From 00e54c13c7c9030c4d5f7151467f2d85a3730e29 Mon Sep 17 00:00:00 2001 From: Arthur Hanson Rasmusson Date: Sun, 13 Sep 2026 18:36:21 -0400 Subject: Initial commit: Open-IOV vGPU-IO complete stack - Firmware decompilation: GSP 570.144W (28.5MB ELF, RV64IMAC), 132 decompiled C files - Kernel modules: nvidia.ko (34MB, OpenRM), open-iov-vfio.ko (2.8MB, VFIO mdev), gsp-vgpu.ko (1.8MB, guest driver) - Userspace: libiov.so/libvgpu.so (76KB), example_vgpu (28KB), rpc_emulator.c - PCI config space emulation (256B with PM, MSI, MSI-X, PCIe caps) - 12 RPC types fully mapped from firmware decompilation - BAR trap, WPR, scheduling, notification, migration emulation - Helper scripts: load_vgpu_stack, create_mdev, launch_qemu_vgpu, test_vgpu_stack, setup_guest_driver, unload_vgpu_stack - Architecture documentation - Wiki: 10 technical documents - Git LFS for large binaries (.ko, .bin, .iso, .img, .o, ghidra repos) - nvidia-open-gpu-kernel-modules as submodule --- userspace/LICENSE | 339 + userspace/Makefile | 25 + userspace/configs/generic.toml | 45 + userspace/examples/Makefile | 27 + userspace/examples/example_vgpu.c | 173 + userspace/extern/inc/cargs.h | 185 + userspace/extern/inc/toml.h | 175 + userspace/extern/src/cargs.c | 460 + userspace/extern/src/toml.c | 2379 ++++ userspace/include/libvgpu.h | 238 + userspace/lib/Makefile | 89 + userspace/lib/libiov.pc.in | 10 + userspace/lib/libiov.so.1 | 1 + userspace/lib/libiov.so.1.0.0 | 1 + userspace/lib/libvgpu.c | 894 ++ userspace/lib/libvgpu.pc.in | 10 + userspace/lib/libvgpu.so | 1 + userspace/lib/libvgpu.so.1 | 1 + userspace/lib/libvgpu.so.1.0.0 | 1 + userspace/lib/rpc_emulator.c | 528 + userspace/lib/rpc_emulator.h | 53 + .../nv525/nvalloc/common/inc/dev_ctrl_defines.h | 86 + .../sdks/nv525/nvalloc/common/inc/flcnifcmn.h | 149 + .../sdks/nv525/nvalloc/common/inc/flcnretval.h | 292 + .../nvalloc/common/inc/fsp/fsp_emem_channels.h | 47 + .../nv525/nvalloc/common/inc/fsp/fsp_mctp_format.h | 55 + .../nv525/nvalloc/common/inc/fsp/fsp_nvdm_format.h | 43 + .../common/inc/fsp/nvdm_payload_cmd_response.h | 44 + .../sdks/nv525/nvalloc/common/inc/gsp/gsp_error.h | 35 + .../nv525/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h | 155 + .../sdks/nv525/nvalloc/common/inc/gsp/gspifpub.h | 96 + .../sdks/nv525/nvalloc/common/inc/inforom/ifrdem.h | 43 + .../sdks/nv525/nvalloc/common/inc/inforom/ifrecc.h | 119 + .../nv525/nvalloc/common/inc/inforom/ifrstruct.h | 83 + .../sdks/nv525/nvalloc/common/inc/inforom/omsdef.h | 84 + .../sdks/nv525/nvalloc/common/inc/inforom/types.h | 79 + .../common/inc/nv-firmware-chip-family-select.h | 62 + .../sdks/nv525/nvalloc/common/inc/nv-firmware.h | 132 + userspace/sdks/nv525/nvalloc/common/inc/nvcst.h | 353 + userspace/sdks/nv525/nvalloc/common/inc/nvdevid.h | 697 ++ userspace/sdks/nv525/nvalloc/common/inc/nvpcie.h | 499 + .../sdks/nv525/nvalloc/common/inc/nvrangetypes.h | 162 + .../sdks/nv525/nvalloc/common/inc/oob/smbpbi.h | 2684 +++++ .../nv525/nvalloc/common/inc/oob/smbpbi_impl.h | 45 + .../nv525/nvalloc/common/inc/oob/smbpbi_priv.h | 79 + .../sdks/nv525/nvalloc/common/inc/rmRiscvUcode.h | 89 + userspace/sdks/nv525/nvalloc/common/inc/rmflcnbl.h | 147 + userspace/sdks/nv525/nvalloc/common/inc/rmgspseq.h | 202 + userspace/sdks/nv525/nvalloc/common/inc/rmifrif.h | 124 + userspace/sdks/nv525/nvalloc/common/inc/rmlsfm.h | 525 + .../sdks/nv525/nvalloc/common/inc/rmpbicmdif.h | 140 + .../sdks/nv525/nvalloc/unix/include/efi-console.h | 65 + .../sdks/nv525/nvalloc/unix/include/nv-caps.h | 94 + .../sdks/nv525/nvalloc/unix/include/nv-gpu-info.h | 44 + .../nv525/nvalloc/unix/include/nv-ioctl-numbers.h | 43 + .../sdks/nv525/nvalloc/unix/include/nv-ioctl.h | 145 + .../nvalloc/unix/include/nv-kernel-rmapi-ops.h | 61 + .../sdks/nv525/nvalloc/unix/include/nv-nb-regs.h | 65 + .../sdks/nv525/nvalloc/unix/include/nv-priv.h | 377 + userspace/sdks/nv525/nvalloc/unix/include/nv-reg.h | 927 ++ .../unix/include/nv-unix-nvos-params-wrappers.h | 49 + userspace/sdks/nv525/nvalloc/unix/include/nv.h | 1058 ++ .../sdks/nv525/nvalloc/unix/include/nv_escape.h | 54 + .../sdks/nv525/nvalloc/unix/include/os-interface.h | 250 + .../sdks/nv525/nvalloc/unix/include/os_custom.h | 61 + userspace/sdks/nv525/nvalloc/unix/include/osapi.h | 192 + .../sdks/nv525/nvalloc/unix/include/osfuncs.h | 55 + .../nv525/nvalloc/unix/include/rmobjexportimport.h | 42 + .../sdks/nv525/nvalloc/unix/src/asm/x86/nv_cpuid.c | 52 + .../sdks/nv525/nvalloc/unix/src/asm/x86/nv_rdcr.c | 44 + userspace/sdks/nv525/nvalloc/unix/src/escape.c | 938 ++ .../sdks/nv525/nvalloc/unix/src/exports-stubs.c | 235 + userspace/sdks/nv525/nvalloc/unix/src/gcc_helper.c | 35 + .../sdks/nv525/nvalloc/unix/src/os-hypervisor.c | 1023 ++ userspace/sdks/nv525/nvalloc/unix/src/os.c | 5238 +++++++++ userspace/sdks/nv525/nvalloc/unix/src/osapi.c | 5333 +++++++++ userspace/sdks/nv525/nvalloc/unix/src/osinit.c | 2202 ++++ userspace/sdks/nv525/nvalloc/unix/src/osmemdesc.c | 1030 ++ userspace/sdks/nv525/nvalloc/unix/src/osnvlink.c | 698 ++ userspace/sdks/nv525/nvalloc/unix/src/osunix.c | 88 + userspace/sdks/nv525/nvalloc/unix/src/registry.c | 705 ++ userspace/sdks/nv525/nvalloc/unix/src/rm-gpu-ops.c | 813 ++ .../nv525/nvalloc/unix/src/rmobjexportimport.c | 634 + .../nvalloc/unix/src/subdevice_ctrl_os_unix.c | 100 + .../sdks/nv525/nvalloc/unix/src/unix_console.c | 118 + userspace/sdks/nv525/nvalloc/unix/src/unix_intr.c | 700 ++ userspace/sdks/nv525/nvidia/inc/Nvcm.h | 71 + .../sdks/nv525/nvidia/inc/alloc/alloc_channel.h | 319 + userspace/sdks/nv525/nvidia/inc/class/cl0000.h | 52 + .../nv525/nvidia/inc/class/cl0000_notification.h | 68 + userspace/sdks/nv525/nvidia/inc/class/cl0001.h | 37 + userspace/sdks/nv525/nvidia/inc/class/cl0002.h | 51 + userspace/sdks/nv525/nvidia/inc/class/cl0004.h | 50 + userspace/sdks/nv525/nvidia/inc/class/cl0005.h | 58 + .../nv525/nvidia/inc/class/cl0005_notification.h | 51 + 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+ userspace/sdks/nv525/nvidia/inc/class/cla16f.h | 254 + userspace/sdks/nv525/nvidia/inc/class/cla16fsw.h | 41 + userspace/sdks/nv525/nvidia/inc/class/cla197.h | 3826 ++++++ userspace/sdks/nv525/nvidia/inc/class/cla1c0.h | 669 ++ userspace/sdks/nv525/nvidia/inc/class/cla26f.h | 254 + userspace/sdks/nv525/nvidia/inc/class/clb069.h | 64 + userspace/sdks/nv525/nvidia/inc/class/clb069sw.h | 38 + userspace/sdks/nv525/nvidia/inc/class/clb06f.h | 260 + userspace/sdks/nv525/nvidia/inc/class/clb06fsw.h | 42 + userspace/sdks/nv525/nvidia/inc/class/clb097.h | 3966 +++++++ userspace/sdks/nv525/nvidia/inc/class/clb097tex.h | 2050 ++++ userspace/sdks/nv525/nvidia/inc/class/clb0b0.h | 39 + userspace/sdks/nv525/nvidia/inc/class/clb0b5.h | 261 + userspace/sdks/nv525/nvidia/inc/class/clb0b5sw.h | 54 + userspace/sdks/nv525/nvidia/inc/class/clb0c0.h | 720 ++ userspace/sdks/nv525/nvidia/inc/class/clb0cc.h | 46 + userspace/sdks/nv525/nvidia/inc/class/clb197.h | 4160 +++++++ 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40 + userspace/sdks/nv525/nvidia/inc/class/clc1b5.h | 273 + userspace/sdks/nv525/nvidia/inc/class/clc1b5sw.h | 54 + userspace/sdks/nv525/nvidia/inc/class/clc1b7.h | 40 + userspace/sdks/nv525/nvidia/inc/class/clc1c0.h | 795 ++ userspace/sdks/nv525/nvidia/inc/class/clc2b0.h | 39 + userspace/sdks/nv525/nvidia/inc/class/clc2b7.h | 40 + userspace/sdks/nv525/nvidia/inc/class/clc361.h | 35 + userspace/sdks/nv525/nvidia/inc/class/clc365.h | 88 + userspace/sdks/nv525/nvidia/inc/class/clc369.h | 77 + userspace/sdks/nv525/nvidia/inc/class/clc36f.h | 366 + userspace/sdks/nv525/nvidia/inc/class/clc36fsw.h | 44 + userspace/sdks/nv525/nvidia/inc/class/clc370.h | 43 + .../nv525/nvidia/inc/class/clc370_notification.h | 45 + userspace/sdks/nv525/nvidia/inc/class/clc371.h | 41 + userspace/sdks/nv525/nvidia/inc/class/clc372sw.h | 36 + userspace/sdks/nv525/nvidia/inc/class/clc373.h | 350 + userspace/sdks/nv525/nvidia/inc/class/clc37a.h | 213 + userspace/sdks/nv525/nvidia/inc/class/clc37b.h | 67 + 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userspace/sdks/nv525/nvidia/inc/class/clc56f.h | 367 + userspace/sdks/nv525/nvidia/inc/class/clc56fsw.h | 44 + userspace/sdks/nv525/nvidia/inc/class/clc570.h | 41 + userspace/sdks/nv525/nvidia/inc/class/clc572.h | 39 + userspace/sdks/nv525/nvidia/inc/class/clc573.h | 598 + userspace/sdks/nv525/nvidia/inc/class/clc574.h | 41 + userspace/sdks/nv525/nvidia/inc/class/clc57a.h | 179 + userspace/sdks/nv525/nvidia/inc/class/clc57b.h | 64 + userspace/sdks/nv525/nvidia/inc/class/clc57d.h | 1277 ++ userspace/sdks/nv525/nvidia/inc/class/clc57e.h | 657 ++ userspace/sdks/nv525/nvidia/inc/class/clc57esw.h | 45 + userspace/sdks/nv525/nvidia/inc/class/clc58b.h | 50 + userspace/sdks/nv525/nvidia/inc/class/clc597.h | 4352 +++++++ userspace/sdks/nv525/nvidia/inc/class/clc5b5.h | 282 + userspace/sdks/nv525/nvidia/inc/class/clc5b5sw.h | 54 + userspace/sdks/nv525/nvidia/inc/class/clc5c0.h | 732 ++ userspace/sdks/nv525/nvidia/inc/class/clc637.h | 62 + userspace/sdks/nv525/nvidia/inc/class/clc638.h | 50 + userspace/sdks/nv525/nvidia/inc/class/clc639.h | 48 + userspace/sdks/nv525/nvidia/inc/class/clc640.h | 48 + userspace/sdks/nv525/nvidia/inc/class/clc661.h | 27 + userspace/sdks/nv525/nvidia/inc/class/clc670.h | 41 + userspace/sdks/nv525/nvidia/inc/class/clc671.h | 47 + userspace/sdks/nv525/nvidia/inc/class/clc673.h | 399 + userspace/sdks/nv525/nvidia/inc/class/clc67a.h | 181 + userspace/sdks/nv525/nvidia/inc/class/clc67b.h | 66 + userspace/sdks/nv525/nvidia/inc/class/clc67d.h | 1339 +++ userspace/sdks/nv525/nvidia/inc/class/clc67e.h | 700 ++ userspace/sdks/nv525/nvidia/inc/class/clc697.h | 4352 +++++++ userspace/sdks/nv525/nvidia/inc/class/clc6b0.h | 40 + userspace/sdks/nv525/nvidia/inc/class/clc6b5.h | 282 + userspace/sdks/nv525/nvidia/inc/class/clc6b5sw.h | 54 + userspace/sdks/nv525/nvidia/inc/class/clc6c0.h | 697 ++ userspace/sdks/nv525/nvidia/inc/class/clc6fa.h | 29 + userspace/sdks/nv525/nvidia/inc/class/clc770.h | 35 + userspace/sdks/nv525/nvidia/inc/class/clc771.h | 155 + userspace/sdks/nv525/nvidia/inc/class/clc773.h | 29 + userspace/sdks/nv525/nvidia/inc/class/clc77d.h | 33 + userspace/sdks/nv525/nvidia/inc/class/clc77f.h | 34 + userspace/sdks/nv525/nvidia/inc/class/clc797.h | 4481 +++++++ userspace/sdks/nv525/nvidia/inc/class/clc7b0.h | 40 + userspace/sdks/nv525/nvidia/inc/class/clc7b5.h | 304 + userspace/sdks/nv525/nvidia/inc/class/clc7b7.h | 39 + userspace/sdks/nv525/nvidia/inc/class/clc7c0.h | 848 ++ userspace/sdks/nv525/nvidia/inc/class/clc7fa.h | 40 + userspace/sdks/nv525/nvidia/inc/class/clc86f.h | 84 + userspace/sdks/nv525/nvidia/inc/class/clc86fsw.h | 44 + userspace/sdks/nv525/nvidia/inc/class/clc8b5.h | 77 + userspace/sdks/nv525/nvidia/inc/class/clc997.h | 4481 +++++++ userspace/sdks/nv525/nvidia/inc/class/clc9b0.h | 29 + userspace/sdks/nv525/nvidia/inc/class/clc9b7.h | 29 + userspace/sdks/nv525/nvidia/inc/class/clc9c0.h | 29 + userspace/sdks/nv525/nvidia/inc/class/clc9d1.h | 31 + userspace/sdks/nv525/nvidia/inc/class/clc9fa.h | 32 + userspace/sdks/nv525/nvidia/inc/class/clcb97.h | 4480 +++++++ userspace/sdks/nv525/nvidia/inc/class/clcb97tex.h | 2437 ++++ userspace/sdks/nv525/nvidia/inc/class/clcbc0.h | 27 + userspace/sdks/nv525/nvidia/inc/class/clcbca.h | 39 + userspace/sdks/nv525/nvidia/inc/class/cld0b7.h | 40 + userspace/sdks/nv525/nvidia/inc/cpuopsys.h | 422 + .../nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h | 68 + .../nvidia/inc/ctrl/ctrl0000/ctrl0000client.h | 183 + .../nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h | 326 + .../nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h | 113 + .../nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h | 873 ++ .../nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h | 255 + .../nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h | 101 + .../nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h | 636 + .../nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h | 98 + .../inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h | 112 + .../nvidia/inc/ctrl/ctrl0000/ctrl0000system.h | 2915 +++++ .../nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h | 435 + .../nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h | 78 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0002.h | 178 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0004.h | 93 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl000f.h | 85 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0020.h | 80 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl003e.h | 191 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0041.h | 450 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073.h | 45 + .../nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h | 60 + .../nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h | 1269 ++ .../nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h | 2767 +++++ .../nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073dpu.h | 32 + .../nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h | 32 + .../nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h | 47 + .../nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h | 32 + .../nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h | 1909 +++ .../nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h | 166 + .../nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073svp.h | 32 + .../nvidia/inc/ctrl/ctrl0073/ctrl0073system.h | 1480 +++ userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080.h | 51 + .../nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h | 73 + .../nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h | 138 + .../nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h | 112 + .../nvidia/inc/ctrl/ctrl0080/ctrl0080cipher.h | 32 + .../nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080clk.h | 32 + .../nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h | 908 ++ .../nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h | 232 + .../nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h | 642 + .../nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h | 585 + .../nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h | 275 + .../nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h | 112 + .../nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h | 103 + .../nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h | 73 + .../nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h | 75 + .../nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h | 48 + .../nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h | 57 + .../nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h | 93 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0090.h | 130 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl00f8.h | 218 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl00fd.h | 160 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl00fe.h | 64 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080.h | 84 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080acr.h | 32 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h | 112 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h | 477 + .../nvidia/inc/ctrl/ctrl2080/ctrl2080boardobj.h | 35 + .../inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h | 34 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h | 1588 +++ .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h | 329 + .../nvidia/inc/ctrl/ctrl2080/ctrl2080cipher.h | 32 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h | 41 + .../nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h | 36 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h | 183 + .../nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h | 105 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h | 63 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h | 372 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080fan.h | 32 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h | 2906 +++++ .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h | 791 ++ .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h | 208 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h | 444 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h | 34 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h | 36 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h | 4115 +++++++ .../nvidia/inc/ctrl/ctrl2080/ctrl2080gpumon.h | 96 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h | 1820 +++ .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h | 263 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h | 82 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h | 55 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h | 365 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h | 31 + .../nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h | 3176 +++++ .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h | 100 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h | 325 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h | 338 + .../nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h | 2950 +++++ .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h | 578 + .../nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h | 33 + .../inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h | 32 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h | 67 + .../nvidia/inc/ctrl/ctrl2080/ctrl2080pmumon.h | 34 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080power.h | 32 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h | 368 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080spi.h | 32 + .../nvidia/inc/ctrl/ctrl2080/ctrl2080thermal.h | 30 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h | 233 + .../nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h | 32 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h | 190 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h | 42 + .../inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h | 407 + .../nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h | 38 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f.h | 51 + .../nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fbase.h | 71 + .../nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h | 194 + .../nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fbus.h | 113 + .../nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fclk.h | 33 + .../nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fdma.h | 92 + .../nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fevent.h | 93 + .../nv525/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h | 611 + .../nv525/nvidia/inc/ctrl/ctrl208f/ctrl208ffbio.h | 249 + .../nv525/nvidia/inc/ctrl/ctrl208f/ctrl208ffifo.h | 159 + .../nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h | 161 + .../nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fgr.h | 109 + .../nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h | 128 + .../nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fpmgr.h | 32 + .../nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fpower.h | 32 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl30f1.h | 1493 +++ userspace/sdks/nv525/nvidia/inc/ctrl/ctrl402c.h | 971 ++ userspace/sdks/nv525/nvidia/inc/ctrl/ctrl503c.h | 200 + .../nv525/nvidia/inc/ctrl/ctrl503c/ctrl503cbase.h | 50 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl506f.h | 96 + .../nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070base.h | 67 + .../nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070chnc.h | 1181 ++ .../nvidia/inc/ctrl/ctrl5070/ctrl5070common.h | 79 + .../nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070event.h | 143 + .../inc/ctrl/ctrl5070/ctrl5070impoverrides.h | 33 + .../nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h | 936 ++ .../nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h | 578 + .../nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070seq.h | 521 + .../nvidia/inc/ctrl/ctrl5070/ctrl5070system.h | 81 + .../nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070verif.h | 32 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5080.h | 212 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl83de.h | 36 + .../nv525/nvidia/inc/ctrl/ctrl83de/ctrl83debase.h | 55 + .../nv525/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h | 1106 ++ userspace/sdks/nv525/nvidia/inc/ctrl/ctrl9010.h | 83 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl9067.h | 150 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl906f.h | 261 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl9072.h | 86 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl9074.h | 148 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl9096.h | 444 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90cc.h | 455 + .../nv525/nvidia/inc/ctrl/ctrl90cc/ctrl90ccbase.h | 54 + .../nv525/nvidia/inc/ctrl/ctrl90cc/ctrl90cchwpm.h | 135 + .../nv525/nvidia/inc/ctrl/ctrl90cc/ctrl90ccpower.h | 403 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90cd.h | 174 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90e6.h | 137 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90ec.h | 124 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90f1.h | 309 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrla06c.h | 421 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrla06f.h | 37 + .../nv525/nvidia/inc/ctrl/ctrla06f/ctrla06fbase.h | 60 + .../nv525/nvidia/inc/ctrl/ctrla06f/ctrla06fevent.h | 92 + .../nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h | 288 + .../nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h | 67 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrla080.h | 658 ++ userspace/sdks/nv525/nvidia/inc/ctrl/ctrla081.h | 716 ++ userspace/sdks/nv525/nvidia/inc/ctrl/ctrla084.h | 302 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrla16f.h | 200 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrla26f.h | 200 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrlb069.h | 180 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrlb06f.h | 527 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrlb0cc.h | 37 + .../nv525/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h | 52 + .../nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h | 79 + .../nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h | 479 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc06f.h | 200 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc365.h | 331 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc369.h | 109 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc36f.h | 275 + .../nv525/nvidia/inc/ctrl/ctrlc370/ctrlc370base.h | 67 + .../nv525/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h | 300 + .../nv525/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h | 46 + .../nv525/nvidia/inc/ctrl/ctrlc370/ctrlc370rg.h | 123 + .../nv525/nvidia/inc/ctrl/ctrlc370/ctrlc370verif.h | 133 + .../nv525/nvidia/inc/ctrl/ctrlc372/ctrlc372base.h | 61 + .../nv525/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h | 721 ++ userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc46f.h | 162 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc56f.h | 166 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc637.h | 392 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc638.h | 91 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc86f.h | 165 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrlcbca.h | 120 + userspace/sdks/nv525/nvidia/inc/ctrl/ctrlxxxx.h | 67 + .../sdks/nv525/nvidia/inc/dpringbuffertypes.h | 59 + userspace/sdks/nv525/nvidia/inc/finn_rm_api.h | 709 ++ userspace/sdks/nv525/nvidia/inc/mmu_fmt_types.h | 151 + userspace/sdks/nv525/nvidia/inc/nv-hypervisor.h | 123 + .../nv525/nvidia/inc/nv-kernel-interface-api.h | 41 + userspace/sdks/nv525/nvidia/inc/nv_stdarg.h | 39 + userspace/sdks/nv525/nvidia/inc/nv_vgpu_types.h | 61 + userspace/sdks/nv525/nvidia/inc/nvcd.h | 159 + userspace/sdks/nv525/nvidia/inc/nvcfg_sdk.h | 29 + userspace/sdks/nv525/nvidia/inc/nvdeprecated.h | 133 + userspace/sdks/nv525/nvidia/inc/nvdisptypes.h | 92 + userspace/sdks/nv525/nvidia/inc/nvdump.h | 163 + userspace/sdks/nv525/nvidia/inc/nverror.h | 224 + userspace/sdks/nv525/nvidia/inc/nvfixedtypes.h | 379 + userspace/sdks/nv525/nvidia/inc/nvgputypes.h | 177 + userspace/sdks/nv525/nvidia/inc/nvi2c.h | 37 + userspace/sdks/nv525/nvidia/inc/nvimpshared.h | 98 + userspace/sdks/nv525/nvidia/inc/nvlimits.h | 52 + userspace/sdks/nv525/nvidia/inc/nvmisc.h | 927 ++ userspace/sdks/nv525/nvidia/inc/nvos.h | 2909 +++++ userspace/sdks/nv525/nvidia/inc/nvsecurityinfo.h | 71 + userspace/sdks/nv525/nvidia/inc/nvstatus.h | 123 + userspace/sdks/nv525/nvidia/inc/nvstatuscodes.h | 163 + userspace/sdks/nv525/nvidia/inc/nvtypes.h | 625 + userspace/sdks/nv525/nvidia/inc/rmcd.h | 393 + userspace/sdks/nv525/nvidia/inc/rs_access.h | 272 + userspace/sdks/nv525/nvml/nvml.h | 9664 +++++++++++++++ .../nv570/inc/alloc/alloc_access_counter_buffer.h | 51 + userspace/sdks/nv570/inc/alloc/alloc_channel.h | 350 + userspace/sdks/nv570/inc/cc_drv.h | 101 + userspace/sdks/nv570/inc/class/cl0000.h | 53 + .../sdks/nv570/inc/class/cl0000_notification.h | 60 + userspace/sdks/nv570/inc/class/cl0001.h | 37 + userspace/sdks/nv570/inc/class/cl0002.h | 51 + userspace/sdks/nv570/inc/class/cl0004.h | 50 + userspace/sdks/nv570/inc/class/cl0005.h | 58 + .../sdks/nv570/inc/class/cl0005_notification.h | 51 + userspace/sdks/nv570/inc/class/cl000f.h | 55 + userspace/sdks/nv570/inc/class/cl0020.h | 31 + userspace/sdks/nv570/inc/class/cl0030.h | 51 + userspace/sdks/nv570/inc/class/cl003e.h | 51 + userspace/sdks/nv570/inc/class/cl003f.h | 58 + userspace/sdks/nv570/inc/class/cl0040.h | 55 + userspace/sdks/nv570/inc/class/cl0041.h | 45 + userspace/sdks/nv570/inc/class/cl0050.h | 81 + userspace/sdks/nv570/inc/class/cl0060.h | 39 + userspace/sdks/nv570/inc/class/cl0070.h | 73 + userspace/sdks/nv570/inc/class/cl0071.h | 38 + userspace/sdks/nv570/inc/class/cl0073.h | 56 + userspace/sdks/nv570/inc/class/cl0076.h | 38 + userspace/sdks/nv570/inc/class/cl007d.h | 64 + userspace/sdks/nv570/inc/class/cl0080.h | 64 + .../sdks/nv570/inc/class/cl0080_notification.h | 45 + userspace/sdks/nv570/inc/class/cl008f.h | 32 + userspace/sdks/nv570/inc/class/cl0090.h | 32 + userspace/sdks/nv570/inc/class/cl0092.h | 72 + userspace/sdks/nv570/inc/class/cl0092_callback.h | 28 + userspace/sdks/nv570/inc/class/cl00b1.h | 28 + userspace/sdks/nv570/inc/class/cl00c1.h | 65 + userspace/sdks/nv570/inc/class/cl00c2.h | 41 + userspace/sdks/nv570/inc/class/cl00c3.h | 43 + userspace/sdks/nv570/inc/class/cl00da.h | 85 + userspace/sdks/nv570/inc/class/cl00db.h | 43 + userspace/sdks/nv570/inc/class/cl00de.h | 511 + userspace/sdks/nv570/inc/class/cl00e0.h | 111 + userspace/sdks/nv570/inc/class/cl00f1.h | 64 + userspace/sdks/nv570/inc/class/cl00f2.h | 38 + userspace/sdks/nv570/inc/class/cl00f8.h | 133 + userspace/sdks/nv570/inc/class/cl00f9.h | 82 + userspace/sdks/nv570/inc/class/cl00fb.h | 71 + userspace/sdks/nv570/inc/class/cl00fc.h | 39 + userspace/sdks/nv570/inc/class/cl00fd.h | 99 + userspace/sdks/nv570/inc/class/cl00fe.h | 53 + userspace/sdks/nv570/inc/class/cl0100.h | 50 + userspace/sdks/nv570/inc/class/cl0101.h | 39 + userspace/sdks/nv570/inc/class/cl2080.h | 46 + .../sdks/nv570/inc/class/cl2080_notification.h | 612 + userspace/sdks/nv570/inc/class/cl2081.h | 40 + userspace/sdks/nv570/inc/class/cl2082.h | 40 + userspace/sdks/nv570/inc/class/cl208f.h | 39 + userspace/sdks/nv570/inc/class/cl30f1.h | 56 + .../sdks/nv570/inc/class/cl30f1_notification.h | 74 + userspace/sdks/nv570/inc/class/cl402c.h | 47 + userspace/sdks/nv570/inc/class/cl503b.h | 81 + userspace/sdks/nv570/inc/class/cl503c.h | 47 + userspace/sdks/nv570/inc/class/cl506f.h | 157 + userspace/sdks/nv570/inc/class/cl5070.h | 44 + .../sdks/nv570/inc/class/cl5070_notification.h | 45 + userspace/sdks/nv570/inc/class/cl5080.h | 46 + .../sdks/nv570/inc/class/cl5080_notification.h | 43 + userspace/sdks/nv570/inc/class/cl50a0.h | 38 + userspace/sdks/nv570/inc/class/cl83de.h | 56 + userspace/sdks/nv570/inc/class/cl844c.h | 47 + userspace/sdks/nv570/inc/class/cl84a0.h | 110 + userspace/sdks/nv570/inc/class/cl84a0_deprecated.h | 90 + userspace/sdks/nv570/inc/class/cl85b5sw.h | 38 + userspace/sdks/nv570/inc/class/cl900e.h | 39 + userspace/sdks/nv570/inc/class/cl9010.h | 45 + userspace/sdks/nv570/inc/class/cl9010_callback.h | 27 + userspace/sdks/nv570/inc/class/cl902d.h | 1092 ++ userspace/sdks/nv570/inc/class/cl9067.h | 39 + userspace/sdks/nv570/inc/class/cl906f.h | 242 + userspace/sdks/nv570/inc/class/cl906fsw.h | 42 + userspace/sdks/nv570/inc/class/cl9072.h | 46 + .../sdks/nv570/inc/class/cl9072_notification.h | 39 + userspace/sdks/nv570/inc/class/cl9074.h | 51 + userspace/sdks/nv570/inc/class/cl9096.h | 40 + userspace/sdks/nv570/inc/class/cl9097.h | 3815 ++++++ userspace/sdks/nv570/inc/class/cl90cc.h | 48 + userspace/sdks/nv570/inc/class/cl90cd.h | 237 + userspace/sdks/nv570/inc/class/cl90cdfecs.h | 112 + userspace/sdks/nv570/inc/class/cl90cdtrace.h | 68 + userspace/sdks/nv570/inc/class/cl90cdtypes.h | 49 + userspace/sdks/nv570/inc/class/cl90cdvideo.h | 129 + userspace/sdks/nv570/inc/class/cl90ce.h | 42 + userspace/sdks/nv570/inc/class/cl90e6.h | 43 + userspace/sdks/nv570/inc/class/cl90e7.h | 38 + userspace/sdks/nv570/inc/class/cl90ec.h | 46 + userspace/sdks/nv570/inc/class/cl90f1.h | 39 + userspace/sdks/nv570/inc/class/cl9170.h | 41 + userspace/sdks/nv570/inc/class/cl9171.h | 317 + userspace/sdks/nv570/inc/class/cl917d.h | 1551 +++ userspace/sdks/nv570/inc/class/cla06c.h | 39 + userspace/sdks/nv570/inc/class/cla06f.h | 240 + userspace/sdks/nv570/inc/class/cla06fsubch.h | 33 + userspace/sdks/nv570/inc/class/cla06fsw.h | 41 + userspace/sdks/nv570/inc/class/cla080.h | 32 + userspace/sdks/nv570/inc/class/cla081.h | 44 + userspace/sdks/nv570/inc/class/cla083.h | 36 + userspace/sdks/nv570/inc/class/cla084.h | 82 + .../sdks/nv570/inc/class/cla084_notification.h | 58 + userspace/sdks/nv570/inc/class/cla097.h | 3817 ++++++ userspace/sdks/nv570/inc/class/cla0b0.h | 39 + userspace/sdks/nv570/inc/class/cla0b5.h | 262 + userspace/sdks/nv570/inc/class/cla0bc.h | 209 + userspace/sdks/nv570/inc/class/cla0bd.h | 81 + userspace/sdks/nv570/inc/class/cla0c0.h | 646 + userspace/sdks/nv570/inc/class/cla0c0qmd.h | 658 ++ userspace/sdks/nv570/inc/class/cla140.h | 29 + userspace/sdks/nv570/inc/class/cla16f.h | 254 + userspace/sdks/nv570/inc/class/cla16fsw.h | 41 + userspace/sdks/nv570/inc/class/cla197.h | 3826 ++++++ userspace/sdks/nv570/inc/class/cla1c0.h | 669 ++ userspace/sdks/nv570/inc/class/clb069.h | 64 + userspace/sdks/nv570/inc/class/clb069sw.h | 38 + userspace/sdks/nv570/inc/class/clb06f.h | 260 + userspace/sdks/nv570/inc/class/clb06fsw.h | 42 + userspace/sdks/nv570/inc/class/clb097.h | 3966 +++++++ userspace/sdks/nv570/inc/class/clb0b0.h | 39 + userspace/sdks/nv570/inc/class/clb0b5.h | 261 + userspace/sdks/nv570/inc/class/clb0b5sw.h | 54 + userspace/sdks/nv570/inc/class/clb0c0.h | 720 ++ userspace/sdks/nv570/inc/class/clb0cc.h | 46 + userspace/sdks/nv570/inc/class/clb0cd.h | 49 + userspace/sdks/nv570/inc/class/clb0ce.h | 53 + userspace/sdks/nv570/inc/class/clb197.h | 4160 +++++++ userspace/sdks/nv570/inc/class/clb1c0.h | 750 ++ userspace/sdks/nv570/inc/class/clb1cc.h | 50 + userspace/sdks/nv570/inc/class/clb2cc.h | 60 + userspace/sdks/nv570/inc/class/clb4b7.h | 40 + userspace/sdks/nv570/inc/class/clb6b0.h | 39 + userspace/sdks/nv570/inc/class/clb8b0.h | 27 + userspace/sdks/nv570/inc/class/clb8d1.h | 27 + userspace/sdks/nv570/inc/class/clb8fa.h | 29 + userspace/sdks/nv570/inc/class/clc06f.h | 312 + userspace/sdks/nv570/inc/class/clc06fsw.h | 44 + userspace/sdks/nv570/inc/class/clc076.h | 82 + userspace/sdks/nv570/inc/class/clc097.h | 4191 +++++++ userspace/sdks/nv570/inc/class/clc0b5.h | 261 + userspace/sdks/nv570/inc/class/clc0b5sw.h | 54 + userspace/sdks/nv570/inc/class/clc0b7.h | 40 + userspace/sdks/nv570/inc/class/clc0c0.h | 777 ++ userspace/sdks/nv570/inc/class/clc197.h | 4242 +++++++ userspace/sdks/nv570/inc/class/clc1b0.h | 40 + userspace/sdks/nv570/inc/class/clc1b5.h | 273 + userspace/sdks/nv570/inc/class/clc1b5sw.h | 54 + userspace/sdks/nv570/inc/class/clc1b7.h | 40 + userspace/sdks/nv570/inc/class/clc1c0.h | 795 ++ userspace/sdks/nv570/inc/class/clc2b0.h | 39 + userspace/sdks/nv570/inc/class/clc2b7.h | 40 + userspace/sdks/nv570/inc/class/clc361.h | 35 + userspace/sdks/nv570/inc/class/clc365.h | 88 + userspace/sdks/nv570/inc/class/clc369.h | 77 + userspace/sdks/nv570/inc/class/clc36f.h | 366 + userspace/sdks/nv570/inc/class/clc36fsw.h | 44 + userspace/sdks/nv570/inc/class/clc370.h | 43 + .../sdks/nv570/inc/class/clc370_notification.h | 44 + userspace/sdks/nv570/inc/class/clc371.h | 109 + userspace/sdks/nv570/inc/class/clc372sw.h | 36 + userspace/sdks/nv570/inc/class/clc373.h | 350 + userspace/sdks/nv570/inc/class/clc37b.h | 68 + userspace/sdks/nv570/inc/class/clc37d.h | 953 ++ userspace/sdks/nv570/inc/class/clc37dcrcnotif.h | 50 + userspace/sdks/nv570/inc/class/clc37dswspare.h | 36 + userspace/sdks/nv570/inc/class/clc37e.h | 498 + userspace/sdks/nv570/inc/class/clc397.h | 4219 +++++++ userspace/sdks/nv570/inc/class/clc3b0.h | 39 + userspace/sdks/nv570/inc/class/clc3b5.h | 278 + userspace/sdks/nv570/inc/class/clc3b5sw.h | 54 + userspace/sdks/nv570/inc/class/clc3b7.h | 40 + userspace/sdks/nv570/inc/class/clc3c0.h | 703 ++ userspace/sdks/nv570/inc/class/clc461.h | 29 + userspace/sdks/nv570/inc/class/clc46f.h | 365 + userspace/sdks/nv570/inc/class/clc46fsw.h | 44 + userspace/sdks/nv570/inc/class/clc4b0.h | 40 + userspace/sdks/nv570/inc/class/clc4b7.h | 40 + userspace/sdks/nv570/inc/class/clc4c0.h | 34 + userspace/sdks/nv570/inc/class/clc4d1.h | 40 + userspace/sdks/nv570/inc/class/clc561.h | 29 + userspace/sdks/nv570/inc/class/clc56f.h | 367 + userspace/sdks/nv570/inc/class/clc56fsw.h | 44 + userspace/sdks/nv570/inc/class/clc570.h | 41 + userspace/sdks/nv570/inc/class/clc572.h | 39 + userspace/sdks/nv570/inc/class/clc573.h | 606 + userspace/sdks/nv570/inc/class/clc574.h | 41 + userspace/sdks/nv570/inc/class/clc57a.h | 213 + userspace/sdks/nv570/inc/class/clc57b.h | 67 + userspace/sdks/nv570/inc/class/clc57d.h | 1277 ++ userspace/sdks/nv570/inc/class/clc57e.h | 657 ++ userspace/sdks/nv570/inc/class/clc57esw.h | 45 + userspace/sdks/nv570/inc/class/clc58b.h | 50 + userspace/sdks/nv570/inc/class/clc597.h | 4352 +++++++ userspace/sdks/nv570/inc/class/clc597tex.h | 1454 +++ userspace/sdks/nv570/inc/class/clc5b5.h | 282 + userspace/sdks/nv570/inc/class/clc5b5sw.h | 54 + userspace/sdks/nv570/inc/class/clc5c0.h | 732 ++ userspace/sdks/nv570/inc/class/clc637.h | 62 + userspace/sdks/nv570/inc/class/clc638.h | 50 + userspace/sdks/nv570/inc/class/clc639.h | 48 + userspace/sdks/nv570/inc/class/clc640.h | 48 + userspace/sdks/nv570/inc/class/clc661.h | 27 + userspace/sdks/nv570/inc/class/clc670.h | 41 + userspace/sdks/nv570/inc/class/clc671.h | 124 + userspace/sdks/nv570/inc/class/clc673.h | 505 + userspace/sdks/nv570/inc/class/clc67a.h | 213 + userspace/sdks/nv570/inc/class/clc67b.h | 67 + userspace/sdks/nv570/inc/class/clc67d.h | 1337 +++ userspace/sdks/nv570/inc/class/clc67e.h | 698 ++ userspace/sdks/nv570/inc/class/clc697.h | 4352 +++++++ userspace/sdks/nv570/inc/class/clc6b0.h | 40 + userspace/sdks/nv570/inc/class/clc6b5.h | 282 + userspace/sdks/nv570/inc/class/clc6b5sw.h | 54 + userspace/sdks/nv570/inc/class/clc6c0.h | 697 ++ userspace/sdks/nv570/inc/class/clc6fa.h | 29 + userspace/sdks/nv570/inc/class/clc761.h | 30 + userspace/sdks/nv570/inc/class/clc763.h | 29 + userspace/sdks/nv570/inc/class/clc770.h | 35 + userspace/sdks/nv570/inc/class/clc771.h | 257 + userspace/sdks/nv570/inc/class/clc773.h | 667 ++ userspace/sdks/nv570/inc/class/clc77d.h | 1372 +++ userspace/sdks/nv570/inc/class/clc77f.h | 34 + userspace/sdks/nv570/inc/class/clc797.h | 4481 +++++++ userspace/sdks/nv570/inc/class/clc7b0.h | 40 + userspace/sdks/nv570/inc/class/clc7b5.h | 304 + userspace/sdks/nv570/inc/class/clc7b7.h | 39 + userspace/sdks/nv570/inc/class/clc7c0.h | 848 ++ userspace/sdks/nv570/inc/class/clc7fa.h | 40 + userspace/sdks/nv570/inc/class/clc863.h | 31 + userspace/sdks/nv570/inc/class/clc86f.h | 191 + userspace/sdks/nv570/inc/class/clc86fsw.h | 45 + userspace/sdks/nv570/inc/class/clc870.h | 41 + userspace/sdks/nv570/inc/class/clc871.h | 380 + userspace/sdks/nv570/inc/class/clc873.h | 399 + userspace/sdks/nv570/inc/class/clc87a.h | 180 + userspace/sdks/nv570/inc/class/clc87b.h | 63 + userspace/sdks/nv570/inc/class/clc87d.h | 1341 +++ userspace/sdks/nv570/inc/class/clc87e.h | 697 ++ userspace/sdks/nv570/inc/class/clc8b5.h | 137 + userspace/sdks/nv570/inc/class/clc96f.h | 113 + userspace/sdks/nv570/inc/class/clc96fsw.h | 45 + userspace/sdks/nv570/inc/class/clc970.h | 41 + userspace/sdks/nv570/inc/class/clc971.h | 329 + userspace/sdks/nv570/inc/class/clc973.h | 379 + userspace/sdks/nv570/inc/class/clc97a.h | 168 + userspace/sdks/nv570/inc/class/clc97b.h | 64 + userspace/sdks/nv570/inc/class/clc97d.h | 1377 +++ userspace/sdks/nv570/inc/class/clc97dswspare.h | 56 + userspace/sdks/nv570/inc/class/clc97e.h | 751 ++ userspace/sdks/nv570/inc/class/clc997.h | 4481 +++++++ userspace/sdks/nv570/inc/class/clc9b0.h | 29 + userspace/sdks/nv570/inc/class/clc9b5.h | 29 + userspace/sdks/nv570/inc/class/clc9b7.h | 29 + userspace/sdks/nv570/inc/class/clc9c0.h | 29 + userspace/sdks/nv570/inc/class/clc9d1.h | 31 + userspace/sdks/nv570/inc/class/clc9fa.h | 32 + userspace/sdks/nv570/inc/class/clca6f.h | 74 + userspace/sdks/nv570/inc/class/clca6fsw.h | 45 + userspace/sdks/nv570/inc/class/clca70.h | 41 + userspace/sdks/nv570/inc/class/clca71.h | 186 + userspace/sdks/nv570/inc/class/clca73.h | 915 ++ userspace/sdks/nv570/inc/class/clca7a.h | 216 + userspace/sdks/nv570/inc/class/clca7b.h | 70 + userspace/sdks/nv570/inc/class/clca7d.h | 2007 ++++ userspace/sdks/nv570/inc/class/clca7e.h | 906 ++ userspace/sdks/nv570/inc/class/clcab5.h | 44 + userspace/sdks/nv570/inc/class/clcb33.h | 40 + userspace/sdks/nv570/inc/class/clcb70.h | 41 + userspace/sdks/nv570/inc/class/clcb71.h | 186 + userspace/sdks/nv570/inc/class/clcb73.h | 915 ++ userspace/sdks/nv570/inc/class/clcb7a.h | 216 + userspace/sdks/nv570/inc/class/clcb7b.h | 70 + userspace/sdks/nv570/inc/class/clcb7d.h | 2007 ++++ userspace/sdks/nv570/inc/class/clcb7e.h | 906 ++ userspace/sdks/nv570/inc/class/clcb97.h | 4480 +++++++ userspace/sdks/nv570/inc/class/clcb97tex.h | 2437 ++++ userspace/sdks/nv570/inc/class/clcba2.h | 159 + userspace/sdks/nv570/inc/class/clcbc0.h | 27 + userspace/sdks/nv570/inc/class/clcbca.h | 39 + userspace/sdks/nv570/inc/class/clcc70.h | 41 + userspace/sdks/nv570/inc/class/clcc71.h | 186 + userspace/sdks/nv570/inc/class/clcc73.h | 915 ++ userspace/sdks/nv570/inc/class/clcc7a.h | 216 + userspace/sdks/nv570/inc/class/clcc7b.h | 70 + userspace/sdks/nv570/inc/class/clcc7d.h | 2007 ++++ userspace/sdks/nv570/inc/class/clcc7e.h | 917 ++ userspace/sdks/nv570/inc/class/clcd40.h | 29 + userspace/sdks/nv570/inc/class/clcd97.h | 29 + userspace/sdks/nv570/inc/class/clcdb0.h | 29 + userspace/sdks/nv570/inc/class/clcdc0.h | 777 ++ userspace/sdks/nv570/inc/class/clcdcd.h | 47 + userspace/sdks/nv570/inc/class/clcdd1.h | 29 + userspace/sdks/nv570/inc/class/clcdfa.h | 29 + userspace/sdks/nv570/inc/class/clce97.h | 30 + userspace/sdks/nv570/inc/class/clceb0.h | 30 + userspace/sdks/nv570/inc/class/clceb7.h | 30 + userspace/sdks/nv570/inc/class/clcec0.h | 30 + userspace/sdks/nv570/inc/class/clced0.h | 30 + userspace/sdks/nv570/inc/class/clcefa.h | 30 + userspace/sdks/nv570/inc/class/clcfb0.h | 30 + userspace/sdks/nv570/inc/class/clcfb7.h | 30 + userspace/sdks/nv570/inc/class/clcfd1.h | 30 + userspace/sdks/nv570/inc/class/clcffa.h | 30 + userspace/sdks/nv570/inc/class/cld0b7.h | 40 + userspace/sdks/nv570/inc/class/cld1b0.h | 29 + userspace/sdks/nv570/inc/class/cld1b7.h | 26 + userspace/sdks/nv570/inc/class/cld1fa.h | 26 + userspace/sdks/nv570/inc/class/cld2b0.h | 29 + userspace/sdks/nv570/inc/class/cld2d1.h | 30 + userspace/sdks/nv570/inc/class/cld2fa.h | 28 + userspace/sdks/nv570/inc/class/cld5b7.h | 30 + userspace/sdks/nv570/inc/cpuopsys.h | 421 + .../sdks/nv570/inc/ctrl/ctrl0000/ctrl0000base.h | 68 + .../sdks/nv570/inc/ctrl/ctrl0000/ctrl0000client.h | 208 + .../sdks/nv570/inc/ctrl/ctrl0000/ctrl0000diag.h | 324 + .../sdks/nv570/inc/ctrl/ctrl0000/ctrl0000event.h | 145 + .../sdks/nv570/inc/ctrl/ctrl0000/ctrl0000gpu.h | 1122 ++ .../sdks/nv570/inc/ctrl/ctrl0000/ctrl0000gpuacct.h | 319 + .../sdks/nv570/inc/ctrl/ctrl0000/ctrl0000gsync.h | 101 + .../sdks/nv570/inc/ctrl/ctrl0000/ctrl0000nvd.h | 637 + .../sdks/nv570/inc/ctrl/ctrl0000/ctrl0000proc.h | 98 + .../nv570/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h | 112 + .../sdks/nv570/inc/ctrl/ctrl0000/ctrl0000system.h | 3239 +++++ .../sdks/nv570/inc/ctrl/ctrl0000/ctrl0000unix.h | 468 + .../sdks/nv570/inc/ctrl/ctrl0000/ctrl0000vgpu.h | 224 + userspace/sdks/nv570/inc/ctrl/ctrl0002.h | 178 + userspace/sdks/nv570/inc/ctrl/ctrl0004.h | 93 + userspace/sdks/nv570/inc/ctrl/ctrl000f.h | 85 + userspace/sdks/nv570/inc/ctrl/ctrl0020.h | 80 + userspace/sdks/nv570/inc/ctrl/ctrl003e.h | 136 + userspace/sdks/nv570/inc/ctrl/ctrl0041.h | 494 + userspace/sdks/nv570/inc/ctrl/ctrl0050.h | 208 + userspace/sdks/nv570/inc/ctrl/ctrl0073.h | 46 + .../sdks/nv570/inc/ctrl/ctrl0073/ctrl0073base.h | 61 + .../sdks/nv570/inc/ctrl/ctrl0073/ctrl0073common.h | 119 + .../sdks/nv570/inc/ctrl/ctrl0073/ctrl0073dfp.h | 1884 +++ .../sdks/nv570/inc/ctrl/ctrl0073/ctrl0073dp.h | 3731 ++++++ .../sdks/nv570/inc/ctrl/ctrl0073/ctrl0073dpu.h | 32 + .../sdks/nv570/inc/ctrl/ctrl0073/ctrl0073event.h | 112 + .../nv570/inc/ctrl/ctrl0073/ctrl0073internal.h | 53 + .../sdks/nv570/inc/ctrl/ctrl0073/ctrl0073psr.h | 70 + .../nv570/inc/ctrl/ctrl0073/ctrl0073specific.h | 3184 +++++ .../sdks/nv570/inc/ctrl/ctrl0073/ctrl0073stereo.h | 201 + .../sdks/nv570/inc/ctrl/ctrl0073/ctrl0073svp.h | 32 + .../sdks/nv570/inc/ctrl/ctrl0073/ctrl0073system.h | 2697 +++++ userspace/sdks/nv570/inc/ctrl/ctrl0076.h | 41 + userspace/sdks/nv570/inc/ctrl/ctrl0080.h | 49 + .../sdks/nv570/inc/ctrl/ctrl0080/ctrl0080base.h | 73 + .../sdks/nv570/inc/ctrl/ctrl0080/ctrl0080bif.h | 125 + .../sdks/nv570/inc/ctrl/ctrl0080/ctrl0080cipher.h | 32 + .../sdks/nv570/inc/ctrl/ctrl0080/ctrl0080dma.h | 860 ++ .../sdks/nv570/inc/ctrl/ctrl0080/ctrl0080fb.h | 265 + .../sdks/nv570/inc/ctrl/ctrl0080/ctrl0080fifo.h | 403 + .../sdks/nv570/inc/ctrl/ctrl0080/ctrl0080gpu.h | 656 ++ .../sdks/nv570/inc/ctrl/ctrl0080/ctrl0080gr.h | 299 + .../sdks/nv570/inc/ctrl/ctrl0080/ctrl0080host.h | 87 + .../nv570/inc/ctrl/ctrl0080/ctrl0080internal.h | 148 + .../sdks/nv570/inc/ctrl/ctrl0080/ctrl0080nvdec.h | 117 + .../sdks/nv570/inc/ctrl/ctrl0080/ctrl0080nvenc.h | 96 + .../sdks/nv570/inc/ctrl/ctrl0080/ctrl0080nvjpg.h | 75 + .../sdks/nv570/inc/ctrl/ctrl0080/ctrl0080perf.h | 63 + .../sdks/nv570/inc/ctrl/ctrl0080/ctrl0080unix.h | 95 + userspace/sdks/nv570/inc/ctrl/ctrl0090.h | 154 + userspace/sdks/nv570/inc/ctrl/ctrl00da.h | 258 + userspace/sdks/nv570/inc/ctrl/ctrl00de.h | 98 + userspace/sdks/nv570/inc/ctrl/ctrl00e0.h | 158 + userspace/sdks/nv570/inc/ctrl/ctrl00f1.h | 245 + userspace/sdks/nv570/inc/ctrl/ctrl00f8.h | 331 + userspace/sdks/nv570/inc/ctrl/ctrl00f9.h | 87 + userspace/sdks/nv570/inc/ctrl/ctrl00fb.h | 114 + userspace/sdks/nv570/inc/ctrl/ctrl00fd.h | 280 + userspace/sdks/nv570/inc/ctrl/ctrl00fe.h | 107 + userspace/sdks/nv570/inc/ctrl/ctrl0100.h | 263 + userspace/sdks/nv570/inc/ctrl/ctrl2080.h | 91 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080acr.h | 32 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080base.h | 119 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080bif.h | 85 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080bios.h | 484 + .../nv570/inc/ctrl/ctrl2080/ctrl2080boardobj.h | 1280 ++ .../inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h | 34 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080bus.h | 1696 +++ .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080ce.h | 577 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080cipher.h | 32 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080clk.h | 128 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080clkavfs.h | 36 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080dma.h | 180 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080dmabuf.h | 127 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080ecc.h | 256 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080event.h | 396 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fan.h | 33 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fb.h | 3093 +++++ .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fifo.h | 1140 ++ .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fla.h | 208 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080flcn.h | 454 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fuse.h | 34 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gpio.h | 74 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gpu.h | 5026 ++++++++ .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gpumon.h | 96 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gr.h | 2034 ++++ .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080grmgr.h | 299 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gsp.h | 273 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080hshub.h | 73 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080i2c.h | 372 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080illum.h | 31 + .../nv570/inc/ctrl/ctrl2080/ctrl2080internal.h | 5589 +++++++++ .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080lpwr.h | 100 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080mc.h | 368 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080nvd.h | 385 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080nvlink.h | 3520 ++++++ .../inc/ctrl/ctrl2080/ctrl2080nvlink_common.h | 43 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080perf.h | 927 ++ .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080perf_cf.h | 33 + .../inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h | 32 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080pmgr.h | 67 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080pmu.h | 38 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080pmumon.h | 100 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080power.h | 123 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080rc.h | 414 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080spdm.h | 248 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080spi.h | 32 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080thermal.h | 417 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080tmr.h | 260 + .../nv570/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h | 32 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080unix.h | 190 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080vfe.h | 42 + .../inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h | 522 + .../sdks/nv570/inc/ctrl/ctrl2080/ctrl2080volt.h | 38 + userspace/sdks/nv570/inc/ctrl/ctrl208f.h | 54 + .../sdks/nv570/inc/ctrl/ctrl208f/ctrl208fbase.h | 69 + .../sdks/nv570/inc/ctrl/ctrl208f/ctrl208fbif.h | 194 + .../sdks/nv570/inc/ctrl/ctrl208f/ctrl208fbus.h | 113 + .../sdks/nv570/inc/ctrl/ctrl208f/ctrl208fce.h | 178 + .../sdks/nv570/inc/ctrl/ctrl208f/ctrl208fdma.h | 92 + .../sdks/nv570/inc/ctrl/ctrl208f/ctrl208ffb.h | 842 ++ .../sdks/nv570/inc/ctrl/ctrl208f/ctrl208ffbio.h | 249 + .../sdks/nv570/inc/ctrl/ctrl208f/ctrl208ffifo.h | 134 + .../sdks/nv570/inc/ctrl/ctrl208f/ctrl208fgpu.h | 169 + .../sdks/nv570/inc/ctrl/ctrl208f/ctrl208fgr.h | 169 + .../sdks/nv570/inc/ctrl/ctrl208f/ctrl208fmmu.h | 169 + .../sdks/nv570/inc/ctrl/ctrl208f/ctrl208fnvlink.h | 97 + .../sdks/nv570/inc/ctrl/ctrl208f/ctrl208fpmgr.h | 32 + .../sdks/nv570/inc/ctrl/ctrl208f/ctrl208fpmu.h | 115 + .../sdks/nv570/inc/ctrl/ctrl208f/ctrl208fpower.h | 32 + .../sdks/nv570/inc/ctrl/ctrl208f/ctrl208fsec2.h | 54 + .../ctrl/ctrl208f/ctrl208fucodeinstrumentation.h | 156 + userspace/sdks/nv570/inc/ctrl/ctrl30f1.h | 1619 +++ userspace/sdks/nv570/inc/ctrl/ctrl402c.h | 971 ++ userspace/sdks/nv570/inc/ctrl/ctrl503c.h | 200 + .../sdks/nv570/inc/ctrl/ctrl503c/ctrl503cbase.h | 50 + userspace/sdks/nv570/inc/ctrl/ctrl506f.h | 101 + .../sdks/nv570/inc/ctrl/ctrl5070/ctrl5070base.h | 66 + .../sdks/nv570/inc/ctrl/ctrl5070/ctrl5070chnc.h | 1062 ++ .../sdks/nv570/inc/ctrl/ctrl5070/ctrl5070common.h | 79 + .../nv570/inc/ctrl/ctrl5070/ctrl5070impoverrides.h | 33 + .../sdks/nv570/inc/ctrl/ctrl5070/ctrl5070or.h | 448 + .../sdks/nv570/inc/ctrl/ctrl5070/ctrl5070rg.h | 437 + .../sdks/nv570/inc/ctrl/ctrl5070/ctrl5070system.h | 81 + .../sdks/nv570/inc/ctrl/ctrl5070/ctrl5070verif.h | 32 + userspace/sdks/nv570/inc/ctrl/ctrl5080.h | 211 + userspace/sdks/nv570/inc/ctrl/ctrl83de.h | 36 + .../sdks/nv570/inc/ctrl/ctrl83de/ctrl83debase.h | 55 + .../sdks/nv570/inc/ctrl/ctrl83de/ctrl83dedebug.h | 1284 ++ userspace/sdks/nv570/inc/ctrl/ctrl9010.h | 83 + userspace/sdks/nv570/inc/ctrl/ctrl9067.h | 157 + userspace/sdks/nv570/inc/ctrl/ctrl906f.h | 223 + userspace/sdks/nv570/inc/ctrl/ctrl9072.h | 86 + userspace/sdks/nv570/inc/ctrl/ctrl9074.h | 148 + userspace/sdks/nv570/inc/ctrl/ctrl9096.h | 444 + userspace/sdks/nv570/inc/ctrl/ctrl90cc.h | 455 + .../sdks/nv570/inc/ctrl/ctrl90cc/ctrl90ccbase.h | 54 + .../sdks/nv570/inc/ctrl/ctrl90cc/ctrl90cchwpm.h | 135 + .../sdks/nv570/inc/ctrl/ctrl90cc/ctrl90ccpower.h | 403 + userspace/sdks/nv570/inc/ctrl/ctrl90cd.h | 174 + userspace/sdks/nv570/inc/ctrl/ctrl90e6.h | 137 + userspace/sdks/nv570/inc/ctrl/ctrl90e7.h | 34 + .../sdks/nv570/inc/ctrl/ctrl90e7/ctrl90e7base.h | 58 + .../sdks/nv570/inc/ctrl/ctrl90e7/ctrl90e7bbx.h | 122 + userspace/sdks/nv570/inc/ctrl/ctrl90ec.h | 124 + userspace/sdks/nv570/inc/ctrl/ctrl90f1.h | 407 + userspace/sdks/nv570/inc/ctrl/ctrla06c.h | 438 + userspace/sdks/nv570/inc/ctrl/ctrla06f.h | 36 + .../sdks/nv570/inc/ctrl/ctrla06f/ctrla06fbase.h | 59 + .../sdks/nv570/inc/ctrl/ctrla06f/ctrla06fgpfifo.h | 261 + .../nv570/inc/ctrl/ctrla06f/ctrla06finternal.h | 64 + userspace/sdks/nv570/inc/ctrl/ctrla080.h | 438 + userspace/sdks/nv570/inc/ctrl/ctrla081.h | 1078 ++ userspace/sdks/nv570/inc/ctrl/ctrla083.h | 227 + userspace/sdks/nv570/inc/ctrl/ctrla084.h | 387 + userspace/sdks/nv570/inc/ctrl/ctrla0bc.h | 119 + userspace/sdks/nv570/inc/ctrl/ctrla0bd.h | 100 + userspace/sdks/nv570/inc/ctrl/ctrlb069.h | 175 + userspace/sdks/nv570/inc/ctrl/ctrlb06f.h | 365 + userspace/sdks/nv570/inc/ctrl/ctrlb0cc.h | 397 + .../sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h | 52 + .../nv570/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h | 283 + .../sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccpower.h | 402 + .../nv570/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h | 727 ++ userspace/sdks/nv570/inc/ctrl/ctrlc365.h | 331 + userspace/sdks/nv570/inc/ctrl/ctrlc369.h | 157 + userspace/sdks/nv570/inc/ctrl/ctrlc36f.h | 159 + .../sdks/nv570/inc/ctrl/ctrlc370/ctrlc370base.h | 66 + .../sdks/nv570/inc/ctrl/ctrlc370/ctrlc370chnc.h | 303 + .../sdks/nv570/inc/ctrl/ctrlc370/ctrlc370event.h | 102 + .../sdks/nv570/inc/ctrl/ctrlc370/ctrlc370or.h | 93 + .../sdks/nv570/inc/ctrl/ctrlc370/ctrlc370rg.h | 98 + .../sdks/nv570/inc/ctrl/ctrlc370/ctrlc370verif.h | 133 + .../sdks/nv570/inc/ctrl/ctrlc372/ctrlc372base.h | 61 + .../sdks/nv570/inc/ctrl/ctrlc372/ctrlc372chnc.h | 903 ++ userspace/sdks/nv570/inc/ctrl/ctrlc56f.h | 187 + userspace/sdks/nv570/inc/ctrl/ctrlc637.h | 436 + userspace/sdks/nv570/inc/ctrl/ctrlc638.h | 91 + userspace/sdks/nv570/inc/ctrl/ctrlc763.h | 242 + userspace/sdks/nv570/inc/ctrl/ctrlcb33.h | 425 + userspace/sdks/nv570/inc/ctrl/ctrlcbca.h | 120 + userspace/sdks/nv570/inc/ctrl/ctrlxxxx.h | 74 + userspace/sdks/nv570/inc/dpringbuffertypes.h | 59 + userspace/sdks/nv570/inc/g_finn_rm_api.h | 728 ++ userspace/sdks/nv570/inc/mmu_fmt_types.h | 151 + userspace/sdks/nv570/inc/nv-hypervisor.h | 93 + userspace/sdks/nv570/inc/nv-kernel-interface-api.h | 41 + userspace/sdks/nv570/inc/nv_stdarg.h | 39 + userspace/sdks/nv570/inc/nv_vgpu_types.h | 61 + userspace/sdks/nv570/inc/nvcd.h | 159 + userspace/sdks/nv570/inc/nvcfg_sdk.h | 29 + userspace/sdks/nv570/inc/nvdeprecated.h | 125 + userspace/sdks/nv570/inc/nvdisptypes.h | 92 + userspace/sdks/nv570/inc/nvdump.h | 164 + userspace/sdks/nv570/inc/nverror.h | 303 + userspace/sdks/nv570/inc/nvfixedtypes.h | 408 + userspace/sdks/nv570/inc/nvgputypes.h | 177 + userspace/sdks/nv570/inc/nvi2c.h | 37 + userspace/sdks/nv570/inc/nvimpshared.h | 93 + userspace/sdks/nv570/inc/nvlimits.h | 58 + userspace/sdks/nv570/inc/nvmisc.h | 1148 ++ userspace/sdks/nv570/inc/nvos.h | 3333 ++++++ userspace/sdks/nv570/inc/nvsecurityinfo.h | 71 + userspace/sdks/nv570/inc/nvstatus.h | 123 + userspace/sdks/nv570/inc/nvstatuscodes.h | 184 + userspace/sdks/nv570/inc/nvtypes.h | 793 ++ userspace/sdks/nv570/inc/rmcd.h | 394 + userspace/sdks/nv570/inc/rs_access.h | 273 + .../common/inc/conf_compute/cc_keyrotation.h | 34 + .../nvalloc/common/inc/conf_compute/cc_keystore.h | 487 + .../nv570/nvalloc/common/inc/dev_ctrl_defines.h | 87 + .../sdks/nv570/nvalloc/common/inc/flcnifcmn.h | 141 + .../sdks/nv570/nvalloc/common/inc/flcnretval.h | 305 + .../nvalloc/common/inc/fsp/fsp_caps_query_rpc.h | 51 + .../nvalloc/common/inc/fsp/fsp_clock_boost_rpc.h | 44 + .../nvalloc/common/inc/fsp/fsp_emem_channels.h | 39 + .../nv570/nvalloc/common/inc/fsp/fsp_tnvl_rpc.h | 137 + .../common/inc/fsp/nvdm_payload_cmd_response.h | 44 + .../common/inc/gsp/gsp_fmc_error_code_formatting.h | 79 + .../nv570/nvalloc/common/inc/gsp/gsp_fw_sr_meta.h | 74 + .../nv570/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h | 242 + .../nv570/nvalloc/common/inc/gsp/gsp_proxy_reg.h | 83 + .../sdks/nv570/nvalloc/common/inc/gsp/gspifpub.h | 181 + .../sdks/nv570/nvalloc/common/inc/inforom/ifrdem.h | 43 + .../sdks/nv570/nvalloc/common/inc/inforom/ifrecc.h | 119 + .../sdks/nv570/nvalloc/common/inc/inforom/ifrnvl.h | 1561 +++ .../nv570/nvalloc/common/inc/inforom/ifrstruct.h | 110 + .../sdks/nv570/nvalloc/common/inc/inforom/omsdef.h | 116 + .../sdks/nv570/nvalloc/common/inc/inforom/types.h | 79 + .../sdks/nv570/nvalloc/common/inc/mctp_format.h | 120 + .../common/inc/nv-firmware-chip-family-select.h | 230 + .../sdks/nv570/nvalloc/common/inc/nv-firmware.h | 145 + userspace/sdks/nv570/nvalloc/common/inc/nvcst.h | 460 + .../sdks/nv570/nvalloc/common/inc/nvdm_format.h | 63 + userspace/sdks/nv570/nvalloc/common/inc/nvpcie.h | 545 + .../sdks/nv570/nvalloc/common/inc/nvrangetypes.h | 162 + .../sdks/nv570/nvalloc/common/inc/oob/smbpbi.h | 2925 +++++ .../nv570/nvalloc/common/inc/oob/smbpbi_impl.h | 45 + .../nv570/nvalloc/common/inc/oob/smbpbi_priv.h | 59 + .../sdks/nv570/nvalloc/common/inc/rmRiscvUcode.h | 95 + .../nv570/nvalloc/common/inc/rm_state_monitor.h | 72 + userspace/sdks/nv570/nvalloc/common/inc/rmflcnbl.h | 147 + userspace/sdks/nv570/nvalloc/common/inc/rmgspseq.h | 66 + userspace/sdks/nv570/nvalloc/common/inc/rmifrif.h | 123 + userspace/sdks/nv570/nvalloc/common/inc/rmlsfm.h | 579 + .../sdks/nv570/nvalloc/common/inc/rmpbicmdif.h | 140 + .../common/inc/sec2/nvdm_payload_cmd_response.h | 44 + .../nvalloc/common/inc/sec2/sec2_emem_channels.h | 39 + .../nv570/nvalloc/common/inc/spdm/rmspdmrsakeys.h | 160 + .../nvalloc/common/inc/spdm/rmspdmtransport.h | 97 + .../nvalloc/common/inc/spdm/rmspdmvendordef.h | 161 + .../sdks/nv570/nvalloc/unix/include/nv-caps.h | 94 + .../nvalloc/unix/include/nv-chardev-numbers.h | 43 + .../sdks/nv570/nvalloc/unix/include/nv-gpu-info.h | 47 + .../nvalloc/unix/include/nv-ioctl-lockless-diag.h | 43 + .../nv570/nvalloc/unix/include/nv-ioctl-numa.h | 81 + .../nv570/nvalloc/unix/include/nv-ioctl-numbers.h | 48 + .../sdks/nv570/nvalloc/unix/include/nv-ioctl.h | 158 + .../nvalloc/unix/include/nv-kernel-rmapi-ops.h | 61 + .../sdks/nv570/nvalloc/unix/include/nv-nb-regs.h | 65 + .../sdks/nv570/nvalloc/unix/include/nv-priv.h | 357 + userspace/sdks/nv570/nvalloc/unix/include/nv-reg.h | 1137 ++ .../unix/include/nv-unix-nvos-params-wrappers.h | 49 + userspace/sdks/nv570/nvalloc/unix/include/nv.h | 1367 +++ .../sdks/nv570/nvalloc/unix/include/nv_escape.h | 55 + .../sdks/nv570/nvalloc/unix/include/os-interface.h | 298 + .../sdks/nv570/nvalloc/unix/include/os_custom.h | 60 + userspace/sdks/nv570/nvalloc/unix/include/osapi.h | 203 + .../nv570/nvalloc/unix/include/rmobjexportimport.h | 40 + .../sdks/nv570/nvalloc/unix/include/x86emu/debug.h | 211 + .../nv570/nvalloc/unix/include/x86emu/decode.h | 88 + .../sdks/nv570/nvalloc/unix/include/x86emu/fpu.h | 61 + .../nv570/nvalloc/unix/include/x86emu/fpu_regs.h | 119 + .../sdks/nv570/nvalloc/unix/include/x86emu/ops.h | 45 + .../nv570/nvalloc/unix/include/x86emu/prim_ops.h | 141 + .../sdks/nv570/nvalloc/unix/include/x86emu/regs.h | 340 + .../sdks/nv570/nvalloc/unix/include/x86emu/types.h | 93 + .../nv570/nvalloc/unix/include/x86emu/x86emu.h | 205 + .../nv570/nvalloc/unix/include/x86emu/x86emui.h | 113 + .../sdks/nv570/nvalloc/unix/src/asm/x86/nv_cpuid.c | 51 + .../sdks/nv570/nvalloc/unix/src/asm/x86/nv_rdcr.c | 37 + .../sdks/nv570/nvalloc/unix/src/dynamic-power.c | 3185 +++++ userspace/sdks/nv570/nvalloc/unix/src/escape.c | 1017 ++ .../sdks/nv570/nvalloc/unix/src/exports-stubs.c | 30 + userspace/sdks/nv570/nvalloc/unix/src/gcc_helper.c | 35 + .../sdks/nv570/nvalloc/unix/src/os-hypervisor.c | 994 ++ userspace/sdks/nv570/nvalloc/unix/src/os.c | 6359 ++++++++++ userspace/sdks/nv570/nvalloc/unix/src/osapi.c | 6284 ++++++++++ userspace/sdks/nv570/nvalloc/unix/src/osinit.c | 2768 +++++ userspace/sdks/nv570/nvalloc/unix/src/osmemdesc.c | 1325 +++ userspace/sdks/nv570/nvalloc/unix/src/osnvlink.c | 783 ++ userspace/sdks/nv570/nvalloc/unix/src/osunix.c | 42 + .../nvalloc/unix/src/power-management-tegra.c | 100 + userspace/sdks/nv570/nvalloc/unix/src/registry.c | 712 ++ userspace/sdks/nv570/nvalloc/unix/src/rm-gpu-ops.c | 1079 ++ .../nv570/nvalloc/unix/src/rmobjexportimport.c | 650 + .../nvalloc/unix/src/subdevice_ctrl_os_unix.c | 97 + .../sdks/nv570/nvalloc/unix/src/unix_console.c | 412 + userspace/sdks/nv570/nvalloc/unix/src/unix_intr.c | 1050 ++ userspace/sdks/nv570/nvalloc/unix/src/vbioscall.c | 457 + userspace/sdks/nv570/nvalloc/unix/x86emu/debug.c | 547 + userspace/sdks/nv570/nvalloc/unix/x86emu/decode.c | 1094 ++ userspace/sdks/nv570/nvalloc/unix/x86emu/fpu.c | 965 ++ userspace/sdks/nv570/nvalloc/unix/x86emu/ops.c | 11761 +++++++++++++++++++ userspace/sdks/nv570/nvalloc/unix/x86emu/ops2.c | 2877 +++++ .../sdks/nv570/nvalloc/unix/x86emu/prim_ops.c | 2655 +++++ userspace/sdks/nv570/nvalloc/unix/x86emu/sys.c | 663 ++ userspace/sdks/nv570/nvidia/inc/Nvcm.h | 71 + .../sdks/nv570/nvidia/inc/alloc/alloc_channel.h | 319 + userspace/sdks/nv570/nvidia/inc/class/cl0000.h | 52 + .../nv570/nvidia/inc/class/cl0000_notification.h | 68 + userspace/sdks/nv570/nvidia/inc/class/cl0001.h | 37 + userspace/sdks/nv570/nvidia/inc/class/cl0002.h | 51 + userspace/sdks/nv570/nvidia/inc/class/cl0004.h | 50 + userspace/sdks/nv570/nvidia/inc/class/cl0005.h | 58 + .../nv570/nvidia/inc/class/cl0005_notification.h | 51 + userspace/sdks/nv570/nvidia/inc/class/cl000f.h | 55 + userspace/sdks/nv570/nvidia/inc/class/cl0020.h | 31 + userspace/sdks/nv570/nvidia/inc/class/cl0030.h | 51 + userspace/sdks/nv570/nvidia/inc/class/cl003e.h | 51 + userspace/sdks/nv570/nvidia/inc/class/cl003f.h | 58 + userspace/sdks/nv570/nvidia/inc/class/cl0040.h | 55 + userspace/sdks/nv570/nvidia/inc/class/cl0041.h | 45 + userspace/sdks/nv570/nvidia/inc/class/cl0060.h | 39 + userspace/sdks/nv570/nvidia/inc/class/cl0070.h | 73 + userspace/sdks/nv570/nvidia/inc/class/cl0071.h | 38 + userspace/sdks/nv570/nvidia/inc/class/cl0073.h | 55 + userspace/sdks/nv570/nvidia/inc/class/cl0076.h | 38 + userspace/sdks/nv570/nvidia/inc/class/cl007d.h | 64 + userspace/sdks/nv570/nvidia/inc/class/cl0080.h | 64 + .../nv570/nvidia/inc/class/cl0080_notification.h | 45 + userspace/sdks/nv570/nvidia/inc/class/cl0090.h | 32 + userspace/sdks/nv570/nvidia/inc/class/cl0092.h | 72 + .../sdks/nv570/nvidia/inc/class/cl0092_callback.h | 28 + userspace/sdks/nv570/nvidia/inc/class/cl00b1.h | 28 + userspace/sdks/nv570/nvidia/inc/class/cl00c1.h | 65 + userspace/sdks/nv570/nvidia/inc/class/cl00c2.h | 41 + userspace/sdks/nv570/nvidia/inc/class/cl00c3.h | 43 + userspace/sdks/nv570/nvidia/inc/class/cl00db.h | 43 + userspace/sdks/nv570/nvidia/inc/class/cl00de.h | 50 + userspace/sdks/nv570/nvidia/inc/class/cl00f2.h | 38 + userspace/sdks/nv570/nvidia/inc/class/cl00f3.h | 75 + userspace/sdks/nv570/nvidia/inc/class/cl00f8.h | 119 + userspace/sdks/nv570/nvidia/inc/class/cl00fc.h | 39 + userspace/sdks/nv570/nvidia/inc/class/cl00fd.h | 73 + userspace/sdks/nv570/nvidia/inc/class/cl00fe.h | 46 + userspace/sdks/nv570/nvidia/inc/class/cl2080.h | 46 + .../nv570/nvidia/inc/class/cl2080_notification.h | 497 + userspace/sdks/nv570/nvidia/inc/class/cl2081.h | 40 + userspace/sdks/nv570/nvidia/inc/class/cl2082.h | 40 + userspace/sdks/nv570/nvidia/inc/class/cl208f.h | 53 + userspace/sdks/nv570/nvidia/inc/class/cl30f1.h | 56 + .../nv570/nvidia/inc/class/cl30f1_notification.h | 74 + userspace/sdks/nv570/nvidia/inc/class/cl402c.h | 47 + userspace/sdks/nv570/nvidia/inc/class/cl503b.h | 57 + userspace/sdks/nv570/nvidia/inc/class/cl503c.h | 47 + userspace/sdks/nv570/nvidia/inc/class/cl506f.h | 157 + userspace/sdks/nv570/nvidia/inc/class/cl5070.h | 44 + .../nv570/nvidia/inc/class/cl5070_notification.h | 45 + userspace/sdks/nv570/nvidia/inc/class/cl5080.h | 46 + .../nv570/nvidia/inc/class/cl5080_notification.h | 43 + userspace/sdks/nv570/nvidia/inc/class/cl50a0.h | 38 + userspace/sdks/nv570/nvidia/inc/class/cl83de.h | 56 + userspace/sdks/nv570/nvidia/inc/class/cl844c.h | 47 + userspace/sdks/nv570/nvidia/inc/class/cl84a0.h | 110 + .../nv570/nvidia/inc/class/cl84a0_deprecated.h | 90 + userspace/sdks/nv570/nvidia/inc/class/cl85b5sw.h | 38 + userspace/sdks/nv570/nvidia/inc/class/cl900e.h | 39 + userspace/sdks/nv570/nvidia/inc/class/cl9010.h | 45 + .../sdks/nv570/nvidia/inc/class/cl9010_callback.h | 27 + userspace/sdks/nv570/nvidia/inc/class/cl902d.h | 1092 ++ userspace/sdks/nv570/nvidia/inc/class/cl9067.h | 39 + userspace/sdks/nv570/nvidia/inc/class/cl906f.h | 242 + userspace/sdks/nv570/nvidia/inc/class/cl906fsw.h | 42 + userspace/sdks/nv570/nvidia/inc/class/cl9072.h | 46 + .../nv570/nvidia/inc/class/cl9072_notification.h | 39 + userspace/sdks/nv570/nvidia/inc/class/cl9074.h | 51 + .../sdks/nv570/nvidia/inc/class/cl907dswspare.h | 37 + userspace/sdks/nv570/nvidia/inc/class/cl9096.h | 40 + userspace/sdks/nv570/nvidia/inc/class/cl9097.h | 3815 ++++++ userspace/sdks/nv570/nvidia/inc/class/cl90cc.h | 48 + userspace/sdks/nv570/nvidia/inc/class/cl90cd.h | 237 + userspace/sdks/nv570/nvidia/inc/class/cl90cdfecs.h | 112 + .../sdks/nv570/nvidia/inc/class/cl90cdtypes.h | 47 + userspace/sdks/nv570/nvidia/inc/class/cl90ce.h | 42 + userspace/sdks/nv570/nvidia/inc/class/cl90e6.h | 43 + userspace/sdks/nv570/nvidia/inc/class/cl90ec.h | 46 + userspace/sdks/nv570/nvidia/inc/class/cl90f1.h | 39 + userspace/sdks/nv570/nvidia/inc/class/cl9170.h | 41 + userspace/sdks/nv570/nvidia/inc/class/cl9171.h | 295 + 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userspace/sdks/nv570/nvidia/inc/class/clb4b7.h | 40 + userspace/sdks/nv570/nvidia/inc/class/clb6b0.h | 39 + userspace/sdks/nv570/nvidia/inc/class/clb8b0.h | 27 + userspace/sdks/nv570/nvidia/inc/class/clb8d1.h | 27 + userspace/sdks/nv570/nvidia/inc/class/clb8fa.h | 29 + userspace/sdks/nv570/nvidia/inc/class/clc06f.h | 312 + userspace/sdks/nv570/nvidia/inc/class/clc06fsw.h | 44 + userspace/sdks/nv570/nvidia/inc/class/clc076.h | 82 + userspace/sdks/nv570/nvidia/inc/class/clc097.h | 4191 +++++++ userspace/sdks/nv570/nvidia/inc/class/clc097tex.h | 1353 +++ userspace/sdks/nv570/nvidia/inc/class/clc0b5.h | 261 + userspace/sdks/nv570/nvidia/inc/class/clc0b5sw.h | 54 + userspace/sdks/nv570/nvidia/inc/class/clc0b7.h | 40 + userspace/sdks/nv570/nvidia/inc/class/clc0c0.h | 777 ++ userspace/sdks/nv570/nvidia/inc/class/clc197.h | 4242 +++++++ userspace/sdks/nv570/nvidia/inc/class/clc1b0.h | 40 + userspace/sdks/nv570/nvidia/inc/class/clc1b5.h | 273 + userspace/sdks/nv570/nvidia/inc/class/clc1b5sw.h | 54 + userspace/sdks/nv570/nvidia/inc/class/clc1b7.h | 40 + userspace/sdks/nv570/nvidia/inc/class/clc1c0.h | 795 ++ userspace/sdks/nv570/nvidia/inc/class/clc2b0.h | 39 + userspace/sdks/nv570/nvidia/inc/class/clc2b7.h | 40 + userspace/sdks/nv570/nvidia/inc/class/clc361.h | 35 + userspace/sdks/nv570/nvidia/inc/class/clc365.h | 88 + userspace/sdks/nv570/nvidia/inc/class/clc369.h | 77 + userspace/sdks/nv570/nvidia/inc/class/clc36f.h | 366 + userspace/sdks/nv570/nvidia/inc/class/clc36fsw.h | 44 + userspace/sdks/nv570/nvidia/inc/class/clc370.h | 43 + .../nv570/nvidia/inc/class/clc370_notification.h | 45 + userspace/sdks/nv570/nvidia/inc/class/clc371.h | 41 + userspace/sdks/nv570/nvidia/inc/class/clc372sw.h | 36 + userspace/sdks/nv570/nvidia/inc/class/clc373.h | 350 + userspace/sdks/nv570/nvidia/inc/class/clc37a.h | 213 + userspace/sdks/nv570/nvidia/inc/class/clc37b.h | 67 + userspace/sdks/nv570/nvidia/inc/class/clc37d.h | 953 ++ .../sdks/nv570/nvidia/inc/class/clc37dcrcnotif.h | 49 + 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userspace/sdks/nv570/nvidia/inc/class/clc77f.h | 34 + userspace/sdks/nv570/nvidia/inc/class/clc797.h | 4481 +++++++ userspace/sdks/nv570/nvidia/inc/class/clc7b0.h | 40 + userspace/sdks/nv570/nvidia/inc/class/clc7b5.h | 304 + userspace/sdks/nv570/nvidia/inc/class/clc7b7.h | 39 + userspace/sdks/nv570/nvidia/inc/class/clc7c0.h | 848 ++ userspace/sdks/nv570/nvidia/inc/class/clc7fa.h | 40 + userspace/sdks/nv570/nvidia/inc/class/clc86f.h | 84 + userspace/sdks/nv570/nvidia/inc/class/clc86fsw.h | 44 + userspace/sdks/nv570/nvidia/inc/class/clc8b5.h | 77 + userspace/sdks/nv570/nvidia/inc/class/clc997.h | 4481 +++++++ userspace/sdks/nv570/nvidia/inc/class/clc9b0.h | 29 + userspace/sdks/nv570/nvidia/inc/class/clc9b7.h | 29 + userspace/sdks/nv570/nvidia/inc/class/clc9c0.h | 29 + userspace/sdks/nv570/nvidia/inc/class/clc9d1.h | 31 + userspace/sdks/nv570/nvidia/inc/class/clc9fa.h | 32 + userspace/sdks/nv570/nvidia/inc/class/clcb97.h | 4480 +++++++ userspace/sdks/nv570/nvidia/inc/class/clcb97tex.h | 2437 ++++ userspace/sdks/nv570/nvidia/inc/class/clcbc0.h | 27 + userspace/sdks/nv570/nvidia/inc/class/clcbca.h | 39 + userspace/sdks/nv570/nvidia/inc/class/cld0b7.h | 40 + userspace/sdks/nv570/nvidia/inc/cpuopsys.h | 422 + .../nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h | 68 + .../nvidia/inc/ctrl/ctrl0000/ctrl0000client.h | 183 + .../nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h | 326 + .../nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h | 113 + .../nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h | 873 ++ .../nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h | 255 + .../nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h | 101 + .../nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h | 636 + .../nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h | 98 + .../inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h | 112 + .../nvidia/inc/ctrl/ctrl0000/ctrl0000system.h | 2915 +++++ .../nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h | 435 + .../nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h | 78 + 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create mode 100644 userspace/tests/test_vgpu_userspace.c (limited to 'userspace') diff --git a/userspace/LICENSE b/userspace/LICENSE new file mode 100644 index 0000000..d159169 --- /dev/null +++ b/userspace/LICENSE @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Lesser General Public License instead.) You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +this service if you wish), that you receive source code or can get it +if you want it, that you can change the software or use pieces of it +in new free programs; and that you know you can do these things. + + To protect your rights, we need to make restrictions that forbid +anyone to deny you these rights or to ask you to surrender the rights. +These restrictions translate to certain responsibilities for you if you +distribute copies of the software, or if you modify it. + + For example, if you distribute copies of such a program, whether +gratis or for a fee, you must give the recipients all the rights that +you have. You must make sure that they, too, receive or can get the +source code. And you must show them these terms so they know their +rights. + + We protect your rights with two steps: (1) copyright the software, and +(2) offer you this license which gives you legal permission to copy, +distribute and/or modify the software. + + Also, for each author's protection and ours, we want to make certain +that everyone understands that there is no warranty for this free +software. If the software is modified by someone else and passed on, we +want its recipients to know that what they have is not the original, so +that any problems introduced by others will not reflect on the original +authors' reputations. + + Finally, any free program is threatened constantly by software +patents. We wish to avoid the danger that redistributors of a free +program will individually obtain patent licenses, in effect making the +program proprietary. To prevent this, we have made it clear that any +patent must be licensed for everyone's free use or not licensed at all. + + The precise terms and conditions for copying, distribution and +modification follow. + + GNU GENERAL PUBLIC LICENSE + TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + + 0. This License applies to any program or other work which contains +a notice placed by the copyright holder saying it may be distributed +under the terms of this General Public License. The "Program", below, +refers to any such program or work, and a "work based on the Program" +means either the Program or any derivative work under copyright law: +that is to say, a work containing the Program or a portion of it, +either verbatim or with modifications and/or translated into another +language. (Hereinafter, translation is included without limitation in +the term "modification".) Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. The act of +running the Program is not restricted, and the output from the Program +is covered only if its contents constitute a work based on the +Program (independent of having been made by running the Program). +Whether that is true depends on what the Program does. + + 1. You may copy and distribute verbatim copies of the Program's +source code as you receive it, in any medium, provided that you +conspicuously and appropriately publish on each copy an appropriate +copyright notice and disclaimer of warranty; keep intact all the +notices that refer to this License and to the absence of any warranty; +and give any other recipients of the Program a copy of this License +along with the Program. + +You may charge a fee for the physical act of transferring a copy, and +you may at your option offer warranty protection in exchange for a fee. + + 2. You may modify your copy or copies of the Program or any portion +of it, thus forming a work based on the Program, and copy and +distribute such modifications or work under the terms of Section 1 +above, provided that you also meet all of these conditions: + + a) You must cause the modified files to carry prominent notices + stating that you changed the files and the date of any change. + + b) You must cause any work that you distribute or publish, that in + whole or in part contains or is derived from the Program or any + part thereof, to be licensed as a whole at no charge to all third + parties under the terms of this License. + + c) If the modified program normally reads commands interactively + when run, you must cause it, when started running for such + interactive use in the most ordinary way, to print or display an + announcement including an appropriate copyright notice and a + notice that there is no warranty (or else, saying that you provide + a warranty) and that users may redistribute the program under + these conditions, and telling the user how to view a copy of this + License. (Exception: if the Program itself is interactive but + does not normally print such an announcement, your work based on + the Program is not required to print an announcement.) + +These requirements apply to the modified work as a whole. If +identifiable sections of that work are not derived from the Program, +and can be reasonably considered independent and separate works in +themselves, then this License, and its terms, do not apply to those +sections when you distribute them as separate works. But when you +distribute the same sections as part of a whole which is a work based +on the Program, the distribution of the whole must be on the terms of +this License, whose permissions for other licensees extend to the +entire whole, and thus to each and every part regardless of who wrote it. + +Thus, it is not the intent of this section to claim rights or contest +your rights to work written entirely by you; rather, the intent is to +exercise the right to control the distribution of derivative or +collective works based on the Program. + +In addition, mere aggregation of another work not based on the Program +with the Program (or with a work based on the Program) on a volume of +a storage or distribution medium does not bring the other work under +the scope of this License. + + 3. You may copy and distribute the Program (or a work based on it, +under Section 2) in object code or executable form under the terms of +Sections 1 and 2 above provided that you also do one of the following: + + a) Accompany it with the complete corresponding machine-readable + source code, which must be distributed under the terms of Sections + 1 and 2 above on a medium customarily used for software interchange; or, + + b) Accompany it with a written offer, valid for at least three + years, to give any third party, for a charge no more than your + cost of physically performing source distribution, a complete + machine-readable copy of the corresponding source code, to be + distributed under the terms of Sections 1 and 2 above on a medium + customarily used for software interchange; or, + + c) Accompany it with the information you received as to the offer + to distribute corresponding source code. (This alternative is + allowed only for noncommercial distribution and only if you + received the program in object code or executable form with such + an offer, in accord with Subsection b above.) + +The source code for a work means the preferred form of the work for +making modifications to it. For an executable work, complete source +code means all the source code for all modules it contains, plus any +associated interface definition files, plus the scripts used to +control compilation and installation of the executable. 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Any attempt +otherwise to copy, modify, sublicense or distribute the Program is +void, and will automatically terminate your rights under this License. +However, parties who have received copies, or rights, from you under +this License will not have their licenses terminated so long as such +parties remain in full compliance. + + 5. You are not required to accept this License, since you have not +signed it. However, nothing else grants you permission to modify or +distribute the Program or its derivative works. These actions are +prohibited by law if you do not accept this License. Therefore, by +modifying or distributing the Program (or any work based on the +Program), you indicate your acceptance of this License to do so, and +all its terms and conditions for copying, distributing or modifying +the Program or works based on it. + + 6. Each time you redistribute the Program (or any work based on the +Program), the recipient automatically receives a license from the +original licensor to copy, distribute or modify the Program subject to +these terms and conditions. You may not impose any further +restrictions on the recipients' exercise of the rights granted herein. +You are not responsible for enforcing compliance by third parties to +this License. + + 7. If, as a consequence of a court judgment or allegation of patent +infringement or for any other reason (not limited to patent issues), +conditions are imposed on you (whether by court order, agreement or +otherwise) that contradict the conditions of this License, they do not +excuse you from the conditions of this License. If you cannot +distribute so as to satisfy simultaneously your obligations under this +License and any other pertinent obligations, then as a consequence you +may not distribute the Program at all. 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Many people have made +generous contributions to the wide range of software distributed +through that system in reliance on consistent application of that +system; it is up to the author/donor to decide if he or she is willing +to distribute software through any other system and a licensee cannot +impose that choice. + +This section is intended to make thoroughly clear what is believed to +be a consequence of the rest of this License. + + 8. If the distribution and/or use of the Program is restricted in +certain countries either by patents or by copyrighted interfaces, the +original copyright holder who places the Program under this License +may add an explicit geographical distribution limitation excluding +those countries, so that distribution is permitted only in or among +countries not thus excluded. In such case, this License incorporates +the limitation as if written in the body of this License. + + 9. The Free Software Foundation may publish revised and/or new versions +of the General Public License from time to time. Such new versions will +be similar in spirit to the present version, but may differ in detail to +address new problems or concerns. + +Each version is given a distinguishing version number. If the Program +specifies a version number of this License which applies to it and "any +later version", you have the option of following the terms and conditions +either of that version or of any later version published by the Free +Software Foundation. If the Program does not specify a version number of +this License, you may choose any version ever published by the Free Software +Foundation. + + 10. If you wish to incorporate parts of the Program into other free +programs whose distribution conditions are different, write to the author +to ask for permission. For software which is copyrighted by the Free +Software Foundation, write to the Free Software Foundation; we sometimes +make exceptions for this. Our decision will be guided by the two goals +of preserving the free status of all derivatives of our free software and +of promoting the sharing and reuse of software generally. + + NO WARRANTY + + 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY +FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN +OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES +PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED +OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS +TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE +PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, +REPAIR OR CORRECTION. + + 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR +REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, +INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING +OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED +TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY +YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER +PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/userspace/Makefile b/userspace/Makefile new file mode 100644 index 0000000..e746fce --- /dev/null +++ b/userspace/Makefile @@ -0,0 +1,25 @@ +# GSP vGPU-IO Userspace Makefile + +SUBDIRS = lib examples + +all: + for dir in $(SUBDIRS); do \ + $(MAKE) -C $$dir || exit 1; \ + done + +clean: + for dir in $(SUBDIRS); do \ + $(MAKE) -C $$dir clean; \ + done + +install: + for dir in $(SUBDIRS); do \ + $(MAKE) -C $$dir install || exit 1; \ + done + +uninstall: + for dir in $(SUBDIRS); do \ + $(MAKE) -C $$dir uninstall; \ + done + +.PHONY: all clean install uninstall $(SUBDIRS) \ No newline at end of file diff --git a/userspace/configs/generic.toml b/userspace/configs/generic.toml new file mode 100644 index 0000000..c4ebe03 --- /dev/null +++ b/userspace/configs/generic.toml @@ -0,0 +1,45 @@ +[[config]] + [[config.gpu_config]] + vendor_id = 0x10DE + + [[config.request]] + num = 587 + v_dev_id = 0x223514F9 + p_dev_id = 0x2235 + name = "GVM GPU" + class = "Compute" + fb_len = 46016 + max_instances = 1 + ecc_support = True + multi_mdev = True + fb_res = 3136 + map_video_size = 4 + enc_cap = 100 + bar1_len = 0x800 + [config.request.display] + num_heads = 1 + max_res_x = 4096 + max_res_y = 2160 + frl_config = 60 + frl_enable = 1 + + [[config.request]] + num = 235 + v_dev_id = 0x1ED31F01 + p_dev_id = 0x1ED3 + name = "GRID RTX T10-4" + class = "Compute" + fb_len = 8192 + max_instances = 1 + ecc_support = True + multi_mdev = True + fb_res = 1024 + map_video_size = 4 + enc_cap = 100 + bar1_len = 0x800 + [config.request.display] + num_heads = 1 + max_res_x = 4096 + max_res_y = 2160 + frl_config = 60 + frl_enable = 1 diff --git a/userspace/examples/Makefile b/userspace/examples/Makefile new file mode 100644 index 0000000..065e00f --- /dev/null +++ b/userspace/examples/Makefile @@ -0,0 +1,27 @@ +# GSP vGPU-IO Examples Makefile + +PREFIX ?= /usr/local +LIBDIR ?= $(PREFIX)/lib +INCLUDEDIR ?= $(PREFIX)/include + +CC ?= gcc +CFLAGS ?= -O2 -g -Wall -Wextra -I../include +LDFLAGS ?= -L../lib -liov + +EXAMPLES = example_vgpu + +all: $(EXAMPLES) + +example_vgpu: example_vgpu.c ../lib/libiov.so + $(CC) $(CFLAGS) -o $@ $< $(LDFLAGS) + +clean: + rm -f $(EXAMPLES) + +install: all + install -d $(DESTDIR)$(PREFIX)/bin + for ex in $(EXAMPLES); do \ + install -m 755 $$ex $(DESTDIR)$(PREFIX)/bin/; \ + done + +.PHONY: all clean install \ No newline at end of file diff --git a/userspace/examples/example_vgpu.c b/userspace/examples/example_vgpu.c new file mode 100644 index 0000000..ede6873 --- /dev/null +++ b/userspace/examples/example_vgpu.c @@ -0,0 +1,173 @@ +/* + * GSP vGPU-IO Example Application + * Demonstrates basic VF creation, memory allocation, and BAR configuration + */ + +#include +#include +#include +#include +#include +#include + +static volatile bool running = true; + +static void signal_handler(int sig) +{ + (void)sig; + running = false; +} + +int main(int argc, char *argv[]) +{ + const char *device_path = "/dev/gsp-vgpu"; + vgpu_device_t device = NULL; + vgpu_vf_t vf = NULL; + vgpu_handle_t handle = 0; + uint64_t va = 0; + uint64_t dma_addr = 0; + int ret; + + if (argc > 1) + device_path = argv[1]; + + printf("GSP vGPU-IO Example Application\n"); + printf("Device: %s\n", device_path); + + signal(SIGINT, signal_handler); + signal(SIGTERM, signal_handler); + + /* Open device */ + ret = vgpu_open(device_path, &device); + if (ret != VGPU_OK) { + fprintf(stderr, "Failed to open device: %s\n", vgpu_strerror(ret)); + return 1; + } + printf("Device opened successfully\n"); + + /* Get device info */ + char info[256]; + ret = vgpu_get_info(device, info, sizeof(info)); + if (ret == VGPU_OK) + printf("Device info: %s\n", info); + + /* Create VF */ + vgpu_vf_config_t config = { + .id = 1, + .bar1_offset = 0x10000000, + .bar1_size = 0x40000, + .pt_base = 0, + .pt_size = 0, + .cmd_base = 0, + .cmd_size = 0, + .max_memory_mb = 1024, + .num_engines = 4, + }; + + ret = vgpu_vf_create(device, &config, &vf); + if (ret != VGPU_OK) { + fprintf(stderr, "Failed to create VF: %s\n", vgpu_strerror(ret)); + vgpu_close(device); + return 1; + } + printf("VF %u created\n", config.id); + + /* Configure BAR1 */ + ret = vgpu_bar_config(vf, 0x10000000, 0x40000); + if (ret != VGPU_OK) { + fprintf(stderr, "Failed to configure BAR: %s\n", vgpu_strerror(ret)); + vgpu_vf_destroy(vf); + vgpu_close(device); + return 1; + } + printf("BAR1 configured\n"); + + /* Allocate VRAM */ + const uint64_t alloc_size = 1024 * 1024; /* 1 MB */ + ret = vgpu_mem_alloc(vf, alloc_size, VGPU_MEM_VRAM, 0x1000, 0, + 0, &handle, &va); + if (ret != VGPU_OK) { + fprintf(stderr, "Failed to allocate memory: %s\n", vgpu_strerror(ret)); + vgpu_vf_destroy(vf); + vgpu_close(device); + return 1; + } + printf("Allocated %llu bytes at VA 0x%llx (handle 0x%llx)\n", + (unsigned long long)alloc_size, (unsigned long long)va, + (unsigned long long)handle); + + /* Map memory */ + uint64_t mapped_va = 0; + ret = vgpu_mem_map(vf, handle, va, alloc_size, 0x3, 0, 0, &mapped_va); + if (ret != VGPU_OK) { + fprintf(stderr, "Failed to map memory: %s\n", vgpu_strerror(ret)); + vgpu_mem_free(vf, handle); + vgpu_vf_destroy(vf); + vgpu_close(device); + return 1; + } + printf("Mapped at 0x%llx\n", (unsigned long long)mapped_va); + + /* Pin for DMA */ + ret = vgpu_mem_pin(vf, handle, 0, alloc_size, VGPU_PIN_READ | VGPU_PIN_WRITE, &dma_addr); + if (ret != VGPU_OK) { + fprintf(stderr, "Failed to pin memory: %s\n", vgpu_strerror(ret)); + } else { + printf("Pinned for DMA at 0x%llx\n", (unsigned long long)dma_addr); + } + + /* Protect with WPR (write) */ + ret = vgpu_wpr_protect_write(vf, va, alloc_size); + if (ret != VGPU_OK) { + fprintf(stderr, "Failed to protect with WPR: %s\n", vgpu_strerror(ret)); + } else { + printf("WPR write protection enabled\n"); + } + + /* Set WPR timeout */ + ret = vgpu_wpr_set_timeout(vf, 1000000000ULL); /* 1 second */ + if (ret != VGPU_OK) { + fprintf(stderr, "Failed to set WPR timeout: %s\n", vgpu_strerror(ret)); + } + + /* Schedule work */ + ret = vgpu_schedule(vf, handle, 0, 0, 0, 0); + if (ret != VGPU_OK) { + fprintf(stderr, "Failed to schedule: %s\n", vgpu_strerror(ret)); + } else { + printf("Work scheduled\n"); + } + + /* Run loop */ + printf("\nRunning... Press Ctrl+C to exit\n"); + while (running) { + ret = vgpu_process_events(device, 1000); + if (ret != VGPU_OK && ret != VGPU_ERR_TIMEOUT) { + fprintf(stderr, "Event processing error: %s\n", vgpu_strerror(ret)); + } + } + + printf("\nShutting down...\n"); + + /* Unprotect WPR */ + vgpu_wpr_unprotect(vf, va); + + /* Unpin */ + if (dma_addr) + vgpu_mem_unpin(vf, handle, 0, alloc_size); + + /* Unmap */ + vgpu_mem_unmap(vf, handle, va, alloc_size); + + /* Free memory */ + vgpu_mem_free(vf, handle); + + /* Destroy VF */ + vgpu_vf_destroy(vf); + + /* Close device */ + vgpu_close(device); + + printf("Done\n"); + return 0; +} \ No newline at end of file diff --git a/userspace/extern/inc/cargs.h b/userspace/extern/inc/cargs.h new file mode 100644 index 0000000..7d9dacd --- /dev/null +++ b/userspace/extern/inc/cargs.h @@ -0,0 +1,185 @@ +/* +MIT License + +Copyright (c) 2022 Leonard Iklé + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. + */ +#pragma once + +/** + * This is a simple alternative cross-platform implementation of getopt, which + * is used to parse argument strings submitted to the executable (argc and argv + * which are received in the main function). + */ + +#ifndef CAG_LIBRARY_H +#define CAG_LIBRARY_H + +#include +#include +#include + +#if defined(_WIN32) || defined(__CYGWIN__) +#define CAG_EXPORT __declspec(dllexport) +#define CAG_IMPORT __declspec(dllimport) +#elif __GNUC__ >= 4 +#define CAG_EXPORT __attribute__((visibility("default"))) +#define CAG_IMPORT __attribute__((visibility("default"))) +#else +#define CAG_EXPORT +#define CAG_IMPORT +#endif + +#if defined(CAG_SHARED) +#if defined(CAG_EXPORTS) +#define CAG_PUBLIC CAG_EXPORT +#else +#define CAG_PUBLIC CAG_IMPORT +#endif +#else +#define CAG_PUBLIC +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * An option is used to describe a flag/argument option submitted when the + * program is run. + */ +typedef struct cag_option +{ + const char identifier; + const char *access_letters; + const char *access_name; + const char *value_name; + const char *description; +} cag_option; + +/** + * A context is used to iterate over all options provided. It stores the parsing + * state. + */ +typedef struct cag_option_context +{ + const struct cag_option *options; + size_t option_count; + int argc; + char **argv; + int index; + int inner_index; + bool forced_end; + char identifier; + char *value; +} cag_option_context; + +/** + * This is just a small macro which calculates the size of an array. + */ +#define CAG_ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) + +/** + * @brief Prints all options to the terminal. + * + * This function prints all options to the terminal. This can be used to + * generate the output for a "--help" option. + * + * @param options The options which will be printed. + * @param option_count The option count which will be printed. + * @param destination The destination where the output will be printed. + */ +CAG_PUBLIC void cag_option_print(const cag_option *options, size_t option_count, + FILE *destination); + +/** + * @brief Prepare argument options context for parsing. + * + * This function prepares the context for iteration and initializes the context + * with the supplied options and arguments. After the context has been prepared, + * it can be used to fetch arguments from it. + * + * @param context The context which will be initialized. + * @param options The registered options which are available for the program. + * @param option_count The amount of options which are available for the + * program. + * @param argc The amount of arguments the user supplied in the main function. + * @param argv A pointer to the arguments of the main function. + */ +CAG_PUBLIC void cag_option_prepare(cag_option_context *context, + const cag_option *options, size_t option_count, int argc, char **argv); + +/** + * @brief Fetches an option from the argument list. + * + * This function fetches a single option from the argument list. The context + * will be moved to that item. Information can be extracted from the context + * after the item has been fetched. + * The arguments will be re-ordered, which means that non-option arguments will + * be moved to the end of the argument list. After all options have been + * fetched, all non-option arguments will be positioned after the index of + * the context. + * + * @param context The context from which we will fetch the option. + * @return Returns true if there was another option or false if the end is + * reached. + */ +CAG_PUBLIC bool cag_option_fetch(cag_option_context *context); + +/** + * @brief Gets the identifier of the option. + * + * This function gets the identifier of the option, which should be unique to + * this option and can be used to determine what kind of option this is. + * + * @param context The context from which the option was fetched. + * @return Returns the identifier of the option. + */ +CAG_PUBLIC char cag_option_get(const cag_option_context *context); + +/** + * @brief Gets the value from the option. + * + * This function gets the value from the option, if any. If the option does not + * contain a value, this function will return NULL. + * + * @param context The context from which the option was fetched. + * @return Returns a pointer to the value or NULL if there is no value. + */ +CAG_PUBLIC const char *cag_option_get_value(const cag_option_context *context); + +/** + * @brief Gets the current index of the context. + * + * This function gets the index within the argv arguments of the context. The + * context always points to the next item which it will inspect. This is + * particularly useful to inspect the original argument array, or to get + * non-option arguments after option fetching has finished. + * + * @param context The context from which the option was fetched. + * @return Returns the current index of the context. + */ +CAG_PUBLIC int cag_option_get_index(const cag_option_context *context); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/userspace/extern/inc/toml.h b/userspace/extern/inc/toml.h new file mode 100644 index 0000000..19dc3d2 --- /dev/null +++ b/userspace/extern/inc/toml.h @@ -0,0 +1,175 @@ +/* + MIT License + + Copyright (c) CK Tan + https://github.com/cktan/tomlc99 + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ +#ifndef TOML_H +#define TOML_H + +#ifdef _MSC_VER +#pragma warning(disable: 4996) +#endif + +#include +#include + +#ifdef __cplusplus +#define TOML_EXTERN extern "C" +#else +#define TOML_EXTERN extern +#endif + +typedef struct toml_timestamp_t toml_timestamp_t; +typedef struct toml_table_t toml_table_t; +typedef struct toml_array_t toml_array_t; +typedef struct toml_datum_t toml_datum_t; + +/* Parse a file. Return a table on success, or 0 otherwise. + * Caller must toml_free(the-return-value) after use. + */ +TOML_EXTERN toml_table_t *toml_parse_file(FILE *fp, char *errbuf, int errbufsz); + +/* Parse a string containing the full config. + * Return a table on success, or 0 otherwise. + * Caller must toml_free(the-return-value) after use. + */ +TOML_EXTERN toml_table_t *toml_parse(char *conf, /* NUL terminated, please. */ + char *errbuf, int errbufsz); + +/* Free the table returned by toml_parse() or toml_parse_file(). Once + * this function is called, any handles accessed through this tab + * directly or indirectly are no longer valid. + */ +TOML_EXTERN void toml_free(toml_table_t *tab); + +/* Timestamp types. The year, month, day, hour, minute, second, z + * fields may be NULL if they are not relevant. e.g. In a DATE + * type, the hour, minute, second and z fields will be NULLs. + */ +struct toml_timestamp_t { + struct { /* internal. do not use. */ + int year, month, day; + int hour, minute, second, millisec; + char z[10]; + } __buffer; + int *year, *month, *day; + int *hour, *minute, *second, *millisec; + char *z; +}; + +/*----------------------------------------------------------------- + * Enhanced access methods + */ +struct toml_datum_t { + int ok; + union { + toml_timestamp_t *ts; /* ts must be freed after use */ + char *s; /* string value. s must be freed after use */ + int b; /* bool value */ + int64_t i; /* int value */ + double d; /* double value */ + } u; +}; + +/* on arrays: */ +/* ... retrieve size of array. */ +TOML_EXTERN int toml_array_nelem(const toml_array_t *arr); +/* ... retrieve values using index. */ +TOML_EXTERN toml_datum_t toml_string_at(const toml_array_t *arr, int idx); +TOML_EXTERN toml_datum_t toml_bool_at(const toml_array_t *arr, int idx); +TOML_EXTERN toml_datum_t toml_int_at(const toml_array_t *arr, int idx); +TOML_EXTERN toml_datum_t toml_double_at(const toml_array_t *arr, int idx); +TOML_EXTERN toml_datum_t toml_timestamp_at(const toml_array_t *arr, int idx); +/* ... retrieve array or table using index. */ +TOML_EXTERN toml_array_t *toml_array_at(const toml_array_t *arr, int idx); +TOML_EXTERN toml_table_t *toml_table_at(const toml_array_t *arr, int idx); + +/* on tables: */ +/* ... retrieve the key in table at keyidx. Return 0 if out of range. */ +TOML_EXTERN const char *toml_key_in(const toml_table_t *tab, int keyidx); +/* ... returns 1 if key exists in tab, 0 otherwise */ +TOML_EXTERN int toml_key_exists(const toml_table_t *tab, const char *key); +/* ... retrieve values using key. */ +TOML_EXTERN toml_datum_t toml_string_in(const toml_table_t *arr, + const char *key); +TOML_EXTERN toml_datum_t toml_bool_in(const toml_table_t *arr, const char *key); +TOML_EXTERN toml_datum_t toml_int_in(const toml_table_t *arr, const char *key); +TOML_EXTERN toml_datum_t toml_double_in(const toml_table_t *arr, + const char *key); +TOML_EXTERN toml_datum_t toml_timestamp_in(const toml_table_t *arr, + const char *key); +/* .. retrieve array or table using key. */ +TOML_EXTERN toml_array_t *toml_array_in(const toml_table_t *tab, + const char *key); +TOML_EXTERN toml_table_t *toml_table_in(const toml_table_t *tab, + const char *key); + +/*----------------------------------------------------------------- + * lesser used + */ +/* Return the array kind: 't'able, 'a'rray, 'v'alue, 'm'ixed */ +TOML_EXTERN char toml_array_kind(const toml_array_t *arr); + +/* For array kind 'v'alue, return the type of values + i:int, d:double, b:bool, s:string, t:time, D:date, T:timestamp, 'm'ixed + 0 if unknown +*/ +TOML_EXTERN char toml_array_type(const toml_array_t *arr); + +/* Return the key of an array */ +TOML_EXTERN const char *toml_array_key(const toml_array_t *arr); + +/* Return the number of key-values in a table */ +TOML_EXTERN int toml_table_nkval(const toml_table_t *tab); + +/* Return the number of arrays in a table */ +TOML_EXTERN int toml_table_narr(const toml_table_t *tab); + +/* Return the number of sub-tables in a table */ +TOML_EXTERN int toml_table_ntab(const toml_table_t *tab); + +/* Return the key of a table*/ +TOML_EXTERN const char *toml_table_key(const toml_table_t *tab); + +/*-------------------------------------------------------------- + * misc + */ +TOML_EXTERN int toml_utf8_to_ucs(const char *orig, int len, int64_t *ret); +TOML_EXTERN int toml_ucs_to_utf8(int64_t code, char buf[6]); +TOML_EXTERN void toml_set_memutil(void *(*xxmalloc)(size_t), + void (*xxfree)(void *)); + +/*-------------------------------------------------------------- + * deprecated + */ +/* A raw value, must be processed by toml_rto* before using. */ +typedef const char *toml_raw_t; +TOML_EXTERN toml_raw_t toml_raw_in(const toml_table_t *tab, const char *key); +TOML_EXTERN toml_raw_t toml_raw_at(const toml_array_t *arr, int idx); +TOML_EXTERN int toml_rtos(toml_raw_t s, char **ret); +TOML_EXTERN int toml_rtob(toml_raw_t s, int *ret); +TOML_EXTERN int toml_rtoi(toml_raw_t s, int64_t *ret); +TOML_EXTERN int toml_rtod(toml_raw_t s, double *ret); +TOML_EXTERN int toml_rtod_ex(toml_raw_t s, double *ret, char *buf, int buflen); +TOML_EXTERN int toml_rtots(toml_raw_t s, toml_timestamp_t *ret); + +#endif /* TOML_H */ diff --git a/userspace/extern/src/cargs.c b/userspace/extern/src/cargs.c new file mode 100644 index 0000000..4f95e18 --- /dev/null +++ b/userspace/extern/src/cargs.c @@ -0,0 +1,460 @@ +/* +MIT License + +Copyright (c) 2022 Leonard Iklé + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. + */ +#include +#include +#include +#include +#include + +#define CAG_OPTION_PRINT_DISTANCE 4 +#define CAG_OPTION_PRINT_MIN_INDENTION 20 + +static void cag_option_print_value(const cag_option *option, + size_t *accessor_length, FILE *destination) +{ + if (option->value_name != NULL) { + *accessor_length += fprintf(destination, "=%s", option->value_name); + } +} + +static void cag_option_print_letters(const cag_option *option, bool *first, + size_t *accessor_length, FILE *destination) +{ + const char *access_letter; + access_letter = option->access_letters; + if (access_letter != NULL) { + while (*access_letter) { + if (*first) { + *accessor_length += fprintf(destination, "-%c", *access_letter); + *first = false; + } else { + *accessor_length += fprintf(destination, ", -%c", *access_letter); + } + ++access_letter; + } + } +} + +static void cag_option_print_name(const cag_option *option, bool *first, + size_t *accessor_length, FILE *destination) +{ + if (option->access_name != NULL) { + if (*first) { + *accessor_length += fprintf(destination, "--%s", option->access_name); + } else { + *accessor_length += fprintf(destination, ", --%s", option->access_name); + } + } +} + +static size_t cag_option_get_print_indention(const cag_option *options, + size_t option_count) +{ + size_t option_index, indention, result; + const cag_option *option; + + result = CAG_OPTION_PRINT_MIN_INDENTION; + + for (option_index = 0; option_index < option_count; ++option_index) { + indention = CAG_OPTION_PRINT_DISTANCE; + option = &options[option_index]; + if (option->access_letters != NULL && *option->access_letters) { + indention += strlen(option->access_letters) * 4 - 2; + if (option->access_name != NULL) { + indention += strlen(option->access_name) + 4; + } + } else if (option->access_name != NULL) { + indention += strlen(option->access_name) + 2; + } + + if (option->value_name != NULL) { + indention += strlen(option->value_name) + 1; + } + + if (indention > result) { + result = indention; + } + } + + return result; +} + +void cag_option_print(const cag_option *options, size_t option_count, + FILE *destination) +{ + size_t option_index, indention, i, accessor_length; + const cag_option *option; + bool first; + + indention = cag_option_get_print_indention(options, option_count); + + for (option_index = 0; option_index < option_count; ++option_index) { + option = &options[option_index]; + accessor_length = 0; + first = true; + + fputs(" ", destination); + + cag_option_print_letters(option, &first, &accessor_length, destination); + cag_option_print_name(option, &first, &accessor_length, destination); + cag_option_print_value(option, &accessor_length, destination); + + for (i = accessor_length; i < indention; ++i) { + fputs(" ", destination); + } + + fputs(" ", destination); + fputs(option->description, destination); + + fprintf(destination, "\n"); + } +} + +void cag_option_prepare(cag_option_context *context, const cag_option *options, + size_t option_count, int argc, char **argv) +{ + // This just initialized the values to the beginning of all the arguments. + context->options = options; + context->option_count = option_count; + context->argc = argc; + context->argv = argv; + context->index = 1; + context->inner_index = 0; + context->forced_end = false; +} + +static const cag_option *cag_option_find_by_name(cag_option_context *context, + char *name, size_t name_size) +{ + const cag_option *option; + size_t i; + + // We loop over all the available options and stop as soon as we have found + // one. We don't use any hash map table, since there won't be that many + // arguments anyway. + for (i = 0; i < context->option_count; ++i) { + option = &context->options[i]; + + // The option might not have an item name, we can just skip those. + if (option->access_name == NULL) { + continue; + } + + // Try to compare the name of the access name. We can use the name_size or + // this comparison, since we are guaranteed to have null-terminated access + // names. + if (strncmp(option->access_name, name, name_size) == 0) { + return option; + } + } + + return NULL; +} + +static const cag_option *cag_option_find_by_letter(cag_option_context *context, + char letter) +{ + const cag_option *option; + size_t i; + + // We loop over all the available options and stop as soon as we have found + // one. We don't use any look up table, since there won't be that many + // arguments anyway. + for (i = 0; i < context->option_count; ++i) { + option = &context->options[i]; + + // If this option doesn't have any access letters we will skip them. + if (option->access_letters == NULL) { + continue; + } + + // Verify whether this option has the access letter in it's access letter + // string. If it does, then this is our option. + if (strchr(option->access_letters, letter) != NULL) { + return option; + } + } + + return NULL; +} + +static void cag_option_parse_value(cag_option_context *context, + const cag_option *option, char **c) +{ + // And now let's check whether this option is supposed to have a value, which + // is the case if there is a value name set. The value can be either submitted + // with a '=' sign or a space, which means we would have to jump over to the + // next argv index. This is somewhat ugly, but we do it to behave the same as + // the other option parsers. + if (option->value_name != NULL) { + if (**c == '=') { + context->value = ++(*c); + } else { + // If the next index is larger or equal to the argument count, then the + // parameter for this option is missing. The user will know about this, + // since the value pointer of the context will be NULL because we don't + // set it here in that case. + if (context->argc > context->index + 1) { + // We consider this argv to be the value, no matter what the contents + // are. + ++context->index; + *c = context->argv[context->index]; + context->value = *c; + } + } + + // Move c to the end of the value, to not confuse the caller about our + // position. + while (**c) { + ++(*c); + } + } +} + +static void cag_option_parse_access_name(cag_option_context *context, char **c) +{ + const cag_option *option; + char *n; + + // Now we need to extract the access name, which is any symbol up to a '=' or + // a '\0'. + n = *c; + while (**c && **c != '=') { + ++*c; + } + + // Now this will obviously always be true, but we are paranoid. Sometimes. It + // doesn't hurt to check. + assert(*c >= n); + + // Figure out which option this name belongs to. This might return NULL if the + // name is not registered, which means the user supplied an unknown option. In + // that case we return true to indicate that we finished with this option. We + // have to skip the value parsing since we don't know whether the user thinks + // this option has one or not. Since we don't set any identifier specifically, + // it will remain '?' within the context. + option = cag_option_find_by_name(context, n, (size_t)(*c - n)); + if (option == NULL) { + // Since this option is invalid, we will move on to the next index. There is + // nothing we can do about this. + ++context->index; + return; + } + + // We found an option and now we can specify the identifier within the + // context. + context->identifier = option->identifier; + + // And now we try to parse the value. This function will also check whether + // this option is actually supposed to have a value. + cag_option_parse_value(context, option, c); + + // And finally we move on to the next index. + ++context->index; +} + +static void cag_option_parse_access_letter(cag_option_context *context, + char **c) +{ + const cag_option *option; + char *n = *c; + char *v; + + // Figure out which option this letter belongs to. This might return NULL if + // the letter is not registered, which means the user supplied an unknown + // option. In that case we return true to indicate that we finished with this + // option. We have to skip the value parsing since we don't know whether the + // user thinks this option has one or not. Since we don't set any identifier + // specifically, it will remain '?' within the context. + option = cag_option_find_by_letter(context, n[context->inner_index]); + if (option == NULL) { + ++context->index; + context->inner_index = 0; + return; + } + + // We found an option and now we can specify the identifier within the + // context. + context->identifier = option->identifier; + + // And now we try to parse the value. This function will also check whether + // this option is actually supposed to have a value. + v = &n[++context->inner_index]; + cag_option_parse_value(context, option, &v); + + // Check whether we reached the end of this option argument. + if (*v == '\0') { + ++context->index; + context->inner_index = 0; + } +} + +static void cag_option_shift(cag_option_context *context, int start, int option, + int end) +{ + char *tmp; + int a_index, shift_index, shift_count, left_index, right_index; + + shift_count = option - start; + + // There is no shift is required if the start and the option have the same + // index. + if (shift_count == 0) { + return; + } + + // Lets loop through the option strings first, which we will move towards the + // beginning. + for (a_index = option; a_index < end; ++a_index) { + // First remember the current option value, because we will have to save + // that later at the beginning. + tmp = context->argv[a_index]; + + // Let's loop over all option values and shift them one towards the end. + // This will override the option value we just stored temporarily. + for (shift_index = 0; shift_index < shift_count; ++shift_index) { + left_index = a_index - shift_index; + right_index = a_index - shift_index - 1; + context->argv[left_index] = context->argv[right_index]; + } + + // Now restore the saved option value at the beginning. + context->argv[a_index - shift_count] = tmp; + } + + // The new index will be before all non-option values, in such a way that they + // all will be moved again in the next fetch call. + context->index = end - shift_count; +} + +static bool cag_option_is_argument_string(const char *c) +{ + return *c == '-' && *(c + 1) != '\0'; +} + +static int cag_option_find_next(cag_option_context *context) +{ + int next_index, next_option_index; + char *c; + + // Prepare to search the next option at the next index. + next_index = context->index; + next_option_index = next_index; + + // Grab a pointer to the string and verify that it is not the end. If it is + // the end, we have to return false to indicate that we finished. + c = context->argv[next_option_index]; + if (context->forced_end || c == NULL) { + return -1; + } + + // Check whether it is a '-'. We need to find the next option - and an option + // always starts with a '-'. If there is a string "-\0", we don't consider it + // as an option neither. + while (!cag_option_is_argument_string(c)) { + c = context->argv[++next_option_index]; + if (c == NULL) { + // We reached the end and did not find any argument anymore. Let's tell + // our caller that we reached the end. + return -1; + } + } + + // Indicate that we found an option which can be processed. The index of the + // next option will be returned. + return next_option_index; +} + +bool cag_option_fetch(cag_option_context *context) +{ + char *c; + int old_index, new_index; + + // Reset our identifier to a question mark, which indicates an "unknown" + // option. The value is set to NULL, to make sure we are not carrying the + // parameter from the previous option to this one. + context->identifier = '?'; + context->value = NULL; + + // Check whether there are any options left to parse and remember the old + // index as well as the new index. In the end we will move the option junk to + // the beginning, so that non option arguments can be read. + old_index = context->index; + new_index = cag_option_find_next(context); + if (new_index >= 0) { + context->index = new_index; + } else { + return false; + } + + // Grab a pointer to the beginning of the option. At this point, the next + // character must be a '-', since if it was not the prepare function would + // have returned false. We will skip that symbol and proceed. + c = context->argv[context->index]; + assert(*c == '-'); + ++c; + + // Check whether this is a long option, starting with a double "--". + if (*c == '-') { + ++c; + + // This might be a double "--" which indicates the end of options. If this + // is the case, we will not move to the next index. That ensures that + // another call to the fetch function will not skip the "--". + if (*c == '\0') { + context->forced_end = true; + } else { + // We parse now the access name. All information about it will be written + // to the context. + cag_option_parse_access_name(context, &c); + } + } else { + // This is no long option, so we can just parse an access letter. + cag_option_parse_access_letter(context, &c); + } + + // Move the items so that the options come first followed by non-option + // arguments. + cag_option_shift(context, old_index, new_index, context->index); + + return context->forced_end == false; +} + +char cag_option_get(const cag_option_context *context) +{ + // We just return the identifier here. + return context->identifier; +} + +const char *cag_option_get_value(const cag_option_context *context) +{ + // We just return the internal value pointer of the context. + return context->value; +} + +int cag_option_get_index(const cag_option_context *context) +{ + // Either we point to a value item, + return context->index; +} diff --git a/userspace/extern/src/toml.c b/userspace/extern/src/toml.c new file mode 100644 index 0000000..2f4dc03 --- /dev/null +++ b/userspace/extern/src/toml.c @@ -0,0 +1,2379 @@ +/* + + MIT License + + Copyright (c) CK Tan + https://github.com/cktan/tomlc99 + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. + +*/ +#define _POSIX_C_SOURCE 200809L +#include "toml.h" +#include +#include +#include +#include +#include +#include +#include +#include + +static void *(*ppmalloc)(size_t) = malloc; +static void (*ppfree)(void *) = free; + +void toml_set_memutil(void *(*xxmalloc)(size_t), void (*xxfree)(void *)) { + if (xxmalloc) + ppmalloc = xxmalloc; + if (xxfree) + ppfree = xxfree; +} + +#define MALLOC(a) ppmalloc(a) +#define FREE(a) ppfree(a) + +#define malloc(x) error - forbidden - use MALLOC instead +#define free(x) error - forbidden - use FREE instead +#define calloc(x, y) error - forbidden - use CALLOC instead + +static void *CALLOC(size_t nmemb, size_t sz) { + int nb = sz * nmemb; + void *p = MALLOC(nb); + if (p) { + memset(p, 0, nb); + } + return p; +} + +// some old platforms define strdup macro -- drop it. +#undef strdup +#define strdup(x) error - forbidden - use STRDUP instead + +static char *STRDUP(const char *s) { + int len = strlen(s); + char *p = MALLOC(len + 1); + if (p) { + memcpy(p, s, len); + p[len] = 0; + } + return p; +} + +// some old platforms define strndup macro -- drop it. +#undef strndup +#define strndup(x) error - forbiden - use STRNDUP instead + +static char *STRNDUP(const char *s, size_t n) { + size_t len = strnlen(s, n); + char *p = MALLOC(len + 1); + if (p) { + memcpy(p, s, len); + p[len] = 0; + } + return p; +} + +/** + * Convert a char in utf8 into UCS, and store it in *ret. + * Return #bytes consumed or -1 on failure. + */ +int toml_utf8_to_ucs(const char *orig, int len, int64_t *ret) { + const unsigned char *buf = (const unsigned char *)orig; + unsigned i = *buf++; + int64_t v; + + /* 0x00000000 - 0x0000007F: + 0xxxxxxx + */ + if (0 == (i >> 7)) { + if (len < 1) + return -1; + v = i; + return *ret = v, 1; + } + /* 0x00000080 - 0x000007FF: + 110xxxxx 10xxxxxx + */ + if (0x6 == (i >> 5)) { + if (len < 2) + return -1; + v = i & 0x1f; + for (int j = 0; j < 1; j++) { + i = *buf++; + if (0x2 != (i >> 6)) + return -1; + v = (v << 6) | (i & 0x3f); + } + return *ret = v, (const char *)buf - orig; + } + + /* 0x00000800 - 0x0000FFFF: + 1110xxxx 10xxxxxx 10xxxxxx + */ + if (0xE == (i >> 4)) { + if (len < 3) + return -1; + v = i & 0x0F; + for (int j = 0; j < 2; j++) { + i = *buf++; + if (0x2 != (i >> 6)) + return -1; + v = (v << 6) | (i & 0x3f); + } + return *ret = v, (const char *)buf - orig; + } + + /* 0x00010000 - 0x001FFFFF: + 11110xxx 10xxxxxx 10xxxxxx 10xxxxxx + */ + if (0x1E == (i >> 3)) { + if (len < 4) + return -1; + v = i & 0x07; + for (int j = 0; j < 3; j++) { + i = *buf++; + if (0x2 != (i >> 6)) + return -1; + v = (v << 6) | (i & 0x3f); + } + return *ret = v, (const char *)buf - orig; + } + + /* 0x00200000 - 0x03FFFFFF: + 111110xx 10xxxxxx 10xxxxxx 10xxxxxx 10xxxxxx + */ + if (0x3E == (i >> 2)) { + if (len < 5) + return -1; + v = i & 0x03; + for (int j = 0; j < 4; j++) { + i = *buf++; + if (0x2 != (i >> 6)) + return -1; + v = (v << 6) | (i & 0x3f); + } + return *ret = v, (const char *)buf - orig; + } + + /* 0x04000000 - 0x7FFFFFFF: + 1111110x 10xxxxxx 10xxxxxx 10xxxxxx 10xxxxxx 10xxxxxx + */ + if (0x7e == (i >> 1)) { + if (len < 6) + return -1; + v = i & 0x01; + for (int j = 0; j < 5; j++) { + i = *buf++; + if (0x2 != (i >> 6)) + return -1; + v = (v << 6) | (i & 0x3f); + } + return *ret = v, (const char *)buf - orig; + } + return -1; +} + +/** + * Convert a UCS char to utf8 code, and return it in buf. + * Return #bytes used in buf to encode the char, or + * -1 on error. + */ +int toml_ucs_to_utf8(int64_t code, char buf[6]) { + /* http://stackoverflow.com/questions/6240055/manually-converting-unicode-codepoints-into-utf-8-and-utf-16 + */ + /* The UCS code values 0xd800–0xdfff (UTF-16 surrogates) as well + * as 0xfffe and 0xffff (UCS noncharacters) should not appear in + * conforming UTF-8 streams. + */ + if (0xd800 <= code && code <= 0xdfff) + return -1; + if (0xfffe <= code && code <= 0xffff) + return -1; + + /* 0x00000000 - 0x0000007F: + 0xxxxxxx + */ + if (code < 0) + return -1; + if (code <= 0x7F) { + buf[0] = (unsigned char)code; + return 1; + } + + /* 0x00000080 - 0x000007FF: + 110xxxxx 10xxxxxx + */ + if (code <= 0x000007FF) { + buf[0] = (unsigned char) (0xc0 | (code >> 6)); + buf[1] = (unsigned char) (0x80 | (code & 0x3f)); + return 2; + } + + /* 0x00000800 - 0x0000FFFF: + 1110xxxx 10xxxxxx 10xxxxxx + */ + if (code <= 0x0000FFFF) { + buf[0] = (unsigned char) (0xe0 | (code >> 12)); + buf[1] = (unsigned char) (0x80 | ((code >> 6) & 0x3f)); + buf[2] = (unsigned char) (0x80 | (code & 0x3f)); + return 3; + } + + /* 0x00010000 - 0x001FFFFF: + 11110xxx 10xxxxxx 10xxxxxx 10xxxxxx + */ + if (code <= 0x001FFFFF) { + buf[0] = (unsigned char) (0xf0 | (code >> 18)); + buf[1] = (unsigned char) (0x80 | ((code >> 12) & 0x3f)); + buf[2] = (unsigned char) (0x80 | ((code >> 6) & 0x3f)); + buf[3] = (unsigned char) (0x80 | (code & 0x3f)); + return 4; + } + + /* 0x00200000 - 0x03FFFFFF: + 111110xx 10xxxxxx 10xxxxxx 10xxxxxx 10xxxxxx + */ + if (code <= 0x03FFFFFF) { + buf[0] = (unsigned char) (0xf8 | (code >> 24)); + buf[1] = (unsigned char) (0x80 | ((code >> 18) & 0x3f)); + buf[2] = (unsigned char) (0x80 | ((code >> 12) & 0x3f)); + buf[3] = (unsigned char) (0x80 | ((code >> 6) & 0x3f)); + buf[4] = (unsigned char) (0x80 | (code & 0x3f)); + return 5; + } + + /* 0x04000000 - 0x7FFFFFFF: + 1111110x 10xxxxxx 10xxxxxx 10xxxxxx 10xxxxxx 10xxxxxx + */ + if (code <= 0x7FFFFFFF) { + buf[0] = (unsigned char) (0xfc | (code >> 30)); + buf[1] = (unsigned char) (0x80 | ((code >> 24) & 0x3f)); + buf[2] = (unsigned char) (0x80 | ((code >> 18) & 0x3f)); + buf[3] = (unsigned char) (0x80 | ((code >> 12) & 0x3f)); + buf[4] = (unsigned char) (0x80 | ((code >> 6) & 0x3f)); + buf[5] = (unsigned char) (0x80 | (code & 0x3f)); + return 6; + } + + return -1; +} + +/* + * TOML has 3 data structures: value, array, table. + * Each of them can have identification key. + */ +typedef struct toml_keyval_t toml_keyval_t; +struct toml_keyval_t { + const char *key; /* key to this value */ + const char *val; /* the raw value */ +}; + +typedef struct toml_arritem_t toml_arritem_t; +struct toml_arritem_t { + int valtype; /* for value kind: 'i'nt, 'd'ouble, 'b'ool, 's'tring, 't'ime, + 'D'ate, 'T'imestamp */ + char *val; + toml_array_t *arr; + toml_table_t *tab; +}; + +struct toml_array_t { + const char *key; /* key to this array */ + int kind; /* element kind: 'v'alue, 'a'rray, or 't'able, 'm'ixed */ + int type; /* for value kind: 'i'nt, 'd'ouble, 'b'ool, 's'tring, 't'ime, + 'D'ate, 'T'imestamp, 'm'ixed */ + + int nitem; /* number of elements */ + toml_arritem_t *item; +}; + +struct toml_table_t { + const char *key; /* key to this table */ + bool implicit; /* table was created implicitly */ + bool readonly; /* no more modification allowed */ + + /* key-values in the table */ + int nkval; + toml_keyval_t **kval; + + /* arrays in the table */ + int narr; + toml_array_t **arr; + + /* tables in the table */ + int ntab; + toml_table_t **tab; +}; + +static inline void xfree(const void *x) { + if (x) + FREE((void *)(intptr_t)x); +} + +enum tokentype_t { + INVALID, + DOT, + COMMA, + EQUAL, + LBRACE, + RBRACE, + NEWLINE, + LBRACKET, + RBRACKET, + STRING, +}; +typedef enum tokentype_t tokentype_t; + +typedef struct token_t token_t; +struct token_t { + tokentype_t tok; + int lineno; + char *ptr; /* points into context->start */ + int len; + int eof; +}; + +typedef struct context_t context_t; +struct context_t { + char *start; + char *stop; + char *errbuf; + int errbufsz; + + token_t tok; + toml_table_t *root; + toml_table_t *curtab; + + struct { + int top; + char *key[10]; + token_t tok[10]; + } tpath; +}; + +#define STRINGIFY(x) #x +#define TOSTRING(x) STRINGIFY(x) +#define FLINE __FILE__ ":" TOSTRING(__LINE__) + +static int next_token(context_t *ctx, int dotisspecial); + +/* + Error reporting. Call when an error is detected. Always return -1. +*/ +static int e_outofmemory(context_t *ctx, const char *fline) { + snprintf(ctx->errbuf, ctx->errbufsz, "ERROR: out of memory (%s)", fline); + return -1; +} + +static int e_internal(context_t *ctx, const char *fline) { + snprintf(ctx->errbuf, ctx->errbufsz, "internal error (%s)", fline); + return -1; +} + +static int e_syntax(context_t *ctx, int lineno, const char *msg) { + snprintf(ctx->errbuf, ctx->errbufsz, "line %d: %s", lineno, msg); + return -1; +} + +static int e_badkey(context_t *ctx, int lineno) { + snprintf(ctx->errbuf, ctx->errbufsz, "line %d: bad key", lineno); + return -1; +} + +static int e_keyexists(context_t *ctx, int lineno) { + snprintf(ctx->errbuf, ctx->errbufsz, "line %d: key exists", lineno); + return -1; +} + +static int e_forbid(context_t *ctx, int lineno, const char *msg) { + snprintf(ctx->errbuf, ctx->errbufsz, "line %d: %s", lineno, msg); + return -1; +} + +static void *expand(void *p, int sz, int newsz) { + void *s = MALLOC(newsz); + if (!s) + return 0; + + memcpy(s, p, sz); + FREE(p); + return s; +} + +static void **expand_ptrarr(void **p, int n) { + void **s = MALLOC((n + 1) * sizeof(void *)); + if (!s) + return 0; + + s[n] = 0; + memcpy(s, p, n * sizeof(void *)); + FREE(p); + return s; +} + +static toml_arritem_t *expand_arritem(toml_arritem_t *p, int n) { + toml_arritem_t *pp = expand(p, n * sizeof(*p), (n + 1) * sizeof(*p)); + if (!pp) + return 0; + + memset(&pp[n], 0, sizeof(pp[n])); + return pp; +} + +static char *norm_lit_str(const char *src, int srclen, int multiline, + char *errbuf, int errbufsz) { + char *dst = 0; /* will write to dst[] and return it */ + int max = 0; /* max size of dst[] */ + int off = 0; /* cur offset in dst[] */ + const char *sp = src; + const char *sq = src + srclen; + int ch; + + /* scan forward on src */ + for (;;) { + if (off >= max - 10) { /* have some slack for misc stuff */ + int newmax = max + 50; + char *x = expand(dst, max, newmax); + if (!x) { + xfree(dst); + snprintf(errbuf, errbufsz, "out of memory"); + return 0; + } + dst = x; + max = newmax; + } + + /* finished? */ + if (sp >= sq) + break; + + ch = *sp++; + /* control characters other than tab is not allowed */ + if ((0 <= ch && ch <= 0x08) || (0x0a <= ch && ch <= 0x1f) || (ch == 0x7f)) { + if (!(multiline && (ch == '\r' || ch == '\n'))) { + xfree(dst); + snprintf(errbuf, errbufsz, "invalid char U+%04x", ch); + return 0; + } + } + + // a plain copy suffice + dst[off++] = ch; + } + + dst[off++] = 0; + return dst; +} + +/* + * Convert src to raw unescaped utf-8 string. + * Returns NULL if error with errmsg in errbuf. + */ +static char *norm_basic_str(const char *src, int srclen, int multiline, + char *errbuf, int errbufsz) { + char *dst = 0; /* will write to dst[] and return it */ + int max = 0; /* max size of dst[] */ + int off = 0; /* cur offset in dst[] */ + const char *sp = src; + const char *sq = src + srclen; + int ch; + + /* scan forward on src */ + for (;;) { + if (off >= max - 10) { /* have some slack for misc stuff */ + int newmax = max + 50; + char *x = expand(dst, max, newmax); + if (!x) { + xfree(dst); + snprintf(errbuf, errbufsz, "out of memory"); + return 0; + } + dst = x; + max = newmax; + } + + /* finished? */ + if (sp >= sq) + break; + + ch = *sp++; + if (ch != '\\') { + /* these chars must be escaped: U+0000 to U+0008, U+000A to U+001F, U+007F + */ + if ((0 <= ch && ch <= 0x08) || (0x0a <= ch && ch <= 0x1f) || + (ch == 0x7f)) { + if (!(multiline && (ch == '\r' || ch == '\n'))) { + xfree(dst); + snprintf(errbuf, errbufsz, "invalid char U+%04x", ch); + return 0; + } + } + + // a plain copy suffice + dst[off++] = ch; + continue; + } + + /* ch was backslash. we expect the escape char. */ + if (sp >= sq) { + snprintf(errbuf, errbufsz, "last backslash is invalid"); + xfree(dst); + return 0; + } + + /* for multi-line, we want to kill line-ending-backslash ... */ + if (multiline) { + + // if there is only whitespace after the backslash ... + if (sp[strspn(sp, " \t\r")] == '\n') { + /* skip all the following whitespaces */ + sp += strspn(sp, " \t\r\n"); + continue; + } + } + + /* get the escaped char */ + ch = *sp++; + switch (ch) { + case 'u': + case 'U': { + int64_t ucs = 0; + int nhex = (ch == 'u' ? 4 : 8); + for (int i = 0; i < nhex; i++) { + if (sp >= sq) { + snprintf(errbuf, errbufsz, "\\%c expects %d hex chars", ch, nhex); + xfree(dst); + return 0; + } + ch = *sp++; + int v = ('0' <= ch && ch <= '9') + ? ch - '0' + : (('A' <= ch && ch <= 'F') ? ch - 'A' + 10 : -1); + if (-1 == v) { + snprintf(errbuf, errbufsz, "invalid hex chars for \\u or \\U"); + xfree(dst); + return 0; + } + ucs = ucs * 16 + v; + } + int n = toml_ucs_to_utf8(ucs, &dst[off]); + if (-1 == n) { + snprintf(errbuf, errbufsz, "illegal ucs code in \\u or \\U"); + xfree(dst); + return 0; + } + off += n; + } + continue; + + case 'b': + ch = '\b'; + break; + case 't': + ch = '\t'; + break; + case 'n': + ch = '\n'; + break; + case 'f': + ch = '\f'; + break; + case 'r': + ch = '\r'; + break; + case '"': + ch = '"'; + break; + case '\\': + ch = '\\'; + break; + default: + snprintf(errbuf, errbufsz, "illegal escape char \\%c", ch); + xfree(dst); + return 0; + } + + dst[off++] = ch; + } + + // Cap with NUL and return it. + dst[off++] = 0; + return dst; +} + +/* Normalize a key. Convert all special chars to raw unescaped utf-8 chars. */ +static char *normalize_key(context_t *ctx, token_t strtok) { + const char *sp = strtok.ptr; + const char *sq = strtok.ptr + strtok.len; + int lineno = strtok.lineno; + char *ret; + int ch = *sp; + char ebuf[80]; + + /* handle quoted string */ + if (ch == '\'' || ch == '\"') { + /* if ''' or """, take 3 chars off front and back. Else, take 1 char off. */ + int multiline = 0; + if (sp[1] == ch && sp[2] == ch) { + sp += 3, sq -= 3; + multiline = 1; + } else + sp++, sq--; + + if (ch == '\'') { + /* for single quote, take it verbatim. */ + if (!(ret = STRNDUP(sp, sq - sp))) { + e_outofmemory(ctx, FLINE); + return 0; + } + } else { + /* for double quote, we need to normalize */ + ret = norm_basic_str(sp, sq - sp, multiline, ebuf, sizeof(ebuf)); + if (!ret) { + e_syntax(ctx, lineno, ebuf); + return 0; + } + } + + /* newlines are not allowed in keys */ + if (strchr(ret, '\n')) { + xfree(ret); + e_badkey(ctx, lineno); + return 0; + } + return ret; + } + + /* for bare-key allow only this regex: [A-Za-z0-9_-]+ */ + const char *xp; + for (xp = sp; xp != sq; xp++) { + int k = *xp; + if (isalnum(k)) + continue; + if (k == '_' || k == '-') + continue; + e_badkey(ctx, lineno); + return 0; + } + + /* dup and return it */ + if (!(ret = STRNDUP(sp, sq - sp))) { + e_outofmemory(ctx, FLINE); + return 0; + } + return ret; +} + +/* + * Look up key in tab. Return 0 if not found, or + * 'v'alue, 'a'rray or 't'able depending on the element. + */ +static int check_key(toml_table_t *tab, const char *key, + toml_keyval_t **ret_val, toml_array_t **ret_arr, + toml_table_t **ret_tab) { + int i; + void *dummy; + + if (!ret_tab) + ret_tab = (toml_table_t **)&dummy; + if (!ret_arr) + ret_arr = (toml_array_t **)&dummy; + if (!ret_val) + ret_val = (toml_keyval_t **)&dummy; + + *ret_tab = 0; + *ret_arr = 0; + *ret_val = 0; + + for (i = 0; i < tab->nkval; i++) { + if (0 == strcmp(key, tab->kval[i]->key)) { + *ret_val = tab->kval[i]; + return 'v'; + } + } + for (i = 0; i < tab->narr; i++) { + if (0 == strcmp(key, tab->arr[i]->key)) { + *ret_arr = tab->arr[i]; + return 'a'; + } + } + for (i = 0; i < tab->ntab; i++) { + if (0 == strcmp(key, tab->tab[i]->key)) { + *ret_tab = tab->tab[i]; + return 't'; + } + } + return 0; +} + +static int key_kind(toml_table_t *tab, const char *key) { + return check_key(tab, key, 0, 0, 0); +} + +/* Create a keyval in the table. + */ +static toml_keyval_t *create_keyval_in_table(context_t *ctx, toml_table_t *tab, + token_t keytok) { + /* first, normalize the key to be used for lookup. + * remember to free it if we error out. + */ + char *newkey = normalize_key(ctx, keytok); + if (!newkey) + return 0; + + /* if key exists: error out. */ + toml_keyval_t *dest = 0; + if (key_kind(tab, newkey)) { + xfree(newkey); + e_keyexists(ctx, keytok.lineno); + return 0; + } + + /* make a new entry */ + int n = tab->nkval; + toml_keyval_t **base; + if (0 == (base = (toml_keyval_t **)expand_ptrarr((void **)tab->kval, n))) { + xfree(newkey); + e_outofmemory(ctx, FLINE); + return 0; + } + tab->kval = base; + + if (0 == (base[n] = (toml_keyval_t *)CALLOC(1, sizeof(*base[n])))) { + xfree(newkey); + e_outofmemory(ctx, FLINE); + return 0; + } + dest = tab->kval[tab->nkval++]; + + /* save the key in the new value struct */ + dest->key = newkey; + return dest; +} + +/* Create a table in the table. + */ +static toml_table_t *create_keytable_in_table(context_t *ctx, toml_table_t *tab, + token_t keytok) { + /* first, normalize the key to be used for lookup. + * remember to free it if we error out. + */ + char *newkey = normalize_key(ctx, keytok); + if (!newkey) + return 0; + + /* if key exists: error out */ + toml_table_t *dest = 0; + if (check_key(tab, newkey, 0, 0, &dest)) { + xfree(newkey); /* don't need this anymore */ + + /* special case: if table exists, but was created implicitly ... */ + if (dest && dest->implicit) { + /* we make it explicit now, and simply return it. */ + dest->implicit = false; + return dest; + } + e_keyexists(ctx, keytok.lineno); + return 0; + } + + /* create a new table entry */ + int n = tab->ntab; + toml_table_t **base; + if (0 == (base = (toml_table_t **)expand_ptrarr((void **)tab->tab, n))) { + xfree(newkey); + e_outofmemory(ctx, FLINE); + return 0; + } + tab->tab = base; + + if (0 == (base[n] = (toml_table_t *)CALLOC(1, sizeof(*base[n])))) { + xfree(newkey); + e_outofmemory(ctx, FLINE); + return 0; + } + dest = tab->tab[tab->ntab++]; + + /* save the key in the new table struct */ + dest->key = newkey; + return dest; +} + +/* Create an array in the table. + */ +static toml_array_t *create_keyarray_in_table(context_t *ctx, toml_table_t *tab, + token_t keytok, char kind) { + /* first, normalize the key to be used for lookup. + * remember to free it if we error out. + */ + char *newkey = normalize_key(ctx, keytok); + if (!newkey) + return 0; + + /* if key exists: error out */ + if (key_kind(tab, newkey)) { + xfree(newkey); /* don't need this anymore */ + e_keyexists(ctx, keytok.lineno); + return 0; + } + + /* make a new array entry */ + int n = tab->narr; + toml_array_t **base; + if (0 == (base = (toml_array_t **)expand_ptrarr((void **)tab->arr, n))) { + xfree(newkey); + e_outofmemory(ctx, FLINE); + return 0; + } + tab->arr = base; + + if (0 == (base[n] = (toml_array_t *)CALLOC(1, sizeof(*base[n])))) { + xfree(newkey); + e_outofmemory(ctx, FLINE); + return 0; + } + toml_array_t *dest = tab->arr[tab->narr++]; + + /* save the key in the new array struct */ + dest->key = newkey; + dest->kind = kind; + return dest; +} + +static toml_arritem_t *create_value_in_array(context_t *ctx, + toml_array_t *parent) { + const int n = parent->nitem; + toml_arritem_t *base = expand_arritem(parent->item, n); + if (!base) { + e_outofmemory(ctx, FLINE); + return 0; + } + parent->item = base; + parent->nitem++; + return &parent->item[n]; +} + +/* Create an array in an array + */ +static toml_array_t *create_array_in_array(context_t *ctx, + toml_array_t *parent) { + const int n = parent->nitem; + toml_arritem_t *base = expand_arritem(parent->item, n); + if (!base) { + e_outofmemory(ctx, FLINE); + return 0; + } + toml_array_t *ret = (toml_array_t *)CALLOC(1, sizeof(toml_array_t)); + if (!ret) { + e_outofmemory(ctx, FLINE); + return 0; + } + base[n].arr = ret; + parent->item = base; + parent->nitem++; + return ret; +} + +/* Create a table in an array + */ +static toml_table_t *create_table_in_array(context_t *ctx, + toml_array_t *parent) { + int n = parent->nitem; + toml_arritem_t *base = expand_arritem(parent->item, n); + if (!base) { + e_outofmemory(ctx, FLINE); + return 0; + } + toml_table_t *ret = (toml_table_t *)CALLOC(1, sizeof(toml_table_t)); + if (!ret) { + e_outofmemory(ctx, FLINE); + return 0; + } + base[n].tab = ret; + parent->item = base; + parent->nitem++; + return ret; +} + +static int skip_newlines(context_t *ctx, int isdotspecial) { + while (ctx->tok.tok == NEWLINE) { + if (next_token(ctx, isdotspecial)) + return -1; + if (ctx->tok.eof) + break; + } + return 0; +} + +static int parse_keyval(context_t *ctx, toml_table_t *tab); + +static inline int eat_token(context_t *ctx, tokentype_t typ, int isdotspecial, + const char *fline) { + if (ctx->tok.tok != typ) + return e_internal(ctx, fline); + + if (next_token(ctx, isdotspecial)) + return -1; + + return 0; +} + +/* We are at '{ ... }'. + * Parse the table. + */ +static int parse_inline_table(context_t *ctx, toml_table_t *tab) { + if (eat_token(ctx, LBRACE, 1, FLINE)) + return -1; + + for (;;) { + if (ctx->tok.tok == NEWLINE) + return e_syntax(ctx, ctx->tok.lineno, + "newline not allowed in inline table"); + + /* until } */ + if (ctx->tok.tok == RBRACE) + break; + + if (ctx->tok.tok != STRING) + return e_syntax(ctx, ctx->tok.lineno, "expect a string"); + + if (parse_keyval(ctx, tab)) + return -1; + + if (ctx->tok.tok == NEWLINE) + return e_syntax(ctx, ctx->tok.lineno, + "newline not allowed in inline table"); + + /* on comma, continue to scan for next keyval */ + if (ctx->tok.tok == COMMA) { + if (eat_token(ctx, COMMA, 1, FLINE)) + return -1; + continue; + } + break; + } + + if (eat_token(ctx, RBRACE, 1, FLINE)) + return -1; + + tab->readonly = 1; + + return 0; +} + +static int valtype(const char *val) { + toml_timestamp_t ts; + if (*val == '\'' || *val == '"') + return 's'; + if (0 == toml_rtob(val, 0)) + return 'b'; + if (0 == toml_rtoi(val, 0)) + return 'i'; + if (0 == toml_rtod(val, 0)) + return 'd'; + if (0 == toml_rtots(val, &ts)) { + if (ts.year && ts.hour) + return 'T'; /* timestamp */ + if (ts.year) + return 'D'; /* date */ + return 't'; /* time */ + } + return 'u'; /* unknown */ +} + +/* We are at '[...]' */ +static int parse_array(context_t *ctx, toml_array_t *arr) { + if (eat_token(ctx, LBRACKET, 0, FLINE)) + return -1; + + for (;;) { + if (skip_newlines(ctx, 0)) + return -1; + + /* until ] */ + if (ctx->tok.tok == RBRACKET) + break; + + switch (ctx->tok.tok) { + case STRING: { + /* set array kind if this will be the first entry */ + if (arr->kind == 0) + arr->kind = 'v'; + else if (arr->kind != 'v') + arr->kind = 'm'; + + char *val = ctx->tok.ptr; + int vlen = ctx->tok.len; + + /* make a new value in array */ + toml_arritem_t *newval = create_value_in_array(ctx, arr); + if (!newval) + return e_outofmemory(ctx, FLINE); + + if (!(newval->val = STRNDUP(val, vlen))) + return e_outofmemory(ctx, FLINE); + + newval->valtype = valtype(newval->val); + + /* set array type if this is the first entry */ + if (arr->nitem == 1) + arr->type = newval->valtype; + else if (arr->type != newval->valtype) + arr->type = 'm'; /* mixed */ + + if (eat_token(ctx, STRING, 0, FLINE)) + return -1; + break; + } + + case LBRACKET: { /* [ [array], [array] ... ] */ + /* set the array kind if this will be the first entry */ + if (arr->kind == 0) + arr->kind = 'a'; + else if (arr->kind != 'a') + arr->kind = 'm'; + + toml_array_t *subarr = create_array_in_array(ctx, arr); + if (!subarr) + return -1; + if (parse_array(ctx, subarr)) + return -1; + break; + } + + case LBRACE: { /* [ {table}, {table} ... ] */ + /* set the array kind if this will be the first entry */ + if (arr->kind == 0) + arr->kind = 't'; + else if (arr->kind != 't') + arr->kind = 'm'; + + toml_table_t *subtab = create_table_in_array(ctx, arr); + if (!subtab) + return -1; + if (parse_inline_table(ctx, subtab)) + return -1; + break; + } + + default: + return e_syntax(ctx, ctx->tok.lineno, "syntax error"); + } + + if (skip_newlines(ctx, 0)) + return -1; + + /* on comma, continue to scan for next element */ + if (ctx->tok.tok == COMMA) { + if (eat_token(ctx, COMMA, 0, FLINE)) + return -1; + continue; + } + break; + } + + if (eat_token(ctx, RBRACKET, 1, FLINE)) + return -1; + return 0; +} + +/* handle lines like these: + key = "value" + key = [ array ] + key = { table } +*/ +static int parse_keyval(context_t *ctx, toml_table_t *tab) { + if (tab->readonly) { + return e_forbid(ctx, ctx->tok.lineno, + "cannot insert new entry into existing table"); + } + + token_t key = ctx->tok; + if (eat_token(ctx, STRING, 1, FLINE)) + return -1; + + if (ctx->tok.tok == DOT) { + /* handle inline dotted key. + e.g. + physical.color = "orange" + physical.shape = "round" + */ + toml_table_t *subtab = 0; + { + char *subtabstr = normalize_key(ctx, key); + if (!subtabstr) + return -1; + + subtab = toml_table_in(tab, subtabstr); + xfree(subtabstr); + } + if (!subtab) { + subtab = create_keytable_in_table(ctx, tab, key); + if (!subtab) + return -1; + } + if (next_token(ctx, 1)) + return -1; + if (parse_keyval(ctx, subtab)) + return -1; + return 0; + } + + if (ctx->tok.tok != EQUAL) { + return e_syntax(ctx, ctx->tok.lineno, "missing ="); + } + + if (next_token(ctx, 0)) + return -1; + + switch (ctx->tok.tok) { + case STRING: { /* key = "value" */ + toml_keyval_t *keyval = create_keyval_in_table(ctx, tab, key); + if (!keyval) + return -1; + token_t val = ctx->tok; + + assert(keyval->val == 0); + if (!(keyval->val = STRNDUP(val.ptr, val.len))) + return e_outofmemory(ctx, FLINE); + + if (next_token(ctx, 1)) + return -1; + + return 0; + } + + case LBRACKET: { /* key = [ array ] */ + toml_array_t *arr = create_keyarray_in_table(ctx, tab, key, 0); + if (!arr) + return -1; + if (parse_array(ctx, arr)) + return -1; + return 0; + } + + case LBRACE: { /* key = { table } */ + toml_table_t *nxttab = create_keytable_in_table(ctx, tab, key); + if (!nxttab) + return -1; + if (parse_inline_table(ctx, nxttab)) + return -1; + return 0; + } + + default: + return e_syntax(ctx, ctx->tok.lineno, "syntax error"); + } + return 0; +} + +typedef struct tabpath_t tabpath_t; +struct tabpath_t { + int cnt; + token_t key[10]; +}; + +/* at [x.y.z] or [[x.y.z]] + * Scan forward and fill tabpath until it enters ] or ]] + * There will be at least one entry on return. + */ +static int fill_tabpath(context_t *ctx) { + int lineno = ctx->tok.lineno; + int i; + + /* clear tpath */ + for (i = 0; i < ctx->tpath.top; i++) { + char **p = &ctx->tpath.key[i]; + xfree(*p); + *p = 0; + } + ctx->tpath.top = 0; + + for (;;) { + if (ctx->tpath.top >= 10) + return e_syntax(ctx, lineno, + "table path is too deep; max allowed is 10."); + + if (ctx->tok.tok != STRING) + return e_syntax(ctx, lineno, "invalid or missing key"); + + char *key = normalize_key(ctx, ctx->tok); + if (!key) + return -1; + ctx->tpath.tok[ctx->tpath.top] = ctx->tok; + ctx->tpath.key[ctx->tpath.top] = key; + ctx->tpath.top++; + + if (next_token(ctx, 1)) + return -1; + + if (ctx->tok.tok == RBRACKET) + break; + + if (ctx->tok.tok != DOT) + return e_syntax(ctx, lineno, "invalid key"); + + if (next_token(ctx, 1)) + return -1; + } + + if (ctx->tpath.top <= 0) + return e_syntax(ctx, lineno, "empty table selector"); + + return 0; +} + +/* Walk tabpath from the root, and create new tables on the way. + * Sets ctx->curtab to the final table. + */ +static int walk_tabpath(context_t *ctx) { + /* start from root */ + toml_table_t *curtab = ctx->root; + + for (int i = 0; i < ctx->tpath.top; i++) { + const char *key = ctx->tpath.key[i]; + + toml_keyval_t *nextval = 0; + toml_array_t *nextarr = 0; + toml_table_t *nexttab = 0; + switch (check_key(curtab, key, &nextval, &nextarr, &nexttab)) { + case 't': + /* found a table. nexttab is where we will go next. */ + break; + + case 'a': + /* found an array. nexttab is the last table in the array. */ + if (nextarr->kind != 't') + return e_internal(ctx, FLINE); + + if (nextarr->nitem == 0) + return e_internal(ctx, FLINE); + + nexttab = nextarr->item[nextarr->nitem - 1].tab; + break; + + case 'v': + return e_keyexists(ctx, ctx->tpath.tok[i].lineno); + + default: { /* Not found. Let's create an implicit table. */ + int n = curtab->ntab; + toml_table_t **base = + (toml_table_t **)expand_ptrarr((void **)curtab->tab, n); + if (0 == base) + return e_outofmemory(ctx, FLINE); + + curtab->tab = base; + + if (0 == (base[n] = (toml_table_t *)CALLOC(1, sizeof(*base[n])))) + return e_outofmemory(ctx, FLINE); + + if (0 == (base[n]->key = STRDUP(key))) + return e_outofmemory(ctx, FLINE); + + nexttab = curtab->tab[curtab->ntab++]; + + /* tabs created by walk_tabpath are considered implicit */ + nexttab->implicit = true; + } break; + } + + /* switch to next tab */ + curtab = nexttab; + } + + /* save it */ + ctx->curtab = curtab; + + return 0; +} + +/* handle lines like [x.y.z] or [[x.y.z]] */ +static int parse_select(context_t *ctx) { + assert(ctx->tok.tok == LBRACKET); + + /* true if [[ */ + int llb = (ctx->tok.ptr + 1 < ctx->stop && ctx->tok.ptr[1] == '['); + /* need to detect '[[' on our own because next_token() will skip whitespace, + and '[ [' would be taken as '[[', which is wrong. */ + + /* eat [ or [[ */ + if (eat_token(ctx, LBRACKET, 1, FLINE)) + return -1; + if (llb) { + assert(ctx->tok.tok == LBRACKET); + if (eat_token(ctx, LBRACKET, 1, FLINE)) + return -1; + } + + if (fill_tabpath(ctx)) + return -1; + + /* For [x.y.z] or [[x.y.z]], remove z from tpath. + */ + token_t z = ctx->tpath.tok[ctx->tpath.top - 1]; + xfree(ctx->tpath.key[ctx->tpath.top - 1]); + ctx->tpath.top--; + + /* set up ctx->curtab */ + if (walk_tabpath(ctx)) + return -1; + + if (!llb) { + /* [x.y.z] -> create z = {} in x.y */ + toml_table_t *curtab = create_keytable_in_table(ctx, ctx->curtab, z); + if (!curtab) + return -1; + ctx->curtab = curtab; + } else { + /* [[x.y.z]] -> create z = [] in x.y */ + toml_array_t *arr = 0; + { + char *zstr = normalize_key(ctx, z); + if (!zstr) + return -1; + arr = toml_array_in(ctx->curtab, zstr); + xfree(zstr); + } + if (!arr) { + arr = create_keyarray_in_table(ctx, ctx->curtab, z, 't'); + if (!arr) + return -1; + } + if (arr->kind != 't') + return e_syntax(ctx, z.lineno, "array mismatch"); + + /* add to z[] */ + toml_table_t *dest; + { + toml_table_t *t = create_table_in_array(ctx, arr); + if (!t) + return -1; + + if (0 == (t->key = STRDUP("__anon__"))) + return e_outofmemory(ctx, FLINE); + + dest = t; + } + + ctx->curtab = dest; + } + + if (ctx->tok.tok != RBRACKET) { + return e_syntax(ctx, ctx->tok.lineno, "expects ]"); + } + if (llb) { + if (!(ctx->tok.ptr + 1 < ctx->stop && ctx->tok.ptr[1] == ']')) { + return e_syntax(ctx, ctx->tok.lineno, "expects ]]"); + } + if (eat_token(ctx, RBRACKET, 1, FLINE)) + return -1; + } + + if (eat_token(ctx, RBRACKET, 1, FLINE)) + return -1; + + if (ctx->tok.tok != NEWLINE) + return e_syntax(ctx, ctx->tok.lineno, "extra chars after ] or ]]"); + + return 0; +} + +toml_table_t *toml_parse(char *conf, char *errbuf, int errbufsz) { + context_t ctx; + + // clear errbuf + if (errbufsz <= 0) + errbufsz = 0; + if (errbufsz > 0) + errbuf[0] = 0; + + // init context + memset(&ctx, 0, sizeof(ctx)); + ctx.start = conf; + ctx.stop = ctx.start + strlen(conf); + ctx.errbuf = errbuf; + ctx.errbufsz = errbufsz; + + // start with an artificial newline of length 0 + ctx.tok.tok = NEWLINE; + ctx.tok.lineno = 1; + ctx.tok.ptr = conf; + ctx.tok.len = 0; + + // make a root table + if (0 == (ctx.root = CALLOC(1, sizeof(*ctx.root)))) { + e_outofmemory(&ctx, FLINE); + // Do not goto fail, root table not set up yet + return 0; + } + + // set root as default table + ctx.curtab = ctx.root; + + /* Scan forward until EOF */ + for (token_t tok = ctx.tok; !tok.eof; tok = ctx.tok) { + switch (tok.tok) { + + case NEWLINE: + if (next_token(&ctx, 1)) + goto fail; + break; + + case STRING: + if (parse_keyval(&ctx, ctx.curtab)) + goto fail; + + if (ctx.tok.tok != NEWLINE) { + e_syntax(&ctx, ctx.tok.lineno, "extra chars after value"); + goto fail; + } + + if (eat_token(&ctx, NEWLINE, 1, FLINE)) + goto fail; + break; + + case LBRACKET: /* [ x.y.z ] or [[ x.y.z ]] */ + if (parse_select(&ctx)) + goto fail; + break; + + default: + e_syntax(&ctx, tok.lineno, "syntax error"); + goto fail; + } + } + + /* success */ + for (int i = 0; i < ctx.tpath.top; i++) + xfree(ctx.tpath.key[i]); + return ctx.root; + +fail: + // Something bad has happened. Free resources and return error. + for (int i = 0; i < ctx.tpath.top; i++) + xfree(ctx.tpath.key[i]); + toml_free(ctx.root); + return 0; +} + +toml_table_t *toml_parse_file(FILE *fp, char *errbuf, int errbufsz) { + int bufsz = 0; + char *buf = 0; + int off = 0; + + /* read from fp into buf */ + while (!feof(fp)) { + + if (off == bufsz) { + int xsz = bufsz + 1000; + char *x = expand(buf, bufsz, xsz); + if (!x) { + snprintf(errbuf, errbufsz, "out of memory"); + xfree(buf); + return 0; + } + buf = x; + bufsz = xsz; + } + + errno = 0; + int n = fread(buf + off, 1, bufsz - off, fp); + if (ferror(fp)) { + snprintf(errbuf, errbufsz, "%s", + errno ? strerror(errno) : "Error reading file"); + xfree(buf); + return 0; + } + off += n; + } + + /* tag on a NUL to cap the string */ + if (off == bufsz) { + int xsz = bufsz + 1; + char *x = expand(buf, bufsz, xsz); + if (!x) { + snprintf(errbuf, errbufsz, "out of memory"); + xfree(buf); + return 0; + } + buf = x; + bufsz = xsz; + } + buf[off] = 0; + + /* parse it, cleanup and finish */ + toml_table_t *ret = toml_parse(buf, errbuf, errbufsz); + xfree(buf); + return ret; +} + +static void xfree_kval(toml_keyval_t *p) { + if (!p) + return; + xfree(p->key); + xfree(p->val); + xfree(p); +} + +static void xfree_tab(toml_table_t *p); + +static void xfree_arr(toml_array_t *p) { + if (!p) + return; + + xfree(p->key); + const int n = p->nitem; + for (int i = 0; i < n; i++) { + toml_arritem_t *a = &p->item[i]; + if (a->val) + xfree(a->val); + else if (a->arr) + xfree_arr(a->arr); + else if (a->tab) + xfree_tab(a->tab); + } + xfree(p->item); + xfree(p); +} + +static void xfree_tab(toml_table_t *p) { + int i; + + if (!p) + return; + + xfree(p->key); + + for (i = 0; i < p->nkval; i++) + xfree_kval(p->kval[i]); + xfree(p->kval); + + for (i = 0; i < p->narr; i++) + xfree_arr(p->arr[i]); + xfree(p->arr); + + for (i = 0; i < p->ntab; i++) + xfree_tab(p->tab[i]); + xfree(p->tab); + + xfree(p); +} + +void toml_free(toml_table_t *tab) { xfree_tab(tab); } + +static void set_token(context_t *ctx, tokentype_t tok, int lineno, char *ptr, + int len) { + token_t t; + t.tok = tok; + t.lineno = lineno; + t.ptr = ptr; + t.len = len; + t.eof = 0; + ctx->tok = t; +} + +static void set_eof(context_t *ctx, int lineno) { + set_token(ctx, NEWLINE, lineno, ctx->stop, 0); + ctx->tok.eof = 1; +} + +/* Scan p for n digits compositing entirely of [0-9] */ +static int scan_digits(const char *p, int n) { + int ret = 0; + for (; n > 0 && isdigit(*p); n--, p++) { + ret = 10 * ret + (*p - '0'); + } + return n ? -1 : ret; +} + +static int scan_date(const char *p, int *YY, int *MM, int *DD) { + int year, month, day; + year = scan_digits(p, 4); + month = (year >= 0 && p[4] == '-') ? scan_digits(p + 5, 2) : -1; + day = (month >= 0 && p[7] == '-') ? scan_digits(p + 8, 2) : -1; + if (YY) + *YY = year; + if (MM) + *MM = month; + if (DD) + *DD = day; + return (year >= 0 && month >= 0 && day >= 0) ? 0 : -1; +} + +static int scan_time(const char *p, int *hh, int *mm, int *ss) { + int hour, minute, second; + hour = scan_digits(p, 2); + minute = (hour >= 0 && p[2] == ':') ? scan_digits(p + 3, 2) : -1; + second = (minute >= 0 && p[5] == ':') ? scan_digits(p + 6, 2) : -1; + if (hh) + *hh = hour; + if (mm) + *mm = minute; + if (ss) + *ss = second; + return (hour >= 0 && minute >= 0 && second >= 0) ? 0 : -1; +} + +static int scan_string(context_t *ctx, char *p, int lineno, int dotisspecial) { + char *orig = p; + if (0 == strncmp(p, "'''", 3)) { + char *q = p + 3; + + while (1) { + q = strstr(q, "'''"); + if (0 == q) { + return e_syntax(ctx, lineno, "unterminated triple-s-quote"); + } + while (q[3] == '\'') + q++; + break; + } + + set_token(ctx, STRING, lineno, orig, q + 3 - orig); + return 0; + } + + if (0 == strncmp(p, "\"\"\"", 3)) { + char *q = p + 3; + + while (1) { + q = strstr(q, "\"\"\""); + if (0 == q) { + return e_syntax(ctx, lineno, "unterminated triple-d-quote"); + } + if (q[-1] == '\\') { + q++; + continue; + } + while (q[3] == '\"') + q++; + break; + } + + // the string is [p+3, q-1] + + int hexreq = 0; /* #hex required */ + int escape = 0; + for (p += 3; p < q; p++) { + if (escape) { + escape = 0; + if (strchr("btnfr\"\\", *p)) + continue; + if (*p == 'u') { + hexreq = 4; + continue; + } + if (*p == 'U') { + hexreq = 8; + continue; + } + if (p[strspn(p, " \t\r")] == '\n') + continue; /* allow for line ending backslash */ + return e_syntax(ctx, lineno, "bad escape char"); + } + if (hexreq) { + hexreq--; + if (strchr("0123456789ABCDEF", *p)) + continue; + return e_syntax(ctx, lineno, "expect hex char"); + } + if (*p == '\\') { + escape = 1; + continue; + } + } + if (escape) + return e_syntax(ctx, lineno, "expect an escape char"); + if (hexreq) + return e_syntax(ctx, lineno, "expected more hex char"); + + set_token(ctx, STRING, lineno, orig, q + 3 - orig); + return 0; + } + + if ('\'' == *p) { + for (p++; *p && *p != '\n' && *p != '\''; p++) + ; + if (*p != '\'') { + return e_syntax(ctx, lineno, "unterminated s-quote"); + } + + set_token(ctx, STRING, lineno, orig, p + 1 - orig); + return 0; + } + + if ('\"' == *p) { + int hexreq = 0; /* #hex required */ + int escape = 0; + for (p++; *p; p++) { + if (escape) { + escape = 0; + if (strchr("btnfr\"\\", *p)) + continue; + if (*p == 'u') { + hexreq = 4; + continue; + } + if (*p == 'U') { + hexreq = 8; + continue; + } + return e_syntax(ctx, lineno, "bad escape char"); + } + if (hexreq) { + hexreq--; + if (strchr("0123456789ABCDEF", *p)) + continue; + return e_syntax(ctx, lineno, "expect hex char"); + } + if (*p == '\\') { + escape = 1; + continue; + } + if (*p == '\'') { + if (p[1] == '\'' && p[2] == '\'') { + return e_syntax(ctx, lineno, "triple-s-quote inside string lit"); + } + continue; + } + if (*p == '\n') + break; + if (*p == '"') + break; + } + if (*p != '"') { + return e_syntax(ctx, lineno, "unterminated quote"); + } + + set_token(ctx, STRING, lineno, orig, p + 1 - orig); + return 0; + } + + /* check for timestamp without quotes */ + if (0 == scan_date(p, 0, 0, 0) || 0 == scan_time(p, 0, 0, 0)) { + // forward thru the timestamp + p += strspn(p, "0123456789.:+-Tt Zz"); + // squeeze out any spaces at end of string + for (; p[-1] == ' '; p--) + ; + // tokenize + set_token(ctx, STRING, lineno, orig, p - orig); + return 0; + } + + /* literals */ + for (; *p && *p != '\n'; p++) { + int ch = *p; + if (ch == '.' && dotisspecial) + break; + if ('A' <= ch && ch <= 'Z') + continue; + if ('a' <= ch && ch <= 'z') + continue; + if (strchr("0123456789+-_.", ch)) + continue; + break; + } + + set_token(ctx, STRING, lineno, orig, p - orig); + return 0; +} + +static int next_token(context_t *ctx, int dotisspecial) { + int lineno = ctx->tok.lineno; + char *p = ctx->tok.ptr; + int i; + + /* eat this tok */ + for (i = 0; i < ctx->tok.len; i++) { + if (*p++ == '\n') + lineno++; + } + + /* make next tok */ + while (p < ctx->stop) { + /* skip comment. stop just before the \n. */ + if (*p == '#') { + for (p++; p < ctx->stop && *p != '\n'; p++) + ; + continue; + } + + if (dotisspecial && *p == '.') { + set_token(ctx, DOT, lineno, p, 1); + return 0; + } + + switch (*p) { + case ',': + set_token(ctx, COMMA, lineno, p, 1); + return 0; + case '=': + set_token(ctx, EQUAL, lineno, p, 1); + return 0; + case '{': + set_token(ctx, LBRACE, lineno, p, 1); + return 0; + case '}': + set_token(ctx, RBRACE, lineno, p, 1); + return 0; + case '[': + set_token(ctx, LBRACKET, lineno, p, 1); + return 0; + case ']': + set_token(ctx, RBRACKET, lineno, p, 1); + return 0; + case '\n': + set_token(ctx, NEWLINE, lineno, p, 1); + return 0; + case '\r': + case ' ': + case '\t': + /* ignore white spaces */ + p++; + continue; + } + + return scan_string(ctx, p, lineno, dotisspecial); + } + + set_eof(ctx, lineno); + return 0; +} + +const char *toml_key_in(const toml_table_t *tab, int keyidx) { + if (keyidx < tab->nkval) + return tab->kval[keyidx]->key; + + keyidx -= tab->nkval; + if (keyidx < tab->narr) + return tab->arr[keyidx]->key; + + keyidx -= tab->narr; + if (keyidx < tab->ntab) + return tab->tab[keyidx]->key; + + return 0; +} + +int toml_key_exists(const toml_table_t *tab, const char *key) { + int i; + for (i = 0; i < tab->nkval; i++) { + if (0 == strcmp(key, tab->kval[i]->key)) + return 1; + } + for (i = 0; i < tab->narr; i++) { + if (0 == strcmp(key, tab->arr[i]->key)) + return 1; + } + for (i = 0; i < tab->ntab; i++) { + if (0 == strcmp(key, tab->tab[i]->key)) + return 1; + } + return 0; +} + +toml_raw_t toml_raw_in(const toml_table_t *tab, const char *key) { + int i; + for (i = 0; i < tab->nkval; i++) { + if (0 == strcmp(key, tab->kval[i]->key)) + return tab->kval[i]->val; + } + return 0; +} + +toml_array_t *toml_array_in(const toml_table_t *tab, const char *key) { + int i; + for (i = 0; i < tab->narr; i++) { + if (0 == strcmp(key, tab->arr[i]->key)) + return tab->arr[i]; + } + return 0; +} + +toml_table_t *toml_table_in(const toml_table_t *tab, const char *key) { + int i; + for (i = 0; i < tab->ntab; i++) { + if (0 == strcmp(key, tab->tab[i]->key)) + return tab->tab[i]; + } + return 0; +} + +toml_raw_t toml_raw_at(const toml_array_t *arr, int idx) { + return (0 <= idx && idx < arr->nitem) ? arr->item[idx].val : 0; +} + +char toml_array_kind(const toml_array_t *arr) { return arr->kind; } + +char toml_array_type(const toml_array_t *arr) { + if (arr->kind != 'v') + return 0; + + if (arr->nitem == 0) + return 0; + + return arr->type; +} + +int toml_array_nelem(const toml_array_t *arr) { return arr->nitem; } + +const char *toml_array_key(const toml_array_t *arr) { + return arr ? arr->key : (const char *)NULL; +} + +int toml_table_nkval(const toml_table_t *tab) { return tab->nkval; } + +int toml_table_narr(const toml_table_t *tab) { return tab->narr; } + +int toml_table_ntab(const toml_table_t *tab) { return tab->ntab; } + +const char *toml_table_key(const toml_table_t *tab) { + return tab ? tab->key : (const char *)NULL; +} + +toml_array_t *toml_array_at(const toml_array_t *arr, int idx) { + return (0 <= idx && idx < arr->nitem) ? arr->item[idx].arr : 0; +} + +toml_table_t *toml_table_at(const toml_array_t *arr, int idx) { + return (0 <= idx && idx < arr->nitem) ? arr->item[idx].tab : 0; +} + +static int parse_millisec(const char *p, const char **endp); + +int toml_rtots(toml_raw_t src_, toml_timestamp_t *ret) { + if (!src_) + return -1; + + const char *p = src_; + int must_parse_time = 0; + + memset(ret, 0, sizeof(*ret)); + + int *year = &ret->__buffer.year; + int *month = &ret->__buffer.month; + int *day = &ret->__buffer.day; + int *hour = &ret->__buffer.hour; + int *minute = &ret->__buffer.minute; + int *second = &ret->__buffer.second; + int *millisec = &ret->__buffer.millisec; + + /* parse date YYYY-MM-DD */ + if (0 == scan_date(p, year, month, day)) { + ret->year = year; + ret->month = month; + ret->day = day; + + p += 10; + if (*p) { + // parse the T or space separator + if (*p != 'T' && *p != 't' && *p != ' ') + return -1; + must_parse_time = 1; + p++; + } + } + + /* parse time HH:MM:SS */ + if (0 == scan_time(p, hour, minute, second)) { + ret->hour = hour; + ret->minute = minute; + ret->second = second; + + /* optionally, parse millisec */ + p += 8; + if (*p == '.') { + p++; /* skip '.' */ + const char *qq; + *millisec = parse_millisec(p, &qq); + ret->millisec = millisec; + p = qq; + } + + if (*p) { + /* parse and copy Z */ + char *z = ret->__buffer.z; + ret->z = z; + if (*p == 'Z' || *p == 'z') { + *z++ = 'Z'; + p++; + *z = 0; + + } else if (*p == '+' || *p == '-') { + *z++ = *p++; + + if (!(isdigit(p[0]) && isdigit(p[1]))) + return -1; + *z++ = *p++; + *z++ = *p++; + + if (*p == ':') { + *z++ = *p++; + + if (!(isdigit(p[0]) && isdigit(p[1]))) + return -1; + *z++ = *p++; + *z++ = *p++; + } + + *z = 0; + } + } + } + if (*p != 0) + return -1; + + if (must_parse_time && !ret->hour) + return -1; + + return 0; +} + +/* Raw to boolean */ +int toml_rtob(toml_raw_t src, int *ret_) { + if (!src) + return -1; + int dummy; + int *ret = ret_ ? ret_ : &dummy; + + if (0 == strcmp(src, "true")) { + *ret = 1; + return 0; + } + if (0 == strcmp(src, "false")) { + *ret = 0; + return 0; + } + return -1; +} + +/* Raw to integer */ +int toml_rtoi(toml_raw_t src, int64_t *ret_) { + if (!src) + return -1; + + char buf[100]; + char *p = buf; + char *q = p + sizeof(buf); + const char *s = src; + int base = 0; + int64_t dummy; + int64_t *ret = ret_ ? ret_ : &dummy; + + /* allow +/- */ + if (s[0] == '+' || s[0] == '-') + *p++ = *s++; + + /* disallow +_100 */ + if (s[0] == '_') + return -1; + + /* if 0* ... */ + if ('0' == s[0]) { + switch (s[1]) { + case 'x': + base = 16; + s += 2; + break; + case 'o': + base = 8; + s += 2; + break; + case 'b': + base = 2; + s += 2; + break; + case '\0': + return *ret = 0, 0; + default: + /* ensure no other digits after it */ + if (s[1]) + return -1; + } + } + + /* just strip underscores and pass to strtoll */ + while (*s && p < q) { + int ch = *s++; + if (ch == '_') { + // disallow '__' + if (s[0] == '_') + return -1; + // numbers cannot end with '_' + if (s[0] == '\0') + return -1; + continue; /* skip _ */ + } + *p++ = ch; + } + + // if not at end-of-string or we ran out of buffer ... + if (*s || p == q) + return -1; + + /* cap with NUL */ + *p = 0; + + /* Run strtoll on buf to get the integer */ + char *endp; + errno = 0; + *ret = strtoll(buf, &endp, base); + return (errno || *endp) ? -1 : 0; +} + +int toml_rtod_ex(toml_raw_t src, double *ret_, char *buf, int buflen) { + if (!src) + return -1; + + char *p = buf; + char *q = p + buflen; + const char *s = src; + double dummy; + double *ret = ret_ ? ret_ : &dummy; + + /* allow +/- */ + if (s[0] == '+' || s[0] == '-') + *p++ = *s++; + + /* disallow +_1.00 */ + if (s[0] == '_') + return -1; + + /* decimal point, if used, must be surrounded by at least one digit on each + * side */ + { + char *dot = strchr(s, '.'); + if (dot) { + if (dot == s || !isdigit(dot[-1]) || !isdigit(dot[1])) + return -1; + } + } + + /* zero must be followed by . or 'e', or NUL */ + if (s[0] == '0' && s[1] && !strchr("eE.", s[1])) + return -1; + + /* just strip underscores and pass to strtod */ + while (*s && p < q) { + int ch = *s++; + if (ch == '_') { + // disallow '__' + if (s[0] == '_') + return -1; + // disallow last char '_' + if (s[0] == 0) + return -1; + continue; /* skip _ */ + } + *p++ = ch; + } + if (*s || p == q) + return -1; /* reached end of string or buffer is full? */ + + /* cap with NUL */ + *p = 0; + + /* Run strtod on buf to get the value */ + char *endp; + errno = 0; + *ret = strtod(buf, &endp); + return (errno || *endp) ? -1 : 0; +} + +int toml_rtod(toml_raw_t src, double *ret_) { + char buf[100]; + return toml_rtod_ex(src, ret_, buf, sizeof(buf)); +} + +int toml_rtos(toml_raw_t src, char **ret) { + int multiline = 0; + const char *sp; + const char *sq; + + *ret = 0; + if (!src) + return -1; + + int qchar = src[0]; + int srclen = strlen(src); + if (!(qchar == '\'' || qchar == '"')) { + return -1; + } + + // triple quotes? + if (qchar == src[1] && qchar == src[2]) { + multiline = 1; + sp = src + 3; + sq = src + srclen - 3; + /* last 3 chars in src must be qchar */ + if (!(sp <= sq && sq[0] == qchar && sq[1] == qchar && sq[2] == qchar)) + return -1; + + /* skip new line immediate after qchar */ + if (sp[0] == '\n') + sp++; + else if (sp[0] == '\r' && sp[1] == '\n') + sp += 2; + + } else { + sp = src + 1; + sq = src + srclen - 1; + /* last char in src must be qchar */ + if (!(sp <= sq && *sq == qchar)) + return -1; + } + + if (qchar == '\'') { + *ret = norm_lit_str(sp, sq - sp, multiline, 0, 0); + } else { + *ret = norm_basic_str(sp, sq - sp, multiline, 0, 0); + } + + return *ret ? 0 : -1; +} + +toml_datum_t toml_string_at(const toml_array_t *arr, int idx) { + toml_datum_t ret; + memset(&ret, 0, sizeof(ret)); + ret.ok = (0 == toml_rtos(toml_raw_at(arr, idx), &ret.u.s)); + return ret; +} + +toml_datum_t toml_bool_at(const toml_array_t *arr, int idx) { + toml_datum_t ret; + memset(&ret, 0, sizeof(ret)); + ret.ok = (0 == toml_rtob(toml_raw_at(arr, idx), &ret.u.b)); + return ret; +} + +toml_datum_t toml_int_at(const toml_array_t *arr, int idx) { + toml_datum_t ret; + memset(&ret, 0, sizeof(ret)); + ret.ok = (0 == toml_rtoi(toml_raw_at(arr, idx), &ret.u.i)); + return ret; +} + +toml_datum_t toml_double_at(const toml_array_t *arr, int idx) { + toml_datum_t ret; + memset(&ret, 0, sizeof(ret)); + ret.ok = (0 == toml_rtod(toml_raw_at(arr, idx), &ret.u.d)); + return ret; +} + +toml_datum_t toml_timestamp_at(const toml_array_t *arr, int idx) { + toml_timestamp_t ts; + toml_datum_t ret; + memset(&ret, 0, sizeof(ret)); + ret.ok = (0 == toml_rtots(toml_raw_at(arr, idx), &ts)); + if (ret.ok) { + ret.ok = !!(ret.u.ts = MALLOC(sizeof(*ret.u.ts))); + if (ret.ok) { + *ret.u.ts = ts; + if (ret.u.ts->year) + ret.u.ts->year = &ret.u.ts->__buffer.year; + if (ret.u.ts->month) + ret.u.ts->month = &ret.u.ts->__buffer.month; + if (ret.u.ts->day) + ret.u.ts->day = &ret.u.ts->__buffer.day; + if (ret.u.ts->hour) + ret.u.ts->hour = &ret.u.ts->__buffer.hour; + if (ret.u.ts->minute) + ret.u.ts->minute = &ret.u.ts->__buffer.minute; + if (ret.u.ts->second) + ret.u.ts->second = &ret.u.ts->__buffer.second; + if (ret.u.ts->millisec) + ret.u.ts->millisec = &ret.u.ts->__buffer.millisec; + if (ret.u.ts->z) + ret.u.ts->z = ret.u.ts->__buffer.z; + } + } + return ret; +} + +toml_datum_t toml_string_in(const toml_table_t *arr, const char *key) { + toml_datum_t ret; + memset(&ret, 0, sizeof(ret)); + toml_raw_t raw = toml_raw_in(arr, key); + if (raw) { + ret.ok = (0 == toml_rtos(raw, &ret.u.s)); + } + return ret; +} + +toml_datum_t toml_bool_in(const toml_table_t *arr, const char *key) { + toml_datum_t ret; + memset(&ret, 0, sizeof(ret)); + ret.ok = (0 == toml_rtob(toml_raw_in(arr, key), &ret.u.b)); + return ret; +} + +toml_datum_t toml_int_in(const toml_table_t *arr, const char *key) { + toml_datum_t ret; + memset(&ret, 0, sizeof(ret)); + ret.ok = (0 == toml_rtoi(toml_raw_in(arr, key), &ret.u.i)); + return ret; +} + +toml_datum_t toml_double_in(const toml_table_t *arr, const char *key) { + toml_datum_t ret; + memset(&ret, 0, sizeof(ret)); + ret.ok = (0 == toml_rtod(toml_raw_in(arr, key), &ret.u.d)); + return ret; +} + +toml_datum_t toml_timestamp_in(const toml_table_t *arr, const char *key) { + toml_timestamp_t ts; + toml_datum_t ret; + memset(&ret, 0, sizeof(ret)); + ret.ok = (0 == toml_rtots(toml_raw_in(arr, key), &ts)); + if (ret.ok) { + ret.ok = !!(ret.u.ts = MALLOC(sizeof(*ret.u.ts))); + if (ret.ok) { + *ret.u.ts = ts; + if (ret.u.ts->year) + ret.u.ts->year = &ret.u.ts->__buffer.year; + if (ret.u.ts->month) + ret.u.ts->month = &ret.u.ts->__buffer.month; + if (ret.u.ts->day) + ret.u.ts->day = &ret.u.ts->__buffer.day; + if (ret.u.ts->hour) + ret.u.ts->hour = &ret.u.ts->__buffer.hour; + if (ret.u.ts->minute) + ret.u.ts->minute = &ret.u.ts->__buffer.minute; + if (ret.u.ts->second) + ret.u.ts->second = &ret.u.ts->__buffer.second; + if (ret.u.ts->millisec) + ret.u.ts->millisec = &ret.u.ts->__buffer.millisec; + if (ret.u.ts->z) + ret.u.ts->z = ret.u.ts->__buffer.z; + } + } + return ret; +} + +static int parse_millisec(const char *p, const char **endp) { + int ret = 0; + int unit = 100; /* unit in millisec */ + for (; '0' <= *p && *p <= '9'; p++, unit /= 10) { + ret += (*p - '0') * unit; + } + *endp = p; + return ret; +} diff --git a/userspace/include/libvgpu.h b/userspace/include/libvgpu.h new file mode 100644 index 0000000..7f6505b --- /dev/null +++ b/userspace/include/libvgpu.h @@ -0,0 +1,238 @@ +/* + * GSP vGPU-IO Userspace Library (libvgpu) + * Simple C API for VF management and GPU operations + */ + +#ifndef _LIBVGPU_H_ +#define _LIBVGPU_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Error codes */ +typedef enum { + VGPU_OK = 0, + VGPU_ERR_INVALID_ARG = -1, + VGPU_ERR_NO_DEVICE = -2, + VGPU_ERR_NO_MEMORY = -3, + VGPU_ERR_BUSY = -4, + VGPU_ERR_TIMEOUT = -5, + VGPU_ERR_PERMISSION = -6, + VGPU_ERR_NOT_SUPPORTED = -7, + VGPU_ERR_INTERNAL = -8, +} vgpu_error_t; + +/* Memory types */ +typedef enum { + VGPU_MEM_VRAM = 0, + VGPU_MEM_SYSMEM = 1, + VGPU_MEM_UNCACHED = 2, +} vgpu_mem_type_t; + +/* Pin flags */ +#define VGPU_PIN_READ (1 << 0) +#define VGPU_PIN_WRITE (1 << 1) +#define VGPU_PIN_LONGTERM (1 << 2) + +/* WPR flags */ +#define VGPU_WPR_WRITE (1 << 0) +#define VGPU_WPR_READ (1 << 1) +#define VGPU_WPR_EXECUTE (1 << 2) + +/* Migration phases */ +typedef enum { + VGPU_MIG_QUERY = 0, + VGPU_MIG_PREPARE = 1, + VGPU_MIG_TRANSFER = 2, + VGPU_MIG_COMMIT = 3, + VGPU_MIG_CLEANUP = 4, +} vgpu_mig_phase_t; + +/* Migration flags */ +#define VGPU_MIG_LIVE (1 << 0) +#define VGPU_MIG_POSTCOPY (1 << 1) +#define VGPU_MIG_AUTO_COMMIT (1 << 2) +#define VGPU_MIG_VERIFY (1 << 3) + +/* VF Configuration */ +typedef struct { + uint32_t id; + uint64_t bar1_offset; + uint64_t bar1_size; + uint64_t pt_base; + uint64_t pt_size; + uint64_t cmd_base; + uint64_t cmd_size; + uint32_t max_memory_mb; + uint32_t num_engines; +} vgpu_vf_config_t; + +/* VF Handle */ +typedef struct vgpu_vf *vgpu_vf_t; + +/* Device Handle */ +typedef struct vgpu_device *vgpu_device_t; + +/* Allocation Handle */ +typedef uint64_t vgpu_handle_t; + +/* ============================================================ + * Device Management + * ============================================================ */ + +/* Open GSP device */ +vgpu_error_t vgpu_open(const char *device_path, vgpu_device_t *device); + +/* Close GSP device */ +void vgpu_close(vgpu_device_t device); + +/* Get device info */ +vgpu_error_t vgpu_get_info(vgpu_device_t device, char *buf, size_t len); + +/* ============================================================ + * VF Management + * ============================================================ */ + +/* Create VF */ +vgpu_error_t vgpu_vf_create(vgpu_device_t device, const vgpu_vf_config_t *config, vgpu_vf_t *vf); + +/* Destroy VF */ +vgpu_error_t vgpu_vf_destroy(vgpu_vf_t vf); + +/* Get VF info */ +vgpu_error_t vgpu_vf_get_info(vgpu_vf_t vf, char *buf, size_t len); + +/* ============================================================ + * Memory Management + * ============================================================ */ + +/* Allocate GPU memory */ +vgpu_error_t vgpu_mem_alloc(vgpu_vf_t vf, uint64_t size, vgpu_mem_type_t type, + uint64_t alignment, uint64_t va_hint, + uint32_t flags, vgpu_handle_t *handle, uint64_t *va); + +/* Free GPU memory */ +vgpu_error_t vgpu_mem_free(vgpu_vf_t vf, vgpu_handle_t handle); + +/* Map memory to VF address space */ +vgpu_error_t vgpu_mem_map(vgpu_vf_t vf, vgpu_handle_t handle, uint64_t gpu_va, + uint64_t size, uint32_t prot, uint32_t flags, + uint64_t offset, uint64_t *mapped_va); + +/* Unmap memory */ +vgpu_error_t vgpu_mem_unmap(vgpu_vf_t vf, vgpu_handle_t handle, uint64_t gpu_va, uint64_t size); + +/* Pin pages for DMA */ +vgpu_error_t vgpu_mem_pin(vgpu_vf_t vf, vgpu_handle_t handle, uint64_t offset, + uint64_t size, uint32_t flags, uint64_t *dma_addr); + +/* Unpin pages */ +vgpu_error_t vgpu_mem_unpin(vgpu_vf_t vf, vgpu_handle_t handle, uint64_t offset, uint64_t size); + +/* ============================================================ + * BAR Emulation + * ============================================================ */ + +/* Configure BAR1 aperture */ +vgpu_error_t vgpu_bar_config(vgpu_vf_t vf, uint64_t offset, uint64_t size); + +/* Enable/disable ForceBarAccess */ +vgpu_error_t vgpu_bar_force_access(vgpu_vf_t vf, bool enable); + +/* Save BAR state for migration */ +vgpu_error_t vgpu_bar_save(vgpu_vf_t vf, void *buf, size_t *size); + +/* Restore BAR state after migration */ +vgpu_error_t vgpu_bar_restore(vgpu_vf_t vf, const void *buf, size_t size); + +/* ============================================================ + * WPR (Write/Read Protect Region) + * ============================================================ */ + +/* Protect memory region (write) */ +vgpu_error_t vgpu_wpr_protect_write(vgpu_vf_t vf, uint64_t base, uint64_t size); + +/* Protect memory region (read) */ +vgpu_error_t vgpu_wpr_protect_read(vgpu_vf_t vf, uint64_t base, uint64_t size); + +/* Unprotect memory region */ +vgpu_error_t vgpu_wpr_unprotect(vgpu_vf_t vf, uint64_t base); + +/* Set WPR timeout */ +vgpu_error_t vgpu_wpr_set_timeout(vgpu_vf_t vf, uint64_t timeout_ns); + +/* Register WPR callback */ +typedef void (*vgpu_wpr_callback_t)(vgpu_vf_t vf, uint64_t addr, uint32_t type, void *ctx); +vgpu_error_t vgpu_wpr_register_callback(vgpu_vf_t vf, uint32_t event_type, + vgpu_wpr_callback_t cb, void *ctx); + +/* ============================================================ + * Scheduling + * ============================================================ */ + +/* Schedule work on VF */ +vgpu_error_t vgpu_schedule(vgpu_vf_t vf, uint64_t work_handle, uint64_t callback, + uint64_t arg, uint32_t priority, uint32_t flags); + +/* Yield VF timeslice */ +vgpu_error_t vgpu_yield(vgpu_vf_t vf); + +/* ============================================================ + * Migration + * ============================================================ */ + +/* Start live migration */ +vgpu_error_t vgpu_migrate_start(vgpu_vf_t vf, uint64_t dst_vf, uint32_t flags); + +/* Check migration status */ +vgpu_error_t vgpu_migrate_status(vgpu_vf_t vf, vgpu_mig_phase_t *phase, uint64_t *progress); + +/* Cancel migration */ +vgpu_error_t vgpu_migrate_cancel(vgpu_vf_t vf); + +/* ============================================================ + * Error Handling + * ============================================================ */ + +/* Get error string */ +const char *vgpu_strerror(vgpu_error_t err); + +/* ============================================================ + * Event Handling (async) + * ============================================================ */ + +/* Event types */ +typedef enum { + VGPU_EVENT_WPR_WRITE_COMPLETE = 0, + VGPU_EVENT_WPR_READ_COMPLETE = 1, + VGPU_EVENT_WPR_WRITE_TIMEOUT = 2, + VGPU_EVENT_WPR_READ_TIMEOUT = 3, + VGPU_EVENT_MIGRATION_PROGRESS = 4, + VGPU_EVENT_MIGRATION_COMPLETE = 5, + VGPU_EVENT_VF_ERROR = 6, +} vgpu_event_type_t; + +/* Event callback */ +typedef void (*vgpu_event_callback_t)(vgpu_vf_t vf, vgpu_event_type_t type, + void *data, size_t size, void *ctx); + +/* Register event callback */ +vgpu_error_t vgpu_register_event_callback(vgpu_vf_t vf, vgpu_event_type_t type, + vgpu_event_callback_t cb, void *ctx); + +/* Unregister event callback */ +vgpu_error_t vgpu_unregister_event_callback(vgpu_vf_t vf, vgpu_event_type_t type); + +/* Process pending events (call periodically) */ +vgpu_error_t vgpu_process_events(vgpu_device_t device, int timeout_ms); + +#ifdef __cplusplus +} +#endif + +#endif /* _LIBVGPU_H_ */ \ No newline at end of file diff --git a/userspace/lib/Makefile b/userspace/lib/Makefile new file mode 100644 index 0000000..05bb05b --- /dev/null +++ b/userspace/lib/Makefile @@ -0,0 +1,89 @@ +# libiov - Userspace library for Open-IOV vGPU +# Makefile + +PREFIX ?= /usr/local +LIBDIR ?= $(PREFIX)/lib +INCLUDEDIR ?= $(PREFIX)/include +PKGCONFIGDIR ?= $(LIBDIR)/pkgconfig + +CC ?= gcc +CFLAGS ?= -O2 -g -Wall -Wextra -fPIC -I../include +LDFLAGS ?= -shared + +LIB_NAME = libiov.so +LIB_MAJOR = 1 +LIB_MINOR = 0 +LIB_PATCH = 0 +LIB_VERSION = $(LIB_MAJOR).$(LIB_MINOR).$(LIB_PATCH) +LIB_SONAME = $(LIB_NAME).$(LIB_MAJOR) + +# Compatibility symlinks for libvgpu +COMPAT_NAMES = libvgpu.so libvgpu.so.1 libvgpu.so.1.0.0 + +SRC_DIR = . +OBJ_DIR = obj +SRC = $(SRC_DIR)/libvgpu.c $(SRC_DIR)/rpc_emulator.c +OBJ = $(OBJ_DIR)/libvgpu.o $(OBJ_DIR)/rpc_emulator.o + +HEADERS = ../include/libvgpu.h rpc_emulator.h + +all: $(OBJ_DIR) $(LIB_NAME) compat-links + +$(OBJ_DIR): + mkdir -p $(OBJ_DIR) + +$(OBJ_DIR)/%.o: $(SRC_DIR)/%.c $(HEADERS) + $(CC) $(CFLAGS) -c $< -o $@ + +$(LIB_NAME): $(OBJ) + $(CC) $(LDFLAGS) -Wl,-soname,$(LIB_SONAME) -o $@ $^ + ln -sf $(LIB_NAME) $(LIB_SONAME) + ln -sf $(LIB_NAME) $(LIB_NAME).$(LIB_VERSION) + +# Create compatibility symlinks for libvgpu +compat-links: $(LIB_NAME) + @for link in $(COMPAT_NAMES); do \ + ln -sf $(LIB_NAME) $$link; \ + done + +install: all + install -d $(DESTDIR)$(LIBDIR) + install -d $(DESTDIR)$(INCLUDEDIR) + install -d $(DESTDIR)$(PKGCONFIGDIR) + install -m 755 $(LIB_NAME) $(DESTDIR)$(LIBDIR)/$(LIB_NAME).$(LIB_VERSION) + ln -sf $(LIB_NAME).$(LIB_VERSION) $(DESTDIR)$(LIBDIR)/$(LIB_SONAME) + ln -sf $(LIB_NAME).$(LIB_VERSION) $(DESTDIR)$(LIBDIR)/$(LIB_NAME) + # Install compatibility symlinks + @for link in $(COMPAT_NAMES); do \ + ln -sf $(LIB_NAME).$(LIB_VERSION) $(DESTDIR)$(LIBDIR)/$$link; \ + done + install -m 644 $(HEADERS) $(DESTDIR)$(INCLUDEDIR)/ + sed -e "s|@PREFIX@|$(PREFIX)|g" \ + -e "s|@LIBDIR@|$(LIBDIR)|g" \ + -e "s|@INCLUDEDIR@|$(INCLUDEDIR)|g" \ + -e "s|@VERSION@|$(LIB_VERSION)|g" \ + libvgpu.pc.in > $(DESTDIR)$(PKGCONFIGDIR)/libvgpu.pc + # Also create libiov.pc + sed -e "s|@PREFIX@|$(PREFIX)|g" \ + -e "s|@LIBDIR@|$(LIBDIR)|g" \ + -e "s|@INCLUDEDIR@|$(INCLUDEDIR)|g" \ + -e "s|@VERSION@|$(LIB_VERSION)|g" \ + -e "s|libvgpu|libiov|g" \ + libvgpu.pc.in > $(DESTDIR)$(PKGCONFIGDIR)/libiov.pc + +uninstall: + rm -f $(DESTDIR)$(LIBDIR)/$(LIB_NAME) + rm -f $(DESTDIR)$(LIBDIR)/$(LIB_SONAME) + rm -f $(DESTDIR)$(LIBDIR)/$(LIB_NAME).$(LIB_VERSION) + @for link in $(COMPAT_NAMES); do \ + rm -f $(DESTDIR)$(LIBDIR)/$$link; \ + done + rm -f $(DESTDIR)$(INCLUDEDIR)/libvgpu.h + rm -f $(DESTDIR)$(INCLUDEDIR)/rpc_emulator.h + rm -f $(DESTDIR)$(PKGCONFIGDIR)/libvgpu.pc + rm -f $(DESTDIR)$(PKGCONFIGDIR)/libiov.pc + +clean: + rm -rf $(OBJ_DIR) $(LIB_NAME) $(LIB_SONAME) $(LIB_NAME).$(LIB_VERSION) $(COMPAT_NAMES) + +.PHONY: all install uninstall clean compat-links \ No newline at end of file diff --git a/userspace/lib/libiov.pc.in b/userspace/lib/libiov.pc.in new file mode 100644 index 0000000..ddc1fc3 --- /dev/null +++ b/userspace/lib/libiov.pc.in @@ -0,0 +1,10 @@ +prefix=@PREFIX@ +exec_prefix=${prefix} +libdir=@LIBDIR@ +includedir=@INCLUDEDIR@ + +Name: libiov +Description: Open-IOV vGPU Userspace Library +Version: @VERSION@ +Libs: -L${libdir} -liov +Cflags: -I${includedir} \ No newline at end of file diff --git a/userspace/lib/libiov.so.1 b/userspace/lib/libiov.so.1 new file mode 120000 index 0000000..2622cee --- /dev/null +++ b/userspace/lib/libiov.so.1 @@ -0,0 +1 @@ +libiov.so \ No newline at end of file diff --git a/userspace/lib/libiov.so.1.0.0 b/userspace/lib/libiov.so.1.0.0 new file mode 120000 index 0000000..2622cee --- /dev/null +++ b/userspace/lib/libiov.so.1.0.0 @@ -0,0 +1 @@ +libiov.so \ No newline at end of file diff --git a/userspace/lib/libvgpu.c b/userspace/lib/libvgpu.c new file mode 100644 index 0000000..a25a228 --- /dev/null +++ b/userspace/lib/libvgpu.c @@ -0,0 +1,894 @@ +/* + * GSP vGPU-IO Userspace Library Implementation + */ + +#define _GNU_SOURCE +#include "libvgpu.h" +#include "rpc_emulator.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* IOCTL definitions (must match kernel driver) */ +#define GSP_IOCTL_MAGIC 'G' +#define GSP_IOCTL_CREATE_VF _IOW(GSP_IOCTL_MAGIC, 0x01, struct gsp_vf_config) +#define GSP_IOCTL_DESTROY_VF _IOW(GSP_IOCTL_MAGIC, 0x02, uint32_t) +#define GSP_IOCTL_ALLOC _IOWR(GSP_IOCTL_MAGIC, 0x10, struct gsp_alloc_args) +#define GSP_IOCTL_FREE _IOW(GSP_IOCTL_MAGIC, 0x11, struct gsp_free_args) +#define GSP_IOCTL_MAP _IOWR(GSP_IOCTL_MAGIC, 0x12, struct gsp_map_args) +#define GSP_IOCTL_UNMAP _IOW(GSP_IOCTL_MAGIC, 0x13, struct gsp_unmap_args) +#define GSP_IOCTL_PIN _IOWR(GSP_IOCTL_MAGIC, 0x14, struct gsp_pin_args) +#define GSP_IOCTL_UNPIN _IOW(GSP_IOCTL_MAGIC, 0x15, struct gsp_unpin_args) +#define GSP_IOCTL_BAR_CONFIG _IOWR(GSP_IOCTL_MAGIC, 0x16, struct gsp_bar_config_args) +#define GSP_IOCTL_BAR_FORCE _IOW(GSP_IOCTL_MAGIC, 0x17, struct gsp_bar_force_args) +#define GSP_IOCTL_BAR_SAVE _IOWR(GSP_IOCTL_MAGIC, 0x18, struct gsp_bar_save_args) +#define GSP_IOCTL_BAR_RESTORE _IOW(GSP_IOCTL_MAGIC, 0x19, struct gsp_bar_restore_args) +#define GSP_IOCTL_WPR_PROTECT _IOWR(GSP_IOCTL_MAGIC, 0x1A, struct gsp_wpr_args) +#define GSP_IOCTL_WPR_UNPROTECT _IOW(GSP_IOCTL_MAGIC, 0x1B, struct gsp_wpr_args) +#define GSP_IOCTL_WPR_TIMEOUT _IOW(GSP_IOCTL_MAGIC, 0x1C, struct gsp_wpr_timeout_args) +#define GSP_IOCTL_SCHEDULE _IOW(GSP_IOCTL_MAGIC, 0x1D, struct gsp_schedule_args) +#define GSP_IOCTL_YIELD _IOW(GSP_IOCTL_MAGIC, 0x1E, uint32_t) +#define GSP_IOCTL_MIGRATE _IOWR(GSP_IOCTL_MAGIC, 0x1F, struct gsp_migrate_args) +#define GSP_IOCTL_GET_INFO _IOR(GSP_IOCTL_MAGIC, 0x20, char[256]) + +/* Kernel argument structures */ +struct gsp_vf_config { + uint32_t id; + uint64_t bar1_offset; + uint64_t bar1_size; + uint64_t pt_base; + uint64_t pt_size; + uint64_t cmd_base; + uint64_t cmd_size; + uint32_t max_memory_mb; + uint32_t num_engines; +}; + +struct gsp_alloc_args { + uint32_t vf_id; + uint64_t size; + uint32_t type; + uint64_t alignment; + uint64_t va_hint; + uint32_t flags; + uint32_t pid; + uint64_t handle; + uint64_t va; + uint64_t actual_size; +}; + +struct gsp_free_args { + uint32_t vf_id; + uint64_t handle; +}; + +struct gsp_map_args { + uint32_t vf_id; + uint64_t handle; + uint64_t gpu_va; + uint64_t size; + uint32_t prot; + uint32_t flags; + uint64_t offset; + uint64_t mapped_va; +}; + +struct gsp_unmap_args { + uint32_t vf_id; + uint64_t handle; + uint64_t gpu_va; + uint64_t size; +}; + +struct gsp_pin_args { + uint32_t vf_id; + uint64_t handle; + uint64_t offset; + uint64_t size; + uint32_t flags; + uint64_t dma_addr; + uint32_t num_pages; +}; + +struct gsp_unpin_args { + uint32_t vf_id; + uint64_t handle; + uint64_t offset; + uint64_t size; +}; + +struct gsp_bar_config_args { + uint32_t vf_id; + uint64_t offset; + uint64_t size; +}; + +struct gsp_bar_force_args { + uint32_t vf_id; + uint32_t enable; +}; + +struct gsp_bar_save_args { + uint32_t vf_id; + void *buf; + size_t *size; +}; + +struct gsp_bar_restore_args { + uint32_t vf_id; + const void *buf; + size_t size; +}; + +struct gsp_wpr_args { + uint32_t vf_id; + uint64_t base; + uint64_t size; + uint32_t flags; +}; + +struct gsp_wpr_timeout_args { + uint32_t vf_id; + uint64_t timeout_ns; +}; + +struct gsp_schedule_args { + uint32_t vf_id; + uint64_t work_handle; + uint64_t callback; + uint64_t arg; + uint32_t priority; + uint32_t flags; +}; + +struct gsp_migrate_args { + uint32_t vf_id; + uint32_t phase; + uint32_t subcmd; + uint64_t src_vf; + uint64_t dst_vf; + uint64_t data_ptr; + uint64_t data_size; + uint32_t flags; + uint64_t token; +}; + +/* Internal structures */ +struct vgpu_device { + int fd; + char path[256]; + pthread_mutex_t lock; + pthread_t event_thread; + bool event_thread_running; + vgpu_event_callback_t event_cb; + void *event_ctx; + bool emulation_enabled; +}; + +struct vgpu_vf { + vgpu_device_t device; + uint32_t id; +}; + +/* Error mapping */ +static vgpu_error_t map_errno(int err) +{ + switch (err) { + case 0: return VGPU_OK; + case EINVAL: return VGPU_ERR_INVALID_ARG; + case ENODEV: return VGPU_ERR_NO_DEVICE; + case ENOMEM: return VGPU_ERR_NO_MEMORY; + case EBUSY: return VGPU_ERR_BUSY; + case ETIMEDOUT: return VGPU_ERR_TIMEOUT; + case EPERM: return VGPU_ERR_PERMISSION; + case ENOTSUP: return VGPU_ERR_NOT_SUPPORTED; + default: return VGPU_ERR_INTERNAL; + } +} + +/* ============================================================ + * Device Management + * ============================================================ */ + +vgpu_error_t vgpu_open(const char *device_path, vgpu_device_t *device) +{ + if (!device_path || !device) + return VGPU_ERR_INVALID_ARG; + + struct vgpu_device *dev = calloc(1, sizeof(*dev)); + if (!dev) + return VGPU_ERR_NO_MEMORY; + + dev->fd = open(device_path, O_RDWR | O_CLOEXEC); + if (dev->fd < 0) { + free(dev); + return map_errno(errno); + } + + strncpy(dev->path, device_path, sizeof(dev->path) - 1); + pthread_mutex_init(&dev->lock, NULL); + + /* Initialize RPC emulator for fallback when GSP lacks vGPU handlers */ + rpc_emu_init(); + dev->emulation_enabled = true; + rpc_emu_enable(true); + + *device = dev; + return VGPU_OK; +} + +void vgpu_close(vgpu_device_t device) +{ + if (!device) + return; + + struct vgpu_device *dev = device; + + if (dev->event_thread_running) { + dev->event_thread_running = false; + pthread_join(dev->event_thread, NULL); + } + + if (dev->emulation_enabled) { + rpc_emu_fini(); + dev->emulation_enabled = false; + } + + pthread_mutex_destroy(&dev->lock); + close(dev->fd); + free(dev); +} + +vgpu_error_t vgpu_get_info(vgpu_device_t device, char *buf, size_t len) +{ + if (!device || !buf || len == 0) + return VGPU_ERR_INVALID_ARG; + + struct vgpu_device *dev = device; + int ret = ioctl(dev->fd, GSP_IOCTL_GET_INFO, buf); + return map_errno(ret < 0 ? errno : 0); +} + +/* ============================================================ + * VF Management + * ============================================================ */ + +vgpu_error_t vgpu_vf_create(vgpu_device_t device, const vgpu_vf_config_t *config, vgpu_vf_t *vf) +{ + if (!device || !config || !vf) + return VGPU_ERR_INVALID_ARG; + + struct vgpu_device *dev = device; + struct gsp_vf_config kconfig = {0}; + + kconfig.id = config->id; + kconfig.bar1_offset = config->bar1_offset; + kconfig.bar1_size = config->bar1_size; + kconfig.pt_base = config->pt_base; + kconfig.pt_size = config->pt_size; + kconfig.cmd_base = config->cmd_base; + kconfig.cmd_size = config->cmd_size; + kconfig.max_memory_mb = config->max_memory_mb; + kconfig.num_engines = config->num_engines; + + pthread_mutex_lock(&dev->lock); + int ret = ioctl(dev->fd, GSP_IOCTL_CREATE_VF, &kconfig); + pthread_mutex_unlock(&dev->lock); + + if (ret < 0) + return map_errno(errno); + + struct vgpu_vf *v = calloc(1, sizeof(*v)); + if (!v) + return VGPU_ERR_NO_MEMORY; + + v->device = dev; + v->id = config->id; + *vf = v; + return VGPU_OK; +} + +vgpu_error_t vgpu_vf_destroy(vgpu_vf_t vf) +{ + if (!vf) + return VGPU_ERR_INVALID_ARG; + + struct vgpu_device *dev = vf->device; + uint32_t id = vf->id; + + pthread_mutex_lock(&dev->lock); + int ret = ioctl(dev->fd, GSP_IOCTL_DESTROY_VF, &id); + pthread_mutex_unlock(&dev->lock); + + free(vf); + return map_errno(ret < 0 ? errno : 0); +} + +vgpu_error_t vgpu_vf_get_info(vgpu_vf_t vf, char *buf, size_t len) +{ + if (!vf || !buf || len == 0) + return VGPU_ERR_INVALID_ARG; + + /* VF-specific info would require a new ioctl */ + snprintf(buf, len, "VF %u", vf->id); + return VGPU_OK; +} + +/* ============================================================ + * Memory Management + * ============================================================ */ + +vgpu_error_t vgpu_mem_alloc(vgpu_vf_t vf, uint64_t size, vgpu_mem_type_t type, + uint64_t alignment, uint64_t va_hint, + uint32_t flags, vgpu_handle_t *handle, uint64_t *va) +{ + if (!vf || !handle || !va) + return VGPU_ERR_INVALID_ARG; + + struct vgpu_device *dev = vf->device; + struct gsp_alloc_args args = {0}; + + args.vf_id = vf->id; + args.size = size; + args.type = type; + args.alignment = alignment; + args.va_hint = va_hint; + args.flags = flags; + args.pid = getpid(); + + pthread_mutex_lock(&dev->lock); + int ret = ioctl(dev->fd, GSP_IOCTL_ALLOC, &args); + pthread_mutex_unlock(&dev->lock); + + if (ret < 0) + return map_errno(errno); + + *handle = args.handle; + *va = args.va; + return VGPU_OK; +} + +vgpu_error_t vgpu_mem_free(vgpu_vf_t vf, vgpu_handle_t handle) +{ + if (!vf) + return VGPU_ERR_INVALID_ARG; + + struct vgpu_device *dev = vf->device; + struct gsp_free_args args = {0}; + + args.vf_id = vf->id; + args.handle = handle; + + pthread_mutex_lock(&dev->lock); + int ret = ioctl(dev->fd, GSP_IOCTL_FREE, &args); + pthread_mutex_unlock(&dev->lock); + + return map_errno(ret < 0 ? errno : 0); +} + +vgpu_error_t vgpu_mem_map(vgpu_vf_t vf, vgpu_handle_t handle, uint64_t gpu_va, + uint64_t size, uint32_t prot, uint32_t flags, + uint64_t offset, uint64_t *mapped_va) +{ + if (!vf || !mapped_va) + return VGPU_ERR_INVALID_ARG; + + struct vgpu_device *dev = vf->device; + struct gsp_map_args args = {0}; + + args.vf_id = vf->id; + args.handle = handle; + args.gpu_va = gpu_va; + args.size = size; + args.prot = prot; + args.flags = flags; + args.offset = offset; + + pthread_mutex_lock(&dev->lock); + int ret = ioctl(dev->fd, GSP_IOCTL_MAP, &args); + pthread_mutex_unlock(&dev->lock); + + if (ret < 0) + return map_errno(errno); + + *mapped_va = args.mapped_va; + return VGPU_OK; +} + +vgpu_error_t vgpu_mem_unmap(vgpu_vf_t vf, vgpu_handle_t handle, uint64_t gpu_va, uint64_t size) +{ + if (!vf) + return VGPU_ERR_INVALID_ARG; + + struct vgpu_device *dev = vf->device; + struct gsp_unmap_args args = {0}; + + args.vf_id = vf->id; + args.handle = handle; + args.gpu_va = gpu_va; + args.size = size; + + pthread_mutex_lock(&dev->lock); + int ret = ioctl(dev->fd, GSP_IOCTL_UNMAP, &args); + pthread_mutex_unlock(&dev->lock); + + return map_errno(ret < 0 ? errno : 0); +} + +vgpu_error_t vgpu_mem_pin(vgpu_vf_t vf, vgpu_handle_t handle, uint64_t offset, + uint64_t size, uint32_t flags, uint64_t *dma_addr) +{ + if (!vf || !dma_addr) + return VGPU_ERR_INVALID_ARG; + + struct vgpu_device *dev = vf->device; + struct gsp_pin_args args = {0}; + + args.vf_id = vf->id; + args.handle = handle; + args.offset = offset; + args.size = size; + args.flags = flags; + + pthread_mutex_lock(&dev->lock); + int ret = ioctl(dev->fd, GSP_IOCTL_PIN, &args); + pthread_mutex_unlock(&dev->lock); + + if (ret < 0) + return map_errno(errno); + + *dma_addr = args.dma_addr; + return VGPU_OK; +} + +vgpu_error_t vgpu_mem_unpin(vgpu_vf_t vf, vgpu_handle_t handle, uint64_t offset, uint64_t size) +{ + if (!vf) + return VGPU_ERR_INVALID_ARG; + + struct vgpu_device *dev = vf->device; + struct gsp_unpin_args args = {0}; + + args.vf_id = vf->id; + args.handle = handle; + args.offset = offset; + args.size = size; + + pthread_mutex_lock(&dev->lock); + int ret = ioctl(dev->fd, GSP_IOCTL_UNPIN, &args); + pthread_mutex_unlock(&dev->lock); + + return map_errno(ret < 0 ? errno : 0); +} + +/* ============================================================ + * BAR Emulation + * ============================================================ */ + +static vgpu_error_t bar_fallback(struct vgpu_device *dev, vgpu_vf_t vf, int ioctl_err, int (*emu_fn)(uint32_t, uint64_t, uint64_t)) +{ + if (dev->emulation_enabled && (ioctl_err == ENOTSUP || ioctl_err == ETIMEDOUT || ioctl_err == EIO)) { + int ret = emu_fn(vf->id, 0, 0); /* Will be overridden below */ + return map_errno(ret); + } + return map_errno(ioctl_err); +} + +vgpu_error_t vgpu_bar_config(vgpu_vf_t vf, uint64_t offset, uint64_t size) +{ + if (!vf) + return VGPU_ERR_INVALID_ARG; + + struct vgpu_device *dev = vf->device; + struct gsp_bar_config_args args = {0}; + + args.vf_id = vf->id; + args.offset = offset; + args.size = size; + + pthread_mutex_lock(&dev->lock); + int ret = ioctl(dev->fd, GSP_IOCTL_BAR_CONFIG, &args); + int ioctl_err = ret < 0 ? errno : 0; + pthread_mutex_unlock(&dev->lock); + + if (ret == 0) + return VGPU_OK; + + /* Fallback to userspace emulator if GSP lacks vGPU RPC handlers */ + if (dev->emulation_enabled && (ioctl_err == ENOTSUP || ioctl_err == ETIMEDOUT || ioctl_err == EIO)) { + int emu_ret = rpc_emu_bar_config(vf->id, offset, size); + return map_errno(emu_ret); + } + + return map_errno(ioctl_err); +} + +vgpu_error_t vgpu_bar_force_access(vgpu_vf_t vf, bool enable) +{ + if (!vf) + return VGPU_ERR_INVALID_ARG; + + struct vgpu_device *dev = vf->device; + struct gsp_bar_force_args args = {0}; + + args.vf_id = vf->id; + args.enable = enable ? 1 : 0; + + pthread_mutex_lock(&dev->lock); + int ret = ioctl(dev->fd, GSP_IOCTL_BAR_FORCE, &args); + int ioctl_err = ret < 0 ? errno : 0; + pthread_mutex_unlock(&dev->lock); + + if (ret == 0) + return VGPU_OK; + + if (dev->emulation_enabled && (ioctl_err == ENOTSUP || ioctl_err == ETIMEDOUT || ioctl_err == EIO)) { + int emu_ret = rpc_emu_bar_force_access(vf->id, enable); + return map_errno(emu_ret); + } + + return map_errno(ioctl_err); +} + +vgpu_error_t vgpu_bar_save(vgpu_vf_t vf, void *buf, size_t *size) +{ + if (!vf || !buf || !size) + return VGPU_ERR_INVALID_ARG; + + struct vgpu_device *dev = vf->device; + struct gsp_bar_save_args args = {0}; + + args.vf_id = vf->id; + args.buf = buf; + args.size = size; + + pthread_mutex_lock(&dev->lock); + int ret = ioctl(dev->fd, GSP_IOCTL_BAR_SAVE, &args); + int ioctl_err = ret < 0 ? errno : 0; + pthread_mutex_unlock(&dev->lock); + + if (ret == 0) + return VGPU_OK; + + if (dev->emulation_enabled && (ioctl_err == ENOTSUP || ioctl_err == ETIMEDOUT || ioctl_err == EIO)) { + int emu_ret = rpc_emu_bar_save(vf->id, buf, size); + return map_errno(emu_ret); + } + + return map_errno(ioctl_err); +} + +vgpu_error_t vgpu_bar_restore(vgpu_vf_t vf, const void *buf, size_t size) +{ + if (!vf || !buf) + return VGPU_ERR_INVALID_ARG; + + struct vgpu_device *dev = vf->device; + struct gsp_bar_restore_args args = {0}; + + args.vf_id = vf->id; + args.buf = buf; + args.size = size; + + pthread_mutex_lock(&dev->lock); + int ret = ioctl(dev->fd, GSP_IOCTL_BAR_RESTORE, &args); + int ioctl_err = ret < 0 ? errno : 0; + pthread_mutex_unlock(&dev->lock); + + if (ret == 0) + return VGPU_OK; + + if (dev->emulation_enabled && (ioctl_err == ENOTSUP || ioctl_err == ETIMEDOUT || ioctl_err == EIO)) { + int emu_ret = rpc_emu_bar_restore(vf->id, buf, size); + return map_errno(emu_ret); + } + + return map_errno(ioctl_err); +} + +/* ============================================================ + * WPR Management + * ============================================================ */ + +vgpu_error_t vgpu_wpr_protect_write(vgpu_vf_t vf, uint64_t base, uint64_t size) +{ + if (!vf) + return VGPU_ERR_INVALID_ARG; + + struct vgpu_device *dev = vf->device; + struct gsp_wpr_args args = {0}; + + args.vf_id = vf->id; + args.base = base; + args.size = size; + args.flags = VGPU_WPR_WRITE; + + pthread_mutex_lock(&dev->lock); + int ret = ioctl(dev->fd, GSP_IOCTL_WPR_PROTECT, &args); + int ioctl_err = ret < 0 ? errno : 0; + pthread_mutex_unlock(&dev->lock); + + if (ret == 0) + return VGPU_OK; + + if (dev->emulation_enabled && (ioctl_err == ENOTSUP || ioctl_err == ETIMEDOUT || ioctl_err == EIO)) { + int emu_ret = rpc_emu_wpr_protect_write(vf->id, base, size); + return map_errno(emu_ret); + } + + return map_errno(ioctl_err); +} + +vgpu_error_t vgpu_wpr_protect_read(vgpu_vf_t vf, uint64_t base, uint64_t size) +{ + if (!vf) + return VGPU_ERR_INVALID_ARG; + + struct vgpu_device *dev = vf->device; + struct gsp_wpr_args args = {0}; + + args.vf_id = vf->id; + args.base = base; + args.size = size; + args.flags = VGPU_WPR_READ; + + pthread_mutex_lock(&dev->lock); + int ret = ioctl(dev->fd, GSP_IOCTL_WPR_PROTECT, &args); + int ioctl_err = ret < 0 ? errno : 0; + pthread_mutex_unlock(&dev->lock); + + if (ret == 0) + return VGPU_OK; + + if (dev->emulation_enabled && (ioctl_err == ENOTSUP || ioctl_err == ETIMEDOUT || ioctl_err == EIO)) { + int emu_ret = rpc_emu_wpr_protect_read(vf->id, base, size); + return map_errno(emu_ret); + } + + return map_errno(ioctl_err); +} + +vgpu_error_t vgpu_wpr_unprotect(vgpu_vf_t vf, uint64_t base) +{ + if (!vf) + return VGPU_ERR_INVALID_ARG; + + struct vgpu_device *dev = vf->device; + struct gsp_wpr_args args = {0}; + + args.vf_id = vf->id; + args.base = base; + args.size = 0; + args.flags = 0; + + pthread_mutex_lock(&dev->lock); + int ret = ioctl(dev->fd, GSP_IOCTL_WPR_UNPROTECT, &args); + int ioctl_err = ret < 0 ? errno : 0; + pthread_mutex_unlock(&dev->lock); + + if (ret == 0) + return VGPU_OK; + + if (dev->emulation_enabled && (ioctl_err == ENOTSUP || ioctl_err == ETIMEDOUT || ioctl_err == EIO)) { + int emu_ret = rpc_emu_wpr_unprotect(vf->id, base); + return map_errno(emu_ret); + } + + return map_errno(ioctl_err); +} + +vgpu_error_t vgpu_wpr_set_timeout(vgpu_vf_t vf, uint64_t timeout_ns) +{ + if (!vf) + return VGPU_ERR_INVALID_ARG; + + struct vgpu_device *dev = vf->device; + struct gsp_wpr_timeout_args args = {0}; + + args.vf_id = vf->id; + args.timeout_ns = timeout_ns; + + pthread_mutex_lock(&dev->lock); + int ret = ioctl(dev->fd, GSP_IOCTL_WPR_TIMEOUT, &args); + int ioctl_err = ret < 0 ? errno : 0; + pthread_mutex_unlock(&dev->lock); + + if (ret == 0) + return VGPU_OK; + + if (dev->emulation_enabled && (ioctl_err == ENOTSUP || ioctl_err == ETIMEDOUT || ioctl_err == EIO)) { + int emu_ret = rpc_emu_wpr_set_timeout(vf->id, timeout_ns); + return map_errno(emu_ret); + } + + return map_errno(ioctl_err); +} + +vgpu_error_t vgpu_wpr_register_callback(vgpu_vf_t vf, uint32_t event_type, + vgpu_wpr_callback_t cb, void *ctx) +{ + /* Callback registration would require kernel support for eventfd or similar */ + (void)vf; (void)event_type; (void)cb; (void)ctx; + return VGPU_ERR_NOT_SUPPORTED; +} + +/* ============================================================ + * Scheduling + * ============================================================ */ + +vgpu_error_t vgpu_schedule(vgpu_vf_t vf, uint64_t work_handle, uint64_t callback, + uint64_t arg, uint32_t priority, uint32_t flags) +{ + if (!vf) + return VGPU_ERR_INVALID_ARG; + + struct vgpu_device *dev = vf->device; + struct gsp_schedule_args args = {0}; + + args.vf_id = vf->id; + args.work_handle = work_handle; + args.callback = callback; + args.arg = arg; + args.priority = priority; + args.flags = flags; + + pthread_mutex_lock(&dev->lock); + int ret = ioctl(dev->fd, GSP_IOCTL_SCHEDULE, &args); + int ioctl_err = ret < 0 ? errno : 0; + pthread_mutex_unlock(&dev->lock); + + if (ret == 0) + return VGPU_OK; + + /* Fallback to userspace emulator if GSP lacks vGPU RPC handlers */ + if (dev->emulation_enabled && (ioctl_err == ENOTSUP || ioctl_err == ETIMEDOUT || ioctl_err == EIO)) { + int emu_ret = rpc_emu_schedule(vf->id, work_handle, callback, arg, priority, flags); + return map_errno(emu_ret); + } + + return map_errno(ioctl_err); +} + +vgpu_error_t vgpu_yield(vgpu_vf_t vf) +{ + if (!vf) + return VGPU_ERR_INVALID_ARG; + + struct vgpu_device *dev = vf->device; + uint32_t id = vf->id; + + pthread_mutex_lock(&dev->lock); + int ret = ioctl(dev->fd, GSP_IOCTL_YIELD, &id); + int ioctl_err = ret < 0 ? errno : 0; + pthread_mutex_unlock(&dev->lock); + + if (ret == 0) + return VGPU_OK; + + if (dev->emulation_enabled && (ioctl_err == ENOTSUP || ioctl_err == ETIMEDOUT || ioctl_err == EIO)) { + int emu_ret = rpc_emu_yield(vf->id); + return map_errno(emu_ret); + } + + return map_errno(ioctl_err); +} + +/* ============================================================ + * Migration + * ============================================================ */ + +vgpu_error_t vgpu_migrate_start(vgpu_vf_t vf, uint64_t dst_vf, uint32_t flags) +{ + if (!vf) + return VGPU_ERR_INVALID_ARG; + + struct vgpu_device *dev = vf->device; + struct gsp_migrate_args args = {0}; + + args.vf_id = vf->id; + args.phase = VGPU_MIG_PREPARE; + args.subcmd = 3; /* Quiesce */ + args.src_vf = vf->id; + args.dst_vf = dst_vf; + args.flags = flags; + + pthread_mutex_lock(&dev->lock); + int ret = ioctl(dev->fd, GSP_IOCTL_MIGRATE, &args); + pthread_mutex_unlock(&dev->lock); + + return map_errno(ret < 0 ? errno : 0); +} + +vgpu_error_t vgpu_migrate_status(vgpu_vf_t vf, vgpu_mig_phase_t *phase, uint64_t *progress) +{ + /* Migration status would require a query ioctl */ + (void)vf; (void)phase; (void)progress; + return VGPU_ERR_NOT_SUPPORTED; +} + +vgpu_error_t vgpu_migrate_cancel(vgpu_vf_t vf) +{ + /* Migration cancel would require a cancel ioctl */ + (void)vf; + return VGPU_ERR_NOT_SUPPORTED; +} + +/* ============================================================ + * Error Handling + * ============================================================ */ + +const char *vgpu_strerror(vgpu_error_t err) +{ + switch (err) { + case VGPU_OK: return "Success"; + case VGPU_ERR_INVALID_ARG: return "Invalid argument"; + case VGPU_ERR_NO_DEVICE: return "No such device"; + case VGPU_ERR_NO_MEMORY: return "Out of memory"; + case VGPU_ERR_BUSY: return "Device or resource busy"; + case VGPU_ERR_TIMEOUT: return "Operation timed out"; + case VGPU_ERR_PERMISSION: return "Permission denied"; + case VGPU_ERR_NOT_SUPPORTED: return "Operation not supported"; + case VGPU_ERR_INTERNAL: return "Internal error"; + default: return "Unknown error"; + } +} + +/* ============================================================ + * Event Handling + * ============================================================ */ + +vgpu_error_t vgpu_register_event_callback(vgpu_vf_t vf, vgpu_event_type_t type, + vgpu_event_callback_t cb, void *ctx) +{ + struct vgpu_device *dev = vf->device; + + /* Try kernel ioctl first */ + /* Would need a new ioctl for notification registration */ + + /* Fallback to userspace emulator */ + if (dev->emulation_enabled) { + rpc_emu_notify_cb_t emu_cb = (rpc_emu_notify_cb_t)cb; + int ret = rpc_emu_notify_register(vf->id, type, emu_cb, ctx); + return map_errno(ret); + } + + return VGPU_ERR_NOT_SUPPORTED; +} + +vgpu_error_t vgpu_unregister_event_callback(vgpu_vf_t vf, vgpu_event_type_t type) +{ + struct vgpu_device *dev = vf->device; + + if (dev->emulation_enabled) { + int ret = rpc_emu_notify_unregister(vf->id, type); + return map_errno(ret); + } + + return VGPU_ERR_NOT_SUPPORTED; +} + +vgpu_error_t vgpu_process_events(vgpu_device_t device, int timeout_ms) +{ + if (!device) + return VGPU_ERR_INVALID_ARG; + + struct vgpu_device *dev = device; + struct pollfd pfd = { .fd = dev->fd, .events = POLLIN }; + + int ret = poll(&pfd, 1, timeout_ms); + if (ret < 0) + return map_errno(errno); + + if (ret == 0) + return VGPU_ERR_TIMEOUT; + + /* Process events would read from device */ + return VGPU_OK; +} \ No newline at end of file diff --git a/userspace/lib/libvgpu.pc.in b/userspace/lib/libvgpu.pc.in new file mode 100644 index 0000000..82ba073 --- /dev/null +++ b/userspace/lib/libvgpu.pc.in @@ -0,0 +1,10 @@ +prefix=@PREFIX@ +exec_prefix=${prefix} +libdir=@LIBDIR@ +includedir=@INCLUDEDIR@ + +Name: libvgpu +Description: GSP vGPU-IO Userspace Library +Version: @VERSION@ +Libs: -L${libdir} -lvgpu +Cflags: -I${includedir} \ No newline at end of file diff --git a/userspace/lib/libvgpu.so b/userspace/lib/libvgpu.so new file mode 120000 index 0000000..2622cee --- /dev/null +++ b/userspace/lib/libvgpu.so @@ -0,0 +1 @@ +libiov.so \ No newline at end of file diff --git a/userspace/lib/libvgpu.so.1 b/userspace/lib/libvgpu.so.1 new file mode 120000 index 0000000..2622cee --- /dev/null +++ b/userspace/lib/libvgpu.so.1 @@ -0,0 +1 @@ +libiov.so \ No newline at end of file diff --git a/userspace/lib/libvgpu.so.1.0.0 b/userspace/lib/libvgpu.so.1.0.0 new file mode 120000 index 0000000..2622cee --- /dev/null +++ b/userspace/lib/libvgpu.so.1.0.0 @@ -0,0 +1 @@ +libiov.so \ No newline at end of file diff --git a/userspace/lib/rpc_emulator.c b/userspace/lib/rpc_emulator.c new file mode 100644 index 0000000..9f7f2c7 --- /dev/null +++ b/userspace/lib/rpc_emulator.c @@ -0,0 +1,528 @@ +/* + * GSP vGPU-IO Userspace RPC Emulator + * + * Emulates missing vGPU RPC handlers (BAR_TRAP, WPR, etc.) that exist only + * in GRID host driver GSP firmware. Allows operation with consumer/OpenRM GSP. + */ + +#define _GNU_SOURCE +#include "rpc_emulator.h" +#include +#include +#include +#include +#include +#include +#include + +/* ============================================================ + * BAR Emulation State + * ============================================================ */ + +struct emu_bar_state { + uint64_t aperture_offset; + uint64_t aperture_size; + bool force_access; + uint32_t force_vf; + void *backing_store; + size_t backing_size; + pthread_mutex_t lock; +}; + +static struct emu_bar_state g_bar_state = { + .aperture_offset = 0, + .aperture_size = 0, + .force_access = false, + .force_vf = 0, + .backing_store = NULL, + .backing_size = 0, +}; + +/* ============================================================ + * WPR Emulation State + * ============================================================ */ + +struct emu_wpr_region { + uint64_t base; + uint64_t size; + uint32_t flags; + uint64_t timeout_ns; + struct emu_wpr_region *next; +}; + +struct emu_wpr_state { + struct emu_wpr_region *regions; + pthread_mutex_t lock; +}; + +static struct emu_wpr_state g_wpr_state = { + .regions = NULL, +}; + +/* ============================================================ + * Emulation Mode Control + * ============================================================ */ + +static bool g_emulation_enabled = false; +static pthread_mutex_t g_emu_lock = PTHREAD_MUTEX_INITIALIZER; + +void rpc_emu_enable(bool enable) +{ + pthread_mutex_lock(&g_emu_lock); + g_emulation_enabled = enable; + pthread_mutex_unlock(&g_emu_lock); +} + +bool rpc_emu_is_enabled(void) +{ + bool enabled; + pthread_mutex_lock(&g_emu_lock); + enabled = g_emulation_enabled; + pthread_mutex_unlock(&g_emu_lock); + return enabled; +} + +/* ============================================================ + * BAR Emulation Implementation + * ============================================================ */ + +int rpc_emu_bar_config(uint32_t vf_id, uint64_t offset, uint64_t size) +{ + if (!rpc_emu_is_enabled()) + return -ENOTSUP; + + if (offset & 0xFFF || size & 0xFFF) + return -EINVAL; + + if (size > 0x40000) /* 256KB max per firmware spec */ + return -EINVAL; + + pthread_mutex_lock(&g_bar_state.lock); + + g_bar_state.aperture_offset = offset; + g_bar_state.aperture_size = size; + + /* Allocate/resize backing store */ + if (g_bar_state.backing_store) { + free(g_bar_state.backing_store); + g_bar_state.backing_store = NULL; + g_bar_state.backing_size = 0; + } + + if (size > 0) { + g_bar_state.backing_size = size; + g_bar_state.backing_store = calloc(1, size); + if (!g_bar_state.backing_store) { + g_bar_state.backing_size = 0; + pthread_mutex_unlock(&g_bar_state.lock); + return -ENOMEM; + } + } + + pthread_mutex_unlock(&g_bar_state.lock); + return 0; +} + +int rpc_emu_bar_force_access(uint32_t vf_id, bool enable) +{ + if (!rpc_emu_is_enabled()) + return -ENOTSUP; + + pthread_mutex_lock(&g_bar_state.lock); + g_bar_state.force_access = enable; + g_bar_state.force_vf = enable ? vf_id : 0; + pthread_mutex_unlock(&g_bar_state.lock); + return 0; +} + +int rpc_emu_bar_save(uint32_t vf_id, void *buf, size_t *size) +{ + if (!rpc_emu_is_enabled()) + return -ENOTSUP; + + if (!buf || !size) + return -EINVAL; + + pthread_mutex_lock(&g_bar_state.lock); + + size_t needed = sizeof(struct emu_bar_state) + g_bar_state.backing_size; + if (*size < needed) { + *size = needed; + pthread_mutex_unlock(&g_bar_state.lock); + return -ENOSPC; + } + + memcpy(buf, &g_bar_state, sizeof(struct emu_bar_state)); + if (g_bar_state.backing_store && g_bar_state.backing_size > 0) + memcpy(buf + sizeof(struct emu_bar_state), g_bar_state.backing_store, g_bar_state.backing_size); + + *size = needed; + pthread_mutex_unlock(&g_bar_state.lock); + return 0; +} + +int rpc_emu_bar_restore(uint32_t vf_id, const void *buf, size_t size) +{ + if (!rpc_emu_is_enabled()) + return -ENOTSUP; + + if (!buf || size < sizeof(struct emu_bar_state)) + return -EINVAL; + + pthread_mutex_lock(&g_bar_state.lock); + + memcpy(&g_bar_state, buf, sizeof(struct emu_bar_state)); + + if (size > sizeof(struct emu_bar_state) && g_bar_state.backing_size > 0) { + if (!g_bar_state.backing_store) { + g_bar_state.backing_store = calloc(1, g_bar_state.backing_size); + if (!g_bar_state.backing_store) { + pthread_mutex_unlock(&g_bar_state.lock); + return -ENOMEM; + } + } + memcpy(g_bar_state.backing_store, buf + sizeof(struct emu_bar_state), + size - sizeof(struct emu_bar_state)); + } + + pthread_mutex_unlock(&g_bar_state.lock); + return 0; +} + +int rpc_emu_bar_get_state(uint32_t vf_id, uint64_t *offset, uint64_t *size) +{ + if (!rpc_emu_is_enabled()) + return -ENOTSUP; + + pthread_mutex_lock(&g_bar_state.lock); + if (offset) *offset = g_bar_state.aperture_offset; + if (size) *size = g_bar_state.aperture_size; + pthread_mutex_unlock(&g_bar_state.lock); + return 0; +} + +/* ============================================================ + * WPR Emulation Implementation + * ============================================================ */ + +static struct emu_wpr_region *emu_wpr_find(uint64_t base) +{ + struct emu_wpr_region *rgn = g_wpr_state.regions; + while (rgn) { + if (rgn->base == base) + return rgn; + rgn = rgn->next; + } + return NULL; +} + +static struct emu_wpr_region *emu_wpr_find_containing(uint64_t addr) +{ + struct emu_wpr_region *rgn = g_wpr_state.regions; + while (rgn) { + if (addr >= rgn->base && addr < rgn->base + rgn->size) + return rgn; + rgn = rgn->next; + } + return NULL; +} + +int rpc_emu_wpr_protect_write(uint32_t vf_id, uint64_t base, uint64_t size) +{ + return rpc_emu_wpr_protect(vf_id, base, size, VGPU_WPR_WRITE); +} + +int rpc_emu_wpr_protect_read(uint32_t vf_id, uint64_t base, uint64_t size) +{ + return rpc_emu_wpr_protect(vf_id, base, size, VGPU_WPR_READ); +} + +int rpc_emu_wpr_protect(uint32_t vf_id, uint64_t base, uint64_t size, uint32_t flags) +{ + if (!rpc_emu_is_enabled()) + return -ENOTSUP; + + if (base & 0xFFF || size & 0xFFF) + return -EINVAL; + + pthread_mutex_lock(&g_wpr_state.lock); + + /* Check for overlap */ + struct emu_wpr_region *rgn = g_wpr_state.regions; + while (rgn) { + if (base < rgn->base + rgn->size && base + size > rgn->base) { + pthread_mutex_unlock(&g_wpr_state.lock); + return -EBUSY; /* Overlaps existing region */ + } + rgn = rgn->next; + } + + struct emu_wpr_region *new_rgn = calloc(1, sizeof(*new_rgn)); + if (!new_rgn) { + pthread_mutex_unlock(&g_wpr_state.lock); + return -ENOMEM; + } + + new_rgn->base = base; + new_rgn->size = size; + new_rgn->flags = flags; + new_rgn->timeout_ns = 10000000; /* 10ms default */ + + new_rgn->next = g_wpr_state.regions; + g_wpr_state.regions = new_rgn; + + pthread_mutex_unlock(&g_wpr_state.lock); + return 0; +} + +int rpc_emu_wpr_unprotect(uint32_t vf_id, uint64_t base) +{ + if (!rpc_emu_is_enabled()) + return -ENOTSUP; + + pthread_mutex_lock(&g_wpr_state.lock); + + struct emu_wpr_region **prev = &g_wpr_state.regions; + struct emu_wpr_region *rgn = g_wpr_state.regions; + bool found = false; + + while (rgn) { + if (rgn->base == base) { + *prev = rgn->next; + free(rgn); + found = true; + break; + } + prev = &rgn->next; + rgn = rgn->next; + } + + pthread_mutex_unlock(&g_wpr_state.lock); + return found ? 0 : -ENOENT; +} + +int rpc_emu_wpr_set_timeout(uint32_t vf_id, uint64_t timeout_ns) +{ + if (!rpc_emu_is_enabled()) + return -ENOTSUP; + + pthread_mutex_lock(&g_wpr_state.lock); + struct emu_wpr_region *rgn = g_wpr_state.regions; + while (rgn) { + rgn->timeout_ns = timeout_ns; + rgn = rgn->next; + } + pthread_mutex_unlock(&g_wpr_state.lock); + return 0; +} + +int rpc_emu_wpr_check_access(uint32_t vf_id, uint64_t addr, uint32_t access_type) +{ + if (!rpc_emu_is_enabled()) + return 0; /* Allow if emulation disabled */ + + pthread_mutex_lock(&g_wpr_state.lock); + struct emu_wpr_region *rgn = emu_wpr_find_containing(addr); + int ret = 0; + + if (rgn) { + if ((access_type == VGPU_WPR_WRITE && (rgn->flags & VGPU_WPR_WRITE)) || + (access_type == VGPU_WPR_READ && (rgn->flags & VGPU_WPR_READ))) { + ret = -EPERM; /* Access violation */ + } + } + + pthread_mutex_unlock(&g_wpr_state.lock); + return 0; +} + +/* ============================================================ + * Scheduling Emulation Implementation + * ============================================================ */ + +struct emu_sched_work { + uint64_t work_handle; + uint64_t callback; + uint64_t arg; + uint32_t priority; + uint32_t flags; + struct emu_sched_work *next; +}; + +static struct emu_sched_work *g_sched_queue = NULL; +static pthread_mutex_t g_sched_lock = PTHREAD_MUTEX_INITIALIZER; + +int rpc_emu_schedule(uint32_t vf_id, uint64_t work_handle, uint64_t callback, uint64_t arg, uint32_t priority, uint32_t flags) +{ + if (!rpc_emu_is_enabled()) + return -ENOTSUP; + + struct emu_sched_work *work = calloc(1, sizeof(*work)); + if (!work) + return -ENOMEM; + + work->work_handle = work_handle; + work->callback = callback; + work->arg = arg; + work->priority = priority; + work->flags = flags; + + pthread_mutex_lock(&g_sched_lock); + work->next = g_sched_queue; + g_sched_queue = work; + pthread_mutex_unlock(&g_sched_lock); + + /* In emulation, we just return success - work is queued locally */ + (void)vf_id; + return 0; +} + +int rpc_emu_yield(uint32_t vf_id) +{ + if (!rpc_emu_is_enabled()) + return -ENOTSUP; + + /* In emulation, yield is a no-op */ + (void)vf_id; + return 0; +} + +/* ============================================================ + * Notification Emulation Implementation + * ============================================================ */ + +struct emu_notify_cb { + uint32_t type; + rpc_emu_notify_cb_t callback; + void *ctx; + struct emu_notify_cb *next; +}; + +static struct emu_notify_cb *g_notify_callbacks = NULL; +static pthread_mutex_t g_notify_lock = PTHREAD_MUTEX_INITIALIZER; + +int rpc_emu_notify_register(uint32_t vf_id, uint32_t type, rpc_emu_notify_cb_t cb, void *ctx) +{ + if (!rpc_emu_is_enabled()) + return -ENOTSUP; + + struct emu_notify_cb *nc = calloc(1, sizeof(*nc)); + if (!nc) + return -ENOMEM; + + nc->type = type; + nc->callback = cb; + nc->ctx = ctx; + + pthread_mutex_lock(&g_notify_lock); + nc->next = g_notify_callbacks; + g_notify_callbacks = nc; + pthread_mutex_unlock(&g_notify_lock); + + (void)vf_id; + return 0; +} + +int rpc_emu_notify_unregister(uint32_t vf_id, uint32_t type) +{ + if (!rpc_emu_is_enabled()) + return -ENOTSUP; + + pthread_mutex_lock(&g_notify_lock); + struct emu_notify_cb **prev = &g_notify_callbacks; + struct emu_notify_cb *nc = g_notify_callbacks; + bool found = false; + + while (nc) { + if (nc->type == type) { + *prev = nc->next; + free(nc); + found = true; + break; + } + prev = &nc->next; + nc = nc->next; + } + pthread_mutex_unlock(&g_notify_lock); + + (void)vf_id; + return found ? 0 : -ENOENT; +} + +int rpc_emu_notify_send(uint32_t vf_id, uint32_t type, void *data, size_t size) +{ + if (!rpc_emu_is_enabled()) + return -ENOTSUP; + + pthread_mutex_lock(&g_notify_lock); + struct emu_notify_cb *nc = g_notify_callbacks; + while (nc) { + if (nc->type == type || nc->type == 0) { + nc->callback(vf_id, type, data, size, nc->ctx); + } + nc = nc->next; + } + pthread_mutex_unlock(&g_notify_lock); + + return 0; +} + +/* ============================================================ + * Initialization / Cleanup + * ============================================================ */ + +int rpc_emu_init(void) +{ + pthread_mutex_init(&g_bar_state.lock, NULL); + pthread_mutex_init(&g_wpr_state.lock, NULL); + pthread_mutex_init(&g_sched_lock, NULL); + pthread_mutex_init(&g_notify_lock, NULL); + return 0; +} + +void rpc_emu_fini(void) +{ + pthread_mutex_lock(&g_bar_state.lock); + if (g_bar_state.backing_store) { + free(g_bar_state.backing_store); + g_bar_state.backing_store = NULL; + g_bar_state.backing_size = 0; + } + pthread_mutex_unlock(&g_bar_state.lock); + pthread_mutex_destroy(&g_bar_state.lock); + + pthread_mutex_lock(&g_wpr_state.lock); + struct emu_wpr_region *rgn = g_wpr_state.regions; + while (rgn) { + struct emu_wpr_region *next = rgn->next; + free(rgn); + rgn = next; + } + g_wpr_state.regions = NULL; + pthread_mutex_unlock(&g_wpr_state.lock); + pthread_mutex_destroy(&g_wpr_state.lock); + + pthread_mutex_lock(&g_sched_lock); + struct emu_sched_work *work = g_sched_queue; + while (work) { + struct emu_sched_work *next = work->next; + free(work); + work = next; + } + g_sched_queue = NULL; + pthread_mutex_unlock(&g_sched_lock); + pthread_mutex_destroy(&g_sched_lock); + + pthread_mutex_lock(&g_notify_lock); + struct emu_notify_cb *nc = g_notify_callbacks; + while (nc) { + struct emu_notify_cb *next = nc->next; + free(nc); + nc = next; + } + g_notify_callbacks = NULL; + pthread_mutex_unlock(&g_notify_lock); + pthread_mutex_destroy(&g_notify_lock); + + pthread_mutex_destroy(&g_emu_lock); +} diff --git a/userspace/lib/rpc_emulator.h b/userspace/lib/rpc_emulator.h new file mode 100644 index 0000000..1b641bf --- /dev/null +++ b/userspace/lib/rpc_emulator.h @@ -0,0 +1,53 @@ +/* + * GSP vGPU-IO Userspace RPC Emulator - Header + */ + +#ifndef _RPC_EMULATOR_H_ +#define _RPC_EMULATOR_H_ + +#include +#include +#include "libvgpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Emulation mode control */ +void rpc_emu_enable(bool enable); +bool rpc_emu_is_enabled(void); + +/* BAR Emulation */ +int rpc_emu_bar_config(uint32_t vf_id, uint64_t offset, uint64_t size); +int rpc_emu_bar_force_access(uint32_t vf_id, bool enable); +int rpc_emu_bar_save(uint32_t vf_id, void *buf, size_t *size); +int rpc_emu_bar_restore(uint32_t vf_id, const void *buf, size_t size); +int rpc_emu_bar_get_state(uint32_t vf_id, uint64_t *offset, uint64_t *size); + +/* WPR Emulation */ +int rpc_emu_wpr_protect_write(uint32_t vf_id, uint64_t base, uint64_t size); +int rpc_emu_wpr_protect_read(uint32_t vf_id, uint64_t base, uint64_t size); +int rpc_emu_wpr_protect(uint32_t vf_id, uint64_t base, uint64_t size, uint32_t flags); +int rpc_emu_wpr_unprotect(uint32_t vf_id, uint64_t base); +int rpc_emu_wpr_set_timeout(uint32_t vf_id, uint64_t timeout_ns); +int rpc_emu_wpr_check_access(uint32_t vf_id, uint64_t addr, uint32_t access_type); + +/* Scheduling Emulation */ +int rpc_emu_schedule(uint32_t vf_id, uint64_t work_handle, uint64_t callback, uint64_t arg, uint32_t priority, uint32_t flags); +int rpc_emu_yield(uint32_t vf_id); + +/* Notification Emulation */ +typedef void (*rpc_emu_notify_cb_t)(uint32_t vf_id, uint32_t type, void *data, size_t size, void *ctx); +int rpc_emu_notify_register(uint32_t vf_id, uint32_t type, rpc_emu_notify_cb_t cb, void *ctx); +int rpc_emu_notify_unregister(uint32_t vf_id, uint32_t type); +int rpc_emu_notify_send(uint32_t vf_id, uint32_t type, void *data, size_t size); + +/* Init/Fini */ +int rpc_emu_init(void); +void rpc_emu_fini(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _RPC_EMULATOR_H_ */ diff --git a/userspace/sdks/nv525/nvalloc/common/inc/dev_ctrl_defines.h b/userspace/sdks/nv525/nvalloc/common/inc/dev_ctrl_defines.h new file mode 100644 index 0000000..1644e3d --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/dev_ctrl_defines.h @@ -0,0 +1,86 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @brief Defines for simplifying SW accesses to the dev_ctrl interrupt tree. + * These are generic defines ued in addition to architecure-specific + * defines in dev_vm_addendum.h + * + */ + +// +// Notes on the terms used below: +// Subtree: The HW tree is a 64-way tree that consists of 2 TOP level interrupt +// registers, 32 bits each. Each of these 64 is referred to as a subtree. +// Leaf: Each of these 64 subtrees are associated with a pair of LEAF registers +// giving us a total of 128 LEAF registers. +// GPU vector: The 128 LEAF registers give us a total of (128*32) GPU vectors +// giving us a total of 4096 GPU vectors +// + +// +// Given a subtree index, the below macros give us the index of the TOP level +// register and the bit within the TOP level register to program for that +// subtree. +// +#define NV_CTRL_INTR_SUBTREE_TO_TOP_IDX(i) ((i) / 32) +#define NV_CTRL_INTR_SUBTREE_TO_TOP_BIT(i) ((i) % 32) + +// +// Given a subtree index, the below macros give us the two LEAF register indices +// that correspond to that subtree. +// +#define NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(i) ((i)*2) +#define NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(i) (((i)*2) + 1) + +// +// Given a LEAF register index, the below macros give us the range of GPU +// interrupt vectors that correspond to those leafs. +// +#define NV_CTRL_INTR_LEAF_IDX_TO_GPU_VECTOR_START(i) ((i)*32) +#define NV_CTRL_INTR_LEAF_IDX_TO_GPU_VECTOR_END(i) (((i)*32) + 31) + +// +// Given a GPU interrupt vector, the below macros give us the index of the +// LEAF register and the bit within the LEAF register to program for that +// GPU interrupt vector. +// +#define NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(i) ((i) / 32) +#define NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(i) ((i) % 32) + +// +// Given a GPU interrupt vector, the below macro gives us the subtree in which +// it belongs. +// +#define NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(i) ((NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(i)) / 2) + +// +// The max number of leaf registers we expect +// This is enforced to be greater than or equal to +// (NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(NV_CPU_INTR_STALL_SUBTREE_LAST) + 1) +// for the largest NV_CPU_INTR_STALL_SUBTREE_LAST +// +#define NV_MAX_INTR_LEAVES 12 + +// In SW, this specifies an invalid interrupt vector +#define NV_INTR_VECTOR_INVALID (NV_U32_MAX) diff --git a/userspace/sdks/nv525/nvalloc/common/inc/flcnifcmn.h b/userspace/sdks/nv525/nvalloc/common/inc/flcnifcmn.h new file mode 100644 index 0000000..854c84e --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/flcnifcmn.h @@ -0,0 +1,149 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * flcn Command/Message Interfaces - Common + */ + +#ifndef FLCNIFCMN_H +#define FLCNIFCMN_H + +#include "nvtypes.h" +#include "flcnretval.h" + +#ifndef NV_SIZEOF32 +#define NV_SIZEOF32(v) (sizeof(v)) +#endif + +#ifndef NV_ARRAY_ELEMENTS +#define NV_ARRAY_ELEMENTS(x) ((sizeof(x)/sizeof((x)[0]))) +#endif + +/*! + * @ref NvU64_ALIGN32 , NvU64_ALIGN32_PACK, NvU64_ALIGN32_UNPACK + * TODO: Use NV types directly + */ +typedef NvU64_ALIGN32 RM_FLCN_U64; +typedef NvU64_ALIGN32 *PRM_FLCN_U64; + +#define RM_FLCN_U64_IS_ZERO NvU64_ALIGN32_IS_ZERO +#define RM_FLCN_U64_PACK NvU64_ALIGN32_PACK +#define RM_FLCN_U64_UNPACK NvU64_ALIGN32_UNPACK + +/*! + * @brief Header preceding each CMD/MSG exchanged through falcon's queues. + * + * @note Data package sent to falcon are referred as CMDs (commands). + * Data package sent by falcon are referred as MSGs (messages). + */ +typedef struct +{ + /*! + * Unit ID identifies falcon's task/unit receiving/issuing this message. + */ + NvU8 unitId; + /*! + * Total CMD/MSG size (including header). + */ + NvU8 size; + /*! + * Flags identifying state of CMD/MSG. + */ + NvU8 ctrlFlags; + /*! + * Sequence # ID to track each request sent to falcon (where applicable). + */ + NvU8 seqNumId; +} RM_FLCN_QUEUE_HDR, +*PRM_FLCN_QUEUE_HDR; + +/*! + * Convenience macro for determining the size of the falcon's queue header: + */ +#define RM_FLCN_QUEUE_HDR_SIZE sizeof(RM_FLCN_QUEUE_HDR) + +/*! + * Generic Falcon rewind unit ID. + */ +#define RM_FLCN_UNIT_ID_REWIND (0x00U) + +/*! + * Generic CMD structure to hold the header. + */ +typedef struct +{ + RM_FLCN_QUEUE_HDR hdr; + NvU32 cmd; +} RM_FLCN_CMD_GEN; + +/*! + * Generic MSG structure to hold the header. + */ +typedef struct +{ + RM_FLCN_QUEUE_HDR hdr; + NvU32 msg; +} RM_FLCN_MSG_GEN; + +/*! + * Convenience macros for determining the size of body for a command or message: + */ +#define RM_FLCN_CMD_BODY_SIZE(u,t) sizeof(RM_FLCN_##u##_CMD_##t) +#define RM_FLCN_MSG_BODY_SIZE(u,t) sizeof(RM_FLCN_##u##_MSG_##t) + +/*! + * Convenience macros for determining the size of a command or message: + */ +#define RM_FLCN_CMD_SIZE(u,t) \ + (RM_FLCN_QUEUE_HDR_SIZE + RM_FLCN_CMD_BODY_SIZE(u,t)) + +#define RM_FLCN_MSG_SIZE(u,t) \ + (RM_FLCN_QUEUE_HDR_SIZE + RM_FLCN_MSG_BODY_SIZE(u,t)) + +/*! + * Convenience macros for determining the type of a command or message + * (intended to be used symmetrically with the CMD and MSG _SIZE macros): + */ +#define RM_FLCN_CMD_TYPE(u,t) RM_FLCN_##u##_CMD_ID_##t +#define RM_FLCN_MSG_TYPE(u,t) RM_FLCN_##u##_MSG_ID_##t + +/*! + * @brief Falcons' queue header flags (@ref RM_FLCN_QUEUE_HDR::ctrlFlags). + * + * RM_FLCN_QUEUE_FLAGS_STATUS + * Set by command's sender to request back message confirming the completion of + * command's execution. In RM->FLCN communication response is required to free + * command related data tracked within RM (***_SEQ_INFO). + * + * RM_FLCN_QUEUE_HDR_FLAGS_EVENT + * Set by the falcon to distinguish messages sent to RM from command responses. + * + * RM_FLCN_QUEUE_HDR_FLAGS_UNIT_ACK + * Used internally within the falcon to track completed commands when updating + * get (tail) command queue pointers. + */ +#define RM_FLCN_QUEUE_HDR_FLAGS_STATUS NVBIT(0) +#define RM_FLCN_QUEUE_HDR_FLAGS_EVENT NVBIT(2) +#define RM_FLCN_QUEUE_HDR_FLAGS_UNIT_ACK NVBIT(5) + +#endif // FLCNIFCMN_H diff --git a/userspace/sdks/nv525/nvalloc/common/inc/flcnretval.h b/userspace/sdks/nv525/nvalloc/common/inc/flcnretval.h new file mode 100644 index 0000000..c43cbb2 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/flcnretval.h @@ -0,0 +1,292 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file flcnretval.h + * @brief Defines various status codes that are convenient to relay status + * information in functions. + */ + +#ifndef FLCNRETVAL_H +#define FLCNRETVAL_H + +#include "nvtypes.h" +/*! + * Defines a generic type that may be used to convey status information. This + * is very similar to the RM_STATUS type but smaller in width to save DMEM and + * stack space. + */ +typedef NvU8 FLCN_STATUS; + +#define FLCN_OK (0x00U) +#define FLCN_ERR_BINARY_NOT_STARTED (0xFEU) +#define FLCN_ERROR (0xFFU) + +#define FLCN_ERR_NOT_SUPPORTED (0x01U) +#define FLCN_ERR_INVALID_ARGUMENT (0x02U) +#define FLCN_ERR_ILLEGAL_OPERATION (0x03U) +#define FLCN_ERR_TIMEOUT (0x04U) +#define FLCN_ERR_NO_FREE_MEM (0x05U) +#define FLCN_ERR_HDCP_INVALID_SRM (0x06U) +#define FLCN_ERR_HDCP_RECV_REVOKED (0x07U) +#define FLCN_ERR_RPC_INVALID_INPUT (0x08U) +#define FLCN_ERR_DMA_SUSPENDED (0x09U) +#define FLCN_ERR_MUTEX_ACQUIRED (0x10U) +#define FLCN_ERR_MUTEX_ID_NOT_AVAILABLE (0x11U) +#define FLCN_ERR_OBJECT_NOT_FOUND (0x12U) +#define FLCN_ERR_MSGBOX_TIMEOUT (0x13U) +#define FLCN_ERR_INVALID_INDEX (0x14U) +#define FLCN_ERR_INVALID_FUNCTION (0x15U) +#define FLCN_ERR_INSUFFICIENT_PMB_PLM_PROTECTION (0x16U) +#define FLCN_ERR_DMA_NACK (0x17U) +#define FLCN_ERR_CHIP_NOT_SUPPORTED_FOR_PR (0x18U) +#define FLCN_ERR_BAR0_PRIV_READ_ERROR (0x19U) +#define FLCN_ERR_BAR0_PRIV_WRITE_ERROR (0x1AU) +#define FLCN_ERR_HDCP22_ABORT_AUTHENTICATION (0x1BU) +#define FLCN_ERR_DPU_IS_BUSY (0x1CU) +#define FLCN_ERR_DPU_TIMEOUT_FOR_HDCP_TYPE1_LOCK_REQUEST (0x1DU) +#define FLCN_ERR_HDCP_TYPE1_LOCK_FAILED (0x1EU) +#define FLCN_ERR_HDCP_TYPE1_LOCK_UNKNOWN (0x1FU) +#define FLCN_ERR_WAIT_FOR_BAR0_IDLE_FAILED (0x20U) +#define FLCN_ERR_CSB_PRIV_READ_ERROR (0x21U) +#define FLCN_ERR_CSB_PRIV_WRITE_ERROR (0x22U) +#define FLCN_ERR_DMA_UNEXPECTED_DMAIDX (0x23U) +#define FLCN_ERR_PRIV_SEC_VIOLATION (0x24U) +#define FLCN_ERR_INVALID_VERSION (0x25U) +#define FLCN_ERR_PR_SHARED_STRUCT_INIT_FAILED (0x26U) +#define FLCN_ERR_GPU_IN_DEBUG_MODE (0x27U) +#define FLCN_ERR_HPD_UNPLUG (0x28U) +#define FLCN_ERR_HDCP22_DELAY_ABORT_AUTHENTICATION (0x29U) +#define FLCN_ERR_SECUREBUS_REGISTER_READ_ERROR (0x2AU) +#define FLCN_ERR_SECUREBUS_REGISTER_WRITE_ERROR (0x2BU) +#define FLCN_ERR_HDCP22_FLUSH_TYPE_LOCK_ACTIVE (0x2CU) +#define FLCN_ERR_HDCP22_FLUSH_TYPE_IN_PROGRESS (0x2DU) +#define FLCN_ERR_FEATURE_NOT_ENABLED (0x2EU) +#define FLCN_ERR_OUT_OF_RANGE (0x2FU) + +// I2C Errors +#define FLCN_ERR_I2C_BUSY (0x30U) +#define FLCN_ERR_I2C_NACK_ADDRESS (0x31U) +#define FLCN_ERR_I2C_NACK_BYTE (0x32U) +#define FLCN_ERR_I2C_SIZE (0x33U) +#define FLCN_ERR_I2C_BUS_INVALID (0x34U) + +#define FLCN_ERR_INVALID_STATE (0x35U) +#define FLCN_ERR_RECURSION_LIMIT_EXCEEDED (0x36U) +#define FLCN_ERR_INVALID_CAST (0x37U) + +// AUX Errors +#define FLCN_ERR_AUX_ERROR (0x3AU) +#define FLCN_ERR_AUX_SEMA_ACQUIRED (0x3BU) +#define FLCN_ERR_AUX_SEMA_INVALID_RELEASE (0x3CU) + +#define FLCN_ERR_MORE_PROCESSING_REQUIRED (0x3EU) +#define FLCN_ERR_DMA_ALIGN (0x3FU) + +// Power-Device Errors +#define FLCN_ERR_PWR_DEVICE_TAMPERED (0x40U) + +#define FLCN_ERR_ITERATION_END (0x41U) + +// Perf change sequence Errors +#define FLCN_ERR_LOCK_NOT_AVAILABLE (0x42U) + +#define FLCN_ERR_STATE_RESET_NEEDED (0x43U) +#define FLCN_ERR_DMA_GENERIC (0x44U) +#define FLCN_ERR_LS_CHK_UCODE_REVOKED (0x45U) +#define FLCN_ERR_ACC_SEQ_MISMATCH (0x46U) +#define FLCN_ERR_SSP_STACK_CHECK_FAILED (0x47U) +#define FLCN_ERR_SE_TRNG_FAILED (0x48U) +#define FLCN_ERR_PROD_MODE_NOT_YET_SUPPORTED (0x49U) + +// SHA HW errors +#define FLCN_ERR_SHA_HW_CHECK_INT_STATUS (0x4AU) +#define FLCN_ERR_SHA_HW_SOFTRESET_REQUIRED (0x4BU) +#define FLCN_ERR_SHA_HW_SOFTRESET_FAILED (0x4CU) +#define FLCN_ERR_SHA_HW_BUSY (0x4DU) + +// +// Add new generic error codes here, do not changes values of exiting error codes, +// because that will affect other binaries and their signatures +// +#define FLCN_ERR_CTXSW_ERROR (0x4EU) +#define FLCN_ERR_SE_SNPKA_HW_CRYPTO_OPERATION_FAILED (0x4FU) + +// VPR SEC2 task errors +#define FLCN_ERR_VPR_APP_INVALID_REQUEST_END_ADDR (0x51U) +#define FLCN_ERR_VPR_APP_INVALID_REQUEST_START_ADDR (0x52U) +#define FLCN_ERR_VPR_APP_SCRUB_VERIF_FAILED (0x53U) +#define FLCN_ERR_VPR_APP_MEMLOCK_ALREADY_SET (0x54U) +#define FLCN_ERR_VPR_APP_INVALID_INDEX (0x55U) +#define FLCN_ERR_VPR_APP_UNEXPECTED_VPR_HANDOFF_FROM_SCRUBBER (0x56U) +#define FLCN_ERR_VPR_APP_CBC_RANGE_CLASH (0x57U) +#define FLCN_ERR_VPR_APP_NOT_SUPPORTED_BY_HW (0x58U) +#define FLCN_ERR_VPR_APP_NOT_SUPPORTED_BY_SW (0x59U) +#define FLCN_ERR_VPR_APP_DISPLAY_VERSION_NOT_SUPPORTED (0x5AU) +#define FLCN_ERR_VPR_APP_VPR_WPR_WRITE_FAILED (0x5BU) +#define FLCN_ERR_VPR_APP_NOTHING_TO_DO (0x5CU) +#define FLCN_ERR_VPR_APP_DISPLAY_NOT_PRESENT (0x5DU) +#define FLCN_ERR_VPR_APP_PREVIOUS_CMD_FAILED_AS_MAX_VPR_IS_0 (0x5EU) +#define FLCN_ERR_VPR_APP_PLM_PROTECTION_NOT_RAISED (0x5FU) +#define FLCN_ERR_VPR_APP_PLM_PROTECTION_ALREADY_RAISED (0x60U) +#define FLCN_ERR_VPR_APP_DISP_FALCON_IS_NOT_IN_LS_MODE (0x61U) +#define FLCN_ERR_VPR_APP_VPR_IS_ALREADY_ENABLED (0x62U) +#define FLCN_ERR_VPR_APP_UNEXPECTEDLY_RUNNING_ON_RISCV (0x63U) + +// Clocks Errors +#define FLCN_ERR_CYCLE_DETECTED (0x70U) +#define FLCN_ERR_INVALID_PATH (0x71U) +#define FLCN_ERR_MISMATCHED_TARGET (0x72U) +#define FLCN_ERR_FREQ_NOT_SUPPORTED (0x73U) +#define FLCN_ERR_INVALID_SOURCE (0x74U) +#define FLCN_ERR_NOT_INITIALIZED (0x75U) + +// HDCP2.2 Errors +#define FLCN_ERR_HDCP22_GETDKEY_FAILED (0x80U) +#define FLCN_ERR_HDCP22_H_PRIME (0x81U) +#define FLCN_ERR_HDCP22_CERT_RX (0x82U) +#define FLCN_ERR_HDCP22_PAIRING (0x83U) +#define FLCN_ERR_HDCP22_L_PRIME (0x84U) +#define FLCN_ERR_HDCP22_V_PRIME (0x85U) +#define FLCN_ERR_HDCP22_INVALID_RXIDLIST (0x86U) +#define FLCN_ERR_HDCP22_M_PRIME (0x87U) +#define FLCN_ERR_HDCP22_SEQ_ROLLOVER (0x88U) +#define FLCN_ERR_HDCP22_RSA_HW (0x89U) +#define FLCN_ERR_HDCP22_ECF_TIMESLOT_MISMATCH (0x90U) + +// LibCCC Errors +#define FLCN_ERR_INIT_CRYPTO_DEVICE_FAILED (0x91U) +#define FLCN_ERR_NVPKA_SELECT_ENGINE_FAILED (0x92U) +#define FLCN_ERR_NVPKA_ACQUIRE_MUTEX_FAILED (0x93U) +#define FLCN_ERR_NVPKA_MODULAR_EXP_LOCK_FAILED (0x94U) +#define FLCN_ERR_NVRNG_INIT_CRYPTO_DEVICE_FAILED (0x95U) +#define FLCN_ERR_NVRNG_SELECT_ENGINE_FAILED (0x96U) +#define FLCN_ERR_NVRNG_GENERATE_FAILED (0x97U) + +// Heavy Secure Errors +#define FLCN_ERR_HS_CHK_INVALID_INPUT (0xA0U) +#define FLCN_ERR_HS_CHK_CHIP_NOT_SUPPORTED (0xA1U) +#define FLCN_ERR_HS_CHK_UCODE_REVOKED (0xA2U) +#define FLCN_ERR_HS_CHK_NOT_IN_LSMODE (0xA3U) +#define FLCN_ERR_HS_CHK_INVALID_LS_PRIV_LEVEL (0xA4U) +#define FLCN_ERR_HS_CHK_INVALID_REGIONCFG (0xA5U) +#define FLCN_ERR_HS_CHK_PRIV_SEC_DISABLED_ON_PROD (0xA6U) +#define FLCN_ERR_HS_CHK_SW_FUSING_ALLOWED_ON_PROD (0xA7U) +#define FLCN_ERR_HS_CHK_INTERNAL_SKU_ON_PROD (0xA8U) +#define FLCN_ERR_HS_CHK_DEVID_OVERRIDE_ENABLED_ON_PROD (0xA9U) +#define FLCN_ERR_HS_CHK_INCONSISTENT_PROD_MODES (0xAAU) +#define FLCN_ERR_HS_CHK_HUB_ENCRPTION_DISABLED (0xABU) +#define FLCN_ERR_HS_PR_ILLEGAL_LASSAHS_STATE_AT_HS_ENTRY (0xACU) +#define FLCN_ERR_HS_PR_ILLEGAL_LASSAHS_STATE_AT_MPK_DECRYPT (0xADU) +#define FLCN_ERR_HS_PR_ILLEGAL_LASSAHS_STATE_AT_HS_EXIT (0xAEU) +#define FLCN_ERR_HS_PROD_MODE_NOT_YET_SUPPORTED (0xAFU) +#define FLCN_ERR_HS_DEV_VERSION_ON_PROD (0xB0U) +#define FLCN_ERR_HS_PR_LASSAHS_LS_SIG_GRP_MISMATCH (0xB1U) +#define FLCN_ERR_HS_PR_LASSAHS_LS_SIG_GRP_OVERLAYS_CNT (0xB2U) +#define FLCN_ERR_HS_PR_LASSAHS_LS_SIG_GRP_INVALID_VA (0xB3U) +#define FLCN_ERR_HS_MUTEX_ACQUIRE_FAILED (0xB4U) +#define FLCN_ERR_HS_MUTEX_RELEASE_FAILED (0xB5U) +#define FLCN_ERR_HS_PR_MPK_DEC_NEEDS_NEWER_ACR_UDE_SCRUBBER (0xB6U) +#define FLCN_ERR_HS_CHK_ENGID_MISMATCH (0xB7U) +#define FLCN_ERR_HS_OPT_INTERNAL_SKU_CHECK_FAILED (0xB8U) +#define FLCN_ERR_HS_CHK_BOARD_MISMATCH (0xB9U) +#define FLCN_ERR_HS_CHK_DISP_ENG_DISABLED (0xBAU) +#define FLCN_ERR_HS_GEN_RANDOM (0xBBU) +#define FLCN_ERR_HS_CHK_IMPROPERLY_FUSED_BOARD (0xBCU) +#define FLCN_ERR_HS_CHK_HDCP_DISABLED (0xBDU) +#define FLCN_ERR_HS_CHK_HDCP_BLACKLISTED_SKU (0XBEU) +#define FLCN_ERR_HS_SECURE_ACTION_ARG_CHECK_FAILED (0xBFU) +#define FLCN_ERR_HS_CHK_RETURN_PC_AT_HS_ENTRY_IS_OF_HS (0xC0U) +#define FLCN_ERR_HS_CHK_HS_LIB_ENTRY_CALLED_BY_NON_HS (0xC1U) +#define FLCN_ERR_HS_DECODE_TRAP_ALREADY_IN_USE (0xC2U) +#define FLCN_ERR_HS_REGISTER_READ_WRITE_ERROR (0xC3U) +#define FLCN_ERR_HS_CHK_CPUCTL_ALIAS_FALSE (0xC4U) +#define FLCN_ERR_HS_UPDATE_RESET_PLM_ERROR (0xC5U) +#define FLCN_ERR_HS_RNG_CONFIG_ERROR (0xC6U) +#define FLCN_ERR_HS_CHK_NOT_IN_HSMODE (0xC7U) +#define FLCN_ERR_HS_CHK_GFW_CHAIN_OF_TRUST_BROKEN (0xC8U) +#define FLCN_ERR_HS_HDCP22_WRONG_SEQUENCE (0xC9U) +#define FLCN_ERR_HS_HDCP22_INTEGRITY_ERROR (0xCAU) +#define FLCN_ERR_HS_HDCP22_WRONG_TYPE (0xCBU) +#define FLCN_ERR_HS_APM_NOT_ENABLED (0xCCU) +#define FLCN_ERR_HS_APM_SMC_ENABLED (0xCDU) +#define FLCN_ERR_HS_APM_FECS_NOT_HALTED (0xCEU) +#define FLCN_ERR_HS_APM_SCRATCH_PLM_INVALID (0xCFU) +#define FLCN_ERR_HS_APM_SCRATCH_INIT_INVALID (0xD0U) +#define FLCN_ERR_HS_INVALID_KEY (0xD1U) +#define FLCN_ERR_HS_SWKG_INVALID_SIGNATURE (0xD2U) + + +// +// BAR0/CSB Priv Read/Write Error Handling Defines +// These need to be defined by HW - NV Bug 200198584 +// +#define FLCN_BAR0_PRIV_PRI_ERROR_MASK 0xFFF00000U +#define FLCN_BAR0_PRIV_PRI_ERROR_CODE 0xBAD00000U +#define FLCN_BAR0_PRIV_PRI_RETURN_VAL 0x00BADBADU + +#define FLCN_CSB_PRIV_PRI_ERROR_MASK 0xFFFF0000U +#define FLCN_CSB_PRIV_PRI_ERROR_CODE 0xBADF0000U + +// +// Macro to check FALCON return status +// +#define CHECK_FLCN_STATUS(expr) do { \ + flcnStatus = (expr); \ + if (flcnStatus != FLCN_OK) \ + { \ + goto ErrorExit; \ + } \ + } while (NV_FALSE) + +// Warnings. +#define FLCN_WARN_NOTHING_TO_DO (0xD0U) +#define FLCN_WARN_NOT_QUERIED (0xD1U) + +// Queue handling Errors +#define FLCN_ERR_QUEUE_MGMT_INVALID_UNIT_ID (0xE0U) +#define FLCN_ERR_QUEUE_MGMT_HEAP_MIRROR_ERR (0xE1U) +#define FLCN_ERR_QUEUE_TASK_INVALID_EVENT_TYPE (0xE2U) +#define FLCN_ERR_QUEUE_TASK_INVALID_UNIT_ID (0xE3U) +#define FLCN_ERR_QUEUE_TASK_INVALID_CMD_TYPE (0xE4U) + +// Posted write errors +#define FLCN_ERR_POSTED_WRITE_FAILURE (0xF0U) +#define FLCN_ERR_POSTED_WRITE_INTERRUPTS_ENABLED (0xF1U) +#define FLCN_ERR_POSTED_WRITE_PRI_CLUSTER_COUNT_MISMATCH (0xF2U) +#define FLCN_ERR_POSTED_WRITE_INCORRECT_PARAMS (0xF3U) + +// Lane Margining errors +#define FLCN_ERR_LM_INVALID_RECEIVER_NUMBER (0xF5U) + +// APM errors +#define FLCN_ERR_APM_NOT_FUSED_FOR_EK (0xF6U) +#define FLCN_ERR_APM_BROM_SIGN_FAIL (0xF7U) +// Booter Reload on SEC2-RTOS errors +#define FLCN_ERR_AUTH_GSP_RM_HANDOFF_FAILED (0xF8U) +#define FLCN_ERR_INVALID_WPRMETA_MAGIC_OR_REVISION (0xF9U) + +// Arithmetic errors +#define FLCN_ERR_ARITHMETIC_OVERFLOW (0xFAU) + +#endif // FLCNRETVAL_H diff --git a/userspace/sdks/nv525/nvalloc/common/inc/fsp/fsp_emem_channels.h b/userspace/sdks/nv525/nvalloc/common/inc/fsp/fsp_emem_channels.h new file mode 100644 index 0000000..c4b9949 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/fsp/fsp_emem_channels.h @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _FSP_EMEM_CHANNELS_H_ +#define _FSP_EMEM_CHANNELS_H_ + +// +// NVDM (NVIDIA Data Model) overlayed on MCTP (Management Component Transport +// Protocol) and sent over EMEM is the communication mechanism used between FSP +// management partition and CPU-RM/other uprocs. +// + +// RM uses channel 0 for FSP EMEM. +#define FSP_EMEM_CHANNEL_RM 0x0 + +// PMU/SOE use channel 4 for FSP EMEM. +#define FSP_EMEM_CHANNEL_PMU_SOE 0x4 +#define FSP_EMEM_CHANNEL_MAX 0x8 + +// EMEM channel 0 (RM) is allocated 1K bytes. +#define FSP_EMEM_CHANNEL_RM_SIZE 1024 + +// EMEM channel 4 (PMU/SOE) is allocated 1K bytes. +#define FSP_EMEM_CHANNEL_PMU_SOE_SIZE 1024 +#define FSP_EMEM_CHANNEL_PMU_SOE_OFFSET 4096 + +#endif // _FSP_EMEM_CHANNELS_H_ diff --git a/userspace/sdks/nv525/nvalloc/common/inc/fsp/fsp_mctp_format.h b/userspace/sdks/nv525/nvalloc/common/inc/fsp/fsp_mctp_format.h new file mode 100644 index 0000000..c087dc2 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/fsp/fsp_mctp_format.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _FSP_MCTP_FORMAT_H_ +#define _FSP_MCTP_FORMAT_H_ + +// +// NVDM (NVIDIA Data Model) overlayed on MCTP (Management Component Transport +// Protocol) and sent over EMEM is the communication mechanism used between FSP +// management partition and CPU-RM/other uprocs. +// + + +#define MCTP_HEADER_VERSION 3:0 +#define MCTP_HEADER_RSVD 7:4 + +#define MCTP_HEADER_DEID 15:8 +#define MCTP_HEADER_SEID 23:16 + +#define MCTP_HEADER_TAG 26:24 +#define MCTP_HEADER_TO 27:27 +#define MCTP_HEADER_SEQ 29:28 +#define MCTP_HEADER_EOM 30:30 +#define MCTP_HEADER_SOM 31:31 + +#define MCTP_MSG_HEADER_TYPE 6:0 +#define MCTP_MSG_HEADER_IC 7:7 + +#define MCTP_MSG_HEADER_VENDOR_ID 23:8 +#define MCTP_MSG_HEADER_NVDM_TYPE 31:24 + +#define MCTP_MSG_HEADER_TYPE_VENDOR_PCI 0x7e +#define MCTP_MSG_HEADER_VENDOR_ID_NV 0x10de + +#endif // _FSP_MCTP_FORMAT_H_ diff --git a/userspace/sdks/nv525/nvalloc/common/inc/fsp/fsp_nvdm_format.h b/userspace/sdks/nv525/nvalloc/common/inc/fsp/fsp_nvdm_format.h new file mode 100644 index 0000000..dc389f1 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/fsp/fsp_nvdm_format.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _FSP_NVDM_FORMAT_H_ +#define _FSP_NVDM_FORMAT_H_ + +#include "fsp/fsp_mctp_format.h" +#include "fsp/fsp_emem_channels.h" + +// +// NVDM (NVIDIA Data Model) overlayed on MCTP (Management Component Transport +// Protocol) and sent over EMEM is the communication mechanism used between FSP +// management partition and CPU-RM/other uprocs. +// + +#define NVDM_TYPE_HULK 0x11 +#define NVDM_TYPE_FIRMWARE_UPDATE 0x12 +#define NVDM_TYPE_COT 0x14 +#define NVDM_TYPE_FSP_RESPONSE 0x15 +#define NVDM_TYPE_INFOROM 0x17 +#define NVDM_TYPE_SMBPBI 0x18 + +#endif // _FSP_NVDM_FORMAT_H_ diff --git a/userspace/sdks/nv525/nvalloc/common/inc/fsp/nvdm_payload_cmd_response.h b/userspace/sdks/nv525/nvalloc/common/inc/fsp/nvdm_payload_cmd_response.h new file mode 100644 index 0000000..fa117aa --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/fsp/nvdm_payload_cmd_response.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * @file nvdm_payload_cmd_response.h + * @brief Header file containing the definition for the + * NVDM_PAYLOAD_COMMAND_RESPONSE structure, which + * is required for SMBPBI-specific payloads and needs + * to be visible by bothe the PMU and the driver sides. + */ + +#ifndef _NVDM_PAYLOAD_CMD_RESPONSE_H +#define _NVDM_PAYLOAD_CMD_RESPONSE_H + +#pragma pack(1) +typedef struct +{ + NvU32 taskId; + NvU32 commandNvdmType; + NvU32 errorCode; +} NVDM_PAYLOAD_COMMAND_RESPONSE; +#pragma pack() + +#endif // _NVDM_PAYLOAD_CMD_RESPONSE_H diff --git a/userspace/sdks/nv525/nvalloc/common/inc/gsp/gsp_error.h b/userspace/sdks/nv525/nvalloc/common/inc/gsp/gsp_error.h new file mode 100644 index 0000000..2401c78 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/gsp/gsp_error.h @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef GSP_ERROR_H +#define GSP_ERROR_H + +// Definitions for GSP-RM to report errors to CPU-RM via mailbox +#define NV_GSP_ERROR_CODE 7:0 +#define NV_GSP_ERROR_REASON 15:8 +#define NV_GSP_ERROR_TASK 23:16 +#define NV_GSP_ERROR_SKIPPED 27:24 +#define NV_GSP_ERROR_TAG 31:28 +#define NV_GSP_ERROR_TAG_VAL 0xE + +#endif // GSP_ERROR_H diff --git a/userspace/sdks/nv525/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h b/userspace/sdks/nv525/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h new file mode 100644 index 0000000..c056000 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h @@ -0,0 +1,155 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#ifndef GSP_FW_WPR_META_H_ +#define GSP_FW_WPR_META_H_ + +/*! + * GSP firmware WPR metadata + * + * Initialized by CPU-RM and DMA'd to FB, at the end of what will be WPR2. + * Verified, and locked in WPR2 by Booter. + * + * Firmware scrubs the last 256mb of FB, no memory outside of this region + * may be used until the FW RM has scrubbed the remainder of memory. + * + * ---------------------------- <- fbSize (end of FB, 1M aligned) + * | VGA WORKSPACE | + * ---------------------------- <- vbiosReservedOffset (64K? aligned) + * | (potential align. gap) | + * ---------------------------- <- gspFwWprEnd (128K aligned) + * | FRTS data | (frtsSize is 0 on GA100) + * | ------------------------ | <- frtsOffset + * | BOOT BIN (e.g. SK + BL) | + * ---------------------------- <- bootBinOffset + * | GSP FW ELF | + * ---------------------------- <- gspFwOffset + * | GSP FW (WPR) HEAP | + * ---------------------------- <- gspFwHeapOffset + * | Booter-placed metadata | + * | (struct GspFwWprMeta) | + * ---------------------------- <- gspFwWprStart (128K aligned) + * | GSP FW (non-WPR) HEAP | + * ---------------------------- <- nonWprHeapOffset, gspFwRsvdStart + * (GSP_CARVEOUT_SIZE bytes from end of FB) + */ +typedef struct +{ + // Magic + // BL to use for verification (i.e. Booter locked it in WPR2) + NvU64 magic; // = 0xdc3aae21371a60b3; + + // Revision number of Booter-BL-Sequencer handoff interface + // Bumped up when we change this interface so it is not backward compatible. + // Bumped up when we revoke GSP-RM ucode + NvU64 revision; // = 1; + + // ---- Members regarding data in SYSMEM ---------------------------- + // Consumed by Booter for DMA + + NvU64 sysmemAddrOfRadix3Elf; + NvU64 sizeOfRadix3Elf; + + NvU64 sysmemAddrOfBootloader; + NvU64 sizeOfBootloader; + + // Offsets inside bootloader image needed by Booter + NvU64 bootloaderCodeOffset; + NvU64 bootloaderDataOffset; + NvU64 bootloaderManifestOffset; + + NvU64 sysmemAddrOfSignature; + NvU64 sizeOfSignature; + + // ---- Members describing FB layout -------------------------------- + NvU64 gspFwRsvdStart; + + NvU64 nonWprHeapOffset; + NvU64 nonWprHeapSize; + + NvU64 gspFwWprStart; + + // GSP-RM to use to setup heap. + NvU64 gspFwHeapOffset; + NvU64 gspFwHeapSize; + + // BL to use to find ELF for jump + NvU64 gspFwOffset; + // Size is sizeOfRadix3Elf above. + + NvU64 bootBinOffset; + // Size is sizeOfBootloader above. + + NvU64 frtsOffset; + NvU64 frtsSize; + + NvU64 gspFwWprEnd; + + // GSP-RM to use for fbRegionInfo? + NvU64 fbSize; + + // ---- Other members ----------------------------------------------- + + // GSP-RM to use for fbRegionInfo? + NvU64 vgaWorkspaceOffset; + NvU64 vgaWorkspaceSize; + + // Boot count. Used to determine whether to load the firmware image. + NvU64 bootCount; + + // TODO: the partitionRpc* fields below do not really belong in this + // structure. The values are patched in by the partition bootstrapper + // when GSP-RM is booted in a partition, and this structure was a + // convenient place for the bootstrapper to access them. These should + // be moved to a different comm. mechanism between the bootstrapper + // and the GSP-RM tasks. + + // Shared partition RPC memory (physical address) + NvU64 partitionRpcAddr; + + // Offsets relative to partitionRpcAddr + NvU16 partitionRpcRequestOffset; + NvU16 partitionRpcReplyOffset; + + // Code section and dataSection offset and size. + NvU32 elfCodeOffset; + NvU32 elfDataOffset; + NvU32 elfCodeSize; + NvU32 elfDataSize; + + // Pad structure to exactly 256 bytes. Can replace padding with additional + // fields without incrementing revision. Padding initialized to 0. + NvU32 padding[3]; + + // BL to use for verification (i.e. Booter says OK to boot) + NvU64 verified; // 0x0 -> unverified, 0xa0a0a0a0a0a0a0a0 -> verified + +} GspFwWprMeta; + +#define GSP_FW_WPR_META_VERIFIED 0xa0a0a0a0a0a0a0a0ULL +#define GSP_FW_WPR_META_REVISION 1 +#define GSP_FW_WPR_META_MAGIC 0xdc3aae21371a60b3ULL + +#endif // GSP_FW_WPR_META_H_ diff --git a/userspace/sdks/nv525/nvalloc/common/inc/gsp/gspifpub.h b/userspace/sdks/nv525/nvalloc/common/inc/gsp/gspifpub.h new file mode 100644 index 0000000..46733a6 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/gsp/gspifpub.h @@ -0,0 +1,96 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef GSPIFPUB_H +#define GSPIFPUB_H + +#include + +/*! + * @file gspifpub.h + * @brief GSP Command/Message Interfaces - Published + */ + +/*! + * Target physical memory apertures supported for DMA + */ +typedef enum { + GSP_DMA_TARGET_LOCAL_FB, + GSP_DMA_TARGET_COHERENT_SYSTEM, + GSP_DMA_TARGET_NONCOHERENT_SYSTEM, + GSP_DMA_TARGET_COUNT +} GSP_DMA_TARGET; + +/*! + * @brief GSP-CC Microcode Initialization Parameters + */ +typedef struct GSP_FMC_INIT_PARAMS +{ + // CC initialization "registry keys" + NvU32 regkeys; +} GSP_FMC_INIT_PARAMS; + +/*! + * @brief GSP-ACR BOOT_GSP_RM Command Parameters + * + * The wprCarveout fields have no effect in environments where the WPR can be allocated + * implicitly by ACR. + */ +typedef struct GSP_ACR_BOOT_GSP_RM_PARAMS +{ + // Physical memory aperture through which gspRmDescPa is accessed + GSP_DMA_TARGET target; + // Size in bytes of the GSP-RM descriptor structure + NvU32 gspRmDescSize; + // Physical offset in the target aperture of the GSP-RM descriptor structure + NvU64 gspRmDescOffset; + // Physical offset in FB to set the start of the WPR containing GSP-RM + NvU64 wprCarveoutOffset; + // Size in bytes of the WPR containing GSP-RM + NvU32 wprCarveoutSize; + // Whether to boot GSP-RM or GSP-Proxy through ACR + NvBool bIsGspRmBoot; +} GSP_ACR_BOOT_GSP_RM_PARAMS; + +/*! + * @brief GSP-RM Parameters + */ +typedef struct GSP_RM_PARAMS +{ + // Physical memory aperture through which bootArgsPa is accessed + GSP_DMA_TARGET target; + // Physical address that will be stuffed in NV_PGSP_FALCON_MAILBOX(0|1) + NvU64 bootArgsOffset; +} GSP_RM_PARAMS; + +/*! + * @brief GSP-CC Microcode Parameters for Boot Partitions + */ +typedef struct GSP_FMC_BOOT_PARAMS +{ + GSP_FMC_INIT_PARAMS initParams; + GSP_ACR_BOOT_GSP_RM_PARAMS bootGspRmParams; + GSP_RM_PARAMS gspRmParams; +} GSP_FMC_BOOT_PARAMS; + +#endif // GSPIFPUB_H diff --git a/userspace/sdks/nv525/nvalloc/common/inc/inforom/ifrdem.h b/userspace/sdks/nv525/nvalloc/common/inc/inforom/ifrdem.h new file mode 100644 index 0000000..26395e8 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/inforom/ifrdem.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _IFR_DEM_H_ +#define _IFR_DEM_H_ + +#define INFOROM_DEM_OBJECT_V1_00_PACKED_SIZE 4144 +#define INFOROM_DEM_OBJECT_V1_00_FIFO_SIZE 4096 + +struct INFOROM_DEM_OBJECT_V1_00 +{ + INFOROM_OBJECT_HEADER_V1_00 header; + inforom_U032 seqNumber; + inforom_U016 writeOffset; + inforom_U016 readOffset; + inforom_X008 fifoBuffer[INFOROM_DEM_OBJECT_V1_00_FIFO_SIZE]; + inforom_U032 reserved[8]; +}; + +#define INFOROM_DEM_OBJECT_V1_00_FMT INFOROM_OBJECT_HEADER_V1_00_FMT "d2w4096x8d" +typedef struct INFOROM_DEM_OBJECT_V1_00 INFOROM_DEM_OBJECT_V1_00; + +#endif // _IFR_DEM_H_ diff --git a/userspace/sdks/nv525/nvalloc/common/inc/inforom/ifrecc.h b/userspace/sdks/nv525/nvalloc/common/inc/inforom/ifrecc.h new file mode 100644 index 0000000..337537d --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/inforom/ifrecc.h @@ -0,0 +1,119 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _IFRECC_H_ +#define _IFRECC_H_ + +#include "nvtypes.h" +#include "inforom/types.h" + +// NVSwitch ECC v6 object definition +#define INFOROM_ECC_OBJECT_V6_S0_PACKED_SIZE 3808 + +//Used to determine if the entry is empty or not +#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_VALID 0:0 +#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_VALID_FALSE 0 +#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_VALID_TRUE 1 +#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_CORRUPT_TIMEDATA 1:1 +#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_CORRUPT_TIMEDATA_FALSE 0 +#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_CORRUPT_TIMEDATA_TRUE 1 +#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_ADDR_VALID 2:2 +#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_ADDR_VALID_FALSE 0 +#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_ADDR_VALID_TRUE 1 + +#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_LOCATION_LINK_ID 7:0 + +typedef struct INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER +{ + inforom_U008 header; + inforom_U032 errId; + inforom_U032 lastErrorTimestamp; + inforom_U032 averageEventDelta; + inforom_U016 location; + inforom_U016 sublocation; + inforom_U032 correctedCount; + inforom_U032 uncorrectedCount; + inforom_U032 address; + +} INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER; + +#define INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_MAX_COUNT 128 + +typedef struct INFOROM_ECC_OBJECT_V6_S0 +{ + INFOROM_OBJECT_HEADER_V1_00 header; + + NvU64_ALIGN32 uncorrectedTotal; + NvU64_ALIGN32 correctedTotal; + inforom_U032 lastClearedTimestamp; + + INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER errorEntries[INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_MAX_COUNT]; + + inforom_U008 padding[68]; +} INFOROM_ECC_OBJECT_V6_S0; + +#define INFOROM_ECC_OBJECT_V6_S0_HEADER_FMT INFOROM_OBJECT_HEADER_V1_00_FMT + +#define INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_FMT "b3d2w3d" + +#define INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_ARRAY_FMT \ + INFOROM_FMT_REP128(INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_FMT) + +#define INFOROM_ECC_OBJECT_V6_S0_PADDING_FMT "68b" + +#define INFOROM_ECC_OBJECT_V6_S0_FMT INFOROM_ECC_OBJECT_V6_S0_HEADER_FMT "qqd" \ + INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_ARRAY_FMT \ + INFOROM_ECC_OBJECT_V6_S0_PADDING_FMT + +// Error event structure for NVSwitch ECC errors +typedef struct +{ + NvU32 sxid; + NvU32 linkId; + NvBool bAddressValid; + NvU32 address; + + // The timestamp is filled in by the inforom ECC error logging API + NvU32 timestamp; + + NvBool bUncErr; + NvU32 errorCount; +} INFOROM_NVS_ECC_ERROR_EVENT; + +typedef union +{ + INFOROM_OBJECT_HEADER_V1_00 header; + INFOROM_ECC_OBJECT_V6_S0 v6s; +} INFOROM_ECC_OBJECT; + +typedef struct +{ + const char *pFmt; + NvU8 *pPackedObject; + INFOROM_ECC_OBJECT *pEcc; + + // Signals if there are pending updates to be flushed to InfoROM + NvBool bDirty; +} INFOROM_ECC_STATE, *PINFOROM_ECC_STATE; + +#endif // _IFRECC_H_ diff --git a/userspace/sdks/nv525/nvalloc/common/inc/inforom/ifrstruct.h b/userspace/sdks/nv525/nvalloc/common/inc/inforom/ifrstruct.h new file mode 100644 index 0000000..0ea7235 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/inforom/ifrstruct.h @@ -0,0 +1,83 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _IFRSTRUCT_H_ +#define _IFRSTRUCT_H_ + +#include "inforom/types.h" + +#include "inforom/ifrecc.h" +#include "inforom/ifrdem.h" + +#define INFOROM_OBD_OBJECT_V1_XX_PACKED_SIZE 128 + +struct INFOROM_OBD_OBJECT_V1_XX +{ + INFOROM_OBJECT_HEADER_V1_00 header; + inforom_U032 buildDate; + inforom_U008 marketingName[24]; + inforom_U008 serialNumber[16]; + inforom_U008 memoryManufacturer; + inforom_U008 memoryPartID[20]; + inforom_U008 memoryDateCode[6]; + inforom_U008 productPartNumber[20]; + inforom_U008 boardRevision[3]; + inforom_U008 boardType; + inforom_U008 board699PartNumber[20]; + inforom_U008 reserved[5]; +}; +#define INFOROM_OBD_OBJECT_V1_XX_FMT INFOROM_OBJECT_HEADER_V1_00_FMT "d116b" +typedef struct INFOROM_OBD_OBJECT_V1_XX INFOROM_OBD_OBJECT_V1_XX; + +// +// OEM 1.0 +// + +#define INFOROM_OEM_OBJECT_V1_00_PACKED_SIZE 512 +#define INFOROM_OEM_OBJECT_HEADER_VERSION 1 + +struct INFOROM_OEM_OBJECT_V1_00 +{ + INFOROM_OBJECT_HEADER_V1_00 header; + inforom_U008 oemInfo[504]; +}; +#define INFOROM_OEM_OBJECT_V1_00_FMT INFOROM_OBJECT_HEADER_V1_00_FMT "504b" +typedef struct INFOROM_OEM_OBJECT_V1_00 INFOROM_OEM_OBJECT_V1_00; + +#define INFOROM_IMG_OBJECT_V1_00_PACKED_SIZE 64 +#define INFOROM_IMG_OBJECT_V1_00_VERSION_LENGTH 16 + +struct INFOROM_IMG_OBJECT_V1_00 +{ + INFOROM_OBJECT_HEADER_V1_00 header; + inforom_U008 version[INFOROM_IMG_OBJECT_V1_00_VERSION_LENGTH]; + inforom_U016 pciDeviceId; + inforom_U016 pciVendorId; + inforom_U016 pciSubsystemId; + inforom_U016 pciSubsystemVendorId; + inforom_U008 reserved[32]; +}; +#define INFOROM_IMG_OBJECT_V1_00_FMT INFOROM_OBJECT_HEADER_V1_00_FMT "16b4w32b" +typedef struct INFOROM_IMG_OBJECT_V1_00 INFOROM_IMG_OBJECT_V1_00; + +#endif // _IFRSTRUCT_H_ diff --git a/userspace/sdks/nv525/nvalloc/common/inc/inforom/omsdef.h b/userspace/sdks/nv525/nvalloc/common/inc/inforom/omsdef.h new file mode 100644 index 0000000..921482e --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/inforom/omsdef.h @@ -0,0 +1,84 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _INFOROM_OMSDEF_H_ +#define _INFOROM_OMSDEF_H_ + +#include "inforom/types.h" + +#define INFOROM_OMS_OBJECT_V1_PACKED_SIZE 112 + +#define INFOROM_OMS_OBJECT_V1_SETTINGS_ENTRY_DATA_ENTRY_AVAILABLE 0:0 +#define INFOROM_OMS_OBJECT_V1_SETTINGS_ENTRY_DATA_ENTRY_AVAILABLE_NO 0 +#define INFOROM_OMS_OBJECT_V1_SETTINGS_ENTRY_DATA_ENTRY_AVAILABLE_YES 1 +#define INFOROM_OMS_OBJECT_V1_SETTINGS_ENTRY_DATA_FORCE_DEVICE_DISABLE 1:1 +#define INFOROM_OMS_OBJECT_V1_SETTINGS_ENTRY_DATA_FORCE_DEVICE_DISABLE_NO 0 +#define INFOROM_OMS_OBJECT_V1_SETTINGS_ENTRY_DATA_FORCE_DEVICE_DISABLE_YES 1 + +#define INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY_DATA_RESERVED 7:2 +#define INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY_DATA_ENTRY_CHECKSUM 15:8 + +typedef struct INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY +{ + inforom_U016 data; +} INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY; + +#define INFOROM_OMS_OBJECT_V1S_NUM_SETTINGS_ENTRIES 50 + +typedef struct INFOROM_OMS_OBJECT_V1S +{ + INFOROM_OBJECT_HEADER_V1_00 header; + inforom_U032 lifetimeRefreshCount; + INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY settings[ + INFOROM_OMS_OBJECT_V1S_NUM_SETTINGS_ENTRIES]; +} INFOROM_OMS_OBJECT_V1S; + +#define INFOROM_OMS_OBJECT_V1S_FMT INFOROM_OBJECT_HEADER_V1_00_FMT "d50w" + +typedef struct INFOROM_OMS_V1S_DATA +{ + INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY *pIter; + INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY prev; + INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY *pNext; +} INFOROM_OMS_V1S_DATA; + +typedef union +{ + INFOROM_OBJECT_HEADER_V1_00 header; + INFOROM_OMS_OBJECT_V1S v1s; +} INFOROM_OMS_OBJECT; + +typedef union +{ + INFOROM_OMS_V1S_DATA v1s; +} INFOROM_OMS_DATA; + +typedef struct +{ + const char *pFmt; + NvU8 *pPackedObject; + INFOROM_OMS_OBJECT *pOms; + INFOROM_OMS_DATA omsData; +} INFOROM_OMS_STATE; + +#endif /* _INFOROM_OMSDEF_H_ */ diff --git a/userspace/sdks/nv525/nvalloc/common/inc/inforom/types.h b/userspace/sdks/nv525/nvalloc/common/inc/inforom/types.h new file mode 100644 index 0000000..c062cb0 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/inforom/types.h @@ -0,0 +1,79 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _INFOROM_TYPES_H_ +#define _INFOROM_TYPES_H_ + +/*! + * @file types.h + * @brief Common types and definitions used by InfoROM objects + */ + +typedef NvS32 inforom_S008; +typedef NvU32 inforom_U004; +typedef NvU32 inforom_U008; +typedef NvU32 inforom_U016; +typedef NvU32 inforom_U024; +typedef NvU32 inforom_U032; +typedef NvU64 inforom_U064; +typedef NvU8 inforom_X008; + +#define INFOROM_FMT_S08 's' +#define INFOROM_FMT_U04 'n' +#define INFOROM_FMT_U08 'b' +#define INFOROM_FMT_U16 'w' +#define INFOROM_FMT_U24 't' +#define INFOROM_FMT_U32 'd' +#define INFOROM_FMT_U64 'q' +#define INFOROM_FMT_BINARY 'x' + +// Helper macros for generating repeating format sequences +#define INFOROM_FMT_REP02(fmt) fmt fmt +#define INFOROM_FMT_REP04(fmt) INFOROM_FMT_REP02(fmt) INFOROM_FMT_REP02(fmt) +#define INFOROM_FMT_REP08(fmt) INFOROM_FMT_REP04(fmt) INFOROM_FMT_REP04(fmt) +#define INFOROM_FMT_REP16(fmt) INFOROM_FMT_REP08(fmt) INFOROM_FMT_REP08(fmt) +#define INFOROM_FMT_REP32(fmt) INFOROM_FMT_REP16(fmt) INFOROM_FMT_REP16(fmt) +#define INFOROM_FMT_REP64(fmt) INFOROM_FMT_REP32(fmt) INFOROM_FMT_REP32(fmt) +#define INFOROM_FMT_REP128(fmt) INFOROM_FMT_REP64(fmt) INFOROM_FMT_REP64(fmt) +#define INFOROM_FMT_REP256(fmt) INFOROM_FMT_REP128(fmt) INFOROM_FMT_REP128(fmt) +#define INFOROM_FMT_REP512(fmt) INFOROM_FMT_REP256(fmt) INFOROM_FMT_REP256(fmt) + +#define INFOROM_OBJECT_SUBVERSION_SUPPORTS_NVSWITCH(sv) \ + ((((sv) & 0xF0) == 0) || (((sv) & 0xF0) == 0x20)) + +#define INFOROM_OBJECT_HEADER_V1_00_SIZE_OFFSET 0x05 +#define INFOROM_OBJECT_HEADER_V1_00_CHECKSUM_OFFSET 0x07 +#define INFOROM_OBJECT_HEADER_V1_00_PACKED_SIZE 8 + +typedef struct INFOROM_OBJECT_HEADER_V1_00 +{ + inforom_S008 type[3]; + inforom_U008 version; + inforom_U008 subversion; + inforom_U016 size; + inforom_U008 checksum; +} INFOROM_OBJECT_HEADER_V1_00; + +#define INFOROM_OBJECT_HEADER_V1_00_FMT "3s2bwb" + +#endif // _INFOROM_TYPES_H_ diff --git a/userspace/sdks/nv525/nvalloc/common/inc/nv-firmware-chip-family-select.h b/userspace/sdks/nv525/nvalloc/common/inc/nv-firmware-chip-family-select.h new file mode 100644 index 0000000..068cc44 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/nv-firmware-chip-family-select.h @@ -0,0 +1,62 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NV_FIRMWARE_CHIP_FAMILY_SELECT_H +#define NV_FIRMWARE_CHIP_FAMILY_SELECT_H + + + +#include +#include + +static inline nv_firmware_chip_family_t nv_firmware_get_chip_family( + NvU32 gpuArch, + NvU32 gpuImpl +) +{ + switch (gpuArch) + { + case GPU_ARCHITECTURE_TURING: + if (gpuImpl <= GPU_IMPLEMENTATION_TU106) + return NV_FIRMWARE_CHIP_FAMILY_TU10X; + else + return NV_FIRMWARE_CHIP_FAMILY_TU11X; + + case GPU_ARCHITECTURE_AMPERE: + if (gpuImpl == GPU_IMPLEMENTATION_GA100) + return NV_FIRMWARE_CHIP_FAMILY_GA100; + else + return NV_FIRMWARE_CHIP_FAMILY_GA10X; + + case GPU_ARCHITECTURE_ADA: + return NV_FIRMWARE_CHIP_FAMILY_AD10X; + + case GPU_ARCHITECTURE_HOPPER: + if (gpuImpl == GPU_IMPLEMENTATION_GH100) + return NV_FIRMWARE_CHIP_FAMILY_GH100; + } + + return NV_FIRMWARE_CHIP_FAMILY_NULL; +} + +#endif // NV_FIRMWARE_CHIP_FAMILY_SELECT_H diff --git a/userspace/sdks/nv525/nvalloc/common/inc/nv-firmware.h b/userspace/sdks/nv525/nvalloc/common/inc/nv-firmware.h new file mode 100644 index 0000000..3ddade5 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/nv-firmware.h @@ -0,0 +1,132 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NV_FIRMWARE_H +#define NV_FIRMWARE_H + + + +#include +#include + +typedef enum +{ + NV_FIRMWARE_TYPE_GSP, + NV_FIRMWARE_TYPE_GSP_LOG +} nv_firmware_type_t; + +typedef enum +{ + NV_FIRMWARE_CHIP_FAMILY_NULL = 0, + NV_FIRMWARE_CHIP_FAMILY_TU10X = 1, + NV_FIRMWARE_CHIP_FAMILY_TU11X = 2, + NV_FIRMWARE_CHIP_FAMILY_GA100 = 3, + NV_FIRMWARE_CHIP_FAMILY_GA10X = 4, + NV_FIRMWARE_CHIP_FAMILY_AD10X = 5, + NV_FIRMWARE_CHIP_FAMILY_GH100 = 6, + NV_FIRMWARE_CHIP_FAMILY_END, +} nv_firmware_chip_family_t; + +static inline const char *nv_firmware_chip_family_to_string( + nv_firmware_chip_family_t fw_chip_family +) +{ + switch (fw_chip_family) { + case NV_FIRMWARE_CHIP_FAMILY_GH100: return "gh100"; + case NV_FIRMWARE_CHIP_FAMILY_AD10X: return "ad10x"; + case NV_FIRMWARE_CHIP_FAMILY_GA10X: return "ga10x"; + case NV_FIRMWARE_CHIP_FAMILY_GA100: return "ga100"; + case NV_FIRMWARE_CHIP_FAMILY_TU11X: return "tu11x"; + case NV_FIRMWARE_CHIP_FAMILY_TU10X: return "tu10x"; + + case NV_FIRMWARE_CHIP_FAMILY_END: // fall through + case NV_FIRMWARE_CHIP_FAMILY_NULL: + return NULL; + } + return NULL; +} + +// The includer (presumably nv.c) may optionally define +// NV_FIRMWARE_PATH_FOR_FILENAME(filename) +// to return a string "path" given a gsp_*.bin or gsp_log_*.bin filename. +// +// The function nv_firmware_path will then be available. +#if defined(NV_FIRMWARE_PATH_FOR_FILENAME) +static inline const char *nv_firmware_path( + nv_firmware_type_t fw_type, + nv_firmware_chip_family_t fw_chip_family +) +{ + if (fw_type == NV_FIRMWARE_TYPE_GSP) + { + switch (fw_chip_family) + { + case NV_FIRMWARE_CHIP_FAMILY_AD10X: + return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_ad10x.bin"); + + case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GA100: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GA10X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_TU11X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_TU10X: + return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_tu10x.bin"); + + case NV_FIRMWARE_CHIP_FAMILY_END: // fall through + case NV_FIRMWARE_CHIP_FAMILY_NULL: + return ""; + } + } + else if (fw_type == NV_FIRMWARE_TYPE_GSP_LOG) + { + switch (fw_chip_family) + { + case NV_FIRMWARE_CHIP_FAMILY_AD10X: + return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_log_ad10x.bin"); + + case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GA100: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GA10X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_TU11X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_TU10X: + return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_log_tu10x.bin"); + + case NV_FIRMWARE_CHIP_FAMILY_END: // fall through + case NV_FIRMWARE_CHIP_FAMILY_NULL: + return ""; + } + } + + return ""; +} +#endif // defined(NV_FIRMWARE_PATH_FOR_FILENAME) + +// The includer (presumably nv.c) may optionally define +// NV_FIRMWARE_DECLARE_GSP_FILENAME(filename) +// which will then be invoked (at the top-level) for each +// gsp_*.bin (but not gsp_log_*.bin) +#if defined(NV_FIRMWARE_DECLARE_GSP_FILENAME) +NV_FIRMWARE_DECLARE_GSP_FILENAME("gsp_ad10x.bin") +NV_FIRMWARE_DECLARE_GSP_FILENAME("gsp_tu10x.bin") +#endif // defined(NV_FIRMWARE_DECLARE_GSP_FILENAME) + +#endif // NV_FIRMWARE_DECLARE_GSP_FILENAME diff --git a/userspace/sdks/nv525/nvalloc/common/inc/nvcst.h b/userspace/sdks/nv525/nvalloc/common/inc/nvcst.h new file mode 100644 index 0000000..9a86d5e --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/nvcst.h @@ -0,0 +1,353 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVCST_H +#define NVCST_H + +#include +#include +#include +#include + +#define CHIPSET_SETUP_FUNC(name) static NV_STATUS name(OBJCL *pCl); + +CHIPSET_SETUP_FUNC(Intel_25XX_setupFunc) +CHIPSET_SETUP_FUNC(Intel_27XX_setupFunc) +CHIPSET_SETUP_FUNC(Intel_2A40_setupFunc) +CHIPSET_SETUP_FUNC(Intel_0040_setupFunc) +CHIPSET_SETUP_FUNC(Intel_2E00_setupFunc) +CHIPSET_SETUP_FUNC(Intel_25E0_setupFunc) +CHIPSET_SETUP_FUNC(Intel_29XX_setupFunc) +CHIPSET_SETUP_FUNC(Intel_29X0_setupFunc) +CHIPSET_SETUP_FUNC(Intel_29E0_setupFunc) +CHIPSET_SETUP_FUNC(Intel_359E_setupFunc) +CHIPSET_SETUP_FUNC(Intel_4000_setupFunc) +CHIPSET_SETUP_FUNC(Intel_4003_setupFunc) +CHIPSET_SETUP_FUNC(Intel_3400_setupFunc) +CHIPSET_SETUP_FUNC(Intel_3B42_setupFunc) +CHIPSET_SETUP_FUNC(Intel_1C46_setupFunc) +CHIPSET_SETUP_FUNC(Intel_1C10_setupFunc) +CHIPSET_SETUP_FUNC(Intel_1C4B_setupFunc) +CHIPSET_SETUP_FUNC(Intel_1C49_setupFunc) +CHIPSET_SETUP_FUNC(Intel_1D40_setupFunc) +CHIPSET_SETUP_FUNC(Intel_8D47_setupFunc) +CHIPSET_SETUP_FUNC(Intel_8D44_setupFunc) +CHIPSET_SETUP_FUNC(Intel_1E10_setupFunc) +CHIPSET_SETUP_FUNC(Intel_8C4B_setupFunc) +CHIPSET_SETUP_FUNC(Intel_8CC4_setupFunc) +CHIPSET_SETUP_FUNC(Intel_A145_setupFunc) +CHIPSET_SETUP_FUNC(Intel_A2C5_setupFunc) +CHIPSET_SETUP_FUNC(Intel_A242_setupFunc) +CHIPSET_SETUP_FUNC(Intel_A2D2_setupFunc) +CHIPSET_SETUP_FUNC(Intel_A2C9_setupFunc) +CHIPSET_SETUP_FUNC(Intel_A301_setupFunc) +CHIPSET_SETUP_FUNC(Intel_0685_setupFunc) +CHIPSET_SETUP_FUNC(Intel_IceLake_setupFunc) +CHIPSET_SETUP_FUNC(Intel_4381_setupFunc) +CHIPSET_SETUP_FUNC(Intel_7A82_setupFunc) +CHIPSET_SETUP_FUNC(Intel_7A04_setupFunc) +CHIPSET_SETUP_FUNC(SiS_656_setupFunc) +CHIPSET_SETUP_FUNC(ATI_RS400_setupFunc) +CHIPSET_SETUP_FUNC(ATI_RS480_setupFunc) +CHIPSET_SETUP_FUNC(ATI_RD870_setupFunc) +CHIPSET_SETUP_FUNC(ATI_RD890_setupFunc) +CHIPSET_SETUP_FUNC(ATI_RX780_setupFunc) +CHIPSET_SETUP_FUNC(ATI_FX990_setupFunc) +CHIPSET_SETUP_FUNC(AMD_RS780_setupFunc) +CHIPSET_SETUP_FUNC(AMD_FX790_setupFunc) +CHIPSET_SETUP_FUNC(AMD_FX890_setupFunc) +CHIPSET_SETUP_FUNC(AMD_X370_setupFunc) +CHIPSET_SETUP_FUNC(VIA_VX900_setupFunc) +CHIPSET_SETUP_FUNC(APM_Storm_setupFunc) +CHIPSET_SETUP_FUNC(ARMV8_generic_setupFunc) +CHIPSET_SETUP_FUNC(Marvell_ThunderX2_setupFunc) +CHIPSET_SETUP_FUNC(QEMU_setupFunc) +CHIPSET_SETUP_FUNC(Ampere_eMag_setupFunc) +CHIPSET_SETUP_FUNC(Huawei_Kunpeng920_setupFunc) +CHIPSET_SETUP_FUNC(Mellanox_BlueField_setupFunc) +CHIPSET_SETUP_FUNC(Amazon_Gravitron2_setupFunc) +CHIPSET_SETUP_FUNC(Fujitsu_A64FX_setupFunc) +CHIPSET_SETUP_FUNC(Ampere_Altra_setupFunc) +CHIPSET_SETUP_FUNC(Arm_NeoverseN1_setupFunc) +CHIPSET_SETUP_FUNC(Nvidia_T210_setupFunc) +CHIPSET_SETUP_FUNC(Nvidia_T194_setupFunc) + + +// Keep string length <=32 (including termination) to avoid string copy overflow +CSINFO chipsetInfo[] = +{ + // PCI Express chipset + + {PCI_VENDOR_ID_INTEL, 0x2580, CS_INTEL_2580, "Grantsdale", Intel_25XX_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x2584, CS_INTEL_2584, "Alderwood", Intel_25XX_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x2588, CS_INTEL_2588, "Intel2588", Intel_25XX_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x2590, CS_INTEL_2590, "Alviso", Intel_25XX_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x25C0, CS_INTEL_25E0, "Greencreek", Intel_25E0_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x25E0, CS_INTEL_25E0, "Greencreek", Intel_25E0_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x29B0, CS_INTEL_29X0, "IntelQ35", Intel_29X0_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x29C0, CS_INTEL_29X0, "BearlakeB", Intel_29X0_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x29D0, CS_INTEL_29X0, "IntelQ33", Intel_29X0_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x29E0, CS_INTEL_29E0, "BearlakeX", Intel_29E0_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x359E, CS_INTEL_359E, "Tumwater", Intel_359E_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x4000, CS_INTEL_4000, "Stoakley", Intel_4000_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x4003, CS_INTEL_4003, "SkullTrail", Intel_4003_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x3400, CS_INTEL_3400, "IntelX58", Intel_3400_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x3403, CS_INTEL_3400, "IntelX58", Intel_3400_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x3405, CS_INTEL_3400, "IntelX58", Intel_3400_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x3406, CS_INTEL_3400, "Tylersburg", Intel_3400_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x2770, CS_INTEL_2770, "Lakeport", Intel_25XX_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x2774, CS_INTEL_2774, "Glenwood", Intel_27XX_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x277C, CS_INTEL_277C, "Glenwood", Intel_27XX_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x2A40, CS_INTEL_2A40, "Montevina", Intel_2A40_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x2E00, CS_INTEL_2E00, "Eaglelake", Intel_2E00_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x2E10, CS_INTEL_2E00, "Eaglelake", Intel_2E00_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x2E20, CS_INTEL_2E00, "Eaglelake", Intel_2E00_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x2E30, CS_INTEL_2E00, "Eaglelake", Intel_2E00_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x0044, CS_INTEL_0040, "Arrandale/Auburndale", Intel_0040_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x0062, CS_INTEL_0040, "Arrandale/Auburndale", Intel_0040_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xD130, CS_INTEL_3B42, "Clarksfield", Intel_3B42_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xD132, CS_INTEL_3B42, "Clarksfield", Intel_3B42_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x3B42, CS_INTEL_3B42, "P55/PM55/H57", Intel_3B42_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x1C46, CS_INTEL_1C46, "IntelP67-CougarPoint", Intel_1C46_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x1C4B, CS_INTEL_1C46, "HuronRiver-HM67", Intel_1C4B_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x1C4F, CS_INTEL_1C46, "HuronRiver-QM67", Intel_1C4B_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x1C49, CS_INTEL_1C49, "HuronRiver-HM65", Intel_1C49_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x1C44, CS_INTEL_1C46, "IntelZ68", Intel_1C46_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x1C10, CS_INTEL_1C10, "IntelP67", Intel_1C10_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x1D40, CS_INTEL_1D40, "IntelX79", Intel_1D40_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x1D41, CS_INTEL_1D40, "IntelX79", Intel_1D40_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x1E10, CS_INTEL_1E10, "IntelZ75", Intel_1E10_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x0150, CS_INTEL_1E10, "IntelZ77A-GD55", Intel_1E10_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x0151, CS_INTEL_1E10, "IntelZ77A-GD55", Intel_1E10_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x0100, CS_INTEL_1E10, "IntelZ77A-GD55", Intel_1E10_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x8C4B, CS_INTEL_8C4B, "SharkBay-HM87", Intel_8C4B_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x8C44, CS_INTEL_8C4B, "SharkBay-Z87", Intel_8C4B_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x8C41, CS_INTEL_8C4B, "SharkBay-H8x/P8x", Intel_8C4B_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x8C49, CS_INTEL_8C4B, "SharkBay-HM86", Intel_8C4B_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x8C52, CS_INTEL_8C4B, "SharkBay-E3", Intel_8C4B_setupFunc}, // Does not support SLI + {PCI_VENDOR_ID_INTEL, 0x8CC4, CS_INTEL_8CC4, "IntelZ97", Intel_8CC4_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x8CC3, CS_INTEL_8CC4, "IntelHM97", Intel_8CC4_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA145, CS_INTEL_A145, "IntelZ170", Intel_A145_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA14E, CS_INTEL_A145, "IntelHM170", Intel_A145_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA150, CS_INTEL_A145, "IntelHM170", Intel_A145_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA149, CS_INTEL_A145, "SkyLake C236", Intel_A145_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA14A, CS_INTEL_A145, "SkyLake C232", Intel_A145_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA14D, CS_INTEL_A145, "SkyLake-H", Intel_A145_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA244, CS_INTEL_A145, "SkyLake C620", Intel_A145_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA1C8, CS_INTEL_A145, "SkyLake C620", Intel_A145_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x8D47, CS_INTEL_8D47, "IntelX99", Intel_8D47_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x8D44, CS_INTEL_8D47, "IntelC612", Intel_8D44_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA2C5, CS_INTEL_A2C5, "IntelZ270", Intel_A2C5_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA154, CS_INTEL_A2C5, "IntelZ270", Intel_A2C5_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA152, CS_INTEL_A2C5, "IntelRX9S", Intel_A2C5_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA242, CS_INTEL_A242, "IntelC422", Intel_A242_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA241, CS_INTEL_A242, "IntelC422", Intel_A242_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA243, CS_INTEL_A242, "IntelC422", Intel_A242_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA2D2, CS_INTEL_A2D2, "IntelX299", Intel_A2D2_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA2D3, CS_INTEL_A242, "IntelC422", Intel_A242_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA1C1, CS_INTEL_A242, "IntelC621", Intel_A242_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA1C2, CS_INTEL_A242, "IntelC622", Intel_A242_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA1C3, CS_INTEL_A242, "IntelC624", Intel_A242_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA1C4, CS_INTEL_A242, "IntelC625", Intel_A242_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA1C5, CS_INTEL_A242, "IntelC626", Intel_A242_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA1C6, CS_INTEL_A242, "IntelC627", Intel_A242_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA1C7, CS_INTEL_A242, "IntelC628", Intel_A242_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA2C9, CS_INTEL_A2C9, "IntelZ370", Intel_A2C9_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA310, CS_INTEL_A2C9, "IntelZ370", Intel_A2C9_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA30E, CS_INTEL_A2C9, "IntelZ370", Intel_A2C9_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA305, CS_INTEL_A2C9, "IntelZ390", Intel_A2C9_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA30D, CS_INTEL_A2C9, "IntelH370", Intel_A2C9_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA301, CS_INTEL_A301, "Intel-CannonLake", Intel_A301_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x0685, CS_INTEL_0685, "Intel-CometLake", Intel_0685_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA1CB, CS_INTEL_C620, "Intel-IceLake", Intel_IceLake_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x4381, CS_INTEL_4381, "Intel-RocketLake", Intel_4381_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x4385, CS_INTEL_4381, "Intel-RocketLake", Intel_4381_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x7A82, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x7A84, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x1B81, CS_INTEL_1B81, "Intel-SapphireRapids", NULL}, + {PCI_VENDOR_ID_INTEL, 0x18DC, CS_INTEL_18DC, "Intel-IceLake", Intel_IceLake_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x7A04, CS_INTEL_7A04, "Intel-RaptorLake", Intel_7A04_setupFunc}, + + {PCI_VENDOR_ID_NVIDIA, 0x0FAE, CS_NVIDIA_T210, "T210", Nvidia_T210_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x0FAF, CS_NVIDIA_T210, "T210", Nvidia_T210_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x10E5, CS_NVIDIA_T186, "T186", Nvidia_T210_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x10E6, CS_NVIDIA_T186, "T186", Nvidia_T210_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x1AD0, CS_NVIDIA_T194, "T194", Nvidia_T194_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x1AD1, CS_NVIDIA_T194, "T194", Nvidia_T194_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x1AD2, CS_NVIDIA_T194, "T194", Nvidia_T194_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x229A, CS_NVIDIA_T234, "T234", Nvidia_T194_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x229C, CS_NVIDIA_T234, "T234", Nvidia_T194_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x229E, CS_NVIDIA_T234, "T234", Nvidia_T194_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22C2, CS_NVIDIA_T23x, "T23x", Nvidia_T194_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22C3, CS_NVIDIA_T23x, "T23x", Nvidia_T194_setupFunc}, + + {PCI_VENDOR_ID_SIS, 0x0649, CS_SIS_649, "649", SiS_656_setupFunc}, + {PCI_VENDOR_ID_SIS, 0x0656, CS_SIS_656, "656", SiS_656_setupFunc}, + + {PCI_VENDOR_ID_ATI, 0x5A31, CS_ATI_RS400, "RS400", ATI_RS400_setupFunc}, + {PCI_VENDOR_ID_ATI, 0x5A33, CS_ATI_RS400, "RS400", ATI_RS400_setupFunc}, + {PCI_VENDOR_ID_ATI, 0x5950, CS_ATI_RS480, "RS480", ATI_RS480_setupFunc}, + {PCI_VENDOR_ID_ATI, 0x5951, CS_ATI_RS480, "RS480", ATI_RS480_setupFunc}, + {PCI_VENDOR_ID_ATI, 0x5956, CS_ATI_FX790, "FX790" ,AMD_FX790_setupFunc}, + {PCI_VENDOR_ID_ATI, 0x5A11, CS_ATI_FX890, "FX890" ,AMD_FX890_setupFunc}, + {PCI_VENDOR_ID_ATI, 0x5a13, CS_ATI_RD850, "RD850" ,ATI_RD870_setupFunc}, + {PCI_VENDOR_ID_ATI, 0x5a12, CS_ATI_RD870, "RD870" ,ATI_RD870_setupFunc}, + {PCI_VENDOR_ID_ATI, 0x5a10, CS_ATI_RD890, "RD890" ,ATI_RD890_setupFunc}, + {PCI_VENDOR_ID_ATI, 0x5957, CS_ATI_RX780, "RX780" ,ATI_RX780_setupFunc}, + {PCI_VENDOR_ID_ATI, 0x5A14, CS_ATI_FX990, "FX990/X990/970",ATI_FX990_setupFunc}, + + {PCI_VENDOR_ID_AMD, 0x9601, CS_AMD_GX890, "GX890" ,AMD_FX890_setupFunc}, + {PCI_VENDOR_ID_AMD, 0x9600, CS_AMD_RS780, "RS780" ,AMD_RS780_setupFunc}, + {PCI_VENDOR_ID_AMD, 0x790e, CS_AMD_X370, "X370/X399/X470/ TRX40/X570/WRX80", AMD_X370_setupFunc }, + + {PCI_VENDOR_ID_VIA, 0x0308, CS_VIA_VT8369B, "VT8369B", NULL}, + {PCI_VENDOR_ID_VIA, 0x0410, CS_VIA_VX900, "VX900", VIA_VX900_setupFunc}, + {PCI_VENDOR_ID_APM, 0xe004, CS_APM_STORM, "X-Gene Storm", APM_Storm_setupFunc}, + {PCI_VENDOR_ID_IBM, 0x03DC, CS_IBM_VENICE, "Venice", NULL}, + {PCI_VENDOR_ID_MARVELL, 0xAF00, CS_MARVELL_THUNDERX2, "Marvell ThunderX2", Marvell_ThunderX2_setupFunc}, + {PCI_VENDOR_ID_REDHAT, 0x0008, CS_REDHAT_QEMU, "QEMU Redhat", QEMU_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE005, CS_AMPERE_EMAG, "AMPERE eMag", Ampere_eMag_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE006, CS_AMPERE_EMAG, "AMPERE eMag", Ampere_eMag_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE007, CS_AMPERE_EMAG, "AMPERE eMag", Ampere_eMag_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE008, CS_AMPERE_EMAG, "AMPERE eMag", Ampere_eMag_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE009, CS_AMPERE_EMAG, "AMPERE eMag", Ampere_eMag_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE00A, CS_AMPERE_EMAG, "AMPERE eMag", Ampere_eMag_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE00B, CS_AMPERE_EMAG, "AMPERE eMag", Ampere_eMag_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE00C, CS_AMPERE_EMAG, "AMPERE eMag", Ampere_eMag_setupFunc}, + {PCI_VENDOR_ID_HUAWEI, 0xA120, CS_HUAWEI_KUNPENG920, "Huawei Kunpeng920", Huawei_Kunpeng920_setupFunc}, + {PCI_VENDOR_ID_MELLANOX, 0xA2D0, CS_MELLANOX_BLUEFIELD, "Mellanox BlueField", Mellanox_BlueField_setupFunc}, + {PCI_VENDOR_ID_MELLANOX, 0xA2D4, CS_MELLANOX_BLUEFIELD2, "Mellanox BlueField 2", NULL}, + {PCI_VENDOR_ID_MELLANOX, 0xA2D5, CS_MELLANOX_BLUEFIELD2, "Mellanox BlueField 2 Crypto disabled", NULL}, + {PCI_VENDOR_ID_AMAZON, 0x0200, CS_AMAZON_GRAVITRON2, "Amazon Gravitron2", Amazon_Gravitron2_setupFunc}, + {PCI_VENDOR_ID_FUJITSU, 0x1952, CS_FUJITSU_A64FX, "Fujitsu A64FX", Fujitsu_A64FX_setupFunc}, + {PCI_VENDOR_ID_CADENCE, 0xDC01, CS_PHYTIUM_S2500, "Phytium S2500", NULL}, + {PCI_VENDOR_ID_CADENCE, 0xDC08, CS_PHYTIUM_S2500, "Phytium S2500", NULL}, + {PCI_VENDOR_ID_CADENCE, 0xDC16, CS_PHYTIUM_S2500, "Phytium S2500", NULL}, + {PCI_VENDOR_ID_CADENCE, 0xFC01, CS_PHYTIUM_S2500, "Phytium S2500", NULL}, + {PCI_VENDOR_ID_CADENCE, 0xFC08, CS_PHYTIUM_S2500, "Phytium S2500", NULL}, + {PCI_VENDOR_ID_CADENCE, 0xFC16, CS_PHYTIUM_S2500, "Phytium S2500", NULL}, + {PCI_VENDOR_ID_AMPERE, 0xE000, CS_AMPERE_ALTRA, "Ampere Altra", Ampere_Altra_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE00D, CS_AMPERE_ALTRA, "Ampere Altra", Ampere_Altra_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE00E, CS_AMPERE_ALTRA, "Ampere Altra", Ampere_Altra_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE010, CS_AMPERE_ALTRA, "Ampere Altra", Ampere_Altra_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE100, CS_AMPERE_ALTRA, "Ampere Altra", Ampere_Altra_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE110, CS_AMPERE_ALTRA, "Ampere Altra", Ampere_Altra_setupFunc}, + {PCI_VENDOR_ID_ARM, 0x0100, CS_ARM_NEOVERSEN1, "Arm Neoverse N1", Arm_NeoverseN1_setupFunc}, + {PCI_VENDOR_ID_HYGON, 0x790E, CS_HYGON_C86, "Hygon-C86-7151", NULL}, + {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN96XX, "Marvell Octeon CN96xx", ARMV8_generic_setupFunc}, + {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN98XX, "Marvell Octeon CN98xx", ARMV8_generic_setupFunc}, + +/////////////////////////////////////////////////////////////////////////////////////////////////// + + // last element must have chipset CS_UNKNOWN (zero) + {0, 0, CS_UNKNOWN, "Unknown", NULL} +}; + + +VENDORNAME vendorName[] = +{ + {PCI_VENDOR_ID_NVIDIA, "NVIDIA"}, + {PCI_VENDOR_ID_INTEL, "Intel"}, + {PCI_VENDOR_ID_VIA, "VIA"}, + {PCI_VENDOR_ID_RCC, "ServerWorks"}, + {PCI_VENDOR_ID_MICRON_1, "Micron"}, + {PCI_VENDOR_ID_MICRON_2, "Micron"}, + {PCI_VENDOR_ID_APPLE, "Apple"}, + {PCI_VENDOR_ID_SIS, "SiS"}, + {PCI_VENDOR_ID_ATI, "ATI"}, + {PCI_VENDOR_ID_TRANSMETA, "Transmeta"}, + {PCI_VENDOR_ID_HP, "HP"}, + {PCI_VENDOR_ID_AMD, "AMD"}, + {PCI_VENDOR_ID_ALI, "ALi"}, + {PCI_VENDOR_ID_APM, "AppliedMicro"}, + {PCI_VENDOR_ID_IBM, "IBM"}, + {PCI_VENDOR_ID_MARVELL, "MarvellThunderX2"}, + {PCI_VENDOR_ID_REDHAT, "QemuRedhat"}, + {PCI_VENDOR_ID_AMPERE, "AmpereComputing"}, + {PCI_VENDOR_ID_HUAWEI, "Huawei"}, + {PCI_VENDOR_ID_MELLANOX, "Mellanox"}, + {PCI_VENDOR_ID_AMAZON, "Amazon"}, + {PCI_VENDOR_ID_FUJITSU, "Fujitsu"}, + {PCI_VENDOR_ID_CADENCE, "Cadence"}, + {PCI_VENDOR_ID_ARM, "ARM"}, + {0, "Unknown"} // Indicates end of the table +}; + + +// +// Allowlist all chipsets with which dGPU over PCIe is supported on ARM +// (both v7 and v8) platforms +// +ARMCSALLOWLISTINFO armChipsetAllowListInfo[] = +{ + {PCI_VENDOR_ID_NVIDIA, 0x0FAE, CS_NVIDIA_T210}, // NVIDIA Tegra X1 RP0 + {PCI_VENDOR_ID_NVIDIA, 0x0FAF, CS_NVIDIA_T210}, // NVIDIA Tegra X1 RP1 + {PCI_VENDOR_ID_NVIDIA, 0x10E5, CS_NVIDIA_T186}, // NVIDIA Tegra P1 RP0 + {PCI_VENDOR_ID_NVIDIA, 0x10E6, CS_NVIDIA_T186}, // NVIDIA Tegra P1 RP1 + {PCI_VENDOR_ID_NVIDIA, 0x1AD0, CS_NVIDIA_T194}, // NVIDIA Tegra V1 RP0 + {PCI_VENDOR_ID_NVIDIA, 0x1AD1, CS_NVIDIA_T194}, // NVIDIA Tegra V1 RP1 + {PCI_VENDOR_ID_NVIDIA, 0x1AD2, CS_NVIDIA_T194}, // NVIDIA Tegra V1 RP2 + {PCI_VENDOR_ID_NVIDIA, 0x229A, CS_NVIDIA_T234}, // NVIDIA Tegra Orin RP0 + {PCI_VENDOR_ID_NVIDIA, 0x229C, CS_NVIDIA_T234}, // NVIDIA Tegra Orin RP1 + {PCI_VENDOR_ID_NVIDIA, 0x229E, CS_NVIDIA_T234}, // NVIDIA Tegra Orin RP2 + {PCI_VENDOR_ID_NVIDIA, 0x22C2, CS_NVIDIA_T23x}, // NVIDIA Tegra RP0 + {PCI_VENDOR_ID_NVIDIA, 0x22C3, CS_NVIDIA_T23x}, // NVIDIA Tegra RP1 + + {PCI_VENDOR_ID_APM, 0xe004, CS_APM_STORM}, // Applied Micro X-Gene "Storm" + {PCI_VENDOR_ID_MARVELL, 0xAF00, CS_MARVELL_THUNDERX2}, // Marvell ThunderX2 + {PCI_VENDOR_ID_REDHAT, 0x0008, CS_REDHAT_QEMU}, // Redhat QEMU + {PCI_VENDOR_ID_AMPERE, 0xE005, CS_AMPERE_EMAG}, // Ampere eMag + {PCI_VENDOR_ID_AMPERE, 0xE006, CS_AMPERE_EMAG}, // Ampere eMag + {PCI_VENDOR_ID_AMPERE, 0xE007, CS_AMPERE_EMAG}, // Ampere eMag + {PCI_VENDOR_ID_AMPERE, 0xE008, CS_AMPERE_EMAG}, // Ampere eMag + {PCI_VENDOR_ID_AMPERE, 0xE009, CS_AMPERE_EMAG}, // Ampere eMag + {PCI_VENDOR_ID_AMPERE, 0xE00A, CS_AMPERE_EMAG}, // Ampere eMag + {PCI_VENDOR_ID_AMPERE, 0xE00B, CS_AMPERE_EMAG}, // Ampere eMag + {PCI_VENDOR_ID_AMPERE, 0xE00C, CS_AMPERE_EMAG}, // Ampere eMag + {PCI_VENDOR_ID_HUAWEI, 0xA120, CS_HUAWEI_KUNPENG920}, // Huawei Kunpeng 920 + {PCI_VENDOR_ID_MELLANOX, 0xA2D0, CS_MELLANOX_BLUEFIELD}, // Mellanox BlueField + {PCI_VENDOR_ID_MELLANOX, 0xA2D4, CS_MELLANOX_BLUEFIELD2},// Mellanox BlueField 2 + {PCI_VENDOR_ID_MELLANOX, 0xA2D5, CS_MELLANOX_BLUEFIELD2},// Mellanox BlueField 2 Crypto disabled + {PCI_VENDOR_ID_AMAZON, 0x0200, CS_AMAZON_GRAVITRON2}, // Amazon Gravitron2 + {PCI_VENDOR_ID_FUJITSU, 0x1952, CS_FUJITSU_A64FX}, // Fujitsu A64FX + {PCI_VENDOR_ID_CADENCE, 0xDC01, CS_PHYTIUM_S2500}, // Phytium S2500 + {PCI_VENDOR_ID_CADENCE, 0xDC08, CS_PHYTIUM_S2500}, // Phytium S2500 + {PCI_VENDOR_ID_CADENCE, 0xDC16, CS_PHYTIUM_S2500}, // Phytium S2500 + {PCI_VENDOR_ID_CADENCE, 0xFC01, CS_PHYTIUM_S2500}, // Phytium S2500 + {PCI_VENDOR_ID_CADENCE, 0xFC08, CS_PHYTIUM_S2500}, // Phytium S2500 + {PCI_VENDOR_ID_CADENCE, 0xFC16, CS_PHYTIUM_S2500}, // Phytium S2500 + {PCI_VENDOR_ID_AMPERE, 0xE000, CS_AMPERE_ALTRA}, // Ampere Altra + {PCI_VENDOR_ID_AMPERE, 0xE00D, CS_AMPERE_ALTRA}, // Ampere Altra + {PCI_VENDOR_ID_AMPERE, 0xE00E, CS_AMPERE_ALTRA}, // Ampere Altra + {PCI_VENDOR_ID_AMPERE, 0xE010, CS_AMPERE_ALTRA}, // Ampere Altra + {PCI_VENDOR_ID_AMPERE, 0xE100, CS_AMPERE_ALTRA}, // Ampere Altra + {PCI_VENDOR_ID_AMPERE, 0xE110, CS_AMPERE_ALTRA}, // Ampere Altra + {PCI_VENDOR_ID_ARM, 0x0100, CS_ARM_NEOVERSEN1}, // Arm Neoverse N1 + {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN96XX}, // Marvell OCTEON CN96xx + {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN98XX}, // Marvell OCTEON CN98xx + + // last element must have chipset CS_UNKNOWN (zero) + {0, 0, CS_UNKNOWN} +}; + +#endif /* NVCST_H */ diff --git a/userspace/sdks/nv525/nvalloc/common/inc/nvdevid.h b/userspace/sdks/nv525/nvalloc/common/inc/nvdevid.h new file mode 100644 index 0000000..559bcb7 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/nvdevid.h @@ -0,0 +1,697 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 200-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVDEVID_H +#define NVDEVID_H + + + +/**************** Resource Manager Defines and Structures ******************\ +* * +* Private device ids defines - only defines ! * +* * +\***************************************************************************/ + +/////////////////////////////////////////////////////////////////////////////////////////// +// +// VENDOR/SUBVENDOR IDS +// XXX Cleanup to do: change PCI_VENDOR_* to NV_PCI_SUBID_VENDOR_* +// +/////////////////////////////////////////////////////////////////////////////////////////// +#define NV_PCI_SUBID_VENDOR 15:0 /* RW--F */ +#define NV_PCI_SUBID_VENDOR_AMD 0x1022 +#define NV_PCI_SUBID_VENDOR_ALI 0x10B9 +#define NV_PCI_SUBID_VENDOR_NVIDIA 0x10DE +#define NV_PCI_SUBID_VENDOR_INTEL 0x8086 +#define NV_PCI_SUBID_VENDOR_VIA 0x1106 +#define NV_PCI_SUBID_VENDOR_RCC 0x1166 +#define NV_PCI_SUBID_VENDOR_MICRON_1 0x1042 +#define NV_PCI_SUBID_VENDOR_MICRON_2 0x1344 +#define NV_PCI_SUBID_VENDOR_APPLE 0x106B +#define NV_PCI_SUBID_VENDOR_SIS 0x1039 +#define NV_PCI_SUBID_VENDOR_ATI 0x1002 +#define NV_PCI_SUBID_VENDOR_TRANSMETA 0x1279 +#define NV_PCI_SUBID_VENDOR_HP 0x103C +#define NV_PCI_SUBID_VENDOR_DELL 0x1028 +#define NV_PCI_SUBID_VENDOR_FUJITSU 0x10cf +#define NV_PCI_SUBID_VENDOR_ASUS 0x1043 +#define NV_PCI_SUBID_VENDOR_MSI 0x1462 +#define NV_PCI_SUBID_VENDOR_FOXCONN 0x105B +#define NV_PCI_SUBID_VENDOR_ECS 0x1019 +#define NV_PCI_SUBID_VENDOR_DFI_1 0x106E +#define NV_PCI_SUBID_VENDOR_TOSHIBA 0x1179 +#define NV_PCI_SUBID_VENDOR_DFI_2 0x15BD +#define NV_PCI_SUBID_VENDOR_ACER 0x1025 +#define NV_PCI_SUBID_VENDOR_GIGABYTE 0x1458 +#define NV_PCI_SUBID_VENDOR_EVGA 0x3842 +#define NV_PCI_SUBID_VENDOR_BROADCOM 0x1166 +#define NV_PCI_SUBID_VENDOR_SUPERMICRO 0x15D9 +#define NV_PCI_SUBID_VENDOR_BIOSTAR 0x1565 +#define NV_PCI_SUBID_VENDOR_XFX 0x1682 +#define NV_PCI_SUBID_VENDOR_PCPARTNER 0x19DA +#define NV_PCI_SUBID_VENDOR_LENOVO 0x17AA +#define NV_PCI_SUBID_VENDOR_FSC 0x1734 +#define NV_PCI_SUBID_VENDOR_FTS 0x1734 +#define NV_PCI_SUBID_VENDOR_COLORFUL 0x7377 +#define NV_PCI_SUBID_VENDOR_ASROCK 0x1849 +#define NV_PCI_SUBID_VENDOR_SHUTTLE 0x1297 +#define NV_PCI_SUBID_VENDOR_CLEVO 0x1558 +#define NV_PCI_SUBID_VENDOR_PEGATRON 0x1B0A +#define NV_PCI_SUBID_VENDOR_JETWAY 0x16F3 +#define NV_PCI_SUBID_VENDOR_HIGHGRADE 0x1C6C +#define NV_PCI_SUBID_VENDOR_GALAXY 0x1B4C +#define NV_PCI_SUBID_VENDOR_ZOTAC 0x19DA +#define NV_PCI_SUBID_VENDOR_ARIMA 0x161F +#define NV_PCI_SUBID_VENDOR_BFG 0x19F1 +#define NV_PCI_SUBID_VENDOR_SONY 0x104D +#define NV_PCI_SUBID_VENDOR_BITLAND 0x1642 +#define NV_PCI_SUBID_VENDOR_PC_PARTNER 0x174B +#define NV_PCI_SUBID_VENDOR_NZXT 0x1D96 + +// XXX CKEANUP TO REMOVE IN FAVOR OF NV_PCI_SUBID_VENDOR_* +#define PCI_VENDOR_ID_AMD 0x1022 +#define PCI_VENDOR_ID_ALI 0x10B9 +#define PCI_VENDOR_ID_NVIDIA 0x10DE +#define PCI_VENDOR_ID_INTEL 0x8086 +#define PCI_VENDOR_ID_VIA 0x1106 +#define PCI_VENDOR_ID_RCC 0x1166 +#define PCI_VENDOR_ID_MICRON_1 0x1042 +#define PCI_VENDOR_ID_MICRON_2 0x1344 +#define PCI_VENDOR_ID_APPLE 0x106B +#define PCI_VENDOR_ID_SIS 0x1039 +#define PCI_VENDOR_ID_ATI 0x1002 +#define PCI_VENDOR_ID_TRANSMETA 0x1279 +#define PCI_VENDOR_ID_HP 0x103C +#define PCI_VENDOR_ID_DELL 0x1028 +#define PCI_VENDOR_ID_FUJITSU 0x10cf +#define PCI_VENDOR_ID_ASUS 0x1043 +#define PCI_VENDOR_ID_MSI 0x1462 +#define PCI_VENDOR_ID_FOXCONN 0x105B +#define PCI_VENDOR_ID_ECS 0x1019 +#define PCI_VENDOR_ID_DFI_1 0x106E +#define PCI_VENDOR_ID_TOSHIBA 0x1179 +#define PCI_VENDOR_ID_DFI_2 0x15BD +#define PCI_VENDOR_ID_ACER 0x1025 +#define PCI_VENDOR_ID_GIGABYTE 0x1458 +#define PCI_VENDOR_ID_EVGA 0x3842 +#define PCI_VENDOR_ID_BROADCOM 0x1166 +#define PCI_VENDOR_ID_SUPERMICRO 0x15D9 +#define PCI_VENDOR_ID_BIOSTAR 0x1565 +#define PCI_VENDOR_ID_XFX 0x1682 +#define PCI_VENDOR_ID_PCPARTNER 0x19DA +#define PCI_VENDOR_ID_LENOVO 0x17AA +#define PCI_VENDOR_ID_FSC 0x1734 +#define PCI_VENDOR_ID_FTS 0x1734 +#define PCI_VENDOR_ID_COLORFUL 0x7377 +#define PCI_VENDOR_ID_ASROCK 0x1849 +#define PCI_VENDOR_ID_SHUTTLE 0x1297 +#define PCI_VENDOR_ID_CLEVO 0x1558 +#define PCI_VENDOR_ID_PEGATRON 0x1B0A +#define PCI_VENDOR_ID_JETWAY 0x16F3 +#define PCI_VENDOR_ID_HIGHGRADE 0x1C6C +#define PCI_VENDOR_ID_GALAXY 0x1B4C +#define PCI_VENDOR_ID_ZOTAC 0x19DA +#define PCI_VENDOR_ID_ARIMA 0x161F +#define PCI_VENDOR_ID_PC_PARTNER 0x174B +#define PCI_VENDOR_ID_APM 0x10E8 +#define PCI_VENDOR_ID_IBM 0x1014 +#define PCI_VENDOR_ID_NZXT 0x1D96 +#define PCI_VENDOR_ID_MARVELL 0x177D +#define PCI_VENDOR_ID_REDHAT 0x1B36 +#define PCI_VENDOR_ID_AMPERE 0x1DEF +#define PCI_VENDOR_ID_HUAWEI 0x19E5 +#define PCI_VENDOR_ID_MELLANOX 0x15B3 +#define PCI_VENDOR_ID_AMAZON 0x1D0F +#define PCI_VENDOR_ID_CADENCE 0x17CD +#define PCI_VENDOR_ID_ARM 0x13B5 +#define PCI_VENDOR_ID_HYGON 0x1D94 + +#define NV_PCI_DEVID_DEVICE 31:16 /* RW--F */ +#define NV_PCI_SUBID_DEVICE 31:16 /* RW--F */ + +/////////////////////////////////////////////////////////////////////////////////////////// +// +// GPU DEVICE IDS +// +/////////////////////////////////////////////////////////////////////////////////////////// + +#define NV_PCI_DEVID_DEVICE_PG171_SKU200_PG179_SKU220 0x25B6 /* NVIDIA A16 / NVIDIA A2 */ +#define NV_PCI_DEVID_DEVICE_PG189_SKU600 0x1EBA + +/////////////////////////////////////////////////////////////////////////////////////////// +// +// SUBDEVICE IDs +// +/////////////////////////////////////////////////////////////////////////////////////////// + +// A16 +#define NV_PCI_SUBID_DEVICE_PG171_SKU200 0x14A9 + +/////////////////////////////////////////////////////////////////////////////////////////// +// +// CHIPSET IDs +// +/////////////////////////////////////////////////////////////////////////////////////////// +// Desktop flavor of X58 +#define X58_DESKTOP_DEVIDS 0x3400, 0x3405 +// Mobile version of X58 +#define X58_MOBILE_DEVID 0x3405 +#define X58_MOBILE_CLEVO_7200_SSDEVID 0x7200 + +// Sandy bridge CLEVO platform +#define SANDYBRIDGE_P180HM_SSDEVID 0x8000 +#define SandyBridge_E_X79_P270WM_SSDEVID 0x270 +#define IvyBridge_Z75_P370EM_SSDEVID 0x371 + +// Device ID's of Devices present on Patsburg's PCIE bus. +#define PATSBURG_PCIE_DEVICE_MIN_DEVID 0x1D10 +#define PATSBURG_PCIE_DEVICE_MAX_DEVID 0x1D1F +#define PATSBURG_PCIE_DEVICE_DEVID 0x244E + +//Tylersburg Congurations +#define TYLERSBURG_DEVID 0x3406 + +// Intel Grantsdale definitions +#define DEVICE_ID_INTEL_2580_HOST_BRIDGE 0x2580 +#define DEVICE_ID_INTEL_2581_ROOT_PORT 0x2581 + +// Intel Alderwood definitions +#define DEVICE_ID_INTEL_2584_HOST_BRIDGE 0x2584 +#define DEVICE_ID_INTEL_2585_ROOT_PORT 0x2585 + +// Intel Alviso definitions +#define DEVICE_ID_INTEL_2590_HOST_BRIDGE 0x2590 +#define DEVICE_ID_INTEL_2591_ROOT_PORT 0x2591 + +// Intel Tumwater definitions +#define DEVICE_ID_INTEL_359E_HOST_BRIDGE 0x359E +#define DEVICE_ID_INTEL_3597_ROOT_PORT 0x3597 + +// Intel Stoakley definitions +#define INTEL_4000_SUBDEVICE_ID 0x021D + +// Intel SkullTrail definitions +#define INTEL_4003_SUBDEVICE_ID 0x5358 + +// Intel Core I7 CPU +#define INTEL_QUICKPATH_SYSTEM_ADDRESS_DECODER_I7 0x2C01 + +// Intel Core I5 CPU Lynnfield +#define INTEL_QUICKPATH_SYSTEM_ADDRESS_DECODER_I5_L 0x2C81 +#define INTEL_LYNNFIELD_ROOTPORT_CPU1 0xD138 +#define INTEL_LYNNFIELD_ROOTPORT_CPU2 0xD13A + +// Intel Core I5 CPU Auburndale +#define INTEL_QUICKPATH_SYSTEM_ADDRESS_DECODER_I5_A 0x2D41 + +// Intel Core I5 CPU 650 +#define INTEL_QUICKPATH_SYSTEM_ADDRESS_DECODER_I5_6 0x2D01 + +// Intel Poulsbo definitions +#define DEVICE_ID_INTEL_8100_HOST_BRIDGE 0x8100 +#define DEVICE_ID_INTEL_8110_ROOT_PORT 0x8110 +#define DEVICE_ID_INTEL_8112_ROOT_PORT 0x8112 + +// Intel TunnelCreek definitions +#define DEVICE_ID_INTEL_8180_ROOT_PORT 0x8180 +#define DEVICE_ID_INTEL_8181_ROOT_PORT 0x8181 +#define DEVICE_ID_INTEL_8184_ROOT_PORT 0x8184 +#define DEVICE_ID_INTEL_8185_ROOT_PORT 0x8185 + +// Intel I/O Hub definitions +#define DEVICE_ID_INTEL_3408_ROOT_PORT 0x3408 +#define DEVICE_ID_INTEL_3411_ROOT_PORT 0x3411 +#define DEVICE_ID_INTEL_3420_ROOT_PORT 0x3420 +#define DEVICE_ID_INTEL_3421_ROOT_PORT 0x3421 + +// Intel SandyBridge IIO definitions +#define DEVICE_ID_INTEL_3C02_ROOT_PORT 0x3c02 +#define DEVICE_ID_INTEL_3C03_ROOT_PORT 0x3c03 +#define DEVICE_ID_INTEL_3C04_ROOT_PORT 0x3c04 +#define DEVICE_ID_INTEL_3C05_ROOT_PORT 0x3c05 +#define DEVICE_ID_INTEL_3C06_ROOT_PORT 0x3c06 +#define DEVICE_ID_INTEL_3C07_ROOT_PORT 0x3c07 +#define DEVICE_ID_INTEL_3C08_ROOT_PORT 0x3c08 +#define DEVICE_ID_INTEL_3C09_ROOT_PORT 0x3c09 +#define DEVICE_ID_INTEL_3C0A_ROOT_PORT 0x3c0a +#define DEVICE_ID_INTEL_3C0B_ROOT_PORT 0x3c0b + +// Intel Haswell-E definitions +#define DEVICE_ID_INTEL_2F00_HOST_BRIDGE 0x2f00 +#define DEVICE_ID_INTEL_2F01_ROOT_PORT 0x2f01 +#define DEVICE_ID_INTEL_2F02_ROOT_PORT 0x2f02 +#define DEVICE_ID_INTEL_2F03_ROOT_PORT 0x2f03 +#define DEVICE_ID_INTEL_2F04_ROOT_PORT 0x2f04 +#define DEVICE_ID_INTEL_2F05_ROOT_PORT 0x2f05 +#define DEVICE_ID_INTEL_2F06_ROOT_PORT 0x2f06 +#define DEVICE_ID_INTEL_2F07_ROOT_PORT 0x2f07 +#define DEVICE_ID_INTEL_2F08_ROOT_PORT 0x2f08 +#define DEVICE_ID_INTEL_2F09_ROOT_PORT 0x2f09 +#define DEVICE_ID_INTEL_2F0A_ROOT_PORT 0x2f0a +#define DEVICE_ID_INTEL_2F0B_ROOT_PORT 0x2f0b + +#define DEVICE_ID_INTEL_0C01_ROOT_PORT 0x0c01 + +// Intel IvyTown definitions + +#define DEVICE_ID_INTEL_0E02_ROOT_PORT 0x0e02 +#define DEVICE_ID_INTEL_0E03_ROOT_PORT 0x0e03 +#define DEVICE_ID_INTEL_0E04_ROOT_PORT 0x0e04 +#define DEVICE_ID_INTEL_0E05_ROOT_PORT 0x0e05 +#define DEVICE_ID_INTEL_0E06_ROOT_PORT 0x0e06 +#define DEVICE_ID_INTEL_0E07_ROOT_PORT 0x0e07 +#define DEVICE_ID_INTEL_0E08_ROOT_PORT 0x0e08 +#define DEVICE_ID_INTEL_0E09_ROOT_PORT 0x0e09 +#define DEVICE_ID_INTEL_0E0A_ROOT_PORT 0x0e0a +#define DEVICE_ID_INTEL_0E0B_ROOT_PORT 0x0e0b +// Intel Ivy Bridge E definitions +#define DEVICE_ID_INTEL_0E00_HOST_BRIDGE 0x0E00 + +// Intel Haswell definitions +#define DEVICE_ID_INTEL_0C00_HASWELL_HOST_BRIDGE 0x0C00 +#define DEVICE_ID_INTEL_0C04_HASWELL_HOST_BRIDGE 0x0C04 + +// Intel PCH definitions +#define DEVICE_ID_INTEL_9D10_PCH_BRIDGE 0x9d10 +#define DEVICE_ID_INTEL_9D18_PCH_BRIDGE 0x9d18 +#define DEVICE_ID_INTEL_A117_PCH_BRIDGE 0xa117 +#define DEVICE_ID_INTEL_A118_PCH_BRIDGE 0xa118 +#define DEVICE_ID_INTEL_9C98_PCH_BRIDGE 0x9c98 + +// Intel Broadwell definitions +#define DEVICE_ID_INTEL_6F00_HOST_BRIDGE 0x6f00 +#define DEVICE_ID_INTEL_6F01_ROOT_PORT 0x6f01 +#define DEVICE_ID_INTEL_6F02_ROOT_PORT 0x6f02 +#define DEVICE_ID_INTEL_6F03_ROOT_PORT 0x6f03 +#define DEVICE_ID_INTEL_6F04_ROOT_PORT 0x6f04 +#define DEVICE_ID_INTEL_6F05_ROOT_PORT 0x6f05 +#define DEVICE_ID_INTEL_6F06_ROOT_PORT 0x6f06 +#define DEVICE_ID_INTEL_6F07_ROOT_PORT 0x6f07 +#define DEVICE_ID_INTEL_6F08_ROOT_PORT 0x6f08 +#define DEVICE_ID_INTEL_6F09_ROOT_PORT 0x6f09 +#define DEVICE_ID_INTEL_6F0A_ROOT_PORT 0x6f0A +#define DEVICE_ID_INTEL_6F0B_ROOT_PORT 0x6f0B +#define DEVICE_ID_INTEL_1601_ROOT_PORT 0x1601 +#define DEVICE_ID_INTEL_1605_ROOT_PORT 0x1605 +#define DEVICE_ID_INTEL_1609_ROOT_PORT 0x1609 +#define DEVICE_ID_INTEL_BROADWELL_U_HOST_BRIDGE 0x1604 +#define DEVICE_ID_INTEL_BROADWELL_H_HOST_BRIDGE 0x1614 + +// Intel Skylake definitions +#define DEVICE_ID_INTEL_1901_ROOT_PORT 0x1901 +#define DEVICE_ID_INTEL_1905_ROOT_PORT 0x1905 +#define DEVICE_ID_INTEL_1909_ROOT_PORT 0x1909 +#define DEVICE_ID_INTEL_SKYLAKE_U_HOST_BRIDGE 0x1904 +#define DEVICE_ID_INTEL_SKYLAKE_S_HOST_BRIDGE 0x191F +#define DEVICE_ID_INTEL_SKYLAKE_H_HOST_BRIDGE 0x1910 + +// Intel Skylake-E definitions +#define DEVICE_ID_INTEL_2030_ROOT_PORT 0x2030 +#define DEVICE_ID_INTEL_2033_ROOT_PORT 0x2033 + +// Intel Kabylake definitions +#define DEVICE_ID_INTEL_KABYLAKE_U_HOST_BRIDGE 0x5904 +#define DEVICE_ID_INTEL_KABYLAKE_H_HOST_BRIDGE 0x5910 + +// AMD Matisse, Rome definitions +#define DEVICE_ID_AMD_1483_ROOT_PORT 0x1483 +// AMD Castle Peak definition +#define DEVICE_ID_AMD_1480_ROOT_PORT 0x1480 +// AMD Renoir-H definition +#define DEVICE_ID_AMD_1630_ROOT_PORT 0x1630 + +// Dell SkullTrail definitions +#define DELL_4003_SUBDEVICE_ID 0x021D + +// Dell Quicksilver MLK definitions +#define DELL_0040_SUBDEVICE_ID 0x043a + +// HP Tylersburg definitions +#define TYLERSBURG_Z800_SSDEVID 0x130B + +// HP Romley definitions +#define ROMLEY_Z820_SSDEVID 0x158B +#define ROMLEY_Z620_SSDEVID 0x158A +#define ROMLEY_Z420_SSDEVID 0x1589 + +// HP Grantley definitions +#define GRANTLEY_Z840_SSDEVID 0x2129 +#define GRANTLEY_Z640_SSDEVID 0x212A +#define GRANTLEY_Z440_SSDEVID 0x212B + +// HP PURELY definitions +#define HP_QUADRO_Z4GEN4_DEVID 0xA2D2 +#define PURLEY_Z8GEN4_SSDEVID 0x81C7 +#define PURLEY_Z6GEN4_SSDEVID 0x81C6 +#define PURLEY_Z4GEN4_SSDEVID 0x81C5 + +// Lenovo Romley definitions +#define ROMLEY_C30_SSDEVID 0x1028 +#define ROMLEY_D30_SSDEVID 0x1027 +#define ROMLEY_S30_SSDEVID 0x1026 + +// Dell Romley definitions +#define ROMLEY_T7600_SSDEVID 0x0495 +#define ROMLEY_T5600_SSDEVID 0x0496 +#define ROMLEY_T3600_SSDEVID 0x0497 + +// Dell Romley + IVB-EP CPU Refresh +#define IVYTOWN_T7610_SSDEVID 0x05D4 +#define IVYTOWN_T5610_SSDEVID 0x05D3 + +// Dell Romley (Ipanema) +#define ROMLEY_R7610_SSDEVID 0x05A1 + +// FTS Romley definitions +#define ROMLEY_R920_SSDEVID 0x11B6 + +// Lenovo Grantley (Messi, Pele, Ronaldo) +#define GRANTLEY_V40_SSDEVID 0x1031 +#define GRANTLEY_D40_SSDEVID 0x1030 +#define GRANTLEY_S40_SSDEVID 0x102F + +// Dell Grantley (Avalon) +#define GRANTLEY_T7810_SSDEVID 0x0618 +#define GRANTLEY_T7910_SSDEVID 0x0619 + +// Lenovo Purley (Nile, Volga) +#define PURLEY_P920_SSDEVID 0x1038 +#define PURLEY_P720_SSDEVID 0x1037 +#define PURLEY_P520_SSDEVID 0x1036 + +// Lenovo P520c +#define LENOVO_P520C_SSDEVID 0x103C + +// Dell Purley(Matira) +#define PURLEY_MATIRA3X_DEVID 0xA2D2 +#define PURLEY_MATIRA3X_SSDEVID 0x08B1 +#define PURLEY_MATIRA3_SSDEVID 0x0738 +#define PURLEY_MATIRA5_SSDEVID 0x0739 +#define PURLEY_MATIRA7_SSDEVID 0x073A + +//FTS Grantley +#define GRANTLEY_R940_SSDEVID 0x1201 + +//FTS Purley +#define PURLEY_R970_SSDEVID 0x1230 +#define PURLEY_M770_SSDEVID 0x1231 + +// HP Arrandale, Clarksfield, X58 workstation definitions +#define ARRANDALE_Z200SFF_SSDEVID 0x304A +#define CLARKSFIELD_Z200_SSDEVID 0x170B +#define X58_Z400_SSDEVID 0x1309 + +// GIGABYTE Sniper 3 (Z77) +#define GIGABYTE_SNIPER_3_SSDEVID_1 0x5000 +#define GIGABYTE_SNIPER_3_SSDEVID_2 0x5001 + +// Supermicro Quadro VCA definitions +#define SUPERMICRO_QUADRO_VCA_DEVID 0x8D44 +#define SUPERMICRO_QUADRO_VCA_SSDEVID 0x7270 + +// Supermicro SYS-4027GR-TRT +#define SUPERMICRO_SYS_4027GR_TRT_DEVID 0x1D41 +#define SUPERMICRO_SYS_4027GR_TRT_SSDEVID 0x0732 + +// Supermicro SYS-4029GP-TRT2 +#define SUPERMICRO_SYS_4029GP_TRT2_DEVID 0xA1C2 +#define SUPERMICRO_SYS_4029GP_TRT2_SSDEVID 0x7270 + +// Asus Quadro BOXX definitions +#define ASUS_QUADRO_BOXX_DEVID 0x8D44 +#define ASUS_QUADRO_BOXX_SSDEVID 0x85F6 + +// APEXX8 Quadro BOXX definitions +#define APEXX8_QUADRO_BOXX_DEVID 0xA2D3 +#define APEXX8_QUADRO_BOXX_SSDEVID 0x098e + +// APEXX5 Quadro BOXX definitions +#define APEXX5_QUADRO_BOXX_DEVID 0xA2D3 +#define APEXX5_QUADRO_BOXX_SSDEVID 0x1000 + +// ASUS X99-E-10G +#define ASUS_X99_E_10G_SSDEVID 0x8600 + +// VIA definitions +#define DEVICE_ID_VIA_VT8369B_HOST_BRIDGE 0x0308 + +// Foxconn Einstein 64 [8086:a1c1][105b:7270] +#define FOXCONN_EINSTEIN_64_DEVID 0xA1C1 +#define FOXCONN_EINSTEIN_64_SSDEVID 0x7270 + +// Tyan Workstation +#define TYAN_B7100_DEVID 0xA1C1 +#define TYAN_B7100_SSDEVID 0x7270 + +// ESC 4000 Series Workstation +#define ESC_4000_G4_DEVID 0xA1C1 +#define ESC_4000_G4_SSDEVID 0x871E + + +// NVIDIA C51 +#define NVIDIA_C51_DEVICE_ID_MIN 0x2F0 +#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_0 0x2F0 +#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_1 0x2F1 +#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_2 0x2F2 +#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_3 0x2F3 +#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_IGPU_DISABLE_0 0x2F4 +#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_IGPU_DISABLE_1 0x2F5 +#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_IGPU_DISABLE_2 0x2F6 +#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_IGPU_DISABLE_3 0x2F7 +#define NVIDIA_C51_DEVICE_ID_MAX 0x2F7 + +// NVIDIA MCP55 +#define NVIDIA_MCP55_ULDT_CFG_0_DEVICE_ID_DEFAULT 0x0369 + +// NVIDIA MCP61 +#define NVIDIA_MCP61_ULDT_CFG_0_DEVICE_ID_DEFAULT 0x03EA +#define NVIDIA_MCP61_ULDT_CFG_0_DEVICE_ID_PA 0x03E2 + +// NVIDIA C55 +#define NVIDIA_C55_CPU_PCI_0_DEVICE_ID_PRO 0x03A0 +#define NVIDIA_C55_CPU_PCI_0_DEVICE_ID_PRO 0x03A0 +#define NVIDIA_C55_CPU_PCI_0_DEVICE_ID_SLIX16 0x03A1 +#define NVIDIA_C55_CPU_PCI_0_DEVICE_ID_SLI 0x03A3 +#define NVIDIA_C55_CPU_PCI_0_DEVICE_ID_U 0x03A2 + +// NVIDIA MCP65 +#define NVIDIA_MCP65_ULDT_CFG_0_DEVICE_ID_DEFAULT 0x0444 + +// NVIDIA MCP67/MCP68 +#define NVIDIA_MCP67_ULDT_CFG_0_DEVICE_ID_DEFAULT 0x0547 + +// NVIDIA MCP73 +#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_PV 0x07C0 +#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_O 0x07C1 +#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_S 0x07C2 +#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_V 0x07C3 +#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_RSVD_0 0x07C4 +#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_RSVD_1 0x07C5 +#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_RSVD_2 0x07C6 +#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_D 0x07C7 + +// NVIDIA C73 +#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_SLI2 0x0800 +#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_SLI_ALL 0x0801 +#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_SLIX8 0x0802 +#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_U 0x0803 +#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_RESERVED_0 0x0804 +#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_RESERVED_1 0x0805 +#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_RESERVED_2 0x0806 +#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_RESERVED_3 0x0807 + +// NVIDIA MCP77/78 +#define NVIDIA_MCP77_ULDT_CFG_0_DEVICE_ID_DEFAULT 0x0754 +#define NVIDIA_MCP77_ULDT_CFG_0_DEVICE_ID_1 0x0755 +#define NVIDIA_MCP77_ULDT_CFG_0_DEVICE_ID_2 0x0756 +#define NVIDIA_MCP77_ULDT_CFG_0_DEVICE_ID_3 0x0757 +#define NVIDIA_MCP77_MCP_SM_CFG_0_DEVICE_ID_UNIT_SM 0x0752 + +// NVIDIA MCP79/7A +#define NVIDIA_MCP79_CPU_PCI_0_DEVICE_ID_DEFAULT 0x0A80 +#define NVIDIA_MCP79_CPU_PCI_0_DEVICE_ID_SLIX16 0x0A81 +#define NVIDIA_MCP79_CPU_PCI_0_DEVICE_ID_SLI 0x0A82 +#define NVIDIA_MCP79_CPU_PCI_0_DEVICE_ID_U 0x0A83 +#define NVIDIA_MCP79_CPU_PCI_0_DEVICE_ID_GM 0x0A84 +#define NVIDIA_MCP79_CPU_PCI_0_DEVICE_ID_GVM 0x0A85 +#define NVIDIA_MCP79_MCP_SM_CFG_0_DEVICE_ID_UNIT_SM 0x0AA2 + +// NVIDIA MCP89/P83 +#define NVIDIA_MCP89_CPU_PCI_0_DEVICE_ID_DEFAULT 0x00000D60 + +/////////////////////////////////////////////////////////////////////////////////////////// +// +// enumeration of chipset families +// +/////////////////////////////////////////////////////////////////////////////////////////// + +// +// When adding a variable to the following enum, please +// add it also to the following chipset_names[]. +// +enum { + CS_UNKNOWN = 0x0000, + CS_UNKNOWN_PCIE = 0x1000 +, CS_INTEL_2580 +, CS_INTEL_2584 +, CS_INTEL_2588 +, CS_INTEL_2590 +, CS_INTEL_25E0 +, CS_INTEL_29X0 +, CS_INTEL_29E0 +, CS_INTEL_359E +, CS_INTEL_4000 +, CS_INTEL_4003 +, CS_INTEL_3400 +, CS_INTEL_3B42 +, CS_INTEL_2770 +, CS_INTEL_2774 +, CS_INTEL_277C +, CS_INTEL_2A40 +, CS_INTEL_2E00 +, CS_INTEL_0040 +, CS_INTEL_1C10 +, CS_INTEL_1C46 +, CS_INTEL_1C49 +, CS_INTEL_1D40 +, CS_INTEL_8D47 +, CS_INTEL_1E10 +, CS_INTEL_8C4B +, CS_INTEL_8CC4 +, CS_INTEL_A145 +, CS_INTEL_A2C5 +, CS_INTEL_A242 +, CS_INTEL_A2D2 +, CS_INTEL_A2C9 +, CS_INTEL_A301 +, CS_INTEL_0685 +, CS_INTEL_4381 +, CS_INTEL_7A82 +, CS_NVIDIA_CK804 +, CS_NVIDIA_C19 +, CS_NVIDIA_C51 +, CS_NVIDIA_MCP55 +, CS_NVIDIA_MCP61 +, CS_NVIDIA_C55 +, CS_NVIDIA_MCP65 +, CS_NVIDIA_MCP67 +, CS_NVIDIA_MCP73 +, CS_NVIDIA_C73 +, CS_NVIDIA_MCP77 +, CS_NVIDIA_MCP79 +, CS_NVIDIA_MCP89 +, CS_NVIDIA_TEGRA3 +, CS_SIS_649 +, CS_SIS_656 +, CS_ATI_RS400 +, CS_ATI_RS400_A21 +, CS_ATI_RS480 +, CS_ATI_RS480_A21 +, CS_AMD_RS780 +, CS_VIA_VT8369B +, CS_ATI_FX790 +, CS_ATI_RD850 +, CS_ATI_RD870 +, CS_ATI_RD890 +, CS_ATI_FX890 +, CS_ATI_RX780 +, CS_ATI_FX990 +, CS_AMD_GX890 +, CS_AMD_X370 +, CS_VIA_VX900 +, CS_APM_STORM +, CS_IBM_VENICE +, CS_NVIDIA_T124 +, CS_NVIDIA_T210 +, CS_NVIDIA_T186 +, CS_NVIDIA_T194 +, CS_NVIDIA_T234 +, CS_NVIDIA_T23x +, CS_MARVELL_THUNDERX2 +, CS_REDHAT_QEMU +, CS_AMPERE_EMAG +, CS_HUAWEI_KUNPENG920 +, CS_MELLANOX_BLUEFIELD +, CS_AMAZON_GRAVITRON2 +, CS_FUJITSU_A64FX +, CS_AMPERE_ALTRA +, CS_ARM_NEOVERSEN1 +, CS_MARVELL_OCTEON_CN96XX +, CS_MARVELL_OCTEON_CN98XX +, CS_INTEL_C620 +, CS_HYGON_C86 +, CS_PHYTIUM_S2500 +, CS_MELLANOX_BLUEFIELD2 +, CS_INTEL_1B81 +, CS_INTEL_18DC +, CS_INTEL_7A04 +, CS_MAX_PCIE +}; + +enum { + RP_UNKNOWN = 0 +, RP_BROADCOM_HT2100 +, RP_INTEL_2581 +, RP_INTEL_2585 +, RP_INTEL_2589 +, RP_INTEL_2591 +, RP_INTEL_3597 +, RP_INTEL_2775 +, RP_INTEL_2771 +, RP_INTEL_8110 +, RP_INTEL_8112 +, RP_INTEL_8180 +, RP_INTEL_8181 +, RP_INTEL_8184 +, RP_INTEL_8185 +, RP_INTEL_3C02 +, RP_INTEL_3C03 +, RP_INTEL_3C04 +, RP_INTEL_3C05 +, RP_INTEL_3C06 +, RP_INTEL_3C07 +, RP_INTEL_3C08 +, RP_INTEL_3C09 +, RP_INTEL_3C0A +, RP_INTEL_3C0B +, RP_INTEL_2F04 +, RP_INTEL_2F08 +, RP_INTEL_0C01 +, RP_INTEL_1601 +, RP_INTEL_1605 +, RP_INTEL_1609 +, RP_INTEL_1901 +, RP_INTEL_1905 +, RP_INTEL_1909 +, RP_INTEL_5904 +, RP_NVIDIA_CK804 +, RP_NVIDIA_C19 +, RP_NVIDIA_C51 +, RP_NVIDIA_MCP55 +, RP_NVIDIA_MCP61 +, RP_NVIDIA_C55 +, RP_NVIDIA_MCP65 +}; + +#endif //NVDEVID_H + diff --git a/userspace/sdks/nv525/nvalloc/common/inc/nvpcie.h b/userspace/sdks/nv525/nvalloc/common/inc/nvpcie.h new file mode 100644 index 0000000..6b5c7ca --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/nvpcie.h @@ -0,0 +1,499 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2000-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVPCIE_H +#define NVPCIE_H + +/**************** Resource Manager Defines and Structures ******************\ +* * +* Private PCI Express related defines and structures. * +* * +\***************************************************************************/ + +#define PCI_VENDOR_ID 0x00 +#ifndef PCI_DEVICE_ID +#define PCI_DEVICE_ID 0x02 +#endif +#define PCI_BASE_ADDRESS_1 0x14 /* Aperture Base */ +#define PCI_BASE_ADDRESS_2 0x18 /* Aperture Base */ +#define PCI_CAPABILITY_LIST 0x34 +#define PCI_DEVICE_SPECIFIC 0x40 + +#define NV_PCI_ID 0x0 +#define NV_PCI_ID_VENDOR 15:0 +#define NV_PCI_ID_VENDOR_NVIDIA 0x10DE +#define NV_PCI_ID_DEVICE 31:16 + +#define PCI_MAX_SLOTS 255 +#define PCI_MAX_LANE_WIDTH 32 + +#define PCI_MAX_FUNCTION 8 +#define PCI_INVALID_VENDORID 0xFFFF +#define PCI_INVALID_DEVICEID 0xFFFF +#define PCI_INVALID_SUBVENDORID 0xFFFF +#define PCI_INVALID_SUBDEVICEID 0xFFFF + +#define PCI_CLASS_BRIDGE_DEV 0x06 +#define PCI_SUBCLASS_BR_HOST 0x00 +#define PCI_MULTIFUNCTION 0x80 + +// From PCI Local Bus Specification, Revision 3.0 +// and PCI Express Base Specification 6.0 +// numbers in comments to right of values indicate +// the referenced section in the PCIE spec + + +#define CAP_ID_MASK 0xFF + +#define CAP_ID_NULL 0x00 // 7.9.28.1 +#define CAP_ID_PMI 0x01 // 7.5.2.1 +#define CAP_ID_AGP 0x02 +#define CAP_ID_VPD 0x03 // 7.9.18.1 +#define CAP_ID_SLOT_ID 0x04 +#define CAP_ID_MSI 0x05 // 7.7.1.1 +#define CAP_ID_HOT_SWAP 0x06 +#define CAP_ID_PCI_X 0x07 +#define CAP_ID_HYPER_TRANSPORT 0x08 +#define CAP_ID_VENDOR_SPECIFIC 0x09 +#define CAP_ID_DEBUG_PORT 0x0A +#define CAP_ID_CRC 0x0B +#define CAP_ID_HOT_PLUG 0x0C +#define CAP_ID_SUBSYSTEM_ID 0x0D // 7.9.23.1 +#define CAP_ID_AGP8X 0x0E +#define CAP_ID_SECURE 0x0F +#define CAP_ID_PCI_EXPRESS 0x10 // 7.5.3.1 +#define CAP_ID_MSI_X 0x11 // 7.7.2.1 +#define CAP_ID_ENHANCED_ALLOCATION 0x14 // 7.8.5.1 +#define CAP_ID_FPB 0x15 // 7.8.11.1 +#define CAP_ID_AF 0x13 // 7.9.21.1 + +// +// sizes for static PCI capabilities structure +// +#define CAP_NULL_SIZE 0x04 // 7.9.28 +#define CAP_PMI_SIZE 0x08 // 7.5.2 +#define CAP_VPD_SIZE 0x08 // 7.9.18 +#define CAP_PCI_X_SIZE 0x3C // 7.5.3 +#define CAP_PCI_EXPRESS_SIZE 0x3C // 7.5.3 +#define CAP_FPB_SIZE 0x08 // 7.8.11.1 +#define CAP_AF_SIZE 0x08 // 7.9.21 +#define CAP_SUBSYSTEM_ID_SIZE 0x08 // 7.9.23 + +// MSI capability size related fields +#define PCI_MSI_CONTROL 0x02 // 7.7.1.2 +#define PCI_MSI_CONTROL_64BIT_CAPABLE 7:7 +#define PCI_MSI_CONTROL_64BIT_CAPABLE_FALSE 0 +#define PCI_MSI_CONTROL_64BIT_CAPABLE_TRUE 1 +#define PCI_MSI_CONTROL_PVM_CAPABLE 8:8 +#define PCI_MSI_CONTROL_PVM_CAPABLE_FALSE 0 +#define PCI_MSI_CONTROL_PVM_CAPABLE_TRUE 1 +#define PCI_MSI_BASE_SIZE 0x0C // 7.7.1 +#define PCI_MSI_64BIT_ADDR_CAPABLE_ADJ_SIZE 0x04 // 7.7.1 +#define PCI_MSI_PVM_CAPABLE_ADJ_SIZE 0x08 // 7.7.1 + +// MSI-X capability size related fields +#define PCI_MSI_X_BASE_SIZE 0x0C // 7.7.2 +#define PCI_MSI_X_CONTROL 0x02 // 7.7.2.2 +#define PCI_MSI_X_CONTROL_TABLE_SIZE 10:0 +#define PCI_MSI_X_TABLE_OFFSET_BIR 0x04 // 7.7.2.3 +#define PCI_MSI_X_TABLE_OFFSET 31:3 +#define PCI_MSI_X_PBR_OFFSET_BIR 0x08 // 7.7.2.4 +#define PCI_MSI_X_PBR_OFFSET 31:3 +#define PCI_MSI_X_TABLE_ENTRY_SIZE 0x10 // 7.7.2 +#define PCI_MSI_X_PBR_ENTRY_SIZE 0x10 // 7.7.2 + +// Enhanced Allocation Capability size related fields +#define PCI_ENHANCED_ALLOCATION_FIRST_DW 0x00 // 7.8.5.1 +#define PCI_ENHANCED_ALLOCATION_FIRST_DW_NUM_ENTRIES 21:16 +#define PCI_ENHANCED_ALLOCATION_TYPE_0_BASE_SIZE 0x04 // 7.8.5.1 +#define PCI_ENHANCED_ALLOCATION_TYPE_1_BASE_SIZE 0x08 // 7.8.5.2 +#define PCI_ENHANCED_ALLOCATION_ENTRY_HEADER 0x00 // 7.8.5.3 +#define PCI_ENHANCED_ALLOCATION_ENTRY_HEADER_ENTRY_SIZE 2:0 + +// PCI Vendor Specific Capability size related fields +#define PCI_VENDOR_SPECIFIC_CAP_HEADER 0x00 // 7.9.4 +#define PCI_VENDOR_SPECIFIC_CAP_HEADER_LENGTH 23:16 + +// +// Extended config space size is 4096 bytes. +// +#define PCI_EXTENDED_CONFIG_SPACE_LENGTH 4096 + +// +// From PCI Local Bus Specification, Revision 3.0 +// HEADER TYPE0 Definitions - Byte offsets +// +#define PCI_HEADER_TYPE0_VENDOR_ID 0x00 +#define PCI_HEADER_TYPE0_DEVICE_ID 0x02 +#define PCI_HEADER_TYPE0_COMMAND 0x04 +#define PCI_HEADER_TYPE0_STATUS 0x06 +#define PCI_HEADER_TYPE0_REVISION_ID 0x08 +#define PCI_HEADER_TYPE0_PROGIF 0x09 +#define PCI_HEADER_TYPE0_SUBCLASS 0x0A +#define PCI_HEADER_TYPE0_BASECLASS 0x0B +#define PCI_HEADER_TYPE0_CACHE_LINE_SIZE 0x0C +#define PCI_HEADER_TYPE0_LATENCY_TIMER 0x0D +#define PCI_HEADER_TYPE0_HEADER_TYPE 0x0E +#define PCI_HEADER_TYPE0_HEADER_TYPE_0 0 +#define PCI_HEADER_TYPE0_HEADER_TYPE_1 1 +#define PCI_HEADER_TYPE0_BIST 0x0F +#define PCI_HEADER_TYPE0_BAR0 0x10 +#define PCI_HEADER_TYPE0_BAR1 0x14 +#define PCI_HEADER_TYPE0_BAR2 0x18 +#define PCI_HEADER_TYPE0_BAR3 0x1C +#define PCI_HEADER_TYPE0_BAR4 0x20 +#define PCI_HEADER_TYPE0_BAR5 0x24 +#define PCI_HEADER_TYPE0_CBCIS_PTR 0x28 +#define PCI_HEADER_TYPE0_SUBSYS_VEN_ID 0x2C +#define PCI_HEADER_TYPE0_SUBSYS_ID 0x2E +#define PCI_HEADER_TYPE0_ROMBAR 0x30 +#define PCI_HEADER_TYPE0_CAP_PTR 0x34 +#define PCI_HEADER_TYPE0_INT_LINE 0x3C +#define PCI_HEADER_TYPE0_INT_PIN 0x3D +#define PCI_HEADER_TYPE0_MIN_GNT 0x3E +#define PCI_HEADER_TYPE0_MAX_LAT 0x3F + +// +// From PCI Express Base Specification Revision 2.0 +// HEADER TYPE1 Definitions +#define PCI_HEADER_TYPE1_BRIDGE_CONTROL 0x3E +#define PCI_HEADER_TYPE1_BRIDGE_CONTROL_VGA_EN 0x08 + +#define PCIE_LINK_CAPABILITIES_2 0x000000A4 /* R--4R */ +#define PCIE_LINK_CAPABILITIES_2_RSVD 0:0 /* C--VF */ +#define PCIE_LINK_CAPABILITIES_2_RSVD_INIT 0x00000000 /* C---V */ +#define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED 7:1 /* R-EVF */ +#define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2_GEN3_GEN4_GEN5 0x0000001F /* R---V */ +#define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_HIDDEN 0x00000000 /* R---V */ +#define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1 0x00000001 /* R---V */ +#define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2 0x00000003 /* R---V */ +#define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2_GEN3 0x00000007 /* R-E-V */ +#define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2_GEN3_GEN4 0x0000000F /* R---V */ +#define PCIE_LINK_CAPABILITIES_2_CROSS_LINK_SUPPORT 8:8 /* C--VF */ +#define PCIE_LINK_CAPABILITIES_2_CROSS_LINK_SUPPORT_DISABLED 0x00000000 /* C---V */ +#define PCIE_LINK_CAPABILITIES_2_RET_PRESENCE_DET_SUPP 23:23 /* R-EVF */ +#define PCIE_LINK_CAPABILITIES_2_RET_PRESENCE_DET_SUPP_UNSET 0x00000000 /* R-E-V */ +#define PCIE_LINK_CAPABILITIES_2_2RET_PRESENCE_DET_SUPP 24:24 /* R-EVF */ +#define PCIE_LINK_CAPABILITIES_2_2RET_PRESENCE_DET_SUPP_UNSET 0x00000000 /* R-E-V */ +#define PCIE_LINK_CAPABILITIES_2_RSVD1 31:25 /* C--VF */ +#define PCIE_LINK_CAPABILITIES_2_RSVD1_INIT 0x00000000 /* C---V */ + +// +// PCI Express Virtual Peer-to-Peer Approval Definition +// +// These offsets are unused in hardware on existing chips and are reserved on +// future chips. Software has defined a virtual PCI capability that may be +// emulated by hypervisors at these offsets, and this capability is not tied +// to any specific hardware. +// +// +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0 0x000000C8 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_ID 7:0 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_NEXT 15:8 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_LENGTH 23:16 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_SIG_LO 31:24 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1 0x000000CC +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_SIG_HI 15:0 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_VERSION 18:16 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_PEER_CLIQUE_ID 22:19 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RSVD 31:23 + +#define NV_PCI_VIRTUAL_P2P_APPROVAL_SIGNATURE 0x00503250 + +// Chipset-specific definitions. +// Intel SantaRosa definitions +#define INTEL_2A00_CONFIG_SPACE_BASE 0x60 + +// Intel Montevina definitions +#define INTEL_2A40_CONFIG_SPACE_BASE 0x60 +#define INTEL_2A40_ASLM_CAPABLE_REVID 0x05 + +// Intel EagleLake definitions +#define INTEL_2E00_CONFIG_SPACE_BASE 0x60 + +// Intel Bearlake definitions +#define INTEL_29XX_CONFIG_SPACE_BASE 0x60 + +// Intel BroadWater definitions +#define INTEL_29A0_CONFIG_SPACE_BASE 0x60 + +// Intel Grantsdale definitions +#define INTEL_25XX_CONFIG_SPACE_BASE 0x48 + +// Intel Tumwater definitions +#define INTEL_359E_CONFIG_SPACE_BASE 0xCC + +// Intel Greencreek definitions +#define INTEL_25E0_CONFIG_SPACE_BASE_ADDRESS 0xE0000000 + +// Intel Stoakley definitions +#define INTEL_4000_CONFIG_SPACE_BASE_ADDRESS 0xE0000000 + +// Intel SkullTrail definitions +#define INTEL_4003_CONFIG_SPACE_BASE_ADDRESS_F 0xF0000000 +#define INTEL_4003_CONFIG_SPACE_BASE_ADDRESS_E 0xE0000000 +#define INTEL_4003_CONFIG_SPACE_BASE_ADDRESS INTEL_4003_CONFIG_SPACE_BASE_ADDRESS_F +#define INTEL_4003_CONFIG_SPACE_BASE 0x64 + +// SiS 656 +#define SIS_656_CONFIG_SPACE_BASE 0xE0 +#define SIS_656_CONFIG_SPACE_BASE_ADDRESS 3:0 // mapped to 31:28 + +// PCI/PCIE definitions +#define PCI_MAX_CAPS 20 // max caps to parse +#define PCI_MAX_DEVICES 32 // max devices on bus +#define PCI_MAX_FUNCTIONS 8 // max functions for a device +#define PCI_CAP_HEADER_ID 7:0 // PCI cap header id +#define PCI_CAP_HEADER_NEXT 15:8 // PCI cap header next +#define PCI_COMMON_CLASS_SUBCLASS 0x0a // PCI class/subclass (word) +#define PCI_COMMON_CLASS_SUBBASECLASS_HOST 0x0600 // Host bridge (connect PCI to CPU) [00] + Bridge Device [06] +#define PCI_COMMON_CLASS_SUBBASECLASS_P2P 0x0604 // PCI-to-PCI bridge (connects PCI buses) [04] + Bridge Device [06] +#define PCI_COMMON_CLASS_SUBBASECLASS_VGA 0x0300 +#define PCI_COMMON_CLASS_SUBBASECLASS_3DCTRL 0x0302 +#define PCI_COMMON_CAP_PTR 0x34 // PCI common cap ptr (byte) +#define PCI_TYPE_1_SECONDARY_BUS_NUMBER 0x19 // PCI type 1 sec bus (byte) +#define PCI_TYPE_1_SUBORDINATE_BUS_NUMBER 0x1a // PCI type 1 sub bus (byte) +#define PCIE_CAP_HEADER_ID 15:0 // PCIE cap header id +#define PCIE_CAP_HEADER_ID_INVALID 0xffff +#define PCIE_CAP_HEADER_NEXT 31:20 // PCIE cap header next +#define PCIE_BUS_SHIFT 20 // PCIE cfg space bus shift +#define PCIE_DEVICE_SHIFT 15 // PCIE cfg space dev shift +#define PCIE_FUNC_SHIFT 12 // PCIE cfg space func shift +#define PCIE_CAP_VERSION 19:16 // PCIE cap version +#define PCIE_CAP_VERSION_2P0 2 // PCIE 2.0 version +#define PCIE_LINK_CNTRL_STATUS_2_OFFSET 0x30 // PCIE Link Control/Status 2 offset +#define PCIE_LINK_STATUS_2 31:16 // PCIE Link Status 2 Register +#define PCIE_LINK_STATUS_2_DE_EMPHASIS 0:0 // PCIE De-Emphasis Level +#define PCI_COMMON_SUBSYSTEM_VENDOR_ID 0x2c // PCI subsystem Vendor Id +#define PCI_COMMON_SUBSYSTEM_ID 0x2e // PCI subsystem Id +#define PCIE_CAPABILITY_BASE 0x100 // 1st PCIE capability. + +// PCI Express Capability ID in the enhanced configuration space +#define PCIE_CAP_ID_NULL 0x00 // 7.9.28.1 +#define PCIE_CAP_ID_ERROR 0x01 // 7.8.4.1 +#define PCIE_CAP_ID_VC 0x02 // 7.9.1.1 +#define PCIE_CAP_ID_SERIAL 0x03 // 7.9.3.1 +#define PCIE_CAP_ID_POWER 0x04 // 7.8.1.1 +#define PCIE_CAP_ID_ROOT_COMPLEX 0x05 // 7.9.8.1 +#define PCIE_CAP_ID_ROOT_COMPLEX_INTERNAL_LINK_CTRL 0x06 // 7.9.9.1 +#define PCIE_CAP_ID_ROOT_COMPLEX_EVENT_COLLECTOR_ENDPOINT 0x07 // 7.9.10.1 +#define PCIE_CAP_ID_PCIE_CAP_ID_MFVC 0x08 // 7.9.2.1 +#define PCIE_CAP_ID_RCRB 0x0A // 7.9.7.1 +#define PCIE_CAP_ID_ACS 0x0D // 7.7.11.1 +#define PCIE_CAP_ID_ARI 0x0E // 7.8.8.1 +#define PCIE_CAP_ID_MULTICAST 0x12 // 7.9.11.1 +#define PCIE_CAP_ID_RESIZABLE_BAR 0x15 // 7.8.6.1 +#define PCIE_CAP_ID_DYNAMIC_POWER_ALLOCATION 0x16 // 7.9.12.1 +#define PCIE_CAP_ID_TPH 0x17 // 7.9.13.1 +#define PCIE_CAP_ID_LATENCY_TOLERANCE 0x18 // 7.8.2.1 +#define PCIE_CAP_ID_SECONDARY_PCIE_CAPABILITY 0x19 // 7.7.3.1 +#define PCIE_CAP_ID_PASID 0x1B // 7.8.9.1 +#define PCIE_CAP_ID_DPC 0x1D // 7.9.14.1 +#define PCIE_CAP_ID_L1_PM_SUBSTATES 0x1E // 7.8.3.1 +#define PCIE_CAP_ID_PTM 0x1F // 7.9.15.1 +#define PCIE_CAP_ID_FRS_QUEUING 0x21 // 7.8.10.1 +#define PCIE_CAP_ID_READINESS_TIME_REPORTING 0x22 // 7.9.16.1 +#define PCIE_CAP_ID_VENDOR_SPECIFIC 0x23 // 7.9.6.1 +#define PCIE_CAP_ID_VF_RESIZABLE_BAR 0x24 // 7.8.7.1 +#define PCIE_CAP_ID_DATA_LINK 0x25 // 7.7.4.1 +#define PCIE_CAP_ID_PHYSLAYER_16_GT 0x26 // 7.7.5.1 +#define PCIE_CAP_ID_LANE_MARGINING_AT_RECEVER 0x27 // 7.7.10.1 +#define PCIE_CAP_ID_HIERARCHY_ID 0x28 // 7.9.17.1 +#define PCIE_CAP_ID_NPEM 0x29 // 7.9.19.1 +#define PCIE_CAP_ID_PHYSLAYER_32_GT 0x2A // 7.7.6.1 +#define PCIE_CAP_ID_ALTERNATE_PROTOCOL 0x2B // 7.9.20.1 +#define PCIE_CAP_ID_SFI 0x2C // 7.9.22.1 +#define PCIE_CAP_ID_SHADOW_FUNCTIONS 0x2D // 7.9.25.1 +#define PCIE_CAP_ID_DATA_OBJECT_EXCHANGE 0x2E // 7.9.24.1 +#define PCIE_CAP_ID_DEVICE_3 0x2F // 7.7.9.1 +#define PCIE_CAP_ID_IDE 0x30 // 7.9.26.1 +#define PCIE_CAP_ID_PHYSLAYER_64_GT 0x31 // 7.7.7.1 +#define PCIE_CAP_ID_FLT_LOGGING 0x32 // 7.7.8.1 +#define PCIE_CAP_ID_FLIT_PERF_MEASURMENT 0x33 // 7.8.12.1 +#define PCIE_CAP_ID_FLIT_ERROR_INJECTION 0x34 // 7.8.13.1 + +// static sized structure sizes +#define PCIE_CAP_HEADER_SIZE 0x04 // 7.6.3 +#define PCIE_CAP_NULL_SIZE 0x04 // 7.9.28 +#define PCIE_CAP_ERROR_SIZE 0x48 // 7.8.4 +#define PCIE_CAP_POWER_SIZE 0x10 // 7.8.1 +#define PCIE_CAP_ROOT_COMPLEX_INTERNAL_LINK_CTRL_SIZE 0x0C // 7.9.9 +#define PCIE_CAP_ROOT_COMPLEX_EVENT_COLLECTOR_ENDPOINT_SIZE 0x0C // 7.9.10 +#define PCIE_CAP_SECONDARY_PCIE_SIZE 0x4C // 7.7.3.1 +#define PCIE_CAP_DATA_LINK_SIZE 0x0C // 7.7.4 +#define PCIE_CAP_PHYSLAYER_16_GT_SIZE 0x40 // 7.7.5 +#define PCIE_CAP_PHYSLAYER_32_GT_SIZE 0x40 // 7.7.6 +#define PCIE_CAP_PHYSLAYER_64_GT_SIZE 0x20 // 7.7.7 +#define PCIE_CAP_FLT_LOGGING_SIZE 0x3C // 7.7.8 +#define PCIE_CAP_DEVICE_3_SIZE 0x10 // 7.7.9 +#define PCIE_CAP_LANE_MARGINING_AT_RECEVER_SIZE 0x88 // 7.7.10 +#define PCIE_CAP_ACS_SIZE 0x10 // 7.7.11 +#define PCIE_CAP_LATENCY_TOLERANCE_SIZE 0x08 // 7.8.2 +#define PCIE_CAP_L1_PM_SUBSTATE_SIZE 0x14 // 7.8.3 +#define PCIE_CAP_RESIZABLE_BAR_SIZE 0x34 // 7.8.6 +#define PCIE_CAP_VF_RESIZABLE_BAR_SIZE 0x34 // 7.8.7 +#define PCIE_CAP_ARI_SIZE 0x08 // 7.8.8 +#define PCIE_CAP_PASID_SIZE 0x08 // 7.8.9 +#define PCIE_CAP_FRS_QUEUING_SIZE 0x10 // 7.8.10 +#define PCIE_CAP_FPB_SIZE 0x24 // 7.8.11 +#define PCIE_CAP_FLIT_PERF_MEASURMENT_SIZE 0x24 // 7.8.12 +#define PCIE_CAP_FLIT_ERROR_INJECTION_SIZE 0x24 // 7.8.13 +#define PCIE_CAP_DEV_SERIAL_SIZE 0x0C // 7.9.3 +#define PCIE_CAP_RCRB_SIZE 0x14 // 7.9.7 +#define PCIE_CAP_MULTICAST_SIZE 0x30 // 7.9.11 +#define PCIE_CAP_DYNAMIC_POWER_ALLOCATION_SIZE 0x30 // 7.9.12 +#define PCIE_CAP_DPC_SIZE 0x5C // 7.9.14 +#define PCIE_CAP_PTM_SIZE 0x0C // 7.9.15 +#define PCIE_CAP_READINESS_TIME_REPORTING_SIZE 0x0C // 7.9.16 +#define PCIE_CAP_HIERARCHY_ID_SIZE 0x0C // 7.9.17 +#define PCIE_CAP_NPEM_SIZE 0x10 // 7.9.19 +#define PCIE_CAP_ALTERNATE_PROTOCOL_SIZE 0x14 // 7.9.20 +#define PCIE_CAP_SFI_SIZE 0x14 // 7.9.22 +#define PCIE_CAP_DATA_OBJECT_EXCHANGE_SIZE 0x18 // 7.9.24 +#define PCIE_CAP_SHADOW_FUNCTIONS_SIZE 0x1C // 7.9.25 +#define PCIE_CAP_IDE_SIZE 0x34 // 7.9.26 + +// Virtual Channel Capability size related fields +#define PCIE_VC_REGISTER_1 0x04 // 7.9.1.2 +#define PCIE_VC_REGISTER_1_EXTENDED_VC_COUNT 2:0 +#define PCIE_VIRTUAL_CHANNELS_BASE_SIZE 0x18 // 7.9.1 +#define PCIE_VIRTUAL_CHANNELS_EXTENDED_VC_ENTRY_SIZE 0x10 // 7.9.1 + +// Multi Function Virtual Channel Capability size related fields +#define PCIE_MFVC_REGISTER_1 0x04 // 7.9.2.2 +#define PCIE_MFVC_REGISTER_1_EXTENDED_VC_COUNT 2:0 +#define PCIE_PCIE_CAP_ID_MFVC_BASE_SIZE 0x18 // 7.9.2 +#define PCIE_PCIE_CAP_ID_MFVC_EXTENDED_VC_ENTRY_SIZE 0x10 // 7.9.2 + +// Vendor Specific Capability size related fields +#define PCIE_VENDOR_SPECIFIC_HEADER_1 0x04 // 7.9.6.2 +#define PCIE_VENDOR_SPECIFIC_HEADER_1_LENGTH 31:20 + +// Root Complex Capability size related fields +#define PCIE_ROOT_COMPLEX_SELF_DESC_REGISTER 0x04 // 7.9.8.2 +#define PCIE_ROOT_COMPLEX_SELF_DESC_REGISTER_NUM_LINK_ENTRIES 15:8 +#define PCIE_ROOT_COMPLEX_BASE_SIZE 0x0C // 7.9.8 +#define PCIE_ROOT_COMPLEX_LINK_ENTRY_SIZE 0x10 // 7.9.8.3 + +// TPH capability size related fields +#define PCIE_TPH_REQUESTOR_REGISTER 0x04 // 7.9.13.2 +#define PCIE_TPH_REQUESTOR_REGISTER_ST_TABLE_SIZE 26:16 +#define PCIE_TPH_BASE_SIZE 0x0C // 7.9.13 +#define PCIE_TPH_ST_ENTRY_SIZE 0x02 // 7.9.13.4 + +// Intel CPU family. +#define INTEL_CPU_FAMILY_06 0x06 +#define INTEL_CPU_FAMILY_15 0x0f +#define INTEL_CPU_FAMILY_16 0x10 +#define INTEL_CPU_FAMILY_21 0x15 + +// Intel CPU Model. Calculated as Model += (extModel << 4). +#define INTEL_CPU_MODEL_2A 0x2a +#define INTEL_CPU_MODEL_2D 0x2d +#define INTEL_CPU_MODEL_3A 0x3a +#define INTEL_CPU_MODEL_3F 0x3f + +// Symbolic defines for each possible virtual channel +enum +{ + RM_PCIE_VIRTUAL_CHANNEL_0 = 0, + RM_PCIE_VIRTUAL_CHANNEL_1, + RM_PCIE_VIRTUAL_CHANNEL_2, + RM_PCIE_VIRTUAL_CHANNEL_3, + RM_PCIE_VIRTUAL_CHANNEL_4, + RM_PCIE_VIRTUAL_CHANNEL_5, + RM_PCIE_VIRTUAL_CHANNEL_6, + RM_PCIE_VIRTUAL_CHANNEL_7, + RM_PCIE_VIRTUAL_CHANNEL_INVALID +}; + +// Diagnostic collection actions. +#define RM_PCIE_ACTION_NOP 0 +#define RM_PCIE_ACTION_COLLECT_CONFIG_SPACE 1 +#define RM_PCIE_ACTION_COLLECT_PCI_CAP_STRUCT 2 +#define RM_PCIE_ACTION_COLLECT_PCIE_CAP_STRUCT 3 +#define RM_PCIE_ACTION_COLLECT_ALL_PCI_CAPS 4 +#define RM_PCIE_ACTION_COLLECT_ALL_PCIE_CAPS 5 +#define RM_PCIE_ACTION_REPORT_PCI_CAPS_COUNT 6 +#define RM_PCIE_ACTION_REPORT_PCIE_CAPS_COUNT 7 +#define RM_PCIE_ACTION_EOS 0xff + + +// Diagnostic collection device Type ids +#define RM_PCIE_DEVICE_TYPE_NONE 0xff +#define RM_PCIE_DEVICE_TYPE_GPU 0 +#define RM_PCIE_DEVICE_TYPE_UPSTREAM_BRIDGE 1 +#define RM_PCIE_DEVICE_COUNT 2 + +// Diagnostic collection capability Type ids +#define RM_PCIE_DC_CAP_TYPE_NONE 0xff +#define RM_PCIE_DC_CAP_TYPE_PCI 0 +#define RM_PCIE_DC_CAP_TYPE_PCIE 1 +#define RM_PCIE_DC_CAP_TYPE_COUNT 2 + +typedef struct _def_bif_dc_diagnostic_collection_command +{ + NvU8 action; + NvU8 deviceType; + NvU16 locator; + NvU16 length; +} CL_PCIE_DC_DIAGNOSTIC_COLLECTION_ENTRY; + +typedef struct _def_cl_pcie_dc_capability_map_entry +{ + NvU16 id; + NvU16 blkOffset; +} CL_PCIE_DC_CAPABILITY_MAP_ENTRY; +typedef struct +{ + NvU16 count; + CL_PCIE_DC_CAPABILITY_MAP_ENTRY entries[PCI_MAX_CAPS]; +} CL_PCIE_DC_CAPABILITY_MAP; + +struct OBJCL; +// root port setup functions +NV_STATUS Broadcom_HT2100_setupFunc(OBJGPU *, OBJCL*); + +NV_STATUS Intel_RP25XX_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS Intel_RP81XX_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS Intel_RP3C0X_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS Intel_RP2F0X_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS Intel_RP0C0X_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS Intel_Broadwell_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS Intel_Skylake_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS Intel_Skylake_U_Pch_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS Intel_Skylake_H_Pch_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS Intel_Kabylake_Y_setupFunc(OBJGPU *, OBJCL*); + +NV_STATUS Nvidia_RPC19_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS Nvidia_RPC51_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS Nvidia_RPC55_setupFunc(OBJGPU *, OBJCL*); + +NV_STATUS AMD_RP1480_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS AMD_RP1630_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS AMD_RP1483_setupFunc(OBJGPU *, OBJCL*); + +// Determines if the GPU is in a multi-GPU board based on devid checks +NvBool gpuIsMultiGpuBoard(OBJGPU *, NvBool *); + +#endif // NVPCIE_H diff --git a/userspace/sdks/nv525/nvalloc/common/inc/nvrangetypes.h b/userspace/sdks/nv525/nvalloc/common/inc/nvrangetypes.h new file mode 100644 index 0000000..1ff7df6 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/nvrangetypes.h @@ -0,0 +1,162 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file nvrangetypes.h + * @brief Range types and operator macros + * @note #include a header to define NvUxx and NvSxx before sourcing this file. + */ + +#ifndef _NVRANGETYPES_H_ +#define _NVRANGETYPES_H_ + + +// +// Define range types by convention +// +#define __NV_DEFINE_RANGE_TYPE(T) \ +typedef struct NvRange ## T \ +{ \ + Nv ## T min; \ + Nv ## T max; \ +} NvRange ## T; + + +__NV_DEFINE_RANGE_TYPE(U64) // NvRangeU64 +__NV_DEFINE_RANGE_TYPE(S64) // NvRangeS64 +__NV_DEFINE_RANGE_TYPE(U32) // NvRangeU32 +__NV_DEFINE_RANGE_TYPE(S32) // NvRangeS32 +__NV_DEFINE_RANGE_TYPE(U16) // NvRangeU16 +__NV_DEFINE_RANGE_TYPE(S16) // NvRangeS16 +__NV_DEFINE_RANGE_TYPE(U8) // NvRangeU8 +__NV_DEFINE_RANGE_TYPE(S8) // NvRangeS8 + + +// +// Operator macros +// +// Macros are named xxx_RANGE (rather than xxx_RANGEU32, etc.) since they work +// properly on ranges with any number of bits, signed or unsigned. +// + +#define NV_EQUAL_RANGE(r1, r2) ((r1).min == (r2).min && (r1).max == (r2).max) +#define NV_EMPTY_INCLUSIVE_RANGE(r) ((r).min > (r).max) +#define NV_EMPTY_EXCLUSIVE_RANGE(r) ((r).min + 1 > (r).max - 1) +#define NV_WITHIN_INCLUSIVE_RANGE(r, x) ((r).min <= (x) && (x) <= (r).max) +#define NV_WITHIN_EXCLUSIVE_RANGE(r, x) ((r).min < (x) && (x) < (r).max) +#define NV_IS_SUBSET_RANGE(r1, r2) ((r1).min >= (r2).min && (r2).max >= (r1).max) +#define NV_IS_SUPERSET_RANGE(r1, r2) ((r1).min <= (r2).min && (r2).max <= (r1).max) +#define NV_CENTER_OF_RANGE(r) ((r).min / 2 + ((r).max + 1) / 2) // Avoid overflow and rounding anomalies. +#define NV_IS_OVERLAPPING_RANGE(r1, r2) \ + (NV_WITHIN_INCLUSIVE_RANGE((r1), (r2).min) || \ + NV_WITHIN_INCLUSIVE_RANGE((r1), (r2).max)) + +#define NV_DISTANCE_FROM_RANGE(r, x) ((x) < (r).min? (r).min - (x): ((x) > (r).max? (x) - (r).max: 0)) +#define NV_VALUE_WITHIN_INCLUSIVE_RANGE(r, x) ((x) < (r).min? (r).min : ((x) > (r).max? (r).max : (x))) +#define NV_VALUE_WITHIN_EXCLUSIVE_RANGE(r, x) ((x) <= (r).min? (r).min + 1 : ((x) >= (r).max? (r).max - 1 : (x))) + +#define NV_INIT_RANGE(r, x, y) \ +do \ +{ \ + (r).min = (x); \ + (r).max = (y); \ +} while(0) + +#define NV_ASSIGN_DELTA_RANGE(r, x, d) \ +do \ +{ \ + (r).min = (x) - (d); \ + (r).max = (x) + (d); \ +} while(0) + +#define NV_ASSIGN_INTERSECTION_RANGE(r1, r2) \ +do \ +{ \ + if ((r1).min < (r2).min) \ + (r1).min = (r2).min; \ + if ((r1).max > (r2).max) \ + (r1).max = (r2).max; \ +} while(0) + +#define NV_ASSIGN_UNION_RANGE(r1, r2) \ +do \ +{ \ + if ((r1).min > (r2).min) \ + (r1).min = (r2).min; \ + if ((r1).max < (r2).max) \ + (r1).max = (r2).max; \ +} while(0) + +#define NV_MULTIPLY_RANGE(r, x) \ +do \ +{ \ + (r).min *= (x); \ + (r).max *= (x); \ +} while(0) + +#define NV_DIVIDE_FLOOR_RANGE(r, x) \ +do \ +{ \ + (r).min /= (x); \ + (r).max /= (x); \ +} while(0) + +#define NV_DIVIDE_CEILING_RANGE(r, x) \ +do \ +{ \ + (r).min = ((r).min + (x) - 1) / (x); \ + (r).max = ((r).max + (x) - 1) / (x); \ +} while(0) + +#define NV_DIVIDE_ROUND_RANGE(r, x) \ +do \ +{ \ + (r).min = ((r).min + (x) / 2) / (x); \ + (r).max = ((r).max + (x) / 2) / (x); \ +} while(0) + +#define NV_DIVIDE_WIDE_RANGE(r, x) \ +do \ +{ \ + (r).min /= (x); \ + (r).max = ((r).max + (x) - 1) / (x); \ +} while(0) + +#define NV_DIVIDE_NARROW_RANGE(r, x) \ +do \ +{ \ + (r).min = ((r).min + (x) - 1) / (x); \ + (r).max /= (x); \ +} while(0) + +#define NV_VALUE_WITHIN_INCLUSIVE_RANGE(r, x) \ + ((x) < (r).min? (r).min : ((x) > (r).max? (r).max : (x))) + +#define NV_WITHIN_INCLUSIVE_RANGE(r, x) \ + ((r).min <= (x) && (x) <= (r).max) + +#define NV_DISTANCE_FROM_RANGE(r, x) \ + ((x) < (r).min? (r).min - (x): ((x) > (r).max? (x) - (r).max: 0)) + +#endif // _NVRANGETYPES_H_ + diff --git a/userspace/sdks/nv525/nvalloc/common/inc/oob/smbpbi.h b/userspace/sdks/nv525/nvalloc/common/inc/oob/smbpbi.h new file mode 100644 index 0000000..e5b17a0 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/oob/smbpbi.h @@ -0,0 +1,2684 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _SMBPBI_H +#define _SMBPBI_H + +#include "oob/smbpbi_impl.h" + +/*! + * This file contains definitions for SMBPBI - SMBUS Out-Of-Band (OOB) interface + */ +/*! + * NV_MSGBOX_CMD() macro below and its derivatives depend on DRF_DEF() and DRF_NUM() + * macros, that are defined in "nvdrf.h" header file, which is a part of + * smbus/msgbox SDK. That file needs to be #included before this (smbpbi.h) + * header file. + */ + +/******************************************************************************** + * * + * GPU COMMANDS * + * * + ********************************************************************************/ + +// +// Encoding: +// 30 29 23 16 15 8 7 0 +// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-. +// |I|C|R| STATUS | ARG2 | ARG1 | OPCODE | COMMAND +// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' +// 31 28 24 +// + +#define NV_MSGBOX_CMD_OPCODE 7:0 +#define NV_MSGBOX_CMD_OPCODE_NULL_CMD 0x00000000 +#define NV_MSGBOX_CMD_OPCODE_GET_CAP_DWORD 0x00000001 +#define NV_MSGBOX_CMD_OPCODE_GET_TEMP 0x00000002 +#define NV_MSGBOX_CMD_OPCODE_GET_EXT_TEMP 0x00000003 /* With 8 fractional bits! */ +#define NV_MSGBOX_CMD_OPCODE_GET_POWER 0x00000004 +#define NV_MSGBOX_CMD_OPCODE_GET_SYS_ID_DATA 0x00000005 +#define NV_MSGBOX_CMD_OPCODE_GET_ECC_V1 0x00000006 +#define NV_MSGBOX_CMD_OPCODE_GET_ECC_V2 0x00000007 +#define NV_MSGBOX_CMD_OPCODE_GPU_PCONTROL 0x00000008 +#define NV_MSGBOX_CMD_OPCODE_GPU_SYSCONTROL 0x00000009 +#define NV_MSGBOX_CMD_OPCODE_SET_MASTER_CAPS 0x0000000a +#define NV_MSGBOX_CMD_OPCODE_SET_PRIMARY_CAPS 0x0000000a // Duplicate value till bug 3190552 is addressed. +#define NV_MSGBOX_CMD_OPCODE_GPU_REQUEST_CPL 0x0000000b +#define NV_MSGBOX_CMD_OPCODE_GET_ECC_V3 0x0000000c +#define NV_MSGBOX_CMD_OPCODE_SCRATCH_READ 0x0000000d +#define NV_MSGBOX_CMD_OPCODE_SCRATCH_WRITE 0x0000000e +#define NV_MSGBOX_CMD_OPCODE_SCRATCH_COPY 0x0000000f +#define NV_MSGBOX_CMD_OPCODE_ASYNC_REQUEST 0x00000010 +#define NV_MSGBOX_CMD_OPCODE_REGISTER_ACCESS 0x00000011 +#define NV_MSGBOX_CMD_OPCODE_GET_POWER_CONNECTOR_STATE 0x00000012 +#define NV_MSGBOX_CMD_OPCODE_GET_PAGE_RETIREMENT_STATS 0x00000013 +#define NV_MSGBOX_CMD_OPCODE_GET_ECC_V4 0x00000014 +#define NV_MSGBOX_CMD_OPCODE_GET_THERM_PARAM 0x00000015 +#define NV_MSGBOX_CMD_OPCODE_GET_ECC_V5 0x00000016 +#define NV_MSGBOX_CMD_OPCODE_ACCESS_WP_MODE 0x00000017 + +// +// TODO: Get rid of MISC_GPU_FLAGS once all SMBPBI implementations have made +// the switch to MISC_DEVICE_FLAGS. +// +#define NV_MSGBOX_CMD_OPCODE_GET_MISC_GPU_FLAGS 0x00000018 +#define NV_MSGBOX_CMD_OPCODE_GET_MISC_DEVICE_FLAGS 0x00000018 +#define NV_MSGBOX_CMD_OPCODE_GPU_UTIL_COUNTERS 0x00000019 +#define NV_MSGBOX_CMD_OPCODE_GET_NVLINK_INFO 0x0000001a +#define NV_MSGBOX_CMD_OPCODE_GET_CLOCK_FREQ_INFO 0x0000001b +#define NV_MSGBOX_CMD_OPCODE_BUNDLE_LAUNCH 0x0000001c +#define NV_MSGBOX_CMD_OPCODE_GET_DRIVER_EVENT_MSG 0x0000001d +#define NV_MSGBOX_CMD_OPCODE_GET_ECC_V6 0x0000001e +#define NV_MSGBOX_CMD_OPCODE_REMAP_ROW_STATS 0x00000020 +#define NV_MSGBOX_CMD_OPCODE_GET_PCIE_LINK_INFO 0x00000021 +#define NV_MSGBOX_CMD_OPCODE_GET_ENERGY_COUNTER 0x00000022 +#define NV_MSGBOX_CMD_OPCODE_RESERVED_0 0x00000024 +#define NV_MSGBOX_CMD_OPCODE_RESERVED_1 0x00000025 +#define NV_MSGBOX_CMD_OPCODE_GET_POWER_HINT_INFO 0x00000026 +#define NV_MSGBOX_CMD_OPCODE_DYNAMIC_SYSTEM_INFORMATION 0x00000027 +#define NV_MSGBOX_CMD_OPCODE_GPU_PERFORMANCE_MONITORING 0x00000028 + +#define NV_MSGBOX_CMD_ARG1 15:8 +#define NV_MSGBOX_CMD_ARG1_NULL 0x00000000 +#define NV_MSGBOX_CMD_ARG1_TEMP_GPU_0 0x00000000 +#define NV_MSGBOX_CMD_ARG1_TEMP_NVSWITCH_0 0x00000000 +#define NV_MSGBOX_CMD_ARG1_TEMP_GPU_1 0x00000001 /* For Gemini boards */ +#define NV_MSGBOX_CMD_ARG1_TEMP_BOARD 0x00000004 +#define NV_MSGBOX_CMD_ARG1_TEMP_MEMORY 0x00000005 +#define NV_MSGBOX_CMD_ARG1_TEMP_PWR_SUPPLY 0x00000006 +#define NV_MSGBOX_CMD_ARG1_TEMP_T_LIMIT 0x00000007 +#define NV_MSGBOX_CMD_ARG1_TEMP_NUM_SENSORS 8 +#define NV_MSGBOX_CMD_ARG1_POWER_TOTAL 0x00000000 +#define NV_MSGBOX_CMD_ARG1_SMBPBI_POWER 0x00000001 +/* SysId info type encodings for opcode NV_MSGBOX_CMD_OPCODE_GET_SYS_ID_DATA (0x05) */ +#define NV_MSGBOX_CMD_ARG1_BOARD_PART_NUM_V1 0x00000000 +#define NV_MSGBOX_CMD_ARG1_OEM_INFO_V1 0x00000001 +#define NV_MSGBOX_CMD_ARG1_SERIAL_NUM_V1 0x00000002 +#define NV_MSGBOX_CMD_ARG1_MARKETING_NAME_V1 0x00000003 +#define NV_MSGBOX_CMD_ARG1_GPU_PART_NUM_V1 0x00000004 +#define NV_MSGBOX_CMD_ARG1_MEMORY_VENDOR_V1 0x00000005 +#define NV_MSGBOX_CMD_ARG1_MEMORY_PART_NUM_V1 0x00000006 +#define NV_MSGBOX_CMD_ARG1_BUILD_DATE_V1 0x00000007 +#define NV_MSGBOX_CMD_ARG1_FIRMWARE_VER_V1 0x00000008 +#define NV_MSGBOX_CMD_ARG1_VENDOR_ID_V1 0x00000009 +#define NV_MSGBOX_CMD_ARG1_DEV_ID_V1 0x0000000a +#define NV_MSGBOX_CMD_ARG1_SUB_VENDOR_ID_V1 0x0000000b +#define NV_MSGBOX_CMD_ARG1_SUB_ID_V1 0x0000000c +#define NV_MSGBOX_CMD_ARG1_GPU_GUID_V1 0x0000000d +#define NV_MSGBOX_CMD_ARG1_INFOROM_VER_V1 0x0000000e +#define NV_MSGBOX_CMD_ARG1_PRODUCT_LENGTH_V1 0x0000000f +#define NV_MSGBOX_CMD_ARG1_PRODUCT_WIDTH_V1 0x00000010 +#define NV_MSGBOX_CMD_ARG1_PRODUCT_HEIGHT_V1 0x00000011 +#define NV_MSGBOX_CMD_ARG1_PCIE_SPEED_V1 0x00000012 +#define NV_MSGBOX_CMD_ARG1_PCIE_WIDTH_V1 0x00000013 +#define NV_MSGBOX_CMD_ARG1_TGP_LIMIT_V1 0x00000014 +#define NV_MSGBOX_CMD_ARG1_SYS_ID_DATA_TYPE_MAX 0x00000014 /* Adjust, when adding new types */ +#define NV_MSGBOX_CMD_ARG1_REGISTER_ACCESS_WRITE 0x00000000 +#define NV_MSGBOX_CMD_ARG1_REGISTER_ACCESS_READ 0x00000001 +#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_TARGET 0x00000000 +#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_HW_SLOWDN 0x00000001 +#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_SHUTDN 0x00000002 +#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_HBM_SLOWDN 0x00000003 +#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_SW_SLOWDN 0x00000004 +#define NV_MSGBOX_CMD_ARG1_GET_MISC_ECC_ENABLED_STATE 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GET_MISC_GPU_RESET_REQUIRED 0x00000001 +#define NV_MSGBOX_CMD_ARG1_GET_MISC_GPU_FLAGS_PAGE_0 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GET_MISC_GPU_FLAGS_PAGE_1 0x00000001 +#define NV_MSGBOX_CMD_ARG1_GET_MISC_DEVICE_FLAGS_PAGE_0 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GET_MISC_DEVICE_FLAGS_PAGE_1 0x00000001 + +#define NV_MSGBOX_CMD_ARG1_GPU_UTIL_COUNTERS_CONTEXT_TIME 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GPU_UTIL_COUNTERS_SM_TIME 0x00000001 +#define NV_MSGBOX_CMD_ARG1_GPU_UTIL_COUNTERS_RESET_COUNTERS 0x000000FF +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_LINK_COUNT 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_LINK_STATE_V1 0x00000001 +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_LINK_BANDWIDTH 0x00000002 +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_ERR_COUNTER_REPLAY 0x00000003 +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_ERR_COUNTER_RECOVERY 0x00000004 +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_ERR_COUNTER_FLIT_CRC 0x00000005 +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_ERR_COUNTER_DATA_CRC 0x00000006 +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_LINK_STATE_V2 0x00000007 +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_SUBLINK_WIDTH 0x00000008 +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_THROUGHPUT_DATA_TX 0x00000009 +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_THROUGHPUT_DATA_RX 0x0000000a +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_THROUGHPUT_RAW_TX 0x0000000b +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_THROUGHPUT_RAW_RX 0x0000000c +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_TRAINING_ERROR_STATE 0x0000000d +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_RUNTIME_ERROR_STATE 0x0000000e +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_AVAILABILITY 0x0000000f +#define NV_MSGBOX_CMD_ARG1_GET_CLOCK_FREQ_INFO_CURRENT 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GET_CLOCK_FREQ_INFO_MIN 0x00000001 +#define NV_MSGBOX_CMD_ARG1_GET_CLOCK_FREQ_INFO_MAX 0x00000002 +#define NV_MSGBOX_CMD_ARG1_GET_CLOCK_FREQ_INFO_PAGE_3 0x00000003 +#define NV_MSGBOX_CMD_ARG1_REMAP_ROWS_RAW_COUNTS 0x00000000 +#define NV_MSGBOX_CMD_ARG1_REMAP_ROWS_STATE_FLAGS 0x00000001 +#define NV_MSGBOX_CMD_ARG1_REMAP_ROWS_HISTOGRAM 0x00000002 +#define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_0 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_1 0x00000001 +#define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_2 0x00000002 +#define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_3 0x00000003 + +/* Async requests */ +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_CONTROL_GET \ + 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_CONTROL_SET \ + 0x00000001 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_INFO_GET \ + 0x00000002 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_THERMAL_FAN_V1_COUNT_GET \ + 0x00000003 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_THERMAL_FAN_V1_INFO_GET \ + 0x00000004 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_THERMAL_FAN_V1_STATUS_GET \ + 0x00000005 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_OVERCLOCKING_LIMIT_CONTROL_GET \ + 0x00000006 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_OVERCLOCKING_LIMIT_CONTROL_SET \ + 0x00000007 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_ENERGY_COUNTER_STATUS_GET \ + 0x00000008 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_VIOLATION_COUNTERS_STATUS_GET \ + 0x00000009 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_UTILIZATION_RATE_GET \ + 0x0000000a +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_OOB_CLOCK_LIMIT_SET \ + 0x0000000b +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_DEVICE_MODE_CONTROL \ + 0x0000000c +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_TEST_MESSAGE_SEND \ + 0x0000000e +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_CLOCK_LIMIT_GET \ + 0x0000000d +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_FAN_CURVE_POINTS_GET_SET \ + 0x0000000f +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_POWER_HINT_GET \ + 0x00000010 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_CONFIGURE_PROGRAMMABLE_EDPP \ + 0x00000011 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_POLL 0x000000ff + + +#define NV_MSGBOX_CMD_ARG1_ECC_V2_SEL 15:14 +#define NV_MSGBOX_CMD_ARG1_ECC_V2_SEL_CNT 0x00000000 /* counters */ +#define NV_MSGBOX_CMD_ARG1_ECC_V2_SEL_FBA 0x00000001 /* FB addresses */ +/* Counters */ +#define NV_MSGBOX_CMD_ARG1_ECC_V2_CNT_DEV 13:12 +#define NV_MSGBOX_CMD_ARG1_ECC_V2_CNT_DEV_FB 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ECC_V2_CNT_DEV_GR 0x00000001 +#define NV_MSGBOX_CMD_ARG1_ECC_V2_CNT_FB_SRC 11:10 +#define NV_MSGBOX_CMD_ARG1_ECC_V2_CNT_FB_SRC_LTC 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ECC_V2_CNT_FB_SRC_FB 0x00000001 +#define NV_MSGBOX_CMD_ARG1_ECC_V2_CNT_GR_SRC 11:10 +#define NV_MSGBOX_CMD_ARG1_ECC_V2_CNT_GR_SRC_L1 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ECC_V2_CNT_GR_SRC_RF 0x00000001 +#define NV_MSGBOX_CMD_ARG1_ECC_V2_CNT_TYPE 9:8 +#define NV_MSGBOX_CMD_ARG1_ECC_V2_CNT_TYPE_SBE 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ECC_V2_CNT_TYPE_DBE 0x00000001 +/* FB addresses */ +#define NV_MSGBOX_CMD_ARG1_ECC_V2_FBA_SC 13:13 /* scope */ +#define NV_MSGBOX_CMD_ARG1_ECC_V2_FBA_SC_IND 0x00000000 /* individual addresses */ +#define NV_MSGBOX_CMD_ARG1_ECC_V2_FBA_SC_CUMUL 0x00000001 /* cumulative counters */ +#define NV_MSGBOX_CMD_ARG1_ECC_V2_FBA_IND_FLD 12:12 /* field */ +#define NV_MSGBOX_CMD_ARG1_ECC_V2_FBA_IND_FLD_CTRS 0x00000000 /* counters: sbe, dbe */ +#define NV_MSGBOX_CMD_ARG1_ECC_V2_FBA_IND_FLD_ADDR 0x00000001 /* address value */ +#define NV_MSGBOX_CMD_ARG1_ECC_V2_FBA_IND_INDEX 11:8 /* address array index: 0-13 */ + +#define NV_MSGBOX_CMD_ARG1_ECC_V3_SEL 15:14 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_SEL_CNT 0x00000000 /* counters */ +#define NV_MSGBOX_CMD_ARG1_ECC_V3_SEL_FBA 0x00000001 /* FB addresses */ +/* Counters */ +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_DEV 13:12 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_DEV_FB 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_DEV_GR 0x00000001 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_FB_SRC 11:10 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_FB_SRC_LTC 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_FB_SRC_FB 0x00000001 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_GR_SRC 11:10 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_GR_SRC_L1 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_GR_SRC_RF 0x00000001 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_GR_SRC_TEX 0x00000002 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_TYPE 9:8 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_TYPE_SBE 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_TYPE_DBE 0x00000001 +/* FB addresses */ +#define NV_MSGBOX_CMD_ARG1_ECC_V3_FBA_SC 13:13 /* scope */ +#define NV_MSGBOX_CMD_ARG1_ECC_V3_FBA_SC_IND 0x00000000 /* individual addresses */ +// These are not present in V3 +//#define NV_MSGBOX_CMD_ARG1_ECC_V3_FBA_SC_CUMUL 0x00000001 /* cumulative counters */ +#define NV_MSGBOX_CMD_ARG1_ECC_V3_FBA_IND_FLD 12:12 /* field */ +#define NV_MSGBOX_CMD_ARG1_ECC_V3_FBA_IND_FLD_CTRS 0x00000000 /* counters: sbe, dbe */ +#define NV_MSGBOX_CMD_ARG1_ECC_V3_FBA_IND_FLD_ADDR 0x00000001 /* address value */ +#define NV_MSGBOX_CMD_ARG1_ECC_V3_FBA_IND_INDEX 11:8 /* address array index: 0-13 */ + +#define NV_MSGBOX_CMD_ARG1_ECC_V4_SEL 15:14 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_SEL_CNT 0x00000000 /* counters */ +#define NV_MSGBOX_CMD_ARG1_ECC_V4_SEL_FBA 0x00000001 /* FB addresses */ +/* Counters */ +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_DEV 13:12 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_DEV_FB 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_DEV_GR 0x00000001 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_FB_SRC 11:10 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_FB_SRC_LTC 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_FB_SRC_FB 0x00000001 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_GR_SRC 11:10 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_GR_SRC_SHM 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_GR_SRC_RF 0x00000001 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_GR_SRC_TEX 0x00000002 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_TYPE 9:8 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_TYPE_SBE 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_TYPE_DBE 0x00000001 +/* FB addresses */ +#define NV_MSGBOX_CMD_ARG1_ECC_V4_FBA_SC 13:13 /* scope */ +#define NV_MSGBOX_CMD_ARG1_ECC_V4_FBA_SC_IND 0x00000000 /* individual addresses */ +// These are not present in V4 +//#define NV_MSGBOX_CMD_ARG1_ECC_V4_FBA_SC_CUMUL 0x00000001 /* cumulative counters */ +#define NV_MSGBOX_CMD_ARG1_ECC_V4_FBA_IND_FLD 12:12 /* field */ +#define NV_MSGBOX_CMD_ARG1_ECC_V4_FBA_IND_FLD_CTRS 0x00000000 /* counters: sbe, dbe */ +#define NV_MSGBOX_CMD_ARG1_ECC_V4_FBA_IND_FLD_ADDR 0x00000001 /* address value */ +#define NV_MSGBOX_CMD_ARG1_ECC_V4_FBA_IND_INDEX 11:8 /* address array index: 0-13 */ + +#define NV_MSGBOX_CMD_ARG1_ECC_V5_SEL 15:15 +#define NV_MSGBOX_CMD_ARG1_ECC_V5_SEL_COUNTS 0x00000000 /* address/region counts */ +#define NV_MSGBOX_CMD_ARG1_ECC_V5_SEL_ERR_BUFFER 0x00000001 /* SRAM error buffer */ + +#define NV_MSGBOX_CMD_ARG1_ECC_V5_COUNTS_INDEX_LO 14:8 /* 7 least significant index bits */ + +#define NV_MSGBOX_CMD_ARG1_ECC_V5_ERR_BUF_INDEX 11:8 /* buffer entry index */ + +#define NV_MSGBOX_CMD_ARG1_ACCESS_WP_MODE_ACTION 8:8 +#define NV_MSGBOX_CMD_ARG1_ACCESS_WP_MODE_ACTION_GET 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ACCESS_WP_MODE_ACTION_SET 0x00000001 + +#define NV_MSGBOX_CMD_ARG1_BUNDLE_REQUEST_COUNT 11:8 +#define NV_MSGBOX_CMD_ARG1_BUNDLE_DISP_RULE_COUNT 15:12 + +#define NV_MSGBOX_CMD_ARG1_GET_DEM_OLDEST 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GET_DEM_BY_SEQ_NUMBER 0x00000001 +#define NV_MSGBOX_CMD_ARG1_GET_DEM_BY_TIMESTAMP 0x00000002 + +#define NV_MSGBOX_CMD_ARG1_ECC_V6_ERROR_TYPE 15:8 +#define NV_MSGBOX_CMD_ARG1_ECC_V6_ERROR_TYPE_CORRECTABLE_ERROR 0 +#define NV_MSGBOX_CMD_ARG1_ECC_V6_ERROR_TYPE_UNCORRECTABLE_ERROR 1 + +// Query type of _GET_POWER_HINT_INFO +#define NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_CLK 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_TEMP 0x00000001 +#define NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_PROFILES 0x00000002 +#define NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_NUM \ + (NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_PROFILES + 1) + +// Arg1 for _GPU_PERFORMANCE_MONITORING +#define NV_MSGBOX_CMD_ARG1_GPM_ACTION 15:14 +#define NV_MSGBOX_CMD_ARG1_GPM_ACTION_GET_INSTANTANEOUS_METRIC 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GPM_ACTION_GET_SNAPSHOT_METRIC 0x00000001 +#define NV_MSGBOX_CMD_ARG1_GPM_ACTION_CAPTURE_SNAPSHOT 0x00000002 +#define NV_MSGBOX_CMD_ARG1_GPM_ACTION_SET_MULTIPLIER 0x00000003 + +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC 13:8 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_GRAPHICS_ENGINE 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_SM_ACTIVITY 0x00000001 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_SM_OCCUPANCY 0x00000002 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_TENSOR_CORE_ACTIVITY 0x00000003 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_DRAM_USAGE 0x00000004 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_FP64_ACTIVITY 0x00000005 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_FP32_ACTIVITY 0x00000006 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_FP16_ACTIVITY 0x00000007 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_PCIE_TX_BANDWIDTH 0x00000008 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_PCIE_RX_BANDWIDTH 0x00000009 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_TX_BANDWIDTH 0x0000000A +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_TX_BANDWIDTH 0x0000000B +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_RX_BANDWIDTH 0x0000000C +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_RX_BANDWIDTH 0x0000000D +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVDEC_UTILIZATION 0x0000000E +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVJPG_UTILIZATION 0x0000000F +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVOFA_UTILIZATION 0x00000010 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_TX_BW_PER_LINK 0x00000011 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_TX_BW_PER_LINK 0x00000012 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_RX_BW_PER_LINK 0x00000013 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_RX_BW_PER_LINK 0x00000014 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVDEC_UTIL_PER_INSTANCE 0x00000015 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVJPG_UTIL_PER_INSTANCE 0x00000016 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_INTEGER_UTILIZATION 0x00000017 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_DMMA_UTILIZATION 0x00000018 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_HMMA_UTILIZATION 0x00000019 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_IMMA_UTILIZATION 0x0000001A + +#define NV_MSGBOX_CMD_ARG1_DYN_SYS_INFO_DRIVER_VERSION_V1 0x00000000 + +#define NV_MSGBOX_CMD_ARG2 23:16 +#define NV_MSGBOX_CMD_ARG2_NULL 0x00000000 + +#define NV_MSGBOX_CMD_ARG2_ECC_V2_FB_PARTITION 23:20 +#define NV_MSGBOX_CMD_ARG2_ECC_V2_FB_SLICE 19:16 +#define NV_MSGBOX_CMD_ARG2_ECC_V2_GR_GPC 23:20 +#define NV_MSGBOX_CMD_ARG2_ECC_V2_GR_TPC 19:16 + +#define NV_MSGBOX_CMD_ARG2_ECC_V3_FB_PARTITION 23:20 +#define NV_MSGBOX_CMD_ARG2_ECC_V3_FB_SLICE 19:16 +#define NV_MSGBOX_CMD_ARG2_ECC_V3_FB_SUBPARTITION 19:16 +#define NV_MSGBOX_CMD_ARG2_ECC_V3_GR_TEX 23:22 +#define NV_MSGBOX_CMD_ARG2_ECC_V3_GR_GPC 21:19 +#define NV_MSGBOX_CMD_ARG2_ECC_V3_GR_TPC 18:16 + +#define NV_MSGBOX_CMD_ARG2_ECC_V4_FB_PARTITION 23:20 +#define NV_MSGBOX_CMD_ARG2_ECC_V4_FB_SLICE 19:16 +#define NV_MSGBOX_CMD_ARG2_ECC_V4_FB_SUBPARTITION 19:16 +#define NV_MSGBOX_CMD_ARG2_ECC_V4_GR_TEX 23:22 +#define NV_MSGBOX_CMD_ARG2_ECC_V4_GR_GPC 21:19 +#define NV_MSGBOX_CMD_ARG2_ECC_V4_GR_TPC 18:16 + +#define NV_MSGBOX_CMD_ARG2_ECC_V5_COUNTS_INDEX_HI 23:21 +#define NV_MSGBOX_CMD_ARG2_ECC_V5_COUNTS_TYPE 18:16 +#define NV_MSGBOX_CMD_ARG2_ECC_V5_COUNTS_TYPE_HDR_META 0x0 /* header and metadata */ + +#define NV_MSGBOX_CMD_ARG2_ECC_V5_COUNTS_TYPE_ADDR_ADDR 0x1 /* addr: address */ +#define NV_MSGBOX_CMD_ARG2_ECC_V5_COUNTS_TYPE_ADDR_UNCORRECTED_COUNTS 0x2 /* addr: uncorrectedCounts */ +#define NV_MSGBOX_CMD_ARG2_ECC_V5_COUNTS_TYPE_ADDR_CORRECTED_TOTAL 0x3 /* addr: correctedTotal */ +#define NV_MSGBOX_CMD_ARG2_ECC_V5_COUNTS_TYPE_ADDR_CORRECTED_UNIQUE 0x4 /* addr: correctedUnique */ + +#define NV_MSGBOX_CMD_ARG2_ECC_V5_COUNTS_TYPE_REGN_CORRECTED_TOTAL 0x1 /* region: correctedTotal */ +#define NV_MSGBOX_CMD_ARG2_ECC_V5_COUNTS_TYPE_REGN_CORRECTED_UNIQUE 0x2 /* region: correctedUnique */ +#define NV_MSGBOX_CMD_ARG2_ECC_V5_COUNTS_TYPE_REGN_UNCORRECTED_TOTAL 0x3 /* region: uncorrectedTotal */ +#define NV_MSGBOX_CMD_ARG2_ECC_V5_COUNTS_TYPE_REGN_UNCORRECTED_UNIQUE 0x4 /* region: uncorrectedUnique */ + +#define NV_MSGBOX_CMD_ARG2_ECC_V5_COUNTS_TYPE_MAX 0x4 + +#define NV_MSGBOX_CMD_ARG2_ECC_V5_ERR_BUF_TYPE 17:16 /* entry element type */ +#define NV_MSGBOX_CMD_ARG2_ECC_V5_ERR_BUF_TYPE_ERR_TYPE_META 0x0 /* errorType and metadata */ +#define NV_MSGBOX_CMD_ARG2_ECC_V5_ERR_BUF_TYPE_TIME_STAMP 0x1 /* time stamp */ +#define NV_MSGBOX_CMD_ARG2_ECC_V5_ERR_BUF_TYPE_ADDR 0x2 /* address */ + +#define NV_MSGBOX_CMD_ARG2_ECC_V5_ERR_BUF_TYPE_MAX 0x2 + +#define NV_MSGBOX_CMD_ARG2_REG_INDEX_SCRATCH_PAGE 0x00000000 +#define NV_MSGBOX_CMD_ARG2_REG_INDEX_EVENTS_PENDING 0x00000001 +#define NV_MSGBOX_CMD_ARG2_REG_INDEX_EVENT_MASK 0x00000002 +#define NV_MSGBOX_CMD_ARG2_REG_INDEX_MAX 0x00000002 /* increase when adding + new registers */ + +#define NV_MSGBOX_CMD_ARG2_NVLINK_INFO_AGGREGATE 0x000000FF + +#define NV_MSGBOX_CMD_ARG2_ACCESS_WP_MODE_SET_STATE 23:16 +#define NV_MSGBOX_CMD_ARG2_ACCESS_WP_MODE_SET_STATE_DISABLED 0x0000005A +#define NV_MSGBOX_CMD_ARG2_ACCESS_WP_MODE_SET_STATE_ENABLED 0x000000A5 + +#define NV_MSGBOX_CMD_ARG2_GET_CLOCK_FREQ_INFO_GPCCLK 0x00000000 +#define NV_MSGBOX_CMD_ARG2_GET_CLOCK_FREQ_INFO_MEMCLK 0x00000001 + +#define NV_MSGBOX_CMD_ARG2_ECC_V6_COUNTER_TYPE 23:16 +#define NV_MSGBOX_CMD_ARG2_ECC_V6_COUNTER_TYPE_SRAM 0 +#define NV_MSGBOX_CMD_ARG2_ECC_V6_COUNTER_TYPE_DRAM 1 + +#define NV_MSGBOX_CMD_ARG2_REMAP_ROW_RAW_CNT_COMBINED 0x00000000 +#define NV_MSGBOX_CMD_ARG2_REMAP_ROW_RAW_CNT_UNCORR 0x00000001 +#define NV_MSGBOX_CMD_ARG2_REMAP_ROW_RAW_CNT_CORR 0x00000002 + +#define NV_MSGBOX_CMD_ARG2_REMAP_ROWS_STATE_FLAGS_PAGE0 0x00000000 + +/*! + * Arg2 for _GET_POWER_HINT_INFO + * ARG1 == _GET_POWER_HINT_INFO_CLK + * Return Min/Max frequency in MHz + */ +#define NV_MSGBOX_CMD_ARG2_GET_POWER_HINT_INFO_CLK_GR 0x00000000 +#define NV_MSGBOX_CMD_ARG2_GET_POWER_HINT_INFO_CLK_MEM 0x00000001 + +/*! + * Arg2 for _GET_POWER_HINT_INFO + * ARG1 == _GET_POWER_HINT_INFO_PROFILES + * Return bits represents which profiles are available + */ +#define NV_MSGBOX_CMD_ARG2_GET_POWER_HINT_INFO_PROFILES_PAGE_0 0x00000000 +#define NV_MSGBOX_CMD_ARG2_GET_POWER_HINT_INFO_PROFILES_PAGE_1 0x00000001 +#define NV_MSGBOX_CMD_ARG2_GET_POWER_HINT_INFO_PROFILES_PAGE_2 0x00000002 +#define NV_MSGBOX_CMD_ARG2_GET_POWER_HINT_INFO_PROFILES_PAGE_3 0x00000003 +#define NV_MSGBOX_CMD_ARG2_GET_POWER_HINT_INFO_PROFILES_TOTAL_PAGES \ + (NV_MSGBOX_CMD_ARG2_GET_POWER_HINT_INFO_PROFILES_PAGE_3 + 1) + +// Arg2 for _GPU_PERFORMANCE_MONITORING +#define NV_MSGBOX_CMD_ARG2_GPM_PARTITION_AGGREGATE 0x000000FF +#define NV_MSGBOX_CMD_ARG2_GPM_PARTITION_INDEX 21:16 +#define NV_MSGBOX_CMD_ARG2_GPM_CI_METRICS_REQUESTED 23:23 +#define NV_MSGBOX_CMD_ARG2_GPM_CI_METRICS_REQUESTED_YES 0x00000001 +#define NV_MSGBOX_CMD_ARG2_GPM_CI_METRICS_REQUESTED_NO 0x00000000 + +#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER 23:16 +#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_1X 0x00000001 +#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_2X 0x00000002 +#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_5X 0x00000005 +#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_10X 0x0000000A +#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_100X 0x00000064 + + +#define NV_MSGBOX_CMD_STATUS 28:24 +#define NV_MSGBOX_CMD_STATUS_NULL 0x00000000 +#define NV_MSGBOX_CMD_STATUS_ERR_REQUEST 0x00000001 +#define NV_MSGBOX_CMD_STATUS_ERR_OPCODE 0x00000002 +#define NV_MSGBOX_CMD_STATUS_ERR_ARG1 0x00000003 +#define NV_MSGBOX_CMD_STATUS_ERR_ARG2 0x00000004 +#define NV_MSGBOX_CMD_STATUS_ERR_DATA 0x00000005 +#define NV_MSGBOX_CMD_STATUS_ERR_MISC 0x00000006 +#define NV_MSGBOX_CMD_STATUS_ERR_I2C_ACCESS 0x00000007 +#define NV_MSGBOX_CMD_STATUS_ERR_NOT_SUPPORTED 0x00000008 +#define NV_MSGBOX_CMD_STATUS_ERR_NOT_AVAILABLE 0x00000009 +#define NV_MSGBOX_CMD_STATUS_ERR_BUSY 0x0000000a +#define NV_MSGBOX_CMD_STATUS_ERR_AGAIN 0x0000000b +#define NV_MSGBOX_CMD_STATUS_ERR_SENSOR_DATA 0x0000000c +#define NV_MSGBOX_CMD_STATUS_ERR_DISPOSITION 0x0000000d +#define NV_MSGBOX_CMD_STATUS_PARTIAL_FAILURE 0x0000001b +#define NV_MSGBOX_CMD_STATUS_ACCEPTED 0x0000001c +#define NV_MSGBOX_CMD_STATUS_INACTIVE 0x0000001d +#define NV_MSGBOX_CMD_STATUS_READY 0x0000001e +#define NV_MSGBOX_CMD_STATUS_SUCCESS 0x0000001f + +#define NV_MSGBOX_CMD_RSVD 29:29 +#define NV_MSGBOX_CMD_RSVD_INIT 0x00000000 + +#define NV_MSGBOX_CMD_COPY_DATA 30:30 +#define NV_MSGBOX_CMD_COPY_DATA_OFF 0x00000000 +#define NV_MSGBOX_CMD_COPY_DATA_ON 0x00000001 + +#define NV_MSGBOX_CMD_EVENT_PENDING 30:30 +#define NV_MSGBOX_CMD_EVENT_PENDING_OFF 0x00000000 +#define NV_MSGBOX_CMD_EVENT_PENDING_ON 0x00000001 + +#define NV_MSGBOX_CMD_INTR 31:31 +#define NV_MSGBOX_CMD_INTR_NOT_PENDING 0x00000000 +#define NV_MSGBOX_CMD_INTR_PENDING 0x00000001 +#define NV_MSGBOX_CMD_INTR_CLEAR 0x00000000 + +/* For individual requests in a bundle */ + +#define NV_MSGBOX_CMD_ON_BUNDLE_FAILURE 31:31 +#define NV_MSGBOX_CMD_ON_BUNDLE_FAILURE_CONTINUE 0x00000000 +#define NV_MSGBOX_CMD_ON_BUNDLE_FAILURE_STOP 0x00000001 + +#define NV_MSGBOX_CMD_DATA_COPY 23:0 +#define NV_MSGBOX_CMD_DATA_COPY_INIT 0x00000000 +#define NV_MSGBOX_CMD_EXT_STATUS 23:0 + +// NV_MSGBOX_CMD_COPY_SIZE_ENCODING used for certain commands to embed size +// indicators in the output when copy-bit is set in request + +#define NV_MSGBOX_CMD_COPY_SIZE_ENCODING_READ_DATA_OUT 0:0 +#define NV_MSGBOX_CMD_COPY_SIZE_ENCODING_READ_DATA_OUT_SET 1 +#define NV_MSGBOX_CMD_COPY_SIZE_ENCODING_READ_DATA_OUT_NOT_SET 0 + +#define NV_MSGBOX_CMD_COPY_SIZE_ENCODING_READ_EXT_DATA_OUT 1:1 +#define NV_MSGBOX_CMD_COPY_SIZE_ENCODING_READ_EXT_DATA_OUT_SET 1 +#define NV_MSGBOX_CMD_COPY_SIZE_ENCODING_READ_EXT_DATA_OUT_NOT_SET 0 + +#define NV_MSGBOX_CMD_COPY_SIZE_ENCODING_DATA 23:2 +#define NV_MSGBOX_CMD_COPY_SIZE_ENCODING_DATA_INIT 0x00000000 + +/* Response to NV_MSGBOX_CMD_ARG1_REMAP_ROWS_HISTOGRAM */ +#define NV_MSGBOX_CMD_REMAP_ROW_HISTOGRAM_NONE_AVAILABILITY 15:0 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_THROUGHPUT_* */ +#define NV_MSGBOX_CMD_NVLINK_INFO_THROUGHPUT_GRANULARITY 1:0 +#define NV_MSGBOX_CMD_NVLINK_INFO_THROUGHPUT_GRANULARITY_KIB 0x00000000 +#define NV_MSGBOX_CMD_NVLINK_INFO_THROUGHPUT_GRANULARITY_MIB 0x00000001 +#define NV_MSGBOX_CMD_NVLINK_INFO_THROUGHPUT_GRANULARITY_GIB 0x00000002 +#define NV_MSGBOX_CMD_NVLINK_INFO_THROUGHPUT_GRANULARITY_TIB 0x00000003 +#define NV_MSGBOX_CMD_NVLINK_INFO_THROUGHPUT_NEW_SAMPLE 2:2 +#define NV_MSGBOX_CMD_NVLINK_INFO_THROUGHPUT_NEW_SAMPLE_FALSE 0x00000000 +#define NV_MSGBOX_CMD_NVLINK_INFO_THROUGHPUT_NEW_SAMPLE_TRUE 0x00000001 +#define NV_MSGBOX_CMD_NVLINK_INFO_THROUGHPUT_INVALID_DELTA 3:3 +#define NV_MSGBOX_CMD_NVLINK_INFO_THROUGHPUT_INVALID_DELTA_FALSE 0x00000000 +#define NV_MSGBOX_CMD_NVLINK_INFO_THROUGHPUT_INVALID_DELTA_TRUE 0x00000001 +#define NV_MSGBOX_CMD_NVLINK_INFO_THROUGHPUT_DELTA 23:4 + +/* + * Response to NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_TRAINING_ERR_STATE + * NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_RUNTIME_ERR_STATE + */ +#define NV_MSGBOX_CMD_NVLINK_INFO_TRAINING_ERROR_COUNT 11:0 +#define NV_MSGBOX_CMD_NVLINK_INFO_RUNTIME_ERROR_COUNT 23:12 +#define NV_MSGBOX_CMD_NVLINK_INFO_ERROR_COUNT_MAX \ + DRF_MASK(NV_MSGBOX_CMD_NVLINK_INFO_TRAINING_ERROR_COUNT) + +/** + * Response to NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_AVAILABILITY + */ +#define NV_MSGBOX_CMD_NVLINK_INFO_GET_NVLINK_INFO_AVAILABILTY_PAGE_0 0x00000000 + +/** + * This field is populated as response to the following metrics: + * - NV_MSGBOX_CMD_ARG1_GPM_METRIC_DRAM_USAGE + * - NV_MSGBOX_CMD_ARG1_GPM_METRIC_PCIE_TX_BANDWIDTH + * - NV_MSGBOX_CMD_ARG1_GPM_METRIC_PCIE_RX_BANDWIDTH + * - NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_TX_BANDWIDTH + * - NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_TX_BANDWIDTH + * - NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_RX_BANDWIDTH + * - NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_RX_BANDWIDTH + */ +#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY 2:0 +#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY_B 0x00000000 +#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY_KIB 0x00000001 +#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY_MIB 0x00000002 +#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY_GIB 0x00000003 + +/* MSGBOX data, capability dword structure */ + +#define NV_MSGBOX_DATA_REG 31:0 +#define NV_MSGBOX_DATA_CAP_COUNT 5 + +#define NV_MSGBOX_DATA_CAP_0 0 +#define NV_MSGBOX_DATA_CAP_0_TEMP_GPU_0 0:0 +#define NV_MSGBOX_DATA_CAP_0_TEMP_GPU_0_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_TEMP_GPU_0_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_TEMP_NVSWITCH_0 0:0 +#define NV_MSGBOX_DATA_CAP_0_TEMP_NVSWITCH_0_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_TEMP_NVSWITCH_0_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_TEMP_GPU_1 1:1 +#define NV_MSGBOX_DATA_CAP_0_TEMP_GPU_1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_TEMP_GPU_1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_TEMP_BOARD 4:4 +#define NV_MSGBOX_DATA_CAP_0_TEMP_BOARD_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_TEMP_BOARD_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_TEMP_MEMORY 5:5 +#define NV_MSGBOX_DATA_CAP_0_TEMP_MEMORY_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_TEMP_MEMORY_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_TEMP_PWR_SUPPLY 6:6 +#define NV_MSGBOX_DATA_CAP_0_TEMP_PWR_SUPPLY_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_TEMP_PWR_SUPPLY_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_TEMP_T_LIMIT 7:7 +#define NV_MSGBOX_DATA_CAP_0_TEMP_T_LIMIT_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_TEMP_T_LIMIT_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS 11:8 +#define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS_ZERO 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS_ADT7473 0x00000002 +#define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS_SFXP11_5 0x00000005 +#define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS_SFXP24_8 0x00000008 +#define NV_MSGBOX_DATA_CAP_0_POWER_TOTAL 16:16 +#define NV_MSGBOX_DATA_CAP_0_POWER_TOTAL_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_POWER_TOTAL_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_GPU_PCONTROL 17:17 +#define NV_MSGBOX_DATA_CAP_0_GPU_PCONTROL_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_GPU_PCONTROL_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_GPU_SYSCONTROL 18:18 +#define NV_MSGBOX_DATA_CAP_0_GPU_SYSCONTROL_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_GPU_SYSCONTROL_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_THERMP_BITS 28:24 // Adjust when adding new bits +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_ACOUSTIC 24:24 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_ACOUSTIC_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_ACOUSTIC_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SLOWDN 25:25 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SLOWDN_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SLOWDN_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SHUTDN 26:26 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SHUTDN_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SHUTDN_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_MEMORY 27:27 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_MEMORY_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_MEMORY_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_GPU_SW_SLOWDOWN 28:28 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_GPU_SW_SLOWDOWN_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_GPU_SW_SLOWDOWN_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_GET_FABRIC_STATE_FLAGS 29:29 +#define NV_MSGBOX_DATA_CAP_0_GET_FABRIC_STATE_FLAGS_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_GET_FABRIC_STATE_FLAGS_AVAILABLE 0x00000001 + +#define NV_MSGBOX_DATA_CAP_1 1 +#define NV_MSGBOX_DATA_CAP_1_BOARD_PART_NUM_V1 0:0 +#define NV_MSGBOX_DATA_CAP_1_BOARD_PART_NUM_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_BOARD_PART_NUM_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_OEM_INFO_V1 1:1 +#define NV_MSGBOX_DATA_CAP_1_OEM_INFO_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_OEM_INFO_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_SERIAL_NUM_V1 2:2 +#define NV_MSGBOX_DATA_CAP_1_SERIAL_NUM_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_SERIAL_NUM_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_MARKETING_NAME_V1 3:3 +#define NV_MSGBOX_DATA_CAP_1_MARKETING_NAME_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_MARKETING_NAME_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_GPU_PART_NUM_V1 4:4 +#define NV_MSGBOX_DATA_CAP_1_GPU_PART_NUM_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_GPU_PART_NUM_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_MEMORY_VENDOR_V1 5:5 +#define NV_MSGBOX_DATA_CAP_1_MEMORY_VENDOR_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_MEMORY_VENDOR_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_MEMORY_PART_NUM_V1 6:6 +#define NV_MSGBOX_DATA_CAP_1_MEMORY_PART_NUM_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_MEMORY_PART_NUM_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_BUILD_DATE_V1 7:7 +#define NV_MSGBOX_DATA_CAP_1_BUILD_DATE_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_BUILD_DATE_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_FIRMWARE_VER_V1 8:8 +#define NV_MSGBOX_DATA_CAP_1_FIRMWARE_VER_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_FIRMWARE_VER_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_VENDOR_ID_V1 9:9 +#define NV_MSGBOX_DATA_CAP_1_VENDOR_ID_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_VENDOR_ID_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_DEV_ID_V1 10:10 +#define NV_MSGBOX_DATA_CAP_1_DEV_ID_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_DEV_ID_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_SUB_VENDOR_ID_V1 11:11 +#define NV_MSGBOX_DATA_CAP_1_SUB_VENDOR_ID_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_SUB_VENDOR_ID_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_SUB_ID_V1 12:12 +#define NV_MSGBOX_DATA_CAP_1_SUB_ID_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_SUB_ID_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_GPU_GUID_V1 13:13 +#define NV_MSGBOX_DATA_CAP_1_GPU_GUID_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_GPU_GUID_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_INFOROM_VER_V1 14:14 +#define NV_MSGBOX_DATA_CAP_1_INFOROM_VER_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_INFOROM_VER_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_ECC_V1 16:16 +#define NV_MSGBOX_DATA_CAP_1_ECC_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_ECC_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_ECC_V2 17:17 +#define NV_MSGBOX_DATA_CAP_1_ECC_V2_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_ECC_V2_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_ECC_V3 18:18 +#define NV_MSGBOX_DATA_CAP_1_ECC_V3_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_ECC_V3_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_RET_PG_CNT 19:19 +#define NV_MSGBOX_DATA_CAP_1_RET_PG_CNT_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_RET_PG_CNT_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_ECC_V4 20:20 +#define NV_MSGBOX_DATA_CAP_1_ECC_V4_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_ECC_V4_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_ECC_V5 21:21 +#define NV_MSGBOX_DATA_CAP_1_ECC_V5_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_ECC_V5_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_ACCESS_WP_MODE 22:22 +#define NV_MSGBOX_DATA_CAP_1_ACCESS_WP_MODE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_ACCESS_WP_MODE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_GET_ECC_ENABLED_STATE 23:23 +#define NV_MSGBOX_DATA_CAP_1_GET_ECC_ENABLED_STATE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_GET_ECC_ENABLED_STATE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_GET_GPU_RESET_REQUIRED 24:24 +#define NV_MSGBOX_DATA_CAP_1_GET_GPU_RESET_REQUIRED_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_GET_GPU_RESET_REQUIRED_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_GPU_UTIL_COUNTERS 25:25 +#define NV_MSGBOX_DATA_CAP_1_GPU_UTIL_COUNTERS_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_GPU_UTIL_COUNTERS_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_NVLINK_INFO_STATE_V1 26:26 +#define NV_MSGBOX_DATA_CAP_1_NVLINK_INFO_STATE_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_NVLINK_INFO_STATE_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_NVLINK_ERROR_COUNTERS 27:27 +#define NV_MSGBOX_DATA_CAP_1_NVLINK_ERROR_COUNTERS_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_NVLINK_ERROR_COUNTERS_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_CLOCK_FREQ_INFO 28:28 +#define NV_MSGBOX_DATA_CAP_1_CLOCK_FREQ_INFO_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_CLOCK_FREQ_INFO_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_GET_MIG_ENABLED_STATE 29:29 +#define NV_MSGBOX_DATA_CAP_1_GET_MIG_ENABLED_STATE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_GET_MIG_ENABLED_STATE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_ECC_V6 30:30 +#define NV_MSGBOX_DATA_CAP_1_ECC_V6_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_ECC_V6_AVAILABLE 0x00000001 + +#define NV_MSGBOX_DATA_CAP_2 2 +#define NV_MSGBOX_DATA_CAP_2_GPU_DRIVER 0:0 +#define NV_MSGBOX_DATA_CAP_2_GPU_DRIVER_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_GPU_DRIVER_NOT_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_NVSWITCH_DRIVER 0:0 +#define NV_MSGBOX_DATA_CAP_2_NVSWITCH_DRIVER_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_NVSWITCH_DRIVER_NOT_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_GPU_REQUEST 1:1 +#define NV_MSGBOX_DATA_CAP_2_GPU_REQUEST_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_GPU_REQUEST_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_NUM_SCRATCH_BANKS 4:2 +#define NV_MSGBOX_DATA_CAP_2_NUM_SCRATCH_BANKS_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_FAN_V1_CONTROL 5:5 +#define NV_MSGBOX_DATA_CAP_2_FAN_V1_CONTROL_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_FAN_V1_CONTROL_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_PRODUCT_LENGTH_V1 6:6 +#define NV_MSGBOX_DATA_CAP_2_PRODUCT_LENGTH_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_PRODUCT_LENGTH_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_PRODUCT_WIDTH_V1 7:7 +#define NV_MSGBOX_DATA_CAP_2_PRODUCT_WIDTH_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_PRODUCT_WIDTH_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_PRODUCT_HEIGHT_V1 8:8 +#define NV_MSGBOX_DATA_CAP_2_PRODUCT_HEIGHT_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_PRODUCT_HEIGHT_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_PCIE_SPEED_V1 9:9 +#define NV_MSGBOX_DATA_CAP_2_PCIE_SPEED_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_PCIE_SPEED_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_PCIE_WIDTH_V1 10:10 +#define NV_MSGBOX_DATA_CAP_2_PCIE_WIDTH_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_PCIE_WIDTH_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_TGP_LIMIT_V1 11:11 +#define NV_MSGBOX_DATA_CAP_2_TGP_LIMIT_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_TGP_LIMIT_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_SCRATCH_PAGE_SIZE 12:12 +#define NV_MSGBOX_DATA_CAP_2_SCRATCH_PAGE_SIZE_1024B 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_SCRATCH_PAGE_SIZE_256B 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_REMAP_ROW_STATS 13:13 +#define NV_MSGBOX_DATA_CAP_2_REMAP_ROW_STATS_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_REMAP_ROW_STATS_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_GET_PCIE_LINK_INFO 14:14 +#define NV_MSGBOX_DATA_CAP_2_GET_PCIE_LINK_INFO_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_GET_PCIE_LINK_INFO_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_GET_GPU_DRAIN_AND_RESET_RECOMMENDED 15:15 +#define NV_MSGBOX_DATA_CAP_2_GET_GPU_DRAIN_AND_RESET_RECOMMENDED_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_GET_GPU_DRAIN_AND_RESET_RECOMMENDED_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_THROUGHPUT 16:16 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_THROUGHPUT_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_THROUGHPUT_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_LINK_STATE_V2 17:17 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_LINK_STATE_V2_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_LINK_STATE_V2_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_SUBLINK_WIDTH 18:18 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_SUBLINK_WIDTH_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_SUBLINK_WIDTH_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_GET_ENERGY_COUNTER 19:19 +#define NV_MSGBOX_DATA_CAP_2_GET_ENERGY_COUNTER_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_GET_ENERGY_COUNTER_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_REMAP_ROW_PENDING 20:20 +#define NV_MSGBOX_DATA_CAP_2_REMAP_ROW_PENDING_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_REMAP_ROW_PENDING_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_REMAP_ROW_HISTOGRAM 21:21 +#define NV_MSGBOX_DATA_CAP_2_REMAP_ROW_HISTOGRAM_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_REMAP_ROW_HISTOGRAM_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_TRAINING_ERROR_STATE 22:22 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_TRAINING_ERROR_STATE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_TRAINING_ERROR_STATE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_RUNTIME_ERROR_STATE 23:23 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_RUNTIME_ERROR_STATE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_RUNTIME_ERROR_STATE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_GET_PCIE_LINK_TARGET_SPEED 25:25 +#define NV_MSGBOX_DATA_CAP_2_GET_PCIE_LINK_TARGET_SPEED_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_GET_PCIE_LINK_TARGET_SPEED_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_CURRENT_PSTATE 26:26 +#define NV_MSGBOX_DATA_CAP_2_CURRENT_PSTATE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_CURRENT_PSTATE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_AVAILABILITY 27:27 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_AVAILABILITY_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_AVAILABILITY_AVAILABLE 0x00000001 + +#define NV_MSGBOX_DATA_CAP_4 4 +#define NV_MSGBOX_DATA_CAP_4_HW_VIOLATION_TIME 0:0 +#define NV_MSGBOX_DATA_CAP_4_HW_VIOLATION_TIME_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_HW_VIOLATION_TIME_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_SW_VIOLATION_TIME 1:1 +#define NV_MSGBOX_DATA_CAP_4_SW_VIOLATION_TIME_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_SW_VIOLATION_TIME_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_SW_POWER_VIOLATION_TIME 2:2 +#define NV_MSGBOX_DATA_CAP_4_SW_POWER_VIOLATION_TIME_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_SW_POWER_VIOLATION_TIME_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_SW_THERMAL_VIOLATION_TIME 3:3 +#define NV_MSGBOX_DATA_CAP_4_SW_THERMAL_VIOLATION_TIME_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_SW_THERMAL_VIOLATION_TIME_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_UTILIZATION_RATE 4:4 +#define NV_MSGBOX_DATA_CAP_4_UTILIZATION_RATE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_UTILIZATION_RATE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_GET_DRIVER_EVENT_MSG 5:5 +#define NV_MSGBOX_DATA_CAP_4_GET_DRIVER_EVENT_MSG_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_GET_DRIVER_EVENT_MSG_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_REQUEST_BUNDLING 6:6 +#define NV_MSGBOX_DATA_CAP_4_REQUEST_BUNDLING_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_REQUEST_BUNDLING_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_SET_DEVICE_DISABLE 7:7 +#define NV_MSGBOX_DATA_CAP_4_SET_DEVICE_DISABLE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_SET_DEVICE_DISABLE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_SET_ECC_MODE 8:8 +#define NV_MSGBOX_DATA_CAP_4_SET_ECC_MODE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_SET_ECC_MODE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_SET_MIG_MODE 10:10 +#define NV_MSGBOX_DATA_CAP_4_SET_MIG_MODE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_SET_MIG_MODE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_FAN_CURVE_POINTS_GET_SET 11:11 +#define NV_MSGBOX_DATA_CAP_4_FAN_CURVE_POINTS_GET_SET_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_FAN_CURVE_POINTS_GET_SET_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_POWER_HINT 22:22 +#define NV_MSGBOX_DATA_CAP_4_POWER_HINT_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_POWER_HINT_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_DRIVER_VERSION_V1 23:23 +#define NV_MSGBOX_DATA_CAP_4_DRIVER_VERSION_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_DRIVER_VERSION_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING 24:24 +#define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_CONFIGURE_PROGRAMMABLE_EDPP 30:30 +#define NV_MSGBOX_DATA_CAP_4_CONFIGURE_PROGRAMMABLE_EDPP_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_CONFIGURE_PROGRAMMABLE_EDPP_AVAILABLE 0x00000001 + +/* ECC counters */ +#define NV_MSGBOX_DATA_ECC_CNT_16BIT_DBE 31:16 +#define NV_MSGBOX_DATA_ECC_CNT_16BIT_SBE 16:0 +#define NV_MSGBOX_DATA_ECC_CNT_8BIT_DBE 23:16 +#define NV_MSGBOX_DATA_ECC_CNT_8BIT_SBE 7:0 + +#define NV_MSGBOX_DATA_ECC_V5_COUNT_HEADER 7:0 + +#define NV_MSGBOX_DATA_ECC_V5_COUNT_HDR_ID 1:0 +#define NV_MSGBOX_DATA_ECC_V5_COUNT_HDR_ID_INVAL 0 +#define NV_MSGBOX_DATA_ECC_V5_COUNT_HDR_ID_ADDR 1 +#define NV_MSGBOX_DATA_ECC_V5_COUNT_HDR_ID_REGN 2 + +#define NV_MSGBOX_DATA_ECC_V5_COUNT_METADATA 31:16 + +#define NV_MSGBOX_DATA_ECC_V5_ERR_BUF_ERR_TYPE 7:0 + +#define NV_MSGBOX_DATA_ECC_V5_ERR_BUF_ERR_TYPE_ID 0:0 +#define NV_MSGBOX_DATA_ECC_V5_ERR_BUF_ERR_TYPE_ID_UNCORR 0 +#define NV_MSGBOX_DATA_ECC_V5_ERR_BUF_ERR_TYPE_ID_CORR 1 + +#define NV_MSGBOX_DATA_ECC_V5_ERR_BUF_METADATA 31:16 + +#define NV_MSGBOX_DATA_ECC_V5_METADATA_STRUCT_ID 21:16 +#define NV_MSGBOX_DATA_ECC_V5_METADATA_STRUCT_ID_LRF 0 +#define NV_MSGBOX_DATA_ECC_V5_METADATA_STRUCT_ID_L1DATA 1 +#define NV_MSGBOX_DATA_ECC_V5_METADATA_STRUCT_ID_L1TAG 2 +#define NV_MSGBOX_DATA_ECC_V5_METADATA_STRUCT_ID_CBU 3 +#define NV_MSGBOX_DATA_ECC_V5_METADATA_STRUCT_ID_LTC 4 +#define NV_MSGBOX_DATA_ECC_V5_METADATA_STRUCT_ID_DRAM 5 + +#define NV_MSGBOX_DATA_ECC_V5_METADATA_LOCATION_ID 26:22 +#define NV_MSGBOX_DATA_ECC_V5_METADATA_SUBLOCATION_ID 31:27 + +/* NV_MSGBOX_CMD_OPCODE_SCRATCH_COPY src offset argument */ +#define NV_MSGBOX_DATA_COPY_SRC_OFFSET 7:0 + +/* NV_MSGBOX_CMD_ARG2_REG_INDEX_SCRATCH_PAGE register layout */ +#define NV_MSGBOX_DATA_SCRATCH_PAGE_DST 7:0 +#define NV_MSGBOX_DATA_SCRATCH_PAGE_SRC 15:8 + +/* Async request status codes returned in the data register */ +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS 7:0 + +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_SUCCESS 0x00000000 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_CARD_NOT_PRESENT 0x00000001 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_DUAL_LINK_INUSE 0x00000002 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_GENERIC 0x00000003 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_GPU_NOT_FULL_POWER 0x00000004 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_IN_USE 0x00000005 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INSUFFICIENT_RESOURCES 0x00000006 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_ACCESS_TYPE 0x00000007 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_ARGUMENT 0x00000008 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_BASE 0x00000009 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_CHANNEL 0x0000000A +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_CLASS 0x0000000B +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_CLIENT 0x0000000C +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_COMMAND 0x0000000D +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_DATA 0x0000000E +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_DEVICE 0x0000000F +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_DMA_SPECIFIER 0x00000010 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_EVENT 0x00000011 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_FLAGS 0x00000012 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_FUNCTION 0x00000013 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_HEAP 0x00000014 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_INDEX 0x00000015 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_LIMIT 0x00000016 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_METHOD 0x00000017 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_OBJECT_BUFFER 0x00000018 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_OBJECT_ERROR 0x00000019 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_OBJECT_HANDLE 0x0000001A +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_OBJECT_NEW 0x0000001B +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_OBJECT_OLD 0x0000001C +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_OBJECT_PARENT 0x0000001D +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_OFFSET 0x0000001E +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_OWNER 0x0000001F +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_PARAM_STRUCT 0x00000020 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_PARAMETER 0x00000021 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_POINTER 0x00000022 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_REGISTRY_KEY 0x00000023 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_STATE 0x00000024 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_STRING_LENGTH 0x00000025 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_XLATE 0x00000026 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_IRQ_NOT_FIRING 0x00000027 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_MULTIPLE_MEMORY_TYPES 0x00000028 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_NOT_SUPPORTED 0x00000029 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_OPERATING_SYSTEM 0x0000002A +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_PROTECTION_FAULT 0x0000002B +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_TIMEOUT 0x0000002C +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_TOO_MANY_PRIMARIES 0x0000002D +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_IRQ_EDGE_TRIGGERED 0x0000002E +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_OPERATION 0x0000002F +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_NOT_COMPATIBLE 0x00000030 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_MORE_PROCESSING_REQUIRED 0x00000031 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INSUFFICIENT_PERMISSIONS 0x00000032 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_TIMEOUT_RETRY 0x00000033 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_NOT_READY 0x00000034 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_GPU_IS_LOST 0x00000035 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_IN_FULLCHIP_RESET 0x00000036 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_LOCK_STATE 0x00000037 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_ADDRESS 0x00000038 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_IRQ_LEVEL 0x00000039 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_MEMORY_TRAINING_FAILED 0x00000040 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_BUSY_RETRY 0x00000041 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INSUFFICIENT_POWER 0x00000042 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_OBJECT_NOT_FOUND 0x00000043 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_BUFFER_TOO_SMALL 0x00000044 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_RESET_REQUIRED 0x00000045 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_PRIV_SEC_VIOLATION 0x00000046 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_DEFERRED 0x00000047 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_FREQ_NOT_SUPPORTED 0x00000048 + +/* Response to NV_MSGBOX_CMD_OPCODE_GET_POWER_CONNECTOR_STATE */ +#define NV_MSGBOX_DATA_POWER_CONNECTED 0:0 +#define NV_MSGBOX_DATA_POWER_CONNECTED_SUFFICIENT 0x00000000 +#define NV_MSGBOX_DATA_POWER_CONNECTED_INSUFFICIENT 0x00000001 + +/* Response to NV_MSGBOX_CMD_OPCODE_GET_PAGE_RETIREMENT_STATS */ +#define NV_MSGBOX_DATA_RETIRED_PAGES_CNT_SBE 7:0 +#define NV_MSGBOX_DATA_RETIRED_PAGES_CNT_DBE 15:8 + +/* + * Response to + * NV_MSGBOX_CMD_ARG1_GET_MISC_ECC_ENABLED_STATE + * NV_MSGBOX_CMD_ARG1_GET_MISC_GPU_FLAGS_PAGE_0 + */ +#define NV_MSGBOX_DATA_ECC_ENABLED_STATE_SUPPORTED 0:0 +#define NV_MSGBOX_DATA_ECC_ENABLED_STATE_SUPPORTED_OFF 0x00000000 +#define NV_MSGBOX_DATA_ECC_ENABLED_STATE_SUPPORTED_ON 0x00000001 +#define NV_MSGBOX_DATA_ECC_ENABLED_STATE_CURRENT 1:1 +#define NV_MSGBOX_DATA_ECC_ENABLED_STATE_CURRENT_OFF 0x00000000 +#define NV_MSGBOX_DATA_ECC_ENABLED_STATE_CURRENT_ON 0x00000001 +#define NV_MSGBOX_DATA_ECC_ENABLED_STATE_PENDING 2:2 +#define NV_MSGBOX_DATA_ECC_ENABLED_STATE_PENDING_OFF 0x00000000 +#define NV_MSGBOX_DATA_ECC_ENABLED_STATE_PENDING_ON 0x00000001 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_MISC_GPU_FLAGS_PAGE_0 */ +#define NV_MSGBOX_DATA_MIG_ENABLED_STATE_SUPPORTED 3:3 +#define NV_MSGBOX_DATA_MIG_ENABLED_STATE_SUPPORTED_OFF 0x00000000 +#define NV_MSGBOX_DATA_MIG_ENABLED_STATE_SUPPORTED_ON 0x00000001 +#define NV_MSGBOX_DATA_MIG_ENABLED_STATE_CURRENT 4:4 +#define NV_MSGBOX_DATA_MIG_ENABLED_STATE_CURRENT_OFF 0x00000000 +#define NV_MSGBOX_DATA_MIG_ENABLED_STATE_CURRENT_ON 0x00000001 +#define NV_MSGBOX_DATA_MIG_ENABLED_STATE_PENDING 5:5 +#define NV_MSGBOX_DATA_MIG_ENABLED_STATE_PENDING_OFF 0x00000000 +#define NV_MSGBOX_DATA_MIG_ENABLED_STATE_PENDING_ON 0x00000001 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_MISC_DEVICE_FLAGS_PAGE_0 */ +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DRIVER_STATUS 6:6 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DRIVER_STATUS_NOT_RUNNING 0x00000000 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DRIVER_STATUS_RUNNING 0x00000001 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DEVICE_STATUS 7:7 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DEVICE_STATUS_ENABLED 0x00000000 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DEVICE_STATUS_DISABLED 0x00000001 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_FABRIC_MANAGER_STATUS 10:8 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_FABRIC_MANAGER_STATUS_NOT_RUNNING 0x00000000 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_FABRIC_MANAGER_STATUS_RUNNING 0x00000001 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_FABRIC_MANAGER_STATUS_TIMEOUT 0x00000002 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_FABRIC_MANAGER_STATUS_ERROR 0x00000003 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DISABLE_SOURCE 13:11 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DISABLE_SOURCE_NONE 0x00000000 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DISABLE_SOURCE_LOCAL_DEVICE 0x00000001 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DISABLE_SOURCE_PEER_DEVICE 0x00000002 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DISABLE_SOURCE_IN_BAND 0x00000003 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DISABLE_SOURCE_OUT_OF_BAND 0x00000004 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DISABLE_REASON 16:14 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DISABLE_REASON_NONE 0x00000000 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DISABLE_REASON_CLIENT_OVERRIDE 0x00000001 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DISABLE_REASON_TRUNK_LINK_FAILED 0x00000002 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DISABLE_REASON_ACCESS_LINK_FAILED 0x00000003 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DISABLE_REASON_UNSPECIFIED_FAILURE 0x00000004 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DRIVER_RELOAD 17:17 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DRIVER_RELOAD_NOT_PENDING 0x00000000 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DRIVER_RELOAD_PENDING 0x00000001 + +/* Response to NV_MSGBOX_CMD_ARG1_ACCESS_WP_MODE_ACTION_GET */ +#define NV_MSGBOX_DATA_ACCESS_WP_MODE_GET_STATE 7:0 +#define NV_MSGBOX_DATA_ACCESS_WP_MODE_GET_STATE_DISABLED 0x0000005A +#define NV_MSGBOX_DATA_ACCESS_WP_MODE_GET_STATE_ENABLED 0x000000A5 + +/* + * Response to + * NV_MSGBOX_CMD_ARG1_GET_MISC_GPU_RESET_REQUIRED + * NV_MSGBOX_CMD_ARG1_GET_MISC_GPU_FLAGS_PAGE_1 + */ +#define NV_MSGBOX_DATA_GPU_RESET_REQUIRED 0:0 +#define NV_MSGBOX_DATA_GPU_RESET_REQUIRED_OFF 0x00000000 +#define NV_MSGBOX_DATA_GPU_RESET_REQUIRED_ON 0x00000001 +#define NV_MSGBOX_DATA_GPU_DRAIN_AND_RESET_RECOMMENDED 1:1 +#define NV_MSGBOX_DATA_GPU_DRAIN_AND_RESET_RECOMMENDED_NO 0x00000000 +#define NV_MSGBOX_DATA_GPU_DRAIN_AND_RESET_RECOMMENDED_YES 0x00000001 + +/** + * Response to + * NV_MSGBOX_CMD_ARG1_GET_CLOCK_FREQ_INFO_PAGE_3 + */ +#define NV_MSGBOX_DATA_GET_CLOCK_FREQ_INFO_PAGE_3_CURRENT_PSTATE 3:0 +#define NV_MSGBOX_DATA_GET_CLOCK_FREQ_INFO_PAGE_3_CURRENT_PSTATE_INVALID 0x0000000F + +/* + * Number of Nvlink data outputs (dataOut, extData) for + * NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_LINK queries + */ +#define NV_MSGBOX_DATA_NVLINK_INFO_DATA_WIDTH 2 + +/* + * Encoding for Invalid data + */ +#define NV_MSGBOX_DATA_NVLINK_INFO_DATA_INVALID 0xFFFFFFFF + +/* Response to NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_LINK_STATE_V1 */ +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V1__SIZE 32 +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V1_DOWN 0x00000000 +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V1_UP 0x00000001 +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V1_INVALID 0x000000ff + +/* Response to NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_LINK_STATE_V2 */ +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2(i) (3+(i)*4):(0+(i)*4) +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2__SIZE 8 +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2_OFF 0x00000000 +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2_SAFE 0x00000001 +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2_ACTIVE 0x00000002 +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2_ERROR 0x00000003 +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2_INVALID 0x000000ff + +/* Response to NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_LINK_BANDWIDTH (in Mps) */ +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_BANDWIDTH__SIZE 1 +#define NV_MSGBOX_DATA_NVLINK_LINE_RATE_INVALID 0xFFFFFFFF +#define NV_MSGBOX_DATA_NVLINK_LINE_RATE_00000_MBPS 0 +#define NV_MSGBOX_DATA_NVLINK_LINE_RATE_16000_MBPS 16000 +#define NV_MSGBOX_DATA_NVLINK_LINE_RATE_19200_MBPS 19200 +#define NV_MSGBOX_DATA_NVLINK_LINE_RATE_20000_MBPS 20000 +#define NV_MSGBOX_DATA_NVLINK_LINE_RATE_25000_MBPS 25000 +#define NV_MSGBOX_DATA_NVLINK_LINE_RATE_25781_MBPS 25781 +#define NV_MSGBOX_DATA_NVLINK_LINE_RATE_32000_MBPS 32000 +#define NV_MSGBOX_DATA_NVLINK_LINE_RATE_40000_MBPS 40000 +#define NV_MSGBOX_DATA_NVLINK_LINE_RATE_50000_MBPS 50000 +#define NV_MSGBOX_DATA_NVLINK_LINE_RATE_53125_MBPS 53125 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_SUBLINK_WIDTH */ +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_WIDTH(i) (5+(i)*6):(0+(i)*6) +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_WIDTH__SIZE 5 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_WIDTH_INVALID 0x000000ff +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_TX_WIDTH 2:0 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_TX_WIDTH_0 0x00000000 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_TX_WIDTH_1 0x00000001 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_TX_WIDTH_2 0x00000002 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_TX_WIDTH_4 0x00000003 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_TX_WIDTH_8 0x00000004 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_TX_WIDTH_INVALID 0x00000007 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_RX_WIDTH 5:3 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_RX_WIDTH_0 0x00000000 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_RX_WIDTH_1 0x00000001 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_RX_WIDTH_2 0x00000002 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_RX_WIDTH_4 0x00000003 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_RX_WIDTH_8 0x00000004 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_RX_WIDTH_INVALID 0x00000007 + +/* + * Response to NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_TRAINING_ERR_STATE + * NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_RUNTIME_ERR_STATE + */ +#define NV_MSGBOX_DATA_NVLINK_INFO_ERROR_STATE__SIZE 32 +#define NV_MSGBOX_DATA_NVLINK_INFO_ERROR_STATE_INVALID 0x000000ff +#define NV_MSGBOX_DATA_NVLINK_INFO_ERROR_STATE_NO_ERROR 0x00000000 +#define NV_MSGBOX_DATA_NVLINK_INFO_ERROR_STATE_ERROR 0x00000001 + +/* Respones to NV_MSGBOX_CMD_ARG2_REMAP_ROW_RAW_CNT_COMBINED */ +#define NV_MSGBOX_DATA_REMAP_ROW_UNCORR_CNT 10:0 +#define NV_MSGBOX_DATA_REMAP_ROW_UNCORR_CNT_EXCESS 11:11 +#define NV_MSGBOX_DATA_REMAP_ROW_UNCORR_CNT_EXCESS_FALSE 0 +#define NV_MSGBOX_DATA_REMAP_ROW_UNCORR_CNT_EXCESS_TRUE 1 +#define NV_MSGBOX_DATA_REMAP_ROW_CORR_CNT 22:12 +#define NV_MSGBOX_DATA_REMAP_ROW_CORR_CNT_EXCESS 23:23 +#define NV_MSGBOX_DATA_REMAP_ROW_CORR_CNT_EXCESS_FALSE 0 +#define NV_MSGBOX_DATA_REMAP_ROW_CORR_CNT_EXCESS_TRUE 1 + +/* Response to NV_MSGBOX_CMD_ARG1_REMAP_ROWS_STATE_FLAGS */ +#define NV_MSGBOX_DATA_REMAP_ROW_STATE_FLAGS_PAGE0_FAILED_REMAPPING 0:0 +#define NV_MSGBOX_DATA_REMAP_ROW_STATE_FLAGS_PAGE0_FAILED_REMAPPING_FALSE 0 +#define NV_MSGBOX_DATA_REMAP_ROW_STATE_FLAGS_PAGE0_FAILED_REMAPPING_TRUE 1 +#define NV_MSGBOX_DATA_REMAP_ROW_STATE_FLAGS_PAGE0_PENDING_REMAPPING 1:1 +#define NV_MSGBOX_DATA_REMAP_ROW_STATE_FLAGS_PAGE0_PENDING_REMAPPING_FALSE 0 +#define NV_MSGBOX_DATA_REMAP_ROW_STATE_FLAGS_PAGE0_PENDING_REMAPPING_TRUE 1 + +/* Response to NV_MSGBOX_CMD_ARG1_REMAP_ROWS_HISTOGRAM */ +#define NV_MSGBOX_DATA_REMAP_ROW_HISTOGRAM_LOW_AVAILABILITY 15:0 +#define NV_MSGBOX_DATA_REMAP_ROW_HISTOGRAM_PARTIAL_AVAILABILITY 31:16 + +/* Respones to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_0 */ +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_SPEED 2:0 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_SPEED_UNKNOWN 0x00000000 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_SPEED_2500_MTPS 0x00000001 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_SPEED_5000_MTPS 0x00000002 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_SPEED_8000_MTPS 0x00000003 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_SPEED_16000_MTPS 0x00000004 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_SPEED_32000_MTPS 0x00000005 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_WIDTH 6:4 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_WIDTH_UNKNOWN 0x00000000 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_WIDTH_X1 0x00000001 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_WIDTH_X2 0x00000002 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_WIDTH_X4 0x00000003 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_WIDTH_X8 0x00000004 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_WIDTH_X16 0x00000005 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_WIDTH_X32 0x00000006 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_NONFATAL_ERROR_COUNT 15:8 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_FATAL_ERROR_COUNT 23:16 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_UNSUPP_REQ_COUNT 31:24 + +/* Respones to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_1 */ +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_1_L0_TO_RECOVERY_COUNT 31:0 + +/* Respones to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_2 */ +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_2_REPLAY_ROLLOVER_COUNT 15:0 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_2_NAKS_RCVD_COUNT 31:16 + +/* + * Input for NV_MSGBOX_CMD_OPCODE_GPU_PERFORMANCE_MONITORING. Value is valid + * only if Arg2 != GPM_PARTITION_AGGREGATE and Arg2.Bit7 == 1 + */ +#define NV_MSGBOX_DATA_GPM_COMPUTE_INSTANCE_INDEX 15:8 + +/* + * The following three fields correspond to the data which is interpreted + * differently depending on GPM Metric specified in Arg1. + */ +#define NV_MSGBOX_DATA_GPM_NVLINK_INDEX 7:0 +#define NV_MSGBOX_DATA_GPM_NVDEC_INSTANCE 7:0 +#define NV_MSGBOX_DATA_GPM_NVJPG_INSTANCE 7:0 + +/* MSGBOX Extended Data Register */ +#define NV_MSGBOX_EXT_DATA_REG 31:0 + +/* Respones to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_0 */ +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_0_CORRECTABLE_ERROR_COUNT 15:0 + +/* Respones to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_1 */ +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_1_REPLAY_COUNT 31:0 + +/* Respones to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_2 */ +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_2_NAKS_SENT_COUNT 15:0 + +/* Respones to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_3 */ +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED 2:0 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_UNKNOWN 0x00000000 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_2500_MTPS 0x00000001 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_5000_MTPS 0x00000002 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_8000_MTPS 0x00000003 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_16000_MTPS 0x00000004 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_32000_MTPS 0x00000005 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_RESERVED 2:0 + +/* Response to NV_MSGBOX_CMD_ARG1_REMAP_ROWS_HISTOGRAM */ +#define NV_MSGBOX_EXT_DATA_REMAP_ROW_HISTOGRAM_MAX_AVAILABILITY 31:16 +#define NV_MSGBOX_EXT_DATA_REMAP_ROW_HISTOGRAM_HIGH_AVAILABILITY 15:0 + +/* SysId info per type sizes */ +#define NV_MSGBOX_SYSID_DATA_SIZE_BOARD_PART_NUM_V1 24 +#define NV_MSGBOX_SYSID_DATA_SIZE_OEM_INFO_V1 24 +#define NV_MSGBOX_SYSID_DATA_SIZE_SERIAL_NUM_V1 16 +#define NV_MSGBOX_SYSID_DATA_SIZE_MARKETING_NAME_V1 24 +#define NV_MSGBOX_SYSID_DATA_SIZE_GPU_PART_NUM_V1 16 +#define NV_MSGBOX_SYSID_DATA_SIZE_MEMORY_VENDOR_V1 1 +#define NV_MSGBOX_SYSID_DATA_SIZE_MEMORY_PART_NUM_V1 20 +#define NV_MSGBOX_SYSID_DATA_SIZE_BUILD_DATE_V1 4 +#define NV_MSGBOX_SYSID_DATA_SIZE_FIRMWARE_VER_V1 14 +#define NV_MSGBOX_SYSID_DATA_SIZE_VENDOR_ID_V1 2 +#define NV_MSGBOX_SYSID_DATA_SIZE_DEV_ID_V1 2 +#define NV_MSGBOX_SYSID_DATA_SIZE_SUB_VENDOR_ID_V1 2 +#define NV_MSGBOX_SYSID_DATA_SIZE_SUB_ID_V1 2 +#define NV_MSGBOX_SYSID_DATA_SIZE_GPU_GUID_V1 16 +#define NV_MSGBOX_SYSID_DATA_SIZE_INFOROM_VER_V1 16 +#define NV_MSGBOX_SYSID_DATA_SIZE_PRODUCT_LENGTH_V1 4 +#define NV_MSGBOX_SYSID_DATA_SIZE_PRODUCT_WIDTH_V1 4 +#define NV_MSGBOX_SYSID_DATA_SIZE_PRODUCT_HEIGHT_V1 4 +#define NV_MSGBOX_SYSID_DATA_SIZE_PCIE_SPEED_V1 1 +#define NV_MSGBOX_SYSID_DATA_SIZE_PCIE_WIDTH_V1 1 + +/*! + * Response to NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_CLK + * 16-bit frequency in MHz + */ +#define NV_MSGBOX_DATA_POWER_HINT_INFO_CLK_GR_MIN 15:0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_CLK_GR_MAX 31:16 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_CLK_MEM_MIN 15:0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_CLK_MEM_MAX 31:16 + +/*! + * Response to NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_TEMP + * 16-bit frequency in MHz + */ +#define NV_MSGBOX_DATA_POWER_HINT_INFO_TEMP_MIN 15:0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_TEMP_MAX 31:16 + +/*! + * Response to _ARG1_GET_POWER_HINT_INFO_PROFILES, 1 page consists of data and + * ext data, then we can support up to 256 profiles + * Bit index represents profile ID + */ +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_DMMA_PERF 0:0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_DMMA_PERF_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_DMMA_PERF_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_DMMA_HIGH_K 1:1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_DMMA_HIGH_K_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_DMMA_HIGH_K_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_DMMA_LOW_K 2:2 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_DMMA_LOW_K_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_DMMA_LOW_K_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_HMMA 3:3 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_HMMA_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_HMMA_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_IMMA 4:4 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_IMMA_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_IMMA_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_SGEMM 5:5 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_SGEMM_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_SGEMM_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_TRANSFORMER 6:6 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_TRANSFORMER_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_TRANSFORMER_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_0 7:7 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_0_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_0_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_1 8:8 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_1_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_1_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_2 9:9 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_2_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_2_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_3 10:10 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_3_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_3_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_4 11:11 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_4_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_4_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_5 12:12 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_5_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_5_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_6 13:13 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_6_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_6_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_7 14:14 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_7_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_7_AVAILABLE 1 + +#define NV_MSGBOX_DATA_DYN_SYS_INFO_SIZE_DRIVER_VERSION 64 + +/* Event types */ +typedef enum +{ + NV_MSGBOX_EVENT_TYPE_SERVER_RESTART_COLD = 0, + NV_MSGBOX_EVENT_TYPE_GPU_RESET_REQUIRED, + NV_MSGBOX_EVENT_TYPE_DRIVER_ERROR_MESSAGE_OLDEST, + NV_MSGBOX_EVENT_TYPE_TGP_LIMIT_SET_SUCCESS, + NV_MSGBOX_EVENT_TYPE_CLOCK_LIMIT_SET_SUCCESS, + NV_MSGBOX_EVENT_TYPE_ECC_TOGGLE_SUCCESS, + NV_MSGBOX_EVENT_TYPE_MIG_TOGGLE_SUCCESS, + NV_MSGBOX_EVENT_TYPE_SERVER_RESTART_WARM, + NV_MSGBOX_EVENT_TYPE_DRIVER_ERROR_MESSAGE_NEW, + NV_MSGBOX_NUM_EVENTS, /* insert new event types before this line */ +} NvMsgboxEventType; + +/* Legacy event names for compatipility */ +#define NV_MSGBOX_EVENT_TYPE_SERVER_RESTART NV_MSGBOX_EVENT_TYPE_SERVER_RESTART_COLD +#define NV_MSGBOX_EVENT_TYPE_DRIVER_ERROR_MESSAGE NV_MSGBOX_EVENT_TYPE_DRIVER_ERROR_MESSAGE_OLDEST + +/* Bit mask of all defined events */ +#define NV_MSGBOX_EVENT_TYPE__ALL (NVBIT(NV_MSGBOX_NUM_EVENTS) - 1) + +/* ----------------------- Set Master Capabilities ---------------------------- */ + +// +// SET_MASTER_CAPS +// +// Descripiton: +// Set/declare SMBPBI Master capabilities. +// +// Common Encoding: +// 7 0 7 0 +// .-+-+-+-+-+-+-+-. .-+-+-+-+-+-+-+-. +// | CLASS | ARG1 | CAP_INDEX | ARG2 +// `-+-+-+-+-+-+-+-' `-+-+-+-+-+-+-+-' +// +// The SMBPBI Master capabilities are logically grouped into classes (specified +// in arg1). Capabilities are sent 32 at a time (dword index stored in arg2) +// per-class (typically once during system-initialization). +// +// Classes: +// _GPU_REQ - Class of capability bits corresponding 1:1 with the GPU- +// Request opcodes the master supports. +// +#define NV_MSGBOX_CMD_SET_MASTER_CAPS_ARG1_CLASS 7:0 +#define NV_MSGBOX_CMD_SET_MASTER_CAPS_ARG1_CLASS_GPU_REQ 0x00000000 + +#define NV_MSGBOX_DATA_MASTER_CAPS_GPU_REQ_COUNT 1 + +#define NV_MSGBOX_DATA_MASTER_CAPS_GPU_REQ_0 31:0 +#define NV_MSGBOX_DATA_MASTER_CAPS_GPU_REQ_0_CPU_PCONTROL 0:0 +#define NV_MSGBOX_DATA_MASTER_CAPS_GPU_REQ_0_CPU_PCONTROL_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_MASTER_CAPS_GPU_REQ_0_CPU_PCONTROL_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_MASTER_CAPS_GPU_REQ_0_SYS_PCONTROL 1:1 +#define NV_MSGBOX_DATA_MASTER_CAPS_GPU_REQ_0_SYS_PCONTROL_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_MASTER_CAPS_GPU_REQ_0_SYS_PCONTROL_AVAILABLE 0x00000001 + +/* ------------------ GPU Performance Control (PCONTROL) ---------------------- */ + +// +// GPU_PCONTROL arg1, arg2, and data encoding (fields are relative to zero, not +// relative to their position in the COMMAND/DATA registers). +// + +// +// ARG1/ARG2 Encoding +// +// 7 3 2 0 7 0 +// .-+-+-+-+-+-+-+-. .-+-+-+-+-+-+-+-. +// | TARGET | ACT | ARG1 |0 0 0 0 0 0 0 0| ARG2 (reserved) +// `-+-+-+-+-+-+-+-' `-+-+-+-+-+-+-+-' +// +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG1_ACTION 2:0 +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG1_ACTION_GET_INFO 0x00000000 +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG1_ACTION_GET_LIMIT 0x00000001 +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG1_ACTION_SET_LIMIT 0x00000002 +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG1_ACTION_GET_STATUS 0x00000003 +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG1_TARGET 7:3 +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG1_TARGET_VPSTATE 0x00000000 +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG1_TARGET_POWER_SMBIDX 0x00000001 +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG2_RSVD 7:0 + +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG1_SET_ACTION(arg1, action) \ + (arg1) = FLD_SET_DRF(_MSGBOX_CMD, _GPU_PCONTROL_ARG1, _ACTION, \ + action, (arg1)) + +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG1_GET_ACTION(arg1) \ + DRF_VAL(_MSGBOX_CMD, _GPU_PCONTROL_ARG1, _ACTION, (arg1)) + +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG1_SET_TARGET(arg1, target) \ + (arg1) = FLD_SET_DRF(_MSGBOX_CMD, _GPU_PCONTROL_ARG1, _TARGET, \ + target, (arg1)) + +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG1_GET_TARGET(arg1) \ + DRF_VAL(_MSGBOX_CMD, _GPU_PCONTROL_ARG1, _TARGET, (arg1)) + +// +// Getting GPU vPstate Information +// +// Inputs: +// ARG1 - {TARGET=VPSTATE, ACTION=GET_INFO} +// ARG2 - Unused/reserved (must be zero) +// +// Outputs: +// DATA - Current min/max range of externally available vpstates +// (vPmin=fastest, vPmax=slowest) +// +// Encoding: +// 31 16 15 8 7 0 +// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-. +// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| MIN | MAX | DATA +// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' +// +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_INFO_MAX 7:0 +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_INFO_MIN 15:8 +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_INFO_RSVD 31:16 + +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_INFO_SET_MAX(data, max) \ + (data) = FLD_SET_DRF_NUM(_MSGBOX_CMD, _GPU_PCONTROL_DATA, \ + _VPSTATE_GET_INFO_MAX, (max), (data)) + +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_INFO_GET_MAX(data) \ + DRF_VAL(_MSGBOX_CMD, _GPU_PCONTROL_DATA, _VPSTATE_GET_INFO_MAX, (data)) + +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_INFO_SET_MIN(data, min) \ + (data) = FLD_SET_DRF_NUM(_MSGBOX_CMD, _GPU_PCONTROL_DATA, \ + _VPSTATE_GET_INFO_MIN, (min), (data)) + +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_INFO_GET_MIN(data) \ + DRF_VAL(_MSGBOX_CMD, _GPU_PCONTROL_DATA, _VPSTATE_GET_INFO_MIN, (data)) + +// +// Getting GPU vPstate Limits +// +// Inputs: +// ARG1 - {TARGET=VPSTATE, ACTION=GET_LIMIT} +// ARG2 - Unused/reserved (must be zero) +// +// Outputs: +// DATA - Last requested vpstate limit/value, zero when no limit has been set. +// +// Encoding: +// 31 8 7 0 +// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-. +// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| VALUE | DATA +// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' +// +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_LIMIT_VALUE 7:0 +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_LIMIT_RSVD 31:8 + +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_LIMIT_SET_VALUE(data, value) \ + (data) = FLD_SET_DRF_NUM(_MSGBOX_CMD, _GPU_PCONTROL_DATA, \ + _VPSTATE_GET_LIMIT_VALUE, (value), (data)) + +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_LIMIT_GET_VALUE(data) \ + DRF_VAL(_MSGBOX_CMD, _GPU_PCONTROL_DATA, _VPSTATE_GET_LIMIT_VALUE, (data)) + +// +// Setting GPU vPstate Limits: +// +// Inputs: +// ARG1 - {TARGET=VPSTATE, ACTION=SET_LIMIT} +// ARG2 - Unused/reserved (must be zero) +// DATA - Desired vpstate limit/value between vPmin and vPmax (inclusive), +// zero to clear active limits. +// Outputs: +// none +// +// Encoding: +// 31 8 7 0 +// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-. +// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| VALUE | DATA +// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' +// +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_SET_LIMIT_VALUE 7:0 +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_SET_LIMIT_VALUE_CLEAR 0x00000000 +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_SET_LIMIT_VALUE_INIT 0x00000000 +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_SET_LIMIT_RSVD 31:8 + +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_SET_LIMIT_SET_VALUE(data, limit) \ + (data) = FLD_SET_DRF_NUM(_MSGBOX_CMD, _GPU_PCONTROL_DATA, \ + _VPSTATE_SET_LIMIT_VALUE, (limit), (data)) + +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_SET_LIMIT_GET_VALUE(data) \ + DRF_VAL(_MSGBOX_CMD, _GPU_PCONTROL_DATA, _VPSTATE_SET_LIMIT_VALUE, (data)) + +// +// Getting GPU vPstate Status +// +// Inputs: +// ARG1 - {TARGET=VPSTATE, ACTION=GET_STATUS} +// ARG2 - Unused/reserved (must be zero) +// +// Outputs: +// DATA - Current vPstate +// +// Encoding: +// 31 8 7 0 +// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-. +// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CURRENT | DATA +// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' +// +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_STATUS_CURRENT 7:0 +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_STATUS_RSVD 31:8 + +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_STATUS_SET_CURRENT(data, curr) \ + (data) = FLD_SET_DRF_NUM(_MSGBOX_CMD, _GPU_PCONTROL_DATA, \ + _VPSTATE_GET_STATUS_CURRENT, (curr), (data)) + +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_STATUS_GET_CURRENT(data) \ + DRF_VAL(_MSGBOX_CMD, _GPU_PCONTROL_DATA, _VPSTATE_GET_STATUS_CURRENT, (data)) + + +/* ------------------------- GPU System Control ------------------------------- */ + +// +// GPU_SYSCONTROL +// +// Description: +// Command sent to the GPU to set/remove a system-imposed operating limit +// on a specific system-parameter. +// +// Common Encoding: +// 7 2 1 0 7 0 +// .-+-+-+-+-+-+-+-. .-+-+-+-+-+-+-+-. +// | TARGET |ACT| ARG1 |0 0 0 0 0 0 0 0| ARG2 (reserved) +// `-+-+-+-+-+-+-+-' `-+-+-+-+-+-+-+-' +// +// Notes: +// - TARGET accepts NV0000_CTRL_SYSTEM_PARAM_* definitions +// - arg1, arg2, and data encoding (fields are relative to zero, not relative +// to their position in the DATA_OUT register). +// +#define NV_MSGBOX_CMD_GPU_SYSCONTROL_ARG1_ACTION 1:0 +#define NV_MSGBOX_CMD_GPU_SYSCONTROL_ARG1_ACTION_CLEAR_LIMIT 0x00000000 +#define NV_MSGBOX_CMD_GPU_SYSCONTROL_ARG1_ACTION_SET_LIMIT 0x00000001 +#define NV_MSGBOX_CMD_GPU_SYSCONTROL_ARG1_TARGET 7:2 +#define NV_MSGBOX_CMD_GPU_SYSCONTROL_ARG2_RSVD 7:0 + +#define NV_MSGBOX_CMD_GPU_SYSCONTROL_ARG1_SET_ACTION(arg1, action) \ + (arg1) = FLD_SET_DRF(_MSGBOX_CMD, _GPU_SYSCONTROL_ARG1, _ACTION, \ + action, (arg1)) + +#define NV_MSGBOX_CMD_GPU_SYSCONTROL_ARG1_GET_ACTION(arg1) \ + DRF_VAL(_MSGBOX_CMD, _GPU_SYSCONTROL_ARG1, _ACTION, (arg1)) + +#define NV_MSGBOX_CMD_GPU_SYSCONTROL_ARG1_SET_TARGET(arg1, target) \ + (arg1) = FLD_SET_DRF_NUM(_MSGBOX_CMD, _GPU_SYSCONTROL_ARG1, _TARGET, \ + target, (arg1)) + +#define NV_MSGBOX_CMD_GPU_SYSCONTROL_ARG1_GET_TARGET(arg1) \ + DRF_VAL(_MSGBOX_CMD, _GPU_SYSCONTROL_ARG1, _TARGET, (arg1)) + +// +// Setting a System-Parameter Operating-Limit: +// +// Inputs: +// ARG1 - {TARGET=NV_MSGBOX_SYS_PARAM_*, ACTION=SET_LIMIT} +// ARG2 - Unused/reserved (must be zero) +// DATA - Desired limit/value. +// +// Outputs: +// none +// +// Encoding: +// 31 0 +// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-. +// | VALUE | DATA +// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' +// +#define NV_MSGBOX_CMD_GPU_SYSCONTROL_DATA_SET_LIMIT_VALUE 31:0 + +#define NV_MSGBOX_CMD_GPU_SYSCONTROL_DATA_SET_LIMIT_SET_VALUE(data, limit) \ + (data) = FLD_SET_DRF_NUM(_MSGBOX_CMD, _GPU_SYSCONTROL_DATA, \ + _SET_LIMIT_VALUE, (limit), (data)) + +#define NV_MSGBOX_CMD_GPU_SYSCONTROL_DATA_PARAM_SET_LIMIT_GET_VALUE(data) \ + DRF_VAL(_MSGBOX_CMD, _GPU_SYSCONTROL_DATA, _SET_LIMIT_VALUE, (data)) + +// +// Host side scratch memory buffer +// This memory buffer is allocated by the host CPU in its system memory +// and is used for passing additional arguments and results, that don't +// fit in the command/status and data registers due to their size. +// This memory can be accessed by the BMC SMBus master through +// dedicated requests. +// +// Page size is various on different SMBPBI servers. +// Capability dword[2] bit 12 shows size in bytes +// +// _1024 --> 0xFF dwords +// _256 --> 0x40 dowrds +// +#define NV_MSGBOX_SCRATCH_PAGE_SIZE_1024_D 0xFF +#define NV_MSGBOX_SCRATCH_PAGE_SIZE_256_D 0x40 + +// +// TODO Once switch soc/pmu/oobtest remove the reference to this, this will be +// removed. +// +#define NV_MSGBOX_SCRATCH_PAGE_SIZE 1024 +#define NV_MSGBOX_SCRATCH_NUM_PAGES_P 2 // expressed as a power of 2 + // must be >= 2 + +// This cap code plugs into NV_MSGBOX_DATA_CAP_2_NUM_SCRATCH_BANKS +#define NV_MSGBOX_SCRATCH_NUM_PAGES_CAP_CODE \ + (NV_MSGBOX_SCRATCH_NUM_PAGES_P > 0 ? \ + NV_MSGBOX_SCRATCH_NUM_PAGES_P - 1 : 0) + +#define NV_MSGBOX_SCRATCH_NUM_PAGES (1 << NV_MSGBOX_SCRATCH_NUM_PAGES_P) +#define NV_MSGBOX_SCRATCH_BUFFER_SIZE (NV_MSGBOX_SCRATCH_NUM_PAGES \ + * NV_MSGBOX_SCRATCH_PAGE_SIZE) + +// Auxiliary definitions related to NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_STATE_SPEED +#define NV_MSGBOX_NVLINK_STATE_BITS_PER_NVLINK 4 +#define NV_MSGBOX_NVLINK_STATE_NVLINKS_PER_REGISTER (32 / NV_MSGBOX_NVLINK_STATE_BITS_PER_NVLINK) +#define NV_MSGBOX_NVLINK_STATE_NUM_NVLINKS_VOLTA 6 +#define NV_MSGBOX_NVLINK_STATE_NUM_NVLINKS_TURING 2 +#define NV_MSGBOX_NVLINK_STATE_NUM_NVLIPT_GA100 3 +#define NV_MSGBOX_NVLINK_STATE_NUM_LINKS_PER_NVLIPT_NVL30 4 +#define NV_MSGBOX_NVLINK_SUBLINK_WIDTH_MAX_NVL30 4 +#define NV_MSGBOX_NVLINK_STATE_NUM_NVLINKS_GA100 \ + (NV_MSGBOX_NVLINK_STATE_NUM_NVLIPT_GA100 * \ + NV_MSGBOX_NVLINK_STATE_NUM_LINKS_PER_NVLIPT_NVL30) +#define NV_MSGBOX_NVLINK_STATE_NUM_NVLIPT_GA10X 1 +#define NV_MSGBOX_NVLINK_STATE_NUM_NVLINKS_GA10X \ + (NV_MSGBOX_NVLINK_STATE_NUM_NVLIPT_GA10X * \ + NV_MSGBOX_NVLINK_STATE_NUM_LINKS_PER_NVLIPT_NVL30) +#define NV_MSGBOX_NVLINK_STATE_NUM_NVLIPT_LR10 9 +#define NV_MSGBOX_NVLINK_STATE_NUM_NVLINKS_LR10 \ + (NV_MSGBOX_NVLINK_STATE_NUM_NVLIPT_LR10 * \ + NV_MSGBOX_NVLINK_STATE_NUM_LINKS_PER_NVLIPT_NVL30) +#define NV_MSGBOX_NVLINK_STATE_NUM_REGISTERS(arch) \ + ((NV_MSGBOX_NVLINK_STATE_NUM_NVLINKS##arch + NV_MSGBOX_NVLINK_STATE_NVLINKS_PER_REGISTER - 1) \ + / NV_MSGBOX_NVLINK_STATE_NVLINKS_PER_REGISTER) + +// Auxiliary definitions related to NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_THROUGHPUT_* +#define NV_MSGBOX_NVLINK_THROUGHPUT_COUNTER_INDEX_DATA_TX 0x00000000 +#define NV_MSGBOX_NVLINK_THROUGHPUT_COUNTER_INDEX_DATA_RX 0x00000001 +#define NV_MSGBOX_NVLINK_THROUGHPUT_COUNTER_INDEX_RAW_TX 0x00000002 +#define NV_MSGBOX_NVLINK_THROUGHPUT_COUNTER_INDEX_RAW_RX 0x00000003 +#define NV_MSGBOX_NVLINK_THROUGHPUT_COUNTER_INDEX_MAX 0x00000004 + +#if !defined(NV_MSGBOX_NO_PARAM_STRUCTS) +// +// Parameter structures for asynchronous requests +// passed in scratch space +// + +/*! + * This structure is used to hold parameters for + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_CONTROL_GET and + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_CONTROL_SET + */ +typedef struct +{ + NvU32 flags; + /*! + * If flags:_PERSIST is _ON, make limitCurrInput persistent, + * surviving the driver reload and the system reboot. + * + * If flags:_CLEAR is _ON, it will clear the TGP limit. The + * persistence still depends on persist flag. + */ +#define NV_MSGBOX_PMGR_PWR_TGP_LIMIT_CONTROL_PARAMS_FLAGS_PERSIST 0:0 +#define NV_MSGBOX_PMGR_PWR_TGP_LIMIT_CONTROL_PARAMS_FLAGS_PERSIST_OFF 0x00000000 +#define NV_MSGBOX_PMGR_PWR_TGP_LIMIT_CONTROL_PARAMS_FLAGS_PERSIST_ON 0x00000001 +#define NV_MSGBOX_PMGR_PWR_TGP_LIMIT_CONTROL_PARAMS_FLAGS_CLEAR 1:1 +#define NV_MSGBOX_PMGR_PWR_TGP_LIMIT_CONTROL_PARAMS_FLAGS_CLEAR_OFF 0x00000000 +#define NV_MSGBOX_PMGR_PWR_TGP_LIMIT_CONTROL_PARAMS_FLAGS_CLEAR_ON 0x00000001 + + /*! + * Current total GPU power limit value to enforce, requested by the + * SMBPBI client, expressed in milliwatts. + * Must always be within range imposed by the current policy. + * 0xffffffff is returned, if the limit has not been set by the SMBPBI client. + */ + NvU32 limitCurrInput; + + /*! + * Currently arbitrated total GPU power limit value after taking + * into account limits, requested by all clients, expressed + * in milliwatts. + */ + NvU32 limitCurrOutput; +} NV_MSGBOX_PMGR_PWR_TGP_LIMIT_CONTROL_PARAMS; + +/*! + * This structure is used to hold parameters for + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_INFO_GET + */ +typedef struct +{ + /*! + * Current total GPU power limit lower and upper bounds and the + * default setting, expressed in milliwatts. + * These constraints must be observed, when the limit + * is being set with + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_CONTROL_SET. + */ + NvU32 limitMin; + NvU32 limitMax; + NvU32 limitDefault; +} NV_MSGBOX_PMGR_PWR_TGP_LIMIT_INFO_PARAMS; + +/*! + * This structure is used to hold parameters for + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_THERMAL_FAN_V1_COUNT_GET + */ +typedef struct +{ + NvU32 fanCount; // POLICY - add types below +#define NV_MSGBOX_VIOLATION_COUNTERS_TYPE_ALL_SUPPORTED_POLICIES 0xFFFFFFFF //-1 represents All Supported policies +#define NV_MSGBOX_VIOLATION_COUNTERS_TYPE_HW_VIOLATION 0 +#define NV_MSGBOX_VIOLATION_COUNTERS_TYPE_SW_GLOBAL_VIOLATION 1 +#define NV_MSGBOX_VIOLATION_COUNTERS_TYPE_SW_POWER_VIOLATION 2 +#define NV_MSGBOX_VIOLATION_COUNTERS_TYPE_SW_THERMAL_VIOLATION 3 + + NV_DECLARE_ALIGNED(NvU64 violationTime[32], 8); //. + */ +typedef struct +{ + NvU32 flags; + /*! + * If flags: _CLEAR is _ON, it will clear the limits. Otherwise, + * set the clock limits. + * + * If flags: _PERSIST is _ON, set/clear limits persistently, + * surviving the driver reload and the system reboot. + * + */ +#define NV_MSGBOX_OOB_CLOCK_LIMIT_CTRL_PARAMS_FLAGS_PERSIST 0:0 +#define NV_MSGBOX_OOB_CLOCK_LIMIT_CTRL_PARAMS_FLAGS_PERSIST_OFF 0x00000000 +#define NV_MSGBOX_OOB_CLOCK_LIMIT_CTRL_PARAMS_FLAGS_PERSIST_ON 0x00000001 +#define NV_MSGBOX_OOB_CLOCK_LIMIT_CTRL_PARAMS_FLAGS_CLEAR 1:1 +#define NV_MSGBOX_OOB_CLOCK_LIMIT_CTRL_PARAMS_FLAGS_CLEAR_OFF 0x00000000 +#define NV_MSGBOX_OOB_CLOCK_LIMIT_CTRL_PARAMS_FLAGS_CLEAR_ON 0x00000001 + + /*! + * Graphics clock limit in MHz + */ + NvU32 clkMinFreqMHz; + NvU32 clkMaxFreqMHz; +} NV_MSGBOX_OOB_CLOCK_LIMIT_CTRL_PARAMS; + +/* + * Parameters for NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_TEST_MESSAGE_SEND + */ +#define NV_MSGBOX_TEST_MESSAGE_SEND_STRING_SIZE_MAX 32 +/* + * If the message starts with this character, the message + * will not be sent to the kernel. + */ +#define NV_MSGBOX_TEST_MESSAGE_SEND_SILENT_CHAR '@' +typedef struct +{ + NvU8 string[NV_MSGBOX_TEST_MESSAGE_SEND_STRING_SIZE_MAX]; +} NV_MSGBOX_TEST_MESSAGE_SEND_PARAMS; + +/* + * Individual request structure definition for bundled requests + */ +typedef struct +{ + NvU32 cmdStatus; //. + */ +typedef struct { + /*! + * Graphics clock limit in MHz + * if there is no cap, return + * NV_MSGBOX_CLOCK_LIMIT_GET_PARAMS_CLOCK_LIMIT_NOT_SET + */ + NvU16 oobClientMin; + NvU16 oobClientMax; + NvU16 enforcedMin; + NvU16 enforcedMax; +#define NV_MSGBOX_CLOCK_LIMIT_GET_PARAMS_CLOCK_LIMIT_NOT_SET 0xffff +} NV_MSGBOX_CLOCK_LIMIT_GET_PARAMS; + +/*! + * This structure is used to hold parameters for + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_DEVICE_MODE_CONTROL + */ +typedef struct +{ + NvU16 modeType; //> 7) \ + ) +#define NV_MSGBOX_ECC_V5_COUNTS_NUM_ENTRIES 600 + +#define NV_MSGBOX_CMD_ECC_V5_CNT_HDR_META(index) \ + ( \ + NV_MSGBOX_CMD_ECC_V5_CNT(index) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_COUNTS_TYPE, _HDR_META) \ + ) + +#define NV_MSGBOX_CMD_ECC_V5_CNT_REGN_CORRECTED_TOTAL(index) \ + ( \ + NV_MSGBOX_CMD_ECC_V5_CNT(index) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_COUNTS_TYPE, _REGN_CORRECTED_TOTAL) \ + ) + +#define NV_MSGBOX_CMD_ECC_V5_CNT_REGN_CORRECTED_UNIQUE(index) \ + ( \ + NV_MSGBOX_CMD_ECC_V5_CNT(index) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_COUNTS_TYPE, _REGN_CORRECTED_UNIQUE) \ + ) + +#define NV_MSGBOX_CMD_ECC_V5_CNT_REGN_UNCORRECTED_TOTAL(index) \ + ( \ + NV_MSGBOX_CMD_ECC_V5_CNT(index) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_COUNTS_TYPE, _REGN_UNCORRECTED_TOTAL) \ + ) + +#define NV_MSGBOX_CMD_ECC_V5_CNT_REGN_UNCORRECTED_UNIQUE(index) \ + ( \ + NV_MSGBOX_CMD_ECC_V5_CNT(index) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_COUNTS_TYPE, _REGN_UNCORRECTED_UNIQUE) \ + ) + +#define NV_MSGBOX_CMD_ECC_V5_CNT_ADDR_ADDR(index) \ + ( \ + NV_MSGBOX_CMD_ECC_V5_CNT(index) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_COUNTS_TYPE, _ADDR_ADDR) \ + ) + +#define NV_MSGBOX_CMD_ECC_V5_CNT_ADDR_UNCORRECTED_COUNTS(index) \ + ( \ + NV_MSGBOX_CMD_ECC_V5_CNT(index) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_COUNTS_TYPE, _ADDR_UNCORRECTED_COUNTS) \ + ) + +#define NV_MSGBOX_CMD_ECC_V5_CNT_ADDR_CORRECTED_TOTAL(index) \ + ( \ + NV_MSGBOX_CMD_ECC_V5_CNT(index) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_COUNTS_TYPE, _ADDR_CORRECTED_TOTAL) \ + ) + +#define NV_MSGBOX_CMD_ECC_V5_CNT_ADDR_CORRECTED_UNIQUE(index) \ + ( \ + NV_MSGBOX_CMD_ECC_V5_CNT(index) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_COUNTS_TYPE, _ADDR_CORRECTED_UNIQUE) \ + ) + +#define NV_MSGBOX_CMD_ECC_V5_ERR_BUF(index) \ + ( \ + NV_MSGBOX_CMD(_GET_ECC_V5, 0, 0) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG1_ECC_V5_SEL, _ERR_BUFFER) | \ + DRF_NUM(_MSGBOX, _CMD, _ARG1_ECC_V5_ERR_BUF_INDEX, (index)) \ + ) +#define NV_MSGBOX_ECC_V5_ERR_BUF_NUM_ENTRIES 16 + +#define NV_MSGBOX_CMD_ECC_V5_ERR_BUF_ERR_TYPE_META(index) \ + ( \ + NV_MSGBOX_CMD_ECC_V5_ERR_BUF(index) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_ERR_BUF_TYPE, _ERR_TYPE_META) \ + ) + +#define NV_MSGBOX_CMD_ECC_V5_ERR_BUF_TIME_STAMP(index) \ + ( \ + NV_MSGBOX_CMD_ECC_V5_ERR_BUF(index) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_ERR_BUF_TYPE, _TIME_STAMP) \ + ) + +#define NV_MSGBOX_CMD_ECC_V5_ERR_BUF_ADDR(index) \ + ( \ + NV_MSGBOX_CMD_ECC_V5_ERR_BUF(index) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_ERR_BUF_TYPE, _ADDR) \ + ) + +#define NV_MSGBOX_CMD_SET_COPY_DATA(cmd) \ + ( \ + FLD_SET_DRF(_MSGBOX, _CMD, _COPY_DATA, _ON, (cmd)) \ + ) + +#define NV_MSGBOX_CMD_GPM_GET_METRIC(type, metric, partition) \ + ( \ + NV_MSGBOX_CMD(_GPU_PERFORMANCE_MONITORING, 0, 0) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_ACTION, type) | \ + DRF_NUM(_MSGBOX, _CMD, _ARG1_GPM_METRIC, metric) | \ + DRF_NUM(_MSGBOX, _CMD, _ARG2_GPM_PARTITION, partition) \ + ) + +#define NV_MSGBOX_CMD_GPM_SET_MULTIPLIER(multiplier) \ + ( \ + NV_MSGBOX_CMD(_GPU_PERFORMANCE_MONITORING, 0, 0) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_ACTION, _SET_MULTIPLIER) | \ + DRF_NUM(_MSGBOX, _CMD, _ARG2_GPM_MULTIPLIER, (multiplier)) \ + ) + +#define NV_MSGBOX_GET_CMD_OPCODE(cmd) DRF_VAL(_MSGBOX, _CMD, _OPCODE, (cmd)) +#define NV_MSGBOX_GET_CMD_ARG1(cmd) DRF_VAL(_MSGBOX, _CMD, _ARG1 , (cmd)) +#define NV_MSGBOX_GET_CMD_ARG2(cmd) DRF_VAL(_MSGBOX, _CMD, _ARG2 , (cmd)) +#define NV_MSGBOX_GET_CMD_STATUS(cmd) DRF_VAL(_MSGBOX, _CMD, _STATUS, (cmd)) +#define NV_MSGBOX_CMD_IS_COPY_DATA_SET(cmd) \ + FLD_TEST_DRF(_MSGBOX, _CMD, _COPY_DATA, _ON, (cmd)) + +#define NV_MSGBOX_CAP_IS_AVAILABLE(caps, idx, name) \ + !(FLD_TEST_DRF(_MSGBOX, _DATA_CAP_##idx, name, _NOT_AVAILABLE, (caps)[idx])) + +#define NV_MSGBOX_CAP_SET_AVAILABLE(caps, idx, name) \ + (caps)[idx] = FLD_SET_DRF(_MSGBOX, _DATA_CAP_##idx, name, _AVAILABLE, \ + (caps)[idx]) + +/******************************************************************************** + * * + * GPU REQUESTS * + * * + ********************************************************************************/ + +// +// Encoding: +// 31 24 23 16 15 8 7 0 +// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-. +// | REQUEST ID | ARG2 | ARG1 | OPCODE | DATA_OUT +// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' +// +#define NV_MSGBOX_REQ_OPCODE 7:0 +#define NV_MSGBOX_REQ_OPCODE_CPU_PCONTROL 0x00000000 +#define NV_MSGBOX_REQ_OPCODE_SYS_PCONTROL 0x00000001 +#define NV_MSGBOX_REQ_ARG1 15:8 +#define NV_MSGBOX_REQ_ARG2 23:16 +#define NV_MSGBOX_REQ_REQUEST_ID 31:24 +#define NV_MSGBOX_REQ(opcode, arg1, arg2, requestId) \ + ( \ + DRF_NUM(_MSGBOX, _REQ, _OPCODE , (opcode)) | \ + DRF_NUM(_MSGBOX, _REQ, _ARG1 , (arg1)) | \ + DRF_NUM(_MSGBOX, _REQ, _ARG2 , (arg2)) | \ + DRF_NUM(_MSGBOX, _REQ, _REQUEST_ID, (requestId)) \ + ) + +/* ---------------- CPU Performance Control (PCONTROL) ------------------------ */ + +// +// CPU_PCONTROL +// +// Description: +// GPU-Request used to retrieve information and control various aspects of +// CPU performance. +// +// Common Encoding: +// 7 3 2 0 +// .-+-+-+-+-+-+-+-. +// | TARGET | ACT | ARG1 +// `-+-+-+-+-+-+-+-' +// +// Notes: +// arg1, arg2, and data encoding (fields are relative to zero, not relative +// to their position in the DATA_OUT register). +// +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG1_ACTION 2:0 +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG1_ACTION_RSVD1 0x00000000 +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG1_ACTION_RSVD2 0x00000001 +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG1_ACTION_SET_LIMIT 0x00000002 +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG1_TARGET 7:3 +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG1_TARGET_PSTATE 0x00000000 + +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG1_SET_ACTION(arg1, action) \ + (arg1) = FLD_SET_DRF(_MSGBOX_REQ, _CPU_PCONTROL_ARG1, _ACTION, \ + action, (arg1)) + +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG1_GET_ACTION(arg1) \ + DRF_VAL(_MSGBOX_REQ, _CPU_PCONTROL_ARG1, _ACTION, (arg1)) + +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG1_SET_TARGET(arg1, target) \ + (arg1) = FLD_SET_DRF(_MSGBOX_REQ, _CPU_PCONTROL_ARG1, _TARGET, \ + target, (arg1)) + +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG1_GET_TARGET(arg1) \ + DRF_VAL(_MSGBOX_REQ, _CPU_PCONTROL_ARG1, _TARGET, (arg1)) + +// +// Setting CPU Pstate Limits: +// +// Inputs: +// ARG1 - {TARGET=PSTATE, ACTION=SET_LIMIT} +// ARG2 - Stores desired CPU Pstate limit +// +// Outputs: +// none +// +// Encoding: +// 7 3 2 0 7 0 +// .-+-+-+-+-+-+-+-. .-+-+-+-+-+-+-+-. +// | TARGET | ACT | ARG1 | VALUE | ARG2 +// `-+-+-+-+-+-+-+-' `-+-+-+-+-+-+-+-' +// +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG2_PSTATE_SET_LIMIT_VALUE 7:0 + +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG2_PSTATE_SET_LIMIT_SET_VALUE(arg2, limit) \ + (arg2) = FLD_SET_DRF_NUM(_MSGBOX_REQ, _CPU_PCONTROL_ARG2, \ + _PSTATE_SET_LIMIT_VALUE, (limit), (arg2)) + +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG2_PSTATE_SET_LIMIT_GET_VALUE(arg2) \ + DRF_VAL(_MSGBOX_REQ, _CPU_PCONTROL_ARG2, _PSTATE_SET_LIMIT_VALUE, (arg2)) + +/* ----------------------- System Performance Control ------------------------- */ + +// +// SYS_PCONTROL +// +// Description: +// GPU-Request used to retrieve information and control various aspects of +// system-performance. +// +// Common Encoding: +// 7 3 2 0 7 0 +// .-+-+-+-+-+-+-+-. .-+-+-+-+-+-+-+-. +// | TARGET | ACT | ARG1 |0 0 0 0 0 0 0 0| ARG2 (reserved) +// `-+-+-+-+-+-+-+-' `-+-+-+-+-+-+-+-' +// +// Notes: +// - TARGET accepts NV0000_CTRL_SYSTEM_PARAM_* definitions +// - arg1, arg2, and data encoding (fields are relative to zero, not relative +// to their position in the DATA_OUT register). +// +#define NV_MSGBOX_REQ_SYS_PCONTROL_ARG1_ACTION 2:0 +#define NV_MSGBOX_REQ_SYS_PCONTROL_ARG1_ACTION_GET_STATUS 0x00000000 +#define NV_MSGBOX_REQ_SYS_PCONTROL_ARG1_ACTION_GET_LIMIT 0x00000001 +#define NV_MSGBOX_REQ_SYS_PCONTROL_ARG1_TARGET 7:3 +#define NV_MSGBOX_REQ_SYS_PCONTROL_ARG2_RSVD 7:0 + +#define NV_MSGBOX_REQ_SYS_PCONTROL_ARG1_SET_ACTION(arg1, action) \ + (arg1) = FLD_SET_DRF(_MSGBOX_REQ, _SYS_PCONTROL_ARG1, _ACTION, \ + action, (arg1)) + +#define NV_MSGBOX_REQ_SYS_PCONTROL_ARG1_GET_ACTION(arg1) \ + DRF_VAL(_MSGBOX_REQ, _SYS_PCONTROL_ARG1, _ACTION, (arg1)) + +#define NV_MSGBOX_REQ_SYS_PCONTROL_ARG1_SET_TARGET(arg1, target) \ + (arg1) = FLD_SET_DRF_NUM(_MSGBOX_REQ, _SYS_PCONTROL_ARG1, _TARGET, \ + (target), (arg1)) + +#define NV_MSGBOX_REQ_SYS_PCONTROL_ARG1_GET_TARGET(arg1) \ + DRF_VAL(_MSGBOX_REQ, _SYS_PCONTROL_ARG1, _TARGET, (arg1)) + +#endif /* _SMBPBI_H */ diff --git a/userspace/sdks/nv525/nvalloc/common/inc/oob/smbpbi_impl.h b/userspace/sdks/nv525/nvalloc/common/inc/oob/smbpbi_impl.h new file mode 100644 index 0000000..e7052c8 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/oob/smbpbi_impl.h @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef _SMBPBI_IMPL_H +#define _SMBPBI_IMPL_H +/*! + * This header file stores implementation dependent parameters of the SMBPBI server. + */ + +/*! + * Maximum number of individual requests in a bundle + */ +#define NV_MSGBOX_PARAM_MAX_BUNDLE_SIZE 4 + +/*! + * Maximum number of Result Disposition Rules + */ +#define NV_MSGBOX_PARAM_MAX_DISP_RULES 10 + +/*! + * Maximum length of the Driver Event Message text string is 80, including + * the terminating NUL character. + */ +#define NV_MSGBOX_MAX_DRIVER_EVENT_MSG_TXT_SIZE 80 + +#endif // _SMBPBI_IMPL_H diff --git a/userspace/sdks/nv525/nvalloc/common/inc/oob/smbpbi_priv.h b/userspace/sdks/nv525/nvalloc/common/inc/oob/smbpbi_priv.h new file mode 100644 index 0000000..2055aeb --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/oob/smbpbi_priv.h @@ -0,0 +1,79 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _SMBPBI_PRIV_H_ +#define _SMBPBI_PRIV_H_ + +/*! + * This file contains NVIDIA private defines for the SMBPBI + * interface. + */ + +#include "oob/smbpbi.h" + +// MSGBOX command word structure + +// +// Reserving opcodes above 0xC0 for internal/private functionationality. +// +// These opcodes should not be included in any documentation we release outside +// of NVIDIA! +// + +// +// Only for internal use (should not be written to the command register). Used +// for internal tracking when commands are redirected to the RM from the PMU. +// +#define NV_MSGBOX_CMD_ERR_MORE_PROCESSING_REQUIRED 0x000000F0 + +// +// Alternative encodings of the command word +// These are distinguished by a non-zero value in the 29:29 bit, +// previously known as _RSVD. +// +#define NV_MSGBOX_CMD_ENCODING 29:29 +#define NV_MSGBOX_CMD_ENCODING_STANDARD 0x00000000 +#define NV_MSGBOX_CMD_ENCODING_DEBUG 0x00000001 + +// Debug command structure +#define NV_MSGBOX_DEBUG_CMD_OPCODE 1:0 +#define NV_MSGBOX_DEBUG_CMD_OPCODE_READ_PRIV 0x00000000 + +#define NV_MSGBOX_DEBUG_CMD_ARG 23:2 + +/* Utility command constructor macros */ + +#define NV_MSGBOX_DEBUG_CMD(opcode, arg) \ + ( \ + DRF_DEF(_MSGBOX, _DEBUG_CMD, _OPCODE, opcode) | \ + DRF_NUM(_MSGBOX, _DEBUG_CMD, _ARG, (arg)) | \ + DRF_DEF(_MSGBOX, _CMD, _STATUS, _NULL) | \ + DRF_DEF(_MSGBOX, _CMD, _ENCODING, _DEBUG) | \ + DRF_DEF(_MSGBOX, _CMD, _INTR, _PENDING) \ + ) + +#define NV_MSGBOX_DEBUG_CMD_READ_PRIV(offset) \ + NV_MSGBOX_DEBUG_CMD(_READ_PRIV, (offset) >> 2) + +#endif // _SMBPBI_PRIV_H_ + diff --git a/userspace/sdks/nv525/nvalloc/common/inc/rmRiscvUcode.h b/userspace/sdks/nv525/nvalloc/common/inc/rmRiscvUcode.h new file mode 100644 index 0000000..22a4c88 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/rmRiscvUcode.h @@ -0,0 +1,89 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * << DO NOT EDIT >> + * + * This file describes the format of generated ucode binary. Please do not change the + * content unless the same change is applied to the target ucode builds. + */ + +#ifndef RM_RISCV_UCODE_H +#define RM_RISCV_UCODE_H + +#include "nvtypes.h" + +typedef struct { + // + // Version 1 + // Version 2 + // Version 3 = for Partition boot + // Version 4 = for eb riscv boot + // Version 5 = Support signing entire RISC-V image as "code" in code section for hopper and later. + // + NvU32 version; // structure version + NvU32 bootloaderOffset; + NvU32 bootloaderSize; + NvU32 bootloaderParamOffset; + NvU32 bootloaderParamSize; + NvU32 riscvElfOffset; + NvU32 riscvElfSize; + NvU32 appVersion; // Changelist number associated with the image + // + // Manifest contains information about Monitor and it is + // input to BR + // + NvU32 manifestOffset; + NvU32 manifestSize; + // + // Monitor Data offset within RISCV image and size + // + NvU32 monitorDataOffset; + NvU32 monitorDataSize; + // + // Monitor Code offset withtin RISCV image and size + // + NvU32 monitorCodeOffset; + NvU32 monitorCodeSize; + NvU32 bIsMonitorEnabled; + // + // Swbrom Code offset within RISCV image and size + // + NvU32 swbromCodeOffset; + NvU32 swbromCodeSize; + // + // Swbrom Data offset within RISCV image and size + // + NvU32 swbromDataOffset; + NvU32 swbromDataSize; + // + // Total size of FB carveout (image and reserved space). + // + NvU32 fbReservedSize; + // + // Indicates whether the entire RISC-V image is signed as "code" in code section. + // + NvU32 bSignedAsCode; +} RM_RISCV_UCODE_DESC; + +#endif // RM_RISCV_UCODE_H diff --git a/userspace/sdks/nv525/nvalloc/common/inc/rmflcnbl.h b/userspace/sdks/nv525/nvalloc/common/inc/rmflcnbl.h new file mode 100644 index 0000000..7a49306 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/rmflcnbl.h @@ -0,0 +1,147 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * Data structures and interfaces used for generic falcon boot-loader. + * + * This generic boot-loader is designed to load both non-secure and + * secure code taking care of signature as well. This bootloader + * should be loaded at the end of the IMEM so that it doesnt overwrite + * itself when it tries to load the code into IMEM starting at blk 0. + * The data will be loaded into DMEM offset 0. + */ + +#ifndef RMFLCNBL_H +#define RMFLCNBL_H + +#include "flcnifcmn.h" + +/*! + * @brief Structure used by the boot-loader to load the rest of the code. + * + * This has to be filled by the GPU driver and copied into DMEM at offset + * provided in the @ref _def_rm_flcn_bl_desc.blDmemDescLoadOff. + */ +typedef struct _def_rm_flcn_bl_dmem_desc +{ + /*! + * reserved should be always first element + */ + NvU32 reserved[4]; + /*! + * signature should follow reserved 16B signature for secure code. + * 0s if no secure code + */ + NvU32 signature[4]; + /*! + * ctxDma is used by the bootloader while loading code/data. + */ + NvU32 ctxDma; + /*! + * 256B aligned physical FB address where code is located. + */ + RM_FLCN_U64 codeDmaBase; + /*! + * Offset from codeDmaBase where the nonSecure code is located. + * The offset must be multiple of 256 to help performance. + */ + NvU32 nonSecureCodeOff; + /*! + * The size of the nonSecure code part. + */ + NvU32 nonSecureCodeSize; + /*! + * Offset from codeDmaBase where the secure code is located. + * The offset must be multiple of 256 to help performance. + */ + NvU32 secureCodeOff; + /*! + * The size of the ecure code part. + */ + NvU32 secureCodeSize; + /*! + * Code entry point which will be invoked by BL after code is loaded. + */ + NvU32 codeEntryPoint; + /*! + * 256B aligned Physical FB Address where data is located. + */ + RM_FLCN_U64 dataDmaBase; + /*! + * Size of data block. Should be multiple of 256B. + */ + NvU32 dataSize; + /*! + * Arguments to be passed to the target firmware being loaded. + */ + NvU32 argc; + /*! + * Number of arguments to be passed to the target firmware being loaded. + */ + NvU32 argv; +} RM_FLCN_BL_DMEM_DESC, *PRM_FLCN_BL_DMEM_DESC; + +/*! + * @brief The header used by the GPU driver to figure out code and data + * sections of bootloader. + */ +typedef struct _def_rm_flcn_bl_img_header +{ + /*! + * Offset of code section in the image. + */ + NvU32 blCodeOffset; + /*! + * Size of code section in the image. + */ + NvU32 blCodeSize; + /*! + * Offset of data section in the image. + */ + NvU32 blDataOffset; + /*! + * Size of data section in the image. + */ + NvU32 blDataSize; +} RM_FLCN_BL_IMG_HEADER, *PRM_FLCN_BL_IMG_HEADER; + +/*! + * @brief The descriptor used by RM to figure out the requirements of boot loader. + */ +typedef struct _def_rm_flcn_bl_desc +{ + /*! + * Starting tag of bootloader + */ + NvU32 blStartTag; + /*! + * Dmem offset where _def_rm_flcn_bl_dmem_desc to be loaded + */ + NvU32 blDmemDescLoadOff; + /*! + * Description of the image + */ + RM_FLCN_BL_IMG_HEADER blImgHeader; +} RM_FLCN_BL_DESC, *PRM_FLCN_BL_DESC; + +#endif // RMFLCNBL_H diff --git a/userspace/sdks/nv525/nvalloc/common/inc/rmgspseq.h b/userspace/sdks/nv525/nvalloc/common/inc/rmgspseq.h new file mode 100644 index 0000000..cee7e65 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/rmgspseq.h @@ -0,0 +1,202 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * Top-level header-file that defines the GSP sequencer structures + */ + +#ifndef _RMGSPSEQ_H_ +#define _RMGSPSEQ_H_ + +/*! + * GSP sequencer structures and defines + * + * Here are the supported opcodes. + * the sequencer buffer is a stream of commands composed of + * an op-code directly followed by the exact number of arguments it needs. + * + * The supported op-codes are: + * GSP_SEQUENCER_BUFFER_OPCODE_REG_WRITE: + * arg[0]: the register offset + * arg[1]: the register value + * + * GSP_SEQUENCER_BUFFER_OPCODE_REG_MODIFY: + * arg[0]: the register offset + * arg[1]: the mask where to apply the modification + * arg[2]: the value to apply. The value needs to be shifted to fit inside the mask, + * + * GSP_SEQUENCER_BUFFER_OPCODE_REG_POLL: + * arg[0]: the register offset + * arg[1]: the mask where to apply the modification + * arg[2]: the value to apply. The value needs to be shifted to fit inside the mask. + * arg[3]: the timeout in MS + * arg[4]: an unique error code from GSP_SEQUENCER_BUFFER_ERR. Helps map to the failing GSP code. + * + * GSP_SEQUENCER_BUFFER_OPCODE_DELAY_US + * arg[0]: the delay in micoseconds. + * + * GSP_SEQUENCER_REG_STORE + * This operation stores the specified register at the specified index in + * the sequencer buffer register storage area. + * arg[0]: the reg offset to store in the save area + * arg[1]: index in save area to store value of reg offset + * + * GSP_SEQUENCER_CORE_RESET + * This operation resets the core. This operation takes no arguments. + * + * GSP_SEQUENCER_CORE_START + * This operation starts the core. This operation takes no arguments. + * + * GSP_SEQUENCER_CORE_WAIT_FOR_HALT + * This operation waits for the core to halt after completing execution. + * This operation takes no arguments. + * + * GSP_SEQUENCER_CORE_RESUME + * This operation resumes the core in preparation for switching back to + * the GSP-RM. + */ +typedef enum GSP_SEQ_BUF_OPCODE +{ + GSP_SEQ_BUF_OPCODE_REG_WRITE = 0, + GSP_SEQ_BUF_OPCODE_REG_MODIFY, + GSP_SEQ_BUF_OPCODE_REG_POLL, + GSP_SEQ_BUF_OPCODE_DELAY_US, + GSP_SEQ_BUF_OPCODE_REG_STORE, + GSP_SEQ_BUF_OPCODE_CORE_RESET, + GSP_SEQ_BUF_OPCODE_CORE_START, + GSP_SEQ_BUF_OPCODE_CORE_WAIT_FOR_HALT, + GSP_SEQ_BUF_OPCODE_CORE_RESUME, +} GSP_SEQ_BUF_OPCODE; + +#define GSP_SEQUENCER_PAYLOAD_SIZE_DWORDS(opcode) \ + ((opcode == GSP_SEQ_BUF_OPCODE_REG_WRITE) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_REG_WRITE) / sizeof(NvU32)) : \ + (opcode == GSP_SEQ_BUF_OPCODE_REG_MODIFY) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_REG_MODIFY) / sizeof(NvU32)) : \ + (opcode == GSP_SEQ_BUF_OPCODE_REG_POLL) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_REG_POLL) / sizeof(NvU32)) : \ + (opcode == GSP_SEQ_BUF_OPCODE_DELAY_US) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_DELAY_US) / sizeof(NvU32)) : \ + (opcode == GSP_SEQ_BUF_OPCODE_REG_STORE) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_REG_STORE) / sizeof(NvU32)) : \ + /* GSP_SEQ_BUF_OPCODE_CORE_RESET */ \ + /* GSP_SEQ_BUF_OPCODE_CORE_START */ \ + /* GSP_SEQ_BUF_OPCODE_CORE_WAIT_FOR_HALT */ \ + /* GSP_SEQ_BUF_OPCODE_CORE_RESUME */ \ + 0) + +// The size of the structure must be DWord aligned! +typedef struct +{ + NvU32 addr; + NvU32 val; +} GSP_SEQ_BUF_PAYLOAD_REG_WRITE; + +// The size of the structure must be DWord aligned! +typedef struct +{ + NvU32 addr; + NvU32 mask; + NvU32 val; +} GSP_SEQ_BUF_PAYLOAD_REG_MODIFY; + +// The size of the structure must be DWord aligned! +typedef struct +{ + NvU32 addr; + NvU32 mask; + NvU32 val; + NvU32 timeout; + NvU32 error; +} GSP_SEQ_BUF_PAYLOAD_REG_POLL; + +// The size of the structure must be DWord aligned! +typedef struct +{ + NvU32 val; +} GSP_SEQ_BUF_PAYLOAD_DELAY_US; + +// The size of the structure must be DWord aligned! +typedef struct +{ + NvU32 addr; + NvU32 index; +} GSP_SEQ_BUF_PAYLOAD_REG_STORE; + +typedef struct GSP_SEQUENCER_BUFFER_CMD +{ + GSP_SEQ_BUF_OPCODE opCode; + union + { + GSP_SEQ_BUF_PAYLOAD_REG_WRITE regWrite; + GSP_SEQ_BUF_PAYLOAD_REG_MODIFY regModify; + GSP_SEQ_BUF_PAYLOAD_REG_POLL regPoll; + GSP_SEQ_BUF_PAYLOAD_DELAY_US delayUs; + GSP_SEQ_BUF_PAYLOAD_REG_STORE regStore; + } payload; +} GSP_SEQUENCER_BUFFER_CMD; + +// +// These error codes printed by the client help us +// see to which GSP uCode line it corresponds. +// +typedef enum GSP_SEQUENCER_BUFFER_ERR +{ + GSP_SEQUENCER_BUFFER_ERR_OK = 0, + GSP_SEQUENCER_BUFFER_ERR_TIMEOUT1, + GSP_SEQUENCER_BUFFER_ERR_TIMEOUT2, + GSP_SEQUENCER_BUFFER_ERR_TIMEOUT3 +} GSP_SEQUENCER_BUFFER_ERR; + + +// Sequencer implementation of FLD_WR_DRF_DEF() +#define GSP_SEQ_FLD_WR_DRF_DEF(gpu, gsp, d, r, f, c) \ +{ \ + GSP_SEQUENCER_BUFFER_CMD cmd; \ + cmd.opCode = GSP_SEQ_BUF_OPCODE_REG_MODIFY; \ + cmd.payload.regModify.addr = NV##d##r; \ + cmd.payload.regModify.mask = DRF_MASK(NV##d##r##f) << DRF_SHIFT(NV##d##r##f); \ + cmd.payload.regModify.val = DRF_DEF(d, r, f, c); \ + (void)gspAppendToSequencerBuffer(gpu, gsp, &cmd); \ +} + +/*! + * Forward references + */ +struct rpc_run_cpu_sequencer_v17_00; + +/*! + * Structure tracking all information relevant to GSP sequencer bufferfor GSP-RM + */ +typedef struct +{ + /*! Pointer to RM-GSP CPU sequencer parameter block */ + struct rpc_run_cpu_sequencer_v17_00 *pRunCpuSeqParam; +} GSP_SEQUENCER_BUFFER; + +/*! + * RM-GSP sequencer buffer register macros. + * GSP_SEQ_BUF_REG_SAVE_SIZE : specifies size of save area in reg values + * GSP_SEQ_BUF_REG_SAVE_MAILBOX0 : index for saving of mailbox0 reg + * GSP_SEQ_BUF_REG_SAVE_MAILBOX1 : index for saving of mailbox1 reg + */ +#define GSP_SEQ_BUF_REG_SAVE_SIZE (8) +#define GSP_SEQ_BUF_REG_SAVE_MAILBOX0 (0) +#define GSP_SEQ_BUF_REG_SAVE_MAILBOX1 (1) + +#endif // _RMGSPSEQ_H_ diff --git a/userspace/sdks/nv525/nvalloc/common/inc/rmifrif.h b/userspace/sdks/nv525/nvalloc/common/inc/rmifrif.h new file mode 100644 index 0000000..048fcf8 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/rmifrif.h @@ -0,0 +1,124 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2012 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _RMIFRIF_H_ +#define _RMIFRIF_H_ + +/*! + * @file rmifrif.h + * @brief Defines structures and interfaces common between RM and + * Init-From-Rom (IFR). + * + * For systems supporting GC6 that have on-board VBIOS ROMs, IFR is used + * to expedite several parts of GC6 exit in parallel with PEX init. + * + * After running devinit using a PMU ucode image loaded from the ROM itself, + * parts of RM stateLoad can be done using RM's ucode image. This is + * achieved by loading RM PMU ucode directly from FB. The primary difficulties + * are how to find RM's PMU ucode and how to bootstrap it. + * + * We use the simple approach of allocating a fixed buffer near the + * top of FB that contains the information required to bootstrap RM's PMU + * image. This buffer is called the RM_IFR_GC6_CTX. + * + * The buffer is allocated within RM's reserved memory space, directly before + * the VBIOS workspace (if any is present). Since the VBIOS workspace is + * always a multiple of 64K, RM enforces that the offset between top of memory + * and the end of the buffer is 64K. This way the IFR code can start + * from the top of memory and search downwards in 64K decrements. + * + * A small header is placed at the end of the buffer which contains a + * string signature identifying the buffer and other data needed to find the + * remaining context data. + * + * Top_Of-FB /---------------------\ <- + * | | \ + * | (VBIOS_Workspace) | | END_OFFSET + * | | / + * |---------------------| <- + | | \ + * | GSP FW (if present) | | pFbHalPvtInfo->gspFwSizeBytes + * | | / + * |---------------------| <- + * | RM_IFR_GC6_CTX_HDR | \ + * |---------------------| | + * | (Padding) | | RM_IFR_GC6_CTX_HDR.bufferSize + * |---------------------| | + * | Sequence Data | / + * |---------------------| <- + * | | + * | | + * | | + * | | + * 0x00000000 \---------------------/ + * + * To simplify the RM PMU bootstrap process and decrease IFR maintainence + * cost, the bootstrap process is encoded as a sequence script, leveraging + * a small subset of RM's PMU_SEQ_INST interface (see pmuseqinst.h). + * Register writes are captured during the initial (CPU-driven) RM PMU bootstrap + * and saved into a sequence for replay during GC6 exit. + * + * Only the following opcodes are supported currently: + * NV_PMU_SEQ_WRITE_REG_OPC - (multi-)register write + * NV_PMU_SEQ_EXIT_OPC - sequence done + * + */ + +/*! + * Header structure which identifies the GC6 context buffer. + */ +typedef struct +{ + NvU8 signature[12]; // RM_IFR_GC6_CTX_SIGNATURE + NvU32 bufferSize; // Size of the entire context buffer in bytes + NvU32 seqSizeWords; // Number of 32-bit words of sequence data + NvU32 checksum; // 32-bit chunk checksum of the sequence data +} RM_IFR_GC6_CTX_HDR, *PRM_IFR_GC6_CTX_HDR; + +/*! + * String signature that IFR searches for to find the GC6 context buffer. + */ +#define RM_IFR_GC6_CTX_SIGNATURE "GC6_CTX_HDR" // 12 bytes + +/*! + * Alignment of the offset between top of memory and the end of the + * GC6 context buffer (which is also the end of the header). + */ +#define RM_IFR_GC6_CTX_END_OFFSET_ALIGNMENT 0x10000 // 64KB + +/*! + * Maximum offset between top of memory and the end of the + * GC6 context buffer. This is meant to be a loose upper bound preventing + * scanning of the whole of memory (e.g. when something goes wrong). + */ +#define RM_IFR_GC6_CTX_END_OFFSET_MAX 0x1000000 // 16MB +#define RM_IFR_GC6_CTX_END_OFFSET_MAX_WITH_GSP 0x10000000 // 256MB + +/*! + * Maximum size of the context data in bytes. + * This is limited by FECS falcon DMEM size (4K on Kepler). + * The buffer must fit within DMEM together with stack and other global data. + */ +#define RM_IFR_GC6_CTX_DATA_MAX_SIZE 2048 // 2KB + +#endif // _RMIFRIF_H_ diff --git a/userspace/sdks/nv525/nvalloc/common/inc/rmlsfm.h b/userspace/sdks/nv525/nvalloc/common/inc/rmlsfm.h new file mode 100644 index 0000000..2e71260 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/rmlsfm.h @@ -0,0 +1,525 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef RMLSFM_H +#define RMLSFM_H + +/*****************************************************************************/ +/* This file is shared between ACR, SEC2 Binaries */ +/* Do not update this file without updating ACR/SEC2 */ +/*****************************************************************************/ + +/*! + * @file rmlsfm.h + * @brief Top-level header-file that defines Light Secure Falcon Managment + SW shared interfaces. + */ + +/*! + * READ/WRITE masks for WPR region + */ +#define LSF_WPR_REGION_RMASK (0xCU) // Readable only from level 2 and 3 client +#define LSF_WPR_REGION_WMASK (0xCU) // Writable only from level 2 and 3 client +#define LSF_WPR_REGION_RMASK_SUB_WPR_ENABLED (0x8) // Readable only from level 3 client +#define LSF_WPR_REGION_WMASK_SUB_WPR_ENABLED (0x8) // Writable only from level 3 client +#define LSF_WPR_REGION_ALLOW_READ_MISMATCH_NO (0x0) // Disallow read mis-match for all clients +#define LSF_WPR_REGION_ALLOW_WRITE_MISMATCH_NO (0x0) // Disallow write mis-match for all clients + +/*! + * READ mask for WPR region on Tegra + * This is required until we update tegra binaries, Bug 200281517 + * TODO: dgoyal - Remove this once tegra binaries are updated + */ +#define LSF_WPR_REGION_RMASK_FOR_TEGRA (0xFU) + +/*! + * Expected REGION ID to be used for the unprotected FB region (region that + * does not have read or write protections) + */ +#define LSF_UNPROTECTED_REGION_ID (0x0U) + +/*! + * Expected REGION ID to be used for the WPR region for the falcon microcode (includes data). + * ACR allots client requests to each region based on read/write masks and it is supposed + * to provide first priority to requests from LSFM. Providing first priority will naturally assign + * region ID 1 to LSFM and this define will provide a way for different parties to sanity check + * this fact. Also there are other falcons (FECS/video falcons) which depends on this define, so please + * be aware while modifying this. + */ +#define LSF_WPR_EXPECTED_REGION_ID (0x1U) + +/*! + * Expected REGION ID to be used for the unused WPR region. + */ +#define LSF_WPR_UNUSED_REGION_ID (0x2U) + +/*! + * Invalid LS falcon subWpr ID + */ +#define LSF_SUB_WPR_ID_INVALID (0xFFFFFFFFU) + +/*! + * Expected REGION ID to be used for the VPR region. + */ +#define LSF_VPR_REGION_ID (0x3U) + +/*! + * Size of the separate bootloader data that could be present in WPR region. + */ +#define LSF_LS_BLDATA_EXPECTED_SIZE (0x100U) + +/*! + * since we dont check signatures in GC6 exit, we need to hardcode the WPR offset + */ +#define LSF_WPR_EXPECTED_OFFSET (0x0U) + +/*! + * CTXDMA to be used while loading code/data in target falcons + */ +#define LSF_BOOTSTRAP_CTX_DMA_FECS (0x0) + +/*! + * Context DMA ID 6 is reserved for Video UCODE + */ +#define LSF_BOOTSTRAP_CTX_DMA_VIDEO (0x6) +#define LSF_BOOTSTRAP_CTX_DMA_BOOTSTRAP_OWNER (0x0) +#define LSF_BOOTSTRAP_CTX_DMA_FBFLCN (0x0) + +/*! + * Falcon Id Defines + * Defines a common Light Secure Falcon identifier. + * Codesigning infra. assumes LSF_FALCON_ID_ prefix for units, + * Changes to the define needs to be reflected in path [1] + * For new Falcon Id adding, we need to append to the end; + * don't insert the new falcon Id in the middle. + */ +#define LSF_FALCON_ID_PMU (0U) +#define LSF_FALCON_ID_DPU (1U) +#define LSF_FALCON_ID_GSPLITE LSF_FALCON_ID_DPU +#define LSF_FALCON_ID_FECS (2U) +#define LSF_FALCON_ID_GPCCS (3U) +#define LSF_FALCON_ID_NVDEC (4U) +#define LSF_FALCON_ID_NVENC (5U) +#define LSF_FALCON_ID_NVENC0 (5U) +#define LSF_FALCON_ID_NVENC1 (6U) +#define LSF_FALCON_ID_SEC2 (7U) +#define LSF_FALCON_ID_NVENC2 (8U) +#define LSF_FALCON_ID_MINION (9U) +#define LSF_FALCON_ID_FBFALCON (10U) +#define LSF_FALCON_ID_XUSB (11U) +#define LSF_FALCON_ID_GSP_RISCV (12U) +#define LSF_FALCON_ID_PMU_RISCV (13U) +#define LSF_FALCON_ID_SOE (14U) +#define LSF_FALCON_ID_NVDEC1 (15U) +#define LSF_FALCON_ID_OFA (16U) +#define LSF_FALCON_ID_SEC2_RISCV (17U) +#define LSF_FALCON_ID_NVDEC_RISCV (18U) +#define LSF_FALCON_ID_NVDEC_RISCV_EB (19U) +#define LSF_FALCON_ID_NVJPG (20U) +#define LSF_FALCON_ID_END (21U) + +#define LSF_FALCON_ID_INVALID (0xFFFFFFFFU) + +// +// ************************ NOTIFICATION ********************************* +// In case anyone needs to add new LSF falconId, please must calculate +// WPR header size per LSF_FALCON_ID_END. RM needs to call lsfmGetWprHeaderSizeMax_HAL +// to align with acrReadSubWprHeader_HAL in ACR. Otherwise, ACR can't get correct +// address to read sub wpr headers. +// We observer in case LSF_FALCON_ID_END > 32 will cause SEC2 IMEM tag missing error; +// but don't get the root cause yet. +// +#define LSF_FALCON_ID_END_15 (15U) +#define LSF_FALCON_ID_END_17 (17U) +#define LSF_FALCON_ID_END_18 (18U) +#define LSF_FALCON_ID_END_21 (21U) + +#define LSF_FALCON_INSTANCE_DEFAULT_0 (0x0) +#define LSF_FALCON_INSTANCE_COUNT_DEFAULT_1 (0x1) + +// Currently max supported instance is 8 for FECS/GPCCS SMC +#define LSF_FALCON_INSTANCE_FECS_GPCCS_MAX (0x8) +#define LSF_FALCON_INSTANCE_INVALID (0xFFFFFFFFU) +#define LSF_FALCON_INDEX_MASK_DEFAULT_0 (0x0) + + + +/*! + * Size in entries of the ucode descriptor's dependency map. + * This used to be LSF_FALCON_ID_END, but since that had to grow and we did not want to break any + * existing binaries, they had to be split. + * + * Increasing this number should be done with care. + */ +#define LSF_FALCON_DEPMAP_SIZE (11) + +/*! + * Falcon Binaries version defines + */ +#define LSF_FALCON_BIN_VERSION_INVALID (0xFFFFFFFFU) + + +/*! + * Light Secure Falcon Ucode Description Defines + * This stucture is prelim and may change as the ucode signing flow evolves. + */ +typedef struct +{ + NvU8 prdKeys[2][16]; + NvU8 dbgKeys[2][16]; + NvU32 bPrdPresent; + NvU32 bDbgPresent; + NvU32 falconId; + NvU32 bSupportsVersioning; + NvU32 version; + NvU32 depMapCount; + NvU8 depMap[LSF_FALCON_DEPMAP_SIZE * 2 * 4]; + NvU8 kdf[16]; +} LSF_UCODE_DESC, *PLSF_UCODE_DESC; + +/*! + * Light Secure WPR Header + * Defines state allowing Light Secure Falcon bootstrapping. + * + * falconId - LS falcon ID + * lsbOffset - Offset into WPR region holding LSB header + * bootstrapOwner - Bootstrap OWNER (either PMU or SEC2) + * bLazyBootstrap - Skip bootstrapping by ACR + * status - Bootstrapping status + */ +typedef struct +{ + NvU32 falconId; + NvU32 lsbOffset; + NvU32 bootstrapOwner; + NvU32 bLazyBootstrap; + NvU32 binVersion; + NvU32 status; +} LSF_WPR_HEADER, *PLSF_WPR_HEADER; + +/*! + * LSF shared SubWpr Header + * + * useCaseId - Shared SubWpr se case ID (updated by RM) + * startAddr - start address of subWpr (updated by RM) + * size4K - size of subWpr in 4K (updated by RM) + */ +typedef struct +{ + NvU32 useCaseId; + NvU32 startAddr; + NvU32 size4K; +} LSF_SHARED_SUB_WPR_HEADER, *PLSF_SHARED_SUB_WPR_HEADER; + +// Shared SubWpr use case IDs +typedef enum +{ + LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_FRTS_VBIOS_TABLES = 1, + LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA = 2, + LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_APM_RTS = 3 +} LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_ENUM; + +#define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_APM_RTS +#define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_INVALID (0xFFFFFFFFU) + +#define MAX_SUPPORTED_SHARED_SUB_WPR_USE_CASES LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX + +// +// Static sizes of shared subWPRs +// Minimum granularity supported is 4K +// +#define LSF_SHARED_DATA_SUB_WPR_FRTS_VBIOS_TABLES_SIZE_IN_4K (0x100) // 1MB in 4K +#define LSF_SHARED_DATA_SUB_WPR_PLAYREADY_SHARED_DATA_SIZE_IN_4K (0x1) // 4K +#define LSF_SHARED_DATA_SUB_WPR_APM_RTS_SIZE_IN_4K (0x1) // 4K + +/*! + * Bootstrap Owner Defines + */ +#define LSF_BOOTSTRAP_OWNER_PMU (LSF_FALCON_ID_PMU) +#define LSF_BOOTSTRAP_OWNER_SEC2 (LSF_FALCON_ID_SEC2) +#define LSF_BOOTSTRAP_OWNER_GSPLITE (LSF_FALCON_ID_GSPLITE) +#define LSF_BOOTSTRAP_OWNER_DEFAULT LSF_BOOTSTRAP_OWNER_PMU + +/*! + * Image Status Defines + */ +#define LSF_IMAGE_STATUS_NONE (0U) +#define LSF_IMAGE_STATUS_COPY (1U) +#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED (2U) +#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED (3U) +#define LSF_IMAGE_STATUS_VALIDATION_DONE (4U) +#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED (5U) +#define LSF_IMAGE_STATUS_BOOTSTRAP_READY (6U) +#define LSF_IMAGE_STATUS_REVOCATION_CHECK_FAILED (7U) + +/*! + * Light Secure Bootstrap Header + * Defines state allowing Light Secure Falcon bootstrapping. + * + * signature - Code/data signature details for this LS falcon + * ucodeOffset - Offset into WPR region where UCODE is located + * ucodeSize - Size of ucode + * dataSize - Size of ucode data + * blCodeSize - Size of bootloader that needs to be loaded by bootstrap owner + * blImemOffset - BL starting virtual address. Need for tagging. + * blDataOffset - Offset into WPR region holding the BL data + * blDataSize - Size of BL data + * appCodeOffset - Offset into WPR region where Application UCODE is located + * appCodeSize - Size of Application UCODE + * appDataOffset - Offset into WPR region where Application DATA is located + * appDataSize - Size of Application DATA + * blLoadCodeAt0 - Load BL at 0th IMEM offset + * bSetVACtx - Make sure to set the code/data loading CTX DMA to be virtual before exiting + * bDmaReqCtx - This falcon requires a ctx before issuing DMAs + * bForcePrivLoad- Use priv loading method instead of bootloader/DMAs + */ + +#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0 0:0 +#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE 0 +#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_TRUE 1 +#define NV_FLCN_ACR_LSF_FLAG_SET_VA_CTX 1:1 +#define NV_FLCN_ACR_LSF_FLAG_SET_VA_CTX_FALSE 0 +#define NV_FLCN_ACR_LSF_FLAG_SET_VA_CTX_TRUE 1 +#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX 2:2 +#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE 0 +#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE 1 +#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD 3:3 +#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE 0 +#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE 1 +typedef struct +{ + LSF_UCODE_DESC signature; + NvU32 ucodeOffset; + NvU32 ucodeSize; + NvU32 dataSize; + NvU32 blCodeSize; + NvU32 blImemOffset; + NvU32 blDataOffset; + NvU32 blDataSize; + NvU32 appCodeOffset; + NvU32 appCodeSize; + NvU32 appDataOffset; + NvU32 appDataSize; + NvU32 flags; + /* + * TODO: Uncomment this once Sanket's changes + * of HALifying is done + NvU32 monitorCodeOffset; + NvU32 monitorDataOffset; + NvU32 manifestOffset; + */ +} LSF_LSB_HEADER, *PLSF_LSB_HEADER; + + +/*! + * Light Secure WPR Content Alignments + */ +#define LSF_WPR_HEADER_ALIGNMENT (256U) +#define LSF_SUB_WPR_HEADER_ALIGNMENT (256U) +#define LSF_LSB_HEADER_ALIGNMENT (256U) +#define LSF_BL_DATA_ALIGNMENT (256U) +#define LSF_BL_DATA_SIZE_ALIGNMENT (256U) +#define LSF_BL_CODE_SIZE_ALIGNMENT (256U) +#define LSF_DATA_SIZE_ALIGNMENT (256U) +#define LSF_CODE_SIZE_ALIGNMENT (256U) + +// MMU excepts subWpr sizes in units of 4K +#define SUB_WPR_SIZE_ALIGNMENT (4096U) + +/*! + * Maximum WPR Header size + */ +#define LSF_WPR_HEADERS_TOTAL_SIZE_MAX (NV_ALIGN_UP((sizeof(LSF_WPR_HEADER) * LSF_FALCON_ID_END), LSF_WPR_HEADER_ALIGNMENT)) +#define LSF_LSB_HEADER_TOTAL_SIZE_MAX (NV_ALIGN_UP(sizeof(LSF_LSB_HEADER), LSF_LSB_HEADER_ALIGNMENT)) + +// +// PMU OBJACR_ALIGNED_256 size will vary with LSF_FALCON_ID_END. +// PMU could run out of DMEM in case we increase LSF_FALCON_ID_END more and more. +// The PMU supports the ACR task on GM20X_thru_VOLTA profiles only. +// In order to prevent LSF_FALCON_ID_END changes to affect older / shipped PMU ucodes (increase of DMEM footprint) +// adding PMU specific ***_END define capturing value covering all PMU profiles that this with the ACR task. +// +#define LSF_FALCON_ID_END_PMU (LSF_FALCON_ID_FBFALCON + 1) +#define LSF_WPR_HEADERS_TOTAL_SIZE_MAX_PMU (NV_ALIGN_UP((sizeof(LSF_WPR_HEADER) * LSF_FALCON_ID_END_PMU), LSF_WPR_HEADER_ALIGNMENT)) + +// Maximum SUB WPR header size +#define LSF_SUB_WPR_HEADERS_TOTAL_SIZE_MAX (NV_ALIGN_UP((sizeof(LSF_SHARED_SUB_WPR_HEADER) * LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX), LSF_SUB_WPR_HEADER_ALIGNMENT)) + +/*! + * For the ucode surface alignment, We align to RM_PAGE_SIZE because of + * busMapRmAperture issues, not because of Falcon ucode alignment requirements + * which currently are that it be at least 256. + */ +#define LSF_UCODE_DATA_ALIGNMENT RM_PAGE_SIZE + +/*! + * ACR Descriptors used by ACR UC + */ + +/*! + * Supporting maximum of 2 regions. + * This is needed to pre-allocate space in DMEM + */ +#define RM_FLCN_ACR_MAX_REGIONS (2) +#define LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE (0x200) + +/*! + * startAddress - Starting address of region + * endAddress - Ending address of region + * regionID - Region ID + * readMask - Read Mask + * writeMask - WriteMask + * clientMask - Bit map of all clients currently using this region + * shadowMemStartAddress- FB location from where contents need to be copied to startAddress + */ +typedef struct _def_acr_dmem_region_prop +{ + NvU32 startAddress; + NvU32 endAddress; + NvU32 regionID; + NvU32 readMask; + NvU32 writeMask; + NvU32 clientMask; + NvU32 shadowMemStartAddress; +} RM_FLCN_ACR_REGION_PROP, *PRM_FLCN_ACR_REGION_PROP; + + +/*! + * noOfRegions - Number of regions used by RM. + * regionProps - Region properties + */ +typedef struct _def_acr_regions +{ + NvU32 noOfRegions; + RM_FLCN_ACR_REGION_PROP regionProps[RM_FLCN_ACR_MAX_REGIONS]; +} RM_FLCN_ACR_REGIONS, *PRM_FLCN_ACR_REGIONS; + +/*! + * bVprEnabled : When set, ACR_LOCKDOWN phase programs VPR range. Needs to be + : NvU32 because of alignment + * vprStartAddress : Start address of VPR region. SEC2 binary updates this value + * vprEndAddress : End address of VPR region. SEC2 binary updates this value + * hdcpPolicies : VPR display policies. SEC2 binary updates this value + */ +typedef struct _def_acr_vpr_dmem_desc +{ + NvU32 bVprEnabled; + NvU32 vprStartAddress; + NvU32 vprEndAddress; + NvU32 hdcpPolicies; +} ACR_BSI_VPR_DESC, *PACR_BSI_VPR_DESC; + +/*! + * reservedDmem - When the bootstrap owner has done bootstrapping other falcons, + * and need to switch into LS mode, it needs to have its own actual + * DMEM image copied into DMEM as part of LS setup. If ACR desc is at + * location 0, it will definitely get overwritten causing data corruption. + * Hence we are reserving 0x200 bytes to give room for any loading data. + * NOTE: This has to be the first member always + * signature - Signature of ACR ucode. + * wprRegionID - Region ID holding the WPR header and its details + * wprOffset - Offset from the WPR region holding the wpr header + * regions - Region descriptors + * ucodeBlobBase- Used for Tegra, stores non-WPR start address where kernel stores ucode blob + * ucodeBlobSize- Used for Tegra, stores the size of the ucode blob + */ +typedef struct _def_acr_dmem_desc +{ + NvU32 signatures[4]; + NvU32 wprRegionID; + NvU32 wprOffset; + NvU32 mmuMemoryRange; + RM_FLCN_ACR_REGIONS regions; + NvU32 ucodeBlobSize; + // uCodeBlobBase is moved after ucodeBlobSize to inherently align to qword (8 bytes) + NvU64 NV_DECLARE_ALIGNED(ucodeBlobBase, 8); + + /*! + * Do not change the offset of this descriptor as it shared between + * ACR_REGION_LOCKDOWN HS binary and SEC2. Any change in this structure + * need recompilation of SEC2 and ACR_LOCKDOWN HS binary + */ + ACR_BSI_VPR_DESC vprDesc; +} RM_FLCN_ACR_DESC, *PRM_FLCN_ACR_DESC; + +/*! +* Hub keys/nonce Structure in BSI +*/ +#define MAX_SFBHUB_ENCRYPTION_REGION_KEY_SIZE 4 + +typedef struct _def_acr_hub_scratch_data +{ + NvU32 key[MAX_SFBHUB_ENCRYPTION_REGION_KEY_SIZE]; + NvU32 nonce[MAX_SFBHUB_ENCRYPTION_REGION_KEY_SIZE]; +} ACR_BSI_HUB_DESC, *PACR_BSI_HUB_DESC; + +#define MAX_HUB_ENCRYPTION_REGION_COUNT 3 +typedef struct _def_acr_hub_scratch_array +{ + ACR_BSI_HUB_DESC entries[MAX_HUB_ENCRYPTION_REGION_COUNT]; +} ACR_BSI_HUB_DESC_ARRAY, *PACR_BSI_HUB_DESC_ARRAY; + +typedef struct _def_acr_reserved_dmem +{ + NvU32 reservedDmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; // Always first.. +} ACR_RESERVED_DMEM, *PACR_RESERVED_DMEM; + +typedef struct _def_booter_reserved_dmem +{ + NvU32 reservedDmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; // Always first.. +} BOOTER_RESERVED_DMEM; + +#define NV_FLCN_ACR_DESC_FLAGS_SIG_VERIF 0:0 +#define NV_FLCN_ACR_DESC_FLAGS_SIG_VERIF_DISABLE 0 +#define NV_FLCN_ACR_DESC_FLAGS_SIG_VERIF_ENABLE 1 + +// Macro defines to be consumed by RM to get GH100 GSP Inst_in_sys FMC boot status. +#define GSP_INST_IN_SYS_COMPLETION_STATUS_OK 0x55 +#define GSP_INST_IN_SYS_COMPLETION_STATUS_ERROR 0xAA +#define GSP_INST_IN_SYS_COMPLETION_STATUS_IN_PROGRESS 0x00 + +/*! + * Size of ACR phase in dword + */ +#define ACR_PHASE_SIZE_DWORD sizeof(RM_FLCN_ACR_DESC)/sizeof(NvU32) + +/*! + * Falcon Mode Tokens + * This is the value logged to a mailbox register to indicate that the + * falcon isn't booted in secure mode. + */ +#define LSF_FALCON_MODE_TOKEN_FLCN_INSECURE (0xDEADDEADU) + + +// LS encryption context, to store data to decrypt LS images. +#define LS_ENCRYPTION_AES128_CBC_IV_SIZE_BYTE (16) + +typedef struct +{ + NvU8 bLsEncrypted; + NvU8 rsvd[3]; + NvU8 lsEncIV[LS_ENCRYPTION_AES128_CBC_IV_SIZE_BYTE]; +} LSF_ENCRYPTION_CONTEXT, *PLSF_ENCRYPTION_CONTEXT; + +#endif // RMLSFM_H + diff --git a/userspace/sdks/nv525/nvalloc/common/inc/rmpbicmdif.h b/userspace/sdks/nv525/nvalloc/common/inc/rmpbicmdif.h new file mode 100644 index 0000000..0efac2f --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/common/inc/rmpbicmdif.h @@ -0,0 +1,140 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * Shared postbox interface defines for RM and PMU. + */ + +#ifndef RMPBICMDIF_H +#define RMPBICMDIF_H + +/* + * Define the status of postbox interface at different instances. + * + * The values should be in accordance to the spec and must not be changed. + * A new PBI command must be submitted with the status NV_PBI_COMMAND_STATUS_UNDEFINED. + */ + +#define NV_PBI_COMMAND_STATUS 7:0 +#define NV_PBI_COMMAND_STATUS_UNDEFINED 0x00 // command submitted to PMU +#define NV_PBI_COMMAND_STATUS_SUCCESS 0x01 // command successfully completed by PMU +#define NV_PBI_COMMAND_STATUS_PENDING 0x02 // command accepted by PMU +#define NV_PBI_COMMAND_STATUS_BUSY 0x03 // command processing in PMU +#define NV_PBI_COMMAND_STATUS_UNSPECIFIED_FAILURE 0x04 // unknown failure or hang +#define NV_PBI_COMMAND_STATUS_INVALID_ADDRESS 0x05 // invalid address submitted to PMU +#define NV_PBI_COMMAND_STATUS_MORE_DATA 0x06 // user needs to send more data to PMU +#define NV_PBI_COMMAND_STATUS_INVALID_COMMAND 0x07 // invalid command submitted + +/* + * This corresponds to reserved bits of command register + */ +#define NV_PBI_COMMAND_RSVD_0 15:8 +#define NV_PBI_COMMAND_RSVD_0_VAL 0x00 + +/* + * This specifies the dword index if client is sending multiple dwords + * for single Dword this should be zero + */ +#define NV_PBI_COMMAND_BUFFER_INDEX 19:16 + +/* + * This specifies the total no. of dwords passed by client + */ +#define NV_PBI_COMMAND_BUFFER_SIZE 23:20 + +/* + * These corresponds the different function ID's supported out of PBI + */ +#define NV_PBI_COMMAND_FUNC_ID 27:24 +#define NV_PBI_COMMAND_FUNC_ID_GET_CAPABILITIES (0) +#define NV_PBI_COMMAND_FUNC_ID_EXECUTE_ROUTINE (11) + +// +// Definitions for common 'Execute Routine' calls that are +// shared across all GPUs. +// +// Common routine IDs must be in the range 0x80 to 0xff. +// +// Get GID: +#define NV_PBI_EXECUTE_ROUTINE_GET_GID 0x80 +// Get Feature: +#define NV_PBI_EXECUTE_ROUTINE_GET_FEATURE 0x81 +#define NV_PBI_EXECUTE_ROUTINE_GET_FEATURE_EXCLUSION 5:0 +#define NV_PBI_EXECUTE_ROUTINE_GET_FEATURE_EXCLUSION_ALLOWED 0x2 + +/* + * This corresponds to reserved field of command register + */ +#define NV_PBI_COMMAND_RSVD_1 28:28 +#define NV_PBI_COMMAND_RSVD_1_VAL 0x00 + +/* + * If this bit is set system will be notified on command completion + */ +#define NV_PBI_COMMAND_SYS_NOTIFY 29:29 +#define NV_PBI_COMMAND_SYS_NOTIFY_TRUE 0x01 +#define NV_PBI_COMMAND_SYS_NOTIFY_FALSE 0x00 + +/* + * If this bit is set driver will be notified of command completion status + */ +#define NV_PBI_COMMAND_DRV_NOTIFY 30:30 +#define NV_PBI_COMMAND_DRV_NOTIFY_TRUE 0x01 +#define NV_PBI_COMMAND_DRV_NOTIFY_FALSE 0x00 + +/* + * Defines the interrupt state of the PBI command + */ +#define NV_PBI_COMMAND_INTERRUPT 31:31 +#define NV_PBI_COMMAND_INTERRUPT_TRUE 0x01 +#define NV_PBI_COMMAND_INTERRUPT_FALSE 0x00 + +/* + * This sets the different fields of command register + */ +#define PBI_SET_COMMAND_PARAMS(status, r0, index, sz, cmd, r1, sys, \ + drv, intr, val) \ +{ \ + val = DRF_NUM(_PBI, _COMMAND, _STATUS, status) | \ + DRF_NUM(_PBI, _COMMAND, _RSVD_0, r0) | \ + DRF_NUM(_PBI, _COMMAND, _BUFFER_INDEX, index) | \ + DRF_NUM(_PBI, _COMMAND, _BUFFER_SIZE, sz) | \ + DRF_NUM(_PBI, _COMMAND, _FUNC_ID, cmd) | \ + DRF_NUM(_PBI, _COMMAND, _RSVD_1, r1) | \ + DRF_NUM(_PBI, _COMMAND, _SYS_NOTIFY, sys) | \ + DRF_NUM(_PBI, _COMMAND, _DRV_NOTIFY, drv) | \ + DRF_NUM(_PBI, _COMMAND, _INTERRUPT, intr); \ +} + +/* + * postbox_clients_mutex_id + * + * Define the Mutex ID for different PBI clients + */ +enum postbox_clients_mutex_id +{ + PBI_CLIENT_NONE = 0x00, + PBI_CLIENT_DRIVER_PCIPBI_SHIM = 0x15 +}; + +#endif /* RMPBICMDIF_H */ diff --git a/userspace/sdks/nv525/nvalloc/unix/include/efi-console.h b/userspace/sdks/nv525/nvalloc/unix/include/efi-console.h new file mode 100644 index 0000000..7971565 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/include/efi-console.h @@ -0,0 +1,65 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef EFI_CONSOLE_H +#define EFI_CONSOLE_H + +#include "gpu/disp/kern_disp_max.h" + +struct OBJGPU; + +typedef struct +{ + NvBool isDispStateSave; + + NvU32 activeDisplayId[OBJ_MAX_HEADS]; + + struct + { + NvU32 displayId; + + struct { + NvU32 index; + NvU32 subLinkMask; + } sorXBar; + + struct { + NvU32 linkBw; + NvU32 laneCount; + NvU32 linkCtl; + } displayPort; + } activeDfpState[OBJ_MAX_DFPS]; + NvU32 numDfps; + + struct + { + NvU32 coreChannelClass; + NvU32 cacheSize; + NvU32 *pCache; + } display; +} nv_efi_t; + +void RmSaveEFIDisplayState (OBJGPU *pGpu); +void RmRestoreEFIDisplayState (OBJGPU *pGpu); + +#endif // EFI_CONSOLE_H diff --git a/userspace/sdks/nv525/nvalloc/unix/include/nv-caps.h b/userspace/sdks/nv525/nvalloc/unix/include/nv-caps.h new file mode 100644 index 0000000..35bbf7c --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/include/nv-caps.h @@ -0,0 +1,94 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NV_CAPS_H_ +#define _NV_CAPS_H_ + +#include + +/* + * Opaque OS-specific struct; on Linux, this has member + * 'struct proc_dir_entry'. + */ +typedef struct nv_cap nv_cap_t; + +/* + * Creates directory named "capabilities" under the provided path. + * + * @param[in] path Absolute path + * + * Returns a valid nv_cap_t upon success. Otherwise, returns NULL. + */ +nv_cap_t* NV_API_CALL nv_cap_init(const char *path); + +/* + * Creates capability directory entry + * + * @param[in] parent_cap Parent capability directory + * @param[in] name Capability directory's name + * @param[in] mode Capability directory's access mode + * + * Returns a valid nv_cap_t upon success. Otherwise, returns NULL. + */ +nv_cap_t* NV_API_CALL nv_cap_create_dir_entry(nv_cap_t *parent_cap, const char *name, int mode); + +/* + * Creates capability file entry + * + * @param[in] parent_cap Parent capability directory + * @param[in] name Capability file's name + * @param[in] mode Capability file's access mode + * + * Returns a valid nv_cap_t upon success. Otherwise, returns NULL. + */ +nv_cap_t* NV_API_CALL nv_cap_create_file_entry(nv_cap_t *parent_cap, const char *name, int mode); + +/* + * Destroys capability entry + * + * @param[in] cap Capability entry + */ +void NV_API_CALL nv_cap_destroy_entry(nv_cap_t *cap); + +/* + * Validates and duplicates the provided file descriptor + * + * @param[in] cap Capability entry + * @param[in] fd File descriptor to be validated + * + * Returns duplicate fd upon success. Otherwise, returns -1. + */ +int NV_API_CALL nv_cap_validate_and_dup_fd(const nv_cap_t *cap, int fd); + +/* + * Closes file descriptor + * + * This function should be used to close duplicate file descriptors + * returned by nv_cap_validate_and_dup_fd. + * + * @param[in] fd File descriptor to be validated + * + */ +void NV_API_CALL nv_cap_close_fd(int fd); + +#endif /* _NV_CAPS_H_ */ diff --git a/userspace/sdks/nv525/nvalloc/unix/include/nv-gpu-info.h b/userspace/sdks/nv525/nvalloc/unix/include/nv-gpu-info.h new file mode 100644 index 0000000..a8c0c0a --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/include/nv-gpu-info.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NV_GPU_INFO_H_ +#define _NV_GPU_INFO_H_ + +typedef struct { + NvU32 gpu_id; + + struct { + NvU32 domain; + NvU8 bus, slot, function; + } pci_info; + + /* + * opaque OS-specific pointer; on Linux, this is a pointer to the + * 'struct device' for the GPU. + */ + void *os_device_ptr; +} nv_gpu_info_t; + +#define NV_MAX_GPUS 32 + +#endif /* _NV_GPU_INFO_H_ */ diff --git a/userspace/sdks/nv525/nvalloc/unix/include/nv-ioctl-numbers.h b/userspace/sdks/nv525/nvalloc/unix/include/nv-ioctl-numbers.h new file mode 100644 index 0000000..cb0b6a2 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/include/nv-ioctl-numbers.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef NV_IOCTL_NUMBERS_H +#define NV_IOCTL_NUMBERS_H + +/* NOTE: using an ioctl() number > 55 will overflow! */ +#define NV_IOCTL_MAGIC 'F' +#define NV_IOCTL_BASE 200 +#define NV_ESC_CARD_INFO (NV_IOCTL_BASE + 0) +#define NV_ESC_REGISTER_FD (NV_IOCTL_BASE + 1) +#define NV_ESC_ALLOC_OS_EVENT (NV_IOCTL_BASE + 6) +#define NV_ESC_FREE_OS_EVENT (NV_IOCTL_BASE + 7) +#define NV_ESC_STATUS_CODE (NV_IOCTL_BASE + 9) +#define NV_ESC_CHECK_VERSION_STR (NV_IOCTL_BASE + 10) +#define NV_ESC_IOCTL_XFER_CMD (NV_IOCTL_BASE + 11) +#define NV_ESC_ATTACH_GPUS_TO_FD (NV_IOCTL_BASE + 12) +#define NV_ESC_QUERY_DEVICE_INTR (NV_IOCTL_BASE + 13) +#define NV_ESC_SYS_PARAMS (NV_IOCTL_BASE + 14) +#define NV_ESC_EXPORT_TO_DMABUF_FD (NV_IOCTL_BASE + 17) + +#endif diff --git a/userspace/sdks/nv525/nvalloc/unix/include/nv-ioctl.h b/userspace/sdks/nv525/nvalloc/unix/include/nv-ioctl.h new file mode 100644 index 0000000..ffd1dee --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/include/nv-ioctl.h @@ -0,0 +1,145 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef NV_IOCTL_H +#define NV_IOCTL_H + +#include +#include + +typedef struct { + NvU32 domain; /* PCI domain number */ + NvU8 bus; /* PCI bus number */ + NvU8 slot; /* PCI slot number */ + NvU8 function; /* PCI function number */ + NvU16 vendor_id; /* PCI vendor ID */ + NvU16 device_id; /* PCI device ID */ +} nv_pci_info_t; + +/* + * ioctl()'s with parameter structures too large for the + * _IOC cmd layout use the nv_ioctl_xfer_t structure + * and the NV_ESC_IOCTL_XFER_CMD ioctl() to pass the actual + * size and user argument pointer into the RM, which + * will then copy it to/from kernel space in separate steps. + */ +typedef struct nv_ioctl_xfer +{ + NvU32 cmd; + NvU32 size; + NvP64 ptr NV_ALIGN_BYTES(8); +} nv_ioctl_xfer_t; + +typedef struct nv_ioctl_card_info +{ + NvBool valid; + nv_pci_info_t pci_info; /* PCI config information */ + NvU32 gpu_id; + NvU16 interrupt_line; + NvU64 reg_address NV_ALIGN_BYTES(8); + NvU64 reg_size NV_ALIGN_BYTES(8); + NvU64 fb_address NV_ALIGN_BYTES(8); + NvU64 fb_size NV_ALIGN_BYTES(8); + NvU32 minor_number; + NvU8 dev_name[10]; /* device names such as vmgfx[0-32] for vmkernel */ +} nv_ioctl_card_info_t; + +/* alloc event */ +typedef struct nv_ioctl_alloc_os_event +{ + NvHandle hClient; + NvHandle hDevice; + NvU32 fd; + NvU32 Status; +} nv_ioctl_alloc_os_event_t; + +/* free event */ +typedef struct nv_ioctl_free_os_event +{ + NvHandle hClient; + NvHandle hDevice; + NvU32 fd; + NvU32 Status; +} nv_ioctl_free_os_event_t; + +/* status code */ +typedef struct nv_ioctl_status_code +{ + NvU32 domain; + NvU8 bus; + NvU8 slot; + NvU32 status; +} nv_ioctl_status_code_t; + +/* check version string */ +#define NV_RM_API_VERSION_STRING_LENGTH 64 + +typedef struct nv_ioctl_rm_api_version +{ + NvU32 cmd; + NvU32 reply; + char versionString[NV_RM_API_VERSION_STRING_LENGTH]; +} nv_ioctl_rm_api_version_t; + +#define NV_RM_API_VERSION_CMD_STRICT 0 +#define NV_RM_API_VERSION_CMD_RELAXED '1' +#define NV_RM_API_VERSION_CMD_OVERRIDE '2' + +#define NV_RM_API_VERSION_REPLY_UNRECOGNIZED 0 +#define NV_RM_API_VERSION_REPLY_RECOGNIZED 1 + +typedef struct nv_ioctl_query_device_intr +{ + NvU32 intrStatus NV_ALIGN_BYTES(4); + NvU32 status; +} nv_ioctl_query_device_intr; + +/* system parameters that the kernel driver may use for configuration */ +typedef struct nv_ioctl_sys_params +{ + NvU64 memblock_size NV_ALIGN_BYTES(8); +} nv_ioctl_sys_params_t; + +typedef struct nv_ioctl_register_fd +{ + int ctl_fd; +} nv_ioctl_register_fd_t; + +#define NV_DMABUF_EXPORT_MAX_HANDLES 128 + +typedef struct nv_ioctl_export_to_dma_buf_fd +{ + int fd; + NvHandle hClient; + NvU32 totalObjects; + NvU32 numObjects; + NvU32 index; + NvU64 totalSize NV_ALIGN_BYTES(8); + NvHandle handles[NV_DMABUF_EXPORT_MAX_HANDLES]; + NvU64 offsets[NV_DMABUF_EXPORT_MAX_HANDLES] NV_ALIGN_BYTES(8); + NvU64 sizes[NV_DMABUF_EXPORT_MAX_HANDLES] NV_ALIGN_BYTES(8); + NvU32 status; +} nv_ioctl_export_to_dma_buf_fd_t; + +#endif diff --git a/userspace/sdks/nv525/nvalloc/unix/include/nv-kernel-rmapi-ops.h b/userspace/sdks/nv525/nvalloc/unix/include/nv-kernel-rmapi-ops.h new file mode 100644 index 0000000..f44799b --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/include/nv-kernel-rmapi-ops.h @@ -0,0 +1,61 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NV_KERNEL_RMAPI_OPS_H_ +#define _NV_KERNEL_RMAPI_OPS_H_ + +/* + * Define the RMAPI provided to kernel-level RM clients. + * + * Kernel-level RM clients should populate nvidia_kernel_rmapi_ops_t + * by assigning nvidia_kernel_rmapi_ops_t::op and the corresponding + * parameter structure in nvidia_kernel_rmapi_ops_t's params union. + * Then, pass a pointer to the nvidia_kernel_rmapi_ops_t to + * rm_kernel_rmapi_op(). + */ + +#include "nvtypes.h" +#include "nvos.h" + +typedef struct { + NvU32 op; /* One of the NV0[14]_XXXX operations listed below. */ + + union { + NVOS00_PARAMETERS free; /* NV01_FREE */ + NVOS02_PARAMETERS allocMemory64; /* NV01_ALLOC_MEMORY */ + NVOS21_PARAMETERS alloc; /* NV04_ALLOC */ + NVOS32_PARAMETERS *pVidHeapControl; /* NV04_VID_HEAP_CONTROL */ + NVOS33_PARAMETERS mapMemory; /* NV04_MAP_MEMORY */ + NVOS34_PARAMETERS unmapMemory; /* NV04_UNMAP_MEMORY */ + NVOS39_PARAMETERS allocContextDma2; /* NV04_ALLOC_CONTEXT_DMA */ + NVOS46_PARAMETERS mapMemoryDma; /* NV04_MAP_MEMORY_DMA */ + NVOS47_PARAMETERS unmapMemoryDma; /* NV04_UNMAP_MEMORY_DMA */ + NVOS49_PARAMETERS bindContextDma; /* NV04_BIND_CONTEXT_DMA */ + NVOS54_PARAMETERS control; /* NV04_CONTROL*/ + NVOS55_PARAMETERS dupObject; /* NV04_DUP_OBJECT */ + NVOS57_PARAMETERS share; /* NV04_SHARE */ + NVOS61_PARAMETERS addVblankCallback; /* NV04_ADD_VBLANK_CALLBACK */ + } params; +} nvidia_kernel_rmapi_ops_t; + +#endif /* _NV_KERNEL_RMAPI_OPS_H_ */ diff --git a/userspace/sdks/nv525/nvalloc/unix/include/nv-nb-regs.h b/userspace/sdks/nv525/nvalloc/unix/include/nv-nb-regs.h new file mode 100644 index 0000000..6282b35 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/include/nv-nb-regs.h @@ -0,0 +1,65 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NV_NB_REGS_H_ +#define _NV_NB_REGS_H_ + +#include "nvdevid.h" + +typedef struct +{ + NvU32 subsystem_vendor_id; + NvU32 subsystem_device_id; + NvU16 gpu_device_id; +} nv_nb_id_t; + +typedef struct +{ + NvU32 vendor_id; + const char *name; + NvU32 data; +} nv_nb_reg_t; + +/* + * nb_id_table contains the OEM vendor ID, the subsystem ID and the + * GPU device ID of the notebooks for which we need to enable + * vendor specific registry keys. nb_reg_table contains the vendor + * specific registry key values. The initVendorSpecificRegistry() + * function compares the present notebooks OEM subsystem ID and the + * GPU device ID with the values present in id_tables. If a match + * is found, initVendorSpecificRegistry() extracts the vendor + * ID and sets any associated registry key listed in nb_reg_table. + */ + +static nv_nb_id_t nb_id_table[] = { + { PCI_VENDOR_ID_PC_PARTNER, 0x0620, 0x1284 }, // Acer GT 630 + { PCI_VENDOR_ID_PC_PARTNER, 0x0620, 0x124b }, // Acer GT 640 + { 0, 0, 0 } +}; + +static nv_nb_reg_t nb_reg_table[] = { + { PCI_VENDOR_ID_PC_PARTNER, "RmOverrideSupportChipsetAspm", 2 }, + { 0, NULL, 0 } +}; + +#endif //_NV_NB_REGS_H_ diff --git a/userspace/sdks/nv525/nvalloc/unix/include/nv-priv.h b/userspace/sdks/nv525/nvalloc/unix/include/nv-priv.h new file mode 100644 index 0000000..b605a73 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/include/nv-priv.h @@ -0,0 +1,377 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NV_PRIV_H_ +#define _NV_PRIV_H_ + +#include +#include +#include +#include +#include + +#include + +#define NV_PRIV_REG_WR08(b,o,d) (*((volatile NvV8*)&(b)->Reg008[(o)/1])=(NvV8)(d)) +#define NV_PRIV_REG_WR16(b,o,d) (*((volatile NvV16*)&(b)->Reg016[(o)/2])=(NvV16)(d)) +#define NV_PRIV_REG_WR32(b,o,d) (*((volatile NvV32*)&(b)->Reg032[(o)/4])=(NvV32)(d)) + +#define NV_PRIV_REG_RD08(b,o) ((b)->Reg008[(o)/1]) +#define NV_PRIV_REG_RD16(b,o) ((b)->Reg016[(o)/2]) +#define NV_PRIV_REG_RD32(b,o) ((b)->Reg032[(o)/4]) + +struct OBJGPU; + +typedef struct +{ + NvBool baseValid; + VGAADDRDESC base; + NvBool workspaceBaseValid; + VGAADDRDESC workspaceBase; + NvU32 vesaMode; +} nv_vga_t; + +/* +* device state during Power Management +*/ +typedef struct nv_pm_state_s +{ + NvU32 IntrEn; + NvBool InHibernate; +} nv_pm_state_t; + +/* +* data structure for the UNIX workqueues +*/ +typedef struct nv_work_item_s +{ + NvU32 flags; + NvU32 gpuInstance; + union + { + OSWorkItemFunction *pGpuFunction; + OSSystemWorkItemFunction *pSystemFunction; + } func; + void *pData; +} nv_work_item_t; + +#define NV_WORK_ITEM_FLAGS_NONE 0x0 +#define NV_WORK_ITEM_FLAGS_REQUIRES_GPU 0x1 +#define NV_WORK_ITEM_FLAGS_DONT_FREE_DATA 0x2 + +/* + * pseudo-registry data structure + */ + +typedef enum +{ + NV_REGISTRY_ENTRY_TYPE_UNKNOWN = 0, + NV_REGISTRY_ENTRY_TYPE_DWORD, + NV_REGISTRY_ENTRY_TYPE_BINARY, + NV_REGISTRY_ENTRY_TYPE_STRING +} nv_reg_type_t; + +typedef struct nv_reg_entry_s +{ + char *regParmStr; + NvU32 type; + NvU32 data; // used when type == NV_REGISTRY_ENTRY_TYPE_DWORD + NvU8 *pdata; // used when type == NV_REGISTRY_ENTRY_TYPE_{BINARY,STRING} + NvU32 len; // used when type == NV_REGISTRY_ENTRY_TYPE_{BINARY,STRING} + struct nv_reg_entry_s *next; +} nv_reg_entry_t; + +#define INVALID_DISP_ID 0xFFFFFFFF +#define MAX_DISP_ID_PER_ADAPTER 0x2 + +typedef struct nv_i2c_adapter_entry_s +{ + void *pOsAdapter; + NvU32 port; + NvU32 displayId[MAX_DISP_ID_PER_ADAPTER]; +} nv_i2c_adapter_entry_t; + +#define NV_INIT_FLAG_HAL 0x0001 +#define NV_INIT_FLAG_HAL_COMPONENTS 0x0002 +#define NV_INIT_FLAG_GPU_STATE 0x0004 +#define NV_INIT_FLAG_GPU_STATE_LOAD 0x0008 +#define NV_INIT_FLAG_FIFO_WATCHDOG 0x0010 +#define NV_INIT_FLAG_CORE_LOGIC 0x0020 +#define NV_INIT_FLAG_GPUMGR_ATTACH 0x0040 +#define NV_INIT_FLAG_PUBLIC_I2C 0x0080 +#define NV_INIT_FLAG_SCALABILITY 0x0100 +#define NV_INIT_FLAG_DMA 0x0200 + +#define MAX_I2C_ADAPTERS NV402C_CTRL_NUM_I2C_PORTS + +/* + * GPU dynamic power state machine. + * + * The GPU is in exactly one of these states at at time. Only certain state + * transitions are valid, as documented by the DAGs below. + * + * When in "instant idle" or COARSE mode: + * + * +----------------------+ + * v | + * +---------+ +----------------+ +--------+ + * | UNKNOWN | --> | IDLE_INDICATED | --> | IN_USE | + * +---------+ +----------------+ +--------+ + * + * The transition from UNKNOWN to IDLE_INDICATED happens in + * rm_init_dynamic_power_management(). + * + * Thereafter, transitions from IDLE_INDICATED to IN_USE happen when + * os_ref_dynamic_power() is called and the refcount transitions from 0 to 1; + * transitions from IN_USE to IDLE_INDICATED happen when + * os_unref_dynamic_power() is called and the refcount transitions from 1 to 0. + * Note that only calls to os_(un)ref_dynamic_power() with the mode == COARSE + * are considered in this mode; calls with mode == FINE are ignored. Since + * COARSE calls are placed only in rm_init_adapter/rm_shutdown_adapter, the GPU + * effectively stays in the IN_USE state any time any client has initialized + * it. + * + * + * When in "deferred idle" or FINE mode: + * + * +----------------------------------------------------------------+ + * | | + * | | + * | +-------------------------------------------+----------------------+ + * | | | v + * | +---------+ +----------------+ +--------------+ +----------------+ +--------+ + * | | UNKNOWN | --> | IDLE_INDICATED | --> | | --> | IDLE_SUSTAINED | --> | IN_USE | -+ + * | +---------+ +----------------+ | | +----------------+ +--------+ | + * | ^ | | | ^ | + * +--------------------+ | IDLE_INSTANT | ------+----------------------+ | + * | | | | + * | | | | + * | | <-----+ | + * +--------------+ | + * ^ | + * +-----------------------------------------------------+ + * + * As before, the transition from UNKNOWN to IDLE_INDICATED happens in + * rm_init_dynamic_power_management(). This is not ideal: it means the GPU may + * be powered down immediately upon loading the RM module, even if + * rm_init_adapter() is going to be called soon thereafter. However, we can't + * rely on deferred idle callbacks yet, since those currently rely on core RM + * being initialized. + * + * At the beginning of rm_init_adapter(), the GPU transitions to the IN_USE + * state; during the rm_init_adapter() sequence, + * RmInitDeferredDynamicPowerManagement() will be called which will schedule + * timer callbacks and set the "deferred_idle_enabled" boolean. + * + * While in "deferred idle" mode, one of the callbacks + * timerCallbackForIdlePreConditions(), timerCallbackToIndicateIdle(), or + * RmIndicateIdle() should be scheduled when in the states: + * - IN_USE + * - IDLE_INSTANT + * - IDLE_SUSTAINED + * Note that since we may transition from IN_USE to IDLE_INSTANT rapidly (e.g., + * for a series of RM calls), we don't attempt to schedule the callbacks and + * cancel them on each of these transitions. The + * timerCallbackForIdlePreConditions() callback will simply exit early if in + * the IN_USE state. + * + * As before, the GPU will remain in the IN_USE state until + * os_unref_dynamic_power() is called and the count transitions from 1 to 0 + * (calls with mode == FINE are honored, in this mode, and these transitions + * can happen frequently). When the refcount reaches 0, rather than going + * directly to the IDLE_INDICATED state, it transitions to the IDLE_INSTANT + * state. + * + * Then, when the next timerCallbackForIdlePreConditions() callback executes, + * if all preconditions are met, the state will transition to IDLE_SUSTAINED. + * + * If, when in the IDLE_SUSTAINED state, os_ref_dynamic_power() is called, the + * GPU will transition back to the IN_USE state and return to the IDLE_INSTANT + * state. This ensures that there is a suitable delay between any activity + * that requires bumping the refcount and indicating idleness. + * + * If the timerCallbackForIdlePreConditions() callback executes again and the + * GPU is still in the IDLE_SUSTAINED state, userspace mappings will be revoked + * and the timerCallbackToIndicateIdle() callback will be scheduled. + * + * If, before the timerCallbackToIndicateIdle() callback executes, either + * os_ref_dynamic_power() is called or a mapping which has been revoked is + * accessed (which triggers the RmForceGpuNotIdle() callback), the GPU will + * transition back to the IN_USE or IDLE_INSTANT state, respectively. + * + * Then, when the timerCallbackToIndicateIdle() callback executes, if all + * mappings are still revoked, and the GPU is still in the IDLE_SUSTAINED + * state, and all GPU idleness preconditions remain satisfied, the + * RmIndicateIdle() work item will be enqueued. (Else, the GPU will transition + * back to the IDLE_INSTANT state and the callback for preconditions is + * scheduled again.) + * + * Finally, once the RmIndicateIdle() work item is called, if all of the same + * conditions still hold, the state will transition to IDLE_INDICATED. No + * callbacks will be scheduled from here; the callbacks for preconditions + * should be re-scheduled when transitioning out of the IDLE_INDICATED state. + * + * Once in the IDLE_INDICATED state, the kernel is free to call the RM to + * perform the GC6 entry sequence then turn off power to the GPU (although it + * may not, if the audio function is being used for example). + * + * There are two paths to exit the IDLE_INDICATED state: + * (a) If os_ref_dynamic_power() is called, in which case it transitions + * directly to the IN_USE state; + * (b) If RmForceGpuNotIdle() is called, in which case it transitions back to + * the IDLE_INSTANT state. + */ +typedef enum +{ + NV_DYNAMIC_POWER_STATE_UNKNOWN = 0, + + NV_DYNAMIC_POWER_STATE_IN_USE, + + NV_DYNAMIC_POWER_STATE_IDLE_INSTANT, + NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED, + NV_DYNAMIC_POWER_STATE_IDLE_INDICATED, +} nv_dynamic_power_state_t; + +typedef struct nv_dynamic_power_s +{ + /* + * mode is read without the mutex -- should be read-only outside of + * rm_init_dynamic_power_management, called during probe only. + */ + nv_dynamic_power_mode_t mode; + /* + * Whether to indicate idle immediately when the refcount reaches 0, or + * only go to the IDLE_INSTANT state, and expect timer callbacks to + * transition through IDLE_SUSTAINED -> IDLE_INDICATED. + */ + NvBool deferred_idle_enabled; + + nv_dynamic_power_state_t state; + NvS32 refcount; + + /* + * A word on lock ordering. These locks must be taken in the order: + * + * RM API lock > this dynamic_power mutex > RM GPUs lock + * + * Skipping any of those locks is fine (if they aren't required to protect + * whatever state is being accessed or modified), so long as the order is + * not violated. + */ + PORT_MUTEX *mutex; + + /* + * callback handles for deferred dynamic power management. + */ + NvP64 idle_precondition_check_event; + NvP64 indicate_idle_event; + NvBool idle_precondition_check_callback_scheduled; + + /* + * callback handle for kernel initiated gc6 entry/exit. + * these will be protected by the gpu lock. + */ + NvP64 remove_idle_holdoff; + NvBool b_idle_holdoff; + + /* + * flag set if the platform does not support fine grain dynamic power + * management. + */ + NvBool b_fine_not_supported; + + /* + * This flag is used to check if a workitem is queued for + * RmQueueIdleSustainedWorkitem(). + */ + NvBool b_idle_sustained_workitem_queued; + + /* + * Counter to track clients disallowing GCOFF. + */ + NvU32 clients_gcoff_disallow_refcount; + + /* + * Maximum FB allocation size which can be saved in system memory + * while doing GCOFF based dynamic PM. + */ + NvU64 gcoff_max_fb_size; + + /* + * NVreg_DynamicPowerManagement regkey value set by the user + */ + NvU32 dynamic_power_regkey; +} nv_dynamic_power_t; + +typedef struct +{ + OBJGPU *pGpu; + + NvU32 pmc_boot_0; + + nv_vga_t vga; + + nv_efi_t efi; + + NvU32 flags; + NvU32 status; + + nv_i2c_adapter_entry_t i2c_adapters[MAX_I2C_ADAPTERS]; + + void *pVbiosCopy; + NvU32 vbiosSize; + + nv_pm_state_t pm_state; + + nv_reg_entry_t *pRegistry; + + nv_dynamic_power_t dynamic_power; + + /* Flag to check if the GPU needs 4K page isolation. */ + NvBool b_4k_page_isolation_required; + + /* Flag to check if GPU mobile config is enabled */ + NvBool b_mobile_config_enabled; + + /* Flag to check if S0ix-based power management is enabled. */ + NvBool s0ix_pm_enabled; + + /* + * Maximum FB allocation size which can be saved in system memory + * during system supened with S0ix-based power management. + */ + NvU64 s0ix_gcoff_max_fb_size; + + NvU32 pmc_boot_42; +} nv_priv_t; + +#define NV_SET_NV_PRIV(nv,p) ((nv)->priv = (p)) +#define NV_GET_NV_PRIV(nv) ((nv) ? (nv)->priv : NULL) + +/* + * Make sure that your stack has taken API Lock before using this macro. + */ +#define NV_GET_NV_PRIV_PGPU(nv) \ + (NV_GET_NV_PRIV(nv) ? ((nv_priv_t *)NV_GET_NV_PRIV(nv))->pGpu : NULL) + +#endif // _NV_PRIV_H_ diff --git a/userspace/sdks/nv525/nvalloc/unix/include/nv-reg.h b/userspace/sdks/nv525/nvalloc/unix/include/nv-reg.h new file mode 100644 index 0000000..31d3560 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/include/nv-reg.h @@ -0,0 +1,927 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _RM_REG_H_ +#define _RM_REG_H_ + +#include "nvtypes.h" + +/* + * use NV_REG_STRING to stringify a registry key when using that registry key + */ + +#define __NV_REG_STRING(regkey) #regkey +#define NV_REG_STRING(regkey) __NV_REG_STRING(regkey) + +/* + * use NV_DEFINE_REG_ENTRY and NV_DEFINE_PARAMS_TABLE_ENTRY to simplify definition + * of registry keys in the kernel module source code. + */ + +#define __NV_REG_VAR(regkey) NVreg_##regkey + +#if defined(NV_MODULE_PARAMETER) +#define NV_DEFINE_REG_ENTRY(regkey, default_value) \ + static NvU32 __NV_REG_VAR(regkey) = (default_value); \ + NV_MODULE_PARAMETER(__NV_REG_VAR(regkey)) +#define NV_DEFINE_REG_ENTRY_GLOBAL(regkey, default_value) \ + NvU32 __NV_REG_VAR(regkey) = (default_value); \ + NV_MODULE_PARAMETER(__NV_REG_VAR(regkey)) +#else +#define NV_DEFINE_REG_ENTRY(regkey, default_value) \ + static NvU32 __NV_REG_VAR(regkey) = (default_value) +#define NV_DEFINE_REG_ENTRY_GLOBAL(regkey, default_value) \ + NvU32 __NV_REG_VAR(regkey) = (default_value) +#endif + +#if defined(NV_MODULE_STRING_PARAMETER) +#define NV_DEFINE_REG_STRING_ENTRY(regkey, default_value) \ + char *__NV_REG_VAR(regkey) = (default_value); \ + NV_MODULE_STRING_PARAMETER(__NV_REG_VAR(regkey)) +#else +#define NV_DEFINE_REG_STRING_ENTRY(regkey, default_value) \ + char *__NV_REG_VAR(regkey) = (default_value) +#endif + +#define NV_DEFINE_PARAMS_TABLE_ENTRY(regkey) \ + { NV_REG_STRING(regkey), &__NV_REG_VAR(regkey) } + +/* + * Like NV_DEFINE_PARMS_TABLE_ENTRY, but allows a mismatch between the name of + * the regkey and the name of the module parameter. When using this macro, the + * name of the parameter is passed to the extra "parameter" argument, and it is + * this name that must be used in the NV_DEFINE_REG_ENTRY() macro. + */ + +#define NV_DEFINE_PARAMS_TABLE_ENTRY_CUSTOM_NAME(regkey, parameter) \ + { NV_REG_STRING(regkey), &__NV_REG_VAR(parameter)} + +/* + *----------------- registry key definitions-------------------------- + */ + +/* + * Option: ModifyDeviceFiles + * + * Description: + * + * When this option is enabled, the NVIDIA driver will verify the validity + * of the NVIDIA device files in /dev and attempt to dynamically modify + * and/or (re-)create them, if necessary. If you don't wish for the NVIDIA + * driver to touch the device files, you can use this registry key. + * + * This module parameter is only honored by the NVIDIA GPU driver and NVIDIA + * capability driver. Furthermore, the NVIDIA capability driver provides + * modifiable /proc file entry (DeviceFileModify=0/1) to alter the behavior of + * this module parameter per device file. + * + * Possible Values: + * 0 = disable dynamic device file management + * 1 = enable dynamic device file management (default) + */ + +#define __NV_MODIFY_DEVICE_FILES ModifyDeviceFiles +#define NV_REG_MODIFY_DEVICE_FILES NV_REG_STRING(__NV_MODIFY_DEVICE_FILES) + +/* + * Option: DeviceFileUID + * + * Description: + * + * This registry key specifies the UID assigned to the NVIDIA device files + * created and/or modified by the NVIDIA driver when dynamic device file + * management is enabled. + * + * This module parameter is only honored by the NVIDIA GPU driver. + * + * The default UID is 0 ('root'). + */ + +#define __NV_DEVICE_FILE_UID DeviceFileUID +#define NV_REG_DEVICE_FILE_UID NV_REG_STRING(__NV_DEVICE_FILE_UID) + +/* + * Option: DeviceFileGID + * + * Description: + * + * This registry key specifies the GID assigned to the NVIDIA device files + * created and/or modified by the NVIDIA driver when dynamic device file + * management is enabled. + * + * This module parameter is only honored by the NVIDIA GPU driver. + * + * The default GID is 0 ('root'). + */ + +#define __NV_DEVICE_FILE_GID DeviceFileGID +#define NV_REG_DEVICE_FILE_GID NV_REG_STRING(__NV_DEVICE_FILE_GID) + +/* + * Option: DeviceFileMode + * + * Description: + * + * This registry key specifies the device file mode assigned to the NVIDIA + * device files created and/or modified by the NVIDIA driver when dynamic + * device file management is enabled. + * + * This module parameter is only honored by the NVIDIA GPU driver. + * + * The default mode is 0666 (octal, rw-rw-rw-). + */ + +#define __NV_DEVICE_FILE_MODE DeviceFileMode +#define NV_REG_DEVICE_FILE_MODE NV_REG_STRING(__NV_DEVICE_FILE_MODE) + +/* + * Option: ResmanDebugLevel + * + * Default value: ~0 + */ + +#define __NV_RESMAN_DEBUG_LEVEL ResmanDebugLevel +#define NV_REG_RESMAN_DEBUG_LEVEL NV_REG_STRING(__NV_RESMAN_DEBUG_LEVEL) + +/* + * Option: RmLogonRC + * + * Default value: 1 + */ + +#define __NV_RM_LOGON_RC RmLogonRC +#define NV_REG_RM_LOGON_RC NV_REG_STRING(__NV_RM_LOGON_RC) + +/* + * Option: InitializeSystemMemoryAllocations + * + * Description: + * + * The NVIDIA Linux driver normally clears system memory it allocates + * for use with GPUs or within the driver stack. This is to ensure + * that potentially sensitive data is not rendered accessible by + * arbitrary user applications. + * + * Owners of single-user systems or similar trusted configurations may + * choose to disable the aforementioned clears using this option and + * potentially improve performance. + * + * Possible values: + * + * 1 = zero out system memory allocations (default) + * 0 = do not perform memory clears + */ + +#define __NV_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS \ + InitializeSystemMemoryAllocations +#define NV_REG_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS \ + NV_REG_STRING(__NV_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS) + +/* + * Option: RegistryDwords + * + * Description: + * + * This option accepts a semicolon-separated list of key=value pairs. Each + * key name is checked against the table of static options; if a match is + * found, the static option value is overridden, but invalid options remain + * invalid. Pairs that do not match an entry in the static option table + * are passed on to the RM directly. + * + * Format: + * + * NVreg_RegistryDwords=";;..." + */ + +#define __NV_REGISTRY_DWORDS RegistryDwords +#define NV_REG_REGISTRY_DWORDS NV_REG_STRING(__NV_REGISTRY_DWORDS) + +/* + * Option: RegistryDwordsPerDevice + * + * Description: + * + * This option allows to specify registry keys per GPU device. It helps to + * control registry at GPU level of granularity. It accepts a semicolon + * separated list of key=value pairs. The first key value pair MUST be + * "pci=DDDD:BB:DD.F;" where DDDD is Domain, BB is Bus Id, DD is device slot + * number and F is the Function. This PCI BDF is used to identify which GPU to + * assign the registry keys that follows next. + * If a GPU corresponding to the value specified in "pci=DDDD:BB:DD.F;" is NOT + * found, then all the registry keys that follows are skipped, until we find next + * valid pci identified "pci=DDDD:BB:DD.F;". Following are the valid formats for + * the value of the "pci" string: + * 1) bus:slot : Domain and function defaults to 0. + * 2) domain:bus:slot : Function defaults to 0. + * 3) domain:bus:slot.func : Complete PCI dev id string. + * + * For each of the registry keys that follows, key name is checked against the + * table of static options; if a match is found, the static option value is + * overridden, but invalid options remain invalid. Pairs that do not match an + * entry in the static option table are passed on to the RM directly. + * + * Format: + * + * NVreg_RegistryDwordsPerDevice="pci=DDDD:BB:DD.F;;;..; \ + * pci=DDDD:BB:DD.F;;..;" + */ + +#define __NV_REGISTRY_DWORDS_PER_DEVICE RegistryDwordsPerDevice +#define NV_REG_REGISTRY_DWORDS_PER_DEVICE NV_REG_STRING(__NV_REGISTRY_DWORDS_PER_DEVICE) + +#define __NV_RM_MSG RmMsg +#define NV_RM_MSG NV_REG_STRING(__NV_RM_MSG) + +/* + * Option: UsePageAttributeTable + * + * Description: + * + * Enable/disable use of the page attribute table (PAT) available in + * modern x86/x86-64 processors to set the effective memory type of memory + * mappings to write-combining (WC). + * + * If enabled, an x86 processor with PAT support is present and the host + * system's Linux kernel did not configure one of the PAT entries to + * indicate the WC memory type, the driver will change the second entry in + * the PAT from its default (write-through (WT)) to WC at module load + * time. If the kernel did update one of the PAT entries, the driver will + * not modify the PAT. + * + * In both cases, the driver will honor attempts to map memory with the WC + * memory type by selecting the appropriate PAT entry using the correct + * set of PTE flags. + * + * Possible values: + * + * ~0 = use the NVIDIA driver's default logic (default) + * 1 = enable use of the PAT for WC mappings. + * 0 = disable use of the PAT for WC mappings. + */ + +#define __NV_USE_PAGE_ATTRIBUTE_TABLE UsePageAttributeTable +#define NV_USE_PAGE_ATTRIBUTE_TABLE NV_REG_STRING(__NV_USE_PAGE_ATTRIBUTE_TABLE) + +/* + * Option: EnableMSI + * + * Description: + * + * When this option is enabled and the host kernel supports the MSI feature, + * the NVIDIA driver will enable the PCI-E MSI capability of GPUs with the + * support for this feature instead of using PCI-E wired interrupt. + * + * Possible Values: + * + * 0 = disable MSI interrupt + * 1 = enable MSI interrupt (default) + * + */ + +#define __NV_ENABLE_MSI EnableMSI +#define NV_REG_ENABLE_MSI NV_REG_STRING(__NV_ENABLE_MSI) + +/* + * Option: EnablePCIeGen3 + * + * Description: + * + * Due to interoperability problems seen with Kepler PCIe Gen3 capable GPUs + * when configured on SandyBridge E desktop platforms, NVIDIA feels that + * delivering a reliable, high-quality experience is not currently possible in + * PCIe Gen3 mode on all PCIe Gen3 platforms. Therefore, Quadro, Tesla and + * NVS Kepler products operate in PCIe Gen2 mode by default. You may use this + * option to enable PCIe Gen3 support. + * + * This is completely unsupported! + * + * Possible Values: + * + * 0: disable PCIe Gen3 support (default) + * 1: enable PCIe Gen3 support + */ + +#define __NV_ENABLE_PCIE_GEN3 EnablePCIeGen3 +#define NV_REG_ENABLE_PCIE_GEN3 NV_REG_STRING(__NV_ENABLE_PCIE_GEN3) + +/* + * Option: MemoryPoolSize + * + * Description: + * + * When set to a non-zero value, this option specifies the size of the + * memory pool, given as a multiple of 1 GB, created on VMware ESXi to + * satisfy any system memory allocations requested by the NVIDIA kernel + * module. + */ + +#define __NV_MEMORY_POOL_SIZE MemoryPoolSize +#define NV_REG_MEMORY_POOL_SIZE NV_REG_STRING(__NV_MEMORY_POOL_SIZE) + +/* + * Option: KMallocHeapMaxSize + * + * Description: + * + * When set to a non-zero value, this option specifies the maximum size of the + * heap memory space reserved for kmalloc operations. Given as a + * multiple of 1 MB created on VMware ESXi to satisfy any system memory + * allocations requested by the NVIDIA kernel module. + */ + +#define __NV_KMALLOC_HEAP_MAX_SIZE KMallocHeapMaxSize +#define NV_KMALLOC_HEAP_MAX_SIZE NV_REG_STRING(__NV_KMALLOC_HEAP_MAX_SIZE) + +/* + * Option: VMallocHeapMaxSize + * + * Description: + * + * When set to a non-zero value, this option specifies the maximum size of the + * heap memory space reserved for vmalloc operations. Given as a + * multiple of 1 MB created on VMware ESXi to satisfy any system memory + * allocations requested by the NVIDIA kernel module. + */ + +#define __NV_VMALLOC_HEAP_MAX_SIZE VMallocHeapMaxSize +#define NV_VMALLOC_HEAP_MAX_SIZE NV_REG_STRING(__NV_VMALLOC_HEAP_MAX_SIZE) + +/* + * Option: IgnoreMMIOCheck + * + * Description: + * + * When this option is enabled, the NVIDIA kernel module will ignore + * MMIO limit check during device probe on VMWare ESXi kernel. This is + * typically necessary when VMware ESXi MMIO limit differs between any + * base version and its updates. Customer using updates can set regkey + * to avoid probe failure. + */ + +#define __NV_IGNORE_MMIO_CHECK IgnoreMMIOCheck +#define NV_REG_IGNORE_MMIO_CHECK NV_REG_STRING(__NV_IGNORE_MMIO_CHECK) + +/* + * Option: TCEBypassMode + * + * Description: + * + * When this option is enabled, the NVIDIA kernel module will attempt to setup + * all GPUs in "TCE bypass mode", in which DMA mappings of system memory bypass + * the IOMMU/TCE remapping hardware on IBM POWER systems. This is typically + * necessary for CUDA applications in which large system memory mappings may + * exceed the default TCE remapping capacity when operated in non-bypass mode. + * + * This option has no effect on non-POWER platforms. + * + * Possible Values: + * + * 0: system default TCE mode on all GPUs + * 1: enable TCE bypass mode on all GPUs + * 2: disable TCE bypass mode on all GPUs + */ +#define __NV_TCE_BYPASS_MODE TCEBypassMode +#define NV_REG_TCE_BYPASS_MODE NV_REG_STRING(__NV_TCE_BYPASS_MODE) + +#define NV_TCE_BYPASS_MODE_DEFAULT 0 +#define NV_TCE_BYPASS_MODE_ENABLE 1 +#define NV_TCE_BYPASS_MODE_DISABLE 2 + +/* + * Option: pci + * + * Description: + * + * On Unix platforms, per GPU based registry key can be specified as: + * NVreg_RegistryDwordsPerDevice="pci=DDDD:BB:DD.F,". + * where DDDD:BB:DD.F refers to Domain:Bus:Device.Function. + * We need this key "pci" to identify what follows next is a PCI BDF identifier, + * for which the registry keys are to be applied. + * + * This define is not used on non-UNIX platforms. + * + * Possible Formats for value: + * + * 1) bus:slot : Domain and function defaults to 0. + * 2) domain:bus:slot : Function defaults to 0. + * 3) domain:bus:slot.func : Complete PCI BDF identifier string. + */ +#define __NV_PCI_DEVICE_BDF pci +#define NV_REG_PCI_DEVICE_BDF NV_REG_STRING(__NV_PCI_DEVICE_BDF) + +/* + * Option: EnableStreamMemOPs + * + * Description: + * + * When this option is enabled, the CUDA driver will enable support for + * CUDA Stream Memory Operations in user-mode applications, which are so + * far required to be disabled by default due to limited support in + * devtools. + * + * Note: this is treated as a hint. MemOPs may still be left disabled by CUDA + * driver for other reasons. + * + * Possible Values: + * + * 0 = disable feature (default) + * 1 = enable feature + */ +#define __NV_ENABLE_STREAM_MEMOPS EnableStreamMemOPs +#define NV_REG_ENABLE_STREAM_MEMOPS NV_REG_STRING(__NV_ENABLE_STREAM_MEMOPS) + +/* + * Option: EnableUserNUMAManagement + * + * Description: + * + * When this option is enabled, the NVIDIA kernel module will require the + * user-mode NVIDIA Persistence daemon to manage the onlining and offlining + * of its NUMA device memory. + * + * This option has no effect on platforms that do not support onlining + * device memory to a NUMA node (this feature is only supported on certain + * POWER9 systems). + * + * Possible Values: + * + * 0: disable user-mode NUMA management + * 1: enable user-mode NUMA management (default) + */ +#define __NV_ENABLE_USER_NUMA_MANAGEMENT EnableUserNUMAManagement +#define NV_REG_ENABLE_USER_NUMA_MANAGEMENT NV_REG_STRING(__NV_ENABLE_USER_NUMA_MANAGEMENT) + +/* + * Option: GpuBlacklist + * + * Description: + * + * This option accepts a list of blacklisted GPUs, separated by commas, that + * cannot be attached or used. Each blacklisted GPU is identified by a UUID in + * the ASCII format with leading "GPU-". An exact match is required; no partial + * UUIDs. This regkey is deprecated and will be removed in the future. Use + * NV_REG_EXCLUDED_GPUS instead. + */ +#define __NV_GPU_BLACKLIST GpuBlacklist +#define NV_REG_GPU_BLACKLIST NV_REG_STRING(__NV_GPU_BLACKLIST) + +/* + * Option: ExcludedGpus + * + * Description: + * + * This option accepts a list of excluded GPUs, separated by commas, that + * cannot be attached or used. Each excluded GPU is identified by a UUID in + * the ASCII format with leading "GPU-". An exact match is required; no partial + * UUIDs. + */ +#define __NV_EXCLUDED_GPUS ExcludedGpus +#define NV_REG_EXCLUDED_GPUS NV_REG_STRING(__NV_EXCLUDED_GPUS) + +/* + * Option: NvLinkDisable + * + * Description: + * + * When this option is enabled, the NVIDIA kernel module will not attempt to + * initialize or train NVLink connections for any GPUs. System reboot is required + * for changes to take affect. + * + * This option has no effect if no GPUs support NVLink. + * + * Possible Values: + * + * 0: Do not disable NVLink (default) + * 1: Disable NVLink + */ +#define __NV_NVLINK_DISABLE NvLinkDisable +#define NV_REG_NVLINK_DISABLE NV_REG_STRING(__NV_NVLINK_DISABLE) + +/* + * Option: RestrictProfilingToAdminUsers + * + * Description: + * + * When this option is enabled, the NVIDIA kernel module will prevent users + * without administrative access (i.e., the CAP_SYS_ADMIN capability) from + * using GPU performance counters. + * + * Possible Values: + * + * 0: Do not restrict GPU counters (default) + * 1: Restrict GPU counters to system administrators only + */ + +#define __NV_RM_PROFILING_ADMIN_ONLY RmProfilingAdminOnly +#define __NV_RM_PROFILING_ADMIN_ONLY_PARAMETER RestrictProfilingToAdminUsers +#define NV_REG_RM_PROFILING_ADMIN_ONLY NV_REG_STRING(__NV_RM_PROFILING_ADMIN_ONLY) + +/* + * Option: TemporaryFilePath + * + * Description: + * + * When specified, this option changes the location in which the + * NVIDIA kernel module will create unnamed temporary files (e.g. to + * save the contents of video memory in). The indicated file must + * be a directory. By default, temporary files are created in /tmp. + */ +#define __NV_TEMPORARY_FILE_PATH TemporaryFilePath +#define NV_REG_TEMPORARY_FILE_PATH NV_REG_STRING(__NV_TEMPORARY_FILE_PATH) + +/* + * Option: PreserveVideoMemoryAllocations + * + * If enabled, this option prompts the NVIDIA kernel module to save and + * restore all video memory allocations across system power management + * cycles, i.e. suspend/resume and hibernate/restore. Otherwise, + * only select allocations are preserved. + * + * Possible Values: + * + * 0: Preserve only select video memory allocations (default) + * 1: Preserve all video memory allocations + */ +#define __NV_PRESERVE_VIDEO_MEMORY_ALLOCATIONS PreserveVideoMemoryAllocations +#define NV_REG_PRESERVE_VIDEO_MEMORY_ALLOCATIONS \ + NV_REG_STRING(__NV_PRESERVE_VIDEO_MEMORY_ALLOCATIONS) + +/* + * Option: EnableS0ixPowerManagement + * + * When this option is enabled, the NVIDIA driver will use S0ix-based + * power management for system suspend/resume, if both the platform and + * the GPU support S0ix. + * + * During system suspend, if S0ix is enabled and + * video memory usage is above the threshold configured by + * 'S0ixPowerManagementVideoMemoryThreshold', video memory will be kept + * in self-refresh mode while the rest of the GPU is powered down. + * + * Otherwise, the driver will copy video memory contents to system memory + * and power off the video memory along with the GPU. + * + * Possible Values: + * + * 0: Disable S0ix based power management (default) + * 1: Enable S0ix based power management + */ + +#define __NV_ENABLE_S0IX_POWER_MANAGEMENT EnableS0ixPowerManagement +#define NV_REG_ENABLE_S0IX_POWER_MANAGEMENT \ + NV_REG_STRING(__NV_ENABLE_S0IX_POWER_MANAGEMENT) + +/* + * Option: S0ixPowerManagementVideoMemoryThreshold + * + * This option controls the threshold that the NVIDIA driver will use during + * S0ix-based system power management. + * + * When S0ix is enabled and the system is suspended, the driver will + * compare the amount of video memory in use with this threshold, + * to decide whether to keep video memory in self-refresh or copy video + * memory content to system memory. + * + * See the 'EnableS0ixPowerManagement' option. + * + * Values are expressed in Megabytes (1048576 bytes). + * + * Default value for this option is 256MB. + * + */ +#define __NV_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD \ + S0ixPowerManagementVideoMemoryThreshold +#define NV_REG_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD \ + NV_REG_STRING(__NV_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD) + +/* + * Option: DynamicPowerManagement + * + * This option controls how aggressively the NVIDIA kernel module will manage + * GPU power through kernel interfaces. + * + * Possible Values: + * + * 0: Never allow the GPU to be powered down (default). + * 1: Power down the GPU when it is not initialized. + * 2: Power down the GPU after it has been inactive for some time. + * 3: (Default) Power down the GPU after a period of inactivity (i.e., + * mode 2) on Ampere or later notebooks. Otherwise, do not power down + * the GPU. + */ +#define __NV_DYNAMIC_POWER_MANAGEMENT DynamicPowerManagement +#define NV_REG_DYNAMIC_POWER_MANAGEMENT \ + NV_REG_STRING(__NV_DYNAMIC_POWER_MANAGEMENT) + +#define NV_REG_DYNAMIC_POWER_MANAGEMENT_NEVER 0 +#define NV_REG_DYNAMIC_POWER_MANAGEMENT_COARSE 1 +#define NV_REG_DYNAMIC_POWER_MANAGEMENT_FINE 2 +#define NV_REG_DYNAMIC_POWER_MANAGEMENT_DEFAULT 3 + +/* + * Option: DynamicPowerManagementVideoMemoryThreshold + * + * This option controls the threshold that the NVIDIA driver will use + * when selecting the dynamic power management scheme. + * + * When the driver detects that the GPU is idle, it will compare the amount + * of video memory in use with this threshold. + * + * If the current video memory usage is less than the threshold, the + * driver may preserve video memory contents in system memory and power off + * the video memory along with the GPU itself, if supported. Otherwise, + * the video memory will be kept in self-refresh mode while powering down + * the rest of the GPU, if supported. + * + * Values are expressed in Megabytes (1048576 bytes). + * + * If the requested value is greater than 200MB (the default), then it + * will be capped to 200MB. + */ +#define __NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD \ + DynamicPowerManagementVideoMemoryThreshold +#define NV_REG_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD \ + NV_REG_STRING(__NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD) + +/* + * Option: RegisterPCIDriver + * + * Description: + * + * When this option is enabled, the NVIDIA driver will register with + * PCI subsystem. + * + * Possible values: + * + * 1 - register as PCI driver (default) + * 0 - do not register as PCI driver + */ + +#define __NV_REGISTER_PCI_DRIVER RegisterPCIDriver +#define NV_REG_REGISTER_PCI_DRIVER NV_REG_STRING(__NV_REGISTER_PCI_DRIVER) + +/* + * Option: EnablePCIERelaxedOrderingMode + * + * Description: + * + * When this option is enabled, the registry key RmSetPCIERelaxedOrdering will + * be set to NV_REG_STR_RM_SET_PCIE_TLP_RELAXED_ORDERING_FORCE_ENABLE, causing + * every device to set the relaxed ordering bit to 1 in all outbound MWr + * transaction-layer packets. This is equivalent to setting the regkey to + * FORCE_ENABLE as a non-per-device registry key. + * + * Possible values: + * 0 - Do not enable PCIe TLP relaxed ordering bit-setting (default) + * 1 - Enable PCIe TLP relaxed ordering bit-setting + */ +#define __NV_ENABLE_PCIE_RELAXED_ORDERING_MODE EnablePCIERelaxedOrderingMode +#define NV_REG_ENABLE_PCIE_RELAXED_ORDERING_MODE \ + NV_REG_STRING(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE) + +/* + * Option: EnableGpuFirmware + * + * Description: + * + * When this option is enabled, the NVIDIA driver will enable use of GPU + * firmware. + * + * Possible mode values: + * 0 - Do not enable GPU firmware + * 1 - Enable GPU firmware + * 2 - (Default) Use the default enablement policy for GPU firmware + * + * Setting this to anything other than 2 will alter driver firmware- + * enablement policies, possibly disabling GPU firmware where it would + * have otherwise been enabled by default. + * + * If this key is set globally to the system, the driver may still attempt + * to apply some policies to maintain uniform firmware modes across all + * GPUS. This may result in the driver failing initialization on some GPUs + * to maintain such a policy. + * + * If this key is set using NVreg_RegistryDwordsPerDevice, then the driver + * will attempt to honor whatever configuration is specified without applying + * additional policies. This may also result in failed GPU initialzations if + * the configuration is not possible (for example if the firmware is missing + * from the filesystem, or the GPU is not capable). + * + * Policy bits: + * + * POLICY_ALLOW_FALLBACK: + * As the normal behavior is to fail GPU initialization if this registry + * entry is set in such a way that results in an invalid configuration, if + * instead the user would like the driver to automatically try to fallback + * to initializing the failing GPU with firmware disabled, then this bit can + * be set (ex: 0x11 means try to enable GPU firmware but fall back if needed). + * Note that this can result in a mixed mode configuration (ex: GPU0 has + * firmware enabled, but GPU1 does not). + * + */ + +#define __NV_ENABLE_GPU_FIRMWARE EnableGpuFirmware +#define NV_REG_ENABLE_GPU_FIRMWARE NV_REG_STRING(__NV_ENABLE_GPU_FIRMWARE) + +#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_MASK 0x0000000F +#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_DISABLED 0x00000000 +#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_ENABLED 0x00000001 +#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_DEFAULT 0x00000002 + +#define NV_REG_ENABLE_GPU_FIRMWARE_POLICY_MASK 0x000000F0 +#define NV_REG_ENABLE_GPU_FIRMWARE_POLICY_ALLOW_FALLBACK 0x00000010 + +#define NV_REG_ENABLE_GPU_FIRMWARE_DEFAULT_VALUE 0x00000012 +#define NV_REG_ENABLE_GPU_FIRMWARE_INVALID_VALUE 0xFFFFFFFF + +/* + * Option: EnableGpuFirmwareLogs + * + * When this option is enabled, the NVIDIA driver will send GPU firmware logs + * to the system log, when possible. + * + * Possible values: + * 0 - Do not send GPU firmware logs to the system log + * 1 - Enable sending of GPU firmware logs to the system log + * 2 - (Default) Enable sending of GPU firmware logs to the system log for + * the debug kernel driver build only + */ +#define __NV_ENABLE_GPU_FIRMWARE_LOGS EnableGpuFirmwareLogs +#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS NV_REG_STRING(__NV_ENABLE_GPU_FIRMWARE_LOGS) + +#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_DISABLE 0x00000000 +#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE 0x00000001 +#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG 0x00000002 + +/* + * Option: EnableDbgBreakpoint + * + * When this option is set to a non-zero value, and the kernel is configured + * appropriately, assertions within resman will trigger a CPU breakpoint (e.g., + * INT3 on x86_64), assumed to be caught by an attached debugger. + * + * When this option is set to the value zero (the default), assertions within + * resman will print to the system log, but no CPU breakpoint will be triggered. + */ +#define __NV_ENABLE_DBG_BREAKPOINT EnableDbgBreakpoint + + +/* + * Option: OpenRmEnableUnsupportedGpus + * + * Open nvidia.ko support for features beyond what is used on Data Center GPUs + * is still fairly immature, so for now require users to opt into use of open + * nvidia.ko with a special registry key, if not on a Data Center GPU. + */ + +#define __NV_OPENRM_ENABLE_UNSUPPORTED_GPUS OpenRmEnableUnsupportedGpus +#define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS NV_REG_STRING(__NV_OPENRM_ENABLE_UNSUPPORTED_GPUS) +#define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DISABLE 0x00000000 +#define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_ENABLE 0x00000001 +#define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DEFAULT NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DISABLE + +/* + * Option: NVreg_DmaRemapPeerMmio + * + * Description: + * + * When this option is enabled, the NVIDIA driver will use device driver + * APIs provided by the Linux kernel for DMA-remapping part of a device's + * MMIO region to another device, creating e.g., IOMMU mappings as necessary. + * When this option is disabled, the NVIDIA driver will instead only apply a + * fixed offset, which may be zero, to CPU physical addresses to produce the + * DMA address for the peer's MMIO region, and no IOMMU mappings will be + * created. + * + * This option only affects peer MMIO DMA mappings, and not system memory + * mappings. + * + * Possible Values: + * 0 = disable dynamic DMA remapping of peer MMIO regions + * 1 = enable dynamic DMA remapping of peer MMIO regions (default) + */ +#define __NV_DMA_REMAP_PEER_MMIO DmaRemapPeerMmio +#define NV_DMA_REMAP_PEER_MMIO NV_REG_STRING(__NV_DMA_REMAP_PEER_MMIO) +#define NV_DMA_REMAP_PEER_MMIO_DISABLE 0x00000000 +#define NV_DMA_REMAP_PEER_MMIO_ENABLE 0x00000001 + +#if defined(NV_DEFINE_REGISTRY_KEY_TABLE) + +/* + *---------registry key parameter declarations-------------- + */ + +NV_DEFINE_REG_ENTRY(__NV_RESMAN_DEBUG_LEVEL, ~0); +NV_DEFINE_REG_ENTRY(__NV_RM_LOGON_RC, 1); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_MODIFY_DEVICE_FILES, 1); +NV_DEFINE_REG_ENTRY(__NV_DEVICE_FILE_UID, 0); +NV_DEFINE_REG_ENTRY(__NV_DEVICE_FILE_GID, 0); +NV_DEFINE_REG_ENTRY(__NV_DEVICE_FILE_MODE, 0666); +NV_DEFINE_REG_ENTRY(__NV_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS, 1); +NV_DEFINE_REG_ENTRY(__NV_USE_PAGE_ATTRIBUTE_TABLE, ~0); +NV_DEFINE_REG_ENTRY(__NV_ENABLE_PCIE_GEN3, 0); +NV_DEFINE_REG_ENTRY(__NV_ENABLE_MSI, 1); +NV_DEFINE_REG_ENTRY(__NV_TCE_BYPASS_MODE, NV_TCE_BYPASS_MODE_DEFAULT); +NV_DEFINE_REG_ENTRY(__NV_ENABLE_STREAM_MEMOPS, 0); +NV_DEFINE_REG_ENTRY(__NV_RM_PROFILING_ADMIN_ONLY_PARAMETER, 1); +NV_DEFINE_REG_ENTRY(__NV_PRESERVE_VIDEO_MEMORY_ALLOCATIONS, 0); +NV_DEFINE_REG_ENTRY(__NV_ENABLE_S0IX_POWER_MANAGEMENT, 0); +NV_DEFINE_REG_ENTRY(__NV_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD, 256); +NV_DEFINE_REG_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT, 3); +NV_DEFINE_REG_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD, 200); +NV_DEFINE_REG_ENTRY(__NV_ENABLE_GPU_FIRMWARE, NV_REG_ENABLE_GPU_FIRMWARE_DEFAULT_VALUE); +NV_DEFINE_REG_ENTRY(__NV_ENABLE_GPU_FIRMWARE_LOGS, NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG); +NV_DEFINE_REG_ENTRY(__NV_OPENRM_ENABLE_UNSUPPORTED_GPUS, NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DEFAULT); + +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_USER_NUMA_MANAGEMENT, 1); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_MEMORY_POOL_SIZE, 0); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_KMALLOC_HEAP_MAX_SIZE, 0); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_VMALLOC_HEAP_MAX_SIZE, 0); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_IGNORE_MMIO_CHECK, 0); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_NVLINK_DISABLE, 0); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE, 0); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_REGISTER_PCI_DRIVER, 1); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_DBG_BREAKPOINT, 0); + +NV_DEFINE_REG_STRING_ENTRY(__NV_REGISTRY_DWORDS, NULL); +NV_DEFINE_REG_STRING_ENTRY(__NV_REGISTRY_DWORDS_PER_DEVICE, NULL); +NV_DEFINE_REG_STRING_ENTRY(__NV_RM_MSG, NULL); +NV_DEFINE_REG_STRING_ENTRY(__NV_GPU_BLACKLIST, NULL); +NV_DEFINE_REG_STRING_ENTRY(__NV_TEMPORARY_FILE_PATH, NULL); +NV_DEFINE_REG_STRING_ENTRY(__NV_EXCLUDED_GPUS, NULL); +NV_DEFINE_REG_ENTRY(__NV_DMA_REMAP_PEER_MMIO, NV_DMA_REMAP_PEER_MMIO_ENABLE); + +/* + *----------------registry database definition---------------------- + */ + +/* + * You can enable any of the registry options disabled by default by + * editing their respective entries in the table below. The last field + * determines if the option is considered valid - in order for the + * changes to take effect, you need to recompile and reload the NVIDIA + * kernel module. + */ +nv_parm_t nv_parms[] = { + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_RESMAN_DEBUG_LEVEL), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_RM_LOGON_RC), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_MODIFY_DEVICE_FILES), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DEVICE_FILE_UID), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DEVICE_FILE_GID), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DEVICE_FILE_MODE), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_USE_PAGE_ATTRIBUTE_TABLE), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_MSI), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_PCIE_GEN3), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_MEMORY_POOL_SIZE), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_KMALLOC_HEAP_MAX_SIZE), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_VMALLOC_HEAP_MAX_SIZE), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_IGNORE_MMIO_CHECK), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_TCE_BYPASS_MODE), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_STREAM_MEMOPS), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_USER_NUMA_MANAGEMENT), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_NVLINK_DISABLE), + NV_DEFINE_PARAMS_TABLE_ENTRY_CUSTOM_NAME(__NV_RM_PROFILING_ADMIN_ONLY, + __NV_RM_PROFILING_ADMIN_ONLY_PARAMETER), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_PRESERVE_VIDEO_MEMORY_ALLOCATIONS), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_S0IX_POWER_MANAGEMENT), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_REGISTER_PCI_DRIVER), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_GPU_FIRMWARE), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_GPU_FIRMWARE_LOGS), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_DBG_BREAKPOINT), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_OPENRM_ENABLE_UNSUPPORTED_GPUS), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DMA_REMAP_PEER_MMIO), + {NULL, NULL} +}; + +#elif defined(NVRM) + +extern nv_parm_t nv_parms[]; + +#endif /* NV_DEFINE_REGISTRY_KEY_TABLE */ + +#endif /* _RM_REG_H_ */ diff --git a/userspace/sdks/nv525/nvalloc/unix/include/nv-unix-nvos-params-wrappers.h b/userspace/sdks/nv525/nvalloc/unix/include/nv-unix-nvos-params-wrappers.h new file mode 100644 index 0000000..02b0156 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/include/nv-unix-nvos-params-wrappers.h @@ -0,0 +1,49 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NV_UNIX_NVOS_PARAMS_WRAPPERS_H_ +#define _NV_UNIX_NVOS_PARAMS_WRAPPERS_H_ + +#include + +/* + * This is a wrapper for NVOS02_PARAMETERS with file descriptor + */ + +typedef struct +{ + NVOS02_PARAMETERS params; + int fd; +} nv_ioctl_nvos02_parameters_with_fd; + +/* + * This is a wrapper for NVOS33_PARAMETERS with file descriptor + */ +typedef struct +{ + NVOS33_PARAMETERS params; + int fd; +} nv_ioctl_nvos33_parameters_with_fd; + +#endif // _NV_UNIX_NVOS_PARAMS_WRAPPERS_H_ + diff --git a/userspace/sdks/nv525/nvalloc/unix/include/nv.h b/userspace/sdks/nv525/nvalloc/unix/include/nv.h new file mode 100644 index 0000000..5cb4d1b --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/include/nv.h @@ -0,0 +1,1058 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _NV_H_ +#define _NV_H_ + + + +#include + +#if defined(NV_KERNEL_INTERFACE_LAYER) && defined(__FreeBSD__) + #include // NULL +#elif defined(NV_KERNEL_INTERFACE_LAYER) && defined(NV_LINUX) + #include // NULL +#else + #include // NULL +#endif + +#include +#include "nv_stdarg.h" +#include +#include +#include +#include + +extern nv_cap_t *nvidia_caps_root; + +extern const NvBool nv_is_rm_firmware_supported_os; + +#include + +/* NVIDIA's reserved major character device number (Linux). */ +#define NV_MAJOR_DEVICE_NUMBER 195 + +#define GPU_UUID_LEN (16) + +/* + * Buffer size for an ASCII UUID: We need 2 digits per byte, plus space + * for "GPU", 5 dashes, and '\0' termination: + */ +#define GPU_UUID_ASCII_LEN (GPU_UUID_LEN * 2 + 9) + +/* + * #define an absolute maximum used as a sanity check for the + * NV_ESC_IOCTL_XFER_CMD ioctl() size argument. + */ +#define NV_ABSOLUTE_MAX_IOCTL_SIZE 16384 + +/* + * Solaris provides no more than 8 bits for the argument size in + * the ioctl() command encoding; make sure we don't exceed this + * limit. + */ +#define __NV_IOWR_ASSERT(type) ((sizeof(type) <= NV_PLATFORM_MAX_IOCTL_SIZE) ? 1 : -1) +#define __NV_IOWR(nr, type) ({ \ + typedef char __NV_IOWR_TYPE_SIZE_ASSERT[__NV_IOWR_ASSERT(type)]; \ + _IOWR(NV_IOCTL_MAGIC, (nr), type); \ +}) + +#define NV_PCI_DEV_FMT "%04x:%02x:%02x.%x" +#define NV_PCI_DEV_FMT_ARGS(nv) (nv)->pci_info.domain, (nv)->pci_info.bus, \ + (nv)->pci_info.slot, (nv)->pci_info.function + +#define NV_RM_DEVICE_INTR_ADDRESS 0x100 + +/*! + * @brief The order of the display clocks in the below defined enum + * should be synced with below mapping array and macro. + * All four should be updated simultaneously in case + * of removal or addition of clocks in below order. + * Also, TEGRASOC_WHICH_CLK_MAX is used in various places + * in below mentioned files. + * arch/nvalloc/unix/Linux/nv-linux.h + * + * arch/nvalloc/unix/src/os.c + * dispClkMapRmToOsArr[] = {...}; + * + * arch/nvalloc/unix/Linux/nv-clk.c + * osMapClk[] = {...}; + * + */ +typedef enum _TEGRASOC_WHICH_CLK +{ + TEGRASOC_WHICH_CLK_NVDISPLAYHUB, + TEGRASOC_WHICH_CLK_NVDISPLAY_DISP, + TEGRASOC_WHICH_CLK_NVDISPLAY_P0, + TEGRASOC_WHICH_CLK_NVDISPLAY_P1, + TEGRASOC_WHICH_CLK_DPAUX0, + TEGRASOC_WHICH_CLK_FUSE, + TEGRASOC_WHICH_CLK_DSIPLL_VCO, + TEGRASOC_WHICH_CLK_DSIPLL_CLKOUTPN, + TEGRASOC_WHICH_CLK_DSIPLL_CLKOUTA, + TEGRASOC_WHICH_CLK_SPPLL0_VCO, + TEGRASOC_WHICH_CLK_SPPLL0_CLKOUTPN, + TEGRASOC_WHICH_CLK_SPPLL0_CLKOUTA, + TEGRASOC_WHICH_CLK_SPPLL0_CLKOUTB, + TEGRASOC_WHICH_CLK_SPPLL0_DIV10, + TEGRASOC_WHICH_CLK_SPPLL0_DIV25, + TEGRASOC_WHICH_CLK_SPPLL0_DIV27, + TEGRASOC_WHICH_CLK_SPPLL1_VCO, + TEGRASOC_WHICH_CLK_SPPLL1_CLKOUTPN, + TEGRASOC_WHICH_CLK_SPPLL1_DIV27, + TEGRASOC_WHICH_CLK_VPLL0_REF, + TEGRASOC_WHICH_CLK_VPLL0, + TEGRASOC_WHICH_CLK_VPLL1, + TEGRASOC_WHICH_CLK_NVDISPLAY_P0_REF, + TEGRASOC_WHICH_CLK_RG0, + TEGRASOC_WHICH_CLK_RG1, + TEGRASOC_WHICH_CLK_DISPPLL, + TEGRASOC_WHICH_CLK_DISPHUBPLL, + TEGRASOC_WHICH_CLK_DSI_LP, + TEGRASOC_WHICH_CLK_DSI_CORE, + TEGRASOC_WHICH_CLK_DSI_PIXEL, + TEGRASOC_WHICH_CLK_PRE_SOR0, + TEGRASOC_WHICH_CLK_PRE_SOR1, + TEGRASOC_WHICH_CLK_DP_LINK_REF, + TEGRASOC_WHICH_CLK_SOR_LINKA_INPUT, + TEGRASOC_WHICH_CLK_SOR_LINKA_AFIFO, + TEGRASOC_WHICH_CLK_SOR_LINKA_AFIFO_M, + TEGRASOC_WHICH_CLK_RG0_M, + TEGRASOC_WHICH_CLK_RG1_M, + TEGRASOC_WHICH_CLK_SOR0_M, + TEGRASOC_WHICH_CLK_SOR1_M, + TEGRASOC_WHICH_CLK_PLLHUB, + TEGRASOC_WHICH_CLK_SOR0, + TEGRASOC_WHICH_CLK_SOR1, + TEGRASOC_WHICH_CLK_SOR_PAD_INPUT, + TEGRASOC_WHICH_CLK_PRE_SF0, + TEGRASOC_WHICH_CLK_SF0, + TEGRASOC_WHICH_CLK_SF1, + TEGRASOC_WHICH_CLK_DSI_PAD_INPUT, + TEGRASOC_WHICH_CLK_PRE_SOR0_REF, + TEGRASOC_WHICH_CLK_PRE_SOR1_REF, + TEGRASOC_WHICH_CLK_SOR0_PLL_REF, + TEGRASOC_WHICH_CLK_SOR1_PLL_REF, + TEGRASOC_WHICH_CLK_SOR0_REF, + TEGRASOC_WHICH_CLK_SOR1_REF, + TEGRASOC_WHICH_CLK_OSC, + TEGRASOC_WHICH_CLK_DSC, + TEGRASOC_WHICH_CLK_MAUD, + TEGRASOC_WHICH_CLK_AZA_2XBIT, + TEGRASOC_WHICH_CLK_AZA_BIT, + TEGRASOC_WHICH_CLK_MIPI_CAL, + TEGRASOC_WHICH_CLK_UART_FST_MIPI_CAL, + TEGRASOC_WHICH_CLK_SOR0_DIV, + TEGRASOC_WHICH_CLK_DISP_ROOT, + TEGRASOC_WHICH_CLK_HUB_ROOT, + TEGRASOC_WHICH_CLK_PLLA_DISP, + TEGRASOC_WHICH_CLK_PLLA_DISPHUB, + TEGRASOC_WHICH_CLK_PLLA, + TEGRASOC_WHICH_CLK_MAX, // TEGRASOC_WHICH_CLK_MAX is defined for boundary checks only. +} TEGRASOC_WHICH_CLK; + +#ifdef NVRM + +extern const char *pNVRM_ID; + +/* + * ptr arithmetic convenience + */ + +typedef union +{ + volatile NvV8 Reg008[1]; + volatile NvV16 Reg016[1]; + volatile NvV32 Reg032[1]; +} nv_hwreg_t, * nv_phwreg_t; + + +#define NVRM_PCICFG_NUM_BARS 6 +#define NVRM_PCICFG_BAR_OFFSET(i) (0x10 + (i) * 4) +#define NVRM_PCICFG_BAR_REQTYPE_MASK 0x00000001 +#define NVRM_PCICFG_BAR_REQTYPE_MEMORY 0x00000000 +#define NVRM_PCICFG_BAR_MEMTYPE_MASK 0x00000006 +#define NVRM_PCICFG_BAR_MEMTYPE_64BIT 0x00000004 +#define NVRM_PCICFG_BAR_ADDR_MASK 0xfffffff0 + +#define NVRM_PCICFG_NUM_DWORDS 16 + +#define NV_GPU_NUM_BARS 3 +#define NV_GPU_BAR_INDEX_REGS 0 +#define NV_GPU_BAR_INDEX_FB 1 +#define NV_GPU_BAR_INDEX_IMEM 2 + +typedef struct +{ + NvU64 cpu_address; + NvU64 size; + NvU32 offset; + NvU32 *map; + nv_phwreg_t map_u; +} nv_aperture_t; + +typedef struct +{ + char *name; + NvU32 *data; +} nv_parm_t; + +#define NV_RM_PAGE_SHIFT 12 +#define NV_RM_PAGE_SIZE (1 << NV_RM_PAGE_SHIFT) +#define NV_RM_PAGE_MASK (NV_RM_PAGE_SIZE - 1) + +#define NV_RM_TO_OS_PAGE_SHIFT (os_page_shift - NV_RM_PAGE_SHIFT) +#define NV_RM_PAGES_PER_OS_PAGE (1U << NV_RM_TO_OS_PAGE_SHIFT) +#define NV_RM_PAGES_TO_OS_PAGES(count) \ + ((((NvUPtr)(count)) >> NV_RM_TO_OS_PAGE_SHIFT) + \ + ((((count) & ((1 << NV_RM_TO_OS_PAGE_SHIFT) - 1)) != 0) ? 1 : 0)) + +#if defined(NVCPU_X86_64) +#define NV_STACK_SIZE (NV_RM_PAGE_SIZE * 3) +#else +#define NV_STACK_SIZE (NV_RM_PAGE_SIZE * 2) +#endif + +typedef struct nvidia_stack_s +{ + NvU32 size; + void *top; + NvU8 stack[NV_STACK_SIZE-16] __attribute__ ((aligned(16))); +} nvidia_stack_t; + +/* + * TODO: Remove once all UNIX layers have been converted to use nvidia_stack_t + */ +typedef nvidia_stack_t nv_stack_t; + +typedef struct nv_file_private_t nv_file_private_t; + +/* + * this is a wrapper for unix events + * unlike the events that will be returned to clients, this includes + * kernel-specific data, such as file pointer, etc.. + */ +typedef struct nv_event_s +{ + NvHandle hParent; + NvHandle hObject; + NvU32 index; + NvU32 info32; + NvU16 info16; + nv_file_private_t *nvfp; /* per file-descriptor data pointer */ + NvU32 fd; + NvBool active; /* whether the event should be signaled */ + NvU32 refcount; /* count of associated RM events */ + struct nv_event_s *next; +} nv_event_t; + +typedef struct nv_kern_mapping_s +{ + void *addr; + NvU64 size; + NvU32 modeFlag; + struct nv_kern_mapping_s *next; +} nv_kern_mapping_t; + +typedef struct nv_usermap_access_params_s +{ + NvU64 addr; + NvU64 size; + NvU64 offset; + NvU64 *page_array; + NvU64 num_pages; + NvU64 mmap_start; + NvU64 mmap_size; + NvU64 access_start; + NvU64 access_size; + NvU64 remap_prot_extra; + NvBool contig; + NvU32 caching; +} nv_usermap_access_params_t; + +/* + * It stores mapping context per mapping + */ +typedef struct nv_alloc_mapping_context_s { + void *alloc; + NvU64 page_index; + NvU64 *page_array; + NvU64 num_pages; + NvU64 mmap_start; + NvU64 mmap_size; + NvU64 access_start; + NvU64 access_size; + NvU64 remap_prot_extra; + NvU32 prot; + NvBool valid; + NvU32 caching; +} nv_alloc_mapping_context_t; + +typedef enum +{ + NV_SOC_IRQ_DISPLAY_TYPE = 0x1, + NV_SOC_IRQ_DPAUX_TYPE, + NV_SOC_IRQ_GPIO_TYPE, + NV_SOC_IRQ_HDACODEC_TYPE, + NV_SOC_IRQ_INVALID_TYPE +} nv_soc_irq_type_t; + +/* + * It stores interrupt numbers and interrupt type and private data + */ +typedef struct nv_soc_irq_info_s { + NvU32 irq_num; + nv_soc_irq_type_t irq_type; + NvBool bh_pending; + union { + NvU32 gpio_num; + NvU32 dpaux_instance; + } irq_data; +} nv_soc_irq_info_t; + +#define NV_MAX_SOC_IRQS 6 +#define NV_MAX_DPAUX_NUM_DEVICES 4 +#define NV_MAX_SOC_DPAUX_NUM_DEVICES 2 // From SOC_DEV_MAPPING + +#define NV_IGPU_LEGACY_STALL_IRQ 70 +#define NV_IGPU_MAX_STALL_IRQS 3 +#define NV_IGPU_MAX_NONSTALL_IRQS 1 +/* + * per device state + */ + +/* DMA-capable device data, defined by kernel interface layer */ +typedef struct nv_dma_device nv_dma_device_t; + +typedef struct nv_state_t +{ + void *priv; /* private data */ + void *os_state; /* os-specific device state */ + + int flags; + + /* PCI config info */ + nv_pci_info_t pci_info; + NvU16 subsystem_id; + NvU16 subsystem_vendor; + NvU32 gpu_id; + NvU32 iovaspace_id; + struct + { + NvBool valid; + NvU8 uuid[GPU_UUID_LEN]; + } nv_uuid_cache; + void *handle; + + NvU32 pci_cfg_space[NVRM_PCICFG_NUM_DWORDS]; + + /* physical characteristics */ + nv_aperture_t bars[NV_GPU_NUM_BARS]; + nv_aperture_t *regs; + nv_aperture_t *dpaux[NV_MAX_DPAUX_NUM_DEVICES]; + nv_aperture_t *hdacodec_regs; + nv_aperture_t *mipical_regs; + nv_aperture_t *fb, ud; + nv_aperture_t *simregs; + nv_aperture_t *emc_regs; + + NvU32 num_dpaux_instance; + NvU32 interrupt_line; + NvU32 dpaux_irqs[NV_MAX_DPAUX_NUM_DEVICES]; + nv_soc_irq_info_t soc_irq_info[NV_MAX_SOC_IRQS]; + NvS32 current_soc_irq; + NvU32 num_soc_irqs; + NvU32 hdacodec_irq; + NvU8 *soc_dcb_blob; + NvU32 soc_dcb_size; + NvU32 disp_sw_soc_chip_id; + + NvU32 igpu_stall_irq[NV_IGPU_MAX_STALL_IRQS]; + NvU32 igpu_nonstall_irq; + NvU32 num_stall_irqs; + NvU64 dma_mask; + + NvBool primary_vga; + + NvU32 sim_env; + + NvU32 rc_timer_enabled; + + /* list of events allocated for this device */ + nv_event_t *event_list; + + /* lock to protect event_list */ + void *event_spinlock; + + nv_kern_mapping_t *kern_mappings; + + /* Kernel interface DMA device data */ + nv_dma_device_t *dma_dev; + nv_dma_device_t *niso_dma_dev; + + /* + * Per-GPU queue. The actual queue object is usually allocated in the + * arch-specific parent structure (e.g. nv_linux_state_t), and this + * pointer just points to it. + */ + struct os_work_queue *queue; + + /* For loading RM as a firmware (DCE or GSP) client */ + NvBool request_firmware; /* request firmware from the OS */ + NvBool request_fw_client_rm; /* attempt to init RM as FW a client */ + NvBool allow_fallback_to_monolithic_rm; /* allow fallback to monolithic RM if FW client RM doesn't work out */ + NvBool enable_firmware_logs; /* attempt to enable firmware log decoding/printing */ + + /* Variable to track, if nvidia_remove is called */ + NvBool removed; + + NvBool console_device; + + /* Variable to track, if GPU is external GPU */ + NvBool is_external_gpu; + + /* Variable to track, if regkey PreserveVideoMemoryAllocations is set */ + NvBool preserve_vidmem_allocations; + + /* Variable to force allocation of 32-bit addressable memory */ + NvBool force_dma32_alloc; + + /* PCI power state should be D0 during system suspend */ + NvBool d0_state_in_suspend; + + /* Current cyclestats client and context */ + NvU32 profiler_owner; + void *profiler_context; + + /* + * RMAPI objects to use in the OS layer to talk to core RM. + * + * Note that we only need to store one subdevice handle: in SLI, we will + * have a separate nv_state_t per physical GPU. + */ + struct { + NvHandle hClient; + NvHandle hDevice; + NvHandle hSubDevice; + NvHandle hI2C; + NvHandle hDisp; + } rmapi; + + /* Bool to check if ISO iommu enabled */ + NvBool iso_iommu_present; + + /* Bool to check if dma-buf is supported */ + NvBool dma_buf_supported; + + NvBool printed_openrm_enable_unsupported_gpus_error; + + /* Check if NVPCF DSM function is implemented under NVPCF or GPU device scope */ + NvBool nvpcf_dsm_in_gpu_scope; + + /* Bool to check if the device received a shutdown notification */ + NvBool is_shutdown; + +} nv_state_t; + +// These define need to be in sync with defines in system.h +#define OS_TYPE_LINUX 0x1 +#define OS_TYPE_FREEBSD 0x2 +#define OS_TYPE_SUNOS 0x3 +#define OS_TYPE_VMWARE 0x4 + +#define NVFP_TYPE_NONE 0x0 +#define NVFP_TYPE_REFCOUNTED 0x1 +#define NVFP_TYPE_REGISTERED 0x2 + +struct nv_file_private_t +{ + NvHandle *handles; + NvU16 maxHandles; + NvU32 deviceInstance; + NvU8 metadata[64]; + + nv_file_private_t *ctl_nvfp; + void *ctl_nvfp_priv; + NvU32 register_or_refcount; +}; + +// Forward define the gpu ops structures +typedef struct gpuSession *nvgpuSessionHandle_t; +typedef struct gpuDevice *nvgpuDeviceHandle_t; +typedef struct gpuAddressSpace *nvgpuAddressSpaceHandle_t; +typedef struct gpuChannel *nvgpuChannelHandle_t; +typedef struct UvmGpuChannelInfo_tag *nvgpuChannelInfo_t; +typedef struct UvmGpuChannelAllocParams_tag nvgpuChannelAllocParams_t; +typedef struct UvmGpuCaps_tag *nvgpuCaps_t; +typedef struct UvmGpuCopyEnginesCaps_tag *nvgpuCesCaps_t; +typedef struct UvmGpuAddressSpaceInfo_tag *nvgpuAddressSpaceInfo_t; +typedef struct UvmGpuAllocInfo_tag *nvgpuAllocInfo_t; +typedef struct UvmGpuP2PCapsParams_tag *nvgpuP2PCapsParams_t; +typedef struct UvmGpuFbInfo_tag *nvgpuFbInfo_t; +typedef struct UvmGpuEccInfo_tag *nvgpuEccInfo_t; +typedef struct UvmGpuFaultInfo_tag *nvgpuFaultInfo_t; +typedef struct UvmGpuAccessCntrInfo_tag *nvgpuAccessCntrInfo_t; +typedef struct UvmGpuAccessCntrConfig_tag *nvgpuAccessCntrConfig_t; +typedef struct UvmGpuInfo_tag nvgpuInfo_t; +typedef struct UvmGpuClientInfo_tag nvgpuClientInfo_t; +typedef struct UvmPmaAllocationOptions_tag *nvgpuPmaAllocationOptions_t; +typedef struct UvmPmaStatistics_tag *nvgpuPmaStatistics_t; +typedef struct UvmGpuMemoryInfo_tag *nvgpuMemoryInfo_t; +typedef struct UvmGpuExternalMappingInfo_tag *nvgpuExternalMappingInfo_t; +typedef struct UvmGpuChannelResourceInfo_tag *nvgpuChannelResourceInfo_t; +typedef struct UvmGpuChannelInstanceInfo_tag *nvgpuChannelInstanceInfo_t; +typedef struct UvmGpuChannelResourceBindParams_tag *nvgpuChannelResourceBindParams_t; +typedef struct UvmGpuPagingChannelAllocParams_tag nvgpuPagingChannelAllocParams_t; +typedef struct UvmGpuPagingChannel_tag *nvgpuPagingChannelHandle_t; +typedef struct UvmGpuPagingChannelInfo_tag *nvgpuPagingChannelInfo_t; +typedef enum UvmPmaGpuMemoryType_tag nvgpuGpuMemoryType_t; +typedef NV_STATUS (*nvPmaEvictPagesCallback)(void *, NvU32, NvU64 *, NvU32, NvU64, NvU64, nvgpuGpuMemoryType_t); +typedef NV_STATUS (*nvPmaEvictRangeCallback)(void *, NvU64, NvU64, nvgpuGpuMemoryType_t); + +/* + * flags + */ + +#define NV_FLAG_OPEN 0x0001 +#define NV_FLAG_EXCLUDE 0x0002 +#define NV_FLAG_CONTROL 0x0004 +// Unused 0x0008 +#define NV_FLAG_SOC_DISPLAY 0x0010 +#define NV_FLAG_USES_MSI 0x0020 +#define NV_FLAG_USES_MSIX 0x0040 +#define NV_FLAG_PASSTHRU 0x0080 +#define NV_FLAG_SUSPENDED 0x0100 +#define NV_FLAG_SOC_IGPU 0x0200 +// Unused 0x0400 +#define NV_FLAG_PERSISTENT_SW_STATE 0x0800 +#define NV_FLAG_IN_RECOVERY 0x1000 +// Unused 0x2000 +#define NV_FLAG_UNBIND_LOCK 0x4000 +/* To be set when GPU is not present on the bus, to help device teardown */ +#define NV_FLAG_IN_SURPRISE_REMOVAL 0x8000 + +typedef enum +{ + NV_PM_ACTION_HIBERNATE, + NV_PM_ACTION_STANDBY, + NV_PM_ACTION_RESUME +} nv_pm_action_t; + +typedef enum +{ + NV_PM_ACTION_DEPTH_DEFAULT, + NV_PM_ACTION_DEPTH_MODESET, + NV_PM_ACTION_DEPTH_UVM +} nv_pm_action_depth_t; + +typedef enum +{ + NV_DYNAMIC_PM_NEVER, + NV_DYNAMIC_PM_COARSE, + NV_DYNAMIC_PM_FINE +} nv_dynamic_power_mode_t; + +typedef enum +{ + NV_POWER_STATE_IN_HIBERNATE, + NV_POWER_STATE_IN_STANDBY, + NV_POWER_STATE_RUNNING +} nv_power_state_t; + +#define NV_PRIMARY_VGA(nv) ((nv)->primary_vga) + +#define NV_IS_CTL_DEVICE(nv) ((nv)->flags & NV_FLAG_CONTROL) +#define NV_IS_SOC_DISPLAY_DEVICE(nv) \ + ((nv)->flags & NV_FLAG_SOC_DISPLAY) + +#define NV_IS_SOC_IGPU_DEVICE(nv) \ + ((nv)->flags & NV_FLAG_SOC_IGPU) + +#define NV_IS_DEVICE_IN_SURPRISE_REMOVAL(nv) \ + (((nv)->flags & NV_FLAG_IN_SURPRISE_REMOVAL) != 0) + +#define NV_SOC_IS_ISO_IOMMU_PRESENT(nv) \ + ((nv)->iso_iommu_present) + +/* + * GPU add/remove events + */ +#define NV_SYSTEM_GPU_ADD_EVENT 0x9001 +#define NV_SYSTEM_GPU_REMOVE_EVENT 0x9002 + +/* + * NVIDIA ACPI sub-event IDs (event types) to be passed into + * to core NVIDIA driver for ACPI events. + */ +#define NV_SYSTEM_ACPI_EVENT_VALUE_DISPLAY_SWITCH_DEFAULT 0 +#define NV_SYSTEM_ACPI_EVENT_VALUE_DOCK_EVENT_UNDOCKED 0 +#define NV_SYSTEM_ACPI_EVENT_VALUE_DOCK_EVENT_DOCKED 1 + +#define NV_ACPI_NVIF_HANDLE_PRESENT 0x01 +#define NV_ACPI_DSM_HANDLE_PRESENT 0x02 +#define NV_ACPI_WMMX_HANDLE_PRESENT 0x04 + +#define NV_EVAL_ACPI_METHOD_NVIF 0x01 +#define NV_EVAL_ACPI_METHOD_WMMX 0x02 + +typedef enum { + NV_I2C_CMD_READ = 1, + NV_I2C_CMD_WRITE, + NV_I2C_CMD_SMBUS_READ, + NV_I2C_CMD_SMBUS_WRITE, + NV_I2C_CMD_SMBUS_QUICK_WRITE, + NV_I2C_CMD_SMBUS_QUICK_READ, + NV_I2C_CMD_SMBUS_BLOCK_READ, + NV_I2C_CMD_SMBUS_BLOCK_WRITE, + NV_I2C_CMD_BLOCK_READ, + NV_I2C_CMD_BLOCK_WRITE +} nv_i2c_cmd_t; + +// Flags needed by OSAllocPagesNode +#define NV_ALLOC_PAGES_NODE_NONE 0x0 +#define NV_ALLOC_PAGES_NODE_SKIP_RECLAIM 0x1 + +/* +** where we hide our nv_state_t * ... +*/ +#define NV_SET_NV_STATE(pgpu,p) ((pgpu)->pOsGpuInfo = (p)) +#define NV_GET_NV_STATE(pGpu) \ + (nv_state_t *)((pGpu) ? (pGpu)->pOsGpuInfo : NULL) + +static inline NvBool IS_REG_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) +{ + return ((offset >= nv->regs->cpu_address) && + ((offset + (length - 1)) >= offset) && + ((offset + (length - 1)) <= (nv->regs->cpu_address + (nv->regs->size - 1)))); +} + +static inline NvBool IS_FB_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) +{ + return ((nv->fb) && (offset >= nv->fb->cpu_address) && + ((offset + (length - 1)) >= offset) && + ((offset + (length - 1)) <= (nv->fb->cpu_address + (nv->fb->size - 1)))); +} + +static inline NvBool IS_UD_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) +{ + return ((nv->ud.cpu_address != 0) && (nv->ud.size != 0) && + (offset >= nv->ud.cpu_address) && + ((offset + (length - 1)) >= offset) && + ((offset + (length - 1)) <= (nv->ud.cpu_address + (nv->ud.size - 1)))); +} + +static inline NvBool IS_IMEM_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) +{ + return ((nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address != 0) && + (nv->bars[NV_GPU_BAR_INDEX_IMEM].size != 0) && + (offset >= nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address) && + ((offset + (length - 1)) >= offset) && + ((offset + (length - 1)) <= (nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + + (nv->bars[NV_GPU_BAR_INDEX_IMEM].size - 1)))); +} + +#define NV_RM_MAX_MSIX_LINES 8 + +#define NV_MAX_ISR_DELAY_US 20000 +#define NV_MAX_ISR_DELAY_MS (NV_MAX_ISR_DELAY_US / 1000) + +#define NV_TIMERCMP(a, b, CMP) \ + (((a)->tv_sec == (b)->tv_sec) ? \ + ((a)->tv_usec CMP (b)->tv_usec) : ((a)->tv_sec CMP (b)->tv_sec)) + +#define NV_TIMERADD(a, b, result) \ + { \ + (result)->tv_sec = (a)->tv_sec + (b)->tv_sec; \ + (result)->tv_usec = (a)->tv_usec + (b)->tv_usec; \ + if ((result)->tv_usec >= 1000000) \ + { \ + ++(result)->tv_sec; \ + (result)->tv_usec -= 1000000; \ + } \ + } + +#define NV_TIMERSUB(a, b, result) \ + { \ + (result)->tv_sec = (a)->tv_sec - (b)->tv_sec; \ + (result)->tv_usec = (a)->tv_usec - (b)->tv_usec; \ + if ((result)->tv_usec < 0) \ + { \ + --(result)->tv_sec; \ + (result)->tv_usec += 1000000; \ + } \ + } + +#define NV_TIMEVAL_TO_US(tv) ((NvU64)(tv).tv_sec * 1000000 + (tv).tv_usec) + +#ifndef NV_ALIGN_UP +#define NV_ALIGN_UP(v,g) (((v) + ((g) - 1)) & ~((g) - 1)) +#endif +#ifndef NV_ALIGN_DOWN +#define NV_ALIGN_DOWN(v,g) ((v) & ~((g) - 1)) +#endif + +/* + * driver internal interfaces + */ + +/* + * --------------------------------------------------------------------------- + * + * Function prototypes for UNIX specific OS interface. + * + * --------------------------------------------------------------------------- + */ + +NvU32 NV_API_CALL nv_get_dev_minor (nv_state_t *); +void* NV_API_CALL nv_alloc_kernel_mapping (nv_state_t *, void *, NvU64, NvU32, NvU64, void **); +NV_STATUS NV_API_CALL nv_free_kernel_mapping (nv_state_t *, void *, void *, void *); +NV_STATUS NV_API_CALL nv_alloc_user_mapping (nv_state_t *, void *, NvU64, NvU32, NvU64, NvU32, NvU64 *, void **); +NV_STATUS NV_API_CALL nv_free_user_mapping (nv_state_t *, void *, NvU64, void *); +NV_STATUS NV_API_CALL nv_add_mapping_context_to_file (nv_state_t *, nv_usermap_access_params_t*, NvU32, void *, NvU64, NvU32); + +NvU64 NV_API_CALL nv_get_kern_phys_address (NvU64); +NvU64 NV_API_CALL nv_get_user_phys_address (NvU64); +nv_state_t* NV_API_CALL nv_get_adapter_state (NvU32, NvU8, NvU8); +nv_state_t* NV_API_CALL nv_get_ctl_state (void); + +void NV_API_CALL nv_set_dma_address_size (nv_state_t *, NvU32 ); + +NV_STATUS NV_API_CALL nv_alias_pages (nv_state_t *, NvU32, NvU32, NvU32, NvU64, NvU64 *, void **); +NV_STATUS NV_API_CALL nv_alloc_pages (nv_state_t *, NvU32, NvBool, NvU32, NvBool, NvBool, NvU64 *, void **); +NV_STATUS NV_API_CALL nv_free_pages (nv_state_t *, NvU32, NvBool, NvU32, void *); + +NV_STATUS NV_API_CALL nv_register_user_pages (nv_state_t *, NvU64, NvU64 *, void *, void **); +void NV_API_CALL nv_unregister_user_pages (nv_state_t *, NvU64, void **, void **); + +NV_STATUS NV_API_CALL nv_register_peer_io_mem (nv_state_t *, NvU64 *, NvU64, void **); +void NV_API_CALL nv_unregister_peer_io_mem(nv_state_t *, void *); + +struct sg_table; + +NV_STATUS NV_API_CALL nv_register_sgt (nv_state_t *, NvU64 *, NvU64, NvU32, void **, struct sg_table *, void *); +void NV_API_CALL nv_unregister_sgt (nv_state_t *, struct sg_table **, void **, void *); +NV_STATUS NV_API_CALL nv_register_phys_pages (nv_state_t *, NvU64 *, NvU64, NvU32, void **); +void NV_API_CALL nv_unregister_phys_pages (nv_state_t *, void *); + +NV_STATUS NV_API_CALL nv_dma_map_sgt (nv_dma_device_t *, NvU64, NvU64 *, NvU32, void **); +NV_STATUS NV_API_CALL nv_dma_map_pages (nv_dma_device_t *, NvU64, NvU64 *, NvBool, NvU32, void **); +NV_STATUS NV_API_CALL nv_dma_unmap_pages (nv_dma_device_t *, NvU64, NvU64 *, void **); + +NV_STATUS NV_API_CALL nv_dma_map_alloc (nv_dma_device_t *, NvU64, NvU64 *, NvBool, void **); +NV_STATUS NV_API_CALL nv_dma_unmap_alloc (nv_dma_device_t *, NvU64, NvU64 *, void **); + +NV_STATUS NV_API_CALL nv_dma_map_peer (nv_dma_device_t *, nv_dma_device_t *, NvU8, NvU64, NvU64 *); +void NV_API_CALL nv_dma_unmap_peer (nv_dma_device_t *, NvU64, NvU64); + +NV_STATUS NV_API_CALL nv_dma_map_mmio (nv_dma_device_t *, NvU64, NvU64 *); +void NV_API_CALL nv_dma_unmap_mmio (nv_dma_device_t *, NvU64, NvU64); + +void NV_API_CALL nv_dma_cache_invalidate (nv_dma_device_t *, void *); +void NV_API_CALL nv_dma_enable_nvlink (nv_dma_device_t *); + +NvS32 NV_API_CALL nv_start_rc_timer (nv_state_t *); +NvS32 NV_API_CALL nv_stop_rc_timer (nv_state_t *); + +void NV_API_CALL nv_post_event (nv_event_t *, NvHandle, NvU32, NvU32, NvU16, NvBool); +NvS32 NV_API_CALL nv_get_event (nv_file_private_t *, nv_event_t *, NvU32 *); + +void* NV_API_CALL nv_i2c_add_adapter (nv_state_t *, NvU32); +void NV_API_CALL nv_i2c_del_adapter (nv_state_t *, void *); + +void NV_API_CALL nv_acpi_methods_init (NvU32 *); +void NV_API_CALL nv_acpi_methods_uninit (void); + +NV_STATUS NV_API_CALL nv_acpi_method (NvU32, NvU32, NvU32, void *, NvU16, NvU32 *, void *, NvU16 *); +NV_STATUS NV_API_CALL nv_acpi_dsm_method (nv_state_t *, NvU8 *, NvU32, NvBool, NvU32, void *, NvU16, NvU32 *, void *, NvU16 *); +NV_STATUS NV_API_CALL nv_acpi_ddc_method (nv_state_t *, void *, NvU32 *, NvBool); +NV_STATUS NV_API_CALL nv_acpi_dod_method (nv_state_t *, NvU32 *, NvU32 *); +NV_STATUS NV_API_CALL nv_acpi_rom_method (nv_state_t *, NvU32 *, NvU32 *); +NV_STATUS NV_API_CALL nv_acpi_get_powersource (NvU32 *); +NvBool NV_API_CALL nv_acpi_is_battery_present(void); + +NV_STATUS NV_API_CALL nv_acpi_mux_method (nv_state_t *, NvU32 *, NvU32, const char *); + +NV_STATUS NV_API_CALL nv_log_error (nv_state_t *, NvU32, const char *, va_list); + +NvU64 NV_API_CALL nv_get_dma_start_address (nv_state_t *); +NV_STATUS NV_API_CALL nv_set_primary_vga_status(nv_state_t *); +NV_STATUS NV_API_CALL nv_pci_trigger_recovery (nv_state_t *); +NvBool NV_API_CALL nv_requires_dma_remap (nv_state_t *); + +NvBool NV_API_CALL nv_is_rm_firmware_active(nv_state_t *); +const void*NV_API_CALL nv_get_firmware(nv_state_t *, nv_firmware_type_t, nv_firmware_chip_family_t, const void **, NvU32 *); +void NV_API_CALL nv_put_firmware(const void *); + +nv_file_private_t* NV_API_CALL nv_get_file_private(NvS32, NvBool, void **); +void NV_API_CALL nv_put_file_private(void *); + +NV_STATUS NV_API_CALL nv_get_device_memory_config(nv_state_t *, NvU64 *, NvU64 *, NvU32 *, NvS32 *); + +NV_STATUS NV_API_CALL nv_get_ibmnpu_genreg_info(nv_state_t *, NvU64 *, NvU64 *, void**); +NV_STATUS NV_API_CALL nv_get_ibmnpu_relaxed_ordering_mode(nv_state_t *nv, NvBool *mode); + +void NV_API_CALL nv_wait_for_ibmnpu_rsync(nv_state_t *nv); + +void NV_API_CALL nv_ibmnpu_cache_flush_range(nv_state_t *nv, NvU64, NvU64); + +void NV_API_CALL nv_p2p_free_platform_data(void *data); + +#if defined(NVCPU_PPC64LE) +NV_STATUS NV_API_CALL nv_get_nvlink_line_rate (nv_state_t *, NvU32 *); +#endif + +NV_STATUS NV_API_CALL nv_revoke_gpu_mappings (nv_state_t *); +void NV_API_CALL nv_acquire_mmap_lock (nv_state_t *); +void NV_API_CALL nv_release_mmap_lock (nv_state_t *); +NvBool NV_API_CALL nv_get_all_mappings_revoked_locked (nv_state_t *); +void NV_API_CALL nv_set_safe_to_mmap_locked (nv_state_t *, NvBool); + +NV_STATUS NV_API_CALL nv_indicate_idle (nv_state_t *); +NV_STATUS NV_API_CALL nv_indicate_not_idle (nv_state_t *); +void NV_API_CALL nv_idle_holdoff (nv_state_t *); + +NvBool NV_API_CALL nv_dynamic_power_available (nv_state_t *); +void NV_API_CALL nv_audio_dynamic_power (nv_state_t *); + +void NV_API_CALL nv_control_soc_irqs (nv_state_t *, NvBool bEnable); +NV_STATUS NV_API_CALL nv_get_current_irq_priv_data(nv_state_t *, NvU32 *); + +NV_STATUS NV_API_CALL nv_acquire_fabric_mgmt_cap (int, int*); +int NV_API_CALL nv_cap_drv_init(void); +void NV_API_CALL nv_cap_drv_exit(void); +NvBool NV_API_CALL nv_is_gpu_accessible(nv_state_t *); +NvBool NV_API_CALL nv_match_gpu_os_info(nv_state_t *, void *); + +NvU32 NV_API_CALL nv_get_os_type(void); + +void NV_API_CALL nv_get_updated_emu_seg(NvU32 *start, NvU32 *end); +struct dma_buf; +typedef struct nv_dma_buf nv_dma_buf_t; +struct drm_gem_object; + +NV_STATUS NV_API_CALL nv_dma_import_sgt (nv_dma_device_t *, struct sg_table *, struct drm_gem_object *); +void NV_API_CALL nv_dma_release_sgt(struct sg_table *, struct drm_gem_object *); +NV_STATUS NV_API_CALL nv_dma_import_dma_buf (nv_dma_device_t *, struct dma_buf *, NvU32 *, void **, struct sg_table **, nv_dma_buf_t **); +NV_STATUS NV_API_CALL nv_dma_import_from_fd (nv_dma_device_t *, NvS32, NvU32 *, void **, struct sg_table **, nv_dma_buf_t **); +void NV_API_CALL nv_dma_release_dma_buf (void *, nv_dma_buf_t *); + +void NV_API_CALL nv_schedule_uvm_isr (nv_state_t *); + +NvBool NV_API_CALL nv_platform_supports_s0ix (void); +NvBool NV_API_CALL nv_s2idle_pm_configured (void); + +NvBool NV_API_CALL nv_is_chassis_notebook (void); +void NV_API_CALL nv_allow_runtime_suspend (nv_state_t *nv); +void NV_API_CALL nv_disallow_runtime_suspend (nv_state_t *nv); + +typedef void (*nvTegraDceClientIpcCallback)(NvU32, NvU32, NvU32, void *, void *); + +NV_STATUS NV_API_CALL nv_get_num_phys_pages (void *, NvU32 *); +NV_STATUS NV_API_CALL nv_get_phys_pages (void *, void *, NvU32 *); + +/* + * --------------------------------------------------------------------------- + * + * Function prototypes for Resource Manager interface. + * + * --------------------------------------------------------------------------- + */ + +NvBool NV_API_CALL rm_init_rm (nvidia_stack_t *); +void NV_API_CALL rm_shutdown_rm (nvidia_stack_t *); +NvBool NV_API_CALL rm_init_private_state (nvidia_stack_t *, nv_state_t *); +void NV_API_CALL rm_free_private_state (nvidia_stack_t *, nv_state_t *); +NvBool NV_API_CALL rm_init_adapter (nvidia_stack_t *, nv_state_t *); +void NV_API_CALL rm_disable_adapter (nvidia_stack_t *, nv_state_t *); +void NV_API_CALL rm_shutdown_adapter (nvidia_stack_t *, nv_state_t *); +NV_STATUS NV_API_CALL rm_exclude_adapter (nvidia_stack_t *, nv_state_t *); +NV_STATUS NV_API_CALL rm_acquire_api_lock (nvidia_stack_t *); +NV_STATUS NV_API_CALL rm_release_api_lock (nvidia_stack_t *); +NV_STATUS NV_API_CALL rm_acquire_gpu_lock (nvidia_stack_t *, nv_state_t *); +NV_STATUS NV_API_CALL rm_release_gpu_lock (nvidia_stack_t *, nv_state_t *); +NV_STATUS NV_API_CALL rm_acquire_all_gpus_lock (nvidia_stack_t *); +NV_STATUS NV_API_CALL rm_release_all_gpus_lock (nvidia_stack_t *); +NV_STATUS NV_API_CALL rm_ioctl (nvidia_stack_t *, nv_state_t *, nv_file_private_t *, NvU32, void *, NvU32); +NvBool NV_API_CALL rm_isr (nvidia_stack_t *, nv_state_t *, NvU32 *); +void NV_API_CALL rm_isr_bh (nvidia_stack_t *, nv_state_t *); +void NV_API_CALL rm_isr_bh_unlocked (nvidia_stack_t *, nv_state_t *); +NV_STATUS NV_API_CALL rm_power_management (nvidia_stack_t *, nv_state_t *, nv_pm_action_t); +NV_STATUS NV_API_CALL rm_stop_user_channels (nvidia_stack_t *, nv_state_t *); +NV_STATUS NV_API_CALL rm_restart_user_channels (nvidia_stack_t *, nv_state_t *); +NV_STATUS NV_API_CALL rm_save_low_res_mode (nvidia_stack_t *, nv_state_t *); +void NV_API_CALL rm_get_vbios_version (nvidia_stack_t *, nv_state_t *, char *); +char* NV_API_CALL rm_get_gpu_uuid (nvidia_stack_t *, nv_state_t *); +const NvU8* NV_API_CALL rm_get_gpu_uuid_raw (nvidia_stack_t *, nv_state_t *); +void NV_API_CALL rm_set_rm_firmware_requested(nvidia_stack_t *, nv_state_t *); +void NV_API_CALL rm_get_firmware_version (nvidia_stack_t *, nv_state_t *, char *, NvLength); +void NV_API_CALL rm_cleanup_file_private (nvidia_stack_t *, nv_state_t *, nv_file_private_t *); +void NV_API_CALL rm_unbind_lock (nvidia_stack_t *, nv_state_t *); +NV_STATUS NV_API_CALL rm_read_registry_dword (nvidia_stack_t *, nv_state_t *, const char *, NvU32 *); +NV_STATUS NV_API_CALL rm_write_registry_dword (nvidia_stack_t *, nv_state_t *, const char *, NvU32); +NV_STATUS NV_API_CALL rm_write_registry_binary (nvidia_stack_t *, nv_state_t *, const char *, NvU8 *, NvU32); +NV_STATUS NV_API_CALL rm_write_registry_string (nvidia_stack_t *, nv_state_t *, const char *, const char *, NvU32); +void NV_API_CALL rm_parse_option_string (nvidia_stack_t *, const char *); +char* NV_API_CALL rm_remove_spaces (const char *); +char* NV_API_CALL rm_string_token (char **, const char); + +NV_STATUS NV_API_CALL rm_run_rc_callback (nvidia_stack_t *, nv_state_t *); +void NV_API_CALL rm_execute_work_item (nvidia_stack_t *, void *); +const char* NV_API_CALL rm_get_device_name (NvU16, NvU16, NvU16); + +NV_STATUS NV_API_CALL rm_is_supported_device (nvidia_stack_t *, nv_state_t *); +NvBool NV_API_CALL rm_is_supported_pci_device(NvU8 pci_class, + NvU8 pci_subclass, + NvU16 vendor, + NvU16 device, + NvU16 subsystem_vendor, + NvU16 subsystem_device, + NvBool print_legacy_warning); + +void NV_API_CALL rm_i2c_remove_adapters (nvidia_stack_t *, nv_state_t *); +NvBool NV_API_CALL rm_i2c_is_smbus_capable (nvidia_stack_t *, nv_state_t *, void *); +NV_STATUS NV_API_CALL rm_i2c_transfer (nvidia_stack_t *, nv_state_t *, void *, nv_i2c_cmd_t, NvU8, NvU8, NvU32, NvU8 *); + +NV_STATUS NV_API_CALL rm_perform_version_check (nvidia_stack_t *, void *, NvU32); + +void NV_API_CALL rm_power_source_change_event (nvidia_stack_t *, NvU32); + +void NV_API_CALL rm_disable_gpu_state_persistence (nvidia_stack_t *sp, nv_state_t *); +NV_STATUS NV_API_CALL rm_p2p_init_mapping (nvidia_stack_t *, NvU64, NvU64 *, NvU64 *, NvU64 *, NvU64 *, NvU64, NvU64, NvU64, NvU64, void (*)(void *), void *); +NV_STATUS NV_API_CALL rm_p2p_destroy_mapping (nvidia_stack_t *, NvU64); +NV_STATUS NV_API_CALL rm_p2p_get_pages (nvidia_stack_t *, NvU64, NvU32, NvU64, NvU64, NvU64 *, NvU32 *, NvU32 *, NvU32 *, NvU8 **, void *); +NV_STATUS NV_API_CALL rm_p2p_get_gpu_info (nvidia_stack_t *, NvU64, NvU64, NvU8 **, void **); +NV_STATUS NV_API_CALL rm_p2p_get_pages_persistent (nvidia_stack_t *, NvU64, NvU64, void **, NvU64 *, NvU32 *, void *, void *); +NV_STATUS NV_API_CALL rm_p2p_register_callback (nvidia_stack_t *, NvU64, NvU64, NvU64, void *, void (*)(void *), void *); +NV_STATUS NV_API_CALL rm_p2p_put_pages (nvidia_stack_t *, NvU64, NvU32, NvU64, void *); +NV_STATUS NV_API_CALL rm_p2p_put_pages_persistent(nvidia_stack_t *, void *, void *); +NV_STATUS NV_API_CALL rm_p2p_dma_map_pages (nvidia_stack_t *, nv_dma_device_t *, NvU8 *, NvU32, NvU32, NvU64 *, void **); +NV_STATUS NV_API_CALL rm_dma_buf_dup_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, NvHandle, void *, NvHandle, NvU64, NvU64, NvHandle *); +void NV_API_CALL rm_dma_buf_undup_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle); +NV_STATUS NV_API_CALL rm_dma_buf_map_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, NvU64, NvU64 *); +NV_STATUS NV_API_CALL rm_dma_buf_unmap_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, NvU64); +NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle *, NvHandle *, NvHandle *, void **); +void NV_API_CALL rm_dma_buf_put_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, void *); +NV_STATUS NV_API_CALL rm_log_gpu_crash (nv_stack_t *, nv_state_t *); + +void NV_API_CALL rm_kernel_rmapi_op(nvidia_stack_t *sp, void *ops_cmd); +NvBool NV_API_CALL rm_get_device_remove_flag(nvidia_stack_t *sp, NvU32 gpu_id); +NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults(nvidia_stack_t *, nv_state_t *, NvU32 *); +NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults_unlocked(nvidia_stack_t *, nv_state_t *, NvU32 *); +NV_STATUS NV_API_CALL rm_gpu_handle_mmu_faults(nvidia_stack_t *, nv_state_t *, NvU32 *); +NvBool NV_API_CALL rm_gpu_need_4k_page_isolation(nv_state_t *); +NvBool NV_API_CALL rm_is_chipset_io_coherent(nv_stack_t *); +NvBool NV_API_CALL rm_init_event_locks(nvidia_stack_t *, nv_state_t *); +void NV_API_CALL rm_destroy_event_locks(nvidia_stack_t *, nv_state_t *); +NV_STATUS NV_API_CALL rm_get_gpu_numa_info(nvidia_stack_t *, nv_state_t *, NvS32 *, NvU64 *, NvU64 *, NvU64 *, NvU32 *); +NV_STATUS NV_API_CALL rm_gpu_numa_online(nvidia_stack_t *, nv_state_t *); +NV_STATUS NV_API_CALL rm_gpu_numa_offline(nvidia_stack_t *, nv_state_t *); +NvBool NV_API_CALL rm_is_device_sequestered(nvidia_stack_t *, nv_state_t *); +void NV_API_CALL rm_check_for_gpu_surprise_removal(nvidia_stack_t *, nv_state_t *); +NV_STATUS NV_API_CALL rm_set_external_kernel_client_count(nvidia_stack_t *, nv_state_t *, NvBool); +NV_STATUS NV_API_CALL rm_schedule_gpu_wakeup(nvidia_stack_t *, nv_state_t *); +NvBool NV_API_CALL rm_is_iommu_needed_for_sriov(nvidia_stack_t *, nv_state_t *); +NvBool NV_API_CALL rm_disable_iomap_wc(void); + +void NV_API_CALL rm_init_dynamic_power_management(nvidia_stack_t *, nv_state_t *, NvBool); +void NV_API_CALL rm_cleanup_dynamic_power_management(nvidia_stack_t *, nv_state_t *); +void NV_API_CALL rm_enable_dynamic_power_management(nvidia_stack_t *, nv_state_t *); +NV_STATUS NV_API_CALL rm_ref_dynamic_power(nvidia_stack_t *, nv_state_t *, nv_dynamic_power_mode_t); +void NV_API_CALL rm_unref_dynamic_power(nvidia_stack_t *, nv_state_t *, nv_dynamic_power_mode_t); +NV_STATUS NV_API_CALL rm_transition_dynamic_power(nvidia_stack_t *, nv_state_t *, NvBool); +const char* NV_API_CALL rm_get_vidmem_power_status(nvidia_stack_t *, nv_state_t *); +const char* NV_API_CALL rm_get_dynamic_power_management_status(nvidia_stack_t *, nv_state_t *); +const char* NV_API_CALL rm_get_gpu_gcx_support(nvidia_stack_t *, nv_state_t *, NvBool); + +void NV_API_CALL rm_acpi_notify(nvidia_stack_t *, nv_state_t *, NvU32); + +NvBool NV_API_CALL rm_is_altstack_in_use(void); + +/* vGPU VFIO specific functions */ +NV_STATUS NV_API_CALL nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU16 *, NvU32, NvBool *); +NV_STATUS NV_API_CALL nv_vgpu_delete(nvidia_stack_t *, const NvU8 *, NvU16); +NV_STATUS NV_API_CALL nv_vgpu_get_type_ids(nvidia_stack_t *, nv_state_t *, NvU32 *, NvU32 *, NvBool, NvU8, NvBool); +NV_STATUS NV_API_CALL nv_vgpu_get_type_info(nvidia_stack_t *, nv_state_t *, NvU32, char *, int, NvU8); +NV_STATUS NV_API_CALL nv_vgpu_get_bar_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *, NvU32, void *); +NV_STATUS NV_API_CALL nv_vgpu_start(nvidia_stack_t *, const NvU8 *, void *, NvS32 *, NvU8 *, NvU32); +NV_STATUS NV_API_CALL nv_vgpu_get_sparse_mmap(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 **, NvU64 **, NvU32 *); +NV_STATUS NV_API_CALL nv_vgpu_process_vf_info(nvidia_stack_t *, nv_state_t *, NvU8, NvU32, NvU8, NvU8, NvU8, NvBool, void *); +NV_STATUS NV_API_CALL nv_vgpu_update_request(nvidia_stack_t *, const NvU8 *, NvU32, NvU64 *, NvU64 *, const char *); +NV_STATUS NV_API_CALL nv_gpu_bind_event(nvidia_stack_t *); + +NV_STATUS NV_API_CALL nv_get_usermap_access_params(nv_state_t*, nv_usermap_access_params_t*); +nv_soc_irq_type_t NV_API_CALL nv_get_current_irq_type(nv_state_t*); +void NV_API_CALL nv_flush_coherent_cpu_cache_range(nv_state_t *nv, NvU64 cpu_virtual, NvU64 size); + +/* Callbacks should occur roughly every 10ms. */ +#define NV_SNAPSHOT_TIMER_HZ 100 +void NV_API_CALL nv_start_snapshot_timer(void (*snapshot_callback)(void *context)); +void NV_API_CALL nv_flush_snapshot_timer(void); +void NV_API_CALL nv_stop_snapshot_timer(void); + +static inline const NvU8 *nv_get_cached_uuid(nv_state_t *nv) +{ + return nv->nv_uuid_cache.valid ? nv->nv_uuid_cache.uuid : NULL; +} + +/* nano second resolution timer callback structure */ +typedef struct nv_nano_timer nv_nano_timer_t; + +/* nano timer functions */ +void NV_API_CALL nv_create_nano_timer(nv_state_t *, void *pTmrEvent, nv_nano_timer_t **); +void NV_API_CALL nv_start_nano_timer(nv_state_t *nv, nv_nano_timer_t *, NvU64 timens); +NV_STATUS NV_API_CALL rm_run_nano_timer_callback(nvidia_stack_t *, nv_state_t *, void *pTmrEvent); +void NV_API_CALL nv_cancel_nano_timer(nv_state_t *, nv_nano_timer_t *); +void NV_API_CALL nv_destroy_nano_timer(nv_state_t *nv, nv_nano_timer_t *); + +#if defined(NVCPU_X86_64) + +static inline NvU64 nv_rdtsc(void) +{ + NvU64 val; + __asm__ __volatile__ ("rdtsc \t\n" + "shlq $0x20,%%rdx \t\n" + "orq %%rdx,%%rax \t\n" + : "=A" (val)); + return val; +} + +#endif + +#endif /* NVRM */ + +static inline int nv_count_bits(NvU64 word) +{ + NvU64 bits; + + bits = (word & 0x5555555555555555ULL) + ((word >> 1) & 0x5555555555555555ULL); + bits = (bits & 0x3333333333333333ULL) + ((bits >> 2) & 0x3333333333333333ULL); + bits = (bits & 0x0f0f0f0f0f0f0f0fULL) + ((bits >> 4) & 0x0f0f0f0f0f0f0f0fULL); + bits = (bits & 0x00ff00ff00ff00ffULL) + ((bits >> 8) & 0x00ff00ff00ff00ffULL); + bits = (bits & 0x0000ffff0000ffffULL) + ((bits >> 16) & 0x0000ffff0000ffffULL); + bits = (bits & 0x00000000ffffffffULL) + ((bits >> 32) & 0x00000000ffffffffULL); + + return (int)(bits); +} + +#endif diff --git a/userspace/sdks/nv525/nvalloc/unix/include/nv_escape.h b/userspace/sdks/nv525/nvalloc/unix/include/nv_escape.h new file mode 100644 index 0000000..629af5a --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/include/nv_escape.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NV_ESCAPE_H_INCLUDED +#define NV_ESCAPE_H_INCLUDED + +#define NV_ESC_RM_ALLOC_MEMORY 0x27 +#define NV_ESC_RM_ALLOC_OBJECT 0x28 +#define NV_ESC_RM_FREE 0x29 +#define NV_ESC_RM_CONTROL 0x2A +#define NV_ESC_RM_ALLOC 0x2B +#define NV_ESC_RM_CONFIG_GET 0x32 +#define NV_ESC_RM_CONFIG_SET 0x33 +#define NV_ESC_RM_DUP_OBJECT 0x34 +#define NV_ESC_RM_SHARE 0x35 +#define NV_ESC_RM_CONFIG_GET_EX 0x37 +#define NV_ESC_RM_CONFIG_SET_EX 0x38 +#define NV_ESC_RM_I2C_ACCESS 0x39 +#define NV_ESC_RM_IDLE_CHANNELS 0x41 +#define NV_ESC_RM_VID_HEAP_CONTROL 0x4A +#define NV_ESC_RM_ACCESS_REGISTRY 0x4D +#define NV_ESC_RM_MAP_MEMORY 0x4E +#define NV_ESC_RM_UNMAP_MEMORY 0x4F +#define NV_ESC_RM_GET_EVENT_DATA 0x52 +#define NV_ESC_RM_ALLOC_CONTEXT_DMA2 0x54 +#define NV_ESC_RM_ADD_VBLANK_CALLBACK 0x56 +#define NV_ESC_RM_MAP_MEMORY_DMA 0x57 +#define NV_ESC_RM_UNMAP_MEMORY_DMA 0x58 +#define NV_ESC_RM_BIND_CONTEXT_DMA 0x59 +#define NV_ESC_RM_EXPORT_OBJECT_TO_FD 0x5C +#define NV_ESC_RM_IMPORT_OBJECT_FROM_FD 0x5D +#define NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO 0x5E + +#endif // NV_ESCAPE_H_INCLUDED diff --git a/userspace/sdks/nv525/nvalloc/unix/include/os-interface.h b/userspace/sdks/nv525/nvalloc/unix/include/os-interface.h new file mode 100644 index 0000000..9ebeeed --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/include/os-interface.h @@ -0,0 +1,250 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/* + * Os interface definitions needed by os-interface.c + */ + +#ifndef OS_INTERFACE_H +#define OS_INTERFACE_H + +/******************* Operating System Interface Routines *******************\ +* * +* Operating system wrapper functions used to abstract the OS. * +* * +\***************************************************************************/ + +#include +#include +#include "nv_stdarg.h" +#include +#include +#include + + + +typedef struct +{ + NvU32 os_major_version; + NvU32 os_minor_version; + NvU32 os_build_number; + const char * os_build_version_str; + const char * os_build_date_plus_str; +}os_version_info; + +/* Each OS defines its own version of this opaque type */ +struct os_work_queue; + +/* Each OS defines its own version of this opaque type */ +typedef struct os_wait_queue os_wait_queue; + +/* + * --------------------------------------------------------------------------- + * + * Function prototypes for OS interface. + * + * --------------------------------------------------------------------------- + */ + +NvU64 NV_API_CALL os_get_num_phys_pages (void); +NV_STATUS NV_API_CALL os_alloc_mem (void **, NvU64); +void NV_API_CALL os_free_mem (void *); +NV_STATUS NV_API_CALL os_get_current_time (NvU32 *, NvU32 *); +NvU64 NV_API_CALL os_get_current_tick (void); +NvU64 NV_API_CALL os_get_current_tick_hr (void); +NvU64 NV_API_CALL os_get_tick_resolution (void); +NV_STATUS NV_API_CALL os_delay (NvU32); +NV_STATUS NV_API_CALL os_delay_us (NvU32); +NvU64 NV_API_CALL os_get_cpu_frequency (void); +NvU32 NV_API_CALL os_get_current_process (void); +void NV_API_CALL os_get_current_process_name (char *, NvU32); +NV_STATUS NV_API_CALL os_get_current_thread (NvU64 *); +char* NV_API_CALL os_string_copy (char *, const char *); +NvU32 NV_API_CALL os_string_length (const char *); +NvU32 NV_API_CALL os_strtoul (const char *, char **, NvU32); +NvS32 NV_API_CALL os_string_compare (const char *, const char *); +NvS32 NV_API_CALL os_snprintf (char *, NvU32, const char *, ...); +NvS32 NV_API_CALL os_vsnprintf (char *, NvU32, const char *, va_list); +void NV_API_CALL os_log_error (const char *, va_list); +void* NV_API_CALL os_mem_copy (void *, const void *, NvU32); +NV_STATUS NV_API_CALL os_memcpy_from_user (void *, const void *, NvU32); +NV_STATUS NV_API_CALL os_memcpy_to_user (void *, const void *, NvU32); +void* NV_API_CALL os_mem_set (void *, NvU8, NvU32); +NvS32 NV_API_CALL os_mem_cmp (const NvU8 *, const NvU8 *, NvU32); +void* NV_API_CALL os_pci_init_handle (NvU32, NvU8, NvU8, NvU8, NvU16 *, NvU16 *); +NV_STATUS NV_API_CALL os_pci_read_byte (void *, NvU32, NvU8 *); +NV_STATUS NV_API_CALL os_pci_read_word (void *, NvU32, NvU16 *); +NV_STATUS NV_API_CALL os_pci_read_dword (void *, NvU32, NvU32 *); +NV_STATUS NV_API_CALL os_pci_write_byte (void *, NvU32, NvU8); +NV_STATUS NV_API_CALL os_pci_write_word (void *, NvU32, NvU16); +NV_STATUS NV_API_CALL os_pci_write_dword (void *, NvU32, NvU32); +NvBool NV_API_CALL os_pci_remove_supported (void); +void NV_API_CALL os_pci_remove (void *); +void* NV_API_CALL os_map_kernel_space (NvU64, NvU64, NvU32); +void NV_API_CALL os_unmap_kernel_space (void *, NvU64); +void* NV_API_CALL os_map_user_space (NvU64, NvU64, NvU32, NvU32, void **); +void NV_API_CALL os_unmap_user_space (void *, NvU64, void *); +NV_STATUS NV_API_CALL os_flush_cpu_cache (void); +NV_STATUS NV_API_CALL os_flush_cpu_cache_all (void); +NV_STATUS NV_API_CALL os_flush_user_cache (void); +void NV_API_CALL os_flush_cpu_write_combine_buffer(void); +NvU8 NV_API_CALL os_io_read_byte (NvU32); +NvU16 NV_API_CALL os_io_read_word (NvU32); +NvU32 NV_API_CALL os_io_read_dword (NvU32); +void NV_API_CALL os_io_write_byte (NvU32, NvU8); +void NV_API_CALL os_io_write_word (NvU32, NvU16); +void NV_API_CALL os_io_write_dword (NvU32, NvU32); +NvBool NV_API_CALL os_is_administrator (void); +NvBool NV_API_CALL os_allow_priority_override (void); +void NV_API_CALL os_dbg_init (void); +void NV_API_CALL os_dbg_breakpoint (void); +void NV_API_CALL os_dbg_set_level (NvU32); +NvU32 NV_API_CALL os_get_cpu_count (void); +NvU32 NV_API_CALL os_get_cpu_number (void); +void NV_API_CALL os_disable_console_access (void); +void NV_API_CALL os_enable_console_access (void); +NV_STATUS NV_API_CALL os_registry_init (void); +NvU64 NV_API_CALL os_get_max_user_va (void); +NV_STATUS NV_API_CALL os_schedule (void); +NV_STATUS NV_API_CALL os_alloc_spinlock (void **); +void NV_API_CALL os_free_spinlock (void *); +NvU64 NV_API_CALL os_acquire_spinlock (void *); +void NV_API_CALL os_release_spinlock (void *, NvU64); +NV_STATUS NV_API_CALL os_queue_work_item (struct os_work_queue *, void *); +NV_STATUS NV_API_CALL os_flush_work_queue (struct os_work_queue *); +NV_STATUS NV_API_CALL os_alloc_mutex (void **); +void NV_API_CALL os_free_mutex (void *); +NV_STATUS NV_API_CALL os_acquire_mutex (void *); +NV_STATUS NV_API_CALL os_cond_acquire_mutex (void *); +void NV_API_CALL os_release_mutex (void *); +void* NV_API_CALL os_alloc_semaphore (NvU32); +void NV_API_CALL os_free_semaphore (void *); +NV_STATUS NV_API_CALL os_acquire_semaphore (void *); +NV_STATUS NV_API_CALL os_cond_acquire_semaphore (void *); +NV_STATUS NV_API_CALL os_release_semaphore (void *); +void* NV_API_CALL os_alloc_rwlock (void); +void NV_API_CALL os_free_rwlock (void *); +NV_STATUS NV_API_CALL os_acquire_rwlock_read (void *); +NV_STATUS NV_API_CALL os_acquire_rwlock_write (void *); +NV_STATUS NV_API_CALL os_cond_acquire_rwlock_read (void *); +NV_STATUS NV_API_CALL os_cond_acquire_rwlock_write(void *); +void NV_API_CALL os_release_rwlock_read (void *); +void NV_API_CALL os_release_rwlock_write (void *); +NvBool NV_API_CALL os_semaphore_may_sleep (void); +NV_STATUS NV_API_CALL os_get_version_info (os_version_info*); +NvBool NV_API_CALL os_is_isr (void); +NvBool NV_API_CALL os_pat_supported (void); +void NV_API_CALL os_dump_stack (void); +NvBool NV_API_CALL os_is_efi_enabled (void); +NvBool NV_API_CALL os_is_xen_dom0 (void); +NvBool NV_API_CALL os_is_vgx_hyper (void); +NV_STATUS NV_API_CALL os_inject_vgx_msi (NvU16, NvU64, NvU32); +NvBool NV_API_CALL os_is_grid_supported (void); +NvU32 NV_API_CALL os_get_grid_csp_support (void); +void NV_API_CALL os_get_screen_info (NvU64 *, NvU16 *, NvU16 *, NvU16 *, NvU16 *, NvU64, NvU64); +void NV_API_CALL os_bug_check (NvU32, const char *); +NV_STATUS NV_API_CALL os_lock_user_pages (void *, NvU64, void **, NvU32); +NV_STATUS NV_API_CALL os_lookup_user_io_memory (void *, NvU64, NvU64 **, void**); +NV_STATUS NV_API_CALL os_unlock_user_pages (NvU64, void *); +NV_STATUS NV_API_CALL os_match_mmap_offset (void *, NvU64, NvU64 *); +NV_STATUS NV_API_CALL os_get_euid (NvU32 *); +NV_STATUS NV_API_CALL os_get_smbios_header (NvU64 *pSmbsAddr); +NV_STATUS NV_API_CALL os_get_acpi_rsdp_from_uefi (NvU32 *); +void NV_API_CALL os_add_record_for_crashLog (void *, NvU32); +void NV_API_CALL os_delete_record_for_crashLog (void *); +NV_STATUS NV_API_CALL os_call_vgpu_vfio (void *, NvU32); +NV_STATUS NV_API_CALL os_numa_memblock_size (NvU64 *); +NV_STATUS NV_API_CALL os_alloc_pages_node (NvS32, NvU32, NvU32, NvU64 *); +NV_STATUS NV_API_CALL os_get_page (NvU64 address); +NV_STATUS NV_API_CALL os_put_page (NvU64 address); +NvU32 NV_API_CALL os_get_page_refcount (NvU64 address); +NvU32 NV_API_CALL os_count_tail_pages (NvU64 address); +void NV_API_CALL os_free_pages_phys (NvU64, NvU32); +NV_STATUS NV_API_CALL os_call_nv_vmbus (NvU32, void *); +NV_STATUS NV_API_CALL os_open_temporary_file (void **); +void NV_API_CALL os_close_file (void *); +NV_STATUS NV_API_CALL os_write_file (void *, NvU8 *, NvU64, NvU64); +NV_STATUS NV_API_CALL os_read_file (void *, NvU8 *, NvU64, NvU64); +NV_STATUS NV_API_CALL os_open_readonly_file (const char *, void **); +NV_STATUS NV_API_CALL os_open_and_read_file (const char *, NvU8 *, NvU64); +NvBool NV_API_CALL os_is_nvswitch_present (void); +void NV_API_CALL os_get_random_bytes (NvU8 *, NvU16); +NV_STATUS NV_API_CALL os_alloc_wait_queue (os_wait_queue **); +void NV_API_CALL os_free_wait_queue (os_wait_queue *); +void NV_API_CALL os_wait_uninterruptible (os_wait_queue *); +void NV_API_CALL os_wait_interruptible (os_wait_queue *); +void NV_API_CALL os_wake_up (os_wait_queue *); +nv_cap_t* NV_API_CALL os_nv_cap_init (const char *); +nv_cap_t* NV_API_CALL os_nv_cap_create_dir_entry (nv_cap_t *, const char *, int); +nv_cap_t* NV_API_CALL os_nv_cap_create_file_entry (nv_cap_t *, const char *, int); +void NV_API_CALL os_nv_cap_destroy_entry (nv_cap_t *); +int NV_API_CALL os_nv_cap_validate_and_dup_fd(const nv_cap_t *, int); +void NV_API_CALL os_nv_cap_close_fd (int); + +enum os_pci_req_atomics_type { + OS_INTF_PCIE_REQ_ATOMICS_32BIT, + OS_INTF_PCIE_REQ_ATOMICS_64BIT, + OS_INTF_PCIE_REQ_ATOMICS_128BIT +}; +NV_STATUS NV_API_CALL os_enable_pci_req_atomics (void *, enum os_pci_req_atomics_type); + +extern NvU32 os_page_size; +extern NvU64 os_page_mask; +extern NvU8 os_page_shift; +extern NvU32 os_sev_status; +extern NvBool os_sev_enabled; +extern NvBool os_dma_buf_enabled; + +/* + * --------------------------------------------------------------------------- + * + * Debug macros. + * + * --------------------------------------------------------------------------- + */ + +#define NV_DBG_INFO 0x0 +#define NV_DBG_SETUP 0x1 +#define NV_DBG_USERERRORS 0x2 +#define NV_DBG_WARNINGS 0x3 +#define NV_DBG_ERRORS 0x4 + + +void NV_API_CALL out_string(const char *str); +int NV_API_CALL nv_printf(NvU32 debuglevel, const char *printf_format, ...); + +#define NV_DEV_PRINTF(debuglevel, nv, format, ... ) \ + nv_printf(debuglevel, "NVRM: GPU " NV_PCI_DEV_FMT ": " format, NV_PCI_DEV_FMT_ARGS(nv), ## __VA_ARGS__) + +#define NV_DEV_PRINTF_STATUS(debuglevel, nv, status, format, ... ) \ + nv_printf(debuglevel, "NVRM: GPU " NV_PCI_DEV_FMT ": " format " (0x%x)\n", NV_PCI_DEV_FMT_ARGS(nv), ## __VA_ARGS__, status) + +/* + * Fields for os_lock_user_pages flags parameter + */ +#define NV_LOCK_USER_PAGES_FLAGS_WRITE 0:0 +#define NV_LOCK_USER_PAGES_FLAGS_WRITE_NO 0x00000000 +#define NV_LOCK_USER_PAGES_FLAGS_WRITE_YES 0x00000001 + +#endif /* OS_INTERFACE_H */ diff --git a/userspace/sdks/nv525/nvalloc/unix/include/os_custom.h b/userspace/sdks/nv525/nvalloc/unix/include/os_custom.h new file mode 100644 index 0000000..37df06f --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/include/os_custom.h @@ -0,0 +1,61 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _OS_CUSTOM_H_ +#define _OS_CUSTOM_H_ + +/*! + * @file os_custom.h + * @brief OS module specific definitions for this OS + */ + +#include +#include + +// File modes, added for NVIDIA capabilities. +#define OS_RUSR 00400 // read permission, owner +#define OS_WUSR 00200 // write permission, owner +#define OS_XUSR 00100 // execute/search permission, owner +#define OS_RWXU (OS_RUSR | OS_WUSR | OS_XUSR) // read, write, execute/search, owner +#define OS_RGRP 00040 // read permission, group +#define OS_WGRP 00020 // write permission, group +#define OS_XGRP 00010 // execute/search permission, group +#define OS_RWXG (OS_RGRP | OS_WGRP | OS_XGRP) // read, write, execute/search, group +#define OS_ROTH 00004 // read permission, other +#define OS_WOTH 00002 // write permission, other +#define OS_XOTH 00001 // execute/search permission, other +#define OS_RWXO (OS_ROTH | OS_WOTH | OS_XOTH) // read, write, execute/search, other +#define OS_RUGO (OS_RUSR | OS_RGRP | OS_ROTH) +#define OS_WUGO (OS_WUSR | OS_WGRP | OS_WOTH) +#define OS_XUGO (OS_XUSR | OS_XGRP | OS_XOTH) + +// Trigger for collecting GPU state for later extraction. +NV_STATUS RmLogGpuCrash(OBJGPU *); + +// This is callback function in the miniport. +// The argument is a device extension, and must be cast as such to be useful. +typedef void (*MINIPORT_CALLBACK)(void*); + +NV_STATUS osPackageRegistry(OBJGPU *pGpu, PACKED_REGISTRY_TABLE *, NvU32 *); + +#endif // _OS_CUSTOM_H_ diff --git a/userspace/sdks/nv525/nvalloc/unix/include/osapi.h b/userspace/sdks/nv525/nvalloc/unix/include/osapi.h new file mode 100644 index 0000000..7c71874 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/include/osapi.h @@ -0,0 +1,192 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _OSAPI_H_ +#define _OSAPI_H_ + +#include "core/system.h" +#include "gpu/gpu.h" + +#include // NV_DBG_ERRORS +#include +#include + +#if defined(__use_altstack__) +#if defined(QA_BUILD) +//--------------------------------------------------------------------------- +// +// 32 bit debug marker values. +// +//--------------------------------------------------------------------------- + +#define NV_MARKER1 (NvU32)(('M' << 24) | ('R' << 16) | ('V' << 8) | 'N') +#define NV_MARKER2 (NvU32)(('N' << 24) | ('V' << 16) | ('R' << 8) | 'M') + +// +// The two macros below implement a simple alternate stack usage sanity +// check for QA_BUILD RM builds. NV_ALTSTACK_WRITE_MARKERS() fills +// altstacks with NV_MARKER1, which enables NV_ALTSTACK_CHECK_MARKERS() +// to determine the stack usage fairly reliably by looking for the +// first clobbered marker. If more than 7/8 of the alternate stack were +// used, NV_ALTSTACK_CHECK_MARKERS() prints an error and asserts. +// +#define NV_ALTSTACK_WRITE_MARKERS(sp) \ +{ \ + NvU32 i, *stack = (void *)(sp)->stack; \ + for (i = 0; i < ((sp)->size / sizeof(NvU32)); i++) \ + stack[i] = NV_MARKER1; \ +} + +#define NV_ALTSTACK_CHECK_MARKERS(sp) \ +{ \ + NvU32 i, *stack = (void *)(sp)->stack; \ + for (i = 0; i < ((sp)->size / sizeof(NvU32)); i++) \ + { \ + if (stack[i] != NV_MARKER1) \ + break; \ + } \ + if ((i * sizeof(NvU32)) < ((sp)->size / 8)) \ + { \ + nv_printf(NV_DBG_ERRORS, "NVRM: altstack: used %d of %d bytes!\n", \ + ((sp)->size - (i * sizeof(NvU32))), (sp)->size); \ + NV_ASSERT_PRECOMP((i * sizeof(NvU32)) >= ((sp)->size / 8)); \ + } \ +} +#else +#define NV_ALTSTACK_WRITE_MARKERS(sp) +#define NV_ALTSTACK_CHECK_MARKERS(sp) +#endif +#if defined(NVCPU_X86_64) +#define NV_ENTER_RM_RUNTIME(sp,fp) \ +{ \ + NV_ALTSTACK_WRITE_MARKERS(sp); \ + __asm__ __volatile__ ("movq %%rbp,%0" : "=r" (fp)); /* save %rbp */ \ + __asm__ __volatile__ ("movq %0,%%rbp" :: "r" ((sp)->top)); \ +} + +#define NV_EXIT_RM_RUNTIME(sp,fp) \ +{ \ + register void *__rbp __asm__ ("rbp"); \ + if (__rbp != (sp)->top) \ + { \ + nv_printf(NV_DBG_ERRORS, "NVRM: detected corrupted runtime stack!\n"); \ + NV_ASSERT_PRECOMP(__rbp == (sp)->top); \ + } \ + NV_ALTSTACK_CHECK_MARKERS(sp); \ + __asm__ __volatile__ ("movq %0,%%rbp" :: "r" (fp)); /* restore %rbp */ \ +} +#else +#error "gcc \"altstacks\" support is not implemented on this platform!" +#endif +#else +#define NV_ENTER_RM_RUNTIME(sp,fp) { (void)sp; (void)fp; } +#define NV_EXIT_RM_RUNTIME(sp,fp) +#endif + +void RmShutdownRm (void); + +NvBool RmInitPrivateState (nv_state_t *); +void RmFreePrivateState (nv_state_t *); + +NvBool RmInitAdapter (nv_state_t *); +NvBool RmPartiallyInitAdapter (nv_state_t *); +void RmShutdownAdapter (nv_state_t *); +void RmDisableAdapter (nv_state_t *); +void RmPartiallyDisableAdapter(nv_state_t *); +NV_STATUS RmGetAdapterStatus (nv_state_t *, NvU32 *); +NV_STATUS RmExcludeAdapter (nv_state_t *); + +NvBool RmGpuHasIOSpaceEnabled (nv_state_t *); + +void RmFreeUnusedClients (nv_state_t *, nv_file_private_t *); +NV_STATUS RmIoctl (nv_state_t *, nv_file_private_t *, NvU32, void *, NvU32); + +NV_STATUS RmAllocOsEvent (NvHandle, nv_file_private_t *, NvU32); +NV_STATUS RmFreeOsEvent (NvHandle, NvU32); + +void RmI2cAddGpuPorts(nv_state_t *); + +NV_STATUS RmInitX86EmuState(OBJGPU *); +void RmFreeX86EmuState(OBJGPU *); +NV_STATUS RmPowerSourceChangeEvent(nv_state_t *, NvU32); + +const NvU8 *RmGetGpuUuidRaw(nv_state_t *); + +NV_STATUS nv_vbios_call(OBJGPU *, NvU32 *, NvU32 *); + +int amd_adv_spec_cache_feature(OBJOS *); +int amd_msr_c0011022_incompatible(OBJOS *); + +NV_STATUS rm_get_adapter_status (nv_state_t *, NvU32 *); + +NV_STATUS rm_alloc_os_event (NvHandle, nv_file_private_t *, NvU32); +NV_STATUS rm_free_os_event (NvHandle, NvU32); +NV_STATUS rm_get_event_data (nv_file_private_t *, NvP64, NvU32 *); +void rm_client_free_os_events (NvHandle); + +NV_STATUS rm_create_mmap_context (NvHandle, NvHandle, NvHandle, NvP64, NvU64, NvU64, NvU32, NvU32); +NV_STATUS rm_update_device_mapping_info (NvHandle, NvHandle, NvHandle, void *, void *); + +NV_STATUS rm_access_registry (NvHandle, NvHandle, NvU32, NvP64, NvU32, NvP64, NvU32, NvP64, NvU32 *, NvU32 *, NvU32 *); + +// registry management +NV_STATUS RmInitRegistry (void); +NV_STATUS RmDestroyRegistry (nv_state_t *); + +NV_STATUS RmWriteRegistryDword (nv_state_t *, const char *, NvU32 ); +NV_STATUS RmReadRegistryDword (nv_state_t *, const char *, NvU32 *); +NV_STATUS RmWriteRegistryString (nv_state_t *, const char *, const char *, NvU32); +NV_STATUS RmReadRegistryBinary (nv_state_t *, const char *, NvU8 *, NvU32 *); +NV_STATUS RmWriteRegistryBinary (nv_state_t *, const char *, NvU8 *, NvU32); +NV_STATUS RmReadRegistryString (nv_state_t *, const char *, NvU8 *, NvU32 *); + +NV_STATUS RmPackageRegistry (nv_state_t *, PACKED_REGISTRY_TABLE *, NvU32 *); + +NvBool RmIsNvifFunctionSupported(NvU32, NvU32); +void RmInitAcpiMethods (OBJOS *, OBJSYS *, OBJGPU *); +void RmUnInitAcpiMethods (OBJSYS *); + +void RmInflateOsToRmPageArray (RmPhysAddr *, NvU64); +void RmDeflateRmToOsPageArray (RmPhysAddr *, NvU64); + +void RmInitS0ixPowerManagement (nv_state_t *); +void RmInitDeferredDynamicPowerManagement (nv_state_t *); +void RmDestroyDeferredDynamicPowerManagement(nv_state_t *); + +NV_STATUS os_ref_dynamic_power (nv_state_t *, nv_dynamic_power_mode_t); +void os_unref_dynamic_power (nv_state_t *, nv_dynamic_power_mode_t); +void RmHandleDisplayChange (nvidia_stack_t *, nv_state_t *); +void RmUpdateGc6ConsoleRefCount (nv_state_t *, NvBool); + +NvBool rm_get_uefi_console_status (nv_state_t *); +NvU64 rm_get_uefi_console_size (nv_state_t *, NvU64 *); + +RM_API *RmUnixRmApiPrologue (nv_state_t *, THREAD_STATE_NODE *, NvU32 module); +void RmUnixRmApiEpilogue (nv_state_t *, THREAD_STATE_NODE *); + +static inline NvBool rm_is_system_notebook(void) +{ + return (nv_is_chassis_notebook() || nv_acpi_is_battery_present()); +} + +#endif // _OSAPI_H_ diff --git a/userspace/sdks/nv525/nvalloc/unix/include/osfuncs.h b/userspace/sdks/nv525/nvalloc/unix/include/osfuncs.h new file mode 100644 index 0000000..7afbf63 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/include/osfuncs.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef OSFUNCS_H +#define OSFUNCS_H + +/**************** Resource Manager Defines and Structures ******************\ +* * +* Declarations for the Operating System Specific Functions. * +* * +\***************************************************************************/ + +#include + +OSQueueWorkItem osQueueWorkItem; +OSQueueWorkItemWithFlags osQueueWorkItemWithFlags; +OSQueueSystemWorkItem osQueueSystemWorkItem; +OSDbgBreakpointEnabled osDbgBreakpointEnabled; + +void* osGetStereoDongleInterface(void); + +OSCallACPI_DSM osCallACPI_DSM; +OSCallACPI_DDC osCallACPI_DDC; +OSCallACPI_NVHG_ROM osCallACPI_NVHG_ROM; +OSCallACPI_DOD osCallACPI_DOD; +OSCallACPI_MXDS osCallACPI_MXDS; +OSCallACPI_MXDM osCallACPI_MXDM; + +#if defined(NVCPU_X86_64) +OSnv_rdcr4 nv_rdcr4; +NvU64 nv_rdcr3(OBJOS *); +OSnv_cpuid nv_cpuid; +#endif + +#endif // OSFUNCS_H diff --git a/userspace/sdks/nv525/nvalloc/unix/include/rmobjexportimport.h b/userspace/sdks/nv525/nvalloc/unix/include/rmobjexportimport.h new file mode 100644 index 0000000..1330ad8 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/include/rmobjexportimport.h @@ -0,0 +1,42 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _RMOBJEXPORTIMPORT_H_ +#define _RMOBJEXPORTIMPORT_H_ + +#include "nvstatus.h" + +typedef NvHandle RmObjExportHandle; + +NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject, + RmObjExportHandle *pDstObject, NvU32 *pDeviceInstance); + +void RmFreeObjExportHandle(RmObjExportHandle hObject); + +NV_STATUS RmImportObject(NvHandle hDstClient, NvHandle hDstParent, + NvHandle *phDstObject, RmObjExportHandle hSrcObject, + NvU8 *pObjectType); + +NV_STATUS RmGetExportObjectInfo(RmObjExportHandle hSrcObject, NvU32 *deviceInstance); +#endif // _RMOBJEXPORTIMPORT_H_ + diff --git a/userspace/sdks/nv525/nvalloc/unix/src/asm/x86/nv_cpuid.c b/userspace/sdks/nv525/nvalloc/unix/src/asm/x86/nv_cpuid.c new file mode 100644 index 0000000..0ebb1c8 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/src/asm/x86/nv_cpuid.c @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2013 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +/* inline assembler routines for UNIX platforms */ + +#if defined(NVCPU_X86_64) + +NvS32 nv_cpuid( + OBJOS *pOS, + NvS32 op, + NvS32 subop, + NvU32 *eax, + NvU32 *ebx, + NvU32 *ecx, + NvU32 *edx +) +{ + asm volatile (" cpuid \n" + : "=a" (*eax), + "=b" (*ebx), + "=c" (*ecx), + "=d" (*edx) + : "a" (op), + "c" (subop) + : "cc"); + + return 1; +} + +#endif diff --git a/userspace/sdks/nv525/nvalloc/unix/src/asm/x86/nv_rdcr.c b/userspace/sdks/nv525/nvalloc/unix/src/asm/x86/nv_rdcr.c new file mode 100644 index 0000000..56e6bfd --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/src/asm/x86/nv_rdcr.c @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2013 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +/* inline assembler routines for UNIX platforms */ + +#if defined(NVCPU_X86_64) + +NvU32 nv_rdcr4(OBJOS *pOS) +{ + NvU64 val; + asm volatile ("movq %%cr4,%0" : "=r" (val)); + return (NvU32)val; +} + +NvU64 nv_rdcr3(OBJOS *pOS) +{ + NvU64 val; + asm volatile ("movq %%cr3,%0" : "=r" (val)); + return val; +} + +#endif diff --git a/userspace/sdks/nv525/nvalloc/unix/src/escape.c b/userspace/sdks/nv525/nvalloc/unix/src/escape.c new file mode 100644 index 0000000..c7b451a --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/src/escape.c @@ -0,0 +1,938 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + + +//***************************** Module Header ********************************** +// +// This code is linked into the resource manager proper. It receives the +// ioctl from the resource manager's customer, unbundles the args and +// calls the correct resman routines. +// +//****************************************************************************** + +#include +#include +#include +#include +#include +#include +#include + +#include +#include // NV01_ROOT +#include // NV01_ROOT_NON_PRIV +#include // NV01_EVENT +#include // NV01_MEMORY_SYSTEM +#include // NV01_MEMORY_SYSTEM_OS_DESCRIPTOR + +#include + +#define NV_CTL_DEVICE_ONLY(nv) \ +{ \ + if (((nv)->flags & NV_FLAG_CONTROL) == 0) \ + { \ + rmStatus = NV_ERR_INVALID_ARGUMENT; \ + goto done; \ + } \ +} + +#define NV_ACTUAL_DEVICE_ONLY(nv) \ +{ \ + if (((nv)->flags & NV_FLAG_CONTROL) != 0) \ + { \ + rmStatus = NV_ERR_INVALID_ARGUMENT; \ + goto done; \ + } \ +} + +static NvBool RmIsDeviceRefNeeded(NVOS54_PARAMETERS *pApi) +{ + switch(pApi->cmd) + { + case NV00FD_CTRL_CMD_ATTACH_MEM: + return NV_TRUE; + default: + return NV_FALSE; + } +} + +static NV_STATUS RmGetDeviceFd(NVOS54_PARAMETERS *pApi, NvS32 *pFd) +{ + RMAPI_PARAM_COPY paramCopy; + void *pKernelParams; + NvU32 paramSize; + NV_STATUS status; + + *pFd = -1; + + switch(pApi->cmd) + { + case NV00FD_CTRL_CMD_ATTACH_MEM: + paramSize = sizeof(NV00FD_CTRL_ATTACH_MEM_PARAMS); + break; + default: + return NV_ERR_INVALID_ARGUMENT; + } + + RMAPI_PARAM_COPY_INIT(paramCopy, pKernelParams, pApi->params, paramSize, 1); + + status = rmapiParamsAcquire(¶mCopy, NV_TRUE); + if (status != NV_OK) + return status; + + switch(pApi->cmd) + { + case NV00FD_CTRL_CMD_ATTACH_MEM: + *pFd = (NvS32)((NV00FD_CTRL_ATTACH_MEM_PARAMS *)pKernelParams)->devDescriptor; + break; + default: + NV_ASSERT(0); + break; + } + + NV_ASSERT(rmapiParamsRelease(¶mCopy) == NV_OK); + + return status; +} + +// Only return errors through pApi->status +static void RmCreateOsDescriptor(NVOS32_PARAMETERS *pApi, API_SECURITY_INFO secInfo) +{ + NV_STATUS rmStatus; + NvBool writable; + NvU32 flags = 0; + NvU64 allocSize, pageCount, *pPteArray = NULL; + void *pDescriptor, *pPageArray = NULL; + + pDescriptor = NvP64_VALUE(pApi->data.AllocOsDesc.descriptor); + if (((NvUPtr)pDescriptor & ~os_page_mask) != 0) + { + rmStatus = NV_ERR_NOT_SUPPORTED; + goto done; + } + + // Check to prevent an NvU64 overflow + if ((pApi->data.AllocOsDesc.limit + 1) == 0) + { + rmStatus = NV_ERR_INVALID_LIMIT; + goto done; + } + + allocSize = (pApi->data.AllocOsDesc.limit + 1); + pageCount = (1 + ((allocSize - 1) / os_page_size)); + + writable = FLD_TEST_DRF(OS32, _ATTR2, _PROTECTION_USER, _READ_WRITE, pApi->data.AllocOsDesc.attr2); + + flags = FLD_SET_DRF_NUM(_LOCK_USER_PAGES, _FLAGS, _WRITE, writable, flags); + rmStatus = os_lock_user_pages(pDescriptor, pageCount, &pPageArray, flags); + if (rmStatus == NV_OK) + { + pApi->data.AllocOsDesc.descriptor = (NvP64)(NvUPtr)pPageArray; + pApi->data.AllocOsDesc.descriptorType = NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY; + } + else if (rmStatus == NV_ERR_INVALID_ADDRESS) + { + rmStatus = os_lookup_user_io_memory(pDescriptor, pageCount, + &pPteArray, &pPageArray); + if (rmStatus == NV_OK) + { + if (pPageArray != NULL) + { + pApi->data.AllocOsDesc.descriptor = (NvP64)(NvUPtr)pPageArray; + pApi->data.AllocOsDesc.descriptorType = NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY; + } + else if (pPteArray != NULL) + { + pApi->data.AllocOsDesc.descriptor = (NvP64)(NvUPtr)pPteArray; + pApi->data.AllocOsDesc.descriptorType = NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY; + } + else + { + NV_ASSERT_FAILED("unknown memory import type"); + rmStatus = NV_ERR_NOT_SUPPORTED; + } + } + } + if (rmStatus != NV_OK) + goto done; + + Nv04VidHeapControlWithSecInfo(pApi, secInfo); + + if (pApi->status != NV_OK) + { + switch (pApi->data.AllocOsDesc.descriptorType) + { + default: + break; + case NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY: + os_unlock_user_pages(pageCount, pPageArray); + break; + } + } + +done: + if (rmStatus != NV_OK) + pApi->status = rmStatus; +} + +// Only return errors through pApi->status +static void RmAllocOsDescriptor(NVOS02_PARAMETERS *pApi, API_SECURITY_INFO secInfo) +{ + NV_STATUS rmStatus = NV_OK; + NvU32 flags, attr, attr2; + NVOS32_PARAMETERS *pVidHeapParams; + + if (!FLD_TEST_DRF(OS02, _FLAGS, _LOCATION, _PCI, pApi->flags) || + !FLD_TEST_DRF(OS02, _FLAGS, _MAPPING, _NO_MAP, pApi->flags)) + { + rmStatus = NV_ERR_INVALID_FLAGS; + goto done; + } + + attr = DRF_DEF(OS32, _ATTR, _LOCATION, _PCI); + + if (FLD_TEST_DRF(OS02, _FLAGS, _COHERENCY, _CACHED, pApi->flags) || + FLD_TEST_DRF(OS02, _FLAGS, _COHERENCY, _WRITE_BACK, pApi->flags)) + { + attr = FLD_SET_DRF(OS32, _ATTR, _COHERENCY, _WRITE_BACK, attr); + } + else if (FLD_TEST_DRF(OS02, _FLAGS, _COHERENCY, _UNCACHED, pApi->flags)) + attr = FLD_SET_DRF(OS32, _ATTR, _COHERENCY, _UNCACHED, attr); + else { + rmStatus = NV_ERR_INVALID_FLAGS; + goto done; + } + + if (FLD_TEST_DRF(OS02, _FLAGS, _PHYSICALITY, _CONTIGUOUS, pApi->flags)) + attr = FLD_SET_DRF(OS32, _ATTR, _PHYSICALITY, _CONTIGUOUS, attr); + else + attr = FLD_SET_DRF(OS32, _ATTR, _PHYSICALITY, _NONCONTIGUOUS, attr); + + if (FLD_TEST_DRF(OS02, _FLAGS, _GPU_CACHEABLE, _YES, pApi->flags)) + attr2 = DRF_DEF(OS32, _ATTR2, _GPU_CACHEABLE, _YES); + else + attr2 = DRF_DEF(OS32, _ATTR2, _GPU_CACHEABLE, _NO); + + pVidHeapParams = portMemAllocNonPaged(sizeof(NVOS32_PARAMETERS)); + if (pVidHeapParams == NULL) + { + rmStatus = NV_ERR_NO_MEMORY; + goto done; + } + portMemSet(pVidHeapParams, 0, sizeof(NVOS32_PARAMETERS)); + + pVidHeapParams->hRoot = pApi->hRoot; + pVidHeapParams->hObjectParent = pApi->hObjectParent; + pVidHeapParams->function = NVOS32_FUNCTION_ALLOC_OS_DESCRIPTOR; + + flags = (NVOS32_ALLOC_FLAGS_MEMORY_HANDLE_PROVIDED | + NVOS32_ALLOC_FLAGS_MAP_NOT_REQUIRED); + + if (DRF_VAL(OS02, _FLAGS, _ALLOC_USER_READ_ONLY, pApi->flags)) + attr2 = FLD_SET_DRF(OS32, _ATTR2, _PROTECTION_USER, _READ_ONLY, attr2); + + // Currently CPU-RO memory implies GPU-RO as well + if (DRF_VAL(OS02, _FLAGS, _ALLOC_DEVICE_READ_ONLY, pApi->flags) || + DRF_VAL(OS02, _FLAGS, _ALLOC_USER_READ_ONLY, pApi->flags)) + attr2 = FLD_SET_DRF(OS32, _ATTR2, _PROTECTION_DEVICE, _READ_ONLY, attr2); + + pVidHeapParams->data.AllocOsDesc.hMemory = pApi->hObjectNew; + pVidHeapParams->data.AllocOsDesc.flags = flags; + pVidHeapParams->data.AllocOsDesc.attr = attr; + pVidHeapParams->data.AllocOsDesc.attr2 = attr2; + pVidHeapParams->data.AllocOsDesc.descriptor = pApi->pMemory; + pVidHeapParams->data.AllocOsDesc.limit = pApi->limit; + pVidHeapParams->data.AllocOsDesc.descriptorType = NVOS32_DESCRIPTOR_TYPE_VIRTUAL_ADDRESS; + + RmCreateOsDescriptor(pVidHeapParams, secInfo); + + pApi->status = pVidHeapParams->status; + + portMemFree(pVidHeapParams); + +done: + if (rmStatus != NV_OK) + pApi->status = rmStatus; +} + +ct_assert(NV_OFFSETOF(NVOS21_PARAMETERS, hRoot) == NV_OFFSETOF(NVOS64_PARAMETERS, hRoot)); +ct_assert(NV_OFFSETOF(NVOS21_PARAMETERS, hObjectParent) == NV_OFFSETOF(NVOS64_PARAMETERS, hObjectParent)); +ct_assert(NV_OFFSETOF(NVOS21_PARAMETERS, hObjectNew) == NV_OFFSETOF(NVOS64_PARAMETERS, hObjectNew)); +ct_assert(NV_OFFSETOF(NVOS21_PARAMETERS, hClass) == NV_OFFSETOF(NVOS64_PARAMETERS, hClass)); +ct_assert(NV_OFFSETOF(NVOS21_PARAMETERS, pAllocParms) == NV_OFFSETOF(NVOS64_PARAMETERS, pAllocParms)); + +NV_STATUS RmIoctl( + nv_state_t *nv, + nv_file_private_t *nvfp, + NvU32 cmd, + void *data, + NvU32 dataSize +) +{ + NV_STATUS rmStatus = NV_ERR_GENERIC; + API_SECURITY_INFO secInfo = { }; + + secInfo.privLevel = osIsAdministrator() ? RS_PRIV_LEVEL_USER_ROOT : RS_PRIV_LEVEL_USER; + secInfo.paramLocation = PARAM_LOCATION_USER; + secInfo.pProcessToken = NULL; + secInfo.gpuOsInfo = NULL; + secInfo.clientOSInfo = nvfp->ctl_nvfp; + if (secInfo.clientOSInfo == NULL) + secInfo.clientOSInfo = nvfp; + + switch (cmd) + { + case NV_ESC_RM_ALLOC_MEMORY: + { + nv_ioctl_nvos02_parameters_with_fd *pApi; + NVOS02_PARAMETERS *pParms; + + pApi = data; + pParms = &pApi->params; + + NV_ACTUAL_DEVICE_ONLY(nv); + + if (dataSize != sizeof(nv_ioctl_nvos02_parameters_with_fd)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + if (pParms->hClass == NV01_MEMORY_SYSTEM_OS_DESCRIPTOR) + RmAllocOsDescriptor(pParms, secInfo); + else + { + NvU32 flags = pParms->flags; + + Nv01AllocMemoryWithSecInfo(pParms, secInfo); + + // + // If the system memory is going to be mapped immediately, + // create the mmap context for it now. + // + if ((pParms->hClass == NV01_MEMORY_SYSTEM) && + (!FLD_TEST_DRF(OS02, _FLAGS, _ALLOC, _NONE, flags)) && + (!FLD_TEST_DRF(OS02, _FLAGS, _MAPPING, _NO_MAP, flags)) && + (pParms->status == NV_OK)) + { + if (rm_create_mmap_context(pParms->hRoot, + pParms->hObjectParent, pParms->hObjectNew, + pParms->pMemory, pParms->limit + 1, 0, + NV_MEMORY_DEFAULT, + pApi->fd) != NV_OK) + { + NV_PRINTF(LEVEL_WARNING, + "could not create mmap context for %p\n", + NvP64_VALUE(pParms->pMemory)); + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + } + } + + break; + } + + case NV_ESC_RM_ALLOC_OBJECT: + { + NVOS05_PARAMETERS *pApi = data; + + NV_CTL_DEVICE_ONLY(nv); + + if (dataSize != sizeof(NVOS05_PARAMETERS)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + Nv01AllocObjectWithSecInfo(pApi, secInfo); + break; + } + + case NV_ESC_RM_ALLOC: + { + NVOS21_PARAMETERS *pApi = data; + NVOS64_PARAMETERS *pApiAccess = data; + NvBool bAccessApi = (dataSize == sizeof(NVOS64_PARAMETERS)); + + if ((dataSize != sizeof(NVOS21_PARAMETERS)) && + (dataSize != sizeof(NVOS64_PARAMETERS))) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + switch (pApi->hClass) + { + case NV01_ROOT: + case NV01_ROOT_CLIENT: + case NV01_ROOT_NON_PRIV: + { + NV_CTL_DEVICE_ONLY(nv); + + // Force userspace client allocations to be the _CLIENT class. + pApi->hClass = NV01_ROOT_CLIENT; + break; + } + case NV01_EVENT: + case NV01_EVENT_OS_EVENT: + case NV01_EVENT_KERNEL_CALLBACK: + case NV01_EVENT_KERNEL_CALLBACK_EX: + { + break; + } + default: + { + NV_CTL_DEVICE_ONLY(nv); + break; + } + } + + if (!bAccessApi) + { + Nv04AllocWithSecInfo(pApi, secInfo); + } + else + { + Nv04AllocWithAccessSecInfo(pApiAccess, secInfo); + } + + break; + } + + case NV_ESC_RM_FREE: + { + NVOS00_PARAMETERS *pApi = data; + + NV_CTL_DEVICE_ONLY(nv); + + if (dataSize != sizeof(NVOS00_PARAMETERS)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + Nv01FreeWithSecInfo(pApi, secInfo); + + if (pApi->status == NV_OK && + pApi->hObjectOld == pApi->hRoot) + { + rm_client_free_os_events(pApi->hRoot); + } + + break; + } + + case NV_ESC_RM_VID_HEAP_CONTROL: + { + NVOS32_PARAMETERS *pApi = data; + + NV_CTL_DEVICE_ONLY(nv); + + if (dataSize != sizeof(NVOS32_PARAMETERS)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + if (pApi->function == NVOS32_FUNCTION_ALLOC_OS_DESCRIPTOR) + RmCreateOsDescriptor(pApi, secInfo); + else + Nv04VidHeapControlWithSecInfo(pApi, secInfo); + + break; + } + + case NV_ESC_RM_I2C_ACCESS: + { + NVOS_I2C_ACCESS_PARAMS *pApi = data; + + NV_ACTUAL_DEVICE_ONLY(nv); + + if (dataSize != sizeof(NVOS_I2C_ACCESS_PARAMS)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + Nv04I2CAccessWithSecInfo(pApi, secInfo); + break; + } + + case NV_ESC_RM_IDLE_CHANNELS: + { + NVOS30_PARAMETERS *pApi = data; + + NV_CTL_DEVICE_ONLY(nv); + + if (dataSize != sizeof(NVOS30_PARAMETERS)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + Nv04IdleChannelsWithSecInfo(pApi, secInfo); + break; + } + + case NV_ESC_RM_MAP_MEMORY: + { + nv_ioctl_nvos33_parameters_with_fd *pApi; + NVOS33_PARAMETERS *pParms; + + pApi = data; + pParms = &pApi->params; + + NV_CTL_DEVICE_ONLY(nv); + + if (dataSize != sizeof(nv_ioctl_nvos33_parameters_with_fd)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + // Don't allow userspace to override the caching type + pParms->flags = FLD_SET_DRF(OS33, _FLAGS, _CACHING_TYPE, _DEFAULT, pParms->flags); + Nv04MapMemoryWithSecInfo(pParms, secInfo); + + if (pParms->status == NV_OK) + { + pParms->status = rm_create_mmap_context(pParms->hClient, + pParms->hDevice, pParms->hMemory, + pParms->pLinearAddress, pParms->length, + pParms->offset, + DRF_VAL(OS33, _FLAGS, _CACHING_TYPE, pParms->flags), + pApi->fd); + if (pParms->status != NV_OK) + { + NVOS34_PARAMETERS params; + portMemSet(¶ms, 0, sizeof(NVOS34_PARAMETERS)); + params.hClient = pParms->hClient; + params.hDevice = pParms->hDevice; + params.hMemory = pParms->hMemory; + params.pLinearAddress = pParms->pLinearAddress; + params.flags = pParms->flags; + Nv04UnmapMemoryWithSecInfo(¶ms, secInfo); + } + } + break; + } + + case NV_ESC_RM_UNMAP_MEMORY: + { + NVOS34_PARAMETERS *pApi = data; + + NV_CTL_DEVICE_ONLY(nv); + + if (dataSize != sizeof(NVOS34_PARAMETERS)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + Nv04UnmapMemoryWithSecInfo(pApi, secInfo); + break; + } + + case NV_ESC_RM_ACCESS_REGISTRY: + { + NVOS38_PARAMETERS *pApi = data; + + NV_CTL_DEVICE_ONLY(nv); + + if (dataSize != sizeof(NVOS38_PARAMETERS)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + pApi->status = rm_access_registry(pApi->hClient, + pApi->hObject, + pApi->AccessType, + pApi->pDevNode, + pApi->DevNodeLength, + pApi->pParmStr, + pApi->ParmStrLength, + pApi->pBinaryData, + &pApi->BinaryDataLength, + &pApi->Data, + &pApi->Entry); + break; + } + + case NV_ESC_RM_ALLOC_CONTEXT_DMA2: + { + NVOS39_PARAMETERS *pApi = data; + + NV_CTL_DEVICE_ONLY(nv); + + if (dataSize != sizeof(NVOS39_PARAMETERS)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + Nv04AllocContextDmaWithSecInfo(pApi, secInfo); + break; + } + + case NV_ESC_RM_BIND_CONTEXT_DMA: + { + NVOS49_PARAMETERS *pApi = data; + + NV_CTL_DEVICE_ONLY(nv); + + if (dataSize != sizeof(NVOS49_PARAMETERS)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + Nv04BindContextDmaWithSecInfo(pApi, secInfo); + break; + } + + case NV_ESC_RM_MAP_MEMORY_DMA: + { + NVOS46_PARAMETERS *pApi = data; + + NV_CTL_DEVICE_ONLY(nv); + + if (dataSize != sizeof(NVOS46_PARAMETERS)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + Nv04MapMemoryDmaWithSecInfo(pApi, secInfo); + break; + } + + case NV_ESC_RM_UNMAP_MEMORY_DMA: + { + NVOS47_PARAMETERS *pApi = data; + + NV_CTL_DEVICE_ONLY(nv); + + if (dataSize != sizeof(NVOS47_PARAMETERS)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + Nv04UnmapMemoryDmaWithSecInfo(pApi, secInfo); + break; + } + + case NV_ESC_RM_DUP_OBJECT: + { + NVOS55_PARAMETERS *pApi = data; + + NV_CTL_DEVICE_ONLY(nv); + + if (dataSize != sizeof(NVOS55_PARAMETERS)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + Nv04DupObjectWithSecInfo(pApi, secInfo); + break; + } + + case NV_ESC_RM_SHARE: + { + NVOS57_PARAMETERS *pApi = data; + + NV_CTL_DEVICE_ONLY(nv); + + if (dataSize != sizeof(NVOS57_PARAMETERS)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + Nv04ShareWithSecInfo(pApi, secInfo); + break; + } + + case NV_ESC_ALLOC_OS_EVENT: + { + nv_ioctl_alloc_os_event_t *pApi = data; + + if (dataSize != sizeof(nv_ioctl_alloc_os_event_t)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + pApi->Status = rm_alloc_os_event(pApi->hClient, + nvfp, + pApi->fd); + break; + } + + case NV_ESC_FREE_OS_EVENT: + { + nv_ioctl_free_os_event_t *pApi = data; + + if (dataSize != sizeof(nv_ioctl_free_os_event_t)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + pApi->Status = rm_free_os_event(pApi->hClient, pApi->fd); + break; + } + + case NV_ESC_RM_GET_EVENT_DATA: + { + NVOS41_PARAMETERS *pApi = data; + + if (dataSize != sizeof(NVOS41_PARAMETERS)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + pApi->status = rm_get_event_data(nvfp, + pApi->pEvent, + &pApi->MoreEvents); + break; + } + + case NV_ESC_STATUS_CODE: + { + nv_state_t *pNv; + nv_ioctl_status_code_t *pApi = data; + + NV_CTL_DEVICE_ONLY(nv); + + if (dataSize != sizeof(nv_ioctl_status_code_t)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + pNv = nv_get_adapter_state(pApi->domain, pApi->bus, pApi->slot); + if (pNv == NULL) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + rmStatus = rm_get_adapter_status(pNv, &pApi->status); + + if (rmStatus != NV_OK) + goto done; + + break; + } + + case NV_ESC_RM_CONTROL: + { + NVOS54_PARAMETERS *pApi = data; + void *priv = NULL; + nv_file_private_t *dev_nvfp = NULL; + NvS32 fd; + + NV_CTL_DEVICE_ONLY(nv); + + if (dataSize != sizeof(NVOS54_PARAMETERS)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + if (RmIsDeviceRefNeeded(pApi)) + { + rmStatus = RmGetDeviceFd(pApi, &fd); + if (rmStatus != NV_OK) + { + goto done; + } + + dev_nvfp = nv_get_file_private(fd, NV_FALSE, &priv); + if (dev_nvfp == NULL) + { + rmStatus = NV_ERR_INVALID_DEVICE; + goto done; + } + + // Check to avoid cyclic dependency with NV_ESC_REGISTER_FD + if (!portAtomicCompareAndSwapU32(&dev_nvfp->register_or_refcount, + NVFP_TYPE_REFCOUNTED, + NVFP_TYPE_NONE)) + { + // Is this already refcounted... + if (dev_nvfp->register_or_refcount != NVFP_TYPE_REFCOUNTED) + { + nv_put_file_private(priv); + rmStatus = NV_ERR_IN_USE; + goto done; + } + } + + secInfo.gpuOsInfo = priv; + } + + Nv04ControlWithSecInfo(pApi, secInfo); + + if ((pApi->status != NV_OK) && (priv != NULL)) + { + // + // No need to reset `register_or_refcount` as it might be set + // for previous successful calls. We let it clear with FD close. + // + nv_put_file_private(priv); + + secInfo.gpuOsInfo = NULL; + } + + break; + } + + case NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO: + { + NVOS56_PARAMETERS *pApi = data; + void *pOldCpuAddress; + void *pNewCpuAddress; + + NV_CTL_DEVICE_ONLY(nv); + + if (dataSize != sizeof(NVOS56_PARAMETERS)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + pOldCpuAddress = NvP64_VALUE(pApi->pOldCpuAddress); + pNewCpuAddress = NvP64_VALUE(pApi->pNewCpuAddress); + + pApi->status = rm_update_device_mapping_info(pApi->hClient, + pApi->hDevice, + pApi->hMemory, + pOldCpuAddress, + pNewCpuAddress); + break; + } + + case NV_ESC_REGISTER_FD: + { + nv_ioctl_register_fd_t *params = data; + void *priv = NULL; + nv_file_private_t *ctl_nvfp; + + if (dataSize != sizeof(nv_ioctl_register_fd_t)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + // LOCK: acquire API lock + rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI); + if (rmStatus != NV_OK) + goto done; + + // If there is already a ctl fd registered on this nvfp, fail. + if (nvfp->ctl_nvfp != NULL) + { + // UNLOCK: release API lock + rmapiLockRelease(); + rmStatus = NV_ERR_INVALID_STATE; + goto done; + } + + // + // Note that this call is valid for both "actual" devices and ctrl + // devices. In particular, NV_ESC_ALLOC_OS_EVENT can be used with + // both types of devices. + // But, the ctl_fd passed in should always correspond to a control FD. + // + ctl_nvfp = nv_get_file_private(params->ctl_fd, + NV_TRUE, /* require ctl fd */ + &priv); + if (ctl_nvfp == NULL) + { + // UNLOCK: release API lock + rmapiLockRelease(); + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + // Disallow self-referential links, and disallow links to FDs that + // themselves have a link. + if ((ctl_nvfp == nvfp) || (ctl_nvfp->ctl_nvfp != NULL)) + { + nv_put_file_private(priv); + // UNLOCK: release API lock + rmapiLockRelease(); + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + // Check to avoid cyclic dependency with device refcounting + if (!portAtomicCompareAndSwapU32(&nvfp->register_or_refcount, + NVFP_TYPE_REGISTERED, + NVFP_TYPE_NONE)) + { + nv_put_file_private(priv); + // UNLOCK: release API lock + rmapiLockRelease(); + rmStatus = NV_ERR_IN_USE; + goto done; + } + + // + // nvfp->ctl_nvfp is read outside the lock, so set it atomically. + // Note that once set, this can never be removed until the fd + // associated with nvfp is closed. We hold on to 'priv' until the + // fd is closed, too, to ensure that the fd associated with + // ctl_nvfp remains valid. + // + portAtomicSetSize(&nvfp->ctl_nvfp, ctl_nvfp); + nvfp->ctl_nvfp_priv = priv; + + // UNLOCK: release API lock + rmapiLockRelease(); + + // NOTE: nv_put_file_private(priv) is not called here. It MUST be + // called during cleanup of this nvfp. + rmStatus = NV_OK; + break; + } + + default: + { + NV_PRINTF(LEVEL_ERROR, "unknown NVRM ioctl command: 0x%x\n", cmd); + goto done; + } + } + + rmStatus = NV_OK; +done: + + return rmStatus; +} diff --git a/userspace/sdks/nv525/nvalloc/unix/src/exports-stubs.c b/userspace/sdks/nv525/nvalloc/unix/src/exports-stubs.c new file mode 100644 index 0000000..4dac378 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/src/exports-stubs.c @@ -0,0 +1,235 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include + +NV_STATUS NV_API_CALL rm_schedule_gpu_wakeup( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + return NV_OK; +} + +void NV_API_CALL rm_init_dynamic_power_management( + nvidia_stack_t *sp, + nv_state_t *nv, + NvBool bPr3AcpiMethodPresent +) +{ +} + +void NV_API_CALL rm_cleanup_dynamic_power_management( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ +} + +void NV_API_CALL rm_enable_dynamic_power_management( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ +} + +NV_STATUS NV_API_CALL rm_ref_dynamic_power( + nvidia_stack_t *sp, + nv_state_t *nv, + nv_dynamic_power_mode_t mode +) +{ + return NV_OK; +} + +void NV_API_CALL rm_unref_dynamic_power( + nvidia_stack_t *sp, + nv_state_t *nv, + nv_dynamic_power_mode_t mode +) +{ +} + +NV_STATUS NV_API_CALL rm_transition_dynamic_power( + nvidia_stack_t *sp, + nv_state_t *nv, + NvBool bEnter +) +{ + return NV_OK; +} + +NV_STATUS NV_API_CALL rm_power_management( + nvidia_stack_t *sp, + nv_state_t *pNv, + nv_pm_action_t pmAction +) +{ + return NV_OK; +} + +const char* NV_API_CALL rm_get_vidmem_power_status( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + return "?"; +} + +const char* NV_API_CALL rm_get_dynamic_power_management_status( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + return "?"; +} + +const char* NV_API_CALL rm_get_gpu_gcx_support( + nvidia_stack_t *sp, + nv_state_t *pNv, + NvBool bGcxTypeGC6 +) +{ + return "?"; +} + +NV_STATUS +subdeviceCtrlCmdOsUnixGc6BlockerRefCnt_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS *pParams +) +{ + return NV_OK; +} + +NV_STATUS +subdeviceCtrlCmdOsUnixAllowDisallowGcoff_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS *pParams +) +{ + return NV_OK; +} + +NV_STATUS +subdeviceCtrlCmdOsUnixAudioDynamicPower_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS *pParams +) +{ + return NV_OK; +} + +void +RmUpdateGc6ConsoleRefCount +( + nv_state_t *nv, + NvBool bIncrease +) +{ +} + +void +RmInitS0ixPowerManagement +( + nv_state_t *nv +) +{ +} + +void +RmInitDeferredDynamicPowerManagement +( + nv_state_t *nv +) +{ +} + +void +RmDestroyDeferredDynamicPowerManagement +( + nv_state_t *nv +) +{ +} + +void RmHandleDisplayChange +( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ +} + +NV_STATUS +os_ref_dynamic_power +( + nv_state_t *nv, + nv_dynamic_power_mode_t mode +) +{ + return NV_OK; +} + +void +os_unref_dynamic_power +( + nv_state_t *nv, + nv_dynamic_power_mode_t mode +) +{ +} + +NV_STATUS +deviceCtrlCmdOsUnixVTSwitch_IMPL +( + Device *pDevice, + NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS *pParams +) +{ + return NV_OK; +} + +NV_STATUS NV_API_CALL rm_save_low_res_mode( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS RmInitX86EmuState(OBJGPU *pGpu) +{ + return NV_OK; +} + +void RmFreeX86EmuState(OBJGPU *pGpu) +{ +} diff --git a/userspace/sdks/nv525/nvalloc/unix/src/gcc_helper.c b/userspace/sdks/nv525/nvalloc/unix/src/gcc_helper.c new file mode 100644 index 0000000..3c1037c --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/src/gcc_helper.c @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +void* memset(void* s, int c, NvUPtr n) +{ + return os_mem_set(s, (NvU8)c, (NvU32)n); +} + +void* memcpy(void* dest, const void* src, NvUPtr n) +{ + return os_mem_copy(dest, src, (NvU32)n); +} diff --git a/userspace/sdks/nv525/nvalloc/unix/src/os-hypervisor.c b/userspace/sdks/nv525/nvalloc/unix/src/os-hypervisor.c new file mode 100644 index 0000000..3982c35 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/src/os-hypervisor.c @@ -0,0 +1,1023 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * + * @file os-hypervisor.c + * @brief OS specific Hypervisor interfaces for RM + * + */ + +#include "os/os.h" +#include "nv.h" +#include "nv-priv.h" +#include +#include +#include "core/thread_state.h" +#include "core/locks.h" +#include "virtualization/kernel_vgpu_mgr.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "kernel/gpu/fifo/kernel_fifo.h" +#include "osapi.h" +#include "virtualization/kernel_hostvgpudeviceapi.h" +#include +#include "gpu/bif/kernel_bif.h" +#include "gpu/bus/kern_bus.h" +#include // NV_PMC_BOOT_1_VGPU +#include "nvdevid.h" + +#define NV_VFIO_PCI_BAR1_REGION_INDEX 1 +#define NV_VFIO_PCI_BAR2_REGION_INDEX 2 +#define NV_VFIO_PCI_BAR3_REGION_INDEX 3 + +static NV_STATUS nv_parse_config_params(const char *, const char *, const char, NvU32 *); + +void hypervisorSetHypervVgpuSupported_IMPL(POBJHYPERVISOR pHypervisor) +{ + pHypervisor->bIsHypervVgpuSupported = NV_TRUE; +} + +NvBool hypervisorIsVgxHyper_IMPL(void) +{ + return os_is_vgx_hyper(); +} + +NV_STATUS hypervisorInjectInterrupt_IMPL +( + POBJHYPERVISOR pHypervisor, + VGPU_NS_INTR *pVgpuNsIntr +) +{ + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + + if (pVgpuNsIntr->pVgpuVfioRef) + status = osVgpuInjectInterrupt(pVgpuNsIntr->pVgpuVfioRef); + else + { + if (pVgpuNsIntr->guestMSIAddr && pVgpuNsIntr->guestMSIData) + { + status = os_inject_vgx_msi((NvU16)pVgpuNsIntr->guestDomainId, + pVgpuNsIntr->guestMSIAddr, + pVgpuNsIntr->guestMSIData); + } + } + + return status; +} + +HYPERVISOR_TYPE NV_API_CALL nv_get_hypervisor_type(void) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + POBJHYPERVISOR pHypervisor = SYS_GET_HYPERVISOR(pSys); + return hypervisorGetHypervisorType(pHypervisor); +} + +static NV_STATUS get_available_instances( + NvU32 *avail_instances, + nv_state_t *pNv, + VGPU_TYPE *vgpuTypeInfo, + NvU32 pgpuIndex, + NvU8 devfn +) +{ + NV_STATUS rmStatus = NV_OK; + OBJGPU *pGpu = NULL; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); + + *avail_instances = 0; + + pGpu = NV_GET_NV_PRIV_PGPU(pNv); + if (pGpu == NULL) + { + NV_PRINTF(LEVEL_ERROR, "%s GPU handle is not valid \n", __FUNCTION__); + rmStatus = NV_ERR_INVALID_STATE; + goto exit; + } + + /* TODO: Needs to have a proper fix this for DriverVM config */ + if (gpuIsSriovEnabled(pGpu) && + !(pHypervisor->getProperty(pHypervisor, PDB_PROP_HYPERVISOR_DRIVERVM_ENABLED))) + { + NvU8 fnId = devfn - pGpu->sriovState.firstVFOffset; + + if (fnId > 63) + { + NV_ASSERT(0); + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto exit; + } + + if (IS_MIG_ENABLED(pGpu)) + { + if (IS_MIG_IN_USE(pGpu)) { + NvU64 swizzIdInUseMask = 0; + NvU32 partitionFlag = PARTITIONID_INVALID; + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + NvU32 id; + + swizzIdInUseMask = kmigmgrGetSwizzIdInUseMask(pGpu, pKernelMIGManager); + + rmStatus = kvgpumgrGetPartitionFlag(vgpuTypeInfo->vgpuTypeId, + &partitionFlag); + if (rmStatus != NV_OK) + { + // Query for a non MIG vgpuType + NV_PRINTF(LEVEL_ERROR, "%s Query for a non MIG vGPU type \n", + __FUNCTION__); + rmStatus = NV_OK; + goto exit; + } + + // Determine valid swizzids not assigned to any vGPU device. + FOR_EACH_INDEX_IN_MASK(64, id, swizzIdInUseMask) + { + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance; + NvU64 mask = 0; + + rmStatus = kmigmgrGetGPUInstanceInfo(pGpu, pKernelMIGManager, + id, &pKernelMIGGpuInstance); + if (rmStatus != NV_OK) + { + // Didn't find requested GPU instance + NV_PRINTF(LEVEL_ERROR, + "No valid GPU instance with SwizzId - %d found\n", id); + goto exit; + } + + mask = NVBIT64(id); + + if (pKernelMIGGpuInstance->partitionFlag == partitionFlag) + { + // Validate that same ID is not already set and VF is available + if (!(mask & pKernelVgpuMgr->pgpuInfo[pgpuIndex].assignedSwizzIdMask) && + !(pKernelVgpuMgr->pgpuInfo[pgpuIndex].createdVfMask & NVBIT64(fnId))) + { + *avail_instances = 1; + break; + } + } + } + FOR_EACH_INDEX_IN_MASK_END; + } + } + else + { + if (pKernelVgpuMgr->pgpuInfo[pgpuIndex].numCreatedVgpu < vgpuTypeInfo->maxInstance) + { + if (vgpuTypeInfo->gpuInstanceSize) + { + // Query for a MIG vgpuType + NV_PRINTF(LEVEL_ERROR, "%s Query for a MIG vGPU type \n", + __FUNCTION__); + rmStatus = NV_OK; + goto exit; + } + + if (!(pKernelVgpuMgr->pgpuInfo[pgpuIndex].createdVfMask & NVBIT64(fnId))) + { + if (kvgpumgrCheckVgpuTypeCreatable(&pKernelVgpuMgr->pgpuInfo[pgpuIndex], vgpuTypeInfo) == NV_OK) + *avail_instances = 1; + } + } + } + } + else + { + if (kvgpumgrCheckVgpuTypeCreatable(&pKernelVgpuMgr->pgpuInfo[pgpuIndex], vgpuTypeInfo) == NV_OK) + *avail_instances = vgpuTypeInfo->maxInstance - pKernelVgpuMgr->pgpuInfo[pgpuIndex].numCreatedVgpu; + } + +exit: + return rmStatus; +} + +#define MAX_STR_LEN 256 +NV_STATUS NV_API_CALL nv_vgpu_get_type_info( + nvidia_stack_t *sp, + nv_state_t *pNv, + NvU32 vgpuTypeId, + char *buffer, + int type_info, + NvU8 devfn +) +{ + THREAD_STATE_NODE threadState; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPU *pGpu = NULL; + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + NV_STATUS rmStatus = NV_OK; + VGPU_TYPE *vgpuTypeInfo; + NvU32 pgpuIndex, i, avail_instances = 0; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + pGpu = NV_GET_NV_PRIV_PGPU(pNv); + if (pGpu == NULL) + { + NV_PRINTF(LEVEL_ERROR, "%s GPU handle is not valid \n", __FUNCTION__); + rmStatus = NV_ERR_INVALID_STATE; + goto exit; + } + + if ((rmStatus = kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pNv->gpu_id, &pgpuIndex)) == + NV_OK) + { + for (i = 0; i < MAX_VGPU_TYPES_PER_PGPU; i++) + { + vgpuTypeInfo = pKernelVgpuMgr->pgpuInfo[pgpuIndex].vgpuTypes[i]; + if (vgpuTypeInfo == NULL) + break; + + if (vgpuTypeInfo->vgpuTypeId != vgpuTypeId) + continue; + + switch (type_info) + { + case VGPU_TYPE_NAME: + os_snprintf(buffer, VGPU_STRING_BUFFER_SIZE, "%s\n", + vgpuTypeInfo->vgpuName); + break; + case VGPU_TYPE_DESCRIPTION: + os_snprintf(buffer, MAX_STR_LEN, + "num_heads=%d, frl_config=%d, " + "framebuffer=%dM, max_resolution=%dx%d, max_instance=%d\n", + vgpuTypeInfo->numHeads, vgpuTypeInfo->frlConfig, + vgpuTypeInfo->profileSize >> 20, + vgpuTypeInfo->maxResolutionX, + vgpuTypeInfo->maxResolutionY, + vgpuTypeInfo->maxInstance); + break; + case VGPU_TYPE_INSTANCES: + rmStatus = get_available_instances(&avail_instances, pNv, + vgpuTypeInfo, + pgpuIndex, devfn); + if (rmStatus != NV_OK) + goto exit; + + os_snprintf(buffer, MAX_STR_LEN, "%d\n", avail_instances); + break; + default: + rmStatus = NV_ERR_INVALID_ARGUMENT; + } + break; + } + } + +exit: + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL nv_vgpu_get_type_ids( + nvidia_stack_t *sp, + nv_state_t *pNv, + NvU32 *numVgpuTypes, + NvU32 *vgpuTypeIds, + NvBool isVirtfn, + NvU8 devfn, + NvBool getCreatableTypes +) +{ + THREAD_STATE_NODE threadState; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + NV_STATUS rmStatus = NV_OK; + NvU32 pgpuIndex, i, avail_instances = 0; + NvU32 numSupportedVgpuTypes = 0; + VGPU_TYPE *vgpuTypeInfo; + void *fp; + + if (!vgpuTypeIds || !numVgpuTypes) + return NV_ERR_INVALID_ARGUMENT; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + if ((rmStatus = kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pNv->gpu_id, &pgpuIndex)) == + NV_OK) + { + if (pKernelVgpuMgr->pgpuInfo[pgpuIndex].sriovEnabled && !isVirtfn) + { + *numVgpuTypes = 0; + } + else + { + numSupportedVgpuTypes = pKernelVgpuMgr->pgpuInfo[pgpuIndex].numVgpuTypes; + *numVgpuTypes = 0; + + for (i = 0; i < numSupportedVgpuTypes; i++) + { + vgpuTypeInfo = pKernelVgpuMgr->pgpuInfo[pgpuIndex].vgpuTypes[i]; + + if (!getCreatableTypes) + { + // Return all available types + vgpuTypeIds[*numVgpuTypes] = vgpuTypeInfo->vgpuTypeId; + (*numVgpuTypes)++; + continue; + } + + rmStatus = get_available_instances(&avail_instances, pNv, + vgpuTypeInfo, pgpuIndex, + devfn); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to get available instances for vGPU ID: %d, status: 0x%x\n", + vgpuTypeInfo->vgpuTypeId, rmStatus); + continue; + } + + if (avail_instances == 0) + continue; + + vgpuTypeIds[*numVgpuTypes] = vgpuTypeInfo->vgpuTypeId; + (*numVgpuTypes)++; + } + } + } + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL nv_vgpu_delete( + nvidia_stack_t *sp, + const NvU8 *pMdevUuid, + NvU16 vgpuId +) +{ + THREAD_STATE_NODE threadState; + void *fp = NULL; + NvU32 rmStatus = NV_OK; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + rmStatus = kvgpumgrDeleteRequestVgpu(pMdevUuid, vgpuId); + // UNLOCK: release API lock + rmapiLockRelease(); + } + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL nv_vgpu_process_vf_info( + nvidia_stack_t *sp, + nv_state_t *pNv, + NvU8 cmd, + NvU32 domain, + NvU8 bus, + NvU8 slot, + NvU8 function, + NvBool isMdevAttached, + void *vf_pci_info +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_OK; + void *fp = NULL; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + rmStatus = kvgpumgrProcessVfInfo(pNv->gpu_id, cmd, domain, bus, slot, function, isMdevAttached, (vgpu_vf_pci_info *) vf_pci_info); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL nv_vgpu_create_request( + nvidia_stack_t *sp, + nv_state_t *pNv, + const NvU8 *pMdevUuid, + NvU32 vgpuTypeId, + NvU16 *vgpuId, + NvU32 gpuPciBdf, + NvBool *is_driver_vm +) +{ + THREAD_STATE_NODE threadState; + OBJSYS *pSys = SYS_GET_INSTANCE(); + void *fp = NULL; + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); + NV_STATUS rmStatus = NV_OK; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + rmStatus = kvgpumgrCreateRequestVgpu(pNv->gpu_id, pMdevUuid, + vgpuTypeId, vgpuId, gpuPciBdf); + + *is_driver_vm = pHypervisor->getProperty(pHypervisor, PDB_PROP_HYPERVISOR_DRIVERVM_ENABLED); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL nv_vgpu_get_bar_info( + nvidia_stack_t *sp, + nv_state_t *pNv, + const NvU8 *pMdevUuid, + NvU64 *size, + NvU32 regionIndex, + void *pVgpuVfioRef +) +{ + REQUEST_VGPU_INFO_NODE *pRequestVgpu = NULL; + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_OK, status; + OBJGPU *pGpu = NULL; + KernelBus *pKernelBus; + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; + void *fp = NULL; + NvU32 value = 0; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr * pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_SILENT, rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR), exit); + + pGpu = NV_GET_NV_PRIV_PGPU(pNv); + if (pGpu == NULL) + { + NV_PRINTF(LEVEL_ERROR, "%s GPU handle is not valid \n", __FUNCTION__); + rmStatus = NV_ERR_INVALID_STATE; + goto release_lock; + } + pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + *size = kbusGetPciBarSize(pKernelBus, regionIndex); + + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_SILENT, + kvgpumgrGetHostVgpuDeviceFromMdevUuid(pNv->gpu_id, + pMdevUuid, + &pKernelHostVgpuDevice), release_lock); + + pRequestVgpu = pKernelHostVgpuDevice->pRequestVgpuInfoNode; + if (pRequestVgpu == NULL) + { + rmStatus = NV_ERR_INVALID_POINTER; + goto release_lock; + } + + pKernelHostVgpuDevice->pVgpuVfioRef = pVgpuVfioRef; + + if (regionIndex == NV_VFIO_PCI_BAR1_REGION_INDEX) + { + VGPU_TYPE *vgpuTypeInfo; + NvU32 pgpuIndex = 0; + NvBool bOverrideBar1Size = NV_FALSE; + + // Read BAR1 length from vgpuTypeInfo + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_SILENT, + kvgpumgrGetVgpuTypeInfo(pKernelHostVgpuDevice->vgpuType, &vgpuTypeInfo), release_lock); + + *size = vgpuTypeInfo->bar1Length << 20; + + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_SILENT, + kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pNv->gpu_id, &pgpuIndex), release_lock); + + /* + * check for 'override_bar1_size' param in vgpuExtraParams list first, + * if param is missing there then check it in vgpu_params list + */ + status = nv_parse_config_params((const char*)vgpuTypeInfo->vgpuExtraParams, + "override_bar1_size", ';', &value); + + if (status == NV_OK && value) { + bOverrideBar1Size = NV_TRUE; + } else if (status == NV_ERR_OBJECT_NOT_FOUND) { + status = nv_parse_config_params(pRequestVgpu->configParams, + "override_bar1_size", ',', &value); + if (status == NV_OK && value) + bOverrideBar1Size = NV_TRUE; + } + if (bOverrideBar1Size) { + NvU64 bar1SizeInBytes, guestBar1; + NvU64 gpuBar1LowerLimit = 256 * 1024 * 1024; // bar1 lower limit for override_bar1_length parameter + + bar1SizeInBytes = kbusGetPciBarSize(pKernelBus, NV_VFIO_PCI_BAR1_REGION_INDEX); + if (pKernelVgpuMgr->pgpuInfo[pgpuIndex].sriovEnabled) + { + *size = pGpu->sriovState.vfBarSize[1]; + } + else if (bar1SizeInBytes > gpuBar1LowerLimit) + { + guestBar1 = bar1SizeInBytes / vgpuTypeInfo->maxInstance; + *size = nvPrevPow2_U64(guestBar1); + } + } + } + else if (regionIndex == NV_VFIO_PCI_BAR2_REGION_INDEX || + regionIndex == NV_VFIO_PCI_BAR3_REGION_INDEX) + { + status = nv_parse_config_params(pRequestVgpu->configParams, + "address64", ',', &value); + + if ((status != NV_OK) || ((status == NV_OK) && (value != 0))) + { + if (regionIndex == NV_VFIO_PCI_BAR2_REGION_INDEX) + *size = 0; + else if (regionIndex == NV_VFIO_PCI_BAR3_REGION_INDEX) + *size = kbusGetPciBarSize(pKernelBus, NV_VFIO_PCI_BAR2_REGION_INDEX); + } + } + +release_lock: + // UNLOCK: release API lock + rmapiLockRelease(); + +exit: + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS osVgpuVfioWake( + void *waitQueue +) +{ + vgpu_vfio_info vgpu_info; + + vgpu_info.waitQueue = waitQueue; + + return os_call_vgpu_vfio((void *) &vgpu_info, CMD_VGPU_VFIO_WAKE_WAIT_QUEUE); +} + +NV_STATUS NV_API_CALL nv_vgpu_start( + nvidia_stack_t *sp, + const NvU8 *pMdevUuid, + void *waitQueue, + NvS32 *returnStatus, + NvU8 *vmName, + NvU32 qemuPid +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_OK; + void *fp = NULL; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + rmStatus = kvgpumgrStart(pMdevUuid, waitQueue, returnStatus, + vmName, qemuPid); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +static NV_STATUS nv_parse_config_params( + const char *config_params, + const char *key, + const char delim, + NvU32 *config_value +) +{ + char *ptr, *configParams = rm_remove_spaces(config_params); + char *token, *value, *name; + NvU32 data; + NV_STATUS rmStatus = NV_ERR_OBJECT_NOT_FOUND; + + ptr = configParams; + while ((token = rm_string_token(&ptr, delim)) != NULL) + { + if (!(name = rm_string_token(&token, '=')) || !os_string_length(name)) + continue; + + if (!(value = rm_string_token(&token, '=')) || !os_string_length(value)) + continue; + + data = os_strtoul(value, NULL, 0); + + if (os_string_compare(name, key) == 0) + { + rmStatus = NV_OK; + *config_value = data; + } + } + + // Free the memory allocated by rm_remove_spaces() + os_free_mem(configParams); + + return rmStatus; +} + +NV_STATUS NV_API_CALL nv_vgpu_get_sparse_mmap( + nvidia_stack_t *sp , + nv_state_t *pNv, + const NvU8 *pMdevUuid, + NvU64 **offsets, + NvU64 **sizes, + NvU32 *numAreas +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_ERR_INVALID_STATE, status; + OBJGPU *pGpu = NULL; + POBJTMR pTmr = NULL; + KernelFifo *pKernelFifo = NULL; + void *fp = NULL; + REQUEST_VGPU_INFO_NODE *pRequestVgpu = NULL; + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; + NvU32 bar0TmrMapSize = 0, bar0FifoMapSize = 0, value = 0; + NvU64 bar0TmrMapOffset = 0, bar0FifoMapOffset = 0; + NvU64 *vfRegionSizes = NULL; + NvU64 *vfRegionOffsets = NULL; + KernelBif *pKernelBif = NULL; + + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + pGpu = NV_GET_NV_PRIV_PGPU(pNv); + + if (pGpu == NULL) + { + rmStatus = NV_ERR_INVALID_STATE; + goto cleanup; + } + pTmr = GPU_GET_TIMER(pGpu); + pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + *numAreas = 0; + rmStatus = kvgpumgrGetHostVgpuDeviceFromMdevUuid(pNv->gpu_id, pMdevUuid, + &pKernelHostVgpuDevice); + if (rmStatus == NV_OK) + { + if (pKernelHostVgpuDevice->gfid != 0) + { + rmStatus = kbifGetNumVFSparseMmapRegions_HAL(pGpu, pKernelBif, pKernelHostVgpuDevice, numAreas); + if (rmStatus == NV_OK) + { + os_alloc_mem((void **)&vfRegionOffsets, sizeof(NvU64) * (*numAreas)); + os_alloc_mem((void **)&vfRegionSizes, sizeof (NvU64) * (*numAreas)); + if (vfRegionOffsets && vfRegionSizes) + { + rmStatus = kbifGetVFSparseMmapRegions_HAL(pGpu, pKernelBif, pKernelHostVgpuDevice, os_page_size, + vfRegionOffsets, vfRegionSizes); + if (rmStatus == NV_OK) + { + *offsets = vfRegionOffsets; + *sizes = vfRegionSizes; + } + } + else + { + if (vfRegionOffsets != NULL) + os_free_mem(vfRegionOffsets); + + if (vfRegionSizes != NULL) + os_free_mem(vfRegionSizes); + + rmStatus = NV_ERR_INSUFFICIENT_RESOURCES; + } + } + } + else + { + pRequestVgpu = pKernelHostVgpuDevice->pRequestVgpuInfoNode; + if (pRequestVgpu == NULL) + { + rmStatus = NV_ERR_INVALID_POINTER; + goto cleanup; + } + + status = nv_parse_config_params(pRequestVgpu->configParams, "direct_gpu_timer_access", ',', &value); + if ((status == NV_OK) && (value != 0)) + { + rmStatus = tmrGetTimerBar0MapInfo_HAL(pGpu, pTmr, + &bar0TmrMapOffset, + &bar0TmrMapSize); + if (rmStatus == NV_OK) + (*numAreas)++; + else + NV_PRINTF(LEVEL_ERROR, + "%s Failed to get NV_PTIMER region \n", + __FUNCTION__); + } + + value = 0; + { + status = kfifoGetUsermodeMapInfo_HAL(pGpu, pKernelFifo, + &bar0FifoMapOffset, + &bar0FifoMapSize); + if (status == NV_OK) + (*numAreas)++; + } + + if (*numAreas != 0) + { + NvU32 i = 0; + NvU64 *tmpOffset, *tmpSize; + os_alloc_mem((void **)offsets, sizeof(NvU64) * (*numAreas)); + os_alloc_mem((void **)sizes, sizeof (NvU64) * (*numAreas)); + + tmpOffset = *offsets; + tmpSize = *sizes; + + if (bar0TmrMapSize != 0) + { + tmpOffset[i] = bar0TmrMapOffset; + tmpSize[i] = bar0TmrMapSize; + i++; + } + + if (bar0FifoMapSize != 0) + { + tmpOffset[i] = bar0FifoMapOffset; + tmpSize[i] = bar0FifoMapSize; + } + } + } + } + +cleanup: + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL nv_vgpu_update_request( + nvidia_stack_t *sp , + const NvU8 *pMdevUuid, + VGPU_DEVICE_STATE deviceState, + NvU64 *offsets, + NvU64 *sizes, + const char *configParams +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_ERR_OBJECT_NOT_FOUND; + void *fp = NULL; + REQUEST_VGPU_INFO_NODE *pRequestVgpu = NULL; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + if (offsets != NULL) + os_free_mem(offsets); + + if (sizes != NULL) + os_free_mem(sizes); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + for (pRequestVgpu = listHead(&pKernelVgpuMgr->listRequestVgpuHead); + pRequestVgpu != NULL; + pRequestVgpu = listNext(&pKernelVgpuMgr->listRequestVgpuHead, pRequestVgpu)) + { + if (portMemCmp(pRequestVgpu->mdevUuid, pMdevUuid, VGPU_UUID_SIZE) == 0) + { + + if (configParams != NULL) + portStringCopy(pRequestVgpu->configParams, + sizeof(pRequestVgpu->configParams), + configParams, (portStringLength(configParams) + 1)); + + pRequestVgpu->deviceState = deviceState; + rmStatus = NV_OK; + } + } + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL nv_gpu_bind_event( + nvidia_stack_t *sp +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_OK; + void *fp = NULL; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + CliAddSystemEvent(NV0000_NOTIFIERS_GPU_BIND_EVENT, 0); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS osVgpuInjectInterrupt(void *vgpuVfioRef) +{ + vgpu_vfio_info vgpu_info; + + vgpu_info.vgpuVfioRef = vgpuVfioRef; + + return os_call_vgpu_vfio((void *) &vgpu_info, CMD_VGPU_VFIO_INJECT_INTERRUPT); +} + +NV_STATUS osVgpuRegisterMdev +( + OS_GPU_INFO *pOsGpuInfo +) +{ + NV_STATUS status = NV_OK; + vgpu_vfio_info vgpu_info; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + KERNEL_PHYS_GPU_INFO *pPhysGpuInfo; + NvU32 pgpuIndex, i; + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); + + status = kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pOsGpuInfo->gpu_id, &pgpuIndex); + if (status != NV_OK) + return status; + + pPhysGpuInfo = &(pKernelVgpuMgr->pgpuInfo[pgpuIndex]); + + vgpu_info.numVgpuTypes = pKernelVgpuMgr->pgpuInfo[pgpuIndex].numVgpuTypes; + + status = os_alloc_mem((void **)&vgpu_info.vgpuTypeIds, + ((vgpu_info.numVgpuTypes) * sizeof(NvU32))); + if (status != NV_OK) + return status; + + vgpu_info.nv = pOsGpuInfo; + for (i = 0; i < pPhysGpuInfo->numVgpuTypes; i++) + { + vgpu_info.vgpuTypeIds[i] = pPhysGpuInfo->vgpuTypes[i]->vgpuTypeId; + } + + if ((!pPhysGpuInfo->sriovEnabled) || + (pHypervisor->getProperty(pHypervisor, PDB_PROP_HYPERVISOR_DRIVERVM_ENABLED))) + { + vgpu_info.is_virtfn = NV_FALSE; + status = os_call_vgpu_vfio((void *)&vgpu_info, CMD_VGPU_VFIO_REGISTER_MDEV); + } + else + { + for (i = 0; i < MAX_VF_COUNT_PER_GPU; i++) + { + if (pPhysGpuInfo->vfPciInfo[i].isNvidiaAttached) + { + vgpu_info.is_virtfn = NV_TRUE; + vgpu_info.domain = pPhysGpuInfo->vfPciInfo[i].domain; + vgpu_info.bus = pPhysGpuInfo->vfPciInfo[i].bus; + vgpu_info.slot = pPhysGpuInfo->vfPciInfo[i].slot; + vgpu_info.function = pPhysGpuInfo->vfPciInfo[i].function; + + status = os_call_vgpu_vfio((void *)&vgpu_info, CMD_VGPU_VFIO_REGISTER_MDEV); + if (status == NV_OK) + { + pPhysGpuInfo->vfPciInfo[i].isMdevAttached = NV_TRUE; + } + } + } + } + + os_free_mem(vgpu_info.vgpuTypeIds); + return status; +} + +NV_STATUS osIsVgpuVfioPresent(void) +{ + vgpu_vfio_info vgpu_info; + + return os_call_vgpu_vfio((void *) &vgpu_info, CMD_VGPU_VFIO_PRESENT); +} + +void initVGXSpecificRegistry(OBJGPU *pGpu) +{ + NvU32 data32; +#if !defined(NVCPU_X86_64) + osWriteRegistryDword(pGpu, NV_REG_STR_RM_BAR2_APERTURE_SIZE_MB, 4); +#endif + osWriteRegistryDword(pGpu, NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR, + NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR_ENABLE); + if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_DUMP_NVLOG, &data32) != NV_OK)) + { + osWriteRegistryDword(pGpu, NV_REG_STR_RM_DUMP_NVLOG, + NV_REG_STR_RM_DUMP_NVLOG_ENABLE); + } + osWriteRegistryDword(pGpu, NV_REG_STR_RM_RC_WATCHDOG, + NV_REG_STR_RM_RC_WATCHDOG_DISABLE); + osWriteRegistryDword(pGpu, NV_REG_STR_CL_FORCE_P2P, + DRF_DEF(_REG_STR, _CL_FORCE_P2P, _READ, _DISABLE) | + DRF_DEF(_REG_STR, _CL_FORCE_P2P, _WRITE, _DISABLE)); +} + + +NV_STATUS rm_is_vgpu_supported_device( + OS_GPU_INFO *pOsGpuInfo, + NvU32 pmc_boot_1 +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + POBJHYPERVISOR pHypervisor = SYS_GET_HYPERVISOR(pSys); + NvBool is_sriov_enabled = FLD_TEST_DRF(_PMC, _BOOT_1, _VGPU, _VF, pmc_boot_1); + + // if not running in vGPU mode (guest VM) return NV_OK + if (!(pHypervisor && pHypervisor->bIsHVMGuest && + (FLD_TEST_DRF(_PMC, _BOOT_1, _VGPU, _PV, pmc_boot_1) || + is_sriov_enabled))) + { + return NV_OK; + } + + return NV_OK; +} diff --git a/userspace/sdks/nv525/nvalloc/unix/src/os.c b/userspace/sdks/nv525/nvalloc/unix/src/os.c new file mode 100644 index 0000000..5f65ba4 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/src/os.c @@ -0,0 +1,5238 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include // NV device driver interface +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "gpu/gpu.h" +#include +#include + +#include "nverror.h" +#include "kernel/gpu/bif/kernel_bif.h" + +#include "gpu/mem_sys/kern_mem_sys.h" + +#include "mem_mgr/io_vaspace.h" +#include +#include "gpu/mem_mgr/mem_desc.h" +#include "core/thread_state.h" +#include +#include +#include +#include +#include "virtualization/hypervisor/hypervisor.h" +#include "rmobjexportimport.h" +#include +#include "rmapi/rs_utils.h" +#include "rmapi/client_resource.h" +#include "os/dce_rm_client_ipc.h" +#include "mem_mgr/mem.h" +#include "gpu/mem_mgr/virt_mem_allocator_common.h" + +#include +#include +#include "gps.h" +#include "jt.h" + + + + +extern const char *ppOsBugCheckBugcodeStr[]; + + +ct_assert(NV_RM_PAGE_SIZE == RM_PAGE_SIZE); +ct_assert(NV_RM_PAGE_MASK == RM_PAGE_MASK); +ct_assert(NV_RM_PAGE_SHIFT == RM_PAGE_SHIFT); + +typedef struct +{ + NvU32 euid; + NvU32 pid; +} TOKEN_USER, *PTOKEN_USER; + +struct OS_RM_CAPS +{ + NvU32 count; + + // This should be the last element + nv_cap_t **caps; +}; + +NvBool osIsRaisedIRQL() +{ + return (!os_semaphore_may_sleep()); +} + +NvBool osIsISR() +{ + return os_is_isr(); +} + +NV_STATUS osGetDriverBlock +( + OS_GPU_INFO *pOsGpuInfo, + OS_DRIVER_BLOCK *pBlock +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS osGetCurrentTick(NvU64 *pTimeInNs) +{ + *pTimeInNs = os_get_current_tick(); + return NV_OK; +} + +NvU64 osGetTickResolution(void) +{ + return os_get_tick_resolution(); +} + +NV_STATUS osGetPerformanceCounter(NvU64 *pTimeInNs) +{ + *pTimeInNs = os_get_current_tick_hr(); + return NV_OK; +} + +NV_STATUS osGetCurrentTime( + NvU32 *pSeconds, + NvU32 *pMicroSeconds +) +{ + return os_get_current_time(pSeconds, pMicroSeconds); +} + +/*! + * @brief Get timestamp for logging. + * + * Everything that logs a time stamp should use this routine for consistency. + * + * The returned value is OS dependent. We want the time stamp to use + * KeQueryPerformanceCounter on Windows so it matches the DirectX timestamps. + * Linux uses microseconds since 1970 (osGetCurrentTime), since matching DirectX + * is not a priority. + * + * osGetTimestampFreq returns the frequency required to decode the time stamps. + * + * @returns system dependent timestamp. + */ +NvU64 osGetTimestamp(void) +{ + NvU32 sec = 0; + NvU32 usec = 0; + osGetCurrentTime(&sec, &usec); + return (NvU64)sec * 1000000 + usec; +} + +/*! + * @brief Get timestamp frequency. + * + * Timestamps are OS dependent. This call returns the frequency + * required to decode them. + * + * @returns Timestamp frequency. For example, 1000000 for MHz. + */ +NvU64 osGetTimestampFreq(void) +{ + return 1000000; +} + +NV_STATUS osDelay(NvU32 milliseconds) +{ + return os_delay(milliseconds); +} + +NV_STATUS osDelayUs(NvU32 microseconds) +{ + return os_delay_us(microseconds); +} + +NV_STATUS osDelayNs(NvU32 nanoseconds) +{ + NvU32 microseconds = NV_MAX(1, (nanoseconds / 1000)); + return os_delay_us(microseconds); +} + +NvU32 osGetCpuFrequency(void) +{ + /* convert os_get_cpu_frequency()'s return value from Hz to MHz */ + return ((NvU32)(os_get_cpu_frequency() / 1000000ULL)); +} + +void* osPciInitHandle( + NvU32 Domain, + NvU8 Bus, + NvU8 Slot, + NvU8 Function, + NvU16 *pVendor, + NvU16 *pDevice +) +{ + // + // Check if the BDF is for a GPU that's already been attached, for which + // we should already have a handle cached. This won't catch devices that + // have been probed but not yet attached, but that shouldn't be a common + // occurrence. + // + // More importantly, having this check here means we don't need to check + // a global list of devices in the kernel interface layer, which could + // have the implication of taking another lock, causing hairy lock + // ordering issues. + // + if (Function == 0) + { + OBJGPU *pGpu = gpumgrGetGpuFromBusInfo(Domain, Bus, Slot); + if (pGpu != NULL) + { + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + if (pVendor) *pVendor = nv->pci_info.vendor_id; + if (pDevice) *pDevice = nv->pci_info.device_id; + return nv->handle; + } + } + + return os_pci_init_handle(Domain, Bus, Slot, Function, pVendor, pDevice); +} + +NvU8 osPciReadByte( + void *pHandle, + NvU32 Offset +) +{ + NvU8 val; + os_pci_read_byte(pHandle, Offset, &val); + return val; +} + +NvU16 osPciReadWord( + void *pHandle, + NvU32 Offset +) +{ + NvU16 val; + os_pci_read_word(pHandle, Offset, &val); + return val; +} + +NvU32 osPciReadDword( + void *pHandle, + NvU32 Offset +) +{ + NvU32 val; + os_pci_read_dword(pHandle, Offset, &val); + return val; +} + +void osPciWriteByte( + void *pHandle, + NvU32 Offset, + NvU8 Value +) +{ + os_pci_write_byte(pHandle, Offset, Value); +} + +void osPciWriteWord( + void *pHandle, + NvU32 Offset, + NvU16 Value +) +{ + os_pci_write_word(pHandle, Offset, Value); +} + +void osPciWriteDword( + void *pHandle, + NvU32 Offset, + NvU32 Value +) +{ + os_pci_write_dword(pHandle, Offset, Value); +} + +void* osMapKernelSpace( + RmPhysAddr Start, + NvU64 Size, + NvU32 Mode, + NvU32 Protect +) +{ + NvU64 offset; + NvU8 *ptr; + + if (0 == Size) + { + NV_ASSERT(Size != 0); + return NULL; + } + + offset = (Start & ~os_page_mask); + Start &= os_page_mask; + Size = ((Size + offset + ~os_page_mask) & os_page_mask); + + ptr = os_map_kernel_space(Start, Size, Mode); + if (ptr != NULL) + return (ptr + offset); + + return NULL; +} + +void osUnmapKernelSpace( + void *pAddress, + NvU64 Size +) +{ + NvU64 offset; + NvUPtr ptr = (NvUPtr)pAddress; + + if (0 == Size) + { + NV_ASSERT(Size != 0); + return; + } + + offset = (ptr & ~os_page_mask); + ptr &= os_page_mask; + Size = ((Size + offset + ~os_page_mask) & os_page_mask); + os_unmap_kernel_space((void *)ptr, Size); +} + +void* osMapIOSpace( + RmPhysAddr Start, + NvU64 Size, + void ** pData, + NvU32 User, + NvU32 Mode, + NvU32 Protect +) +{ + + NvU64 offset; + NvU8 *addr; + + if (0 == Size) + { + NV_ASSERT(Size != 0); + return NULL; + } + + offset = (Start & ~os_page_mask); + Start &= os_page_mask; + Size = ((Size + offset + ~os_page_mask) & os_page_mask); + + if (User) + addr = os_map_user_space(Start, Size, Mode, Protect, pData); + else + addr = os_map_kernel_space(Start, Size, Mode); + if (addr != NULL) + return (addr + offset); + + return addr; +} + +void osUnmapIOSpace( + void *pAddress, + NvU64 Size, + void *pData, + NvU32 User +) +{ + NvU64 offset; + NvUPtr addr = (NvUPtr)pAddress; + + if (0 == Size) + { + NV_ASSERT(Size != 0); + return; + } + + offset = (addr & ~os_page_mask); + addr &= os_page_mask; + Size = ((Size + offset + ~os_page_mask) & os_page_mask); + + if (User) + os_unmap_user_space((void *)addr, Size, pData); + else + os_unmap_kernel_space((void *)addr, Size); +} + +static NV_STATUS setNumaPrivData +( + KernelMemorySystem *pKernelMemorySystem, + nv_state_t *nv, + MEMORY_DESCRIPTOR *pMemDesc +) +{ + NV_STATUS rmStatus = NV_OK; + void *pAllocPrivate = NULL; + NvU64 *addrArray = NULL; + NvU64 numOsPages = pMemDesc->PageCount; + + addrArray = pMemDesc->_pteArray; + + if (NV_RM_PAGE_SIZE < os_page_size) + { + NvU64 numPages; + NvU64 i; + + numPages = pMemDesc->PageCount; + addrArray = portMemAllocNonPaged(numPages * sizeof(NvU64)); + if (addrArray == NULL) + { + return NV_ERR_NO_MEMORY; + } + + portMemCopy((void*)addrArray, + (numPages * sizeof(NvU64)), (void*)pMemDesc->_pteArray, + (numPages * sizeof(NvU64))); + RmDeflateRmToOsPageArray(addrArray, numPages); + numOsPages = NV_RM_PAGES_TO_OS_PAGES(numPages); + + for (i = 0; i < numOsPages; i++) + { + // Update GPA to system physical address + addrArray[i] += pKernelMemorySystem->coherentCpuFbBase; + } + } + + rmStatus = nv_register_phys_pages(nv, addrArray, numOsPages, NV_MEMORY_CACHED, &pAllocPrivate); + if (rmStatus != NV_OK) + { + goto errors; + } + + memdescSetMemData(pMemDesc, pAllocPrivate, NULL); + +errors: + if (NV_RM_PAGE_SIZE < os_page_size) + { + portMemFree(addrArray); + } + + return rmStatus; +} + +NV_STATUS osGetNumMemoryPages +( + MEMORY_DESCRIPTOR *pMemDesc, + NvU32 *pNumPages +) +{ + void *pAllocPrivate = NULL; + + pAllocPrivate = memdescGetMemData(pMemDesc); + if (pAllocPrivate == NULL) + { + NV_PRINTF(LEVEL_ERROR, "pAllocPrivate is NULL!\n"); + return NV_ERR_INVALID_STATE; + } + + return nv_get_num_phys_pages(pAllocPrivate, pNumPages); +} + +NV_STATUS osGetMemoryPages +( + MEMORY_DESCRIPTOR *pMemDesc, + void *pPages, + NvU32 *pNumPages +) +{ + void *pAllocPrivate = NULL; + + pAllocPrivate = memdescGetMemData(pMemDesc); + if (pAllocPrivate == NULL) + { + NV_PRINTF(LEVEL_ERROR, "pAllocPrivate is NULL!\n"); + return NV_ERR_INVALID_STATE; + } + + return nv_get_phys_pages(pAllocPrivate, pPages, pNumPages); +} + +NV_STATUS osMapSystemMemory +( + MEMORY_DESCRIPTOR *pMemDesc, + NvU64 Offset, + NvU64 Length, + NvBool Kernel, + NvU32 Protect, + NvP64 *ppAddress, + NvP64 *ppPrivate +) +{ + OBJGPU *pGpu = pMemDesc->pGpu; + + RmPhysAddr userAddress; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + NV_STATUS rmStatus = NV_OK; + void *pAllocPrivate = NULL; + void *pAddress; + void *pPrivate = NULL; + NvU64 pageIndex; + NvU32 pageOffset; + + if (pGpu != NULL && + pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) && + memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM) + { + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + + rmStatus = setNumaPrivData(pKernelMemorySystem, nv, pMemDesc); + if (rmStatus != NV_OK) + return rmStatus; + } + + *ppAddress = NvP64_NULL; + *ppPrivate = NvP64_NULL; + + if ((Offset + Length) < Length) + return NV_ERR_INVALID_ARGUMENT; + if ((Offset + Length) > pMemDesc->Size) + return NV_ERR_INVALID_ARGUMENT; + + pageIndex = (Offset >> os_page_shift); + pageOffset = (Offset & ~os_page_mask); + + pAllocPrivate = memdescGetMemData(pMemDesc); + if (!pAllocPrivate) + { + NV_PRINTF(LEVEL_ERROR, "pAllocPrivate is NULL!\n"); + return NV_ERR_INVALID_STATE; + } + + if (Kernel) + { + pAddress = nv_alloc_kernel_mapping(nv, pAllocPrivate, + pageIndex, pageOffset, Length, &pPrivate); + if (pAddress == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "failed to create system memory kernel mapping!\n"); + rmStatus = NV_ERR_GENERIC; + } + else + { + *ppAddress = NV_PTR_TO_NvP64(pAddress); + *ppPrivate = NV_PTR_TO_NvP64(pPrivate); + } + } + else + { + rmStatus = nv_alloc_user_mapping(nv, pAllocPrivate, + pageIndex, pageOffset, Length, Protect, &userAddress, + &pPrivate); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "failed to create system memory user mapping!\n"); + } + else + { + *ppAddress = (NvP64)(userAddress); + *ppPrivate = NV_PTR_TO_NvP64(pPrivate); + } + } + + return rmStatus; +} + +void osUnmapSystemMemory +( + MEMORY_DESCRIPTOR *pMemDesc, + NvBool Kernel, + NvU32 ProcessId, + NvP64 pAddress, + NvP64 pPrivate +) +{ + NV_STATUS status; + void *pAllocPrivate = memdescGetMemData(pMemDesc); + OBJGPU *pGpu = pMemDesc->pGpu; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + if (Kernel) + { + status = nv_free_kernel_mapping(nv, pAllocPrivate, NvP64_VALUE(pAddress), + NvP64_VALUE(pPrivate)); + } + else + { + status = nv_free_user_mapping(nv, pAllocPrivate, (NvU64)pAddress, + NvP64_VALUE(pPrivate)); + } + + if (pGpu != NULL && + pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) && + memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM && + pAllocPrivate != NULL) + { + nv_unregister_phys_pages(nv, pAllocPrivate); + memdescSetMemData(pMemDesc, NULL, NULL); + } + + NV_ASSERT(status == NV_OK); +} + +void osIoWriteByte( + NvU32 Address, + NvU8 Value +) +{ + os_io_write_byte(Address, Value); +} + +NvU16 osIoReadWord( + NvU32 Address +) +{ + return os_io_read_word(Address); +} + +void osIoWriteWord( + NvU32 Address, + NvU16 Value +) +{ + os_io_write_word(Address, Value); +} + +NvU8 osIoReadByte( + NvU32 Address +) +{ + return os_io_read_byte(Address); +} + +NvBool osIsAdministrator(void) +{ + return os_is_administrator(); +} + +NvBool osAllowPriorityOverride(void) +{ + return os_allow_priority_override(); +} + +NvU32 osGetCurrentProcess(void) +{ + return os_get_current_process(); +} + +void osGetCurrentProcessName(char *ProcName, NvU32 Length) +{ + return os_get_current_process_name(ProcName, Length); +} + +NV_STATUS osGetCurrentThread(OS_THREAD_HANDLE *pThreadId) +{ + NV_STATUS rmStatus; + NvU64 threadId = 0; + + if (pThreadId == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + rmStatus = os_get_current_thread(&threadId); + if (rmStatus == NV_OK) + { + *pThreadId = threadId; + } + else + { + *pThreadId = 0; + } + + return rmStatus; +} + +NV_STATUS osAttachToProcess(void** ppProcessInfo, NvU32 ProcessId) +{ + // + // This function is used by RmUnmapMemory() to attach to the + // process for which a given device memory mapping was + // created, in order to be able to unmap it. On Linux/UNIX + // platforms, we can't "attach" to a random process, but + // since we don't create/destroy user mappings in the RM, we + // don't need to, either. + // + // Report success to the caller to keep RmUnmapMemory() from + // failing, and memory from being leaked as a result. + // + *ppProcessInfo = NULL; + return NV_OK; +} + +void osDetachFromProcess(void* pProcessInfo) +{ + // stub + return; +} + +NvBool osDbgBreakpointEnabled(void) +{ + return NV_TRUE; +} + +NV_STATUS osAcquireRmSema(void *pSema) +{ + return NV_OK; +} + +NV_STATUS osCondAcquireRmSema(void *pSema) +{ + return NV_OK; +} + +NvU32 osReleaseRmSema(void *pSema, OBJGPU *pDpcGpu) +{ + return NV_SEMA_RELEASE_SUCCEED; +} + +void osSpinLoop(void) +{ + // Enable this code to get debug prints from Libos. +} + +NvU64 osGetMaxUserVa(void) +{ + return os_get_max_user_va(); +} + +NV_STATUS osSchedule(void) +{ + return os_schedule(); +} + +NV_STATUS osQueueWorkItemWithFlags( + OBJGPU *pGpu, + OSWorkItemFunction pFunction, + void *pParams, + NvU32 flags +) +{ + nv_work_item_t *pWi; + nv_state_t *nv; + NV_STATUS status; + + pWi = portMemAllocNonPaged(sizeof(nv_work_item_t)); + + if (NULL == pWi) + { + return NV_ERR_NO_MEMORY; + } + + pWi->flags = NV_WORK_ITEM_FLAGS_REQUIRES_GPU; + if (flags & OS_QUEUE_WORKITEM_FLAGS_DONT_FREE_PARAMS) + pWi->flags |= NV_WORK_ITEM_FLAGS_DONT_FREE_DATA; + + if (flags & OS_QUEUE_WORKITEM_FLAGS_LOCK_SEMA) + pWi->flags |= OS_QUEUE_WORKITEM_FLAGS_LOCK_SEMA; + if (flags & OS_QUEUE_WORKITEM_FLAGS_LOCK_API_RW) + pWi->flags |= OS_QUEUE_WORKITEM_FLAGS_LOCK_API_RW; + if (flags & OS_QUEUE_WORKITEM_FLAGS_LOCK_GPUS_RW) + pWi->flags |= OS_QUEUE_WORKITEM_FLAGS_LOCK_GPUS_RW; + if (flags & OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_DEVICE_RW) + pWi->flags |= OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_DEVICE_RW; + if (flags & OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW) + pWi->flags |= OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW; + + if (flags & OS_QUEUE_WORKITEM_FLAGS_FULL_GPU_SANITY) + pWi->flags |= OS_QUEUE_WORKITEM_FLAGS_FULL_GPU_SANITY; + + pWi->gpuInstance = gpuGetInstance(pGpu); + pWi->func.pGpuFunction = pFunction; + pWi->pData = pParams; + nv = NV_GET_NV_STATE(pGpu); + + status = os_queue_work_item(nv ? nv->queue : NULL, pWi); + + if (NV_OK != status) + { + portMemFree((void *)pWi); + } + + return status; +} + +NV_STATUS osQueueWorkItem( + OBJGPU *pGpu, + OSWorkItemFunction pFunction, + void *pParams +) +{ + return osQueueWorkItemWithFlags(pGpu, pFunction, pParams, OS_QUEUE_WORKITEM_FLAGS_NONE); +} + +NV_STATUS osQueueSystemWorkItem( + OSSystemWorkItemFunction pFunction, + void *pParams +) +{ + nv_work_item_t *pWi; + NV_STATUS status; + + pWi = portMemAllocNonPaged(sizeof(nv_work_item_t)); + + if (NULL == pWi) + { + return NV_ERR_NO_MEMORY; + } + + pWi->flags = NV_WORK_ITEM_FLAGS_NONE; + pWi->func.pSystemFunction = pFunction; + pWi->pData = pParams; + + status = os_queue_work_item(NULL, pWi); + + if (NV_OK != status) + { + portMemFree((void *)pWi); + } + + return status; +} + +void osQueueMMUFaultHandler(OBJGPU *pGpu) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + nv_schedule_uvm_isr(nv); +} + +static inline nv_dma_device_t* osGetDmaDeviceForMemDesc( + OS_GPU_INFO *pOsGpuInfo, + MEMORY_DESCRIPTOR *pMemDesc +) +{ + return (pOsGpuInfo->niso_dma_dev != NULL) && + memdescGetFlag(pMemDesc, MEMDESC_FLAGS_MEMORY_TYPE_DISPLAY_NISO) ? + pOsGpuInfo->niso_dma_dev : pOsGpuInfo->dma_dev; +} + +NV_STATUS osDmaMapPages( + OS_GPU_INFO *pOsGpuInfo, + MEMORY_DESCRIPTOR *pMemDesc +) +{ + return nv_dma_map_pages( + osGetDmaDeviceForMemDesc(pOsGpuInfo, pMemDesc), + NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount), + memdescGetPteArray(pMemDesc, AT_CPU), + memdescGetContiguity(pMemDesc, AT_CPU), + memdescGetCpuCacheAttrib(pMemDesc), + NULL); +} + +NV_STATUS osDmaUnmapPages( + OS_GPU_INFO *pOsGpuInfo, + MEMORY_DESCRIPTOR *pMemDesc +) +{ + return nv_dma_unmap_pages( + pOsGpuInfo->dma_dev, + NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount), + memdescGetPteArray(pMemDesc, AT_CPU), + NULL); +} + +// +// Set the DMA address size for the given GPU +// +// This is a global device setting and care would need to be taken if it was to +// be modified outside of GPU initialization. At least on Linux other drivers, +// like UVM, might be requesting its own DMA mappings for the same GPU after +// the GPU has been initialized. +// +void osDmaSetAddressSize( + OS_GPU_INFO *pOsGpuInfo, + NvU32 bits +) +{ + nv_set_dma_address_size(pOsGpuInfo, bits); +} + +NV_STATUS osAllocPagesInternal( + MEMORY_DESCRIPTOR *pMemDesc +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPU *pGpu = pMemDesc->pGpu; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + void *pMemData = NULL; + NV_STATUS status; + + memdescSetAddress(pMemDesc, NvP64_NULL); + memdescSetMemData(pMemDesc, NULL, NULL); + + NV_ASSERT_OR_RETURN(pMemDesc->PageCount > 0, NV_ERR_INVALID_ARGUMENT); + + if (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_GUEST_ALLOCATED)) + { + if (NV_RM_PAGE_SIZE < os_page_size && + !memdescGetContiguity(pMemDesc, AT_CPU)) + { + RmDeflateRmToOsPageArray(memdescGetPteArray(pMemDesc, AT_CPU), + pMemDesc->PageCount); + } + + status = nv_alias_pages( + NV_GET_NV_STATE(pGpu), + NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount), + memdescGetContiguity(pMemDesc, AT_CPU), + memdescGetCpuCacheAttrib(pMemDesc), + memdescGetGuestId(pMemDesc), + memdescGetPteArray(pMemDesc, AT_CPU), + &pMemData); + } + else + { + NvBool unencrypted = 0; + + if (nv && (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_32BIT_ADDRESSABLE))) + nv->force_dma32_alloc = NV_TRUE; + + status = nv_alloc_pages( + NV_GET_NV_STATE(pGpu), + NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount), + memdescGetContiguity(pMemDesc, AT_CPU), + memdescGetCpuCacheAttrib(pMemDesc), + pSys->getProperty(pSys, + PDB_PROP_SYS_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS), + unencrypted, + memdescGetPteArray(pMemDesc, AT_CPU), + &pMemData); + + if (nv && nv->force_dma32_alloc) + nv->force_dma32_alloc = NV_FALSE; + } + + if (status != NV_OK) + { + return status; + } + + // + // If the OS layer doesn't think in RM page size, we need to inflate the + // PTE array into RM pages. + // + if (NV_RM_PAGE_SIZE < os_page_size && + !memdescGetContiguity(pMemDesc, AT_CPU)) + { + RmInflateOsToRmPageArray(memdescGetPteArray(pMemDesc, AT_CPU), + pMemDesc->PageCount); + } + + memdescSetMemData(pMemDesc, pMemData, NULL); + + return status; +} + +void osFreePagesInternal( + MEMORY_DESCRIPTOR *pMemDesc +) +{ + OBJGPU *pGpu = pMemDesc->pGpu; + NV_STATUS rmStatus; + + if (NV_RM_PAGE_SIZE < os_page_size && + !memdescGetContiguity(pMemDesc, AT_CPU)) + { + RmDeflateRmToOsPageArray(memdescGetPteArray(pMemDesc, AT_CPU), + pMemDesc->PageCount); + } + + rmStatus = nv_free_pages(NV_GET_NV_STATE(pGpu), + NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount), + memdescGetContiguity(pMemDesc, AT_CPU), + memdescGetCpuCacheAttrib(pMemDesc), + memdescGetMemData(pMemDesc)); + NV_ASSERT(rmStatus == NV_OK); +} + +NV_STATUS osLockMem( + MEMORY_DESCRIPTOR *pMemDesc +) +{ + // Not supported on this OS. + DBG_BREAKPOINT(); + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS osUnlockMem( + MEMORY_DESCRIPTOR *pMemDesc +) +{ + // Not supported on this OS. + DBG_BREAKPOINT(); + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS osMapPciMemoryUser( + OS_GPU_INFO *pOsGpuInfo, + RmPhysAddr busAddress, + NvU64 length, + NvU32 Protect, + NvP64 *pVirtualAddress, + NvP64 *pPriv, + NvU32 modeFlag +) +{ + void *addr; + void *priv = NULL; + + addr = osMapIOSpace(busAddress, length, &priv, NV_TRUE, modeFlag, Protect); + + *pPriv = NV_PTR_TO_NvP64(priv); + *pVirtualAddress = NV_PTR_TO_NvP64(addr); + + return (addr != NULL) ? NV_OK : NV_ERR_GENERIC; +} + +void osUnmapPciMemoryUser( + OS_GPU_INFO *pOsGpuInfo, + NvP64 virtualAddress, + NvU64 length, + NvP64 pPriv +) +{ + void *addr, *priv; + + addr = NvP64_VALUE(virtualAddress); + priv = NvP64_VALUE(pPriv); + + osUnmapIOSpace(addr, length, priv, NV_TRUE); +} + +NV_STATUS osMapPciMemoryKernelOld +( + OBJGPU *pGpu, + RmPhysAddr busAddress, + NvU64 length, + NvU32 Protect, + void **pVirtualAddress, + NvU32 modeFlag +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_kern_mapping_t *mapping; + + if (pVirtualAddress == NULL) + return NV_ERR_GENERIC; + + *pVirtualAddress = os_map_kernel_space(busAddress, length, modeFlag); + if (*pVirtualAddress == NULL) + return NV_ERR_GENERIC; + + mapping = portMemAllocNonPaged(sizeof(nv_kern_mapping_t)); + if (NULL == mapping) + { + os_unmap_kernel_space(*pVirtualAddress, length); + *pVirtualAddress = 0; + return NV_ERR_GENERIC; + } + + mapping->addr = *pVirtualAddress; + mapping->size = length; + mapping->modeFlag = modeFlag; + + mapping->next = nv->kern_mappings; + nv->kern_mappings = mapping; + + return NV_OK; +} + +NV_STATUS osMapPciMemoryKernel64 +( + OBJGPU *pGpu, + RmPhysAddr busAddress, + NvU64 length, + NvU32 Protect, + NvP64 *pVirtualAddress, + NvU32 modeFlag +) +{ + void *tmppVirtualAddress = NvP64_VALUE(pVirtualAddress); + NV_STATUS rc; + + rc = osMapPciMemoryKernelOld(pGpu, + busAddress, + length, + Protect, + &tmppVirtualAddress, + modeFlag); + + *pVirtualAddress = NV_PTR_TO_NvP64(tmppVirtualAddress); + + return rc; +} + +void osUnmapPciMemoryKernelOld +( + OBJGPU *pGpu, + void* virtualAddress +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_kern_mapping_t *mapping, *tmp; + + // this can happen, for example, during a call to RmShutdownAdapter() + // from a failed RmInitAdapter() + if (virtualAddress == NULL) + { + return; + } + + tmp = mapping = nv->kern_mappings; + while (mapping) + { + if (mapping->addr == virtualAddress) + { + if (mapping == nv->kern_mappings) + { + nv->kern_mappings = mapping->next; + } + else + { + tmp->next = mapping->next; + } + + os_unmap_kernel_space(mapping->addr, mapping->size); + + portMemFree(mapping); + return; + } + tmp = mapping; + mapping = mapping->next; + } + + DBG_BREAKPOINT(); +} + +void osUnmapPciMemoryKernel64 +( + OBJGPU *pGpu, + NvP64 virtualAddress +) +{ + osUnmapPciMemoryKernelOld(pGpu, NvP64_VALUE(virtualAddress)); +} + +NV_STATUS osMapGPU( + OBJGPU *pGpu, + RS_PRIV_LEVEL privLevel, + NvU64 offset, + NvU64 length, + NvU32 Protect, + NvP64 *pAddress, + NvP64 *pPriv +) +{ + NV_STATUS rmStatus = NV_OK; + + if (privLevel >= RS_PRIV_LEVEL_KERNEL) + { + if (!portSafeAddU64((NvUPtr)pGpu->deviceMappings[0].gpuNvAddr, offset, (NvU64*)pAddress)) + { + rmStatus = NV_ERR_INVALID_LIMIT; + } + } + else + { + RmPhysAddr busAddress; + if (!portSafeAddU64(pGpu->busInfo.gpuPhysAddr, offset, &busAddress)) + { + rmStatus = NV_ERR_INVALID_LIMIT; + } + else + { + rmStatus = osMapPciMemoryUser(pGpu->pOsGpuInfo, + busAddress, + length, + Protect, + pAddress, + pPriv, + NV_FALSE); + } + } + + return rmStatus; +} + +void osUnmapGPU( + OS_GPU_INFO *pOsGpuInfo, + RS_PRIV_LEVEL privLevel, + NvP64 address, + NvU64 length, + NvP64 priv +) +{ + if (privLevel < RS_PRIV_LEVEL_KERNEL) + { + osUnmapPciMemoryUser(pOsGpuInfo, address, length, priv); + } +} + +NV_STATUS osDeviceClassToDeviceName( + NvU32 deviceInstance, + NvU8 *szName +) +{ + return NV_ERR_GENERIC; +} + +static void postEvent( + nv_event_t *event, + NvU32 hEvent, + NvU32 notifyIndex, + NvU32 info32, + NvU16 info16, + NvBool dataValid +) +{ + nv_state_t *nv = nv_get_ctl_state(); + portSyncSpinlockAcquire(nv->event_spinlock); + if (event->active) + nv_post_event(event, hEvent, notifyIndex, + info32, info16, dataValid); + portSyncSpinlockRelease(nv->event_spinlock); +} + +NvU32 osSetEvent +( + OBJGPU *pGpu, + NvP64 eventID +) +{ + nv_event_t *event = NvP64_VALUE(eventID); + postEvent(event, 0, 0, 0, 0, NV_FALSE); + return 1; +} + +NV_STATUS osNotifyEvent( + OBJGPU *pGpu, + PEVENTNOTIFICATION NotifyEvent, + NvU32 Method, + NvU32 Data, + NV_STATUS Status +) +{ + NV_STATUS rmStatus = NV_OK; + + // notify the event + switch (NotifyEvent->NotifyType) + { + case NV01_EVENT_OS_EVENT: + { + nv_event_t *event = NvP64_VALUE(NotifyEvent->Data); + postEvent(event, + NotifyEvent->hEvent, + NotifyEvent->NotifyIndex, + 0, 0, + NotifyEvent->bEventDataRequired); + break; + } + + // NOTE: NV01_EVENT_KERNEL_CALLBACK is deprecated. please use NV01_EVENT_KERNEL_CALLBACK_EX. + case NV01_EVENT_KERNEL_CALLBACK: + { + MINIPORT_CALLBACK callBackToMiniport = + (MINIPORT_CALLBACK)NvP64_VALUE(NotifyEvent->Data); + + // perform a direct callback to the miniport + if (callBackToMiniport) + callBackToMiniport(NV_GET_NV_STATE(pGpu)); + break; + } + + case NV01_EVENT_KERNEL_CALLBACK_EX: + { + NVOS10_EVENT_KERNEL_CALLBACK_EX *kc = (NVOS10_EVENT_KERNEL_CALLBACK_EX *)NvP64_VALUE(NotifyEvent->Data); + + // passes two arguments (arg, params) to the kernel callback instead of one (arg). + if (kc && kc->func) + { + kc->func(kc->arg, NULL, NotifyEvent->hEvent, Data, Status); + } + break; + } + + + default: + { + rmStatus = NV_ERR_GENERIC; + break; + } + } + + return rmStatus; + +} // end of osNotifyEvent() + +// Allow CPL Events to be callback or events +NV_STATUS osEventNotification +( + OBJGPU *pGpu, + PEVENTNOTIFICATION pNotifyEvent, + NvU32 notifyIndex, + void * pEventData, + NvU32 eventDataSize +) +{ + return osEventNotificationWithInfo(pGpu, pNotifyEvent, notifyIndex, 0, 0, + pEventData, eventDataSize); +} + +NV_STATUS osEventNotificationWithInfo +( + OBJGPU *pGpu, + PEVENTNOTIFICATION pNotifyEvent, + NvU32 notifyIndex, + NvU32 info32, + NvU16 info16, + void * pEventData, + NvU32 eventDataSize +) +{ + NV_STATUS rmStatus = NV_OK; + + // walk this object's event list and find any matches for this specific notify + for (; pNotifyEvent; pNotifyEvent = pNotifyEvent->Next) + { + // notifyIndex must match if request isn't for all + if ((notifyIndex != OS_EVENT_NOTIFICATION_INDEX_ALL) && + (pNotifyEvent->NotifyIndex != notifyIndex)) + { + continue; + } + + switch (pNotifyEvent->NotifyType) + { + case NV_EVENT_BUFFER_BIND: + case NV01_EVENT_WIN32_EVENT: + { + nv_event_t *event = NvP64_VALUE(pNotifyEvent->Data); + postEvent(event, + pNotifyEvent->hEvent, + pNotifyEvent->NotifyIndex, + info32, info16, + pNotifyEvent->bEventDataRequired); + break; + } + + // NOTE: NV01_EVENT_KERNEL_CALLBACK is deprecated. please use NV01_EVENT_KERNEL_CALLBACK_EX. + case NV01_EVENT_KERNEL_CALLBACK: + { + MINIPORT_CALLBACK callBackToMiniport = + (MINIPORT_CALLBACK)NvP64_VALUE(pNotifyEvent->Data); + + // perform a direct callback to the miniport + if (callBackToMiniport) + callBackToMiniport(NV_GET_NV_STATE(pGpu)); + break; + } + + case NV01_EVENT_KERNEL_CALLBACK_EX: + { + NVOS10_EVENT_KERNEL_CALLBACK_EX *kc = (NVOS10_EVENT_KERNEL_CALLBACK_EX *)NvP64_VALUE(pNotifyEvent->Data); + + if (kc && kc->func) + { + kc->func(kc->arg, pEventData, pNotifyEvent->hEvent, 0, NV_OK); + } + break; + } + + default: + break; + } + } + + return rmStatus; +} + +// Allow CPL Events to be callback or events +NV_STATUS osObjectEventNotification +( + NvHandle hClient, + NvHandle hObject, + NvU32 hClass, + PEVENTNOTIFICATION pNotifyEvent, + NvU32 notifyIndex, + void *pEventData, + NvU32 eventDataSize +) +{ + NV_STATUS rmStatus = NV_OK; + + NV_PRINTF(LEVEL_INFO, "%s()\n", __FUNCTION__); + // walk this object's event list and find any matches for this specific notify + for (; pNotifyEvent; pNotifyEvent = pNotifyEvent->Next) + { + // notifyIndex must match if request isn't for all + if ((notifyIndex != OS_EVENT_NOTIFICATION_INDEX_ALL) && + (pNotifyEvent->NotifyIndex != notifyIndex)) + { + continue; + } + + switch (pNotifyEvent->NotifyType) + { + case NV01_EVENT_OS_EVENT: + { + nv_event_t *event = NvP64_VALUE(pNotifyEvent->Data); + postEvent(event, + pNotifyEvent->hEvent, + pNotifyEvent->NotifyIndex, + 0, 0, + pNotifyEvent->bEventDataRequired); + break; + } + + case NV01_EVENT_KERNEL_CALLBACK_EX: + { + NVOS10_EVENT_KERNEL_CALLBACK_EX *kc = (NVOS10_EVENT_KERNEL_CALLBACK_EX *)NvP64_VALUE(pNotifyEvent->Data); + + if (kc && kc->func) + { + kc->func(kc->arg, pEventData, pNotifyEvent->hEvent, 0, NV_OK); + } + break; + } + + default: + break; + } + } + + return rmStatus; +} + +NV_STATUS osReferenceObjectCount(void *pEvent) +{ + nv_state_t *nv = nv_get_ctl_state(); + nv_event_t *event = pEvent; + + portSyncSpinlockAcquire(nv->event_spinlock); + ++event->refcount; + portSyncSpinlockRelease(nv->event_spinlock); + return NV_OK; +} + +NV_STATUS osDereferenceObjectCount(void *pOSEvent) +{ + nv_state_t *nv = nv_get_ctl_state(); + nv_event_t *event = pOSEvent; + + portSyncSpinlockAcquire(nv->event_spinlock); + NV_ASSERT(event->refcount > 0); + --event->refcount; + // If event->refcount == 0 but event->active is true, the client + // has not yet freed the OS event. free_os_event will free its + // memory when they do, or else when the client itself is freed. + if (event->refcount == 0 && !event->active) + portMemFree(event); + portSyncSpinlockRelease(nv->event_spinlock); + + return NV_OK; +} + +NV_STATUS osUserHandleToKernelPtr(NvHandle hClient, NvP64 hEvent, NvP64 *pEvent) +{ + nv_state_t *nv = nv_get_ctl_state(); + NvU32 fd = (NvU64)hEvent; + NV_STATUS result; + + portSyncSpinlockAcquire(nv->event_spinlock); + nv_event_t *e = nv->event_list; + while (e != NULL) + { + if (e->fd == fd && e->hParent == hClient) + break; + e = e->next; + } + + if (e != NULL) + { + ++e->refcount; + *pEvent = NV_PTR_TO_NvP64(e); + result = NV_OK; + } + else + result = NV_ERR_OBJECT_NOT_FOUND; + portSyncSpinlockRelease(nv->event_spinlock); + + return result; +} + +NV_STATUS osFlushCpuCache(void) +{ + return os_flush_cpu_cache_all(); +} + +void osFlushCpuWriteCombineBuffer(void) +{ + os_flush_cpu_write_combine_buffer(); +} + + +// +// Evict GPU memory range from the CPU caches. +// +// On some platforms (e.g. P9+V100), the CPU can coherently cache GPU memory +// and RM takes advantage of that. Most everything is handled transparently, +// but there are two exceptions that require explicitly flushing any CPU cache +// lines of GPU memory. These are: +// +// 1) Flushing memory backing ACR regions before they get locked. +// +// Otherwise the cache could get flushed while the regions are locked causing a +// region violation physical fault. See more details in +// acrFlushRegionsFromGpuCoherentCpuCache_IMPL(). +// +// 2) Flushing all of FB before GPU reset (NVLink going down) +// +// Leaving cache entries on the CPU causes fatal errors when the CPU tries +// flushing them later while the link is down. See more details in +// nvlinkStatePostUnload_IMPL(). +// +void osFlushGpuCoherentCpuCacheRange +( + OS_GPU_INFO *pOsGpuInfo, + NvU64 cpuVirtual, + NvU64 size +) +{ + nv_flush_coherent_cpu_cache_range(pOsGpuInfo, cpuVirtual, size); +} + +void osErrorLogV(OBJGPU *pGpu, NvU32 num, const char * pFormat, va_list arglist) +{ + NV_STATUS rmStatus; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + if ((pFormat == NULL) || (*pFormat == '\0')) + { + return; + } + + rmStatus = nv_log_error(nv, num, pFormat, arglist); + NV_ASSERT(rmStatus == NV_OK); +} + +void osErrorLog(OBJGPU *pGpu, NvU32 num, const char* pFormat, ...) +{ + va_list arglist; + va_start(arglist, pFormat); + osErrorLogV(pGpu, num, pFormat, arglist); + va_end(arglist); +} + +NvU32 +osPollHotkeyState +( + OBJGPU *pGpu +) +{ + return 0; +} + +void osDevWriteReg008( + OBJGPU *pGpu, + DEVICE_MAPPING *pMapping, + NvU32 thisAddress, + NvV8 thisValue +) +{ + if (thisAddress >= pMapping->gpuNvLength) + { + NV_ASSERT(thisAddress < pMapping->gpuNvLength); + return; + } + + NV_PRIV_REG_WR08(pMapping->gpuNvAddr, thisAddress, thisValue); +} + +void osDevWriteReg016( + OBJGPU *pGpu, + DEVICE_MAPPING *pMapping, + NvU32 thisAddress, + NvV16 thisValue +) +{ + if (thisAddress >= pMapping->gpuNvLength) + { + NV_ASSERT(thisAddress < pMapping->gpuNvLength); + return; + } + + NV_PRIV_REG_WR16(pMapping->gpuNvAddr, thisAddress, thisValue); +} + +void osDevWriteReg032( + OBJGPU *pGpu, + DEVICE_MAPPING *pMapping, + NvU32 thisAddress, + NvV32 thisValue +) +{ + NvBool vgpuHandled = NV_FALSE; + + vgpuDevWriteReg032(pGpu, thisAddress, thisValue, &vgpuHandled); + if (vgpuHandled) + { + return; + } + + if (thisAddress >= pMapping->gpuNvLength) + { + NV_ASSERT(thisAddress < pMapping->gpuNvLength); + return; + } + + NV_PRIV_REG_WR32(pMapping->gpuNvAddr, thisAddress, thisValue); +} + +NvU8 osDevReadReg008( + OBJGPU *pGpu, + DEVICE_MAPPING *pMapping, + NvU32 thisAddress +) +{ + NvU8 retval = 0; + + if (thisAddress >= pMapping->gpuNvLength) + { + NV_ASSERT(thisAddress < pMapping->gpuNvLength); + } + else + retval = NV_PRIV_REG_RD08(pMapping->gpuNvAddr, thisAddress); + + return retval; +} + +NvU16 osDevReadReg016( + OBJGPU *pGpu, + DEVICE_MAPPING *pMapping, + NvU32 thisAddress +) +{ + NvU16 retval = 0; + + if (thisAddress >= pMapping->gpuNvLength) + { + NV_ASSERT(thisAddress < pMapping->gpuNvLength); + } + else + retval = NV_PRIV_REG_RD16(pMapping->gpuNvAddr, thisAddress); + + return retval; +} + +NvU32 osDevReadReg032( + OBJGPU *pGpu, + DEVICE_MAPPING *pMapping, + NvU32 thisAddress +) +{ + NvU32 retval = 0; + NvBool vgpuHandled = NV_FALSE; + + retval = vgpuDevReadReg032(pGpu, thisAddress, &vgpuHandled); + if (vgpuHandled) + { + return retval; + } + + if (thisAddress >= pMapping->gpuNvLength) + { + NV_ASSERT(thisAddress < pMapping->gpuNvLength); + } + else + retval = NV_PRIV_REG_RD32(pMapping->gpuNvAddr, thisAddress); + + return retval; +} + +NV_STATUS osReadRegistryDwordBase( + OBJGPU *pGpu, + const char *regParmStr, + NvU32 *Data +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + return RmReadRegistryDword(nv, regParmStr, Data); +} + +NV_STATUS osWriteRegistryDword( + OBJGPU *pGpu, + const char *regParmStr, + NvU32 Data +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + return RmWriteRegistryDword(nv, regParmStr, Data); +} + +NV_STATUS osReadRegistryBinary( + OBJGPU *pGpu, + const char *regParmStr, + NvU8 *Data, + NvU32 *cbLen +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + return RmReadRegistryBinary(nv, regParmStr, Data, cbLen); +} + +NV_STATUS osWriteRegistryBinary( + OBJGPU *pGpu, + const char *regParmStr, + NvU8 *Data, + NvU32 cbLen +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + return RmWriteRegistryBinary(nv, regParmStr, Data, cbLen); +} + +NV_STATUS osWriteRegistryVolatile( + OBJGPU *pGpu, + const char *regParmStr, + NvU8 *Data, + NvU32 cbLen +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS osReadRegistryVolatile +( + OBJGPU *pGpu, + const char *regParmStr, + NvU8 *Data, + NvU32 cbLen +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS osReadRegistryVolatileSize +( + OBJGPU *pGpu, + const char *regParmStr, + NvU32 *pSize +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS osReadRegistryStringBase( + OBJGPU *pGpu, + const char *regParmStr, + NvU8 *buffer, + NvU32 *pBufferLength +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + return RmReadRegistryString(nv, regParmStr, buffer, pBufferLength); +} + +NV_STATUS osPackageRegistry( + OBJGPU *pGpu, + PACKED_REGISTRY_TABLE *pRegTable, + NvU32 *pSize +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + return RmPackageRegistry(nv, pRegTable, pSize); +} + +NvU32 osGetCpuCount() +{ + return os_get_cpu_count(); // Total number of logical CPUs. +} + +NvU32 osGetCurrentProcessorNumber(void) +{ + return os_get_cpu_number(); +} + +void osGetTimeoutParams(OBJGPU *pGpu, NvU32 *pTimeoutUs, NvU32 *pScale, NvU32 *pFlags) +{ + NvU32 gpuMode = gpuGetMode(pGpu); + + NV_ASSERT((NV_GPU_MODE_GRAPHICS_MODE == gpuMode) || + (NV_GPU_MODE_COMPUTE_MODE == gpuMode)); + + if (hypervisorIsVgxHyper()) + { + // + // 1.8 seconds is chosen because it is 90% of the overall hard limit of 2.0 + // seconds, imposed by WDDM driver rules. + // Currently primary use case of VGX is Windows, so setting 1.8 as default + // + *pTimeoutUs = 1.8 * 1000000; + } + else + { + switch (gpuMode) + { + default: + case NV_GPU_MODE_GRAPHICS_MODE: + *pTimeoutUs = 4 * 1000000; + break; + + case NV_GPU_MODE_COMPUTE_MODE: + *pTimeoutUs = 30 * 1000000; + break; + } + } + + *pFlags = GPU_TIMEOUT_FLAGS_OSTIMER; + + *pScale = 1; + if (IS_EMULATION(pGpu) || IS_SIMULATION(pGpu)) + { + *pScale = 60; // 1s -> 1m + } + return; +} + +void osFlushLog() +{ + // Not implemented +} + +NvU32 osGetSimulationMode(void) +{ + return NV_SIM_MODE_HARDWARE; +} + +NV_STATUS +cliresCtrlCmdOsUnixFlushUserCache_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS *pAddressSpaceParams +) +{ + Memory *pMemory; + MEMORY_DESCRIPTOR *pMemDesc; + NvU64 start, end; + NvBool bInvalidateOnly; + + NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, + memGetByHandle(RES_GET_CLIENT(pRmCliRes), + pAddressSpaceParams->hObject, + &pMemory)); + + pMemDesc = pMemory->pMemDesc; + + if (memdescGetAddressSpace(pMemDesc) != ADDR_SYSMEM) + { + NV_PRINTF(LEVEL_ERROR, "%s: wrong address space %d\n", + __FUNCTION__, memdescGetAddressSpace(pMemDesc)); + return NV_ERR_INVALID_COMMAND; + } + + if (memdescGetCpuCacheAttrib(pMemDesc) != NV_MEMORY_CACHED) + { + NV_PRINTF(LEVEL_ERROR, "%s: wrong caching type %d\n", + __FUNCTION__, memdescGetCpuCacheAttrib(pMemDesc)); + return NV_ERR_INVALID_COMMAND; + } + + start = pAddressSpaceParams->offset; + end = start + pAddressSpaceParams->length; + + switch(pAddressSpaceParams->cacheOps) + { + case NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH_INVALIDATE: + case NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH: + bInvalidateOnly = NV_FALSE; + break; + + case NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_INVALIDATE: + bInvalidateOnly = NV_TRUE; + break; + + default: + NV_PRINTF(LEVEL_ERROR, "%s: cacheOps not specified\n", __FUNCTION__); + return NV_ERR_INVALID_COMMAND; + } + + if ((end - start) > pMemory->Length) + { + NV_PRINTF(LEVEL_ERROR, + "%s: end address 0x%llx exceeded buffer length: 0x%llx\n", + __FUNCTION__, end, pMemory->Length); + return NV_ERR_INVALID_LIMIT; + } + + if (bInvalidateOnly) + { + // + // XXX: this seems fishy - I'm not sure if invalidating by the kernel + // VA only as nv_dma_cache_invalidate() does here is sufficient for + // this control call. + // pAddressSpaceParams->internalOnly is expected to be the RM client + // VA for this control call; if we wanted to invalidate the user VA we + // could do so using that. + // + // For I/O coherent platforms this won't actually do anything. + // On non-I/O-coherent platforms, there's no need to do a second + // invalidation after the full flush. + // + nv_state_t *nv = NV_GET_NV_STATE(pMemDesc->pGpu); + if (nv->iovaspace_id != NV_IOVA_DOMAIN_NONE) + { + PIOVAMAPPING pIovaMapping = memdescGetIommuMap(pMemDesc, nv->iovaspace_id); + // + // This should only be called for devices that map memory descriptors + // through the nv-dma library, where the memory descriptor data + // contains all the kernel-specific context we need for the + // invalidation. + // + // (These checks match those in osIovaUnmap() leading up to + // nv_dma_unmap_alloc()). + // + if (pIovaMapping == NULL || + pIovaMapping->pOsData == NULL || + memdescGetFlag(pIovaMapping->pPhysMemDesc, MEMDESC_FLAGS_GUEST_ALLOCATED) || + memdescGetFlag(pIovaMapping->pPhysMemDesc, MEMDESC_FLAGS_PEER_IO_MEM)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + nv_dma_cache_invalidate(nv->dma_dev, pIovaMapping->pOsData); + } + else + { + return NV_ERR_INVALID_ARGUMENT; + } + } + else + { + return os_flush_user_cache(); + } + + return NV_OK; +} + +static NV_STATUS +_initializeExportObjectFd +( + nv_file_private_t *nvfp, + NvHandle hClient, + NvHandle hDevice, + NvU16 maxObjects, + NvU8 *metadata +) +{ + NV_STATUS status; + RsResourceRef *pResourceRef; + Device *pDevice; + NvU32 deviceInstance = NV_MAX_DEVICES; + + if (nvfp->handles != NULL) + { + return NV_ERR_STATE_IN_USE; + } + + if (hDevice != 0) + { + status = serverutilGetResourceRef(hClient, hDevice, &pResourceRef); + if (status != NV_OK) + { + return status; + } + + pDevice = dynamicCast(pResourceRef->pResource, Device); + if (pDevice == NULL) + { + return NV_ERR_INVALID_PARAMETER; + } + + deviceInstance = pDevice->deviceInst; + } + + NV_ASSERT_OK_OR_RETURN(os_alloc_mem((void **)&nvfp->handles, + sizeof(nvfp->handles[0]) * maxObjects)); + + os_mem_set(nvfp->handles, 0, + sizeof(nvfp->handles[0]) * maxObjects); + + nvfp->maxHandles = maxObjects; + nvfp->deviceInstance = deviceInstance; + + if (metadata != NULL) + { + os_mem_copy(nvfp->metadata, metadata, sizeof(nvfp->metadata)); + } + + return NV_OK; +} + +NV_STATUS +cliresCtrlCmdOsUnixExportObjectToFd_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS *pParams +) +{ + NvHandle hClient = RES_GET_CLIENT_HANDLE(pRmCliRes); + RmObjExportHandle hExportHandle = 0; + nv_file_private_t *nvfp = NULL; + void *priv = NULL; + NV_STATUS status = NV_OK; + + /* + * This flag is intended to be implemented entirely in the rmapi library in + * userspace, we should never encounter it here. + */ + if (FLD_TEST_DRF(0000_CTRL, _OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS, + _EMPTY_FD, _TRUE, pParams->flags)) + { + return NV_ERR_INVALID_PARAMETER; + } + + if (pParams->object.type != NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM || + pParams->fd == -1) + { + return NV_ERR_INVALID_PARAMETER; + } + + status = RmExportObject(hClient, + pParams->object.data.rmObject.hObject, + &hExportHandle, NULL); + if (status != NV_OK) + { + goto done; + } + NV_ASSERT(hExportHandle != 0); + + nvfp = nv_get_file_private(pParams->fd, NV_TRUE, &priv); + if (nvfp == NULL) + { + NV_ASSERT(priv == NULL); + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + + status = _initializeExportObjectFd(nvfp, hClient, + pParams->object.data.rmObject.hDevice, + 1, NULL); + if (status != NV_OK) + { + goto done; + } + + nvfp->handles[0] = hExportHandle; + +done: + + if (status != NV_OK && hExportHandle != 0) + { + RmFreeObjExportHandle(hExportHandle); + } + + if (priv != NULL) + { + nv_put_file_private(priv); + } + + return status; +} + +// This control call has been deprecated. It will be deleted soon. +NV_STATUS +cliresCtrlCmdOsUnixCreateExportObjectFd_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS *pParams +) +{ + NV_STATUS status; + NvHandle hClient = RES_GET_CLIENT_HANDLE(pRmCliRes); + nv_file_private_t *nvfp = NULL; + void *priv = NULL; + + ct_assert(sizeof(nvfp->metadata) == sizeof(pParams->metadata)); + + if (pParams->maxObjects == 0) + { + return NV_ERR_INVALID_PARAMETER; + } + + nvfp = nv_get_file_private(pParams->fd, NV_TRUE, &priv); + if (nvfp == NULL) + { + NV_ASSERT(priv == NULL); + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + + status = _initializeExportObjectFd(nvfp, hClient, pParams->hDevice, + pParams->maxObjects, pParams->metadata); + +done: + if (priv != NULL) + { + nv_put_file_private(priv); + } + + return status; +} + +NV_STATUS +cliresCtrlCmdOsUnixExportObjectsToFd_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS *pParams +) +{ + NvHandle hClient = RES_GET_CLIENT_HANDLE(pRmCliRes); + RmObjExportHandle *pExportHandle; + nv_file_private_t *nvfp = NULL; + void *priv = NULL; + NV_STATUS status = NV_OK; + NvU32 i; + NvU32 deviceInstance; + NvU32 result; + NvHandle *exportHandles = NULL; + NvBool bFdSetup = NV_FALSE; + + nvfp = nv_get_file_private(pParams->fd, NV_TRUE, &priv); + if (nvfp == NULL) + { + NV_ASSERT(priv == NULL); + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + + ct_assert(sizeof(nvfp->metadata) == sizeof(pParams->metadata)); + + /* Setup export FD if not done */ + if (nvfp->handles == NULL) + { + if (pParams->maxObjects == 0) + { + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + + status = _initializeExportObjectFd(nvfp, hClient, pParams->hDevice, + pParams->maxObjects, + pParams->metadata); + if (status != NV_OK) + { + goto done; + } + + bFdSetup = NV_TRUE; + } + + if ((nvfp->handles == NULL) || + (pParams->numObjects > + NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_MAX_OBJECTS)) + { + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + + if (!portSafeAddU32(pParams->numObjects, pParams->index, &result) || + (result > nvfp->maxHandles)) + { + status = NV_ERR_OUT_OF_RANGE; + goto done; + } + + status = os_alloc_mem((void **)&exportHandles, + sizeof(exportHandles[0]) * + pParams->numObjects); + if (status != NV_OK) + { + goto done; + } + + for (i = 0; i < pParams->numObjects; i++) + { + exportHandles[i] = 0; + + if (pParams->objects[i] == 0) + { + continue; + } + + status = RmExportObject(hClient, + pParams->objects[i], + &exportHandles[i], + &deviceInstance); + if (status != NV_OK) + { + goto done; + } + + NV_ASSERT(exportHandles[i] != 0); + + if (deviceInstance != nvfp->deviceInstance) + { + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + } + + for (i = 0; i < pParams->numObjects; i++) + { + pExportHandle = &nvfp->handles[i + pParams->index]; + + // If the handle already exists in this position, free it + if (*pExportHandle != 0) + { + RmFreeObjExportHandle(*pExportHandle); + *pExportHandle = 0; + } + + *pExportHandle = exportHandles[i]; + } + +done: + + if ((status != NV_OK) && (exportHandles != NULL)) + { + for (i = 0; i < pParams->numObjects; i++) + { + if (exportHandles[i] != 0) + { + RmFreeObjExportHandle(exportHandles[i]); + } + } + } + + if (exportHandles != NULL) + { + os_free_mem(exportHandles); + } + + if ((status != NV_OK) && bFdSetup) + { + os_free_mem(nvfp->handles); + nvfp->handles = NULL; + nvfp->maxHandles = 0; + } + + if (priv != NULL) + { + nv_put_file_private(priv); + } + + return status; +} + +NV_STATUS +cliresCtrlCmdOsUnixImportObjectFromFd_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS *pParams +) +{ + NvHandle hClient = RES_GET_CLIENT_HANDLE(pRmCliRes); + nv_file_private_t *nvfp = NULL; + void *priv = NULL; + NV_STATUS status = NV_OK; + + if (pParams->object.type != NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM || + pParams->fd == -1) + { + return NV_ERR_INVALID_PARAMETER; + } + + nvfp = nv_get_file_private(pParams->fd, NV_TRUE, &priv); + if (nvfp == NULL) + { + NV_ASSERT(priv == NULL); + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + + if ((nvfp->handles == NULL) || (nvfp->handles[0] == 0) || + (nvfp->maxHandles > 1)) + { + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + + status = RmImportObject(hClient, + pParams->object.data.rmObject.hParent, + &pParams->object.data.rmObject.hObject, + nvfp->handles[0], NULL); + +done: + if (priv != NULL) + { + nv_put_file_private(priv); + } + + return status; +} + +NV_STATUS +cliresCtrlCmdOsUnixImportObjectsFromFd_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS *pParams +) +{ + NvHandle hClient = RES_GET_CLIENT_HANDLE(pRmCliRes); + nv_file_private_t *nvfp = NULL; + void *priv = NULL; + NV_STATUS status = NV_OK; + NvU32 i = 0; + RmObjExportHandle hImportHandle; + NvU32 result; + RM_API *pRmApi; + + nvfp = nv_get_file_private(pParams->fd, NV_TRUE, &priv); + if (nvfp == NULL) + { + NV_ASSERT(priv == NULL); + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + + if ((nvfp->handles == NULL) || + (pParams->numObjects > + NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS)) + { + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + + if (!portSafeAddU32(pParams->numObjects, pParams->index, &result) || + (result > nvfp->maxHandles)) + { + status = NV_ERR_OUT_OF_RANGE; + goto done; + } + + for (i = 0; i < pParams->numObjects; i++) + { + hImportHandle = nvfp->handles[i + pParams->index]; + + /* Nothing to import, just continue */ + if (hImportHandle == 0) + { + pParams->objectTypes[i] = \ + NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_NONE; + continue; + } + + status = RmImportObject(hClient, + pParams->hParent, + &pParams->objects[i], + hImportHandle, + &pParams->objectTypes[i]); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "%s: Unable to import handle (%x, %x, %x)\n", + __FUNCTION__, pParams->hParent, pParams->objects[i], hImportHandle); + goto done; + } + } + +done: + + if (status != NV_OK) + { + pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); + while (i > 0) + { + i--; + + if (pParams->objects[i] != 0) + { + pRmApi->Free(pRmApi, hClient, pParams->objects[i]); + } + } + } + + if (priv != NULL) + { + nv_put_file_private(priv); + } + + return status; +} + +NV_STATUS +cliresCtrlCmdOsUnixGetExportObjectInfo_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS *pParams +) +{ + nv_file_private_t *nvfp = NULL; + void *priv = NULL; + NV_STATUS status = NV_OK; + + if (pParams->fd < 0) + { + return NV_ERR_INVALID_PARAMETER; + } + + nvfp = nv_get_file_private(pParams->fd, NV_TRUE, &priv); + if (nvfp == NULL) + { + NV_ASSERT(priv == NULL); + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + + if (nvfp->handles == NULL) + { + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + + pParams->maxObjects = nvfp->maxHandles; + pParams->deviceInstance = nvfp->deviceInstance; + os_mem_copy(pParams->metadata, nvfp->metadata, sizeof(nvfp->metadata)); + +done: + if (priv != NULL) + { + nv_put_file_private(priv); + } + + return status; +} + +/*! + * osAcpiDsm + * + * @brief Handles os specific _DSM method function calls. + * + * Input parameters: + * @param[in] pGpu : OBJGPU pointer + * @param[in] acpiDsmFunction : ACPI DSM function + * @param[in] acpiDsmSubFunction : ACPI DSM subfunction + * @param[in/out] pInOut : in/out buffer, caller should make sure the buffer is large enough. + * @param[in] pSize : when input, size of data that the caller wants to read, in bytes. + * when output, size of valid data in pInOuta in bytes. + */ +NV_STATUS osCallACPI_DSM +( + OBJGPU *pGpu, + ACPI_DSM_FUNCTION acpiDsmFunction, + NvU32 acpiDsmSubFunction, + NvU32 *pInOut, + NvU16 *pSize +) +{ + NV_STATUS status; + NvU8 *pAcpiDsmGuid = NULL; + NvU32 acpiDsmRev; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvU16 acpiDsmInArgSize = 4; + NvBool acpiNvpcfDsmFunction = NV_FALSE; + + // do any handling/remapping of guid needed. + status = checkDsmCall(pGpu, + (ACPI_DSM_FUNCTION *) &acpiDsmFunction, + &acpiDsmSubFunction, + pInOut, + pSize); + + // return if subfunction is not supported or we're returning cache data + if (status != NV_WARN_MORE_PROCESSING_REQUIRED) + { + return status; + } + + switch ((NvU32) acpiDsmFunction) + { + case ACPI_DSM_FUNCTION_NBSI: + pAcpiDsmGuid = (NvU8 *) &NBSI_DSM_GUID; + acpiDsmRev = NBSI_REVISION_ID; + break; + case ACPI_DSM_FUNCTION_NVHG: + pAcpiDsmGuid = (NvU8 *) &NVHG_DSM_GUID; + acpiDsmRev = NVHG_REVISION_ID; + break; + case ACPI_DSM_FUNCTION_MXM: + pAcpiDsmGuid = (NvU8 *) &DSM_MXM_GUID; + acpiDsmRev = ACPI_MXM_REVISION_ID; + break; + case ACPI_DSM_FUNCTION_NBCI: + pAcpiDsmGuid = (NvU8 *) &NBCI_DSM_GUID; + acpiDsmRev = NBCI_REVISION_ID; + break; + case ACPI_DSM_FUNCTION_NVOP: + pAcpiDsmGuid = (NvU8 *) &NVOP_DSM_GUID; + acpiDsmRev = NVOP_REVISION_ID; + break; + case ACPI_DSM_FUNCTION_PCFG: + pAcpiDsmGuid = (NvU8 *) &PCFG_DSM_GUID; + acpiDsmRev = PCFG_REVISION_ID; + break; + case ACPI_DSM_FUNCTION_PEX: + pAcpiDsmGuid = (NvU8 *) &PEX_DSM_GUID; + acpiDsmRev = PEX_REVISION_ID; + if (acpiDsmSubFunction == PEX_FUNC_SETLTRLATENCY) + { + acpiDsmInArgSize = (3 + *pSize); + } + break; + case (ACPI_DSM_FUNCTION_JT): + pAcpiDsmGuid = (NvU8 *) &JT_DSM_GUID; + acpiDsmRev = JT_REVISION_ID; + break; + case ACPI_DSM_FUNCTION_NVPCF: + { + pAcpiDsmGuid = (NvU8 *)&NVPCF_ACPI_DSM_GUID; + acpiDsmRev = NVPCF_ACPI_DSM_REVISION_ID; + acpiDsmInArgSize = (*pSize); + acpiNvpcfDsmFunction = NV_TRUE; + break; + } + case ACPI_DSM_FUNCTION_NVPCF_2X: + pAcpiDsmGuid = (NvU8 *)&NVPCF_ACPI_DSM_GUID; + acpiDsmRev = NVPCF_2X_ACPI_DSM_REVISION_ID; + acpiDsmInArgSize = (*pSize); + if (!nv->nvpcf_dsm_in_gpu_scope) + { + acpiNvpcfDsmFunction = NV_TRUE; + } + break; + + default: + return NV_ERR_NOT_SUPPORTED; + break; + } + + status = nv_acpi_dsm_method(nv, + pAcpiDsmGuid, + acpiDsmRev, + acpiNvpcfDsmFunction, + acpiDsmSubFunction, + pInOut, + acpiDsmInArgSize, + NULL, + pInOut, + pSize); + + if (status == NV_OK) + { + if (acpiDsmSubFunction == NV_ACPI_ALL_FUNC_SUPPORT) + { + // if handling get supported functions list... cache it for later calls + cacheDsmSupportedFunction(pGpu, acpiDsmFunction, acpiDsmSubFunction, pInOut, *pSize); + } + } + else if (nvp->b_mobile_config_enabled) + { + NV_PRINTF(LEVEL_ERROR, + "osCallACPI_DSM: Error during 0x%x DSM subfunction 0x%x! status=0x%x\n", + acpiDsmFunction, acpiDsmSubFunction, status); + } + + return status; +} + +NV_STATUS osCallACPI_DOD +( + OBJGPU *pGpu, + NvU32 *pOut, + NvU32 *pSize +) +{ + NV_STATUS rmStatus; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + if ((pOut == NULL) || (pSize == NULL)) + { + return NV_ERR_INVALID_POINTER; + } + + rmStatus = nv_acpi_dod_method(nv, pOut, pSize); + + return rmStatus; +} + +// +// osAcpiDdc +// +// Handles os specific _DDC method function calls. _DDC is to get EDID from SBIOS. +// +NV_STATUS osCallACPI_DDC +( + OBJGPU *pGpu, + NvU32 ulAcpiId, + NvU8 *pOutData, + NvU32 *pOutSize, + NvBool bReadMultiBlock +) +{ + NV_STATUS rmStatus; + + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + if ((pOutData == NULL) || (pOutSize == NULL)) + { + return NV_ERR_INVALID_POINTER; + } + + portMemSet(pOutData, 0, *pOutSize); + + rmStatus = nv_acpi_ddc_method(nv, pOutData, pOutSize, bReadMultiBlock); + + return rmStatus; +} + +// osCallACPI_NVHG_ROM +// Making ACPI Call into SBIOS with ROM method to get display device's ROM data. +// +NV_STATUS osCallACPI_NVHG_ROM +( + OBJGPU *pGpu, + NvU32 *pInData, + NvU32 *pOutData +) +{ + NV_STATUS rmStatus; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + if ((pOutData == NULL) || (pInData == NULL)) + { + return NV_ERR_INVALID_POINTER; + } + + if (pInData[1] > ROM_METHOD_MAX_RETURN_BUFFER_SIZE) + { + return NV_ERR_INVALID_ARGUMENT; + } + + rmStatus = nv_acpi_rom_method(nv, pInData, pOutData); + + return rmStatus; +} + +void osInitSystemStaticConfig(SYS_STATIC_CONFIG *pConfig) +{ + pConfig->bIsNotebook = rm_is_system_notebook(); + pConfig->osType = nv_get_os_type(); + pConfig->osSevStatus = os_sev_status; + pConfig->bOsSevEnabled = os_sev_enabled; +} + +NvU32 osApiLockAcquireConfigureFlags(NvU32 flags) +{ + return flags; +} + +NV_STATUS osGpuLocksQueueRelease(OBJGPU *pGpu, NvU32 dpcGpuLocksRelease) +{ + return NV_SEMA_RELEASE_FAILED; +} + +void osSyncWithRmDestroy() +{ +} + +void osSyncWithGpuDestroy(NvBool bEntry) +{ +} + +void osModifyGpuSwStatePersistence +( + OS_GPU_INFO *pOsGpuInfo, + NvBool bEnable +) +{ + if (bEnable) + { + pOsGpuInfo->flags |= NV_FLAG_PERSISTENT_SW_STATE; + } + else + { + pOsGpuInfo->flags &= ~NV_FLAG_PERSISTENT_SW_STATE; + } +} + +NV_STATUS +osSystemGetBatteryDrain(NvS32 *pChargeRate) +{ + NV_PRINTF(LEVEL_WARNING, "%s: Platform not supported!\n", __FUNCTION__); + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +osPexRecoveryCallback +( + OS_GPU_INFO *pOsGpuInfo, + OS_PEX_RECOVERY_STATUS Status +) +{ + NV_ASSERT_FAILED("Not supported"); + return NV_ERR_NOT_SUPPORTED; +} + +// +//osCallACPI_MXDS +// +//Handles OS specific MXDS function call. +// +NV_STATUS osCallACPI_MXDS +( + OBJGPU *pGpu, + NvU32 acpiId, + NvU32 *pInOut +) +{ + NV_STATUS rmStatus; + + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + if (pInOut == NULL) + { + return NV_ERR_INVALID_POINTER; + } + + rmStatus = nv_acpi_mux_method(nv, pInOut, acpiId, "MXDS"); + + return rmStatus; +} + +// +//osCallACPI_MXDM +// +//Handles OS specific MXDM function call. +// +NV_STATUS osCallACPI_MXDM +( + OBJGPU *pGpu, + NvU32 acpiId, + NvU32 *pInOut +) +{ + NV_STATUS rmStatus; + + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + if (pInOut == NULL) + { + return NV_ERR_INVALID_POINTER; + } + + rmStatus = nv_acpi_mux_method(nv, pInOut, acpiId, "MXDM"); + + return rmStatus; +} + +#include "lib/protobuf/prb.h" +#include "lib/protobuf/prb_util.h" +#include "g_nvdebug_pb.h" + +NV_STATUS osGetVersionDump(void * pVoid) +{ + PRB_ENCODER * pPrbEnc = (PRB_ENCODER *)pVoid; + NV_STATUS rmStatus; + os_version_info * pOsVersionInfo = NULL; + const char NV_UNKNOWN_BUILD_VERSION[] = "Unknown build version"; + const char NV_UNKNOWN_BUILD_DATE[] = "Unknown build date"; + + NV_ASSERT_OK_OR_RETURN(os_alloc_mem((void**)&pOsVersionInfo, + sizeof(os_version_info))); + portMemSet(pOsVersionInfo, 0, sizeof(os_version_info)); + + prbEncAddUInt32(pPrbEnc, + NVDEBUG_SYSTEMINFO_OSINFO_FAMILY, + NVDEBUG_OS_UNIX); + + rmStatus = os_get_version_info(pOsVersionInfo); + if (rmStatus != NV_OK) + { + goto cleanup; + } + + prbEncAddUInt32(pPrbEnc, + NVDEBUG_SYSTEMINFO_OSINFO_OSMAJORVERSION, + pOsVersionInfo->os_major_version); + + prbEncAddUInt32(pPrbEnc, + NVDEBUG_SYSTEMINFO_OSINFO_OSMINORVERSION, + pOsVersionInfo->os_minor_version); + + prbEncAddUInt32(pPrbEnc, + NVDEBUG_SYSTEMINFO_OSINFO_OSBLDNUM, + pOsVersionInfo->os_build_number); + + if (NULL == pOsVersionInfo->os_build_version_str) + { + pOsVersionInfo->os_build_version_str = NV_UNKNOWN_BUILD_VERSION; + } + + prbEncAddString(pPrbEnc, + NVDEBUG_SYSTEMINFO_OSINFO_BUILDVERSION, + pOsVersionInfo->os_build_version_str); + + if (NULL == pOsVersionInfo->os_build_date_plus_str) + { + pOsVersionInfo->os_build_date_plus_str = NV_UNKNOWN_BUILD_DATE; + } + + prbEncAddString(pPrbEnc, + NVDEBUG_SYSTEMINFO_OSINFO_BUILDDATEPLUS, + pOsVersionInfo->os_build_date_plus_str); + +cleanup: + os_free_mem(pOsVersionInfo); + return rmStatus; +} + +NV_STATUS osGetVersion(NvU32 *majorVer, NvU32 *minorVer, NvU32 *buildNum, NvU16 *unusedPatchVersion, NvU16 *unusedProductType) +{ + os_version_info osVersionInfo; + NV_STATUS rmStatus; + + portMemSet(&osVersionInfo, 0, sizeof(osVersionInfo)); + + rmStatus = os_get_version_info(&osVersionInfo); + if (rmStatus == NV_OK) + { + if (majorVer) + *majorVer = osVersionInfo.os_major_version; + if (minorVer) + *minorVer = osVersionInfo.os_minor_version; + if (buildNum) + *buildNum = osVersionInfo.os_build_number; + } + + return rmStatus; +} + +NV_STATUS +osGetSystemCpuLogicalCoreCounts +( + NvU32 *pCpuCoreCount +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +osGetSystemCpuC0AndAPerfCounters +( + NvU32 coreIndex, + POS_CPU_CORE_PERF_COUNTERS pCpuPerfData +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +void +osEnableCpuPerformanceCounters +( + OBJOS *pOS +) +{ + NV_ASSERT_FAILED("Not supported"); + return; +} + +NV_STATUS +osCpuDpcObjInit +( + void **ppCpuDpcObj, + OBJGPU *pGpu, + NvU32 coreCount +) +{ + NV_ASSERT_FAILED("Not supported"); + return NV_ERR_NOT_SUPPORTED; +} + +void +osCpuDpcObjQueue +( + void **ppCpuDpcObj, + NvU32 coreCount, + POS_CPU_CORE_PERF_COUNTERS pCpuPerfData +) +{ + NV_ASSERT_FAILED("Not supported"); +} + +void +osCpuDpcObjFree +( + void **ppCpuDpcObj +) +{ + NV_ASSERT_FAILED("Not supported"); +} + +NV_STATUS +osGetCarveoutInfo +( + NvU64 *pAddr, + NvU64 *pSize +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +osGetVPRInfo +( + NvU64 *pAddr, + NvU64 *pSize +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +osAllocInVPR +( + MEMORY_DESCRIPTOR *pMemDesc +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +osGetGenCarveout +( + NvU64 *pAddr, + NvU64 *pSize, + NvU32 id, + NvU64 align +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +osI2CClosePorts +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 numPorts +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +osI2CTransfer +( + OBJGPU *pGpu, + NvU32 Port, + NvU8 Address, + nv_i2c_msg_t *nv_i2c_msgs, + NvU32 count +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +osTegraI2CGetBusState +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 port, + NvS32 *scl, + NvS32 *sda +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +osReadI2CBufferDirect +( + OBJGPU *pGpu, + NvU32 Port, + NvU8 Address, + void *pOutputBuffer, + NvU32 OutputSize, + void *pInputBuffer, + NvU32 InputSize +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +osWriteI2CBufferDirect +( + OBJGPU *pGpu, + NvU32 Port, + NvU8 Address, + void *pOutputBuffer0, + NvU32 OutputSize0, + void *pOutputBuffer1, + NvU32 OutputSize1 +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +osGC6PowerControl +( + OBJGPU *pGpu, + NvU32 cmd, + NvU32 *pOut +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NvBool osTestPcieExtendedConfigAccess(void *handle, NvU32 offset) +{ + OBJGPU *pGpu; + KernelBif *pKernelBif; + NvU32 nvXveId = 0; + NvU32 nvXveVccapHdr = 0; + NvU32 pciStart = 0; + NvU32 pcieStart = 0; + + static NvBool retryAllowed = NV_TRUE; + static NvBool configAccess = NV_FALSE; + + // + // Return early for offset within PCI space + // and does not requires extended config space access + // + if (offset < 0x100) + { + return NV_TRUE; + } + + if (!retryAllowed) + { + return configAccess; + } + + pGpu = gpumgrGetSomeGpu(); + if (pGpu == NULL) + { + return configAccess; + } + + retryAllowed = NV_FALSE; + + pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + if (pKernelBif == NULL || kbifGetBusIntfType_HAL(pKernelBif) != + NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS) + { + return configAccess; + } + + // Now verify PCI and PCIe config start registers. + kbifGetPcieConfigAccessTestRegisters_HAL(pGpu, pKernelBif, &pciStart, &pcieStart); + os_pci_read_dword(handle, pciStart, &nvXveId); + os_pci_read_dword(handle, pcieStart, &nvXveVccapHdr); + + if (NV_OK == kbifVerifyPcieConfigAccessTestRegisters_HAL(pGpu, + pKernelBif, + nvXveId, + nvXveVccapHdr)) + { + configAccess = NV_TRUE; + } + + return configAccess; +} + +/*! + * @brief Map memory into an IOVA space according to the given mapping info. + * + * @param[in] pIovaMapping IOVA mapping info + * + * @return NV_ERR_NOT_SUPPORTED + */ +NV_STATUS +osIovaMap +( + PIOVAMAPPING pIovaMapping +) +{ + OBJGPU *pGpu; + nv_state_t *nv, *peer; + NV_STATUS status; + RmPhysAddr base; + NvBool bIsBar0; + PMEMORY_DESCRIPTOR pRootMemDesc; + NvBool bIsFbOffset = NV_FALSE; + NvBool bIsIndirectPeerMapping = NV_FALSE; + NvBool bIsContig; + NV_ADDRESS_SPACE addressSpace; + NvU32 osPageCount; + + if (pIovaMapping == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + pGpu = gpumgrGetGpuFromId(pIovaMapping->iovaspaceId); + if (pGpu == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + pRootMemDesc = memdescGetRootMemDesc(pIovaMapping->pPhysMemDesc, NULL); + addressSpace = memdescGetAddressSpace(pIovaMapping->pPhysMemDesc); + if (gpumgrCheckIndirectPeer(pGpu, pRootMemDesc->pGpu) && + (addressSpace == ADDR_FBMEM)) + { + bIsIndirectPeerMapping = NV_TRUE; + } + + if ((addressSpace != ADDR_SYSMEM) && !bIsIndirectPeerMapping) + { + NV_PRINTF(LEVEL_INFO, + "%s passed memory descriptor in an unsupported address space (%s)\n", + __FUNCTION__, + memdescGetApertureString(memdescGetAddressSpace(pIovaMapping->pPhysMemDesc))); + return NV_ERR_NOT_SUPPORTED; + } + + // + // For guest-allocated memory, we don't actually want to do any remapping, + // since the physical address is already the DMA address to be used by the + // GPU. + // + if (memdescGetFlag(pIovaMapping->pPhysMemDesc, MEMDESC_FLAGS_GUEST_ALLOCATED)) + { + return NV_OK; + } + + nv = NV_GET_NV_STATE(pGpu); + + // + // Intercept peer IO type memory. These are contiguous allocations, so no + // need to adjust pages. + // + if (memdescGetFlag(pIovaMapping->pPhysMemDesc, MEMDESC_FLAGS_PEER_IO_MEM)) + { + NV_ASSERT(memdescGetContiguity(pIovaMapping->pPhysMemDesc, AT_CPU)); + + status = nv_dma_map_mmio(nv->dma_dev, + NV_RM_PAGES_TO_OS_PAGES(pIovaMapping->pPhysMemDesc->PageCount), + &pIovaMapping->iovaArray[0]); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s: failed to map peer IO mem (status = 0x%x)\n", + __FUNCTION__, status); + } + + return status; + } + + // + // We need to check against the "root" GPU, e.g., the GPU that owns this + // allocation. If we're trying to map one of its BARs for a peer, we need + // to handle it differently because it wouldn't have gone through our system + // memory page allocation paths, obviously, and wouldn't have alloc private + // data associated with it. + // + peer = NV_GET_NV_STATE(pRootMemDesc->pGpu); + bIsContig = memdescGetContiguity(pIovaMapping->pPhysMemDesc, AT_CPU); + if (NV_RM_PAGE_SIZE < os_page_size && !bIsContig) + { + RmDeflateRmToOsPageArray(&pIovaMapping->iovaArray[0], + pIovaMapping->pPhysMemDesc->PageCount); + } + + base = memdescGetPhysAddr(pIovaMapping->pPhysMemDesc, AT_CPU, 0); + bIsBar0 = IS_REG_OFFSET(peer, base, pIovaMapping->pPhysMemDesc->Size); + + bIsFbOffset = IS_FB_OFFSET(peer, base, pIovaMapping->pPhysMemDesc->Size); + + // + // For indirect peers bIsFbOffset should be NV_TRUE + // TODO:IS_FB_OFFSET macro is currently broken for P9 systems + // Bug 2010857 tracks fixing this + // +#if defined(NVCPU_PPC64LE) + KernelMemorySystem *pRootKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pRootMemDesc->pGpu); + if (bIsIndirectPeerMapping) + { + NvU64 atsBase = base + pRootKernelMemorySystem->coherentCpuFbBase; + if ((atsBase >= pRootKernelMemorySystem->coherentCpuFbBase) && + (atsBase + pIovaMapping->pPhysMemDesc->Size <= + pRootKernelMemorySystem->coherentCpuFbEnd)) + { + bIsFbOffset = NV_TRUE; + } + else + { + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_STATE); + } + } +#endif + + void *pPriv = memdescGetMemData(pIovaMapping->pPhysMemDesc); + osPageCount = NV_RM_PAGES_TO_OS_PAGES(pIovaMapping->pPhysMemDesc->PageCount); + + if (!bIsBar0 && !bIsFbOffset) + { + if (pPriv == NULL) + { + return NV_ERR_INVALID_STATE; + } + } + else if(bIsIndirectPeerMapping) + { + NV_ASSERT(!bIsBar0 && bIsFbOffset); + // + // TODO: Align onlined GPU memory allocation paths with system memory allocation + // That way pMemDesc->pMemData is setup correctly when we try to create mapping + // to onlined memory of indirect peer. After that we can also get rid of some + // extra code in nv_dma_map_alloc. See bug 190324 for details + // + + status = memdescGetNvLinkGpa(pRootMemDesc->pGpu, (bIsContig ? 1 : osPageCount), + &pIovaMapping->iovaArray[0]); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "%s Failed to get SPA\n", __FUNCTION__); + return status; + } + } + + if (!bIsBar0 && (!bIsFbOffset || bIsIndirectPeerMapping)) + { + status = nv_dma_map_alloc( + osGetDmaDeviceForMemDesc(nv, pIovaMapping->pPhysMemDesc), + osPageCount, + &pIovaMapping->iovaArray[0], + bIsContig, &pPriv); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s: failed to map allocation (status = 0x%x)\n", + __FUNCTION__, status); + return status; + } + + pIovaMapping->pOsData = pPriv; + } + else if (peer != nv) + { + status = nv_dma_map_peer(nv->dma_dev, peer->dma_dev, bIsBar0 ? 0 : 1, + osPageCount, &pIovaMapping->iovaArray[0]); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_INFO, + "%s: failed to map peer (base = 0x%llx, status = 0x%x)\n", + __FUNCTION__, base, status); + return status; + } + + // + // pOsData must be NULL to distinguish a peer DMA mapping from a + // system memory mapping in osIovaUnmap(), so make sure to set it + // accordingly here. + // + pIovaMapping->pOsData = NULL; + } + else + { + NV_PRINTF(LEVEL_INFO, "cannot map a GPU's BAR to itself\n"); + return NV_ERR_NOT_SUPPORTED; + } + + // + // If the OS layer doesn't think in RM page size, we need to inflate the + // PTE array into RM pages. + // + if (NV_RM_PAGE_SIZE < os_page_size && !bIsContig) + { + RmInflateOsToRmPageArray(&pIovaMapping->iovaArray[0], + pIovaMapping->pPhysMemDesc->PageCount); + } + + return NV_OK; +} + +/*! + * @brief Unmap memory from an IOVA space according to the given mapping info. + * + * This mapping info must have been previously mapped by osIovaMap(). + * + * @param[in] pIovaMapping IOVA mapping info + * + */ +void +osIovaUnmap +( + PIOVAMAPPING pIovaMapping +) +{ + OBJGPU *pGpu; + nv_state_t *nv; + void *pPriv; + NV_STATUS status; + + if (pIovaMapping == NULL) + { + return; + } + + pGpu = gpumgrGetGpuFromId(pIovaMapping->iovaspaceId); + if (pGpu == NULL) + { + return; + } + + // + // For guest-allocated memory, we never actually remapped the memory, so we + // shouldn't try to unmap it here. + // + if (memdescGetFlag(pIovaMapping->pPhysMemDesc, MEMDESC_FLAGS_GUEST_ALLOCATED)) + { + return; + } + + nv = NV_GET_NV_STATE(pGpu); + + if (memdescGetFlag(pIovaMapping->pPhysMemDesc, MEMDESC_FLAGS_PEER_IO_MEM)) + { + nv_dma_unmap_mmio(nv->dma_dev, + NV_RM_PAGES_TO_OS_PAGES(pIovaMapping->pPhysMemDesc->PageCount), + pIovaMapping->iovaArray[0]); + + return; + } + + // + // TODO: Formalize the interface with the OS layers so we can use a common + // definition of OS_IOVA_MAPPING_DATA. + // + pPriv = (void *)pIovaMapping->pOsData; + + if (NV_RM_PAGE_SIZE < os_page_size && + !memdescGetContiguity(pIovaMapping->pPhysMemDesc, AT_CPU)) + { + RmDeflateRmToOsPageArray(&pIovaMapping->iovaArray[0], + pIovaMapping->pPhysMemDesc->PageCount); + } + + if (pPriv != NULL) + { + status = nv_dma_unmap_alloc(nv->dma_dev, + NV_RM_PAGES_TO_OS_PAGES(pIovaMapping->pPhysMemDesc->PageCount), + &pIovaMapping->iovaArray[0], &pPriv); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s: failed to unmap allocation (status = 0x%x)\n", + __FUNCTION__, status); + } + } + else + { + nv_dma_unmap_peer(nv->dma_dev, + NV_RM_PAGES_TO_OS_PAGES(pIovaMapping->pPhysMemDesc->PageCount), + pIovaMapping->iovaArray[0]); + } + + // + // If the OS layer doesn't think in RM page size, we need to fluff out the + // PTE array into RM pages. + // + if (NV_RM_PAGE_SIZE < os_page_size && + !memdescGetContiguity(pIovaMapping->pPhysMemDesc, AT_CPU)) + { + RmInflateOsToRmPageArray(&pIovaMapping->iovaArray[0], + pIovaMapping->pPhysMemDesc->PageCount); + } + + pIovaMapping->pOsData = NULL; +} + +/*! + * @brief Set the GPU Rail Voltage in Tegra SoC. Currently not supported + * + * @param[in] pGpu GPU object pointer + * @param[in] reqVoltageuV Rail Voltage requested in uV + * @param[out] pSetVoltageuV Rail Voltage set in uV + * + * @return NV_ERR_NOT_SUPPORTED + */ +NV_STATUS +osSetGpuRailVoltage +( + OBJGPU *pGpu, + NvU32 reqVoltageuV, + NvU32 *pSetVoltageuV +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +/*! + * @brief Get the GPU Rail Voltage in Tegra SoC. Currently not supported + * + * @param[in] pGpu GPU object pointer + * @param[out] voltageuV Rail Voltage in uV + * + * @return NV_ERR_NOT_SUPPORTED + */ +NV_STATUS +osGetGpuRailVoltage +( + OBJGPU *pGpu, + NvU32 *pVoltageuV +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +/*! + * @brief Bring down system in a controlled manner on known error conditions. + * + * @bugCode[in] Error code / reason. + */ +void osBugCheck(NvU32 bugCode) +{ + if (bugCode > OS_BUG_CHECK_BUGCODE_LAST) + { + bugCode = OS_BUG_CHECK_BUGCODE_UNKNOWN; + } + + os_bug_check(bugCode, ppOsBugCheckBugcodeStr[bugCode]); +} + +/*! + * @brief Perform an action at assertion failure. + */ +void osAssertFailed(void) +{ + os_dump_stack(); +} + +/*! + * @brief Get the GPU Chip Info - Speedo and IDDQ values + * + * + * @param[in] pGpu GPU object pointer + * @param[out] pGpuSpeedoHv Pointer to GPU Speedo value at high voltage corner. + * @param[out] pGpuSpeedoLv Pointer to GPU Speedo value at low voltage corner. + * @param[out] pGpuIddq Pointer to GPU Iddq Value + * @param[out] pChipSkuId SKU ID for the chip + * + * @return NV_ERR_NOT_SUPPORTED + */ +NV_STATUS +osGetChipInfo +( + OBJGPU *pGpu, + NvU32 *pGpuSpeedoHv, + NvU32 *pGpuSpeedoLv, + NvU32 *pGpuIddq, + NvU32 *pChipSkuId +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +/* + * @brief Get the GPU Rail Voltage Info (i.e. Min, Max and StepSize) in Tegra SoC. + * + * @param[in] pGpu GPU object pointer + * @param[out] pMinVoltageuV Minimum Voltage supported on the Rail in Micro Volts + * @param[out] pMaxVoltageuV Maximum Voltage supported on the Rail in Micro Volts + * @param[out] pStepVoltageuV Voltage Step-size supported on the Rail in Micro Volts + * + * @return NV_ERR_NOT_SUPPORTED + */ +NV_STATUS +osGetGpuRailVoltageInfo +( + OBJGPU *pGpu, + NvU32 *pMinVoltageuV, + NvU32 *pMaxVoltageuV, + NvU32 *pStepVoltageuV +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +/*! + * @brief Get the current opaque security token. + * + * For Linux the security token is the effective UID of a process and process ID + * + * Note: This function allocates memory for the token. The onus is on the calling + * function to free the memory associated with the token once its done with it. + * + * @return pointer to the security token. + */ +PSECURITY_TOKEN +osGetSecurityToken() +{ + NV_STATUS rmStatus; + TOKEN_USER *pTokenUser; + + pTokenUser = portMemAllocNonPaged(sizeof(TOKEN_USER)); + if (pTokenUser == NULL) + { + return NULL; + } + rmStatus = os_get_euid(&pTokenUser->euid); + if (rmStatus != NV_OK) + { + portMemFree(pTokenUser); + return NULL; + } + + pTokenUser->pid = os_get_current_process(); + + return (PSECURITY_TOKEN)pTokenUser; +} + +PUID_TOKEN +osGetCurrentUidToken(void) +{ + NV_STATUS rmStatus; + NvU32 *pUidToken; + + pUidToken = portMemAllocNonPaged(sizeof(NvU32)); + if (pUidToken == NULL) + { + return NULL; + } + + rmStatus = os_get_euid(pUidToken); + if (rmStatus != NV_OK) + { + portMemFree(pUidToken); + return NULL; + } + + return (PUID_TOKEN)pUidToken; +} + +/*! + * @brief Interface function to validate the token for the current client + * + * This function takes two tokens as parameters, validates them and checks + * if either the PID or EUID from client database matches the current PID or EUID. + * + * @param[in] pClientSecurityToken security token cached in the client db + * @param[in] pCurrentSecurityToken security token of the current client + * @return NV_OK if the validation is successful + * NV_ERR_INVALID_CLIENT if the tokens do not match + * NV_ERR_INVALID_POINTER if the tokens are invalid + */ +NV_STATUS +osValidateClientTokens +( + PSECURITY_TOKEN pClientSecurityToken, + PSECURITY_TOKEN pCurrentSecurityToken +) +{ + PTOKEN_USER pClientTokenUser = (PTOKEN_USER)pClientSecurityToken; + PTOKEN_USER pCurrentTokenUser = (PTOKEN_USER)pCurrentSecurityToken; + + NV_ASSERT_OR_RETURN((pClientTokenUser != NULL), NV_ERR_INVALID_POINTER); + NV_ASSERT_OR_RETURN((pCurrentTokenUser != NULL), NV_ERR_INVALID_POINTER); + + if ((pClientTokenUser->euid != pCurrentTokenUser->euid) && + (pClientTokenUser->pid != pCurrentTokenUser->pid)) + { + NV_PRINTF(LEVEL_INFO, + "NVRM: %s: Current security token doesn't match the one in the client database. " + "Current EUID: %d, PID: %d; Client DB EUID: %d, PID: %d\n", + __FUNCTION__, pCurrentTokenUser->euid, pCurrentTokenUser->pid, + pClientTokenUser->euid, pClientTokenUser->pid); + return NV_ERR_INVALID_CLIENT; + } + + return NV_OK; +} + +/*! + * @brief Interface function to compare the tokens for two client + * + * This function takes two tokens as parameters, validates them and checks + * if the EUIDs of each token match. + * + * @param[in] pToken1 Token to compare + * @param[in] pToken2 Token to compare + * @return NV_TRUE if the tokens match + * NV_FALSE if the tokens do not match + */ +NvBool +osUidTokensEqual +( + PUID_TOKEN pUidToken1, + PUID_TOKEN pUidToken2 +) +{ + NvU32 * pTokenUser1 = (NvU32*)pUidToken1; + NvU32 * pTokenUser2 = (NvU32*)pUidToken2; + + NV_ASSERT_OR_RETURN((pTokenUser1 != NULL), NV_FALSE); + NV_ASSERT_OR_RETURN((pTokenUser2 != NULL), NV_FALSE); + + if (*pTokenUser1 != *pTokenUser2) + { + return NV_FALSE; + } + + return NV_TRUE; +} + +NvBool +osRemoveGpuSupported +( + void +) +{ + return os_pci_remove_supported(); +} + +/* + * @brief Get the address ranges assigned to local or peer GPUs on a system that + * supports hardware address translation services (ATS) over NVLink/C2C. + * + * @note + * - All address values are in the System Physical Address (SPA) space + * - Targets can either be "Local" (bIsPeer=False) or for a specified "Peer" + * (bIsPeer=True, peerIndex=#) GPU + * - Target address and mask values have a specified bit width, and represent + * the higher order bits above the target address granularity + * + * @param[in] pGpu GPU object pointer + * @param[out] pAddrSysPhys Pointer to hold SPA + * @param[out] pAddrWidth Address range width value pointer + * @param[out] pMask Mask value pointer + * @param[out] pMaskWidth Mask width value pointer + * @param[in] bIsPeer NV_TRUE if this is a peer, local GPU otherwise + * @param[in] peerIndex Peer index + * + * @return NV_OK or NV_ERR_NOT_SUPPORTED + * + * A return value of NV_ERR_NOT_SUPPORTED for the local GPU would + * indicate that the system does not support ATS over NVLink/C2C + */ +NV_STATUS +osGetAtsTargetAddressRange +( + OBJGPU *pGpu, + NvU64 *pAddrSysPhys, + NvU32 *pAddrWidth, + NvU32 *pMask, + NvU32 *pMaskWidth, + NvBool bIsPeer, + NvU32 peerIndex +) +{ +#if RMCFG_MODULE_KERNEL_BIF && RMCFG_MODULE_KERNEL_NVLINK && (defined(NVCPU_PPC64LE) || defined(NVCPU_AARCH64)) + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + nv_state_t *nv; + const int addrMaskWidth = 0x10; + + if (!pKernelNvlink && !pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_IS_C2C_LINK_UP)) + return NV_ERR_INVALID_ARGUMENT; + + nv = NV_GET_NV_STATE(pGpu); + + // + // TODO : Bug 1848958 restricts peer device tree parsing. Return early if + // peer values are requested. This should be fixed by passing correct pGpu + // pointer of the peer GPU retrieved using peerIds. + // + if (bIsPeer) + { + const int addrWidth = 0x10; + + *pAddrSysPhys = 0; + *pAddrWidth = addrWidth; + *pMask = 0; + *pMaskWidth = addrMaskWidth; + return NV_OK; + } + else + { + NV_STATUS status = nv_get_device_memory_config(nv, pAddrSysPhys, NULL, + pAddrWidth, NULL); + if (status == NV_OK) + { + *pMask = NVBIT(*pAddrWidth) - 1U; + *pMaskWidth = addrMaskWidth; + } + return status; + } + + return NV_OK; +#endif + return NV_ERR_NOT_SUPPORTED; +} + +/* + * @brief Get the physical address in CPU address map and NUMA node id + * of the GPU memory. + * + * @note + * - The physical address is System Physical Address (SPA) in baremetal/host + * and Intermediate Physical Address(IPA) or Guest Physical Address(GPA) + * inside a VM. + * + * @param[in] pGpu GPU object pointer + * @param[out] pAddrPhys Pointer to hold the physical address of FB in + * CPU address map + * @param[out] pNodeId NUMA nodeID of respective GPU memory + * + * @return NV_OK or NV_ERR_NOT_SUPPORTED + * + */ +NV_STATUS +osGetFbNumaInfo +( + OBJGPU *pGpu, + NvU64 *pAddrPhys, + NvS32 *pNodeId +) +{ +#if RMCFG_MODULE_KERNEL_BIF && RMCFG_MODULE_KERNEL_NVLINK && (defined(NVCPU_PPC64LE) || defined(NVCPU_AARCH64)) + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + nv_state_t *nv; + + *pNodeId = NV0000_CTRL_NO_NUMA_NODE; + + if (!pKernelNvlink && !pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_IS_C2C_LINK_UP)) + return NV_ERR_INVALID_ARGUMENT; + + nv = NV_GET_NV_STATE(pGpu); + + NV_STATUS status = nv_get_device_memory_config(nv, NULL, pAddrPhys, NULL, pNodeId); + + return status; +#endif + return NV_ERR_NOT_SUPPORTED; +} + + +/* + * @brief Verif only function to get the chiplib overrides for link connection + * state for all C2C links. + * + * If chiplib overrides exist, each link can either be enabled (1) or disabled (0) + * + * @param[in] pGpu GPU object pointer + * @param[in] maxLinks Size of pLinkConnection array + * @param[out] pLinkConnection array of pLinkConnection values to be populated by MODS + * + * @return NV_OK or NV_ERR_NOT_SUPPORTED (no overrides available) + */ +NV_STATUS +osGetForcedC2CConnection +( + OBJGPU *pGpu, + NvU32 maxLinks, + NvU32 *pLinkConnection +) +{ + int i, ret; + NV_STATUS status; + char path[64]; + OBJOS *pOS; + OBJSYS *pSys; + + NV_ASSERT_OR_RETURN((pLinkConnection != NULL), NV_ERR_INVALID_POINTER); + NV_ASSERT_OR_RETURN((maxLinks > 0), NV_ERR_NOT_SUPPORTED); + NV_ASSERT_OR_RETURN((pGpu != NULL), NV_ERR_INVALID_ARGUMENT); + + pSys = SYS_GET_INSTANCE(); + pOS = SYS_GET_OS(pSys); + if (pOS == NULL || pOS->osSimEscapeRead == NULL) + { + NV_PRINTF(LEVEL_ERROR, "%s: escape reads not supported on platform\n", + __FUNCTION__); + return NV_ERR_NOT_SUPPORTED; + } + + for (i = 0; i < maxLinks; i++) + { + ret = os_snprintf(path, sizeof(path), "CPU_MODEL|CM_ATS_ADDRESS|C2C%u", i); + NV_ASSERT((ret > 0) && (ret < (sizeof(path) - 1))); + + status = pOS->osSimEscapeRead(pGpu, path, 0, 4, &pLinkConnection[i]); + if (status == NV_OK) + { + NV_PRINTF(LEVEL_INFO, "%s: %s=0x%X\n", __FUNCTION__, + path, pLinkConnection[i]); + } + else + { + NV_PRINTF(LEVEL_INFO, "%s: osSimEscapeRead for '%s' failed (%u)\n", + __FUNCTION__, path, status); + return NV_ERR_NOT_SUPPORTED; + } + } + return NV_OK; +} + +static NV_STATUS +osGetSmbiosTableInfo +( + const NvU8 *pMappedAddr, + NvU64 *pBaseAddr, + NvU64 *pLength, + NvU64 *pNumSubTypes, + NvU32 *pVersion +) +{ + *pBaseAddr = 0; + *pLength = 0; + *pNumSubTypes = 0; + *pVersion = 0; + + if (portMemCmp(pMappedAddr, "_SM3_", 5) == 0) + { + *pVersion = (pMappedAddr[7] << 8) | pMappedAddr[8]; + portMemCopy(pLength, 4, pMappedAddr + 12, 4); + portMemCopy(pBaseAddr, 8, pMappedAddr + 16, 8); + + *pNumSubTypes = *pLength / 4; + + return NV_OK; + } + + if (portMemCmp(pMappedAddr, "_SM_", 4) == 0) + { + *pVersion = (pMappedAddr[6] << 8) | pMappedAddr[7]; + + pMappedAddr += 16; + + if (portMemCmp(pMappedAddr, "_DMI_", 5) == 0) + { + portMemCopy(pLength, 2, pMappedAddr + 6, 2); + portMemCopy(pBaseAddr, 4, pMappedAddr + 8, 4); + portMemCopy(pNumSubTypes, 2, pMappedAddr + 12, 2); + + if (!*pVersion) + *pVersion = (pMappedAddr[14] & 0xF0) << 4 | + (pMappedAddr[14] & 0x0F); + + return NV_OK; + } + } + + return NV_ERR_INVALID_ADDRESS; +} + + +/* + * @brief Function to export SMBIOS table. Also, maps table in kernel-space. + * + * @param[out] ppBaseVAddr Base virtual address of SMBIOS table. + * @param[out] pLength Size of SMBIOS table. + * @param[out] pNumSubTypes Count of structures (types) embedded in + * the SMBIOS table. + * @param[out] pVersion SMBIOS version + * + * @return NV_OK, NV_ERR_INSUFFICIENT_RESOURCES or NV_ERR_INVALID_ADDRESS + * or errors from OS layer + */ +NV_STATUS +osGetSmbiosTable +( + void **ppBaseVAddr, + NvU64 *pLength, + NvU64 *pNumSubTypes, + NvU32 *pVersion +) +{ + NV_STATUS status = NV_OK; + NvU64 physSmbiosAddr = ~0ull; + void *pMappedAddr = NULL; + NvU64 basePAddr = 0; + + if (!NVCPU_IS_X86_64) + { + return NV_ERR_NOT_SUPPORTED; + } + + status = os_get_smbios_header(&physSmbiosAddr); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_INFO, "%s: Failed query SMBIOS table with error: %x \n", + __FUNCTION__, status); + return status; + } + + NV_ASSERT(physSmbiosAddr != ~0ull); + + pMappedAddr = osMapKernelSpace(physSmbiosAddr, + os_page_size, + NV_MEMORY_CACHED, + NV_PROTECT_READ_WRITE); + if (!pMappedAddr) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + status = osGetSmbiosTableInfo(pMappedAddr, + &basePAddr, + pLength, + pNumSubTypes, + pVersion); + + osUnmapKernelSpace(pMappedAddr, os_page_size); + + if (status != NV_OK) + { + return status; + } + + *ppBaseVAddr = osMapKernelSpace(basePAddr, + *pLength, + NV_MEMORY_CACHED, + NV_PROTECT_READ_WRITE); + if (!*ppBaseVAddr) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + return NV_OK; +} + +/* + * @brief Function to free SMBIOS table mappings + * + * @param[in] pBaseVAddr Base virtual address of SMBIOS table. + * @param[in] length Size of SMBIOS table. + * + */ +void +osPutSmbiosTable +( + void *pBaseVAddr, + NvU64 length +) +{ + osUnmapKernelSpace(pBaseVAddr, length); +} + +NV_STATUS +osGetAcpiRsdpFromUefi +( + NvU32 *pRsdpAddr +) +{ + return os_get_acpi_rsdp_from_uefi(pRsdpAddr); +} + +/* + * @brief Returns NV_TRUE if NvSwitch device is present in the system. + */ +NvBool +osIsNvswitchPresent +( + void +) +{ + return os_is_nvswitch_present(); +} + +/* + * @brief Function to add crashlog buffer entry. + * + * @param[in] pBuffer virt_addr of nvlog buffer + * @param[in] length size of nvlog buffer + */ +void +osAddRecordForCrashLog +( + void *pBuffer, + NvU32 length +) +{ + os_add_record_for_crashLog(pBuffer, length); +} + +/* + * @brief Function to delete crashlog buffer entry. + * + * @param[in] pBuffer virt_addr of nvlog buffer + */ +void +osDeleteRecordForCrashLog +( + void *pBuffer +) +{ + os_delete_record_for_crashLog(pBuffer); +} + +/* + * @brief Queries the sysfs interface to get memblock size + * @param[out] memblock_size Pointer to the memblock_size + */ +NV_STATUS +osNumaMemblockSize +( + NvU64 *memblock_size +) +{ + return os_numa_memblock_size(memblock_size); +} + +NvBool +osNumaOnliningEnabled +( + OS_GPU_INFO *pOsGpuInfo +) +{ + NvS32 numaNodeId = NV0000_CTRL_NO_NUMA_NODE; + + // + // Note that this numaNodeId value fetched from Linux layer might not be + // accurate since it is possible to overwrite it with regkey on some configs + // + if (nv_get_device_memory_config(pOsGpuInfo, NULL, NULL, NULL, + &numaNodeId) != NV_OK) + { + return NV_FALSE; + } + + return (numaNodeId != NV0000_CTRL_NO_NUMA_NODE); +} + +/* + * @brief Function to call NUMA allocation entry. + * + * @param[in] nid NUMA node id + * @param[in] size Allocation size + * @param[in] flag Allocation flags + * @param[out] pAddress Ptr to the allocated physical address + */ +NV_STATUS +osAllocPagesNode +( + NvS32 nid, + NvLength size, + NvU32 flag, + NvU64 *pAddress +) +{ + NV_STATUS status = NV_OK; + NvU32 localFlag = NV_ALLOC_PAGES_NODE_NONE; + + if (pAddress == NULL || nid < 0 || size > NV_U32_MAX) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // Translate the flags + if (flag & OS_ALLOC_PAGES_NODE_SKIP_RECLAIM) + { + localFlag |= NV_ALLOC_PAGES_NODE_SKIP_RECLAIM; + } + + status = os_alloc_pages_node(nid, (NvU32)size, localFlag, pAddress); + return status; +} + +NV_STATUS +osAllocAcquirePage +( + NvU64 pAddress +) +{ + os_get_page(pAddress); + return NV_OK; +} + +NV_STATUS +osAllocReleasePage +( + NvU64 pAddress +) +{ + os_put_page(pAddress); + return NV_OK; +} + +/* + * @brief Function to return refcount on a page + * @param[in] address The physical address of the page + */ +NvU32 +osGetPageRefcount +( + NvU64 pAddress +) +{ + return os_get_page_refcount(pAddress); +} + +/* + * @brief Function to return the number of tail pages if the address is + * referring to a compound page; For non-compound pages, 1 is returned. + * @param[in] address The physical address of the page + */ +NvU32 +osCountTailPages +( + NvU64 pAddress +) +{ + return os_count_tail_pages(pAddress); +} + +/* + * @brief Upon success, gets NPU register address range. + * + * @param[in] pOsGpuInfo OS specific GPU information pointer + * @param[out] pBase base (physical) of NPU register address range + * @param[out] pSize size of NPU register address range + */ +NV_STATUS +osGetIbmnpuGenregInfo +( + OS_GPU_INFO *pOsGpuInfo, + NvU64 *pBase, + NvU64 *pSize +) +{ + return nv_get_ibmnpu_genreg_info(pOsGpuInfo, pBase, pSize, NULL); +} + +/* + * @brief Upon success, gets NPU's relaxed ordering mode. + * + * @param[in] pOsGpuInfo OS specific GPU information pointer + * @param[out] pMode relaxed ordering mode + */ +NV_STATUS +osGetIbmnpuRelaxedOrderingMode +( + OS_GPU_INFO *pOsGpuInfo, + NvBool *pMode +) +{ + return nv_get_ibmnpu_relaxed_ordering_mode(pOsGpuInfo, pMode); +} + +/* + * @brief Waits for NVLink HW flush on an NPU associated with a GPU. + * + * @param[in] pOsGpuInfo OS specific GPU information pointer + */ +void +osWaitForIbmnpuRsync +( + OS_GPU_INFO *pOsGpuInfo +) +{ + nv_wait_for_ibmnpu_rsync(pOsGpuInfo); +} + +NvU32 +osGetPageSize() +{ + return os_page_size; +} + + + +/* + * @brief Opens a new temporary file for reading and writing + * + * @param[in] ppFile void double pointer + * + * @returns NV_STATUS, NV_OK if success, + NV_ERR_GENERIC, if error + NV_ERR_NOT_SUPPORTED, for unsupported platforms + */ +NV_STATUS +osOpenTemporaryFile +( + void **ppFile +) +{ + return os_open_temporary_file(ppFile); +} + +/* + * @brief Closes the specified temporary file + * + * @param[in] pFile Pointer to file + * + * @returns void + */ +void +osCloseFile +( + void *pFile +) +{ + os_close_file(pFile); +} + +/* + * @brief Writes the buffer to the specified file at the given offset + * + * @param[in] pFile Pointer to file (void) + * @param[in] pBuffer Pointer to buffer from which to copy + * @param[in] size Size of the copy + * @parma[in] offset offset in the file + * + * @returns NV_STATUS, NV_OK if success, + NV_ERR_GENERIC, if error + NV_ERR_NOT_SUPPORTED, for unsupported platforms + */ +NV_STATUS +osWriteToFile +( + void *pFile, + NvU8 *pBuffer, + NvU64 size, + NvU64 offset +) +{ + return os_write_file(pFile, pBuffer, size, offset); +} + +/* + * @brief Reads from the specified file at the given offset + * + * @param[in] pFile Pointer to file (void *) + * @param[in] pBuffer Pointer to buffer to which the data is copied + * @param[in] size Size of the copy + * @parma[in] offset offset in the file + * + * @returns NV_STATUS, NV_OK if success, + NV_ERR_GENERIC, if error + NV_ERR_NOT_SUPPORTED, for unsupported platforms + */ +NV_STATUS +osReadFromFile +( + void *pFile, + NvU8 *pBuffer, + NvU64 size, + NvU64 offset +) +{ + return os_read_file(pFile, pBuffer, size, offset); +} + +/* + * @brief Unregisters caps from the capability framework. + * The function assumes that the caps are allocated and stored in the + * hierarchical order. If they aren't, OS (Linux kernel) would warn and + * leak the caps. + * + * @param[in] pOsRmCaps caps of interest + */ +void +osRmCapUnregister +( + OS_RM_CAPS **ppOsRmCaps +) +{ + OS_RM_CAPS *pOsRmCaps = *ppOsRmCaps; + NvS32 i; + + if (pOsRmCaps == NULL) + { + return; + } + + for (i = pOsRmCaps->count - 1; i >= 0; i--) + { + if (pOsRmCaps->caps[i] != NULL) + { + os_nv_cap_destroy_entry(pOsRmCaps->caps[i]); + } + } + + os_free_mem(pOsRmCaps->caps); + os_free_mem(pOsRmCaps); + + *ppOsRmCaps = NULL; +} + +static NV_STATUS +_allocOsRmCaps +( + OS_RM_CAPS **ppOsRmCaps, + NvU32 count +) +{ + NV_STATUS status; + OS_RM_CAPS *pOsRmCaps; + + *ppOsRmCaps = NULL; + + status = os_alloc_mem((void**)&pOsRmCaps, sizeof(OS_RM_CAPS)); + if (status != NV_OK) + return status; + + pOsRmCaps->count = count; + + status = os_alloc_mem((void**)&pOsRmCaps->caps, sizeof(pOsRmCaps->caps[0]) * count); + if (status != NV_OK) + { + os_free_mem(pOsRmCaps); + return status; + } + + os_mem_set(pOsRmCaps->caps, 0, sizeof(pOsRmCaps->caps[0]) * count); + + *ppOsRmCaps = pOsRmCaps; + return NV_OK; +} + +#define OS_RM_CAP_GPU_DIR 0 +#define OS_RM_CAP_GPU_MIG_DIR 1 +#define OS_RM_CAP_GPU_COUNT 2 + +/* + * @brief Registers OBJGPU with the capability framework. + * + * @param[in] pOsGpuInfo OS specific GPU information pointer + * @param[out] ppOsRmCaps GPU OS specific capabilities pointer + */ +NV_STATUS +osRmCapRegisterGpu +( + OS_GPU_INFO *pOsGpuInfo, + OS_RM_CAPS **ppOsRmCaps +) +{ + NvU32 minor = nv_get_dev_minor(pOsGpuInfo); + char name[16]; + NV_STATUS status; + OS_RM_CAPS *pOsRmCaps; + nv_cap_t *parent; + nv_cap_t *cap; + + // Return success on the unsupported platforms. + if (nvidia_caps_root == NULL) + { + return NV_OK; + } + + if (*ppOsRmCaps != NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + status = _allocOsRmCaps(&pOsRmCaps, OS_RM_CAP_GPU_COUNT); + if (status != NV_OK) + return status; + + *ppOsRmCaps = pOsRmCaps; + + os_snprintf(name, sizeof(name), "gpu%u", minor); + name[sizeof(name) - 1] = '\0'; + parent = nvidia_caps_root; + + cap = os_nv_cap_create_dir_entry(parent, name, (OS_RUGO | OS_XUGO)); + if (cap == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to setup gpu%u directory\n", minor); + status = NV_ERR_OPERATING_SYSTEM; + goto failed; + } + + pOsRmCaps->caps[OS_RM_CAP_GPU_DIR] = cap; + parent = cap; + + // TODO: Bug 2679591: Add MIG directory only if SMC is enabled. + // For now, always add "mig" directory. + cap = os_nv_cap_create_dir_entry(parent, "mig", (OS_RUGO | OS_XUGO)); + if (cap == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to setup mig directory\n"); + status = NV_ERR_OPERATING_SYSTEM; + goto failed; + } + + pOsRmCaps->caps[OS_RM_CAP_GPU_MIG_DIR] = cap; + + return NV_OK; + +failed: + osRmCapUnregister(ppOsRmCaps); + + return status; +} + +#define OS_RM_CAP_SMC_PART_DIR 0 +#define OS_RM_CAP_SMC_PART_ACCESS_FILE 1 +#define OS_RM_CAP_SMC_PART_COUNT 2 + +/* + * @brief Registers SMC partition (a.k.a. GPU instance) with the capability + * framework + * + * @param[in] pGpuOsRmCaps GPU OS specific capabilities pointer + * @param[out] ppPartitionOsRmCaps OS specific capabilities pointer for SMC partition + * @param[in] swizzId SMC partition swizz ID + */ +NV_STATUS +osRmCapRegisterSmcPartition +( + OS_RM_CAPS *pGpuOsRmCaps, + OS_RM_CAPS **ppPartitionOsRmCaps, + NvU32 swizzId +) +{ + char name[16]; + NV_STATUS status; + nv_cap_t *parent; + nv_cap_t *cap; + OS_RM_CAPS *pOsRmCaps; + + // Return success as there is nothing to do. + if (pGpuOsRmCaps == NULL) + { + return NV_OK; + } + + if (*ppPartitionOsRmCaps != NULL || swizzId >= NV_U32_MAX) + { + return NV_ERR_INVALID_ARGUMENT; + } + + parent = pGpuOsRmCaps->caps[OS_RM_CAP_GPU_MIG_DIR]; + if (parent == NULL) + { + return NV_ERR_INVALID_STATE; + } + + status = _allocOsRmCaps(&pOsRmCaps, OS_RM_CAP_SMC_PART_COUNT); + if (status != NV_OK) + return status; + + *ppPartitionOsRmCaps = pOsRmCaps; + + os_snprintf(name, sizeof(name), "gi%u", swizzId); + name[sizeof(name) - 1] = '\0'; + + cap = os_nv_cap_create_dir_entry(parent, name, OS_RUGO | OS_XUGO); + if (cap == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to setup gi%u directory\n", + swizzId); + status = NV_ERR_OPERATING_SYSTEM; + goto failed; + } + + pOsRmCaps->caps[OS_RM_CAP_SMC_PART_DIR] = cap; + parent = cap; + + cap = os_nv_cap_create_file_entry(parent, "access", OS_RUGO); + if (cap == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to setup access file for ID:%u\n", + swizzId); + status = NV_ERR_OPERATING_SYSTEM; + goto failed; + } + + pOsRmCaps->caps[OS_RM_CAP_SMC_PART_ACCESS_FILE] = cap; + + return NV_OK; + +failed: + osRmCapUnregister(ppPartitionOsRmCaps); + + return status; +} + +#define OS_RM_CAP_SMC_EXEC_PART_DIR 0 +#define OS_RM_CAP_SMC_EXEC_PART_ACCESS_FILE 1 +#define OS_RM_CAP_SMC_EXEC_PART_COUNT 2 + +/* + * @brief Registers SMC execution partition (a.k.a. compute instance) with the + * capability framework + * + * @param[in] pPartitionOsRmCaps OS specific capabilities pointer for SMC partition + * @param[out] ppExecPartitionOsRmCaps OS specific capabilities pointer for SMC execution partition + * @param[in] execPartitionId SMC execution partition ID + */ +NV_STATUS +osRmCapRegisterSmcExecutionPartition +( + OS_RM_CAPS *pPartitionOsRmCaps, + OS_RM_CAPS **ppExecPartitionOsRmCaps, + NvU32 execPartitionId +) +{ + char name[16]; + NV_STATUS status; + nv_cap_t *parent; + nv_cap_t *cap; + OS_RM_CAPS *pOsRmCaps; + + // Return success as there is nothing to do. + if (pPartitionOsRmCaps == NULL) + { + return NV_OK; + } + + if ((*ppExecPartitionOsRmCaps != NULL) || (execPartitionId >= NV_U32_MAX)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + parent = pPartitionOsRmCaps->caps[OS_RM_CAP_SMC_PART_DIR]; + if (parent == NULL) + { + return NV_ERR_INVALID_STATE; + } + + status = _allocOsRmCaps(&pOsRmCaps, OS_RM_CAP_SMC_EXEC_PART_COUNT); + if (status != NV_OK) + { + return status; + } + + *ppExecPartitionOsRmCaps = pOsRmCaps; + + os_snprintf(name, sizeof(name), "ci%u", execPartitionId); + name[sizeof(name) - 1] = '\0'; + + cap = os_nv_cap_create_dir_entry(parent, name, OS_RUGO | OS_XUGO); + if (cap == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to setup ci%u directory\n", + execPartitionId); + status = NV_ERR_OPERATING_SYSTEM; + goto failed; + } + + pOsRmCaps->caps[OS_RM_CAP_SMC_EXEC_PART_DIR] = cap; + parent = cap; + + cap = os_nv_cap_create_file_entry(parent, "access", OS_RUGO); + if (cap == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to setup access file for ID:%u\n", + execPartitionId); + status = NV_ERR_OPERATING_SYSTEM; + goto failed; + } + + pOsRmCaps->caps[OS_RM_CAP_SMC_EXEC_PART_ACCESS_FILE] = cap; + + return NV_OK; + +failed: + osRmCapUnregister(ppExecPartitionOsRmCaps); + + return status; +} + +/* + * @brief Release the acquired capability + * + * @param[in] dupedCapDescriptor descriptor to be released + */ +void +osRmCapRelease +( + NvU64 dupedCapDescriptor +) +{ + if (dupedCapDescriptor == NV_U64_MAX) + { + return; + } + + os_nv_cap_close_fd((int)dupedCapDescriptor); +} + +#define OS_RM_CAP_SYS_MIG_DIR 0 +#define OS_RM_CAP_SYS_SMC_CONFIG_FILE 1 +#define OS_RM_CAP_SYS_SMC_MONITOR_FILE 2 +#define OS_RM_CAP_SYS_COUNT 3 + +NV_STATUS +osRmCapRegisterSys +( + OS_RM_CAPS **ppOsRmCaps +) +{ + nv_cap_t **ppCaps; + nv_cap_t *parent; + nv_cap_t *cap; + NV_STATUS status; + OS_RM_CAPS *pOsRmCaps; + + if (nvidia_caps_root == NULL) + return NV_ERR_NOT_SUPPORTED; + + status = _allocOsRmCaps(&pOsRmCaps, OS_RM_CAP_SYS_COUNT); + if (status != NV_OK) + return status; + + *ppOsRmCaps = pOsRmCaps; + + ppCaps = pOsRmCaps->caps; + + parent = os_nv_cap_create_dir_entry(nvidia_caps_root, "mig", OS_RUGO | OS_XUGO); + if (parent == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to create mig directory\n"); + status = NV_ERR_OPERATING_SYSTEM; + goto failed; + } + ppCaps[OS_RM_CAP_SYS_MIG_DIR] = parent; + + cap = os_nv_cap_create_file_entry(parent, "config", OS_RUSR); + if (cap == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to create mig config file\n"); + status = NV_ERR_OPERATING_SYSTEM; + goto failed; + } + ppCaps[OS_RM_CAP_SYS_SMC_CONFIG_FILE] = cap; + + cap = os_nv_cap_create_file_entry(parent, "monitor", OS_RUGO); + if (cap == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to create mig monitor file\n"); + status = NV_ERR_OPERATING_SYSTEM; + goto failed; + } + ppCaps[OS_RM_CAP_SYS_SMC_MONITOR_FILE] = cap; + + return NV_OK; + +failed: + osRmCapUnregister(ppOsRmCaps); + return status; +} + +/* + * @brief Acquire the requested capability + * + * @param[in] pOsRmCaps opaque pointer to the caps. + * @param[in] rmCap the capability to be acquired. + * @param[in] capDescriptor descriptor to be used for validation + * @param[out] dupedCapDescriptor returns duplicated descriptor if validation + * is successful + * + * Note: On Linux, duplicating fd is helpful to let administrators know about + * the capability users. See https://linux.die.net/man/8/lsof usage. + */ +NV_STATUS +osRmCapAcquire +( + OS_RM_CAPS *pOsRmCaps, + NvU32 rmCap, + NvU64 capDescriptor, + NvU64 *dupedCapDescriptor +) +{ + nv_cap_t *cap; + int fd = (int)capDescriptor; + int duped_fd; + NvU32 index; + NV_STATUS status; + + *dupedCapDescriptor = NV_U64_MAX; + + switch (rmCap) + { + case NV_RM_CAP_SMC_PARTITION_ACCESS: + { + index = OS_RM_CAP_SMC_PART_ACCESS_FILE; + break; + } + case NV_RM_CAP_EXT_FABRIC_MGMT: + { + status = nv_acquire_fabric_mgmt_cap(fd, &duped_fd); + if (status != NV_OK) + { + return status; + } + + goto done; + } + case NV_RM_CAP_SMC_EXEC_PARTITION_ACCESS: + { + index = OS_RM_CAP_SMC_EXEC_PART_ACCESS_FILE; + break; + } + case NV_RM_CAP_SYS_SMC_CONFIG: + { + index = OS_RM_CAP_SYS_SMC_CONFIG_FILE; + break; + } + case NV_RM_CAP_SYS_SMC_MONITOR: + { + index = OS_RM_CAP_SYS_SMC_MONITOR_FILE; + break; + } + default: + { + return NV_ERR_INVALID_ARGUMENT; + } + } + + if (pOsRmCaps == NULL) + { + return NV_ERR_NOT_SUPPORTED; + } + + if (index >= pOsRmCaps->count) + { + return NV_ERR_INVALID_ARGUMENT; + } + + cap = pOsRmCaps->caps[index]; + + duped_fd = os_nv_cap_validate_and_dup_fd(cap, fd); + if (duped_fd < 0) + { + return NV_ERR_INSUFFICIENT_PERMISSIONS; + } + +done: + *dupedCapDescriptor = duped_fd; + + return NV_OK; +} + +/* + * @brief Initializes capability descriptor + * + * @param[out] pCapDescriptor descriptor to be used + * + */ +void +osRmCapInitDescriptor +( + NvU64 *pCapDescriptor +) +{ + *pCapDescriptor = NV_U64_MAX; +} + +/* + * @brief Generates random bytes which can be used as a universally unique + * identifier. + * + * @param[out] pBytes Array of random bytes + * @param[in] numBytes Size of the array + */ +NV_STATUS +osGetRandomBytes +( + NvU8 *pBytes, + NvU16 numBytes +) +{ + os_get_random_bytes(pBytes, numBytes); + + return NV_OK; +} + +/* + * @brief Allocate wait queue + * + * @param[out] ppWq Wait queue + */ +NV_STATUS +osAllocWaitQueue +( + OS_WAIT_QUEUE **ppWq +) +{ + return os_alloc_wait_queue(ppWq); +} + +/* + * @brief Free wait queue + * + * @param[in] pWq Wait queue + */ +void +osFreeWaitQueue +( + OS_WAIT_QUEUE *pWq +) +{ + os_free_wait_queue(pWq); +} + +/* + * @brief Put thread to uninterruptible sleep + * + * @param[in] pWq Wait queue + */ +void +osWaitUninterruptible +( + OS_WAIT_QUEUE *pWq +) +{ + os_wait_uninterruptible(pWq); +} + +/* + * @brief Put thread to interruptible sleep + * + * @param[in] pWq Wait queue + */ +void +osWaitInterruptible +( + OS_WAIT_QUEUE *pWq +) +{ + os_wait_interruptible(pWq); +} + +/* + * @brief Wake up thread from uninterruptible sleep + * + * @param[in] pWq Wait queue + */ +void +osWakeUp +( + OS_WAIT_QUEUE *pWq +) +{ + os_wake_up(pWq); +} + +NV_STATUS +osReadPFPciConfigInVF +( + NvU32 addr, + NvU32 *data +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +/*! + * @brief Returns IMP-relevant data collected from other modules + * + * This function is basically a wrapper to call the unix/linux layer. + * + * @param[out] pTegraImpImportData Structure to receive the data + * + * @returns NV_OK if successful, + * NV_ERR_BUFFER_TOO_SMALL if the array in TEGRA_IMP_IMPORT_DATA is + * too small, + * NV_ERR_NOT_SUPPORTED if the functionality is not available, or + * other errors as may be returned by subfunctions. + */ +NV_STATUS +osTegraSocGetImpImportData +( + TEGRA_IMP_IMPORT_DATA *pTegraImpImportData +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +/*! + * @brief Tells BPMP whether or not RFL is valid + * + * Display HW generates an ok_to_switch signal which asserts when mempool + * occupancy is high enough to be able to turn off memory long enough to + * execute a dramclk frequency switch without underflowing display output. + * ok_to_switch drives the RFL ("request for latency") signal in the memory + * unit, and the switch sequencer waits for this signal to go active before + * starting a dramclk switch. However, if the signal is not valid (e.g., if + * display HW or SW has not been initialized yet), the switch sequencer ignores + * the signal. This API tells BPMP whether or not the signal is valid. + * + * @param[in] pOsGpuInfo Per GPU Linux state + * @param[in] bEnable True if RFL will be valid; false if invalid + * + * @returns NV_OK if successful, + * NV_ERR_NOT_SUPPORTED if the functionality is not available, or + * NV_ERR_GENERIC if some other kind of error occurred. + */ +NV_STATUS +osTegraSocEnableDisableRfl +( + OS_GPU_INFO *pOsGpuInfo, + NvBool bEnable +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +/*! + * @brief Allocates a specified amount of ISO memory bandwidth for display + * + * floorBandwidthKBPS is the minimum required (i.e., floor) dramclk frequency + * multiplied by the width of the pipe over which the display data will travel. + * (It is understood that the bandwidth calculated by multiplying the clock + * frequency by the pipe width will not be realistically achievable, due to + * overhead in the memory subsystem. The infrastructure will not actually use + * the bandwidth value, except to reverse the calculation to get the required + * dramclk frequency.) + * + * This function is basically a wrapper to call the unix/linux layer. + * + * @param[in] pOsGpuInfo OS specific GPU information pointer + * @param[in] averageBandwidthKBPS Amount of ISO memory bandwidth requested + * @param[in] floorBandwidhtKBPS Min required dramclk freq * pipe width + * + * @returns NV_OK if successful, + * NV_ERR_INSUFFICIENT_RESOURCES if one of the bandwidth values is too + * high, and bandwidth cannot be allocated, + * NV_ERR_NOT_SUPPORTED if the functionality is not available, or + * NV_ERR_GENERIC if some other kind of error occurred. + */ +NV_STATUS +osTegraAllocateDisplayBandwidth +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 averageBandwidthKBPS, + NvU32 floorBandwidthKBPS +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +/*! + * @brief Creates or sets up platform specific nano second resolution timer + * + * @param[in] pOsGpuInfo OS specific GPU information pointer + * @param[in] pTmrEvent Pointer to timer event information + * @param[in/out] pTimer pointer to hold high resolution timer object + */ +NV_STATUS +osCreateNanoTimer +( + OS_GPU_INFO *pOsGpuInfo, + void *pTmrEvent, + void **pTimer +) +{ + nv_create_nano_timer(pOsGpuInfo, pTmrEvent, (nv_nano_timer_t **)pTimer); + return NV_OK; +} + +/*! + * @brief Starts platform specific nano second resolution timer + * + * @param[in] pOsGpuInfo OS specific GPU information pointer + * @param[in] pTimer pointer to high resolution timer object + * @param[in] timens time in nano seconds + */ +NV_STATUS +osStartNanoTimer +( + OS_GPU_INFO *pOsGpuInfo, + void *pTimer, + NvU64 timeNs +) +{ + nv_start_nano_timer(pOsGpuInfo, (nv_nano_timer_t *)pTimer, timeNs); + return NV_OK; +} + +/*! + * @brief Cancels platform specific nano second resolution timer + * + * @param[in] pOsGpuInfo OS specific GPU information pointer + * @param[in] pTimer pointer to timer object + */ +NV_STATUS +osCancelNanoTimer +( + OS_GPU_INFO *pOsGpuInfo, + void *pTimer +) +{ + nv_cancel_nano_timer(pOsGpuInfo, (nv_nano_timer_t *)pTimer); + return NV_OK; +} + +/*! + * @brief Destroys & cancels platform specific nano second resolution timer + * + * + * @param[in] pGpu Device of interest + * @param[in] pTimer pointer to timer object + */ +NV_STATUS +osDestroyNanoTimer +( + OS_GPU_INFO *pOsGpuInfo, + void *pTimer +) +{ + nv_destroy_nano_timer(pOsGpuInfo, (nv_nano_timer_t *)pTimer); + return NV_OK; +} + +/*! + * @brief Get number of dpAux instances. + * It is wrapper function to call unix/linux layer. + * + * @param[in] pGpu GPU object pointer + * @param[out] pNumIntances Number of dpAux instances. + * + * @returns NV_STATUS, NV_OK if success, + * NV_ERR_GENERIC, if error + * NV_ERR_NOT_SUPPORTED, for unsupported platforms + */ + +NV_STATUS +osGetTegraNumDpAuxInstances +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 *pNumIntances +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +/* + * @brief Return the priv Data of current IRQ. + * It is wrapper function to call unix/linux layer. + * + * @param[in] pGpu Device of interest + * @param[out] pPrivData privData of current IRQ + * + * @returns NV_STATUS, NV_OK if success, + * NV_ERR_GENERIC, if error + * NV_ERR_NOT_SUPPORTED, for unsupported platforms + */ +NV_STATUS +osGetCurrentIrqPrivData +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 *pPrivData +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +/*! + * @brief Get the brightness level + * It is wrapper function to call unix/linux layer. + * + * @param[in] pGpu GPU object pointer + * @param[out] brightness Pointer to brightness level + * + * @returns NV_STATUS, NV_OK if success, + * NV_ERR_GENERIC, if error + * NV_ERR_NOT_SUPPORTED, for unsupported platforms + */ +NV_STATUS +osGetTegraBrightnessLevel +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 *brightness +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +/*! + * @brief Set the brightness level + * It is wrapper function to call unix/linux layer. + * + * @param[in] pGpu GPU object pointer + * @param[out] brightness brightness level + * + * @returns NV_STATUS, NV_OK if success, + * NV_ERR_GENERIC, if error + * NV_ERR_NOT_SUPPORTED, for unsupported platforms + */ +NV_STATUS +osSetTegraBrightnessLevel +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 brightness +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +/* @brief Gets syncpoint aperture information + * + * @param[in] OS_GPU_INFO OS specific GPU information pointer + * @param[in] syncpointId + * @param[out] *physAddr + * @param[out] *limit + * @param[out] *offset + */ +NV_STATUS +osGetSyncpointAperture +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 syncpointId, + NvU64 *physAddr, + NvU64 *limit, + NvU32 *offset +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +/*! + * @brief Enable PCIe AtomicOp Requester Enable and return + * the completer side capabilities that the requester can send. + * + * @param[in] pOsGpuInfo OS_GPU_INFO OS specific GPU information pointer + * @param[out] pMask mask of supported atomic size, including one or more of: + * OS_PCIE_CAP_MASK_REQ_ATOMICS_32 + * OS_PCIE_CAP_MASK_REQ_ATOMICS_64 + * OS_PCIE_CAP_MASK_REQ_ATOMICS_128 + * + * @returns NV_STATUS, NV_OK if success + * NV_ERR_NOT_SUPPORTED if platform doesn't support this + * feature. + * NV_ERR_GENERIC for any other error + */ + +NV_STATUS +osConfigurePcieReqAtomics +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 *pMask +) +{ + if (pMask) + { + *pMask = 0U; + if (pOsGpuInfo) + { + if (os_enable_pci_req_atomics(pOsGpuInfo->handle, + OS_INTF_PCIE_REQ_ATOMICS_32BIT) == NV_OK) + *pMask |= OS_PCIE_CAP_MASK_REQ_ATOMICS_32; + if (os_enable_pci_req_atomics(pOsGpuInfo->handle, + OS_INTF_PCIE_REQ_ATOMICS_64BIT) == NV_OK) + *pMask |= OS_PCIE_CAP_MASK_REQ_ATOMICS_64; + if (os_enable_pci_req_atomics(pOsGpuInfo->handle, + OS_INTF_PCIE_REQ_ATOMICS_128BIT) == NV_OK) + *pMask |= OS_PCIE_CAP_MASK_REQ_ATOMICS_128; + + if (*pMask != 0) + return NV_OK; + } + } + return NV_ERR_NOT_SUPPORTED; +} + +/*! + * @brief Check GPU is accessible or not + * + * @param[in] pGpu GPU object pointer + * + * @returns NVBool, Returns TRUE if the GPU is accessible, + * FALSE, if error + */ +NvBool +osIsGpuAccessible +( + OBJGPU *pGpu +) +{ + return nv_is_gpu_accessible(NV_GET_NV_STATE(pGpu)); +} + +/*! + * @brief Check whether GPU has received a shutdown notification from the OS + */ +NvBool +osIsGpuShutdown +( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + return nv ? nv->is_shutdown : NV_TRUE; +} + +/*! + * @brief Check GPU OS info matches + * + * @param[in] pGpu GPU object pointer + * + * @returns NVBool, Returns TRUE if matched. + */ +NvBool +osMatchGpuOsInfo +( + OBJGPU *pGpu, + void *pOsInfo +) +{ + return nv_match_gpu_os_info(NV_GET_NV_STATE(pGpu), pOsInfo); +} + +/*! + * @brief Release GPU OS info. + * + * @param[in] pOsInfo GPU OS info pointer + * + * @returns void + */ +void +osReleaseGpuOsInfo +( + void *pOsInfo +) +{ + nv_put_file_private(pOsInfo); +} + +NvBool +osDmabufIsSupported(void) +{ + return os_dma_buf_enabled; +} diff --git a/userspace/sdks/nv525/nvalloc/unix/src/osapi.c b/userspace/sdks/nv525/nvalloc/unix/src/osapi.c new file mode 100644 index 0000000..dcd8604 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/src/osapi.c @@ -0,0 +1,5333 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + + +#include +#include +#include +#include +#include +#include +#include // Declares RmInitRm(). +#include "gpu/gpu.h" +#include +#include + +#include +#include +#include +#include "kernel/gpu/mem_mgr/mem_mgr.h" + +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "rmapi/exports.h" +#include "rmapi/rmapi_utils.h" +#include "rmapi/rs_utils.h" +#include "rmapi/resource_fwd_decls.h" +#include +#include +#include "nv-reg.h" +#include "core/hal_mgr.h" +#include "gpu/device/device.h" + +#include "resserv/rs_server.h" +#include "resserv/rs_client.h" +#include "resserv/rs_resource.h" +#include "gpu/gpu_uuid.h" + +#include "platform/chipset/pci_pbi.h" + +#include "ctrl/ctrl0000/ctrl0000system.h" +#include "ctrl/ctrl0073/ctrl0073dp.h" +#include "ctrl/ctrl0073/ctrl0073system.h" +#include "ctrl/ctrl0073/ctrl0073specific.h" +#include "ctrl/ctrl2080/ctrl2080bios.h" +#include "ctrl/ctrl2080/ctrl2080fb.h" +#include "ctrl/ctrl2080/ctrl2080perf.h" +#include "ctrl/ctrl2080/ctrl2080gpu.h" +#include "ctrl/ctrl402c.h" + +#include "g_nv_name_released.h" // released chip entries from nvChipAutoFlags.h + +#include + +#include "gpu/bus/kern_bus.h" + +// +// Helper function which can be called before doing any RM control +// This function: +// +// a. Performs threadStateInit(). +// b. Acquires API lock. +// c. Checks if RMAPI client handle is valid (i.e. RM is initialized) and +// returns early if RMAPI client handle is invalid. +// d. Increments the dynamic power refcount. If GPU is in RTD3 suspended +// state, then it will wake-up the GPU. +// e. Returns the RMAPI interface handle. +// +// This function should be called only when caller doesn't have acquired API +// lock. Caller needs to use RmUnixRmApiEpilogue() after RM control, if +// RmUnixRmApiPrologue() is successful. +// +RM_API *RmUnixRmApiPrologue(nv_state_t *pNv, THREAD_STATE_NODE *pThreadNode, NvU32 module) +{ + threadStateInit(pThreadNode, THREAD_STATE_FLAGS_NONE); + + if ((rmapiLockAcquire(API_LOCK_FLAGS_NONE, module)) == NV_OK) + { + if ((pNv->rmapi.hClient != 0) && + (os_ref_dynamic_power(pNv, NV_DYNAMIC_PM_FINE) == NV_OK)) + { + return rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); + } + + rmapiLockRelease(); + } + + threadStateFree(pThreadNode, THREAD_STATE_FLAGS_NONE); + + return NULL; +} + +// +// Helper function which can be called after doing RM control, if +// caller has used RmUnixRmApiPrologue() helper function. This function: +// +// a. Decrements the dynamic power refcount. +// b. Release API lock. +// c. Performs threadStateFree(). +// +void RmUnixRmApiEpilogue(nv_state_t *pNv, THREAD_STATE_NODE *pThreadNode) +{ + os_unref_dynamic_power(pNv, NV_DYNAMIC_PM_FINE); + rmapiLockRelease(); + threadStateFree(pThreadNode, THREAD_STATE_FLAGS_NONE); +} + +NvBool RmGpuHasIOSpaceEnabled(nv_state_t * nv) +{ + NvU16 val; + NvBool has_io; + os_pci_read_word(nv->handle, NV_CONFIG_PCI_NV_1, &val); + has_io = FLD_TEST_DRF(_CONFIG, _PCI_NV_1, _IO_SPACE, _ENABLED, val); + return has_io; +} + +// This is a stub function for unix +void osHandleDeferredRecovery( + OBJGPU *pGpu +) +{ + +} + +// This is a stub function for unix +NvBool osIsSwPreInitOnly +( + OS_GPU_INFO *pOsGpuInfo +) +{ + return NV_FALSE; +} + +const NvU8 * RmGetGpuUuidRaw( + nv_state_t *pNv +) +{ + NV_STATUS rmStatus; + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + NvU32 gidFlags; + NvBool isApiLockTaken = NV_FALSE; + + if (pNv->nv_uuid_cache.valid) + goto done; + + // + // PBI is not present in simulation and the loop inside + // pciPbiReadUuid takes up considerable amount of time in + // simulation environment during RM load. + // + if (pGpu && IS_SIMULATION(pGpu)) + { + rmStatus = NV_ERR_NOT_SUPPORTED; + } + else + { + rmStatus = pciPbiReadUuid(pNv->handle, pNv->nv_uuid_cache.uuid); + } + + if (rmStatus == NV_OK) + { + rmStatus = gpumgrSetUuid(pNv->gpu_id, pNv->nv_uuid_cache.uuid); + if (rmStatus != NV_OK) + { + return NULL; + } + + pNv->nv_uuid_cache.valid = NV_TRUE; + goto done; + } + else if (rmStatus == NV_ERR_NOT_SUPPORTED) + { + nv_printf(NV_DBG_INFO, + "NVRM: PBI is not supported for GPU " NV_PCI_DEV_FMT "\n", + NV_PCI_DEV_FMT_ARGS(pNv)); + } + + gidFlags = DRF_DEF(2080_GPU_CMD,_GPU_GET_GID_FLAGS,_TYPE,_SHA1) + | DRF_DEF(2080_GPU_CMD,_GPU_GET_GID_FLAGS,_FORMAT,_BINARY); + + if (!rmapiLockIsOwner()) + { + rmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU); + if (rmStatus != NV_OK) + { + return NULL; + } + + isApiLockTaken = NV_TRUE; + } + + if (pGpu == NULL) + { + if (isApiLockTaken == NV_TRUE) + { + rmapiLockRelease(); + } + + return NULL; + } + + rmStatus = gpuGetGidInfo(pGpu, NULL, NULL, gidFlags); + if (isApiLockTaken == NV_TRUE) + { + rmapiLockRelease(); + } + + if (rmStatus != NV_OK) + return NULL; + + if (!pGpu->gpuUuid.isInitialized) + return NULL; + + // copy the uuid from the OBJGPU uuid cache + os_mem_copy(pNv->nv_uuid_cache.uuid, pGpu->gpuUuid.uuid, GPU_UUID_LEN); + pNv->nv_uuid_cache.valid = NV_TRUE; + +done: + return pNv->nv_uuid_cache.uuid; +} + +static NV_STATUS RmGpuUuidRawToString( + const NvU8 *pGidData, + char *pBuf, + NvU32 bufLen +) +{ + NvU8 *pGidString; + NvU32 GidStrlen; + NV_STATUS rmStatus; + NvU32 gidFlags; + + gidFlags = DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _FORMAT, _ASCII) | + DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, _SHA1); + + rmStatus = transformGidToUserFriendlyString(pGidData, RM_SHA1_GID_SIZE, + &pGidString, &GidStrlen, + gidFlags); + if (rmStatus != NV_OK) + return rmStatus; + + if (bufLen >= GidStrlen) + portMemCopy(pBuf, bufLen, pGidString, GidStrlen); + else + rmStatus = NV_ERR_BUFFER_TOO_SMALL; + + portMemFree((void *)pGidString); + + return rmStatus; +} + +// This function should be called with the API and GPU locks already acquired. +NV_STATUS +RmLogGpuCrash(OBJGPU *pGpu) +{ + NV_STATUS status = NV_OK; + NvBool bGpuIsLost, bGpuIsConnected; + + if (pGpu == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // + // Re-evaluate whether or not the GPU is accessible. This could be called + // from a recovery context where the OS has re-enabled MMIO for the device. + // This happens during EEH processing on IBM Power + Linux, and marking + // the device as connected again will allow rcdbAddRmGpuDump() to collect + // more GPU state. + // + bGpuIsLost = pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_LOST); + bGpuIsConnected = pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_CONNECTED); + if (!bGpuIsConnected || bGpuIsLost) + { + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvU32 pmcBoot0 = NV_PRIV_REG_RD32(nv->regs->map_u, NV_PMC_BOOT_0); + if (pmcBoot0 == nvp->pmc_boot_0) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_CONNECTED, NV_TRUE); + pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_LOST, NV_FALSE); + } + } + + // + // Log the engine data to the Journal object, to be pulled out later. This + // will return NV_WARN_MORE_PROCESSING_REQUIRED if the dump needed to be + // deferred to a passive IRQL. We still log the crash dump as being created + // in that case since it (should) be created shortly thereafter, and + // there's currently not a good way to print the below notification + // publicly from the core RM when the DPC completes. + // + status = rcdbAddRmGpuDump(pGpu); + if (status != NV_OK && status != NV_WARN_MORE_PROCESSING_REQUIRED) + { + NV_PRINTF(LEVEL_ERROR, + "%s: failed to save GPU crash data\n", __FUNCTION__); + } + else + { + status = NV_OK; + nv_printf(NV_DBG_ERRORS, + "NVRM: A GPU crash dump has been created. If possible, please run\n" + "NVRM: nvidia-bug-report.sh as root to collect this data before\n" + "NVRM: the NVIDIA kernel module is unloaded.\n"); + } + + // Restore the disconnected properties, if they were reset + pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_CONNECTED, bGpuIsConnected); + pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_LOST, bGpuIsLost); + + // Restore persistence mode to the way it was prior to the crash + osModifyGpuSwStatePersistence(pGpu->pOsGpuInfo, + pGpu->getProperty(pGpu, PDB_PROP_GPU_PERSISTENT_SW_STATE)); + + return status; +} + +static void free_os_event_under_lock(nv_event_t *event) +{ + event->active = NV_FALSE; + + // If refcount > 0, event will be freed by osDereferenceObjectCount + // when the last associated RM event is freed. + if (event->refcount == 0) + { + portMemFree(event); + } +} + +static void free_os_events( + nv_file_private_t *nvfp, + NvHandle client +) +{ + nv_state_t *nv = nv_get_ctl_state(); + nv_event_t **pprev; + + portSyncSpinlockAcquire(nv->event_spinlock); + + pprev = &nv->event_list; + while (*pprev != NULL) + { + nv_event_t *cur = *pprev; + // + // XXX We must be called from either rm_client_free_os_events() or + // RmFreeUnusedClients() for this to work. + // + if ((cur->hParent == client) || (cur->nvfp == nvfp)) + { + *pprev = cur->next; + free_os_event_under_lock(cur); + } + else + { + pprev = &cur->next; + } + } + + portSyncSpinlockRelease(nv->event_spinlock); +} + +void rm_client_free_os_events( + NvHandle client +) +{ + free_os_events(NULL, client); +} + +void RmFreeUnusedClients( + nv_state_t *nv, + nv_file_private_t *nvfp +) +{ + NvU32 *pClientList; + NvU32 numClients, i; + NV_STATUS status; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + // + // The 'nvfp' pointer uniquely identifies an open instance in kernel space + // and the kernel interface layer guarantees that we are not called before + // the associated nvfp descriptor is closed. We can thus safely free + // abandoned clients with matching 'nvfp' pointers. + // + status = rmapiGetClientHandlesFromOSInfo(nvfp, &pClientList, &numClients); + if (status != NV_OK) + { + numClients = 0; + } + + for (i = 0; i < numClients; ++i) + { + NV_PRINTF(LEVEL_INFO, "freeing abandoned client 0x%x\n", + pClientList[i]); + + } + + if (numClients != 0) + { + pRmApi->FreeClientList(pRmApi, pClientList, numClients); + + portMemFree(pClientList); + } + + // Clean up any remaining events using this nvfp. + free_os_events(nvfp, 0); +} + +static void RmUnbindLock( + nv_state_t *nv +) +{ + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + + if ((pGpu == NULL) || (gpuGetUserClientCount(pGpu) == 0)) + { + nv->flags |= NV_FLAG_UNBIND_LOCK; + } +} + +static NV_STATUS allocate_os_event( + NvHandle hParent, + nv_file_private_t *nvfp, + NvU32 fd +) +{ + nv_state_t *nv = nv_get_ctl_state(); + NvU32 status = NV_OK; + nv_event_t *event; + + nv_event_t *new_event = portMemAllocNonPaged(sizeof(nv_event_t)); + if (new_event == NULL) + { + status = NV_ERR_NO_MEMORY; + goto done; + } + + portSyncSpinlockAcquire(nv->event_spinlock); + for (event = nv->event_list; event; event = event->next) + { + // Only one event may be associated with a given fd. + if (event->hParent == hParent && event->fd == fd) + { + status = NV_ERR_INVALID_ARGUMENT; + portSyncSpinlockRelease(nv->event_spinlock); + goto done; + } + } + + new_event->next = nv->event_list; + nv->event_list = new_event; + portSyncSpinlockRelease(nv->event_spinlock); + +done: + if (status == NV_OK) + { + new_event->hParent = hParent; + new_event->nvfp = nvfp; + new_event->fd = fd; + new_event->active = NV_TRUE; + new_event->refcount = 0; + + NV_PRINTF(LEVEL_INFO, "allocated OS event:\n"); + NV_PRINTF(LEVEL_INFO, " hParent: 0x%x\n", hParent); + NV_PRINTF(LEVEL_INFO, " fd: %d\n", fd); + } + else + { + portMemFree(new_event); + } + + return status; +} + +NV_STATUS RmAllocOsEvent( + NvHandle hParent, + nv_file_private_t *nvfp, + NvU32 fd +) +{ + if (NV_OK != allocate_os_event(hParent, nvfp, fd)) + { + NV_PRINTF(LEVEL_ERROR, "failed to allocate OS event\n"); + return NV_ERR_INSUFFICIENT_RESOURCES; + } + return NV_OK; +} + +static NV_STATUS free_os_event( + NvHandle hParent, + NvU32 fd +) +{ + nv_state_t *nv = nv_get_ctl_state(); + nv_event_t *event, *tmp; + NV_STATUS result; + + portSyncSpinlockAcquire(nv->event_spinlock); + tmp = event = nv->event_list; + while (event) + { + if ((event->fd == fd) && (event->hParent == hParent)) + { + if (event == nv->event_list) + nv->event_list = event->next; + else + tmp->next = event->next; + break; + } + tmp = event; + event = event->next; + } + + if (event != NULL) + { + free_os_event_under_lock(event); + result = NV_OK; + } + else + result = NV_ERR_INVALID_EVENT; + portSyncSpinlockRelease(nv->event_spinlock); + + if (result == NV_OK) + { + NV_PRINTF(LEVEL_INFO, "freed OS event:\n"); + NV_PRINTF(LEVEL_INFO, " hParent: 0x%x\n", hParent); + NV_PRINTF(LEVEL_INFO, " fd: %d\n", fd); + } + else + { + NV_PRINTF(LEVEL_ERROR, "failed to find OS event:\n"); + NV_PRINTF(LEVEL_ERROR, " hParent: 0x%x\n", hParent); + NV_PRINTF(LEVEL_ERROR, " fd: %d\n", fd); + } + + return result; +} + +NV_STATUS RmFreeOsEvent( + NvHandle hParent, + NvU32 fd +) +{ + if (NV_OK != free_os_event(hParent, fd)) + { + return NV_ERR_INVALID_EVENT; + } + return NV_OK; +} + +static void RmExecuteWorkItem( + void *pWorkItem +) +{ + nv_work_item_t *pWi = (nv_work_item_t *)pWorkItem; + NvU32 gpuMask; + NvU32 releaseLocks = 0; + + if (!(pWi->flags & NV_WORK_ITEM_FLAGS_REQUIRES_GPU) && + ((pWi->flags & OS_QUEUE_WORKITEM_FLAGS_LOCK_GPUS_RW) || + (pWi->flags & OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_DEVICE_RW) || + (pWi->flags & OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW) || + (pWi->flags & OS_QUEUE_WORKITEM_FLAGS_FULL_GPU_SANITY))) + { + // Requesting one of the GPU locks without providing a GPU instance + NV_ASSERT(0); + goto done; + } + + // Get locks requested by workitem + if (NV_OK != workItemLocksAcquire(pWi->gpuInstance, pWi->flags, + &releaseLocks, &gpuMask)) + { + goto done; + } + + // Some work items may not require a valid GPU instance + if (pWi->flags & NV_WORK_ITEM_FLAGS_REQUIRES_GPU) + { + pWi->func.pGpuFunction(pWi->gpuInstance, pWi->pData); + } + else + { + pWi->func.pSystemFunction(pWi->pData); + } + + // Release any locks taken + workItemLocksRelease(releaseLocks, gpuMask); + +done: + if ((pWi->pData != NULL) && + !(pWi->flags & NV_WORK_ITEM_FLAGS_DONT_FREE_DATA)) + { + portMemFree(pWi->pData); + } + + portMemFree((void *)pWi); +} + +static NV_STATUS RmGetEventData( + nv_file_private_t *nvfp, + NvP64 pEvent, + NvU32 *MoreEvents, + NvBool bUserModeArgs +) +{ + NV_STATUS RmStatus; + NvUnixEvent *pKernelEvent = NULL; + nv_event_t nv_event; + RMAPI_PARAM_COPY paramCopy; + + RmStatus = nv_get_event(nvfp, &nv_event, MoreEvents); + if (RmStatus != NV_OK) + return NV_ERR_OPERATING_SYSTEM; + + // setup for access to client's parameters + RMAPI_PARAM_COPY_INIT(paramCopy, pKernelEvent, pEvent, 1, sizeof(NvUnixEvent)); + RmStatus = rmapiParamsAcquire(¶mCopy, bUserModeArgs); + if (RmStatus != NV_OK) + return NV_ERR_OPERATING_SYSTEM; + + pKernelEvent->hObject = nv_event.hObject; + pKernelEvent->NotifyIndex = nv_event.index; + pKernelEvent->info32 = nv_event.info32; + pKernelEvent->info16 = nv_event.info16; + + // release client buffer access, with copyout as needed + if (rmapiParamsRelease(¶mCopy) != NV_OK) + return NV_ERR_OPERATING_SYSTEM; + + return NV_OK; +} + +static NV_STATUS RmAccessRegistry( + NvHandle hClient, + NvHandle hObject, + NvU32 AccessType, + NvP64 clientDevNodeAddress, + NvU32 DevNodeLength, + NvP64 clientParmStrAddress, + NvU32 ParmStrLength, + NvP64 clientBinaryDataAddress, + NvU32 *pBinaryDataLength, + NvU32 *Data, + NvU32 *Entry +) +{ + NvU32 gpuMask = 0, gpuInstance = 0; + OBJGPU *pGpu; + NvBool isDevice = NV_FALSE; + NV_STATUS RmStatus = NV_ERR_OPERATING_SYSTEM; + RsClient *pClient; + Device *pDevice; + Subdevice *pSubdevice; + + RMAPI_PARAM_COPY devNodeParamCopy; + NvU8 *tmpDevNode = NULL; + NvU32 copyOutDevNodeLength = 0; + + RMAPI_PARAM_COPY parmStrParamCopy; + char *tmpParmStr = NULL; + NvU32 copyOutParmStrLength = 0; + + RMAPI_PARAM_COPY binaryDataParamCopy; + NvU8 *tmpBinaryData = NULL; + NvU32 BinaryDataLength = 0; + NvU32 copyOutBinaryDataLength = 0; + + if (NV_OK != serverAcquireClient(&g_resServ, hClient, LOCK_ACCESS_WRITE, &pClient)) + return NV_ERR_INVALID_CLIENT; + + if (hClient == hObject) + { + pGpu = NULL; + } + else + { + RmStatus = deviceGetByHandle(pClient, hObject, &pDevice); + if (RmStatus != NV_OK) + { + RmStatus = subdeviceGetByHandle(pClient, hObject, &pSubdevice); + if (RmStatus != NV_OK) + goto done; + + RmStatus = rmGpuGroupLockAcquire(pSubdevice->subDeviceInst, + GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_GPU, + &gpuMask); + if (RmStatus != NV_OK) + return RmStatus; + + GPU_RES_SET_THREAD_BC_STATE(pSubdevice); + pGpu = GPU_RES_GET_GPU(pSubdevice); + } + else + { + RmStatus = rmGpuGroupLockAcquire(pDevice->deviceInst, + GPU_LOCK_GRP_DEVICE, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_GPU, + &gpuMask); + if (RmStatus != NV_OK) + return RmStatus; + + GPU_RES_SET_THREAD_BC_STATE(pDevice); + pGpu = GPU_RES_GET_GPU(pDevice); + isDevice = NV_TRUE; + } + } + + if (pBinaryDataLength) + { + BinaryDataLength = *pBinaryDataLength; + } + + // a passed-in devNode + if (DevNodeLength) + { + // the passed-in DevNodeLength does not account for '\0' + DevNodeLength++; + + if (DevNodeLength > NVOS38_MAX_REGISTRY_STRING_LENGTH) + { + RmStatus = NV_ERR_INVALID_STRING_LENGTH; + goto done; + } + + // get access to client's DevNode + RMAPI_PARAM_COPY_INIT(devNodeParamCopy, tmpDevNode, clientDevNodeAddress, DevNodeLength, 1); + devNodeParamCopy.flags |= RMAPI_PARAM_COPY_FLAGS_ZERO_BUFFER; + RmStatus = rmapiParamsAcquire(&devNodeParamCopy, NV_TRUE); + if (RmStatus != NV_OK) + { + RmStatus = NV_ERR_OPERATING_SYSTEM; + goto done; + } + } + + // a passed-in parmStr + if (ParmStrLength) + { + // the passed-in ParmStrLength does not account for '\0' + ParmStrLength++; + + if ((ParmStrLength == 0) || (ParmStrLength > NVOS38_MAX_REGISTRY_STRING_LENGTH)) + { + RmStatus = NV_ERR_INVALID_STRING_LENGTH; + goto done; + } + // get access to client's parmStr + RMAPI_PARAM_COPY_INIT(parmStrParamCopy, tmpParmStr, clientParmStrAddress, ParmStrLength, 1); + RmStatus = rmapiParamsAcquire(&parmStrParamCopy, NV_TRUE); + if (RmStatus != NV_OK) + { + RmStatus = NV_ERR_OPERATING_SYSTEM; + goto done; + } + if (tmpParmStr[ParmStrLength - 1] != '\0') + { + RmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + } + + if ((AccessType == NVOS38_ACCESS_TYPE_READ_BINARY) || + (AccessType == NVOS38_ACCESS_TYPE_WRITE_BINARY)) + { + if ((BinaryDataLength > NVOS38_MAX_REGISTRY_BINARY_LENGTH) || + (BinaryDataLength == 0)) + { + RmStatus = NV_ERR_INVALID_STRING_LENGTH; + goto done; + } + + // get access to client's binaryData + RMAPI_PARAM_COPY_INIT(binaryDataParamCopy, tmpBinaryData, clientBinaryDataAddress, BinaryDataLength, 1); + if (AccessType == NVOS38_ACCESS_TYPE_READ_BINARY) + binaryDataParamCopy.flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYIN; + RmStatus = rmapiParamsAcquire(&binaryDataParamCopy, NV_TRUE); + if (RmStatus != NV_OK) + { + RmStatus = NV_ERR_OPERATING_SYSTEM; + goto done; + } + } + + switch (AccessType) + { + case NVOS38_ACCESS_TYPE_READ_DWORD: + RmStatus = osReadRegistryDword(pGpu, + tmpParmStr, Data); + break; + + case NVOS38_ACCESS_TYPE_WRITE_DWORD: + if (isDevice && osIsAdministrator()) + { + while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + RmStatus = osWriteRegistryDword(pGpu, + tmpParmStr, *Data); + + if (RmStatus != NV_OK) + goto done; + } + break; + } + + RmStatus = osWriteRegistryDword(pGpu, + tmpParmStr, *Data); + break; + + case NVOS38_ACCESS_TYPE_READ_BINARY: + RmStatus = osReadRegistryBinary(pGpu, + tmpParmStr, tmpBinaryData, &BinaryDataLength); + + if (RmStatus != NV_OK) + { + goto done; + } + + if (BinaryDataLength) + copyOutBinaryDataLength = BinaryDataLength; + + break; + + case NVOS38_ACCESS_TYPE_WRITE_BINARY: + if (isDevice && osIsAdministrator()) + { + while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + RmStatus = osWriteRegistryBinary(pGpu, + tmpParmStr, tmpBinaryData, + BinaryDataLength); + + if (RmStatus != NV_OK) + goto done; + } + break; + } + + RmStatus = osWriteRegistryBinary(pGpu, + tmpParmStr, tmpBinaryData, + BinaryDataLength); + break; + + default: + RmStatus = NV_ERR_INVALID_ACCESS_TYPE; + } + + done: + if (gpuMask != 0) + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + + if (tmpDevNode != NULL) + { + // skip copyout on error + if ((RmStatus != NV_OK) || (copyOutDevNodeLength == 0)) + devNodeParamCopy.flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYOUT; + devNodeParamCopy.paramsSize = copyOutDevNodeLength; + if (NV_OK != rmapiParamsRelease(&devNodeParamCopy)) + if (RmStatus == NV_OK) + RmStatus = NV_ERR_OPERATING_SYSTEM; + } + if (tmpParmStr != NULL) + { + // skip copyout on error + if ((RmStatus != NV_OK) || (copyOutParmStrLength == 0)) + parmStrParamCopy.flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYOUT; + parmStrParamCopy.paramsSize = copyOutParmStrLength; + if (NV_OK != rmapiParamsRelease(&parmStrParamCopy)) + if (RmStatus == NV_OK) + RmStatus = NV_ERR_OPERATING_SYSTEM; + } + if (tmpBinaryData != NULL) + { + // skip copyout on error + if ((RmStatus != NV_OK) || (copyOutBinaryDataLength == 0)) + binaryDataParamCopy.flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYOUT; + binaryDataParamCopy.paramsSize = copyOutBinaryDataLength; + if (NV_OK != rmapiParamsRelease(&binaryDataParamCopy)) + if (RmStatus == NV_OK) + RmStatus = NV_ERR_OPERATING_SYSTEM; + *pBinaryDataLength = copyOutBinaryDataLength; + } + + serverReleaseClient(&g_resServ, LOCK_ACCESS_WRITE, pClient); + return RmStatus; +} + +static NV_STATUS RmUpdateDeviceMappingInfo( + NvHandle hClient, + NvHandle hDevice, + NvHandle hMappable, + void *pOldCpuAddress, + void *pNewCpuAddress +) +{ + NV_STATUS status; + RsClient *pClient; + RsResourceRef *pMappableRef; + RsCpuMapping *pCpuMapping; + Device *pDevice; + Subdevice *pSubdevice; + NvU32 gpuMask = 0; + + status = serverAcquireClient(&g_resServ, hClient, LOCK_ACCESS_WRITE, &pClient); + if (status != NV_OK) + return status; + + status = deviceGetByHandle(pClient, hDevice, &pDevice); + if (status != NV_OK) + { + status = subdeviceGetByHandle(pClient, hDevice, &pSubdevice); + if (status != NV_OK) + goto done; + + status = rmGpuGroupLockAcquire(pSubdevice->subDeviceInst, + GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_GPU, + &gpuMask); + if (status != NV_OK) + goto done; + + GPU_RES_SET_THREAD_BC_STATE(pSubdevice); + } + else + { + status = rmGpuGroupLockAcquire(pDevice->deviceInst, + GPU_LOCK_GRP_DEVICE, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_GPU, + &gpuMask); + if (status != NV_OK) + goto done; + + GPU_RES_SET_THREAD_BC_STATE(pDevice); + } + + status = clientGetResourceRef(pClient, hMappable, &pMappableRef); + if (status != NV_OK) + goto done; + + if ((objDynamicCastById(pMappableRef->pResource, classId(Memory)) == NULL) && + (objDynamicCastById(pMappableRef->pResource, classId(KernelChannel)) == NULL)) + { + status = NV_ERR_INVALID_OBJECT_HANDLE; + goto done; + } + + status = refFindCpuMappingWithFilter(pMappableRef, + NV_PTR_TO_NvP64(pOldCpuAddress), + serverutilMappingFilterCurrentUserProc, + &pCpuMapping); + if (status != NV_OK) + goto done; + + pCpuMapping->pLinearAddress = NV_PTR_TO_NvP64(pNewCpuAddress); + +done: + + if (gpuMask != 0) + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + + serverReleaseClient(&g_resServ, LOCK_ACCESS_WRITE, pClient); + return status; +} + +static NV_STATUS RmPerformVersionCheck( + void *pData, + NvU32 dataSize +) +{ + nv_ioctl_rm_api_version_t *pParams; + char clientCh, rmCh; + const char *rmStr = NV_VERSION_STRING; + NvBool relaxed = NV_FALSE; + NvU32 i; + + if (dataSize != sizeof(nv_ioctl_rm_api_version_t)) + return NV_ERR_INVALID_ARGUMENT; + + pParams = pData; + + // + // write the reply value, so that the client knows we recognized + // the request + // + pParams->reply = NV_RM_API_VERSION_REPLY_RECOGNIZED; + + // + // the client requested to override the version check; just return + // success. + // + if (pParams->cmd == NV_RM_API_VERSION_CMD_OVERRIDE) + { + return NV_OK; + } + + // + // the client requested relaxed version checking; we will only + // compare the strings until the first decimal point. + // + if (pParams->cmd == NV_RM_API_VERSION_CMD_RELAXED) + { + relaxed = NV_TRUE; + } + + // + // rmStr (i.e., NV_VERSION_STRING) must be null-terminated and fit within + // NV_RM_API_VERSION_STRING_LENGTH, so that: + // + // (1) If the versions don't match, we can return rmStr in + // pParams->versionString. + // (2) The below loop is guaranteed to not overrun rmStr. + // + if ((os_string_length(rmStr) + 1) > NV_RM_API_VERSION_STRING_LENGTH) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + for (i = 0; i < NV_RM_API_VERSION_STRING_LENGTH; i++) + { + clientCh = pParams->versionString[i]; + rmCh = rmStr[i]; + + // + // fail if the current character is not the same + // + if (clientCh != rmCh) + { + break; + } + + // + // if relaxed matching was requested, succeed when we find the + // first decimal point + // + if ((relaxed) && (clientCh == '.')) + { + return NV_OK; + } + + // + // we found the end of the strings: succeed + // + if (clientCh == '\0') + { + return NV_OK; + } + } + + // + // the version strings did not match: print an error message and + // copy the RM's version string into pParams->versionString, so + // that the client can report the mismatch; explicitly NULL + // terminate the client's string, since we cannot trust it + // + pParams->versionString[NV_RM_API_VERSION_STRING_LENGTH - 1] = '\0'; + + nv_printf(NV_DBG_ERRORS, + "NVRM: API mismatch: the client has the version %s, but\n" + "NVRM: this kernel module has the version %s. Please\n" + "NVRM: make sure that this kernel module and all NVIDIA driver\n" + "NVRM: components have the same version.\n", + pParams->versionString, NV_VERSION_STRING); + + os_string_copy(pParams->versionString, rmStr); + + return NV_ERR_GENERIC; +} + +// +// Check if the NVPCF _DSM functions are implemented under +// NVPCF scope or GPU device scope. +// As part of RM initialisation this function checks the +// support of NVPCF _DSM function implementation under +// NVPCF scope, in case that fails, clear the cached DSM +// support status and retry the NVPCF _DSM function under +// GPU scope. +// +static void RmCheckNvpcfDsmScope( + OBJGPU *pGpu +) +{ + NvU32 supportedFuncs; + NvU16 dsmDataSize = sizeof(supportedFuncs); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + ACPI_DSM_FUNCTION acpiDsmFunction = ACPI_DSM_FUNCTION_NVPCF_2X; + NvU32 acpiDsmSubFunction = NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED; + + nv->nvpcf_dsm_in_gpu_scope = NV_FALSE; + + if ((osCallACPI_DSM(pGpu, acpiDsmFunction, acpiDsmSubFunction, + &supportedFuncs, &dsmDataSize) != NV_OK) || + (FLD_TEST_DRF(PCF0100, _CTRL_CONFIG_DSM, + _FUNC_GET_SUPPORTED_IS_SUPPORTED, _NO, supportedFuncs)) || + (dsmDataSize != sizeof(supportedFuncs))) + { + nv->nvpcf_dsm_in_gpu_scope = NV_TRUE; + + // clear cached DSM function status + uncacheDsmFuncStatus(pGpu, acpiDsmFunction, acpiDsmSubFunction); + } +} + +NV_STATUS RmPowerSourceChangeEvent( + nv_state_t *pNv, + NvU32 event_val +) +{ + NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS params = {0}; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + params.powerStateInfo.powerState = event_val ? NV2080_CTRL_PERF_POWER_SOURCE_BATTERY : + NV2080_CTRL_PERF_POWER_SOURCE_AC; + + return pRmApi->Control(pRmApi, pNv->rmapi.hClient, + pNv->rmapi.hSubDevice, + NV2080_CTRL_CMD_PERF_SET_POWERSTATE, + ¶ms, sizeof(params)); +} + +/*! + * @brief Deal with D-notifier events to apply a performance + * level based on the requested auxiliary power-state. + * Read confluence page "D-Notifiers on Linux" for more details. + * + * @param[in] pGpu OBJGPU pointer. + * @param[in] event_type NvU32 Event type. + */ +static void RmHandleDNotifierEvent( + nv_state_t *pNv, + NvU32 event_type +) +{ + NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS params = { 0 }; + RM_API *pRmApi; + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_OK; + + switch (event_type) + { + case ACPI_NOTIFY_POWER_LEVEL_D1: + params.powerState = NV2080_CTRL_PERF_AUX_POWER_STATE_P0; + break; + case ACPI_NOTIFY_POWER_LEVEL_D2: + params.powerState = NV2080_CTRL_PERF_AUX_POWER_STATE_P1; + break; + case ACPI_NOTIFY_POWER_LEVEL_D3: + params.powerState = NV2080_CTRL_PERF_AUX_POWER_STATE_P2; + break; + case ACPI_NOTIFY_POWER_LEVEL_D4: + params.powerState = NV2080_CTRL_PERF_AUX_POWER_STATE_P3; + break; + case ACPI_NOTIFY_POWER_LEVEL_D5: + params.powerState = NV2080_CTRL_PERF_AUX_POWER_STATE_P4; + break; + default: + return; + } + + pRmApi = RmUnixRmApiPrologue(pNv, &threadState, RM_LOCK_MODULES_ACPI); + if (pRmApi == NULL) + { + return; + } + + rmStatus = pRmApi->Control(pRmApi, pNv->rmapi.hClient, + pNv->rmapi.hSubDevice, + NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE, + ¶ms, sizeof(params)); + + RmUnixRmApiEpilogue(pNv, &threadState); + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s: Failed to handle ACPI D-Notifier event, status=0x%x\n", + __FUNCTION__, rmStatus); + } +} + +static NV_STATUS +RmDmabufVerifyMemHandle( + OBJGPU *pGpu, + NvHandle hSrcClient, + NvHandle hMemory, + NvU64 offset, + NvU64 size, + void *pGpuInstanceInfo +) +{ + NV_STATUS status; + RsClient *pClient = NULL; + RsResourceRef *pSrcMemoryRef = NULL; + Memory *pSrcMemory = NULL; + MEMORY_DESCRIPTOR *pMemDesc = NULL; + + NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hSrcClient, &pClient)); + + status = clientGetResourceRef(pClient, hMemory, &pSrcMemoryRef); + if (status != NV_OK) + { + return status; + } + + pSrcMemory = dynamicCast(pSrcMemoryRef->pResource, Memory); + if (pSrcMemory == NULL) + { + return NV_ERR_INVALID_OBJECT; + } + + pMemDesc = pSrcMemory->pMemDesc; + + if (pGpuInstanceInfo != NULL) + { + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance; + pKernelMIGGpuInstance = (KERNEL_MIG_GPU_INSTANCE *) pGpuInstanceInfo; + + if ((pKernelMIGGpuInstance->pMemoryPartitionHeap != pSrcMemory->pHeap)) + { + return NV_ERR_INVALID_OBJECT_PARENT; + } + } + + // Check if hMemory belongs to the same pGpu + if ((pMemDesc->pGpu != pGpu) && + (pSrcMemory->pGpu != pGpu)) + { + return NV_ERR_INVALID_OBJECT_PARENT; + } + + // Offset and size must be aligned to OS page-size + if (!NV_IS_ALIGNED64(offset, os_page_size) || + !NV_IS_ALIGNED64(size, os_page_size)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // Only supported for vidmem handles + if (memdescGetAddressSpace(pMemDesc) != ADDR_FBMEM) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if ((size == 0) || + (size > memdescGetSize(pMemDesc)) || + (offset > (memdescGetSize(pMemDesc) - size))) + { + return NV_ERR_INVALID_ARGUMENT; + } + + return NV_OK; +} + +static NV_STATUS +RmDmabufGetClientAndDevice( + OBJGPU *pGpu, + NvHandle hClient, + NvHandle *phClient, + NvHandle *phDevice, + NvHandle *phSubdevice, + void **ppGpuInstanceInfo +) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + if (IS_MIG_ENABLED(pGpu)) + { + NV_STATUS status; + MIG_INSTANCE_REF ref; + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + + status = kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, + hClient, &ref); + if (status != NV_OK) + { + return status; + } + + status = kmigmgrIncRefCount(ref.pKernelMIGGpuInstance->pShare); + if (status != NV_OK) + { + return status; + } + + *phClient = ref.pKernelMIGGpuInstance->instanceHandles.hClient; + *phDevice = ref.pKernelMIGGpuInstance->instanceHandles.hDevice; + *phSubdevice = ref.pKernelMIGGpuInstance->instanceHandles.hSubdevice; + *ppGpuInstanceInfo = (void *) ref.pKernelMIGGpuInstance; + + return NV_OK; + } + + *phClient = pMemoryManager->hClient; + *phDevice = pMemoryManager->hDevice; + *phSubdevice = pMemoryManager->hSubdevice; + *ppGpuInstanceInfo = NULL; + + return NV_OK; +} + +static void +RmDmabufPutClientAndDevice( + OBJGPU *pGpu, + NvHandle hClient, + NvHandle hDevice, + NvHandle hSubdevice, + void *pGpuInstanceInfo +) +{ + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance; + + if (pGpuInstanceInfo == NULL) + { + return; + } + + pKernelMIGGpuInstance = (KERNEL_MIG_GPU_INSTANCE *) pGpuInstanceInfo; + + NV_ASSERT_OK(kmigmgrDecRefCount(pKernelMIGGpuInstance->pShare)); +} + +/* + * --------------------------------------------------------------------------- + * + * The routines below are part of the interface between the kernel interface + * layer and the kernel-agnostic portions of the resource manager. + * + * --------------------------------------------------------------------------- + */ + +NvBool NV_API_CALL rm_init_private_state( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + NvBool retval; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + retval = RmInitPrivateState(pNv); + + NV_EXIT_RM_RUNTIME(sp,fp); + + return retval; +} + +void NV_API_CALL rm_free_private_state( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + RmFreePrivateState(pNv); + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NvBool NV_API_CALL rm_init_adapter( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + THREAD_STATE_NODE threadState; + NvBool retval = NV_FALSE; + void *fp; + NvBool bEnabled; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_DEVICE_INIT); + + // LOCK: acquire API lock + if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_INIT) == NV_OK) + { + if (!((gpumgrQueryGpuDrainState(pNv->gpu_id, &bEnabled, NULL) == NV_OK) + && bEnabled)) + { + if (pNv->flags & NV_FLAG_PERSISTENT_SW_STATE) + { + retval = RmPartiallyInitAdapter(pNv); + } + else + { + retval = RmInitAdapter(pNv); + } + } + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return retval; +} + +void NV_API_CALL rm_disable_adapter( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + THREAD_STATE_NODE threadState; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_ASSERT_OK(os_flush_work_queue(pNv->queue)); + + // LOCK: acquire API lock + if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DESTROY) == NV_OK) + { + if (pNv->flags & NV_FLAG_PERSISTENT_SW_STATE) + { + RmPartiallyDisableAdapter(pNv); + } + else + { + RmDisableAdapter(pNv); + } + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + NV_ASSERT_OK(os_flush_work_queue(pNv->queue)); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +void NV_API_CALL rm_shutdown_adapter( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + THREAD_STATE_NODE threadState; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DESTROY) == NV_OK) + { + RmShutdownAdapter(pNv); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NV_STATUS NV_API_CALL rm_exclude_adapter( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + NV_STATUS rmStatus; + THREAD_STATE_NODE threadState; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + rmStatus = RmExcludeAdapter(pNv); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_acquire_api_lock( + nvidia_stack_t *sp +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_release_api_lock( + nvidia_stack_t *sp +) +{ + THREAD_STATE_NODE threadState; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // UNLOCK: release API lock + rmapiLockRelease(); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return NV_OK; +} + +NV_STATUS NV_API_CALL rm_acquire_gpu_lock( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire GPU lock + rmStatus = rmDeviceGpuLocksAcquire(NV_GET_NV_PRIV_PGPU(nv), + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_OSAPI); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_release_gpu_lock( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + THREAD_STATE_NODE threadState; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // UNLOCK: release GPU lock + rmDeviceGpuLocksRelease(NV_GET_NV_PRIV_PGPU(nv), GPUS_LOCK_FLAGS_NONE, NULL); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return NV_OK; +} + +NV_STATUS NV_API_CALL rm_acquire_all_gpus_lock( + nvidia_stack_t *sp +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire all GPUs lock + rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_release_all_gpus_lock( + nvidia_stack_t *sp +) +{ + THREAD_STATE_NODE threadState; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // UNLOCK: release all GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return NV_OK; +} + +/*! + * @brief Handle ACPI_NOTIFY_GPS_STATUS_CHANGE event. + * + * This function is called for GPS when SBIOS trigger + * gps STATUS_CHANGE event, which calls rm control call + * NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL to init the GPS + * data from SBIOS. + */ +static void RmHandleGPSStatusChange +( + nv_state_t *pNv +) +{ +} + +/*! + * @brief Function to handle device specific ACPI events. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + * @param[in] event_type NvU32 Event type. + */ +void NV_API_CALL rm_acpi_notify( + nvidia_stack_t *sp, + nv_state_t *nv, + NvU32 event_type +) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + + switch (event_type) + { + case ACPI_VIDEO_NOTIFY_PROBE: + { + THREAD_STATE_NODE threadState; + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + RmHandleDisplayChange(sp, nv); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + break; + } + + case ACPI_NOTIFY_GPS_STATUS_CHANGE: + RmHandleGPSStatusChange(nv); + break; + + case ACPI_NOTIFY_POWER_LEVEL_D1: /* fallthrough */ + case ACPI_NOTIFY_POWER_LEVEL_D2: /* fallthrough */ + case ACPI_NOTIFY_POWER_LEVEL_D3: /* fallthrough */ + case ACPI_NOTIFY_POWER_LEVEL_D4: /* fallthrough */ + case ACPI_NOTIFY_POWER_LEVEL_D5: + RmHandleDNotifierEvent(nv, event_type); + break; + + default: + NV_PRINTF(LEVEL_INFO, "No support for 0x%x event\n", event_type); + NV_ASSERT(0); + break; + } + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +static void nv_align_mmap_offset_length( + nv_usermap_access_params_t *nvuap) +{ + NvU64 page_size = os_page_size; + NvU64 end = nvuap->size + (nvuap->addr & (page_size - 1)); + + nvuap->mmap_start = NV_ALIGN_DOWN(nvuap->addr, page_size); + nvuap->mmap_size = NV_ALIGN_UP(end, page_size); + nvuap->offset = NV_ALIGN_DOWN(nvuap->offset, page_size); +} + +static inline NV_STATUS RmGetArrayMinMax( + NvU64 *array, + NvU64 count, + NvU64 *min, + NvU64 *max +) +{ + NvU64 i; + + if (array == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + *min = array[0]; + *max = array[0]; + + if (count == 1) + return NV_OK; + + for (i = 1; i < count; i++) + { + if (array[i] > *max) + *max = array[i]; + + if (array[i] < *min) + *min = array[i]; + } + + return NV_OK; +} + +static NV_STATUS RmSetUserMapAccessRange( + nv_usermap_access_params_t *nvuap +) +{ + NV_STATUS status = NV_OK; + + if (nvuap->contig) + { + nvuap->access_start = nvuap->mmap_start; + nvuap->access_size = nvuap->mmap_size; + } + else + { + NvU64 highest_address_mapped; + NvU64 lowest_address_mapped; + + status = RmGetArrayMinMax(nvuap->page_array, nvuap->num_pages, + &lowest_address_mapped, + &highest_address_mapped); + if (status != NV_OK) + { + return status; + } + + nvuap->access_start = lowest_address_mapped; + nvuap->access_size = (highest_address_mapped + os_page_size) - lowest_address_mapped; + } + + return status; +} + +static NV_STATUS RmGetAllocPrivate(NvU32, NvU32, NvU64, NvU64, NvU32 *, void **, + NvU64 *); +static NV_STATUS RmValidateMmapRequest(nv_state_t *, NvU64, NvU64, NvU32 *); + +static NV_STATUS RmGetMmapPteArray( + KernelMemorySystem *pKernelMemorySystem, + NvHandle hClient, + NvHandle hMemory, + nv_usermap_access_params_t *nvuap +) +{ + NV_STATUS status = NV_OK; + NvU64 pages = 0; + Memory *pMemory = NULL; + PMEMORY_DESCRIPTOR pMemDesc = NULL; + RsResourceRef *pResourceRef; + NvU64 i; + NvU64 *pteArray; + NvU64 index; + + if (nvuap == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // + // If we're mapping a memory handle, we can get the data from the + // descriptor (required if the allocation being mapped is discontiguous). + // + if (serverutilGetResourceRefWithType(hClient, hMemory, classId(Memory), + &pResourceRef) == NV_OK) + { + pMemory = dynamicCast(pResourceRef->pResource, Memory); + pMemDesc = pMemory->pMemDesc; + nvuap->contig = memdescGetContiguity(pMemDesc, AT_CPU); + } + + // + // In the discontiguous case, the page array needs to be large enough to hold + // the 4K-page-sized addresses that we will then deflate to OS page addresses. + // For the contiguous case, we can create the OS-page-sized addresses + // directly in the array. + // + if (nvuap->contig) + { + pages = nvuap->mmap_size / os_page_size; + } + else + { + pages = nvuap->mmap_size / NV_RM_PAGE_SIZE; + } + + NV_ASSERT_OR_RETURN(pages != 0, NV_ERR_INVALID_ARGUMENT); + + status = os_alloc_mem((void **)&nvuap->page_array, (pages * sizeof(NvU64))); + if (status != NV_OK) + { + return status; + } + + if (!nvuap->contig) + { + pteArray = memdescGetPteArray(pMemDesc, AT_CPU); + index = nvuap->offset / NV_RM_PAGE_SIZE; + + // + // We're guaranteed to have a MEMORY_DESCRIPTOR in the discontiguous + // case. Copy over the addresses now. + // + portMemCopy((void *)nvuap->page_array, + pages * sizeof(NvU64), (void *)&pteArray[index], + pages * sizeof(NvU64)); + + if (NV_RM_PAGE_SIZE < os_page_size) + { + RmDeflateRmToOsPageArray(nvuap->page_array, pages); + pages = NV_RM_PAGES_TO_OS_PAGES(pages); + } + + // + // Convert the GPU physical addresses to system physical addresses, + // if applicable. + // + for (i = 0; i < pages; i++) + { + nvuap->page_array[i] += pKernelMemorySystem->coherentCpuFbBase; + } + } + else + { + // Offset is accounted in mmap_start. + for (nvuap->page_array[0] = nvuap->mmap_start, i = 1; + i < pages; i++) + { + nvuap->page_array[i] = nvuap->page_array[i-1] + os_page_size; + } + } + + nvuap->num_pages = pages; + + return status; +} + +/* Must be called with the API lock and the GPU locks */ +static NV_STATUS RmCreateMmapContextLocked( + NvHandle hClient, + NvHandle hDevice, + NvHandle hMemory, + NvP64 address, + NvU64 size, + NvU64 offset, + NvU32 cachingType, + NvU32 fd +) +{ + NV_STATUS status = NV_OK; + void *pAllocPriv = NULL; + OBJGPU *pGpu = NULL; + KernelMemorySystem *pKernelMemorySystem = NULL; + NvBool bCoherentAtsCpuOffset = NV_FALSE; + nv_state_t *pNv = NULL; + NvU64 addr = (NvU64)address; + NvU32 prot = 0; + NvU64 pageIndex = 0; + nv_usermap_access_params_t *nvuap = NULL; + NvBool bClientMap = (hClient == hDevice); + + if (!bClientMap) + { + if (CliSetGpuContext(hClient, hDevice, &pGpu, NULL) != NV_OK) + { + NvU32 tmp; + if (CliSetSubDeviceContext(hClient, hDevice, &tmp, &pGpu) != NV_OK) + { + // + // If this mapping isn't for a GPU then we don't need to + // create a context for it. + // + return status; + } + } + } + + status = os_alloc_mem((void**)&nvuap, sizeof(nv_usermap_access_params_t)); + if (status != NV_OK) + { + return status; + } + + portMemSet(nvuap, 0, sizeof(nv_usermap_access_params_t)); + nvuap->addr = addr; + nvuap->size = size; + nvuap->offset = offset; + nvuap->caching = cachingType; + + // + // Assume the allocation is contiguous until RmGetMmapPteArray + // determines otherwise. + // + nvuap->contig = NV_TRUE; + nv_align_mmap_offset_length(nvuap); + + if (pGpu != NULL) + { + pNv = NV_GET_NV_STATE(pGpu); + pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + bCoherentAtsCpuOffset = IS_COHERENT_CPU_ATS_OFFSET(pKernelMemorySystem, addr, size); + } + + // + // If no device is given, or the address isn't in the given device's BARs, + // validate this as a system memory mapping and associate it with the + // control device. + // + if ((pNv == NULL) || + (!IS_REG_OFFSET(pNv, addr, size) && + !IS_FB_OFFSET(pNv, addr, size) && + !bCoherentAtsCpuOffset && + !IS_IMEM_OFFSET(pNv, addr, size))) + { + pNv = nv_get_ctl_state(); + + // + // Validate the mapping request by looking up the underlying sysmem + // allocation. + // + status = RmGetAllocPrivate(hClient, hMemory, addr, size, &prot, &pAllocPriv, + &pageIndex); + + if (status != NV_OK) + { + goto done; + } + } + else + { + // + // Validate the mapping request for ATS and get pteArray + // + if (bCoherentAtsCpuOffset) + { + status = RmGetMmapPteArray(pKernelMemorySystem, hClient, hMemory, nvuap); + if (status != NV_OK) + { + goto done; + } + } + + if (RmSetUserMapAccessRange(nvuap) != NV_OK) + { + goto done; + } + + status = nv_get_usermap_access_params(pNv, nvuap); + if (status != NV_OK) + { + goto done; + } + + // Validate the mapping request for BAR's. + status = RmValidateMmapRequest(pNv, nvuap->access_start, + nvuap->access_size, &prot); + if (status != NV_OK) + { + goto done; + } + } + + status = nv_add_mapping_context_to_file(pNv, nvuap, prot, pAllocPriv, + pageIndex, fd); + +done: + os_free_mem(nvuap); + return status; +} + +// TODO: Bug 1802250: [uvm8] Use an alt stack in all functions in unix/src/osapi.c +NV_STATUS rm_create_mmap_context( + NvHandle hClient, + NvHandle hDevice, + NvHandle hMemory, + NvP64 address, + NvU64 size, + NvU64 offset, + NvU32 cachingType, + NvU32 fd +) +{ + NV_STATUS rmStatus = NV_OK; + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_OSAPI)) == NV_OK) + { + RmClient *pClient; + + if (NV_OK != serverutilAcquireClient(hClient, LOCK_ACCESS_READ, &pClient)) + return NV_ERR_INVALID_CLIENT; + + if (pClient->ProcID != osGetCurrentProcess()) + { + rmStatus = NV_ERR_INVALID_CLIENT; + } + // LOCK: acquire GPUs lock + else if ((rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI)) == NV_OK) + { + rmStatus = RmCreateMmapContextLocked(hClient, hDevice, hMemory, + address, size, offset, cachingType, fd); + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + + serverutilReleaseClient(LOCK_ACCESS_READ, pClient); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + return rmStatus; +} + +static NV_STATUS RmGetAllocPrivate( + NvU32 hClient, + NvU32 hMemory, + NvU64 offset, + NvU64 length, + NvU32 *pProtection, + void **ppPrivate, + NvU64 *pPageIndex +) +{ + RmClient *pClient; + NV_STATUS rmStatus; + PMEMORY_DESCRIPTOR pMemDesc; + NvU32 pageOffset; + NvU64 pageCount; + NvU64 endingOffset; + RsResourceRef *pResourceRef; + RmResource *pRmResource; + void *pMemData; + NvBool bPeerIoMem; + NvBool bReadOnlyMem; + *pProtection = NV_PROTECT_READ_WRITE; + *ppPrivate = NULL; + + pageOffset = (offset & ~os_page_mask); + offset &= os_page_mask; + + NV_ASSERT_OR_RETURN(rmapiLockIsOwner(), NV_ERR_INVALID_LOCK_STATE); + + if (NV_OK != serverutilAcquireClient(hClient, LOCK_ACCESS_READ, &pClient)) + return NV_ERR_INVALID_CLIENT; + + rmStatus = clientGetResourceRef(staticCast(pClient, RsClient), hMemory, &pResourceRef); + if (rmStatus != NV_OK) + goto done; + + pRmResource = dynamicCast(pResourceRef->pResource, RmResource); + if (!pRmResource) + { + rmStatus = NV_ERR_INVALID_OBJECT; + goto done; + } + + rmStatus = rmresGetMemoryMappingDescriptor(pRmResource, &pMemDesc); + if (rmStatus != NV_OK) + goto done; + + bReadOnlyMem = memdescGetFlag(pMemDesc, MEMDESC_FLAGS_USER_READ_ONLY); + bPeerIoMem = memdescGetFlag(pMemDesc, MEMDESC_FLAGS_PEER_IO_MEM); + + if (!(pMemDesc->Allocated || bPeerIoMem)) + { + rmStatus = NV_ERR_OBJECT_NOT_FOUND; + goto done; + } + + switch (memdescGetAddressSpace(pMemDesc)) + { + case ADDR_SYSMEM: + break; + default: + rmStatus = NV_ERR_OBJECT_NOT_FOUND; + goto done; + } + + pMemData = memdescGetMemData(pMemDesc); + if (pMemData == NULL) + { + rmStatus = NV_ERR_OBJECT_NOT_FOUND; + goto done; + } + + rmStatus = os_match_mmap_offset(pMemData, offset, pPageIndex); + if (rmStatus != NV_OK) + goto done; + + if (!portSafeAddU64(pageOffset, length, &endingOffset)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + pageCount = (endingOffset / os_page_size); + + if (!portSafeAddU64(*pPageIndex + ((endingOffset % os_page_size) ? 1 : 0), + pageCount, &pageCount)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + if (pageCount > NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + if (bReadOnlyMem) + *pProtection = NV_PROTECT_READABLE; + + *ppPrivate = pMemData; + +done: + serverutilReleaseClient(LOCK_ACCESS_READ, pClient); + + return rmStatus; +} + +static NV_STATUS RmValidateMmapRequest( + nv_state_t *pNv, + NvU64 offset, + NvU64 length, + NvU32 *pProtection +) +{ + NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS params = { 0 }; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NV_STATUS status; + + if (osIsAdministrator()) + { + *pProtection = NV_PROTECT_READ_WRITE; + return NV_OK; + } + + params.addressStart = offset; + params.addressLength = length; + + status = pRmApi->Control(pRmApi, pNv->rmapi.hClient, + pNv->rmapi.hSubDevice, + NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST, + ¶ms, sizeof(params)); + + if (status == NV_OK) + { + *pProtection = params.protection; + } + + return status; +} + +NV_STATUS rm_get_adapter_status( + nv_state_t *pNv, + NvU32 *pStatus +) +{ + NV_STATUS rmStatus = NV_ERR_OPERATING_SYSTEM; + + // LOCK: acquire API lock + if (rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_OSAPI) == NV_OK) + { + rmStatus = RmGetAdapterStatus(pNv, pStatus); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + return rmStatus; +} + +NvBool NV_API_CALL rm_init_rm( + nvidia_stack_t *sp +) +{ + NvBool retval; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + retval = RmInitRm(); + + NV_EXIT_RM_RUNTIME(sp,fp); + + return retval; +} + +void NV_API_CALL rm_shutdown_rm( + nvidia_stack_t *sp +) +{ + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + RmShutdownRm(); + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NvBool NV_API_CALL rm_init_event_locks( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + void *fp; + NvBool ret; + + NV_ENTER_RM_RUNTIME(sp,fp); + + pNv->event_spinlock = portSyncSpinlockCreate(portMemAllocatorGetGlobalNonPaged()); + ret = (pNv->event_spinlock != NULL); + + NV_EXIT_RM_RUNTIME(sp,fp); + return ret; +} + +void NV_API_CALL rm_destroy_event_locks( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + if (pNv && pNv->event_spinlock) + portSyncSpinlockDestroy(pNv->event_spinlock); + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +void NV_API_CALL rm_get_vbios_version( + nvidia_stack_t *sp, + nv_state_t *pNv, + char *vbiosString +) +{ + void *fp; + NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS *params; + RM_API *pRmApi; + THREAD_STATE_NODE threadState; + const size_t vbiosStringLen = 15; // "xx.xx.xx.xx.xx" + + os_snprintf(vbiosString, vbiosStringLen, "??.??.??.??.??"); + + NV_ENTER_RM_RUNTIME(sp,fp); + + params = portMemAllocNonPaged(sizeof(*params)); + if (params == NULL) + { + NV_EXIT_RM_RUNTIME(sp,fp); + return; + } + + portMemSet(params, 0, sizeof(*params)); + + params->biosInfoList[0].index = NV2080_CTRL_BIOS_INFO_INDEX_REVISION; + params->biosInfoList[1].index = NV2080_CTRL_BIOS_INFO_INDEX_OEM_REVISION; + params->biosInfoListSize = 2; + + pRmApi = RmUnixRmApiPrologue(pNv, &threadState, RM_LOCK_MODULES_VBIOS); + if (pRmApi != NULL) + { + NV_STATUS rmStatus; + + rmStatus = pRmApi->Control(pRmApi, + pNv->rmapi.hClient, + pNv->rmapi.hSubDevice, + NV2080_CTRL_CMD_BIOS_GET_INFO_V2, + params, + sizeof(*params)); + + if (rmStatus == NV_OK) + { + const NvU32 biosRevision = params->biosInfoList[0].data; + const NvU32 biosOEMRevision = params->biosInfoList[1].data; + + os_snprintf(vbiosString, vbiosStringLen, + "%02x.%02x.%02x.%02x.%02x", + (biosRevision & 0xff000000) >> 24, + (biosRevision & 0x00ff0000) >> 16, + (biosRevision & 0x0000ff00) >> 8, + (biosRevision & 0x000000ff) >> 0, + biosOEMRevision); + } + + RmUnixRmApiEpilogue(pNv, &threadState); + } + + portMemFree(params); + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NV_STATUS NV_API_CALL rm_stop_user_channels( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS params = { 0 }; + RM_API *pRmApi; + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_ERR_INVALID_STATE; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + pRmApi = RmUnixRmApiPrologue(pNv, &threadState, RM_LOCK_MODULES_FIFO); + if (pRmApi != NULL) + { + params.bDisable = NV_TRUE; + rmStatus = pRmApi->Control(pRmApi, pNv->rmapi.hClient, + pNv->rmapi.hSubDevice, + NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS, + ¶ms, sizeof(params)); + + RmUnixRmApiEpilogue(pNv, &threadState); + } + + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_restart_user_channels( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS params = { 0 }; + RM_API *pRmApi; + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_ERR_INVALID_STATE; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + pRmApi = RmUnixRmApiPrologue(pNv, &threadState, RM_LOCK_MODULES_FIFO); + if (pRmApi != NULL) + { + params.bDisable = NV_FALSE; + rmStatus = pRmApi->Control(pRmApi, pNv->rmapi.hClient, pNv->rmapi.hSubDevice, + NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS, + ¶ms, sizeof(params)); + + RmUnixRmApiEpilogue(pNv, &threadState); + } + + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +// +// Use this call to check if the chipset is io coherent +// +NvBool NV_API_CALL rm_is_chipset_io_coherent( + nvidia_stack_t *sp) +{ + void *fp; + OBJSYS *pSys; + OBJCL *pCl; + NvBool bIoCoherent = NV_FALSE; + + NV_ENTER_RM_RUNTIME(sp,fp); + + pSys = SYS_GET_INSTANCE(); + pCl = SYS_GET_CL(pSys); + if (pCl == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "%s: no CL object found, setting io coherent by default\n", + __FUNCTION__); + goto done; + } + + bIoCoherent = pCl->getProperty(pCl, PDB_PROP_CL_IS_CHIPSET_IO_COHERENT); + +done: + NV_EXIT_RM_RUNTIME(sp,fp); + + return bIoCoherent; +} + +NV_STATUS NV_API_CALL rm_ioctl( + nvidia_stack_t *sp, + nv_state_t *pNv, + nv_file_private_t *nvfp, + NvU32 Command, + void *pData, + NvU32 dataSize +) +{ + NV_STATUS rmStatus; + THREAD_STATE_NODE threadState; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + rmStatus = RmIoctl(pNv, nvfp, Command, pData, dataSize); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +void NV_API_CALL rm_cleanup_file_private( + nvidia_stack_t *sp, + nv_state_t *pNv, + nv_file_private_t *nvfp +) +{ + THREAD_STATE_NODE threadState; + void *fp; + RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL); + RM_API_CONTEXT rmApiContext = {0}; + NvU32 i; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + threadStateSetTimeoutOverride(&threadState, 10 * 1000); + + if (rmapiPrologue(pRmApi, &rmApiContext) != NV_OK) + return; + + // LOCK: acquire API lock + if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI) == NV_OK) + { + // Unref any object which was exported on this file. + if (nvfp->handles != NULL) + { + for (i = 0; i < nvfp->maxHandles; i++) + { + if (nvfp->handles[i] == 0) + { + continue; + } + + RmFreeObjExportHandle(nvfp->handles[i]); + nvfp->handles[i] = 0; + } + + os_free_mem(nvfp->handles); + nvfp->handles = NULL; + nvfp->maxHandles = 0; + } + + // Free any RM clients associated with this file. + RmFreeUnusedClients(pNv, nvfp); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + rmapiEpilogue(pRmApi, &rmApiContext); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + if (nvfp->ctl_nvfp != NULL) + { + nv_put_file_private(nvfp->ctl_nvfp_priv); + nvfp->ctl_nvfp = NULL; + nvfp->ctl_nvfp_priv = NULL; + } + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +void NV_API_CALL rm_unbind_lock( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + THREAD_STATE_NODE threadState; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI) == NV_OK) + { + RmUnbindLock(pNv); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NV_STATUS rm_alloc_os_event( + NvHandle hClient, + nv_file_private_t *nvfp, + NvU32 fd +) +{ + NV_STATUS RmStatus; + + // LOCK: acquire API lock + if ((RmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_EVENT)) == NV_OK) + { + RmStatus = RmAllocOsEvent(hClient, nvfp, fd); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + return RmStatus; +} + +NV_STATUS rm_free_os_event( + NvHandle hClient, + NvU32 fd +) +{ + NV_STATUS RmStatus; + + // LOCK: acquire API lock + if ((RmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_EVENT)) == NV_OK) + { + RmStatus = RmFreeOsEvent(hClient, fd); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + return RmStatus; +} + +NV_STATUS rm_get_event_data( + nv_file_private_t *nvfp, + NvP64 pEvent, + NvU32 *MoreEvents +) +{ + NV_STATUS RmStatus; + + // LOCK: acquire API lock + if ((RmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_EVENT)) == NV_OK) + { + RmStatus = RmGetEventData(nvfp, pEvent, MoreEvents, NV_TRUE); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + return RmStatus; +} + +NV_STATUS NV_API_CALL rm_read_registry_dword( + nvidia_stack_t *sp, + nv_state_t *nv, + const char *regParmStr, + NvU32 *Data +) +{ + OBJGPU *pGpu = NULL; + NV_STATUS RmStatus; + void *fp; + NvBool isApiLockTaken = NV_FALSE; + + NV_ENTER_RM_RUNTIME(sp,fp); + + // + // We can be called from different contexts: + // + // 1) early initialization without device state. + // 2) from outside the RM API (without the lock held) + // + // In context 1)the API lock is not needed and + // in context 2), it needs to be acquired. + // + if (nv != NULL) + { + // LOCK: acquire API lock + if ((RmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_OSAPI)) != NV_OK) + { + NV_EXIT_RM_RUNTIME(sp,fp); + return RmStatus; + } + + isApiLockTaken = NV_TRUE; + } + + pGpu = NV_GET_NV_PRIV_PGPU(nv); + + // Skipping the NULL check as osReadRegistryDword takes care of it. + RmStatus = osReadRegistryDword(pGpu, regParmStr, Data); + + if (isApiLockTaken == NV_TRUE) + { + // UNLOCK: release API lock + rmapiLockRelease(); + } + + NV_EXIT_RM_RUNTIME(sp,fp); + + return RmStatus; +} + +NV_STATUS NV_API_CALL rm_write_registry_dword( + nvidia_stack_t *sp, + nv_state_t *nv, + const char *regParmStr, + NvU32 Data +) +{ + NV_STATUS RmStatus; + void *fp; + NvBool isApiLockTaken = NV_FALSE; + + NV_ENTER_RM_RUNTIME(sp,fp); + + if (nv != NULL) + { + // LOCK: acquire API lock + if ((RmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI)) != NV_OK) + { + NV_EXIT_RM_RUNTIME(sp,fp); + return RmStatus; + } + + isApiLockTaken = NV_TRUE; + } + + RmStatus = RmWriteRegistryDword(nv, regParmStr, Data); + + if (isApiLockTaken == NV_TRUE) + { + // UNLOCK: release API lock + rmapiLockRelease(); + } + + NV_EXIT_RM_RUNTIME(sp,fp); + + return RmStatus; +} + +NV_STATUS NV_API_CALL rm_write_registry_binary( + nvidia_stack_t *sp, + nv_state_t *nv, + const char *regParmStr, + NvU8 *Data, + NvU32 cbLen +) +{ + NV_STATUS RmStatus; + void *fp; + NvBool isApiLockTaken = NV_FALSE; + + NV_ENTER_RM_RUNTIME(sp,fp); + + if (nv != NULL) + { + // LOCK: acquire API lock + if ((RmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI)) != NV_OK) + { + NV_EXIT_RM_RUNTIME(sp,fp); + return RmStatus; + } + + isApiLockTaken = NV_TRUE; + } + + RmStatus = RmWriteRegistryBinary(nv, regParmStr, Data, cbLen); + + if (isApiLockTaken == NV_TRUE) + { + // UNLOCK: release API lock + rmapiLockRelease(); + } + + NV_EXIT_RM_RUNTIME(sp,fp); + + return RmStatus; +} + +NV_STATUS NV_API_CALL rm_write_registry_string( + nvidia_stack_t *sp, + nv_state_t *nv, + const char *regParmStr, + const char *string, + NvU32 stringLength +) +{ + NV_STATUS rmStatus; + void *fp; + NvBool isApiLockTaken = NV_FALSE; + + NV_ENTER_RM_RUNTIME(sp,fp); + + if (nv != NULL) + { + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI)) != NV_OK) + { + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; + } + + isApiLockTaken = NV_TRUE; + } + + rmStatus = RmWriteRegistryString(nv, regParmStr, string, (stringLength + 1)); + + if (isApiLockTaken == NV_TRUE) + { + // UNLOCK: release API lock + rmapiLockRelease(); + } + + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +static NvBool NV_API_CALL rm_is_space(const char ch) +{ + // + // return true if it is a: + // ' ' : (space - decimal 32.) + // '\t' : (TAB - decimal 9) + // 'LF' : (Line feed, new line - decimal 10) + // 'VT' : (Vertical TAB - decimal 11) + // 'FF' : (Form feed, new page - decimal 12) + // '\r' : (carriage return - decimal 13) + // + return ((ch == ' ') || ((ch >= '\t') && (ch <= '\r'))); +} + +char* NV_API_CALL rm_remove_spaces(const char *in) +{ + unsigned int len = os_string_length(in) + 1; + const char *in_ptr; + char *out, *out_ptr; + + if (os_alloc_mem((void **)&out, len) != NV_OK) + return NULL; + + in_ptr = in; + out_ptr = out; + + while (*in_ptr != '\0') + { + if (!rm_is_space(*in_ptr)) + *out_ptr++ = *in_ptr; + in_ptr++; + } + *out_ptr = '\0'; + + return out; +} + +char* NV_API_CALL rm_string_token(char **strp, const char delim) +{ + char *s, *token; + + if ((strp == NULL) || (*strp == NULL)) + return NULL; + + s = token = *strp; + *strp = NULL; + + for (; *s != '\0'; s++) { + if (*s == delim) { + *s = '\0'; + *strp = ++s; + break; + } + } + + return token; +} + +// Parse string passed in NVRM as module parameter. +void NV_API_CALL rm_parse_option_string(nvidia_stack_t *sp, const char *nvRegistryDwords) +{ + unsigned int i; + nv_parm_t *entry; + char *option_string = NULL; + char *ptr, *token; + char *name, *value; + NvU32 data; + + if (nvRegistryDwords != NULL) + { + if ((option_string = rm_remove_spaces(nvRegistryDwords)) == NULL) + { + return; + } + + ptr = option_string; + + while ((token = rm_string_token(&ptr, ';')) != NULL) + { + if (!(name = rm_string_token(&token, '=')) || !os_string_length(name)) + { + continue; + } + + if (!(value = rm_string_token(&token, '=')) || !os_string_length(value)) + { + continue; + } + + if (rm_string_token(&token, '=') != NULL) + { + continue; + } + + data = os_strtoul(value, NULL, 0); + + for (i = 0; (entry = &nv_parms[i])->name != NULL; i++) + { + if (os_string_compare(entry->name, name) == 0) + break; + } + + if (!entry->name) + rm_write_registry_dword(sp, NULL, name, data); + else + *entry->data = data; + } + + // Free the memory allocated by rm_remove_spaces() + os_free_mem(option_string); + } +} + +NV_STATUS NV_API_CALL rm_run_rc_callback( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + OBJGPU *pGpu; + void *fp; + + /* make sure our timer's not still running when it shouldn't be */ + if (nv == NULL) + return NV_ERR_GENERIC; + + pGpu = NV_GET_NV_PRIV_PGPU(nv); + if (pGpu == NULL) + return NV_ERR_GENERIC; + + if (nv->rc_timer_enabled == 0) + return NV_ERR_GENERIC; + + if (!FULL_GPU_SANITY_CHECK(pGpu)) + { + return NV_ERR_GENERIC; + } + + NV_ENTER_RM_RUNTIME(sp,fp); + + osRun1HzCallbacksNow(pGpu); + + NV_EXIT_RM_RUNTIME(sp,fp); + + return NV_OK; +} + +static NV_STATUS RmRunNanoTimerCallback( + OBJGPU *pGpu, + void *pTmrEvent +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + POBJTMR pTmr = GPU_GET_TIMER(pGpu); + THREAD_STATE_NODE threadState; + NV_STATUS status = NV_OK; + // LOCK: try to acquire GPUs lock + if ((status = rmGpuLocksAcquire(GPU_LOCK_FLAGS_COND_ACQUIRE, RM_LOCK_MODULES_TMR)) != NV_OK) + { + PTMR_EVENT_PVT pEvent = (PTMR_EVENT_PVT) pTmrEvent; + // We failed to acquire the lock; schedule a timer to try again. + return osStartNanoTimer(pGpu->pOsGpuInfo, pEvent->super.pOSTmrCBdata, 1000); + } + + if ((status = osCondAcquireRmSema(pSys->pSema)) != NV_OK) + { + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + return status; + } + + threadStateInitISRAndDeferredIntHandler(&threadState, pGpu, + THREAD_STATE_FLAGS_IS_DEFERRED_INT_HANDLER); + + // Call timer event service + status = tmrEventServiceOSTimerCallback_HAL(pGpu, pTmr, (PTMR_EVENT)pTmrEvent); + + // Out of conflicting thread + threadStateFreeISRAndDeferredIntHandler(&threadState, + pGpu, THREAD_STATE_FLAGS_IS_DEFERRED_INT_HANDLER); + + osReleaseRmSema(pSys->pSema, NULL); + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, pGpu); + + return status; +} + +NV_STATUS NV_API_CALL rm_run_nano_timer_callback +( + nvidia_stack_t *sp, + nv_state_t *nv, + void *pTmrEvent +) +{ + NV_STATUS status; + OBJGPU *pGpu = NULL; + void *fp; + + if (nv == NULL) + return NV_ERR_GENERIC; + + pGpu = NV_GET_NV_PRIV_PGPU(nv); + if (pGpu == NULL) + return NV_ERR_GENERIC; + + if (!FULL_GPU_SANITY_CHECK(pGpu)) + { + return NV_ERR_GENERIC; + } + + NV_ENTER_RM_RUNTIME(sp,fp); + + status = RmRunNanoTimerCallback(pGpu, pTmrEvent); + + NV_EXIT_RM_RUNTIME(sp,fp); + + return status; +} + +void NV_API_CALL rm_execute_work_item( + nvidia_stack_t *sp, + void *pNvWorkItem +) +{ + void *fp; + THREAD_STATE_NODE threadState; + + NV_ENTER_RM_RUNTIME(sp, fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + RmExecuteWorkItem(pNvWorkItem); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp, fp); +} + +const char* NV_API_CALL rm_get_device_name( + NvU16 device, + NvU16 subsystem_vendor, + NvU16 subsystem_device +) +{ + unsigned int i; + const char *tmpName = NULL; + + for (i = 0; i < NV_ARRAY_ELEMENTS(sChipsReleased); i++) + { + // if the device ID doesn't match, go to the next entry + if (device != sChipsReleased[i].devID) + { + continue; + } + + // if the entry has 0 for the subsystem IDs, then the device + // ID match is sufficient, but continue scanning through + // sChipsReleased[] in case there is a subsystem ID match later + // in the table + if (sChipsReleased[i].subSystemVendorID == 0 && + sChipsReleased[i].subSystemID == 0) + { + tmpName = sChipsReleased[i].name; + continue; + } + + if (subsystem_vendor == sChipsReleased[i].subSystemVendorID && + subsystem_device == sChipsReleased[i].subSystemID) + { + tmpName = sChipsReleased[i].name; + break; + } + } + + return (tmpName != NULL) ? tmpName : "Unknown"; +} + +NV_STATUS rm_access_registry( + NvHandle hClient, + NvHandle hObject, + NvU32 AccessType, + NvP64 clientDevNodeAddress, + NvU32 DevNodeLength, + NvP64 clientParmStrAddress, + NvU32 ParmStrLength, + NvP64 clientBinaryDataAddress, + NvU32 *pBinaryDataLength, + NvU32 *Data, + NvU32 *Entry +) +{ + NV_STATUS RmStatus; + NvBool bReadOnly = (AccessType == NVOS38_ACCESS_TYPE_READ_DWORD) || + (AccessType == NVOS38_ACCESS_TYPE_READ_BINARY); + + // LOCK: acquire API lock + if ((RmStatus = rmapiLockAcquire(bReadOnly ? RMAPI_LOCK_FLAGS_READ : RMAPI_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_OSAPI)) == NV_OK) + { + RmStatus = RmAccessRegistry(hClient, + hObject, + AccessType, + clientDevNodeAddress, + DevNodeLength, + clientParmStrAddress, + ParmStrLength, + clientBinaryDataAddress, + pBinaryDataLength, + Data, + Entry); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + return RmStatus; +} + +NV_STATUS rm_update_device_mapping_info( + NvHandle hClient, + NvHandle hDevice, + NvHandle hMemory, + void *pOldCpuAddress, + void *pNewCpuAddress +) +{ + NV_STATUS RmStatus; + + // LOCK: acquire API lock + if ((RmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU)) == NV_OK) + { + RmStatus = RmUpdateDeviceMappingInfo(hClient, + hDevice, + hMemory, + pOldCpuAddress, + pNewCpuAddress); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + return RmStatus; +} + +static void rm_is_device_rm_firmware_capable( + nv_state_t *pNv, + NvU32 pmcBoot42, + NvBool *pbIsFirmwareCapable, + NvBool *pbEnableByDefault +) +{ + NvBool bIsFirmwareCapable = NV_FALSE; + NvBool bEnableByDefault = NV_FALSE; + + if (NV_IS_SOC_DISPLAY_DEVICE(pNv)) + { + bIsFirmwareCapable = NV_TRUE; + } + else + { + bIsFirmwareCapable = gpumgrIsDeviceRmFirmwareCapable(pNv->pci_info.device_id, + pmcBoot42, + &bEnableByDefault); + } + + if (pbIsFirmwareCapable != NULL) + { + *pbIsFirmwareCapable = bIsFirmwareCapable; + } + if (pbEnableByDefault != NULL) + { + *pbEnableByDefault = bEnableByDefault; + } +} + +static NvBool NV_API_CALL rm_is_legacy_device( + NvU16 device_id, + NvU16 subsystem_vendor, + NvU16 subsystem_device, + NvBool print_warning +) +{ + return NV_FALSE; +} + +static NvBool NV_API_CALL rm_is_legacy_arch( + NvU32 pmc_boot_0, + NvU32 pmc_boot_42 +) +{ + NvBool legacy = NV_FALSE; + + return legacy; +} + +NV_STATUS NV_API_CALL rm_is_supported_device( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + OBJSYS *pSys; + POBJHALMGR pHalMgr; + GPUHWREG *reg_mapping; + NvU32 myHalPublicID; + void *fp; + NvU32 pmc_boot_0; + NvU32 pmc_boot_42; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + pSys = SYS_GET_INSTANCE(); + pHalMgr = SYS_GET_HALMGR(pSys); + + reg_mapping = osMapKernelSpace(pNv->regs->cpu_address, + os_page_size, + NV_MEMORY_UNCACHED, + NV_PROTECT_READABLE); + + if (reg_mapping == NULL) + { + nv_printf(NV_DBG_ERRORS, "NVRM: failed to map registers!\n"); + rmStatus = NV_ERR_OPERATING_SYSTEM; + goto threadfree; + } + NvU32 pmc_boot_1 = NV_PRIV_REG_RD32(reg_mapping, NV_PMC_BOOT_1); + pmc_boot_0 = NV_PRIV_REG_RD32(reg_mapping, NV_PMC_BOOT_0); + pmc_boot_42 = NV_PRIV_REG_RD32(reg_mapping, NV_PMC_BOOT_42); + + osUnmapKernelSpace(reg_mapping, os_page_size); + + if ((pmc_boot_0 == 0xFFFFFFFF) && (pmc_boot_42 == 0xFFFFFFFF)) + { + nv_printf(NV_DBG_ERRORS, + "NVRM: The NVIDIA GPU %04x:%02x:%02x.%x\n" + "NVRM: (PCI ID: %04x:%04x) installed in this system has\n" + "NVRM: fallen off the bus and is not responding to commands.\n", + pNv->pci_info.domain, pNv->pci_info.bus, pNv->pci_info.slot, + pNv->pci_info.function, pNv->pci_info.vendor_id, + pNv->pci_info.device_id); + rmStatus = NV_ERR_GPU_IS_LOST; + goto threadfree; + } + + /* + * For legacy architectures, rm_is_legacy_arch() prints "legacy" message. + * We do not want to print "unsupported" message for legacy architectures + * to avoid confusion. Also, the probe should not continue for legacy + * architectures. Hence, we set rmStatus to NV_ERR_NOT_SUPPORTED and + * goto threadfree. + */ + if (rm_is_legacy_arch(pmc_boot_0, pmc_boot_42)) + { + rmStatus = NV_ERR_NOT_SUPPORTED; + goto threadfree; + } + + rmStatus = halmgrGetHalForGpu(pHalMgr, pmc_boot_0, pmc_boot_42, &myHalPublicID); + + if (rmStatus != NV_OK) + { + NvBool bIsFirmwareCapable; + + rm_is_device_rm_firmware_capable(pNv, + pmc_boot_42, + &bIsFirmwareCapable, + NULL); + if (!bIsFirmwareCapable) + { + nv_printf(NV_DBG_ERRORS, + "NVRM: The NVIDIA GPU %04x:%02x:%02x.%x (PCI ID: %04x:%04x)\n" + "NVRM: installed in this system is not supported by open\n" + "NVRM: nvidia.ko because it does not include the required GPU\n" + "NVRM: System Processor (GSP).\n" + "NVRM: Please see the 'Open Linux Kernel Modules' and 'GSP\n" + "NVRM: Firmware' sections in the driver README, available on\n" + "NVRM: the Linux graphics driver download page at\n" + "NVRM: www.nvidia.com.\n", + pNv->pci_info.domain, pNv->pci_info.bus, pNv->pci_info.slot, + pNv->pci_info.function, pNv->pci_info.vendor_id, + pNv->pci_info.device_id, NV_VERSION_STRING); + goto threadfree; + } + goto print_unsupported; + } + + rmStatus = rm_is_vgpu_supported_device(pNv, pmc_boot_1); + + if (rmStatus != NV_OK) + goto print_unsupported; + goto threadfree; + +print_unsupported: + nv_printf(NV_DBG_ERRORS, + "NVRM: The NVIDIA GPU %04x:%02x:%02x.%x (PCI ID: %04x:%04x)\n" + "NVRM: installed in this system is not supported by the\n" + "NVRM: NVIDIA %s driver release.\n" + "NVRM: Please see 'Appendix A - Supported NVIDIA GPU Products'\n" + "NVRM: in this release's README, available on the operating system\n" + "NVRM: specific graphics driver download page at www.nvidia.com.\n", + pNv->pci_info.domain, pNv->pci_info.bus, pNv->pci_info.slot, + pNv->pci_info.function, pNv->pci_info.vendor_id, + pNv->pci_info.device_id, NV_VERSION_STRING); + +threadfree: + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NvBool NV_API_CALL rm_is_supported_pci_device( + NvU8 pci_class, + NvU8 pci_subclass, + NvU16 vendor, + NvU16 device, + NvU16 subsystem_vendor, + NvU16 subsystem_device, + NvBool print_legacy_warning +) +{ + const NvU16 nv_pci_vendor_id = 0x10DE; + const NvU16 nv_pci_id_riva_tnt = 0x0020; + const NvU8 nv_pci_class_display = 0x03; + const NvU8 nv_pci_subclass_display_vga = 0x00; + const NvU8 nv_pci_subclass_display_3d = 0x02; + + if (pci_class != nv_pci_class_display) + { + return NV_FALSE; + } + + if ((pci_subclass != nv_pci_subclass_display_vga) && + (pci_subclass != nv_pci_subclass_display_3d)) + { + return NV_FALSE; + } + + if (vendor != nv_pci_vendor_id) + { + return NV_FALSE; + } + + if (device < nv_pci_id_riva_tnt) + { + return NV_FALSE; + } + + if (rm_is_legacy_device( + device, + subsystem_vendor, + subsystem_device, + print_legacy_warning)) + { + return NV_FALSE; + } + + return NV_TRUE; +} + +/* + * Performs the I2C transfers which are related with DP AUX channel + */ +static NV_STATUS RmDpAuxI2CTransfer +( + nv_state_t *pNv, + NvU32 displayId, + NvU8 addr, + NvU32 len, + NvU8 *pData, + NvBool bWrite +) +{ + NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_CTRL_PARAMS *pParams; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NV_STATUS status; + + if (len > NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_MAX_DATA_SIZE) + { + NV_PRINTF(LEVEL_ERROR, + "%s: requested I2C transfer length %u is greater than maximum supported length %u\n", + __FUNCTION__, len, NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_MAX_DATA_SIZE); + return NV_ERR_NOT_SUPPORTED; + } + + pParams = portMemAllocNonPaged(sizeof(*pParams)); + if (pParams == NULL) + { + return NV_ERR_NO_MEMORY; + } + + portMemSet(pParams, 0, sizeof(*pParams)); + + pParams->subDeviceInstance = 0; + pParams->displayId = displayId; + pParams->addr = addr; + pParams->size = len; + pParams->bWrite = bWrite; + + if (bWrite) + { + portMemCopy(pParams->data, NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_MAX_DATA_SIZE, + pData, len); + } + + status = pRmApi->Control(pRmApi, pNv->rmapi.hClient, pNv->rmapi.hDisp, + NV0073_CTRL_CMD_DP_AUXCH_I2C_TRANSFER_CTRL, + pParams, sizeof(*pParams)); + + if ((status == NV_OK) && !bWrite) + { + portMemCopy(pData, len, pParams->data, pParams->size); + } + + portMemFree(pParams); + + return status; +} + +/* + * Performs the I2C transfers which are not related with DP AUX channel + */ +static NV_STATUS RmNonDPAuxI2CTransfer +( + nv_state_t *pNv, + NvU8 portId, + nv_i2c_cmd_t type, + NvU8 addr, + NvU8 command, + NvU32 len, + NvU8 *pData +) +{ + NV402C_CTRL_I2C_TRANSACTION_PARAMS *params; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NV_STATUS rmStatus = NV_OK; + + params = portMemAllocNonPaged(sizeof(*params)); + if (params == NULL) + { + return NV_ERR_NO_MEMORY; + } + + portMemSet(params, 0, sizeof(*params)); + + params->portId = portId; + // precondition our address (our stack requires this) + params->deviceAddress = addr << 1; + + switch (type) + { + case NV_I2C_CMD_WRITE: + params->transData.i2cBlockData.bWrite = NV_TRUE; + /* fall through*/ + + case NV_I2C_CMD_READ: + params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW; + params->transData.i2cBlockData.messageLength = len; + params->transData.i2cBlockData.pMessage = pData; + break; + + case NV_I2C_CMD_SMBUS_WRITE: + if (len == 2) + { + params->transData.smbusWordData.bWrite = NV_TRUE; + } + else + { + params->transData.smbusByteData.bWrite = NV_TRUE; + } + /* fall through*/ + + case NV_I2C_CMD_SMBUS_READ: + if (len == 2) + { + params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW; + params->transData.smbusWordData.message = pData[0] | ((NvU16)pData[1] << 8); + params->transData.smbusWordData.registerAddress = command; + } + else + { + params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW; + params->transData.smbusByteData.message = pData[0]; + params->transData.smbusByteData.registerAddress = command; + } + break; + + case NV_I2C_CMD_SMBUS_BLOCK_WRITE: + params->transData.smbusBlockData.bWrite = NV_TRUE; + /* fall through*/ + + case NV_I2C_CMD_SMBUS_BLOCK_READ: + params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW; + params->transData.smbusBlockData.registerAddress = command; + params->transData.smbusBlockData.messageLength = len; + params->transData.smbusBlockData.pMessage = pData; + break; + + case NV_I2C_CMD_SMBUS_QUICK_WRITE: + params->transData.smbusQuickData.bWrite = NV_TRUE; + /* fall through*/ + + case NV_I2C_CMD_SMBUS_QUICK_READ: + params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW; + break; + + case NV_I2C_CMD_BLOCK_WRITE: + params->transData.i2cBufferData.bWrite = NV_TRUE; + /* fall through */ + + case NV_I2C_CMD_BLOCK_READ: + params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW; + params->transData.i2cBufferData.registerAddress = command; + params->transData.i2cBufferData.messageLength = len; + params->transData.i2cBufferData.pMessage = pData; + break; + + default: + portMemFree(params); + return NV_ERR_INVALID_ARGUMENT; + } + + rmStatus = pRmApi->Control(pRmApi, pNv->rmapi.hClient, + pNv->rmapi.hI2C, + NV402C_CTRL_CMD_I2C_TRANSACTION, + params, sizeof(*params)); + + // + // For NV_I2C_CMD_SMBUS_READ, copy the read data to original + // data buffer. + // + if (rmStatus == NV_OK && type == NV_I2C_CMD_SMBUS_READ) + { + if (len == 2) + { + pData[0] = (params->transData.smbusWordData.message & 0xff); + pData[1] = params->transData.smbusWordData.message >> 8; + } + else + { + pData[0] = params->transData.smbusByteData.message; + } + } + + portMemFree(params); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_i2c_transfer( + nvidia_stack_t *sp, + nv_state_t *pNv, + void *pI2cAdapter, + nv_i2c_cmd_t type, + NvU8 addr, + NvU8 command, + NvU32 len, + NvU8 *pData +) +{ + THREAD_STATE_NODE threadState; + nv_priv_t *pNvp = NV_GET_NV_PRIV(pNv); + NV_STATUS rmStatus = NV_OK; + OBJGPU *pGpu = NULL; + NvBool unlockApi = NV_FALSE; + NvBool unlockGpu = NV_FALSE; + NvU32 x; + void *fp; + NvU32 numDispId = 0; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + if (pNvp->flags & NV_INIT_FLAG_PUBLIC_I2C) + { + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_I2C)) != NV_OK) + goto finish; + + unlockApi = NV_TRUE; + + // LOCK: acquire GPUs lock + if ((rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_I2C)) != NV_OK) + goto finish; + + unlockGpu = NV_TRUE; + } + + pGpu = NV_GET_NV_PRIV_PGPU(pNv); + + if (!pGpu) + { + rmStatus = NV_ERR_GENERIC; + goto finish; + } + + for (x = 0; x < MAX_I2C_ADAPTERS; x++) + { + if (pNvp->i2c_adapters[x].pOsAdapter == pI2cAdapter) + { + break; + } + } + + if (x == MAX_I2C_ADAPTERS) + { + rmStatus = NV_ERR_GENERIC; + goto finish; + } + + for (numDispId = 0; numDispId < MAX_DISP_ID_PER_ADAPTER; numDispId++) + { + NvU32 displayId = pNvp->i2c_adapters[x].displayId[numDispId]; + + if (displayId == INVALID_DISP_ID) + { + continue; + } + + // Handle i2c-over-DpAux adapters separately from regular i2c adapters + if (displayId == 0) + { + rmStatus = RmNonDPAuxI2CTransfer(pNv, pNvp->i2c_adapters[x].port, + type, addr, command, len, pData); + } + else + { + if ((type != NV_I2C_CMD_READ) && (type != NV_I2C_CMD_WRITE)) + { + rmStatus = NV_ERR_NOT_SUPPORTED; + goto semafinish; + } + + rmStatus = RmDpAuxI2CTransfer(pNv, displayId, addr, len, pData, + type == NV_I2C_CMD_WRITE); + } +semafinish: + if (rmStatus == NV_OK) + { + break; + } + } + +finish: + if (unlockGpu) + { + // UNLOCK: release GPU lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + + if (unlockApi) + { + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +static void rm_i2c_add_adapter( + nv_state_t *pNv, + NvU32 port, + NvU32 displayId +) +{ + NvU32 y, free; + nv_priv_t *pNvp = NV_GET_NV_PRIV(pNv); + NvU32 numDispId = 0; + + for (y = 0, free = MAX_I2C_ADAPTERS; y < MAX_I2C_ADAPTERS; y++) + { + if (pNvp->i2c_adapters[y].pOsAdapter == NULL) + { + // Only find the first free entry, and ignore the rest + if (free == MAX_I2C_ADAPTERS) + { + free = y; + } + } + else if (pNvp->i2c_adapters[y].port == port) + { + break; + } + } + + if (y < MAX_I2C_ADAPTERS) + { + for (numDispId = 0; numDispId < MAX_DISP_ID_PER_ADAPTER; numDispId++) + { + if (pNvp->i2c_adapters[y].displayId[numDispId] == INVALID_DISP_ID) + { + pNvp->i2c_adapters[y].displayId[numDispId] = displayId; + break; + } + else + { + NV_PRINTF(LEVEL_INFO, + "%s: adapter already exists (port=0x%x, displayId=0x%x)\n", + __FUNCTION__, port, + pNvp->i2c_adapters[y].displayId[numDispId]); + } + } + + if (numDispId == MAX_DISP_ID_PER_ADAPTER) + { + NV_PRINTF(LEVEL_ERROR, + "%s: no more free display Id entries in adapter\n", + __FUNCTION__); + } + + return; + } + + if (free == MAX_I2C_ADAPTERS) + { + NV_PRINTF(LEVEL_ERROR, "%s: no more free adapter entries exist\n", + __FUNCTION__); + return; + } + + pNvp->i2c_adapters[free].pOsAdapter = nv_i2c_add_adapter(pNv, port); + pNvp->i2c_adapters[free].port = port; + // When port is added, numDispId will be 0. + pNvp->i2c_adapters[free].displayId[numDispId] = displayId; +} + +void RmI2cAddGpuPorts(nv_state_t * pNv) +{ + NvU32 x = 0; + nv_priv_t *pNvp = NV_GET_NV_PRIV(pNv); + RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); + NvU32 displayMask; + NV_STATUS status; + NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS systemGetSupportedParams = { 0 }; + + // Make displayId as Invalid. + for (x = 0; x < MAX_I2C_ADAPTERS; x++) + { + NvU32 numDispId; + + for (numDispId = 0; numDispId < MAX_DISP_ID_PER_ADAPTER; numDispId++) + { + pNvp->i2c_adapters[x].displayId[numDispId] = INVALID_DISP_ID; + } + } + + // First, set up the regular i2c adapters - one per i2c port + if (pNv->rmapi.hI2C != 0) + { + NV402C_CTRL_I2C_GET_PORT_INFO_PARAMS i2cPortInfoParams = { 0 }; + + status = pRmApi->Control(pRmApi, pNv->rmapi.hClient, pNv->rmapi.hI2C, + NV402C_CTRL_CMD_I2C_GET_PORT_INFO, + &i2cPortInfoParams, sizeof(i2cPortInfoParams)); + + if (status == NV_OK) + { + for (x = 0; x < NV_ARRAY_ELEMENTS(i2cPortInfoParams.info); x++) + { + // + // Check if this port is implemented and RM I2C framework has + // validated this port. Only limited amount of ports can + // be added to the OS framework. + // + if (FLD_TEST_DRF(402C_CTRL, _I2C_GET_PORT_INFO, _IMPLEMENTED, + _YES, i2cPortInfoParams.info[x]) && + FLD_TEST_DRF(402C_CTRL, _I2C_GET_PORT_INFO, _VALID, + _YES, i2cPortInfoParams.info[x])) + { + rm_i2c_add_adapter(pNv, x, 0); + } + } + } + } + + // + // Now set up the i2c-over-DpAux adapters - one per DP OD + // + // 1. Perform NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS RM control which + // will return the mask for all the display ID's. + // 2. Loop for all the display ID's and do + // NV0073_CTRL_CMD_SPECIFIC_OR_GET_INFO RM control call. For each + // output resource, check for the following requirements: + // a. It must be DisplayPort. + // b. It must be internal to the GPU (ie, not on the board) + // c. It must be directly connected to the physical connector (ie, no DP + // 1.2 multistream ODs). + // 3. Perform NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID RM control for + // getting the I2C port data. + // + // With these restrictions, we should only end up with at most one OD + // per DP connector. + // + + if (pNv->rmapi.hDisp == 0) + { + return; + } + + systemGetSupportedParams.subDeviceInstance = 0; + status = pRmApi->Control(pRmApi, pNv->rmapi.hClient, pNv->rmapi.hDisp, + NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED, + &systemGetSupportedParams, sizeof(systemGetSupportedParams)); + + if (status != NV_OK) + { + return; + } + + for (displayMask = systemGetSupportedParams.displayMask; + displayMask != 0; + displayMask &= ~LOWESTBIT(displayMask)) + { + NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS orInfoParams = { 0 }; + NvU32 displayId = LOWESTBIT(displayMask); + + orInfoParams.subDeviceInstance = 0; + orInfoParams.displayId = displayId; + + status = pRmApi->Control(pRmApi, pNv->rmapi.hClient, pNv->rmapi.hDisp, + NV0073_CTRL_CMD_SPECIFIC_OR_GET_INFO, + &orInfoParams, sizeof(orInfoParams)); + + if ((status == NV_OK) && + (orInfoParams.type == NV0073_CTRL_SPECIFIC_OR_TYPE_SOR) && + ((orInfoParams.protocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_A) || + (orInfoParams.protocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_B)) && + (orInfoParams.location == NV0073_CTRL_SPECIFIC_OR_LOCATION_CHIP) && + (!orInfoParams.bIsDispDynamic)) + { + NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS i2cPortIdParams = { 0 }; + + i2cPortIdParams.subDeviceInstance = 0; + i2cPortIdParams.displayId = displayId; + + status = pRmApi->Control(pRmApi, + pNv->rmapi.hClient, + pNv->rmapi.hDisp, + NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID, + &i2cPortIdParams, + sizeof(i2cPortIdParams)); + + if ((status == NV_OK) && + (i2cPortIdParams.ddcPortId != NV0073_CTRL_SPECIFIC_I2C_PORT_NONE)) + { + rm_i2c_add_adapter(pNv, i2cPortIdParams.ddcPortId - 1, displayId); + } + } + } +} + +void NV_API_CALL rm_i2c_remove_adapters( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + // + // Cycle through all adapter entries, and first remove the adapter + // from the list from the kernel, then remove the i2c adapter + // list once that is completed. This should only be used from exit + // module time. Otherwise it could fail to remove some of the + // kernel adapters and subsequent transfer requests would result + // in crashes. + // + NvU32 x = 0; + nv_priv_t *pNvp = NV_GET_NV_PRIV(pNv); + NvU32 numDispId; + + for (x = 0; x < MAX_I2C_ADAPTERS; x++) + { + if (pNvp->i2c_adapters[x].pOsAdapter != NULL) + { + nv_i2c_del_adapter(pNv, pNvp->i2c_adapters[x].pOsAdapter); + + pNvp->i2c_adapters[x].pOsAdapter = NULL; + pNvp->i2c_adapters[x].port = 0; + for (numDispId = 0; numDispId < MAX_DISP_ID_PER_ADAPTER; numDispId++) + { + pNvp->i2c_adapters[x].displayId[numDispId] = INVALID_DISP_ID; + } + } + } +} + +NvBool NV_API_CALL rm_i2c_is_smbus_capable( + nvidia_stack_t *sp, + nv_state_t *pNv, + void *pI2cAdapter +) +{ + THREAD_STATE_NODE threadState; + nv_priv_t *pNvp = NV_GET_NV_PRIV(pNv); + NV_STATUS rmStatus = NV_OK; + OBJGPU *pGpu = NULL; + NvBool unlock = NV_FALSE; + NvU32 x; + NvBool ret = NV_FALSE; + void *fp; + NvU32 numDispId = 0; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + if (pNvp->flags & NV_INIT_FLAG_PUBLIC_I2C) + { + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_I2C)) != NV_OK) + goto semafinish; + + unlock = NV_TRUE; + } + + pGpu = NV_GET_NV_PRIV_PGPU(pNv); + + if (!pGpu) + { + goto semafinish; + } + + for (x = 0; x < MAX_I2C_ADAPTERS; x++) + { + if (pNvp->i2c_adapters[x].pOsAdapter == pI2cAdapter) + { + break; + } + } + + if (x == MAX_I2C_ADAPTERS) + { + goto semafinish; + } + + // we do not support smbus functions on i2c-over-DPAUX + for (numDispId = 0; numDispId < MAX_DISP_ID_PER_ADAPTER; numDispId++) + { + if (pNvp->i2c_adapters[x].displayId[numDispId] == 0x0) + { + ret = NV_TRUE; + } + } + +semafinish: + if (unlock) + { + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return ret; +} + +NV_STATUS NV_API_CALL rm_perform_version_check( + nvidia_stack_t *sp, + void *pData, + NvU32 dataSize +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + rmStatus = RmPerformVersionCheck(pData, dataSize); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +// +// Handles the Power Source Change event(AC/DC) for Notebooks. +// Notebooks from Maxwell have only one Gpu, so this functions grabs first Gpu +// from GpuMgr and call subdevice RmControl. +// +void NV_API_CALL rm_power_source_change_event( + nvidia_stack_t *sp, + NvU32 event_val +) +{ + THREAD_STATE_NODE threadState; + void *fp; + nv_state_t *nv; + OBJGPU *pGpu = gpumgrGetGpu(0); + NV_STATUS rmStatus = NV_OK; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_EVENT)) == NV_OK) + { + if (pGpu != NULL) + { + nv = NV_GET_NV_STATE(pGpu); + if ((rmStatus = os_ref_dynamic_power(nv, NV_DYNAMIC_PM_FINE)) == + NV_OK) + { + // LOCK: acquire GPU lock + if ((rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_EVENT)) == + NV_OK) + { + rmStatus = RmPowerSourceChangeEvent(nv, event_val); + + // UNLOCK: release GPU lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + os_unref_dynamic_power(nv, NV_DYNAMIC_PM_FINE); + } + // UNLOCK: release API lock + rmapiLockRelease(); + } + } + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s: Failed to handle Power Source change event, status=0x%x\n", + __FUNCTION__, rmStatus); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NV_STATUS NV_API_CALL rm_p2p_dma_map_pages( + nvidia_stack_t *sp, + nv_dma_device_t *peer, + NvU8 *pGpuUuid, + NvU32 pageSize, + NvU32 pageCount, + NvU64 *pDmaAddresses, + void **ppPriv +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + if (ppPriv == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + *ppPriv = NULL; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) + { + OBJGPU *pGpu = gpumgrGetGpuFromUuid(pGpuUuid, + DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, _SHA1) | + DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _FORMAT, _BINARY)); + if (pGpu == NULL) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + } + else + { + NvU32 i; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) + { + NV_ASSERT(pageSize == os_page_size); + + rmStatus = nv_dma_map_alloc(peer, pageCount, pDmaAddresses, + NV_FALSE, ppPriv); + } + else + { + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + for (i = 0; i < pageCount; i++) + { + // Peer mappings through this API are always via BAR1 + rmStatus = nv_dma_map_peer(peer, nv->dma_dev, 0x1, + pageSize / os_page_size, + &pDmaAddresses[i]); + if ((rmStatus != NV_OK) && (i > 0)) + { + NvU32 j; + for (j = i - 1; j < pageCount; j--) + { + nv_dma_unmap_peer(peer, pageSize / os_page_size, + pDmaAddresses[j]); + } + } + } + } + } + + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_p2p_get_gpu_info( + nvidia_stack_t *sp, + NvU64 gpuVirtualAddress, + NvU64 length, + NvU8 **ppGpuUuid, + void **ppGpuInfo +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P); + if (rmStatus == NV_OK) + { + OBJGPU *pGpu; + rmStatus = RmP2PGetGpuByAddress(gpuVirtualAddress, + length, + &pGpu); + if (rmStatus == NV_OK) + { + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + const NvU8 *pGid; + + pGid = RmGetGpuUuidRaw(nv); + if (pGid == NULL) + { + rmStatus = NV_ERR_GPU_UUID_NOT_FOUND; + } + else + { + rmStatus = os_alloc_mem((void **)ppGpuUuid, GPU_UUID_LEN); + if (rmStatus == NV_OK) + { + os_mem_copy(*ppGpuUuid, pGid, GPU_UUID_LEN); + } + } + + *ppGpuInfo = (void *) pGpu; + } + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_p2p_get_pages_persistent( + nvidia_stack_t *sp, + NvU64 gpuVirtualAddress, + NvU64 length, + void **p2pObject, + NvU64 *pPhysicalAddresses, + NvU32 *pEntries, + void *pPlatformData, + void *pGpuInfo +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) + { + rmStatus = RmP2PGetPagesPersistent(gpuVirtualAddress, + length, + p2pObject, + pPhysicalAddresses, + pEntries, + pPlatformData, + pGpuInfo); + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_p2p_get_pages( + nvidia_stack_t *sp, + NvU64 p2pToken, + NvU32 vaSpaceToken, + NvU64 gpuVirtualAddress, + NvU64 length, + NvU64 *pPhysicalAddresses, + NvU32 *pWreqMbH, + NvU32 *pRreqMbH, + NvU32 *pEntries, + NvU8 **ppGpuUuid, + void *pPlatformData +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) + { + OBJGPU *pGpu; + rmStatus = RmP2PGetPagesWithoutCallbackRegistration(p2pToken, + vaSpaceToken, + gpuVirtualAddress, + length, + pPhysicalAddresses, + pWreqMbH, + pRreqMbH, + pEntries, + &pGpu, + pPlatformData); + if (rmStatus == NV_OK) + { + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + const NvU8 *pGid; + + pGid = RmGetGpuUuidRaw(nv); + if (pGid == NULL) + { + NV_ASSERT_OK(RmP2PPutPages(p2pToken, vaSpaceToken, + gpuVirtualAddress, + pPlatformData)); + rmStatus = NV_ERR_GENERIC; + } + else + { + rmStatus = os_alloc_mem((void **)ppGpuUuid, GPU_UUID_LEN); + if (rmStatus == NV_OK) + os_mem_copy(*ppGpuUuid, pGid, GPU_UUID_LEN); + } + } + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_p2p_register_callback( + nvidia_stack_t *sp, + NvU64 p2pToken, + NvU64 gpuVirtualAddress, + NvU64 length, + void *pPlatformData, + void (*pFreeCallback)(void *pData), + void *pData +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) + { + rmStatus = RmP2PRegisterCallback(p2pToken, gpuVirtualAddress, length, + pPlatformData, pFreeCallback, pData); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_p2p_put_pages_persistent( + nvidia_stack_t *sp, + void *p2pObject, + void *pKey +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) + { + rmStatus = RmP2PPutPagesPersistent(p2pObject, pKey); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_p2p_put_pages( + nvidia_stack_t *sp, + NvU64 p2pToken, + NvU32 vaSpaceToken, + NvU64 gpuVirtualAddress, + void *pKey +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) + { + rmStatus = RmP2PPutPages(p2pToken, + vaSpaceToken, + gpuVirtualAddress, + pKey); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +char* NV_API_CALL rm_get_gpu_uuid( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + NV_STATUS rmStatus; + const NvU8 *pGid; + char *pGidString; + + THREAD_STATE_NODE threadState; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // Allocate space for the ASCII string + rmStatus = os_alloc_mem((void **)&pGidString, GPU_UUID_ASCII_LEN); + if (rmStatus != NV_OK) + { + pGidString = NULL; + goto done; + } + + // Get the raw UUID; note the pGid is cached, so we do not need to free it + pGid = RmGetGpuUuidRaw(nv); + + if (pGid != NULL) + { + // Convert the raw UUID to ASCII + rmStatus = RmGpuUuidRawToString(pGid, pGidString, GPU_UUID_ASCII_LEN); + if (rmStatus != NV_OK) + { + os_free_mem(pGidString); + pGidString = NULL; + } + } + else + { + const char *pTmpString = "GPU-???????\?-???\?-???\?-???\?-????????????"; + + portStringCopy(pGidString, GPU_UUID_ASCII_LEN, pTmpString, + portStringLength(pTmpString) + 1); + } + +done: + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return pGidString; +} + +// +// This function will return the UUID in the binary format +// +const NvU8 * NV_API_CALL rm_get_gpu_uuid_raw( + nvidia_stack_t *sp, + nv_state_t *nv) +{ + THREAD_STATE_NODE threadState; + void *fp; + const NvU8 *pGid; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + pGid = RmGetGpuUuidRaw(nv); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return pGid; +} + +static void rm_set_firmware_logs( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + NV_STATUS status; + NvU32 data; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + status = RmReadRegistryDword(nv, NV_REG_ENABLE_GPU_FIRMWARE_LOGS, &data); + if (status == NV_OK) + { + if ((data == NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE) +#if defined(DEBUG) || defined(DEVELOP) + || (data == NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG) +#endif + ) + { + nv->enable_firmware_logs = NV_TRUE; + } + } + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +void NV_API_CALL rm_set_rm_firmware_requested( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + nv->request_firmware = NV_TRUE; + nv->allow_fallback_to_monolithic_rm = NV_FALSE; + + // Check if we want firmware logs + if (nv->request_firmware) + rm_set_firmware_logs(sp, nv); +} + +// +// This function will be called by nv_procfs_read_gpu_info(). +// nv_procfs_read_gpu_info() will not print the 'GPU Firmware:' field at +// all if the 'version' string is empty. +// +// If GSP is enabled (firmware was requested), this function needs to return +// the firmware version or "NA" in case of any errors. +// +// If GSP is not enabled (firmware was not requested), this function needs to +// return the empty string, regardless of error cases. +// +void NV_API_CALL rm_get_firmware_version( + nvidia_stack_t *sp, + nv_state_t *nv, + char *version, + NvLength version_length +) +{ + NV2080_CTRL_GSP_GET_FEATURES_PARAMS params = { 0 }; + RM_API *pRmApi; + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_OK; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + pRmApi = RmUnixRmApiPrologue(nv, &threadState, RM_LOCK_MODULES_GPU); + if (pRmApi != NULL) + { + rmStatus = pRmApi->Control(pRmApi, + nv->rmapi.hClient, + nv->rmapi.hSubDevice, + NV2080_CTRL_CMD_GSP_GET_FEATURES, + ¶ms, + sizeof(params)); + + RmUnixRmApiEpilogue(nv, &threadState); + } + else + { + rmStatus = NV_ERR_INVALID_STATE; + } + + if (rmStatus != NV_OK) + { + if (RMCFG_FEATURE_GSP_CLIENT_RM && nv->request_firmware) + { + const char *pTmpString = "N/A"; + portStringCopy(version, version_length, pTmpString, portStringLength(pTmpString) + 1); + } + NV_PRINTF(LEVEL_INFO, + "%s: Failed to query gpu build versions, status=0x%x\n", + __FUNCTION__, + rmStatus); + goto finish; + } + portMemCopy(version, version_length, params.firmwareVersion, sizeof(params.firmwareVersion)); + +finish: + NV_EXIT_RM_RUNTIME(sp,fp); +} + +// +// disable GPU SW state persistence +// + +void NV_API_CALL rm_disable_gpu_state_persistence(nvidia_stack_t *sp, nv_state_t *nv) +{ + THREAD_STATE_NODE threadState; + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + pGpu->setProperty(pGpu, PDB_PROP_GPU_PERSISTENT_SW_STATE, NV_FALSE); + osModifyGpuSwStatePersistence(pGpu->pOsGpuInfo, NV_FALSE); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NV_STATUS NV_API_CALL rm_log_gpu_crash( + nv_stack_t *sp, + nv_state_t *nv +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS status; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + if ((status = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DIAG)) == NV_OK) + { + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + + if ((pGpu != NULL) && + ((status = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DIAG)) == NV_OK)) + { + status = RmLogGpuCrash(pGpu); + + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return status; +} + +void NV_API_CALL rm_kernel_rmapi_op(nvidia_stack_t *sp, void *ops_cmd) +{ + nvidia_kernel_rmapi_ops_t *ops = ops_cmd; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + switch (ops->op) + { + case NV01_FREE: + Nv01FreeKernel(&ops->params.free); + break; + + case NV01_ALLOC_MEMORY: + Nv01AllocMemoryKernel(&ops->params.allocMemory64); + break; + + case NV04_ALLOC: + Nv04AllocKernel(&ops->params.alloc); + break; + + case NV04_VID_HEAP_CONTROL: + Nv04VidHeapControlKernel(ops->params.pVidHeapControl); + break; + + case NV04_MAP_MEMORY: + Nv04MapMemoryKernel(&ops->params.mapMemory); + break; + + case NV04_UNMAP_MEMORY: + Nv04UnmapMemoryKernel(&ops->params.unmapMemory); + break; + + case NV04_ALLOC_CONTEXT_DMA: + Nv04AllocContextDmaKernel(&ops->params.allocContextDma2); + break; + + case NV04_MAP_MEMORY_DMA: + Nv04MapMemoryDmaKernel(&ops->params.mapMemoryDma); + break; + + case NV04_UNMAP_MEMORY_DMA: + Nv04UnmapMemoryDmaKernel(&ops->params.unmapMemoryDma); + break; + + case NV04_BIND_CONTEXT_DMA: + Nv04BindContextDmaKernel(&ops->params.bindContextDma); + break; + + case NV04_CONTROL: + Nv04ControlKernel(&ops->params.control); + break; + + case NV04_DUP_OBJECT: + Nv04DupObjectKernel(&ops->params.dupObject); + break; + + case NV04_SHARE: + Nv04ShareKernel(&ops->params.share); + break; + + case NV04_ADD_VBLANK_CALLBACK: + Nv04AddVblankCallbackKernel(&ops->params.addVblankCallback); + break; + } + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +// +// ACPI method (NVIF/_DSM/WMMX/MXM*/etc.) initialization +// +void RmInitAcpiMethods(OBJOS *pOS, OBJSYS *pSys, OBJGPU *pGpu) +{ + NvU32 handlesPresent; + + if (pSys->getProperty(pSys, PDB_PROP_SYS_NVIF_INIT_DONE)) + return; + + nv_acpi_methods_init(&handlesPresent); + + // Check if NVPCF _DSM functions are implemented under NVPCF or GPU device scope. + RmCheckNvpcfDsmScope(pGpu); + acpiDsmInit(pGpu); + +} + +// +// ACPI method (NVIF/_DSM/WMMX/MXM*/etc.) teardown +// +void RmUnInitAcpiMethods(OBJSYS *pSys) +{ + pSys->setProperty(pSys, PDB_PROP_SYS_NVIF_INIT_DONE, NV_FALSE); + + nv_acpi_methods_uninit(); +} + +// +// Converts an array of OS page address to an array of RM page addresses.This +// assumes that: +// (1) The pteArray is at least pageCount entries large, +// (2) The pageCount is given in RM pages, and +// (3) The OS page entries start at index 0. +// +void RmInflateOsToRmPageArray(RmPhysAddr *pteArray, NvU64 pageCount) +{ + NvUPtr osPageIdx, osPageOffset; + NvU64 i; + + // + // We can do the translation in place by moving backwards, since there + // will always be more RM pages than OS pages + // + for (i = pageCount - 1; i != NV_U64_MAX; i--) + { + osPageIdx = i >> NV_RM_TO_OS_PAGE_SHIFT; + osPageOffset = (i & ((1 << NV_RM_TO_OS_PAGE_SHIFT) - 1)) * + NV_RM_PAGE_SIZE; + pteArray[i] = pteArray[osPageIdx] + osPageOffset; + } +} + +void RmDeflateRmToOsPageArray(RmPhysAddr *pteArray, NvU64 pageCount) +{ + NvU64 i; + + for (i = 0; i < NV_RM_PAGES_TO_OS_PAGES(pageCount); i++) + { + pteArray[i] = pteArray[(i << NV_RM_TO_OS_PAGE_SHIFT)]; + } + + // Zero out the rest of the addresses, which are now invalid + portMemSet(pteArray + i, 0, sizeof(*pteArray) * (pageCount - i)); +} + +NvBool NV_API_CALL +rm_get_device_remove_flag +( + nvidia_stack_t * sp, + NvU32 gpu_id +) +{ + THREAD_STATE_NODE threadState; + void *fp; + NvBool bRemove; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + if (gpumgrQueryGpuDrainState(gpu_id, NULL, &bRemove) != NV_OK) + { + bRemove = NV_FALSE; + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + return bRemove; +} + +NvBool NV_API_CALL +rm_gpu_need_4k_page_isolation +( + nv_state_t *nv +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + return nvp->b_4k_page_isolation_required; +} + +NV_STATUS NV_API_CALL rm_get_gpu_numa_info( + nvidia_stack_t *sp, + nv_state_t *nv, + NvS32 *pNid, + NvU64 *pNumaMemAddr, + NvU64 *pNumaMemSize, + NvU64 *pOfflineAddresses, + NvU32 *pOfflineAddressesCount +) +{ + NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS *pParams; + RM_API *pRmApi; + THREAD_STATE_NODE threadState; + void *fp; + NV_STATUS status = NV_OK; + + if ((pNid == NULL) || (pNumaMemAddr == NULL) || (pNumaMemSize == NULL)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if ((pOfflineAddressesCount != NULL) && + ((pOfflineAddresses == NULL) || + (*pOfflineAddressesCount > NV_ARRAY_ELEMENTS(pParams->numaOfflineAddresses)))) + { + return NV_ERR_INVALID_ARGUMENT; + } + + NV_ENTER_RM_RUNTIME(sp,fp); + + pParams = portMemAllocNonPaged(sizeof(*pParams)); + if (pParams == NULL) + { + NV_EXIT_RM_RUNTIME(sp,fp); + return NV_ERR_NO_MEMORY; + } + + portMemSet(pParams, 0, sizeof(*pParams)); + + if (pOfflineAddressesCount != NULL) + { + pParams->numaOfflineAddressesCount = *pOfflineAddressesCount; + } + + pRmApi = RmUnixRmApiPrologue(nv, &threadState, RM_LOCK_MODULES_MEM); + if (pRmApi == NULL) + { + status = NV_ERR_INVALID_STATE; + goto finish; + } + + status = pRmApi->Control(pRmApi, nv->rmapi.hClient, nv->rmapi.hSubDevice, + NV2080_CTRL_CMD_FB_GET_NUMA_INFO, + pParams, sizeof(*pParams)); + + RmUnixRmApiEpilogue(nv, &threadState); + + if (status == NV_OK) + { + NvU32 i; + + *pNid = pParams->numaNodeId; + *pNumaMemAddr = pParams->numaMemAddr; + *pNumaMemSize = pParams->numaMemSize; + *pOfflineAddressesCount = pParams->numaOfflineAddressesCount; + + for (i = 0; i < pParams->numaOfflineAddressesCount; i++) + { + pOfflineAddresses[i] = pParams->numaOfflineAddresses[i]; + } + } + +finish: + portMemFree(pParams); + + NV_EXIT_RM_RUNTIME(sp,fp); + + return status; +} + +NV_STATUS NV_API_CALL rm_gpu_numa_online( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS params = { 0 }; + RM_API *pRmApi; + THREAD_STATE_NODE threadState; + void *fp; + NV_STATUS status = NV_OK; + + NV_ENTER_RM_RUNTIME(sp,fp); + + pRmApi = RmUnixRmApiPrologue(nv, &threadState, RM_LOCK_MODULES_MEM); + if (pRmApi == NULL) + { + status = NV_ERR_INVALID_STATE; + goto finish; + } + + params.bOnline = NV_TRUE; + + status = pRmApi->Control(pRmApi, nv->rmapi.hClient, nv->rmapi.hSubDevice, + NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS, + ¶ms, sizeof(params)); + + RmUnixRmApiEpilogue(nv, &threadState); + +finish: + NV_EXIT_RM_RUNTIME(sp,fp); + + return status; +} + + +NV_STATUS NV_API_CALL rm_gpu_numa_offline( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS params = { 0 }; + RM_API *pRmApi; + THREAD_STATE_NODE threadState; + void *fp; + NV_STATUS status = NV_OK; + + NV_ENTER_RM_RUNTIME(sp,fp); + + pRmApi = RmUnixRmApiPrologue(nv, &threadState, RM_LOCK_MODULES_MEM); + if (pRmApi == NULL) + { + status = NV_ERR_INVALID_STATE; + goto finish; + } + + params.bOnline = NV_FALSE; + + status = pRmApi->Control(pRmApi, nv->rmapi.hClient, + nv->rmapi.hSubDevice, + NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS, + ¶ms, sizeof(params)); + + RmUnixRmApiEpilogue(nv, &threadState); + +finish: + NV_EXIT_RM_RUNTIME(sp,fp); + + return status; +} + +// +// A device is considered "sequestered" if it has drain state enabled for it. +// The kernel interface layer can use this to check the drain state of a device +// in paths outside of initialization, e.g., when clients attempt to reference +// count the device. +// +NvBool NV_API_CALL rm_is_device_sequestered( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + THREAD_STATE_NODE threadState; + void *fp; + NvBool bDrain = NV_FALSE; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + if (rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU) == NV_OK) + { + // + // If gpumgrQueryGpuDrainState succeeds, bDrain will be set as needed. + // If gpumgrQueryGpuDrainState fails, bDrain will stay false; we assume + // that if core RM can't tell us the drain state, it must not be + // attached and the "sequestered" question is not relevant. + // + (void) gpumgrQueryGpuDrainState(pNv->gpu_id, &bDrain, NULL); + + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + return bDrain; +} + +void NV_API_CALL rm_check_for_gpu_surprise_removal( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + THREAD_STATE_NODE threadState; + void *fp; + NV_STATUS rmStatus; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock. + if ((rmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU)) == NV_OK) + { + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + + if ((rmStatus = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_GPU)) == NV_OK) + { + osHandleGpuLost(pGpu); + rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); + } + + // UNLOCK: release api lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NV_STATUS NV_API_CALL rm_set_external_kernel_client_count( + nvidia_stack_t *sp, + nv_state_t *pNv, + NvBool bIncr +) +{ + THREAD_STATE_NODE threadState; + void *fp; + OBJGPU *pGpu; + NV_STATUS rmStatus = NV_OK; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + pGpu = NV_GET_NV_PRIV_PGPU(pNv); + + if (pGpu != NULL) + { + rmStatus = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_GPU); + if (rmStatus == NV_OK) + { + rmStatus = gpuSetExternalKernelClientCount(pGpu, bIncr); + rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); + } + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NvBool rm_get_uefi_console_status( + nv_state_t *nv +) +{ + NvU16 fbWidth, fbHeight, fbDepth, fbPitch; + NvU64 fbSize; + NvU64 fbBaseAddress = 0; + NvBool bConsoleDevice = NV_FALSE; + + // os_get_screen_info() will return dimensions and an address for + // any fbdev driver (e.g., efifb, vesafb, etc). To find if this is a + // UEFI console check the fbBaseAddress: if it was set up by the EFI GOP + // driver, it will point into BAR1 (FB); if it was set up by the VBIOS, + // it will point to BAR2 + 16MB. + os_get_screen_info(&fbBaseAddress, &fbWidth, &fbHeight, &fbDepth, &fbPitch, + nv->bars[NV_GPU_BAR_INDEX_FB].cpu_address, + nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000); + + fbSize = fbHeight * fbPitch; + + bConsoleDevice = (fbSize != 0); + + return bConsoleDevice; +} + +NvU64 rm_get_uefi_console_size( + nv_state_t *nv, + NvU64 *pFbBaseAddress +) +{ + NvU16 fbWidth, fbHeight, fbDepth, fbPitch; + NvU64 fbSize; + + fbSize = fbWidth = fbHeight = fbDepth = fbPitch = 0; + + // os_get_screen_info() will return dimensions and an address for + // any fbdev driver (e.g., efifb, vesafb, etc). To find if this is a + // UEFI console check the fbBaseAddress: if it was set up by the EFI GOP + // driver, it will point into BAR1 (FB); if it was set up by the VBIOS, + // it will point to BAR2 + 16MB. + os_get_screen_info(pFbBaseAddress, &fbWidth, &fbHeight, &fbDepth, &fbPitch, + nv->bars[NV_GPU_BAR_INDEX_FB].cpu_address, + nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000); + + fbSize = fbHeight * fbPitch; + + return fbSize; +} + +/* + * IOMMU needs to be present on the server to support SR-IOV vGPU, unless + * we have SR-IOV enabled for remote GPU. + */ + +NvBool NV_API_CALL rm_is_iommu_needed_for_sriov( + nvidia_stack_t *sp, + nv_state_t * nv +) +{ + OBJGPU *pGpu; + NvU32 data; + NvBool ret = NV_TRUE; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + pGpu = NV_GET_NV_PRIV_PGPU(nv); + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_REMOTE_GPU, &data) == NV_OK) + { + if (data == NV_REG_STR_RM_REMOTE_GPU_ENABLE) + ret = NV_FALSE; + } + + NV_EXIT_RM_RUNTIME(sp,fp); + + return ret; +} + +NvBool NV_API_CALL rm_disable_iomap_wc(void) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + return pSys->pCl->getProperty(pSys, PDB_PROP_CL_DISABLE_IOMAP_WC) == NV_TRUE; +} + +// +// Verifies the handle, offset and size and dups hMemory. +// Must be called with API lock and GPU lock held. +// +NV_STATUS NV_API_CALL rm_dma_buf_dup_mem_handle( + nvidia_stack_t *sp, + nv_state_t *nv, + NvHandle hSrcClient, + NvHandle hDstClient, + NvHandle hDevice, + NvHandle hSubdevice, + void *pGpuInstanceInfo, + NvHandle hMemory, + NvU64 offset, + NvU64 size, + NvHandle *phMemoryDuped +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + OBJGPU *pGpu; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + pGpu = NV_GET_NV_PRIV_PGPU(nv); + + NV_ASSERT(rmapiLockIsOwner()); + + NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); + + rmStatus = RmDmabufVerifyMemHandle(pGpu, hSrcClient, hMemory, + offset, size, pGpuInstanceInfo); + if (rmStatus == NV_OK) + { + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NvHandle hMemoryDuped = 0; + + rmStatus = pRmApi->DupObject(pRmApi, + hDstClient, + hDevice, + &hMemoryDuped, + hSrcClient, + hMemory, + 0); + if (rmStatus == NV_OK) + { + *phMemoryDuped = hMemoryDuped; + } + else if (rmStatus == NV_ERR_INVALID_OBJECT_PARENT) + { + hMemoryDuped = 0; + + // If duping under Device fails, try duping under Subdevice + rmStatus = pRmApi->DupObject(pRmApi, + hDstClient, + hSubdevice, + &hMemoryDuped, + hSrcClient, + hMemory, + 0); + if (rmStatus == NV_OK) + { + *phMemoryDuped = hMemoryDuped; + } + } + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +// +// Frees dup'd hMemory. +// Must be called with API lock and GPU lock held. +// +void NV_API_CALL rm_dma_buf_undup_mem_handle( + nvidia_stack_t *sp, + nv_state_t *nv, + NvHandle hClient, + NvHandle hMemory +) +{ + THREAD_STATE_NODE threadState; + RM_API *pRmApi; + OBJGPU *pGpu; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + pGpu = NV_GET_NV_PRIV_PGPU(nv); + + NV_ASSERT(rmapiLockIsOwner()); + + NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); + + pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + pRmApi->Free(pRmApi, hClient, hMemory); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +// +// Maps a handle to BAR1. +// Must be called with API lock and GPU lock held. +// +NV_STATUS NV_API_CALL rm_dma_buf_map_mem_handle( + nvidia_stack_t *sp, + nv_state_t *nv, + NvHandle hClient, + NvHandle hMemory, + NvU64 offset, + NvU64 size, + NvU64 *pBar1Va +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + OBJGPU *pGpu; + KernelBus *pKernelBus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + pGpu = NV_GET_NV_PRIV_PGPU(nv); + pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + + NV_ASSERT(rmapiLockIsOwner()); + + NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); + + rmStatus = kbusMapFbApertureByHandle(pGpu, pKernelBus, hClient, + hMemory, offset, size, pBar1Va); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +// +// Unmaps a handle from BAR1. +// Must be called with API lock and GPU lock held. +// +NV_STATUS NV_API_CALL rm_dma_buf_unmap_mem_handle( + nvidia_stack_t *sp, + nv_state_t *nv, + NvHandle hClient, + NvHandle hMemory, + NvU64 size, + NvU64 bar1Va +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + OBJGPU *pGpu; + KernelBus *pKernelBus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + pGpu = NV_GET_NV_PRIV_PGPU(nv); + pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + + NV_ASSERT(rmapiLockIsOwner()); + + NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); + + rmStatus = kbusUnmapFbApertureByHandle(pGpu, pKernelBus, hClient, + hMemory, bar1Va); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device( + nvidia_stack_t *sp, + nv_state_t *nv, + NvHandle hClient, + NvHandle *phClient, + NvHandle *phDevice, + NvHandle *phSubdevice, + void **ppGpuInstanceInfo +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI); + if (rmStatus == NV_OK) + { + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + + rmStatus = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI); + if (rmStatus == NV_OK) + { + rmStatus = RmDmabufGetClientAndDevice(pGpu, hClient, phClient, phDevice, + phSubdevice, ppGpuInstanceInfo); + + rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); + } + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +void NV_API_CALL rm_dma_buf_put_client_and_device( + nvidia_stack_t *sp, + nv_state_t *nv, + NvHandle hClient, + NvHandle hDevice, + NvHandle hSubdevice, + void *pGpuInstanceInfo +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI); + if (rmStatus == NV_OK) + { + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + + rmStatus = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI); + if (rmStatus == NV_OK) + { + RmDmabufPutClientAndDevice(pGpu, hClient, hDevice, hSubdevice, + pGpuInstanceInfo); + + rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); + } + + // UNLOCK: release API lock + rmapiLockRelease(); + } + NV_ASSERT_OK(rmStatus); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +// +// Fetches GSP ucode data for usage during RM Init +// NOTE: Used only on VMWware +// + +NvBool NV_API_CALL rm_is_altstack_in_use(void) +{ +#if defined(__use_altstack__) + return NV_TRUE; +#else + return NV_FALSE; +#endif +} diff --git a/userspace/sdks/nv525/nvalloc/unix/src/osinit.c b/userspace/sdks/nv525/nvalloc/unix/src/osinit.c new file mode 100644 index 0000000..5080e50 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/src/osinit.c @@ -0,0 +1,2202 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/************************************************************************************************************** +* +* Description: +* UNIX-general, device-independent initialization code for +* the resource manager. +* +* +**************************************************************************************************************/ + +#include +#include // NV device driver interface +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "gpu/gpu.h" +#include +#include "gpu/bus/kern_bus.h" +#include "nverror.h" +#include +#include +#include +#include +#include "kernel/gpu/intr/intr.h" +#include +#include +#include +#include +#include +#include +#include +#include "liblogdecode.h" +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "platform/nbsi/nbsi_read.h" +#include "gpu_mgr/gpu_db.h" +#include +#include +#include +#include + +#include +// RMCONFIG: need definition of REGISTER_ALL_HALS() +#include "g_hal_register.h" + +typedef enum +{ + RM_INIT_OK, + + /* general os errors */ + RM_INIT_REG_SETUP_FAILED = 0x10, + RM_INIT_SYS_ENVIRONMENT_FAILED, + + /* gpu errors */ + RM_INIT_GPU_GPUMGR_ALLOC_GPU_FAILED = 0x20, + RM_INIT_GPU_GPUMGR_CREATE_DEV_FAILED, + RM_INIT_GPU_GPUMGR_ATTACH_GPU_FAILED, + RM_INIT_GPU_PRE_INIT_FAILED, + RM_INIT_GPU_STATE_INIT_FAILED, + RM_INIT_GPU_LOAD_FAILED, + RM_INIT_GPU_UNIVERSAL_VALIDATION_FAILED, + RM_INIT_GPU_DMA_CONFIGURATION_FAILED, + + /* vbios errors */ + RM_INIT_VBIOS_FAILED = 0x30, + RM_INIT_VBIOS_POST_FAILED, + RM_INIT_VBIOS_X86EMU_FAILED, + + /* scalability errors */ + RM_INIT_SCALABILITY_FAILED = 0x40, + + /* general core rm errors */ + RM_INIT_WATCHDOG_FAILED, + RM_FIFO_GET_UD_BAR1_MAP_INFO_FAILED, + RM_GPUDB_REGISTER_FAILED, + + RM_INIT_ALLOC_RMAPI_FAILED, + RM_INIT_GPUINFO_WITH_RMAPI_FAILED, + + /* rm firmware errors */ + RM_INIT_FIRMWARE_POLICY_FAILED = 0x60, + RM_INIT_FIRMWARE_FETCH_FAILED, + RM_INIT_FIRMWARE_INIT_FAILED, + + RM_INIT_MAX_FAILURES +} rm_init_status; + +typedef rm_init_status RM_INIT_STATUS; + +typedef struct { + RM_INIT_STATUS initStatus; + NV_STATUS rmStatus; + NvU32 line; +} UNIX_STATUS; + +#define INIT_UNIX_STATUS { RM_INIT_OK, NV_OK, 0 } +#define RM_INIT_SUCCESS(init) ((init) == RM_INIT_OK) + +#define RM_SET_ERROR(status, err) { (status).initStatus = (err); \ + (status).line = __LINE__; } + + +// +// GPU architectures support DMA addressing up to a certain address width, +// above which all other bits in any given DMA address must not vary +// (e.g., all 0). This value is the minimum of the DMA addressing +// capabilities, in number of physical address bits, for all supported +// GPU architectures. +// +#define NV_GPU_MIN_SUPPORTED_DMA_ADDR_WIDTH 36 + +// +// All GPU architectures with GSP support at least 47 physical address bits. +// +#define NV_GSP_GPU_MIN_SUPPORTED_DMA_ADDR_WIDTH 47 + +static inline NvU64 nv_encode_pci_info(nv_pci_info_t *pci_info) +{ + return gpuEncodeDomainBusDevice(pci_info->domain, pci_info->bus, pci_info->slot); +} + +static inline NvU32 nv_generate_id_from_pci_info(nv_pci_info_t *pci_info) +{ + return gpuGenerate32BitId(pci_info->domain, pci_info->bus, pci_info->slot); +} + +static inline void nv_os_map_kernel_space(nv_state_t *nv, nv_aperture_t *aperture) +{ + NV_ASSERT(aperture->map == NULL); + + // let's start off assuming a standard device and map the registers + // normally. It is unfortunate to hard-code the register size here, but we don't + // want to fail trying to map all of a multi-devices' register space + aperture->map = osMapKernelSpace(aperture->cpu_address, + aperture->size, + NV_MEMORY_UNCACHED, + NV_PROTECT_READ_WRITE); + aperture->map_u = (nv_phwreg_t)aperture->map; +} + +// local prototypes +static NV_STATUS initCoreLogic(OBJGPU *); +static void initVendorSpecificRegistry(OBJGPU *, NvU16); +static NV_STATUS teardownCoreLogic(OBJOS *, OBJGPU *); +static void initUnixSpecificRegistry(OBJGPU *); + +NvBool osRmInitRm(OBJOS *pOS) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + NvU64 system_memory_size = (NvU64)-1; + + NV_PRINTF(LEVEL_INFO, "init rm\n"); + + if (os_is_efi_enabled()) + { + pSys->setProperty(pSys, PDB_PROP_SYS_IS_UEFI, NV_TRUE); + } + + // have to init this before the debug subsystem, which will + // try to check the value of ResmanDebugLevel + RmInitRegistry(); + + NvU32 data = 0; + if ((osReadRegistryDword(NULL, + NV_REG_ENABLE_PCIE_GEN3, &data) == NV_OK) && + (data != 0)) + { + data = DRF_DEF(_REG_STR, _RM_PCIE, _LINK_SPEED_ALLOW_GEN3, _ENABLE); + + osWriteRegistryDword(NULL, + NV_REG_STR_RM_PCIE_LINK_SPEED, data); + } + + if (!(osReadRegistryDword(NULL, + NV_REG_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS, + &data) == NV_OK) || data) + { + pSys->setProperty(pSys, + PDB_PROP_SYS_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS, + NV_TRUE); + } + + if ((osReadRegistryDword(NULL, + NV_REG_ENABLE_STREAM_MEMOPS, + &data) == NV_OK) && (data != 0)) + { + data = DRF_DEF(_REG_STR, _RM_STREAM_MEMOPS, _ENABLE, _YES); + osWriteRegistryDword(NULL, NV_REG_STR_RM_STREAM_MEMOPS, data); + } + + if ((osReadRegistryDword(NULL, + NV_REG_STR_RM_FORCE_BAR_PATH, + &data) == NV_OK) && (data == 1)) + { + // + // Exposing the GPU memory as NUMA node memory requires coherent CPU + // mappings over NVLink. If those mappings are disabled, also disable + // NUMA-onlining of the device memory. + // + osWriteRegistryDword(NULL, + NV_REG_ENABLE_USER_NUMA_MANAGEMENT, 0); + } + + if ((osReadRegistryDword(NULL, + NV_REG_NVLINK_DISABLE, &data) == NV_OK) && + (data == 1)) + { + osWriteRegistryDword(NULL, NV_REG_STR_RM_NVLINK_CONTROL, 0x1); + } + + if ((osReadRegistryDword(NULL, + NV_REG_ENABLE_PCIE_RELAXED_ORDERING_MODE, &data) == NV_OK) && + (data == 1)) + { + osWriteRegistryDword(NULL, + NV_REG_STR_RM_SET_PCIE_TLP_RELAXED_ORDERING, + NV_REG_STR_RM_SET_PCIE_TLP_RELAXED_ORDERING_ENABLE); + } + + // init the debug subsystem if necessary + os_dbg_init(); + nvDbgInitRmMsg(NULL); + + // Force nvlog reinit since module params are now available + NVLOG_UPDATE(); + + // Register all supported hals + if (REGISTER_ALL_HALS() != NV_OK) + { + RmDestroyRegistry(NULL); + return NV_FALSE; + } + + system_memory_size = NV_RM_PAGES_PER_OS_PAGE * os_get_num_phys_pages(); + + // if known, relay the number of system memory pages (in terms of RM page + // size) to the RM; this is needed for e.g. TurboCache parts. + if (system_memory_size != (NvU64)-1) + pOS->SystemMemorySize = system_memory_size; + + // Setup any ThreadState defaults + threadStateInitSetupFlags(THREAD_STATE_SETUP_FLAGS_ENABLED | + THREAD_STATE_SETUP_FLAGS_TIMEOUT_ENABLED | + THREAD_STATE_SETUP_FLAGS_SLI_LOGIC_ENABLED | + THREAD_STATE_SETUP_FLAGS_DO_NOT_INCLUDE_SLEEP_TIME_ENABLED); + + return NV_TRUE; +} + +void RmShutdownRm(void) +{ + NV_PRINTF(LEVEL_INFO, "shutdown rm\n"); + + RmDestroyRegistry(NULL); + + // Free objects created with RmInitRm, including the system object + RmDestroyRm(); +} + +// +// osAttachGpu +// +// This routine is used as a callback by the gpumgrAttachGpu +// interface to allow os-dependent code to set up any state +// before engine construction begins. +// +NV_STATUS osAttachGpu( + OBJGPU *pGpu, + void *pOsGpuInfo +) +{ + nv_state_t *nv = (nv_state_t *)pOsGpuInfo; + nv_priv_t *nvp; + + nvp = NV_GET_NV_PRIV(nv); + + nvp->pGpu = pGpu; + + NV_SET_NV_STATE(pGpu, (void *)nv); + + initUnixSpecificRegistry(pGpu); + + // Assign default values to Registry keys for VGX + if (os_is_vgx_hyper()) + { + initVGXSpecificRegistry(pGpu); + } + + return NV_OK; +} + +NV_STATUS osDpcAttachGpu( + OBJGPU *pGpu, + void *pOsGpuInfo +) +{ + return NV_OK; // Nothing to do for unix +} + +void osDpcDetachGpu( + OBJGPU *pGpu +) +{ + return; // Nothing to do for unix +} + +NV_STATUS +osHandleGpuLost +( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvU32 pmc_boot_0; + + // Determine if we've already run the handler + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_CONNECTED)) + { + return NV_OK; + } + + pmc_boot_0 = NV_PRIV_REG_RD32(nv->regs->map_u, NV_PMC_BOOT_0); + if (pmc_boot_0 != nvp->pmc_boot_0) + { + // + // This doesn't support PEX Reset and Recovery yet. + // This will help to prevent accessing registers of a GPU + // which has fallen off the bus. + // + nvErrorLog_va((void *)pGpu, ROBUST_CHANNEL_GPU_HAS_FALLEN_OFF_THE_BUS, + "GPU has fallen off the bus."); + + NV_DEV_PRINTF(NV_DBG_ERRORS, nv, "GPU has fallen off the bus.\n"); + + if (pGpu->boardInfo != NULL && pGpu->boardInfo->serialNumber[0] != '\0') + { + NV_DEV_PRINTF(NV_DBG_ERRORS, nv, + "GPU serial number is %s.\n", + pGpu->boardInfo->serialNumber); + } + + gpuSetDisconnectedProperties(pGpu); + + // Trigger the OS's PCI recovery mechanism + if (nv_pci_trigger_recovery(nv) != NV_OK) + { + // + // Initiate a crash dump immediately, since the OS doesn't appear + // to have a mechanism wired up for attempted recovery. + // + (void) RmLogGpuCrash(pGpu); + } + else + { + // + // Make the SW state stick around until the recovery can start, but + // don't change the PDB property: this is only used to report to + // clients whether or not persistence mode is enabled, and we'll + // need it after the recovery callbacks to restore the correct + // persistence mode for the GPU. + // + osModifyGpuSwStatePersistence(pGpu->pOsGpuInfo, NV_TRUE); + } + + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + // Set SURPRISE_REMOVAL flag for eGPU to help in device removal. + if ((pCl != NULL) && + pCl->getProperty(pCl, PDB_PROP_CL_IS_EXTERNAL_GPU)) + { + nv->flags |= NV_FLAG_IN_SURPRISE_REMOVAL; + } + DBG_BREAKPOINT(); + } + + return NV_OK; +} + +/* + * Initialize the required GPU information by doing RMAPI control calls + * and store the same in the UNIX specific data structures. + */ +static NV_STATUS +RmInitGpuInfoWithRmApi +( + OBJGPU *pGpu +) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pGpuInfoParams = { 0 }; + NV_STATUS status; + + // LOCK: acquire GPUs lock + status = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_INIT); + if (status != NV_OK) + { + return status; + } + + pGpuInfoParams = portMemAllocNonPaged(sizeof(*pGpuInfoParams)); + if (pGpuInfoParams == NULL) + { + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + + return NV_ERR_NO_MEMORY; + } + + + portMemSet(pGpuInfoParams, 0, sizeof(*pGpuInfoParams)); + + pGpuInfoParams->gpuInfoListSize = 3; + pGpuInfoParams->gpuInfoList[0].index = NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED; + pGpuInfoParams->gpuInfoList[1].index = NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED; + pGpuInfoParams->gpuInfoList[2].index = NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY; + + status = pRmApi->Control(pRmApi, nv->rmapi.hClient, + nv->rmapi.hSubDevice, + NV2080_CTRL_CMD_GPU_GET_INFO_V2, + pGpuInfoParams, sizeof(*pGpuInfoParams)); + + if (status == NV_OK) + { + nvp->b_4k_page_isolation_required = + (pGpuInfoParams->gpuInfoList[0].data == + NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_YES); + nvp->b_mobile_config_enabled = + (pGpuInfoParams->gpuInfoList[1].data == + NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_YES); + nv->dma_buf_supported = + (pGpuInfoParams->gpuInfoList[2].data == + NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES); + } + + portMemFree(pGpuInfoParams); + + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + + return status; +} + +static void RmSetSocDispDeviceMappings( + GPUATTACHARG *gpuAttachArg, + nv_state_t *nv +) +{ + gpuAttachArg->socDeviceArgs.deviceMapping[SOC_DEV_MAPPING_DISP].gpuNvAddr = (GPUHWREG*) nv->regs->map; + gpuAttachArg->socDeviceArgs.deviceMapping[SOC_DEV_MAPPING_DISP].gpuNvPAddr = nv->regs->cpu_address; + gpuAttachArg->socDeviceArgs.deviceMapping[SOC_DEV_MAPPING_DISP].gpuNvLength = (NvU32) nv->regs->size; +} + +static void RmSetSocDpauxDeviceMappings( + GPUATTACHARG *gpuAttachArg, + nv_state_t *nv +) +{ +} + +static void RmSetSocHdacodecDeviceMappings( + GPUATTACHARG *gpuAttachArg, + nv_state_t *nv +) +{ +} + +static void RmSetSocMipiCalDeviceMappings( + GPUATTACHARG *gpuAttachArg, + nv_state_t *nv +) +{ +} + +static void +osInitNvMapping( + nv_state_t *nv, + NvU32 *pDeviceReference, + UNIX_STATUS *status +) +{ + OBJGPU *pGpu; + OBJSYS *pSys = SYS_GET_INSTANCE(); + GPUATTACHARG *gpuAttachArg; + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvU32 deviceInstance; + NvU32 data = 0; + + NV_PRINTF(LEVEL_INFO, "osInitNvMapping:\n"); + + // allocate the next available gpu device number + status->rmStatus = gpumgrAllocGpuInstance(pDeviceReference); + if (status->rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "*** Cannot get valid gpu instance\n"); + RM_SET_ERROR(*status, RM_INIT_GPU_GPUMGR_ALLOC_GPU_FAILED); + return; + } + + // RM_BASIC_LOCK_MODEL: allocate GPU lock + status->rmStatus = rmGpuLockAlloc(*pDeviceReference); + if (status->rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "*** cannot allocate GPU lock\n"); + RM_SET_ERROR(*status, RM_INIT_GPU_GPUMGR_ALLOC_GPU_FAILED); + // RM_BASIC_LOCK_MODEL: free GPU lock + rmGpuLockFree(*pDeviceReference); + return; + } + + // attach default single-entry broadcast device for this gpu + status->rmStatus = gpumgrCreateDevice(&deviceInstance, NVBIT(*pDeviceReference), NULL); + if (status->rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "*** Cannot attach bc gpu\n"); + RM_SET_ERROR(*status, RM_INIT_GPU_GPUMGR_CREATE_DEV_FAILED); + // RM_BASIC_LOCK_MODEL: free GPU lock + rmGpuLockFree(*pDeviceReference); + return; + } + + // init attach state + gpuAttachArg = portMemAllocNonPaged(sizeof(GPUATTACHARG)); + if (gpuAttachArg == NULL) + { + NV_PRINTF(LEVEL_ERROR, "*** Cannot allocate gpuAttachArg\n"); + RM_SET_ERROR(*status, RM_INIT_GPU_GPUMGR_ALLOC_GPU_FAILED); + // RM_BASIC_LOCK_MODEL: free GPU lock + rmGpuLockFree(*pDeviceReference); + return; + } + + portMemSet(gpuAttachArg, 0, sizeof(GPUATTACHARG)); + + if (NV_IS_SOC_DISPLAY_DEVICE(nv)) + { + gpuAttachArg->socDeviceArgs.specified = NV_TRUE; + + RmSetSocDispDeviceMappings(gpuAttachArg, nv); + + RmSetSocDpauxDeviceMappings(gpuAttachArg, nv); + + RmSetSocHdacodecDeviceMappings(gpuAttachArg, nv); + + RmSetSocMipiCalDeviceMappings(gpuAttachArg, nv); + + gpuAttachArg->socDeviceArgs.socChipId0 = nv->disp_sw_soc_chip_id; + + gpuAttachArg->socDeviceArgs.iovaspaceId = nv->iovaspace_id; + } + else + { + gpuAttachArg->fbPhysAddr = nv->fb->cpu_address; + gpuAttachArg->fbBaseAddr = (GPUHWREG*) 0; // not mapped + gpuAttachArg->devPhysAddr = nv->regs->cpu_address; + gpuAttachArg->regBaseAddr = (GPUHWREG*) nv->regs->map; + gpuAttachArg->intLine = 0; // don't know yet + gpuAttachArg->instPhysAddr = nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address; + gpuAttachArg->instBaseAddr = (GPUHWREG*) 0; // not mapped + + gpuAttachArg->regLength = nv->regs->size; + gpuAttachArg->fbLength = nv->fb->size; + gpuAttachArg->instLength = nv->bars[NV_GPU_BAR_INDEX_IMEM].size; + + gpuAttachArg->iovaspaceId = nv->iovaspace_id; + } + + // + // we need this to check if we are running on virtual GPU + // in gpuBindHal function later. + // + gpuAttachArg->nvDomainBusDeviceFunc = nv_encode_pci_info(&nv->pci_info); + + gpuAttachArg->bRequestFwClientRm = nv->request_fw_client_rm; + + gpuAttachArg->pOsAttachArg = (void *)nv; + + // use gpu manager to attach gpu + status->rmStatus = gpumgrAttachGpu(*pDeviceReference, gpuAttachArg); + portMemFree(gpuAttachArg); + if (status->rmStatus != NV_OK) + { + gpumgrDestroyDevice(deviceInstance); + RM_SET_ERROR(*status, RM_INIT_GPU_GPUMGR_ATTACH_GPU_FAILED); + NV_PRINTF(LEVEL_ERROR, "*** Cannot attach gpu\n"); + // RM_BASIC_LOCK_MODEL: free GPU lock + rmGpuLockFree(*pDeviceReference); + return; + } + nvp->flags |= NV_INIT_FLAG_GPUMGR_ATTACH; + + pGpu = gpumgrGetGpu(*pDeviceReference); + + sysInitRegistryOverrides(pSys); + + sysApplyLockingPolicy(pSys); + + pGpu->busInfo.IntLine = nv->interrupt_line; + + // + // Set the DMA address size as soon as we have the HAL to call to + // determine the precise number of physical address bits supported + // by the architecture. DMA allocations should not be made before + // this point. + // + nv_set_dma_address_size(nv, gpuGetPhysAddrWidth_HAL(pGpu, ADDR_SYSMEM)); + + pGpu->dmaStartAddress = (RmPhysAddr)nv_get_dma_start_address(nv); + if (nv->fb != NULL) + { + pGpu->registerAccess.gpuFbAddr = (GPUHWREG*) nv->fb->map; + pGpu->busInfo.gpuPhysFbAddr = nv->fb->cpu_address; + } + + // set default parent gpu + gpumgrSetParentGPU(pGpu, pGpu); + + NV_PRINTF(LEVEL_INFO, "device instance : %d\n", *pDeviceReference); + NV_PRINTF(LEVEL_INFO, "NV regs using linear address : 0x%p\n", + pGpu->deviceMappings[SOC_DEV_MAPPING_DISP].gpuNvAddr); + NV_PRINTF(LEVEL_INFO, + "NV fb using linear address : 0x%p\n", pGpu->registerAccess.gpuFbAddr); + + pGpu->setProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_ENABLED, NV_TRUE); + pGpu->setProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS, NV_FALSE); + + if (osReadRegistryDword(pGpu, + NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR, &data) == NV_OK) + { + if (data == NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR_ENABLE) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS, NV_TRUE); + } + } + + if (!os_is_vgx_hyper()) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_ALLOW_PAGE_RETIREMENT, NV_TRUE); + } + + if ((osReadRegistryDword(NULL, + NV_REG_PRESERVE_VIDEO_MEMORY_ALLOCATIONS, + &data) == NV_OK) && data) + { + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + memmgrSetPmaForcePersistence(pMemoryManager, NV_TRUE); + pKernelMemorySystem->bPreserveComptagBackingStoreOnSuspend = NV_TRUE; + + nv->preserve_vidmem_allocations = NV_TRUE; + } +} + +void osInitScalabilityOptions +( + OBJGPU *pGpu, + void *pDeviceExtension +) +{ +} + + +static NV_STATUS +osInitScalability( + OBJGPU *pGpu +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + + osInitScalabilityOptions(pGpu, NULL); + + // We need PCI-E chipset information very early. + if (pCl != NULL) + { + return clInitPcie(pGpu, pCl); + } + else + { + return NV_ERR_NOT_SUPPORTED; + } +} + +static NV_STATUS +osTeardownScalability( + OBJGPU *pGpu +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + + return clTeardownPcie(pGpu, pCl); +} + +static void +populateDeviceAttributes( + OBJGPU *pGpu, + nv_state_t *nv +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + + if ((pCl != NULL) && pCl->getProperty(pCl, PDB_PROP_CL_IS_EXTERNAL_GPU)) + { + nv->is_external_gpu = NV_TRUE; + } +} + +static void +RmSetConsolePreservationParams(OBJGPU *pGpu) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + NvU64 fbBaseAddress = 0; + NvU64 fbConsoleSize = 0; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + // + // PDB_PROP_GPU_PRIMARY_DEVICE should be NV_FALSE for vGPU configuration so + // return early + // + if (os_is_vgx_hyper() || IS_VIRTUAL(pGpu)) + return; + + // + // Check the OS layer for any video memory used by a console + // driver that should be reserved. + // + // If the console driver is using some amount of memory, its + // mapping is presumably either pointing at the start of BAR1 + // (this is the mapping the EFI GOP driver provides for + // efifb), or the upper 16MB of BAR2 (this is the mapping the + // VBIOS provides for, e.g., vesafb). + // + // In the BAR2 case, there is nothing more to do: the upper + // 16MB of BAR2 will remain in physical mode + // (see the documentation for NV_PBUS_BAR2_BLOCK in dev_bus.ref), + // and the console driver can continue to access it. + // + // In the BAR1 case, RM will put all of BAR1 into virtual + // mode, so we need to create a BAR1 mapping for the console + // driver to use. + // + // If the console driver is not using _either_ of those + // mappings, then the console driver will not be able to + // access the memory we reserve. This happens on some + // UEFI systems with multiple GPUs, because the firmware + // initializes the GOP driver on more than one GPU. In + // that case, just skip reserving anything for GPUs where + // neither BAR1 nor BAR2 match the console's base + // address. + // + fbConsoleSize = rm_get_uefi_console_size(nv, &fbBaseAddress); + + if (fbConsoleSize == 0) + { + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_UEFI)) + { + fbConsoleSize = 0x40000; + } + else + { + NV_PRINTF(LEVEL_INFO, "No Frame Buffer Present\n"); + } + } + + if ((fbConsoleSize > 0) && (fbBaseAddress != 0)) + { + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + pKernelBus->bPreserveBar1ConsoleEnabled = + (fbBaseAddress == nv->fb->cpu_address); + } + + pMemoryManager->Ram.ReservedConsoleDispMemSize = NV_ALIGN_UP(fbConsoleSize, 0x10000); +} + +static NV_STATUS +RmInitDeviceDma( + nv_state_t *nv +) +{ + if (nv->iovaspace_id != NV_IOVA_DOMAIN_NONE) + { + OBJSYS *pSys = SYS_GET_INSTANCE(); + POBJVMM pVmm = SYS_GET_VMM(pSys); + POBJVASPACE pIOVAS; + NV_STATUS status = vmmCreateVaspace(pVmm, IO_VASPACE_A, + nv->iovaspace_id, 0, 0ULL, ~0ULL, + 0ULL, 0ULL, + NULL, VASPACE_FLAGS_ENABLE_VMM, + &pIOVAS); + if (status != NV_OK) + { + return status; + } + } + + return NV_OK; +} + +static void +RmTeardownDeviceDma( + nv_state_t *nv +) +{ + if (nv->iovaspace_id != NV_IOVA_DOMAIN_NONE) + { + OBJSYS *pSys = SYS_GET_INSTANCE(); + POBJVMM pVmm = SYS_GET_VMM(pSys); + POBJVASPACE pIOVAS; + + if (NV_OK == vmmGetVaspaceFromId(pVmm, nv->iovaspace_id, IO_VASPACE_A, &pIOVAS)) + { + vmmDestroyVaspace(pVmm, pIOVAS); + } + } +} + +static void +RmInitNvDevice( + NvU32 deviceReference, + UNIX_STATUS *status +) +{ + // set the device context + OBJGPU *pGpu = gpumgrGetGpu(deviceReference); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + NV_PRINTF(LEVEL_INFO, "RmInitNvDevice:\n"); + + NV_PRINTF(LEVEL_INFO, + "device instance : 0x%08x\n", deviceReference); + + // initialize all engines -- calls back osInitMapping() + status->rmStatus = gpumgrStatePreInitGpu(pGpu); + if (status->rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "*** Cannot pre-initialize the device\n"); + RM_SET_ERROR(*status, RM_INIT_GPU_PRE_INIT_FAILED); + return; + } + + os_disable_console_access(); + + status->rmStatus = gpumgrStateInitGpu(pGpu); + if (status->rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "*** Cannot initialize the device\n"); + RM_SET_ERROR(*status, RM_INIT_GPU_STATE_INIT_FAILED); + os_enable_console_access(); + return; + } + nvp->flags |= NV_INIT_FLAG_GPU_STATE; + + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + // + // Make sure bifIsMSIEnabled() gets a chance to look up the OS PCI + // handle for this GPU. This must happen after GPU state + // initialization. + // + if (pKernelBif != NULL) + { + kbifCheckAndRearmMSI(pGpu, pKernelBif); + } + + // Set RM's interrupt enable state to zero here so that interrupts + // won't be enabled during loading + Intr *pIntr = GPU_GET_INTR(pGpu); + if (pIntr != NULL) + { + intrSetIntrEn(pIntr, INTERRUPT_TYPE_DISABLED); + } + + status->rmStatus = gpumgrStateLoadGpu(pGpu, GPU_STATE_DEFAULT); + if (status->rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "*** Cannot load state into the device\n"); + RM_SET_ERROR(*status, RM_INIT_GPU_LOAD_FAILED); + os_enable_console_access(); + return; + } + nvp->flags |= NV_INIT_FLAG_GPU_STATE_LOAD; + + os_enable_console_access(); + + status->rmStatus = gpuPerformUniversalValidation_HAL(pGpu); + if (status->rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "*** Failed universal validation\n"); + RM_SET_ERROR(*status, RM_INIT_GPU_UNIVERSAL_VALIDATION_FAILED); + return; + } + + return; +} + +NV_STATUS osInitMapping( + OBJGPU *pGpu +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + NV_PRINTF(LEVEL_INFO, "osInitMapping:\n"); + + // Some PCI BIOSs leave the ROM mapped. This causes problems if it overlays system RAM. Just disable it. + GPU_BUS_CFG_WR32(pGpu, NV_CONFIG_PCI_NV_12, 0); + + // make sure our PCI latency timer is sufficient (max it out) + GPU_BUS_CFG_WR32(pGpu, NV_CONFIG_PCI_NV_3, + DRF_DEF(_CONFIG, _PCI_NV_3, _LATENCY_TIMER, _248_CLOCKS)); + + if (pCl != NULL) + { + initCoreLogic(pGpu); + } + nvp->flags |= NV_INIT_FLAG_CORE_LOGIC; + + return NV_OK; + +} // end of osInitMapping() + +static NV_STATUS +initCoreLogic( + OBJGPU *pGpu +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + +#if defined(NVCPU_X86_64) + OBJOS *pOS = SYS_GET_OS(pSys); + if (!os_pat_supported()) + pOS->setProperty(pOS, PDB_PROP_OS_PAT_UNSUPPORTED, NV_TRUE); +#endif + + return clInit(pGpu, pCl); +} + +static NV_STATUS +teardownCoreLogic( + OBJOS *pOS, + OBJGPU *pGpu +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + + return clTeardown(pGpu, pCl); +} + +static void RmTeardownDpauxRegisters( + nv_state_t *nv +) +{ +} + +static void RmTeardownHdacodecRegisters( + nv_state_t *nv +) +{ +} + +static void RmTeardownMipiCalRegisters( + nv_state_t *nv +) +{ +} + +static NV_STATUS +RmTeardownRegisters( + nv_state_t *nv +) +{ + NV_DEV_PRINTF(NV_DBG_SETUP, nv, "Tearing down registers\n"); + + if (nv->regs && nv->regs->map) + { + osUnmapKernelSpace(nv->regs->map, nv->regs->size); + nv->regs->map = 0; + nv->regs->map_u = NULL; + } + + RmTeardownDpauxRegisters(nv); + + RmTeardownHdacodecRegisters(nv); + + RmTeardownMipiCalRegisters(nv); + + return NV_OK; +} + +static NV_STATUS +RmSetupDpauxRegisters( + nv_state_t *nv, + UNIX_STATUS *status +) +{ + + return NV_OK; +} + +static NV_STATUS +RmSetupHdacodecRegisters( + nv_state_t *nv, + UNIX_STATUS *status +) +{ + + return NV_OK; +} + +static NV_STATUS +RmSetupMipiCalRegisters( + nv_state_t *nv, + UNIX_STATUS *status +) +{ + + return NV_OK; +} + +static void +RmSetupRegisters( + nv_state_t *nv, + UNIX_STATUS *status +) +{ + NV_STATUS ret; + + NV_DEV_PRINTF(NV_DBG_SETUP, nv, "RmSetupRegisters for 0x%x:0x%x\n", + nv->pci_info.vendor_id, nv->pci_info.device_id); + NV_DEV_PRINTF(NV_DBG_SETUP, nv, "pci config info:\n"); + NV_DEV_PRINTF(NV_DBG_SETUP, nv, " registers look like: " NvP64_fmt " " NvP64_fmt, + nv->regs->cpu_address, nv->regs->size); + + if (nv->fb != NULL) + { + NV_DEV_PRINTF(NV_DBG_SETUP, nv, " fb looks like: " NvP64_fmt " " NvP64_fmt, + nv->fb->cpu_address, nv->fb->size); + } + + { + nv_os_map_kernel_space(nv, nv->regs); + } + + if (nv->regs->map == NULL) + { + NV_DEV_PRINTF(NV_DBG_ERRORS, nv, "Failed to map regs registers!!\n"); + RM_SET_ERROR(*status, RM_INIT_REG_SETUP_FAILED); + status->rmStatus = NV_ERR_OPERATING_SYSTEM; + return; + } + NV_DEV_PRINTF(NV_DBG_SETUP, nv, "Successfully mapped framebuffer and registers\n"); + NV_DEV_PRINTF(NV_DBG_SETUP, nv, "final mappings:\n"); + NV_DEV_PRINTF(NV_DBG_SETUP, nv, " regs: " NvP64_fmt " " NvP64_fmt " 0x%p\n", + nv->regs->cpu_address, nv->regs->size, nv->regs->map); + + ret = RmSetupDpauxRegisters(nv, status); + if (ret != NV_OK) + goto err_unmap_disp_regs; + + ret = RmSetupHdacodecRegisters(nv, status); + if (ret != NV_OK) + { + RmTeardownDpauxRegisters(nv); + goto err_unmap_disp_regs; + } + + ret = RmSetupMipiCalRegisters(nv, status); + if (ret != NV_OK) + { + RmTeardownHdacodecRegisters(nv); + RmTeardownDpauxRegisters(nv); + goto err_unmap_disp_regs; + } + + return; + +err_unmap_disp_regs: + if (nv->regs && nv->regs->map) + { + osUnmapKernelSpace(nv->regs->map, nv->regs->size); + nv->regs->map = 0; + } + + return; +} + +NvBool RmInitPrivateState( + nv_state_t *pNv +) +{ + nv_priv_t *nvp; + NvU32 gpuId; + NvU32 pmc_boot_0 = 0; + NvU32 pmc_boot_42 = 0; + + NV_SET_NV_PRIV(pNv, NULL); + + if (!NV_IS_SOC_DISPLAY_DEVICE(pNv) && !NV_IS_SOC_IGPU_DEVICE(pNv)) + { + pNv->regs->map_u = os_map_kernel_space(pNv->regs->cpu_address, + os_page_size, + NV_MEMORY_UNCACHED); + if (pNv->regs->map_u == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "failed to map GPU registers (DISABLE_INTERRUPTS).\n"); + return NV_FALSE; + } + + pmc_boot_0 = NV_PRIV_REG_RD32(pNv->regs->map_u, NV_PMC_BOOT_0); + pmc_boot_42 = NV_PRIV_REG_RD32(pNv->regs->map_u, NV_PMC_BOOT_42); + + os_unmap_kernel_space(pNv->regs->map_u, os_page_size); + pNv->regs->map_u = NULL; + } + + if (os_alloc_mem((void **)&nvp, sizeof(*nvp)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "failed to allocate private device state.\n"); + return NV_FALSE; + } + + gpuId = nv_generate_id_from_pci_info(&pNv->pci_info); + + if (gpumgrRegisterGpuId(gpuId, nv_encode_pci_info(&pNv->pci_info)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "failed to register GPU with GPU manager.\n"); + os_free_mem(nvp); + return NV_FALSE; + } + + pNv->gpu_id = gpuId; + + pNv->iovaspace_id = nv_requires_dma_remap(pNv) ? gpuId : + NV_IOVA_DOMAIN_NONE; + + kvgpumgrAttachGpu(pNv->gpu_id); + + // + // Set up a reasonable default DMA address size, based on the minimum + // possible on currently supported GPUs. + // + nv_set_dma_address_size(pNv, NV_GPU_MIN_SUPPORTED_DMA_ADDR_WIDTH); + + os_mem_set(nvp, 0, sizeof(*nvp)); + nvp->status = NV_ERR_INVALID_STATE; + nvp->pmc_boot_0 = pmc_boot_0; + nvp->pmc_boot_42 = pmc_boot_42; + NV_SET_NV_PRIV(pNv, nvp); + + return NV_TRUE; +} + +void RmClearPrivateState( + nv_state_t *pNv +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(pNv); + NvU32 status; + void *pVbiosCopy = NULL; + void *pRegistryCopy = NULL; + NvU32 vbiosSize; + NvU32 *pEfiDisplayCache; + NvU32 efiDisplayCacheSize; + nv_i2c_adapter_entry_t i2c_adapters[MAX_I2C_ADAPTERS]; + nv_dynamic_power_t dynamicPowerCopy; + NvU32 x = 0; + NvU32 pmc_boot_0, pmc_boot_42; + + // + // Do not clear private state after GPU resets, it is used while + // recovering the GPU. Only clear the pGpu pointer, which is + // restored during next initialization cycle. + // + if (pNv->flags & NV_FLAG_IN_RECOVERY) + { + nvp->pGpu = NULL; + } + + status = nvp->status; + pVbiosCopy = nvp->pVbiosCopy; + vbiosSize = nvp->vbiosSize; + pRegistryCopy = nvp->pRegistry; + pEfiDisplayCache = nvp->efi.display.pCache; + efiDisplayCacheSize = nvp->efi.display.cacheSize; + dynamicPowerCopy = nvp->dynamic_power; + pmc_boot_0 = nvp->pmc_boot_0; + pmc_boot_42 = nvp->pmc_boot_42; + + for (x = 0; x < MAX_I2C_ADAPTERS; x++) + { + i2c_adapters[x] = nvp->i2c_adapters[x]; + } + + portMemSet(nvp, 0, sizeof(nv_priv_t)); + + nvp->status = status; + nvp->pVbiosCopy = pVbiosCopy; + nvp->vbiosSize = vbiosSize; + nvp->pRegistry = pRegistryCopy; + nvp->efi.display.pCache = pEfiDisplayCache; + nvp->efi.display.cacheSize = efiDisplayCacheSize; + nvp->dynamic_power = dynamicPowerCopy; + nvp->pmc_boot_0 = pmc_boot_0; + nvp->pmc_boot_42 = pmc_boot_42; + + for (x = 0; x < MAX_I2C_ADAPTERS; x++) + { + nvp->i2c_adapters[x] = i2c_adapters[x]; + } + + nvp->flags |= NV_INIT_FLAG_PUBLIC_I2C; +} + +void RmFreePrivateState( + nv_state_t *pNv +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(pNv); + + gpumgrUnregisterGpuId(pNv->gpu_id); + + kvgpumgrDetachGpu(pNv->gpu_id); + + RmDestroyRegistry(pNv); + + if (nvp != NULL) + { + portMemFree(nvp->pVbiosCopy); + portMemFree(nvp->efi.display.pCache); + os_free_mem(nvp); + } + + NV_SET_NV_PRIV(pNv, NULL); +} + +NvBool RmPartiallyInitAdapter( + nv_state_t *nv +) +{ + NV_PRINTF(LEVEL_INFO, "%s: %04x:%02x:%02x.0\n", __FUNCTION__, + nv->pci_info.domain, nv->pci_info.bus, nv->pci_info.slot); + + nv_start_rc_timer(nv); + + return NV_TRUE; +} + +static NV_STATUS +RmInitX86Emu( + OBJGPU *pGpu +) +{ + NV_STATUS status = NV_OK; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + PORT_UNREFERENCED_VARIABLE(nv); + +#if NVCPU_IS_X86_64 + status = RmInitX86EmuState(pGpu); +#else + // We don't expect a "primary VGA" adapter on non-amd64 platforms + NV_ASSERT(!NV_PRIMARY_VGA(nv)); +#endif + + return status; +} + +static NV_STATUS RmRegisterGpudb( + OBJGPU *pGpu +) +{ + NV_STATUS rmStatus; + const NvU8 *pGid; + nv_state_t *pNv = NV_GET_NV_STATE(pGpu); + + pGid = RmGetGpuUuidRaw(pNv); + if (pGid == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to get UUID\n"); + return NV_ERR_OPERATING_SYSTEM; + } + + rmStatus = gpudbRegisterGpu(pGid, &pGpu->gpuClData.upstreamPort.addr, + pGpu->busInfo.nvDomainBusDeviceFunc); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to register GPU with GPU data base\n"); + } + + return rmStatus; +} + +static void RmUnixFreeRmApi( + nv_state_t *nv +) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); + + if (nv->rmapi.hClient != 0) + { + pRmApi->Free(pRmApi, nv->rmapi.hClient, nv->rmapi.hClient); + } + + portMemSet(&nv->rmapi, 0, sizeof(nv->rmapi)); +} + +static NvBool RmUnixAllocRmApi( + nv_state_t *nv, + NvU32 deviceId +) +{ + NV0080_ALLOC_PARAMETERS deviceParams = { 0 }; + NV2080_ALLOC_PARAMETERS subDeviceParams = { 0 }; + RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); + + portMemSet(&nv->rmapi, 0, sizeof(nv->rmapi)); + + if (pRmApi->AllocWithHandle( + pRmApi, + NV01_NULL_OBJECT, + NV01_NULL_OBJECT, + NV01_NULL_OBJECT, + NV01_ROOT, + &nv->rmapi.hClient) != NV_OK) + { + goto fail; + } + + // + // Any call to rmapiDelPendingDevices() will internally delete the UNIX OS + // layer RMAPI handles. Set this flag to preserve these handles. These + // handles will be freed explicitly by RmUnixFreeRmApi(). + // + if (!rmclientSetClientFlagsByHandle(nv->rmapi.hClient, + RMAPI_CLIENT_FLAG_RM_INTERNAL_CLIENT)) + { + goto fail; + } + + deviceParams.deviceId = deviceId; + + if (pRmApi->Alloc( + pRmApi, + nv->rmapi.hClient, + nv->rmapi.hClient, + &nv->rmapi.hDevice, + NV01_DEVICE_0, + &deviceParams) != NV_OK) + { + goto fail; + } + + subDeviceParams.subDeviceId = 0; + + if (pRmApi->Alloc( + pRmApi, + nv->rmapi.hClient, + nv->rmapi.hDevice, + &nv->rmapi.hSubDevice, + NV20_SUBDEVICE_0, + &subDeviceParams) != NV_OK) + { + goto fail; + } + + // + // The NV40_I2C allocation expected to fail, if it is disabled + // with RM config. + // + if (pRmApi->Alloc( + pRmApi, + nv->rmapi.hClient, + nv->rmapi.hSubDevice, + &nv->rmapi.hI2C, + NV40_I2C, + NULL) != NV_OK) + { + nv->rmapi.hI2C = 0; + } + + // + // The NV04_DISPLAY_COMMON allocation expected to fail for displayless + // system. nv->rmapi.hDisp value needs to be checked before doing display + // related control calls. + // + if (pRmApi->Alloc( + pRmApi, + nv->rmapi.hClient, + nv->rmapi.hDevice, + &nv->rmapi.hDisp, + NV04_DISPLAY_COMMON, + NULL) != NV_OK) + { + nv->rmapi.hDisp = 0; + } + + return NV_TRUE; + +fail: + RmUnixFreeRmApi(nv); + return NV_FALSE; +} + +NvBool RmInitAdapter( + nv_state_t *nv +) +{ + NvU32 devicereference = 0; + UNIX_STATUS status = INIT_UNIX_STATUS; + nv_priv_t *nvp; + NvBool retVal = NV_FALSE; + OBJSYS *pSys; + OBJGPU *pGpu = NULL; + OBJOS *pOS; + KernelDisplay *pKernelDisplay; + const void *gspFwHandle = NULL; + const void *gspFwLogHandle = NULL; + + GSP_FIRMWARE gspFw = {0}; + PORT_UNREFERENCED_VARIABLE(gspFw); + + NV_DEV_PRINTF(NV_DBG_SETUP, nv, "RmInitAdapter\n"); + + nv->flags &= ~NV_FLAG_PASSTHRU; + + RmSetupRegisters(nv, &status); + if (! RM_INIT_SUCCESS(status.initStatus) ) + goto failed; + + nvp = NV_GET_NV_PRIV(nv); + nvp->status = NV_ERR_OPERATING_SYSTEM; + + status.rmStatus = RmInitDeviceDma(nv); + if (status.rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Cannot configure the device for DMA\n"); + RM_SET_ERROR(status, RM_INIT_GPU_DMA_CONFIGURATION_FAILED); + goto shutdown; + } + + nvp->flags |= NV_INIT_FLAG_DMA; + + pSys = SYS_GET_INSTANCE(); + + // + // WAR: If the below UEFI property is set, display RM will attempt to read + // the state cache during RM init in order to retrieve a snapshot of the + // display state that the UEFI driver has already programmed. On Orin + // (T234D), the UEFI boot flow is being enabled on Linux, but our UEFI + // driver doesn't have any display support right now. As such, our UEFI + // driver won't allocate any of the display channels, which means that RM + // will attempt to read the state cache for uninitialized channels. WAR this + // issue by un-setting the below UEFI property for now. + // + // JIRA task TDS-5094 tracks adding display support to the UEFI driver. + // + if (NV_IS_SOC_DISPLAY_DEVICE(nv)) { + pSys->setProperty(pSys, PDB_PROP_SYS_IS_UEFI, NV_FALSE); + } + + // + // Get firmware from the OS, if requested, and decide if RM will run as a + // firmware client. + // + if (nv->request_firmware) + { + NvU32 gpuArch = (DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, nvp->pmc_boot_42) << + GPU_ARCH_SHIFT); + NvU32 gpuImpl = DRF_VAL(_PMC, _BOOT_42, _IMPLEMENTATION, nvp->pmc_boot_42); + + nv_firmware_chip_family_t chipFamily = nv_firmware_get_chip_family(gpuArch, gpuImpl); + + nv_set_dma_address_size(nv, NV_GSP_GPU_MIN_SUPPORTED_DMA_ADDR_WIDTH); + + gspFwHandle = nv_get_firmware(nv, NV_FIRMWARE_TYPE_GSP, + chipFamily, + &gspFw.pBuf, + &gspFw.size); + if (gspFwHandle == NULL && + !nv->allow_fallback_to_monolithic_rm) + { + RM_SET_ERROR(status, RM_INIT_FIRMWARE_FETCH_FAILED); + goto shutdown; + } + else if (gspFwHandle != NULL) + { +#if LIBOS_LOG_DECODE_ENABLE + if (nv->enable_firmware_logs) + { + gspFwLogHandle = nv_get_firmware(nv, NV_FIRMWARE_TYPE_GSP_LOG, + chipFamily, + &gspFw.pLogElf, + &gspFw.logElfSize); + if (gspFwLogHandle == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to load gsp_log_*.bin, no GSP-RM logs will be printed (non-fatal)\n"); + } + } +#endif + + nv->request_fw_client_rm = NV_TRUE; + } + else + { + nv->request_fw_client_rm = NV_FALSE; + } + } + + // initialize the RM device register mapping + osInitNvMapping(nv, &devicereference, &status); + if (! RM_INIT_SUCCESS(status.initStatus) ) + { + switch (status.rmStatus) + { + case NV_ERR_NOT_SUPPORTED: + nvp->status = NV_ERR_NOT_SUPPORTED; + break; + } + NV_PRINTF(LEVEL_ERROR, + "osInitNvMapping failed, bailing out of RmInitAdapter\n"); + goto shutdown; + } + + // + // now we can have a pdev for the first time... + // + pGpu = gpumgrGetGpu(devicereference); + + pOS = SYS_GET_OS(pSys); + + status.rmStatus = osInitScalability(pGpu); + if (status.rmStatus == NV_OK) + { + nvp->flags |= NV_INIT_FLAG_SCALABILITY; + } + else if (status.rmStatus != NV_ERR_NOT_SUPPORTED) + { + RM_SET_ERROR(status, RM_INIT_SCALABILITY_FAILED); + goto shutdown; + } + + KernelFsp *pKernelFsp = GPU_GET_KERNEL_FSP(pGpu); + if ((pKernelFsp != NULL) && !IS_GSP_CLIENT(pGpu) && !IS_VIRTUAL(pGpu)) + { + status.rmStatus = kfspSendBootCommands_HAL(pGpu, pKernelFsp); + if (status.rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "FSP boot command failed.\n"); + goto shutdown; + } + } + + RmSetConsolePreservationParams(pGpu); + + RmInitAcpiMethods(pOS, pSys, pGpu); + + // + // If GSP fw RM support is enabled then start the GSP microcode + // (including the task running the full instance of the RM) and + // exchange the necessary initial RPC messages before continuing + // with GPU initialization here. + // + if (IS_GSP_CLIENT(pGpu)) + { + status.rmStatus = kgspInitRm(pGpu, GPU_GET_KERNEL_GSP(pGpu), &gspFw); + if (status.rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Cannot initialize GSP firmware RM\n"); + RM_SET_ERROR(status, RM_INIT_FIRMWARE_INIT_FAILED); + goto shutdown; + } + } + else if (nv->request_fw_client_rm) + { + // We were expecting to enable GSP-RM but something went wrong. + if (!nv->allow_fallback_to_monolithic_rm) + { + RM_SET_ERROR(status, RM_INIT_FIRMWARE_POLICY_FAILED); + goto shutdown; + } + else + { + NV_PRINTF(LEVEL_NOTICE, "Falling back to monolithic RM\n"); + } + } + + pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + if (pKernelDisplay != NULL) + { + kdispSetWarPurgeSatellitesOnCoreFree(pKernelDisplay, NV_TRUE); + } + + if (IS_PASSTHRU(pGpu)) + nv->flags |= NV_FLAG_PASSTHRU; + + populateDeviceAttributes(pGpu, nv); + + initVendorSpecificRegistry(pGpu, nv->pci_info.device_id); + if (!IS_VIRTUAL(pGpu) && !IS_GSP_CLIENT(pGpu)) + { + initNbsiTable(pGpu); + } + + // finally, initialize the device + RmInitNvDevice(devicereference, &status); + if (! RM_INIT_SUCCESS(status.initStatus) ) + { + NV_PRINTF(LEVEL_ERROR, + "RmInitNvDevice failed, bailing out of RmInitAdapter\n"); + switch (status.rmStatus) + { + case NV_ERR_INSUFFICIENT_POWER: + nvp->status = NV_ERR_INSUFFICIENT_POWER; + NV_DEV_PRINTF(NV_DBG_ERRORS, nv, + "GPU does not have the necessary power cables connected.\n"); + break; + } + goto shutdown; + } + + // LOCK: acquire GPUs lock + status.rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_INIT); + if (status.rmStatus != NV_OK) + { + goto shutdown; + } + + status.rmStatus = osVerifySystemEnvironment(pGpu); + + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + + if (status.rmStatus != NV_OK) + { + RM_SET_ERROR(status, RM_INIT_SYS_ENVIRONMENT_FAILED); + switch (status.rmStatus) + { + case NV_ERR_IRQ_NOT_FIRING: + nvp->status = NV_ERR_IRQ_NOT_FIRING; + break; + } + NV_PRINTF(LEVEL_ERROR, "RmVerifySystemEnvironment failed, bailing!\n"); + goto shutdown; + } + + Intr *pIntr = GPU_GET_INTR(pGpu); + if (pIntr != NULL) + { + intrSetIntrEn(pIntr, INTERRUPT_TYPE_HARDWARE); + } + + KernelRc *pKernelRc = GPU_GET_KERNEL_RC(pGpu); + // initialize the watchdog (disabled by default) + status.rmStatus = pKernelRc != NULL ? krcWatchdogInit_HAL(pGpu, pKernelRc) : + NV_ERR_NOT_SUPPORTED; + if (status.rmStatus == NV_OK) + { + krcWatchdogDisable(pKernelRc); + nvp->flags |= NV_INIT_FLAG_FIFO_WATCHDOG; + } + else if (status.rmStatus == NV_ERR_NOT_SUPPORTED) + { + NV_PRINTF(LEVEL_INFO, + "krcWatchdogInit returned _NOT_SUPPORTED. For Kepler GPUs in PGOB mode, this is normal\n"); + } + else + { + RM_SET_ERROR(status, RM_INIT_WATCHDOG_FAILED); + NV_PRINTF(LEVEL_ERROR, + "krcWatchdogInit failed, bailing out of RmInitAdapter\n"); + goto shutdown; + } + nv_start_rc_timer(nv); + + nvp->status = NV_OK; + + if (!RmUnixAllocRmApi(nv, devicereference)) { + RM_SET_ERROR(status, RM_INIT_ALLOC_RMAPI_FAILED); + status.rmStatus = NV_ERR_GENERIC; + goto shutdown; + } + + status.rmStatus = RmInitGpuInfoWithRmApi(pGpu); + if (status.rmStatus != NV_OK) + { + RM_SET_ERROR(status, RM_INIT_GPUINFO_WITH_RMAPI_FAILED); + goto shutdown; + } + + status.rmStatus = RmInitX86Emu(pGpu); + if (status.rmStatus != NV_OK) + { + RM_SET_ERROR(status, RM_INIT_VBIOS_X86EMU_FAILED); + NV_PRINTF(LEVEL_ERROR, + "RmInitX86Emu failed, bailing out of RmInitAdapter\n"); + goto shutdown; + } + + // i2c only on master device?? + RmI2cAddGpuPorts(nv); + nvp->flags |= NV_INIT_FLAG_PUBLIC_I2C; + + // This fifo hal call will fail on pre-fermi gpus. In that case, userd + // info will remain 0 and skipped by fb mmap code + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + NvU64 udaddr = 0; + NvU32 udsize = 0; + if (pKernelFifo != NULL) + { + status.rmStatus = kfifoGetUserdBar1MapInfo_HAL(pGpu, pKernelFifo, &udaddr, &udsize); + if (status.rmStatus == NV_OK) + { + nv->ud.cpu_address = (nv->fb->cpu_address + udaddr); + nv->ud.size = udsize; + } + else if (status.rmStatus != NV_ERR_NOT_SUPPORTED) + { + RM_SET_ERROR(status, RM_FIFO_GET_UD_BAR1_MAP_INFO_FAILED); + NV_PRINTF(LEVEL_ERROR, + "kfifoGetUserdBar1MapInfo failed, bailing out of RmInitAdapter\n"); + goto shutdown; + } + } + + nv->flags &= ~NV_FLAG_IN_RECOVERY; + + pOS->setProperty(pOS, PDB_PROP_OS_SYSTEM_EVENTS_SUPPORTED, NV_TRUE); + + RmInitS0ixPowerManagement(nv); + RmInitDeferredDynamicPowerManagement(nv); + + if (!NV_IS_SOC_DISPLAY_DEVICE(nv) && !NV_IS_SOC_IGPU_DEVICE(nv)) + { + status.rmStatus = RmRegisterGpudb(pGpu); + if (status.rmStatus != NV_OK) + { + RM_SET_ERROR(status, RM_GPUDB_REGISTER_FAILED); + goto shutdown; + } + } + + if (nvp->b_mobile_config_enabled) + { + NvU32 ac_plugged = 0; + if (nv_acpi_get_powersource(&ac_plugged) == NV_OK) + { + // LOCK: acquire GPU lock + if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_NONE) == NV_OK) + { + // + // As we have already acquired the API Lock here, we are calling + // RmPowerSourceChangeEvent directly instead of rm_power_source_change_event. + // + RmPowerSourceChangeEvent(nv, !ac_plugged); + + // UNLOCK: release GPU lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + } + } + + { + // OpenRM support for features beyond what is used on Data Center GPUs + // is still fairly immature, so for now require users to opt into use of + // OpenRM with a special registry key, if not on a Data Center GPU. + const GspStaticConfigInfo *pSCI = GPU_GET_GSP_STATIC_INFO(pGpu); + + if (pSCI->computeBranding != COMPUTE_BRANDING_TYPE_TESLA && + ((pGpu->idInfo.PCIDeviceID >> 16) & 0xffff) != NV_PCI_DEVID_DEVICE_PG189_SKU600) + { + NvU32 data = NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DEFAULT; + RmReadRegistryDword(nv, NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS, &data); + + if (data == NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DISABLE) + { + if (!nv->printed_openrm_enable_unsupported_gpus_error) + { + nv_printf(NV_DBG_ERRORS, + "NVRM: Open nvidia.ko is only ready for use on Data Center GPUs.\n"); + nv_printf(NV_DBG_ERRORS, + "NVRM: To force use of Open nvidia.ko on other GPUs, see the\n"); + nv_printf(NV_DBG_ERRORS, + "NVRM: 'OpenRmEnableUnsupportedGpus' kernel module parameter described\n"); + nv_printf(NV_DBG_ERRORS, + "NVRM: in the README.\n"); + nv->printed_openrm_enable_unsupported_gpus_error = NV_TRUE; + } + RM_SET_ERROR(status, RM_INIT_FIRMWARE_INIT_FAILED); + goto shutdown; + } + } + } + + NV_DEV_PRINTF(NV_DBG_SETUP, nv, "RmInitAdapter succeeded!\n"); + + retVal = NV_TRUE; + goto done; + + shutdown: + nv->flags &= ~NV_FLAG_IN_RECOVERY; + + // call ShutdownAdapter to undo anything we've done above + RmShutdownAdapter(nv); + + failed: + NV_DEV_PRINTF(NV_DBG_ERRORS, nv, "RmInitAdapter failed! (0x%x:0x%x:%d)\n", + status.initStatus, status.rmStatus, status.line); + +done: + nv_put_firmware(gspFwHandle); + nv_put_firmware(gspFwLogHandle); + + return retVal; +} + +void RmShutdownAdapter( + nv_state_t *nv +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + NV_STATUS rmStatus; + + if ((pGpu != NULL) && (nvp->flags & NV_INIT_FLAG_GPUMGR_ATTACH)) + { + NvU32 gpuInstance = gpuGetInstance(pGpu); + NvU32 deviceInstance = gpuGetDeviceInstance(pGpu); + OBJSYS *pSys = SYS_GET_INSTANCE(); + + RmUnixFreeRmApi(nv); + + nv->ud.cpu_address = 0; + nv->ud.size = 0; + + // LOCK: acquire GPUs lock + if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DESTROY) == NV_OK) + { + RmDestroyDeferredDynamicPowerManagement(nv); + + freeNbsiTable(pGpu); + + gpuFreeEventHandle(pGpu); + + OBJCL *pCl = SYS_GET_CL(pSys); + OBJOS *pOS = GPU_GET_OS(pGpu); + if (pCl != NULL) + { + if (nvp->flags & NV_INIT_FLAG_CORE_LOGIC) + { + teardownCoreLogic(pOS, pGpu); + } + else if (nvp->flags & NV_INIT_FLAG_SCALABILITY) + { + osTeardownScalability(pGpu); + } + } + + rmapiSetDelPendingClientResourcesFromGpuMask(NVBIT(gpuInstance)); + rmapiDelPendingDevices(NVBIT(gpuInstance)); + + os_disable_console_access(); + + if (nvp->flags & NV_INIT_FLAG_GPU_STATE_LOAD) + { + rmStatus = gpuStateUnload(pGpu, GPU_STATE_DEFAULT); + NV_ASSERT(rmStatus == NV_OK); + } + + if (nvp->flags & NV_INIT_FLAG_GPU_STATE) + { + rmStatus = gpuStateDestroy(pGpu); + NV_ASSERT(rmStatus == NV_OK); + } + + os_enable_console_access(); + + //if (nvp->flags & NV_INIT_FLAG_HAL) + // destroyHal(pDev); + +#if NVCPU_IS_X86_64 + RmFreeX86EmuState(pGpu); +#endif + + gpumgrDetachGpu(gpuInstance); + gpumgrDestroyDevice(deviceInstance); + + if (nvp->flags & NV_INIT_FLAG_DMA) + { + RmTeardownDeviceDma(nv); + } + + RmClearPrivateState(nv); + + RmUnInitAcpiMethods(pSys); + + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + + // RM_BASIC_LOCK_MODEL: free GPU lock + rmGpuLockFree(deviceInstance); + } + } + else + { + RmClearPrivateState(nv); + } + + RmTeardownRegisters(nv); +} + +void RmPartiallyDisableAdapter( + nv_state_t *nv +) +{ + NV_PRINTF(LEVEL_INFO, "%s: RM is in SW Persistence mode\n", __FUNCTION__); + + nv_stop_rc_timer(nv); +} + +void RmDisableAdapter( + nv_state_t *nv +) +{ + NV_STATUS rmStatus; + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + NvU32 gpuMask; + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + // + // Normally, we re-enable interrupts when we release the lock + // after RmDisableAdapter(), before disabling the bottom-half ISR. + // If an interrupt came in in that time window, but the bottom half + // wasn't scheduled to run in time, the semaphore acquired by the + // top-half would never be released afterwards (since the bottom-half + // would never run). This call to intrSetIntrEn() ensures that this won't + // happen, by making sure interrupts remain disabled on the GPU in question after + // RmDisableAdapter(). + // + Intr *pIntr = GPU_GET_INTR(pGpu); + if (pIntr != NULL) + { + intrSetIntrEn(pIntr, INTERRUPT_TYPE_DISABLED); + } + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_SECONDARY_BUS_RESET) || + pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_FULLCHIP_RESET)) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_TIMEOUT_RECOVERY, NV_TRUE); + nv->flags |= NV_FLAG_IN_RECOVERY; + } + + // + // Free the client allocated resources. + // + // This needs to happen prior to tearing down SLI state when SLI is enabled. + // + // Note this doesn't free RM internal resource allocations. Those are + // freed during (gpumgrUpdateSLIConfig->...->)gpuStateUnload. + // + // We need to free resources for all GPUs linked in a group as + // gpumgrUpdateSLIConfig will teardown GPU state for the entire set. + // + gpuMask = gpumgrGetGpuMask(pGpu); + + rmapiSetDelPendingClientResourcesFromGpuMask(gpuMask); + rmapiDelPendingDevices(gpuMask); + + // LOCK: acquire GPUs lock + if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DESTROY) == NV_OK) + { + nv_stop_rc_timer(nv); + + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + OBJOS *pOS = SYS_GET_OS(pSys); + if (pCl != NULL) + { + teardownCoreLogic(pOS, pGpu); + nvp->flags &= ~NV_INIT_FLAG_CORE_LOGIC; + } + + if (nvp->flags & NV_INIT_FLAG_FIFO_WATCHDOG) + { + krcWatchdogShutdown(pGpu, GPU_GET_KERNEL_RC(pGpu)); + nvp->flags &= ~NV_INIT_FLAG_FIFO_WATCHDOG; + } + + os_disable_console_access(); + + if (nvp->flags & NV_INIT_FLAG_GPU_STATE_LOAD) + { + rmStatus = gpuStateUnload(pGpu, GPU_STATE_DEFAULT); + NV_ASSERT(rmStatus == NV_OK); + nvp->flags &= ~NV_INIT_FLAG_GPU_STATE_LOAD; + } + + os_enable_console_access(); + + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } +} + +NV_STATUS RmGetAdapterStatus( + nv_state_t *pNv, + NvU32 *pStatus +) +{ + // + // This status is determined in RmInitAdapter(); the glue layer + // requests it when the adapter failed to initialize to learn + // more about the error condition. This is currently limited to + // osVerifySystemEnvironment() failures. + // + nv_priv_t *nvp; + + nvp = NV_GET_NV_PRIV(pNv); + if (nvp == NULL) + { + return NV_ERR_INVALID_STATE; + } + + *pStatus = nvp->status; + return NV_OK; +} + +static void initVendorSpecificRegistry( + OBJGPU *pGpu, + NvU16 device_id +) +{ + NV_STATUS rmStatus; + NvU32 i; + NvU32 subsystem_id; + NvU32 subsystem_vendor_id; + NvU32 subsystem_device_id; + NvU32 vendor_id = 0; + + if (!pGpu) + return; + + rmStatus = GPU_BUS_CFG_RD32(pGpu, + NV_CONFIG_PCI_NV_11, &subsystem_id); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s: Cannot read NV_CONFIG_PCI_NV_11\n", __FUNCTION__); + return; + } + + subsystem_vendor_id = (subsystem_id & 0xffff); + subsystem_device_id = (subsystem_id >> 16); + + for (i = 0; (nb_id_table[i].subsystem_vendor_id) != 0; i++) + { + if ((nb_id_table[i].subsystem_vendor_id == subsystem_vendor_id) && + (nb_id_table[i].subsystem_device_id == subsystem_device_id) && + (nb_id_table[i].gpu_device_id == device_id)) + { + vendor_id = subsystem_vendor_id; + break; + } + } + + if (vendor_id != 0) + { + for (i = 0; nb_reg_table[i].vendor_id != 0; i++) + { + if (nb_reg_table[i].vendor_id == vendor_id) + { + osWriteRegistryDword(pGpu, nb_reg_table[i].name, + nb_reg_table[i].data); + } + } + } +} + +static void initUnixSpecificRegistry( + OBJGPU *pGpu +) +{ + // By default, enable GPU reset on Unix + osWriteRegistryDword(pGpu, "RMSecBusResetEnable", 1); + osWriteRegistryDword(pGpu, "RMForcePcieConfigSave", 1); + +} + +void +osRemoveGpu( + NvU32 domain, + NvU8 bus, + NvU8 device +) +{ + void *handle; + + handle = os_pci_init_handle(domain, bus, device, 0, NULL, NULL); + if (handle != NULL) + { + os_pci_remove(handle); + } +} + +/* + * Check to see if this board supports GPU exclusion. + */ +static NvBool RmIsExcludingAllowed( + nv_state_t *pNv +) +{ + NvU32 feature = 0; + NvU32 brand; + + // DGX-2/HGX-2 systems pre-date the PBI call + if (pNv->pci_info.device_id == 0x1db8) + return NV_TRUE; + + if (pciPbiGetFeature(pNv->handle, &feature) != NV_OK) + return NV_FALSE; + + brand = DRF_VAL(_PBI, _EXECUTE_ROUTINE, _GET_FEATURE_EXCLUSION, feature); + + return (brand == NV_PBI_EXECUTE_ROUTINE_GET_FEATURE_EXCLUSION_ALLOWED); +} + +NV_STATUS RmExcludeAdapter( + nv_state_t *nv +) +{ + NV_STATUS rmStatus; + + if (!RmIsExcludingAllowed(nv)) + return NV_ERR_NOT_SUPPORTED; + + rmStatus = gpumgrExcludeGpuId(nv->gpu_id); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to exclude GPU: 0x%x\n", rmStatus); + return rmStatus; + } + + /* + * GPU exclusion only happens during initialization, and therefore there + * is no need to stop activity on the GPU + */ + + return rmStatus; +} diff --git a/userspace/sdks/nv525/nvalloc/unix/src/osmemdesc.c b/userspace/sdks/nv525/nvalloc/unix/src/osmemdesc.c new file mode 100644 index 0000000..ad49cf7 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/src/osmemdesc.c @@ -0,0 +1,1030 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/******************* OS Memory Descriptor APIS *****************************\ +* * +* This contains routines to create and destroy OS memory descriptor * +* * +****************************************************************************/ + +#include // NV device driver interface +#include +#include +#include +#include +#include +#include + +#include "gpu/bif/kernel_bif.h" + +static NV_STATUS osCreateOsDescriptorFromPageArray(OBJGPU *, NvP64, NvHandle, NvU32, NvU64 *, MEMORY_DESCRIPTOR **, void **); +static void osDestroyOsDescriptorPageArray(PMEMORY_DESCRIPTOR); + +static NV_STATUS osCreateOsDescriptorFromIoMemory(OBJGPU *, NvP64, NvHandle, NvU32, NvU64 *, MEMORY_DESCRIPTOR **, void**); +static void osDestroyOsDescriptorFromIoMemory(PMEMORY_DESCRIPTOR); + +static NV_STATUS osCreateOsDescriptorFromPhysAddr(OBJGPU *, NvP64, NvHandle, NvU32, NvU64 *, MEMORY_DESCRIPTOR **, void**); +static void osDestroyOsDescriptorFromPhysAddr(PMEMORY_DESCRIPTOR); + +static NV_STATUS osCreateOsDescriptorFromFileHandle(OBJGPU *, NvP64, NvHandle, NvU32, NvU64 *, MEMORY_DESCRIPTOR **, void**); +static NV_STATUS osCreateOsDescriptorFromDmaBufPtr(OBJGPU *, NvP64, NvHandle, NvU32, NvU64 *, MEMORY_DESCRIPTOR **, void**); +static void osDestroyOsDescriptorFromDmaBuf(PMEMORY_DESCRIPTOR); +static NV_STATUS osCreateOsDescriptorFromSgtPtr(OBJGPU *, NvP64, NvHandle, NvU32, NvU64 *, MEMORY_DESCRIPTOR **, void**); +static void osDestroyOsDescriptorFromSgt(PMEMORY_DESCRIPTOR); + +static NV_STATUS osCheckGpuBarsOverlapAddrRange(NvRangeU64 addrRange); + +NV_STATUS +osCreateMemFromOsDescriptor +( + OBJGPU *pGpu, + NvP64 pDescriptor, + NvHandle hClient, + NvU32 flags, + NvU64 *pLimit, + MEMORY_DESCRIPTOR **ppMemDesc, + NvU32 descriptorType, + RS_PRIV_LEVEL privilegeLevel +) +{ + RmClient* pClient; + NV_STATUS rmStatus; + void *pPrivate; + + if ((pDescriptor == NvP64_NULL) || + (*pLimit == 0) || + (serverutilGetClientUnderLock(hClient, &pClient) != NV_OK)) + { + return NV_ERR_INVALID_PARAM_STRUCT; + } + + // + // For the sake of simplicity, unmatched RM and OS page + // sizes are not currently supported in this path, except for + // PPC64LE and aarch64. + // + // Also, the nvmap handle is sent which can be any random number so + // the virtual address alignment sanity check can't be done here. + // + if (!NVCPU_IS_PPC64LE && + !NVCPU_IS_AARCH64 && + (NV_RM_PAGE_SIZE != os_page_size)) + { + return NV_ERR_NOT_SUPPORTED; + } + + // + // The two checks below use cached privilege because they + // concern the privilege level of the client, and not the + // privilege level of the calling context which may be + // overridden to KERNEL at some internal callsites. + // + + // + // The RM cannot obtain a table of physical addresses + // for a kernel virtual address range on all of + // the supported UNIX platforms. Since this path is + // not really compelling for kernel allocations on any + // of those platforms, it is not supported. + // For UVM, they could have pre-allocated sysmem to register + // with RM so we put in an exception for that case. + // + if ((rmclientGetCachedPrivilege(pClient) >= RS_PRIV_LEVEL_KERNEL) && + (descriptorType != NVOS32_DESCRIPTOR_TYPE_OS_PHYS_ADDR) && + (descriptorType != NVOS32_DESCRIPTOR_TYPE_OS_FILE_HANDLE) && + (descriptorType != NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR) && + (descriptorType != NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR)) + { + return NV_ERR_NOT_SUPPORTED; + } + + // + // NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR and + // NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR can only be utilized by kernel space + // rm-clients. + // + if ((rmclientGetCachedPrivilege(pClient) < RS_PRIV_LEVEL_KERNEL) && + ((descriptorType == NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR) || + (descriptorType == NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR))) + { + return NV_ERR_NOT_SUPPORTED; + } + + switch (descriptorType) + { + case NVOS32_DESCRIPTOR_TYPE_VIRTUAL_ADDRESS: + rmStatus = NV_ERR_NOT_SUPPORTED; + break; + case NVOS32_DESCRIPTOR_TYPE_OS_PHYS_ADDR: + if (privilegeLevel < RS_PRIV_LEVEL_KERNEL) + { + rmStatus = NV_ERR_NOT_SUPPORTED; + break; + } + rmStatus = osCreateOsDescriptorFromPhysAddr(pGpu, pDescriptor, + hClient, flags, pLimit, ppMemDesc, &pPrivate); + break; + case NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY: + rmStatus = osCreateOsDescriptorFromIoMemory(pGpu, pDescriptor, + hClient, flags, pLimit, ppMemDesc, &pPrivate); + break; + case NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY: + rmStatus = osCreateOsDescriptorFromPageArray(pGpu, pDescriptor, + hClient, flags, pLimit, ppMemDesc, &pPrivate); + break; + case NVOS32_DESCRIPTOR_TYPE_OS_FILE_HANDLE: + rmStatus = osCreateOsDescriptorFromFileHandle(pGpu, pDescriptor, + hClient, flags, pLimit, ppMemDesc, &pPrivate); + break; + case NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR: + rmStatus = osCreateOsDescriptorFromDmaBufPtr(pGpu, pDescriptor, + hClient, flags, pLimit, ppMemDesc, &pPrivate); + break; + case NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR: + rmStatus = osCreateOsDescriptorFromSgtPtr(pGpu, pDescriptor, + hClient, flags, pLimit, ppMemDesc, &pPrivate); + break; + default: + rmStatus = NV_ERR_INVALID_ARGUMENT; + break; + } + + return rmStatus; +} + +static NV_STATUS +osCreateMemdescFromPages +( + OBJGPU *pGpu, + NvU64 size, + NvU32 flags, + NvU32 cacheType, + MEMORY_DESCRIPTOR **ppMemDesc, + void *pImportPriv, + void **ppPrivate +) +{ + NV_STATUS rmStatus; + MEMORY_DESCRIPTOR *pMemDesc; + NvU64 memdescFlags = MEMDESC_FLAGS_NONE; + NvU32 gpuCachedFlags; + + if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_NISO_DISPLAY, _YES, flags)) + { + memdescFlags |= MEMDESC_FLAGS_MEMORY_TYPE_DISPLAY_NISO; + } + + rmStatus = memdescCreate(ppMemDesc, pGpu, size, 0, + NV_MEMORY_NONCONTIGUOUS, ADDR_SYSMEM, + cacheType, memdescFlags); + if (rmStatus != NV_OK) + { + return rmStatus; + } + + if (FLD_TEST_DRF(OS02, _FLAGS, _GPU_CACHEABLE, _YES, flags)) + gpuCachedFlags = NV_MEMORY_CACHED; + else + gpuCachedFlags = NV_MEMORY_UNCACHED; + + pMemDesc = *ppMemDesc; + rmStatus = nv_register_user_pages(NV_GET_NV_STATE(pGpu), + NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount), + memdescGetPteArray(pMemDesc, AT_CPU), pImportPriv, + ppPrivate); + if (rmStatus != NV_OK) + { + memdescDestroy(pMemDesc); + return rmStatus; + } + + memdescSetGpuCacheAttrib(pMemDesc, gpuCachedFlags); + memdescSetAddress(pMemDesc, NvP64_NULL); + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_KERNEL_MODE, NV_FALSE); + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_EXT_PAGE_ARRAY_MEM, NV_TRUE); + + // + // If the OS layer doesn't think in RM page size, we need to inflate the + // PTE array into RM pages. + // + if ((NV_RM_PAGE_SIZE < os_page_size) && + !memdescGetContiguity(pMemDesc, AT_CPU)) + { + RmInflateOsToRmPageArray(memdescGetPteArray(pMemDesc, AT_CPU), + pMemDesc->PageCount); + } + + // + // memdescMapIommu() requires the OS-private data to be set on the memory + // descriptor, but we don't want to wire up the teardown callback just yet: + // that callback needs to unpin the pages, but that will already be done + // as part of failure handling further up the stack if memdescMapIommu() + // fails. So we only set up the priv-data cleanup callback once we're sure + // this call will succeed. + // + memdescSetMemData(pMemDesc, *ppPrivate, NULL); + + rmStatus = memdescMapIommu(pMemDesc, pGpu->busInfo.iovaspaceId); + if (rmStatus != NV_OK) + { + if ((NV_RM_PAGE_SIZE < os_page_size) && + !memdescGetContiguity(pMemDesc, AT_CPU)) + { + RmDeflateRmToOsPageArray(memdescGetPteArray(pMemDesc, AT_CPU), + pMemDesc->PageCount); + } + + nv_unregister_user_pages(NV_GET_NV_STATE(pGpu), + NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount), + NULL /* import_priv */, ppPrivate); + memdescDestroy(pMemDesc); + return rmStatus; + } + + return NV_OK; +} + +static NV_STATUS +osCreateOsDescriptorFromPageArray +( + OBJGPU *pGpu, + NvP64 pDescriptor, + NvHandle hClient, + NvU32 flags, + NvU64 *pLimit, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppPrivate +) +{ + NV_STATUS rmStatus; + + *ppPrivate = NvP64_VALUE(pDescriptor); + + // + // Since the only type of memory permitted in this path + // is anonymous user memory, certain restrictions + // apply for the allocation flags: + // + // 1) anonymous memory is write-back cacheable, hence + // the _COHERENCY flag must match. + // + // 2) the RM has no control over the location of the + // associated pages in memory and thus cannot + // honor requests for contiguous memory. + // + // These restrictions are enforced here to avoid subtle + // bugs later on. + // + if ((!FLD_TEST_DRF(OS02, _FLAGS, _COHERENCY, _CACHED, flags) && + !FLD_TEST_DRF(OS02, _FLAGS, _COHERENCY, _WRITE_BACK, flags)) || + FLD_TEST_DRF(OS02, _FLAGS, _PHYSICALITY, _CONTIGUOUS, flags)) + { + return NV_ERR_INVALID_FLAGS; + } + + rmStatus = osCreateMemdescFromPages(pGpu, (*pLimit + 1), flags, + NV_MEMORY_CACHED, ppMemDesc, + NULL /* pImportPriv */, ppPrivate); + if (rmStatus != NV_OK) + { + return rmStatus; + } + + // All is well - wire up the cleanup callback now + memdescSetMemData(*ppMemDesc, memdescGetMemData(*ppMemDesc), + osDestroyOsDescriptorPageArray); + + return NV_OK; +} + +/*! + * @brief Checks if the given address range overlaps with the BARs for any of + * the GPUs. + */ +static NV_STATUS +osCheckGpuBarsOverlapAddrRange +( + NvRangeU64 addrRange +) +{ + NvRangeU64 gpuPhysAddrRange; + NvRangeU64 gpuPhysFbAddrRange; + NvRangeU64 gpuPhysInstAddrRange; + NvU32 gpuInstance; + OBJGPU *pGpu; + NvU32 gpuMask; + NV_STATUS rmStatus; + + rmStatus = gpumgrGetGpuAttachInfo(NULL, &gpuMask); + NV_ASSERT_OR_RETURN(rmStatus == NV_OK, rmStatus); + + gpuInstance = 0; + while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + NV_INIT_RANGE(gpuPhysFbAddrRange, gpumgrGetGpuPhysFbAddr(pGpu), + gpumgrGetGpuPhysFbAddr(pGpu) + pGpu->fbLength -1); + + NV_INIT_RANGE(gpuPhysAddrRange, pGpu->busInfo.gpuPhysAddr, + pGpu->busInfo.gpuPhysAddr + pGpu->deviceMappings[0].gpuNvLength -1); + + NV_INIT_RANGE(gpuPhysInstAddrRange, pGpu->busInfo.gpuPhysInstAddr, + pGpu->busInfo.gpuPhysInstAddr + pGpu->instLength -1); + + if (NV_IS_OVERLAPPING_RANGE(gpuPhysFbAddrRange, addrRange) || + NV_IS_OVERLAPPING_RANGE(gpuPhysAddrRange, addrRange) || + NV_IS_OVERLAPPING_RANGE(gpuPhysInstAddrRange, addrRange)) + { + return NV_ERR_INVALID_ADDRESS; + } + } + + return NV_OK; +} + +static NV_STATUS +osCreateOsDescriptorFromIoMemory +( + OBJGPU *pGpu, + NvP64 pDescriptor, + NvHandle hClient, + NvU32 flags, + NvU64 *pLimit, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppPrivate +) +{ + NV_STATUS rmStatus; + NvU32 gpuCachedFlags; + MEMORY_DESCRIPTOR *pMemDesc; + NvU64 *pPteArray; + NvRangeU64 physAddrRange; + NvU64 *base = 0; + NvBool bAllowMmap; + + // + // Unlike the page array path, this one deals exclusively + // with I/O memory, which is expected to be contiguous + // physically, and which may only be accessed with uncached + // transactions. + // + if (!FLD_TEST_DRF(OS02, _FLAGS, _COHERENCY, _UNCACHED, flags) || + !FLD_TEST_DRF(OS02, _FLAGS, _PHYSICALITY, _CONTIGUOUS, flags)) + { + return NV_ERR_INVALID_FLAGS; + } + + // + // _PEER_MAP_OVERRIDE flag is controlled by the RM and not the client. + // + // RM will set the _PEER_MAP_OVERRIDE_REQUIRED flag itself for IO memory + // memory imported with RmVidHeapControl. + // + if (FLD_TEST_DRF(OS02, _FLAGS, _PEER_MAP_OVERRIDE, _REQUIRED, flags)) + { + // + // Don't allow MMIO mappings for unprivileged users + // This is a temporary WAR for bug 1630288 "[PeerSync] threat related + // to GPU" + // + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + if (!pKernelBif->peerMappingOverride && !osIsAdministrator()) + { + NV_PRINTF(LEVEL_ERROR, + "%s(): permission denied, allowPeermapping=%d\n", + __FUNCTION__, pKernelBif->peerMappingOverride); + return NV_ERR_INSUFFICIENT_PERMISSIONS; + } + } + + bAllowMmap = !FLD_TEST_DRF(OS02, _FLAGS, _MAPPING, _NEVER_MAP, flags); + + base = (void *)(NvUPtr)pDescriptor; + + // + // There is an architectural deadlock scenario involved when full-duplex P2P + // enabled over BAR1. See #3 in the description of bug 1571948 which explains + // the classic deadlock. So, make sure to error out usermode's memory + // registration if a memory range falls within any of the available GPU's + // BAR window. + // + physAddrRange.min = *base; + physAddrRange.max = *base + *pLimit; + + rmStatus = osCheckGpuBarsOverlapAddrRange(physAddrRange); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s(): phys range 0x%016llx-0x%016llx overlaps with GPU BARs", + __FUNCTION__, physAddrRange.min, physAddrRange.max); + return rmStatus; + } + + rmStatus = memdescCreate(ppMemDesc, pGpu, (*pLimit + 1), 0, + NV_MEMORY_CONTIGUOUS, ADDR_SYSMEM, + NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s(): error %d while attempting to create the MMIO mapping\n", + __FUNCTION__, rmStatus); + return rmStatus; + } + + pMemDesc = *ppMemDesc; + + if (FLD_TEST_DRF(OS02, _FLAGS, _GPU_CACHEABLE, _YES, flags)) + gpuCachedFlags = NV_MEMORY_CACHED; + else + gpuCachedFlags = NV_MEMORY_UNCACHED; + + memdescSetGpuCacheAttrib(pMemDesc, gpuCachedFlags); + memdescSetAddress(pMemDesc, NvP64_NULL); + memdescSetMemData(pMemDesc, NULL, NULL); + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_KERNEL_MODE, NV_FALSE); + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_PEER_IO_MEM, NV_TRUE); + + pPteArray = memdescGetPteArray(pMemDesc, AT_CPU); + pPteArray[0] = *base; + + *ppPrivate = NULL; + + if (bAllowMmap) + { + rmStatus = nv_register_peer_io_mem(NV_GET_NV_STATE(pGpu), pPteArray, + NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount), + ppPrivate); + if (rmStatus != NV_OK) + { + memdescDestroy(pMemDesc); + return rmStatus; + } + } + + memdescSetMemData(pMemDesc, *ppPrivate, NULL); + + // + // memdescMapIommu() requires the OS-private data to be set on the memory + // descriptor, but we don't want to wire up the teardown callback just yet: + // that callback needs to unpin the pages, but that will already be done + // as part of failure handling further up the stack if memdescMapIommu() + // fails. So we only set up the priv-data cleanup callback once we're sure + // this call will succeed. + // + rmStatus = memdescMapIommu(pMemDesc, pGpu->busInfo.iovaspaceId); + if (rmStatus != NV_OK) + { + if (*ppPrivate != NULL) + { + nv_unregister_peer_io_mem(NV_GET_NV_STATE(pGpu), *ppPrivate); + } + memdescDestroy(pMemDesc); + return rmStatus; + } + + // All is well - wire up the cleanup callback now + memdescSetMemData(pMemDesc, memdescGetMemData(pMemDesc), + osDestroyOsDescriptorFromIoMemory); + + return NV_OK; +} + +static NV_STATUS +osCreateOsDescriptorFromPhysAddr +( + OBJGPU *pGpu, + NvP64 pDescriptor, + NvHandle hClient, + NvU32 flags, + NvU64 *pLimit, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppPrivate +) +{ + NV_STATUS rmStatus; + MEMORY_DESCRIPTOR *pMemDesc; + NvU64 *pPteArray; + NvU64 base = 0; + NvU32 cache_type = NV_MEMORY_CACHED; + NvU64 memdescFlags = MEMDESC_FLAGS_NONE; + NvU64 *pPhys_addrs; + NvU64 num_os_pages; + NvU32 idx; + // Currently only work with contiguous sysmem allocations + if (!FLD_TEST_DRF(OS02, _FLAGS, _PHYSICALITY, _CONTIGUOUS, flags)) + { + return NV_ERR_INVALID_FLAGS; + } + + if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_TYPE_SYNCPOINT, _APERTURE, flags)) + { + // Syncpoint memory is uncached, DMA mapping needs to skip CPU sync. + cache_type = NV_MEMORY_UNCACHED; + } + + if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_NISO_DISPLAY, _YES, flags)) + { + memdescFlags |= MEMDESC_FLAGS_MEMORY_TYPE_DISPLAY_NISO; + } + + base = (NvU64)pDescriptor; + rmStatus = memdescCreate(ppMemDesc, pGpu, (*pLimit + 1), 0, + NV_MEMORY_CONTIGUOUS, ADDR_SYSMEM, + cache_type, memdescFlags); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s(): error %d while creating memdesc for kernel memory\n", + __FUNCTION__, rmStatus); + return rmStatus; + } + + pMemDesc = *ppMemDesc; + + memdescSetAddress(pMemDesc, NvP64_NULL); + memdescSetMemData(pMemDesc, NULL, NULL); + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_EXT_PAGE_ARRAY_MEM, NV_TRUE); + + pPteArray = memdescGetPteArray(pMemDesc, AT_CPU); + pPteArray[0] = base; + + num_os_pages = NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount); + pPhys_addrs = portMemAllocNonPaged(sizeof(NvU64) * num_os_pages); + if (pPhys_addrs == NULL) + return NV_ERR_NO_MEMORY; + + for (idx = 0; idx < num_os_pages; idx++) + { + pPhys_addrs[idx] = base + (idx * os_page_size); + } + + *ppPrivate = NULL; + rmStatus = nv_register_phys_pages(NV_GET_NV_STATE(pGpu), pPhys_addrs, + num_os_pages, + memdescGetCpuCacheAttrib(pMemDesc), + ppPrivate); + if (rmStatus != NV_OK) + { + memdescDestroy(pMemDesc); + goto cleanup; + } + + memdescSetMemData(pMemDesc, *ppPrivate, + osDestroyOsDescriptorFromPhysAddr); + +cleanup: + portMemFree(pPhys_addrs); + + return rmStatus; +} + +static NV_STATUS +_createMemdescFromDmaBufSgtHelper +( + OBJGPU *pGpu, + NvU32 flags, + void *pImportPriv, + struct sg_table *pImportSgt, + NvU32 size, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppPrivate, + MEM_DATA_RELEASE_CALL_BACK *pMemDataReleaseCallback +) +{ + NV_STATUS rmStatus = NV_OK; + NvU32 cacheType = NV_MEMORY_UNCACHED; + MEMORY_DESCRIPTOR *pMemDesc; + NvU64 memdescFlags = MEMDESC_FLAGS_NONE; + NvU32 gpuCachedFlags; + + NV_ASSERT((pMemDataReleaseCallback == osDestroyOsDescriptorFromDmaBuf) || + (pMemDataReleaseCallback == osDestroyOsDescriptorFromSgt)); + + if (FLD_TEST_DRF(OS02, _FLAGS, _COHERENCY, _WRITE_COMBINE, flags)) + { + cacheType = NV_MEMORY_WRITECOMBINED; + } + else if (!FLD_TEST_DRF(OS02, _FLAGS, _COHERENCY, _UNCACHED, flags)) + { + cacheType = NV_MEMORY_CACHED; + } + + if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_NISO_DISPLAY, _YES, flags)) + { + memdescFlags |= MEMDESC_FLAGS_MEMORY_TYPE_DISPLAY_NISO; + } + + rmStatus = memdescCreate(ppMemDesc, pGpu, size, 0, + NV_MEMORY_NONCONTIGUOUS, ADDR_SYSMEM, + cacheType, memdescFlags); + if (rmStatus != NV_OK) + { + return rmStatus; + } + + if (FLD_TEST_DRF(OS02, _FLAGS, _GPU_CACHEABLE, _YES, flags)) + { + gpuCachedFlags = NV_MEMORY_CACHED; + } + else + { + gpuCachedFlags = NV_MEMORY_UNCACHED; + } + + pMemDesc = *ppMemDesc; + + memdescSetGpuCacheAttrib(pMemDesc, gpuCachedFlags); + memdescSetAddress(pMemDesc, NvP64_NULL); + memdescSetMemData(pMemDesc, NULL, NULL); + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_KERNEL_MODE, NV_FALSE); + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_EXT_PAGE_ARRAY_MEM, NV_TRUE); + + *ppPrivate = NULL; + rmStatus = nv_register_sgt(NV_GET_NV_STATE(pGpu), + memdescGetPteArray(pMemDesc, AT_CPU), + NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount), + memdescGetCpuCacheAttrib(pMemDesc), + ppPrivate, + pImportSgt, + pImportPriv); + if (rmStatus != NV_OK) + { + memdescDestroy(pMemDesc); + return rmStatus; + } + + // + // If the OS layer doesn't think in RM page size, we need to inflate the + // PTE array into RM pages. + // + if ((NV_RM_PAGE_SIZE < os_page_size) && + !memdescGetContiguity(pMemDesc, AT_CPU)) + { + RmInflateOsToRmPageArray(memdescGetPteArray(pMemDesc, AT_CPU), + pMemDesc->PageCount); + } + + memdescSetMemData(*ppMemDesc, *ppPrivate, NULL); + + // + // memdescMapIommu() requires the OS-private data to be set on the memory + // descriptor, but we don't want to wire up the teardown callback just yet: + // that callback does teardown that will already be done as part of failure + // handling further up the stack if memdescMapIommu() fails. So we only + // setup the priv-data cleanup callback once we're sure this call will + // succeed. + // + rmStatus = memdescMapIommu(*ppMemDesc, pGpu->busInfo.iovaspaceId); + if (rmStatus != NV_OK) + { + if ((NV_RM_PAGE_SIZE < os_page_size) && + !memdescGetContiguity(pMemDesc, AT_CPU)) + { + RmDeflateRmToOsPageArray(memdescGetPteArray(pMemDesc, AT_CPU), + pMemDesc->PageCount); + } + if (*ppPrivate != NULL) + { + nv_unregister_sgt(NV_GET_NV_STATE(pGpu), &pImportSgt, + (void **) &pImportPriv, *ppPrivate); + } + memdescDestroy(pMemDesc); + return rmStatus; + } + + // All is well - wire up the cleanup callback now + memdescSetMemData(*ppMemDesc, *ppPrivate, pMemDataReleaseCallback); + + return rmStatus; +} + +static NV_STATUS +_createMemdescFromDmaBuf +( + OBJGPU *pGpu, + NvU32 flags, + nv_dma_buf_t *pImportPriv, + void *pUserPages, + struct sg_table *pImportSgt, + NvU32 size, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppPrivate +) +{ + NV_STATUS rmStatus = + _createMemdescFromDmaBufSgtHelper(pGpu, flags, pImportPriv, pImportSgt, + size, ppMemDesc, ppPrivate, + osDestroyOsDescriptorFromDmaBuf); + + NV_ASSERT(pUserPages == NULL); + + if (rmStatus != NV_OK) + { + nv_dma_release_dma_buf(NULL, pImportPriv); + } + + return rmStatus; +} + +static NV_STATUS +_createMemdescFromSgt +( + OBJGPU *pGpu, + NvU32 flags, + struct drm_gem_object *pImportPrivGem, + struct sg_table *pImportSgt, + NvU32 size, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppPrivate +) +{ + NV_STATUS rmStatus = + _createMemdescFromDmaBufSgtHelper(pGpu, flags, pImportPrivGem, + pImportSgt, size, ppMemDesc, + ppPrivate, + osDestroyOsDescriptorFromSgt); + if (rmStatus != NV_OK) + { + nv_dma_release_sgt(pImportSgt, pImportPrivGem); + } + + return rmStatus; +} + +static NV_STATUS +osCreateOsDescriptorFromFileHandle +( + OBJGPU *pGpu, + NvP64 pDescriptor, + NvHandle hClient, + NvU32 flags, + NvU64 *pLimit, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppPrivate +) +{ + NV_STATUS rmStatus = NV_OK; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + NvU32 size = 0; + void *pUserPages = NULL; + nv_dma_buf_t *pImportPriv = NULL; + struct sg_table *pImportSgt = NULL; + NvS32 fd; + + fd = (NvS32)((NvU64)pDescriptor); + if ((NvU64)fd != (NvU64)pDescriptor) + { + NV_PRINTF(LEVEL_ERROR, + "%s(): fd must fit within a signed 32-bit integer!\n", + __FUNCTION__); + return NV_ERR_INVALID_ARGUMENT; + } + + rmStatus = nv_dma_import_from_fd(nv->dma_dev, fd, &size, + &pUserPages, &pImportSgt, &pImportPriv); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s(): Error (%d) while trying to import fd!\n", + __FUNCTION__, rmStatus); + return rmStatus; + } + + return _createMemdescFromDmaBuf(pGpu, flags, pImportPriv, + pUserPages, pImportSgt, + size, ppMemDesc, ppPrivate); +} + +static NV_STATUS +osCreateOsDescriptorFromSgtPtr +( + OBJGPU *pGpu, + NvP64 pDescriptor, + NvHandle hClient, + NvU32 flags, + NvU64 *pLimit, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppPrivate +) +{ + NV_STATUS rmStatus = NV_OK; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS *params = + (NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS*)((NvUPtr) pDescriptor); + + struct sg_table *sgt = params->sgt; + struct drm_gem_object *gem = params->gem; + + rmStatus = nv_dma_import_sgt(nv->dma_dev, sgt, gem); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s(): Error (%d) while trying to import sgt!\n", + __FUNCTION__, rmStatus); + return rmStatus; + } + + return _createMemdescFromSgt(pGpu, flags, gem, sgt, + (*pLimit + 1), ppMemDesc, ppPrivate); +} + +static NV_STATUS +osCreateOsDescriptorFromDmaBufPtr +( + OBJGPU *pGpu, + NvP64 pDescriptor, + NvHandle hClient, + NvU32 flags, + NvU64 *pLimit, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppPrivate +) +{ + NV_STATUS rmStatus = NV_OK; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + NvU32 size = 0; + void *pUserPages = NULL; + nv_dma_buf_t *pImportPriv = NULL; + struct sg_table *pImportSgt = NULL; + void *dmaBuf = (void*)((NvUPtr)pDescriptor); + + rmStatus = nv_dma_import_dma_buf(nv->dma_dev, dmaBuf, &size, + &pUserPages, &pImportSgt, &pImportPriv); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s(): Error (%d) while trying to import dma_buf!\n", + __FUNCTION__, rmStatus); + return rmStatus; + } + + return _createMemdescFromDmaBuf(pGpu, flags, pImportPriv, + pUserPages, pImportSgt, + size, ppMemDesc, ppPrivate); +} + +static void +osDestroyOsDescriptorFromPhysAddr +( + PMEMORY_DESCRIPTOR pMemDesc +) +{ + OBJGPU *pGpu = pMemDesc->pGpu; + void *pPrivate; + + pPrivate = memdescGetMemData(pMemDesc); + NV_ASSERT(pPrivate != NULL); + + nv_unregister_phys_pages(NV_GET_NV_STATE(pGpu), pPrivate); +} + +static void +osDestroyOsDescriptorFromIoMemory +( + PMEMORY_DESCRIPTOR pMemDesc +) +{ + OBJGPU *pGpu = pMemDesc->pGpu; + void *pPrivate = memdescGetMemData(pMemDesc); + + if (pPrivate == NULL) + { + return; + } + + nv_unregister_peer_io_mem(NV_GET_NV_STATE(pGpu), pPrivate); +} + +static void +osDestroyOsDescriptorPageArray +( + MEMORY_DESCRIPTOR *pMemDesc +) +{ + OBJGPU *pGpu = pMemDesc->pGpu; + NvU64 osPageCount = NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount); + NV_STATUS status; + void *pPrivate; + + pPrivate = memdescGetMemData(pMemDesc); + + NV_ASSERT(pPrivate != NULL); + + // + // TODO: Bug 1811006: Notably skip any IOMMU mapping management as the + // pMemDesc->pGpu might have been torn down already and the pGpu passed in + // doesn't necessarily have IOMMU mappings. For now just allow memdescDestroy() + // to clean up whatever is there (this may not work correctly either if any + // of the IOMMU mappings have outlasted their VASPACEs). This should + // be cleaned up once the fix for bug 1811006 is known. + // + + if ((NV_RM_PAGE_SIZE < os_page_size) && + !memdescGetContiguity(pMemDesc, AT_CPU)) + { + RmDeflateRmToOsPageArray(memdescGetPteArray(pMemDesc, AT_CPU), + pMemDesc->PageCount); + } + + nv_unregister_user_pages(NV_GET_NV_STATE(pGpu), osPageCount, + NULL /* import_priv */, &pPrivate); + + if (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_FOREIGN_PAGE) == NV_FALSE) + { + status = os_unlock_user_pages(osPageCount, pPrivate); + NV_ASSERT(status == NV_OK); + } + else + { + os_free_mem(pPrivate); + } +} + +static void +osDestroyOsDescriptorFromDmaBuf +( + PMEMORY_DESCRIPTOR pMemDesc +) +{ + OBJGPU *pGpu = pMemDesc->pGpu; + void *pPrivate = memdescGetMemData(pMemDesc); + + struct sg_table *pImportSgt; + void *pImportPriv; + + /* + * Unmap IOMMU now or we will get a kernel crash when it is unmapped after + * pImportSgt is freed. + */ + memdescUnmapIommu(pMemDesc, pGpu->busInfo.iovaspaceId); + + if ((NV_RM_PAGE_SIZE < os_page_size) && + !memdescGetContiguity(pMemDesc, AT_CPU)) + { + RmDeflateRmToOsPageArray(memdescGetPteArray(pMemDesc, AT_CPU), + pMemDesc->PageCount); + } + + nv_unregister_sgt(NV_GET_NV_STATE(pGpu), &pImportSgt, + &pImportPriv, pPrivate); + + /* + * pImportSgt doesn't need to be passed to nv_dma_release_dma_buf() because + * the DMA-BUF associated with pImportPriv already has a reference to the + * SGT. + */ + + nv_dma_release_dma_buf(NULL, pImportPriv); +} + +static void +osDestroyOsDescriptorFromSgt +( + PMEMORY_DESCRIPTOR pMemDesc +) +{ + OBJGPU *pGpu = pMemDesc->pGpu; + void *pPrivate = memdescGetMemData(pMemDesc); + + struct sg_table *pImportSgt; + struct drm_gem_object *pImportPrivGem; + + NV_ASSERT(pPrivate != NULL); + + /* + * Unmap IOMMU now or we will get a kernel crash when it is unmapped after + * pImportSgt is freed. + */ + memdescUnmapIommu(pMemDesc, pGpu->busInfo.iovaspaceId); + + if ((NV_RM_PAGE_SIZE < os_page_size) && + !memdescGetContiguity(pMemDesc, AT_CPU)) + { + RmDeflateRmToOsPageArray(memdescGetPteArray(pMemDesc, AT_CPU), + pMemDesc->PageCount); + } + + nv_unregister_sgt(NV_GET_NV_STATE(pGpu), &pImportSgt, + (void **) &pImportPrivGem, pPrivate); + + nv_dma_release_sgt(pImportSgt, pImportPrivGem); +} diff --git a/userspace/sdks/nv525/nvalloc/unix/src/osnvlink.c b/userspace/sdks/nv525/nvalloc/unix/src/osnvlink.c new file mode 100644 index 0000000..2d597a1 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/src/osnvlink.c @@ -0,0 +1,698 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "osapi.h" + +#if defined(INCLUDE_NVLINK_LIB) +#include "nvlink.h" +// +// The functions in this file are a workaround for a significant design flaw +// where RM callbacks for the nvlink library are built with the altstack +// enabled, but the nvlink library is not built with altstack support. Whenever +// the library calls a callback, the stack switching needs to be accounted for +// or else we will observe corruption of data structures in the nvlink library +// as data is pushed onto what the callback thinks is the stack. See bug +// 1710300. +// +// This bug has also exposed other problems, such as the complete lack of +// locking awareness by these callbacks (e.g., assumption that the RMAPI and +// GPU locks are always held on entry, which is not a legitimate assumption). +// For now, we ignore that just to unblock testing. +// +extern NvlStatus knvlinkCoreAddLinkCallback(struct nvlink_link *); +extern NvlStatus knvlinkCoreRemoveLinkCallback(struct nvlink_link *); +extern NvlStatus knvlinkCoreLockLinkCallback(struct nvlink_link *); +extern void knvlinkCoreUnlockLinkCallback(struct nvlink_link *); +extern NvlStatus knvlinkCoreQueueLinkChangeCallback(struct nvlink_link_change *); +extern NvlStatus knvlinkCoreSetDlLinkModeCallback(struct nvlink_link *, NvU64, NvU32); +extern NvlStatus knvlinkCoreGetDlLinkModeCallback(struct nvlink_link *, NvU64 *); +extern NvlStatus knvlinkCoreSetTlLinkModeCallback(struct nvlink_link *, NvU64, NvU32); +extern NvlStatus knvlinkCoreGetTlLinkModeCallback(struct nvlink_link *, NvU64 *); +extern NvlStatus knvlinkCoreGetTxSublinkModeCallback(struct nvlink_link *, NvU64 *, NvU32 *); +extern NvlStatus knvlinkCoreSetTxSublinkModeCallback(struct nvlink_link *, NvU64, NvU32); +extern NvlStatus knvlinkCoreGetRxSublinkModeCallback(struct nvlink_link *, NvU64 *, NvU32 *); +extern NvlStatus knvlinkCoreSetRxSublinkModeCallback(struct nvlink_link *, NvU64, NvU32); +extern NvlStatus knvlinkCoreReadDiscoveryTokenCallback(struct nvlink_link *, NvU64 *); +extern NvlStatus knvlinkCoreWriteDiscoveryTokenCallback(struct nvlink_link *, NvU64); +extern void knvlinkCoreTrainingCompleteCallback(struct nvlink_link *); +extern void knvlinkCoreGetUphyLoadCallback(struct nvlink_link *, NvBool*); + +/*! + * @brief Helper to allocate an alternate stack from within core RM. + * + * This needs to be an NV_API_CALL (built to use the original stack instead + * of the altstack) since it is called before we switch to using the altstack. + */ +static NV_STATUS NV_API_CALL osNvlinkAllocAltStack(nvidia_stack_t **pSp) +{ + NV_STATUS status = NV_OK; + nvidia_stack_t *sp = NULL; +#if defined(NVCPU_X86_64) && defined(__use_altstack__) + status = os_alloc_mem((void **)&sp, sizeof(nvidia_stack_t)); + if (status == NV_OK) + { + sp->size = sizeof(sp->stack); + sp->top = sp->stack + sp->size; + } +#endif + *pSp = sp; + return status; +} + +/*! + * @brief Helper to free an alternate stack from within core RM. + * + * This needs to be an NV_API_CALL (built to use the original stack instead + * of the altstack) since it is called after we've switched back to using the + * original stack. + */ +static void NV_API_CALL osNvlinkFreeAltStack(nvidia_stack_t *sp) +{ +#if defined(NVCPU_X86_64) && defined(__use_altstack__) + os_free_mem(sp); +#endif +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_add_link +( + struct nvlink_link *link +) +{ + void *fp; + NvlStatus status; + KNVLINK_RM_LINK *pLink = link->link_info; + nvidia_stack_t *sp; + + if (NV_OK != osNvlinkAllocAltStack(&sp)) + { + return NVL_ERR_GENERIC; + } + + NV_ENTER_RM_RUNTIME(sp, fp); + + status = knvlinkCoreAddLinkCallback(link); + + NV_EXIT_RM_RUNTIME(sp, fp); + + if (status == NVL_SUCCESS) + { + pLink->pOsInfo = sp; + } + else + { + osNvlinkFreeAltStack(sp); + } + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_remove_link +( + struct nvlink_link *link +) +{ + void *fp; + NvlStatus status; + KNVLINK_RM_LINK *pLink = link->link_info; + nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + + pLink->pOsInfo = NULL; + + NV_ENTER_RM_RUNTIME(sp, fp); + + status = knvlinkCoreRemoveLinkCallback(link); + + NV_EXIT_RM_RUNTIME(sp, fp); + + osNvlinkFreeAltStack(sp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_lock_link +( + struct nvlink_link *link +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + KNVLINK_RM_LINK *pLink = link->link_info; + nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreLockLinkCallback(link); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + return status; +} + +static void NV_API_CALL rm_nvlink_ops_unlock_link +( + struct nvlink_link *link +) +{ + void *fp; + THREAD_STATE_NODE threadState = {0}; + KNVLINK_RM_LINK *pLink = link->link_info; + nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + knvlinkCoreUnlockLinkCallback(link); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_queue_link_change +( + struct nvlink_link_change *link_change +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + KNVLINK_RM_LINK *pLink = link_change->master->link_info; + nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreQueueLinkChangeCallback(link_change); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_set_dl_link_mode +( + struct nvlink_link *link, + NvU64 mode, + NvU32 flags +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + KNVLINK_RM_LINK *pLink = link->link_info; + nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreSetDlLinkModeCallback(link, mode, flags); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_get_dl_link_mode +( + struct nvlink_link *link, + NvU64 *mode +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + KNVLINK_RM_LINK *pLink = link->link_info; + nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreGetDlLinkModeCallback(link, mode); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_set_tl_link_mode +( + struct nvlink_link *link, + NvU64 mode, + NvU32 flags +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + KNVLINK_RM_LINK *pLink = link->link_info; + nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreSetTlLinkModeCallback(link, mode, flags); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_get_tl_link_mode +( + struct nvlink_link *link, + NvU64 *mode +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + KNVLINK_RM_LINK *pLink = link->link_info; + nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreGetTlLinkModeCallback(link, mode); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_set_link_tx_mode +( + struct nvlink_link *link, + NvU64 mode, + NvU32 flags +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + KNVLINK_RM_LINK *pLink = link->link_info; + nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreSetTxSublinkModeCallback(link, mode, flags); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_get_link_tx_mode +( + struct nvlink_link *link, + NvU64 *mode, + NvU32 *subMode +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + KNVLINK_RM_LINK *pLink = link->link_info; + nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreGetTxSublinkModeCallback(link, mode, subMode); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_set_link_rx_mode +( + struct nvlink_link *link, + NvU64 mode, + NvU32 flags +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + KNVLINK_RM_LINK *pLink = link->link_info; + nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreSetRxSublinkModeCallback(link, mode, flags); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_get_link_rx_mode +( + struct nvlink_link *link, + NvU64 *mode, + NvU32 *subMode +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + KNVLINK_RM_LINK *pLink = link->link_info; + nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreGetRxSublinkModeCallback(link, mode, subMode); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_set_link_rx_detect +( + struct nvlink_link *link, + NvU32 flags +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + KNVLINK_RM_LINK *pLink = link->link_info; + nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreSetRxSublinkDetectCallback(link, flags); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_get_link_rx_detect +( + struct nvlink_link *link +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + KNVLINK_RM_LINK *pLink = link->link_info; + nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreGetRxSublinkDetectCallback(link); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + return status; +} + +static void NV_API_CALL rm_nvlink_get_uphy_load +( + struct nvlink_link *link, + NvBool *bUnlocked +) +{ + void *fp; + THREAD_STATE_NODE threadState = {0}; + KNVLINK_RM_LINK *pLink = link->link_info; + nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + knvlinkCoreGetUphyLoadCallback(link, bUnlocked); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_read_link_discovery_token +( + struct nvlink_link *link, + NvU64 *token +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + KNVLINK_RM_LINK *pLink = link->link_info; + nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreReadDiscoveryTokenCallback(link, token); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_write_link_discovery_token +( + struct nvlink_link *link, + NvU64 token +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + KNVLINK_RM_LINK *pLink = link->link_info; + nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreWriteDiscoveryTokenCallback(link, token); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + return status; +} + +static void NV_API_CALL rm_nvlink_ops_training_complete +( + struct nvlink_link *link +) +{ + void *fp; + THREAD_STATE_NODE threadState = {0}; + KNVLINK_RM_LINK *pLink = link->link_info; + nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + knvlinkCoreTrainingCompleteCallback(link); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_ali_training +( + struct nvlink_link *link +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + KNVLINK_RM_LINK * pLink = link->link_info; + nvidia_stack_t * sp = (nvidia_stack_t *)pLink->pOsInfo; + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreAliTrainingCallback(link); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + return status; +} + +#endif /* defined(INCLUDE_NVLINK_LIB) */ + +const struct nvlink_link_handlers* osGetNvlinkLinkCallbacks(void) +{ +#if defined(INCLUDE_NVLINK_LIB) + static const struct nvlink_link_handlers rm_nvlink_link_ops = + { + .add = rm_nvlink_ops_add_link, + .remove = rm_nvlink_ops_remove_link, + .lock = rm_nvlink_ops_lock_link, + .unlock = rm_nvlink_ops_unlock_link, + .queue_link_change = rm_nvlink_ops_queue_link_change, + .set_dl_link_mode = rm_nvlink_ops_set_dl_link_mode, + .get_dl_link_mode = rm_nvlink_ops_get_dl_link_mode, + .set_tl_link_mode = rm_nvlink_ops_set_tl_link_mode, + .get_tl_link_mode = rm_nvlink_ops_get_tl_link_mode, + .set_tx_mode = rm_nvlink_ops_set_link_tx_mode, + .get_tx_mode = rm_nvlink_ops_get_link_tx_mode, + .set_rx_mode = rm_nvlink_ops_set_link_rx_mode, + .get_rx_mode = rm_nvlink_ops_get_link_rx_mode, + .set_rx_detect = rm_nvlink_ops_set_link_rx_detect, + .get_rx_detect = rm_nvlink_ops_get_link_rx_detect, + .write_discovery_token = rm_nvlink_ops_write_link_discovery_token, + .read_discovery_token = rm_nvlink_ops_read_link_discovery_token, + .training_complete = rm_nvlink_ops_training_complete, + .get_uphy_load = rm_nvlink_get_uphy_load, + .ali_training = rm_nvlink_ops_ali_training, + }; + + return &rm_nvlink_link_ops; +#else + return NULL; +#endif +} + +/* + * @brief Verif only function to get the chiplib overrides for link connection + * state for all NVLINKs. + * + * If chiplib overrides exist, each link can either be enabled (1) or disabled (0) + * + * @param[in] pGpu GPU object pointer + * @param[in] maxLinks Size of pLinkConnection array + * @param[out] pLinkConnection array of pLinkConnection values to be populated by MODS + * + * @return NV_OK or NV_ERR_NOT_SUPPORTED (no overrides available) + */ +NV_STATUS +osGetForcedNVLinkConnection +( + OBJGPU *pGpu, + NvU32 maxLinks, + NvU32 *pLinkConnection +) +{ + int i, ret; + NV_STATUS status; + char path[64]; + OBJSYS *pSys; + OBJOS *pOS; + + NV_ASSERT_OR_RETURN((pLinkConnection != NULL), NV_ERR_INVALID_POINTER); + NV_ASSERT_OR_RETURN((maxLinks > 0), NV_ERR_NOT_SUPPORTED); + NV_ASSERT_OR_RETURN((pGpu != NULL), NV_ERR_INVALID_ARGUMENT); + + pSys = SYS_GET_INSTANCE(); + pOS = SYS_GET_OS(pSys); + if (pOS == NULL || pOS->osSimEscapeRead == NULL) + { + NV_PRINTF(LEVEL_ERROR, "%s: escape reads not supported on platform\n", + __FUNCTION__); + return NV_ERR_NOT_SUPPORTED; + } + + for (i = 0; i < maxLinks; i++) + { + ret = os_snprintf(path, sizeof(path), "CPU_MODEL|CM_ATS_ADDRESS|NVLink%u", i); + NV_ASSERT((ret > 0) && (ret < (sizeof(path) - 1))); + + status = pOS->osSimEscapeRead(pGpu, path, 0, 4, &pLinkConnection[i]); + if (status == NV_OK) + { + NV_PRINTF(LEVEL_INFO, "%s: %s=0x%X\n", __FUNCTION__, + path, pLinkConnection[i]); + } + else + { + NV_PRINTF(LEVEL_INFO, "%s: osSimEscapeRead for '%s' failed (%u)\n", + __FUNCTION__, path, status); + return NV_ERR_NOT_SUPPORTED; + } + } + return NV_OK; +} + +/* + * @brief Get Platform suggested NVLink linerate + * + * NVLink will use this function to get the platform suggested linerate + * if available in FRU or device tree. + * + * @param[in] pGpu GPU object pointer + * @param[out] NvU32 * Suggested datarate + * + * @return NV_OK or NV_ERR_NOT_SUPPORTED (platform linerate data not available) + */ +NV_STATUS +osGetPlatformNvlinkLinerate +( + OBJGPU *pGpu, + NvU32 *lineRate +) +{ +#if defined(NVCPU_PPC64LE) + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + if (!pKernelNvlink) + return NV_ERR_INVALID_ARGUMENT; + + return nv_get_nvlink_line_rate(nv, lineRate); +#else + //TODO : FRU based method to be filled out by Bug 200285656 + //*lineRate = 0; + //return NV_OK; + return NV_ERR_NOT_SUPPORTED; +#endif +} + +void +osSetNVLinkSysmemLinkState +( + OBJGPU *pGpu, + NvBool enabled +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + NV_ASSERT(enabled); + if (enabled) + nv_dma_enable_nvlink(nv->dma_dev); +} diff --git a/userspace/sdks/nv525/nvalloc/unix/src/osunix.c b/userspace/sdks/nv525/nvalloc/unix/src/osunix.c new file mode 100644 index 0000000..7d70602 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/src/osunix.c @@ -0,0 +1,88 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/***************************** HW State Routines ***************************\ +* * +* Fills in os specific function pointers for the Unix OS object. * +* * +\***************************************************************************/ + +#include +#include + +static void initOSSpecificFunctionPointers(OBJOS *); +static void initMiscOSFunctionPointers(OBJOS *); +static void initUnixOSFunctionPointers(OBJOS *); +static void initOSSpecificProperties(OBJOS *); + +void +osInitObjOS(OBJOS *pOS) +{ + initOSSpecificFunctionPointers(pOS); + initOSSpecificProperties(pOS); +} + +static void +initOSSpecificFunctionPointers(OBJOS *pOS) +{ + initMiscOSFunctionPointers(pOS); + initUnixOSFunctionPointers(pOS); +} + +static void +initMiscOSFunctionPointers(OBJOS *pOS) +{ + pOS->osQueueWorkItem = osQueueWorkItem; + pOS->osQueueWorkItemWithFlags = osQueueWorkItemWithFlags; + pOS->osQueueSystemWorkItem = osQueueSystemWorkItem; +} + +static void +initUnixOSFunctionPointers(OBJOS *pOS) +{ +#if defined(NVCPU_X86_64) + pOS->osNv_rdcr4 = nv_rdcr4; + pOS->osNv_cpuid = nv_cpuid; +#endif + + pOS->osCallACPI_DSM = osCallACPI_DSM; + pOS->osCallACPI_DDC = osCallACPI_DDC; + pOS->osCallACPI_NVHG_ROM = osCallACPI_NVHG_ROM; + pOS->osCallACPI_DOD = osCallACPI_DOD; + pOS->osCallACPI_MXDM = osCallACPI_MXDM; + pOS->osCallACPI_MXDS = osCallACPI_MXDS; + + pOS->osDbgBreakpointEnabled = osDbgBreakpointEnabled; +} + +static void +initOSSpecificProperties +( + OBJOS *pOS +) +{ + pOS->setProperty(pOS, PDB_PROP_OS_ONDEMAND_VBLANK_CONTROL_ENABLE_DEFAULT, NV_TRUE); + pOS->setProperty(pOS, PDB_PROP_OS_CACHED_MEMORY_MAPPINGS_FOR_ACPI_TABLE, NV_TRUE); + pOS->setProperty(pOS, PDB_PROP_OS_LIMIT_GPU_RESET, NV_TRUE); +} diff --git a/userspace/sdks/nv525/nvalloc/unix/src/registry.c b/userspace/sdks/nv525/nvalloc/unix/src/registry.c new file mode 100644 index 0000000..522b937 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/src/registry.c @@ -0,0 +1,705 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#if defined(DEBUG_REGISTRY) +#define DBG_REG_PRINTF(a, ...) \ + NV_PRINTF(LEVEL_INFO, a, ##__VA_ARGS__) +#else +#define DBG_REG_PRINTF(a, ...) +#endif + +static NvS32 stringCaseCompare( + const char *string1, + const char *string2 +) +{ + NvU8 c1, c2; + + do + { + c1 = *string1, c2 = *string2; + if (c1 >= 'A' && c1 <= 'Z') + c1 += ('a' - 'A'); + if (c2 >= 'A' && c2 <= 'Z') + c2 += ('a' - 'A'); + string1++, string2++; + } + while ((c1 == c2) && (c1 != '\0')); + + return (c1 - c2); +} + +static nv_reg_entry_t *the_registry = NULL; + +static nv_reg_entry_t* regCreateNewRegistryKey( + nv_state_t *nv, + const char *regParmStr +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + nv_reg_entry_t *new_reg = NULL; + char *new_ParmStr = NULL; + NvU32 parm_size; + + if (regParmStr == NULL) + { + DBG_BREAKPOINT(); + return NULL; + } + + new_reg = portMemAllocNonPaged(sizeof(nv_reg_entry_t)); + if (NULL == new_reg) + { + NV_PRINTF(LEVEL_ERROR, "failed to grow registry\n"); + return NULL; + } + + portMemSet(new_reg, 0, sizeof(nv_reg_entry_t)); + + if (regParmStr != NULL) + { + parm_size = (portStringLength(regParmStr) + 1); + new_ParmStr = portMemAllocNonPaged(parm_size); + if (NULL == new_ParmStr) + { + NV_PRINTF(LEVEL_ERROR, "failed to allocate registry param string\n"); + portMemFree(new_reg); + return NULL; + } + + NV_ASSERT(parm_size <= NVOS38_MAX_REGISTRY_STRING_LENGTH); + + if (portMemCopy(new_ParmStr, parm_size, regParmStr, parm_size) == NULL) + { + NV_PRINTF(LEVEL_ERROR, "failed to copy registry param string\n"); + portMemFree(new_ParmStr); + portMemFree(new_reg); + return NULL; + } + } + + new_reg->regParmStr = new_ParmStr; + new_reg->type = NV_REGISTRY_ENTRY_TYPE_UNKNOWN; + + if (nvp != NULL) + { + new_reg->next = nvp->pRegistry; + nvp->pRegistry = new_reg; + DBG_REG_PRINTF("local registry now at 0x%p\n", nvp->pRegistry); + } + else + { + new_reg->next = the_registry; + the_registry = new_reg; + DBG_REG_PRINTF("global registry now at 0x%p\n", the_registry); + } + + return new_reg; +} + +static NV_STATUS regFreeEntry(nv_reg_entry_t *tmp) +{ + portMemFree(tmp->regParmStr); + tmp->regParmStr = NULL; + { + portMemFree(tmp->pdata); + tmp->pdata = NULL; + tmp->len = 0; + } + portMemFree(tmp); + + return NV_OK; +} + +static nv_reg_entry_t* regFindRegistryEntry( + nv_state_t *nv, + const char *regParmStr, + NvU32 type, + NvBool *bGlobalEntry +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + nv_reg_entry_t *tmp; + + DBG_REG_PRINTF("%s: %s\n", __FUNCTION__, regParmStr); + + if (nvp != NULL) + { + tmp = nvp->pRegistry; + DBG_REG_PRINTF(" local registry at 0x%p\n", tmp); + + while ((tmp != NULL) && (tmp->regParmStr != NULL)) + { + DBG_REG_PRINTF(" Testing against %s\n", + tmp->regParmStr); + if ((stringCaseCompare(tmp->regParmStr, regParmStr) == 0) && + (type == tmp->type)) + { + DBG_REG_PRINTF(" found a match!\n"); + if (bGlobalEntry) + *bGlobalEntry = NV_FALSE; + return tmp; + } + tmp = tmp->next; + } + } + + tmp = the_registry; + DBG_REG_PRINTF(" global registry at 0x%p\n", tmp); + + while ((tmp != NULL) && (tmp->regParmStr != NULL)) + { + DBG_REG_PRINTF(" Testing against %s\n", + tmp->regParmStr); + if ((stringCaseCompare(tmp->regParmStr, regParmStr) == 0) && + (type == tmp->type)) + { + DBG_REG_PRINTF(" found a match!\n"); + if (bGlobalEntry) + *bGlobalEntry = NV_TRUE; + return tmp; + } + tmp = tmp->next; + } + + DBG_REG_PRINTF(" no match\n"); + return NULL; +} + +NV_STATUS RmWriteRegistryDword( + nv_state_t *nv, + const char *regParmStr, + NvU32 Data +) +{ + nv_reg_entry_t *tmp; + NvBool bGlobalEntry; + + if (regParmStr == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + DBG_REG_PRINTF("%s: %s -> 0x%x\n", __FUNCTION__, regParmStr, Data); + + tmp = regFindRegistryEntry(nv, regParmStr, + NV_REGISTRY_ENTRY_TYPE_DWORD, &bGlobalEntry); + + // If we found an entry and we were looking for a global entry and + // found a global, or we were looking for a per-GPU entry and found a + // per-GPU entry + if (tmp != NULL && + ((nv == NULL && bGlobalEntry) || + (nv != NULL && !bGlobalEntry))) + { + tmp->data = Data; + + if (stringCaseCompare(regParmStr, "ResmanDebugLevel") == 0) + { + os_dbg_set_level(Data); + } + + return NV_OK; + } + + tmp = regCreateNewRegistryKey(nv, regParmStr); + if (tmp == NULL) + return NV_ERR_GENERIC; + + tmp->type = NV_REGISTRY_ENTRY_TYPE_DWORD; + tmp->data = Data; + + return NV_OK; +} + +NV_STATUS RmReadRegistryDword( + nv_state_t *nv, + const char *regParmStr, + NvU32 *Data +) +{ + nv_reg_entry_t *tmp; + + if ((regParmStr == NULL) || (Data == NULL)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + DBG_REG_PRINTF("%s: %s\n", __FUNCTION__, regParmStr); + + tmp = regFindRegistryEntry(nv, regParmStr, + NV_REGISTRY_ENTRY_TYPE_DWORD, NULL); + if (tmp == NULL) + { + tmp = regFindRegistryEntry(nv, regParmStr, + NV_REGISTRY_ENTRY_TYPE_BINARY, NULL); + if ((tmp != NULL) && (tmp->len >= sizeof(NvU32))) + { + *Data = *(NvU32 *)tmp->pdata; + } + else + { + DBG_REG_PRINTF(" not found\n"); + return NV_ERR_GENERIC; + } + } + else + { + *Data = tmp->data; + } + + DBG_REG_PRINTF(" found in the_registry: 0x%x\n", *Data); + + return NV_OK; +} + +NV_STATUS RmReadRegistryBinary( + nv_state_t *nv, + const char *regParmStr, + NvU8 *Data, + NvU32 *cbLen +) +{ + nv_reg_entry_t *tmp; + NV_STATUS status; + + if ((regParmStr == NULL) || (Data == NULL) || (cbLen == NULL)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + DBG_REG_PRINTF("%s: %s\n", __FUNCTION__, regParmStr); + + tmp = regFindRegistryEntry(nv, regParmStr, + NV_REGISTRY_ENTRY_TYPE_BINARY, NULL); + if (tmp == NULL) + { + DBG_REG_PRINTF(" not found\n"); + return NV_ERR_GENERIC; + } + + DBG_REG_PRINTF(" found\n"); + + if (*cbLen >= tmp->len) + { + portMemCopy((NvU8 *)Data, *cbLen, (NvU8 *)tmp->pdata, tmp->len); + *cbLen = tmp->len; + status = NV_OK; + } + else + { + NV_PRINTF(LEVEL_ERROR, + "buffer (length: %u) is too small (data length: %u)\n", + *cbLen, tmp->len); + status = NV_ERR_GENERIC; + } + + return status; +} + +NV_STATUS RmWriteRegistryBinary( + nv_state_t *nv, + const char *regParmStr, + NvU8 *Data, + NvU32 cbLen +) +{ + nv_reg_entry_t *tmp; + NvBool bGlobalEntry; + + if ((regParmStr == NULL) || (Data == NULL)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + DBG_REG_PRINTF("%s: %s\n", __FUNCTION__, regParmStr); + + tmp = regFindRegistryEntry(nv, regParmStr, + NV_REGISTRY_ENTRY_TYPE_BINARY, &bGlobalEntry); + + // If we found an entry and we were looking for a global entry and + // found a global, or we were looking for a per-GPU entry and found a + // per-GPU entry + if (tmp != NULL && + ((nv == NULL && bGlobalEntry) || + (nv != NULL && !bGlobalEntry))) + { + if (tmp->pdata != NULL) + { + portMemFree(tmp->pdata); + tmp->pdata = NULL; + tmp->len = 0; + } + } + else + { + tmp = regCreateNewRegistryKey(nv, regParmStr); + if (tmp == NULL) + { + NV_PRINTF(LEVEL_ERROR, "failed to create binary registry entry\n"); + return NV_ERR_GENERIC; + } + } + + tmp->pdata = portMemAllocNonPaged(cbLen); + if (NULL == tmp->pdata) + { + NV_PRINTF(LEVEL_ERROR, "failed to write binary registry entry\n"); + return NV_ERR_GENERIC; + } + + tmp->type = NV_REGISTRY_ENTRY_TYPE_BINARY; + tmp->len = cbLen; + portMemCopy((NvU8 *)tmp->pdata, tmp->len, (NvU8 *)Data, cbLen); + + return NV_OK; +} + +NV_STATUS RmWriteRegistryString( + nv_state_t *nv, + const char *regParmStr, + const char *buffer, + NvU32 bufferLength +) +{ + nv_reg_entry_t *tmp; + NvBool bGlobalEntry; + + if ((regParmStr == NULL) || (buffer == NULL)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + DBG_REG_PRINTF("%s: %s\n", __FUNCTION__, regParmStr); + + tmp = regFindRegistryEntry(nv, regParmStr, + NV_REGISTRY_ENTRY_TYPE_STRING, &bGlobalEntry); + + // If we found an entry and we were looking for a global entry and + // found a global, or we were looking for a per-GPU entry and found a + // per-GPU entry + if (tmp != NULL && + ((nv == NULL && bGlobalEntry) || + (nv != NULL && !bGlobalEntry))) + { + if (tmp->pdata != NULL) + { + portMemFree(tmp->pdata); + tmp->len = 0; + tmp->pdata = NULL; + } + } + else + { + tmp = regCreateNewRegistryKey(nv, regParmStr); + if (tmp == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "failed to allocate a string registry entry!\n"); + return NV_ERR_INSUFFICIENT_RESOURCES; + } + } + + tmp->pdata = portMemAllocNonPaged(bufferLength); + if (tmp->pdata == NULL) + { + NV_PRINTF(LEVEL_ERROR, "failed to write a string registry entry!\n"); + return NV_ERR_NO_MEMORY; + } + + tmp->type = NV_REGISTRY_ENTRY_TYPE_STRING; + tmp->len = bufferLength; + portMemCopy((void *)tmp->pdata, tmp->len, buffer, (bufferLength - 1)); + tmp->pdata[bufferLength-1] = '\0'; + + return NV_OK; +} + +NV_STATUS RmReadRegistryString( + nv_state_t *nv, + const char *regParmStr, + NvU8 *buffer, + NvU32 *pBufferLength +) +{ + NvU32 bufferLength; + nv_reg_entry_t *tmp; + + if ((regParmStr == NULL) || (buffer == NULL) || (pBufferLength == NULL)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + DBG_REG_PRINTF("%s: %s\n", __FUNCTION__, regParmStr); + + bufferLength = *pBufferLength; + *pBufferLength = 0; + *buffer = '\0'; + + tmp = regFindRegistryEntry(nv, regParmStr, + NV_REGISTRY_ENTRY_TYPE_STRING, NULL); + if (tmp == NULL) + { + return NV_ERR_GENERIC; + } + + if (bufferLength >= tmp->len) + { + portMemCopy((void *)buffer, bufferLength, (void *)tmp->pdata, tmp->len); + *pBufferLength = tmp->len; + } + else + { + NV_PRINTF(LEVEL_ERROR, + "buffer (length: %u) is too small (data length: %u)\n", + bufferLength, tmp->len); + return NV_ERR_BUFFER_TOO_SMALL; + } + + return NV_OK; +} + +NV_STATUS RmInitRegistry(void) +{ + NV_STATUS rmStatus; + + rmStatus = os_registry_init(); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to initialize the OS registry!\n"); + } + + return rmStatus; +} + +NV_STATUS RmDestroyRegistry(nv_state_t *nv) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + nv_reg_entry_t *tmp; + + if (nvp != NULL) + { + tmp = nvp->pRegistry; + nvp->pRegistry = NULL; + } + else + { + tmp = the_registry; + the_registry = NULL; + } + + while (tmp != NULL) + { + nv_reg_entry_t *entry = tmp; + tmp = tmp->next; + regFreeEntry(entry); + } + + return NV_OK; +} + +static void regCountEntriesAndSize( + NvU32 *pNumEntries, // Pointer to number of entries + NvU32 *pSize, // Pointer to total size + nv_reg_entry_t *pRegEntry // Pointer local or global registry +) +{ + // + // Note that *pNumEntries and *pSize are not initialized here. This is so + // we can accumulate totals of both global and local registries. + // + NvU32 numEntries = *pNumEntries; + NvU32 size = *pSize; + + while ((pRegEntry != NULL) && (pRegEntry->regParmStr != NULL)) + { + size += portStringLength(pRegEntry->regParmStr) + 1 + pRegEntry->len; + numEntries++; + pRegEntry = pRegEntry->next; + } + + *pNumEntries = numEntries; + *pSize = size; +} + +static NV_STATUS regCopyEntriesToPackedBuffer( + PACKED_REGISTRY_TABLE *pRegTable, // Pointer to packed record + nv_reg_entry_t *pRegEntry, // Pointer local or global registry + NvU32 *pEntryIndex, // Pointer to next index + NvU32 *pDataOffset // Pointer to offset of next data byte. +) +{ + NvU8 *pByte = (NvU8 *)pRegTable; // Byte version of record pointer. + NV_STATUS nvStatus = NV_OK; + NvU32 entryIndex = *pEntryIndex; + NvU32 dataOffset = *pDataOffset; + + // Walk the records and copy the data. + while ((pRegEntry != NULL) && (pRegEntry->regParmStr != NULL)) + { + PACKED_REGISTRY_ENTRY *pEntry = &pRegTable->entries[entryIndex]; + NvU32 slen = portStringLength(pRegEntry->regParmStr) + 1; + + // Sanity check the data offset and index against counted totals. + if ((dataOffset + slen + pRegEntry->len > pRegTable->size) || + (entryIndex >= pRegTable->numEntries)) + { + // Something has changed since we counted them? + NV_PRINTF(LEVEL_ERROR, "Registry entry record is full\n"); + nvStatus = NV_ERR_INVALID_STATE; + break; + } + + // Copy registry entry name to data blob. + pEntry->nameOffset = dataOffset; + portMemCopy(&pByte[dataOffset], slen, pRegEntry->regParmStr, slen); + dataOffset += slen; + + switch (pRegEntry->type) + { + case NV_REGISTRY_ENTRY_TYPE_DWORD: + pEntry->type = REGISTRY_TABLE_ENTRY_TYPE_DWORD; + pEntry->length = sizeof(NvU32); + pEntry->data = pRegEntry->data; + break; + + case NV_REGISTRY_ENTRY_TYPE_BINARY: + case NV_REGISTRY_ENTRY_TYPE_STRING: + pEntry->type = REGISTRY_TABLE_ENTRY_TYPE_STRING; + if (pRegEntry->type == NV_REGISTRY_ENTRY_TYPE_BINARY) + pEntry->type = REGISTRY_TABLE_ENTRY_TYPE_BINARY; + + pEntry->length = pRegEntry->len; + pEntry->data = dataOffset; + portMemCopy(&pByte[dataOffset], pEntry->length, + pRegEntry->pdata, pRegEntry->len); + dataOffset += pRegEntry->len; + break; + + default: + // We should never get here. + pEntry->type = REGISTRY_TABLE_ENTRY_TYPE_UNKNOWN; + pEntry->length = 0; + pEntry->data = 0; + DBG_BREAKPOINT(); + break; + } + + pRegEntry = pRegEntry->next; + entryIndex++; + } + + *pEntryIndex = entryIndex; + *pDataOffset = dataOffset; + return nvStatus; +} + +// Package registry entries +NV_STATUS RmPackageRegistry( + nv_state_t *nv, + PACKED_REGISTRY_TABLE *pRegTable, + NvU32 *pSize +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + nv_reg_entry_t *pLocalRegistry = NULL; + NV_STATUS nvStatus = NV_OK; + NvU32 totalSize; + NvU32 numEntries; + + if (pSize == NULL) + return NV_ERR_INVALID_ARGUMENT; + + // Use the local (per-device) registry if we have one. + if (nvp != NULL) + pLocalRegistry = nvp->pRegistry; + + numEntries = 0; + totalSize = NV_OFFSETOF(PACKED_REGISTRY_TABLE, entries); + + // Count the number of global entries and total size. + regCountEntriesAndSize(&numEntries, &totalSize, the_registry); + + // Count the number of local entries and total size. + regCountEntriesAndSize(&numEntries, &totalSize, pLocalRegistry); + + // Add table record size into total size. + totalSize += sizeof(PACKED_REGISTRY_ENTRY) * numEntries; + + // + // If this function is called to only compute total size of registry table, + // then we are done here. + // + if (pRegTable == NULL) + { + *pSize = totalSize; + return NV_OK; + } + + // Return warning if there are no registry entries. + if (numEntries == 0) + return NV_WARN_NOTHING_TO_DO; + + if (totalSize > *pSize) + { + NV_PRINTF(LEVEL_ERROR, "Registry entries overflow RPC record\n"); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Fill in our new structure with the first pass (counting) values. + pRegTable->size = totalSize; + *pSize = totalSize; + pRegTable->numEntries = numEntries; + + // Offset of first byte after the registry entry table. + totalSize = NV_OFFSETOF(PACKED_REGISTRY_TABLE, entries) + + (sizeof(PACKED_REGISTRY_ENTRY) * numEntries); + + // Starting index in the registry entry table. + numEntries = 0; + + // Walk the global registry and copy the data. + nvStatus = regCopyEntriesToPackedBuffer(pRegTable, + the_registry, &numEntries, &totalSize); + + // Walk the local registry and copy the data. + if (nvStatus == NV_OK) + { + nvStatus = regCopyEntriesToPackedBuffer(pRegTable, + pLocalRegistry, &numEntries, &totalSize); + } + + // Sanity check second pass against first pass. + if ((numEntries != pRegTable->numEntries) || (totalSize != pRegTable->size)) + { + NV_PRINTF(LEVEL_ERROR, "First/second pass mismatch\n"); + nvStatus = NV_ERR_INVALID_STATE; + } + + return nvStatus; +} + diff --git a/userspace/sdks/nv525/nvalloc/unix/src/rm-gpu-ops.c b/userspace/sdks/nv525/nvalloc/unix/src/rm-gpu-ops.c new file mode 100644 index 0000000..d542393 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/src/rm-gpu-ops.c @@ -0,0 +1,813 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include "rmapi/nv_gpu_ops.h" +#include "gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h" + +NV_STATUS NV_API_CALL rm_gpu_ops_create_session( + nvidia_stack_t *sp, + struct gpuSession **session) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCreateSession(session); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_destroy_session ( + nvidia_stack_t *sp, gpuSessionHandle session) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsDestroySession(session); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_device_create ( + nvidia_stack_t *sp, + nvgpuSessionHandle_t session, + const gpuInfo *pGpuInfo, + const NvProcessorUuid *gpuUuid, + nvgpuDeviceHandle_t *device, + NvBool bCreateSmcPartition) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsDeviceCreate(session, pGpuInfo, gpuUuid, device, bCreateSmcPartition); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_device_destroy ( + nvidia_stack_t *sp, + gpuDeviceHandle device) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsDeviceDestroy(device); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_address_space_create ( + nvidia_stack_t *sp, + gpuDeviceHandle device, + NvU64 vaBase, + NvU64 vaSize, + gpuAddressSpaceHandle *vaSpace, + gpuAddressSpaceInfo *vaSpaceInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsAddressSpaceCreate(device, vaBase, vaSize, vaSpace, + vaSpaceInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_dup_address_space( + nvidia_stack_t *sp, + gpuDeviceHandle device, + NvHandle hUserClient, + NvHandle hUserVASpace, + gpuAddressSpaceHandle *dupedVaspace, + gpuAddressSpaceInfo *vaSpaceInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsDupAddressSpace(device, hUserClient, hUserVASpace, + dupedVaspace, vaSpaceInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_address_space_destroy(nvidia_stack_t *sp, + gpuAddressSpaceHandle vaspace) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + nvGpuOpsAddressSpaceDestroy(vaspace); + NV_EXIT_RM_RUNTIME(sp,fp); + return NV_OK; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_memory_alloc_fb( + nvidia_stack_t *sp, gpuAddressSpaceHandle vaspace, + NvLength size, NvU64 *gpuOffset, gpuAllocInfo *allocInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsMemoryAllocFb(vaspace, size, gpuOffset, allocInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_get_p2p_caps(nvidia_stack_t *sp, + gpuDeviceHandle device1, + gpuDeviceHandle device2, + getP2PCapsParams *pP2pCapsParams) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsGetP2PCaps(device1, device2, pP2pCapsParams); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_memory_alloc_sys( + nvidia_stack_t *sp, gpuAddressSpaceHandle vaspace, + NvLength size, NvU64 *gpuOffset, gpuAllocInfo *allocInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsMemoryAllocSys(vaspace, size, gpuOffset, allocInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_pma_register_callbacks( + nvidia_stack_t *sp, + void *pPma, + pmaEvictPagesCb_t evictPages, + pmaEvictRangeCb_t evictRange, + void *callbackData) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + rmStatus = pmaRegisterEvictionCb(pPma, evictPages, evictRange, callbackData); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +void NV_API_CALL rm_gpu_ops_pma_unregister_callbacks( + nvidia_stack_t *sp, + void *pPma) +{ + THREAD_STATE_NODE threadState; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + pmaUnregisterEvictionCb(pPma); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NV_STATUS NV_API_CALL rm_gpu_ops_get_pma_object( + nvidia_stack_t *sp, + gpuDeviceHandle device, + void **pPma, + const nvgpuPmaStatistics_t *pPmaPubStats) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsGetPmaObject(device, pPma, + (const UvmPmaStatistics **)pPmaPubStats); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_pma_alloc_pages( + nvidia_stack_t *sp, void *pPma, + NvLength pageCount, NvU32 pageSize, + nvgpuPmaAllocationOptions_t pPmaAllocOptions, + NvU64 *pPages) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsPmaAllocPages(pPma, pageCount, pageSize, + pPmaAllocOptions, pPages); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_pma_pin_pages( + nvidia_stack_t *sp, void *pPma, + NvU64 *pPages, NvLength pageCount, NvU32 pageSize, NvU32 flags) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsPmaPinPages(pPma, pPages, pageCount, pageSize, flags); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_pma_unpin_pages( + nvidia_stack_t *sp, void *pPma, + NvU64 *pPages, NvLength pageCount, NvU32 pageSize) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsPmaUnpinPages(pPma, pPages, pageCount, pageSize); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_memory_cpu_map( + nvidia_stack_t *sp, gpuAddressSpaceHandle vaspace, + NvU64 gpuOffset, NvLength length, void **cpuPtr, NvU32 pageSize) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsMemoryCpuMap(vaspace, gpuOffset, length, cpuPtr, + pageSize); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_memory_cpu_ummap( + nvidia_stack_t *sp, gpuAddressSpaceHandle vaspace, void* cpuPtr) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + nvGpuOpsMemoryCpuUnMap(vaspace, cpuPtr); + NV_EXIT_RM_RUNTIME(sp,fp); + return NV_OK; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_channel_allocate(nvidia_stack_t *sp, + gpuAddressSpaceHandle vaspace, + const gpuChannelAllocParams *allocParams, + gpuChannelHandle *channel, + gpuChannelInfo *channelInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsChannelAllocate(vaspace, allocParams, channel, + channelInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_channel_destroy(nvidia_stack_t * sp, + nvgpuChannelHandle_t channel) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + nvGpuOpsChannelDestroy(channel); + NV_EXIT_RM_RUNTIME(sp,fp); + return NV_OK; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_pma_free_pages(nvidia_stack_t *sp, + void *pPma, NvU64 *pPages, NvLength pageCount, NvU32 pageSize, NvU32 flags) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + nvGpuOpsPmaFreePages(pPma, pPages, pageCount, pageSize, flags); + NV_EXIT_RM_RUNTIME(sp,fp); + return NV_OK; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_memory_free( + nvidia_stack_t *sp, gpuAddressSpaceHandle vaspace, NvU64 gpuOffset) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + nvGpuOpsMemoryFree(vaspace, gpuOffset); + NV_EXIT_RM_RUNTIME(sp,fp); + return NV_OK; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_query_caps(nvidia_stack_t *sp, + gpuDeviceHandle device, + gpuCaps * caps) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsQueryCaps(device, caps); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_query_ces_caps(nvidia_stack_t *sp, + gpuDeviceHandle device, + gpuCesCaps *caps) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsQueryCesCaps(device, caps); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_get_gpu_info(nvidia_stack_t *sp, + const NvProcessorUuid *pUuid, + const gpuClientInfo *pGpuClientInfo, + gpuInfo *pGpuInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsGetGpuInfo(pUuid, pGpuClientInfo, pGpuInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_service_device_interrupts_rm(nvidia_stack_t *sp, + gpuDeviceHandle device) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsServiceDeviceInterruptsRM(device); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_set_page_directory (nvidia_stack_t *sp, + gpuAddressSpaceHandle vaSpace, + NvU64 physAddress, unsigned numEntries, + NvBool bVidMemAperture, NvU32 pasid) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsSetPageDirectory(vaSpace, physAddress, numEntries, + bVidMemAperture, pasid); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_unset_page_directory (nvidia_stack_t *sp, + gpuAddressSpaceHandle vaSpace) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsUnsetPageDirectory(vaSpace); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_dup_allocation(nvidia_stack_t *sp, + gpuAddressSpaceHandle srcVaSpace, + NvU64 srcAddress, + gpuAddressSpaceHandle dstVaSpace, + NvU64 dstVaAlignment, + NvU64 *dstAddress) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsDupAllocation(srcVaSpace, srcAddress, dstVaSpace, dstVaAlignment, dstAddress); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_dup_memory (nvidia_stack_t *sp, + gpuDeviceHandle device, + NvHandle hClient, + NvHandle hPhysMemory, + NvHandle *hDupMemory, + nvgpuMemoryInfo_t gpuMemoryInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsDupMemory(device, hClient, hPhysMemory, hDupMemory, gpuMemoryInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_free_duped_handle (nvidia_stack_t *sp, + gpuDeviceHandle device, + NvHandle hPhysHandle) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsFreeDupedHandle(device, hPhysHandle); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_get_fb_info (nvidia_stack_t *sp, + gpuDeviceHandle device, + gpuFbInfo * fbInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsGetFbInfo(device, fbInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_get_ecc_info (nvidia_stack_t *sp, + gpuDeviceHandle device, + gpuEccInfo * eccInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsGetEccInfo(device, eccInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +// +// Please see the comments for nvUvmInterfaceOwnPageFaultIntr(), in +// nv_uvm_interface.h, for the recommended way to use this routine. +// +// How it works: +// +// The rmGpuLocksAcquire call generally saves the current GPU interrupt +// state, then disables interrupt generation for one (or all) GPUs. +// Likewise, the rmGpuLocksRelease call restores (re-enables) those +// interrupts to their previous state. However, the rmGpuLocksRelease +// call does NOT restore interrupts that RM does not own. +// +// This is rather hard to find in the code, so: very approximately, the +// following sequence happens: rmGpuLocksRelease, osEnableInterrupts, +// intrRestoreNonStall_HAL, intrEncodeIntrEn_HAL, and that last one skips +// over any interrupts that RM does not own. +// +// This means that things are a bit asymmetric, because this routine +// actually changes that ownership in between the rmGpuLocksAcquire and +// rmGpuLocksRelease calls. So: +// +// -- If you call this routine with bOwnInterrupts == NV_TRUE (UVM is +// taking ownership from the RM), then rmGpuLocksAcquire disables all +// GPU interrupts. Then the ownership is taken away from RM, so the +// rmGpuLocksRelease call leaves the replayable page fault interrupts +// disabled. It is then up to UVM (the caller) to enable replayable +// page fault interrupts when it is ready. +// +// -- If you call this routine with bOwnInterrupts == NV_FALSE (UVM is +// returning ownership to the RM), then rmGpuLocksAcquire disables +// all GPU interrupts that RM owns. Then the ownership is returned to +// RM, so the rmGpuLocksRelease call re-enables replayable page fault +// interrupts. So, that implies that you need to disable replayable page +// fault interrupts before calling this routine, in order to hand +// over a GPU to RM that is not generating interrupts, until RM is +// ready to handle the interrupts. +// +NV_STATUS NV_API_CALL rm_gpu_ops_own_page_fault_intr(nvidia_stack_t *sp, + struct gpuDevice *device, + NvBool bOwnInterrupts) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsOwnPageFaultIntr(device, bOwnInterrupts); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_init_fault_info (nvidia_stack_t *sp, + gpuDeviceHandle device, + gpuFaultInfo *pFaultInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsInitFaultInfo(device, pFaultInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_destroy_fault_info (nvidia_stack_t *sp, + gpuDeviceHandle device, + gpuFaultInfo *pFaultInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsDestroyFaultInfo(device, pFaultInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +// Functions +// +// - rm_gpu_ops_has_pending_non_replayable_faults +// - rm_gpu_ops_get_non_replayable_faults +// +// Cannot take the GPU/RM lock because it is called during fault servicing. +// This could produce deadlocks if the UVM bottom half gets stuck behind a +// stalling interrupt that cannot be serviced if UVM is holding the lock. +// +// However, these functions can be safely called with no locks because it is +// just accessing the given client shadow fault buffer, which is implemented +// using a lock-free queue. There is a different client shadow fault buffer +// per GPU: RM top-half producer, UVM top/bottom-half consumer. + +NV_STATUS NV_API_CALL rm_gpu_ops_has_pending_non_replayable_faults(nvidia_stack_t *sp, + gpuFaultInfo *pFaultInfo, + NvBool *hasPendingFaults) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsHasPendingNonReplayableFaults(pFaultInfo, hasPendingFaults); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_get_non_replayable_faults(nvidia_stack_t *sp, + gpuFaultInfo *pFaultInfo, + void *faultBuffer, + NvU32 *numFaults) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsGetNonReplayableFaults(pFaultInfo, faultBuffer, numFaults); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_init_access_cntr_info(nvidia_stack_t *sp, + gpuDeviceHandle device, + gpuAccessCntrInfo *accessCntrInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsInitAccessCntrInfo(device, accessCntrInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_destroy_access_cntr_info(nvidia_stack_t *sp, + gpuDeviceHandle device, + gpuAccessCntrInfo *accessCntrInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsDestroyAccessCntrInfo(device, accessCntrInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_enable_access_cntr(nvidia_stack_t *sp, + gpuDeviceHandle device, + gpuAccessCntrInfo *accessCntrInfo, + gpuAccessCntrConfig *accessCntrConfig) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsEnableAccessCntr(device, accessCntrInfo, accessCntrConfig); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_disable_access_cntr(nvidia_stack_t *sp, + gpuDeviceHandle device, + gpuAccessCntrInfo *accessCntrInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsDisableAccessCntr(device, accessCntrInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL +rm_gpu_ops_p2p_object_create(nvidia_stack_t *sp, + gpuDeviceHandle device1, + gpuDeviceHandle device2, + NvHandle *hP2pObject) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp, fp); + rmStatus = nvGpuOpsP2pObjectCreate(device1, device2, hP2pObject); + NV_EXIT_RM_RUNTIME(sp, fp); + return rmStatus; +} + +void NV_API_CALL +rm_gpu_ops_p2p_object_destroy(nvidia_stack_t *sp, + nvgpuSessionHandle_t session, + NvHandle hP2pObject) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp, fp); + nvGpuOpsP2pObjectDestroy(session, hP2pObject); + NV_EXIT_RM_RUNTIME(sp, fp); +} + +NV_STATUS NV_API_CALL +rm_gpu_ops_get_external_alloc_ptes(nvidia_stack_t* sp, + nvgpuAddressSpaceHandle_t vaSpace, + NvHandle hDupedMemory, + NvU64 offset, + NvU64 size, + nvgpuExternalMappingInfo_t gpuExternalMappingInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp, fp); + rmStatus = nvGpuOpsGetExternalAllocPtes(vaSpace, hDupedMemory, offset, size, + gpuExternalMappingInfo); + NV_EXIT_RM_RUNTIME(sp, fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL +rm_gpu_ops_retain_channel(nvidia_stack_t* sp, + nvgpuAddressSpaceHandle_t vaSpace, + NvHandle hClient, + NvHandle hChannel, + void **retainedChannel, + nvgpuChannelInstanceInfo_t channelInstanceInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp, fp); + rmStatus = nvGpuOpsRetainChannel(vaSpace, hClient, hChannel, + (gpuRetainedChannel **)retainedChannel, + channelInstanceInfo); + NV_EXIT_RM_RUNTIME(sp, fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL +rm_gpu_ops_bind_channel_resources(nvidia_stack_t* sp, + void *retainedChannel, + nvgpuChannelResourceBindParams_t channelResourceBindParams) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp, fp); + rmStatus = nvGpuOpsBindChannelResources(retainedChannel, + channelResourceBindParams); + NV_EXIT_RM_RUNTIME(sp, fp); + return rmStatus; +} + +void NV_API_CALL +rm_gpu_ops_release_channel(nvidia_stack_t *sp, void *retainedChannel) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp, fp); + nvGpuOpsReleaseChannel(retainedChannel); + NV_EXIT_RM_RUNTIME(sp, fp); +} + +void NV_API_CALL +rm_gpu_ops_stop_channel(nvidia_stack_t * sp, + void *retainedChannel, + NvBool bImmediate) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + nvGpuOpsStopChannel(retainedChannel, bImmediate); + NV_EXIT_RM_RUNTIME(sp, fp); +} + +NV_STATUS NV_API_CALL +rm_gpu_ops_get_channel_resource_ptes(nvidia_stack_t* sp, + nvgpuAddressSpaceHandle_t vaSpace, + NvP64 resourceDescriptor, + NvU64 offset, + NvU64 size, + nvgpuExternalMappingInfo_t gpuExternalMappingInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp, fp); + rmStatus = nvGpuOpsGetChannelResourcePtes(vaSpace, resourceDescriptor, + offset, size, + gpuExternalMappingInfo); + NV_EXIT_RM_RUNTIME(sp, fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL +rm_gpu_ops_report_non_replayable_fault(nvidia_stack_t *sp, + nvgpuDeviceHandle_t device, + const void *pFaultPacket) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsReportNonReplayableFault(device, pFaultPacket); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL +rm_gpu_ops_paging_channel_allocate(nvidia_stack_t *sp, + gpuDeviceHandle device, + const gpuPagingChannelAllocParams *allocParams, + gpuPagingChannelHandle *channel, + gpuPagingChannelInfo *channelInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsPagingChannelAllocate(device, allocParams, channel, + channelInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +void NV_API_CALL +rm_gpu_ops_paging_channel_destroy(nvidia_stack_t *sp, + gpuPagingChannelHandle channel) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + nvGpuOpsPagingChannelDestroy(channel); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NV_STATUS NV_API_CALL +rm_gpu_ops_paging_channels_map(nvidia_stack_t *sp, + gpuAddressSpaceHandle srcVaSpace, + NvU64 srcAddress, + gpuDeviceHandle device, + NvU64 *dstAddress) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsPagingChannelsMap(srcVaSpace, srcAddress, device, dstAddress); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +void NV_API_CALL +rm_gpu_ops_paging_channels_unmap(nvidia_stack_t *sp, + gpuAddressSpaceHandle srcVaSpace, + NvU64 srcAddress, + gpuDeviceHandle device) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + nvGpuOpsPagingChannelsUnmap(srcVaSpace, srcAddress, device); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NV_STATUS NV_API_CALL +rm_gpu_ops_paging_channel_push_stream(nvidia_stack_t *sp, + gpuPagingChannelHandle channel, + char *methodStream, + NvU32 methodStreamSize) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsPagingChannelPushStream(channel, methodStream, methodStreamSize); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + diff --git a/userspace/sdks/nv525/nvalloc/unix/src/rmobjexportimport.c b/userspace/sdks/nv525/nvalloc/unix/src/rmobjexportimport.c new file mode 100644 index 0000000..dcc8d94 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/src/rmobjexportimport.c @@ -0,0 +1,634 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file + * + * @brief Provides RmExportObject, RmImportObject, RmFreeObjExportHandle and + * RmGetExportObjectInfo interfaces : + * + * These interfaces allow rm clients to export their objects into + * a unique RmObjExportHandle which another rm client could + * import, even if the source rm client gets destroyed. + * + * RM's device instance may get destroyed asynchronously, in which + * case exported objects residing on that device instance also get + * destroyed. This means it is not possible to import it back, but the + * RmObjExportHandle into which the object had been exported still + * remains valid but no other object could get it. + * + * There are not init/fini routines, it is the responsibility of the + * rest of RM's eco-system to make sure that all RmObjExportHandles get + * freed during driver unload. + * + * The api lock is expected to be held before calling into + * rmobjexportimport.c; do not hold gpu or any other lock. + */ + +#include "rmobjexportimport.h" +#include "nvlimits.h" +#include "gpu/device/device.h" + +#include "containers/map.h" +#include "rmapi/rmapi.h" +#include "rmapi/rs_utils.h" + +#include "class/cl0080.h" +#include "class/cl2080.h" +#include +#include + +// +// A reference to an RmObjExportHandle +// generated by function RmGenerateObjExportHandle(). +// +typedef struct +{ + NvU32 deviceInstance; +} RmObjExportHandleRef; +MAKE_MAP(RmObjExportHandleMap, RmObjExportHandleRef); + +// +// Memory allocator +// +PORT_MEM_ALLOCATOR *pMemAllocator; + +// +// Map RmObjExportHandle -> RmObjExportHandleRef +// +RmObjExportHandleMap objExportHandleMap; + +// +// Rm client to use to dup an object exported to RmObjExportHandle. The minimal +// requirement for duping is to have a device object allocated. This rm client +// is simply like any other external rm client and has no any special handling. +// +// We keep this rm client just like any other external rm client: if +// gpu(s)/device gets powered-down/uninitialized, rm objects allocated by +// external rm clients and located on that gpu(s)/device gets freed (the +// os-layer does that). In that way, code in this file doesn't need to worry +// about freeing exported objects located on that gpu(s)/device. +// +NvHandle hObjExportRmClient; + +// +// Tracker for device and subdevice handles. For now only one subdevice +// (instance 0) is supported per device. +// +typedef struct +{ + NvHandle hRmDevice; + NvHandle hRmSubDevice; +} RmObjExportDevice; + +RmObjExportDevice objExportDevice[NV_MAX_DEVICES]; + +// +// Usage reference counter for static object in this file like rm client used to +// dup an exported object, memory allocator, map etc. +// +NvU64 objExportImportRefCount; + +// +// Static functions for internal use to code in this file. +// +static NV_STATUS RmRefObjExportImport (void); +static void RmUnrefObjExportImport (void); + +static RmObjExportHandle RmGenerateObjExportHandle (NvU32 deviceInstance); +static NV_STATUS RmUnrefObjExportHandle (RmObjExportHandle hObject); + +// +// Free the RmObjExportHandle. +// +static NV_STATUS RmUnrefObjExportHandle(RmObjExportHandle hObject) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); + + RmObjExportHandleRef *pHandleRef = + mapFind(&objExportHandleMap, hObject); + + if (pHandleRef == NULL) + { + return NV_ERR_OBJECT_NOT_FOUND; + } + + if (pRmApi->Free(pRmApi, + hObjExportRmClient, + (NvHandle)mapKey(&objExportHandleMap, pHandleRef)) != NV_OK) + { + NV_PRINTF(LEVEL_WARNING, + "Exported object trying to free was zombie in %s\n", + __FUNCTION__); + } + + mapRemove(&objExportHandleMap, pHandleRef); + + return NV_OK; +} + +// +// Generate unique RmObjExportHandle. +// +static RmObjExportHandle RmGenerateObjExportHandle(NvU32 deviceInstance) +{ + // + // The object export handle belongs to range of 0 to + // (MAX_OBJ_EXPORT_HANDLES - 1). + // + // Handle 0 is considered as invalid object handle, this function generates + // handle from range of 1 to (MAX_OBJ_EXPORT_HANDLES - 1). + // + #define MAX_OBJ_EXPORT_HANDLES 0x80000 + + static NvHandle hObjExportHandleNext = 1; + + RmObjExportHandle hStartHandle = hObjExportHandleNext; + RmObjExportHandle hObject = 0; + + do + { + RmObjExportHandleRef *pHandleRef; + + hObject = hObjExportHandleNext++; + /* Reset hObjExportHandleNext to next valid handle */ + if (hObjExportHandleNext == MAX_OBJ_EXPORT_HANDLES) { + hObjExportHandleNext = 1; + } + + pHandleRef = mapFind(&objExportHandleMap, hObject); + + if (hObject != hObjExportRmClient && pHandleRef == NULL) + { + break; + } + else + { + hObject = 0; + } + + } while(hObjExportHandleNext != hStartHandle); + + if (hObject != 0) + { + RmObjExportHandleRef *pHandleRef = + mapInsertNew(&objExportHandleMap, hObject); + + if (pHandleRef != NULL) + { + pHandleRef->deviceInstance = deviceInstance; + } + else + { + hObject = 0; + } + } + + return hObject; +} + +// +// Validate that the given hObject is not one of our internally used handles. +// +// Note that mapFind(&objExportHandleMap, hObject) could still fail; that is the +// caller's responsibility. +// +static NvBool RmValidateHandleAgainstInternalHandles(RmObjExportHandle hObject) +{ + NvU32 i; + + // + // No external RmObjExportHandle could be valid if hObjExportRmClient has + // not been allocated yet, or if it is equal to any of the handles used + // internally by code in this file. + // + if (objExportImportRefCount == 0 || hObjExportRmClient == 0 || + hObject == hObjExportRmClient) + { + return NV_FALSE; + } + + for (i = 0; i < NV_ARRAY_ELEMENTS(objExportDevice); i++) + { + if (objExportDevice[i].hRmDevice != 0 && + (hObject == objExportDevice[i].hRmDevice || + hObject == objExportDevice[i].hRmSubDevice)) + { + return NV_FALSE; + } + } + + return NV_TRUE; +} + +// +// Increment reference count of static objects internally +// used by code in this file. +// +static NV_STATUS RmRefObjExportImport(void) +{ + NV_STATUS rmStatus = NV_OK; + RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); + + if ((objExportImportRefCount++) != 0) + { + NV_ASSERT(hObjExportRmClient != 0); + NV_ASSERT(pMemAllocator != NULL); + return NV_OK; + } + + rmStatus = pRmApi->AllocWithHandle(pRmApi, + NV01_NULL_OBJECT, + NV01_NULL_OBJECT, + NV01_NULL_OBJECT, + NV01_ROOT, + &hObjExportRmClient); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to alloc root in %s\n", __FUNCTION__); + goto failed; + } + + pMemAllocator = portMemAllocatorCreateNonPaged(); + + if (pMemAllocator == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to alloc memory allocator in %s\n", + __FUNCTION__); + goto failed; + } + + mapInit(&objExportHandleMap, pMemAllocator); + + return NV_OK; + +failed: + + RmUnrefObjExportImport(); + + return rmStatus; +} + +// +// Decrement reference count of static objects internally used by code in this +// file, and free them if reference count reaches to zero. +// +static void RmUnrefObjExportImport(void) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + if ((--objExportImportRefCount) != 0) + { + return; + } + + if (pMemAllocator != NULL) + { + NvU32 i; + + for (i = 0; i < NV_ARRAY_ELEMENTS(objExportDevice); i++) + { + if (objExportDevice[i].hRmDevice != 0) + { + RmUnrefObjExportHandle(objExportDevice[i].hRmSubDevice); + objExportDevice[i].hRmSubDevice = 0; + RmUnrefObjExportHandle(objExportDevice[i].hRmDevice); + objExportDevice[i].hRmDevice = 0; + } + } + + mapDestroy(&objExportHandleMap); + + portMemAllocatorRelease(pMemAllocator); + pMemAllocator = NULL; + } + + if (hObjExportRmClient != 0) + { + NV_STATUS rmStatus = pRmApi->Free(pRmApi, + hObjExportRmClient, + hObjExportRmClient); + + NV_ASSERT(rmStatus == NV_OK); + hObjExportRmClient = 0; + } +} + +NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject, + RmObjExportHandle *pDstObject, NvU32 *pDeviceInstance) +{ + RmObjExportHandle hDstObject; + NvU32 deviceInstance = NV_MAX_DEVICES; + NvHandle hTmpObject; + NvBool bClientAsDstParent = NV_FALSE; + NV_STATUS status; + RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); + + if (pDstObject == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // + // Find the device instance on which the rm object exists. + // + hTmpObject = hSrcObject; + do + { + RsResourceRef *pResourceRef; + + status = serverutilGetResourceRef(hSrcClient, hTmpObject, &pResourceRef); + if (status != NV_OK) + return status; + + Device *pDevice = dynamicCast(pResourceRef->pResource, Device); + if (pDevice != NULL) + { + deviceInstance = pDevice->deviceInst; + break; + } + + hTmpObject = pResourceRef->pParentRef ? pResourceRef->pParentRef->hResource : 0; + } while (hTmpObject != 0); + + // If a memory object is not parented by a device, use client as a parent. + if ((hTmpObject == 0) || (deviceInstance >= NV_MAX_DEVICES)) + { + bClientAsDstParent = NV_TRUE; + } + + status = RmRefObjExportImport(); + + if (status != NV_OK) + { + return status; + } + + if (!bClientAsDstParent && + ((objExportDevice[deviceInstance].hRmDevice == 0) || + serverutilValidateNewResourceHandle(hObjExportRmClient, + objExportDevice[deviceInstance].hRmDevice))) + { + // + // Device object has not been created or it got destroyed in the + // teardown path of device instance destruction; allocate a fresh device + // object. + // + NV0080_ALLOC_PARAMETERS params; + NV2080_ALLOC_PARAMETERS subdevParams; + + if (objExportDevice[deviceInstance].hRmDevice == 0) + { + NV_ASSERT(objExportDevice[deviceInstance].hRmSubDevice == 0); + + objExportDevice[deviceInstance].hRmDevice = + RmGenerateObjExportHandle(deviceInstance); + objExportDevice[deviceInstance].hRmSubDevice = + RmGenerateObjExportHandle(deviceInstance); + + if (objExportDevice[deviceInstance].hRmDevice == 0 || + objExportDevice[deviceInstance].hRmSubDevice == 0) + { + NV_PRINTF(LEVEL_ERROR, "Failed to allocate object handles in %s\n", + __FUNCTION__); + + status = NV_ERR_NO_MEMORY; + goto done; + } + } + + portMemSet(¶ms, 0, sizeof(NV0080_ALLOC_PARAMETERS)); + + params.deviceId = deviceInstance; + + status = pRmApi->AllocWithHandle(pRmApi, + hObjExportRmClient, + hObjExportRmClient, + objExportDevice[deviceInstance].hRmDevice, + NV01_DEVICE_0, + ¶ms); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to alloc device in %s\n", + __FUNCTION__); + goto done; + } + + portMemSet(&subdevParams, 0, sizeof(NV2080_ALLOC_PARAMETERS)); + + subdevParams.subDeviceId = 0; + + status = pRmApi->AllocWithHandle(pRmApi, + hObjExportRmClient, + objExportDevice[deviceInstance].hRmDevice, + objExportDevice[deviceInstance].hRmSubDevice, + NV20_SUBDEVICE_0, + &subdevParams); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to alloc subdevice in %s\n", + __FUNCTION__); + + (void) pRmApi->Free(pRmApi, hObjExportRmClient, + objExportDevice[deviceInstance].hRmDevice); + goto done; + } + } + + hDstObject = RmGenerateObjExportHandle(deviceInstance); + + if (hDstObject == 0) + { + NV_PRINTF(LEVEL_ERROR, "Failed to allocate object handle in %s\n", + __FUNCTION__); + status = NV_ERR_NO_MEMORY; + goto done; + } + + // If duping under device handle fails, try subdevice handle. + status = pRmApi->DupObject(pRmApi, + hObjExportRmClient, + bClientAsDstParent ? hObjExportRmClient : + objExportDevice[deviceInstance].hRmDevice, + &hDstObject, + hSrcClient, + hSrcObject, + 0 /* flags */); + if (status != NV_OK) + { + if (!bClientAsDstParent && (status == NV_ERR_INVALID_OBJECT_PARENT)) + { + NV_PRINTF(LEVEL_INFO, + "pRmApi->DupObject(Dev, failed due to invalid parent in %s." + " Now attempting DupObject with Subdev handle.\n", + __FUNCTION__); + + status = pRmApi->DupObject(pRmApi, + hObjExportRmClient, + objExportDevice[deviceInstance].hRmSubDevice, + &hDstObject, + hSrcClient, + hSrcObject, + 0 /* flags */); + if (status != NV_OK) + { + RmUnrefObjExportHandle(hDstObject); + + NV_PRINTF(LEVEL_ERROR, + "pRmApi->DupObject(Subdev, failed with error code 0x%x in %s\n", + status, __FUNCTION__); + goto done; + } + } + else + { + RmUnrefObjExportHandle(hDstObject); + + NV_PRINTF(LEVEL_ERROR, + "pRmApi->DupObject(Dev, failed with error code 0x%x in %s\n", + status, __FUNCTION__); + goto done; + } + } + + if (pDeviceInstance != NULL) + { + *pDeviceInstance = deviceInstance; + } + + *pDstObject = hDstObject; + +done: + if (status != NV_OK) + { + RmUnrefObjExportImport(); + } + + return status; +} + +void RmFreeObjExportHandle(RmObjExportHandle hObject) +{ + if (!RmValidateHandleAgainstInternalHandles(hObject)) + { + NV_PRINTF(LEVEL_ERROR, "Invalid handle to exported object in %s\n", + __FUNCTION__); + return; + } + + RmUnrefObjExportHandle(hObject); + + RmUnrefObjExportImport(); +} + +NV_STATUS RmImportObject(NvHandle hDstClient, NvHandle hDstParent, + NvHandle *phDstObject, RmObjExportHandle hSrcObject, + NvU8 *pObjectType) +{ + NV_STATUS status; + NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS params; + RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); + + if (!RmValidateHandleAgainstInternalHandles(hSrcObject)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (mapFind(&objExportHandleMap, hSrcObject) == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (pObjectType != NULL) + { + params.hObject = hSrcObject; + params.mapFlags = 0; + params.addrSpaceType = \ + NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_INVALID; + + status = pRmApi->Control(pRmApi, hObjExportRmClient, hObjExportRmClient, + NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE, + ¶ms, sizeof(params)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "GET_ADDR_SPACE_TYPE failed with error code 0x%x in %s\n", + status, __FUNCTION__); + return status; + } + + switch (params.addrSpaceType) + { + case NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_SYSMEM: + *pObjectType = NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_SYSMEM; + break; + case NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM: + *pObjectType = NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_VIDMEM; + break; + case NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC: + *pObjectType = NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC; + break; +#if defined(NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC_MC) && \ + defined(NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC_MC) + case NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC_MC: + *pObjectType = NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC_MC; + break; +#endif + default: + NV_ASSERT_OK_OR_RETURN(NV_ERR_INVALID_ARGUMENT); + } + } + + status = pRmApi->DupObject(pRmApi, hDstClient, hDstParent, phDstObject, + hObjExportRmClient, hSrcObject, + 0 /* flags */); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "pRmApi->DupObject(pRmApi, failed with error code 0x%x in %s\n", + status, __FUNCTION__); + return status; + } + + return NV_OK; +} + +NV_STATUS RmGetExportObjectInfo(RmObjExportHandle hSrcObject, NvU32 *deviceInstance) +{ + RmObjExportHandleRef *pHandleRef = NULL; + + if (!RmValidateHandleAgainstInternalHandles(hSrcObject)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + pHandleRef = mapFind(&objExportHandleMap, hSrcObject); + if (pHandleRef == NULL) + { + return NV_ERR_OBJECT_NOT_FOUND; + } + + *deviceInstance = pHandleRef->deviceInstance; + return NV_OK; +} diff --git a/userspace/sdks/nv525/nvalloc/unix/src/subdevice_ctrl_os_unix.c b/userspace/sdks/nv525/nvalloc/unix/src/subdevice_ctrl_os_unix.c new file mode 100644 index 0000000..6989c7c --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/src/subdevice_ctrl_os_unix.c @@ -0,0 +1,100 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include // NV device driver interface +#include +#include +#include +#include +#include "gpu/gpu.h" +#include "gpu/gpu_resource.h" +#include "gpu/subdevice/subdevice.h" +#include +#include +#include "gpu/mem_mgr/mem_desc.h" +#include "mem_mgr/mem.h" +#include +#include +#include "rmapi/rs_utils.h" +#include "rmapi/client_resource.h" +#include +#include +#include // NV01_EVENT +#include // NV01_MEMORY_SYSTEM +#include // G84_PERFBUFFER +#include +#include +#include +#include + +/*! + * @brief Implements the NV2080_CTRL_CMD_OS_UNIX_VIDMEM_PERSISTENCE_STATUS + * RmControl request. It will check if the GPU video memory will be + * persistent during system suspend/resume cycle. + * + * @param[in] pSubdevice + * @param[in,out] pParams + * + * @return + * NV_OK Success + */ +NV_STATUS +subdeviceCtrlCmdOsUnixVidmemPersistenceStatus_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + pParams->bVidmemPersistent = !gpuIsVidmemPreservationBrokenBug3172217(pGpu) && + (nv->preserve_vidmem_allocations || + nvp->s0ix_pm_enabled); + + return NV_OK; +} + +/*! + * @brief Implements the NV2080_CTRL_CMD_OS_UNIX_UPDATE_TGP_STATUS + * RmControl request. It sets restore TGP flag which is used + * to restore TGP limits when client is killed. + * + * @param[in] pSubdevice + * @param[in] pParams + * + * @return + * NV_OK Success + */ +NV_STATUS +subdeviceCtrlCmdOsUnixUpdateTgpStatus_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS *pParams +) +{ + pSubdevice->bUpdateTGP = pParams->bUpdateTGP; + + return NV_OK; +} diff --git a/userspace/sdks/nv525/nvalloc/unix/src/unix_console.c b/userspace/sdks/nv525/nvalloc/unix/src/unix_console.c new file mode 100644 index 0000000..8b1c055 --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/src/unix_console.c @@ -0,0 +1,118 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +NV_STATUS deviceCtrlCmdOsUnixVTGetFBInfo_IMPL +( + Device *pDevice, + NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); + NvBool bContinue = NV_TRUE; + + if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_FB) == NV_OK) + { + // See if the console is on one of the subdevices of this device. + portMemSet(pParams, 0, sizeof(*pParams)); + + SLI_LOOP_START(SLI_LOOP_FLAGS_NONE) + + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + if ((memmgrGetReservedConsoleMemDesc(pGpu, pMemoryManager) != NULL) && bContinue) + { + NvU64 baseAddr; + + // There should only be one. + NV_ASSERT(pParams->width == 0); + + pParams->subDeviceInstance = gpumgrGetSubDeviceInstanceFromGpu(pGpu); + + // Console is either mapped to BAR1 or BAR2 + 16 MB + os_get_screen_info(&baseAddr, &pParams->width, + &pParams->height, &pParams->depth, + &pParams->pitch, + nv->bars[NV_GPU_BAR_INDEX_FB].cpu_address, + nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000); + + if (baseAddr != 0) + { + bContinue = NV_FALSE; + } + } + + SLI_LOOP_END + + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + else + { + NV_PRINTF(LEVEL_INFO,"%s: Failed to acquire GPU lock", __FUNCTION__); + } + + return NV_OK; +} + + +void +dispdeviceFillVgaSavedDisplayState +( + OBJGPU *pGpu, + NvU64 vgaAddr, + NvU8 vgaMemType, + NvBool vgaValid, + NvU64 workspaceAddr, + NvU8 workspaceMemType, + NvBool workspaceValid, + NvBool baseValid, + NvBool workspaceBaseValid +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvBool use_vbios = NV_PRIMARY_VGA(nv) && RmGpuHasIOSpaceEnabled(nv); + + if (use_vbios) + { + nvp->vga.base.addr = vgaAddr; + nvp->vga.base.memTarget = vgaMemType; + nvp->vga.base.valid = vgaValid; + nvp->vga.baseValid = baseValid; + + nvp->vga.workspaceBase.addr = workspaceAddr; + nvp->vga.workspaceBase.memTarget = workspaceMemType; + nvp->vga.workspaceBase.valid = workspaceValid; + nvp->vga.workspaceBaseValid = workspaceBaseValid; + } +} + diff --git a/userspace/sdks/nv525/nvalloc/unix/src/unix_intr.c b/userspace/sdks/nv525/nvalloc/unix/src/unix_intr.c new file mode 100644 index 0000000..d60a30d --- /dev/null +++ b/userspace/sdks/nv525/nvalloc/unix/src/unix_intr.c @@ -0,0 +1,700 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include "kernel/gpu/intr/intr.h" +#include "gpu/bif/kernel_bif.h" +#include "gpu/mmu/kern_gmmu.h" +#include "gpu/disp/kern_disp.h" +#include +#include "objtmr.h" + + +static NvBool osInterruptPending( + OBJGPU *pGpu, + NvBool *serviced, + THREAD_STATE_NODE *pThreadState +) +{ + POBJDISP pDisp; + KernelDisplay *pKernelDisplay; + NvBool pending, sema_release; + THREAD_STATE_NODE threadState; + NvU32 gpuMask, gpuInstance; + Intr *pIntr = NULL; + MC_ENGINE_BITVECTOR intr0Pending; + MC_ENGINE_BITVECTOR intr1Pending; + + *serviced = NV_FALSE; + pending = NV_FALSE; + sema_release = NV_TRUE; + OBJGPU *pDeviceLockGpu = pGpu; + NvU8 stackAllocator[TLS_ISR_ALLOCATOR_SIZE]; // ISR allocations come from this buffer + PORT_MEM_ALLOCATOR *pIsrAllocator; + + // + // GPU interrupt servicing ("top half") + // + // Top-level processing of GPU interrupts is performed using the + // steps below; although the code is straight forward, there + // are a few points to be aware of: + // + // 1) The GPUs lock is acquired for two reasons: to allow + // looping over GPUs atomically in SLI and to sanity + // check the PCI configuration space of any initialized + // GPUs. If the acquisition fails, the early return + // is acceptable since GPU interrupts are disabled while + // the lock is held; note that returning success + // in this case could interfere with the processing + // of third-party device interrupts if the IRQ is shared. + // Due to the above, some interrupts may be reported as + // unhandled if invocations of the ISR registered with + // the kernel are not serialized. This is bad, but + // ignored by currently supported kernels, provided most + // interrupts are handled. + // + // 2) Since acquisition of the lock disables interrupts + // on all initialized GPUs, NV_PMC_INTR_EN_0 can not be + // relied up on to determine whether interrupts are + // expected from a given GPU. The code below is therefore + // forced to rely on software state. NV_PMC_INTR_EN_0 + // is read only as a sanity check to guard against + // invalid GPU state (lack of PCI memory access, etc.). + // + // 3) High priority interrupts (VBLANK, etc.), are serviced in + // this function, service of all other interrupts is + // deferred until a bottom half. If a bottom half needs + // to be scheduled, release of the GPUs lock is + // likewise deferred until completion of the bottom half. + // + // 4) To reduce the risk of starvation, an effort is made to + // consolidate processing of interrupts pending on + // all GPUs sharing a given IRQ. + // + // 5) Care is taken to ensure that the consolidated interrupt + // processing is performed in the context of a GPU + // that has interrupts pending. Else if additional ISR + // processing via a bottom-half is required, this + // bottom-half ISR might race against the GPU's shut-down + // path. + // + + pIsrAllocator = portMemAllocatorCreateOnExistingBlock(stackAllocator, sizeof(stackAllocator)); + tlsIsrInit(pIsrAllocator); + + // For SWRL granular locking process the countdown timer interrupt. + if (pDeviceLockGpu->getProperty(pDeviceLockGpu, PDB_PROP_GPU_SWRL_GRANULAR_LOCKING)) + { + threadStateInitISRLockless(&threadState, pDeviceLockGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS); + + gpuMask = gpumgrGetGpuMask(pDeviceLockGpu); + + gpuInstance = 0; + while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + pIntr = GPU_GET_INTR(pGpu); + + if (INTERRUPT_TYPE_HARDWARE == intrGetIntrEn(pIntr)) + { + // If interrupt enable is garbage the GPU is probably in a bad state + if (intrGetIntrEnFromHw_HAL(pGpu, pIntr, &threadState) > INTERRUPT_TYPE_MAX) + { + continue; + } + + intrGetPendingStall_HAL(pGpu, pIntr, &intr0Pending, &threadState); + POBJTMR pTmr = GPU_GET_TIMER(pGpu); + *serviced = tmrServiceSwrlWrapper(pGpu, pTmr, &intr0Pending, &threadState); + } + } + + threadStateFreeISRLockless(&threadState, pDeviceLockGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS); + } + + // LOCK: try to acquire GPUs lock + if (rmDeviceGpuLocksAcquire(pDeviceLockGpu, GPU_LOCK_FLAGS_COND_ACQUIRE, RM_LOCK_MODULES_ISR) == NV_OK) + { + threadStateInitISRAndDeferredIntHandler(&threadState, + pDeviceLockGpu, THREAD_STATE_FLAGS_IS_ISR); + + gpuMask = gpumgrGetGpuMask(pDeviceLockGpu); + + gpuInstance = 0; + while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + pIntr = GPU_GET_INTR(pGpu); + pDisp = GPU_GET_DISP(pGpu); + pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + + if ((pDisp != NULL) && pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) + { + } + else if ((pIntr != NULL) && INTERRUPT_TYPE_HARDWARE == intrGetIntrEn(pIntr)) + { + // If interrupt enable is garbage the GPU is probably in a bad state + if (intrGetIntrEnFromHw_HAL(pGpu, pIntr, &threadState) > INTERRUPT_TYPE_MAX) + continue; + + intrGetPendingStall_HAL(pGpu, pIntr, &intr0Pending, &threadState); + if (bitVectorTest(&intr0Pending, MC_ENGINE_IDX_DISP)) + { + if (pKernelDisplay != NULL) + { + kdispServiceVblank_HAL(pGpu, pKernelDisplay, 0, + (VBLANK_STATE_PROCESS_LOW_LATENCY | + VBLANK_STATE_PROCESS_CALLED_FROM_ISR), + &threadState); + *serviced = NV_TRUE; + intrGetPendingStall_HAL(pGpu, pIntr, &intr0Pending, &threadState); + } + } + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_ENABLED) && + !pGpu->getProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS)) + { + pIntr = GPU_GET_INTR(pGpu); + if (pIntr != NULL) + { + NvBool bCtxswLog = NV_FALSE; + intrGetPendingNonStall_HAL(pGpu, pIntr, &intr1Pending, &threadState); + intrCheckFecsEventbufferPending(pGpu, pIntr, &intr1Pending, &bCtxswLog); + } + } + + if (!bitVectorTestAllCleared(&intr0Pending) || + !bitVectorTestAllCleared(&intr1Pending)) + { + pending = NV_TRUE; + sema_release = NV_FALSE; + } + } + } + threadStateFreeISRAndDeferredIntHandler(&threadState, + pDeviceLockGpu, THREAD_STATE_FLAGS_IS_ISR); + + if (sema_release) + { + NV_ASSERT(!pending); + + // UNLOCK: release GPUs lock + rmDeviceGpuLocksRelease(pDeviceLockGpu, GPUS_LOCK_FLAGS_NONE, NULL); + } + else + { + rmDeviceGpuLockSetOwner(pDeviceLockGpu, GPUS_LOCK_OWNER_PENDING_DPC_REFRESH); + } + } + + if (pDeviceLockGpu->getProperty(pDeviceLockGpu, PDB_PROP_GPU_ALTERNATE_TREE_ENABLED) && + pDeviceLockGpu->getProperty(pDeviceLockGpu, PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS)) + { + threadStateInitISRLockless(&threadState, pDeviceLockGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS); + + gpuMask = gpumgrGetGpuMask(pDeviceLockGpu); + gpuInstance = 0; + while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + pIntr = GPU_GET_INTR(pGpu); + if ((pIntr != NULL) && (INTERRUPT_TYPE_HARDWARE == intrGetIntrEn(pIntr))) + { + NvBool bCtxswLog = NV_FALSE; + intrGetPendingNonStall_HAL(pGpu, pIntr, &intr1Pending, &threadState); + intrCheckFecsEventbufferPending(pGpu, pIntr, &intr1Pending, &bCtxswLog); + if (!bitVectorTestAllCleared(&intr1Pending)) + { + intrServiceNonStall_HAL(pGpu, pIntr, &intr1Pending, &threadState); + *serviced = NV_TRUE; + } + } + } + threadStateFreeISRLockless(&threadState, pDeviceLockGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS); + } + + tlsIsrDestroy(pIsrAllocator); + portMemAllocatorRelease(pIsrAllocator); + + return pending; +} + +NV_STATUS osIsr( + OBJGPU *pGpu +) +{ + NV_STATUS status = NV_OK; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvBool pending = NV_FALSE; + NvBool serviced = NV_FALSE; + Intr *pIntr; + + if (nvp->flags & NV_INIT_FLAG_GPU_STATE_LOAD) + { + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) + { + pending = osInterruptPending(pGpu, &serviced, NULL /* threadstate */); + } + else + { + pIntr = GPU_GET_INTR(pGpu); + if (INTERRUPT_TYPE_HARDWARE == intrGetIntrEn(pIntr)) + { + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + pending = osInterruptPending(pGpu, &serviced, NULL /* threadstate */); + kbifCheckAndRearmMSI(pGpu, pKernelBif); + } + } + } + + if (!pending && (IS_VIRTUAL(pGpu) || !serviced)) + status = NV_ERR_NO_INTR_PENDING; + else if (pending) + status = NV_WARN_MORE_PROCESSING_REQUIRED; + + return status; +} + +/* + * Helper function to determine when the RM SEMA/GPUS LOCK should toggle + * interrupts. Based on the state of the GPU - we must add cases here as we + * discover them. + * + * Noteworthy special cases: + * + * - Suspend/resume: the GPU could still be suspended and not accessible + * on the bus, while passive-level threads need to grab the GPUs + * lock, or other GPUs are being resumed and triggering interrupts. + * + * - SLI state transitions: interrupts are disabled manually prior to + * removing GPUs from the lock mask leading up to SLI link/unlink + * operations on UNIX, but since the GPUs lock is not held by design in + * these paths, it needs to be ensured that GPUs lock acquisitions + * occurring aynchronously do not re-enable interrupts on any of the + * GPUs undergoing the SLI state transition. + * + * @param[in] pGpu OBJGPU pointer + * + * @return NV_TRUE if the RM SEMA/GPUS LOCK should toggle interrupts, NV_FALSE + * otherwise. + */ +NvBool osLockShouldToggleInterrupts(OBJGPU *pGpu) +{ + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) + return NV_TRUE; + + return (!pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_PM_CODEPATH) && + gpuIsStateLoaded(pGpu) && + !pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_SLI_LINK_CODEPATH)); +} + +void osEnableInterrupts(OBJGPU *pGpu) +{ + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) + { + // enable irq through os call + nv_control_soc_irqs(NV_GET_NV_STATE(pGpu), NV_TRUE); + return; + } + else + { + Intr *pIntr = GPU_GET_INTR(pGpu); + NvU32 intrEn; + + if (!pIntr->getProperty(pIntr, PDB_PROP_INTR_USE_INTR_MASK_FOR_LOCKING)) + NV_ASSERT(intrGetIntrEnFromHw_HAL(pGpu, pIntr, NULL) == INTERRUPT_TYPE_DISABLED); + + intrEn = intrGetIntrEn(pIntr); + intrSetIntrEnInHw_HAL(pGpu, pIntr, intrEn, NULL); + + if (pIntr != NULL) + { + intrSetStall_HAL(pGpu, pIntr, intrEn, NULL); + } + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_ENABLED)) + { + if (pIntr != NULL) + { + intrRestoreNonStall_HAL(pGpu, pIntr, intrGetIntrEn(pIntr), NULL); + } + } + + } +} + +void osDisableInterrupts( + OBJGPU *pGpu, + NvBool bIsr +) +{ + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) + { + // disable irq through os call + nv_control_soc_irqs(NV_GET_NV_STATE(pGpu), NV_FALSE); + return; + } + else + { + Intr *pIntr = GPU_GET_INTR(pGpu); + NvU32 new_intr_en_0 = INTERRUPT_TYPE_DISABLED; + + intrSetIntrEnInHw_HAL(pGpu, pIntr, new_intr_en_0, NULL); + + if (pIntr != NULL) + { + intrSetStall_HAL(pGpu, pIntr, new_intr_en_0, NULL); + } + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_ENABLED)) + { + if (pIntr != NULL) + { + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS)) + { + intrRestoreNonStall_HAL(pGpu, pIntr, intrGetIntrEn(pIntr), NULL); + } + else + { + intrRestoreNonStall_HAL(pGpu, pIntr, new_intr_en_0, NULL); + } + } + } + } +} + +static void RmIsrBottomHalf( + nv_state_t *pNv +) +{ + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + THREAD_STATE_NODE threadState; + OS_THREAD_HANDLE threadId; + NvU32 gpuMask, gpuInstance; + OBJGPU *pDeviceLockGpu = pGpu; + Intr *pIntr = NULL; + POBJDISP pDisp = NULL; + NvU8 stackAllocator[TLS_ISR_ALLOCATOR_SIZE]; // ISR allocations come from this buffer + PORT_MEM_ALLOCATOR *pIsrAllocator; + + pIsrAllocator = portMemAllocatorCreateOnExistingBlock(stackAllocator, sizeof(stackAllocator)); + tlsIsrInit(pIsrAllocator); + + // + // The owning thread changes as the ISR acquires the GPUs lock, + // but the bottom half releases it. Refresh the ThreadId owner to be + // correct here for the bottom half context. + // + osGetCurrentThread(&threadId); + rmDeviceGpuLockSetOwner(pDeviceLockGpu, threadId); + + gpuMask = gpumgrGetGpuMask(pGpu); + + gpuInstance = 0; + while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + + threadStateInitISRAndDeferredIntHandler(&threadState, + pGpu, THREAD_STATE_FLAGS_IS_ISR_DEFERRED_INT_HANDLER); + + pIntr = GPU_GET_INTR(pGpu); + pDisp = GPU_GET_DISP(pGpu); + + // + // Call disp service incase of SOC Display, + // TODO : with multi interrupt handling based on irq aux interrupts are serviced by dpAuxService + // See JIRA task TDS-4253. + // + if ((pDisp != NULL) && pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) + { + } + else if ((pIntr != NULL) && (INTERRUPT_TYPE_HARDWARE == intrGetIntrEn(pIntr))) + { + intrServiceStall_HAL(pGpu, pIntr); + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_ENABLED) && + !pGpu->getProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS)) + { + MC_ENGINE_BITVECTOR intrPending; + intrServiceNonStall_HAL(pGpu, pIntr, &intrPending, &threadState); + } + } + + threadStateFreeISRAndDeferredIntHandler(&threadState, + pGpu, THREAD_STATE_FLAGS_IS_ISR_DEFERRED_INT_HANDLER); + } + + // UNLOCK: release GPUs lock + rmDeviceGpuLocksRelease(pDeviceLockGpu, GPUS_LOCK_FLAGS_NONE, NULL); + + tlsIsrDestroy(pIsrAllocator); + portMemAllocatorRelease(pIsrAllocator); +} + +static void RmIsrBottomHalfUnlocked( + nv_state_t *pNv +) +{ + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + Intr *pIntr; + THREAD_STATE_NODE threadState; + + // In the GSP client scenario, the fatal fault interrupt is not shared + // by UVM and CPU-RM. Instead, it is handled entirely by GSP-RM. We + // therefore do not expect this function to be called. But if it is, bail + // without attempting to service interrupts. + if (IS_GSP_CLIENT(pGpu)) + { + return; + } + + // Grab GPU lock here as this kthread-item was enqueued without grabbing GPU lock + if (rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DPC) == NV_OK) + { + if (FULL_GPU_SANITY_CHECK(pGpu)) + { + pIntr = GPU_GET_INTR(pGpu); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + if (intrGetIntrEn(pIntr) != INTERRUPT_TYPE_DISABLED) + { + MC_ENGINE_BITVECTOR intrPending; + intrGetPendingStall_HAL(pGpu, pIntr, &intrPending, &threadState); + intrServiceNonStallBottomHalf(pGpu, pIntr, &intrPending, &threadState); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + } + + rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); + } +} + +NvBool NV_API_CALL rm_isr( + nvidia_stack_t *sp, + nv_state_t *nv, + NvU32 *NeedBottomHalf +) +{ + NV_STATUS status; + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + OBJGPU *pGpu; + NvBool retval; + void *fp; + + if ((nvp->flags & NV_INIT_FLAG_GPU_STATE_LOAD) == 0) + { + return NV_FALSE; + } + + pGpu = NV_GET_NV_PRIV_PGPU(nv); + if (pGpu == NULL) + { + return NV_FALSE; + } + + NV_ENTER_RM_RUNTIME(sp,fp); + + // call actual isr function here + status = isrWrapper(pGpu->testIntr, pGpu); + + switch (status) + { + case NV_OK: + *NeedBottomHalf = NV_FALSE; + retval = NV_TRUE; + break; + case NV_WARN_MORE_PROCESSING_REQUIRED: + *NeedBottomHalf = NV_TRUE; + retval = NV_TRUE; + break; + case NV_ERR_NO_INTR_PENDING: + default: + *NeedBottomHalf = NV_FALSE; + retval = NV_FALSE; + break; + } + + NV_EXIT_RM_RUNTIME(sp,fp); + + return retval; +} + +void NV_API_CALL rm_isr_bh( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + RmIsrBottomHalf(pNv); + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +void NV_API_CALL rm_isr_bh_unlocked( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + RmIsrBottomHalfUnlocked(pNv); + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults( + nvidia_stack_t *sp, + nv_state_t *nv, + NvU32 *faultsCopied +) +{ + NV_STATUS status = NV_OK; + OBJGPU *pGpu; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + pGpu = NV_GET_NV_PRIV_PGPU(nv); + if (pGpu == NULL || faultsCopied == NULL) + { + status = NV_ERR_OBJECT_NOT_FOUND; + goto done; + } + + // Non-replayable faults are copied to the client shadow buffer by GSP-RM. + if (IS_GSP_CLIENT(pGpu)) + { + status = NV_ERR_NOT_SUPPORTED; + goto done; + } + +done: + NV_EXIT_RM_RUNTIME(sp,fp); + + return status; +} + +// +// Use this call when MMU faults needs to be copied +// outisde of RM lock. +// +NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults_unlocked( + nvidia_stack_t *sp, + nv_state_t *nv, + NvU32 *faultsCopied +) +{ + OBJGPU *pGpu; + void *fp; + NV_STATUS status = NV_OK; + + NV_ENTER_RM_RUNTIME(sp,fp); + + pGpu = NV_GET_NV_PRIV_PGPU(nv); + if (pGpu == NULL || faultsCopied == NULL) + { + status = NV_ERR_OBJECT_NOT_FOUND; + goto done; + } + + // Non-replayable faults are copied to the client shadow buffer by GSP-RM. + if (IS_GSP_CLIENT(pGpu)) + { + status = NV_ERR_NOT_SUPPORTED; + goto done; + } + +done: + NV_EXIT_RM_RUNTIME(sp,fp); + + return status; +} + +// +// Wrapper to handle calls to copy mmu faults +// +NV_STATUS rm_gpu_handle_mmu_faults( + nvidia_stack_t *sp, + nv_state_t *nv, + NvU32 *faultsCopied +) +{ + NvU32 status = NV_OK; + + *faultsCopied = 0; + + OBJGPU *pGpu; + pGpu = NV_GET_NV_PRIV_PGPU(nv); + + if (pGpu == NULL) + { + return NV_ERR_OBJECT_NOT_FOUND; + } + + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && !IS_VIRTUAL(pGpu)) + { + THREAD_STATE_NODE threadState; + + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + Intr *pIntr = GPU_GET_INTR(pGpu); + + NvU32 hw_put = 0; + NvU32 hw_get = 0; + + threadStateInitISRLockless(&threadState, pGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS); + + kgmmuReadFaultBufferPutPtr_HAL(pGpu, pKernelGmmu, NON_REPLAYABLE_FAULT_BUFFER, + &hw_put, &threadState); + + kgmmuReadFaultBufferGetPtr_HAL(pGpu, pKernelGmmu, NON_REPLAYABLE_FAULT_BUFFER, + &hw_get, &threadState); + + if(hw_get != hw_put) + { + // We have to clear the top level interrupt bit here since otherwise + // the bottom half will attempt to service the interrupt on the CPU + // side before GSP recieves the notification and services it + kgmmuClearNonReplayableFaultIntr(pGpu, pKernelGmmu, &threadState); + status = intrTriggerPrivDoorbell_HAL(pGpu, pIntr, NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_HANDLE); + + } + + threadStateFreeISRLockless(&threadState, pGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS); + } + else + { + status = rm_gpu_copy_mmu_faults_unlocked(sp, nv, faultsCopied); + } + return status; +} + diff --git a/userspace/sdks/nv525/nvidia/inc/Nvcm.h b/userspace/sdks/nv525/nvidia/inc/Nvcm.h new file mode 100644 index 0000000..71dc880 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/Nvcm.h @@ -0,0 +1,71 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/******************* Operating System Interface Routines *******************\ +* * +* Module: NVCM.H * +* Windows Configuration Manager defines and prototypes. * +* * +* ***IMPORTANT*** The interfaces defined in this file are *deprecated* * +* ***IMPORTANT*** in favor of RmControl. * +* ***IMPORTANT*** Try hard to not use this file at all and definitely * +* ***IMPORTANT*** do not add or modify interfaces here. * +* Ref: bug 488474: delete CFG and CFG_EX * +* * +\***************************************************************************/ + +#ifndef _NVCM_H_ +#define _NVCM_H_ + +#include "nvdeprecated.h" + +#if NV_DEPRECATED_COMPAT(RM_CONFIG_GET_SET) + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvgputypes.h" +#ifndef _H2INC +#include "rmcd.h" +#endif + +#include "nverror.h" + +#define NV_ROBUST_CHANNEL_ALLOCFAIL_CLIENT 0x00000001 +#define NV_ROBUST_CHANNEL_ALLOCFAIL_DEVICE 0x00000002 +#define NV_ROBUST_CHANNEL_ALLOCFAIL_SUBDEVICE 0x00000004 +#define NV_ROBUST_CHANNEL_ALLOCFAIL_CHANNEL 0x00000008 +#define NV_ROBUST_CHANNEL_ALLOCFAIL_CTXDMA 0x00000010 +#define NV_ROBUST_CHANNEL_ALLOCFAIL_EVENT 0x00000020 +#define NV_ROBUST_CHANNEL_ALLOCFAIL_MEMORY 0x00000040 +#define NV_ROBUST_CHANNEL_ALLOCFAIL_OBJECT 0x00000080 +#define NV_ROBUST_CHANNEL_ALLOCFAIL_HEAP 0x00000100 + +#define NV_ROBUST_CHANNEL_BREAKONERROR_DEFAULT 0x00000000 +#define NV_ROBUST_CHANNEL_BREAKONERROR_DISABLE 0x00000001 +#define NV_ROBUST_CHANNEL_BREAKONERROR_ENABLE 0x00000002 + +#endif // NV_DEPRECATED_RM_CONFIG_GET_SET + +#endif // _NVCM_H_ diff --git a/userspace/sdks/nv525/nvidia/inc/alloc/alloc_channel.h b/userspace/sdks/nv525/nvidia/inc/alloc/alloc_channel.h new file mode 100644 index 0000000..4e96204 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/alloc/alloc_channel.h @@ -0,0 +1,319 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: alloc/alloc_channel.finn +// + +#include "nvlimits.h" +#include "nvcfg_sdk.h" + +typedef struct NV_MEMORY_DESC_PARAMS { + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 addressSpace; + NvU32 cacheAttrib; +} NV_MEMORY_DESC_PARAMS; + + +/* + * NV_CHANNEL_ALLOC_PARAMS.flags values. + * + * These flags may apply to all channel types: PIO, DMA, and GPFIFO. + * They are also designed so that zero is always the correct default. + * + * NVOS04_FLAGS_CHANNEL_TYPE: + * This flag specifies the type of channel to allocate. Legal values + * for this flag include: + * + * NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL: + * This flag specifies that a physical channel is to be allocated. + * + * NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL: + * OBSOLETE - NOT SUPPORTED + * + * NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL: + * OBSOLETE - NOT SUPPORTED + */ + +/* valid NVOS04_FLAGS_CHANNEL_TYPE values */ +#define NVOS04_FLAGS_CHANNEL_TYPE 1:0 +#define NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL 0x00000000 +#define NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL 0x00000001 // OBSOLETE +#define NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL 0x00000002 // OBSOLETE + +/* + * NVOS04_FLAGS_VPR: + * This flag specifies if channel is intended for work with + * Video Protected Regions (VPR) + * + * NVOS04_FLAGS_VPR_TRUE: + * The channel will only write to protected memory regions. + * + * NVOS04_FLAGS_VPR_FALSE: + * The channel will never read from protected memory regions. + */ +#define NVOS04_FLAGS_VPR 2:2 +#define NVOS04_FLAGS_VPR_FALSE 0x00000000 +#define NVOS04_FLAGS_VPR_TRUE 0x00000001 + + + +/* + * NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING: + * This flag specifies if the channel can skip refcounting of potentially + * accessed mappings on job kickoff. This flag is only meaningful for + * kernel drivers which perform refcounting of memory mappings. + * + * NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE: + * The channel cannot not skip refcounting of memory mappings + * + * NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE: + * The channel can skip refcounting of memory mappings + */ +#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING 3:3 +#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE: + * This flag specifies which "runqueue" the allocated channel will be + * executed on in a TSG. Channels on different runqueues within a TSG + * may be able to feed methods into the engine simultaneously. + * Non-default values are only supported on GP10x and later and only for + * channels within a TSG. + */ +#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE 4:4 +#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_DEFAULT 0x00000000 +#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_ONE 0x00000001 + +/* + * NVOS04_FLAGS_PRIVILEGED_CHANNEL: + * This flag tells RM whether to give the channel admin privilege. This + * flag will only take effect if the client is GSP-vGPU plugin. It is + * needed so that guest can update page tables in physical mode and do + * scrubbing. + */ +#define NVOS04_FLAGS_PRIVILEGED_CHANNEL 5:5 +#define NVOS04_FLAGS_PRIVILEGED_CHANNEL_FALSE 0x00000000 +#define NVOS04_FLAGS_PRIVILEGED_CHANNEL_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING: + * This flags tells RM not to schedule a newly created channel within a + * channel group immediately even if channel group is currently scheduled. + * Channel will not be scheduled until NVA06F_CTRL_GPFIFO_SCHEDULE is + * invoked. This is used eg. for CUDA which needs to do additional + * initialization before starting up a channel. + * Default is FALSE. + */ +#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING 6:6 +#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_FALSE 0x00000000 +#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_DENY_PHYSICAL_MODE_CE: + * This flag specifies whether or not to deny access to the physical + * mode of CopyEngine regardless of whether or not the client handle + * is admin. If set to true, this channel allocation will always result + * in an unprivileged channel. If set to false, the privilege of the channel + * will depend on the privilege level of the client handle. + * This is primarily meant for vGPU since all client handles + * granted to guests are admin. + */ +#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE 7:7 +#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_CHANNEL_USERD_INDEX_VALUE + * + * This flag specifies the channel offset in terms of within a page of + * USERD. For example, value 3 means the 4th channel within a USERD page. + * Given the USERD size is 512B, we will have 8 channels total, so 3 bits + * are reserved. + * + * When _USERD_INDEX_FIXED_TRUE is set but INDEX_PAGE_FIXED_FALSE is set, + * it will ask for a new USERD page. + * + */ +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_VALUE 10:8 + +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED 11:11 +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_VALUE + * + * This flag specifies the channel offset in terms of USERD page. When + * this PAGE_FIXED_TRUE is set, the INDEX_FIXED_FALSE bit should also + * be set, otherwise INVALID_STATE will be returned. + * + * And the field _USERD_INDEX_VALUE will be used to request the specific + * offset within a USERD page. + */ + +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_VALUE 20:12 + +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED 21:21 +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_DENY_AUTH_LEVEL_PRIV + * This flag specifies whether or not to deny access to the privileged + * host methods TLB_INVALIDATE and ACCESS_COUNTER_CLR + */ +#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV 22:22 +#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER + * + * This flag specifies scrubbing should be skipped for any internal + * allocations made for this channel from PMA using ctx buf pools. + * Only kernel clients are allowed to use this setting. + */ +#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER 23:23 +#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO + * + * This flag specifies that the client is expected to map USERD themselves + * and RM need not do so. + */ +#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO 24:24 +#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL + */ +#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL 25:25 +#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_FALSE 0x00000000 +#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT + * + * This flag specifies whether the channel calling context is from CPU + * VGPU plugin. + */ +#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT 26:26 +#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_TRUE 0x00000001 + + /* + * NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT + * + * This flag specifies the channel PBDMA ACQUIRE timeout option. + * _FALSE to disable it, _TRUE to enable it. + * When this flag is enabled, if a host semaphore acquire does not + * complete in about 2 sec, it will time out and trigger a RC error. + */ +#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT 27:27 +#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_GROUP_CHANNEL_THREAD: + * This flags specifies the thread id in which an allocated channel + * will be executed in a TSG. The relationship between the thread id + * in A TSG and respective definitions are implementation specific. + * Also, not all classes will be supported at thread > 0. + * This field cannot be used on non-TSG channels and must be set to + * the default value (0) in that case. If thread > 0 on a non-TSG + * channel, the allocation will fail + */ +#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD 29:28 +#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_DEFAULT 0x00000000 +#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_ONE 0x00000001 +#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_TWO 0x00000002 + +#define NVOS04_FLAGS_MAP_CHANNEL 30:30 +#define NVOS04_FLAGS_MAP_CHANNEL_FALSE 0x00000000 +#define NVOS04_FLAGS_MAP_CHANNEL_TRUE 0x00000001 + +#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC 31:31 +#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_FALSE 0x00000000 +#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_TRUE 0x00000001 + + + + +#define NV_CHANNEL_ALLOC_PARAMS_MESSAGE_ID (0x906fU) + +typedef struct NV_CHANNEL_ALLOC_PARAMS { + + NvHandle hObjectError; // error context DMA + NvHandle hObjectBuffer; // no longer used + NV_DECLARE_ALIGNED(NvU64 gpFifoOffset, 8); // offset to beginning of GP FIFO + NvU32 gpFifoEntries; // number of GP FIFO entries + + NvU32 flags; + + + NvHandle hContextShare; // context share handle + NvHandle hVASpace; // VASpace for the channel + + // handle to UserD memory object for channel, ignored if hUserdMemory[0]=0 + NvHandle hUserdMemory[NV_MAX_SUBDEVICES]; + + // offset to beginning of UserD within hUserdMemory[x] + NV_DECLARE_ALIGNED(NvU64 userdOffset[NV_MAX_SUBDEVICES], 8); + + // engine type(NV2080_ENGINE_TYPE_*) with which this channel is associated + NvU32 engineType; + // Channel identifier that is unique for the duration of a RM session + NvU32 cid; + // One-hot encoded bitmask to match SET_SUBDEVICE_MASK methods + NvU32 subDeviceId; + NvHandle hObjectEccError; // ECC error context DMA + + + + NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS instanceMem, 8); + NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS userdMem, 8); + NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS ramfcMem, 8); + NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS mthdbufMem, 8); + + NvHandle hPhysChannelGroup; // reserved + NvU32 internalFlags; // reserved + NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS errorNotifierMem, 8); // reserved + NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS eccErrorNotifierMem, 8); // reserved + NvU32 ProcessID; // reserved + NvU32 SubProcessID; // reserved +} NV_CHANNEL_ALLOC_PARAMS; + +typedef NV_CHANNEL_ALLOC_PARAMS NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl0000.h b/userspace/sdks/nv525/nvidia/inc/class/cl0000.h new file mode 100644 index 0000000..e7fefba --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl0000.h @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0000.finn +// + +#include "nvlimits.h" +#include "cl0000_notification.h" + +/* object NV01_NULL_OBJECT */ +#define NV01_NULL_OBJECT (0x0) /* finn: Evaluated from "NV0000_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* obsolete alises */ +#define NV1_NULL_OBJECT NV01_NULL_OBJECT + +#define NV01_ROOT (0x0U) /* finn: Evaluated from "NV0000_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* NvAlloc parameteters */ +#define NV0000_ALLOC_PARAMETERS_MESSAGE_ID (0x0000U) + +typedef struct NV0000_ALLOC_PARAMETERS { + NvHandle hClient; /* CORERM-2934: hClient must remain the first member until all allocations use these params */ + NvU32 processID; + char processName[NV_PROC_NAME_MAX_LENGTH]; +} NV0000_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl0000_notification.h b/userspace/sdks/nv525/nvidia/inc/class/cl0000_notification.h new file mode 100644 index 0000000..79b51d9 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl0000_notification.h @@ -0,0 +1,68 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0000_notification_h_ +#define _cl0000_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/*event values*/ +#define NV0000_NOTIFIERS_DISPLAY_CHANGE (0) +#define NV0000_NOTIFIERS_EVENT_NONE_PENDING (1) +#define NV0000_NOTIFIERS_VM_START (2) +#define NV0000_NOTIFIERS_GPU_BIND_EVENT (3) +#define NV0000_NOTIFIERS_NVTELEMETRY_REPORT_EVENT (4) +#define NV0000_NOTIFIERS_MAXCOUNT (5) + +/*Status definitions for NV0000_NOTIFIERS_DISPLAY_CHANGE event*/ + +#define NV0000_NOTIFIERS_STATUS_ACPI_DISPLAY_DEVICE_CYCLE (0) + +//--------------------------------------------------------------------------- + +/* NvNotification[] fields and values */ +#define NV000_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + + +/* pio method data structure */ +typedef volatile struct _cl0000_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv000Typedef, Nv01Root; + +/* obsolete aliases */ +#define NV000_TYPEDEF Nv01Root +#define Nv1Root Nv01Root +#define nv1Root Nv01Root +#define nv01Root Nv01Root + +/*event values*/ +#define NV0000_NOTIFIERS_ENABLE_CPU_UTIL_CTRL (1) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0000_notification_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl0001.h b/userspace/sdks/nv525/nvidia/inc/class/cl0001.h new file mode 100644 index 0000000..10a8af4 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl0001.h @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2013 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0001_h_ +#define _cl0001_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV01_ROOT_NON_PRIV (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0001_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl0002.h b/userspace/sdks/nv525/nvidia/inc/class/cl0002.h new file mode 100644 index 0000000..dd1d6c6 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl0002.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2001-2001, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0002_h_ +#define _cl0002_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV01_CONTEXT_DMA_FROM_MEMORY (0x00000002) +/* NvNotification[] fields and values */ +#define NV002_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +typedef volatile struct _cl0002_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv002Typedef, Nv01ContextDmaFromMemory; +#define NV002_TYPEDEF Nv01ContextDmaFromMemory +/* obsolete stuff */ +#define NV1_CONTEXT_DMA_FROM_MEMORY (0x00000002) +#define NV01_CONTEXT_DMA (0x00000002) +#define Nv1ContextDmaFromMemory Nv01ContextDmaFromMemory +#define nv1ContextDmaFromMemory Nv01ContextDmaFromMemory +#define nv01ContextDmaFromMemory Nv01ContextDmaFromMemory + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0002_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl0004.h b/userspace/sdks/nv525/nvidia/inc/class/cl0004.h new file mode 100644 index 0000000..32e25e7 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl0004.h @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0004_h_ +#define _cl0004_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV01_TIMER (0x00000004) +/* NvNotification[] elements */ +#define NV004_NOTIFIERS_SET_ALARM_NOTIFY (0) +#define NV004_NOTIFIERS_MAXCOUNT (1) + +/* mapped timer registers */ +typedef volatile struct _Nv01TimerMapTypedef { + NvU32 Reserved00[0x100]; + NvU32 PTimerTime0; /* 0x00009400 */ + NvU32 Reserved01[0x3]; + NvU32 PTimerTime1; /* 0x00009410 */ +} Nv01TimerMap; + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0004_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl0005.h b/userspace/sdks/nv525/nvidia/inc/class/cl0005.h new file mode 100644 index 0000000..2d04c34 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl0005.h @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0005.finn +// + +#include "cl0005_notification.h" + +#define NV01_EVENT (0x5U) /* finn: Evaluated from "NV0005_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* NvRmAlloc() parameters */ +#define NV0005_ALLOC_PARAMETERS_MESSAGE_ID (0x0005U) + +typedef struct NV0005_ALLOC_PARAMETERS { + NvHandle hParentClient; + NvHandle hSrcResource; + + NvV32 hClass; + NvV32 notifyIndex; + NV_DECLARE_ALIGNED(NvP64 data, 8); +} NV0005_ALLOC_PARAMETERS; + + +/* NV0005_ALLOC_PARAMETERS's notifyIndex field is overloaded to contain the + * notifyIndex value itself, plus flags, and optionally a subdevice field if + * flags contains NV01_EVENT_SUBDEVICE_SPECIFIC. Note that NV01_EVENT_* + * contain the full 32-bit flag value that is OR'd into notifyIndex, not the + * contents of the FLAGS field (i.e. NV01_EVENT_* are pre-shifted into place). + */ +#define NV0005_NOTIFY_INDEX_INDEX 15:0 +#define NV0005_NOTIFY_INDEX_SUBDEVICE 23:16 +#define NV0005_NOTIFY_INDEX_FLAGS 31:24 diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl0005_notification.h b/userspace/sdks/nv525/nvidia/inc/class/cl0005_notification.h new file mode 100644 index 0000000..5e6b32e --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl0005_notification.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0005_notification_h_ +#define _cl0005_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* NvNotification[] fields and values */ +#define NV003_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +/* pio method data structure */ +typedef volatile struct _cl0005_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv005Typedef, Nv01Event; + +#define NV005_TYPEDEF Nv01Event + +/* obsolete stuff */ +#define NV1_TIMER (0x00000004) +#define Nv1Event Nv01Event +#define nv1Event Nv01Event +#define nv01Event Nv01Event + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0005_notification_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl000f.h b/userspace/sdks/nv525/nvidia/inc/class/cl000f.h new file mode 100644 index 0000000..7c0d96b --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl000f.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl000f.finn +// + +#define FABRIC_MANAGER_SESSION (0xfU) /* finn: Evaluated from "NV000F_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV000F_NOTIFIERS_FABRIC_EVENT (0) + +#define NV000F_FLAGS_CHANNEL_RECOVERY 0:0 +#define NV000F_FLAGS_CHANNEL_RECOVERY_ENABLED 0x0 +#define NV000F_FLAGS_CHANNEL_RECOVERY_DISABLED 0x1 + +#define NV000F_ALLOCATION_PARAMETERS_MESSAGE_ID (0x000fU) + +typedef struct NV000F_ALLOCATION_PARAMETERS { + // + // capDescriptor is a file descriptor for unix RM clients, but a void + // pointer for windows RM clients. + // + // capDescriptor is transparent to RM clients i.e. RM's user-mode shim + // populates this field on behalf of clients. + // + NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8); + + NvU32 flags; +} NV000F_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl0020.h b/userspace/sdks/nv525/nvidia/inc/class/cl0020.h new file mode 100644 index 0000000..87154a9 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl0020.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0020_h_ +#define _cl0020_h_ + +#include "nvtypes.h" + +#define NV0020_GPU_MANAGEMENT (0x00000020) + +#endif /* _cl0020_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl0030.h b/userspace/sdks/nv525/nvidia/inc/class/cl0030.h new file mode 100644 index 0000000..9a0000e --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl0030.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0030_h_ +#define _cl0030_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV01_NULL (0x00000030) +/* NvNotification[] fields and values */ +#define NV030_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +typedef volatile struct _cl0030_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv030Typedef, Nv01Null; +#define NV030_TYPEDEF Nv01Null +/* obsolete stuff */ +#define NV1_NULL (0x00000030) +#define Nv1Null Nv01Null +#define nv1Null Nv01Null +#define nv01Null Nv01Null + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0030_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl003e.h b/userspace/sdks/nv525/nvidia/inc/class/cl003e.h new file mode 100644 index 0000000..d23e642 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl003e.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2001-2001, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl003e_h_ +#define _cl003e_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV01_CONTEXT_ERROR_TO_MEMORY (0x0000003E) +#define NV01_MEMORY_SYSTEM (0x0000003E) +/* NvNotification[] fields and values */ +#define NV03E_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +typedef volatile struct _cl003e_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv03eTypedef, Nv01ContextErrorToMemory; +#define NV03E_TYPEDEF Nv01ContextErrorToMemory +/* obsolete stuff */ +#define NV1_CONTEXT_ERROR_TO_MEMORY (0x0000003E) +#define Nv1ContextErrorToMemory Nv01ContextErrorToMemory +#define nv1ContextErrorToMemory Nv01ContextErrorToMemory +#define nv01ContextErrorToMemory Nv01ContextErrorToMemory + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl003e_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl003f.h b/userspace/sdks/nv525/nvidia/inc/class/cl003f.h new file mode 100644 index 0000000..b124538 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl003f.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2001-2001, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl003f_h_ +#define _cl003f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV01_MEMORY_LOCAL_PRIVILEGED (0x0000003F) +/* NvNotification[] fields and values */ +#define NV03F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +#ifndef AMD64 +typedef volatile struct _cl003f_tag0 { +#else +typedef struct { +#endif + NvV32 Reserved00[0x7c0]; +} Nv01MemoryLocalPrivileged; +#define NV03F_TYPEDEF Nv01MemoryLocalPrivileged +typedef Nv01MemoryLocalPrivileged Nv03fTypedef; +/* obsolete stuff */ +#define NV01_MEMORY_PRIVILEGED (0x0000003F) +#define NV1_MEMORY_PRIVILEGED (0x0000003F) +#define Nv01MemoryPrivileged Nv01MemoryLocalPrivileged +#define nv01MemoryPrivileged Nv01MemoryLocalPrivileged +#define Nv1MemoryPrivileged Nv01MemoryLocalPrivileged +#define nv1MemoryPrivileged Nv01MemoryLocalPrivileged +#define nv01MemoryLocalPrivileged Nv01MemoryLocalPrivileged + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl003f_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl0040.h b/userspace/sdks/nv525/nvidia/inc/class/cl0040.h new file mode 100644 index 0000000..103ec3a --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl0040.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2001 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl0040_h_ +#define _cl0040_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV01_MEMORY_LOCAL_USER (0x00000040) +/* NvNotification[] fields and values */ +#define NV040_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +typedef volatile struct _cl0040_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv040Typedef, Nv01MemoryLocalUser; +#define NV040_TYPEDEF Nv01MemoryLocalUser +/* obsolete stuff */ +#define NV01_MEMORY_USER (0x00000040) +#define NV1_MEMORY_USER (0x00000040) +#define Nv01MemoryUser Nv01MemoryLocalUser +#define nv01MemoryUser Nv01MemoryLocalUser +#define Nv1MemoryUser Nv01MemoryLocalUser +#define nv1MemoryUser Nv01MemoryLocalUser +#define nv01MemoryLocalUser Nv01MemoryLocalUser + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0040_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl0041.h b/userspace/sdks/nv525/nvidia/inc/class/cl0041.h new file mode 100644 index 0000000..fa8707a --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl0041.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2001-2005, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0041_h_ +#define _cl0041_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV04_MEMORY (0x00000041) +/* NvNotification[] fields and values */ +#define NV041_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +typedef volatile struct _cl0041_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv041Typedef, Nv04Memory; +#define NV041_TYPEDEF Nv04Memory; + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0041_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl0060.h b/userspace/sdks/nv525/nvidia/inc/class/cl0060.h new file mode 100644 index 0000000..80e3778 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl0060.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0060.finn +// + +#define NV0060_SYNC_GPU_BOOST (0x60U) /* finn: Evaluated from "NV0060_ALLOC_PARAMETERS_MESSAGE_ID" */ + +#define NV0060_ALLOC_PARAMETERS_MESSAGE_ID (0x0060U) + +typedef struct NV0060_ALLOC_PARAMETERS { + NvU32 gpuBoostGroupId; +} NV0060_ALLOC_PARAMETERS; diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl0070.h b/userspace/sdks/nv525/nvidia/inc/class/cl0070.h new file mode 100644 index 0000000..c2a8f4b --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl0070.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2001-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0070.finn +// + +#define NV01_MEMORY_VIRTUAL (0x70U) /* finn: Evaluated from "NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_MESSAGE_ID" */ +#define NV01_MEMORY_SYSTEM_DYNAMIC (0x70U) /* finn: Evaluated from "NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_MESSAGE_ID" */ + +/* + * NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS + * + * Allocation params for NV01_MEMORY_VIRTUAL. + * + * NV01_MEMORY_SYSTEM_DYNAMIC is an alias for NV01_MEMORY_VIRTUAL. This + * was traditionally allocated with RmAllocMemory64(). The default GPU + * virtual address space is used, and the limit of this address space is + * returned in limit. The NV01_MEMORY_SYSTEM_DYNAMIC handle can be + * passed to RmAllocContextDma2() with an offset/limit. The context dma + * handle can then be used as the hDma handle for RmMapMemoryDma. + * + * This behavior is maintained in the RM compatibility shim. + * + * NV01_MEMORY_VIRTUAL replaces this behavior with a single object. + * + * hVASpace - if hVASpace is NV01_NULL_OBJECT the default GPU VA space is + * selected. Alternatively a FERMI_VASPACE_A handle may be specified. + * + * The NV_MEMORY_VIRTUAL_SYSMEM_DYNAMIC_HVASPACE is used for by the + * compatibility layer to emulate NV01_MEMORY_SYSTEM_DYNAMIC semantics. + * + * offset - An offset into the virtual address space may be specified. This + * will limit range of the GPU VA returned by RmMapMemoryDma to be + * above offset. + * + * limit - When limit is zero the maximum limit used. If a non-zero limit + * is specified then it will be used. The final limit is returned. + */ +#define NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_MESSAGE_ID (0x0070U) + +typedef struct NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offset, 8); // [IN] - offset into address space + NV_DECLARE_ALIGNED(NvU64 limit, 8); // [IN/OUT] - limit of address space + NvHandle hVASpace; // [IN] - Address space handle +} NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS; + +#define NV_MEMORY_VIRTUAL_SYSMEM_DYNAMIC_HVASPACE 0xffffffffU + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl0071.h b/userspace/sdks/nv525/nvidia/inc/class/cl0071.h new file mode 100644 index 0000000..be106d3 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl0071.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2001-2001, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0071_h_ +#define _cl0071_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV01_MEMORY_SYSTEM_OS_DESCRIPTOR (0x00000071) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0071_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl0073.h b/userspace/sdks/nv525/nvidia/inc/class/cl0073.h new file mode 100644 index 0000000..3775287 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl0073.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2001-2021, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0073_h_ +#define _cl0073_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV04_DISPLAY_COMMON (0x00000073) + +/* event values */ +#define NV0073_NOTIFIERS_SW (0) +#define NV0073_NOTIFIERS_MAXCOUNT (5) + + +#define NV0073_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NV0073_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000) +#define NV0073_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000) +#define NV0073_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000) +#define NV0073_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) + +/* pio method data structure */ +typedef volatile struct _cl0073_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv073Typedef, Nv04DisplayCommon; +#define NV073_TYPEDEF Nv04DisplayCommon + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0073_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl0076.h b/userspace/sdks/nv525/nvidia/inc/class/cl0076.h new file mode 100644 index 0000000..50bd0a9 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl0076.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0076_h_ +#define _cl0076_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV01_MEMORY_FRAMEBUFFER_CONSOLE (0x00000076) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0076_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl007d.h b/userspace/sdks/nv525/nvidia/inc/class/cl007d.h new file mode 100644 index 0000000..f9d25d9 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl007d.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl007d_h_ +#define _cl007d_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV04_SOFTWARE_TEST (0x0000007D) +#define NV07D 0x00001fff:0x00000000 +/* NvNotification[] elements */ +#define NV07D_NOTIFIERS_NOTIFY (0) +#define NV07D_NOTIFIERS_MAXCOUNT (1) +/* NvNotification[] fields and values */ +#define NV07D_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NV07D_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +#define NV07D_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NV07D_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x1000) +#define NV07D_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x0800) +#define NV07D_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) + +/* pio method data structures */ +typedef volatile struct _cl007d_tag0 { + NvV32 NoOperation; /* ignored 0100-0103*/ + NvV32 Notify; /* NV07D_NOTIFY_* 0104-0107*/ + NvV32 Reserved0104[0x78/4]; + NvV32 SetContextDmaNotifies; /* NV01_CONTEXT_DMA 0180-0183*/ + NvV32 Reserved0184[0x1f7c/4]; +} Nv07dTypedef, Nv04SoftwareTest; + +#define NV07D_TYPEDEF Nv04SoftwareTest +/* dma method offsets, fields, and values */ +#define NV07D_SET_OBJECT (0x00000000) +#define NV07D_NO_OPERATION (0x00000100) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl007d_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl0080.h b/userspace/sdks/nv525/nvidia/inc/class/cl0080.h new file mode 100644 index 0000000..7f4bd59 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl0080.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0080.finn +// + +#include "nvlimits.h" +#include "cl0080_notification.h" + +#define NV01_DEVICE_0 (0x80U) /* finn: Evaluated from "NV0080_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* NvAlloc parameteters */ +#define NV0080_MAX_DEVICES NV_MAX_DEVICES + +/** + * @brief Alloc param + * + * @param vaMode mode for virtual address space allocation + * Three modes: + * NV_DEVICE_ALLOCATION_VAMODE_OPTIONAL_MULTIPLE_VASPACES + * NV_DEVICE_ALLOCATION_VAMODE_SINGLE_VASPACE + * NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES + * Detailed description of these modes is in nvos.h + **/ + +#define NV0080_ALLOC_PARAMETERS_MESSAGE_ID (0x0080U) + +typedef struct NV0080_ALLOC_PARAMETERS { + NvU32 deviceId; + NvHandle hClientShare; + NvHandle hTargetClient; + NvHandle hTargetDevice; + NvV32 flags; + NV_DECLARE_ALIGNED(NvU64 vaSpaceSize, 8); + NV_DECLARE_ALIGNED(NvU64 vaStartInternal, 8); + NV_DECLARE_ALIGNED(NvU64 vaLimitInternal, 8); + NvV32 vaMode; +} NV0080_ALLOC_PARAMETERS; diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl0080_notification.h b/userspace/sdks/nv525/nvidia/inc/class/cl0080_notification.h new file mode 100644 index 0000000..a976d3f --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl0080_notification.h @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0080_notification_h_ +#define _cl0080_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* NvNotification[] fields and values */ +#define NV080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +/* pio method data structure */ +typedef volatile struct _cl0080_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv080Typedef, Nv01Device0; + +#define NV080_TYPEDEF Nv01Device0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0080_notification_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl0090.h b/userspace/sdks/nv525/nvidia/inc/class/cl0090.h new file mode 100644 index 0000000..1ed7835 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl0090.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl0090_h_ +#define _cl0090_h_ + +#include "nvtypes.h" + +#define KERNEL_GRAPHICS_CONTEXT (0x00000090) + +#endif /* _cl0090_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl0092.h b/userspace/sdks/nv525/nvidia/inc/class/cl0092.h new file mode 100644 index 0000000..327e0e4 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl0092.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0092.finn +// + +#include "class/cl0092_callback.h" + +/* + * This RgLineCallback class allows RM clients to register/unregister the RG line callback functions. + * + * Must be allocated with kernel access rights. + * + * Allocation params: + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the NV04_DISPLAY_COMMON parent device to which the + * operation should be directed. + * head + * This parameter specifies the head for which the callback is to be egistered/unregistered. This value must be + * less than the maximum number of heads supported by the GPU subdevice. + * rgLineNum + * This indicates the RG scanout line number on which the callback will be executed. + * 1/ Client should set the proper RG line number based on mode in which the display head is running and + * subsequent possible modeset that may affect the line number. + * 2/ Client is expected to clear/set the interrupts around modesets or power-transitions (like s3/hibernation). + * 3/ Client should make sure that this param does not exceed the raster settings. + * pCallbkFn + * Pointer to callback function. Cannot be NULL. + * pCallbkParams + * Pointer to the ctrl call param struct. + */ + +#define NV0092_RG_LINE_CALLBACK (0x92U) /* finn: Evaluated from "NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS_MESSAGE_ID (0x0092U) + +typedef struct NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS { + NvU32 subDeviceInstance; + NvU32 head; + NvU32 rgLineNum; + + NV_DECLARE_ALIGNED(NvP64 pCallbkFn, 8); /* A function pointer of NV0092_REGISTER_RG_LINE_CALLBACK_FN */ + + NV_DECLARE_ALIGNED(NvP64 pCallbkParams, 8); /* The param1 in NV0092_REGISTER_RG_LINE_CALLBACK_FN */ +} NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl0092_callback.h b/userspace/sdks/nv525/nvidia/inc/class/cl0092_callback.h new file mode 100644 index 0000000..4cd86ad --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl0092_callback.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef SDK_CL0092_CALLBACK_H +#define SDK_CL0092_CALLBACK_H + +typedef void (*NV0092_REGISTER_RG_LINE_CALLBACK_FN)(NvU32 rgIntrLine, NvP64 param1, NvBool bIsIrqlIsr); + +#endif // SDK_CL0092_CALLBACK_H diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl00b1.h b/userspace/sdks/nv525/nvidia/inc/class/cl00b1.h new file mode 100644 index 0000000..bc6e69f --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl00b1.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _CL00B1_H_ +#define _CL00B1_H_ + +#define NV01_MEMORY_HW_RESOURCES 0x00b1 + +#endif // _CL00B1_H_ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl00c1.h b/userspace/sdks/nv525/nvidia/inc/class/cl00c1.h new file mode 100644 index 0000000..73fea05 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl00c1.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00c1.finn +// + +#include "nvlimits.h" +#define NV_FB_SEGMENT (0xc1U) /* finn: Evaluated from "NV_FB_SEGMENT_ALLOCATION_PARAMS_MESSAGE_ID" */ + +/* + * NV_FB_SEGMENT_ALLOCATION_PARAMS - Allocation params to create FB segment through + * NvRmAlloc. + */ +#define NV_FB_SEGMENT_ALLOCATION_PARAMS_MESSAGE_ID (0x00C1U) + +typedef struct NV_FB_SEGMENT_ALLOCATION_PARAMS { + NvHandle hCtxDma; // unused + NvU32 subDeviceIDMask; + NV_DECLARE_ALIGNED(NvU64 dmaOffset, 8); // unused + NV_DECLARE_ALIGNED(NvU64 VidOffset, 8); + NV_DECLARE_ALIGNED(NvU64 Offset, 8); // To be deprecated + NV_DECLARE_ALIGNED(NvU64 pOffset[NV_MAX_SUBDEVICES], 8); + NV_DECLARE_ALIGNED(NvU64 Length, 8); + NV_DECLARE_ALIGNED(NvU64 ValidLength, 8); + NV_DECLARE_ALIGNED(NvP64 pPageArray, 8); + NvU32 startPageIndex; + NvHandle AllocHintHandle; + NvU32 Flags; + NvHandle hMemory; // Not used in NvRmAlloc path; only used in CTRL path + NvHandle hClient; // Not used in NvRmAlloc path; only used in CTRL path + NvHandle hDevice; // Not used in NvRmAlloc path; only used in CTRL path + NV_DECLARE_ALIGNED(NvP64 pCpuAddress, 8); // To be deprecated + NV_DECLARE_ALIGNED(NvP64 ppCpuAddress[NV_MAX_SUBDEVICES], 8); + NV_DECLARE_ALIGNED(NvU64 GpuAddress, 8); // To be deprecated + NV_DECLARE_ALIGNED(NvU64 pGpuAddress[NV_MAX_SUBDEVICES], 8); + NvHandle hAllocHintClient; + NvU32 kind; + NvU32 compTag; +} NV_FB_SEGMENT_ALLOCATION_PARAMS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl00c2.h b/userspace/sdks/nv525/nvidia/inc/class/cl00c2.h new file mode 100644 index 0000000..ef2d168 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl00c2.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00c2.finn +// + +#define NV01_MEMORY_LOCAL_PHYSICAL (0xc2U) /* finn: Evaluated from "NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID" */ + +#define NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID (0x00c2U) + +typedef struct NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS { + NV_DECLARE_ALIGNED(NvU64 memSize, 8); // [OUT] + NvU32 format; // [IN] - PTE format to use + NvU32 pageSize; // [IN] - Page size to use +} NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl00c3.h b/userspace/sdks/nv525/nvidia/inc/class/cl00c3.h new file mode 100644 index 0000000..298e582 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl00c3.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00c3.finn +// + +#define NV01_MEMORY_SYNCPOINT (0xc3U) /* finn: Evaluated from "NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS_MESSAGE_ID" */ + +/* + * NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS - Allocation params to create syncpoint + * through NvRmAlloc. + */ +#define NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS_MESSAGE_ID (0x00c3U) + +typedef struct NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS { + NvU32 syncpointId; +} NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl00db.h b/userspace/sdks/nv525/nvidia/inc/class/cl00db.h new file mode 100644 index 0000000..91791bd --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl00db.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00db.finn +// + +#define NV40_DEBUG_BUFFER (0xdbU) /* finn: Evaluated from "NV00DB_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* NvRmAlloc() parameters */ +#define NV00DB_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00dbU) + +typedef struct NV00DB_ALLOCATION_PARAMETERS { + NvU32 size; /* Desired message size / actual size returned */ + NvU32 tag; /* Protobuf tag for message location in dump message */ +} NV00DB_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl00de.h b/userspace/sdks/nv525/nvidia/inc/class/cl00de.h new file mode 100644 index 0000000..8c772ef --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl00de.h @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl00de_h_ +#define _cl00de_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define RM_USER_SHARED_DATA (0x000000de) + +typedef struct NV00DE_SHARED_DATA { + volatile NvU32 seq; + + NvU32 bar1Size; + NvU32 bar1AvailSize; + // New data members always add to bottom +} NV00DE_SHARED_DATA; + +typedef struct NV00DE_ALLOC_PARAMETERS { + // initialize to 0 + NvU32 reserved; +} NV00DE_ALLOC_PARAMETERS; + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl00de_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl00f2.h b/userspace/sdks/nv525/nvidia/inc/class/cl00f2.h new file mode 100644 index 0000000..13b0624 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl00f2.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _cl00f2_h_ +#define _cl00f2_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define IO_VASPACE_A (0x000000f2) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl00f2_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl00f3.h b/userspace/sdks/nv525/nvidia/inc/class/cl00f3.h new file mode 100644 index 0000000..09647c3 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl00f3.h @@ -0,0 +1,75 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00f3.finn +// + + + +/* + * Class definition for creating a memory descriptor from a FLA range in RmAllocMemory. + * No memory is allocated, only a memory descriptor and memory object is created + * for later use in other calls. These classes are used by clients who tries to + * import the memory exported by other GPU(s)/FAM/process. The range, size and + * other parameters are passed as Nv01MemoryFla structure. + */ + +#define NV01_MEMORY_FLA (0xf3U) /* finn: Evaluated from "NV_FLA_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID" */ + +/* + * Structure of NV_FLA_MEMORY_ALLOCATION_PARAMS + * + * + */ +#define NV_FLA_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID (0x00f3U) + +typedef struct NV_FLA_MEMORY_ALLOCATION_PARAMS { + NvU32 type; /* FBMEM: NVOS32_TYPE_* */ + NvU32 flags; /* FBMEM: NVOS32_ALLOC_FLAGS_* */ + NvU32 attr; /* FBMEM: NVOS32_ATTR_* */ + NvU32 attr2; /* FBMEM: NVOS32_ATTR2_* */ + NV_DECLARE_ALIGNED(NvU64 base, 8); /* base of FLA range */ + NV_DECLARE_ALIGNED(NvU64 align, 8); /* alignment for FLA range*/ + NV_DECLARE_ALIGNED(NvU64 limit, 8); + // + // For Direct connected systems, clients need to program this hSubDevice with + // the exporting GPU, for RM to route the traffic to the destination GPU + // Clients need not program this for NvSwitch connected systems + // + NvHandle hExportSubdevice; /* hSubdevice of the exporting GPU */ + // + // Instead of base and limit, clients can also pass the FLA handle (or hExportHandle) + // being exported from destination side to import on the access side + // + NvHandle hExportHandle; /* FLA handle being exported or Export handle */ + // The RM client used to export memory + NvHandle hExportClient; + NvU32 flagsOs02; +} NV_FLA_MEMORY_ALLOCATION_PARAMS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl00f8.h b/userspace/sdks/nv525/nvidia/inc/class/cl00f8.h new file mode 100644 index 0000000..096c46c --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl00f8.h @@ -0,0 +1,119 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00f8.finn +// + + + +/* + * Class definition for allocating a contiguous or discontiguous FLA. + */ + +#define NV_MEMORY_FABRIC (0xf8U) /* finn: Evaluated from "NV00F8_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* + * alignment [IN] + * Alignment for the allocation. + * Should be at least the requested page size. + * + * allocSize [IN] + * Size of the FLA VA. + * + * pageSize [IN] + * Requested page size. Can be any of the NV_MEMORY_FABRIC_PAGE_SIZE_* + * + * allocFlags [IN] + * Can be any of the NV00F8_ALLOC_FLAGS_* + * DEFAULT (sticky) + * The FLA -> PA mappings will be stuck to the object, i.e, once the mapping is created + * there is no way to unmap it explicitly. + * The FLA object must be destroyed to release the mappings. + * The FLA object can't be duped or exported until it has a mapping associated with it. + * Partial FLA->PA mappings will NOT be allowed. + * FLEXIBLE_FLA + * The FLA -> PA mappings can be modified anytime irrespective of the FLA object is duped + * or exported. + * Partial FLA mappings are allowed. + * FORCE_NONCONTIGUOUS + * The allocator may pick contiguous memory whenever possible. This flag forces the + * allocator to always allocate noncontiguous memory. This flag is mainly used for + * testing purpose. So, use with caution. + * FORCE_CONTIGUOUS + * This flag forces the allocator to always allocate contiguous memory. + * READ_ONLY + * The FLA -> PA mappings will be created read-only. This option is only available on + * debug/develop builds due to security concerns. The security concerns are due to the + * fact that FLA access errors (a.k.a PRIV errors) are not aways context attributable. + * + * map.offset [IN] + * Offset into the physical memory descriptor. + * Must be physical memory page size aligned. + * + * map.hVidMem [IN] + * - Handle to the physical memory. + * - Must be passed so that the FLA -> GPA mapping can happen during object creation. + * - For sticky allocations, physical memory being mapped should be large enough + * (accounting map.offset) to cover the whole fabric object allocation size. + * - For flexible allocations, physical memory handle should be zero. + * - Phys memory with 2MB and 512MB pages is supported. + * - hVidMem should belong the same device and client which is allocating FLA. + * + * map.flags [IN] + * Reserved for future use. + * Clients should pass 0 as of now. + */ + +#define NV_MEMORY_FABRIC_PAGE_SIZE_2M 0x200000 +#define NV_MEMORY_FABRIC_PAGE_SIZE_512M 0x20000000 + +#define NV00F8_ALLOC_FLAGS_DEFAULT 0 +#define NV00F8_ALLOC_FLAGS_FLEXIBLE_FLA NVBIT(0) +#define NV00F8_ALLOC_FLAGS_FORCE_NONCONTIGUOUS NVBIT(1) +#define NV00F8_ALLOC_FLAGS_FORCE_CONTIGUOUS NVBIT(2) +#define NV00F8_ALLOC_FLAGS_READ_ONLY NVBIT(3) + +#define NV00F8_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00f8U) + +typedef struct NV00F8_ALLOCATION_PARAMETERS { + + NV_DECLARE_ALIGNED(NvU64 alignment, 8); + NV_DECLARE_ALIGNED(NvU64 allocSize, 8); + + NvU32 pageSize; + NvU32 allocFlags; + + struct { + NV_DECLARE_ALIGNED(NvU64 offset, 8); + + NvHandle hVidMem; + NvU32 flags; + } map; +} NV00F8_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl00fc.h b/userspace/sdks/nv525/nvidia/inc/class/cl00fc.h new file mode 100644 index 0000000..aa50ead --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl00fc.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _cl00fc_h_ +#define _cl00fc_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define FABRIC_VASPACE_A (0x000000fc) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl00fc_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl00fd.h b/userspace/sdks/nv525/nvidia/inc/class/cl00fd.h new file mode 100644 index 0000000..5e80d46 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl00fd.h @@ -0,0 +1,73 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * Class definition for allocating a contiguous or discontiguous Multicast FLA. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00fd.finn +// + +#define NV_MEMORY_MULTICAST_FABRIC (0xfdU) /* finn: Evaluated from "NV00FD_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* + * alignment [IN] + * Alignment for the allocation. + * Should be at least the requested page size. + * + * allocSize [IN] + * Size of the Multicast FLA VA. + * + * pageSize [IN] + * Requested page size. Can be any of the NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_* + * + * allocFlags [IN] + * Reserved for future use + * Clients should pass 0 as of now. + * + * numGpus [IN] + * Number of unique GPUs to be attached. + * + * pOsEvent [IN] + * Optional OS event handle created with NvRmAllocOsEvent(). + */ + +#define NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_512M 0x20000000 + +#define NV00FD_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00fdU) + +typedef struct NV00FD_ALLOCATION_PARAMETERS { + NV_DECLARE_ALIGNED(NvU64 alignment, 8); + NV_DECLARE_ALIGNED(NvU64 allocSize, 8); + NvU32 pageSize; + NvU32 allocFlags; + NvU32 numGpus; + NV_DECLARE_ALIGNED(NvP64 pOsEvent, 8); +} NV00FD_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl00fe.h b/userspace/sdks/nv525/nvidia/inc/class/cl00fe.h new file mode 100644 index 0000000..464c1ec --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl00fe.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00fe.finn +// + +#define NV_MEMORY_MAPPER (0xfeU) /* finn: Evaluated from "NV_MEMORY_MAPPER_ALLOCATION_PARAMS_MESSAGE_ID" */ + +/* + * NV_MEMORY_MAPPER_ALLOCATION_PARAMS + * + * Allocation params for NV_MEMORY_MAPPER. + * This class provides paging operations channel interface to userspace clients. + */ +#define NV_MEMORY_MAPPER_ALLOCATION_PARAMS_MESSAGE_ID (0x00FEU) + +typedef struct NV_MEMORY_MAPPER_ALLOCATION_PARAMS { + NvBool unused; +} NV_MEMORY_MAPPER_ALLOCATION_PARAMS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl2080.h b/userspace/sdks/nv525/nvidia/inc/class/cl2080.h new file mode 100644 index 0000000..32b616f --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl2080.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2002-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl2080.finn +// + +#include "nvlimits.h" +#include "cl2080_notification.h" + +#define NV20_SUBDEVICE_0 (0x2080U) /* finn: Evaluated from "NV2080_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* NvAlloc parameteters */ +#define NV2080_MAX_SUBDEVICES NV_MAX_SUBDEVICES + +#define NV2080_ALLOC_PARAMETERS_MESSAGE_ID (0x2080U) + +typedef struct NV2080_ALLOC_PARAMETERS { + NvU32 subDeviceId; +} NV2080_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl2080_notification.h b/userspace/sdks/nv525/nvidia/inc/class/cl2080_notification.h new file mode 100644 index 0000000..1879905 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl2080_notification.h @@ -0,0 +1,497 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl2080_notification_h_ +#define _cl2080_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* event values */ +#define NV2080_NOTIFIERS_SW (0) +#define NV2080_NOTIFIERS_HOTPLUG (1) +#define NV2080_NOTIFIERS_POWER_CONNECTOR (2) +#define NV2080_NOTIFIERS_THERMAL_SW (3) +#define NV2080_NOTIFIERS_THERMAL_HW (4) +#define NV2080_NOTIFIERS_FULL_SCREEN_CHANGE (5) +#define NV2080_NOTIFIERS_EVENTBUFFER (6) +#define NV2080_NOTIFIERS_DP_IRQ (7) +#define NV2080_NOTIFIERS_GR_DEBUG_INTR (8) +#define NV2080_NOTIFIERS_PMU_EVENT (9) +#define NV2080_NOTIFIERS_PMU_COMMAND (10) +#define NV2080_NOTIFIERS_TIMER (11) +#define NV2080_NOTIFIERS_GRAPHICS (12) +#define NV2080_NOTIFIERS_PPP (13) +#define NV2080_NOTIFIERS_VLD (14) // also known as BSP +#define NV2080_NOTIFIERS_NVDEC0 NV2080_NOTIFIERS_VLD +#define NV2080_NOTIFIERS_NVDEC1 (15) +#define NV2080_NOTIFIERS_NVDEC2 (16) +#define NV2080_NOTIFIERS_NVDEC3 (17) +#define NV2080_NOTIFIERS_NVDEC4 (18) +#define NV2080_NOTIFIERS_NVDEC5 (19) +#define NV2080_NOTIFIERS_NVDEC6 (20) +#define NV2080_NOTIFIERS_NVDEC7 (21) +#define NV2080_NOTIFIERS_PDEC (22) // also known as VP +#define NV2080_NOTIFIERS_CE0 (23) +#define NV2080_NOTIFIERS_CE1 (24) +#define NV2080_NOTIFIERS_CE2 (25) +#define NV2080_NOTIFIERS_CE3 (26) +#define NV2080_NOTIFIERS_CE4 (27) +#define NV2080_NOTIFIERS_CE5 (28) +#define NV2080_NOTIFIERS_CE6 (29) +#define NV2080_NOTIFIERS_CE7 (30) +#define NV2080_NOTIFIERS_CE8 (31) +#define NV2080_NOTIFIERS_CE9 (32) +#define NV2080_NOTIFIERS_PSTATE_CHANGE (33) +#define NV2080_NOTIFIERS_HDCP_STATUS_CHANGE (34) +#define NV2080_NOTIFIERS_FIFO_EVENT_MTHD (35) +#define NV2080_NOTIFIERS_PRIV_RING_HANG (36) +#define NV2080_NOTIFIERS_RC_ERROR (37) +#define NV2080_NOTIFIERS_MSENC (38) +#define NV2080_NOTIFIERS_NVENC0 NV2080_NOTIFIERS_MSENC +#define NV2080_NOTIFIERS_NVENC1 (39) +#define NV2080_NOTIFIERS_NVENC2 (40) +#define NV2080_NOTIFIERS_UNUSED_0 (41) // Unused +#define NV2080_NOTIFIERS_ACPI_NOTIFY (42) +#define NV2080_NOTIFIERS_COOLER_DIAG_ZONE (43) +#define NV2080_NOTIFIERS_THERMAL_DIAG_ZONE (44) +#define NV2080_NOTIFIERS_AUDIO_HDCP_REQUEST (45) +#define NV2080_NOTIFIERS_WORKLOAD_MODULATION_CHANGE (46) +#define NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT (47) +#define NV2080_NOTIFIERS_GPIO_1_RISING_INTERRUPT (48) +#define NV2080_NOTIFIERS_GPIO_2_RISING_INTERRUPT (49) +#define NV2080_NOTIFIERS_GPIO_3_RISING_INTERRUPT (50) +#define NV2080_NOTIFIERS_GPIO_4_RISING_INTERRUPT (51) +#define NV2080_NOTIFIERS_GPIO_5_RISING_INTERRUPT (52) +#define NV2080_NOTIFIERS_GPIO_6_RISING_INTERRUPT (53) +#define NV2080_NOTIFIERS_GPIO_7_RISING_INTERRUPT (54) +#define NV2080_NOTIFIERS_GPIO_8_RISING_INTERRUPT (55) +#define NV2080_NOTIFIERS_GPIO_9_RISING_INTERRUPT (56) +#define NV2080_NOTIFIERS_GPIO_10_RISING_INTERRUPT (57) +#define NV2080_NOTIFIERS_GPIO_11_RISING_INTERRUPT (58) +#define NV2080_NOTIFIERS_GPIO_12_RISING_INTERRUPT (59) +#define NV2080_NOTIFIERS_GPIO_13_RISING_INTERRUPT (60) +#define NV2080_NOTIFIERS_GPIO_14_RISING_INTERRUPT (61) +#define NV2080_NOTIFIERS_GPIO_15_RISING_INTERRUPT (62) +#define NV2080_NOTIFIERS_GPIO_16_RISING_INTERRUPT (63) +#define NV2080_NOTIFIERS_GPIO_17_RISING_INTERRUPT (64) +#define NV2080_NOTIFIERS_GPIO_18_RISING_INTERRUPT (65) +#define NV2080_NOTIFIERS_GPIO_19_RISING_INTERRUPT (66) +#define NV2080_NOTIFIERS_GPIO_20_RISING_INTERRUPT (67) +#define NV2080_NOTIFIERS_GPIO_21_RISING_INTERRUPT (68) +#define NV2080_NOTIFIERS_GPIO_22_RISING_INTERRUPT (69) +#define NV2080_NOTIFIERS_GPIO_23_RISING_INTERRUPT (70) +#define NV2080_NOTIFIERS_GPIO_24_RISING_INTERRUPT (71) +#define NV2080_NOTIFIERS_GPIO_25_RISING_INTERRUPT (72) +#define NV2080_NOTIFIERS_GPIO_26_RISING_INTERRUPT (73) +#define NV2080_NOTIFIERS_GPIO_27_RISING_INTERRUPT (74) +#define NV2080_NOTIFIERS_GPIO_28_RISING_INTERRUPT (75) +#define NV2080_NOTIFIERS_GPIO_29_RISING_INTERRUPT (76) +#define NV2080_NOTIFIERS_GPIO_30_RISING_INTERRUPT (77) +#define NV2080_NOTIFIERS_GPIO_31_RISING_INTERRUPT (78) +#define NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT (79) +#define NV2080_NOTIFIERS_GPIO_1_FALLING_INTERRUPT (80) +#define NV2080_NOTIFIERS_GPIO_2_FALLING_INTERRUPT (81) +#define NV2080_NOTIFIERS_GPIO_3_FALLING_INTERRUPT (82) +#define NV2080_NOTIFIERS_GPIO_4_FALLING_INTERRUPT (83) +#define NV2080_NOTIFIERS_GPIO_5_FALLING_INTERRUPT (84) +#define NV2080_NOTIFIERS_GPIO_6_FALLING_INTERRUPT (85) +#define NV2080_NOTIFIERS_GPIO_7_FALLING_INTERRUPT (86) +#define NV2080_NOTIFIERS_GPIO_8_FALLING_INTERRUPT (87) +#define NV2080_NOTIFIERS_GPIO_9_FALLING_INTERRUPT (88) +#define NV2080_NOTIFIERS_GPIO_10_FALLING_INTERRUPT (89) +#define NV2080_NOTIFIERS_GPIO_11_FALLING_INTERRUPT (90) +#define NV2080_NOTIFIERS_GPIO_12_FALLING_INTERRUPT (91) +#define NV2080_NOTIFIERS_GPIO_13_FALLING_INTERRUPT (92) +#define NV2080_NOTIFIERS_GPIO_14_FALLING_INTERRUPT (93) +#define NV2080_NOTIFIERS_GPIO_15_FALLING_INTERRUPT (94) +#define NV2080_NOTIFIERS_GPIO_16_FALLING_INTERRUPT (95) +#define NV2080_NOTIFIERS_GPIO_17_FALLING_INTERRUPT (96) +#define NV2080_NOTIFIERS_GPIO_18_FALLING_INTERRUPT (97) +#define NV2080_NOTIFIERS_GPIO_19_FALLING_INTERRUPT (98) +#define NV2080_NOTIFIERS_GPIO_20_FALLING_INTERRUPT (99) +#define NV2080_NOTIFIERS_GPIO_21_FALLING_INTERRUPT (100) +#define NV2080_NOTIFIERS_GPIO_22_FALLING_INTERRUPT (101) +#define NV2080_NOTIFIERS_GPIO_23_FALLING_INTERRUPT (102) +#define NV2080_NOTIFIERS_GPIO_24_FALLING_INTERRUPT (103) +#define NV2080_NOTIFIERS_GPIO_25_FALLING_INTERRUPT (104) +#define NV2080_NOTIFIERS_GPIO_26_FALLING_INTERRUPT (105) +#define NV2080_NOTIFIERS_GPIO_27_FALLING_INTERRUPT (106) +#define NV2080_NOTIFIERS_GPIO_28_FALLING_INTERRUPT (107) +#define NV2080_NOTIFIERS_GPIO_29_FALLING_INTERRUPT (108) +#define NV2080_NOTIFIERS_GPIO_30_FALLING_INTERRUPT (109) +#define NV2080_NOTIFIERS_GPIO_31_FALLING_INTERRUPT (110) +#define NV2080_NOTIFIERS_ECC_SBE (111) +#define NV2080_NOTIFIERS_ECC_DBE (112) +#define NV2080_NOTIFIERS_STEREO_EMITTER_DETECTION (113) +#define NV2080_NOTIFIERS_GC5_GPU_READY (114) +#define NV2080_NOTIFIERS_SEC2 (115) +#define NV2080_NOTIFIERS_GC6_REFCOUNT_INC (116) +#define NV2080_NOTIFIERS_GC6_REFCOUNT_DEC (117) +#define NV2080_NOTIFIERS_POWER_EVENT (118) +#define NV2080_NOTIFIERS_CLOCKS_CHANGE (119) +#define NV2080_NOTIFIERS_HOTPLUG_PROCESSING_COMPLETE (120) +#define NV2080_NOTIFIERS_PHYSICAL_PAGE_FAULT (121) +#define NV2080_NOTIFIERS_RESERVED122 (122) +#define NV2080_NOTIFIERS_NVLINK_ERROR_FATAL (123) +#define NV2080_NOTIFIERS_PRIV_REG_ACCESS_FAULT (124) +#define NV2080_NOTIFIERS_NVLINK_ERROR_RECOVERY_REQUIRED (125) +#define NV2080_NOTIFIERS_NVJPG (126) +#define NV2080_NOTIFIERS_NVJPEG0 NV2080_NOTIFIERS_NVJPG +#define NV2080_NOTIFIERS_NVJPEG1 (127) +#define NV2080_NOTIFIERS_NVJPEG2 (128) +#define NV2080_NOTIFIERS_NVJPEG3 (129) +#define NV2080_NOTIFIERS_NVJPEG4 (130) +#define NV2080_NOTIFIERS_NVJPEG5 (131) +#define NV2080_NOTIFIERS_NVJPEG6 (132) +#define NV2080_NOTIFIERS_NVJPEG7 (133) +#define NV2080_NOTIFIERS_RUNLIST_AND_ENG_IDLE (134) +#define NV2080_NOTIFIERS_RUNLIST_ACQUIRE (135) +#define NV2080_NOTIFIERS_RUNLIST_ACQUIRE_AND_ENG_IDLE (136) +#define NV2080_NOTIFIERS_RUNLIST_IDLE (137) +#define NV2080_NOTIFIERS_TSG_PREEMPT_COMPLETE (138) +#define NV2080_NOTIFIERS_RUNLIST_PREEMPT_COMPLETE (139) +#define NV2080_NOTIFIERS_CTXSW_TIMEOUT (140) +#define NV2080_NOTIFIERS_INFOROM_ECC_OBJECT_UPDATED (141) +#define NV2080_NOTIFIERS_NVTELEMETRY_REPORT_EVENT (142) +#define NV2080_NOTIFIERS_DSTATE_XUSB_PPC (143) +#define NV2080_NOTIFIERS_FECS_CTX_SWITCH (144) +#define NV2080_NOTIFIERS_XUSB_PPC_CONNECTED (145) +#define NV2080_NOTIFIERS_GR0 NV2080_NOTIFIERS_GRAPHICS +#define NV2080_NOTIFIERS_GR1 (146) +#define NV2080_NOTIFIERS_GR2 (147) +#define NV2080_NOTIFIERS_GR3 (148) +#define NV2080_NOTIFIERS_GR4 (149) +#define NV2080_NOTIFIERS_GR5 (150) +#define NV2080_NOTIFIERS_GR6 (151) +#define NV2080_NOTIFIERS_GR7 (152) +#define NV2080_NOTIFIERS_OFA (153) +#define NV2080_NOTIFIERS_DSTATE_HDA (154) +#define NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL (155) +#define NV2080_NOTIFIERS_POISON_ERROR_FATAL (156) +#define NV2080_NOTIFIERS_UCODE_RESET (157) +#define NV2080_NOTIFIERS_PLATFORM_POWER_MODE_CHANGE (158) +#define NV2080_NOTIFIERS_SMC_CONFIG_UPDATE (159) +#define NV2080_NOTIFIERS_INFOROM_RRL_OBJECT_UPDATED (160) +#define NV2080_NOTIFIERS_INFOROM_PBL_OBJECT_UPDATED (161) +#define NV2080_NOTIFIERS_LPWR_DIFR_PREFETCH_REQUEST (162) +#define NV2080_NOTIFIERS_SEC_FAULT_ERROR (163) +#define NV2080_NOTIFIERS_POSSIBLE_ERROR (164) +#define NV2080_NOTIFIERS_NVLINK_INFO_LINK_UP (165) +#define NV2080_NOTIFIERS_NVLINK_INFO_LINK_DOWN (176) +#define NV2080_NOTIFIERS_MAXCOUNT (177) + +// Indexed GR notifier reference +#define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x - 1))) +#define NV2080_NOTIFIERS_GR_IDX(x) ((x) - NV2080_NOTIFIERS_GR0) +#define NV2080_NOTIFIER_TYPE_IS_GR(x) (((x) == NV2080_NOTIFIERS_GR0) || (((x) >= NV2080_NOTIFIERS_GR1) && ((x) <= NV2080_NOTIFIERS_GR7))) + +#define NV2080_NOTIFIERS_CE(x) (NV2080_NOTIFIERS_CE0 + (x)) +#define NV2080_NOTIFIERS_CE_IDX(x) ((x) - NV2080_NOTIFIERS_CE0) +#define NV2080_NOTIFIER_TYPE_IS_CE(x) (((x) >= NV2080_NOTIFIERS_CE0) && ((x) <= NV2080_NOTIFIERS_CE9)) + +// Indexed MSENC notifier reference +#define NV2080_NOTIFIERS_NVENC(x) (NV2080_NOTIFIERS_NVENC0 + (x)) +#define NV2080_NOTIFIERS_NVENC_IDX(x) ((x) - NV2080_NOTIFIERS_NVENC0) +#define NV2080_NOTIFIER_TYPE_IS_NVENC(x) (((x) >= NV2080_NOTIFIERS_NVENC0) && ((x) <= NV2080_NOTIFIERS_NVENC2)) +// Indexed NVDEC notifier reference +#define NV2080_NOTIFIERS_NVDEC(x) (NV2080_NOTIFIERS_NVDEC0 + (x)) +#define NV2080_NOTIFIERS_NVDEC_IDX(x) ((x) - NV2080_NOTIFIERS_NVDEC0) +#define NV2080_NOTIFIER_TYPE_IS_NVDEC(x) (((x) >= NV2080_NOTIFIERS_NVDEC0) && ((x) <= NV2080_NOTIFIERS_NVDEC7)) +// Indexed NVJPEG notifier reference +#define NV2080_NOTIFIERS_NVJPEG(x) (NV2080_NOTIFIERS_NVJPEG0 + (x)) +#define NV2080_NOTIFIERS_NVJPEG_IDX(x) ((x) - NV2080_NOTIFIERS_NVJPEG0) +#define NV2080_NOTIFIER_TYPE_IS_NVJPEG(x) (((x) >= NV2080_NOTIFIERS_NVJPEG0) && ((x) <= NV2080_NOTIFIERS_NVJPEG7)) + +#define NV2080_NOTIFIERS_GPIO_RISING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT + (pin)) +#define NV2080_NOTIFIERS_GPIO_FALLING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT + (pin)) + +#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000) +#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000) +#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000) +#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) + +/* exported engine defines */ +#define NV2080_ENGINE_TYPE_NULL (0x00000000) +#define NV2080_ENGINE_TYPE_GRAPHICS (0x00000001) +#define NV2080_ENGINE_TYPE_GR0 NV2080_ENGINE_TYPE_GRAPHICS +#define NV2080_ENGINE_TYPE_GR1 (0x00000002) +#define NV2080_ENGINE_TYPE_GR2 (0x00000003) +#define NV2080_ENGINE_TYPE_GR3 (0x00000004) +#define NV2080_ENGINE_TYPE_GR4 (0x00000005) +#define NV2080_ENGINE_TYPE_GR5 (0x00000006) +#define NV2080_ENGINE_TYPE_GR6 (0x00000007) +#define NV2080_ENGINE_TYPE_GR7 (0x00000008) +#define NV2080_ENGINE_TYPE_COPY0 (0x00000009) +#define NV2080_ENGINE_TYPE_COPY1 (0x0000000a) +#define NV2080_ENGINE_TYPE_COPY2 (0x0000000b) +#define NV2080_ENGINE_TYPE_COPY3 (0x0000000c) +#define NV2080_ENGINE_TYPE_COPY4 (0x0000000d) +#define NV2080_ENGINE_TYPE_COPY5 (0x0000000e) +#define NV2080_ENGINE_TYPE_COPY6 (0x0000000f) +#define NV2080_ENGINE_TYPE_COPY7 (0x00000010) +#define NV2080_ENGINE_TYPE_COPY8 (0x00000011) +#define NV2080_ENGINE_TYPE_COPY9 (0x00000012) +#define NV2080_ENGINE_TYPE_BSP (0x00000013) +#define NV2080_ENGINE_TYPE_NVDEC0 NV2080_ENGINE_TYPE_BSP +#define NV2080_ENGINE_TYPE_NVDEC1 (0x00000014) +#define NV2080_ENGINE_TYPE_NVDEC2 (0x00000015) +#define NV2080_ENGINE_TYPE_NVDEC3 (0x00000016) +#define NV2080_ENGINE_TYPE_NVDEC4 (0x00000017) +#define NV2080_ENGINE_TYPE_NVDEC5 (0x00000018) +#define NV2080_ENGINE_TYPE_NVDEC6 (0x00000019) +#define NV2080_ENGINE_TYPE_NVDEC7 (0x0000001a) +#define NV2080_ENGINE_TYPE_MSENC (0x0000001b) +#define NV2080_ENGINE_TYPE_NVENC0 NV2080_ENGINE_TYPE_MSENC /* Mutually exclusive alias */ +#define NV2080_ENGINE_TYPE_NVENC1 (0x0000001c) +#define NV2080_ENGINE_TYPE_NVENC2 (0x0000001d) +#define NV2080_ENGINE_TYPE_VP (0x0000001e) +#define NV2080_ENGINE_TYPE_ME (0x0000001f) +#define NV2080_ENGINE_TYPE_PPP (0x00000020) +#define NV2080_ENGINE_TYPE_MPEG (0x00000021) +#define NV2080_ENGINE_TYPE_SW (0x00000022) +#define NV2080_ENGINE_TYPE_CIPHER (0x00000023) +#define NV2080_ENGINE_TYPE_TSEC NV2080_ENGINE_TYPE_CIPHER +#define NV2080_ENGINE_TYPE_VIC (0x00000024) +#define NV2080_ENGINE_TYPE_MP (0x00000025) +#define NV2080_ENGINE_TYPE_SEC2 (0x00000026) +#define NV2080_ENGINE_TYPE_HOST (0x00000027) +#define NV2080_ENGINE_TYPE_DPU (0x00000028) +#define NV2080_ENGINE_TYPE_PMU (0x00000029) +#define NV2080_ENGINE_TYPE_FBFLCN (0x0000002a) +#define NV2080_ENGINE_TYPE_NVJPG (0x0000002b) +#define NV2080_ENGINE_TYPE_NVJPEG0 NV2080_ENGINE_TYPE_NVJPG +#define NV2080_ENGINE_TYPE_NVJPEG1 (0x0000002c) +#define NV2080_ENGINE_TYPE_NVJPEG2 (0x0000002d) +#define NV2080_ENGINE_TYPE_NVJPEG3 (0x0000002e) +#define NV2080_ENGINE_TYPE_NVJPEG4 (0x0000002f) +#define NV2080_ENGINE_TYPE_NVJPEG5 (0x00000030) +#define NV2080_ENGINE_TYPE_NVJPEG6 (0x00000031) +#define NV2080_ENGINE_TYPE_NVJPEG7 (0x00000032) +#define NV2080_ENGINE_TYPE_OFA (0x00000033) +#define NV2080_ENGINE_TYPE_LAST (0x0000003e) +#define NV2080_ENGINE_TYPE_ALLENGINES (0xffffffff) + +#define NV2080_ENGINE_TYPE_COPY_SIZE 10 +#define NV2080_ENGINE_TYPE_NVENC_SIZE 3 +#define NV2080_ENGINE_TYPE_NVJPEG_SIZE 8 +#define NV2080_ENGINE_TYPE_NVDEC_SIZE 8 +#define NV2080_ENGINE_TYPE_GR_SIZE 8 + +// Indexed engines +#define NV2080_ENGINE_TYPE_COPY(i) (NV2080_ENGINE_TYPE_COPY0+(i)) +#define NV2080_ENGINE_TYPE_IS_COPY(i) (((i) >= NV2080_ENGINE_TYPE_COPY0) && ((i) <= NV2080_ENGINE_TYPE_COPY9)) +#define NV2080_ENGINE_TYPE_COPY_IDX(i) ((i) - NV2080_ENGINE_TYPE_COPY0) + +#define NV2080_ENGINE_TYPE_NVENC(i) (NV2080_ENGINE_TYPE_NVENC0+(i)) +#define NV2080_ENGINE_TYPE_IS_NVENC(i) (((i) >= NV2080_ENGINE_TYPE_NVENC0) && ((i) < NV2080_ENGINE_TYPE_NVENC(NV2080_ENGINE_TYPE_NVENC_SIZE))) +#define NV2080_ENGINE_TYPE_NVENC_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVENC0) + +#define NV2080_ENGINE_TYPE_NVDEC(i) (NV2080_ENGINE_TYPE_NVDEC0+(i)) +#define NV2080_ENGINE_TYPE_IS_NVDEC(i) (((i) >= NV2080_ENGINE_TYPE_NVDEC0) && ((i) < NV2080_ENGINE_TYPE_NVDEC(NV2080_ENGINE_TYPE_NVDEC_SIZE))) +#define NV2080_ENGINE_TYPE_NVDEC_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVDEC0) + +#define NV2080_ENGINE_TYPE_NVJPEG(i) (NV2080_ENGINE_TYPE_NVJPEG0+(i)) +#define NV2080_ENGINE_TYPE_IS_NVJPEG(i) (((i) >= NV2080_ENGINE_TYPE_NVJPEG0) && ((i) < NV2080_ENGINE_TYPE_NVJPEG(NV2080_ENGINE_TYPE_NVJPEG_SIZE))) +#define NV2080_ENGINE_TYPE_NVJPEG_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVJPEG0) + +#define NV2080_ENGINE_TYPE_GR(i) (NV2080_ENGINE_TYPE_GR0 + (i)) +#define NV2080_ENGINE_TYPE_IS_GR(i) (((i) >= NV2080_ENGINE_TYPE_GR0) && ((i) < NV2080_ENGINE_TYPE_GR(NV2080_ENGINE_TYPE_GR_SIZE))) +#define NV2080_ENGINE_TYPE_GR_IDX(i) ((i) - NV2080_ENGINE_TYPE_GR0) + +#define NV2080_ENGINE_TYPE_IS_VALID(i) (((i) > (NV2080_ENGINE_TYPE_NULL)) && ((i) < (NV2080_ENGINE_TYPE_LAST))) + +/* exported client defines */ +#define NV2080_CLIENT_TYPE_TEX (0x00000001) +#define NV2080_CLIENT_TYPE_COLOR (0x00000002) +#define NV2080_CLIENT_TYPE_DEPTH (0x00000003) +#define NV2080_CLIENT_TYPE_DA (0x00000004) +#define NV2080_CLIENT_TYPE_FE (0x00000005) +#define NV2080_CLIENT_TYPE_SCC (0x00000006) +#define NV2080_CLIENT_TYPE_WID (0x00000007) +#define NV2080_CLIENT_TYPE_MSVLD (0x00000008) +#define NV2080_CLIENT_TYPE_MSPDEC (0x00000009) +#define NV2080_CLIENT_TYPE_MSPPP (0x0000000a) +#define NV2080_CLIENT_TYPE_VIC (0x0000000b) +#define NV2080_CLIENT_TYPE_ALLCLIENTS (0xffffffff) + +/* GC5 Gpu Ready event defines */ +#define NV2080_GC5_EXIT_COMPLETE (0x00000001) +#define NV2080_GC5_ENTRY_ABORTED (0x00000002) + +/* Platform Power Mode event defines */ +#define NV2080_PLATFORM_POWER_MODE_CHANGE_COMPLETION (0x00000000) +#define NV2080_PLATFORM_POWER_MODE_CHANGE_ACPI_NOTIFICATION (0x00000001) + +/* NvNotification[] fields and values */ +#define NV2080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +typedef volatile struct _cl2080_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv2080Typedef, Nv20Subdevice0; +#define NV2080_TYPEDEF Nv20Subdevice0 + +/* HDCP Status change notification information */ +typedef struct Nv2080HdcpStatusChangeNotificationRec { + NvU32 displayId; + NvU32 hdcpStatusChangeNotif; +} Nv2080HdcpStatusChangeNotification; + +/* Pstate change notification information */ +typedef struct Nv2080PStateChangeNotificationRec { + struct { + NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/ + } timeStamp; /* -0007*/ + NvU32 NewPstate; +} Nv2080PStateChangeNotification; + +/* Clocks change notification information */ +typedef struct Nv2080ClocksChangeNotificationRec { + struct { + NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/ + } timeStamp; /* -0007*/ +} Nv2080ClocksChangeNotification; + +/* WorkLoad Modulation state change notification information*/ +typedef struct Nv2080WorkloadModulationChangeNotificationRec { + struct { + NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/ + } timeStamp; /* -0007*/ + NvBool WorkloadModulationEnabled; +} Nv2080WorkloadModulationChangeNotification; + +/* Hotplug notification information */ +typedef struct { + NvU32 plugDisplayMask; + NvU32 unplugDisplayMask; +} Nv2080HotplugNotification; + +/* Power state changing notification information */ +typedef struct { + NvBool bSwitchToAC; + NvBool bGPUCapabilityChanged; + NvU32 displayMaskAffected; +} Nv2080PowerEventNotification; + +/* DP IRQ notification information */ +typedef struct Nv2080DpIrqNotificationRec { + NvU32 displayId; +} Nv2080DpIrqNotification; + +/* XUSB/PPC D-State change notification information */ +typedef struct Nv2080DstateXusbPpcNotificationRec { + NvU32 dstateXusb; + NvU32 dstatePpc; +} Nv2080DstateXusbPpcNotification; + +/* XUSB/PPC Connection status notification information */ +typedef struct Nv2080XusbPpcConnectStateNotificationRec { + NvBool bConnected; +} Nv2080XusbPpcConnectStateNotification; + +/* ACPI event notification information */ +typedef struct Nv2080ACPIEvent { + NvU32 event; +} Nv2080ACPIEvent; + +/* Cooler Zone notification information */ +typedef struct _NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC { + NvU32 currentZone; +} NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC; + +/* Thermal Zone notification information */ +typedef struct _NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC { + NvU32 currentZone; +} NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC; + +/* HDCP ref count change notification information */ +typedef struct Nv2080AudioHdcpRequestRec { + NvU32 displayId; + NvU32 requestedState; +} Nv2080AudioHdcpRequest; + +/* Gpu ready event information */ +typedef struct Nv2080GC5GpuReadyParams { + NvU32 event; + NvU32 sciIntr0; + NvU32 sciIntr1; +} Nv2080GC5GpuReadyParams; + +/* Priv reg access fault notification information */ +typedef struct { + NvU32 errAddr; +} Nv2080PrivRegAccessFaultNotification; + +/* HDA D-State change notification information + * See @HDACODEC_DSTATE for definitions + */ +typedef struct Nv2080DstateHdaCodecNotificationRec { + NvU32 dstateHdaCodec; +} Nv2080DstateHdaCodecNotification; + +/* + * Platform Power Mode event information + */ +typedef struct _NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS { + NvU8 platformPowerModeIndex; + NvU8 platformPowerModeMask; + NvU8 eventReason; +} NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS; + +#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_INDEX 7:0 +#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_MASK 15:8 +#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_REASON 23:16 + +/* + * ENGINE_INFO_TYPE_NV2080 of the engine for which the QOS interrupt has been raised + */ +typedef struct { + NvU32 engineType; +} Nv2080QosIntrNotification; + +typedef struct { + NvU64 physAddress NV_ALIGN_BYTES(8); +} Nv2080EccDbeNotification; + +/* + * LPWR DIFR Prefetch Request - Size of L2 Cache + */ +typedef struct { + NvU32 l2CacheSize; +} Nv2080LpwrDifrPrefetchNotification; + +/* + * Nvlink Link status change Notification + */ +typedef struct { + NvU32 GpuId; + NvU32 linkId; +} Nv2080NvlinkLnkChangeNotification; + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl2080_notification_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl2081.h b/userspace/sdks/nv525/nvidia/inc/class/cl2081.h new file mode 100644 index 0000000..05341ca --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl2081.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl2081.finn +// + +#define NV2081_BINAPI (0x2081U) /* finn: Evaluated from "NV2081_ALLOC_PARAMETERS_MESSAGE_ID" */ + +#define NV2081_ALLOC_PARAMETERS_MESSAGE_ID (0x2081U) + +typedef struct NV2081_ALLOC_PARAMETERS { + NvU32 reserved; +} NV2081_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl2082.h b/userspace/sdks/nv525/nvidia/inc/class/cl2082.h new file mode 100644 index 0000000..0a721f5 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl2082.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl2082.finn +// + +#define NV2082_BINAPI_PRIVILEGED (0x2082U) /* finn: Evaluated from "NV2082_ALLOC_PARAMETERS_MESSAGE_ID" */ + +#define NV2082_ALLOC_PARAMETERS_MESSAGE_ID (0x2082U) + +typedef struct NV2082_ALLOC_PARAMETERS { + NvU32 reserved; +} NV2082_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl208f.h b/userspace/sdks/nv525/nvidia/inc/class/cl208f.h new file mode 100644 index 0000000..c9d7f01 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl208f.h @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2006 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl208f_h_ +#define _cl208f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* Class within the subdevice used for diagnostic purpose*/ +#define NV20_SUBDEVICE_DIAG (0x0000208f) + +/* event values */ +#define NV208F_NOTIFIERS_SW (0) +#define NV208F_NOTIFIERS_MAXCOUNT (1) + +/* NvNotification[] fields and values */ +#define NV208f_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +typedef volatile struct _cl208f_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv208fTypedef, Nv20SubdeviceDiag; +#define NV208f_TYPEDEF Nv20SubdeviceDiag + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl208f_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl30f1.h b/userspace/sdks/nv525/nvidia/inc/class/cl30f1.h new file mode 100644 index 0000000..b7edbd2 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl30f1.h @@ -0,0 +1,56 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl30f1.finn +// + +#include "cl30f1_notification.h" + +/* class NV30_GSYNC */ +#define NV30_GSYNC (0x30f1U) /* finn: Evaluated from "NV30F1_ALLOC_PARAMETERS_MESSAGE_ID" */ + +#define NV30F1_GSYNC_CONNECTOR_ONE (0) +#define NV30F1_GSYNC_CONNECTOR_TWO (1) +#define NV30F1_GSYNC_CONNECTOR_THREE (2) +#define NV30F1_GSYNC_CONNECTOR_FOUR (3) + +#define NV30F1_GSYNC_CONNECTOR_PRIMARY NV30F1_GSYNC_CONNECTOR_ONE +#define NV30F1_GSYNC_CONNECTOR_SECONDARY NV30F1_GSYNC_CONNECTOR_TWO + +#define NV30F1_GSYNC_CONNECTOR_COUNT (4) + +/* NvRmAlloc parameters */ +#define NV30F1_MAX_GSYNCS (0x0000004) + +#define NV30F1_ALLOC_PARAMETERS_MESSAGE_ID (0x30f1U) + +typedef struct NV30F1_ALLOC_PARAMETERS { + NvU32 gsyncInstance; +} NV30F1_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl30f1_notification.h b/userspace/sdks/nv525/nvidia/inc/class/cl30f1_notification.h new file mode 100644 index 0000000..290eb5c --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl30f1_notification.h @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl30f1_notification_h_ +#define _cl30f1_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * A client should use NV01_EVENT_OS_EVENT as hClass and NV30F1_GSYNC_NOTIFIERS_* as + * notify index when allocating event, if separate event notifications are needed for + * separate event types. + * + * A client should use NV01_EVENT_KERNEL_CALLBACK as hClass and + * NV30F1_GSYNC_NOTIFIERS_ALL as notify index, if a single event is required. + * In this case RM would set event data equal to a pointer to NvNotification structure. + * The info32 field of NvNotification structure would be equal a bitmask of + * NV30F1_GSYNC_NOTIFIERS_* values. + */ + +/* NvNotification[] fields and values */ + +/* Framelock sync gain and loss events. These are connector specific events. */ +#define NV30F1_GSYNC_NOTIFIERS_SYNC_LOSS(c) (0x00+(c)) +#define NV30F1_GSYNC_NOTIFIERS_SYNC_GAIN(c) (0x04+(c)) + +/* Framelock stereo gain and loss events. These are connector specific events. */ +#define NV30F1_GSYNC_NOTIFIERS_STEREO_LOSS(c) (0x08+(c)) +#define NV30F1_GSYNC_NOTIFIERS_STEREO_GAIN(c) (0x0C+(c)) + +/* House cable gain(plug in) and loss(plug out) events. */ +#define NV30F1_GSYNC_NOTIFIERS_HOUSE_GAIN (0x10) +#define NV30F1_GSYNC_NOTIFIERS_HOUSE_LOSS (0x11) + +/* RJ45 cable gain(plug in) and loss(plug out) events. */ +#define NV30F1_GSYNC_NOTIFIERS_RJ45_GAIN (0x12) +#define NV30F1_GSYNC_NOTIFIERS_RJ45_LOSS (0x13) + +#define NV30F1_GSYNC_NOTIFIERS_MAXCOUNT (0x14) + +/* + * For handling all event types. + * Note for Windows, it only handles NV01_EVENT_KERNEL_CALLBACK_EX; as for NV01_EVENT_OS_EVENT, it can only + * signal an event but not handle over any information. + */ +#define NV30F1_GSYNC_NOTIFIERS_ALL NV30F1_GSYNC_NOTIFIERS_MAXCOUNT + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl30f1_notification_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl402c.h b/userspace/sdks/nv525/nvidia/inc/class/cl402c.h new file mode 100644 index 0000000..9ba7c3b --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl402c.h @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2010 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl402c_h_ +#define _cl402c_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* I2C operations */ +#define NV40_I2C (0x0000402c) + +typedef volatile struct _cl402c_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv402cTypedef, Nv40I2c; +#define NV402C_TYPEDEF Nv40I2c + + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl402c_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl503b.h b/userspace/sdks/nv525/nvidia/inc/class/cl503b.h new file mode 100644 index 0000000..b372f78 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl503b.h @@ -0,0 +1,57 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl503b.finn +// + +#define NV50_P2P (0x503bU) /* finn: Evaluated from "NV503B_ALLOC_PARAMETERS_MESSAGE_ID" */ + +#define NV503B_FLAGS_P2P_TYPE 0:0 +#define NV503B_FLAGS_P2P_TYPE_GPA 0 +#define NV503B_FLAGS_P2P_TYPE_SPA 1 + +/* NvRmAlloc parameters */ +#define NV503B_ALLOC_PARAMETERS_MESSAGE_ID (0x503bU) + +typedef struct NV503B_ALLOC_PARAMETERS { + NvHandle hSubDevice; /* subDevice handle of local GPU */ + NvHandle hPeerSubDevice; /* subDevice handle of peer GPU */ + NvU32 subDevicePeerIdMask; /* Bit mask of peer ID for SubDevice + * A value of 0 defaults to RM selected + * PeerIdMasks must match in loopback */ + NvU32 peerSubDevicePeerIdMask; /* Bit mask of peer ID for PeerSubDevice + * A value of 0 defaults to RM selected + * PeerIdMasks must match in loopback */ + NV_DECLARE_ALIGNED(NvU64 mailboxBar1Addr, 8); /* P2P Mailbox area base offset in BAR1 + * Must have the same value across the GPUs */ + NvU32 mailboxTotalSize; /* Size of the P2P Mailbox area + * Must have the same value across the GPUs */ + NvU32 flags; /* Flag to indicate types/attib of p2p */ +} NV503B_ALLOC_PARAMETERS; diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl503c.h b/userspace/sdks/nv525/nvidia/inc/class/cl503c.h new file mode 100644 index 0000000..7f28960 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl503c.h @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl503c.finn +// + +#define NV50_THIRD_PARTY_P2P (0x503cU) /* finn: Evaluated from "NV503C_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* NvRmAlloc parameters */ +#define NV503C_ALLOC_PARAMETERS_MESSAGE_ID (0x503cU) + +typedef struct NV503C_ALLOC_PARAMETERS { + NvU32 flags; +} NV503C_ALLOC_PARAMETERS; + +#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE 1:0 +#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_PROPRIETARY (0x00000000) +#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_BAR1 (0x00000001) +#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_NVLINK (0x00000002) + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl506f.h b/userspace/sdks/nv525/nvidia/inc/class/cl506f.h new file mode 100644 index 0000000..b086c43 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl506f.h @@ -0,0 +1,157 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl506f_h_ +#define _cl506f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class NV50_CHANNEL_GPFIFO */ +#define NV50_CHANNEL_GPFIFO (0x0000506F) + +/* NvNotification[] elements */ +#define NV506F_NOTIFIERS_RC (0) +#define NV506F_NOTIFIERS_SW (1) +#define NV506F_NOTIFIERS_GR_DEBUG_INTR (2) +#define NV506F_NOTIFIERS_MAXCOUNT (3) + +/* NvNotification[] fields and values */ +#define NV506f_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NV506f_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +typedef volatile struct _cl506f_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv506fTypedef, Nv50ChannelGPFifo; +#define NV506F_TYPEDEF Nv50ChannelGPFifo +/* pio flow control data structure */ +typedef volatile struct _cl506f_tag1 { + NvU32 Ignored00[0x010]; /* 0000-0039*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 SetReference; /* set reference value 0050-0053*/ + NvU32 Ignored02[0x001]; /* 0054-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored03[0x007]; /* 0064-007f*/ + NvU32 Yield; /* engine yield, write only 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x3dc]; +} Nv506fControl, Nv50ControlGPFifo; +/* fields and values */ +#define NV506F_NUMBER_OF_SUBCHANNELS (8) +#define NV506F_SET_OBJECT (0x00000000) +#define NV506F_SET_REFERENCE (0x00000050) +#define NV506F_SET_CONTEXT_DMA_SEMAPHORE (0x00000060) +#define NV506F_SEMAPHORE_OFFSET (0x00000064) +#define NV506F_SEMAPHORE_ACQUIRE (0x00000068) +#define NV506F_SEMAPHORE_RELEASE (0x0000006c) +#define NV506F_YIELD (0x00000080) + +// +// GPFIFO entry format +// +#define NV506F_GP_ENTRY__SIZE 8 +#define NV506F_GP_ENTRY0_DISABLE 0:0 +#define NV506F_GP_ENTRY0_DISABLE_NOT 0x00000000 +#define NV506F_GP_ENTRY0_DISABLE_SKIP 0x00000001 +#define NV506F_GP_ENTRY0_NO_CONTEXT_SWITCH 1:1 +#define NV506F_GP_ENTRY0_NO_CONTEXT_SWITCH_FALSE 0x00000000 +#define NV506F_GP_ENTRY0_NO_CONTEXT_SWITCH_TRUE 0x00000001 +#define NV506F_GP_ENTRY0_GET 31:2 +#define NV506F_GP_ENTRY1_GET_HI 7:0 +#define NV506F_GP_ENTRY1_PRIV 8:8 +#define NV506F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NV506F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NV506F_GP_ENTRY1_LEVEL 9:9 +#define NV506F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NV506F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NV506F_GP_ENTRY1_LENGTH 31:10 + +/* dma method descriptor formats */ +#define NV506F_DMA_PRIMARY_OPCODE 1:0 +#define NV506F_DMA_PRIMARY_OPCODE_USES_SECONDARY (0x00000000) +#define NV506F_DMA_PRIMARY_OPCODE_RESERVED (0x00000003) +#define NV506F_DMA_METHOD_ADDRESS 12:2 +#define NV506F_DMA_METHOD_SUBCHANNEL 15:13 +#define NV506F_DMA_TERT_OP 17:16 +#define NV506F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NV506F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NV506F_DMA_TERT_OP_GRP0_DOUBLE_HEADER (0x00000003) +#define NV506F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NV506F_DMA_TERT_OP_GRP2_RESERVED01 (0x00000001) +#define NV506F_DMA_TERT_OP_GRP2_RESERVED10 (0x00000002) +#define NV506F_DMA_TERT_OP_GRP2_RESERVED11 (0x00000003) +#define NV506F_DMA_METHOD_COUNT 28:18 +#define NV506F_DMA_SEC_OP 31:29 +#define NV506F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NV506F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NV506F_DMA_SEC_OP_GRP3_RESERVED (0x00000003) +#define NV506F_DMA_SEC_OP_GRP4_RESERVED (0x00000004) +#define NV506F_DMA_SEC_OP_GRP5_RESERVED (0x00000005) +#define NV506F_DMA_SEC_OP_GRP6_RESERVED (0x00000006) +#define NV506F_DMA_SEC_OP_GRP7_RESERVED (0x00000007) +#define NV506F_DMA_LONG_COUNT 31:0 +/* dma legacy method descriptor format */ +#define NV506F_DMA_OPCODE2 1:0 +#define NV506F_DMA_OPCODE2_NONE (0x00000000) +#define NV506F_DMA_OPCODE 31:29 +#define NV506F_DMA_OPCODE_METHOD (0x00000000) +#define NV506F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NV506F_DMA_OPCODE3_NONE (0x00000000) +/* dma data format */ +#define NV506F_DMA_DATA 31:0 +/* dma double header descriptor format */ +#define NV506F_DMA_DH_OPCODE2 1:0 +#define NV506F_DMA_DH_OPCODE2_NONE (0x00000000) +#define NV506F_DMA_DH_METHOD_ADDRESS 12:2 +#define NV506F_DMA_DH_METHOD_SUBCHANNEL 15:13 +#define NV506F_DMA_DH_OPCODE3 17:16 +#define NV506F_DMA_DH_OPCODE3_DOUBLE_HEADER (0x00000003) +#define NV506F_DMA_DH_OPCODE 31:29 +#define NV506F_DMA_DH_OPCODE_METHOD (0x00000000) +/* dma double header method count format */ +#define NV506F_DMA_DH_METHOD_COUNT 23:0 +/* dma double header data format */ +#define NV506F_DMA_DH_DATA 31:0 +/* dma nop format */ +#define NV506F_DMA_NOP (0x00000000) +/* dma set subdevice mask format */ +#define NV506F_DMA_SET_SUBDEVICE_MASK (0x00010000) +#define NV506F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NV506F_DMA_OPCODE3 17:16 +#define NV506F_DMA_OPCODE3_SET_SUBDEVICE_MASK (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl506f_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl5070.h b/userspace/sdks/nv525/nvidia/inc/class/cl5070.h new file mode 100644 index 0000000..6a26551 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl5070.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl5070.finn +// + +#include "cl5070_notification.h" + +#define NV50_DISPLAY (0x5070U) /* finn: Evaluated from "NV5070_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV5070_ALLOCATION_PARAMETERS_MESSAGE_ID (0x5070U) + +typedef struct NV5070_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numDacs; // Number of DACs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NV5070_ALLOCATION_PARAMETERS; diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl5070_notification.h b/userspace/sdks/nv525/nvidia/inc/class/cl5070_notification.h new file mode 100644 index 0000000..a23107d --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl5070_notification.h @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl5070_notification_h_ +#define _cl5070_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* event values */ +#define NV5070_NOTIFIERS_SW (0) +#define NV5070_NOTIFIERS_MAXCOUNT (1) + +#define NV5070_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NV5070_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000) +#define NV5070_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000) +#define NV5070_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000) +#define NV5070_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl5070_notification_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl5080.h b/userspace/sdks/nv525/nvidia/inc/class/cl5080.h new file mode 100644 index 0000000..cf05945 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl5080.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2002-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl5080.finn +// + +#include "cl5080_notification.h" + +#define NV50_DEFERRED_API_CLASS (0x5080U) /* finn: Evaluated from "NV5080_ALLOC_PARAMS_MESSAGE_ID" */ + +/* NvRmAlloc parameters */ +#define NV5080_ALLOC_PARAMS_MESSAGE_ID (0x5080U) + +typedef struct NV5080_ALLOC_PARAMS { + // Should the deferred api completion trigger an event + NvBool notifyCompletion; +} NV5080_ALLOC_PARAMS; + +// Class-specific allocation capabilities + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl5080_notification.h b/userspace/sdks/nv525/nvidia/inc/class/cl5080_notification.h new file mode 100644 index 0000000..170c8fb --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl5080_notification.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl5080_notification_h_ +#define _cl5080_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* dma method offsets, fields, and values */ +#define NV5080_SET_OBJECT (0x00000000) +#define NV5080_NO_OPERATION (0x00000100) +#define NV5080_DEFERRED_API (0x00000200) +#define NV5080_DEFERRED_API_HANDLE 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl5080_notification_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl50a0.h b/userspace/sdks/nv525/nvidia/inc/class/cl50a0.h new file mode 100644 index 0000000..5fec57e --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl50a0.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2005, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl50a0_h_ +#define _cl50a0_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV50_MEMORY_VIRTUAL (0x000050a0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl50a0_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl83de.h b/userspace/sdks/nv525/nvidia/inc/class/cl83de.h new file mode 100644 index 0000000..df67deb --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl83de.h @@ -0,0 +1,56 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl83de.finn +// + +#define GT200_DEBUGGER (0x83deU) /* finn: Evaluated from "NV83DE_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* + * Creating the GT200_DEBUGGER object: + * - The debug object is instantiated as a child of either the compute or the + * 3D-class object. + * - The Cuda/GR debugger uses the NV83DE_ALLOC_PARAMETERS to fill in the Client + * and 3D-Class handles of the debuggee and passes this to the NvRmAlloc. + * e.g: + NV83DE_ALLOC_PARAMETERS params; + * memset (¶ms, 0, sizeof (NV83DE_ALLOC_PARAMETERS)); + * params.hAppClient = DebuggeeClient; + * params.hClass3dObject = 3DClassHandle; + * NvRmAlloc(hDebuggerClient, hDebuggerClient, hDebugger, GT200_DEBUGGER, ¶ms); + */ + +#define NV83DE_ALLOC_PARAMETERS_MESSAGE_ID (0x83deU) + +typedef struct NV83DE_ALLOC_PARAMETERS { + NvHandle hDebuggerClient_Obsolete; // No longer supported (must be zero) + NvHandle hAppClient; + NvHandle hClass3dObject; +} NV83DE_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl844c.h b/userspace/sdks/nv525/nvidia/inc/class/cl844c.h new file mode 100644 index 0000000..c4afe5f --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl844c.h @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl844c_h_ +#define _cl844c_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define G84_PERFBUFFER (0x0000844C) + +/* pio method data structure */ +typedef volatile struct _cl844c_tag0 { + NvV32 Reserved00[0x7c0]; +} G844cTypedef, G84PerfBuffer; +#define G844C_TYPEDEF G84PerfBuffer + +#define G844C_PERFBUFFER_MEMORY_HANDLE (0x844C0001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl844c_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl84a0.h b/userspace/sdks/nv525/nvidia/inc/class/cl84a0.h new file mode 100644 index 0000000..1ee51ad --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl84a0.h @@ -0,0 +1,110 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl84a0.finn +// + +#include "cl84a0_deprecated.h" + +/* + * Class definitions for creating a memory descriptor from a list of page numbers + * in RmAllocMemory. No memory is allocated: only a memory descriptor and + * memory object are created for later use in other calls. These classes + * are used by vGPU to create references to memory assigned to a guest VM. + * In all cases, the list is passed as reference, in the pAddress argument + * of RmAllocMemory, to a Nv01MemoryList structure (cast to a void **). + */ + +/* List of system memory physical page numbers */ +#define NV01_MEMORY_LIST_SYSTEM (0x00000081) +/* List of frame buffer physical page numbers */ +#define NV01_MEMORY_LIST_FBMEM (0x00000082) +/* List of page numbers relative to the start of the specified object */ +#define NV01_MEMORY_LIST_OBJECT (0x00000083) + +/* + * List structure of NV01_MEMORY_LIST_* classes + * + * The pageNumber array is variable in length, with pageCount elements, + * so the allocated size of the structure must reflect that. + * + * FBMEM items apply only to NV01_MEMORY_LIST_FBMEM and to + * NV01_MEMORY_LIST_OBJECT when the underlying object is + * FBMEM (must be zero for other cases) + * + * NV_MEMORY_LIST_ALLOCATION_PARAMS - Allocation params to create memory list + * through NvRmAlloc. + */ +#define NV_MEMORY_LIST_ALLOCATION_PARAMS_MESSAGE_ID (0x84a0U) + +typedef struct NV_MEMORY_LIST_ALLOCATION_PARAMS { + NvHandle hClient; /* client to which object belongs + * (may differ from client creating the mapping). + * May be NV01_NULL_OBJECT, in which case client + * handle is used */ + NvHandle hParent; /* device with which object is associated. + * Must be NV01_NULL_OBJECT if hClient is NV01_NULL_OBJECT. + * Must not be NV01_NULL_OBJECT if hClient is + * not NV01_NULL_OBJECT. */ + NvHandle hObject; /* object to which pages are relative + * (NV01_NULL_OBJECT for NV01_MEMORY_LIST_SYSTEM + * and NV01_MEMORY_LIST_FBMEM) */ + NvHandle hHwResClient; /* client associated with the backdoor vnc surface*/ + NvHandle hHwResDevice; /* device associated to the bacdoor vnc surface*/ + NvHandle hHwResHandle; /* handle to hardware resources allocated to + * backdoor vnc surface*/ + NvU32 pteAdjust; /* offset of data in first page */ + NvU32 reserved_0; /* reserved: must be 0 */ + NvU32 type; /* FBMEM: NVOS32_TYPE_* */ + NvU32 flags; /* FBMEM: NVOS32_ALLOC_FLAGS_* */ + NvU32 attr; /* FBMEM: NVOS32_ATTR_* */ + NvU32 attr2; /* FBMEM: NVOS32_ATTR2_* */ + NvU32 height; /* FBMEM: height in pixels */ + NvU32 width; /* FBMEM: width in pixels */ + NvU32 format; /* FBMEM: memory kind */ + NvU32 comprcovg; /* FBMEM: compression coverage */ + NvU32 zcullcovg; /* FBMEM: Z-cull coverage */ + NvU32 pageCount; /* count of elements in pageNumber array */ + NvU32 heapOwner; /* heap owner information from client */ + + NV_DECLARE_ALIGNED(NvU64 guestId, 8); + /* ID of the guest VM. e.g., domain ID in case of Xen */ + NV_DECLARE_ALIGNED(NvU64 rangeBegin, 8); + /* preferred VA range start address */ + NV_DECLARE_ALIGNED(NvU64 rangeEnd, 8); + /* preferred VA range end address */ + NvU32 pitch; + NvU32 ctagOffset; + NV_DECLARE_ALIGNED(NvU64 size, 8); + NV_DECLARE_ALIGNED(NvU64 align, 8); + NV_DECLARE_ALIGNED(NvP64 pageNumberList, 8); + NV_DECLARE_ALIGNED(NvU64 limit, 8); + NvU32 flagsOs02; +} NV_MEMORY_LIST_ALLOCATION_PARAMS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl84a0_deprecated.h b/userspace/sdks/nv525/nvidia/inc/class/cl84a0_deprecated.h new file mode 100644 index 0000000..f1e7f0c --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl84a0_deprecated.h @@ -0,0 +1,90 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl84a0_deprecated_h_ +#define _cl84a0_deprecated_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * List structure of NV01_MEMORY_LIST_* classes + * + * The pageNumber array is variable in length, with pageCount elements, + * so the allocated size of the structure must reflect that. + * + * FBMEM items apply only to NV01_MEMORY_LIST_FBMEM and to + * NV01_MEMORY_LIST_OBJECT when the underlying object is + * FBMEM (must be zero for other cases) + * + * Nv01MemoryList is deprecated. NV_MEMORY_LIST_ALLOCATION_PARAMS should be used + * instead. + */ +typedef struct Nv01MemoryListRec { + NvHandle hClient; /* client to which object belongs + * (may differ from client creating the mapping). + * May be NV01_NULL_OBJECT, in which case client + * handle is used */ + NvHandle hParent; /* device with which object is associated. + * Must be NV01_NULL_OBJECT if hClient is NV01_NULL_OBJECT. + * Must not be NV01_NULL_OBJECT if hClient is + * not NV01_NULL_OBJECT. */ + NvHandle hObject; /* object to which pages are relative + * (NV01_NULL_OBJECT for NV01_MEMORY_LIST_SYSTEM + * and NV01_MEMORY_LIST_FBMEM) */ + NvHandle hHwResClient;/* client associated with the backdoor vnc surface*/ + NvHandle hHwResDevice;/* device associated to the bacdoor vnc surface*/ + NvHandle hHwResHandle;/* handle to hardware resources allocated to + * backdoor vnc surface*/ + NvU32 pteAdjust; /* offset of data in first page */ + NvU32 type; /* FBMEM: NVOS32_TYPE_* */ + NvU32 flags; /* FBMEM: NVOS32_ALLOC_FLAGS_* */ + NvU32 attr; /* FBMEM: NVOS32_ATTR_* */ + NvU32 attr2; /* FBMEM: NVOS32_ATTR2_* */ + NvU32 height; /* FBMEM: height in pixels */ + NvU32 width; /* FBMEM: width in pixels */ + NvU32 format; /* FBMEM: memory kind */ + NvU32 comprcovg; /* FBMEM: compression coverage */ + NvU32 zcullcovg; /* FBMEM: Z-cull coverage */ + NvU32 pageCount; /* count of elements in pageNumber array */ + NvU32 heapOwner; /* heap owner information from client */ + NvU32 reserved_1; /* reserved: must be 0 */ + NvU64 NV_DECLARE_ALIGNED(guestId,8); + /* ID of the guest VM. e.g., domain ID in case of Xen */ + NvU64 NV_DECLARE_ALIGNED(rangeBegin,8); + /* preferred VA range start address */ + NvU64 NV_DECLARE_ALIGNED(rangeEnd,8); + /* preferred VA range end address */ + NvU32 pitch; + NvU32 ctagOffset; + NvU64 size; + NvU64 align; + NvU64 pageNumber[1]; /* variable length array of page numbers */ +} Nv01MemoryList; + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl84a0_deprecated_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl85b5sw.h b/userspace/sdks/nv525/nvidia/inc/class/cl85b5sw.h new file mode 100644 index 0000000..63e1160 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl85b5sw.h @@ -0,0 +1,38 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl85b5sw.finn +// + +#define NV85B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0x85b5U) + +typedef struct NV85B5_ALLOCATION_PARAMETERS { + NvU32 version; // set to 0 + NvU32 engineInstance; // CE instance +} NV85B5_ALLOCATION_PARAMETERS; diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl900e.h b/userspace/sdks/nv525/nvidia/inc/class/cl900e.h new file mode 100644 index 0000000..6684889 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl900e.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl900e_h_ +#define _cl900e_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define MPS_COMPUTE (0x0000900E) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl900e_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl9010.h b/userspace/sdks/nv525/nvidia/inc/class/cl9010.h new file mode 100644 index 0000000..722277b --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl9010.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9010.finn +// + +#include "class/cl9010_callback.h" + +#define NV9010_VBLANK_CALLBACK (0x9010U) /* finn: Evaluated from "NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9010U) + +typedef struct NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS { + NV_DECLARE_ALIGNED(NvP64 pProc, 8); // Routine to call at vblank time + // A function pointer of OSVBLANKCALLBACKPROC + NvV32 LogicalHead; // Logical Head + NV_DECLARE_ALIGNED(NvP64 pParm1, 8); // pParm1 + NV_DECLARE_ALIGNED(NvP64 pParm2, 8); // pParm2 +} NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl9010_callback.h b/userspace/sdks/nv525/nvidia/inc/class/cl9010_callback.h new file mode 100644 index 0000000..1945b68 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl9010_callback.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef SDK_CL9010_CALLBACK_H +#define SDK_CL9010_CALLBACK_H + +typedef void (*OSVBLANKCALLBACKPROC)(NvP64 pParm1, NvP64 pParm2); + +#endif // SDK_CL9010_CALLBACK_H diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl902d.h b/userspace/sdks/nv525/nvidia/inc/class/cl902d.h new file mode 100644 index 0000000..38bd5cf --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl902d.h @@ -0,0 +1,1092 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_fermi_twod_a_h_ +#define _cl_fermi_twod_a_h_ + +#define FERMI_TWOD_A 0x902D + +typedef volatile struct fermi_twod_a_struct { + NvU32 SetObject; + NvU32 Reserved_0x04[0x3F]; + NvU32 NoOperation; + NvU32 SetNotifyA; + NvU32 SetNotifyB; + NvU32 Notify; + NvU32 WaitForIdle; + NvU32 LoadMmeInstructionRamPointer; + NvU32 LoadMmeInstructionRam; + NvU32 LoadMmeStartAddressRamPointer; + NvU32 LoadMmeStartAddressRam; + NvU32 SetMmeShadowRamControl; + NvU32 Reserved_0x128[0x2]; + NvU32 SetGlobalRenderEnableA; + NvU32 SetGlobalRenderEnableB; + NvU32 SetGlobalRenderEnableC; + NvU32 SendGoIdle; + NvU32 PmTrigger; + NvU32 Reserved_0x144[0x3]; + NvU32 SetInstrumentationMethodHeader; + NvU32 SetInstrumentationMethodData; + NvU32 Reserved_0x158[0x25]; + NvU32 SetMmeSwitchState; + NvU32 Reserved_0x1F0[0x4]; + NvU32 SetDstFormat; + NvU32 SetDstMemoryLayout; + NvU32 SetDstBlockSize; + NvU32 SetDstDepth; + NvU32 SetDstLayer; + NvU32 SetDstPitch; + NvU32 SetDstWidth; + NvU32 SetDstHeight; + NvU32 SetDstOffsetUpper; + NvU32 SetDstOffsetLower; + NvU32 FlushAndInvalidateRopMiniCache; + NvU32 SetSpareNoop06; + NvU32 SetSrcFormat; + NvU32 SetSrcMemoryLayout; + NvU32 SetSrcBlockSize; + NvU32 SetSrcDepth; + NvU32 TwodInvalidateTextureDataCache; + NvU32 SetSrcPitch; + NvU32 SetSrcWidth; + NvU32 SetSrcHeight; + NvU32 SetSrcOffsetUpper; + NvU32 SetSrcOffsetLower; + NvU32 SetPixelsFromMemorySectorPromotion; + NvU32 SetSpareNoop12; + NvU32 SetNumProcessingClusters; + NvU32 SetRenderEnableA; + NvU32 SetRenderEnableB; + NvU32 SetRenderEnableC; + NvU32 SetSpareNoop08; + NvU32 SetSpareNoop01; + NvU32 SetSpareNoop11; + NvU32 SetSpareNoop07; + NvU32 SetClipX0; + NvU32 SetClipY0; + NvU32 SetClipWidth; + NvU32 SetClipHeight; + NvU32 SetClipEnable; + NvU32 SetColorKeyFormat; + NvU32 SetColorKey; + NvU32 SetColorKeyEnable; + NvU32 SetRop; + NvU32 SetBeta1; + NvU32 SetBeta4; + NvU32 SetOperation; + NvU32 SetPatternOffset; + NvU32 SetPatternSelect; + NvU32 SetDstColorRenderToZetaSurface; + NvU32 SetSpareNoop04; + NvU32 SetSpareNoop15; + NvU32 SetSpareNoop13; + NvU32 SetSpareNoop03; + NvU32 SetSpareNoop14; + NvU32 SetSpareNoop02; + NvU32 SetCompression; + NvU32 SetSpareNoop09; + NvU32 SetRenderEnableOverride; + NvU32 SetPixelsFromMemoryDirection; + NvU32 SetSpareNoop10; + NvU32 SetMonochromePatternColorFormat; + NvU32 SetMonochromePatternFormat; + NvU32 SetMonochromePatternColor0; + NvU32 SetMonochromePatternColor1; + NvU32 SetMonochromePattern0; + NvU32 SetMonochromePattern1; + NvU32 ColorPatternX8R8G8B8[0x40]; + NvU32 ColorPatternR5G6B5[0x20]; + NvU32 ColorPatternX1R5G5B5[0x20]; + NvU32 ColorPatternY8[0x10]; + NvU32 SetRenderSolidPrimColor0; + NvU32 SetRenderSolidPrimColor1; + NvU32 SetRenderSolidPrimColor2; + NvU32 SetRenderSolidPrimColor3; + NvU32 SetMmeMemAddressA; + NvU32 SetMmeMemAddressB; + NvU32 SetMmeDataRamAddress; + NvU32 MmeDmaRead; + NvU32 MmeDmaReadFifoed; + NvU32 MmeDmaWrite; + NvU32 MmeDmaReduction; + NvU32 MmeDmaSysmembar; + NvU32 MmeDmaSync; + NvU32 SetMmeDataFifoConfig; + NvU32 Reserved_0x578[0x2]; + NvU32 RenderSolidPrimMode; + NvU32 SetRenderSolidPrimColorFormat; + NvU32 SetRenderSolidPrimColor; + NvU32 SetRenderSolidLineTieBreakBits; + NvU32 Reserved_0x590[0x14]; + NvU32 RenderSolidPrimPointXY; + NvU32 Reserved_0x5E4[0x7]; + struct { + NvU32 SetX; + NvU32 Y; + } RenderSolidPrimPoint[0x40]; + NvU32 SetPixelsFromCpuDataType; + NvU32 SetPixelsFromCpuColorFormat; + NvU32 SetPixelsFromCpuIndexFormat; + NvU32 SetPixelsFromCpuMonoFormat; + NvU32 SetPixelsFromCpuWrap; + NvU32 SetPixelsFromCpuColor0; + NvU32 SetPixelsFromCpuColor1; + NvU32 SetPixelsFromCpuMonoOpacity; + NvU32 Reserved_0x820[0x6]; + NvU32 SetPixelsFromCpuSrcWidth; + NvU32 SetPixelsFromCpuSrcHeight; + NvU32 SetPixelsFromCpuDxDuFrac; + NvU32 SetPixelsFromCpuDxDuInt; + NvU32 SetPixelsFromCpuDyDvFrac; + NvU32 SetPixelsFromCpuDyDvInt; + NvU32 SetPixelsFromCpuDstX0Frac; + NvU32 SetPixelsFromCpuDstX0Int; + NvU32 SetPixelsFromCpuDstY0Frac; + NvU32 SetPixelsFromCpuDstY0Int; + NvU32 PixelsFromCpuData; + NvU32 Reserved_0x864[0x3]; + NvU32 SetBigEndianControl; + NvU32 Reserved_0x874[0x3]; + NvU32 SetPixelsFromMemoryBlockShape; + NvU32 SetPixelsFromMemoryCorralSize; + NvU32 SetPixelsFromMemorySafeOverlap; + NvU32 SetPixelsFromMemorySampleMode; + NvU32 Reserved_0x890[0x8]; + NvU32 SetPixelsFromMemoryDstX0; + NvU32 SetPixelsFromMemoryDstY0; + NvU32 SetPixelsFromMemoryDstWidth; + NvU32 SetPixelsFromMemoryDstHeight; + NvU32 SetPixelsFromMemoryDuDxFrac; + NvU32 SetPixelsFromMemoryDuDxInt; + NvU32 SetPixelsFromMemoryDvDyFrac; + NvU32 SetPixelsFromMemoryDvDyInt; + NvU32 SetPixelsFromMemorySrcX0Frac; + NvU32 SetPixelsFromMemorySrcX0Int; + NvU32 SetPixelsFromMemorySrcY0Frac; + NvU32 PixelsFromMemorySrcY0Int; + NvU32 SetFalcon00; + NvU32 SetFalcon01; + NvU32 SetFalcon02; + NvU32 SetFalcon03; + NvU32 SetFalcon04; + NvU32 SetFalcon05; + NvU32 SetFalcon06; + NvU32 SetFalcon07; + NvU32 SetFalcon08; + NvU32 SetFalcon09; + NvU32 SetFalcon10; + NvU32 SetFalcon11; + NvU32 SetFalcon12; + NvU32 SetFalcon13; + NvU32 SetFalcon14; + NvU32 SetFalcon15; + NvU32 SetFalcon16; + NvU32 SetFalcon17; + NvU32 SetFalcon18; + NvU32 SetFalcon19; + NvU32 SetFalcon20; + NvU32 SetFalcon21; + NvU32 SetFalcon22; + NvU32 SetFalcon23; + NvU32 SetFalcon24; + NvU32 SetFalcon25; + NvU32 SetFalcon26; + NvU32 SetFalcon27; + NvU32 SetFalcon28; + NvU32 SetFalcon29; + NvU32 SetFalcon30; + NvU32 SetFalcon31; + NvU32 Reserved_0x960[0x123]; + NvU32 MmeDmaWriteMethodBarrier; + NvU32 Reserved_0xDF0[0x984]; + NvU32 SetMmeShadowScratch[0x100]; + struct { + NvU32 Macro; + NvU32 Data; + } CallMme[0xE0]; +} fermi_twod_a_t; + + +#define NV902D_SET_OBJECT 0x0000 +#define NV902D_SET_OBJECT_CLASS_ID 15:0 +#define NV902D_SET_OBJECT_ENGINE_ID 20:16 + +#define NV902D_NO_OPERATION 0x0100 +#define NV902D_NO_OPERATION_V 31:0 + +#define NV902D_SET_NOTIFY_A 0x0104 +#define NV902D_SET_NOTIFY_A_ADDRESS_UPPER 24:0 + +#define NV902D_SET_NOTIFY_B 0x0108 +#define NV902D_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NV902D_NOTIFY 0x010c +#define NV902D_NOTIFY_TYPE 31:0 +#define NV902D_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NV902D_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NV902D_WAIT_FOR_IDLE 0x0110 +#define NV902D_WAIT_FOR_IDLE_V 31:0 + +#define NV902D_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NV902D_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NV902D_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NV902D_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NV902D_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NV902D_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NV902D_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NV902D_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NV902D_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NV902D_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NV902D_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NV902D_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NV902D_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NV902D_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NV902D_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV902D_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV902D_SEND_GO_IDLE 0x013c +#define NV902D_SEND_GO_IDLE_V 31:0 + +#define NV902D_PM_TRIGGER 0x0140 +#define NV902D_PM_TRIGGER_V 31:0 + +#define NV902D_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NV902D_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NV902D_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NV902D_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NV902D_SET_MME_SWITCH_STATE 0x01ec +#define NV902D_SET_MME_SWITCH_STATE_VALID 0:0 +#define NV902D_SET_MME_SWITCH_STATE_VALID_FALSE 0x00000000 +#define NV902D_SET_MME_SWITCH_STATE_VALID_TRUE 0x00000001 +#define NV902D_SET_MME_SWITCH_STATE_SAVE_MACRO 11:4 +#define NV902D_SET_MME_SWITCH_STATE_RESTORE_MACRO 19:12 + +#define NV902D_SET_DST_FORMAT 0x0200 +#define NV902D_SET_DST_FORMAT_V 7:0 +#define NV902D_SET_DST_FORMAT_V_A8R8G8B8 0x000000CF +#define NV902D_SET_DST_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NV902D_SET_DST_FORMAT_V_A2R10G10B10 0x000000DF +#define NV902D_SET_DST_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV902D_SET_DST_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NV902D_SET_DST_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV902D_SET_DST_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV902D_SET_DST_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NV902D_SET_DST_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV902D_SET_DST_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NV902D_SET_DST_FORMAT_V_R5G6B5 0x000000E8 +#define NV902D_SET_DST_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV902D_SET_DST_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV902D_SET_DST_FORMAT_V_Y8 0x000000F3 +#define NV902D_SET_DST_FORMAT_V_Y16 0x000000EE +#define NV902D_SET_DST_FORMAT_V_Y32 0x000000FF +#define NV902D_SET_DST_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV902D_SET_DST_FORMAT_V_O1R5G5B5 0x000000FC +#define NV902D_SET_DST_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV902D_SET_DST_FORMAT_V_O8R8G8B8 0x000000FE +#define NV902D_SET_DST_FORMAT_V_Y1_8X8 0x0000001C +#define NV902D_SET_DST_FORMAT_V_RF16 0x000000F2 +#define NV902D_SET_DST_FORMAT_V_RF32 0x000000E5 +#define NV902D_SET_DST_FORMAT_V_RF32_GF32 0x000000CB +#define NV902D_SET_DST_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NV902D_SET_DST_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NV902D_SET_DST_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NV902D_SET_DST_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NV902D_SET_DST_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NV902D_SET_DST_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NV902D_SET_DST_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NV902D_SET_DST_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NV902D_SET_DST_FORMAT_V_RF16_GF16 0x000000DE +#define NV902D_SET_DST_FORMAT_V_R16_G16 0x000000DA +#define NV902D_SET_DST_FORMAT_V_RN16_GN16 0x000000DB +#define NV902D_SET_DST_FORMAT_V_G8R8 0x000000EA +#define NV902D_SET_DST_FORMAT_V_GN8RN8 0x000000EB +#define NV902D_SET_DST_FORMAT_V_RN16 0x000000EF +#define NV902D_SET_DST_FORMAT_V_RN8 0x000000F4 +#define NV902D_SET_DST_FORMAT_V_A8 0x000000F7 + +#define NV902D_SET_DST_MEMORY_LAYOUT 0x0204 +#define NV902D_SET_DST_MEMORY_LAYOUT_V 0:0 +#define NV902D_SET_DST_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000 +#define NV902D_SET_DST_MEMORY_LAYOUT_V_PITCH 0x00000001 + +#define NV902D_SET_DST_BLOCK_SIZE 0x0208 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT 6:4 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH 10:8 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NV902D_SET_DST_DEPTH 0x020c +#define NV902D_SET_DST_DEPTH_V 31:0 + +#define NV902D_SET_DST_LAYER 0x0210 +#define NV902D_SET_DST_LAYER_V 31:0 + +#define NV902D_SET_DST_PITCH 0x0214 +#define NV902D_SET_DST_PITCH_V 31:0 + +#define NV902D_SET_DST_WIDTH 0x0218 +#define NV902D_SET_DST_WIDTH_V 31:0 + +#define NV902D_SET_DST_HEIGHT 0x021c +#define NV902D_SET_DST_HEIGHT_V 31:0 + +#define NV902D_SET_DST_OFFSET_UPPER 0x0220 +#define NV902D_SET_DST_OFFSET_UPPER_V 7:0 + +#define NV902D_SET_DST_OFFSET_LOWER 0x0224 +#define NV902D_SET_DST_OFFSET_LOWER_V 31:0 + +#define NV902D_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x0228 +#define NV902D_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NV902D_SET_SPARE_NOOP06 0x022c +#define NV902D_SET_SPARE_NOOP06_V 31:0 + +#define NV902D_SET_SRC_FORMAT 0x0230 +#define NV902D_SET_SRC_FORMAT_V 7:0 +#define NV902D_SET_SRC_FORMAT_V_A8R8G8B8 0x000000CF +#define NV902D_SET_SRC_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NV902D_SET_SRC_FORMAT_V_A2R10G10B10 0x000000DF +#define NV902D_SET_SRC_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV902D_SET_SRC_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NV902D_SET_SRC_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV902D_SET_SRC_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV902D_SET_SRC_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NV902D_SET_SRC_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV902D_SET_SRC_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NV902D_SET_SRC_FORMAT_V_R5G6B5 0x000000E8 +#define NV902D_SET_SRC_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV902D_SET_SRC_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV902D_SET_SRC_FORMAT_V_Y8 0x000000F3 +#define NV902D_SET_SRC_FORMAT_V_AY8 0x0000001D +#define NV902D_SET_SRC_FORMAT_V_Y16 0x000000EE +#define NV902D_SET_SRC_FORMAT_V_Y32 0x000000FF +#define NV902D_SET_SRC_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV902D_SET_SRC_FORMAT_V_O1R5G5B5 0x000000FC +#define NV902D_SET_SRC_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV902D_SET_SRC_FORMAT_V_O8R8G8B8 0x000000FE +#define NV902D_SET_SRC_FORMAT_V_Y1_8X8 0x0000001C +#define NV902D_SET_SRC_FORMAT_V_RF16 0x000000F2 +#define NV902D_SET_SRC_FORMAT_V_RF32 0x000000E5 +#define NV902D_SET_SRC_FORMAT_V_RF32_GF32 0x000000CB +#define NV902D_SET_SRC_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NV902D_SET_SRC_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NV902D_SET_SRC_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NV902D_SET_SRC_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NV902D_SET_SRC_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NV902D_SET_SRC_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NV902D_SET_SRC_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NV902D_SET_SRC_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NV902D_SET_SRC_FORMAT_V_RF16_GF16 0x000000DE +#define NV902D_SET_SRC_FORMAT_V_R16_G16 0x000000DA +#define NV902D_SET_SRC_FORMAT_V_RN16_GN16 0x000000DB +#define NV902D_SET_SRC_FORMAT_V_G8R8 0x000000EA +#define NV902D_SET_SRC_FORMAT_V_GN8RN8 0x000000EB +#define NV902D_SET_SRC_FORMAT_V_RN16 0x000000EF +#define NV902D_SET_SRC_FORMAT_V_RN8 0x000000F4 +#define NV902D_SET_SRC_FORMAT_V_A8 0x000000F7 + +#define NV902D_SET_SRC_MEMORY_LAYOUT 0x0234 +#define NV902D_SET_SRC_MEMORY_LAYOUT_V 0:0 +#define NV902D_SET_SRC_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000 +#define NV902D_SET_SRC_MEMORY_LAYOUT_V_PITCH 0x00000001 + +#define NV902D_SET_SRC_BLOCK_SIZE 0x0238 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT 6:4 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH 10:8 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NV902D_SET_SRC_DEPTH 0x023c +#define NV902D_SET_SRC_DEPTH_V 31:0 + +#define NV902D_TWOD_INVALIDATE_TEXTURE_DATA_CACHE 0x0240 +#define NV902D_TWOD_INVALIDATE_TEXTURE_DATA_CACHE_V 1:0 +#define NV902D_TWOD_INVALIDATE_TEXTURE_DATA_CACHE_V_L1_ONLY 0x00000000 +#define NV902D_TWOD_INVALIDATE_TEXTURE_DATA_CACHE_V_L2_ONLY 0x00000001 +#define NV902D_TWOD_INVALIDATE_TEXTURE_DATA_CACHE_V_L1_AND_L2 0x00000002 + +#define NV902D_SET_SRC_PITCH 0x0244 +#define NV902D_SET_SRC_PITCH_V 31:0 + +#define NV902D_SET_SRC_WIDTH 0x0248 +#define NV902D_SET_SRC_WIDTH_V 31:0 + +#define NV902D_SET_SRC_HEIGHT 0x024c +#define NV902D_SET_SRC_HEIGHT_V 31:0 + +#define NV902D_SET_SRC_OFFSET_UPPER 0x0250 +#define NV902D_SET_SRC_OFFSET_UPPER_V 7:0 + +#define NV902D_SET_SRC_OFFSET_LOWER 0x0254 +#define NV902D_SET_SRC_OFFSET_LOWER_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION 0x0258 +#define NV902D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V 1:0 +#define NV902D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V_NO_PROMOTION 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V_PROMOTE_TO_2_V 0x00000001 +#define NV902D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V_PROMOTE_TO_2_H 0x00000002 +#define NV902D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V_PROMOTE_TO_4 0x00000003 + +#define NV902D_SET_SPARE_NOOP12 0x025c +#define NV902D_SET_SPARE_NOOP12_V 31:0 + +#define NV902D_SET_NUM_PROCESSING_CLUSTERS 0x0260 +#define NV902D_SET_NUM_PROCESSING_CLUSTERS_V 0:0 +#define NV902D_SET_NUM_PROCESSING_CLUSTERS_V_ALL 0x00000000 +#define NV902D_SET_NUM_PROCESSING_CLUSTERS_V_ONE 0x00000001 + +#define NV902D_SET_RENDER_ENABLE_A 0x0264 +#define NV902D_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV902D_SET_RENDER_ENABLE_B 0x0268 +#define NV902D_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV902D_SET_RENDER_ENABLE_C 0x026c +#define NV902D_SET_RENDER_ENABLE_C_MODE 2:0 +#define NV902D_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV902D_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV902D_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV902D_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV902D_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV902D_SET_SPARE_NOOP08 0x0270 +#define NV902D_SET_SPARE_NOOP08_V 31:0 + +#define NV902D_SET_SPARE_NOOP01 0x0274 +#define NV902D_SET_SPARE_NOOP01_V 31:0 + +#define NV902D_SET_SPARE_NOOP11 0x0278 +#define NV902D_SET_SPARE_NOOP11_V 31:0 + +#define NV902D_SET_SPARE_NOOP07 0x027c +#define NV902D_SET_SPARE_NOOP07_V 31:0 + +#define NV902D_SET_CLIP_X0 0x0280 +#define NV902D_SET_CLIP_X0_V 31:0 + +#define NV902D_SET_CLIP_Y0 0x0284 +#define NV902D_SET_CLIP_Y0_V 31:0 + +#define NV902D_SET_CLIP_WIDTH 0x0288 +#define NV902D_SET_CLIP_WIDTH_V 31:0 + +#define NV902D_SET_CLIP_HEIGHT 0x028c +#define NV902D_SET_CLIP_HEIGHT_V 31:0 + +#define NV902D_SET_CLIP_ENABLE 0x0290 +#define NV902D_SET_CLIP_ENABLE_V 0:0 +#define NV902D_SET_CLIP_ENABLE_V_FALSE 0x00000000 +#define NV902D_SET_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NV902D_SET_COLOR_KEY_FORMAT 0x0294 +#define NV902D_SET_COLOR_KEY_FORMAT_V 2:0 +#define NV902D_SET_COLOR_KEY_FORMAT_V_A16R5G6B5 0x00000000 +#define NV902D_SET_COLOR_KEY_FORMAT_V_A1R5G5B5 0x00000001 +#define NV902D_SET_COLOR_KEY_FORMAT_V_A8R8G8B8 0x00000002 +#define NV902D_SET_COLOR_KEY_FORMAT_V_A2R10G10B10 0x00000003 +#define NV902D_SET_COLOR_KEY_FORMAT_V_Y8 0x00000004 +#define NV902D_SET_COLOR_KEY_FORMAT_V_Y16 0x00000005 +#define NV902D_SET_COLOR_KEY_FORMAT_V_Y32 0x00000006 + +#define NV902D_SET_COLOR_KEY 0x0298 +#define NV902D_SET_COLOR_KEY_V 31:0 + +#define NV902D_SET_COLOR_KEY_ENABLE 0x029c +#define NV902D_SET_COLOR_KEY_ENABLE_V 0:0 +#define NV902D_SET_COLOR_KEY_ENABLE_V_FALSE 0x00000000 +#define NV902D_SET_COLOR_KEY_ENABLE_V_TRUE 0x00000001 + +#define NV902D_SET_ROP 0x02a0 +#define NV902D_SET_ROP_V 7:0 + +#define NV902D_SET_BETA1 0x02a4 +#define NV902D_SET_BETA1_V 31:0 + +#define NV902D_SET_BETA4 0x02a8 +#define NV902D_SET_BETA4_B 7:0 +#define NV902D_SET_BETA4_G 15:8 +#define NV902D_SET_BETA4_R 23:16 +#define NV902D_SET_BETA4_A 31:24 + +#define NV902D_SET_OPERATION 0x02ac +#define NV902D_SET_OPERATION_V 2:0 +#define NV902D_SET_OPERATION_V_SRCCOPY_AND 0x00000000 +#define NV902D_SET_OPERATION_V_ROP_AND 0x00000001 +#define NV902D_SET_OPERATION_V_BLEND_AND 0x00000002 +#define NV902D_SET_OPERATION_V_SRCCOPY 0x00000003 +#define NV902D_SET_OPERATION_V_ROP 0x00000004 +#define NV902D_SET_OPERATION_V_SRCCOPY_PREMULT 0x00000005 +#define NV902D_SET_OPERATION_V_BLEND_PREMULT 0x00000006 + +#define NV902D_SET_PATTERN_OFFSET 0x02b0 +#define NV902D_SET_PATTERN_OFFSET_X 5:0 +#define NV902D_SET_PATTERN_OFFSET_Y 13:8 + +#define NV902D_SET_PATTERN_SELECT 0x02b4 +#define NV902D_SET_PATTERN_SELECT_V 1:0 +#define NV902D_SET_PATTERN_SELECT_V_MONOCHROME_8x8 0x00000000 +#define NV902D_SET_PATTERN_SELECT_V_MONOCHROME_64x1 0x00000001 +#define NV902D_SET_PATTERN_SELECT_V_MONOCHROME_1x64 0x00000002 +#define NV902D_SET_PATTERN_SELECT_V_COLOR 0x00000003 + +#define NV902D_SET_DST_COLOR_RENDER_TO_ZETA_SURFACE 0x02b8 +#define NV902D_SET_DST_COLOR_RENDER_TO_ZETA_SURFACE_V 0:0 +#define NV902D_SET_DST_COLOR_RENDER_TO_ZETA_SURFACE_V_FALSE 0x00000000 +#define NV902D_SET_DST_COLOR_RENDER_TO_ZETA_SURFACE_V_TRUE 0x00000001 + +#define NV902D_SET_SPARE_NOOP04 0x02bc +#define NV902D_SET_SPARE_NOOP04_V 31:0 + +#define NV902D_SET_SPARE_NOOP15 0x02c0 +#define NV902D_SET_SPARE_NOOP15_V 31:0 + +#define NV902D_SET_SPARE_NOOP13 0x02c4 +#define NV902D_SET_SPARE_NOOP13_V 31:0 + +#define NV902D_SET_SPARE_NOOP03 0x02c8 +#define NV902D_SET_SPARE_NOOP03_V 31:0 + +#define NV902D_SET_SPARE_NOOP14 0x02cc +#define NV902D_SET_SPARE_NOOP14_V 31:0 + +#define NV902D_SET_SPARE_NOOP02 0x02d0 +#define NV902D_SET_SPARE_NOOP02_V 31:0 + +#define NV902D_SET_COMPRESSION 0x02d4 +#define NV902D_SET_COMPRESSION_ENABLE 0:0 +#define NV902D_SET_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NV902D_SET_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NV902D_SET_SPARE_NOOP09 0x02d8 +#define NV902D_SET_SPARE_NOOP09_V 31:0 + +#define NV902D_SET_RENDER_ENABLE_OVERRIDE 0x02dc +#define NV902D_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NV902D_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NV902D_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NV902D_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION 0x02e0 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_HORIZONTAL 1:0 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_HORIZONTAL_HW_DECIDES 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_HORIZONTAL_LEFT_TO_RIGHT 0x00000001 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_HORIZONTAL_RIGHT_TO_LEFT 0x00000002 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_VERTICAL 5:4 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_VERTICAL_HW_DECIDES 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_VERTICAL_TOP_TO_BOTTOM 0x00000001 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_VERTICAL_BOTTOM_TO_TOP 0x00000002 + +#define NV902D_SET_SPARE_NOOP10 0x02e4 +#define NV902D_SET_SPARE_NOOP10_V 31:0 + +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT 0x02e8 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V 2:0 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8X8R5G6B5 0x00000000 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A1R5G5B5 0x00000001 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8R8G8B8 0x00000002 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8Y8 0x00000003 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8X8Y16 0x00000004 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_Y32 0x00000005 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_BYTE_EXPAND 0x00000006 + +#define NV902D_SET_MONOCHROME_PATTERN_FORMAT 0x02ec +#define NV902D_SET_MONOCHROME_PATTERN_FORMAT_V 0:0 +#define NV902D_SET_MONOCHROME_PATTERN_FORMAT_V_CGA6_M1 0x00000000 +#define NV902D_SET_MONOCHROME_PATTERN_FORMAT_V_LE_M1 0x00000001 + +#define NV902D_SET_MONOCHROME_PATTERN_COLOR0 0x02f0 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR0_V 31:0 + +#define NV902D_SET_MONOCHROME_PATTERN_COLOR1 0x02f4 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR1_V 31:0 + +#define NV902D_SET_MONOCHROME_PATTERN0 0x02f8 +#define NV902D_SET_MONOCHROME_PATTERN0_V 31:0 + +#define NV902D_SET_MONOCHROME_PATTERN1 0x02fc +#define NV902D_SET_MONOCHROME_PATTERN1_V 31:0 + +#define NV902D_COLOR_PATTERN_X8R8G8B8(i) (0x0300+(i)*4) +#define NV902D_COLOR_PATTERN_X8R8G8B8_B0 7:0 +#define NV902D_COLOR_PATTERN_X8R8G8B8_G0 15:8 +#define NV902D_COLOR_PATTERN_X8R8G8B8_R0 23:16 +#define NV902D_COLOR_PATTERN_X8R8G8B8_IGNORE0 31:24 + +#define NV902D_COLOR_PATTERN_R5G6B5(i) (0x0400+(i)*4) +#define NV902D_COLOR_PATTERN_R5G6B5_B0 4:0 +#define NV902D_COLOR_PATTERN_R5G6B5_G0 10:5 +#define NV902D_COLOR_PATTERN_R5G6B5_R0 15:11 +#define NV902D_COLOR_PATTERN_R5G6B5_B1 20:16 +#define NV902D_COLOR_PATTERN_R5G6B5_G1 26:21 +#define NV902D_COLOR_PATTERN_R5G6B5_R1 31:27 + +#define NV902D_COLOR_PATTERN_X1R5G5B5(i) (0x0480+(i)*4) +#define NV902D_COLOR_PATTERN_X1R5G5B5_B0 4:0 +#define NV902D_COLOR_PATTERN_X1R5G5B5_G0 9:5 +#define NV902D_COLOR_PATTERN_X1R5G5B5_R0 14:10 +#define NV902D_COLOR_PATTERN_X1R5G5B5_IGNORE0 15:15 +#define NV902D_COLOR_PATTERN_X1R5G5B5_B1 20:16 +#define NV902D_COLOR_PATTERN_X1R5G5B5_G1 25:21 +#define NV902D_COLOR_PATTERN_X1R5G5B5_R1 30:26 +#define NV902D_COLOR_PATTERN_X1R5G5B5_IGNORE1 31:31 + +#define NV902D_COLOR_PATTERN_Y8(i) (0x0500+(i)*4) +#define NV902D_COLOR_PATTERN_Y8_Y0 7:0 +#define NV902D_COLOR_PATTERN_Y8_Y1 15:8 +#define NV902D_COLOR_PATTERN_Y8_Y2 23:16 +#define NV902D_COLOR_PATTERN_Y8_Y3 31:24 + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR0 0x0540 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR0_V 31:0 + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR1 0x0544 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR1_V 31:0 + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR2 0x0548 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR2_V 31:0 + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR3 0x054c +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR3_V 31:0 + +#define NV902D_SET_MME_MEM_ADDRESS_A 0x0550 +#define NV902D_SET_MME_MEM_ADDRESS_A_UPPER 24:0 + +#define NV902D_SET_MME_MEM_ADDRESS_B 0x0554 +#define NV902D_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NV902D_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NV902D_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NV902D_MME_DMA_READ 0x055c +#define NV902D_MME_DMA_READ_LENGTH 31:0 + +#define NV902D_MME_DMA_READ_FIFOED 0x0560 +#define NV902D_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NV902D_MME_DMA_WRITE 0x0564 +#define NV902D_MME_DMA_WRITE_LENGTH 31:0 + +#define NV902D_MME_DMA_REDUCTION 0x0568 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NV902D_MME_DMA_SYSMEMBAR 0x056c +#define NV902D_MME_DMA_SYSMEMBAR_V 0:0 + +#define NV902D_MME_DMA_SYNC 0x0570 +#define NV902D_MME_DMA_SYNC_VALUE 31:0 + +#define NV902D_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NV902D_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NV902D_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NV902D_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NV902D_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NV902D_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NV902D_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NV902D_RENDER_SOLID_PRIM_MODE 0x0580 +#define NV902D_RENDER_SOLID_PRIM_MODE_V 2:0 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_POINTS 0x00000000 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_LINES 0x00000001 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_POLYLINE 0x00000002 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_TRIANGLES 0x00000003 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_RECTS 0x00000004 + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT 0x0584 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V 7:0 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_RF32_GF32 0x000000CB +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A8R8G8B8 0x000000CF +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A2R10G10B10 0x000000DF +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_R5G6B5 0x000000E8 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y8 0x000000F3 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y16 0x000000EE +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y32 0x000000FF +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_O1R5G5B5 0x000000FC +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_O8R8G8B8 0x000000FE + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR 0x0588 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_V 31:0 + +#define NV902D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS 0x058c +#define NV902D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS_XMAJ__XINC__YINC 0:0 +#define NV902D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS_XMAJ__XDEC__YINC 4:4 +#define NV902D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS_YMAJ__XINC__YINC 8:8 +#define NV902D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS_YMAJ__XDEC__YINC 12:12 + +#define NV902D_RENDER_SOLID_PRIM_POINT_X_Y 0x05e0 +#define NV902D_RENDER_SOLID_PRIM_POINT_X_Y_X 15:0 +#define NV902D_RENDER_SOLID_PRIM_POINT_X_Y_Y 31:16 + +#define NV902D_RENDER_SOLID_PRIM_POINT_SET_X(j) (0x0600+(j)*8) +#define NV902D_RENDER_SOLID_PRIM_POINT_SET_X_V 31:0 + +#define NV902D_RENDER_SOLID_PRIM_POINT_Y(j) (0x0604+(j)*8) +#define NV902D_RENDER_SOLID_PRIM_POINT_Y_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE 0x0800 +#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE_V 0:0 +#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE_V_COLOR 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE_V_INDEX 0x00000001 + +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT 0x0804 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V 7:0 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A8R8G8B8 0x000000CF +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A2R10G10B10 0x000000DF +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_R5G6B5 0x000000E8 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y8 0x000000F3 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y16 0x000000EE +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y32 0x000000FF +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_O1R5G5B5 0x000000FC +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_O8R8G8B8 0x000000FE + +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT 0x0808 +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V 1:0 +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I1 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I4 0x00000001 +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I8 0x00000002 + +#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT 0x080c +#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V 0:0 +#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V_CGA6_M1 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V_LE_M1 0x00000001 + +#define NV902D_SET_PIXELS_FROM_CPU_WRAP 0x0810 +#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V 1:0 +#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_PIXEL 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_BYTE 0x00000001 +#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_DWORD 0x00000002 + +#define NV902D_SET_PIXELS_FROM_CPU_COLOR0 0x0814 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR0_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_COLOR1 0x0818 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR1_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY 0x081c +#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V 0:0 +#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V_TRANSPARENT 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V_OPAQUE 0x00000001 + +#define NV902D_SET_PIXELS_FROM_CPU_SRC_WIDTH 0x0838 +#define NV902D_SET_PIXELS_FROM_CPU_SRC_WIDTH_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_SRC_HEIGHT 0x083c +#define NV902D_SET_PIXELS_FROM_CPU_SRC_HEIGHT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_FRAC 0x0840 +#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_INT 0x0844 +#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_FRAC 0x0848 +#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_INT 0x084c +#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_FRAC 0x0850 +#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_INT 0x0854 +#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_FRAC 0x0858 +#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_INT 0x085c +#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_INT_V 31:0 + +#define NV902D_PIXELS_FROM_CPU_DATA 0x0860 +#define NV902D_PIXELS_FROM_CPU_DATA_V 31:0 + +#define NV902D_SET_BIG_ENDIAN_CONTROL 0x0870 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X32_SWAP_1 0:0 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X32_SWAP_4 1:1 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X32_SWAP_8 2:2 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X32_SWAP_16 3:3 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X16_SWAP_1 4:4 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X16_SWAP_4 5:5 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X16_SWAP_8 6:6 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X16_SWAP_16 7:7 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X8_SWAP_1 8:8 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X8_SWAP_4 9:9 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X8_SWAP_8 10:10 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X8_SWAP_16 11:11 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_CGA6_SWAP_1 12:12 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_CGA6_SWAP_4 13:13 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_CGA6_SWAP_8 14:14 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_CGA6_SWAP_16 15:15 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_LE_SWAP_1 16:16 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_LE_SWAP_4 17:17 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_LE_SWAP_8 18:18 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_LE_SWAP_16 19:19 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I4_SWAP_1 20:20 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I4_SWAP_4 21:21 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I4_SWAP_8 22:22 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I4_SWAP_16 23:23 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I8_SWAP_1 24:24 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I8_SWAP_4 25:25 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I8_SWAP_8 26:26 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I8_SWAP_16 27:27 +#define NV902D_SET_BIG_ENDIAN_CONTROL_OVERRIDE 28:28 + +#define NV902D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE 0x0880 +#define NV902D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE_V 2:0 +#define NV902D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE_V_AUTO 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE_V_SHAPE_8X8 0x00000001 +#define NV902D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE_V_SHAPE_16X4 0x00000002 + +#define NV902D_SET_PIXELS_FROM_MEMORY_CORRAL_SIZE 0x0884 +#define NV902D_SET_PIXELS_FROM_MEMORY_CORRAL_SIZE_V 9:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP 0x0888 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V 0:0 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V_FALSE 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V_TRUE 0x00000001 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE 0x088c +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_ORIGIN 0:0 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_ORIGIN_CENTER 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_ORIGIN_CORNER 0x00000001 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_FILTER 4:4 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_FILTER_POINT 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_FILTER_BILINEAR 0x00000001 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_X0 0x08b0 +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_X0_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_Y0 0x08b4 +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_Y0_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_WIDTH 0x08b8 +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_WIDTH_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_HEIGHT 0x08bc +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_HEIGHT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_FRAC 0x08c0 +#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_INT 0x08c4 +#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_FRAC 0x08c8 +#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_INT 0x08cc +#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC 0x08d0 +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_INT 0x08d4 +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC 0x08d8 +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC_V 31:0 + +#define NV902D_PIXELS_FROM_MEMORY_SRC_Y0_INT 0x08dc +#define NV902D_PIXELS_FROM_MEMORY_SRC_Y0_INT_V 31:0 + +#define NV902D_SET_FALCON00 0x08e0 +#define NV902D_SET_FALCON00_V 31:0 + +#define NV902D_SET_FALCON01 0x08e4 +#define NV902D_SET_FALCON01_V 31:0 + +#define NV902D_SET_FALCON02 0x08e8 +#define NV902D_SET_FALCON02_V 31:0 + +#define NV902D_SET_FALCON03 0x08ec +#define NV902D_SET_FALCON03_V 31:0 + +#define NV902D_SET_FALCON04 0x08f0 +#define NV902D_SET_FALCON04_V 31:0 + +#define NV902D_SET_FALCON05 0x08f4 +#define NV902D_SET_FALCON05_V 31:0 + +#define NV902D_SET_FALCON06 0x08f8 +#define NV902D_SET_FALCON06_V 31:0 + +#define NV902D_SET_FALCON07 0x08fc +#define NV902D_SET_FALCON07_V 31:0 + +#define NV902D_SET_FALCON08 0x0900 +#define NV902D_SET_FALCON08_V 31:0 + +#define NV902D_SET_FALCON09 0x0904 +#define NV902D_SET_FALCON09_V 31:0 + +#define NV902D_SET_FALCON10 0x0908 +#define NV902D_SET_FALCON10_V 31:0 + +#define NV902D_SET_FALCON11 0x090c +#define NV902D_SET_FALCON11_V 31:0 + +#define NV902D_SET_FALCON12 0x0910 +#define NV902D_SET_FALCON12_V 31:0 + +#define NV902D_SET_FALCON13 0x0914 +#define NV902D_SET_FALCON13_V 31:0 + +#define NV902D_SET_FALCON14 0x0918 +#define NV902D_SET_FALCON14_V 31:0 + +#define NV902D_SET_FALCON15 0x091c +#define NV902D_SET_FALCON15_V 31:0 + +#define NV902D_SET_FALCON16 0x0920 +#define NV902D_SET_FALCON16_V 31:0 + +#define NV902D_SET_FALCON17 0x0924 +#define NV902D_SET_FALCON17_V 31:0 + +#define NV902D_SET_FALCON18 0x0928 +#define NV902D_SET_FALCON18_V 31:0 + +#define NV902D_SET_FALCON19 0x092c +#define NV902D_SET_FALCON19_V 31:0 + +#define NV902D_SET_FALCON20 0x0930 +#define NV902D_SET_FALCON20_V 31:0 + +#define NV902D_SET_FALCON21 0x0934 +#define NV902D_SET_FALCON21_V 31:0 + +#define NV902D_SET_FALCON22 0x0938 +#define NV902D_SET_FALCON22_V 31:0 + +#define NV902D_SET_FALCON23 0x093c +#define NV902D_SET_FALCON23_V 31:0 + +#define NV902D_SET_FALCON24 0x0940 +#define NV902D_SET_FALCON24_V 31:0 + +#define NV902D_SET_FALCON25 0x0944 +#define NV902D_SET_FALCON25_V 31:0 + +#define NV902D_SET_FALCON26 0x0948 +#define NV902D_SET_FALCON26_V 31:0 + +#define NV902D_SET_FALCON27 0x094c +#define NV902D_SET_FALCON27_V 31:0 + +#define NV902D_SET_FALCON28 0x0950 +#define NV902D_SET_FALCON28_V 31:0 + +#define NV902D_SET_FALCON29 0x0954 +#define NV902D_SET_FALCON29_V 31:0 + +#define NV902D_SET_FALCON30 0x0958 +#define NV902D_SET_FALCON30_V 31:0 + +#define NV902D_SET_FALCON31 0x095c +#define NV902D_SET_FALCON31_V 31:0 + +#define NV902D_MME_DMA_WRITE_METHOD_BARRIER 0x0dec +#define NV902D_MME_DMA_WRITE_METHOD_BARRIER_V 0:0 + +#define NV902D_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NV902D_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NV902D_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NV902D_CALL_MME_MACRO_V 31:0 + +#define NV902D_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NV902D_CALL_MME_DATA_V 31:0 + +#endif /* _cl_fermi_twod_a_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl9067.h b/userspace/sdks/nv525/nvidia/inc/class/cl9067.h new file mode 100644 index 0000000..5355f18 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl9067.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _cl9067_h_ +#define _cl9067_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define FERMI_CONTEXT_SHARE_A (0x00009067) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl9067_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl906f.h b/userspace/sdks/nv525/nvidia/inc/class/cl906f.h new file mode 100644 index 0000000..b20d8ff --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl906f.h @@ -0,0 +1,242 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl906f_h_ +#define _cl906f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class GF100_CHANNEL_GPFIFO */ +/* + * Documentation for GF100_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + */ +#define GF100_CHANNEL_GPFIFO (0x0000906F) + +/* pio method data structure */ +typedef volatile struct _cl906f_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv906fTypedef, GF100ChannelGPFifo; +#define NV906F_TYPEDEF GF100ChannelGPFifo +/* dma flow control data structure */ +typedef volatile struct _cl906f_tag1 { + NvU32 Ignored00[0x010]; /* 0000-0043*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 SetReferenceThreshold; /* set reference value threshold 0050-0053*/ + NvU32 Ignored01[0x001]; /* 0054-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x3dc]; +} Nv906fControl, GF100ControlGPFifo; +/* fields and values */ +#define NV906F_NUMBER_OF_SUBCHANNELS (8) +#define NV906F_SET_OBJECT (0x00000000) +#define NV906F_SET_OBJECT_NVCLASS 15:0 +#define NV906F_SET_OBJECT_ENGINE 20:16 +#define NV906F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NV906F_ILLEGAL (0x00000004) +#define NV906F_ILLEGAL_HANDLE 31:0 +#define NV906F_NOP (0x00000008) +#define NV906F_NOP_HANDLE 31:0 +#define NV906F_SEMAPHOREA (0x00000010) +#define NV906F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NV906F_SEMAPHOREB (0x00000014) +#define NV906F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NV906F_SEMAPHOREC (0x00000018) +#define NV906F_SEMAPHOREC_PAYLOAD 31:0 +#define NV906F_SEMAPHORED (0x0000001C) +#define NV906F_SEMAPHORED_OPERATION 3:0 +#define NV906F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NV906F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NV906F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NV906F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NV906F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NV906F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NV906F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NV906F_SEMAPHORED_RELEASE_WFI 20:20 +#define NV906F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NV906F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NV906F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NV906F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NV906F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NV906F_NON_STALL_INTERRUPT (0x00000020) +#define NV906F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NV906F_FB_FLUSH (0x00000024) +#define NV906F_FB_FLUSH_HANDLE 31:0 +#define NV906F_MEM_OP_A (0x00000028) +#define NV906F_MEM_OP_A_OPERAND_LOW 31:2 +#define NV906F_MEM_OP_A_TLB_INVALIDATE_ADDR 29:2 +#define NV906F_MEM_OP_A_TLB_INVALIDATE_TARGET 31:30 +#define NV906F_MEM_OP_A_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000 +#define NV906F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002 +#define NV906F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 +#define NV906F_MEM_OP_B (0x0000002c) +#define NV906F_MEM_OP_B_OPERAND_HIGH 7:0 +#define NV906F_MEM_OP_B_OPERATION 31:27 +#define NV906F_MEM_OP_B_OPERATION_SYSMEMBAR_FLUSH 0x00000005 +#define NV906F_MEM_OP_B_OPERATION_SOFT_FLUSH 0x00000006 +#define NV906F_MEM_OP_B_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NV906F_MEM_OP_B_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NV906F_MEM_OP_B_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +#define NV906F_MEM_OP_B_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NV906F_MEM_OP_B_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB 0:0 +#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ALL 0x00000001 +#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC 1:1 +#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NV906F_SET_REFERENCE (0x00000050) +#define NV906F_SET_REFERENCE_COUNT 31:0 +#define NV906F_CRC_CHECK (0x0000007c) +#define NV906F_CRC_CHECK_VALUE 31:0 +#define NV906F_YIELD (0x00000080) +#define NV906F_YIELD_OP 1:0 +#define NV906F_YIELD_OP_NOP 0x00000000 + +/* GPFIFO entry format */ +#define NV906F_GP_ENTRY__SIZE 8 +#define NV906F_GP_ENTRY0_FETCH 0:0 +#define NV906F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NV906F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NV906F_GP_ENTRY0_NO_CONTEXT_SWITCH 1:1 +#define NV906F_GP_ENTRY0_NO_CONTEXT_SWITCH_FALSE 0x00000000 +#define NV906F_GP_ENTRY0_NO_CONTEXT_SWITCH_TRUE 0x00000001 +#define NV906F_GP_ENTRY0_GET 31:2 +#define NV906F_GP_ENTRY0_OPERAND 31:0 +#define NV906F_GP_ENTRY1_GET_HI 7:0 +#define NV906F_GP_ENTRY1_PRIV 8:8 +#define NV906F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NV906F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NV906F_GP_ENTRY1_LEVEL 9:9 +#define NV906F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NV906F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NV906F_GP_ENTRY1_LENGTH 30:10 +#define NV906F_GP_ENTRY1_SYNC 31:31 +#define NV906F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NV906F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NV906F_GP_ENTRY1_OPCODE 7:0 +#define NV906F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NV906F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NV906F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NV906F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NV906F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NV906F_DMA_METHOD_ADDRESS 11:0 +#define NV906F_DMA_SUBDEVICE_MASK 15:4 +#define NV906F_DMA_METHOD_SUBCHANNEL 15:13 +#define NV906F_DMA_TERT_OP 17:16 +#define NV906F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NV906F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NV906F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NV906F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NV906F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NV906F_DMA_METHOD_COUNT_OLD 28:18 +#define NV906F_DMA_METHOD_COUNT 28:16 +#define NV906F_DMA_IMMD_DATA 28:16 +#define NV906F_DMA_SEC_OP 31:29 +#define NV906F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NV906F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NV906F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NV906F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NV906F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NV906F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NV906F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NV906F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NV906F_DMA_INCR_ADDRESS 11:0 +#define NV906F_DMA_INCR_SUBCHANNEL 15:13 +#define NV906F_DMA_INCR_COUNT 28:16 +#define NV906F_DMA_INCR_OPCODE 31:29 +#define NV906F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NV906F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NV906F_DMA_NONINCR_ADDRESS 11:0 +#define NV906F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NV906F_DMA_NONINCR_COUNT 28:16 +#define NV906F_DMA_NONINCR_OPCODE 31:29 +#define NV906F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NV906F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NV906F_DMA_ONEINCR_ADDRESS 11:0 +#define NV906F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NV906F_DMA_ONEINCR_COUNT 28:16 +#define NV906F_DMA_ONEINCR_OPCODE 31:29 +#define NV906F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NV906F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NV906F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NV906F_DMA_IMMD_ADDRESS 11:0 +#define NV906F_DMA_IMMD_SUBCHANNEL 15:13 +#define NV906F_DMA_IMMD_DATA 28:16 +#define NV906F_DMA_IMMD_OPCODE 31:29 +#define NV906F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NV906F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NV906F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NV906F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NV906F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NV906F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NV906F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NV906F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NV906F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NV906F_DMA_ENDSEG_OPCODE 31:29 +#define NV906F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NV906F_DMA_ADDRESS 12:2 +#define NV906F_DMA_SUBCH 15:13 +#define NV906F_DMA_OPCODE3 17:16 +#define NV906F_DMA_OPCODE3_NONE (0x00000000) +#define NV906F_DMA_COUNT 28:18 +#define NV906F_DMA_OPCODE 31:29 +#define NV906F_DMA_OPCODE_METHOD (0x00000000) +#define NV906F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NV906F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl906f_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl906fsw.h b/userspace/sdks/nv525/nvidia/inc/class/cl906fsw.h new file mode 100644 index 0000000..465a91a --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl906fsw.h @@ -0,0 +1,42 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl906f_sw_h_ +#define _cl906f_sw_h_ + +/* NvNotification[] elements */ +#define NV906F_NOTIFIERS_RC (0) +#define NV906F_NOTIFIERS_REFCNT (1) +#define NV906F_NOTIFIERS_NONSTALL (2) +#define NV906F_NOTIFIERS_EVENTBUFFER (3) +#define NV906F_NOTIFIERS_IDLECHANNEL (4) +#define NV906F_NOTIFIERS_ENDCTX (5) +#define NV906F_NOTIFIERS_SW (6) +#define NV906F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NV906F_NOTIFIERS_MAXCOUNT (8) + +/* NvNotification[] fields and values */ +#define NV906f_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NV906f_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _cl906f_sw_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl9072.h b/userspace/sdks/nv525/nvidia/inc/class/cl9072.h new file mode 100644 index 0000000..61e134a --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl9072.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9072.finn +// + +#include "cl9072_notification.h" + +#define GF100_DISP_SW (0x9072U) /* finn: Evaluated from "NV9072_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV9072_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9072U) + +typedef struct NV9072_ALLOCATION_PARAMETERS { + NvU32 logicalHeadId; + /* + * 0 implies use Head argument only (i.e. whatever is currently setup on this head) + */ + NvU32 displayMask; + NvU32 caps; +} NV9072_ALLOCATION_PARAMETERS; diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl9072_notification.h b/userspace/sdks/nv525/nvidia/inc/class/cl9072_notification.h new file mode 100644 index 0000000..21b48f8 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl9072_notification.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl9072_notification_h_ +#define _cl9072_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV9072_NOTIFIERS_NOTIFY_ON_VBLANK (9) +#define NV9072_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl9072_notification_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl9074.h b/userspace/sdks/nv525/nvidia/inc/class/cl9074.h new file mode 100644 index 0000000..60436ba --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl9074.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl9074_h_ +#define _cl9074_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define GF100_TIMED_SEMAPHORE_SW (0x00009074) + +/* NvNotification[] fields and values */ +#define NV9074_NOTIFICATION_STATUS_PENDING (0x8000) +#define NV9074_NOTIFICATION_STATUS_DONE_FLUSHED (0x0001) +#define NV9074_NOTIFICATION_STATUS_DONE (0x0000) + +#define NV9074_SET_NOTIFIER_HI_V 7:0 + +#define NV9074_SET_SEMAPHORE_HI_V 7:0 + +#define NV9074_SCHEDULE_SEMAPHORE_RELEASE_NOTIFY 1:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl9074_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl907dswspare.h b/userspace/sdks/nv525/nvidia/inc/class/cl907dswspare.h new file mode 100644 index 0000000..ee9ddaa --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl907dswspare.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl907d_sw_spare_h_ +#define _cl907d_sw_spare_h_ + +/* This file is *not* auto-generated. */ + +#define NV907D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF 1:0 +#define NV907D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF_NO_PREF (0x00000000) +#define NV907D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF_GSYNC (0x00000001) + +#define NV907D_PIOR_SET_SW_SPARE_A_CODE_FOR_LOCK_SIGNAL_PROPAGATION_ONLY 1:0 +#define NV907D_PIOR_SET_SW_SPARE_A_CODE_FOR_LOCK_SIGNAL_PROPAGATION_ONLY_FALSE (0x00000000) +#define NV907D_PIOR_SET_SW_SPARE_A_CODE_FOR_LOCK_SIGNAL_PROPAGATION_ONLY_TRUE (0x00000001) + +#endif // _cl907d_sw_spare_h_ + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl9096.h b/userspace/sdks/nv525/nvidia/inc/class/cl9096.h new file mode 100644 index 0000000..559216d --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl9096.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl9096_h_ +#define _cl9096_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define GF100_ZBC_CLEAR (0x00009096) +#define NV9096_TYPEDEF GF100ZBCClear + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl9096_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl9097.h b/userspace/sdks/nv525/nvidia/inc/class/cl9097.h new file mode 100644 index 0000000..8bc7792 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl9097.h @@ -0,0 +1,3815 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_fermi_a_h_ +#define _cl_fermi_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl fermi_a */ + +#include "nvtypes.h" + +#define FERMI_A 0x9097 + +#define NV9097_SET_OBJECT 0x0000 +#define NV9097_SET_OBJECT_CLASS_ID 15:0 +#define NV9097_SET_OBJECT_ENGINE_ID 20:16 + +#define NV9097_NO_OPERATION 0x0100 +#define NV9097_NO_OPERATION_V 31:0 + +#define NV9097_SET_NOTIFY_A 0x0104 +#define NV9097_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NV9097_SET_NOTIFY_B 0x0108 +#define NV9097_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NV9097_NOTIFY 0x010c +#define NV9097_NOTIFY_TYPE 31:0 +#define NV9097_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NV9097_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NV9097_WAIT_FOR_IDLE 0x0110 +#define NV9097_WAIT_FOR_IDLE_V 31:0 + +#define NV9097_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NV9097_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NV9097_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NV9097_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NV9097_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NV9097_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NV9097_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NV9097_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NV9097_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NV9097_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NV9097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NV9097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NV9097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NV9097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NV9097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NV9097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NV9097_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NV9097_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NV9097_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV9097_SEND_GO_IDLE 0x013c +#define NV9097_SEND_GO_IDLE_V 31:0 + +#define NV9097_PM_TRIGGER 0x0140 +#define NV9097_PM_TRIGGER_V 31:0 + +#define NV9097_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NV9097_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NV9097_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NV9097_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NV9097_RUN_DS_NOW 0x0200 +#define NV9097_RUN_DS_NOW_V 31:0 + +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NV9097_SET_RASTER_PIPE_SYNC_CONTROL 0x0208 +#define NV9097_SET_RASTER_PIPE_SYNC_CONTROL_PRIM_AREA_THRESHOLD 21:0 +#define NV9097_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE 24:24 +#define NV9097_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE_FALSE 0x00000000 +#define NV9097_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NV9097_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NV9097_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_API_MANDATED_EARLY_Z 0x0210 +#define NV9097_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NV9097_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NV9097_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_GS_DM_FIFO 0x0214 +#define NV9097_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NV9097_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NV9097_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NV9097_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NV9097_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NV9097_INVALIDATE_SHADER_CACHES 0x021c +#define NV9097_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NV9097_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NV9097_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NV9097_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NV9097_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NV9097_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NV9097_INVALIDATE_SHADER_CACHES_UNIFORM 8:8 +#define NV9097_INVALIDATE_SHADER_CACHES_UNIFORM_FALSE 0x00000000 +#define NV9097_INVALIDATE_SHADER_CACHES_UNIFORM_TRUE 0x00000001 +#define NV9097_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NV9097_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NV9097_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NV9097_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NV9097_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NV9097_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NV9097_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NV9097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NV9097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NV9097_SET_VAB_VERTEX3F(i) (0x0220+(i)*4) +#define NV9097_SET_VAB_VERTEX3F_V 31:0 + +#define NV9097_SET_VAB_VERTEX4F(i) (0x0230+(i)*4) +#define NV9097_SET_VAB_VERTEX4F_V 31:0 + +#define NV9097_SET_VAB_NORMAL3F(i) (0x0240+(i)*4) +#define NV9097_SET_VAB_NORMAL3F_V 31:0 + +#define NV9097_SET_VAB_COLOR3F(i) (0x0250+(i)*4) +#define NV9097_SET_VAB_COLOR3F_V 31:0 + +#define NV9097_SET_VAB_COLOR4F(i) (0x0260+(i)*4) +#define NV9097_SET_VAB_COLOR4F_V 31:0 + +#define NV9097_SET_VAB_COLOR4UB(i) (0x0270+(i)*4) +#define NV9097_SET_VAB_COLOR4UB_V 31:0 + +#define NV9097_SET_VAB_TEX_COORD1F(i) (0x0280+(i)*4) +#define NV9097_SET_VAB_TEX_COORD1F_V 31:0 + +#define NV9097_SET_VAB_TEX_COORD2F(i) (0x0290+(i)*4) +#define NV9097_SET_VAB_TEX_COORD2F_V 31:0 + +#define NV9097_SET_VAB_TEX_COORD3F(i) (0x02a0+(i)*4) +#define NV9097_SET_VAB_TEX_COORD3F_V 31:0 + +#define NV9097_SET_VAB_TEX_COORD4F(i) (0x02b0+(i)*4) +#define NV9097_SET_VAB_TEX_COORD4F_V 31:0 + +#define NV9097_SET_GA_TO_VA_MAPPING_MODE 0x02c4 +#define NV9097_SET_GA_TO_VA_MAPPING_MODE_V 0:0 +#define NV9097_SET_GA_TO_VA_MAPPING_MODE_V_DISABLE 0x00000000 +#define NV9097_SET_GA_TO_VA_MAPPING_MODE_V_ENABLE 0x00000001 + +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY 0x02c8 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_VIRTUAL_ADDRESS_UPPER 7:0 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_GENERIC_ADDRESS_UPPER 23:16 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE 30:30 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_FALSE 0x00000000 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_TRUE 0x00000001 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE 31:31 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_FALSE 0x00000000 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_TASK_CIRCULAR_BUFFER_THROTTLE 0x02cc +#define NV9097_SET_TASK_CIRCULAR_BUFFER_THROTTLE_TASK_COUNT 21:0 + +#define NV9097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NV9097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NV9097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NV9097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NV9097_SET_RASTER_BOUNDING_BOX 0x02ec +#define NV9097_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NV9097_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NV9097_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NV9097_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NV9097_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NV9097_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NV9097_DRAW_ZERO_INDEX 0x0304 +#define NV9097_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NV9097_SET_L1_CONFIGURATION 0x0308 +#define NV9097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NV9097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NV9097_SET_RENDER_ENABLE_CONTROL 0x030c +#define NV9097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NV9097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NV9097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NV9097_X_X_X_SET_CT_ENABLE 0x0310 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET0 0:0 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET0_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET0_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET1 1:1 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET1_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET1_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET2 2:2 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET2_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET2_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET3 3:3 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET3_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET3_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET4 4:4 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET4_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET4_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET5 5:5 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET5_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET5_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET6 6:6 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET6_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET6_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET7 7:7 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET7_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET7_TRUE 0x00000001 + +#define NV9097_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NV9097_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NV9097_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SNAP_GRID_LINE 0x0318 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NV9097_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NV9097_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NV9097_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NV9097_SET_SNAP_GRID_NON_LINE 0x031c +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NV9097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NV9097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NV9097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NV9097_SET_TESSELLATION_PARAMETERS 0x0320 +#define NV9097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NV9097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NV9097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NV9097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NV9097_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NV9097_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NV9097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NV9097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NV9097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NV9097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NV9097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NV9097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NV9097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NV9097_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NV9097_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NV9097_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NV9097_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NV9097_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NV9097_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NV9097_SET_TESSELLATION_LOD_V1 0x0330 +#define NV9097_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NV9097_SET_TG_LOD_INTERIOR_U 0x0334 +#define NV9097_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NV9097_SET_TG_LOD_INTERIOR_V 0x0338 +#define NV9097_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NV9097_RESERVED_TG07 0x033c +#define NV9097_RESERVED_TG07_V 0:0 + +#define NV9097_RESERVED_TG08 0x0340 +#define NV9097_RESERVED_TG08_V 0:0 + +#define NV9097_RESERVED_TG09 0x0344 +#define NV9097_RESERVED_TG09_V 0:0 + +#define NV9097_RESERVED_TG10 0x0348 +#define NV9097_RESERVED_TG10_V 0:0 + +#define NV9097_RESERVED_TG11 0x034c +#define NV9097_RESERVED_TG11_V 0:0 + +#define NV9097_RESERVED_TG12 0x0350 +#define NV9097_RESERVED_TG12_V 0:0 + +#define NV9097_RESERVED_TG13 0x0354 +#define NV9097_RESERVED_TG13_V 0:0 + +#define NV9097_RESERVED_TG14 0x0358 +#define NV9097_RESERVED_TG14_V 0:0 + +#define NV9097_RESERVED_TG15 0x035c +#define NV9097_RESERVED_TG15_V 0:0 + +#define NV9097_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NV9097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NV9097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NV9097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NV9097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NV9097_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NV9097_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NV9097_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NV9097_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NV9097_SET_RASTER_ENABLE 0x037c +#define NV9097_SET_RASTER_ENABLE_V 0:0 +#define NV9097_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NV9097_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NV9097_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NV9097_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NV9097_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NV9097_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NV9097_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NV9097_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NV9097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NV9097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NV9097_SET_VAB_DATA_TYPELESS(i) (0x0400+(i)*4) +#define NV9097_SET_VAB_DATA_TYPELESS_V 31:0 + +#define NV9097_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NV9097_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NV9097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NV9097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NV9097_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NV9097_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NV9097_SET_RASTER_INPUT 0x0740 +#define NV9097_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NV9097_SET_STREAM_OUTPUT 0x0744 +#define NV9097_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NV9097_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NV9097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NV9097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_ALPHA_FRACTION 0x074c +#define NV9097_SET_ALPHA_FRACTION_V 7:0 + +#define NV9097_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NV9097_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NV9097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NV9097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NV9097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 + +#define NV9097_SET_MAX_TI_WARPS_PER_BATCH 0x075c +#define NV9097_SET_MAX_TI_WARPS_PER_BATCH_V 5:0 + +#define NV9097_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NV9097_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NV9097_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NV9097_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NV9097_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NV9097_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NV9097_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NV9097_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NV9097_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NV9097_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NV9097_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NV9097_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NV9097_SET_VAB_VERTEX2F(i) (0x07b0+(i)*4) +#define NV9097_SET_VAB_VERTEX2F_V 31:0 + +#define NV9097_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NV9097_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NV9097_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NV9097_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NV9097_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NV9097_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NV9097_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NV9097_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NV9097_SET_CULL_BEFORE_FETCH 0x07dc +#define NV9097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NV9097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NV9097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NV9097_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NV9097_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NV9097_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NV9097_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NV9097_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NV9097_SET_ZCULL_STORAGE_A 0x07e8 +#define NV9097_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NV9097_SET_ZCULL_STORAGE_B 0x07ec +#define NV9097_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NV9097_SET_ZCULL_STORAGE_C 0x07f0 +#define NV9097_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NV9097_SET_ZCULL_STORAGE_D 0x07f4 +#define NV9097_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NV9097_SET_ZT_READ_ONLY 0x07f8 +#define NV9097_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NV9097_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NV9097_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NV9097_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NV9097_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NV9097_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NV9097_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NV9097_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NV9097_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NV9097_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NV9097_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NV9097_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NV9097_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NV9097_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NV9097_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NV9097_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NV9097_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NV9097_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NV9097_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV9097_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NV9097_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV9097_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 + +#define NV9097_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NV9097_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NV9097_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NV9097_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NV9097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NV9097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NV9097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NV9097_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NV9097_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NV9097_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NV9097_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NV9097_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NV9097_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NV9097_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NV9097_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NV9097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NV9097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NV9097_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NV9097_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NV9097_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NV9097_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NV9097_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NV9097_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NV9097_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NV9097_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NV9097_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NV9097_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NV9097_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NV9097_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NV9097_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NV9097_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NV9097_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NV9097_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NV9097_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NV9097_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NV9097_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NV9097_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NV9097_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NV9097_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NV9097_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NV9097_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NV9097_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NV9097_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NV9097_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NV9097_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NV9097_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NV9097_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NV9097_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NV9097_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NV9097_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NV9097_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NV9097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NV9097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NV9097_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NV9097_SET_STATISTICS_COUNTER 0x0d68 +#define NV9097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NV9097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NV9097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NV9097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NV9097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NV9097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NV9097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NV9097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NV9097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NV9097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NV9097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NV9097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NV9097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NV9097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NV9097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NV9097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NV9097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NV9097_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NV9097_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NV9097_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NV9097_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NV9097_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NV9097_SET_VERTEX_ARRAY_START 0x0d74 +#define NV9097_SET_VERTEX_ARRAY_START_V 31:0 + +#define NV9097_DRAW_VERTEX_ARRAY 0x0d78 +#define NV9097_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NV9097_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NV9097_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NV9097_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NV9097_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NV9097_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NV9097_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NV9097_SET_Z_CLEAR_VALUE 0x0d90 +#define NV9097_SET_Z_CLEAR_VALUE_V 31:0 + +#define NV9097_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NV9097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NV9097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NV9097_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NV9097_SET_FRONT_POLYGON_MODE 0x0dac +#define NV9097_SET_FRONT_POLYGON_MODE_V 31:0 +#define NV9097_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NV9097_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NV9097_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NV9097_SET_BACK_POLYGON_MODE 0x0db0 +#define NV9097_SET_BACK_POLYGON_MODE_V 31:0 +#define NV9097_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NV9097_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NV9097_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NV9097_SET_POLY_SMOOTH 0x0db4 +#define NV9097_SET_POLY_SMOOTH_ENABLE 0:0 +#define NV9097_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NV9097_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_ZT_MARK 0x0db8 +#define NV9097_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NV9097_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NV9097_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NV9097_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NV9097_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NV9097_SET_POLY_OFFSET_POINT 0x0dc0 +#define NV9097_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NV9097_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_POLY_OFFSET_LINE 0x0dc4 +#define NV9097_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NV9097_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_POLY_OFFSET_FILL 0x0dc8 +#define NV9097_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NV9097_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NV9097_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_PATCH 0x0dcc +#define NV9097_SET_PATCH_SIZE 7:0 + +#define NV9097_SET_ZCULL_CRITERION 0x0dd8 +#define NV9097_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NV9097_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NV9097_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NV9097_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NV9097_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NV9097_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NV9097_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NV9097_SET_ZCULL_CRITERION_SREF 23:16 +#define NV9097_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NV9097_X_X_X_SET_DA_ATTRIBUTE_CACHE_LINE 0x0ddc +#define NV9097_X_X_X_SET_DA_ATTRIBUTE_CACHE_LINE_V 1:0 +#define NV9097_X_X_X_SET_DA_ATTRIBUTE_CACHE_LINE_V_SIZE128 0x00000000 +#define NV9097_X_X_X_SET_DA_ATTRIBUTE_CACHE_LINE_V_SIZE64 0x00000001 +#define NV9097_X_X_X_SET_DA_ATTRIBUTE_CACHE_LINE_V_SIZE32 0x00000002 + +#define NV9097_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NV9097_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NV9097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NV9097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NV9097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE 0x0dec +#define NV9097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE 0:0 +#define NV9097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE_TRUE 0x00000001 + +#define NV9097_X_X_X_SET_REDUCE_COLOR 0x0df4 +#define NV9097_X_X_X_SET_REDUCE_COLOR_U8_THRESHOLD 7:0 +#define NV9097_X_X_X_SET_REDUCE_COLOR_FP16_THRESHOLD 23:8 + +#define NV9097_SET_WINDOW_OFFSET_X 0x0df8 +#define NV9097_SET_WINDOW_OFFSET_X_V 16:0 + +#define NV9097_SET_WINDOW_OFFSET_Y 0x0dfc +#define NV9097_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NV9097_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NV9097_SET_SCISSOR_ENABLE_V 0:0 +#define NV9097_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NV9097_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NV9097_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NV9097_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NV9097_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NV9097_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NV9097_SET_VAB_NORMAL3S(i) (0x0f00+(i)*4) +#define NV9097_SET_VAB_NORMAL3S_V 31:0 + +#define NV9097_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NV9097_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NV9097_SET_BACK_STENCIL_MASK 0x0f58 +#define NV9097_SET_BACK_STENCIL_MASK_V 7:0 + +#define NV9097_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NV9097_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NV9097_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NV9097_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NV9097_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NV9097_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NV9097_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NV9097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NV9097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NV9097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NV9097_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NV9097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NV9097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NV9097_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NV9097_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NV9097_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NV9097_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NV9097_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NV9097_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NV9097_SET_CT_MRT_ENABLE 0x0fac +#define NV9097_SET_CT_MRT_ENABLE_V 0:0 +#define NV9097_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NV9097_SET_NONMULTISAMPLED_Z_V 0:0 +#define NV9097_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NV9097_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NV9097_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NV9097_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NV9097_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NV9097_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NV9097_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NV9097_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NV9097_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NV9097_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NV9097_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NV9097_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NV9097_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_BLEND_OPT_CONTROL 0x0fdc +#define NV9097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NV9097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NV9097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NV9097_SET_ZT_A 0x0fe0 +#define NV9097_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_ZT_B 0x0fe4 +#define NV9097_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_ZT_FORMAT 0x0fe8 +#define NV9097_SET_ZT_FORMAT_V 4:0 +#define NV9097_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NV9097_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NV9097_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NV9097_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NV9097_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NV9097_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NV9097_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NV9097_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NV9097_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NV9097_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NV9097_SET_ZT_BLOCK_SIZE 0x0fec +#define NV9097_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NV9097_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV9097_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NV9097_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NV9097_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NV9097_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NV9097_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NV9097_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NV9097_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NV9097_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NV9097_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NV9097_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NV9097_SET_FORCE_ONE_TEXTURE_UNIT 0x1004 +#define NV9097_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE 0:0 +#define NV9097_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NV9097_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NV9097_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NV9097_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NV9097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NV9097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NV9097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NV9097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NV9097_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NV9097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NV9097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NV9097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NV9097_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NV9097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NV9097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SPARE_NOOP00 0x1040 +#define NV9097_SET_SPARE_NOOP00_V 31:0 + +#define NV9097_SET_SPARE_NOOP01 0x1044 +#define NV9097_SET_SPARE_NOOP01_V 31:0 + +#define NV9097_SET_SPARE_NOOP02 0x1048 +#define NV9097_SET_SPARE_NOOP02_V 31:0 + +#define NV9097_SET_SPARE_NOOP03 0x104c +#define NV9097_SET_SPARE_NOOP03_V 31:0 + +#define NV9097_SET_SPARE_NOOP04 0x1050 +#define NV9097_SET_SPARE_NOOP04_V 31:0 + +#define NV9097_SET_SPARE_NOOP05 0x1054 +#define NV9097_SET_SPARE_NOOP05_V 31:0 + +#define NV9097_SET_SPARE_NOOP06 0x1058 +#define NV9097_SET_SPARE_NOOP06_V 31:0 + +#define NV9097_SET_SPARE_NOOP07 0x105c +#define NV9097_SET_SPARE_NOOP07_V 31:0 + +#define NV9097_SET_SPARE_NOOP08 0x1060 +#define NV9097_SET_SPARE_NOOP08_V 31:0 + +#define NV9097_SET_SPARE_NOOP09 0x1064 +#define NV9097_SET_SPARE_NOOP09_V 31:0 + +#define NV9097_SET_SPARE_NOOP10 0x1068 +#define NV9097_SET_SPARE_NOOP10_V 31:0 + +#define NV9097_SET_SPARE_NOOP11 0x106c +#define NV9097_SET_SPARE_NOOP11_V 31:0 + +#define NV9097_SET_SPARE_NOOP12 0x1070 +#define NV9097_SET_SPARE_NOOP12_V 31:0 + +#define NV9097_SET_SPARE_NOOP13 0x1074 +#define NV9097_SET_SPARE_NOOP13_V 31:0 + +#define NV9097_SET_SPARE_NOOP14 0x1078 +#define NV9097_SET_SPARE_NOOP14_V 31:0 + +#define NV9097_SET_SPARE_NOOP15 0x107c +#define NV9097_SET_SPARE_NOOP15_V 31:0 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NV9097_UNBIND_ALL 0x10f4 +#define NV9097_UNBIND_ALL_TEXTURE_HEADERS 0:0 +#define NV9097_UNBIND_ALL_TEXTURE_HEADERS_FALSE 0x00000000 +#define NV9097_UNBIND_ALL_TEXTURE_HEADERS_TRUE 0x00000001 +#define NV9097_UNBIND_ALL_TEXTURE_SAMPLERS 4:4 +#define NV9097_UNBIND_ALL_TEXTURE_SAMPLERS_FALSE 0x00000000 +#define NV9097_UNBIND_ALL_TEXTURE_SAMPLERS_TRUE 0x00000001 +#define NV9097_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NV9097_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NV9097_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NV9097_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NV9097_NO_OPERATION_DATA_HI 0x110c +#define NV9097_NO_OPERATION_DATA_HI_V 31:0 + +#define NV9097_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NV9097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NV9097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NV9097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NV9097_PM_TRIGGER_END 0x1114 +#define NV9097_PM_TRIGGER_END_V 31:0 + +#define NV9097_SET_VERTEX_ID_BASE 0x1118 +#define NV9097_SET_VERTEX_ID_BASE_V 31:0 + +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NV9097_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NV9097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NV9097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NV9097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NV9097_FLUSH_PENDING_WRITES 0x1144 +#define NV9097_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NV9097_SET_VAB_DATA_CONTROL 0x114c +#define NV9097_SET_VAB_DATA_CONTROL_VAB_INDEX 7:0 +#define NV9097_SET_VAB_DATA_CONTROL_COMPONENT_COUNT 10:8 +#define NV9097_SET_VAB_DATA_CONTROL_COMPONENT_BYTE_WIDTH 14:12 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT 18:16 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_SNORM 0x00000001 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_UNORM 0x00000002 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_SINT 0x00000003 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_UINT 0x00000004 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_USCALED 0x00000005 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_SSCALED 0x00000006 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_FLOAT 0x00000007 + +#define NV9097_SET_VAB_DATA(i) (0x1150+(i)*4) +#define NV9097_SET_VAB_DATA_V 31:0 + +#define NV9097_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NV9097_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NV9097_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NV9097_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_SET_CT_SELECT 0x121c +#define NV9097_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NV9097_SET_CT_SELECT_TARGET0 6:4 +#define NV9097_SET_CT_SELECT_TARGET1 9:7 +#define NV9097_SET_CT_SELECT_TARGET2 12:10 +#define NV9097_SET_CT_SELECT_TARGET3 15:13 +#define NV9097_SET_CT_SELECT_TARGET4 18:16 +#define NV9097_SET_CT_SELECT_TARGET5 21:19 +#define NV9097_SET_CT_SELECT_TARGET6 24:22 +#define NV9097_SET_CT_SELECT_TARGET7 27:25 + +#define NV9097_SET_COMPRESSION_THRESHOLD 0x1220 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NV9097_SET_ZT_SIZE_A 0x1228 +#define NV9097_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NV9097_SET_ZT_SIZE_B 0x122c +#define NV9097_SET_ZT_SIZE_B_HEIGHT 16:0 + +#define NV9097_SET_ZT_SIZE_C 0x1230 +#define NV9097_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NV9097_SET_ZT_SIZE_C_CONTROL 16:16 +#define NV9097_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NV9097_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NV9097_SET_SAMPLER_BINDING 0x1234 +#define NV9097_SET_SAMPLER_BINDING_V 0:0 +#define NV9097_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NV9097_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NV9097_DRAW_AUTO 0x123c +#define NV9097_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NV9097_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NV9097_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 9:0 + +#define NV9097_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NV9097_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NV9097_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NV9097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NV9097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NV9097_SET_SHADER_SCHEDULING 0x12ac +#define NV9097_SET_SHADER_SCHEDULING_MODE 0:0 +#define NV9097_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 +#define NV9097_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 + +#define NV9097_CLEAR_ZCULL_REGION 0x12c8 +#define NV9097_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NV9097_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NV9097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NV9097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NV9097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NV9097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NV9097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NV9097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NV9097_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NV9097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NV9097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NV9097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NV9097_SET_DEPTH_TEST 0x12cc +#define NV9097_SET_DEPTH_TEST_ENABLE 0:0 +#define NV9097_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_FILL_MODE 0x12d0 +#define NV9097_SET_FILL_MODE_V 31:0 +#define NV9097_SET_FILL_MODE_V_POINT 0x00000001 +#define NV9097_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NV9097_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NV9097_SET_SHADE_MODE 0x12d4 +#define NV9097_SET_SHADE_MODE_V 31:0 +#define NV9097_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NV9097_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NV9097_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NV9097_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NV9097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NV9097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NV9097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NV9097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NV9097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NV9097_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NV9097_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NV9097_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NV9097_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_DEPTH_WRITE 0x12e8 +#define NV9097_SET_DEPTH_WRITE_ENABLE 0:0 +#define NV9097_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_ALPHA_TEST 0x12ec +#define NV9097_SET_ALPHA_TEST_ENABLE 0:0 +#define NV9097_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NV9097_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NV9097_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NV9097_DRAW_INLINE_INDEX4X8 0x1304 +#define NV9097_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NV9097_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NV9097_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NV9097_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NV9097_D3D_SET_CULL_MODE 0x1308 +#define NV9097_D3D_SET_CULL_MODE_V 31:0 +#define NV9097_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NV9097_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NV9097_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NV9097_SET_DEPTH_FUNC 0x130c +#define NV9097_SET_DEPTH_FUNC_V 31:0 +#define NV9097_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NV9097_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NV9097_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NV9097_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NV9097_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NV9097_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NV9097_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NV9097_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NV9097_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NV9097_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NV9097_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NV9097_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NV9097_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NV9097_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NV9097_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NV9097_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NV9097_SET_ALPHA_REF 0x1310 +#define NV9097_SET_ALPHA_REF_V 31:0 + +#define NV9097_SET_ALPHA_FUNC 0x1314 +#define NV9097_SET_ALPHA_FUNC_V 31:0 +#define NV9097_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NV9097_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NV9097_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NV9097_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NV9097_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NV9097_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NV9097_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NV9097_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NV9097_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NV9097_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NV9097_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NV9097_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NV9097_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NV9097_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NV9097_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NV9097_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NV9097_SET_DRAW_AUTO_STRIDE 0x1318 +#define NV9097_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NV9097_SET_BLEND_CONST_RED 0x131c +#define NV9097_SET_BLEND_CONST_RED_V 31:0 + +#define NV9097_SET_BLEND_CONST_GREEN 0x1320 +#define NV9097_SET_BLEND_CONST_GREEN_V 31:0 + +#define NV9097_SET_BLEND_CONST_BLUE 0x1324 +#define NV9097_SET_BLEND_CONST_BLUE_V 31:0 + +#define NV9097_SET_BLEND_CONST_ALPHA 0x1328 +#define NV9097_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NV9097_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NV9097_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NV9097_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NV9097_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NV9097_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS 2:1 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY 0x00000000 + +#define NV9097_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NV9097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NV9097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NV9097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_BLEND_COLOR_OP 0x1340 +#define NV9097_SET_BLEND_COLOR_OP_V 31:0 +#define NV9097_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NV9097_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NV9097_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NV9097_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NV9097_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NV9097_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NV9097_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NV9097_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NV9097_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NV9097_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_BLEND_ALPHA_OP 0x134c +#define NV9097_SET_BLEND_ALPHA_OP_V 31:0 +#define NV9097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NV9097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NV9097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NV9097_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NV9097_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NV9097_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NV9097_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NV9097_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NV9097_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NV9097_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_GLOBAL_COLOR_KEY 0x1354 +#define NV9097_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NV9097_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NV9097_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_SINGLE_ROP_CONTROL 0x135c +#define NV9097_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NV9097_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_BLEND(i) (0x1360+(i)*4) +#define NV9097_SET_BLEND_ENABLE 0:0 +#define NV9097_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NV9097_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_STENCIL_TEST 0x1380 +#define NV9097_SET_STENCIL_TEST_ENABLE 0:0 +#define NV9097_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_STENCIL_OP_FAIL 0x1384 +#define NV9097_SET_STENCIL_OP_FAIL_V 31:0 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NV9097_SET_STENCIL_OP_ZFAIL 0x1388 +#define NV9097_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NV9097_SET_STENCIL_OP_ZPASS 0x138c +#define NV9097_SET_STENCIL_OP_ZPASS_V 31:0 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NV9097_SET_STENCIL_FUNC 0x1390 +#define NV9097_SET_STENCIL_FUNC_V 31:0 +#define NV9097_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NV9097_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NV9097_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NV9097_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NV9097_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NV9097_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NV9097_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NV9097_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NV9097_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NV9097_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NV9097_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NV9097_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NV9097_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NV9097_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NV9097_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NV9097_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NV9097_SET_STENCIL_FUNC_REF 0x1394 +#define NV9097_SET_STENCIL_FUNC_REF_V 7:0 + +#define NV9097_SET_STENCIL_FUNC_MASK 0x1398 +#define NV9097_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NV9097_SET_STENCIL_MASK 0x139c +#define NV9097_SET_STENCIL_MASK_V 7:0 + +#define NV9097_SET_DRAW_AUTO_START 0x13a4 +#define NV9097_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NV9097_SET_PS_SATURATE 0x13a8 +#define NV9097_SET_PS_SATURATE_OUTPUT0 0:0 +#define NV9097_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT1 4:4 +#define NV9097_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT2 8:8 +#define NV9097_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT3 12:12 +#define NV9097_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT4 16:16 +#define NV9097_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT5 20:20 +#define NV9097_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT6 24:24 +#define NV9097_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT7 28:28 +#define NV9097_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 + +#define NV9097_SET_WINDOW_ORIGIN 0x13ac +#define NV9097_SET_WINDOW_ORIGIN_MODE 0:0 +#define NV9097_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NV9097_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NV9097_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NV9097_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NV9097_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NV9097_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NV9097_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NV9097_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NV9097_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NV9097_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NV9097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NV9097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_ALPHA_HYSTERESIS 0x1420 +#define NV9097_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NV9097_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NV9097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NV9097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NV9097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NV9097_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NV9097_INVALIDATE_DA_DMA_CACHE 0x142c +#define NV9097_INVALIDATE_DA_DMA_CACHE_V 0:0 + +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR 0x1430 +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR_UNORM_ENABLE 4:4 +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR_UNORM_ENABLE_FALSE 0x00000000 +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR_UNORM_ENABLE_TRUE 0x00000001 +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR_SRGB_ENABLE 8:8 +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR_SRGB_ENABLE_FALSE 0x00000000 +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR_SRGB_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NV9097_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NV9097_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NV9097_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NV9097_X_X_X_SET_CLEAR_CONTROL 0x143c +#define NV9097_X_X_X_SET_CLEAR_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NV9097_X_X_X_SET_CLEAR_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CLEAR_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CLEAR_CONTROL_USE_CLEAR_RECT 4:4 +#define NV9097_X_X_X_SET_CLEAR_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CLEAR_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 + +#define NV9097_SET_PS_WARP_WATERMARKS 0x1450 +#define NV9097_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NV9097_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NV9097_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NV9097_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NV9097_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NV9097_STORE_ZCULL 0x1464 +#define NV9097_STORE_ZCULL_V 0:0 + +#define NV9097_LOAD_ZCULL 0x1500 +#define NV9097_LOAD_ZCULL_V 0:0 + +#define NV9097_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NV9097_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NV9097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NV9097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NV9097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NV9097_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NV9097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NV9097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NV9097_SET_USER_CLIP_ENABLE 0x1510 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NV9097_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NV9097_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NV9097_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_POINT_SIZE 0x1518 +#define NV9097_SET_POINT_SIZE_V 31:0 + +#define NV9097_SET_ZCULL_STATS 0x151c +#define NV9097_SET_ZCULL_STATS_ENABLE 0:0 +#define NV9097_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_POINT_SPRITE 0x1520 +#define NV9097_SET_POINT_SPRITE_ENABLE 0:0 +#define NV9097_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SHADER_EXCEPTIONS 0x1528 +#define NV9097_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NV9097_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NV9097_CLEAR_REPORT_VALUE 0x1530 +#define NV9097_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NV9097_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NV9097_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NV9097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NV9097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NV9097_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NV9097_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 + +#define NV9097_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NV9097_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NV9097_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_ZT_SELECT 0x1538 +#define NV9097_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NV9097_SET_RENDER_ENABLE_A 0x1550 +#define NV9097_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_RENDER_ENABLE_B 0x1554 +#define NV9097_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_RENDER_ENABLE_C 0x1558 +#define NV9097_SET_RENDER_ENABLE_C_MODE 2:0 +#define NV9097_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV9097_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV9097_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV9097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV9097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV9097_SET_TEX_SAMPLER_POOL_A 0x155c +#define NV9097_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NV9097_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NV9097_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NV9097_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NV9097_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NV9097_SET_ANTI_ALIASED_LINE 0x1570 +#define NV9097_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NV9097_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_TEX_HEADER_POOL_A 0x1574 +#define NV9097_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_TEX_HEADER_POOL_B 0x1578 +#define NV9097_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_TEX_HEADER_POOL_C 0x157c +#define NV9097_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NV9097_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NV9097_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NV9097_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NV9097_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NV9097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NV9097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NV9097_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NV9097_SET_BACK_STENCIL_FUNC 0x15a4 +#define NV9097_SET_BACK_STENCIL_FUNC_V 31:0 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NV9097_SET_SRGB_WRITE 0x15b8 +#define NV9097_SET_SRGB_WRITE_ENABLE 0:0 +#define NV9097_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_DEPTH_BIAS 0x15bc +#define NV9097_SET_DEPTH_BIAS_V 31:0 + +#define NV9097_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NV9097_SET_ZCULL_REGION_FORMAT_TYPE 1:0 +#define NV9097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NV9097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NV9097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NV9097_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 + +#define NV9097_SET_RT_LAYER 0x15cc +#define NV9097_SET_RT_LAYER_V 15:0 +#define NV9097_SET_RT_LAYER_CONTROL 16:16 +#define NV9097_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NV9097_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NV9097_SET_ANTI_ALIAS 0x15d0 +#define NV9097_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NV9097_SET_EDGE_FLAG 0x15e4 +#define NV9097_SET_EDGE_FLAG_V 0:0 +#define NV9097_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NV9097_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NV9097_DRAW_INLINE_INDEX 0x15e8 +#define NV9097_DRAW_INLINE_INDEX_V 31:0 + +#define NV9097_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NV9097_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NV9097_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NV9097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NV9097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NV9097_DRAW_INLINE_INDEX2X16 0x15f0 +#define NV9097_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NV9097_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NV9097_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NV9097_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NV9097_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NV9097_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NV9097_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NV9097_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NV9097_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NV9097_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NV9097_SET_POINT_SPRITE_SELECT 0x1604 +#define NV9097_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NV9097_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NV9097_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NV9097_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NV9097_SET_PROGRAM_REGION_A 0x1608 +#define NV9097_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NV9097_SET_PROGRAM_REGION_B 0x160c +#define NV9097_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NV9097_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NV9097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NV9097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NV9097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NV9097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NV9097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NV9097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NV9097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NV9097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NV9097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NV9097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NV9097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NV9097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NV9097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NV9097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NV9097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NV9097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NV9097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NV9097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NV9097_END 0x1614 +#define NV9097_END_V 0:0 + +#define NV9097_BEGIN 0x1618 +#define NV9097_BEGIN_OP 15:0 +#define NV9097_BEGIN_OP_POINTS 0x00000000 +#define NV9097_BEGIN_OP_LINES 0x00000001 +#define NV9097_BEGIN_OP_LINE_LOOP 0x00000002 +#define NV9097_BEGIN_OP_LINE_STRIP 0x00000003 +#define NV9097_BEGIN_OP_TRIANGLES 0x00000004 +#define NV9097_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NV9097_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NV9097_BEGIN_OP_QUADS 0x00000007 +#define NV9097_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NV9097_BEGIN_OP_POLYGON 0x00000009 +#define NV9097_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NV9097_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NV9097_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_BEGIN_OP_PATCH 0x0000000E +#define NV9097_BEGIN_PRIMITIVE_ID 24:24 +#define NV9097_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NV9097_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NV9097_BEGIN_INSTANCE_ID 27:26 +#define NV9097_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NV9097_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NV9097_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NV9097_BEGIN_SPLIT_MODE 30:29 +#define NV9097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NV9097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NV9097_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NV9097_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 + +#define NV9097_SET_VERTEX_ID_COPY 0x161c +#define NV9097_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NV9097_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NV9097_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NV9097_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NV9097_ADD_TO_PRIMITIVE_ID 0x1620 +#define NV9097_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NV9097_LOAD_PRIMITIVE_ID 0x1624 +#define NV9097_LOAD_PRIMITIVE_ID_V 31:0 + +#define NV9097_SET_SHADER_BASED_CULL 0x162c +#define NV9097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NV9097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NV9097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NV9097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SHADER_ISA_VERSION 0x1634 +#define NV9097_SET_SHADER_ISA_VERSION_MINOR_SUB 7:0 +#define NV9097_SET_SHADER_ISA_VERSION_MINOR 15:8 +#define NV9097_SET_SHADER_ISA_VERSION_MAJOR 23:16 + +#define NV9097_SET_FERMI_CLASS_VERSION 0x1638 +#define NV9097_SET_FERMI_CLASS_VERSION_CURRENT 15:0 +#define NV9097_SET_FERMI_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NV9097_SET_VAB_PAGE 0x163c +#define NV9097_SET_VAB_PAGE_READ_SELECT 0:0 +#define NV9097_SET_VAB_PAGE_READ_SELECT_PAGES_0_AND_1 0x00000000 +#define NV9097_SET_VAB_PAGE_READ_SELECT_PAGES_0_AND_2 0x00000001 + +#define NV9097_DRAW_INLINE_VERTEX 0x1640 +#define NV9097_DRAW_INLINE_VERTEX_V 31:0 + +#define NV9097_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NV9097_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NV9097_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NV9097_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NV9097_SET_DA_OUTPUT 0x164c +#define NV9097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NV9097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NV9097_SET_ANTI_ALIASED_POINT 0x1658 +#define NV9097_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NV9097_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_POINT_CENTER_MODE 0x165c +#define NV9097_SET_POINT_CENTER_MODE_V 31:0 +#define NV9097_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NV9097_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NV9097_SET_CUBEMAP_INTER_FACE_FILTERING 0x1664 +#define NV9097_SET_CUBEMAP_INTER_FACE_FILTERING_MODE 2:1 +#define NV9097_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_USE_WRAP 0x00000000 +#define NV9097_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_OVERRIDE_WRAP 0x00000001 +#define NV9097_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_SPAN_SEAM 0x00000002 +#define NV9097_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_CROSS_SEAM 0x00000003 + +#define NV9097_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NV9097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NV9097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NV9097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NV9097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NV9097_SET_LINE_STIPPLE 0x166c +#define NV9097_SET_LINE_STIPPLE_ENABLE 0:0 +#define NV9097_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NV9097_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NV9097_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NV9097_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NV9097_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NV9097_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NV9097_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NV9097_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NV9097_SET_PROVOKING_VERTEX 0x1684 +#define NV9097_SET_PROVOKING_VERTEX_V 0:0 +#define NV9097_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NV9097_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NV9097_SET_TWO_SIDED_LIGHT 0x1688 +#define NV9097_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NV9097_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_POLYGON_STIPPLE 0x168c +#define NV9097_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NV9097_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SHADER_CONTROL 0x1690 +#define NV9097_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NV9097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NV9097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NV9097_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO 16:16 +#define NV9097_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NV9097_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NV9097_LAUNCH_VERTEX 0x169c +#define NV9097_LAUNCH_VERTEX_V 0:0 + +#define NV9097_CHECK_FERMI_CLASS_VERSION 0x16a0 +#define NV9097_CHECK_FERMI_CLASS_VERSION_CURRENT 15:0 +#define NV9097_CHECK_FERMI_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NV9097_SET_SPH_VERSION 0x16a4 +#define NV9097_SET_SPH_VERSION_CURRENT 15:0 +#define NV9097_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NV9097_CHECK_SPH_VERSION 0x16a8 +#define NV9097_CHECK_SPH_VERSION_CURRENT 15:0 +#define NV9097_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NV9097_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NV9097_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NV9097_SET_AAM_VERSION 0x1790 +#define NV9097_SET_AAM_VERSION_CURRENT 15:0 +#define NV9097_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NV9097_CHECK_AAM_VERSION 0x1794 +#define NV9097_CHECK_AAM_VERSION_CURRENT 15:0 +#define NV9097_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NV9097_SET_ZT_LAYER 0x179c +#define NV9097_SET_ZT_LAYER_OFFSET 15:0 + +#define NV9097_SET_VAB_MEMORY_AREA_A 0x17bc +#define NV9097_SET_VAB_MEMORY_AREA_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_VAB_MEMORY_AREA_B 0x17c0 +#define NV9097_SET_VAB_MEMORY_AREA_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_VAB_MEMORY_AREA_C 0x17c4 +#define NV9097_SET_VAB_MEMORY_AREA_C_SIZE 1:0 +#define NV9097_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_64K 0x00000001 +#define NV9097_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_128K 0x00000002 +#define NV9097_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_256K 0x00000003 + +#define NV9097_SET_INDEX_BUFFER_A 0x17c8 +#define NV9097_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NV9097_SET_INDEX_BUFFER_B 0x17cc +#define NV9097_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NV9097_SET_INDEX_BUFFER_C 0x17d0 +#define NV9097_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NV9097_SET_INDEX_BUFFER_D 0x17d4 +#define NV9097_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NV9097_SET_INDEX_BUFFER_E 0x17d8 +#define NV9097_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NV9097_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NV9097_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NV9097_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NV9097_SET_INDEX_BUFFER_F 0x17dc +#define NV9097_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NV9097_DRAW_INDEX_BUFFER 0x17e0 +#define NV9097_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_SET_DEPTH_BIAS_CLAMP 0x187c +#define NV9097_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NV9097_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NV9097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NV9097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NV9097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NV9097_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NV9097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NV9097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NV9097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NV9097_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NV9097_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NV9097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NV9097_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NV9097_OGL_SET_CULL 0x1918 +#define NV9097_OGL_SET_CULL_ENABLE 0:0 +#define NV9097_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NV9097_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NV9097_OGL_SET_FRONT_FACE 0x191c +#define NV9097_OGL_SET_FRONT_FACE_V 31:0 +#define NV9097_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NV9097_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NV9097_OGL_SET_CULL_FACE 0x1920 +#define NV9097_OGL_SET_CULL_FACE_V 31:0 +#define NV9097_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NV9097_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NV9097_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NV9097_SET_VIEWPORT_PIXEL 0x1924 +#define NV9097_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NV9097_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NV9097_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NV9097_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NV9097_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NV9097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NV9097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NV9097_INVALIDATE_CONSTANT_BUFFER_CACHE 0x1930 +#define NV9097_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2 0:0 +#define NV9097_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_FALSE 0x00000000 +#define NV9097_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_TRUE 0x00000001 + +#define NV9097_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NV9097_SET_USER_CLIP_OP 0x1940 +#define NV9097_SET_USER_CLIP_OP_PLANE0 0:0 +#define NV9097_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE1 4:4 +#define NV9097_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE2 8:8 +#define NV9097_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE3 12:12 +#define NV9097_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE4 16:16 +#define NV9097_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE5 20:20 +#define NV9097_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE6 24:24 +#define NV9097_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE7 28:28 +#define NV9097_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NV9097_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NV9097_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NV9097_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NV9097_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NV9097_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NV9097_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NV9097_SET_WINDOW_CLIP_ENABLE 0x194c +#define NV9097_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NV9097_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_WINDOW_CLIP_TYPE 0x1950 +#define NV9097_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NV9097_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NV9097_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NV9097_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NV9097_INVALIDATE_ZCULL 0x1958 +#define NV9097_INVALIDATE_ZCULL_V 31:0 +#define NV9097_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NV9097_SET_ZCULL 0x1968 +#define NV9097_SET_ZCULL_Z_ENABLE 0:0 +#define NV9097_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NV9097_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NV9097_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_ZCULL_BOUNDS 0x196c +#define NV9097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NV9097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NV9097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NV9097_ZCULL_SYNC 0x1978 +#define NV9097_ZCULL_SYNC_V 31:0 + +#define NV9097_SET_CLIP_ID_TEST 0x197c +#define NV9097_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NV9097_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NV9097_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NV9097_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NV9097_SET_CLIP_ID 0x1984 +#define NV9097_SET_CLIP_ID_V 31:0 + +#define NV9097_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NV9097_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NV9097_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NV9097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NV9097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NV9097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NV9097_SET_LOGIC_OP 0x19c4 +#define NV9097_SET_LOGIC_OP_ENABLE 0:0 +#define NV9097_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NV9097_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_LOGIC_OP_FUNC 0x19c8 +#define NV9097_SET_LOGIC_OP_FUNC_V 31:0 +#define NV9097_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NV9097_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NV9097_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NV9097_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NV9097_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NV9097_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NV9097_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NV9097_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NV9097_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NV9097_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NV9097_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NV9097_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NV9097_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NV9097_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NV9097_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NV9097_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NV9097_SET_Z_COMPRESSION 0x19cc +#define NV9097_SET_Z_COMPRESSION_ENABLE 0:0 +#define NV9097_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NV9097_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NV9097_CLEAR_SURFACE 0x19d0 +#define NV9097_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NV9097_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NV9097_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_SURFACE_R_ENABLE 2:2 +#define NV9097_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_SURFACE_G_ENABLE 3:3 +#define NV9097_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_SURFACE_B_ENABLE 4:4 +#define NV9097_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_SURFACE_A_ENABLE 5:5 +#define NV9097_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NV9097_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NV9097_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NV9097_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NV9097_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NV9097_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NV9097_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NV9097_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NV9097_SET_CT_WRITE_R_ENABLE 0:0 +#define NV9097_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NV9097_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NV9097_SET_CT_WRITE_G_ENABLE 4:4 +#define NV9097_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NV9097_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NV9097_SET_CT_WRITE_B_ENABLE 8:8 +#define NV9097_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NV9097_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NV9097_SET_CT_WRITE_A_ENABLE 12:12 +#define NV9097_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NV9097_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NV9097_PIPE_NOP 0x1a2c +#define NV9097_PIPE_NOP_V 31:0 + +#define NV9097_SET_SPARE00 0x1a30 +#define NV9097_SET_SPARE00_V 31:0 + +#define NV9097_SET_SPARE01 0x1a34 +#define NV9097_SET_SPARE01_V 31:0 + +#define NV9097_SET_SPARE02 0x1a38 +#define NV9097_SET_SPARE02_V 31:0 + +#define NV9097_SET_SPARE03 0x1a3c +#define NV9097_SET_SPARE03_V 31:0 + +#define NV9097_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NV9097_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NV9097_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NV9097_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NV9097_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NV9097_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NV9097_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NV9097_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NV9097_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NV9097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NV9097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NV9097_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NV9097_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NV9097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NV9097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NV9097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NV9097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NV9097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 + +#define NV9097_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NV9097_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NV9097_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NV9097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NV9097_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NV9097_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NV9097_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NV9097_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NV9097_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NV9097_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NV9097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NV9097_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NV9097_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NV9097_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NV9097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NV9097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NV9097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NV9097_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NV9097_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NV9097_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NV9097_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NV9097_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NV9097_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NV9097_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NV9097_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NV9097_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NV9097_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NV9097_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NV9097_SET_PIPELINE_SHADER_TYPE 7:4 +#define NV9097_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NV9097_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NV9097_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NV9097_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NV9097_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NV9097_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NV9097_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NV9097_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NV9097_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NV9097_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NV9097_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NV9097_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NV9097_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NV9097_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NV9097_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NV9097_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NV9097_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NV9097_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NV9097_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NV9097_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NV9097_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NV9097_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NV9097_SET_BINDING_CONTROL_TEXTURE(j) (0x2200+(j)*16) +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS 3:0 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__1 0x00000000 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__2 0x00000001 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__4 0x00000002 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__8 0x00000003 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__16 0x00000004 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS 7:4 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__1 0x00000000 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__2 0x00000001 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__4 0x00000002 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__8 0x00000003 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__16 0x00000004 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__32 0x00000005 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__64 0x00000006 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__128 0x00000007 + +#define NV9097_SET_BINDING_CONTROL_RESERVED_A(j) (0x2204+(j)*16) +#define NV9097_SET_BINDING_CONTROL_RESERVED_A_V 0:0 + +#define NV9097_SET_BINDING_CONTROL_RESERVED_B(j) (0x2208+(j)*16) +#define NV9097_SET_BINDING_CONTROL_RESERVED_B_V 0:0 + +#define NV9097_SET_FALCON00 0x2300 +#define NV9097_SET_FALCON00_V 31:0 + +#define NV9097_SET_FALCON01 0x2304 +#define NV9097_SET_FALCON01_V 31:0 + +#define NV9097_SET_FALCON02 0x2308 +#define NV9097_SET_FALCON02_V 31:0 + +#define NV9097_SET_FALCON03 0x230c +#define NV9097_SET_FALCON03_V 31:0 + +#define NV9097_SET_FALCON04 0x2310 +#define NV9097_SET_FALCON04_V 31:0 + +#define NV9097_SET_FALCON05 0x2314 +#define NV9097_SET_FALCON05_V 31:0 + +#define NV9097_SET_FALCON06 0x2318 +#define NV9097_SET_FALCON06_V 31:0 + +#define NV9097_SET_FALCON07 0x231c +#define NV9097_SET_FALCON07_V 31:0 + +#define NV9097_SET_FALCON08 0x2320 +#define NV9097_SET_FALCON08_V 31:0 + +#define NV9097_SET_FALCON09 0x2324 +#define NV9097_SET_FALCON09_V 31:0 + +#define NV9097_SET_FALCON10 0x2328 +#define NV9097_SET_FALCON10_V 31:0 + +#define NV9097_SET_FALCON11 0x232c +#define NV9097_SET_FALCON11_V 31:0 + +#define NV9097_SET_FALCON12 0x2330 +#define NV9097_SET_FALCON12_V 31:0 + +#define NV9097_SET_FALCON13 0x2334 +#define NV9097_SET_FALCON13_V 31:0 + +#define NV9097_SET_FALCON14 0x2338 +#define NV9097_SET_FALCON14_V 31:0 + +#define NV9097_SET_FALCON15 0x233c +#define NV9097_SET_FALCON15_V 31:0 + +#define NV9097_SET_FALCON16 0x2340 +#define NV9097_SET_FALCON16_V 31:0 + +#define NV9097_SET_FALCON17 0x2344 +#define NV9097_SET_FALCON17_V 31:0 + +#define NV9097_SET_FALCON18 0x2348 +#define NV9097_SET_FALCON18_V 31:0 + +#define NV9097_SET_FALCON19 0x234c +#define NV9097_SET_FALCON19_V 31:0 + +#define NV9097_SET_FALCON20 0x2350 +#define NV9097_SET_FALCON20_V 31:0 + +#define NV9097_SET_FALCON21 0x2354 +#define NV9097_SET_FALCON21_V 31:0 + +#define NV9097_SET_FALCON22 0x2358 +#define NV9097_SET_FALCON22_V 31:0 + +#define NV9097_SET_FALCON23 0x235c +#define NV9097_SET_FALCON23_V 31:0 + +#define NV9097_SET_FALCON24 0x2360 +#define NV9097_SET_FALCON24_V 31:0 + +#define NV9097_SET_FALCON25 0x2364 +#define NV9097_SET_FALCON25_V 31:0 + +#define NV9097_SET_FALCON26 0x2368 +#define NV9097_SET_FALCON26_V 31:0 + +#define NV9097_SET_FALCON27 0x236c +#define NV9097_SET_FALCON27_V 31:0 + +#define NV9097_SET_FALCON28 0x2370 +#define NV9097_SET_FALCON28_V 31:0 + +#define NV9097_SET_FALCON29 0x2374 +#define NV9097_SET_FALCON29_V 31:0 + +#define NV9097_SET_FALCON30 0x2378 +#define NV9097_SET_FALCON30_V 31:0 + +#define NV9097_SET_FALCON31 0x237c +#define NV9097_SET_FALCON31_V 31:0 + +#define NV9097_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NV9097_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NV9097_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NV9097_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NV9097_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NV9097_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NV9097_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NV9097_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NV9097_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NV9097_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NV9097_BIND_GROUP_TEXTURE_SAMPLER(j) (0x2400+(j)*32) +#define NV9097_BIND_GROUP_TEXTURE_SAMPLER_VALID 0:0 +#define NV9097_BIND_GROUP_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 +#define NV9097_BIND_GROUP_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 +#define NV9097_BIND_GROUP_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 +#define NV9097_BIND_GROUP_TEXTURE_SAMPLER_INDEX 24:12 + +#define NV9097_BIND_GROUP_TEXTURE_HEADER(j) (0x2404+(j)*32) +#define NV9097_BIND_GROUP_TEXTURE_HEADER_VALID 0:0 +#define NV9097_BIND_GROUP_TEXTURE_HEADER_VALID_FALSE 0x00000000 +#define NV9097_BIND_GROUP_TEXTURE_HEADER_VALID_TRUE 0x00000001 +#define NV9097_BIND_GROUP_TEXTURE_HEADER_TEXTURE_SLOT 8:1 +#define NV9097_BIND_GROUP_TEXTURE_HEADER_INDEX 30:9 + +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_SAMPLER(j) (0x2408+(j)*32) +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_SAMPLER_VALID 0:0 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_SAMPLER_INDEX 24:12 + +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_HEADER(j) (0x240c+(j)*32) +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_HEADER_VALID 0:0 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_HEADER_VALID_FALSE 0x00000000 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_HEADER_VALID_TRUE 0x00000001 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_HEADER_TEXTURE_SLOT 8:1 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_HEADER_INDEX 30:9 + +#define NV9097_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NV9097_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NV9097_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NV9097_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NV9097_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NV9097_RESERVED_GROUP_B_RESERVED_A(j) (0x2500+(j)*32) +#define NV9097_RESERVED_GROUP_B_RESERVED_A_V 0:0 + +#define NV9097_RESERVED_GROUP_B_RESERVED_B(j) (0x2504+(j)*32) +#define NV9097_RESERVED_GROUP_B_RESERVED_B_V 0:0 + +#define NV9097_RESERVED_GROUP_B_RESERVED_C(j) (0x2508+(j)*32) +#define NV9097_RESERVED_GROUP_B_RESERVED_C_V 0:0 + +#define NV9097_RESERVED_GROUP_B_RESERVED_D(j) (0x250c+(j)*32) +#define NV9097_RESERVED_GROUP_B_RESERVED_D_V 0:0 + +#define NV9097_RESERVED_GROUP_B_RESERVED_E(j) (0x2510+(j)*32) +#define NV9097_RESERVED_GROUP_B_RESERVED_E_V 0:0 + +#define NV9097_SET_COLOR_CLAMP 0x2600 +#define NV9097_SET_COLOR_CLAMP_ENABLE 0:0 +#define NV9097_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NV9097_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SU_LD_ST_TARGET_A(j) (0x2700+(j)*32) +#define NV9097_SET_SU_LD_ST_TARGET_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_SU_LD_ST_TARGET_B(j) (0x2704+(j)*32) +#define NV9097_SET_SU_LD_ST_TARGET_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_SU_LD_ST_TARGET_C(j) (0x2708+(j)*32) +#define NV9097_SET_SU_LD_ST_TARGET_C_WIDTH 31:0 + +#define NV9097_SET_SU_LD_ST_TARGET_D(j) (0x270c+(j)*32) +#define NV9097_SET_SU_LD_ST_TARGET_D_HEIGHT 16:0 +#define NV9097_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY 20:20 +#define NV9097_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_BLOCKLINEAR 0x00000000 +#define NV9097_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_PITCH 0x00000001 + +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT(j) (0x2710+(j)*32) +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_TYPE 0:0 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_TYPE_COLOR 0x00000000 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_TYPE_ZETA 0x00000001 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR 11:4 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_DISABLED 0x00000000 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_AF32 0x000000C0 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_AS32 0x000000C1 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_AU32 0x000000C2 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_X32 0x000000C3 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_X32 0x000000C4 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_X32 0x000000C5 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16_B16_A16 0x000000C6 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16_BN16_AN16 0x000000C7 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16_BS16_AS16 0x000000C8 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16_BU16_AU16 0x000000C9 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_AF16 0x000000CA +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32 0x000000CB +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32 0x000000CC +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32 0x000000CD +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_X16 0x000000CE +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8G8B8 0x000000CF +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8RL8GL8BL8 0x000000D0 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2B10G10R10 0x000000D1 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU2BU10GU10RU10 0x000000D2 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8B8G8R8 0x000000D5 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8BL8GL8RL8 0x000000D6 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AN8BN8GN8RN8 0x000000D7 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AS8BS8GS8RS8 0x000000D8 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU8BU8GU8RU8 0x000000D9 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16 0x000000DA +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16 0x000000DB +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16 0x000000DC +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16 0x000000DD +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16 0x000000DE +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2R10G10B10 0x000000DF +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_BF10GF11RF11 0x000000E0 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32 0x000000E3 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32 0x000000E4 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32 0x000000E5 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8R8G8B8 0x000000E6 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8RL8GL8BL8 0x000000E7 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R5G6B5 0x000000E8 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A1R5G5B5 0x000000E9 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_G8R8 0x000000EA +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GN8RN8 0x000000EB +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GS8RS8 0x000000EC +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GU8RU8 0x000000ED +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16 0x000000EE +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16 0x000000EF +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16 0x000000F0 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16 0x000000F1 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16 0x000000F2 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R8 0x000000F3 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN8 0x000000F4 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS8 0x000000F5 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU8 0x000000F6 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8 0x000000F7 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X1R5G5B5 0x000000F8 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8B8G8R8 0x000000F9 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8BL8GL8RL8 0x000000FA +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z1R5G5B5 0x000000FB +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O1R5G5B5 0x000000FC +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z8R8G8B8 0x000000FD +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O8R8G8B8 0x000000FE +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R32 0x000000FF +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A16 0x00000040 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF16 0x00000041 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF32 0x00000042 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8 0x00000043 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_A16 0x00000044 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_AF16 0x00000045 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_AF32 0x00000046 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA 16:12 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z16 0x00000013 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z24S8 0x00000014 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24 0x00000015 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_S8Z24 0x00000016 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_V8Z24 0x00000018 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32 0x0000000A +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X24S8 0x00000019 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24_X16V8S8 0x0000001D +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8X8 0x0000001E +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8S8 0x0000001F + +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE(j) (0x2714+(j)*32) +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH 3:0 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT 7:4 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 + +#define NV9097_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NV9097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NV9097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NV9097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NV9097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 2:0 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 6:4 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 10:8 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 14:12 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 18:16 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 22:20 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 26:24 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 30:28 + +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NV9097_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NV9097_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NV9097_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NV9097_CALL_MME_MACRO_V 31:0 + +#define NV9097_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NV9097_CALL_MME_DATA_V 31:0 + +#endif /* _cl_fermi_a_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl90cc.h b/userspace/sdks/nv525/nvidia/inc/class/cl90cc.h new file mode 100644 index 0000000..25d8570 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl90cc.h @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl90cc_h_ +#define _cl90cc_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define GF100_PROFILER (0x000090CC) + +/* + * Creating the GF100_PROFILER object: + * - The profiler object is instantiated as a child of either the subdevice or + * a channel group or channel, depending on whether reservations + * should be global to the subdevice or per-context. When the profiler + * requests a reservation or information about outstanding reservations, the + * scope of the request is determined by the profiler object's parent class. + */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl90cc_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl90cd.h b/userspace/sdks/nv525/nvidia/inc/class/cl90cd.h new file mode 100644 index 0000000..6c626a6 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl90cd.h @@ -0,0 +1,237 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * NV_EVENT_BUFFER + * An event buffer is shared between user (RO) and kernel(RW). + * It holds debug/profile event data provided by the kernel. + * + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl90cd.finn +// + +#define NV_EVENT_BUFFER (0x90cdU) /* finn: Evaluated from "NV_EVENT_BUFFER_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* + * NV_EVENT_BUFFER_HEADER + * This structure holds the get and put values used to index/consume event buffer. + * Along with other RO data shared with the user. + * + * recordGet/Put: These "pointers" work in the traditional sense: + * - when GET==PUT, the fifo is empty + * - when GET==PUT+1, the fifo is full + * This implies a full fifo always has one "wasted" element. + * + * recordCount: This is the total number of records added to the buffer by the kernel + * This information is filled out when the buffer is setup to keep newest records. + * recordCount = number of records currently in the buffer + overflow count. + * + * recordDropcount: This is the number of event records that are dropped because the + * buffer is full. + * This information is filled out when event buffer is setup to keep oldest records. + * + * vardataDropcount: Event buffer provides a dual stream of data, where the record can contain + * an optional offset to a variable length data buffer. + * This is the number of variable data records that are dropped because the + * buffer is full. + * This information is filled out when event buffer is setup to keep oldest records. + */ +typedef struct NV_EVENT_BUFFER_HEADER { + NvU32 recordGet; + NvU32 recordPut; + NV_DECLARE_ALIGNED(NvU64 recordCount, 8); + NV_DECLARE_ALIGNED(NvU64 recordDropcount, 8); + NV_DECLARE_ALIGNED(NvU64 vardataDropcount, 8); +} NV_EVENT_BUFFER_HEADER; + +/* + * NV_EVENT_BUFFER_RECORD_HEADER + * This is the header added to each event record. + * This helps identify the event type and variable length data is associated with it. + */ +typedef struct NV_EVENT_BUFFER_RECORD_HEADER { + NvU16 type; + NvU16 subtype; + NvU32 varData; // [31: 5] = (varDataOffset >> 5); 0 < vardataOffset <= vardataBufferSize + // [ 4: 1] = reserved for future use + // [ 0: 0] = isVardataStartOffsetZero +} NV_EVENT_BUFFER_RECORD_HEADER; + +/* + * NV_EVENT_BUFFER_RECORD + * This structure defines a generic event record. + * The size of this record is fixed for a given event buffer. + * It is configured by the user during allocation. + */ +typedef struct NV_EVENT_BUFFER_RECORD { + NV_EVENT_BUFFER_RECORD_HEADER recordHeader; + NV_DECLARE_ALIGNED(NvU64 inlinePayload[1], 8); // 1st element of the payload/data + // Do not add more elements here, inlinePayload can contain more than one elements +} NV_EVENT_BUFFER_RECORD; + +#define NV_EVENT_VARDATA_GRANULARITY 32 +#define NV_EVENT_VARDATA_OFFSET_MASK (~(NV_EVENT_VARDATA_GRANULARITY - 1)) +#define NV_EVENT_VARDATA_START_OFFSET_ZERO 0x01 + +/* + * NV_EVENT_BUFFER_ALLOC_PARAMETERS + * + * bufferHeader [OUT] + * This is the user VA offset pointing to the base of NV_EVENT_BUFFER_HEADER. + * + * recordBuffer [OUT] + * This is the user VA offset pointing to the base of the event record buffer. + * This buffer will contain NV_EVENT_BUFFER_RECORDs added by the kernel. + * + * recordSize [IN] + * This is the size of NV_EVENT_BUFFER_RECORD used by this buffer + * + * recordCount [IN] + * This is the number of records that recordBuffer can hold. + * + * vardataBuffer [OUT] + * This is the user VA offset pointing to the base of the variable data buffer. + * + * vardataBufferSize [IN] + * Size of the variable data buffer in bytes. + * + * recordsFreeThreshold [IN] + * This is the notification threshold for the event record buffer. + * This felid specifies the number of records that the buffer can + * still hold before it gets full. + * + * vardataFreeThreshold [IN] + * This is the notification threshold for the vardata buffer. + * This felid specifies the number of bytes that the buffer can + * still hold before it gets full. + * + * notificationHandle [IN] + * When recordsFreeThreshold or vardataFreeThreshold is met, kernel will notify + * user on this handle. If notificationHandle = NULL, event notification + * is disabled. This is an OS specific notification handle. + * It is a Windows event handle or a fd pointer on Linux. + * + * hSubDevice [IN] + * An event buffer can either hold sub-device related events or system events. + * This handle specifies the sub-device to associate this buffer with. + * If this parameter is NULL, then the buffer is tied to the client instead. + * + * flags [IN] + * Set to 0 by default. + * This field can hold any future flags to configure the buffer if needed. + * + * hBufferHeader [IN] + * The backing memory object for the buffer header. Must be a NV01_MEMORY_DEVICELESS object. + * On Windows platforms, a buffer will be internally generated if hBufferHeader is 0. + * + * hRecordBuffer [IN] + * The backing memory object for the record buffer. Must be a NV01_MEMORY_DEVICELESS object. + * On Windows platforms, a buffer will be internally generated if hRecordBuffer is 0. + * + * hVardataBuffer [IN] + * The backing memory object for the vardata buffer. Must be a NV01_MEMORY_DEVICELESS object. + * On Windows platforms, a buffer will be internally generated if hVardataBuffer is 0. + * + */ +#define NV_EVENT_BUFFER_ALLOC_PARAMETERS_MESSAGE_ID (0x90cdU) + +typedef struct NV_EVENT_BUFFER_ALLOC_PARAMETERS { + NV_DECLARE_ALIGNED(NvP64 bufferHeader, 8); + NV_DECLARE_ALIGNED(NvP64 recordBuffer, 8); + NvU32 recordSize; + NvU32 recordCount; + NV_DECLARE_ALIGNED(NvP64 vardataBuffer, 8); + NvU32 vardataBufferSize; + NvU32 recordsFreeThreshold; + NV_DECLARE_ALIGNED(NvU64 notificationHandle, 8); + NvU32 vardataFreeThreshold; + NvHandle hSubDevice; + NvU32 flags; + + NvHandle hBufferHeader; + NvHandle hRecordBuffer; + NvHandle hVardataBuffer; +} NV_EVENT_BUFFER_ALLOC_PARAMETERS; + +/* + * NV_EVENT_BUFFER_BIND + * This class is used to allocate an Event Type object bound to a given event buffer. + * This allocation call associates an event type with an event buffer. + * Multiple event types can be associated with the same buffer as long as they belong to + * the same category i.e. either sub-device or system. + * When event buffer is enabled, if an event bound to this buffer occurs, + * some relevant data gets added to it. + * cl2080.h has a list of sub-device events that can be associated with a buffer + * cl0000.h has a list of system events that can be associated with a buffer + * These defines are also used in class NV01_EVENT_OS_EVENT (0x79) to get event notification + * and class NV01_EVENT_KERNEL_CALLBACK_EX (0x7E) to get kernel callbacks. + * This class extends that support to additionally get relevant data in an event buffer + * + */ +#define NV_EVENT_BUFFER_BIND (0x0000007F) + +/* + * NV_EVENT_BUFFER_BIND_PARAMETERS + * + * bufferHandle [IN] + * Event buffer handle used to bind the given event type + * + * eventType [IN] + * This is one of the eventTypeIDs from cl2080.h/cl000.h + * e.g. NV2080_NOTIFIERS_PSTATE_CHANGE + * + * eventSubtype [IN] + * Event subtype for a given type of event. + * This field is optional depending on if an eventtype has a subtype. + * + * hClientTarget [IN] + * Handle of the target client whose events are to be bound to the given buffer + * e.g. context switch events can be tracked for a given client. + * This field is optional depending on the event type. + * e.g. pstate change events are per gpu but do not depend on a client. + * + * hSrcResource [IN] + * source resource handle for the event type + * e.g. channel handle: RC/context switch can be tracked for a given channel + * This field is optional depending on the event type. + * e.g. pstate change events are per gpu and cannot be sub-categorized + * + * KernelCallbackdata [IN] + * This field is reserved for KERNEL ONLY clients. + * + */ +typedef struct NV_EVENT_BUFFER_BIND_PARAMETERS { + NvHandle bufferHandle; + NvU16 eventType; + NvU16 eventSubtype; + NvHandle hClientTarget; + NvHandle hSrcResource; + NV_DECLARE_ALIGNED(NvP64 KernelCallbackdata, 8); +} NV_EVENT_BUFFER_BIND_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl90cdfecs.h b/userspace/sdks/nv525/nvidia/inc/class/cl90cdfecs.h new file mode 100644 index 0000000..5118249 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl90cdfecs.h @@ -0,0 +1,112 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl90cdFecs_h_ +#define _cl90cdFecs_h_ + +/* This file defines parameters for FECS context switch events*/ + +#define NV_EVENT_BUFFER_FECS_VERSION 2 + +/* + * These are the types of context switch events + * This field gets added to NV_EVENT_BUFFER_FECS_RECORD to specify the sub type of fecs event + * Do *not* edit these as they are defined to maintain consistency with Tegra tools + */ +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_SO 0x00 +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_CTXSW_REQ_BY_HOST 0x01 +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_FE_ACK 0x02 +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_FE_ACK_WFI 0x0a +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_FE_ACK_GFXP 0x0b +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_FE_ACK_CTAP 0x0c +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_FE_ACK_CILP 0x0d +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_SAVE_END 0x03 +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_RESTORE_START 0x04 +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_CONTEXT_START 0x05 +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_SIMPLE_START 0x06 +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_SIMPLE_END 0x07 +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_ENGINE_RESET 0xfe +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_INVALID_TIMESTAMP 0xff +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_LAST NV_EVENT_BUFFER_FECS_EVENTS_CTXSWTAG_INVALID_TIMESTAMP + +/* + * Bit fields used to enable a particular sub type of event + */ +#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_SO NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_SO) +#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_CTXSW_REQ_BY_HOST NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_CTXSW_REQ_BY_HOST) +#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_FE_ACK NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_FE_ACK) +#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_SAVE_END NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_SAVE_END) +#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_RESTORE_START NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_RESTORE_START) +#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_CONTEXT_START NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_CONTEXT_START) +#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_SIMPLE_START NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_SIMPLE_START) +#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_SIMPLE_END NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_SIMPLE_END) + +/* context_id is set to this value if fecs info doesn't match a known channel/tsg handle*/ +#define NV_EVENT_BUFFER_INVALID_CONTEXT 0xFFFFFFFF + +/* + * PID/context_id are set to these values if the data is from another user's + * client and the current user is not an administrator + */ +#define NV_EVENT_BUFFER_HIDDEN_PID 0x0 +#define NV_EVENT_BUFFER_HIDDEN_CONTEXT 0x0 + +/* + * PID/context_id are set to these values if the data is from a kernel client + * and the data is being read by a user client + */ +#define NV_EVENT_BUFFER_KERNEL_PID 0xFFFFFFFF +#define NV_EVENT_BUFFER_KERNEL_CONTEXT 0xFFFFFFFF + +// V1 ------------------------------------------------------------------------ +typedef struct +{ + NvU8 tag; ///< NV_EVENT_BUFFER_FECS_CTXSWTAG_* + NvU8 vmid; + NvU16 seqno; ///< used to detect drop + NvU32 context_id; ///< channel/tsg handle + NvU64 pid NV_ALIGN_BYTES(8); ///< process id + NvU64 timestamp NV_ALIGN_BYTES(8); + /* Do *not* edit items above this to maintain consistency with tegra tools + Always add to the end of this structure to retain backward compatibility */ +} NV_EVENT_BUFFER_FECS_RECORD_V1; + +// V2 ------------------------------------------------------------------------ +typedef struct +{ + NvU8 tag; ///< NV_EVENT_BUFFER_FECS_CTXSWTAG_* + NvU8 vmid; + NvU16 seqno; ///< used to detect drop + NvU32 context_id; ///< channel/tsg handle + NvU32 pid; ///< process id + NvU16 reserved0; + NvU8 migGpuInstanceId; + NvU8 migComputeInstanceId; + NvU64 timestamp NV_ALIGN_BYTES(8); + /* Do *not* edit items above this to maintain consistency with tegra tools + Always add to the end of this structure to retain backward compatibility */ +} NV_EVENT_BUFFER_FECS_RECORD_V2; + +typedef NV_EVENT_BUFFER_FECS_RECORD_V1 NV_EVENT_BUFFER_FECS_RECORD_V0; +typedef NV_EVENT_BUFFER_FECS_RECORD_V1 NV_EVENT_BUFFER_FECS_RECORD; +#endif /* _cl90cdFecs_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl90cdtypes.h b/userspace/sdks/nv525/nvidia/inc/class/cl90cdtypes.h new file mode 100644 index 0000000..f2a40cf --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl90cdtypes.h @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl90cdtypes_h_ +#define _cl90cdtypes_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Legacy values record type values have been kept for backward +// compatibility. New values should be added sequentially. +// +#define NV_EVENT_BUFFER_RECORD_TYPE_INVALID (0) +#define NV_EVENT_BUFFER_RECORD_TYPE_VIDEO_TRACE (1) +#define NV_EVENT_BUFFER_RECORD_TYPE_FECS_CTX_SWITCH_V2 (2) +#define NV_EVENT_BUFFER_RECORD_TYPE_NVTELEMETRY_REPORT_EVENT_SYSTEM (4) +#define NV_EVENT_BUFFER_RECORD_TYPE_NVTELEMETRY_REPORT_EVENT_SUBDEVICE (132) +#define NV_EVENT_BUFFER_RECORD_TYPE_FECS_CTX_SWITCH (134) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _cl90cdtypes_h_ + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl90ce.h b/userspace/sdks/nv525/nvidia/inc/class/cl90ce.h new file mode 100644 index 0000000..b4506df --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl90ce.h @@ -0,0 +1,42 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl90ce_h_ +#define _cl90ce_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* +* NV_MEMORY_DEVICELESS +* Memory that is not associated with a device +*/ +#define NV01_MEMORY_DEVICELESS (0x000090CE) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _cl90ce_h_ + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl90e6.h b/userspace/sdks/nv525/nvidia/inc/class/cl90e6.h new file mode 100644 index 0000000..63348ea --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl90e6.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl90e6_h_ +#define _cl90e6_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define GF100_SUBDEVICE_MASTER (0x000090e6) + +typedef struct { + NvU32 Reserved00[0x400]; /* NV_PMC 0x00000FFF:0x00000000 */ +} Nv90e6MapTypedef, GF100MASTERMap; + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl90e6_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl90ec.h b/userspace/sdks/nv525/nvidia/inc/class/cl90ec.h new file mode 100644 index 0000000..182640a --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl90ec.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl90ec_h_ +#define _cl90ec_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* Class within the subdevice used for communicating with HDACODEC*/ +#define GF100_HDACODEC (0x000090EC) + + /* pio method data structure */ +typedef volatile struct _cl90ec_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv90ECTypedef, GF100Hdacodec; +#define NV90EC_TYPEDEF GF100Hdacodec + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl9071_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl90f1.h b/userspace/sdks/nv525/nvidia/inc/class/cl90f1.h new file mode 100644 index 0000000..7523ef1 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl90f1.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _cl90f1_h_ +#define _cl90f1_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define FERMI_VASPACE_A (0x000090f1) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl90f1_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl9170.h b/userspace/sdks/nv525/nvidia/inc/class/cl9170.h new file mode 100644 index 0000000..478125f --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl9170.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9170.finn +// + +#define NV9170_DISPLAY (0x9170U) /* finn: Evaluated from "NV9170_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV9170_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9170U) + +typedef struct NV9170_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numDacs; // Number of DACs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NV9170_ALLOCATION_PARAMETERS; diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl9171.h b/userspace/sdks/nv525/nvidia/inc/class/cl9171.h new file mode 100644 index 0000000..dcbd90b --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl9171.h @@ -0,0 +1,295 @@ +/* + * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl9171_h_ +#define _cl9171_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV9171_DISP_SF_USER 0x9171 + +typedef volatile struct _cl9171_tag0 { + NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x00690FFF:0x00690000 */ +} _Nv9171DispSfUser, Nv9171DispSfUserMap; + +#define NV9171_SF_HDMI_INFO_IDX_AVI_INFOFRAME 0x00000000 /* */ +#define NV9171_SF_HDMI_INFO_IDX_GENERIC_INFOFRAME 0x00000001 /* */ +#define NV9171_SF_HDMI_INFO_IDX_GCP 0x00000003 /* */ +#define NV9171_SF_HDMI_INFO_IDX_VSI 0x00000004 /* */ +#define NV9171_SF_HDMI_INFO_CTRL(i,j) (0x00690000-0x00690000+(i)*1024+(j)*64) /* RWX4A */ +#define NV9171_SF_HDMI_INFO_CTRL__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_INFO_CTRL__SIZE_2 5 /* */ +#define NV9171_SF_HDMI_INFO_CTRL_ENABLE 0:0 /* RWIVF */ +#define NV9171_SF_HDMI_INFO_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_INFO_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_OTHER 4:4 /* RWIVF */ +#define NV9171_SF_HDMI_INFO_CTRL_OTHER_DIS 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_INFO_CTRL_OTHER_EN 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_SINGLE 8:8 /* RWIVF */ +#define NV9171_SF_HDMI_INFO_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_INFO_CTRL_SINGLE_EN 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_CHKSUM_HW 9:9 /* RWIVF */ +#define NV9171_SF_HDMI_INFO_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_CHKSUM_HW_EN 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_CHKSUM_HW_DIS 0x00000000 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */ +#define NV9171_SF_HDMI_INFO_CTRL_HBLANK 12:12 /* RWIVF */ +#define NV9171_SF_HDMI_INFO_CTRL_HBLANK_DIS 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_INFO_CTRL_HBLANK_EN 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_VIDEO_FMT 16:16 /* RWIVF */ +#define NV9171_SF_HDMI_INFO_CTRL_VIDEO_FMT_SW_CONTROLLED 0x00000000 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_VIDEO_FMT_HW_CONTROLLED 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_VIDEO_FMT_INIT 0x00000001 /* RWI-V */ +#define NV9171_SF_HDMI_INFO_STATUS(i,j) (0x00690004-0x00690000+(i)*1024+(j)*64) /* R--4A */ +#define NV9171_SF_HDMI_INFO_STATUS__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_INFO_STATUS__SIZE_2 5 /* */ +#define NV9171_SF_HDMI_INFO_STATUS_SENT 0:0 /* R--VF */ +#define NV9171_SF_HDMI_INFO_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NV9171_SF_HDMI_INFO_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NV9171_SF_HDMI_INFO_STATUS_SENT_INIT 0x00000000 /* R-I-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x00690000-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x00690008-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x0069000C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x00690010-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x00690014-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x00690018-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_HEADER(i) (0x00690048-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_HEADER__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_HEADER_HB0 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_HEADER_HB1 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_HEADER_HB2 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW(i) (0x0069004C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH(i) (0x00690050-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW(i) (0x00690054-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH(i) (0x00690058-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW(i) (0x0069005C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH(i) (0x00690060-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW(i) (0x00690064-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH(i) (0x00690068-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GCP_SUBPACK(i) (0x006900CC-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GCP_SUBPACK__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GCP_SUBPACK_SB0 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GCP_SUBPACK_SB0_INIT 0x00000001 /* RWI-V */ +#define NV9171_SF_HDMI_GCP_SUBPACK_SB0_SET_AVMUTE 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_GCP_SUBPACK_SB0_CLR_AVMUTE 0x00000010 /* RW--V */ +#define NV9171_SF_HDMI_GCP_SUBPACK_SB1 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GCP_SUBPACK_SB1_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GCP_SUBPACK_SB2 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GCP_SUBPACK_SB2_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_HEADER(i) (0x00690108-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_HEADER__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_HEADER_HB0 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_HEADER_HB1 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_HEADER_HB2 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW(i) (0x0069010C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH(i) (0x00690110-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW(i) (0x00690114-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH(i) (0x00690118-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW(i) (0x0069011C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH(i) (0x00690120-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW(i) (0x00690124-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB21 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB22 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB23 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB24 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH(i) (0x00690128-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _cl9171_h_ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl917a.h b/userspace/sdks/nv525/nvidia/inc/class/cl917a.h new file mode 100644 index 0000000..b6d6239 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl917a.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl917a_h_ +#define _cl917a_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV917A_CURSOR_CHANNEL_PIO (0x0000917A) + +typedef volatile struct { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x1D]; + NvV32 Update; // 0x00000080 - 0x00000083 + NvV32 SetCursorHotSpotPointsOut[2]; // 0x00000084 - 0x0000008B + NvV32 Reserved02[0x3DD]; +} GK104DispCursorControlPio; + +#define NV917A_FREE (0x00000008) +#define NV917A_FREE_COUNT 5:0 +#define NV917A_UPDATE (0x00000080) +#define NV917A_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV917A_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV917A_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV917A_SET_CURSOR_HOT_SPOT_POINTS_OUT(b) (0x00000084 + (b)*0x00000004) +#define NV917A_SET_CURSOR_HOT_SPOT_POINTS_OUT_X 15:0 +#define NV917A_SET_CURSOR_HOT_SPOT_POINTS_OUT_Y 31:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl917a_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl917b.h b/userspace/sdks/nv525/nvidia/inc/class/cl917b.h new file mode 100644 index 0000000..05270e2 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl917b.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl917b_h_ +#define _cl917b_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV917B_OVERLAY_IMM_CHANNEL_PIO (0x0000917B) + +typedef volatile struct { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x1D]; + NvV32 Update; // 0x00000080 - 0x00000083 + NvV32 SetPointsOut[2]; // 0x00000084 - 0x0000008B + NvV32 Reserved02[0x1]; + NvV32 AwakenOnceFlippedTo; // 0x00000090 - 0x00000093 + NvV32 Reserved03[0x3DB]; +} GK104DispOverlayImmControlPio; + +#define NV917B_FREE (0x00000008) +#define NV917B_FREE_COUNT 5:0 +#define NV917B_UPDATE (0x00000080) +#define NV917B_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV917B_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV917B_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV917B_SET_POINTS_OUT(b) (0x00000084 + (b)*0x00000004) +#define NV917B_SET_POINTS_OUT_X 15:0 +#define NV917B_SET_POINTS_OUT_Y 31:16 +#define NV917B_AWAKEN_ONCE_FLIPPED_TO (0x00000090) +#define NV917B_AWAKEN_ONCE_FLIPPED_TO_AWAKEN_COUNT 11:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl917b_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl917c.h b/userspace/sdks/nv525/nvidia/inc/class/cl917c.h new file mode 100644 index 0000000..2b7c6a2 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl917c.h @@ -0,0 +1,298 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl917c_h_ +#define _cl917c_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV917C_BASE_CHANNEL_DMA (0x0000917C) + +#define NV_DISP_BASE_NOTIFIER_1 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1_SIZEOF 0x00000004 +#define NV_DISP_BASE_NOTIFIER_1__0 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT 15:0 +#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP 29:16 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS 31:30 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED 0x00000002 + + +#define NV_DISP_NOTIFICATION_2 0x00000000 +#define NV_DISP_NOTIFICATION_2_SIZEOF 0x00000010 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0 0x00000000 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0_NANOSECONDS0 31:0 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1 0x00000001 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1_NANOSECONDS1 31:0 +#define NV_DISP_NOTIFICATION_2_INFO32_2 0x00000002 +#define NV_DISP_NOTIFICATION_2_INFO32_2_R0 31:0 +#define NV_DISP_NOTIFICATION_2_INFO16_3 0x00000003 +#define NV_DISP_NOTIFICATION_2_INFO16_3_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_2_INFO16_3_FIELD 8:8 +#define NV_DISP_NOTIFICATION_2_INFO16_3_R1 15:9 +#define NV_DISP_NOTIFICATION_2__3_STATUS 31:16 +#define NV_DISP_NOTIFICATION_2__3_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_2__3_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_2__3_STATUS_FINISHED 0x00000000 + + +#define NV_DISP_NOTIFICATION_INFO16 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_INFO16__0 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_INFO16__0_FIELD 8:8 +#define NV_DISP_NOTIFICATION_INFO16__0_R1 15:9 + + +#define NV_DISP_NOTIFICATION_STATUS 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_STATUS__0 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS 15:0 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED 0x00000000 + + +// dma opcode instructions +#define NV917C_DMA 0x00000000 +#define NV917C_DMA_OPCODE 31:29 +#define NV917C_DMA_OPCODE_METHOD 0x00000000 +#define NV917C_DMA_OPCODE_JUMP 0x00000001 +#define NV917C_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV917C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV917C_DMA_OPCODE 31:29 +#define NV917C_DMA_OPCODE_METHOD 0x00000000 +#define NV917C_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV917C_DMA_METHOD_COUNT 27:18 +#define NV917C_DMA_METHOD_OFFSET 11:2 +#define NV917C_DMA_DATA 31:0 +#define NV917C_DMA_DATA_NOP 0x00000000 +#define NV917C_DMA_OPCODE 31:29 +#define NV917C_DMA_OPCODE_JUMP 0x00000001 +#define NV917C_DMA_JUMP_OFFSET 11:2 +#define NV917C_DMA_OPCODE 31:29 +#define NV917C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV917C_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV917C_PUT (0x00000000) +#define NV917C_PUT_PTR 11:2 +#define NV917C_GET (0x00000004) +#define NV917C_GET_PTR 11:2 +#define NV917C_GET_SCANLINE (0x00000010) +#define NV917C_GET_SCANLINE_LINE 15:0 +#define NV917C_UPDATE (0x00000080) +#define NV917C_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV917C_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV917C_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV917C_UPDATE_SPECIAL_HANDLING 25:24 +#define NV917C_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV917C_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV917C_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV917C_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV917C_SET_PRESENT_CONTROL (0x00000084) +#define NV917C_SET_PRESENT_CONTROL_BEGIN_MODE 9:8 +#define NV917C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NV917C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NV917C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE (0x00000002) +#define NV917C_SET_PRESENT_CONTROL_STEREO_FLIP_MODE 3:3 +#define NV917C_SET_PRESENT_CONTROL_STEREO_FLIP_MODE_PAIR_FLIP (0x00000000) +#define NV917C_SET_PRESENT_CONTROL_STEREO_FLIP_MODE_AT_ANY_FRAME (0x00000001) +#define NV917C_SET_PRESENT_CONTROL_TIMESTAMP_MODE 2:2 +#define NV917C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000) +#define NV917C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001) +#define NV917C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV917C_SET_PRESENT_CONTROL_BEGIN_LINE 30:16 +#define NV917C_SET_PRESENT_CONTROL_ON_LINE_MARGIN 15:10 +#define NV917C_SET_PRESENT_CONTROL_MODE 1:0 +#define NV917C_SET_PRESENT_CONTROL_MODE_MONO (0x00000000) +#define NV917C_SET_PRESENT_CONTROL_MODE_STEREO (0x00000001) +#define NV917C_SET_PRESENT_CONTROL_MODE_SPEC_FLIP (0x00000002) +#define NV917C_SET_SEMAPHORE_CONTROL (0x00000088) +#define NV917C_SET_SEMAPHORE_CONTROL_OFFSET 11:2 +#define NV917C_SET_SEMAPHORE_CONTROL_DELAY 26:26 +#define NV917C_SET_SEMAPHORE_CONTROL_DELAY_DISABLE (0x00000000) +#define NV917C_SET_SEMAPHORE_CONTROL_DELAY_ENABLE (0x00000001) +#define NV917C_SET_SEMAPHORE_CONTROL_FORMAT 28:28 +#define NV917C_SET_SEMAPHORE_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV917C_SET_SEMAPHORE_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV917C_SET_SEMAPHORE_ACQUIRE (0x0000008C) +#define NV917C_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NV917C_SET_SEMAPHORE_RELEASE (0x00000090) +#define NV917C_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NV917C_SET_CONTEXT_DMA_SEMAPHORE (0x00000094) +#define NV917C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NV917C_SET_NOTIFIER_CONTROL (0x000000A0) +#define NV917C_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV917C_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV917C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV917C_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV917C_SET_NOTIFIER_CONTROL_DELAY 26:26 +#define NV917C_SET_NOTIFIER_CONTROL_DELAY_DISABLE (0x00000000) +#define NV917C_SET_NOTIFIER_CONTROL_DELAY_ENABLE (0x00000001) +#define NV917C_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV917C_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV917C_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV917C_SET_CONTEXT_DMA_NOTIFIER (0x000000A4) +#define NV917C_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV917C_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0x00000004) +#define NV917C_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV917C_SET_BASE_LUT_LO (0x000000E0) +#define NV917C_SET_BASE_LUT_LO_ENABLE 31:30 +#define NV917C_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV917C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001) +#define NV917C_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000002) +#define NV917C_SET_BASE_LUT_LO_MODE 27:24 +#define NV917C_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV917C_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV917C_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV917C_SET_BASE_LUT_HI (0x000000E4) +#define NV917C_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV917C_SET_OUTPUT_LUT_LO (0x000000E8) +#define NV917C_SET_OUTPUT_LUT_LO_ENABLE 31:30 +#define NV917C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV917C_SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001) +#define NV917C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000002) +#define NV917C_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV917C_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV917C_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV917C_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV917C_SET_OUTPUT_LUT_HI (0x000000EC) +#define NV917C_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV917C_SET_CONTEXT_DMA_LUT (0x000000FC) +#define NV917C_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV917C_SET_PROCESSING (0x00000110) +#define NV917C_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV917C_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV917C_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV917C_SET_CONVERSION_RED (0x00000114) +#define NV917C_SET_CONVERSION_RED_GAIN 15:0 +#define NV917C_SET_CONVERSION_RED_OFS 31:16 +#define NV917C_SET_CONVERSION_GRN (0x00000118) +#define NV917C_SET_CONVERSION_GRN_GAIN 15:0 +#define NV917C_SET_CONVERSION_GRN_OFS 31:16 +#define NV917C_SET_CONVERSION_BLU (0x0000011C) +#define NV917C_SET_CONVERSION_BLU_GAIN 15:0 +#define NV917C_SET_CONVERSION_BLU_OFS 31:16 +#define NV917C_SET_TIMESTAMP_ORIGIN_LO (0x00000130) +#define NV917C_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NV917C_SET_TIMESTAMP_ORIGIN_HI (0x00000134) +#define NV917C_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NV917C_SET_UPDATE_TIMESTAMP_LO (0x00000138) +#define NV917C_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NV917C_SET_UPDATE_TIMESTAMP_HI (0x0000013C) +#define NV917C_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NV917C_SET_CSC_RED2RED (0x00000140) +#define NV917C_SET_CSC_RED2RED_OWNER 31:31 +#define NV917C_SET_CSC_RED2RED_OWNER_CORE (0x00000000) +#define NV917C_SET_CSC_RED2RED_OWNER_BASE (0x00000001) +#define NV917C_SET_CSC_RED2RED_COEFF 18:0 +#define NV917C_SET_CSC_GRN2RED (0x00000144) +#define NV917C_SET_CSC_GRN2RED_COEFF 18:0 +#define NV917C_SET_CSC_BLU2RED (0x00000148) +#define NV917C_SET_CSC_BLU2RED_COEFF 18:0 +#define NV917C_SET_CSC_CONSTANT2RED (0x0000014C) +#define NV917C_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV917C_SET_CSC_RED2GRN (0x00000150) +#define NV917C_SET_CSC_RED2GRN_COEFF 18:0 +#define NV917C_SET_CSC_GRN2GRN (0x00000154) +#define NV917C_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV917C_SET_CSC_BLU2GRN (0x00000158) +#define NV917C_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV917C_SET_CSC_CONSTANT2GRN (0x0000015C) +#define NV917C_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV917C_SET_CSC_RED2BLU (0x00000160) +#define NV917C_SET_CSC_RED2BLU_COEFF 18:0 +#define NV917C_SET_CSC_GRN2BLU (0x00000164) +#define NV917C_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV917C_SET_CSC_BLU2BLU (0x00000168) +#define NV917C_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV917C_SET_CSC_CONSTANT2BLU (0x0000016C) +#define NV917C_SET_CSC_CONSTANT2BLU_COEFF 18:0 +#define NV917C_SET_SPARE (0x000003BC) +#define NV917C_SET_SPARE_UNUSED 31:0 +#define NV917C_SET_SPARE_NOOP(b) (0x000003C0 + (b)*0x00000004) +#define NV917C_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV917C_SURFACE_SET_OFFSET(a,b) (0x00000400 + (a)*0x00000020 + (b)*0x00000004) +#define NV917C_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV917C_SURFACE_SET_SIZE(a) (0x00000408 + (a)*0x00000020) +#define NV917C_SURFACE_SET_SIZE_WIDTH 15:0 +#define NV917C_SURFACE_SET_SIZE_HEIGHT 31:16 +#define NV917C_SURFACE_SET_STORAGE(a) (0x0000040C + (a)*0x00000020) +#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV917C_SURFACE_SET_STORAGE_PITCH 20:8 +#define NV917C_SURFACE_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV917C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV917C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV917C_SURFACE_SET_PARAMS(a) (0x00000410 + (a)*0x00000020) +#define NV917C_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV917C_SURFACE_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV917C_SURFACE_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV917C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV917C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV917C_SURFACE_SET_PARAMS_GAMMA 2:2 +#define NV917C_SURFACE_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV917C_SURFACE_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV917C_SURFACE_SET_PARAMS_LAYOUT 5:4 +#define NV917C_SURFACE_SET_PARAMS_LAYOUT_FRM (0x00000000) +#define NV917C_SURFACE_SET_PARAMS_LAYOUT_FLD1 (0x00000001) +#define NV917C_SURFACE_SET_PARAMS_LAYOUT_FLD2 (0x00000002) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl917c_h diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl917cswspare.h b/userspace/sdks/nv525/nvidia/inc/class/cl917cswspare.h new file mode 100644 index 0000000..39e88c0 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl917cswspare.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl917c_sw_spare_h_ +#define _cl917c_sw_spare_h_ + +/* This file is *not* auto-generated. */ + +/* NV917C_SET_SPARE_PRE_UPDATE_TRAP is an alias of NV917C_SET_SPARE_NOOP(0) */ +#define NV917C_SET_SPARE_PRE_UPDATE_TRAP (0x000003C0) +#define NV917C_SET_SPARE_PRE_UPDATE_TRAP_UNUSED 31:0 + +/* NV917C_SET_SPARE_POST_UPDATE_TRAP is an alias of NV917C_SET_SPARE_NOOP(1) */ +#define NV917C_SET_SPARE_POST_UPDATE_TRAP (0x000003C4) +#define NV917C_SET_SPARE_POST_UPDATE_TRAP_UNUSED 31:0 + + +#endif /* _cl917c_sw_spare_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl917d.h b/userspace/sdks/nv525/nvidia/inc/class/cl917d.h new file mode 100644 index 0000000..4f70d81 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl917d.h @@ -0,0 +1,1551 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl917d_h_ +#define _cl917d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV917D_CORE_CHANNEL_DMA (0x0000917D) + +#define NV917D_CORE_NOTIFIER_3 0x00000000 +#define NV917D_CORE_NOTIFIER_3_SIZEOF 0x00000150 +#define NV917D_CORE_NOTIFIER_3_COMPLETION_0 0x00000000 +#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_DONE 0:0 +#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_R0 15:1 +#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP 29:16 +#define NV917D_CORE_NOTIFIER_3__1 0x00000001 +#define NV917D_CORE_NOTIFIER_3__1_R1 31:0 +#define NV917D_CORE_NOTIFIER_3__2 0x00000002 +#define NV917D_CORE_NOTIFIER_3__2_R2 31:0 +#define NV917D_CORE_NOTIFIER_3__3 0x00000003 +#define NV917D_CORE_NOTIFIER_3__3_R3 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_R0 19:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA 20:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_R1 29:21 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE 30:30 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5 0x00000005 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE 3:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE 11:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE 15:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE 19:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE 27:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE 31:28 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6 0x00000006 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE 3:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE 11:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE 15:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE 19:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE 27:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE 31:28 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_7 0x00000007 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_7_R4 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_8 0x00000008 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_8_R5 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_9 0x00000009 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_9_R6 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_10 0x0000000A +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_10_R7 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_11 0x0000000B +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_11_R8 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12 0x0000000C +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0 31:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13 0x0000000D +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14 0x0000000E +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0 31:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15 0x0000000F +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16 0x00000010 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0 31:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17 0x00000011 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18 0x00000012 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0 31:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19 0x00000013 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21 0x00000015 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22 0x00000016 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23 0x00000017 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24 0x00000018 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25 0x00000019 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26 0x0000001A +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27 0x0000001B +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28 0x0000001C +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29 0x0000001D +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30 0x0000001E +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31 0x0000001F +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32 0x00000020 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33 0x00000021 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34 0x00000022 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35 0x00000023 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36 0x00000024 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0 31:7 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37 0x00000025 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38 0x00000026 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0 31:7 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39 0x00000027 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40 0x00000028 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0 31:7 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41 0x00000029 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42 0x0000002A +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0 31:7 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43 0x0000002B +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44 0x0000002C +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45 0x0000002D +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45_R1 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46 0x0000002E +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47 0x0000002F +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47_R1 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48 0x00000030 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49 0x00000031 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49_R1 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50 0x00000032 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51 0x00000033 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51_R1 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52 0x00000034 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53 0x00000035 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54 0x00000036 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55 0x00000037 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56 0x00000038 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57 0x00000039 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58 0x0000003A +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59 0x0000003B +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60 0x0000003C +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61 0x0000003D +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62 0x0000003E +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63 0x0000003F +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64 0x00000040 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65 0x00000041 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66 0x00000042 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67 0x00000043 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68 0x00000044 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69 0x00000045 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70 0x00000046 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71 0x00000047 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72 0x00000048 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73 0x00000049 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74 0x0000004A +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75 0x0000004B +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76 0x0000004C +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77 0x0000004D +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78 0x0000004E +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79 0x0000004F +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80 0x00000050 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81 0x00000051 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82 0x00000052 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83 0x00000053 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10 31:0 + + +// dma opcode instructions +#define NV917D_DMA 0x00000000 +#define NV917D_DMA_OPCODE 31:29 +#define NV917D_DMA_OPCODE_METHOD 0x00000000 +#define NV917D_DMA_OPCODE_JUMP 0x00000001 +#define NV917D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV917D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV917D_DMA_OPCODE 31:29 +#define NV917D_DMA_OPCODE_METHOD 0x00000000 +#define NV917D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV917D_DMA_METHOD_COUNT 27:18 +#define NV917D_DMA_METHOD_OFFSET 11:2 +#define NV917D_DMA_DATA 31:0 +#define NV917D_DMA_DATA_NOP 0x00000000 +#define NV917D_DMA_OPCODE 31:29 +#define NV917D_DMA_OPCODE_JUMP 0x00000001 +#define NV917D_DMA_JUMP_OFFSET 11:2 +#define NV917D_DMA_OPCODE 31:29 +#define NV917D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV917D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV917D_PUT (0x00000000) +#define NV917D_PUT_PTR 11:2 +#define NV917D_GET (0x00000004) +#define NV917D_GET_PTR 11:2 +#define NV917D_UPDATE (0x00000080) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR(i) (0 +(i)*4):(0 +(i)*4) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1 4 +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0 +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR1 4:4 +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR2 8:8 +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR3 12:12 +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE(i) (1 +(i)*4):(1 +(i)*4) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1 4 +#define NV917D_UPDATE_INTERLOCK_WITH_BASE_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE0 1:1 +#define NV917D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE1 5:5 +#define NV917D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE2 9:9 +#define NV917D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE3 13:13 +#define NV917D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY(i) (2 +(i)*4):(2 +(i)*4) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1 4 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY1 6:6 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY2 10:10 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY3 14:14 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i) (3 +(i)*4):(3 +(i)*4) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1 4 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 7:7 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2 11:11 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3 15:15 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE (0x00000001) +#define NV917D_UPDATE_SPECIAL_HANDLING 25:24 +#define NV917D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV917D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV917D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV917D_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV917D_UPDATE_NOT_DRIVER_FRIENDLY 31:31 +#define NV917D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000) +#define NV917D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001) +#define NV917D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30 +#define NV917D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000) +#define NV917D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001) +#define NV917D_UPDATE_INHIBIT_INTERRUPTS 29:29 +#define NV917D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NV917D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NV917D_SET_NOTIFIER_CONTROL (0x00000084) +#define NV917D_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV917D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV917D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV917D_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV917D_SET_NOTIFIER_CONTROL_NOTIFY 31:31 +#define NV917D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NV917D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NV917D_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV917D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV917D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV917D_SET_CONTEXT_DMA_NOTIFIER (0x00000088) +#define NV917D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV917D_GET_CAPABILITIES (0x0000008C) +#define NV917D_GET_CAPABILITIES_DUMMY 31:0 +#define NV917D_SET_SPARE (0x0000016C) +#define NV917D_SET_SPARE_UNUSED 31:0 +#define NV917D_SET_SPARE_NOOP(b) (0x00000170 + (b)*0x00000004) +#define NV917D_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV917D_DAC_SET_CONTROL(a) (0x00000180 + (a)*0x00000020) +#define NV917D_DAC_SET_CONTROL_OWNER_MASK 3:0 +#define NV917D_DAC_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV917D_DAC_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV917D_DAC_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV917D_DAC_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV917D_DAC_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV917D_DAC_SET_CONTROL_PROTOCOL 12:8 +#define NV917D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV917D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT (0x00000013) +#define NV917D_DAC_SET_SW_SPARE_A(a) (0x00000184 + (a)*0x00000020) +#define NV917D_DAC_SET_SW_SPARE_A_CODE 31:0 +#define NV917D_DAC_SET_SW_SPARE_B(a) (0x00000188 + (a)*0x00000020) +#define NV917D_DAC_SET_SW_SPARE_B_CODE 31:0 +#define NV917D_DAC_SET_CUSTOM_REASON(a) (0x00000190 + (a)*0x00000020) +#define NV917D_DAC_SET_CUSTOM_REASON_CODE 31:0 + +#define NV917D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV917D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV917D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NV917D_SOR_SET_SW_SPARE_A(a) (0x00000204 + (a)*0x00000020) +#define NV917D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NV917D_SOR_SET_SW_SPARE_B(a) (0x00000208 + (a)*0x00000020) +#define NV917D_SOR_SET_SW_SPARE_B_CODE 31:0 +#define NV917D_SOR_SET_CUSTOM_REASON(a) (0x00000210 + (a)*0x00000020) +#define NV917D_SOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV917D_PIOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NV917D_PIOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV917D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV917D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV917D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV917D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV917D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV917D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV917D_PIOR_SET_SW_SPARE_A(a) (0x00000304 + (a)*0x00000020) +#define NV917D_PIOR_SET_SW_SPARE_A_CODE 31:0 +#define NV917D_PIOR_SET_SW_SPARE_B(a) (0x00000308 + (a)*0x00000020) +#define NV917D_PIOR_SET_SW_SPARE_B_CODE 31:0 +#define NV917D_PIOR_SET_CUSTOM_REASON(a) (0x00000310 + (a)*0x00000020) +#define NV917D_PIOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV917D_HEAD_SET_PRESENT_CONTROL(a) (0x00000400 + (a)*0x00000300) +#define NV917D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NV917D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 8:8 +#define NV917D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NV917D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NV917D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00000404 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 3:3 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 4:4 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 9:6 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000009) +#define NV917D_HEAD_SET_CONTROL(a) (0x00000408 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTROL_STRUCTURE 0:0 +#define NV917D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 3:2 +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 19:15 +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 7:4 +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 9:8 +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 14:10 +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK 1:1 +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_ENABLE (0x00000001) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN 24:20 +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN 29:25 +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000003) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000004) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000005) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000006) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000007) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000008) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x00000009) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000A) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000B) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000C) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000D) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000E) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x0000000F) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_UNSPECIFIED (0x00000010) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV917D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NV917D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NV917D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000410 + (a)*0x00000300) +#define NV917D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV917D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV917D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV917D_HEAD_SET_RASTER_SIZE(a) (0x00000414 + (a)*0x00000300) +#define NV917D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV917D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV917D_HEAD_SET_RASTER_SYNC_END(a) (0x00000418 + (a)*0x00000300) +#define NV917D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV917D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV917D_HEAD_SET_RASTER_BLANK_END(a) (0x0000041C + (a)*0x00000300) +#define NV917D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV917D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV917D_HEAD_SET_RASTER_BLANK_START(a) (0x00000420 + (a)*0x00000300) +#define NV917D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV917D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV917D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000424 + (a)*0x00000300) +#define NV917D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV917D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV917D_HEAD_SET_LOCK_CHAIN(a) (0x00000428 + (a)*0x00000300) +#define NV917D_HEAD_SET_LOCK_CHAIN_POSITION 27:24 +#define NV917D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000042C + (a)*0x00000300) +#define NV917D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV917D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV917D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV917D_HEAD_SET_CRC_CONTROL(a) (0x00000430 + (a)*0x00000300) +#define NV917D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 1:0 +#define NV917D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000000) +#define NV917D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_BASE (0x00000001) +#define NV917D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_OVERLAY (0x00000002) +#define NV917D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 2:2 +#define NV917D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NV917D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NV917D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE 3:3 +#define NV917D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_FALSE (0x00000000) +#define NV917D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_TRUE (0x00000001) +#define NV917D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE 4:4 +#define NV917D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_FALSE (0x00000000) +#define NV917D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_TRUE (0x00000001) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT 19:8 +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC__SIZE_1 4 +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC0 (0x00000FF0) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC1 (0x00000FF1) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC2 (0x00000FF2) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC3 (0x00000FF3) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG__SIZE_1 4 +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG0 (0x00000FF8) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG1 (0x00000FF9) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG2 (0x00000FFA) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG3 (0x00000FFB) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR__SIZE_1 8 +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR0 (0x00000F0F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR1 (0x00000F1F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR2 (0x00000F2F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR3 (0x00000F3F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR4 (0x00000F4F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR5 (0x00000F5F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR6 (0x00000F6F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR7 (0x00000F7F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF__SIZE_1 4 +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF0 (0x00000F8F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF1 (0x00000F9F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF2 (0x00000FAF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF3 (0x00000FBF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR__SIZE_1 8 +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR0 (0x000000FF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR1 (0x000001FF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR2 (0x000002FF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR3 (0x000003FF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR4 (0x000004FF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR5 (0x000005FF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR6 (0x000006FF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR7 (0x000007FF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_NONE (0x00000FFF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT 31:20 +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC__SIZE_1 4 +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC0 (0x00000FF0) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC1 (0x00000FF1) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC2 (0x00000FF2) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC3 (0x00000FF3) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG__SIZE_1 4 +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG0 (0x00000FF8) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG1 (0x00000FF9) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG2 (0x00000FFA) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG3 (0x00000FFB) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR__SIZE_1 8 +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR0 (0x00000F0F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR1 (0x00000F1F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR2 (0x00000F2F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR3 (0x00000F3F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR4 (0x00000F4F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR5 (0x00000F5F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR6 (0x00000F6F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR7 (0x00000F7F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF__SIZE_1 4 +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF0 (0x00000F8F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF1 (0x00000F9F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF2 (0x00000FAF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF3 (0x00000FBF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR__SIZE_1 8 +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR0 (0x000000FF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR1 (0x000001FF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR2 (0x000002FF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR3 (0x000003FF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR4 (0x000004FF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR5 (0x000005FF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR6 (0x000006FF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR7 (0x000007FF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_NONE (0x00000FFF) +#define NV917D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 5:5 +#define NV917D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC 6:6 +#define NV917D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_ENABLE (0x00000001) +#define NV917D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00000438 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NV917D_HEAD_SET_BASE_LUT_LO(a) (0x00000440 + (a)*0x00000300) +#define NV917D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV917D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE 27:24 +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV917D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV917D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_BASE_LUT_HI(a) (0x00000444 + (a)*0x00000300) +#define NV917D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV917D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000448 + (a)*0x00000300) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000044C + (a)*0x00000300) +#define NV917D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x00000450 + (a)*0x00000300) +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x00000454 + (a)*0x00000300) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE 21:20 +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25 (0x00000000) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28 (0x00000001) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM (0x00000002) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 24:24 +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING 25:25 +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE (0x00000000) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE (0x00000001) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 26:26 +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00000458 + (a)*0x00000300) +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NV917D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000045C + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV917D_HEAD_SET_OFFSET(a) (0x00000460 + (a)*0x00000300) +#define NV917D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV917D_HEAD_SET_SIZE(a) (0x00000468 + (a)*0x00000300) +#define NV917D_HEAD_SET_SIZE_WIDTH 15:0 +#define NV917D_HEAD_SET_SIZE_HEIGHT 31:16 +#define NV917D_HEAD_SET_STORAGE(a) (0x0000046C + (a)*0x00000300) +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV917D_HEAD_SET_STORAGE_PITCH 20:8 +#define NV917D_HEAD_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV917D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV917D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV917D_HEAD_SET_PARAMS(a) (0x00000470 + (a)*0x00000300) +#define NV917D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV917D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV917D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV917D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV917D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV917D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV917D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV917D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV917D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV917D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV917D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV917D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV917D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV917D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV917D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV917D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV917D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV917D_HEAD_SET_PARAMS_GAMMA 2:2 +#define NV917D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV917D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV917D_HEAD_SET_CONTEXT_DMAS_ISO(a) (0x00000474 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV917D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x0000047C + (a)*0x00000300) +#define NV917D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 1:0 +#define NV917D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NV917D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NV917D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_SPEC_FLIP (0x00000002) +#define NV917D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE 27:26 +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NV917D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 15:8 +#define NV917D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 23:16 +#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV917D_HEAD_SET_OFFSETS_CURSOR(a,b) (0x00000484 + (a)*0x00000300 + (b)*0x00000004) +#define NV917D_HEAD_SET_OFFSETS_CURSOR_ORIGIN 31:0 +#define NV917D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b) (0x0000048C + (a)*0x00000300 + (b)*0x00000004) +#define NV917D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE 31:0 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00000494 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422 8:8 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE (0x00000001) +#define NV917D_HEAD_SET_PROCAMP(a) (0x00000498 + (a)*0x00000300) +#define NV917D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV917D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV917D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV917D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV917D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV917D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV917D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV917D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV917D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV917D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 5:5 +#define NV917D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NV917D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NV917D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 6:6 +#define NV917D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) +#define NV917D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) +#define NV917D_HEAD_SET_DITHER_CONTROL(a) (0x000004A0 + (a)*0x00000300) +#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NV917D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV917D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x000004B0 + (a)*0x00000300) +#define NV917D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV917D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000004B8 + (a)*0x00000300) +#define NV917D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV917D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x000004BC + (a)*0x00000300) +#define NV917D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NV917D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000004C0 + (a)*0x00000300) +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000004C4 + (a)*0x00000300) +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a) (0x000004C8 + (a)*0x00000300) +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH 14:0 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT 30:16 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT 17:16 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257 (0x00000001) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025 (0x00000002) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT 21:20 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x000004D4 + (a)*0x00000300) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT 13:12 +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE (0x00000000) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257 (0x00000001) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025 (0x00000002) +#define NV917D_HEAD_SET_PROCESSING(a) (0x000004E0 + (a)*0x00000300) +#define NV917D_HEAD_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV917D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV917D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV917D_HEAD_SET_CONVERSION_RED(a) (0x000004E4 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONVERSION_RED_GAIN 15:0 +#define NV917D_HEAD_SET_CONVERSION_RED_OFS 31:16 +#define NV917D_HEAD_SET_CONVERSION_GRN(a) (0x000004E8 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONVERSION_GRN_GAIN 15:0 +#define NV917D_HEAD_SET_CONVERSION_GRN_OFS 31:16 +#define NV917D_HEAD_SET_CONVERSION_BLU(a) (0x000004EC + (a)*0x00000300) +#define NV917D_HEAD_SET_CONVERSION_BLU_GAIN 15:0 +#define NV917D_HEAD_SET_CONVERSION_BLU_OFS 31:16 +#define NV917D_HEAD_SET_CSC_RED2RED(a) (0x000004F0 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE 31:31 +#define NV917D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_CSC_RED2RED_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_GRN2RED(a) (0x000004F4 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_GRN2RED_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_BLU2RED(a) (0x000004F8 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_BLU2RED_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_CONSTANT2RED(a) (0x000004FC + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_RED2GRN(a) (0x00000500 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_RED2GRN_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_GRN2GRN(a) (0x00000504 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_BLU2GRN(a) (0x00000508 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_CONSTANT2GRN(a) (0x0000050C + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_RED2BLU(a) (0x00000510 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_RED2BLU_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_GRN2BLU(a) (0x00000514 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_BLU2BLU(a) (0x00000518 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_CONSTANT2BLU(a) (0x0000051C + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_CONSTANT2BLU_COEFF 18:0 +#define NV917D_HEAD_SET_HDMI_CTRL(a) (0x00000520 + (a)*0x00000300) +#define NV917D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NV917D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NV917D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NV917D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NV917D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE 15:12 +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000000) +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FIELD_ALTERNATIVE (0x00000001) +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_LINE_ALTERNATIVE (0x00000002) +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_FULL (0x00000003) +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH (0x00000004) +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH_GRAPHICS (0x00000005) +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_TOP_AND_BOTTOM (0x00000006) +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_HALF (0x00000008) +#define NV917D_HEAD_SET_VACTIVE_SPACE_COLOR(a) (0x00000524 + (a)*0x00000300) +#define NV917D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR 9:0 +#define NV917D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y 19:10 +#define NV917D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB 29:20 +#define NV917D_HEAD_SET_DISPLAY_ID(a,b) (0x0000052C + (a)*0x00000300 + (b)*0x00000004) +#define NV917D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NV917D_HEAD_SET_SW_SPARE_A(a) (0x0000054C + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NV917D_HEAD_SET_SW_SPARE_B(a) (0x00000550 + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NV917D_HEAD_SET_SW_SPARE_C(a) (0x00000554 + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NV917D_HEAD_SET_SW_SPARE_D(a) (0x00000558 + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NV917D_HEAD_SET_GET_BLANKING_CTRL(a) (0x0000055C + (a)*0x00000300) +#define NV917D_HEAD_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NV917D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NV917D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NV917D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NV917D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NV917D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a) (0x000006D0 + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED 31:0 +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a) (0x000006D4 + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED 31:0 +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a) (0x000006D8 + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED 31:0 +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a) (0x000006DC + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED 31:0 +#define NV917D_HEAD_SET_SPARE(a) (0x000006EC + (a)*0x00000300) +#define NV917D_HEAD_SET_SPARE_UNUSED 31:0 +#define NV917D_HEAD_SET_SPARE_NOOP(a,b) (0x000006F0 + (a)*0x00000300 + (b)*0x00000004) +#define NV917D_HEAD_SET_SPARE_NOOP_UNUSED 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl917d_h diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl917dcrcnotif.h b/userspace/sdks/nv525/nvidia/inc/class/cl917dcrcnotif.h new file mode 100644 index 0000000..9abc605 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl917dcrcnotif.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2003-2010, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __cl917dcrcnotif_h__ +#define __cl917dcrcnotif_h__ +/* This file is autogenerated. Do not edit */ + +#define NV917D_NOTIFIER_CRC_1_STATUS_0 0x00000000 +#define NV917D_NOTIFIER_CRC_1_STATUS_0_DONE 0:0 +#define NV917D_NOTIFIER_CRC_1_STATUS_0_DONE_FALSE 0x00000000 +#define NV917D_NOTIFIER_CRC_1_STATUS_0_DONE_TRUE 0x00000001 +#define NV917D_NOTIFIER_CRC_1_STATUS_0_COMPOSITOR_OVERFLOW 3:3 +#define NV917D_NOTIFIER_CRC_1_STATUS_0_COMPOSITOR_OVERFLOW_FALSE 0x00000000 +#define NV917D_NOTIFIER_CRC_1_STATUS_0_COMPOSITOR_OVERFLOW_TRUE 0x00000001 +#define NV917D_NOTIFIER_CRC_1_STATUS_0_PRIMARY_OUTPUT_OVERFLOW 4:4 +#define NV917D_NOTIFIER_CRC_1_STATUS_0_PRIMARY_OUTPUT_OVERFLOW_FALSE 0x00000000 +#define NV917D_NOTIFIER_CRC_1_STATUS_0_PRIMARY_OUTPUT_OVERFLOW_TRUE 0x00000001 +#define NV917D_NOTIFIER_CRC_1_STATUS_0_COUNT 31:24 +#define NV917D_NOTIFIER_CRC_1_CRC_ENTRY0_3 0x00000003 +#define NV917D_NOTIFIER_CRC_1_CRC_ENTRY0_3_COMPOSITOR_CRC 31:0 +#define NV917D_NOTIFIER_CRC_1_CRC_ENTRY0_4 0x00000004 +#define NV917D_NOTIFIER_CRC_1_CRC_ENTRY0_4_PRIMARY_OUTPUT_CRC 31:0 +#define NV917D_NOTIFIER_CRC_1_CRC_ENTRY1_8 0x00000008 + +#endif // __cl917dcrcnotif_h__ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl917e.h b/userspace/sdks/nv525/nvidia/inc/class/cl917e.h new file mode 100644 index 0000000..6586bda --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl917e.h @@ -0,0 +1,265 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl917e_h_ +#define _cl917e_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV917E_OVERLAY_CHANNEL_DMA (0x0000917E) + +#define NV_DISP_NOTIFICATION_2 0x00000000 +#define NV_DISP_NOTIFICATION_2_SIZEOF 0x00000010 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0 0x00000000 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0_NANOSECONDS0 31:0 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1 0x00000001 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1_NANOSECONDS1 31:0 +#define NV_DISP_NOTIFICATION_2_INFO32_2 0x00000002 +#define NV_DISP_NOTIFICATION_2_INFO32_2_R0 31:0 +#define NV_DISP_NOTIFICATION_2_INFO16_3 0x00000003 +#define NV_DISP_NOTIFICATION_2_INFO16_3_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_2_INFO16_3_FIELD 8:8 +#define NV_DISP_NOTIFICATION_2_INFO16_3_R1 15:9 +#define NV_DISP_NOTIFICATION_2__3_STATUS 31:16 +#define NV_DISP_NOTIFICATION_2__3_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_2__3_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_2__3_STATUS_FINISHED 0x00000000 + + +#define NV_DISP_NOTIFICATION_INFO16 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_INFO16__0 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_INFO16__0_FIELD 8:8 +#define NV_DISP_NOTIFICATION_INFO16__0_R1 15:9 + + +#define NV_DISP_NOTIFICATION_STATUS 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_STATUS__0 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS 15:0 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED 0x00000000 + + +// dma opcode instructions +#define NV917E_DMA 0x00000000 +#define NV917E_DMA_OPCODE 31:29 +#define NV917E_DMA_OPCODE_METHOD 0x00000000 +#define NV917E_DMA_OPCODE_JUMP 0x00000001 +#define NV917E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV917E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV917E_DMA_OPCODE 31:29 +#define NV917E_DMA_OPCODE_METHOD 0x00000000 +#define NV917E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV917E_DMA_METHOD_COUNT 27:18 +#define NV917E_DMA_METHOD_OFFSET 11:2 +#define NV917E_DMA_DATA 31:0 +#define NV917E_DMA_DATA_NOP 0x00000000 +#define NV917E_DMA_OPCODE 31:29 +#define NV917E_DMA_OPCODE_JUMP 0x00000001 +#define NV917E_DMA_JUMP_OFFSET 11:2 +#define NV917E_DMA_OPCODE 31:29 +#define NV917E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV917E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV917E_PUT (0x00000000) +#define NV917E_PUT_PTR 11:2 +#define NV917E_GET (0x00000004) +#define NV917E_GET_PTR 11:2 +#define NV917E_UPDATE (0x00000080) +#define NV917E_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV917E_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV917E_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV917E_UPDATE_SPECIAL_HANDLING 25:24 +#define NV917E_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV917E_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV917E_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV917E_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV917E_SET_PRESENT_CONTROL (0x00000084) +#define NV917E_SET_PRESENT_CONTROL_BEGIN_MODE 1:0 +#define NV917E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP (0x00000000) +#define NV917E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP (0x00000003) +#define NV917E_SET_PRESENT_CONTROL_STEREO_FLIP_MODE 3:3 +#define NV917E_SET_PRESENT_CONTROL_STEREO_FLIP_MODE_PAIR_FLIP (0x00000000) +#define NV917E_SET_PRESENT_CONTROL_STEREO_FLIP_MODE_AT_ANY_FRAME (0x00000001) +#define NV917E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV917E_SET_PRESENT_CONTROL_MODE 11:10 +#define NV917E_SET_PRESENT_CONTROL_MODE_MONO (0x00000000) +#define NV917E_SET_PRESENT_CONTROL_MODE_STEREO (0x00000001) +#define NV917E_SET_PRESENT_CONTROL_MODE_SPEC_FLIP (0x00000002) +#define NV917E_SET_SEMAPHORE_ACQUIRE (0x00000088) +#define NV917E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NV917E_SET_SEMAPHORE_RELEASE (0x0000008C) +#define NV917E_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NV917E_SET_SEMAPHORE_CONTROL (0x00000090) +#define NV917E_SET_SEMAPHORE_CONTROL_OFFSET 11:2 +#define NV917E_SET_SEMAPHORE_CONTROL_FORMAT 28:28 +#define NV917E_SET_SEMAPHORE_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV917E_SET_SEMAPHORE_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV917E_SET_CONTEXT_DMA_SEMAPHORE (0x00000094) +#define NV917E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NV917E_SET_NOTIFIER_CONTROL (0x000000A0) +#define NV917E_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV917E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV917E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV917E_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV917E_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV917E_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV917E_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV917E_SET_CONTEXT_DMA_NOTIFIER (0x000000A4) +#define NV917E_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV917E_SET_CONTEXT_DMA_LUT (0x000000B0) +#define NV917E_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV917E_SET_OVERLAY_LUT_LO (0x000000B4) +#define NV917E_SET_OVERLAY_LUT_LO_ENABLE 31:31 +#define NV917E_SET_OVERLAY_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV917E_SET_OVERLAY_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV917E_SET_OVERLAY_LUT_LO_MODE 27:24 +#define NV917E_SET_OVERLAY_LUT_LO_MODE_LORES (0x00000000) +#define NV917E_SET_OVERLAY_LUT_LO_MODE_HIRES (0x00000001) +#define NV917E_SET_OVERLAY_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV917E_SET_OVERLAY_LUT_HI (0x000000B8) +#define NV917E_SET_OVERLAY_LUT_HI_ORIGIN 31:0 +#define NV917E_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0x00000004) +#define NV917E_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV917E_SET_POINT_IN (0x000000E0) +#define NV917E_SET_POINT_IN_X 14:0 +#define NV917E_SET_POINT_IN_Y 30:16 +#define NV917E_SET_SIZE_IN (0x000000E4) +#define NV917E_SET_SIZE_IN_WIDTH 14:0 +#define NV917E_SET_SIZE_IN_HEIGHT 30:16 +#define NV917E_SET_SIZE_OUT (0x000000E8) +#define NV917E_SET_SIZE_OUT_WIDTH 14:0 +#define NV917E_SET_COMPOSITION_CONTROL (0x00000100) +#define NV917E_SET_COMPOSITION_CONTROL_MODE 3:0 +#define NV917E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING (0x00000000) +#define NV917E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING (0x00000001) +#define NV917E_SET_COMPOSITION_CONTROL_MODE_OPAQUE (0x00000002) +#define NV917E_SET_KEY_COLOR_LO (0x00000104) +#define NV917E_SET_KEY_COLOR_LO_COLOR 31:0 +#define NV917E_SET_KEY_COLOR_HI (0x00000108) +#define NV917E_SET_KEY_COLOR_HI_COLOR 31:0 +#define NV917E_SET_KEY_MASK_LO (0x0000010C) +#define NV917E_SET_KEY_MASK_LO_MASK 31:0 +#define NV917E_SET_KEY_MASK_HI (0x00000110) +#define NV917E_SET_KEY_MASK_HI_MASK 31:0 +#define NV917E_SET_PROCESSING (0x00000118) +#define NV917E_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV917E_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV917E_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV917E_SET_CONVERSION_RED (0x0000011C) +#define NV917E_SET_CONVERSION_RED_GAIN 15:0 +#define NV917E_SET_CONVERSION_RED_OFS 31:16 +#define NV917E_SET_CONVERSION_GRN (0x00000120) +#define NV917E_SET_CONVERSION_GRN_GAIN 15:0 +#define NV917E_SET_CONVERSION_GRN_OFS 31:16 +#define NV917E_SET_CONVERSION_BLU (0x00000124) +#define NV917E_SET_CONVERSION_BLU_GAIN 15:0 +#define NV917E_SET_CONVERSION_BLU_OFS 31:16 +#define NV917E_SET_TIMESTAMP_ORIGIN_LO (0x00000130) +#define NV917E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NV917E_SET_TIMESTAMP_ORIGIN_HI (0x00000134) +#define NV917E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NV917E_SET_UPDATE_TIMESTAMP_LO (0x00000138) +#define NV917E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NV917E_SET_UPDATE_TIMESTAMP_HI (0x0000013C) +#define NV917E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NV917E_SET_CSC_RED2RED (0x00000140) +#define NV917E_SET_CSC_RED2RED_COEFF 18:0 +#define NV917E_SET_CSC_GRN2RED (0x00000144) +#define NV917E_SET_CSC_GRN2RED_COEFF 18:0 +#define NV917E_SET_CSC_BLU2RED (0x00000148) +#define NV917E_SET_CSC_BLU2RED_COEFF 18:0 +#define NV917E_SET_CSC_CONSTANT2RED (0x0000014C) +#define NV917E_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV917E_SET_CSC_RED2GRN (0x00000150) +#define NV917E_SET_CSC_RED2GRN_COEFF 18:0 +#define NV917E_SET_CSC_GRN2GRN (0x00000154) +#define NV917E_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV917E_SET_CSC_BLU2GRN (0x00000158) +#define NV917E_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV917E_SET_CSC_CONSTANT2GRN (0x0000015C) +#define NV917E_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV917E_SET_CSC_RED2BLU (0x00000160) +#define NV917E_SET_CSC_RED2BLU_COEFF 18:0 +#define NV917E_SET_CSC_GRN2BLU (0x00000164) +#define NV917E_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV917E_SET_CSC_BLU2BLU (0x00000168) +#define NV917E_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV917E_SET_CSC_CONSTANT2BLU (0x0000016C) +#define NV917E_SET_CSC_CONSTANT2BLU_COEFF 18:0 +#define NV917E_SET_SPARE (0x000003BC) +#define NV917E_SET_SPARE_UNUSED 31:0 +#define NV917E_SET_SPARE_NOOP(b) (0x000003C0 + (b)*0x00000004) +#define NV917E_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV917E_SURFACE_SET_OFFSET(b) (0x00000400 + (b)*0x00000004) +#define NV917E_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV917E_SURFACE_SET_SIZE (0x00000408) +#define NV917E_SURFACE_SET_SIZE_WIDTH 15:0 +#define NV917E_SURFACE_SET_SIZE_HEIGHT 31:16 +#define NV917E_SURFACE_SET_STORAGE (0x0000040C) +#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV917E_SURFACE_SET_STORAGE_PITCH 20:8 +#define NV917E_SURFACE_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV917E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV917E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV917E_SURFACE_SET_PARAMS (0x00000410) +#define NV917E_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV917E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8 (0x00000028) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8 (0x00000029) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV917E_SURFACE_SET_PARAMS_COLOR_SPACE 1:0 +#define NV917E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB (0x00000000) +#define NV917E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601 (0x00000001) +#define NV917E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709 (0x00000002) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl917e_h diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl9270.h b/userspace/sdks/nv525/nvidia/inc/class/cl9270.h new file mode 100644 index 0000000..de3f498 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl9270.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9270.finn +// + +#define NV9270_DISPLAY (0x9270U) /* finn: Evaluated from "NV9270_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV9270_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9270U) + +typedef struct NV9270_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numDacs; // Number of DACs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NV9270_ALLOCATION_PARAMETERS; diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl9271.h b/userspace/sdks/nv525/nvidia/inc/class/cl9271.h new file mode 100644 index 0000000..397cdc2 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl9271.h @@ -0,0 +1,295 @@ +/* + * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl9271_h_ +#define _cl9271_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV9271_DISP_SF_USER 0x9271 + +typedef volatile struct _cl9271_tag0 { + NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x00690FFF:0x00690000 */ +} _Nv9271DispSfUser, Nv9271DispSfUserMap; + +#define NV9271_SF_HDMI_INFO_IDX_AVI_INFOFRAME 0x00000000 /* */ +#define NV9271_SF_HDMI_INFO_IDX_GENERIC_INFOFRAME 0x00000001 /* */ +#define NV9271_SF_HDMI_INFO_IDX_GCP 0x00000003 /* */ +#define NV9271_SF_HDMI_INFO_IDX_VSI 0x00000004 /* */ +#define NV9271_SF_HDMI_INFO_CTRL(i,j) (0x00690000-0x00690000+(i)*1024+(j)*64) /* RWX4A */ +#define NV9271_SF_HDMI_INFO_CTRL__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_INFO_CTRL__SIZE_2 5 /* */ +#define NV9271_SF_HDMI_INFO_CTRL_ENABLE 0:0 /* RWIVF */ +#define NV9271_SF_HDMI_INFO_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_INFO_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NV9271_SF_HDMI_INFO_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NV9271_SF_HDMI_INFO_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NV9271_SF_HDMI_INFO_CTRL_OTHER 4:4 /* RWIVF */ +#define NV9271_SF_HDMI_INFO_CTRL_OTHER_DIS 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_INFO_CTRL_OTHER_EN 0x00000001 /* RW--V */ +#define NV9271_SF_HDMI_INFO_CTRL_SINGLE 8:8 /* RWIVF */ +#define NV9271_SF_HDMI_INFO_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_INFO_CTRL_SINGLE_EN 0x00000001 /* RW--V */ +#define NV9271_SF_HDMI_INFO_CTRL_CHKSUM_HW 9:9 /* RWIVF */ +#define NV9271_SF_HDMI_INFO_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */ +#define NV9271_SF_HDMI_INFO_CTRL_CHKSUM_HW_EN 0x00000001 /* RW--V */ +#define NV9271_SF_HDMI_INFO_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */ +#define NV9271_SF_HDMI_INFO_CTRL_CHKSUM_HW_DIS 0x00000000 /* RW--V */ +#define NV9271_SF_HDMI_INFO_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */ +#define NV9271_SF_HDMI_INFO_CTRL_HBLANK 12:12 /* RWIVF */ +#define NV9271_SF_HDMI_INFO_CTRL_HBLANK_DIS 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_INFO_CTRL_HBLANK_EN 0x00000001 /* RW--V */ +#define NV9271_SF_HDMI_INFO_CTRL_VIDEO_FMT 16:16 /* RWIVF */ +#define NV9271_SF_HDMI_INFO_CTRL_VIDEO_FMT_SW_CONTROLLED 0x00000000 /* RW--V */ +#define NV9271_SF_HDMI_INFO_CTRL_VIDEO_FMT_HW_CONTROLLED 0x00000001 /* RW--V */ +#define NV9271_SF_HDMI_INFO_CTRL_VIDEO_FMT_INIT 0x00000001 /* RWI-V */ +#define NV9271_SF_HDMI_INFO_STATUS(i,j) (0x00690004-0x00690000+(i)*1024+(j)*64) /* R--4A */ +#define NV9271_SF_HDMI_INFO_STATUS__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_INFO_STATUS__SIZE_2 5 /* */ +#define NV9271_SF_HDMI_INFO_STATUS_SENT 0:0 /* R--VF */ +#define NV9271_SF_HDMI_INFO_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NV9271_SF_HDMI_INFO_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NV9271_SF_HDMI_INFO_STATUS_SENT_INIT 0x00000000 /* R-I-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x00690000-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x00690008-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x0069000C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x00690010-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x00690014-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x00690018-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_HEADER(i) (0x00690048-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_GENERIC_HEADER__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_GENERIC_HEADER_HB0 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_HEADER_HB1 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_HEADER_HB2 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW(i) (0x0069004C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_HIGH(i) (0x00690050-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW(i) (0x00690054-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_HIGH(i) (0x00690058-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW(i) (0x0069005C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_HIGH(i) (0x00690060-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_HIGH__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW(i) (0x00690064-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24 31:24 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_HIGH(i) (0x00690068-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_HIGH__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GCP_SUBPACK(i) (0x006900CC-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_GCP_SUBPACK__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_GCP_SUBPACK_SB0 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_GCP_SUBPACK_SB0_INIT 0x00000001 /* RWI-V */ +#define NV9271_SF_HDMI_GCP_SUBPACK_SB0_SET_AVMUTE 0x00000001 /* RW--V */ +#define NV9271_SF_HDMI_GCP_SUBPACK_SB0_CLR_AVMUTE 0x00000010 /* RW--V */ +#define NV9271_SF_HDMI_GCP_SUBPACK_SB1 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_GCP_SUBPACK_SB1_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GCP_SUBPACK_SB2 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_GCP_SUBPACK_SB2_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_HEADER(i) (0x00690108-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_VSI_HEADER__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_VSI_HEADER_HB0 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_HEADER_HB1 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_HEADER_HB2 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW(i) (0x0069010C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_HIGH(i) (0x00690110-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW(i) (0x00690114-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_HIGH(i) (0x00690118-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW(i) (0x0069011C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_HIGH(i) (0x00690120-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_HIGH__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW(i) (0x00690124-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW_PB21 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW_PB22 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW_PB23 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW_PB24 31:24 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_HIGH(i) (0x00690128-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_HIGH__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _cl9271_h_ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl927c.h b/userspace/sdks/nv525/nvidia/inc/class/cl927c.h new file mode 100644 index 0000000..1b78305 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl927c.h @@ -0,0 +1,299 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl927c_h_ +#define _cl927c_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV927C_BASE_CHANNEL_DMA (0x0000927C) + +#define NV_DISP_BASE_NOTIFIER_1 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1_SIZEOF 0x00000004 +#define NV_DISP_BASE_NOTIFIER_1__0 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT 15:0 +#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP 29:16 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS 31:30 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED 0x00000002 + + +#define NV_DISP_NOTIFICATION_2 0x00000000 +#define NV_DISP_NOTIFICATION_2_SIZEOF 0x00000010 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0 0x00000000 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0_NANOSECONDS0 31:0 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1 0x00000001 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1_NANOSECONDS1 31:0 +#define NV_DISP_NOTIFICATION_2_INFO32_2 0x00000002 +#define NV_DISP_NOTIFICATION_2_INFO32_2_R0 31:0 +#define NV_DISP_NOTIFICATION_2_INFO16_3 0x00000003 +#define NV_DISP_NOTIFICATION_2_INFO16_3_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_2_INFO16_3_FIELD 8:8 +#define NV_DISP_NOTIFICATION_2_INFO16_3_R1 15:9 +#define NV_DISP_NOTIFICATION_2__3_STATUS 31:16 +#define NV_DISP_NOTIFICATION_2__3_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_2__3_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_2__3_STATUS_FINISHED 0x00000000 + + +#define NV_DISP_NOTIFICATION_INFO16 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_INFO16__0 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_INFO16__0_FIELD 8:8 +#define NV_DISP_NOTIFICATION_INFO16__0_R1 15:9 + + +#define NV_DISP_NOTIFICATION_STATUS 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_STATUS__0 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS 15:0 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED 0x00000000 + + +// dma opcode instructions +#define NV927C_DMA 0x00000000 +#define NV927C_DMA_OPCODE 31:29 +#define NV927C_DMA_OPCODE_METHOD 0x00000000 +#define NV927C_DMA_OPCODE_JUMP 0x00000001 +#define NV927C_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV927C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV927C_DMA_OPCODE 31:29 +#define NV927C_DMA_OPCODE_METHOD 0x00000000 +#define NV927C_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV927C_DMA_METHOD_COUNT 27:18 +#define NV927C_DMA_METHOD_OFFSET 11:2 +#define NV927C_DMA_DATA 31:0 +#define NV927C_DMA_DATA_NOP 0x00000000 +#define NV927C_DMA_OPCODE 31:29 +#define NV927C_DMA_OPCODE_JUMP 0x00000001 +#define NV927C_DMA_JUMP_OFFSET 11:2 +#define NV927C_DMA_OPCODE 31:29 +#define NV927C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV927C_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV927C_PUT (0x00000000) +#define NV927C_PUT_PTR 11:2 +#define NV927C_GET (0x00000004) +#define NV927C_GET_PTR 11:2 +#define NV927C_GET_SCANLINE (0x00000010) +#define NV927C_GET_SCANLINE_LINE 15:0 +#define NV927C_UPDATE (0x00000080) +#define NV927C_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV927C_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV927C_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV927C_UPDATE_SPECIAL_HANDLING 25:24 +#define NV927C_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV927C_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV927C_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV927C_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV927C_SET_PRESENT_CONTROL (0x00000084) +#define NV927C_SET_PRESENT_CONTROL_BEGIN_MODE 9:8 +#define NV927C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NV927C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NV927C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE (0x00000002) +#define NV927C_SET_PRESENT_CONTROL_STEREO_FLIP_MODE 3:3 +#define NV927C_SET_PRESENT_CONTROL_STEREO_FLIP_MODE_PAIR_FLIP (0x00000000) +#define NV927C_SET_PRESENT_CONTROL_STEREO_FLIP_MODE_AT_ANY_FRAME (0x00000001) +#define NV927C_SET_PRESENT_CONTROL_TIMESTAMP_MODE 2:2 +#define NV927C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000) +#define NV927C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001) +#define NV927C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV927C_SET_PRESENT_CONTROL_BEGIN_LINE 30:16 +#define NV927C_SET_PRESENT_CONTROL_ON_LINE_MARGIN 15:10 +#define NV927C_SET_PRESENT_CONTROL_MODE 1:0 +#define NV927C_SET_PRESENT_CONTROL_MODE_MONO (0x00000000) +#define NV927C_SET_PRESENT_CONTROL_MODE_STEREO (0x00000001) +#define NV927C_SET_PRESENT_CONTROL_MODE_SPEC_FLIP (0x00000002) +#define NV927C_SET_SEMAPHORE_CONTROL (0x00000088) +#define NV927C_SET_SEMAPHORE_CONTROL_OFFSET 11:2 +#define NV927C_SET_SEMAPHORE_CONTROL_DELAY 26:26 +#define NV927C_SET_SEMAPHORE_CONTROL_DELAY_DISABLE (0x00000000) +#define NV927C_SET_SEMAPHORE_CONTROL_DELAY_ENABLE (0x00000001) +#define NV927C_SET_SEMAPHORE_CONTROL_FORMAT 28:28 +#define NV927C_SET_SEMAPHORE_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV927C_SET_SEMAPHORE_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV927C_SET_SEMAPHORE_ACQUIRE (0x0000008C) +#define NV927C_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NV927C_SET_SEMAPHORE_RELEASE (0x00000090) +#define NV927C_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NV927C_SET_CONTEXT_DMA_SEMAPHORE (0x00000094) +#define NV927C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NV927C_SET_NOTIFIER_CONTROL (0x000000A0) +#define NV927C_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV927C_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV927C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV927C_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV927C_SET_NOTIFIER_CONTROL_DELAY 26:26 +#define NV927C_SET_NOTIFIER_CONTROL_DELAY_DISABLE (0x00000000) +#define NV927C_SET_NOTIFIER_CONTROL_DELAY_ENABLE (0x00000001) +#define NV927C_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV927C_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV927C_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV927C_SET_CONTEXT_DMA_NOTIFIER (0x000000A4) +#define NV927C_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV927C_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0x00000004) +#define NV927C_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV927C_SET_BASE_LUT_LO (0x000000E0) +#define NV927C_SET_BASE_LUT_LO_ENABLE 31:30 +#define NV927C_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV927C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001) +#define NV927C_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000002) +#define NV927C_SET_BASE_LUT_LO_MODE 27:24 +#define NV927C_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV927C_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV927C_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV927C_SET_BASE_LUT_HI (0x000000E4) +#define NV927C_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV927C_SET_OUTPUT_LUT_LO (0x000000E8) +#define NV927C_SET_OUTPUT_LUT_LO_ENABLE 31:30 +#define NV927C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV927C_SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001) +#define NV927C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000002) +#define NV927C_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV927C_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV927C_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV927C_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV927C_SET_OUTPUT_LUT_HI (0x000000EC) +#define NV927C_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV927C_SET_CONTEXT_DMA_LUT (0x000000FC) +#define NV927C_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV927C_SET_PROCESSING (0x00000110) +#define NV927C_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV927C_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV927C_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV927C_SET_CONVERSION_RED (0x00000114) +#define NV927C_SET_CONVERSION_RED_GAIN 15:0 +#define NV927C_SET_CONVERSION_RED_OFS 31:16 +#define NV927C_SET_CONVERSION_GRN (0x00000118) +#define NV927C_SET_CONVERSION_GRN_GAIN 15:0 +#define NV927C_SET_CONVERSION_GRN_OFS 31:16 +#define NV927C_SET_CONVERSION_BLU (0x0000011C) +#define NV927C_SET_CONVERSION_BLU_GAIN 15:0 +#define NV927C_SET_CONVERSION_BLU_OFS 31:16 +#define NV927C_SET_TIMESTAMP_ORIGIN_LO (0x00000130) +#define NV927C_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NV927C_SET_TIMESTAMP_ORIGIN_HI (0x00000134) +#define NV927C_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NV927C_SET_UPDATE_TIMESTAMP_LO (0x00000138) +#define NV927C_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NV927C_SET_UPDATE_TIMESTAMP_HI (0x0000013C) +#define NV927C_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NV927C_SET_CSC_RED2RED (0x00000140) +#define NV927C_SET_CSC_RED2RED_OWNER 31:31 +#define NV927C_SET_CSC_RED2RED_OWNER_CORE (0x00000000) +#define NV927C_SET_CSC_RED2RED_OWNER_BASE (0x00000001) +#define NV927C_SET_CSC_RED2RED_COEFF 18:0 +#define NV927C_SET_CSC_GRN2RED (0x00000144) +#define NV927C_SET_CSC_GRN2RED_COEFF 18:0 +#define NV927C_SET_CSC_BLU2RED (0x00000148) +#define NV927C_SET_CSC_BLU2RED_COEFF 18:0 +#define NV927C_SET_CSC_CONSTANT2RED (0x0000014C) +#define NV927C_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV927C_SET_CSC_RED2GRN (0x00000150) +#define NV927C_SET_CSC_RED2GRN_COEFF 18:0 +#define NV927C_SET_CSC_GRN2GRN (0x00000154) +#define NV927C_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV927C_SET_CSC_BLU2GRN (0x00000158) +#define NV927C_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV927C_SET_CSC_CONSTANT2GRN (0x0000015C) +#define NV927C_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV927C_SET_CSC_RED2BLU (0x00000160) +#define NV927C_SET_CSC_RED2BLU_COEFF 18:0 +#define NV927C_SET_CSC_GRN2BLU (0x00000164) +#define NV927C_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV927C_SET_CSC_BLU2BLU (0x00000168) +#define NV927C_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV927C_SET_CSC_CONSTANT2BLU (0x0000016C) +#define NV927C_SET_CSC_CONSTANT2BLU_COEFF 18:0 +#define NV927C_SET_SPARE (0x000003BC) +#define NV927C_SET_SPARE_UNUSED 31:0 +#define NV927C_SET_SPARE_NOOP(b) (0x000003C0 + (b)*0x00000004) +#define NV927C_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV927C_SURFACE_SET_OFFSET(a,b) (0x00000400 + (a)*0x00000020 + (b)*0x00000004) +#define NV927C_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV927C_SURFACE_SET_SIZE(a) (0x00000408 + (a)*0x00000020) +#define NV927C_SURFACE_SET_SIZE_WIDTH 15:0 +#define NV927C_SURFACE_SET_SIZE_HEIGHT 31:16 +#define NV927C_SURFACE_SET_STORAGE(a) (0x0000040C + (a)*0x00000020) +#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV927C_SURFACE_SET_STORAGE_PITCH 20:8 +#define NV927C_SURFACE_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV927C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV927C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV927C_SURFACE_SET_PARAMS(a) (0x00000410 + (a)*0x00000020) +#define NV927C_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV927C_SURFACE_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV927C_SURFACE_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV927C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV927C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV927C_SURFACE_SET_PARAMS_GAMMA 2:2 +#define NV927C_SURFACE_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV927C_SURFACE_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV927C_SURFACE_SET_PARAMS_LAYOUT 5:4 +#define NV927C_SURFACE_SET_PARAMS_LAYOUT_FRM (0x00000000) +#define NV927C_SURFACE_SET_PARAMS_LAYOUT_FLD1 (0x00000001) +#define NV927C_SURFACE_SET_PARAMS_LAYOUT_FLD2 (0x00000002) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl927c_h diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl927d.h b/userspace/sdks/nv525/nvidia/inc/class/cl927d.h new file mode 100644 index 0000000..df45fec --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl927d.h @@ -0,0 +1,1556 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl927d_h_ +#define _cl927d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV927D_CORE_CHANNEL_DMA (0x0000927D) + +#define NV927D_CORE_NOTIFIER_3 0x00000000 +#define NV927D_CORE_NOTIFIER_3_SIZEOF 0x00000150 +#define NV927D_CORE_NOTIFIER_3_COMPLETION_0 0x00000000 +#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_DONE 0:0 +#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_R0 15:1 +#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP 29:16 +#define NV927D_CORE_NOTIFIER_3__1 0x00000001 +#define NV927D_CORE_NOTIFIER_3__1_R1 31:0 +#define NV927D_CORE_NOTIFIER_3__2 0x00000002 +#define NV927D_CORE_NOTIFIER_3__2_R2 31:0 +#define NV927D_CORE_NOTIFIER_3__3 0x00000003 +#define NV927D_CORE_NOTIFIER_3__3_R3 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_R0 19:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA 20:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_R1 29:21 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE 30:30 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5 0x00000005 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE 3:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE 11:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE 15:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE 19:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE 27:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE 31:28 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6 0x00000006 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE 3:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE 11:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE 15:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE 19:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE 27:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE 31:28 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_7 0x00000007 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_7_R4 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_8 0x00000008 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_8_R5 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_9 0x00000009 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_9_R6 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_10 0x0000000A +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_10_R7 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_11 0x0000000B +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_11_R8 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12 0x0000000C +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0 31:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13 0x0000000D +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14 0x0000000E +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0 31:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15 0x0000000F +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16 0x00000010 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0 31:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17 0x00000011 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18 0x00000012 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0 31:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19 0x00000013 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A 8:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B 9:9 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1 10:10 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS 11:11 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2 12:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3 15:14 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4 19:17 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A 24:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B 25:25 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE 26:26 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6 31:27 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21 0x00000015 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_LVDS_CLK_MAX 23:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R8 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22 0x00000016 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A 8:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B 9:9 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1 10:10 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS 11:11 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2 12:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3 15:14 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4 19:17 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A 24:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B 25:25 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE 26:26 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6 31:27 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23 0x00000017 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_LVDS_CLK_MAX 23:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R8 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24 0x00000018 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A 8:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B 9:9 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1 10:10 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS 11:11 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2 12:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3 15:14 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4 19:17 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A 24:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B 25:25 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE 26:26 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6 31:27 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25 0x00000019 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_LVDS_CLK_MAX 23:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R8 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26 0x0000001A +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A 8:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B 9:9 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1 10:10 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS 11:11 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2 12:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3 15:14 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4 19:17 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A 24:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B 25:25 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE 26:26 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6 31:27 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27 0x0000001B +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_LVDS_CLK_MAX 23:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R8 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28 0x0000001C +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A 8:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B 9:9 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1 10:10 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS 11:11 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2 12:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3 15:14 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4 19:17 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A 24:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B 25:25 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE 26:26 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6 31:27 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29 0x0000001D +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_LVDS_CLK_MAX 23:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R8 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30 0x0000001E +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A 8:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B 9:9 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1 10:10 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS 11:11 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2 12:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3 15:14 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4 19:17 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A 24:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B 25:25 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE 26:26 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6 31:27 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31 0x0000001F +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_LVDS_CLK_MAX 23:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R8 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32 0x00000020 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A 8:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B 9:9 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1 10:10 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS 11:11 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2 12:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3 15:14 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4 19:17 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A 24:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B 25:25 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE 26:26 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6 31:27 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33 0x00000021 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_LVDS_CLK_MAX 23:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R8 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34 0x00000022 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A 8:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B 9:9 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1 10:10 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS 11:11 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2 12:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3 15:14 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4 19:17 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A 24:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B 25:25 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE 26:26 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6 31:27 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35 0x00000023 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_LVDS_CLK_MAX 23:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R8 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36 0x00000024 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0 31:7 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37 0x00000025 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38 0x00000026 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0 31:7 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39 0x00000027 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40 0x00000028 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0 31:7 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41 0x00000029 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42 0x0000002A +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0 31:7 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43 0x0000002B +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44 0x0000002C +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44_R0 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45 0x0000002D +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45_R1 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46 0x0000002E +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46_R0 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47 0x0000002F +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47_R1 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48 0x00000030 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48_R0 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49 0x00000031 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49_R1 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50 0x00000032 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50_R0 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51 0x00000033 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51_R1 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52 0x00000034 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53 0x00000035 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54 0x00000036 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55 0x00000037 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56 0x00000038 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57 0x00000039 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58 0x0000003A +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59 0x0000003B +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60 0x0000003C +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61 0x0000003D +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62 0x0000003E +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63 0x0000003F +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64 0x00000040 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65 0x00000041 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66 0x00000042 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67 0x00000043 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68 0x00000044 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69 0x00000045 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70 0x00000046 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71 0x00000047 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72 0x00000048 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73 0x00000049 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74 0x0000004A +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75 0x0000004B +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76 0x0000004C +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77 0x0000004D +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78 0x0000004E +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79 0x0000004F +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80 0x00000050 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81 0x00000051 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82 0x00000052 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83 0x00000053 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10 31:0 + + +// dma opcode instructions +#define NV927D_DMA 0x00000000 +#define NV927D_DMA_OPCODE 31:29 +#define NV927D_DMA_OPCODE_METHOD 0x00000000 +#define NV927D_DMA_OPCODE_JUMP 0x00000001 +#define NV927D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV927D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV927D_DMA_OPCODE 31:29 +#define NV927D_DMA_OPCODE_METHOD 0x00000000 +#define NV927D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV927D_DMA_METHOD_COUNT 27:18 +#define NV927D_DMA_METHOD_OFFSET 11:2 +#define NV927D_DMA_DATA 31:0 +#define NV927D_DMA_DATA_NOP 0x00000000 +#define NV927D_DMA_OPCODE 31:29 +#define NV927D_DMA_OPCODE_JUMP 0x00000001 +#define NV927D_DMA_JUMP_OFFSET 11:2 +#define NV927D_DMA_OPCODE 31:29 +#define NV927D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV927D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV927D_PUT (0x00000000) +#define NV927D_PUT_PTR 11:2 +#define NV927D_GET (0x00000004) +#define NV927D_GET_PTR 11:2 +#define NV927D_UPDATE (0x00000080) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR(i) (0 +(i)*4):(0 +(i)*4) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1 4 +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0 +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR1 4:4 +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR2 8:8 +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR3 12:12 +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE(i) (1 +(i)*4):(1 +(i)*4) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1 4 +#define NV927D_UPDATE_INTERLOCK_WITH_BASE_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE0 1:1 +#define NV927D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE1 5:5 +#define NV927D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE2 9:9 +#define NV927D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE3 13:13 +#define NV927D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY(i) (2 +(i)*4):(2 +(i)*4) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1 4 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY1 6:6 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY2 10:10 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY3 14:14 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i) (3 +(i)*4):(3 +(i)*4) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1 4 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 7:7 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2 11:11 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3 15:15 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE (0x00000001) +#define NV927D_UPDATE_SPECIAL_HANDLING 25:24 +#define NV927D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV927D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV927D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV927D_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV927D_UPDATE_NOT_DRIVER_FRIENDLY 31:31 +#define NV927D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000) +#define NV927D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001) +#define NV927D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30 +#define NV927D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000) +#define NV927D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001) +#define NV927D_UPDATE_INHIBIT_INTERRUPTS 29:29 +#define NV927D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NV927D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NV927D_SET_NOTIFIER_CONTROL (0x00000084) +#define NV927D_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV927D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV927D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV927D_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV927D_SET_NOTIFIER_CONTROL_NOTIFY 31:31 +#define NV927D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NV927D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NV927D_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV927D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV927D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV927D_SET_CONTEXT_DMA_NOTIFIER (0x00000088) +#define NV927D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV927D_GET_CAPABILITIES (0x0000008C) +#define NV927D_GET_CAPABILITIES_DUMMY 31:0 +#define NV927D_SET_SPARE (0x0000016C) +#define NV927D_SET_SPARE_UNUSED 31:0 +#define NV927D_SET_SPARE_NOOP(b) (0x00000170 + (b)*0x00000004) +#define NV927D_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV927D_DAC_SET_CONTROL(a) (0x00000180 + (a)*0x00000020) +#define NV927D_DAC_SET_CONTROL_OWNER_MASK 3:0 +#define NV927D_DAC_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV927D_DAC_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV927D_DAC_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV927D_DAC_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV927D_DAC_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV927D_DAC_SET_CONTROL_PROTOCOL 12:8 +#define NV927D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV927D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT (0x00000013) +#define NV927D_DAC_SET_SW_SPARE_A(a) (0x00000184 + (a)*0x00000020) +#define NV927D_DAC_SET_SW_SPARE_A_CODE 31:0 +#define NV927D_DAC_SET_SW_SPARE_B(a) (0x00000188 + (a)*0x00000020) +#define NV927D_DAC_SET_SW_SPARE_B_CODE 31:0 +#define NV927D_DAC_SET_CUSTOM_REASON(a) (0x00000190 + (a)*0x00000020) +#define NV927D_DAC_SET_CUSTOM_REASON_CODE 31:0 + +#define NV927D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020) +#define NV927D_SOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV927D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV927D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV927D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV927D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV927D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV927D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV927D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV927D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV927D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV927D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV927D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NV927D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NV927D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV927D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV927D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV927D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV927D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NV927D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NV927D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NV927D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NV927D_SOR_SET_SW_SPARE_A(a) (0x00000204 + (a)*0x00000020) +#define NV927D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NV927D_SOR_SET_SW_SPARE_B(a) (0x00000208 + (a)*0x00000020) +#define NV927D_SOR_SET_SW_SPARE_B_CODE 31:0 +#define NV927D_SOR_SET_CUSTOM_REASON(a) (0x00000210 + (a)*0x00000020) +#define NV927D_SOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV927D_PIOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NV927D_PIOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV927D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV927D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV927D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV927D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV927D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV927D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV927D_PIOR_SET_SW_SPARE_A(a) (0x00000304 + (a)*0x00000020) +#define NV927D_PIOR_SET_SW_SPARE_A_CODE 31:0 +#define NV927D_PIOR_SET_SW_SPARE_B(a) (0x00000308 + (a)*0x00000020) +#define NV927D_PIOR_SET_SW_SPARE_B_CODE 31:0 +#define NV927D_PIOR_SET_CUSTOM_REASON(a) (0x00000310 + (a)*0x00000020) +#define NV927D_PIOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV927D_HEAD_SET_PRESENT_CONTROL(a) (0x00000400 + (a)*0x00000300) +#define NV927D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NV927D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 8:8 +#define NV927D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NV927D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NV927D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00000404 + (a)*0x00000300) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 3:3 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 4:4 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 9:6 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000009) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 12:12 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 20:13 +#define NV927D_HEAD_SET_CONTROL(a) (0x00000408 + (a)*0x00000300) +#define NV927D_HEAD_SET_CONTROL_STRUCTURE 0:0 +#define NV927D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV927D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 3:2 +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 19:15 +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 7:4 +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 9:8 +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 14:10 +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK 1:1 +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_DISABLE (0x00000000) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_ENABLE (0x00000001) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN 24:20 +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN 29:25 +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000000) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000001) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000002) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000003) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000004) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000005) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000006) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000007) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000008) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x00000009) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000A) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000B) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000C) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000D) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000E) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x0000000F) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_UNSPECIFIED (0x00000010) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV927D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NV927D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NV927D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000410 + (a)*0x00000300) +#define NV927D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV927D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV927D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV927D_HEAD_SET_RASTER_SIZE(a) (0x00000414 + (a)*0x00000300) +#define NV927D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV927D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV927D_HEAD_SET_RASTER_SYNC_END(a) (0x00000418 + (a)*0x00000300) +#define NV927D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV927D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV927D_HEAD_SET_RASTER_BLANK_END(a) (0x0000041C + (a)*0x00000300) +#define NV927D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV927D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV927D_HEAD_SET_RASTER_BLANK_START(a) (0x00000420 + (a)*0x00000300) +#define NV927D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV927D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV927D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000424 + (a)*0x00000300) +#define NV927D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV927D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV927D_HEAD_SET_LOCK_CHAIN(a) (0x00000428 + (a)*0x00000300) +#define NV927D_HEAD_SET_LOCK_CHAIN_POSITION 27:24 +#define NV927D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000042C + (a)*0x00000300) +#define NV927D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV927D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV927D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV927D_HEAD_SET_CRC_CONTROL(a) (0x00000430 + (a)*0x00000300) +#define NV927D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 1:0 +#define NV927D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000000) +#define NV927D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_BASE (0x00000001) +#define NV927D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_OVERLAY (0x00000002) +#define NV927D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 2:2 +#define NV927D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NV927D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NV927D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE 3:3 +#define NV927D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_FALSE (0x00000000) +#define NV927D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_TRUE (0x00000001) +#define NV927D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE 4:4 +#define NV927D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_FALSE (0x00000000) +#define NV927D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_TRUE (0x00000001) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT 19:8 +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC__SIZE_1 4 +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC0 (0x00000FF0) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC1 (0x00000FF1) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC2 (0x00000FF2) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC3 (0x00000FF3) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG__SIZE_1 4 +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG0 (0x00000FF8) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG1 (0x00000FF9) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG2 (0x00000FFA) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG3 (0x00000FFB) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR__SIZE_1 8 +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR0 (0x00000F0F) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR1 (0x00000F1F) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR2 (0x00000F2F) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR3 (0x00000F3F) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR4 (0x00000F4F) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR5 (0x00000F5F) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR6 (0x00000F6F) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR7 (0x00000F7F) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF__SIZE_1 4 +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF0 (0x00000F8F) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF1 (0x00000F9F) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF2 (0x00000FAF) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF3 (0x00000FBF) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR__SIZE_1 8 +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR0 (0x000000FF) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR1 (0x000001FF) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR2 (0x000002FF) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR3 (0x000003FF) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR4 (0x000004FF) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR5 (0x000005FF) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR6 (0x000006FF) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR7 (0x000007FF) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_NONE (0x00000FFF) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT 31:20 +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC__SIZE_1 4 +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC0 (0x00000FF0) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC1 (0x00000FF1) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC2 (0x00000FF2) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC3 (0x00000FF3) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG__SIZE_1 4 +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG0 (0x00000FF8) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG1 (0x00000FF9) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG2 (0x00000FFA) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG3 (0x00000FFB) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR__SIZE_1 8 +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR0 (0x00000F0F) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR1 (0x00000F1F) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR2 (0x00000F2F) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR3 (0x00000F3F) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR4 (0x00000F4F) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR5 (0x00000F5F) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR6 (0x00000F6F) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR7 (0x00000F7F) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF__SIZE_1 4 +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF0 (0x00000F8F) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF1 (0x00000F9F) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF2 (0x00000FAF) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF3 (0x00000FBF) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR__SIZE_1 8 +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR0 (0x000000FF) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR1 (0x000001FF) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR2 (0x000002FF) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR3 (0x000003FF) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR4 (0x000004FF) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR5 (0x000005FF) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR6 (0x000006FF) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR7 (0x000007FF) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_NONE (0x00000FFF) +#define NV927D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 5:5 +#define NV927D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC 6:6 +#define NV927D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_DISABLE (0x00000000) +#define NV927D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_ENABLE (0x00000001) +#define NV927D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00000438 + (a)*0x00000300) +#define NV927D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NV927D_HEAD_SET_BASE_LUT_LO(a) (0x00000440 + (a)*0x00000300) +#define NV927D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV927D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE 27:24 +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV927D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV927D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_BASE_LUT_HI(a) (0x00000444 + (a)*0x00000300) +#define NV927D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV927D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000448 + (a)*0x00000300) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000044C + (a)*0x00000300) +#define NV927D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x00000450 + (a)*0x00000300) +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x00000454 + (a)*0x00000300) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE 21:20 +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25 (0x00000000) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28 (0x00000001) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM (0x00000002) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 24:24 +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING 25:25 +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE (0x00000000) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE (0x00000001) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 26:26 +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00000458 + (a)*0x00000300) +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NV927D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000045C + (a)*0x00000300) +#define NV927D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV927D_HEAD_SET_OFFSET(a) (0x00000460 + (a)*0x00000300) +#define NV927D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV927D_HEAD_SET_SIZE(a) (0x00000468 + (a)*0x00000300) +#define NV927D_HEAD_SET_SIZE_WIDTH 15:0 +#define NV927D_HEAD_SET_SIZE_HEIGHT 31:16 +#define NV927D_HEAD_SET_STORAGE(a) (0x0000046C + (a)*0x00000300) +#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV927D_HEAD_SET_STORAGE_PITCH 20:8 +#define NV927D_HEAD_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV927D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV927D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV927D_HEAD_SET_PARAMS(a) (0x00000470 + (a)*0x00000300) +#define NV927D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV927D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV927D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV927D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV927D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV927D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV927D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV927D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV927D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024) +#define NV927D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV927D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV927D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV927D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV927D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV927D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV927D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV927D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV927D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV927D_HEAD_SET_PARAMS_GAMMA 2:2 +#define NV927D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV927D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV927D_HEAD_SET_CONTEXT_DMAS_ISO(a) (0x00000474 + (a)*0x00000300) +#define NV927D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV927D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x0000047C + (a)*0x00000300) +#define NV927D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 1:0 +#define NV927D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NV927D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NV927D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_SPEC_FLIP (0x00000002) +#define NV927D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300) +#define NV927D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV927D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV927D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV927D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE 27:26 +#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NV927D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 15:8 +#define NV927D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 23:16 +#define NV927D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV927D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV927D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV927D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV927D_HEAD_SET_OFFSETS_CURSOR(a,b) (0x00000484 + (a)*0x00000300 + (b)*0x00000004) +#define NV927D_HEAD_SET_OFFSETS_CURSOR_ORIGIN 31:0 +#define NV927D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b) (0x0000048C + (a)*0x00000300 + (b)*0x00000004) +#define NV927D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE 31:0 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00000494 + (a)*0x00000300) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422 8:8 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE (0x00000000) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE (0x00000001) +#define NV927D_HEAD_SET_PROCAMP(a) (0x00000498 + (a)*0x00000300) +#define NV927D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV927D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV927D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV927D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV927D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV927D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV927D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV927D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV927D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV927D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 5:5 +#define NV927D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NV927D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NV927D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 6:6 +#define NV927D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) +#define NV927D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) +#define NV927D_HEAD_SET_DITHER_CONTROL(a) (0x000004A0 + (a)*0x00000300) +#define NV927D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV927D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV927D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV927D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV927D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002) +#define NV927D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NV927D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV927D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x000004B0 + (a)*0x00000300) +#define NV927D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV927D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV927D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000004B8 + (a)*0x00000300) +#define NV927D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV927D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV927D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x000004BC + (a)*0x00000300) +#define NV927D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NV927D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000004C0 + (a)*0x00000300) +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000004C4 + (a)*0x00000300) +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a) (0x000004C8 + (a)*0x00000300) +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH 14:0 +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT 30:16 +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT 17:16 +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE (0x00000000) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257 (0x00000001) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025 (0x00000002) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT 21:20 +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x000004D4 + (a)*0x00000300) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT 13:12 +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE (0x00000000) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257 (0x00000001) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025 (0x00000002) +#define NV927D_HEAD_SET_PROCESSING(a) (0x000004E0 + (a)*0x00000300) +#define NV927D_HEAD_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV927D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV927D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV927D_HEAD_SET_CONVERSION_RED(a) (0x000004E4 + (a)*0x00000300) +#define NV927D_HEAD_SET_CONVERSION_RED_GAIN 15:0 +#define NV927D_HEAD_SET_CONVERSION_RED_OFS 31:16 +#define NV927D_HEAD_SET_CONVERSION_GRN(a) (0x000004E8 + (a)*0x00000300) +#define NV927D_HEAD_SET_CONVERSION_GRN_GAIN 15:0 +#define NV927D_HEAD_SET_CONVERSION_GRN_OFS 31:16 +#define NV927D_HEAD_SET_CONVERSION_BLU(a) (0x000004EC + (a)*0x00000300) +#define NV927D_HEAD_SET_CONVERSION_BLU_GAIN 15:0 +#define NV927D_HEAD_SET_CONVERSION_BLU_OFS 31:16 +#define NV927D_HEAD_SET_CSC_RED2RED(a) (0x000004F0 + (a)*0x00000300) +#define NV927D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE 31:31 +#define NV927D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_CSC_RED2RED_COEFF 18:0 +#define NV927D_HEAD_SET_CSC_GRN2RED(a) (0x000004F4 + (a)*0x00000300) +#define NV927D_HEAD_SET_CSC_GRN2RED_COEFF 18:0 +#define NV927D_HEAD_SET_CSC_BLU2RED(a) (0x000004F8 + (a)*0x00000300) +#define NV927D_HEAD_SET_CSC_BLU2RED_COEFF 18:0 +#define NV927D_HEAD_SET_CSC_CONSTANT2RED(a) (0x000004FC + (a)*0x00000300) +#define NV927D_HEAD_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV927D_HEAD_SET_CSC_RED2GRN(a) (0x00000500 + (a)*0x00000300) +#define NV927D_HEAD_SET_CSC_RED2GRN_COEFF 18:0 +#define NV927D_HEAD_SET_CSC_GRN2GRN(a) (0x00000504 + (a)*0x00000300) +#define NV927D_HEAD_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV927D_HEAD_SET_CSC_BLU2GRN(a) (0x00000508 + (a)*0x00000300) +#define NV927D_HEAD_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV927D_HEAD_SET_CSC_CONSTANT2GRN(a) (0x0000050C + (a)*0x00000300) +#define NV927D_HEAD_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV927D_HEAD_SET_CSC_RED2BLU(a) (0x00000510 + (a)*0x00000300) +#define NV927D_HEAD_SET_CSC_RED2BLU_COEFF 18:0 +#define NV927D_HEAD_SET_CSC_GRN2BLU(a) (0x00000514 + (a)*0x00000300) +#define NV927D_HEAD_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV927D_HEAD_SET_CSC_BLU2BLU(a) (0x00000518 + (a)*0x00000300) +#define NV927D_HEAD_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV927D_HEAD_SET_CSC_CONSTANT2BLU(a) (0x0000051C + (a)*0x00000300) +#define NV927D_HEAD_SET_CSC_CONSTANT2BLU_COEFF 18:0 +#define NV927D_HEAD_SET_HDMI_CTRL(a) (0x00000520 + (a)*0x00000300) +#define NV927D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NV927D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NV927D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NV927D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NV927D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NV927D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE 15:12 +#define NV927D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000000) +#define NV927D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FIELD_ALTERNATIVE (0x00000001) +#define NV927D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_LINE_ALTERNATIVE (0x00000002) +#define NV927D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_FULL (0x00000003) +#define NV927D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH (0x00000004) +#define NV927D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH_GRAPHICS (0x00000005) +#define NV927D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_TOP_AND_BOTTOM (0x00000006) +#define NV927D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_HALF (0x00000008) +#define NV927D_HEAD_SET_VACTIVE_SPACE_COLOR(a) (0x00000524 + (a)*0x00000300) +#define NV927D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR 9:0 +#define NV927D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y 19:10 +#define NV927D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB 29:20 +#define NV927D_HEAD_SET_DISPLAY_ID(a,b) (0x0000052C + (a)*0x00000300 + (b)*0x00000004) +#define NV927D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NV927D_HEAD_SET_SW_SPARE_A(a) (0x0000054C + (a)*0x00000300) +#define NV927D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NV927D_HEAD_SET_SW_SPARE_B(a) (0x00000550 + (a)*0x00000300) +#define NV927D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NV927D_HEAD_SET_SW_SPARE_C(a) (0x00000554 + (a)*0x00000300) +#define NV927D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NV927D_HEAD_SET_SW_SPARE_D(a) (0x00000558 + (a)*0x00000300) +#define NV927D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NV927D_HEAD_SET_GET_BLANKING_CTRL(a) (0x0000055C + (a)*0x00000300) +#define NV927D_HEAD_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NV927D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NV927D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NV927D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NV927D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NV927D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) +#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a) (0x000006D0 + (a)*0x00000300) +#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED 31:0 +#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a) (0x000006D4 + (a)*0x00000300) +#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED 31:0 +#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a) (0x000006D8 + (a)*0x00000300) +#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED 31:0 +#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a) (0x000006DC + (a)*0x00000300) +#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED 31:0 +#define NV927D_HEAD_SET_SPARE(a) (0x000006EC + (a)*0x00000300) +#define NV927D_HEAD_SET_SPARE_UNUSED 31:0 +#define NV927D_HEAD_SET_SPARE_NOOP(a,b) (0x000006F0 + (a)*0x00000300 + (b)*0x00000004) +#define NV927D_HEAD_SET_SPARE_NOOP_UNUSED 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl927d_h diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl9470.h b/userspace/sdks/nv525/nvidia/inc/class/cl9470.h new file mode 100644 index 0000000..faacb95 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl9470.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9470.finn +// + +#define NV9470_DISPLAY (0x9470U) /* finn: Evaluated from "NV9470_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV9470_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9470U) + +typedef struct NV9470_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numDacs; // Number of DACs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NV9470_ALLOCATION_PARAMETERS; diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl9471.h b/userspace/sdks/nv525/nvidia/inc/class/cl9471.h new file mode 100644 index 0000000..c5f557f --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl9471.h @@ -0,0 +1,295 @@ +/* + * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl9471_h_ +#define _cl9471_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV9471_DISP_SF_USER 0x9471 + +typedef volatile struct _cl9471_tag0 { + NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x00690FFF:0x00690000 */ +} _Nv9471DispSfUser, Nv9471DispSfUserMap; + +#define NV9471_SF_HDMI_INFO_IDX_AVI_INFOFRAME 0x00000000 /* */ +#define NV9471_SF_HDMI_INFO_IDX_GENERIC_INFOFRAME 0x00000001 /* */ +#define NV9471_SF_HDMI_INFO_IDX_GCP 0x00000003 /* */ +#define NV9471_SF_HDMI_INFO_IDX_VSI 0x00000004 /* */ +#define NV9471_SF_HDMI_INFO_CTRL(i,j) (0x00690000-0x00690000+(i)*1024+(j)*64) /* RWX4A */ +#define NV9471_SF_HDMI_INFO_CTRL__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_INFO_CTRL__SIZE_2 5 /* */ +#define NV9471_SF_HDMI_INFO_CTRL_ENABLE 0:0 /* RWIVF */ +#define NV9471_SF_HDMI_INFO_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_INFO_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NV9471_SF_HDMI_INFO_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NV9471_SF_HDMI_INFO_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NV9471_SF_HDMI_INFO_CTRL_OTHER 4:4 /* RWIVF */ +#define NV9471_SF_HDMI_INFO_CTRL_OTHER_DIS 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_INFO_CTRL_OTHER_EN 0x00000001 /* RW--V */ +#define NV9471_SF_HDMI_INFO_CTRL_SINGLE 8:8 /* RWIVF */ +#define NV9471_SF_HDMI_INFO_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_INFO_CTRL_SINGLE_EN 0x00000001 /* RW--V */ +#define NV9471_SF_HDMI_INFO_CTRL_CHKSUM_HW 9:9 /* RWIVF */ +#define NV9471_SF_HDMI_INFO_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */ +#define NV9471_SF_HDMI_INFO_CTRL_CHKSUM_HW_EN 0x00000001 /* RW--V */ +#define NV9471_SF_HDMI_INFO_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */ +#define NV9471_SF_HDMI_INFO_CTRL_CHKSUM_HW_DIS 0x00000000 /* RW--V */ +#define NV9471_SF_HDMI_INFO_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */ +#define NV9471_SF_HDMI_INFO_CTRL_HBLANK 12:12 /* RWIVF */ +#define NV9471_SF_HDMI_INFO_CTRL_HBLANK_DIS 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_INFO_CTRL_HBLANK_EN 0x00000001 /* RW--V */ +#define NV9471_SF_HDMI_INFO_CTRL_VIDEO_FMT 16:16 /* RWIVF */ +#define NV9471_SF_HDMI_INFO_CTRL_VIDEO_FMT_SW_CONTROLLED 0x00000000 /* RW--V */ +#define NV9471_SF_HDMI_INFO_CTRL_VIDEO_FMT_HW_CONTROLLED 0x00000001 /* RW--V */ +#define NV9471_SF_HDMI_INFO_CTRL_VIDEO_FMT_INIT 0x00000001 /* RWI-V */ +#define NV9471_SF_HDMI_INFO_STATUS(i,j) (0x00690004-0x00690000+(i)*1024+(j)*64) /* R--4A */ +#define NV9471_SF_HDMI_INFO_STATUS__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_INFO_STATUS__SIZE_2 5 /* */ +#define NV9471_SF_HDMI_INFO_STATUS_SENT 0:0 /* R--VF */ +#define NV9471_SF_HDMI_INFO_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NV9471_SF_HDMI_INFO_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NV9471_SF_HDMI_INFO_STATUS_SENT_INIT 0x00000000 /* R-I-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x00690000-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x00690008-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x0069000C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x00690010-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x00690014-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x00690018-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_HEADER(i) (0x00690048-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_GENERIC_HEADER__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_GENERIC_HEADER_HB0 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_HEADER_HB1 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_HEADER_HB2 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW(i) (0x0069004C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_HIGH(i) (0x00690050-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW(i) (0x00690054-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_HIGH(i) (0x00690058-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW(i) (0x0069005C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_HIGH(i) (0x00690060-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_HIGH__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW(i) (0x00690064-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24 31:24 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_HIGH(i) (0x00690068-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_HIGH__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GCP_SUBPACK(i) (0x006900CC-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_GCP_SUBPACK__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_GCP_SUBPACK_SB0 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_GCP_SUBPACK_SB0_INIT 0x00000001 /* RWI-V */ +#define NV9471_SF_HDMI_GCP_SUBPACK_SB0_SET_AVMUTE 0x00000001 /* RW--V */ +#define NV9471_SF_HDMI_GCP_SUBPACK_SB0_CLR_AVMUTE 0x00000010 /* RW--V */ +#define NV9471_SF_HDMI_GCP_SUBPACK_SB1 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_GCP_SUBPACK_SB1_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GCP_SUBPACK_SB2 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_GCP_SUBPACK_SB2_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_HEADER(i) (0x00690108-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_VSI_HEADER__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_VSI_HEADER_HB0 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_HEADER_HB1 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_HEADER_HB2 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW(i) (0x0069010C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_HIGH(i) (0x00690110-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW(i) (0x00690114-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_HIGH(i) (0x00690118-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW(i) (0x0069011C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_HIGH(i) (0x00690120-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_HIGH__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW(i) (0x00690124-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW_PB21 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW_PB22 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW_PB23 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW_PB24 31:24 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_HIGH(i) (0x00690128-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_HIGH__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _cl9471_h_ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl947d.h b/userspace/sdks/nv525/nvidia/inc/class/cl947d.h new file mode 100644 index 0000000..6842406 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl947d.h @@ -0,0 +1,1606 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl947d_h_ +#define _cl947d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV947D_CORE_CHANNEL_DMA (0x0000947D) + +#define NV947D_CORE_NOTIFIER_3 0x00000000 +#define NV947D_CORE_NOTIFIER_3_SIZEOF 0x00000150 +#define NV947D_CORE_NOTIFIER_3_COMPLETION_0 0x00000000 +#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_DONE 0:0 +#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_R0 15:1 +#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP 29:16 +#define NV947D_CORE_NOTIFIER_3__1 0x00000001 +#define NV947D_CORE_NOTIFIER_3__1_R1 31:0 +#define NV947D_CORE_NOTIFIER_3__2 0x00000002 +#define NV947D_CORE_NOTIFIER_3__2_R2 31:0 +#define NV947D_CORE_NOTIFIER_3__3 0x00000003 +#define NV947D_CORE_NOTIFIER_3__3_R3 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_R0 19:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA 20:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_R1 29:21 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE 30:30 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5 0x00000005 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE 3:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE 11:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE 15:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE 19:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE 27:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6 0x00000006 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE 3:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE 11:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE 15:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE 19:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE 27:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_7 0x00000007 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_7_R4 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_8 0x00000008 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_8_R5 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_9 0x00000009 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_9_R6 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_10 0x0000000A +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_10_R7 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_11 0x0000000B +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_11_R8 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12 0x0000000C +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0 31:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13 0x0000000D +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14 0x0000000E +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0 31:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15 0x0000000F +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16 0x00000010 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0 31:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17 0x00000011 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18 0x00000012 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0 31:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19 0x00000013 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A 8:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B 9:9 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1 10:10 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS 11:11 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2 12:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3 15:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4 19:17 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A 24:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B 25:25 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE 26:26 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21 0x00000015 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_LVDS_CLK_MAX 23:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R8 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22 0x00000016 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A 8:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B 9:9 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1 10:10 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS 11:11 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2 12:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3 15:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4 19:17 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A 24:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B 25:25 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE 26:26 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23 0x00000017 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_LVDS_CLK_MAX 23:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R8 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24 0x00000018 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A 8:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B 9:9 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1 10:10 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS 11:11 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2 12:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3 15:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4 19:17 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A 24:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B 25:25 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE 26:26 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25 0x00000019 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_LVDS_CLK_MAX 23:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R8 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26 0x0000001A +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A 8:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B 9:9 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1 10:10 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS 11:11 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2 12:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3 15:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4 19:17 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A 24:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B 25:25 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE 26:26 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27 0x0000001B +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_LVDS_CLK_MAX 23:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R8 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28 0x0000001C +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A 8:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B 9:9 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1 10:10 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS 11:11 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2 12:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3 15:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4 19:17 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A 24:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B 25:25 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE 26:26 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29 0x0000001D +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_LVDS_CLK_MAX 23:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R8 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30 0x0000001E +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A 8:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B 9:9 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1 10:10 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS 11:11 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2 12:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3 15:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4 19:17 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A 24:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B 25:25 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE 26:26 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31 0x0000001F +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_LVDS_CLK_MAX 23:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R8 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32 0x00000020 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A 8:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B 9:9 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1 10:10 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS 11:11 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2 12:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3 15:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4 19:17 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A 24:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B 25:25 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE 26:26 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33 0x00000021 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_LVDS_CLK_MAX 23:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R8 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34 0x00000022 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A 8:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B 9:9 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1 10:10 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS 11:11 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2 12:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3 15:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4 19:17 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A 24:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B 25:25 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE 26:26 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35 0x00000023 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_LVDS_CLK_MAX 23:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R8 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36 0x00000024 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0 31:7 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37 0x00000025 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38 0x00000026 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0 31:7 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39 0x00000027 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40 0x00000028 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0 31:7 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41 0x00000029 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42 0x0000002A +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0 31:7 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43 0x0000002B +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44 0x0000002C +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44_R0 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45 0x0000002D +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45_R1 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46 0x0000002E +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46_R0 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47 0x0000002F +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47_R1 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48 0x00000030 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48_R0 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49 0x00000031 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49_R1 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50 0x00000032 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50_R0 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51 0x00000033 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51_R1 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52 0x00000034 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_REORDER_BANK_WIDTH_SIZE_MAX 13:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0 31:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53 0x00000035 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54 0x00000036 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55 0x00000037 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56 0x00000038 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57 0x00000039 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58 0x0000003A +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59 0x0000003B +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60 0x0000003C +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_REORDER_BANK_WIDTH_SIZE_MAX 13:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0 31:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61 0x0000003D +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62 0x0000003E +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63 0x0000003F +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64 0x00000040 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65 0x00000041 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66 0x00000042 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67 0x00000043 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68 0x00000044 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_REORDER_BANK_WIDTH_SIZE_MAX 13:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0 31:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69 0x00000045 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70 0x00000046 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71 0x00000047 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72 0x00000048 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73 0x00000049 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74 0x0000004A +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75 0x0000004B +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76 0x0000004C +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_REORDER_BANK_WIDTH_SIZE_MAX 13:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0 31:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77 0x0000004D +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78 0x0000004E +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79 0x0000004F +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80 0x00000050 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81 0x00000051 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82 0x00000052 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83 0x00000053 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10 31:0 + + +// dma opcode instructions +#define NV947D_DMA 0x00000000 +#define NV947D_DMA_OPCODE 31:29 +#define NV947D_DMA_OPCODE_METHOD 0x00000000 +#define NV947D_DMA_OPCODE_JUMP 0x00000001 +#define NV947D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV947D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV947D_DMA_METHOD_COUNT 27:18 +#define NV947D_DMA_METHOD_OFFSET 11:2 +#define NV947D_DMA_DATA 31:0 +#define NV947D_DMA_DATA_NOP 0x00000000 +#define NV947D_DMA_JUMP_OFFSET 11:2 +#define NV947D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV947D_PUT (0x00000000) +#define NV947D_PUT_PTR 11:2 +#define NV947D_GET (0x00000004) +#define NV947D_GET_PTR 11:2 +#define NV947D_UPDATE (0x00000080) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR(i) (0 +(i)*4):(0 +(i)*4) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1 4 +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0 +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR1 4:4 +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR2 8:8 +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR3 12:12 +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE(i) (1 +(i)*4):(1 +(i)*4) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1 4 +#define NV947D_UPDATE_INTERLOCK_WITH_BASE_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE0 1:1 +#define NV947D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE1 5:5 +#define NV947D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE2 9:9 +#define NV947D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE3 13:13 +#define NV947D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY(i) (2 +(i)*4):(2 +(i)*4) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1 4 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY1 6:6 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY2 10:10 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY3 14:14 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i) (3 +(i)*4):(3 +(i)*4) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1 4 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 7:7 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2 11:11 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3 15:15 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE (0x00000001) +#define NV947D_UPDATE_SPECIAL_HANDLING 25:24 +#define NV947D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV947D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV947D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV947D_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV947D_UPDATE_NOT_DRIVER_FRIENDLY 31:31 +#define NV947D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000) +#define NV947D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001) +#define NV947D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30 +#define NV947D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000) +#define NV947D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001) +#define NV947D_UPDATE_INHIBIT_INTERRUPTS 29:29 +#define NV947D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NV947D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NV947D_SET_NOTIFIER_CONTROL (0x00000084) +#define NV947D_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV947D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV947D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV947D_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV947D_SET_NOTIFIER_CONTROL_NOTIFY 31:31 +#define NV947D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NV947D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NV947D_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV947D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV947D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV947D_SET_CONTEXT_DMA_NOTIFIER (0x00000088) +#define NV947D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV947D_GET_CAPABILITIES (0x0000008C) +#define NV947D_GET_CAPABILITIES_DUMMY 31:0 +#define NV947D_SET_SPARE (0x0000016C) +#define NV947D_SET_SPARE_UNUSED 31:0 +#define NV947D_SET_SPARE_NOOP(b) (0x00000170 + (b)*0x00000004) +#define NV947D_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV947D_DAC_SET_CONTROL(a) (0x00000180 + (a)*0x00000020) +#define NV947D_DAC_SET_CONTROL_OWNER_MASK 3:0 +#define NV947D_DAC_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV947D_DAC_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV947D_DAC_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV947D_DAC_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV947D_DAC_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV947D_DAC_SET_CONTROL_PROTOCOL 12:8 +#define NV947D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV947D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT (0x00000013) +#define NV947D_DAC_SET_SW_SPARE_A(a) (0x00000184 + (a)*0x00000020) +#define NV947D_DAC_SET_SW_SPARE_A_CODE 31:0 +#define NV947D_DAC_SET_SW_SPARE_B(a) (0x00000188 + (a)*0x00000020) +#define NV947D_DAC_SET_SW_SPARE_B_CODE 31:0 +#define NV947D_DAC_SET_CUSTOM_REASON(a) (0x00000190 + (a)*0x00000020) +#define NV947D_DAC_SET_CUSTOM_REASON_CODE 31:0 + +#define NV947D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020) +#define NV947D_SOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV947D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV947D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV947D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV947D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV947D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV947D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV947D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV947D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV947D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV947D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV947D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NV947D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NV947D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV947D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV947D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV947D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV947D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NV947D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NV947D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NV947D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NV947D_SOR_SET_SW_SPARE_A(a) (0x00000204 + (a)*0x00000020) +#define NV947D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NV947D_SOR_SET_SW_SPARE_B(a) (0x00000208 + (a)*0x00000020) +#define NV947D_SOR_SET_SW_SPARE_B_CODE 31:0 +#define NV947D_SOR_SET_CUSTOM_REASON(a) (0x00000210 + (a)*0x00000020) +#define NV947D_SOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV947D_PIOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NV947D_PIOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV947D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV947D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV947D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV947D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV947D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV947D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV947D_PIOR_SET_SW_SPARE_A(a) (0x00000304 + (a)*0x00000020) +#define NV947D_PIOR_SET_SW_SPARE_A_CODE 31:0 +#define NV947D_PIOR_SET_SW_SPARE_B(a) (0x00000308 + (a)*0x00000020) +#define NV947D_PIOR_SET_SW_SPARE_B_CODE 31:0 +#define NV947D_PIOR_SET_CUSTOM_REASON(a) (0x00000310 + (a)*0x00000020) +#define NV947D_PIOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV947D_HEAD_SET_PRESENT_CONTROL(a) (0x00000400 + (a)*0x00000300) +#define NV947D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NV947D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 8:8 +#define NV947D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NV947D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NV947D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00000404 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 3:3 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 4:4 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 9:6 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000009) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 12:12 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 20:13 +#define NV947D_HEAD_SET_CONTROL(a) (0x00000408 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTROL_STRUCTURE 0:0 +#define NV947D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 3:2 +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 19:15 +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 7:4 +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 9:8 +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 14:10 +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK 1:1 +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_DISABLE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN 24:20 +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN 29:25 +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000000) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000001) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000002) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000003) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000004) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000005) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000006) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000007) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000008) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x00000009) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000A) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000B) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000C) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000D) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000E) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x0000000F) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_UNSPECIFIED (0x00000010) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV947D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NV947D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NV947D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000410 + (a)*0x00000300) +#define NV947D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV947D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV947D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV947D_HEAD_SET_RASTER_SIZE(a) (0x00000414 + (a)*0x00000300) +#define NV947D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV947D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV947D_HEAD_SET_RASTER_SYNC_END(a) (0x00000418 + (a)*0x00000300) +#define NV947D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV947D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV947D_HEAD_SET_RASTER_BLANK_END(a) (0x0000041C + (a)*0x00000300) +#define NV947D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV947D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV947D_HEAD_SET_RASTER_BLANK_START(a) (0x00000420 + (a)*0x00000300) +#define NV947D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV947D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV947D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000424 + (a)*0x00000300) +#define NV947D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV947D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV947D_HEAD_SET_LOCK_CHAIN(a) (0x00000428 + (a)*0x00000300) +#define NV947D_HEAD_SET_LOCK_CHAIN_POSITION 27:24 +#define NV947D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000042C + (a)*0x00000300) +#define NV947D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV947D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV947D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV947D_HEAD_SET_CRC_CONTROL(a) (0x00000430 + (a)*0x00000300) +#define NV947D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 1:0 +#define NV947D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000000) +#define NV947D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_BASE (0x00000001) +#define NV947D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_OVERLAY (0x00000002) +#define NV947D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 2:2 +#define NV947D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NV947D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NV947D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE 3:3 +#define NV947D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_FALSE (0x00000000) +#define NV947D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_TRUE (0x00000001) +#define NV947D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE 4:4 +#define NV947D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_FALSE (0x00000000) +#define NV947D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_TRUE (0x00000001) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT 19:8 +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC__SIZE_1 4 +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC0 (0x00000FF0) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC1 (0x00000FF1) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC2 (0x00000FF2) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC3 (0x00000FF3) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG__SIZE_1 4 +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG0 (0x00000FF8) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG1 (0x00000FF9) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG2 (0x00000FFA) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG3 (0x00000FFB) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR__SIZE_1 8 +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR0 (0x00000F0F) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR1 (0x00000F1F) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR2 (0x00000F2F) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR3 (0x00000F3F) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR4 (0x00000F4F) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR5 (0x00000F5F) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR6 (0x00000F6F) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR7 (0x00000F7F) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF__SIZE_1 4 +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF0 (0x00000F8F) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF1 (0x00000F9F) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF2 (0x00000FAF) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF3 (0x00000FBF) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR__SIZE_1 8 +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR0 (0x000000FF) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR1 (0x000001FF) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR2 (0x000002FF) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR3 (0x000003FF) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR4 (0x000004FF) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR5 (0x000005FF) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR6 (0x000006FF) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR7 (0x000007FF) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_NONE (0x00000FFF) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT 31:20 +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC__SIZE_1 4 +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC0 (0x00000FF0) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC1 (0x00000FF1) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC2 (0x00000FF2) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC3 (0x00000FF3) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG__SIZE_1 4 +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG0 (0x00000FF8) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG1 (0x00000FF9) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG2 (0x00000FFA) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG3 (0x00000FFB) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR__SIZE_1 8 +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR0 (0x00000F0F) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR1 (0x00000F1F) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR2 (0x00000F2F) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR3 (0x00000F3F) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR4 (0x00000F4F) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR5 (0x00000F5F) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR6 (0x00000F6F) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR7 (0x00000F7F) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF__SIZE_1 4 +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF0 (0x00000F8F) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF1 (0x00000F9F) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF2 (0x00000FAF) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF3 (0x00000FBF) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR__SIZE_1 8 +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR0 (0x000000FF) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR1 (0x000001FF) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR2 (0x000002FF) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR3 (0x000003FF) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR4 (0x000004FF) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR5 (0x000005FF) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR6 (0x000006FF) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR7 (0x000007FF) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_NONE (0x00000FFF) +#define NV947D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 5:5 +#define NV947D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC 6:6 +#define NV947D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_DISABLE (0x00000000) +#define NV947D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00000438 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NV947D_HEAD_SET_BASE_LUT_LO(a) (0x00000440 + (a)*0x00000300) +#define NV947D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV947D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE 27:24 +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV947D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV947D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_BASE_LUT_HI(a) (0x00000444 + (a)*0x00000300) +#define NV947D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV947D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000448 + (a)*0x00000300) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000044C + (a)*0x00000300) +#define NV947D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x00000450 + (a)*0x00000300) +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x00000454 + (a)*0x00000300) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE 21:20 +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25 (0x00000000) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28 (0x00000001) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM (0x00000002) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 24:24 +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING 25:25 +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE (0x00000000) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE (0x00000001) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 26:26 +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00000458 + (a)*0x00000300) +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NV947D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000045C + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV947D_HEAD_SET_OFFSET(a) (0x00000460 + (a)*0x00000300) +#define NV947D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV947D_HEAD_SET_SIZE(a) (0x00000468 + (a)*0x00000300) +#define NV947D_HEAD_SET_SIZE_WIDTH 15:0 +#define NV947D_HEAD_SET_SIZE_HEIGHT 31:16 +#define NV947D_HEAD_SET_STORAGE(a) (0x0000046C + (a)*0x00000300) +#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV947D_HEAD_SET_STORAGE_PITCH 20:8 +#define NV947D_HEAD_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV947D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV947D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV947D_HEAD_SET_PARAMS(a) (0x00000470 + (a)*0x00000300) +#define NV947D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV947D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV947D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV947D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV947D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV947D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV947D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV947D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV947D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024) +#define NV947D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV947D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV947D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV947D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV947D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV947D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV947D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV947D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV947D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV947D_HEAD_SET_PARAMS_GAMMA 2:2 +#define NV947D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV947D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV947D_HEAD_SET_CONTEXT_DMAS_ISO(a) (0x00000474 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV947D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x0000047C + (a)*0x00000300) +#define NV947D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 1:0 +#define NV947D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NV947D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NV947D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_SPEC_FLIP (0x00000002) +#define NV947D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV947D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV947D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV947D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE 27:26 +#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NV947D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 15:8 +#define NV947D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 23:16 +#define NV947D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV947D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV947D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV947D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV947D_HEAD_SET_OFFSETS_CURSOR(a,b) (0x00000484 + (a)*0x00000300 + (b)*0x00000004) +#define NV947D_HEAD_SET_OFFSETS_CURSOR_ORIGIN 31:0 +#define NV947D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b) (0x0000048C + (a)*0x00000300 + (b)*0x00000004) +#define NV947D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE 31:0 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00000494 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422 8:8 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE (0x00000001) +#define NV947D_HEAD_SET_PROCAMP(a) (0x00000498 + (a)*0x00000300) +#define NV947D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV947D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV947D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV947D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV947D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV947D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV947D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV947D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV947D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV947D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 5:5 +#define NV947D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NV947D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NV947D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 6:6 +#define NV947D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) +#define NV947D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) +#define NV947D_HEAD_SET_DITHER_CONTROL(a) (0x000004A0 + (a)*0x00000300) +#define NV947D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV947D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV947D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV947D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV947D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002) +#define NV947D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NV947D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV947D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x000004B0 + (a)*0x00000300) +#define NV947D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV947D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV947D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000004B8 + (a)*0x00000300) +#define NV947D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV947D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV947D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x000004BC + (a)*0x00000300) +#define NV947D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NV947D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000004C0 + (a)*0x00000300) +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000004C4 + (a)*0x00000300) +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a) (0x000004C8 + (a)*0x00000300) +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH 14:0 +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT 30:16 +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT 17:16 +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE (0x00000000) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257 (0x00000001) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025 (0x00000002) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT 21:20 +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x000004D4 + (a)*0x00000300) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT 13:12 +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE (0x00000000) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257 (0x00000001) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025 (0x00000002) +#define NV947D_HEAD_SET_PROCESSING(a) (0x000004E0 + (a)*0x00000300) +#define NV947D_HEAD_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV947D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV947D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CONVERSION_RED(a) (0x000004E4 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONVERSION_RED_GAIN 15:0 +#define NV947D_HEAD_SET_CONVERSION_RED_OFS 31:16 +#define NV947D_HEAD_SET_CONVERSION_GRN(a) (0x000004E8 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONVERSION_GRN_GAIN 15:0 +#define NV947D_HEAD_SET_CONVERSION_GRN_OFS 31:16 +#define NV947D_HEAD_SET_CONVERSION_BLU(a) (0x000004EC + (a)*0x00000300) +#define NV947D_HEAD_SET_CONVERSION_BLU_GAIN 15:0 +#define NV947D_HEAD_SET_CONVERSION_BLU_OFS 31:16 +#define NV947D_HEAD_SET_CSC_RED2RED(a) (0x000004F0 + (a)*0x00000300) +#define NV947D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE 31:31 +#define NV947D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CSC_RED2RED_COEFF 18:0 +#define NV947D_HEAD_SET_CSC_GRN2RED(a) (0x000004F4 + (a)*0x00000300) +#define NV947D_HEAD_SET_CSC_GRN2RED_COEFF 18:0 +#define NV947D_HEAD_SET_CSC_BLU2RED(a) (0x000004F8 + (a)*0x00000300) +#define NV947D_HEAD_SET_CSC_BLU2RED_COEFF 18:0 +#define NV947D_HEAD_SET_CSC_CONSTANT2RED(a) (0x000004FC + (a)*0x00000300) +#define NV947D_HEAD_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV947D_HEAD_SET_CSC_RED2GRN(a) (0x00000500 + (a)*0x00000300) +#define NV947D_HEAD_SET_CSC_RED2GRN_COEFF 18:0 +#define NV947D_HEAD_SET_CSC_GRN2GRN(a) (0x00000504 + (a)*0x00000300) +#define NV947D_HEAD_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV947D_HEAD_SET_CSC_BLU2GRN(a) (0x00000508 + (a)*0x00000300) +#define NV947D_HEAD_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV947D_HEAD_SET_CSC_CONSTANT2GRN(a) (0x0000050C + (a)*0x00000300) +#define NV947D_HEAD_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV947D_HEAD_SET_CSC_RED2BLU(a) (0x00000510 + (a)*0x00000300) +#define NV947D_HEAD_SET_CSC_RED2BLU_COEFF 18:0 +#define NV947D_HEAD_SET_CSC_GRN2BLU(a) (0x00000514 + (a)*0x00000300) +#define NV947D_HEAD_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV947D_HEAD_SET_CSC_BLU2BLU(a) (0x00000518 + (a)*0x00000300) +#define NV947D_HEAD_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV947D_HEAD_SET_CSC_CONSTANT2BLU(a) (0x0000051C + (a)*0x00000300) +#define NV947D_HEAD_SET_CSC_CONSTANT2BLU_COEFF 18:0 +#define NV947D_HEAD_SET_HDMI_CTRL(a) (0x00000520 + (a)*0x00000300) +#define NV947D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NV947D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NV947D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NV947D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NV947D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NV947D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE 15:12 +#define NV947D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000000) +#define NV947D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FIELD_ALTERNATIVE (0x00000001) +#define NV947D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_LINE_ALTERNATIVE (0x00000002) +#define NV947D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_FULL (0x00000003) +#define NV947D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH (0x00000004) +#define NV947D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH_GRAPHICS (0x00000005) +#define NV947D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_TOP_AND_BOTTOM (0x00000006) +#define NV947D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_HALF (0x00000008) +#define NV947D_HEAD_SET_VACTIVE_SPACE_COLOR(a) (0x00000524 + (a)*0x00000300) +#define NV947D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR 9:0 +#define NV947D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y 19:10 +#define NV947D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB 29:20 +#define NV947D_HEAD_SET_PIXEL_REORDER_CONTROL(a) (0x00000528 + (a)*0x00000300) +#define NV947D_HEAD_SET_PIXEL_REORDER_CONTROL_BANK_WIDTH 13:0 +#define NV947D_HEAD_SET_DISPLAY_ID(a,b) (0x0000052C + (a)*0x00000300 + (b)*0x00000004) +#define NV947D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NV947D_HEAD_SET_SW_SPARE_A(a) (0x0000054C + (a)*0x00000300) +#define NV947D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NV947D_HEAD_SET_SW_SPARE_B(a) (0x00000550 + (a)*0x00000300) +#define NV947D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NV947D_HEAD_SET_SW_SPARE_C(a) (0x00000554 + (a)*0x00000300) +#define NV947D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NV947D_HEAD_SET_SW_SPARE_D(a) (0x00000558 + (a)*0x00000300) +#define NV947D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NV947D_HEAD_SET_GET_BLANKING_CTRL(a) (0x0000055C + (a)*0x00000300) +#define NV947D_HEAD_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NV947D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NV947D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NV947D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NV947D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NV947D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CONTROL_COMPRESSION(a) (0x00000560 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_ENABLE 0:0 +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_CHUNK_BANDWIDTH 12:1 +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LAST_BANDWIDTH 24:13 +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA(a) (0x00000564 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY1 7:4 +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY2 11:8 +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY3 15:12 +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA_CHUNK_SIZE 23:16 +#define NV947D_HEAD_SET_STALL_LOCK(a) (0x00000568 + (a)*0x00000300) +#define NV947D_HEAD_SET_STALL_LOCK_ENABLE 0:0 +#define NV947D_HEAD_SET_STALL_LOCK_ENABLE_FALSE (0x00000000) +#define NV947D_HEAD_SET_STALL_LOCK_ENABLE_TRUE (0x00000001) +#define NV947D_HEAD_SET_STALL_LOCK_MODE 1:1 +#define NV947D_HEAD_SET_STALL_LOCK_MODE_CONTINUOUS (0x00000000) +#define NV947D_HEAD_SET_STALL_LOCK_MODE_ONE_SHOT (0x00000001) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN 6:2 +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV947D_HEAD_SET_STALL_LOCK_UNSTALL_MODE 7:7 +#define NV947D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_CRASH_LOCK (0x00000000) +#define NV947D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_LINE_LOCK (0x00000001) +#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a) (0x000006D0 + (a)*0x00000300) +#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED 31:0 +#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a) (0x000006D4 + (a)*0x00000300) +#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED 31:0 +#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a) (0x000006D8 + (a)*0x00000300) +#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED 31:0 +#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a) (0x000006DC + (a)*0x00000300) +#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED 31:0 +#define NV947D_HEAD_SET_SPARE(a) (0x000006EC + (a)*0x00000300) +#define NV947D_HEAD_SET_SPARE_UNUSED 31:0 +#define NV947D_HEAD_SET_SPARE_NOOP(a,b) (0x000006F0 + (a)*0x00000300 + (b)*0x00000004) +#define NV947D_HEAD_SET_SPARE_NOOP_UNUSED 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl947d_h diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl9570.h b/userspace/sdks/nv525/nvidia/inc/class/cl9570.h new file mode 100644 index 0000000..00e6d7f --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl9570.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9570.finn +// + +#define NV9570_DISPLAY (0x9570U) /* finn: Evaluated from "NV9570_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV9570_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9570U) + +typedef struct NV9570_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numDacs; // Number of DACs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NV9570_ALLOCATION_PARAMETERS; diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl9571.h b/userspace/sdks/nv525/nvidia/inc/class/cl9571.h new file mode 100644 index 0000000..be40b1f --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl9571.h @@ -0,0 +1,295 @@ +/* + * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl9571_h_ +#define _cl9571_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV9571_DISP_SF_USER 0x9571 + +typedef volatile struct _cl9571_tag0 { + NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x00690FFF:0x00690000 */ +} _Nv9571DispSfUser, Nv9571DispSfUserMap; + +#define NV9571_SF_HDMI_INFO_IDX_AVI_INFOFRAME 0x00000000 /* */ +#define NV9571_SF_HDMI_INFO_IDX_GENERIC_INFOFRAME 0x00000001 /* */ +#define NV9571_SF_HDMI_INFO_IDX_GCP 0x00000003 /* */ +#define NV9571_SF_HDMI_INFO_IDX_VSI 0x00000004 /* */ +#define NV9571_SF_HDMI_INFO_CTRL(i,j) (0x00690000-0x00690000+(i)*1024+(j)*64) /* RWX4A */ +#define NV9571_SF_HDMI_INFO_CTRL__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_INFO_CTRL__SIZE_2 5 /* */ +#define NV9571_SF_HDMI_INFO_CTRL_ENABLE 0:0 /* RWIVF */ +#define NV9571_SF_HDMI_INFO_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_INFO_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NV9571_SF_HDMI_INFO_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NV9571_SF_HDMI_INFO_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NV9571_SF_HDMI_INFO_CTRL_OTHER 4:4 /* RWIVF */ +#define NV9571_SF_HDMI_INFO_CTRL_OTHER_DIS 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_INFO_CTRL_OTHER_EN 0x00000001 /* RW--V */ +#define NV9571_SF_HDMI_INFO_CTRL_SINGLE 8:8 /* RWIVF */ +#define NV9571_SF_HDMI_INFO_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_INFO_CTRL_SINGLE_EN 0x00000001 /* RW--V */ +#define NV9571_SF_HDMI_INFO_CTRL_CHKSUM_HW 9:9 /* RWIVF */ +#define NV9571_SF_HDMI_INFO_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */ +#define NV9571_SF_HDMI_INFO_CTRL_CHKSUM_HW_EN 0x00000001 /* RW--V */ +#define NV9571_SF_HDMI_INFO_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */ +#define NV9571_SF_HDMI_INFO_CTRL_CHKSUM_HW_DIS 0x00000000 /* RW--V */ +#define NV9571_SF_HDMI_INFO_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */ +#define NV9571_SF_HDMI_INFO_CTRL_HBLANK 12:12 /* RWIVF */ +#define NV9571_SF_HDMI_INFO_CTRL_HBLANK_DIS 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_INFO_CTRL_HBLANK_EN 0x00000001 /* RW--V */ +#define NV9571_SF_HDMI_INFO_CTRL_VIDEO_FMT 16:16 /* RWIVF */ +#define NV9571_SF_HDMI_INFO_CTRL_VIDEO_FMT_SW_CONTROLLED 0x00000000 /* RW--V */ +#define NV9571_SF_HDMI_INFO_CTRL_VIDEO_FMT_HW_CONTROLLED 0x00000001 /* RW--V */ +#define NV9571_SF_HDMI_INFO_CTRL_VIDEO_FMT_INIT 0x00000001 /* RWI-V */ +#define NV9571_SF_HDMI_INFO_STATUS(i,j) (0x00690004-0x00690000+(i)*1024+(j)*64) /* R--4A */ +#define NV9571_SF_HDMI_INFO_STATUS__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_INFO_STATUS__SIZE_2 5 /* */ +#define NV9571_SF_HDMI_INFO_STATUS_SENT 0:0 /* R--VF */ +#define NV9571_SF_HDMI_INFO_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NV9571_SF_HDMI_INFO_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NV9571_SF_HDMI_INFO_STATUS_SENT_INIT 0x00000000 /* R-I-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x00690000-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x00690008-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x0069000C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x00690010-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x00690014-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x00690018-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_HEADER(i) (0x00690048-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_GENERIC_HEADER__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_GENERIC_HEADER_HB0 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_HEADER_HB1 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_HEADER_HB2 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW(i) (0x0069004C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_HIGH(i) (0x00690050-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW(i) (0x00690054-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_HIGH(i) (0x00690058-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW(i) (0x0069005C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_HIGH(i) (0x00690060-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_HIGH__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW(i) (0x00690064-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24 31:24 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_HIGH(i) (0x00690068-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_HIGH__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GCP_SUBPACK(i) (0x006900CC-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_GCP_SUBPACK__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_GCP_SUBPACK_SB0 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_GCP_SUBPACK_SB0_INIT 0x00000001 /* RWI-V */ +#define NV9571_SF_HDMI_GCP_SUBPACK_SB0_SET_AVMUTE 0x00000001 /* RW--V */ +#define NV9571_SF_HDMI_GCP_SUBPACK_SB0_CLR_AVMUTE 0x00000010 /* RW--V */ +#define NV9571_SF_HDMI_GCP_SUBPACK_SB1 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_GCP_SUBPACK_SB1_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GCP_SUBPACK_SB2 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_GCP_SUBPACK_SB2_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_HEADER(i) (0x00690108-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_VSI_HEADER__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_VSI_HEADER_HB0 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_HEADER_HB1 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_HEADER_HB2 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW(i) (0x0069010C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_HIGH(i) (0x00690110-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW(i) (0x00690114-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_HIGH(i) (0x00690118-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW(i) (0x0069011C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_HIGH(i) (0x00690120-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_HIGH__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW(i) (0x00690124-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW_PB21 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW_PB22 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW_PB23 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW_PB24 31:24 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_HIGH(i) (0x00690128-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_HIGH__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _cl9571_h_ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl957d.h b/userspace/sdks/nv525/nvidia/inc/class/cl957d.h new file mode 100644 index 0000000..ea10694 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl957d.h @@ -0,0 +1,1602 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl957d_h_ +#define _cl957d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV957D_CORE_CHANNEL_DMA (0x0000957D) + +#define NV957D_CORE_NOTIFIER_3 0x00000000 +#define NV957D_CORE_NOTIFIER_3_SIZEOF 0x00000150 +#define NV957D_CORE_NOTIFIER_3_COMPLETION_0 0x00000000 +#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_DONE 0:0 +#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_R0 15:1 +#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP 29:16 +#define NV957D_CORE_NOTIFIER_3__1 0x00000001 +#define NV957D_CORE_NOTIFIER_3__1_R1 31:0 +#define NV957D_CORE_NOTIFIER_3__2 0x00000002 +#define NV957D_CORE_NOTIFIER_3__2_R2 31:0 +#define NV957D_CORE_NOTIFIER_3__3 0x00000003 +#define NV957D_CORE_NOTIFIER_3__3_R3 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_R0 19:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA 20:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_R1 29:21 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE 30:30 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5 0x00000005 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE 3:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE 11:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE 15:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE 19:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE 27:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6 0x00000006 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE 3:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE 11:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE 15:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE 19:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE 27:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_7 0x00000007 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_7_R4 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_8 0x00000008 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_8_R5 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_9 0x00000009 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_9_R6 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_10 0x0000000A +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_10_R7 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_11 0x0000000B +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_11_R8 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12 0x0000000C +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0 31:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13 0x0000000D +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14 0x0000000E +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0 31:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15 0x0000000F +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16 0x00000010 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0 31:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17 0x00000011 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18 0x00000012 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0 31:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19 0x00000013 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A 8:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B 9:9 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1 10:10 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS 11:11 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2 13:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3 16:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4 19:17 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A 24:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B 25:25 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE 26:26 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21 0x00000015 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_CLK_MAX 23:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_LVDS_CLK_MAX 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22 0x00000016 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A 8:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B 9:9 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1 10:10 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS 11:11 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2 13:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3 16:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4 19:17 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A 24:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B 25:25 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE 26:26 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23 0x00000017 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_CLK_MAX 23:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_LVDS_CLK_MAX 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24 0x00000018 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A 8:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B 9:9 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1 10:10 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS 11:11 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2 13:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3 16:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4 19:17 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A 24:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B 25:25 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE 26:26 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25 0x00000019 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_CLK_MAX 23:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_LVDS_CLK_MAX 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26 0x0000001A +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A 8:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B 9:9 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1 10:10 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS 11:11 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2 13:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3 16:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4 19:17 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A 24:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B 25:25 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE 26:26 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27 0x0000001B +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_CLK_MAX 23:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_LVDS_CLK_MAX 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28 0x0000001C +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A 8:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B 9:9 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1 10:10 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS 11:11 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2 13:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3 16:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4 19:17 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A 24:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B 25:25 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE 26:26 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29 0x0000001D +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_CLK_MAX 23:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_LVDS_CLK_MAX 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30 0x0000001E +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A 8:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B 9:9 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1 10:10 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS 11:11 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2 13:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3 16:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4 19:17 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A 24:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B 25:25 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE 26:26 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31 0x0000001F +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_CLK_MAX 23:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_LVDS_CLK_MAX 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32 0x00000020 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A 8:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B 9:9 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1 10:10 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS 11:11 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2 13:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3 16:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4 19:17 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A 24:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B 25:25 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE 26:26 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33 0x00000021 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_CLK_MAX 23:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_LVDS_CLK_MAX 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34 0x00000022 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A 8:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B 9:9 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1 10:10 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS 11:11 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2 13:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3 16:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4 19:17 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A 24:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B 25:25 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE 26:26 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35 0x00000023 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_CLK_MAX 23:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_LVDS_CLK_MAX 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36 0x00000024 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0 31:7 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37 0x00000025 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38 0x00000026 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0 31:7 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39 0x00000027 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40 0x00000028 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0 31:7 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41 0x00000029 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42 0x0000002A +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0 31:7 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43 0x0000002B +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44 0x0000002C +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44_R0 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45 0x0000002D +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45_R1 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46 0x0000002E +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46_R0 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47 0x0000002F +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47_R1 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48 0x00000030 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48_R0 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49 0x00000031 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49_R1 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50 0x00000032 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50_R0 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51 0x00000033 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51_R1 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52 0x00000034 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0 31:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53 0x00000035 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54 0x00000036 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55 0x00000037 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56 0x00000038 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57 0x00000039 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58 0x0000003A +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59 0x0000003B +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60 0x0000003C +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0 31:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61 0x0000003D +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62 0x0000003E +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63 0x0000003F +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64 0x00000040 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65 0x00000041 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66 0x00000042 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67 0x00000043 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68 0x00000044 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0 31:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69 0x00000045 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70 0x00000046 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71 0x00000047 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72 0x00000048 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73 0x00000049 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74 0x0000004A +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75 0x0000004B +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76 0x0000004C +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0 31:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77 0x0000004D +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78 0x0000004E +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79 0x0000004F +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80 0x00000050 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81 0x00000051 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82 0x00000052 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83 0x00000053 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10 31:0 + + +// dma opcode instructions +#define NV957D_DMA 0x00000000 +#define NV957D_DMA_OPCODE 31:29 +#define NV957D_DMA_OPCODE_METHOD 0x00000000 +#define NV957D_DMA_OPCODE_JUMP 0x00000001 +#define NV957D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV957D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV957D_DMA_METHOD_COUNT 27:18 +#define NV957D_DMA_METHOD_OFFSET 11:2 +#define NV957D_DMA_DATA 31:0 +#define NV957D_DMA_DATA_NOP 0x00000000 +#define NV957D_DMA_JUMP_OFFSET 11:2 +#define NV957D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV957D_PUT (0x00000000) +#define NV957D_PUT_PTR 11:2 +#define NV957D_GET (0x00000004) +#define NV957D_GET_PTR 11:2 +#define NV957D_UPDATE (0x00000080) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR(i) (0 +(i)*4):(0 +(i)*4) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1 4 +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0 +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR1 4:4 +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR2 8:8 +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR3 12:12 +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE(i) (1 +(i)*4):(1 +(i)*4) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1 4 +#define NV957D_UPDATE_INTERLOCK_WITH_BASE_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE0 1:1 +#define NV957D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE1 5:5 +#define NV957D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE2 9:9 +#define NV957D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE3 13:13 +#define NV957D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY(i) (2 +(i)*4):(2 +(i)*4) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1 4 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY1 6:6 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY2 10:10 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY3 14:14 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i) (3 +(i)*4):(3 +(i)*4) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1 4 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 7:7 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2 11:11 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3 15:15 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE (0x00000001) +#define NV957D_UPDATE_SPECIAL_HANDLING 25:24 +#define NV957D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV957D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV957D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV957D_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV957D_UPDATE_NOT_DRIVER_FRIENDLY 31:31 +#define NV957D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000) +#define NV957D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001) +#define NV957D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30 +#define NV957D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000) +#define NV957D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001) +#define NV957D_UPDATE_INHIBIT_INTERRUPTS 29:29 +#define NV957D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NV957D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NV957D_SET_NOTIFIER_CONTROL (0x00000084) +#define NV957D_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV957D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV957D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV957D_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV957D_SET_NOTIFIER_CONTROL_NOTIFY 31:31 +#define NV957D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NV957D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NV957D_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV957D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV957D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV957D_SET_CONTEXT_DMA_NOTIFIER (0x00000088) +#define NV957D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV957D_GET_CAPABILITIES (0x0000008C) +#define NV957D_GET_CAPABILITIES_DUMMY 31:0 +#define NV957D_SET_SPARE (0x0000016C) +#define NV957D_SET_SPARE_UNUSED 31:0 +#define NV957D_SET_SPARE_NOOP(b) (0x00000170 + (b)*0x00000004) +#define NV957D_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV957D_DAC_SET_CONTROL(a) (0x00000180 + (a)*0x00000020) +#define NV957D_DAC_SET_CONTROL_OWNER_MASK 3:0 +#define NV957D_DAC_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV957D_DAC_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV957D_DAC_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV957D_DAC_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV957D_DAC_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV957D_DAC_SET_CONTROL_PROTOCOL 12:8 +#define NV957D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV957D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT (0x00000013) +#define NV957D_DAC_SET_SW_SPARE_A(a) (0x00000184 + (a)*0x00000020) +#define NV957D_DAC_SET_SW_SPARE_A_CODE 31:0 +#define NV957D_DAC_SET_SW_SPARE_B(a) (0x00000188 + (a)*0x00000020) +#define NV957D_DAC_SET_SW_SPARE_B_CODE 31:0 +#define NV957D_DAC_SET_CUSTOM_REASON(a) (0x00000190 + (a)*0x00000020) +#define NV957D_DAC_SET_CUSTOM_REASON_CODE 31:0 + +#define NV957D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020) +#define NV957D_SOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV957D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV957D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV957D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV957D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV957D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV957D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV957D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV957D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV957D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV957D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV957D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NV957D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NV957D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV957D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV957D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV957D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV957D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NV957D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NV957D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NV957D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NV957D_SOR_SET_SW_SPARE_A(a) (0x00000204 + (a)*0x00000020) +#define NV957D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NV957D_SOR_SET_SW_SPARE_B(a) (0x00000208 + (a)*0x00000020) +#define NV957D_SOR_SET_SW_SPARE_B_CODE 31:0 +#define NV957D_SOR_SET_CUSTOM_REASON(a) (0x00000210 + (a)*0x00000020) +#define NV957D_SOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV957D_PIOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NV957D_PIOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV957D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV957D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV957D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV957D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV957D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV957D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV957D_PIOR_SET_SW_SPARE_A(a) (0x00000304 + (a)*0x00000020) +#define NV957D_PIOR_SET_SW_SPARE_A_CODE 31:0 +#define NV957D_PIOR_SET_SW_SPARE_B(a) (0x00000308 + (a)*0x00000020) +#define NV957D_PIOR_SET_SW_SPARE_B_CODE 31:0 +#define NV957D_PIOR_SET_CUSTOM_REASON(a) (0x00000310 + (a)*0x00000020) +#define NV957D_PIOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV957D_HEAD_SET_PRESENT_CONTROL(a) (0x00000400 + (a)*0x00000300) +#define NV957D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NV957D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 8:8 +#define NV957D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NV957D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NV957D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00000404 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 3:3 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 4:4 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 9:6 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000009) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 12:12 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 20:13 +#define NV957D_HEAD_SET_CONTROL(a) (0x00000408 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTROL_STRUCTURE 0:0 +#define NV957D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 3:2 +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 19:15 +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 7:4 +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 9:8 +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 14:10 +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK 1:1 +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_DISABLE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN 24:20 +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN 29:25 +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000000) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000001) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000002) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000003) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000004) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000005) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000006) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000007) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000008) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x00000009) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000A) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000B) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000C) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000D) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000E) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x0000000F) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_UNSPECIFIED (0x00000010) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV957D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NV957D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NV957D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000410 + (a)*0x00000300) +#define NV957D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV957D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV957D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV957D_HEAD_SET_RASTER_SIZE(a) (0x00000414 + (a)*0x00000300) +#define NV957D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV957D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV957D_HEAD_SET_RASTER_SYNC_END(a) (0x00000418 + (a)*0x00000300) +#define NV957D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV957D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV957D_HEAD_SET_RASTER_BLANK_END(a) (0x0000041C + (a)*0x00000300) +#define NV957D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV957D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV957D_HEAD_SET_RASTER_BLANK_START(a) (0x00000420 + (a)*0x00000300) +#define NV957D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV957D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV957D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000424 + (a)*0x00000300) +#define NV957D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV957D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV957D_HEAD_SET_LOCK_CHAIN(a) (0x00000428 + (a)*0x00000300) +#define NV957D_HEAD_SET_LOCK_CHAIN_POSITION 27:24 +#define NV957D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000042C + (a)*0x00000300) +#define NV957D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV957D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV957D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV957D_HEAD_SET_CRC_CONTROL(a) (0x00000430 + (a)*0x00000300) +#define NV957D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 1:0 +#define NV957D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000000) +#define NV957D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_BASE (0x00000001) +#define NV957D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_OVERLAY (0x00000002) +#define NV957D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 2:2 +#define NV957D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NV957D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NV957D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE 3:3 +#define NV957D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_FALSE (0x00000000) +#define NV957D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_TRUE (0x00000001) +#define NV957D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE 4:4 +#define NV957D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_FALSE (0x00000000) +#define NV957D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_TRUE (0x00000001) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT 19:8 +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC__SIZE_1 4 +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC0 (0x00000FF0) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC1 (0x00000FF1) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC2 (0x00000FF2) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC3 (0x00000FF3) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG__SIZE_1 4 +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG0 (0x00000FF8) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG1 (0x00000FF9) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG2 (0x00000FFA) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG3 (0x00000FFB) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR__SIZE_1 8 +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR0 (0x00000F0F) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR1 (0x00000F1F) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR2 (0x00000F2F) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR3 (0x00000F3F) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR4 (0x00000F4F) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR5 (0x00000F5F) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR6 (0x00000F6F) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR7 (0x00000F7F) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF__SIZE_1 4 +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF0 (0x00000F8F) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF1 (0x00000F9F) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF2 (0x00000FAF) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF3 (0x00000FBF) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR__SIZE_1 8 +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR0 (0x000000FF) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR1 (0x000001FF) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR2 (0x000002FF) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR3 (0x000003FF) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR4 (0x000004FF) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR5 (0x000005FF) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR6 (0x000006FF) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR7 (0x000007FF) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_NONE (0x00000FFF) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT 31:20 +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC__SIZE_1 4 +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC0 (0x00000FF0) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC1 (0x00000FF1) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC2 (0x00000FF2) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC3 (0x00000FF3) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG__SIZE_1 4 +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG0 (0x00000FF8) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG1 (0x00000FF9) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG2 (0x00000FFA) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG3 (0x00000FFB) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR__SIZE_1 8 +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR0 (0x00000F0F) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR1 (0x00000F1F) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR2 (0x00000F2F) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR3 (0x00000F3F) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR4 (0x00000F4F) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR5 (0x00000F5F) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR6 (0x00000F6F) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR7 (0x00000F7F) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF__SIZE_1 4 +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF0 (0x00000F8F) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF1 (0x00000F9F) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF2 (0x00000FAF) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF3 (0x00000FBF) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR__SIZE_1 8 +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR0 (0x000000FF) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR1 (0x000001FF) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR2 (0x000002FF) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR3 (0x000003FF) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR4 (0x000004FF) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR5 (0x000005FF) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR6 (0x000006FF) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR7 (0x000007FF) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_NONE (0x00000FFF) +#define NV957D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 5:5 +#define NV957D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC 6:6 +#define NV957D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_DISABLE (0x00000000) +#define NV957D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00000438 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NV957D_HEAD_SET_BASE_LUT_LO(a) (0x00000440 + (a)*0x00000300) +#define NV957D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV957D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE 27:24 +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV957D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV957D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_BASE_LUT_HI(a) (0x00000444 + (a)*0x00000300) +#define NV957D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV957D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000448 + (a)*0x00000300) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000044C + (a)*0x00000300) +#define NV957D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x00000450 + (a)*0x00000300) +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x00000454 + (a)*0x00000300) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE 21:20 +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25 (0x00000000) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28 (0x00000001) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM (0x00000002) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 24:24 +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING 25:25 +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE (0x00000000) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE (0x00000001) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 26:26 +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00000458 + (a)*0x00000300) +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NV957D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000045C + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV957D_HEAD_SET_OFFSET(a) (0x00000460 + (a)*0x00000300) +#define NV957D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV957D_HEAD_SET_SIZE(a) (0x00000468 + (a)*0x00000300) +#define NV957D_HEAD_SET_SIZE_WIDTH 15:0 +#define NV957D_HEAD_SET_SIZE_HEIGHT 31:16 +#define NV957D_HEAD_SET_STORAGE(a) (0x0000046C + (a)*0x00000300) +#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV957D_HEAD_SET_STORAGE_PITCH 20:8 +#define NV957D_HEAD_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV957D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV957D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV957D_HEAD_SET_PARAMS(a) (0x00000470 + (a)*0x00000300) +#define NV957D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV957D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV957D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV957D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV957D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV957D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV957D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV957D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV957D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024) +#define NV957D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV957D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV957D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV957D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV957D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV957D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV957D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV957D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV957D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV957D_HEAD_SET_PARAMS_GAMMA 2:2 +#define NV957D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV957D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV957D_HEAD_SET_CONTEXT_DMAS_ISO(a) (0x00000474 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV957D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x0000047C + (a)*0x00000300) +#define NV957D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 1:0 +#define NV957D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NV957D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NV957D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_SPEC_FLIP (0x00000002) +#define NV957D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV957D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV957D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV957D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE 27:26 +#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NV957D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 15:8 +#define NV957D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 23:16 +#define NV957D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV957D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV957D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV957D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV957D_HEAD_SET_OFFSETS_CURSOR(a,b) (0x00000484 + (a)*0x00000300 + (b)*0x00000004) +#define NV957D_HEAD_SET_OFFSETS_CURSOR_ORIGIN 31:0 +#define NV957D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b) (0x0000048C + (a)*0x00000300 + (b)*0x00000004) +#define NV957D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE 31:0 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00000494 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422 8:8 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE (0x00000001) +#define NV957D_HEAD_SET_PROCAMP(a) (0x00000498 + (a)*0x00000300) +#define NV957D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV957D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV957D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV957D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV957D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV957D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV957D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV957D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV957D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV957D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 5:5 +#define NV957D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NV957D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NV957D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 6:6 +#define NV957D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) +#define NV957D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) +#define NV957D_HEAD_SET_DITHER_CONTROL(a) (0x000004A0 + (a)*0x00000300) +#define NV957D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV957D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV957D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV957D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV957D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002) +#define NV957D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NV957D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV957D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x000004B0 + (a)*0x00000300) +#define NV957D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV957D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV957D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000004B8 + (a)*0x00000300) +#define NV957D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV957D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV957D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x000004BC + (a)*0x00000300) +#define NV957D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NV957D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000004C0 + (a)*0x00000300) +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000004C4 + (a)*0x00000300) +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a) (0x000004C8 + (a)*0x00000300) +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH 14:0 +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT 30:16 +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT 17:16 +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE (0x00000000) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257 (0x00000001) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025 (0x00000002) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT 21:20 +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x000004D4 + (a)*0x00000300) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT 13:12 +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE (0x00000000) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257 (0x00000001) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025 (0x00000002) +#define NV957D_HEAD_SET_PROCESSING(a) (0x000004E0 + (a)*0x00000300) +#define NV957D_HEAD_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV957D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV957D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CONVERSION_RED(a) (0x000004E4 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONVERSION_RED_GAIN 15:0 +#define NV957D_HEAD_SET_CONVERSION_RED_OFS 31:16 +#define NV957D_HEAD_SET_CONVERSION_GRN(a) (0x000004E8 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONVERSION_GRN_GAIN 15:0 +#define NV957D_HEAD_SET_CONVERSION_GRN_OFS 31:16 +#define NV957D_HEAD_SET_CONVERSION_BLU(a) (0x000004EC + (a)*0x00000300) +#define NV957D_HEAD_SET_CONVERSION_BLU_GAIN 15:0 +#define NV957D_HEAD_SET_CONVERSION_BLU_OFS 31:16 +#define NV957D_HEAD_SET_CSC_RED2RED(a) (0x000004F0 + (a)*0x00000300) +#define NV957D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE 31:31 +#define NV957D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CSC_RED2RED_COEFF 18:0 +#define NV957D_HEAD_SET_CSC_GRN2RED(a) (0x000004F4 + (a)*0x00000300) +#define NV957D_HEAD_SET_CSC_GRN2RED_COEFF 18:0 +#define NV957D_HEAD_SET_CSC_BLU2RED(a) (0x000004F8 + (a)*0x00000300) +#define NV957D_HEAD_SET_CSC_BLU2RED_COEFF 18:0 +#define NV957D_HEAD_SET_CSC_CONSTANT2RED(a) (0x000004FC + (a)*0x00000300) +#define NV957D_HEAD_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV957D_HEAD_SET_CSC_RED2GRN(a) (0x00000500 + (a)*0x00000300) +#define NV957D_HEAD_SET_CSC_RED2GRN_COEFF 18:0 +#define NV957D_HEAD_SET_CSC_GRN2GRN(a) (0x00000504 + (a)*0x00000300) +#define NV957D_HEAD_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV957D_HEAD_SET_CSC_BLU2GRN(a) (0x00000508 + (a)*0x00000300) +#define NV957D_HEAD_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV957D_HEAD_SET_CSC_CONSTANT2GRN(a) (0x0000050C + (a)*0x00000300) +#define NV957D_HEAD_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV957D_HEAD_SET_CSC_RED2BLU(a) (0x00000510 + (a)*0x00000300) +#define NV957D_HEAD_SET_CSC_RED2BLU_COEFF 18:0 +#define NV957D_HEAD_SET_CSC_GRN2BLU(a) (0x00000514 + (a)*0x00000300) +#define NV957D_HEAD_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV957D_HEAD_SET_CSC_BLU2BLU(a) (0x00000518 + (a)*0x00000300) +#define NV957D_HEAD_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV957D_HEAD_SET_CSC_CONSTANT2BLU(a) (0x0000051C + (a)*0x00000300) +#define NV957D_HEAD_SET_CSC_CONSTANT2BLU_COEFF 18:0 +#define NV957D_HEAD_SET_HDMI_CTRL(a) (0x00000520 + (a)*0x00000300) +#define NV957D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NV957D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NV957D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NV957D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NV957D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NV957D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE 15:12 +#define NV957D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000000) +#define NV957D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FIELD_ALTERNATIVE (0x00000001) +#define NV957D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_LINE_ALTERNATIVE (0x00000002) +#define NV957D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_FULL (0x00000003) +#define NV957D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH (0x00000004) +#define NV957D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH_GRAPHICS (0x00000005) +#define NV957D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_TOP_AND_BOTTOM (0x00000006) +#define NV957D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_HALF (0x00000008) +#define NV957D_HEAD_SET_VACTIVE_SPACE_COLOR(a) (0x00000524 + (a)*0x00000300) +#define NV957D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR 9:0 +#define NV957D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y 19:10 +#define NV957D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB 29:20 +#define NV957D_HEAD_SET_PIXEL_REORDER_CONTROL(a) (0x00000528 + (a)*0x00000300) +#define NV957D_HEAD_SET_PIXEL_REORDER_CONTROL_BANK_WIDTH 13:0 +#define NV957D_HEAD_SET_DISPLAY_ID(a,b) (0x0000052C + (a)*0x00000300 + (b)*0x00000004) +#define NV957D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NV957D_HEAD_SET_SW_SPARE_A(a) (0x0000054C + (a)*0x00000300) +#define NV957D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NV957D_HEAD_SET_SW_SPARE_B(a) (0x00000550 + (a)*0x00000300) +#define NV957D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NV957D_HEAD_SET_SW_SPARE_C(a) (0x00000554 + (a)*0x00000300) +#define NV957D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NV957D_HEAD_SET_SW_SPARE_D(a) (0x00000558 + (a)*0x00000300) +#define NV957D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NV957D_HEAD_SET_GET_BLANKING_CTRL(a) (0x0000055C + (a)*0x00000300) +#define NV957D_HEAD_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NV957D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NV957D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NV957D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NV957D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NV957D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CONTROL_COMPRESSION(a) (0x00000560 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_ENABLE 0:0 +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_CHUNK_BANDWIDTH 12:1 +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LAST_BANDWIDTH 24:13 +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA(a) (0x00000564 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY1 7:4 +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY2 11:8 +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY3 15:12 +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA_CHUNK_SIZE 23:16 +#define NV957D_HEAD_SET_STALL_LOCK(a) (0x00000568 + (a)*0x00000300) +#define NV957D_HEAD_SET_STALL_LOCK_ENABLE 0:0 +#define NV957D_HEAD_SET_STALL_LOCK_ENABLE_FALSE (0x00000000) +#define NV957D_HEAD_SET_STALL_LOCK_ENABLE_TRUE (0x00000001) +#define NV957D_HEAD_SET_STALL_LOCK_MODE 1:1 +#define NV957D_HEAD_SET_STALL_LOCK_MODE_CONTINUOUS (0x00000000) +#define NV957D_HEAD_SET_STALL_LOCK_MODE_ONE_SHOT (0x00000001) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN 6:2 +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV957D_HEAD_SET_STALL_LOCK_UNSTALL_MODE 7:7 +#define NV957D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_CRASH_LOCK (0x00000000) +#define NV957D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_LINE_LOCK (0x00000001) +#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a) (0x000006D0 + (a)*0x00000300) +#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED 31:0 +#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a) (0x000006D4 + (a)*0x00000300) +#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED 31:0 +#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a) (0x000006D8 + (a)*0x00000300) +#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED 31:0 +#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a) (0x000006DC + (a)*0x00000300) +#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED 31:0 +#define NV957D_HEAD_SET_SPARE(a) (0x000006EC + (a)*0x00000300) +#define NV957D_HEAD_SET_SPARE_UNUSED 31:0 +#define NV957D_HEAD_SET_SPARE_NOOP(a,b) (0x000006F0 + (a)*0x00000300 + (b)*0x00000004) +#define NV957D_HEAD_SET_SPARE_NOOP_UNUSED 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl957d_h diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl9770.h b/userspace/sdks/nv525/nvidia/inc/class/cl9770.h new file mode 100644 index 0000000..914838f --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl9770.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9770.finn +// + +#define NV9770_DISPLAY (0x9770U) /* finn: Evaluated from "NV9770_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV9770_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9770U) + +typedef struct NV9770_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numDacs; // Number of DACs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NV9770_ALLOCATION_PARAMETERS; diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl977d.h b/userspace/sdks/nv525/nvidia/inc/class/cl977d.h new file mode 100644 index 0000000..adf59a2 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl977d.h @@ -0,0 +1,1587 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl977d_h_ +#define _cl977d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV977D_CORE_CHANNEL_DMA (0x0000977D) + +#define NV977D_CORE_NOTIFIER_3 0x00000000 +#define NV977D_CORE_NOTIFIER_3_SIZEOF 0x00000150 +#define NV977D_CORE_NOTIFIER_3_COMPLETION_0 0x00000000 +#define NV977D_CORE_NOTIFIER_3_COMPLETION_0_DONE 0:0 +#define NV977D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_COMPLETION_0_R0 15:1 +#define NV977D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP 29:16 +#define NV977D_CORE_NOTIFIER_3__1 0x00000001 +#define NV977D_CORE_NOTIFIER_3__1_R1 31:0 +#define NV977D_CORE_NOTIFIER_3__2 0x00000002 +#define NV977D_CORE_NOTIFIER_3__2_R2 31:0 +#define NV977D_CORE_NOTIFIER_3__3 0x00000003 +#define NV977D_CORE_NOTIFIER_3__3_R3 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO 2:2 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_R0 19:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA 20:20 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_R1 29:21 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE 30:30 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5 0x00000005 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE 3:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE 7:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE 11:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE 15:12 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE 19:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE 23:20 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE 27:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE 31:28 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6 0x00000006 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE 3:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE 7:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE 11:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE 15:12 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE 19:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE 23:20 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE 27:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE 31:28 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_7 0x00000007 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_7_R4 31:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_8 0x00000008 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_8_R5 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_9 0x00000009 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_9_R6 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_10 0x0000000A +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_10_R7 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_11 0x0000000B +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_11_R8 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12 0x0000000C +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE 3:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0 31:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13 0x0000000D +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1 31:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14 0x0000000E +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE 3:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0 31:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15 0x0000000F +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1 31:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16 0x00000010 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE 3:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0 31:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17 0x00000011 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1 31:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18 0x00000012 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE 3:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0 31:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19 0x00000013 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1 31:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18 2:2 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24 3:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0 7:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A 8:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B 9:9 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1 10:10 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS 11:11 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2 13:12 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3 16:14 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4 19:17 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5 23:20 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A 24:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B 25:25 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE 26:26 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6 31:28 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21 0x00000015 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7 15:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_CLK_MAX 23:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_LVDS_CLK_MAX 31:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22 0x00000016 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18 2:2 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24 3:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0 7:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A 8:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B 9:9 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1 10:10 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS 11:11 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2 13:12 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3 16:14 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4 19:17 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5 23:20 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A 24:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B 25:25 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE 26:26 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6 31:28 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23 0x00000017 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7 15:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_CLK_MAX 23:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_LVDS_CLK_MAX 31:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24 0x00000018 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18 2:2 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24 3:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0 7:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A 8:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B 9:9 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1 10:10 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS 11:11 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2 13:12 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3 16:14 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4 19:17 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5 23:20 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A 24:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B 25:25 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE 26:26 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6 31:28 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25 0x00000019 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7 15:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_CLK_MAX 23:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_LVDS_CLK_MAX 31:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26 0x0000001A +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18 2:2 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24 3:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0 7:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A 8:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B 9:9 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1 10:10 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS 11:11 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2 13:12 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3 16:14 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4 19:17 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5 23:20 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A 24:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B 25:25 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE 26:26 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6 31:28 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27 0x0000001B +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7 15:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_CLK_MAX 23:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_LVDS_CLK_MAX 31:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28 0x0000001C +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18 2:2 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24 3:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0 7:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A 8:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B 9:9 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1 10:10 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS 11:11 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2 13:12 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3 16:14 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4 19:17 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5 23:20 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A 24:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B 25:25 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE 26:26 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6 31:28 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29 0x0000001D +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7 15:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_CLK_MAX 23:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_LVDS_CLK_MAX 31:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30 0x0000001E +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18 2:2 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24 3:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0 7:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A 8:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B 9:9 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1 10:10 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS 11:11 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2 13:12 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3 16:14 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4 19:17 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5 23:20 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A 24:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B 25:25 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE 26:26 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6 31:28 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31 0x0000001F +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7 15:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_CLK_MAX 23:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_LVDS_CLK_MAX 31:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32 0x00000020 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18 2:2 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24 3:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0 7:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A 8:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B 9:9 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1 10:10 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS 11:11 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2 13:12 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3 16:14 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4 19:17 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5 23:20 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A 24:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B 25:25 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE 26:26 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6 31:28 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33 0x00000021 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7 15:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_CLK_MAX 23:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_LVDS_CLK_MAX 31:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34 0x00000022 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18 2:2 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24 3:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0 7:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A 8:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B 9:9 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1 10:10 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS 11:11 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2 13:12 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3 16:14 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4 19:17 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5 23:20 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A 24:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B 25:25 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE 26:26 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6 31:28 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35 0x00000023 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7 15:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_CLK_MAX 23:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_LVDS_CLK_MAX 31:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36 0x00000024 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0 31:7 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37 0x00000025 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1 15:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2 31:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38 0x00000026 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0 31:7 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39 0x00000027 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1 15:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2 31:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40 0x00000028 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0 31:7 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41 0x00000029 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1 15:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2 31:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42 0x0000002A +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0 31:7 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43 0x0000002B +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1 15:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2 31:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52 0x00000034 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0 31:14 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53 0x00000035 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444 14:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1 15:15 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422 30:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54 0x00000036 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444 14:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3 15:15 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422 30:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55 0x00000037 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444 14:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5 15:15 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422 30:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56 0x00000038 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7 31:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57 0x00000039 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58 0x0000003A +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59 0x0000003B +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60 0x0000003C +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0 31:14 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61 0x0000003D +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444 14:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1 15:15 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422 30:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62 0x0000003E +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444 14:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3 15:15 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422 30:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63 0x0000003F +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444 14:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5 15:15 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422 30:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64 0x00000040 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7 31:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65 0x00000041 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66 0x00000042 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67 0x00000043 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68 0x00000044 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0 31:14 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69 0x00000045 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444 14:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1 15:15 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422 30:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70 0x00000046 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444 14:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3 15:15 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422 30:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71 0x00000047 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444 14:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5 15:15 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422 30:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72 0x00000048 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7 31:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73 0x00000049 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74 0x0000004A +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75 0x0000004B +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76 0x0000004C +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0 31:14 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77 0x0000004D +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444 14:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1 15:15 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422 30:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78 0x0000004E +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444 14:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3 15:15 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422 30:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79 0x0000004F +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444 14:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5 15:15 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422 30:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80 0x00000050 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7 31:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81 0x00000051 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82 0x00000052 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83 0x00000053 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10 31:0 + + +// dma opcode instructions +#define NV977D_DMA 0x00000000 +#define NV977D_DMA_OPCODE 31:29 +#define NV977D_DMA_OPCODE_METHOD 0x00000000 +#define NV977D_DMA_OPCODE_JUMP 0x00000001 +#define NV977D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV977D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV977D_DMA_METHOD_COUNT 27:18 +#define NV977D_DMA_METHOD_OFFSET 11:2 +#define NV977D_DMA_DATA 31:0 +#define NV977D_DMA_DATA_NOP 0x00000000 +#define NV977D_DMA_JUMP_OFFSET 11:2 +#define NV977D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV977D_PUT (0x00000000) +#define NV977D_PUT_PTR 11:2 +#define NV977D_GET (0x00000004) +#define NV977D_GET_PTR 11:2 +#define NV977D_UPDATE (0x00000080) +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR(i) (0 +(i)*4):(0 +(i)*4) +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1 4 +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0 +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR1 4:4 +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR2 8:8 +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR3 12:12 +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_BASE(i) (1 +(i)*4):(1 +(i)*4) +#define NV977D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1 4 +#define NV977D_UPDATE_INTERLOCK_WITH_BASE_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_BASE_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_BASE0 1:1 +#define NV977D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_BASE1 5:5 +#define NV977D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_BASE2 9:9 +#define NV977D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_BASE3 13:13 +#define NV977D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY(i) (2 +(i)*4):(2 +(i)*4) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1 4 +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2 +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY1 6:6 +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY2 10:10 +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY3 14:14 +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i) (3 +(i)*4):(3 +(i)*4) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1 4 +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3 +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 7:7 +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2 11:11 +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3 15:15 +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE (0x00000001) +#define NV977D_UPDATE_SPECIAL_HANDLING 25:24 +#define NV977D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV977D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV977D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV977D_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV977D_UPDATE_NOT_DRIVER_FRIENDLY 31:31 +#define NV977D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000) +#define NV977D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001) +#define NV977D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30 +#define NV977D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000) +#define NV977D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001) +#define NV977D_UPDATE_INHIBIT_INTERRUPTS 29:29 +#define NV977D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NV977D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NV977D_SET_NOTIFIER_CONTROL (0x00000084) +#define NV977D_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV977D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV977D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV977D_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV977D_SET_NOTIFIER_CONTROL_NOTIFY 31:31 +#define NV977D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NV977D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NV977D_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV977D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV977D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV977D_SET_CONTEXT_DMA_NOTIFIER (0x00000088) +#define NV977D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV977D_GET_CAPABILITIES (0x0000008C) +#define NV977D_GET_CAPABILITIES_DUMMY 31:0 +#define NV977D_SET_SPARE (0x0000016C) +#define NV977D_SET_SPARE_UNUSED 31:0 +#define NV977D_SET_SPARE_NOOP(b) (0x00000170 + (b)*0x00000004) +#define NV977D_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV977D_DAC_SET_CONTROL(a) (0x00000180 + (a)*0x00000020) +#define NV977D_DAC_SET_CONTROL_OWNER_MASK 3:0 +#define NV977D_DAC_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV977D_DAC_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV977D_DAC_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV977D_DAC_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV977D_DAC_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV977D_DAC_SET_CONTROL_PROTOCOL 12:8 +#define NV977D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV977D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT (0x00000013) +#define NV977D_DAC_SET_SW_SPARE_A(a) (0x00000184 + (a)*0x00000020) +#define NV977D_DAC_SET_SW_SPARE_A_CODE 31:0 +#define NV977D_DAC_SET_SW_SPARE_B(a) (0x00000188 + (a)*0x00000020) +#define NV977D_DAC_SET_SW_SPARE_B_CODE 31:0 +#define NV977D_DAC_SET_CUSTOM_REASON(a) (0x00000190 + (a)*0x00000020) +#define NV977D_DAC_SET_CUSTOM_REASON_CODE 31:0 + +#define NV977D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020) +#define NV977D_SOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV977D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV977D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV977D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV977D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV977D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV977D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV977D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV977D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV977D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV977D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV977D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NV977D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NV977D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV977D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV977D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV977D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV977D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NV977D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NV977D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NV977D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NV977D_SOR_SET_SW_SPARE_A(a) (0x00000204 + (a)*0x00000020) +#define NV977D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NV977D_SOR_SET_SW_SPARE_B(a) (0x00000208 + (a)*0x00000020) +#define NV977D_SOR_SET_SW_SPARE_B_CODE 31:0 +#define NV977D_SOR_SET_CUSTOM_REASON(a) (0x00000210 + (a)*0x00000020) +#define NV977D_SOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV977D_PIOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NV977D_PIOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV977D_PIOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV977D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV977D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV977D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV977D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV977D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV977D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV977D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV977D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV977D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV977D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV977D_PIOR_SET_SW_SPARE_A(a) (0x00000304 + (a)*0x00000020) +#define NV977D_PIOR_SET_SW_SPARE_A_CODE 31:0 +#define NV977D_PIOR_SET_SW_SPARE_B(a) (0x00000308 + (a)*0x00000020) +#define NV977D_PIOR_SET_SW_SPARE_B_CODE 31:0 +#define NV977D_PIOR_SET_CUSTOM_REASON(a) (0x00000310 + (a)*0x00000020) +#define NV977D_PIOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV977D_HEAD_SET_PRESENT_CONTROL(a) (0x00000400 + (a)*0x00000300) +#define NV977D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NV977D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 8:8 +#define NV977D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NV977D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NV977D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00000404 + (a)*0x00000300) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 3:3 +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 4:4 +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 9:6 +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000009) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 12:12 +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 24:13 +#define NV977D_HEAD_SET_CONTROL(a) (0x00000408 + (a)*0x00000300) +#define NV977D_HEAD_SET_CONTROL_STRUCTURE 0:0 +#define NV977D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV977D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 3:2 +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 19:15 +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 7:4 +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 9:8 +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 14:10 +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK 1:1 +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_DISABLE (0x00000000) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_ENABLE (0x00000001) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN 24:20 +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN 29:25 +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000000) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000001) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000002) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000003) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000004) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000005) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000006) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000007) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000008) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x00000009) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000A) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000B) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000C) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000D) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000E) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x0000000F) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_UNSPECIFIED (0x00000010) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV977D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NV977D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV977D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV977D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NV977D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV977D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV977D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000410 + (a)*0x00000300) +#define NV977D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV977D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV977D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV977D_HEAD_SET_RASTER_SIZE(a) (0x00000414 + (a)*0x00000300) +#define NV977D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV977D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV977D_HEAD_SET_RASTER_SYNC_END(a) (0x00000418 + (a)*0x00000300) +#define NV977D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV977D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV977D_HEAD_SET_RASTER_BLANK_END(a) (0x0000041C + (a)*0x00000300) +#define NV977D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV977D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV977D_HEAD_SET_RASTER_BLANK_START(a) (0x00000420 + (a)*0x00000300) +#define NV977D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV977D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV977D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000424 + (a)*0x00000300) +#define NV977D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV977D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV977D_HEAD_SET_LOCK_CHAIN(a) (0x00000428 + (a)*0x00000300) +#define NV977D_HEAD_SET_LOCK_CHAIN_POSITION 27:24 +#define NV977D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000042C + (a)*0x00000300) +#define NV977D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV977D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV977D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV977D_HEAD_SET_CRC_CONTROL(a) (0x00000430 + (a)*0x00000300) +#define NV977D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 1:0 +#define NV977D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000000) +#define NV977D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_BASE (0x00000001) +#define NV977D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_OVERLAY (0x00000002) +#define NV977D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 2:2 +#define NV977D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NV977D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NV977D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE 3:3 +#define NV977D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_FALSE (0x00000000) +#define NV977D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_TRUE (0x00000001) +#define NV977D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE 4:4 +#define NV977D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_FALSE (0x00000000) +#define NV977D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_TRUE (0x00000001) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT 19:8 +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC__SIZE_1 4 +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC0 (0x00000FF0) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC1 (0x00000FF1) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC2 (0x00000FF2) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC3 (0x00000FF3) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG__SIZE_1 4 +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG0 (0x00000FF8) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG1 (0x00000FF9) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG2 (0x00000FFA) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG3 (0x00000FFB) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR__SIZE_1 8 +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR0 (0x00000F0F) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR1 (0x00000F1F) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR2 (0x00000F2F) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR3 (0x00000F3F) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR4 (0x00000F4F) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR5 (0x00000F5F) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR6 (0x00000F6F) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR7 (0x00000F7F) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF__SIZE_1 4 +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF0 (0x00000F8F) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF1 (0x00000F9F) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF2 (0x00000FAF) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF3 (0x00000FBF) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR__SIZE_1 8 +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR0 (0x000000FF) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR1 (0x000001FF) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR2 (0x000002FF) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR3 (0x000003FF) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR4 (0x000004FF) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR5 (0x000005FF) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR6 (0x000006FF) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR7 (0x000007FF) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_NONE (0x00000FFF) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT 31:20 +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC__SIZE_1 4 +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC0 (0x00000FF0) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC1 (0x00000FF1) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC2 (0x00000FF2) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC3 (0x00000FF3) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG__SIZE_1 4 +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG0 (0x00000FF8) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG1 (0x00000FF9) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG2 (0x00000FFA) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG3 (0x00000FFB) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR__SIZE_1 8 +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR0 (0x00000F0F) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR1 (0x00000F1F) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR2 (0x00000F2F) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR3 (0x00000F3F) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR4 (0x00000F4F) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR5 (0x00000F5F) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR6 (0x00000F6F) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR7 (0x00000F7F) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF__SIZE_1 4 +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF0 (0x00000F8F) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF1 (0x00000F9F) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF2 (0x00000FAF) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF3 (0x00000FBF) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR__SIZE_1 8 +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR0 (0x000000FF) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR1 (0x000001FF) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR2 (0x000002FF) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR3 (0x000003FF) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR4 (0x000004FF) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR5 (0x000005FF) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR6 (0x000006FF) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR7 (0x000007FF) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_NONE (0x00000FFF) +#define NV977D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 5:5 +#define NV977D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NV977D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NV977D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC 6:6 +#define NV977D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_DISABLE (0x00000000) +#define NV977D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_ENABLE (0x00000001) +#define NV977D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00000438 + (a)*0x00000300) +#define NV977D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NV977D_HEAD_SET_BASE_LUT_LO(a) (0x00000440 + (a)*0x00000300) +#define NV977D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV977D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV977D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV977D_HEAD_SET_BASE_LUT_LO_MODE 27:24 +#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV977D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV977D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV977D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV977D_HEAD_SET_BASE_LUT_HI(a) (0x00000444 + (a)*0x00000300) +#define NV977D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV977D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000448 + (a)*0x00000300) +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV977D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000044C + (a)*0x00000300) +#define NV977D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x00000450 + (a)*0x00000300) +#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x00000454 + (a)*0x00000300) +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE 21:20 +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25 (0x00000000) +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28 (0x00000001) +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM (0x00000002) +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 24:24 +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING 25:25 +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE (0x00000000) +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE (0x00000001) +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 26:26 +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00000458 + (a)*0x00000300) +#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NV977D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000045C + (a)*0x00000300) +#define NV977D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV977D_HEAD_SET_OFFSET(a) (0x00000460 + (a)*0x00000300) +#define NV977D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV977D_HEAD_SET_SIZE(a) (0x00000468 + (a)*0x00000300) +#define NV977D_HEAD_SET_SIZE_WIDTH 15:0 +#define NV977D_HEAD_SET_SIZE_HEIGHT 31:16 +#define NV977D_HEAD_SET_STORAGE(a) (0x0000046C + (a)*0x00000300) +#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV977D_HEAD_SET_STORAGE_PITCH 20:8 +#define NV977D_HEAD_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV977D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV977D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV977D_HEAD_SET_PARAMS(a) (0x00000470 + (a)*0x00000300) +#define NV977D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV977D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV977D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV977D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV977D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV977D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV977D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV977D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV977D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024) +#define NV977D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV977D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV977D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV977D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV977D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV977D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV977D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV977D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV977D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV977D_HEAD_SET_PARAMS_GAMMA 2:2 +#define NV977D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV977D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV977D_HEAD_SET_CONTEXT_DMAS_ISO(a) (0x00000474 + (a)*0x00000300) +#define NV977D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV977D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x0000047C + (a)*0x00000300) +#define NV977D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 1:0 +#define NV977D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NV977D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NV977D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_SPEC_FLIP (0x00000002) +#define NV977D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300) +#define NV977D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV977D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV977D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV977D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV977D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV977D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV977D_HEAD_SET_CONTROL_CURSOR_SIZE 27:26 +#define NV977D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV977D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV977D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NV977D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NV977D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 15:8 +#define NV977D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 23:16 +#define NV977D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV977D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV977D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV977D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV977D_HEAD_SET_OFFSETS_CURSOR(a,b) (0x00000484 + (a)*0x00000300 + (b)*0x00000004) +#define NV977D_HEAD_SET_OFFSETS_CURSOR_ORIGIN 31:0 +#define NV977D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b) (0x0000048C + (a)*0x00000300 + (b)*0x00000004) +#define NV977D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE 31:0 +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00000494 + (a)*0x00000300) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422 8:8 +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE (0x00000000) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE (0x00000001) +#define NV977D_HEAD_SET_PROCAMP(a) (0x00000498 + (a)*0x00000300) +#define NV977D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV977D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV977D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV977D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV977D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003) +#define NV977D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV977D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV977D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV977D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV977D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV977D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 5:5 +#define NV977D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NV977D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NV977D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 6:6 +#define NV977D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) +#define NV977D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) +#define NV977D_HEAD_SET_DITHER_CONTROL(a) (0x000004A0 + (a)*0x00000300) +#define NV977D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV977D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV977D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV977D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV977D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV977D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV977D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002) +#define NV977D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV977D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV977D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV977D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV977D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV977D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NV977D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV977D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x000004B0 + (a)*0x00000300) +#define NV977D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV977D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV977D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000004B8 + (a)*0x00000300) +#define NV977D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV977D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV977D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x000004BC + (a)*0x00000300) +#define NV977D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NV977D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000004C0 + (a)*0x00000300) +#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000004C4 + (a)*0x00000300) +#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a) (0x000004C8 + (a)*0x00000300) +#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH 14:0 +#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT 30:16 +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT 17:16 +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE (0x00000000) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257 (0x00000001) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025 (0x00000002) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT 21:20 +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) +#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x000004D4 + (a)*0x00000300) +#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT 13:12 +#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE (0x00000000) +#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257 (0x00000001) +#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025 (0x00000002) +#define NV977D_HEAD_SET_PROCESSING(a) (0x000004E0 + (a)*0x00000300) +#define NV977D_HEAD_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV977D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV977D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV977D_HEAD_SET_CONVERSION_RED(a) (0x000004E4 + (a)*0x00000300) +#define NV977D_HEAD_SET_CONVERSION_RED_GAIN 15:0 +#define NV977D_HEAD_SET_CONVERSION_RED_OFS 31:16 +#define NV977D_HEAD_SET_CONVERSION_GRN(a) (0x000004E8 + (a)*0x00000300) +#define NV977D_HEAD_SET_CONVERSION_GRN_GAIN 15:0 +#define NV977D_HEAD_SET_CONVERSION_GRN_OFS 31:16 +#define NV977D_HEAD_SET_CONVERSION_BLU(a) (0x000004EC + (a)*0x00000300) +#define NV977D_HEAD_SET_CONVERSION_BLU_GAIN 15:0 +#define NV977D_HEAD_SET_CONVERSION_BLU_OFS 31:16 +#define NV977D_HEAD_SET_CSC_RED2RED(a) (0x000004F0 + (a)*0x00000300) +#define NV977D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE 31:31 +#define NV977D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV977D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV977D_HEAD_SET_CSC_RED2RED_COEFF 18:0 +#define NV977D_HEAD_SET_CSC_GRN2RED(a) (0x000004F4 + (a)*0x00000300) +#define NV977D_HEAD_SET_CSC_GRN2RED_COEFF 18:0 +#define NV977D_HEAD_SET_CSC_BLU2RED(a) (0x000004F8 + (a)*0x00000300) +#define NV977D_HEAD_SET_CSC_BLU2RED_COEFF 18:0 +#define NV977D_HEAD_SET_CSC_CONSTANT2RED(a) (0x000004FC + (a)*0x00000300) +#define NV977D_HEAD_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV977D_HEAD_SET_CSC_RED2GRN(a) (0x00000500 + (a)*0x00000300) +#define NV977D_HEAD_SET_CSC_RED2GRN_COEFF 18:0 +#define NV977D_HEAD_SET_CSC_GRN2GRN(a) (0x00000504 + (a)*0x00000300) +#define NV977D_HEAD_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV977D_HEAD_SET_CSC_BLU2GRN(a) (0x00000508 + (a)*0x00000300) +#define NV977D_HEAD_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV977D_HEAD_SET_CSC_CONSTANT2GRN(a) (0x0000050C + (a)*0x00000300) +#define NV977D_HEAD_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV977D_HEAD_SET_CSC_RED2BLU(a) (0x00000510 + (a)*0x00000300) +#define NV977D_HEAD_SET_CSC_RED2BLU_COEFF 18:0 +#define NV977D_HEAD_SET_CSC_GRN2BLU(a) (0x00000514 + (a)*0x00000300) +#define NV977D_HEAD_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV977D_HEAD_SET_CSC_BLU2BLU(a) (0x00000518 + (a)*0x00000300) +#define NV977D_HEAD_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV977D_HEAD_SET_CSC_CONSTANT2BLU(a) (0x0000051C + (a)*0x00000300) +#define NV977D_HEAD_SET_CSC_CONSTANT2BLU_COEFF 18:0 +#define NV977D_HEAD_SET_HDMI_CTRL(a) (0x00000520 + (a)*0x00000300) +#define NV977D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NV977D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NV977D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NV977D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NV977D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NV977D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE 15:12 +#define NV977D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000000) +#define NV977D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FIELD_ALTERNATIVE (0x00000001) +#define NV977D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_LINE_ALTERNATIVE (0x00000002) +#define NV977D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_FULL (0x00000003) +#define NV977D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH (0x00000004) +#define NV977D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH_GRAPHICS (0x00000005) +#define NV977D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_TOP_AND_BOTTOM (0x00000006) +#define NV977D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_HALF (0x00000008) +#define NV977D_HEAD_SET_VACTIVE_SPACE_COLOR(a) (0x00000524 + (a)*0x00000300) +#define NV977D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR 9:0 +#define NV977D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y 19:10 +#define NV977D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB 29:20 +#define NV977D_HEAD_SET_PIXEL_REORDER_CONTROL(a) (0x00000528 + (a)*0x00000300) +#define NV977D_HEAD_SET_PIXEL_REORDER_CONTROL_BANK_WIDTH 13:0 +#define NV977D_HEAD_SET_DISPLAY_ID(a,b) (0x0000052C + (a)*0x00000300 + (b)*0x00000004) +#define NV977D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NV977D_HEAD_SET_SW_SPARE_A(a) (0x0000054C + (a)*0x00000300) +#define NV977D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NV977D_HEAD_SET_SW_SPARE_B(a) (0x00000550 + (a)*0x00000300) +#define NV977D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NV977D_HEAD_SET_SW_SPARE_C(a) (0x00000554 + (a)*0x00000300) +#define NV977D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NV977D_HEAD_SET_SW_SPARE_D(a) (0x00000558 + (a)*0x00000300) +#define NV977D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NV977D_HEAD_SET_GET_BLANKING_CTRL(a) (0x0000055C + (a)*0x00000300) +#define NV977D_HEAD_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NV977D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NV977D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NV977D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NV977D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NV977D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) +#define NV977D_HEAD_SET_CONTROL_COMPRESSION(a) (0x00000560 + (a)*0x00000300) +#define NV977D_HEAD_SET_CONTROL_COMPRESSION_ENABLE 0:0 +#define NV977D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_DISABLE (0x00000000) +#define NV977D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_ENABLE (0x00000001) +#define NV977D_HEAD_SET_CONTROL_COMPRESSION_CHUNK_BANDWIDTH 12:1 +#define NV977D_HEAD_SET_CONTROL_COMPRESSION_LAST_BANDWIDTH 24:13 +#define NV977D_HEAD_SET_CONTROL_COMPRESSION_LA(a) (0x00000564 + (a)*0x00000300) +#define NV977D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY1 7:4 +#define NV977D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY2 11:8 +#define NV977D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY3 15:12 +#define NV977D_HEAD_SET_CONTROL_COMPRESSION_LA_CHUNK_SIZE 23:16 +#define NV977D_HEAD_SET_STALL_LOCK(a) (0x00000568 + (a)*0x00000300) +#define NV977D_HEAD_SET_STALL_LOCK_ENABLE 0:0 +#define NV977D_HEAD_SET_STALL_LOCK_ENABLE_FALSE (0x00000000) +#define NV977D_HEAD_SET_STALL_LOCK_ENABLE_TRUE (0x00000001) +#define NV977D_HEAD_SET_STALL_LOCK_MODE 1:1 +#define NV977D_HEAD_SET_STALL_LOCK_MODE_CONTINUOUS (0x00000000) +#define NV977D_HEAD_SET_STALL_LOCK_MODE_ONE_SHOT (0x00000001) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN 6:2 +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV977D_HEAD_SET_STALL_LOCK_UNSTALL_MODE 7:7 +#define NV977D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_CRASH_LOCK (0x00000000) +#define NV977D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_LINE_LOCK (0x00000001) +#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a) (0x000006D0 + (a)*0x00000300) +#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED 31:0 +#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a) (0x000006D4 + (a)*0x00000300) +#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED 31:0 +#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a) (0x000006D8 + (a)*0x00000300) +#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED 31:0 +#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a) (0x000006DC + (a)*0x00000300) +#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED 31:0 +#define NV977D_HEAD_SET_SPARE(a) (0x000006EC + (a)*0x00000300) +#define NV977D_HEAD_SET_SPARE_UNUSED 31:0 +#define NV977D_HEAD_SET_SPARE_NOOP(a,b) (0x000006F0 + (a)*0x00000300 + (b)*0x00000004) +#define NV977D_HEAD_SET_SPARE_NOOP_UNUSED 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl977d_h diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl9870.h b/userspace/sdks/nv525/nvidia/inc/class/cl9870.h new file mode 100644 index 0000000..44b7659 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl9870.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9870.finn +// + +#define NV9870_DISPLAY (0x9870U) /* finn: Evaluated from "NV9870_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV9870_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9870U) + +typedef struct NV9870_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numDacs; // Number of DACs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NV9870_ALLOCATION_PARAMETERS; diff --git a/userspace/sdks/nv525/nvidia/inc/class/cl987d.h b/userspace/sdks/nv525/nvidia/inc/class/cl987d.h new file mode 100644 index 0000000..ab01f62 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cl987d.h @@ -0,0 +1,1590 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl987d_h_ +#define _cl987d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV987D_CORE_CHANNEL_DMA (0x0000987D) + +#define NV987D_CORE_NOTIFIER_3 0x00000000 +#define NV987D_CORE_NOTIFIER_3_SIZEOF 0x00000150 +#define NV987D_CORE_NOTIFIER_3_COMPLETION_0 0x00000000 +#define NV987D_CORE_NOTIFIER_3_COMPLETION_0_DONE 0:0 +#define NV987D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_COMPLETION_0_R0 15:1 +#define NV987D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP 29:16 +#define NV987D_CORE_NOTIFIER_3__1 0x00000001 +#define NV987D_CORE_NOTIFIER_3__1_R1 31:0 +#define NV987D_CORE_NOTIFIER_3__2 0x00000002 +#define NV987D_CORE_NOTIFIER_3__2_R2 31:0 +#define NV987D_CORE_NOTIFIER_3__3 0x00000003 +#define NV987D_CORE_NOTIFIER_3__3_R3 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO 2:2 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_R0 19:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA 20:20 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_R1 29:21 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE 30:30 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5 0x00000005 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE 3:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE 7:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE 11:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE 15:12 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE 19:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE 23:20 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE 27:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE 31:28 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6 0x00000006 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE 3:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE 7:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE 11:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE 15:12 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE 19:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE 23:20 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE 27:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE 31:28 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_7 0x00000007 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_7_R4 31:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_8 0x00000008 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_8_R5 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_9 0x00000009 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_9_R6 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_10 0x0000000A +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_10_R7 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_11 0x0000000B +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_11_R8 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12 0x0000000C +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE 3:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0 31:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13 0x0000000D +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1 31:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14 0x0000000E +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE 3:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0 31:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15 0x0000000F +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1 31:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16 0x00000010 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE 3:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0 31:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17 0x00000011 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1 31:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18 0x00000012 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE 3:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0 31:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19 0x00000013 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1 31:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18 2:2 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24 3:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0 7:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A 8:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B 9:9 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1 10:10 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS 11:11 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2 13:12 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3 16:14 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4 19:17 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5 23:20 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A 24:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B 25:25 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE 26:26 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6 31:28 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21 0x00000015 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7 15:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_CLK_MAX 23:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_LVDS_CLK_MAX 31:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22 0x00000016 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18 2:2 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24 3:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0 7:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A 8:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B 9:9 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1 10:10 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS 11:11 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2 13:12 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3 16:14 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4 19:17 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5 23:20 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A 24:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B 25:25 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE 26:26 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6 31:28 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23 0x00000017 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7 15:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_CLK_MAX 23:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_LVDS_CLK_MAX 31:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24 0x00000018 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18 2:2 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24 3:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0 7:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A 8:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B 9:9 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1 10:10 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS 11:11 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2 13:12 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3 16:14 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4 19:17 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5 23:20 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A 24:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B 25:25 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE 26:26 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6 31:28 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25 0x00000019 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7 15:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_CLK_MAX 23:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_LVDS_CLK_MAX 31:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26 0x0000001A +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18 2:2 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24 3:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0 7:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A 8:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B 9:9 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1 10:10 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS 11:11 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2 13:12 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3 16:14 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4 19:17 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5 23:20 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A 24:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B 25:25 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE 26:26 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6 31:28 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27 0x0000001B +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7 15:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_CLK_MAX 23:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_LVDS_CLK_MAX 31:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28 0x0000001C +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18 2:2 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24 3:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0 7:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A 8:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B 9:9 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1 10:10 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS 11:11 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2 13:12 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3 16:14 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4 19:17 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5 23:20 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A 24:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B 25:25 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE 26:26 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6 31:28 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29 0x0000001D +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7 15:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_CLK_MAX 23:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_LVDS_CLK_MAX 31:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30 0x0000001E +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18 2:2 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24 3:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0 7:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A 8:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B 9:9 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1 10:10 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS 11:11 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2 13:12 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3 16:14 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4 19:17 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5 23:20 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A 24:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B 25:25 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE 26:26 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6 31:28 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31 0x0000001F +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7 15:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_CLK_MAX 23:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_LVDS_CLK_MAX 31:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32 0x00000020 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18 2:2 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24 3:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0 7:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A 8:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B 9:9 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1 10:10 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS 11:11 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2 13:12 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3 16:14 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4 19:17 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5 23:20 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A 24:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B 25:25 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE 26:26 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6 31:28 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33 0x00000021 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7 15:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_CLK_MAX 23:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_LVDS_CLK_MAX 31:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34 0x00000022 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18 2:2 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24 3:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0 7:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A 8:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B 9:9 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1 10:10 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS 11:11 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2 13:12 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3 16:14 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4 19:17 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5 23:20 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A 24:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B 25:25 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE 26:26 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6 31:28 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35 0x00000023 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7 15:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_CLK_MAX 23:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_LVDS_CLK_MAX 31:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36 0x00000024 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0 31:10 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37 0x00000025 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1 15:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2 31:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38 0x00000026 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0 31:10 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39 0x00000027 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1 15:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2 31:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40 0x00000028 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0 31:10 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41 0x00000029 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1 15:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2 31:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42 0x0000002A +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0 31:10 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43 0x0000002B +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1 15:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2 31:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52 0x00000034 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0 31:14 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53 0x00000035 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444 14:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1 15:15 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422 30:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54 0x00000036 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444 14:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3 15:15 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422 30:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55 0x00000037 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444 14:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5 15:15 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422 30:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56 0x00000038 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7 31:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57 0x00000039 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58 0x0000003A +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59 0x0000003B +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60 0x0000003C +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0 31:14 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61 0x0000003D +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444 14:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1 15:15 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422 30:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62 0x0000003E +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444 14:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3 15:15 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422 30:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63 0x0000003F +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444 14:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5 15:15 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422 30:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64 0x00000040 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7 31:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65 0x00000041 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66 0x00000042 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67 0x00000043 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68 0x00000044 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0 31:14 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69 0x00000045 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444 14:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1 15:15 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422 30:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70 0x00000046 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444 14:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3 15:15 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422 30:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71 0x00000047 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444 14:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5 15:15 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422 30:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72 0x00000048 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7 31:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73 0x00000049 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74 0x0000004A +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75 0x0000004B +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76 0x0000004C +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0 31:14 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77 0x0000004D +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444 14:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1 15:15 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422 30:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78 0x0000004E +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444 14:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3 15:15 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422 30:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79 0x0000004F +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444 14:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5 15:15 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422 30:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80 0x00000050 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7 31:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81 0x00000051 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82 0x00000052 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83 0x00000053 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10 31:0 + + +// dma opcode instructions +#define NV987D_DMA 0x00000000 +#define NV987D_DMA_OPCODE 31:29 +#define NV987D_DMA_OPCODE_METHOD 0x00000000 +#define NV987D_DMA_OPCODE_JUMP 0x00000001 +#define NV987D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV987D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV987D_DMA_METHOD_COUNT 27:18 +#define NV987D_DMA_METHOD_OFFSET 11:2 +#define NV987D_DMA_DATA 31:0 +#define NV987D_DMA_DATA_NOP 0x00000000 +#define NV987D_DMA_JUMP_OFFSET 11:2 +#define NV987D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV987D_PUT (0x00000000) +#define NV987D_PUT_PTR 11:2 +#define NV987D_GET (0x00000004) +#define NV987D_GET_PTR 11:2 +#define NV987D_UPDATE (0x00000080) +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR(i) (0 +(i)*4):(0 +(i)*4) +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1 4 +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0 +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR1 4:4 +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR2 8:8 +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR3 12:12 +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_BASE(i) (1 +(i)*4):(1 +(i)*4) +#define NV987D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1 4 +#define NV987D_UPDATE_INTERLOCK_WITH_BASE_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_BASE_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_BASE0 1:1 +#define NV987D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_BASE1 5:5 +#define NV987D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_BASE2 9:9 +#define NV987D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_BASE3 13:13 +#define NV987D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY(i) (2 +(i)*4):(2 +(i)*4) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1 4 +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2 +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY1 6:6 +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY2 10:10 +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY3 14:14 +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i) (3 +(i)*4):(3 +(i)*4) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1 4 +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3 +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 7:7 +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2 11:11 +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3 15:15 +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE (0x00000001) +#define NV987D_UPDATE_SPECIAL_HANDLING 25:24 +#define NV987D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV987D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV987D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV987D_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV987D_UPDATE_NOT_DRIVER_FRIENDLY 31:31 +#define NV987D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000) +#define NV987D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001) +#define NV987D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30 +#define NV987D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000) +#define NV987D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001) +#define NV987D_UPDATE_INHIBIT_INTERRUPTS 29:29 +#define NV987D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NV987D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NV987D_SET_NOTIFIER_CONTROL (0x00000084) +#define NV987D_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV987D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV987D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV987D_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV987D_SET_NOTIFIER_CONTROL_NOTIFY 31:31 +#define NV987D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NV987D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NV987D_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV987D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV987D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV987D_SET_NOTIFIER_CONTROL_NO_WAIT_ACTIVE 0:0 +#define NV987D_SET_NOTIFIER_CONTROL_NO_WAIT_ACTIVE_FALSE (0x00000000) +#define NV987D_SET_NOTIFIER_CONTROL_NO_WAIT_ACTIVE_TRUE (0x00000001) +#define NV987D_SET_CONTEXT_DMA_NOTIFIER (0x00000088) +#define NV987D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV987D_GET_CAPABILITIES (0x0000008C) +#define NV987D_GET_CAPABILITIES_DUMMY 31:0 +#define NV987D_SET_SPARE (0x0000016C) +#define NV987D_SET_SPARE_UNUSED 31:0 +#define NV987D_SET_SPARE_NOOP(b) (0x00000170 + (b)*0x00000004) +#define NV987D_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV987D_DAC_SET_CONTROL(a) (0x00000180 + (a)*0x00000020) +#define NV987D_DAC_SET_CONTROL_OWNER_MASK 3:0 +#define NV987D_DAC_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV987D_DAC_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV987D_DAC_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV987D_DAC_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV987D_DAC_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV987D_DAC_SET_CONTROL_PROTOCOL 12:8 +#define NV987D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV987D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT (0x00000013) +#define NV987D_DAC_SET_SW_SPARE_A(a) (0x00000184 + (a)*0x00000020) +#define NV987D_DAC_SET_SW_SPARE_A_CODE 31:0 +#define NV987D_DAC_SET_SW_SPARE_B(a) (0x00000188 + (a)*0x00000020) +#define NV987D_DAC_SET_SW_SPARE_B_CODE 31:0 +#define NV987D_DAC_SET_CUSTOM_REASON(a) (0x00000190 + (a)*0x00000020) +#define NV987D_DAC_SET_CUSTOM_REASON_CODE 31:0 + +#define NV987D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020) +#define NV987D_SOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV987D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV987D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV987D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV987D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV987D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV987D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV987D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV987D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV987D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV987D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV987D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NV987D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NV987D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV987D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV987D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV987D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV987D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NV987D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NV987D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NV987D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NV987D_SOR_SET_SW_SPARE_A(a) (0x00000204 + (a)*0x00000020) +#define NV987D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NV987D_SOR_SET_SW_SPARE_B(a) (0x00000208 + (a)*0x00000020) +#define NV987D_SOR_SET_SW_SPARE_B_CODE 31:0 +#define NV987D_SOR_SET_CUSTOM_REASON(a) (0x00000210 + (a)*0x00000020) +#define NV987D_SOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV987D_PIOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NV987D_PIOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV987D_PIOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV987D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV987D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV987D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV987D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV987D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV987D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV987D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV987D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV987D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV987D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV987D_PIOR_SET_SW_SPARE_A(a) (0x00000304 + (a)*0x00000020) +#define NV987D_PIOR_SET_SW_SPARE_A_CODE 31:0 +#define NV987D_PIOR_SET_SW_SPARE_B(a) (0x00000308 + (a)*0x00000020) +#define NV987D_PIOR_SET_SW_SPARE_B_CODE 31:0 +#define NV987D_PIOR_SET_CUSTOM_REASON(a) (0x00000310 + (a)*0x00000020) +#define NV987D_PIOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV987D_HEAD_SET_PRESENT_CONTROL(a) (0x00000400 + (a)*0x00000300) +#define NV987D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NV987D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 8:8 +#define NV987D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NV987D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NV987D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00000404 + (a)*0x00000300) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 3:3 +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 4:4 +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 9:6 +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000009) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 12:12 +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 24:13 +#define NV987D_HEAD_SET_CONTROL(a) (0x00000408 + (a)*0x00000300) +#define NV987D_HEAD_SET_CONTROL_STRUCTURE 0:0 +#define NV987D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV987D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 3:2 +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 19:15 +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 7:4 +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 9:8 +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 14:10 +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK 1:1 +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_DISABLE (0x00000000) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_ENABLE (0x00000001) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN 24:20 +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN 29:25 +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000000) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000001) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000002) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000003) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000004) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000005) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000006) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000007) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000008) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x00000009) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000A) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000B) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000C) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000D) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000E) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x0000000F) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_UNSPECIFIED (0x00000010) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV987D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NV987D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV987D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV987D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NV987D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV987D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV987D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000410 + (a)*0x00000300) +#define NV987D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV987D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV987D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV987D_HEAD_SET_RASTER_SIZE(a) (0x00000414 + (a)*0x00000300) +#define NV987D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV987D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV987D_HEAD_SET_RASTER_SYNC_END(a) (0x00000418 + (a)*0x00000300) +#define NV987D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV987D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV987D_HEAD_SET_RASTER_BLANK_END(a) (0x0000041C + (a)*0x00000300) +#define NV987D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV987D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV987D_HEAD_SET_RASTER_BLANK_START(a) (0x00000420 + (a)*0x00000300) +#define NV987D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV987D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV987D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000424 + (a)*0x00000300) +#define NV987D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV987D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV987D_HEAD_SET_LOCK_CHAIN(a) (0x00000428 + (a)*0x00000300) +#define NV987D_HEAD_SET_LOCK_CHAIN_POSITION 27:24 +#define NV987D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000042C + (a)*0x00000300) +#define NV987D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV987D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV987D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV987D_HEAD_SET_CRC_CONTROL(a) (0x00000430 + (a)*0x00000300) +#define NV987D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 1:0 +#define NV987D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000000) +#define NV987D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_BASE (0x00000001) +#define NV987D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_OVERLAY (0x00000002) +#define NV987D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 2:2 +#define NV987D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NV987D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NV987D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE 3:3 +#define NV987D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_FALSE (0x00000000) +#define NV987D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_TRUE (0x00000001) +#define NV987D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE 4:4 +#define NV987D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_FALSE (0x00000000) +#define NV987D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_TRUE (0x00000001) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT 19:8 +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC__SIZE_1 4 +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC0 (0x00000FF0) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC1 (0x00000FF1) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC2 (0x00000FF2) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC3 (0x00000FF3) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG__SIZE_1 4 +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG0 (0x00000FF8) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG1 (0x00000FF9) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG2 (0x00000FFA) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG3 (0x00000FFB) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR__SIZE_1 8 +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR0 (0x00000F0F) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR1 (0x00000F1F) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR2 (0x00000F2F) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR3 (0x00000F3F) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR4 (0x00000F4F) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR5 (0x00000F5F) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR6 (0x00000F6F) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR7 (0x00000F7F) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF__SIZE_1 4 +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF0 (0x00000F8F) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF1 (0x00000F9F) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF2 (0x00000FAF) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF3 (0x00000FBF) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR__SIZE_1 8 +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR0 (0x000000FF) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR1 (0x000001FF) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR2 (0x000002FF) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR3 (0x000003FF) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR4 (0x000004FF) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR5 (0x000005FF) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR6 (0x000006FF) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR7 (0x000007FF) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_NONE (0x00000FFF) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT 31:20 +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC__SIZE_1 4 +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC0 (0x00000FF0) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC1 (0x00000FF1) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC2 (0x00000FF2) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC3 (0x00000FF3) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG__SIZE_1 4 +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG0 (0x00000FF8) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG1 (0x00000FF9) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG2 (0x00000FFA) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG3 (0x00000FFB) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR__SIZE_1 8 +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR0 (0x00000F0F) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR1 (0x00000F1F) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR2 (0x00000F2F) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR3 (0x00000F3F) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR4 (0x00000F4F) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR5 (0x00000F5F) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR6 (0x00000F6F) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR7 (0x00000F7F) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF__SIZE_1 4 +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF0 (0x00000F8F) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF1 (0x00000F9F) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF2 (0x00000FAF) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF3 (0x00000FBF) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR__SIZE_1 8 +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR0 (0x000000FF) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR1 (0x000001FF) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR2 (0x000002FF) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR3 (0x000003FF) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR4 (0x000004FF) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR5 (0x000005FF) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR6 (0x000006FF) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR7 (0x000007FF) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_NONE (0x00000FFF) +#define NV987D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 5:5 +#define NV987D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NV987D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NV987D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC 6:6 +#define NV987D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_DISABLE (0x00000000) +#define NV987D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_ENABLE (0x00000001) +#define NV987D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00000438 + (a)*0x00000300) +#define NV987D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NV987D_HEAD_SET_BASE_LUT_LO(a) (0x00000440 + (a)*0x00000300) +#define NV987D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV987D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV987D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV987D_HEAD_SET_BASE_LUT_LO_MODE 27:24 +#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV987D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV987D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV987D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV987D_HEAD_SET_BASE_LUT_HI(a) (0x00000444 + (a)*0x00000300) +#define NV987D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV987D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000448 + (a)*0x00000300) +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV987D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000044C + (a)*0x00000300) +#define NV987D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x00000450 + (a)*0x00000300) +#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x00000454 + (a)*0x00000300) +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE 21:20 +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25 (0x00000000) +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28 (0x00000001) +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM (0x00000002) +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 24:24 +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING 25:25 +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE (0x00000000) +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE (0x00000001) +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 26:26 +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00000458 + (a)*0x00000300) +#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NV987D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000045C + (a)*0x00000300) +#define NV987D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV987D_HEAD_SET_OFFSET(a) (0x00000460 + (a)*0x00000300) +#define NV987D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV987D_HEAD_SET_SIZE(a) (0x00000468 + (a)*0x00000300) +#define NV987D_HEAD_SET_SIZE_WIDTH 15:0 +#define NV987D_HEAD_SET_SIZE_HEIGHT 31:16 +#define NV987D_HEAD_SET_STORAGE(a) (0x0000046C + (a)*0x00000300) +#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV987D_HEAD_SET_STORAGE_PITCH 20:8 +#define NV987D_HEAD_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV987D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV987D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV987D_HEAD_SET_PARAMS(a) (0x00000470 + (a)*0x00000300) +#define NV987D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV987D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV987D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV987D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV987D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV987D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV987D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV987D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV987D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024) +#define NV987D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV987D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV987D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV987D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV987D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV987D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV987D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV987D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV987D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV987D_HEAD_SET_PARAMS_GAMMA 2:2 +#define NV987D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV987D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV987D_HEAD_SET_CONTEXT_DMAS_ISO(a) (0x00000474 + (a)*0x00000300) +#define NV987D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV987D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x0000047C + (a)*0x00000300) +#define NV987D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 1:0 +#define NV987D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NV987D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NV987D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_SPEC_FLIP (0x00000002) +#define NV987D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300) +#define NV987D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV987D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV987D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV987D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV987D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV987D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV987D_HEAD_SET_CONTROL_CURSOR_SIZE 27:26 +#define NV987D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV987D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV987D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NV987D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NV987D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 15:8 +#define NV987D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 23:16 +#define NV987D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV987D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV987D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV987D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV987D_HEAD_SET_OFFSETS_CURSOR(a,b) (0x00000484 + (a)*0x00000300 + (b)*0x00000004) +#define NV987D_HEAD_SET_OFFSETS_CURSOR_ORIGIN 31:0 +#define NV987D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b) (0x0000048C + (a)*0x00000300 + (b)*0x00000004) +#define NV987D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE 31:0 +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00000494 + (a)*0x00000300) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422 8:8 +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE (0x00000000) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE (0x00000001) +#define NV987D_HEAD_SET_PROCAMP(a) (0x00000498 + (a)*0x00000300) +#define NV987D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV987D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV987D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV987D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV987D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003) +#define NV987D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV987D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV987D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV987D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV987D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV987D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 5:5 +#define NV987D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NV987D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NV987D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 6:6 +#define NV987D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) +#define NV987D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) +#define NV987D_HEAD_SET_DITHER_CONTROL(a) (0x000004A0 + (a)*0x00000300) +#define NV987D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV987D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV987D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV987D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV987D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV987D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV987D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002) +#define NV987D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV987D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV987D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV987D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV987D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV987D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NV987D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV987D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x000004B0 + (a)*0x00000300) +#define NV987D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV987D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV987D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000004B8 + (a)*0x00000300) +#define NV987D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV987D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV987D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x000004BC + (a)*0x00000300) +#define NV987D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NV987D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000004C0 + (a)*0x00000300) +#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000004C4 + (a)*0x00000300) +#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a) (0x000004C8 + (a)*0x00000300) +#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH 14:0 +#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT 30:16 +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT 17:16 +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE (0x00000000) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257 (0x00000001) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025 (0x00000002) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT 21:20 +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) +#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x000004D4 + (a)*0x00000300) +#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT 13:12 +#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE (0x00000000) +#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257 (0x00000001) +#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025 (0x00000002) +#define NV987D_HEAD_SET_PROCESSING(a) (0x000004E0 + (a)*0x00000300) +#define NV987D_HEAD_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV987D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV987D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV987D_HEAD_SET_CONVERSION_RED(a) (0x000004E4 + (a)*0x00000300) +#define NV987D_HEAD_SET_CONVERSION_RED_GAIN 15:0 +#define NV987D_HEAD_SET_CONVERSION_RED_OFS 31:16 +#define NV987D_HEAD_SET_CONVERSION_GRN(a) (0x000004E8 + (a)*0x00000300) +#define NV987D_HEAD_SET_CONVERSION_GRN_GAIN 15:0 +#define NV987D_HEAD_SET_CONVERSION_GRN_OFS 31:16 +#define NV987D_HEAD_SET_CONVERSION_BLU(a) (0x000004EC + (a)*0x00000300) +#define NV987D_HEAD_SET_CONVERSION_BLU_GAIN 15:0 +#define NV987D_HEAD_SET_CONVERSION_BLU_OFS 31:16 +#define NV987D_HEAD_SET_CSC_RED2RED(a) (0x000004F0 + (a)*0x00000300) +#define NV987D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE 31:31 +#define NV987D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV987D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV987D_HEAD_SET_CSC_RED2RED_COEFF 18:0 +#define NV987D_HEAD_SET_CSC_GRN2RED(a) (0x000004F4 + (a)*0x00000300) +#define NV987D_HEAD_SET_CSC_GRN2RED_COEFF 18:0 +#define NV987D_HEAD_SET_CSC_BLU2RED(a) (0x000004F8 + (a)*0x00000300) +#define NV987D_HEAD_SET_CSC_BLU2RED_COEFF 18:0 +#define NV987D_HEAD_SET_CSC_CONSTANT2RED(a) (0x000004FC + (a)*0x00000300) +#define NV987D_HEAD_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV987D_HEAD_SET_CSC_RED2GRN(a) (0x00000500 + (a)*0x00000300) +#define NV987D_HEAD_SET_CSC_RED2GRN_COEFF 18:0 +#define NV987D_HEAD_SET_CSC_GRN2GRN(a) (0x00000504 + (a)*0x00000300) +#define NV987D_HEAD_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV987D_HEAD_SET_CSC_BLU2GRN(a) (0x00000508 + (a)*0x00000300) +#define NV987D_HEAD_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV987D_HEAD_SET_CSC_CONSTANT2GRN(a) (0x0000050C + (a)*0x00000300) +#define NV987D_HEAD_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV987D_HEAD_SET_CSC_RED2BLU(a) (0x00000510 + (a)*0x00000300) +#define NV987D_HEAD_SET_CSC_RED2BLU_COEFF 18:0 +#define NV987D_HEAD_SET_CSC_GRN2BLU(a) (0x00000514 + (a)*0x00000300) +#define NV987D_HEAD_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV987D_HEAD_SET_CSC_BLU2BLU(a) (0x00000518 + (a)*0x00000300) +#define NV987D_HEAD_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV987D_HEAD_SET_CSC_CONSTANT2BLU(a) (0x0000051C + (a)*0x00000300) +#define NV987D_HEAD_SET_CSC_CONSTANT2BLU_COEFF 18:0 +#define NV987D_HEAD_SET_HDMI_CTRL(a) (0x00000520 + (a)*0x00000300) +#define NV987D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NV987D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NV987D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NV987D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NV987D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NV987D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE 15:12 +#define NV987D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000000) +#define NV987D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FIELD_ALTERNATIVE (0x00000001) +#define NV987D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_LINE_ALTERNATIVE (0x00000002) +#define NV987D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_FULL (0x00000003) +#define NV987D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH (0x00000004) +#define NV987D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH_GRAPHICS (0x00000005) +#define NV987D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_TOP_AND_BOTTOM (0x00000006) +#define NV987D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_HALF (0x00000008) +#define NV987D_HEAD_SET_VACTIVE_SPACE_COLOR(a) (0x00000524 + (a)*0x00000300) +#define NV987D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR 9:0 +#define NV987D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y 19:10 +#define NV987D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB 29:20 +#define NV987D_HEAD_SET_PIXEL_REORDER_CONTROL(a) (0x00000528 + (a)*0x00000300) +#define NV987D_HEAD_SET_PIXEL_REORDER_CONTROL_BANK_WIDTH 13:0 +#define NV987D_HEAD_SET_DISPLAY_ID(a,b) (0x0000052C + (a)*0x00000300 + (b)*0x00000004) +#define NV987D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NV987D_HEAD_SET_SW_SPARE_A(a) (0x0000054C + (a)*0x00000300) +#define NV987D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NV987D_HEAD_SET_SW_SPARE_B(a) (0x00000550 + (a)*0x00000300) +#define NV987D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NV987D_HEAD_SET_SW_SPARE_C(a) (0x00000554 + (a)*0x00000300) +#define NV987D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NV987D_HEAD_SET_SW_SPARE_D(a) (0x00000558 + (a)*0x00000300) +#define NV987D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NV987D_HEAD_SET_GET_BLANKING_CTRL(a) (0x0000055C + (a)*0x00000300) +#define NV987D_HEAD_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NV987D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NV987D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NV987D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NV987D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NV987D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) +#define NV987D_HEAD_SET_CONTROL_COMPRESSION(a) (0x00000560 + (a)*0x00000300) +#define NV987D_HEAD_SET_CONTROL_COMPRESSION_ENABLE 0:0 +#define NV987D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_DISABLE (0x00000000) +#define NV987D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_ENABLE (0x00000001) +#define NV987D_HEAD_SET_CONTROL_COMPRESSION_CHUNK_BANDWIDTH 12:1 +#define NV987D_HEAD_SET_CONTROL_COMPRESSION_LAST_BANDWIDTH 24:13 +#define NV987D_HEAD_SET_CONTROL_COMPRESSION_LA(a) (0x00000564 + (a)*0x00000300) +#define NV987D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY1 7:4 +#define NV987D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY2 11:8 +#define NV987D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY3 15:12 +#define NV987D_HEAD_SET_CONTROL_COMPRESSION_LA_CHUNK_SIZE 23:16 +#define NV987D_HEAD_SET_STALL_LOCK(a) (0x00000568 + (a)*0x00000300) +#define NV987D_HEAD_SET_STALL_LOCK_ENABLE 0:0 +#define NV987D_HEAD_SET_STALL_LOCK_ENABLE_FALSE (0x00000000) +#define NV987D_HEAD_SET_STALL_LOCK_ENABLE_TRUE (0x00000001) +#define NV987D_HEAD_SET_STALL_LOCK_MODE 1:1 +#define NV987D_HEAD_SET_STALL_LOCK_MODE_CONTINUOUS (0x00000000) +#define NV987D_HEAD_SET_STALL_LOCK_MODE_ONE_SHOT (0x00000001) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN 6:2 +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV987D_HEAD_SET_STALL_LOCK_UNSTALL_MODE 7:7 +#define NV987D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_CRASH_LOCK (0x00000000) +#define NV987D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_LINE_LOCK (0x00000001) +#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a) (0x000006D0 + (a)*0x00000300) +#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED 31:0 +#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a) (0x000006D4 + (a)*0x00000300) +#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED 31:0 +#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a) (0x000006D8 + (a)*0x00000300) +#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED 31:0 +#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a) (0x000006DC + (a)*0x00000300) +#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED 31:0 +#define NV987D_HEAD_SET_SPARE(a) (0x000006EC + (a)*0x00000300) +#define NV987D_HEAD_SET_SPARE_UNUSED 31:0 +#define NV987D_HEAD_SET_SPARE_NOOP(a,b) (0x000006F0 + (a)*0x00000300 + (b)*0x00000004) +#define NV987D_HEAD_SET_SPARE_NOOP_UNUSED 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl987d_h diff --git a/userspace/sdks/nv525/nvidia/inc/class/cla06c.h b/userspace/sdks/nv525/nvidia/inc/class/cla06c.h new file mode 100644 index 0000000..0b4f5c9 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cla06c.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _cla06c_h_ +#define _cla06c_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define KEPLER_CHANNEL_GROUP_A (0x0000A06C) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cla06c_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cla06f.h b/userspace/sdks/nv525/nvidia/inc/class/cla06f.h new file mode 100644 index 0000000..336cab5 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cla06f.h @@ -0,0 +1,240 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clA06f_h_ +#define _clA06f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class KEPLER_CHANNEL_GPFIFO */ +/* + * Documentation for KEPLER_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + */ +#define KEPLER_CHANNEL_GPFIFO_A (0x0000A06F) + + +/* pio method data structure */ +typedef volatile struct _cla06f_tag0 { + NvV32 Reserved00[0x7c0]; +} NvA06FTypedef, KEPLER_ChannelGPFifo; +#define NVA06F_TYPEDEF KEPLER_CHANNELChannelGPFifo +/* dma flow control data structure */ +typedef volatile struct _cla06f_tag1 { + NvU32 Ignored00[0x010]; /* 0000-0043*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} NvA06FControl, KeplerAControlGPFifo; +/* fields and values */ +#define NVA06F_NUMBER_OF_SUBCHANNELS (8) +#define NVA06F_SET_OBJECT (0x00000000) +#define NVA06F_SET_OBJECT_NVCLASS 15:0 +#define NVA06F_SET_OBJECT_ENGINE 20:16 +#define NVA06F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVA06F_ILLEGAL (0x00000004) +#define NVA06F_ILLEGAL_HANDLE 31:0 +#define NVA06F_NOP (0x00000008) +#define NVA06F_NOP_HANDLE 31:0 +#define NVA06F_SEMAPHOREA (0x00000010) +#define NVA06F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVA06F_SEMAPHOREB (0x00000014) +#define NVA06F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVA06F_SEMAPHOREC (0x00000018) +#define NVA06F_SEMAPHOREC_PAYLOAD 31:0 +#define NVA06F_SEMAPHORED (0x0000001C) +#define NVA06F_SEMAPHORED_OPERATION 3:0 +#define NVA06F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVA06F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVA06F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVA06F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVA06F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVA06F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVA06F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVA06F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVA06F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVA06F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVA06F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVA06F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVA06F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVA06F_NON_STALL_INTERRUPT (0x00000020) +#define NVA06F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVA06F_FB_FLUSH (0x00000024) +#define NVA06F_FB_FLUSH_HANDLE 31:0 +#define NVA06F_MEM_OP_A (0x00000028) +#define NVA06F_MEM_OP_A_OPERAND_LOW 31:2 +#define NVA06F_MEM_OP_A_TLB_INVALIDATE_ADDR 29:2 +#define NVA06F_MEM_OP_A_TLB_INVALIDATE_TARGET 31:30 +#define NVA06F_MEM_OP_A_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000 +#define NVA06F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002 +#define NVA06F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 +#define NVA06F_MEM_OP_B (0x0000002c) +#define NVA06F_MEM_OP_B_OPERAND_HIGH 7:0 +#define NVA06F_MEM_OP_B_OPERATION 31:27 +#define NVA06F_MEM_OP_B_OPERATION_SYSMEMBAR_FLUSH 0x00000005 +#define NVA06F_MEM_OP_B_OPERATION_SOFT_FLUSH 0x00000006 +#define NVA06F_MEM_OP_B_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVA06F_MEM_OP_B_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NVA06F_MEM_OP_B_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +#define NVA06F_MEM_OP_B_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVA06F_MEM_OP_B_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB 0:0 +#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ALL 0x00000001 +#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC 1:1 +#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVA06F_SET_REFERENCE (0x00000050) +#define NVA06F_SET_REFERENCE_COUNT 31:0 +#define NVA06F_CRC_CHECK (0x0000007c) +#define NVA06F_CRC_CHECK_VALUE 31:0 +#define NVA06F_YIELD (0x00000080) +#define NVA06F_YIELD_OP 1:0 +#define NVA06F_YIELD_OP_NOP 0x00000000 + + +/* GPFIFO entry format */ +#define NVA06F_GP_ENTRY__SIZE 8 +#define NVA06F_GP_ENTRY0_FETCH 0:0 +#define NVA06F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVA06F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVA06F_GP_ENTRY0_GET 31:2 +#define NVA06F_GP_ENTRY0_OPERAND 31:0 +#define NVA06F_GP_ENTRY1_GET_HI 7:0 +#define NVA06F_GP_ENTRY1_PRIV 8:8 +#define NVA06F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NVA06F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NVA06F_GP_ENTRY1_LEVEL 9:9 +#define NVA06F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVA06F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVA06F_GP_ENTRY1_LENGTH 30:10 +#define NVA06F_GP_ENTRY1_SYNC 31:31 +#define NVA06F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVA06F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVA06F_GP_ENTRY1_OPCODE 7:0 +#define NVA06F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVA06F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVA06F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVA06F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVA06F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVA06F_DMA_METHOD_ADDRESS 11:0 +#define NVA06F_DMA_SUBDEVICE_MASK 15:4 +#define NVA06F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVA06F_DMA_TERT_OP 17:16 +#define NVA06F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVA06F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVA06F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVA06F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVA06F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVA06F_DMA_METHOD_COUNT_OLD 28:18 +#define NVA06F_DMA_METHOD_COUNT 28:16 +#define NVA06F_DMA_IMMD_DATA 28:16 +#define NVA06F_DMA_SEC_OP 31:29 +#define NVA06F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVA06F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVA06F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVA06F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVA06F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVA06F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVA06F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVA06F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVA06F_DMA_INCR_ADDRESS 11:0 +#define NVA06F_DMA_INCR_SUBCHANNEL 15:13 +#define NVA06F_DMA_INCR_COUNT 28:16 +#define NVA06F_DMA_INCR_OPCODE 31:29 +#define NVA06F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVA06F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVA06F_DMA_NONINCR_ADDRESS 11:0 +#define NVA06F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVA06F_DMA_NONINCR_COUNT 28:16 +#define NVA06F_DMA_NONINCR_OPCODE 31:29 +#define NVA06F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVA06F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVA06F_DMA_ONEINCR_ADDRESS 11:0 +#define NVA06F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVA06F_DMA_ONEINCR_COUNT 28:16 +#define NVA06F_DMA_ONEINCR_OPCODE 31:29 +#define NVA06F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVA06F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVA06F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVA06F_DMA_IMMD_ADDRESS 11:0 +#define NVA06F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVA06F_DMA_IMMD_DATA 28:16 +#define NVA06F_DMA_IMMD_OPCODE 31:29 +#define NVA06F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVA06F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVA06F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA06F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVA06F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVA06F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA06F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVA06F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA06F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVA06F_DMA_ENDSEG_OPCODE 31:29 +#define NVA06F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVA06F_DMA_ADDRESS 12:2 +#define NVA06F_DMA_SUBCH 15:13 +#define NVA06F_DMA_OPCODE3 17:16 +#define NVA06F_DMA_OPCODE3_NONE (0x00000000) +#define NVA06F_DMA_COUNT 28:18 +#define NVA06F_DMA_OPCODE 31:29 +#define NVA06F_DMA_OPCODE_METHOD (0x00000000) +#define NVA06F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVA06F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clA06F_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cla06fsubch.h b/userspace/sdks/nv525/nvidia/inc/class/cla06fsubch.h new file mode 100644 index 0000000..330a681 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cla06fsubch.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cla06fsubch_h_ +#define _cla06fsubch_h_ + +#define NVA06F_SUBCHANNEL_2D 3 +#define NVA06F_SUBCHANNEL_3D 0 +#define NVA06F_SUBCHANNEL_COMPUTE 1 +#define NVA06F_SUBCHANNEL_COPY_ENGINE 4 +#define NVA06F_SUBCHANNEL_I2M 2 + +#endif // _cla06fsubch_h_ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cla06fsw.h b/userspace/sdks/nv525/nvidia/inc/class/cla06fsw.h new file mode 100644 index 0000000..99c3b8a --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cla06fsw.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cla06f_sw_h_ +#define _cla06f_sw_h_ + +#define NVA06F_NOTIFIERS_RC (0) +#define NVA06F_NOTIFIERS_REFCNT (1) +#define NVA06F_NOTIFIERS_NONSTALL (2) +#define NVA06F_NOTIFIERS_EVENTBUFFER (3) +#define NVA06F_NOTIFIERS_IDLECHANNEL (4) +#define NVA06F_NOTIFIERS_ENDCTX (5) +#define NVA06F_NOTIFIERS_SW (6) +#define NVA06F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVA06F_NOTIFIERS_MAXCOUNT (8) + +/* NvNotification[] fields and values */ +#define NVA06F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVA06F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _cla06f_sw_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cla081.h b/userspace/sdks/nv525/nvidia/inc/class/cla081.h new file mode 100644 index 0000000..d17271a --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cla081.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cla081_h_ +#define _cla081_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVA081_VGPU_CONFIG (0x0000a081) + +/*event values*/ +#define NVA081_NOTIFIERS_EVENT_VGPU_GUEST_CREATED (0) +#define NVA081_NOTIFIERS_EVENT_VGPU_GUEST_INITIALISING (1) +#define NVA081_NOTIFIERS_EVENT_VGPU_GUEST_DESTROYED (2) +#define NVA081_NOTIFIERS_MAXCOUNT (5) + + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cla081_h diff --git a/userspace/sdks/nv525/nvidia/inc/class/cla084.h b/userspace/sdks/nv525/nvidia/inc/class/cla084.h new file mode 100644 index 0000000..a224c6d --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cla084.h @@ -0,0 +1,77 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cla084.finn +// + +#include "nv_vgpu_types.h" +#include "cla084_notification.h" + +#define NVA084_KERNEL_HOST_VGPU_DEVICE (0xa084U) /* finn: Evaluated from "NVA084_ALLOC_PARAMETERS_MESSAGE_ID" */ + +#define NVA084_MAX_VMMU_SEGMENTS 384 + +/* + * NVA084_ALLOC_PARAMETERS + * + * This structure represents vGPU host device KERNEL object allocation parameters. + * dbdf -> domain (31:16), bus (15:8), device (7:3), function (2:0) + * gfid -> Used only when SRIOV is enabled otherwise set to 0. + * swizzId [IN/OUT] -> Used only when MIG mode is enabled otherwise set + * to NV2080_CTRL_GPU_PARTITION_ID_INVALID. + * numChannels -> Used only when SRIOV is enabled. Must be a power of 2. + * bDisableDefaultSmcExecPartRestore - If set to true, SMC default execution partition + * save/restore will not be done in host-RM + * vgpuDeviceInstanceId -> Specifies the vGPU device instance per VM to be used + * for supporting multiple vGPUs per VM. + * numGuestFbHandles -> number of guest memory handles + * guestFbHandleList -> handle list to guest memory + * hPluginHeapMemory -> plugin heap memory handle + * bDeviceProfilingEnabled -> If set to true, profiling is allowed + */ +#define NVA084_ALLOC_PARAMETERS_MESSAGE_ID (0xa084U) + +typedef struct NVA084_ALLOC_PARAMETERS { + NvU32 dbdf; + NvU32 gfid; + NvU32 swizzId; + NvU32 vgpuType; + NvU32 vmPid; + NvU32 numChannels; + NvU32 numPluginChannels; + VM_ID_TYPE vmIdType; + NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); + NvBool bDisableDefaultSmcExecPartRestore; + NvU32 vgpuDeviceInstanceId; + NvU32 numGuestFbHandles; + NvHandle guestFbHandleList[NVA084_MAX_VMMU_SEGMENTS]; + NvHandle hPluginHeapMemory; + NV_DECLARE_ALIGNED(NvU64 ctrlBuffOffset, 8); + NvBool bDeviceProfilingEnabled; +} NVA084_ALLOC_PARAMETERS; diff --git a/userspace/sdks/nv525/nvidia/inc/class/cla084_notification.h b/userspace/sdks/nv525/nvidia/inc/class/cla084_notification.h new file mode 100644 index 0000000..da2ec5b --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cla084_notification.h @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cla084_notification_h_ +#define _cla084_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +// +// @todo: We will define the actual event values later based on the use case. +// These event values are only for Test purpose. +// +/* event values */ +#define NVA084_NOTIFIERS_EVENT_VGPU_PLUGIN_TASK_BOOTLOADED (0) +#define NVA084_NOTIFIERS_EVENT_VGPU_PLUGIN_TASK_UNLOADED (1) +#define NVA084_NOTIFIERS_EVENT_VGPU_PLUGIN_TASK_CRASHED (2) +#define NVA084_NOTIFIERS_EVENT_GUEST_DRIVER_LOADED (3) +#define NVA084_NOTIFIERS_EVENT_GUEST_DRIVER_UNLOADED (4) +#define NVA084_NOTIFIERS_MAXCOUNT (5) + +#define NVA084_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NVA084_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000) +#define NVA084_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000) +#define NVA084_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000) +#define NVA084_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cla084_notification_h_ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cla097.h b/userspace/sdks/nv525/nvidia/inc/class/cla097.h new file mode 100644 index 0000000..9ebbcfd --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cla097.h @@ -0,0 +1,3817 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_kepler_a_h_ +#define _cl_kepler_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl kepler_a */ + +#include "nvtypes.h" + +#define KEPLER_A 0xA097 + +#define NVA097_SET_OBJECT 0x0000 +#define NVA097_SET_OBJECT_CLASS_ID 15:0 +#define NVA097_SET_OBJECT_ENGINE_ID 20:16 + +#define NVA097_NO_OPERATION 0x0100 +#define NVA097_NO_OPERATION_V 31:0 + +#define NVA097_SET_NOTIFY_A 0x0104 +#define NVA097_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVA097_SET_NOTIFY_B 0x0108 +#define NVA097_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVA097_NOTIFY 0x010c +#define NVA097_NOTIFY_TYPE 31:0 +#define NVA097_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVA097_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVA097_WAIT_FOR_IDLE 0x0110 +#define NVA097_WAIT_FOR_IDLE_V 31:0 + +#define NVA097_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVA097_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVA097_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVA097_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVA097_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVA097_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVA097_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVA097_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVA097_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVA097_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVA097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVA097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVA097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVA097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVA097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVA097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVA097_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVA097_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVA097_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA097_SEND_GO_IDLE 0x013c +#define NVA097_SEND_GO_IDLE_V 31:0 + +#define NVA097_PM_TRIGGER 0x0140 +#define NVA097_PM_TRIGGER_V 31:0 + +#define NVA097_PM_TRIGGER_WFI 0x0144 +#define NVA097_PM_TRIGGER_WFI_V 31:0 + +#define NVA097_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVA097_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVA097_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVA097_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVA097_LINE_LENGTH_IN 0x0180 +#define NVA097_LINE_LENGTH_IN_VALUE 31:0 + +#define NVA097_LINE_COUNT 0x0184 +#define NVA097_LINE_COUNT_VALUE 31:0 + +#define NVA097_OFFSET_OUT_UPPER 0x0188 +#define NVA097_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVA097_OFFSET_OUT 0x018c +#define NVA097_OFFSET_OUT_VALUE 31:0 + +#define NVA097_PITCH_OUT 0x0190 +#define NVA097_PITCH_OUT_VALUE 31:0 + +#define NVA097_SET_DST_BLOCK_SIZE 0x0194 +#define NVA097_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVA097_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVA097_SET_DST_WIDTH 0x0198 +#define NVA097_SET_DST_WIDTH_V 31:0 + +#define NVA097_SET_DST_HEIGHT 0x019c +#define NVA097_SET_DST_HEIGHT_V 31:0 + +#define NVA097_SET_DST_DEPTH 0x01a0 +#define NVA097_SET_DST_DEPTH_V 31:0 + +#define NVA097_SET_DST_LAYER 0x01a4 +#define NVA097_SET_DST_LAYER_V 31:0 + +#define NVA097_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVA097_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVA097_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVA097_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVA097_LAUNCH_DMA 0x01b0 +#define NVA097_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVA097_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA097_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA097_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVA097_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVA097_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVA097_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVA097_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVA097_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVA097_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVA097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVA097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVA097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVA097_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVA097_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA097_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA097_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA097_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVA097_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA097_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA097_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVA097_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVA097_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVA097_LOAD_INLINE_DATA 0x01b4 +#define NVA097_LOAD_INLINE_DATA_V 31:0 + +#define NVA097_SET_I2M_SEMAPHORE_A 0x01dc +#define NVA097_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVA097_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVA097_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA097_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVA097_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVA097_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVA097_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVA097_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVA097_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVA097_SET_I2M_SPARE_NOOP03 0x01fc +#define NVA097_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVA097_RUN_DS_NOW 0x0200 +#define NVA097_RUN_DS_NOW_V 31:0 + +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVA097_SET_RASTER_PIPE_SYNC_CONTROL 0x0208 +#define NVA097_SET_RASTER_PIPE_SYNC_CONTROL_PRIM_AREA_THRESHOLD 21:0 +#define NVA097_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE 24:24 +#define NVA097_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE_FALSE 0x00000000 +#define NVA097_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVA097_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVA097_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVA097_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVA097_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVA097_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_GS_DM_FIFO 0x0214 +#define NVA097_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVA097_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVA097_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVA097_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVA097_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA097_INVALIDATE_SHADER_CACHES 0x021c +#define NVA097_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVA097_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVA097_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVA097_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVA097_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVA097_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVA097_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVA097_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVA097_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVA097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVA097_SET_VAB_VERTEX3F(i) (0x0220+(i)*4) +#define NVA097_SET_VAB_VERTEX3F_V 31:0 + +#define NVA097_SET_VAB_VERTEX4F(i) (0x0230+(i)*4) +#define NVA097_SET_VAB_VERTEX4F_V 31:0 + +#define NVA097_SET_VAB_NORMAL3F(i) (0x0240+(i)*4) +#define NVA097_SET_VAB_NORMAL3F_V 31:0 + +#define NVA097_SET_VAB_COLOR3F(i) (0x0250+(i)*4) +#define NVA097_SET_VAB_COLOR3F_V 31:0 + +#define NVA097_SET_VAB_COLOR4F(i) (0x0260+(i)*4) +#define NVA097_SET_VAB_COLOR4F_V 31:0 + +#define NVA097_SET_VAB_COLOR4UB(i) (0x0270+(i)*4) +#define NVA097_SET_VAB_COLOR4UB_V 31:0 + +#define NVA097_SET_VAB_TEX_COORD1F(i) (0x0280+(i)*4) +#define NVA097_SET_VAB_TEX_COORD1F_V 31:0 + +#define NVA097_SET_VAB_TEX_COORD2F(i) (0x0290+(i)*4) +#define NVA097_SET_VAB_TEX_COORD2F_V 31:0 + +#define NVA097_SET_VAB_TEX_COORD3F(i) (0x02a0+(i)*4) +#define NVA097_SET_VAB_TEX_COORD3F_V 31:0 + +#define NVA097_SET_VAB_TEX_COORD4F(i) (0x02b0+(i)*4) +#define NVA097_SET_VAB_TEX_COORD4F_V 31:0 + +#define NVA097_SET_TASK_CIRCULAR_BUFFER_THROTTLE 0x02cc +#define NVA097_SET_TASK_CIRCULAR_BUFFER_THROTTLE_TASK_COUNT 21:0 + +#define NVA097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NVA097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NVA097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVA097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVA097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVA097_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 9:0 + +#define NVA097_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVA097_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVA097_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVA097_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVA097_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVA097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVA097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVA097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVA097_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVA097_SET_ZCULL_SUBREGION 0x02e8 +#define NVA097_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVA097_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVA097_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVA097_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVA097_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVA097_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVA097_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVA097_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVA097_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVA097_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVA097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVA097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVA097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVA097_DRAW_ZERO_INDEX 0x0304 +#define NVA097_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVA097_SET_L1_CONFIGURATION 0x0308 +#define NVA097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVA097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVA097_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVA097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVA097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVA097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVA097_SET_SPA_VERSION 0x0310 +#define NVA097_SET_SPA_VERSION_MINOR 7:0 +#define NVA097_SET_SPA_VERSION_MAJOR 15:8 + +#define NVA097_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NVA097_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NVA097_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_SNAP_GRID_LINE 0x0318 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVA097_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVA097_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVA097_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVA097_SET_SNAP_GRID_NON_LINE 0x031c +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVA097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVA097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVA097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVA097_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVA097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVA097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVA097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVA097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVA097_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVA097_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVA097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVA097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVA097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVA097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVA097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVA097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVA097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVA097_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVA097_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVA097_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVA097_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVA097_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVA097_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVA097_SET_TESSELLATION_LOD_V1 0x0330 +#define NVA097_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVA097_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVA097_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVA097_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVA097_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVA097_RESERVED_TG07 0x033c +#define NVA097_RESERVED_TG07_V 0:0 + +#define NVA097_RESERVED_TG08 0x0340 +#define NVA097_RESERVED_TG08_V 0:0 + +#define NVA097_RESERVED_TG09 0x0344 +#define NVA097_RESERVED_TG09_V 0:0 + +#define NVA097_RESERVED_TG10 0x0348 +#define NVA097_RESERVED_TG10_V 0:0 + +#define NVA097_RESERVED_TG11 0x034c +#define NVA097_RESERVED_TG11_V 0:0 + +#define NVA097_RESERVED_TG12 0x0350 +#define NVA097_RESERVED_TG12_V 0:0 + +#define NVA097_RESERVED_TG13 0x0354 +#define NVA097_RESERVED_TG13_V 0:0 + +#define NVA097_RESERVED_TG14 0x0358 +#define NVA097_RESERVED_TG14_V 0:0 + +#define NVA097_RESERVED_TG15 0x035c +#define NVA097_RESERVED_TG15_V 0:0 + +#define NVA097_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVA097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVA097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVA097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVA097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVA097_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVA097_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVA097_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVA097_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVA097_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVA097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVA097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVA097_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVA097_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVA097_SET_RASTER_ENABLE 0x037c +#define NVA097_SET_RASTER_ENABLE_V 0:0 +#define NVA097_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVA097_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVA097_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVA097_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVA097_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVA097_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVA097_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVA097_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVA097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVA097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVA097_SET_VAB_DATA_TYPELESS(i) (0x0400+(i)*4) +#define NVA097_SET_VAB_DATA_TYPELESS_V 31:0 + +#define NVA097_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVA097_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVA097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVA097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVA097_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVA097_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVA097_SET_RASTER_INPUT 0x0740 +#define NVA097_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVA097_SET_STREAM_OUTPUT 0x0744 +#define NVA097_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVA097_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVA097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVA097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_ALPHA_FRACTION 0x074c +#define NVA097_SET_ALPHA_FRACTION_V 7:0 + +#define NVA097_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVA097_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVA097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVA097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVA097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 + +#define NVA097_SET_MAX_TI_WARPS_PER_BATCH 0x075c +#define NVA097_SET_MAX_TI_WARPS_PER_BATCH_V 5:0 + +#define NVA097_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVA097_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA097_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVA097_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVA097_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVA097_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVA097_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVA097_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVA097_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVA097_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVA097_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVA097_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVA097_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVA097_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVA097_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVA097_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVA097_SET_ISBE_SAVE_RESTORE_PROGRAM 0x07ac +#define NVA097_SET_ISBE_SAVE_RESTORE_PROGRAM_OFFSET 31:0 + +#define NVA097_SET_VAB_VERTEX2F(i) (0x07b0+(i)*4) +#define NVA097_SET_VAB_VERTEX2F_V 31:0 + +#define NVA097_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVA097_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVA097_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVA097_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVA097_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVA097_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVA097_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVA097_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVA097_SET_CULL_BEFORE_FETCH 0x07dc +#define NVA097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVA097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVA097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVA097_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVA097_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVA097_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVA097_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVA097_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVA097_SET_ZCULL_STORAGE_A 0x07e8 +#define NVA097_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVA097_SET_ZCULL_STORAGE_B 0x07ec +#define NVA097_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVA097_SET_ZCULL_STORAGE_C 0x07f0 +#define NVA097_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVA097_SET_ZCULL_STORAGE_D 0x07f4 +#define NVA097_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVA097_SET_ZT_READ_ONLY 0x07f8 +#define NVA097_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVA097_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVA097_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVA097_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVA097_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVA097_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVA097_SET_TEXTURE_INSTRUCTION_OPERAND 0x07fc +#define NVA097_SET_TEXTURE_INSTRUCTION_OPERAND_ORDERING 0:0 +#define NVA097_SET_TEXTURE_INSTRUCTION_OPERAND_ORDERING_FERMI_ORDER 0x00000000 +#define NVA097_SET_TEXTURE_INSTRUCTION_OPERAND_ORDERING_KEPLER_ORDER 0x00000001 + +#define NVA097_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVA097_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVA097_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVA097_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVA097_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVA097_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVA097_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVA097_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVA097_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVA097_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVA097_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVA097_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVA097_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVA097_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVA097_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVA097_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVA097_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVA097_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVA097_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA097_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVA097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVA097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVA097_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVA097_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVA097_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVA097_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVA097_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVA097_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVA097_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NVA097_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NVA097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVA097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVA097_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVA097_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVA097_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVA097_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVA097_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVA097_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVA097_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVA097_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVA097_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVA097_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVA097_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVA097_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVA097_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVA097_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVA097_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVA097_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVA097_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVA097_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVA097_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVA097_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVA097_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVA097_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVA097_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVA097_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVA097_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVA097_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVA097_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVA097_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVA097_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVA097_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVA097_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVA097_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVA097_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVA097_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVA097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVA097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVA097_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVA097_SET_STATISTICS_COUNTER 0x0d68 +#define NVA097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVA097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVA097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVA097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVA097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVA097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVA097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVA097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVA097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVA097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVA097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVA097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVA097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVA097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVA097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVA097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVA097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVA097_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVA097_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVA097_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVA097_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVA097_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVA097_SET_VERTEX_ARRAY_START 0x0d74 +#define NVA097_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVA097_DRAW_VERTEX_ARRAY 0x0d78 +#define NVA097_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVA097_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVA097_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVA097_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVA097_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVA097_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVA097_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVA097_SET_Z_CLEAR_VALUE 0x0d90 +#define NVA097_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVA097_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVA097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVA097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVA097_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVA097_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVA097_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVA097_SET_FRONT_POLYGON_MODE 0x0dac +#define NVA097_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVA097_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVA097_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVA097_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVA097_SET_BACK_POLYGON_MODE 0x0db0 +#define NVA097_SET_BACK_POLYGON_MODE_V 31:0 +#define NVA097_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVA097_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVA097_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVA097_SET_POLY_SMOOTH 0x0db4 +#define NVA097_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVA097_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVA097_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_ZT_MARK 0x0db8 +#define NVA097_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NVA097_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVA097_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVA097_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVA097_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVA097_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVA097_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVA097_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVA097_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVA097_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVA097_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVA097_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVA097_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_PATCH 0x0dcc +#define NVA097_SET_PATCH_SIZE 7:0 + +#define NVA097_SET_ZCULL_CRITERION 0x0dd8 +#define NVA097_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVA097_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVA097_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVA097_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVA097_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVA097_SET_ZCULL_CRITERION_SREF 23:16 +#define NVA097_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVA097_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVA097_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVA097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVA097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVA097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE 0x0dec +#define NVA097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE 0:0 +#define NVA097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_WINDOW_OFFSET_X 0x0df8 +#define NVA097_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVA097_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVA097_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVA097_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVA097_SET_SCISSOR_ENABLE_V 0:0 +#define NVA097_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVA097_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVA097_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVA097_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVA097_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVA097_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVA097_SET_VAB_NORMAL3S(i) (0x0f00+(i)*4) +#define NVA097_SET_VAB_NORMAL3S_V 31:0 + +#define NVA097_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVA097_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVA097_SET_BACK_STENCIL_MASK 0x0f58 +#define NVA097_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVA097_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVA097_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVA097_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVA097_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVA097_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVA097_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVA097_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVA097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVA097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVA097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVA097_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVA097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVA097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVA097_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVA097_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVA097_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVA097_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVA097_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVA097_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVA097_SET_CT_MRT_ENABLE 0x0fac +#define NVA097_SET_CT_MRT_ENABLE_V 0:0 +#define NVA097_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVA097_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVA097_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVA097_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVA097_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVA097_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVA097_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVA097_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVA097_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVA097_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVA097_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVA097_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVA097_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVA097_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVA097_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVA097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVA097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVA097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVA097_SET_ZT_A 0x0fe0 +#define NVA097_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_ZT_B 0x0fe4 +#define NVA097_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_ZT_FORMAT 0x0fe8 +#define NVA097_SET_ZT_FORMAT_V 4:0 +#define NVA097_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVA097_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVA097_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVA097_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVA097_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVA097_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVA097_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVA097_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVA097_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVA097_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVA097_SET_ZT_BLOCK_SIZE 0x0fec +#define NVA097_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVA097_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA097_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVA097_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVA097_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVA097_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVA097_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVA097_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVA097_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVA097_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVA097_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVA097_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA097_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVA097_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVA097_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVA097_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVA097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVA097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVA097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVA097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVA097_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVA097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVA097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVA097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVA097_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVA097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVA097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_SPARE_NOOP00 0x1040 +#define NVA097_SET_SPARE_NOOP00_V 31:0 + +#define NVA097_SET_SPARE_NOOP01 0x1044 +#define NVA097_SET_SPARE_NOOP01_V 31:0 + +#define NVA097_SET_SPARE_NOOP02 0x1048 +#define NVA097_SET_SPARE_NOOP02_V 31:0 + +#define NVA097_SET_SPARE_NOOP03 0x104c +#define NVA097_SET_SPARE_NOOP03_V 31:0 + +#define NVA097_SET_SPARE_NOOP04 0x1050 +#define NVA097_SET_SPARE_NOOP04_V 31:0 + +#define NVA097_SET_SPARE_NOOP05 0x1054 +#define NVA097_SET_SPARE_NOOP05_V 31:0 + +#define NVA097_SET_SPARE_NOOP06 0x1058 +#define NVA097_SET_SPARE_NOOP06_V 31:0 + +#define NVA097_SET_SPARE_NOOP07 0x105c +#define NVA097_SET_SPARE_NOOP07_V 31:0 + +#define NVA097_SET_SPARE_NOOP08 0x1060 +#define NVA097_SET_SPARE_NOOP08_V 31:0 + +#define NVA097_SET_SPARE_NOOP09 0x1064 +#define NVA097_SET_SPARE_NOOP09_V 31:0 + +#define NVA097_SET_SPARE_NOOP10 0x1068 +#define NVA097_SET_SPARE_NOOP10_V 31:0 + +#define NVA097_SET_SPARE_NOOP11 0x106c +#define NVA097_SET_SPARE_NOOP11_V 31:0 + +#define NVA097_SET_SPARE_NOOP12 0x1070 +#define NVA097_SET_SPARE_NOOP12_V 31:0 + +#define NVA097_SET_SPARE_NOOP13 0x1074 +#define NVA097_SET_SPARE_NOOP13_V 31:0 + +#define NVA097_SET_SPARE_NOOP14 0x1078 +#define NVA097_SET_SPARE_NOOP14_V 31:0 + +#define NVA097_SET_SPARE_NOOP15 0x107c +#define NVA097_SET_SPARE_NOOP15_V 31:0 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVA097_UNBIND_ALL 0x10f4 +#define NVA097_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVA097_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVA097_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVA097_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA097_NO_OPERATION_DATA_HI 0x110c +#define NVA097_NO_OPERATION_DATA_HI_V 31:0 + +#define NVA097_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVA097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVA097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVA097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVA097_PM_TRIGGER_END 0x1114 +#define NVA097_PM_TRIGGER_END_V 31:0 + +#define NVA097_SET_VERTEX_ID_BASE 0x1118 +#define NVA097_SET_VERTEX_ID_BASE_V 31:0 + +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVA097_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVA097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVA097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVA097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVA097_FLUSH_PENDING_WRITES 0x1144 +#define NVA097_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVA097_SET_VAB_DATA_CONTROL 0x114c +#define NVA097_SET_VAB_DATA_CONTROL_VAB_INDEX 7:0 +#define NVA097_SET_VAB_DATA_CONTROL_COMPONENT_COUNT 10:8 +#define NVA097_SET_VAB_DATA_CONTROL_COMPONENT_BYTE_WIDTH 14:12 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT 18:16 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_SNORM 0x00000001 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_UNORM 0x00000002 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_SINT 0x00000003 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_UINT 0x00000004 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_USCALED 0x00000005 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_SSCALED 0x00000006 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_FLOAT 0x00000007 + +#define NVA097_SET_VAB_DATA(i) (0x1150+(i)*4) +#define NVA097_SET_VAB_DATA_V 31:0 + +#define NVA097_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVA097_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVA097_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVA097_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_SET_CT_SELECT 0x121c +#define NVA097_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVA097_SET_CT_SELECT_TARGET0 6:4 +#define NVA097_SET_CT_SELECT_TARGET1 9:7 +#define NVA097_SET_CT_SELECT_TARGET2 12:10 +#define NVA097_SET_CT_SELECT_TARGET3 15:13 +#define NVA097_SET_CT_SELECT_TARGET4 18:16 +#define NVA097_SET_CT_SELECT_TARGET5 21:19 +#define NVA097_SET_CT_SELECT_TARGET6 24:22 +#define NVA097_SET_CT_SELECT_TARGET7 27:25 + +#define NVA097_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVA097_SET_ZT_SIZE_A 0x1228 +#define NVA097_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVA097_SET_ZT_SIZE_B 0x122c +#define NVA097_SET_ZT_SIZE_B_HEIGHT 16:0 + +#define NVA097_SET_ZT_SIZE_C 0x1230 +#define NVA097_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVA097_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVA097_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVA097_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVA097_SET_SAMPLER_BINDING 0x1234 +#define NVA097_SET_SAMPLER_BINDING_V 0:0 +#define NVA097_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVA097_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVA097_DRAW_AUTO 0x123c +#define NVA097_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVA097_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVA097_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 9:0 + +#define NVA097_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVA097_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVA097_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVA097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVA097_SET_SHADER_SCHEDULING 0x12ac +#define NVA097_SET_SHADER_SCHEDULING_MODE 0:0 +#define NVA097_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 +#define NVA097_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 + +#define NVA097_CLEAR_ZCULL_REGION 0x12c8 +#define NVA097_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVA097_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVA097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVA097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVA097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVA097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVA097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVA097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVA097_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVA097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVA097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVA097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVA097_SET_DEPTH_TEST 0x12cc +#define NVA097_SET_DEPTH_TEST_ENABLE 0:0 +#define NVA097_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_FILL_MODE 0x12d0 +#define NVA097_SET_FILL_MODE_V 31:0 +#define NVA097_SET_FILL_MODE_V_POINT 0x00000001 +#define NVA097_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVA097_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVA097_SET_SHADE_MODE 0x12d4 +#define NVA097_SET_SHADE_MODE_V 31:0 +#define NVA097_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVA097_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVA097_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVA097_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVA097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVA097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVA097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVA097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVA097_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVA097_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVA097_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVA097_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_DEPTH_WRITE 0x12e8 +#define NVA097_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVA097_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_ALPHA_TEST 0x12ec +#define NVA097_SET_ALPHA_TEST_ENABLE 0:0 +#define NVA097_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVA097_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVA097_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVA097_DRAW_INLINE_INDEX4X8 0x1304 +#define NVA097_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVA097_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVA097_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVA097_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVA097_D3D_SET_CULL_MODE 0x1308 +#define NVA097_D3D_SET_CULL_MODE_V 31:0 +#define NVA097_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVA097_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVA097_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVA097_SET_DEPTH_FUNC 0x130c +#define NVA097_SET_DEPTH_FUNC_V 31:0 +#define NVA097_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVA097_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVA097_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA097_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA097_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVA097_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA097_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA097_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA097_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVA097_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVA097_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA097_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA097_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVA097_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA097_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA097_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA097_SET_ALPHA_REF 0x1310 +#define NVA097_SET_ALPHA_REF_V 31:0 + +#define NVA097_SET_ALPHA_FUNC 0x1314 +#define NVA097_SET_ALPHA_FUNC_V 31:0 +#define NVA097_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVA097_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVA097_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA097_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA097_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVA097_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA097_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA097_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA097_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVA097_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVA097_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA097_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA097_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVA097_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA097_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA097_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA097_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVA097_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVA097_SET_BLEND_CONST_RED 0x131c +#define NVA097_SET_BLEND_CONST_RED_V 31:0 + +#define NVA097_SET_BLEND_CONST_GREEN 0x1320 +#define NVA097_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVA097_SET_BLEND_CONST_BLUE 0x1324 +#define NVA097_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVA097_SET_BLEND_CONST_ALPHA 0x1328 +#define NVA097_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVA097_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVA097_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVA097_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVA097_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVA097_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVA097_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVA097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVA097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVA097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_BLEND_COLOR_OP 0x1340 +#define NVA097_SET_BLEND_COLOR_OP_V 31:0 +#define NVA097_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA097_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA097_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA097_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVA097_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVA097_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVA097_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA097_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA097_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVA097_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_BLEND_ALPHA_OP 0x134c +#define NVA097_SET_BLEND_ALPHA_OP_V 31:0 +#define NVA097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA097_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVA097_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVA097_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVA097_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA097_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA097_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVA097_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVA097_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVA097_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVA097_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_SINGLE_ROP_CONTROL 0x135c +#define NVA097_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVA097_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_BLEND(i) (0x1360+(i)*4) +#define NVA097_SET_BLEND_ENABLE 0:0 +#define NVA097_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVA097_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_STENCIL_TEST 0x1380 +#define NVA097_SET_STENCIL_TEST_ENABLE 0:0 +#define NVA097_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_STENCIL_OP_FAIL 0x1384 +#define NVA097_SET_STENCIL_OP_FAIL_V 31:0 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVA097_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVA097_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVA097_SET_STENCIL_OP_ZPASS 0x138c +#define NVA097_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVA097_SET_STENCIL_FUNC 0x1390 +#define NVA097_SET_STENCIL_FUNC_V 31:0 +#define NVA097_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVA097_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVA097_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA097_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA097_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVA097_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA097_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA097_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA097_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVA097_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVA097_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA097_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA097_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVA097_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA097_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA097_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA097_SET_STENCIL_FUNC_REF 0x1394 +#define NVA097_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVA097_SET_STENCIL_FUNC_MASK 0x1398 +#define NVA097_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVA097_SET_STENCIL_MASK 0x139c +#define NVA097_SET_STENCIL_MASK_V 7:0 + +#define NVA097_SET_DRAW_AUTO_START 0x13a4 +#define NVA097_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVA097_SET_PS_SATURATE 0x13a8 +#define NVA097_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVA097_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVA097_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVA097_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVA097_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVA097_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVA097_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVA097_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVA097_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 + +#define NVA097_SET_WINDOW_ORIGIN 0x13ac +#define NVA097_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVA097_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVA097_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVA097_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVA097_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVA097_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVA097_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVA097_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVA097_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVA097_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVA097_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVA097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVA097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_ALPHA_HYSTERESIS 0x1420 +#define NVA097_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NVA097_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVA097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVA097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA097_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVA097_INVALIDATE_DA_DMA_CACHE 0x142c +#define NVA097_INVALIDATE_DA_DMA_CACHE_V 0:0 + +#define NVA097_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVA097_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVA097_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVA097_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVA097_SET_PS_WARP_WATERMARKS 0x1450 +#define NVA097_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVA097_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVA097_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVA097_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVA097_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVA097_STORE_ZCULL 0x1464 +#define NVA097_STORE_ZCULL_V 0:0 + +#define NVA097_LOAD_ZCULL 0x1500 +#define NVA097_LOAD_ZCULL_V 0:0 + +#define NVA097_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVA097_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVA097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVA097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVA097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVA097_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVA097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVA097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVA097_SET_USER_CLIP_ENABLE 0x1510 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVA097_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVA097_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVA097_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_POINT_SIZE 0x1518 +#define NVA097_SET_POINT_SIZE_V 31:0 + +#define NVA097_SET_ZCULL_STATS 0x151c +#define NVA097_SET_ZCULL_STATS_ENABLE 0:0 +#define NVA097_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_POINT_SPRITE 0x1520 +#define NVA097_SET_POINT_SPRITE_ENABLE 0:0 +#define NVA097_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_SHADER_EXCEPTIONS 0x1528 +#define NVA097_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVA097_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVA097_CLEAR_REPORT_VALUE 0x1530 +#define NVA097_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVA097_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVA097_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVA097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVA097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVA097_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVA097_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 + +#define NVA097_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVA097_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVA097_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_ZT_SELECT 0x1538 +#define NVA097_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVA097_SET_RENDER_ENABLE_A 0x1550 +#define NVA097_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_RENDER_ENABLE_B 0x1554 +#define NVA097_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_RENDER_ENABLE_C 0x1558 +#define NVA097_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVA097_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA097_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA097_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA097_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVA097_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVA097_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVA097_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVA097_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVA097_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVA097_SET_ANTI_ALIASED_LINE 0x1570 +#define NVA097_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVA097_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_TEX_HEADER_POOL_A 0x1574 +#define NVA097_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_TEX_HEADER_POOL_B 0x1578 +#define NVA097_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_TEX_HEADER_POOL_C 0x157c +#define NVA097_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVA097_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVA097_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVA097_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVA097_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVA097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVA097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVA097_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVA097_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVA097_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA097_SET_SRGB_WRITE 0x15b8 +#define NVA097_SET_SRGB_WRITE_ENABLE 0:0 +#define NVA097_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_DEPTH_BIAS 0x15bc +#define NVA097_SET_DEPTH_BIAS_V 31:0 + +#define NVA097_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVA097_SET_RT_LAYER 0x15cc +#define NVA097_SET_RT_LAYER_V 15:0 +#define NVA097_SET_RT_LAYER_CONTROL 16:16 +#define NVA097_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVA097_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVA097_SET_ANTI_ALIAS 0x15d0 +#define NVA097_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVA097_SET_EDGE_FLAG 0x15e4 +#define NVA097_SET_EDGE_FLAG_V 0:0 +#define NVA097_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVA097_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVA097_DRAW_INLINE_INDEX 0x15e8 +#define NVA097_DRAW_INLINE_INDEX_V 31:0 + +#define NVA097_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVA097_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVA097_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVA097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVA097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVA097_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVA097_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVA097_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVA097_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVA097_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVA097_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVA097_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVA097_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVA097_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVA097_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVA097_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVA097_SET_POINT_SPRITE_SELECT 0x1604 +#define NVA097_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVA097_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVA097_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVA097_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVA097_SET_PROGRAM_REGION_A 0x1608 +#define NVA097_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVA097_SET_PROGRAM_REGION_B 0x160c +#define NVA097_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVA097_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVA097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVA097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVA097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVA097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVA097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVA097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVA097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVA097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVA097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVA097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVA097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVA097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVA097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVA097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVA097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVA097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVA097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVA097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVA097_END 0x1614 +#define NVA097_END_V 0:0 + +#define NVA097_BEGIN 0x1618 +#define NVA097_BEGIN_OP 15:0 +#define NVA097_BEGIN_OP_POINTS 0x00000000 +#define NVA097_BEGIN_OP_LINES 0x00000001 +#define NVA097_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVA097_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVA097_BEGIN_OP_TRIANGLES 0x00000004 +#define NVA097_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVA097_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVA097_BEGIN_OP_QUADS 0x00000007 +#define NVA097_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVA097_BEGIN_OP_POLYGON 0x00000009 +#define NVA097_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVA097_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVA097_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_BEGIN_OP_PATCH 0x0000000E +#define NVA097_BEGIN_PRIMITIVE_ID 24:24 +#define NVA097_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVA097_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVA097_BEGIN_INSTANCE_ID 27:26 +#define NVA097_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVA097_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVA097_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVA097_BEGIN_SPLIT_MODE 30:29 +#define NVA097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVA097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVA097_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVA097_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 + +#define NVA097_SET_VERTEX_ID_COPY 0x161c +#define NVA097_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVA097_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVA097_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVA097_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVA097_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVA097_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVA097_LOAD_PRIMITIVE_ID 0x1624 +#define NVA097_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVA097_SET_SHADER_BASED_CULL 0x162c +#define NVA097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVA097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVA097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVA097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_CLASS_VERSION 0x1638 +#define NVA097_SET_CLASS_VERSION_CURRENT 15:0 +#define NVA097_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA097_SET_VAB_PAGE 0x163c +#define NVA097_SET_VAB_PAGE_READ_SELECT 0:0 +#define NVA097_SET_VAB_PAGE_READ_SELECT_PAGES_0_AND_1 0x00000000 +#define NVA097_SET_VAB_PAGE_READ_SELECT_PAGES_0_AND_2 0x00000001 + +#define NVA097_DRAW_INLINE_VERTEX 0x1640 +#define NVA097_DRAW_INLINE_VERTEX_V 31:0 + +#define NVA097_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVA097_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVA097_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVA097_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVA097_SET_DA_OUTPUT 0x164c +#define NVA097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVA097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVA097_SET_ANTI_ALIASED_POINT 0x1658 +#define NVA097_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVA097_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_POINT_CENTER_MODE 0x165c +#define NVA097_SET_POINT_CENTER_MODE_V 31:0 +#define NVA097_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVA097_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVA097_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVA097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVA097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVA097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVA097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVA097_SET_LINE_STIPPLE 0x166c +#define NVA097_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVA097_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVA097_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVA097_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVA097_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVA097_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVA097_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVA097_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVA097_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVA097_SET_PROVOKING_VERTEX 0x1684 +#define NVA097_SET_PROVOKING_VERTEX_V 0:0 +#define NVA097_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVA097_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVA097_SET_TWO_SIDED_LIGHT 0x1688 +#define NVA097_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVA097_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_POLYGON_STIPPLE 0x168c +#define NVA097_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVA097_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_SHADER_CONTROL 0x1690 +#define NVA097_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVA097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVA097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVA097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVA097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVA097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVA097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVA097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVA097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVA097_LAUNCH_VERTEX 0x169c +#define NVA097_LAUNCH_VERTEX_V 0:0 + +#define NVA097_CHECK_CLASS_VERSION 0x16a0 +#define NVA097_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVA097_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA097_SET_SPH_VERSION 0x16a4 +#define NVA097_SET_SPH_VERSION_CURRENT 15:0 +#define NVA097_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA097_CHECK_SPH_VERSION 0x16a8 +#define NVA097_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVA097_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVA097_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVA097_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVA097_SET_AAM_VERSION 0x1790 +#define NVA097_SET_AAM_VERSION_CURRENT 15:0 +#define NVA097_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA097_CHECK_AAM_VERSION 0x1794 +#define NVA097_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVA097_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA097_SET_ZT_LAYER 0x179c +#define NVA097_SET_ZT_LAYER_OFFSET 15:0 + +#define NVA097_SET_VAB_MEMORY_AREA_A 0x17bc +#define NVA097_SET_VAB_MEMORY_AREA_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_VAB_MEMORY_AREA_B 0x17c0 +#define NVA097_SET_VAB_MEMORY_AREA_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_VAB_MEMORY_AREA_C 0x17c4 +#define NVA097_SET_VAB_MEMORY_AREA_C_SIZE 1:0 +#define NVA097_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_64K 0x00000001 +#define NVA097_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_128K 0x00000002 +#define NVA097_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_256K 0x00000003 + +#define NVA097_SET_INDEX_BUFFER_A 0x17c8 +#define NVA097_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVA097_SET_INDEX_BUFFER_B 0x17cc +#define NVA097_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVA097_SET_INDEX_BUFFER_C 0x17d0 +#define NVA097_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVA097_SET_INDEX_BUFFER_D 0x17d4 +#define NVA097_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVA097_SET_INDEX_BUFFER_E 0x17d8 +#define NVA097_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVA097_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVA097_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVA097_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVA097_SET_INDEX_BUFFER_F 0x17dc +#define NVA097_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVA097_DRAW_INDEX_BUFFER 0x17e0 +#define NVA097_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVA097_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVA097_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVA097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVA097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVA097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVA097_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVA097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVA097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVA097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVA097_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVA097_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVA097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVA097_OGL_SET_CULL 0x1918 +#define NVA097_OGL_SET_CULL_ENABLE 0:0 +#define NVA097_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVA097_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVA097_OGL_SET_FRONT_FACE 0x191c +#define NVA097_OGL_SET_FRONT_FACE_V 31:0 +#define NVA097_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVA097_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVA097_OGL_SET_CULL_FACE 0x1920 +#define NVA097_OGL_SET_CULL_FACE_V 31:0 +#define NVA097_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVA097_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVA097_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVA097_SET_VIEWPORT_PIXEL 0x1924 +#define NVA097_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVA097_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVA097_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVA097_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVA097_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVA097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVA097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVA097_INVALIDATE_CONSTANT_BUFFER_CACHE 0x1930 +#define NVA097_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2 0:0 +#define NVA097_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_FALSE 0x00000000 +#define NVA097_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_TRUE 0x00000001 + +#define NVA097_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVA097_SET_USER_CLIP_OP 0x1940 +#define NVA097_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVA097_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVA097_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVA097_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVA097_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVA097_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVA097_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVA097_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVA097_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVA097_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVA097_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVA097_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVA097_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVA097_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVA097_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVA097_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVA097_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVA097_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVA097_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVA097_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVA097_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVA097_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVA097_INVALIDATE_ZCULL 0x1958 +#define NVA097_INVALIDATE_ZCULL_V 31:0 +#define NVA097_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVA097_SET_ZCULL 0x1968 +#define NVA097_SET_ZCULL_Z_ENABLE 0:0 +#define NVA097_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVA097_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_ZCULL_BOUNDS 0x196c +#define NVA097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVA097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVA097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVA097_ZCULL_SYNC 0x1978 +#define NVA097_ZCULL_SYNC_V 31:0 + +#define NVA097_SET_CLIP_ID_TEST 0x197c +#define NVA097_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVA097_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVA097_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVA097_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVA097_SET_CLIP_ID 0x1984 +#define NVA097_SET_CLIP_ID_V 31:0 + +#define NVA097_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVA097_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVA097_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVA097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVA097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVA097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVA097_SET_LOGIC_OP 0x19c4 +#define NVA097_SET_LOGIC_OP_ENABLE 0:0 +#define NVA097_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVA097_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_LOGIC_OP_FUNC 0x19c8 +#define NVA097_SET_LOGIC_OP_FUNC_V 31:0 +#define NVA097_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVA097_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVA097_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVA097_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVA097_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVA097_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVA097_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVA097_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVA097_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVA097_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVA097_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVA097_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVA097_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVA097_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVA097_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVA097_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVA097_SET_Z_COMPRESSION 0x19cc +#define NVA097_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVA097_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVA097_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVA097_CLEAR_SURFACE 0x19d0 +#define NVA097_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVA097_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVA097_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVA097_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVA097_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVA097_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVA097_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVA097_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVA097_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVA097_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVA097_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVA097_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVA097_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVA097_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVA097_SET_CT_WRITE_R_ENABLE 0:0 +#define NVA097_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVA097_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVA097_SET_CT_WRITE_G_ENABLE 4:4 +#define NVA097_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVA097_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVA097_SET_CT_WRITE_B_ENABLE 8:8 +#define NVA097_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVA097_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVA097_SET_CT_WRITE_A_ENABLE 12:12 +#define NVA097_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVA097_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVA097_PIPE_NOP 0x1a2c +#define NVA097_PIPE_NOP_V 31:0 + +#define NVA097_SET_SPARE00 0x1a30 +#define NVA097_SET_SPARE00_V 31:0 + +#define NVA097_SET_SPARE01 0x1a34 +#define NVA097_SET_SPARE01_V 31:0 + +#define NVA097_SET_SPARE02 0x1a38 +#define NVA097_SET_SPARE02_V 31:0 + +#define NVA097_SET_SPARE03 0x1a3c +#define NVA097_SET_SPARE03_V 31:0 + +#define NVA097_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVA097_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVA097_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVA097_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA097_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVA097_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVA097_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVA097_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVA097_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVA097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVA097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVA097_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVA097_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVA097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVA097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVA097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVA097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVA097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVA097_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVA097_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVA097_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVA097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVA097_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVA097_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVA097_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVA097_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVA097_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVA097_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVA097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVA097_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVA097_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVA097_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVA097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVA097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVA097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVA097_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVA097_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVA097_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVA097_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVA097_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVA097_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVA097_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVA097_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVA097_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVA097_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVA097_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVA097_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVA097_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVA097_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVA097_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVA097_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVA097_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVA097_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVA097_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NVA097_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NVA097_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVA097_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVA097_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVA097_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NVA097_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVA097_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVA097_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NVA097_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVA097_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NVA097_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NVA097_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVA097_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVA097_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVA097_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVA097_SET_FALCON00 0x2300 +#define NVA097_SET_FALCON00_V 31:0 + +#define NVA097_SET_FALCON01 0x2304 +#define NVA097_SET_FALCON01_V 31:0 + +#define NVA097_SET_FALCON02 0x2308 +#define NVA097_SET_FALCON02_V 31:0 + +#define NVA097_SET_FALCON03 0x230c +#define NVA097_SET_FALCON03_V 31:0 + +#define NVA097_SET_FALCON04 0x2310 +#define NVA097_SET_FALCON04_V 31:0 + +#define NVA097_SET_FALCON05 0x2314 +#define NVA097_SET_FALCON05_V 31:0 + +#define NVA097_SET_FALCON06 0x2318 +#define NVA097_SET_FALCON06_V 31:0 + +#define NVA097_SET_FALCON07 0x231c +#define NVA097_SET_FALCON07_V 31:0 + +#define NVA097_SET_FALCON08 0x2320 +#define NVA097_SET_FALCON08_V 31:0 + +#define NVA097_SET_FALCON09 0x2324 +#define NVA097_SET_FALCON09_V 31:0 + +#define NVA097_SET_FALCON10 0x2328 +#define NVA097_SET_FALCON10_V 31:0 + +#define NVA097_SET_FALCON11 0x232c +#define NVA097_SET_FALCON11_V 31:0 + +#define NVA097_SET_FALCON12 0x2330 +#define NVA097_SET_FALCON12_V 31:0 + +#define NVA097_SET_FALCON13 0x2334 +#define NVA097_SET_FALCON13_V 31:0 + +#define NVA097_SET_FALCON14 0x2338 +#define NVA097_SET_FALCON14_V 31:0 + +#define NVA097_SET_FALCON15 0x233c +#define NVA097_SET_FALCON15_V 31:0 + +#define NVA097_SET_FALCON16 0x2340 +#define NVA097_SET_FALCON16_V 31:0 + +#define NVA097_SET_FALCON17 0x2344 +#define NVA097_SET_FALCON17_V 31:0 + +#define NVA097_SET_FALCON18 0x2348 +#define NVA097_SET_FALCON18_V 31:0 + +#define NVA097_SET_FALCON19 0x234c +#define NVA097_SET_FALCON19_V 31:0 + +#define NVA097_SET_FALCON20 0x2350 +#define NVA097_SET_FALCON20_V 31:0 + +#define NVA097_SET_FALCON21 0x2354 +#define NVA097_SET_FALCON21_V 31:0 + +#define NVA097_SET_FALCON22 0x2358 +#define NVA097_SET_FALCON22_V 31:0 + +#define NVA097_SET_FALCON23 0x235c +#define NVA097_SET_FALCON23_V 31:0 + +#define NVA097_SET_FALCON24 0x2360 +#define NVA097_SET_FALCON24_V 31:0 + +#define NVA097_SET_FALCON25 0x2364 +#define NVA097_SET_FALCON25_V 31:0 + +#define NVA097_SET_FALCON26 0x2368 +#define NVA097_SET_FALCON26_V 31:0 + +#define NVA097_SET_FALCON27 0x236c +#define NVA097_SET_FALCON27_V 31:0 + +#define NVA097_SET_FALCON28 0x2370 +#define NVA097_SET_FALCON28_V 31:0 + +#define NVA097_SET_FALCON29 0x2374 +#define NVA097_SET_FALCON29_V 31:0 + +#define NVA097_SET_FALCON30 0x2378 +#define NVA097_SET_FALCON30_V 31:0 + +#define NVA097_SET_FALCON31 0x237c +#define NVA097_SET_FALCON31_V 31:0 + +#define NVA097_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVA097_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVA097_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVA097_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVA097_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVA097_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVA097_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVA097_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVA097_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVA097_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVA097_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVA097_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVA097_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVA097_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVA097_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVA097_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVA097_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVA097_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVA097_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVA097_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVA097_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA097_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA097_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVA097_SET_COLOR_CLAMP 0x2600 +#define NVA097_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVA097_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVA097_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVA097_NOOP_X_X_X_SET_VALVE 0x2604 +#define NVA097_NOOP_X_X_X_SET_VALVE_HIGHER_PRIORITY 0:0 +#define NVA097_NOOP_X_X_X_SET_VALVE_HIGHER_PRIORITY_COMPUTE 0x00000000 +#define NVA097_NOOP_X_X_X_SET_VALVE_HIGHER_PRIORITY_GRAPHICS 0x00000001 + +#define NVA097_SET_BINDLESS_TEXTURE 0x2608 +#define NVA097_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVA097_SET_TRAP_HANDLER 0x260c +#define NVA097_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVA097_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVA097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVA097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVA097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVA097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVA097_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVA097_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVA097_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVA097_CALL_MME_MACRO_V 31:0 + +#define NVA097_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVA097_CALL_MME_DATA_V 31:0 + +#endif /* _cl_kepler_a_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cla0b0.h b/userspace/sdks/nv525/nvidia/inc/class/cla0b0.h new file mode 100644 index 0000000..ef4faa8 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cla0b0.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "nvtypes.h" + +#ifndef _cla0b0_h_ +#define _cla0b0_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVA0B0_VIDEO_DECODER (0x0000A0B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cla0b0_h diff --git a/userspace/sdks/nv525/nvidia/inc/class/cla0b5.h b/userspace/sdks/nv525/nvidia/inc/class/cla0b5.h new file mode 100644 index 0000000..92076c6 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cla0b5.h @@ -0,0 +1,262 @@ +/******************************************************************************* + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _cla0b5_h_ +#define _cla0b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define KEPLER_DMA_COPY_A (0x0000A0B5) + +#define NVA0B5_NOP (0x00000100) +#define NVA0B5_NOP_PARAMETER 31:0 +#define NVA0B5_PM_TRIGGER (0x00000140) +#define NVA0B5_PM_TRIGGER_V 31:0 +#define NVA0B5_SET_SEMAPHORE_A (0x00000240) +#define NVA0B5_SET_SEMAPHORE_A_UPPER 7:0 +#define NVA0B5_SET_SEMAPHORE_B (0x00000244) +#define NVA0B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVA0B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVA0B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVA0B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVA0B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVA0B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVA0B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVA0B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVA0B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVA0B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVA0B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVA0B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVA0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVA0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVA0B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVA0B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVA0B5_SET_DST_PHYS_MODE (0x00000264) +#define NVA0B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVA0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVA0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVA0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVA0B5_LAUNCH_DMA (0x00000300) +#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVA0B5_LAUNCH_DMA_BYPASS_L2 11:11 +#define NVA0B5_LAUNCH_DMA_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVA0B5_LAUNCH_DMA_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVA0B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVA0B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVA0B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVA0B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVA0B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVA0B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN (0x0000000B) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX (0x0000000C) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMUL (0x0000000D) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMUL (0x0000000E) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVA0B5_OFFSET_IN_UPPER (0x00000400) +#define NVA0B5_OFFSET_IN_UPPER_UPPER 7:0 +#define NVA0B5_OFFSET_IN_LOWER (0x00000404) +#define NVA0B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVA0B5_OFFSET_OUT_UPPER (0x00000408) +#define NVA0B5_OFFSET_OUT_UPPER_UPPER 7:0 +#define NVA0B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVA0B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVA0B5_PITCH_IN (0x00000410) +#define NVA0B5_PITCH_IN_VALUE 31:0 +#define NVA0B5_PITCH_OUT (0x00000414) +#define NVA0B5_PITCH_OUT_VALUE 31:0 +#define NVA0B5_LINE_LENGTH_IN (0x00000418) +#define NVA0B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVA0B5_LINE_COUNT (0x0000041C) +#define NVA0B5_LINE_COUNT_VALUE 31:0 +#define NVA0B5_SET_REMAP_CONST_A (0x00000700) +#define NVA0B5_SET_REMAP_CONST_A_V 31:0 +#define NVA0B5_SET_REMAP_CONST_B (0x00000704) +#define NVA0B5_SET_REMAP_CONST_B_V 31:0 +#define NVA0B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVA0B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVA0B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVA0B5_SET_DST_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) +#define NVA0B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVA0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVA0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) +#define NVA0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVA0B5_SET_DST_WIDTH (0x00000710) +#define NVA0B5_SET_DST_WIDTH_V 31:0 +#define NVA0B5_SET_DST_HEIGHT (0x00000714) +#define NVA0B5_SET_DST_HEIGHT_V 31:0 +#define NVA0B5_SET_DST_DEPTH (0x00000718) +#define NVA0B5_SET_DST_DEPTH_V 31:0 +#define NVA0B5_SET_DST_LAYER (0x0000071C) +#define NVA0B5_SET_DST_LAYER_V 31:0 +#define NVA0B5_SET_DST_ORIGIN (0x00000720) +#define NVA0B5_SET_DST_ORIGIN_X 15:0 +#define NVA0B5_SET_DST_ORIGIN_Y 31:16 +#define NVA0B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVA0B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVA0B5_SET_SRC_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) +#define NVA0B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVA0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVA0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) +#define NVA0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVA0B5_SET_SRC_WIDTH (0x0000072C) +#define NVA0B5_SET_SRC_WIDTH_V 31:0 +#define NVA0B5_SET_SRC_HEIGHT (0x00000730) +#define NVA0B5_SET_SRC_HEIGHT_V 31:0 +#define NVA0B5_SET_SRC_DEPTH (0x00000734) +#define NVA0B5_SET_SRC_DEPTH_V 31:0 +#define NVA0B5_SET_SRC_LAYER (0x00000738) +#define NVA0B5_SET_SRC_LAYER_V 31:0 +#define NVA0B5_SET_SRC_ORIGIN (0x0000073C) +#define NVA0B5_SET_SRC_ORIGIN_X 15:0 +#define NVA0B5_SET_SRC_ORIGIN_Y 31:16 +#define NVA0B5_PM_TRIGGER_END (0x00001114) +#define NVA0B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cla0b5_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/cla0c0.h b/userspace/sdks/nv525/nvidia/inc/class/cla0c0.h new file mode 100644 index 0000000..bc73e40 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cla0c0.h @@ -0,0 +1,646 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_kepler_compute_a_h_ +#define _cl_kepler_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl kepler_compute_a */ + +#include "nvtypes.h" + +#define KEPLER_COMPUTE_A 0xA0C0 + +#define NVA0C0_SET_OBJECT 0x0000 +#define NVA0C0_SET_OBJECT_CLASS_ID 15:0 +#define NVA0C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVA0C0_NO_OPERATION 0x0100 +#define NVA0C0_NO_OPERATION_V 31:0 + +#define NVA0C0_SET_NOTIFY_A 0x0104 +#define NVA0C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVA0C0_SET_NOTIFY_B 0x0108 +#define NVA0C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVA0C0_NOTIFY 0x010c +#define NVA0C0_NOTIFY_TYPE 31:0 +#define NVA0C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVA0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVA0C0_WAIT_FOR_IDLE 0x0110 +#define NVA0C0_WAIT_FOR_IDLE_V 31:0 + +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA0C0_SEND_GO_IDLE 0x013c +#define NVA0C0_SEND_GO_IDLE_V 31:0 + +#define NVA0C0_PM_TRIGGER 0x0140 +#define NVA0C0_PM_TRIGGER_V 31:0 + +#define NVA0C0_PM_TRIGGER_WFI 0x0144 +#define NVA0C0_PM_TRIGGER_WFI_V 31:0 + +#define NVA0C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVA0C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVA0C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVA0C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVA0C0_LINE_LENGTH_IN 0x0180 +#define NVA0C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVA0C0_LINE_COUNT 0x0184 +#define NVA0C0_LINE_COUNT_VALUE 31:0 + +#define NVA0C0_OFFSET_OUT_UPPER 0x0188 +#define NVA0C0_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVA0C0_OFFSET_OUT 0x018c +#define NVA0C0_OFFSET_OUT_VALUE 31:0 + +#define NVA0C0_PITCH_OUT 0x0190 +#define NVA0C0_PITCH_OUT_VALUE 31:0 + +#define NVA0C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVA0C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVA0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVA0C0_SET_DST_WIDTH 0x0198 +#define NVA0C0_SET_DST_WIDTH_V 31:0 + +#define NVA0C0_SET_DST_HEIGHT 0x019c +#define NVA0C0_SET_DST_HEIGHT_V 31:0 + +#define NVA0C0_SET_DST_DEPTH 0x01a0 +#define NVA0C0_SET_DST_DEPTH_V 31:0 + +#define NVA0C0_SET_DST_LAYER 0x01a4 +#define NVA0C0_SET_DST_LAYER_V 31:0 + +#define NVA0C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVA0C0_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVA0C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVA0C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVA0C0_LAUNCH_DMA 0x01b0 +#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVA0C0_LOAD_INLINE_DATA 0x01b4 +#define NVA0C0_LOAD_INLINE_DATA_V 31:0 + +#define NVA0C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVA0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVA0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVA0C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA0C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVA0C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVA0C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVA0C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVA0C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVA0C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVA0C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVA0C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVA0C0_PERFMON_TRANSFER 0x0210 +#define NVA0C0_PERFMON_TRANSFER_V 31:0 + +#define NVA0C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVA0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA0C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVA0C0_SET_CWD_CONTROL 0x0240 +#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVA0C0_SET_CWD_REF_COUNTER 0x0248 +#define NVA0C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVA0C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0 + +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVA0C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVA0C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVA0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA0C0_SET_QMD_VERSION 0x0288 +#define NVA0C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVA0C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA0C0_CHECK_QMD_VERSION 0x0290 +#define NVA0C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVA0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA0C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVA0C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVA0C0_SEND_PCAS_A 0x02b4 +#define NVA0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVA0C0_SEND_PCAS_B 0x02b8 +#define NVA0C0_SEND_PCAS_B_FROM 23:0 +#define NVA0C0_SEND_PCAS_B_DELTA 31:24 + +#define NVA0C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVA0C0_SET_SPA_VERSION 0x0310 +#define NVA0C0_SET_SPA_VERSION_MINOR 7:0 +#define NVA0C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVA0C0_SET_FALCON00 0x0500 +#define NVA0C0_SET_FALCON00_V 31:0 + +#define NVA0C0_SET_FALCON01 0x0504 +#define NVA0C0_SET_FALCON01_V 31:0 + +#define NVA0C0_SET_FALCON02 0x0508 +#define NVA0C0_SET_FALCON02_V 31:0 + +#define NVA0C0_SET_FALCON03 0x050c +#define NVA0C0_SET_FALCON03_V 31:0 + +#define NVA0C0_SET_FALCON04 0x0510 +#define NVA0C0_SET_FALCON04_V 31:0 + +#define NVA0C0_SET_FALCON05 0x0514 +#define NVA0C0_SET_FALCON05_V 31:0 + +#define NVA0C0_SET_FALCON06 0x0518 +#define NVA0C0_SET_FALCON06_V 31:0 + +#define NVA0C0_SET_FALCON07 0x051c +#define NVA0C0_SET_FALCON07_V 31:0 + +#define NVA0C0_SET_FALCON08 0x0520 +#define NVA0C0_SET_FALCON08_V 31:0 + +#define NVA0C0_SET_FALCON09 0x0524 +#define NVA0C0_SET_FALCON09_V 31:0 + +#define NVA0C0_SET_FALCON10 0x0528 +#define NVA0C0_SET_FALCON10_V 31:0 + +#define NVA0C0_SET_FALCON11 0x052c +#define NVA0C0_SET_FALCON11_V 31:0 + +#define NVA0C0_SET_FALCON12 0x0530 +#define NVA0C0_SET_FALCON12_V 31:0 + +#define NVA0C0_SET_FALCON13 0x0534 +#define NVA0C0_SET_FALCON13_V 31:0 + +#define NVA0C0_SET_FALCON14 0x0538 +#define NVA0C0_SET_FALCON14_V 31:0 + +#define NVA0C0_SET_FALCON15 0x053c +#define NVA0C0_SET_FALCON15_V 31:0 + +#define NVA0C0_SET_FALCON16 0x0540 +#define NVA0C0_SET_FALCON16_V 31:0 + +#define NVA0C0_SET_FALCON17 0x0544 +#define NVA0C0_SET_FALCON17_V 31:0 + +#define NVA0C0_SET_FALCON18 0x0548 +#define NVA0C0_SET_FALCON18_V 31:0 + +#define NVA0C0_SET_FALCON19 0x054c +#define NVA0C0_SET_FALCON19_V 31:0 + +#define NVA0C0_SET_FALCON20 0x0550 +#define NVA0C0_SET_FALCON20_V 31:0 + +#define NVA0C0_SET_FALCON21 0x0554 +#define NVA0C0_SET_FALCON21_V 31:0 + +#define NVA0C0_SET_FALCON22 0x0558 +#define NVA0C0_SET_FALCON22_V 31:0 + +#define NVA0C0_SET_FALCON23 0x055c +#define NVA0C0_SET_FALCON23_V 31:0 + +#define NVA0C0_SET_FALCON24 0x0560 +#define NVA0C0_SET_FALCON24_V 31:0 + +#define NVA0C0_SET_FALCON25 0x0564 +#define NVA0C0_SET_FALCON25_V 31:0 + +#define NVA0C0_SET_FALCON26 0x0568 +#define NVA0C0_SET_FALCON26_V 31:0 + +#define NVA0C0_SET_FALCON27 0x056c +#define NVA0C0_SET_FALCON27_V 31:0 + +#define NVA0C0_SET_FALCON28 0x0570 +#define NVA0C0_SET_FALCON28_V 31:0 + +#define NVA0C0_SET_FALCON29 0x0574 +#define NVA0C0_SET_FALCON29_V 31:0 + +#define NVA0C0_SET_FALCON30 0x0578 +#define NVA0C0_SET_FALCON30_V 31:0 + +#define NVA0C0_SET_FALCON31 0x057c +#define NVA0C0_SET_FALCON31_V 31:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVA0C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVA0C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVA0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVA0C0_SET_SPARE_NOOP12 0x0f44 +#define NVA0C0_SET_SPARE_NOOP12_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP13 0x0f48 +#define NVA0C0_SET_SPARE_NOOP13_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP14 0x0f4c +#define NVA0C0_SET_SPARE_NOOP14_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP15 0x0f50 +#define NVA0C0_SET_SPARE_NOOP15_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP00 0x1040 +#define NVA0C0_SET_SPARE_NOOP00_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP01 0x1044 +#define NVA0C0_SET_SPARE_NOOP01_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP02 0x1048 +#define NVA0C0_SET_SPARE_NOOP02_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP03 0x104c +#define NVA0C0_SET_SPARE_NOOP03_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP04 0x1050 +#define NVA0C0_SET_SPARE_NOOP04_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP05 0x1054 +#define NVA0C0_SET_SPARE_NOOP05_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP06 0x1058 +#define NVA0C0_SET_SPARE_NOOP06_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP07 0x105c +#define NVA0C0_SET_SPARE_NOOP07_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP08 0x1060 +#define NVA0C0_SET_SPARE_NOOP08_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP09 0x1064 +#define NVA0C0_SET_SPARE_NOOP09_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP10 0x1068 +#define NVA0C0_SET_SPARE_NOOP10_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP11 0x106c +#define NVA0C0_SET_SPARE_NOOP11_V 31:0 + +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVA0C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVA0C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVA0C0_SET_RENDER_ENABLE_A 0x1550 +#define NVA0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_RENDER_ENABLE_B 0x1554 +#define NVA0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_RENDER_ENABLE_C 0x1558 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA0C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVA0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVA0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVA0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVA0C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVA0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVA0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVA0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVA0C0_SET_PROGRAM_REGION_A 0x1608 +#define NVA0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVA0C0_SET_PROGRAM_REGION_B 0x160c +#define NVA0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVA0C0_SET_SHADER_CONTROL 0x1690 +#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 + +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVA0C0_PIPE_NOP 0x1a2c +#define NVA0C0_PIPE_NOP_V 31:0 + +#define NVA0C0_SET_SPARE00 0x1a30 +#define NVA0C0_SET_SPARE00_V 31:0 + +#define NVA0C0_SET_SPARE01 0x1a34 +#define NVA0C0_SET_SPARE01_V 31:0 + +#define NVA0C0_SET_SPARE02 0x1a38 +#define NVA0C0_SET_SPARE02_V 31:0 + +#define NVA0C0_SET_SPARE03 0x1a3c +#define NVA0C0_SET_SPARE03_V 31:0 + +#define NVA0C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVA0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVA0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVA0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA0C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVA0C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVA0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVA0C0_SET_TRAP_HANDLER 0x260c +#define NVA0C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVA0C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVA0C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_kepler_compute_a_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cla0c0qmd.h b/userspace/sdks/nv525/nvidia/inc/class/cla0c0qmd.h new file mode 100644 index 0000000..b04ce5b --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cla0c0qmd.h @@ -0,0 +1,658 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __CLA0C0QMD_H__ +#define __CLA0C0QMD_H__ + +/* +** Queue Meta Data, Version 00_06 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_A MW(30:0) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_B MW(31:31) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_C MW(62:32) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_D MW(63:63) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_E MW(94:64) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_F MW(95:95) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_G MW(126:96) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_H MW(127:127) +#define NVA0C0_QMDV00_06_QMD_RESERVED_A_A MW(159:128) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_I MW(191:160) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_J MW(196:192) +#define NVA0C0_QMDV00_06_QMD_RESERVED_A MW(199:197) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K MW(200:200) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L MW(201:201) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_B MW(207:204) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_M MW(222:208) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N MW(223:223) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_O MW(248:224) +#define NVA0C0_QMDV00_06_QMD_RESERVED_C MW(249:249) +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_PROGRAM_OFFSET MW(287:256) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_P MW(319:288) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_Q MW(327:320) +#define NVA0C0_QMDV00_06_QMD_RESERVED_D MW(335:328) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_R MW(351:336) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_S MW(357:352) +#define NVA0C0_QMDV00_06_QMD_RESERVED_E MW(365:358) +#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE MW(369:368) +#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T MW(370:370) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U MW(371:371) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_THROTTLED MW(372:372) +#define NVA0C0_QMDV00_06_THROTTLED_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_THROTTLED_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_E2_A MW(376:376) +#define NVA0C0_QMDV00_06_QMD_RESERVED_E2_B MW(377:377) +#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVA0C0_QMDV00_06_SAMPLER_INDEX MW(382:382) +#define NVA0C0_QMDV00_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVA0C0_QMDV00_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_E3_A MW(383:383) +#define NVA0C0_QMDV00_06_CTA_RASTER_WIDTH MW(415:384) +#define NVA0C0_QMDV00_06_CTA_RASTER_HEIGHT MW(431:416) +#define NVA0C0_QMDV00_06_CTA_RASTER_DEPTH MW(447:432) +#define NVA0C0_QMDV00_06_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVA0C0_QMDV00_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVA0C0_QMDV00_06_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_V MW(535:512) +#define NVA0C0_QMDV00_06_QMD_RESERVED_F MW(542:536) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W MW(543:543) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_SHARED_MEMORY_SIZE MW(561:544) +#define NVA0C0_QMDV00_06_QMD_RESERVED_G MW(575:562) +#define NVA0C0_QMDV00_06_QMD_VERSION MW(579:576) +#define NVA0C0_QMDV00_06_QMD_MAJOR_VERSION MW(583:580) +#define NVA0C0_QMDV00_06_QMD_RESERVED_H MW(591:584) +#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_I MW(668:648) +#define NVA0C0_QMDV00_06_L1_CONFIGURATION MW(671:669) +#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_X MW(703:672) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_Y MW(735:704) +#define NVA0C0_QMDV00_06_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVA0C0_QMDV00_06_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVA0C0_QMDV00_06_QMD_RESERVED_J MW(783:776) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP MW(790:788) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV00_06_QMD_RESERVED_K MW(791:791) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE0_PAYLOAD MW(831:800) +#define NVA0C0_QMDV00_06_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVA0C0_QMDV00_06_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVA0C0_QMDV00_06_QMD_RESERVED_L MW(879:872) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP MW(886:884) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV00_06_QMD_RESERVED_M MW(887:887) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE1_PAYLOAD MW(927:896) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVA0C0_QMDV00_06_QMD_RESERVED_N MW(1466:1464) +#define NVA0C0_QMDV00_06_BARRIER_COUNT MW(1471:1467) +#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVA0C0_QMDV00_06_REGISTER_COUNT MW(1503:1496) +#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVA0C0_QMDV00_06_SASS_VERSION MW(1535:1528) +#define NVA0C0_QMDV00_06_QMD_SPARE_A MW(1567:1536) +#define NVA0C0_QMDV00_06_QMD_SPARE_B MW(1599:1568) +#define NVA0C0_QMDV00_06_QMD_SPARE_C MW(1631:1600) +#define NVA0C0_QMDV00_06_QMD_SPARE_D MW(1663:1632) +#define NVA0C0_QMDV00_06_QMD_SPARE_E MW(1695:1664) +#define NVA0C0_QMDV00_06_QMD_SPARE_F MW(1727:1696) +#define NVA0C0_QMDV00_06_QMD_SPARE_G MW(1759:1728) +#define NVA0C0_QMDV00_06_QMD_SPARE_H MW(1791:1760) +#define NVA0C0_QMDV00_06_QMD_SPARE_I MW(1823:1792) +#define NVA0C0_QMDV00_06_QMD_SPARE_J MW(1855:1824) +#define NVA0C0_QMDV00_06_QMD_SPARE_K MW(1887:1856) +#define NVA0C0_QMDV00_06_QMD_SPARE_L MW(1919:1888) +#define NVA0C0_QMDV00_06_QMD_SPARE_M MW(1951:1920) +#define NVA0C0_QMDV00_06_QMD_SPARE_N MW(1983:1952) +#define NVA0C0_QMDV00_06_DEBUG_ID_UPPER MW(2015:1984) +#define NVA0C0_QMDV00_06_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 01_06 + */ + +#define NVA0C0_QMDV01_06_OUTER_PUT MW(30:0) +#define NVA0C0_QMDV01_06_OUTER_OVERFLOW MW(31:31) +#define NVA0C0_QMDV01_06_OUTER_GET MW(62:32) +#define NVA0C0_QMDV01_06_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVA0C0_QMDV01_06_INNER_GET MW(94:64) +#define NVA0C0_QMDV01_06_INNER_OVERFLOW MW(95:95) +#define NVA0C0_QMDV01_06_INNER_PUT MW(126:96) +#define NVA0C0_QMDV01_06_INNER_STICKY_OVERFLOW MW(127:127) +#define NVA0C0_QMDV01_06_QMD_RESERVED_A_A MW(159:128) +#define NVA0C0_QMDV01_06_SCHEDULER_NEXT_QMD_POINTER MW(191:160) +#define NVA0C0_QMDV01_06_QMD_GROUP_ID MW(197:192) +#define NVA0C0_QMDV01_06_QMD_RESERVED_A MW(199:198) +#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE MW(200:200) +#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_QMD_RESERVED_B MW(207:205) +#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_ADDR MW(222:208) +#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID MW(223:223) +#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVA0C0_QMDV01_06_QMD_RESERVED_C MW(249:249) +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_PROGRAM_OFFSET MW(287:256) +#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVA0C0_QMDV01_06_QMD_RESERVED_D MW(335:328) +#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE MW(369:368) +#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_THROTTLED MW(372:372) +#define NVA0C0_QMDV01_06_THROTTLED_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_THROTTLED_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR MW(376:376) +#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVA0C0_QMDV01_06_SAMPLER_INDEX MW(382:382) +#define NVA0C0_QMDV01_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVA0C0_QMDV01_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVA0C0_QMDV01_06_CTA_RASTER_WIDTH MW(415:384) +#define NVA0C0_QMDV01_06_CTA_RASTER_HEIGHT MW(431:416) +#define NVA0C0_QMDV01_06_CTA_RASTER_DEPTH MW(447:432) +#define NVA0C0_QMDV01_06_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVA0C0_QMDV01_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVA0C0_QMDV01_06_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVA0C0_QMDV01_06_LAUNCH_QUOTA MW(535:512) +#define NVA0C0_QMDV01_06_QMD_RESERVED_F MW(542:536) +#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE MW(543:543) +#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_SHARED_MEMORY_SIZE MW(561:544) +#define NVA0C0_QMDV01_06_QMD_RESERVED_G MW(575:562) +#define NVA0C0_QMDV01_06_QMD_VERSION MW(579:576) +#define NVA0C0_QMDV01_06_QMD_MAJOR_VERSION MW(583:580) +#define NVA0C0_QMDV01_06_QMD_RESERVED_H MW(591:584) +#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_QMD_RESERVED_I MW(668:648) +#define NVA0C0_QMDV01_06_L1_CONFIGURATION MW(671:669) +#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVA0C0_QMDV01_06_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVA0C0_QMDV01_06_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVA0C0_QMDV01_06_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVA0C0_QMDV01_06_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVA0C0_QMDV01_06_QMD_RESERVED_J MW(783:776) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP MW(790:788) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV01_06_QMD_RESERVED_K MW(791:791) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE0_PAYLOAD MW(831:800) +#define NVA0C0_QMDV01_06_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVA0C0_QMDV01_06_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVA0C0_QMDV01_06_QMD_RESERVED_L MW(879:872) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP MW(886:884) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV01_06_QMD_RESERVED_M MW(887:887) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE1_PAYLOAD MW(927:896) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVA0C0_QMDV01_06_QMD_RESERVED_N MW(1466:1464) +#define NVA0C0_QMDV01_06_BARRIER_COUNT MW(1471:1467) +#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVA0C0_QMDV01_06_REGISTER_COUNT MW(1503:1496) +#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVA0C0_QMDV01_06_SASS_VERSION MW(1535:1528) +#define NVA0C0_QMDV01_06_HW_ONLY_INNER_GET MW(1566:1536) +#define NVA0C0_QMDV01_06_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVA0C0_QMDV01_06_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVA0C0_QMDV01_06_HW_ONLY_SCHEDULE_ON_PUT_UPDATE_ENABLE MW(1599:1599) +#define NVA0C0_QMDV01_06_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(1606:1600) +#define NVA0C0_QMDV01_06_QMD_RESERVED_Q MW(1609:1607) +#define NVA0C0_QMDV01_06_COALESCE_WAITING_PERIOD MW(1617:1610) +#define NVA0C0_QMDV01_06_QMD_RESERVED_R MW(1631:1618) +#define NVA0C0_QMDV01_06_QMD_SPARE_D MW(1663:1632) +#define NVA0C0_QMDV01_06_QMD_SPARE_E MW(1695:1664) +#define NVA0C0_QMDV01_06_QMD_SPARE_F MW(1727:1696) +#define NVA0C0_QMDV01_06_QMD_SPARE_G MW(1759:1728) +#define NVA0C0_QMDV01_06_QMD_SPARE_H MW(1791:1760) +#define NVA0C0_QMDV01_06_QMD_SPARE_I MW(1823:1792) +#define NVA0C0_QMDV01_06_QMD_SPARE_J MW(1855:1824) +#define NVA0C0_QMDV01_06_QMD_SPARE_K MW(1887:1856) +#define NVA0C0_QMDV01_06_QMD_SPARE_L MW(1919:1888) +#define NVA0C0_QMDV01_06_QMD_SPARE_M MW(1951:1920) +#define NVA0C0_QMDV01_06_QMD_SPARE_N MW(1983:1952) +#define NVA0C0_QMDV01_06_DEBUG_ID_UPPER MW(2015:1984) +#define NVA0C0_QMDV01_06_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 01_07 + */ + +#define NVA0C0_QMDV01_07_OUTER_PUT MW(30:0) +#define NVA0C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) +#define NVA0C0_QMDV01_07_OUTER_GET MW(62:32) +#define NVA0C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVA0C0_QMDV01_07_INNER_GET MW(94:64) +#define NVA0C0_QMDV01_07_INNER_OVERFLOW MW(95:95) +#define NVA0C0_QMDV01_07_INNER_PUT MW(126:96) +#define NVA0C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) +#define NVA0C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) +#define NVA0C0_QMDV01_07_QMD_GROUP_ID MW(197:192) +#define NVA0C0_QMDV01_07_QMD_RESERVED_A MW(200:198) +#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_QMD_RESERVED_B MW(223:208) +#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVA0C0_QMDV01_07_QMD_RESERVED_C MW(249:249) +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) +#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVA0C0_QMDV01_07_QMD_RESERVED_D MW(335:328) +#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) +#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_THROTTLED MW(372:372) +#define NVA0C0_QMDV01_07_THROTTLED_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_THROTTLED_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) +#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVA0C0_QMDV01_07_SAMPLER_INDEX MW(382:382) +#define NVA0C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVA0C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVA0C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) +#define NVA0C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) +#define NVA0C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) +#define NVA0C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVA0C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVA0C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVA0C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVA0C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) +#define NVA0C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) +#define NVA0C0_QMDV01_07_QMD_RESERVED_G MW(575:562) +#define NVA0C0_QMDV01_07_QMD_VERSION MW(579:576) +#define NVA0C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) +#define NVA0C0_QMDV01_07_QMD_RESERVED_H MW(591:584) +#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_QMD_RESERVED_I MW(668:648) +#define NVA0C0_QMDV01_07_L1_CONFIGURATION MW(671:669) +#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVA0C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVA0C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVA0C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVA0C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVA0C0_QMDV01_07_QMD_RESERVED_J MW(783:776) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV01_07_QMD_RESERVED_K MW(791:791) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) +#define NVA0C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVA0C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVA0C0_QMDV01_07_QMD_RESERVED_L MW(879:872) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV01_07_QMD_RESERVED_M MW(887:887) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVA0C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) +#define NVA0C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) +#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVA0C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) +#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVA0C0_QMDV01_07_SASS_VERSION MW(1535:1528) +#define NVA0C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) +#define NVA0C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVA0C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVA0C0_QMDV01_07_QMD_RESERVED_P MW(1599:1599) +#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVA0C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) +#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVA0C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) +#define NVA0C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) +#define NVA0C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) +#define NVA0C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) +#define NVA0C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) +#define NVA0C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) +#define NVA0C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) +#define NVA0C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) +#define NVA0C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) +#define NVA0C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) +#define NVA0C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) +#define NVA0C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLA0C0QMD_H__ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cla140.h b/userspace/sdks/nv525/nvidia/inc/class/cla140.h new file mode 100644 index 0000000..08b8fc1 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cla140.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cla140_h_ +#define _cla140_h_ + +#define KEPLER_INLINE_TO_MEMORY_B 0xA140 + +#endif // _cla140_h_ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cla16f.h b/userspace/sdks/nv525/nvidia/inc/class/cla16f.h new file mode 100644 index 0000000..66e7594 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cla16f.h @@ -0,0 +1,254 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cla16f_h_ +#define _cla16f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class KEPLER_CHANNEL_GPFIFO */ +/* + * Documentation for KEPLER_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + */ +#define KEPLER_CHANNEL_GPFIFO_B (0x0000A16F) + +/* pio method data structure */ +typedef volatile struct _cla16f_tag0 { + NvV32 Reserved00[0x7c0]; +} NvA16FTypedef, KEPLER_ChannelGPFifoB; +#define NVA16F_TYPEDEF KEPLER_CHANNELChannelGPFifo +/* dma flow control data structure */ +typedef volatile struct _cla16f_tag1 { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} NvA16FControl, KeplerBControlGPFifo; +/* fields and values */ +#define NVA16F_NUMBER_OF_SUBCHANNELS (8) +#define NVA16F_SET_OBJECT (0x00000000) +#define NVA16F_SET_OBJECT_NVCLASS 15:0 +#define NVA16F_SET_OBJECT_ENGINE 20:16 +#define NVA16F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVA16F_ILLEGAL (0x00000004) +#define NVA16F_ILLEGAL_HANDLE 31:0 +#define NVA16F_NOP (0x00000008) +#define NVA16F_NOP_HANDLE 31:0 +#define NVA16F_SEMAPHOREA (0x00000010) +#define NVA16F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVA16F_SEMAPHOREB (0x00000014) +#define NVA16F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVA16F_SEMAPHOREC (0x00000018) +#define NVA16F_SEMAPHOREC_PAYLOAD 31:0 +#define NVA16F_SEMAPHORED (0x0000001C) +#define NVA16F_SEMAPHORED_OPERATION 4:0 +#define NVA16F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVA16F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVA16F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVA16F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVA16F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 +#define NVA16F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVA16F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVA16F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVA16F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVA16F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVA16F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVA16F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVA16F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVA16F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVA16F_SEMAPHORED_REDUCTION 30:27 +#define NVA16F_SEMAPHORED_REDUCTION_MIN 0x00000000 +#define NVA16F_SEMAPHORED_REDUCTION_MAX 0x00000001 +#define NVA16F_SEMAPHORED_REDUCTION_XOR 0x00000002 +#define NVA16F_SEMAPHORED_REDUCTION_AND 0x00000003 +#define NVA16F_SEMAPHORED_REDUCTION_OR 0x00000004 +#define NVA16F_SEMAPHORED_REDUCTION_ADD 0x00000005 +#define NVA16F_SEMAPHORED_REDUCTION_INC 0x00000006 +#define NVA16F_SEMAPHORED_REDUCTION_DEC 0x00000007 +#define NVA16F_SEMAPHORED_FORMAT 31:31 +#define NVA16F_SEMAPHORED_FORMAT_SIGNED 0x00000000 +#define NVA16F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 +#define NVA16F_NON_STALL_INTERRUPT (0x00000020) +#define NVA16F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVA16F_FB_FLUSH (0x00000024) +#define NVA16F_FB_FLUSH_HANDLE 31:0 +#define NVA16F_MEM_OP_A (0x00000028) +#define NVA16F_MEM_OP_A_OPERAND_LOW 31:2 +#define NVA16F_MEM_OP_A_TLB_INVALIDATE_ADDR 29:2 +#define NVA16F_MEM_OP_A_TLB_INVALIDATE_TARGET 31:30 +#define NVA16F_MEM_OP_A_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000 +#define NVA16F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002 +#define NVA16F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 +#define NVA16F_MEM_OP_B (0x0000002c) +#define NVA16F_MEM_OP_B_OPERAND_HIGH 7:0 +#define NVA16F_MEM_OP_B_OPERATION 31:27 +#define NVA16F_MEM_OP_B_OPERATION_SYSMEMBAR_FLUSH 0x00000005 +#define NVA16F_MEM_OP_B_OPERATION_SOFT_FLUSH 0x00000006 +#define NVA16F_MEM_OP_B_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVA16F_MEM_OP_B_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NVA16F_MEM_OP_B_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +#define NVA16F_MEM_OP_B_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVA16F_MEM_OP_B_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB 0:0 +#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ALL 0x00000001 +#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC 1:1 +#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVA16F_SET_REFERENCE (0x00000050) +#define NVA16F_SET_REFERENCE_COUNT 31:0 +#define NVA16F_WFI (0x00000078) +#define NVA16F_WFI_HANDLE 31:0 +#define NVA16F_CRC_CHECK (0x0000007c) +#define NVA16F_CRC_CHECK_VALUE 31:0 +#define NVA16F_YIELD (0x00000080) +#define NVA16F_YIELD_OP 1:0 +#define NVA16F_YIELD_OP_NOP 0x00000000 + + +/* GPFIFO entry format */ +#define NVA16F_GP_ENTRY__SIZE 8 +#define NVA16F_GP_ENTRY0_FETCH 0:0 +#define NVA16F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVA16F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVA16F_GP_ENTRY0_GET 31:2 +#define NVA16F_GP_ENTRY0_OPERAND 31:0 +#define NVA16F_GP_ENTRY1_GET_HI 7:0 +#define NVA16F_GP_ENTRY1_PRIV 8:8 +#define NVA16F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NVA16F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NVA16F_GP_ENTRY1_LEVEL 9:9 +#define NVA16F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVA16F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVA16F_GP_ENTRY1_LENGTH 30:10 +#define NVA16F_GP_ENTRY1_SYNC 31:31 +#define NVA16F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVA16F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVA16F_GP_ENTRY1_OPCODE 7:0 +#define NVA16F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVA16F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVA16F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVA16F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVA16F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVA16F_DMA_METHOD_ADDRESS 11:0 +#define NVA16F_DMA_SUBDEVICE_MASK 15:4 +#define NVA16F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVA16F_DMA_TERT_OP 17:16 +#define NVA16F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVA16F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVA16F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVA16F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVA16F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVA16F_DMA_METHOD_COUNT_OLD 28:18 +#define NVA16F_DMA_METHOD_COUNT 28:16 +#define NVA16F_DMA_IMMD_DATA 28:16 +#define NVA16F_DMA_SEC_OP 31:29 +#define NVA16F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVA16F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVA16F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVA16F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVA16F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVA16F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVA16F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVA16F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVA16F_DMA_INCR_ADDRESS 11:0 +#define NVA16F_DMA_INCR_SUBCHANNEL 15:13 +#define NVA16F_DMA_INCR_COUNT 28:16 +#define NVA16F_DMA_INCR_OPCODE 31:29 +#define NVA16F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVA16F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVA16F_DMA_NONINCR_ADDRESS 11:0 +#define NVA16F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVA16F_DMA_NONINCR_COUNT 28:16 +#define NVA16F_DMA_NONINCR_OPCODE 31:29 +#define NVA16F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVA16F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVA16F_DMA_ONEINCR_ADDRESS 11:0 +#define NVA16F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVA16F_DMA_ONEINCR_COUNT 28:16 +#define NVA16F_DMA_ONEINCR_OPCODE 31:29 +#define NVA16F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVA16F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVA16F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVA16F_DMA_IMMD_ADDRESS 11:0 +#define NVA16F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVA16F_DMA_IMMD_DATA 28:16 +#define NVA16F_DMA_IMMD_OPCODE 31:29 +#define NVA16F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVA16F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVA16F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA16F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVA16F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVA16F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA16F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVA16F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA16F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVA16F_DMA_ENDSEG_OPCODE 31:29 +#define NVA16F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVA16F_DMA_ADDRESS 12:2 +#define NVA16F_DMA_SUBCH 15:13 +#define NVA16F_DMA_OPCODE3 17:16 +#define NVA16F_DMA_OPCODE3_NONE (0x00000000) +#define NVA16F_DMA_COUNT 28:18 +#define NVA16F_DMA_OPCODE 31:29 +#define NVA16F_DMA_OPCODE_METHOD (0x00000000) +#define NVA16F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVA16F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cla16F_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cla16fsw.h b/userspace/sdks/nv525/nvidia/inc/class/cla16fsw.h new file mode 100644 index 0000000..cea256f --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cla16fsw.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cla16f_sw_h_ +#define _cla16f_sw_h_ + +#define NVA16F_NOTIFIERS_RC (0) +#define NVA16F_NOTIFIERS_REFCNT (1) +#define NVA16F_NOTIFIERS_NONSTALL (2) +#define NVA16F_NOTIFIERS_EVENTBUFFER (3) +#define NVA16F_NOTIFIERS_IDLECHANNEL (4) +#define NVA16F_NOTIFIERS_ENDCTX (5) +#define NVA16F_NOTIFIERS_SW (6) +#define NVA16F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVA16F_NOTIFIERS_MAXCOUNT (8) + +/* NvNotification[] fields and values */ +#define NVA16F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVA16F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _cla16f_sw_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cla197.h b/userspace/sdks/nv525/nvidia/inc/class/cla197.h new file mode 100644 index 0000000..deae603 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cla197.h @@ -0,0 +1,3826 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_kepler_b_h_ +#define _cl_kepler_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl kepler_b */ + +#include "nvtypes.h" + +#define KEPLER_B 0xA197 + +#define NVA197_SET_OBJECT 0x0000 +#define NVA197_SET_OBJECT_CLASS_ID 15:0 +#define NVA197_SET_OBJECT_ENGINE_ID 20:16 + +#define NVA197_NO_OPERATION 0x0100 +#define NVA197_NO_OPERATION_V 31:0 + +#define NVA197_SET_NOTIFY_A 0x0104 +#define NVA197_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVA197_SET_NOTIFY_B 0x0108 +#define NVA197_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVA197_NOTIFY 0x010c +#define NVA197_NOTIFY_TYPE 31:0 +#define NVA197_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVA197_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVA197_WAIT_FOR_IDLE 0x0110 +#define NVA197_WAIT_FOR_IDLE_V 31:0 + +#define NVA197_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVA197_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVA197_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVA197_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVA197_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVA197_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVA197_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVA197_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVA197_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVA197_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVA197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVA197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVA197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVA197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVA197_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVA197_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVA197_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVA197_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVA197_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA197_SEND_GO_IDLE 0x013c +#define NVA197_SEND_GO_IDLE_V 31:0 + +#define NVA197_PM_TRIGGER 0x0140 +#define NVA197_PM_TRIGGER_V 31:0 + +#define NVA197_PM_TRIGGER_WFI 0x0144 +#define NVA197_PM_TRIGGER_WFI_V 31:0 + +#define NVA197_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVA197_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVA197_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVA197_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVA197_LINE_LENGTH_IN 0x0180 +#define NVA197_LINE_LENGTH_IN_VALUE 31:0 + +#define NVA197_LINE_COUNT 0x0184 +#define NVA197_LINE_COUNT_VALUE 31:0 + +#define NVA197_OFFSET_OUT_UPPER 0x0188 +#define NVA197_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVA197_OFFSET_OUT 0x018c +#define NVA197_OFFSET_OUT_VALUE 31:0 + +#define NVA197_PITCH_OUT 0x0190 +#define NVA197_PITCH_OUT_VALUE 31:0 + +#define NVA197_SET_DST_BLOCK_SIZE 0x0194 +#define NVA197_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVA197_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVA197_SET_DST_WIDTH 0x0198 +#define NVA197_SET_DST_WIDTH_V 31:0 + +#define NVA197_SET_DST_HEIGHT 0x019c +#define NVA197_SET_DST_HEIGHT_V 31:0 + +#define NVA197_SET_DST_DEPTH 0x01a0 +#define NVA197_SET_DST_DEPTH_V 31:0 + +#define NVA197_SET_DST_LAYER 0x01a4 +#define NVA197_SET_DST_LAYER_V 31:0 + +#define NVA197_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVA197_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVA197_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVA197_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVA197_LAUNCH_DMA 0x01b0 +#define NVA197_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVA197_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA197_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA197_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVA197_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVA197_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVA197_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVA197_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVA197_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVA197_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVA197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVA197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVA197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVA197_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVA197_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA197_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA197_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA197_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVA197_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA197_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA197_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVA197_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVA197_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVA197_LOAD_INLINE_DATA 0x01b4 +#define NVA197_LOAD_INLINE_DATA_V 31:0 + +#define NVA197_SET_I2M_SEMAPHORE_A 0x01dc +#define NVA197_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVA197_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVA197_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA197_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVA197_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVA197_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVA197_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVA197_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVA197_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVA197_SET_I2M_SPARE_NOOP03 0x01fc +#define NVA197_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVA197_RUN_DS_NOW 0x0200 +#define NVA197_RUN_DS_NOW_V 31:0 + +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVA197_SET_RASTER_PIPE_SYNC_CONTROL 0x0208 +#define NVA197_SET_RASTER_PIPE_SYNC_CONTROL_PRIM_AREA_THRESHOLD 21:0 +#define NVA197_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE 24:24 +#define NVA197_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE_FALSE 0x00000000 +#define NVA197_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVA197_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVA197_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVA197_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVA197_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVA197_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_GS_DM_FIFO 0x0214 +#define NVA197_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVA197_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVA197_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVA197_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVA197_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA197_INVALIDATE_SHADER_CACHES 0x021c +#define NVA197_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVA197_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVA197_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVA197_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVA197_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVA197_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVA197_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVA197_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVA197_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVA197_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVA197_SET_VAB_VERTEX3F(i) (0x0220+(i)*4) +#define NVA197_SET_VAB_VERTEX3F_V 31:0 + +#define NVA197_SET_VAB_VERTEX4F(i) (0x0230+(i)*4) +#define NVA197_SET_VAB_VERTEX4F_V 31:0 + +#define NVA197_SET_VAB_NORMAL3F(i) (0x0240+(i)*4) +#define NVA197_SET_VAB_NORMAL3F_V 31:0 + +#define NVA197_SET_VAB_COLOR3F(i) (0x0250+(i)*4) +#define NVA197_SET_VAB_COLOR3F_V 31:0 + +#define NVA197_SET_VAB_COLOR4F(i) (0x0260+(i)*4) +#define NVA197_SET_VAB_COLOR4F_V 31:0 + +#define NVA197_SET_VAB_COLOR4UB(i) (0x0270+(i)*4) +#define NVA197_SET_VAB_COLOR4UB_V 31:0 + +#define NVA197_SET_VAB_TEX_COORD1F(i) (0x0280+(i)*4) +#define NVA197_SET_VAB_TEX_COORD1F_V 31:0 + +#define NVA197_SET_VAB_TEX_COORD2F(i) (0x0290+(i)*4) +#define NVA197_SET_VAB_TEX_COORD2F_V 31:0 + +#define NVA197_SET_VAB_TEX_COORD3F(i) (0x02a0+(i)*4) +#define NVA197_SET_VAB_TEX_COORD3F_V 31:0 + +#define NVA197_SET_VAB_TEX_COORD4F(i) (0x02b0+(i)*4) +#define NVA197_SET_VAB_TEX_COORD4F_V 31:0 + +#define NVA197_SET_GLOBAL_LOAD_VIA_TEXTURE 0x02c4 +#define NVA197_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE 0:0 +#define NVA197_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE_TRUE 0x00000001 +#define NVA197_SET_GLOBAL_LOAD_VIA_TEXTURE_HEADER_INDEX 23:4 + +#define NVA197_SET_TASK_CIRCULAR_BUFFER_THROTTLE 0x02cc +#define NVA197_SET_TASK_CIRCULAR_BUFFER_THROTTLE_TASK_COUNT 21:0 + +#define NVA197_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NVA197_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NVA197_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVA197_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVA197_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVA197_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 9:0 + +#define NVA197_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVA197_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVA197_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVA197_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVA197_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVA197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVA197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVA197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVA197_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVA197_SET_ZCULL_SUBREGION 0x02e8 +#define NVA197_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVA197_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVA197_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVA197_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVA197_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVA197_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVA197_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVA197_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVA197_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVA197_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVA197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVA197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVA197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVA197_DRAW_ZERO_INDEX 0x0304 +#define NVA197_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVA197_SET_L1_CONFIGURATION 0x0308 +#define NVA197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVA197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVA197_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVA197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVA197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVA197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVA197_SET_SPA_VERSION 0x0310 +#define NVA197_SET_SPA_VERSION_MINOR 7:0 +#define NVA197_SET_SPA_VERSION_MAJOR 15:8 + +#define NVA197_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NVA197_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NVA197_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_SNAP_GRID_LINE 0x0318 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVA197_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVA197_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVA197_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVA197_SET_SNAP_GRID_NON_LINE 0x031c +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVA197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVA197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVA197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVA197_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVA197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVA197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVA197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVA197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVA197_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVA197_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVA197_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVA197_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVA197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVA197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVA197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVA197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVA197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVA197_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVA197_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVA197_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVA197_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVA197_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVA197_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVA197_SET_TESSELLATION_LOD_V1 0x0330 +#define NVA197_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVA197_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVA197_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVA197_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVA197_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVA197_RESERVED_TG07 0x033c +#define NVA197_RESERVED_TG07_V 0:0 + +#define NVA197_RESERVED_TG08 0x0340 +#define NVA197_RESERVED_TG08_V 0:0 + +#define NVA197_RESERVED_TG09 0x0344 +#define NVA197_RESERVED_TG09_V 0:0 + +#define NVA197_RESERVED_TG10 0x0348 +#define NVA197_RESERVED_TG10_V 0:0 + +#define NVA197_RESERVED_TG11 0x034c +#define NVA197_RESERVED_TG11_V 0:0 + +#define NVA197_RESERVED_TG12 0x0350 +#define NVA197_RESERVED_TG12_V 0:0 + +#define NVA197_RESERVED_TG13 0x0354 +#define NVA197_RESERVED_TG13_V 0:0 + +#define NVA197_RESERVED_TG14 0x0358 +#define NVA197_RESERVED_TG14_V 0:0 + +#define NVA197_RESERVED_TG15 0x035c +#define NVA197_RESERVED_TG15_V 0:0 + +#define NVA197_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVA197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVA197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVA197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVA197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVA197_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVA197_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVA197_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVA197_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVA197_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVA197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVA197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVA197_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVA197_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVA197_SET_RASTER_ENABLE 0x037c +#define NVA197_SET_RASTER_ENABLE_V 0:0 +#define NVA197_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVA197_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVA197_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVA197_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVA197_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVA197_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVA197_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVA197_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVA197_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVA197_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVA197_SET_VAB_DATA_TYPELESS(i) (0x0400+(i)*4) +#define NVA197_SET_VAB_DATA_TYPELESS_V 31:0 + +#define NVA197_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVA197_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVA197_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVA197_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVA197_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVA197_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVA197_SET_RASTER_INPUT 0x0740 +#define NVA197_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVA197_SET_STREAM_OUTPUT 0x0744 +#define NVA197_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVA197_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVA197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVA197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_ALPHA_FRACTION 0x074c +#define NVA197_SET_ALPHA_FRACTION_V 7:0 + +#define NVA197_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVA197_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVA197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVA197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVA197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 + +#define NVA197_SET_MAX_TI_WARPS_PER_BATCH 0x075c +#define NVA197_SET_MAX_TI_WARPS_PER_BATCH_V 5:0 + +#define NVA197_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVA197_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA197_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVA197_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVA197_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVA197_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVA197_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVA197_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVA197_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVA197_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVA197_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVA197_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVA197_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVA197_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVA197_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVA197_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVA197_SET_ISBE_SAVE_RESTORE_PROGRAM 0x07ac +#define NVA197_SET_ISBE_SAVE_RESTORE_PROGRAM_OFFSET 31:0 + +#define NVA197_SET_VAB_VERTEX2F(i) (0x07b0+(i)*4) +#define NVA197_SET_VAB_VERTEX2F_V 31:0 + +#define NVA197_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVA197_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVA197_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVA197_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVA197_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVA197_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVA197_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVA197_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVA197_SET_CULL_BEFORE_FETCH 0x07dc +#define NVA197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVA197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVA197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVA197_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVA197_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVA197_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVA197_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVA197_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVA197_SET_ZCULL_STORAGE_A 0x07e8 +#define NVA197_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVA197_SET_ZCULL_STORAGE_B 0x07ec +#define NVA197_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVA197_SET_ZCULL_STORAGE_C 0x07f0 +#define NVA197_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVA197_SET_ZCULL_STORAGE_D 0x07f4 +#define NVA197_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVA197_SET_ZT_READ_ONLY 0x07f8 +#define NVA197_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVA197_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVA197_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVA197_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVA197_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVA197_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVA197_SET_TEXTURE_INSTRUCTION_OPERAND 0x07fc +#define NVA197_SET_TEXTURE_INSTRUCTION_OPERAND_ORDERING 0:0 +#define NVA197_SET_TEXTURE_INSTRUCTION_OPERAND_ORDERING_FERMI_ORDER 0x00000000 +#define NVA197_SET_TEXTURE_INSTRUCTION_OPERAND_ORDERING_KEPLER_ORDER 0x00000001 + +#define NVA197_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVA197_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVA197_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVA197_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVA197_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVA197_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVA197_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVA197_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVA197_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVA197_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVA197_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVA197_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVA197_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVA197_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVA197_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVA197_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVA197_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVA197_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVA197_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA197_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVA197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVA197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVA197_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVA197_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVA197_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVA197_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVA197_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVA197_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVA197_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NVA197_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NVA197_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVA197_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVA197_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVA197_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVA197_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVA197_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVA197_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVA197_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVA197_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVA197_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVA197_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVA197_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVA197_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVA197_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVA197_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVA197_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVA197_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVA197_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVA197_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVA197_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVA197_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVA197_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVA197_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVA197_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVA197_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVA197_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVA197_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVA197_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVA197_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVA197_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVA197_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVA197_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVA197_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVA197_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVA197_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVA197_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVA197_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVA197_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVA197_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVA197_SET_STATISTICS_COUNTER 0x0d68 +#define NVA197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVA197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVA197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVA197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVA197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVA197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVA197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVA197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVA197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVA197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVA197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVA197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVA197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVA197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVA197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVA197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVA197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVA197_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVA197_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVA197_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVA197_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVA197_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVA197_SET_VERTEX_ARRAY_START 0x0d74 +#define NVA197_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVA197_DRAW_VERTEX_ARRAY 0x0d78 +#define NVA197_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVA197_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVA197_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVA197_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVA197_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVA197_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVA197_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVA197_SET_Z_CLEAR_VALUE 0x0d90 +#define NVA197_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVA197_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVA197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVA197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVA197_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVA197_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVA197_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVA197_SET_FRONT_POLYGON_MODE 0x0dac +#define NVA197_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVA197_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVA197_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVA197_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVA197_SET_BACK_POLYGON_MODE 0x0db0 +#define NVA197_SET_BACK_POLYGON_MODE_V 31:0 +#define NVA197_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVA197_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVA197_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVA197_SET_POLY_SMOOTH 0x0db4 +#define NVA197_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVA197_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVA197_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_ZT_MARK 0x0db8 +#define NVA197_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NVA197_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVA197_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVA197_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVA197_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVA197_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVA197_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVA197_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVA197_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVA197_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVA197_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVA197_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVA197_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_PATCH 0x0dcc +#define NVA197_SET_PATCH_SIZE 7:0 + +#define NVA197_SET_ZCULL_CRITERION 0x0dd8 +#define NVA197_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVA197_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVA197_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVA197_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVA197_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVA197_SET_ZCULL_CRITERION_SREF 23:16 +#define NVA197_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVA197_SET_SM_QUADRANT_SELECTION_CONTROL 0x0ddc +#define NVA197_SET_SM_QUADRANT_SELECTION_CONTROL_MAX_PIXEL_WARPS 7:0 + +#define NVA197_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVA197_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVA197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVA197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVA197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_DRAW_INLINE_VERTEX_VAB_UPDATE 0x0dec +#define NVA197_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE 0:0 +#define NVA197_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_WINDOW_OFFSET_X 0x0df8 +#define NVA197_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVA197_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVA197_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVA197_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVA197_SET_SCISSOR_ENABLE_V 0:0 +#define NVA197_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVA197_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVA197_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVA197_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVA197_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVA197_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVA197_SET_VAB_NORMAL3S(i) (0x0f00+(i)*4) +#define NVA197_SET_VAB_NORMAL3S_V 31:0 + +#define NVA197_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVA197_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVA197_SET_BACK_STENCIL_MASK 0x0f58 +#define NVA197_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVA197_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVA197_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVA197_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVA197_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVA197_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVA197_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVA197_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVA197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVA197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVA197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVA197_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVA197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVA197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVA197_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVA197_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVA197_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVA197_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVA197_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVA197_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVA197_SET_CT_MRT_ENABLE 0x0fac +#define NVA197_SET_CT_MRT_ENABLE_V 0:0 +#define NVA197_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVA197_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVA197_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVA197_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVA197_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVA197_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVA197_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVA197_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVA197_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVA197_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVA197_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVA197_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVA197_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVA197_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVA197_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVA197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVA197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVA197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVA197_SET_ZT_A 0x0fe0 +#define NVA197_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_ZT_B 0x0fe4 +#define NVA197_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_ZT_FORMAT 0x0fe8 +#define NVA197_SET_ZT_FORMAT_V 4:0 +#define NVA197_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVA197_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVA197_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVA197_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVA197_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVA197_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVA197_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVA197_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVA197_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVA197_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVA197_SET_ZT_BLOCK_SIZE 0x0fec +#define NVA197_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVA197_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA197_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVA197_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVA197_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVA197_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVA197_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVA197_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVA197_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVA197_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVA197_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVA197_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA197_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVA197_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVA197_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVA197_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVA197_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVA197_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVA197_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVA197_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVA197_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVA197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVA197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVA197_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVA197_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVA197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVA197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_SPARE_NOOP00 0x1040 +#define NVA197_SET_SPARE_NOOP00_V 31:0 + +#define NVA197_SET_SPARE_NOOP01 0x1044 +#define NVA197_SET_SPARE_NOOP01_V 31:0 + +#define NVA197_SET_SPARE_NOOP02 0x1048 +#define NVA197_SET_SPARE_NOOP02_V 31:0 + +#define NVA197_SET_SPARE_NOOP03 0x104c +#define NVA197_SET_SPARE_NOOP03_V 31:0 + +#define NVA197_SET_SPARE_NOOP04 0x1050 +#define NVA197_SET_SPARE_NOOP04_V 31:0 + +#define NVA197_SET_SPARE_NOOP05 0x1054 +#define NVA197_SET_SPARE_NOOP05_V 31:0 + +#define NVA197_SET_SPARE_NOOP06 0x1058 +#define NVA197_SET_SPARE_NOOP06_V 31:0 + +#define NVA197_SET_SPARE_NOOP07 0x105c +#define NVA197_SET_SPARE_NOOP07_V 31:0 + +#define NVA197_SET_SPARE_NOOP08 0x1060 +#define NVA197_SET_SPARE_NOOP08_V 31:0 + +#define NVA197_SET_SPARE_NOOP09 0x1064 +#define NVA197_SET_SPARE_NOOP09_V 31:0 + +#define NVA197_SET_SPARE_NOOP10 0x1068 +#define NVA197_SET_SPARE_NOOP10_V 31:0 + +#define NVA197_SET_SPARE_NOOP11 0x106c +#define NVA197_SET_SPARE_NOOP11_V 31:0 + +#define NVA197_SET_SPARE_NOOP12 0x1070 +#define NVA197_SET_SPARE_NOOP12_V 31:0 + +#define NVA197_SET_SPARE_NOOP13 0x1074 +#define NVA197_SET_SPARE_NOOP13_V 31:0 + +#define NVA197_SET_SPARE_NOOP14 0x1078 +#define NVA197_SET_SPARE_NOOP14_V 31:0 + +#define NVA197_SET_SPARE_NOOP15 0x107c +#define NVA197_SET_SPARE_NOOP15_V 31:0 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVA197_UNBIND_ALL 0x10f4 +#define NVA197_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVA197_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVA197_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVA197_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA197_NO_OPERATION_DATA_HI 0x110c +#define NVA197_NO_OPERATION_DATA_HI_V 31:0 + +#define NVA197_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVA197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVA197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVA197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVA197_PM_TRIGGER_END 0x1114 +#define NVA197_PM_TRIGGER_END_V 31:0 + +#define NVA197_SET_VERTEX_ID_BASE 0x1118 +#define NVA197_SET_VERTEX_ID_BASE_V 31:0 + +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVA197_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVA197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVA197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVA197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVA197_FLUSH_PENDING_WRITES 0x1144 +#define NVA197_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVA197_SET_VAB_DATA_CONTROL 0x114c +#define NVA197_SET_VAB_DATA_CONTROL_VAB_INDEX 7:0 +#define NVA197_SET_VAB_DATA_CONTROL_COMPONENT_COUNT 10:8 +#define NVA197_SET_VAB_DATA_CONTROL_COMPONENT_BYTE_WIDTH 14:12 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT 18:16 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_SNORM 0x00000001 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_UNORM 0x00000002 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_SINT 0x00000003 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_UINT 0x00000004 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_USCALED 0x00000005 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_SSCALED 0x00000006 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_FLOAT 0x00000007 + +#define NVA197_SET_VAB_DATA(i) (0x1150+(i)*4) +#define NVA197_SET_VAB_DATA_V 31:0 + +#define NVA197_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVA197_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVA197_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVA197_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_SET_CT_SELECT 0x121c +#define NVA197_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVA197_SET_CT_SELECT_TARGET0 6:4 +#define NVA197_SET_CT_SELECT_TARGET1 9:7 +#define NVA197_SET_CT_SELECT_TARGET2 12:10 +#define NVA197_SET_CT_SELECT_TARGET3 15:13 +#define NVA197_SET_CT_SELECT_TARGET4 18:16 +#define NVA197_SET_CT_SELECT_TARGET5 21:19 +#define NVA197_SET_CT_SELECT_TARGET6 24:22 +#define NVA197_SET_CT_SELECT_TARGET7 27:25 + +#define NVA197_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVA197_SET_ZT_SIZE_A 0x1228 +#define NVA197_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVA197_SET_ZT_SIZE_B 0x122c +#define NVA197_SET_ZT_SIZE_B_HEIGHT 16:0 + +#define NVA197_SET_ZT_SIZE_C 0x1230 +#define NVA197_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVA197_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVA197_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVA197_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVA197_SET_SAMPLER_BINDING 0x1234 +#define NVA197_SET_SAMPLER_BINDING_V 0:0 +#define NVA197_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVA197_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVA197_DRAW_AUTO 0x123c +#define NVA197_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVA197_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVA197_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 9:0 + +#define NVA197_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVA197_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVA197_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA197_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVA197_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVA197_SET_SHADER_SCHEDULING 0x12ac +#define NVA197_SET_SHADER_SCHEDULING_MODE 0:0 +#define NVA197_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 +#define NVA197_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 + +#define NVA197_CLEAR_ZCULL_REGION 0x12c8 +#define NVA197_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVA197_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVA197_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVA197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVA197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVA197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVA197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVA197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVA197_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVA197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVA197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVA197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVA197_SET_DEPTH_TEST 0x12cc +#define NVA197_SET_DEPTH_TEST_ENABLE 0:0 +#define NVA197_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_FILL_MODE 0x12d0 +#define NVA197_SET_FILL_MODE_V 31:0 +#define NVA197_SET_FILL_MODE_V_POINT 0x00000001 +#define NVA197_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVA197_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVA197_SET_SHADE_MODE 0x12d4 +#define NVA197_SET_SHADE_MODE_V 31:0 +#define NVA197_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVA197_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVA197_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVA197_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVA197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVA197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVA197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVA197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVA197_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVA197_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVA197_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVA197_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_DEPTH_WRITE 0x12e8 +#define NVA197_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVA197_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_ALPHA_TEST 0x12ec +#define NVA197_SET_ALPHA_TEST_ENABLE 0:0 +#define NVA197_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVA197_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVA197_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVA197_DRAW_INLINE_INDEX4X8 0x1304 +#define NVA197_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVA197_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVA197_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVA197_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVA197_D3D_SET_CULL_MODE 0x1308 +#define NVA197_D3D_SET_CULL_MODE_V 31:0 +#define NVA197_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVA197_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVA197_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVA197_SET_DEPTH_FUNC 0x130c +#define NVA197_SET_DEPTH_FUNC_V 31:0 +#define NVA197_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVA197_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVA197_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA197_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA197_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVA197_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA197_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA197_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA197_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVA197_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVA197_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA197_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA197_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVA197_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA197_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA197_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA197_SET_ALPHA_REF 0x1310 +#define NVA197_SET_ALPHA_REF_V 31:0 + +#define NVA197_SET_ALPHA_FUNC 0x1314 +#define NVA197_SET_ALPHA_FUNC_V 31:0 +#define NVA197_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVA197_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVA197_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA197_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA197_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVA197_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA197_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA197_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA197_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVA197_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVA197_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA197_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA197_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVA197_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA197_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA197_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA197_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVA197_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVA197_SET_BLEND_CONST_RED 0x131c +#define NVA197_SET_BLEND_CONST_RED_V 31:0 + +#define NVA197_SET_BLEND_CONST_GREEN 0x1320 +#define NVA197_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVA197_SET_BLEND_CONST_BLUE 0x1324 +#define NVA197_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVA197_SET_BLEND_CONST_ALPHA 0x1328 +#define NVA197_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVA197_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVA197_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVA197_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVA197_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVA197_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVA197_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVA197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVA197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVA197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_BLEND_COLOR_OP 0x1340 +#define NVA197_SET_BLEND_COLOR_OP_V 31:0 +#define NVA197_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA197_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA197_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA197_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVA197_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVA197_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVA197_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA197_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA197_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVA197_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_BLEND_ALPHA_OP 0x134c +#define NVA197_SET_BLEND_ALPHA_OP_V 31:0 +#define NVA197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA197_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVA197_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVA197_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVA197_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA197_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA197_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVA197_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVA197_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVA197_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVA197_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_SINGLE_ROP_CONTROL 0x135c +#define NVA197_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVA197_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_BLEND(i) (0x1360+(i)*4) +#define NVA197_SET_BLEND_ENABLE 0:0 +#define NVA197_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVA197_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_STENCIL_TEST 0x1380 +#define NVA197_SET_STENCIL_TEST_ENABLE 0:0 +#define NVA197_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_STENCIL_OP_FAIL 0x1384 +#define NVA197_SET_STENCIL_OP_FAIL_V 31:0 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVA197_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVA197_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVA197_SET_STENCIL_OP_ZPASS 0x138c +#define NVA197_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVA197_SET_STENCIL_FUNC 0x1390 +#define NVA197_SET_STENCIL_FUNC_V 31:0 +#define NVA197_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVA197_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVA197_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA197_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA197_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVA197_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA197_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA197_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA197_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVA197_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVA197_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA197_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA197_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVA197_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA197_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA197_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA197_SET_STENCIL_FUNC_REF 0x1394 +#define NVA197_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVA197_SET_STENCIL_FUNC_MASK 0x1398 +#define NVA197_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVA197_SET_STENCIL_MASK 0x139c +#define NVA197_SET_STENCIL_MASK_V 7:0 + +#define NVA197_SET_DRAW_AUTO_START 0x13a4 +#define NVA197_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVA197_SET_PS_SATURATE 0x13a8 +#define NVA197_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVA197_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVA197_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVA197_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVA197_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVA197_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVA197_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVA197_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVA197_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 + +#define NVA197_SET_WINDOW_ORIGIN 0x13ac +#define NVA197_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVA197_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVA197_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVA197_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVA197_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVA197_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVA197_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVA197_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVA197_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVA197_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVA197_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVA197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVA197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_ALPHA_HYSTERESIS 0x1420 +#define NVA197_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NVA197_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVA197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVA197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA197_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVA197_INVALIDATE_DA_DMA_CACHE 0x142c +#define NVA197_INVALIDATE_DA_DMA_CACHE_V 0:0 + +#define NVA197_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVA197_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVA197_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVA197_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVA197_SET_PS_WARP_WATERMARKS 0x1450 +#define NVA197_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVA197_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVA197_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVA197_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVA197_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVA197_STORE_ZCULL 0x1464 +#define NVA197_STORE_ZCULL_V 0:0 + +#define NVA197_LOAD_ZCULL 0x1500 +#define NVA197_LOAD_ZCULL_V 0:0 + +#define NVA197_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVA197_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVA197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVA197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVA197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVA197_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVA197_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVA197_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVA197_SET_USER_CLIP_ENABLE 0x1510 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVA197_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVA197_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVA197_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_POINT_SIZE 0x1518 +#define NVA197_SET_POINT_SIZE_V 31:0 + +#define NVA197_SET_ZCULL_STATS 0x151c +#define NVA197_SET_ZCULL_STATS_ENABLE 0:0 +#define NVA197_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_POINT_SPRITE 0x1520 +#define NVA197_SET_POINT_SPRITE_ENABLE 0:0 +#define NVA197_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_SHADER_EXCEPTIONS 0x1528 +#define NVA197_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVA197_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVA197_CLEAR_REPORT_VALUE 0x1530 +#define NVA197_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVA197_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVA197_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVA197_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVA197_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVA197_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVA197_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 + +#define NVA197_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVA197_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVA197_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_ZT_SELECT 0x1538 +#define NVA197_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVA197_SET_RENDER_ENABLE_A 0x1550 +#define NVA197_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_RENDER_ENABLE_B 0x1554 +#define NVA197_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_RENDER_ENABLE_C 0x1558 +#define NVA197_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVA197_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA197_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA197_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA197_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA197_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA197_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVA197_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVA197_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVA197_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVA197_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVA197_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVA197_SET_ANTI_ALIASED_LINE 0x1570 +#define NVA197_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVA197_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_TEX_HEADER_POOL_A 0x1574 +#define NVA197_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_TEX_HEADER_POOL_B 0x1578 +#define NVA197_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_TEX_HEADER_POOL_C 0x157c +#define NVA197_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVA197_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVA197_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVA197_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVA197_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVA197_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVA197_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVA197_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVA197_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVA197_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA197_SET_SRGB_WRITE 0x15b8 +#define NVA197_SET_SRGB_WRITE_ENABLE 0:0 +#define NVA197_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_DEPTH_BIAS 0x15bc +#define NVA197_SET_DEPTH_BIAS_V 31:0 + +#define NVA197_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVA197_SET_RT_LAYER 0x15cc +#define NVA197_SET_RT_LAYER_V 15:0 +#define NVA197_SET_RT_LAYER_CONTROL 16:16 +#define NVA197_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVA197_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVA197_SET_ANTI_ALIAS 0x15d0 +#define NVA197_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVA197_SET_EDGE_FLAG 0x15e4 +#define NVA197_SET_EDGE_FLAG_V 0:0 +#define NVA197_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVA197_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVA197_DRAW_INLINE_INDEX 0x15e8 +#define NVA197_DRAW_INLINE_INDEX_V 31:0 + +#define NVA197_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVA197_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVA197_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVA197_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVA197_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVA197_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVA197_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVA197_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVA197_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVA197_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVA197_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVA197_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVA197_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVA197_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVA197_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVA197_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVA197_SET_POINT_SPRITE_SELECT 0x1604 +#define NVA197_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVA197_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVA197_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVA197_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVA197_SET_PROGRAM_REGION_A 0x1608 +#define NVA197_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVA197_SET_PROGRAM_REGION_B 0x160c +#define NVA197_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVA197_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVA197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVA197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVA197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVA197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVA197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVA197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVA197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVA197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVA197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVA197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVA197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVA197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVA197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVA197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVA197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVA197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVA197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVA197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVA197_END 0x1614 +#define NVA197_END_V 0:0 + +#define NVA197_BEGIN 0x1618 +#define NVA197_BEGIN_OP 15:0 +#define NVA197_BEGIN_OP_POINTS 0x00000000 +#define NVA197_BEGIN_OP_LINES 0x00000001 +#define NVA197_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVA197_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVA197_BEGIN_OP_TRIANGLES 0x00000004 +#define NVA197_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVA197_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVA197_BEGIN_OP_QUADS 0x00000007 +#define NVA197_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVA197_BEGIN_OP_POLYGON 0x00000009 +#define NVA197_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVA197_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVA197_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_BEGIN_OP_PATCH 0x0000000E +#define NVA197_BEGIN_PRIMITIVE_ID 24:24 +#define NVA197_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVA197_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVA197_BEGIN_INSTANCE_ID 27:26 +#define NVA197_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVA197_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVA197_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVA197_BEGIN_SPLIT_MODE 30:29 +#define NVA197_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVA197_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVA197_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVA197_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 + +#define NVA197_SET_VERTEX_ID_COPY 0x161c +#define NVA197_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVA197_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVA197_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVA197_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVA197_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVA197_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVA197_LOAD_PRIMITIVE_ID 0x1624 +#define NVA197_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVA197_SET_SHADER_BASED_CULL 0x162c +#define NVA197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVA197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVA197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVA197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_CLASS_VERSION 0x1638 +#define NVA197_SET_CLASS_VERSION_CURRENT 15:0 +#define NVA197_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA197_SET_VAB_PAGE 0x163c +#define NVA197_SET_VAB_PAGE_READ_SELECT 0:0 +#define NVA197_SET_VAB_PAGE_READ_SELECT_PAGES_0_AND_1 0x00000000 +#define NVA197_SET_VAB_PAGE_READ_SELECT_PAGES_0_AND_2 0x00000001 + +#define NVA197_DRAW_INLINE_VERTEX 0x1640 +#define NVA197_DRAW_INLINE_VERTEX_V 31:0 + +#define NVA197_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVA197_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVA197_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVA197_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVA197_SET_DA_OUTPUT 0x164c +#define NVA197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVA197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVA197_SET_ANTI_ALIASED_POINT 0x1658 +#define NVA197_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVA197_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_POINT_CENTER_MODE 0x165c +#define NVA197_SET_POINT_CENTER_MODE_V 31:0 +#define NVA197_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVA197_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVA197_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVA197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVA197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVA197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVA197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVA197_SET_LINE_STIPPLE 0x166c +#define NVA197_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVA197_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVA197_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVA197_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVA197_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVA197_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVA197_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVA197_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVA197_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVA197_SET_PROVOKING_VERTEX 0x1684 +#define NVA197_SET_PROVOKING_VERTEX_V 0:0 +#define NVA197_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVA197_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVA197_SET_TWO_SIDED_LIGHT 0x1688 +#define NVA197_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVA197_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_POLYGON_STIPPLE 0x168c +#define NVA197_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVA197_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_SHADER_CONTROL 0x1690 +#define NVA197_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVA197_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVA197_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVA197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVA197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVA197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVA197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVA197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVA197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVA197_LAUNCH_VERTEX 0x169c +#define NVA197_LAUNCH_VERTEX_V 0:0 + +#define NVA197_CHECK_CLASS_VERSION 0x16a0 +#define NVA197_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVA197_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA197_SET_SPH_VERSION 0x16a4 +#define NVA197_SET_SPH_VERSION_CURRENT 15:0 +#define NVA197_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA197_CHECK_SPH_VERSION 0x16a8 +#define NVA197_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVA197_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVA197_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVA197_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVA197_SET_AAM_VERSION 0x1790 +#define NVA197_SET_AAM_VERSION_CURRENT 15:0 +#define NVA197_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA197_CHECK_AAM_VERSION 0x1794 +#define NVA197_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVA197_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA197_SET_ZT_LAYER 0x179c +#define NVA197_SET_ZT_LAYER_OFFSET 15:0 + +#define NVA197_SET_VAB_MEMORY_AREA_A 0x17bc +#define NVA197_SET_VAB_MEMORY_AREA_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_VAB_MEMORY_AREA_B 0x17c0 +#define NVA197_SET_VAB_MEMORY_AREA_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_VAB_MEMORY_AREA_C 0x17c4 +#define NVA197_SET_VAB_MEMORY_AREA_C_SIZE 1:0 +#define NVA197_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_64K 0x00000001 +#define NVA197_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_128K 0x00000002 +#define NVA197_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_256K 0x00000003 + +#define NVA197_SET_INDEX_BUFFER_A 0x17c8 +#define NVA197_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVA197_SET_INDEX_BUFFER_B 0x17cc +#define NVA197_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVA197_SET_INDEX_BUFFER_C 0x17d0 +#define NVA197_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVA197_SET_INDEX_BUFFER_D 0x17d4 +#define NVA197_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVA197_SET_INDEX_BUFFER_E 0x17d8 +#define NVA197_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVA197_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVA197_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVA197_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVA197_SET_INDEX_BUFFER_F 0x17dc +#define NVA197_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVA197_DRAW_INDEX_BUFFER 0x17e0 +#define NVA197_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVA197_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVA197_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVA197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVA197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVA197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVA197_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVA197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVA197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVA197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVA197_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVA197_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVA197_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVA197_OGL_SET_CULL 0x1918 +#define NVA197_OGL_SET_CULL_ENABLE 0:0 +#define NVA197_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVA197_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVA197_OGL_SET_FRONT_FACE 0x191c +#define NVA197_OGL_SET_FRONT_FACE_V 31:0 +#define NVA197_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVA197_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVA197_OGL_SET_CULL_FACE 0x1920 +#define NVA197_OGL_SET_CULL_FACE_V 31:0 +#define NVA197_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVA197_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVA197_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVA197_SET_VIEWPORT_PIXEL 0x1924 +#define NVA197_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVA197_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVA197_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVA197_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVA197_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVA197_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVA197_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVA197_INVALIDATE_CONSTANT_BUFFER_CACHE 0x1930 +#define NVA197_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2 0:0 +#define NVA197_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_FALSE 0x00000000 +#define NVA197_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_TRUE 0x00000001 + +#define NVA197_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVA197_SET_USER_CLIP_OP 0x1940 +#define NVA197_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVA197_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVA197_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVA197_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVA197_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVA197_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVA197_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVA197_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVA197_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVA197_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVA197_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVA197_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVA197_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVA197_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVA197_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVA197_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVA197_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVA197_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVA197_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVA197_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVA197_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVA197_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVA197_INVALIDATE_ZCULL 0x1958 +#define NVA197_INVALIDATE_ZCULL_V 31:0 +#define NVA197_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVA197_SET_ZCULL 0x1968 +#define NVA197_SET_ZCULL_Z_ENABLE 0:0 +#define NVA197_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVA197_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_ZCULL_BOUNDS 0x196c +#define NVA197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVA197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVA197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVA197_ZCULL_SYNC 0x1978 +#define NVA197_ZCULL_SYNC_V 31:0 + +#define NVA197_SET_CLIP_ID_TEST 0x197c +#define NVA197_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVA197_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVA197_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVA197_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVA197_SET_CLIP_ID 0x1984 +#define NVA197_SET_CLIP_ID_V 31:0 + +#define NVA197_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVA197_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVA197_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVA197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVA197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVA197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVA197_SET_LOGIC_OP 0x19c4 +#define NVA197_SET_LOGIC_OP_ENABLE 0:0 +#define NVA197_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVA197_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_LOGIC_OP_FUNC 0x19c8 +#define NVA197_SET_LOGIC_OP_FUNC_V 31:0 +#define NVA197_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVA197_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVA197_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVA197_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVA197_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVA197_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVA197_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVA197_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVA197_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVA197_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVA197_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVA197_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVA197_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVA197_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVA197_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVA197_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVA197_SET_Z_COMPRESSION 0x19cc +#define NVA197_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVA197_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVA197_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVA197_CLEAR_SURFACE 0x19d0 +#define NVA197_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVA197_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVA197_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVA197_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVA197_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVA197_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVA197_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVA197_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVA197_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVA197_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVA197_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVA197_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVA197_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVA197_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVA197_SET_CT_WRITE_R_ENABLE 0:0 +#define NVA197_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVA197_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVA197_SET_CT_WRITE_G_ENABLE 4:4 +#define NVA197_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVA197_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVA197_SET_CT_WRITE_B_ENABLE 8:8 +#define NVA197_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVA197_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVA197_SET_CT_WRITE_A_ENABLE 12:12 +#define NVA197_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVA197_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVA197_PIPE_NOP 0x1a2c +#define NVA197_PIPE_NOP_V 31:0 + +#define NVA197_SET_SPARE00 0x1a30 +#define NVA197_SET_SPARE00_V 31:0 + +#define NVA197_SET_SPARE01 0x1a34 +#define NVA197_SET_SPARE01_V 31:0 + +#define NVA197_SET_SPARE02 0x1a38 +#define NVA197_SET_SPARE02_V 31:0 + +#define NVA197_SET_SPARE03 0x1a3c +#define NVA197_SET_SPARE03_V 31:0 + +#define NVA197_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVA197_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVA197_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVA197_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA197_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVA197_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVA197_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVA197_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVA197_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVA197_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVA197_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVA197_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVA197_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVA197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVA197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVA197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVA197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVA197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVA197_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVA197_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVA197_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVA197_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVA197_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVA197_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVA197_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVA197_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVA197_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVA197_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVA197_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVA197_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVA197_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVA197_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVA197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVA197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVA197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVA197_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVA197_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVA197_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVA197_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVA197_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVA197_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVA197_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVA197_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVA197_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVA197_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVA197_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVA197_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVA197_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVA197_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVA197_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVA197_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVA197_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVA197_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVA197_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NVA197_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NVA197_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVA197_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVA197_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVA197_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NVA197_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVA197_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVA197_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NVA197_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVA197_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NVA197_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NVA197_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVA197_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVA197_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVA197_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVA197_SET_FALCON00 0x2300 +#define NVA197_SET_FALCON00_V 31:0 + +#define NVA197_SET_FALCON01 0x2304 +#define NVA197_SET_FALCON01_V 31:0 + +#define NVA197_SET_FALCON02 0x2308 +#define NVA197_SET_FALCON02_V 31:0 + +#define NVA197_SET_FALCON03 0x230c +#define NVA197_SET_FALCON03_V 31:0 + +#define NVA197_SET_FALCON04 0x2310 +#define NVA197_SET_FALCON04_V 31:0 + +#define NVA197_SET_FALCON05 0x2314 +#define NVA197_SET_FALCON05_V 31:0 + +#define NVA197_SET_FALCON06 0x2318 +#define NVA197_SET_FALCON06_V 31:0 + +#define NVA197_SET_FALCON07 0x231c +#define NVA197_SET_FALCON07_V 31:0 + +#define NVA197_SET_FALCON08 0x2320 +#define NVA197_SET_FALCON08_V 31:0 + +#define NVA197_SET_FALCON09 0x2324 +#define NVA197_SET_FALCON09_V 31:0 + +#define NVA197_SET_FALCON10 0x2328 +#define NVA197_SET_FALCON10_V 31:0 + +#define NVA197_SET_FALCON11 0x232c +#define NVA197_SET_FALCON11_V 31:0 + +#define NVA197_SET_FALCON12 0x2330 +#define NVA197_SET_FALCON12_V 31:0 + +#define NVA197_SET_FALCON13 0x2334 +#define NVA197_SET_FALCON13_V 31:0 + +#define NVA197_SET_FALCON14 0x2338 +#define NVA197_SET_FALCON14_V 31:0 + +#define NVA197_SET_FALCON15 0x233c +#define NVA197_SET_FALCON15_V 31:0 + +#define NVA197_SET_FALCON16 0x2340 +#define NVA197_SET_FALCON16_V 31:0 + +#define NVA197_SET_FALCON17 0x2344 +#define NVA197_SET_FALCON17_V 31:0 + +#define NVA197_SET_FALCON18 0x2348 +#define NVA197_SET_FALCON18_V 31:0 + +#define NVA197_SET_FALCON19 0x234c +#define NVA197_SET_FALCON19_V 31:0 + +#define NVA197_SET_FALCON20 0x2350 +#define NVA197_SET_FALCON20_V 31:0 + +#define NVA197_SET_FALCON21 0x2354 +#define NVA197_SET_FALCON21_V 31:0 + +#define NVA197_SET_FALCON22 0x2358 +#define NVA197_SET_FALCON22_V 31:0 + +#define NVA197_SET_FALCON23 0x235c +#define NVA197_SET_FALCON23_V 31:0 + +#define NVA197_SET_FALCON24 0x2360 +#define NVA197_SET_FALCON24_V 31:0 + +#define NVA197_SET_FALCON25 0x2364 +#define NVA197_SET_FALCON25_V 31:0 + +#define NVA197_SET_FALCON26 0x2368 +#define NVA197_SET_FALCON26_V 31:0 + +#define NVA197_SET_FALCON27 0x236c +#define NVA197_SET_FALCON27_V 31:0 + +#define NVA197_SET_FALCON28 0x2370 +#define NVA197_SET_FALCON28_V 31:0 + +#define NVA197_SET_FALCON29 0x2374 +#define NVA197_SET_FALCON29_V 31:0 + +#define NVA197_SET_FALCON30 0x2378 +#define NVA197_SET_FALCON30_V 31:0 + +#define NVA197_SET_FALCON31 0x237c +#define NVA197_SET_FALCON31_V 31:0 + +#define NVA197_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVA197_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVA197_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVA197_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVA197_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVA197_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVA197_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVA197_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVA197_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVA197_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVA197_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVA197_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVA197_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVA197_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVA197_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVA197_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVA197_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVA197_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVA197_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVA197_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVA197_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA197_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA197_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVA197_SET_COLOR_CLAMP 0x2600 +#define NVA197_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVA197_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVA197_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVA197_NOOP_X_X_X_SET_VALVE 0x2604 +#define NVA197_NOOP_X_X_X_SET_VALVE_HIGHER_PRIORITY 0:0 +#define NVA197_NOOP_X_X_X_SET_VALVE_HIGHER_PRIORITY_COMPUTE 0x00000000 +#define NVA197_NOOP_X_X_X_SET_VALVE_HIGHER_PRIORITY_GRAPHICS 0x00000001 + +#define NVA197_SET_BINDLESS_TEXTURE 0x2608 +#define NVA197_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVA197_SET_TRAP_HANDLER 0x260c +#define NVA197_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVA197_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVA197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVA197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVA197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVA197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVA197_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVA197_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVA197_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVA197_CALL_MME_MACRO_V 31:0 + +#define NVA197_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVA197_CALL_MME_DATA_V 31:0 + +#endif /* _cl_kepler_b_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cla1c0.h b/userspace/sdks/nv525/nvidia/inc/class/cla1c0.h new file mode 100644 index 0000000..2b904c0 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cla1c0.h @@ -0,0 +1,669 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_kepler_compute_b_h_ +#define _cl_kepler_compute_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl kepler_compute_b */ + +#include "nvtypes.h" + +#define KEPLER_COMPUTE_B 0xA1C0 + +#define NVA1C0_SET_OBJECT 0x0000 +#define NVA1C0_SET_OBJECT_CLASS_ID 15:0 +#define NVA1C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVA1C0_NO_OPERATION 0x0100 +#define NVA1C0_NO_OPERATION_V 31:0 + +#define NVA1C0_SET_NOTIFY_A 0x0104 +#define NVA1C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_SET_NOTIFY_B 0x0108 +#define NVA1C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_NOTIFY 0x010c +#define NVA1C0_NOTIFY_TYPE 31:0 +#define NVA1C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVA1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVA1C0_WAIT_FOR_IDLE 0x0110 +#define NVA1C0_WAIT_FOR_IDLE_V 31:0 + +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA1C0_SEND_GO_IDLE 0x013c +#define NVA1C0_SEND_GO_IDLE_V 31:0 + +#define NVA1C0_PM_TRIGGER 0x0140 +#define NVA1C0_PM_TRIGGER_V 31:0 + +#define NVA1C0_PM_TRIGGER_WFI 0x0144 +#define NVA1C0_PM_TRIGGER_WFI_V 31:0 + +#define NVA1C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVA1C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVA1C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVA1C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVA1C0_LINE_LENGTH_IN 0x0180 +#define NVA1C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVA1C0_LINE_COUNT 0x0184 +#define NVA1C0_LINE_COUNT_VALUE 31:0 + +#define NVA1C0_OFFSET_OUT_UPPER 0x0188 +#define NVA1C0_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVA1C0_OFFSET_OUT 0x018c +#define NVA1C0_OFFSET_OUT_VALUE 31:0 + +#define NVA1C0_PITCH_OUT 0x0190 +#define NVA1C0_PITCH_OUT_VALUE 31:0 + +#define NVA1C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVA1C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVA1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVA1C0_SET_DST_WIDTH 0x0198 +#define NVA1C0_SET_DST_WIDTH_V 31:0 + +#define NVA1C0_SET_DST_HEIGHT 0x019c +#define NVA1C0_SET_DST_HEIGHT_V 31:0 + +#define NVA1C0_SET_DST_DEPTH 0x01a0 +#define NVA1C0_SET_DST_DEPTH_V 31:0 + +#define NVA1C0_SET_DST_LAYER 0x01a4 +#define NVA1C0_SET_DST_LAYER_V 31:0 + +#define NVA1C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVA1C0_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVA1C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVA1C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVA1C0_LAUNCH_DMA 0x01b0 +#define NVA1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVA1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVA1C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVA1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVA1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVA1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVA1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVA1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVA1C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVA1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA1C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVA1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVA1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVA1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVA1C0_LOAD_INLINE_DATA 0x01b4 +#define NVA1C0_LOAD_INLINE_DATA_V 31:0 + +#define NVA1C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVA1C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVA1C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVA1C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA1C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVA1C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVA1C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVA1C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVA1C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVA1C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVA1C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVA1C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVA1C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVA1C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVA1C0_PERFMON_TRANSFER 0x0210 +#define NVA1C0_PERFMON_TRANSFER_V 31:0 + +#define NVA1C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVA1C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA1C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVA1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVA1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVA1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVA1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVA1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVA1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVA1C0_SET_CWD_CONTROL 0x0240 +#define NVA1C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVA1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVA1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVA1C0_SET_CWD_REF_COUNTER 0x0248 +#define NVA1C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVA1C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVA1C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVA1C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVA1C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA1C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVA1C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVA1C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA1C0_SET_QMD_VERSION 0x0288 +#define NVA1C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVA1C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA1C0_CHECK_QMD_VERSION 0x0290 +#define NVA1C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVA1C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA1C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVA1C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVA1C0_SEND_PCAS_A 0x02b4 +#define NVA1C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVA1C0_SEND_PCAS_B 0x02b8 +#define NVA1C0_SEND_PCAS_B_FROM 23:0 +#define NVA1C0_SEND_PCAS_B_DELTA 31:24 + +#define NVA1C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVA1C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVA1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVA1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVA1C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVA1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVA1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE 0x02c4 +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE 0:0 +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE_TRUE 0x00000001 +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_HEADER_INDEX 23:4 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVA1C0_SET_SPA_VERSION 0x0310 +#define NVA1C0_SET_SPA_VERSION_MINOR 7:0 +#define NVA1C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVA1C0_SET_FALCON00 0x0500 +#define NVA1C0_SET_FALCON00_V 31:0 + +#define NVA1C0_SET_FALCON01 0x0504 +#define NVA1C0_SET_FALCON01_V 31:0 + +#define NVA1C0_SET_FALCON02 0x0508 +#define NVA1C0_SET_FALCON02_V 31:0 + +#define NVA1C0_SET_FALCON03 0x050c +#define NVA1C0_SET_FALCON03_V 31:0 + +#define NVA1C0_SET_FALCON04 0x0510 +#define NVA1C0_SET_FALCON04_V 31:0 + +#define NVA1C0_SET_FALCON05 0x0514 +#define NVA1C0_SET_FALCON05_V 31:0 + +#define NVA1C0_SET_FALCON06 0x0518 +#define NVA1C0_SET_FALCON06_V 31:0 + +#define NVA1C0_SET_FALCON07 0x051c +#define NVA1C0_SET_FALCON07_V 31:0 + +#define NVA1C0_SET_FALCON08 0x0520 +#define NVA1C0_SET_FALCON08_V 31:0 + +#define NVA1C0_SET_FALCON09 0x0524 +#define NVA1C0_SET_FALCON09_V 31:0 + +#define NVA1C0_SET_FALCON10 0x0528 +#define NVA1C0_SET_FALCON10_V 31:0 + +#define NVA1C0_SET_FALCON11 0x052c +#define NVA1C0_SET_FALCON11_V 31:0 + +#define NVA1C0_SET_FALCON12 0x0530 +#define NVA1C0_SET_FALCON12_V 31:0 + +#define NVA1C0_SET_FALCON13 0x0534 +#define NVA1C0_SET_FALCON13_V 31:0 + +#define NVA1C0_SET_FALCON14 0x0538 +#define NVA1C0_SET_FALCON14_V 31:0 + +#define NVA1C0_SET_FALCON15 0x053c +#define NVA1C0_SET_FALCON15_V 31:0 + +#define NVA1C0_SET_FALCON16 0x0540 +#define NVA1C0_SET_FALCON16_V 31:0 + +#define NVA1C0_SET_FALCON17 0x0544 +#define NVA1C0_SET_FALCON17_V 31:0 + +#define NVA1C0_SET_FALCON18 0x0548 +#define NVA1C0_SET_FALCON18_V 31:0 + +#define NVA1C0_SET_FALCON19 0x054c +#define NVA1C0_SET_FALCON19_V 31:0 + +#define NVA1C0_SET_FALCON20 0x0550 +#define NVA1C0_SET_FALCON20_V 31:0 + +#define NVA1C0_SET_FALCON21 0x0554 +#define NVA1C0_SET_FALCON21_V 31:0 + +#define NVA1C0_SET_FALCON22 0x0558 +#define NVA1C0_SET_FALCON22_V 31:0 + +#define NVA1C0_SET_FALCON23 0x055c +#define NVA1C0_SET_FALCON23_V 31:0 + +#define NVA1C0_SET_FALCON24 0x0560 +#define NVA1C0_SET_FALCON24_V 31:0 + +#define NVA1C0_SET_FALCON25 0x0564 +#define NVA1C0_SET_FALCON25_V 31:0 + +#define NVA1C0_SET_FALCON26 0x0568 +#define NVA1C0_SET_FALCON26_V 31:0 + +#define NVA1C0_SET_FALCON27 0x056c +#define NVA1C0_SET_FALCON27_V 31:0 + +#define NVA1C0_SET_FALCON28 0x0570 +#define NVA1C0_SET_FALCON28_V 31:0 + +#define NVA1C0_SET_FALCON29 0x0574 +#define NVA1C0_SET_FALCON29_V 31:0 + +#define NVA1C0_SET_FALCON30 0x0578 +#define NVA1C0_SET_FALCON30_V 31:0 + +#define NVA1C0_SET_FALCON31 0x057c +#define NVA1C0_SET_FALCON31_V 31:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVA1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVA1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVA1C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVA1C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVA1C0_SET_SPARE_NOOP12 0x0f44 +#define NVA1C0_SET_SPARE_NOOP12_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP13 0x0f48 +#define NVA1C0_SET_SPARE_NOOP13_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP14 0x0f4c +#define NVA1C0_SET_SPARE_NOOP14_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP15 0x0f50 +#define NVA1C0_SET_SPARE_NOOP15_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP00 0x1040 +#define NVA1C0_SET_SPARE_NOOP00_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP01 0x1044 +#define NVA1C0_SET_SPARE_NOOP01_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP02 0x1048 +#define NVA1C0_SET_SPARE_NOOP02_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP03 0x104c +#define NVA1C0_SET_SPARE_NOOP03_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP04 0x1050 +#define NVA1C0_SET_SPARE_NOOP04_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP05 0x1054 +#define NVA1C0_SET_SPARE_NOOP05_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP06 0x1058 +#define NVA1C0_SET_SPARE_NOOP06_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP07 0x105c +#define NVA1C0_SET_SPARE_NOOP07_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP08 0x1060 +#define NVA1C0_SET_SPARE_NOOP08_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP09 0x1064 +#define NVA1C0_SET_SPARE_NOOP09_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP10 0x1068 +#define NVA1C0_SET_SPARE_NOOP10_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP11 0x106c +#define NVA1C0_SET_SPARE_NOOP11_V 31:0 + +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVA1C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVA1C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVA1C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVA1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVA1C0_SET_RENDER_ENABLE_A 0x1550 +#define NVA1C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_RENDER_ENABLE_B 0x1554 +#define NVA1C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_RENDER_ENABLE_C 0x1558 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA1C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVA1C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVA1C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVA1C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVA1C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVA1C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVA1C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVA1C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVA1C0_SET_PROGRAM_REGION_A 0x1608 +#define NVA1C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_SET_PROGRAM_REGION_B 0x160c +#define NVA1C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_SET_SHADER_CONTROL 0x1690 +#define NVA1C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVA1C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVA1C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 + +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVA1C0_PIPE_NOP 0x1a2c +#define NVA1C0_PIPE_NOP_V 31:0 + +#define NVA1C0_SET_SPARE00 0x1a30 +#define NVA1C0_SET_SPARE00_V 31:0 + +#define NVA1C0_SET_SPARE01 0x1a34 +#define NVA1C0_SET_SPARE01_V 31:0 + +#define NVA1C0_SET_SPARE02 0x1a38 +#define NVA1C0_SET_SPARE02_V 31:0 + +#define NVA1C0_SET_SPARE03 0x1a3c +#define NVA1C0_SET_SPARE03_V 31:0 + +#define NVA1C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVA1C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVA1C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVA1C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA1C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVA1C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVA1C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVA1C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVA1C0_SET_TRAP_HANDLER 0x260c +#define NVA1C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVA1C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVA1C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_kepler_compute_b_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cla26f.h b/userspace/sdks/nv525/nvidia/inc/class/cla26f.h new file mode 100644 index 0000000..807c5cf --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cla26f.h @@ -0,0 +1,254 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cla26f_h_ +#define _cla26f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class KEPLER_CHANNEL_GPFIFO */ +/* + * Documentation for KEPLER_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + */ +#define KEPLER_CHANNEL_GPFIFO_C (0x0000A26F) + +/* pio method data structure */ +typedef volatile struct _cla26f_tag0 { + NvV32 Reserved00[0x7c0]; +} NvA26FTypedef, KEPLER_ChannelGPFifoC; +#define NVA26F_TYPEDEF KEPLER_CHANNELChannelGPFifo +/* dma flow control data structure */ +typedef volatile struct _cla26f_tag1 { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} NvA26FControl, KeplerCControlGPFifo; +/* fields and values */ +#define NVA26F_NUMBER_OF_SUBCHANNELS (8) +#define NVA26F_SET_OBJECT (0x00000000) +#define NVA26F_SET_OBJECT_NVCLASS 15:0 +#define NVA26F_SET_OBJECT_ENGINE 20:16 +#define NVA26F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVA26F_ILLEGAL (0x00000004) +#define NVA26F_ILLEGAL_HANDLE 31:0 +#define NVA26F_NOP (0x00000008) +#define NVA26F_NOP_HANDLE 31:0 +#define NVA26F_SEMAPHOREA (0x00000010) +#define NVA26F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVA26F_SEMAPHOREB (0x00000014) +#define NVA26F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVA26F_SEMAPHOREC (0x00000018) +#define NVA26F_SEMAPHOREC_PAYLOAD 31:0 +#define NVA26F_SEMAPHORED (0x0000001C) +#define NVA26F_SEMAPHORED_OPERATION 3:0 +#define NVA26F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVA26F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVA26F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVA26F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVA26F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVA26F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVA26F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVA26F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVA26F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVA26F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVA26F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVA26F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVA26F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVA26F_NON_STALL_INTERRUPT (0x00000020) +#define NVA26F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVA26F_FB_FLUSH (0x00000024) +#define NVA26F_FB_FLUSH_HANDLE 31:0 +#define NVA26F_MEM_OP_A (0x00000028) +#define NVA26F_MEM_OP_A_OPERAND_LOW 31:2 +#define NVA26F_MEM_OP_A_TLB_INVALIDATE_ADDR 29:2 +#define NVA26F_MEM_OP_A_TLB_INVALIDATE_TARGET 31:30 +#define NVA26F_MEM_OP_A_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000 +#define NVA26F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002 +#define NVA26F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 +#define NVA26F_MEM_OP_B (0x0000002c) +#define NVA26F_MEM_OP_B_OPERAND_HIGH 7:0 +#define NVA26F_MEM_OP_B_OPERATION 31:27 +#define NVA26F_MEM_OP_B_OPERATION_SYSMEMBAR_FLUSH 0x00000005 +#define NVA26F_MEM_OP_B_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVA26F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e +#define NVA26F_MEM_OP_B_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVA26F_MEM_OP_B_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB 0:0 +#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ALL 0x00000001 +#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC 1:1 +#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVA26F_SET_REFERENCE (0x00000050) +#define NVA26F_SET_REFERENCE_COUNT 31:0 +#define NVA26F_SYNCPOINTA (0x00000070) +#define NVA26F_SYNCPOINTA_PAYLOAD 31:0 +#define NVA26F_SYNCPOINTB (0x00000074) +#define NVA26F_SYNCPOINTB_OPERATION 1:0 +#define NVA26F_SYNCPOINTB_OPERATION_WAIT 0x00000000 +#define NVA26F_SYNCPOINTB_OPERATION_INCR 0x00000001 +#define NVA26F_SYNCPOINTB_OPERATION_BASE_ADD 0x00000002 +#define NVA26F_SYNCPOINTB_OPERATION_BASE_WRITE 0x00000003 +#define NVA26F_SYNCPOINTB_WAIT_SWITCH 4:4 +#define NVA26F_SYNCPOINTB_WAIT_SWITCH_DIS 0x00000000 +#define NVA26F_SYNCPOINTB_WAIT_SWITCH_EN 0x00000001 +#define NVA26F_SYNCPOINTB_BASE 5:5 +#define NVA26F_SYNCPOINTB_BASE_DIS 0x00000000 +#define NVA26F_SYNCPOINTB_BASE_EN 0x00000001 +#define NVA26F_SYNCPOINTB_SYNCPT_INDEX 15:8 +#define NVA26F_SYNCPOINTB_BASE_INDEX 25:20 +#define NVA26F_WFI (0x00000078) +#define NVA26F_WFI_HANDLE 31:0 +#define NVA26F_CRC_CHECK (0x0000007c) +#define NVA26F_CRC_CHECK_VALUE 31:0 +#define NVA26F_YIELD (0x00000080) +#define NVA26F_YIELD_OP 1:0 +#define NVA26F_YIELD_OP_NOP 0x00000000 + +/* GPFIFO entry format */ +#define NVA26F_GP_ENTRY__SIZE 8 +#define NVA26F_GP_ENTRY0_FETCH 0:0 +#define NVA26F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVA26F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVA26F_GP_ENTRY0_GET 31:2 +#define NVA26F_GP_ENTRY0_OPERAND 31:0 +#define NVA26F_GP_ENTRY1_GET_HI 7:0 +#define NVA26F_GP_ENTRY1_PRIV 8:8 +#define NVA26F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NVA26F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NVA26F_GP_ENTRY1_LEVEL 9:9 +#define NVA26F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVA26F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVA26F_GP_ENTRY1_LENGTH 30:10 +#define NVA26F_GP_ENTRY1_SYNC 31:31 +#define NVA26F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVA26F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVA26F_GP_ENTRY1_OPCODE 7:0 +#define NVA26F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVA26F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVA26F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVA26F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVA26F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVA26F_DMA_METHOD_ADDRESS 11:0 +#define NVA26F_DMA_SUBDEVICE_MASK 15:4 +#define NVA26F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVA26F_DMA_TERT_OP 17:16 +#define NVA26F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVA26F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVA26F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVA26F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVA26F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVA26F_DMA_METHOD_COUNT_OLD 28:18 +#define NVA26F_DMA_METHOD_COUNT 28:16 +#define NVA26F_DMA_IMMD_DATA 28:16 +#define NVA26F_DMA_SEC_OP 31:29 +#define NVA26F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVA26F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVA26F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVA26F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVA26F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVA26F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVA26F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVA26F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVA26F_DMA_INCR_ADDRESS 11:0 +#define NVA26F_DMA_INCR_SUBCHANNEL 15:13 +#define NVA26F_DMA_INCR_COUNT 28:16 +#define NVA26F_DMA_INCR_OPCODE 31:29 +#define NVA26F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVA26F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVA26F_DMA_NONINCR_ADDRESS 11:0 +#define NVA26F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVA26F_DMA_NONINCR_COUNT 28:16 +#define NVA26F_DMA_NONINCR_OPCODE 31:29 +#define NVA26F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVA26F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVA26F_DMA_ONEINCR_ADDRESS 11:0 +#define NVA26F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVA26F_DMA_ONEINCR_COUNT 28:16 +#define NVA26F_DMA_ONEINCR_OPCODE 31:29 +#define NVA26F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVA26F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVA26F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVA26F_DMA_IMMD_ADDRESS 11:0 +#define NVA26F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVA26F_DMA_IMMD_DATA 28:16 +#define NVA26F_DMA_IMMD_OPCODE 31:29 +#define NVA26F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVA26F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVA26F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA26F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVA26F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVA26F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA26F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVA26F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA26F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVA26F_DMA_ENDSEG_OPCODE 31:29 +#define NVA26F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVA26F_DMA_ADDRESS 12:2 +#define NVA26F_DMA_SUBCH 15:13 +#define NVA26F_DMA_OPCODE3 17:16 +#define NVA26F_DMA_OPCODE3_NONE (0x00000000) +#define NVA26F_DMA_COUNT 28:18 +#define NVA26F_DMA_OPCODE 31:29 +#define NVA26F_DMA_OPCODE_METHOD (0x00000000) +#define NVA26F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVA26F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cla26f_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clb069.h b/userspace/sdks/nv525/nvidia/inc/class/clb069.h new file mode 100644 index 0000000..94140dd --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clb069.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clb069_h_ +#define _clb069_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define MAXWELL_FAULT_BUFFER_A (0xb069) + +#define NVB069_FAULT_BUF_ENTRY 0x0000001f:0x00000000 +#define NVB069_FAULT_BUF_SIZE 32 +#define NVB069_FAULT_BUF_ENTRY_INST_APERTURE MW((9+0*32):(0*32+8)) +#define NVB069_FAULT_BUF_ENTRY_INST_APERTURE_VID_MEM 0x00000000 +#define NVB069_FAULT_BUF_ENTRY_INST_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVB069_FAULT_BUF_ENTRY_INST_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVB069_FAULT_BUF_ENTRY_INST_LO MW((31+0*32):(0*32+12)) +#define NVB069_FAULT_BUF_ENTRY_INST_HI MW((31+1*32):(1*32+0)) +#define NVB069_FAULT_BUF_ENTRY_INST MW((31+1*32):(0*32+12)) +#define NVB069_FAULT_BUF_ENTRY_ADDR_LO MW((31+2*32):(2*32+0)) +#define NVB069_FAULT_BUF_ENTRY_ADDR_HI MW((31+3*32):(3*32+0)) +#define NVB069_FAULT_BUF_ENTRY_ADDR MW((31+3*32):(2*32+0)) +#define NVB069_FAULT_BUF_ENTRY_TIMESTAMP_LO MW((31+4*32):(4*32+0)) +#define NVB069_FAULT_BUF_ENTRY_TIMESTAMP_HI MW((31+5*32):(5*32+0)) +#define NVB069_FAULT_BUF_ENTRY_TIMESTAMP MW((31+5*32):(4*32+0)) +#define NVB069_FAULT_BUF_ENTRY_RESERVED MW((31+6*32):(6*32+0)) +#define NVB069_FAULT_BUF_ENTRY_FAULT_TYPE MW((4+7*32):(7*32+0)) +#define NVB069_FAULT_BUF_ENTRY_CLIENT MW((14+7*32):(7*32+8)) +#define NVB069_FAULT_BUF_ENTRY_ACCESS_TYPE MW((18+7*32):(7*32+16)) +#define NVB069_FAULT_BUF_ENTRY_MMU_CLIENT_TYPE MW((20+7*32):(7*32+20)) +#define NVB069_FAULT_BUF_ENTRY_GPC_ID MW((28+7*32):(7*32+24)) +#define NVB069_FAULT_BUF_ENTRY_VALID MW((31+7*32):(7*32+31)) +#define NVB069_FAULT_BUF_ENTRY_VALID_FALSE 0x00000000 +#define NVB069_FAULT_BUF_ENTRY_VALID_TRUE 0x00000001 +#define NVB069_NOTIFIERS_REPLAYABLE_FAULT (0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clb069_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clb069sw.h b/userspace/sdks/nv525/nvidia/inc/class/clb069sw.h new file mode 100644 index 0000000..840ac79 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clb069sw.h @@ -0,0 +1,38 @@ +/******************************************************************************* + Copyright (c) 2008-2022 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clb069sw.finn +// + +#define NVB069_ALLOCATION_PARAMETERS_MESSAGE_ID (0xb069U) + +typedef struct NVB069_ALLOCATION_PARAMETERS { + NvU32 flags; // set to 0 +} NVB069_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clb06f.h b/userspace/sdks/nv525/nvidia/inc/class/clb06f.h new file mode 100644 index 0000000..b2b51e0 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clb06f.h @@ -0,0 +1,260 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clb06f_h_ +#define _clb06f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class MAXWELL_CHANNEL_GPFIFO */ +/* + * Documentation for MAXWELL_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + */ +#define MAXWELL_CHANNEL_GPFIFO_A (0x0000B06F) + +#define NVB06F_TYPEDEF MAXWELL_CHANNELChannelGPFifoA + +/* dma flow control data structure */ +typedef volatile struct _clb06f_tag0 { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} Nvb06FControl, MaxwellAControlGPFifo; + +/* fields and values */ +#define NVB06F_NUMBER_OF_SUBCHANNELS (8) +#define NVB06F_SET_OBJECT (0x00000000) +#define NVB06F_SET_OBJECT_NVCLASS 15:0 +#define NVB06F_SET_OBJECT_ENGINE 20:16 +#define NVB06F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVB06F_ILLEGAL (0x00000004) +#define NVB06F_ILLEGAL_HANDLE 31:0 +#define NVB06F_NOP (0x00000008) +#define NVB06F_NOP_HANDLE 31:0 +#define NVB06F_SEMAPHOREA (0x00000010) +#define NVB06F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVB06F_SEMAPHOREB (0x00000014) +#define NVB06F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVB06F_SEMAPHOREC (0x00000018) +#define NVB06F_SEMAPHOREC_PAYLOAD 31:0 +#define NVB06F_SEMAPHORED (0x0000001C) +#define NVB06F_SEMAPHORED_OPERATION 4:0 +#define NVB06F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVB06F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVB06F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVB06F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVB06F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 +#define NVB06F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVB06F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVB06F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVB06F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVB06F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVB06F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVB06F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVB06F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVB06F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVB06F_SEMAPHORED_REDUCTION 30:27 +#define NVB06F_SEMAPHORED_REDUCTION_MIN 0x00000000 +#define NVB06F_SEMAPHORED_REDUCTION_MAX 0x00000001 +#define NVB06F_SEMAPHORED_REDUCTION_XOR 0x00000002 +#define NVB06F_SEMAPHORED_REDUCTION_AND 0x00000003 +#define NVB06F_SEMAPHORED_REDUCTION_OR 0x00000004 +#define NVB06F_SEMAPHORED_REDUCTION_ADD 0x00000005 +#define NVB06F_SEMAPHORED_REDUCTION_INC 0x00000006 +#define NVB06F_SEMAPHORED_REDUCTION_DEC 0x00000007 +#define NVB06F_SEMAPHORED_FORMAT 31:31 +#define NVB06F_SEMAPHORED_FORMAT_SIGNED 0x00000000 +#define NVB06F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 +#define NVB06F_NON_STALL_INTERRUPT (0x00000020) +#define NVB06F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVB06F_FB_FLUSH (0x00000024) +#define NVB06F_FB_FLUSH_HANDLE 31:0 +// NOTE - MEM_OP_A and MEM_OP_B have been removed for gm20x to make room for +// possible future MEM_OP features. MEM_OP_C/D have identical functionality +// to the previous MEM_OP_A/B methods. +#define NVB06F_MEM_OP_C (0x00000030) +#define NVB06F_MEM_OP_C_OPERAND_LOW 31:2 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_TARGET 11:10 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_ADDR_LO 31:12 +#define NVB06F_MEM_OP_D (0x00000034) +#define NVB06F_MEM_OP_D_OPERAND_HIGH 7:0 +#define NVB06F_MEM_OP_D_OPERATION 31:27 +#define NVB06F_MEM_OP_D_OPERATION_MEMBAR 0x00000005 +#define NVB06F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVB06F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NVB06F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +#define NVB06F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVB06F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVB06F_MEM_OP_D_TLB_INVALIDATE_ADDR_HI 7:0 +#define NVB06F_SET_REFERENCE (0x00000050) +#define NVB06F_SET_REFERENCE_COUNT 31:0 +#define NVB06F_WFI (0x00000078) +#define NVB06F_WFI_SCOPE 0:0 +#define NVB06F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000 +#define NVB06F_WFI_SCOPE_ALL 0x00000001 +#define NVB06F_CRC_CHECK (0x0000007c) +#define NVB06F_CRC_CHECK_VALUE 31:0 +#define NVB06F_YIELD (0x00000080) +#define NVB06F_YIELD_OP 1:0 +#define NVB06F_YIELD_OP_NOP 0x00000000 +#define NVB06F_YIELD_OP_PBDMA_TIMESLICE 0x00000001 +#define NVB06F_YIELD_OP_RUNLIST_TIMESLICE 0x00000002 +#define NVB06F_YIELD_OP_TSG 0x00000003 + + +/* GPFIFO entry format */ +#define NVB06F_GP_ENTRY__SIZE 8 +#define NVB06F_GP_ENTRY0_FETCH 0:0 +#define NVB06F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVB06F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVB06F_GP_ENTRY0_GET 31:2 +#define NVB06F_GP_ENTRY0_OPERAND 31:0 +#define NVB06F_GP_ENTRY1_GET_HI 7:0 +#define NVB06F_GP_ENTRY1_PRIV 8:8 +#define NVB06F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NVB06F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NVB06F_GP_ENTRY1_LEVEL 9:9 +#define NVB06F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVB06F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVB06F_GP_ENTRY1_LENGTH 30:10 +#define NVB06F_GP_ENTRY1_SYNC 31:31 +#define NVB06F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVB06F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVB06F_GP_ENTRY1_OPCODE 7:0 +#define NVB06F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVB06F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVB06F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVB06F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVB06F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVB06F_DMA_METHOD_ADDRESS 11:0 +#define NVB06F_DMA_SUBDEVICE_MASK 15:4 +#define NVB06F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVB06F_DMA_TERT_OP 17:16 +#define NVB06F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVB06F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVB06F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVB06F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVB06F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVB06F_DMA_METHOD_COUNT_OLD 28:18 +#define NVB06F_DMA_METHOD_COUNT 28:16 +#define NVB06F_DMA_IMMD_DATA 28:16 +#define NVB06F_DMA_SEC_OP 31:29 +#define NVB06F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVB06F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVB06F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVB06F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVB06F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVB06F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVB06F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVB06F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVB06F_DMA_INCR_ADDRESS 11:0 +#define NVB06F_DMA_INCR_SUBCHANNEL 15:13 +#define NVB06F_DMA_INCR_COUNT 28:16 +#define NVB06F_DMA_INCR_OPCODE 31:29 +#define NVB06F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVB06F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVB06F_DMA_NONINCR_ADDRESS 11:0 +#define NVB06F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVB06F_DMA_NONINCR_COUNT 28:16 +#define NVB06F_DMA_NONINCR_OPCODE 31:29 +#define NVB06F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVB06F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVB06F_DMA_ONEINCR_ADDRESS 11:0 +#define NVB06F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVB06F_DMA_ONEINCR_COUNT 28:16 +#define NVB06F_DMA_ONEINCR_OPCODE 31:29 +#define NVB06F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVB06F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVB06F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVB06F_DMA_IMMD_ADDRESS 11:0 +#define NVB06F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVB06F_DMA_IMMD_DATA 28:16 +#define NVB06F_DMA_IMMD_OPCODE 31:29 +#define NVB06F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVB06F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVB06F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVB06F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVB06F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVB06F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVB06F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVB06F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVB06F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVB06F_DMA_ENDSEG_OPCODE 31:29 +#define NVB06F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVB06F_DMA_ADDRESS 12:2 +#define NVB06F_DMA_SUBCH 15:13 +#define NVB06F_DMA_OPCODE3 17:16 +#define NVB06F_DMA_OPCODE3_NONE (0x00000000) +#define NVB06F_DMA_COUNT 28:18 +#define NVB06F_DMA_OPCODE 31:29 +#define NVB06F_DMA_OPCODE_METHOD (0x00000000) +#define NVB06F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVB06F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clb06f_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clb06fsw.h b/userspace/sdks/nv525/nvidia/inc/class/clb06fsw.h new file mode 100644 index 0000000..3e1c74b --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clb06fsw.h @@ -0,0 +1,42 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clb06f_sw_h_ +#define _clb06f_sw_h_ + +#define NVB06F_NOTIFIERS_RC (0) +#define NVB06F_NOTIFIERS_REFCNT (1) +#define NVB06F_NOTIFIERS_NONSTALL (2) +#define NVB06F_NOTIFIERS_EVENTBUFFER (3) +#define NVB06F_NOTIFIERS_IDLECHANNEL (4) +#define NVB06F_NOTIFIERS_ENDCTX (5) +#define NVB06F_NOTIFIERS_SW (6) +#define NVB06F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVB06F_NOTIFIERS_REPLAYABLE_FAULT (8) +#define NVB06F_NOTIFIERS_MAXCOUNT (9) + +/* NvNotification[] fields and values */ +#define NVB06F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVB06F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _clb06f_sw_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clb097.h b/userspace/sdks/nv525/nvidia/inc/class/clb097.h new file mode 100644 index 0000000..52ee310 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clb097.h @@ -0,0 +1,3966 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_maxwell_a_h_ +#define _cl_maxwell_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl maxwell_a */ + +#include "nvtypes.h" + +#define MAXWELL_A 0xB097 + +#define NVB097_SET_OBJECT 0x0000 +#define NVB097_SET_OBJECT_CLASS_ID 15:0 +#define NVB097_SET_OBJECT_ENGINE_ID 20:16 + +#define NVB097_NO_OPERATION 0x0100 +#define NVB097_NO_OPERATION_V 31:0 + +#define NVB097_SET_NOTIFY_A 0x0104 +#define NVB097_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVB097_SET_NOTIFY_B 0x0108 +#define NVB097_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVB097_NOTIFY 0x010c +#define NVB097_NOTIFY_TYPE 31:0 +#define NVB097_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVB097_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVB097_WAIT_FOR_IDLE 0x0110 +#define NVB097_WAIT_FOR_IDLE_V 31:0 + +#define NVB097_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVB097_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVB097_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVB097_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVB097_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVB097_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVB097_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVB097_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVB097_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVB097_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVB097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVB097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVB097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVB097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVB097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVB097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVB097_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVB097_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVB097_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB097_SEND_GO_IDLE 0x013c +#define NVB097_SEND_GO_IDLE_V 31:0 + +#define NVB097_PM_TRIGGER 0x0140 +#define NVB097_PM_TRIGGER_V 31:0 + +#define NVB097_PM_TRIGGER_WFI 0x0144 +#define NVB097_PM_TRIGGER_WFI_V 31:0 + +#define NVB097_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVB097_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVB097_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVB097_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVB097_LINE_LENGTH_IN 0x0180 +#define NVB097_LINE_LENGTH_IN_VALUE 31:0 + +#define NVB097_LINE_COUNT 0x0184 +#define NVB097_LINE_COUNT_VALUE 31:0 + +#define NVB097_OFFSET_OUT_UPPER 0x0188 +#define NVB097_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVB097_OFFSET_OUT 0x018c +#define NVB097_OFFSET_OUT_VALUE 31:0 + +#define NVB097_PITCH_OUT 0x0190 +#define NVB097_PITCH_OUT_VALUE 31:0 + +#define NVB097_SET_DST_BLOCK_SIZE 0x0194 +#define NVB097_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVB097_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVB097_SET_DST_WIDTH 0x0198 +#define NVB097_SET_DST_WIDTH_V 31:0 + +#define NVB097_SET_DST_HEIGHT 0x019c +#define NVB097_SET_DST_HEIGHT_V 31:0 + +#define NVB097_SET_DST_DEPTH 0x01a0 +#define NVB097_SET_DST_DEPTH_V 31:0 + +#define NVB097_SET_DST_LAYER 0x01a4 +#define NVB097_SET_DST_LAYER_V 31:0 + +#define NVB097_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVB097_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVB097_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVB097_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVB097_LAUNCH_DMA 0x01b0 +#define NVB097_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVB097_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB097_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB097_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVB097_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVB097_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVB097_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVB097_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVB097_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVB097_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVB097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVB097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVB097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVB097_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVB097_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB097_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB097_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB097_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVB097_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB097_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB097_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVB097_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVB097_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVB097_LOAD_INLINE_DATA 0x01b4 +#define NVB097_LOAD_INLINE_DATA_V 31:0 + +#define NVB097_SET_I2M_SEMAPHORE_A 0x01dc +#define NVB097_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVB097_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVB097_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB097_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVB097_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVB097_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVB097_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVB097_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVB097_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVB097_SET_I2M_SPARE_NOOP03 0x01fc +#define NVB097_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVB097_RUN_DS_NOW 0x0200 +#define NVB097_RUN_DS_NOW_V 31:0 + +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVB097_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVB097_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVB097_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVB097_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVB097_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVB097_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_GS_DM_FIFO 0x0214 +#define NVB097_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVB097_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVB097_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVB097_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVB097_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB097_INVALIDATE_SHADER_CACHES 0x021c +#define NVB097_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVB097_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVB097_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVB097_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVB097_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVB097_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVB097_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVB097_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVB097_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVB097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVB097_INCREMENT_SYNC_POINT 0x02c8 +#define NVB097_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVB097_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVB097_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVB097_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVB097_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVB097_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVB097_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVB097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NVB097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NVB097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVB097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVB097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVB097_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVB097_DECOMPRESS_SURFACE 0x02e0 +#define NVB097_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVB097_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVB097_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVB097_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVB097_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVB097_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVB097_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVB097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVB097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVB097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVB097_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVB097_SET_ZCULL_SUBREGION 0x02e8 +#define NVB097_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVB097_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVB097_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVB097_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVB097_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVB097_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVB097_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVB097_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVB097_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVB097_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVB097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVB097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVB097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVB097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVB097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVB097_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVB097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVB097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVB097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVB097_DRAW_ZERO_INDEX 0x0304 +#define NVB097_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVB097_SET_L1_CONFIGURATION 0x0308 +#define NVB097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVB097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVB097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVB097_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVB097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVB097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVB097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVB097_SET_SPA_VERSION 0x0310 +#define NVB097_SET_SPA_VERSION_MINOR 7:0 +#define NVB097_SET_SPA_VERSION_MAJOR 15:8 + +#define NVB097_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NVB097_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NVB097_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_SNAP_GRID_LINE 0x0318 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVB097_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVB097_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVB097_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVB097_SET_SNAP_GRID_NON_LINE 0x031c +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVB097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVB097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVB097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVB097_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVB097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVB097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVB097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVB097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVB097_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVB097_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVB097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVB097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVB097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVB097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVB097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVB097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVB097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVB097_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVB097_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVB097_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVB097_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVB097_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVB097_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVB097_SET_TESSELLATION_LOD_V1 0x0330 +#define NVB097_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVB097_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVB097_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVB097_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVB097_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVB097_RESERVED_TG07 0x033c +#define NVB097_RESERVED_TG07_V 0:0 + +#define NVB097_RESERVED_TG08 0x0340 +#define NVB097_RESERVED_TG08_V 0:0 + +#define NVB097_RESERVED_TG09 0x0344 +#define NVB097_RESERVED_TG09_V 0:0 + +#define NVB097_RESERVED_TG10 0x0348 +#define NVB097_RESERVED_TG10_V 0:0 + +#define NVB097_RESERVED_TG11 0x034c +#define NVB097_RESERVED_TG11_V 0:0 + +#define NVB097_RESERVED_TG12 0x0350 +#define NVB097_RESERVED_TG12_V 0:0 + +#define NVB097_RESERVED_TG13 0x0354 +#define NVB097_RESERVED_TG13_V 0:0 + +#define NVB097_RESERVED_TG14 0x0358 +#define NVB097_RESERVED_TG14_V 0:0 + +#define NVB097_RESERVED_TG15 0x035c +#define NVB097_RESERVED_TG15_V 0:0 + +#define NVB097_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVB097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVB097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVB097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVB097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVB097_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVB097_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVB097_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVB097_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVB097_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVB097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVB097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVB097_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVB097_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVB097_SET_RASTER_ENABLE 0x037c +#define NVB097_SET_RASTER_ENABLE_V 0:0 +#define NVB097_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVB097_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVB097_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVB097_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVB097_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVB097_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVB097_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVB097_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVB097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVB097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVB097_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVB097_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVB097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVB097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVB097_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVB097_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVB097_SET_RASTER_INPUT 0x0740 +#define NVB097_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVB097_SET_STREAM_OUTPUT 0x0744 +#define NVB097_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVB097_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVB097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVB097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_ALPHA_FRACTION 0x074c +#define NVB097_SET_ALPHA_FRACTION_V 7:0 + +#define NVB097_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVB097_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVB097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVB097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVB097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 + +#define NVB097_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVB097_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB097_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVB097_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVB097_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVB097_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVB097_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVB097_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVB097_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVB097_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVB097_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVB097_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVB097_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVB097_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVB097_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVB097_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVB097_SET_ISBE_SAVE_RESTORE_PROGRAM 0x07ac +#define NVB097_SET_ISBE_SAVE_RESTORE_PROGRAM_OFFSET 31:0 + +#define NVB097_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVB097_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVB097_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVB097_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVB097_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVB097_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVB097_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVB097_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVB097_SET_CULL_BEFORE_FETCH 0x07dc +#define NVB097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVB097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVB097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVB097_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVB097_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVB097_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVB097_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVB097_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVB097_SET_ZCULL_STORAGE_A 0x07e8 +#define NVB097_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVB097_SET_ZCULL_STORAGE_B 0x07ec +#define NVB097_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVB097_SET_ZCULL_STORAGE_C 0x07f0 +#define NVB097_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVB097_SET_ZCULL_STORAGE_D 0x07f4 +#define NVB097_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVB097_SET_ZT_READ_ONLY 0x07f8 +#define NVB097_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVB097_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVB097_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVB097_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVB097_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVB097_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVB097_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVB097_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVB097_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVB097_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVB097_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVB097_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVB097_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVB097_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVB097_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVB097_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVB097_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVB097_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVB097_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVB097_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVB097_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVB097_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVB097_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVB097_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVB097_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB097_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVB097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVB097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVB097_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVB097_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVB097_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVB097_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVB097_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVB097_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVB097_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NVB097_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NVB097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVB097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVB097_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVB097_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVB097_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVB097_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVB097_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVB097_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVB097_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVB097_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVB097_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVB097_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVB097_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVB097_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVB097_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVB097_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVB097_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVB097_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVB097_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVB097_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVB097_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVB097_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVB097_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVB097_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVB097_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVB097_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVB097_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVB097_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVB097_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVB097_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVB097_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVB097_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVB097_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVB097_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVB097_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVB097_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVB097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVB097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVB097_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVB097_SET_STATISTICS_COUNTER 0x0d68 +#define NVB097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVB097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVB097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVB097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVB097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVB097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVB097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVB097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVB097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVB097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVB097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVB097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVB097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVB097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVB097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVB097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVB097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVB097_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVB097_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVB097_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVB097_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVB097_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVB097_SET_VERTEX_ARRAY_START 0x0d74 +#define NVB097_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVB097_DRAW_VERTEX_ARRAY 0x0d78 +#define NVB097_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVB097_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVB097_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVB097_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVB097_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVB097_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVB097_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVB097_SET_Z_CLEAR_VALUE 0x0d90 +#define NVB097_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVB097_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVB097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVB097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVB097_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVB097_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVB097_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVB097_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVB097_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVB097_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVB097_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVB097_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVB097_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVB097_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVB097_SET_FRONT_POLYGON_MODE 0x0dac +#define NVB097_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVB097_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVB097_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVB097_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVB097_SET_BACK_POLYGON_MODE 0x0db0 +#define NVB097_SET_BACK_POLYGON_MODE_V 31:0 +#define NVB097_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVB097_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVB097_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVB097_SET_POLY_SMOOTH 0x0db4 +#define NVB097_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVB097_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVB097_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_ZT_MARK 0x0db8 +#define NVB097_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NVB097_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVB097_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVB097_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVB097_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVB097_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVB097_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVB097_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVB097_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVB097_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVB097_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVB097_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVB097_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_PATCH 0x0dcc +#define NVB097_SET_PATCH_SIZE 7:0 + +#define NVB097_SET_ITERATED_BLEND 0x0dd0 +#define NVB097_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVB097_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVB097_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVB097_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVB097_SET_ZCULL_CRITERION 0x0dd8 +#define NVB097_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVB097_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVB097_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVB097_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVB097_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVB097_SET_ZCULL_CRITERION_SREF 23:16 +#define NVB097_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVB097_PIXEL_SHADER_BARRIER 0x0de0 +#define NVB097_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVB097_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVB097_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVB097_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVB097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVB097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVB097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVB097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVB097_SET_WINDOW_OFFSET_X 0x0df8 +#define NVB097_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVB097_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVB097_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVB097_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVB097_SET_SCISSOR_ENABLE_V 0:0 +#define NVB097_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVB097_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVB097_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVB097_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVB097_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVB097_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVB097_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0f10 +#define NVB097_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVB097_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVB097_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVB097_SET_VPC_PERF_KNOB 0x0f14 +#define NVB097_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVB097_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVB097_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVB097_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVB097_PM_LOCAL_TRIGGER 0x0f18 +#define NVB097_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVB097_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVB097_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVB097_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVB097_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVB097_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVB097_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVB097_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVB097_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVB097_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVB097_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVB097_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVB097_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVB097_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVB097_SET_BACK_STENCIL_MASK 0x0f58 +#define NVB097_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVB097_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVB097_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVB097_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVB097_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVB097_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVB097_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVB097_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVB097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVB097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVB097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVB097_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVB097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVB097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVB097_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVB097_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVB097_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVB097_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVB097_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVB097_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVB097_SET_CT_MRT_ENABLE 0x0fac +#define NVB097_SET_CT_MRT_ENABLE_V 0:0 +#define NVB097_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVB097_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVB097_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVB097_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVB097_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVB097_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVB097_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVB097_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVB097_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVB097_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVB097_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVB097_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVB097_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVB097_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVB097_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVB097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVB097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVB097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVB097_SET_ZT_A 0x0fe0 +#define NVB097_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_ZT_B 0x0fe4 +#define NVB097_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_ZT_FORMAT 0x0fe8 +#define NVB097_SET_ZT_FORMAT_V 4:0 +#define NVB097_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVB097_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVB097_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVB097_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVB097_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVB097_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVB097_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVB097_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVB097_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVB097_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVB097_SET_ZT_BLOCK_SIZE 0x0fec +#define NVB097_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVB097_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVB097_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVB097_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVB097_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVB097_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVB097_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVB097_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVB097_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVB097_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVB097_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVB097_SET_TILED_CACHE_BUNDLE_CONTROL 0x0ffc +#define NVB097_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT 0:0 +#define NVB097_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_FALSE 0x00000000 +#define NVB097_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_TRUE 0x00000001 + +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB097_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVB097_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVB097_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVB097_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVB097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVB097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVB097_SET_RESERVED_SW_METHOD00 0x1014 +#define NVB097_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVB097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVB097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVB097_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVB097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVB097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVB097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVB097_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVB097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVB097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_RESERVED_SW_METHOD01 0x1028 +#define NVB097_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD02 0x102c +#define NVB097_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVB097_SET_SPARE_NOOP01 0x1044 +#define NVB097_SET_SPARE_NOOP01_V 31:0 + +#define NVB097_SET_SPARE_NOOP02 0x1048 +#define NVB097_SET_SPARE_NOOP02_V 31:0 + +#define NVB097_SET_SPARE_NOOP03 0x104c +#define NVB097_SET_SPARE_NOOP03_V 31:0 + +#define NVB097_SET_SPARE_NOOP04 0x1050 +#define NVB097_SET_SPARE_NOOP04_V 31:0 + +#define NVB097_SET_SPARE_NOOP05 0x1054 +#define NVB097_SET_SPARE_NOOP05_V 31:0 + +#define NVB097_SET_SPARE_NOOP06 0x1058 +#define NVB097_SET_SPARE_NOOP06_V 31:0 + +#define NVB097_SET_SPARE_NOOP07 0x105c +#define NVB097_SET_SPARE_NOOP07_V 31:0 + +#define NVB097_SET_SPARE_NOOP08 0x1060 +#define NVB097_SET_SPARE_NOOP08_V 31:0 + +#define NVB097_SET_SPARE_NOOP09 0x1064 +#define NVB097_SET_SPARE_NOOP09_V 31:0 + +#define NVB097_SET_SPARE_NOOP10 0x1068 +#define NVB097_SET_SPARE_NOOP10_V 31:0 + +#define NVB097_SET_SPARE_NOOP11 0x106c +#define NVB097_SET_SPARE_NOOP11_V 31:0 + +#define NVB097_SET_SPARE_NOOP12 0x1070 +#define NVB097_SET_SPARE_NOOP12_V 31:0 + +#define NVB097_SET_SPARE_NOOP13 0x1074 +#define NVB097_SET_SPARE_NOOP13_V 31:0 + +#define NVB097_SET_SPARE_NOOP14 0x1078 +#define NVB097_SET_SPARE_NOOP14_V 31:0 + +#define NVB097_SET_SPARE_NOOP15 0x107c +#define NVB097_SET_SPARE_NOOP15_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVB097_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVB097_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVB097_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD06 0x10bc +#define NVB097_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVB097_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVB097_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVB097_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVB097_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVB097_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVB097_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVB097_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD13 0x10dc +#define NVB097_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVB097_UNBIND_ALL 0x10f4 +#define NVB097_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVB097_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVB097_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVB097_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB097_SET_RESERVED_SW_METHOD14 0x1100 +#define NVB097_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD15 0x1104 +#define NVB097_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVB097_NO_OPERATION_DATA_HI 0x110c +#define NVB097_NO_OPERATION_DATA_HI_V 31:0 + +#define NVB097_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVB097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVB097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVB097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVB097_PM_TRIGGER_END 0x1114 +#define NVB097_PM_TRIGGER_END_V 31:0 + +#define NVB097_SET_VERTEX_ID_BASE 0x1118 +#define NVB097_SET_VERTEX_ID_BASE_V 31:0 + +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVB097_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVB097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVB097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVB097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVB097_FLUSH_PENDING_WRITES 0x1144 +#define NVB097_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVB097_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVB097_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVB097_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVB097_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_SET_CT_SELECT 0x121c +#define NVB097_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVB097_SET_CT_SELECT_TARGET0 6:4 +#define NVB097_SET_CT_SELECT_TARGET1 9:7 +#define NVB097_SET_CT_SELECT_TARGET2 12:10 +#define NVB097_SET_CT_SELECT_TARGET3 15:13 +#define NVB097_SET_CT_SELECT_TARGET4 18:16 +#define NVB097_SET_CT_SELECT_TARGET5 21:19 +#define NVB097_SET_CT_SELECT_TARGET6 24:22 +#define NVB097_SET_CT_SELECT_TARGET7 27:25 + +#define NVB097_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVB097_SET_ZT_SIZE_A 0x1228 +#define NVB097_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVB097_SET_ZT_SIZE_B 0x122c +#define NVB097_SET_ZT_SIZE_B_HEIGHT 16:0 + +#define NVB097_SET_ZT_SIZE_C 0x1230 +#define NVB097_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVB097_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVB097_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVB097_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVB097_SET_SAMPLER_BINDING 0x1234 +#define NVB097_SET_SAMPLER_BINDING_V 0:0 +#define NVB097_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVB097_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVB097_DRAW_AUTO 0x123c +#define NVB097_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVB097_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVB097_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVB097_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVB097_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVB097_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVB097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVB097_CLEAR_ZCULL_REGION 0x12c8 +#define NVB097_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVB097_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVB097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVB097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVB097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVB097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVB097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVB097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVB097_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVB097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVB097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVB097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVB097_SET_DEPTH_TEST 0x12cc +#define NVB097_SET_DEPTH_TEST_ENABLE 0:0 +#define NVB097_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVB097_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_FILL_MODE 0x12d0 +#define NVB097_SET_FILL_MODE_V 31:0 +#define NVB097_SET_FILL_MODE_V_POINT 0x00000001 +#define NVB097_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVB097_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVB097_SET_SHADE_MODE 0x12d4 +#define NVB097_SET_SHADE_MODE_V 31:0 +#define NVB097_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVB097_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVB097_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVB097_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVB097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVB097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVB097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVB097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVB097_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVB097_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVB097_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVB097_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_DEPTH_WRITE 0x12e8 +#define NVB097_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVB097_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_ALPHA_TEST 0x12ec +#define NVB097_SET_ALPHA_TEST_ENABLE 0:0 +#define NVB097_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVB097_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVB097_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVB097_DRAW_INLINE_INDEX4X8 0x1304 +#define NVB097_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVB097_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVB097_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVB097_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVB097_D3D_SET_CULL_MODE 0x1308 +#define NVB097_D3D_SET_CULL_MODE_V 31:0 +#define NVB097_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVB097_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVB097_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVB097_SET_DEPTH_FUNC 0x130c +#define NVB097_SET_DEPTH_FUNC_V 31:0 +#define NVB097_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVB097_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVB097_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB097_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB097_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVB097_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB097_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB097_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB097_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVB097_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVB097_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB097_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB097_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVB097_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB097_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB097_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB097_SET_ALPHA_REF 0x1310 +#define NVB097_SET_ALPHA_REF_V 31:0 + +#define NVB097_SET_ALPHA_FUNC 0x1314 +#define NVB097_SET_ALPHA_FUNC_V 31:0 +#define NVB097_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVB097_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVB097_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB097_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB097_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVB097_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB097_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB097_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB097_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVB097_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVB097_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB097_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB097_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVB097_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB097_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB097_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB097_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVB097_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVB097_SET_BLEND_CONST_RED 0x131c +#define NVB097_SET_BLEND_CONST_RED_V 31:0 + +#define NVB097_SET_BLEND_CONST_GREEN 0x1320 +#define NVB097_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVB097_SET_BLEND_CONST_BLUE 0x1324 +#define NVB097_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVB097_SET_BLEND_CONST_ALPHA 0x1328 +#define NVB097_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVB097_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVB097_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVB097_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVB097_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVB097_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVB097_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVB097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVB097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVB097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BLEND_COLOR_OP 0x1340 +#define NVB097_SET_BLEND_COLOR_OP_V 31:0 +#define NVB097_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB097_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB097_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB097_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVB097_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVB097_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVB097_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB097_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB097_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVB097_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_BLEND_ALPHA_OP 0x134c +#define NVB097_SET_BLEND_ALPHA_OP_V 31:0 +#define NVB097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB097_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVB097_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVB097_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVB097_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB097_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB097_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVB097_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVB097_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVB097_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVB097_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_SINGLE_ROP_CONTROL 0x135c +#define NVB097_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVB097_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BLEND(i) (0x1360+(i)*4) +#define NVB097_SET_BLEND_ENABLE 0:0 +#define NVB097_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVB097_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_STENCIL_TEST 0x1380 +#define NVB097_SET_STENCIL_TEST_ENABLE 0:0 +#define NVB097_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_STENCIL_OP_FAIL 0x1384 +#define NVB097_SET_STENCIL_OP_FAIL_V 31:0 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVB097_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVB097_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVB097_SET_STENCIL_OP_ZPASS 0x138c +#define NVB097_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVB097_SET_STENCIL_FUNC 0x1390 +#define NVB097_SET_STENCIL_FUNC_V 31:0 +#define NVB097_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVB097_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVB097_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB097_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB097_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVB097_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB097_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB097_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB097_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVB097_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVB097_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB097_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB097_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVB097_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB097_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB097_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB097_SET_STENCIL_FUNC_REF 0x1394 +#define NVB097_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVB097_SET_STENCIL_FUNC_MASK 0x1398 +#define NVB097_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVB097_SET_STENCIL_MASK 0x139c +#define NVB097_SET_STENCIL_MASK_V 7:0 + +#define NVB097_SET_DRAW_AUTO_START 0x13a4 +#define NVB097_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVB097_SET_PS_SATURATE 0x13a8 +#define NVB097_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVB097_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVB097_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVB097_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVB097_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVB097_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVB097_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVB097_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVB097_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVB097_SET_WINDOW_ORIGIN 0x13ac +#define NVB097_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVB097_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVB097_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVB097_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVB097_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVB097_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVB097_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVB097_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVB097_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVB097_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVB097_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVB097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVB097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_ALPHA_HYSTERESIS 0x1420 +#define NVB097_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NVB097_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVB097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVB097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB097_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVB097_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVB097_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVB097_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVB097_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVB097_SET_PS_WARP_WATERMARKS 0x1450 +#define NVB097_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVB097_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVB097_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVB097_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVB097_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVB097_STORE_ZCULL 0x1464 +#define NVB097_STORE_ZCULL_V 0:0 + +#define NVB097_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVB097_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVB097_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVB097_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVB097_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVB097_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVB097_LOAD_ZCULL 0x1500 +#define NVB097_LOAD_ZCULL_V 0:0 + +#define NVB097_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVB097_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVB097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVB097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVB097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVB097_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVB097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVB097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVB097_SET_USER_CLIP_ENABLE 0x1510 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVB097_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVB097_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVB097_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_POINT_SIZE 0x1518 +#define NVB097_SET_POINT_SIZE_V 31:0 + +#define NVB097_SET_ZCULL_STATS 0x151c +#define NVB097_SET_ZCULL_STATS_ENABLE 0:0 +#define NVB097_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_POINT_SPRITE 0x1520 +#define NVB097_SET_POINT_SPRITE_ENABLE 0:0 +#define NVB097_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_SHADER_EXCEPTIONS 0x1528 +#define NVB097_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVB097_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVB097_CLEAR_REPORT_VALUE 0x1530 +#define NVB097_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVB097_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVB097_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVB097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVB097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVB097_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVB097_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 + +#define NVB097_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVB097_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVB097_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_ZT_SELECT 0x1538 +#define NVB097_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVB097_SET_RENDER_ENABLE_A 0x1550 +#define NVB097_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_RENDER_ENABLE_B 0x1554 +#define NVB097_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_RENDER_ENABLE_C 0x1558 +#define NVB097_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVB097_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB097_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB097_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB097_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVB097_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVB097_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVB097_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVB097_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVB097_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVB097_SET_ANTI_ALIASED_LINE 0x1570 +#define NVB097_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVB097_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_TEX_HEADER_POOL_A 0x1574 +#define NVB097_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_TEX_HEADER_POOL_B 0x1578 +#define NVB097_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_TEX_HEADER_POOL_C 0x157c +#define NVB097_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVB097_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVB097_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVB097_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVB097_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVB097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVB097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVB097_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVB097_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVB097_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB097_SET_SRGB_WRITE 0x15b8 +#define NVB097_SET_SRGB_WRITE_ENABLE 0:0 +#define NVB097_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_DEPTH_BIAS 0x15bc +#define NVB097_SET_DEPTH_BIAS_V 31:0 + +#define NVB097_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVB097_SET_RT_LAYER 0x15cc +#define NVB097_SET_RT_LAYER_V 15:0 +#define NVB097_SET_RT_LAYER_CONTROL 16:16 +#define NVB097_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVB097_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVB097_SET_ANTI_ALIAS 0x15d0 +#define NVB097_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVB097_SET_EDGE_FLAG 0x15e4 +#define NVB097_SET_EDGE_FLAG_V 0:0 +#define NVB097_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVB097_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVB097_DRAW_INLINE_INDEX 0x15e8 +#define NVB097_DRAW_INLINE_INDEX_V 31:0 + +#define NVB097_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVB097_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVB097_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVB097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVB097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVB097_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVB097_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVB097_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVB097_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVB097_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVB097_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVB097_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVB097_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVB097_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVB097_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVB097_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVB097_SET_POINT_SPRITE_SELECT 0x1604 +#define NVB097_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVB097_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVB097_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVB097_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVB097_SET_PROGRAM_REGION_A 0x1608 +#define NVB097_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVB097_SET_PROGRAM_REGION_B 0x160c +#define NVB097_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVB097_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVB097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVB097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVB097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVB097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVB097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVB097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVB097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVB097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVB097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVB097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVB097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVB097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVB097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVB097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVB097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVB097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVB097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVB097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVB097_END 0x1614 +#define NVB097_END_V 0:0 + +#define NVB097_BEGIN 0x1618 +#define NVB097_BEGIN_OP 15:0 +#define NVB097_BEGIN_OP_POINTS 0x00000000 +#define NVB097_BEGIN_OP_LINES 0x00000001 +#define NVB097_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVB097_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVB097_BEGIN_OP_TRIANGLES 0x00000004 +#define NVB097_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVB097_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVB097_BEGIN_OP_QUADS 0x00000007 +#define NVB097_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVB097_BEGIN_OP_POLYGON 0x00000009 +#define NVB097_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVB097_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVB097_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_BEGIN_OP_PATCH 0x0000000E +#define NVB097_BEGIN_PRIMITIVE_ID 24:24 +#define NVB097_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVB097_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVB097_BEGIN_INSTANCE_ID 27:26 +#define NVB097_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVB097_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVB097_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVB097_BEGIN_SPLIT_MODE 30:29 +#define NVB097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVB097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVB097_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVB097_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 + +#define NVB097_SET_VERTEX_ID_COPY 0x161c +#define NVB097_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVB097_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVB097_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVB097_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVB097_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVB097_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVB097_LOAD_PRIMITIVE_ID 0x1624 +#define NVB097_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVB097_SET_SHADER_BASED_CULL 0x162c +#define NVB097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVB097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVB097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVB097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_CLASS_VERSION 0x1638 +#define NVB097_SET_CLASS_VERSION_CURRENT 15:0 +#define NVB097_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB097_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVB097_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVB097_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVB097_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVB097_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVB097_SET_DA_OUTPUT 0x164c +#define NVB097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVB097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVB097_SET_ANTI_ALIASED_POINT 0x1658 +#define NVB097_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVB097_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_POINT_CENTER_MODE 0x165c +#define NVB097_SET_POINT_CENTER_MODE_V 31:0 +#define NVB097_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVB097_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVB097_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVB097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVB097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVB097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVB097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVB097_SET_LINE_STIPPLE 0x166c +#define NVB097_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVB097_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVB097_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVB097_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVB097_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVB097_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVB097_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVB097_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVB097_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVB097_SET_PROVOKING_VERTEX 0x1684 +#define NVB097_SET_PROVOKING_VERTEX_V 0:0 +#define NVB097_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVB097_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVB097_SET_TWO_SIDED_LIGHT 0x1688 +#define NVB097_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVB097_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_POLYGON_STIPPLE 0x168c +#define NVB097_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVB097_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_SHADER_CONTROL 0x1690 +#define NVB097_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVB097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVB097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVB097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVB097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVB097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVB097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVB097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVB097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVB097_CHECK_CLASS_VERSION 0x16a0 +#define NVB097_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVB097_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB097_SET_SPH_VERSION 0x16a4 +#define NVB097_SET_SPH_VERSION_CURRENT 15:0 +#define NVB097_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB097_CHECK_SPH_VERSION 0x16a8 +#define NVB097_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVB097_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVB097_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVB097_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVB097_SET_AAM_VERSION 0x1790 +#define NVB097_SET_AAM_VERSION_CURRENT 15:0 +#define NVB097_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB097_CHECK_AAM_VERSION 0x1794 +#define NVB097_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVB097_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB097_SET_ZT_LAYER 0x179c +#define NVB097_SET_ZT_LAYER_OFFSET 15:0 + +#define NVB097_SET_INDEX_BUFFER_A 0x17c8 +#define NVB097_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVB097_SET_INDEX_BUFFER_B 0x17cc +#define NVB097_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVB097_SET_INDEX_BUFFER_C 0x17d0 +#define NVB097_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVB097_SET_INDEX_BUFFER_D 0x17d4 +#define NVB097_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVB097_SET_INDEX_BUFFER_E 0x17d8 +#define NVB097_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVB097_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVB097_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVB097_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVB097_SET_INDEX_BUFFER_F 0x17dc +#define NVB097_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVB097_DRAW_INDEX_BUFFER 0x17e0 +#define NVB097_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVB097_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVB097_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVB097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVB097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVB097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVB097_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVB097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVB097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVB097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVB097_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVB097_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVB097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVB097_OGL_SET_CULL 0x1918 +#define NVB097_OGL_SET_CULL_ENABLE 0:0 +#define NVB097_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVB097_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVB097_OGL_SET_FRONT_FACE 0x191c +#define NVB097_OGL_SET_FRONT_FACE_V 31:0 +#define NVB097_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVB097_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVB097_OGL_SET_CULL_FACE 0x1920 +#define NVB097_OGL_SET_CULL_FACE_V 31:0 +#define NVB097_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVB097_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVB097_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVB097_SET_VIEWPORT_PIXEL 0x1924 +#define NVB097_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVB097_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVB097_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVB097_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVB097_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVB097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVB097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVB097_SET_USER_CLIP_OP 0x1940 +#define NVB097_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVB097_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVB097_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVB097_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVB097_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVB097_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVB097_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVB097_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVB097_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVB097_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVB097_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVB097_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVB097_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVB097_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVB097_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVB097_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVB097_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVB097_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVB097_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVB097_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVB097_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVB097_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVB097_INVALIDATE_ZCULL 0x1958 +#define NVB097_INVALIDATE_ZCULL_V 31:0 +#define NVB097_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVB097_SET_ZCULL 0x1968 +#define NVB097_SET_ZCULL_Z_ENABLE 0:0 +#define NVB097_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVB097_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_ZCULL_BOUNDS 0x196c +#define NVB097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVB097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVB097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVB097_ZCULL_SYNC 0x1978 +#define NVB097_ZCULL_SYNC_V 31:0 + +#define NVB097_SET_CLIP_ID_TEST 0x197c +#define NVB097_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVB097_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVB097_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVB097_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVB097_SET_CLIP_ID 0x1984 +#define NVB097_SET_CLIP_ID_V 31:0 + +#define NVB097_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVB097_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVB097_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVB097_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVB097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVB097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVB097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVB097_SET_LOGIC_OP 0x19c4 +#define NVB097_SET_LOGIC_OP_ENABLE 0:0 +#define NVB097_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVB097_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_LOGIC_OP_FUNC 0x19c8 +#define NVB097_SET_LOGIC_OP_FUNC_V 31:0 +#define NVB097_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVB097_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVB097_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVB097_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVB097_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVB097_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVB097_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVB097_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVB097_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVB097_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVB097_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVB097_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVB097_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVB097_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVB097_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVB097_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVB097_SET_Z_COMPRESSION 0x19cc +#define NVB097_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVB097_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVB097_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVB097_CLEAR_SURFACE 0x19d0 +#define NVB097_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVB097_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVB097_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVB097_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVB097_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVB097_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVB097_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVB097_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVB097_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVB097_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVB097_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVB097_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVB097_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVB097_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVB097_SET_CT_WRITE_R_ENABLE 0:0 +#define NVB097_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVB097_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVB097_SET_CT_WRITE_G_ENABLE 4:4 +#define NVB097_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVB097_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVB097_SET_CT_WRITE_B_ENABLE 8:8 +#define NVB097_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVB097_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVB097_SET_CT_WRITE_A_ENABLE 12:12 +#define NVB097_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVB097_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVB097_PIPE_NOP 0x1a2c +#define NVB097_PIPE_NOP_V 31:0 + +#define NVB097_SET_SPARE00 0x1a30 +#define NVB097_SET_SPARE00_V 31:0 + +#define NVB097_SET_SPARE01 0x1a34 +#define NVB097_SET_SPARE01_V 31:0 + +#define NVB097_SET_SPARE02 0x1a38 +#define NVB097_SET_SPARE02_V 31:0 + +#define NVB097_SET_SPARE03 0x1a3c +#define NVB097_SET_SPARE03_V 31:0 + +#define NVB097_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVB097_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVB097_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVB097_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB097_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVB097_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVB097_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVB097_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVB097_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVB097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVB097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVB097_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVB097_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVB097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVB097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVB097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVB097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVB097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVB097_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVB097_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVB097_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVB097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVB097_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVB097_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVB097_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVB097_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVB097_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVB097_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVB097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVB097_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVB097_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVB097_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVB097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVB097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVB097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVB097_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVB097_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVB097_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVB097_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVB097_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVB097_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVB097_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVB097_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVB097_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVB097_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVB097_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVB097_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVB097_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVB097_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVB097_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVB097_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVB097_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVB097_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVB097_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NVB097_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NVB097_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVB097_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVB097_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVB097_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NVB097_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVB097_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVB097_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NVB097_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVB097_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NVB097_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NVB097_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVB097_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVB097_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVB097_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVB097_SET_FALCON00 0x2300 +#define NVB097_SET_FALCON00_V 31:0 + +#define NVB097_SET_FALCON01 0x2304 +#define NVB097_SET_FALCON01_V 31:0 + +#define NVB097_SET_FALCON02 0x2308 +#define NVB097_SET_FALCON02_V 31:0 + +#define NVB097_SET_FALCON03 0x230c +#define NVB097_SET_FALCON03_V 31:0 + +#define NVB097_SET_FALCON04 0x2310 +#define NVB097_SET_FALCON04_V 31:0 + +#define NVB097_SET_FALCON05 0x2314 +#define NVB097_SET_FALCON05_V 31:0 + +#define NVB097_SET_FALCON06 0x2318 +#define NVB097_SET_FALCON06_V 31:0 + +#define NVB097_SET_FALCON07 0x231c +#define NVB097_SET_FALCON07_V 31:0 + +#define NVB097_SET_FALCON08 0x2320 +#define NVB097_SET_FALCON08_V 31:0 + +#define NVB097_SET_FALCON09 0x2324 +#define NVB097_SET_FALCON09_V 31:0 + +#define NVB097_SET_FALCON10 0x2328 +#define NVB097_SET_FALCON10_V 31:0 + +#define NVB097_SET_FALCON11 0x232c +#define NVB097_SET_FALCON11_V 31:0 + +#define NVB097_SET_FALCON12 0x2330 +#define NVB097_SET_FALCON12_V 31:0 + +#define NVB097_SET_FALCON13 0x2334 +#define NVB097_SET_FALCON13_V 31:0 + +#define NVB097_SET_FALCON14 0x2338 +#define NVB097_SET_FALCON14_V 31:0 + +#define NVB097_SET_FALCON15 0x233c +#define NVB097_SET_FALCON15_V 31:0 + +#define NVB097_SET_FALCON16 0x2340 +#define NVB097_SET_FALCON16_V 31:0 + +#define NVB097_SET_FALCON17 0x2344 +#define NVB097_SET_FALCON17_V 31:0 + +#define NVB097_SET_FALCON18 0x2348 +#define NVB097_SET_FALCON18_V 31:0 + +#define NVB097_SET_FALCON19 0x234c +#define NVB097_SET_FALCON19_V 31:0 + +#define NVB097_SET_FALCON20 0x2350 +#define NVB097_SET_FALCON20_V 31:0 + +#define NVB097_SET_FALCON21 0x2354 +#define NVB097_SET_FALCON21_V 31:0 + +#define NVB097_SET_FALCON22 0x2358 +#define NVB097_SET_FALCON22_V 31:0 + +#define NVB097_SET_FALCON23 0x235c +#define NVB097_SET_FALCON23_V 31:0 + +#define NVB097_SET_FALCON24 0x2360 +#define NVB097_SET_FALCON24_V 31:0 + +#define NVB097_SET_FALCON25 0x2364 +#define NVB097_SET_FALCON25_V 31:0 + +#define NVB097_SET_FALCON26 0x2368 +#define NVB097_SET_FALCON26_V 31:0 + +#define NVB097_SET_FALCON27 0x236c +#define NVB097_SET_FALCON27_V 31:0 + +#define NVB097_SET_FALCON28 0x2370 +#define NVB097_SET_FALCON28_V 31:0 + +#define NVB097_SET_FALCON29 0x2374 +#define NVB097_SET_FALCON29_V 31:0 + +#define NVB097_SET_FALCON30 0x2378 +#define NVB097_SET_FALCON30_V 31:0 + +#define NVB097_SET_FALCON31 0x237c +#define NVB097_SET_FALCON31_V 31:0 + +#define NVB097_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVB097_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVB097_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVB097_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVB097_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVB097_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVB097_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVB097_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVB097_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVB097_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVB097_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVB097_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVB097_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVB097_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVB097_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVB097_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVB097_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVB097_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVB097_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVB097_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVB097_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVB097_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVB097_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVB097_SET_COLOR_CLAMP 0x2600 +#define NVB097_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVB097_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVB097_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BINDLESS_TEXTURE 0x2608 +#define NVB097_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVB097_SET_TRAP_HANDLER 0x260c +#define NVB097_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVB097_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVB097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVB097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVB097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVB097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVB097_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVB097_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB097_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVB097_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB097_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVB097_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVB097_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVB097_CALL_MME_MACRO_V 31:0 + +#define NVB097_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVB097_CALL_MME_DATA_V 31:0 + +#endif /* _cl_maxwell_a_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clb097tex.h b/userspace/sdks/nv525/nvidia/inc/class/clb097tex.h new file mode 100644 index 0000000..e5543e3 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clb097tex.h @@ -0,0 +1,2050 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2010 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLB097TEX_H__ +#define __CLB097TEX_H__ + +/* +** Texture Header State + */ + +#define NVB097_TEXHEAD0_COMPONENT_SIZES 5:0 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R32_G32_B32_A32 0x00000001 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R32_G32_B32 0x00000002 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R16_G16_B16_A16 0x00000003 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R32_G32 0x00000004 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R32_B24G8 0x00000005 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_X8B8G8R8 0x00000007 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_A8B8G8R8 0x00000008 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_A2B10G10R10 0x00000009 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R16_G16 0x0000000c +#define NVB097_TEXHEAD0_COMPONENT_SIZES_G8R24 0x0000000d +#define NVB097_TEXHEAD0_COMPONENT_SIZES_G24R8 0x0000000e +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R32 0x0000000f +#define NVB097_TEXHEAD0_COMPONENT_SIZES_A4B4G4R4 0x00000012 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_A5B5G5R1 0x00000013 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_A1B5G5R5 0x00000014 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_B5G6R5 0x00000015 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_B6G5R5 0x00000016 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_G8R8 0x00000018 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R16 0x0000001b +#define NVB097_TEXHEAD0_COMPONENT_SIZES_Y8_VIDEO 0x0000001c +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R8 0x0000001d +#define NVB097_TEXHEAD0_COMPONENT_SIZES_G4R4 0x0000001e +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R1 0x0000001f +#define NVB097_TEXHEAD0_COMPONENT_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_BF10GF11RF11 0x00000021 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_G8B8G8R8 0x00000022 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_B8G8R8G8 0x00000023 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_DXT1 0x00000024 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_DXT23 0x00000025 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_DXT45 0x00000026 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_DXN1 0x00000027 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_DXN2 0x00000028 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_BC6H_SF16 0x00000010 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_BC6H_UF16 0x00000011 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_BC7U 0x00000017 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ETC2_RGB 0x00000006 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ETC2_RGBA 0x0000000b +#define NVB097_TEXHEAD0_COMPONENT_SIZES_EAC 0x00000019 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_EACX2 0x0000001a +#define NVB097_TEXHEAD0_COMPONENT_SIZES_Z24S8 0x00000029 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_X8Z24 0x0000002a +#define NVB097_TEXHEAD0_COMPONENT_SIZES_S8Z24 0x0000002b +#define NVB097_TEXHEAD0_COMPONENT_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVB097_TEXHEAD0_COMPONENT_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVB097_TEXHEAD0_COMPONENT_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32 0x0000002f +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X24S8 0x00000030 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_Z16 0x0000003a +#define NVB097_TEXHEAD0_COMPONENT_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVB097_TEXHEAD0_COMPONENT_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVB097_TEXHEAD0_COMPONENT_SIZES_CS_BITFIELD_SIZE 0x0000003f +#define NVB097_TEXHEAD0_R_DATA_TYPE 8:6 +#define NVB097_TEXHEAD0_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD0_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD0_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD0_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD0_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD0_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD0_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD0_G_DATA_TYPE 11:9 +#define NVB097_TEXHEAD0_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD0_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD0_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD0_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD0_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD0_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD0_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD0_B_DATA_TYPE 14:12 +#define NVB097_TEXHEAD0_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD0_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD0_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD0_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD0_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD0_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD0_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD0_A_DATA_TYPE 17:15 +#define NVB097_TEXHEAD0_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD0_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD0_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD0_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD0_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD0_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD0_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD0_X_SOURCE 20:18 +#define NVB097_TEXHEAD0_X_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD0_X_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD0_X_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD0_X_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD0_X_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD0_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD0_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD0_Y_SOURCE 23:21 +#define NVB097_TEXHEAD0_Y_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD0_Y_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD0_Y_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD0_Y_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD0_Y_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD0_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD0_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD0_Z_SOURCE 26:24 +#define NVB097_TEXHEAD0_Z_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD0_Z_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD0_Z_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD0_Z_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD0_Z_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD0_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD0_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD0_W_SOURCE 29:27 +#define NVB097_TEXHEAD0_W_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD0_W_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD0_W_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD0_W_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD0_W_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD0_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD0_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD0_PACK_COMPONENTS 30:30 +#define NVB097_TEXHEAD0_USE_COMPONENT_SIZES_EXTENDED 31:31 +#define NVB097_TEXHEAD1_OFFSET_LOWER 31:0 +#define NVB097_TEXHEAD2_OFFSET_UPPER 7:0 +#define NVB097_TEXHEAD2_ANISO_SPREAD_MAX_LOG2_L_S_B 9:8 +#define NVB097_TEXHEAD2_S_R_G_B_CONVERSION 10:10 +#define NVB097_TEXHEAD2_ANISO_SPREAD_MAX_LOG2_M_S_B 11:11 +#define NVB097_TEXHEAD2_LOD_ANISO_QUALITY2 12:12 +#define NVB097_TEXHEAD2_COLOR_KEY_OP 13:13 +#define NVB097_TEXHEAD2_TEXTURE_TYPE 17:14 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVB097_TEXHEAD2_MEMORY_LAYOUT 18:18 +#define NVB097_TEXHEAD2_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB097_TEXHEAD2_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_WIDTH 21:19 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_HEIGHT 24:22 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_DEPTH 27:25 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEAD2_SECTOR_PROMOTION 29:28 +#define NVB097_TEXHEAD2_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVB097_TEXHEAD2_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVB097_TEXHEAD2_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVB097_TEXHEAD2_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVB097_TEXHEAD2_BORDER_SOURCE 30:30 +#define NVB097_TEXHEAD2_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVB097_TEXHEAD2_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVB097_TEXHEAD2_NORMALIZED_COORDS 31:31 +#define NVB097_TEXHEAD3_PITCH 19:0 +#define NVB097_TEXHEAD3_LOD_ANISO_QUALITY 20:20 +#define NVB097_TEXHEAD3_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD3_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD3_LOD_ISO_QUALITY 21:21 +#define NVB097_TEXHEAD3_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD3_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD3_ANISO_COARSE_SPREAD_MODIFIER 23:22 +#define NVB097_TEXHEAD3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD3_ANISO_SPREAD_SCALE 28:24 +#define NVB097_TEXHEAD3_USE_HEADER_OPT_CONTROL 29:29 +#define NVB097_TEXHEAD3_RESERVED3A 30:30 +#define NVB097_TEXHEAD3_RESERVED3B 31:31 +#define NVB097_TEXHEAD4_WIDTH 29:0 +#define NVB097_TEXHEAD4_DEPTH_TEXTURE 30:30 +#define NVB097_TEXHEAD4_USE_TEXTURE_HEADER_VERSION2 31:31 +#define NVB097_TEXHEAD5_HEIGHT 15:0 +#define NVB097_TEXHEAD5_DEPTH 27:16 +#define NVB097_TEXHEAD5_MAX_MIP_LEVEL 31:28 +#define NVB097_TEXHEAD6_TRILIN_OPT 4:0 +#define NVB097_TEXHEAD6_MIP_LOD_BIAS 17:5 +#define NVB097_TEXHEAD6_RESERVED6A 18:18 +#define NVB097_TEXHEAD6_ANISO_BIAS 22:19 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_FUNC 24:23 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD6_ANISO_COARSE_SPREAD_FUNC 26:25 +#define NVB097_TEXHEAD6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY 29:27 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_MODIFIER 31:30 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD7_COLOR_KEY_VALUE 31:0 + + +/* +** Texture Header State Blocklinear + */ + +#define NVB097_TEXHEAD_BL_COMPONENTS MW(6:0) +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R32 0x0000000f +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R16 0x0000001b +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R8 0x0000001d +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R1 0x0000001f +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_EAC 0x00000019 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_Z16 0x0000003a +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVB097_TEXHEAD_BL_R_DATA_TYPE MW(9:7) +#define NVB097_TEXHEAD_BL_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_BL_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_BL_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_BL_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_BL_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_BL_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_BL_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BL_G_DATA_TYPE MW(12:10) +#define NVB097_TEXHEAD_BL_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_BL_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_BL_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_BL_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_BL_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_BL_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_BL_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BL_B_DATA_TYPE MW(15:13) +#define NVB097_TEXHEAD_BL_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_BL_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_BL_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_BL_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_BL_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_BL_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_BL_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BL_A_DATA_TYPE MW(18:16) +#define NVB097_TEXHEAD_BL_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_BL_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_BL_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_BL_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_BL_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_BL_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_BL_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BL_X_SOURCE MW(21:19) +#define NVB097_TEXHEAD_BL_X_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_BL_X_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_BL_X_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_BL_X_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_BL_X_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_BL_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_BL_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BL_Y_SOURCE MW(24:22) +#define NVB097_TEXHEAD_BL_Y_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_BL_Y_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_BL_Y_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_BL_Y_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_BL_Y_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_BL_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_BL_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BL_Z_SOURCE MW(27:25) +#define NVB097_TEXHEAD_BL_Z_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_BL_Z_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_BL_Z_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_BL_Z_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_BL_Z_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_BL_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_BL_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BL_W_SOURCE MW(30:28) +#define NVB097_TEXHEAD_BL_W_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_BL_W_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_BL_W_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_BL_W_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_BL_W_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_BL_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_BL_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BL_PACK_COMPONENTS MW(31:31) +#define NVB097_TEXHEAD_BL_RESERVED1Y MW(36:32) +#define NVB097_TEXHEAD_BL_GOB_DEPTH_OFFSET MW(38:37) +#define NVB097_TEXHEAD_BL_RESERVED1X MW(40:39) +#define NVB097_TEXHEAD_BL_ADDRESS_BITS31TO9 MW(63:41) +#define NVB097_TEXHEAD_BL_ADDRESS_BITS47TO32 MW(79:64) +#define NVB097_TEXHEAD_BL_RESERVED_ADDRESS MW(84:80) +#define NVB097_TEXHEAD_BL_HEADER_VERSION MW(87:85) +#define NVB097_TEXHEAD_BL_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVB097_TEXHEAD_BL_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVB097_TEXHEAD_BL_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVB097_TEXHEAD_BL_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVB097_TEXHEAD_BL_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVB097_TEXHEAD_BL_RESERVED_HEADER_VERSION MW(88:88) +#define NVB097_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVB097_TEXHEAD_BL_RESERVED2A MW(95:93) +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_WIDTH MW(98:96) +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT MW(101:99) +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH MW(104:102) +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEAD_BL_SPARSE_ENABLE MW(105:105) +#define NVB097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS MW(108:106) +#define NVB097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVB097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEAD_BL_GOB3D MW(109:109) +#define NVB097_TEXHEAD_BL_USE_ARRAY_TILE_ALIGNMENT MW(110:110) +#define NVB097_TEXHEAD_BL_RESERVED3Z MW(111:111) +#define NVB097_TEXHEAD_BL_LOD_ANISO_QUALITY2 MW(112:112) +#define NVB097_TEXHEAD_BL_LOD_ANISO_QUALITY MW(113:113) +#define NVB097_TEXHEAD_BL_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD_BL_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD_BL_LOD_ISO_QUALITY MW(114:114) +#define NVB097_TEXHEAD_BL_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD_BL_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD_BL_ANISO_SPREAD_SCALE MW(121:117) +#define NVB097_TEXHEAD_BL_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVB097_TEXHEAD_BL_DEPTH_TEXTURE MW(123:123) +#define NVB097_TEXHEAD_BL_MAX_MIP_LEVEL MW(127:124) +#define NVB097_TEXHEAD_BL_WIDTH_MINUS_ONE MW(143:128) +#define NVB097_TEXHEAD_BL_RESERVED4A MW(146:144) +#define NVB097_TEXHEAD_BL_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVB097_TEXHEAD_BL_S_R_G_B_CONVERSION MW(150:150) +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE MW(154:151) +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVB097_TEXHEAD_BL_SECTOR_PROMOTION MW(156:155) +#define NVB097_TEXHEAD_BL_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVB097_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVB097_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVB097_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVB097_TEXHEAD_BL_BORDER_SIZE MW(159:157) +#define NVB097_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVB097_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVB097_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVB097_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVB097_TEXHEAD_BL_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVB097_TEXHEAD_BL_HEIGHT_MINUS_ONE MW(175:160) +#define NVB097_TEXHEAD_BL_DEPTH_MINUS_ONE MW(189:176) +#define NVB097_TEXHEAD_BL_RESERVED5A MW(190:190) +#define NVB097_TEXHEAD_BL_NORMALIZED_COORDS MW(191:191) +#define NVB097_TEXHEAD_BL_RESERVED6Y MW(192:192) +#define NVB097_TEXHEAD_BL_TRILIN_OPT MW(197:193) +#define NVB097_TEXHEAD_BL_MIP_LOD_BIAS MW(210:198) +#define NVB097_TEXHEAD_BL_ANISO_BIAS MW(214:211) +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY MW(221:219) +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD_BL_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVB097_TEXHEAD_BL_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT MW(235:232) +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1_CENTER 0x0000000c +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_CENTER 0x0000000d +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_CENTER 0x0000000e +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X4_REGULAR 0x0000000f +#define NVB097_TEXHEAD_BL_MIN_LOD_CLAMP MW(247:236) +#define NVB097_TEXHEAD_BL_RESERVED7Y MW(255:248) + + +/* +** Texture Header State Blocklinear Color Key + */ + +#define NVB097_TEXHEAD_BLCK_COMPONENTS MW(6:0) +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVB097_TEXHEAD_BLCK_R_DATA_TYPE MW(9:7) +#define NVB097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BLCK_G_DATA_TYPE MW(12:10) +#define NVB097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BLCK_B_DATA_TYPE MW(15:13) +#define NVB097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BLCK_A_DATA_TYPE MW(18:16) +#define NVB097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BLCK_X_SOURCE MW(21:19) +#define NVB097_TEXHEAD_BLCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_BLCK_X_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_BLCK_X_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_BLCK_X_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_BLCK_X_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_BLCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_BLCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BLCK_Y_SOURCE MW(24:22) +#define NVB097_TEXHEAD_BLCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_BLCK_Y_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_BLCK_Y_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_BLCK_Y_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_BLCK_Y_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_BLCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_BLCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BLCK_Z_SOURCE MW(27:25) +#define NVB097_TEXHEAD_BLCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_BLCK_Z_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_BLCK_Z_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_BLCK_Z_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_BLCK_Z_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_BLCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_BLCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BLCK_W_SOURCE MW(30:28) +#define NVB097_TEXHEAD_BLCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_BLCK_W_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_BLCK_W_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_BLCK_W_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_BLCK_W_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_BLCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_BLCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BLCK_PACK_COMPONENTS MW(31:31) +#define NVB097_TEXHEAD_BLCK_RESERVED1Y MW(36:32) +#define NVB097_TEXHEAD_BLCK_GOB_DEPTH_OFFSET MW(38:37) +#define NVB097_TEXHEAD_BLCK_RESERVED1X MW(40:39) +#define NVB097_TEXHEAD_BLCK_ADDRESS_BITS31TO9 MW(63:41) +#define NVB097_TEXHEAD_BLCK_ADDRESS_BITS47TO32 MW(79:64) +#define NVB097_TEXHEAD_BLCK_RESERVED_ADDRESS MW(84:80) +#define NVB097_TEXHEAD_BLCK_HEADER_VERSION MW(87:85) +#define NVB097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVB097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVB097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVB097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVB097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVB097_TEXHEAD_BLCK_RESERVED_HEADER_VERSION MW(88:88) +#define NVB097_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVB097_TEXHEAD_BLCK_RESERVED2A MW(95:93) +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_WIDTH MW(98:96) +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT MW(101:99) +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH MW(104:102) +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEAD_BLCK_SPARSE_ENABLE MW(105:105) +#define NVB097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS MW(108:106) +#define NVB097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVB097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEAD_BLCK_GOB3D MW(109:109) +#define NVB097_TEXHEAD_BLCK_USE_ARRAY_TILE_ALIGNMENT MW(110:110) +#define NVB097_TEXHEAD_BLCK_RESERVED3Z MW(111:111) +#define NVB097_TEXHEAD_BLCK_LOD_ANISO_QUALITY2 MW(112:112) +#define NVB097_TEXHEAD_BLCK_LOD_ANISO_QUALITY MW(113:113) +#define NVB097_TEXHEAD_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD_BLCK_LOD_ISO_QUALITY MW(114:114) +#define NVB097_TEXHEAD_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD_BLCK_ANISO_SPREAD_SCALE MW(121:117) +#define NVB097_TEXHEAD_BLCK_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVB097_TEXHEAD_BLCK_DEPTH_TEXTURE MW(123:123) +#define NVB097_TEXHEAD_BLCK_MAX_MIP_LEVEL MW(127:124) +#define NVB097_TEXHEAD_BLCK_WIDTH_MINUS_ONE MW(143:128) +#define NVB097_TEXHEAD_BLCK_RESERVED4A MW(146:144) +#define NVB097_TEXHEAD_BLCK_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVB097_TEXHEAD_BLCK_S_R_G_B_CONVERSION MW(150:150) +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE MW(154:151) +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVB097_TEXHEAD_BLCK_SECTOR_PROMOTION MW(156:155) +#define NVB097_TEXHEAD_BLCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVB097_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVB097_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVB097_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVB097_TEXHEAD_BLCK_BORDER_SIZE MW(159:157) +#define NVB097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVB097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVB097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVB097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVB097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVB097_TEXHEAD_BLCK_HEIGHT_MINUS_ONE MW(175:160) +#define NVB097_TEXHEAD_BLCK_DEPTH_MINUS_ONE MW(189:176) +#define NVB097_TEXHEAD_BLCK_RESERVED5A MW(190:190) +#define NVB097_TEXHEAD_BLCK_NORMALIZED_COORDS MW(191:191) +#define NVB097_TEXHEAD_BLCK_COLOR_KEY_OP MW(192:192) +#define NVB097_TEXHEAD_BLCK_TRILIN_OPT MW(197:193) +#define NVB097_TEXHEAD_BLCK_MIP_LOD_BIAS MW(210:198) +#define NVB097_TEXHEAD_BLCK_ANISO_BIAS MW(214:211) +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY MW(221:219) +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD_BLCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Header State One-D Buffer + */ + +#define NVB097_TEXHEAD_1D_COMPONENTS MW(6:0) +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R32 0x0000000f +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R16 0x0000001b +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R8 0x0000001d +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R1 0x0000001f +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_EAC 0x00000019 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_Z16 0x0000003a +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVB097_TEXHEAD_1D_R_DATA_TYPE MW(9:7) +#define NVB097_TEXHEAD_1D_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_1D_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_1D_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_1D_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_1D_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_1D_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_1D_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_1D_G_DATA_TYPE MW(12:10) +#define NVB097_TEXHEAD_1D_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_1D_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_1D_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_1D_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_1D_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_1D_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_1D_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_1D_B_DATA_TYPE MW(15:13) +#define NVB097_TEXHEAD_1D_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_1D_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_1D_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_1D_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_1D_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_1D_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_1D_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_1D_A_DATA_TYPE MW(18:16) +#define NVB097_TEXHEAD_1D_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_1D_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_1D_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_1D_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_1D_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_1D_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_1D_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_1D_X_SOURCE MW(21:19) +#define NVB097_TEXHEAD_1D_X_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_1D_X_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_1D_X_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_1D_X_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_1D_X_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_1D_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_1D_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_1D_Y_SOURCE MW(24:22) +#define NVB097_TEXHEAD_1D_Y_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_1D_Y_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_1D_Y_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_1D_Y_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_1D_Y_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_1D_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_1D_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_1D_Z_SOURCE MW(27:25) +#define NVB097_TEXHEAD_1D_Z_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_1D_Z_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_1D_Z_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_1D_Z_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_1D_Z_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_1D_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_1D_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_1D_W_SOURCE MW(30:28) +#define NVB097_TEXHEAD_1D_W_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_1D_W_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_1D_W_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_1D_W_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_1D_W_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_1D_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_1D_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_1D_PACK_COMPONENTS MW(31:31) +#define NVB097_TEXHEAD_1D_ADDRESS_BITS31TO0 MW(63:32) +#define NVB097_TEXHEAD_1D_ADDRESS_BITS47TO32 MW(79:64) +#define NVB097_TEXHEAD_1D_RESERVED_ADDRESS MW(84:80) +#define NVB097_TEXHEAD_1D_HEADER_VERSION MW(87:85) +#define NVB097_TEXHEAD_1D_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVB097_TEXHEAD_1D_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVB097_TEXHEAD_1D_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVB097_TEXHEAD_1D_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVB097_TEXHEAD_1D_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVB097_TEXHEAD_1D_RESERVED_HEADER_VERSION MW(88:88) +#define NVB097_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVB097_TEXHEAD_1D_RESERVED2A MW(95:93) +#define NVB097_TEXHEAD_1D_WIDTH_MINUS_ONE_BITS31TO16 MW(111:96) +#define NVB097_TEXHEAD_1D_RESERVED3X MW(127:112) +#define NVB097_TEXHEAD_1D_WIDTH_MINUS_ONE_BITS15TO0 MW(143:128) +#define NVB097_TEXHEAD_1D_RESERVED4A MW(146:144) +#define NVB097_TEXHEAD_1D_RESERVED4X MW(149:147) +#define NVB097_TEXHEAD_1D_S_R_G_B_CONVERSION MW(150:150) +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE MW(154:151) +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVB097_TEXHEAD_1D_SECTOR_PROMOTION MW(156:155) +#define NVB097_TEXHEAD_1D_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVB097_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVB097_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVB097_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVB097_TEXHEAD_1D_RESERVED4Y MW(159:157) +#define NVB097_TEXHEAD_1D_RESERVED5X MW(189:160) +#define NVB097_TEXHEAD_1D_RESERVED5A MW(190:190) +#define NVB097_TEXHEAD_1D_RESERVED5Y MW(191:191) +#define NVB097_TEXHEAD_1D_RESERVED6X MW(223:192) +#define NVB097_TEXHEAD_1D_RESERVED7X MW(255:224) + + +/* +** Texture Header State Pitch + */ + +#define NVB097_TEXHEAD_PITCH_COMPONENTS MW(6:0) +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32 0x0000000f +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R16 0x0000001b +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R8 0x0000001d +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R1 0x0000001f +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_EAC 0x00000019 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_Z16 0x0000003a +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVB097_TEXHEAD_PITCH_R_DATA_TYPE MW(9:7) +#define NVB097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCH_G_DATA_TYPE MW(12:10) +#define NVB097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCH_B_DATA_TYPE MW(15:13) +#define NVB097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCH_A_DATA_TYPE MW(18:16) +#define NVB097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCH_X_SOURCE MW(21:19) +#define NVB097_TEXHEAD_PITCH_X_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_PITCH_X_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_PITCH_X_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_PITCH_X_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_PITCH_X_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_PITCH_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_PITCH_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCH_Y_SOURCE MW(24:22) +#define NVB097_TEXHEAD_PITCH_Y_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_PITCH_Y_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_PITCH_Y_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_PITCH_Y_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_PITCH_Y_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_PITCH_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_PITCH_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCH_Z_SOURCE MW(27:25) +#define NVB097_TEXHEAD_PITCH_Z_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_PITCH_Z_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_PITCH_Z_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_PITCH_Z_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_PITCH_Z_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_PITCH_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_PITCH_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCH_W_SOURCE MW(30:28) +#define NVB097_TEXHEAD_PITCH_W_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_PITCH_W_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_PITCH_W_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_PITCH_W_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_PITCH_W_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_PITCH_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_PITCH_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCH_PACK_COMPONENTS MW(31:31) +#define NVB097_TEXHEAD_PITCH_RESERVED1A MW(36:32) +#define NVB097_TEXHEAD_PITCH_ADDRESS_BITS31TO5 MW(63:37) +#define NVB097_TEXHEAD_PITCH_ADDRESS_BITS47TO32 MW(79:64) +#define NVB097_TEXHEAD_PITCH_RESERVED_ADDRESS MW(84:80) +#define NVB097_TEXHEAD_PITCH_HEADER_VERSION MW(87:85) +#define NVB097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVB097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVB097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVB097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVB097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVB097_TEXHEAD_PITCH_RESERVED_HEADER_VERSION MW(88:88) +#define NVB097_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVB097_TEXHEAD_PITCH_RESERVED2A MW(95:93) +#define NVB097_TEXHEAD_PITCH_PITCH_BITS20TO5 MW(111:96) +#define NVB097_TEXHEAD_PITCH_LOD_ANISO_QUALITY2 MW(112:112) +#define NVB097_TEXHEAD_PITCH_LOD_ANISO_QUALITY MW(113:113) +#define NVB097_TEXHEAD_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD_PITCH_LOD_ISO_QUALITY MW(114:114) +#define NVB097_TEXHEAD_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD_PITCH_ANISO_SPREAD_SCALE MW(121:117) +#define NVB097_TEXHEAD_PITCH_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVB097_TEXHEAD_PITCH_DEPTH_TEXTURE MW(123:123) +#define NVB097_TEXHEAD_PITCH_MAX_MIP_LEVEL MW(127:124) +#define NVB097_TEXHEAD_PITCH_WIDTH_MINUS_ONE MW(143:128) +#define NVB097_TEXHEAD_PITCH_RESERVED4A MW(146:144) +#define NVB097_TEXHEAD_PITCH_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVB097_TEXHEAD_PITCH_S_R_G_B_CONVERSION MW(150:150) +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE MW(154:151) +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVB097_TEXHEAD_PITCH_SECTOR_PROMOTION MW(156:155) +#define NVB097_TEXHEAD_PITCH_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVB097_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVB097_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVB097_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVB097_TEXHEAD_PITCH_BORDER_SIZE MW(159:157) +#define NVB097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVB097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVB097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVB097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVB097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVB097_TEXHEAD_PITCH_HEIGHT_MINUS_ONE MW(175:160) +#define NVB097_TEXHEAD_PITCH_DEPTH_MINUS_ONE MW(189:176) +#define NVB097_TEXHEAD_PITCH_RESERVED5A MW(190:190) +#define NVB097_TEXHEAD_PITCH_NORMALIZED_COORDS MW(191:191) +#define NVB097_TEXHEAD_PITCH_RESERVED6Y MW(192:192) +#define NVB097_TEXHEAD_PITCH_TRILIN_OPT MW(197:193) +#define NVB097_TEXHEAD_PITCH_MIP_LOD_BIAS MW(210:198) +#define NVB097_TEXHEAD_PITCH_ANISO_BIAS MW(214:211) +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY MW(221:219) +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD_PITCH_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVB097_TEXHEAD_PITCH_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT MW(235:232) +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1_CENTER 0x0000000c +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_CENTER 0x0000000d +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_CENTER 0x0000000e +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X4_REGULAR 0x0000000f +#define NVB097_TEXHEAD_PITCH_MIN_LOD_CLAMP MW(247:236) +#define NVB097_TEXHEAD_PITCH_RESERVED7Y MW(255:248) + + +/* +** Texture Header State Pitch Color Key + */ + +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS MW(6:0) +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVB097_TEXHEAD_PITCHCK_R_DATA_TYPE MW(9:7) +#define NVB097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_G_DATA_TYPE MW(12:10) +#define NVB097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_B_DATA_TYPE MW(15:13) +#define NVB097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_A_DATA_TYPE MW(18:16) +#define NVB097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_X_SOURCE MW(21:19) +#define NVB097_TEXHEAD_PITCHCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_X_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_X_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_X_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_X_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_Y_SOURCE MW(24:22) +#define NVB097_TEXHEAD_PITCHCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_Y_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_Y_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_Y_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_Y_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_Z_SOURCE MW(27:25) +#define NVB097_TEXHEAD_PITCHCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_Z_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_Z_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_Z_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_Z_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_W_SOURCE MW(30:28) +#define NVB097_TEXHEAD_PITCHCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_W_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_W_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_W_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_W_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_PACK_COMPONENTS MW(31:31) +#define NVB097_TEXHEAD_PITCHCK_RESERVED1A MW(36:32) +#define NVB097_TEXHEAD_PITCHCK_ADDRESS_BITS31TO5 MW(63:37) +#define NVB097_TEXHEAD_PITCHCK_ADDRESS_BITS47TO32 MW(79:64) +#define NVB097_TEXHEAD_PITCHCK_RESERVED_ADDRESS MW(84:80) +#define NVB097_TEXHEAD_PITCHCK_HEADER_VERSION MW(87:85) +#define NVB097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_RESERVED_HEADER_VERSION MW(88:88) +#define NVB097_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVB097_TEXHEAD_PITCHCK_RESERVED2A MW(95:93) +#define NVB097_TEXHEAD_PITCHCK_PITCH_BITS20TO5 MW(111:96) +#define NVB097_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY2 MW(112:112) +#define NVB097_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY MW(113:113) +#define NVB097_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_LOD_ISO_QUALITY MW(114:114) +#define NVB097_TEXHEAD_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_ANISO_SPREAD_SCALE MW(121:117) +#define NVB097_TEXHEAD_PITCHCK_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVB097_TEXHEAD_PITCHCK_DEPTH_TEXTURE MW(123:123) +#define NVB097_TEXHEAD_PITCHCK_MAX_MIP_LEVEL MW(127:124) +#define NVB097_TEXHEAD_PITCHCK_WIDTH_MINUS_ONE MW(143:128) +#define NVB097_TEXHEAD_PITCHCK_RESERVED4A MW(146:144) +#define NVB097_TEXHEAD_PITCHCK_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVB097_TEXHEAD_PITCHCK_S_R_G_B_CONVERSION MW(150:150) +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE MW(154:151) +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVB097_TEXHEAD_PITCHCK_SECTOR_PROMOTION MW(156:155) +#define NVB097_TEXHEAD_PITCHCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_BORDER_SIZE MW(159:157) +#define NVB097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_HEIGHT_MINUS_ONE MW(175:160) +#define NVB097_TEXHEAD_PITCHCK_DEPTH_MINUS_ONE MW(189:176) +#define NVB097_TEXHEAD_PITCHCK_RESERVED5A MW(190:190) +#define NVB097_TEXHEAD_PITCHCK_NORMALIZED_COORDS MW(191:191) +#define NVB097_TEXHEAD_PITCHCK_COLOR_KEY_OP MW(192:192) +#define NVB097_TEXHEAD_PITCHCK_TRILIN_OPT MW(197:193) +#define NVB097_TEXHEAD_PITCHCK_MIP_LOD_BIAS MW(210:198) +#define NVB097_TEXHEAD_PITCHCK_ANISO_BIAS MW(214:211) +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY MW(221:219) +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Header State, Version 2 + */ + +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES 5:0 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R32_G32_B32_A32 0x00000001 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R32_G32_B32 0x00000002 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R16_G16_B16_A16 0x00000003 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R32_G32 0x00000004 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R32_B24G8 0x00000005 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_X8B8G8R8 0x00000007 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_A8B8G8R8 0x00000008 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_A2B10G10R10 0x00000009 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R16_G16 0x0000000c +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_G8R24 0x0000000d +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_G24R8 0x0000000e +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R32 0x0000000f +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_A4B4G4R4 0x00000012 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_A5B5G5R1 0x00000013 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_A1B5G5R5 0x00000014 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_B5G6R5 0x00000015 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_B6G5R5 0x00000016 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_G8R8 0x00000018 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R16 0x0000001b +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_Y8_VIDEO 0x0000001c +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R8 0x0000001d +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_G4R4 0x0000001e +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R1 0x0000001f +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_BF10GF11RF11 0x00000021 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_G8B8G8R8 0x00000022 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_B8G8R8G8 0x00000023 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_DXT1 0x00000024 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_DXT23 0x00000025 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_DXT45 0x00000026 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_DXN1 0x00000027 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_DXN2 0x00000028 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_BC6H_SF16 0x00000010 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_BC6H_UF16 0x00000011 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_BC7U 0x00000017 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ETC2_RGB 0x00000006 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ETC2_RGBA 0x0000000b +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_EAC 0x00000019 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_EACX2 0x0000001a +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_Z24S8 0x00000029 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_X8Z24 0x0000002a +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_S8Z24 0x0000002b +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32 0x0000002f +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X24S8 0x00000030 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_Z16 0x0000003a +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_CS_BITFIELD_SIZE 0x0000003f +#define NVB097_TEXHEADV2_0_R_DATA_TYPE 8:6 +#define NVB097_TEXHEADV2_0_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEADV2_0_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEADV2_0_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEADV2_0_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEADV2_0_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEADV2_0_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEADV2_0_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEADV2_0_G_DATA_TYPE 11:9 +#define NVB097_TEXHEADV2_0_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEADV2_0_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEADV2_0_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEADV2_0_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEADV2_0_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEADV2_0_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEADV2_0_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEADV2_0_B_DATA_TYPE 14:12 +#define NVB097_TEXHEADV2_0_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEADV2_0_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEADV2_0_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEADV2_0_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEADV2_0_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEADV2_0_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEADV2_0_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEADV2_0_A_DATA_TYPE 17:15 +#define NVB097_TEXHEADV2_0_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEADV2_0_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEADV2_0_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEADV2_0_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEADV2_0_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEADV2_0_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEADV2_0_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEADV2_0_X_SOURCE 20:18 +#define NVB097_TEXHEADV2_0_X_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEADV2_0_X_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEADV2_0_X_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEADV2_0_X_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEADV2_0_X_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEADV2_0_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEADV2_0_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEADV2_0_Y_SOURCE 23:21 +#define NVB097_TEXHEADV2_0_Y_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEADV2_0_Y_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEADV2_0_Y_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEADV2_0_Y_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEADV2_0_Y_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEADV2_0_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEADV2_0_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEADV2_0_Z_SOURCE 26:24 +#define NVB097_TEXHEADV2_0_Z_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEADV2_0_Z_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEADV2_0_Z_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEADV2_0_Z_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEADV2_0_Z_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEADV2_0_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEADV2_0_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEADV2_0_W_SOURCE 29:27 +#define NVB097_TEXHEADV2_0_W_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEADV2_0_W_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEADV2_0_W_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEADV2_0_W_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEADV2_0_W_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEADV2_0_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEADV2_0_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEADV2_0_PACK_COMPONENTS 30:30 +#define NVB097_TEXHEADV2_0_USE_COMPONENT_SIZES_EXTENDED 31:31 +#define NVB097_TEXHEADV2_1_OFFSET_LOWER 31:0 +#define NVB097_TEXHEADV2_2_OFFSET_UPPER 7:0 +#define NVB097_TEXHEADV2_2_ANISO_SPREAD_MAX_LOG2_L_S_B 9:8 +#define NVB097_TEXHEADV2_2_S_R_G_B_CONVERSION 10:10 +#define NVB097_TEXHEADV2_2_ANISO_SPREAD_MAX_LOG2_M_S_B 11:11 +#define NVB097_TEXHEADV2_2_LOD_ANISO_QUALITY2 12:12 +#define NVB097_TEXHEADV2_2_COLOR_KEY_OP 13:13 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE 17:14 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVB097_TEXHEADV2_2_MEMORY_LAYOUT 18:18 +#define NVB097_TEXHEADV2_2_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB097_TEXHEADV2_2_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_WIDTH 21:19 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_HEIGHT 24:22 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_DEPTH 27:25 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEADV2_2_SECTOR_PROMOTION 29:28 +#define NVB097_TEXHEADV2_2_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVB097_TEXHEADV2_2_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVB097_TEXHEADV2_2_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVB097_TEXHEADV2_2_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVB097_TEXHEADV2_2_BORDER_SOURCE 30:30 +#define NVB097_TEXHEADV2_2_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVB097_TEXHEADV2_2_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVB097_TEXHEADV2_2_NORMALIZED_COORDS 31:31 +#define NVB097_TEXHEADV2_3_PITCH 19:0 +#define NVB097_TEXHEADV2_3_LOD_ANISO_QUALITY 20:20 +#define NVB097_TEXHEADV2_3_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEADV2_3_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEADV2_3_LOD_ISO_QUALITY 21:21 +#define NVB097_TEXHEADV2_3_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEADV2_3_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEADV2_3_ANISO_COARSE_SPREAD_MODIFIER 23:22 +#define NVB097_TEXHEADV2_3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEADV2_3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEADV2_3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEADV2_3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEADV2_3_ANISO_SPREAD_SCALE 28:24 +#define NVB097_TEXHEADV2_3_USE_HEADER_OPT_CONTROL 29:29 +#define NVB097_TEXHEADV2_3_RESERVED3A 30:30 +#define NVB097_TEXHEADV2_3_RESERVED3B 31:31 +#define NVB097_TEXHEADV2_4_WIDTH 29:0 +#define NVB097_TEXHEADV2_4_DEPTH_TEXTURE 30:30 +#define NVB097_TEXHEADV2_4_USE_TEXTURE_HEADER_VERSION2 31:31 +#define NVB097_TEXHEADV2_5_HEIGHT 15:0 +#define NVB097_TEXHEADV2_5_DEPTH 27:16 +#define NVB097_TEXHEADV2_5_MAX_MIP_LEVEL 31:28 +#define NVB097_TEXHEADV2_6_TRILIN_OPT 4:0 +#define NVB097_TEXHEADV2_6_MIP_LOD_BIAS 17:5 +#define NVB097_TEXHEADV2_6_RESERVED6A 18:18 +#define NVB097_TEXHEADV2_6_ANISO_BIAS 22:19 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_FUNC 24:23 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEADV2_6_ANISO_COARSE_SPREAD_FUNC 26:25 +#define NVB097_TEXHEADV2_6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEADV2_6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEADV2_6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEADV2_6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY 29:27 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_MODIFIER 31:30 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEADV2_7_RES_VIEW_MIN_MIP_LEVEL 3:0 +#define NVB097_TEXHEADV2_7_RES_VIEW_MAX_MIP_LEVEL 7:4 +#define NVB097_TEXHEADV2_7_HEIGHT_MSB 8:8 +#define NVB097_TEXHEADV2_7_HEIGHT_MSB_RESERVED 11:9 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT 15:12 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_2X1_CENTER 0x0000000c +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_2X2_CENTER 0x0000000d +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_4X2_CENTER 0x0000000e +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_4X4_REGULAR 0x0000000f +#define NVB097_TEXHEADV2_7_MIN_LOD_CLAMP 27:16 +#define NVB097_TEXHEADV2_7_DEPTH_MSB 30:28 +#define NVB097_TEXHEADV2_7_RESERVED7A 31:31 + + +/* +** Texture Header State, Version 3 + */ + +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES 5:0 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_4X4 0x00000000 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_5X4 0x00000010 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_5X5 0x00000001 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_6X5 0x00000011 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_6X6 0x00000002 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_8X5 0x00000015 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_8X6 0x00000012 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_8X8 0x00000004 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_10X5 0x00000016 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_10X6 0x00000017 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_10X8 0x00000013 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_10X10 0x00000005 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_12X10 0x00000014 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_12X12 0x00000006 +#define NVB097_TEXHEADV3_0_R_DATA_TYPE 8:6 +#define NVB097_TEXHEADV3_0_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEADV3_0_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEADV3_0_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEADV3_0_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEADV3_0_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEADV3_0_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEADV3_0_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEADV3_0_G_DATA_TYPE 11:9 +#define NVB097_TEXHEADV3_0_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEADV3_0_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEADV3_0_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEADV3_0_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEADV3_0_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEADV3_0_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEADV3_0_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEADV3_0_B_DATA_TYPE 14:12 +#define NVB097_TEXHEADV3_0_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEADV3_0_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEADV3_0_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEADV3_0_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEADV3_0_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEADV3_0_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEADV3_0_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEADV3_0_A_DATA_TYPE 17:15 +#define NVB097_TEXHEADV3_0_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEADV3_0_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEADV3_0_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEADV3_0_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEADV3_0_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEADV3_0_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEADV3_0_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEADV3_0_X_SOURCE 20:18 +#define NVB097_TEXHEADV3_0_X_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEADV3_0_X_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEADV3_0_X_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEADV3_0_X_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEADV3_0_X_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEADV3_0_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEADV3_0_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEADV3_0_Y_SOURCE 23:21 +#define NVB097_TEXHEADV3_0_Y_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEADV3_0_Y_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEADV3_0_Y_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEADV3_0_Y_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEADV3_0_Y_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEADV3_0_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEADV3_0_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEADV3_0_Z_SOURCE 26:24 +#define NVB097_TEXHEADV3_0_Z_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEADV3_0_Z_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEADV3_0_Z_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEADV3_0_Z_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEADV3_0_Z_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEADV3_0_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEADV3_0_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEADV3_0_W_SOURCE 29:27 +#define NVB097_TEXHEADV3_0_W_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEADV3_0_W_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEADV3_0_W_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEADV3_0_W_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEADV3_0_W_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEADV3_0_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEADV3_0_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEADV3_0_PACK_COMPONENTS 30:30 +#define NVB097_TEXHEADV3_0_USE_COMPONENT_SIZES_EXTENDED 31:31 +#define NVB097_TEXHEADV3_1_OFFSET_LOWER 31:0 +#define NVB097_TEXHEADV3_2_OFFSET_UPPER 7:0 +#define NVB097_TEXHEADV3_2_ANISO_SPREAD_MAX_LOG2_L_S_B 9:8 +#define NVB097_TEXHEADV3_2_S_R_G_B_CONVERSION 10:10 +#define NVB097_TEXHEADV3_2_ANISO_SPREAD_MAX_LOG2_M_S_B 11:11 +#define NVB097_TEXHEADV3_2_LOD_ANISO_QUALITY2 12:12 +#define NVB097_TEXHEADV3_2_COLOR_KEY_OP 13:13 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE 17:14 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVB097_TEXHEADV3_2_MEMORY_LAYOUT 18:18 +#define NVB097_TEXHEADV3_2_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB097_TEXHEADV3_2_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_WIDTH 21:19 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_HEIGHT 24:22 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_DEPTH 27:25 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEADV3_2_SECTOR_PROMOTION 29:28 +#define NVB097_TEXHEADV3_2_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVB097_TEXHEADV3_2_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVB097_TEXHEADV3_2_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVB097_TEXHEADV3_2_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVB097_TEXHEADV3_2_BORDER_SOURCE 30:30 +#define NVB097_TEXHEADV3_2_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVB097_TEXHEADV3_2_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVB097_TEXHEADV3_2_NORMALIZED_COORDS 31:31 +#define NVB097_TEXHEADV3_3_PITCH 19:0 +#define NVB097_TEXHEADV3_3_LOD_ANISO_QUALITY 20:20 +#define NVB097_TEXHEADV3_3_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEADV3_3_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEADV3_3_LOD_ISO_QUALITY 21:21 +#define NVB097_TEXHEADV3_3_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEADV3_3_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEADV3_3_ANISO_COARSE_SPREAD_MODIFIER 23:22 +#define NVB097_TEXHEADV3_3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEADV3_3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEADV3_3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEADV3_3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEADV3_3_ANISO_SPREAD_SCALE 28:24 +#define NVB097_TEXHEADV3_3_USE_HEADER_OPT_CONTROL 29:29 +#define NVB097_TEXHEADV3_3_RESERVED3A 30:30 +#define NVB097_TEXHEADV3_3_RESERVED3B 31:31 +#define NVB097_TEXHEADV3_4_WIDTH 29:0 +#define NVB097_TEXHEADV3_4_DEPTH_TEXTURE 30:30 +#define NVB097_TEXHEADV3_4_USE_TEXTURE_HEADER_VERSION2 31:31 +#define NVB097_TEXHEADV3_5_HEIGHT 15:0 +#define NVB097_TEXHEADV3_5_DEPTH 27:16 +#define NVB097_TEXHEADV3_5_MAX_MIP_LEVEL 31:28 +#define NVB097_TEXHEADV3_6_TRILIN_OPT 4:0 +#define NVB097_TEXHEADV3_6_MIP_LOD_BIAS 17:5 +#define NVB097_TEXHEADV3_6_RESERVED6A 18:18 +#define NVB097_TEXHEADV3_6_ANISO_BIAS 22:19 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_FUNC 24:23 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEADV3_6_ANISO_COARSE_SPREAD_FUNC 26:25 +#define NVB097_TEXHEADV3_6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEADV3_6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEADV3_6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEADV3_6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY 29:27 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_MODIFIER 31:30 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEADV3_7_RES_VIEW_MIN_MIP_LEVEL 3:0 +#define NVB097_TEXHEADV3_7_RES_VIEW_MAX_MIP_LEVEL 7:4 +#define NVB097_TEXHEADV3_7_HEIGHT_MSB 8:8 +#define NVB097_TEXHEADV3_7_HEIGHT_MSB_RESERVED 11:9 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT 15:12 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_2X1_CENTER 0x0000000c +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_2X2_CENTER 0x0000000d +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_4X2_CENTER 0x0000000e +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_4X4_REGULAR 0x0000000f +#define NVB097_TEXHEADV3_7_MIN_LOD_CLAMP 27:16 +#define NVB097_TEXHEADV3_7_DEPTH_MSB 30:28 +#define NVB097_TEXHEADV3_7_RESERVED7A 31:31 + + +/* +** Texture Sampler State + */ + +#define NVB097_TEXSAMP0_ADDRESS_U 2:0 +#define NVB097_TEXSAMP0_ADDRESS_U_WRAP 0x00000000 +#define NVB097_TEXSAMP0_ADDRESS_U_MIRROR 0x00000001 +#define NVB097_TEXSAMP0_ADDRESS_U_CLAMP_TO_EDGE 0x00000002 +#define NVB097_TEXSAMP0_ADDRESS_U_BORDER 0x00000003 +#define NVB097_TEXSAMP0_ADDRESS_U_CLAMP_OGL 0x00000004 +#define NVB097_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVB097_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_BORDER 0x00000006 +#define NVB097_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVB097_TEXSAMP0_ADDRESS_V 5:3 +#define NVB097_TEXSAMP0_ADDRESS_V_WRAP 0x00000000 +#define NVB097_TEXSAMP0_ADDRESS_V_MIRROR 0x00000001 +#define NVB097_TEXSAMP0_ADDRESS_V_CLAMP_TO_EDGE 0x00000002 +#define NVB097_TEXSAMP0_ADDRESS_V_BORDER 0x00000003 +#define NVB097_TEXSAMP0_ADDRESS_V_CLAMP_OGL 0x00000004 +#define NVB097_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVB097_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_BORDER 0x00000006 +#define NVB097_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVB097_TEXSAMP0_ADDRESS_P 8:6 +#define NVB097_TEXSAMP0_ADDRESS_P_WRAP 0x00000000 +#define NVB097_TEXSAMP0_ADDRESS_P_MIRROR 0x00000001 +#define NVB097_TEXSAMP0_ADDRESS_P_CLAMP_TO_EDGE 0x00000002 +#define NVB097_TEXSAMP0_ADDRESS_P_BORDER 0x00000003 +#define NVB097_TEXSAMP0_ADDRESS_P_CLAMP_OGL 0x00000004 +#define NVB097_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVB097_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_BORDER 0x00000006 +#define NVB097_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVB097_TEXSAMP0_DEPTH_COMPARE 9:9 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC 12:10 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_NEVER 0x00000000 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_LESS 0x00000001 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_EQUAL 0x00000002 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_LEQUAL 0x00000003 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_GREATER 0x00000004 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_NOTEQUAL 0x00000005 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_GEQUAL 0x00000006 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_ALWAYS 0x00000007 +#define NVB097_TEXSAMP0_S_R_G_B_CONVERSION 13:13 +#define NVB097_TEXSAMP0_RESERVED0A 16:14 +#define NVB097_TEXSAMP0_RESERVED0B 19:17 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY 22:20 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVB097_TEXSAMP1_MAG_FILTER 2:0 +#define NVB097_TEXSAMP1_MAG_FILTER_MAG_POINT 0x00000001 +#define NVB097_TEXSAMP1_MAG_FILTER_MAG_LINEAR 0x00000002 +#define NVB097_TEXSAMP1_MAG_FILTER_VCAA_4_TAP 0x00000003 +#define NVB097_TEXSAMP1_MAG_FILTER_VCAA_8_TAP 0x00000004 +#define NVB097_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP 3:3 +#define NVB097_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP_INTEGER_AND_FRACTION 0x00000000 +#define NVB097_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP_INTEGER_ONLY 0x00000001 +#define NVB097_TEXSAMP1_MIN_FILTER 5:4 +#define NVB097_TEXSAMP1_MIN_FILTER_MIN_POINT 0x00000001 +#define NVB097_TEXSAMP1_MIN_FILTER_MIN_LINEAR 0x00000002 +#define NVB097_TEXSAMP1_MIN_FILTER_MIN_ANISO 0x00000003 +#define NVB097_TEXSAMP1_MIP_FILTER 7:6 +#define NVB097_TEXSAMP1_MIP_FILTER_MIP_NONE 0x00000001 +#define NVB097_TEXSAMP1_MIP_FILTER_MIP_POINT 0x00000002 +#define NVB097_TEXSAMP1_MIP_FILTER_MIP_LINEAR 0x00000003 +#define NVB097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING 9:8 +#define NVB097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_USE_WRAP 0x00000000 +#define NVB097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_OVERRIDE_WRAP 0x00000001 +#define NVB097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_AUTO_SPAN_SEAM 0x00000002 +#define NVB097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_AUTO_CROSS_SEAM 0x00000003 +#define NVB097_TEXSAMP1_MIP_LOD_BIAS 24:12 +#define NVB097_TEXSAMP1_FLOAT_COORD_NORMALIZATION 25:25 +#define NVB097_TEXSAMP1_FLOAT_COORD_NORMALIZATION_USE_HEADER_SETTING 0x00000000 +#define NVB097_TEXSAMP1_FLOAT_COORD_NORMALIZATION_FORCE_UNNORMALIZED_COORDS 0x00000001 +#define NVB097_TEXSAMP1_TRILIN_OPT 30:26 +#define NVB097_TEXSAMP2_MIN_LOD_CLAMP 11:0 +#define NVB097_TEXSAMP2_MAX_LOD_CLAMP 23:12 +#define NVB097_TEXSAMP2_S_R_G_B_BORDER_COLOR_R 31:24 +#define NVB097_TEXSAMP3_RESERVED12 11:0 +#define NVB097_TEXSAMP3_S_R_G_B_BORDER_COLOR_G 19:12 +#define NVB097_TEXSAMP3_S_R_G_B_BORDER_COLOR_B 27:20 +#define NVB097_TEXSAMP4_BORDER_COLOR_R 31:0 +#define NVB097_TEXSAMP5_BORDER_COLOR_G 31:0 +#define NVB097_TEXSAMP6_BORDER_COLOR_B 31:0 +#define NVB097_TEXSAMP7_BORDER_COLOR_A 31:0 + + + +#endif // #ifndef __CLB097TEX_H__ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clb0b0.h b/userspace/sdks/nv525/nvidia/inc/class/clb0b0.h new file mode 100644 index 0000000..030040c --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clb0b0.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "nvtypes.h" + +#ifndef _clb0b0_h_ +#define _clb0b0_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVB0B0_VIDEO_DECODER (0x0000B0B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clb0b0_h diff --git a/userspace/sdks/nv525/nvidia/inc/class/clb0b5.h b/userspace/sdks/nv525/nvidia/inc/class/clb0b5.h new file mode 100644 index 0000000..63fe695 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clb0b5.h @@ -0,0 +1,261 @@ +/******************************************************************************* + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clb0b5_h_ +#define _clb0b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define MAXWELL_DMA_COPY_A (0x0000B0B5) + +#define NVB0B5_NOP (0x00000100) +#define NVB0B5_NOP_PARAMETER 31:0 +#define NVB0B5_PM_TRIGGER (0x00000140) +#define NVB0B5_PM_TRIGGER_V 31:0 +#define NVB0B5_SET_SEMAPHORE_A (0x00000240) +#define NVB0B5_SET_SEMAPHORE_A_UPPER 7:0 +#define NVB0B5_SET_SEMAPHORE_B (0x00000244) +#define NVB0B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVB0B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVB0B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVB0B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVB0B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVB0B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVB0B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVB0B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVB0B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVB0B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVB0B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVB0B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVB0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVB0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVB0B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVB0B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVB0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVB0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVB0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVB0B5_SET_DST_PHYS_MODE (0x00000264) +#define NVB0B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVB0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVB0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVB0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVB0B5_LAUNCH_DMA (0x00000300) +#define NVB0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVB0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVB0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVB0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVB0B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVB0B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVB0B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVB0B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVB0B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVB0B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVB0B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVB0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVB0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVB0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVB0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVB0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVB0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVB0B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVB0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVB0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVB0B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVB0B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVB0B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVB0B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVB0B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVB0B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVB0B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVB0B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVB0B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVB0B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVB0B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVB0B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVB0B5_LAUNCH_DMA_BYPASS_L2 20:20 +#define NVB0B5_LAUNCH_DMA_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVB0B5_LAUNCH_DMA_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVB0B5_OFFSET_IN_UPPER (0x00000400) +#define NVB0B5_OFFSET_IN_UPPER_UPPER 7:0 +#define NVB0B5_OFFSET_IN_LOWER (0x00000404) +#define NVB0B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVB0B5_OFFSET_OUT_UPPER (0x00000408) +#define NVB0B5_OFFSET_OUT_UPPER_UPPER 7:0 +#define NVB0B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVB0B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVB0B5_PITCH_IN (0x00000410) +#define NVB0B5_PITCH_IN_VALUE 31:0 +#define NVB0B5_PITCH_OUT (0x00000414) +#define NVB0B5_PITCH_OUT_VALUE 31:0 +#define NVB0B5_LINE_LENGTH_IN (0x00000418) +#define NVB0B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVB0B5_LINE_COUNT (0x0000041C) +#define NVB0B5_LINE_COUNT_VALUE 31:0 +#define NVB0B5_SET_REMAP_CONST_A (0x00000700) +#define NVB0B5_SET_REMAP_CONST_A_V 31:0 +#define NVB0B5_SET_REMAP_CONST_B (0x00000704) +#define NVB0B5_SET_REMAP_CONST_B_V 31:0 +#define NVB0B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVB0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVB0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVB0B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVB0B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVB0B5_SET_DST_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) +#define NVB0B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVB0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVB0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) +#define NVB0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVB0B5_SET_DST_WIDTH (0x00000710) +#define NVB0B5_SET_DST_WIDTH_V 31:0 +#define NVB0B5_SET_DST_HEIGHT (0x00000714) +#define NVB0B5_SET_DST_HEIGHT_V 31:0 +#define NVB0B5_SET_DST_DEPTH (0x00000718) +#define NVB0B5_SET_DST_DEPTH_V 31:0 +#define NVB0B5_SET_DST_LAYER (0x0000071C) +#define NVB0B5_SET_DST_LAYER_V 31:0 +#define NVB0B5_SET_DST_ORIGIN (0x00000720) +#define NVB0B5_SET_DST_ORIGIN_X 15:0 +#define NVB0B5_SET_DST_ORIGIN_Y 31:16 +#define NVB0B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVB0B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVB0B5_SET_SRC_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) +#define NVB0B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVB0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVB0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) +#define NVB0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVB0B5_SET_SRC_WIDTH (0x0000072C) +#define NVB0B5_SET_SRC_WIDTH_V 31:0 +#define NVB0B5_SET_SRC_HEIGHT (0x00000730) +#define NVB0B5_SET_SRC_HEIGHT_V 31:0 +#define NVB0B5_SET_SRC_DEPTH (0x00000734) +#define NVB0B5_SET_SRC_DEPTH_V 31:0 +#define NVB0B5_SET_SRC_LAYER (0x00000738) +#define NVB0B5_SET_SRC_LAYER_V 31:0 +#define NVB0B5_SET_SRC_ORIGIN (0x0000073C) +#define NVB0B5_SET_SRC_ORIGIN_X 15:0 +#define NVB0B5_SET_SRC_ORIGIN_Y 31:16 +#define NVB0B5_PM_TRIGGER_END (0x00001114) +#define NVB0B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clb0b5_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clb0b5sw.h b/userspace/sdks/nv525/nvidia/inc/class/clb0b5sw.h new file mode 100644 index 0000000..ff18931 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clb0b5sw.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clb0b5sw.finn +// + + + +// +// Using VERSION_0 will cause the API to interpret +// engineType as a CE engine instance. This allows +// for backward compatibility with 85B5sw and 90B5sw. +// +#define NVB0B5_ALLOCATION_PARAMETERS_VERSION_0 0 + +// +// Using VERSION_1 will cause the API to interpret +// engineType as an NV2080_ENGINE_TYPE ordinal. +// +#define NVB0B5_ALLOCATION_PARAMETERS_VERSION_1 1 + +#define NVB0B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xb0b5U) + +typedef struct NVB0B5_ALLOCATION_PARAMETERS { + NvU32 version; + NvU32 engineType; +} NVB0B5_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clb0c0.h b/userspace/sdks/nv525/nvidia/inc/class/clb0c0.h new file mode 100644 index 0000000..c343c51 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clb0c0.h @@ -0,0 +1,720 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_maxwell_compute_a_h_ +#define _cl_maxwell_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl maxwell_compute_a */ + +#include "nvtypes.h" + +#define MAXWELL_COMPUTE_A 0xB0C0 + +#define NVB0C0_SET_OBJECT 0x0000 +#define NVB0C0_SET_OBJECT_CLASS_ID 15:0 +#define NVB0C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVB0C0_NO_OPERATION 0x0100 +#define NVB0C0_NO_OPERATION_V 31:0 + +#define NVB0C0_SET_NOTIFY_A 0x0104 +#define NVB0C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_SET_NOTIFY_B 0x0108 +#define NVB0C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_NOTIFY 0x010c +#define NVB0C0_NOTIFY_TYPE 31:0 +#define NVB0C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVB0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVB0C0_WAIT_FOR_IDLE 0x0110 +#define NVB0C0_WAIT_FOR_IDLE_V 31:0 + +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB0C0_SEND_GO_IDLE 0x013c +#define NVB0C0_SEND_GO_IDLE_V 31:0 + +#define NVB0C0_PM_TRIGGER 0x0140 +#define NVB0C0_PM_TRIGGER_V 31:0 + +#define NVB0C0_PM_TRIGGER_WFI 0x0144 +#define NVB0C0_PM_TRIGGER_WFI_V 31:0 + +#define NVB0C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVB0C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVB0C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVB0C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVB0C0_LINE_LENGTH_IN 0x0180 +#define NVB0C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVB0C0_LINE_COUNT 0x0184 +#define NVB0C0_LINE_COUNT_VALUE 31:0 + +#define NVB0C0_OFFSET_OUT_UPPER 0x0188 +#define NVB0C0_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVB0C0_OFFSET_OUT 0x018c +#define NVB0C0_OFFSET_OUT_VALUE 31:0 + +#define NVB0C0_PITCH_OUT 0x0190 +#define NVB0C0_PITCH_OUT_VALUE 31:0 + +#define NVB0C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVB0C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVB0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVB0C0_SET_DST_WIDTH 0x0198 +#define NVB0C0_SET_DST_WIDTH_V 31:0 + +#define NVB0C0_SET_DST_HEIGHT 0x019c +#define NVB0C0_SET_DST_HEIGHT_V 31:0 + +#define NVB0C0_SET_DST_DEPTH 0x01a0 +#define NVB0C0_SET_DST_DEPTH_V 31:0 + +#define NVB0C0_SET_DST_LAYER 0x01a4 +#define NVB0C0_SET_DST_LAYER_V 31:0 + +#define NVB0C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVB0C0_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVB0C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVB0C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVB0C0_LAUNCH_DMA 0x01b0 +#define NVB0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVB0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVB0C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVB0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVB0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVB0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVB0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVB0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVB0C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVB0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB0C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVB0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVB0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVB0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVB0C0_LOAD_INLINE_DATA 0x01b4 +#define NVB0C0_LOAD_INLINE_DATA_V 31:0 + +#define NVB0C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVB0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVB0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVB0C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB0C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVB0C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVB0C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVB0C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVB0C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVB0C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVB0C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVB0C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVB0C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVB0C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVB0C0_PERFMON_TRANSFER 0x0210 +#define NVB0C0_PERFMON_TRANSFER_V 31:0 + +#define NVB0C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVB0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0218 +#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVB0C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVB0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVB0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVB0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVB0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVB0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVB0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVB0C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVB0C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVB0C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVB0C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVB0C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVB0C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVB0C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVB0C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVB0C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVB0C0_SET_CWD_CONTROL 0x0240 +#define NVB0C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVB0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVB0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVB0C0_SET_CWD_REF_COUNTER 0x0248 +#define NVB0C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVB0C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVB0C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVB0C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVB0C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVB0C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVB0C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVB0C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVB0C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVB0C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVB0C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVB0C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVB0C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVB0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB0C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVB0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVB0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB0C0_SET_QMD_VERSION 0x0288 +#define NVB0C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVB0C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB0C0_CHECK_QMD_VERSION 0x0290 +#define NVB0C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVB0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB0C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVB0C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVB0C0_SEND_PCAS_A 0x02b4 +#define NVB0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVB0C0_SEND_PCAS_B 0x02b8 +#define NVB0C0_SEND_PCAS_B_FROM 23:0 +#define NVB0C0_SEND_PCAS_B_DELTA 31:24 + +#define NVB0C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVB0C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVB0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVB0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVB0C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVB0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVB0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVB0C0_SET_SPA_VERSION 0x0310 +#define NVB0C0_SET_SPA_VERSION_MINOR 7:0 +#define NVB0C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVB0C0_SET_FALCON00 0x0500 +#define NVB0C0_SET_FALCON00_V 31:0 + +#define NVB0C0_SET_FALCON01 0x0504 +#define NVB0C0_SET_FALCON01_V 31:0 + +#define NVB0C0_SET_FALCON02 0x0508 +#define NVB0C0_SET_FALCON02_V 31:0 + +#define NVB0C0_SET_FALCON03 0x050c +#define NVB0C0_SET_FALCON03_V 31:0 + +#define NVB0C0_SET_FALCON04 0x0510 +#define NVB0C0_SET_FALCON04_V 31:0 + +#define NVB0C0_SET_FALCON05 0x0514 +#define NVB0C0_SET_FALCON05_V 31:0 + +#define NVB0C0_SET_FALCON06 0x0518 +#define NVB0C0_SET_FALCON06_V 31:0 + +#define NVB0C0_SET_FALCON07 0x051c +#define NVB0C0_SET_FALCON07_V 31:0 + +#define NVB0C0_SET_FALCON08 0x0520 +#define NVB0C0_SET_FALCON08_V 31:0 + +#define NVB0C0_SET_FALCON09 0x0524 +#define NVB0C0_SET_FALCON09_V 31:0 + +#define NVB0C0_SET_FALCON10 0x0528 +#define NVB0C0_SET_FALCON10_V 31:0 + +#define NVB0C0_SET_FALCON11 0x052c +#define NVB0C0_SET_FALCON11_V 31:0 + +#define NVB0C0_SET_FALCON12 0x0530 +#define NVB0C0_SET_FALCON12_V 31:0 + +#define NVB0C0_SET_FALCON13 0x0534 +#define NVB0C0_SET_FALCON13_V 31:0 + +#define NVB0C0_SET_FALCON14 0x0538 +#define NVB0C0_SET_FALCON14_V 31:0 + +#define NVB0C0_SET_FALCON15 0x053c +#define NVB0C0_SET_FALCON15_V 31:0 + +#define NVB0C0_SET_FALCON16 0x0540 +#define NVB0C0_SET_FALCON16_V 31:0 + +#define NVB0C0_SET_FALCON17 0x0544 +#define NVB0C0_SET_FALCON17_V 31:0 + +#define NVB0C0_SET_FALCON18 0x0548 +#define NVB0C0_SET_FALCON18_V 31:0 + +#define NVB0C0_SET_FALCON19 0x054c +#define NVB0C0_SET_FALCON19_V 31:0 + +#define NVB0C0_SET_FALCON20 0x0550 +#define NVB0C0_SET_FALCON20_V 31:0 + +#define NVB0C0_SET_FALCON21 0x0554 +#define NVB0C0_SET_FALCON21_V 31:0 + +#define NVB0C0_SET_FALCON22 0x0558 +#define NVB0C0_SET_FALCON22_V 31:0 + +#define NVB0C0_SET_FALCON23 0x055c +#define NVB0C0_SET_FALCON23_V 31:0 + +#define NVB0C0_SET_FALCON24 0x0560 +#define NVB0C0_SET_FALCON24_V 31:0 + +#define NVB0C0_SET_FALCON25 0x0564 +#define NVB0C0_SET_FALCON25_V 31:0 + +#define NVB0C0_SET_FALCON26 0x0568 +#define NVB0C0_SET_FALCON26_V 31:0 + +#define NVB0C0_SET_FALCON27 0x056c +#define NVB0C0_SET_FALCON27_V 31:0 + +#define NVB0C0_SET_FALCON28 0x0570 +#define NVB0C0_SET_FALCON28_V 31:0 + +#define NVB0C0_SET_FALCON29 0x0574 +#define NVB0C0_SET_FALCON29_V 31:0 + +#define NVB0C0_SET_FALCON30 0x0578 +#define NVB0C0_SET_FALCON30_V 31:0 + +#define NVB0C0_SET_FALCON31 0x057c +#define NVB0C0_SET_FALCON31_V 31:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVB0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVB0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVB0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVB0C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVB0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVB0C0_SET_SPARE_NOOP12 0x0f44 +#define NVB0C0_SET_SPARE_NOOP12_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP13 0x0f48 +#define NVB0C0_SET_SPARE_NOOP13_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP14 0x0f4c +#define NVB0C0_SET_SPARE_NOOP14_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP15 0x0f50 +#define NVB0C0_SET_SPARE_NOOP15_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP00 0x1040 +#define NVB0C0_SET_SPARE_NOOP00_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP01 0x1044 +#define NVB0C0_SET_SPARE_NOOP01_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP02 0x1048 +#define NVB0C0_SET_SPARE_NOOP02_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP03 0x104c +#define NVB0C0_SET_SPARE_NOOP03_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP04 0x1050 +#define NVB0C0_SET_SPARE_NOOP04_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP05 0x1054 +#define NVB0C0_SET_SPARE_NOOP05_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP06 0x1058 +#define NVB0C0_SET_SPARE_NOOP06_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP07 0x105c +#define NVB0C0_SET_SPARE_NOOP07_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP08 0x1060 +#define NVB0C0_SET_SPARE_NOOP08_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP09 0x1064 +#define NVB0C0_SET_SPARE_NOOP09_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP10 0x1068 +#define NVB0C0_SET_SPARE_NOOP10_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP11 0x106c +#define NVB0C0_SET_SPARE_NOOP11_V 31:0 + +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVB0C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVB0C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVB0C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVB0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVB0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVB0C0_SET_RENDER_ENABLE_A 0x1550 +#define NVB0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_RENDER_ENABLE_B 0x1554 +#define NVB0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_RENDER_ENABLE_C 0x1558 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB0C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVB0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVB0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVB0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVB0C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVB0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVB0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVB0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVB0C0_SET_PROGRAM_REGION_A 0x1608 +#define NVB0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_SET_PROGRAM_REGION_B 0x160c +#define NVB0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVB0C0_PIPE_NOP 0x1a2c +#define NVB0C0_PIPE_NOP_V 31:0 + +#define NVB0C0_SET_SPARE00 0x1a30 +#define NVB0C0_SET_SPARE00_V 31:0 + +#define NVB0C0_SET_SPARE01 0x1a34 +#define NVB0C0_SET_SPARE01_V 31:0 + +#define NVB0C0_SET_SPARE02 0x1a38 +#define NVB0C0_SET_SPARE02_V 31:0 + +#define NVB0C0_SET_SPARE03 0x1a3c +#define NVB0C0_SET_SPARE03_V 31:0 + +#define NVB0C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVB0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVB0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVB0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB0C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVB0C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVB0C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVB0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVB0C0_SET_TRAP_HANDLER 0x260c +#define NVB0C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVB0C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVB0C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB0C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVB0C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB0C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVB0C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_maxwell_compute_a_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clb0cc.h b/userspace/sdks/nv525/nvidia/inc/class/clb0cc.h new file mode 100644 index 0000000..61ee79f --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clb0cc.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clb0cc_h_ +#define _clb0cc_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define MAXWELL_PROFILER (0x0000B0CC) + +/* + * This is an interface definition for MAXWELL_PROFILER class and cannot + * be instantiated by clients. + * MAXWELL_PROFILER_DEVICE extends this interface to define interface for + * device level profiling + */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clb0cc_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clb197.h b/userspace/sdks/nv525/nvidia/inc/class/clb197.h new file mode 100644 index 0000000..f8c976c --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clb197.h @@ -0,0 +1,4160 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_maxwell_b_h_ +#define _cl_maxwell_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl maxwell_b */ + +#include "nvtypes.h" + +#define MAXWELL_B 0xB197 + +#define NVB197_SET_OBJECT 0x0000 +#define NVB197_SET_OBJECT_CLASS_ID 15:0 +#define NVB197_SET_OBJECT_ENGINE_ID 20:16 + +#define NVB197_NO_OPERATION 0x0100 +#define NVB197_NO_OPERATION_V 31:0 + +#define NVB197_SET_NOTIFY_A 0x0104 +#define NVB197_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVB197_SET_NOTIFY_B 0x0108 +#define NVB197_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVB197_NOTIFY 0x010c +#define NVB197_NOTIFY_TYPE 31:0 +#define NVB197_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVB197_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVB197_WAIT_FOR_IDLE 0x0110 +#define NVB197_WAIT_FOR_IDLE_V 31:0 + +#define NVB197_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVB197_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVB197_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVB197_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVB197_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVB197_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVB197_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVB197_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVB197_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVB197_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVB197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVB197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVB197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVB197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVB197_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVB197_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVB197_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVB197_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVB197_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB197_SEND_GO_IDLE 0x013c +#define NVB197_SEND_GO_IDLE_V 31:0 + +#define NVB197_PM_TRIGGER 0x0140 +#define NVB197_PM_TRIGGER_V 31:0 + +#define NVB197_PM_TRIGGER_WFI 0x0144 +#define NVB197_PM_TRIGGER_WFI_V 31:0 + +#define NVB197_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVB197_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVB197_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVB197_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVB197_LINE_LENGTH_IN 0x0180 +#define NVB197_LINE_LENGTH_IN_VALUE 31:0 + +#define NVB197_LINE_COUNT 0x0184 +#define NVB197_LINE_COUNT_VALUE 31:0 + +#define NVB197_OFFSET_OUT_UPPER 0x0188 +#define NVB197_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVB197_OFFSET_OUT 0x018c +#define NVB197_OFFSET_OUT_VALUE 31:0 + +#define NVB197_PITCH_OUT 0x0190 +#define NVB197_PITCH_OUT_VALUE 31:0 + +#define NVB197_SET_DST_BLOCK_SIZE 0x0194 +#define NVB197_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVB197_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVB197_SET_DST_WIDTH 0x0198 +#define NVB197_SET_DST_WIDTH_V 31:0 + +#define NVB197_SET_DST_HEIGHT 0x019c +#define NVB197_SET_DST_HEIGHT_V 31:0 + +#define NVB197_SET_DST_DEPTH 0x01a0 +#define NVB197_SET_DST_DEPTH_V 31:0 + +#define NVB197_SET_DST_LAYER 0x01a4 +#define NVB197_SET_DST_LAYER_V 31:0 + +#define NVB197_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVB197_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVB197_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVB197_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVB197_LAUNCH_DMA 0x01b0 +#define NVB197_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVB197_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB197_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB197_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVB197_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVB197_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVB197_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVB197_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVB197_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVB197_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVB197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVB197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVB197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVB197_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVB197_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB197_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB197_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB197_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVB197_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB197_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB197_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVB197_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVB197_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVB197_LOAD_INLINE_DATA 0x01b4 +#define NVB197_LOAD_INLINE_DATA_V 31:0 + +#define NVB197_SET_I2M_SEMAPHORE_A 0x01dc +#define NVB197_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVB197_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVB197_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB197_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVB197_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVB197_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVB197_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVB197_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVB197_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVB197_SET_I2M_SPARE_NOOP03 0x01fc +#define NVB197_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVB197_RUN_DS_NOW 0x0200 +#define NVB197_RUN_DS_NOW_V 31:0 + +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVB197_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVB197_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVB197_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVB197_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVB197_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVB197_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_GS_DM_FIFO 0x0214 +#define NVB197_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVB197_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVB197_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVB197_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVB197_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB197_INVALIDATE_SHADER_CACHES 0x021c +#define NVB197_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVB197_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVB197_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVB197_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVB197_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVB197_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVB197_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVB197_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVB197_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVB197_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVB197_INCREMENT_SYNC_POINT 0x02c8 +#define NVB197_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVB197_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVB197_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVB197_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVB197_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVB197_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVB197_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVB197_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NVB197_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NVB197_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVB197_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVB197_DECOMPRESS_SURFACE 0x02e0 +#define NVB197_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVB197_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVB197_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVB197_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVB197_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVB197_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVB197_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVB197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVB197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVB197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVB197_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVB197_SET_ZCULL_SUBREGION 0x02e8 +#define NVB197_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVB197_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVB197_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVB197_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVB197_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVB197_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVB197_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVB197_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVB197_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVB197_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVB197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVB197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVB197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVB197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVB197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVB197_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVB197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVB197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVB197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVB197_DRAW_ZERO_INDEX 0x0304 +#define NVB197_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVB197_SET_L1_CONFIGURATION 0x0308 +#define NVB197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVB197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVB197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVB197_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVB197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVB197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVB197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVB197_SET_SPA_VERSION 0x0310 +#define NVB197_SET_SPA_VERSION_MINOR 7:0 +#define NVB197_SET_SPA_VERSION_MAJOR 15:8 + +#define NVB197_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NVB197_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NVB197_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_SNAP_GRID_LINE 0x0318 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVB197_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVB197_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVB197_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVB197_SET_SNAP_GRID_NON_LINE 0x031c +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVB197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVB197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVB197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVB197_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVB197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVB197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVB197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVB197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVB197_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVB197_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVB197_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVB197_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVB197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVB197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVB197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVB197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVB197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVB197_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVB197_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVB197_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVB197_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVB197_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVB197_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVB197_SET_TESSELLATION_LOD_V1 0x0330 +#define NVB197_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVB197_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVB197_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVB197_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVB197_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVB197_RESERVED_TG07 0x033c +#define NVB197_RESERVED_TG07_V 0:0 + +#define NVB197_RESERVED_TG08 0x0340 +#define NVB197_RESERVED_TG08_V 0:0 + +#define NVB197_RESERVED_TG09 0x0344 +#define NVB197_RESERVED_TG09_V 0:0 + +#define NVB197_RESERVED_TG10 0x0348 +#define NVB197_RESERVED_TG10_V 0:0 + +#define NVB197_RESERVED_TG11 0x034c +#define NVB197_RESERVED_TG11_V 0:0 + +#define NVB197_RESERVED_TG12 0x0350 +#define NVB197_RESERVED_TG12_V 0:0 + +#define NVB197_RESERVED_TG13 0x0354 +#define NVB197_RESERVED_TG13_V 0:0 + +#define NVB197_RESERVED_TG14 0x0358 +#define NVB197_RESERVED_TG14_V 0:0 + +#define NVB197_RESERVED_TG15 0x035c +#define NVB197_RESERVED_TG15_V 0:0 + +#define NVB197_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVB197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVB197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVB197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVB197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVB197_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVB197_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVB197_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVB197_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVB197_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVB197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVB197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVB197_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVB197_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVB197_SET_RASTER_ENABLE 0x037c +#define NVB197_SET_RASTER_ENABLE_V 0:0 +#define NVB197_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVB197_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVB197_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVB197_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVB197_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVB197_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVB197_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVB197_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVB197_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVB197_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVB197_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVB197_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVB197_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVB197_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVB197_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVB197_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVB197_SET_RASTER_INPUT 0x0740 +#define NVB197_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVB197_SET_STREAM_OUTPUT 0x0744 +#define NVB197_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVB197_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVB197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVB197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ALPHA_FRACTION 0x074c +#define NVB197_SET_ALPHA_FRACTION_V 7:0 + +#define NVB197_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVB197_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVB197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVB197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVB197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVB197_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVB197_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVB197_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB197_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVB197_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVB197_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVB197_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVB197_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVB197_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVB197_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVB197_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVB197_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVB197_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVB197_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVB197_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVB197_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVB197_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVB197_SET_ISBE_SAVE_RESTORE_PROGRAM 0x07ac +#define NVB197_SET_ISBE_SAVE_RESTORE_PROGRAM_OFFSET 31:0 + +#define NVB197_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVB197_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVB197_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVB197_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVB197_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVB197_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVB197_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVB197_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVB197_SET_CULL_BEFORE_FETCH 0x07dc +#define NVB197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVB197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVB197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVB197_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVB197_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVB197_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVB197_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVB197_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVB197_SET_ZCULL_STORAGE_A 0x07e8 +#define NVB197_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVB197_SET_ZCULL_STORAGE_B 0x07ec +#define NVB197_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVB197_SET_ZCULL_STORAGE_C 0x07f0 +#define NVB197_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVB197_SET_ZCULL_STORAGE_D 0x07f4 +#define NVB197_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVB197_SET_ZT_READ_ONLY 0x07f8 +#define NVB197_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVB197_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVB197_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVB197_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVB197_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVB197_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVB197_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVB197_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVB197_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVB197_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVB197_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVB197_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVB197_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVB197_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVB197_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVB197_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVB197_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVB197_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVB197_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVB197_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVB197_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVB197_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVB197_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVB197_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVB197_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB197_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVB197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVB197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVB197_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVB197_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVB197_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVB197_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVB197_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVB197_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVB197_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NVB197_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NVB197_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVB197_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVB197_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVB197_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVB197_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVB197_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVB197_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVB197_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVB197_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVB197_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVB197_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVB197_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVB197_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVB197_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVB197_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVB197_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVB197_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVB197_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVB197_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVB197_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVB197_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVB197_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVB197_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVB197_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVB197_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVB197_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVB197_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVB197_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVB197_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVB197_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVB197_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVB197_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVB197_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVB197_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVB197_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVB197_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVB197_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVB197_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVB197_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVB197_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVB197_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVB197_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVB197_SET_STATISTICS_COUNTER 0x0d68 +#define NVB197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVB197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVB197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVB197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVB197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVB197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVB197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVB197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVB197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVB197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVB197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVB197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVB197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVB197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVB197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVB197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVB197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVB197_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVB197_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVB197_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVB197_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVB197_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVB197_SET_VERTEX_ARRAY_START 0x0d74 +#define NVB197_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVB197_DRAW_VERTEX_ARRAY 0x0d78 +#define NVB197_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVB197_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVB197_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVB197_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVB197_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVB197_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVB197_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVB197_SET_Z_CLEAR_VALUE 0x0d90 +#define NVB197_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVB197_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVB197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVB197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVB197_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVB197_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVB197_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVB197_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVB197_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVB197_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVB197_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVB197_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVB197_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVB197_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVB197_SET_FRONT_POLYGON_MODE 0x0dac +#define NVB197_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVB197_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVB197_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVB197_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVB197_SET_BACK_POLYGON_MODE 0x0db0 +#define NVB197_SET_BACK_POLYGON_MODE_V 31:0 +#define NVB197_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVB197_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVB197_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVB197_SET_POLY_SMOOTH 0x0db4 +#define NVB197_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVB197_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ZT_MARK 0x0db8 +#define NVB197_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NVB197_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVB197_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVB197_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVB197_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVB197_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVB197_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVB197_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVB197_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVB197_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVB197_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVB197_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_PATCH 0x0dcc +#define NVB197_SET_PATCH_SIZE 7:0 + +#define NVB197_SET_ITERATED_BLEND 0x0dd0 +#define NVB197_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVB197_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVB197_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVB197_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVB197_SET_ZCULL_CRITERION 0x0dd8 +#define NVB197_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVB197_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVB197_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVB197_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVB197_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVB197_SET_ZCULL_CRITERION_SREF 23:16 +#define NVB197_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVB197_PIXEL_SHADER_BARRIER 0x0de0 +#define NVB197_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVB197_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVB197_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVB197_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVB197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVB197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVB197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVB197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVB197_SET_WINDOW_OFFSET_X 0x0df8 +#define NVB197_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVB197_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVB197_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVB197_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVB197_SET_SCISSOR_ENABLE_V 0:0 +#define NVB197_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVB197_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVB197_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVB197_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVB197_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVB197_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVB197_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0f10 +#define NVB197_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVB197_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVB197_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVB197_SET_VPC_PERF_KNOB 0x0f14 +#define NVB197_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVB197_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVB197_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVB197_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVB197_PM_LOCAL_TRIGGER 0x0f18 +#define NVB197_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVB197_SET_POST_Z_PS_IMASK 0x0f1c +#define NVB197_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVB197_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVB197_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVB197_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVB197_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVB197_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVB197_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVB197_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVB197_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVB197_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVB197_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVB197_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVB197_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVB197_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVB197_SET_BACK_STENCIL_MASK 0x0f58 +#define NVB197_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVB197_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVB197_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVB197_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVB197_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVB197_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVB197_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVB197_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVB197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVB197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVB197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVB197_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVB197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVB197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVB197_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVB197_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVB197_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVB197_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVB197_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVB197_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVB197_SET_SAMPLE_MASK 0x0fa4 +#define NVB197_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVB197_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVB197_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVB197_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVB197_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVB197_SET_CT_MRT_ENABLE 0x0fac +#define NVB197_SET_CT_MRT_ENABLE_V 0:0 +#define NVB197_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVB197_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVB197_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVB197_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVB197_SET_TIR 0x0fb4 +#define NVB197_SET_TIR_MODE 1:0 +#define NVB197_SET_TIR_MODE_DISABLED 0x00000000 +#define NVB197_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVB197_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVB197_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVB197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVB197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVB197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVB197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVB197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVB197_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVB197_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVB197_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVB197_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVB197_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVB197_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVB197_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVB197_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVB197_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVB197_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVB197_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_TIR_MODULATION 0x0fd4 +#define NVB197_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVB197_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVB197_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVB197_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVB197_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVB197_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVB197_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVB197_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVB197_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVB197_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVB197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVB197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVB197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVB197_SET_ZT_A 0x0fe0 +#define NVB197_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_ZT_B 0x0fe4 +#define NVB197_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_ZT_FORMAT 0x0fe8 +#define NVB197_SET_ZT_FORMAT_V 4:0 +#define NVB197_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVB197_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVB197_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVB197_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVB197_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVB197_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVB197_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVB197_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVB197_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVB197_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVB197_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVB197_SET_ZT_BLOCK_SIZE 0x0fec +#define NVB197_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVB197_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB197_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVB197_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVB197_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVB197_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVB197_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVB197_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVB197_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVB197_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVB197_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVB197_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVB197_SET_TILED_CACHE_BUNDLE_CONTROL 0x0ffc +#define NVB197_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT 0:0 +#define NVB197_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_FALSE 0x00000000 +#define NVB197_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_TRUE 0x00000001 + +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB197_SET_VIEWPORT_MULTICAST 0x1004 +#define NVB197_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVB197_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVB197_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVB197_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVB197_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVB197_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVB197_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVB197_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVB197_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVB197_SET_RESERVED_SW_METHOD00 0x1014 +#define NVB197_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVB197_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVB197_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVB197_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVB197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVB197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVB197_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVB197_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVB197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVB197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_RESERVED_SW_METHOD01 0x1028 +#define NVB197_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD02 0x102c +#define NVB197_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVB197_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVB197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVB197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVB197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVB197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVB197_SET_SPARE_NOOP01 0x1044 +#define NVB197_SET_SPARE_NOOP01_V 31:0 + +#define NVB197_SET_SPARE_NOOP02 0x1048 +#define NVB197_SET_SPARE_NOOP02_V 31:0 + +#define NVB197_SET_SPARE_NOOP03 0x104c +#define NVB197_SET_SPARE_NOOP03_V 31:0 + +#define NVB197_SET_SPARE_NOOP04 0x1050 +#define NVB197_SET_SPARE_NOOP04_V 31:0 + +#define NVB197_SET_SPARE_NOOP05 0x1054 +#define NVB197_SET_SPARE_NOOP05_V 31:0 + +#define NVB197_SET_SPARE_NOOP06 0x1058 +#define NVB197_SET_SPARE_NOOP06_V 31:0 + +#define NVB197_SET_SPARE_NOOP07 0x105c +#define NVB197_SET_SPARE_NOOP07_V 31:0 + +#define NVB197_SET_SPARE_NOOP08 0x1060 +#define NVB197_SET_SPARE_NOOP08_V 31:0 + +#define NVB197_SET_SPARE_NOOP09 0x1064 +#define NVB197_SET_SPARE_NOOP09_V 31:0 + +#define NVB197_SET_SPARE_NOOP10 0x1068 +#define NVB197_SET_SPARE_NOOP10_V 31:0 + +#define NVB197_SET_SPARE_NOOP11 0x106c +#define NVB197_SET_SPARE_NOOP11_V 31:0 + +#define NVB197_SET_SPARE_NOOP12 0x1070 +#define NVB197_SET_SPARE_NOOP12_V 31:0 + +#define NVB197_SET_SPARE_NOOP13 0x1074 +#define NVB197_SET_SPARE_NOOP13_V 31:0 + +#define NVB197_SET_SPARE_NOOP14 0x1078 +#define NVB197_SET_SPARE_NOOP14_V 31:0 + +#define NVB197_SET_SPARE_NOOP15 0x107c +#define NVB197_SET_SPARE_NOOP15_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVB197_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVB197_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVB197_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD06 0x10bc +#define NVB197_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVB197_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVB197_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVB197_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVB197_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVB197_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVB197_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVB197_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD13 0x10dc +#define NVB197_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVB197_UNBIND_ALL 0x10f4 +#define NVB197_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVB197_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVB197_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVB197_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB197_SET_RESERVED_SW_METHOD14 0x1100 +#define NVB197_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD15 0x1104 +#define NVB197_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVB197_NO_OPERATION_DATA_HI 0x110c +#define NVB197_NO_OPERATION_DATA_HI_V 31:0 + +#define NVB197_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVB197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVB197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVB197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVB197_PM_TRIGGER_END 0x1114 +#define NVB197_PM_TRIGGER_END_V 31:0 + +#define NVB197_SET_VERTEX_ID_BASE 0x1118 +#define NVB197_SET_VERTEX_ID_BASE_V 31:0 + +#define NVB197_SET_STENCIL_COMPRESSION 0x111c +#define NVB197_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVB197_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVB197_SET_TIR_CONTROL 0x1130 +#define NVB197_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVB197_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVB197_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVB197_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVB197_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVB197_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVB197_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVB197_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVB197_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 + +#define NVB197_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVB197_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVB197_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVB197_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVB197_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVB197_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVB197_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVB197_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVB197_SET_FILL_VIA_TRIANGLE 0x113c +#define NVB197_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVB197_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVB197_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVB197_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVB197_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVB197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVB197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVB197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVB197_FLUSH_PENDING_WRITES 0x1144 +#define NVB197_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVB197_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVB197_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVB197_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVB197_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVB197_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVB197_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVB197_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVB197_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVB197_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVB197_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVB197_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVB197_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVB197_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVB197_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVB197_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVB197_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVB197_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVB197_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVB197_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVB197_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVB197_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB197_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ZT_SPARSE 0x1208 +#define NVB197_SET_ZT_SPARSE_ENABLE 0:0 +#define NVB197_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVB197_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVB197_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVB197_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVB197_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_SET_CT_SELECT 0x121c +#define NVB197_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVB197_SET_CT_SELECT_TARGET0 6:4 +#define NVB197_SET_CT_SELECT_TARGET1 9:7 +#define NVB197_SET_CT_SELECT_TARGET2 12:10 +#define NVB197_SET_CT_SELECT_TARGET3 15:13 +#define NVB197_SET_CT_SELECT_TARGET4 18:16 +#define NVB197_SET_CT_SELECT_TARGET5 21:19 +#define NVB197_SET_CT_SELECT_TARGET6 24:22 +#define NVB197_SET_CT_SELECT_TARGET7 27:25 + +#define NVB197_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVB197_SET_ZT_SIZE_A 0x1228 +#define NVB197_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVB197_SET_ZT_SIZE_B 0x122c +#define NVB197_SET_ZT_SIZE_B_HEIGHT 16:0 + +#define NVB197_SET_ZT_SIZE_C 0x1230 +#define NVB197_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVB197_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVB197_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVB197_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVB197_SET_SAMPLER_BINDING 0x1234 +#define NVB197_SET_SAMPLER_BINDING_V 0:0 +#define NVB197_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVB197_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVB197_DRAW_AUTO 0x123c +#define NVB197_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVB197_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVB197_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVB197_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVB197_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVB197_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVB197_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVB197_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVB197_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVB197_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVB197_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB197_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVB197_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVB197_CLEAR_ZCULL_REGION 0x12c8 +#define NVB197_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVB197_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVB197_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVB197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVB197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVB197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVB197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVB197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVB197_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVB197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVB197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVB197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVB197_SET_DEPTH_TEST 0x12cc +#define NVB197_SET_DEPTH_TEST_ENABLE 0:0 +#define NVB197_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVB197_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_FILL_MODE 0x12d0 +#define NVB197_SET_FILL_MODE_V 31:0 +#define NVB197_SET_FILL_MODE_V_POINT 0x00000001 +#define NVB197_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVB197_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVB197_SET_SHADE_MODE 0x12d4 +#define NVB197_SET_SHADE_MODE_V 31:0 +#define NVB197_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVB197_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVB197_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVB197_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVB197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVB197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVB197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVB197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVB197_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVB197_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVB197_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVB197_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_DEPTH_WRITE 0x12e8 +#define NVB197_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVB197_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ALPHA_TEST 0x12ec +#define NVB197_SET_ALPHA_TEST_ENABLE 0:0 +#define NVB197_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVB197_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVB197_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVB197_DRAW_INLINE_INDEX4X8 0x1304 +#define NVB197_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVB197_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVB197_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVB197_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVB197_D3D_SET_CULL_MODE 0x1308 +#define NVB197_D3D_SET_CULL_MODE_V 31:0 +#define NVB197_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVB197_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVB197_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVB197_SET_DEPTH_FUNC 0x130c +#define NVB197_SET_DEPTH_FUNC_V 31:0 +#define NVB197_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVB197_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVB197_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB197_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB197_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVB197_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB197_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB197_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB197_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVB197_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVB197_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB197_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB197_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVB197_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB197_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB197_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB197_SET_ALPHA_REF 0x1310 +#define NVB197_SET_ALPHA_REF_V 31:0 + +#define NVB197_SET_ALPHA_FUNC 0x1314 +#define NVB197_SET_ALPHA_FUNC_V 31:0 +#define NVB197_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVB197_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVB197_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB197_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB197_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVB197_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB197_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB197_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB197_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVB197_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVB197_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB197_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB197_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVB197_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB197_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB197_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB197_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVB197_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVB197_SET_BLEND_CONST_RED 0x131c +#define NVB197_SET_BLEND_CONST_RED_V 31:0 + +#define NVB197_SET_BLEND_CONST_GREEN 0x1320 +#define NVB197_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVB197_SET_BLEND_CONST_BLUE 0x1324 +#define NVB197_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVB197_SET_BLEND_CONST_ALPHA 0x1328 +#define NVB197_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVB197_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVB197_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVB197_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVB197_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVB197_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVB197_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVB197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVB197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVB197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BLEND_COLOR_OP 0x1340 +#define NVB197_SET_BLEND_COLOR_OP_V 31:0 +#define NVB197_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB197_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB197_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB197_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVB197_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVB197_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVB197_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB197_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB197_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVB197_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_BLEND_ALPHA_OP 0x134c +#define NVB197_SET_BLEND_ALPHA_OP_V 31:0 +#define NVB197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB197_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVB197_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVB197_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVB197_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB197_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB197_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVB197_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVB197_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVB197_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVB197_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_SINGLE_ROP_CONTROL 0x135c +#define NVB197_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVB197_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BLEND(i) (0x1360+(i)*4) +#define NVB197_SET_BLEND_ENABLE 0:0 +#define NVB197_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVB197_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_STENCIL_TEST 0x1380 +#define NVB197_SET_STENCIL_TEST_ENABLE 0:0 +#define NVB197_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_STENCIL_OP_FAIL 0x1384 +#define NVB197_SET_STENCIL_OP_FAIL_V 31:0 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVB197_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVB197_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVB197_SET_STENCIL_OP_ZPASS 0x138c +#define NVB197_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVB197_SET_STENCIL_FUNC 0x1390 +#define NVB197_SET_STENCIL_FUNC_V 31:0 +#define NVB197_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVB197_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVB197_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB197_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB197_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVB197_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB197_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB197_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB197_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVB197_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVB197_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB197_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB197_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVB197_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB197_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB197_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB197_SET_STENCIL_FUNC_REF 0x1394 +#define NVB197_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVB197_SET_STENCIL_FUNC_MASK 0x1398 +#define NVB197_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVB197_SET_STENCIL_MASK 0x139c +#define NVB197_SET_STENCIL_MASK_V 7:0 + +#define NVB197_SET_DRAW_AUTO_START 0x13a4 +#define NVB197_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVB197_SET_PS_SATURATE 0x13a8 +#define NVB197_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVB197_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVB197_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVB197_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVB197_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVB197_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVB197_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVB197_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVB197_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVB197_SET_WINDOW_ORIGIN 0x13ac +#define NVB197_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVB197_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVB197_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVB197_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVB197_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVB197_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVB197_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVB197_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVB197_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVB197_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVB197_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVB197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVB197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ALPHA_HYSTERESIS 0x1420 +#define NVB197_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NVB197_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVB197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVB197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB197_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVB197_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVB197_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVB197_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVB197_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVB197_SET_PS_WARP_WATERMARKS 0x1450 +#define NVB197_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVB197_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVB197_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVB197_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVB197_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVB197_STORE_ZCULL 0x1464 +#define NVB197_STORE_ZCULL_V 0:0 + +#define NVB197_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVB197_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVB197_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVB197_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVB197_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVB197_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVB197_LOAD_ZCULL 0x1500 +#define NVB197_LOAD_ZCULL_V 0:0 + +#define NVB197_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVB197_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVB197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVB197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVB197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVB197_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVB197_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVB197_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVB197_SET_USER_CLIP_ENABLE 0x1510 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVB197_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVB197_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVB197_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_POINT_SIZE 0x1518 +#define NVB197_SET_POINT_SIZE_V 31:0 + +#define NVB197_SET_ZCULL_STATS 0x151c +#define NVB197_SET_ZCULL_STATS_ENABLE 0:0 +#define NVB197_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_POINT_SPRITE 0x1520 +#define NVB197_SET_POINT_SPRITE_ENABLE 0:0 +#define NVB197_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_SHADER_EXCEPTIONS 0x1528 +#define NVB197_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVB197_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVB197_CLEAR_REPORT_VALUE 0x1530 +#define NVB197_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVB197_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVB197_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVB197_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVB197_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVB197_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVB197_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 + +#define NVB197_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVB197_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVB197_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_ZT_SELECT 0x1538 +#define NVB197_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVB197_SET_RENDER_ENABLE_A 0x1550 +#define NVB197_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_RENDER_ENABLE_B 0x1554 +#define NVB197_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_RENDER_ENABLE_C 0x1558 +#define NVB197_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVB197_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB197_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB197_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB197_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB197_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB197_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVB197_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVB197_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVB197_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVB197_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVB197_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVB197_SET_ANTI_ALIASED_LINE 0x1570 +#define NVB197_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVB197_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_TEX_HEADER_POOL_A 0x1574 +#define NVB197_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_TEX_HEADER_POOL_B 0x1578 +#define NVB197_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_TEX_HEADER_POOL_C 0x157c +#define NVB197_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVB197_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVB197_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVB197_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVB197_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVB197_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVB197_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVB197_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVB197_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVB197_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB197_SET_SRGB_WRITE 0x15b8 +#define NVB197_SET_SRGB_WRITE_ENABLE 0:0 +#define NVB197_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_DEPTH_BIAS 0x15bc +#define NVB197_SET_DEPTH_BIAS_V 31:0 + +#define NVB197_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVB197_SET_RT_LAYER 0x15cc +#define NVB197_SET_RT_LAYER_V 15:0 +#define NVB197_SET_RT_LAYER_CONTROL 16:16 +#define NVB197_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVB197_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVB197_SET_ANTI_ALIAS 0x15d0 +#define NVB197_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVB197_SET_EDGE_FLAG 0x15e4 +#define NVB197_SET_EDGE_FLAG_V 0:0 +#define NVB197_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVB197_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVB197_DRAW_INLINE_INDEX 0x15e8 +#define NVB197_DRAW_INLINE_INDEX_V 31:0 + +#define NVB197_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVB197_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVB197_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVB197_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVB197_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVB197_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVB197_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVB197_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVB197_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVB197_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVB197_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVB197_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVB197_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVB197_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVB197_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVB197_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVB197_SET_POINT_SPRITE_SELECT 0x1604 +#define NVB197_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVB197_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVB197_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVB197_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVB197_SET_PROGRAM_REGION_A 0x1608 +#define NVB197_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVB197_SET_PROGRAM_REGION_B 0x160c +#define NVB197_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVB197_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVB197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVB197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVB197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVB197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVB197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVB197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVB197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVB197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVB197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVB197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVB197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVB197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVB197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVB197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVB197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVB197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVB197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVB197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVB197_END 0x1614 +#define NVB197_END_V 0:0 + +#define NVB197_BEGIN 0x1618 +#define NVB197_BEGIN_OP 15:0 +#define NVB197_BEGIN_OP_POINTS 0x00000000 +#define NVB197_BEGIN_OP_LINES 0x00000001 +#define NVB197_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVB197_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVB197_BEGIN_OP_TRIANGLES 0x00000004 +#define NVB197_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVB197_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVB197_BEGIN_OP_QUADS 0x00000007 +#define NVB197_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVB197_BEGIN_OP_POLYGON 0x00000009 +#define NVB197_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVB197_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVB197_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_BEGIN_OP_PATCH 0x0000000E +#define NVB197_BEGIN_PRIMITIVE_ID 24:24 +#define NVB197_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVB197_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVB197_BEGIN_INSTANCE_ID 27:26 +#define NVB197_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVB197_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVB197_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVB197_BEGIN_SPLIT_MODE 30:29 +#define NVB197_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVB197_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVB197_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVB197_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 + +#define NVB197_SET_VERTEX_ID_COPY 0x161c +#define NVB197_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVB197_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVB197_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVB197_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVB197_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVB197_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVB197_LOAD_PRIMITIVE_ID 0x1624 +#define NVB197_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVB197_SET_SHADER_BASED_CULL 0x162c +#define NVB197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVB197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVB197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVB197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_CLASS_VERSION 0x1638 +#define NVB197_SET_CLASS_VERSION_CURRENT 15:0 +#define NVB197_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB197_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVB197_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVB197_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVB197_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVB197_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVB197_SET_DA_OUTPUT 0x164c +#define NVB197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVB197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVB197_SET_ANTI_ALIASED_POINT 0x1658 +#define NVB197_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVB197_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_POINT_CENTER_MODE 0x165c +#define NVB197_SET_POINT_CENTER_MODE_V 31:0 +#define NVB197_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVB197_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVB197_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVB197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVB197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVB197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVB197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVB197_SET_LINE_STIPPLE 0x166c +#define NVB197_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVB197_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVB197_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVB197_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVB197_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVB197_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVB197_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVB197_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVB197_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVB197_SET_PROVOKING_VERTEX 0x1684 +#define NVB197_SET_PROVOKING_VERTEX_V 0:0 +#define NVB197_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVB197_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVB197_SET_TWO_SIDED_LIGHT 0x1688 +#define NVB197_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVB197_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_POLYGON_STIPPLE 0x168c +#define NVB197_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVB197_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_SHADER_CONTROL 0x1690 +#define NVB197_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVB197_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVB197_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVB197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVB197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVB197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVB197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVB197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVB197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVB197_CHECK_CLASS_VERSION 0x16a0 +#define NVB197_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVB197_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB197_SET_SPH_VERSION 0x16a4 +#define NVB197_SET_SPH_VERSION_CURRENT 15:0 +#define NVB197_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB197_CHECK_SPH_VERSION 0x16a8 +#define NVB197_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVB197_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVB197_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVB197_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVB197_SET_AAM_VERSION 0x1790 +#define NVB197_SET_AAM_VERSION_CURRENT 15:0 +#define NVB197_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB197_CHECK_AAM_VERSION 0x1794 +#define NVB197_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVB197_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB197_SET_ZT_LAYER 0x179c +#define NVB197_SET_ZT_LAYER_OFFSET 15:0 + +#define NVB197_SET_INDEX_BUFFER_A 0x17c8 +#define NVB197_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVB197_SET_INDEX_BUFFER_B 0x17cc +#define NVB197_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVB197_SET_INDEX_BUFFER_C 0x17d0 +#define NVB197_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVB197_SET_INDEX_BUFFER_D 0x17d4 +#define NVB197_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVB197_SET_INDEX_BUFFER_E 0x17d8 +#define NVB197_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVB197_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVB197_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVB197_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVB197_SET_INDEX_BUFFER_F 0x17dc +#define NVB197_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVB197_DRAW_INDEX_BUFFER 0x17e0 +#define NVB197_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVB197_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVB197_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVB197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVB197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVB197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVB197_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVB197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVB197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVB197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVB197_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVB197_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVB197_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVB197_OGL_SET_CULL 0x1918 +#define NVB197_OGL_SET_CULL_ENABLE 0:0 +#define NVB197_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVB197_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVB197_OGL_SET_FRONT_FACE 0x191c +#define NVB197_OGL_SET_FRONT_FACE_V 31:0 +#define NVB197_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVB197_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVB197_OGL_SET_CULL_FACE 0x1920 +#define NVB197_OGL_SET_CULL_FACE_V 31:0 +#define NVB197_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVB197_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVB197_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVB197_SET_VIEWPORT_PIXEL 0x1924 +#define NVB197_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVB197_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVB197_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVB197_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVB197_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVB197_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVB197_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVB197_SET_USER_CLIP_OP 0x1940 +#define NVB197_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVB197_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVB197_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVB197_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVB197_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVB197_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVB197_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVB197_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVB197_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVB197_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVB197_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVB197_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVB197_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVB197_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVB197_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVB197_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVB197_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVB197_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVB197_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVB197_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVB197_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVB197_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVB197_INVALIDATE_ZCULL 0x1958 +#define NVB197_INVALIDATE_ZCULL_V 31:0 +#define NVB197_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVB197_SET_ZCULL 0x1968 +#define NVB197_SET_ZCULL_Z_ENABLE 0:0 +#define NVB197_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVB197_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ZCULL_BOUNDS 0x196c +#define NVB197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVB197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVB197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVB197_ZCULL_SYNC 0x1978 +#define NVB197_ZCULL_SYNC_V 31:0 + +#define NVB197_SET_CLIP_ID_TEST 0x197c +#define NVB197_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVB197_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVB197_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVB197_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVB197_SET_CLIP_ID 0x1984 +#define NVB197_SET_CLIP_ID_V 31:0 + +#define NVB197_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVB197_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVB197_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVB197_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVB197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVB197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVB197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVB197_SET_LOGIC_OP 0x19c4 +#define NVB197_SET_LOGIC_OP_ENABLE 0:0 +#define NVB197_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVB197_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_LOGIC_OP_FUNC 0x19c8 +#define NVB197_SET_LOGIC_OP_FUNC_V 31:0 +#define NVB197_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVB197_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVB197_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVB197_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVB197_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVB197_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVB197_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVB197_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVB197_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVB197_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVB197_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVB197_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVB197_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVB197_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVB197_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVB197_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVB197_SET_Z_COMPRESSION 0x19cc +#define NVB197_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVB197_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVB197_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVB197_CLEAR_SURFACE 0x19d0 +#define NVB197_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVB197_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVB197_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVB197_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVB197_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVB197_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVB197_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVB197_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVB197_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVB197_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVB197_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVB197_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVB197_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVB197_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVB197_SET_CT_WRITE_R_ENABLE 0:0 +#define NVB197_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVB197_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVB197_SET_CT_WRITE_G_ENABLE 4:4 +#define NVB197_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVB197_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVB197_SET_CT_WRITE_B_ENABLE 8:8 +#define NVB197_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVB197_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVB197_SET_CT_WRITE_A_ENABLE 12:12 +#define NVB197_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVB197_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVB197_PIPE_NOP 0x1a2c +#define NVB197_PIPE_NOP_V 31:0 + +#define NVB197_SET_SPARE00 0x1a30 +#define NVB197_SET_SPARE00_V 31:0 + +#define NVB197_SET_SPARE01 0x1a34 +#define NVB197_SET_SPARE01_V 31:0 + +#define NVB197_SET_SPARE02 0x1a38 +#define NVB197_SET_SPARE02_V 31:0 + +#define NVB197_SET_SPARE03 0x1a3c +#define NVB197_SET_SPARE03_V 31:0 + +#define NVB197_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVB197_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVB197_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVB197_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB197_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVB197_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVB197_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVB197_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVB197_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVB197_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVB197_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVB197_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVB197_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVB197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVB197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVB197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVB197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVB197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVB197_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVB197_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVB197_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVB197_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVB197_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVB197_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVB197_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVB197_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVB197_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVB197_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVB197_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVB197_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVB197_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVB197_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVB197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVB197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVB197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVB197_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVB197_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVB197_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVB197_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVB197_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVB197_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVB197_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVB197_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVB197_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVB197_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVB197_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVB197_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVB197_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVB197_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVB197_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVB197_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVB197_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVB197_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVB197_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NVB197_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NVB197_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVB197_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVB197_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVB197_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NVB197_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVB197_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVB197_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NVB197_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVB197_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NVB197_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NVB197_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVB197_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVB197_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVB197_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVB197_SET_FALCON00 0x2300 +#define NVB197_SET_FALCON00_V 31:0 + +#define NVB197_SET_FALCON01 0x2304 +#define NVB197_SET_FALCON01_V 31:0 + +#define NVB197_SET_FALCON02 0x2308 +#define NVB197_SET_FALCON02_V 31:0 + +#define NVB197_SET_FALCON03 0x230c +#define NVB197_SET_FALCON03_V 31:0 + +#define NVB197_SET_FALCON04 0x2310 +#define NVB197_SET_FALCON04_V 31:0 + +#define NVB197_SET_FALCON05 0x2314 +#define NVB197_SET_FALCON05_V 31:0 + +#define NVB197_SET_FALCON06 0x2318 +#define NVB197_SET_FALCON06_V 31:0 + +#define NVB197_SET_FALCON07 0x231c +#define NVB197_SET_FALCON07_V 31:0 + +#define NVB197_SET_FALCON08 0x2320 +#define NVB197_SET_FALCON08_V 31:0 + +#define NVB197_SET_FALCON09 0x2324 +#define NVB197_SET_FALCON09_V 31:0 + +#define NVB197_SET_FALCON10 0x2328 +#define NVB197_SET_FALCON10_V 31:0 + +#define NVB197_SET_FALCON11 0x232c +#define NVB197_SET_FALCON11_V 31:0 + +#define NVB197_SET_FALCON12 0x2330 +#define NVB197_SET_FALCON12_V 31:0 + +#define NVB197_SET_FALCON13 0x2334 +#define NVB197_SET_FALCON13_V 31:0 + +#define NVB197_SET_FALCON14 0x2338 +#define NVB197_SET_FALCON14_V 31:0 + +#define NVB197_SET_FALCON15 0x233c +#define NVB197_SET_FALCON15_V 31:0 + +#define NVB197_SET_FALCON16 0x2340 +#define NVB197_SET_FALCON16_V 31:0 + +#define NVB197_SET_FALCON17 0x2344 +#define NVB197_SET_FALCON17_V 31:0 + +#define NVB197_SET_FALCON18 0x2348 +#define NVB197_SET_FALCON18_V 31:0 + +#define NVB197_SET_FALCON19 0x234c +#define NVB197_SET_FALCON19_V 31:0 + +#define NVB197_SET_FALCON20 0x2350 +#define NVB197_SET_FALCON20_V 31:0 + +#define NVB197_SET_FALCON21 0x2354 +#define NVB197_SET_FALCON21_V 31:0 + +#define NVB197_SET_FALCON22 0x2358 +#define NVB197_SET_FALCON22_V 31:0 + +#define NVB197_SET_FALCON23 0x235c +#define NVB197_SET_FALCON23_V 31:0 + +#define NVB197_SET_FALCON24 0x2360 +#define NVB197_SET_FALCON24_V 31:0 + +#define NVB197_SET_FALCON25 0x2364 +#define NVB197_SET_FALCON25_V 31:0 + +#define NVB197_SET_FALCON26 0x2368 +#define NVB197_SET_FALCON26_V 31:0 + +#define NVB197_SET_FALCON27 0x236c +#define NVB197_SET_FALCON27_V 31:0 + +#define NVB197_SET_FALCON28 0x2370 +#define NVB197_SET_FALCON28_V 31:0 + +#define NVB197_SET_FALCON29 0x2374 +#define NVB197_SET_FALCON29_V 31:0 + +#define NVB197_SET_FALCON30 0x2378 +#define NVB197_SET_FALCON30_V 31:0 + +#define NVB197_SET_FALCON31 0x237c +#define NVB197_SET_FALCON31_V 31:0 + +#define NVB197_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVB197_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVB197_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVB197_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVB197_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVB197_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVB197_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVB197_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVB197_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVB197_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVB197_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVB197_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVB197_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVB197_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVB197_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVB197_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVB197_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVB197_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVB197_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVB197_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVB197_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVB197_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVB197_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVB197_SET_COLOR_CLAMP 0x2600 +#define NVB197_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVB197_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVB197_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BINDLESS_TEXTURE 0x2608 +#define NVB197_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVB197_SET_TRAP_HANDLER 0x260c +#define NVB197_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVB197_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVB197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVB197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVB197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVB197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVB197_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVB197_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB197_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVB197_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB197_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVB197_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVB197_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVB197_CALL_MME_MACRO_V 31:0 + +#define NVB197_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVB197_CALL_MME_DATA_V 31:0 + +#endif /* _cl_maxwell_b_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clb1c0.h b/userspace/sdks/nv525/nvidia/inc/class/clb1c0.h new file mode 100644 index 0000000..8d7aaac --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clb1c0.h @@ -0,0 +1,750 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_maxwell_compute_b_h_ +#define _cl_maxwell_compute_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl maxwell_compute_b */ + +#include "nvtypes.h" + +#define MAXWELL_COMPUTE_B 0xB1C0 + +#define NVB1C0_SET_OBJECT 0x0000 +#define NVB1C0_SET_OBJECT_CLASS_ID 15:0 +#define NVB1C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVB1C0_NO_OPERATION 0x0100 +#define NVB1C0_NO_OPERATION_V 31:0 + +#define NVB1C0_SET_NOTIFY_A 0x0104 +#define NVB1C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_SET_NOTIFY_B 0x0108 +#define NVB1C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_NOTIFY 0x010c +#define NVB1C0_NOTIFY_TYPE 31:0 +#define NVB1C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVB1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVB1C0_WAIT_FOR_IDLE 0x0110 +#define NVB1C0_WAIT_FOR_IDLE_V 31:0 + +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB1C0_SEND_GO_IDLE 0x013c +#define NVB1C0_SEND_GO_IDLE_V 31:0 + +#define NVB1C0_PM_TRIGGER 0x0140 +#define NVB1C0_PM_TRIGGER_V 31:0 + +#define NVB1C0_PM_TRIGGER_WFI 0x0144 +#define NVB1C0_PM_TRIGGER_WFI_V 31:0 + +#define NVB1C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVB1C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVB1C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVB1C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVB1C0_LINE_LENGTH_IN 0x0180 +#define NVB1C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVB1C0_LINE_COUNT 0x0184 +#define NVB1C0_LINE_COUNT_VALUE 31:0 + +#define NVB1C0_OFFSET_OUT_UPPER 0x0188 +#define NVB1C0_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVB1C0_OFFSET_OUT 0x018c +#define NVB1C0_OFFSET_OUT_VALUE 31:0 + +#define NVB1C0_PITCH_OUT 0x0190 +#define NVB1C0_PITCH_OUT_VALUE 31:0 + +#define NVB1C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVB1C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVB1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVB1C0_SET_DST_WIDTH 0x0198 +#define NVB1C0_SET_DST_WIDTH_V 31:0 + +#define NVB1C0_SET_DST_HEIGHT 0x019c +#define NVB1C0_SET_DST_HEIGHT_V 31:0 + +#define NVB1C0_SET_DST_DEPTH 0x01a0 +#define NVB1C0_SET_DST_DEPTH_V 31:0 + +#define NVB1C0_SET_DST_LAYER 0x01a4 +#define NVB1C0_SET_DST_LAYER_V 31:0 + +#define NVB1C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVB1C0_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVB1C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVB1C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVB1C0_LAUNCH_DMA 0x01b0 +#define NVB1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVB1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVB1C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVB1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVB1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVB1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVB1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVB1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVB1C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVB1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB1C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVB1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVB1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVB1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVB1C0_LOAD_INLINE_DATA 0x01b4 +#define NVB1C0_LOAD_INLINE_DATA_V 31:0 + +#define NVB1C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVB1C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVB1C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVB1C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB1C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVB1C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVB1C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVB1C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVB1C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVB1C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVB1C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVB1C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVB1C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVB1C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVB1C0_PERFMON_TRANSFER 0x0210 +#define NVB1C0_PERFMON_TRANSFER_V 31:0 + +#define NVB1C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVB1C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0218 +#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVB1C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVB1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVB1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVB1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVB1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVB1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVB1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVB1C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVB1C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVB1C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVB1C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVB1C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVB1C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVB1C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVB1C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVB1C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVB1C0_SET_CWD_CONTROL 0x0240 +#define NVB1C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVB1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVB1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVB1C0_SET_CWD_REF_COUNTER 0x0248 +#define NVB1C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVB1C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVB1C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVB1C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVB1C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVB1C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVB1C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVB1C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVB1C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVB1C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVB1C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVB1C0_SET_GWC_SCG_TYPE 0x026c +#define NVB1C0_SET_GWC_SCG_TYPE_SCG_TYPE 0:0 +#define NVB1C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0 0x00000000 +#define NVB1C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1 0x00000001 + +#define NVB1C0_SET_SCG_CONTROL 0x0270 +#define NVB1C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 + +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVB1C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVB1C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVB1C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB1C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVB1C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVB1C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB1C0_SET_QMD_VERSION 0x0288 +#define NVB1C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVB1C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB1C0_SET_WFI_CONFIG 0x028c +#define NVB1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI 0:0 +#define NVB1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE 0x00000000 +#define NVB1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE 0x00000001 + +#define NVB1C0_CHECK_QMD_VERSION 0x0290 +#define NVB1C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVB1C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB1C0_WAIT_FOR_IDLE_SCG_TYPE 0x0294 +#define NVB1C0_WAIT_FOR_IDLE_SCG_TYPE_V 31:0 + +#define NVB1C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVB1C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL 0x029c +#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE 0:0 +#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE 0x00000001 + +#define NVB1C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVB1C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVB1C0_SEND_PCAS_A 0x02b4 +#define NVB1C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVB1C0_SEND_PCAS_B 0x02b8 +#define NVB1C0_SEND_PCAS_B_FROM 23:0 +#define NVB1C0_SEND_PCAS_B_DELTA 31:24 + +#define NVB1C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVB1C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVB1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVB1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVB1C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVB1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVB1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVB1C0_SET_SPA_VERSION 0x0310 +#define NVB1C0_SET_SPA_VERSION_MINOR 7:0 +#define NVB1C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVB1C0_SET_FALCON00 0x0500 +#define NVB1C0_SET_FALCON00_V 31:0 + +#define NVB1C0_SET_FALCON01 0x0504 +#define NVB1C0_SET_FALCON01_V 31:0 + +#define NVB1C0_SET_FALCON02 0x0508 +#define NVB1C0_SET_FALCON02_V 31:0 + +#define NVB1C0_SET_FALCON03 0x050c +#define NVB1C0_SET_FALCON03_V 31:0 + +#define NVB1C0_SET_FALCON04 0x0510 +#define NVB1C0_SET_FALCON04_V 31:0 + +#define NVB1C0_SET_FALCON05 0x0514 +#define NVB1C0_SET_FALCON05_V 31:0 + +#define NVB1C0_SET_FALCON06 0x0518 +#define NVB1C0_SET_FALCON06_V 31:0 + +#define NVB1C0_SET_FALCON07 0x051c +#define NVB1C0_SET_FALCON07_V 31:0 + +#define NVB1C0_SET_FALCON08 0x0520 +#define NVB1C0_SET_FALCON08_V 31:0 + +#define NVB1C0_SET_FALCON09 0x0524 +#define NVB1C0_SET_FALCON09_V 31:0 + +#define NVB1C0_SET_FALCON10 0x0528 +#define NVB1C0_SET_FALCON10_V 31:0 + +#define NVB1C0_SET_FALCON11 0x052c +#define NVB1C0_SET_FALCON11_V 31:0 + +#define NVB1C0_SET_FALCON12 0x0530 +#define NVB1C0_SET_FALCON12_V 31:0 + +#define NVB1C0_SET_FALCON13 0x0534 +#define NVB1C0_SET_FALCON13_V 31:0 + +#define NVB1C0_SET_FALCON14 0x0538 +#define NVB1C0_SET_FALCON14_V 31:0 + +#define NVB1C0_SET_FALCON15 0x053c +#define NVB1C0_SET_FALCON15_V 31:0 + +#define NVB1C0_SET_FALCON16 0x0540 +#define NVB1C0_SET_FALCON16_V 31:0 + +#define NVB1C0_SET_FALCON17 0x0544 +#define NVB1C0_SET_FALCON17_V 31:0 + +#define NVB1C0_SET_FALCON18 0x0548 +#define NVB1C0_SET_FALCON18_V 31:0 + +#define NVB1C0_SET_FALCON19 0x054c +#define NVB1C0_SET_FALCON19_V 31:0 + +#define NVB1C0_SET_FALCON20 0x0550 +#define NVB1C0_SET_FALCON20_V 31:0 + +#define NVB1C0_SET_FALCON21 0x0554 +#define NVB1C0_SET_FALCON21_V 31:0 + +#define NVB1C0_SET_FALCON22 0x0558 +#define NVB1C0_SET_FALCON22_V 31:0 + +#define NVB1C0_SET_FALCON23 0x055c +#define NVB1C0_SET_FALCON23_V 31:0 + +#define NVB1C0_SET_FALCON24 0x0560 +#define NVB1C0_SET_FALCON24_V 31:0 + +#define NVB1C0_SET_FALCON25 0x0564 +#define NVB1C0_SET_FALCON25_V 31:0 + +#define NVB1C0_SET_FALCON26 0x0568 +#define NVB1C0_SET_FALCON26_V 31:0 + +#define NVB1C0_SET_FALCON27 0x056c +#define NVB1C0_SET_FALCON27_V 31:0 + +#define NVB1C0_SET_FALCON28 0x0570 +#define NVB1C0_SET_FALCON28_V 31:0 + +#define NVB1C0_SET_FALCON29 0x0574 +#define NVB1C0_SET_FALCON29_V 31:0 + +#define NVB1C0_SET_FALCON30 0x0578 +#define NVB1C0_SET_FALCON30_V 31:0 + +#define NVB1C0_SET_FALCON31 0x057c +#define NVB1C0_SET_FALCON31_V 31:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVB1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVB1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVB1C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVB1C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVB1C0_SET_SPARE_NOOP12 0x0f44 +#define NVB1C0_SET_SPARE_NOOP12_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP13 0x0f48 +#define NVB1C0_SET_SPARE_NOOP13_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP14 0x0f4c +#define NVB1C0_SET_SPARE_NOOP14_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP15 0x0f50 +#define NVB1C0_SET_SPARE_NOOP15_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP00 0x1040 +#define NVB1C0_SET_SPARE_NOOP00_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP01 0x1044 +#define NVB1C0_SET_SPARE_NOOP01_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP02 0x1048 +#define NVB1C0_SET_SPARE_NOOP02_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP03 0x104c +#define NVB1C0_SET_SPARE_NOOP03_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP04 0x1050 +#define NVB1C0_SET_SPARE_NOOP04_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP05 0x1054 +#define NVB1C0_SET_SPARE_NOOP05_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP06 0x1058 +#define NVB1C0_SET_SPARE_NOOP06_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP07 0x105c +#define NVB1C0_SET_SPARE_NOOP07_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP08 0x1060 +#define NVB1C0_SET_SPARE_NOOP08_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP09 0x1064 +#define NVB1C0_SET_SPARE_NOOP09_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP10 0x1068 +#define NVB1C0_SET_SPARE_NOOP10_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP11 0x106c +#define NVB1C0_SET_SPARE_NOOP11_V 31:0 + +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVB1C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVB1C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVB1C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVB1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVB1C0_SET_RENDER_ENABLE_A 0x1550 +#define NVB1C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_RENDER_ENABLE_B 0x1554 +#define NVB1C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_RENDER_ENABLE_C 0x1558 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB1C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVB1C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVB1C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVB1C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVB1C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVB1C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVB1C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVB1C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVB1C0_SET_PROGRAM_REGION_A 0x1608 +#define NVB1C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_SET_PROGRAM_REGION_B 0x160c +#define NVB1C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVB1C0_PIPE_NOP 0x1a2c +#define NVB1C0_PIPE_NOP_V 31:0 + +#define NVB1C0_SET_SPARE00 0x1a30 +#define NVB1C0_SET_SPARE00_V 31:0 + +#define NVB1C0_SET_SPARE01 0x1a34 +#define NVB1C0_SET_SPARE01_V 31:0 + +#define NVB1C0_SET_SPARE02 0x1a38 +#define NVB1C0_SET_SPARE02_V 31:0 + +#define NVB1C0_SET_SPARE03 0x1a3c +#define NVB1C0_SET_SPARE03_V 31:0 + +#define NVB1C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVB1C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVB1C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVB1C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB1C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVB1C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVB1C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVB1C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVB1C0_SET_TRAP_HANDLER 0x260c +#define NVB1C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVB1C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVB1C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB1C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVB1C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB1C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVB1C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_maxwell_compute_b_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clb2cc.h b/userspace/sdks/nv525/nvidia/inc/class/clb2cc.h new file mode 100644 index 0000000..e539404 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clb2cc.h @@ -0,0 +1,60 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clb2cc.finn +// + +#include "clb0cc.h" + +#define MAXWELL_PROFILER_DEVICE (0xb2ccU) /* finn: Evaluated from "NVB2CC_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* + * Creating the MAXWELL_PROFILER_DEVICE object: + * - The profiler object is instantiated as a child of subdevice. + */ +#define NVB2CC_ALLOC_PARAMETERS_MESSAGE_ID (0xb2ccU) + +typedef struct NVB2CC_ALLOC_PARAMETERS { + /* + * This parameter specifies the handle of the client that owns the context + * specified by hContextTarget. This can set it to 0 where a context + * specific operation is not needed. For context level operations see: + * @ref NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY, @ref NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC, + * @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM. + */ + NvHandle hClientTarget; + + /* + * This parameter specifies the handle of the BC channel (or BC channel + * group) object instance to which context-specific operations are to be + * directed. If hClientTarget is set to 0 then this parameter is ignored. + */ + NvHandle hContextTarget; +} NVB2CC_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clb4b7.h b/userspace/sdks/nv525/nvidia/inc/class/clb4b7.h new file mode 100644 index 0000000..e015151 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clb4b7.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clb4b7_h_ +#define clb4b7_h_ + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVB4B7_VIDEO_ENCODER (0x0000B4B7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clb4b7_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clb6b0.h b/userspace/sdks/nv525/nvidia/inc/class/clb6b0.h new file mode 100644 index 0000000..d79dcb4 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clb6b0.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "nvtypes.h" + +#ifndef _clb6b0_h_ +#define _clb6b0_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVB6B0_VIDEO_DECODER (0x0000B6B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clb6b0_h diff --git a/userspace/sdks/nv525/nvidia/inc/class/clb8b0.h b/userspace/sdks/nv525/nvidia/inc/class/clb8b0.h new file mode 100644 index 0000000..b2d0e09 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clb8b0.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clb8b0_h__ +#define __gh100_clb8b0_h__ +#define NVB8B0_VIDEO_DECODER (0x0000B8B0) +#endif // __gh100_clb8b0_h__ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clb8d1.h b/userspace/sdks/nv525/nvidia/inc/class/clb8d1.h new file mode 100644 index 0000000..e6c8e4c --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clb8d1.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clb8d1_h__ +#define __gh100_clb8d1_h__ +#define NVB8D1_VIDEO_NVJPG (0x0000B8D1) +#endif // __gh100_clb8d1_h__ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clb8fa.h b/userspace/sdks/nv525/nvidia/inc/class/clb8fa.h new file mode 100644 index 0000000..19edb23 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clb8fa.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clb8fa_h_ +#define _clb8fa_h_ + +#define NVB8FA_VIDEO_OFA (0x0000B8FA) + +#endif /* _clb8fa_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc06f.h b/userspace/sdks/nv525/nvidia/inc/class/clc06f.h new file mode 100644 index 0000000..d8b8607 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc06f.h @@ -0,0 +1,312 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc06f_h_ +#define _clc06f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class PASCAL_CHANNEL_GPFIFO */ +/* + * Documentation for PASCAL_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + * Note there is no .mfs file for this class. + */ +#define PASCAL_CHANNEL_GPFIFO_A (0x0000C06F) + +#define NVC06F_TYPEDEF PASCAL_CHANNELChannelGPFifoA + +/* dma flow control data structure */ +typedef volatile struct Nvc06fControl_struct { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} Nvc06fControl, PascalAControlGPFifo; + +/* fields and values */ +#define NVC06F_NUMBER_OF_SUBCHANNELS (8) +#define NVC06F_SET_OBJECT (0x00000000) +#define NVC06F_SET_OBJECT_NVCLASS 15:0 +#define NVC06F_SET_OBJECT_ENGINE 20:16 +#define NVC06F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVC06F_ILLEGAL (0x00000004) +#define NVC06F_ILLEGAL_HANDLE 31:0 +#define NVC06F_NOP (0x00000008) +#define NVC06F_NOP_HANDLE 31:0 +#define NVC06F_SEMAPHOREA (0x00000010) +#define NVC06F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVC06F_SEMAPHOREB (0x00000014) +#define NVC06F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVC06F_SEMAPHOREC (0x00000018) +#define NVC06F_SEMAPHOREC_PAYLOAD 31:0 +#define NVC06F_SEMAPHORED (0x0000001C) +#define NVC06F_SEMAPHORED_OPERATION 4:0 +#define NVC06F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVC06F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVC06F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVC06F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVC06F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 +#define NVC06F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVC06F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVC06F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVC06F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVC06F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVC06F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVC06F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVC06F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVC06F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVC06F_SEMAPHORED_REDUCTION 30:27 +#define NVC06F_SEMAPHORED_REDUCTION_MIN 0x00000000 +#define NVC06F_SEMAPHORED_REDUCTION_MAX 0x00000001 +#define NVC06F_SEMAPHORED_REDUCTION_XOR 0x00000002 +#define NVC06F_SEMAPHORED_REDUCTION_AND 0x00000003 +#define NVC06F_SEMAPHORED_REDUCTION_OR 0x00000004 +#define NVC06F_SEMAPHORED_REDUCTION_ADD 0x00000005 +#define NVC06F_SEMAPHORED_REDUCTION_INC 0x00000006 +#define NVC06F_SEMAPHORED_REDUCTION_DEC 0x00000007 +#define NVC06F_SEMAPHORED_FORMAT 31:31 +#define NVC06F_SEMAPHORED_FORMAT_SIGNED 0x00000000 +#define NVC06F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 +#define NVC06F_NON_STALL_INTERRUPT (0x00000020) +#define NVC06F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVC06F_FB_FLUSH (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR +#define NVC06F_FB_FLUSH_HANDLE 31:0 +// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for +// specifying the page address for a targeted TLB invalidate and the uTLB for +// a targeted REPLAY_CANCEL for UVM. +// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly +// rearranged fields. +#define NVC06F_MEM_OP_A (0x00000028) +#define NVC06F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC06F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC06F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11 +#define NVC06F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001 +#define NVC06F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000 +#define NVC06F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12 +#define NVC06F_MEM_OP_B (0x0000002c) +#define NVC06F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0 +#define NVC06F_MEM_OP_C (0x00000030) +#define NVC06F_MEM_OP_C_MEMBAR_TYPE 2:0 +#define NVC06F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000 +#define NVC06F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE +// MEM_OP_D MUST be preceded by MEM_OPs A-C. +#define NVC06F_MEM_OP_D (0x00000034) +#define NVC06F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE +#define NVC06F_MEM_OP_D_OPERATION 31:27 +#define NVC06F_MEM_OP_D_OPERATION_MEMBAR 0x00000005 +#define NVC06F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVC06F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a +#define NVC06F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NVC06F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +// CLEAN_LINES is an alias for Tegra/GPU IP usage +#define NVC06F_MEM_OP_D_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e +// This B alias is confusing but it was missed as part of the update. Left here +// for compatibility. +#define NVC06F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e +#define NVC06F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVC06F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVC06F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015 +#define NVC06F_SET_REFERENCE (0x00000050) +#define NVC06F_SET_REFERENCE_COUNT 31:0 +// Syncpoint methods are only available on Tegra parts. Attempting to use +// them on discrete GPUs will result in Host raising NV_PPBDMA_INTR_0_METHOD. +#define NVC06F_SYNCPOINTA (0x00000070) +#define NVC06F_SYNCPOINTA_PAYLOAD 31:0 +#define NVC06F_SYNCPOINTB (0x00000074) +#define NVC06F_SYNCPOINTB_OPERATION 0:0 +#define NVC06F_SYNCPOINTB_OPERATION_WAIT 0x00000000 +#define NVC06F_SYNCPOINTB_OPERATION_INCR 0x00000001 +#define NVC06F_SYNCPOINTB_WAIT_SWITCH 4:4 +#define NVC06F_SYNCPOINTB_WAIT_SWITCH_DIS 0x00000000 +#define NVC06F_SYNCPOINTB_WAIT_SWITCH_EN 0x00000001 +#define NVC06F_SYNCPOINTB_SYNCPT_INDEX 19:8 +#define NVC06F_WFI (0x00000078) +#define NVC06F_WFI_SCOPE 0:0 +#define NVC06F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000 +#define NVC06F_WFI_SCOPE_ALL 0x00000001 +#define NVC06F_CRC_CHECK (0x0000007c) +#define NVC06F_CRC_CHECK_VALUE 31:0 +#define NVC06F_YIELD (0x00000080) +#define NVC06F_YIELD_OP 1:0 +#define NVC06F_YIELD_OP_NOP 0x00000000 +#define NVC06F_YIELD_OP_PBDMA_TIMESLICE 0x00000001 +#define NVC06F_YIELD_OP_RUNLIST_TIMESLICE 0x00000002 +#define NVC06F_YIELD_OP_TSG 0x00000003 + + +/* GPFIFO entry format */ +#define NVC06F_GP_ENTRY__SIZE 8 +#define NVC06F_GP_ENTRY0_FETCH 0:0 +#define NVC06F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVC06F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVC06F_GP_ENTRY0_GET 31:2 +#define NVC06F_GP_ENTRY0_OPERAND 31:0 +#define NVC06F_GP_ENTRY1_GET_HI 7:0 +#define NVC06F_GP_ENTRY1_PRIV 8:8 +#define NVC06F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NVC06F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NVC06F_GP_ENTRY1_LEVEL 9:9 +#define NVC06F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVC06F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVC06F_GP_ENTRY1_LENGTH 30:10 +#define NVC06F_GP_ENTRY1_SYNC 31:31 +#define NVC06F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVC06F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVC06F_GP_ENTRY1_OPCODE 7:0 +#define NVC06F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVC06F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVC06F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVC06F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVC06F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVC06F_DMA_METHOD_ADDRESS 11:0 +#define NVC06F_DMA_SUBDEVICE_MASK 15:4 +#define NVC06F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVC06F_DMA_TERT_OP 17:16 +#define NVC06F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVC06F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVC06F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVC06F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVC06F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVC06F_DMA_METHOD_COUNT_OLD 28:18 +#define NVC06F_DMA_METHOD_COUNT 28:16 +#define NVC06F_DMA_IMMD_DATA 28:16 +#define NVC06F_DMA_SEC_OP 31:29 +#define NVC06F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVC06F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVC06F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVC06F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVC06F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVC06F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVC06F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVC06F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVC06F_DMA_INCR_ADDRESS 11:0 +#define NVC06F_DMA_INCR_SUBCHANNEL 15:13 +#define NVC06F_DMA_INCR_COUNT 28:16 +#define NVC06F_DMA_INCR_OPCODE 31:29 +#define NVC06F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVC06F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVC06F_DMA_NONINCR_ADDRESS 11:0 +#define NVC06F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVC06F_DMA_NONINCR_COUNT 28:16 +#define NVC06F_DMA_NONINCR_OPCODE 31:29 +#define NVC06F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVC06F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVC06F_DMA_ONEINCR_ADDRESS 11:0 +#define NVC06F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVC06F_DMA_ONEINCR_COUNT 28:16 +#define NVC06F_DMA_ONEINCR_OPCODE 31:29 +#define NVC06F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVC06F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVC06F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVC06F_DMA_IMMD_ADDRESS 11:0 +#define NVC06F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVC06F_DMA_IMMD_DATA 28:16 +#define NVC06F_DMA_IMMD_OPCODE 31:29 +#define NVC06F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVC06F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVC06F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC06F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVC06F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVC06F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC06F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVC06F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC06F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVC06F_DMA_ENDSEG_OPCODE 31:29 +#define NVC06F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVC06F_DMA_ADDRESS 12:2 +#define NVC06F_DMA_SUBCH 15:13 +#define NVC06F_DMA_OPCODE3 17:16 +#define NVC06F_DMA_OPCODE3_NONE (0x00000000) +#define NVC06F_DMA_COUNT 28:18 +#define NVC06F_DMA_OPCODE 31:29 +#define NVC06F_DMA_OPCODE_METHOD (0x00000000) +#define NVC06F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVC06F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc06f_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc06fsw.h b/userspace/sdks/nv525/nvidia/inc/class/clc06fsw.h new file mode 100644 index 0000000..4e000c6 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc06fsw.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* This file is *not* auto-generated. */ + +#ifndef _clc06f_sw_h_ +#define _clc06f_sw_h_ + +#define NVC06F_NOTIFIERS_RC (0) +#define NVC06F_NOTIFIERS_REFCNT (1) +#define NVC06F_NOTIFIERS_NONSTALL (2) +#define NVC06F_NOTIFIERS_EVENTBUFFER (3) +#define NVC06F_NOTIFIERS_IDLECHANNEL (4) +#define NVC06F_NOTIFIERS_ENDCTX (5) +#define NVC06F_NOTIFIERS_SW (6) +#define NVC06F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVC06F_NOTIFIERS_REPLAYABLE_FAULT (8) +#define NVC06F_NOTIFIERS_MAXCOUNT (9) + +/* NvNotification[] fields and values */ +#define NVC06F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVC06F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _clc06f_sw_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc076.h b/userspace/sdks/nv525/nvidia/inc/class/clc076.h new file mode 100644 index 0000000..284c57a --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc076.h @@ -0,0 +1,82 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc076_h_ +#define _clc076_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define GP100_UVM_SW (0x0000c076) + +#define NVC076_SET_OBJECT (0x00000000) +#define NVC076_NO_OPERATION (0x00000100) + +/* Method data fields to support gpu fault cancel. These are pushed in order by UVM */ + +#define NVC076_FAULT_CANCEL_A (0x00000104) +#define NVC076_FAULT_CANCEL_A_INST_APERTURE 1:0 +#define NVC076_FAULT_CANCEL_A_INST_APERTURE_VID_MEM 0x00000000 +#define NVC076_FAULT_CANCEL_A_INST_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC076_FAULT_CANCEL_A_INST_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 + +/* instance pointer is 4k aligned so those bits are reused to store the aperture */ +#define NVC076_FAULT_CANCEL_A_INST_LOW 31:12 + +#define NVC076_FAULT_CANCEL_B (0x00000108) +#define NVC076_FAULT_CANCEL_B_INST_HI 31:0 + +#define NVC076_FAULT_CANCEL_C (0x0000010c) +#define NVC076_FAULT_CANCEL_C_CLIENT_ID 5:0 +#define NVC076_FAULT_CANCEL_C_GPC_ID 10:6 +#define NVC076_FAULT_CANCEL_C_MODE 31:30 +#define NVC076_FAULT_CANCEL_C_MODE_TARGETED 0x00000000 +#define NVC076_FAULT_CANCEL_C_MODE_GLOBAL 0x00000001 + +/* Method data fields to support clearing faulted bit. These are pushed in order by UVM */ + +#define NVC076_CLEAR_FAULTED_A (0x00000110) + +#define NVC076_CLEAR_FAULTED_A_INST_APERTURE 1:0 +#define NVC076_CLEAR_FAULTED_A_INST_APERTURE_VID_MEM 0x00000000 +#define NVC076_CLEAR_FAULTED_A_INST_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC076_CLEAR_FAULTED_A_INST_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 + +#define NVC076_CLEAR_FAULTED_A_TYPE 2:2 +#define NVC076_CLEAR_FAULTED_A_TYPE_PBDMA_FAULTED 0x00000000 +#define NVC076_CLEAR_FAULTED_A_TYPE_ENG_FAULTED 0x00000001 + +/* instance pointer is 4k aligned */ +#define NVC076_CLEAR_FAULTED_A_INST_LOW 31:12 + +#define NVC076_CLEAR_FAULTED_B (0x00000114) +#define NVC076_CLEAR_FAULTED_B_INST_HI 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc076_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc097.h b/userspace/sdks/nv525/nvidia/inc/class/clc097.h new file mode 100644 index 0000000..129056b --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc097.h @@ -0,0 +1,4191 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_pascal_a_h_ +#define _cl_pascal_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl pascal_a */ + +#include "nvtypes.h" + +#define PASCAL_A 0xC097 + +#define NVC097_SET_OBJECT 0x0000 +#define NVC097_SET_OBJECT_CLASS_ID 15:0 +#define NVC097_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC097_NO_OPERATION 0x0100 +#define NVC097_NO_OPERATION_V 31:0 + +#define NVC097_SET_NOTIFY_A 0x0104 +#define NVC097_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC097_SET_NOTIFY_B 0x0108 +#define NVC097_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC097_NOTIFY 0x010c +#define NVC097_NOTIFY_TYPE 31:0 +#define NVC097_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC097_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC097_WAIT_FOR_IDLE 0x0110 +#define NVC097_WAIT_FOR_IDLE_V 31:0 + +#define NVC097_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC097_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC097_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC097_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC097_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC097_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC097_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC097_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC097_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC097_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC097_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC097_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC097_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC097_SEND_GO_IDLE 0x013c +#define NVC097_SEND_GO_IDLE_V 31:0 + +#define NVC097_PM_TRIGGER 0x0140 +#define NVC097_PM_TRIGGER_V 31:0 + +#define NVC097_PM_TRIGGER_WFI 0x0144 +#define NVC097_PM_TRIGGER_WFI_V 31:0 + +#define NVC097_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC097_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC097_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC097_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC097_LINE_LENGTH_IN 0x0180 +#define NVC097_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC097_LINE_COUNT 0x0184 +#define NVC097_LINE_COUNT_VALUE 31:0 + +#define NVC097_OFFSET_OUT_UPPER 0x0188 +#define NVC097_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC097_OFFSET_OUT 0x018c +#define NVC097_OFFSET_OUT_VALUE 31:0 + +#define NVC097_PITCH_OUT 0x0190 +#define NVC097_PITCH_OUT_VALUE 31:0 + +#define NVC097_SET_DST_BLOCK_SIZE 0x0194 +#define NVC097_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC097_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC097_SET_DST_WIDTH 0x0198 +#define NVC097_SET_DST_WIDTH_V 31:0 + +#define NVC097_SET_DST_HEIGHT 0x019c +#define NVC097_SET_DST_HEIGHT_V 31:0 + +#define NVC097_SET_DST_DEPTH 0x01a0 +#define NVC097_SET_DST_DEPTH_V 31:0 + +#define NVC097_SET_DST_LAYER 0x01a4 +#define NVC097_SET_DST_LAYER_V 31:0 + +#define NVC097_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC097_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC097_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC097_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC097_LAUNCH_DMA 0x01b0 +#define NVC097_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC097_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC097_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC097_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC097_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC097_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC097_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC097_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC097_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC097_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC097_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC097_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC097_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC097_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC097_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC097_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC097_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC097_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC097_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC097_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC097_LOAD_INLINE_DATA 0x01b4 +#define NVC097_LOAD_INLINE_DATA_V 31:0 + +#define NVC097_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC097_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC097_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC097_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC097_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC097_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC097_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC097_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC097_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC097_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC097_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC097_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC097_RUN_DS_NOW 0x0200 +#define NVC097_RUN_DS_NOW_V 31:0 + +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC097_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC097_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC097_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC097_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC097_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC097_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_GS_DM_FIFO 0x0214 +#define NVC097_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC097_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC097_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC097_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC097_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC097_INVALIDATE_SHADER_CACHES 0x021c +#define NVC097_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC097_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC097_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC097_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC097_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC097_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC097_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC097_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC097_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC097_INCREMENT_SYNC_POINT 0x02c8 +#define NVC097_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC097_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC097_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC097_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC097_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC097_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC097_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NVC097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NVC097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 21:0 + +#define NVC097_DECOMPRESS_SURFACE 0x02e0 +#define NVC097_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC097_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC097_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC097_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC097_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC097_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC097_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC097_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC097_SET_ZCULL_SUBREGION 0x02e8 +#define NVC097_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC097_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC097_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC097_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC097_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC097_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC097_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC097_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC097_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC097_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC097_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC097_DRAW_ZERO_INDEX 0x0304 +#define NVC097_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC097_SET_L1_CONFIGURATION 0x0308 +#define NVC097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC097_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC097_SET_SPA_VERSION 0x0310 +#define NVC097_SET_SPA_VERSION_MINOR 7:0 +#define NVC097_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC097_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NVC097_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NVC097_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_SNAP_GRID_LINE 0x0318 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC097_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC097_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC097_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC097_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC097_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC097_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC097_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC097_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC097_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC097_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC097_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC097_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC097_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC097_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC097_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC097_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC097_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC097_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC097_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC097_RESERVED_TG07 0x033c +#define NVC097_RESERVED_TG07_V 0:0 + +#define NVC097_RESERVED_TG08 0x0340 +#define NVC097_RESERVED_TG08_V 0:0 + +#define NVC097_RESERVED_TG09 0x0344 +#define NVC097_RESERVED_TG09_V 0:0 + +#define NVC097_RESERVED_TG10 0x0348 +#define NVC097_RESERVED_TG10_V 0:0 + +#define NVC097_RESERVED_TG11 0x034c +#define NVC097_RESERVED_TG11_V 0:0 + +#define NVC097_RESERVED_TG12 0x0350 +#define NVC097_RESERVED_TG12_V 0:0 + +#define NVC097_RESERVED_TG13 0x0354 +#define NVC097_RESERVED_TG13_V 0:0 + +#define NVC097_RESERVED_TG14 0x0358 +#define NVC097_RESERVED_TG14_V 0:0 + +#define NVC097_RESERVED_TG15 0x035c +#define NVC097_RESERVED_TG15_V 0:0 + +#define NVC097_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC097_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC097_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC097_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC097_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC097_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC097_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC097_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC097_SET_RASTER_ENABLE 0x037c +#define NVC097_SET_RASTER_ENABLE_V 0:0 +#define NVC097_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC097_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC097_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC097_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC097_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC097_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC097_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC097_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC097_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC097_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC097_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC097_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC097_SET_RASTER_INPUT 0x0740 +#define NVC097_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC097_SET_STREAM_OUTPUT 0x0744 +#define NVC097_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC097_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_ALPHA_FRACTION 0x074c +#define NVC097_SET_ALPHA_FRACTION_V 7:0 + +#define NVC097_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC097_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC097_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC097_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC097_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC097_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC097_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC097_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC097_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC097_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC097_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC097_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC097_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC097_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC097_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC097_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC097_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC097_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC097_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC097_SET_ISBE_SAVE_RESTORE_PROGRAM 0x07ac +#define NVC097_SET_ISBE_SAVE_RESTORE_PROGRAM_OFFSET 31:0 + +#define NVC097_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC097_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC097_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC097_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC097_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC097_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC097_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC097_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC097_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC097_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC097_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC097_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC097_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC097_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC097_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC097_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC097_SET_ZCULL_STORAGE_B 0x07ec +#define NVC097_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC097_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC097_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC097_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC097_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC097_SET_ZT_READ_ONLY 0x07f8 +#define NVC097_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC097_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC097_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC097_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC097_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC097_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC097_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC097_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC097_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC097_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC097_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC097_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC097_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC097_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC097_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC097_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC097_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC097_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC097_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC097_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC097_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC097_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC097_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC097_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC097_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC097_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC097_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC097_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC097_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC097_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC097_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC097_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC097_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NVC097_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NVC097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVC097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVC097_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC097_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC097_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC097_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC097_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC097_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC097_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC097_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC097_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC097_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC097_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC097_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC097_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC097_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC097_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC097_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC097_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC097_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC097_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC097_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC097_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC097_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC097_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC097_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC097_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC097_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC097_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC097_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC097_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC097_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC097_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC097_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC097_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC097_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC097_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC097_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC097_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC097_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC097_SET_STATISTICS_COUNTER 0x0d68 +#define NVC097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC097_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC097_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC097_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC097_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC097_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC097_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC097_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC097_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC097_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC097_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC097_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC097_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC097_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC097_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC097_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC097_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC097_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC097_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC097_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC097_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC097_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC097_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC097_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC097_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC097_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC097_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC097_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC097_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC097_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC097_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC097_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC097_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC097_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC097_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC097_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC097_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC097_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC097_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC097_SET_POLY_SMOOTH 0x0db4 +#define NVC097_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC097_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_ZT_MARK 0x0db8 +#define NVC097_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NVC097_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVC097_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVC097_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC097_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC097_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC097_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC097_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC097_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC097_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC097_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC097_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_PATCH 0x0dcc +#define NVC097_SET_PATCH_SIZE 7:0 + +#define NVC097_SET_ITERATED_BLEND 0x0dd0 +#define NVC097_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC097_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC097_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC097_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC097_SET_ZCULL_CRITERION 0x0dd8 +#define NVC097_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC097_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC097_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC097_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC097_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC097_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC097_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC097_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC097_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC097_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC097_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC097_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC097_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC097_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC097_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC097_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC097_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC097_SET_SCISSOR_ENABLE_V 0:0 +#define NVC097_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC097_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC097_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC097_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC097_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC097_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC097_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0f10 +#define NVC097_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVC097_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVC097_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVC097_SET_VPC_PERF_KNOB 0x0f14 +#define NVC097_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC097_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC097_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC097_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC097_PM_LOCAL_TRIGGER 0x0f18 +#define NVC097_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC097_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC097_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC097_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC097_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC097_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC097_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC097_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC097_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC097_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC097_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC097_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC097_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC097_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC097_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC097_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC097_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC097_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC097_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC097_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC097_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC097_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC097_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC097_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC097_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC097_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC097_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC097_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC097_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC097_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC097_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC097_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC097_SET_SAMPLE_MASK 0x0fa4 +#define NVC097_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC097_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC097_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC097_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC097_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC097_SET_CT_MRT_ENABLE 0x0fac +#define NVC097_SET_CT_MRT_ENABLE_V 0:0 +#define NVC097_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC097_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC097_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC097_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC097_SET_TIR 0x0fb4 +#define NVC097_SET_TIR_MODE 1:0 +#define NVC097_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC097_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC097_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC097_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC097_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC097_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC097_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC097_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC097_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC097_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC097_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC097_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC097_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC097_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC097_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC097_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC097_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC097_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC097_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC097_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_TIR_MODULATION 0x0fd4 +#define NVC097_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC097_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC097_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC097_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC097_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC097_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC097_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC097_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC097_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC097_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC097_SET_ZT_A 0x0fe0 +#define NVC097_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_ZT_B 0x0fe4 +#define NVC097_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_ZT_FORMAT 0x0fe8 +#define NVC097_SET_ZT_FORMAT_V 4:0 +#define NVC097_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC097_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC097_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC097_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC097_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC097_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC097_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC097_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC097_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC097_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC097_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC097_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC097_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC097_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC097_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC097_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC097_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC097_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC097_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC097_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC097_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC097_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC097_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC097_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC097_SET_TILED_CACHE_BUNDLE_CONTROL 0x0ffc +#define NVC097_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT 0:0 +#define NVC097_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_FALSE 0x00000000 +#define NVC097_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_TRUE 0x00000001 + +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC097_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC097_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC097_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC097_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC097_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC097_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC097_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC097_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC097_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC097_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC097_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC097_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC097_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD02 0x102c +#define NVC097_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC097_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC097_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC097_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC097_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC097_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC097_SET_SPARE_NOOP01 0x1044 +#define NVC097_SET_SPARE_NOOP01_V 31:0 + +#define NVC097_SET_SPARE_NOOP02 0x1048 +#define NVC097_SET_SPARE_NOOP02_V 31:0 + +#define NVC097_SET_SPARE_NOOP03 0x104c +#define NVC097_SET_SPARE_NOOP03_V 31:0 + +#define NVC097_SET_SPARE_NOOP04 0x1050 +#define NVC097_SET_SPARE_NOOP04_V 31:0 + +#define NVC097_SET_SPARE_NOOP05 0x1054 +#define NVC097_SET_SPARE_NOOP05_V 31:0 + +#define NVC097_SET_SPARE_NOOP06 0x1058 +#define NVC097_SET_SPARE_NOOP06_V 31:0 + +#define NVC097_SET_SPARE_NOOP07 0x105c +#define NVC097_SET_SPARE_NOOP07_V 31:0 + +#define NVC097_SET_SPARE_NOOP08 0x1060 +#define NVC097_SET_SPARE_NOOP08_V 31:0 + +#define NVC097_SET_SPARE_NOOP09 0x1064 +#define NVC097_SET_SPARE_NOOP09_V 31:0 + +#define NVC097_SET_SPARE_NOOP10 0x1068 +#define NVC097_SET_SPARE_NOOP10_V 31:0 + +#define NVC097_SET_SPARE_NOOP11 0x106c +#define NVC097_SET_SPARE_NOOP11_V 31:0 + +#define NVC097_SET_SPARE_NOOP12 0x1070 +#define NVC097_SET_SPARE_NOOP12_V 31:0 + +#define NVC097_SET_SPARE_NOOP13 0x1074 +#define NVC097_SET_SPARE_NOOP13_V 31:0 + +#define NVC097_SET_SPARE_NOOP14 0x1078 +#define NVC097_SET_SPARE_NOOP14_V 31:0 + +#define NVC097_SET_SPARE_NOOP15 0x107c +#define NVC097_SET_SPARE_NOOP15_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC097_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC097_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC097_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC097_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC097_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC097_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC097_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC097_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC097_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC097_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC097_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC097_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC097_UNBIND_ALL 0x10f4 +#define NVC097_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC097_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC097_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC097_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC097_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC097_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC097_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC097_NO_OPERATION_DATA_HI 0x110c +#define NVC097_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC097_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC097_PM_TRIGGER_END 0x1114 +#define NVC097_PM_TRIGGER_END_V 31:0 + +#define NVC097_SET_VERTEX_ID_BASE 0x1118 +#define NVC097_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC097_SET_STENCIL_COMPRESSION 0x111c +#define NVC097_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC097_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC097_SET_TIR_CONTROL 0x1130 +#define NVC097_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC097_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC097_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC097_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC097_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC097_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC097_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC097_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC097_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 + +#define NVC097_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC097_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC097_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC097_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC097_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC097_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC097_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC097_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC097_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC097_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC097_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC097_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC097_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC097_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC097_FLUSH_PENDING_WRITES 0x1144 +#define NVC097_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC097_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC097_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC097_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC097_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC097_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC097_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC097_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC097_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC097_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC097_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC097_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC097_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC097_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC097_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC097_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC097_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC097_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC097_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC097_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC097_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC097_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC097_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_SCREEN_STATE_MASK 0x1204 +#define NVC097_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC097_SET_ZT_SPARSE 0x1208 +#define NVC097_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC097_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC097_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC097_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC097_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC097_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_SET_CT_SELECT 0x121c +#define NVC097_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC097_SET_CT_SELECT_TARGET0 6:4 +#define NVC097_SET_CT_SELECT_TARGET1 9:7 +#define NVC097_SET_CT_SELECT_TARGET2 12:10 +#define NVC097_SET_CT_SELECT_TARGET3 15:13 +#define NVC097_SET_CT_SELECT_TARGET4 18:16 +#define NVC097_SET_CT_SELECT_TARGET5 21:19 +#define NVC097_SET_CT_SELECT_TARGET6 24:22 +#define NVC097_SET_CT_SELECT_TARGET7 27:25 + +#define NVC097_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC097_SET_ZT_SIZE_A 0x1228 +#define NVC097_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC097_SET_ZT_SIZE_B 0x122c +#define NVC097_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC097_SET_ZT_SIZE_C 0x1230 +#define NVC097_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC097_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC097_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC097_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC097_SET_SAMPLER_BINDING 0x1234 +#define NVC097_SET_SAMPLER_BINDING_V 0:0 +#define NVC097_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC097_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC097_DRAW_AUTO 0x123c +#define NVC097_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC097_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC097_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC097_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC097_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC097_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC097_SET_BACK_END_COPY_A 0x1264 +#define NVC097_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC097_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC097_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC097_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC097_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BACK_END_COPY_B 0x1268 +#define NVC097_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC097_SET_BACK_END_COPY_C 0x126c +#define NVC097_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC097_SET_BACK_END_COPY_D 0x1270 +#define NVC097_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC097_SET_BACK_END_COPY_E 0x1274 +#define NVC097_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC097_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC097_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 21:0 + +#define NVC097_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC097_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC097_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC097_CLEAR_ZCULL_REGION 0x12c8 +#define NVC097_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC097_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC097_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC097_SET_DEPTH_TEST 0x12cc +#define NVC097_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC097_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC097_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_FILL_MODE 0x12d0 +#define NVC097_SET_FILL_MODE_V 31:0 +#define NVC097_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC097_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC097_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC097_SET_SHADE_MODE 0x12d4 +#define NVC097_SET_SHADE_MODE_V 31:0 +#define NVC097_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC097_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC097_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC097_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC097_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC097_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC097_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_DEPTH_WRITE 0x12e8 +#define NVC097_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC097_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_ALPHA_TEST 0x12ec +#define NVC097_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC097_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC097_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC097_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC097_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC097_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC097_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC097_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC097_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC097_D3D_SET_CULL_MODE 0x1308 +#define NVC097_D3D_SET_CULL_MODE_V 31:0 +#define NVC097_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC097_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC097_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC097_SET_DEPTH_FUNC 0x130c +#define NVC097_SET_DEPTH_FUNC_V 31:0 +#define NVC097_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC097_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC097_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC097_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC097_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC097_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC097_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC097_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC097_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC097_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC097_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC097_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC097_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC097_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC097_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC097_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC097_SET_ALPHA_REF 0x1310 +#define NVC097_SET_ALPHA_REF_V 31:0 + +#define NVC097_SET_ALPHA_FUNC 0x1314 +#define NVC097_SET_ALPHA_FUNC_V 31:0 +#define NVC097_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC097_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC097_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC097_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC097_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC097_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC097_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC097_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC097_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC097_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC097_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC097_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC097_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC097_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC097_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC097_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC097_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC097_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC097_SET_BLEND_CONST_RED 0x131c +#define NVC097_SET_BLEND_CONST_RED_V 31:0 + +#define NVC097_SET_BLEND_CONST_GREEN 0x1320 +#define NVC097_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC097_SET_BLEND_CONST_BLUE 0x1324 +#define NVC097_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC097_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC097_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC097_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC097_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC097_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC097_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC097_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC097_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BLEND_COLOR_OP 0x1340 +#define NVC097_SET_BLEND_COLOR_OP_V 31:0 +#define NVC097_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC097_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC097_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC097_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC097_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC097_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC097_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC097_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC097_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC097_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_BLEND_ALPHA_OP 0x134c +#define NVC097_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC097_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC097_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC097_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC097_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC097_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC097_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC097_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC097_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC097_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC097_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC097_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC097_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BLEND(i) (0x1360+(i)*4) +#define NVC097_SET_BLEND_ENABLE 0:0 +#define NVC097_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_STENCIL_TEST 0x1380 +#define NVC097_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC097_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_STENCIL_OP_FAIL 0x1384 +#define NVC097_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC097_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC097_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC097_SET_STENCIL_OP_ZPASS 0x138c +#define NVC097_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC097_SET_STENCIL_FUNC 0x1390 +#define NVC097_SET_STENCIL_FUNC_V 31:0 +#define NVC097_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC097_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC097_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC097_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC097_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC097_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC097_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC097_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC097_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC097_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC097_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC097_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC097_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC097_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC097_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC097_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC097_SET_STENCIL_FUNC_REF 0x1394 +#define NVC097_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC097_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC097_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC097_SET_STENCIL_MASK 0x139c +#define NVC097_SET_STENCIL_MASK_V 7:0 + +#define NVC097_SET_DRAW_AUTO_START 0x13a4 +#define NVC097_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC097_SET_PS_SATURATE 0x13a8 +#define NVC097_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC097_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC097_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC097_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC097_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC097_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC097_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC097_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC097_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC097_SET_WINDOW_ORIGIN 0x13ac +#define NVC097_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC097_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC097_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC097_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC097_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC097_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC097_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC097_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC097_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC097_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC097_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_ALPHA_HYSTERESIS 0x1420 +#define NVC097_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NVC097_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC097_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC097_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC097_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC097_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC097_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC097_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC097_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC097_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC097_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC097_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC097_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC097_STORE_ZCULL 0x1464 +#define NVC097_STORE_ZCULL_V 0:0 + +#define NVC097_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC097_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC097_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC097_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC097_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC097_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC097_LOAD_ZCULL 0x1500 +#define NVC097_LOAD_ZCULL_V 0:0 + +#define NVC097_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC097_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC097_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC097_SET_USER_CLIP_ENABLE 0x1510 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC097_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC097_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC097_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_POINT_SIZE 0x1518 +#define NVC097_SET_POINT_SIZE_V 31:0 + +#define NVC097_SET_ZCULL_STATS 0x151c +#define NVC097_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC097_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_POINT_SPRITE 0x1520 +#define NVC097_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC097_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC097_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC097_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC097_CLEAR_REPORT_VALUE 0x1530 +#define NVC097_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC097_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC097_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC097_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC097_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 + +#define NVC097_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC097_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC097_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_ZT_SELECT 0x1538 +#define NVC097_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC097_SET_RENDER_ENABLE_A 0x1550 +#define NVC097_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_RENDER_ENABLE_B 0x1554 +#define NVC097_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_RENDER_ENABLE_C 0x1558 +#define NVC097_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC097_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC097_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC097_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC097_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC097_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC097_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC097_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC097_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC097_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC097_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC097_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC097_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC097_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC097_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_TEX_HEADER_POOL_C 0x157c +#define NVC097_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC097_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC097_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC097_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC097_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC097_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC097_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC097_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC097_SET_SRGB_WRITE 0x15b8 +#define NVC097_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC097_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_DEPTH_BIAS 0x15bc +#define NVC097_SET_DEPTH_BIAS_V 31:0 + +#define NVC097_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC097_SET_RT_LAYER 0x15cc +#define NVC097_SET_RT_LAYER_V 15:0 +#define NVC097_SET_RT_LAYER_CONTROL 16:16 +#define NVC097_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC097_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC097_SET_ANTI_ALIAS 0x15d0 +#define NVC097_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC097_SET_EDGE_FLAG 0x15e4 +#define NVC097_SET_EDGE_FLAG_V 0:0 +#define NVC097_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC097_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC097_DRAW_INLINE_INDEX 0x15e8 +#define NVC097_DRAW_INLINE_INDEX_V 31:0 + +#define NVC097_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC097_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC097_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC097_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC097_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC097_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC097_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC097_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC097_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC097_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC097_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC097_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC097_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC097_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC097_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC097_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC097_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC097_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC097_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC097_SET_PROGRAM_REGION_A 0x1608 +#define NVC097_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVC097_SET_PROGRAM_REGION_B 0x160c +#define NVC097_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVC097_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC097_END 0x1614 +#define NVC097_END_V 0:0 + +#define NVC097_BEGIN 0x1618 +#define NVC097_BEGIN_OP 15:0 +#define NVC097_BEGIN_OP_POINTS 0x00000000 +#define NVC097_BEGIN_OP_LINES 0x00000001 +#define NVC097_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC097_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC097_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC097_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC097_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC097_BEGIN_OP_QUADS 0x00000007 +#define NVC097_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC097_BEGIN_OP_POLYGON 0x00000009 +#define NVC097_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC097_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC097_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_BEGIN_OP_PATCH 0x0000000E +#define NVC097_BEGIN_PRIMITIVE_ID 24:24 +#define NVC097_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC097_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC097_BEGIN_INSTANCE_ID 27:26 +#define NVC097_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC097_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC097_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC097_BEGIN_SPLIT_MODE 30:29 +#define NVC097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC097_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC097_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 + +#define NVC097_SET_VERTEX_ID_COPY 0x161c +#define NVC097_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC097_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC097_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC097_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC097_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC097_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC097_LOAD_PRIMITIVE_ID 0x1624 +#define NVC097_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC097_SET_SHADER_BASED_CULL 0x162c +#define NVC097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_CLASS_VERSION 0x1638 +#define NVC097_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC097_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC097_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC097_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC097_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC097_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC097_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC097_SET_DA_OUTPUT 0x164c +#define NVC097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC097_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC097_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC097_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_POINT_CENTER_MODE 0x165c +#define NVC097_SET_POINT_CENTER_MODE_V 31:0 +#define NVC097_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC097_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC097_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC097_SET_LINE_STIPPLE 0x166c +#define NVC097_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC097_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC097_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC097_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC097_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC097_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC097_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC097_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC097_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC097_SET_PROVOKING_VERTEX 0x1684 +#define NVC097_SET_PROVOKING_VERTEX_V 0:0 +#define NVC097_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC097_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC097_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC097_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC097_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_POLYGON_STIPPLE 0x168c +#define NVC097_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC097_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_SHADER_CONTROL 0x1690 +#define NVC097_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC097_CHECK_CLASS_VERSION 0x16a0 +#define NVC097_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC097_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC097_SET_SPH_VERSION 0x16a4 +#define NVC097_SET_SPH_VERSION_CURRENT 15:0 +#define NVC097_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC097_CHECK_SPH_VERSION 0x16a8 +#define NVC097_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC097_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC097_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC097_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC097_SET_AAM_VERSION 0x1790 +#define NVC097_SET_AAM_VERSION_CURRENT 15:0 +#define NVC097_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC097_CHECK_AAM_VERSION 0x1794 +#define NVC097_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC097_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC097_SET_ZT_LAYER 0x179c +#define NVC097_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC097_SET_INDEX_BUFFER_A 0x17c8 +#define NVC097_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC097_SET_INDEX_BUFFER_B 0x17cc +#define NVC097_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC097_SET_INDEX_BUFFER_C 0x17d0 +#define NVC097_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC097_SET_INDEX_BUFFER_D 0x17d4 +#define NVC097_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC097_SET_INDEX_BUFFER_E 0x17d8 +#define NVC097_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC097_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC097_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC097_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC097_SET_INDEX_BUFFER_F 0x17dc +#define NVC097_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC097_DRAW_INDEX_BUFFER 0x17e0 +#define NVC097_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC097_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC097_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC097_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC097_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC097_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC097_OGL_SET_CULL 0x1918 +#define NVC097_OGL_SET_CULL_ENABLE 0:0 +#define NVC097_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC097_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC097_OGL_SET_FRONT_FACE 0x191c +#define NVC097_OGL_SET_FRONT_FACE_V 31:0 +#define NVC097_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC097_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC097_OGL_SET_CULL_FACE 0x1920 +#define NVC097_OGL_SET_CULL_FACE_V 31:0 +#define NVC097_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC097_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC097_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC097_SET_VIEWPORT_PIXEL 0x1924 +#define NVC097_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC097_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC097_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC097_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC097_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC097_SET_USER_CLIP_OP 0x1940 +#define NVC097_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC097_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC097_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC097_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC097_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC097_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC097_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC097_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC097_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC097_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC097_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC097_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC097_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC097_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC097_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC097_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC097_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC097_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC097_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC097_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC097_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC097_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC097_INVALIDATE_ZCULL 0x1958 +#define NVC097_INVALIDATE_ZCULL_V 31:0 +#define NVC097_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC097_SET_ZCULL 0x1968 +#define NVC097_SET_ZCULL_Z_ENABLE 0:0 +#define NVC097_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC097_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_ZCULL_BOUNDS 0x196c +#define NVC097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC097_ZCULL_SYNC 0x1978 +#define NVC097_ZCULL_SYNC_V 31:0 + +#define NVC097_SET_CLIP_ID_TEST 0x197c +#define NVC097_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC097_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC097_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC097_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC097_SET_CLIP_ID 0x1984 +#define NVC097_SET_CLIP_ID_V 31:0 + +#define NVC097_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC097_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC097_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC097_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC097_SET_LOGIC_OP 0x19c4 +#define NVC097_SET_LOGIC_OP_ENABLE 0:0 +#define NVC097_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC097_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC097_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC097_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC097_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC097_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC097_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC097_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC097_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC097_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC097_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC097_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC097_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC097_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC097_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC097_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC097_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC097_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC097_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC097_SET_Z_COMPRESSION 0x19cc +#define NVC097_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC097_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC097_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC097_CLEAR_SURFACE 0x19d0 +#define NVC097_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC097_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC097_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC097_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC097_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC097_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC097_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC097_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC097_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC097_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC097_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC097_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC097_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC097_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC097_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC097_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC097_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC097_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC097_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC097_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC097_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC097_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC097_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC097_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC097_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC097_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC097_PIPE_NOP 0x1a2c +#define NVC097_PIPE_NOP_V 31:0 + +#define NVC097_SET_SPARE00 0x1a30 +#define NVC097_SET_SPARE00_V 31:0 + +#define NVC097_SET_SPARE01 0x1a34 +#define NVC097_SET_SPARE01_V 31:0 + +#define NVC097_SET_SPARE02 0x1a38 +#define NVC097_SET_SPARE02_V 31:0 + +#define NVC097_SET_SPARE03 0x1a3c +#define NVC097_SET_SPARE03_V 31:0 + +#define NVC097_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC097_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC097_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC097_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC097_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC097_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC097_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC097_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC097_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC097_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC097_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC097_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC097_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC097_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC097_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC097_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC097_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC097_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC097_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC097_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC097_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC097_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC097_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVC097_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVC097_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVC097_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVC097_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVC097_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVC097_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVC097_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVC097_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC097_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC097_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC097_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC097_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC097_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC097_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC097_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC097_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC097_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC097_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC097_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NVC097_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NVC097_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC097_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC097_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC097_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NVC097_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC097_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC097_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NVC097_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVC097_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NVC097_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NVC097_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVC097_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVC097_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC097_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC097_SET_FALCON00 0x2300 +#define NVC097_SET_FALCON00_V 31:0 + +#define NVC097_SET_FALCON01 0x2304 +#define NVC097_SET_FALCON01_V 31:0 + +#define NVC097_SET_FALCON02 0x2308 +#define NVC097_SET_FALCON02_V 31:0 + +#define NVC097_SET_FALCON03 0x230c +#define NVC097_SET_FALCON03_V 31:0 + +#define NVC097_SET_FALCON04 0x2310 +#define NVC097_SET_FALCON04_V 31:0 + +#define NVC097_SET_FALCON05 0x2314 +#define NVC097_SET_FALCON05_V 31:0 + +#define NVC097_SET_FALCON06 0x2318 +#define NVC097_SET_FALCON06_V 31:0 + +#define NVC097_SET_FALCON07 0x231c +#define NVC097_SET_FALCON07_V 31:0 + +#define NVC097_SET_FALCON08 0x2320 +#define NVC097_SET_FALCON08_V 31:0 + +#define NVC097_SET_FALCON09 0x2324 +#define NVC097_SET_FALCON09_V 31:0 + +#define NVC097_SET_FALCON10 0x2328 +#define NVC097_SET_FALCON10_V 31:0 + +#define NVC097_SET_FALCON11 0x232c +#define NVC097_SET_FALCON11_V 31:0 + +#define NVC097_SET_FALCON12 0x2330 +#define NVC097_SET_FALCON12_V 31:0 + +#define NVC097_SET_FALCON13 0x2334 +#define NVC097_SET_FALCON13_V 31:0 + +#define NVC097_SET_FALCON14 0x2338 +#define NVC097_SET_FALCON14_V 31:0 + +#define NVC097_SET_FALCON15 0x233c +#define NVC097_SET_FALCON15_V 31:0 + +#define NVC097_SET_FALCON16 0x2340 +#define NVC097_SET_FALCON16_V 31:0 + +#define NVC097_SET_FALCON17 0x2344 +#define NVC097_SET_FALCON17_V 31:0 + +#define NVC097_SET_FALCON18 0x2348 +#define NVC097_SET_FALCON18_V 31:0 + +#define NVC097_SET_FALCON19 0x234c +#define NVC097_SET_FALCON19_V 31:0 + +#define NVC097_SET_FALCON20 0x2350 +#define NVC097_SET_FALCON20_V 31:0 + +#define NVC097_SET_FALCON21 0x2354 +#define NVC097_SET_FALCON21_V 31:0 + +#define NVC097_SET_FALCON22 0x2358 +#define NVC097_SET_FALCON22_V 31:0 + +#define NVC097_SET_FALCON23 0x235c +#define NVC097_SET_FALCON23_V 31:0 + +#define NVC097_SET_FALCON24 0x2360 +#define NVC097_SET_FALCON24_V 31:0 + +#define NVC097_SET_FALCON25 0x2364 +#define NVC097_SET_FALCON25_V 31:0 + +#define NVC097_SET_FALCON26 0x2368 +#define NVC097_SET_FALCON26_V 31:0 + +#define NVC097_SET_FALCON27 0x236c +#define NVC097_SET_FALCON27_V 31:0 + +#define NVC097_SET_FALCON28 0x2370 +#define NVC097_SET_FALCON28_V 31:0 + +#define NVC097_SET_FALCON29 0x2374 +#define NVC097_SET_FALCON29_V 31:0 + +#define NVC097_SET_FALCON30 0x2378 +#define NVC097_SET_FALCON30_V 31:0 + +#define NVC097_SET_FALCON31 0x237c +#define NVC097_SET_FALCON31_V 31:0 + +#define NVC097_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC097_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC097_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC097_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC097_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC097_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC097_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC097_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC097_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC097_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC097_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC097_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC097_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC097_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC097_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC097_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC097_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC097_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC097_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC097_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC097_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC097_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC097_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC097_SET_COLOR_CLAMP 0x2600 +#define NVC097_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC097_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC097_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BINDLESS_TEXTURE 0x2608 +#define NVC097_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVC097_SET_TRAP_HANDLER 0x260c +#define NVC097_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVC097_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC097_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC097_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC097_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC097_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC097_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC097_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC097_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC097_CALL_MME_MACRO_V 31:0 + +#define NVC097_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC097_CALL_MME_DATA_V 31:0 + +#endif /* _cl_pascal_a_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc097tex.h b/userspace/sdks/nv525/nvidia/inc/class/clc097tex.h new file mode 100644 index 0000000..7c5a822 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc097tex.h @@ -0,0 +1,1353 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2010 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLC097TEX_H__ +#define __CLC097TEX_H__ + +/* +** Texture Header State Blocklinear + */ + +#define NVC097_TEXHEAD_BL_COMPONENTS MW(6:0) +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R32 0x0000000f +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R16 0x0000001b +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R8 0x0000001d +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R1 0x0000001f +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_EAC 0x00000019 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_Z16 0x0000003a +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVC097_TEXHEAD_BL_R_DATA_TYPE MW(9:7) +#define NVC097_TEXHEAD_BL_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_BL_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_BL_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_BL_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_BL_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_BL_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_BL_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BL_G_DATA_TYPE MW(12:10) +#define NVC097_TEXHEAD_BL_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_BL_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_BL_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_BL_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_BL_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_BL_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_BL_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BL_B_DATA_TYPE MW(15:13) +#define NVC097_TEXHEAD_BL_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_BL_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_BL_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_BL_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_BL_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_BL_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_BL_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BL_A_DATA_TYPE MW(18:16) +#define NVC097_TEXHEAD_BL_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_BL_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_BL_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_BL_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_BL_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_BL_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_BL_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BL_X_SOURCE MW(21:19) +#define NVC097_TEXHEAD_BL_X_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_BL_X_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_BL_X_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_BL_X_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_BL_X_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_BL_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_BL_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BL_Y_SOURCE MW(24:22) +#define NVC097_TEXHEAD_BL_Y_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_BL_Y_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_BL_Y_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_BL_Y_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_BL_Y_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_BL_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_BL_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BL_Z_SOURCE MW(27:25) +#define NVC097_TEXHEAD_BL_Z_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_BL_Z_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_BL_Z_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_BL_Z_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_BL_Z_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_BL_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_BL_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BL_W_SOURCE MW(30:28) +#define NVC097_TEXHEAD_BL_W_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_BL_W_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_BL_W_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_BL_W_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_BL_W_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_BL_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_BL_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BL_PACK_COMPONENTS MW(31:31) +#define NVC097_TEXHEAD_BL_RESERVED1Y MW(36:32) +#define NVC097_TEXHEAD_BL_GOB_DEPTH_OFFSET MW(38:37) +#define NVC097_TEXHEAD_BL_RESERVED1X MW(40:39) +#define NVC097_TEXHEAD_BL_ADDRESS_BITS31TO9 MW(63:41) +#define NVC097_TEXHEAD_BL_ADDRESS_BITS48TO32 MW(80:64) +#define NVC097_TEXHEAD_BL_RESERVED_ADDRESS MW(84:81) +#define NVC097_TEXHEAD_BL_HEADER_VERSION MW(87:85) +#define NVC097_TEXHEAD_BL_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVC097_TEXHEAD_BL_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVC097_TEXHEAD_BL_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVC097_TEXHEAD_BL_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVC097_TEXHEAD_BL_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVC097_TEXHEAD_BL_RESERVED_HEADER_VERSION MW(88:88) +#define NVC097_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVC097_TEXHEAD_BL_RESERVED2A MW(95:93) +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_WIDTH MW(98:96) +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT MW(101:99) +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH MW(104:102) +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC097_TEXHEAD_BL_RESERVED3Y MW(105:105) +#define NVC097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS MW(108:106) +#define NVC097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVC097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVC097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVC097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVC097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVC097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVC097_TEXHEAD_BL_GOB3D MW(109:109) +#define NVC097_TEXHEAD_BL_RESERVED3Z MW(111:110) +#define NVC097_TEXHEAD_BL_LOD_ANISO_QUALITY2 MW(112:112) +#define NVC097_TEXHEAD_BL_LOD_ANISO_QUALITY MW(113:113) +#define NVC097_TEXHEAD_BL_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC097_TEXHEAD_BL_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC097_TEXHEAD_BL_LOD_ISO_QUALITY MW(114:114) +#define NVC097_TEXHEAD_BL_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC097_TEXHEAD_BL_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC097_TEXHEAD_BL_ANISO_SPREAD_SCALE MW(121:117) +#define NVC097_TEXHEAD_BL_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVC097_TEXHEAD_BL_DEPTH_TEXTURE MW(123:123) +#define NVC097_TEXHEAD_BL_MAX_MIP_LEVEL MW(127:124) +#define NVC097_TEXHEAD_BL_WIDTH_MINUS_ONE MW(144:128) +#define NVC097_TEXHEAD_BL_DEPTH_MINUS_ONE_BIT14 MW(145:145) +#define NVC097_TEXHEAD_BL_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVC097_TEXHEAD_BL_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVC097_TEXHEAD_BL_S_R_G_B_CONVERSION MW(150:150) +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE MW(154:151) +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVC097_TEXHEAD_BL_SECTOR_PROMOTION MW(156:155) +#define NVC097_TEXHEAD_BL_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVC097_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVC097_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVC097_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVC097_TEXHEAD_BL_BORDER_SIZE MW(159:157) +#define NVC097_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVC097_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVC097_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVC097_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVC097_TEXHEAD_BL_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVC097_TEXHEAD_BL_HEIGHT_MINUS_ONE MW(175:160) +#define NVC097_TEXHEAD_BL_DEPTH_MINUS_ONE MW(189:176) +#define NVC097_TEXHEAD_BL_RESERVED5A MW(190:190) +#define NVC097_TEXHEAD_BL_NORMALIZED_COORDS MW(191:191) +#define NVC097_TEXHEAD_BL_RESERVED6Y MW(192:192) +#define NVC097_TEXHEAD_BL_TRILIN_OPT MW(197:193) +#define NVC097_TEXHEAD_BL_MIP_LOD_BIAS MW(210:198) +#define NVC097_TEXHEAD_BL_ANISO_BIAS MW(214:211) +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY MW(221:219) +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC097_TEXHEAD_BL_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVC097_TEXHEAD_BL_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT MW(235:232) +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVC097_TEXHEAD_BL_MIN_LOD_CLAMP MW(247:236) +#define NVC097_TEXHEAD_BL_RESERVED7Y MW(255:248) + + +/* +** Texture Header State Blocklinear Color Key + */ + +#define NVC097_TEXHEAD_BLCK_COMPONENTS MW(6:0) +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVC097_TEXHEAD_BLCK_R_DATA_TYPE MW(9:7) +#define NVC097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BLCK_G_DATA_TYPE MW(12:10) +#define NVC097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BLCK_B_DATA_TYPE MW(15:13) +#define NVC097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BLCK_A_DATA_TYPE MW(18:16) +#define NVC097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BLCK_X_SOURCE MW(21:19) +#define NVC097_TEXHEAD_BLCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_BLCK_X_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_BLCK_X_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_BLCK_X_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_BLCK_X_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_BLCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_BLCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BLCK_Y_SOURCE MW(24:22) +#define NVC097_TEXHEAD_BLCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_BLCK_Y_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_BLCK_Y_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_BLCK_Y_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_BLCK_Y_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_BLCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_BLCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BLCK_Z_SOURCE MW(27:25) +#define NVC097_TEXHEAD_BLCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_BLCK_Z_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_BLCK_Z_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_BLCK_Z_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_BLCK_Z_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_BLCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_BLCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BLCK_W_SOURCE MW(30:28) +#define NVC097_TEXHEAD_BLCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_BLCK_W_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_BLCK_W_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_BLCK_W_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_BLCK_W_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_BLCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_BLCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BLCK_PACK_COMPONENTS MW(31:31) +#define NVC097_TEXHEAD_BLCK_RESERVED1Y MW(36:32) +#define NVC097_TEXHEAD_BLCK_GOB_DEPTH_OFFSET MW(38:37) +#define NVC097_TEXHEAD_BLCK_RESERVED1X MW(40:39) +#define NVC097_TEXHEAD_BLCK_ADDRESS_BITS31TO9 MW(63:41) +#define NVC097_TEXHEAD_BLCK_ADDRESS_BITS48TO32 MW(80:64) +#define NVC097_TEXHEAD_BLCK_RESERVED_ADDRESS MW(84:81) +#define NVC097_TEXHEAD_BLCK_HEADER_VERSION MW(87:85) +#define NVC097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVC097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVC097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVC097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVC097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVC097_TEXHEAD_BLCK_RESERVED_HEADER_VERSION MW(88:88) +#define NVC097_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVC097_TEXHEAD_BLCK_RESERVED2A MW(95:93) +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_WIDTH MW(98:96) +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT MW(101:99) +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH MW(104:102) +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC097_TEXHEAD_BLCK_RESERVED3Y MW(105:105) +#define NVC097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS MW(108:106) +#define NVC097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVC097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVC097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVC097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVC097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVC097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVC097_TEXHEAD_BLCK_GOB3D MW(109:109) +#define NVC097_TEXHEAD_BLCK_RESERVED3Z MW(111:110) +#define NVC097_TEXHEAD_BLCK_LOD_ANISO_QUALITY2 MW(112:112) +#define NVC097_TEXHEAD_BLCK_LOD_ANISO_QUALITY MW(113:113) +#define NVC097_TEXHEAD_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC097_TEXHEAD_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC097_TEXHEAD_BLCK_LOD_ISO_QUALITY MW(114:114) +#define NVC097_TEXHEAD_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC097_TEXHEAD_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC097_TEXHEAD_BLCK_ANISO_SPREAD_SCALE MW(121:117) +#define NVC097_TEXHEAD_BLCK_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVC097_TEXHEAD_BLCK_DEPTH_TEXTURE MW(123:123) +#define NVC097_TEXHEAD_BLCK_MAX_MIP_LEVEL MW(127:124) +#define NVC097_TEXHEAD_BLCK_WIDTH_MINUS_ONE MW(144:128) +#define NVC097_TEXHEAD_BLCK_DEPTH_MINUS_ONE_BIT14 MW(145:145) +#define NVC097_TEXHEAD_BLCK_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVC097_TEXHEAD_BLCK_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVC097_TEXHEAD_BLCK_S_R_G_B_CONVERSION MW(150:150) +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE MW(154:151) +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVC097_TEXHEAD_BLCK_SECTOR_PROMOTION MW(156:155) +#define NVC097_TEXHEAD_BLCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVC097_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVC097_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVC097_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVC097_TEXHEAD_BLCK_BORDER_SIZE MW(159:157) +#define NVC097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVC097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVC097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVC097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVC097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVC097_TEXHEAD_BLCK_HEIGHT_MINUS_ONE MW(175:160) +#define NVC097_TEXHEAD_BLCK_DEPTH_MINUS_ONE MW(189:176) +#define NVC097_TEXHEAD_BLCK_RESERVED5A MW(190:190) +#define NVC097_TEXHEAD_BLCK_NORMALIZED_COORDS MW(191:191) +#define NVC097_TEXHEAD_BLCK_COLOR_KEY_OP MW(192:192) +#define NVC097_TEXHEAD_BLCK_TRILIN_OPT MW(197:193) +#define NVC097_TEXHEAD_BLCK_MIP_LOD_BIAS MW(210:198) +#define NVC097_TEXHEAD_BLCK_ANISO_BIAS MW(214:211) +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY MW(221:219) +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC097_TEXHEAD_BLCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Header State One-D Buffer + */ + +#define NVC097_TEXHEAD_1D_COMPONENTS MW(6:0) +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R32 0x0000000f +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R16 0x0000001b +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R8 0x0000001d +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R1 0x0000001f +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_EAC 0x00000019 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_Z16 0x0000003a +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVC097_TEXHEAD_1D_R_DATA_TYPE MW(9:7) +#define NVC097_TEXHEAD_1D_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_1D_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_1D_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_1D_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_1D_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_1D_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_1D_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_1D_G_DATA_TYPE MW(12:10) +#define NVC097_TEXHEAD_1D_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_1D_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_1D_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_1D_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_1D_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_1D_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_1D_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_1D_B_DATA_TYPE MW(15:13) +#define NVC097_TEXHEAD_1D_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_1D_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_1D_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_1D_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_1D_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_1D_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_1D_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_1D_A_DATA_TYPE MW(18:16) +#define NVC097_TEXHEAD_1D_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_1D_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_1D_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_1D_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_1D_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_1D_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_1D_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_1D_X_SOURCE MW(21:19) +#define NVC097_TEXHEAD_1D_X_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_1D_X_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_1D_X_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_1D_X_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_1D_X_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_1D_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_1D_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_1D_Y_SOURCE MW(24:22) +#define NVC097_TEXHEAD_1D_Y_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_1D_Y_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_1D_Y_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_1D_Y_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_1D_Y_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_1D_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_1D_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_1D_Z_SOURCE MW(27:25) +#define NVC097_TEXHEAD_1D_Z_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_1D_Z_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_1D_Z_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_1D_Z_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_1D_Z_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_1D_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_1D_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_1D_W_SOURCE MW(30:28) +#define NVC097_TEXHEAD_1D_W_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_1D_W_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_1D_W_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_1D_W_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_1D_W_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_1D_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_1D_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_1D_PACK_COMPONENTS MW(31:31) +#define NVC097_TEXHEAD_1D_ADDRESS_BITS31TO0 MW(63:32) +#define NVC097_TEXHEAD_1D_ADDRESS_BITS48TO32 MW(80:64) +#define NVC097_TEXHEAD_1D_RESERVED_ADDRESS MW(84:81) +#define NVC097_TEXHEAD_1D_HEADER_VERSION MW(87:85) +#define NVC097_TEXHEAD_1D_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVC097_TEXHEAD_1D_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVC097_TEXHEAD_1D_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVC097_TEXHEAD_1D_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVC097_TEXHEAD_1D_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVC097_TEXHEAD_1D_RESERVED_HEADER_VERSION MW(88:88) +#define NVC097_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVC097_TEXHEAD_1D_RESERVED2A MW(95:93) +#define NVC097_TEXHEAD_1D_WIDTH_MINUS_ONE_BITS31TO16 MW(111:96) +#define NVC097_TEXHEAD_1D_RESERVED3X MW(127:112) +#define NVC097_TEXHEAD_1D_WIDTH_MINUS_ONE_BITS15TO0 MW(143:128) +#define NVC097_TEXHEAD_1D_RESERVED4X MW(149:144) +#define NVC097_TEXHEAD_1D_S_R_G_B_CONVERSION MW(150:150) +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE MW(154:151) +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVC097_TEXHEAD_1D_SECTOR_PROMOTION MW(156:155) +#define NVC097_TEXHEAD_1D_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVC097_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVC097_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVC097_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVC097_TEXHEAD_1D_RESERVED4Y MW(159:157) +#define NVC097_TEXHEAD_1D_RESERVED5X MW(189:160) +#define NVC097_TEXHEAD_1D_RESERVED5A MW(190:190) +#define NVC097_TEXHEAD_1D_RESERVED5Y MW(191:191) +#define NVC097_TEXHEAD_1D_RESERVED6X MW(223:192) +#define NVC097_TEXHEAD_1D_RESERVED7X MW(255:224) + + +/* +** Texture Header State Pitch + */ + +#define NVC097_TEXHEAD_PITCH_COMPONENTS MW(6:0) +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32 0x0000000f +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R16 0x0000001b +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R8 0x0000001d +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R1 0x0000001f +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_EAC 0x00000019 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_Z16 0x0000003a +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVC097_TEXHEAD_PITCH_R_DATA_TYPE MW(9:7) +#define NVC097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCH_G_DATA_TYPE MW(12:10) +#define NVC097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCH_B_DATA_TYPE MW(15:13) +#define NVC097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCH_A_DATA_TYPE MW(18:16) +#define NVC097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCH_X_SOURCE MW(21:19) +#define NVC097_TEXHEAD_PITCH_X_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_PITCH_X_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_PITCH_X_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_PITCH_X_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_PITCH_X_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_PITCH_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_PITCH_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCH_Y_SOURCE MW(24:22) +#define NVC097_TEXHEAD_PITCH_Y_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_PITCH_Y_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_PITCH_Y_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_PITCH_Y_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_PITCH_Y_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_PITCH_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_PITCH_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCH_Z_SOURCE MW(27:25) +#define NVC097_TEXHEAD_PITCH_Z_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_PITCH_Z_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_PITCH_Z_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_PITCH_Z_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_PITCH_Z_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_PITCH_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_PITCH_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCH_W_SOURCE MW(30:28) +#define NVC097_TEXHEAD_PITCH_W_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_PITCH_W_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_PITCH_W_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_PITCH_W_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_PITCH_W_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_PITCH_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_PITCH_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCH_PACK_COMPONENTS MW(31:31) +#define NVC097_TEXHEAD_PITCH_RESERVED1A MW(36:32) +#define NVC097_TEXHEAD_PITCH_ADDRESS_BITS31TO5 MW(63:37) +#define NVC097_TEXHEAD_PITCH_ADDRESS_BITS48TO32 MW(80:64) +#define NVC097_TEXHEAD_PITCH_RESERVED_ADDRESS MW(84:81) +#define NVC097_TEXHEAD_PITCH_HEADER_VERSION MW(87:85) +#define NVC097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVC097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVC097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVC097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVC097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVC097_TEXHEAD_PITCH_RESERVED_HEADER_VERSION MW(88:88) +#define NVC097_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVC097_TEXHEAD_PITCH_RESERVED2A MW(95:93) +#define NVC097_TEXHEAD_PITCH_PITCH_BITS20TO5 MW(111:96) +#define NVC097_TEXHEAD_PITCH_LOD_ANISO_QUALITY2 MW(112:112) +#define NVC097_TEXHEAD_PITCH_LOD_ANISO_QUALITY MW(113:113) +#define NVC097_TEXHEAD_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC097_TEXHEAD_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC097_TEXHEAD_PITCH_LOD_ISO_QUALITY MW(114:114) +#define NVC097_TEXHEAD_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC097_TEXHEAD_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC097_TEXHEAD_PITCH_ANISO_SPREAD_SCALE MW(121:117) +#define NVC097_TEXHEAD_PITCH_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVC097_TEXHEAD_PITCH_DEPTH_TEXTURE MW(123:123) +#define NVC097_TEXHEAD_PITCH_MAX_MIP_LEVEL MW(127:124) +#define NVC097_TEXHEAD_PITCH_WIDTH_MINUS_ONE MW(144:128) +#define NVC097_TEXHEAD_PITCH_PITCH_BIT21 MW(145:145) +#define NVC097_TEXHEAD_PITCH_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVC097_TEXHEAD_PITCH_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVC097_TEXHEAD_PITCH_S_R_G_B_CONVERSION MW(150:150) +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE MW(154:151) +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVC097_TEXHEAD_PITCH_SECTOR_PROMOTION MW(156:155) +#define NVC097_TEXHEAD_PITCH_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVC097_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVC097_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVC097_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVC097_TEXHEAD_PITCH_BORDER_SIZE MW(159:157) +#define NVC097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVC097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVC097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVC097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVC097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVC097_TEXHEAD_PITCH_HEIGHT_MINUS_ONE MW(175:160) +#define NVC097_TEXHEAD_PITCH_DEPTH_MINUS_ONE MW(189:176) +#define NVC097_TEXHEAD_PITCH_RESERVED5A MW(190:190) +#define NVC097_TEXHEAD_PITCH_NORMALIZED_COORDS MW(191:191) +#define NVC097_TEXHEAD_PITCH_RESERVED6Y MW(192:192) +#define NVC097_TEXHEAD_PITCH_TRILIN_OPT MW(197:193) +#define NVC097_TEXHEAD_PITCH_MIP_LOD_BIAS MW(210:198) +#define NVC097_TEXHEAD_PITCH_ANISO_BIAS MW(214:211) +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY MW(221:219) +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC097_TEXHEAD_PITCH_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVC097_TEXHEAD_PITCH_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT MW(235:232) +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVC097_TEXHEAD_PITCH_MIN_LOD_CLAMP MW(247:236) +#define NVC097_TEXHEAD_PITCH_RESERVED7Y MW(255:248) + + +/* +** Texture Header State Pitch Color Key + */ + +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS MW(6:0) +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVC097_TEXHEAD_PITCHCK_R_DATA_TYPE MW(9:7) +#define NVC097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_G_DATA_TYPE MW(12:10) +#define NVC097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_B_DATA_TYPE MW(15:13) +#define NVC097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_A_DATA_TYPE MW(18:16) +#define NVC097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_X_SOURCE MW(21:19) +#define NVC097_TEXHEAD_PITCHCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_X_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_X_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_X_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_X_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_Y_SOURCE MW(24:22) +#define NVC097_TEXHEAD_PITCHCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_Y_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_Y_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_Y_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_Y_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_Z_SOURCE MW(27:25) +#define NVC097_TEXHEAD_PITCHCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_Z_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_Z_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_Z_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_Z_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_W_SOURCE MW(30:28) +#define NVC097_TEXHEAD_PITCHCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_W_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_W_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_W_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_W_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_PACK_COMPONENTS MW(31:31) +#define NVC097_TEXHEAD_PITCHCK_RESERVED1A MW(36:32) +#define NVC097_TEXHEAD_PITCHCK_ADDRESS_BITS31TO5 MW(63:37) +#define NVC097_TEXHEAD_PITCHCK_ADDRESS_BITS48TO32 MW(80:64) +#define NVC097_TEXHEAD_PITCHCK_RESERVED_ADDRESS MW(84:81) +#define NVC097_TEXHEAD_PITCHCK_HEADER_VERSION MW(87:85) +#define NVC097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_RESERVED_HEADER_VERSION MW(88:88) +#define NVC097_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVC097_TEXHEAD_PITCHCK_RESERVED2A MW(95:93) +#define NVC097_TEXHEAD_PITCHCK_PITCH_BITS20TO5 MW(111:96) +#define NVC097_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY2 MW(112:112) +#define NVC097_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY MW(113:113) +#define NVC097_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_LOD_ISO_QUALITY MW(114:114) +#define NVC097_TEXHEAD_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_ANISO_SPREAD_SCALE MW(121:117) +#define NVC097_TEXHEAD_PITCHCK_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVC097_TEXHEAD_PITCHCK_DEPTH_TEXTURE MW(123:123) +#define NVC097_TEXHEAD_PITCHCK_MAX_MIP_LEVEL MW(127:124) +#define NVC097_TEXHEAD_PITCHCK_WIDTH_MINUS_ONE MW(144:128) +#define NVC097_TEXHEAD_PITCHCK_PITCH_BIT21 MW(145:145) +#define NVC097_TEXHEAD_PITCHCK_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVC097_TEXHEAD_PITCHCK_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVC097_TEXHEAD_PITCHCK_S_R_G_B_CONVERSION MW(150:150) +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE MW(154:151) +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVC097_TEXHEAD_PITCHCK_SECTOR_PROMOTION MW(156:155) +#define NVC097_TEXHEAD_PITCHCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_BORDER_SIZE MW(159:157) +#define NVC097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_HEIGHT_MINUS_ONE MW(175:160) +#define NVC097_TEXHEAD_PITCHCK_DEPTH_MINUS_ONE MW(189:176) +#define NVC097_TEXHEAD_PITCHCK_RESERVED5A MW(190:190) +#define NVC097_TEXHEAD_PITCHCK_NORMALIZED_COORDS MW(191:191) +#define NVC097_TEXHEAD_PITCHCK_COLOR_KEY_OP MW(192:192) +#define NVC097_TEXHEAD_PITCHCK_TRILIN_OPT MW(197:193) +#define NVC097_TEXHEAD_PITCHCK_MIP_LOD_BIAS MW(210:198) +#define NVC097_TEXHEAD_PITCHCK_ANISO_BIAS MW(214:211) +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY MW(221:219) +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Sampler State + */ + +#define NVC097_TEXSAMP0_ADDRESS_U 2:0 +#define NVC097_TEXSAMP0_ADDRESS_U_WRAP 0x00000000 +#define NVC097_TEXSAMP0_ADDRESS_U_MIRROR 0x00000001 +#define NVC097_TEXSAMP0_ADDRESS_U_CLAMP_TO_EDGE 0x00000002 +#define NVC097_TEXSAMP0_ADDRESS_U_BORDER 0x00000003 +#define NVC097_TEXSAMP0_ADDRESS_U_CLAMP_OGL 0x00000004 +#define NVC097_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVC097_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_BORDER 0x00000006 +#define NVC097_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVC097_TEXSAMP0_ADDRESS_V 5:3 +#define NVC097_TEXSAMP0_ADDRESS_V_WRAP 0x00000000 +#define NVC097_TEXSAMP0_ADDRESS_V_MIRROR 0x00000001 +#define NVC097_TEXSAMP0_ADDRESS_V_CLAMP_TO_EDGE 0x00000002 +#define NVC097_TEXSAMP0_ADDRESS_V_BORDER 0x00000003 +#define NVC097_TEXSAMP0_ADDRESS_V_CLAMP_OGL 0x00000004 +#define NVC097_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVC097_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_BORDER 0x00000006 +#define NVC097_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVC097_TEXSAMP0_ADDRESS_P 8:6 +#define NVC097_TEXSAMP0_ADDRESS_P_WRAP 0x00000000 +#define NVC097_TEXSAMP0_ADDRESS_P_MIRROR 0x00000001 +#define NVC097_TEXSAMP0_ADDRESS_P_CLAMP_TO_EDGE 0x00000002 +#define NVC097_TEXSAMP0_ADDRESS_P_BORDER 0x00000003 +#define NVC097_TEXSAMP0_ADDRESS_P_CLAMP_OGL 0x00000004 +#define NVC097_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVC097_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_BORDER 0x00000006 +#define NVC097_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVC097_TEXSAMP0_DEPTH_COMPARE 9:9 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC 12:10 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_NEVER 0x00000000 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_LESS 0x00000001 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_EQUAL 0x00000002 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_LEQUAL 0x00000003 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_GREATER 0x00000004 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_NOTEQUAL 0x00000005 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_GEQUAL 0x00000006 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_ALWAYS 0x00000007 +#define NVC097_TEXSAMP0_S_R_G_B_CONVERSION 13:13 +#define NVC097_TEXSAMP0_RESERVED0A 16:14 +#define NVC097_TEXSAMP0_RESERVED0B 19:17 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY 22:20 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVC097_TEXSAMP1_MAG_FILTER 2:0 +#define NVC097_TEXSAMP1_MAG_FILTER_MAG_POINT 0x00000001 +#define NVC097_TEXSAMP1_MAG_FILTER_MAG_LINEAR 0x00000002 +#define NVC097_TEXSAMP1_MAG_FILTER_VCAA_4_TAP 0x00000003 +#define NVC097_TEXSAMP1_MAG_FILTER_VCAA_8_TAP 0x00000004 +#define NVC097_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP 3:3 +#define NVC097_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP_INTEGER_AND_FRACTION 0x00000000 +#define NVC097_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP_INTEGER_ONLY 0x00000001 +#define NVC097_TEXSAMP1_MIN_FILTER 5:4 +#define NVC097_TEXSAMP1_MIN_FILTER_MIN_POINT 0x00000001 +#define NVC097_TEXSAMP1_MIN_FILTER_MIN_LINEAR 0x00000002 +#define NVC097_TEXSAMP1_MIN_FILTER_MIN_ANISO 0x00000003 +#define NVC097_TEXSAMP1_MIP_FILTER 7:6 +#define NVC097_TEXSAMP1_MIP_FILTER_MIP_NONE 0x00000001 +#define NVC097_TEXSAMP1_MIP_FILTER_MIP_POINT 0x00000002 +#define NVC097_TEXSAMP1_MIP_FILTER_MIP_LINEAR 0x00000003 +#define NVC097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING 9:8 +#define NVC097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_USE_WRAP 0x00000000 +#define NVC097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_OVERRIDE_WRAP 0x00000001 +#define NVC097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_AUTO_SPAN_SEAM 0x00000002 +#define NVC097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_AUTO_CROSS_SEAM 0x00000003 +#define NVC097_TEXSAMP1_REDUCTION_FILTER 11:10 +#define NVC097_TEXSAMP1_REDUCTION_FILTER_RED_NONE 0x00000000 +#define NVC097_TEXSAMP1_REDUCTION_FILTER_RED_MINIMUM 0x00000001 +#define NVC097_TEXSAMP1_REDUCTION_FILTER_RED_MAXIMUM 0x00000002 +#define NVC097_TEXSAMP1_MIP_LOD_BIAS 24:12 +#define NVC097_TEXSAMP1_FLOAT_COORD_NORMALIZATION 25:25 +#define NVC097_TEXSAMP1_FLOAT_COORD_NORMALIZATION_USE_HEADER_SETTING 0x00000000 +#define NVC097_TEXSAMP1_FLOAT_COORD_NORMALIZATION_FORCE_UNNORMALIZED_COORDS 0x00000001 +#define NVC097_TEXSAMP1_TRILIN_OPT 30:26 +#define NVC097_TEXSAMP2_MIN_LOD_CLAMP 11:0 +#define NVC097_TEXSAMP2_MAX_LOD_CLAMP 23:12 +#define NVC097_TEXSAMP2_S_R_G_B_BORDER_COLOR_R 31:24 +#define NVC097_TEXSAMP3_RESERVED12 11:0 +#define NVC097_TEXSAMP3_S_R_G_B_BORDER_COLOR_G 19:12 +#define NVC097_TEXSAMP3_S_R_G_B_BORDER_COLOR_B 27:20 +#define NVC097_TEXSAMP4_BORDER_COLOR_R 31:0 +#define NVC097_TEXSAMP5_BORDER_COLOR_G 31:0 +#define NVC097_TEXSAMP6_BORDER_COLOR_B 31:0 +#define NVC097_TEXSAMP7_BORDER_COLOR_A 31:0 + + + +#endif // #ifndef __CLC097TEX_H__ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc0b5.h b/userspace/sdks/nv525/nvidia/inc/class/clc0b5.h new file mode 100644 index 0000000..d1fa85a --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc0b5.h @@ -0,0 +1,261 @@ +/******************************************************************************* + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clc0b5_h_ +#define _clc0b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define PASCAL_DMA_COPY_A (0x0000C0B5) + +#define NVC0B5_NOP (0x00000100) +#define NVC0B5_NOP_PARAMETER 31:0 +#define NVC0B5_PM_TRIGGER (0x00000140) +#define NVC0B5_PM_TRIGGER_V 31:0 +#define NVC0B5_SET_SEMAPHORE_A (0x00000240) +#define NVC0B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC0B5_SET_SEMAPHORE_B (0x00000244) +#define NVC0B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC0B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC0B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC0B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC0B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC0B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC0B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC0B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC0B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC0B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC0B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC0B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC0B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC0B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC0B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC0B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC0B5_LAUNCH_DMA (0x00000300) +#define NVC0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC0B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC0B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC0B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC0B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC0B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC0B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC0B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC0B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC0B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC0B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC0B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC0B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC0B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC0B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC0B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC0B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC0B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC0B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC0B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC0B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC0B5_LAUNCH_DMA_SRC_BYPASS_L2 20:20 +#define NVC0B5_LAUNCH_DMA_SRC_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC0B5_LAUNCH_DMA_SRC_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC0B5_LAUNCH_DMA_DST_BYPASS_L2 21:21 +#define NVC0B5_LAUNCH_DMA_DST_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC0B5_LAUNCH_DMA_DST_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC0B5_LAUNCH_DMA_RESERVED 31:28 +#define NVC0B5_OFFSET_IN_UPPER (0x00000400) +#define NVC0B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC0B5_OFFSET_IN_LOWER (0x00000404) +#define NVC0B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC0B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC0B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC0B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC0B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC0B5_PITCH_IN (0x00000410) +#define NVC0B5_PITCH_IN_VALUE 31:0 +#define NVC0B5_PITCH_OUT (0x00000414) +#define NVC0B5_PITCH_OUT_VALUE 31:0 +#define NVC0B5_LINE_LENGTH_IN (0x00000418) +#define NVC0B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC0B5_LINE_COUNT (0x0000041C) +#define NVC0B5_LINE_COUNT_VALUE 31:0 +#define NVC0B5_SET_REMAP_CONST_A (0x00000700) +#define NVC0B5_SET_REMAP_CONST_A_V 31:0 +#define NVC0B5_SET_REMAP_CONST_B (0x00000704) +#define NVC0B5_SET_REMAP_CONST_B_V 31:0 +#define NVC0B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC0B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC0B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC0B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC0B5_SET_DST_WIDTH (0x00000710) +#define NVC0B5_SET_DST_WIDTH_V 31:0 +#define NVC0B5_SET_DST_HEIGHT (0x00000714) +#define NVC0B5_SET_DST_HEIGHT_V 31:0 +#define NVC0B5_SET_DST_DEPTH (0x00000718) +#define NVC0B5_SET_DST_DEPTH_V 31:0 +#define NVC0B5_SET_DST_LAYER (0x0000071C) +#define NVC0B5_SET_DST_LAYER_V 31:0 +#define NVC0B5_SET_DST_ORIGIN (0x00000720) +#define NVC0B5_SET_DST_ORIGIN_X 15:0 +#define NVC0B5_SET_DST_ORIGIN_Y 31:16 +#define NVC0B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC0B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC0B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC0B5_SET_SRC_WIDTH (0x0000072C) +#define NVC0B5_SET_SRC_WIDTH_V 31:0 +#define NVC0B5_SET_SRC_HEIGHT (0x00000730) +#define NVC0B5_SET_SRC_HEIGHT_V 31:0 +#define NVC0B5_SET_SRC_DEPTH (0x00000734) +#define NVC0B5_SET_SRC_DEPTH_V 31:0 +#define NVC0B5_SET_SRC_LAYER (0x00000738) +#define NVC0B5_SET_SRC_LAYER_V 31:0 +#define NVC0B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC0B5_SET_SRC_ORIGIN_X 15:0 +#define NVC0B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC0B5_PM_TRIGGER_END (0x00001114) +#define NVC0B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc0b5_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc0b5sw.h b/userspace/sdks/nv525/nvidia/inc/class/clc0b5sw.h new file mode 100644 index 0000000..dc5bc41 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc0b5sw.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc0b5sw.finn +// + + + +// +// Using VERSION_0 will cause the API to interpret +// engineType as a CE engine instance. This allows +// for backward compatibility with 85B5sw and 90B5sw. +// +#define NVC0B5_ALLOCATION_PARAMETERS_VERSION_0 0 + +// +// Using VERSION_1 will cause the API to interpret +// engineType as an NV2080_ENGINE_TYPE ordinal. +// +#define NVC0B5_ALLOCATION_PARAMETERS_VERSION_1 1 + +#define NVC0B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc0b5U) + +typedef struct NVC0B5_ALLOCATION_PARAMETERS { + NvU32 version; + NvU32 engineType; +} NVC0B5_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc0b7.h b/userspace/sdks/nv525/nvidia/inc/class/clc0b7.h new file mode 100644 index 0000000..bdb9bba --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc0b7.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clc0b7_h +#define clc0b7_h + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC0B7_VIDEO_ENCODER (0x0000C0B7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc0b7_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc0c0.h b/userspace/sdks/nv525/nvidia/inc/class/clc0c0.h new file mode 100644 index 0000000..fde8702 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc0c0.h @@ -0,0 +1,777 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_pascal_compute_a_h_ +#define _cl_pascal_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl pascal_compute_a */ + +#include "nvtypes.h" + +#define PASCAL_COMPUTE_A 0xC0C0 + +#define NVC0C0_SET_OBJECT 0x0000 +#define NVC0C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC0C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC0C0_NO_OPERATION 0x0100 +#define NVC0C0_NO_OPERATION_V 31:0 + +#define NVC0C0_SET_NOTIFY_A 0x0104 +#define NVC0C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC0C0_SET_NOTIFY_B 0x0108 +#define NVC0C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_NOTIFY 0x010c +#define NVC0C0_NOTIFY_TYPE 31:0 +#define NVC0C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC0C0_WAIT_FOR_IDLE 0x0110 +#define NVC0C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC0C0_SEND_GO_IDLE 0x013c +#define NVC0C0_SEND_GO_IDLE_V 31:0 + +#define NVC0C0_PM_TRIGGER 0x0140 +#define NVC0C0_PM_TRIGGER_V 31:0 + +#define NVC0C0_PM_TRIGGER_WFI 0x0144 +#define NVC0C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC0C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC0C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC0C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC0C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC0C0_LINE_LENGTH_IN 0x0180 +#define NVC0C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC0C0_LINE_COUNT 0x0184 +#define NVC0C0_LINE_COUNT_VALUE 31:0 + +#define NVC0C0_OFFSET_OUT_UPPER 0x0188 +#define NVC0C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC0C0_OFFSET_OUT 0x018c +#define NVC0C0_OFFSET_OUT_VALUE 31:0 + +#define NVC0C0_PITCH_OUT 0x0190 +#define NVC0C0_PITCH_OUT_VALUE 31:0 + +#define NVC0C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC0C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC0C0_SET_DST_WIDTH 0x0198 +#define NVC0C0_SET_DST_WIDTH_V 31:0 + +#define NVC0C0_SET_DST_HEIGHT 0x019c +#define NVC0C0_SET_DST_HEIGHT_V 31:0 + +#define NVC0C0_SET_DST_DEPTH 0x01a0 +#define NVC0C0_SET_DST_DEPTH_V 31:0 + +#define NVC0C0_SET_DST_LAYER 0x01a4 +#define NVC0C0_SET_DST_LAYER_V 31:0 + +#define NVC0C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC0C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC0C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC0C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC0C0_LAUNCH_DMA 0x01b0 +#define NVC0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC0C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC0C0_LOAD_INLINE_DATA 0x01b4 +#define NVC0C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC0C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC0C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC0C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC0C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC0C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC0C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC0C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC0C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC0C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC0C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC0C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC0C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVC0C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVC0C0_PERFMON_TRANSFER 0x0210 +#define NVC0C0_PERFMON_TRANSFER_V 31:0 + +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0218 +#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVC0C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC0C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC0C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC0C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC0C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC0C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC0C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC0C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC0C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC0C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC0C0_SET_CWD_CONTROL 0x0240 +#define NVC0C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVC0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVC0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC0C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC0C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC0C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC0C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC0C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC0C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC0C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC0C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC0C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC0C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC0C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC0C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC0C0_SET_GWC_SCG_TYPE 0x026c +#define NVC0C0_SET_GWC_SCG_TYPE_SCG_TYPE 0:0 +#define NVC0C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0 0x00000000 +#define NVC0C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1 0x00000001 + +#define NVC0C0_SET_SCG_CONTROL 0x0270 +#define NVC0C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 + +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 16:0 + +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVC0C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC0C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC0C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC0C0_SET_QMD_VERSION 0x0288 +#define NVC0C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC0C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC0C0_SET_WFI_CONFIG 0x028c +#define NVC0C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI 0:0 +#define NVC0C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE 0x00000000 +#define NVC0C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE 0x00000001 + +#define NVC0C0_CHECK_QMD_VERSION 0x0290 +#define NVC0C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC0C0_WAIT_FOR_IDLE_SCG_TYPE 0x0294 +#define NVC0C0_WAIT_FOR_IDLE_SCG_TYPE_V 31:0 + +#define NVC0C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC0C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL 0x029c +#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE 0:0 +#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE 0x00000001 + +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC0C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC0C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC0C0_SEND_PCAS_A 0x02b4 +#define NVC0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC0C0_SEND_PCAS_B 0x02b8 +#define NVC0C0_SEND_PCAS_B_FROM 23:0 +#define NVC0C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC0C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC0C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC0C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC0C0_SET_SPA_VERSION 0x0310 +#define NVC0C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC0C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC0C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC0C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC0C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC0C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC0C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC0C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC0C0_SET_FALCON00 0x0500 +#define NVC0C0_SET_FALCON00_V 31:0 + +#define NVC0C0_SET_FALCON01 0x0504 +#define NVC0C0_SET_FALCON01_V 31:0 + +#define NVC0C0_SET_FALCON02 0x0508 +#define NVC0C0_SET_FALCON02_V 31:0 + +#define NVC0C0_SET_FALCON03 0x050c +#define NVC0C0_SET_FALCON03_V 31:0 + +#define NVC0C0_SET_FALCON04 0x0510 +#define NVC0C0_SET_FALCON04_V 31:0 + +#define NVC0C0_SET_FALCON05 0x0514 +#define NVC0C0_SET_FALCON05_V 31:0 + +#define NVC0C0_SET_FALCON06 0x0518 +#define NVC0C0_SET_FALCON06_V 31:0 + +#define NVC0C0_SET_FALCON07 0x051c +#define NVC0C0_SET_FALCON07_V 31:0 + +#define NVC0C0_SET_FALCON08 0x0520 +#define NVC0C0_SET_FALCON08_V 31:0 + +#define NVC0C0_SET_FALCON09 0x0524 +#define NVC0C0_SET_FALCON09_V 31:0 + +#define NVC0C0_SET_FALCON10 0x0528 +#define NVC0C0_SET_FALCON10_V 31:0 + +#define NVC0C0_SET_FALCON11 0x052c +#define NVC0C0_SET_FALCON11_V 31:0 + +#define NVC0C0_SET_FALCON12 0x0530 +#define NVC0C0_SET_FALCON12_V 31:0 + +#define NVC0C0_SET_FALCON13 0x0534 +#define NVC0C0_SET_FALCON13_V 31:0 + +#define NVC0C0_SET_FALCON14 0x0538 +#define NVC0C0_SET_FALCON14_V 31:0 + +#define NVC0C0_SET_FALCON15 0x053c +#define NVC0C0_SET_FALCON15_V 31:0 + +#define NVC0C0_SET_FALCON16 0x0540 +#define NVC0C0_SET_FALCON16_V 31:0 + +#define NVC0C0_SET_FALCON17 0x0544 +#define NVC0C0_SET_FALCON17_V 31:0 + +#define NVC0C0_SET_FALCON18 0x0548 +#define NVC0C0_SET_FALCON18_V 31:0 + +#define NVC0C0_SET_FALCON19 0x054c +#define NVC0C0_SET_FALCON19_V 31:0 + +#define NVC0C0_SET_FALCON20 0x0550 +#define NVC0C0_SET_FALCON20_V 31:0 + +#define NVC0C0_SET_FALCON21 0x0554 +#define NVC0C0_SET_FALCON21_V 31:0 + +#define NVC0C0_SET_FALCON22 0x0558 +#define NVC0C0_SET_FALCON22_V 31:0 + +#define NVC0C0_SET_FALCON23 0x055c +#define NVC0C0_SET_FALCON23_V 31:0 + +#define NVC0C0_SET_FALCON24 0x0560 +#define NVC0C0_SET_FALCON24_V 31:0 + +#define NVC0C0_SET_FALCON25 0x0564 +#define NVC0C0_SET_FALCON25_V 31:0 + +#define NVC0C0_SET_FALCON26 0x0568 +#define NVC0C0_SET_FALCON26_V 31:0 + +#define NVC0C0_SET_FALCON27 0x056c +#define NVC0C0_SET_FALCON27_V 31:0 + +#define NVC0C0_SET_FALCON28 0x0570 +#define NVC0C0_SET_FALCON28_V 31:0 + +#define NVC0C0_SET_FALCON29 0x0574 +#define NVC0C0_SET_FALCON29_V 31:0 + +#define NVC0C0_SET_FALCON30 0x0578 +#define NVC0C0_SET_FALCON30_V 31:0 + +#define NVC0C0_SET_FALCON31 0x057c +#define NVC0C0_SET_FALCON31_V 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC0C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC0C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC0C0_SET_SPARE_NOOP12 0x0f44 +#define NVC0C0_SET_SPARE_NOOP12_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP13 0x0f48 +#define NVC0C0_SET_SPARE_NOOP13_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP14 0x0f4c +#define NVC0C0_SET_SPARE_NOOP14_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP15 0x0f50 +#define NVC0C0_SET_SPARE_NOOP15_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP00 0x1040 +#define NVC0C0_SET_SPARE_NOOP00_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP01 0x1044 +#define NVC0C0_SET_SPARE_NOOP01_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP02 0x1048 +#define NVC0C0_SET_SPARE_NOOP02_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP03 0x104c +#define NVC0C0_SET_SPARE_NOOP03_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP04 0x1050 +#define NVC0C0_SET_SPARE_NOOP04_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP05 0x1054 +#define NVC0C0_SET_SPARE_NOOP05_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP06 0x1058 +#define NVC0C0_SET_SPARE_NOOP06_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP07 0x105c +#define NVC0C0_SET_SPARE_NOOP07_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP08 0x1060 +#define NVC0C0_SET_SPARE_NOOP08_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP09 0x1064 +#define NVC0C0_SET_SPARE_NOOP09_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP10 0x1068 +#define NVC0C0_SET_SPARE_NOOP10_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP11 0x106c +#define NVC0C0_SET_SPARE_NOOP11_V 31:0 + +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC0C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC0C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC0C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC0C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC0C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC0C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC0C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC0C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC0C0_SET_PROGRAM_REGION_A 0x1608 +#define NVC0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 16:0 + +#define NVC0C0_SET_PROGRAM_REGION_B 0x160c +#define NVC0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC0C0_PIPE_NOP 0x1a2c +#define NVC0C0_PIPE_NOP_V 31:0 + +#define NVC0C0_SET_SPARE00 0x1a30 +#define NVC0C0_SET_SPARE00_V 31:0 + +#define NVC0C0_SET_SPARE01 0x1a34 +#define NVC0C0_SET_SPARE01_V 31:0 + +#define NVC0C0_SET_SPARE02 0x1a38 +#define NVC0C0_SET_SPARE02_V 31:0 + +#define NVC0C0_SET_SPARE03 0x1a3c +#define NVC0C0_SET_SPARE03_V 31:0 + +#define NVC0C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC0C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC0C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC0C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC0C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC0C0_SET_TRAP_HANDLER 0x260c +#define NVC0C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC0C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC0C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC0C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC0C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC0C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC0C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_pascal_compute_a_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc197.h b/userspace/sdks/nv525/nvidia/inc/class/clc197.h new file mode 100644 index 0000000..b03d735 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc197.h @@ -0,0 +1,4242 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_pascal_b_h_ +#define _cl_pascal_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl pascal_b */ + +#include "nvtypes.h" + +#define PASCAL_B 0xC197 + +#define NVC197_SET_OBJECT 0x0000 +#define NVC197_SET_OBJECT_CLASS_ID 15:0 +#define NVC197_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC197_NO_OPERATION 0x0100 +#define NVC197_NO_OPERATION_V 31:0 + +#define NVC197_SET_NOTIFY_A 0x0104 +#define NVC197_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC197_SET_NOTIFY_B 0x0108 +#define NVC197_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC197_NOTIFY 0x010c +#define NVC197_NOTIFY_TYPE 31:0 +#define NVC197_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC197_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC197_WAIT_FOR_IDLE 0x0110 +#define NVC197_WAIT_FOR_IDLE_V 31:0 + +#define NVC197_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC197_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC197_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC197_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC197_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC197_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC197_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC197_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC197_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC197_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC197_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC197_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC197_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC197_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC197_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC197_SEND_GO_IDLE 0x013c +#define NVC197_SEND_GO_IDLE_V 31:0 + +#define NVC197_PM_TRIGGER 0x0140 +#define NVC197_PM_TRIGGER_V 31:0 + +#define NVC197_PM_TRIGGER_WFI 0x0144 +#define NVC197_PM_TRIGGER_WFI_V 31:0 + +#define NVC197_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC197_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC197_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC197_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC197_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC197_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC197_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC197_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC197_LINE_LENGTH_IN 0x0180 +#define NVC197_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC197_LINE_COUNT 0x0184 +#define NVC197_LINE_COUNT_VALUE 31:0 + +#define NVC197_OFFSET_OUT_UPPER 0x0188 +#define NVC197_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC197_OFFSET_OUT 0x018c +#define NVC197_OFFSET_OUT_VALUE 31:0 + +#define NVC197_PITCH_OUT 0x0190 +#define NVC197_PITCH_OUT_VALUE 31:0 + +#define NVC197_SET_DST_BLOCK_SIZE 0x0194 +#define NVC197_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC197_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC197_SET_DST_WIDTH 0x0198 +#define NVC197_SET_DST_WIDTH_V 31:0 + +#define NVC197_SET_DST_HEIGHT 0x019c +#define NVC197_SET_DST_HEIGHT_V 31:0 + +#define NVC197_SET_DST_DEPTH 0x01a0 +#define NVC197_SET_DST_DEPTH_V 31:0 + +#define NVC197_SET_DST_LAYER 0x01a4 +#define NVC197_SET_DST_LAYER_V 31:0 + +#define NVC197_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC197_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC197_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC197_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC197_LAUNCH_DMA 0x01b0 +#define NVC197_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC197_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC197_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC197_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC197_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC197_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC197_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC197_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC197_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC197_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC197_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC197_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC197_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC197_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC197_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC197_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC197_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC197_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC197_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC197_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC197_LOAD_INLINE_DATA 0x01b4 +#define NVC197_LOAD_INLINE_DATA_V 31:0 + +#define NVC197_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC197_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC197_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC197_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC197_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC197_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC197_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC197_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC197_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC197_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC197_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC197_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC197_RUN_DS_NOW 0x0200 +#define NVC197_RUN_DS_NOW_V 31:0 + +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC197_SET_GS_MODE 0x0208 +#define NVC197_SET_GS_MODE_TYPE 0:0 +#define NVC197_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVC197_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVC197_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC197_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC197_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC197_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC197_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC197_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_GS_DM_FIFO 0x0214 +#define NVC197_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC197_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC197_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC197_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC197_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC197_INVALIDATE_SHADER_CACHES 0x021c +#define NVC197_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC197_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC197_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC197_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC197_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC197_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC197_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC197_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC197_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC197_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC197_SET_INSTANCE_COUNT 0x0220 +#define NVC197_SET_INSTANCE_COUNT_V 31:0 + +#define NVC197_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVC197_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVC197_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC197_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVC197_INCREMENT_SYNC_POINT 0x02c8 +#define NVC197_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC197_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC197_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC197_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC197_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC197_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC197_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC197_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NVC197_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NVC197_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC197_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC197_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC197_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVC197_DECOMPRESS_SURFACE 0x02e0 +#define NVC197_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC197_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC197_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC197_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC197_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC197_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC197_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC197_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC197_SET_ZCULL_SUBREGION 0x02e8 +#define NVC197_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC197_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC197_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC197_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC197_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC197_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC197_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC197_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC197_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC197_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC197_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC197_DRAW_ZERO_INDEX 0x0304 +#define NVC197_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC197_SET_L1_CONFIGURATION 0x0308 +#define NVC197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC197_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC197_SET_SPA_VERSION 0x0310 +#define NVC197_SET_SPA_VERSION_MINOR 7:0 +#define NVC197_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC197_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NVC197_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NVC197_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_SNAP_GRID_LINE 0x0318 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC197_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC197_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC197_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC197_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC197_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC197_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC197_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC197_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC197_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC197_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC197_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC197_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC197_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC197_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC197_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC197_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC197_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC197_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC197_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC197_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC197_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC197_RESERVED_TG07 0x033c +#define NVC197_RESERVED_TG07_V 0:0 + +#define NVC197_RESERVED_TG08 0x0340 +#define NVC197_RESERVED_TG08_V 0:0 + +#define NVC197_RESERVED_TG09 0x0344 +#define NVC197_RESERVED_TG09_V 0:0 + +#define NVC197_RESERVED_TG10 0x0348 +#define NVC197_RESERVED_TG10_V 0:0 + +#define NVC197_RESERVED_TG11 0x034c +#define NVC197_RESERVED_TG11_V 0:0 + +#define NVC197_RESERVED_TG12 0x0350 +#define NVC197_RESERVED_TG12_V 0:0 + +#define NVC197_RESERVED_TG13 0x0354 +#define NVC197_RESERVED_TG13_V 0:0 + +#define NVC197_RESERVED_TG14 0x0358 +#define NVC197_RESERVED_TG14_V 0:0 + +#define NVC197_RESERVED_TG15 0x035c +#define NVC197_RESERVED_TG15_V 0:0 + +#define NVC197_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC197_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC197_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC197_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC197_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC197_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC197_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC197_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC197_SET_RASTER_ENABLE 0x037c +#define NVC197_SET_RASTER_ENABLE_V 0:0 +#define NVC197_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC197_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC197_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC197_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC197_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC197_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC197_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC197_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC197_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC197_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC197_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVC197_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVC197_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVC197_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVC197_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVC197_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVC197_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVC197_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVC197_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC197_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC197_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC197_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC197_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC197_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC197_SET_RASTER_INPUT 0x0740 +#define NVC197_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC197_SET_STREAM_OUTPUT 0x0744 +#define NVC197_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC197_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_ALPHA_FRACTION 0x074c +#define NVC197_SET_ALPHA_FRACTION_V 7:0 + +#define NVC197_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC197_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC197_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC197_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC197_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC197_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC197_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC197_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC197_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC197_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC197_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC197_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC197_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC197_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC197_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC197_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC197_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC197_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC197_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC197_SET_ISBE_SAVE_RESTORE_PROGRAM 0x07ac +#define NVC197_SET_ISBE_SAVE_RESTORE_PROGRAM_OFFSET 31:0 + +#define NVC197_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVC197_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC197_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC197_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC197_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC197_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC197_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC197_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC197_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC197_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC197_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC197_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC197_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC197_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC197_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC197_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC197_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC197_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC197_SET_ZCULL_STORAGE_B 0x07ec +#define NVC197_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC197_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC197_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC197_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC197_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC197_SET_ZT_READ_ONLY 0x07f8 +#define NVC197_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC197_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC197_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC197_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC197_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC197_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC197_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC197_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC197_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC197_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC197_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC197_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC197_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC197_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC197_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC197_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC197_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC197_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC197_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC197_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC197_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC197_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC197_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC197_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC197_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC197_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC197_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC197_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC197_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC197_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC197_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC197_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC197_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NVC197_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NVC197_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVC197_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVC197_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC197_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC197_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC197_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC197_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC197_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC197_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC197_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC197_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC197_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC197_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC197_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC197_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC197_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC197_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC197_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC197_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC197_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC197_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC197_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC197_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC197_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC197_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC197_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC197_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC197_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC197_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC197_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC197_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC197_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC197_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC197_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC197_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC197_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC197_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC197_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC197_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC197_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC197_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC197_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC197_SET_STATISTICS_COUNTER 0x0d68 +#define NVC197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVC197_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC197_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC197_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC197_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC197_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC197_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC197_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC197_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC197_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC197_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC197_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC197_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC197_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC197_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC197_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC197_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC197_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC197_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC197_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC197_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC197_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC197_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC197_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC197_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC197_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC197_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC197_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC197_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC197_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC197_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC197_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC197_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC197_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC197_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC197_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC197_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC197_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC197_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC197_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC197_SET_POLY_SMOOTH 0x0db4 +#define NVC197_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC197_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_ZT_MARK 0x0db8 +#define NVC197_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NVC197_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVC197_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVC197_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC197_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC197_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC197_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC197_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC197_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC197_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC197_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC197_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_PATCH 0x0dcc +#define NVC197_SET_PATCH_SIZE 7:0 + +#define NVC197_SET_ITERATED_BLEND 0x0dd0 +#define NVC197_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC197_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC197_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC197_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC197_SET_ZCULL_CRITERION 0x0dd8 +#define NVC197_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC197_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC197_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC197_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC197_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC197_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC197_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC197_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC197_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC197_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC197_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC197_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC197_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC197_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC197_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC197_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC197_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC197_SET_SCISSOR_ENABLE_V 0:0 +#define NVC197_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC197_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC197_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC197_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC197_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC197_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC197_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0f10 +#define NVC197_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVC197_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVC197_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVC197_SET_VPC_PERF_KNOB 0x0f14 +#define NVC197_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC197_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC197_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC197_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC197_PM_LOCAL_TRIGGER 0x0f18 +#define NVC197_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC197_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC197_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC197_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC197_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC197_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC197_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC197_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC197_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC197_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC197_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC197_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC197_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC197_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC197_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC197_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC197_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC197_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC197_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC197_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC197_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC197_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC197_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC197_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC197_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC197_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC197_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC197_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC197_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC197_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC197_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC197_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC197_SET_SAMPLE_MASK 0x0fa4 +#define NVC197_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC197_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC197_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC197_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC197_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC197_SET_CT_MRT_ENABLE 0x0fac +#define NVC197_SET_CT_MRT_ENABLE_V 0:0 +#define NVC197_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC197_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC197_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC197_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC197_SET_TIR 0x0fb4 +#define NVC197_SET_TIR_MODE 1:0 +#define NVC197_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC197_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC197_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC197_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC197_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC197_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC197_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC197_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC197_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC197_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC197_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC197_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC197_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC197_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC197_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_TIR_MODULATION 0x0fd4 +#define NVC197_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC197_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC197_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC197_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC197_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC197_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC197_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC197_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC197_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC197_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC197_SET_ZT_A 0x0fe0 +#define NVC197_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_ZT_B 0x0fe4 +#define NVC197_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_ZT_FORMAT 0x0fe8 +#define NVC197_SET_ZT_FORMAT_V 4:0 +#define NVC197_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC197_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC197_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC197_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC197_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC197_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC197_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC197_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC197_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC197_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC197_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC197_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC197_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC197_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC197_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC197_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC197_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC197_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC197_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC197_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC197_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC197_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC197_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC197_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC197_SET_TILED_CACHE_BUNDLE_CONTROL 0x0ffc +#define NVC197_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT 0:0 +#define NVC197_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_FALSE 0x00000000 +#define NVC197_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_TRUE 0x00000001 + +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC197_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC197_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC197_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC197_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC197_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC197_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC197_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC197_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC197_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC197_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC197_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC197_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC197_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC197_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC197_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC197_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC197_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC197_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD02 0x102c +#define NVC197_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC197_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC197_SET_SPARE_NOOP01 0x1044 +#define NVC197_SET_SPARE_NOOP01_V 31:0 + +#define NVC197_SET_SPARE_NOOP02 0x1048 +#define NVC197_SET_SPARE_NOOP02_V 31:0 + +#define NVC197_SET_SPARE_NOOP03 0x104c +#define NVC197_SET_SPARE_NOOP03_V 31:0 + +#define NVC197_SET_SPARE_NOOP04 0x1050 +#define NVC197_SET_SPARE_NOOP04_V 31:0 + +#define NVC197_SET_SPARE_NOOP05 0x1054 +#define NVC197_SET_SPARE_NOOP05_V 31:0 + +#define NVC197_SET_SPARE_NOOP06 0x1058 +#define NVC197_SET_SPARE_NOOP06_V 31:0 + +#define NVC197_SET_SPARE_NOOP07 0x105c +#define NVC197_SET_SPARE_NOOP07_V 31:0 + +#define NVC197_SET_SPARE_NOOP08 0x1060 +#define NVC197_SET_SPARE_NOOP08_V 31:0 + +#define NVC197_SET_SPARE_NOOP09 0x1064 +#define NVC197_SET_SPARE_NOOP09_V 31:0 + +#define NVC197_SET_SPARE_NOOP10 0x1068 +#define NVC197_SET_SPARE_NOOP10_V 31:0 + +#define NVC197_SET_SPARE_NOOP11 0x106c +#define NVC197_SET_SPARE_NOOP11_V 31:0 + +#define NVC197_SET_SPARE_NOOP12 0x1070 +#define NVC197_SET_SPARE_NOOP12_V 31:0 + +#define NVC197_SET_SPARE_NOOP13 0x1074 +#define NVC197_SET_SPARE_NOOP13_V 31:0 + +#define NVC197_SET_SPARE_NOOP14 0x1078 +#define NVC197_SET_SPARE_NOOP14_V 31:0 + +#define NVC197_SET_SPARE_NOOP15 0x107c +#define NVC197_SET_SPARE_NOOP15_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC197_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC197_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC197_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC197_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC197_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC197_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC197_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC197_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC197_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC197_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC197_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC197_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC197_UNBIND_ALL 0x10f4 +#define NVC197_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC197_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC197_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC197_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC197_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC197_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC197_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC197_NO_OPERATION_DATA_HI 0x110c +#define NVC197_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC197_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC197_PM_TRIGGER_END 0x1114 +#define NVC197_PM_TRIGGER_END_V 31:0 + +#define NVC197_SET_VERTEX_ID_BASE 0x1118 +#define NVC197_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC197_SET_STENCIL_COMPRESSION 0x111c +#define NVC197_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC197_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC197_SET_TIR_CONTROL 0x1130 +#define NVC197_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC197_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC197_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC197_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC197_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC197_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC197_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC197_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC197_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 + +#define NVC197_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC197_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC197_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC197_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC197_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC197_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC197_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC197_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC197_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC197_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC197_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC197_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC197_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC197_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC197_FLUSH_PENDING_WRITES 0x1144 +#define NVC197_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC197_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC197_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC197_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC197_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC197_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC197_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC197_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC197_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC197_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC197_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC197_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC197_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC197_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC197_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC197_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC197_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC197_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC197_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC197_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC197_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC197_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC197_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_SCREEN_STATE_MASK 0x1204 +#define NVC197_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC197_SET_ZT_SPARSE 0x1208 +#define NVC197_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC197_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC197_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC197_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC197_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC197_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_SET_CT_SELECT 0x121c +#define NVC197_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC197_SET_CT_SELECT_TARGET0 6:4 +#define NVC197_SET_CT_SELECT_TARGET1 9:7 +#define NVC197_SET_CT_SELECT_TARGET2 12:10 +#define NVC197_SET_CT_SELECT_TARGET3 15:13 +#define NVC197_SET_CT_SELECT_TARGET4 18:16 +#define NVC197_SET_CT_SELECT_TARGET5 21:19 +#define NVC197_SET_CT_SELECT_TARGET6 24:22 +#define NVC197_SET_CT_SELECT_TARGET7 27:25 + +#define NVC197_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC197_SET_ZT_SIZE_A 0x1228 +#define NVC197_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC197_SET_ZT_SIZE_B 0x122c +#define NVC197_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC197_SET_ZT_SIZE_C 0x1230 +#define NVC197_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC197_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC197_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC197_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC197_SET_SAMPLER_BINDING 0x1234 +#define NVC197_SET_SAMPLER_BINDING_V 0:0 +#define NVC197_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC197_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC197_DRAW_AUTO 0x123c +#define NVC197_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC197_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC197_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC197_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC197_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC197_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC197_SET_BACK_END_COPY_A 0x1264 +#define NVC197_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC197_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC197_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC197_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC197_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BACK_END_COPY_B 0x1268 +#define NVC197_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC197_SET_BACK_END_COPY_C 0x126c +#define NVC197_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC197_SET_BACK_END_COPY_D 0x1270 +#define NVC197_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC197_SET_BACK_END_COPY_E 0x1274 +#define NVC197_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC197_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC197_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVC197_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC197_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC197_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC197_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC197_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC197_CLEAR_ZCULL_REGION 0x12c8 +#define NVC197_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC197_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC197_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC197_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC197_SET_DEPTH_TEST 0x12cc +#define NVC197_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC197_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC197_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_FILL_MODE 0x12d0 +#define NVC197_SET_FILL_MODE_V 31:0 +#define NVC197_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC197_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC197_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC197_SET_SHADE_MODE 0x12d4 +#define NVC197_SET_SHADE_MODE_V 31:0 +#define NVC197_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC197_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC197_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC197_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC197_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC197_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC197_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_DEPTH_WRITE 0x12e8 +#define NVC197_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC197_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_ALPHA_TEST 0x12ec +#define NVC197_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC197_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC197_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC197_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC197_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC197_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC197_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC197_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC197_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC197_D3D_SET_CULL_MODE 0x1308 +#define NVC197_D3D_SET_CULL_MODE_V 31:0 +#define NVC197_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC197_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC197_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC197_SET_DEPTH_FUNC 0x130c +#define NVC197_SET_DEPTH_FUNC_V 31:0 +#define NVC197_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC197_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC197_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC197_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC197_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC197_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC197_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC197_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC197_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC197_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC197_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC197_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC197_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC197_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC197_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC197_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC197_SET_ALPHA_REF 0x1310 +#define NVC197_SET_ALPHA_REF_V 31:0 + +#define NVC197_SET_ALPHA_FUNC 0x1314 +#define NVC197_SET_ALPHA_FUNC_V 31:0 +#define NVC197_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC197_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC197_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC197_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC197_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC197_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC197_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC197_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC197_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC197_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC197_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC197_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC197_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC197_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC197_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC197_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC197_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC197_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC197_SET_BLEND_CONST_RED 0x131c +#define NVC197_SET_BLEND_CONST_RED_V 31:0 + +#define NVC197_SET_BLEND_CONST_GREEN 0x1320 +#define NVC197_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC197_SET_BLEND_CONST_BLUE 0x1324 +#define NVC197_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC197_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC197_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC197_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC197_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC197_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC197_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC197_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC197_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BLEND_COLOR_OP 0x1340 +#define NVC197_SET_BLEND_COLOR_OP_V 31:0 +#define NVC197_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC197_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC197_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC197_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC197_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC197_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC197_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC197_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC197_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC197_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_BLEND_ALPHA_OP 0x134c +#define NVC197_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC197_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC197_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC197_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC197_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC197_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC197_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC197_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC197_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC197_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC197_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC197_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC197_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BLEND(i) (0x1360+(i)*4) +#define NVC197_SET_BLEND_ENABLE 0:0 +#define NVC197_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_STENCIL_TEST 0x1380 +#define NVC197_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC197_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_STENCIL_OP_FAIL 0x1384 +#define NVC197_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC197_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC197_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC197_SET_STENCIL_OP_ZPASS 0x138c +#define NVC197_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC197_SET_STENCIL_FUNC 0x1390 +#define NVC197_SET_STENCIL_FUNC_V 31:0 +#define NVC197_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC197_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC197_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC197_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC197_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC197_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC197_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC197_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC197_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC197_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC197_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC197_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC197_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC197_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC197_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC197_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC197_SET_STENCIL_FUNC_REF 0x1394 +#define NVC197_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC197_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC197_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC197_SET_STENCIL_MASK 0x139c +#define NVC197_SET_STENCIL_MASK_V 7:0 + +#define NVC197_SET_DRAW_AUTO_START 0x13a4 +#define NVC197_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC197_SET_PS_SATURATE 0x13a8 +#define NVC197_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC197_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC197_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC197_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC197_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC197_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC197_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC197_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC197_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC197_SET_WINDOW_ORIGIN 0x13ac +#define NVC197_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC197_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC197_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC197_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC197_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC197_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC197_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC197_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC197_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC197_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC197_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_ALPHA_HYSTERESIS 0x1420 +#define NVC197_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NVC197_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC197_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC197_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC197_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC197_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC197_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC197_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC197_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC197_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC197_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC197_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC197_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC197_STORE_ZCULL 0x1464 +#define NVC197_STORE_ZCULL_V 0:0 + +#define NVC197_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC197_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC197_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC197_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC197_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC197_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC197_LOAD_ZCULL 0x1500 +#define NVC197_LOAD_ZCULL_V 0:0 + +#define NVC197_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC197_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC197_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC197_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC197_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC197_SET_USER_CLIP_ENABLE 0x1510 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC197_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC197_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC197_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_POINT_SIZE 0x1518 +#define NVC197_SET_POINT_SIZE_V 31:0 + +#define NVC197_SET_ZCULL_STATS 0x151c +#define NVC197_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC197_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_POINT_SPRITE 0x1520 +#define NVC197_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC197_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC197_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC197_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC197_CLEAR_REPORT_VALUE 0x1530 +#define NVC197_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC197_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC197_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC197_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC197_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC197_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC197_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVC197_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC197_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC197_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_ZT_SELECT 0x1538 +#define NVC197_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC197_SET_RENDER_ENABLE_A 0x1550 +#define NVC197_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_RENDER_ENABLE_B 0x1554 +#define NVC197_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_RENDER_ENABLE_C 0x1558 +#define NVC197_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC197_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC197_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC197_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC197_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC197_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC197_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC197_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC197_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC197_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC197_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC197_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC197_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC197_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC197_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC197_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC197_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_TEX_HEADER_POOL_C 0x157c +#define NVC197_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC197_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC197_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC197_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC197_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC197_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC197_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC197_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC197_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC197_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC197_SET_SRGB_WRITE 0x15b8 +#define NVC197_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC197_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_DEPTH_BIAS 0x15bc +#define NVC197_SET_DEPTH_BIAS_V 31:0 + +#define NVC197_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC197_SET_RT_LAYER 0x15cc +#define NVC197_SET_RT_LAYER_V 15:0 +#define NVC197_SET_RT_LAYER_CONTROL 16:16 +#define NVC197_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC197_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC197_SET_ANTI_ALIAS 0x15d0 +#define NVC197_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC197_SET_EDGE_FLAG 0x15e4 +#define NVC197_SET_EDGE_FLAG_V 0:0 +#define NVC197_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC197_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC197_DRAW_INLINE_INDEX 0x15e8 +#define NVC197_DRAW_INLINE_INDEX_V 31:0 + +#define NVC197_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC197_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC197_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC197_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC197_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC197_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC197_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC197_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC197_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC197_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC197_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC197_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC197_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC197_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC197_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC197_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC197_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC197_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC197_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC197_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC197_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC197_SET_PROGRAM_REGION_A 0x1608 +#define NVC197_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVC197_SET_PROGRAM_REGION_B 0x160c +#define NVC197_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVC197_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC197_END 0x1614 +#define NVC197_END_V 0:0 + +#define NVC197_BEGIN 0x1618 +#define NVC197_BEGIN_OP 15:0 +#define NVC197_BEGIN_OP_POINTS 0x00000000 +#define NVC197_BEGIN_OP_LINES 0x00000001 +#define NVC197_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC197_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC197_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC197_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC197_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC197_BEGIN_OP_QUADS 0x00000007 +#define NVC197_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC197_BEGIN_OP_POLYGON 0x00000009 +#define NVC197_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC197_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC197_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_BEGIN_OP_PATCH 0x0000000E +#define NVC197_BEGIN_PRIMITIVE_ID 24:24 +#define NVC197_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC197_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC197_BEGIN_INSTANCE_ID 27:26 +#define NVC197_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC197_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC197_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC197_BEGIN_SPLIT_MODE 30:29 +#define NVC197_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC197_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC197_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC197_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC197_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVC197_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC197_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_VERTEX_ID_COPY 0x161c +#define NVC197_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC197_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC197_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC197_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC197_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC197_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC197_LOAD_PRIMITIVE_ID 0x1624 +#define NVC197_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC197_SET_SHADER_BASED_CULL 0x162c +#define NVC197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_CLASS_VERSION 0x1638 +#define NVC197_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC197_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC197_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC197_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC197_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC197_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC197_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC197_SET_DA_OUTPUT 0x164c +#define NVC197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC197_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC197_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC197_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_POINT_CENTER_MODE 0x165c +#define NVC197_SET_POINT_CENTER_MODE_V 31:0 +#define NVC197_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC197_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC197_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC197_SET_LINE_STIPPLE 0x166c +#define NVC197_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC197_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC197_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC197_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC197_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC197_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC197_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC197_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC197_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC197_SET_PROVOKING_VERTEX 0x1684 +#define NVC197_SET_PROVOKING_VERTEX_V 0:0 +#define NVC197_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC197_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC197_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC197_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC197_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_POLYGON_STIPPLE 0x168c +#define NVC197_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC197_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_SHADER_CONTROL 0x1690 +#define NVC197_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC197_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC197_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC197_CHECK_CLASS_VERSION 0x16a0 +#define NVC197_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC197_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC197_SET_SPH_VERSION 0x16a4 +#define NVC197_SET_SPH_VERSION_CURRENT 15:0 +#define NVC197_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC197_CHECK_SPH_VERSION 0x16a8 +#define NVC197_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC197_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC197_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC197_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC197_SET_AAM_VERSION 0x1790 +#define NVC197_SET_AAM_VERSION_CURRENT 15:0 +#define NVC197_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC197_CHECK_AAM_VERSION 0x1794 +#define NVC197_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC197_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC197_SET_ZT_LAYER 0x179c +#define NVC197_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC197_SET_INDEX_BUFFER_A 0x17c8 +#define NVC197_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC197_SET_INDEX_BUFFER_B 0x17cc +#define NVC197_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC197_SET_INDEX_BUFFER_C 0x17d0 +#define NVC197_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC197_SET_INDEX_BUFFER_D 0x17d4 +#define NVC197_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC197_SET_INDEX_BUFFER_E 0x17d8 +#define NVC197_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC197_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC197_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC197_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC197_SET_INDEX_BUFFER_F 0x17dc +#define NVC197_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC197_DRAW_INDEX_BUFFER 0x17e0 +#define NVC197_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC197_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC197_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC197_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC197_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC197_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC197_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC197_OGL_SET_CULL 0x1918 +#define NVC197_OGL_SET_CULL_ENABLE 0:0 +#define NVC197_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC197_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC197_OGL_SET_FRONT_FACE 0x191c +#define NVC197_OGL_SET_FRONT_FACE_V 31:0 +#define NVC197_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC197_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC197_OGL_SET_CULL_FACE 0x1920 +#define NVC197_OGL_SET_CULL_FACE_V 31:0 +#define NVC197_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC197_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC197_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC197_SET_VIEWPORT_PIXEL 0x1924 +#define NVC197_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC197_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC197_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC197_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC197_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC197_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC197_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC197_SET_USER_CLIP_OP 0x1940 +#define NVC197_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC197_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC197_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC197_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC197_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC197_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC197_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC197_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC197_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC197_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC197_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC197_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC197_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC197_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC197_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC197_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC197_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC197_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC197_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC197_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC197_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC197_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC197_INVALIDATE_ZCULL 0x1958 +#define NVC197_INVALIDATE_ZCULL_V 31:0 +#define NVC197_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC197_SET_ZCULL 0x1968 +#define NVC197_SET_ZCULL_Z_ENABLE 0:0 +#define NVC197_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC197_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_ZCULL_BOUNDS 0x196c +#define NVC197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC197_ZCULL_SYNC 0x1978 +#define NVC197_ZCULL_SYNC_V 31:0 + +#define NVC197_SET_CLIP_ID_TEST 0x197c +#define NVC197_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC197_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC197_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC197_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC197_SET_CLIP_ID 0x1984 +#define NVC197_SET_CLIP_ID_V 31:0 + +#define NVC197_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC197_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC197_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC197_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC197_SET_LOGIC_OP 0x19c4 +#define NVC197_SET_LOGIC_OP_ENABLE 0:0 +#define NVC197_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC197_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC197_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC197_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC197_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC197_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC197_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC197_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC197_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC197_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC197_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC197_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC197_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC197_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC197_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC197_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC197_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC197_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC197_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC197_SET_Z_COMPRESSION 0x19cc +#define NVC197_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC197_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC197_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC197_CLEAR_SURFACE 0x19d0 +#define NVC197_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC197_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC197_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC197_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC197_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC197_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC197_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC197_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC197_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC197_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC197_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC197_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC197_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC197_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC197_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC197_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC197_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC197_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC197_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC197_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC197_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC197_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC197_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC197_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC197_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC197_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC197_PIPE_NOP 0x1a2c +#define NVC197_PIPE_NOP_V 31:0 + +#define NVC197_SET_SPARE00 0x1a30 +#define NVC197_SET_SPARE00_V 31:0 + +#define NVC197_SET_SPARE01 0x1a34 +#define NVC197_SET_SPARE01_V 31:0 + +#define NVC197_SET_SPARE02 0x1a38 +#define NVC197_SET_SPARE02_V 31:0 + +#define NVC197_SET_SPARE03 0x1a3c +#define NVC197_SET_SPARE03_V 31:0 + +#define NVC197_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC197_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC197_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC197_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC197_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC197_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC197_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC197_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC197_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC197_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC197_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC197_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC197_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC197_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC197_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC197_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC197_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC197_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC197_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC197_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC197_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC197_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC197_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC197_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC197_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC197_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC197_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVC197_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVC197_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVC197_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVC197_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVC197_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVC197_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVC197_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVC197_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC197_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC197_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC197_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC197_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC197_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC197_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC197_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC197_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC197_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC197_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC197_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NVC197_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NVC197_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC197_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC197_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC197_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NVC197_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC197_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC197_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NVC197_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVC197_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NVC197_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NVC197_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVC197_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVC197_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC197_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC197_SET_FALCON00 0x2300 +#define NVC197_SET_FALCON00_V 31:0 + +#define NVC197_SET_FALCON01 0x2304 +#define NVC197_SET_FALCON01_V 31:0 + +#define NVC197_SET_FALCON02 0x2308 +#define NVC197_SET_FALCON02_V 31:0 + +#define NVC197_SET_FALCON03 0x230c +#define NVC197_SET_FALCON03_V 31:0 + +#define NVC197_SET_FALCON04 0x2310 +#define NVC197_SET_FALCON04_V 31:0 + +#define NVC197_SET_FALCON05 0x2314 +#define NVC197_SET_FALCON05_V 31:0 + +#define NVC197_SET_FALCON06 0x2318 +#define NVC197_SET_FALCON06_V 31:0 + +#define NVC197_SET_FALCON07 0x231c +#define NVC197_SET_FALCON07_V 31:0 + +#define NVC197_SET_FALCON08 0x2320 +#define NVC197_SET_FALCON08_V 31:0 + +#define NVC197_SET_FALCON09 0x2324 +#define NVC197_SET_FALCON09_V 31:0 + +#define NVC197_SET_FALCON10 0x2328 +#define NVC197_SET_FALCON10_V 31:0 + +#define NVC197_SET_FALCON11 0x232c +#define NVC197_SET_FALCON11_V 31:0 + +#define NVC197_SET_FALCON12 0x2330 +#define NVC197_SET_FALCON12_V 31:0 + +#define NVC197_SET_FALCON13 0x2334 +#define NVC197_SET_FALCON13_V 31:0 + +#define NVC197_SET_FALCON14 0x2338 +#define NVC197_SET_FALCON14_V 31:0 + +#define NVC197_SET_FALCON15 0x233c +#define NVC197_SET_FALCON15_V 31:0 + +#define NVC197_SET_FALCON16 0x2340 +#define NVC197_SET_FALCON16_V 31:0 + +#define NVC197_SET_FALCON17 0x2344 +#define NVC197_SET_FALCON17_V 31:0 + +#define NVC197_SET_FALCON18 0x2348 +#define NVC197_SET_FALCON18_V 31:0 + +#define NVC197_SET_FALCON19 0x234c +#define NVC197_SET_FALCON19_V 31:0 + +#define NVC197_SET_FALCON20 0x2350 +#define NVC197_SET_FALCON20_V 31:0 + +#define NVC197_SET_FALCON21 0x2354 +#define NVC197_SET_FALCON21_V 31:0 + +#define NVC197_SET_FALCON22 0x2358 +#define NVC197_SET_FALCON22_V 31:0 + +#define NVC197_SET_FALCON23 0x235c +#define NVC197_SET_FALCON23_V 31:0 + +#define NVC197_SET_FALCON24 0x2360 +#define NVC197_SET_FALCON24_V 31:0 + +#define NVC197_SET_FALCON25 0x2364 +#define NVC197_SET_FALCON25_V 31:0 + +#define NVC197_SET_FALCON26 0x2368 +#define NVC197_SET_FALCON26_V 31:0 + +#define NVC197_SET_FALCON27 0x236c +#define NVC197_SET_FALCON27_V 31:0 + +#define NVC197_SET_FALCON28 0x2370 +#define NVC197_SET_FALCON28_V 31:0 + +#define NVC197_SET_FALCON29 0x2374 +#define NVC197_SET_FALCON29_V 31:0 + +#define NVC197_SET_FALCON30 0x2378 +#define NVC197_SET_FALCON30_V 31:0 + +#define NVC197_SET_FALCON31 0x237c +#define NVC197_SET_FALCON31_V 31:0 + +#define NVC197_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC197_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC197_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC197_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC197_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC197_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC197_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC197_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC197_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC197_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC197_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC197_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC197_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC197_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC197_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC197_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC197_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC197_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC197_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC197_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC197_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC197_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC197_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC197_SET_COLOR_CLAMP 0x2600 +#define NVC197_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC197_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC197_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BINDLESS_TEXTURE 0x2608 +#define NVC197_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVC197_SET_TRAP_HANDLER 0x260c +#define NVC197_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVC197_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC197_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC197_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC197_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC197_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC197_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC197_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC197_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC197_CALL_MME_MACRO_V 31:0 + +#define NVC197_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC197_CALL_MME_DATA_V 31:0 + +#endif /* _cl_pascal_b_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc1b0.h b/userspace/sdks/nv525/nvidia/inc/class/clc1b0.h new file mode 100644 index 0000000..ec139e9 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc1b0.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "nvtypes.h" + +#ifndef _clc1b0_h_ +#define _clc1b0_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC1B0_VIDEO_DECODER (0x0000C1B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc1b0_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc1b5.h b/userspace/sdks/nv525/nvidia/inc/class/clc1b5.h new file mode 100644 index 0000000..fff8467 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc1b5.h @@ -0,0 +1,273 @@ +/******************************************************************************* + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clc1b5_h_ +#define _clc1b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define PASCAL_DMA_COPY_B (0x0000C1B5) + +#define NVC1B5_NOP (0x00000100) +#define NVC1B5_NOP_PARAMETER 31:0 +#define NVC1B5_PM_TRIGGER (0x00000140) +#define NVC1B5_PM_TRIGGER_V 31:0 +#define NVC1B5_SET_SEMAPHORE_A (0x00000240) +#define NVC1B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC1B5_SET_SEMAPHORE_B (0x00000244) +#define NVC1B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC1B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC1B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC1B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC1B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC1B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC1B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC1B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC1B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC1B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC1B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC1B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC1B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC1B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC1B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC1B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC1B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC1B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC1B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC1B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC1B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC1B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC1B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC1B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC1B5_LAUNCH_DMA (0x00000300) +#define NVC1B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC1B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC1B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC1B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC1B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC1B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC1B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC1B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC1B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC1B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC1B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC1B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC1B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC1B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC1B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC1B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC1B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC1B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC1B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC1B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC1B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC1B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC1B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC1B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC1B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC1B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC1B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC1B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC1B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC1B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC1B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC1B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC1B5_LAUNCH_DMA_SRC_BYPASS_L2 20:20 +#define NVC1B5_LAUNCH_DMA_SRC_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC1B5_LAUNCH_DMA_SRC_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC1B5_LAUNCH_DMA_DST_BYPASS_L2 21:21 +#define NVC1B5_LAUNCH_DMA_DST_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC1B5_LAUNCH_DMA_DST_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC1B5_LAUNCH_DMA_VPRMODE 23:22 +#define NVC1B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVC1B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC1B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC1B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 +#define NVC1B5_OFFSET_IN_UPPER (0x00000400) +#define NVC1B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC1B5_OFFSET_IN_LOWER (0x00000404) +#define NVC1B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC1B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC1B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC1B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC1B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC1B5_PITCH_IN (0x00000410) +#define NVC1B5_PITCH_IN_VALUE 31:0 +#define NVC1B5_PITCH_OUT (0x00000414) +#define NVC1B5_PITCH_OUT_VALUE 31:0 +#define NVC1B5_LINE_LENGTH_IN (0x00000418) +#define NVC1B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC1B5_LINE_COUNT (0x0000041C) +#define NVC1B5_LINE_COUNT_VALUE 31:0 +#define NVC1B5_SET_REMAP_CONST_A (0x00000700) +#define NVC1B5_SET_REMAP_CONST_A_V 31:0 +#define NVC1B5_SET_REMAP_CONST_B (0x00000704) +#define NVC1B5_SET_REMAP_CONST_B_V 31:0 +#define NVC1B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC1B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC1B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC1B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC1B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC1B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC1B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC1B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC1B5_SET_DST_WIDTH (0x00000710) +#define NVC1B5_SET_DST_WIDTH_V 31:0 +#define NVC1B5_SET_DST_HEIGHT (0x00000714) +#define NVC1B5_SET_DST_HEIGHT_V 31:0 +#define NVC1B5_SET_DST_DEPTH (0x00000718) +#define NVC1B5_SET_DST_DEPTH_V 31:0 +#define NVC1B5_SET_DST_LAYER (0x0000071C) +#define NVC1B5_SET_DST_LAYER_V 31:0 +#define NVC1B5_SET_DST_ORIGIN (0x00000720) +#define NVC1B5_SET_DST_ORIGIN_X 15:0 +#define NVC1B5_SET_DST_ORIGIN_Y 31:16 +#define NVC1B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC1B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC1B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC1B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC1B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC1B5_SET_SRC_WIDTH (0x0000072C) +#define NVC1B5_SET_SRC_WIDTH_V 31:0 +#define NVC1B5_SET_SRC_HEIGHT (0x00000730) +#define NVC1B5_SET_SRC_HEIGHT_V 31:0 +#define NVC1B5_SET_SRC_DEPTH (0x00000734) +#define NVC1B5_SET_SRC_DEPTH_V 31:0 +#define NVC1B5_SET_SRC_LAYER (0x00000738) +#define NVC1B5_SET_SRC_LAYER_V 31:0 +#define NVC1B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC1B5_SET_SRC_ORIGIN_X 15:0 +#define NVC1B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC1B5_SRC_ORIGIN_X (0x00000744) +#define NVC1B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC1B5_SRC_ORIGIN_Y (0x00000748) +#define NVC1B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC1B5_DST_ORIGIN_X (0x0000074C) +#define NVC1B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC1B5_DST_ORIGIN_Y (0x00000750) +#define NVC1B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC1B5_PM_TRIGGER_END (0x00001114) +#define NVC1B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc1b5_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc1b5sw.h b/userspace/sdks/nv525/nvidia/inc/class/clc1b5sw.h new file mode 100644 index 0000000..27af6f2 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc1b5sw.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc1b5sw.finn +// + + + +// +// Using VERSION_0 will cause the API to interpret +// engineType as a CE engine instance. This allows +// for backward compatibility with 85B5sw and 90B5sw. +// +#define NVC1B5_ALLOCATION_PARAMETERS_VERSION_0 0 + +// +// Using VERSION_1 will cause the API to interpret +// engineType as an NV2080_ENGINE_TYPE ordinal. +// +#define NVC1B5_ALLOCATION_PARAMETERS_VERSION_1 1 + +#define NVC1B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc1b5U) + +typedef struct NVC1B5_ALLOCATION_PARAMETERS { + NvU32 version; + NvU32 engineType; +} NVC1B5_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc1b7.h b/userspace/sdks/nv525/nvidia/inc/class/clc1b7.h new file mode 100644 index 0000000..14d94ed --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc1b7.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clc1b7_h +#define clc1b7_h + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC1B7_VIDEO_ENCODER (0x0000C1B7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc1b7_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc1c0.h b/userspace/sdks/nv525/nvidia/inc/class/clc1c0.h new file mode 100644 index 0000000..f2569bf --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc1c0.h @@ -0,0 +1,795 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_pascal_compute_b_h_ +#define _cl_pascal_compute_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl pascal_compute_b */ + +#include "nvtypes.h" + +#define PASCAL_COMPUTE_B 0xC1C0 + +#define NVC1C0_SET_OBJECT 0x0000 +#define NVC1C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC1C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC1C0_NO_OPERATION 0x0100 +#define NVC1C0_NO_OPERATION_V 31:0 + +#define NVC1C0_SET_NOTIFY_A 0x0104 +#define NVC1C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC1C0_SET_NOTIFY_B 0x0108 +#define NVC1C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_NOTIFY 0x010c +#define NVC1C0_NOTIFY_TYPE 31:0 +#define NVC1C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC1C0_WAIT_FOR_IDLE 0x0110 +#define NVC1C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC1C0_SEND_GO_IDLE 0x013c +#define NVC1C0_SEND_GO_IDLE_V 31:0 + +#define NVC1C0_PM_TRIGGER 0x0140 +#define NVC1C0_PM_TRIGGER_V 31:0 + +#define NVC1C0_PM_TRIGGER_WFI 0x0144 +#define NVC1C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC1C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC1C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC1C0_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC1C0_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC1C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC1C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC1C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC1C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC1C0_LINE_LENGTH_IN 0x0180 +#define NVC1C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC1C0_LINE_COUNT 0x0184 +#define NVC1C0_LINE_COUNT_VALUE 31:0 + +#define NVC1C0_OFFSET_OUT_UPPER 0x0188 +#define NVC1C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC1C0_OFFSET_OUT 0x018c +#define NVC1C0_OFFSET_OUT_VALUE 31:0 + +#define NVC1C0_PITCH_OUT 0x0190 +#define NVC1C0_PITCH_OUT_VALUE 31:0 + +#define NVC1C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC1C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC1C0_SET_DST_WIDTH 0x0198 +#define NVC1C0_SET_DST_WIDTH_V 31:0 + +#define NVC1C0_SET_DST_HEIGHT 0x019c +#define NVC1C0_SET_DST_HEIGHT_V 31:0 + +#define NVC1C0_SET_DST_DEPTH 0x01a0 +#define NVC1C0_SET_DST_DEPTH_V 31:0 + +#define NVC1C0_SET_DST_LAYER 0x01a4 +#define NVC1C0_SET_DST_LAYER_V 31:0 + +#define NVC1C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC1C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC1C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC1C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC1C0_LAUNCH_DMA 0x01b0 +#define NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC1C0_LOAD_INLINE_DATA 0x01b4 +#define NVC1C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC1C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC1C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC1C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC1C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC1C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC1C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC1C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC1C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC1C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC1C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC1C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC1C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC1C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC1C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVC1C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVC1C0_PERFMON_TRANSFER 0x0210 +#define NVC1C0_PERFMON_TRANSFER_V 31:0 + +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0218 +#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVC1C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC1C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC1C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC1C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC1C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC1C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC1C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC1C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC1C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC1C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC1C0_SET_CWD_CONTROL 0x0240 +#define NVC1C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVC1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVC1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC1C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC1C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC1C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC1C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC1C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC1C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC1C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC1C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC1C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC1C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC1C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC1C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC1C0_SET_GWC_SCG_TYPE 0x026c +#define NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE 0:0 +#define NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0 0x00000000 +#define NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1 0x00000001 + +#define NVC1C0_SET_SCG_CONTROL 0x0270 +#define NVC1C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 +#define NVC1C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 +#define NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 +#define NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 +#define NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 + +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 16:0 + +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVC1C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC1C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC1C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC1C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC1C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC1C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC1C0_SET_QMD_VERSION 0x0288 +#define NVC1C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC1C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC1C0_SET_WFI_CONFIG 0x028c +#define NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI 0:0 +#define NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE 0x00000000 +#define NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE 0x00000001 + +#define NVC1C0_CHECK_QMD_VERSION 0x0290 +#define NVC1C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC1C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC1C0_WAIT_FOR_IDLE_SCG_TYPE 0x0294 +#define NVC1C0_WAIT_FOR_IDLE_SCG_TYPE_V 31:0 + +#define NVC1C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC1C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL 0x029c +#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE 0:0 +#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE 0x00000001 + +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC1C0_SCG_HYSTERESIS_CONTROL 0x02a8 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 + +#define NVC1C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC1C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC1C0_SEND_PCAS_A 0x02b4 +#define NVC1C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC1C0_SEND_PCAS_B 0x02b8 +#define NVC1C0_SEND_PCAS_B_FROM 23:0 +#define NVC1C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC1C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC1C0_SET_SPA_VERSION 0x0310 +#define NVC1C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC1C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC1C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC1C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC1C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC1C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC1C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC1C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC1C0_SET_FALCON00 0x0500 +#define NVC1C0_SET_FALCON00_V 31:0 + +#define NVC1C0_SET_FALCON01 0x0504 +#define NVC1C0_SET_FALCON01_V 31:0 + +#define NVC1C0_SET_FALCON02 0x0508 +#define NVC1C0_SET_FALCON02_V 31:0 + +#define NVC1C0_SET_FALCON03 0x050c +#define NVC1C0_SET_FALCON03_V 31:0 + +#define NVC1C0_SET_FALCON04 0x0510 +#define NVC1C0_SET_FALCON04_V 31:0 + +#define NVC1C0_SET_FALCON05 0x0514 +#define NVC1C0_SET_FALCON05_V 31:0 + +#define NVC1C0_SET_FALCON06 0x0518 +#define NVC1C0_SET_FALCON06_V 31:0 + +#define NVC1C0_SET_FALCON07 0x051c +#define NVC1C0_SET_FALCON07_V 31:0 + +#define NVC1C0_SET_FALCON08 0x0520 +#define NVC1C0_SET_FALCON08_V 31:0 + +#define NVC1C0_SET_FALCON09 0x0524 +#define NVC1C0_SET_FALCON09_V 31:0 + +#define NVC1C0_SET_FALCON10 0x0528 +#define NVC1C0_SET_FALCON10_V 31:0 + +#define NVC1C0_SET_FALCON11 0x052c +#define NVC1C0_SET_FALCON11_V 31:0 + +#define NVC1C0_SET_FALCON12 0x0530 +#define NVC1C0_SET_FALCON12_V 31:0 + +#define NVC1C0_SET_FALCON13 0x0534 +#define NVC1C0_SET_FALCON13_V 31:0 + +#define NVC1C0_SET_FALCON14 0x0538 +#define NVC1C0_SET_FALCON14_V 31:0 + +#define NVC1C0_SET_FALCON15 0x053c +#define NVC1C0_SET_FALCON15_V 31:0 + +#define NVC1C0_SET_FALCON16 0x0540 +#define NVC1C0_SET_FALCON16_V 31:0 + +#define NVC1C0_SET_FALCON17 0x0544 +#define NVC1C0_SET_FALCON17_V 31:0 + +#define NVC1C0_SET_FALCON18 0x0548 +#define NVC1C0_SET_FALCON18_V 31:0 + +#define NVC1C0_SET_FALCON19 0x054c +#define NVC1C0_SET_FALCON19_V 31:0 + +#define NVC1C0_SET_FALCON20 0x0550 +#define NVC1C0_SET_FALCON20_V 31:0 + +#define NVC1C0_SET_FALCON21 0x0554 +#define NVC1C0_SET_FALCON21_V 31:0 + +#define NVC1C0_SET_FALCON22 0x0558 +#define NVC1C0_SET_FALCON22_V 31:0 + +#define NVC1C0_SET_FALCON23 0x055c +#define NVC1C0_SET_FALCON23_V 31:0 + +#define NVC1C0_SET_FALCON24 0x0560 +#define NVC1C0_SET_FALCON24_V 31:0 + +#define NVC1C0_SET_FALCON25 0x0564 +#define NVC1C0_SET_FALCON25_V 31:0 + +#define NVC1C0_SET_FALCON26 0x0568 +#define NVC1C0_SET_FALCON26_V 31:0 + +#define NVC1C0_SET_FALCON27 0x056c +#define NVC1C0_SET_FALCON27_V 31:0 + +#define NVC1C0_SET_FALCON28 0x0570 +#define NVC1C0_SET_FALCON28_V 31:0 + +#define NVC1C0_SET_FALCON29 0x0574 +#define NVC1C0_SET_FALCON29_V 31:0 + +#define NVC1C0_SET_FALCON30 0x0578 +#define NVC1C0_SET_FALCON30_V 31:0 + +#define NVC1C0_SET_FALCON31 0x057c +#define NVC1C0_SET_FALCON31_V 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC1C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC1C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC1C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC1C0_SET_SPARE_NOOP12 0x0f44 +#define NVC1C0_SET_SPARE_NOOP12_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP13 0x0f48 +#define NVC1C0_SET_SPARE_NOOP13_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP14 0x0f4c +#define NVC1C0_SET_SPARE_NOOP14_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP15 0x0f50 +#define NVC1C0_SET_SPARE_NOOP15_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP00 0x1040 +#define NVC1C0_SET_SPARE_NOOP00_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP01 0x1044 +#define NVC1C0_SET_SPARE_NOOP01_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP02 0x1048 +#define NVC1C0_SET_SPARE_NOOP02_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP03 0x104c +#define NVC1C0_SET_SPARE_NOOP03_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP04 0x1050 +#define NVC1C0_SET_SPARE_NOOP04_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP05 0x1054 +#define NVC1C0_SET_SPARE_NOOP05_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP06 0x1058 +#define NVC1C0_SET_SPARE_NOOP06_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP07 0x105c +#define NVC1C0_SET_SPARE_NOOP07_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP08 0x1060 +#define NVC1C0_SET_SPARE_NOOP08_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP09 0x1064 +#define NVC1C0_SET_SPARE_NOOP09_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP10 0x1068 +#define NVC1C0_SET_SPARE_NOOP10_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP11 0x106c +#define NVC1C0_SET_SPARE_NOOP11_V 31:0 + +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC1C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC1C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC1C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC1C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC1C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC1C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC1C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC1C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC1C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC1C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC1C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC1C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC1C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC1C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC1C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC1C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC1C0_SET_PROGRAM_REGION_A 0x1608 +#define NVC1C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 16:0 + +#define NVC1C0_SET_PROGRAM_REGION_B 0x160c +#define NVC1C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC1C0_PIPE_NOP 0x1a2c +#define NVC1C0_PIPE_NOP_V 31:0 + +#define NVC1C0_SET_SPARE00 0x1a30 +#define NVC1C0_SET_SPARE00_V 31:0 + +#define NVC1C0_SET_SPARE01 0x1a34 +#define NVC1C0_SET_SPARE01_V 31:0 + +#define NVC1C0_SET_SPARE02 0x1a38 +#define NVC1C0_SET_SPARE02_V 31:0 + +#define NVC1C0_SET_SPARE03 0x1a3c +#define NVC1C0_SET_SPARE03_V 31:0 + +#define NVC1C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC1C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC1C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC1C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC1C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC1C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC1C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC1C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC1C0_SET_TRAP_HANDLER 0x260c +#define NVC1C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC1C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC1C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC1C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC1C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC1C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC1C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_pascal_compute_b_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc2b0.h b/userspace/sdks/nv525/nvidia/inc/class/clc2b0.h new file mode 100644 index 0000000..9961f82 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc2b0.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _clc2b0_h_ +#define _clc2b0_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC2B0_VIDEO_DECODER (0x0000C2B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc2b0_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc2b7.h b/userspace/sdks/nv525/nvidia/inc/class/clc2b7.h new file mode 100644 index 0000000..4c4e37d --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc2b7.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clc2b7_h +#define clc2b7_h + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC2B7_VIDEO_ENCODER (0x0000C2B7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc2b7_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc361.h b/userspace/sdks/nv525/nvidia/inc/class/clc361.h new file mode 100644 index 0000000..daa8841 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc361.h @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc361_h_ +#define _clc361_h_ + +#define VOLTA_USERMODE_A (0xc361) + +#define NVC361 0x0081ffff:0x00810000 +#define NVC361_NV_USERMODE__SIZE 65536 +#define NVC361_TIME_0 0x00000080 +#define NVC361_TIME_1 0x00000084 +#define NVC361_NOTIFY_CHANNEL_PENDING 0x00000090 + +#endif // _clc361_h_ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc365.h b/userspace/sdks/nv525/nvidia/inc/class/clc365.h new file mode 100644 index 0000000..2bbd766 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc365.h @@ -0,0 +1,88 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc365_h_ +#define _clc365_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define ACCESS_COUNTER_NOTIFY_BUFFER (0xc365) + +#define NVC365_NOTIFY_BUF +#define NVC365_NOTIFY_BUF_ENTRY 0x0000001f:0x00000000 +#define NVC365_NOTIFY_BUF_SIZE 32 +#define NVC365_NOTIFY_BUF_ENTRY_TYPE MW((0+0*32):(0*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_TYPE_CPU 0x00000000 +#define NVC365_NOTIFY_BUF_ENTRY_TYPE_GPU 0x00000001 +#define NVC365_NOTIFY_BUF_ENTRY_ADDR_TYPE MW((1+0*32):(0*32+1)) +#define NVC365_NOTIFY_BUF_ENTRY_ADDR_TYPE_GVA 0x00000000 +#define NVC365_NOTIFY_BUF_ENTRY_ADDR_TYPE_GPA 0x00000001 +#define NVC365_NOTIFY_BUF_ENTRY_BANK MW((5+0*32):(0*32+2)) +#define NVC365_NOTIFY_BUF_ENTRY_BANK_0 0x00000000 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_1 0x00000001 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_2 0x00000002 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_3 0x00000003 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_4 0x00000004 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_5 0x00000005 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_6 0x00000006 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_7 0x00000007 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_8 0x00000008 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_9 0x00000009 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_10 0x0000000a +#define NVC365_NOTIFY_BUF_ENTRY_BANK_11 0x0000000b +#define NVC365_NOTIFY_BUF_ENTRY_BANK_12 0x0000000c +#define NVC365_NOTIFY_BUF_ENTRY_BANK_13 0x0000000d +#define NVC365_NOTIFY_BUF_ENTRY_BANK_14 0x0000000e +#define NVC365_NOTIFY_BUF_ENTRY_BANK_15 0x0000000f +#define NVC365_NOTIFY_BUF_ENTRY_APERTURE MW((9+0*32):(0*32+8)) +#define NVC365_NOTIFY_BUF_ENTRY_APERTURE_VID_MEM 0x00000000 +#define NVC365_NOTIFY_BUF_ENTRY_APERTURE_PEER_MEM 0x00000001 +#define NVC365_NOTIFY_BUF_ENTRY_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC365_NOTIFY_BUF_ENTRY_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVC365_NOTIFY_BUF_ENTRY_INST_APERTURE MW((11+0*32):(0*32+10)) +#define NVC365_NOTIFY_BUF_ENTRY_INST_APERTURE_VID_MEM 0x00000000 +#define NVC365_NOTIFY_BUF_ENTRY_INST_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC365_NOTIFY_BUF_ENTRY_INST_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVC365_NOTIFY_BUF_ENTRY_INST_LO MW((31+0*32):(0*32+12)) +#define NVC365_NOTIFY_BUF_ENTRY_INST_HI MW((31+1*32):(1*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_INST MW((31+1*32):(0*32+12)) +#define NVC365_NOTIFY_BUF_ENTRY_ADDR_LO MW((31+2*32):(2*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_ADDR_HI MW((31+3*32):(3*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_ADDR MW((31+3*32):(2*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_SUB_GRANULARITY MW((31+4*32):(4*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_NOTIFY_TAG MW((19+5*32):(5*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_COUNTER_VAL MW((15+6*32):(6*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_PEER_ID MW((2+7*32):(7*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_MMU_ENGINE_ID MW((28+7*32):(7*32+20)) +#define NVC365_NOTIFY_BUF_ENTRY_VALID MW((31+7*32):(7*32+31)) +#define NVC365_NOTIFY_BUF_ENTRY_VALID_FALSE 0x00000000 +#define NVC365_NOTIFY_BUF_ENTRY_VALID_TRUE 0x00000001 +#define NVC365_NOTIFIERS_ACCESS_COUNTER (0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc365_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc369.h b/userspace/sdks/nv525/nvidia/inc/class/clc369.h new file mode 100644 index 0000000..a73e182 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc369.h @@ -0,0 +1,77 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc369_h_ +#define _clc369_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define MMU_FAULT_BUFFER (0xc369) + +#define NVC369_BUF +#define NVC369_BUF_ENTRY 0x0000001f:0x00000000 +#define NVC369_BUF_SIZE 32 +#define NVC369_BUF_ENTRY_INST_APERTURE MW((9+0*32):(0*32+8)) +#define NVC369_BUF_ENTRY_INST_APERTURE_VID_MEM 0x00000000 +#define NVC369_BUF_ENTRY_INST_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC369_BUF_ENTRY_INST_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVC369_BUF_ENTRY_INST_LO MW((31+0*32):(0*32+12)) +#define NVC369_BUF_ENTRY_INST_HI MW((31+1*32):(1*32+0)) +#define NVC369_BUF_ENTRY_INST MW((31+1*32):(0*32+12)) +#define NVC369_BUF_ENTRY_ADDR_PHYS_APERTURE MW((1+2*32):(2*32+0)) +#define NVC369_BUF_ENTRY_ADDR_LO MW((31+2*32):(2*32+12)) +#define NVC369_BUF_ENTRY_ADDR_HI MW((31+3*32):(3*32+0)) +#define NVC369_BUF_ENTRY_ADDR MW((31+3*32):(2*32+12)) +#define NVC369_BUF_ENTRY_TIMESTAMP_LO MW((31+4*32):(4*32+0)) +#define NVC369_BUF_ENTRY_TIMESTAMP_HI MW((31+5*32):(5*32+0)) +#define NVC369_BUF_ENTRY_TIMESTAMP MW((31+5*32):(4*32+0)) +#define NVC369_BUF_ENTRY_ENGINE_ID MW((8+6*32):(6*32+0)) +#define NVC369_BUF_ENTRY_FAULT_TYPE MW((4+7*32):(7*32+0)) +#define NVC369_BUF_ENTRY_REPLAYABLE_FAULT MW((7+7*32):(7*32+7)) +#define NVC369_BUF_ENTRY_REPLAYABLE_FAULT_FALSE 0x00000000 +#define NVC369_BUF_ENTRY_REPLAYABLE_FAULT_TRUE 0x00000001 +#define NVC369_BUF_ENTRY_CLIENT MW((14+7*32):(7*32+8)) +#define NVC369_BUF_ENTRY_ACCESS_TYPE MW((19+7*32):(7*32+16)) +#define NVC369_BUF_ENTRY_MMU_CLIENT_TYPE MW((20+7*32):(7*32+20)) +#define NVC369_BUF_ENTRY_GPC_ID MW((28+7*32):(7*32+24)) +#define NVC369_BUF_ENTRY_PROTECTED_MODE MW((29+7*32):(7*32+29)) +#define NVC369_BUF_ENTRY_PROTECTED_MODE_FALSE 0x00000000 +#define NVC369_BUF_ENTRY_PROTECTED_MODE_TRUE 0x00000001 +#define NVC369_BUF_ENTRY_REPLAYABLE_FAULT_EN MW((30+7*32):(7*32+30)) +#define NVC369_BUF_ENTRY_REPLAYABLE_FAULT_EN_FALSE 0x00000000 +#define NVC369_BUF_ENTRY_REPLAYABLE_FAULT_EN_TRUE 0x00000001 +#define NVC369_BUF_ENTRY_VALID MW((31+7*32):(7*32+31)) +#define NVC369_BUF_ENTRY_VALID_FALSE 0x00000000 +#define NVC369_BUF_ENTRY_VALID_TRUE 0x00000001 +#define NVC369_NOTIFIER_MMU_FAULT_NON_REPLAYABLE 0 +#define NVC369_NOTIFIER_MMU_FAULT_REPLAYABLE 1 +#define NVC369_NOTIFIER_MMU_FAULT_ERROR 2 +#define NVC369_NOTIFIER_MMU_FAULT_NON_REPLAYABLE_IN_PRIV 3 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc369_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc36f.h b/userspace/sdks/nv525/nvidia/inc/class/clc36f.h new file mode 100644 index 0000000..cae1c68 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc36f.h @@ -0,0 +1,366 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc36f_h_ +#define _clc36f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class VOLTA_CHANNEL_GPFIFO */ +/* + * Documentation for VOLTA_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + * Note there is no .mfs file for this class. + */ +#define VOLTA_CHANNEL_GPFIFO_A (0x0000C36F) + +#define NVC36F_TYPEDEF VOLTA_CHANNELChannelGPFifoA + +/* dma flow control data structure */ +typedef volatile struct Nvc36fControl_struct { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} Nvc36fControl, VoltaAControlGPFifo; + +/* fields and values */ +#define NVC36F_NUMBER_OF_SUBCHANNELS (8) +#define NVC36F_SET_OBJECT (0x00000000) +#define NVC36F_SET_OBJECT_NVCLASS 15:0 +#define NVC36F_SET_OBJECT_ENGINE 20:16 +#define NVC36F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVC36F_ILLEGAL (0x00000004) +#define NVC36F_ILLEGAL_HANDLE 31:0 +#define NVC36F_NOP (0x00000008) +#define NVC36F_NOP_HANDLE 31:0 +#define NVC36F_SEMAPHOREA (0x00000010) +#define NVC36F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVC36F_SEMAPHOREB (0x00000014) +#define NVC36F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVC36F_SEMAPHOREC (0x00000018) +#define NVC36F_SEMAPHOREC_PAYLOAD 31:0 +#define NVC36F_SEMAPHORED (0x0000001C) +#define NVC36F_SEMAPHORED_OPERATION 4:0 +#define NVC36F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVC36F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVC36F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVC36F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVC36F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 +#define NVC36F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVC36F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVC36F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVC36F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVC36F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVC36F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVC36F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVC36F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVC36F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVC36F_SEMAPHORED_REDUCTION 30:27 +#define NVC36F_SEMAPHORED_REDUCTION_MIN 0x00000000 +#define NVC36F_SEMAPHORED_REDUCTION_MAX 0x00000001 +#define NVC36F_SEMAPHORED_REDUCTION_XOR 0x00000002 +#define NVC36F_SEMAPHORED_REDUCTION_AND 0x00000003 +#define NVC36F_SEMAPHORED_REDUCTION_OR 0x00000004 +#define NVC36F_SEMAPHORED_REDUCTION_ADD 0x00000005 +#define NVC36F_SEMAPHORED_REDUCTION_INC 0x00000006 +#define NVC36F_SEMAPHORED_REDUCTION_DEC 0x00000007 +#define NVC36F_SEMAPHORED_FORMAT 31:31 +#define NVC36F_SEMAPHORED_FORMAT_SIGNED 0x00000000 +#define NVC36F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 +#define NVC36F_NON_STALL_INTERRUPT (0x00000020) +#define NVC36F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVC36F_FB_FLUSH (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR +#define NVC36F_FB_FLUSH_HANDLE 31:0 +// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for +// specifying the page address for a targeted TLB invalidate and the uTLB for +// a targeted REPLAY_CANCEL for UVM. +// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly +// rearranged fields. +#define NVC36F_MEM_OP_A (0x00000028) +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID 6:0 // only relevant for REPLAY_CANCEL_VA_GLOBAL +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11 +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001 +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000 +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12 +#define NVC36F_MEM_OP_B (0x0000002c) +#define NVC36F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0 +#define NVC36F_MEM_OP_C (0x00000030) +#define NVC36F_MEM_OP_C_MEMBAR_TYPE 2:0 +#define NVC36F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000 +#define NVC36F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE 9:7 //only relevant for REPLAY_CANCEL_VA_GLOBAL +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ 0 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE 1 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG 2 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD 3 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK 4 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL 5 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC 6 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL 7 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE +#define NVC36F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG 19:0 +// MEM_OP_D MUST be preceded by MEM_OPs A-C. +#define NVC36F_MEM_OP_D (0x00000034) +#define NVC36F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE +#define NVC36F_MEM_OP_D_OPERATION 31:27 +#define NVC36F_MEM_OP_D_OPERATION_MEMBAR 0x00000005 +#define NVC36F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVC36F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a +#define NVC36F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NVC36F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +// CLEAN_LINES is an alias for Tegra/GPU IP usage +#define NVC36F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e +#define NVC36F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVC36F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVC36F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015 +#define NVC36F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR 0x00000016 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE 1:0 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC 0x00000000 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC 0x00000001 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL 0x00000002 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED 0x00000003 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE 2:2 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC 0x00000000 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC 0x00000001 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK 6:3 +#define NVC36F_SET_REFERENCE (0x00000050) +#define NVC36F_SET_REFERENCE_COUNT 31:0 +#define NVC36F_SEM_ADDR_LO (0x0000005c) +#define NVC36F_SEM_ADDR_LO_OFFSET 31:2 +#define NVC36F_SEM_ADDR_HI (0x00000060) +#define NVC36F_SEM_ADDR_HI_OFFSET 7:0 +#define NVC36F_SEM_PAYLOAD_LO (0x00000064) +#define NVC36F_SEM_PAYLOAD_LO_PAYLOAD 31:0 +#define NVC36F_SEM_PAYLOAD_HI (0x00000068) +#define NVC36F_SEM_PAYLOAD_HI_PAYLOAD 31:0 +#define NVC36F_SEM_EXECUTE (0x0000006c) +#define NVC36F_SEM_EXECUTE_OPERATION 2:0 +#define NVC36F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000 +#define NVC36F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001 +#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ 0x00000002 +#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003 +#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_AND 0x00000004 +#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_NOR 0x00000005 +#define NVC36F_SEM_EXECUTE_OPERATION_REDUCTION 0x00000006 +#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12 +#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS 0x00000000 +#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001 +#define NVC36F_SEM_EXECUTE_RELEASE_WFI 20:20 +#define NVC36F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000 +#define NVC36F_SEM_EXECUTE_RELEASE_WFI_EN 0x00000001 +#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE 24:24 +#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000 +#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT 0x00000001 +#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25 +#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000 +#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001 +#define NVC36F_SEM_EXECUTE_REDUCTION 30:27 +#define NVC36F_SEM_EXECUTE_REDUCTION_IMIN 0x00000000 +#define NVC36F_SEM_EXECUTE_REDUCTION_IMAX 0x00000001 +#define NVC36F_SEM_EXECUTE_REDUCTION_IXOR 0x00000002 +#define NVC36F_SEM_EXECUTE_REDUCTION_IAND 0x00000003 +#define NVC36F_SEM_EXECUTE_REDUCTION_IOR 0x00000004 +#define NVC36F_SEM_EXECUTE_REDUCTION_IADD 0x00000005 +#define NVC36F_SEM_EXECUTE_REDUCTION_INC 0x00000006 +#define NVC36F_SEM_EXECUTE_REDUCTION_DEC 0x00000007 +#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT 31:31 +#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000000 +#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000001 +#define NVC36F_WFI (0x00000078) +#define NVC36F_WFI_SCOPE 0:0 +#define NVC36F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000 +#define NVC36F_WFI_SCOPE_CURRENT_VEID 0x00000000 +#define NVC36F_WFI_SCOPE_ALL 0x00000001 +#define NVC36F_CRC_CHECK (0x0000007c) +#define NVC36F_CRC_CHECK_VALUE 31:0 +#define NVC36F_YIELD (0x00000080) +#define NVC36F_YIELD_OP 1:0 +#define NVC36F_YIELD_OP_NOP 0x00000000 +#define NVC36F_YIELD_OP_RUNLIST_TIMESLICE 0x00000002 +#define NVC36F_YIELD_OP_TSG 0x00000003 +#define NVC36F_CLEAR_FAULTED (0x00000084) +#define NVC36F_CLEAR_FAULTED_CHID 11:0 +#define NVC36F_CLEAR_FAULTED_TYPE 31:31 +#define NVC36F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED 0x00000000 +#define NVC36F_CLEAR_FAULTED_TYPE_ENG_FAULTED 0x00000001 + + +/* GPFIFO entry format */ +#define NVC36F_GP_ENTRY__SIZE 8 +#define NVC36F_GP_ENTRY0_FETCH 0:0 +#define NVC36F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVC36F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVC36F_GP_ENTRY0_GET 31:2 +#define NVC36F_GP_ENTRY0_OPERAND 31:0 +#define NVC36F_GP_ENTRY1_GET_HI 7:0 +#define NVC36F_GP_ENTRY1_PRIV 8:8 +#define NVC36F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NVC36F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NVC36F_GP_ENTRY1_LEVEL 9:9 +#define NVC36F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVC36F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVC36F_GP_ENTRY1_LENGTH 30:10 +#define NVC36F_GP_ENTRY1_SYNC 31:31 +#define NVC36F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVC36F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVC36F_GP_ENTRY1_OPCODE 7:0 +#define NVC36F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVC36F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVC36F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVC36F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVC36F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVC36F_DMA_METHOD_ADDRESS 11:0 +#define NVC36F_DMA_SUBDEVICE_MASK 15:4 +#define NVC36F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVC36F_DMA_TERT_OP 17:16 +#define NVC36F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVC36F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVC36F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVC36F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVC36F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVC36F_DMA_METHOD_COUNT_OLD 28:18 +#define NVC36F_DMA_METHOD_COUNT 28:16 +#define NVC36F_DMA_IMMD_DATA 28:16 +#define NVC36F_DMA_SEC_OP 31:29 +#define NVC36F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVC36F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVC36F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVC36F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVC36F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVC36F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVC36F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVC36F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVC36F_DMA_INCR_ADDRESS 11:0 +#define NVC36F_DMA_INCR_SUBCHANNEL 15:13 +#define NVC36F_DMA_INCR_COUNT 28:16 +#define NVC36F_DMA_INCR_OPCODE 31:29 +#define NVC36F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVC36F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVC36F_DMA_NONINCR_ADDRESS 11:0 +#define NVC36F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVC36F_DMA_NONINCR_COUNT 28:16 +#define NVC36F_DMA_NONINCR_OPCODE 31:29 +#define NVC36F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVC36F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVC36F_DMA_ONEINCR_ADDRESS 11:0 +#define NVC36F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVC36F_DMA_ONEINCR_COUNT 28:16 +#define NVC36F_DMA_ONEINCR_OPCODE 31:29 +#define NVC36F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVC36F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVC36F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVC36F_DMA_IMMD_ADDRESS 11:0 +#define NVC36F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVC36F_DMA_IMMD_DATA 28:16 +#define NVC36F_DMA_IMMD_OPCODE 31:29 +#define NVC36F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVC36F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVC36F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC36F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVC36F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVC36F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC36F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVC36F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC36F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVC36F_DMA_ENDSEG_OPCODE 31:29 +#define NVC36F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVC36F_DMA_ADDRESS 12:2 +#define NVC36F_DMA_SUBCH 15:13 +#define NVC36F_DMA_OPCODE3 17:16 +#define NVC36F_DMA_OPCODE3_NONE (0x00000000) +#define NVC36F_DMA_COUNT 28:18 +#define NVC36F_DMA_OPCODE 31:29 +#define NVC36F_DMA_OPCODE_METHOD (0x00000000) +#define NVC36F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVC36F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc36f_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc36fsw.h b/userspace/sdks/nv525/nvidia/inc/class/clc36fsw.h new file mode 100644 index 0000000..b54c505 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc36fsw.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* This file is *not* auto-generated. */ + +#ifndef _clc36f_sw_h_ +#define _clc36f_sw_h_ + +#define NVC36F_NOTIFIERS_RC (0) +#define NVC36F_NOTIFIERS_REFCNT (1) +#define NVC36F_NOTIFIERS_NONSTALL (2) +#define NVC36F_NOTIFIERS_EVENTBUFFER (3) +#define NVC36F_NOTIFIERS_IDLECHANNEL (4) +#define NVC36F_NOTIFIERS_ENDCTX (5) +#define NVC36F_NOTIFIERS_SW (6) +#define NVC36F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVC36F_NOTIFIERS_REPLAYABLE_FAULT (8) +#define NVC36F_NOTIFIERS_MAXCOUNT (9) + +/* NvNotification[] fields and values */ +#define NVC36F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVC36F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _clc36f_sw_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc370.h b/userspace/sdks/nv525/nvidia/inc/class/clc370.h new file mode 100644 index 0000000..4f6bf4b --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc370.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc370.finn +// + +#include "clc370_notification.h" + +#define NVC370_DISPLAY (0xc370U) /* finn: Evaluated from "NVC370_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NVC370_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc370U) + +typedef struct NVC370_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NVC370_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc370_notification.h b/userspace/sdks/nv525/nvidia/inc/class/clc370_notification.h new file mode 100644 index 0000000..e0c8867 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc370_notification.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc370_notification_h_ +#define _clc370_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "class/cl5070.h" + +/* event values */ +#define NVC370_NOTIFIERS_SW NV5070_NOTIFIERS_SW +#define NVC370_NOTIFIERS_BEGIN NV5070_NOTIFIERS_MAXCOUNT +#define NVC370_NOTIFIERS_VPR NVC370_NOTIFIERS_BEGIN + (0) +#define NVC370_NOTIFIERS_RG_SEM_NOTIFICATION NVC370_NOTIFIERS_VPR + (1) +#define NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION NVC370_NOTIFIERS_RG_SEM_NOTIFICATION + (1) +#define NVC370_NOTIFIERS_MAXCOUNT NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION + (1) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc370_notification_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc371.h b/userspace/sdks/nv525/nvidia/inc/class/clc371.h new file mode 100644 index 0000000..a8398cc --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc371.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc371_h_ +#define _clc371_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC371_DISP_SF_USER (0x000C371) + +typedef volatile struct _clc371_tag0 { + NvU32 dispSfUserOffset[0x400]; +} _NvC371DispSfUser, NvC371DispSfUserMap; + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _clc371_h_ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc372sw.h b/userspace/sdks/nv525/nvidia/inc/class/clc372sw.h new file mode 100644 index 0000000..552ea08 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc372sw.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc372sw_h_ +#define _clc372sw_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC372_DISPLAY_SW (0x0000C372) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc372sw_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc373.h b/userspace/sdks/nv525/nvidia/inc/class/clc373.h new file mode 100644 index 0000000..c707022 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc373.h @@ -0,0 +1,350 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc373_h_ +#define _clc373_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC373_DISP_CAPABILITIES 0xC373 + +typedef volatile struct _clc373_tag0 { + NvU32 dispCapabilities[0x400]; +} _NvC373DispCapabilities,NvC373DispCapabilities_Map ; + + +#define NVC373_SYS_CAP 0x0 /* RW-4R */ +#define NVC373_SYS_CAP_HEAD0_EXISTS 0:0 /* RWIVF */ +#define NVC373_SYS_CAP_HEAD0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_HEAD1_EXISTS 1:1 /* RWIVF */ +#define NVC373_SYS_CAP_HEAD1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_HEAD2_EXISTS 2:2 /* RWIVF */ +#define NVC373_SYS_CAP_HEAD2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_HEAD3_EXISTS 3:3 /* RWIVF */ +#define NVC373_SYS_CAP_HEAD3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_HEAD4_EXISTS 4:4 /* RWIVF */ +#define NVC373_SYS_CAP_HEAD4_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_HEAD5_EXISTS 5:5 /* RWIVF */ +#define NVC373_SYS_CAP_HEAD5_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_HEAD6_EXISTS 6:6 /* RWIVF */ +#define NVC373_SYS_CAP_HEAD6_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_HEAD7_EXISTS 7:7 /* RWIVF */ +#define NVC373_SYS_CAP_HEAD7_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVC373_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */ +#define NVC373_SYS_CAP_HEAD_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR0_EXISTS 8:8 /* RWIVF */ +#define NVC373_SYS_CAP_SOR0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR1_EXISTS 9:9 /* RWIVF */ +#define NVC373_SYS_CAP_SOR1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR2_EXISTS 10:10 /* RWIVF */ +#define NVC373_SYS_CAP_SOR2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR3_EXISTS 11:11 /* RWIVF */ +#define NVC373_SYS_CAP_SOR3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR4_EXISTS 12:12 /* RWIVF */ +#define NVC373_SYS_CAP_SOR4_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR5_EXISTS 13:13 /* RWIVF */ +#define NVC373_SYS_CAP_SOR5_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR6_EXISTS 14:14 /* RWIVF */ +#define NVC373_SYS_CAP_SOR6_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR7_EXISTS 15:15 /* RWIVF */ +#define NVC373_SYS_CAP_SOR7_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* RWIVF */ +#define NVC373_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */ +#define NVC373_SYS_CAP_SOR_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB 0x4 /* RW-4R */ +#define NVC373_SYS_CAPB_WINDOW0_EXISTS 0:0 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW1_EXISTS 1:1 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW2_EXISTS 2:2 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW3_EXISTS 3:3 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW4_EXISTS 4:4 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW4_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW5_EXISTS 5:5 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW5_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW6_EXISTS 6:6 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW6_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW7_EXISTS 7:7 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW7_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW8_EXISTS 8:8 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW8_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW8_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW8_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW9_EXISTS 9:9 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW9_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW9_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW9_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW10_EXISTS 10:10 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW10_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW10_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW10_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW11_EXISTS 11:11 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW11_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW11_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW11_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW12_EXISTS 12:12 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW12_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW12_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW12_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW13_EXISTS 13:13 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW13_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW13_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW13_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW14_EXISTS 14:14 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW14_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW14_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW14_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW15_EXISTS 15:15 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW15_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW15_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW15_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW16_EXISTS 16:16 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW16_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW16_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW16_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW17_EXISTS 17:17 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW17_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW17_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW17_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW18_EXISTS 18:18 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW18_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW18_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW18_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW19_EXISTS 19:19 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW19_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW19_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW19_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW20_EXISTS 20:20 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW20_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW20_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW20_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW21_EXISTS 21:21 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW21_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW21_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW21_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW22_EXISTS 22:22 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW22_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW22_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW22_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW23_EXISTS 23:23 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW23_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW23_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW23_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW24_EXISTS 24:24 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW24_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW24_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW24_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW25_EXISTS 25:25 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW25_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW25_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW25_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW26_EXISTS 26:26 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW26_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW26_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW26_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW27_EXISTS 27:27 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW27_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW27_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW27_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW28_EXISTS 28:28 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW28_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW28_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW28_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW29_EXISTS 29:29 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW29_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW29_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW29_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW30_EXISTS 30:30 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW30_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW30_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW30_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW31_EXISTS 31:31 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW31_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW31_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW31_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW_EXISTS__SIZE_1 32 /* */ +#define NVC373_SYS_CAPB_WINDOW_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_HEAD_CAPA(i) (0x30+(i)*32) /* RW-4A */ +#define NVC373_HEAD_CAPA__SIZE_1 8 /* */ +#define NVC373_HEAD_CAPA_SCALER 0:0 /* RWIVF */ +#define NVC373_HEAD_CAPA_SCALER_TRUE 0x00000001 /* RW--V */ +#define NVC373_HEAD_CAPA_SCALER_FALSE 0x00000000 /* RW--V */ +#define NVC373_HEAD_CAPA_SCALER_INIT 0x00000000 /* RWI-V */ +#define NVC373_HEAD_CAPA_SCALER_HAS_YUV422 1:1 /* RWIVF */ +#define NVC373_HEAD_CAPA_SCALER_HAS_YUV422_TRUE 0x00000001 /* RW--V */ +#define NVC373_HEAD_CAPA_SCALER_HAS_YUV422_FALSE 0x00000000 /* RW--V */ +#define NVC373_HEAD_CAPA_SCALER_HAS_YUV422_INIT 0x00000000 /* RWI-V */ +#define NVC373_HEAD_CAPA_HSAT 2:2 /* RWIVF */ +#define NVC373_HEAD_CAPA_HSAT_TRUE 0x00000001 /* RW--V */ +#define NVC373_HEAD_CAPA_HSAT_FALSE 0x00000000 /* RW--V */ +#define NVC373_HEAD_CAPA_HSAT_INIT 0x00000000 /* RWI-V */ +#define NVC373_HEAD_CAPA_OCSC 3:3 /* RWIVF */ +#define NVC373_HEAD_CAPA_OCSC_TRUE 0x00000001 /* RW--V */ +#define NVC373_HEAD_CAPA_OCSC_FALSE 0x00000000 /* RW--V */ +#define NVC373_HEAD_CAPA_OCSC_INIT 0x00000000 /* RWI-V */ +#define NVC373_HEAD_CAPA_YUV422 4:4 /* RWIVF */ +#define NVC373_HEAD_CAPA_YUV422_TRUE 0x00000001 /* RW--V */ +#define NVC373_HEAD_CAPA_YUV422_FALSE 0x00000000 /* RW--V */ +#define NVC373_HEAD_CAPA_YUV422_INIT 0x00000000 /* RWI-V */ +#define NVC373_HEAD_CAPA_LUT_TYPE 6:5 /* RWIVF */ +#define NVC373_HEAD_CAPA_LUT_TYPE_NONE 0x00000000 /* RW--V */ +#define NVC373_HEAD_CAPA_LUT_TYPE_257 0x00000001 /* RW--V */ +#define NVC373_HEAD_CAPA_LUT_TYPE_1025 0x00000002 /* RW--V */ +#define NVC373_HEAD_CAPA_LUT_TYPE_INIT 0x00000000 /* RWI-V */ +#define NVC373_HEAD_CAPA_LUT_LOCATION 7:7 /* RWIVF */ +#define NVC373_HEAD_CAPA_LUT_LOCATION_EARLY 0x00000000 /* RW--V */ +#define NVC373_HEAD_CAPA_LUT_LOCATION_LATE 0x00000001 /* RW--V */ +#define NVC373_HEAD_CAPA_LUT_LOCATION_INIT 0x00000000 /* RWI-V */ +#define NVC373_HEAD_CAPD(i) (0x3c+(i)*32) /* RW-4A */ +#define NVC373_HEAD_CAPD__SIZE_1 8 /* */ +#define NVC373_HEAD_CAPD_MAX_PIXELS_2TAP422 15:0 /* RWIUF */ +#define NVC373_HEAD_CAPD_MAX_PIXELS_2TAP422_INIT 0x00000000 /* RWI-V */ +#define NVC373_HEAD_CAPD_MAX_PIXELS_2TAP444 31:16 /* RWIUF */ +#define NVC373_HEAD_CAPD_MAX_PIXELS_2TAP444_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP(i) (0x144+(i)*8) /* RW-4A */ +#define NVC373_SOR_CAP__SIZE_1 8 /* */ +#define NVC373_SOR_CAP_SINGLE_LVDS_18 0:0 /* RWIVF */ +#define NVC373_SOR_CAP_SINGLE_LVDS_18_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_SINGLE_LVDS_24 1:1 /* RWIVF */ +#define NVC373_SOR_CAP_SINGLE_LVDS_24_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_DUAL_LVDS_18 2:2 /* RWIVF */ +#define NVC373_SOR_CAP_DUAL_LVDS_18_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_DUAL_LVDS_24 3:3 /* RWIVF */ +#define NVC373_SOR_CAP_DUAL_LVDS_24_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_SINGLE_TMDS_A 8:8 /* RWIVF */ +#define NVC373_SOR_CAP_SINGLE_TMDS_A_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_SINGLE_TMDS_B 9:9 /* RWIVF */ +#define NVC373_SOR_CAP_SINGLE_TMDS_B_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_DUAL_TMDS 11:11 /* RWIVF */ +#define NVC373_SOR_CAP_DUAL_TMDS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* RWIVF */ +#define NVC373_SOR_CAP_DISPLAY_OVER_PCIE_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_SDI 16:16 /* RWIVF */ +#define NVC373_SOR_CAP_SDI_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_SDI_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_SDI_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_DP_A 24:24 /* RWIVF */ +#define NVC373_SOR_CAP_DP_A_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_DP_A_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_DP_A_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_DP_B 25:25 /* RWIVF */ +#define NVC373_SOR_CAP_DP_B_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_DP_B_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_DP_B_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_DP_INTERLACE 26:26 /* RWIVF */ +#define NVC373_SOR_CAP_DP_INTERLACE_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_DP_8_LANES 27:27 /* RWIVF */ +#define NVC373_SOR_CAP_DP_8_LANES_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CLK_CAP(i) (0x608+(i)*4) /* RW-4A */ +#define NVC373_SOR_CLK_CAP__SIZE_1 8 /* */ +#define NVC373_SOR_CLK_CAP_DP_MAX 7:0 /* RWIUF */ +#define NVC373_SOR_CLK_CAP_DP_MAX_INIT 0x00000036 /* RWI-V */ +#define NVC373_SOR_CLK_CAP_TMDS_MAX 23:16 /* RWIUF */ +#define NVC373_SOR_CLK_CAP_TMDS_MAX_INIT 0x0000003C /* RWI-V */ +#define NVC373_SOR_CLK_CAP_LVDS_MAX 31:24 /* RWIUF */ +#define NVC373_SOR_CLK_CAP_LVDS_MAX_INIT 0x00000000 /* RWI-V */ + +#ifdef __cplusplus +}; +#endif /* extern C */ +#endif //_clc373_h_ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc37a.h b/userspace/sdks/nv525/nvidia/inc/class/clc37a.h new file mode 100644 index 0000000..4a096b6 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc37a.h @@ -0,0 +1,213 @@ +/* + * Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _clc37a__h_ +#define _clc37a__h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC37A_CURSOR_IMM_CHANNEL_PIO (0x0000C37A) + +typedef volatile struct _clc37a_tag0 { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x7D]; + NvV32 Update; // 0x00000200 - 0x00000203 + NvV32 SetInterlockFlags; // 0x00000204 - 0x00000207 + NvV32 SetCursorHotSpotPointOut[2]; // 0x00000208 - 0x0000020F + NvV32 SetWindowInterlockFlags; // 0x00000210 - 0x00000213 + NvV32 Reserved02[0x37B]; +} NVC37ADispCursorImmControlPio; + +#define NVC37A_FREE (0x00000008) +#define NVC37A_FREE_COUNT 5:0 +#define NVC37A_UPDATE (0x00000200) +#define NVC37A_UPDATE_RELEASE_ELV 0:0 +#define NVC37A_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC37A_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC37A_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC37A_SET_INTERLOCK_FLAGS (0x00000204) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC37A_SET_CURSOR_HOT_SPOT_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVC37A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0 +#define NVC37A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS (0x00000210) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc37a_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc37b.h b/userspace/sdks/nv525/nvidia/inc/class/clc37b.h new file mode 100644 index 0000000..b61700e --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc37b.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _clC37b_h_ +#define _clC37b_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC37B_WINDOW_IMM_CHANNEL_DMA (0x0000C37B) + +// dma opcode instructions +#define NVC37B_DMA +#define NVC37B_DMA_OPCODE 31:29 +#define NVC37B_DMA_OPCODE_METHOD 0x00000000 +#define NVC37B_DMA_OPCODE_JUMP 0x00000001 +#define NVC37B_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC37B_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC37B_DMA_METHOD_COUNT 27:18 +#define NVC37B_DMA_METHOD_OFFSET 13:2 +#define NVC37B_DMA_DATA 31:0 +#define NVC37B_DMA_DATA_NOP 0x00000000 +#define NVC37B_DMA_JUMP_OFFSET 11:2 +#define NVC37B_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVC37B_PUT (0x00000000) +#define NVC37B_PUT_PTR 9:0 +#define NVC37B_GET (0x00000004) +#define NVC37B_GET_PTR 9:0 +#define NVC37B_UPDATE (0x00000200) +#define NVC37B_UPDATE_RELEASE_ELV 0:0 +#define NVC37B_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC37B_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC37B_UPDATE_INTERLOCK_WITH_WINDOW 1:1 +#define NVC37B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC37B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC37B_SET_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVC37B_SET_POINT_OUT_X 15:0 +#define NVC37B_SET_POINT_OUT_Y 31:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC37b_h diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc37d.h b/userspace/sdks/nv525/nvidia/inc/class/clc37d.h new file mode 100644 index 0000000..9ac7050 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc37d.h @@ -0,0 +1,953 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _clC37d_h_ +#define _clC37d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC37D_CORE_CHANNEL_DMA (0x0000C37D) + +#define NV_DISP_NOTIFIER 0x00000000 +#define NV_DISP_NOTIFIER_SIZEOF 0x00000010 +#define NV_DISP_NOTIFIER__0 0x00000000 +#define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFIER__0_FIELD 8:8 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE 9:9 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001 +#define NV_DISP_NOTIFIER__0_R1 15:10 +#define NV_DISP_NOTIFIER__0_R2 23:16 +#define NV_DISP_NOTIFIER__0_R3 29:24 +#define NV_DISP_NOTIFIER__0_STATUS 31:30 +#define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002 +#define NV_DISP_NOTIFIER__1 0x00000001 +#define NV_DISP_NOTIFIER__1_R4 31:0 +#define NV_DISP_NOTIFIER__2 0x00000002 +#define NV_DISP_NOTIFIER__2_TIMESTAMP_LO 31:0 +#define NV_DISP_NOTIFIER__3 0x00000003 +#define NV_DISP_NOTIFIER__3_TIMESTAMP_HI 31:0 + + +// dma opcode instructions +#define NVC37D_DMA +#define NVC37D_DMA_OPCODE 31:29 +#define NVC37D_DMA_OPCODE_METHOD 0x00000000 +#define NVC37D_DMA_OPCODE_JUMP 0x00000001 +#define NVC37D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC37D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC37D_DMA_METHOD_COUNT 27:18 +#define NVC37D_DMA_METHOD_OFFSET 13:2 +#define NVC37D_DMA_DATA 31:0 +#define NVC37D_DMA_DATA_NOP 0x00000000 +#define NVC37D_DMA_JUMP_OFFSET 11:2 +#define NVC37D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// if cap SUPPORT_FLEXIBLE_WIN_MAPPING is FALSE, this define can be used to obtain which head a window is mapped to +#define NVC37D_WINDOW_MAPPED_TO_HEAD(w) ((w)>>1) +#define NVC37D_GET_VALID_WINDOWMASK_FOR_HEAD(h) ((1<<((h)*2)) | (1<<((h)*2+1))) + +// class methods +#define NVC37D_PUT (0x00000000) +#define NVC37D_PUT_PTR 9:0 +#define NVC37D_GET (0x00000004) +#define NVC37D_GET_PTR 9:0 +#define NVC37D_UPDATE (0x00000200) +#define NVC37D_UPDATE_SPECIAL_HANDLING 21:20 +#define NVC37D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NVC37D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NVC37D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NVC37D_UPDATE_SPECIAL_HANDLING_REASON 19:12 +#define NVC37D_UPDATE_INHIBIT_INTERRUPTS 24:24 +#define NVC37D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NVC37D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NVC37D_UPDATE_RELEASE_ELV 0:0 +#define NVC37D_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC37D_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC37D_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC37D_SET_CONTEXT_DMA_NOTIFIER (0x00000208) +#define NVC37D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NVC37D_SET_NOTIFIER_CONTROL (0x0000020C) +#define NVC37D_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC37D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC37D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC37D_SET_NOTIFIER_CONTROL_OFFSET 11:4 +#define NVC37D_SET_NOTIFIER_CONTROL_NOTIFY 12:12 +#define NVC37D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NVC37D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NVC37D_SET_CONTROL (0x00000210) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN(i) ((i)+0):((i)+0) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN__SIZE_1 4 +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN_DISABLE (0x00000000) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN_ENABLE (0x00000001) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN0 0:0 +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN0_DISABLE (0x00000000) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN0_ENABLE (0x00000001) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN1 1:1 +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN1_DISABLE (0x00000000) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN1_ENABLE (0x00000001) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN2 2:2 +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN2_DISABLE (0x00000000) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN2_ENABLE (0x00000001) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN3 3:3 +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN3_DISABLE (0x00000000) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN3_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS (0x00000218) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+0):((i)+0) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS (0x0000021C) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVC37D_GET_RG_SCAN_LINE(b) (0x00000220 + (b)*0x00000004) +#define NVC37D_GET_RG_SCAN_LINE_LINE 15:0 +#define NVC37D_GET_RG_SCAN_LINE_VBLANK 16:16 +#define NVC37D_GET_RG_SCAN_LINE_VBLANK_FALSE (0x00000000) +#define NVC37D_GET_RG_SCAN_LINE_VBLANK_TRUE (0x00000001) +#define NVC37D_SET_GET_BLANKING_CTRL(b) (0x00000240 + (b)*0x00000004) +#define NVC37D_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NVC37D_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NVC37D_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NVC37D_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NVC37D_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NVC37D_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) + +#define NVC37D_PIOR_SET_CONTROL(a) (0x00000280 + (a)*0x00000020) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK 7:0 +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVC37D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NVC37D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NVC37D_PIOR_SET_CONTROL_PROTOCOL_EXT_SDI_SD_ENC (0x00000001) +#define NVC37D_PIOR_SET_CONTROL_PROTOCOL_EXT_SDI_HD_ENC (0x00000002) +#define NVC37D_PIOR_SET_CONTROL_PROTOCOL_DIST_RENDER_OUT (0x00000004) +#define NVC37D_PIOR_SET_CONTROL_PROTOCOL_DIST_RENDER_IN (0x00000005) +#define NVC37D_PIOR_SET_CONTROL_PROTOCOL_DIST_RENDER_INOUT (0x00000006) +#define NVC37D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 16:16 +#define NVC37D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC37D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC37D_PIOR_SET_CUSTOM_REASON(a) (0x00000284 + (a)*0x00000020) +#define NVC37D_PIOR_SET_CUSTOM_REASON_CODE 31:0 +#define NVC37D_PIOR_SET_SW_SPARE_A(a) (0x00000288 + (a)*0x00000020) +#define NVC37D_PIOR_SET_SW_SPARE_A_CODE 31:0 +#define NVC37D_PIOR_SET_SW_SPARE_B(a) (0x0000028C + (a)*0x00000020) +#define NVC37D_PIOR_SET_SW_SPARE_B_CODE 31:0 + +#define NVC37D_SOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK 7:0 +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DSI (0x0000000A) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NVC37D_SOR_SET_CONTROL_DE_SYNC_POLARITY 16:16 +#define NVC37D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC37D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NVC37D_SOR_SET_CUSTOM_REASON(a) (0x00000304 + (a)*0x00000020) +#define NVC37D_SOR_SET_CUSTOM_REASON_CODE 31:0 +#define NVC37D_SOR_SET_SW_SPARE_A(a) (0x00000308 + (a)*0x00000020) +#define NVC37D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NVC37D_SOR_SET_SW_SPARE_B(a) (0x0000030C + (a)*0x00000020) +#define NVC37D_SOR_SET_SW_SPARE_B_CODE 31:0 + +#define NVC37D_WINDOW_SET_CONTROL(a) (0x00001000 + (a)*0x00000080) +#define NVC37D_WINDOW_SET_CONTROL_OWNER 3:0 +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD(i) (0x00000000 +(i)) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD__SIZE_1 8 +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD0 (0x00000000) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD1 (0x00000001) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD2 (0x00000002) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD3 (0x00000003) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD4 (0x00000004) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD5 (0x00000005) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD6 (0x00000006) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD7 (0x00000007) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_NONE (0x0000000F) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0x00000080) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a) (0x00001008 + (a)*0x00000080) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR(a) (0x0000100C + (a)*0x00000080) +#define NVC37D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVC37D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a) (0x00001010 + (a)*0x00000080) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_MAX_PIXELS_FETCHED_PER_LINE 14:0 +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT 17:16 +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT_USAGE_NONE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT_USAGE_257 (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT_USAGE_1025 (0x00000002) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS 22:20 +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED 24:24 +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) + +#define NVC37D_HEAD_SET_PROCAMP(a) (0x00002000 + (a)*0x00000400) +#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003) +#define NVC37D_HEAD_SET_PROCAMP_CHROMA_LPF 3:3 +#define NVC37D_HEAD_SET_PROCAMP_CHROMA_LPF_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_PROCAMP_CHROMA_LPF_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_PROCAMP_SAT_COS 15:4 +#define NVC37D_HEAD_SET_PROCAMP_SAT_SINE 27:16 +#define NVC37D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 28:28 +#define NVC37D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NVC37D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NVC37D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 29:29 +#define NVC37D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL 31:30 +#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL_AUTO (0x00000000) +#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL_VIDEO (0x00000001) +#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL_GRAPHICS (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00002004 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 2:2 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 3:3 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 7:4 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000004) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000005) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000006) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000007) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000008) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 24:24 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 23:12 +#define NVC37D_HEAD_SET_CONTROL(a) (0x00002008 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTROL_STRUCTURE 1:0 +#define NVC37D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE 2:2 +#define NVC37D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_NORMAL (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 11:10 +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 8:4 +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 15:12 +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 23:22 +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 20:16 +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN 28:24 +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000004) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000005) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000006) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000007) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000008) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000009) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000B) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000C) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000D) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000E) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000F) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x00000010) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NVC37D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NVC37D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x0000200C + (a)*0x00000400) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC37D_HEAD_SET_PIXEL_REORDER_CONTROL(a) (0x00002010 + (a)*0x00000400) +#define NVC37D_HEAD_SET_PIXEL_REORDER_CONTROL_BANK_WIDTH 13:0 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00002014 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVC37D_HEAD_SET_DITHER_CONTROL(a) (0x00002018 + (a)*0x00000400) +#define NVC37D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NVC37D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS 5:4 +#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_6_BITS (0x00000000) +#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_8_BITS (0x00000001) +#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_10_BITS (0x00000002) +#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_12_BITS (0x00000003) +#define NVC37D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE 2:2 +#define NVC37D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE 10:8 +#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NVC37D_HEAD_SET_DITHER_CONTROL_PHASE 13:12 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x0000201C + (a)*0x00000400) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 0:0 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING 4:4 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 9:8 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NVC37D_HEAD_SET_DISPLAY_ID(a,b) (0x00002020 + (a)*0x00000400 + (b)*0x00000004) +#define NVC37D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00002028 + (a)*0x00000400) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC37D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR(a) (0x0000202C + (a)*0x00000400) +#define NVC37D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVC37D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS(a) (0x00002030 + (a)*0x00000400) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR 2:0 +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_NONE (0x00000000) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W32_H32 (0x00000001) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W64_H64 (0x00000002) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W128_H128 (0x00000003) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W256_H256 (0x00000004) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT 5:4 +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED 8:8 +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVC37D_HEAD_SET_STALL_LOCK(a) (0x00002034 + (a)*0x00000400) +#define NVC37D_HEAD_SET_STALL_LOCK_ENABLE 0:0 +#define NVC37D_HEAD_SET_STALL_LOCK_ENABLE_FALSE (0x00000000) +#define NVC37D_HEAD_SET_STALL_LOCK_ENABLE_TRUE (0x00000001) +#define NVC37D_HEAD_SET_STALL_LOCK_MODE 2:2 +#define NVC37D_HEAD_SET_STALL_LOCK_MODE_CONTINUOUS (0x00000000) +#define NVC37D_HEAD_SET_STALL_LOCK_MODE_ONE_SHOT (0x00000001) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN 8:4 +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC37D_HEAD_SET_STALL_LOCK_UNSTALL_MODE 12:12 +#define NVC37D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_CRASH_LOCK (0x00000000) +#define NVC37D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_LINE_LOCK (0x00000001) +#define NVC37D_HEAD_SET_STALL_LOCK_TEPOLARITY 14:14 +#define NVC37D_HEAD_SET_STALL_LOCK_TEPOLARITY_POSITIVE_TRUE (0x00000000) +#define NVC37D_HEAD_SET_STALL_LOCK_TEPOLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC37D_HEAD_SET_LOCK_CHAIN(a) (0x00002044 + (a)*0x00000400) +#define NVC37D_HEAD_SET_LOCK_CHAIN_POSITION 3:0 +#define NVC37D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x00002048 + (a)*0x00000400) +#define NVC37D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NVC37D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NVC37D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x0000204C + (a)*0x00000400) +#define NVC37D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NVC37D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NVC37D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x00002058 + (a)*0x00000400) +#define NVC37D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NVC37D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NVC37D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x0000205C + (a)*0x00000400) +#define NVC37D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NVC37D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NVC37D_HEAD_SET_DESKTOP_COLOR(a) (0x00002060 + (a)*0x00000400) +#define NVC37D_HEAD_SET_DESKTOP_COLOR_ALPHA 7:0 +#define NVC37D_HEAD_SET_DESKTOP_COLOR_RED 15:8 +#define NVC37D_HEAD_SET_DESKTOP_COLOR_GREEN 23:16 +#define NVC37D_HEAD_SET_DESKTOP_COLOR_BLUE 31:24 +#define NVC37D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000400) +#define NVC37D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NVC37D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NVC37D_HEAD_SET_RASTER_SYNC_END(a) (0x00002068 + (a)*0x00000400) +#define NVC37D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NVC37D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NVC37D_HEAD_SET_RASTER_BLANK_END(a) (0x0000206C + (a)*0x00000400) +#define NVC37D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NVC37D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NVC37D_HEAD_SET_RASTER_BLANK_START(a) (0x00002070 + (a)*0x00000400) +#define NVC37D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NVC37D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NVC37D_HEAD_SET_OVERSCAN_COLOR(a) (0x00002078 + (a)*0x00000400) +#define NVC37D_HEAD_SET_OVERSCAN_COLOR_RED_CR 9:0 +#define NVC37D_HEAD_SET_OVERSCAN_COLOR_GREEN_Y 19:10 +#define NVC37D_HEAD_SET_OVERSCAN_COLOR_BLUE_CB 29:20 +#define NVC37D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR(a) (0x0000207C + (a)*0x00000400) +#define NVC37D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_RED_CR 9:0 +#define NVC37D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_GREEN_Y 19:10 +#define NVC37D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_BLUE_CB 29:20 +#define NVC37D_HEAD_SET_HDMI_CTRL(a) (0x00002080 + (a)*0x00000400) +#define NVC37D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NVC37D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NVC37D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NVC37D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NVC37D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NVC37D_HEAD_SET_CONTEXT_DMA_CURSOR(a,b) (0x00002088 + (a)*0x00000400 + (b)*0x00000004) +#define NVC37D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0 +#define NVC37D_HEAD_SET_OFFSET_CURSOR(a,b) (0x00002090 + (a)*0x00000400 + (b)*0x00000004) +#define NVC37D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0 +#define NVC37D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x00002098 + (a)*0x00000400) +#define NVC37D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 0:0 +#define NVC37D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NVC37D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_CURSOR(a) (0x0000209C + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_FORMAT 7:0 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE 9:8 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 19:12 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 27:20 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA 29:28 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_NONE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_SRGB (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_YUV8_10 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_YUV12 (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION(a) (0x000020A0 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_K1 7:0 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT 11:8 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT 15:12 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_ZERO (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE 16:16 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_BLEND (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_XOR (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT(a) (0x000020A4 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE 1:0 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_257 (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_1025 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE 5:4 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_UNITY (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_XRBIAS (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_XVYCC (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE 9:8 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE_INDEX (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE_INTERPOLATE (0x00000001) +#define NVC37D_HEAD_SET_OFFSET_OUTPUT_LUT(a) (0x000020A8 + (a)*0x00000400) +#define NVC37D_HEAD_SET_OFFSET_OUTPUT_LUT_ORIGIN 31:0 +#define NVC37D_HEAD_SET_CONTEXT_DMA_OUTPUT_LUT(a) (0x000020AC + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTEXT_DMA_OUTPUT_LUT_HANDLE 31:0 +#define NVC37D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00002180 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NVC37D_HEAD_SET_CRC_CONTROL(a) (0x00002184 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 4:0 +#define NVC37D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 8:8 +#define NVC37D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NVC37D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC 19:12 +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_NONE (0x00000000) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SF (0x00000030) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR__SIZE_1 8 +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR0 (0x00000050) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR1 (0x00000051) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR2 (0x00000052) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR3 (0x00000053) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR4 (0x00000054) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR5 (0x00000055) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR6 (0x00000056) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR7 (0x00000057) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR(i) (0x00000060 +(i)) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR__SIZE_1 4 +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR0 (0x00000060) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR1 (0x00000061) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR2 (0x00000062) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR3 (0x00000063) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC 27:20 +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_NONE (0x00000000) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SF (0x00000030) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR__SIZE_1 8 +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR0 (0x00000050) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR1 (0x00000051) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR2 (0x00000052) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR3 (0x00000053) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR4 (0x00000054) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR5 (0x00000055) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR6 (0x00000056) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR7 (0x00000057) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR(i) (0x00000060 +(i)) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR__SIZE_1 4 +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR0 (0x00000060) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR1 (0x00000061) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR2 (0x00000062) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR3 (0x00000063) +#define NVC37D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 9:9 +#define NVC37D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_PRESENT_CONTROL(a) (0x0000218C + (a)*0x00000400) +#define NVC37D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 0:0 +#define NVC37D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NVC37D_HEAD_SET_SW_SPARE_A(a) (0x00002194 + (a)*0x00000400) +#define NVC37D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NVC37D_HEAD_SET_SW_SPARE_B(a) (0x00002198 + (a)*0x00000400) +#define NVC37D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NVC37D_HEAD_SET_SW_SPARE_C(a) (0x0000219C + (a)*0x00000400) +#define NVC37D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NVC37D_HEAD_SET_SW_SPARE_D(a) (0x000021A0 + (a)*0x00000400) +#define NVC37D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NVC37D_HEAD_SET_DISPLAY_RATE(a) (0x000021A8 + (a)*0x00000400) +#define NVC37D_HEAD_SET_DISPLAY_RATE_RUN_MODE 0:0 +#define NVC37D_HEAD_SET_DISPLAY_RATE_RUN_MODE_CONTINUOUS (0x00000000) +#define NVC37D_HEAD_SET_DISPLAY_RATE_RUN_MODE_ONE_SHOT (0x00000001) +#define NVC37D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_INTERVAL 25:4 +#define NVC37D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH 2:2 +#define NVC37D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_MIN_FRAME_IDLE(a) (0x00002218 + (a)*0x00000400) +#define NVC37D_HEAD_SET_MIN_FRAME_IDLE_LEADING_RASTER_LINES 14:0 +#define NVC37D_HEAD_SET_MIN_FRAME_IDLE_TRAILING_RASTER_LINES 30:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC37d_h diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc37dcrcnotif.h b/userspace/sdks/nv525/nvidia/inc/class/clc37dcrcnotif.h new file mode 100644 index 0000000..88b5b77 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc37dcrcnotif.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2003-2016, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __clc37dcrcnotif_h__ +#define __clc37dcrcnotif_h__ +/* This file is autogenerated. Do not edit */ + +#define NVC37D_NOTIFIER_CRC_STATUS_0 0x00000000 +#define NVC37D_NOTIFIER_CRC_STATUS_0_DONE 0:0 +#define NVC37D_NOTIFIER_CRC_STATUS_0_DONE_FALSE 0x00000000 +#define NVC37D_NOTIFIER_CRC_STATUS_0_DONE_TRUE 0x00000001 +#define NVC37D_NOTIFIER_CRC_STATUS_0_COMPOSITOR_OVERFLOW 3:3 +#define NVC37D_NOTIFIER_CRC_STATUS_0_COMPOSITOR_OVERFLOW_FALSE 0x00000000 +#define NVC37D_NOTIFIER_CRC_STATUS_0_COMPOSITOR_OVERFLOW_TRUE 0x00000001 +#define NVC37D_NOTIFIER_CRC_STATUS_0_RG_OVERFLOW 4:4 +#define NVC37D_NOTIFIER_CRC_STATUS_0_RG_OVERFLOW_FALSE 0x00000000 +#define NVC37D_NOTIFIER_CRC_STATUS_0_RG_OVERFLOW_TRUE 0x00000001 +#define NVC37D_NOTIFIER_CRC_STATUS_0_PRIMARY_OUTPUT_OVERFLOW 5:5 +#define NVC37D_NOTIFIER_CRC_STATUS_0_PRIMARY_OUTPUT_OVERFLOW_FALSE 0x00000000 +#define NVC37D_NOTIFIER_CRC_STATUS_0_PRIMARY_OUTPUT_OVERFLOW_TRUE 0x00000001 +#define NVC37D_NOTIFIER_CRC_STATUS_0_COUNT 27:16 +#define NVC37D_NOTIFIER_CRC_CRC_ENTRY0_11 0x0000000B +#define NVC37D_NOTIFIER_CRC_CRC_ENTRY0_11_COMPOSITOR_CRC 31:0 +#define NVC37D_NOTIFIER_CRC_CRC_ENTRY0_12 0x0000000C +#define NVC37D_NOTIFIER_CRC_CRC_ENTRY0_12_RG_CRC 31:0 +#define NVC37D_NOTIFIER_CRC_CRC_ENTRY0_13 0x0000000D +#define NVC37D_NOTIFIER_CRC_CRC_ENTRY0_13_PRIMARY_OUTPUT_CRC 31:0 +#define NVC37D_NOTIFIER_CRC_CRC_ENTRY1_21 0x00000015 + +#endif // __clc37dcrcnotif_h__ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc37dswspare.h b/userspace/sdks/nv525/nvidia/inc/class/clc37dswspare.h new file mode 100644 index 0000000..44b21a8 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc37dswspare.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc37d_sw_spare_h_ +#define _clc37d_sw_spare_h_ + +/* This file is *not* auto-generated. */ + +#define NVC37D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF 1:0 +#define NVC37D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF_NO_PREF (0x00000000) +#define NVC37D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF_QSYNC (0x00000001) + +#define NVC37D_HEAD_SET_SW_SPARE_A_DISABLE_MID_FRAME_AND_DWCF_WATERMARK 2:2 +#define NVC37D_HEAD_SET_SW_SPARE_A_DISABLE_MID_FRAME_AND_DWCF_WATERMARK_FALSE (0x00000000) +#define NVC37D_HEAD_SET_SW_SPARE_A_DISABLE_MID_FRAME_AND_DWCF_WATERMARK_TRUE (0x00000001) + +#endif // _clc37d_sw_spare_h_ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc37e.h b/userspace/sdks/nv525/nvidia/inc/class/clc37e.h new file mode 100644 index 0000000..f46929a --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc37e.h @@ -0,0 +1,498 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _clC37e_h_ +#define _clC37e_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC37E_WINDOW_CHANNEL_DMA (0x0000C37E) + +// dma opcode instructions +#define NVC37E_DMA +#define NVC37E_DMA_OPCODE 31:29 +#define NVC37E_DMA_OPCODE_METHOD 0x00000000 +#define NVC37E_DMA_OPCODE_JUMP 0x00000001 +#define NVC37E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC37E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC37E_DMA_METHOD_COUNT 27:18 +#define NVC37E_DMA_METHOD_OFFSET 13:2 +#define NVC37E_DMA_DATA 31:0 +#define NVC37E_DMA_DATA_NOP 0x00000000 +#define NVC37E_DMA_JUMP_OFFSET 11:2 +#define NVC37E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVC37E_PUT (0x00000000) +#define NVC37E_PUT_PTR 9:0 +#define NVC37E_GET (0x00000004) +#define NVC37E_GET_PTR 9:0 +#define NVC37E_UPDATE (0x00000200) +#define NVC37E_UPDATE_RELEASE_ELV 0:0 +#define NVC37E_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC37E_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC37E_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM 12:12 +#define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE (0x00000000) +#define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE (0x00000001) +#define NVC37E_GET_LINE (0x00000208) +#define NVC37E_GET_LINE_LINE 15:0 +#define NVC37E_SET_SEMAPHORE_CONTROL (0x0000020C) +#define NVC37E_SET_SEMAPHORE_CONTROL_OFFSET 7:0 +#define NVC37E_SET_SEMAPHORE_ACQUIRE (0x00000210) +#define NVC37E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NVC37E_SET_SEMAPHORE_RELEASE (0x00000214) +#define NVC37E_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NVC37E_SET_CONTEXT_DMA_SEMAPHORE (0x00000218) +#define NVC37E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NVC37E_SET_CONTEXT_DMA_NOTIFIER (0x0000021C) +#define NVC37E_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NVC37E_SET_NOTIFIER_CONTROL (0x00000220) +#define NVC37E_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC37E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC37E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC37E_SET_NOTIFIER_CONTROL_OFFSET 11:4 +#define NVC37E_SET_SIZE (0x00000224) +#define NVC37E_SET_SIZE_WIDTH 15:0 +#define NVC37E_SET_SIZE_HEIGHT 31:16 +#define NVC37E_SET_STORAGE (0x00000228) +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC37E_SET_STORAGE_MEMORY_LAYOUT 4:4 +#define NVC37E_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC37E_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC37E_SET_PARAMS (0x0000022C) +#define NVC37E_SET_PARAMS_FORMAT 7:0 +#define NVC37E_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NVC37E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F) +#define NVC37E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NVC37E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC37E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E) +#define NVC37E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC37E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6) +#define NVC37E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NVC37E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9) +#define NVC37E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NVC37E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NVC37E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NVC37E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024) +#define NVC37E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NVC37E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NVC37E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NVC37E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028) +#define NVC37E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029) +#define NVC37E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035) +#define NVC37E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036) +#define NVC37E_SET_PARAMS_FORMAT_Y8___U8V8_N422R (0x00000037) +#define NVC37E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038) +#define NVC37E_SET_PARAMS_FORMAT_Y8___U8___V8_N444 (0x0000003A) +#define NVC37E_SET_PARAMS_FORMAT_Y8___U8___V8_N420 (0x0000003B) +#define NVC37E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055) +#define NVC37E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056) +#define NVC37E_SET_PARAMS_FORMAT_Y10___U10V10_N422R (0x00000057) +#define NVC37E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058) +#define NVC37E_SET_PARAMS_FORMAT_Y10___U10___V10_N444 (0x0000005A) +#define NVC37E_SET_PARAMS_FORMAT_Y10___U10___V10_N420 (0x0000005B) +#define NVC37E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075) +#define NVC37E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076) +#define NVC37E_SET_PARAMS_FORMAT_Y12___U12V12_N422R (0x00000077) +#define NVC37E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078) +#define NVC37E_SET_PARAMS_FORMAT_Y12___U12___V12_N444 (0x0000007A) +#define NVC37E_SET_PARAMS_FORMAT_Y12___U12___V12_N420 (0x0000007B) +#define NVC37E_SET_PARAMS_COLOR_SPACE 9:8 +#define NVC37E_SET_PARAMS_COLOR_SPACE_RGB (0x00000000) +#define NVC37E_SET_PARAMS_COLOR_SPACE_YUV_601 (0x00000001) +#define NVC37E_SET_PARAMS_COLOR_SPACE_YUV_709 (0x00000002) +#define NVC37E_SET_PARAMS_COLOR_SPACE_YUV_2020 (0x00000003) +#define NVC37E_SET_PARAMS_INPUT_RANGE 13:12 +#define NVC37E_SET_PARAMS_INPUT_RANGE_BYPASS (0x00000000) +#define NVC37E_SET_PARAMS_INPUT_RANGE_LIMITED (0x00000001) +#define NVC37E_SET_PARAMS_INPUT_RANGE_FULL (0x00000002) +#define NVC37E_SET_PARAMS_UNDERREPLICATE 16:16 +#define NVC37E_SET_PARAMS_UNDERREPLICATE_DISABLE (0x00000000) +#define NVC37E_SET_PARAMS_UNDERREPLICATE_ENABLE (0x00000001) +#define NVC37E_SET_PARAMS_DE_GAMMA 21:20 +#define NVC37E_SET_PARAMS_DE_GAMMA_NONE (0x00000000) +#define NVC37E_SET_PARAMS_DE_GAMMA_SRGB (0x00000001) +#define NVC37E_SET_PARAMS_DE_GAMMA_YUV8_10 (0x00000002) +#define NVC37E_SET_PARAMS_DE_GAMMA_YUV12 (0x00000003) +#define NVC37E_SET_PARAMS_CSC 17:17 +#define NVC37E_SET_PARAMS_CSC_DISABLE (0x00000000) +#define NVC37E_SET_PARAMS_CSC_ENABLE (0x00000001) +#define NVC37E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18 +#define NVC37E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000) +#define NVC37E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001) +#define NVC37E_SET_PARAMS_SWAP_UV 19:19 +#define NVC37E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000) +#define NVC37E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001) +#define NVC37E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004) +#define NVC37E_SET_PLANAR_STORAGE_PITCH 12:0 +#define NVC37E_SET_CONTEXT_DMA_ISO(b) (0x00000240 + (b)*0x00000004) +#define NVC37E_SET_CONTEXT_DMA_ISO_HANDLE 31:0 +#define NVC37E_SET_OFFSET(b) (0x00000260 + (b)*0x00000004) +#define NVC37E_SET_OFFSET_ORIGIN 31:0 +#define NVC37E_SET_PROCESSING (0x00000280) +#define NVC37E_SET_PROCESSING_USE_GAIN_OFFSETS 0:0 +#define NVC37E_SET_PROCESSING_USE_GAIN_OFFSETS_DISABLE (0x00000000) +#define NVC37E_SET_PROCESSING_USE_GAIN_OFFSETS_ENABLE (0x00000001) +#define NVC37E_SET_CONVERSION_RED (0x00000284) +#define NVC37E_SET_CONVERSION_RED_GAIN 15:0 +#define NVC37E_SET_CONVERSION_RED_OFFSET 31:16 +#define NVC37E_SET_CONVERSION_GREEN (0x00000288) +#define NVC37E_SET_CONVERSION_GREEN_GAIN 15:0 +#define NVC37E_SET_CONVERSION_GREEN_OFFSET 31:16 +#define NVC37E_SET_CONVERSION_BLUE (0x0000028C) +#define NVC37E_SET_CONVERSION_BLUE_GAIN 15:0 +#define NVC37E_SET_CONVERSION_BLUE_OFFSET 31:16 +#define NVC37E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004) +#define NVC37E_SET_POINT_IN_X 15:0 +#define NVC37E_SET_POINT_IN_Y 31:16 +#define NVC37E_SET_SIZE_IN (0x00000298) +#define NVC37E_SET_SIZE_IN_WIDTH 14:0 +#define NVC37E_SET_SIZE_IN_HEIGHT 30:16 +#define NVC37E_SET_SIZE_OUT (0x000002A4) +#define NVC37E_SET_SIZE_OUT_WIDTH 14:0 +#define NVC37E_SET_SIZE_OUT_HEIGHT 30:16 +#define NVC37E_SET_CONTROL_INPUT_SCALER (0x000002A8) +#define NVC37E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVC37E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVC37E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVC37E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVC37E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVC37E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVC37E_SET_INPUT_SCALER_COEFF_VALUE (0x000002AC) +#define NVC37E_SET_INPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVC37E_SET_INPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVC37E_SET_CONTROL_INPUT_LUT (0x000002B0) +#define NVC37E_SET_CONTROL_INPUT_LUT_SIZE 1:0 +#define NVC37E_SET_CONTROL_INPUT_LUT_SIZE_SIZE_257 (0x00000000) +#define NVC37E_SET_CONTROL_INPUT_LUT_SIZE_SIZE_1025 (0x00000002) +#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE 5:4 +#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE_UNITY (0x00000000) +#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE_XRBIAS (0x00000001) +#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE_XVYCC (0x00000002) +#define NVC37E_SET_CONTROL_INPUT_LUT_OUTPUT_MODE 9:8 +#define NVC37E_SET_CONTROL_INPUT_LUT_OUTPUT_MODE_INDEX (0x00000000) +#define NVC37E_SET_CONTROL_INPUT_LUT_OUTPUT_MODE_INTERPOLATE (0x00000001) +#define NVC37E_SET_OFFSET_INPUT_LUT (0x000002B4) +#define NVC37E_SET_OFFSET_INPUT_LUT_ORIGIN 31:0 +#define NVC37E_SET_CONTEXT_DMA_INPUT_LUT (0x000002B8) +#define NVC37E_SET_CONTEXT_DMA_INPUT_LUT_HANDLE 31:0 +#define NVC37E_SET_CSC_RED2RED (0x000002BC) +#define NVC37E_SET_CSC_RED2RED_COEFF 18:0 +#define NVC37E_SET_CSC_GREEN2RED (0x000002C0) +#define NVC37E_SET_CSC_GREEN2RED_COEFF 18:0 +#define NVC37E_SET_CSC_BLUE2RED (0x000002C4) +#define NVC37E_SET_CSC_BLUE2RED_COEFF 18:0 +#define NVC37E_SET_CSC_CONSTANT2RED (0x000002C8) +#define NVC37E_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NVC37E_SET_CSC_RED2GREEN (0x000002CC) +#define NVC37E_SET_CSC_RED2GREEN_COEFF 18:0 +#define NVC37E_SET_CSC_GREEN2GREEN (0x000002D0) +#define NVC37E_SET_CSC_GREEN2GREEN_COEFF 18:0 +#define NVC37E_SET_CSC_BLUE2GREEN (0x000002D4) +#define NVC37E_SET_CSC_BLUE2GREEN_COEFF 18:0 +#define NVC37E_SET_CSC_CONSTANT2GREEN (0x000002D8) +#define NVC37E_SET_CSC_CONSTANT2GREEN_COEFF 18:0 +#define NVC37E_SET_CSC_RED2BLUE (0x000002DC) +#define NVC37E_SET_CSC_RED2BLUE_COEFF 18:0 +#define NVC37E_SET_CSC_GREEN2BLUE (0x000002E0) +#define NVC37E_SET_CSC_GREEN2BLUE_COEFF 18:0 +#define NVC37E_SET_CSC_BLUE2BLUE (0x000002E4) +#define NVC37E_SET_CSC_BLUE2BLUE_COEFF 18:0 +#define NVC37E_SET_CSC_CONSTANT2BLUE (0x000002E8) +#define NVC37E_SET_CSC_CONSTANT2BLUE_COEFF 18:0 +#define NVC37E_SET_COMPOSITION_CONTROL (0x000002EC) +#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0 +#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000) +#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001) +#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002) +#define NVC37E_SET_COMPOSITION_CONTROL_DEPTH 11:4 +#define NVC37E_SET_COMPOSITION_CONSTANT_ALPHA (0x000002F0) +#define NVC37E_SET_COMPOSITION_CONSTANT_ALPHA_K1 7:0 +#define NVC37E_SET_COMPOSITION_CONSTANT_ALPHA_K2 15:8 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT (0x000002F4) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC37E_SET_KEY_ALPHA (0x000002F8) +#define NVC37E_SET_KEY_ALPHA_MIN 15:0 +#define NVC37E_SET_KEY_ALPHA_MAX 31:16 +#define NVC37E_SET_KEY_RED_CR (0x000002FC) +#define NVC37E_SET_KEY_RED_CR_MIN 15:0 +#define NVC37E_SET_KEY_RED_CR_MAX 31:16 +#define NVC37E_SET_KEY_GREEN_Y (0x00000300) +#define NVC37E_SET_KEY_GREEN_Y_MIN 15:0 +#define NVC37E_SET_KEY_GREEN_Y_MAX 31:16 +#define NVC37E_SET_KEY_BLUE_CB (0x00000304) +#define NVC37E_SET_KEY_BLUE_CB_MIN 15:0 +#define NVC37E_SET_KEY_BLUE_CB_MAX 31:16 +#define NVC37E_SET_PRESENT_CONTROL (0x00000308) +#define NVC37E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NVC37E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4 +#define NVC37E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NVC37E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NVC37E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8 +#define NVC37E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000) +#define NVC37E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001) +#define NVC37E_SET_PRESENT_CONTROL_STEREO_MODE 13:12 +#define NVC37E_SET_PRESENT_CONTROL_STEREO_MODE_MONO (0x00000000) +#define NVC37E_SET_PRESENT_CONTROL_STEREO_MODE_PAIR_FLIP (0x00000001) +#define NVC37E_SET_PRESENT_CONTROL_STEREO_MODE_AT_ANY_FRAME (0x00000002) +#define NVC37E_SET_TIMESTAMP_ORIGIN_LO (0x00000340) +#define NVC37E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NVC37E_SET_TIMESTAMP_ORIGIN_HI (0x00000344) +#define NVC37E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NVC37E_SET_UPDATE_TIMESTAMP_LO (0x00000348) +#define NVC37E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NVC37E_SET_UPDATE_TIMESTAMP_HI (0x0000034C) +#define NVC37E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NVC37E_SET_INTERLOCK_FLAGS (0x00000370) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 0:0 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+1):((i)+1) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 1:1 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 2:2 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 3:3 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 4:4 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 5:5 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 6:6 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 7:7 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 8:8 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS (0x00000374) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC37e_h diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc397.h b/userspace/sdks/nv525/nvidia/inc/class/clc397.h new file mode 100644 index 0000000..2122c75 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc397.h @@ -0,0 +1,4219 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_volta_a_h_ +#define _cl_volta_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl volta_a */ + +#include "nvtypes.h" + +#define VOLTA_A 0xC397 + +#define NVC397_SET_OBJECT 0x0000 +#define NVC397_SET_OBJECT_CLASS_ID 15:0 +#define NVC397_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC397_NO_OPERATION 0x0100 +#define NVC397_NO_OPERATION_V 31:0 + +#define NVC397_SET_NOTIFY_A 0x0104 +#define NVC397_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC397_SET_NOTIFY_B 0x0108 +#define NVC397_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC397_NOTIFY 0x010c +#define NVC397_NOTIFY_TYPE 31:0 +#define NVC397_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC397_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC397_WAIT_FOR_IDLE 0x0110 +#define NVC397_WAIT_FOR_IDLE_V 31:0 + +#define NVC397_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC397_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC397_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC397_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC397_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC397_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC397_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC397_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC397_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC397_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC397_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC397_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC397_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC397_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC397_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC397_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC397_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC397_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC397_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC397_SEND_GO_IDLE 0x013c +#define NVC397_SEND_GO_IDLE_V 31:0 + +#define NVC397_PM_TRIGGER 0x0140 +#define NVC397_PM_TRIGGER_V 31:0 + +#define NVC397_PM_TRIGGER_WFI 0x0144 +#define NVC397_PM_TRIGGER_WFI_V 31:0 + +#define NVC397_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC397_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC397_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC397_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC397_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC397_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC397_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC397_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC397_LINE_LENGTH_IN 0x0180 +#define NVC397_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC397_LINE_COUNT 0x0184 +#define NVC397_LINE_COUNT_VALUE 31:0 + +#define NVC397_OFFSET_OUT_UPPER 0x0188 +#define NVC397_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC397_OFFSET_OUT 0x018c +#define NVC397_OFFSET_OUT_VALUE 31:0 + +#define NVC397_PITCH_OUT 0x0190 +#define NVC397_PITCH_OUT_VALUE 31:0 + +#define NVC397_SET_DST_BLOCK_SIZE 0x0194 +#define NVC397_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC397_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC397_SET_DST_WIDTH 0x0198 +#define NVC397_SET_DST_WIDTH_V 31:0 + +#define NVC397_SET_DST_HEIGHT 0x019c +#define NVC397_SET_DST_HEIGHT_V 31:0 + +#define NVC397_SET_DST_DEPTH 0x01a0 +#define NVC397_SET_DST_DEPTH_V 31:0 + +#define NVC397_SET_DST_LAYER 0x01a4 +#define NVC397_SET_DST_LAYER_V 31:0 + +#define NVC397_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC397_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC397_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC397_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC397_LAUNCH_DMA 0x01b0 +#define NVC397_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC397_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC397_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC397_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC397_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC397_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC397_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC397_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC397_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC397_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC397_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC397_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC397_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC397_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC397_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC397_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC397_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC397_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC397_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC397_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC397_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC397_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC397_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC397_LOAD_INLINE_DATA 0x01b4 +#define NVC397_LOAD_INLINE_DATA_V 31:0 + +#define NVC397_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC397_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC397_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC397_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC397_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC397_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC397_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC397_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC397_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC397_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC397_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC397_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC397_RUN_DS_NOW 0x0200 +#define NVC397_RUN_DS_NOW_V 31:0 + +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC397_SET_GS_MODE 0x0208 +#define NVC397_SET_GS_MODE_TYPE 0:0 +#define NVC397_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVC397_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVC397_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC397_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC397_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC397_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC397_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC397_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_GS_DM_FIFO 0x0214 +#define NVC397_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC397_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC397_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC397_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC397_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC397_INVALIDATE_SHADER_CACHES 0x021c +#define NVC397_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC397_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC397_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC397_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC397_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC397_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC397_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC397_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC397_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC397_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC397_SET_INSTANCE_COUNT 0x0220 +#define NVC397_SET_INSTANCE_COUNT_V 31:0 + +#define NVC397_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVC397_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVC397_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC397_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVC397_SET_MME_VERSION 0x0234 +#define NVC397_SET_MME_VERSION_MAJOR 7:0 + +#define NVC397_INCREMENT_SYNC_POINT 0x02c8 +#define NVC397_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC397_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC397_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC397_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC397_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC397_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC397_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC397_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC397_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVC397_DECOMPRESS_SURFACE 0x02e0 +#define NVC397_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC397_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC397_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC397_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC397_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC397_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC397_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC397_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC397_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC397_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC397_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC397_SET_ZCULL_SUBREGION 0x02e8 +#define NVC397_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC397_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC397_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC397_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC397_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC397_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC397_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC397_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC397_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC397_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC397_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC397_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC397_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC397_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC397_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC397_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC397_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC397_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC397_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC397_DRAW_ZERO_INDEX 0x0304 +#define NVC397_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC397_SET_L1_CONFIGURATION 0x0308 +#define NVC397_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC397_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC397_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC397_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC397_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC397_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC397_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC397_SET_SPA_VERSION 0x0310 +#define NVC397_SET_SPA_VERSION_MINOR 7:0 +#define NVC397_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC397_SET_SNAP_GRID_LINE 0x0318 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC397_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC397_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC397_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC397_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC397_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC397_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC397_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC397_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC397_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC397_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC397_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC397_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC397_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC397_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC397_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC397_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC397_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC397_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC397_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC397_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC397_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC397_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC397_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC397_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC397_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC397_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC397_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC397_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC397_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC397_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC397_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC397_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC397_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC397_RESERVED_TG07 0x033c +#define NVC397_RESERVED_TG07_V 0:0 + +#define NVC397_RESERVED_TG08 0x0340 +#define NVC397_RESERVED_TG08_V 0:0 + +#define NVC397_RESERVED_TG09 0x0344 +#define NVC397_RESERVED_TG09_V 0:0 + +#define NVC397_RESERVED_TG10 0x0348 +#define NVC397_RESERVED_TG10_V 0:0 + +#define NVC397_RESERVED_TG11 0x034c +#define NVC397_RESERVED_TG11_V 0:0 + +#define NVC397_RESERVED_TG12 0x0350 +#define NVC397_RESERVED_TG12_V 0:0 + +#define NVC397_RESERVED_TG13 0x0354 +#define NVC397_RESERVED_TG13_V 0:0 + +#define NVC397_RESERVED_TG14 0x0358 +#define NVC397_RESERVED_TG14_V 0:0 + +#define NVC397_RESERVED_TG15 0x035c +#define NVC397_RESERVED_TG15_V 0:0 + +#define NVC397_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC397_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC397_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC397_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC397_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC397_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC397_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC397_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC397_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC397_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC397_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC397_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC397_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC397_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC397_SET_RASTER_ENABLE 0x037c +#define NVC397_SET_RASTER_ENABLE_V 0:0 +#define NVC397_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC397_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC397_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC397_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC397_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC397_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC397_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC397_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC397_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC397_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC397_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVC397_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVC397_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVC397_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVC397_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVC397_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVC397_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVC397_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVC397_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC397_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC397_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC397_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC397_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC397_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC397_SET_RASTER_INPUT 0x0740 +#define NVC397_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC397_SET_STREAM_OUTPUT 0x0744 +#define NVC397_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC397_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC397_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC397_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC397_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC397_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC397_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC397_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC397_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC397_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC397_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC397_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC397_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC397_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC397_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC397_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC397_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC397_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC397_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC397_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC397_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC397_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC397_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC397_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC397_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC397_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVC397_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC397_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC397_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC397_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC397_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC397_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC397_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC397_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC397_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC397_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC397_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC397_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC397_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC397_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC397_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC397_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC397_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC397_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC397_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC397_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC397_SET_ZCULL_STORAGE_B 0x07ec +#define NVC397_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC397_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC397_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC397_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC397_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC397_SET_ZT_READ_ONLY 0x07f8 +#define NVC397_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC397_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC397_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC397_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC397_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC397_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC397_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC397_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC397_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC397_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC397_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC397_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC397_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC397_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC397_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC397_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC397_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC397_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC397_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC397_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC397_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC397_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC397_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC397_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC397_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC397_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC397_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC397_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC397_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC397_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC397_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC397_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC397_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC397_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC397_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC397_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC397_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC397_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC397_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC397_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC397_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC397_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC397_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC397_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC397_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC397_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC397_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC397_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC397_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC397_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC397_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC397_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC397_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC397_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC397_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC397_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC397_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC397_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC397_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC397_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC397_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC397_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC397_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC397_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC397_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC397_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC397_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC397_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC397_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC397_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC397_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC397_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC397_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC397_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC397_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC397_SET_STATISTICS_COUNTER 0x0d68 +#define NVC397_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC397_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC397_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC397_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC397_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC397_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC397_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC397_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC397_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC397_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC397_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC397_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC397_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC397_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC397_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC397_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC397_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVC397_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC397_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC397_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC397_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC397_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC397_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC397_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC397_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC397_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC397_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC397_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC397_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC397_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC397_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC397_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC397_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC397_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC397_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC397_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC397_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC397_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC397_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC397_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC397_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC397_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC397_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC397_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC397_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC397_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC397_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC397_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC397_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC397_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC397_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC397_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC397_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC397_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC397_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC397_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC397_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC397_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC397_SET_POLY_SMOOTH 0x0db4 +#define NVC397_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC397_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC397_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC397_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC397_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC397_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC397_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC397_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC397_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC397_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_PATCH 0x0dcc +#define NVC397_SET_PATCH_SIZE 7:0 + +#define NVC397_SET_ITERATED_BLEND 0x0dd0 +#define NVC397_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC397_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC397_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC397_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC397_SET_ZCULL_CRITERION 0x0dd8 +#define NVC397_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC397_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC397_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC397_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC397_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC397_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC397_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC397_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC397_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC397_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC397_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC397_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC397_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC397_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC397_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC397_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC397_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC397_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC397_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC397_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC397_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC397_SET_SCISSOR_ENABLE_V 0:0 +#define NVC397_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC397_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC397_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC397_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC397_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC397_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC397_SET_VPC_PERF_KNOB 0x0f14 +#define NVC397_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC397_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC397_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC397_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC397_PM_LOCAL_TRIGGER 0x0f18 +#define NVC397_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC397_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC397_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC397_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC397_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC397_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC397_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC397_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC397_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC397_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC397_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC397_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC397_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC397_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC397_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC397_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC397_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC397_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC397_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC397_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC397_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC397_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC397_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC397_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC397_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC397_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC397_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC397_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC397_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC397_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC397_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC397_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC397_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC397_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC397_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC397_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC397_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC397_SET_SAMPLE_MASK 0x0fa4 +#define NVC397_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC397_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC397_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC397_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC397_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC397_SET_CT_MRT_ENABLE 0x0fac +#define NVC397_SET_CT_MRT_ENABLE_V 0:0 +#define NVC397_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC397_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC397_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC397_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC397_SET_TIR 0x0fb4 +#define NVC397_SET_TIR_MODE 1:0 +#define NVC397_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC397_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC397_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC397_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC397_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC397_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC397_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC397_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC397_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC397_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC397_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC397_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC397_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC397_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC397_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC397_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC397_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC397_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC397_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC397_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_TIR_MODULATION 0x0fd4 +#define NVC397_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC397_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC397_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC397_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC397_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC397_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC397_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC397_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC397_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC397_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC397_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC397_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC397_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC397_SET_ZT_A 0x0fe0 +#define NVC397_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_ZT_B 0x0fe4 +#define NVC397_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_ZT_FORMAT 0x0fe8 +#define NVC397_SET_ZT_FORMAT_V 4:0 +#define NVC397_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC397_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC397_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC397_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC397_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC397_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC397_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC397_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC397_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC397_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC397_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC397_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC397_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC397_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC397_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC397_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC397_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC397_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC397_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC397_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC397_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC397_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC397_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC397_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC397_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC397_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC397_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC397_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC397_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC397_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC397_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC397_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC397_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC397_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC397_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC397_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC397_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC397_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC397_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC397_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC397_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC397_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC397_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC397_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC397_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC397_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD02 0x102c +#define NVC397_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC397_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC397_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC397_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC397_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC397_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC397_SET_SPARE_NOOP01 0x1044 +#define NVC397_SET_SPARE_NOOP01_V 31:0 + +#define NVC397_SET_SPARE_NOOP02 0x1048 +#define NVC397_SET_SPARE_NOOP02_V 31:0 + +#define NVC397_SET_SPARE_NOOP03 0x104c +#define NVC397_SET_SPARE_NOOP03_V 31:0 + +#define NVC397_SET_SPARE_NOOP04 0x1050 +#define NVC397_SET_SPARE_NOOP04_V 31:0 + +#define NVC397_SET_SPARE_NOOP05 0x1054 +#define NVC397_SET_SPARE_NOOP05_V 31:0 + +#define NVC397_SET_SPARE_NOOP06 0x1058 +#define NVC397_SET_SPARE_NOOP06_V 31:0 + +#define NVC397_SET_SPARE_NOOP07 0x105c +#define NVC397_SET_SPARE_NOOP07_V 31:0 + +#define NVC397_SET_SPARE_NOOP08 0x1060 +#define NVC397_SET_SPARE_NOOP08_V 31:0 + +#define NVC397_SET_SPARE_NOOP09 0x1064 +#define NVC397_SET_SPARE_NOOP09_V 31:0 + +#define NVC397_SET_SPARE_NOOP10 0x1068 +#define NVC397_SET_SPARE_NOOP10_V 31:0 + +#define NVC397_SET_SPARE_NOOP11 0x106c +#define NVC397_SET_SPARE_NOOP11_V 31:0 + +#define NVC397_SET_SPARE_NOOP12 0x1070 +#define NVC397_SET_SPARE_NOOP12_V 31:0 + +#define NVC397_SET_SPARE_NOOP13 0x1074 +#define NVC397_SET_SPARE_NOOP13_V 31:0 + +#define NVC397_SET_SPARE_NOOP14 0x1078 +#define NVC397_SET_SPARE_NOOP14_V 31:0 + +#define NVC397_SET_SPARE_NOOP15 0x107c +#define NVC397_SET_SPARE_NOOP15_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC397_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC397_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC397_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC397_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC397_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC397_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC397_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC397_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC397_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC397_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC397_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC397_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC397_UNBIND_ALL 0x10f4 +#define NVC397_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC397_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC397_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC397_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC397_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC397_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC397_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC397_NO_OPERATION_DATA_HI 0x110c +#define NVC397_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC397_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC397_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC397_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC397_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC397_PM_TRIGGER_END 0x1114 +#define NVC397_PM_TRIGGER_END_V 31:0 + +#define NVC397_SET_VERTEX_ID_BASE 0x1118 +#define NVC397_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC397_SET_STENCIL_COMPRESSION 0x111c +#define NVC397_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC397_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC397_SET_TIR_CONTROL 0x1130 +#define NVC397_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC397_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC397_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC397_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC397_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC397_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC397_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC397_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC397_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 + +#define NVC397_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC397_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC397_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC397_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC397_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC397_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC397_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC397_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC397_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC397_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC397_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC397_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC397_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC397_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC397_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC397_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC397_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC397_FLUSH_PENDING_WRITES 0x1144 +#define NVC397_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC397_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC397_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC397_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC397_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC397_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC397_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC397_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC397_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC397_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC397_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC397_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC397_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC397_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC397_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC397_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC397_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC397_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC397_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC397_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC397_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC397_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC397_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_SCREEN_STATE_MASK 0x1204 +#define NVC397_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC397_SET_ZT_SPARSE 0x1208 +#define NVC397_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC397_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC397_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC397_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC397_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC397_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_SET_CT_SELECT 0x121c +#define NVC397_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC397_SET_CT_SELECT_TARGET0 6:4 +#define NVC397_SET_CT_SELECT_TARGET1 9:7 +#define NVC397_SET_CT_SELECT_TARGET2 12:10 +#define NVC397_SET_CT_SELECT_TARGET3 15:13 +#define NVC397_SET_CT_SELECT_TARGET4 18:16 +#define NVC397_SET_CT_SELECT_TARGET5 21:19 +#define NVC397_SET_CT_SELECT_TARGET6 24:22 +#define NVC397_SET_CT_SELECT_TARGET7 27:25 + +#define NVC397_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC397_SET_ZT_SIZE_A 0x1228 +#define NVC397_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC397_SET_ZT_SIZE_B 0x122c +#define NVC397_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC397_SET_ZT_SIZE_C 0x1230 +#define NVC397_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC397_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC397_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC397_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC397_SET_SAMPLER_BINDING 0x1234 +#define NVC397_SET_SAMPLER_BINDING_V 0:0 +#define NVC397_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC397_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC397_DRAW_AUTO 0x123c +#define NVC397_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC397_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC397_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC397_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC397_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC397_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC397_SET_BACK_END_COPY_A 0x1264 +#define NVC397_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC397_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC397_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC397_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC397_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BACK_END_COPY_B 0x1268 +#define NVC397_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC397_SET_BACK_END_COPY_C 0x126c +#define NVC397_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC397_SET_BACK_END_COPY_D 0x1270 +#define NVC397_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC397_SET_BACK_END_COPY_E 0x1274 +#define NVC397_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC397_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC397_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVC397_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC397_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC397_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC397_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC397_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC397_CLEAR_ZCULL_REGION 0x12c8 +#define NVC397_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC397_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC397_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC397_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC397_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC397_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC397_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC397_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC397_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC397_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC397_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC397_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC397_SET_DEPTH_TEST 0x12cc +#define NVC397_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC397_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC397_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_FILL_MODE 0x12d0 +#define NVC397_SET_FILL_MODE_V 31:0 +#define NVC397_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC397_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC397_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC397_SET_SHADE_MODE 0x12d4 +#define NVC397_SET_SHADE_MODE_V 31:0 +#define NVC397_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC397_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC397_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC397_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC397_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC397_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC397_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC397_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC397_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC397_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC397_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC397_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_DEPTH_WRITE 0x12e8 +#define NVC397_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC397_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_ALPHA_TEST 0x12ec +#define NVC397_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC397_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC397_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC397_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC397_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC397_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC397_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC397_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC397_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC397_D3D_SET_CULL_MODE 0x1308 +#define NVC397_D3D_SET_CULL_MODE_V 31:0 +#define NVC397_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC397_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC397_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC397_SET_DEPTH_FUNC 0x130c +#define NVC397_SET_DEPTH_FUNC_V 31:0 +#define NVC397_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC397_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC397_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC397_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC397_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC397_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC397_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC397_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC397_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC397_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC397_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC397_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC397_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC397_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC397_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC397_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC397_SET_ALPHA_REF 0x1310 +#define NVC397_SET_ALPHA_REF_V 31:0 + +#define NVC397_SET_ALPHA_FUNC 0x1314 +#define NVC397_SET_ALPHA_FUNC_V 31:0 +#define NVC397_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC397_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC397_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC397_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC397_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC397_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC397_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC397_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC397_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC397_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC397_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC397_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC397_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC397_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC397_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC397_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC397_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC397_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC397_SET_BLEND_CONST_RED 0x131c +#define NVC397_SET_BLEND_CONST_RED_V 31:0 + +#define NVC397_SET_BLEND_CONST_GREEN 0x1320 +#define NVC397_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC397_SET_BLEND_CONST_BLUE 0x1324 +#define NVC397_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC397_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC397_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC397_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC397_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC397_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC397_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC397_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC397_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC397_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC397_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BLEND_COLOR_OP 0x1340 +#define NVC397_SET_BLEND_COLOR_OP_V 31:0 +#define NVC397_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC397_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC397_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC397_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC397_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC397_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC397_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC397_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC397_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC397_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_BLEND_ALPHA_OP 0x134c +#define NVC397_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC397_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC397_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC397_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC397_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC397_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC397_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC397_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC397_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC397_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC397_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC397_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC397_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC397_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC397_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC397_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BLEND(i) (0x1360+(i)*4) +#define NVC397_SET_BLEND_ENABLE 0:0 +#define NVC397_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_STENCIL_TEST 0x1380 +#define NVC397_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC397_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_STENCIL_OP_FAIL 0x1384 +#define NVC397_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC397_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC397_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC397_SET_STENCIL_OP_ZPASS 0x138c +#define NVC397_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC397_SET_STENCIL_FUNC 0x1390 +#define NVC397_SET_STENCIL_FUNC_V 31:0 +#define NVC397_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC397_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC397_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC397_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC397_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC397_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC397_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC397_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC397_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC397_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC397_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC397_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC397_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC397_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC397_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC397_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC397_SET_STENCIL_FUNC_REF 0x1394 +#define NVC397_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC397_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC397_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC397_SET_STENCIL_MASK 0x139c +#define NVC397_SET_STENCIL_MASK_V 7:0 + +#define NVC397_SET_DRAW_AUTO_START 0x13a4 +#define NVC397_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC397_SET_PS_SATURATE 0x13a8 +#define NVC397_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC397_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC397_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC397_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC397_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC397_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC397_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC397_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC397_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC397_SET_WINDOW_ORIGIN 0x13ac +#define NVC397_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC397_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC397_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC397_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC397_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC397_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC397_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC397_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC397_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC397_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC397_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC397_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC397_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC397_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC397_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC397_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC397_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC397_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC397_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC397_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC397_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC397_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC397_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC397_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC397_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC397_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC397_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC397_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC397_STORE_ZCULL 0x1464 +#define NVC397_STORE_ZCULL_V 0:0 + +#define NVC397_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC397_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC397_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC397_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC397_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC397_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC397_LOAD_ZCULL 0x1500 +#define NVC397_LOAD_ZCULL_V 0:0 + +#define NVC397_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC397_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC397_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC397_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC397_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC397_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC397_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC397_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC397_SET_USER_CLIP_ENABLE 0x1510 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC397_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC397_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC397_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_POINT_SIZE 0x1518 +#define NVC397_SET_POINT_SIZE_V 31:0 + +#define NVC397_SET_ZCULL_STATS 0x151c +#define NVC397_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC397_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_POINT_SPRITE 0x1520 +#define NVC397_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC397_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC397_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC397_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC397_CLEAR_REPORT_VALUE 0x1530 +#define NVC397_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC397_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC397_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC397_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC397_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC397_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC397_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVC397_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC397_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC397_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_ZT_SELECT 0x1538 +#define NVC397_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC397_SET_RENDER_ENABLE_A 0x1550 +#define NVC397_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_RENDER_ENABLE_B 0x1554 +#define NVC397_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_RENDER_ENABLE_C 0x1558 +#define NVC397_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC397_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC397_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC397_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC397_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC397_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC397_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC397_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC397_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC397_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC397_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC397_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC397_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC397_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC397_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC397_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC397_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_TEX_HEADER_POOL_C 0x157c +#define NVC397_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC397_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC397_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC397_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC397_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC397_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC397_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC397_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC397_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC397_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC397_SET_SRGB_WRITE 0x15b8 +#define NVC397_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC397_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_DEPTH_BIAS 0x15bc +#define NVC397_SET_DEPTH_BIAS_V 31:0 + +#define NVC397_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC397_SET_RT_LAYER 0x15cc +#define NVC397_SET_RT_LAYER_V 15:0 +#define NVC397_SET_RT_LAYER_CONTROL 16:16 +#define NVC397_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC397_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC397_SET_ANTI_ALIAS 0x15d0 +#define NVC397_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC397_SET_EDGE_FLAG 0x15e4 +#define NVC397_SET_EDGE_FLAG_V 0:0 +#define NVC397_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC397_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC397_DRAW_INLINE_INDEX 0x15e8 +#define NVC397_DRAW_INLINE_INDEX_V 31:0 + +#define NVC397_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC397_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC397_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC397_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC397_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC397_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC397_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC397_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC397_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC397_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC397_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC397_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC397_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC397_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC397_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC397_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC397_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC397_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC397_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC397_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC397_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC397_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC397_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC397_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC397_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC397_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC397_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC397_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC397_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC397_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC397_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC397_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC397_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC397_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC397_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC397_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC397_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC397_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC397_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC397_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC397_END 0x1614 +#define NVC397_END_V 0:0 + +#define NVC397_BEGIN 0x1618 +#define NVC397_BEGIN_OP 15:0 +#define NVC397_BEGIN_OP_POINTS 0x00000000 +#define NVC397_BEGIN_OP_LINES 0x00000001 +#define NVC397_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC397_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC397_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC397_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC397_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC397_BEGIN_OP_QUADS 0x00000007 +#define NVC397_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC397_BEGIN_OP_POLYGON 0x00000009 +#define NVC397_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC397_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC397_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_BEGIN_OP_PATCH 0x0000000E +#define NVC397_BEGIN_PRIMITIVE_ID 24:24 +#define NVC397_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC397_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC397_BEGIN_INSTANCE_ID 27:26 +#define NVC397_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC397_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC397_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC397_BEGIN_SPLIT_MODE 30:29 +#define NVC397_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC397_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC397_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC397_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC397_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVC397_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC397_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_VERTEX_ID_COPY 0x161c +#define NVC397_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC397_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC397_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC397_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC397_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC397_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC397_LOAD_PRIMITIVE_ID 0x1624 +#define NVC397_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC397_SET_SHADER_BASED_CULL 0x162c +#define NVC397_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC397_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC397_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC397_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_CLASS_VERSION 0x1638 +#define NVC397_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC397_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC397_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC397_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC397_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC397_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC397_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC397_SET_DA_OUTPUT 0x164c +#define NVC397_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC397_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC397_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC397_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC397_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_POINT_CENTER_MODE 0x165c +#define NVC397_SET_POINT_CENTER_MODE_V 31:0 +#define NVC397_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC397_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC397_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC397_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC397_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC397_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC397_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC397_SET_LINE_STIPPLE 0x166c +#define NVC397_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC397_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC397_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC397_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC397_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC397_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC397_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC397_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC397_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC397_SET_PROVOKING_VERTEX 0x1684 +#define NVC397_SET_PROVOKING_VERTEX_V 0:0 +#define NVC397_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC397_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC397_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC397_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC397_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_POLYGON_STIPPLE 0x168c +#define NVC397_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC397_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_SHADER_CONTROL 0x1690 +#define NVC397_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC397_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC397_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC397_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC397_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC397_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC397_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC397_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC397_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC397_CHECK_CLASS_VERSION 0x16a0 +#define NVC397_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC397_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC397_SET_SPH_VERSION 0x16a4 +#define NVC397_SET_SPH_VERSION_CURRENT 15:0 +#define NVC397_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC397_CHECK_SPH_VERSION 0x16a8 +#define NVC397_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC397_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC397_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC397_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC397_SET_AAM_VERSION 0x1790 +#define NVC397_SET_AAM_VERSION_CURRENT 15:0 +#define NVC397_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC397_CHECK_AAM_VERSION 0x1794 +#define NVC397_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC397_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC397_SET_ZT_LAYER 0x179c +#define NVC397_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC397_SET_INDEX_BUFFER_A 0x17c8 +#define NVC397_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC397_SET_INDEX_BUFFER_B 0x17cc +#define NVC397_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC397_SET_INDEX_BUFFER_C 0x17d0 +#define NVC397_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC397_SET_INDEX_BUFFER_D 0x17d4 +#define NVC397_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC397_SET_INDEX_BUFFER_E 0x17d8 +#define NVC397_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC397_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC397_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC397_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC397_SET_INDEX_BUFFER_F 0x17dc +#define NVC397_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC397_DRAW_INDEX_BUFFER 0x17e0 +#define NVC397_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC397_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC397_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC397_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC397_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC397_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC397_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC397_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC397_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC397_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC397_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC397_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC397_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC397_OGL_SET_CULL 0x1918 +#define NVC397_OGL_SET_CULL_ENABLE 0:0 +#define NVC397_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC397_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC397_OGL_SET_FRONT_FACE 0x191c +#define NVC397_OGL_SET_FRONT_FACE_V 31:0 +#define NVC397_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC397_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC397_OGL_SET_CULL_FACE 0x1920 +#define NVC397_OGL_SET_CULL_FACE_V 31:0 +#define NVC397_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC397_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC397_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC397_SET_VIEWPORT_PIXEL 0x1924 +#define NVC397_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC397_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC397_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC397_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC397_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC397_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC397_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE 17:16 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_USE_FIELD_MIN_Z_ZERO_MAX_Z_ONE 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MIN_Z_MAX_Z 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_ZERO_ONE 0x00000002 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MINUS_INF_PLUS_INF 0x00000003 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC397_SET_USER_CLIP_OP 0x1940 +#define NVC397_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC397_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC397_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC397_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC397_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC397_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC397_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC397_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC397_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC397_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC397_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC397_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC397_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC397_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC397_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC397_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC397_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC397_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC397_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC397_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC397_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC397_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC397_INVALIDATE_ZCULL 0x1958 +#define NVC397_INVALIDATE_ZCULL_V 31:0 +#define NVC397_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC397_SET_ZCULL 0x1968 +#define NVC397_SET_ZCULL_Z_ENABLE 0:0 +#define NVC397_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC397_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_ZCULL_BOUNDS 0x196c +#define NVC397_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC397_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC397_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC397_ZCULL_SYNC 0x1978 +#define NVC397_ZCULL_SYNC_V 31:0 + +#define NVC397_SET_CLIP_ID_TEST 0x197c +#define NVC397_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC397_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC397_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC397_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC397_SET_CLIP_ID 0x1984 +#define NVC397_SET_CLIP_ID_V 31:0 + +#define NVC397_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC397_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC397_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC397_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC397_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC397_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC397_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC397_SET_LOGIC_OP 0x19c4 +#define NVC397_SET_LOGIC_OP_ENABLE 0:0 +#define NVC397_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC397_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC397_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC397_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC397_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC397_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC397_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC397_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC397_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC397_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC397_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC397_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC397_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC397_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC397_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC397_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC397_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC397_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC397_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC397_SET_Z_COMPRESSION 0x19cc +#define NVC397_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC397_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC397_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC397_CLEAR_SURFACE 0x19d0 +#define NVC397_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC397_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC397_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC397_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC397_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC397_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC397_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC397_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC397_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC397_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC397_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC397_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC397_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC397_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC397_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC397_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC397_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC397_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC397_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC397_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC397_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC397_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC397_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC397_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC397_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC397_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC397_PIPE_NOP 0x1a2c +#define NVC397_PIPE_NOP_V 31:0 + +#define NVC397_SET_SPARE00 0x1a30 +#define NVC397_SET_SPARE00_V 31:0 + +#define NVC397_SET_SPARE01 0x1a34 +#define NVC397_SET_SPARE01_V 31:0 + +#define NVC397_SET_SPARE02 0x1a38 +#define NVC397_SET_SPARE02_V 31:0 + +#define NVC397_SET_SPARE03 0x1a3c +#define NVC397_SET_SPARE03_V 31:0 + +#define NVC397_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC397_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC397_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC397_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC397_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC397_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC397_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC397_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC397_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC397_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC397_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC397_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC397_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC397_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC397_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC397_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC397_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC397_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC397_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC397_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC397_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC397_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC397_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC397_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC397_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC397_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC397_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC397_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC397_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC397_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC397_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC397_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC397_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC397_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVC397_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVC397_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVC397_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVC397_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVC397_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVC397_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVC397_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVC397_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC397_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC397_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC397_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC397_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC397_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC397_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC397_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC397_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC397_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC397_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC397_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC397_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC397_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC397_SET_PIPELINE_REGISTER_COUNT_V 8:0 + +#define NVC397_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC397_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC397_SET_PIPELINE_PROGRAM_ADDRESS_A(j) (0x2014+(j)*64) +#define NVC397_SET_PIPELINE_PROGRAM_ADDRESS_A_UPPER 7:0 + +#define NVC397_SET_PIPELINE_PROGRAM_ADDRESS_B(j) (0x2018+(j)*64) +#define NVC397_SET_PIPELINE_PROGRAM_ADDRESS_B_LOWER 31:0 + +#define NVC397_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVC397_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVC397_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC397_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC397_SET_FALCON00 0x2300 +#define NVC397_SET_FALCON00_V 31:0 + +#define NVC397_SET_FALCON01 0x2304 +#define NVC397_SET_FALCON01_V 31:0 + +#define NVC397_SET_FALCON02 0x2308 +#define NVC397_SET_FALCON02_V 31:0 + +#define NVC397_SET_FALCON03 0x230c +#define NVC397_SET_FALCON03_V 31:0 + +#define NVC397_SET_FALCON04 0x2310 +#define NVC397_SET_FALCON04_V 31:0 + +#define NVC397_SET_FALCON05 0x2314 +#define NVC397_SET_FALCON05_V 31:0 + +#define NVC397_SET_FALCON06 0x2318 +#define NVC397_SET_FALCON06_V 31:0 + +#define NVC397_SET_FALCON07 0x231c +#define NVC397_SET_FALCON07_V 31:0 + +#define NVC397_SET_FALCON08 0x2320 +#define NVC397_SET_FALCON08_V 31:0 + +#define NVC397_SET_FALCON09 0x2324 +#define NVC397_SET_FALCON09_V 31:0 + +#define NVC397_SET_FALCON10 0x2328 +#define NVC397_SET_FALCON10_V 31:0 + +#define NVC397_SET_FALCON11 0x232c +#define NVC397_SET_FALCON11_V 31:0 + +#define NVC397_SET_FALCON12 0x2330 +#define NVC397_SET_FALCON12_V 31:0 + +#define NVC397_SET_FALCON13 0x2334 +#define NVC397_SET_FALCON13_V 31:0 + +#define NVC397_SET_FALCON14 0x2338 +#define NVC397_SET_FALCON14_V 31:0 + +#define NVC397_SET_FALCON15 0x233c +#define NVC397_SET_FALCON15_V 31:0 + +#define NVC397_SET_FALCON16 0x2340 +#define NVC397_SET_FALCON16_V 31:0 + +#define NVC397_SET_FALCON17 0x2344 +#define NVC397_SET_FALCON17_V 31:0 + +#define NVC397_SET_FALCON18 0x2348 +#define NVC397_SET_FALCON18_V 31:0 + +#define NVC397_SET_FALCON19 0x234c +#define NVC397_SET_FALCON19_V 31:0 + +#define NVC397_SET_FALCON20 0x2350 +#define NVC397_SET_FALCON20_V 31:0 + +#define NVC397_SET_FALCON21 0x2354 +#define NVC397_SET_FALCON21_V 31:0 + +#define NVC397_SET_FALCON22 0x2358 +#define NVC397_SET_FALCON22_V 31:0 + +#define NVC397_SET_FALCON23 0x235c +#define NVC397_SET_FALCON23_V 31:0 + +#define NVC397_SET_FALCON24 0x2360 +#define NVC397_SET_FALCON24_V 31:0 + +#define NVC397_SET_FALCON25 0x2364 +#define NVC397_SET_FALCON25_V 31:0 + +#define NVC397_SET_FALCON26 0x2368 +#define NVC397_SET_FALCON26_V 31:0 + +#define NVC397_SET_FALCON27 0x236c +#define NVC397_SET_FALCON27_V 31:0 + +#define NVC397_SET_FALCON28 0x2370 +#define NVC397_SET_FALCON28_V 31:0 + +#define NVC397_SET_FALCON29 0x2374 +#define NVC397_SET_FALCON29_V 31:0 + +#define NVC397_SET_FALCON30 0x2378 +#define NVC397_SET_FALCON30_V 31:0 + +#define NVC397_SET_FALCON31 0x237c +#define NVC397_SET_FALCON31_V 31:0 + +#define NVC397_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC397_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC397_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC397_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC397_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC397_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC397_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC397_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC397_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC397_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC397_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC397_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC397_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC397_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC397_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC397_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC397_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC397_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC397_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC397_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC397_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC397_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC397_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC397_SET_TRAP_HANDLER_A 0x25f8 +#define NVC397_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC397_SET_TRAP_HANDLER_B 0x25fc +#define NVC397_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC397_SET_COLOR_CLAMP 0x2600 +#define NVC397_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC397_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC397_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BINDLESS_TEXTURE 0x2608 +#define NVC397_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVC397_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC397_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC397_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC397_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC397_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC397_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC397_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC397_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC397_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC397_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC397_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC397_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC397_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC397_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC397_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC397_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC397_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC397_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC397_CALL_MME_MACRO_V 31:0 + +#define NVC397_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC397_CALL_MME_DATA_V 31:0 + +#endif /* _cl_volta_a_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc3b0.h b/userspace/sdks/nv525/nvidia/inc/class/clc3b0.h new file mode 100644 index 0000000..5ccaedd --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc3b0.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _clc3b0_h_ +#define _clc3b0_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC3B0_VIDEO_DECODER (0x0000C3B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc3b0_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc3b5.h b/userspace/sdks/nv525/nvidia/inc/class/clc3b5.h new file mode 100644 index 0000000..74ee1b7 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc3b5.h @@ -0,0 +1,278 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clc3b5_h_ +#define _clc3b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define VOLTA_DMA_COPY_A (0x0000C3B5) + +#define NVC3B5_NOP (0x00000100) +#define NVC3B5_NOP_PARAMETER 31:0 +#define NVC3B5_PM_TRIGGER (0x00000140) +#define NVC3B5_PM_TRIGGER_V 31:0 +#define NVC3B5_SET_SEMAPHORE_A (0x00000240) +#define NVC3B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC3B5_SET_SEMAPHORE_B (0x00000244) +#define NVC3B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC3B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC3B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC3B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC3B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC3B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC3B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC3B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC3B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC3B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC3B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC3B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC3B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC3B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC3B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC3B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC3B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC3B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC3B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC3B5_SET_SRC_PHYS_MODE_BASIC_KIND 5:2 +#define NVC3B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC3B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC3B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC3B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC3B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC3B5_SET_DST_PHYS_MODE_BASIC_KIND 5:2 +#define NVC3B5_LAUNCH_DMA (0x00000300) +#define NVC3B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC3B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC3B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC3B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC3B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC3B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC3B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC3B5_LAUNCH_DMA_FLUSH_TYPE 25:25 +#define NVC3B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000) +#define NVC3B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC3B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC3B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC3B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC3B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC3B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC3B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC3B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC3B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC3B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC3B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC3B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC3B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC3B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC3B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC3B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC3B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC3B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC3B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC3B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC3B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC3B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC3B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC3B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC3B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC3B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC3B5_LAUNCH_DMA_SRC_BYPASS_L2 20:20 +#define NVC3B5_LAUNCH_DMA_SRC_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC3B5_LAUNCH_DMA_SRC_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC3B5_LAUNCH_DMA_DST_BYPASS_L2 21:21 +#define NVC3B5_LAUNCH_DMA_DST_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC3B5_LAUNCH_DMA_DST_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC3B5_LAUNCH_DMA_VPRMODE 23:22 +#define NVC3B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVC3B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC3B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC3B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 +#define NVC3B5_OFFSET_IN_UPPER (0x00000400) +#define NVC3B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC3B5_OFFSET_IN_LOWER (0x00000404) +#define NVC3B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC3B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC3B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC3B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC3B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC3B5_PITCH_IN (0x00000410) +#define NVC3B5_PITCH_IN_VALUE 31:0 +#define NVC3B5_PITCH_OUT (0x00000414) +#define NVC3B5_PITCH_OUT_VALUE 31:0 +#define NVC3B5_LINE_LENGTH_IN (0x00000418) +#define NVC3B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC3B5_LINE_COUNT (0x0000041C) +#define NVC3B5_LINE_COUNT_VALUE 31:0 +#define NVC3B5_SET_REMAP_CONST_A (0x00000700) +#define NVC3B5_SET_REMAP_CONST_A_V 31:0 +#define NVC3B5_SET_REMAP_CONST_B (0x00000704) +#define NVC3B5_SET_REMAP_CONST_B_V 31:0 +#define NVC3B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC3B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC3B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC3B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC3B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC3B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC3B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC3B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC3B5_SET_DST_WIDTH (0x00000710) +#define NVC3B5_SET_DST_WIDTH_V 31:0 +#define NVC3B5_SET_DST_HEIGHT (0x00000714) +#define NVC3B5_SET_DST_HEIGHT_V 31:0 +#define NVC3B5_SET_DST_DEPTH (0x00000718) +#define NVC3B5_SET_DST_DEPTH_V 31:0 +#define NVC3B5_SET_DST_LAYER (0x0000071C) +#define NVC3B5_SET_DST_LAYER_V 31:0 +#define NVC3B5_SET_DST_ORIGIN (0x00000720) +#define NVC3B5_SET_DST_ORIGIN_X 15:0 +#define NVC3B5_SET_DST_ORIGIN_Y 31:16 +#define NVC3B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC3B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC3B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC3B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC3B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC3B5_SET_SRC_WIDTH (0x0000072C) +#define NVC3B5_SET_SRC_WIDTH_V 31:0 +#define NVC3B5_SET_SRC_HEIGHT (0x00000730) +#define NVC3B5_SET_SRC_HEIGHT_V 31:0 +#define NVC3B5_SET_SRC_DEPTH (0x00000734) +#define NVC3B5_SET_SRC_DEPTH_V 31:0 +#define NVC3B5_SET_SRC_LAYER (0x00000738) +#define NVC3B5_SET_SRC_LAYER_V 31:0 +#define NVC3B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC3B5_SET_SRC_ORIGIN_X 15:0 +#define NVC3B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC3B5_SRC_ORIGIN_X (0x00000744) +#define NVC3B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC3B5_SRC_ORIGIN_Y (0x00000748) +#define NVC3B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC3B5_DST_ORIGIN_X (0x0000074C) +#define NVC3B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC3B5_DST_ORIGIN_Y (0x00000750) +#define NVC3B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC3B5_PM_TRIGGER_END (0x00001114) +#define NVC3B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc3b5_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc3b5sw.h b/userspace/sdks/nv525/nvidia/inc/class/clc3b5sw.h new file mode 100644 index 0000000..b913984 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc3b5sw.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc3b5sw.finn +// + + + +// +// Using VERSION_0 will cause the API to interpret +// engineType as a CE engine instance. This allows +// for backward compatibility with 85B5sw and 90B5sw. +// +#define NVC3B5_ALLOCATION_PARAMETERS_VERSION_0 0 + +// +// Using VERSION_1 will cause the API to interpret +// engineType as an NV2080_ENGINE_TYPE ordinal. +// +#define NVC3B5_ALLOCATION_PARAMETERS_VERSION_1 1 + +#define NVC3B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc3b5U) + +typedef struct NVC3B5_ALLOCATION_PARAMETERS { + NvU32 version; + NvU32 engineType; +} NVC3B5_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc3b7.h b/userspace/sdks/nv525/nvidia/inc/class/clc3b7.h new file mode 100644 index 0000000..0a313b8 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc3b7.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clc3b7_h +#define clc3b7_h + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC3B7_VIDEO_ENCODER (0x0000C3B7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc3b7_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc3c0.h b/userspace/sdks/nv525/nvidia/inc/class/clc3c0.h new file mode 100644 index 0000000..76b4566 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc3c0.h @@ -0,0 +1,703 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_volta_compute_a_h_ +#define _cl_volta_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl volta_compute_a */ + +#include "nvtypes.h" + +#define VOLTA_COMPUTE_A 0xC3C0 + +#define NVC3C0_SET_OBJECT 0x0000 +#define NVC3C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC3C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC3C0_NO_OPERATION 0x0100 +#define NVC3C0_NO_OPERATION_V 31:0 + +#define NVC3C0_SET_NOTIFY_A 0x0104 +#define NVC3C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC3C0_SET_NOTIFY_B 0x0108 +#define NVC3C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC3C0_NOTIFY 0x010c +#define NVC3C0_NOTIFY_TYPE 31:0 +#define NVC3C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC3C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC3C0_WAIT_FOR_IDLE 0x0110 +#define NVC3C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC3C0_SEND_GO_IDLE 0x013c +#define NVC3C0_SEND_GO_IDLE_V 31:0 + +#define NVC3C0_PM_TRIGGER 0x0140 +#define NVC3C0_PM_TRIGGER_V 31:0 + +#define NVC3C0_PM_TRIGGER_WFI 0x0144 +#define NVC3C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC3C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC3C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC3C0_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC3C0_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC3C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC3C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC3C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC3C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC3C0_LINE_LENGTH_IN 0x0180 +#define NVC3C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC3C0_LINE_COUNT 0x0184 +#define NVC3C0_LINE_COUNT_VALUE 31:0 + +#define NVC3C0_OFFSET_OUT_UPPER 0x0188 +#define NVC3C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC3C0_OFFSET_OUT 0x018c +#define NVC3C0_OFFSET_OUT_VALUE 31:0 + +#define NVC3C0_PITCH_OUT 0x0190 +#define NVC3C0_PITCH_OUT_VALUE 31:0 + +#define NVC3C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC3C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC3C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC3C0_SET_DST_WIDTH 0x0198 +#define NVC3C0_SET_DST_WIDTH_V 31:0 + +#define NVC3C0_SET_DST_HEIGHT 0x019c +#define NVC3C0_SET_DST_HEIGHT_V 31:0 + +#define NVC3C0_SET_DST_DEPTH 0x01a0 +#define NVC3C0_SET_DST_DEPTH_V 31:0 + +#define NVC3C0_SET_DST_LAYER 0x01a4 +#define NVC3C0_SET_DST_LAYER_V 31:0 + +#define NVC3C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC3C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC3C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC3C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC3C0_LAUNCH_DMA 0x01b0 +#define NVC3C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC3C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC3C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC3C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC3C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC3C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC3C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC3C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC3C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC3C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC3C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC3C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC3C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC3C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC3C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC3C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC3C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC3C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC3C0_LOAD_INLINE_DATA 0x01b4 +#define NVC3C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC3C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC3C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC3C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC3C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC3C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC3C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC3C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC3C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC3C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC3C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC3C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC3C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC3C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC3C0_PERFMON_TRANSFER 0x0210 +#define NVC3C0_PERFMON_TRANSFER_V 31:0 + +#define NVC3C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC3C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC3C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC3C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC3C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC3C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC3C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC3C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC3C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC3C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC3C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC3C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC3C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC3C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC3C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC3C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC3C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC3C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC3C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC3C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC3C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC3C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC3C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC3C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC3C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC3C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC3C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC3C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC3C0_SET_SCG_CONTROL 0x0270 +#define NVC3C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 +#define NVC3C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 +#define NVC3C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 +#define NVC3C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 +#define NVC3C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 + +#define NVC3C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC3C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC3C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC3C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC3C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC3C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC3C0_SET_QMD_VERSION 0x0288 +#define NVC3C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC3C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC3C0_CHECK_QMD_VERSION 0x0290 +#define NVC3C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC3C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC3C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC3C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC3C0_SCG_HYSTERESIS_CONTROL 0x02a8 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 + +#define NVC3C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC3C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC3C0_SEND_PCAS_A 0x02b4 +#define NVC3C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC3C0_SEND_PCAS_B 0x02b8 +#define NVC3C0_SEND_PCAS_B_FROM 23:0 +#define NVC3C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC3C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC3C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC3C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC3C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC3C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC3C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC3C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC3C0_SET_SKED_CACHE_CONTROL 0x02cc +#define NVC3C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID 0:0 +#define NVC3C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE 0x00000000 +#define NVC3C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE 0x00000001 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC3C0_SET_SPA_VERSION 0x0310 +#define NVC3C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC3C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC3C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC3C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC3C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC3C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC3C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC3C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC3C0_SET_FALCON00 0x0500 +#define NVC3C0_SET_FALCON00_V 31:0 + +#define NVC3C0_SET_FALCON01 0x0504 +#define NVC3C0_SET_FALCON01_V 31:0 + +#define NVC3C0_SET_FALCON02 0x0508 +#define NVC3C0_SET_FALCON02_V 31:0 + +#define NVC3C0_SET_FALCON03 0x050c +#define NVC3C0_SET_FALCON03_V 31:0 + +#define NVC3C0_SET_FALCON04 0x0510 +#define NVC3C0_SET_FALCON04_V 31:0 + +#define NVC3C0_SET_FALCON05 0x0514 +#define NVC3C0_SET_FALCON05_V 31:0 + +#define NVC3C0_SET_FALCON06 0x0518 +#define NVC3C0_SET_FALCON06_V 31:0 + +#define NVC3C0_SET_FALCON07 0x051c +#define NVC3C0_SET_FALCON07_V 31:0 + +#define NVC3C0_SET_FALCON08 0x0520 +#define NVC3C0_SET_FALCON08_V 31:0 + +#define NVC3C0_SET_FALCON09 0x0524 +#define NVC3C0_SET_FALCON09_V 31:0 + +#define NVC3C0_SET_FALCON10 0x0528 +#define NVC3C0_SET_FALCON10_V 31:0 + +#define NVC3C0_SET_FALCON11 0x052c +#define NVC3C0_SET_FALCON11_V 31:0 + +#define NVC3C0_SET_FALCON12 0x0530 +#define NVC3C0_SET_FALCON12_V 31:0 + +#define NVC3C0_SET_FALCON13 0x0534 +#define NVC3C0_SET_FALCON13_V 31:0 + +#define NVC3C0_SET_FALCON14 0x0538 +#define NVC3C0_SET_FALCON14_V 31:0 + +#define NVC3C0_SET_FALCON15 0x053c +#define NVC3C0_SET_FALCON15_V 31:0 + +#define NVC3C0_SET_FALCON16 0x0540 +#define NVC3C0_SET_FALCON16_V 31:0 + +#define NVC3C0_SET_FALCON17 0x0544 +#define NVC3C0_SET_FALCON17_V 31:0 + +#define NVC3C0_SET_FALCON18 0x0548 +#define NVC3C0_SET_FALCON18_V 31:0 + +#define NVC3C0_SET_FALCON19 0x054c +#define NVC3C0_SET_FALCON19_V 31:0 + +#define NVC3C0_SET_FALCON20 0x0550 +#define NVC3C0_SET_FALCON20_V 31:0 + +#define NVC3C0_SET_FALCON21 0x0554 +#define NVC3C0_SET_FALCON21_V 31:0 + +#define NVC3C0_SET_FALCON22 0x0558 +#define NVC3C0_SET_FALCON22_V 31:0 + +#define NVC3C0_SET_FALCON23 0x055c +#define NVC3C0_SET_FALCON23_V 31:0 + +#define NVC3C0_SET_FALCON24 0x0560 +#define NVC3C0_SET_FALCON24_V 31:0 + +#define NVC3C0_SET_FALCON25 0x0564 +#define NVC3C0_SET_FALCON25_V 31:0 + +#define NVC3C0_SET_FALCON26 0x0568 +#define NVC3C0_SET_FALCON26_V 31:0 + +#define NVC3C0_SET_FALCON27 0x056c +#define NVC3C0_SET_FALCON27_V 31:0 + +#define NVC3C0_SET_FALCON28 0x0570 +#define NVC3C0_SET_FALCON28_V 31:0 + +#define NVC3C0_SET_FALCON29 0x0574 +#define NVC3C0_SET_FALCON29_V 31:0 + +#define NVC3C0_SET_FALCON30 0x0578 +#define NVC3C0_SET_FALCON30_V 31:0 + +#define NVC3C0_SET_FALCON31 0x057c +#define NVC3C0_SET_FALCON31_V 31:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC3C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC3C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC3C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC3C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC3C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC3C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC3C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC3C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC3C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC3C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC3C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC3C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC3C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC3C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC3C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC3C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC3C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC3C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC3C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC3C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC3C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC3C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC3C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC3C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC3C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC3C0_PIPE_NOP 0x1a2c +#define NVC3C0_PIPE_NOP_V 31:0 + +#define NVC3C0_SET_SPARE00 0x1a30 +#define NVC3C0_SET_SPARE00_V 31:0 + +#define NVC3C0_SET_SPARE01 0x1a34 +#define NVC3C0_SET_SPARE01_V 31:0 + +#define NVC3C0_SET_SPARE02 0x1a38 +#define NVC3C0_SET_SPARE02_V 31:0 + +#define NVC3C0_SET_SPARE03 0x1a3c +#define NVC3C0_SET_SPARE03_V 31:0 + +#define NVC3C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC3C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC3C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC3C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC3C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC3C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC3C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC3C0_SET_TRAP_HANDLER_A 0x25f8 +#define NVC3C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC3C0_SET_TRAP_HANDLER_B 0x25fc +#define NVC3C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC3C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC3C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC3C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC3C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC3C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC3C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC3C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC3C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC3C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC3C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC3C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC3C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_volta_compute_a_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc461.h b/userspace/sdks/nv525/nvidia/inc/class/clc461.h new file mode 100644 index 0000000..0c0378f --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc461.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc461_h_ +#define _clc461_h_ + +#define TURING_USERMODE_A (0xc461) + +#endif // _clc461_h_ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc46f.h b/userspace/sdks/nv525/nvidia/inc/class/clc46f.h new file mode 100644 index 0000000..fb1c594 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc46f.h @@ -0,0 +1,365 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc46f_h_ +#define _clc46f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class TURING_CHANNEL_GPFIFO */ +/* + * Documentation for TURING_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + * Note there is no .mfs file for this class. + */ +#define TURING_CHANNEL_GPFIFO_A (0x0000C46F) + +#define NVC46F_TYPEDEF TURING_CHANNELChannelGPFifoA + +/* dma flow control data structure */ +typedef volatile struct Nvc46fControl_struct { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} Nvc46fControl, TuringAControlGPFifo; + +/* fields and values */ +#define NVC46F_NUMBER_OF_SUBCHANNELS (8) +#define NVC46F_SET_OBJECT (0x00000000) +#define NVC46F_SET_OBJECT_NVCLASS 15:0 +#define NVC46F_SET_OBJECT_ENGINE 20:16 +#define NVC46F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVC46F_ILLEGAL (0x00000004) +#define NVC46F_ILLEGAL_HANDLE 31:0 +#define NVC46F_NOP (0x00000008) +#define NVC46F_NOP_HANDLE 31:0 +#define NVC46F_SEMAPHOREA (0x00000010) +#define NVC46F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVC46F_SEMAPHOREB (0x00000014) +#define NVC46F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVC46F_SEMAPHOREC (0x00000018) +#define NVC46F_SEMAPHOREC_PAYLOAD 31:0 +#define NVC46F_SEMAPHORED (0x0000001C) +#define NVC46F_SEMAPHORED_OPERATION 4:0 +#define NVC46F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVC46F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVC46F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVC46F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVC46F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 +#define NVC46F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVC46F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVC46F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVC46F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVC46F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVC46F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVC46F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVC46F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVC46F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVC46F_SEMAPHORED_REDUCTION 30:27 +#define NVC46F_SEMAPHORED_REDUCTION_MIN 0x00000000 +#define NVC46F_SEMAPHORED_REDUCTION_MAX 0x00000001 +#define NVC46F_SEMAPHORED_REDUCTION_XOR 0x00000002 +#define NVC46F_SEMAPHORED_REDUCTION_AND 0x00000003 +#define NVC46F_SEMAPHORED_REDUCTION_OR 0x00000004 +#define NVC46F_SEMAPHORED_REDUCTION_ADD 0x00000005 +#define NVC46F_SEMAPHORED_REDUCTION_INC 0x00000006 +#define NVC46F_SEMAPHORED_REDUCTION_DEC 0x00000007 +#define NVC46F_SEMAPHORED_FORMAT 31:31 +#define NVC46F_SEMAPHORED_FORMAT_SIGNED 0x00000000 +#define NVC46F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 +#define NVC46F_NON_STALL_INTERRUPT (0x00000020) +#define NVC46F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVC46F_FB_FLUSH (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR +#define NVC46F_FB_FLUSH_HANDLE 31:0 +// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for +// specifying the page address for a targeted TLB invalidate and the uTLB for +// a targeted REPLAY_CANCEL for UVM. +// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly +// rearranged fields. +#define NVC46F_MEM_OP_A (0x00000028) +#define NVC46F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC46F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type +#define NVC46F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC46F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID 6:0 // only relevant for REPLAY_CANCEL_VA_GLOBAL +#define NVC46F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11 +#define NVC46F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001 +#define NVC46F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000 +#define NVC46F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12 +#define NVC46F_MEM_OP_B (0x0000002c) +#define NVC46F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0 +#define NVC46F_MEM_OP_C (0x00000030) +#define NVC46F_MEM_OP_C_MEMBAR_TYPE 2:0 +#define NVC46F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000 +#define NVC46F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE 9:7 //only relevant for REPLAY_CANCEL_VA_GLOBAL +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ 0 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE 1 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG 2 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD 3 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK 4 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL 5 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC 6 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL 7 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE +#define NVC46F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG 19:0 +// MEM_OP_D MUST be preceded by MEM_OPs A-C. +#define NVC46F_MEM_OP_D (0x00000034) +#define NVC46F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE +#define NVC46F_MEM_OP_D_OPERATION 31:27 +#define NVC46F_MEM_OP_D_OPERATION_MEMBAR 0x00000005 +#define NVC46F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVC46F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a +#define NVC46F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NVC46F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +// CLEAN_LINES is an alias for Tegra/GPU IP usage +#define NVC46F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e +#define NVC46F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVC46F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVC46F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015 +#define NVC46F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR 0x00000016 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE 1:0 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC 0x00000000 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC 0x00000001 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL 0x00000002 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED 0x00000003 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE 2:2 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC 0x00000000 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC 0x00000001 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK 6:3 +#define NVC46F_SET_REFERENCE (0x00000050) +#define NVC46F_SET_REFERENCE_COUNT 31:0 +#define NVC46F_SEM_ADDR_LO (0x0000005c) +#define NVC46F_SEM_ADDR_LO_OFFSET 31:2 +#define NVC46F_SEM_ADDR_HI (0x00000060) +#define NVC46F_SEM_ADDR_HI_OFFSET 7:0 +#define NVC46F_SEM_PAYLOAD_LO (0x00000064) +#define NVC46F_SEM_PAYLOAD_LO_PAYLOAD 31:0 +#define NVC46F_SEM_PAYLOAD_HI (0x00000068) +#define NVC46F_SEM_PAYLOAD_HI_PAYLOAD 31:0 +#define NVC46F_SEM_EXECUTE (0x0000006c) +#define NVC46F_SEM_EXECUTE_OPERATION 2:0 +#define NVC46F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000 +#define NVC46F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001 +#define NVC46F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ 0x00000002 +#define NVC46F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003 +#define NVC46F_SEM_EXECUTE_OPERATION_ACQ_AND 0x00000004 +#define NVC46F_SEM_EXECUTE_OPERATION_ACQ_NOR 0x00000005 +#define NVC46F_SEM_EXECUTE_OPERATION_REDUCTION 0x00000006 +#define NVC46F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12 +#define NVC46F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS 0x00000000 +#define NVC46F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001 +#define NVC46F_SEM_EXECUTE_RELEASE_WFI 20:20 +#define NVC46F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000 +#define NVC46F_SEM_EXECUTE_RELEASE_WFI_EN 0x00000001 +#define NVC46F_SEM_EXECUTE_PAYLOAD_SIZE 24:24 +#define NVC46F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000 +#define NVC46F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT 0x00000001 +#define NVC46F_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25 +#define NVC46F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000 +#define NVC46F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001 +#define NVC46F_SEM_EXECUTE_REDUCTION 30:27 +#define NVC46F_SEM_EXECUTE_REDUCTION_IMIN 0x00000000 +#define NVC46F_SEM_EXECUTE_REDUCTION_IMAX 0x00000001 +#define NVC46F_SEM_EXECUTE_REDUCTION_IXOR 0x00000002 +#define NVC46F_SEM_EXECUTE_REDUCTION_IAND 0x00000003 +#define NVC46F_SEM_EXECUTE_REDUCTION_IOR 0x00000004 +#define NVC46F_SEM_EXECUTE_REDUCTION_IADD 0x00000005 +#define NVC46F_SEM_EXECUTE_REDUCTION_INC 0x00000006 +#define NVC46F_SEM_EXECUTE_REDUCTION_DEC 0x00000007 +#define NVC46F_SEM_EXECUTE_REDUCTION_FORMAT 31:31 +#define NVC46F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000000 +#define NVC46F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000001 +#define NVC46F_WFI (0x00000078) +#define NVC46F_WFI_SCOPE 0:0 +#define NVC46F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000 +#define NVC46F_WFI_SCOPE_CURRENT_VEID 0x00000000 +#define NVC46F_WFI_SCOPE_ALL 0x00000001 +#define NVC46F_CRC_CHECK (0x0000007c) +#define NVC46F_CRC_CHECK_VALUE 31:0 +#define NVC46F_YIELD (0x00000080) +#define NVC46F_YIELD_OP 1:0 +#define NVC46F_YIELD_OP_NOP 0x00000000 +#define NVC46F_YIELD_OP_RUNLIST_TIMESLICE 0x00000002 +#define NVC46F_YIELD_OP_TSG 0x00000003 +#define NVC46F_CLEAR_FAULTED (0x00000084) +// Note: RM provides the HANDLE as an opaque value; the internal detail fields +// are intentionally not exposed to the driver through these defines. +#define NVC46F_CLEAR_FAULTED_HANDLE 30:0 +#define NVC46F_CLEAR_FAULTED_TYPE 31:31 +#define NVC46F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED 0x00000000 +#define NVC46F_CLEAR_FAULTED_TYPE_ENG_FAULTED 0x00000001 + + +/* GPFIFO entry format */ +#define NVC46F_GP_ENTRY__SIZE 8 +#define NVC46F_GP_ENTRY0_FETCH 0:0 +#define NVC46F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVC46F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVC46F_GP_ENTRY0_GET 31:2 +#define NVC46F_GP_ENTRY0_OPERAND 31:0 +#define NVC46F_GP_ENTRY1_GET_HI 7:0 +#define NVC46F_GP_ENTRY1_LEVEL 9:9 +#define NVC46F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVC46F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVC46F_GP_ENTRY1_LENGTH 30:10 +#define NVC46F_GP_ENTRY1_SYNC 31:31 +#define NVC46F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVC46F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVC46F_GP_ENTRY1_OPCODE 7:0 +#define NVC46F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVC46F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVC46F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVC46F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVC46F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVC46F_DMA_METHOD_ADDRESS 11:0 +#define NVC46F_DMA_SUBDEVICE_MASK 15:4 +#define NVC46F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVC46F_DMA_TERT_OP 17:16 +#define NVC46F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVC46F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVC46F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVC46F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVC46F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVC46F_DMA_METHOD_COUNT_OLD 28:18 +#define NVC46F_DMA_METHOD_COUNT 28:16 +#define NVC46F_DMA_IMMD_DATA 28:16 +#define NVC46F_DMA_SEC_OP 31:29 +#define NVC46F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVC46F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVC46F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVC46F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVC46F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVC46F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVC46F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVC46F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVC46F_DMA_INCR_ADDRESS 11:0 +#define NVC46F_DMA_INCR_SUBCHANNEL 15:13 +#define NVC46F_DMA_INCR_COUNT 28:16 +#define NVC46F_DMA_INCR_OPCODE 31:29 +#define NVC46F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVC46F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVC46F_DMA_NONINCR_ADDRESS 11:0 +#define NVC46F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVC46F_DMA_NONINCR_COUNT 28:16 +#define NVC46F_DMA_NONINCR_OPCODE 31:29 +#define NVC46F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVC46F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVC46F_DMA_ONEINCR_ADDRESS 11:0 +#define NVC46F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVC46F_DMA_ONEINCR_COUNT 28:16 +#define NVC46F_DMA_ONEINCR_OPCODE 31:29 +#define NVC46F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVC46F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVC46F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVC46F_DMA_IMMD_ADDRESS 11:0 +#define NVC46F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVC46F_DMA_IMMD_DATA 28:16 +#define NVC46F_DMA_IMMD_OPCODE 31:29 +#define NVC46F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVC46F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVC46F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC46F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVC46F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVC46F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC46F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVC46F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC46F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVC46F_DMA_ENDSEG_OPCODE 31:29 +#define NVC46F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVC46F_DMA_ADDRESS 12:2 +#define NVC46F_DMA_SUBCH 15:13 +#define NVC46F_DMA_OPCODE3 17:16 +#define NVC46F_DMA_OPCODE3_NONE (0x00000000) +#define NVC46F_DMA_COUNT 28:18 +#define NVC46F_DMA_OPCODE 31:29 +#define NVC46F_DMA_OPCODE_METHOD (0x00000000) +#define NVC46F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVC46F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc46f_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc46fsw.h b/userspace/sdks/nv525/nvidia/inc/class/clc46fsw.h new file mode 100644 index 0000000..7438195 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc46fsw.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* This file is *not* auto-generated. */ + +#ifndef _clc46f_sw_h_ +#define _clc46f_sw_h_ + +#define NVC46F_NOTIFIERS_RC (0) +#define NVC46F_NOTIFIERS_REFCNT (1) +#define NVC46F_NOTIFIERS_NONSTALL (2) +#define NVC46F_NOTIFIERS_EVENTBUFFER (3) +#define NVC46F_NOTIFIERS_IDLECHANNEL (4) +#define NVC46F_NOTIFIERS_ENDCTX (5) +#define NVC46F_NOTIFIERS_SW (6) +#define NVC46F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVC46F_NOTIFIERS_REPLAYABLE_FAULT (8) +#define NVC46F_NOTIFIERS_MAXCOUNT (9) + +/* NvNotification[] fields and values */ +#define NVC46F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVC46F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _clc46f_sw_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc4b0.h b/userspace/sdks/nv525/nvidia/inc/class/clc4b0.h new file mode 100644 index 0000000..4b7d335 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc4b0.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clc4b0_h_ +#define clc4b0_h_ + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC4B0_VIDEO_DECODER (0x0000C4B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc4b0_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc4b7.h b/userspace/sdks/nv525/nvidia/inc/class/clc4b7.h new file mode 100644 index 0000000..27f3983 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc4b7.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clc4b7_h_ +#define clc4b7_h_ + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC4B7_VIDEO_ENCODER (0x0000C4B7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc4b7_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc4c0.h b/userspace/sdks/nv525/nvidia/inc/class/clc4c0.h new file mode 100644 index 0000000..f96026c --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc4c0.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_volta_compute_b_h_ +#define _cl_volta_compute_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl volta_compute_b */ + +#include "nvtypes.h" + +#define VOLTA_COMPUTE_B 0xC4C0 + +#endif /* _cl_volta_compute_b_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc4d1.h b/userspace/sdks/nv525/nvidia/inc/class/clc4d1.h new file mode 100644 index 0000000..196b034 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc4d1.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "nvtypes.h" + +#ifndef _clc4d1_h_ +#define _clc4d1_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC4D1_VIDEO_NVJPG (0x0000C4D1) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc4d1_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc561.h b/userspace/sdks/nv525/nvidia/inc/class/clc561.h new file mode 100644 index 0000000..83a9339 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc561.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc561_h_ +#define _clc561_h_ + +#define AMPERE_USERMODE_A (0xc561) + +#endif // _clc561_h_ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc56f.h b/userspace/sdks/nv525/nvidia/inc/class/clc56f.h new file mode 100644 index 0000000..bc8b675 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc56f.h @@ -0,0 +1,367 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc56f_h_ +#define _clc56f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class AMPERE_CHANNEL_GPFIFO */ +/* + * Documentation for AMPERE_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + * Note there is no .mfs file for this class. + */ +#define AMPERE_CHANNEL_GPFIFO_A (0x0000C56F) + +#define NVC56F_TYPEDEF AMPERE_CHANNELChannelGPFifoA + +/* dma flow control data structure */ +typedef volatile struct Nvc56fControl_struct { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} Nvc56fControl, AmpereAControlGPFifo; + +/* fields and values */ +#define NVC56F_NUMBER_OF_SUBCHANNELS (8) +#define NVC56F_SET_OBJECT (0x00000000) +#define NVC56F_SET_OBJECT_NVCLASS 15:0 +#define NVC56F_SET_OBJECT_ENGINE 20:16 +#define NVC56F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVC56F_ILLEGAL (0x00000004) +#define NVC56F_ILLEGAL_HANDLE 31:0 +#define NVC56F_NOP (0x00000008) +#define NVC56F_NOP_HANDLE 31:0 +#define NVC56F_SEMAPHOREA (0x00000010) +#define NVC56F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVC56F_SEMAPHOREB (0x00000014) +#define NVC56F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVC56F_SEMAPHOREC (0x00000018) +#define NVC56F_SEMAPHOREC_PAYLOAD 31:0 +#define NVC56F_SEMAPHORED (0x0000001C) +#define NVC56F_SEMAPHORED_OPERATION 4:0 +#define NVC56F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVC56F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVC56F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVC56F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVC56F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 +#define NVC56F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVC56F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVC56F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVC56F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVC56F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVC56F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVC56F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVC56F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVC56F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVC56F_SEMAPHORED_REDUCTION 30:27 +#define NVC56F_SEMAPHORED_REDUCTION_MIN 0x00000000 +#define NVC56F_SEMAPHORED_REDUCTION_MAX 0x00000001 +#define NVC56F_SEMAPHORED_REDUCTION_XOR 0x00000002 +#define NVC56F_SEMAPHORED_REDUCTION_AND 0x00000003 +#define NVC56F_SEMAPHORED_REDUCTION_OR 0x00000004 +#define NVC56F_SEMAPHORED_REDUCTION_ADD 0x00000005 +#define NVC56F_SEMAPHORED_REDUCTION_INC 0x00000006 +#define NVC56F_SEMAPHORED_REDUCTION_DEC 0x00000007 +#define NVC56F_SEMAPHORED_FORMAT 31:31 +#define NVC56F_SEMAPHORED_FORMAT_SIGNED 0x00000000 +#define NVC56F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 +#define NVC56F_NON_STALL_INTERRUPT (0x00000020) +#define NVC56F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVC56F_FB_FLUSH (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR +#define NVC56F_FB_FLUSH_HANDLE 31:0 +// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for +// specifying the page address for a targeted TLB invalidate and the uTLB for +// a targeted REPLAY_CANCEL for UVM. +// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly +// rearranged fields. +#define NVC56F_MEM_OP_A (0x00000028) +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE 7:6 // only relevant for invalidates with NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE for invalidating link TLB only, or non-link TLB only or all TLBs +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS 0 +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS 1 +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS 2 +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD 3 +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID 6:0 // only relevant for REPLAY_CANCEL_VA_GLOBAL +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11 +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001 +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000 +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12 +#define NVC56F_MEM_OP_B (0x0000002c) +#define NVC56F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0 +#define NVC56F_MEM_OP_C (0x00000030) +#define NVC56F_MEM_OP_C_MEMBAR_TYPE 2:0 +#define NVC56F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000 +#define NVC56F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE 9:7 //only relevant for REPLAY_CANCEL_VA_GLOBAL +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ 0 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE 1 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG 2 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD 3 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK 4 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL 5 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC 6 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL 7 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE +#define NVC56F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG 19:0 +// MEM_OP_D MUST be preceded by MEM_OPs A-C. +#define NVC56F_MEM_OP_D (0x00000034) +#define NVC56F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE +#define NVC56F_MEM_OP_D_OPERATION 31:27 +#define NVC56F_MEM_OP_D_OPERATION_MEMBAR 0x00000005 +#define NVC56F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVC56F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a +#define NVC56F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NVC56F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +// CLEAN_LINES is an alias for Tegra/GPU IP usage +#define NVC56F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e +#define NVC56F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVC56F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVC56F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015 +#define NVC56F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR 0x00000016 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE 1:0 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC 0x00000000 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC 0x00000001 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL 0x00000002 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED 0x00000003 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE 2:2 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC 0x00000000 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC 0x00000001 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK 6:3 +#define NVC56F_SET_REFERENCE (0x00000050) +#define NVC56F_SET_REFERENCE_COUNT 31:0 +#define NVC56F_SEM_ADDR_LO (0x0000005c) +#define NVC56F_SEM_ADDR_LO_OFFSET 31:2 +#define NVC56F_SEM_ADDR_HI (0x00000060) +#define NVC56F_SEM_ADDR_HI_OFFSET 7:0 +#define NVC56F_SEM_PAYLOAD_LO (0x00000064) +#define NVC56F_SEM_PAYLOAD_LO_PAYLOAD 31:0 +#define NVC56F_SEM_PAYLOAD_HI (0x00000068) +#define NVC56F_SEM_PAYLOAD_HI_PAYLOAD 31:0 +#define NVC56F_SEM_EXECUTE (0x0000006c) +#define NVC56F_SEM_EXECUTE_OPERATION 2:0 +#define NVC56F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000 +#define NVC56F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001 +#define NVC56F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ 0x00000002 +#define NVC56F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003 +#define NVC56F_SEM_EXECUTE_OPERATION_ACQ_AND 0x00000004 +#define NVC56F_SEM_EXECUTE_OPERATION_ACQ_NOR 0x00000005 +#define NVC56F_SEM_EXECUTE_OPERATION_REDUCTION 0x00000006 +#define NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12 +#define NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS 0x00000000 +#define NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001 +#define NVC56F_SEM_EXECUTE_RELEASE_WFI 20:20 +#define NVC56F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000 +#define NVC56F_SEM_EXECUTE_RELEASE_WFI_EN 0x00000001 +#define NVC56F_SEM_EXECUTE_PAYLOAD_SIZE 24:24 +#define NVC56F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000 +#define NVC56F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT 0x00000001 +#define NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25 +#define NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000 +#define NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001 +#define NVC56F_SEM_EXECUTE_REDUCTION 30:27 +#define NVC56F_SEM_EXECUTE_REDUCTION_IMIN 0x00000000 +#define NVC56F_SEM_EXECUTE_REDUCTION_IMAX 0x00000001 +#define NVC56F_SEM_EXECUTE_REDUCTION_IXOR 0x00000002 +#define NVC56F_SEM_EXECUTE_REDUCTION_IAND 0x00000003 +#define NVC56F_SEM_EXECUTE_REDUCTION_IOR 0x00000004 +#define NVC56F_SEM_EXECUTE_REDUCTION_IADD 0x00000005 +#define NVC56F_SEM_EXECUTE_REDUCTION_INC 0x00000006 +#define NVC56F_SEM_EXECUTE_REDUCTION_DEC 0x00000007 +#define NVC56F_SEM_EXECUTE_REDUCTION_FORMAT 31:31 +#define NVC56F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000000 +#define NVC56F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000001 +#define NVC56F_WFI (0x00000078) +#define NVC56F_WFI_SCOPE 0:0 +#define NVC56F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000 +#define NVC56F_WFI_SCOPE_CURRENT_VEID 0x00000000 +#define NVC56F_WFI_SCOPE_ALL 0x00000001 +#define NVC56F_YIELD (0x00000080) +#define NVC56F_YIELD_OP 1:0 +#define NVC56F_YIELD_OP_NOP 0x00000000 +#define NVC56F_YIELD_OP_TSG 0x00000003 +#define NVC56F_CLEAR_FAULTED (0x00000084) +// Note: RM provides the HANDLE as an opaque value; the internal detail fields +// are intentionally not exposed to the driver through these defines. +#define NVC56F_CLEAR_FAULTED_HANDLE 30:0 +#define NVC56F_CLEAR_FAULTED_TYPE 31:31 +#define NVC56F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED 0x00000000 +#define NVC56F_CLEAR_FAULTED_TYPE_ENG_FAULTED 0x00000001 + + +/* GPFIFO entry format */ +#define NVC56F_GP_ENTRY__SIZE 8 +#define NVC56F_GP_ENTRY0_FETCH 0:0 +#define NVC56F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVC56F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVC56F_GP_ENTRY0_GET 31:2 +#define NVC56F_GP_ENTRY0_OPERAND 31:0 +#define NVC56F_GP_ENTRY1_GET_HI 7:0 +#define NVC56F_GP_ENTRY1_LEVEL 9:9 +#define NVC56F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVC56F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVC56F_GP_ENTRY1_LENGTH 30:10 +#define NVC56F_GP_ENTRY1_SYNC 31:31 +#define NVC56F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVC56F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVC56F_GP_ENTRY1_OPCODE 7:0 +#define NVC56F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVC56F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVC56F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVC56F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVC56F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVC56F_DMA_METHOD_ADDRESS 11:0 +#define NVC56F_DMA_SUBDEVICE_MASK 15:4 +#define NVC56F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVC56F_DMA_TERT_OP 17:16 +#define NVC56F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVC56F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVC56F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVC56F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVC56F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVC56F_DMA_METHOD_COUNT_OLD 28:18 +#define NVC56F_DMA_METHOD_COUNT 28:16 +#define NVC56F_DMA_IMMD_DATA 28:16 +#define NVC56F_DMA_SEC_OP 31:29 +#define NVC56F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVC56F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVC56F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVC56F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVC56F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVC56F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVC56F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVC56F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVC56F_DMA_INCR_ADDRESS 11:0 +#define NVC56F_DMA_INCR_SUBCHANNEL 15:13 +#define NVC56F_DMA_INCR_COUNT 28:16 +#define NVC56F_DMA_INCR_OPCODE 31:29 +#define NVC56F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVC56F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVC56F_DMA_NONINCR_ADDRESS 11:0 +#define NVC56F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVC56F_DMA_NONINCR_COUNT 28:16 +#define NVC56F_DMA_NONINCR_OPCODE 31:29 +#define NVC56F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVC56F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVC56F_DMA_ONEINCR_ADDRESS 11:0 +#define NVC56F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVC56F_DMA_ONEINCR_COUNT 28:16 +#define NVC56F_DMA_ONEINCR_OPCODE 31:29 +#define NVC56F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVC56F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVC56F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVC56F_DMA_IMMD_ADDRESS 11:0 +#define NVC56F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVC56F_DMA_IMMD_DATA 28:16 +#define NVC56F_DMA_IMMD_OPCODE 31:29 +#define NVC56F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVC56F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVC56F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC56F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVC56F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVC56F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC56F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVC56F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC56F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVC56F_DMA_ENDSEG_OPCODE 31:29 +#define NVC56F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVC56F_DMA_ADDRESS 12:2 +#define NVC56F_DMA_SUBCH 15:13 +#define NVC56F_DMA_OPCODE3 17:16 +#define NVC56F_DMA_OPCODE3_NONE (0x00000000) +#define NVC56F_DMA_COUNT 28:18 +#define NVC56F_DMA_OPCODE 31:29 +#define NVC56F_DMA_OPCODE_METHOD (0x00000000) +#define NVC56F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVC56F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc56f_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc56fsw.h b/userspace/sdks/nv525/nvidia/inc/class/clc56fsw.h new file mode 100644 index 0000000..13496be --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc56fsw.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* This file is *not* auto-generated. */ + +#ifndef _clc56f_sw_h_ +#define _clc56f_sw_h_ + +#define NVC56F_NOTIFIERS_RC (0) +#define NVC56F_NOTIFIERS_REFCNT (1) +#define NVC56F_NOTIFIERS_NONSTALL (2) +#define NVC56F_NOTIFIERS_EVENTBUFFER (3) +#define NVC56F_NOTIFIERS_IDLECHANNEL (4) +#define NVC56F_NOTIFIERS_ENDCTX (5) +#define NVC56F_NOTIFIERS_SW (6) +#define NVC56F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVC56F_NOTIFIERS_REPLAYABLE_FAULT (8) +#define NVC56F_NOTIFIERS_MAXCOUNT (9) + +/* NvNotification[] fields and values */ +#define NVC56F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVC56F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _clc56f_sw_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc570.h b/userspace/sdks/nv525/nvidia/inc/class/clc570.h new file mode 100644 index 0000000..0e562ab --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc570.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc570.finn +// + +#define NVC570_DISPLAY (0xc570U) /* finn: Evaluated from "NVC570_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NVC570_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc570U) + +typedef struct NVC570_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NVC570_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc572.h b/userspace/sdks/nv525/nvidia/inc/class/clc572.h new file mode 100644 index 0000000..79dd9b3 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc572.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc572_h_ +#define _clc572_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define PHYSICAL_CHANNEL_GPFIFO (0x0000C572) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc572_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc573.h b/userspace/sdks/nv525/nvidia/inc/class/clc573.h new file mode 100644 index 0000000..a7bb1f4 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc573.h @@ -0,0 +1,598 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc573_h_ +#define _clc573_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC573_DISP_CAPABILITIES 0xC573 + +typedef volatile struct _clc573_tag0 { + NvU32 dispCapabilities[0x400]; +} _NvC573DispCapabilities,NvC573DispCapabilities_Map ; + + +#define NVC573_SYS_CAP 0x0 /* RW-4R */ +#define NVC573_SYS_CAP_HEAD0_EXISTS 0:0 /* RWIVF */ +#define NVC573_SYS_CAP_HEAD0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_HEAD1_EXISTS 1:1 /* RWIVF */ +#define NVC573_SYS_CAP_HEAD1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_HEAD2_EXISTS 2:2 /* RWIVF */ +#define NVC573_SYS_CAP_HEAD2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_HEAD3_EXISTS 3:3 /* RWIVF */ +#define NVC573_SYS_CAP_HEAD3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_HEAD4_EXISTS 4:4 /* RWIVF */ +#define NVC573_SYS_CAP_HEAD4_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_HEAD5_EXISTS 5:5 /* RWIVF */ +#define NVC573_SYS_CAP_HEAD5_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_HEAD6_EXISTS 6:6 /* RWIVF */ +#define NVC573_SYS_CAP_HEAD6_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_HEAD7_EXISTS 7:7 /* RWIVF */ +#define NVC573_SYS_CAP_HEAD7_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVC573_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */ +#define NVC573_SYS_CAP_HEAD_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR0_EXISTS 8:8 /* RWIVF */ +#define NVC573_SYS_CAP_SOR0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR1_EXISTS 9:9 /* RWIVF */ +#define NVC573_SYS_CAP_SOR1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR2_EXISTS 10:10 /* RWIVF */ +#define NVC573_SYS_CAP_SOR2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR3_EXISTS 11:11 /* RWIVF */ +#define NVC573_SYS_CAP_SOR3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR4_EXISTS 12:12 /* RWIVF */ +#define NVC573_SYS_CAP_SOR4_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR5_EXISTS 13:13 /* RWIVF */ +#define NVC573_SYS_CAP_SOR5_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR6_EXISTS 14:14 /* RWIVF */ +#define NVC573_SYS_CAP_SOR6_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR7_EXISTS 15:15 /* RWIVF */ +#define NVC573_SYS_CAP_SOR7_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* RWIVF */ +#define NVC573_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */ +#define NVC573_SYS_CAP_SOR_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB 0x4 /* RW-4R */ +#define NVC573_SYS_CAPB_WINDOW0_EXISTS 0:0 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW1_EXISTS 1:1 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW2_EXISTS 2:2 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW3_EXISTS 3:3 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW4_EXISTS 4:4 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW4_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW5_EXISTS 5:5 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW5_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW6_EXISTS 6:6 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW6_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW7_EXISTS 7:7 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW7_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW8_EXISTS 8:8 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW8_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW8_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW8_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW9_EXISTS 9:9 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW9_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW9_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW9_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW10_EXISTS 10:10 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW10_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW10_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW10_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW11_EXISTS 11:11 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW11_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW11_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW11_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW12_EXISTS 12:12 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW12_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW12_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW12_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW13_EXISTS 13:13 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW13_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW13_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW13_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW14_EXISTS 14:14 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW14_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW14_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW14_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW15_EXISTS 15:15 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW15_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW15_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW15_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW16_EXISTS 16:16 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW16_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW16_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW16_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW17_EXISTS 17:17 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW17_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW17_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW17_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW18_EXISTS 18:18 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW18_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW18_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW18_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW19_EXISTS 19:19 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW19_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW19_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW19_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW20_EXISTS 20:20 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW20_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW20_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW20_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW21_EXISTS 21:21 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW21_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW21_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW21_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW22_EXISTS 22:22 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW22_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW22_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW22_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW23_EXISTS 23:23 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW23_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW23_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW23_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW24_EXISTS 24:24 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW24_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW24_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW24_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW25_EXISTS 25:25 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW25_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW25_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW25_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW26_EXISTS 26:26 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW26_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW26_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW26_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW27_EXISTS 27:27 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW27_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW27_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW27_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW28_EXISTS 28:28 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW28_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW28_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW28_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW29_EXISTS 29:29 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW29_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW29_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW29_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW30_EXISTS 30:30 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW30_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW30_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW30_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW31_EXISTS 31:31 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW31_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW31_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW31_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW_EXISTS__SIZE_1 32 /* */ +#define NVC573_SYS_CAPB_WINDOW_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA 0x10 /* RW-4R */ +#define NVC573_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES 15:0 /* RWIUF */ +#define NVC573_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH 17:16 /* RWIVF */ +#define NVC573_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B 0x00000000 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B 0x00000002 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B 0x00000003 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_PLANAR 19:19 /* RWIVF */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_PLANAR_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_PLANAR_FALSE 0x00000000 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_PLANAR_TRUE 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_VGA 20:20 /* RWIVF */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_VGA_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE 0x00000000 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION 21:21 /* RWIVF */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_FALSE 0x00000000 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_TRUE 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MSCG 22:22 /* RWIVF */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MSCG_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MSCG_FALSE 0x00000000 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MSCG_TRUE 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH 23:23 /* RWIVF */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_FALSE 0x00000000 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_TRUE 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT 26:26 /* RWIVF */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION 31:30 /* RWIVF */ +#define NVC573_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B 0x00000000 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B 0x00000002 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B 0x00000003 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA(i) (0x680+(i)*32) /* RW-4A */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA__SIZE_1 8 /* */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_FULL_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_UNIT_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT 16:16 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT 17:17 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT 18:18 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OLPF_PRESENT 19:19 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OLPF_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OLPF_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OLPF_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT 20:20 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT 21:21 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT 22:22 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB(i) (0x684+(i)*32) /* RW-4A */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB__SIZE_1 8 /* */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_VGA 0:0 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_VGA_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_VGA_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_VGA_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGSZ 9:6 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGSZ_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGNR 12:10 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGNR_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT 15:15 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC(i) (0x688+(i)*32) /* RW-4A */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC__SIZE_1 8 /* */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC0_PRECISION 4:0 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC0_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC1_PRECISION 12:8 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC1_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP 13:13 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_SF_PRECISION 20:16 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_SF_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_CI_PRECISION 24:21 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_CI_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB 25:25 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPD(i) (0x68c+(i)*32) /* RW-4A */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPD__SIZE_1 8 /* */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE(i) (0x690+(i)*32) /* RW-4A */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE__SIZE_1 8 /* */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_RATEBUFSIZE 3:0 /* RWIUF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_RATEBUFSIZE_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_LINEBUFSIZE 13:8 /* RWIUF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_LINEBUFSIZE_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422 16:16 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420 17:17 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP(i) (0x144+(i)*8) /* RW-4A */ +#define NVC573_SOR_CAP__SIZE_1 8 /* */ +#define NVC573_SOR_CAP_SINGLE_LVDS_18 0:0 /* RWIVF */ +#define NVC573_SOR_CAP_SINGLE_LVDS_18_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_SINGLE_LVDS_24 1:1 /* RWIVF */ +#define NVC573_SOR_CAP_SINGLE_LVDS_24_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_DUAL_LVDS_18 2:2 /* RWIVF */ +#define NVC573_SOR_CAP_DUAL_LVDS_18_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_DUAL_LVDS_24 3:3 /* RWIVF */ +#define NVC573_SOR_CAP_DUAL_LVDS_24_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_SINGLE_TMDS_A 8:8 /* RWIVF */ +#define NVC573_SOR_CAP_SINGLE_TMDS_A_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_SINGLE_TMDS_B 9:9 /* RWIVF */ +#define NVC573_SOR_CAP_SINGLE_TMDS_B_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_DUAL_TMDS 11:11 /* RWIVF */ +#define NVC573_SOR_CAP_DUAL_TMDS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* RWIVF */ +#define NVC573_SOR_CAP_DISPLAY_OVER_PCIE_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_SDI 16:16 /* RWIVF */ +#define NVC573_SOR_CAP_SDI_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_SDI_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_SDI_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_DP_A 24:24 /* RWIVF */ +#define NVC573_SOR_CAP_DP_A_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_DP_A_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_DP_A_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_DP_B 25:25 /* RWIVF */ +#define NVC573_SOR_CAP_DP_B_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_DP_B_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_DP_B_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_DP_INTERLACE 26:26 /* RWIVF */ +#define NVC573_SOR_CAP_DP_INTERLACE_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_DP_8_LANES 27:27 /* RWIVF */ +#define NVC573_SOR_CAP_DP_8_LANES_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA(i) (0x780+(i)*32) /* RW-4A */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA__SIZE_1 32 /* */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH 13:10 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT 16:16 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT 17:17 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT 18:18 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT 19:19 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT 20:20 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT 21:21 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT 22:22 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT 23:23 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT 24:24 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB(i) (0x784+(i)*32) /* RW-4A */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB__SIZE_1 32 /* */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION 4:0 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ 9:6 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR 12:10 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT 15:15 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC(i) (0x788+(i)*32) /* RW-4A */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC__SIZE_1 32 /* */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION 4:0 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGSZ 9:6 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGSZ_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGNR 12:10 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGNR_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT 15:15 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION 20:16 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP 21:21 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD(i) (0x78c+(i)*32) /* RW-4A */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD__SIZE_1 32 /* */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ 3:0 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR 6:4 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD 8:8 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT 9:9 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION 16:12 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION 20:17 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB 21:21 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA 22:22 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE(i) (0x790+(i)*32) /* RW-4A */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE__SIZE_1 32 /* */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION 4:0 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGSZ 9:6 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGSZ_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGNR 12:10 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGNR_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT 15:15 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION 20:16 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP 21:21 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPF(i) (0x794+(i)*32) /* RW-4A */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPF__SIZE_1 32 /* */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP_INIT 0x00000000 /* RWI-V */ + +#ifdef __cplusplus +}; +#endif /* extern C */ +#endif //_clc573_h_ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc574.h b/userspace/sdks/nv525/nvidia/inc/class/clc574.h new file mode 100644 index 0000000..4587c7a --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc574.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc574.finn +// + +#define UVM_CHANNEL_RETAINER (0xc574U) /* finn: Evaluated from "NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_MESSAGE_ID" */ + +#define NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_MESSAGE_ID (0xc574U) + +typedef struct NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS { + NvHandle hClient; + NvHandle hChannel; +} NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc57a.h b/userspace/sdks/nv525/nvidia/inc/class/clc57a.h new file mode 100644 index 0000000..54eb741 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc57a.h @@ -0,0 +1,179 @@ +/* + * Copyright (c) 1993-2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc57a__h_ +#define _clc57a__h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC57A_CURSOR_IMM_CHANNEL_PIO (0x0000C57A) + +typedef volatile struct _clc57a_tag0 { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x7D]; + NvV32 Update; // 0x00000200 - 0x00000203 + NvV32 SetInterlockFlags; // 0x00000204 - 0x00000207 + NvV32 SetCursorHotSpotPointOut[2]; // 0x00000208 - 0x0000020F + NvV32 SetWindowInterlockFlags; // 0x00000210 - 0x00000213 + NvV32 Reserved02[0x37B]; +} NVC57ADispCursorImmControlPio; + +#define NVC57A_FREE (0x00000008) +#define NVC57A_FREE_COUNT 5:0 +#define NVC57A_UPDATE (0x00000200) +#define NVC57A_SET_INTERLOCK_FLAGS (0x00000204) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC57A_SET_CURSOR_HOT_SPOT_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVC57A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0 +#define NVC57A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS (0x00000210) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc57a_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc57b.h b/userspace/sdks/nv525/nvidia/inc/class/clc57b.h new file mode 100644 index 0000000..545ccc5 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc57b.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clC57b_h_ +#define _clC57b_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC57B_WINDOW_IMM_CHANNEL_DMA (0x0000C57B) + +// dma opcode instructions +#define NVC57B_DMA +#define NVC57B_DMA_OPCODE 31:29 +#define NVC57B_DMA_OPCODE_METHOD 0x00000000 +#define NVC57B_DMA_OPCODE_JUMP 0x00000001 +#define NVC57B_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC57B_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC57B_DMA_METHOD_COUNT 27:18 +#define NVC57B_DMA_METHOD_OFFSET 13:2 +#define NVC57B_DMA_DATA 31:0 +#define NVC57B_DMA_DATA_NOP 0x00000000 +#define NVC57B_DMA_JUMP_OFFSET 11:2 +#define NVC57B_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVC57B_PUT (0x00000000) +#define NVC57B_PUT_PTR 9:0 +#define NVC57B_GET (0x00000004) +#define NVC57B_GET_PTR 9:0 +#define NVC57B_UPDATE (0x00000200) +#define NVC57B_UPDATE_INTERLOCK_WITH_WINDOW 1:1 +#define NVC57B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC57B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC57B_SET_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVC57B_SET_POINT_OUT_X 15:0 +#define NVC57B_SET_POINT_OUT_Y 31:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC57b_h diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc57d.h b/userspace/sdks/nv525/nvidia/inc/class/clc57d.h new file mode 100644 index 0000000..4f415d0 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc57d.h @@ -0,0 +1,1277 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clC57d_h_ +#define _clC57d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC57D_CORE_CHANNEL_DMA (0x0000C57D) + +#define NV_DISP_NOTIFIER 0x00000000 +#define NV_DISP_NOTIFIER_SIZEOF 0x00000010 +#define NV_DISP_NOTIFIER__0 0x00000000 +#define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFIER__0_FIELD 8:8 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE 9:9 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001 +#define NV_DISP_NOTIFIER__0_R1 15:10 +#define NV_DISP_NOTIFIER__0_R2 23:16 +#define NV_DISP_NOTIFIER__0_R3 29:24 +#define NV_DISP_NOTIFIER__0_STATUS 31:30 +#define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002 +#define NV_DISP_NOTIFIER__1 0x00000001 +#define NV_DISP_NOTIFIER__1_R4 31:0 +#define NV_DISP_NOTIFIER__2 0x00000002 +#define NV_DISP_NOTIFIER__2_TIMESTAMP_LO 31:0 +#define NV_DISP_NOTIFIER__3 0x00000003 +#define NV_DISP_NOTIFIER__3_TIMESTAMP_HI 31:0 + + +// dma opcode instructions +#define NVC57D_DMA +#define NVC57D_DMA_OPCODE 31:29 +#define NVC57D_DMA_OPCODE_METHOD 0x00000000 +#define NVC57D_DMA_OPCODE_JUMP 0x00000001 +#define NVC57D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC57D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC57D_DMA_METHOD_COUNT 27:18 +#define NVC57D_DMA_METHOD_OFFSET 13:2 +#define NVC57D_DMA_DATA 31:0 +#define NVC57D_DMA_DATA_NOP 0x00000000 +#define NVC57D_DMA_JUMP_OFFSET 11:2 +#define NVC57D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// if cap SUPPORT_FLEXIBLE_WIN_MAPPING is FALSE, this define can be used to obtain which head a window is mapped to +#define NVC37D_WINDOW_MAPPED_TO_HEAD(w) ((w)>>1) +#define NVC37D_GET_VALID_WINDOWMASK_FOR_HEAD(h) ((1<<((h)*2)) | (1<<((h)*2+1))) + +// class methods +#define NVC57D_PUT (0x00000000) +#define NVC57D_PUT_PTR 9:0 +#define NVC57D_GET (0x00000004) +#define NVC57D_GET_PTR 9:0 +#define NVC57D_UPDATE (0x00000200) +#define NVC57D_UPDATE_SPECIAL_HANDLING 21:20 +#define NVC57D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NVC57D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NVC57D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NVC57D_UPDATE_SPECIAL_HANDLING_REASON 19:12 +#define NVC57D_UPDATE_INHIBIT_INTERRUPTS 24:24 +#define NVC57D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NVC57D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NVC57D_UPDATE_RELEASE_ELV 0:0 +#define NVC57D_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC57D_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC57D_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC57D_SET_CONTEXT_DMA_NOTIFIER (0x00000208) +#define NVC57D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NVC57D_SET_NOTIFIER_CONTROL (0x0000020C) +#define NVC57D_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC57D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC57D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC57D_SET_NOTIFIER_CONTROL_OFFSET 11:4 +#define NVC57D_SET_NOTIFIER_CONTROL_NOTIFY 12:12 +#define NVC57D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NVC57D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NVC57D_SET_CONTROL (0x00000210) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN(i) ((i)+0):((i)+0) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN__SIZE_1 4 +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN_DISABLE (0x00000000) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN_ENABLE (0x00000001) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN0 0:0 +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN0_DISABLE (0x00000000) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN0_ENABLE (0x00000001) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN1 1:1 +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN1_DISABLE (0x00000000) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN1_ENABLE (0x00000001) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN2 2:2 +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN2_DISABLE (0x00000000) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN2_ENABLE (0x00000001) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN3 3:3 +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN3_DISABLE (0x00000000) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN3_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS (0x00000218) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+0):((i)+0) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS (0x0000021C) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVC57D_GET_RG_SCAN_LINE(b) (0x00000220 + (b)*0x00000004) +#define NVC57D_GET_RG_SCAN_LINE_LINE 15:0 +#define NVC57D_GET_RG_SCAN_LINE_VBLANK 16:16 +#define NVC57D_GET_RG_SCAN_LINE_VBLANK_FALSE (0x00000000) +#define NVC57D_GET_RG_SCAN_LINE_VBLANK_TRUE (0x00000001) +#define NVC57D_SET_GET_BLANKING_CTRL(b) (0x00000240 + (b)*0x00000004) +#define NVC57D_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NVC57D_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NVC57D_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NVC57D_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NVC57D_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NVC57D_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) + +#define NVC57D_SOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK 7:0 +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVC57D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NVC57D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NVC57D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NVC57D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NVC57D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NVC57D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NVC57D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NVC57D_SOR_SET_CONTROL_PROTOCOL_DSI (0x0000000A) +#define NVC57D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NVC57D_SOR_SET_CONTROL_DE_SYNC_POLARITY 16:16 +#define NVC57D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC57D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC57D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NVC57D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NVC57D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NVC57D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NVC57D_SOR_SET_CUSTOM_REASON(a) (0x00000304 + (a)*0x00000020) +#define NVC57D_SOR_SET_CUSTOM_REASON_CODE 31:0 +#define NVC57D_SOR_SET_SW_SPARE_A(a) (0x00000308 + (a)*0x00000020) +#define NVC57D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NVC57D_SOR_SET_SW_SPARE_B(a) (0x0000030C + (a)*0x00000020) +#define NVC57D_SOR_SET_SW_SPARE_B_CODE 31:0 + +#define NVC57D_WINDOW_SET_CONTROL(a) (0x00001000 + (a)*0x00000080) +#define NVC57D_WINDOW_SET_CONTROL_OWNER 3:0 +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD(i) (0x00000000 +(i)) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD__SIZE_1 8 +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD0 (0x00000000) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD1 (0x00000001) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD2 (0x00000002) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD3 (0x00000003) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD4 (0x00000004) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD5 (0x00000005) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD6 (0x00000006) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD7 (0x00000007) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_NONE (0x0000000F) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0x00000080) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a) (0x00001008 + (a)*0x00000080) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR(a) (0x0000100C + (a)*0x00000080) +#define NVC57D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVC57D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a) (0x00001010 + (a)*0x00000080) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_MAX_PIXELS_FETCHED_PER_LINE 14:0 +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED 16:16 +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED 28:28 +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS 22:20 +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED 24:24 +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) + +#define NVC57D_HEAD_SET_PROCAMP(a) (0x00002000 + (a)*0x00000400) +#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003) +#define NVC57D_HEAD_SET_PROCAMP_CHROMA_LPF 3:3 +#define NVC57D_HEAD_SET_PROCAMP_CHROMA_LPF_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_PROCAMP_CHROMA_LPF_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 28:28 +#define NVC57D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NVC57D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00002004 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 2:2 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 3:3 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 7:4 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000004) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000005) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000006) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000007) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000008) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 24:24 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 23:12 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN 31:26 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN0 (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN1 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN2 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN3 (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN4 (0x00000004) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN5 (0x00000005) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN6 (0x00000006) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN7 (0x00000007) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN8 (0x00000008) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN9 (0x00000009) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN10 (0x0000000A) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN11 (0x0000000B) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN12 (0x0000000C) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN13 (0x0000000D) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN14 (0x0000000E) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN15 (0x0000000F) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN16 (0x00000010) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN17 (0x00000011) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN18 (0x00000012) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN19 (0x00000013) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN20 (0x00000014) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN21 (0x00000015) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN22 (0x00000016) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN23 (0x00000017) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN24 (0x00000018) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN25 (0x00000019) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN26 (0x0000001A) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN27 (0x0000001B) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN28 (0x0000001C) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN29 (0x0000001D) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN30 (0x0000001E) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN31 (0x0000001F) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_NONE (0x0000003F) +#define NVC57D_HEAD_SET_CONTROL(a) (0x00002008 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CONTROL_STRUCTURE 1:0 +#define NVC57D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE 2:2 +#define NVC57D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_NORMAL (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 11:10 +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 8:4 +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 15:12 +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 23:22 +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 20:16 +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN 28:24 +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000004) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000005) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000006) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000007) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000008) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000009) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000B) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000C) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000D) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000E) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000F) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x00000010) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NVC57D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NVC57D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x0000200C + (a)*0x00000400) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC57D_HEAD_SET_PIXEL_REORDER_CONTROL(a) (0x00002010 + (a)*0x00000400) +#define NVC57D_HEAD_SET_PIXEL_REORDER_CONTROL_BANK_WIDTH 13:0 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00002014 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVC57D_HEAD_SET_DITHER_CONTROL(a) (0x00002018 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NVC57D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_DITHER_CONTROL_BITS 5:4 +#define NVC57D_HEAD_SET_DITHER_CONTROL_BITS_TO_6_BITS (0x00000000) +#define NVC57D_HEAD_SET_DITHER_CONTROL_BITS_TO_8_BITS (0x00000001) +#define NVC57D_HEAD_SET_DITHER_CONTROL_BITS_TO_10_BITS (0x00000002) +#define NVC57D_HEAD_SET_DITHER_CONTROL_BITS_TO_12_BITS (0x00000003) +#define NVC57D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE 2:2 +#define NVC57D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_DITHER_CONTROL_MODE 10:8 +#define NVC57D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NVC57D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NVC57D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NVC57D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NVC57D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NVC57D_HEAD_SET_DITHER_CONTROL_MODE_ROUND (0x00000005) +#define NVC57D_HEAD_SET_DITHER_CONTROL_PHASE 13:12 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x0000201C + (a)*0x00000400) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 0:0 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING 4:4 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 9:8 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NVC57D_HEAD_SET_DISPLAY_ID(a,b) (0x00002020 + (a)*0x00000400 + (b)*0x00000004) +#define NVC57D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00002028 + (a)*0x00000400) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC57D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR(a) (0x0000202C + (a)*0x00000400) +#define NVC57D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVC57D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS(a) (0x00002030 + (a)*0x00000400) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR 2:0 +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_NONE (0x00000000) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W32_H32 (0x00000001) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W64_H64 (0x00000002) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W128_H128 (0x00000003) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W256_H256 (0x00000004) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED 4:4 +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_FALSE (0x00000000) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_TRUE (0x00000001) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS 14:12 +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED 8:8 +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVC57D_HEAD_SET_STALL_LOCK(a) (0x00002034 + (a)*0x00000400) +#define NVC57D_HEAD_SET_STALL_LOCK_ENABLE 0:0 +#define NVC57D_HEAD_SET_STALL_LOCK_ENABLE_FALSE (0x00000000) +#define NVC57D_HEAD_SET_STALL_LOCK_ENABLE_TRUE (0x00000001) +#define NVC57D_HEAD_SET_STALL_LOCK_MODE 2:2 +#define NVC57D_HEAD_SET_STALL_LOCK_MODE_CONTINUOUS (0x00000000) +#define NVC57D_HEAD_SET_STALL_LOCK_MODE_ONE_SHOT (0x00000001) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN 8:4 +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC57D_HEAD_SET_STALL_LOCK_UNSTALL_MODE 12:12 +#define NVC57D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_CRASH_LOCK (0x00000000) +#define NVC57D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_LINE_LOCK (0x00000001) +#define NVC57D_HEAD_SET_STALL_LOCK_TEPOLARITY 14:14 +#define NVC57D_HEAD_SET_STALL_LOCK_TEPOLARITY_POSITIVE_TRUE (0x00000000) +#define NVC57D_HEAD_SET_STALL_LOCK_TEPOLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC57D_HEAD_SET_LOCK_CHAIN(a) (0x00002044 + (a)*0x00000400) +#define NVC57D_HEAD_SET_LOCK_CHAIN_POSITION 3:0 +#define NVC57D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x00002048 + (a)*0x00000400) +#define NVC57D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NVC57D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NVC57D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x0000204C + (a)*0x00000400) +#define NVC57D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NVC57D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NVC57D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x00002058 + (a)*0x00000400) +#define NVC57D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NVC57D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NVC57D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x0000205C + (a)*0x00000400) +#define NVC57D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NVC57D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NVC57D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000400) +#define NVC57D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NVC57D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NVC57D_HEAD_SET_RASTER_SYNC_END(a) (0x00002068 + (a)*0x00000400) +#define NVC57D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NVC57D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NVC57D_HEAD_SET_RASTER_BLANK_END(a) (0x0000206C + (a)*0x00000400) +#define NVC57D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NVC57D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NVC57D_HEAD_SET_RASTER_BLANK_START(a) (0x00002070 + (a)*0x00000400) +#define NVC57D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NVC57D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NVC57D_HEAD_SET_OVERSCAN_COLOR(a) (0x00002078 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OVERSCAN_COLOR_RED_CR 9:0 +#define NVC57D_HEAD_SET_OVERSCAN_COLOR_GREEN_Y 19:10 +#define NVC57D_HEAD_SET_OVERSCAN_COLOR_BLUE_CB 29:20 +#define NVC57D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR(a) (0x0000207C + (a)*0x00000400) +#define NVC57D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_RED_CR 9:0 +#define NVC57D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_GREEN_Y 19:10 +#define NVC57D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_BLUE_CB 29:20 +#define NVC57D_HEAD_SET_HDMI_CTRL(a) (0x00002080 + (a)*0x00000400) +#define NVC57D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NVC57D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NVC57D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NVC57D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NVC57D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NVC57D_HEAD_SET_CONTEXT_DMA_CURSOR(a,b) (0x00002088 + (a)*0x00000400 + (b)*0x00000004) +#define NVC57D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0 +#define NVC57D_HEAD_SET_OFFSET_CURSOR(a,b) (0x00002090 + (a)*0x00000400 + (b)*0x00000004) +#define NVC57D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0 +#define NVC57D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x00002098 + (a)*0x00000400) +#define NVC57D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 0:0 +#define NVC57D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NVC57D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_CURSOR(a) (0x0000209C + (a)*0x00000400) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_FORMAT 7:0 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_SIZE 9:8 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 19:12 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 27:20 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION(a) (0x000020A0 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_K1 7:0 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT 11:8 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT 15:12 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_ZERO (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE 16:16 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_BLEND (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_XOR (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS 20:20 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00002180 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NVC57D_HEAD_SET_CRC_CONTROL(a) (0x00002184 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 5:0 +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_0 (0x00000000) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_1 (0x00000001) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_2 (0x00000002) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_3 (0x00000003) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_4 (0x00000004) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_5 (0x00000005) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_6 (0x00000006) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_7 (0x00000007) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_8 (0x00000008) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_9 (0x00000009) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_10 (0x0000000A) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_11 (0x0000000B) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_12 (0x0000000C) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_13 (0x0000000D) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_14 (0x0000000E) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_15 (0x0000000F) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_16 (0x00000010) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_17 (0x00000011) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_18 (0x00000012) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_19 (0x00000013) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_20 (0x00000014) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_21 (0x00000015) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_22 (0x00000016) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_23 (0x00000017) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_24 (0x00000018) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_25 (0x00000019) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_26 (0x0000001A) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_27 (0x0000001B) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_28 (0x0000001C) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_29 (0x0000001D) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_30 (0x0000001E) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_31 (0x0000001F) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000020) +#define NVC57D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 8:8 +#define NVC57D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NVC57D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC 19:12 +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_NONE (0x00000000) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SF (0x00000030) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR__SIZE_1 8 +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR0 (0x00000050) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR1 (0x00000051) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR2 (0x00000052) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR3 (0x00000053) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR4 (0x00000054) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR5 (0x00000055) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR6 (0x00000056) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR7 (0x00000057) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC 27:20 +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_NONE (0x00000000) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SF (0x00000030) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR__SIZE_1 8 +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR0 (0x00000050) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR1 (0x00000051) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR2 (0x00000052) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR3 (0x00000053) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR4 (0x00000054) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR5 (0x00000055) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR6 (0x00000056) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR7 (0x00000057) +#define NVC57D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 9:9 +#define NVC57D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_PRESENT_CONTROL(a) (0x0000218C + (a)*0x00000400) +#define NVC57D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 0:0 +#define NVC57D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NVC57D_HEAD_SET_SW_SPARE_A(a) (0x00002194 + (a)*0x00000400) +#define NVC57D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NVC57D_HEAD_SET_SW_SPARE_B(a) (0x00002198 + (a)*0x00000400) +#define NVC57D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NVC57D_HEAD_SET_SW_SPARE_C(a) (0x0000219C + (a)*0x00000400) +#define NVC57D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NVC57D_HEAD_SET_SW_SPARE_D(a) (0x000021A0 + (a)*0x00000400) +#define NVC57D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NVC57D_HEAD_SET_DISPLAY_RATE(a) (0x000021A8 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DISPLAY_RATE_RUN_MODE 0:0 +#define NVC57D_HEAD_SET_DISPLAY_RATE_RUN_MODE_CONTINUOUS (0x00000000) +#define NVC57D_HEAD_SET_DISPLAY_RATE_RUN_MODE_ONE_SHOT (0x00000001) +#define NVC57D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_INTERVAL 25:4 +#define NVC57D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH 2:2 +#define NVC57D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE(a) (0x00002214 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVC57D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVC57D_HEAD_SET_MIN_FRAME_IDLE(a) (0x00002218 + (a)*0x00000400) +#define NVC57D_HEAD_SET_MIN_FRAME_IDLE_LEADING_RASTER_LINES 14:0 +#define NVC57D_HEAD_SET_MIN_FRAME_IDLE_TRAILING_RASTER_LINES 30:16 +#define NVC57D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED(a) (0x00002220 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED_ALPHA 7:0 +#define NVC57D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED_RED 31:16 +#define NVC57D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE(a) (0x00002224 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE_GREEN 15:0 +#define NVC57D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE_BLUE 31:16 +#define NVC57D_HEAD_SET_CURSOR_COLOR_NORM_SCALE(a) (0x00002228 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CURSOR_COLOR_NORM_SCALE_VALUE 15:0 +#define NVC57D_HEAD_SET_XOR_BLEND_FACTOR(a) (0x0000222C + (a)*0x00000400) +#define NVC57D_HEAD_SET_XOR_BLEND_FACTOR_LOG2PEAK_LUMINANCE 3:0 +#define NVC57D_HEAD_SET_XOR_BLEND_FACTOR_S1 16:4 +#define NVC57D_HEAD_SET_XOR_BLEND_FACTOR_S2 30:18 +#define NVC57D_HEAD_SET_CLAMP_RANGE_GREEN(a) (0x00002238 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CLAMP_RANGE_GREEN_LOW 11:0 +#define NVC57D_HEAD_SET_CLAMP_RANGE_GREEN_HIGH 27:16 +#define NVC57D_HEAD_SET_CLAMP_RANGE_RED_BLUE(a) (0x0000223C + (a)*0x00000400) +#define NVC57D_HEAD_SET_CLAMP_RANGE_RED_BLUE_LOW 11:0 +#define NVC57D_HEAD_SET_CLAMP_RANGE_RED_BLUE_HIGH 27:16 +#define NVC57D_HEAD_SET_OCSC0CONTROL(a) (0x00002240 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0CONTROL_ENABLE 0:0 +#define NVC57D_HEAD_SET_OCSC0CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_OCSC0CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C00(a) (0x00002244 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C00_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C01(a) (0x00002248 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C01_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C02(a) (0x0000224C + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C02_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C03(a) (0x00002250 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C03_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C10(a) (0x00002254 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C10_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C11(a) (0x00002258 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C11_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C12(a) (0x0000225C + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C12_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C13(a) (0x00002260 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C13_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C20(a) (0x00002264 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C20_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C21(a) (0x00002268 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C21_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C22(a) (0x0000226C + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C22_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C23(a) (0x00002270 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C23_VALUE 20:0 +#define NVC57D_HEAD_SET_OLUT_CONTROL(a) (0x00002280 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OLUT_CONTROL_INTERPOLATE 0:0 +#define NVC57D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_OLUT_CONTROL_MIRROR 1:1 +#define NVC57D_HEAD_SET_OLUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_OLUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_OLUT_CONTROL_MODE 3:2 +#define NVC57D_HEAD_SET_OLUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVC57D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVC57D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVC57D_HEAD_SET_OLUT_CONTROL_SIZE 18:8 +#define NVC57D_HEAD_SET_OLUT_FP_NORM_SCALE(a) (0x00002284 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OLUT_FP_NORM_SCALE_VALUE 31:0 +#define NVC57D_HEAD_SET_CONTEXT_DMA_OLUT(a) (0x00002288 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CONTEXT_DMA_OLUT_HANDLE 31:0 +#define NVC57D_HEAD_SET_OFFSET_OLUT(a) (0x0000228C + (a)*0x00000400) +#define NVC57D_HEAD_SET_OFFSET_OLUT_ORIGIN 31:0 +#define NVC57D_HEAD_SET_OCSC1CONTROL(a) (0x0000229C + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1CONTROL_ENABLE 0:0 +#define NVC57D_HEAD_SET_OCSC1CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_OCSC1CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C00(a) (0x000022A0 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C00_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C01(a) (0x000022A4 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C01_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C02(a) (0x000022A8 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C02_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C03(a) (0x000022AC + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C03_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C10(a) (0x000022B0 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C10_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C11(a) (0x000022B4 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C11_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C12(a) (0x000022B8 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C12_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C13(a) (0x000022BC + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C13_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C20(a) (0x000022C0 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C20_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C21(a) (0x000022C4 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C21_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C22(a) (0x000022C8 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C22_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C23(a) (0x000022CC + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C23_VALUE 20:0 +#define NVC57D_HEAD_SET_TILE_POSITION(a) (0x000022D0 + (a)*0x00000400) +#define NVC57D_HEAD_SET_TILE_POSITION_X 2:0 +#define NVC57D_HEAD_SET_TILE_POSITION_Y 6:4 +#define NVC57D_HEAD_SET_DSC_CONTROL(a) (0x000022D4 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_CONTROL_ENABLE 0:0 +#define NVC57D_HEAD_SET_DSC_CONTROL_ENABLE_FALSE (0x00000000) +#define NVC57D_HEAD_SET_DSC_CONTROL_ENABLE_TRUE (0x00000001) +#define NVC57D_HEAD_SET_DSC_CONTROL_MODE 2:1 +#define NVC57D_HEAD_SET_DSC_CONTROL_MODE_SINGLE (0x00000000) +#define NVC57D_HEAD_SET_DSC_CONTROL_MODE_DUAL (0x00000001) +#define NVC57D_HEAD_SET_DSC_CONTROL_MODE_QUAD (0x00000002) +#define NVC57D_HEAD_SET_DSC_CONTROL_MODE_DROP (0x00000003) +#define NVC57D_HEAD_SET_DSC_CONTROL_AUTO_RESET 3:3 +#define NVC57D_HEAD_SET_DSC_CONTROL_AUTO_RESET_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_DSC_CONTROL_AUTO_RESET_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION 4:4 +#define NVC57D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET 5:5 +#define NVC57D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET_FALSE (0x00000000) +#define NVC57D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET_TRUE (0x00000001) +#define NVC57D_HEAD_SET_DSC_CONTROL_FLATNESS_DET_THRESH 15:6 +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL(a) (0x000022D8 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_ENABLE 0:0 +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_ENABLE_FALSE (0x00000000) +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_ENABLE_TRUE (0x00000001) +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_LOCATION 1:1 +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_VSYNC (0x00000000) +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_VBLANK (0x00000001) +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_SIZE 9:2 +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY 10:10 +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY_ONCE (0x00000001) +#define NVC57D_HEAD_SET_DSC_PPS_HEAD(a) (0x000022DC + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_HEAD_BYTE0 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_HEAD_BYTE1 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_HEAD_BYTE2 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_HEAD_BYTE3 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA0(a) (0x000022E0 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA0_DSC_VERSION_MINOR 3:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA0_DSC_VERSION_MAJOR 7:4 +#define NVC57D_HEAD_SET_DSC_PPS_DATA0_PPS_IDENTIFIER 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA0_RESERVED 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA0_LINEBUF_DEPTH 27:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA0_BITS_PER_COMPONENT 31:28 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1(a) (0x000022E4 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_BITS_PER_PIXEL_HIGH 1:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_VBR_ENABLE 2:2 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_SIMPLE422 3:3 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_CONVERT_RGB 4:4 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_BLOCK_PRED_ENABLE 5:5 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_RESERVED 7:6 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_BITS_PER_PIXEL_LOW 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_PIC_HEIGHT_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_PIC_HEIGHT_LOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA2(a) (0x000022E8 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA2_PIC_WIDTH_HIGH 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA2_PIC_WIDTH_LOW 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA2_SLICE_HEIGHT_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA2_SLICE_HEIGHT_LOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA3(a) (0x000022EC + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA3_SLICE_WIDTH_HIGH 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA3_SLICE_WIDTH_LOW 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA3_CHUNK_SIZE_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA3_CHUNK_SIZE_LOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA4(a) (0x000022F0 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA4_INITIAL_XMIT_DELAY_HIGH 1:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA4_RESERVED 7:2 +#define NVC57D_HEAD_SET_DSC_PPS_DATA4_INITIAL_XMIT_DELAY_LOW 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA4_INITIAL_DEC_DELAY_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA4_INITIAL_DEC_DELAY_LOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA5(a) (0x000022F4 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA5_RESERVED0 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA5_INITIAL_SCALE_VALUE 13:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA5_RESERVED1 15:14 +#define NVC57D_HEAD_SET_DSC_PPS_DATA5_SCALE_INCREMENT_INTERVAL_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA5_SCALE_INCREMENT_INTERVAL_LOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA6(a) (0x000022F8 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA6_SCALE_DECREMENT_INTERVAL_HIGH 3:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA6_RESERVED0 7:4 +#define NVC57D_HEAD_SET_DSC_PPS_DATA6_SCALE_DECREMENT_INTERVAL_LOW 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA6_RESERVED1 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA6_FIRST_LINE_BPG_OFFSET 28:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA6_RESERVED2 31:29 +#define NVC57D_HEAD_SET_DSC_PPS_DATA7(a) (0x000022FC + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA7_NFL_BPG_OFFSET_HIGH 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA7_NFL_BPG_OFFSET_LOW 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA7_SLICE_BPG_OFFSET_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA7_SLICE_BPG_OFFSET_LOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA8(a) (0x00002300 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA8_INITIAL_OFFSET_HIGH 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA8_INITIAL_OFFSET_LOW 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA8_FINAL_OFFSET_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA8_FINAL_OFFSET_LOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA9(a) (0x00002304 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA9_FLATNESS_MIN_QP 4:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA9_RESERVED0 7:5 +#define NVC57D_HEAD_SET_DSC_PPS_DATA9_FLATNESS_MAX_QP 12:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA9_RESERVED1 15:13 +#define NVC57D_HEAD_SET_DSC_PPS_DATA9_RC_MODEL_SIZE_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA9_RC_MODEL_SIZE_LOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA10(a) (0x00002308 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA10_RC_EDGE_FACTOR 3:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA10_RESERVED0 7:4 +#define NVC57D_HEAD_SET_DSC_PPS_DATA10_RC_QUANT_INCR_LIMIT0 12:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA10_RESERVED1 15:13 +#define NVC57D_HEAD_SET_DSC_PPS_DATA10_RC_QUANT_INCR_LIMIT1 20:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA10_RESERVED2 23:21 +#define NVC57D_HEAD_SET_DSC_PPS_DATA10_RC_TGT_OFFSET_LO 27:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA10_RC_TGT_OFFSET_HI 31:28 +#define NVC57D_HEAD_SET_DSC_PPS_DATA11(a) (0x0000230C + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH0 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH1 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH2 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH3 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA12(a) (0x00002310 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH4 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH5 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH6 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH7 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA13(a) (0x00002314 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH8 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH9 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH10 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH11 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA14(a) (0x00002318 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA14_RC_BUF_THRESH12 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA14_RC_BUF_THRESH13 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MAX_QP_HIGH0 18:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MIN_QP0 23:19 +#define NVC57D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_BPG_OFFSET0 29:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MAX_QP_LOW0 31:30 +#define NVC57D_HEAD_SET_DSC_PPS_DATA15(a) (0x0000231C + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_HIGH1 2:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MIN_QP1 7:3 +#define NVC57D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_BPG_OFFSET1 13:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_LOW1 15:14 +#define NVC57D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_HIGH2 18:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MIN_QP2 23:19 +#define NVC57D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_BPG_OFFSET2 29:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_LOW2 31:30 +#define NVC57D_HEAD_SET_DSC_PPS_DATA16(a) (0x00002320 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_HIGH3 2:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MIN_QP3 7:3 +#define NVC57D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_BPG_OFFSET3 13:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_LOW3 15:14 +#define NVC57D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_HIGH4 18:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MIN_QP4 23:19 +#define NVC57D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_BPG_OFFSET4 29:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_LOW4 31:30 +#define NVC57D_HEAD_SET_DSC_PPS_DATA17(a) (0x00002324 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_HIGH5 2:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MIN_QP5 7:3 +#define NVC57D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_BPG_OFFSET5 13:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_LOW5 15:14 +#define NVC57D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_HIGH6 18:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MIN_QP6 23:19 +#define NVC57D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_BPG_OFFSET6 29:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_LOW6 31:30 +#define NVC57D_HEAD_SET_DSC_PPS_DATA18(a) (0x00002328 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_HIGH7 2:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MIN_QP7 7:3 +#define NVC57D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_BPG_OFFSET7 13:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_LOW7 15:14 +#define NVC57D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_HIGH8 18:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MIN_QP8 23:19 +#define NVC57D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_BPG_OFFSET8 29:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_LOW8 31:30 +#define NVC57D_HEAD_SET_DSC_PPS_DATA19(a) (0x0000232C + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_HIGH9 2:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MIN_QP9 7:3 +#define NVC57D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_BPG_OFFSET9 13:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_LOW9 15:14 +#define NVC57D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_HIGH10 18:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MIN_QP10 23:19 +#define NVC57D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_BPG_OFFSET10 29:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_LOW10 31:30 +#define NVC57D_HEAD_SET_DSC_PPS_DATA20(a) (0x00002330 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_HIGH11 2:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MIN_QP11 7:3 +#define NVC57D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_BPG_OFFSET11 13:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_LOW11 15:14 +#define NVC57D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_HIGH12 18:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MIN_QP12 23:19 +#define NVC57D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_BPG_OFFSET12 29:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_LOW12 31:30 +#define NVC57D_HEAD_SET_DSC_PPS_DATA21(a) (0x00002334 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_HIGH13 2:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MIN_QP13 7:3 +#define NVC57D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_BPG_OFFSET13 13:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_LOW13 15:14 +#define NVC57D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_HIGH14 18:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MIN_QP14 23:19 +#define NVC57D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_BPG_OFFSET14 29:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_LOW14 31:30 +#define NVC57D_HEAD_SET_DSC_PPS_DATA22(a) (0x00002338 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA22_NATIVE422 0:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA22_NATIVE420 1:1 +#define NVC57D_HEAD_SET_DSC_PPS_DATA22_RESERVED0 7:2 +#define NVC57D_HEAD_SET_DSC_PPS_DATA22_SECOND_LINE_BPG_OFFSET 12:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA22_RESERVED1 15:13 +#define NVC57D_HEAD_SET_DSC_PPS_DATA22_NSL_BPG_OFFSET_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA22_NSL_BPG_OFFSETLOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA23(a) (0x0000233C + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA23_SECOND_LINE_OFFSET_ADJ_HIGH 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA23_SECOND_LINE_OFFSET_ADJ_LOW 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA23_RESERVED 31:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA24(a) (0x00002340 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA24_RESERVED 31:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA25(a) (0x00002344 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA25_RESERVED 31:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA26(a) (0x00002348 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA26_RESERVED 31:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA27(a) (0x0000234C + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA27_RESERVED 31:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA28(a) (0x00002350 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA28_RESERVED 31:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA29(a) (0x00002354 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA29_RESERVED 31:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA30(a) (0x00002358 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA30_RESERVED 31:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA31(a) (0x0000235C + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA31_RESERVED 31:0 +#define NVC57D_HEAD_SET_RG_MERGE(a) (0x00002360 + (a)*0x00000400) +#define NVC57D_HEAD_SET_RG_MERGE_MODE 1:0 +#define NVC57D_HEAD_SET_RG_MERGE_MODE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_RG_MERGE_MODE_SETUP (0x00000001) +#define NVC57D_HEAD_SET_RG_MERGE_MODE_MASTER (0x00000002) +#define NVC57D_HEAD_SET_RG_MERGE_MODE_SLAVE (0x00000003) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC57d_h diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc57e.h b/userspace/sdks/nv525/nvidia/inc/class/clc57e.h new file mode 100644 index 0000000..d613410 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc57e.h @@ -0,0 +1,657 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clC57e_h_ +#define _clC57e_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC57E_WINDOW_CHANNEL_DMA (0x0000C57E) + +// dma opcode instructions +#define NVC57E_DMA +#define NVC57E_DMA_OPCODE 31:29 +#define NVC57E_DMA_OPCODE_METHOD 0x00000000 +#define NVC57E_DMA_OPCODE_JUMP 0x00000001 +#define NVC57E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC57E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC57E_DMA_METHOD_COUNT 27:18 +#define NVC57E_DMA_METHOD_OFFSET 13:2 +#define NVC57E_DMA_DATA 31:0 +#define NVC57E_DMA_DATA_NOP 0x00000000 +#define NVC57E_DMA_JUMP_OFFSET 11:2 +#define NVC57E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVC57E_PUT (0x00000000) +#define NVC57E_PUT_PTR 9:0 +#define NVC57E_GET (0x00000004) +#define NVC57E_GET_PTR 9:0 +#define NVC57E_UPDATE (0x00000200) +#define NVC57E_UPDATE_RELEASE_ELV 0:0 +#define NVC57E_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC57E_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC57E_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC57E_UPDATE_INTERLOCK_WITH_WIN_IMM 12:12 +#define NVC57E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE (0x00000000) +#define NVC57E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE (0x00000001) +#define NVC57E_GET_LINE (0x00000208) +#define NVC57E_GET_LINE_LINE 15:0 +#define NVC57E_SET_SEMAPHORE_CONTROL (0x0000020C) +#define NVC57E_SET_SEMAPHORE_CONTROL_OFFSET 7:0 +#define NVC57E_SET_SEMAPHORE_ACQUIRE (0x00000210) +#define NVC57E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NVC57E_SET_SEMAPHORE_RELEASE (0x00000214) +#define NVC57E_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NVC57E_SET_CONTEXT_DMA_SEMAPHORE (0x00000218) +#define NVC57E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NVC57E_SET_CONTEXT_DMA_NOTIFIER (0x0000021C) +#define NVC57E_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NVC57E_SET_NOTIFIER_CONTROL (0x00000220) +#define NVC57E_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC57E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC57E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC57E_SET_NOTIFIER_CONTROL_OFFSET 11:4 +#define NVC57E_SET_SIZE (0x00000224) +#define NVC57E_SET_SIZE_WIDTH 15:0 +#define NVC57E_SET_SIZE_HEIGHT 31:16 +#define NVC57E_SET_STORAGE (0x00000228) +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC57E_SET_STORAGE_MEMORY_LAYOUT 4:4 +#define NVC57E_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC57E_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC57E_SET_PARAMS (0x0000022C) +#define NVC57E_SET_PARAMS_FORMAT 7:0 +#define NVC57E_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NVC57E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F) +#define NVC57E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NVC57E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC57E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E) +#define NVC57E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC57E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6) +#define NVC57E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NVC57E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9) +#define NVC57E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NVC57E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NVC57E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NVC57E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024) +#define NVC57E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NVC57E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NVC57E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NVC57E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028) +#define NVC57E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029) +#define NVC57E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035) +#define NVC57E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036) +#define NVC57E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038) +#define NVC57E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055) +#define NVC57E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056) +#define NVC57E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058) +#define NVC57E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075) +#define NVC57E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076) +#define NVC57E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078) +#define NVC57E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18 +#define NVC57E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000) +#define NVC57E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001) +#define NVC57E_SET_PARAMS_SWAP_UV 19:19 +#define NVC57E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000) +#define NVC57E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001) +#define NVC57E_SET_PARAMS_FMT_ROUNDING_MODE 22:22 +#define NVC57E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_TO_NEAREST (0x00000000) +#define NVC57E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_DOWN (0x00000001) +#define NVC57E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004) +#define NVC57E_SET_PLANAR_STORAGE_PITCH 12:0 +#define NVC57E_SET_CONTEXT_DMA_ISO(b) (0x00000240 + (b)*0x00000004) +#define NVC57E_SET_CONTEXT_DMA_ISO_HANDLE 31:0 +#define NVC57E_SET_OFFSET(b) (0x00000260 + (b)*0x00000004) +#define NVC57E_SET_OFFSET_ORIGIN 31:0 +#define NVC57E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004) +#define NVC57E_SET_POINT_IN_X 15:0 +#define NVC57E_SET_POINT_IN_Y 31:16 +#define NVC57E_SET_SIZE_IN (0x00000298) +#define NVC57E_SET_SIZE_IN_WIDTH 15:0 +#define NVC57E_SET_SIZE_IN_HEIGHT 31:16 +#define NVC57E_SET_SIZE_OUT (0x000002A4) +#define NVC57E_SET_SIZE_OUT_WIDTH 15:0 +#define NVC57E_SET_SIZE_OUT_HEIGHT 31:16 +#define NVC57E_SET_CONTROL_INPUT_SCALER (0x000002A8) +#define NVC57E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVC57E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVC57E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVC57E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVC57E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVC57E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVC57E_SET_INPUT_SCALER_COEFF_VALUE (0x000002AC) +#define NVC57E_SET_INPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVC57E_SET_INPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVC57E_SET_COMPOSITION_CONTROL (0x000002EC) +#define NVC57E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0 +#define NVC57E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000) +#define NVC57E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001) +#define NVC57E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002) +#define NVC57E_SET_COMPOSITION_CONTROL_DEPTH 11:4 +#define NVC57E_SET_COMPOSITION_CONTROL_BYPASS 16:16 +#define NVC57E_SET_COMPOSITION_CONTROL_BYPASS_DISABLE (0x00000000) +#define NVC57E_SET_COMPOSITION_CONTROL_BYPASS_ENABLE (0x00000001) +#define NVC57E_SET_COMPOSITION_CONSTANT_ALPHA (0x000002F0) +#define NVC57E_SET_COMPOSITION_CONSTANT_ALPHA_K1 7:0 +#define NVC57E_SET_COMPOSITION_CONSTANT_ALPHA_K2 15:8 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT (0x000002F4) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC57E_SET_KEY_ALPHA (0x000002F8) +#define NVC57E_SET_KEY_ALPHA_MIN 15:0 +#define NVC57E_SET_KEY_ALPHA_MAX 31:16 +#define NVC57E_SET_KEY_RED_CR (0x000002FC) +#define NVC57E_SET_KEY_RED_CR_MIN 15:0 +#define NVC57E_SET_KEY_RED_CR_MAX 31:16 +#define NVC57E_SET_KEY_GREEN_Y (0x00000300) +#define NVC57E_SET_KEY_GREEN_Y_MIN 15:0 +#define NVC57E_SET_KEY_GREEN_Y_MAX 31:16 +#define NVC57E_SET_KEY_BLUE_CB (0x00000304) +#define NVC57E_SET_KEY_BLUE_CB_MIN 15:0 +#define NVC57E_SET_KEY_BLUE_CB_MAX 31:16 +#define NVC57E_SET_PRESENT_CONTROL (0x00000308) +#define NVC57E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NVC57E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4 +#define NVC57E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NVC57E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NVC57E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8 +#define NVC57E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000) +#define NVC57E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001) +#define NVC57E_SET_PRESENT_CONTROL_STEREO_MODE 13:12 +#define NVC57E_SET_PRESENT_CONTROL_STEREO_MODE_MONO (0x00000000) +#define NVC57E_SET_PRESENT_CONTROL_STEREO_MODE_PAIR_FLIP (0x00000001) +#define NVC57E_SET_PRESENT_CONTROL_STEREO_MODE_AT_ANY_FRAME (0x00000002) +#define NVC57E_SET_TIMESTAMP_ORIGIN_LO (0x00000340) +#define NVC57E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NVC57E_SET_TIMESTAMP_ORIGIN_HI (0x00000344) +#define NVC57E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NVC57E_SET_UPDATE_TIMESTAMP_LO (0x00000348) +#define NVC57E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NVC57E_SET_UPDATE_TIMESTAMP_HI (0x0000034C) +#define NVC57E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NVC57E_SET_INTERLOCK_FLAGS (0x00000370) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 0:0 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+1):((i)+1) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 1:1 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 2:2 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 3:3 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 4:4 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 5:5 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 6:6 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 7:7 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 8:8 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS (0x00000374) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVC57E_SET_EXT_PACKET_CONTROL (0x00000398) +#define NVC57E_SET_EXT_PACKET_CONTROL_ENABLE 0:0 +#define NVC57E_SET_EXT_PACKET_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57E_SET_EXT_PACKET_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57E_SET_EXT_PACKET_CONTROL_LOCATION 4:4 +#define NVC57E_SET_EXT_PACKET_CONTROL_LOCATION_VSYNC (0x00000000) +#define NVC57E_SET_EXT_PACKET_CONTROL_LOCATION_VBLANK (0x00000001) +#define NVC57E_SET_EXT_PACKET_CONTROL_FREQUENCY 8:8 +#define NVC57E_SET_EXT_PACKET_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVC57E_SET_EXT_PACKET_CONTROL_FREQUENCY_ONCE (0x00000001) +#define NVC57E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE 12:12 +#define NVC57E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_DISABLE (0x00000000) +#define NVC57E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_ENABLE (0x00000001) +#define NVC57E_SET_EXT_PACKET_CONTROL_SIZE 27:16 +#define NVC57E_SET_EXT_PACKET_DATA (0x0000039C) +#define NVC57E_SET_EXT_PACKET_DATA_DB0 7:0 +#define NVC57E_SET_EXT_PACKET_DATA_DB1 15:8 +#define NVC57E_SET_EXT_PACKET_DATA_DB2 23:16 +#define NVC57E_SET_EXT_PACKET_DATA_DB3 31:24 +#define NVC57E_SET_FMT_COEFFICIENT_C00 (0x00000400) +#define NVC57E_SET_FMT_COEFFICIENT_C00_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C01 (0x00000404) +#define NVC57E_SET_FMT_COEFFICIENT_C01_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C02 (0x00000408) +#define NVC57E_SET_FMT_COEFFICIENT_C02_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C03 (0x0000040C) +#define NVC57E_SET_FMT_COEFFICIENT_C03_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C10 (0x00000410) +#define NVC57E_SET_FMT_COEFFICIENT_C10_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C11 (0x00000414) +#define NVC57E_SET_FMT_COEFFICIENT_C11_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C12 (0x00000418) +#define NVC57E_SET_FMT_COEFFICIENT_C12_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C13 (0x0000041C) +#define NVC57E_SET_FMT_COEFFICIENT_C13_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C20 (0x00000420) +#define NVC57E_SET_FMT_COEFFICIENT_C20_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C21 (0x00000424) +#define NVC57E_SET_FMT_COEFFICIENT_C21_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C22 (0x00000428) +#define NVC57E_SET_FMT_COEFFICIENT_C22_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C23 (0x0000042C) +#define NVC57E_SET_FMT_COEFFICIENT_C23_VALUE 20:0 +#define NVC57E_SET_ILUT_CONTROL (0x00000440) +#define NVC57E_SET_ILUT_CONTROL_INTERPOLATE 0:0 +#define NVC57E_SET_ILUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC57E_SET_ILUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC57E_SET_ILUT_CONTROL_MIRROR 1:1 +#define NVC57E_SET_ILUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC57E_SET_ILUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC57E_SET_ILUT_CONTROL_MODE 3:2 +#define NVC57E_SET_ILUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVC57E_SET_ILUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVC57E_SET_ILUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVC57E_SET_ILUT_CONTROL_SIZE 18:8 +#define NVC57E_SET_CONTEXT_DMA_ILUT (0x00000444) +#define NVC57E_SET_CONTEXT_DMA_ILUT_HANDLE 31:0 +#define NVC57E_SET_OFFSET_ILUT (0x00000448) +#define NVC57E_SET_OFFSET_ILUT_ORIGIN 31:0 +#define NVC57E_SET_CSC00CONTROL (0x0000045C) +#define NVC57E_SET_CSC00CONTROL_ENABLE 0:0 +#define NVC57E_SET_CSC00CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57E_SET_CSC00CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57E_SET_CSC00COEFFICIENT_C00 (0x00000460) +#define NVC57E_SET_CSC00COEFFICIENT_C00_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C01 (0x00000464) +#define NVC57E_SET_CSC00COEFFICIENT_C01_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C02 (0x00000468) +#define NVC57E_SET_CSC00COEFFICIENT_C02_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C03 (0x0000046C) +#define NVC57E_SET_CSC00COEFFICIENT_C03_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C10 (0x00000470) +#define NVC57E_SET_CSC00COEFFICIENT_C10_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C11 (0x00000474) +#define NVC57E_SET_CSC00COEFFICIENT_C11_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C12 (0x00000478) +#define NVC57E_SET_CSC00COEFFICIENT_C12_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C13 (0x0000047C) +#define NVC57E_SET_CSC00COEFFICIENT_C13_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C20 (0x00000480) +#define NVC57E_SET_CSC00COEFFICIENT_C20_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C21 (0x00000484) +#define NVC57E_SET_CSC00COEFFICIENT_C21_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C22 (0x00000488) +#define NVC57E_SET_CSC00COEFFICIENT_C22_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C23 (0x0000048C) +#define NVC57E_SET_CSC00COEFFICIENT_C23_VALUE 20:0 +#define NVC57E_SET_CSC0LUT_CONTROL (0x000004A0) +#define NVC57E_SET_CSC0LUT_CONTROL_INTERPOLATE 0:0 +#define NVC57E_SET_CSC0LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC57E_SET_CSC0LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC57E_SET_CSC0LUT_CONTROL_MIRROR 1:1 +#define NVC57E_SET_CSC0LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC57E_SET_CSC0LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC57E_SET_CSC0LUT_CONTROL_ENABLE 4:4 +#define NVC57E_SET_CSC0LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57E_SET_CSC0LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57E_SET_CSC0LUT_SEGMENT_SIZE (0x000004A4) +#define NVC57E_SET_CSC0LUT_SEGMENT_SIZE_IDX 5:0 +#define NVC57E_SET_CSC0LUT_SEGMENT_SIZE_VALUE 18:16 +#define NVC57E_SET_CSC0LUT_ENTRY (0x000004A8) +#define NVC57E_SET_CSC0LUT_ENTRY_IDX 10:0 +#define NVC57E_SET_CSC0LUT_ENTRY_VALUE 31:16 +#define NVC57E_SET_CSC01CONTROL (0x000004BC) +#define NVC57E_SET_CSC01CONTROL_ENABLE 0:0 +#define NVC57E_SET_CSC01CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57E_SET_CSC01CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57E_SET_CSC01COEFFICIENT_C00 (0x000004C0) +#define NVC57E_SET_CSC01COEFFICIENT_C00_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C01 (0x000004C4) +#define NVC57E_SET_CSC01COEFFICIENT_C01_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C02 (0x000004C8) +#define NVC57E_SET_CSC01COEFFICIENT_C02_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C03 (0x000004CC) +#define NVC57E_SET_CSC01COEFFICIENT_C03_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C10 (0x000004D0) +#define NVC57E_SET_CSC01COEFFICIENT_C10_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C11 (0x000004D4) +#define NVC57E_SET_CSC01COEFFICIENT_C11_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C12 (0x000004D8) +#define NVC57E_SET_CSC01COEFFICIENT_C12_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C13 (0x000004DC) +#define NVC57E_SET_CSC01COEFFICIENT_C13_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C20 (0x000004E0) +#define NVC57E_SET_CSC01COEFFICIENT_C20_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C21 (0x000004E4) +#define NVC57E_SET_CSC01COEFFICIENT_C21_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C22 (0x000004E8) +#define NVC57E_SET_CSC01COEFFICIENT_C22_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C23 (0x000004EC) +#define NVC57E_SET_CSC01COEFFICIENT_C23_VALUE 20:0 +#define NVC57E_SET_TMO_CONTROL (0x00000500) +#define NVC57E_SET_TMO_CONTROL_INTERPOLATE 0:0 +#define NVC57E_SET_TMO_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC57E_SET_TMO_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC57E_SET_TMO_CONTROL_SAT_MODE 3:2 +#define NVC57E_SET_TMO_CONTROL_SIZE 18:8 +#define NVC57E_SET_TMO_LOW_INTENSITY_ZONE (0x00000508) +#define NVC57E_SET_TMO_LOW_INTENSITY_ZONE_END 29:16 +#define NVC57E_SET_TMO_LOW_INTENSITY_VALUE (0x0000050C) +#define NVC57E_SET_TMO_LOW_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVC57E_SET_TMO_LOW_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVC57E_SET_TMO_LOW_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVC57E_SET_TMO_MEDIUM_INTENSITY_ZONE (0x00000510) +#define NVC57E_SET_TMO_MEDIUM_INTENSITY_ZONE_START 13:0 +#define NVC57E_SET_TMO_MEDIUM_INTENSITY_ZONE_END 29:16 +#define NVC57E_SET_TMO_MEDIUM_INTENSITY_VALUE (0x00000514) +#define NVC57E_SET_TMO_MEDIUM_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVC57E_SET_TMO_MEDIUM_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVC57E_SET_TMO_MEDIUM_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVC57E_SET_TMO_HIGH_INTENSITY_ZONE (0x00000518) +#define NVC57E_SET_TMO_HIGH_INTENSITY_ZONE_START 13:0 +#define NVC57E_SET_TMO_HIGH_INTENSITY_VALUE (0x0000051C) +#define NVC57E_SET_TMO_HIGH_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVC57E_SET_TMO_HIGH_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVC57E_SET_TMO_HIGH_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVC57E_SET_CONTEXT_DMA_TMO_LUT (0x00000528) +#define NVC57E_SET_CONTEXT_DMA_TMO_LUT_HANDLE 31:0 +#define NVC57E_SET_OFFSET_TMO_LUT (0x0000052C) +#define NVC57E_SET_OFFSET_TMO_LUT_ORIGIN 31:0 +#define NVC57E_SET_CSC10CONTROL (0x0000053C) +#define NVC57E_SET_CSC10CONTROL_ENABLE 0:0 +#define NVC57E_SET_CSC10CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57E_SET_CSC10CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57E_SET_CSC10COEFFICIENT_C00 (0x00000540) +#define NVC57E_SET_CSC10COEFFICIENT_C00_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C01 (0x00000544) +#define NVC57E_SET_CSC10COEFFICIENT_C01_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C02 (0x00000548) +#define NVC57E_SET_CSC10COEFFICIENT_C02_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C03 (0x0000054C) +#define NVC57E_SET_CSC10COEFFICIENT_C03_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C10 (0x00000550) +#define NVC57E_SET_CSC10COEFFICIENT_C10_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C11 (0x00000554) +#define NVC57E_SET_CSC10COEFFICIENT_C11_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C12 (0x00000558) +#define NVC57E_SET_CSC10COEFFICIENT_C12_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C13 (0x0000055C) +#define NVC57E_SET_CSC10COEFFICIENT_C13_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C20 (0x00000560) +#define NVC57E_SET_CSC10COEFFICIENT_C20_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C21 (0x00000564) +#define NVC57E_SET_CSC10COEFFICIENT_C21_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C22 (0x00000568) +#define NVC57E_SET_CSC10COEFFICIENT_C22_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C23 (0x0000056C) +#define NVC57E_SET_CSC10COEFFICIENT_C23_VALUE 20:0 +#define NVC57E_SET_CSC1LUT_CONTROL (0x00000580) +#define NVC57E_SET_CSC1LUT_CONTROL_INTERPOLATE 0:0 +#define NVC57E_SET_CSC1LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC57E_SET_CSC1LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC57E_SET_CSC1LUT_CONTROL_MIRROR 1:1 +#define NVC57E_SET_CSC1LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC57E_SET_CSC1LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC57E_SET_CSC1LUT_CONTROL_ENABLE 4:4 +#define NVC57E_SET_CSC1LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57E_SET_CSC1LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57E_SET_CSC1LUT_SEGMENT_SIZE (0x00000584) +#define NVC57E_SET_CSC1LUT_SEGMENT_SIZE_IDX 5:0 +#define NVC57E_SET_CSC1LUT_SEGMENT_SIZE_VALUE 18:16 +#define NVC57E_SET_CSC1LUT_ENTRY (0x00000588) +#define NVC57E_SET_CSC1LUT_ENTRY_IDX 10:0 +#define NVC57E_SET_CSC1LUT_ENTRY_VALUE 31:16 +#define NVC57E_SET_CSC11CONTROL (0x0000059C) +#define NVC57E_SET_CSC11CONTROL_ENABLE 0:0 +#define NVC57E_SET_CSC11CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57E_SET_CSC11CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57E_SET_CSC11COEFFICIENT_C00 (0x000005A0) +#define NVC57E_SET_CSC11COEFFICIENT_C00_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C01 (0x000005A4) +#define NVC57E_SET_CSC11COEFFICIENT_C01_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C02 (0x000005A8) +#define NVC57E_SET_CSC11COEFFICIENT_C02_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C03 (0x000005AC) +#define NVC57E_SET_CSC11COEFFICIENT_C03_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C10 (0x000005B0) +#define NVC57E_SET_CSC11COEFFICIENT_C10_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C11 (0x000005B4) +#define NVC57E_SET_CSC11COEFFICIENT_C11_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C12 (0x000005B8) +#define NVC57E_SET_CSC11COEFFICIENT_C12_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C13 (0x000005BC) +#define NVC57E_SET_CSC11COEFFICIENT_C13_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C20 (0x000005C0) +#define NVC57E_SET_CSC11COEFFICIENT_C20_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C21 (0x000005C4) +#define NVC57E_SET_CSC11COEFFICIENT_C21_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C22 (0x000005C8) +#define NVC57E_SET_CSC11COEFFICIENT_C22_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C23 (0x000005CC) +#define NVC57E_SET_CSC11COEFFICIENT_C23_VALUE 20:0 +#define NVC57E_SET_CLAMP_RANGE (0x000005D0) +#define NVC57E_SET_CLAMP_RANGE_LOW 15:0 +#define NVC57E_SET_CLAMP_RANGE_HIGH 31:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC57e_h diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc57esw.h b/userspace/sdks/nv525/nvidia/inc/class/clc57esw.h new file mode 100644 index 0000000..8c106b4 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc57esw.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2009-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc57e_sw_h_ +#define _clc57e_sw_h_ + +/* This file is *not* auto-generated. */ + +#define NVC57E_WINDOWS_NOTIFY_RM (0x0000058C) +#define NVC57E_WINDOWS_NOTIFY_RM_VSYNC_STATE_CHANGE 0:0 +#define NVC57E_WINDOWS_NOTIFY_RM_VSYNC_STATE_CHANGE_FALSE (0x00000000) +#define NVC57E_WINDOWS_NOTIFY_RM_VSYNC_STATE_CHANGE_TRUE (0x00000001) +#define NVC57E_WINDOWS_NOTIFY_RM_VSYNC_STATE 1:1 +#define NVC57E_WINDOWS_NOTIFY_RM_VSYNC_STATE_OFF (0x00000000) +#define NVC57E_WINDOWS_NOTIFY_RM_VSYNC_STATE_ON (0x00000001) +#define NVC57E_WINDOWS_NOTIFY_RM_ASSOCIATED_HEAD 7:4 + +#define SwSetMClkSwitch Reserved05[1] + +#define NVC57E_SW_SET_MCLK_SWITCH (0x000002B4) +#define NVC57E_SW_SET_MCLK_SWITCH_ENABLE 0:0 +#define NVC57E_SW_SET_MCLK_SWITCH_ENABLE_FALSE (0x00000000) +#define NVC57E_SW_SET_MCLK_SWITCH_ENABLE_TRUE (0x00000001) + +#endif // _clc57e_sw_h_ + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc58b.h b/userspace/sdks/nv525/nvidia/inc/class/clc58b.h new file mode 100644 index 0000000..7dba2c6 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc58b.h @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc58b.finn +// + +#define TURING_VMMU_A (0xc58bU) /* finn: Evaluated from "TURING_VMMU_A_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* + * @brief NvAlloc parameters for TuringVmmuA class + * + * This class represents mapping between guest physical and system physical. + * Will also be used to represent VF specific state for a given guest. + * + * gfid [in] + * GFID of VF + */ + +#define TURING_VMMU_A_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc58bU) + +typedef struct TURING_VMMU_A_ALLOCATION_PARAMETERS { + NvHandle hHostVgpuDevice; +} TURING_VMMU_A_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc597.h b/userspace/sdks/nv525/nvidia/inc/class/clc597.h new file mode 100644 index 0000000..711dae1 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc597.h @@ -0,0 +1,4352 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_turing_a_h_ +#define _cl_turing_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl turing_a */ + +#include "nvtypes.h" + +#define TURING_A 0xC597 + +#define NVC597_SET_OBJECT 0x0000 +#define NVC597_SET_OBJECT_CLASS_ID 15:0 +#define NVC597_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC597_NO_OPERATION 0x0100 +#define NVC597_NO_OPERATION_V 31:0 + +#define NVC597_SET_NOTIFY_A 0x0104 +#define NVC597_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC597_SET_NOTIFY_B 0x0108 +#define NVC597_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC597_NOTIFY 0x010c +#define NVC597_NOTIFY_TYPE 31:0 +#define NVC597_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC597_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC597_WAIT_FOR_IDLE 0x0110 +#define NVC597_WAIT_FOR_IDLE_V 31:0 + +#define NVC597_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC597_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC597_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC597_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC597_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC597_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC597_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC597_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC597_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC597_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC597_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC597_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC597_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC597_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC597_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC597_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC597_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC597_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC597_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC597_SEND_GO_IDLE 0x013c +#define NVC597_SEND_GO_IDLE_V 31:0 + +#define NVC597_PM_TRIGGER 0x0140 +#define NVC597_PM_TRIGGER_V 31:0 + +#define NVC597_PM_TRIGGER_WFI 0x0144 +#define NVC597_PM_TRIGGER_WFI_V 31:0 + +#define NVC597_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC597_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC597_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC597_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC597_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC597_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC597_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC597_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC597_LINE_LENGTH_IN 0x0180 +#define NVC597_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC597_LINE_COUNT 0x0184 +#define NVC597_LINE_COUNT_VALUE 31:0 + +#define NVC597_OFFSET_OUT_UPPER 0x0188 +#define NVC597_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC597_OFFSET_OUT 0x018c +#define NVC597_OFFSET_OUT_VALUE 31:0 + +#define NVC597_PITCH_OUT 0x0190 +#define NVC597_PITCH_OUT_VALUE 31:0 + +#define NVC597_SET_DST_BLOCK_SIZE 0x0194 +#define NVC597_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC597_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC597_SET_DST_WIDTH 0x0198 +#define NVC597_SET_DST_WIDTH_V 31:0 + +#define NVC597_SET_DST_HEIGHT 0x019c +#define NVC597_SET_DST_HEIGHT_V 31:0 + +#define NVC597_SET_DST_DEPTH 0x01a0 +#define NVC597_SET_DST_DEPTH_V 31:0 + +#define NVC597_SET_DST_LAYER 0x01a4 +#define NVC597_SET_DST_LAYER_V 31:0 + +#define NVC597_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC597_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC597_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC597_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC597_LAUNCH_DMA 0x01b0 +#define NVC597_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC597_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC597_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC597_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC597_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC597_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC597_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC597_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC597_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC597_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC597_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC597_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC597_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC597_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC597_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC597_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC597_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC597_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC597_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC597_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC597_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC597_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC597_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC597_LOAD_INLINE_DATA 0x01b4 +#define NVC597_LOAD_INLINE_DATA_V 31:0 + +#define NVC597_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC597_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC597_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC597_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC597_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC597_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC597_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC597_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC597_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC597_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC597_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC597_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC597_RUN_DS_NOW 0x0200 +#define NVC597_RUN_DS_NOW_V 31:0 + +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC597_SET_GS_MODE 0x0208 +#define NVC597_SET_GS_MODE_TYPE 0:0 +#define NVC597_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVC597_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVC597_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC597_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC597_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC597_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC597_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC597_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_GS_DM_FIFO 0x0214 +#define NVC597_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC597_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC597_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC597_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC597_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC597_INVALIDATE_SHADER_CACHES 0x021c +#define NVC597_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC597_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC597_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC597_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC597_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC597_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC597_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC597_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC597_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC597_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC597_SET_INSTANCE_COUNT 0x0220 +#define NVC597_SET_INSTANCE_COUNT_V 31:0 + +#define NVC597_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVC597_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVC597_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC597_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVC597_SET_MME_VERSION 0x0234 +#define NVC597_SET_MME_VERSION_MAJOR 7:0 + +#define NVC597_SET_INDEX_BUFFER_SIZE_A 0x0238 +#define NVC597_SET_INDEX_BUFFER_SIZE_A_UPPER 7:0 + +#define NVC597_SET_INDEX_BUFFER_SIZE_B 0x023c +#define NVC597_SET_INDEX_BUFFER_SIZE_B_LOWER 31:0 + +#define NVC597_SET_ROOT_TABLE_VISIBILITY(i) (0x0240+(i)*4) +#define NVC597_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP0_ENABLE 1:0 +#define NVC597_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP1_ENABLE 5:4 +#define NVC597_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP2_ENABLE 9:8 +#define NVC597_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP3_ENABLE 13:12 +#define NVC597_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP4_ENABLE 17:16 + +#define NVC597_SET_DRAW_CONTROL_A 0x0260 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY 3:0 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_POINTS 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_LINES 0x00000001 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_QUADS 0x00000007 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_PATCH 0x0000000E +#define NVC597_SET_DRAW_CONTROL_A_PRIMITIVE_ID 4:4 +#define NVC597_SET_DRAW_CONTROL_A_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ID 6:5 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ID_FIRST 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC597_SET_DRAW_CONTROL_A_SPLIT_MODE 8:7 +#define NVC597_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC597_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC597_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE 9:9 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 +#define NVC597_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX 10:10 +#define NVC597_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_FALSE 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_TRUE 0x00000001 +#define NVC597_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX 11:11 +#define NVC597_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_FALSE 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_TRUE 0x00000001 + +#define NVC597_SET_DRAW_CONTROL_B 0x0264 +#define NVC597_SET_DRAW_CONTROL_B_INSTANCE_COUNT 31:0 + +#define NVC597_DRAW_INDEX_BUFFER_BEGIN_END_A 0x0268 +#define NVC597_DRAW_INDEX_BUFFER_BEGIN_END_A_FIRST 31:0 + +#define NVC597_DRAW_INDEX_BUFFER_BEGIN_END_B 0x026c +#define NVC597_DRAW_INDEX_BUFFER_BEGIN_END_B_COUNT 31:0 + +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_A 0x0270 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_A_START 31:0 + +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_B 0x0274 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_B_COUNT 31:0 + +#define NVC597_INVALIDATE_RASTER_CACHE_NO_WFI 0x027c +#define NVC597_INVALIDATE_RASTER_CACHE_NO_WFI_V 0:0 + +#define NVC597_SET_COLOR_RENDER_TO_ZETA_SURFACE 0x02b8 +#define NVC597_SET_COLOR_RENDER_TO_ZETA_SURFACE_V 0:0 +#define NVC597_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_FALSE 0x00000000 +#define NVC597_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_TRUE 0x00000001 + +#define NVC597_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION 0x02bc +#define NVC597_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V 0:0 +#define NVC597_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_FALSE 0x00000000 +#define NVC597_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_TRUE 0x00000001 + +#define NVC597_INCREMENT_SYNC_POINT 0x02c8 +#define NVC597_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC597_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC597_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC597_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC597_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC597_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC597_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC597_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC597_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC597_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC597_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVC597_DECOMPRESS_SURFACE 0x02e0 +#define NVC597_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC597_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC597_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC597_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC597_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC597_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC597_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC597_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC597_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC597_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC597_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC597_SET_ZCULL_SUBREGION 0x02e8 +#define NVC597_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC597_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC597_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC597_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC597_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC597_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC597_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC597_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC597_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC597_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC597_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC597_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC597_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC597_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC597_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC597_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC597_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC597_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC597_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC597_DRAW_ZERO_INDEX 0x0304 +#define NVC597_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC597_SET_L1_CONFIGURATION 0x0308 +#define NVC597_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC597_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC597_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC597_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC597_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC597_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC597_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC597_SET_SPA_VERSION 0x0310 +#define NVC597_SET_SPA_VERSION_MINOR 7:0 +#define NVC597_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC597_SET_TIMESLICE_BATCH_LIMIT 0x0314 +#define NVC597_SET_TIMESLICE_BATCH_LIMIT_BATCH_LIMIT 15:0 + +#define NVC597_SET_SNAP_GRID_LINE 0x0318 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC597_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC597_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC597_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC597_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC597_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC597_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC597_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC597_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC597_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC597_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC597_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC597_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC597_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC597_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC597_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC597_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC597_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC597_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC597_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC597_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC597_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC597_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC597_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC597_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC597_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC597_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC597_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC597_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC597_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC597_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC597_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC597_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC597_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC597_RESERVED_TG07 0x033c +#define NVC597_RESERVED_TG07_V 0:0 + +#define NVC597_RESERVED_TG08 0x0340 +#define NVC597_RESERVED_TG08_V 0:0 + +#define NVC597_RESERVED_TG09 0x0344 +#define NVC597_RESERVED_TG09_V 0:0 + +#define NVC597_RESERVED_TG10 0x0348 +#define NVC597_RESERVED_TG10_V 0:0 + +#define NVC597_RESERVED_TG11 0x034c +#define NVC597_RESERVED_TG11_V 0:0 + +#define NVC597_RESERVED_TG12 0x0350 +#define NVC597_RESERVED_TG12_V 0:0 + +#define NVC597_RESERVED_TG13 0x0354 +#define NVC597_RESERVED_TG13_V 0:0 + +#define NVC597_RESERVED_TG14 0x0358 +#define NVC597_RESERVED_TG14_V 0:0 + +#define NVC597_RESERVED_TG15 0x035c +#define NVC597_RESERVED_TG15_V 0:0 + +#define NVC597_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC597_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC597_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC597_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC597_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC597_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC597_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC597_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC597_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC597_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC597_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC597_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC597_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC597_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC597_SET_RASTER_ENABLE 0x037c +#define NVC597_SET_RASTER_ENABLE_V 0:0 +#define NVC597_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC597_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC597_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC597_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC597_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC597_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC597_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC597_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC597_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC597_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC597_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVC597_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVC597_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVC597_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVC597_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVC597_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVC597_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVC597_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVC597_SET_ROOT_TABLE_SELECTOR 0x0504 +#define NVC597_SET_ROOT_TABLE_SELECTOR_ROOT_TABLE 2:0 +#define NVC597_SET_ROOT_TABLE_SELECTOR_OFFSET 15:8 + +#define NVC597_LOAD_ROOT_TABLE 0x0508 +#define NVC597_LOAD_ROOT_TABLE_V 31:0 + +#define NVC597_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVC597_SET_MME_MEM_ADDRESS_A_UPPER 7:0 + +#define NVC597_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVC597_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVC597_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVC597_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVC597_MME_DMA_READ 0x055c +#define NVC597_MME_DMA_READ_LENGTH 31:0 + +#define NVC597_MME_DMA_READ_FIFOED 0x0560 +#define NVC597_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVC597_MME_DMA_WRITE 0x0564 +#define NVC597_MME_DMA_WRITE_LENGTH 31:0 + +#define NVC597_MME_DMA_REDUCTION 0x0568 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVC597_MME_DMA_SYSMEMBAR 0x056c +#define NVC597_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVC597_MME_DMA_SYNC 0x0570 +#define NVC597_MME_DMA_SYNC_VALUE 31:0 + +#define NVC597_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NVC597_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NVC597_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NVC597_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NVC597_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NVC597_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NVC597_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NVC597_SET_VERTEX_STREAM_SIZE_A(j) (0x0600+(j)*8) +#define NVC597_SET_VERTEX_STREAM_SIZE_A_UPPER 7:0 + +#define NVC597_SET_VERTEX_STREAM_SIZE_B(j) (0x0604+(j)*8) +#define NVC597_SET_VERTEX_STREAM_SIZE_B_LOWER 31:0 + +#define NVC597_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC597_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC597_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC597_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC597_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC597_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC597_SET_RASTER_INPUT 0x0740 +#define NVC597_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC597_SET_STREAM_OUTPUT 0x0744 +#define NVC597_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC597_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC597_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC597_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC597_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC597_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC597_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC597_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC597_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC597_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC597_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC597_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC597_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC597_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC597_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC597_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC597_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC597_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC597_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC597_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC597_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC597_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC597_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC597_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC597_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC597_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVC597_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC597_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC597_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC597_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC597_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC597_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC597_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC597_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC597_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC597_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC597_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC597_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC597_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC597_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC597_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC597_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC597_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC597_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC597_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC597_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC597_SET_ZCULL_STORAGE_B 0x07ec +#define NVC597_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC597_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC597_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC597_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC597_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC597_SET_ZT_READ_ONLY 0x07f8 +#define NVC597_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC597_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC597_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC597_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC597_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC597_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC597_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC597_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC597_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC597_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC597_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC597_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC597_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC597_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC597_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC597_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC597_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC597_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC597_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC597_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC597_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC597_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC597_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC597_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC597_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC597_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC597_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC597_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC597_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC597_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC597_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC597_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC597_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC597_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC597_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC597_SET_COLOR_TARGET_RESERVED_A(j) (0x0824+(j)*64) +#define NVC597_SET_COLOR_TARGET_RESERVED_A_V 0:0 + +#define NVC597_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC597_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC597_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC597_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC597_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC597_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC597_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC597_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC597_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC597_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC597_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC597_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC597_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC597_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC597_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC597_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC597_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC597_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC597_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC597_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC597_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC597_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC597_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC597_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC597_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC597_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC597_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC597_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC597_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC597_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC597_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC597_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC597_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC597_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC597_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC597_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC597_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC597_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC597_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC597_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC597_SET_STATISTICS_COUNTER 0x0d68 +#define NVC597_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC597_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC597_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC597_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC597_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC597_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC597_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC597_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC597_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC597_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC597_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC597_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC597_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC597_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC597_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC597_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC597_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVC597_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC597_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC597_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC597_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC597_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC597_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC597_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC597_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC597_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC597_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC597_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC597_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC597_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC597_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC597_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC597_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC597_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC597_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC597_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC597_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC597_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC597_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC597_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC597_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC597_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC597_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC597_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC597_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC597_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC597_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC597_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC597_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC597_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC597_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC597_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC597_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC597_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC597_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC597_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC597_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC597_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC597_SET_POLY_SMOOTH 0x0db4 +#define NVC597_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC597_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC597_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC597_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC597_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC597_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC597_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC597_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC597_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC597_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_PATCH 0x0dcc +#define NVC597_SET_PATCH_SIZE 7:0 + +#define NVC597_SET_ITERATED_BLEND 0x0dd0 +#define NVC597_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC597_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC597_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC597_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC597_SET_ZCULL_CRITERION 0x0dd8 +#define NVC597_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC597_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC597_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC597_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC597_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC597_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC597_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC597_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC597_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC597_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC597_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC597_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC597_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC597_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC597_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC597_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC597_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC597_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC597_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC597_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC597_SET_SCISSOR_ENABLE_V 0:0 +#define NVC597_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC597_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC597_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC597_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC597_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC597_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC597_SET_VPC_PERF_KNOB 0x0f14 +#define NVC597_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC597_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC597_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC597_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC597_PM_LOCAL_TRIGGER 0x0f18 +#define NVC597_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC597_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC597_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC597_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC597_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC597_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC597_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC597_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC597_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC597_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC597_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC597_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC597_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC597_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC597_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC597_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC597_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC597_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC597_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC597_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC597_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC597_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC597_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC597_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC597_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC597_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC597_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC597_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC597_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC597_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC597_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC597_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC597_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC597_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC597_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC597_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC597_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC597_SET_SAMPLE_MASK 0x0fa4 +#define NVC597_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC597_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC597_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC597_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC597_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC597_SET_CT_MRT_ENABLE 0x0fac +#define NVC597_SET_CT_MRT_ENABLE_V 0:0 +#define NVC597_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC597_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC597_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC597_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC597_SET_TIR 0x0fb4 +#define NVC597_SET_TIR_MODE 1:0 +#define NVC597_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC597_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC597_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC597_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC597_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC597_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC597_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC597_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC597_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC597_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC597_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC597_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC597_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC597_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC597_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC597_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC597_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC597_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC597_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC597_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_TIR_MODULATION 0x0fd4 +#define NVC597_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC597_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC597_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC597_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC597_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC597_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC597_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC597_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC597_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC597_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC597_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC597_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC597_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC597_SET_ZT_A 0x0fe0 +#define NVC597_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_ZT_B 0x0fe4 +#define NVC597_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_ZT_FORMAT 0x0fe8 +#define NVC597_SET_ZT_FORMAT_V 4:0 +#define NVC597_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC597_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC597_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC597_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC597_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC597_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC597_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC597_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC597_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC597_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC597_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC597_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC597_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC597_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC597_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC597_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC597_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC597_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC597_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC597_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC597_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC597_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC597_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC597_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC597_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC597_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC597_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC597_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC597_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC597_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC597_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC597_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC597_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC597_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC597_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC597_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC597_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC597_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC597_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC597_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC597_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC597_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC597_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC597_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC597_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC597_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD02 0x102c +#define NVC597_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC597_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC597_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC597_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC597_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC597_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC597_SET_SPARE_NOOP01 0x1044 +#define NVC597_SET_SPARE_NOOP01_V 31:0 + +#define NVC597_SET_SPARE_NOOP02 0x1048 +#define NVC597_SET_SPARE_NOOP02_V 31:0 + +#define NVC597_SET_SPARE_NOOP03 0x104c +#define NVC597_SET_SPARE_NOOP03_V 31:0 + +#define NVC597_SET_SPARE_NOOP04 0x1050 +#define NVC597_SET_SPARE_NOOP04_V 31:0 + +#define NVC597_SET_SPARE_NOOP05 0x1054 +#define NVC597_SET_SPARE_NOOP05_V 31:0 + +#define NVC597_SET_SPARE_NOOP06 0x1058 +#define NVC597_SET_SPARE_NOOP06_V 31:0 + +#define NVC597_SET_SPARE_NOOP07 0x105c +#define NVC597_SET_SPARE_NOOP07_V 31:0 + +#define NVC597_SET_SPARE_NOOP08 0x1060 +#define NVC597_SET_SPARE_NOOP08_V 31:0 + +#define NVC597_SET_SPARE_NOOP09 0x1064 +#define NVC597_SET_SPARE_NOOP09_V 31:0 + +#define NVC597_SET_SPARE_NOOP10 0x1068 +#define NVC597_SET_SPARE_NOOP10_V 31:0 + +#define NVC597_SET_SPARE_NOOP11 0x106c +#define NVC597_SET_SPARE_NOOP11_V 31:0 + +#define NVC597_SET_SPARE_NOOP12 0x1070 +#define NVC597_SET_SPARE_NOOP12_V 31:0 + +#define NVC597_SET_SPARE_NOOP13 0x1074 +#define NVC597_SET_SPARE_NOOP13_V 31:0 + +#define NVC597_SET_SPARE_NOOP14 0x1078 +#define NVC597_SET_SPARE_NOOP14_V 31:0 + +#define NVC597_SET_SPARE_NOOP15 0x107c +#define NVC597_SET_SPARE_NOOP15_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC597_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC597_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC597_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC597_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC597_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC597_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC597_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC597_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC597_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC597_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC597_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC597_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC597_UNBIND_ALL 0x10f4 +#define NVC597_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC597_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC597_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC597_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC597_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC597_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC597_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC597_NO_OPERATION_DATA_HI 0x110c +#define NVC597_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC597_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC597_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC597_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC597_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC597_PM_TRIGGER_END 0x1114 +#define NVC597_PM_TRIGGER_END_V 31:0 + +#define NVC597_SET_VERTEX_ID_BASE 0x1118 +#define NVC597_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC597_SET_STENCIL_COMPRESSION 0x111c +#define NVC597_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC597_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC597_SET_TIR_CONTROL 0x1130 +#define NVC597_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC597_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC597_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC597_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC597_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC597_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC597_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC597_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC597_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 + +#define NVC597_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC597_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC597_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC597_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC597_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC597_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC597_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC597_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC597_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC597_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC597_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC597_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC597_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC597_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC597_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC597_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC597_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC597_FLUSH_PENDING_WRITES 0x1144 +#define NVC597_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC597_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC597_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC597_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC597_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC597_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC597_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC597_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC597_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC597_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC597_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC597_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC597_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC597_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC597_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC597_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC597_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC597_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC597_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC597_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC597_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC597_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC597_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_SCREEN_STATE_MASK 0x1204 +#define NVC597_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC597_SET_ZT_SPARSE 0x1208 +#define NVC597_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC597_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC597_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC597_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_SET_CT_SELECT 0x121c +#define NVC597_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC597_SET_CT_SELECT_TARGET0 6:4 +#define NVC597_SET_CT_SELECT_TARGET1 9:7 +#define NVC597_SET_CT_SELECT_TARGET2 12:10 +#define NVC597_SET_CT_SELECT_TARGET3 15:13 +#define NVC597_SET_CT_SELECT_TARGET4 18:16 +#define NVC597_SET_CT_SELECT_TARGET5 21:19 +#define NVC597_SET_CT_SELECT_TARGET6 24:22 +#define NVC597_SET_CT_SELECT_TARGET7 27:25 + +#define NVC597_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC597_SET_ZT_SIZE_A 0x1228 +#define NVC597_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC597_SET_ZT_SIZE_B 0x122c +#define NVC597_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC597_SET_ZT_SIZE_C 0x1230 +#define NVC597_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC597_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC597_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC597_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC597_SET_SAMPLER_BINDING 0x1234 +#define NVC597_SET_SAMPLER_BINDING_V 0:0 +#define NVC597_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC597_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC597_DRAW_AUTO 0x123c +#define NVC597_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC597_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC597_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC597_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC597_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC597_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC597_SET_BACK_END_COPY_A 0x1264 +#define NVC597_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC597_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC597_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC597_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC597_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BACK_END_COPY_B 0x1268 +#define NVC597_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC597_SET_BACK_END_COPY_C 0x126c +#define NVC597_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC597_SET_BACK_END_COPY_D 0x1270 +#define NVC597_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC597_SET_BACK_END_COPY_E 0x1274 +#define NVC597_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC597_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC597_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVC597_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC597_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC597_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC597_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC597_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC597_CLEAR_ZCULL_REGION 0x12c8 +#define NVC597_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC597_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC597_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC597_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC597_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC597_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC597_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC597_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC597_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC597_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC597_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC597_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC597_SET_DEPTH_TEST 0x12cc +#define NVC597_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC597_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_FILL_MODE 0x12d0 +#define NVC597_SET_FILL_MODE_V 31:0 +#define NVC597_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC597_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC597_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC597_SET_SHADE_MODE 0x12d4 +#define NVC597_SET_SHADE_MODE_V 31:0 +#define NVC597_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC597_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC597_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC597_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC597_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC597_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC597_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC597_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC597_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC597_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC597_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC597_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_DEPTH_WRITE 0x12e8 +#define NVC597_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC597_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_ALPHA_TEST 0x12ec +#define NVC597_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC597_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC597_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC597_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC597_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC597_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC597_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC597_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC597_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC597_D3D_SET_CULL_MODE 0x1308 +#define NVC597_D3D_SET_CULL_MODE_V 31:0 +#define NVC597_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC597_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC597_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC597_SET_DEPTH_FUNC 0x130c +#define NVC597_SET_DEPTH_FUNC_V 31:0 +#define NVC597_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC597_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC597_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC597_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC597_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC597_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC597_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC597_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC597_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC597_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC597_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC597_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC597_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC597_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC597_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC597_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC597_SET_ALPHA_REF 0x1310 +#define NVC597_SET_ALPHA_REF_V 31:0 + +#define NVC597_SET_ALPHA_FUNC 0x1314 +#define NVC597_SET_ALPHA_FUNC_V 31:0 +#define NVC597_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC597_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC597_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC597_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC597_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC597_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC597_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC597_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC597_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC597_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC597_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC597_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC597_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC597_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC597_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC597_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC597_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC597_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC597_SET_BLEND_CONST_RED 0x131c +#define NVC597_SET_BLEND_CONST_RED_V 31:0 + +#define NVC597_SET_BLEND_CONST_GREEN 0x1320 +#define NVC597_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC597_SET_BLEND_CONST_BLUE 0x1324 +#define NVC597_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC597_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC597_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC597_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC597_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC597_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC597_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC597_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC597_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC597_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC597_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BLEND_COLOR_OP 0x1340 +#define NVC597_SET_BLEND_COLOR_OP_V 31:0 +#define NVC597_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC597_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC597_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC597_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC597_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC597_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC597_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC597_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC597_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC597_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_BLEND_ALPHA_OP 0x134c +#define NVC597_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC597_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC597_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC597_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC597_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC597_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC597_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC597_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC597_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC597_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC597_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC597_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC597_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC597_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC597_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC597_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BLEND(i) (0x1360+(i)*4) +#define NVC597_SET_BLEND_ENABLE 0:0 +#define NVC597_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_STENCIL_TEST 0x1380 +#define NVC597_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC597_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_STENCIL_OP_FAIL 0x1384 +#define NVC597_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC597_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC597_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC597_SET_STENCIL_OP_ZPASS 0x138c +#define NVC597_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC597_SET_STENCIL_FUNC 0x1390 +#define NVC597_SET_STENCIL_FUNC_V 31:0 +#define NVC597_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC597_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC597_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC597_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC597_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC597_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC597_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC597_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC597_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC597_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC597_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC597_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC597_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC597_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC597_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC597_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC597_SET_STENCIL_FUNC_REF 0x1394 +#define NVC597_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC597_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC597_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC597_SET_STENCIL_MASK 0x139c +#define NVC597_SET_STENCIL_MASK_V 7:0 + +#define NVC597_SET_DRAW_AUTO_START 0x13a4 +#define NVC597_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC597_SET_PS_SATURATE 0x13a8 +#define NVC597_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC597_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC597_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC597_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC597_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC597_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC597_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC597_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC597_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC597_SET_WINDOW_ORIGIN 0x13ac +#define NVC597_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC597_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC597_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC597_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC597_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC597_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC597_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC597_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC597_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC597_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC597_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC597_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC597_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC597_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC597_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC597_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC597_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC597_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC597_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC597_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC597_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC597_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC597_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC597_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC597_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC597_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC597_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC597_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC597_STORE_ZCULL 0x1464 +#define NVC597_STORE_ZCULL_V 0:0 + +#define NVC597_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC597_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC597_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC597_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC597_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC597_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC597_LOAD_ZCULL 0x1500 +#define NVC597_LOAD_ZCULL_V 0:0 + +#define NVC597_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC597_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC597_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC597_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC597_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC597_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC597_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC597_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC597_SET_USER_CLIP_ENABLE 0x1510 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC597_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC597_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC597_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_POINT_SIZE 0x1518 +#define NVC597_SET_POINT_SIZE_V 31:0 + +#define NVC597_SET_ZCULL_STATS 0x151c +#define NVC597_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC597_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_POINT_SPRITE 0x1520 +#define NVC597_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC597_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC597_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC597_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC597_CLEAR_REPORT_VALUE 0x1530 +#define NVC597_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC597_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC597_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC597_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC597_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC597_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC597_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVC597_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC597_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC597_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_ZT_SELECT 0x1538 +#define NVC597_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC597_SET_RENDER_ENABLE_A 0x1550 +#define NVC597_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_RENDER_ENABLE_B 0x1554 +#define NVC597_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_RENDER_ENABLE_C 0x1558 +#define NVC597_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC597_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC597_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC597_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC597_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC597_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC597_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC597_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC597_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC597_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC597_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC597_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC597_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC597_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC597_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC597_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC597_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_TEX_HEADER_POOL_C 0x157c +#define NVC597_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC597_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC597_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC597_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC597_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC597_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC597_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC597_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC597_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC597_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC597_SET_SRGB_WRITE 0x15b8 +#define NVC597_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC597_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_DEPTH_BIAS 0x15bc +#define NVC597_SET_DEPTH_BIAS_V 31:0 + +#define NVC597_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC597_SET_RT_LAYER 0x15cc +#define NVC597_SET_RT_LAYER_V 15:0 +#define NVC597_SET_RT_LAYER_CONTROL 16:16 +#define NVC597_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC597_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC597_SET_ANTI_ALIAS 0x15d0 +#define NVC597_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC597_SET_EDGE_FLAG 0x15e4 +#define NVC597_SET_EDGE_FLAG_V 0:0 +#define NVC597_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC597_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC597_DRAW_INLINE_INDEX 0x15e8 +#define NVC597_DRAW_INLINE_INDEX_V 31:0 + +#define NVC597_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC597_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC597_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC597_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC597_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC597_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC597_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC597_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC597_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC597_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC597_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC597_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC597_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC597_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC597_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC597_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC597_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC597_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC597_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC597_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC597_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC597_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC597_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC597_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC597_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC597_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC597_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC597_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC597_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC597_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC597_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC597_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC597_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC597_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC597_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC597_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC597_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC597_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC597_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC597_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC597_END 0x1614 +#define NVC597_END_V 0:0 + +#define NVC597_BEGIN 0x1618 +#define NVC597_BEGIN_OP 15:0 +#define NVC597_BEGIN_OP_POINTS 0x00000000 +#define NVC597_BEGIN_OP_LINES 0x00000001 +#define NVC597_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC597_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC597_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC597_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC597_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC597_BEGIN_OP_QUADS 0x00000007 +#define NVC597_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC597_BEGIN_OP_POLYGON 0x00000009 +#define NVC597_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC597_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC597_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_BEGIN_OP_PATCH 0x0000000E +#define NVC597_BEGIN_PRIMITIVE_ID 24:24 +#define NVC597_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC597_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC597_BEGIN_INSTANCE_ID 27:26 +#define NVC597_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC597_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC597_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC597_BEGIN_SPLIT_MODE 30:29 +#define NVC597_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC597_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC597_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC597_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC597_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVC597_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC597_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_VERTEX_ID_COPY 0x161c +#define NVC597_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC597_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC597_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC597_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC597_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC597_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC597_LOAD_PRIMITIVE_ID 0x1624 +#define NVC597_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC597_SET_SHADER_BASED_CULL 0x162c +#define NVC597_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC597_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC597_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC597_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_CLASS_VERSION 0x1638 +#define NVC597_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC597_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC597_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC597_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC597_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC597_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC597_SET_DA_OUTPUT 0x164c +#define NVC597_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC597_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC597_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC597_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC597_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_POINT_CENTER_MODE 0x165c +#define NVC597_SET_POINT_CENTER_MODE_V 31:0 +#define NVC597_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC597_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC597_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC597_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC597_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC597_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC597_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC597_SET_LINE_STIPPLE 0x166c +#define NVC597_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC597_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC597_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC597_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC597_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC597_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC597_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC597_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC597_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC597_SET_PROVOKING_VERTEX 0x1684 +#define NVC597_SET_PROVOKING_VERTEX_V 0:0 +#define NVC597_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC597_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC597_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC597_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC597_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_POLYGON_STIPPLE 0x168c +#define NVC597_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC597_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_SHADER_CONTROL 0x1690 +#define NVC597_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC597_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC597_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC597_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC597_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC597_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC597_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC597_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC597_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC597_CHECK_CLASS_VERSION 0x16a0 +#define NVC597_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC597_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC597_SET_SPH_VERSION 0x16a4 +#define NVC597_SET_SPH_VERSION_CURRENT 15:0 +#define NVC597_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC597_CHECK_SPH_VERSION 0x16a8 +#define NVC597_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC597_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC597_SET_SCG_GRAPHICS_PRIORITY 0x16bc +#define NVC597_SET_SCG_GRAPHICS_PRIORITY_PRIORITY 5:0 + +#define NVC597_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS(i) (0x16c0+(i)*4) +#define NVC597_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC597_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC597_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC597_SET_AAM_VERSION 0x1790 +#define NVC597_SET_AAM_VERSION_CURRENT 15:0 +#define NVC597_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC597_CHECK_AAM_VERSION 0x1794 +#define NVC597_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC597_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC597_SET_ZT_LAYER 0x179c +#define NVC597_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC597_SET_INDEX_BUFFER_A 0x17c8 +#define NVC597_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC597_SET_INDEX_BUFFER_B 0x17cc +#define NVC597_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC597_SET_INDEX_BUFFER_E 0x17d8 +#define NVC597_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC597_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC597_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC597_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC597_SET_INDEX_BUFFER_F 0x17dc +#define NVC597_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC597_DRAW_INDEX_BUFFER 0x17e0 +#define NVC597_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC597_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC597_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC597_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC597_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC597_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC597_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC597_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC597_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC597_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC597_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC597_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC597_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC597_OGL_SET_CULL 0x1918 +#define NVC597_OGL_SET_CULL_ENABLE 0:0 +#define NVC597_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC597_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC597_OGL_SET_FRONT_FACE 0x191c +#define NVC597_OGL_SET_FRONT_FACE_V 31:0 +#define NVC597_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC597_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC597_OGL_SET_CULL_FACE 0x1920 +#define NVC597_OGL_SET_CULL_FACE_V 31:0 +#define NVC597_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC597_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC597_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC597_SET_VIEWPORT_PIXEL 0x1924 +#define NVC597_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC597_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC597_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC597_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC597_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC597_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC597_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE 17:16 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_USE_FIELD_MIN_Z_ZERO_MAX_Z_ONE 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MIN_Z_MAX_Z 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_ZERO_ONE 0x00000002 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MINUS_INF_PLUS_INF 0x00000003 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC597_SET_USER_CLIP_OP 0x1940 +#define NVC597_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC597_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC597_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC597_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC597_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC597_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC597_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC597_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC597_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC597_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC597_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC597_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC597_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC597_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC597_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC597_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC597_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC597_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC597_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC597_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC597_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC597_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC597_INVALIDATE_ZCULL 0x1958 +#define NVC597_INVALIDATE_ZCULL_V 31:0 +#define NVC597_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC597_SET_ZCULL 0x1968 +#define NVC597_SET_ZCULL_Z_ENABLE 0:0 +#define NVC597_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC597_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_ZCULL_BOUNDS 0x196c +#define NVC597_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC597_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC597_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC597_ZCULL_SYNC 0x1978 +#define NVC597_ZCULL_SYNC_V 31:0 + +#define NVC597_SET_CLIP_ID_TEST 0x197c +#define NVC597_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC597_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC597_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC597_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC597_SET_CLIP_ID 0x1984 +#define NVC597_SET_CLIP_ID_V 31:0 + +#define NVC597_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC597_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC597_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC597_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC597_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC597_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC597_SET_LOGIC_OP 0x19c4 +#define NVC597_SET_LOGIC_OP_ENABLE 0:0 +#define NVC597_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC597_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC597_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC597_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC597_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC597_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC597_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC597_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC597_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC597_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC597_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC597_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC597_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC597_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC597_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC597_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC597_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC597_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC597_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC597_SET_Z_COMPRESSION 0x19cc +#define NVC597_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC597_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC597_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC597_CLEAR_SURFACE 0x19d0 +#define NVC597_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC597_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC597_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC597_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC597_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC597_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC597_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC597_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC597_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC597_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC597_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC597_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC597_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC597_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC597_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC597_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC597_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC597_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC597_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC597_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC597_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC597_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC597_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC597_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC597_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC597_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC597_PIPE_NOP 0x1a2c +#define NVC597_PIPE_NOP_V 31:0 + +#define NVC597_SET_SPARE00 0x1a30 +#define NVC597_SET_SPARE00_V 31:0 + +#define NVC597_SET_SPARE01 0x1a34 +#define NVC597_SET_SPARE01_V 31:0 + +#define NVC597_SET_SPARE02 0x1a38 +#define NVC597_SET_SPARE02_V 31:0 + +#define NVC597_SET_SPARE03 0x1a3c +#define NVC597_SET_SPARE03_V 31:0 + +#define NVC597_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC597_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC597_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC597_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC597_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC597_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC597_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC597_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC597_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC597_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC597_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC597_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC597_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC597_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC597_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC597_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC597_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC597_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC597_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC597_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC597_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC597_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC597_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC597_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC597_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC597_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC597_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC597_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC597_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC597_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC597_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC597_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC597_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC597_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC597_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC597_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC597_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC597_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC597_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC597_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC597_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC597_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC597_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC597_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC597_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC597_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC597_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC597_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC597_SET_PIPELINE_REGISTER_COUNT_V 8:0 + +#define NVC597_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC597_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC597_SET_PIPELINE_PROGRAM_ADDRESS_A(j) (0x2014+(j)*64) +#define NVC597_SET_PIPELINE_PROGRAM_ADDRESS_A_UPPER 7:0 + +#define NVC597_SET_PIPELINE_PROGRAM_ADDRESS_B(j) (0x2018+(j)*64) +#define NVC597_SET_PIPELINE_PROGRAM_ADDRESS_B_LOWER 31:0 + +#define NVC597_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVC597_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVC597_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC597_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC597_SET_FALCON00 0x2300 +#define NVC597_SET_FALCON00_V 31:0 + +#define NVC597_SET_FALCON01 0x2304 +#define NVC597_SET_FALCON01_V 31:0 + +#define NVC597_SET_FALCON02 0x2308 +#define NVC597_SET_FALCON02_V 31:0 + +#define NVC597_SET_FALCON03 0x230c +#define NVC597_SET_FALCON03_V 31:0 + +#define NVC597_SET_FALCON04 0x2310 +#define NVC597_SET_FALCON04_V 31:0 + +#define NVC597_SET_FALCON05 0x2314 +#define NVC597_SET_FALCON05_V 31:0 + +#define NVC597_SET_FALCON06 0x2318 +#define NVC597_SET_FALCON06_V 31:0 + +#define NVC597_SET_FALCON07 0x231c +#define NVC597_SET_FALCON07_V 31:0 + +#define NVC597_SET_FALCON08 0x2320 +#define NVC597_SET_FALCON08_V 31:0 + +#define NVC597_SET_FALCON09 0x2324 +#define NVC597_SET_FALCON09_V 31:0 + +#define NVC597_SET_FALCON10 0x2328 +#define NVC597_SET_FALCON10_V 31:0 + +#define NVC597_SET_FALCON11 0x232c +#define NVC597_SET_FALCON11_V 31:0 + +#define NVC597_SET_FALCON12 0x2330 +#define NVC597_SET_FALCON12_V 31:0 + +#define NVC597_SET_FALCON13 0x2334 +#define NVC597_SET_FALCON13_V 31:0 + +#define NVC597_SET_FALCON14 0x2338 +#define NVC597_SET_FALCON14_V 31:0 + +#define NVC597_SET_FALCON15 0x233c +#define NVC597_SET_FALCON15_V 31:0 + +#define NVC597_SET_FALCON16 0x2340 +#define NVC597_SET_FALCON16_V 31:0 + +#define NVC597_SET_FALCON17 0x2344 +#define NVC597_SET_FALCON17_V 31:0 + +#define NVC597_SET_FALCON18 0x2348 +#define NVC597_SET_FALCON18_V 31:0 + +#define NVC597_SET_FALCON19 0x234c +#define NVC597_SET_FALCON19_V 31:0 + +#define NVC597_SET_FALCON20 0x2350 +#define NVC597_SET_FALCON20_V 31:0 + +#define NVC597_SET_FALCON21 0x2354 +#define NVC597_SET_FALCON21_V 31:0 + +#define NVC597_SET_FALCON22 0x2358 +#define NVC597_SET_FALCON22_V 31:0 + +#define NVC597_SET_FALCON23 0x235c +#define NVC597_SET_FALCON23_V 31:0 + +#define NVC597_SET_FALCON24 0x2360 +#define NVC597_SET_FALCON24_V 31:0 + +#define NVC597_SET_FALCON25 0x2364 +#define NVC597_SET_FALCON25_V 31:0 + +#define NVC597_SET_FALCON26 0x2368 +#define NVC597_SET_FALCON26_V 31:0 + +#define NVC597_SET_FALCON27 0x236c +#define NVC597_SET_FALCON27_V 31:0 + +#define NVC597_SET_FALCON28 0x2370 +#define NVC597_SET_FALCON28_V 31:0 + +#define NVC597_SET_FALCON29 0x2374 +#define NVC597_SET_FALCON29_V 31:0 + +#define NVC597_SET_FALCON30 0x2378 +#define NVC597_SET_FALCON30_V 31:0 + +#define NVC597_SET_FALCON31 0x237c +#define NVC597_SET_FALCON31_V 31:0 + +#define NVC597_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC597_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC597_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC597_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC597_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC597_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC597_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC597_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC597_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC597_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC597_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC597_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC597_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC597_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC597_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC597_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC597_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC597_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC597_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC597_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC597_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC597_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC597_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC597_SET_TRAP_HANDLER_A 0x25f8 +#define NVC597_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC597_SET_TRAP_HANDLER_B 0x25fc +#define NVC597_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC597_SET_COLOR_CLAMP 0x2600 +#define NVC597_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC597_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC597_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BINDLESS_TEXTURE 0x2608 +#define NVC597_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVC597_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC597_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC597_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC597_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC597_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC597_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC597_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC597_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC597_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC597_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC597_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC597_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC597_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC597_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC597_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC597_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC597_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC597_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC597_CALL_MME_MACRO_V 31:0 + +#define NVC597_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC597_CALL_MME_DATA_V 31:0 + +#endif /* _cl_turing_a_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc5b5.h b/userspace/sdks/nv525/nvidia/inc/class/clc5b5.h new file mode 100644 index 0000000..cc3633e --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc5b5.h @@ -0,0 +1,282 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clc5b5_h_ +#define _clc5b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define TURING_DMA_COPY_A (0x0000C5B5) + +#define NVC5B5_NOP (0x00000100) +#define NVC5B5_NOP_PARAMETER 31:0 +#define NVC5B5_PM_TRIGGER (0x00000140) +#define NVC5B5_PM_TRIGGER_V 31:0 +#define NVC5B5_SET_SEMAPHORE_A (0x00000240) +#define NVC5B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC5B5_SET_SEMAPHORE_B (0x00000244) +#define NVC5B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC5B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC5B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC5B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC5B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC5B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC5B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC5B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC5B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC5B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC5B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC5B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC5B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC5B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC5B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC5B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC5B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC5B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC5B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC5B5_SET_SRC_PHYS_MODE_BASIC_KIND 5:2 +#define NVC5B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC5B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC5B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC5B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC5B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC5B5_SET_DST_PHYS_MODE_BASIC_KIND 5:2 +#define NVC5B5_LAUNCH_DMA (0x00000300) +#define NVC5B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC5B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC5B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC5B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC5B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC5B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC5B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC5B5_LAUNCH_DMA_FLUSH_TYPE 25:25 +#define NVC5B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000) +#define NVC5B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE (0x00000003) +#define NVC5B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC5B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC5B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC5B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC5B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC5B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC5B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC5B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC5B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC5B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC5B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC5B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC5B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC5B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC5B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC5B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC5B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC5B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC5B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC5B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC5B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC5B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC5B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC5B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC5B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC5B5_LAUNCH_DMA_SRC_BYPASS_L2 20:20 +#define NVC5B5_LAUNCH_DMA_SRC_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC5B5_LAUNCH_DMA_SRC_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC5B5_LAUNCH_DMA_DST_BYPASS_L2 21:21 +#define NVC5B5_LAUNCH_DMA_DST_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC5B5_LAUNCH_DMA_DST_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC5B5_LAUNCH_DMA_VPRMODE 23:22 +#define NVC5B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVC5B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC5B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC5B5_LAUNCH_DMA_DISABLE_PLC 26:26 +#define NVC5B5_LAUNCH_DMA_DISABLE_PLC_FALSE (0x00000000) +#define NVC5B5_LAUNCH_DMA_DISABLE_PLC_TRUE (0x00000001) +#define NVC5B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 +#define NVC5B5_OFFSET_IN_UPPER (0x00000400) +#define NVC5B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC5B5_OFFSET_IN_LOWER (0x00000404) +#define NVC5B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC5B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC5B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC5B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC5B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC5B5_PITCH_IN (0x00000410) +#define NVC5B5_PITCH_IN_VALUE 31:0 +#define NVC5B5_PITCH_OUT (0x00000414) +#define NVC5B5_PITCH_OUT_VALUE 31:0 +#define NVC5B5_LINE_LENGTH_IN (0x00000418) +#define NVC5B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC5B5_LINE_COUNT (0x0000041C) +#define NVC5B5_LINE_COUNT_VALUE 31:0 +#define NVC5B5_SET_REMAP_CONST_A (0x00000700) +#define NVC5B5_SET_REMAP_CONST_A_V 31:0 +#define NVC5B5_SET_REMAP_CONST_B (0x00000704) +#define NVC5B5_SET_REMAP_CONST_B_V 31:0 +#define NVC5B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC5B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC5B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC5B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC5B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC5B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC5B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC5B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC5B5_SET_DST_WIDTH (0x00000710) +#define NVC5B5_SET_DST_WIDTH_V 31:0 +#define NVC5B5_SET_DST_HEIGHT (0x00000714) +#define NVC5B5_SET_DST_HEIGHT_V 31:0 +#define NVC5B5_SET_DST_DEPTH (0x00000718) +#define NVC5B5_SET_DST_DEPTH_V 31:0 +#define NVC5B5_SET_DST_LAYER (0x0000071C) +#define NVC5B5_SET_DST_LAYER_V 31:0 +#define NVC5B5_SET_DST_ORIGIN (0x00000720) +#define NVC5B5_SET_DST_ORIGIN_X 15:0 +#define NVC5B5_SET_DST_ORIGIN_Y 31:16 +#define NVC5B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC5B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC5B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC5B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC5B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC5B5_SET_SRC_WIDTH (0x0000072C) +#define NVC5B5_SET_SRC_WIDTH_V 31:0 +#define NVC5B5_SET_SRC_HEIGHT (0x00000730) +#define NVC5B5_SET_SRC_HEIGHT_V 31:0 +#define NVC5B5_SET_SRC_DEPTH (0x00000734) +#define NVC5B5_SET_SRC_DEPTH_V 31:0 +#define NVC5B5_SET_SRC_LAYER (0x00000738) +#define NVC5B5_SET_SRC_LAYER_V 31:0 +#define NVC5B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC5B5_SET_SRC_ORIGIN_X 15:0 +#define NVC5B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC5B5_SRC_ORIGIN_X (0x00000744) +#define NVC5B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC5B5_SRC_ORIGIN_Y (0x00000748) +#define NVC5B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC5B5_DST_ORIGIN_X (0x0000074C) +#define NVC5B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC5B5_DST_ORIGIN_Y (0x00000750) +#define NVC5B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC5B5_PM_TRIGGER_END (0x00001114) +#define NVC5B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc5b5_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc5b5sw.h b/userspace/sdks/nv525/nvidia/inc/class/clc5b5sw.h new file mode 100644 index 0000000..0295824 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc5b5sw.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc5b5sw.finn +// + + + +// +// Using VERSION_0 will cause the API to interpret +// engineType as a CE engine instance. This allows +// for backward compatibility with 85B5sw and 90B5sw. +// +#define NVC5B5_ALLOCATION_PARAMETERS_VERSION_0 0 + +// +// Using VERSION_1 will cause the API to interpret +// engineType as an NV2080_ENGINE_TYPE ordinal. +// +#define NVC5B5_ALLOCATION_PARAMETERS_VERSION_1 1 + +#define NVC5B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc5b5U) + +typedef struct NVC5B5_ALLOCATION_PARAMETERS { + NvU32 version; + NvU32 engineType; +} NVC5B5_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc5c0.h b/userspace/sdks/nv525/nvidia/inc/class/clc5c0.h new file mode 100644 index 0000000..51e0837 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc5c0.h @@ -0,0 +1,732 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_turing_compute_a_h_ +#define _cl_turing_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl turing_compute_a */ + +#include "nvtypes.h" + +#define TURING_COMPUTE_A 0xC5C0 + +#define NVC5C0_SET_OBJECT 0x0000 +#define NVC5C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC5C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC5C0_NO_OPERATION 0x0100 +#define NVC5C0_NO_OPERATION_V 31:0 + +#define NVC5C0_SET_NOTIFY_A 0x0104 +#define NVC5C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC5C0_SET_NOTIFY_B 0x0108 +#define NVC5C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_NOTIFY 0x010c +#define NVC5C0_NOTIFY_TYPE 31:0 +#define NVC5C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC5C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC5C0_WAIT_FOR_IDLE 0x0110 +#define NVC5C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC5C0_SEND_GO_IDLE 0x013c +#define NVC5C0_SEND_GO_IDLE_V 31:0 + +#define NVC5C0_PM_TRIGGER 0x0140 +#define NVC5C0_PM_TRIGGER_V 31:0 + +#define NVC5C0_PM_TRIGGER_WFI 0x0144 +#define NVC5C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC5C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC5C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC5C0_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC5C0_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC5C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC5C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC5C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC5C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC5C0_LINE_LENGTH_IN 0x0180 +#define NVC5C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC5C0_LINE_COUNT 0x0184 +#define NVC5C0_LINE_COUNT_VALUE 31:0 + +#define NVC5C0_OFFSET_OUT_UPPER 0x0188 +#define NVC5C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC5C0_OFFSET_OUT 0x018c +#define NVC5C0_OFFSET_OUT_VALUE 31:0 + +#define NVC5C0_PITCH_OUT 0x0190 +#define NVC5C0_PITCH_OUT_VALUE 31:0 + +#define NVC5C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC5C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC5C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC5C0_SET_DST_WIDTH 0x0198 +#define NVC5C0_SET_DST_WIDTH_V 31:0 + +#define NVC5C0_SET_DST_HEIGHT 0x019c +#define NVC5C0_SET_DST_HEIGHT_V 31:0 + +#define NVC5C0_SET_DST_DEPTH 0x01a0 +#define NVC5C0_SET_DST_DEPTH_V 31:0 + +#define NVC5C0_SET_DST_LAYER 0x01a4 +#define NVC5C0_SET_DST_LAYER_V 31:0 + +#define NVC5C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC5C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC5C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC5C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC5C0_LAUNCH_DMA 0x01b0 +#define NVC5C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC5C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC5C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC5C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC5C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC5C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC5C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC5C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC5C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC5C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC5C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC5C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC5C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC5C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC5C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC5C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC5C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC5C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC5C0_LOAD_INLINE_DATA 0x01b4 +#define NVC5C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC5C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC5C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC5C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC5C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC5C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC5C0_SET_SM_SCG_CONTROL 0x01e8 +#define NVC5C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS 0:0 +#define NVC5C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE 0x00000000 +#define NVC5C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE 0x00000001 + +#define NVC5C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC5C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC5C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC5C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC5C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC5C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC5C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC5C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC5C0_PERFMON_TRANSFER 0x0210 +#define NVC5C0_PERFMON_TRANSFER_V 31:0 + +#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_A 0x0214 +#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_A_ADDRESS_UPPER 7:0 + +#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_B 0x0218 +#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC5C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC5C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC5C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC5C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC5C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC5C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC5C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC5C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC5C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC5C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC5C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC5C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC5C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC5C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC5C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC5C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC5C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC5C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC5C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC5C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC5C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC5C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC5C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC5C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC5C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC5C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC5C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC5C0_SET_SCG_CONTROL 0x0270 +#define NVC5C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 +#define NVC5C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 +#define NVC5C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 +#define NVC5C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 +#define NVC5C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 + +#define NVC5C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC5C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC5C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC5C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC5C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC5C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC5C0_SET_QMD_VERSION 0x0288 +#define NVC5C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC5C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC5C0_CHECK_QMD_VERSION 0x0290 +#define NVC5C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC5C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC5C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC5C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL 0x029c +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_CONSTANT_BUFFER_MASK 7:0 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE 8:8 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE 12:12 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE 16:16 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE 20:20 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE 24:24 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_TRUE 0x00000001 + +#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC5C0_SCG_HYSTERESIS_CONTROL 0x02a8 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 + +#define NVC5C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC5C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC5C0_SEND_PCAS_A 0x02b4 +#define NVC5C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC5C0_SEND_PCAS_B 0x02b8 +#define NVC5C0_SEND_PCAS_B_FROM 23:0 +#define NVC5C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC5C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC5C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC5C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC5C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC5C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC5C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC5C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC5C0_SET_SKED_CACHE_CONTROL 0x02cc +#define NVC5C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID 0:0 +#define NVC5C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE 0x00000000 +#define NVC5C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE 0x00000001 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC5C0_SET_SPA_VERSION 0x0310 +#define NVC5C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC5C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC5C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC5C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC5C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC5C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC5C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC5C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC5C0_SET_FALCON00 0x0500 +#define NVC5C0_SET_FALCON00_V 31:0 + +#define NVC5C0_SET_FALCON01 0x0504 +#define NVC5C0_SET_FALCON01_V 31:0 + +#define NVC5C0_SET_FALCON02 0x0508 +#define NVC5C0_SET_FALCON02_V 31:0 + +#define NVC5C0_SET_FALCON03 0x050c +#define NVC5C0_SET_FALCON03_V 31:0 + +#define NVC5C0_SET_FALCON04 0x0510 +#define NVC5C0_SET_FALCON04_V 31:0 + +#define NVC5C0_SET_FALCON05 0x0514 +#define NVC5C0_SET_FALCON05_V 31:0 + +#define NVC5C0_SET_FALCON06 0x0518 +#define NVC5C0_SET_FALCON06_V 31:0 + +#define NVC5C0_SET_FALCON07 0x051c +#define NVC5C0_SET_FALCON07_V 31:0 + +#define NVC5C0_SET_FALCON08 0x0520 +#define NVC5C0_SET_FALCON08_V 31:0 + +#define NVC5C0_SET_FALCON09 0x0524 +#define NVC5C0_SET_FALCON09_V 31:0 + +#define NVC5C0_SET_FALCON10 0x0528 +#define NVC5C0_SET_FALCON10_V 31:0 + +#define NVC5C0_SET_FALCON11 0x052c +#define NVC5C0_SET_FALCON11_V 31:0 + +#define NVC5C0_SET_FALCON12 0x0530 +#define NVC5C0_SET_FALCON12_V 31:0 + +#define NVC5C0_SET_FALCON13 0x0534 +#define NVC5C0_SET_FALCON13_V 31:0 + +#define NVC5C0_SET_FALCON14 0x0538 +#define NVC5C0_SET_FALCON14_V 31:0 + +#define NVC5C0_SET_FALCON15 0x053c +#define NVC5C0_SET_FALCON15_V 31:0 + +#define NVC5C0_SET_FALCON16 0x0540 +#define NVC5C0_SET_FALCON16_V 31:0 + +#define NVC5C0_SET_FALCON17 0x0544 +#define NVC5C0_SET_FALCON17_V 31:0 + +#define NVC5C0_SET_FALCON18 0x0548 +#define NVC5C0_SET_FALCON18_V 31:0 + +#define NVC5C0_SET_FALCON19 0x054c +#define NVC5C0_SET_FALCON19_V 31:0 + +#define NVC5C0_SET_FALCON20 0x0550 +#define NVC5C0_SET_FALCON20_V 31:0 + +#define NVC5C0_SET_FALCON21 0x0554 +#define NVC5C0_SET_FALCON21_V 31:0 + +#define NVC5C0_SET_FALCON22 0x0558 +#define NVC5C0_SET_FALCON22_V 31:0 + +#define NVC5C0_SET_FALCON23 0x055c +#define NVC5C0_SET_FALCON23_V 31:0 + +#define NVC5C0_SET_FALCON24 0x0560 +#define NVC5C0_SET_FALCON24_V 31:0 + +#define NVC5C0_SET_FALCON25 0x0564 +#define NVC5C0_SET_FALCON25_V 31:0 + +#define NVC5C0_SET_FALCON26 0x0568 +#define NVC5C0_SET_FALCON26_V 31:0 + +#define NVC5C0_SET_FALCON27 0x056c +#define NVC5C0_SET_FALCON27_V 31:0 + +#define NVC5C0_SET_FALCON28 0x0570 +#define NVC5C0_SET_FALCON28_V 31:0 + +#define NVC5C0_SET_FALCON29 0x0574 +#define NVC5C0_SET_FALCON29_V 31:0 + +#define NVC5C0_SET_FALCON30 0x0578 +#define NVC5C0_SET_FALCON30_V 31:0 + +#define NVC5C0_SET_FALCON31 0x057c +#define NVC5C0_SET_FALCON31_V 31:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC5C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC5C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC5C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC5C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS(i) (0x0da0+(i)*4) +#define NVC5C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC5C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC5C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC5C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC5C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC5C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC5C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC5C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC5C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC5C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC5C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC5C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC5C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC5C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC5C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC5C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC5C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC5C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC5C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC5C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC5C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC5C0_PIPE_NOP 0x1a2c +#define NVC5C0_PIPE_NOP_V 31:0 + +#define NVC5C0_SET_SPARE00 0x1a30 +#define NVC5C0_SET_SPARE00_V 31:0 + +#define NVC5C0_SET_SPARE01 0x1a34 +#define NVC5C0_SET_SPARE01_V 31:0 + +#define NVC5C0_SET_SPARE02 0x1a38 +#define NVC5C0_SET_SPARE02_V 31:0 + +#define NVC5C0_SET_SPARE03 0x1a3c +#define NVC5C0_SET_SPARE03_V 31:0 + +#define NVC5C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC5C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC5C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC5C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC5C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC5C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC5C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC5C0_SET_TRAP_HANDLER_A 0x25f8 +#define NVC5C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC5C0_SET_TRAP_HANDLER_B 0x25fc +#define NVC5C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC5C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC5C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC5C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC5C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC5C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC5C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC5C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC5C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC5C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC5C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC5C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_turing_compute_a_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc637.h b/userspace/sdks/nv525/nvidia/inc/class/clc637.h new file mode 100644 index 0000000..65bed26 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc637.h @@ -0,0 +1,62 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc637.finn +// + +#define AMPERE_SMC_PARTITION_REF (0xc637U) /* finn: Evaluated from "NVC637_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +// +// This swizzId can be used by root clients like tools for device level +// profiling +// +#define NVC637_DEVICE_PROFILING_SWIZZID (0xFFFFFFFE) + +// +// TODO: Deprecate NVC637_DEVICE_LEVEL_SWIZZID once all the clients are moved to +// NVC637_DEVICE_PROFILING_SWIZZID +// +#define NVC637_DEVICE_LEVEL_SWIZZID NVC637_DEVICE_PROFILING_SWIZZID + +/* NvRmAlloc parameters */ +#define NVC637_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc637U) + +typedef struct NVC637_ALLOCATION_PARAMETERS { + // + // capDescriptor is a file descriptor for unix RM clients, but a void + // pointer for windows RM clients. + // + // capDescriptor is transparent to RM clients i.e. RM's user-mode shim + // populates this field on behalf of clients. + // + NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8); + + NvU32 swizzId; +} NVC637_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc638.h b/userspace/sdks/nv525/nvidia/inc/class/clc638.h new file mode 100644 index 0000000..73b3fda --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc638.h @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc638.finn +// + +#define AMPERE_SMC_EXEC_PARTITION_REF (0xc638U) /* finn: Evaluated from "NVC638_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* NvRmAlloc parameters */ +#define NVC638_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc638U) + +typedef struct NVC638_ALLOCATION_PARAMETERS { + // + // capDescriptor is a file descriptor for unix RM clients, but a void + // pointer for windows RM clients. + // + // capDescriptor is transparent to RM clients i.e. RM's user-mode shim + // populates this field on behalf of clients. + // + NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8); + + NvU32 execPartitionId; +} NVC638_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc639.h b/userspace/sdks/nv525/nvidia/inc/class/clc639.h new file mode 100644 index 0000000..d589de7 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc639.h @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc639.finn +// + +#define AMPERE_SMC_CONFIG_SESSION (0xc639U) /* finn: Evaluated from "NVC639_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* NvRmAlloc parameters */ +#define NVC639_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc639U) + +typedef struct NVC639_ALLOCATION_PARAMETERS { + // + // capDescriptor is a file descriptor for unix RM clients, but a void + // pointer for windows RM clients. + // + // capDescriptor is transparent to RM clients i.e. RM's user-mode shim + // populates this field on behalf of clients. + // + NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8); +} NVC639_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc640.h b/userspace/sdks/nv525/nvidia/inc/class/clc640.h new file mode 100644 index 0000000..214a45c --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc640.h @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc640.finn +// + +#define AMPERE_SMC_MONITOR_SESSION (0xc640U) /* finn: Evaluated from "NVC640_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* NvRmAlloc parameters */ +#define NVC640_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc640U) + +typedef struct NVC640_ALLOCATION_PARAMETERS { + // + // capDescriptor is a file descriptor for unix RM clients, but a void + // pointer for windows RM clients. + // + // capDescriptor is transparent to RM clients i.e. RM's user-mode shim + // populates this field on behalf of clients. + // + NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8); +} NVC640_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc661.h b/userspace/sdks/nv525/nvidia/inc/class/clc661.h new file mode 100644 index 0000000..d9f8a48 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc661.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clc661_h__ +#define __gh100_clc661_h__ +#define HOPPER_USERMODE_A (0xc661) +#endif // __gh100_clc661_h__ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc670.h b/userspace/sdks/nv525/nvidia/inc/class/clc670.h new file mode 100644 index 0000000..e46194d --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc670.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc670.finn +// + +#define NVC670_DISPLAY (0xc670U) /* finn: Evaluated from "NVC670_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NVC670_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc670U) + +typedef struct NVC670_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numDsis; // Number of DSIs in this chip/display +} NVC670_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc671.h b/userspace/sdks/nv525/nvidia/inc/class/clc671.h new file mode 100644 index 0000000..11f77d7 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc671.h @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc671_h_ +#define _clc671_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC671_DISP_SF_USER (0x000C671) + +typedef volatile struct _clc671_tag0 { + NvU32 dispSfUserOffset[0x400]; +} _NvC671DispSfUser, NvC671DispSfUserMap; + +#define NVC671_SF_HDMI_INFO_IDX_GENERIC_INFOFRAME 0x00000001 /* */ +#define NVC671_SF_HDMI_INFO_IDX_VSI 0x00000004 /* */ +#define NVC671_SF_HDMI_INFO_CTRL(i,j) (0x000E0000-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVC671_SF_HDMI_INFO_CTRL__SIZE_1 4 /* */ +#define NVC671_SF_HDMI_INFO_CTRL__SIZE_2 5 /* */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _clc671_h_ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc673.h b/userspace/sdks/nv525/nvidia/inc/class/clc673.h new file mode 100644 index 0000000..7ae1334 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc673.h @@ -0,0 +1,399 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc673_h_ +#define _clc673_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC673_DISP_CAPABILITIES 0xC673 + +typedef volatile struct _clc673_tag0 { + NvU32 dispCapabilities[0x400]; +} _NvC673DispCapabilities,NvC673DispCapabilities_Map ; + + +#define NVC673_SYS_CAP 0x0 /* RW-4R */ +#define NVC673_SYS_CAP_HEAD0_EXISTS 0:0 /* RWIVF */ +#define NVC673_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_HEAD1_EXISTS 1:1 /* RWIVF */ +#define NVC673_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_HEAD2_EXISTS 2:2 /* RWIVF */ +#define NVC673_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_HEAD3_EXISTS 3:3 /* RWIVF */ +#define NVC673_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_HEAD4_EXISTS 4:4 /* RWIVF */ +#define NVC673_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_HEAD5_EXISTS 5:5 /* RWIVF */ +#define NVC673_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_HEAD6_EXISTS 6:6 /* RWIVF */ +#define NVC673_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_HEAD7_EXISTS 7:7 /* RWIVF */ +#define NVC673_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVC673_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */ +#define NVC673_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR0_EXISTS 8:8 /* RWIVF */ +#define NVC673_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR1_EXISTS 9:9 /* RWIVF */ +#define NVC673_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR2_EXISTS 10:10 /* RWIVF */ +#define NVC673_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR3_EXISTS 11:11 /* RWIVF */ +#define NVC673_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR4_EXISTS 12:12 /* RWIVF */ +#define NVC673_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR5_EXISTS 13:13 /* RWIVF */ +#define NVC673_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR6_EXISTS 14:14 /* RWIVF */ +#define NVC673_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR7_EXISTS 15:15 /* RWIVF */ +#define NVC673_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* RWIVF */ +#define NVC673_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */ +#define NVC673_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_DSI0_EXISTS 20:20 /* RWIVF */ +#define NVC673_SYS_CAP_DSI0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_DSI0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_DSI1_EXISTS 21:21 /* RWIVF */ +#define NVC673_SYS_CAP_DSI1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_DSI1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_DSI2_EXISTS 22:22 /* RWIVF */ +#define NVC673_SYS_CAP_DSI2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_DSI2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_DSI3_EXISTS 23:23 /* RWIVF */ +#define NVC673_SYS_CAP_DSI3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_DSI3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_DSI_EXISTS(i) (20+(i)):(20+(i)) /* RWIVF */ +#define NVC673_SYS_CAP_DSI_EXISTS__SIZE_1 4 /* */ +#define NVC673_SYS_CAP_DSI_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_DSI_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA 0x10 /* RW-4R */ +#define NVC673_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES 15:0 /* RWIUF */ +#define NVC673_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH 17:16 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B 0x00000002 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B 0x00000003 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_ROTATION 18:18 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_ROTATION_FALSE 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_ROTATION_TRUE 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_PLANAR 19:19 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_PLANAR_FALSE 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_PLANAR_TRUE 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_VGA 20:20 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION 21:21 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_FALSE 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_TRUE 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MSCG 22:22 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MSCG_FALSE 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MSCG_TRUE 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH 23:23 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_FALSE 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_TRUE 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT 26:26 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION 31:30 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B 0x00000002 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B 0x00000003 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC 0x18 /* RW-4R */ +#define NVC673_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE 1:0 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_32B 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_64B 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_128B 0x00000002 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_256B 0x00000003 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED 6:4 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_NONE 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_TWO 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_FOUR 0x00000002 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_EIGHT 0x00000003 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_SIXTEEN 0x00000004 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR 11:11 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_FALSE 0x00000000 /* RWI-V */ +#define NVC673_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_TRUE 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP 12:12 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_FALSE 0x00000000 /* RWI-V */ +#define NVC673_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA(i) (0x680+(i)*32) /* RW-4A */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA__SIZE_1 8 /* */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT 16:16 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT 17:17 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT 18:18 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT 19:19 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT 20:20 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT 21:21 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT 22:22 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT 23:23 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT 24:24 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB(i) (0x684+(i)*32) /* RW-4A */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB__SIZE_1 8 /* */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_VGA 0:0 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_VGA_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_VGA_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGSZ 9:6 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGNR 12:10 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT 15:15 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC(i) (0x688+(i)*32) /* RW-4A */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC__SIZE_1 8 /* */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_OCSC0_PRECISION 4:0 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_OCSC1_PRECISION 12:8 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP 13:13 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_SF_PRECISION 20:16 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_CI_PRECISION 24:21 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB 25:25 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPD(i) (0x68c+(i)*32) /* RW-4A */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPD__SIZE_1 8 /* */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE(i) (0x690+(i)*32) /* RW-4A */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE__SIZE_1 8 /* */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE_DSC_RATEBUFSIZE 3:0 /* RWIUF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE_DSC_LINEBUFSIZE 13:8 /* RWIUF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422 16:16 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420 17:17 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPF(i) (0x694+(i)*32) /* RW-4A */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPF__SIZE_1 8 /* */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPF_VFILTER_MAX_PIXELS 15:0 /* RWIVF */ +#define NVC673_SOR_CAP(i) (0x144+(i)*8) /* RW-4A */ +#define NVC673_SOR_CAP__SIZE_1 8 /* */ +#define NVC673_SOR_CAP_SINGLE_LVDS_18 0:0 /* RWIVF */ +#define NVC673_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_SINGLE_LVDS_24 1:1 /* RWIVF */ +#define NVC673_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_DUAL_LVDS_18 2:2 /* RWIVF */ +#define NVC673_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_DUAL_LVDS_24 3:3 /* RWIVF */ +#define NVC673_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_SINGLE_TMDS_A 8:8 /* RWIVF */ +#define NVC673_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_SINGLE_TMDS_B 9:9 /* RWIVF */ +#define NVC673_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_DUAL_TMDS 11:11 /* RWIVF */ +#define NVC673_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* RWIVF */ +#define NVC673_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_SDI 16:16 /* RWIVF */ +#define NVC673_SOR_CAP_SDI_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_SDI_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_DP_A 24:24 /* RWIVF */ +#define NVC673_SOR_CAP_DP_A_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_DP_A_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_DP_B 25:25 /* RWIVF */ +#define NVC673_SOR_CAP_DP_B_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_DP_B_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_DP_INTERLACE 26:26 /* RWIVF */ +#define NVC673_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_DP_8_LANES 27:27 /* RWIVF */ +#define NVC673_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_HDMI_FRL 28:28 /* RWIVF */ +#define NVC673_SOR_CAP_HDMI_FRL_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_HDMI_FRL_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA(i) (0x780+(i)*32) /* RW-4A */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA__SIZE_1 32 /* */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH 13:10 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT 16:16 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT 17:17 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT 18:18 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT 19:19 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT 20:20 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT 21:21 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT 22:22 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT 23:23 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT 24:24 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB(i) (0x784+(i)*32) /* RW-4A */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB__SIZE_1 32 /* */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION 4:0 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ 9:6 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR 12:10 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT 15:15 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC(i) (0x788+(i)*32) /* RW-4A */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC__SIZE_1 32 /* */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION 4:0 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGSZ 9:6 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGNR 12:10 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT 15:15 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION 20:16 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP 21:21 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD(i) (0x78c+(i)*32) /* RW-4A */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD__SIZE_1 32 /* */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ 3:0 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR 6:4 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD 8:8 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT 9:9 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION 16:12 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION 20:17 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB 21:21 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA 22:22 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE(i) (0x790+(i)*32) /* RW-4A */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE__SIZE_1 32 /* */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION 4:0 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGSZ 9:6 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGNR 12:10 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT 15:15 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION 20:16 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP 21:21 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPF(i) (0x794+(i)*32) /* RW-4A */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPF__SIZE_1 32 /* */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */ + +#ifdef __cplusplus +}; +#endif /* extern C */ +#endif //_clc673_h_ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc67a.h b/userspace/sdks/nv525/nvidia/inc/class/clc67a.h new file mode 100644 index 0000000..ab6f1d4 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc67a.h @@ -0,0 +1,181 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + + +#ifndef _clc67a__h_ +#define _clc67a__h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC67A_CURSOR_IMM_CHANNEL_PIO (0x0000C67A) + +typedef volatile struct _clc67a_tag0 { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x7D]; + NvV32 Update; // 0x00000200 - 0x00000203 + NvV32 SetInterlockFlags; // 0x00000204 - 0x00000207 + NvV32 SetCursorHotSpotPointOut[2]; // 0x00000208 - 0x0000020F + NvV32 SetWindowInterlockFlags; // 0x00000210 - 0x00000213 + NvV32 Reserved02[0x37B]; +} NVC67ADispCursorImmControlPio; + +#define NVC67A_FREE (0x00000008) +#define NVC67A_FREE_COUNT 5:0 +#define NVC67A_UPDATE (0x00000200) +#define NVC67A_SET_INTERLOCK_FLAGS (0x00000204) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC67A_SET_CURSOR_HOT_SPOT_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVC67A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0 +#define NVC67A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS (0x00000210) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc67a_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc67b.h b/userspace/sdks/nv525/nvidia/inc/class/clc67b.h new file mode 100644 index 0000000..c9779a0 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc67b.h @@ -0,0 +1,66 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + + + +#ifndef _clC67b_h_ +#define _clC67b_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC67B_WINDOW_IMM_CHANNEL_DMA (0x0000C67B) + +// dma opcode instructions +#define NVC67B_DMA +#define NVC67B_DMA_OPCODE 31:29 +#define NVC67B_DMA_OPCODE_METHOD 0x00000000 +#define NVC67B_DMA_OPCODE_JUMP 0x00000001 +#define NVC67B_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC67B_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC67B_DMA_METHOD_COUNT 27:18 +#define NVC67B_DMA_METHOD_OFFSET 13:2 +#define NVC67B_DMA_DATA 31:0 +#define NVC67B_DMA_DATA_NOP 0x00000000 +#define NVC67B_DMA_JUMP_OFFSET 11:2 +#define NVC67B_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVC67B_PUT (0x00000000) +#define NVC67B_PUT_PTR 9:0 +#define NVC67B_GET (0x00000004) +#define NVC67B_GET_PTR 9:0 +#define NVC67B_UPDATE (0x00000200) +#define NVC67B_UPDATE_INTERLOCK_WITH_WINDOW 1:1 +#define NVC67B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC67B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC67B_SET_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVC67B_SET_POINT_OUT_X 15:0 +#define NVC67B_SET_POINT_OUT_Y 31:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC67b_h diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc67d.h b/userspace/sdks/nv525/nvidia/inc/class/clc67d.h new file mode 100644 index 0000000..dd2a4f6 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc67d.h @@ -0,0 +1,1339 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + + + +#ifndef _clC67d_h_ +#define _clC67d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC67D_CORE_CHANNEL_DMA (0x0000C67D) + +#define NV_DISP_NOTIFIER 0x00000000 +#define NV_DISP_NOTIFIER_SIZEOF 0x00000010 +#define NV_DISP_NOTIFIER__0 0x00000000 +#define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFIER__0_FIELD 8:8 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE 9:9 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001 +#define NV_DISP_NOTIFIER__0_R1 15:10 +#define NV_DISP_NOTIFIER__0_R2 23:16 +#define NV_DISP_NOTIFIER__0_R3 29:24 +#define NV_DISP_NOTIFIER__0_STATUS 31:30 +#define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002 +#define NV_DISP_NOTIFIER__1 0x00000001 +#define NV_DISP_NOTIFIER__1_R4 31:0 +#define NV_DISP_NOTIFIER__2 0x00000002 +#define NV_DISP_NOTIFIER__2_TIMESTAMP_LO 31:0 +#define NV_DISP_NOTIFIER__3 0x00000003 +#define NV_DISP_NOTIFIER__3_TIMESTAMP_HI 31:0 + + +// dma opcode instructions +#define NVC67D_DMA +#define NVC67D_DMA_OPCODE 31:29 +#define NVC67D_DMA_OPCODE_METHOD 0x00000000 +#define NVC67D_DMA_OPCODE_JUMP 0x00000001 +#define NVC67D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC67D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC67D_DMA_METHOD_COUNT 27:18 +#define NVC67D_DMA_METHOD_OFFSET 13:2 +#define NVC67D_DMA_DATA 31:0 +#define NVC67D_DMA_DATA_NOP 0x00000000 +#define NVC67D_DMA_JUMP_OFFSET 11:2 +#define NVC67D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// if cap SUPPORT_FLEXIBLE_WIN_MAPPING is FALSE, this define can be used to obtain which head a window is mapped to +#define NVC37D_WINDOW_MAPPED_TO_HEAD(w) ((w)>>1) +#define NVC37D_GET_VALID_WINDOWMASK_FOR_HEAD(h) ((1<<((h)*2)) | (1<<((h)*2+1))) + +// class methods +#define NVC67D_PUT (0x00000000) +#define NVC67D_PUT_PTR 9:0 +#define NVC67D_GET (0x00000004) +#define NVC67D_GET_PTR 9:0 +#define NVC67D_UPDATE (0x00000200) +#define NVC67D_UPDATE_SPECIAL_HANDLING 21:20 +#define NVC67D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NVC67D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NVC67D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NVC67D_UPDATE_SPECIAL_HANDLING_REASON 19:12 +#define NVC67D_UPDATE_INHIBIT_INTERRUPTS 24:24 +#define NVC67D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NVC67D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NVC67D_UPDATE_RELEASE_ELV 0:0 +#define NVC67D_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC67D_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC67D_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC67D_SET_CONTEXT_DMA_NOTIFIER (0x00000208) +#define NVC67D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NVC67D_SET_NOTIFIER_CONTROL (0x0000020C) +#define NVC67D_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC67D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC67D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC67D_SET_NOTIFIER_CONTROL_OFFSET 11:4 +#define NVC67D_SET_NOTIFIER_CONTROL_NOTIFY 12:12 +#define NVC67D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NVC67D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NVC67D_SET_CONTROL (0x00000210) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN(i) ((i)+0):((i)+0) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN__SIZE_1 4 +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN_DISABLE (0x00000000) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN_ENABLE (0x00000001) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN0 0:0 +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN0_DISABLE (0x00000000) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN0_ENABLE (0x00000001) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN1 1:1 +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN1_DISABLE (0x00000000) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN1_ENABLE (0x00000001) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN2 2:2 +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN2_DISABLE (0x00000000) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN2_ENABLE (0x00000001) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN3 3:3 +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN3_DISABLE (0x00000000) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN3_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS (0x00000218) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+0):((i)+0) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS (0x0000021C) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVC67D_GET_RG_SCAN_LINE(b) (0x00000220 + (b)*0x00000004) +#define NVC67D_GET_RG_SCAN_LINE_LINE 15:0 +#define NVC67D_GET_RG_SCAN_LINE_VBLANK 16:16 +#define NVC67D_GET_RG_SCAN_LINE_VBLANK_FALSE (0x00000000) +#define NVC67D_GET_RG_SCAN_LINE_VBLANK_TRUE (0x00000001) +#define NVC67D_SET_GET_BLANKING_CTRL(b) (0x00000240 + (b)*0x00000004) +#define NVC67D_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NVC67D_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NVC67D_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NVC67D_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NVC67D_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NVC67D_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) + +#define NVC67D_SOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK 7:0 +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVC67D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NVC67D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NVC67D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NVC67D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NVC67D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NVC67D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NVC67D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NVC67D_SOR_SET_CONTROL_PROTOCOL_HDMI_FRL (0x0000000C) +#define NVC67D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NVC67D_SOR_SET_CONTROL_DE_SYNC_POLARITY 16:16 +#define NVC67D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC67D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC67D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NVC67D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NVC67D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NVC67D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NVC67D_SOR_SET_CUSTOM_REASON(a) (0x00000304 + (a)*0x00000020) +#define NVC67D_SOR_SET_CUSTOM_REASON_CODE 31:0 +#define NVC67D_SOR_SET_SW_SPARE_A(a) (0x00000308 + (a)*0x00000020) +#define NVC67D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NVC67D_SOR_SET_SW_SPARE_B(a) (0x0000030C + (a)*0x00000020) +#define NVC67D_SOR_SET_SW_SPARE_B_CODE 31:0 + +#define NVC67D_DSI_SET_CONTROL(a) (0x00000500 + (a)*0x00000020) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK 7:0 +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVC67D_DSI_SET_CUSTOM_REASON(a) (0x00000504 + (a)*0x00000020) +#define NVC67D_DSI_SET_CUSTOM_REASON_CODE 31:0 +#define NVC67D_DSI_SET_SW_SPARE_A(a) (0x00000508 + (a)*0x00000020) +#define NVC67D_DSI_SET_SW_SPARE_A_CODE 31:0 +#define NVC67D_DSI_SET_SW_SPARE_B(a) (0x0000050C + (a)*0x00000020) +#define NVC67D_DSI_SET_SW_SPARE_B_CODE 31:0 + +#define NVC67D_WINDOW_SET_CONTROL(a) (0x00001000 + (a)*0x00000080) +#define NVC67D_WINDOW_SET_CONTROL_OWNER 3:0 +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD(i) (0x00000000 +(i)) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD__SIZE_1 8 +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD0 (0x00000000) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD1 (0x00000001) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD2 (0x00000002) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD3 (0x00000003) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD4 (0x00000004) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD5 (0x00000005) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD6 (0x00000006) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD7 (0x00000007) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_NONE (0x0000000F) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0x00000080) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a) (0x00001008 + (a)*0x00000080) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR(a) (0x0000100C + (a)*0x00000080) +#define NVC67D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVC67D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a) (0x00001010 + (a)*0x00000080) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_MAX_PIXELS_FETCHED_PER_LINE 14:0 +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED 16:16 +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED 28:28 +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS 22:20 +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED 24:24 +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED 30:30 +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED_TRUE (0x00000001) + +#define NVC67D_HEAD_SET_PROCAMP(a) (0x00002000 + (a)*0x00000400) +#define NVC67D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NVC67D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NVC67D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NVC67D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NVC67D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003) +#define NVC67D_HEAD_SET_PROCAMP_CHROMA_LPF 3:3 +#define NVC67D_HEAD_SET_PROCAMP_CHROMA_LPF_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_PROCAMP_CHROMA_LPF_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_PROCAMP_CHROMA_DOWN_V 4:4 +#define NVC67D_HEAD_SET_PROCAMP_CHROMA_DOWN_V_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_PROCAMP_CHROMA_DOWN_V_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 28:28 +#define NVC67D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NVC67D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00002004 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 2:2 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 3:3 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 7:4 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000003) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000004) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000005) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000006) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000007) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000008) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_444 (0x00000009) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444NP (0x0000000A) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 24:24 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 23:12 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN 31:26 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN0 (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN1 (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN2 (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN3 (0x00000003) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN4 (0x00000004) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN5 (0x00000005) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN6 (0x00000006) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN7 (0x00000007) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN8 (0x00000008) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN9 (0x00000009) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN10 (0x0000000A) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN11 (0x0000000B) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN12 (0x0000000C) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN13 (0x0000000D) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN14 (0x0000000E) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN15 (0x0000000F) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN16 (0x00000010) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN17 (0x00000011) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN18 (0x00000012) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN19 (0x00000013) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN20 (0x00000014) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN21 (0x00000015) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN22 (0x00000016) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN23 (0x00000017) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN24 (0x00000018) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN25 (0x00000019) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN26 (0x0000001A) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN27 (0x0000001B) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN28 (0x0000001C) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN29 (0x0000001D) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN30 (0x0000001E) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN31 (0x0000001F) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_NONE (0x0000003F) +#define NVC67D_HEAD_SET_CONTROL(a) (0x00002008 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CONTROL_STRUCTURE 1:0 +#define NVC67D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE 2:2 +#define NVC67D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_NORMAL (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_YUV420PACKER 3:3 +#define NVC67D_HEAD_SET_CONTROL_YUV420PACKER_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_YUV420PACKER_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 11:10 +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 8:4 +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 15:12 +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 23:22 +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 20:16 +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN 28:24 +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000003) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000004) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000005) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000006) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000007) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000008) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000009) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000B) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000C) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000D) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000E) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000F) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x00000010) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NVC67D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NVC67D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x0000200C + (a)*0x00000400) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC67D_HEAD_SET_PIXEL_REORDER_CONTROL(a) (0x00002010 + (a)*0x00000400) +#define NVC67D_HEAD_SET_PIXEL_REORDER_CONTROL_BANK_WIDTH 13:0 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00002014 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVC67D_HEAD_SET_DITHER_CONTROL(a) (0x00002018 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NVC67D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_DITHER_CONTROL_BITS 5:4 +#define NVC67D_HEAD_SET_DITHER_CONTROL_BITS_TO_6_BITS (0x00000000) +#define NVC67D_HEAD_SET_DITHER_CONTROL_BITS_TO_8_BITS (0x00000001) +#define NVC67D_HEAD_SET_DITHER_CONTROL_BITS_TO_10_BITS (0x00000002) +#define NVC67D_HEAD_SET_DITHER_CONTROL_BITS_TO_12_BITS (0x00000003) +#define NVC67D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE 2:2 +#define NVC67D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_DITHER_CONTROL_MODE 10:8 +#define NVC67D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NVC67D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NVC67D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NVC67D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NVC67D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NVC67D_HEAD_SET_DITHER_CONTROL_MODE_ROUND (0x00000005) +#define NVC67D_HEAD_SET_DITHER_CONTROL_PHASE 13:12 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x0000201C + (a)*0x00000400) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 0:0 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING 4:4 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 9:8 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NVC67D_HEAD_SET_DISPLAY_ID(a,b) (0x00002020 + (a)*0x00000400 + (b)*0x00000004) +#define NVC67D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00002028 + (a)*0x00000400) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC67D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR(a) (0x0000202C + (a)*0x00000400) +#define NVC67D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVC67D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS(a) (0x00002030 + (a)*0x00000400) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR 2:0 +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_NONE (0x00000000) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W32_H32 (0x00000001) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W64_H64 (0x00000002) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W128_H128 (0x00000003) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W256_H256 (0x00000004) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED 4:4 +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_FALSE (0x00000000) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_TRUE (0x00000001) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS 14:12 +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED 8:8 +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED 16:16 +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED_FALSE (0x00000000) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED_TRUE (0x00000001) +#define NVC67D_HEAD_SET_STALL_LOCK(a) (0x00002034 + (a)*0x00000400) +#define NVC67D_HEAD_SET_STALL_LOCK_ENABLE 0:0 +#define NVC67D_HEAD_SET_STALL_LOCK_ENABLE_FALSE (0x00000000) +#define NVC67D_HEAD_SET_STALL_LOCK_ENABLE_TRUE (0x00000001) +#define NVC67D_HEAD_SET_STALL_LOCK_MODE 2:2 +#define NVC67D_HEAD_SET_STALL_LOCK_MODE_CONTINUOUS (0x00000000) +#define NVC67D_HEAD_SET_STALL_LOCK_MODE_ONE_SHOT (0x00000001) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN 8:4 +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC67D_HEAD_SET_STALL_LOCK_UNSTALL_MODE 12:12 +#define NVC67D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_CRASH_LOCK (0x00000000) +#define NVC67D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_LINE_LOCK (0x00000001) +#define NVC67D_HEAD_SET_STALL_LOCK_TEPOLARITY 14:14 +#define NVC67D_HEAD_SET_STALL_LOCK_TEPOLARITY_POSITIVE_TRUE (0x00000000) +#define NVC67D_HEAD_SET_STALL_LOCK_TEPOLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC67D_HEAD_SET_STALL_LOCK_UNSTALL_SYNC_ADVANCE 25:16 +#define NVC67D_HEAD_SET_LOCK_CHAIN(a) (0x00002044 + (a)*0x00000400) +#define NVC67D_HEAD_SET_LOCK_CHAIN_POSITION 3:0 +#define NVC67D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x00002048 + (a)*0x00000400) +#define NVC67D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NVC67D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NVC67D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x0000204C + (a)*0x00000400) +#define NVC67D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NVC67D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NVC67D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x00002058 + (a)*0x00000400) +#define NVC67D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NVC67D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NVC67D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x0000205C + (a)*0x00000400) +#define NVC67D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NVC67D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NVC67D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000400) +#define NVC67D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NVC67D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NVC67D_HEAD_SET_RASTER_SYNC_END(a) (0x00002068 + (a)*0x00000400) +#define NVC67D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NVC67D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NVC67D_HEAD_SET_RASTER_BLANK_END(a) (0x0000206C + (a)*0x00000400) +#define NVC67D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NVC67D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NVC67D_HEAD_SET_RASTER_BLANK_START(a) (0x00002070 + (a)*0x00000400) +#define NVC67D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NVC67D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NVC67D_HEAD_SET_OVERSCAN_COLOR(a) (0x00002078 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OVERSCAN_COLOR_RED_CR 9:0 +#define NVC67D_HEAD_SET_OVERSCAN_COLOR_GREEN_Y 19:10 +#define NVC67D_HEAD_SET_OVERSCAN_COLOR_BLUE_CB 29:20 +#define NVC67D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR(a) (0x0000207C + (a)*0x00000400) +#define NVC67D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_RED_CR 9:0 +#define NVC67D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_GREEN_Y 19:10 +#define NVC67D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_BLUE_CB 29:20 +#define NVC67D_HEAD_SET_HDMI_CTRL(a) (0x00002080 + (a)*0x00000400) +#define NVC67D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NVC67D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NVC67D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NVC67D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NVC67D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NVC67D_HEAD_SET_CONTEXT_DMA_CURSOR(a,b) (0x00002088 + (a)*0x00000400 + (b)*0x00000004) +#define NVC67D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0 +#define NVC67D_HEAD_SET_OFFSET_CURSOR(a,b) (0x00002090 + (a)*0x00000400 + (b)*0x00000004) +#define NVC67D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0 +#define NVC67D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x00002098 + (a)*0x00000400) +#define NVC67D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 0:0 +#define NVC67D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NVC67D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_CURSOR(a) (0x0000209C + (a)*0x00000400) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_FORMAT 7:0 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_SIZE 9:8 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 19:12 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 27:20 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION(a) (0x000020A0 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_K1 7:0 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT 11:8 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT 15:12 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_ZERO (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE 16:16 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_BLEND (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_XOR (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS 20:20 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00002180 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NVC67D_HEAD_SET_CRC_CONTROL(a) (0x00002184 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 5:0 +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_0 (0x00000000) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_1 (0x00000001) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_2 (0x00000002) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_3 (0x00000003) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_4 (0x00000004) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_5 (0x00000005) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_6 (0x00000006) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_7 (0x00000007) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_8 (0x00000008) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_9 (0x00000009) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_10 (0x0000000A) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_11 (0x0000000B) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_12 (0x0000000C) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_13 (0x0000000D) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_14 (0x0000000E) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_15 (0x0000000F) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_16 (0x00000010) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_17 (0x00000011) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_18 (0x00000012) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_19 (0x00000013) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_20 (0x00000014) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_21 (0x00000015) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_22 (0x00000016) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_23 (0x00000017) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_24 (0x00000018) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_25 (0x00000019) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_26 (0x0000001A) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_27 (0x0000001B) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_28 (0x0000001C) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_29 (0x0000001D) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_30 (0x0000001E) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_31 (0x0000001F) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000020) +#define NVC67D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 8:8 +#define NVC67D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NVC67D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC 19:12 +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_NONE (0x00000000) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SF (0x00000030) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR__SIZE_1 8 +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR0 (0x00000050) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR1 (0x00000051) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR2 (0x00000052) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR3 (0x00000053) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR4 (0x00000054) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR5 (0x00000055) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR6 (0x00000056) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR7 (0x00000057) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC 27:20 +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_NONE (0x00000000) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SF (0x00000030) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR__SIZE_1 8 +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR0 (0x00000050) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR1 (0x00000051) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR2 (0x00000052) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR3 (0x00000053) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR4 (0x00000054) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR5 (0x00000055) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR6 (0x00000056) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR7 (0x00000057) +#define NVC67D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 9:9 +#define NVC67D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_PRESENT_CONTROL(a) (0x0000218C + (a)*0x00000400) +#define NVC67D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 0:0 +#define NVC67D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NVC67D_HEAD_SET_SW_SPARE_A(a) (0x00002194 + (a)*0x00000400) +#define NVC67D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NVC67D_HEAD_SET_SW_SPARE_B(a) (0x00002198 + (a)*0x00000400) +#define NVC67D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NVC67D_HEAD_SET_SW_SPARE_C(a) (0x0000219C + (a)*0x00000400) +#define NVC67D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NVC67D_HEAD_SET_SW_SPARE_D(a) (0x000021A0 + (a)*0x00000400) +#define NVC67D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NVC67D_HEAD_SET_DISPLAY_RATE(a) (0x000021A8 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DISPLAY_RATE_RUN_MODE 0:0 +#define NVC67D_HEAD_SET_DISPLAY_RATE_RUN_MODE_CONTINUOUS (0x00000000) +#define NVC67D_HEAD_SET_DISPLAY_RATE_RUN_MODE_ONE_SHOT (0x00000001) +#define NVC67D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_INTERVAL 25:4 +#define NVC67D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH 2:2 +#define NVC67D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_CONTEXT_DMA_RG_REL_SEMAPHORE(a,b) (0x000021AC + (a)*0x00000400 + (b)*0x00000004) +#define NVC67D_HEAD_SET_CONTEXT_DMA_RG_REL_SEMAPHORE_HANDLE 31:0 +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL(a,b) (0x000021CC + (a)*0x00000400 + (b)*0x00000004) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_OFFSET 7:0 +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE 14:14 +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE_WRITE (0x00000000) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE 10:10 +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE_ONE_TIME (0x00000000) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE_CONTINUOUS (0x00000001) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RASTER_LINE 30:16 +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_VALUE(a,b) (0x000021EC + (a)*0x00000400 + (b)*0x00000004) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_VALUE 31:0 +#define NVC67D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE(a) (0x00002214 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVC67D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVC67D_HEAD_SET_MIN_FRAME_IDLE(a) (0x00002218 + (a)*0x00000400) +#define NVC67D_HEAD_SET_MIN_FRAME_IDLE_LEADING_RASTER_LINES 14:0 +#define NVC67D_HEAD_SET_MIN_FRAME_IDLE_TRAILING_RASTER_LINES 30:16 +#define NVC67D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED(a) (0x00002220 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED_ALPHA 7:0 +#define NVC67D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED_RED 31:16 +#define NVC67D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE(a) (0x00002224 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE_GREEN 15:0 +#define NVC67D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE_BLUE 31:16 +#define NVC67D_HEAD_SET_CURSOR_COLOR_NORM_SCALE(a) (0x00002228 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CURSOR_COLOR_NORM_SCALE_VALUE 15:0 +#define NVC67D_HEAD_SET_XOR_BLEND_FACTOR(a) (0x0000222C + (a)*0x00000400) +#define NVC67D_HEAD_SET_XOR_BLEND_FACTOR_LOG2PEAK_LUMINANCE 3:0 +#define NVC67D_HEAD_SET_XOR_BLEND_FACTOR_S1 16:4 +#define NVC67D_HEAD_SET_XOR_BLEND_FACTOR_S2 30:18 +#define NVC67D_HEAD_SET_CLAMP_RANGE_GREEN(a) (0x00002238 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CLAMP_RANGE_GREEN_LOW 11:0 +#define NVC67D_HEAD_SET_CLAMP_RANGE_GREEN_HIGH 27:16 +#define NVC67D_HEAD_SET_CLAMP_RANGE_RED_BLUE(a) (0x0000223C + (a)*0x00000400) +#define NVC67D_HEAD_SET_CLAMP_RANGE_RED_BLUE_LOW 11:0 +#define NVC67D_HEAD_SET_CLAMP_RANGE_RED_BLUE_HIGH 27:16 +#define NVC67D_HEAD_SET_OCSC0CONTROL(a) (0x00002240 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0CONTROL_ENABLE 0:0 +#define NVC67D_HEAD_SET_OCSC0CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_OCSC0CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C00(a) (0x00002244 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C00_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C01(a) (0x00002248 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C01_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C02(a) (0x0000224C + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C02_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C03(a) (0x00002250 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C03_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C10(a) (0x00002254 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C10_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C11(a) (0x00002258 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C11_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C12(a) (0x0000225C + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C12_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C13(a) (0x00002260 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C13_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C20(a) (0x00002264 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C20_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C21(a) (0x00002268 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C21_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C22(a) (0x0000226C + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C22_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C23(a) (0x00002270 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C23_VALUE 20:0 +#define NVC67D_HEAD_SET_OLUT_CONTROL(a) (0x00002280 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OLUT_CONTROL_INTERPOLATE 0:0 +#define NVC67D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_OLUT_CONTROL_MIRROR 1:1 +#define NVC67D_HEAD_SET_OLUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_OLUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_OLUT_CONTROL_MODE 3:2 +#define NVC67D_HEAD_SET_OLUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVC67D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVC67D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVC67D_HEAD_SET_OLUT_CONTROL_SIZE 18:8 +#define NVC67D_HEAD_SET_OLUT_FP_NORM_SCALE(a) (0x00002284 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OLUT_FP_NORM_SCALE_VALUE 31:0 +#define NVC67D_HEAD_SET_CONTEXT_DMA_OLUT(a) (0x00002288 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CONTEXT_DMA_OLUT_HANDLE 31:0 +#define NVC67D_HEAD_SET_OFFSET_OLUT(a) (0x0000228C + (a)*0x00000400) +#define NVC67D_HEAD_SET_OFFSET_OLUT_ORIGIN 31:0 +#define NVC67D_HEAD_SET_OCSC1CONTROL(a) (0x0000229C + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1CONTROL_ENABLE 0:0 +#define NVC67D_HEAD_SET_OCSC1CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_OCSC1CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C00(a) (0x000022A0 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C00_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C01(a) (0x000022A4 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C01_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C02(a) (0x000022A8 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C02_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C03(a) (0x000022AC + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C03_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C10(a) (0x000022B0 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C10_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C11(a) (0x000022B4 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C11_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C12(a) (0x000022B8 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C12_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C13(a) (0x000022BC + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C13_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C20(a) (0x000022C0 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C20_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C21(a) (0x000022C4 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C21_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C22(a) (0x000022C8 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C22_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C23(a) (0x000022CC + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C23_VALUE 20:0 +#define NVC67D_HEAD_SET_TILE_POSITION(a) (0x000022D0 + (a)*0x00000400) +#define NVC67D_HEAD_SET_TILE_POSITION_X 2:0 +#define NVC67D_HEAD_SET_TILE_POSITION_Y 6:4 +#define NVC67D_HEAD_SET_DSC_CONTROL(a) (0x000022D4 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_CONTROL_ENABLE 0:0 +#define NVC67D_HEAD_SET_DSC_CONTROL_ENABLE_FALSE (0x00000000) +#define NVC67D_HEAD_SET_DSC_CONTROL_ENABLE_TRUE (0x00000001) +#define NVC67D_HEAD_SET_DSC_CONTROL_MODE 2:1 +#define NVC67D_HEAD_SET_DSC_CONTROL_MODE_SINGLE (0x00000000) +#define NVC67D_HEAD_SET_DSC_CONTROL_MODE_DUAL (0x00000001) +#define NVC67D_HEAD_SET_DSC_CONTROL_MODE_QUAD (0x00000002) +#define NVC67D_HEAD_SET_DSC_CONTROL_AUTO_RESET 3:3 +#define NVC67D_HEAD_SET_DSC_CONTROL_AUTO_RESET_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_DSC_CONTROL_AUTO_RESET_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION 4:4 +#define NVC67D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET 5:5 +#define NVC67D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET_FALSE (0x00000000) +#define NVC67D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET_TRUE (0x00000001) +#define NVC67D_HEAD_SET_DSC_CONTROL_FLATNESS_DET_THRESH 15:6 +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL(a) (0x000022D8 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_ENABLE 0:0 +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_ENABLE_FALSE (0x00000000) +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_ENABLE_TRUE (0x00000001) +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_LOCATION 1:1 +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_VSYNC (0x00000000) +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_VBLANK (0x00000001) +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_SIZE 9:2 +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY 10:10 +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY_ONCE (0x00000001) +#define NVC67D_HEAD_SET_DSC_PPS_HEAD(a) (0x000022DC + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_HEAD_BYTE0 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_HEAD_BYTE1 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_HEAD_BYTE2 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_HEAD_BYTE3 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA0(a) (0x000022E0 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA0_DSC_VERSION_MINOR 3:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA0_DSC_VERSION_MAJOR 7:4 +#define NVC67D_HEAD_SET_DSC_PPS_DATA0_PPS_IDENTIFIER 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA0_RESERVED 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA0_LINEBUF_DEPTH 27:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA0_BITS_PER_COMPONENT 31:28 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1(a) (0x000022E4 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_BITS_PER_PIXEL_HIGH 1:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_VBR_ENABLE 2:2 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_SIMPLE422 3:3 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_CONVERT_RGB 4:4 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_BLOCK_PRED_ENABLE 5:5 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_RESERVED 7:6 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_BITS_PER_PIXEL_LOW 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_PIC_HEIGHT_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_PIC_HEIGHT_LOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA2(a) (0x000022E8 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA2_PIC_WIDTH_HIGH 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA2_PIC_WIDTH_LOW 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA2_SLICE_HEIGHT_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA2_SLICE_HEIGHT_LOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA3(a) (0x000022EC + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA3_SLICE_WIDTH_HIGH 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA3_SLICE_WIDTH_LOW 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA3_CHUNK_SIZE_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA3_CHUNK_SIZE_LOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA4(a) (0x000022F0 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA4_INITIAL_XMIT_DELAY_HIGH 1:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA4_RESERVED 7:2 +#define NVC67D_HEAD_SET_DSC_PPS_DATA4_INITIAL_XMIT_DELAY_LOW 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA4_INITIAL_DEC_DELAY_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA4_INITIAL_DEC_DELAY_LOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA5(a) (0x000022F4 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA5_RESERVED0 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA5_INITIAL_SCALE_VALUE 13:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA5_RESERVED1 15:14 +#define NVC67D_HEAD_SET_DSC_PPS_DATA5_SCALE_INCREMENT_INTERVAL_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA5_SCALE_INCREMENT_INTERVAL_LOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA6(a) (0x000022F8 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA6_SCALE_DECREMENT_INTERVAL_HIGH 3:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA6_RESERVED0 7:4 +#define NVC67D_HEAD_SET_DSC_PPS_DATA6_SCALE_DECREMENT_INTERVAL_LOW 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA6_RESERVED1 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA6_FIRST_LINE_BPG_OFFSET 28:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA6_RESERVED2 31:29 +#define NVC67D_HEAD_SET_DSC_PPS_DATA7(a) (0x000022FC + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA7_NFL_BPG_OFFSET_HIGH 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA7_NFL_BPG_OFFSET_LOW 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA7_SLICE_BPG_OFFSET_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA7_SLICE_BPG_OFFSET_LOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA8(a) (0x00002300 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA8_INITIAL_OFFSET_HIGH 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA8_INITIAL_OFFSET_LOW 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA8_FINAL_OFFSET_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA8_FINAL_OFFSET_LOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA9(a) (0x00002304 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA9_FLATNESS_MIN_QP 4:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA9_RESERVED0 7:5 +#define NVC67D_HEAD_SET_DSC_PPS_DATA9_FLATNESS_MAX_QP 12:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA9_RESERVED1 15:13 +#define NVC67D_HEAD_SET_DSC_PPS_DATA9_RC_MODEL_SIZE_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA9_RC_MODEL_SIZE_LOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA10(a) (0x00002308 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA10_RC_EDGE_FACTOR 3:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA10_RESERVED0 7:4 +#define NVC67D_HEAD_SET_DSC_PPS_DATA10_RC_QUANT_INCR_LIMIT0 12:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA10_RESERVED1 15:13 +#define NVC67D_HEAD_SET_DSC_PPS_DATA10_RC_QUANT_INCR_LIMIT1 20:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA10_RESERVED2 23:21 +#define NVC67D_HEAD_SET_DSC_PPS_DATA10_RC_TGT_OFFSET_LO 27:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA10_RC_TGT_OFFSET_HI 31:28 +#define NVC67D_HEAD_SET_DSC_PPS_DATA11(a) (0x0000230C + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH0 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH1 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH2 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH3 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA12(a) (0x00002310 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH4 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH5 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH6 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH7 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA13(a) (0x00002314 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH8 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH9 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH10 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH11 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA14(a) (0x00002318 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA14_RC_BUF_THRESH12 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA14_RC_BUF_THRESH13 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MAX_QP_HIGH0 18:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MIN_QP0 23:19 +#define NVC67D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_BPG_OFFSET0 29:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MAX_QP_LOW0 31:30 +#define NVC67D_HEAD_SET_DSC_PPS_DATA15(a) (0x0000231C + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_HIGH1 2:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MIN_QP1 7:3 +#define NVC67D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_BPG_OFFSET1 13:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_LOW1 15:14 +#define NVC67D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_HIGH2 18:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MIN_QP2 23:19 +#define NVC67D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_BPG_OFFSET2 29:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_LOW2 31:30 +#define NVC67D_HEAD_SET_DSC_PPS_DATA16(a) (0x00002320 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_HIGH3 2:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MIN_QP3 7:3 +#define NVC67D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_BPG_OFFSET3 13:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_LOW3 15:14 +#define NVC67D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_HIGH4 18:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MIN_QP4 23:19 +#define NVC67D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_BPG_OFFSET4 29:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_LOW4 31:30 +#define NVC67D_HEAD_SET_DSC_PPS_DATA17(a) (0x00002324 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_HIGH5 2:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MIN_QP5 7:3 +#define NVC67D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_BPG_OFFSET5 13:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_LOW5 15:14 +#define NVC67D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_HIGH6 18:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MIN_QP6 23:19 +#define NVC67D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_BPG_OFFSET6 29:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_LOW6 31:30 +#define NVC67D_HEAD_SET_DSC_PPS_DATA18(a) (0x00002328 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_HIGH7 2:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MIN_QP7 7:3 +#define NVC67D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_BPG_OFFSET7 13:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_LOW7 15:14 +#define NVC67D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_HIGH8 18:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MIN_QP8 23:19 +#define NVC67D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_BPG_OFFSET8 29:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_LOW8 31:30 +#define NVC67D_HEAD_SET_DSC_PPS_DATA19(a) (0x0000232C + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_HIGH9 2:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MIN_QP9 7:3 +#define NVC67D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_BPG_OFFSET9 13:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_LOW9 15:14 +#define NVC67D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_HIGH10 18:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MIN_QP10 23:19 +#define NVC67D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_BPG_OFFSET10 29:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_LOW10 31:30 +#define NVC67D_HEAD_SET_DSC_PPS_DATA20(a) (0x00002330 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_HIGH11 2:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MIN_QP11 7:3 +#define NVC67D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_BPG_OFFSET11 13:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_LOW11 15:14 +#define NVC67D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_HIGH12 18:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MIN_QP12 23:19 +#define NVC67D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_BPG_OFFSET12 29:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_LOW12 31:30 +#define NVC67D_HEAD_SET_DSC_PPS_DATA21(a) (0x00002334 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_HIGH13 2:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MIN_QP13 7:3 +#define NVC67D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_BPG_OFFSET13 13:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_LOW13 15:14 +#define NVC67D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_HIGH14 18:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MIN_QP14 23:19 +#define NVC67D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_BPG_OFFSET14 29:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_LOW14 31:30 +#define NVC67D_HEAD_SET_DSC_PPS_DATA22(a) (0x00002338 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA22_NATIVE422 0:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA22_NATIVE420 1:1 +#define NVC67D_HEAD_SET_DSC_PPS_DATA22_RESERVED0 7:2 +#define NVC67D_HEAD_SET_DSC_PPS_DATA22_SECOND_LINE_BPG_OFFSET 12:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA22_RESERVED1 15:13 +#define NVC67D_HEAD_SET_DSC_PPS_DATA22_NSL_BPG_OFFSET_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA22_NSL_BPG_OFFSETLOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA23(a) (0x0000233C + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA23_SECOND_LINE_OFFSET_ADJ_HIGH 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA23_SECOND_LINE_OFFSET_ADJ_LOW 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA23_RESERVED 31:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA24(a) (0x00002340 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA24_RESERVED 31:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA25(a) (0x00002344 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA25_RESERVED 31:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA26(a) (0x00002348 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA26_RESERVED 31:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA27(a) (0x0000234C + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA27_RESERVED 31:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA28(a) (0x00002350 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA28_RESERVED 31:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA29(a) (0x00002354 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA29_RESERVED 31:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA30(a) (0x00002358 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA30_RESERVED 31:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA31(a) (0x0000235C + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA31_RESERVED 31:0 +#define NVC67D_HEAD_SET_RG_MERGE(a) (0x00002360 + (a)*0x00000400) +#define NVC67D_HEAD_SET_RG_MERGE_MODE 1:0 +#define NVC67D_HEAD_SET_RG_MERGE_MODE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_RG_MERGE_MODE_SETUP (0x00000001) +#define NVC67D_HEAD_SET_RG_MERGE_MODE_MASTER (0x00000002) +#define NVC67D_HEAD_SET_RG_MERGE_MODE_SLAVE (0x00000003) +#define NVC67D_HEAD_SET_RASTER_HBLANK_DELAY(a) (0x00002364 + (a)*0x00000400) +#define NVC67D_HEAD_SET_RASTER_HBLANK_DELAY_BLANK_START 15:0 +#define NVC67D_HEAD_SET_RASTER_HBLANK_DELAY_BLANK_END 31:16 +#define NVC67D_HEAD_SET_HDMI_DSC_HCACTIVE(a) (0x00002368 + (a)*0x00000400) +#define NVC67D_HEAD_SET_HDMI_DSC_HCACTIVE_BYTES 15:0 +#define NVC67D_HEAD_SET_HDMI_DSC_HCACTIVE_TRI_BYTES 31:16 +#define NVC67D_HEAD_SET_HDMI_DSC_HCBLANK(a) (0x0000236C + (a)*0x00000400) +#define NVC67D_HEAD_SET_HDMI_DSC_HCBLANK_WIDTH 15:0 +#define NVC67D_HEAD_SW_RESERVED(a,b) (0x00002370 + (a)*0x00000400 + (b)*0x00000004) +#define NVC67D_HEAD_SW_RESERVED_VALUE 31:0 +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_HI(a,b) (0x00002380 + (a)*0x00000400 + (b)*0x00000004) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_HI_VALUE 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC67d_h diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc67e.h b/userspace/sdks/nv525/nvidia/inc/class/clc67e.h new file mode 100644 index 0000000..516e6ea --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc67e.h @@ -0,0 +1,700 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + + + +#ifndef _clC67e_h_ +#define _clC67e_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC67E_WINDOW_CHANNEL_DMA (0x0000C67E) + +// dma opcode instructions +#define NVC67E_DMA +#define NVC67E_DMA_OPCODE 31:29 +#define NVC67E_DMA_OPCODE_METHOD 0x00000000 +#define NVC67E_DMA_OPCODE_JUMP 0x00000001 +#define NVC67E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC67E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC67E_DMA_METHOD_COUNT 27:18 +#define NVC67E_DMA_METHOD_OFFSET 13:2 +#define NVC67E_DMA_DATA 31:0 +#define NVC67E_DMA_DATA_NOP 0x00000000 +#define NVC67E_DMA_JUMP_OFFSET 11:2 +#define NVC67E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVC67E_PUT (0x00000000) +#define NVC67E_PUT_PTR 9:0 +#define NVC67E_GET (0x00000004) +#define NVC67E_GET_PTR 9:0 +#define NVC67E_UPDATE (0x00000200) +#define NVC67E_UPDATE_RELEASE_ELV 0:0 +#define NVC67E_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC67E_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC67E_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC67E_UPDATE_INTERLOCK_WITH_WIN_IMM 12:12 +#define NVC67E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE (0x00000000) +#define NVC67E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE (0x00000001) +#define NVC67E_SET_SEMAPHORE_ACQUIRE_HI (0x00000204) +#define NVC67E_SET_SEMAPHORE_ACQUIRE_HI_VALUE 31:0 +#define NVC67E_GET_LINE (0x00000208) +#define NVC67E_GET_LINE_LINE 15:0 +#define NVC67E_SET_SEMAPHORE_CONTROL (0x0000020C) +#define NVC67E_SET_SEMAPHORE_CONTROL_OFFSET 7:0 +#define NVC67E_SET_SEMAPHORE_CONTROL_SKIP_ACQ 11:11 +#define NVC67E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_FALSE (0x00000000) +#define NVC67E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_TRUE (0x00000001) +#define NVC67E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVC67E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVC67E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVC67E_SET_SEMAPHORE_CONTROL_ACQ_MODE 13:12 +#define NVC67E_SET_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000) +#define NVC67E_SET_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001) +#define NVC67E_SET_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002) +#define NVC67E_SET_SEMAPHORE_CONTROL_REL_MODE 14:14 +#define NVC67E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE (0x00000000) +#define NVC67E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC67E_SET_SEMAPHORE_ACQUIRE (0x00000210) +#define NVC67E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NVC67E_SET_SEMAPHORE_RELEASE (0x00000214) +#define NVC67E_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NVC67E_SET_CONTEXT_DMA_SEMAPHORE (0x00000218) +#define NVC67E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NVC67E_SET_CONTEXT_DMA_NOTIFIER (0x0000021C) +#define NVC67E_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NVC67E_SET_NOTIFIER_CONTROL (0x00000220) +#define NVC67E_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC67E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC67E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC67E_SET_NOTIFIER_CONTROL_OFFSET 11:4 +#define NVC67E_SET_SIZE (0x00000224) +#define NVC67E_SET_SIZE_WIDTH 15:0 +#define NVC67E_SET_SIZE_HEIGHT 31:16 +#define NVC67E_SET_STORAGE (0x00000228) +#define NVC67E_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NVC67E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NVC67E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NVC67E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC67E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC67E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC67E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC67E_SET_PARAMS (0x0000022C) +#define NVC67E_SET_PARAMS_FORMAT 7:0 +#define NVC67E_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NVC67E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F) +#define NVC67E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NVC67E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC67E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E) +#define NVC67E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC67E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6) +#define NVC67E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NVC67E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9) +#define NVC67E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NVC67E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NVC67E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NVC67E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NVC67E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NVC67E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028) +#define NVC67E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029) +#define NVC67E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035) +#define NVC67E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036) +#define NVC67E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038) +#define NVC67E_SET_PARAMS_FORMAT_Y8___U8___V8_N444 (0x0000003A) +#define NVC67E_SET_PARAMS_FORMAT_Y8___U8___V8_N420 (0x0000003B) +#define NVC67E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055) +#define NVC67E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056) +#define NVC67E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058) +#define NVC67E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075) +#define NVC67E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076) +#define NVC67E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078) +#define NVC67E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18 +#define NVC67E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000) +#define NVC67E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001) +#define NVC67E_SET_PARAMS_SWAP_UV 19:19 +#define NVC67E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000) +#define NVC67E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001) +#define NVC67E_SET_PARAMS_FMT_ROUNDING_MODE 22:22 +#define NVC67E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_TO_NEAREST (0x00000000) +#define NVC67E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_DOWN (0x00000001) +#define NVC67E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004) +#define NVC67E_SET_PLANAR_STORAGE_PITCH 12:0 +#define NVC67E_SET_SEMAPHORE_RELEASE_HI (0x0000023C) +#define NVC67E_SET_SEMAPHORE_RELEASE_HI_VALUE 31:0 +#define NVC67E_SET_CONTEXT_DMA_ISO(b) (0x00000240 + (b)*0x00000004) +#define NVC67E_SET_CONTEXT_DMA_ISO_HANDLE 31:0 +#define NVC67E_SET_OFFSET(b) (0x00000260 + (b)*0x00000004) +#define NVC67E_SET_OFFSET_ORIGIN 31:0 +#define NVC67E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004) +#define NVC67E_SET_POINT_IN_X 15:0 +#define NVC67E_SET_POINT_IN_Y 31:16 +#define NVC67E_SET_SIZE_IN (0x00000298) +#define NVC67E_SET_SIZE_IN_WIDTH 15:0 +#define NVC67E_SET_SIZE_IN_HEIGHT 31:16 +#define NVC67E_SET_SIZE_OUT (0x000002A4) +#define NVC67E_SET_SIZE_OUT_WIDTH 15:0 +#define NVC67E_SET_SIZE_OUT_HEIGHT 31:16 +#define NVC67E_SET_CONTROL_INPUT_SCALER (0x000002A8) +#define NVC67E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVC67E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVC67E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVC67E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVC67E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVC67E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVC67E_SET_INPUT_SCALER_COEFF_VALUE (0x000002AC) +#define NVC67E_SET_INPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVC67E_SET_INPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVC67E_SET_COMPOSITION_CONTROL (0x000002EC) +#define NVC67E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0 +#define NVC67E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000) +#define NVC67E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001) +#define NVC67E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002) +#define NVC67E_SET_COMPOSITION_CONTROL_DEPTH 11:4 +#define NVC67E_SET_COMPOSITION_CONTROL_BYPASS 16:16 +#define NVC67E_SET_COMPOSITION_CONTROL_BYPASS_DISABLE (0x00000000) +#define NVC67E_SET_COMPOSITION_CONTROL_BYPASS_ENABLE (0x00000001) +#define NVC67E_SET_COMPOSITION_CONSTANT_ALPHA (0x000002F0) +#define NVC67E_SET_COMPOSITION_CONSTANT_ALPHA_K1 7:0 +#define NVC67E_SET_COMPOSITION_CONSTANT_ALPHA_K2 15:8 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT (0x000002F4) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC67E_SET_KEY_ALPHA (0x000002F8) +#define NVC67E_SET_KEY_ALPHA_MIN 15:0 +#define NVC67E_SET_KEY_ALPHA_MAX 31:16 +#define NVC67E_SET_KEY_RED_CR (0x000002FC) +#define NVC67E_SET_KEY_RED_CR_MIN 15:0 +#define NVC67E_SET_KEY_RED_CR_MAX 31:16 +#define NVC67E_SET_KEY_GREEN_Y (0x00000300) +#define NVC67E_SET_KEY_GREEN_Y_MIN 15:0 +#define NVC67E_SET_KEY_GREEN_Y_MAX 31:16 +#define NVC67E_SET_KEY_BLUE_CB (0x00000304) +#define NVC67E_SET_KEY_BLUE_CB_MIN 15:0 +#define NVC67E_SET_KEY_BLUE_CB_MAX 31:16 +#define NVC67E_SET_PRESENT_CONTROL (0x00000308) +#define NVC67E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NVC67E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4 +#define NVC67E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NVC67E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NVC67E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8 +#define NVC67E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000) +#define NVC67E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001) +#define NVC67E_SET_PRESENT_CONTROL_STEREO_MODE 13:12 +#define NVC67E_SET_PRESENT_CONTROL_STEREO_MODE_MONO (0x00000000) +#define NVC67E_SET_PRESENT_CONTROL_STEREO_MODE_PAIR_FLIP (0x00000001) +#define NVC67E_SET_PRESENT_CONTROL_STEREO_MODE_AT_ANY_FRAME (0x00000002) +#define NVC67E_SET_ACQ_SEMAPHORE_VALUE_HI (0x0000030C) +#define NVC67E_SET_ACQ_SEMAPHORE_VALUE_HI_VALUE 31:0 +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL (0x00000330) +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL_OFFSET 7:0 +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE 13:12 +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000) +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001) +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002) +#define NVC67E_SET_ACQ_SEMAPHORE_VALUE (0x00000334) +#define NVC67E_SET_ACQ_SEMAPHORE_VALUE_VALUE 31:0 +#define NVC67E_SET_CONTEXT_DMA_ACQ_SEMAPHORE (0x00000338) +#define NVC67E_SET_CONTEXT_DMA_ACQ_SEMAPHORE_HANDLE 31:0 +#define NVC67E_SET_SCAN_DIRECTION (0x0000033C) +#define NVC67E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION 0:0 +#define NVC67E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_LEFT (0x00000000) +#define NVC67E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_RIGHT (0x00000001) +#define NVC67E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION 1:1 +#define NVC67E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_TOP (0x00000000) +#define NVC67E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_BOTTOM (0x00000001) +#define NVC67E_SET_SCAN_DIRECTION_COLUMN_ORDER 2:2 +#define NVC67E_SET_SCAN_DIRECTION_COLUMN_ORDER_FALSE (0x00000000) +#define NVC67E_SET_SCAN_DIRECTION_COLUMN_ORDER_TRUE (0x00000001) +#define NVC67E_SET_TIMESTAMP_ORIGIN_LO (0x00000340) +#define NVC67E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NVC67E_SET_TIMESTAMP_ORIGIN_HI (0x00000344) +#define NVC67E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NVC67E_SET_UPDATE_TIMESTAMP_LO (0x00000348) +#define NVC67E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NVC67E_SET_UPDATE_TIMESTAMP_HI (0x0000034C) +#define NVC67E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NVC67E_SET_INTERLOCK_FLAGS (0x00000370) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 0:0 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+1):((i)+1) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 1:1 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 2:2 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 3:3 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 4:4 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 5:5 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 6:6 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 7:7 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 8:8 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS (0x00000374) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVC67E_SET_EXT_PACKET_CONTROL (0x00000398) +#define NVC67E_SET_EXT_PACKET_CONTROL_ENABLE 0:0 +#define NVC67E_SET_EXT_PACKET_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67E_SET_EXT_PACKET_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67E_SET_EXT_PACKET_CONTROL_LOCATION 4:4 +#define NVC67E_SET_EXT_PACKET_CONTROL_LOCATION_VSYNC (0x00000000) +#define NVC67E_SET_EXT_PACKET_CONTROL_LOCATION_VBLANK (0x00000001) +#define NVC67E_SET_EXT_PACKET_CONTROL_FREQUENCY 8:8 +#define NVC67E_SET_EXT_PACKET_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVC67E_SET_EXT_PACKET_CONTROL_FREQUENCY_ONCE (0x00000001) +#define NVC67E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE 12:12 +#define NVC67E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_DISABLE (0x00000000) +#define NVC67E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_ENABLE (0x00000001) +#define NVC67E_SET_EXT_PACKET_CONTROL_SIZE 27:16 +#define NVC67E_SET_EXT_PACKET_DATA (0x0000039C) +#define NVC67E_SET_EXT_PACKET_DATA_DB0 7:0 +#define NVC67E_SET_EXT_PACKET_DATA_DB1 15:8 +#define NVC67E_SET_EXT_PACKET_DATA_DB2 23:16 +#define NVC67E_SET_EXT_PACKET_DATA_DB3 31:24 +#define NVC67E_SET_FMT_COEFFICIENT_C00 (0x00000400) +#define NVC67E_SET_FMT_COEFFICIENT_C00_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C01 (0x00000404) +#define NVC67E_SET_FMT_COEFFICIENT_C01_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C02 (0x00000408) +#define NVC67E_SET_FMT_COEFFICIENT_C02_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C03 (0x0000040C) +#define NVC67E_SET_FMT_COEFFICIENT_C03_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C10 (0x00000410) +#define NVC67E_SET_FMT_COEFFICIENT_C10_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C11 (0x00000414) +#define NVC67E_SET_FMT_COEFFICIENT_C11_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C12 (0x00000418) +#define NVC67E_SET_FMT_COEFFICIENT_C12_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C13 (0x0000041C) +#define NVC67E_SET_FMT_COEFFICIENT_C13_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C20 (0x00000420) +#define NVC67E_SET_FMT_COEFFICIENT_C20_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C21 (0x00000424) +#define NVC67E_SET_FMT_COEFFICIENT_C21_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C22 (0x00000428) +#define NVC67E_SET_FMT_COEFFICIENT_C22_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C23 (0x0000042C) +#define NVC67E_SET_FMT_COEFFICIENT_C23_VALUE 20:0 +#define NVC67E_SET_ILUT_CONTROL (0x00000440) +#define NVC67E_SET_ILUT_CONTROL_INTERPOLATE 0:0 +#define NVC67E_SET_ILUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC67E_SET_ILUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC67E_SET_ILUT_CONTROL_MIRROR 1:1 +#define NVC67E_SET_ILUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC67E_SET_ILUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC67E_SET_ILUT_CONTROL_MODE 3:2 +#define NVC67E_SET_ILUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVC67E_SET_ILUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVC67E_SET_ILUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVC67E_SET_ILUT_CONTROL_SIZE 18:8 +#define NVC67E_SET_CONTEXT_DMA_ILUT (0x00000444) +#define NVC67E_SET_CONTEXT_DMA_ILUT_HANDLE 31:0 +#define NVC67E_SET_OFFSET_ILUT (0x00000448) +#define NVC67E_SET_OFFSET_ILUT_ORIGIN 31:0 +#define NVC67E_SET_CSC00CONTROL (0x0000045C) +#define NVC67E_SET_CSC00CONTROL_ENABLE 0:0 +#define NVC67E_SET_CSC00CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67E_SET_CSC00CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67E_SET_CSC00COEFFICIENT_C00 (0x00000460) +#define NVC67E_SET_CSC00COEFFICIENT_C00_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C01 (0x00000464) +#define NVC67E_SET_CSC00COEFFICIENT_C01_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C02 (0x00000468) +#define NVC67E_SET_CSC00COEFFICIENT_C02_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C03 (0x0000046C) +#define NVC67E_SET_CSC00COEFFICIENT_C03_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C10 (0x00000470) +#define NVC67E_SET_CSC00COEFFICIENT_C10_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C11 (0x00000474) +#define NVC67E_SET_CSC00COEFFICIENT_C11_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C12 (0x00000478) +#define NVC67E_SET_CSC00COEFFICIENT_C12_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C13 (0x0000047C) +#define NVC67E_SET_CSC00COEFFICIENT_C13_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C20 (0x00000480) +#define NVC67E_SET_CSC00COEFFICIENT_C20_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C21 (0x00000484) +#define NVC67E_SET_CSC00COEFFICIENT_C21_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C22 (0x00000488) +#define NVC67E_SET_CSC00COEFFICIENT_C22_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C23 (0x0000048C) +#define NVC67E_SET_CSC00COEFFICIENT_C23_VALUE 20:0 +#define NVC67E_SET_CSC0LUT_CONTROL (0x000004A0) +#define NVC67E_SET_CSC0LUT_CONTROL_INTERPOLATE 0:0 +#define NVC67E_SET_CSC0LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC67E_SET_CSC0LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC67E_SET_CSC0LUT_CONTROL_MIRROR 1:1 +#define NVC67E_SET_CSC0LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC67E_SET_CSC0LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC67E_SET_CSC0LUT_CONTROL_ENABLE 4:4 +#define NVC67E_SET_CSC0LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67E_SET_CSC0LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67E_SET_CSC0LUT_SEGMENT_SIZE (0x000004A4) +#define NVC67E_SET_CSC0LUT_SEGMENT_SIZE_IDX 5:0 +#define NVC67E_SET_CSC0LUT_SEGMENT_SIZE_VALUE 18:16 +#define NVC67E_SET_CSC0LUT_ENTRY (0x000004A8) +#define NVC67E_SET_CSC0LUT_ENTRY_IDX 10:0 +#define NVC67E_SET_CSC0LUT_ENTRY_VALUE 31:16 +#define NVC67E_SET_CSC01CONTROL (0x000004BC) +#define NVC67E_SET_CSC01CONTROL_ENABLE 0:0 +#define NVC67E_SET_CSC01CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67E_SET_CSC01CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67E_SET_CSC01COEFFICIENT_C00 (0x000004C0) +#define NVC67E_SET_CSC01COEFFICIENT_C00_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C01 (0x000004C4) +#define NVC67E_SET_CSC01COEFFICIENT_C01_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C02 (0x000004C8) +#define NVC67E_SET_CSC01COEFFICIENT_C02_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C03 (0x000004CC) +#define NVC67E_SET_CSC01COEFFICIENT_C03_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C10 (0x000004D0) +#define NVC67E_SET_CSC01COEFFICIENT_C10_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C11 (0x000004D4) +#define NVC67E_SET_CSC01COEFFICIENT_C11_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C12 (0x000004D8) +#define NVC67E_SET_CSC01COEFFICIENT_C12_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C13 (0x000004DC) +#define NVC67E_SET_CSC01COEFFICIENT_C13_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C20 (0x000004E0) +#define NVC67E_SET_CSC01COEFFICIENT_C20_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C21 (0x000004E4) +#define NVC67E_SET_CSC01COEFFICIENT_C21_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C22 (0x000004E8) +#define NVC67E_SET_CSC01COEFFICIENT_C22_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C23 (0x000004EC) +#define NVC67E_SET_CSC01COEFFICIENT_C23_VALUE 20:0 +#define NVC67E_SET_TMO_CONTROL (0x00000500) +#define NVC67E_SET_TMO_CONTROL_INTERPOLATE 0:0 +#define NVC67E_SET_TMO_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC67E_SET_TMO_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC67E_SET_TMO_CONTROL_SAT_MODE 3:2 +#define NVC67E_SET_TMO_CONTROL_SIZE 18:8 +#define NVC67E_SET_TMO_LOW_INTENSITY_ZONE (0x00000508) +#define NVC67E_SET_TMO_LOW_INTENSITY_ZONE_END 29:16 +#define NVC67E_SET_TMO_LOW_INTENSITY_VALUE (0x0000050C) +#define NVC67E_SET_TMO_LOW_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVC67E_SET_TMO_LOW_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVC67E_SET_TMO_LOW_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVC67E_SET_TMO_MEDIUM_INTENSITY_ZONE (0x00000510) +#define NVC67E_SET_TMO_MEDIUM_INTENSITY_ZONE_START 13:0 +#define NVC67E_SET_TMO_MEDIUM_INTENSITY_ZONE_END 29:16 +#define NVC67E_SET_TMO_MEDIUM_INTENSITY_VALUE (0x00000514) +#define NVC67E_SET_TMO_MEDIUM_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVC67E_SET_TMO_MEDIUM_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVC67E_SET_TMO_MEDIUM_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVC67E_SET_TMO_HIGH_INTENSITY_ZONE (0x00000518) +#define NVC67E_SET_TMO_HIGH_INTENSITY_ZONE_START 13:0 +#define NVC67E_SET_TMO_HIGH_INTENSITY_VALUE (0x0000051C) +#define NVC67E_SET_TMO_HIGH_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVC67E_SET_TMO_HIGH_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVC67E_SET_TMO_HIGH_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVC67E_SET_CONTEXT_DMA_TMO_LUT (0x00000528) +#define NVC67E_SET_CONTEXT_DMA_TMO_LUT_HANDLE 31:0 +#define NVC67E_SET_OFFSET_TMO_LUT (0x0000052C) +#define NVC67E_SET_OFFSET_TMO_LUT_ORIGIN 31:0 +#define NVC67E_SET_CSC10CONTROL (0x0000053C) +#define NVC67E_SET_CSC10CONTROL_ENABLE 0:0 +#define NVC67E_SET_CSC10CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67E_SET_CSC10CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67E_SET_CSC10COEFFICIENT_C00 (0x00000540) +#define NVC67E_SET_CSC10COEFFICIENT_C00_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C01 (0x00000544) +#define NVC67E_SET_CSC10COEFFICIENT_C01_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C02 (0x00000548) +#define NVC67E_SET_CSC10COEFFICIENT_C02_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C03 (0x0000054C) +#define NVC67E_SET_CSC10COEFFICIENT_C03_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C10 (0x00000550) +#define NVC67E_SET_CSC10COEFFICIENT_C10_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C11 (0x00000554) +#define NVC67E_SET_CSC10COEFFICIENT_C11_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C12 (0x00000558) +#define NVC67E_SET_CSC10COEFFICIENT_C12_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C13 (0x0000055C) +#define NVC67E_SET_CSC10COEFFICIENT_C13_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C20 (0x00000560) +#define NVC67E_SET_CSC10COEFFICIENT_C20_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C21 (0x00000564) +#define NVC67E_SET_CSC10COEFFICIENT_C21_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C22 (0x00000568) +#define NVC67E_SET_CSC10COEFFICIENT_C22_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C23 (0x0000056C) +#define NVC67E_SET_CSC10COEFFICIENT_C23_VALUE 20:0 +#define NVC67E_SET_CSC1LUT_CONTROL (0x00000580) +#define NVC67E_SET_CSC1LUT_CONTROL_INTERPOLATE 0:0 +#define NVC67E_SET_CSC1LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC67E_SET_CSC1LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC67E_SET_CSC1LUT_CONTROL_MIRROR 1:1 +#define NVC67E_SET_CSC1LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC67E_SET_CSC1LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC67E_SET_CSC1LUT_CONTROL_ENABLE 4:4 +#define NVC67E_SET_CSC1LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67E_SET_CSC1LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67E_SET_CSC1LUT_SEGMENT_SIZE (0x00000584) +#define NVC67E_SET_CSC1LUT_SEGMENT_SIZE_IDX 5:0 +#define NVC67E_SET_CSC1LUT_SEGMENT_SIZE_VALUE 18:16 +#define NVC67E_SET_CSC1LUT_ENTRY (0x00000588) +#define NVC67E_SET_CSC1LUT_ENTRY_IDX 10:0 +#define NVC67E_SET_CSC1LUT_ENTRY_VALUE 31:16 +#define NVC67E_SET_CSC11CONTROL (0x0000059C) +#define NVC67E_SET_CSC11CONTROL_ENABLE 0:0 +#define NVC67E_SET_CSC11CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67E_SET_CSC11CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67E_SET_CSC11COEFFICIENT_C00 (0x000005A0) +#define NVC67E_SET_CSC11COEFFICIENT_C00_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C01 (0x000005A4) +#define NVC67E_SET_CSC11COEFFICIENT_C01_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C02 (0x000005A8) +#define NVC67E_SET_CSC11COEFFICIENT_C02_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C03 (0x000005AC) +#define NVC67E_SET_CSC11COEFFICIENT_C03_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C10 (0x000005B0) +#define NVC67E_SET_CSC11COEFFICIENT_C10_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C11 (0x000005B4) +#define NVC67E_SET_CSC11COEFFICIENT_C11_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C12 (0x000005B8) +#define NVC67E_SET_CSC11COEFFICIENT_C12_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C13 (0x000005BC) +#define NVC67E_SET_CSC11COEFFICIENT_C13_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C20 (0x000005C0) +#define NVC67E_SET_CSC11COEFFICIENT_C20_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C21 (0x000005C4) +#define NVC67E_SET_CSC11COEFFICIENT_C21_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C22 (0x000005C8) +#define NVC67E_SET_CSC11COEFFICIENT_C22_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C23 (0x000005CC) +#define NVC67E_SET_CSC11COEFFICIENT_C23_VALUE 20:0 +#define NVC67E_SET_CLAMP_RANGE (0x000005D0) +#define NVC67E_SET_CLAMP_RANGE_LOW 15:0 +#define NVC67E_SET_CLAMP_RANGE_HIGH 31:16 +#define NVC67E_SW_RESERVED(b) (0x000005D4 + (b)*0x00000004) +#define NVC67E_SW_RESERVED_VALUE 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC67e_h diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc697.h b/userspace/sdks/nv525/nvidia/inc/class/clc697.h new file mode 100644 index 0000000..a8b447e --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc697.h @@ -0,0 +1,4352 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_ampere_a_h_ +#define _cl_ampere_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl ampere_a */ + +#include "nvtypes.h" + +#define AMPERE_A 0xC697 + +#define NVC697_SET_OBJECT 0x0000 +#define NVC697_SET_OBJECT_CLASS_ID 15:0 +#define NVC697_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC697_NO_OPERATION 0x0100 +#define NVC697_NO_OPERATION_V 31:0 + +#define NVC697_SET_NOTIFY_A 0x0104 +#define NVC697_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC697_SET_NOTIFY_B 0x0108 +#define NVC697_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC697_NOTIFY 0x010c +#define NVC697_NOTIFY_TYPE 31:0 +#define NVC697_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC697_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC697_WAIT_FOR_IDLE 0x0110 +#define NVC697_WAIT_FOR_IDLE_V 31:0 + +#define NVC697_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC697_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC697_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC697_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC697_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC697_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC697_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC697_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC697_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC697_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC697_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC697_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC697_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC697_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC697_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC697_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC697_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC697_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC697_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC697_SEND_GO_IDLE 0x013c +#define NVC697_SEND_GO_IDLE_V 31:0 + +#define NVC697_PM_TRIGGER 0x0140 +#define NVC697_PM_TRIGGER_V 31:0 + +#define NVC697_PM_TRIGGER_WFI 0x0144 +#define NVC697_PM_TRIGGER_WFI_V 31:0 + +#define NVC697_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC697_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC697_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC697_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC697_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC697_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC697_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC697_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC697_LINE_LENGTH_IN 0x0180 +#define NVC697_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC697_LINE_COUNT 0x0184 +#define NVC697_LINE_COUNT_VALUE 31:0 + +#define NVC697_OFFSET_OUT_UPPER 0x0188 +#define NVC697_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC697_OFFSET_OUT 0x018c +#define NVC697_OFFSET_OUT_VALUE 31:0 + +#define NVC697_PITCH_OUT 0x0190 +#define NVC697_PITCH_OUT_VALUE 31:0 + +#define NVC697_SET_DST_BLOCK_SIZE 0x0194 +#define NVC697_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC697_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC697_SET_DST_WIDTH 0x0198 +#define NVC697_SET_DST_WIDTH_V 31:0 + +#define NVC697_SET_DST_HEIGHT 0x019c +#define NVC697_SET_DST_HEIGHT_V 31:0 + +#define NVC697_SET_DST_DEPTH 0x01a0 +#define NVC697_SET_DST_DEPTH_V 31:0 + +#define NVC697_SET_DST_LAYER 0x01a4 +#define NVC697_SET_DST_LAYER_V 31:0 + +#define NVC697_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC697_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC697_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC697_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC697_LAUNCH_DMA 0x01b0 +#define NVC697_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC697_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC697_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC697_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC697_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC697_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC697_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC697_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC697_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC697_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC697_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC697_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC697_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC697_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC697_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC697_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC697_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC697_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC697_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC697_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC697_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC697_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC697_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC697_LOAD_INLINE_DATA 0x01b4 +#define NVC697_LOAD_INLINE_DATA_V 31:0 + +#define NVC697_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC697_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC697_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC697_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC697_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC697_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC697_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC697_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC697_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC697_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC697_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC697_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC697_RUN_DS_NOW 0x0200 +#define NVC697_RUN_DS_NOW_V 31:0 + +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC697_SET_GS_MODE 0x0208 +#define NVC697_SET_GS_MODE_TYPE 0:0 +#define NVC697_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVC697_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVC697_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC697_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC697_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC697_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC697_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC697_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_GS_DM_FIFO 0x0214 +#define NVC697_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC697_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC697_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC697_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC697_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC697_INVALIDATE_SHADER_CACHES 0x021c +#define NVC697_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC697_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC697_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC697_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC697_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC697_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC697_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC697_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC697_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC697_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC697_SET_INSTANCE_COUNT 0x0220 +#define NVC697_SET_INSTANCE_COUNT_V 31:0 + +#define NVC697_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVC697_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVC697_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC697_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVC697_SET_MME_VERSION 0x0234 +#define NVC697_SET_MME_VERSION_MAJOR 7:0 + +#define NVC697_SET_INDEX_BUFFER_SIZE_A 0x0238 +#define NVC697_SET_INDEX_BUFFER_SIZE_A_UPPER 7:0 + +#define NVC697_SET_INDEX_BUFFER_SIZE_B 0x023c +#define NVC697_SET_INDEX_BUFFER_SIZE_B_LOWER 31:0 + +#define NVC697_SET_ROOT_TABLE_VISIBILITY(i) (0x0240+(i)*4) +#define NVC697_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP0_ENABLE 1:0 +#define NVC697_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP1_ENABLE 5:4 +#define NVC697_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP2_ENABLE 9:8 +#define NVC697_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP3_ENABLE 13:12 +#define NVC697_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP4_ENABLE 17:16 + +#define NVC697_SET_DRAW_CONTROL_A 0x0260 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY 3:0 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_POINTS 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_LINES 0x00000001 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_QUADS 0x00000007 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_PATCH 0x0000000E +#define NVC697_SET_DRAW_CONTROL_A_PRIMITIVE_ID 4:4 +#define NVC697_SET_DRAW_CONTROL_A_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ID 6:5 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ID_FIRST 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC697_SET_DRAW_CONTROL_A_SPLIT_MODE 8:7 +#define NVC697_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC697_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC697_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE 9:9 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 +#define NVC697_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX 10:10 +#define NVC697_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_FALSE 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_TRUE 0x00000001 +#define NVC697_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX 11:11 +#define NVC697_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_FALSE 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_TRUE 0x00000001 + +#define NVC697_SET_DRAW_CONTROL_B 0x0264 +#define NVC697_SET_DRAW_CONTROL_B_INSTANCE_COUNT 31:0 + +#define NVC697_DRAW_INDEX_BUFFER_BEGIN_END_A 0x0268 +#define NVC697_DRAW_INDEX_BUFFER_BEGIN_END_A_FIRST 31:0 + +#define NVC697_DRAW_INDEX_BUFFER_BEGIN_END_B 0x026c +#define NVC697_DRAW_INDEX_BUFFER_BEGIN_END_B_COUNT 31:0 + +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_A 0x0270 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_A_START 31:0 + +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_B 0x0274 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_B_COUNT 31:0 + +#define NVC697_INVALIDATE_RASTER_CACHE_NO_WFI 0x027c +#define NVC697_INVALIDATE_RASTER_CACHE_NO_WFI_V 0:0 + +#define NVC697_SET_COLOR_RENDER_TO_ZETA_SURFACE 0x02b8 +#define NVC697_SET_COLOR_RENDER_TO_ZETA_SURFACE_V 0:0 +#define NVC697_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_FALSE 0x00000000 +#define NVC697_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_TRUE 0x00000001 + +#define NVC697_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION 0x02bc +#define NVC697_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V 0:0 +#define NVC697_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_FALSE 0x00000000 +#define NVC697_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_TRUE 0x00000001 + +#define NVC697_INCREMENT_SYNC_POINT 0x02c8 +#define NVC697_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC697_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC697_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC697_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC697_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC697_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC697_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC697_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC697_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC697_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC697_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVC697_DECOMPRESS_SURFACE 0x02e0 +#define NVC697_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC697_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC697_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC697_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC697_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC697_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC697_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC697_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC697_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC697_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC697_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC697_SET_ZCULL_SUBREGION 0x02e8 +#define NVC697_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC697_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC697_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC697_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC697_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC697_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC697_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC697_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC697_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC697_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC697_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC697_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC697_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC697_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC697_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC697_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC697_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC697_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC697_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC697_DRAW_ZERO_INDEX 0x0304 +#define NVC697_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC697_SET_L1_CONFIGURATION 0x0308 +#define NVC697_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC697_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC697_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC697_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC697_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC697_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC697_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC697_SET_SPA_VERSION 0x0310 +#define NVC697_SET_SPA_VERSION_MINOR 7:0 +#define NVC697_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC697_SET_TIMESLICE_BATCH_LIMIT 0x0314 +#define NVC697_SET_TIMESLICE_BATCH_LIMIT_BATCH_LIMIT 15:0 + +#define NVC697_SET_SNAP_GRID_LINE 0x0318 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC697_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC697_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC697_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC697_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC697_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC697_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC697_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC697_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC697_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC697_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC697_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC697_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC697_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC697_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC697_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC697_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC697_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC697_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC697_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC697_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC697_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC697_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC697_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC697_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC697_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC697_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC697_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC697_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC697_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC697_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC697_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC697_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC697_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC697_RESERVED_TG07 0x033c +#define NVC697_RESERVED_TG07_V 0:0 + +#define NVC697_RESERVED_TG08 0x0340 +#define NVC697_RESERVED_TG08_V 0:0 + +#define NVC697_RESERVED_TG09 0x0344 +#define NVC697_RESERVED_TG09_V 0:0 + +#define NVC697_RESERVED_TG10 0x0348 +#define NVC697_RESERVED_TG10_V 0:0 + +#define NVC697_RESERVED_TG11 0x034c +#define NVC697_RESERVED_TG11_V 0:0 + +#define NVC697_RESERVED_TG12 0x0350 +#define NVC697_RESERVED_TG12_V 0:0 + +#define NVC697_RESERVED_TG13 0x0354 +#define NVC697_RESERVED_TG13_V 0:0 + +#define NVC697_RESERVED_TG14 0x0358 +#define NVC697_RESERVED_TG14_V 0:0 + +#define NVC697_RESERVED_TG15 0x035c +#define NVC697_RESERVED_TG15_V 0:0 + +#define NVC697_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC697_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC697_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC697_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC697_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC697_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC697_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC697_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC697_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC697_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC697_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC697_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC697_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC697_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC697_SET_RASTER_ENABLE 0x037c +#define NVC697_SET_RASTER_ENABLE_V 0:0 +#define NVC697_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC697_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC697_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC697_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC697_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC697_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC697_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC697_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC697_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC697_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC697_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVC697_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVC697_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVC697_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVC697_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVC697_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVC697_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVC697_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVC697_SET_ROOT_TABLE_SELECTOR 0x0504 +#define NVC697_SET_ROOT_TABLE_SELECTOR_ROOT_TABLE 2:0 +#define NVC697_SET_ROOT_TABLE_SELECTOR_OFFSET 15:8 + +#define NVC697_LOAD_ROOT_TABLE 0x0508 +#define NVC697_LOAD_ROOT_TABLE_V 31:0 + +#define NVC697_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVC697_SET_MME_MEM_ADDRESS_A_UPPER 7:0 + +#define NVC697_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVC697_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVC697_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVC697_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVC697_MME_DMA_READ 0x055c +#define NVC697_MME_DMA_READ_LENGTH 31:0 + +#define NVC697_MME_DMA_READ_FIFOED 0x0560 +#define NVC697_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVC697_MME_DMA_WRITE 0x0564 +#define NVC697_MME_DMA_WRITE_LENGTH 31:0 + +#define NVC697_MME_DMA_REDUCTION 0x0568 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVC697_MME_DMA_SYSMEMBAR 0x056c +#define NVC697_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVC697_MME_DMA_SYNC 0x0570 +#define NVC697_MME_DMA_SYNC_VALUE 31:0 + +#define NVC697_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NVC697_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NVC697_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NVC697_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NVC697_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NVC697_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NVC697_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NVC697_SET_VERTEX_STREAM_SIZE_A(j) (0x0600+(j)*8) +#define NVC697_SET_VERTEX_STREAM_SIZE_A_UPPER 7:0 + +#define NVC697_SET_VERTEX_STREAM_SIZE_B(j) (0x0604+(j)*8) +#define NVC697_SET_VERTEX_STREAM_SIZE_B_LOWER 31:0 + +#define NVC697_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC697_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC697_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC697_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC697_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC697_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC697_SET_RASTER_INPUT 0x0740 +#define NVC697_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC697_SET_STREAM_OUTPUT 0x0744 +#define NVC697_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC697_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC697_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC697_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC697_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC697_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC697_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC697_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC697_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC697_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC697_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC697_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC697_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC697_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC697_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC697_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC697_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC697_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC697_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC697_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC697_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC697_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC697_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC697_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC697_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC697_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVC697_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC697_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC697_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC697_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC697_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC697_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC697_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC697_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC697_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC697_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC697_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC697_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC697_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC697_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC697_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC697_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC697_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC697_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC697_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC697_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC697_SET_ZCULL_STORAGE_B 0x07ec +#define NVC697_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC697_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC697_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC697_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC697_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC697_SET_ZT_READ_ONLY 0x07f8 +#define NVC697_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC697_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC697_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC697_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC697_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC697_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC697_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC697_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC697_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC697_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC697_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC697_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC697_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC697_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC697_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC697_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC697_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC697_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC697_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC697_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC697_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC697_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC697_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC697_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC697_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC697_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC697_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC697_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC697_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC697_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC697_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC697_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC697_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC697_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC697_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC697_SET_COLOR_TARGET_RESERVED_A(j) (0x0824+(j)*64) +#define NVC697_SET_COLOR_TARGET_RESERVED_A_V 0:0 + +#define NVC697_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC697_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC697_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC697_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC697_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC697_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC697_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC697_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC697_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC697_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC697_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC697_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC697_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC697_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC697_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC697_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC697_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC697_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC697_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC697_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC697_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC697_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC697_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC697_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC697_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC697_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC697_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC697_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC697_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC697_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC697_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC697_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC697_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC697_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC697_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC697_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC697_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC697_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC697_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC697_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC697_SET_STATISTICS_COUNTER 0x0d68 +#define NVC697_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC697_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC697_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC697_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC697_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC697_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC697_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC697_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC697_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC697_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC697_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC697_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC697_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC697_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC697_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC697_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC697_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVC697_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC697_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC697_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC697_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC697_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC697_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC697_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC697_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC697_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC697_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC697_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC697_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC697_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC697_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC697_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC697_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC697_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC697_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC697_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC697_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC697_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC697_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC697_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC697_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC697_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC697_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC697_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC697_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC697_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC697_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC697_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC697_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC697_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC697_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC697_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC697_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC697_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC697_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC697_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC697_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC697_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC697_SET_POLY_SMOOTH 0x0db4 +#define NVC697_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC697_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC697_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC697_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC697_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC697_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC697_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC697_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC697_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC697_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_PATCH 0x0dcc +#define NVC697_SET_PATCH_SIZE 7:0 + +#define NVC697_SET_ITERATED_BLEND 0x0dd0 +#define NVC697_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC697_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC697_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC697_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC697_SET_ZCULL_CRITERION 0x0dd8 +#define NVC697_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC697_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC697_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC697_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC697_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC697_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC697_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC697_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC697_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC697_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC697_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC697_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC697_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC697_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC697_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC697_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC697_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC697_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC697_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC697_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC697_SET_SCISSOR_ENABLE_V 0:0 +#define NVC697_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC697_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC697_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC697_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC697_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC697_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC697_SET_VPC_PERF_KNOB 0x0f14 +#define NVC697_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC697_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC697_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC697_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC697_PM_LOCAL_TRIGGER 0x0f18 +#define NVC697_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC697_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC697_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC697_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC697_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC697_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC697_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC697_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC697_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC697_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC697_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC697_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC697_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC697_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC697_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC697_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC697_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC697_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC697_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC697_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC697_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC697_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC697_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC697_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC697_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC697_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC697_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC697_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC697_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC697_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC697_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC697_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC697_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC697_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC697_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC697_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC697_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC697_SET_SAMPLE_MASK 0x0fa4 +#define NVC697_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC697_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC697_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC697_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC697_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC697_SET_CT_MRT_ENABLE 0x0fac +#define NVC697_SET_CT_MRT_ENABLE_V 0:0 +#define NVC697_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC697_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC697_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC697_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC697_SET_TIR 0x0fb4 +#define NVC697_SET_TIR_MODE 1:0 +#define NVC697_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC697_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC697_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC697_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC697_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC697_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC697_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC697_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC697_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC697_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC697_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC697_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC697_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC697_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC697_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC697_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC697_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC697_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC697_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC697_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_TIR_MODULATION 0x0fd4 +#define NVC697_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC697_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC697_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC697_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC697_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC697_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC697_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC697_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC697_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC697_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC697_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC697_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC697_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC697_SET_ZT_A 0x0fe0 +#define NVC697_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_ZT_B 0x0fe4 +#define NVC697_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_ZT_FORMAT 0x0fe8 +#define NVC697_SET_ZT_FORMAT_V 4:0 +#define NVC697_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC697_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC697_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC697_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC697_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC697_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC697_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC697_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC697_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC697_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC697_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC697_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC697_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC697_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC697_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC697_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC697_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC697_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC697_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC697_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC697_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC697_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC697_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC697_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC697_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC697_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC697_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC697_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC697_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC697_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC697_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC697_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC697_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC697_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC697_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC697_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC697_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC697_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC697_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC697_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC697_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC697_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC697_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC697_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC697_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC697_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD02 0x102c +#define NVC697_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC697_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC697_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC697_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC697_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC697_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC697_SET_SPARE_NOOP01 0x1044 +#define NVC697_SET_SPARE_NOOP01_V 31:0 + +#define NVC697_SET_SPARE_NOOP02 0x1048 +#define NVC697_SET_SPARE_NOOP02_V 31:0 + +#define NVC697_SET_SPARE_NOOP03 0x104c +#define NVC697_SET_SPARE_NOOP03_V 31:0 + +#define NVC697_SET_SPARE_NOOP04 0x1050 +#define NVC697_SET_SPARE_NOOP04_V 31:0 + +#define NVC697_SET_SPARE_NOOP05 0x1054 +#define NVC697_SET_SPARE_NOOP05_V 31:0 + +#define NVC697_SET_SPARE_NOOP06 0x1058 +#define NVC697_SET_SPARE_NOOP06_V 31:0 + +#define NVC697_SET_SPARE_NOOP07 0x105c +#define NVC697_SET_SPARE_NOOP07_V 31:0 + +#define NVC697_SET_SPARE_NOOP08 0x1060 +#define NVC697_SET_SPARE_NOOP08_V 31:0 + +#define NVC697_SET_SPARE_NOOP09 0x1064 +#define NVC697_SET_SPARE_NOOP09_V 31:0 + +#define NVC697_SET_SPARE_NOOP10 0x1068 +#define NVC697_SET_SPARE_NOOP10_V 31:0 + +#define NVC697_SET_SPARE_NOOP11 0x106c +#define NVC697_SET_SPARE_NOOP11_V 31:0 + +#define NVC697_SET_SPARE_NOOP12 0x1070 +#define NVC697_SET_SPARE_NOOP12_V 31:0 + +#define NVC697_SET_SPARE_NOOP13 0x1074 +#define NVC697_SET_SPARE_NOOP13_V 31:0 + +#define NVC697_SET_SPARE_NOOP14 0x1078 +#define NVC697_SET_SPARE_NOOP14_V 31:0 + +#define NVC697_SET_SPARE_NOOP15 0x107c +#define NVC697_SET_SPARE_NOOP15_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC697_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC697_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC697_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC697_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC697_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC697_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC697_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC697_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC697_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC697_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC697_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC697_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC697_UNBIND_ALL 0x10f4 +#define NVC697_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC697_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC697_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC697_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC697_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC697_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC697_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC697_NO_OPERATION_DATA_HI 0x110c +#define NVC697_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC697_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC697_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC697_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC697_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC697_PM_TRIGGER_END 0x1114 +#define NVC697_PM_TRIGGER_END_V 31:0 + +#define NVC697_SET_VERTEX_ID_BASE 0x1118 +#define NVC697_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC697_SET_STENCIL_COMPRESSION 0x111c +#define NVC697_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC697_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC697_SET_TIR_CONTROL 0x1130 +#define NVC697_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC697_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC697_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC697_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC697_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC697_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC697_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC697_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC697_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 + +#define NVC697_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC697_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC697_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC697_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC697_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC697_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC697_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC697_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC697_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC697_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC697_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC697_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC697_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC697_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC697_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC697_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC697_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC697_FLUSH_PENDING_WRITES 0x1144 +#define NVC697_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC697_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC697_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC697_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC697_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC697_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC697_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC697_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC697_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC697_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC697_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC697_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC697_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC697_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC697_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC697_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC697_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC697_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC697_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC697_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC697_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC697_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC697_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_SCREEN_STATE_MASK 0x1204 +#define NVC697_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC697_SET_ZT_SPARSE 0x1208 +#define NVC697_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC697_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC697_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC697_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_SET_CT_SELECT 0x121c +#define NVC697_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC697_SET_CT_SELECT_TARGET0 6:4 +#define NVC697_SET_CT_SELECT_TARGET1 9:7 +#define NVC697_SET_CT_SELECT_TARGET2 12:10 +#define NVC697_SET_CT_SELECT_TARGET3 15:13 +#define NVC697_SET_CT_SELECT_TARGET4 18:16 +#define NVC697_SET_CT_SELECT_TARGET5 21:19 +#define NVC697_SET_CT_SELECT_TARGET6 24:22 +#define NVC697_SET_CT_SELECT_TARGET7 27:25 + +#define NVC697_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC697_SET_ZT_SIZE_A 0x1228 +#define NVC697_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC697_SET_ZT_SIZE_B 0x122c +#define NVC697_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC697_SET_ZT_SIZE_C 0x1230 +#define NVC697_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC697_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC697_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC697_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC697_SET_SAMPLER_BINDING 0x1234 +#define NVC697_SET_SAMPLER_BINDING_V 0:0 +#define NVC697_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC697_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC697_DRAW_AUTO 0x123c +#define NVC697_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC697_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC697_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC697_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC697_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC697_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC697_SET_BACK_END_COPY_A 0x1264 +#define NVC697_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC697_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC697_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC697_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC697_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BACK_END_COPY_B 0x1268 +#define NVC697_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC697_SET_BACK_END_COPY_C 0x126c +#define NVC697_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC697_SET_BACK_END_COPY_D 0x1270 +#define NVC697_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC697_SET_BACK_END_COPY_E 0x1274 +#define NVC697_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC697_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC697_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVC697_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC697_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC697_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC697_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC697_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC697_CLEAR_ZCULL_REGION 0x12c8 +#define NVC697_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC697_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC697_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC697_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC697_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC697_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC697_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC697_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC697_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC697_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC697_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC697_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC697_SET_DEPTH_TEST 0x12cc +#define NVC697_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC697_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_FILL_MODE 0x12d0 +#define NVC697_SET_FILL_MODE_V 31:0 +#define NVC697_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC697_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC697_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC697_SET_SHADE_MODE 0x12d4 +#define NVC697_SET_SHADE_MODE_V 31:0 +#define NVC697_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC697_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC697_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC697_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC697_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC697_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC697_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC697_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC697_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC697_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC697_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC697_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_DEPTH_WRITE 0x12e8 +#define NVC697_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC697_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_ALPHA_TEST 0x12ec +#define NVC697_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC697_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC697_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC697_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC697_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC697_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC697_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC697_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC697_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC697_D3D_SET_CULL_MODE 0x1308 +#define NVC697_D3D_SET_CULL_MODE_V 31:0 +#define NVC697_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC697_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC697_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC697_SET_DEPTH_FUNC 0x130c +#define NVC697_SET_DEPTH_FUNC_V 31:0 +#define NVC697_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC697_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC697_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC697_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC697_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC697_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC697_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC697_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC697_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC697_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC697_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC697_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC697_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC697_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC697_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC697_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC697_SET_ALPHA_REF 0x1310 +#define NVC697_SET_ALPHA_REF_V 31:0 + +#define NVC697_SET_ALPHA_FUNC 0x1314 +#define NVC697_SET_ALPHA_FUNC_V 31:0 +#define NVC697_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC697_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC697_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC697_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC697_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC697_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC697_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC697_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC697_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC697_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC697_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC697_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC697_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC697_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC697_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC697_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC697_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC697_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC697_SET_BLEND_CONST_RED 0x131c +#define NVC697_SET_BLEND_CONST_RED_V 31:0 + +#define NVC697_SET_BLEND_CONST_GREEN 0x1320 +#define NVC697_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC697_SET_BLEND_CONST_BLUE 0x1324 +#define NVC697_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC697_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC697_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC697_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC697_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC697_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC697_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC697_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC697_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC697_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC697_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BLEND_COLOR_OP 0x1340 +#define NVC697_SET_BLEND_COLOR_OP_V 31:0 +#define NVC697_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC697_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC697_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC697_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC697_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC697_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC697_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC697_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC697_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC697_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_BLEND_ALPHA_OP 0x134c +#define NVC697_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC697_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC697_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC697_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC697_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC697_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC697_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC697_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC697_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC697_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC697_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC697_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC697_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC697_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC697_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC697_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BLEND(i) (0x1360+(i)*4) +#define NVC697_SET_BLEND_ENABLE 0:0 +#define NVC697_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_STENCIL_TEST 0x1380 +#define NVC697_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC697_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_STENCIL_OP_FAIL 0x1384 +#define NVC697_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC697_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC697_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC697_SET_STENCIL_OP_ZPASS 0x138c +#define NVC697_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC697_SET_STENCIL_FUNC 0x1390 +#define NVC697_SET_STENCIL_FUNC_V 31:0 +#define NVC697_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC697_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC697_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC697_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC697_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC697_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC697_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC697_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC697_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC697_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC697_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC697_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC697_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC697_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC697_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC697_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC697_SET_STENCIL_FUNC_REF 0x1394 +#define NVC697_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC697_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC697_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC697_SET_STENCIL_MASK 0x139c +#define NVC697_SET_STENCIL_MASK_V 7:0 + +#define NVC697_SET_DRAW_AUTO_START 0x13a4 +#define NVC697_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC697_SET_PS_SATURATE 0x13a8 +#define NVC697_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC697_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC697_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC697_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC697_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC697_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC697_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC697_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC697_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC697_SET_WINDOW_ORIGIN 0x13ac +#define NVC697_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC697_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC697_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC697_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC697_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC697_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC697_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC697_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC697_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC697_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC697_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC697_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC697_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC697_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC697_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC697_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC697_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC697_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC697_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC697_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC697_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC697_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC697_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC697_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC697_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC697_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC697_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC697_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC697_STORE_ZCULL 0x1464 +#define NVC697_STORE_ZCULL_V 0:0 + +#define NVC697_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC697_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC697_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC697_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC697_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC697_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC697_LOAD_ZCULL 0x1500 +#define NVC697_LOAD_ZCULL_V 0:0 + +#define NVC697_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC697_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC697_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC697_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC697_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC697_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC697_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC697_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC697_SET_USER_CLIP_ENABLE 0x1510 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC697_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC697_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC697_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_POINT_SIZE 0x1518 +#define NVC697_SET_POINT_SIZE_V 31:0 + +#define NVC697_SET_ZCULL_STATS 0x151c +#define NVC697_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC697_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_POINT_SPRITE 0x1520 +#define NVC697_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC697_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC697_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC697_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC697_CLEAR_REPORT_VALUE 0x1530 +#define NVC697_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC697_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC697_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC697_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC697_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC697_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC697_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVC697_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC697_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC697_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_ZT_SELECT 0x1538 +#define NVC697_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC697_SET_RENDER_ENABLE_A 0x1550 +#define NVC697_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_RENDER_ENABLE_B 0x1554 +#define NVC697_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_RENDER_ENABLE_C 0x1558 +#define NVC697_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC697_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC697_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC697_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC697_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC697_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC697_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC697_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC697_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC697_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC697_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC697_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC697_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC697_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC697_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC697_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC697_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_TEX_HEADER_POOL_C 0x157c +#define NVC697_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC697_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC697_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC697_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC697_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC697_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC697_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC697_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC697_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC697_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC697_SET_SRGB_WRITE 0x15b8 +#define NVC697_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC697_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_DEPTH_BIAS 0x15bc +#define NVC697_SET_DEPTH_BIAS_V 31:0 + +#define NVC697_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC697_SET_RT_LAYER 0x15cc +#define NVC697_SET_RT_LAYER_V 15:0 +#define NVC697_SET_RT_LAYER_CONTROL 16:16 +#define NVC697_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC697_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC697_SET_ANTI_ALIAS 0x15d0 +#define NVC697_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC697_SET_EDGE_FLAG 0x15e4 +#define NVC697_SET_EDGE_FLAG_V 0:0 +#define NVC697_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC697_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC697_DRAW_INLINE_INDEX 0x15e8 +#define NVC697_DRAW_INLINE_INDEX_V 31:0 + +#define NVC697_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC697_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC697_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC697_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC697_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC697_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC697_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC697_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC697_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC697_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC697_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC697_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC697_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC697_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC697_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC697_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC697_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC697_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC697_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC697_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC697_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC697_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC697_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC697_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC697_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC697_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC697_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC697_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC697_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC697_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC697_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC697_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC697_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC697_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC697_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC697_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC697_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC697_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC697_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC697_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC697_END 0x1614 +#define NVC697_END_V 0:0 + +#define NVC697_BEGIN 0x1618 +#define NVC697_BEGIN_OP 15:0 +#define NVC697_BEGIN_OP_POINTS 0x00000000 +#define NVC697_BEGIN_OP_LINES 0x00000001 +#define NVC697_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC697_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC697_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC697_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC697_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC697_BEGIN_OP_QUADS 0x00000007 +#define NVC697_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC697_BEGIN_OP_POLYGON 0x00000009 +#define NVC697_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC697_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC697_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_BEGIN_OP_PATCH 0x0000000E +#define NVC697_BEGIN_PRIMITIVE_ID 24:24 +#define NVC697_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC697_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC697_BEGIN_INSTANCE_ID 27:26 +#define NVC697_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC697_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC697_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC697_BEGIN_SPLIT_MODE 30:29 +#define NVC697_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC697_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC697_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC697_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC697_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVC697_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC697_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_VERTEX_ID_COPY 0x161c +#define NVC697_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC697_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC697_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC697_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC697_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC697_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC697_LOAD_PRIMITIVE_ID 0x1624 +#define NVC697_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC697_SET_SHADER_BASED_CULL 0x162c +#define NVC697_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC697_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC697_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC697_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_CLASS_VERSION 0x1638 +#define NVC697_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC697_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC697_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC697_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC697_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC697_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC697_SET_DA_OUTPUT 0x164c +#define NVC697_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC697_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC697_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC697_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC697_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_POINT_CENTER_MODE 0x165c +#define NVC697_SET_POINT_CENTER_MODE_V 31:0 +#define NVC697_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC697_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC697_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC697_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC697_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC697_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC697_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC697_SET_LINE_STIPPLE 0x166c +#define NVC697_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC697_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC697_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC697_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC697_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC697_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC697_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC697_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC697_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC697_SET_PROVOKING_VERTEX 0x1684 +#define NVC697_SET_PROVOKING_VERTEX_V 0:0 +#define NVC697_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC697_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC697_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC697_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC697_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_POLYGON_STIPPLE 0x168c +#define NVC697_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC697_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_SHADER_CONTROL 0x1690 +#define NVC697_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC697_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC697_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC697_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC697_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC697_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC697_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC697_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC697_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC697_CHECK_CLASS_VERSION 0x16a0 +#define NVC697_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC697_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC697_SET_SPH_VERSION 0x16a4 +#define NVC697_SET_SPH_VERSION_CURRENT 15:0 +#define NVC697_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC697_CHECK_SPH_VERSION 0x16a8 +#define NVC697_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC697_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC697_SET_SCG_GRAPHICS_PRIORITY 0x16bc +#define NVC697_SET_SCG_GRAPHICS_PRIORITY_PRIORITY 5:0 + +#define NVC697_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS(i) (0x16c0+(i)*4) +#define NVC697_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC697_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC697_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC697_SET_AAM_VERSION 0x1790 +#define NVC697_SET_AAM_VERSION_CURRENT 15:0 +#define NVC697_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC697_CHECK_AAM_VERSION 0x1794 +#define NVC697_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC697_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC697_SET_ZT_LAYER 0x179c +#define NVC697_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC697_SET_INDEX_BUFFER_A 0x17c8 +#define NVC697_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC697_SET_INDEX_BUFFER_B 0x17cc +#define NVC697_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC697_SET_INDEX_BUFFER_E 0x17d8 +#define NVC697_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC697_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC697_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC697_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC697_SET_INDEX_BUFFER_F 0x17dc +#define NVC697_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC697_DRAW_INDEX_BUFFER 0x17e0 +#define NVC697_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC697_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC697_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC697_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC697_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC697_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC697_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC697_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC697_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC697_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC697_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC697_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC697_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC697_OGL_SET_CULL 0x1918 +#define NVC697_OGL_SET_CULL_ENABLE 0:0 +#define NVC697_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC697_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC697_OGL_SET_FRONT_FACE 0x191c +#define NVC697_OGL_SET_FRONT_FACE_V 31:0 +#define NVC697_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC697_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC697_OGL_SET_CULL_FACE 0x1920 +#define NVC697_OGL_SET_CULL_FACE_V 31:0 +#define NVC697_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC697_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC697_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC697_SET_VIEWPORT_PIXEL 0x1924 +#define NVC697_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC697_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC697_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC697_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC697_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC697_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC697_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE 17:16 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_USE_FIELD_MIN_Z_ZERO_MAX_Z_ONE 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MIN_Z_MAX_Z 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_ZERO_ONE 0x00000002 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MINUS_INF_PLUS_INF 0x00000003 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC697_SET_USER_CLIP_OP 0x1940 +#define NVC697_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC697_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC697_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC697_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC697_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC697_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC697_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC697_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC697_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC697_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC697_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC697_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC697_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC697_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC697_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC697_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC697_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC697_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC697_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC697_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC697_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC697_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC697_INVALIDATE_ZCULL 0x1958 +#define NVC697_INVALIDATE_ZCULL_V 31:0 +#define NVC697_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC697_SET_ZCULL 0x1968 +#define NVC697_SET_ZCULL_Z_ENABLE 0:0 +#define NVC697_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC697_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_ZCULL_BOUNDS 0x196c +#define NVC697_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC697_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC697_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC697_ZCULL_SYNC 0x1978 +#define NVC697_ZCULL_SYNC_V 31:0 + +#define NVC697_SET_CLIP_ID_TEST 0x197c +#define NVC697_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC697_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC697_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC697_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC697_SET_CLIP_ID 0x1984 +#define NVC697_SET_CLIP_ID_V 31:0 + +#define NVC697_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC697_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC697_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC697_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC697_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC697_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC697_SET_LOGIC_OP 0x19c4 +#define NVC697_SET_LOGIC_OP_ENABLE 0:0 +#define NVC697_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC697_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC697_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC697_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC697_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC697_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC697_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC697_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC697_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC697_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC697_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC697_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC697_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC697_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC697_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC697_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC697_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC697_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC697_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC697_SET_Z_COMPRESSION 0x19cc +#define NVC697_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC697_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC697_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC697_CLEAR_SURFACE 0x19d0 +#define NVC697_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC697_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC697_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC697_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC697_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC697_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC697_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC697_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC697_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC697_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC697_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC697_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC697_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC697_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC697_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC697_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC697_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC697_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC697_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC697_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC697_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC697_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC697_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC697_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC697_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC697_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC697_PIPE_NOP 0x1a2c +#define NVC697_PIPE_NOP_V 31:0 + +#define NVC697_SET_SPARE00 0x1a30 +#define NVC697_SET_SPARE00_V 31:0 + +#define NVC697_SET_SPARE01 0x1a34 +#define NVC697_SET_SPARE01_V 31:0 + +#define NVC697_SET_SPARE02 0x1a38 +#define NVC697_SET_SPARE02_V 31:0 + +#define NVC697_SET_SPARE03 0x1a3c +#define NVC697_SET_SPARE03_V 31:0 + +#define NVC697_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC697_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC697_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC697_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC697_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC697_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC697_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC697_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC697_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC697_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC697_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC697_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC697_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC697_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC697_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC697_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC697_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC697_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC697_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC697_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC697_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC697_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC697_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC697_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC697_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC697_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC697_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC697_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC697_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC697_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC697_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC697_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC697_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC697_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC697_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC697_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC697_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC697_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC697_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC697_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC697_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC697_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC697_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC697_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC697_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC697_SET_PIPELINE_RESERVED_B(j) (0x2004+(j)*64) +#define NVC697_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVC697_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC697_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC697_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC697_SET_PIPELINE_REGISTER_COUNT_V 8:0 + +#define NVC697_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC697_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC697_SET_PIPELINE_PROGRAM_ADDRESS_A(j) (0x2014+(j)*64) +#define NVC697_SET_PIPELINE_PROGRAM_ADDRESS_A_UPPER 7:0 + +#define NVC697_SET_PIPELINE_PROGRAM_ADDRESS_B(j) (0x2018+(j)*64) +#define NVC697_SET_PIPELINE_PROGRAM_ADDRESS_B_LOWER 31:0 + +#define NVC697_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVC697_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVC697_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC697_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC697_SET_FALCON00 0x2300 +#define NVC697_SET_FALCON00_V 31:0 + +#define NVC697_SET_FALCON01 0x2304 +#define NVC697_SET_FALCON01_V 31:0 + +#define NVC697_SET_FALCON02 0x2308 +#define NVC697_SET_FALCON02_V 31:0 + +#define NVC697_SET_FALCON03 0x230c +#define NVC697_SET_FALCON03_V 31:0 + +#define NVC697_SET_FALCON04 0x2310 +#define NVC697_SET_FALCON04_V 31:0 + +#define NVC697_SET_FALCON05 0x2314 +#define NVC697_SET_FALCON05_V 31:0 + +#define NVC697_SET_FALCON06 0x2318 +#define NVC697_SET_FALCON06_V 31:0 + +#define NVC697_SET_FALCON07 0x231c +#define NVC697_SET_FALCON07_V 31:0 + +#define NVC697_SET_FALCON08 0x2320 +#define NVC697_SET_FALCON08_V 31:0 + +#define NVC697_SET_FALCON09 0x2324 +#define NVC697_SET_FALCON09_V 31:0 + +#define NVC697_SET_FALCON10 0x2328 +#define NVC697_SET_FALCON10_V 31:0 + +#define NVC697_SET_FALCON11 0x232c +#define NVC697_SET_FALCON11_V 31:0 + +#define NVC697_SET_FALCON12 0x2330 +#define NVC697_SET_FALCON12_V 31:0 + +#define NVC697_SET_FALCON13 0x2334 +#define NVC697_SET_FALCON13_V 31:0 + +#define NVC697_SET_FALCON14 0x2338 +#define NVC697_SET_FALCON14_V 31:0 + +#define NVC697_SET_FALCON15 0x233c +#define NVC697_SET_FALCON15_V 31:0 + +#define NVC697_SET_FALCON16 0x2340 +#define NVC697_SET_FALCON16_V 31:0 + +#define NVC697_SET_FALCON17 0x2344 +#define NVC697_SET_FALCON17_V 31:0 + +#define NVC697_SET_FALCON18 0x2348 +#define NVC697_SET_FALCON18_V 31:0 + +#define NVC697_SET_FALCON19 0x234c +#define NVC697_SET_FALCON19_V 31:0 + +#define NVC697_SET_FALCON20 0x2350 +#define NVC697_SET_FALCON20_V 31:0 + +#define NVC697_SET_FALCON21 0x2354 +#define NVC697_SET_FALCON21_V 31:0 + +#define NVC697_SET_FALCON22 0x2358 +#define NVC697_SET_FALCON22_V 31:0 + +#define NVC697_SET_FALCON23 0x235c +#define NVC697_SET_FALCON23_V 31:0 + +#define NVC697_SET_FALCON24 0x2360 +#define NVC697_SET_FALCON24_V 31:0 + +#define NVC697_SET_FALCON25 0x2364 +#define NVC697_SET_FALCON25_V 31:0 + +#define NVC697_SET_FALCON26 0x2368 +#define NVC697_SET_FALCON26_V 31:0 + +#define NVC697_SET_FALCON27 0x236c +#define NVC697_SET_FALCON27_V 31:0 + +#define NVC697_SET_FALCON28 0x2370 +#define NVC697_SET_FALCON28_V 31:0 + +#define NVC697_SET_FALCON29 0x2374 +#define NVC697_SET_FALCON29_V 31:0 + +#define NVC697_SET_FALCON30 0x2378 +#define NVC697_SET_FALCON30_V 31:0 + +#define NVC697_SET_FALCON31 0x237c +#define NVC697_SET_FALCON31_V 31:0 + +#define NVC697_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC697_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC697_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC697_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC697_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC697_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC697_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC697_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC697_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC697_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC697_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC697_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC697_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC697_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC697_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC697_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC697_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC697_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC697_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC697_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC697_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC697_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC697_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC697_SET_TRAP_HANDLER_A 0x25f8 +#define NVC697_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC697_SET_TRAP_HANDLER_B 0x25fc +#define NVC697_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC697_SET_COLOR_CLAMP 0x2600 +#define NVC697_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC697_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC697_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC697_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC697_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC697_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC697_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC697_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC697_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC697_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC697_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC697_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC697_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC697_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC697_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC697_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC697_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC697_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC697_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC697_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC697_CALL_MME_MACRO_V 31:0 + +#define NVC697_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC697_CALL_MME_DATA_V 31:0 + +#endif /* _cl_ampere_a_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc6b0.h b/userspace/sdks/nv525/nvidia/inc/class/clc6b0.h new file mode 100644 index 0000000..d36f053 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc6b0.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clc6b0_h_ +#define clc6b0_h_ + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC6B0_VIDEO_DECODER (0x0000C6B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc6b0_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc6b5.h b/userspace/sdks/nv525/nvidia/inc/class/clc6b5.h new file mode 100644 index 0000000..873ca74 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc6b5.h @@ -0,0 +1,282 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clc6b5_h_ +#define _clc6b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define AMPERE_DMA_COPY_A (0x0000C6B5) + +#define NVC6B5_NOP (0x00000100) +#define NVC6B5_NOP_PARAMETER 31:0 +#define NVC6B5_PM_TRIGGER (0x00000140) +#define NVC6B5_PM_TRIGGER_V 31:0 +#define NVC6B5_SET_SEMAPHORE_A (0x00000240) +#define NVC6B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC6B5_SET_SEMAPHORE_B (0x00000244) +#define NVC6B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC6B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC6B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC6B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC6B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC6B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC6B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC6B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC6B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC6B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC6B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC6B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC6B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC6B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC6B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC6B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC6B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC6B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC6B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC6B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVC6B5_SET_SRC_PHYS_MODE_BASIC_KIND 5:2 +#define NVC6B5_SET_SRC_PHYS_MODE_PEER_ID 8:6 +#define NVC6B5_SET_SRC_PHYS_MODE_FLA 9:9 +#define NVC6B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC6B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC6B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC6B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC6B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC6B5_SET_DST_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVC6B5_SET_DST_PHYS_MODE_BASIC_KIND 5:2 +#define NVC6B5_SET_DST_PHYS_MODE_PEER_ID 8:6 +#define NVC6B5_SET_DST_PHYS_MODE_FLA 9:9 +#define NVC6B5_LAUNCH_DMA (0x00000300) +#define NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC6B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC6B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC6B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC6B5_LAUNCH_DMA_FLUSH_TYPE 25:25 +#define NVC6B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000) +#define NVC6B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE (0x00000003) +#define NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC6B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC6B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC6B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC6B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC6B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC6B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC6B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC6B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC6B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC6B5_LAUNCH_DMA_VPRMODE 23:22 +#define NVC6B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVC6B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC6B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC6B5_LAUNCH_DMA_DISABLE_PLC 26:26 +#define NVC6B5_LAUNCH_DMA_DISABLE_PLC_FALSE (0x00000000) +#define NVC6B5_LAUNCH_DMA_DISABLE_PLC_TRUE (0x00000001) +#define NVC6B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 +#define NVC6B5_OFFSET_IN_UPPER (0x00000400) +#define NVC6B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC6B5_OFFSET_IN_LOWER (0x00000404) +#define NVC6B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC6B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC6B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC6B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC6B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC6B5_PITCH_IN (0x00000410) +#define NVC6B5_PITCH_IN_VALUE 31:0 +#define NVC6B5_PITCH_OUT (0x00000414) +#define NVC6B5_PITCH_OUT_VALUE 31:0 +#define NVC6B5_LINE_LENGTH_IN (0x00000418) +#define NVC6B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC6B5_LINE_COUNT (0x0000041C) +#define NVC6B5_LINE_COUNT_VALUE 31:0 +#define NVC6B5_SET_REMAP_CONST_A (0x00000700) +#define NVC6B5_SET_REMAP_CONST_A_V 31:0 +#define NVC6B5_SET_REMAP_CONST_B (0x00000704) +#define NVC6B5_SET_REMAP_CONST_B_V 31:0 +#define NVC6B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC6B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC6B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC6B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC6B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC6B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC6B5_SET_DST_WIDTH (0x00000710) +#define NVC6B5_SET_DST_WIDTH_V 31:0 +#define NVC6B5_SET_DST_HEIGHT (0x00000714) +#define NVC6B5_SET_DST_HEIGHT_V 31:0 +#define NVC6B5_SET_DST_DEPTH (0x00000718) +#define NVC6B5_SET_DST_DEPTH_V 31:0 +#define NVC6B5_SET_DST_LAYER (0x0000071C) +#define NVC6B5_SET_DST_LAYER_V 31:0 +#define NVC6B5_SET_DST_ORIGIN (0x00000720) +#define NVC6B5_SET_DST_ORIGIN_X 15:0 +#define NVC6B5_SET_DST_ORIGIN_Y 31:16 +#define NVC6B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC6B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC6B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC6B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC6B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC6B5_SET_SRC_WIDTH (0x0000072C) +#define NVC6B5_SET_SRC_WIDTH_V 31:0 +#define NVC6B5_SET_SRC_HEIGHT (0x00000730) +#define NVC6B5_SET_SRC_HEIGHT_V 31:0 +#define NVC6B5_SET_SRC_DEPTH (0x00000734) +#define NVC6B5_SET_SRC_DEPTH_V 31:0 +#define NVC6B5_SET_SRC_LAYER (0x00000738) +#define NVC6B5_SET_SRC_LAYER_V 31:0 +#define NVC6B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC6B5_SET_SRC_ORIGIN_X 15:0 +#define NVC6B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC6B5_SRC_ORIGIN_X (0x00000744) +#define NVC6B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC6B5_SRC_ORIGIN_Y (0x00000748) +#define NVC6B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC6B5_DST_ORIGIN_X (0x0000074C) +#define NVC6B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC6B5_DST_ORIGIN_Y (0x00000750) +#define NVC6B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC6B5_PM_TRIGGER_END (0x00001114) +#define NVC6B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc6b5_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc6b5sw.h b/userspace/sdks/nv525/nvidia/inc/class/clc6b5sw.h new file mode 100644 index 0000000..7a928aa --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc6b5sw.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc6b5sw.finn +// + + + +// +// Using VERSION_0 will cause the API to interpret +// engineType as a CE engine instance. This allows +// for backward compatibility with 85B5sw and 90B5sw. +// +#define NVC6B5_ALLOCATION_PARAMETERS_VERSION_0 0 + +// +// Using VERSION_1 will cause the API to interpret +// engineType as an NV2080_ENGINE_TYPE ordinal. +// +#define NVC6B5_ALLOCATION_PARAMETERS_VERSION_1 1 + +#define NVC6B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc6b5U) + +typedef struct NVC6B5_ALLOCATION_PARAMETERS { + NvU32 version; + NvU32 engineType; +} NVC6B5_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc6c0.h b/userspace/sdks/nv525/nvidia/inc/class/clc6c0.h new file mode 100644 index 0000000..48aa385 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc6c0.h @@ -0,0 +1,697 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_ampere_compute_a_h_ +#define _cl_ampere_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl ampere_compute_a */ + +#include "nvtypes.h" + +#define AMPERE_COMPUTE_A 0xC6C0 + +#define NVC6C0_SET_OBJECT 0x0000 +#define NVC6C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC6C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC6C0_NO_OPERATION 0x0100 +#define NVC6C0_NO_OPERATION_V 31:0 + +#define NVC6C0_SET_NOTIFY_A 0x0104 +#define NVC6C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC6C0_SET_NOTIFY_B 0x0108 +#define NVC6C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC6C0_NOTIFY 0x010c +#define NVC6C0_NOTIFY_TYPE 31:0 +#define NVC6C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC6C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC6C0_WAIT_FOR_IDLE 0x0110 +#define NVC6C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC6C0_SEND_GO_IDLE 0x013c +#define NVC6C0_SEND_GO_IDLE_V 31:0 + +#define NVC6C0_PM_TRIGGER 0x0140 +#define NVC6C0_PM_TRIGGER_V 31:0 + +#define NVC6C0_PM_TRIGGER_WFI 0x0144 +#define NVC6C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC6C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC6C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC6C0_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC6C0_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC6C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC6C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC6C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC6C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC6C0_LINE_LENGTH_IN 0x0180 +#define NVC6C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC6C0_LINE_COUNT 0x0184 +#define NVC6C0_LINE_COUNT_VALUE 31:0 + +#define NVC6C0_OFFSET_OUT_UPPER 0x0188 +#define NVC6C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC6C0_OFFSET_OUT 0x018c +#define NVC6C0_OFFSET_OUT_VALUE 31:0 + +#define NVC6C0_PITCH_OUT 0x0190 +#define NVC6C0_PITCH_OUT_VALUE 31:0 + +#define NVC6C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC6C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC6C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC6C0_SET_DST_WIDTH 0x0198 +#define NVC6C0_SET_DST_WIDTH_V 31:0 + +#define NVC6C0_SET_DST_HEIGHT 0x019c +#define NVC6C0_SET_DST_HEIGHT_V 31:0 + +#define NVC6C0_SET_DST_DEPTH 0x01a0 +#define NVC6C0_SET_DST_DEPTH_V 31:0 + +#define NVC6C0_SET_DST_LAYER 0x01a4 +#define NVC6C0_SET_DST_LAYER_V 31:0 + +#define NVC6C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC6C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC6C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC6C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC6C0_LAUNCH_DMA 0x01b0 +#define NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC6C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC6C0_LOAD_INLINE_DATA 0x01b4 +#define NVC6C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC6C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC6C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC6C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC6C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC6C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC6C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC6C0_SET_SM_SCG_CONTROL 0x01e8 +#define NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS 0:0 +#define NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE 0x00000000 +#define NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE 0x00000001 + +#define NVC6C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC6C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC6C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC6C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC6C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC6C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC6C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC6C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC6C0_PERFMON_TRANSFER 0x0210 +#define NVC6C0_PERFMON_TRANSFER_V 31:0 + +#define NVC6C0_SET_QMD_VIRTUALIZATION_BASE_A 0x0214 +#define NVC6C0_SET_QMD_VIRTUALIZATION_BASE_A_ADDRESS_UPPER 7:0 + +#define NVC6C0_SET_QMD_VIRTUALIZATION_BASE_B 0x0218 +#define NVC6C0_SET_QMD_VIRTUALIZATION_BASE_B_ADDRESS_LOWER 31:0 + +#define NVC6C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC6C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC6C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC6C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC6C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC6C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC6C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC6C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC6C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC6C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC6C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC6C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC6C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC6C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC6C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC6C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC6C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC6C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC6C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC6C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC6C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC6C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC6C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC6C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC6C0_SET_SCG_CONTROL 0x0270 +#define NVC6C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 +#define NVC6C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 +#define NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 +#define NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 +#define NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 + +#define NVC6C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC6C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC6C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC6C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC6C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC6C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC6C0_SET_QMD_VERSION 0x0288 +#define NVC6C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC6C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC6C0_CHECK_QMD_VERSION 0x0290 +#define NVC6C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC6C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC6C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC6C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL 0x029c +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_CONSTANT_BUFFER_MASK 7:0 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE 8:8 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE 12:12 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE 16:16 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE 20:20 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE 24:24 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_TRUE 0x00000001 + +#define NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC6C0_SCG_HYSTERESIS_CONTROL 0x02a8 +#define NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 +#define NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 +#define NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 +#define NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 + +#define NVC6C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC6C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC6C0_SEND_PCAS_A 0x02b4 +#define NVC6C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC6C0_SEND_PCAS_B 0x02b8 +#define NVC6C0_SEND_PCAS_B_FROM 23:0 +#define NVC6C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC6C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC6C0_SEND_SIGNALING_PCAS2_B 0x02c0 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION 3:0 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_NOP 0x00000000 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE 0x00000001 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_SCHEDULE 0x00000002 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_COPY_SCHEDULE 0x00000003 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_PUT 0x00000006 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_DECREMENT_DEPENDENCE 0x00000007 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH 0x00000008 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH_SCHEDULE 0x00000009 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_SCHEDULE 0x0000000A +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_FORCE_REQUIRE_SCHEDULING 0x0000000B + +#define NVC6C0_SET_SKED_CACHE_CONTROL 0x02cc +#define NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID 0:0 +#define NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE 0x00000000 +#define NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE 0x00000001 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC6C0_SET_SPA_VERSION 0x0310 +#define NVC6C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC6C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC6C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC6C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC6C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC6C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC6C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC6C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC6C0_SET_FALCON00 0x0500 +#define NVC6C0_SET_FALCON00_V 31:0 + +#define NVC6C0_SET_FALCON01 0x0504 +#define NVC6C0_SET_FALCON01_V 31:0 + +#define NVC6C0_SET_FALCON02 0x0508 +#define NVC6C0_SET_FALCON02_V 31:0 + +#define NVC6C0_SET_FALCON03 0x050c +#define NVC6C0_SET_FALCON03_V 31:0 + +#define NVC6C0_SET_FALCON04 0x0510 +#define NVC6C0_SET_FALCON04_V 31:0 + +#define NVC6C0_SET_FALCON05 0x0514 +#define NVC6C0_SET_FALCON05_V 31:0 + +#define NVC6C0_SET_FALCON06 0x0518 +#define NVC6C0_SET_FALCON06_V 31:0 + +#define NVC6C0_SET_FALCON07 0x051c +#define NVC6C0_SET_FALCON07_V 31:0 + +#define NVC6C0_SET_FALCON08 0x0520 +#define NVC6C0_SET_FALCON08_V 31:0 + +#define NVC6C0_SET_FALCON09 0x0524 +#define NVC6C0_SET_FALCON09_V 31:0 + +#define NVC6C0_SET_FALCON10 0x0528 +#define NVC6C0_SET_FALCON10_V 31:0 + +#define NVC6C0_SET_FALCON11 0x052c +#define NVC6C0_SET_FALCON11_V 31:0 + +#define NVC6C0_SET_FALCON12 0x0530 +#define NVC6C0_SET_FALCON12_V 31:0 + +#define NVC6C0_SET_FALCON13 0x0534 +#define NVC6C0_SET_FALCON13_V 31:0 + +#define NVC6C0_SET_FALCON14 0x0538 +#define NVC6C0_SET_FALCON14_V 31:0 + +#define NVC6C0_SET_FALCON15 0x053c +#define NVC6C0_SET_FALCON15_V 31:0 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC6C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC6C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS(i) (0x0da0+(i)*4) +#define NVC6C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC6C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC6C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC6C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC6C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC6C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC6C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC6C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC6C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC6C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC6C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC6C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC6C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC6C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC6C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC6C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC6C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC6C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC6C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC6C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC6C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC6C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC6C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC6C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC6C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC6C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC6C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC6C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC6C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC6C0_PIPE_NOP 0x1a2c +#define NVC6C0_PIPE_NOP_V 31:0 + +#define NVC6C0_SET_SPARE00 0x1a30 +#define NVC6C0_SET_SPARE00_V 31:0 + +#define NVC6C0_SET_SPARE01 0x1a34 +#define NVC6C0_SET_SPARE01_V 31:0 + +#define NVC6C0_SET_SPARE02 0x1a38 +#define NVC6C0_SET_SPARE02_V 31:0 + +#define NVC6C0_SET_SPARE03 0x1a3c +#define NVC6C0_SET_SPARE03_V 31:0 + +#define NVC6C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC6C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC6C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC6C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC6C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC6C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC6C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC6C0_SET_TRAP_HANDLER_A 0x25f8 +#define NVC6C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC6C0_SET_TRAP_HANDLER_B 0x25fc +#define NVC6C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC6C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC6C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC6C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC6C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC6C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC6C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC6C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC6C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC6C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC6C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC6C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC6C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_ampere_compute_a_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc6fa.h b/userspace/sdks/nv525/nvidia/inc/class/clc6fa.h new file mode 100644 index 0000000..92d06ea --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc6fa.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc6fa_h_ +#define _clc6fa_h_ + +#define NVC6FA_VIDEO_OFA (0x0000C6FA) + +#endif // _clc6fa_h_ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc770.h b/userspace/sdks/nv525/nvidia/inc/class/clc770.h new file mode 100644 index 0000000..4f66916 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc770.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc770.finn +// + +#define NVC770_DISPLAY (0xc770U) /* finn: Evaluated from "NVC770_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + + + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc771.h b/userspace/sdks/nv525/nvidia/inc/class/clc771.h new file mode 100644 index 0000000..b2b1976 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc771.h @@ -0,0 +1,155 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef _clc771_h_ +#define _clc771_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC771_DISP_SF_USER (0x000C771) + +typedef volatile struct _clc771_tag0 { + NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x000D0FFF:0x000D0000 */ +} _NvC771DispSfUser, NvC771DispSfUserMap; + +#define NVC771_SF_SHARED_GENERIC_CTRL(i,j) (0x000E0200-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_CTRL_ENABLE 0:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_SINGLE 4:4 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_CTRL_SINGLE_NO 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_SINGLE_YES 0x00000001 /* RW--V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_CHECKSUM_HW 16:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_CTRL_CHECKSUM_HW_NO 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_CHECKSUM_HW_YES 0x00000001 /* RW--V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_LOC 9:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_CTRL_LOC_VBLANK 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_LOC_VSYNC 0x00000001 /* RW--V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_LOC_LOADV 0x00000002 /* RW--V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER(i,j) (0x000E0204-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ + +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB3 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB3_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0(i,j) (0x000E0208-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB0 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB0_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB1 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB1_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB2 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB2_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB3 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB3_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1(i,j) (0x000E020C-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB4 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB4_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB5 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB5_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB6 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB6_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB7 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB7_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2(i,j) (0x000E0210-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB8 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB8_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB9 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB9_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB10 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB10_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB11 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB11_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3(i,j) (0x000E0214-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB12 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB12_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB13 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB13_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB14 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB14_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB15 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB15_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4(i,j) (0x000E0218-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB16 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB16_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB17 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB17_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB18 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB18_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB19 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB19_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5(i,j) (0x000E021C-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB20 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB20_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB21 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB21_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB22 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB22_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB23 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB23_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6(i,j) (0x000E0220-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB24 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB24_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB25 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB25_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB26 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB26_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB27 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB27_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7(i,j) (0x000E0224-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB28 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB28_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB29 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB29_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB30 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB30_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB31 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB31_INIT 0x00000000 /* RWI-V */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc773.h b/userspace/sdks/nv525/nvidia/inc/class/clc773.h new file mode 100644 index 0000000..db5505a --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc773.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc773_h_ +#define _clc773_h_ + +#define NVC773_DISP_CAPABILITIES 0xC773 + +#endif diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc77d.h b/userspace/sdks/nv525/nvidia/inc/class/clc77d.h new file mode 100644 index 0000000..f46235a --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc77d.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc77d_h_ +#define _clc77d_h_ + +#define NVC77D_CORE_CHANNEL_DMA (0x0000C77D) + +#define NVC77D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000400) +#define NVC77D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NVC77D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 + +#endif diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc77f.h b/userspace/sdks/nv525/nvidia/inc/class/clc77f.h new file mode 100644 index 0000000..3651a58 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc77f.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clC77F_h_ +#define _clC77F_h_ + +// +// This class provides functional support of Display ANYChannel, Display Contextdmas bound to +// ANYChannel can be used on any other display window channels. +// +#define NVC77F_ANY_CHANNEL_DMA (0x0000C77F) + +#endif // _clC77F_h_ + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc797.h b/userspace/sdks/nv525/nvidia/inc/class/clc797.h new file mode 100644 index 0000000..dc4b600 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc797.h @@ -0,0 +1,4481 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_ampere_b_h_ +#define _cl_ampere_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl ampere_b */ + +#include "nvtypes.h" + +#define AMPERE_B 0xC797 + +#define NVC797_SET_OBJECT 0x0000 +#define NVC797_SET_OBJECT_CLASS_ID 15:0 +#define NVC797_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC797_NO_OPERATION 0x0100 +#define NVC797_NO_OPERATION_V 31:0 + +#define NVC797_SET_NOTIFY_A 0x0104 +#define NVC797_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC797_SET_NOTIFY_B 0x0108 +#define NVC797_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC797_NOTIFY 0x010c +#define NVC797_NOTIFY_TYPE 31:0 +#define NVC797_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC797_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC797_WAIT_FOR_IDLE 0x0110 +#define NVC797_WAIT_FOR_IDLE_V 31:0 + +#define NVC797_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC797_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC797_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC797_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC797_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC797_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC797_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC797_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC797_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC797_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC797_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC797_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC797_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC797_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC797_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC797_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC797_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC797_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC797_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC797_SEND_GO_IDLE 0x013c +#define NVC797_SEND_GO_IDLE_V 31:0 + +#define NVC797_PM_TRIGGER 0x0140 +#define NVC797_PM_TRIGGER_V 31:0 + +#define NVC797_PM_TRIGGER_WFI 0x0144 +#define NVC797_PM_TRIGGER_WFI_V 31:0 + +#define NVC797_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC797_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC797_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC797_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC797_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC797_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC797_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC797_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER 0x0158 +#define NVC797_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER_PAYLOAD_LOWER 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER 0x015c +#define NVC797_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD_UPPER 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_ADDRESS_LOWER 0x0160 +#define NVC797_SET_REPORT_SEMAPHORE_ADDRESS_LOWER_LOWER 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_ADDRESS_UPPER 0x0164 +#define NVC797_SET_REPORT_SEMAPHORE_ADDRESS_UPPER_UPPER 7:0 + +#define NVC797_REPORT_SEMAPHORE_EXECUTE 0x0168 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_OPERATION 1:0 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_OPERATION_RELEASE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_OPERATION_ACQUIRE 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_OPERATION_REPORT_ONLY 0x00000002 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_OPERATION_TRAP 0x00000003 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION 5:2 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC797_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE 6:6 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT 11:7 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_NONE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_SCG_CLOCKS 0x00000008 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS0 0x0000000A +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS1 0x0000000C +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS2 0x0000000E +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS3 0x00000010 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_TIMESTAMP 0x00000014 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE 14:13 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_SUB_REPORT 17:15 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE 19:19 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE 18:18 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE 20:20 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP 23:21 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_INC 0x00000003 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_AND 0x00000005 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_OR 0x00000006 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT 25:24 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64 27:27 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_FALSE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_TRUE 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE 29:28 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_NONE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 + +#define NVC797_LINE_LENGTH_IN 0x0180 +#define NVC797_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC797_LINE_COUNT 0x0184 +#define NVC797_LINE_COUNT_VALUE 31:0 + +#define NVC797_OFFSET_OUT_UPPER 0x0188 +#define NVC797_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC797_OFFSET_OUT 0x018c +#define NVC797_OFFSET_OUT_VALUE 31:0 + +#define NVC797_PITCH_OUT 0x0190 +#define NVC797_PITCH_OUT_VALUE 31:0 + +#define NVC797_SET_DST_BLOCK_SIZE 0x0194 +#define NVC797_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC797_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC797_SET_DST_WIDTH 0x0198 +#define NVC797_SET_DST_WIDTH_V 31:0 + +#define NVC797_SET_DST_HEIGHT 0x019c +#define NVC797_SET_DST_HEIGHT_V 31:0 + +#define NVC797_SET_DST_DEPTH 0x01a0 +#define NVC797_SET_DST_DEPTH_V 31:0 + +#define NVC797_SET_DST_LAYER 0x01a4 +#define NVC797_SET_DST_LAYER_V 31:0 + +#define NVC797_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC797_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC797_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC797_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC797_LAUNCH_DMA 0x01b0 +#define NVC797_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC797_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC797_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC797_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC797_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC797_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC797_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC797_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC797_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC797_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC797_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC797_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC797_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC797_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC797_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC797_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC797_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC797_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC797_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC797_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC797_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC797_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC797_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC797_LOAD_INLINE_DATA 0x01b4 +#define NVC797_LOAD_INLINE_DATA_V 31:0 + +#define NVC797_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC797_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC797_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC797_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC797_SET_MME_SWITCH_STATE 0x01ec +#define NVC797_SET_MME_SWITCH_STATE_VALID 0:0 +#define NVC797_SET_MME_SWITCH_STATE_VALID_FALSE 0x00000000 +#define NVC797_SET_MME_SWITCH_STATE_VALID_TRUE 0x00000001 +#define NVC797_SET_MME_SWITCH_STATE_SAVE_MACRO 11:4 +#define NVC797_SET_MME_SWITCH_STATE_RESTORE_MACRO 19:12 + +#define NVC797_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC797_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC797_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC797_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC797_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC797_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC797_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC797_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC797_RUN_DS_NOW 0x0200 +#define NVC797_RUN_DS_NOW_V 31:0 + +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC797_SET_GS_MODE 0x0208 +#define NVC797_SET_GS_MODE_TYPE 0:0 +#define NVC797_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVC797_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVC797_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC797_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC797_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC797_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC797_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC797_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_GS_DM_FIFO 0x0214 +#define NVC797_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC797_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC797_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC797_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC797_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC797_INVALIDATE_SHADER_CACHES 0x021c +#define NVC797_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC797_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC797_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC797_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC797_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC797_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC797_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC797_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC797_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC797_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC797_SET_INSTANCE_COUNT 0x0220 +#define NVC797_SET_INSTANCE_COUNT_V 31:0 + +#define NVC797_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVC797_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVC797_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC797_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVC797_SET_MME_VERSION 0x0234 +#define NVC797_SET_MME_VERSION_MAJOR 7:0 + +#define NVC797_SET_INDEX_BUFFER_SIZE_A 0x0238 +#define NVC797_SET_INDEX_BUFFER_SIZE_A_UPPER 7:0 + +#define NVC797_SET_INDEX_BUFFER_SIZE_B 0x023c +#define NVC797_SET_INDEX_BUFFER_SIZE_B_LOWER 31:0 + +#define NVC797_SET_ROOT_TABLE_VISIBILITY(i) (0x0240+(i)*4) +#define NVC797_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP0_ENABLE 1:0 +#define NVC797_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP1_ENABLE 5:4 +#define NVC797_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP2_ENABLE 9:8 +#define NVC797_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP3_ENABLE 13:12 +#define NVC797_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP4_ENABLE 17:16 + +#define NVC797_SET_DRAW_CONTROL_A 0x0260 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY 3:0 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_POINTS 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_LINES 0x00000001 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_QUADS 0x00000007 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_PATCH 0x0000000E +#define NVC797_SET_DRAW_CONTROL_A_PRIMITIVE_ID 4:4 +#define NVC797_SET_DRAW_CONTROL_A_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ID 6:5 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ID_FIRST 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC797_SET_DRAW_CONTROL_A_SPLIT_MODE 8:7 +#define NVC797_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC797_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC797_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE 9:9 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 +#define NVC797_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX 10:10 +#define NVC797_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_FALSE 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_TRUE 0x00000001 +#define NVC797_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX 11:11 +#define NVC797_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_FALSE 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_TRUE 0x00000001 + +#define NVC797_SET_DRAW_CONTROL_B 0x0264 +#define NVC797_SET_DRAW_CONTROL_B_INSTANCE_COUNT 31:0 + +#define NVC797_DRAW_INDEX_BUFFER_BEGIN_END_A 0x0268 +#define NVC797_DRAW_INDEX_BUFFER_BEGIN_END_A_FIRST 31:0 + +#define NVC797_DRAW_INDEX_BUFFER_BEGIN_END_B 0x026c +#define NVC797_DRAW_INDEX_BUFFER_BEGIN_END_B_COUNT 31:0 + +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_A 0x0270 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_A_START 31:0 + +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_B 0x0274 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_B_COUNT 31:0 + +#define NVC797_INVALIDATE_RASTER_CACHE_NO_WFI 0x027c +#define NVC797_INVALIDATE_RASTER_CACHE_NO_WFI_V 0:0 + +#define NVC797_SET_COLOR_RENDER_TO_ZETA_SURFACE 0x02b8 +#define NVC797_SET_COLOR_RENDER_TO_ZETA_SURFACE_V 0:0 +#define NVC797_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_FALSE 0x00000000 +#define NVC797_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_TRUE 0x00000001 + +#define NVC797_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION 0x02bc +#define NVC797_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V 0:0 +#define NVC797_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_FALSE 0x00000000 +#define NVC797_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_TRUE 0x00000001 + +#define NVC797_INCREMENT_SYNC_POINT 0x02c8 +#define NVC797_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC797_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC797_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC797_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC797_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC797_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC797_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC797_SET_ROOT_TABLE_PREFETCH 0x02d0 +#define NVC797_SET_ROOT_TABLE_PREFETCH_STAGE_ENABLES 5:0 + +#define NVC797_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC797_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC797_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC797_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVC797_DECOMPRESS_SURFACE 0x02e0 +#define NVC797_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC797_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC797_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC797_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC797_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC797_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC797_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC797_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC797_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC797_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC797_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC797_SET_ZCULL_SUBREGION 0x02e8 +#define NVC797_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC797_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC797_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC797_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC797_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC797_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC797_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC797_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC797_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC797_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC797_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC797_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC797_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC797_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC797_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC797_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC797_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC797_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC797_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC797_DRAW_ZERO_INDEX 0x0304 +#define NVC797_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC797_SET_L1_CONFIGURATION 0x0308 +#define NVC797_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC797_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC797_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC797_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC797_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC797_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC797_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC797_SET_SPA_VERSION 0x0310 +#define NVC797_SET_SPA_VERSION_MINOR 7:0 +#define NVC797_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC797_SET_TIMESLICE_BATCH_LIMIT 0x0314 +#define NVC797_SET_TIMESLICE_BATCH_LIMIT_BATCH_LIMIT 15:0 + +#define NVC797_SET_SNAP_GRID_LINE 0x0318 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC797_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC797_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC797_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC797_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC797_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC797_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC797_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC797_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC797_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC797_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC797_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC797_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC797_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC797_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC797_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC797_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC797_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC797_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC797_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC797_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC797_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC797_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC797_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC797_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC797_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC797_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC797_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC797_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC797_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC797_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC797_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC797_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC797_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC797_RESERVED_TG07 0x033c +#define NVC797_RESERVED_TG07_V 0:0 + +#define NVC797_RESERVED_TG08 0x0340 +#define NVC797_RESERVED_TG08_V 0:0 + +#define NVC797_RESERVED_TG09 0x0344 +#define NVC797_RESERVED_TG09_V 0:0 + +#define NVC797_RESERVED_TG10 0x0348 +#define NVC797_RESERVED_TG10_V 0:0 + +#define NVC797_RESERVED_TG11 0x034c +#define NVC797_RESERVED_TG11_V 0:0 + +#define NVC797_RESERVED_TG12 0x0350 +#define NVC797_RESERVED_TG12_V 0:0 + +#define NVC797_RESERVED_TG13 0x0354 +#define NVC797_RESERVED_TG13_V 0:0 + +#define NVC797_RESERVED_TG14 0x0358 +#define NVC797_RESERVED_TG14_V 0:0 + +#define NVC797_RESERVED_TG15 0x035c +#define NVC797_RESERVED_TG15_V 0:0 + +#define NVC797_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC797_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC797_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC797_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC797_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC797_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC797_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC797_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC797_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC797_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC797_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC797_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC797_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC797_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC797_SET_RASTER_ENABLE 0x037c +#define NVC797_SET_RASTER_ENABLE_V 0:0 +#define NVC797_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC797_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC797_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC797_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC797_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC797_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC797_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC797_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC797_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC797_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC797_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVC797_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVC797_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVC797_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVC797_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVC797_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVC797_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVC797_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVC797_SET_Z_ROP_SLICE_MAP 0x0500 +#define NVC797_SET_Z_ROP_SLICE_MAP_VIRTUAL_ADDRESS_MASK 31:0 + +#define NVC797_SET_ROOT_TABLE_SELECTOR 0x0504 +#define NVC797_SET_ROOT_TABLE_SELECTOR_ROOT_TABLE 2:0 +#define NVC797_SET_ROOT_TABLE_SELECTOR_OFFSET 15:8 + +#define NVC797_LOAD_ROOT_TABLE 0x0508 +#define NVC797_LOAD_ROOT_TABLE_V 31:0 + +#define NVC797_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVC797_SET_MME_MEM_ADDRESS_A_UPPER 16:0 + +#define NVC797_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVC797_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVC797_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVC797_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVC797_MME_DMA_READ 0x055c +#define NVC797_MME_DMA_READ_LENGTH 31:0 + +#define NVC797_MME_DMA_READ_FIFOED 0x0560 +#define NVC797_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVC797_MME_DMA_WRITE 0x0564 +#define NVC797_MME_DMA_WRITE_LENGTH 31:0 + +#define NVC797_MME_DMA_REDUCTION 0x0568 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVC797_MME_DMA_SYSMEMBAR 0x056c +#define NVC797_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVC797_MME_DMA_SYNC 0x0570 +#define NVC797_MME_DMA_SYNC_VALUE 31:0 + +#define NVC797_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NVC797_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NVC797_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NVC797_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NVC797_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NVC797_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NVC797_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NVC797_SET_VERTEX_STREAM_SIZE_A(j) (0x0600+(j)*8) +#define NVC797_SET_VERTEX_STREAM_SIZE_A_UPPER 7:0 + +#define NVC797_SET_VERTEX_STREAM_SIZE_B(j) (0x0604+(j)*8) +#define NVC797_SET_VERTEX_STREAM_SIZE_B_LOWER 31:0 + +#define NVC797_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC797_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC797_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC797_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC797_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC797_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC797_SET_RASTER_INPUT 0x0740 +#define NVC797_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC797_SET_STREAM_OUTPUT 0x0744 +#define NVC797_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC797_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC797_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC797_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC797_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC797_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC797_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC797_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC797_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC797_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC797_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC797_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC797_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC797_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC797_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC797_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC797_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC797_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC797_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC797_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC797_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC797_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC797_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC797_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC797_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC797_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVC797_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC797_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC797_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC797_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC797_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC797_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC797_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC797_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC797_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC797_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC797_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC797_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC797_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC797_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC797_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC797_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC797_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC797_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC797_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC797_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC797_SET_ZCULL_STORAGE_B 0x07ec +#define NVC797_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC797_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC797_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC797_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC797_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC797_SET_ZT_READ_ONLY 0x07f8 +#define NVC797_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC797_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC797_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC797_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC797_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC797_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC797_THROTTLE_SM 0x07fc +#define NVC797_THROTTLE_SM_MULTIPLY_ADD 0:0 +#define NVC797_THROTTLE_SM_MULTIPLY_ADD_FALSE 0x00000000 +#define NVC797_THROTTLE_SM_MULTIPLY_ADD_TRUE 0x00000001 + +#define NVC797_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC797_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC797_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC797_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC797_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC797_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC797_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC797_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC797_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC797_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC797_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC797_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC797_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC797_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC797_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC797_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC797_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC797_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC797_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC797_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC797_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC797_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC797_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC797_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC797_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC797_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC797_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC797_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC797_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC797_SET_COLOR_TARGET_C_ROP_SLICE_MAP(j) (0x0824+(j)*64) +#define NVC797_SET_COLOR_TARGET_C_ROP_SLICE_MAP_VIRTUAL_ADDRESS_MASK 31:0 + +#define NVC797_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC797_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC797_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC797_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC797_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC797_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC797_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC797_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC797_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC797_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC797_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC797_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC797_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC797_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC797_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC797_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC797_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC797_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC797_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC797_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC797_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC797_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC797_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC797_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC797_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC797_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC797_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC797_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC797_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC797_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC797_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC797_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC797_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC797_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC797_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC797_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC797_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC797_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC797_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC797_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC797_SET_STATISTICS_COUNTER 0x0d68 +#define NVC797_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC797_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC797_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC797_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC797_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC797_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC797_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC797_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC797_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC797_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC797_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC797_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC797_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC797_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC797_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC797_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC797_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVC797_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC797_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC797_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC797_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC797_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC797_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC797_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC797_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC797_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC797_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC797_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC797_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC797_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC797_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC797_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC797_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC797_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC797_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC797_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC797_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC797_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC797_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC797_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC797_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC797_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC797_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC797_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC797_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC797_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC797_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC797_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC797_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC797_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC797_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC797_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC797_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC797_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC797_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC797_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC797_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC797_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC797_SET_POLY_SMOOTH 0x0db4 +#define NVC797_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC797_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC797_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC797_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC797_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC797_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC797_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC797_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC797_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC797_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_PATCH 0x0dcc +#define NVC797_SET_PATCH_SIZE 7:0 + +#define NVC797_SET_ITERATED_BLEND 0x0dd0 +#define NVC797_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC797_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC797_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC797_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC797_SET_ZCULL_CRITERION 0x0dd8 +#define NVC797_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC797_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC797_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC797_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC797_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC797_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC797_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC797_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC797_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC797_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC797_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 +#define NVC797_PIXEL_SHADER_BARRIER_BARRIER_LOCATION 1:1 +#define NVC797_PIXEL_SHADER_BARRIER_BARRIER_LOCATION_BLOCK_BEFORE_PS 0x00000000 +#define NVC797_PIXEL_SHADER_BARRIER_BARRIER_LOCATION_BLOCK_BEFORE_PS_AND_ZTEST 0x00000001 + +#define NVC797_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC797_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC797_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC797_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC797_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC797_MME_DMA_WRITE_METHOD_BARRIER 0x0dec +#define NVC797_MME_DMA_WRITE_METHOD_BARRIER_V 0:0 + +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC797_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC797_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC797_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC797_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC797_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC797_SET_SCISSOR_ENABLE_V 0:0 +#define NVC797_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC797_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC797_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC797_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC797_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC797_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC797_SET_VPC_PERF_KNOB 0x0f14 +#define NVC797_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC797_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC797_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC797_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC797_PM_LOCAL_TRIGGER 0x0f18 +#define NVC797_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC797_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC797_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC797_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC797_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC797_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC797_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC797_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC797_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC797_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC797_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC797_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC797_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC797_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC797_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC797_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC797_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC797_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC797_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC797_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC797_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC797_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC797_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC797_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC797_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC797_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC797_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC797_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC797_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC797_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC797_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC797_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC797_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC797_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC797_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC797_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC797_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC797_SET_SAMPLE_MASK 0x0fa4 +#define NVC797_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC797_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC797_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC797_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC797_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC797_SET_CT_MRT_ENABLE 0x0fac +#define NVC797_SET_CT_MRT_ENABLE_V 0:0 +#define NVC797_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC797_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC797_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC797_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC797_SET_TIR 0x0fb4 +#define NVC797_SET_TIR_MODE 1:0 +#define NVC797_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC797_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC797_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC797_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC797_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC797_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC797_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC797_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC797_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC797_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC797_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC797_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC797_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC797_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC797_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC797_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC797_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC797_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC797_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC797_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_TIR_MODULATION 0x0fd4 +#define NVC797_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC797_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC797_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC797_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC797_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC797_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC797_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC797_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC797_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC797_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC797_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC797_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC797_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC797_SET_ZT_A 0x0fe0 +#define NVC797_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_ZT_B 0x0fe4 +#define NVC797_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_ZT_FORMAT 0x0fe8 +#define NVC797_SET_ZT_FORMAT_V 4:0 +#define NVC797_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC797_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC797_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC797_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC797_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC797_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC797_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC797_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC797_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC797_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC797_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC797_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC797_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC797_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC797_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC797_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC797_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC797_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC797_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC797_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC797_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC797_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC797_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC797_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC797_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC797_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC797_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC797_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC797_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC797_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC797_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC797_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC797_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC797_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC797_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC797_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC797_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC797_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC797_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC797_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC797_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC797_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC797_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC797_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC797_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC797_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD02 0x102c +#define NVC797_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC797_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC797_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC797_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC797_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC797_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC797_SET_SPARE_NOOP01 0x1044 +#define NVC797_SET_SPARE_NOOP01_V 31:0 + +#define NVC797_SET_SPARE_NOOP02 0x1048 +#define NVC797_SET_SPARE_NOOP02_V 31:0 + +#define NVC797_SET_SPARE_NOOP03 0x104c +#define NVC797_SET_SPARE_NOOP03_V 31:0 + +#define NVC797_SET_SPARE_NOOP04 0x1050 +#define NVC797_SET_SPARE_NOOP04_V 31:0 + +#define NVC797_SET_SPARE_NOOP05 0x1054 +#define NVC797_SET_SPARE_NOOP05_V 31:0 + +#define NVC797_SET_SPARE_NOOP06 0x1058 +#define NVC797_SET_SPARE_NOOP06_V 31:0 + +#define NVC797_SET_SPARE_NOOP07 0x105c +#define NVC797_SET_SPARE_NOOP07_V 31:0 + +#define NVC797_SET_SPARE_NOOP08 0x1060 +#define NVC797_SET_SPARE_NOOP08_V 31:0 + +#define NVC797_SET_SPARE_NOOP09 0x1064 +#define NVC797_SET_SPARE_NOOP09_V 31:0 + +#define NVC797_SET_SPARE_NOOP10 0x1068 +#define NVC797_SET_SPARE_NOOP10_V 31:0 + +#define NVC797_SET_SPARE_NOOP11 0x106c +#define NVC797_SET_SPARE_NOOP11_V 31:0 + +#define NVC797_SET_SPARE_NOOP12 0x1070 +#define NVC797_SET_SPARE_NOOP12_V 31:0 + +#define NVC797_SET_SPARE_NOOP13 0x1074 +#define NVC797_SET_SPARE_NOOP13_V 31:0 + +#define NVC797_SET_SPARE_NOOP14 0x1078 +#define NVC797_SET_SPARE_NOOP14_V 31:0 + +#define NVC797_SET_SPARE_NOOP15 0x107c +#define NVC797_SET_SPARE_NOOP15_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC797_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC797_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC797_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC797_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC797_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC797_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC797_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC797_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC797_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC797_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC797_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC797_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC797_UNBIND_ALL 0x10f4 +#define NVC797_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC797_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC797_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC797_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC797_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC797_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC797_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC797_NO_OPERATION_DATA_HI 0x110c +#define NVC797_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC797_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC797_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC797_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC797_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC797_PM_TRIGGER_END 0x1114 +#define NVC797_PM_TRIGGER_END_V 31:0 + +#define NVC797_SET_VERTEX_ID_BASE 0x1118 +#define NVC797_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC797_SET_STENCIL_COMPRESSION 0x111c +#define NVC797_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC797_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC797_SET_TIR_CONTROL 0x1130 +#define NVC797_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC797_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC797_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC797_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC797_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC797_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC797_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC797_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC797_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 +#define NVC797_SET_TIR_CONTROL_REDUCTION_MODE 2:2 +#define NVC797_SET_TIR_CONTROL_REDUCTION_MODE_AFFINITY_MAP 0x00000000 +#define NVC797_SET_TIR_CONTROL_REDUCTION_MODE_TRUNCATION 0x00000001 + +#define NVC797_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC797_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC797_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC797_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC797_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC797_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC797_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC797_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC797_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC797_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC797_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC797_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC797_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC797_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC797_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC797_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC797_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC797_FLUSH_PENDING_WRITES 0x1144 +#define NVC797_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC797_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC797_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC797_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC797_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC797_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC797_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC797_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC797_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC797_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC797_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC797_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC797_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC797_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC797_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC797_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC797_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC797_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC797_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC797_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC797_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC797_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC797_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_SCREEN_STATE_MASK 0x1204 +#define NVC797_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC797_SET_ZT_SPARSE 0x1208 +#define NVC797_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC797_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC797_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC797_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_SET_CT_SELECT 0x121c +#define NVC797_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC797_SET_CT_SELECT_TARGET0 6:4 +#define NVC797_SET_CT_SELECT_TARGET1 9:7 +#define NVC797_SET_CT_SELECT_TARGET2 12:10 +#define NVC797_SET_CT_SELECT_TARGET3 15:13 +#define NVC797_SET_CT_SELECT_TARGET4 18:16 +#define NVC797_SET_CT_SELECT_TARGET5 21:19 +#define NVC797_SET_CT_SELECT_TARGET6 24:22 +#define NVC797_SET_CT_SELECT_TARGET7 27:25 + +#define NVC797_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC797_SET_ZT_SIZE_A 0x1228 +#define NVC797_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC797_SET_ZT_SIZE_B 0x122c +#define NVC797_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC797_SET_ZT_SIZE_C 0x1230 +#define NVC797_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC797_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC797_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC797_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC797_SET_SAMPLER_BINDING 0x1234 +#define NVC797_SET_SAMPLER_BINDING_V 0:0 +#define NVC797_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC797_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC797_DRAW_AUTO 0x123c +#define NVC797_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC797_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC797_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC797_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC797_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC797_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC797_SET_BACK_END_COPY_A 0x1264 +#define NVC797_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC797_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC797_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC797_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC797_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BACK_END_COPY_B 0x1268 +#define NVC797_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC797_SET_BACK_END_COPY_C 0x126c +#define NVC797_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC797_SET_BACK_END_COPY_D 0x1270 +#define NVC797_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC797_SET_BACK_END_COPY_E 0x1274 +#define NVC797_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC797_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC797_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVC797_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC797_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC797_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC797_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC797_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC797_CLEAR_ZCULL_REGION 0x12c8 +#define NVC797_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC797_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC797_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC797_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC797_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC797_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC797_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC797_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC797_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC797_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC797_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC797_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC797_SET_DEPTH_TEST 0x12cc +#define NVC797_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC797_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_FILL_MODE 0x12d0 +#define NVC797_SET_FILL_MODE_V 31:0 +#define NVC797_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC797_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC797_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC797_SET_SHADE_MODE 0x12d4 +#define NVC797_SET_SHADE_MODE_V 31:0 +#define NVC797_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC797_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC797_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC797_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC797_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC797_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC797_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC797_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC797_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC797_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC797_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC797_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_DEPTH_WRITE 0x12e8 +#define NVC797_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC797_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_ALPHA_TEST 0x12ec +#define NVC797_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC797_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC797_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC797_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC797_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC797_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC797_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC797_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC797_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC797_D3D_SET_CULL_MODE 0x1308 +#define NVC797_D3D_SET_CULL_MODE_V 31:0 +#define NVC797_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC797_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC797_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC797_SET_DEPTH_FUNC 0x130c +#define NVC797_SET_DEPTH_FUNC_V 31:0 +#define NVC797_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC797_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC797_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC797_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC797_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC797_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC797_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC797_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC797_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC797_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC797_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC797_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC797_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC797_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC797_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC797_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC797_SET_ALPHA_REF 0x1310 +#define NVC797_SET_ALPHA_REF_V 31:0 + +#define NVC797_SET_ALPHA_FUNC 0x1314 +#define NVC797_SET_ALPHA_FUNC_V 31:0 +#define NVC797_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC797_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC797_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC797_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC797_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC797_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC797_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC797_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC797_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC797_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC797_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC797_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC797_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC797_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC797_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC797_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC797_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC797_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC797_SET_BLEND_CONST_RED 0x131c +#define NVC797_SET_BLEND_CONST_RED_V 31:0 + +#define NVC797_SET_BLEND_CONST_GREEN 0x1320 +#define NVC797_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC797_SET_BLEND_CONST_BLUE 0x1324 +#define NVC797_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC797_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC797_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC797_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC797_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC797_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC797_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC797_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC797_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC797_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC797_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BLEND_COLOR_OP 0x1340 +#define NVC797_SET_BLEND_COLOR_OP_V 31:0 +#define NVC797_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC797_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC797_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC797_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC797_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC797_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC797_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC797_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC797_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC797_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_BLEND_ALPHA_OP 0x134c +#define NVC797_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC797_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC797_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC797_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC797_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC797_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC797_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC797_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC797_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC797_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC797_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC797_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC797_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC797_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC797_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC797_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BLEND(i) (0x1360+(i)*4) +#define NVC797_SET_BLEND_ENABLE 0:0 +#define NVC797_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_STENCIL_TEST 0x1380 +#define NVC797_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC797_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_STENCIL_OP_FAIL 0x1384 +#define NVC797_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC797_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC797_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC797_SET_STENCIL_OP_ZPASS 0x138c +#define NVC797_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC797_SET_STENCIL_FUNC 0x1390 +#define NVC797_SET_STENCIL_FUNC_V 31:0 +#define NVC797_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC797_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC797_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC797_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC797_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC797_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC797_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC797_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC797_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC797_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC797_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC797_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC797_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC797_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC797_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC797_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC797_SET_STENCIL_FUNC_REF 0x1394 +#define NVC797_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC797_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC797_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC797_SET_STENCIL_MASK 0x139c +#define NVC797_SET_STENCIL_MASK_V 7:0 + +#define NVC797_SET_DRAW_AUTO_START 0x13a4 +#define NVC797_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC797_SET_PS_SATURATE 0x13a8 +#define NVC797_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC797_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC797_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC797_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC797_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC797_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC797_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC797_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC797_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC797_SET_WINDOW_ORIGIN 0x13ac +#define NVC797_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC797_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC797_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC797_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC797_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC797_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC797_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC797_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC797_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC797_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC797_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC797_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC797_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC797_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC797_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC797_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC797_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC797_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC797_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC797_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC797_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC797_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC797_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC797_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC797_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC797_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC797_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC797_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC797_STORE_ZCULL 0x1464 +#define NVC797_STORE_ZCULL_V 0:0 + +#define NVC797_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC797_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC797_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC797_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC797_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC797_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC797_LOAD_ZCULL 0x1500 +#define NVC797_LOAD_ZCULL_V 0:0 + +#define NVC797_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC797_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC797_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC797_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC797_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC797_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC797_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC797_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC797_SET_USER_CLIP_ENABLE 0x1510 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC797_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC797_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC797_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_POINT_SIZE 0x1518 +#define NVC797_SET_POINT_SIZE_V 31:0 + +#define NVC797_SET_ZCULL_STATS 0x151c +#define NVC797_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC797_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_POINT_SPRITE 0x1520 +#define NVC797_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC797_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC797_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC797_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC797_CLEAR_REPORT_VALUE 0x1530 +#define NVC797_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC797_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC797_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC797_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC797_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC797_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC797_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVC797_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC797_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC797_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_ZT_SELECT 0x1538 +#define NVC797_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC797_SET_RENDER_ENABLE_A 0x1550 +#define NVC797_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_RENDER_ENABLE_B 0x1554 +#define NVC797_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_RENDER_ENABLE_C 0x1558 +#define NVC797_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC797_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC797_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC797_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC797_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC797_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC797_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC797_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC797_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC797_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC797_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC797_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC797_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC797_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC797_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC797_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC797_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_TEX_HEADER_POOL_C 0x157c +#define NVC797_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC797_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC797_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC797_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC797_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC797_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC797_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC797_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC797_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC797_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC797_SET_SRGB_WRITE 0x15b8 +#define NVC797_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC797_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_DEPTH_BIAS 0x15bc +#define NVC797_SET_DEPTH_BIAS_V 31:0 + +#define NVC797_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC797_SET_RT_LAYER 0x15cc +#define NVC797_SET_RT_LAYER_V 15:0 +#define NVC797_SET_RT_LAYER_CONTROL 16:16 +#define NVC797_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC797_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC797_SET_ANTI_ALIAS 0x15d0 +#define NVC797_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC797_SET_EDGE_FLAG 0x15e4 +#define NVC797_SET_EDGE_FLAG_V 0:0 +#define NVC797_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC797_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC797_DRAW_INLINE_INDEX 0x15e8 +#define NVC797_DRAW_INLINE_INDEX_V 31:0 + +#define NVC797_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC797_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC797_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC797_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC797_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC797_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC797_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC797_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC797_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC797_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC797_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC797_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC797_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC797_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC797_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC797_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC797_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC797_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC797_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC797_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC797_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC797_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC797_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC797_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC797_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC797_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC797_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC797_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC797_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC797_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC797_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC797_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC797_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC797_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC797_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC797_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC797_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC797_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC797_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC797_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC797_END 0x1614 +#define NVC797_END_V 0:0 + +#define NVC797_BEGIN 0x1618 +#define NVC797_BEGIN_OP 15:0 +#define NVC797_BEGIN_OP_POINTS 0x00000000 +#define NVC797_BEGIN_OP_LINES 0x00000001 +#define NVC797_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC797_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC797_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC797_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC797_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC797_BEGIN_OP_QUADS 0x00000007 +#define NVC797_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC797_BEGIN_OP_POLYGON 0x00000009 +#define NVC797_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC797_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC797_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_BEGIN_OP_PATCH 0x0000000E +#define NVC797_BEGIN_PRIMITIVE_ID 24:24 +#define NVC797_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC797_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC797_BEGIN_INSTANCE_ID 27:26 +#define NVC797_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC797_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC797_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC797_BEGIN_SPLIT_MODE 30:29 +#define NVC797_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC797_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC797_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC797_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC797_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVC797_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC797_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_VERTEX_ID_COPY 0x161c +#define NVC797_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC797_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC797_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC797_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC797_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC797_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC797_LOAD_PRIMITIVE_ID 0x1624 +#define NVC797_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC797_SET_SHADER_BASED_CULL 0x162c +#define NVC797_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC797_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC797_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC797_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_CLASS_VERSION 0x1638 +#define NVC797_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC797_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC797_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC797_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC797_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC797_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC797_SET_DA_OUTPUT 0x164c +#define NVC797_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC797_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC797_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC797_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC797_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_POINT_CENTER_MODE 0x165c +#define NVC797_SET_POINT_CENTER_MODE_V 31:0 +#define NVC797_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC797_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC797_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC797_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC797_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC797_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC797_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC797_SET_LINE_STIPPLE 0x166c +#define NVC797_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC797_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC797_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC797_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC797_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC797_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC797_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC797_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC797_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC797_SET_PROVOKING_VERTEX 0x1684 +#define NVC797_SET_PROVOKING_VERTEX_V 0:0 +#define NVC797_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC797_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC797_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC797_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC797_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_POLYGON_STIPPLE 0x168c +#define NVC797_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC797_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_SHADER_CONTROL 0x1690 +#define NVC797_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC797_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC797_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC797_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC797_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC797_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC797_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC797_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC797_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC797_CHECK_CLASS_VERSION 0x16a0 +#define NVC797_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC797_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC797_SET_SPH_VERSION 0x16a4 +#define NVC797_SET_SPH_VERSION_CURRENT 15:0 +#define NVC797_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC797_CHECK_SPH_VERSION 0x16a8 +#define NVC797_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC797_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC797_SET_SCG_GRAPHICS_PRIORITY 0x16bc +#define NVC797_SET_SCG_GRAPHICS_PRIORITY_PRIORITY 5:0 + +#define NVC797_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS(i) (0x16c0+(i)*4) +#define NVC797_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC797_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC797_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC797_SET_AAM_VERSION 0x1790 +#define NVC797_SET_AAM_VERSION_CURRENT 15:0 +#define NVC797_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC797_CHECK_AAM_VERSION 0x1794 +#define NVC797_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC797_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC797_SET_ZT_LAYER 0x179c +#define NVC797_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC797_SET_INDEX_BUFFER_A 0x17c8 +#define NVC797_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC797_SET_INDEX_BUFFER_B 0x17cc +#define NVC797_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC797_SET_INDEX_BUFFER_E 0x17d8 +#define NVC797_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC797_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC797_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC797_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC797_SET_INDEX_BUFFER_F 0x17dc +#define NVC797_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC797_DRAW_INDEX_BUFFER 0x17e0 +#define NVC797_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC797_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC797_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC797_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC797_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC797_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC797_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC797_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC797_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC797_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC797_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC797_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC797_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC797_OGL_SET_CULL 0x1918 +#define NVC797_OGL_SET_CULL_ENABLE 0:0 +#define NVC797_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC797_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC797_OGL_SET_FRONT_FACE 0x191c +#define NVC797_OGL_SET_FRONT_FACE_V 31:0 +#define NVC797_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC797_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC797_OGL_SET_CULL_FACE 0x1920 +#define NVC797_OGL_SET_CULL_FACE_V 31:0 +#define NVC797_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC797_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC797_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC797_SET_VIEWPORT_PIXEL 0x1924 +#define NVC797_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC797_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC797_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC797_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC797_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC797_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC797_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE 17:16 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_USE_FIELD_MIN_Z_ZERO_MAX_Z_ONE 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MIN_Z_MAX_Z 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_ZERO_ONE 0x00000002 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MINUS_INF_PLUS_INF 0x00000003 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC797_SET_USER_CLIP_OP 0x1940 +#define NVC797_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC797_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC797_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC797_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC797_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC797_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC797_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC797_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC797_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC797_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC797_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC797_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC797_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC797_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC797_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC797_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC797_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC797_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC797_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC797_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC797_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC797_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC797_INVALIDATE_ZCULL 0x1958 +#define NVC797_INVALIDATE_ZCULL_V 31:0 +#define NVC797_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC797_SET_ZCULL 0x1968 +#define NVC797_SET_ZCULL_Z_ENABLE 0:0 +#define NVC797_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC797_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_ZCULL_BOUNDS 0x196c +#define NVC797_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC797_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC797_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC797_ZCULL_SYNC 0x1978 +#define NVC797_ZCULL_SYNC_V 31:0 + +#define NVC797_SET_CLIP_ID_TEST 0x197c +#define NVC797_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC797_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC797_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC797_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC797_SET_CLIP_ID 0x1984 +#define NVC797_SET_CLIP_ID_V 31:0 + +#define NVC797_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC797_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC797_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC797_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC797_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC797_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC797_SET_LOGIC_OP 0x19c4 +#define NVC797_SET_LOGIC_OP_ENABLE 0:0 +#define NVC797_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC797_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC797_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC797_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC797_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC797_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC797_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC797_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC797_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC797_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC797_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC797_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC797_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC797_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC797_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC797_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC797_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC797_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC797_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC797_SET_Z_COMPRESSION 0x19cc +#define NVC797_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC797_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC797_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC797_CLEAR_SURFACE 0x19d0 +#define NVC797_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC797_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC797_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC797_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC797_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC797_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC797_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC797_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC797_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC797_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC797_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC797_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC797_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC797_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC797_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC797_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC797_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC797_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC797_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC797_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC797_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC797_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC797_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC797_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC797_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC797_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC797_PIPE_NOP 0x1a2c +#define NVC797_PIPE_NOP_V 31:0 + +#define NVC797_SET_SPARE00 0x1a30 +#define NVC797_SET_SPARE00_V 31:0 + +#define NVC797_SET_SPARE01 0x1a34 +#define NVC797_SET_SPARE01_V 31:0 + +#define NVC797_SET_SPARE02 0x1a38 +#define NVC797_SET_SPARE02_V 31:0 + +#define NVC797_SET_SPARE03 0x1a3c +#define NVC797_SET_SPARE03_V 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC797_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC797_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC797_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC797_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC797_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC797_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC797_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC797_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC797_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC797_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC797_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC797_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_TIMESTAMP 0x00000014 +#define NVC797_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC797_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC797_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC797_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC797_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC797_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC797_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC797_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC797_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC797_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC797_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC797_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC797_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC797_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC797_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC797_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC797_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC797_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC797_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC797_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC797_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC797_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC797_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC797_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC797_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC797_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC797_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC797_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC797_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC797_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC797_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC797_SET_PIPELINE_RESERVED_B(j) (0x2004+(j)*64) +#define NVC797_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVC797_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC797_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC797_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC797_SET_PIPELINE_REGISTER_COUNT_V 8:0 + +#define NVC797_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC797_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC797_SET_PIPELINE_PROGRAM_ADDRESS_A(j) (0x2014+(j)*64) +#define NVC797_SET_PIPELINE_PROGRAM_ADDRESS_A_UPPER 7:0 + +#define NVC797_SET_PIPELINE_PROGRAM_ADDRESS_B(j) (0x2018+(j)*64) +#define NVC797_SET_PIPELINE_PROGRAM_ADDRESS_B_LOWER 31:0 + +#define NVC797_SET_PIPELINE_PROGRAM_PREFETCH(j) (0x201c+(j)*64) +#define NVC797_SET_PIPELINE_PROGRAM_PREFETCH_SIZE_IN_BLOCKS 6:0 + +#define NVC797_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC797_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC797_SET_FALCON00 0x2300 +#define NVC797_SET_FALCON00_V 31:0 + +#define NVC797_SET_FALCON01 0x2304 +#define NVC797_SET_FALCON01_V 31:0 + +#define NVC797_SET_FALCON02 0x2308 +#define NVC797_SET_FALCON02_V 31:0 + +#define NVC797_SET_FALCON03 0x230c +#define NVC797_SET_FALCON03_V 31:0 + +#define NVC797_SET_FALCON04 0x2310 +#define NVC797_SET_FALCON04_V 31:0 + +#define NVC797_SET_FALCON05 0x2314 +#define NVC797_SET_FALCON05_V 31:0 + +#define NVC797_SET_FALCON06 0x2318 +#define NVC797_SET_FALCON06_V 31:0 + +#define NVC797_SET_FALCON07 0x231c +#define NVC797_SET_FALCON07_V 31:0 + +#define NVC797_SET_FALCON08 0x2320 +#define NVC797_SET_FALCON08_V 31:0 + +#define NVC797_SET_FALCON09 0x2324 +#define NVC797_SET_FALCON09_V 31:0 + +#define NVC797_SET_FALCON10 0x2328 +#define NVC797_SET_FALCON10_V 31:0 + +#define NVC797_SET_FALCON11 0x232c +#define NVC797_SET_FALCON11_V 31:0 + +#define NVC797_SET_FALCON12 0x2330 +#define NVC797_SET_FALCON12_V 31:0 + +#define NVC797_SET_FALCON13 0x2334 +#define NVC797_SET_FALCON13_V 31:0 + +#define NVC797_SET_FALCON14 0x2338 +#define NVC797_SET_FALCON14_V 31:0 + +#define NVC797_SET_FALCON15 0x233c +#define NVC797_SET_FALCON15_V 31:0 + +#define NVC797_SET_FALCON16 0x2340 +#define NVC797_SET_FALCON16_V 31:0 + +#define NVC797_SET_FALCON17 0x2344 +#define NVC797_SET_FALCON17_V 31:0 + +#define NVC797_SET_FALCON18 0x2348 +#define NVC797_SET_FALCON18_V 31:0 + +#define NVC797_SET_FALCON19 0x234c +#define NVC797_SET_FALCON19_V 31:0 + +#define NVC797_SET_FALCON20 0x2350 +#define NVC797_SET_FALCON20_V 31:0 + +#define NVC797_SET_FALCON21 0x2354 +#define NVC797_SET_FALCON21_V 31:0 + +#define NVC797_SET_FALCON22 0x2358 +#define NVC797_SET_FALCON22_V 31:0 + +#define NVC797_SET_FALCON23 0x235c +#define NVC797_SET_FALCON23_V 31:0 + +#define NVC797_SET_FALCON24 0x2360 +#define NVC797_SET_FALCON24_V 31:0 + +#define NVC797_SET_FALCON25 0x2364 +#define NVC797_SET_FALCON25_V 31:0 + +#define NVC797_SET_FALCON26 0x2368 +#define NVC797_SET_FALCON26_V 31:0 + +#define NVC797_SET_FALCON27 0x236c +#define NVC797_SET_FALCON27_V 31:0 + +#define NVC797_SET_FALCON28 0x2370 +#define NVC797_SET_FALCON28_V 31:0 + +#define NVC797_SET_FALCON29 0x2374 +#define NVC797_SET_FALCON29_V 31:0 + +#define NVC797_SET_FALCON30 0x2378 +#define NVC797_SET_FALCON30_V 31:0 + +#define NVC797_SET_FALCON31 0x237c +#define NVC797_SET_FALCON31_V 31:0 + +#define NVC797_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC797_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC797_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC797_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC797_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC797_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC797_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC797_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC797_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC797_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC797_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC797_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC797_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC797_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC797_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC797_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC797_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC797_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC797_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC797_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC797_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC797_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC797_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC797_SET_TRAP_HANDLER_A 0x25f8 +#define NVC797_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC797_SET_TRAP_HANDLER_B 0x25fc +#define NVC797_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC797_SET_COLOR_CLAMP 0x2600 +#define NVC797_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC797_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC797_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC797_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC797_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC797_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC797_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC797_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC797_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC797_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC797_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC797_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC797_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC797_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC797_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC797_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC797_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC797_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC797_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC797_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC797_CALL_MME_MACRO_V 31:0 + +#define NVC797_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC797_CALL_MME_DATA_V 31:0 + +#endif /* _cl_ampere_b_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc7b0.h b/userspace/sdks/nv525/nvidia/inc/class/clc7b0.h new file mode 100644 index 0000000..8c98771 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc7b0.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clc7b0_h_ +#define clc7b0_h_ + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC7B0_VIDEO_DECODER (0x0000C7B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc7b0_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc7b5.h b/userspace/sdks/nv525/nvidia/inc/class/clc7b5.h new file mode 100644 index 0000000..df331e8 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc7b5.h @@ -0,0 +1,304 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clc7b5_h_ +#define _clc7b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define AMPERE_DMA_COPY_B (0x0000C7B5) + +#define NVC7B5_NOP (0x00000100) +#define NVC7B5_NOP_PARAMETER 31:0 +#define NVC7B5_PM_TRIGGER (0x00000140) +#define NVC7B5_PM_TRIGGER_V 31:0 +#define NVC7B5_SET_MONITORED_FENCE_TYPE (0x0000021C) +#define NVC7B5_SET_MONITORED_FENCE_TYPE_TYPE 0:0 +#define NVC7B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE (0x00000000) +#define NVC7B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE_EXT (0x00000001) +#define NVC7B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER (0x00000220) +#define NVC7B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER_UPPER 16:0 +#define NVC7B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER (0x00000224) +#define NVC7B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER_LOWER 31:0 +#define NVC7B5_SET_SEMAPHORE_A (0x00000240) +#define NVC7B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC7B5_SET_SEMAPHORE_B (0x00000244) +#define NVC7B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC7B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC7B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC7B5_SET_SEMAPHORE_PAYLOAD_UPPER (0x0000024C) +#define NVC7B5_SET_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD 31:0 +#define NVC7B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC7B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC7B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC7B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC7B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC7B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC7B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC7B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC7B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC7B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC7B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC7B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC7B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC7B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC7B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC7B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC7B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVC7B5_SET_SRC_PHYS_MODE_BASIC_KIND 5:2 +#define NVC7B5_SET_SRC_PHYS_MODE_PEER_ID 8:6 +#define NVC7B5_SET_SRC_PHYS_MODE_FLA 9:9 +#define NVC7B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC7B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC7B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC7B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC7B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC7B5_SET_DST_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVC7B5_SET_DST_PHYS_MODE_BASIC_KIND 5:2 +#define NVC7B5_SET_DST_PHYS_MODE_PEER_ID 8:6 +#define NVC7B5_SET_DST_PHYS_MODE_FLA 9:9 +#define NVC7B5_LAUNCH_DMA (0x00000300) +#define NVC7B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC7B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC7B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC7B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC7B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC7B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC7B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC7B5_LAUNCH_DMA_FLUSH_TYPE 25:25 +#define NVC7B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000) +#define NVC7B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_NO_TIMESTAMP (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_WITH_TIMESTAMP (0x00000002) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE (0x00000003) +#define NVC7B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC7B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC7B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC7B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC7B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC7B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC7B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC7B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC7B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC7B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC7B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC7B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC7B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC7B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC7B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC7B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC7B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC7B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC7B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC7B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC7B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC7B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC7B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC7B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC7B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDA (0x00000008) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDB (0x00000009) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN (0x0000000B) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX (0x0000000C) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDC (0x0000000D) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDD (0x0000000E) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDE (0x0000000F) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC7B5_LAUNCH_DMA_VPRMODE 23:22 +#define NVC7B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVC7B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC7B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC7B5_LAUNCH_DMA_DISABLE_PLC 26:26 +#define NVC7B5_LAUNCH_DMA_DISABLE_PLC_FALSE (0x00000000) +#define NVC7B5_LAUNCH_DMA_DISABLE_PLC_TRUE (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE 27:27 +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_ONE_WORD (0x00000000) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_TWO_WORD (0x00000001) +#define NVC7B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 +#define NVC7B5_OFFSET_IN_UPPER (0x00000400) +#define NVC7B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC7B5_OFFSET_IN_LOWER (0x00000404) +#define NVC7B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC7B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC7B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC7B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC7B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC7B5_PITCH_IN (0x00000410) +#define NVC7B5_PITCH_IN_VALUE 31:0 +#define NVC7B5_PITCH_OUT (0x00000414) +#define NVC7B5_PITCH_OUT_VALUE 31:0 +#define NVC7B5_LINE_LENGTH_IN (0x00000418) +#define NVC7B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC7B5_LINE_COUNT (0x0000041C) +#define NVC7B5_LINE_COUNT_VALUE 31:0 +#define NVC7B5_SET_REMAP_CONST_A (0x00000700) +#define NVC7B5_SET_REMAP_CONST_A_V 31:0 +#define NVC7B5_SET_REMAP_CONST_B (0x00000704) +#define NVC7B5_SET_REMAP_CONST_B_V 31:0 +#define NVC7B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC7B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC7B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC7B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC7B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC7B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC7B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC7B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC7B5_SET_DST_WIDTH (0x00000710) +#define NVC7B5_SET_DST_WIDTH_V 31:0 +#define NVC7B5_SET_DST_HEIGHT (0x00000714) +#define NVC7B5_SET_DST_HEIGHT_V 31:0 +#define NVC7B5_SET_DST_DEPTH (0x00000718) +#define NVC7B5_SET_DST_DEPTH_V 31:0 +#define NVC7B5_SET_DST_LAYER (0x0000071C) +#define NVC7B5_SET_DST_LAYER_V 31:0 +#define NVC7B5_SET_DST_ORIGIN (0x00000720) +#define NVC7B5_SET_DST_ORIGIN_X 15:0 +#define NVC7B5_SET_DST_ORIGIN_Y 31:16 +#define NVC7B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC7B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC7B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC7B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC7B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC7B5_SET_SRC_WIDTH (0x0000072C) +#define NVC7B5_SET_SRC_WIDTH_V 31:0 +#define NVC7B5_SET_SRC_HEIGHT (0x00000730) +#define NVC7B5_SET_SRC_HEIGHT_V 31:0 +#define NVC7B5_SET_SRC_DEPTH (0x00000734) +#define NVC7B5_SET_SRC_DEPTH_V 31:0 +#define NVC7B5_SET_SRC_LAYER (0x00000738) +#define NVC7B5_SET_SRC_LAYER_V 31:0 +#define NVC7B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC7B5_SET_SRC_ORIGIN_X 15:0 +#define NVC7B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC7B5_SRC_ORIGIN_X (0x00000744) +#define NVC7B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC7B5_SRC_ORIGIN_Y (0x00000748) +#define NVC7B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC7B5_DST_ORIGIN_X (0x0000074C) +#define NVC7B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC7B5_DST_ORIGIN_Y (0x00000750) +#define NVC7B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC7B5_PM_TRIGGER_END (0x00001114) +#define NVC7B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc7b5_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc7b7.h b/userspace/sdks/nv525/nvidia/inc/class/clc7b7.h new file mode 100644 index 0000000..909195b --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc7b7.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef clc7b7_h_ +#define clc7b7_h_ + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC7B7_VIDEO_ENCODER (0x0000C7B7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc7b7_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc7c0.h b/userspace/sdks/nv525/nvidia/inc/class/clc7c0.h new file mode 100644 index 0000000..6eb2889 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc7c0.h @@ -0,0 +1,848 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_ampere_compute_b_h_ +#define _cl_ampere_compute_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl ampere_compute_b */ + +#include "nvtypes.h" + +#define AMPERE_COMPUTE_B 0xC7C0 + +#define NVC7C0_SET_OBJECT 0x0000 +#define NVC7C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC7C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC7C0_NO_OPERATION 0x0100 +#define NVC7C0_NO_OPERATION_V 31:0 + +#define NVC7C0_SET_NOTIFY_A 0x0104 +#define NVC7C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC7C0_SET_NOTIFY_B 0x0108 +#define NVC7C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC7C0_NOTIFY 0x010c +#define NVC7C0_NOTIFY_TYPE 31:0 +#define NVC7C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC7C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC7C0_WAIT_FOR_IDLE 0x0110 +#define NVC7C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC7C0_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC7C0_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC7C0_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC7C0_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC7C0_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC7C0_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC7C0_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC7C0_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC7C0_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC7C0_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC7C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC7C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC7C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC7C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC7C0_SEND_GO_IDLE 0x013c +#define NVC7C0_SEND_GO_IDLE_V 31:0 + +#define NVC7C0_PM_TRIGGER 0x0140 +#define NVC7C0_PM_TRIGGER_V 31:0 + +#define NVC7C0_PM_TRIGGER_WFI 0x0144 +#define NVC7C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC7C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC7C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC7C0_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC7C0_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC7C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC7C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC7C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC7C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER 0x0158 +#define NVC7C0_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER_PAYLOAD_LOWER 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER 0x015c +#define NVC7C0_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD_UPPER 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_ADDRESS_LOWER 0x0160 +#define NVC7C0_SET_REPORT_SEMAPHORE_ADDRESS_LOWER_LOWER 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_ADDRESS_UPPER 0x0164 +#define NVC7C0_SET_REPORT_SEMAPHORE_ADDRESS_UPPER_UPPER 7:0 + +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE 0x0168 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_OPERATION 1:0 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_OPERATION_RELEASE 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_OPERATION_ACQUIRE 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_OPERATION_REPORT_ONLY 0x00000002 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_OPERATION_TRAP 0x00000003 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE 2:2 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE 4:3 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE 5:5 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE 6:6 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP 9:7 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_INC 0x00000003 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_AND 0x00000005 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_OR 0x00000006 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT 11:10 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64 12:12 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_FALSE 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_TRUE 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE 14:13 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_NONE 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 + +#define NVC7C0_LINE_LENGTH_IN 0x0180 +#define NVC7C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC7C0_LINE_COUNT 0x0184 +#define NVC7C0_LINE_COUNT_VALUE 31:0 + +#define NVC7C0_OFFSET_OUT_UPPER 0x0188 +#define NVC7C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC7C0_OFFSET_OUT 0x018c +#define NVC7C0_OFFSET_OUT_VALUE 31:0 + +#define NVC7C0_PITCH_OUT 0x0190 +#define NVC7C0_PITCH_OUT_VALUE 31:0 + +#define NVC7C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC7C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC7C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC7C0_SET_DST_WIDTH 0x0198 +#define NVC7C0_SET_DST_WIDTH_V 31:0 + +#define NVC7C0_SET_DST_HEIGHT 0x019c +#define NVC7C0_SET_DST_HEIGHT_V 31:0 + +#define NVC7C0_SET_DST_DEPTH 0x01a0 +#define NVC7C0_SET_DST_DEPTH_V 31:0 + +#define NVC7C0_SET_DST_LAYER 0x01a4 +#define NVC7C0_SET_DST_LAYER_V 31:0 + +#define NVC7C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC7C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC7C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC7C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC7C0_LAUNCH_DMA 0x01b0 +#define NVC7C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC7C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC7C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC7C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC7C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC7C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC7C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC7C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC7C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC7C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC7C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC7C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC7C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC7C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC7C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC7C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC7C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC7C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC7C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC7C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC7C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC7C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC7C0_LOAD_INLINE_DATA 0x01b4 +#define NVC7C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC7C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC7C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC7C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC7C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC7C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC7C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC7C0_SET_SM_SCG_CONTROL 0x01e8 +#define NVC7C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS 0:0 +#define NVC7C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE 0x00000000 +#define NVC7C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE 0x00000001 + +#define NVC7C0_SET_MME_SWITCH_STATE 0x01ec +#define NVC7C0_SET_MME_SWITCH_STATE_VALID 0:0 +#define NVC7C0_SET_MME_SWITCH_STATE_VALID_FALSE 0x00000000 +#define NVC7C0_SET_MME_SWITCH_STATE_VALID_TRUE 0x00000001 +#define NVC7C0_SET_MME_SWITCH_STATE_SAVE_MACRO 11:4 +#define NVC7C0_SET_MME_SWITCH_STATE_RESTORE_MACRO 19:12 + +#define NVC7C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC7C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC7C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC7C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC7C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC7C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC7C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC7C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC7C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC7C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC7C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC7C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC7C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC7C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC7C0_PERFMON_TRANSFER 0x0210 +#define NVC7C0_PERFMON_TRANSFER_V 31:0 + +#define NVC7C0_SET_QMD_VIRTUALIZATION_BASE_A 0x0214 +#define NVC7C0_SET_QMD_VIRTUALIZATION_BASE_A_ADDRESS_UPPER 7:0 + +#define NVC7C0_SET_QMD_VIRTUALIZATION_BASE_B 0x0218 +#define NVC7C0_SET_QMD_VIRTUALIZATION_BASE_B_ADDRESS_LOWER 31:0 + +#define NVC7C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC7C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC7C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC7C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC7C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC7C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC7C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC7C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC7C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC7C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC7C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC7C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC7C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC7C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC7C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC7C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC7C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC7C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC7C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC7C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC7C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC7C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC7C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC7C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC7C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC7C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC7C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC7C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC7C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC7C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC7C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC7C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC7C0_SET_SCG_CONTROL 0x0270 +#define NVC7C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 +#define NVC7C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 +#define NVC7C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 +#define NVC7C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 +#define NVC7C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 + +#define NVC7C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC7C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC7C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC7C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC7C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC7C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC7C0_SET_QMD_VERSION 0x0288 +#define NVC7C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC7C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC7C0_CHECK_QMD_VERSION 0x0290 +#define NVC7C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC7C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC7C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC7C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL 0x029c +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_CONSTANT_BUFFER_MASK 7:0 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE 8:8 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE 12:12 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_DEPENDENT_ENABLE 9:9 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_DEPENDENT_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_DEPENDENT_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE 16:16 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE 20:20 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_DEPENDENT_ENABLE 10:10 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_DEPENDENT_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_DEPENDENT_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE 24:24 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_TRUE 0x00000001 + +#define NVC7C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC7C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC7C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC7C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC7C0_SCG_HYSTERESIS_CONTROL 0x02a8 +#define NVC7C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 +#define NVC7C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC7C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 +#define NVC7C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 +#define NVC7C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC7C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 + +#define NVC7C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC7C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC7C0_SEND_PCAS_A 0x02b4 +#define NVC7C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC7C0_SEND_PCAS_B 0x02b8 +#define NVC7C0_SEND_PCAS_B_FROM 23:0 +#define NVC7C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC7C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC7C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC7C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC7C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC7C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC7C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC7C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC7C0_SEND_SIGNALING_PCAS2_B 0x02c0 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION 3:0 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_NOP 0x00000000 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE 0x00000001 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_SCHEDULE 0x00000002 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_COPY_SCHEDULE 0x00000003 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_PUT 0x00000006 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_DECREMENT_DEPENDENCE 0x00000007 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH 0x00000008 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH_SCHEDULE 0x00000009 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_SCHEDULE 0x0000000A +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_FORCE_REQUIRE_SCHEDULING 0x0000000B +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_DEPENDENCE 0x0000000C +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_CWD_REF_COUNTER 0x0000000D +#define NVC7C0_SEND_SIGNALING_PCAS2_B_SELECT 13:8 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_OFFSET_MINUS_ONE 23:14 + +#define NVC7C0_SET_SKED_CACHE_CONTROL 0x02cc +#define NVC7C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID 0:0 +#define NVC7C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE 0x00000000 +#define NVC7C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE 0x00000001 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC7C0_SET_SPA_VERSION 0x0310 +#define NVC7C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC7C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC7C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC7C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC7C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC7C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC7C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC7C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC7C0_SET_FALCON00 0x0500 +#define NVC7C0_SET_FALCON00_V 31:0 + +#define NVC7C0_SET_FALCON01 0x0504 +#define NVC7C0_SET_FALCON01_V 31:0 + +#define NVC7C0_SET_FALCON02 0x0508 +#define NVC7C0_SET_FALCON02_V 31:0 + +#define NVC7C0_SET_FALCON03 0x050c +#define NVC7C0_SET_FALCON03_V 31:0 + +#define NVC7C0_SET_FALCON04 0x0510 +#define NVC7C0_SET_FALCON04_V 31:0 + +#define NVC7C0_SET_FALCON05 0x0514 +#define NVC7C0_SET_FALCON05_V 31:0 + +#define NVC7C0_SET_FALCON06 0x0518 +#define NVC7C0_SET_FALCON06_V 31:0 + +#define NVC7C0_SET_FALCON07 0x051c +#define NVC7C0_SET_FALCON07_V 31:0 + +#define NVC7C0_SET_FALCON08 0x0520 +#define NVC7C0_SET_FALCON08_V 31:0 + +#define NVC7C0_SET_FALCON09 0x0524 +#define NVC7C0_SET_FALCON09_V 31:0 + +#define NVC7C0_SET_FALCON10 0x0528 +#define NVC7C0_SET_FALCON10_V 31:0 + +#define NVC7C0_SET_FALCON11 0x052c +#define NVC7C0_SET_FALCON11_V 31:0 + +#define NVC7C0_SET_FALCON12 0x0530 +#define NVC7C0_SET_FALCON12_V 31:0 + +#define NVC7C0_SET_FALCON13 0x0534 +#define NVC7C0_SET_FALCON13_V 31:0 + +#define NVC7C0_SET_FALCON14 0x0538 +#define NVC7C0_SET_FALCON14_V 31:0 + +#define NVC7C0_SET_FALCON15 0x053c +#define NVC7C0_SET_FALCON15_V 31:0 + +#define NVC7C0_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVC7C0_SET_MME_MEM_ADDRESS_A_UPPER 16:0 + +#define NVC7C0_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVC7C0_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVC7C0_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVC7C0_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVC7C0_MME_DMA_READ 0x055c +#define NVC7C0_MME_DMA_READ_LENGTH 31:0 + +#define NVC7C0_MME_DMA_READ_FIFOED 0x0560 +#define NVC7C0_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVC7C0_MME_DMA_WRITE 0x0564 +#define NVC7C0_MME_DMA_WRITE_LENGTH 31:0 + +#define NVC7C0_MME_DMA_REDUCTION 0x0568 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVC7C0_MME_DMA_SYSMEMBAR 0x056c +#define NVC7C0_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVC7C0_MME_DMA_SYNC 0x0570 +#define NVC7C0_MME_DMA_SYNC_VALUE 31:0 + +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC7C0_THROTTLE_SM 0x07fc +#define NVC7C0_THROTTLE_SM_MULTIPLY_ADD 0:0 +#define NVC7C0_THROTTLE_SM_MULTIPLY_ADD_FALSE 0x00000000 +#define NVC7C0_THROTTLE_SM_MULTIPLY_ADD_TRUE 0x00000001 + +#define NVC7C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC7C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC7C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC7C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS(i) (0x0da0+(i)*4) +#define NVC7C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC7C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC7C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC7C0_MME_DMA_WRITE_METHOD_BARRIER 0x0dec +#define NVC7C0_MME_DMA_WRITE_METHOD_BARRIER_V 0:0 + +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC7C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC7C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC7C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC7C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC7C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC7C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC7C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC7C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC7C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC7C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC7C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC7C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC7C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC7C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC7C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC7C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC7C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC7C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC7C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC7C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC7C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC7C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC7C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC7C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC7C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC7C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC7C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC7C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC7C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC7C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC7C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC7C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC7C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC7C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC7C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC7C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC7C0_PIPE_NOP 0x1a2c +#define NVC7C0_PIPE_NOP_V 31:0 + +#define NVC7C0_SET_SPARE00 0x1a30 +#define NVC7C0_SET_SPARE00_V 31:0 + +#define NVC7C0_SET_SPARE01 0x1a34 +#define NVC7C0_SET_SPARE01_V 31:0 + +#define NVC7C0_SET_SPARE02 0x1a38 +#define NVC7C0_SET_SPARE02_V 31:0 + +#define NVC7C0_SET_SPARE03 0x1a3c +#define NVC7C0_SET_SPARE03_V 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC7C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC7C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC7C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC7C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC7C0_SET_TRAP_HANDLER_A 0x25f8 +#define NVC7C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC7C0_SET_TRAP_HANDLER_B 0x25fc +#define NVC7C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC7C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC7C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC7C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC7C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC7C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC7C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC7C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC7C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC7C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC7C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC7C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC7C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC7C0_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC7C0_CALL_MME_MACRO_V 31:0 + +#define NVC7C0_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC7C0_CALL_MME_DATA_V 31:0 + +#endif /* _cl_ampere_compute_b_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc7fa.h b/userspace/sdks/nv525/nvidia/inc/class/clc7fa.h new file mode 100644 index 0000000..50892c5 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc7fa.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "nvtypes.h" + +#ifndef _clc7fa_h_ +#define _clc7fa_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC7FA_VIDEO_OFA (0x0000C7FA) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc7fa_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc86f.h b/userspace/sdks/nv525/nvidia/inc/class/clc86f.h new file mode 100644 index 0000000..48154a3 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc86f.h @@ -0,0 +1,84 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clc86f_h__ +#define __gh100_clc86f_h__ + +typedef volatile struct Nvc86fControl_struct { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} Nvc86fControl, HopperAControlGPFifo; + +#define HOPPER_CHANNEL_GPFIFO_A (0x0000C86F) +#define NVC86F_SET_OBJECT (0x00000000) +#define NVC86F_SEM_ADDR_LO (0x0000005c) +#define NVC86F_SEM_ADDR_LO_OFFSET 31:2 +#define NVC86F_SEM_ADDR_HI (0x00000060) +#define NVC86F_SEM_ADDR_HI_OFFSET 24:0 +#define NVC86F_SEM_PAYLOAD_LO (0x00000064) +#define NVC86F_SEM_PAYLOAD_HI (0x00000068) +#define NVC86F_SEM_EXECUTE (0x0000006c) +#define NVC86F_SEM_EXECUTE_OPERATION 2:0 +#define NVC86F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001 +#define NVC86F_SEM_EXECUTE_RELEASE_WFI 20:20 +#define NVC86F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000 +#define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE 24:24 +#define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000 + +/* GPFIFO entry format */ +#define NVC86F_GP_ENTRY__SIZE 8 +#define NVC86F_GP_ENTRY0_FETCH 0:0 +#define NVC86F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVC86F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVC86F_GP_ENTRY0_GET 31:2 +#define NVC86F_GP_ENTRY0_OPERAND 31:0 +#define NVC86F_GP_ENTRY0_PB_EXTENDED_BASE_OPERAND 24:8 +#define NVC86F_GP_ENTRY1_GET_HI 7:0 +#define NVC86F_GP_ENTRY1_LEVEL 9:9 +#define NVC86F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVC86F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVC86F_GP_ENTRY1_LENGTH 30:10 +#define NVC86F_GP_ENTRY1_SYNC 31:31 +#define NVC86F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVC86F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVC86F_GP_ENTRY1_OPCODE 7:0 +#define NVC86F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVC86F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVC86F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVC86F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 +#define NVC86F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE 0x00000004 + +#endif // __gh100_clc86f_h__ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc86fsw.h b/userspace/sdks/nv525/nvidia/inc/class/clc86fsw.h new file mode 100644 index 0000000..dce4dfd --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc86fsw.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* This file is *not* auto-generated. */ + +#ifndef _clc86f_sw_h_ +#define _clc86f_sw_h_ + +#define NVC86F_NOTIFIERS_RC (0) +#define NVC86F_NOTIFIERS_REFCNT (1) +#define NVC86F_NOTIFIERS_NONSTALL (2) +#define NVC86F_NOTIFIERS_EVENTBUFFER (3) +#define NVC86F_NOTIFIERS_IDLECHANNEL (4) +#define NVC86F_NOTIFIERS_ENDCTX (5) +#define NVC86F_NOTIFIERS_SW (6) +#define NVC86F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVC86F_NOTIFIERS_REPLAYABLE_FAULT (8) +#define NVC86F_NOTIFIERS_MAXCOUNT (9) + +/* NvNotification[] fields and values */ +#define NVC86F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVC86F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _clc56f_sw_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc8b5.h b/userspace/sdks/nv525/nvidia/inc/class/clc8b5.h new file mode 100644 index 0000000..38fd8be --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc8b5.h @@ -0,0 +1,77 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clc8b5_h__ +#define __gh100_clc8b5_h__ +#define HOPPER_DMA_COPY_A (0x0000C8B5) +#define NVC8B5_SET_SEMAPHORE_A (0x00000240) +#define NVC8B5_SET_SEMAPHORE_A_UPPER 24:0 +#define NVC8B5_SET_SEMAPHORE_B (0x00000244) +#define NVC8B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC8B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC8B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC8B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC8B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC8B5_LAUNCH_DMA (0x00000300) +#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC8B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC8B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC8B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC8B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC8B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC8B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC8B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC8B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE 23:23 +#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_DISABLE_PLC 26:26 +#define NVC8B5_LAUNCH_DMA_DISABLE_PLC_TRUE (0x00000001) +#define NVC8B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC8B5_OFFSET_OUT_UPPER_UPPER 24:0 +#define NVC8B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC8B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC8B5_LINE_LENGTH_IN (0x00000418) +#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS (0x000006FC) +#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE 0:0 +#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_FALSE (0x00000000) +#define NVC8B5_SET_REMAP_CONST_A (0x00000700) +#define NVC8B5_SET_REMAP_CONST_B (0x00000704) +#define NVC8B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#endif // __gh100_clc8b5_h__ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc997.h b/userspace/sdks/nv525/nvidia/inc/class/clc997.h new file mode 100644 index 0000000..81607be --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc997.h @@ -0,0 +1,4481 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_ada_a_h_ +#define _cl_ada_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl ada_a */ + +#include "nvtypes.h" + +#define ADA_A 0xC997 + +#define NVC997_SET_OBJECT 0x0000 +#define NVC997_SET_OBJECT_CLASS_ID 15:0 +#define NVC997_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC997_NO_OPERATION 0x0100 +#define NVC997_NO_OPERATION_V 31:0 + +#define NVC997_SET_NOTIFY_A 0x0104 +#define NVC997_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC997_SET_NOTIFY_B 0x0108 +#define NVC997_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC997_NOTIFY 0x010c +#define NVC997_NOTIFY_TYPE 31:0 +#define NVC997_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC997_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC997_WAIT_FOR_IDLE 0x0110 +#define NVC997_WAIT_FOR_IDLE_V 31:0 + +#define NVC997_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC997_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC997_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC997_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC997_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC997_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC997_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC997_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC997_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC997_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC997_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC997_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC997_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC997_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC997_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC997_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC997_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC997_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC997_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC997_SEND_GO_IDLE 0x013c +#define NVC997_SEND_GO_IDLE_V 31:0 + +#define NVC997_PM_TRIGGER 0x0140 +#define NVC997_PM_TRIGGER_V 31:0 + +#define NVC997_PM_TRIGGER_WFI 0x0144 +#define NVC997_PM_TRIGGER_WFI_V 31:0 + +#define NVC997_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC997_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC997_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC997_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC997_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC997_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC997_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC997_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER 0x0158 +#define NVC997_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER_PAYLOAD_LOWER 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER 0x015c +#define NVC997_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD_UPPER 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_ADDRESS_LOWER 0x0160 +#define NVC997_SET_REPORT_SEMAPHORE_ADDRESS_LOWER_LOWER 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_ADDRESS_UPPER 0x0164 +#define NVC997_SET_REPORT_SEMAPHORE_ADDRESS_UPPER_UPPER 7:0 + +#define NVC997_REPORT_SEMAPHORE_EXECUTE 0x0168 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_OPERATION 1:0 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_OPERATION_RELEASE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_OPERATION_ACQUIRE 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_OPERATION_REPORT_ONLY 0x00000002 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_OPERATION_TRAP 0x00000003 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION 5:2 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC997_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE 6:6 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT 11:7 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_NONE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_SCG_CLOCKS 0x00000008 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS0 0x0000000A +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS1 0x0000000C +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS2 0x0000000E +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS3 0x00000010 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_TIMESTAMP 0x00000014 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE 14:13 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_SUB_REPORT 17:15 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE 19:19 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE 18:18 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE 20:20 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP 23:21 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_INC 0x00000003 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_AND 0x00000005 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_OR 0x00000006 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT 25:24 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64 27:27 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_FALSE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_TRUE 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE 29:28 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_NONE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 + +#define NVC997_LINE_LENGTH_IN 0x0180 +#define NVC997_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC997_LINE_COUNT 0x0184 +#define NVC997_LINE_COUNT_VALUE 31:0 + +#define NVC997_OFFSET_OUT_UPPER 0x0188 +#define NVC997_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC997_OFFSET_OUT 0x018c +#define NVC997_OFFSET_OUT_VALUE 31:0 + +#define NVC997_PITCH_OUT 0x0190 +#define NVC997_PITCH_OUT_VALUE 31:0 + +#define NVC997_SET_DST_BLOCK_SIZE 0x0194 +#define NVC997_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC997_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC997_SET_DST_WIDTH 0x0198 +#define NVC997_SET_DST_WIDTH_V 31:0 + +#define NVC997_SET_DST_HEIGHT 0x019c +#define NVC997_SET_DST_HEIGHT_V 31:0 + +#define NVC997_SET_DST_DEPTH 0x01a0 +#define NVC997_SET_DST_DEPTH_V 31:0 + +#define NVC997_SET_DST_LAYER 0x01a4 +#define NVC997_SET_DST_LAYER_V 31:0 + +#define NVC997_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC997_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC997_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC997_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC997_LAUNCH_DMA 0x01b0 +#define NVC997_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC997_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC997_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC997_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC997_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC997_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC997_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC997_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC997_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC997_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC997_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC997_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC997_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC997_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC997_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC997_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC997_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC997_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC997_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC997_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC997_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC997_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC997_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC997_LOAD_INLINE_DATA 0x01b4 +#define NVC997_LOAD_INLINE_DATA_V 31:0 + +#define NVC997_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC997_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC997_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC997_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC997_SET_MME_SWITCH_STATE 0x01ec +#define NVC997_SET_MME_SWITCH_STATE_VALID 0:0 +#define NVC997_SET_MME_SWITCH_STATE_VALID_FALSE 0x00000000 +#define NVC997_SET_MME_SWITCH_STATE_VALID_TRUE 0x00000001 +#define NVC997_SET_MME_SWITCH_STATE_SAVE_MACRO 11:4 +#define NVC997_SET_MME_SWITCH_STATE_RESTORE_MACRO 19:12 + +#define NVC997_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC997_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC997_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC997_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC997_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC997_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC997_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC997_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC997_RUN_DS_NOW 0x0200 +#define NVC997_RUN_DS_NOW_V 31:0 + +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC997_SET_GS_MODE 0x0208 +#define NVC997_SET_GS_MODE_TYPE 0:0 +#define NVC997_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVC997_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVC997_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC997_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC997_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC997_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC997_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC997_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_GS_DM_FIFO 0x0214 +#define NVC997_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC997_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC997_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC997_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC997_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC997_INVALIDATE_SHADER_CACHES 0x021c +#define NVC997_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC997_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC997_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC997_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC997_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC997_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC997_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC997_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC997_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC997_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC997_SET_INSTANCE_COUNT 0x0220 +#define NVC997_SET_INSTANCE_COUNT_V 31:0 + +#define NVC997_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVC997_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVC997_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC997_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVC997_SET_MME_VERSION 0x0234 +#define NVC997_SET_MME_VERSION_MAJOR 7:0 + +#define NVC997_SET_INDEX_BUFFER_SIZE_A 0x0238 +#define NVC997_SET_INDEX_BUFFER_SIZE_A_UPPER 7:0 + +#define NVC997_SET_INDEX_BUFFER_SIZE_B 0x023c +#define NVC997_SET_INDEX_BUFFER_SIZE_B_LOWER 31:0 + +#define NVC997_SET_ROOT_TABLE_VISIBILITY(i) (0x0240+(i)*4) +#define NVC997_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP0_ENABLE 1:0 +#define NVC997_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP1_ENABLE 5:4 +#define NVC997_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP2_ENABLE 9:8 +#define NVC997_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP3_ENABLE 13:12 +#define NVC997_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP4_ENABLE 17:16 + +#define NVC997_SET_DRAW_CONTROL_A 0x0260 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY 3:0 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_POINTS 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_LINES 0x00000001 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_QUADS 0x00000007 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_PATCH 0x0000000E +#define NVC997_SET_DRAW_CONTROL_A_PRIMITIVE_ID 4:4 +#define NVC997_SET_DRAW_CONTROL_A_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ID 6:5 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ID_FIRST 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC997_SET_DRAW_CONTROL_A_SPLIT_MODE 8:7 +#define NVC997_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC997_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC997_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE 9:9 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 +#define NVC997_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX 10:10 +#define NVC997_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_FALSE 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_TRUE 0x00000001 +#define NVC997_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX 11:11 +#define NVC997_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_FALSE 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_TRUE 0x00000001 + +#define NVC997_SET_DRAW_CONTROL_B 0x0264 +#define NVC997_SET_DRAW_CONTROL_B_INSTANCE_COUNT 31:0 + +#define NVC997_DRAW_INDEX_BUFFER_BEGIN_END_A 0x0268 +#define NVC997_DRAW_INDEX_BUFFER_BEGIN_END_A_FIRST 31:0 + +#define NVC997_DRAW_INDEX_BUFFER_BEGIN_END_B 0x026c +#define NVC997_DRAW_INDEX_BUFFER_BEGIN_END_B_COUNT 31:0 + +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_A 0x0270 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_A_START 31:0 + +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_B 0x0274 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_B_COUNT 31:0 + +#define NVC997_INVALIDATE_RASTER_CACHE_NO_WFI 0x027c +#define NVC997_INVALIDATE_RASTER_CACHE_NO_WFI_V 0:0 + +#define NVC997_SET_COLOR_RENDER_TO_ZETA_SURFACE 0x02b8 +#define NVC997_SET_COLOR_RENDER_TO_ZETA_SURFACE_V 0:0 +#define NVC997_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_FALSE 0x00000000 +#define NVC997_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_TRUE 0x00000001 + +#define NVC997_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION 0x02bc +#define NVC997_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V 0:0 +#define NVC997_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_FALSE 0x00000000 +#define NVC997_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_TRUE 0x00000001 + +#define NVC997_INCREMENT_SYNC_POINT 0x02c8 +#define NVC997_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC997_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC997_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC997_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC997_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC997_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC997_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC997_SET_ROOT_TABLE_PREFETCH 0x02d0 +#define NVC997_SET_ROOT_TABLE_PREFETCH_STAGE_ENABLES 5:0 + +#define NVC997_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC997_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC997_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC997_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVC997_DECOMPRESS_SURFACE 0x02e0 +#define NVC997_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC997_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC997_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC997_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC997_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC997_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC997_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC997_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC997_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC997_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC997_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC997_SET_ZCULL_SUBREGION 0x02e8 +#define NVC997_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC997_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC997_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC997_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC997_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC997_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC997_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC997_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC997_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC997_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC997_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC997_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC997_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC997_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC997_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC997_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC997_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC997_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC997_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC997_DRAW_ZERO_INDEX 0x0304 +#define NVC997_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC997_SET_L1_CONFIGURATION 0x0308 +#define NVC997_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC997_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC997_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC997_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC997_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC997_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC997_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC997_SET_SPA_VERSION 0x0310 +#define NVC997_SET_SPA_VERSION_MINOR 7:0 +#define NVC997_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC997_SET_TIMESLICE_BATCH_LIMIT 0x0314 +#define NVC997_SET_TIMESLICE_BATCH_LIMIT_BATCH_LIMIT 15:0 + +#define NVC997_SET_SNAP_GRID_LINE 0x0318 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC997_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC997_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC997_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC997_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC997_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC997_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC997_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC997_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC997_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC997_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC997_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC997_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC997_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC997_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC997_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC997_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC997_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC997_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC997_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC997_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC997_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC997_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC997_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC997_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC997_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC997_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC997_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC997_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC997_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC997_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC997_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC997_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC997_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC997_RESERVED_TG07 0x033c +#define NVC997_RESERVED_TG07_V 0:0 + +#define NVC997_RESERVED_TG08 0x0340 +#define NVC997_RESERVED_TG08_V 0:0 + +#define NVC997_RESERVED_TG09 0x0344 +#define NVC997_RESERVED_TG09_V 0:0 + +#define NVC997_RESERVED_TG10 0x0348 +#define NVC997_RESERVED_TG10_V 0:0 + +#define NVC997_RESERVED_TG11 0x034c +#define NVC997_RESERVED_TG11_V 0:0 + +#define NVC997_RESERVED_TG12 0x0350 +#define NVC997_RESERVED_TG12_V 0:0 + +#define NVC997_RESERVED_TG13 0x0354 +#define NVC997_RESERVED_TG13_V 0:0 + +#define NVC997_RESERVED_TG14 0x0358 +#define NVC997_RESERVED_TG14_V 0:0 + +#define NVC997_RESERVED_TG15 0x035c +#define NVC997_RESERVED_TG15_V 0:0 + +#define NVC997_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC997_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC997_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC997_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC997_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC997_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC997_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC997_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC997_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC997_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC997_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC997_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC997_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC997_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC997_SET_RASTER_ENABLE 0x037c +#define NVC997_SET_RASTER_ENABLE_V 0:0 +#define NVC997_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC997_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC997_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC997_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC997_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC997_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC997_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC997_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC997_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC997_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC997_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVC997_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVC997_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVC997_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVC997_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVC997_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVC997_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVC997_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVC997_SET_Z_ROP_SLICE_MAP 0x0500 +#define NVC997_SET_Z_ROP_SLICE_MAP_VIRTUAL_ADDRESS_MASK 31:0 + +#define NVC997_SET_ROOT_TABLE_SELECTOR 0x0504 +#define NVC997_SET_ROOT_TABLE_SELECTOR_ROOT_TABLE 2:0 +#define NVC997_SET_ROOT_TABLE_SELECTOR_OFFSET 15:8 + +#define NVC997_LOAD_ROOT_TABLE 0x0508 +#define NVC997_LOAD_ROOT_TABLE_V 31:0 + +#define NVC997_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVC997_SET_MME_MEM_ADDRESS_A_UPPER 16:0 + +#define NVC997_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVC997_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVC997_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVC997_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVC997_MME_DMA_READ 0x055c +#define NVC997_MME_DMA_READ_LENGTH 31:0 + +#define NVC997_MME_DMA_READ_FIFOED 0x0560 +#define NVC997_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVC997_MME_DMA_WRITE 0x0564 +#define NVC997_MME_DMA_WRITE_LENGTH 31:0 + +#define NVC997_MME_DMA_REDUCTION 0x0568 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVC997_MME_DMA_SYSMEMBAR 0x056c +#define NVC997_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVC997_MME_DMA_SYNC 0x0570 +#define NVC997_MME_DMA_SYNC_VALUE 31:0 + +#define NVC997_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NVC997_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NVC997_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NVC997_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NVC997_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NVC997_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NVC997_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NVC997_SET_VERTEX_STREAM_SIZE_A(j) (0x0600+(j)*8) +#define NVC997_SET_VERTEX_STREAM_SIZE_A_UPPER 7:0 + +#define NVC997_SET_VERTEX_STREAM_SIZE_B(j) (0x0604+(j)*8) +#define NVC997_SET_VERTEX_STREAM_SIZE_B_LOWER 31:0 + +#define NVC997_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC997_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC997_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC997_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC997_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC997_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC997_SET_RASTER_INPUT 0x0740 +#define NVC997_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC997_SET_STREAM_OUTPUT 0x0744 +#define NVC997_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC997_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC997_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC997_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC997_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC997_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC997_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC997_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC997_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC997_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC997_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC997_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC997_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC997_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC997_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC997_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC997_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC997_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC997_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC997_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC997_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC997_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC997_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC997_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC997_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC997_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVC997_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC997_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC997_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC997_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC997_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC997_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC997_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC997_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC997_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC997_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC997_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC997_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC997_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC997_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC997_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC997_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC997_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC997_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC997_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC997_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC997_SET_ZCULL_STORAGE_B 0x07ec +#define NVC997_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC997_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC997_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC997_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC997_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC997_SET_ZT_READ_ONLY 0x07f8 +#define NVC997_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC997_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC997_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC997_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC997_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC997_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC997_THROTTLE_SM 0x07fc +#define NVC997_THROTTLE_SM_MULTIPLY_ADD 0:0 +#define NVC997_THROTTLE_SM_MULTIPLY_ADD_FALSE 0x00000000 +#define NVC997_THROTTLE_SM_MULTIPLY_ADD_TRUE 0x00000001 + +#define NVC997_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC997_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC997_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC997_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC997_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC997_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC997_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC997_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC997_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC997_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC997_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC997_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC997_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC997_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC997_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC997_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC997_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC997_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC997_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC997_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC997_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC997_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC997_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC997_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC997_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC997_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC997_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC997_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC997_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC997_SET_COLOR_TARGET_C_ROP_SLICE_MAP(j) (0x0824+(j)*64) +#define NVC997_SET_COLOR_TARGET_C_ROP_SLICE_MAP_VIRTUAL_ADDRESS_MASK 31:0 + +#define NVC997_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC997_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC997_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC997_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC997_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC997_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC997_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC997_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC997_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC997_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC997_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC997_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC997_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC997_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC997_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC997_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC997_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC997_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC997_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC997_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC997_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC997_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC997_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC997_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC997_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC997_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC997_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC997_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC997_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC997_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC997_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC997_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC997_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC997_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC997_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC997_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC997_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC997_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC997_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC997_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC997_SET_STATISTICS_COUNTER 0x0d68 +#define NVC997_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC997_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC997_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC997_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC997_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC997_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC997_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC997_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC997_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC997_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC997_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC997_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC997_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC997_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC997_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC997_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC997_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVC997_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC997_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC997_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC997_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC997_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC997_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC997_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC997_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC997_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC997_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC997_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC997_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC997_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC997_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC997_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC997_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC997_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC997_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC997_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC997_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC997_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC997_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC997_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC997_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC997_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC997_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC997_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC997_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC997_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC997_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC997_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC997_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC997_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC997_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC997_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC997_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC997_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC997_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC997_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC997_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC997_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC997_SET_POLY_SMOOTH 0x0db4 +#define NVC997_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC997_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC997_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC997_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC997_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC997_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC997_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC997_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC997_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC997_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_PATCH 0x0dcc +#define NVC997_SET_PATCH_SIZE 7:0 + +#define NVC997_SET_ITERATED_BLEND 0x0dd0 +#define NVC997_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC997_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC997_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC997_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC997_SET_ZCULL_CRITERION 0x0dd8 +#define NVC997_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC997_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC997_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC997_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC997_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC997_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC997_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC997_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC997_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC997_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC997_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 +#define NVC997_PIXEL_SHADER_BARRIER_BARRIER_LOCATION 1:1 +#define NVC997_PIXEL_SHADER_BARRIER_BARRIER_LOCATION_BLOCK_BEFORE_PS 0x00000000 +#define NVC997_PIXEL_SHADER_BARRIER_BARRIER_LOCATION_BLOCK_BEFORE_PS_AND_ZTEST 0x00000001 + +#define NVC997_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC997_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC997_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC997_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC997_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC997_MME_DMA_WRITE_METHOD_BARRIER 0x0dec +#define NVC997_MME_DMA_WRITE_METHOD_BARRIER_V 0:0 + +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC997_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC997_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC997_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC997_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC997_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC997_SET_SCISSOR_ENABLE_V 0:0 +#define NVC997_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC997_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC997_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC997_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC997_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC997_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC997_SET_VPC_PERF_KNOB 0x0f14 +#define NVC997_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC997_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC997_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC997_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC997_PM_LOCAL_TRIGGER 0x0f18 +#define NVC997_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC997_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC997_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC997_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC997_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC997_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC997_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC997_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC997_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC997_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC997_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC997_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC997_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC997_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC997_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC997_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC997_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC997_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC997_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC997_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC997_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC997_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC997_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC997_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC997_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC997_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC997_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC997_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC997_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC997_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC997_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC997_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC997_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC997_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC997_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC997_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC997_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC997_SET_SAMPLE_MASK 0x0fa4 +#define NVC997_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC997_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC997_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC997_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC997_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC997_SET_CT_MRT_ENABLE 0x0fac +#define NVC997_SET_CT_MRT_ENABLE_V 0:0 +#define NVC997_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC997_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC997_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC997_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC997_SET_TIR 0x0fb4 +#define NVC997_SET_TIR_MODE 1:0 +#define NVC997_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC997_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC997_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC997_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC997_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC997_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC997_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC997_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC997_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC997_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC997_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC997_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC997_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC997_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC997_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC997_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC997_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC997_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC997_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC997_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_TIR_MODULATION 0x0fd4 +#define NVC997_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC997_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC997_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC997_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC997_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC997_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC997_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC997_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC997_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC997_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC997_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC997_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC997_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC997_SET_ZT_A 0x0fe0 +#define NVC997_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_ZT_B 0x0fe4 +#define NVC997_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_ZT_FORMAT 0x0fe8 +#define NVC997_SET_ZT_FORMAT_V 4:0 +#define NVC997_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC997_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC997_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC997_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC997_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC997_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC997_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC997_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC997_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC997_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC997_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC997_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC997_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC997_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC997_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC997_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC997_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC997_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC997_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC997_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC997_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC997_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC997_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC997_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC997_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC997_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC997_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC997_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC997_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC997_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC997_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC997_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC997_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC997_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC997_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC997_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC997_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC997_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC997_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC997_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC997_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC997_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC997_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC997_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC997_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC997_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD02 0x102c +#define NVC997_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC997_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC997_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC997_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC997_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC997_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC997_SET_SPARE_NOOP01 0x1044 +#define NVC997_SET_SPARE_NOOP01_V 31:0 + +#define NVC997_SET_SPARE_NOOP02 0x1048 +#define NVC997_SET_SPARE_NOOP02_V 31:0 + +#define NVC997_SET_SPARE_NOOP03 0x104c +#define NVC997_SET_SPARE_NOOP03_V 31:0 + +#define NVC997_SET_SPARE_NOOP04 0x1050 +#define NVC997_SET_SPARE_NOOP04_V 31:0 + +#define NVC997_SET_SPARE_NOOP05 0x1054 +#define NVC997_SET_SPARE_NOOP05_V 31:0 + +#define NVC997_SET_SPARE_NOOP06 0x1058 +#define NVC997_SET_SPARE_NOOP06_V 31:0 + +#define NVC997_SET_SPARE_NOOP07 0x105c +#define NVC997_SET_SPARE_NOOP07_V 31:0 + +#define NVC997_SET_SPARE_NOOP08 0x1060 +#define NVC997_SET_SPARE_NOOP08_V 31:0 + +#define NVC997_SET_SPARE_NOOP09 0x1064 +#define NVC997_SET_SPARE_NOOP09_V 31:0 + +#define NVC997_SET_SPARE_NOOP10 0x1068 +#define NVC997_SET_SPARE_NOOP10_V 31:0 + +#define NVC997_SET_SPARE_NOOP11 0x106c +#define NVC997_SET_SPARE_NOOP11_V 31:0 + +#define NVC997_SET_SPARE_NOOP12 0x1070 +#define NVC997_SET_SPARE_NOOP12_V 31:0 + +#define NVC997_SET_SPARE_NOOP13 0x1074 +#define NVC997_SET_SPARE_NOOP13_V 31:0 + +#define NVC997_SET_SPARE_NOOP14 0x1078 +#define NVC997_SET_SPARE_NOOP14_V 31:0 + +#define NVC997_SET_SPARE_NOOP15 0x107c +#define NVC997_SET_SPARE_NOOP15_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC997_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC997_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC997_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC997_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC997_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC997_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC997_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC997_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC997_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC997_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC997_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC997_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC997_UNBIND_ALL 0x10f4 +#define NVC997_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC997_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC997_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC997_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC997_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC997_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC997_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC997_NO_OPERATION_DATA_HI 0x110c +#define NVC997_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC997_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC997_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC997_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC997_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC997_PM_TRIGGER_END 0x1114 +#define NVC997_PM_TRIGGER_END_V 31:0 + +#define NVC997_SET_VERTEX_ID_BASE 0x1118 +#define NVC997_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC997_SET_STENCIL_COMPRESSION 0x111c +#define NVC997_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC997_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC997_SET_TIR_CONTROL 0x1130 +#define NVC997_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC997_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC997_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC997_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC997_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC997_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC997_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC997_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC997_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 +#define NVC997_SET_TIR_CONTROL_REDUCTION_MODE 2:2 +#define NVC997_SET_TIR_CONTROL_REDUCTION_MODE_AFFINITY_MAP 0x00000000 +#define NVC997_SET_TIR_CONTROL_REDUCTION_MODE_TRUNCATION 0x00000001 + +#define NVC997_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC997_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC997_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC997_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC997_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC997_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC997_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC997_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC997_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC997_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC997_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC997_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC997_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC997_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC997_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC997_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC997_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC997_FLUSH_PENDING_WRITES 0x1144 +#define NVC997_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC997_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC997_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC997_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC997_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC997_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC997_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC997_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC997_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC997_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC997_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC997_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC997_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC997_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC997_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC997_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC997_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC997_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC997_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC997_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC997_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC997_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC997_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_SCREEN_STATE_MASK 0x1204 +#define NVC997_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC997_SET_ZT_SPARSE 0x1208 +#define NVC997_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC997_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC997_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC997_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_SET_CT_SELECT 0x121c +#define NVC997_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC997_SET_CT_SELECT_TARGET0 6:4 +#define NVC997_SET_CT_SELECT_TARGET1 9:7 +#define NVC997_SET_CT_SELECT_TARGET2 12:10 +#define NVC997_SET_CT_SELECT_TARGET3 15:13 +#define NVC997_SET_CT_SELECT_TARGET4 18:16 +#define NVC997_SET_CT_SELECT_TARGET5 21:19 +#define NVC997_SET_CT_SELECT_TARGET6 24:22 +#define NVC997_SET_CT_SELECT_TARGET7 27:25 + +#define NVC997_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC997_SET_ZT_SIZE_A 0x1228 +#define NVC997_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC997_SET_ZT_SIZE_B 0x122c +#define NVC997_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC997_SET_ZT_SIZE_C 0x1230 +#define NVC997_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC997_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC997_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC997_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC997_SET_SAMPLER_BINDING 0x1234 +#define NVC997_SET_SAMPLER_BINDING_V 0:0 +#define NVC997_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC997_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC997_DRAW_AUTO 0x123c +#define NVC997_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC997_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC997_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC997_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC997_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC997_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC997_SET_BACK_END_COPY_A 0x1264 +#define NVC997_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC997_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC997_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC997_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC997_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BACK_END_COPY_B 0x1268 +#define NVC997_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC997_SET_BACK_END_COPY_C 0x126c +#define NVC997_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC997_SET_BACK_END_COPY_D 0x1270 +#define NVC997_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC997_SET_BACK_END_COPY_E 0x1274 +#define NVC997_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC997_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC997_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVC997_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC997_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC997_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC997_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC997_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC997_CLEAR_ZCULL_REGION 0x12c8 +#define NVC997_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC997_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC997_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC997_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC997_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC997_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC997_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC997_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC997_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC997_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC997_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC997_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC997_SET_DEPTH_TEST 0x12cc +#define NVC997_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC997_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_FILL_MODE 0x12d0 +#define NVC997_SET_FILL_MODE_V 31:0 +#define NVC997_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC997_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC997_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC997_SET_SHADE_MODE 0x12d4 +#define NVC997_SET_SHADE_MODE_V 31:0 +#define NVC997_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC997_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC997_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC997_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC997_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC997_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC997_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC997_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC997_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC997_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC997_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC997_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_DEPTH_WRITE 0x12e8 +#define NVC997_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC997_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_ALPHA_TEST 0x12ec +#define NVC997_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC997_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC997_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC997_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC997_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC997_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC997_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC997_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC997_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC997_D3D_SET_CULL_MODE 0x1308 +#define NVC997_D3D_SET_CULL_MODE_V 31:0 +#define NVC997_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC997_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC997_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC997_SET_DEPTH_FUNC 0x130c +#define NVC997_SET_DEPTH_FUNC_V 31:0 +#define NVC997_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC997_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC997_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC997_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC997_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC997_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC997_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC997_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC997_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC997_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC997_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC997_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC997_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC997_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC997_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC997_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC997_SET_ALPHA_REF 0x1310 +#define NVC997_SET_ALPHA_REF_V 31:0 + +#define NVC997_SET_ALPHA_FUNC 0x1314 +#define NVC997_SET_ALPHA_FUNC_V 31:0 +#define NVC997_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC997_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC997_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC997_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC997_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC997_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC997_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC997_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC997_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC997_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC997_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC997_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC997_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC997_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC997_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC997_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC997_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC997_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC997_SET_BLEND_CONST_RED 0x131c +#define NVC997_SET_BLEND_CONST_RED_V 31:0 + +#define NVC997_SET_BLEND_CONST_GREEN 0x1320 +#define NVC997_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC997_SET_BLEND_CONST_BLUE 0x1324 +#define NVC997_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC997_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC997_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC997_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC997_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC997_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC997_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC997_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC997_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC997_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC997_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BLEND_COLOR_OP 0x1340 +#define NVC997_SET_BLEND_COLOR_OP_V 31:0 +#define NVC997_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC997_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC997_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC997_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC997_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC997_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC997_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC997_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC997_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC997_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_BLEND_ALPHA_OP 0x134c +#define NVC997_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC997_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC997_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC997_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC997_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC997_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC997_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC997_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC997_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC997_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC997_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC997_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC997_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC997_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC997_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC997_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BLEND(i) (0x1360+(i)*4) +#define NVC997_SET_BLEND_ENABLE 0:0 +#define NVC997_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_STENCIL_TEST 0x1380 +#define NVC997_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC997_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_STENCIL_OP_FAIL 0x1384 +#define NVC997_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC997_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC997_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC997_SET_STENCIL_OP_ZPASS 0x138c +#define NVC997_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC997_SET_STENCIL_FUNC 0x1390 +#define NVC997_SET_STENCIL_FUNC_V 31:0 +#define NVC997_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC997_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC997_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC997_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC997_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC997_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC997_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC997_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC997_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC997_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC997_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC997_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC997_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC997_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC997_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC997_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC997_SET_STENCIL_FUNC_REF 0x1394 +#define NVC997_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC997_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC997_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC997_SET_STENCIL_MASK 0x139c +#define NVC997_SET_STENCIL_MASK_V 7:0 + +#define NVC997_SET_DRAW_AUTO_START 0x13a4 +#define NVC997_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC997_SET_PS_SATURATE 0x13a8 +#define NVC997_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC997_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC997_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC997_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC997_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC997_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC997_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC997_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC997_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC997_SET_WINDOW_ORIGIN 0x13ac +#define NVC997_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC997_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC997_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC997_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC997_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC997_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC997_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC997_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC997_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC997_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC997_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC997_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC997_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC997_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC997_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC997_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC997_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC997_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC997_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC997_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC997_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC997_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC997_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC997_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC997_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC997_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC997_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC997_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC997_STORE_ZCULL 0x1464 +#define NVC997_STORE_ZCULL_V 0:0 + +#define NVC997_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC997_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC997_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC997_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC997_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC997_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC997_LOAD_ZCULL 0x1500 +#define NVC997_LOAD_ZCULL_V 0:0 + +#define NVC997_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC997_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC997_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC997_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC997_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC997_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC997_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC997_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC997_SET_USER_CLIP_ENABLE 0x1510 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC997_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC997_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC997_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_POINT_SIZE 0x1518 +#define NVC997_SET_POINT_SIZE_V 31:0 + +#define NVC997_SET_ZCULL_STATS 0x151c +#define NVC997_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC997_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_POINT_SPRITE 0x1520 +#define NVC997_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC997_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC997_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC997_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC997_CLEAR_REPORT_VALUE 0x1530 +#define NVC997_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC997_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC997_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC997_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC997_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC997_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC997_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVC997_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC997_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC997_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_ZT_SELECT 0x1538 +#define NVC997_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC997_SET_RENDER_ENABLE_A 0x1550 +#define NVC997_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_RENDER_ENABLE_B 0x1554 +#define NVC997_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_RENDER_ENABLE_C 0x1558 +#define NVC997_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC997_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC997_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC997_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC997_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC997_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC997_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC997_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC997_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC997_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC997_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC997_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC997_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC997_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC997_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC997_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC997_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_TEX_HEADER_POOL_C 0x157c +#define NVC997_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC997_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC997_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC997_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC997_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC997_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC997_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC997_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC997_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC997_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC997_SET_SRGB_WRITE 0x15b8 +#define NVC997_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC997_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_DEPTH_BIAS 0x15bc +#define NVC997_SET_DEPTH_BIAS_V 31:0 + +#define NVC997_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC997_SET_RT_LAYER 0x15cc +#define NVC997_SET_RT_LAYER_V 15:0 +#define NVC997_SET_RT_LAYER_CONTROL 16:16 +#define NVC997_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC997_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC997_SET_ANTI_ALIAS 0x15d0 +#define NVC997_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC997_SET_EDGE_FLAG 0x15e4 +#define NVC997_SET_EDGE_FLAG_V 0:0 +#define NVC997_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC997_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC997_DRAW_INLINE_INDEX 0x15e8 +#define NVC997_DRAW_INLINE_INDEX_V 31:0 + +#define NVC997_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC997_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC997_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC997_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC997_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC997_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC997_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC997_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC997_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC997_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC997_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC997_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC997_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC997_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC997_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC997_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC997_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC997_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC997_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC997_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC997_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC997_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC997_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC997_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC997_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC997_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC997_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC997_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC997_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC997_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC997_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC997_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC997_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC997_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC997_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC997_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC997_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC997_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC997_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC997_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC997_END 0x1614 +#define NVC997_END_V 0:0 + +#define NVC997_BEGIN 0x1618 +#define NVC997_BEGIN_OP 15:0 +#define NVC997_BEGIN_OP_POINTS 0x00000000 +#define NVC997_BEGIN_OP_LINES 0x00000001 +#define NVC997_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC997_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC997_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC997_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC997_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC997_BEGIN_OP_QUADS 0x00000007 +#define NVC997_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC997_BEGIN_OP_POLYGON 0x00000009 +#define NVC997_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC997_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC997_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_BEGIN_OP_PATCH 0x0000000E +#define NVC997_BEGIN_PRIMITIVE_ID 24:24 +#define NVC997_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC997_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC997_BEGIN_INSTANCE_ID 27:26 +#define NVC997_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC997_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC997_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC997_BEGIN_SPLIT_MODE 30:29 +#define NVC997_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC997_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC997_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC997_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC997_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVC997_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC997_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_VERTEX_ID_COPY 0x161c +#define NVC997_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC997_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC997_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC997_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC997_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC997_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC997_LOAD_PRIMITIVE_ID 0x1624 +#define NVC997_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC997_SET_SHADER_BASED_CULL 0x162c +#define NVC997_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC997_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC997_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC997_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_CLASS_VERSION 0x1638 +#define NVC997_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC997_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC997_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC997_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC997_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC997_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC997_SET_DA_OUTPUT 0x164c +#define NVC997_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC997_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC997_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC997_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC997_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_POINT_CENTER_MODE 0x165c +#define NVC997_SET_POINT_CENTER_MODE_V 31:0 +#define NVC997_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC997_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC997_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC997_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC997_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC997_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC997_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC997_SET_LINE_STIPPLE 0x166c +#define NVC997_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC997_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC997_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC997_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC997_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC997_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC997_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC997_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC997_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC997_SET_PROVOKING_VERTEX 0x1684 +#define NVC997_SET_PROVOKING_VERTEX_V 0:0 +#define NVC997_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC997_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC997_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC997_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC997_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_POLYGON_STIPPLE 0x168c +#define NVC997_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC997_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_SHADER_CONTROL 0x1690 +#define NVC997_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC997_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC997_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC997_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC997_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC997_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC997_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC997_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC997_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC997_CHECK_CLASS_VERSION 0x16a0 +#define NVC997_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC997_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC997_SET_SPH_VERSION 0x16a4 +#define NVC997_SET_SPH_VERSION_CURRENT 15:0 +#define NVC997_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC997_CHECK_SPH_VERSION 0x16a8 +#define NVC997_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC997_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC997_SET_SCG_GRAPHICS_PRIORITY 0x16bc +#define NVC997_SET_SCG_GRAPHICS_PRIORITY_PRIORITY 5:0 + +#define NVC997_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS(i) (0x16c0+(i)*4) +#define NVC997_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC997_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC997_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC997_SET_AAM_VERSION 0x1790 +#define NVC997_SET_AAM_VERSION_CURRENT 15:0 +#define NVC997_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC997_CHECK_AAM_VERSION 0x1794 +#define NVC997_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC997_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC997_SET_ZT_LAYER 0x179c +#define NVC997_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC997_SET_INDEX_BUFFER_A 0x17c8 +#define NVC997_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC997_SET_INDEX_BUFFER_B 0x17cc +#define NVC997_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC997_SET_INDEX_BUFFER_E 0x17d8 +#define NVC997_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC997_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC997_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC997_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC997_SET_INDEX_BUFFER_F 0x17dc +#define NVC997_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC997_DRAW_INDEX_BUFFER 0x17e0 +#define NVC997_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC997_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC997_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC997_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC997_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC997_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC997_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC997_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC997_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC997_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC997_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC997_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC997_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC997_OGL_SET_CULL 0x1918 +#define NVC997_OGL_SET_CULL_ENABLE 0:0 +#define NVC997_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC997_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC997_OGL_SET_FRONT_FACE 0x191c +#define NVC997_OGL_SET_FRONT_FACE_V 31:0 +#define NVC997_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC997_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC997_OGL_SET_CULL_FACE 0x1920 +#define NVC997_OGL_SET_CULL_FACE_V 31:0 +#define NVC997_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC997_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC997_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC997_SET_VIEWPORT_PIXEL 0x1924 +#define NVC997_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC997_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC997_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC997_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC997_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC997_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC997_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE 17:16 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_USE_FIELD_MIN_Z_ZERO_MAX_Z_ONE 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MIN_Z_MAX_Z 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_ZERO_ONE 0x00000002 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MINUS_INF_PLUS_INF 0x00000003 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC997_SET_USER_CLIP_OP 0x1940 +#define NVC997_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC997_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC997_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC997_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC997_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC997_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC997_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC997_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC997_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC997_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC997_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC997_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC997_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC997_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC997_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC997_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC997_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC997_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC997_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC997_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC997_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC997_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC997_INVALIDATE_ZCULL 0x1958 +#define NVC997_INVALIDATE_ZCULL_V 31:0 +#define NVC997_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC997_SET_ZCULL 0x1968 +#define NVC997_SET_ZCULL_Z_ENABLE 0:0 +#define NVC997_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC997_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_ZCULL_BOUNDS 0x196c +#define NVC997_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC997_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC997_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC997_ZCULL_SYNC 0x1978 +#define NVC997_ZCULL_SYNC_V 31:0 + +#define NVC997_SET_CLIP_ID_TEST 0x197c +#define NVC997_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC997_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC997_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC997_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC997_SET_CLIP_ID 0x1984 +#define NVC997_SET_CLIP_ID_V 31:0 + +#define NVC997_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC997_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC997_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC997_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC997_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC997_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC997_SET_LOGIC_OP 0x19c4 +#define NVC997_SET_LOGIC_OP_ENABLE 0:0 +#define NVC997_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC997_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC997_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC997_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC997_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC997_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC997_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC997_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC997_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC997_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC997_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC997_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC997_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC997_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC997_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC997_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC997_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC997_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC997_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC997_SET_Z_COMPRESSION 0x19cc +#define NVC997_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC997_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC997_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC997_CLEAR_SURFACE 0x19d0 +#define NVC997_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC997_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC997_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC997_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC997_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC997_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC997_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC997_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC997_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC997_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC997_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC997_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC997_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC997_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC997_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC997_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC997_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC997_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC997_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC997_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC997_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC997_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC997_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC997_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC997_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC997_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC997_PIPE_NOP 0x1a2c +#define NVC997_PIPE_NOP_V 31:0 + +#define NVC997_SET_SPARE00 0x1a30 +#define NVC997_SET_SPARE00_V 31:0 + +#define NVC997_SET_SPARE01 0x1a34 +#define NVC997_SET_SPARE01_V 31:0 + +#define NVC997_SET_SPARE02 0x1a38 +#define NVC997_SET_SPARE02_V 31:0 + +#define NVC997_SET_SPARE03 0x1a3c +#define NVC997_SET_SPARE03_V 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC997_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC997_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC997_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC997_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC997_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC997_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC997_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC997_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC997_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC997_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC997_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC997_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_TIMESTAMP 0x00000014 +#define NVC997_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC997_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC997_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC997_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC997_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC997_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC997_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC997_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC997_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC997_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC997_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC997_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC997_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC997_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC997_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC997_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC997_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC997_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC997_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC997_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC997_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC997_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC997_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC997_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC997_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC997_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC997_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC997_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC997_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC997_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC997_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC997_SET_PIPELINE_RESERVED_B(j) (0x2004+(j)*64) +#define NVC997_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVC997_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC997_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC997_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC997_SET_PIPELINE_REGISTER_COUNT_V 8:0 + +#define NVC997_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC997_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC997_SET_PIPELINE_PROGRAM_ADDRESS_A(j) (0x2014+(j)*64) +#define NVC997_SET_PIPELINE_PROGRAM_ADDRESS_A_UPPER 7:0 + +#define NVC997_SET_PIPELINE_PROGRAM_ADDRESS_B(j) (0x2018+(j)*64) +#define NVC997_SET_PIPELINE_PROGRAM_ADDRESS_B_LOWER 31:0 + +#define NVC997_SET_PIPELINE_PROGRAM_PREFETCH(j) (0x201c+(j)*64) +#define NVC997_SET_PIPELINE_PROGRAM_PREFETCH_SIZE_IN_BLOCKS 6:0 + +#define NVC997_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC997_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC997_SET_FALCON00 0x2300 +#define NVC997_SET_FALCON00_V 31:0 + +#define NVC997_SET_FALCON01 0x2304 +#define NVC997_SET_FALCON01_V 31:0 + +#define NVC997_SET_FALCON02 0x2308 +#define NVC997_SET_FALCON02_V 31:0 + +#define NVC997_SET_FALCON03 0x230c +#define NVC997_SET_FALCON03_V 31:0 + +#define NVC997_SET_FALCON04 0x2310 +#define NVC997_SET_FALCON04_V 31:0 + +#define NVC997_SET_FALCON05 0x2314 +#define NVC997_SET_FALCON05_V 31:0 + +#define NVC997_SET_FALCON06 0x2318 +#define NVC997_SET_FALCON06_V 31:0 + +#define NVC997_SET_FALCON07 0x231c +#define NVC997_SET_FALCON07_V 31:0 + +#define NVC997_SET_FALCON08 0x2320 +#define NVC997_SET_FALCON08_V 31:0 + +#define NVC997_SET_FALCON09 0x2324 +#define NVC997_SET_FALCON09_V 31:0 + +#define NVC997_SET_FALCON10 0x2328 +#define NVC997_SET_FALCON10_V 31:0 + +#define NVC997_SET_FALCON11 0x232c +#define NVC997_SET_FALCON11_V 31:0 + +#define NVC997_SET_FALCON12 0x2330 +#define NVC997_SET_FALCON12_V 31:0 + +#define NVC997_SET_FALCON13 0x2334 +#define NVC997_SET_FALCON13_V 31:0 + +#define NVC997_SET_FALCON14 0x2338 +#define NVC997_SET_FALCON14_V 31:0 + +#define NVC997_SET_FALCON15 0x233c +#define NVC997_SET_FALCON15_V 31:0 + +#define NVC997_SET_FALCON16 0x2340 +#define NVC997_SET_FALCON16_V 31:0 + +#define NVC997_SET_FALCON17 0x2344 +#define NVC997_SET_FALCON17_V 31:0 + +#define NVC997_SET_FALCON18 0x2348 +#define NVC997_SET_FALCON18_V 31:0 + +#define NVC997_SET_FALCON19 0x234c +#define NVC997_SET_FALCON19_V 31:0 + +#define NVC997_SET_FALCON20 0x2350 +#define NVC997_SET_FALCON20_V 31:0 + +#define NVC997_SET_FALCON21 0x2354 +#define NVC997_SET_FALCON21_V 31:0 + +#define NVC997_SET_FALCON22 0x2358 +#define NVC997_SET_FALCON22_V 31:0 + +#define NVC997_SET_FALCON23 0x235c +#define NVC997_SET_FALCON23_V 31:0 + +#define NVC997_SET_FALCON24 0x2360 +#define NVC997_SET_FALCON24_V 31:0 + +#define NVC997_SET_FALCON25 0x2364 +#define NVC997_SET_FALCON25_V 31:0 + +#define NVC997_SET_FALCON26 0x2368 +#define NVC997_SET_FALCON26_V 31:0 + +#define NVC997_SET_FALCON27 0x236c +#define NVC997_SET_FALCON27_V 31:0 + +#define NVC997_SET_FALCON28 0x2370 +#define NVC997_SET_FALCON28_V 31:0 + +#define NVC997_SET_FALCON29 0x2374 +#define NVC997_SET_FALCON29_V 31:0 + +#define NVC997_SET_FALCON30 0x2378 +#define NVC997_SET_FALCON30_V 31:0 + +#define NVC997_SET_FALCON31 0x237c +#define NVC997_SET_FALCON31_V 31:0 + +#define NVC997_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC997_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC997_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC997_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC997_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC997_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC997_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC997_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC997_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC997_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC997_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC997_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC997_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC997_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC997_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC997_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC997_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC997_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC997_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC997_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC997_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC997_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC997_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC997_SET_TRAP_HANDLER_A 0x25f8 +#define NVC997_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC997_SET_TRAP_HANDLER_B 0x25fc +#define NVC997_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC997_SET_COLOR_CLAMP 0x2600 +#define NVC997_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC997_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC997_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC997_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC997_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC997_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC997_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC997_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC997_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC997_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC997_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC997_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC997_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC997_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC997_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC997_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC997_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC997_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC997_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC997_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC997_CALL_MME_MACRO_V 31:0 + +#define NVC997_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC997_CALL_MME_DATA_V 31:0 + +#endif /* _cl_ada_a_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc9b0.h b/userspace/sdks/nv525/nvidia/inc/class/clc9b0.h new file mode 100644 index 0000000..604fe53 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc9b0.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc9b0_h_ +#define _clc9b0_h_ + +#define NVC9B0_VIDEO_DECODER (0x0000C9B0) + +#endif diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc9b7.h b/userspace/sdks/nv525/nvidia/inc/class/clc9b7.h new file mode 100644 index 0000000..6a0caef --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc9b7.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc9b7_h_ +#define _clc9b7_h_ + +#define NVC9B7_VIDEO_ENCODER (0x0000C9B7) + +#endif diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc9c0.h b/userspace/sdks/nv525/nvidia/inc/class/clc9c0.h new file mode 100644 index 0000000..35da97f --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc9c0.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc9c0_h_ +#define _clc9c0_h_ + +#define ADA_COMPUTE_A 0xC9C0 + +#endif diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc9d1.h b/userspace/sdks/nv525/nvidia/inc/class/clc9d1.h new file mode 100644 index 0000000..6849f96 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc9d1.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _clc9d1_h_ +#define _clc9d1_h_ + +#define NVC9D1_VIDEO_NVJPG (0x0000C9D1) + +#endif // _clc9d1_h diff --git a/userspace/sdks/nv525/nvidia/inc/class/clc9fa.h b/userspace/sdks/nv525/nvidia/inc/class/clc9fa.h new file mode 100644 index 0000000..6b4a20a --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clc9fa.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _clc9fa_h_ +#define _clc9fa_h_ + +#define NVC9FA_VIDEO_OFA (0x0000C9FA) + +#endif // _clc9fa_h + diff --git a/userspace/sdks/nv525/nvidia/inc/class/clcb97.h b/userspace/sdks/nv525/nvidia/inc/class/clcb97.h new file mode 100644 index 0000000..7528a2d --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clcb97.h @@ -0,0 +1,4480 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_hopper_a_h_ +#define _cl_hopper_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl hopper_a */ + +#include "nvtypes.h" + +#define HOPPER_A 0xCB97 + +#define NVCB97_SET_OBJECT 0x0000 +#define NVCB97_SET_OBJECT_CLASS_ID 15:0 +#define NVCB97_SET_OBJECT_ENGINE_ID 20:16 + +#define NVCB97_NO_OPERATION 0x0100 +#define NVCB97_NO_OPERATION_V 31:0 + +#define NVCB97_SET_NOTIFY_A 0x0104 +#define NVCB97_SET_NOTIFY_A_ADDRESS_UPPER 24:0 + +#define NVCB97_SET_NOTIFY_B 0x0108 +#define NVCB97_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVCB97_NOTIFY 0x010c +#define NVCB97_NOTIFY_TYPE 31:0 +#define NVCB97_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVCB97_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVCB97_WAIT_FOR_IDLE 0x0110 +#define NVCB97_WAIT_FOR_IDLE_V 31:0 + +#define NVCB97_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVCB97_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVCB97_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVCB97_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVCB97_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVCB97_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVCB97_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVCB97_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVCB97_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVCB97_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVCB97_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVCB97_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVCB97_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVCB97_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVCB97_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVCB97_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVCB97_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVCB97_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVCB97_SEND_GO_IDLE 0x013c +#define NVCB97_SEND_GO_IDLE_V 31:0 + +#define NVCB97_PM_TRIGGER 0x0140 +#define NVCB97_PM_TRIGGER_V 31:0 + +#define NVCB97_PM_TRIGGER_WFI 0x0144 +#define NVCB97_PM_TRIGGER_WFI_V 31:0 + +#define NVCB97_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVCB97_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVCB97_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVCB97_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVCB97_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVCB97_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVCB97_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVCB97_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER 0x0158 +#define NVCB97_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER_PAYLOAD_LOWER 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER 0x015c +#define NVCB97_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD_UPPER 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_ADDRESS_LOWER 0x0160 +#define NVCB97_SET_REPORT_SEMAPHORE_ADDRESS_LOWER_LOWER 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_ADDRESS_UPPER 0x0164 +#define NVCB97_SET_REPORT_SEMAPHORE_ADDRESS_UPPER_UPPER 24:0 + +#define NVCB97_REPORT_SEMAPHORE_EXECUTE 0x0168 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_OPERATION 1:0 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_OPERATION_RELEASE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_OPERATION_ACQUIRE 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_OPERATION_REPORT_ONLY 0x00000002 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_OPERATION_TRAP 0x00000003 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION 5:2 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_NONE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_VPC 0x00000004 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_ALL 0x0000000F +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE 6:6 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT 11:7 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_NONE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_VS_INVOCATIONS 0x00000005 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_TI_INVOCATIONS 0x0000001B +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_TS_INVOCATIONS 0x0000001D +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_GS_INVOCATIONS 0x00000007 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_SCG_CLOCKS 0x00000008 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS0 0x0000000A +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS1 0x0000000C +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS2 0x0000000E +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS3 0x00000010 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_PS_INVOCATIONS 0x00000013 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_TIMESTAMP 0x00000014 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE 14:13 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_SUB_REPORT 17:15 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE 19:19 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_FALSE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_TRUE 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE 18:18 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE_FALSE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE_TRUE 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE 20:20 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP 23:21 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_ADD 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MIN 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MAX 0x00000002 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_INC 0x00000003 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_DEC 0x00000004 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_AND 0x00000005 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_OR 0x00000006 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_XOR 0x00000007 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT 25:24 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64 27:27 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_FALSE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_TRUE 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE 29:28 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_NONE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 + +#define NVCB97_LINE_LENGTH_IN 0x0180 +#define NVCB97_LINE_LENGTH_IN_VALUE 31:0 + +#define NVCB97_LINE_COUNT 0x0184 +#define NVCB97_LINE_COUNT_VALUE 31:0 + +#define NVCB97_OFFSET_OUT_UPPER 0x0188 +#define NVCB97_OFFSET_OUT_UPPER_VALUE 24:0 + +#define NVCB97_OFFSET_OUT 0x018c +#define NVCB97_OFFSET_OUT_VALUE 31:0 + +#define NVCB97_PITCH_OUT 0x0190 +#define NVCB97_PITCH_OUT_VALUE 31:0 + +#define NVCB97_SET_DST_BLOCK_SIZE 0x0194 +#define NVCB97_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVCB97_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVCB97_SET_DST_WIDTH 0x0198 +#define NVCB97_SET_DST_WIDTH_V 31:0 + +#define NVCB97_SET_DST_HEIGHT 0x019c +#define NVCB97_SET_DST_HEIGHT_V 31:0 + +#define NVCB97_SET_DST_DEPTH 0x01a0 +#define NVCB97_SET_DST_DEPTH_V 31:0 + +#define NVCB97_SET_DST_LAYER 0x01a4 +#define NVCB97_SET_DST_LAYER_V 31:0 + +#define NVCB97_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVCB97_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVCB97_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVCB97_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVCB97_LAUNCH_DMA 0x01b0 +#define NVCB97_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVCB97_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVCB97_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVCB97_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVCB97_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVCB97_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVCB97_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVCB97_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVCB97_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVCB97_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVCB97_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVCB97_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVCB97_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVCB97_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVCB97_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVCB97_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVCB97_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVCB97_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVCB97_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVCB97_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVCB97_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVCB97_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVCB97_LOAD_INLINE_DATA 0x01b4 +#define NVCB97_LOAD_INLINE_DATA_V 31:0 + +#define NVCB97_SET_I2M_SEMAPHORE_A 0x01dc +#define NVCB97_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 24:0 + +#define NVCB97_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVCB97_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVCB97_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVCB97_SET_MME_SWITCH_STATE 0x01ec +#define NVCB97_SET_MME_SWITCH_STATE_VALID 0:0 +#define NVCB97_SET_MME_SWITCH_STATE_VALID_FALSE 0x00000000 +#define NVCB97_SET_MME_SWITCH_STATE_VALID_TRUE 0x00000001 +#define NVCB97_SET_MME_SWITCH_STATE_SAVE_MACRO 11:4 +#define NVCB97_SET_MME_SWITCH_STATE_RESTORE_MACRO 19:12 + +#define NVCB97_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVCB97_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVCB97_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVCB97_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVCB97_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVCB97_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVCB97_SET_I2M_SPARE_NOOP03 0x01fc +#define NVCB97_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVCB97_RUN_DS_NOW 0x0200 +#define NVCB97_RUN_DS_NOW_V 31:0 + +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVCB97_SET_GS_MODE 0x0208 +#define NVCB97_SET_GS_MODE_TYPE 0:0 +#define NVCB97_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVCB97_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVCB97_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVCB97_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVCB97_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVCB97_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVCB97_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_GS_DM_FIFO 0x0214 +#define NVCB97_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVCB97_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVCB97_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVCB97_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVCB97_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVCB97_INVALIDATE_SHADER_CACHES 0x021c +#define NVCB97_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVCB97_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVCB97_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVCB97_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVCB97_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVCB97_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVCB97_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVCB97_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVCB97_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVCB97_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVCB97_SET_INSTANCE_COUNT 0x0220 +#define NVCB97_SET_INSTANCE_COUNT_V 31:0 + +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_GO_IDLE_TIMEOUT 0x022c +#define NVCB97_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVCB97_SET_MME_VERSION 0x0234 +#define NVCB97_SET_MME_VERSION_MAJOR 7:0 + +#define NVCB97_SET_INDEX_BUFFER_SIZE_A 0x0238 +#define NVCB97_SET_INDEX_BUFFER_SIZE_A_UPPER 7:0 + +#define NVCB97_SET_INDEX_BUFFER_SIZE_B 0x023c +#define NVCB97_SET_INDEX_BUFFER_SIZE_B_LOWER 31:0 + +#define NVCB97_SET_ROOT_TABLE_VISIBILITY(i) (0x0240+(i)*4) +#define NVCB97_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP0_ENABLE 1:0 +#define NVCB97_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP1_ENABLE 5:4 +#define NVCB97_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP2_ENABLE 9:8 +#define NVCB97_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP3_ENABLE 13:12 +#define NVCB97_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP4_ENABLE 17:16 + +#define NVCB97_SET_DRAW_CONTROL_A 0x0260 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY 3:0 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_LINES 0x00000001 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_PATCH 0x0000000E +#define NVCB97_SET_DRAW_CONTROL_A_PRIMITIVE_ID 4:4 +#define NVCB97_SET_DRAW_CONTROL_A_PRIMITIVE_ID_FIRST 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ID 6:5 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ID_FIRST 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVCB97_SET_DRAW_CONTROL_A_SPLIT_MODE 8:7 +#define NVCB97_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVCB97_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVCB97_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE 9:9 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX 10:10 +#define NVCB97_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_FALSE 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_TRUE 0x00000001 +#define NVCB97_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX 11:11 +#define NVCB97_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_FALSE 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_TRUE 0x00000001 + +#define NVCB97_SET_DRAW_CONTROL_B 0x0264 +#define NVCB97_SET_DRAW_CONTROL_B_INSTANCE_COUNT 31:0 + +#define NVCB97_DRAW_INDEX_BUFFER_BEGIN_END_A 0x0268 +#define NVCB97_DRAW_INDEX_BUFFER_BEGIN_END_A_FIRST 31:0 + +#define NVCB97_DRAW_INDEX_BUFFER_BEGIN_END_B 0x026c +#define NVCB97_DRAW_INDEX_BUFFER_BEGIN_END_B_COUNT 31:0 + +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_A 0x0270 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_A_START 31:0 + +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_B 0x0274 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_B_COUNT 31:0 + +#define NVCB97_INVALIDATE_RASTER_CACHE_NO_WFI 0x027c +#define NVCB97_INVALIDATE_RASTER_CACHE_NO_WFI_V 0:0 + +#define NVCB97_SET_COLOR_RENDER_TO_ZETA_SURFACE 0x02b8 +#define NVCB97_SET_COLOR_RENDER_TO_ZETA_SURFACE_V 0:0 +#define NVCB97_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_FALSE 0x00000000 +#define NVCB97_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_TRUE 0x00000001 + +#define NVCB97_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION 0x02bc +#define NVCB97_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V 0:0 +#define NVCB97_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_TRUE 0x00000001 + +#define NVCB97_INCREMENT_SYNC_POINT 0x02c8 +#define NVCB97_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVCB97_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVCB97_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVCB97_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVCB97_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVCB97_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVCB97_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVCB97_SET_ROOT_TABLE_PREFETCH 0x02d0 +#define NVCB97_SET_ROOT_TABLE_PREFETCH_STAGE_ENABLES 5:0 + +#define NVCB97_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVCB97_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVCB97_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVCB97_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVCB97_DECOMPRESS_SURFACE 0x02e0 +#define NVCB97_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVCB97_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVCB97_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVCB97_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVCB97_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVCB97_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVCB97_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVCB97_SET_ZCULL_SUBREGION 0x02e8 +#define NVCB97_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVCB97_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVCB97_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVCB97_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVCB97_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVCB97_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVCB97_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVCB97_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVCB97_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVCB97_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVCB97_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVCB97_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVCB97_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVCB97_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVCB97_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVCB97_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVCB97_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVCB97_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVCB97_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVCB97_DRAW_ZERO_INDEX 0x0304 +#define NVCB97_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVCB97_SET_L1_CONFIGURATION 0x0308 +#define NVCB97_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVCB97_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVCB97_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVCB97_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVCB97_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVCB97_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVCB97_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVCB97_SET_SPA_VERSION 0x0310 +#define NVCB97_SET_SPA_VERSION_MINOR 7:0 +#define NVCB97_SET_SPA_VERSION_MAJOR 15:8 + +#define NVCB97_SET_TIMESLICE_BATCH_LIMIT 0x0314 +#define NVCB97_SET_TIMESLICE_BATCH_LIMIT_BATCH_LIMIT 15:0 + +#define NVCB97_SET_SNAP_GRID_LINE 0x0318 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVCB97_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVCB97_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVCB97_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVCB97_SET_SNAP_GRID_NON_LINE 0x031c +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVCB97_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVCB97_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVCB97_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVCB97_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVCB97_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVCB97_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVCB97_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVCB97_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVCB97_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVCB97_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVCB97_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVCB97_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVCB97_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVCB97_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVCB97_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVCB97_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVCB97_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVCB97_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVCB97_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVCB97_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVCB97_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVCB97_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVCB97_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVCB97_SET_TESSELLATION_LOD_V1 0x0330 +#define NVCB97_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVCB97_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVCB97_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVCB97_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVCB97_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVCB97_RESERVED_TG07 0x033c +#define NVCB97_RESERVED_TG07_V 0:0 + +#define NVCB97_RESERVED_TG08 0x0340 +#define NVCB97_RESERVED_TG08_V 0:0 + +#define NVCB97_RESERVED_TG09 0x0344 +#define NVCB97_RESERVED_TG09_V 0:0 + +#define NVCB97_RESERVED_TG10 0x0348 +#define NVCB97_RESERVED_TG10_V 0:0 + +#define NVCB97_RESERVED_TG11 0x034c +#define NVCB97_RESERVED_TG11_V 0:0 + +#define NVCB97_RESERVED_TG12 0x0350 +#define NVCB97_RESERVED_TG12_V 0:0 + +#define NVCB97_RESERVED_TG13 0x0354 +#define NVCB97_RESERVED_TG13_V 0:0 + +#define NVCB97_RESERVED_TG14 0x0358 +#define NVCB97_RESERVED_TG14_V 0:0 + +#define NVCB97_RESERVED_TG15 0x035c +#define NVCB97_RESERVED_TG15_V 0:0 + +#define NVCB97_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVCB97_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVCB97_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVCB97_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVCB97_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVCB97_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVCB97_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVCB97_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVCB97_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVCB97_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVCB97_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVCB97_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVCB97_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVCB97_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVCB97_SET_RASTER_ENABLE 0x037c +#define NVCB97_SET_RASTER_ENABLE_V 0:0 +#define NVCB97_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVCB97_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVCB97_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVCB97_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVCB97_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVCB97_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVCB97_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVCB97_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVCB97_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVCB97_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVCB97_SET_Z_ROP_SLICE_MAP 0x0500 +#define NVCB97_SET_Z_ROP_SLICE_MAP_VIRTUAL_ADDRESS_MASK 31:0 + +#define NVCB97_SET_ROOT_TABLE_SELECTOR 0x0504 +#define NVCB97_SET_ROOT_TABLE_SELECTOR_ROOT_TABLE 2:0 +#define NVCB97_SET_ROOT_TABLE_SELECTOR_OFFSET 15:8 + +#define NVCB97_LOAD_ROOT_TABLE 0x0508 +#define NVCB97_LOAD_ROOT_TABLE_V 31:0 + +#define NVCB97_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVCB97_SET_MME_MEM_ADDRESS_A_UPPER 24:0 + +#define NVCB97_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVCB97_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVCB97_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVCB97_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVCB97_MME_DMA_READ 0x055c +#define NVCB97_MME_DMA_READ_LENGTH 31:0 + +#define NVCB97_MME_DMA_READ_FIFOED 0x0560 +#define NVCB97_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVCB97_MME_DMA_WRITE 0x0564 +#define NVCB97_MME_DMA_WRITE_LENGTH 31:0 + +#define NVCB97_MME_DMA_REDUCTION 0x0568 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVCB97_MME_DMA_SYSMEMBAR 0x056c +#define NVCB97_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVCB97_MME_DMA_SYNC 0x0570 +#define NVCB97_MME_DMA_SYNC_VALUE 31:0 + +#define NVCB97_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NVCB97_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NVCB97_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NVCB97_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NVCB97_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NVCB97_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NVCB97_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NVCB97_SET_VERTEX_STREAM_SIZE_A(j) (0x0600+(j)*8) +#define NVCB97_SET_VERTEX_STREAM_SIZE_A_UPPER 7:0 + +#define NVCB97_SET_VERTEX_STREAM_SIZE_B(j) (0x0604+(j)*8) +#define NVCB97_SET_VERTEX_STREAM_SIZE_B_LOWER 31:0 + +#define NVCB97_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVCB97_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVCB97_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVCB97_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVCB97_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVCB97_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVCB97_SET_RASTER_INPUT 0x0740 +#define NVCB97_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVCB97_SET_STREAM_OUTPUT 0x0744 +#define NVCB97_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVCB97_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVCB97_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVCB97_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVCB97_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVCB97_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVCB97_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVCB97_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVCB97_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVCB97_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVCB97_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVCB97_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVCB97_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 6:0 + +#define NVCB97_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVCB97_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVCB97_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVCB97_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVCB97_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVCB97_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVCB97_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVCB97_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVCB97_SET_TEXTURE_HEADER_VERSION 0x07ac +#define NVCB97_SET_TEXTURE_HEADER_VERSION_MAJOR 7:0 + +#define NVCB97_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVCB97_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVCB97_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVCB97_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVCB97_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVCB97_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVCB97_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVCB97_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVCB97_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVCB97_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVCB97_SET_CULL_BEFORE_FETCH 0x07dc +#define NVCB97_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVCB97_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVCB97_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVCB97_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVCB97_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVCB97_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVCB97_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVCB97_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVCB97_SET_ZCULL_STORAGE_A 0x07e8 +#define NVCB97_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_ZCULL_STORAGE_B 0x07ec +#define NVCB97_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_ZCULL_STORAGE_C 0x07f0 +#define NVCB97_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_ZCULL_STORAGE_D 0x07f4 +#define NVCB97_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_ZT_READ_ONLY 0x07f8 +#define NVCB97_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVCB97_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVCB97_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVCB97_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVCB97_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVCB97_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVCB97_THROTTLE_SM 0x07fc +#define NVCB97_THROTTLE_SM_MULTIPLY_ADD 0:0 +#define NVCB97_THROTTLE_SM_MULTIPLY_ADD_FALSE 0x00000000 +#define NVCB97_THROTTLE_SM_MULTIPLY_ADD_TRUE 0x00000001 + +#define NVCB97_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVCB97_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVCB97_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVCB97_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVCB97_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVCB97_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVCB97_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVCB97_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVCB97_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVCB97_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVCB97_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVCB97_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVCB97_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVCB97_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVCB97_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVCB97_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVCB97_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVCB97_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVCB97_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVCB97_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVCB97_SET_COLOR_TARGET_C_ROP_SLICE_MAP(j) (0x0824+(j)*64) +#define NVCB97_SET_COLOR_TARGET_C_ROP_SLICE_MAP_VIRTUAL_ADDRESS_MASK 31:0 + +#define NVCB97_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVCB97_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVCB97_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVCB97_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVCB97_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVCB97_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVCB97_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVCB97_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVCB97_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVCB97_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVCB97_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVCB97_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVCB97_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVCB97_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVCB97_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVCB97_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVCB97_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVCB97_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVCB97_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVCB97_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVCB97_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVCB97_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVCB97_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVCB97_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVCB97_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVCB97_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVCB97_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVCB97_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVCB97_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVCB97_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVCB97_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVCB97_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVCB97_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVCB97_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVCB97_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVCB97_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVCB97_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVCB97_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVCB97_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVCB97_SET_STATISTICS_COUNTER 0x0d68 +#define NVCB97_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVCB97_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVCB97_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVCB97_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVCB97_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVCB97_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVCB97_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVCB97_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVCB97_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVCB97_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVCB97_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVCB97_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVCB97_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVCB97_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVCB97_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVCB97_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVCB97_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVCB97_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVCB97_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVCB97_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVCB97_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVCB97_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVCB97_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVCB97_SET_VERTEX_ARRAY_START 0x0d74 +#define NVCB97_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVCB97_DRAW_VERTEX_ARRAY 0x0d78 +#define NVCB97_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVCB97_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVCB97_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVCB97_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVCB97_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVCB97_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVCB97_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVCB97_SET_Z_CLEAR_VALUE 0x0d90 +#define NVCB97_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVCB97_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVCB97_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVCB97_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVCB97_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVCB97_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVCB97_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVCB97_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVCB97_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVCB97_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVCB97_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVCB97_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVCB97_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVCB97_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVCB97_SET_FRONT_POLYGON_MODE 0x0dac +#define NVCB97_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVCB97_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVCB97_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVCB97_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVCB97_SET_BACK_POLYGON_MODE 0x0db0 +#define NVCB97_SET_BACK_POLYGON_MODE_V 31:0 +#define NVCB97_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVCB97_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVCB97_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVCB97_SET_POLY_SMOOTH 0x0db4 +#define NVCB97_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVCB97_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVCB97_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVCB97_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVCB97_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVCB97_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVCB97_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVCB97_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVCB97_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_PATCH 0x0dcc +#define NVCB97_SET_PATCH_SIZE 7:0 + +#define NVCB97_SET_ITERATED_BLEND 0x0dd0 +#define NVCB97_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVCB97_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVCB97_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVCB97_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVCB97_SET_ZCULL_CRITERION 0x0dd8 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVCB97_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVCB97_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVCB97_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_CRITERION_SREF 23:16 +#define NVCB97_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVCB97_PIXEL_SHADER_BARRIER 0x0de0 +#define NVCB97_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVCB97_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVCB97_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 +#define NVCB97_PIXEL_SHADER_BARRIER_BARRIER_LOCATION 1:1 +#define NVCB97_PIXEL_SHADER_BARRIER_BARRIER_LOCATION_BLOCK_BEFORE_PS 0x00000000 +#define NVCB97_PIXEL_SHADER_BARRIER_BARRIER_LOCATION_BLOCK_BEFORE_PS_AND_ZTEST 0x00000001 + +#define NVCB97_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVCB97_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVCB97_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVCB97_MME_DMA_WRITE_METHOD_BARRIER 0x0dec +#define NVCB97_MME_DMA_WRITE_METHOD_BARRIER_V 0:0 + +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVCB97_SET_WINDOW_OFFSET_X 0x0df8 +#define NVCB97_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVCB97_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVCB97_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVCB97_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVCB97_SET_SCISSOR_ENABLE_V 0:0 +#define NVCB97_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVCB97_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVCB97_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVCB97_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVCB97_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVCB97_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVCB97_SET_VPC_PERF_KNOB 0x0f14 +#define NVCB97_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVCB97_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVCB97_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVCB97_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVCB97_PM_LOCAL_TRIGGER 0x0f18 +#define NVCB97_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVCB97_SET_POST_Z_PS_IMASK 0x0f1c +#define NVCB97_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVCB97_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVCB97_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVCB97_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVCB97_SET_BACK_STENCIL_MASK 0x0f58 +#define NVCB97_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVCB97_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVCB97_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVCB97_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVCB97_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVCB97_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVCB97_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVCB97_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVCB97_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVCB97_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVCB97_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVCB97_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVCB97_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVCB97_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVCB97_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVCB97_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVCB97_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVCB97_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVCB97_SET_SAMPLE_MASK 0x0fa4 +#define NVCB97_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVCB97_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVCB97_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVCB97_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVCB97_SET_CT_MRT_ENABLE 0x0fac +#define NVCB97_SET_CT_MRT_ENABLE_V 0:0 +#define NVCB97_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVCB97_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVCB97_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVCB97_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVCB97_SET_TIR 0x0fb4 +#define NVCB97_SET_TIR_MODE 1:0 +#define NVCB97_SET_TIR_MODE_DISABLED 0x00000000 +#define NVCB97_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVCB97_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVCB97_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVCB97_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVCB97_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVCB97_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVCB97_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVCB97_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVCB97_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVCB97_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVCB97_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVCB97_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVCB97_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVCB97_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVCB97_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVCB97_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVCB97_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVCB97_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVCB97_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_TIR_MODULATION 0x0fd4 +#define NVCB97_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVCB97_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVCB97_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVCB97_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVCB97_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVCB97_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVCB97_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVCB97_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVCB97_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVCB97_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVCB97_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVCB97_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVCB97_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVCB97_SET_ZT_A 0x0fe0 +#define NVCB97_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_ZT_B 0x0fe4 +#define NVCB97_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_ZT_FORMAT 0x0fe8 +#define NVCB97_SET_ZT_FORMAT_V 4:0 +#define NVCB97_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVCB97_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVCB97_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVCB97_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVCB97_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVCB97_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVCB97_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 + +#define NVCB97_SET_ZT_BLOCK_SIZE 0x0fec +#define NVCB97_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVCB97_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVCB97_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVCB97_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVCB97_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVCB97_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVCB97_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVCB97_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVCB97_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVCB97_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVCB97_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVCB97_SET_VIEWPORT_MULTICAST 0x1004 +#define NVCB97_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVCB97_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVCB97_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVCB97_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVCB97_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVCB97_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVCB97_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVCB97_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVCB97_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVCB97_SET_RESERVED_SW_METHOD00 0x1014 +#define NVCB97_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVCB97_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVCB97_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVCB97_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVCB97_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVCB97_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVCB97_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVCB97_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVCB97_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVCB97_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_RESERVED_SW_METHOD01 0x1028 +#define NVCB97_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD02 0x102c +#define NVCB97_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVCB97_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVCB97_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVCB97_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVCB97_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVCB97_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVCB97_SET_SPARE_NOOP01 0x1044 +#define NVCB97_SET_SPARE_NOOP01_V 31:0 + +#define NVCB97_SET_SPARE_NOOP02 0x1048 +#define NVCB97_SET_SPARE_NOOP02_V 31:0 + +#define NVCB97_SET_SPARE_NOOP03 0x104c +#define NVCB97_SET_SPARE_NOOP03_V 31:0 + +#define NVCB97_SET_SPARE_NOOP04 0x1050 +#define NVCB97_SET_SPARE_NOOP04_V 31:0 + +#define NVCB97_SET_SPARE_NOOP05 0x1054 +#define NVCB97_SET_SPARE_NOOP05_V 31:0 + +#define NVCB97_SET_SPARE_NOOP06 0x1058 +#define NVCB97_SET_SPARE_NOOP06_V 31:0 + +#define NVCB97_SET_SPARE_NOOP07 0x105c +#define NVCB97_SET_SPARE_NOOP07_V 31:0 + +#define NVCB97_SET_SPARE_NOOP08 0x1060 +#define NVCB97_SET_SPARE_NOOP08_V 31:0 + +#define NVCB97_SET_SPARE_NOOP09 0x1064 +#define NVCB97_SET_SPARE_NOOP09_V 31:0 + +#define NVCB97_SET_SPARE_NOOP10 0x1068 +#define NVCB97_SET_SPARE_NOOP10_V 31:0 + +#define NVCB97_SET_SPARE_NOOP11 0x106c +#define NVCB97_SET_SPARE_NOOP11_V 31:0 + +#define NVCB97_SET_SPARE_NOOP12 0x1070 +#define NVCB97_SET_SPARE_NOOP12_V 31:0 + +#define NVCB97_SET_SPARE_NOOP13 0x1074 +#define NVCB97_SET_SPARE_NOOP13_V 31:0 + +#define NVCB97_SET_SPARE_NOOP14 0x1078 +#define NVCB97_SET_SPARE_NOOP14_V 31:0 + +#define NVCB97_SET_SPARE_NOOP15 0x107c +#define NVCB97_SET_SPARE_NOOP15_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVCB97_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVCB97_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVCB97_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD06 0x10bc +#define NVCB97_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVCB97_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVCB97_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVCB97_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVCB97_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVCB97_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVCB97_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVCB97_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD13 0x10dc +#define NVCB97_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVCB97_UNBIND_ALL 0x10f4 +#define NVCB97_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVCB97_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVCB97_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVCB97_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVCB97_SET_RESERVED_SW_METHOD14 0x1100 +#define NVCB97_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD15 0x1104 +#define NVCB97_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVCB97_NO_OPERATION_DATA_HI 0x110c +#define NVCB97_NO_OPERATION_DATA_HI_V 31:0 + +#define NVCB97_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVCB97_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVCB97_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVCB97_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVCB97_PM_TRIGGER_END 0x1114 +#define NVCB97_PM_TRIGGER_END_V 31:0 + +#define NVCB97_SET_VERTEX_ID_BASE 0x1118 +#define NVCB97_SET_VERTEX_ID_BASE_V 31:0 + +#define NVCB97_SET_STENCIL_COMPRESSION 0x111c +#define NVCB97_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVCB97_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVCB97_SET_TIR_CONTROL 0x1130 +#define NVCB97_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVCB97_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVCB97_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVCB97_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVCB97_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVCB97_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVCB97_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVCB97_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVCB97_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 +#define NVCB97_SET_TIR_CONTROL_REDUCTION_MODE 2:2 +#define NVCB97_SET_TIR_CONTROL_REDUCTION_MODE_AFFINITY_MAP 0x00000000 +#define NVCB97_SET_TIR_CONTROL_REDUCTION_MODE_TRUNCATION 0x00000001 + +#define NVCB97_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVCB97_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVCB97_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVCB97_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVCB97_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVCB97_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVCB97_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVCB97_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVCB97_SET_FILL_VIA_TRIANGLE 0x113c +#define NVCB97_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVCB97_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVCB97_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVCB97_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVCB97_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVCB97_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVCB97_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVCB97_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVCB97_FLUSH_PENDING_WRITES 0x1144 +#define NVCB97_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVCB97_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVCB97_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVCB97_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVCB97_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVCB97_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVCB97_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVCB97_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVCB97_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVCB97_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVCB97_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVCB97_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVCB97_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVCB97_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVCB97_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVCB97_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVCB97_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVCB97_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVCB97_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_SCREEN_STATE_MASK 0x1204 +#define NVCB97_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVCB97_SET_ZT_SPARSE 0x1208 +#define NVCB97_SET_ZT_SPARSE_ENABLE 0:0 +#define NVCB97_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVCB97_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVCB97_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_SET_CT_SELECT 0x121c +#define NVCB97_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVCB97_SET_CT_SELECT_TARGET0 6:4 +#define NVCB97_SET_CT_SELECT_TARGET1 9:7 +#define NVCB97_SET_CT_SELECT_TARGET2 12:10 +#define NVCB97_SET_CT_SELECT_TARGET3 15:13 +#define NVCB97_SET_CT_SELECT_TARGET4 18:16 +#define NVCB97_SET_CT_SELECT_TARGET5 21:19 +#define NVCB97_SET_CT_SELECT_TARGET6 24:22 +#define NVCB97_SET_CT_SELECT_TARGET7 27:25 + +#define NVCB97_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVCB97_SET_ZT_SIZE_A 0x1228 +#define NVCB97_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVCB97_SET_ZT_SIZE_B 0x122c +#define NVCB97_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVCB97_SET_ZT_SIZE_C 0x1230 +#define NVCB97_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVCB97_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVCB97_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVCB97_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVCB97_SET_SAMPLER_BINDING 0x1234 +#define NVCB97_SET_SAMPLER_BINDING_V 0:0 +#define NVCB97_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVCB97_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVCB97_DRAW_AUTO 0x123c +#define NVCB97_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVCB97_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVCB97_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVCB97_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVCB97_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVCB97_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVCB97_SET_BACK_END_COPY_A 0x1264 +#define NVCB97_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVCB97_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVCB97_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVCB97_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BACK_END_COPY_B 0x1268 +#define NVCB97_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_BACK_END_COPY_C 0x126c +#define NVCB97_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_BACK_END_COPY_D 0x1270 +#define NVCB97_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_BACK_END_COPY_E 0x1274 +#define NVCB97_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVCB97_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVCB97_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVCB97_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVCB97_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVCB97_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVCB97_CLEAR_ZCULL_REGION 0x12c8 +#define NVCB97_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVCB97_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVCB97_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVCB97_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVCB97_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVCB97_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVCB97_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVCB97_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVCB97_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVCB97_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVCB97_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVCB97_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVCB97_SET_DEPTH_TEST 0x12cc +#define NVCB97_SET_DEPTH_TEST_ENABLE 0:0 +#define NVCB97_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_FILL_MODE 0x12d0 +#define NVCB97_SET_FILL_MODE_V 31:0 +#define NVCB97_SET_FILL_MODE_V_POINT 0x00000001 +#define NVCB97_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVCB97_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVCB97_SET_SHADE_MODE 0x12d4 +#define NVCB97_SET_SHADE_MODE_V 31:0 +#define NVCB97_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVCB97_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVCB97_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVCB97_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVCB97_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVCB97_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVCB97_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVCB97_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVCB97_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVCB97_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVCB97_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVCB97_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_DEPTH_WRITE 0x12e8 +#define NVCB97_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVCB97_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_ALPHA_TEST 0x12ec +#define NVCB97_SET_ALPHA_TEST_ENABLE 0:0 +#define NVCB97_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVCB97_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVCB97_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVCB97_DRAW_INLINE_INDEX4X8 0x1304 +#define NVCB97_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVCB97_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVCB97_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVCB97_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVCB97_D3D_SET_CULL_MODE 0x1308 +#define NVCB97_D3D_SET_CULL_MODE_V 31:0 +#define NVCB97_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVCB97_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVCB97_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVCB97_SET_DEPTH_FUNC 0x130c +#define NVCB97_SET_DEPTH_FUNC_V 31:0 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVCB97_SET_ALPHA_REF 0x1310 +#define NVCB97_SET_ALPHA_REF_V 31:0 + +#define NVCB97_SET_ALPHA_FUNC 0x1314 +#define NVCB97_SET_ALPHA_FUNC_V 31:0 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVCB97_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVCB97_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVCB97_SET_BLEND_CONST_RED 0x131c +#define NVCB97_SET_BLEND_CONST_RED_V 31:0 + +#define NVCB97_SET_BLEND_CONST_GREEN 0x1320 +#define NVCB97_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVCB97_SET_BLEND_CONST_BLUE 0x1324 +#define NVCB97_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVCB97_SET_BLEND_CONST_ALPHA 0x1328 +#define NVCB97_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVCB97_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVCB97_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVCB97_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVCB97_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BLEND_COLOR_OP 0x1340 +#define NVCB97_SET_BLEND_COLOR_OP_V 31:0 +#define NVCB97_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVCB97_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVCB97_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVCB97_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVCB97_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVCB97_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVCB97_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVCB97_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVCB97_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVCB97_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_BLEND_ALPHA_OP 0x134c +#define NVCB97_SET_BLEND_ALPHA_OP_V 31:0 +#define NVCB97_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVCB97_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVCB97_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVCB97_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVCB97_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVCB97_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVCB97_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVCB97_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVCB97_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVCB97_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVCB97_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVCB97_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_SINGLE_ROP_CONTROL 0x135c +#define NVCB97_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVCB97_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BLEND(i) (0x1360+(i)*4) +#define NVCB97_SET_BLEND_ENABLE 0:0 +#define NVCB97_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_STENCIL_TEST 0x1380 +#define NVCB97_SET_STENCIL_TEST_ENABLE 0:0 +#define NVCB97_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_STENCIL_OP_FAIL 0x1384 +#define NVCB97_SET_STENCIL_OP_FAIL_V 31:0 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVCB97_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVCB97_SET_STENCIL_OP_ZPASS 0x138c +#define NVCB97_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVCB97_SET_STENCIL_FUNC 0x1390 +#define NVCB97_SET_STENCIL_FUNC_V 31:0 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVCB97_SET_STENCIL_FUNC_REF 0x1394 +#define NVCB97_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVCB97_SET_STENCIL_FUNC_MASK 0x1398 +#define NVCB97_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVCB97_SET_STENCIL_MASK 0x139c +#define NVCB97_SET_STENCIL_MASK_V 7:0 + +#define NVCB97_SET_DRAW_AUTO_START 0x13a4 +#define NVCB97_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVCB97_SET_PS_SATURATE 0x13a8 +#define NVCB97_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVCB97_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVCB97_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVCB97_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVCB97_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVCB97_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVCB97_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVCB97_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVCB97_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVCB97_SET_WINDOW_ORIGIN 0x13ac +#define NVCB97_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVCB97_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVCB97_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVCB97_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVCB97_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVCB97_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVCB97_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVCB97_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVCB97_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVCB97_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVCB97_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVCB97_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVCB97_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVCB97_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVCB97_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVCB97_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVCB97_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVCB97_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVCB97_SET_PS_WARP_WATERMARKS 0x1450 +#define NVCB97_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVCB97_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVCB97_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVCB97_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVCB97_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVCB97_STORE_ZCULL 0x1464 +#define NVCB97_STORE_ZCULL_V 0:0 + +#define NVCB97_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVCB97_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVCB97_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVCB97_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVCB97_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVCB97_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVCB97_LOAD_ZCULL 0x1500 +#define NVCB97_LOAD_ZCULL_V 0:0 + +#define NVCB97_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVCB97_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVCB97_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVCB97_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVCB97_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVCB97_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVCB97_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVCB97_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVCB97_SET_USER_CLIP_ENABLE 0x1510 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVCB97_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVCB97_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVCB97_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_POINT_SIZE 0x1518 +#define NVCB97_SET_POINT_SIZE_V 31:0 + +#define NVCB97_SET_ZCULL_STATS 0x151c +#define NVCB97_SET_ZCULL_STATS_ENABLE 0:0 +#define NVCB97_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_POINT_SPRITE 0x1520 +#define NVCB97_SET_POINT_SPRITE_ENABLE 0:0 +#define NVCB97_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_SHADER_EXCEPTIONS 0x1528 +#define NVCB97_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVCB97_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVCB97_CLEAR_REPORT_VALUE 0x1530 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVCB97_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVCB97_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVCB97_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_ZT_SELECT 0x1538 +#define NVCB97_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVCB97_SET_RENDER_ENABLE_A 0x1550 +#define NVCB97_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_RENDER_ENABLE_B 0x1554 +#define NVCB97_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_RENDER_ENABLE_C 0x1558 +#define NVCB97_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVCB97_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVCB97_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVCB97_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVCB97_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVCB97_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVCB97_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVCB97_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVCB97_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVCB97_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVCB97_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVCB97_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVCB97_SET_ANTI_ALIASED_LINE 0x1570 +#define NVCB97_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVCB97_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_TEX_HEADER_POOL_A 0x1574 +#define NVCB97_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_TEX_HEADER_POOL_B 0x1578 +#define NVCB97_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_TEX_HEADER_POOL_C 0x157c +#define NVCB97_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVCB97_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVCB97_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVCB97_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVCB97_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVCB97_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVCB97_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVCB97_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVCB97_SET_SRGB_WRITE 0x15b8 +#define NVCB97_SET_SRGB_WRITE_ENABLE 0:0 +#define NVCB97_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_DEPTH_BIAS 0x15bc +#define NVCB97_SET_DEPTH_BIAS_V 31:0 + +#define NVCB97_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVCB97_SET_RT_LAYER 0x15cc +#define NVCB97_SET_RT_LAYER_V 15:0 +#define NVCB97_SET_RT_LAYER_CONTROL 16:16 +#define NVCB97_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVCB97_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVCB97_SET_ANTI_ALIAS 0x15d0 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVCB97_SET_EDGE_FLAG 0x15e4 +#define NVCB97_SET_EDGE_FLAG_V 0:0 +#define NVCB97_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVCB97_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVCB97_DRAW_INLINE_INDEX 0x15e8 +#define NVCB97_DRAW_INLINE_INDEX_V 31:0 + +#define NVCB97_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVCB97_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVCB97_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVCB97_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVCB97_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVCB97_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVCB97_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVCB97_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVCB97_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVCB97_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVCB97_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVCB97_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVCB97_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVCB97_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVCB97_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVCB97_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVCB97_SET_POINT_SPRITE_SELECT 0x1604 +#define NVCB97_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVCB97_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVCB97_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVCB97_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVCB97_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVCB97_END 0x1614 +#define NVCB97_END_V 0:0 + +#define NVCB97_BEGIN 0x1618 +#define NVCB97_BEGIN_OP 15:0 +#define NVCB97_BEGIN_OP_POINTS 0x00000000 +#define NVCB97_BEGIN_OP_LINES 0x00000001 +#define NVCB97_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVCB97_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVCB97_BEGIN_OP_TRIANGLES 0x00000004 +#define NVCB97_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVCB97_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVCB97_BEGIN_OP_QUADS 0x00000007 +#define NVCB97_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVCB97_BEGIN_OP_POLYGON 0x00000009 +#define NVCB97_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVCB97_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_BEGIN_OP_PATCH 0x0000000E +#define NVCB97_BEGIN_PRIMITIVE_ID 24:24 +#define NVCB97_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVCB97_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVCB97_BEGIN_INSTANCE_ID 27:26 +#define NVCB97_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVCB97_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVCB97_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVCB97_BEGIN_SPLIT_MODE 30:29 +#define NVCB97_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVCB97_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVCB97_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVCB97_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVCB97_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVCB97_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVCB97_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_VERTEX_ID_COPY 0x161c +#define NVCB97_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVCB97_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVCB97_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVCB97_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVCB97_LOAD_PRIMITIVE_ID 0x1624 +#define NVCB97_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVCB97_SET_SHADER_BASED_CULL 0x162c +#define NVCB97_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVCB97_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVCB97_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_CLASS_VERSION 0x1638 +#define NVCB97_SET_CLASS_VERSION_CURRENT 15:0 +#define NVCB97_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCB97_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVCB97_SET_DA_OUTPUT 0x164c +#define NVCB97_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVCB97_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVCB97_SET_ANTI_ALIASED_POINT 0x1658 +#define NVCB97_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVCB97_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_POINT_CENTER_MODE 0x165c +#define NVCB97_SET_POINT_CENTER_MODE_V 31:0 +#define NVCB97_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVCB97_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVCB97_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVCB97_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVCB97_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVCB97_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVCB97_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVCB97_SET_LINE_STIPPLE 0x166c +#define NVCB97_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVCB97_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVCB97_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVCB97_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVCB97_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVCB97_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVCB97_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVCB97_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVCB97_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVCB97_SET_PROVOKING_VERTEX 0x1684 +#define NVCB97_SET_PROVOKING_VERTEX_V 0:0 +#define NVCB97_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVCB97_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVCB97_SET_TWO_SIDED_LIGHT 0x1688 +#define NVCB97_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVCB97_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_POLYGON_STIPPLE 0x168c +#define NVCB97_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVCB97_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_SHADER_CONTROL 0x1690 +#define NVCB97_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVCB97_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVCB97_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVCB97_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVCB97_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVCB97_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVCB97_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVCB97_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVCB97_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVCB97_CHECK_CLASS_VERSION 0x16a0 +#define NVCB97_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVCB97_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCB97_SET_SPH_VERSION 0x16a4 +#define NVCB97_SET_SPH_VERSION_CURRENT 15:0 +#define NVCB97_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCB97_CHECK_SPH_VERSION 0x16a8 +#define NVCB97_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVCB97_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVCB97_SET_SCG_GRAPHICS_PRIORITY 0x16bc +#define NVCB97_SET_SCG_GRAPHICS_PRIORITY_PRIORITY 5:0 + +#define NVCB97_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS(i) (0x16c0+(i)*4) +#define NVCB97_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS_V 31:0 + +#define NVCB97_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVCB97_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVCB97_SET_AAM_VERSION 0x1790 +#define NVCB97_SET_AAM_VERSION_CURRENT 15:0 +#define NVCB97_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCB97_CHECK_AAM_VERSION 0x1794 +#define NVCB97_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVCB97_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCB97_SET_ZT_LAYER 0x179c +#define NVCB97_SET_ZT_LAYER_OFFSET 15:0 + +#define NVCB97_SET_INDEX_BUFFER_A 0x17c8 +#define NVCB97_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_INDEX_BUFFER_B 0x17cc +#define NVCB97_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_INDEX_BUFFER_E 0x17d8 +#define NVCB97_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVCB97_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVCB97_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVCB97_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVCB97_SET_INDEX_BUFFER_F 0x17dc +#define NVCB97_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVCB97_DRAW_INDEX_BUFFER 0x17e0 +#define NVCB97_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVCB97_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVCB97_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVCB97_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVCB97_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVCB97_OGL_SET_CULL 0x1918 +#define NVCB97_OGL_SET_CULL_ENABLE 0:0 +#define NVCB97_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVCB97_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVCB97_OGL_SET_FRONT_FACE 0x191c +#define NVCB97_OGL_SET_FRONT_FACE_V 31:0 +#define NVCB97_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVCB97_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVCB97_OGL_SET_CULL_FACE 0x1920 +#define NVCB97_OGL_SET_CULL_FACE_V 31:0 +#define NVCB97_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVCB97_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVCB97_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVCB97_SET_VIEWPORT_PIXEL 0x1924 +#define NVCB97_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVCB97_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVCB97_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVCB97_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVCB97_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVCB97_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE 17:16 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_USE_FIELD_MIN_Z_ZERO_MAX_Z_ONE 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MIN_Z_MAX_Z 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_ZERO_ONE 0x00000002 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MINUS_INF_PLUS_INF 0x00000003 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVCB97_SET_USER_CLIP_OP 0x1940 +#define NVCB97_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVCB97_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVCB97_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVCB97_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVCB97_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVCB97_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVCB97_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVCB97_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVCB97_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVCB97_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVCB97_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVCB97_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVCB97_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVCB97_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVCB97_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVCB97_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVCB97_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVCB97_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVCB97_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVCB97_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVCB97_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVCB97_INVALIDATE_ZCULL 0x1958 +#define NVCB97_INVALIDATE_ZCULL_V 31:0 +#define NVCB97_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVCB97_SET_ZCULL 0x1968 +#define NVCB97_SET_ZCULL_Z_ENABLE 0:0 +#define NVCB97_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVCB97_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_ZCULL_BOUNDS 0x196c +#define NVCB97_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVCB97_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVCB97_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVCB97_ZCULL_SYNC 0x1978 +#define NVCB97_ZCULL_SYNC_V 31:0 + +#define NVCB97_SET_CLIP_ID_TEST 0x197c +#define NVCB97_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVCB97_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVCB97_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVCB97_SET_CLIP_ID 0x1984 +#define NVCB97_SET_CLIP_ID_V 31:0 + +#define NVCB97_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVCB97_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVCB97_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVCB97_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVCB97_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVCB97_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVCB97_SET_LOGIC_OP 0x19c4 +#define NVCB97_SET_LOGIC_OP_ENABLE 0:0 +#define NVCB97_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_LOGIC_OP_FUNC 0x19c8 +#define NVCB97_SET_LOGIC_OP_FUNC_V 31:0 +#define NVCB97_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVCB97_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVCB97_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVCB97_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVCB97_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVCB97_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVCB97_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVCB97_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVCB97_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVCB97_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVCB97_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVCB97_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVCB97_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVCB97_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVCB97_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVCB97_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVCB97_SET_Z_COMPRESSION 0x19cc +#define NVCB97_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVCB97_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVCB97_CLEAR_SURFACE 0x19d0 +#define NVCB97_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVCB97_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVCB97_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVCB97_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVCB97_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVCB97_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVCB97_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVCB97_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVCB97_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVCB97_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVCB97_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVCB97_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVCB97_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVCB97_SET_CT_WRITE_R_ENABLE 0:0 +#define NVCB97_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_CT_WRITE_G_ENABLE 4:4 +#define NVCB97_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_CT_WRITE_B_ENABLE 8:8 +#define NVCB97_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_CT_WRITE_A_ENABLE 12:12 +#define NVCB97_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVCB97_PIPE_NOP 0x1a2c +#define NVCB97_PIPE_NOP_V 31:0 + +#define NVCB97_SET_SPARE00 0x1a30 +#define NVCB97_SET_SPARE00_V 31:0 + +#define NVCB97_SET_SPARE01 0x1a34 +#define NVCB97_SET_SPARE01_V 31:0 + +#define NVCB97_SET_SPARE02 0x1a38 +#define NVCB97_SET_SPARE02_V 31:0 + +#define NVCB97_SET_SPARE03 0x1a3c +#define NVCB97_SET_SPARE03_V 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVCB97_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 24:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVCB97_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVCB97_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVCB97_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVCB97_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVCB97_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVCB97_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVCB97_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVCB97_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVCB97_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVCB97_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVCB97_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_TIMESTAMP 0x00000014 +#define NVCB97_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVCB97_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVCB97_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVCB97_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVCB97_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVCB97_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVCB97_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVCB97_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVCB97_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVCB97_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVCB97_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVCB97_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVCB97_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVCB97_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVCB97_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVCB97_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVCB97_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVCB97_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVCB97_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVCB97_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVCB97_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVCB97_SET_PIPELINE_RESERVED_B(j) (0x2004+(j)*64) +#define NVCB97_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVCB97_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVCB97_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVCB97_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVCB97_SET_PIPELINE_REGISTER_COUNT_V 8:0 + +#define NVCB97_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVCB97_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVCB97_SET_PIPELINE_PROGRAM_ADDRESS_A(j) (0x2014+(j)*64) +#define NVCB97_SET_PIPELINE_PROGRAM_ADDRESS_A_UPPER 7:0 + +#define NVCB97_SET_PIPELINE_PROGRAM_ADDRESS_B(j) (0x2018+(j)*64) +#define NVCB97_SET_PIPELINE_PROGRAM_ADDRESS_B_LOWER 31:0 + +#define NVCB97_SET_PIPELINE_PROGRAM_PREFETCH(j) (0x201c+(j)*64) +#define NVCB97_SET_PIPELINE_PROGRAM_PREFETCH_SIZE_IN_BLOCKS 6:0 + +#define NVCB97_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVCB97_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVCB97_SET_FALCON00 0x2300 +#define NVCB97_SET_FALCON00_V 31:0 + +#define NVCB97_SET_FALCON01 0x2304 +#define NVCB97_SET_FALCON01_V 31:0 + +#define NVCB97_SET_FALCON02 0x2308 +#define NVCB97_SET_FALCON02_V 31:0 + +#define NVCB97_SET_FALCON03 0x230c +#define NVCB97_SET_FALCON03_V 31:0 + +#define NVCB97_SET_FALCON04 0x2310 +#define NVCB97_SET_FALCON04_V 31:0 + +#define NVCB97_SET_FALCON05 0x2314 +#define NVCB97_SET_FALCON05_V 31:0 + +#define NVCB97_SET_FALCON06 0x2318 +#define NVCB97_SET_FALCON06_V 31:0 + +#define NVCB97_SET_FALCON07 0x231c +#define NVCB97_SET_FALCON07_V 31:0 + +#define NVCB97_SET_FALCON08 0x2320 +#define NVCB97_SET_FALCON08_V 31:0 + +#define NVCB97_SET_FALCON09 0x2324 +#define NVCB97_SET_FALCON09_V 31:0 + +#define NVCB97_SET_FALCON10 0x2328 +#define NVCB97_SET_FALCON10_V 31:0 + +#define NVCB97_SET_FALCON11 0x232c +#define NVCB97_SET_FALCON11_V 31:0 + +#define NVCB97_SET_FALCON12 0x2330 +#define NVCB97_SET_FALCON12_V 31:0 + +#define NVCB97_SET_FALCON13 0x2334 +#define NVCB97_SET_FALCON13_V 31:0 + +#define NVCB97_SET_FALCON14 0x2338 +#define NVCB97_SET_FALCON14_V 31:0 + +#define NVCB97_SET_FALCON15 0x233c +#define NVCB97_SET_FALCON15_V 31:0 + +#define NVCB97_SET_FALCON16 0x2340 +#define NVCB97_SET_FALCON16_V 31:0 + +#define NVCB97_SET_FALCON17 0x2344 +#define NVCB97_SET_FALCON17_V 31:0 + +#define NVCB97_SET_FALCON18 0x2348 +#define NVCB97_SET_FALCON18_V 31:0 + +#define NVCB97_SET_FALCON19 0x234c +#define NVCB97_SET_FALCON19_V 31:0 + +#define NVCB97_SET_FALCON20 0x2350 +#define NVCB97_SET_FALCON20_V 31:0 + +#define NVCB97_SET_FALCON21 0x2354 +#define NVCB97_SET_FALCON21_V 31:0 + +#define NVCB97_SET_FALCON22 0x2358 +#define NVCB97_SET_FALCON22_V 31:0 + +#define NVCB97_SET_FALCON23 0x235c +#define NVCB97_SET_FALCON23_V 31:0 + +#define NVCB97_SET_FALCON24 0x2360 +#define NVCB97_SET_FALCON24_V 31:0 + +#define NVCB97_SET_FALCON25 0x2364 +#define NVCB97_SET_FALCON25_V 31:0 + +#define NVCB97_SET_FALCON26 0x2368 +#define NVCB97_SET_FALCON26_V 31:0 + +#define NVCB97_SET_FALCON27 0x236c +#define NVCB97_SET_FALCON27_V 31:0 + +#define NVCB97_SET_FALCON28 0x2370 +#define NVCB97_SET_FALCON28_V 31:0 + +#define NVCB97_SET_FALCON29 0x2374 +#define NVCB97_SET_FALCON29_V 31:0 + +#define NVCB97_SET_FALCON30 0x2378 +#define NVCB97_SET_FALCON30_V 31:0 + +#define NVCB97_SET_FALCON31 0x237c +#define NVCB97_SET_FALCON31_V 31:0 + +#define NVCB97_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVCB97_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVCB97_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVCB97_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVCB97_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVCB97_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVCB97_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVCB97_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVCB97_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVCB97_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVCB97_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVCB97_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVCB97_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVCB97_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVCB97_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVCB97_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVCB97_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVCB97_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVCB97_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVCB97_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVCB97_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVCB97_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVCB97_SET_TRAP_HANDLER_A 0x25f8 +#define NVCB97_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVCB97_SET_TRAP_HANDLER_B 0x25fc +#define NVCB97_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_COLOR_CLAMP 0x2600 +#define NVCB97_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVCB97_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVCB97_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVCB97_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVCB97_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVCB97_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVCB97_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVCB97_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVCB97_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVCB97_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVCB97_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVCB97_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVCB97_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVCB97_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVCB97_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVCB97_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVCB97_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVCB97_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVCB97_CALL_MME_MACRO_V 31:0 + +#define NVCB97_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVCB97_CALL_MME_DATA_V 31:0 + +#endif /* _cl_hopper_a_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clcb97tex.h b/userspace/sdks/nv525/nvidia/inc/class/clcb97tex.h new file mode 100644 index 0000000..f9871b7 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clcb97tex.h @@ -0,0 +1,2437 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLCB97TEX_H__ +#define __CLCB97TEX_H__ + +/* +** Texture Header State Blocklinear + */ + +#define NVCB97_TEXHEAD_BL_COMPONENTS MW(6:0) +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE MW(9:7) +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE MW(12:10) +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE MW(15:13) +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE MW(18:16) +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_X_SOURCE MW(21:19) +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_Y_SOURCE MW(24:22) +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_Z_SOURCE MW(27:25) +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_W_SOURCE MW(30:28) +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_PACK_COMPONENTS MW(31:31) +#define NVCB97_TEXHEAD_BL_RESERVED1Y MW(36:32) +#define NVCB97_TEXHEAD_BL_GOB_DEPTH_OFFSET MW(38:37) +#define NVCB97_TEXHEAD_BL_RESERVED1X MW(40:39) +#define NVCB97_TEXHEAD_BL_ADDRESS_BITS31TO9 MW(63:41) +#define NVCB97_TEXHEAD_BL_ADDRESS_BITS48TO32 MW(80:64) +#define NVCB97_TEXHEAD_BL_RESERVED_ADDRESS MW(84:81) +#define NVCB97_TEXHEAD_BL_HEADER_VERSION MW(87:85) +#define NVCB97_TEXHEAD_BL_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVCB97_TEXHEAD_BL_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVCB97_TEXHEAD_BL_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVCB97_TEXHEAD_BL_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVCB97_TEXHEAD_BL_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVCB97_TEXHEAD_BL_RESERVED_HEADER_VERSION MW(88:88) +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVCB97_TEXHEAD_BL_RESERVED2A MW(95:93) +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_WIDTH MW(98:96) +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT MW(101:99) +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH MW(104:102) +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_BL_RESERVED3Y MW(105:105) +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS MW(108:106) +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_BL_GOB3D MW(109:109) +#define NVCB97_TEXHEAD_BL_RESERVED3Z MW(111:110) +#define NVCB97_TEXHEAD_BL_LOD_ANISO_QUALITY2 MW(112:112) +#define NVCB97_TEXHEAD_BL_LOD_ANISO_QUALITY MW(113:113) +#define NVCB97_TEXHEAD_BL_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_BL_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_BL_LOD_ISO_QUALITY MW(114:114) +#define NVCB97_TEXHEAD_BL_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_BL_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_BL_ANISO_SPREAD_SCALE MW(121:117) +#define NVCB97_TEXHEAD_BL_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVCB97_TEXHEAD_BL_DEPTH_TEXTURE MW(123:123) +#define NVCB97_TEXHEAD_BL_MAX_MIP_LEVEL MW(127:124) +#define NVCB97_TEXHEAD_BL_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_BL_DEPTH_MINUS_ONE_BIT14 MW(145:145) +#define NVCB97_TEXHEAD_BL_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVCB97_TEXHEAD_BL_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVCB97_TEXHEAD_BL_S_R_G_B_CONVERSION MW(150:150) +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE MW(154:151) +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_BL_SECTOR_PROMOTION MW(156:155) +#define NVCB97_TEXHEAD_BL_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_BL_BORDER_SIZE MW(159:157) +#define NVCB97_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVCB97_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVCB97_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVCB97_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVCB97_TEXHEAD_BL_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVCB97_TEXHEAD_BL_HEIGHT_MINUS_ONE MW(175:160) +#define NVCB97_TEXHEAD_BL_DEPTH_MINUS_ONE MW(189:176) +#define NVCB97_TEXHEAD_BL_RESERVED5A MW(190:190) +#define NVCB97_TEXHEAD_BL_NORMALIZED_COORDS MW(191:191) +#define NVCB97_TEXHEAD_BL_RESERVED6Y MW(192:192) +#define NVCB97_TEXHEAD_BL_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_BL_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_BL_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_BL_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVCB97_TEXHEAD_BL_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT MW(235:232) +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVCB97_TEXHEAD_BL_MIN_LOD_CLAMP MW(247:236) +#define NVCB97_TEXHEAD_BL_RESERVED7Y MW(255:248) + + +/* +** Texture Header State Blocklinear Color Key + */ + +#define NVCB97_TEXHEAD_BLCK_COMPONENTS MW(6:0) +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE MW(9:7) +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE MW(12:10) +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE MW(15:13) +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE MW(18:16) +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE MW(21:19) +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE MW(24:22) +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE MW(27:25) +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE MW(30:28) +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_PACK_COMPONENTS MW(31:31) +#define NVCB97_TEXHEAD_BLCK_RESERVED1Y MW(36:32) +#define NVCB97_TEXHEAD_BLCK_GOB_DEPTH_OFFSET MW(38:37) +#define NVCB97_TEXHEAD_BLCK_RESERVED1X MW(40:39) +#define NVCB97_TEXHEAD_BLCK_ADDRESS_BITS31TO9 MW(63:41) +#define NVCB97_TEXHEAD_BLCK_ADDRESS_BITS48TO32 MW(80:64) +#define NVCB97_TEXHEAD_BLCK_RESERVED_ADDRESS MW(84:81) +#define NVCB97_TEXHEAD_BLCK_HEADER_VERSION MW(87:85) +#define NVCB97_TEXHEAD_BLCK_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVCB97_TEXHEAD_BLCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVCB97_TEXHEAD_BLCK_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVCB97_TEXHEAD_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVCB97_TEXHEAD_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVCB97_TEXHEAD_BLCK_RESERVED_HEADER_VERSION MW(88:88) +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVCB97_TEXHEAD_BLCK_RESERVED2A MW(95:93) +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_WIDTH MW(98:96) +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT MW(101:99) +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH MW(104:102) +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_BLCK_RESERVED3Y MW(105:105) +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS MW(108:106) +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_BLCK_GOB3D MW(109:109) +#define NVCB97_TEXHEAD_BLCK_RESERVED3Z MW(111:110) +#define NVCB97_TEXHEAD_BLCK_LOD_ANISO_QUALITY2 MW(112:112) +#define NVCB97_TEXHEAD_BLCK_LOD_ANISO_QUALITY MW(113:113) +#define NVCB97_TEXHEAD_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_BLCK_LOD_ISO_QUALITY MW(114:114) +#define NVCB97_TEXHEAD_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_ANISO_SPREAD_SCALE MW(121:117) +#define NVCB97_TEXHEAD_BLCK_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVCB97_TEXHEAD_BLCK_DEPTH_TEXTURE MW(123:123) +#define NVCB97_TEXHEAD_BLCK_MAX_MIP_LEVEL MW(127:124) +#define NVCB97_TEXHEAD_BLCK_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_BLCK_DEPTH_MINUS_ONE_BIT14 MW(145:145) +#define NVCB97_TEXHEAD_BLCK_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVCB97_TEXHEAD_BLCK_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVCB97_TEXHEAD_BLCK_S_R_G_B_CONVERSION MW(150:150) +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE MW(154:151) +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_BLCK_SECTOR_PROMOTION MW(156:155) +#define NVCB97_TEXHEAD_BLCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_BLCK_BORDER_SIZE MW(159:157) +#define NVCB97_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVCB97_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVCB97_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVCB97_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVCB97_TEXHEAD_BLCK_HEIGHT_MINUS_ONE MW(175:160) +#define NVCB97_TEXHEAD_BLCK_DEPTH_MINUS_ONE MW(189:176) +#define NVCB97_TEXHEAD_BLCK_RESERVED5A MW(190:190) +#define NVCB97_TEXHEAD_BLCK_NORMALIZED_COORDS MW(191:191) +#define NVCB97_TEXHEAD_BLCK_COLOR_KEY_OP MW(192:192) +#define NVCB97_TEXHEAD_BLCK_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_BLCK_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_BLCK_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Header State One-D Buffer + */ + +#define NVCB97_TEXHEAD_1D_COMPONENTS MW(6:0) +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE MW(9:7) +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE MW(12:10) +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE MW(15:13) +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE MW(18:16) +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_X_SOURCE MW(21:19) +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_Y_SOURCE MW(24:22) +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_Z_SOURCE MW(27:25) +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_W_SOURCE MW(30:28) +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_PACK_COMPONENTS MW(31:31) +#define NVCB97_TEXHEAD_1D_ADDRESS_BITS31TO0 MW(63:32) +#define NVCB97_TEXHEAD_1D_ADDRESS_BITS48TO32 MW(80:64) +#define NVCB97_TEXHEAD_1D_RESERVED_ADDRESS MW(84:81) +#define NVCB97_TEXHEAD_1D_HEADER_VERSION MW(87:85) +#define NVCB97_TEXHEAD_1D_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVCB97_TEXHEAD_1D_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVCB97_TEXHEAD_1D_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVCB97_TEXHEAD_1D_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVCB97_TEXHEAD_1D_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVCB97_TEXHEAD_1D_RESERVED_HEADER_VERSION MW(88:88) +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVCB97_TEXHEAD_1D_RESERVED2A MW(95:93) +#define NVCB97_TEXHEAD_1D_WIDTH_MINUS_ONE_BITS31TO16 MW(111:96) +#define NVCB97_TEXHEAD_1D_RESERVED3X MW(127:112) +#define NVCB97_TEXHEAD_1D_WIDTH_MINUS_ONE_BITS15TO0 MW(143:128) +#define NVCB97_TEXHEAD_1D_RESERVED4X MW(149:144) +#define NVCB97_TEXHEAD_1D_S_R_G_B_CONVERSION MW(150:150) +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE MW(154:151) +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_1D_SECTOR_PROMOTION MW(156:155) +#define NVCB97_TEXHEAD_1D_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_1D_RESERVED4Y MW(159:157) +#define NVCB97_TEXHEAD_1D_RESERVED5X MW(189:160) +#define NVCB97_TEXHEAD_1D_RESERVED5A MW(190:190) +#define NVCB97_TEXHEAD_1D_RESERVED5Y MW(191:191) +#define NVCB97_TEXHEAD_1D_RESERVED6X MW(223:192) +#define NVCB97_TEXHEAD_1D_RESERVED7X MW(255:224) + + +/* +** Texture Header State Pitch + */ + +#define NVCB97_TEXHEAD_PITCH_COMPONENTS MW(6:0) +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE MW(9:7) +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE MW(12:10) +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE MW(15:13) +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE MW(18:16) +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE MW(21:19) +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE MW(24:22) +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE MW(27:25) +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE MW(30:28) +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_PACK_COMPONENTS MW(31:31) +#define NVCB97_TEXHEAD_PITCH_RESERVED1A MW(36:32) +#define NVCB97_TEXHEAD_PITCH_ADDRESS_BITS31TO5 MW(63:37) +#define NVCB97_TEXHEAD_PITCH_ADDRESS_BITS48TO32 MW(80:64) +#define NVCB97_TEXHEAD_PITCH_RESERVED_ADDRESS MW(84:81) +#define NVCB97_TEXHEAD_PITCH_HEADER_VERSION MW(87:85) +#define NVCB97_TEXHEAD_PITCH_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVCB97_TEXHEAD_PITCH_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVCB97_TEXHEAD_PITCH_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVCB97_TEXHEAD_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVCB97_TEXHEAD_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVCB97_TEXHEAD_PITCH_RESERVED_HEADER_VERSION MW(88:88) +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVCB97_TEXHEAD_PITCH_RESERVED2A MW(95:93) +#define NVCB97_TEXHEAD_PITCH_PITCH_BITS20TO5 MW(111:96) +#define NVCB97_TEXHEAD_PITCH_LOD_ANISO_QUALITY2 MW(112:112) +#define NVCB97_TEXHEAD_PITCH_LOD_ANISO_QUALITY MW(113:113) +#define NVCB97_TEXHEAD_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_PITCH_LOD_ISO_QUALITY MW(114:114) +#define NVCB97_TEXHEAD_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_ANISO_SPREAD_SCALE MW(121:117) +#define NVCB97_TEXHEAD_PITCH_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVCB97_TEXHEAD_PITCH_DEPTH_TEXTURE MW(123:123) +#define NVCB97_TEXHEAD_PITCH_MAX_MIP_LEVEL MW(127:124) +#define NVCB97_TEXHEAD_PITCH_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_PITCH_PITCH_BIT21 MW(145:145) +#define NVCB97_TEXHEAD_PITCH_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVCB97_TEXHEAD_PITCH_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVCB97_TEXHEAD_PITCH_S_R_G_B_CONVERSION MW(150:150) +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE MW(154:151) +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_PITCH_SECTOR_PROMOTION MW(156:155) +#define NVCB97_TEXHEAD_PITCH_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_PITCH_BORDER_SIZE MW(159:157) +#define NVCB97_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVCB97_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVCB97_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVCB97_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVCB97_TEXHEAD_PITCH_HEIGHT_MINUS_ONE MW(175:160) +#define NVCB97_TEXHEAD_PITCH_DEPTH_MINUS_ONE MW(189:176) +#define NVCB97_TEXHEAD_PITCH_RESERVED5A MW(190:190) +#define NVCB97_TEXHEAD_PITCH_NORMALIZED_COORDS MW(191:191) +#define NVCB97_TEXHEAD_PITCH_RESERVED6Y MW(192:192) +#define NVCB97_TEXHEAD_PITCH_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_PITCH_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_PITCH_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVCB97_TEXHEAD_PITCH_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT MW(235:232) +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVCB97_TEXHEAD_PITCH_MIN_LOD_CLAMP MW(247:236) +#define NVCB97_TEXHEAD_PITCH_RESERVED7Y MW(255:248) + + +/* +** Texture Header State Pitch Color Key + */ + +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS MW(6:0) +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE MW(9:7) +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE MW(12:10) +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE MW(15:13) +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE MW(18:16) +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE MW(21:19) +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE MW(24:22) +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE MW(27:25) +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE MW(30:28) +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_PACK_COMPONENTS MW(31:31) +#define NVCB97_TEXHEAD_PITCHCK_RESERVED1A MW(36:32) +#define NVCB97_TEXHEAD_PITCHCK_ADDRESS_BITS31TO5 MW(63:37) +#define NVCB97_TEXHEAD_PITCHCK_ADDRESS_BITS48TO32 MW(80:64) +#define NVCB97_TEXHEAD_PITCHCK_RESERVED_ADDRESS MW(84:81) +#define NVCB97_TEXHEAD_PITCHCK_HEADER_VERSION MW(87:85) +#define NVCB97_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_RESERVED_HEADER_VERSION MW(88:88) +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVCB97_TEXHEAD_PITCHCK_RESERVED2A MW(95:93) +#define NVCB97_TEXHEAD_PITCHCK_PITCH_BITS20TO5 MW(111:96) +#define NVCB97_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY2 MW(112:112) +#define NVCB97_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY MW(113:113) +#define NVCB97_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_LOD_ISO_QUALITY MW(114:114) +#define NVCB97_TEXHEAD_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_SPREAD_SCALE MW(121:117) +#define NVCB97_TEXHEAD_PITCHCK_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVCB97_TEXHEAD_PITCHCK_DEPTH_TEXTURE MW(123:123) +#define NVCB97_TEXHEAD_PITCHCK_MAX_MIP_LEVEL MW(127:124) +#define NVCB97_TEXHEAD_PITCHCK_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_PITCHCK_PITCH_BIT21 MW(145:145) +#define NVCB97_TEXHEAD_PITCHCK_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVCB97_TEXHEAD_PITCHCK_S_R_G_B_CONVERSION MW(150:150) +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE MW(154:151) +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_PITCHCK_SECTOR_PROMOTION MW(156:155) +#define NVCB97_TEXHEAD_PITCHCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_BORDER_SIZE MW(159:157) +#define NVCB97_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_HEIGHT_MINUS_ONE MW(175:160) +#define NVCB97_TEXHEAD_PITCHCK_DEPTH_MINUS_ONE MW(189:176) +#define NVCB97_TEXHEAD_PITCHCK_RESERVED5A MW(190:190) +#define NVCB97_TEXHEAD_PITCHCK_NORMALIZED_COORDS MW(191:191) +#define NVCB97_TEXHEAD_PITCHCK_COLOR_KEY_OP MW(192:192) +#define NVCB97_TEXHEAD_PITCHCK_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_PITCHCK_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Header V2 Blocklinear + */ + +#define NVCB97_TEXHEAD_V2_BL_RESERVED0A MW(3:0) +#define NVCB97_TEXHEAD_V2_BL_GOB_DEPTH_OFFSET MW(8:4) +#define NVCB97_TEXHEAD_V2_BL_ADDRESS_BITS31TO9 MW(31:9) +#define NVCB97_TEXHEAD_V2_BL_ADDRESS_BITS56TO32 MW(56:32) +#define NVCB97_TEXHEAD_V2_BL_RESERVED1A MW(63:57) +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_WIDTH MW(66:64) +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT MW(69:67) +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH MW(72:70) +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_RESERVED3Y MW(73:73) +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS MW(76:74) +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_GOB3D MW(77:77) +#define NVCB97_TEXHEAD_V2_BL_RESERVED2Z MW(79:78) +#define NVCB97_TEXHEAD_V2_BL_LOD_ANISO_QUALITY2 MW(80:80) +#define NVCB97_TEXHEAD_V2_BL_LOD_ANISO_QUALITY MW(81:81) +#define NVCB97_TEXHEAD_V2_BL_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_LOD_ISO_QUALITY MW(82:82) +#define NVCB97_TEXHEAD_V2_BL_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_MODIFIER MW(84:83) +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_ANISO_SPREAD_SCALE MW(89:85) +#define NVCB97_TEXHEAD_V2_BL_USE_HEADER_OPT_CONTROL MW(90:90) +#define NVCB97_TEXHEAD_V2_BL_DEPTH_TEXTURE MW(91:91) +#define NVCB97_TEXHEAD_V2_BL_MAX_MIP_LEVEL MW(95:92) +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE MW(98:96) +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE MW(101:99) +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE MW(104:102) +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE MW(107:105) +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE MW(111:108) +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_UNORM 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_SNORM 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_FLOAT 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_SGNRGB 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_SGNA 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_DSDT 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_UINT 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_SINT 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_ZS 0x00000008 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_SZ 0x00000009 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_ZFS 0x0000000a +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS MW(118:112) +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_V2_BL_PACK_COMPONENTS MW(119:119) +#define NVCB97_TEXHEAD_V2_BL_RESERVED3A MW(123:120) +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION MW(127:124) +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION_SELECT_PITCH_COLOR_KEY_V2 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION_SELECT_PITCH_V2 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION_SELECT_BLOCKLINEAR_V2 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY_V2 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION_SELECT_ONE_D_RAW_TYPED 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION_SELECT_ONE_D_STRUCT_BUF 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_V2_BL_NORMALIZED_COORDS MW(145:145) +#define NVCB97_TEXHEAD_V2_BL_ANISO_SPREAD_MAX_LOG2 MW(148:146) +#define NVCB97_TEXHEAD_V2_BL_S_R_G_B_CONVERSION MW(149:149) +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE MW(153:150) +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_V2_BL_SECTOR_PROMOTION MW(155:154) +#define NVCB97_TEXHEAD_V2_BL_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_BORDER_SOURCE MW(156:156) +#define NVCB97_TEXHEAD_V2_BL_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_RESERVED4A MW(159:157) +#define NVCB97_TEXHEAD_V2_BL_HEIGHT_MINUS_ONE MW(176:160) +#define NVCB97_TEXHEAD_V2_BL_DEPTH_MINUS_ONE MW(191:177) +#define NVCB97_TEXHEAD_V2_BL_RESERVED6Y MW(192:192) +#define NVCB97_TEXHEAD_V2_BL_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_V2_BL_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_V2_BL_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVCB97_TEXHEAD_V2_BL_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT MW(235:232) +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVCB97_TEXHEAD_V2_BL_MIN_LOD_CLAMP MW(247:236) +#define NVCB97_TEXHEAD_V2_BL_RESERVED7Y MW(255:248) + + +/* +** Texture Header V2 Blocklinear Color Key + */ + +#define NVCB97_TEXHEAD_V2_BLCK_RESERVED0A MW(3:0) +#define NVCB97_TEXHEAD_V2_BLCK_GOB_DEPTH_OFFSET MW(8:4) +#define NVCB97_TEXHEAD_V2_BLCK_ADDRESS_BITS31TO9 MW(31:9) +#define NVCB97_TEXHEAD_V2_BLCK_ADDRESS_BITS56TO32 MW(56:32) +#define NVCB97_TEXHEAD_V2_BLCK_RESERVED1A MW(63:57) +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_WIDTH MW(66:64) +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT MW(69:67) +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH MW(72:70) +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_RESERVED3Y MW(73:73) +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS MW(76:74) +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_GOB3D MW(77:77) +#define NVCB97_TEXHEAD_V2_BLCK_RESERVED2Z MW(79:78) +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ANISO_QUALITY2 MW(80:80) +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ANISO_QUALITY MW(81:81) +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ISO_QUALITY MW(82:82) +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_MODIFIER MW(84:83) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_SPREAD_SCALE MW(89:85) +#define NVCB97_TEXHEAD_V2_BLCK_USE_HEADER_OPT_CONTROL MW(90:90) +#define NVCB97_TEXHEAD_V2_BLCK_DEPTH_TEXTURE MW(91:91) +#define NVCB97_TEXHEAD_V2_BLCK_MAX_MIP_LEVEL MW(95:92) +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE MW(98:96) +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE MW(101:99) +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE MW(104:102) +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE MW(107:105) +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE MW(111:108) +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_UNORM 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_SNORM 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_FLOAT 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_SGNRGB 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_SGNA 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_DSDT 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_UINT 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_SINT 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_ZS 0x00000008 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_SZ 0x00000009 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_ZFS 0x0000000a +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS MW(118:112) +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_V2_BLCK_PACK_COMPONENTS MW(119:119) +#define NVCB97_TEXHEAD_V2_BLCK_RESERVED3A MW(123:120) +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION MW(127:124) +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY_V2 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION_SELECT_PITCH_V2 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR_V2 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY_V2 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION_SELECT_ONE_D_RAW_TYPED 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION_SELECT_ONE_D_STRUCT_BUF 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_V2_BLCK_NORMALIZED_COORDS MW(145:145) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_SPREAD_MAX_LOG2 MW(148:146) +#define NVCB97_TEXHEAD_V2_BLCK_S_R_G_B_CONVERSION MW(149:149) +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE MW(153:150) +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_V2_BLCK_SECTOR_PROMOTION MW(155:154) +#define NVCB97_TEXHEAD_V2_BLCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_BORDER_SOURCE MW(156:156) +#define NVCB97_TEXHEAD_V2_BLCK_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_RESERVED4A MW(159:157) +#define NVCB97_TEXHEAD_V2_BLCK_HEIGHT_MINUS_ONE MW(176:160) +#define NVCB97_TEXHEAD_V2_BLCK_DEPTH_MINUS_ONE MW(191:177) +#define NVCB97_TEXHEAD_V2_BLCK_COLOR_KEY_OP MW(192:192) +#define NVCB97_TEXHEAD_V2_BLCK_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_V2_BLCK_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Header V2 One-D Raw Typed + */ + +#define NVCB97_TEXHEAD_V2_1DRT_ADDRESS_BITS31TO0 MW(31:0) +#define NVCB97_TEXHEAD_V2_1DRT_ADDRESS_BITS63TO32 MW(63:32) +#define NVCB97_TEXHEAD_V2_1DRT_WIDTH_MINUS_ONE MW(95:64) +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE MW(98:96) +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE MW(101:99) +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE MW(104:102) +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE MW(107:105) +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE MW(111:108) +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_UNORM 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_SNORM 0x00000001 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_FLOAT 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_SGNRGB 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_SGNA 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_DSDT 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_UINT 0x00000006 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_SINT 0x00000007 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_ZS 0x00000008 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_SZ 0x00000009 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_ZFS 0x0000000a +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS MW(117:112) +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_INVALID 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_G8R24 0x0000000d +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_G24R8 0x0000000e +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R32 0x0000000f +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_G8R8 0x00000018 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R16 0x0000001b +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R8 0x0000001d +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_G4R4 0x0000001e +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_X8B8G8R8_SRGB 0x00000031 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_A8B8G8R8_SRGB 0x00000032 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_G8R8_SRGB 0x00000033 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R8_SRGB 0x00000034 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZESV2_CS_BITFIELD_SIZE 0x0000003f +#define NVCB97_TEXHEAD_V2_1DRT_SECTOR_PROMOTION MW(119:118) +#define NVCB97_TEXHEAD_V2_1DRT_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_V2_1DRT_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_RESERVED3A MW(123:120) +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION MW(127:124) +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION_SELECT_PITCH_COLOR_KEY_V2 0x00000001 +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION_SELECT_PITCH_V2 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION_SELECT_BLOCKLINEAR_V2 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY_V2 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION_SELECT_ONE_D_RAW_TYPED 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION_SELECT_ONE_D_STRUCT_BUF 0x00000006 +#define NVCB97_TEXHEAD_V2_1DRT_RESERVED4X MW(156:128) +#define NVCB97_TEXHEAD_V2_1DRT_RESERVED4A MW(159:157) +#define NVCB97_TEXHEAD_V2_1DRT_RESERVED5X MW(191:160) +#define NVCB97_TEXHEAD_V2_1DRT_RESERVED6X MW(223:192) +#define NVCB97_TEXHEAD_V2_1DRT_RESERVED7X MW(255:224) + + +/* +** Texture Header V2 One-D Structured Buffer + */ + +#define NVCB97_TEXHEAD_V2_1DSB_ADDRESS_BITS31TO0 MW(31:0) +#define NVCB97_TEXHEAD_V2_1DSB_ADDRESS_BITS63TO32 MW(63:32) +#define NVCB97_TEXHEAD_V2_1DSB_WIDTH_MINUS_ONE MW(95:64) +#define NVCB97_TEXHEAD_V2_1DSB_STRIDE MW(107:96) +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE MW(111:108) +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_UNORM 0x00000000 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_SNORM 0x00000001 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_FLOAT 0x00000002 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_SGNRGB 0x00000003 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_SGNA 0x00000004 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_DSDT 0x00000005 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_UINT 0x00000006 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_SINT 0x00000007 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_ZS 0x00000008 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_SZ 0x00000009 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_ZFS 0x0000000a +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS MW(117:112) +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_INVALID 0x00000000 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_G8R24 0x0000000d +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_G24R8 0x0000000e +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R32 0x0000000f +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_G8R8 0x00000018 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R16 0x0000001b +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R8 0x0000001d +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_G4R4 0x0000001e +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_X8B8G8R8_SRGB 0x00000031 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_A8B8G8R8_SRGB 0x00000032 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_G8R8_SRGB 0x00000033 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R8_SRGB 0x00000034 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZESV2_CS_BITFIELD_SIZE 0x0000003f +#define NVCB97_TEXHEAD_V2_1DSB_SECTOR_PROMOTION MW(119:118) +#define NVCB97_TEXHEAD_V2_1DSB_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_V2_1DSB_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_V2_1DSB_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_V2_1DSB_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_V2_1DSB_RESERVED3A MW(123:120) +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION MW(127:124) +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION_SELECT_PITCH_COLOR_KEY_V2 0x00000001 +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION_SELECT_PITCH_V2 0x00000002 +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION_SELECT_BLOCKLINEAR_V2 0x00000003 +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY_V2 0x00000004 +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION_SELECT_ONE_D_RAW_TYPED 0x00000005 +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION_SELECT_ONE_D_STRUCT_BUF 0x00000006 +#define NVCB97_TEXHEAD_V2_1DSB_RESERVED4X MW(156:128) +#define NVCB97_TEXHEAD_V2_1DSB_RESERVED4A MW(159:157) +#define NVCB97_TEXHEAD_V2_1DSB_RESERVED5X MW(191:160) +#define NVCB97_TEXHEAD_V2_1DSB_RESERVED6X MW(223:192) +#define NVCB97_TEXHEAD_V2_1DSB_RESERVED7X MW(255:224) + + +/* +** Texture Header V2 Pitch + */ + +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED0A MW(3:0) +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED0X MW(4:4) +#define NVCB97_TEXHEAD_V2_PITCH_ADDRESS_BITS31TO5 MW(31:5) +#define NVCB97_TEXHEAD_V2_PITCH_ADDRESS_BITS56TO32 MW(56:32) +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED1A MW(63:57) +#define NVCB97_TEXHEAD_V2_PITCH_PITCH_BITS21TO5 MW(80:64) +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ANISO_QUALITY2 MW(81:81) +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ANISO_QUALITY MW(82:82) +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ISO_QUALITY MW(83:83) +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_MODIFIER MW(85:84) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_SPREAD_SCALE MW(90:86) +#define NVCB97_TEXHEAD_V2_PITCH_DEPTH_TEXTURE MW(91:91) +#define NVCB97_TEXHEAD_V2_PITCH_MAX_MIP_LEVEL MW(95:92) +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE MW(98:96) +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE MW(101:99) +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE MW(104:102) +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE MW(107:105) +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE MW(111:108) +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_UNORM 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_SNORM 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_FLOAT 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_SGNRGB 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_SGNA 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_DSDT 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_UINT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_SINT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_ZS 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_SZ 0x00000009 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_ZFS 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS MW(118:112) +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_V2_PITCH_PACK_COMPONENTS MW(119:119) +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED3A MW(123:120) +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION MW(127:124) +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION_SELECT_PITCH_COLOR_KEY_V2 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION_SELECT_PITCH_V2 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR_V2 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY_V2 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION_SELECT_ONE_D_RAW_TYPED 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION_SELECT_ONE_D_STRUCT_BUF 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_V2_PITCH_NORMALIZED_COORDS MW(145:145) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_SPREAD_MAX_LOG2 MW(148:146) +#define NVCB97_TEXHEAD_V2_PITCH_S_R_G_B_CONVERSION MW(149:149) +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE MW(153:150) +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_V2_PITCH_SECTOR_PROMOTION MW(155:154) +#define NVCB97_TEXHEAD_V2_PITCH_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_BORDER_SOURCE MW(156:156) +#define NVCB97_TEXHEAD_V2_PITCH_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED4A MW(159:157) +#define NVCB97_TEXHEAD_V2_PITCH_HEIGHT_MINUS_ONE MW(176:160) +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED5Y MW(191:177) +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED6Y MW(192:192) +#define NVCB97_TEXHEAD_V2_PITCH_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_V2_PITCH_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVCB97_TEXHEAD_V2_PITCH_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT MW(235:232) +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVCB97_TEXHEAD_V2_PITCH_MIN_LOD_CLAMP MW(247:236) +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED7Y MW(255:248) + + +/* +** Texture Header V2 Pitch Color Key + */ + +#define NVCB97_TEXHEAD_V2_PITCHCK_RESERVED0A MW(3:0) +#define NVCB97_TEXHEAD_V2_PITCHCK_RESERVED0X MW(4:4) +#define NVCB97_TEXHEAD_V2_PITCHCK_ADDRESS_BITS31TO5 MW(31:5) +#define NVCB97_TEXHEAD_V2_PITCHCK_ADDRESS_BITS56TO32 MW(56:32) +#define NVCB97_TEXHEAD_V2_PITCHCK_RESERVED1A MW(63:57) +#define NVCB97_TEXHEAD_V2_PITCHCK_PITCH_BITS21TO5 MW(80:64) +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ANISO_QUALITY2 MW(81:81) +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ANISO_QUALITY MW(82:82) +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ISO_QUALITY MW(83:83) +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER MW(85:84) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_SPREAD_SCALE MW(90:86) +#define NVCB97_TEXHEAD_V2_PITCHCK_DEPTH_TEXTURE MW(91:91) +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_MIP_LEVEL MW(95:92) +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE MW(98:96) +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE MW(101:99) +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE MW(104:102) +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE MW(107:105) +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE MW(111:108) +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_UNORM 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_SNORM 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_FLOAT 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_SGNRGB 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_SGNA 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_DSDT 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_UINT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_SINT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_ZS 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_SZ 0x00000009 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_ZFS 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS MW(118:112) +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_V2_PITCHCK_PACK_COMPONENTS MW(119:119) +#define NVCB97_TEXHEAD_V2_PITCHCK_RESERVED3A MW(123:120) +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION MW(127:124) +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY_V2 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION_SELECT_PITCH_V2 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR_V2 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY_V2 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION_SELECT_ONE_D_RAW_TYPED 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION_SELECT_ONE_D_STRUCT_BUF 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_V2_PITCHCK_NORMALIZED_COORDS MW(145:145) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_SPREAD_MAX_LOG2 MW(148:146) +#define NVCB97_TEXHEAD_V2_PITCHCK_S_R_G_B_CONVERSION MW(149:149) +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE MW(153:150) +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_V2_PITCHCK_SECTOR_PROMOTION MW(155:154) +#define NVCB97_TEXHEAD_V2_PITCHCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_BORDER_SOURCE MW(156:156) +#define NVCB97_TEXHEAD_V2_PITCHCK_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_RESERVED4A MW(159:157) +#define NVCB97_TEXHEAD_V2_PITCHCK_HEIGHT_MINUS_ONE MW(176:160) +#define NVCB97_TEXHEAD_V2_PITCHCK_RESERVED5Y MW(191:177) +#define NVCB97_TEXHEAD_V2_PITCHCK_COLOR_KEY_OP MW(192:192) +#define NVCB97_TEXHEAD_V2_PITCHCK_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_V2_PITCHCK_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Sampler State + */ + +#define NVCB97_TEXSAMP0_ADDRESS_U 2:0 +#define NVCB97_TEXSAMP0_ADDRESS_U_WRAP 0x00000000 +#define NVCB97_TEXSAMP0_ADDRESS_U_MIRROR 0x00000001 +#define NVCB97_TEXSAMP0_ADDRESS_U_CLAMP_TO_EDGE 0x00000002 +#define NVCB97_TEXSAMP0_ADDRESS_U_BORDER 0x00000003 +#define NVCB97_TEXSAMP0_ADDRESS_U_CLAMP_OGL 0x00000004 +#define NVCB97_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVCB97_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_BORDER 0x00000006 +#define NVCB97_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVCB97_TEXSAMP0_ADDRESS_V 5:3 +#define NVCB97_TEXSAMP0_ADDRESS_V_WRAP 0x00000000 +#define NVCB97_TEXSAMP0_ADDRESS_V_MIRROR 0x00000001 +#define NVCB97_TEXSAMP0_ADDRESS_V_CLAMP_TO_EDGE 0x00000002 +#define NVCB97_TEXSAMP0_ADDRESS_V_BORDER 0x00000003 +#define NVCB97_TEXSAMP0_ADDRESS_V_CLAMP_OGL 0x00000004 +#define NVCB97_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVCB97_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_BORDER 0x00000006 +#define NVCB97_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVCB97_TEXSAMP0_ADDRESS_P 8:6 +#define NVCB97_TEXSAMP0_ADDRESS_P_WRAP 0x00000000 +#define NVCB97_TEXSAMP0_ADDRESS_P_MIRROR 0x00000001 +#define NVCB97_TEXSAMP0_ADDRESS_P_CLAMP_TO_EDGE 0x00000002 +#define NVCB97_TEXSAMP0_ADDRESS_P_BORDER 0x00000003 +#define NVCB97_TEXSAMP0_ADDRESS_P_CLAMP_OGL 0x00000004 +#define NVCB97_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVCB97_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_BORDER 0x00000006 +#define NVCB97_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE 9:9 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC 12:10 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_NEVER 0x00000000 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_LESS 0x00000001 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_EQUAL 0x00000002 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_LEQUAL 0x00000003 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_GREATER 0x00000004 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_NOTEQUAL 0x00000005 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_GEQUAL 0x00000006 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_ALWAYS 0x00000007 +#define NVCB97_TEXSAMP0_S_R_G_B_CONVERSION 13:13 +#define NVCB97_TEXSAMP0_RESERVED0A 16:14 +#define NVCB97_TEXSAMP0_RESERVED0B 19:17 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY 22:20 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXSAMP0_FORCED_INVALID 31:31 +#define NVCB97_TEXSAMP1_MAG_FILTER 2:0 +#define NVCB97_TEXSAMP1_MAG_FILTER_MAG_POINT 0x00000001 +#define NVCB97_TEXSAMP1_MAG_FILTER_MAG_LINEAR 0x00000002 +#define NVCB97_TEXSAMP1_MAG_FILTER_VCAA_4_TAP 0x00000003 +#define NVCB97_TEXSAMP1_MAG_FILTER_VCAA_8_TAP 0x00000004 +#define NVCB97_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP 3:3 +#define NVCB97_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP_INTEGER_AND_FRACTION 0x00000000 +#define NVCB97_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP_INTEGER_ONLY 0x00000001 +#define NVCB97_TEXSAMP1_MIN_FILTER 5:4 +#define NVCB97_TEXSAMP1_MIN_FILTER_MIN_POINT 0x00000001 +#define NVCB97_TEXSAMP1_MIN_FILTER_MIN_LINEAR 0x00000002 +#define NVCB97_TEXSAMP1_MIN_FILTER_MIN_ANISO 0x00000003 +#define NVCB97_TEXSAMP1_MIP_FILTER 7:6 +#define NVCB97_TEXSAMP1_MIP_FILTER_MIP_NONE 0x00000001 +#define NVCB97_TEXSAMP1_MIP_FILTER_MIP_POINT 0x00000002 +#define NVCB97_TEXSAMP1_MIP_FILTER_MIP_LINEAR 0x00000003 +#define NVCB97_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING 9:8 +#define NVCB97_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_USE_WRAP 0x00000000 +#define NVCB97_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_OVERRIDE_WRAP 0x00000001 +#define NVCB97_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_AUTO_SPAN_SEAM 0x00000002 +#define NVCB97_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_AUTO_CROSS_SEAM 0x00000003 +#define NVCB97_TEXSAMP1_REDUCTION_FILTER 11:10 +#define NVCB97_TEXSAMP1_REDUCTION_FILTER_RED_NONE 0x00000000 +#define NVCB97_TEXSAMP1_REDUCTION_FILTER_RED_MINIMUM 0x00000001 +#define NVCB97_TEXSAMP1_REDUCTION_FILTER_RED_MAXIMUM 0x00000002 +#define NVCB97_TEXSAMP1_MIP_LOD_BIAS 24:12 +#define NVCB97_TEXSAMP1_FLOAT_COORD_NORMALIZATION 25:25 +#define NVCB97_TEXSAMP1_FLOAT_COORD_NORMALIZATION_USE_HEADER_SETTING 0x00000000 +#define NVCB97_TEXSAMP1_FLOAT_COORD_NORMALIZATION_FORCE_UNNORMALIZED_COORDS 0x00000001 +#define NVCB97_TEXSAMP1_TRILIN_OPT 30:26 +#define NVCB97_TEXSAMP2_MIN_LOD_CLAMP 11:0 +#define NVCB97_TEXSAMP2_MAX_LOD_CLAMP 23:12 +#define NVCB97_TEXSAMP2_S_R_G_B_BORDER_COLOR_R 31:24 +#define NVCB97_TEXSAMP3_RESERVED12 11:0 +#define NVCB97_TEXSAMP3_S_R_G_B_BORDER_COLOR_G 19:12 +#define NVCB97_TEXSAMP3_S_R_G_B_BORDER_COLOR_B 27:20 +#define NVCB97_TEXSAMP4_BORDER_COLOR_R 31:0 +#define NVCB97_TEXSAMP5_BORDER_COLOR_G 31:0 +#define NVCB97_TEXSAMP6_BORDER_COLOR_B 31:0 +#define NVCB97_TEXSAMP7_BORDER_COLOR_A 31:0 + + + +#endif // #ifndef __CLCB97TEX_H__ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clcbc0.h b/userspace/sdks/nv525/nvidia/inc/class/clcbc0.h new file mode 100644 index 0000000..bed5e94 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clcbc0.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clcbc0_h__ +#define __gh100_clcbc0_h__ +#define HOPPER_COMPUTE_A 0xCBC0 +#endif // __gh100_clcbc0_h__ diff --git a/userspace/sdks/nv525/nvidia/inc/class/clcbca.h b/userspace/sdks/nv525/nvidia/inc/class/clcbca.h new file mode 100644 index 0000000..4570cc9 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/clcbca.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _CLCBCA_H_ +#define _CLCBCA_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV_COUNTER_COLLECTION_UNIT (0x0000CBCA) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _CLCBCA_H_ diff --git a/userspace/sdks/nv525/nvidia/inc/class/cld0b7.h b/userspace/sdks/nv525/nvidia/inc/class/cld0b7.h new file mode 100644 index 0000000..d7c044d --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/class/cld0b7.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef cld0b7_h +#define cld0b7_h + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVD0B7_VIDEO_ENCODER (0x0000D0B7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // cld0b7_h + diff --git a/userspace/sdks/nv525/nvidia/inc/cpuopsys.h b/userspace/sdks/nv525/nvidia/inc/cpuopsys.h new file mode 100644 index 0000000..230c7b5 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/cpuopsys.h @@ -0,0 +1,422 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! \brief + * Define compile time symbols for CPU type and operating system type. + * This file should only contain preprocessor commands so that + * there are no dependencies on other files. + * + * cpuopsys.h + * + * Copyright (c) 2001, Nvidia Corporation. All rights reserved. + */ + +/*! + * Uniform names are defined for compile time options to distinguish + * CPU types and Operating systems. + * Distinctions between CPU and OpSys should be orthogonal. + * + * These uniform names have initially been defined by keying off the + * makefile/build names defined for builds in the OpenGL group. + * Getting the uniform names defined for other builds may require + * different qualifications. + * + * The file is placed here to allow for the possibility of all driver + * components using the same naming convention for conditional compilation. + */ + +#ifndef CPUOPSYS_H +#define CPUOPSYS_H + +/*****************************************************************************/ +/* Define all OS/CPU-Chip related symbols */ + +/* ***** WINDOWS variations */ +#if defined(_WIN32) || defined(_WIN16) +# define NV_WINDOWS + +# if defined(_WIN32_WINNT) +# define NV_WINDOWS_NT +# elif defined(_WIN32_WCE) +# define NV_WINDOWS_CE +# else +# define NV_WINDOWS_9X +# endif +#endif /* _WIN32 || defined(_WIN16) */ + +/* ***** Unix variations */ +#if defined(__linux__) && !defined(NV_LINUX) && !defined(NV_VMWARE) +# define NV_LINUX +#endif /* defined(__linux__) */ + +#if defined(__VMWARE__) && !defined(NV_VMWARE) +# define NV_VMWARE +#endif /* defined(__VMWARE__) */ + +/* SunOS + gcc */ +#if defined(__sun__) && defined(__svr4__) && !defined(NV_SUNOS) +# define NV_SUNOS +#endif /* defined(__sun__) && defined(__svr4__) */ + +/* SunOS + Sun Compiler (named SunPro, Studio or Forte) */ +#if defined(__SUNPRO_C) || defined(__SUNPRO_CC) +# define NV_SUNPRO_C +# define NV_SUNOS +#endif /* defined(_SUNPRO_C) || defined(__SUNPRO_CC) */ + +#if defined(__FreeBSD__) && !defined(NV_BSD) +# define NV_BSD +#endif /* defined(__FreeBSD__) */ + +/* XXXar don't define NV_UNIX on MacOSX or vxworks or QNX */ +#if (defined(__unix__) || defined(__unix) || defined(__INTEGRITY) ) && !defined(nvmacosx) && !defined(vxworks) && !defined(NV_UNIX) && !defined(__QNX__) && !defined(__QNXNTO__)/* XXX until removed from Makefiles */ +# define NV_UNIX +#endif /* defined(__unix__) */ + +#if (defined(__QNX__) || defined(__QNXNTO__)) && !defined(NV_QNX) +# define NV_QNX +#endif + +#if (defined(__ANDROID__) || defined(ANDROID)) && !defined(NV_ANDROID) +# define NV_ANDROID +#endif + +#if defined(DceCore) && !defined(NV_DCECORE) +# define NV_DCECORE +#endif + +/* ***** Apple variations */ +#if defined(macintosh) || defined(__APPLE__) +# define NV_MACINTOSH +# if defined(__MACH__) +# define NV_MACINTOSH_OSX +# else +# define NV_MACINTOSH_OS9 +# endif +# if defined(__LP64__) +# define NV_MACINTOSH_64 +# endif +#endif /* defined(macintosh) */ + +/* ***** VxWorks */ +/* Tornado 2.21 is gcc 2.96 and #defines __vxworks. */ +/* Tornado 2.02 is gcc 2.7.2 and doesn't define any OS symbol, so we rely on */ +/* the build system #defining vxworks. */ +#if defined(__vxworks) || defined(vxworks) +# define NV_VXWORKS +#endif + +/* ***** Integrity OS */ +#if defined(__INTEGRITY) +# if !defined(NV_INTEGRITY) +# define NV_INTEGRITY +# endif +#endif + +/* ***** Processor type variations */ +/* Note: The prefix NV_CPU_* is taken by Nvcm.h */ + +#if ((defined(_M_IX86) || defined(__i386__) || defined(__i386)) && !defined(NVCPU_X86)) /* XXX until removed from Makefiles */ +/* _M_IX86 for windows, __i386__ for Linux (or any x86 using gcc) */ +/* __i386 for Studio compiler on Solaris x86 */ +# define NVCPU_X86 /* any IA32 machine (not x86-64) */ +# define NVCPU_MIN_PAGE_SHIFT 12 +#endif + +#if defined(NV_LINUX) && defined(__ia64__) +# define NVCPU_IA64_LINUX /* any IA64 for Linux opsys */ +#endif +#if defined(NVCPU_IA64_WINDOWS) || defined(NVCPU_IA64_LINUX) || defined(IA64) +# define NVCPU_IA64 /* any IA64 for any opsys */ +#endif + +#if (defined(NV_MACINTOSH) && !(defined(__i386__) || defined(__x86_64__))) || defined(__PPC__) || defined(__ppc) +# if defined(__powerpc64__) && defined(__LITTLE_ENDIAN__) +# ifndef NVCPU_PPC64LE +# define NVCPU_PPC64LE /* PPC 64-bit little endian */ +# endif +# else +# ifndef NVCPU_PPC +# define NVCPU_PPC /* any non-PPC64LE PowerPC architecture */ +# endif +# ifndef NV_BIG_ENDIAN +# define NV_BIG_ENDIAN +# endif +# endif +# define NVCPU_FAMILY_PPC +#endif + +#if defined(__x86_64) || defined(AMD64) || defined(_M_AMD64) +# define NVCPU_X86_64 /* any x86-64 for any opsys */ +#endif + +#if defined(NVCPU_X86) || defined(NVCPU_X86_64) +# define NVCPU_FAMILY_X86 +#endif + +#if defined(__riscv) && (__riscv_xlen==64) +# define NVCPU_RISCV64 +# if defined(__nvriscv) +# define NVCPU_NVRISCV64 +# endif +#endif + +#if defined(__arm__) || defined(_M_ARM) +/* + * 32-bit instruction set on, e.g., ARMv7 or AArch32 execution state + * on ARMv8 + */ +# define NVCPU_ARM +# define NVCPU_MIN_PAGE_SHIFT 12 +#endif + +#if defined(__aarch64__) || defined(__ARM64__) || defined(_M_ARM64) +# define NVCPU_AARCH64 /* 64-bit A64 instruction set on ARMv8 */ +# define NVCPU_MIN_PAGE_SHIFT 12 +#endif + +#if defined(NVCPU_ARM) || defined(NVCPU_AARCH64) +# define NVCPU_FAMILY_ARM +#endif + +#if defined(__SH4__) +# ifndef NVCPU_SH4 +# define NVCPU_SH4 /* Renesas (formerly Hitachi) SH4 */ +# endif +# if defined NV_WINDOWS_CE +# define NVCPU_MIN_PAGE_SHIFT 12 +# endif +#endif + +/* For Xtensa processors */ +#if defined(__XTENSA__) +# define NVCPU_XTENSA +# if defined(__XTENSA_EB__) +# define NV_BIG_ENDIAN +# endif +#endif + + +/* + * Other flavors of CPU type should be determined at run-time. + * For example, an x86 architecture with/without SSE. + * If it can compile, then there's no need for a compile time option. + * For some current GCC limitations, these may be fixed by using the Intel + * compiler for certain files in a Linux build. + */ + +/* The minimum page size can be determined from the minimum page shift */ +#if defined(NVCPU_MIN_PAGE_SHIFT) +#define NVCPU_MIN_PAGE_SIZE (1 << NVCPU_MIN_PAGE_SHIFT) +#endif + +#if defined(NVCPU_IA64) || defined(NVCPU_X86_64) || \ + defined(NV_MACINTOSH_64) || defined(NVCPU_AARCH64) || \ + defined(NVCPU_PPC64LE) || defined(NVCPU_RISCV64) +# define NV_64_BITS /* all architectures where pointers are 64 bits */ +#else +/* we assume 32 bits. I don't see a need for NV_16_BITS. */ +#endif + +/* For verification-only features not intended to be included in normal drivers */ +#if defined(ENABLE_VERIF_FEATURES) +#define NV_VERIF_FEATURES +#endif + +/* + * New, safer family of #define's -- these ones use 0 vs. 1 rather than + * defined/!defined. This is advantageous because if you make a typo, + * say misspelled ENDIAN: + * + * #if NVCPU_IS_BIG_ENDAIN + * + * ...some compilers can give you a warning telling you that you screwed up. + * The compiler can also give you a warning if you forget to #include + * "cpuopsys.h" in your code before the point where you try to use these + * conditionals. + * + * Also, the names have been prefixed in more cases with "CPU" or "OS" for + * increased clarity. You can tell the names apart from the old ones because + * they all use "_IS_" in the name. + * + * Finally, these can be used in "if" statements and not just in #if's. For + * example: + * + * if (NVCPU_IS_BIG_ENDIAN) x = Swap32(x); + * + * Maybe some day in the far-off future these can replace the old #define's. + */ + +#define NV_IS_MODS 0 + +#define NVOS_IS_WINDOWS 0 +#if defined(NV_WINDOWS_CE) +#define NVOS_IS_WINDOWS_CE 1 +#else +#define NVOS_IS_WINDOWS_CE 0 +#endif +#if defined(NV_LINUX) +#define NVOS_IS_LINUX 1 +#else +#define NVOS_IS_LINUX 0 +#endif +#if defined(NV_UNIX) +#define NVOS_IS_UNIX 1 +#else +#define NVOS_IS_UNIX 0 +#endif +#if defined(NV_BSD) +#define NVOS_IS_FREEBSD 1 +#else +#define NVOS_IS_FREEBSD 0 +#endif +#if defined(NV_SUNOS) +#define NVOS_IS_SOLARIS 1 +#else +#define NVOS_IS_SOLARIS 0 +#endif +#define NVOS_IS_VMWARE 0 +#if defined(NV_QNX) +#define NVOS_IS_QNX 1 +#else +#define NVOS_IS_QNX 0 +#endif +#if defined(NV_ANDROID) +#define NVOS_IS_ANDROID 1 +#else +#define NVOS_IS_ANDROID 0 +#endif +#if defined(NV_MACINTOSH) +#define NVOS_IS_MACINTOSH 1 +#else +#define NVOS_IS_MACINTOSH 0 +#endif +#if defined(NV_VXWORKS) +#define NVOS_IS_VXWORKS 1 +#else +#define NVOS_IS_VXWORKS 0 +#endif +#if defined(NV_LIBOS) +#define NVOS_IS_LIBOS 1 +#else +#define NVOS_IS_LIBOS 0 +#endif +#if defined(NV_INTEGRITY) +#define NVOS_IS_INTEGRITY 1 +#else +#define NVOS_IS_INTEGRITY 0 +#endif + +#if defined(NVCPU_X86) +#define NVCPU_IS_X86 1 +#else +#define NVCPU_IS_X86 0 +#endif +#if defined(NVCPU_RISCV64) +#define NVCPU_IS_RISCV64 1 +#else +#define NVCPU_IS_RISCV64 0 +#endif +#if defined(NVCPU_NVRISCV64) +#define NVCPU_IS_NVRISCV64 1 +#else +#define NVCPU_IS_NVRISCV64 0 +#endif +#if defined(NVCPU_IA64) +#define NVCPU_IS_IA64 1 +#else +#define NVCPU_IS_IA64 0 +#endif +#if defined(NVCPU_X86_64) +#define NVCPU_IS_X86_64 1 +#else +#define NVCPU_IS_X86_64 0 +#endif +#if defined(NVCPU_FAMILY_X86) +#define NVCPU_IS_FAMILY_X86 1 +#else +#define NVCPU_IS_FAMILY_X86 0 +#endif +#if defined(NVCPU_PPC) +#define NVCPU_IS_PPC 1 +#else +#define NVCPU_IS_PPC 0 +#endif +#if defined(NVCPU_PPC64LE) +#define NVCPU_IS_PPC64LE 1 +#else +#define NVCPU_IS_PPC64LE 0 +#endif +#if defined(NVCPU_FAMILY_PPC) +#define NVCPU_IS_FAMILY_PPC 1 +#else +#define NVCPU_IS_FAMILY_PPC 0 +#endif +#if defined(NVCPU_ARM) +#define NVCPU_IS_ARM 1 +#else +#define NVCPU_IS_ARM 0 +#endif +#if defined(NVCPU_AARCH64) +#define NVCPU_IS_AARCH64 1 +#else +#define NVCPU_IS_AARCH64 0 +#endif +#if defined(NVCPU_FAMILY_ARM) +#define NVCPU_IS_FAMILY_ARM 1 +#else +#define NVCPU_IS_FAMILY_ARM 0 +#endif +#if defined(NVCPU_SH4) +#define NVCPU_IS_SH4 1 +#else +#define NVCPU_IS_SH4 0 +#endif +#if defined(NVCPU_XTENSA) +#define NVCPU_IS_XTENSA 1 +#else +#define NVCPU_IS_XTENSA 0 +#endif +#if defined(NV_BIG_ENDIAN) +#define NVCPU_IS_BIG_ENDIAN 1 +#else +#define NVCPU_IS_BIG_ENDIAN 0 +#endif +#if defined(NV_64_BITS) +#define NVCPU_IS_64_BITS 1 +#else +#define NVCPU_IS_64_BITS 0 +#endif +#if defined(NVCPU_FAMILY_ARM) +#define NVCPU_IS_PCIE_CACHE_COHERENT 0 +#else +#define NVCPU_IS_PCIE_CACHE_COHERENT 1 +#endif +#if defined(NV_DCECORE) +#define NVOS_IS_DCECORE 1 +#else +#define NVOS_IS_DCECORE 0 +#endif +/*****************************************************************************/ + +#endif /* CPUOPSYS_H */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h new file mode 100644 index 0000000..89e2219 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h @@ -0,0 +1,68 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000base.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV01_ROOT (client) control commands and parameters */ + +#define NV0000_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0000,NV0000_CTRL_##cat,idx) + +/* Client command categories (6bits) */ +#define NV0000_CTRL_RESERVED (0x00) +#define NV0000_CTRL_SYSTEM (0x01) +#define NV0000_CTRL_GPU (0x02) +#define NV0000_CTRL_GSYNC (0x03) +#define NV0000_CTRL_DIAG (0x04) +#define NV0000_CTRL_EVENT (0x05) +#define NV0000_CTRL_NVD (0x06) +#define NV0000_CTRL_SWINSTR (0x07) +#define NV0000_CTRL_PROC (0x09) +#define NV0000_CTRL_SYNC_GPU_BOOST (0x0A) +#define NV0000_CTRL_GPUACCT (0x0B) +#define NV0000_CTRL_VGPU (0x0C) +#define NV0000_CTRL_CLIENT (0x0D) + +// per-OS categories start at highest category and work backwards +#define NV0000_CTRL_OS_WINDOWS (0x3F) +#define NV0000_CTRL_OS_MACOS (0x3E) +#define NV0000_CTRL_OS_UNIX (0x3D) + + +/* + * NV0000_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0000_CTRL_CMD_NULL (0x0) /* finn: Evaluated from "(FINN_NV01_ROOT_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrl0000_base_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h new file mode 100644 index 0000000..a05add6 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h @@ -0,0 +1,183 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000client.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +#include "class/cl0000.h" +#include "rs_access.h" + +/* + * NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE + * + * This command may be used to query memory address space type associated with an object + * + * Parameters: + * hObject[IN] + * handle of the object to look up + * addrSpaceType[OUT] + * addrSpaceType with associated memory descriptor + * + * Possible status values are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_OBJECT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE (0xd01) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS { + NvHandle hObject; /* [in] - Handle of object to look up */ + NvU32 mapFlags; /* [in] - Flags that will be used when mapping the object */ + NvU32 addrSpaceType; /* [out] - Memory Address Space Type */ +} NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS; + +#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_INVALID 0x00000000 +#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_SYSMEM 0x00000001 +#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM 0x00000002 +#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_REGMEM 0x00000003 +#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC 0x00000004 + + + +/* + * NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO + * + * This command may be used to query information on a handle + */ +#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO (0xd02) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS { + NvHandle hObject; /* [in] - Handle of object to look up */ + NvU32 index; /* [in] - Type of lookup */ + + union { + NvHandle hResult; /* [out] - Result of lookup when result is a handle type */ + NV_DECLARE_ALIGNED(NvU64 iResult, 8); /* [out] - Result of lookup when result is a integer */ + } data; +} NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS; + +#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_INVALID 0x00000000 +#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_PARENT 0x00000001 +#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_CLASSID 0x00000002 + +/* + * NV0000_CTRL_CMD_CLIENT_GET_ACCESS_RIGHTS + * + * This command may be used to get this client's access rights for an object + * The object to which access rights are checked does not have to be owned by + * the client calling the command, it is owned by the hClient parameter + */ +#define NV0000_CTRL_CMD_CLIENT_GET_ACCESS_RIGHTS (0xd03) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS { + NvHandle hObject; /* [in] - Handle of object to look up */ + NvHandle hClient; /* [in] - Handle of client which owns hObject */ + RS_ACCESS_MASK maskResult; /* [out] - Result of lookup */ +} NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS; + +/* + * NV0000_CTRL_CMD_CLIENT_SET_INHERITED_SHARE_POLICY + * + * DEPRECATED: Calls NV0000_CTRL_CMD_CLIENT_SHARE_OBJECT with hObject=hClient + * + * This command will modify a client's inherited share policy list + * The policy is applied in the same way that NvRmShare applies policies, + * except to the client's inherited policy list instead of an object's policy list + */ +#define NV0000_CTRL_CMD_CLIENT_SET_INHERITED_SHARE_POLICY (0xd04) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS { + RS_SHARE_POLICY sharePolicy; /* [in] - Share Policy to apply */ +} NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS; + +/* + * NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE + * + * This command may be used to get a handle of a child of a given type + */ +#define NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE (0xd05) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS { + NvHandle hParent; /* [in] - Handle of parent object */ + NvU32 classId; /* [in] - Class ID of the child object */ + NvHandle hObject; /* [out] - Handle of the child object (0 if not found) */ +} NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS; + +/* + * NV0000_CTRL_CMD_CLIENT_SHARE_OBJECT + * + * This command is meant to imitate the NvRmShare API. + * Applies a share policy to an object, which should be owned by the caller's client. + * The policy is applied in the same way that NvRmShare applies policies. + * + * This ctrl command is only meant to be used in older branches. For releases after R450, + * use NvRmShare directly instead. + */ +#define NV0000_CTRL_CMD_CLIENT_SHARE_OBJECT (0xd06) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS { + NvHandle hObject; /* [in] - Handle of object to share */ + RS_SHARE_POLICY sharePolicy; /* [in] - Share Policy to apply */ +} NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS; + +/* + * NV0000_CTRL_CMD_CLIENT_OBJECTS_ARE_DUPLICATES + * + * This command returns true if the objects are duplicates. + * + * Currently supported only for memory objects. + */ +#define NV0000_CTRL_CMD_CLIENT_OBJECTS_ARE_DUPLICATES (0xd07) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS { + NvHandle hObject1; /* [in] - Handle of object to be checked */ + NvHandle hObject2; /* [in] - Handle of object to be checked */ + NvBool bDuplicates; /* [out] - Returns true if duplicates */ +} NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS; + +/* _ctrl0000client_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h new file mode 100644 index 0000000..9b72f20 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h @@ -0,0 +1,326 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000diag.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +/* NV01_ROOT (client) system control commands and parameters */ + +/* + * NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_STATE + * + * This command returns the current lock meter logging state. + * + * state + * This parameter returns the current lock meter logging state. + * NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_DISABLED + * This value indicates lock metering is disabled. + * NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_ENABLED + * This value indicates lock metering is enabled. + * count + * This parameter returns the total number of lock metering entries + * (NV0000_CTRL_DIAG_LOCK_METER_ENTRY) available. This value will + * not exceed NV0000_CTRL_DIAG_LOCK_METER_MAX_ENTRIES. When lock metering + * is enabled this parameter will return zero. + * missedCount + * This parameter returns the number of lock metering entries that had + * to be discarded due to a full lock metering table. This value will + * not exceed NV0000_CTRL_DIAG_LOCK_METER_MAX_TABLE_ENTRIES. When lock + * metering is enabled this parameter will return zero. + * bCircularBuffer + * This parameter returns type of buffer. + * TRUE + * Buffer is circular + * FALSE + * Buffer is sequential + * + * Possible status values returned are: + * NV_OK + */ +#define NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_STATE (0x480) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS_MESSAGE_ID (0x80U) + +typedef struct NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS { + NvU32 state; + NvU32 count; + NvU32 missedCount; + NvBool bCircularBuffer; +} NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS; + +/* valid lock metering state values */ +#define NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_DISABLED (0x00000000) +#define NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_ENABLED (0x00000001) + +/* maximum possible number of lock metering entries stored internally */ +#define NV0000_CTRL_DIAG_LOCK_METER_MAX_TABLE_ENTRIES (0x20000) + +/* + * NV0000_CTRL_CMD_DIAG_SET_LOCK_METER_STATE + * + * This command sets the current lock meter logging state. + * + * state + * This parameter specifies the new state of the lock metering mechanism. + * Legal state values are: + * NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_DISABLE + * This value disables lock metering. + * NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_ENABLE + * This value enables lock metering. + * NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_RESET + * This value resets, or clears, all lock metering state. Lock + * metering must be disabled prior to attempting a reset. + * bCircularBuffer + * This parameter specifies type of buffer. + * Possible values are: + * TRUE + * For circular buffer. + * FALSE + * For sequential buffer. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV0000_CTRL_CMD_DIAG_SET_LOCK_METER_STATE (0x481) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS { + NvU32 state; + NvBool bCircularBuffer; +} NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS; + +/* valid lock metering state values */ +#define NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_DISABLE (0x00000000) +#define NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_ENABLE (0x00000001) +#define NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_RESET (0x00000002) + +/* + * NV0000_CTRL_DIAG_LOCK_METER_ENTRY + * + * This structure represents a single lock meter entry. + * + * counter + * This field contains the number of nanonseconds elapsed since the + * the last system boot when the lock meter entry was generated. + * freq + * This field contains the CPU performance counter frequency in units + * of ticks per second. + * line + * This field contains the relevant line number. + * filename + * This field contains the relevant file name. + * tag + * This field contains a tag uniquely identifying the user of the metered + * lock operations. + * cpuNum + * This field contains the CPU number from which the metered operation + * was initiated. + * irql + * This field contains the IRQL at which the metered operation was + * initiated. + * data0 + * data1 + * data2 + * These fields contain tag-specific data. + */ +#define NV0000_CTRL_DIAG_LOCK_METER_ENTRY_FILENAME_LENGTH (0xc) + +typedef struct NV0000_CTRL_DIAG_LOCK_METER_ENTRY { + NV_DECLARE_ALIGNED(NvU64 counter, 8); + + NvU32 line; + NvU8 filename[NV0000_CTRL_DIAG_LOCK_METER_ENTRY_FILENAME_LENGTH]; + + NvU16 tag; + NvU8 cpuNum; + NvU8 irql; + + NV_DECLARE_ALIGNED(NvU64 threadId, 8); + + NvU32 data0; + NvU32 data1; + NvU32 data2; +} NV0000_CTRL_DIAG_LOCK_METER_ENTRY; + +/* valid lock meter entry tag values */ +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA (0x00000001) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_FORCED (0x00000002) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_COND (0x00000003) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_SEMA (0x00000004) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_API (0x00000010) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_API (0x00000011) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_GPUS (0x00000020) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_GPUS (0x00000021) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_DATA (0x00000100) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RMCTRL (0x00001000) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GET (0x00002000) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SET (0x00002001) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GETEX (0x00002002) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SETEX (0x00002003) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_VIDHEAP (0x00003000) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM (0x00003001) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM (0x00003002) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM_DMA (0x00003003) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM_DMA (0x00003004) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC (0x00004000) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_MEM (0x00004001) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_DUP_OBJECT (0x00004010) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CLIENT (0x00005000) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DEVICE (0x00005001) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE (0x00005002) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE_DIAG (0x00005003) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP (0x00005004) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP_CMN (0x00005005) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL (0x00005006) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_MPEG (0x00005007) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_DISP (0x00005008) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_MEMORY (0x00005009) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_FBMEM (0x0000500A) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_OBJECT (0x0000500B) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_EVENT (0x0000500C) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_IDLE_CHANNELS (0x00006000) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_BIND_CTXDMA (0x00007000) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_CTXDMA (0x00007001) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ISR (0x0000F000) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_DPC (0x0000F00F) + +/* + * NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_ENTRIES + * + * This command returns lock metering data in a fixed-sized array of entries. + * Each request will return up NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_MAX_ENTRIES + * entries. + * + * It is up to the caller to repeat these requests to retrieve the total number + * of entries reported by NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_STATE. + * + * entryCount + * This parameter returns the total number of valid entries returned + * in the entries array. This value will not exceed + * NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_MAX but may be less. + * A value of zero indicates there are no more valid entries. + * entries + * This parameter contains the storage into which lock metering entry + * data is returned. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_ENTRIES (0x485) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS_MESSAGE_ID" */ + +/* total number of entries returned */ +#define NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_MAX (0x40) + +#define NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS_MESSAGE_ID (0x85U) + +typedef struct NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS { + NvU32 entryCount; + NV_DECLARE_ALIGNED(NV0000_CTRL_DIAG_LOCK_METER_ENTRY entries[NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_MAX], 8); +} NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS; + +/* + * NV0000_CTRL_CMD_DIAG_PROFILE_RPC + * + * This command returns the RPC runtime information, and + * will only return valid when it is running inside VGX mode. + * + * rpcProfileCmd: + * RPC profiler command issued by rpc profiler utility + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_DIAG_PROFILE_RPC (0x488) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS_MESSAGE_ID" */ + +typedef struct RPC_METER_ENTRY { + NV_DECLARE_ALIGNED(NvU64 startTimeInNs, 8); + NV_DECLARE_ALIGNED(NvU64 endTimeInNs, 8); + NV_DECLARE_ALIGNED(NvU64 rpcDataTag, 8); + NV_DECLARE_ALIGNED(NvU64 rpcExtraData, 8); +} RPC_METER_ENTRY; + +#define NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS_MESSAGE_ID (0x88U) + +typedef struct NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS { + NvU32 rpcProfileCmd; +} NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS; + +#define NV0000_CTRL_PROFILE_RPC_CMD_DISABLE (0x00000000) +#define NV0000_CTRL_PROFILE_RPC_CMD_ENABLE (0x00000001) +#define NV0000_CTRL_PROFILE_RPC_CMD_RESET (0x00000002) + +/* + * NV0000_CTRL_CMD_DIAG_DUMP_RPC + * + * This command returns the RPC runtime information, which + * will be logged by NV0000_CTRL_CMD_DIAG_PROFILE_RPC command + * when running inside VGX mode. + * + * When issuing this command, the RPC profiler has to be disabled. + * + * firstEntryOffset: + * [IN] offset for first entry. + * + * outputEntryCout: + * [OUT] number of entries returned in rpcProfilerBuffer. + * + * remainingEntryCount: + * [OUT] number of entries remaining. + * + * elapsedTimeInNs: + * [OUT] runtime for the RPC profiler tool. + * + * rpcProfilerBuffer: + * [OUT] buffer to store the RPC entries + */ + +#define NV0000_CTRL_CMD_DIAG_DUMP_RPC (0x489) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_DUMP_RPC_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_DIAG_RPC_MAX_ENTRIES (100) + +#define NV0000_CTRL_DIAG_DUMP_RPC_PARAMS_MESSAGE_ID (0x89U) + +typedef struct NV0000_CTRL_DIAG_DUMP_RPC_PARAMS { + NvU32 firstEntryOffset; + NvU32 outputEntryCount; + NvU32 remainingEntryCount; + NV_DECLARE_ALIGNED(NvU64 elapsedTimeInNs, 8); + NV_DECLARE_ALIGNED(RPC_METER_ENTRY rpcProfilerBuffer[NV0000_CTRL_DIAG_RPC_MAX_ENTRIES], 8); +} NV0000_CTRL_DIAG_DUMP_RPC_PARAMS; + +/* _ctrl0000diag_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h new file mode 100644 index 0000000..1679f84 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h @@ -0,0 +1,113 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000event.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +#include "class/cl0000.h" +/* + * NV0000_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * This command sets event notification for the system events. + * + * event + * This parameter specifies the type of event to which the specified + * action is to be applied. The valid event values can be found in + * cl0000.h. + * + * action + * This parameter specifies the desired event notification action. + * Valid notification actions include: + * NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE + * This action disables event notification for the specified + * event. + * NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE + * This action enables single-shot event notification for the + * specified event. + * NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT + * This action enables repeated event notification for the + * specified event. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_CLIENT + * + */ + +#define NV0000_CTRL_CMD_EVENT_SET_NOTIFICATION (0x501) /* finn: Evaluated from "(FINN_NV01_ROOT_EVENT_INTERFACE_ID << 8) | NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS { + NvU32 event; + NvU32 action; +} NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001) +#define NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002) + +/* + * NV0000_CTRL_CMD_GET_SYSTEM_EVENT_STATUS + * + * This command returns the status of the specified system event type. + * See the description of NV01_EVENT for details on registering events. + * + * event + * This parameter specifies the event type. Valid event type values + * can be found in cl0000.h. + * status + * This parameter returns the status for a given event type. Valid + * status values can be found in cl0000.h. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_CLIENT + * + */ + +#define NV0000_CTRL_CMD_GET_SYSTEM_EVENT_STATUS (0x502) /* finn: Evaluated from "(FINN_NV01_ROOT_EVENT_INTERFACE_ID << 8) | NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS { + NvU32 event; + NvU32 status; +} NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS; + +/* _ctrl0000event_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h new file mode 100644 index 0000000..3ce0f06 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h @@ -0,0 +1,873 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000gpu.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" +#include "ctrl/ctrl0000/ctrl0000system.h" +#include "ctrl/ctrlxxxx.h" +#include "nvlimits.h" + +/* NV01_ROOT (client) GPU control commands and parameters */ + +/* + * NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS + * + * This command returns a table of attached gpuId values. + * The table is NV0000_CTRL_GPU_MAX_ATTACHED_GPUS entries in size. + * + * gpuIds[] + * This parameter returns the table of attached GPU IDs. + * The GPU ID is an opaque platform-dependent value that can be used + * with the NV0000_CTRL_CMD_GPU_GET_ID_INFO command to retrieve + * additional information about the GPU. The valid entries in gpuIds[] + * are contiguous, with a value of NV0000_CTRL_GPU_INVALID_ID indicating + * the invalid entries. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS (0x201U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_MAX_ATTACHED_GPUS 32U +#define NV0000_CTRL_GPU_INVALID_ID (0xffffffffU) + +#define NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS { + NvU32 gpuIds[NV0000_CTRL_GPU_MAX_ATTACHED_GPUS]; +} NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS; + +/* + * Deprecated. Please use NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 instead. + */ +#define NV0000_CTRL_CMD_GPU_GET_ID_INFO (0x202U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_MAX_SZNAME 128U + +#define NV0000_CTRL_NO_NUMA_NODE (-1) + +#define NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_GPU_GET_ID_INFO_PARAMS { + NvU32 gpuId; + NvU32 gpuFlags; + NvU32 deviceInstance; + NvU32 subDeviceInstance; + NV_DECLARE_ALIGNED(NvP64 szName, 8); + NvU32 sliStatus; + NvU32 boardId; + NvU32 gpuInstance; + NvS32 numaId; +} NV0000_CTRL_GPU_GET_ID_INFO_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 + * This command returns GPU instance information for the specified GPU. + * + * [in] gpuId + * This parameter should specify a valid GPU ID value. If there + * is no GPU present with the specified ID, a status of + * NV_ERR_INVALID_ARGUMENT is returned. + * [out] gpuFlags + * This parameter returns various flags values for the specified GPU. + * Valid flag values include: + * NV0000_CTRL_GPU_ID_INFO_IN_USE + * When true this flag indicates there are client references + * to the GPU in the form of device class instantiations (see + * NV01_DEVICE or NV03_DEVICE descriptions for details). + * NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE + * When true this flag indicates the GPU is linked into an + * active SLI device. + * NV0000_CTRL_GPU_ID_INFO_MOBILE + * When true this flag indicates the GPU is a mobile GPU. + * NV0000_CTRL_GPU_ID_BOOT_MASTER + * When true this flag indicates the GPU is the boot master GPU. + * NV0000_CTRL_GPU_ID_INFO_SOC + * When true this flag indicates the GPU is part of a + * System-on-Chip (SOC). + * NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED + * When ATS is enabled on the system. + * [out] deviceInstance + * This parameter returns the broadcast device instance number associated + * with the specified GPU. This value can be used to instantiate + * a broadcast reference to the GPU using the NV01_DEVICE classes. + * [out] subDeviceInstance + * This parameter returns the unicast subdevice instance number + * associated with the specified GPU. This value can be used to + * instantiate a unicast reference to the GPU using the NV20_SUBDEVICE + * classes. + * [out] sliStatus + * This parameters returns the SLI status for the specified GPU. + * Legal values for this member are described by NV0000_CTRL_SLI_STATUS. + * [out] boardId + * This parameter returns the board ID value with which the + * specified GPU is associated. Multiple GPUs can share the + * same board ID in multi-GPU configurations. + * [out] gpuInstance + * This parameter returns the GPU instance number for the specified GPU. + * GPU instance numbers are assigned in bus-probe order beginning with + * zero and are limited to one less the number of GPUs in the system. + * [out] numaId + * This parameter returns the ID of NUMA node for the specified GPU. + * In case there is no NUMA node, NV0000_CTRL_NO_NUMA_NODE is returned. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + + + +#define NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 (0x205U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS { + NvU32 gpuId; + NvU32 gpuFlags; + NvU32 deviceInstance; + NvU32 subDeviceInstance; + NvU32 sliStatus; + NvU32 boardId; + NvU32 gpuInstance; + NvS32 numaId; +} NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS; + + +/* valid flags values */ +#define NV0000_CTRL_GPU_ID_INFO_IN_USE 0:0 +#define NV0000_CTRL_GPU_ID_INFO_IN_USE_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_IN_USE_TRUE (0x00000001U) +#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE 1:1 +#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_TRUE (0x00000001U) +#define NV0000_CTRL_GPU_ID_INFO_MOBILE 2:2 +#define NV0000_CTRL_GPU_ID_INFO_MOBILE_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_MOBILE_TRUE (0x00000001U) +#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER 3:3 +#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_TRUE (0x00000001U) + + +#define NV0000_CTRL_GPU_ID_INFO_SOC 5:5 +#define NV0000_CTRL_GPU_ID_INFO_SOC_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_SOC_TRUE (0x00000001U) +#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED 6:6 +#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE (0x00000001U) + +/* + * NV0000_CTRL_CMD_GPU_GET_INIT_STATUS + * + * This command returns the initialization status for the specified GPU, and + * will return NV_ERR_INVALID_STATE if called prior to GPU + * initialization. + * + * gpuId + * This parameter should specify a valid GPU ID value. If there + * is no GPU present with the specified ID, a status of + * NV_ERR_INVALID_ARGUMENT is returned. + * status + * This parameter returns the status code identifying the initialization + * state of the GPU. If this parameter has the value NV_OK, + * then no errors were detected during GPU initialization. Otherwise, this + * parameter specifies the top-level error that was detected during GPU + * initialization. Note that a value of NV_OK only means that + * no errors were detected during the actual GPU initialization, and other + * errors may have occurred that prevent the GPU from being attached or + * accessible via the NV01_DEVICE or NV20_SUBDEVICE classes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV0000_CTRL_CMD_GPU_GET_INIT_STATUS (0x203U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS { + NvU32 gpuId; + NvU32 status; +} NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS + * + * This command returns a mask of valid device IDs. These device IDs + * can be used to instantiate the NV01_DEVICE_0 class (see NV01_DEVICE_0 + * for more information). + * + * deviceIds + * This parameter returns the mask of valid device IDs. Each enabled bit + * in the mask corresponds to a valid device instance. Valid device + * instances can be used to initialize the NV0080_ALLOC_PARAMETERS + * structure when using NvRmAlloc to instantiate device handles. The + * number of device IDs will not exceed NV_MAX_DEVICES in number. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS (0x204U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS { + NvU32 deviceIds; +} NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS; + + + +/* + * NV0000_CTRL_CMD_GPU_GET_PROBED_IDS + * + * This command returns a table of probed gpuId values. + * The table is NV0000_CTRL_GPU_MAX_PROBED_GPUS entries in size. + * + * gpuIds[] + * This parameter returns the table of probed GPU IDs. + * The GPU ID is an opaque platform-dependent value that can + * be used with the NV0000_CTRL_CMD_GPU_ATTACH_IDS and + * NV0000_CTRL_CMD_GPU_DETACH_ID commands to attach and detach + * the GPU. + * The valid entries in gpuIds[] are contiguous, with a value + * of NV0000_CTRL_GPU_INVALID_ID indicating the invalid entries. + * excludedGpuIds[] + * This parameter returns the table of excluded GPU IDs. + * An excluded GPU ID is an opaque platform-dependent value that + * can be used with NV0000_CTRL_CMD_GPU_GET_PCI_INFO and + * NV0000_CTRL_CMD_GPU_GET_UUID_INFO. + * The valid entries in excludedGpuIds[] are contiguous, with a value + * of NV0000_CTRL_GPU_INVALID_ID indicating the invalid entries. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0000_CTRL_CMD_GPU_GET_PROBED_IDS (0x214U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_MAX_PROBED_GPUS NV_MAX_DEVICES + +#define NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS { + NvU32 gpuIds[NV0000_CTRL_GPU_MAX_PROBED_GPUS]; + NvU32 excludedGpuIds[NV0000_CTRL_GPU_MAX_PROBED_GPUS]; +} NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_GET_PCI_INFO + * + * This command takes a gpuId and returns PCI bus information about + * the device. If the OS does not support returning PCI bus + * information, this call will return NV_ERR_NOT_SUPPORTED + * + * gpuId + * This parameter should specify a valid GPU ID value. If there + * is no GPU present with the specified ID, a status of + * NV_ERR_INVALID_ARGUMENT is returned. + * + * domain + * This parameter returns the PCI domain of the GPU. + * + * bus + * This parameter returns the PCI bus of the GPU. + * + * slot + * This parameter returns the PCI slot of the GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_GPU_GET_PCI_INFO (0x21bU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID (0x1BU) + +typedef struct NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS { + NvU32 gpuId; + NvU32 domain; + NvU16 bus; + NvU16 slot; +} NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_ATTACH_IDS + * + * This command attaches the GPUs with the gpuIds matching those in + * the table provided by the client. + * The table is NV0000_CTRL_GPU_MAX_PROBED_GPUS entries in size. + * + * gpuIds[] + * This parameter holds the table of gpuIds to attach. At least + * one gpuId must be specified; clients may use the special + * gpuId value NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS to indicate + * that all probed GPUs are to be attached. + * The entries in gpuIds[] must be contiguous, with a value of + * NV0000_CTRL_GPU_INVALID_ID to indicate the first invalid + * entry. + * If one or more of the gpuId values do not specify a GPU found + * in the system, the NV_ERR_INVALID_ARGUMENT error + * status is returned. + * + * failedId + * If NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS is specified and + * a GPU cannot be attached, the NV0000_CTRL_CMD_GPU_ATTACH_IDS + * command returns an error code and saves the failing GPU's + * gpuId in this field. + * + * If a table of gpuIds is provided, these gpuIds will be validated + * against the RM's table of probed gpuIds and attached in turn, + * if valid; if NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS is used, all + * probed gpuIds will be attached, in the order the associated GPUs + * were probed in by the RM. + * + * If a gpuId fails to attach, this gpuId is stored in the failedId + * field. Any GPUs attached by the command prior the failure are + * detached. + * + * If multiple clients use NV0000_CTRL_CMD_GPU_ATTACH_IDS to attach + * a gpuId, the RM ensures that the gpuId won't be detached until + * all clients have issued a call to NV0000_CTRL_CMD_GPU_DETACH_IDS + * to detach the gpuId (or have terminated). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OPERATING_SYSTEM + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_IRQ_EDGE_TRIGGERED + * NV_ERR_IRQ_NOT_FIRING + */ +#define NV0000_CTRL_CMD_GPU_ATTACH_IDS (0x215U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS (0x0000ffffU) + +#define NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV0000_CTRL_GPU_ATTACH_IDS_PARAMS { + NvU32 gpuIds[NV0000_CTRL_GPU_MAX_PROBED_GPUS]; + NvU32 failedId; +} NV0000_CTRL_GPU_ATTACH_IDS_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_DETACH_IDS + * + * This command detaches the GPUs with the gpuIds matching those in + * the table provided by the client. + * The table is NV0000_CTRL_GPU_MAX_ATTACHED_GPUS entries in size. + * + * gpuIds[] + * This parameter holds the table of gpuIds to detach. At least + * one gpuId must be specified; clients may use the special + * gpuId NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS to indicate that + * all attached GPUs are to be detached. + * The entries in gpuIds[] must be contiguous, with a value of + * NV0000_CTRL_GPU_INVALID_ID to indicate the first invalid + * entry. + * If one or more of the gpuId values do not specify a GPU found + * in the system, the NV_ERR_INVALID_ARGUMENT error + * status is returned. + * + * If a table of gpuIds is provided, these gpuIds will be validated + * against the RM's list of attached gpuIds; each valid gpuId is + * detached immediately if it's no longer in use (i.e. if there are + * no client references to the associated GPU in the form of + * device class instantiations (see the NV01_DEVICE or NV03_DEVICE + * descriptions for details)) and if no other client still requires + * the associated GPU to be attached. + * + * If a given gpuId can't be detached immediately, it will instead + * be detached when the last client reference is freed or when + * the last client that issued NV0000_CTRL_CMD_GPU_ATTACH_IDS for + * this gpuId either issues NV0000_CTRL_CMD_GPU_DETACH_IDS or exits + * without detaching the gpuId explicitly. + * + * Clients may use the NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS command + * to obtain a table of the attached gpuIds. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OPERATING_SYSTEM + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_GPU_DETACH_IDS (0x216U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS (0x0000ffffU) + +#define NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV0000_CTRL_GPU_DETACH_IDS_PARAMS { + NvU32 gpuIds[NV0000_CTRL_GPU_MAX_ATTACHED_GPUS]; +} NV0000_CTRL_GPU_DETACH_IDS_PARAMS; + + + +/* + * NV0000_CTRL_CMD_GPU_GET_SVM_SIZE + * + * This command is used to get the SVM size. + * + * gpuId + * This parameter uniquely identifies the GPU whose associated + * SVM size is to be returned. The value of this field must + * match one of those in the table returned by + * NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS + * + * SvmSize + * SVM size is returned in this. + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + * + */ +#define NV0000_CTRL_CMD_GPU_GET_SVM_SIZE (0x240U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID (0x40U) + +typedef struct NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS { + NvU32 gpuId; + NvU32 svmSize; +} NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS; + + + +/* + * NV0000_CTRL_CMD_GPU_GET_UUID_INFO + * + * This command returns requested information pertaining to the GPU + * specified by the GPU UUID passed in. + * + * Generally only GPUs that have been attached are visible to this call. Therefore + * queries on unattached GPUs will fail with NV_ERR_OBJECT_NOT_FOUND. However, + * a query for a SHA1 UUID may succeed for an unattached GPU in cases where the GID + * is cached, such as an excluded GPU. + * + * gpuGuid (INPUT) + * The GPU UUID of the gpu whose parameters are to be returned. Refer to + * NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information. + * + * flags (INPUT) + * The _FORMAT* flags designate ascii string format or a binary format. + * + * The _TYPE* flags designate either SHA-1-based (32-hex-character) or + * SHA-256-based (64-hex-character). + * + * gpuId (OUTPUT) + * The GPU ID of the GPU identified by gpuGuid. Refer to + * NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information. + * + * deviceInstance (OUTPUT) + * The device instance of the GPU identified by gpuGuid. Refer to + * NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information. + * + * subdeviceInstance (OUTPUT) + * The subdevice instance of the GPU identified by gpuGuid. Refer to + * NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * + */ +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO (0x274U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID" */ + +/* maximum possible number of bytes of GID information */ +#define NV0000_GPU_MAX_GID_LENGTH (0x00000100U) + +#define NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID (0x74U) + +typedef struct NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS { + NvU8 gpuUuid[NV0000_GPU_MAX_GID_LENGTH]; + NvU32 flags; + NvU32 gpuId; + NvU32 deviceInstance; + NvU32 subdeviceInstance; +} NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS; + +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT 1:0 +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_ASCII (0x00000000U) +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_BINARY (0x00000002U) + +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE 2:2 +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA1 (0x00000000U) +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA256 (0x00000001U) + +/* + * NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID + * + * This command returns the GPU UUID for the provided GPU ID. + * Note that only GPUs that have been attached are visible to this call. + * Therefore queries on unattached GPUs will fail + * with NV_ERR_OBJECT_NOT_FOUND. + * + * gpuId (INPUT) + * The GPU ID whose parameters are to be returned. Refer to + * NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information. + * + * flags (INPUT) + * + * NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII + * This value is used to request the GPU UUID in ASCII format. + * NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY + * This value is used to request the GPU UUID in binary format. + * + * NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1 + * This value is used to request that the GPU UUID value + * be SHA1-based (32-hex-character). + * NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256 + * This value is used to request that the GPU UUID value + * be SHA256-based (64-hex-character). + * + * gpuUuid[NV0000_GPU_MAX_GID_LENGTH] (OUTPUT) + * The GPU UUID of the GPU identified by GPU ID. Refer to + * NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information. + * + * uuidStrLen (OUTPUT) + * The length of the UUID returned which is related to the format that + * was requested using flags. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_OPERATING_SYSTEM + */ +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID (0x275U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID (0x75U) + +typedef struct NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS { + NvU32 gpuId; + NvU32 flags; + NvU8 gpuUuid[NV0000_GPU_MAX_GID_LENGTH]; + NvU32 uuidStrLen; +} NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS; + +/* valid format values */ +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT 1:0 +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII (0x00000000U) +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY (0x00000002U) + +/*valid type values*/ +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE 2:2 +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1 (0x00000000U) +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256 (0x00000001U) + + + +/* + * NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE + * + * This command is used to enter or exit the so called "drain" state. + * When this state is enabled, the existing clients continue executing + * as usual, however no new client connections are allowed. + * This is done in order to "drain" the system of the running clients + * in preparation to selectively powering down the GPU. + * No GPU can enter a bleed state if that GPU is in an SLI group. + * In that case, NV_ERR_IN_USE is returned. + * Requires administrator privileges. + * + * It is expected, that the "drain" state will be eventually deprecated + * and replaced with another mechanism to quiesce a GPU (Bug 1718113). + * + * gpuId (INPUT) + * This parameter should specify a valid GPU ID value. If there + * is no GPU present with the specified ID, a status of + * NV_ERR_INVALID_ARGUMENT is returned. + * newState (INPUT) + * This input parameter is used to enter or exit the "drain" + * software state of the GPU specified by the gpuId parameter. + * Possible values are: + * NV0000_CTRL_GPU_DRAIN_STATE_ENABLED + * NV0000_CTRL_GPU_DRAIN_STATE_DISABLED + * flags (INPUT) + * NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE + * if set, upon reaching quiescence, a request will be made to + * the OS to "forget" the PCI device associated with the + * GPU specified by the gpuId parameter, in case such a request + * is supported by the OS. Otherwise, NV_ERR_NOT_SUPPORTED + * will be returned. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_IN_USE + */ + +#define NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE (0x278U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID" */ + +/* Possible values of newState */ +#define NV0000_CTRL_GPU_DRAIN_STATE_DISABLED (0x00000000U) +#define NV0000_CTRL_GPU_DRAIN_STATE_ENABLED (0x00000001U) + +/* Defined bits for the "flags" argument */ +#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE (0x00000001U) +#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE (0x00000002U) + +#define NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID (0x78U) + +typedef struct NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS { + NvU32 gpuId; + NvU32 newState; + NvU32 flags; +} NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE + * + * gpuId (INPUT) + * This parameter should specify a valid GPU ID value. If there + * is no GPU present with the specified ID, a status of + * NVOS_STATUS_ERROR_INVALID_ARGUMENT is returned. + * drainState (OUTPUT) + * This parameter returns a value indicating if the "drain" + * state is currently enabled or not for the specified GPU. See the + * description of NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE. + * Possible values are: + * NV0000_CTRL_GPU_DRAIN_STATE_ENABLED + * NV0000_CTRL_GPU_DRAIN_STATE_DISABLED + * flags (OUTPUT) + * NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE + * if set, upon reaching quiesence, the GPU device will be + * removed automatically from the kernel space, similar + * to what writing "1" to the sysfs "remove" node does. + * NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE + * after removing the GPU, also disable the parent bridge's + * PCIe link. This flag can only be set in conjunction with + * NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE, and then + * only when the GPU is already idle (not attached). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE (0x279U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID (0x79U) + +typedef struct NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS { + NvU32 gpuId; + NvU32 drainState; + NvU32 flags; +} NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_DISCOVER + * + * This request asks the OS to scan the PCI tree or a sub-tree for GPUs, + * that are not yet known to the OS, and to make them available for use. + * If all of domain:bus:slot.function are zeros, the entire tree is scanned, + * otherwise the parameters identify the bridge device, that roots the + * subtree to be scanned. + * Requires administrator privileges. + * + * domain (INPUT) + * PCI domain of the bridge + * bus (INPUT) + * PCI bus of the bridge + * slot (INPUT) + * PCI slot of the bridge + * function (INPUT) + * PCI function of the bridge + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_DEVICE + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_OPERATING_SYSTEM + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_GPU_DISCOVER (0x27aU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | 0x7A" */ + +typedef struct NV0000_CTRL_GPU_DISCOVER_PARAMS { + NvU32 domain; + NvU8 bus; + NvU8 slot; + NvU8 function; +} NV0000_CTRL_GPU_DISCOVER_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE + * + * This command is used to get the content of the MemOp (CUDA Memory Operation) + * enablement mask, which can be overridden by using the MemOpOverride RegKey. + * + * The enableMask member must be treated as a bitmask, where each bit controls + * the enablement of a feature. + * + * So far, the only feature which is defined controls to whole MemOp APIs. + * + * Possible status values returned are: + * NV_OK + * + */ +#define NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE (0x27bU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID (0x7BU) + +typedef struct NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS { + NvU32 enableMask; +} NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS; + +#define NV0000_CTRL_GPU_FLAGS_MEMOP_ENABLE (0x00000001U) + + + +/* + * NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT + * + * This privileged command is used to disable initialization for the NVLinks + * provided in the mask. + * + * The mask must be applied before the GPU is attached. DISABLE_NVLINK_INIT + * is an NOP for non-NVLink GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_DEVICE + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_INVALID_STATE + * NV_ERR_IN_USE + * + */ +#define NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT (0x281U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS { + NvU32 gpuId; + NvU32 mask; + NvBool bSkipHwNvlinkDisable; +} NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS; + + +#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA 0x00000175U +#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN 6U +#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT 5U + +/* + * NV0000_CTRL_CMD_GPU_LEGACY_CONFIG + * + * Path to use legacy RM GetConfig/Set API. This API is being phased out. + */ +#define NV0000_CTRL_CMD_GPU_LEGACY_CONFIG (0x282U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID (0x82U) + +typedef struct NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS { + NvHandle hContext; /* [in] - Handle of object to perform operation on (Device, Subdevice, etc) */ + NvU32 opType; /* [in] - Type of API */ + NvV32 index; /* [in] - command type */ + NvU32 dataType; /* [out] - data union type */ + + union { + struct { + NvU32 newValue; + NvU32 oldValue; + } configSet; + struct { + NvU8 paramData[NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA]; + NvU32 paramSize; + } configEx; + struct { + NvU32 propertyId; + NvU32 propertyIn[NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN]; + NvU32 propertyOut[NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT]; + } reservedProperty; + } data; +} NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS; + +#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET (0x00000001U) +#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET_EX (0x00000002U) +#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET_EX (0x00000003U) +#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_RESERVED (0x00000004U) + +/* + * NV0000_CTRL_CMD_IDLE_CHANNELS + */ +#define NV0000_CTRL_CMD_IDLE_CHANNELS (0x283U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID (0x83U) + +typedef struct NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS { + NvHandle hDevice; + NvHandle hChannel; + NvV32 numChannels; + /* C form: NvP64 phClients NV_ALIGN_BYTES(8); */ + NV_DECLARE_ALIGNED(NvP64 phClients, 8); + /* C form: NvP64 phDevices NV_ALIGN_BYTES(8); */ + NV_DECLARE_ALIGNED(NvP64 phDevices, 8); + /* C form: NvP64 phChannels NV_ALIGN_BYTES(8); */ + NV_DECLARE_ALIGNED(NvP64 phChannels, 8); + NvV32 flags; + NvV32 timeout; +} NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS; + +#define NV0000_CTRL_GPU_IMAGE_TYPE_GSP (0x00000001U) +#define NV0000_CTRL_GPU_IMAGE_TYPE_GSP_LOG (0x00000002U) + +/* + * NV0000_CTRL_CMD_PUSH_GSP_UCODE + * + * This command is used to push the GSP ucode into RM. + * This function is used only on VMware + * + * Possible status values returned are: + * NV_OK The sent data is stored successfully + * NV_ERR_INVALID_ARGUMENT if the arguments are not proper + * NV_ERR_NO_MEMORY if memory allocation failed + * NV_ERR_NOT_SUPPORTED if function is invoked on non-GSP setup or any + * setup other than VMware host + * + */ +#define NV0000_CTRL_CMD_PUSH_GSP_UCODE (0x285) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS_MESSAGE_ID (0x85U) + +typedef struct NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS { + NvU8 image; + NV_DECLARE_ALIGNED(NvU64 totalSize, 8); + NV_DECLARE_ALIGNED(NvP64 pData, 8); +} NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS; +/* _ctrl0000gpu_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h new file mode 100644 index 0000000..6f8ff13 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h @@ -0,0 +1,255 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000gpuacct.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +/* + * NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE + * + * This command is used to enable or disable the per process GPU accounting. + * This is part of GPU's software state and will persist if persistent + * software state is enabled. Refer to the description of + * NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE for more information. + * + * gpuId + * This parameter should specify a valid GPU ID value. Refer to the + * description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more + * information. If there is no GPU present with the specified ID, + * a status of NV_ERR_INVALID_ARGUMENT is returned. + * pid + * This input parameter specifies the process id of the process for which + * the accounting state needs to be set. + * In case of VGX host, this parameter specifies VGPU plugin(VM) pid. This + * parameter is set only when this RM control is called from VGPU plugin, + * otherwise it is zero meaning set/reset the accounting state for the + * specified GPU. + * newState + * This input parameter is used to enable or disable the GPU accounting. + * Possible values are: + * NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED + * NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE (0xb01) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID" */ + +/* Possible values of persistentSwState */ +#define NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED (0x00000000) +#define NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED (0x00000001) + +#define NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS { + NvU32 gpuId; + NvU32 pid; + NvU32 newState; +} NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS; + +/* + * NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_STATE + * + * This command is used to get the current state of GPU accounting. + * + * gpuId + * This parameter should specify a valid GPU ID value. Refer to the + * description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more + * information. If there is no GPU present with the specified ID, + * a status of NV_ERR_INVALID_ARGUMENT is returned. + * pid + * This input parameter specifies the process id of the process of which the + * accounting state needs to be queried. + * In case of VGX host, this parameter specifies VGPU plugin(VM) pid. This + * parameter is set only when this RM control is called from VGPU plugin, + * otherwise it is zero meaning the accounting state needs to be queried for + * the specified GPU. + * state + * This parameter returns a value indicating if per process GPU accounting + * is currently enabled or not for the specified GPU. See the + * description of NV0000_CTRL_CMD_GPU_SET_ACCOUNTING_STATE. + * Possible values are: + * NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED + * NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_STATE (0xb02) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS { + NvU32 gpuId; + NvU32 pid; + NvU32 state; +} NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS; + +/* + * NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS + * + * This command returns GPU accounting data for the process. + * + * gpuId + * This parameter should specify a valid GPU ID value. Refer to the + * description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more + * information. If there is no GPU present with the specified ID, + * a status of NV_ERR_INVALID_ARGUMENT is returned. + * pid + * This parameter specifies the PID of the process for which information is + * to be queried. + * In case of VGX host, this parameter specifies VGPU plugin(VM) pid inside + * which the subPid is running. This parameter is set to VGPU plugin pid + * when this RM control is called from VGPU plugin. + * subPid + * In case of VGX host, this parameter specifies the PID of the process for + * which information is to be queried. In other cases, it is zero. + * gpuUtil + * This parameter returns the average GR utilization during the process's + * lifetime. + * fbUtil + * This parameter returns the average FB bandwidth utilization during the + * process's lifetime. + * maxFbUsage + * This parameter returns the maximum FB allocated (in bytes) by the process. + * startTime + * This parameter returns the time stamp value in micro seconds at the time + * process started utilizing GPU. + * stopTime + * This parameter returns the time stamp value in micro seconds at the time + * process stopped utilizing GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_GPUACCT_GET_PROC_ACCOUNTING_INFO (0xb03) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS { + NvU32 gpuId; + NvU32 pid; + NvU32 subPid; + NvU32 gpuUtil; + NvU32 fbUtil; + NV_DECLARE_ALIGNED(NvU64 maxFbUsage, 8); + NV_DECLARE_ALIGNED(NvU64 startTime, 8); + NV_DECLARE_ALIGNED(NvU64 endTime, 8); +} NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS; + +/* + * NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_PIDS + * + * This command is used to get the PIDS of processes with accounting + * information in the driver. + * + * gpuId + * This parameter should specify a valid GPU ID value. Refer to the + * description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more + * information. If there is no GPU present with the specified ID, + * a status of NV_ERR_INVALID_ARGUMENT is returned. + * pid + * This input parameter specifies the process id of the process of which the + * information needs to be queried. + * In case of VGX host, this parameter specifies VGPU plugin(VM) pid. This + * parameter is set only when this RM control is called from VGPU plugin, + * otherwise it is zero meaning get the pid list of the all the processes + * running on the specified GPU. + * pidTbl + * This parameter returns the table of all PIDs for which driver has + * accounting info. + * pidCount + * This parameter returns the number of entries in the PID table. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_PIDS (0xb04) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_MESSAGE_ID" */ + +/* max size of pidTable */ +#define NV0000_GPUACCT_PID_MAX_COUNT 4000 + +#define NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS { + NvU32 gpuId; + NvU32 pid; + NvU32 pidTbl[NV0000_GPUACCT_PID_MAX_COUNT]; + NvU32 pidCount; +} NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS; + +/* + * NV0000_CTRL_CMD_GPUACCT_CLEAR_ACCOUNTING_DATA + * + * This command is used to clear previously collected GPU accounting data. This + * will have no affect on data for the running processes, accounting data for + * these processes will not be cleared and will still be logged for these + * processes. In order to clear ALL accounting data, accounting needs to be + * disabled using NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE before executing + * this command. + * + * gpuId + * This parameter should specify a valid GPU ID value. Refer to the + * description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more + * information. If there is no GPU present with the specified ID, + * a status of NV_ERR_INVALID_ARGUMENT is returned. + * pid + * This input parameter specifies the process id of the process for which + * the accounting data needs to be cleared. + * In case of VGX host, this parameter specifies VGPU plugin(VM) pid for + * which the accounting data needs to be cleared. This parameter is set only + * when this RM control is called from VGPU plugin, otherwise it is zero + * meaning clear the accounting data of processes running on baremetal + * system. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ + +#define NV0000_CTRL_CMD_GPUACCT_CLEAR_ACCOUNTING_DATA (0xb05) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS { + NvU32 gpuId; + NvU32 pid; +} NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS; + + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h new file mode 100644 index 0000000..2df6c42 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h @@ -0,0 +1,101 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000gsync.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +#include "class/cl30f1.h" +/* NV01_ROOT (client) system controller control commands and parameters */ + +/* + * NV0000_CTRL_CMD_GSYNC_GET_ATTACHED_IDS + * + * This command returns a table of attached gsyncId values. + * The table is NV0000_CTRL_GSYNC_MAX_ATTACHED_GSYNCS entries in size. + * + * gsyncIds[] + * This parameter returns the table of attached gsync IDs. + * The gsync ID is an opaque platform-dependent value that + * can be used with the NV0000_CTRL_CMD_GSYNC_GET_ID_INFO command to + * retrieve additional information about the gsync device. + * The valid entries in gsyncIds[] are contiguous, with a value + * of NV0000_CTRL_GSYNC_INVALID_ID indicating the invalid entries. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV0000_CTRL_CMD_GSYNC_GET_ATTACHED_IDS (0x301) /* finn: Evaluated from "(FINN_NV01_ROOT_GSYNC_INTERFACE_ID << 8) | NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS { + NvU32 gsyncIds[NV30F1_MAX_GSYNCS]; +} NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS; + +/* this value marks entries in gsyncIds[] as invalid */ +#define NV0000_CTRL_GSYNC_INVALID_ID (0xffffffff) + +/* + * NV0000_CTRL_CMD_GSYNC_GET_ID_INFO + * + * This command returns gsync instance information for the + * specified gsync device. + * + * gsyncId + * This parameter should specify a valid gsync ID value. + * If there is no gsync present with the specified ID, a + * status of NV_ERR_INVALID_ARGUMENT is returned. + * gsyncFlags + * This parameter returns the current state of the gsync device. + * gsyncInstance + * This parameter returns the instance number associated with the + * specified gsync. This value can be used to instantiate + * a reference to the gsync using one of the NV30_GSYNC + * classes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_GSYNC_GET_ID_INFO (0x302) /* finn: Evaluated from "(FINN_NV01_ROOT_GSYNC_INTERFACE_ID << 8) | NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS { + NvU32 gsyncId; + NvU32 gsyncFlags; + NvU32 gsyncInstance; +} NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS; + +/* _ctrl0000gsync_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h new file mode 100644 index 0000000..41a4954 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h @@ -0,0 +1,636 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000nvd.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +/* NV01_ROOT (client) nvd control commands and parameters */ + +/* + * NV0080_CTRL_NVD_DUMP_COMPONENT + * + * The following dump components are used to describe legal ranges in + * commands below: + * + * NV0080_CTRL_CMD_NVD_DUMP_COMPONENT_SYS + * This is the system dump component. + * NV0080_CTRL_CMD_NVD_DUMP_COMPONENT_NVLOG + * This is the nvlog dump component. + * NV0080_CTRL_CMD_NVD_DUMP_COMPONENT_RESERVED + * This component is reserved. + * + * See nvdump.h for more information on dump component values. + */ +#define NV0000_CTRL_NVD_DUMP_COMPONENT_SYS (0x400) +#define NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG (0x800) +#define NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED (0xB00) + +/* + * NV0000_CTRL_CMD_NVD_GET_DUMP_SIZE + * + * This command gets the expected dump size of a particular system + * dump component. Note that events that occur between this command + * and a later NV0000_CTRL_CMD_NVD_GET_DUMP command could alter the size of + * the buffer required. + * + * component + * This parameter specifies the system dump component for which the + * dump size is desired. Legal values for this parameter must + * be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_SYS and + * less than NV0000_CTRL_NVD_GET_DUMP_COMPONENT_NVLOG. + * size + * This parameter returns the expected size in bytes. The maximum + * value of this call is NV0000_CTRL_NVD_MAX_DUMP_SIZE. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT if components are invalid. + */ + +#define NV0000_CTRL_CMD_NVD_GET_DUMP_SIZE (0x601) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS { + NvU32 component; + NvU32 size; +} NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS; + +/* Max size that a GET_DUMP_SIZE_PARAMS call can return */ +#define NV0000_CTRL_NVD_MAX_DUMP_SIZE (1000000) + +/* + * NV0000_CTRL_CMD_NVD_GET_DUMP + * + * This command gets a dump of a particular system dump component. If triggers + * is non-zero, the command waits for the trigger to occur before it returns. + * + * pBuffer + * This parameter points to the buffer for the data. + * component + * This parameter specifies the system dump component for which the + * dump is to be retrieved. Legal values for this parameter must + * be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_SYS and + * less than NV0000_CTRL_NVD_GET_DUMP_COMPONENT_NVLOG. + * size + * On entry, this parameter specifies the maximum length for + * the returned data. On exit, it specifies the number of bytes + * returned. + * + * Possible status values returned are: + * NV_OK + * NVOS_ERROR_INVALID_ARGUMENT if components are invalid. + * NVOS_ERROR_INVALID_ADDRESS if pBuffer is invalid + * NVOS_ERROR_INVALID_???? if the buffer was too small + */ +#define NV0000_CTRL_CMD_NVD_GET_DUMP (0x602) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_NVD_GET_DUMP_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pBuffer, 8); + NvU32 component; + NvU32 size; +} NV0000_CTRL_NVD_GET_DUMP_PARAMS; + +/* + * NV0000_CTRL_CMD_NVD_GET_TIMESTAMP + * + * This command returns the current value of the timestamp used + * by the RM in NvDebug dumps. It is provided to keep the RM and NvDebug + * clients on the same time base. + * + * cpuClkId + * See also NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO + * This parameter specifies the source of the CPU clock. Legal values for + * this parameter include: + * NV0000_NVD_CPU_TIME_CLK_ID_DEFAULT and NV0000_NVD_CPU_TIME_CLK_ID_OSTIME + * This clock id will provide real time in microseconds since 00:00:00 UTC on January 1, 1970. + * It is calculated as follows: + * (seconds * 1000000) + uSeconds + * NV0000_NVD_CPU_TIME_CLK_ID_PLATFORM_API + * This clock id will provide time stamp that is constant-rate, high + * precision using platform API that is also available in the user mode. + * NV0000_NVD_CPU_TIME_CLK_ID_TSC + * This clock id will provide time stamp using CPU's time stamp counter. + * + * timestamp + * Retrieved timestamp + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_NVD_CPU_TIME_CLK_ID_DEFAULT (0x00000000) +#define NV0000_NVD_CPU_TIME_CLK_ID_OSTIME (0x00000001) +#define NV0000_NVD_CPU_TIME_CLK_ID_TSC (0x00000002) +#define NV0000_NVD_CPU_TIME_CLK_ID_PLATFORM_API (0x00000003) + +#define NV0000_CTRL_CMD_NVD_GET_TIMESTAMP (0x603) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS { + NV_DECLARE_ALIGNED(NvU64 timestamp, 8); + NvU8 cpuClkId; +} NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS; + +/* + * NV0000_CTRL_CMD_NVD_GET_NVLOG_INFO + * + * This command gets the current state of the NvLog buffer system. + * + * component (in) + * This parameter specifies the system dump component for which the + * NvLog info is desired. Legal values for this parameter must + * be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG and + * less than NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED. + * version (out) + * This parameter returns the version of the Nvlog subsystem. + * runtimeSizes (out) + * This parameter returns the array of sizes for all supported printf + * specifiers. This information is necessary to know how many bytes + * to decode when given a certain specifier (such as %d). + * The following describes the contents of each array entry: + * NV0000_CTRL_NVD_RUNTIME_SIZE_UNUSED + * This array entry has special meaning and is unused in the + * runtimeSizes array. + * NV0000_CTRL_NVD_RUNTIME_SIZE_INT + * This array entry returns the size of integer types for use in + * interpreting the %d, %u, %x, %X, %i, %o specifiers. + * NV0000_CTRL_NVD_RUNTIME_SIZE_LONG_LONG + * This array entry returns the size of long long integer types for + * using in interpreting the %lld, %llu, %llx, %llX, %lli, %llo + * specifiers. + * NV0000_CTRL_NVD_RUNTIME_SIZE_STRING + * This array entry returns zero as strings are not allowed. + * NV0000_CTRL_NVD_RUNTIME_SIZE_PTR + * This array entry returns the size of the pointer type for use + * in interpreting the %p specifier. + * NV0000_CTRL_NVD_RUNTIME_SIZE_CHAR + * This array entry returns the size of the char type for use in + * intpreting the %c specifier. + * NV0000_CTRL_NVD_RUNTIME_SIZE_FLOAT + * This array entry returns the size of the float types for use in + * in interpreting the %f, %g, %e, %F, %G, %E specifiers. + * All remaining entries are reserved and return 0. + * printFlags (out) + * This parameter returns the flags of the NvLog system. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_BUFFER_FLAGS + * See NV0000_CTRL_CMD_NVD_GET_NVLOG_BUF_INFO for more details. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_BUFFER_SIZE + * This field returns the buffer size in KBytes. A value of zero + * is returned when logging is disabled. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP + * This field returns the format of the timestamp. Legal values + * for this parameter include: + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP_NONE + * This value indicates no timestamp. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP_32BIT + * This value indicates a 32-bit timestamp. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP_64BIT + * This value indicates a 64-bit timestamp. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP_32BIT_DIFF + * This value indicates a 32-bit differential timestamp. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_RESERVED + * This field is reserved. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_RUNTIME_LEVEL + * This field returns the lowest debug level for which logging + * is enabled by default. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_INIT + * This field indicates if logging for the specified component has + * been initialized. Legal values for this parameter include: + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_INIT_NO + * This value indicates NvLog is uninitialized. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_INIT_YES + * This value indicates NvLog has been initialized. + * signature (out) + * This parameter is the signature of the database + * required to decode these logs, autogenerated at buildtime. + * bufferTags (out) + * This parameter identifies the buffer tag used during allocation + * or a value of '0' if buffer is unallocated for each possible + * buffer. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT if components are invalid. + */ +#define NV0000_CTRL_CMD_NVD_GET_NVLOG_INFO (0x604) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS_MESSAGE_ID" */ + +/* maximum size of the runtimeSizes array */ +#define NV0000_CTRL_NVD_MAX_RUNTIME_SIZES (16) + +/* size of signature parameter */ +#define NV0000_CTRL_NVD_SIGNATURE_SIZE (4) + +/* Maximum number of buffers */ +#define NV0000_CTRL_NVD_MAX_BUFFERS (256) + +#define NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS { + NvU32 component; + NvU32 version; + NvU8 runtimeSizes[NV0000_CTRL_NVD_MAX_RUNTIME_SIZES]; + NvU32 printFlags; + NvU32 signature[NV0000_CTRL_NVD_SIGNATURE_SIZE]; + NvU32 bufferTags[NV0000_CTRL_NVD_MAX_BUFFERS]; +} NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS; + +/* runtimeSize array indices */ +#define NV0000_CTRL_NVD_RUNTIME_SIZE_UNUSED (0) +#define NV0000_CTRL_NVD_RUNTIME_SIZE_INT (1) +#define NV0000_CTRL_NVD_RUNTIME_SIZE_LONG_LONG (2) +#define NV0000_CTRL_NVD_RUNTIME_SIZE_STRING (3) +#define NV0000_CTRL_NVD_RUNTIME_SIZE_PTR (4) +#define NV0000_CTRL_NVD_RUNTIME_SIZE_CHAR (5) +#define NV0000_CTRL_NVD_RUNTIME_SIZE_FLOAT (6) + +/* printFlags fields and values */ +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_INFO 7:0 +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE 23:8 +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DISABLE (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DEFAULT (0x00000004) +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_RUNTIME_LEVEL 28:25 +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP 30:29 +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_NONE (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32 (0x00000001) +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_64 (0x00000002) +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32_DIFF (0x00000003) +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED 31:31 +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_NO (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_YES (0x00000001) + +/* + * NV0000_CTRL_CMD_NVD_GET_NVLOG_BUFFER_INFO + * + * This command gets the current state of a specific buffer in the NvLog + * buffer system. + * + * component (in) + * This parameter specifies the system dump component for which the + * NvLog info is desired. Legal values for this parameter must + * be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG and + * less than NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED. + * buffer (in/out) + * This parameter specifies the buffer number from which to retrieve the + * buffer information. Valid values are 0 to (NV0000_CTRL_NVD_MAX_BUFFERS - 1). + * If the buffer is specified using the 'tag' parameter, the buffer + * number is returned through this one. + * tag (in/out) + * If this parameter is non-zero, it will be used to specify the buffer, + * instead of 'buffer' parameter. It returns the tag of the specified buffer + * size (out) + * This parameter returns the size of the specified buffer. + * flags (in/out) + * On input, this parameter sets the following behavior: + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE + * This flag controls if the nvlog system should pause output + * to this buffer. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_YES + * The buffer should be paused until another command + * unpauses this buffer. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_NO + * The buffer should not be paused. + * On output, this parameter returns the flags of a specified buffer: + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED + * This flag indicates if logging to the specified buffer is + * disabled or not. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE + * This flag indicates the buffer logging type: + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_RING + * This type value indicates logging to the buffer wraps. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_NOWRAP + * This type value indicates logging to the buffer does not wrap. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE + * This flag indicates if the buffer size is expandable. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_NO + * The buffer is not expandable. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_YES + * The buffer is expandable. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NON_PAGED + * This flag indicates if the buffer occupies non-paged or pageable + * memory. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NON_PAGED_NO + * The buffer is in pageable memory. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NON_PAGES_YES + * The buffer is in non-paged memory. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING + * This flag indicates the locking mode for the specified buffer. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_NONE + * This locking value indicates that no locking is performed. This + * locking mode is typically used for inherently single-threaded + * buffers. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_STATE + * This locking value indicates that the buffer is locked only + * during state changes and that memory copying is unlocked. This + * mode should not be used tiny buffers that overflow every write + * or two. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_FULL + * This locking value indicates the buffer is locked for the full + * duration of the write. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA + * This flag indicates if the buffer is stored in OCA dumps. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_NO + * The buffer is not included in OCA dumps. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_YES + * The buffer is included in OCA dumps. + * pos (out) + * This parameter is the current position of the tracker/cursor in the + * buffer. + * overflow (out) + * This parameter is the number of times the buffer has overflowed. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT if components are invalid. + */ + +#define NV0000_CTRL_CMD_NVD_GET_NVLOG_BUFFER_INFO (0x605) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS { + NvU32 component; + NvU32 buffer; + NvU32 tag; + NvU32 size; + NvU32 flags; + NvU32 pos; + NvU32 overflow; +} NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS; + +/* flags fields and values */ +/* input */ +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE 0:0 +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_NO (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_YES (0x00000001) + +/* output */ +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED 0:0 +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_NO (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_YES (0x00000001) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE 1:1 +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_RING (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_NOWRAP (0x00000001) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE 2:2 +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_NO (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_YES (0x00000001) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED 3:3 +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_NO (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_YES (0x00000001) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING 5:4 +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_NONE (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_STATE (0x00000001) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_FULL (0x00000002) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA 6:6 +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_NO (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_YES (0x00000001) + +/* + * NV0000_CTRL_CMD_NVD_GET_NVLOG + * + * This command retrieves the specified dump block from the specified + * NvLog buffer. To retrieve the entire buffer, the caller should start + * with blockNum set to 0 and continue issuing calls with an incremented + * blockNum until the returned size value is less than + * NV0000_CTRL_NVD_NVLOG_MAX_BLOCK_SIZE. + * + * component (in) + * This parameter specifies the system dump component for which the NvLog + * dump operation is to be directed. Legal values for this parameter + * must be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG + * and less than NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED. + * buffer (in) + * This parameter specifies the NvLog buffer to dump. + * blockNum (in) + * This parameter specifies the block number for which data is to be + * dumped. + * size (in/out) + * On entry, this parameter specifies the maximum length in bytes for + * the returned data (should be set to NV0000_CTRL_NVLOG_MAX_BLOCK_SIZE). + * On exit, it specifies the number of bytes returned. + * data (out) + * This parameter returns the data for the specified block. The size + * patameter values indicates the number of valid bytes returned. + * + * Possible status values returned are: + * NV_OK + * NVOS_ERROR_INVALID_ARGUMENT if components are invalid. + */ +#define NV0000_CTRL_CMD_NVD_GET_NVLOG (0x606) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_NVLOG_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_NVLOG_MAX_BLOCK_SIZE (4000) + +#define NV0000_CTRL_NVD_GET_NVLOG_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV0000_CTRL_NVD_GET_NVLOG_PARAMS { + NvU32 component; + NvU32 buffer; + NvU32 blockNum; + NvU32 size; + NvU8 data[NV0000_CTRL_NVLOG_MAX_BLOCK_SIZE]; +} NV0000_CTRL_NVD_GET_NVLOG_PARAMS; + +/* + * NV0000_CTRL_CMD_NVD_GET_RCERR_RPT + * + * This command returns block of registers that were recorded at the time + * of an RC error for the current process. + * + * reqIdx: + * [IN] the index of the report being requested. + * index rolls over to 0. + * if the requested index is not in the circular buffer, then no data is + * transferred & either NV_ERR_INVALID_INDEX (indicating the specified + * index is not in the table) is returned. + * + * rptIdx: + * [OUT] the index of the report being returned. + * if the requested index is not in the circular buffer, then the value is + * undefined, no data istransferred & NV_ERR_INVALID_INDEX is returned. + * if the the specified index is present, but does not meet the requested + * criteria (refer to the owner & processId fields). the rptIdx will be + * set to a value that does not match the reqIdx, and no data will be + * transferred. NV_ERR_INSUFFICIENT_PERMISSIONS is still returned. + * + * gpuTag: + * [OUT] id of the GPU whose data was collected. + * + * rptTimeInNs: + * [OUT] the timestamp for when the report was created. + * + * startIdx: + * [OUT] the index of the oldest start record for the first report that + * matches the specified criteria (refer to the owner & processId + * fields). If no records match the specified criteria, this value is + * undefined, the failure code NV_ERR_MISSING_TABLE_ENTRY will + * be returned, and no data will be transferred. + * + * endIdx: + * [OUT] the index of the newest end record for the most recent report that + * matches the specified criteria (refer to the owner & processId + * fields). If no records match the specified criteria, this value is + * undefined, the failure code NV_ERR_MISSING_TABLE_ENTRY will + * be returned, and no data will be transferred. + * + * rptType: + * [OUT] indicator of what data is in the report. + * + * flags + * [OUT] a set odf flags indicating attributes of the record + * NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_FIRST -- indicates this is the first record of a report. + * NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_LAST -- indicates this is the last record of the report. + * NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_RANGE_VALID -- indicates this is the response contains a valid +* index range. + * Note, this may be set when an error is returned indicating a valid range was found, but event of + * the requested index was not. + * NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_DATA_VALID -- indicates this is the response contains valid data. + * + * rptCount: + * [OUT] number of entries returned in report. + * + * owner: + * [IN] Entries are only returned if they have the same owner as the specified owner or the specified + * owner Id is NV0000_CTRL_CMD_NVD_RPT_ANY_OWNER_ID. + * if the requested index is not owned by the specified owner, the rptIdx + * will be set to a value that does not match the reqIdx, and no data will + * be transferred. NV_ERR_INSUFFICIENT_PERMISSIONS is returned. + * + * processId: + * [IN] Deprecated + * report: + * [OUT] array of rptCount enum/value pair entries containing the data from the report. + * entries beyond rptCount are undefined. + * + * + * Possible status values returned are: + * NV_OK -- we found & transferred the requested record. + * NV_ERR_MISSING_TABLE_ENTRY -- we don't find any records that meet the criteria. + * NV_ERR_INVALID_INDEX -- the requested index was not found in the buffer. + * NV_ERR_INSUFFICIENT_PERMISSIONS -- the requested record was found, but it did not meet the criteria. + * NV_ERR_BUSY_RETRY -- We could not access the circular buffer. + * + */ + +#define NV0000_CTRL_CMD_NVD_GET_RCERR_RPT (0x607) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_MAX_ENTRIES 200 + +// report types +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_TEST 0 +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GRSTATUS 1 +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GPCSTATUS 2 +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_MMU_FAULT_STATUS 3 + +// pseudo register enums attribute content +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_EMPTY 0x00000000 +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_OVERFLOWED 0x00000001 // number of missed entries. +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_MAX_PSEDO_REG 0x0000000f + + + +// Flags Definitions +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_FIRST 0x00000001 // indicates this is the first record of a report. +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_LAST 0x00000002 // indicates this is the last record of the report. +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_RANGE_VALID 0x00000004 // indicates this is the response contains a valid range +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_DATA_VALID 0x00000008 // indicates this is the response contains valid data + + +// Attribute Definitions +#define TPC_REG_ATTR(gpcId, tpcId) ((gpcId << 8) | (tpcId)) +#define ROP_REG_ATTR(gpcId, ropId) ((gpcId << 8) | (ropId)) +#define SM_REG_ATTR(gpcId, tpcId, smId) ((((gpcId) << 16) | ((tpcId) << 8)) | (smId)) + +// Process Id Pseudo values +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_PROCESS_ID 0x00000000 // get report for any process ID + +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_OWNER_ID 0xFFFFFFFF // get report for any owner ID + + +typedef struct NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY { + NvU32 tag; + NvU32 value; + NvU32 attribute; +} NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY; + +#define NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS { + NvU16 reqIdx; + NvU16 rptIdx; + NvU32 GPUTag; + NvU32 rptTime; // time in seconds since 1/1/1970 + NvU16 startIdx; + NvU16 endIdx; + NvU16 rptType; + NvU32 flags; + NvU16 rptCount; + NvU32 owner; // indicating whose reports to get + NvU32 processId; // deprecated field + + NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY report[NV0000_CTRL_CMD_NVD_RCERR_RPT_MAX_ENTRIES]; +} NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS; + +/* + * NV0000_CTRL_CMD_NVD_GET_DPC_ISR_TS + * + * This command returns the time stamp information that are collected from + * the execution of various DPCs/ISRs. This time stamp information is for + * debugging purposes only and would help with analyzing regressions and + * latencies for DPC/ISR execution times. + * + * tsBufferSize + * This field specifies the size of the buffer that the caller allocates. + * tsBuffer + * THis field specifies a pointer in the callers address space to the + * buffer into which the timestamp info on DPC/ISR is to be returned. + * This buffer must at least be as big as tsBufferSize. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV0000_CTRL_CMD_NVD_GET_DPC_ISR_TS (0x608) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS { + NvU32 tsBufferSize; + NV_DECLARE_ALIGNED(NvP64 pTSBuffer, 8); +} NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS; + +/* _ctrl0000nvd_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h new file mode 100644 index 0000000..9a48202 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h @@ -0,0 +1,98 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000proc.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" +#include "nvlimits.h" + +/* + * NV0000_CTRL_CMD_SET_SUB_PROCESS_ID + * + * Save the sub process ID and sub process name in client database + * subProcID + * Sub process ID + * subProcessName + * Sub process name + * + * In vGPU environment, sub process means the guest user/kernel process running + * within a single VM. It also refers to any sub process (or sub-sub process) + * within a parent process. + * + * Please refer to the wiki for more details about sub process concept: Resource_Server + * + * Possible return values are: + * NV_OK + */ +#define NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS { + NvU32 subProcessID; + char subProcessName[NV_PROC_NAME_MAX_LENGTH]; +} NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS; + +/* + * NV0000_CTRL_CMD_DISABLE_SUB_PROCESS_USERD_ISOLATION + * + * Disable sub process USERD isolation. + * bIsSubProcIsolated + * NV_TRUE to disable sub process USERD isolation + * + * USERD allocated by different domains should not be put into the same physical page. + * This provides the basic security isolation because a physical page is the unit of + * granularity at which OS can provide isolation between processes. + * + * GUEST_USER: USERD allocated by guest user process + * GUEST_KERNEL: USERD allocated by guest kernel process + * GUEST_INSECURE: USERD allocated by guest/kernel process, + * INSECURE means there is no isolation between guest user and guest kernel + * HOST_USER: USERD allocated by host user process + * HOST_KERNEL: USERD allocated by host kernel process + * + * When sub process USERD isolation is disabled, we won't distinguish USERD allocated by guest + * user and guest kernel. They all belong to the GUEST_INSECURE domain. + * + * Please refer to wiki for more details: RM_USERD_Isolation + * + * Possible return values are: + * NV_OK + */ +#define NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS { + NvBool bIsSubProcessDisabled; +} NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS; + +#define NV0000_CTRL_CMD_SET_SUB_PROCESS_ID (0x901) /* finn: Evaluated from "(FINN_NV01_ROOT_PROC_INTERFACE_ID << 8) | NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_DISABLE_SUB_PROCESS_USERD_ISOLATION (0x902) /* finn: Evaluated from "(FINN_NV01_ROOT_PROC_INTERFACE_ID << 8) | NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS_MESSAGE_ID" */ + +/* _ctrl0000proc_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h new file mode 100644 index 0000000..b8e921e --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h @@ -0,0 +1,112 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000syncgpuboost.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +#include "nvtypes.h" +#include "nvlimits.h" + +/* --------------------------- Macros ----------------------------------------*/ +// There are at least 2 GPUs in a sync group. Hence max is half of max devices. +#define NV0000_SYNC_GPU_BOOST_MAX_GROUPS (0x10) /* finn: Evaluated from "((NV_MAX_DEVICES) >> 1)" */ +#define NV0000_SYNC_GPU_BOOST_INVALID_GROUP_ID 0xFFFFFFFF + +/*-------------------------Command Prototypes---------------------------------*/ + +/*! + * Query whether SYNC GPU BOOST MANAGER is enabled or disabled. + */ +#define NV0000_CTRL_CMD_SYNC_GPU_BOOST_INFO (0xa01) /* finn: Evaluated from "(FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID << 8) | NV0000_SYNC_GPU_BOOST_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_SYNC_GPU_BOOST_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_SYNC_GPU_BOOST_INFO_PARAMS { + // [out] Specifies if Sync Gpu Boost Manager is enabled or not. + NvBool bEnabled; +} NV0000_SYNC_GPU_BOOST_INFO_PARAMS; + +/*! + * Creates a Synchronized GPU-Boost Group (SGBG) + */ +#define NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_CREATE (0xa02) /* finn: Evaluated from "(FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID << 8) | NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS_MESSAGE_ID" */ + +/*! + * Describes a Synchronized GPU-Boost Group configuration + */ +typedef struct NV0000_SYNC_GPU_BOOST_GROUP_CONFIG { + // [in] Number of elements in @ref gpuIds + NvU32 gpuCount; + + // [in] IDs of GPUs to be put in the Sync Boost Group + NvU32 gpuIds[NV_MAX_DEVICES]; + + // [out] Unique ID of the SGBG, if created + NvU32 boostGroupId; + + // [in] If this group represents bridgeless SLI + NvBool bBridgeless; +} NV0000_SYNC_GPU_BOOST_GROUP_CONFIG; + +#define NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS { + NV0000_SYNC_GPU_BOOST_GROUP_CONFIG boostConfig; +} NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS; + +/*! + * Destroys a previously created Synchronized GPU-Boost Group(SGBG) + */ +#define NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_DESTROY (0xa03) /* finn: Evaluated from "(FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID << 8) | NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS_MESSAGE_ID" */ + +#define NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS { + // [[in] Unique ID of the SGBG to be destroyed + NvU32 boostGroupId; +} NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS; + +/*! + * Get configuration information for all Synchronized Boost Groups in the system. + */ +#define NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_INFO (0xa04) /* finn: Evaluated from "(FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID << 8) | NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS { + // [out] Number of groups retrieved. @ref NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS::boostGroups + NvU32 groupCount; + + // [out] @ref NV0000_SYNC_GPU_BOOST_GROUP_CONFIG + NV0000_SYNC_GPU_BOOST_GROUP_CONFIG pBoostGroups[NV0000_SYNC_GPU_BOOST_MAX_GROUPS]; +} NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS; + +/* _ctrl0000syncgpuboost_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h new file mode 100644 index 0000000..74b65c7 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h @@ -0,0 +1,2915 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000system.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl0000/ctrl0000base.h" + +/* NV01_ROOT (client) system control commands and parameters */ + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_FEATURES + * + * This command returns a mask of supported features for the SYSTEM category + * of the 0000 class. + * + * Valid features include: + * + * NV0000_CTRL_GET_FEATURES_SLI + * When this bit is set, SLI is supported. + * NV0000_CTRL_GET_FEATURES_UEFI + * When this bit is set, it is a UEFI system. + * NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT + * When this bit is set, EFI has initialized core channel + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_FEATURES (0x1f0U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID (0xF0U) + +typedef struct NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS { + NvU32 featuresMask; +} NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS; + + + +/* Valid feature values */ +#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI 0:0 +#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI 1:1 +#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT 2:2 +#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE (0x00000001U) +/* + * NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION + * + * This command returns the current driver information. + * The first time this is called the size of strings is + * set with the greater of NV_BUILD_BRANCH_VERSION and + * NV_DISPLAY_DRIVER_TITLE. The client then allocates memory + * of size sizeOfStrings for pVersionBuffer and pTitleBuffer + * and calls the command again to receive driver info. + * + * sizeOfStrings + * This field returns the size in bytes of the pVersionBuffer and + * pTitleBuffer strings. + * pDriverVersionBuffer + * This field returns the version (NV_VERSION_STRING). + * pVersionBuffer + * This field returns the version (NV_BUILD_BRANCH_VERSION). + * pTitleBuffer + * This field returns the title (NV_DISPLAY_DRIVER_TITLE). + * changelistNumber + * This field returns the changelist value (NV_BUILD_CHANGELIST_NUM). + * officialChangelistNumber + * This field returns the last official changelist value + * (NV_LAST_OFFICIAL_CHANGELIST_NUM). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION (0x101U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS { + NvU32 sizeOfStrings; + NV_DECLARE_ALIGNED(NvP64 pDriverVersionBuffer, 8); + NV_DECLARE_ALIGNED(NvP64 pVersionBuffer, 8); + NV_DECLARE_ALIGNED(NvP64 pTitleBuffer, 8); + NvU32 changelistNumber; + NvU32 officialChangelistNumber; +} NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO + * + * This command returns system CPU information. + * + * type + * This field returns the processor type. + * Legal processor types include: + * Intel processors: + * P55 : P55C - MMX + * P6 : PPro + * P2 : PentiumII + * P2XC : Xeon & Celeron + * CELA : Celeron-A + * P3 : Pentium-III + * P3_INTL2 : Pentium-III w/integrated L2 (fullspeed, on die, 256K) + * P4 : Pentium 4 + * CORE2 : Core2 Duo Conroe + * AMD processors + * K62 : K6-2 w/ 3DNow + * IDT/Centaur processors + * C6 : WinChip C6 + * C62 : WinChip 2 w/ 3DNow + * Cyrix processors + * GX : MediaGX + * M1 : 6x86 + * M2 : M2 + * MGX : MediaGX w/ MMX + * Transmeta processors + * TM_CRUSOE : Transmeta Crusoe(tm) + * PowerPC processors + * PPC603 : PowerPC 603 + * PPC604 : PowerPC 604 + * PPC750 : PowerPC 750 + * + * capabilities + * This field returns the capabilities of the processor. + * Legal processor capabilities include: + * MMX : supports MMX + * SSE : supports SSE + * 3DNOW : supports 3DNow + * SSE2 : supports SSE2 + * SFENCE : supports SFENCE + * WRITE_COMBINING : supports write-combining + * ALTIVEC : supports ALTIVEC + * PUT_NEEDS_IO : requires OUT inst w/PUT updates + * NEEDS_WC_WORKAROUND : requires workaround for P4 write-combining bug + * 3DNOW_EXT : supports 3DNow Extensions + * MMX_EXT : supports MMX Extensions + * CMOV : supports CMOV + * CLFLUSH : supports CLFLUSH + * SSE3 : supports SSE3 + * NEEDS_WAR_124888 : requires write to GPU while spinning on + * : GPU value + * HT : support hyper-threading + * clock + * This field returns the processor speed in MHz. + * L1DataCacheSize + * This field returns the level 1 data (or unified) cache size + * in kilobytes. + * L2DataCacheSize + * This field returns the level 2 data (or unified) cache size + * in kilobytes. + * dataCacheLineSize + * This field returns the bytes per line in the level 1 data cache. + * numLogicalCpus + * This field returns the number of logical processors. On Intel x86 + * systems that support it, this value will incorporate the current state + * of HyperThreading. + * numPhysicalCpus + * This field returns the number of physical processors. + * name + * This field returns the CPU name in ASCII string format. + * family + * Vendor defined Family and Extended Family combined + * model + * Vendor defined Model and Extended Model combined + * stepping + * Silicon stepping + * bSEVEnabled + * Secure Encrypted Virtualization enabled/disabled state + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO (0x102U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS { + NvU32 type; /* processor type */ + NvU32 capabilities; /* processor caps */ + NvU32 clock; /* processor speed (MHz) */ + NvU32 L1DataCacheSize; /* L1 dcache size (KB) */ + NvU32 L2DataCacheSize; /* L2 dcache size (KB) */ + NvU32 dataCacheLineSize; /* L1 dcache bytes/line */ + NvU32 numLogicalCpus; /* logial processor cnt */ + NvU32 numPhysicalCpus; /* physical processor cnt*/ + NvU8 name[52]; /* embedded cpu name */ + NvU32 family; /* Vendor defined Family and Extended Family combined */ + NvU32 model; /* Vendor defined Model and Extended Model combined */ + NvU8 stepping; /* Silicon stepping */ + NvU32 coresOnDie; /* cpu cores per die */ + NvBool bSEVEnabled; /* SEV enabled on cpu */ +} NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS; + +// Macros for CPU family information +#define NV0000_CTRL_SYSTEM_CPU_FAMILY 3:0 +#define NV0000_CTRL_SYSTEM_CPU_EXTENDED_FAMILY 11:4 + +// Macros for CPU model information +#define NV0000_CTRL_SYSTEM_CPU_MODEL 3:0 +#define NV0000_CTRL_SYSTEM_CPU_EXTENDED_MODEL 7:4 + +// Macros for AMD CPU information +#define NV0000_CTRL_SYSTEM_CPU_ID_AMD_FAMILY 0xF +#define NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_FAMILY 0xA +#define NV0000_CTRL_SYSTEM_CPU_ID_AMD_MODEL 0x0 +#define NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_MODEL 0x4 + +// Macros for Intel CPU information +#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_FAMILY 0x6 +#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_FAMILY 0x0 +#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_S_MODEL 0x7 +#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_P_MODEL 0xA +#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_MODEL 0x9 + +/* processor type values */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_UNKNOWN (0x00000000U) +/* Intel types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P5 (0x00000001U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P55 (0x00000002U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P6 (0x00000003U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P2 (0x00000004U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P2XC (0x00000005U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_CELA (0x00000006U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P3 (0x00000007U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P3_INTL2 (0x00000008U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P4 (0x00000009U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2 (0x00000010U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_CELN_M16H (0x00000011U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2_EXTRM (0x00000012U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_ATOM (0x00000013U) +/* AMD types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K5 (0x00000030U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K6 (0x00000031U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K62 (0x00000032U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K63 (0x00000033U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K7 (0x00000034U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K8 (0x00000035U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K10 (0x00000036U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K11 (0x00000037U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_RYZEN (0x00000038U) +/* IDT/Centaur types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_C6 (0x00000060U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_C62 (0x00000061U) +/* Cyrix types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_GX (0x00000070U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_M1 (0x00000071U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_M2 (0x00000072U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_MGX (0x00000073U) +/* Transmeta types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_TM_CRUSOE (0x00000080U) +/* IBM types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC603 (0x00000090U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC604 (0x00000091U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC750 (0x00000092U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_POWERN (0x00000093U) +/* Unknown ARM architecture CPU type */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_UNKNOWN (0xA0000000U) +/* ARM Ltd types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A9 (0xA0000009U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A15 (0xA000000FU) +/* NVIDIA types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_1_0 (0xA0001000U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_2_0 (0xA0002000U) + +/* Generic types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC (0xA00FF000U) + + + +/* processor capabilities */ +#define NV0000_CTRL_SYSTEM_CPU_CAP_MMX (0x00000001U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE (0x00000002U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW (0x00000004U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 (0x00000008U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE (0x00000010U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING (0x00000020U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC (0x00000040U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_PUT_NEEDS_IO (0x00000080U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WC_WORKAROUND (0x00000100U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT (0x00000200U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT (0x00000400U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_CMOV (0x00000800U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH (0x00001000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_190854 (0x00002000U) /* deprecated */ +#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 (0x00004000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_124888 (0x00008000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE (0x00010000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 (0x00020000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 (0x00040000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_AVX (0x00080000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_ERMS (0x00100000U) + +/* feature mask (as opposed to bugs, requirements, etc.) */ +#define NV0000_CTRL_SYSTEM_CPU_CAP_FEATURE_MASK (0x1f5e7fU) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_CPU_CAP_MMX | NV0000_CTRL_SYSTEM_CPU_CAP_SSE | NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW | NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 | NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE | NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING | NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC | NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT | NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT | NV0000_CTRL_SYSTEM_CPU_CAP_CMOV | NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH | NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 | NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE | NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 | NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 | NV0000_CTRL_SYSTEM_CPU_CAP_AVX | NV0000_CTRL_SYSTEM_CPU_CAP_ERMS)" */ + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_CAPS + * + * This command returns the set of system capabilities in the + * form of an array of unsigned bytes. System capabilities include + * supported features and required workarounds for the system, + * each represented by a byte offset into the table and a bit + * position within that byte. + * + * capsTblSize + * This parameter specifies the size in bytes of the caps table. + * This value should be set to NV0000_CTRL_SYSTEM_CAPS_TBL_SIZE. + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the system caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_CAPS (0x103U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x3" */ + +typedef struct NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS { + NvU32 capsTblSize; + NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); +} NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS; + +/* extract cap bit setting from tbl */ +#define NV0000_CTRL_SYSTEM_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* caps format is byte_index:bit_mask */ +#define NV0000_CTRL_SYSTEM_CAPS_POWER_SLI_SUPPORTED 0:0x01 + +/* size in bytes of system caps table */ +#define NV0000_CTRL_SYSTEM_CAPS_TBL_SIZE 1U + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO + * + * This command returns system chipset information. + * + * vendorId + * This parameter returns the vendor identification for the chipset. + * A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the chipset + * cannot be identified. + * deviceId + * This parameter returns the device identification for the chipset. + * A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the chipset + * cannot be identified. + * subSysVendorId + * This parameter returns the subsystem vendor identification for the + * chipset. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the + * chipset cannot be identified. + * subSysDeviceId + * This parameter returns the subsystem device identification for the + * chipset. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the + * chipset cannot be identified. + * HBvendorId + * This parameter returns the vendor identification for the chipset's + * host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates + * the chipset's host bridge cannot be identified. + * HBdeviceId + * This parameter returns the device identification for the chipset's + * host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates + * the chipset's host bridge cannot be identified. + * HBsubSysVendorId + * This parameter returns the subsystem vendor identification for the + * chipset's host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID + * indicates the chipset's host bridge cannot be identified. + * HBsubSysDeviceId + * This parameter returns the subsystem device identification for the + * chipset's host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID + * indicates the chipset's host bridge cannot be identified. + * sliBondId + * This parameter returns the SLI bond identification for the chipset. + * vendorNameString + * This parameter returns the vendor name string. + * chipsetNameString + * This parameter returns the vendor name string. + * sliBondNameString + * This parameter returns the SLI bond name string. + * flag + * This parameter specifies NV0000_CTRL_SYSTEM_CHIPSET_FLAG_XXX flags: + * _HAS_RESIZABLE_BAR_ISSUE_YES: Chipset where the use of resizable BAR1 + * should be disabled - bug 3440153 + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO (0x104U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID" */ + +/* maximum name string length */ +#define NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH (0x0000020U) + +/* invalid id */ +#define NV0000_SYSTEM_CHIPSET_INVALID_ID (0xffffU) + +#define NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS { + NvU16 vendorId; + NvU16 deviceId; + NvU16 subSysVendorId; + NvU16 subSysDeviceId; + NvU16 HBvendorId; + NvU16 HBdeviceId; + NvU16 HBsubSysVendorId; + NvU16 HBsubSysDeviceId; + NvU32 sliBondId; + NvU8 vendorNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; + NvU8 subSysVendorNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; + NvU8 chipsetNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; + NvU8 sliBondNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; + NvU32 flags; +} NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS; + +#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE 0:0 +#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_NO (0x00000000U) +#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_YES (0x00000001U) + + + +/* + * NV0000_CTRL_CMD_SYSTEM_SET_MEMORY_SIZE + * + * This command is used to set the system memory size in pages. + * + * memorySize + * This parameter specifies the system memory size in pages. All values + * are considered legal. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0000_CTRL_CMD_SYSTEM_SET_MEMORY_SIZE (0x107U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS { + NvU32 memorySize; +} NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST + * + * This command is used to retrieve the set of system-level classes + * supported by the platform. + * + * numClasses + * This parameter returns the number of valid entries in the returned + * classes[] list. This parameter will not exceed + * Nv0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE. + * classes + * This parameter returns the list of supported classes + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST (0x108U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID" */ + +/* maximum number of classes returned in classes[] array */ +#define NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE (32U) + +#define NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS { + NvU32 numClasses; + NvU32 classes[NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE]; +} NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT + * + * This command is used to send triggered mobile related system events + * to the RM. + * + * eventType + * This parameter indicates the triggered event type. This parameter + * should specify a valid NV0000_CTRL_SYSTEM_EVENT_TYPE value. + * eventData + * This parameter specifies the type-dependent event data associated + * with EventType. This parameter should specify a valid + * NV0000_CTRL_SYSTEM_EVENT_DATA value. + * bEventDataForced + * This parameter specifies what we have to do, Whether trust current + * Lid/Dock state or not. This parameter should specify a valid + * NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED value. + + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * Sync this up (#defines) with one in nvapi.spec! + * (NV_ACPI_EVENT_TYPE & NV_ACPI_EVENT_DATA) + */ +#define NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT (0x110U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS { + NvU32 eventType; + NvU32 eventData; + NvBool bEventDataForced; +} NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS; + +/* valid eventType values */ +#define NV0000_CTRL_SYSTEM_EVENT_TYPE_LID_STATE (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_TYPE_POWER_SOURCE (0x00000001U) +#define NV0000_CTRL_SYSTEM_EVENT_TYPE_DOCK_STATE (0x00000002U) +#define NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_LID (0x00000003U) +#define NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_DOCK (0x00000004U) + +/* valid eventData values */ +#define NV0000_CTRL_SYSTEM_EVENT_DATA_LID_OPEN (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_LID_CLOSED (0x00000001U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_BATTERY (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_AC (0x00000001U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_UNDOCKED (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_DOCKED (0x00000001U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DSM (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DCS (0x00000001U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_NVIF (0x00000002U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_ACPI (0x00000003U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL (0x00000004U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_COUNT (0x5U) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL + 1)" */ +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DSM (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DCS (0x00000001U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_NVIF (0x00000002U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_ACPI (0x00000003U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL (0x00000004U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_COUNT (0x5U) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL + 1)" */ + +/* valid bEventDataForced values */ +#define NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_TRUE (0x00000001U) + +/* + * NV000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE + * + * This command is used to query the platform type. + * + * systemType + * This parameter returns the type of the system. + * Legal values for this parameter include: + * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP + * The system is a desktop platform. + * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC + * The system is a mobile (non-Toshiba) platform. + * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP + * The system is a mobile Toshiba platform. + * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC + * The system is a system-on-a-chip (SOC) platform. + * + + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE (0x111U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS { + NvU32 systemType; +} NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS; + +/* valid systemType values */ +#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP (0x000000U) +#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC (0x000001U) +#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_TOSHIBA (0x000002U) +#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC (0x000003U) + + + + +/* + * NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL + * + * This command controls the current RmMsg filters. + * + * It is only supported if RmMsg is enabled (e.g. debug builds). + * + * cmd + * GET - Gets the current RmMsg filter string. + * SET - Sets the current RmMsg filter string. + * + * count + * The length of the RmMsg filter string. + * + * data + * The RmMsg filter string. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL (0x121U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE 512U + +#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_GET (0x00000000U) +#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_SET (0x00000001U) + +#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID (0x21U) + +typedef struct NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS { + NvU32 cmd; + NvU32 count; + NvU8 data[NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE]; +} NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS; + +/* + * NV0000_CTRL_SYSTEM_HWBC_INFO + * + * This structure contains information about the HWBC (BR04) specified by + * hwbcId. + * + * hwbcId + * This field specifies the HWBC ID. + * firmwareVersion + * This field returns the version of the firmware on the HWBC (BR04), if + * present. This is a packed binary number of the form 0x12345678, which + * corresponds to a firmware version of 12.34.56.78. + * subordinateBus + * This field returns the subordinate bus number of the HWBC (BR04). + * secondaryBus + * This field returns the secondary bus number of the HWBC (BR04). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +typedef struct NV0000_CTRL_SYSTEM_HWBC_INFO { + NvU32 hwbcId; + NvU32 firmwareVersion; + NvU32 subordinateBus; + NvU32 secondaryBus; +} NV0000_CTRL_SYSTEM_HWBC_INFO; + +#define NV0000_CTRL_SYSTEM_HWBC_INVALID_ID (0xFFFFFFFFU) + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO + * + * This command returns information about all Hardware Broadcast (HWBC) + * devices present in the system that are BR04s. To get the complete + * list of HWBCs in the system, all GPUs present in the system must be + * initialized. See the description of NV0000_CTRL_CMD_GPU_ATTACH_IDS to + * accomplish this. + * + * hwbcInfo + * This field is an array of NV0000_CTRL_SYSTEM_HWBC_INFO structures into + * which HWBC information is placed. There is one entry for each HWBC + * present in the system. Valid entries are contiguous, invalid entries + * have the hwbcId equal to NV0000_CTRL_SYSTEM_HWBC_INVALID_ID. If no HWBC + * is present in the system, all the entries would be marked invalid, but + * the return value would still be SUCCESS. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO (0x124U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_MAX_HWBCS (0x00000080U) + +#define NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID (0x24U) + +typedef struct NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS { + NV0000_CTRL_SYSTEM_HWBC_INFO hwbcInfo[NV0000_CTRL_SYSTEM_MAX_HWBCS]; +} NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL + * + * This command is used to control GPS functionality. It allows control of + * GPU Performance Scaling (GPS), changing its operational parameters and read + * most GPS dynamic parameters. + * + * command + * This parameter specifies the command to execute. Invalid commands + * result in the return of an NV_ERR_INVALID_ARGUMENT status. + * locale + * This parameter indicates the specific locale to which the command + * 'command' is to be applied. + * Supported range of CPU/GPU {i = 0, ..., 255} + * data + * This parameter contains a command-specific data payload. It can + * be used to input data as well as output data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_COMMAND + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_DATA + * NV_ERR_INVALID_REQUEST + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL (0x122U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS { + NvU16 command; + NvU16 locale; + NvU32 data; +} NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS; + +/* + * Valid command values : + * + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT + * Is used to check if GPS was correctly initialized. + * Possible return (OUT) values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC + * Are used to stop/start GPS functionality and to get current status. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS + * Are used to control execution of GPS actions and to get current status. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC + * Are used to switch current GPS logic and to retrieve current logic. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF + * Will cause that all GPS actions will be NULL. + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY + * Fuzzy logic will determine GPS actions based on current ruleset. + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC + * Deterministic logic will define GPS actions based on current ruleset. + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE + * Are used to set/retrieve system control preference. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT + * Are used to set/retrieve GPU2CPU pstate limits. + * IN/OUT values are four bytes packed into a 32-bit data field. + * The CPU cap index for GPU pstate 0 is in the lowest byte, the CPU cap + * index for the GPU pstate 3 is in the highest byte, etc. One + * special value is to disable the override to the GPU2CPU map: + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE + * Is used to stop/start GPS PMU functionality. + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE + * Is used to get the current status of PMU GPS. + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER + * Are used to set/retrieve max power [mW] that system can provide. + * This is hardcoded GPS safety feature and logic/rules does not apply + * to this threshold. + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET + * Are used to set/retrieve current system cooling budget [mW]. + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD + * Are used to set/retrieve integration interval [sec]. + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT + * Are used to set/retrieve used ruleset [#]. Value is checked + * against MAX number of rules for currently used GPS logic. Also COUNT + * provides a way to find out how many rules exist for the current control + * system. + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST + * Is used to set/get a delay relative to now during which to allow unbound + * CPU performance. Units are seconds. + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE + * Is used to override/get the actual power supply mode (AC/Battery). + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO + * Is used to get the Ventura system information for VCT tool + * Returned 32bit value should be treated as bitmask and decoded in + * following way: + * Encoding details are defined in objgps.h refer to + * NV_GPS_SYS_SUPPORT_INFO and corresponding bit defines. + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTION + * Is used to get the supported sub-functions defined in SBIOS. Returned + * value is a bitmask where each bit corresponds to different function: + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE + * Are used to retrieve appropriate power measurements and their derivatives + * in [mW] for required locale. _BURDEN is defined only for _LOCALE_SYSTEM. + * _INTERMEDIATE is not defined for _LOCALE_SYSTEM, and takes an In value as + * index. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS + * Is used to retrieve parameters when adjusting raw sensor power reading. + * The values may come from SBIOS, VBIOS, registry or driver default. + * Possible IN value is the index of interested parameter. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE + * Are used to retrieve appropriate temperature measurements and their + * derivatives in [1/1000 Celsius]. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX + * Are used to retrieve CPU(x)/GPU(x) p-state or it's limits. + * Not applicable to _LOCALE_SYSTEM. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION + * Is used to retrieve last GPS action for given domain. + * Not applicable to _LOCALE_SYSTEM. + * Possible return (OUT) values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0 + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1 + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1 + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2 + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE + * Is used to set the power sensor simulator state. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE + * Is used to get the power simulator sensor simulator state. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA + * Is used to set power sensor simulator data + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA + * Is used to get power sensor simulator data + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK + * Is used to respond to the ACPI event triggered by SBIOS. RM will + * request value for budget and status, validate them, apply them + * and send ACK back to SBIOS. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT + * Is a test cmd that should notify SBIOS to send ACPI event requesting + * budget and status change. + */ +#define NV0000_CTRL_CMD_SYSTEM_GPS_INVALID (0xFFFFU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT (0x0000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC (0x0001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC (0x0002U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS (0x0003U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS (0x0004U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC (0x0005U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC (0x0006U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE (0x0007U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE (0x0008U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT (0x0009U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT (0x000AU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE (0x000BU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE (0x000CU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER (0x0100U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER (0x0101U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET (0x0102U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET (0x0103U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD (0x0104U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD (0x0105U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET (0x0106U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET (0x0107U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT (0x0108U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST (0x0109U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST (0x010AU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE (0x010BU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE (0x010CU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO (0x010DU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTIONS (0x010EU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER (0x0200U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA (0x0201U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE (0x0202U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG (0x0203U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL (0x0204U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN (0x0205U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE (0x0206U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS (0x0210U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP (0x0220U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA (0x0221U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE (0x0222U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE (0x0240U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP (0x0241U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN (0x0242U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX (0x0243U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION (0x0244U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_SLFM_PRESENT (0x0245U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE (0x0250U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE (0x0251U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA (0x0252U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA (0x0253U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK (0x0320U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT (0x0321U) + +/* valid LOCALE values */ +#define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_INVALID (0xFFFFU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_SYSTEM (0x0000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_CPU(i) (0x0100+((i)%0x100)) +#define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_GPU(i) (0x0200+((i)%0x100)) + +/* valid data values for enums */ +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID (0x80000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE (0xFFFFFFFFU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_ON (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS (0x00000004U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC (0x00000008U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC (0x00000010U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB (0x00000020U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS (0x00000040U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0 (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1 (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT (0x00000003U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1 (0x00000004U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2 (0x00000005U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM (0x00000006U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM (0x00000007U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_NO (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_YES (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_ON (0x00000001U) + +/* + * NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL + * + * This command allows execution of multiple GpsControl commands within one + * RmControl call. For practical reasons # of commands is limited to 16. + * This command shares defines with NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL. + * + * cmdCount + * Number of commands that should be executed. + * Less or equal to NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX. + * + * succeeded + * Number of commands that were succesully executed. + * Less or equal to NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX. + * Failing commands return NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID + * in their data field. + * + * cmdData + * Array of commands with following structure: + * command + * This parameter specifies the command to execute. + * Invalid commands result in the return of an + * NV_ERR_INVALID_ARGUMENT status. + * locale + * This parameter indicates the specific locale to which + * the command 'command' is to be applied. + * Supported range of CPU/GPU {i = 0, ..., 255} + * data + * This parameter contains a command-specific data payload. + * It is used both to input data as well as to output data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL (0x123U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX (16U) +#define NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID (0x23U) + +typedef struct NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS { + NvU32 cmdCount; + NvU32 succeeded; + + struct { + NvU16 command; + NvU16 locale; + NvU32 data; + } cmdData[NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX]; +} NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS; + + +/* + * Deprecated. Please use NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 instead. + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS (0x127U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID" */ + +/* + * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED must remain equal to the square of + * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS due to Check RM parsing issues. + * NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS is the maximum size of GPU groups + * allowed for batched P2P caps queries provided by the RM control + * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX. + */ +#define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS 32U +#define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED 1024U +#define NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS 8U +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER 0xffffffffU + +/* P2P capabilities status index values */ +#define NV0000_CTRL_P2P_CAPS_INDEX_READ 0U +#define NV0000_CTRL_P2P_CAPS_INDEX_WRITE 1U +#define NV0000_CTRL_P2P_CAPS_INDEX_NVLINK 2U +#define NV0000_CTRL_P2P_CAPS_INDEX_ATOMICS 3U +#define NV0000_CTRL_P2P_CAPS_INDEX_PROP 4U +#define NV0000_CTRL_P2P_CAPS_INDEX_LOOPBACK 5U +#define NV0000_CTRL_P2P_CAPS_INDEX_PCI 6U +#define NV0000_CTRL_P2P_CAPS_INDEX_C2C 7U +#define NV0000_CTRL_P2P_CAPS_INDEX_PCI_BAR1 8U + +#define NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE 9U + + +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID (0x27U) + +typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS { + NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; + NvU32 gpuCount; + NvU32 p2pCaps; + NvU32 p2pOptimalReadCEs; + NvU32 p2pOptimalWriteCEs; + NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; + NV_DECLARE_ALIGNED(NvP64 busPeerIds, 8); +} NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS; + +/* valid p2pCaps values */ +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED 0:0 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED 1:1 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED 2:2 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED 3:3 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED 4:4 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED 5:5 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED 6:6 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED 7:7 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED 8:8 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED 9:9 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED 10:10 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_TRUE (0x00000001U) + + +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED 12:12 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED 13:13 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_TRUE (0x00000001U) + +/* P2P status codes */ +#define NV0000_P2P_CAPS_STATUS_OK (0x00U) +#define NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED (0x01U) +#define NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED (0x02U) +#define NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED (0x03U) +#define NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY (0x04U) +#define NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED (0x05U) + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 + * + * This command returns peer to peer capabilities present between GPUs. + * Valid requests must present a list of GPU Ids. + * + * [in] gpuIds + * This member contains the array of GPU IDs for which we query the P2P + * capabilities. Valid entries are contiguous, beginning with the first + * entry in the list. + * [in] gpuCount + * This member contains the number of GPU IDs stored in the gpuIds[] array. + * [out] p2pCaps + * This member returns the peer to peer capabilities discovered between the + * GPUs. Valid p2pCaps values include: + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED + * When this bit is set, peer to peer writes between subdevices owned + * by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED + * When this bit is set, peer to peer reads between subdevices owned + * by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED + * When this bit is set, peer to peer PROP between subdevices owned + * by this device are supported. This is enabled by default + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED + * When this bit is set, PCI is supported for all P2P between subdevices + * owned by this device. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED + * When this bit is set, NVLINK is supported for all P2P between subdevices + * owned by this device. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED + * When this bit is set, peer to peer atomics between subdevices owned + * by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED + * When this bit is set, peer to peer loopback is supported for subdevices + * owned by this device. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED + * When this bit is set, indirect peer to peer writes between subdevices + * owned by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED + * When this bit is set, indirect peer to peer reads between subdevices + * owned by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED + * When this bit is set, indirect peer to peer atomics between + * subdevices owned by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED + * When this bit is set, indirect NVLINK is supported for subdevices + * owned by this device. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED + * When this bit is set, C2C P2P is supported between the GPUs + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_BAR1_SUPPORTED + * When this bit is set, BAR1 P2P is supported between the GPUs + * mentioned in @ref gpuIds + * [out] p2pOptimalReadCEs + * For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink + * [out] p2pOptimalWriteCEs + * For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink + * [out] p2pCapsStatus + * This member returns status of all supported p2p capabilities. Valid + * status values include: + * NV0000_P2P_CAPS_STATUS_OK + * P2P capability is supported. + * NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED + * Chipset doesn't support p2p capability. + * NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED + * GPU doesn't support p2p capability. + * NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED + * IOH topology isn't supported. For e.g. root ports are on different + * IOH. + * NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY + * P2P Capability is disabled by a regkey. + * NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED + * P2P Capability is not supported. + * NV0000_P2P_CAPS_STATUS_NVLINK_SETUP_FAILED + * Indicates that NvLink P2P link setup failed. + * [out] busPeerIds + * Peer ID matrix. It is a one-dimentional array. + * busPeerIds[X * gpuCount + Y] maps from index X to index Y in + * the gpuIds[] table. For invalid or non-existent peer busPeerIds[] + * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ + + + +#define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 (0x12bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID (0x2BU) + +typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS { + NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; + NvU32 gpuCount; + NvU32 p2pCaps; + NvU32 p2pOptimalReadCEs; + NvU32 p2pOptimalWriteCEs; + NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; + NvU32 busPeerIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED]; +} NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX + * + * This command returns peer to peer capabilities present between all pairs of + * GPU IDs {(a, b) : a in gpuIdGrpA and b in gpuIdGrpB}. This can be used to + * collect all P2P capabilities in the system - see the SRT: + * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX_TEST + * for a demonstration. + * + * The call will query for all pairs between set A and set B, and returns + * results in both link directions. The results are two-dimensional arrays where + * the first dimension is the index within the set-A array of one GPU ID under + * consideration, and the second dimension is the index within the set-B array + * of the other GPU ID under consideration. + * + * That is, the result arrays are *ALWAYS* to be indexed first with the set-A + * index, then with the set-B index. The B-to-A direction of results are put in + * the b2aOptimal(Read|Write)CEs. This makes it unnecessary to call the query + * twice, since the usual use case requires both directions. + * + * If a set is being compared against itself (by setting grpBCount to 0), then + * the result matrices are symmetric - it doesn't matter which index is first. + * However, the choice of indices is effectively a choice of which ID is "B" and + * which is "A" for the "a2b" and "b2a" directional results. + * + * [in] grpACount + * This member contains the number of GPU IDs stored in the gpuIdGrpA[] + * array. Must be >= 0. + * [in] grpBCount + * This member contains the number of GPU IDs stored in the gpuIdGrpB[] + * array. Can be == 0 to specify a check of group A against itself. + * [in] gpuIdGrpA + * This member contains the array of GPU IDs in "group A", each of which + * will have its P2P capabilities returned with respect to each GPU ID in + * "group B". Valid entries are contiguous, beginning with the first entry + * in the list. + * [in] gpuIdGrpB + * This member contains the array of GPU IDs in "group B", each of which + * will have its P2P capabilities returned with respect to each GPU ID in + * "group A". Valid entries are contiguous, beginning with the first entry + * in the list. May be equal to gpuIdGrpA, but best performance requires + * that the caller specifies grpBCount = 0 in this case, and ignores this. + * [out] p2pCaps + * This member returns the peer to peer capabilities discovered between the + * pairs of input GPUs between the groups, indexed by [A_index][B_index]. + * Valid p2pCaps values include: + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED + * When this bit is set, peer to peer writes between subdevices owned + * by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED + * When this bit is set, peer to peer reads between subdevices owned + * by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED + * When this bit is set, peer to peer PROP between subdevices owned + * by this device are supported. This is enabled by default + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED + * When this bit is set, PCI is supported for all P2P between subdevices + * owned by this device. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED + * When this bit is set, NVLINK is supported for all P2P between subdevices + * owned by this device. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED + * When this bit is set, peer to peer atomics between subdevices owned + * by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED + * When this bit is set, peer to peer loopback is supported for subdevices + * owned by this device. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED + * When this bit is set, indirect peer to peer writes between subdevices + * owned by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED + * When this bit is set, indirect peer to peer reads between subdevices + * owned by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED + * When this bit is set, indirect peer to peer atomics between + * subdevices owned by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED + * When this bit is set, indirect NVLINK is supported for subdevices + * owned by this device. + * [out] a2bOptimalReadCes + * For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink + * in the A-to-B direction. + * [out] a2bOptimalWriteCes + * For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink + * in the A-to-B direction. + * [out] b2aOptimalReadCes + * For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink + * in the B-to-A direction. + * [out] b2aOptimalWriteCes + * For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink + * in the B-to-A direction. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ + + + +#define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX (0x13aU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID" */ + +typedef NvU32 NV0000_CTRL_P2P_CAPS_MATRIX_ROW[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID (0x3AU) + +typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS { + NvU32 grpACount; + NvU32 grpBCount; + NvU32 gpuIdGrpA[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; + NvU32 gpuIdGrpB[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; + NV0000_CTRL_P2P_CAPS_MATRIX_ROW p2pCaps[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; + NV0000_CTRL_P2P_CAPS_MATRIX_ROW a2bOptimalReadCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; + NV0000_CTRL_P2P_CAPS_MATRIX_ROW a2bOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; + NV0000_CTRL_P2P_CAPS_MATRIX_ROW b2aOptimalReadCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; + NV0000_CTRL_P2P_CAPS_MATRIX_ROW b2aOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; +} NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GPS_CTRL + * + * This command is used to execute general GPS Functions, most dealing with + * calling SBIOS, or retrieving cached sensor and GPS state data. + * + * version + * This parameter specifies the version of the interface. Legal values + * for this parameter are 1. + * cmd + * This parameter specifies the GPS API to be invoked. + * Valid values for this parameter are: + * NV0000_CTRL_GPS_CMD_GET_THERM_LIMIT + * This command gets the temperature limit for thermal controller. When + * this command is specified the input parameter contains ???. + * NV0000_CTRL_GPS_CMD_SET_THERM_LIMIT + * This command set the temperature limit for thermal controller. When + * this command is specified the input parameter contains ???. + * input + * This parameter specifies the cmd-specific input value. + * result + * This parameter returns the cmd-specific output value. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_SYSTEM_GPS_CTRL (0x12aU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID (0x2AU) + +typedef struct NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS { + NvU32 cmd; + NvS32 input[2]; + NvS32 result[4]; +} NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS; + +/* valid version values */ +#define NV0000_CTRL_GPS_PSHARE_PARAMS_PSP_CURRENT_VERSION (0x00010000U) + +/* valid cmd values */ +#define NV0000_CTRL_GPS_CMD_TYPE_GET_THERM_LIMIT (0x00000002U) +#define NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000U) +#define NV0000_CTRL_GPS_RESULT_THERMAL_LIMIT (0x00000000U) +#define NV0000_CTRL_GPS_RESULT_MIN_LIMIT (0x00000001U) +#define NV0000_CTRL_GPS_RESULT_MAX_LIMIT (0x00000002U) +#define NV0000_CTRL_GPS_RESULT_LIMIT_SOURCE (0x00000003U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_THERM_LIMIT (0x00000003U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_THERMAL_LIMIT (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA (0x00000004U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DOWN_N_DELTA (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA (0x00000005U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DOWN_N_DELTA (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA (0x00000006U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_HOLD_DELTA (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA (0x00000007U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_HOLD_DELTA (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA (0x00000008U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_UP_DELTA (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA (0x00000009U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_UP_DELTA (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA (0x0000000AU) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_ENGAGE_DELTA (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA (0x0000000BU) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_ENGAGE_DELTA (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000CU) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000DU) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_STATUS (0x00000016U) +#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_STATUS (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_STATUS (0x00000017U) +#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_STATUS (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM (0x00000018U) +#define NV0000_CTRL_GPS_RESULT_CPU_SET_UTIL_AVG_NUM (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM (0x00000019U) +#define NV0000_CTRL_GPS_INPUT_CPU_GET_UTIL_AVG_NUM (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_PERF_SENSOR (0x0000001AU) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_NEXT_EXPECTED_POLL (0x00000001U) +#define NV0000_CTRL_GPS_RESULT_PERF_SENSOR_VALUE (0x00000000U) +#define NV0000_CTRL_GPS_RESULT_PERF_SENSOR_AVAILABLE (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_CALL_ACPI (0x0000001BU) +#define NV0000_CTRL_GPS_INPUT_ACPI_CMD (0x00000000U) +#define NV0000_CTRL_GPS_INPUT_ACPI_PARAM_IN (0x00000001U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_1 (0x00000000U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_2 (0x00000001U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_STATUS (0x00000000U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_VERSION (0x00000001U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_SZ (0x00000002U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_SZ (0x00000000U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_COUNT (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_IGPU_TURBO (0x0000001CU) +#define NV0000_CTRL_GPS_INPUT_SET_IGPU_TURBO (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERIOD (0x00000026U) +#define NV0000_CTRL_GPS_INPUT_TEMP_PERIOD (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERIOD (0x00000027U) +#define NV0000_CTRL_GPS_RESULT_TEMP_PERIOD (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_NUDGE_FACTOR (0x00000028U) +#define NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_UP (0x00000000U) +#define NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_DOWN (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_NUDGE_FACTOR (0x00000029U) +#define NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_UP (0x00000000U) +#define NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_DOWN (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES (0x0000002AU) +#define NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) +#define NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES (0x0000002BU) +#define NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) +#define NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERF_LIMITS (0x0000002CU) +#define NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_UPPER (0x00000000U) +#define NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_LOWER (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERF_LIMITS (0x0000002DU) +#define NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_UPPER (0x00000000U) +#define NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_LOWER (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_PM1_AVAILABLE (0x0000002EU) +#define NV0000_CTRL_GPS_INPUT_PM1_AVAILABLE (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_PM1_AVAILABLE (0x0000002FU) +#define NV0000_CTRL_GPS_OUTPUT_PM1_AVAILABLE (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS (0x00000044U) +#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) +#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS (0x00000045U) +#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT (0x00000046U) +#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ (0000000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT (0x00000047U) +#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ (0000000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM (0x00000048U) +#define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_INDEX (0000000000U) +#define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_AVAILABLE_MASK (0000000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM (0x00000049U) +#define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX (0000000000U) +#define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX_MAX (2U) + +#define NV0000_CTRL_GPS_PPM_INDEX 7:0 +#define NV0000_CTRL_GPS_PPM_INDEX_MAXPERF (0U) +#define NV0000_CTRL_GPS_PPM_INDEX_BALANCED (1U) +#define NV0000_CTRL_GPS_PPM_INDEX_QUIET (2U) +#define NV0000_CTRL_GPS_PPM_INDEX_INVALID (0xFFU) +#define NV0000_CTRL_GPS_PPM_MASK 15:8 +#define NV0000_CTRL_GPS_PPM_MASK_INVALID (0U) + +/* valid PS_STATUS result values */ +#define NV0000_CTRL_GPS_CMD_PS_STATUS_OFF (0U) +#define NV0000_CTRL_GPS_CMD_PS_STATUS_ON (1U) + + +/* + * NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS + * + * This command allows privileged users to update the values of + * security settings governing RM behavior. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT, + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_PERMISSIONS + * + * Please note: as implied above, administrator privileges are + * required to modify security settings. + */ +#define NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS (0x129U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x29" */ + +#define GPS_MAX_COUNTERS_PER_BLOCK 32U +typedef struct NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS { + NvU32 objHndl; + NvU32 blockId; + NvU32 nextExpectedSampleTimems; + NvU32 countersReq; + NvU32 countersReturned; + NvU32 counterBlock[GPS_MAX_COUNTERS_PER_BLOCK]; +} NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS; + +#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS (0x12cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x2C" */ + +#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS (0x12eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x2E" */ + +/* + * NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI + * + * This command allows users to call GPS ACPI commands for testing purposes. + * + * cmd + * This parameter specifies the GPS ACPI command to execute. + * + * input + * This parameter specified the cmd-dependent input value. + * + * resultSz + * This parameter returns the size (in bytes) of the valid data + * returned in the result parameter. + * + * result + * This parameter returns the results of the specified cmd. + * The maximum size (in bytes) of this returned data will + * not exceed GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE + * + * GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE + * The size of buffer (result) in unit of NvU32. + * The smallest value is sizeof(PSS_ENTRY)*ACPI_PSS_ENTRY_MAX. + * Since the prior one is 24 bytes, and the later one is 48, + * this value cannot be smaller than 288. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT, + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_PERMISSIONS + * + */ +#define GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U +#define NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID (0x2DU) + +typedef struct NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS { + NvU32 cmd; + NvU32 input; + NvU32 resultSz; + NvU32 result[GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE]; +} NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS; + +#define NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI (0x12dU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID" */ + +/* + * NV0000_CTRL_SYSTEM_PARAM_* + * + * The following is a list of system-level parameters (often sensors) that the + * driver can be made aware of. They are primarily intended to be used by system + * power-balancing algorithms that require system-wide visibility in order to + * function. The names and values used here are established and specified in + * several different NVIDIA documents that are made externally available. Thus, + * updates to this list must be made with great caution. The only permissible + * change is to append new parameters. Reordering is strictly prohibited. + * + * Brief Parameter Summary: + * TGPU - GPU temperature (NvTemp) + * PDTS - CPU package temperature (NvTemp) + * SFAN - System fan speed (% of maximum fan speed) + * SKNT - Skin temperature (NvTemp) + * CPUE - CPU energy counter (NvU32) + * TMP1 - Additional temperature sensor 1 (NvTemp) + * TMP2 - Additional temperature sensor 2 (NvTemp) + * CTGP - Mode 2 power limit offset (NvU32) + * PPMD - Power mode data (NvU32) + */ +#define NV0000_CTRL_SYSTEM_PARAM_TGPU (0x00000000U) +#define NV0000_CTRL_SYSTEM_PARAM_PDTS (0x00000001U) +#define NV0000_CTRL_SYSTEM_PARAM_SFAN (0x00000002U) +#define NV0000_CTRL_SYSTEM_PARAM_SKNT (0x00000003U) +#define NV0000_CTRL_SYSTEM_PARAM_CPUE (0x00000004U) +#define NV0000_CTRL_SYSTEM_PARAM_TMP1 (0x00000005U) +#define NV0000_CTRL_SYSTEM_PARAM_TMP2 (0x00000006U) +#define NV0000_CTRL_SYSTEM_PARAM_CTGP (0x00000007U) +#define NV0000_CTRL_SYSTEM_PARAM_PPMD (0x00000008U) +#define NV0000_CTRL_SYSTEM_PARAM_COUNT (0x00000009U) + +/* + * NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD + * + * This command is used to execute general ACPI methods. + * + * method + * This parameter identifies the MXM ACPI API to be invoked. + * Valid values for this parameter are: + * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS + * This value specifies that the DSM NVOP subfunction OPTIMUSCAPS + * API is to be invoked. + * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG + * This value specifies that the DSM NVOP subfunction OPTIMUSFLAG + * API is to be invoked. This API will set a Flag in sbios to Indicate + * that HD Audio Controller is disable/Enabled from GPU Config space. + * This flag will be used by sbios to restore Audio state after resuming + * from s3/s4. + * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS + * This value specifies that the DSM JT subfunction FUNC_CAPS is to + * to be invoked to get the SBIOS capabilities + * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY + * This value specifies that the DSM JT subfunction FUNC_PLATPOLICY is + * to be invoked to set and get the various platform policies for JT. + * Refer to the JT spec in more detail on various policies. + * inData + * This parameter specifies the method-specific input buffer. Data is + * passed to the specified API using this buffer. + * inDataSize + * This parameter specifies the size of the inData buffer in bytes. + * outStatus + * This parameter returns the status code from the associated ACPI call. + * outData + * This parameter specifies the method-specific output buffer. Data + * is returned by the specified API using this buffer. + * outDataSize + * This parameter specifies the size of the outData buffer in bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD (0x130U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID (0x30U) + +typedef struct NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS { + NvU32 method; + NV_DECLARE_ALIGNED(NvP64 inData, 8); + NvU16 inDataSize; + NvU32 outStatus; + NV_DECLARE_ALIGNED(NvP64 outData, 8); + NvU16 outDataSize; +} NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS; + +/* valid method parameter values */ +#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS (0x00000000U) +#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG (0x00000001U) +#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS (0x00000002U) +#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY (0x00000003U) +/* + * NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS + * + * This command can be used to instruct the RM to enable/disable specific module + * of ETW events. + * + * moduleMask + * This parameter specifies the module of events we would like to + * enable/disable. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS (0x131U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID (0x31U) + +typedef struct NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS { + NvU32 moduleMask; +} NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS; + +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ALL (0x00000001U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NOFREQ (0x00000002U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_FLUSH (0x00000004U) + +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PERF (0x00000010U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ELPG (0x00000020U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVDPS (0x00000040U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_POWER (0x00000080U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_DISP (0x00000100U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RMAPI (0x00000200U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_INTR (0x00000400U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_LOCK (0x00000800U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RCJOURNAL (0x00001000U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GENERIC (0x00002000U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_THERM (0x00004000U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GPS (0x00008000U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PCIE (0x00010000U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVTELEMETRY (0x00020000U) + +/* + * NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA + * + * This command is used to read FRL data based on need. + * + * nextSampleNumber + * This parameter returns the counter of next sample which is being filled. + * samples + * This parameter returns the frame time, render time, target time, client ID + * with one reserve bit for future use. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA (0x12fU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE 64U + +typedef struct NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE { + NvU16 frameTime; + NvU16 renderTime; + NvU16 targetTime; + NvU8 sleepTime; + NvU8 sampleNumber; +} NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE; + +#define NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID (0x2FU) + +typedef struct NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS { + NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE samples[NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE]; + NvU8 nextSampleNumber; +} NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA + * + * This command is used to write FRM data based on need. + * + * frameTime + * This parameter contains the frame time of current frame. + * renderTime + * This parameter contains the render time of current frame. + * targetTime + * This parameter contains the target time of current frame. + * sleepTime + * This parameter contains the sleep duration inserted by FRL for the latest frame. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA (0x132U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID (0x32U) + +typedef struct NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS { + NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE sampleData; +} NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO + * + * This command returns the current host driver, host OS and + * plugin information. It is only valid when VGX is setup. + * szHostDriverVersionBuffer + * This field returns the host driver version (NV_VERSION_STRING). + * szHostVersionBuffer + * This field returns the host driver version (NV_BUILD_BRANCH_VERSION). + * szHostTitleBuffer + * This field returns the host driver title (NV_DISPLAY_DRIVER_TITLE). + * szPluginTitleBuffer + * This field returns the plugin build title (NV_DISPLAY_DRIVER_TITLE). + * szHostUnameBuffer + * This field returns the call of 'uname' on the host OS. + * iHostChangelistNumber + * This field returns the changelist value of the host driver (NV_BUILD_CHANGELIST_NUM). + * iPluginChangelistNumber + * This field returns the changelist value of the plugin (NV_BUILD_CHANGELIST_NUM). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE 256U +#define NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO (0x133U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID (0x33U) + +typedef struct NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS { + char szHostDriverVersionBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; + char szHostVersionBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; + char szHostTitleBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; + char szPluginTitleBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; + char szHostUnameBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; + NvU32 iHostChangelistNumber; + NvU32 iPluginChangelistNumber; +} NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS + * + * This command returns the power status of the GPUs in the system, successfully attached or not because of + * insufficient power. It is supported on Kepler and up only. + * gpuCount + * This field returns the count into the following arrays. + * busNumber + * This field returns the busNumber of a GPU. + * gpuExternalPowerStatus + * This field returns the corresponding external power status: + * NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED + * NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS (0x134U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID (0x34U) + +typedef struct NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS { + NvU8 gpuCount; + NvU8 gpuBus[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; + NvU8 gpuExternalPowerStatus[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; +} NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS; + +/* Valid gpuExternalPowerStatus values */ +#define NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED 0U +#define NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED 1U + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS + * + * This command returns the caller's API access privileges using + * this client handle. + * + * privStatus + * This parameter returns a mask of possible access privileges: + * NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_PRIV_USER_FLAG + * The caller is running with elevated privileges + * NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_ROOT_HANDLE_FLAG + * Client is of NV01_ROOT class. + * NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG + * Client has PRIV bit set. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ + + +#define NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS (0x135U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID (0x35U) + +typedef struct NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS { + NvU8 privStatusFlags; +} NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS; + + +/* Valid privStatus values */ +#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_USER_FLAG (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_KERNEL_HANDLE_FLAG (0x00000002U) +#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG (0x00000004U) + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS + * + * The fabric manager (FM) notifies RM that fabric (system) is ready for peer to + * peer (P2P) use or still initializing the fabric. This command allows clients + * to query fabric status to allow P2P operations. + * + * Note, on systems where FM isn't used, RM just returns _SKIP. + * + * fabricStatus + * This parameter returns current fabric status: + * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP + * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED + * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS + * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_INVALID_PARAM_STRUCT + */ + +typedef enum NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS { + NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP = 1, + NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED = 2, + NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS = 3, + NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED = 4, +} NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS; + +#define NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS (0x136U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID (0x36U) + +typedef struct NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS { + NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS fabricStatus; +} NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS; + +/* + * NV0000_CTRL_VGPU_GET_VGPU_VERSION_INFO + * + * This command is used to query the range of VGX version supported. + * + * host_min_supported_version + * The minimum vGPU version supported by host driver + * host_max_supported_version + * The maximum vGPU version supported by host driver + * user_min_supported_version + * The minimum vGPU version set by user for vGPU support + * user_max_supported_version + * The maximum vGPU version set by user for vGPU support + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + */ +#define NV0000_CTRL_VGPU_GET_VGPU_VERSION (0x137U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID" */ + +/* + * NV0000_CTRL_VGPU_GET_VGPU_VERSION + */ +#define NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID (0x37U) + +typedef struct NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS { + NvU32 host_min_supported_version; + NvU32 host_max_supported_version; + NvU32 user_min_supported_version; + NvU32 user_max_supported_version; +} NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS; + +/* + * NV0000_CTRL_VGPU_SET_VGPU_VERSION + * + * This command is used to query whether pGPU is live migration capable or not. + * + * min_version + * The minimum vGPU version to be supported being set + * max_version + * The maximum vGPU version to be supported being set + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + */ +#define NV0000_CTRL_VGPU_SET_VGPU_VERSION (0x138U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID" */ + +/* + * NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS + */ +#define NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID (0x38U) + +typedef struct NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS { + NvU32 min_version; + NvU32 max_version; +} NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS; + +/* + * NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID + * + * This command is used to get a unique identifier for the instance of RM. + * The returned value will only change when the driver is reloaded. A previous + * value will never be reused on a given machine. + * + * rm_instance_id; + * The instance ID of the current RM instance + * + * Possible status values returned are: + * NV_OK + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_RM_INSTANCE_ID (0x139U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID" */ + +/* + * NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS + */ +#define NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID (0x39U) + +typedef struct NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS { + NV_DECLARE_ALIGNED(NvU64 rm_instance_id, 8); +} NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO + * + * This API is used to get the TPP(total processing power) and + * the rated TGP(total GPU power) from SBIOS. + * + * NVPCF is an acronym for Nvidia Platform Controllers and Framework + * which implements platform level policies. NVPCF is implemented in + * a kernel driver on windows. It is implemented in a user mode app + * called nvidia-powerd on Linux. + * + * gpuId + * GPU ID + * tpp + * Total processing power including CPU and GPU + * ratedTgp + * Rated total GPU Power + * subFunc + * NVPCF subfunction id + * ctgpOffsetmW + * Configurable TGP offset, in mW + * targetTppOffsetmW + * TPP, as offset in mW. + * maxOutputOffsetmW + * Maximum allowed output, as offset in mW. + * minOutputOffsetmW; + * Minimum allowed output, as offset in mW. + * + * Valid subFunc ids for NVPCF 1x include : + * NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED + * NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO (0x13bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID (0x3BU) + +typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS { + NvU32 gpuId; + NvU32 tpp; + NvU32 ratedTgp; + NvU32 subFunc; + NvU32 ctgpOffsetmW; + NvU32 targetTppOffsetmW; + NvU32 maxOutputOffsetmW; + NvU32 minOutputOffsetmW; +} NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS; + +/* Valid NVPCF subfunction case */ +#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED_CASE 0U +#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_CASE 1U +#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE 2U +#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_CASE 3U + +/* Valid NVPCF subfunction ids */ +#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED (0x00000000) +#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS (0x00000002) + +/* + * Defines for get supported sub functions bit fields + */ +#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED 0:0 +#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_YES 1 +#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_NO 0 + +/*! + * Config DSM 2x version specific defines + */ +#define NVPCF0100_CTRL_CONFIG_DSM_2X_VERSION (0x00000200) +#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED (0x00000000) +#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS (0x00000002) + +/* + * NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT + * + * This API is used to sync the external fabric management status with + * GSP-RM + * + * bExternalFabricMgmt + * Whether fabric is externally managed + * + * Possible status values returned are: + * NV_OK + */ +#define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT (0x13cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID (0x3CU) + +typedef struct NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS { + NvBool bExternalFabricMgmt; +} NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS; + +/* + * NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO + * + * This API is used to get information about the RM client + * database. + * + * clientCount [OUT] + * This field indicates the number of clients currently allocated. + * + * resourceCount [OUT] + * This field indicates the number of resources currently allocated + * across all clients. + * + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_CLIENT_DATABASE_INFO (0x13dU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID (0x3DU) + +typedef struct NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS { + NvU32 clientCount; + NV_DECLARE_ALIGNED(NvU64 resourceCount, 8); +} NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 + * + * This command returns the current driver information in + * statically sized character arrays. + * + * driverVersionBuffer + * This field returns the version (NV_VERSION_STRING). + * versionBuffer + * This field returns the version (NV_BUILD_BRANCH_VERSION). + * titleBuffer + * This field returns the title (NV_DISPLAY_DRIVER_TITLE). + * changelistNumber + * This field returns the changelist value (NV_BUILD_CHANGELIST_NUM). + * officialChangelistNumber + * This field returns the last official changelist value + * (NV_LAST_OFFICIAL_CHANGELIST_NUM). + * + * Possible status values returned are: + * NV_OK + */ + +#define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE 256U +#define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 (0x13eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID (0x3EU) + +typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS { + char driverVersionBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; + char versionBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; + char titleBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; + NvU32 changelistNumber; + NvU32 officialChangelistNumber; +} NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL + * + * This API is used to get/set RMCTRL cache mode + * + * cmd [IN] + * GET - Gets RMCTRL cache mode + * SET - Sets RMCTRL cache mode + * + * mode [IN/OUT] + * On GET, this field is the output of current RMCTRL cache mode + * On SET, this field indicates the mode to set RMCTRL cache to + * Valid values for this parameter are: + * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE + * No get/set action to cache. + * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE + * Try to get from cache at the beginning of the control. + * Set cache after control finished if the control has not been cached. + * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY + * Do not get from cache. Set cache when control call finished. + * When setting the cache, verify the value in the cache is the same + * with the current control value if the control is already cached. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL (0x13fU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID (0x3FU) + +typedef struct NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS { + NvU32 cmd; + NvU32 mode; +} NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS; + +#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_GET (0x00000000U) +#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_SET (0x00000001U) + +#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE (0x00000000U) +#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE (0x00000001U) +#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY (0x00000002U) + +/* + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL + * + * This command is used to control PFM_REQ_HNDLR functionality. It allows control of + * GPU Performance Scaling (PFM_REQ_HNDLR), changing its operational parameters and read + * most PFM_REQ_HNDLR dynamic parameters. + * + * command + * This parameter specifies the command to execute. Invalid commands + * result in the return of an NV_ERR_INVALID_ARGUMENT status. + * locale + * This parameter indicates the specific locale to which the command + * 'command' is to be applied. +* Supported range of CPU/GPU {i = 0, ..., 255} + * data + * This parameter contains a command-specific data payload. It can + * be used to input data as well as output data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_COMMAND + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_DATA + * NV_ERR_INVALID_REQUEST + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL (0x140U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID (0x40U) + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS { + NvU16 command; + NvU16 locale; + NvU32 data; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS; + +/* + * Valid command values : + * + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT + * Is used to check if PFM_REQ_HNDLR was correctly initialized. + * Possible return (OUT) values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC + * Are used to stop/start PFM_REQ_HNDLR functionality and to get current status. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS + * Are used to control execution of PFM_REQ_HNDLR actions and to get current status. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC + * Are used to switch current PFM_REQ_HNDLR logic and to retrieve current logic. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF + * Will cause that all PFM_REQ_HNDLR actions will be NULL. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY + * Fuzzy logic will determine PFM_REQ_HNDLR actions based on current ruleset. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC + * Deterministic logic will define PFM_REQ_HNDLR actions based on current ruleset. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE + * Are used to set/retrieve system control preference. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT + * Are used to set/retrieve GPU2CPU pstate limits. + * IN/OUT values are four bytes packed into a 32-bit data field. + * The CPU cap index for GPU pstate 0 is in the lowest byte, the CPU cap + * index for the GPU pstate 3 is in the highest byte, etc. One + * special value is to disable the override to the GPU2CPU map: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE + * Is used to stop/start PFM_REQ_HNDLR PMU functionality. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE + * Is used to get the current status of PMU PFM_REQ_HNDLR. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER + * Are used to set/retrieve max power [mW] that system can provide. + * This is hardcoded PFM_REQ_HNDLR safety feature and logic/rules does not apply + * to this threshold. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET + * Are used to set/retrieve current system cooling budget [mW]. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD + * Are used to set/retrieve integration interval [sec]. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT + * Are used to set/retrieve used ruleset [#]. Value is checked + * against MAX number of rules for currently used PFM_REQ_HNDLR logic. Also COUNT + * provides a way to find out how many rules exist for the current control + * system. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST + * Is used to set/get a delay relative to now during which to allow unbound + * CPU performance. Units are seconds. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE + * Is used to override/get the actual power supply mode (AC/Battery). + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO + * Is used to get the Ventura system information for VCT tool + * Returned 32bit value should be treated as bitmask and decoded in + * following way: + * Encoding details are defined in objPFM_REQ_HNDLR.h refer to + * NV_PFM_REQ_HNDLR_SYS_SUPPORT_INFO and corresponding bit defines. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTION + * Is used to get the supported sub-functions defined in SBIOS. Returned + * value is a bitmask where each bit corresponds to different function: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE + * Are used to retrieve appropriate power measurements and their derivatives + * in [mW] for required locale. _BURDEN is defined only for _LOCALE_SYSTEM. + * _INTERMEDIATE is not defined for _LOCALE_SYSTEM, and takes an In value as + * index. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS + * Is used to retrieve parameters when adjusting raw sensor power reading. + * The values may come from SBIOS, VBIOS, registry or driver default. + * Possible IN value is the index of interested parameter. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE + * Are used to retrieve appropriate temperature measurements and their + * derivatives in [1/1000 Celsius]. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX + * Are used to retrieve CPU(x)/GPU(x) p-state or it's limits. + * Not applicable to _LOCALE_SYSTEM. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION + * Is used to retrieve last PFM_REQ_HNDLR action for given domain. + * Not applicable to _LOCALE_SYSTEM. + * Possible return (OUT) values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0 + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1 + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1 + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2 + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE + * Is used to set the power sensor simulator state. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE + * Is used to get the power simulator sensor simulator state. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA + * Is used to set power sensor simulator data + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA + * Is used to get power sensor simulator data + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK + * Is used to respond to the ACPI event triggered by SBIOS. RM will + * request value for budget and status, validate them, apply them + * and send ACK back to SBIOS. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT + * Is a test cmd that should notify SBIOS to send ACPI event requesting + * budget and status change. + */ +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_INVALID (0xFFFFU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT (0x0000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC (0x0001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC (0x0002U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS (0x0003U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS (0x0004U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC (0x0005U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC (0x0006U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE (0x0007U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE (0x0008U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT (0x0009U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT (0x000AU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE (0x000BU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE (0x000CU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER (0x0100U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER (0x0101U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET (0x0102U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET (0x0103U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD (0x0104U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD (0x0105U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET (0x0106U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET (0x0107U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT (0x0108U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST (0x0109U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST (0x010AU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE (0x010BU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE (0x010CU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO (0x010DU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTIONS (0x010EU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER (0x0200U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA (0x0201U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE (0x0202U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG (0x0203U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL (0x0204U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN (0x0205U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE (0x0206U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS (0x0210U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP (0x0220U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA (0x0221U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE (0x0222U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE (0x0240U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP (0x0241U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN (0x0242U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX (0x0243U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION (0x0244U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_SLFM_PRESENT (0x0245U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE (0x0250U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE (0x0251U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA (0x0252U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA (0x0253U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK (0x0320U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT (0x0321U) + +/* valid LOCALE values */ +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_INVALID (0xFFFFU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_SYSTEM (0x0000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_CPU(i) (0x0100+((i)%0x100)) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_GPU(i) (0x0200+((i)%0x100)) + +/* valid data values for enums */ +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID (0x80000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE (0xFFFFFFFFU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_ON (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS (0x00000004U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC (0x00000008U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC (0x00000010U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB (0x00000020U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS (0x00000040U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0 (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1 (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT (0x00000003U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1 (0x00000004U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2 (0x00000005U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM (0x00000006U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM (0x00000007U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_NO (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_YES (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_ON (0x00000001U) + +/* + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL + * + * This command allows execution of multiple PFM_REQ_HNDLRControl commands within one + * RmControl call. For practical reasons # of commands is limited to 16. + * This command shares defines with NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL. + * + * cmdCount + * Number of commands that should be executed. + * Less or equal to NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX. + * + * succeeded + * Number of commands that were succesully executed. + * Less or equal to NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX. + * Failing commands return NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID + * in their data field. + * + * cmdData + * Array of commands with following structure: + * command + * This parameter specifies the command to execute. + * Invalid commands result in the return of an + * NV_ERR_INVALID_ARGUMENT status. + * locale + * This parameter indicates the specific locale to which + * the command 'command' is to be applied. + * Supported range of CPU/GPU {i = 0, ..., 255} + * data + * This parameter contains a command-specific data payload. + * It is used both to input data as well as to output data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL (0x141U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX (16U) +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID (0x41U) + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS { + NvU32 cmdCount; + NvU32 succeeded; + + struct { + NvU16 command; + NvU16 locale; + NvU32 data; + } cmdData[NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX]; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL + * + * This command is used to execute general PFM_REQ_HNDLR Functions, most dealing with + * calling SBIOS, or retrieving cached sensor and PFM_REQ_HNDLR state data. + * + * version + * This parameter specifies the version of the interface. Legal values + * for this parameter are 1. + * cmd + * This parameter specifies the PFM_REQ_HNDLR API to be invoked. + * Valid values for this parameter are: + * NV0000_CTRL_PFM_REQ_HNDLR_CMD_GET_THERM_LIMIT + * This command gets the temperature limit for thermal controller. When + * this command is specified the input parameter contains ???. + * NV0000_CTRL_PFM_REQ_HNDLR_CMD_SET_THERM_LIMIT + * This command set the temperature limit for thermal controller. When + * this command is specified the input parameter contains ???. + * input + * This parameter specifies the cmd-specific input value. + * result + * This parameter returns the cmd-specific output value. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL (0x142U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID (0x42U) + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS { + NvU32 cmd; + NvS32 input[2]; + NvS32 result[4]; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS; + +/* valid version values */ +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_PSP_CURRENT_VERSION (0x00010000U) + +/* valid cmd values */ +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_THERM_LIMIT (0x00000002U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_THERMAL_LIMIT (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MIN_LIMIT (0x00000001U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MAX_LIMIT (0x00000002U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE (0x00000003U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_THERM_LIMIT (0x00000003U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_THERMAL_LIMIT (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA (0x00000004U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DOWN_N_DELTA (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA (0x00000005U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DOWN_N_DELTA (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA (0x00000006U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_HOLD_DELTA (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA (0x00000007U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_HOLD_DELTA (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA (0x00000008U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_UP_DELTA (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA (0x00000009U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_UP_DELTA (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA (0x0000000AU) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_ENGAGE_DELTA (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA (0x0000000BU) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_ENGAGE_DELTA (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000CU) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000DU) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_STATUS (0x00000016U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_STATUS (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_STATUS (0x00000017U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_STATUS (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM (0x00000018U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_CPU_SET_UTIL_AVG_NUM (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM (0x00000019U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_CPU_GET_UTIL_AVG_NUM (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PERF_SENSOR (0x0000001AU) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_NEXT_EXPECTED_POLL (0x00000001U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_VALUE (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_AVAILABLE (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_CALL_ACPI (0x0000001BU) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_CMD (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_PARAM_IN (0x00000001U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_1 (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_2 (0x00000001U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_STATUS (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_VERSION (0x00000001U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_SZ (0x00000002U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_SZ (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_COUNT (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_IGPU_TURBO (0x0000001CU) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SET_IGPU_TURBO (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERIOD (0x00000026U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERIOD (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERIOD (0x00000027U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERIOD (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_NUDGE_FACTOR (0x00000028U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_UP (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_DOWN (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_NUDGE_FACTOR (0x00000029U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_UP (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_DOWN (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES (0x0000002AU) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES (0x0000002BU) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERF_LIMITS (0x0000002CU) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_UPPER (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_LOWER (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERF_LIMITS (0x0000002DU) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_UPPER (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_LOWER (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PM1_AVAILABLE (0x0000002EU) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_PM1_AVAILABLE (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PM1_AVAILABLE (0x0000002FU) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_PM1_AVAILABLE (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS (0x00000044U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS (0x00000045U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT (0x00000046U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ (0000000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT (0x00000047U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ (0000000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM (0x00000048U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_INDEX (0000000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_AVAILABLE_MASK (0000000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM (0x00000049U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX (0000000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX_MAX (2U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX 7:0 +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_MAXPERF (0U) +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_BALANCED (1U) +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_QUIET (2U) +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID (0xFFU) +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK 15:8 +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK_INVALID (0U) + +/* valid PS_STATUS result values */ +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_OFF (0U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_ON (1U) + +#define PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK 32U +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS { + NvU32 objHndl; + NvU32 blockId; + NvU32 nextExpectedSampleTimems; + NvU32 countersReq; + NvU32 countersReturned; + NvU32 counterBlock[PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK]; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS; + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS (0x146U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x46" */ + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS (0x147U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x47" */ + +/* + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI + * + * This command allows users to call PFM_REQ_HNDLR ACPI commands for testing purposes. + * + * cmd + * This parameter specifies the PFM_REQ_HNDLR ACPI command to execute. + * + * input + * This parameter specified the cmd-dependent input value. + * + * resultSz + * This parameter returns the size (in bytes) of the valid data + * returned in the result parameter. + * + * result + * This parameter returns the results of the specified cmd. + * The maximum size (in bytes) of this returned data will + * not exceed PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE + * + * PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE + * The size of buffer (result) in unit of NvU32. + * The smallest value is sizeof(PSS_ENTRY)*ACPI_PSS_ENTRY_MAX. + * Since the prior one is 24 bytes, and the later one is 48, + * this value cannot be smaller than 288. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT, + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_PERMISSIONS + * + */ +#define PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID (0x43U) + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS { + NvU32 cmd; + NvU32 input; + NvU32 resultSz; + NvU32 result[PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE]; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS; + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI (0x143U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PFM_REQ_HNDLR (0x00008000U) + +/* + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA + * + * This command is used to read FRL data based on need. + * + * nextSampleNumber + * This parameter returns the counter of next sample which is being filled. + * samples + * This parameter returns the frame time, render time, target time, client ID + * with one reserve bit for future use. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA (0x144U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE 64U + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE { + NvU16 frameTime; + NvU16 renderTime; + NvU16 targetTime; + NvU8 sleepTime; + NvU8 sampleNumber; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE; + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID (0x44U) + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS { + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE samples[NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE]; + NvU8 nextSampleNumber; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA + * + * This command is used to write FRM data based on need. + * + * frameTime + * This parameter contains the frame time of current frame. + * renderTime + * This parameter contains the render time of current frame. + * targetTime + * This parameter contains the target time of current frame. + * sleepTime + * This parameter contains the sleep duration inserted by FRL for the latest frame. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA (0x145U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID (0x45U) + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS { + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE sampleData; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS; + +/* _ctrl0000system_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h new file mode 100644 index 0000000..d55703d --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h @@ -0,0 +1,435 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000unix.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +/* NV01_ROOT (client) Linux control commands and parameters */ + +/* + * NV0000_CTRL_CMD_OS_UNIX_FLUSH_USER_CACHE + * + * This command may be used to force a cache flush for a range of virtual addresses in + * memory. Can be used for either user or kernel addresses. + * + * offset, length + * These parameters specify the offset within the memory block + * and the number of bytes to flush/invalidate + * cacheOps + * This parameter flags whether to flush, invalidate or do both. + * Possible values are: + * NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH + * NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_INVALIDATE + * NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH_INVALIDATE + * hDevice + * This parameter is the handle to the device + * hObject + * This parameter is the handle to the memory structure being operated on. + * internalOnly + * Intended for internal use unless client is running in MODS UNIX environment, + * in which case this parameter specify the virtual address of the memory block + * to flush. + * + * Possible status values are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_COMMAND + * NV_ERR_INVALID_LIMIT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_OS_UNIX_FLUSH_USER_CACHE (0x3d02) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 length, 8); + NvU32 cacheOps; + NvHandle hDevice; + NvHandle hObject; + NV_DECLARE_ALIGNED(NvU64 internalOnly, 8); +} NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS; + +#define NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH (0x00000001) +#define NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_INVALIDATE (0x00000002) +#define NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH_INVALIDATE (0x00000003) + + +/* + * NV0000_CTRL_CMD_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR + * + * This command is used to get the control file descriptor. + * + * Possible status values returned are: + * NV_OK + * + */ +#define NV0000_CTRL_CMD_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR (0x3d04) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | 0x4" */ + +typedef struct NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS { + NvS32 fd; +} NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS; + +typedef enum NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE { + NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_NONE = 0, + NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM = 1, +} NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE; + +typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECT { + NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE type; + + union { + struct { + NvHandle hDevice; + NvHandle hParent; + NvHandle hObject; + } rmObject; + } data; +} NV0000_CTRL_OS_UNIX_EXPORT_OBJECT; + +/* + * NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD + * + * This command may be used to export NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE + * object to file descriptor. + * + * Note that the 'fd' parameter is an input parameter at the kernel level, but + * an output parameter for usermode RMAPI clients -- the RMAPI library will + * open a new FD automatically if a usermode RMAPI client exports an object. + * + * Kernel-mode RM clients can export an object to an FD in two steps: + * 1. User client calls this RMControl with the flag 'EMPTY_FD_TRUE' to create + * an empty FD to receive the object, then passes that FD to the kernel-mode + * RM client. + * 2. Kernel-mode RM client fills in the rest of the + * NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS as usual and calls RM to + * associate its desired RM object with the empty FD from its usermode + * client. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_PARAMETER + */ +#define NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD (0x3d05) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS { + NV0000_CTRL_OS_UNIX_EXPORT_OBJECT object; /* IN */ + NvS32 fd; /* IN/OUT */ + NvU32 flags; /* IN */ +} NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS; + +/* + * If EMPTY_FD is TRUE, the 'fd' will be created but no object will be + * associated with it. The hDevice parameter is still required, to determine + * the correct device node on which to create the file descriptor. + * (An empty FD can then be passed to a kernel-mode driver to associate it with + * an actual object.) + */ +#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD 0:0 +#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_FALSE (0x00000000) +#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_TRUE (0x00000001) + +/* + * NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD + * + * This command may be used to import back + * NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE object from file descriptor. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_PARAMETER + */ +#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD (0x3d06) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS { + NvS32 fd; /* IN */ + NV0000_CTRL_OS_UNIX_EXPORT_OBJECT object; /* IN */ +} NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS; + +/* + * NV0000_CTRL_CMD_OS_GET_GPU_INFO + * + * This command will query the OS specific info for the specified GPU. + * + * gpuId + * This parameter should specify a valid GPU ID value. If there + * is no GPU present with the specified ID, a status of + * NV_ERR_INVALID_ARGUMENT is returned. + * minorNum + * This parameter returns minor number of device node. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_OS_GET_GPU_INFO (0x3d07) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | 0x7" */ + +typedef struct NV0000_CTRL_OS_GET_GPU_INFO_PARAMS { + NvU32 gpuId; /* IN */ + NvU32 minorNum; /* OUT */ +} NV0000_CTRL_OS_GET_GPU_INFO_PARAMS; + +/* + * NV0000_CTRL_CMD_OS_UNIX_GET_EXPORT_OBJECT_INFO + * + * This command will query the deviceInstance for the specified FD + * which is referencing an exported object. + * + * fd + * File descriptor parameter is referencing an exported object on a Unix system. + * + * deviceInstatnce + * This parameter returns a deviceInstance on which the object is located. + * + * NV_MAX_DEVICES is returned if the object is parented by a client instead + * of a device. + * + * maxObjects + * This parameter returns the maximum number of object handles that may be + * contained in the file descriptor. + * + * metadata + * This parameter returns the user metadata passed into the + * _EXPORT_OBJECTS_TO_FD control call. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OBJECT_NOT_FOUND + */ + +#define NV0000_CTRL_CMD_OS_UNIX_GET_EXPORT_OBJECT_INFO (0x3d08) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE 64 + +#define NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS { + NvS32 fd; /* IN */ + NvU32 deviceInstance; /* OUT */ + NvU16 maxObjects; /* OUT */ + NvU8 metadata[NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE]; /* OUT */ +} NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS; + +/* + * NV0000_CTRL_CMD_OS_UNIX_REFRESH_RMAPI_DEVICE_LIST + * + * This command will re-fetch probed GPUs information and update RMAPI library's + * internal detected GPU context information accordingly. Without this, GPUs + * attached to RM after RMAPI client initialization will not be accessible and + * all RMAPI library calls will fail on them. + * Currently this is used by NVSwitch Fabric Manager in conjunction with NVSwitch + * Shared Virtualization feature where GPUs are hot-plugged to OS/RM (by Hypervisor) + * and Fabric Manager is signaled externally by the Hypervisor to initialize those GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_OPERATING_SYSTEM + */ + +#define NV0000_CTRL_CMD_OS_UNIX_REFRESH_RMAPI_DEVICE_LIST (0x3d09) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | 0x9" */ + +/* + * This control call has been deprecated. It will be deleted soon. + * Use NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD (singular) or + * NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD (plural) instead. + */ +#define NV0000_CTRL_CMD_OS_UNIX_CREATE_EXPORT_OBJECT_FD (0x3d0a) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_BUFFER_SIZE NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE + +#define NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS { + NvHandle hDevice; /* IN */ + NvU16 maxObjects; /* IN */ + NvU8 metadata[NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_BUFFER_SIZE]; /* IN */ + NvS32 fd; /* IN/OUT */ +} NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS; + +/* + * NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD + * + * Exports RM handles to an fd that was provided, also creates an FD if + * requested. + * + * The objects in the 'handles' array are exported into the fd + * as the range [index, index + numObjects). + * + * If index + numObjects is greater than the maxObjects value used + * to create the file descriptor, NV_ERR_INVALID_PARAMETER is returned. + * + * If 'numObjects and 'index' overlap with a prior call, the newer call's RM object + * handles will overwrite the previously exported handles from the previous call. + * This overlapping behavior can also be used to unexport a handle by setting + * the appropriate object in 'objects' to 0. + * + * fd + * A file descriptor. If -1, a new FD will be created. + * + * hDevice + * The owning device of the objects to be exported (must be the same for + * all objects). + * + * maxObjects + * The total number of objects that the client wishes to export to the FD. + * This parameter will be honored only when the FD is getting created. + * + * metadata + * A buffer for clients to write some metadata to and pass to the importing + * client. This parameter will be honored only when the FD is getting + * created. + * + * objects + * Array of RM object handles to export to the fd. + * + * numObjects + * The number of handles the user wishes to export in this call. + * + * index + * The index into the export fd at which to start exporting the handles in + * 'objects' (for use in iterative calls). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OUT_OF_RANGE + * NV_ERR_NOT_SUPPORTED + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_OBJECT_HANDLE + */ +#define NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD (0x3d0b) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_MAX_OBJECTS 512 + +#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS { + NvS32 fd; /* IN/OUT */ + NvHandle hDevice; /* IN */ + NvU16 maxObjects; /* IN */ + NvU8 metadata[NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE]; /* IN */ + NvHandle objects[NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_MAX_OBJECTS]; /* IN */ + NvU16 numObjects; /* IN */ + NvU16 index; /* IN */ +} NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS; + +/* + * NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECTS_FROM_FD + * + * This command can be used to import back RM handles + * that were exported to an fd using the + * NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD control call. + * + * If index + numObjects is greater than the maxObjects value used + * to create the file descriptor, NV_ERR_INVALID_PARAMETER is returned + * and no objects are imported. + * + * For each valid handle in the 'objects' array parameter at index 'i', + * the corresponding object handle at index ('i' + 'index') contained by + * the fd will be imported. If the object at index ('i' + 'index') has + * not been exported into the fd, no object will be imported. + * + * If any of handles contained in the 'objects' array parameter are invalid + * and the corresponding export object handle is valid, + * NV_ERR_INVALID_PARAMETER will be returned and no handles will be imported. + * + * fd + * The export fd on which to import handles out of. + * + * hParent + * The parent RM handle of which all of the exported objects will + * be duped under. + * + * objects + * An array of RM handles. The exported objects will be duped under + * these handles during the import process. + * + * objectTypes + * An array of RM handle types. The type _NONE will be returned if + * the object was not imported. Other possible object types are + * mentioned below. + * + * numObjects + * The number of valid object handles in the 'objects' array. This should + * be set to the number of objects that the client wishes to import. + * + * index + * The index into the fd in which to start importing from. For + * use in iterative calls. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OUT_OF_RANGE + * NV_ERR_NOT_SUPPORTED + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_PARAMETER + */ +#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECTS_FROM_FD (0x3d0c) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID" */ + +// +// TODO Bump this back up to 512 after the FLA revamp is complete +// +#define NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS 128 + +#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_NONE 0 +#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_VIDMEM 1 +#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_SYSMEM 2 +#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC 3 + + + +#define NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS { + NvS32 fd; /* IN */ + NvHandle hParent; /* IN */ + NvHandle objects[NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS]; /* IN */ + NvU8 objectTypes[NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS]; /* OUT */ + NvU16 numObjects; /* IN */ + NvU16 index; /* IN */ +} NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS; + +/* _ctrl0000unix_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h new file mode 100644 index 0000000..671c1a3 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h @@ -0,0 +1,78 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000vgpu.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrla081.h" +#include "class/cl0000.h" +#include "nv_vgpu_types.h" +/* + * NV0000_CTRL_CMD_VGPU_GET_START_DATA + * + * This command gets data associated with NV0000_NOTIFIERS_VGPU_MGR_START to + * start VGPU process. + * + * mdevUuid + * This parameter gives mdev device UUID for which nvidia-vgpu-mgr should + * init process. + * + * qemuPid + * This parameter specifies the QEMU process ID of the VM. + * + * gpuPciId + * This parameter provides gpuId of GPU on which vgpu device is created. + * + * configParams + * This parameter specifies the configuration parameters for vGPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_EVENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_CLIENT + * + */ +#define NV0000_CTRL_CMD_VGPU_GET_START_DATA (0xc01) /* finn: Evaluated from "(FINN_NV01_ROOT_VGPU_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_GET_START_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_VGPU_GET_START_DATA_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_VGPU_GET_START_DATA_PARAMS { + NvU8 mdevUuid[VM_UUID_SIZE]; + NvU8 configParams[1024]; + NvU32 qemuPid; + NvU32 gpuPciId; + NvU16 vgpuId; + NvU32 gpuPciBdf; +} NV0000_CTRL_VGPU_GET_START_DATA_PARAMS; + +/* _ctrl0000vgpu_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0002.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0002.h new file mode 100644 index 0000000..046c931 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0002.h @@ -0,0 +1,178 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0002.finn +// + +#include "ctrl/ctrlxxxx.h" +#define NV0002_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0002, NV0002_CTRL_##cat, idx) + +/* Client command categories (6bits) */ +#define NV0002_CTRL_RESERVED (0x00) +#define NV0002_CTRL_DMA (0x01) + + +/* + * NV0002_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ + +#define NV0002_CTRL_CMD_NULL (0x20000) /* finn: Evaluated from "(FINN_NV01_CONTEXT_DMA_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV0002_CTRL_CMD_UPDATE_CONTEXTDMA + * + * This command will update the parameters of the specified context dma. The + * context dma must be bound to a display channel. The update is limited + * to the display view of the context dma. Other use cases will continue to + * use the original allocation parameters. + * + * This is used on platforms where memory may be moved by the operating + * system after allocation. + * + * This control call supports the NVOS54_FLAGS_LOCK_BYPASS flag. + * + * baseAddress + * This parameter, if selected by flags, indicates the new baseAddress for + * the ctxdma + * limit + * This parameter, if selected by flags, indicates the new limit of the + * ctxdma. + * hCtxDma + * ContextDma handle on which to operate. Must match the handle given to the control + * call. + * hChannel + * Display channel handle. This field is ignored. + * hintHandle + * Hint value returned from HeapAllocHint which encodes information about + * the surface. This is used by chips without generic kind. Newer chips + * use the COMPR_INFO flag and the hintHandle must be zero. + * flags + * This parameter specifies flags which indicate which other parameters are + * valid. + * FLAGS_PAGESIZE updates the context DMA pagesize field, if not _DEFAULT + * FLAGS_USE_COMPR_INFO uses the surface format specified in the params, instead of hintHandle. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_NOT_SUPPORTED + */ +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA (0x20101) /* finn: Evaluated from "(FINN_NV01_CONTEXT_DMA_DMA_INTERFACE_ID << 8) | NV0002_CTRL_UPDATE_CONTEXTDMA_PARAMS_MESSAGE_ID" */ + +#define NV0002_CTRL_UPDATE_CONTEXTDMA_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0002_CTRL_UPDATE_CONTEXTDMA_PARAMS { + NV_DECLARE_ALIGNED(NvU64 baseAddress, 8); + NV_DECLARE_ALIGNED(NvU64 limit, 8); + NvHandle hSubDevice; + NvHandle hCtxDma; + NvHandle hChannel; + NvHandle hintHandle; + NvU32 flags; +} NV0002_CTRL_UPDATE_CONTEXTDMA_PARAMS; + +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_BASEADDRESS 0:0 +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_BASEADDRESS_INVALID (0x00000000) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_BASEADDRESS_VALID (0x00000001) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_LIMIT 1:1 +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_LIMIT_INVALID (0x00000000) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_LIMIT_VALID (0x00000001) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_HINT 2:2 +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_HINT_INVALID (0x00000000) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_HINT_VALID (0x00000001) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_PAGESIZE 4:3 +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_PAGESIZE_DEFAULT (0x00000000) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_PAGESIZE_4K (0x00000001) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_PAGESIZE_BIG (0x00000002) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_USE_COMPR_INFO 6:5 +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_USE_COMPR_INFO_NONE (0x00000000) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_USE_COMPR_INFO_FORMAT_PITCH (0x00000001) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_USE_COMPR_INFO_FORMAT_BLOCK_LINEAR (0x00000002) + +/* + * NV0002_CTRL_CMD_BIND_CONTEXTDMA + * + * Bind a context dma to a display channel. Binding is no longer required for + * Host channels, but does silently succeed. + * + * This control call supports the NVOS54_FLAGS_LOCK_BYPASS flag. + * + * This control replaces the obsolete RmBindContextDma() API. + * + * hChannel + * The channel for ctxdma bind + * + * Possible error codes include + * NV_OK + * NV_ERR_TOO_MANY_PRIMARIES hash table is full + * NV_ERR_NO_MEMORY instance memory is full + * NV_ERR_INVALID_OFFSET surface is not correctly aligned + * NV_ERR_STATE_IN_USE context dma was already bound given channel + */ +#define NV0002_CTRL_CMD_BIND_CONTEXTDMA (0x20102) /* finn: Evaluated from "(FINN_NV01_CONTEXT_DMA_DMA_INTERFACE_ID << 8) | NV0002_CTRL_BIND_CONTEXTDMA_PARAMS_MESSAGE_ID" */ + +#define NV0002_CTRL_BIND_CONTEXTDMA_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0002_CTRL_BIND_CONTEXTDMA_PARAMS { + NvHandle hChannel; +} NV0002_CTRL_BIND_CONTEXTDMA_PARAMS; + +/* + * NV0002_CTRL_CMD_UNBIND_CONTEXTDMA + * + * Unbind a context dma from a display channel. + * + * This control call supports the NVOS54_FLAGS_LOCK_BYPASS flag. + * + * hChannel + * The display channel to unbind from + * + * Possible error codes include + * NV_OK + * NV_ERR_INVALID_STATE channel was not bound + */ +#define NV0002_CTRL_CMD_UNBIND_CONTEXTDMA (0x20103) /* finn: Evaluated from "(FINN_NV01_CONTEXT_DMA_DMA_INTERFACE_ID << 8) | NV0002_CTRL_UNBIND_CONTEXTDMA_PARAMS_MESSAGE_ID" */ + +#define NV0002_CTRL_UNBIND_CONTEXTDMA_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0002_CTRL_UNBIND_CONTEXTDMA_PARAMS { + NvHandle hChannel; +} NV0002_CTRL_UNBIND_CONTEXTDMA_PARAMS; + +/* _ctrl0002.h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0004.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0004.h new file mode 100644 index 0000000..91431ce --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0004.h @@ -0,0 +1,93 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0004.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV01_TIMER control commands and parameters */ + +#define NV0004_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0004, NV0004_CTRL_##cat, idx) + +/* NV01_TIMER command categories (8bits) */ +#define NV0004_CTRL_RESERVED (0x00) +#define NV0004_CTRL_TMR (0x01) + +/* + * NV0004_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0004_CTRL_CMD_NULL (0x40000) /* finn: Evaluated from "(FINN_NV01_TIMER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV0004_CTRL_CMD_TMR_SET_ALARM_NOTIFY + * + * This command can be used to set a PTIMER alarm to trigger at the + * specified time in the future on the subdevice associated with this + * NV01_TIMER object instance. + * + * hEvent + * This parameter specifies the handle of an NV01_EVENT object instance + * that is to be signaled when the alarm triggers. This NV01_EVENT + * object instance must have been allocated with this NV01_TIMER object + * instance as its parent. If this parameter is set to NV01_NULL_OBJECT + * then all NV01_EVENT object instances associated with this NV01_TIMER + * object instance are signaled. + * alarmTimeUsecs + * This parameter specifies the relative time in nanoseconds at which + * the alarm should trigger. Note that the accuracy between the alarm + * trigger and the subsequent notification to the caller can vary + * depending on system conditions. + * + * Possible status values returned include: + * NVOS_STATUS_SUCCES + * NVOS_STATUS_INVALID_PARAM_STRUCT + * NVOS_STATUS_INVALID_OBJECT_HANDLE + */ + +#define NV0004_CTRL_CMD_TMR_SET_ALARM_NOTIFY (0x40110) /* finn: Evaluated from "(FINN_NV01_TIMER_TMR_INTERFACE_ID << 8) | NV0004_CTRL_TMR_SET_ALARM_NOTIFY_PARAMS_MESSAGE_ID" */ + +#define NV0004_CTRL_TMR_SET_ALARM_NOTIFY_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV0004_CTRL_TMR_SET_ALARM_NOTIFY_PARAMS { + NvHandle hEvent; + NV_DECLARE_ALIGNED(NvU64 alarmTimeNsecs, 8); +} NV0004_CTRL_TMR_SET_ALARM_NOTIFY_PARAMS; + +/* _ctrl0004_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl000f.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl000f.h new file mode 100644 index 0000000..ecabf33 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl000f.h @@ -0,0 +1,85 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl000f.finn +// + +#include "ctrl/ctrlxxxx.h" + +#define NV000F_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x000f, NV000F_CTRL_##cat, idx) + +/* Client command categories (6bits) */ +#define NV000F_CTRL_RESERVED (0x00U) +#define NV000F_CTRL_FM (0x01U) +#define NV000F_CTRL_RESERVED2 (0x02U) + +/* + * NV000f_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV000F_CTRL_CMD_NULL (0xf0000U) /* finn: Evaluated from "(FINN_FABRIC_MANAGER_SESSION_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV000F_CTRL_CMD_SET_FM_STATE + * + * This command will notify RM that the fabric manager is initialized. + * + * RM would block P2P operations such as P2P capability reporting, NV50_P2P object + * allocation etc. until the notification received. + * + * Possible status values returned are: + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + * NV_OK + */ +#define NV000F_CTRL_CMD_SET_FM_STATE (0xf0101U) /* finn: Evaluated from "(FINN_FABRIC_MANAGER_SESSION_FM_INTERFACE_ID << 8) | 0x1" */ + +/* + * NV000F_CTRL_CMD_CLEAR_FM_STATE + * + * This command will notify RM that the fabric manager is uninitialized. + * + * RM would block P2P operations such as P2P capability reporting, NV50_P2P object + * allocation etc. as soon as the notification received. + * + * Possible status values returned are: + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + * NV_OK + */ +#define NV000F_CTRL_CMD_CLEAR_FM_STATE (0xf0102U) /* finn: Evaluated from "(FINN_FABRIC_MANAGER_SESSION_FM_INTERFACE_ID << 8) | 0x2" */ + +/* _ctrl000f.h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0020.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0020.h new file mode 100644 index 0000000..60f6684 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0020.h @@ -0,0 +1,80 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0020.finn +// + +#include "ctrl/ctrlxxxx.h" +#define NV0020_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0x0020, NV0020_CTRL_##cat, idx) + +/* NV0020_GPU_MANAGEMENT command categories (6bits) */ +#define NV0020_CTRL_RESERVED (0x00) +#define NV0020_CTRL_GPU_MGMT (0x01) + +/* + * NV0020_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0020_CTRL_CMD_NULL (0x200000) /* finn: Evaluated from "(FINN_NV0020_GPU_MANAGEMENT_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* Maximum possible number of bytes of GID information */ +#define NV0020_GPU_MAX_GID_LENGTH (0x00000100) + +/* + * NV0020_CTRL_CMD_GPU_MGMT_SET_SHUTDOWN_STATE + * + * This command modifies GPU zero power state for the desired GPU in the + * database. This state is set by a privileged client, after the GPU is + * completely unregistered from RM as well as PCI subsystem. On Linux, + * clients perform this operation through pci-sysfs. + * This control call requires admin privileges. + * + * uuid (INPUT) + * The UUID of the gpu. + * Supports binary format and SHA-1 type. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0020_CTRL_CMD_GPU_MGMT_SET_SHUTDOWN_STATE (0x200101) /* finn: Evaluated from "(FINN_NV0020_GPU_MANAGEMENT_GPU_MGMT_INTERFACE_ID << 8) | NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS { + NvU8 uuid[NV0020_GPU_MAX_GID_LENGTH]; +} NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS; + +/* _ctrl0020_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl003e.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl003e.h new file mode 100644 index 0000000..880fcc8 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl003e.h @@ -0,0 +1,191 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl003e.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV01_MEMORY_SYSTEM control commands and parameters */ + +#define NV003E_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x003E, NV003E_CTRL_##cat, idx) + +/* NV01_MEMORY_SYSTEM command categories (6bits) */ +#define NV003E_CTRL_RESERVED (0x00) +#define NV003E_CTRL_MEMORY (0x01) + +/* + * NV003E_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV003E_CTRL_CMD_NULL (0x3e0000) /* finn: Evaluated from "(FINN_NV01_MEMORY_SYSTEM_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV003E_CTRL_CMD_GET_SURFACE_PHYS_ATTR + * + * This command returns attributes associated with the memory object + * at the given offset. The architecture dependent return parameter + * comprFormat determines the meaningfulness (or not) of comprOffset. + * + * This call is currently only supported in the MODS environment. + * + * memOffset + * This parameter is both an input and an output. As input, this + * parameter holds an offset into the memory surface. The return + * value is the physical address of the surface at the given offset. + * memFormat + * This parameter returns the memory kind of the surface. + * comprOffset + * This parameter returns the compression offset of the surface. + * comprFormat + * This parameter returns the type of compression of the surface. + * gpuCacheAttr + * gpuCacheAttr returns the gpu cache attribute of the surface. + * Legal return values for this field are + * NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN + * NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED + * NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED + * gpuP2PCacheAttr + * gpuP2PCacheAttr returns the gpu peer-to-peer cache attribute of the surface. + * Legal return values for this field are + * NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN + * NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED + * NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED + * mmuContext + * mmuContext returns the requested type of physical address + * Legal return values for this field are + * TEGRA_VASPACE_A -- return the non-GPU device physical address ( the system physical address itself) for Tegra engines. + * returns the system physical address, may change to use a class value in future. + * FERMI_VASPACE_A -- return the GPU device physical address( the system physical address, or the SMMU VA) for Big GPU engines. + * 0 -- return the GPU device physical address( the system physical address, or the SMMU VA) for Big GPU engines. + * use of zero may be deprecated in future. + * contigSegmentSize + * If the underlying surface is physically contiguous, this parameter + * returns the size in bytes of the piece of memory starting from + * the offset specified in the memOffset parameter extending to the last + * byte of the surface. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_BAD_OBJECT_HANDLE + * NVOS_STATUS_BAD_OBJECT_PARENT + * NVOS_STATUS_NOT_SUPPORTED + * + */ +#define NV003E_CTRL_CMD_GET_SURFACE_PHYS_ATTR (0x3e0101) /* finn: Evaluated from "(FINN_NV01_MEMORY_SYSTEM_MEMORY_INTERFACE_ID << 8) | NV003E_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS_MESSAGE_ID" */ + +#define NV003E_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV003E_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS { + NV_DECLARE_ALIGNED(NvU64 memOffset, 8); + NvU32 memFormat; + NvU32 comprOffset; + NvU32 comprFormat; + NvU32 gpuCacheAttr; + NvU32 gpuP2PCacheAttr; + NvU32 mmuContext; + NV_DECLARE_ALIGNED(NvU64 contigSegmentSize, 8); +} NV003E_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS; + +/* valid gpuCacheAttr return values */ +#define NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN (0x00000000) +#define NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED (0x00000001) +#define NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED (0x00000002) + +/* NV003E_CTRL_CMD_GET_SURFACE_NUM_PHYS_PAGES + * + * This command returns the number of physical pages associated with the + * memory object. + * + * This call is currently only implemented on Linux and assumes that linux + * kernel in which RM module will be loaded has same page size as defined + * in linux kernel source with which RM module was built. + * + * numPages + * This parameter returns total number of physical pages associated with + * the memory object. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV003E_CTRL_CMD_GET_SURFACE_NUM_PHYS_PAGES (0x3e0102) /* finn: Evaluated from "(FINN_NV01_MEMORY_SYSTEM_MEMORY_INTERFACE_ID << 8) | NV003E_CTRL_GET_SURFACE_NUM_PHYS_PAGES_PARAMS_MESSAGE_ID" */ + +#define NV003E_CTRL_GET_SURFACE_NUM_PHYS_PAGES_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV003E_CTRL_GET_SURFACE_NUM_PHYS_PAGES_PARAMS { + NvU32 numPages; +} NV003E_CTRL_GET_SURFACE_NUM_PHYS_PAGES_PARAMS; + + +/* NV003E_CTRL_CMD_GET_SURFACE_PHYS_PAGES + * + * This command returns physical pages associated with the memory object. + * + * This call is currently only implemented on Linux and assumes that linux + * kernel in which RM module will be loaded has same page size as defined + * in linux kernel source with which RM module was built. + * + * pPages + * This parameter returns physical pages associated with the memory object. + * + * numPages + * This parameter is both an input and an output. As an input parameter, + * it's value indicates maximum number of physical pages to be copied to + * pPages. As an output parameter, it's value indicates number of physical + * pages copied to pPages. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV003E_CTRL_CMD_GET_SURFACE_PHYS_PAGES (0x3e0103) /* finn: Evaluated from "(FINN_NV01_MEMORY_SYSTEM_MEMORY_INTERFACE_ID << 8) | NV003E_CTRL_GET_SURFACE_PHYS_PAGES_PARAMS_MESSAGE_ID" */ + +#define NV003E_CTRL_GET_SURFACE_PHYS_PAGES_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV003E_CTRL_GET_SURFACE_PHYS_PAGES_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pPages, 8); + NvU32 numPages; +} NV003E_CTRL_GET_SURFACE_PHYS_PAGES_PARAMS; + +/* _ctrl003e_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0041.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0041.h new file mode 100644 index 0000000..322393d --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0041.h @@ -0,0 +1,450 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0041.finn +// + +#include "nvos.h" +#include "ctrl/ctrlxxxx.h" +/* NV04_MEMORY control commands and parameters */ + +#define NV0041_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0041, NV0041_CTRL_##cat, idx) + +/* NV04_MEMORY command categories (6bits) */ +#define NV0041_CTRL_RESERVED (0x00) +#define NV0041_CTRL_MEMORY (0x01) + +/* + * NV0041_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0041_CTRL_CMD_NULL (0x410000) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR + * + * This command returns attributes associated with the memory object + * at the given offset. The architecture dependent return parameter + * comprFormat determines the meaningfulness (or not) of comprOffset. + * + * This call is only currently supported in the MODS environment. + * + * memOffset + * This parameter is both an input and an output. As input, this + * parameter holds an offset into the memory surface. The return + * value is the physical address of the surface at the given offset. + * memFormat + * This parameter returns the memory kind of the surface. + * comprOffset + * This parameter returns the compression offset of the surface. + * comprFormat + * This parameter returns the type of compression of the surface. + * memAperture + * The aperture of the surface is returned in this field. + * Legal return values for this parameter are + * NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_VIDMEM + * NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_SYSMEM + * gpuCacheAttr + * gpuCacheAttr returns the gpu cache attribute of the surface. + * Legal return values for this field are + * NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN + * NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED + * NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED + * gpuP2PCacheAttr + * gpuP2PCacheAttr returns the gpu peer-to-peer cache attribute of the surface. + * Legal return values for this field are + * NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN + * NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED + * NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED + * mmuContext + * mmuContext indicates the type of physical address to be returned (input parameter). + * Legal return values for this field are + * TEGRA_VASPACE_A -- return the device physical address for Tegra (non-GPU) engines. This is the system physical address itself. + * returns the system physical address. This may change to use a class value in future. + * FERMI_VASPACE_A -- return the device physical address for GPU engines. This can be a system physical address or a GPU SMMU virtual address. + * 0 -- return the device physical address for GPU engines. This can be a system physical address or a GPU SMMU virtual address. + * use of zero may be deprecated in future. + * contigSegmentSize + * If the underlying surface is physically contiguous, this parameter + * returns the size in bytes of the piece of memory starting from + * the offset specified in the memOffset parameter extending to the last + * byte of the surface. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_BAD_OBJECT_HANDLE + * NVOS_STATUS_BAD_OBJECT_PARENT + * NVOS_STATUS_NOT_SUPPORTED + * + */ +#define NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR (0x410103) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS { + NV_DECLARE_ALIGNED(NvU64 memOffset, 8); + NvU32 memFormat; + NvU32 comprOffset; + NvU32 comprFormat; + NvU32 memAperture; + NvU32 gpuCacheAttr; + NvU32 gpuP2PCacheAttr; + NvU32 mmuContext; + NV_DECLARE_ALIGNED(NvU64 contigSegmentSize, 8); +} NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS; + +/* valid memAperture return values */ +#define NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_VIDMEM (0x00000000) +#define NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_SYSMEM (0x00000001) + +/* valid gpuCacheAttr return values */ +#define NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN (0x00000000) +#define NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED (0x00000001) +#define NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED (0x00000002) + +/* + * NV0041_CTRL_CMD_GET_SURFACE_ZCULL_ID + * + * This command returns the Z-cull identifier for a surface. + * The value of ~0 is returned if there is none associated. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_BAD_OBJECT_HANDLE + * NVOS_STATUS_BAD_OBJECT_PARENT + * NVOS_STATUS_NOT_SUPPORTED + * + */ +#define NV0041_CTRL_CMD_GET_SURFACE_ZCULL_ID (0x410104) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS { + NvU32 zcullId; +} NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS; + + +// return values for 'tilingFormat' +// XXX - the names for these are misleading +#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_INVALID (0x00000000) +#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_FB (0x00000001) +#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_FB_1HIGH (0x00000002) +#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_FB_4HIGH (0x00000003) +#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_UMA_1HIGH (0x00000004) +#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_UMA_4HIGH (0x00000005) + +/* + * NV0041_CTRL_SURFACE_INFO + * + * This structure represents a single 32bit surface value. Clients + * request a particular surface value by specifying a unique surface + * information index. + * + * Legal surface information index values are: + * NV0041_CTRL_SURFACE_INFO_INDEX_ATTRS + * This index is used to request the set of hw attributes associated + * with the surface. Each distinct attribute is represented by a + * single bit flag in the returned value. + * Legal flags values for this index are: + * NV0041_CTRL_SURFACE_INFO_ATTRS_COMPR + * This surface has compression resources bound to it. + * NV0041_CTRL_SURFACE_INFO_ATTRS_ZCULL + * This surface has zcull resources bound to it. + * NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE + * This index is used to request the compression coverage (if any) + * in units of 64K for the associated surface. A value of zero indicates + * there are no compression resources associated with the surface. + * Legal return values range from zero to a maximum number of 64K units + * that is GPU implementation dependent. + * NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_SIZE + * This index is used to request the physically allocated size in units + * of 4K(NV0041_CTRL_SURFACE_INFO_PHYS_SIZE_SCALE_FACTOR) for the associated + * surface. + * NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_ATTR + * This index is used to request the surface attribute field. The returned + * field value can be decoded using the NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_* + * DRF-style macros provided below. + * NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE + * This index is used to request the surface address space type. + * Returned values are described by NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE. + */ +typedef struct NV0041_CTRL_SURFACE_INFO { + NvU32 index; + NvU32 data; +} NV0041_CTRL_SURFACE_INFO; + +/* valid surface info index values */ +#define NV0041_CTRL_SURFACE_INFO_INDEX_ATTRS (0x00000001) +#define NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE (0x00000005) +#define NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_SIZE (0x00000007) +#define NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_ATTR (0x00000008) +#define NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE (0x00000009) + +/* + * This define indicates the scale factor of the reported physical size to the + * actual size in bytes. We use the scale factor to save space from the + * interface and account for large surfaces. To get the actual size, + * use `(NvU64)reported_size * NV0041_CTRL_SURFACE_INFO_PHYS_SIZE_SCALE_FACTOR`. + */ +#define NV0041_CTRL_SURFACE_INFO_PHYS_SIZE_SCALE_FACTOR (0x1000) + +/* valid surface info attr flags */ +#define NV0041_CTRL_SURFACE_INFO_ATTRS_COMPR (0x00000002) +#define NV0041_CTRL_SURFACE_INFO_ATTRS_ZCULL (0x00000004) + +/* Valid surface info page size */ +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE NVOS32_ATTR_PAGE_SIZE +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE_DEFAULT NVOS32_ATTR_PAGE_SIZE_DEFAULT +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE_4KB NVOS32_ATTR_PAGE_SIZE_4KB +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE_BIG NVOS32_ATTR_PAGE_SIZE_BIG +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE_HUGE NVOS32_ATTR_PAGE_SIZE_HUGE + +/* Valid surface info CPU coherency */ +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY NVOS32_ATTR_COHERENCY +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_UNCACHED NVOS32_ATTR_COHERENCY_UNCACHED +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_CACHED NVOS32_ATTR_COHERENCY_CACHED +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_COMBINE NVOS32_ATTR_COHERENCY_WRITE_COMBINE +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_THROUGH NVOS32_ATTR_COHERENCY_WRITE_THROUGH +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_PROTECT NVOS32_ATTR_COHERENCY_WRITE_PROTECT +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_BACK NVOS32_ATTR_COHERENCY_WRITE_BACK + +/* + * NV0041_CTRL_CMD_GET_SURFACE_INFO + * + * This command returns surface information for the associated memory object. + * Requests to retrieve surface information use a list of one or more + * NV0041_CTRL_SURFACE_INFO structures. + * + * surfaceInfoListSize + * This field specifies the number of entries on the caller's + * surfaceInfoList. + * surfaceInfoList + * This field specifies a pointer in the caller's address space + * to the buffer into which the surface information is to be returned. + * This buffer must be at least as big as surfaceInfoListSize multiplied + * by the size of the NV0041_CTRL_SURFACE_INFO structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV0041_CTRL_CMD_GET_SURFACE_INFO (0x410110) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_GET_SURFACE_INFO_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV0041_CTRL_GET_SURFACE_INFO_PARAMS { + NvU32 surfaceInfoListSize; + NV_DECLARE_ALIGNED(NvP64 surfaceInfoList, 8); +} NV0041_CTRL_GET_SURFACE_INFO_PARAMS; + +/* + * NV0041_CTRL_CMD_GET_SURFACE_COMPRESSION_COVERAGE + * + * This command returns the percentage of surface compression tag coverage. + * The value of 0 is returned if there are no tags associated. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_BAD_OBJECT_HANDLE + * NVOS_STATUS_BAD_OBJECT_PARENT + * NVOS_STATUS_NOT_SUPPORTED + * + */ +#define NV0041_CTRL_CMD_GET_SURFACE_COMPRESSION_COVERAGE (0x410112) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS { + NvHandle hSubDevice; /* if non zero subDevice handle of local GPU */ + NvU32 lineMin; + NvU32 lineMax; + NvU32 format; +} NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS; + +/* + * NV0041_CTRL_CMD_GET_FBMEM_BUS_ADDR + * + * This command returns the BAR1 physical address of a + * Memory mapping made using NvRmMapMemory() + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INVALID_DATA + * NV_ERR_INVALID_CLIENT + * NV_ERR_INVALID_OBJECT_HANDLE + * + */ +#define NV0041_CTRL_CMD_GET_FBMEM_BUS_ADDR (0x410114) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_FBMEM_BUS_ADDR_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_GET_FBMEM_BUS_ADDR_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV0041_CTRL_GET_FBMEM_BUS_ADDR_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pLinearAddress, 8); /* [in] Linear address of CPU mapping */ + NV_DECLARE_ALIGNED(NvU64 busAddress, 8); /* [out] BAR1 address */ +} NV0041_CTRL_GET_FBMEM_BUS_ADDR_PARAMS; + +/* + * NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE + * + * This command flushes a cache on the GPU which all memory accesses go + * through. The types of flushes supported by this API may not be supported by + * all hardware. Attempting an unsupported flush type will result in an error. + * + * flags + * Contains flags to control various aspects of the flush. Valid values + * are defined in NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS*. Not all + * flags are valid for all GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NVOS_STATUS_INVALID_ARGUMENT + * NVOS_STATUS_INVALID_STATE + * + * See Also: + * NV0080_CTRL_CMD_DMA_FLUSH + * Performs flush operations in broadcast for the GPU cache and other hardware + * engines. Use this call if you want to flush all GPU caches in a + * broadcast device. + * NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE + * Flushes the entire GPU cache or a set of physical addresses (if the + * hardware supports it). Use this call if you want to flush a set of + * addresses or the entire GPU cache in unicast mode. + * + */ +#define NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE (0x410116) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS { + NvU32 flags; +} NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS; + +#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK 0:0 +#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_NO (0x00000000) +#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_YES (0x00000001) +#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_INVALIDATE 1:1 +#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_NO (0x00000000) +#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_YES (0x00000001) + +/* + * NV0041_CTRL_CMD_GET_EME_PAGE_SIZE + * + * This command may be used to get the memory page size + * + * Parameters: + * pageSize [OUT] + * pageSize with associated memory descriptor + * + * Possible status values are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_NOT_SUPPORTED + */ +#define NV0041_CTRL_CMD_GET_MEM_PAGE_SIZE (0x410118) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS { + NvU32 pageSize; /* [out] - page size */ +} NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS; + +/* + * NV0041_CTRL_CMD_UPDATE_SURFACE_COMPRESSION + * + * Acquire/release compression for surface + * + * Parameters: + * bRelease [IN] + * true = release compression; false = acquire compression + */ +#define NV0041_CTRL_CMD_UPDATE_SURFACE_COMPRESSION (0x410119) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_UPDATE_SURFACE_COMPRESSION_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_UPDATE_SURFACE_COMPRESSION_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV0041_CTRL_UPDATE_SURFACE_COMPRESSION_PARAMS { + NvBool bRelease; /* [in] - acquire/release setting */ +} NV0041_CTRL_UPDATE_SURFACE_COMPRESSION_PARAMS; + +#define NV0041_CTRL_CMD_PRINT_LABELS_PARAMS_MESSAGE_ID (0x50U) + +typedef struct NV0041_CTRL_CMD_PRINT_LABELS_PARAMS { + NvU32 tag; /* [in] */ +} NV0041_CTRL_CMD_PRINT_LABELS_PARAMS; +#define NV0041_CTRL_CMD_SET_LABEL_PARAMS_MESSAGE_ID (0x51U) + +typedef struct NV0041_CTRL_CMD_SET_LABEL_PARAMS { + NvU32 tag; /* [in] */ +} NV0041_CTRL_CMD_SET_LABEL_PARAMS; +#define NV0041_CTRL_CMD_SET_LABEL (0x410151) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_CMD_SET_LABEL_PARAMS_MESSAGE_ID" */ +#define NV0041_CTRL_CMD_GET_LABEL (0x410152) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_CMD_GET_LABEL_PARAMS_MESSAGE_ID" */ +#define NV0041_CTRL_CMD_GET_LABEL_PARAMS_MESSAGE_ID (0x52U) + +typedef struct NV0041_CTRL_CMD_GET_LABEL_PARAMS { + NvU32 tag; /* [in] */ +} NV0041_CTRL_CMD_GET_LABEL_PARAMS; + +/* + * NV0041_CTRL_CMD_SET_TAG + * + * This command sets memory allocation tag used for debugging. +* Every client has it's own memory allocation tag and tag is copying when object is duping. + * This control can be used for shared allocations to change it's tag. + */ +#define NV0041_CTRL_CMD_SET_TAG (0x410120) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_CMD_SET_TAG_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_CMD_SET_TAG_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV0041_CTRL_CMD_SET_TAG_PARAMS { + NvU32 tag; /* [in] */ +} NV0041_CTRL_CMD_SET_TAG_PARAMS; + +/* + * NV0041_CTRL_CMD_GET_TAG + * + * This command returns memory allocation tag used for debugging. + */ +#define NV0041_CTRL_CMD_GET_TAG (0x410121) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_CMD_GET_TAG_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_CMD_GET_TAG_PARAMS_MESSAGE_ID (0x21U) + +typedef struct NV0041_CTRL_CMD_GET_TAG_PARAMS { + NvU32 tag; /* [out] */ +} NV0041_CTRL_CMD_GET_TAG_PARAMS; + +/* _ctrl0041_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073.h new file mode 100644 index 0000000..fa7d8f7 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073.h @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2015,2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073.finn +// + + + + +#include "ctrl/ctrlxxxx.h" +/* category-specific includes */ +#include "ctrl0073/ctrl0073system.h" +#include "ctrl0073/ctrl0073specific.h" +#include "ctrl0073/ctrl0073stereo.h" +#include "ctrl0073/ctrl0073event.h" +#include "ctrl0073/ctrl0073internal.h" +#include "ctrl0073/ctrl0073dfp.h" +#include "ctrl0073/ctrl0073dp.h" +#include "ctrl0073/ctrl0073svp.h" +#include "ctrl0073/ctrl0073dpu.h" +#include "ctrl0073/ctrl0073psr.h" diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h new file mode 100644 index 0000000..970ea3b --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h @@ -0,0 +1,60 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073base.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV04_DISPLAY_COMMON control commands and parameters */ + +#define NV0073_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0073, NV0073_CTRL_##cat, idx) + +/* NV04_DISPLAY_COMMON command categories (6bits) */ +#define NV0073_CTRL_RESERVED (0x00U) +#define NV0073_CTRL_SYSTEM (0x01U) +#define NV0073_CTRL_SPECIFIC (0x02U) +#define NV0073_CTRL_EVENT (0x03U) +#define NV0073_CTRL_INTERNAL (0x04U) +#define NV0073_CTRL_DFP (0x11U) +#define NV0073_CTRL_DP (0x13U) +#define NV0073_CTRL_SVP (0x14U) +#define NV0073_CTRL_DPU (0x15U) +#define NV0073_CTRL_PSR (0x16U) +#define NV0073_CTRL_STEREO (0x17U) + +/* + * NV0073_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0073_CTRL_CMD_NULL (0x730000U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrl0073base_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h new file mode 100644 index 0000000..347b478 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h @@ -0,0 +1,1269 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073dfp.finn +// + +#include "ctrl/ctrl0073/ctrl0073base.h" + +/* NV04_DISPLAY_COMMON dfp-display-specific control commands and parameters */ + +/* + * NV0073_CTRL_CMD_DFP_GET_INFO + * + * This command can be used to determine the associated display type for + * the specified displayId. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must be a dfp display + * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * flags + * This parameter returns the information specific to this dfp. Here are + * the possible fields: + * NV0073_CTRL_DFP_FLAGS_SIGNAL + * This specifies the type of signal used for this dfp. + * NV0073_CTRL_DFP_FLAGS_LANES + * This specifies whether the board supports 1, 2, or 4 lanes + * for DISPLAYPORT signals. + * NV0073_CTRL_DFP_FLAGS_LIMIT + * Some GPUs were not qualified to run internal TMDS except at 60 HZ + * refresh rates. So, if LIMIT_60HZ_RR is set, then the client must + * make sure to only allow 60 HZ refresh rate modes to the OS/User. + * NV0073_CTRL_DFP_FLAGS_SLI_SCALER + * While running in SLI, if SLI_SCALER_DISABLE is set, the GPU cannot + * scale any resolutions. So, the output timing must match the + * memory footprint. + * NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE + * This specifies whether the DFP displayId is capable of + * transmitting HDMI. + * NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE + * This specifies whether the displayId is capable of sending a + * limited color range out from the board. + * NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE + * This specifies whether the displayId is capable of auto-configuring + * the color range. + * NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE + * This specifies whether the displayId is capable of sending the + * YCBCR422 color format out from the board. + * NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE + * This specifies whether the displayId is capable of sending + * YCBCR444 color format out from the board. + * NV0073_CTRL_DFP_FLAGS_DP_LINK_BANDWIDTH + * This specifies whether the displayId is capable of doing high + * bit-rate (2.7Gbps) or low bit-rate (1.62Gbps) if the DFP is + * display port. + * NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED + * This specifies whether the DFP displayId is allowed to transmit HDMI + * based on the VBIOS settings. + * NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT + * This specifies whether the DFP displayId is actually an embedded display + * port based on VBIOS connector information AND ASSR cap. + * NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT + * This specifies whether the DFP displayId must be trained to RBR mode + * (if it is using DP protocol) whenever possible. + * NV0073_CTRL_DFP_FLAGS_LINK + * This specifies whether the board supports single or dual links + * for TMDS, LVDS, and SDI signals. + * NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED + * This specifies if PostCursor2 is disabled in the VBIOS + * NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID + * This indicates whether this SOR uses DSI-A, DSI-B or both (ganged mode). + * NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE + * This indicates whether this DFP supports Dynamic MUX + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_DFP_GET_INFO (0x731140U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_GET_INFO_PARAMS_MESSAGE_ID (0x40U) + +typedef struct NV0073_CTRL_DFP_GET_INFO_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 flags; +} NV0073_CTRL_DFP_GET_INFO_PARAMS; + +/* valid display types */ +#define NV0073_CTRL_DFP_FLAGS_SIGNAL 2:0 +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_TMDS (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_LVDS (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_SDI (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DISPLAYPORT (0x00000003U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DSI (0x00000004U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_WRBK (0x00000005U) +#define NV0073_CTRL_DFP_FLAGS_LANE 5:3 +#define NV0073_CTRL_DFP_FLAGS_LANE_NONE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_LANE_SINGLE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_LANE_DUAL (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_LANE_QUAD (0x00000003U) +#define NV0073_CTRL_DFP_FLAGS_LANE_OCT (0x00000004U) +#define NV0073_CTRL_DFP_FLAGS_LIMIT 6:6 +#define NV0073_CTRL_DFP_FLAGS_LIMIT_DISABLE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_LIMIT_60HZ_RR (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER 7:7 +#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_NORMAL (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_DISABLE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE 8:8 +#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE 9:9 +#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE 10:10 +#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE 11:11 +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE 12:12 +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED 14:14 +#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT 15:15 +#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT 16:16 +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_NONE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_PREFER_RBR (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW 19:17 +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_1_62GBPS (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_2_70GBPS (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_5_40GBPS (0x00000003U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_8_10GBPS (0x00000004U) +#define NV0073_CTRL_DFP_FLAGS_LINK 21:20 +#define NV0073_CTRL_DFP_FLAGS_LINK_NONE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_LINK_SINGLE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_LINK_DUAL (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID 22:22 +#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID 24:23 +#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_NONE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_A (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_B (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_GANGED (0x00000003U) +#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED 25:25 +#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DP_PHY_REPEATER_COUNT 29:26 +#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE 30:30 +#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_TRUE (0x00000001U) + + + +/* + * NV0073_CTRL_CMD_DFP_GET_DP2TMDS_DONGLE_INFO + * + * This command can be used to determine information about dongles attached + * to a displayport connection. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the dfp display which owns the + * panel power to adjust. The display ID must be a dfp display + * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * flags + * This parameter provide state information about the dongle attachments. + * NV0073_CTRL_DFP_GET_DP2TMDS_DONGLE_INFO_FLAGS_CAPABLE + * Specifies if the connection is capable of a dongle. This field + * returns false in all cases of signal types except for those capable + * of outputting TMDS. Even then the if a gpio is not defined, the + * the a statement of false will also be returned. + * NV0073_CTRL_DFP_GET_DP2TMDS_DONGLE_INFO_FLAGS_ATTACHED + * When attached, this value specifies that a dongle is detected and + * attached. The client should read the _TYPE field to determine + * if it is a dp2hdmi or dp2dvi dongle. + * NV0073_CTRL_DFP_GET_DP2TMDS_DONGLE_INFO_FLAGS_TYPE + * _DP2DVI: no response to i2cAddr 0x80 per DP interop guidelines. + * clients MUST avoid outputting HDMI even if capable. + * _DP2HDMI: dongle responds to i2cAddr 0x80 per DP interop guidelines. + * client is allowed to output HDMI when possible. + * _LFH_DVI: DMS59-DVI breakout dongle is in use. + * _LFH_VGA: DMS59-VGA breakout dongle is in use. + * NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE + * _1: Max TMDS Clock rate is 165 MHz for both DVI and HDMI. + * _2: Max TMDS Clock rate will be specified in the dongle + * address space at device address 0x80. + * DVI is up to 165 MHz + * HDMI is up to 300 MHz + * There are type 2 devices that support beyond 600 MHz + * though not defined in the spec. + * maxTmdsClkRateHz + * This defines the max TMDS clock rate for dual mode adaptor in Hz. + */ +#define NV0073_CTRL_CMD_DFP_GET_DISPLAYPORT_DONGLE_INFO (0x731142U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS_MESSAGE_ID (0x42U) + +typedef struct NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 flags; + NvU32 maxTmdsClkRateHz; +} NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS; + +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_CAPABLE 0:0 +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_ATTACHED 1:1 +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_ATTACHED_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_ATTACHED_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE 7:4 +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE_DP2DVI (0x00000000U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE_DP2HDMI (0x00000001U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE_LFH_DVI (0x00000002U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE_LFH_VGA (0x00000003U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE 8:8 +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE_1 (0x00000000U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE_2 (0x00000001U) + + + +/* + * NV0073_CTRL_CMD_DFP_SET_ELD_AUDIO_CAPS + * + * This command is used to inform hardware the receiver's audio capabilities + * using the new EDID Like Data (ELD) memory structure. The ELD memory + * structure is read by the audio driver by issuing the ELD Data command verb. + * This mechanism is used for passing sink device' audio EDID information + * from graphics software to audio software. ELD contents will contain a + * subset of the sink device's EDID information. + * The client should inform hardware at initial boot, a modeset, and whenever + * a hotplug event occurs. + * + * displayId + * This parameter indicates the digital display device's + * mask. This comes as input to this command. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * numELDSize + * This parameter specifies how many bytes of data RM should write to the + * ELD buffer. Section 7.3.3.36 of the ECN specifies that the ELD buffer + * size of zero based. HDAudio driver will then use this information to + * determine how many bytes of the ELD buffer the HDAudio should read. + * The maximum size of the buffer is 96 bytes. + * bufferELD + * This buffer contains data as defined in the ECR HDMI ELD memory structure. + * Refer to the ELD Memory Structure Specification for more details. + * The format should be: + * - Header block is fixed at 4 bytes + * The header block contains the ELD version and baseline ELD len as + * well as some reserved fields. + * - Baseline block for audio descriptors is 76 bytes + * (15 SAD; each SAD=3 bytes requiring 45 bytes with 31 bytes to spare) + * As well as some other bits used to denote the CEA version, + * the speaker allocation data, monitor name, connector type, and + * hdcp capabilities. + * - Vendor specific block of 16 bytes + * maxFreqSupported + * Supply the maximum frequency supported for the overall audio caps. + * This value should match CEA861-X defines for sample freq. + * ctrl: + * NV0073_CTRL_DFP_SET_ELD_AUDIO_CAPS_CTRL_PD: + * Specifies the presence detect of the receiver. On a hotplug + * or modeset client should set this bit to TRUE. + * NV0073_CTRL_DFP_SET_ELD_AUDIO_CAPS_CTRL_ELDV: + * Specifies whether the ELD buffer contents are valid. + * An intrinsic unsolicited response (UR) is generated whenever + * the ELDV bit changes in value and the PD=1. When _PD=1(hotplug), + * RM will set the ELDV bit after ELD buffer contents are written. + * If _ELDV bit is set to false such as during a unplug, then the + * contents of the ELD buffer will be cleared. + * deviceEntry: + * The deviceEntry number from which the SF should accept packets. + * _NONE if disabling audio. + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_DFP_SET_ELD_AUDIO_CAPS (0x731144U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER 96U + +#define NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS_MESSAGE_ID (0x44U) + +typedef struct NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 numELDSize; + NvU8 bufferELD[NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER]; + NvU32 maxFreqSupported; + NvU32 ctrl; + NvU32 deviceEntry; +} NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS; + +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0320KHZ (0x00000001U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0441KHZ (0x00000002U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0480KHZ (0x00000003U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0882KHZ (0x00000004U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0960KHZ (0x00000005U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_1764KHZ (0x00000006U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_1920KHZ (0x00000007U) + +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD 0:0 +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV 1:1 +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV_TRUE (0x00000001U) + +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_0 (0x00000000U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_1 (0x00000001U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_2 (0x00000002U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_3 (0x00000003U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_NONE (0x00000007U) + + + +/* + * NV0073_CTRL_CMD_DFP_GET_SPREAD_SPECTRUM_STATUS + * + * This command is used to get spread spectrum status for a display device. + * + * displayId + * Display ID for which the spread spectrum status is needed. + * checkRMSsState + * Default is to check in Vbios. This flag lets this control call to check in register. + * status + * Return status value. + */ + +#define NV0073_CTRL_CMD_DFP_GET_SPREAD_SPECTRUM (0x73114cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS_MESSAGE_ID (0x4CU) + +typedef struct NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS { + NvU32 displayId; + NvBool enabled; +} NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS; + +/* + * NV0073_CTRL_CMD_DFP_UPDATE_DYNAMIC_DFP_CACHE + * + * Update the Dynamic DFP with Bcaps read from remote display. + * Also updates hdcpFlags, gpu hdcp capable flags in DFP. + * If bResetDfp is true, all the flags are reset before making changes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_DFP_UPDATE_DYNAMIC_DFP_CACHE (0x73114eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS_MESSAGE_ID (0x4EU) + +typedef struct NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS { + NvU32 subDeviceInstance; + NvU32 headIndex; + NvU8 bcaps; + NvU8 bksv[5]; + NvU32 hdcpFlags; + NvBool bHdcpCapable; + NvBool bResetDfp; + NvU8 updateMask; +} NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS; + +#define NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_MASK_BCAPS 0x01U +#define NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_MASK_BKSV 0x02U +#define NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_MASK_FLAGS 0x03U + +/* + * NV0073_CTRL_CMD_DFP_SET_AUDIO_ENABLE + * + * This command sets the audio enable state of the DFP. When disabled, + * no audio stream packets or audio timestamp packets will be sent. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the dfp + * audio should be enabled or disabled. The display ID must be a dfp display. + * If the displayId is not a dfp, this call will return + * NV_ERR_INVALID_ARGUMENT. + * enable + * This parameter specifies whether to enable (NV_TRUE) or disable (NV_FALSE) + * audio to the display. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * + */ +#define NV0073_CTRL_CMD_DFP_SET_AUDIO_ENABLE (0x731150U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS_MESSAGE_ID (0x50U) + +typedef struct NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool enable; +} NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS; + + + +/* + * NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG + * + * This enum defines default/primary/secondary sor sublinks to be configured. + * These access modes are: + * + * NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_NONE + * Default link config + * NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_PRIMARY_SOR_LINK + * Primary sor sublink to be configured + * NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_SECONDARY_SOR_LINK + * Secondary sor sublink to be configured + */ +typedef enum NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG { + NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_NONE = 0, + NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_PRIMARY_SOR_LINK = 1, + NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_SECONDARY_SOR_LINK = 2, +} NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG; + +/* + * NV0073_CTRL_DFP_ASSIGN_SOR_INFO + * + * This structure describes info about assigned SOR + * + * displayMask + * The displayMask for the SOR corresponding to its HW routings + * sorType + * This parameter specifies the SOR type + * Here are the current defined fields: + * NV0073_CTRL_DFP_SOR_TYPE_NONE + * Unallocated SOR + * NV0073_CTRL_DFP_SOR_TYPE_2H1OR_PRIMARY + * Primary SOR for 2H1OR stream + * NV0073_CTRL_DFP_SOR_TYPE_2H1OR_SECONDARY + * Secondary SOR for 2H1OR stream + * NV0073_CTRL_DFP_SOR_TYPE_SINGLE + * Default Single SOR + * Note - sorType should only be referred to identify 2H1OR Primary and Secondary SOR + * + */ + +typedef struct NV0073_CTRL_DFP_ASSIGN_SOR_INFO { + NvU32 displayMask; + NvU32 sorType; +} NV0073_CTRL_DFP_ASSIGN_SOR_INFO; + +#define NV0073_CTRL_DFP_SOR_TYPE_NONE (0x00000000U) +#define NV0073_CTRL_DFP_SOR_TYPE_SINGLE (0x00000001U) +#define NV0073_CTRL_DFP_SOR_TYPE_2H1OR_PRIMARY (0x00000002U) +#define NV0073_CTRL_DFP_SOR_TYPE_2H1OR_SECONDARY (0x00000003U) + +/* + * NV0073_CTRL_CMD_DFP_ASSIGN_SOR + * + * This command is used by the clients to assign SOR to DFP for CROSS-BAR + * when the default SOR-DFP routing that comes from vbios is not considered. + * SOR shall be assigned to a DFP at the runtime. This call should be called + * before a modeset is done on any dfp display and also before LinkTraining for DP displays. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * DisplayId of the primary display for which SOR is to be assigned. However, if + * displayId is 0 then RM shall return the XBAR config it has stored in it's structures. + * sorExcludeMask + * sorMask of the SORs which should not be used for assignment. If this is 0, + * then SW is free to allocate any available SOR. + * slaveDisplayId + * displayId of the slave device in case of dualSST mode. This ctrl call will + * allocate SORs to both slave and the master if slaveDisplayId is set. + * forceSublinkConfig + * forces RM to configure primary or secondary sor sublink on the given diaplayId. + * If not set, then RM will do the default configurations. + * bIs2Head1Or + * Specifies that SOR allocation is required for 2 head 1 OR. This will allocate + * 2 SOR for same displayId - one Master and one Slave. Slave SOR would be disconnected + * from any padlink and get feedback clock from Master SOR's padlink. + * sorAssignList[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS] + * returns the displayMask for all SORs corresponding to their HW routings. + * sorAssignListWithTag[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS] + * returns the displayMask for all SORs corresponding to their HW routings along with + * SOR type to identify 2H1OR Primary and Secondary SORs. SOR type would be identified by + * NV0073_CTRL_DFP_SOR_TYPE. sorAssignList would look as below - + * sorAssignListWithTag[] = { DisplayMask, SOR Type + * {0x100, SECONDARY_SOR} + * {0x200, SINGLE_SOR} + * {0x100, PRIMARY_SOR} + * {0, NONE}} + * } + * Here, for display id = 0x100, SOR2 is Primary and SOR0 is Secondary. + * Note - sorAssignList parameter would be removed after Bug 200749158 is resolved + * reservedSorMask + * returns the sorMask reserved for the internal panels. + * flags + * Other detail settings. + * _AUDIO_OPTIMAL: Client requests trying to get audio SOR if possible. + * If there's no audio capable SOR and OD is HDMI/DP, + * RM will fail the control call. + * _AUDIO_DEFAULT: RM does not check audio-capability of SOR. + * + * _ACTIVE_SOR_NOT_AUDIO_CAPABLE_YES : RM returns Active SOR which is not Audio capable. + * _ACTIVE_SOR_NOT_AUDIO_CAPABLE_NO : RM is not returning 'Active non-audio capable SOR'. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + + +#define NV0073_CTRL_CMD_DFP_ASSIGN_SOR (0x731152U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS 4U + +#define NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS_MESSAGE_ID (0x52U) + +typedef struct NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU8 sorExcludeMask; + NvU32 slaveDisplayId; + NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG forceSublinkConfig; + NvBool bIs2Head1Or; + NvU32 sorAssignList[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS]; + NV0073_CTRL_DFP_ASSIGN_SOR_INFO sorAssignListWithTag[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS]; + NvU8 reservedSorMask; + NvU32 flags; +} NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS; + +#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO 0:0 +#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO_OPTIMAL (0x00000001U) +#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO_DEFAULT (0x00000000U) +#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE 1:1 +#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE_NO (0x00000000U) +#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE_YES (0x00000001U) + +/* +* NV0073_CTRL_CMD_DFP_GET_PADLINK_MASK +* +* This command will only be used by chipTB tests to get the padlinks corresponding +* to the given displayId. RM gets this information from vbios. This control call is +* only for verif purpose. +* +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. This parameter must specify a value between zero and the +* total number of subdevices within the parent device. This parameter +* should be set to zero for default behavior. +* displayId +* DisplayId of the display for which the client needs analog link Mask +* padlinkMask +* analogLinkMask for the given displayId. This value returned is 0xffffffff if +* the given displayId is invalid else RM returns the corresponding padlinkMask. +* NV_OK +* NV_ERR_INVALID_ARGUMENT +* NV_ERR_NOT_SUPPORTED +*/ + + +#define NV0073_CTRL_CMD_DFP_GET_PADLINK_MASK (0x731153U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS_MESSAGE_ID (0x53U) + +typedef struct NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 padlinkMask; +} NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS; + +/* + * NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE + * This enum defines the functions that are supported for which a + * corresponding GPIO pin number could be retrieved + * Values copied from objgpio.h GPIO_FUNC_TYPE_LCD_*. Please keep the + * values in sync between the 2 files + */ + +typedef enum NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE { + // GPIO types of LCD GPIO functions common to all internal panels + NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_BACKLIGHT = 268435456, + NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_POWER = 285212672, + NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_POWER_OK = 301989888, + NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_SELF_TEST = 318767104, + NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_LAMP_STATUS = 335544320, + NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_BRIGHTNESS = 352321536, +} NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE; + +/* + * NV0073_CTRL_CMD_DFP_GET_LCD_GPIO_PIN_NUM + * + * This command can be used to get the GPIO pin number that corresponds to one + * of the LCD functions + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the dfp display. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NVOS_STATUS_ERROR_INVALID_ARGUMENT. + * funcType + * The LDC function for which the GPIO pin number is needed + * lcdGpioPinNum + * The GPIO pin number that corresponds to the LCD function. + * +*/ +#define NV0073_CTRL_CMD_DFP_GET_LCD_GPIO_PIN_NUM (0x731154U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS_MESSAGE_ID (0x54U) + +typedef struct NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE funcType; + NvU32 lcdGpioPinNum; +} NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS; + + + +/* + * NV0073_CTRL_CMD_DFP_CONFIG_TWO_HEAD_ONE_OR + * + * This command is used for configuration of 2 head 1 OR. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * Display Id of the panel for which Two Head One OR is going to be used + * bEnable + * Enable/Disable 2 Head 1 OR + * masterSorIdx + * Master SOR Index which will send pixels to panel + * slaveSorIdx + * Slave SOR Index which will take feedback clock from Master SOR's + * padlink + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + * NVOS_STATUS_ERROR_INVALID_ARGUMENT + * NVOS_STATUS_ERROR_NOT_SUPPORTED + */ + + +#define NV0073_CTRL_CMD_DFP_CONFIG_TWO_HEAD_ONE_OR (0x731156U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS_MESSAGE_ID (0x56U) + +typedef struct NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bEnable; + NvU32 masterSorIdx; + NvU32 slaveSorIdx; +} NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS; + +/* + * NV0073_CTRL_CMD_DFP_DSC_CRC_CONTROL + * + * This command is used to enable/disable CRC on the GPU or query the registers + * related to it + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * headIndex + * index of the head + * cmd + * specifying if setup or querying is done + * bEnable + * enable or disable CRC on the GPU + * gpuCrc0 + * 0-indexed CRC register of the GPU + * gpuCrc1 + * 1-indexed CRC register of the GPU + * gpuCrc0 + * 2-indexed CRC register of the GPU + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + * NVOS_STATUS_ERROR_NOT_SUPPORTED + */ + + +#define NV0073_CTRL_CMD_DFP_DSC_CRC_CONTROL (0x731157U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS_MESSAGE_ID (0x57U) + +typedef struct NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS { + NvU32 subDeviceInstance; + NvU32 headIndex; + NvU32 cmd; + NvBool bEnable; + NvU16 gpuCrc0; + NvU16 gpuCrc1; + NvU16 gpuCrc2; +} NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS; + +#define NV0073_CTRL_DP_CRC_CONTROL_CMD 0:0 +#define NV0073_CTRL_DP_CRC_CONTROL_CMD_SETUP (0x00000000U) +#define NV0073_CTRL_DP_CRC_CONTROL_CMD_QUERY (0x00000001U) + +/* + * NV0073_CTRL_CMD_DFP_INIT_MUX_DATA + * + * This control call is used to configure the display MUX related data + * for the given display device. Clients to RM are expected to call this + * control call to initialize the data related to MUX before any MUX related + * operations such mux switch or PSR entry/ exit are performed. + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId (in) + * ID of the display device for which the mux state has to be initialized + * manfId (in) + * Specifies the manufacturer ID of panel obtained from the EDID. This + * parameter is expected to be non-zero only in case of internal panel. + * productId (in) + * Specifies the product ID of panel obtained from the EDID. This + * parameter is expected to be non-zero only in case of internal panel. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_DFP_INIT_MUX_DATA (0x731158U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS_MESSAGE_ID (0x58U) + +typedef struct NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU16 manfId; + NvU16 productId; +} NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS; + + + +/* + * NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX + * + * This command is used to switch the dynamic display mux between + * integrated GPU and discrete GPU. + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId (in) + * ID of the display device for which the display MUX has to be switched + * flags (in) + * Flags indicating the action to be performed. Here are the possible + * valid values- + * NV0073_CTRL_DFP_DISP_MUX_SWITCH_IGPU_TO_DGPU + * When set mux is switched from integrated to discrete GPU. + * NV0073_CTRL_DFP_DISP_MUX_SWITCH_DGPU_TO_IGPU + * When set mux is switched from discrete to integrated GPU. + * NV0073_CTRL_DFP_DISP_MUX_SWITCH_SKIP_SIDEBAND_ACCESS + * Set to true for PSR panels as we skip sideband access. + * auxSettleDelay (in) + * Time, in milliseconds, necessary for AUX channel to settle and become + * accessible after a mux switch. Set to zero to use the default delay. + * muxSwitchLatencyMs (out) + * mux switch latency stats in milli-seconds + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX (0x731160U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS_MESSAGE_ID (0x60U) + +typedef struct NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 flags; + NvU32 auxSettleDelay; + NvU32 muxSwitchLatencyMs; +} NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS; + +/* valid flags*/ +#define NV0073_CTRL_DFP_DISP_MUX_SWITCH 0:0 +#define NV0073_CTRL_DFP_DISP_MUX_SWITCH_IGPU_TO_DGPU 0x00000000 +#define NV0073_CTRL_DFP_DISP_MUX_SWITCH_DGPU_TO_IGPU 0x00000001 +#define NV0073_CTRL_DFP_DISP_MUX_SWITCH_SKIP_SIDEBAND_ACCESS 1:1 +#define NV0073_CTRL_DFP_DISP_MUX_SWITCH_SKIP_SIDEBAND_ACCESS_YES 0x00000001 +#define NV0073_CTRL_DFP_DISP_MUX_SWITCH_SKIP_SIDEBAND_ACCESS_NO 0x00000000 + +/* + * NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS + * + * This command is used to perform all the operations that need to be + * performed before a mux switch is started. + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId (in) + * ID of the display device for which the pre mux switch operations have + * to be performed. + * flags (in) + * Flags indicating the action to be performed. Here are the possible + * valid values - + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_IGPU_TO_DGPU + * Indicates a switch from i to d is initiated + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_DGPU_TO_IGPU + * Indicates a switch from d to i is initiated + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP_NO + * When set RM will execute the PSR enter sequence. By default RM will + * not skip SR enter sequence + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP_YES + * When set RM will skip the PSR enter sequence + * iGpuBrightness (in) + * iGPU brightness value (scale 0~100) before switching mux from I2D. + * This is used to match brightness after switching mux to dGPU + * preOpsLatencyMs (out) + * premux switch operations latency stats in milli-seconds. This includes - + * - disabling SOR sequencer and enable BL GPIO control + * - toggling LCD VDD, BL EN and PWM MUX GPIOs + * - PSR entry, if not skipped + * psrEntryLatencyMs (out) + * psr entry latency stats in milli-seconds + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS (0x731161U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS_MESSAGE_ID (0x61U) + +typedef struct NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 flags; + NvU32 iGpuBrightness; + NvU32 preOpsLatencyMs; + NvU32 psrEntryLatencyMs; +} NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS; + +/* valid flags*/ +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE 0:0 +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_IGPU_TO_DGPU 0x00000000U +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_DGPU_TO_IGPU 0x00000001U +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP 1:1 +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP_NO 0x00000000U +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP_YES 0x00000001U +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING 2:2 +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_KNOWN 0x00000000 +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_UNKNOWN 0x00000001 + +#define NV0073_CTRL_DISP_MUX_BACKLIGHT_BRIGHTNESS_MIN 0U +#define NV0073_CTRL_DISP_MUX_BACKLIGHT_BRIGHTNESS_MAX 100U + +/* + * NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS + * + * This command is used to perform all the operations that need to be + * performed after a successful mux switch is completed. + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId (in) + * ID of the display device for which the post mux switch operations have + * to be performed. + * flags (in) + * Flags indicating the action to be performed. Here are the possible + * valid values - + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_IGPU_TO_DGPU + * Indicates a switch from i to d is initiated + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_DGPU_TO_IGPU + * Indicates a switch from d to i is initiated + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP_NO + * When set RM will execute the PSR exit sequence. By default RM will + * not skip SR exit sequence + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP_YES + * When set RM will skip the PSR exit sequence + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_KNOWN + * Indicates mux switches where we know when igpu powers up + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_UNKNOWN + * Indicates mux switches where we don't know when igpu powers up + * postOpsLatencyMs (out) + * postmux switch operations latency stats in milli-seconds. This includes - + * - restoring SOR sequencer and BL GPIO control + * - toggling LCD VDD, BL EN and PWM MUX GPIOs + * - PSR exit, if not skipped + * psrExitLatencyMs (out) + * psr exit latency stats in milli-seconds + * psrExitTransitionToInactiveLatencyMs (out) + * psr exit latency stats in milli-seconds, from state 2 (SR active) to state 4 (transition to inactive) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_TIMEOUT in case of SR exit failure + */ + +#define NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS (0x731162U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS_MESSAGE_ID (0x62U) + +typedef struct NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 flags; + NvU32 postOpsLatencyMs; + NvU32 psrExitLatencyMs; + NvU32 psrExitTransitionToInactiveLatencyMs; +} NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS; + +/* valid flags*/ +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE 0:0 +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP 1:1 +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP_NO 0x00000000U +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP_YES 0x00000001U + +/* + * NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS + * + * This command is used to query the display mux status for the given + * display device + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId (in) + * ID of the display device for which the post mux switch operations have + * to be performed. + * muxStatus (out) + * status indicating the current state of the mux. + * valid values - + * NV0073_CTRL_DFP_DISP_MUX_STATE_INTEGRATED_GPU + * Indicates that the MUX is currently switched to integrated GPU. + * NV0073_CTRL_DFP_DISP_MUX_STATE_DISCRETE_GPU + * Indicates that the MUX is currently switched to discrete GPU. + * NV0073_CTRL_DFP_DISP_MUX_MODE_DISCRETE_ONLY + * Indicates that the MUX mode is set to discrete mode, where all displays + * are driven by discrete GPU. + * NV0073_CTRL_DFP_DISP_MUX_MODE_INTEGRATED_ONLY + * Indicates that the MUX mode is set to integrated mode, where all + * displays are driven by Integrated GPU. + * NV0073_CTRL_DFP_DISP_MUX_MODE_HYBRID + * Indicates that the MUX mode is set to hybrid, where internal panel is + * driven by integrated GPU, while external displays might be driven by + * discrete GPU. + * NV0073_CTRL_DFP_DISP_MUX_MODE_DYNAMIC + * Indicates that the MUX mode is dynamic. It is only in this mode, the + * display MUX can be toggled between discrete and hybrid dynamically. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS (0x731163U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS_MESSAGE_ID (0x63U) + +typedef struct NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 muxStatus; +} NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS; + +/* valid flags */ +#define NV0073_CTRL_DFP_DISP_MUX_STATE 1:0 +#define NV0073_CTRL_DFP_DISP_MUX_STATE_INVALID 0x00000000U +#define NV0073_CTRL_DFP_DISP_MUX_STATE_INTEGRATED_GPU 0x00000001U +#define NV0073_CTRL_DFP_DISP_MUX_STATE_DISCRETE_GPU 0x00000002U +#define NV0073_CTRL_DFP_DISP_MUX_MODE 4:2 +#define NV0073_CTRL_DFP_DISP_MUX_MODE_INVALID 0x00000000U +#define NV0073_CTRL_DFP_DISP_MUX_MODE_INTEGRATED_ONLY 0x00000001U +#define NV0073_CTRL_DFP_DISP_MUX_MODE_DISCRETE_ONLY 0x00000002U +#define NV0073_CTRL_DFP_DISP_MUX_MODE_HYBRID 0x00000003U +#define NV0073_CTRL_DFP_DISP_MUX_MODE_DYNAMIC 0x00000004U + + + +/* +* NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING +* +* This command can be used to get DSI mode timing parameters. +* +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. This parameter must specify a value between zero and the +* total number of subdevices within the parent device. This parameter +* should be set to zero for default behavior. +* displayId +* This parameter specifies the ID of the display on which the DSI +* info will be set. The display ID must be a DSI-capable display. +* hActive +* This parameter specifies the horizontal length of the active pixel +* data in the raster. +* vActive +* This parameter specifies the vertical lines of the active pixel +* data in the raster. +* hFrontPorch +* This parameter specifies the number of horizontal front porch +* blanking pixels in the raster. +* vFrontPorch +* This parameter specifies the numer of lines of the vertical front +* porch in the raster. +* hBackPorch +* This parameter specifies the number of horizontal back porch +* blanking pixels in the raster. +* vBackPorch +* This parameter specifies the numer of lines of the vertical back +* porch in the raster. +* hSyncWidth +* This parameter specifies the number of horizontal sync pixels in +* the raster. +* vSyncWidth +* This parameter specifies the numer of lines of the vertical sync +* in the raster. +* bpp +* This parameter specifies the depth (Bits per Pixel) of the output +* display stream. +* refresh +* This parameter specifies the refresh rate of the panel (in Hz). +* pclkHz +* This parameter specifies the pixel clock rate in Hz. +* numLanes +* Number of DSI data lanes. +* dscEnable +* Flag to indicate if DSC an be enabled, which in turn indicates if +* panel supports DSC. +* dscBpp +* DSC Bits per pixel +* dscNumSlices +* Number of slices for DSC. +* dscDuaDsc +* Flag to indicate if panel supports DSC streams from two DSI +* controllers. +* dscSliceHeight +* Height of DSC slices. +* dscBlockPrediction +* Flag to indicate if DSC Block Prediction needs to be enabled. +* dscDecoderVersionMajor +* Major version number of DSC decoder on Panel. +* dscDecoderVersionMinor +* Minor version number of DSC decoder on Panel. +* dscUseCustomPPS +* Flag to indicate if Panel uses custom PPS values which deviate from standard values. +* dscCustomPPSData +* 32 bytes of custom PPS data required by Panel. +* dscEncoderCaps +* Capabilities of DSC encoder in SoC. +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_ARGUMENT +* NV_ERR_NOT_SUPPORTED +*/ + +#define NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING (0x731166U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DFP_DSI_CUSTOM_PPS_DATA_COUNT 32U + +#define NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS_MESSAGE_ID (0x66U) + +typedef struct NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 hActive; + NvU32 vActive; + NvU32 hFrontPorch; + NvU32 vFrontPorch; + NvU32 hBackPorch; + NvU32 vBackPorch; + NvU32 hSyncWidth; + NvU32 vSyncWidth; + NvU32 bpp; + NvU32 refresh; + NvU32 pclkHz; + NvU32 numLanes; + NvU32 dscEnable; + NvU32 dscBpp; + NvU32 dscNumSlices; + NvU32 dscDualDsc; + NvU32 dscSliceHeight; + NvU32 dscBlockPrediction; + NvU32 dscDecoderVersionMajor; + NvU32 dscDecoderVersionMinor; + NvBool dscUseCustomPPS; + NvU32 dscCustomPPSData[NV0073_CTRL_CMD_DFP_DSI_CUSTOM_PPS_DATA_COUNT]; + + struct { + NvBool bDscSupported; + NvU32 encoderColorFormatMask; + NvU32 lineBufferSizeKB; + NvU32 rateBufferSizeKB; + NvU32 bitsPerPixelPrecision; + NvU32 maxNumHztSlices; + NvU32 lineBufferBitDepth; + } dscEncoderCaps; +} NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS; + + + +/* + * NV0073_CTRL_CMD_DFP_GET_FIXED_MODE_TIMING + * + * This control call is used to retrieve the display mode timing info that's + * specified for a given DFP from an offline configuration blob (e.g., Device Tree). + * This display timing info is intended to replace the timings exposed in a + * sink's EDID. + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId (in) + * ID of the display device for which the timings should be retrieved. + * stream (in) + * For MST connectors with static topologies (e.g., DP serializers), + * this parameter further identifies the video stream for which the + * timings should be retrieved. + * valid (out) + * Indicates whether a valid display timing was found for this DFP. + * hActive (out) + * Horizontal active width in pixels + * hFrontPorch (out) + * Horizontal front porch + * hSyncWidth (out) + * Horizontal sync width + * hBackPorch (out) + * Horizontal back porch + * vActive (out) + * Vertical active height in lines + * vFrontPorch (out) + * Vertical front porch + * vSyncWidth (out) + * Vertical sync width + * vBackPorch (out) + * Vertical back porch + * pclkKHz (out) + * Pixel clock frequency in KHz + * rrx1k (out) + * Refresh rate in units of 0.001Hz + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_DFP_GET_FIXED_MODE_TIMING (0x731172) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8 | NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS_MESSAGE_ID)" */ + +#define NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS_MESSAGE_ID (0x72U) + +typedef struct NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU8 stream; + + NvBool valid; + + NvU16 hActive; + NvU16 hFrontPorch; + NvU16 hSyncWidth; + NvU16 hBackPorch; + + NvU16 vActive; + NvU16 vFrontPorch; + NvU16 vSyncWidth; + NvU16 vBackPorch; + + NvU32 pclkKHz; + NvU32 rrx1k; +} NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS; + +/* _ctrl0073dfp_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h new file mode 100644 index 0000000..e593227 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h @@ -0,0 +1,2767 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073dp.finn +// + +#include "ctrl/ctrl0073/ctrl0073base.h" + +/* NV04_DISPLAY_COMMON dfp-display-specific control commands and parameters */ + +/* + * NV0073_CTRL_CMD_DP_AUXCH_CTRL + * + * This command can be used to perform an aux channel transaction to the + * displayPort receiver. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must a dfp display. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * bAddrOnly + * If set to NV_TRUE, this parameter prompts an address-only + * i2c-over-AUX transaction to be issued, if supported. Else the + * call fails with NVOS_STATUS_ERR_NOT_SUPPORTED. The size parameter is + * expected to be 0 for address-only transactions. + * cmd + * This parameter is an input to this command. The cmd parameter follows + * Section 2.4 AUX channel syntax in the DisplayPort spec. + * Here are the current defined fields: + * NV0073_CTRL_DP_AUXCH_CMD_TYPE + * This specifies the request command transaction + * NV0073_CTRL_DP_AUXCH_CMD_TYPE_I2C + * Set this value to indicate a I2C transaction. + * NV0073_CTRL_DP_AUXCH_CMD_TYPE_AUX + * Set this value to indicate a DisplayPort transaction. + * NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT + * This field is dependent on NV0073_CTRL_DP_AUXCH_CMD_TYPE. + * It is only valid if NV0073_CTRL_DP_AUXCH_CMD_TYPE_I2C + * is specified above and indicates a middle of transaction. + * In the case of AUX, this field should be set to zero. The valid + * values are: + * NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT_FALSE + * The I2C transaction is not in the middle of a transaction. + * NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT_TRUE + * The I2C transaction is in the middle of a transaction. + * NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE + * The request type specifies if we are doing a read/write or write + * status request: + * NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_READ + * An I2C or AUX channel read is requested. + * NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_WRITE + * An I2C or AUX channel write is requested. + * NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_WRITE_STATUS + * An I2C write status request desired. This value should + * not be set in the case of an AUX CH request and only applies + * to I2C write transaction command. + * addr + * This parameter is an input to this command. The addr parameter follows + * Section 2.4 in DisplayPort spec and the client should refer to the valid + * address in DisplayPort spec. Only the first 20 bits are valid. + * data[] + * In the case of a read transaction, this parameter returns the data from + * transaction request. In the case of a write transaction, the client + * should write to this buffer for the data to send. The max # of bytes + * allowed is NV0073_CTRL_DP_AUXCH_MAX_DATA_SIZE. + * size + * Specifies how many data bytes to read/write depending on the transaction type. + * The input size value should be indexed from 0. That means if you want to read + * 1 byte -> size = 0, 2 bytes -> size = 1, 3 bytes -> size = 2, up to 16 bytes + * where size = 15. On return, this parameter returns total number of data bytes + * successfully read/written from/to the transaction (indexed from 1). That is, + * if you successfully requested 1 byte, you would send down size = 0. On return, + * you should expect size = 1 if all 1 byte were successfully read. (Note that + * it is valid for a display to reply with fewer than the requested number of + * bytes; in that case, it is up to the client to make a new request for the + * remaining bytes.) + * replyType + * This parameter is an output to this command. It returns the auxChannel + * status after the end of the aux Ch transaction. The valid values are + * based on the DisplayPort spec: + * NV0073_CTRL_DP_AUXCH_REPLYTYPE_ACK + * In the case of a write, + * AUX: write transaction completed and all data bytes written. + * I2C: return size bytes has been written to i2c slave. + * In the case of a read, return of ACK indicates ready to reply + * another read request. + * NV0073_CTRL_DP_AUXCH_REPLYTYPE_NACK + * In the case of a write, first return size bytes have been written. + * In the case of a read, implies that does not have requested data + * for the read request transaction. + * NV0073_CTRL_DP_AUXCH_REPLYTYPE_DEFER + * Not ready for the write/read request and client should retry later. + * NV0073_CTRL_DP_DISPLAYPORT_AUXCH_REPLYTYPE_I2CNACK + * Applies to I2C transactions only. For I2C write transaction: + * has written the first return size bytes to I2C slave before getting + * NACK. For a read I2C transaction, the I2C slave has NACKED the I2C + * address. + * NV0073_CTRL_DP_AUXCH_REPLYTYPE_I2CDEFER + * Applicable to I2C transactions. For I2C write and read + * transactions, I2C slave has yet to ACK or NACK the I2C transaction. + * NV0073_CTRL_DP_AUXCH_REPLYTYPE_TIMEOUT + * The receiver did not respond within the timeout period defined in + * the DisplayPort 1.1a specification. + * retryTimeMs + * This parameter is an output to this command. In case of + * NVOS_STATUS_ERROR_RETRY return status, this parameter returns the time + * duration in milli-seconds after which client should retry this command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_ERROR_RETRY + */ +#define NV0073_CTRL_CMD_DP_AUXCH_CTRL (0x731341U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_AUXCH_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_AUXCH_MAX_DATA_SIZE 16U +#define NV0073_CTRL_DP_AUXCH_CTRL_PARAMS_MESSAGE_ID (0x41U) + +typedef struct NV0073_CTRL_DP_AUXCH_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bAddrOnly; + NvU32 cmd; + NvU32 addr; + NvU8 data[NV0073_CTRL_DP_AUXCH_MAX_DATA_SIZE]; + NvU32 size; + NvU32 replyType; + NvU32 retryTimeMs; +} NV0073_CTRL_DP_AUXCH_CTRL_PARAMS; + +#define NV0073_CTRL_DP_AUXCH_CMD_TYPE 3:3 +#define NV0073_CTRL_DP_AUXCH_CMD_TYPE_I2C (0x00000000U) +#define NV0073_CTRL_DP_AUXCH_CMD_TYPE_AUX (0x00000001U) +#define NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT 2:2 +#define NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT_FALSE (0x00000000U) +#define NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT_TRUE (0x00000001U) +#define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE 1:0 +#define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_WRITE (0x00000000U) +#define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_READ (0x00000001U) +#define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_WRITE_STATUS (0x00000002U) + +#define NV0073_CTRL_DP_AUXCH_ADDR 20:0 + +#define NV0073_CTRL_DP_AUXCH_REPLYTYPE 3:0 +#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_ACK (0x00000000U) +#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_NACK (0x00000001U) +#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_DEFER (0x00000002U) +#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_TIMEOUT (0x00000003U) +#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_I2CNACK (0x00000004U) +#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_I2CDEFER (0x00000008U) + +//This is not the register field, this is software failure case when we +//have invalid argument +#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_INVALID_ARGUMENT (0xffffffffU) + +/* + * NV0073_CTRL_CMD_DP_AUXCH_SET_SEMA + * + * This command can be used to set the semaphore in order to gain control of + * the aux channel. This control is only used in HW verification. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must a dfp display + * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * owner + * This parameter is an input to this command. + * Here are the current defined fields: + * NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_RM + * Write the aux channel semaphore for resource manager to own the + * the aux channel. + * NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_VBIOS + * Write the aux channel semaphore for vbios/efi to own the + * the aux channel. This value is used only for HW verification + * and should not be used in normal driver operation. + * NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_PMU + * Write the aux channel semaphore for pmu to own the + * the aux channel. This value is used only by pmu + * and should not be used in normal driver operation. + * NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_DPU + * Write the aux channel semaphore for dpu to own the + * the aux channel and should not be used in normal + * driver operation. + * NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_SEC2 + * Write the aux channel semaphore for sec2 to own the + * the aux channel and should not be used in normal + * driver operation. + * NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_RELEASE + * Write the aux channel semaphore for hardware to own the + * the aux channel. This value is used only for HW verification + * and should not be used in normal driver operation. + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_DP_AUXCH_SET_SEMA (0x731342U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_AUXCH_SET_SEMA_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_AUXCH_SET_SEMA_PARAMS_MESSAGE_ID (0x42U) + +typedef struct NV0073_CTRL_DP_AUXCH_SET_SEMA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 owner; +} NV0073_CTRL_DP_AUXCH_SET_SEMA_PARAMS; + +#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER 2:0 +#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_RELEASE (0x00000000U) +#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_RM (0x00000001U) +#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_VBIOS (0x00000002U) +#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_PMU (0x00000003U) +#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_DPU (0x00000004U) +#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_SEC2 (0x00000005U) + +/* + * NV0073_CTRL_CMD_DP_CTRL + * + * This command is used to set various displayPort configurations for + * the specified displayId such a lane count and link bandwidth. It + * is assumed that link training has already occurred. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must a dfp display. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * cmd + * This parameter is an input to this command. + * Here are the current defined fields: + * NV0073_CTRL_DP_CMD_SET_LANE_COUNT + * Set to specify the number of displayPort lanes to configure. + * NV0073_CTRL_DP_CMD_SET_LANE_COUNT_FALSE + * No request to set the displayport lane count. + * NV0073_CTRL_DP_CMD_SET_LANE_COUNT_TRUE + * Set this value to indicate displayport lane count change. + * NV0073_CTRL_DP_CMD_SET_LINK_BANDWIDTH + * Set to specify a request to change the link bandwidth. + * NV0073_CTRL_DP_CMD_SET_LINK_BANDWIDTH_FALSE + * No request to set the displayport link bandwidth. + * NV0073_CTRL_DP_CMD_SET_LINK_BANDWIDTH_TRUE + * Set this value to indicate displayport link bandwidth change. + * NV0073_CTRL_DP_CMD_SET_LINK_BANDWIDTH + * Set to specify a request to change the link bandwidth. + * NV0073_CTRL_DP_CMD_SET_LINK_BANDWIDTH_FALSE + * No request to set the displayport link bandwidth. + * NV0073_CTRL_DP_CMD_SET_LINK_BANDWIDTH_TRUE + * Set this value to indicate displayport link bandwidth change. + * NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD + * Set to disable downspread during link training. + * NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD_FALSE + * Downspread will be enabled. + * NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD_TRUE + * Downspread will be disabled (e.g. for compliance testing). + * NV0073_CTRL_DP_CMD_SET_FORMAT_MODE + * This field specifies the DP stream mode. + * NV0073_CTRL_DP_CMD_SET_FORMAT_MODE_SINGLE_STREAM + * This value indicates that single stream mode is specified. + * NV0073_CTRL_DP_CMD_SET_FORMAT_MODE_MULTI_STREAM + * This value indicates that multi stream mode is specified. + * NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING + * Set to do Fast link training (avoid AUX transactions for link + * training). We need to restore all the previous trained link settings + * (e.g. the drive current/preemphasis settings) before doing FLT. + * During FLT, we send training pattern 1 followed by training pattern 2 + * each for a period of 500us. + * NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING_NO + * Not a fast link training scenario. + * NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING_YES + * Do fast link training. + * NV0073_CTRL_DP_CMD_NO_LINK_TRAINING + * Set to do No link training. We need to restore all the previous + * trained link settings (e.g. the drive current/preemphasis settings) + * before doing NLT, but we don't need to do the Clock Recovery and + * Channel Equalization. (Please refer to NVIDIA PANEL SELFREFRESH + * CONTROLLER SPECIFICATION 3.1.6 for detail flow) + * NV0073_CTRL_DP_CMD_NO_LINK_TRAINING_NO + * Not a no link training scenario. + * NV0073_CTRL_DP_CMD_NO_LINK_TRAINING_YES + * Do no link training. + * NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING + * Specifies whether RM should use the DP Downspread setting specified by + * NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD command regardless of what the Display + * is capable of. This is used along with the Fake link training option so that + * we can configure the GPU to enable/disable spread when a real display is + * not connected. + * NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING_FORCE + * RM Always use the DP Downspread setting specified. + * NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING_DEFAULT + * RM will enable Downspread only if the display supports it. (default) + * NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING + * Specifies whether RM should skip HW training of the link. + * If this is the case then RM only updates its SW state without actually + * touching any HW registers. Clients should use this ONLY if it has determined - + * a. link is trained and not lost + * b. desired link config is same as current trained link config + * c. link is not in D3 (should be in D0) + * NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING_NO + * RM doesn't skip HW LT as the current Link Config is not the same as the + * requested Link Config. + * NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING_YES + * RM skips HW LT and only updates its SW state as client has determined that + * the current state of the link and the requested Link Config is the same. + * NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG + * Set if the client does not want link training to happen. + * This should ONLY be used for HW verification. + * NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG_FALSE + * This is normal production behaviour which shall perform + * link training or follow the normal procedure for lane count + * reduction. + * NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG_TRUE + * Set this value to not perform link config steps, this should + * only be turned on for HW verif testing. If _LINK_BANDWIDTH + * or _LANE_COUNT is set, RM will only write to the TX DP registers + * and perform no link training. + * NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED + * This field specifies if source grants Post Link training Adjustment request or not. + * NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED_NO + * Source does not grant Post Link training Adjustment request + * NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED_YES + * Source grants Post Link training Adjustment request + * Source wants to link train LT Tunable Repeaters + * NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING + * This field specifies if fake link training is to be done. This will + * program enough of the hardware to avoid any hardware hangs and + * depending upon option chosen by the client, OR will be enabled for + * transmisssion. + * NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_NO + * No Fake LT will be performed + * NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_DONOT_TOGGLE_TRANSMISSION + * SOR will be not powered up during Fake LT + * NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_TOGGLE_TRANSMISSION_ON + * SOR will be powered up during Fake LT + * NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER + * This field specifies if source wants to link train LT Tunable Repeaters or not. + * NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER_NO + * Source does not want to link train LT Tunable Repeaters + * NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER_YES + * NV0073_CTRL_DP_CMD_BANDWIDTH_TEST + * Set if the client wants to reset the link after the link + * training is done. As a part of uncommtting a DP display. + * NV0073_CTRL_DP_CMD_BANDWIDTH_TEST_NO + * This is for normal operation, if DD decided not to reset the link. + * NV0073_CTRL_DP_CMD_BANDWIDTH_TEST_YES + * This is to reset the link, if DD decided to uncommit the display because + * the link is no more required to be enabled, as in a DP compliance test. + * NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE + * Set if the client does not want link training to happen. + * This should ONLY be used for HW verification if necessary. + * NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_FALSE + * This is normal production behaviour which shall perform + * pre link training checks such as if both rx and tx are capable + * of the requested config for lane and link bw. + * NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_TRUE + * Set this value to bypass link config check, this should + * only be turned on for HW verif testing. If _LINK_BANDWIDTH + * or _LANE_COUNT is set, RM will not check TX and DX caps. + * NV0073_CTRL_DP_CMD_FALLBACK_CONFIG + * Set if requested config by client fails and if link if being + * trained for the fallback config. + * NV0073_CTRL_DP_CMD_FALLBACK_CONFIG_FALSE + * This is the normal case when the link is being trained for a requested config. + * NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_TRUE + * Set this value in case the link configuration for requested config fails + * and the link is being trained for a fallback config. + * NV0073_CTRL_DP_CMD_ENABLE_FEC + * Specifies whether RM should set NV_DPCD14_FEC_CONFIGURATION_FEC_READY + * before link training if client has determined that FEC is required(for DSC). + * If required to be enabled RM sets FEC enable bit in panel, start link training. + * Enabling/disabling FEC on GPU side is not done during Link training + * and RM Ctrl call NV0073_CTRL_CMD_DP_CONFIGURE_FEC has to be called + * explicitly to enable/disable FEC after LT(including PostLT LQA). + * If enabled, FEC would be disabled while powering down the link. + * Client has to make sure to account for 3% overhead of transmitting + * FEC symbols while calculating DP bandwidth. + * NV0073_CTRL_DP_CMD_ENABLE_FEC_FALSE + * This is the normal case when FEC is not required + * NV0073_CTRL_DP_CMD_ENABLE_FEC_TRUE + * Set this value in case FEC needs to be enabled + * data + * This parameter is an input and output to this command. + * Here are the current defined fields: + * NV0073_CTRL_DP_DATA_SET_LANE_COUNT + * This field specifies the desired setting for lane count. A client + * may choose any lane count as long as it does not exceed the + * capability of DisplayPort receiver as indicated in the + * receiver capability field. The valid values for this field are: + * NV0073_CTRL_DP_DATA_SET_LANE_COUNT_0 + * For zero-lane configurations, link training is shut down. + * NV0073_CTRL_DP_DATA_SET_LANE_COUNT_1 + * For one-lane configurations, lane0 is used. + * NV0073_CTRL_DP_DATA_SET_LANE_COUNT_2 + * For two-lane configurations, lane0 and lane1 is used. + * NV0073_CTRL_DP_DATA_SET_LANE_COUNT_4 + * For four-lane configurations, all lanes are used. + * NV0073_CTRL_DP_DATA_SET_LANE_COUNT_8 + * For devices that supports 8-lane DP. + * On return, the lane count setting is returned which may be + * different from the requested input setting. + * NV0073_CTRL_DP_DATA_SET_LINK_BW + * This field specifies the desired setting for link bandwidth. There + * are only four supported main link bandwidth settings. The + * valid values for this field are: + * NV0073_CTRL_DP_DATA_SET_LINK_BW_1_62GBPS + * NV0073_CTRL_DP_DATA_SET_LINK_BW_2_70GBPS + * NV0073_CTRL_DP_DATA_SET_LINK_BW_5_40GBPS + * NV0073_CTRL_DP_DATA_SET_LINK_BW_8_10GBPS + * On return, the link bandwidth setting is returned which may be + * different from the requested input setting. + * NV0073_CTRL_DP_DATA_TARGET + * This field specifies which physical repeater or sink to be trained. + * Client should make sure + * 1. Physical repeater should be targeted in order, start from the one closest to GPU. + * 2. All physical repeater is properly trained before targets sink. + * The valid values for this field are: + * NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_X + * 'X' denotes physical repeater index. It's a 1-based index to + * reserve 0 for _SINK. + * 'X' can't be more than 8. + * NV0073_CTRL_DP_DATA_TARGET_SINK + * err + * This parameter specifies provides info regarding the outcome + * of this calling control call. If zero, no errors were found. + * Otherwise, this parameter will specify the error detected. + * The valid parameter is broken down as follows: + * NV0073_CTRL_DP_ERR_SET_LANE_COUNT + * If set to _ERR, set lane count failed. + * NV0073_CTRL_DP_ERR_SET_LINK_BANDWIDTH + * If set to _ERR, set link bandwidth failed. + * NV0073_CTRL_DP_ERR_DISABLE_DOWNSPREAD + * If set to _ERR, disable downspread failed. + * NV0073_CTRL_DP_ERR_INVALID_PARAMETER + * If set to _ERR, at least one of the calling functions + * failed due to an invalid parameter. + * NV0073_CTRL_DP_ERR_SET_LINK_TRAINING + * If set to _ERR, link training failed. + * NV0073_CTRL_DP_ERR_TRAIN_PHY_REPEATER + * If set to _ERR, the operation to Link Train repeater is failed. + * NV0073_CTRL_DP_ERR_ENABLE_FEC + * If set to _ERR, the operation to enable FEC is failed. + * retryTimeMs + * This parameter is an output to this command. In case of + * NVOS_STATUS_ERROR_RETRY return status, this parameter returns the time + * duration in milli-seconds after which client should retry this command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_ERROR_RETRY + */ + +#define NV0073_CTRL_CMD_DP_CTRL (0x731343U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_CTRL_PARAMS_MESSAGE_ID (0x43U) + +typedef struct NV0073_CTRL_DP_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 cmd; + NvU32 data; + NvU32 err; + NvU32 retryTimeMs; + NvU32 eightLaneDpcdBaseAddr; +} NV0073_CTRL_DP_CTRL_PARAMS; + +#define NV0073_CTRL_DP_CMD_SET_LANE_COUNT 0:0 +#define NV0073_CTRL_DP_CMD_SET_LANE_COUNT_FALSE (0x00000000U) +#define NV0073_CTRL_DP_CMD_SET_LANE_COUNT_TRUE (0x00000001U) +#define NV0073_CTRL_DP_CMD_SET_LINK_BW 1:1 +#define NV0073_CTRL_DP_CMD_SET_LINK_BW_FALSE (0x00000000U) +#define NV0073_CTRL_DP_CMD_SET_LINK_BW_TRUE (0x00000001U) +#define NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD 2:2 +#define NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD_FALSE (0x00000000U) +#define NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD_TRUE (0x00000001U) +#define NV0073_CTRL_DP_CMD_UNUSED 3:3 +#define NV0073_CTRL_DP_CMD_SET_FORMAT_MODE 4:4 +#define NV0073_CTRL_DP_CMD_SET_FORMAT_MODE_SINGLE_STREAM (0x00000000U) +#define NV0073_CTRL_DP_CMD_SET_FORMAT_MODE_MULTI_STREAM (0x00000001U) +#define NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING 5:5 +#define NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING_NO (0x00000000U) +#define NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING_YES (0x00000001U) +#define NV0073_CTRL_DP_CMD_NO_LINK_TRAINING 6:6 +#define NV0073_CTRL_DP_CMD_NO_LINK_TRAINING_NO (0x00000000U) +#define NV0073_CTRL_DP_CMD_NO_LINK_TRAINING_YES (0x00000001U) +#define NV0073_CTRL_DP_CMD_SET_ENHANCED_FRAMING 7:7 +#define NV0073_CTRL_DP_CMD_SET_ENHANCED_FRAMING_FALSE (0x00000000U) +#define NV0073_CTRL_DP_CMD_SET_ENHANCED_FRAMING_TRUE (0x00000001U) +#define NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING 8:8 +#define NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING_DEFAULT (0x00000000U) +#define NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING_FORCE (0x00000001U) +#define NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING 9:9 +#define NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING_NO (0x00000000U) +#define NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING_YES (0x00000001U) +#define NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED 10:10 +#define NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED_NO (0x00000000U) +#define NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED_YES (0x00000001U) +#define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING 12:11 +#define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_NO (0x00000000U) +#define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_DONOT_TOGGLE_TRANSMISSION (0x00000001U) +#define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_TOGGLE_TRANSMISSION_ON (0x00000002U) +#define NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER 13:13 +#define NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER_NO (0x00000000U) +#define NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER_YES (0x00000001U) +#define NV0073_CTRL_DP_CMD_FALLBACK_CONFIG 14:14 +#define NV0073_CTRL_DP_CMD_FALLBACK_CONFIG_FALSE (0x00000000U) +#define NV0073_CTRL_DP_CMD_FALLBACK_CONFIG_TRUE (0x00000001U) +#define NV0073_CTRL_DP_CMD_ENABLE_FEC 15:15 +#define NV0073_CTRL_DP_CMD_ENABLE_FEC_FALSE (0x00000000U) +#define NV0073_CTRL_DP_CMD_ENABLE_FEC_TRUE (0x00000001U) + +#define NV0073_CTRL_DP_CMD_BANDWIDTH_TEST 29:29 +#define NV0073_CTRL_DP_CMD_BANDWIDTH_TEST_NO (0x00000000U) +#define NV0073_CTRL_DP_CMD_BANDWIDTH_TEST_YES (0x00000001U) +#define NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE 30:30 +#define NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG 31:31 +#define NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG_FALSE (0x00000000U) +#define NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG_TRUE (0x00000001U) + +#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT 4:0 +#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_0 (0x00000000U) +#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_1 (0x00000001U) +#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_2 (0x00000002U) +#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_4 (0x00000004U) +#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_8 (0x00000008U) +#define NV0073_CTRL_DP_DATA_SET_LINK_BW 15:8 +#define NV0073_CTRL_DP_DATA_SET_LINK_BW_1_62GBPS (0x00000006U) +#define NV0073_CTRL_DP_DATA_SET_LINK_BW_2_16GBPS (0x00000008U) +#define NV0073_CTRL_DP_DATA_SET_LINK_BW_2_43GBPS (0x00000009U) +#define NV0073_CTRL_DP_DATA_SET_LINK_BW_2_70GBPS (0x0000000AU) +#define NV0073_CTRL_DP_DATA_SET_LINK_BW_3_24GBPS (0x0000000CU) +#define NV0073_CTRL_DP_DATA_SET_LINK_BW_4_32GBPS (0x00000010U) +#define NV0073_CTRL_DP_DATA_SET_LINK_BW_5_40GBPS (0x00000014U) +#define NV0073_CTRL_DP_DATA_SET_LINK_BW_8_10GBPS (0x0000001EU) +#define NV0073_CTRL_DP_DATA_SET_ENHANCED_FRAMING 18:18 +#define NV0073_CTRL_DP_DATA_SET_ENHANCED_FRAMING_NO (0x00000000U) +#define NV0073_CTRL_DP_DATA_SET_ENHANCED_FRAMING_YES (0x00000001U) +#define NV0073_CTRL_DP_DATA_TARGET 22:19 +#define NV0073_CTRL_DP_DATA_TARGET_SINK (0x00000000U) +#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_0 (0x00000001U) +#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_1 (0x00000002U) +#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_2 (0x00000003U) +#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_3 (0x00000004U) +#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_4 (0x00000005U) +#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_5 (0x00000006U) +#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_6 (0x00000007U) +#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_7 (0x00000008U) + +#define NV0073_CTRL_DP_ERR_SET_LANE_COUNT 0:0 +#define NV0073_CTRL_DP_ERR_SET_LANE_COUNT_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_SET_LANE_COUNT_ERR (0x00000001U) +#define NV0073_CTRL_DP_ERR_SET_LINK_BW 1:1 +#define NV0073_CTRL_DP_ERR_SET_LINK_BW_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_SET_LINK_BW_ERR (0x00000001U) +#define NV0073_CTRL_DP_ERR_DISABLE_DOWNSPREAD 2:2 +#define NV0073_CTRL_DP_ERR_DISABLE_DOWNSPREAD_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_DISABLE_DOWNSPREAD_ERR (0x00000001U) +#define NV0073_CTRL_DP_ERR_UNUSED 3:3 +#define NV0073_CTRL_DP_ERR_CLOCK_RECOVERY 4:4 +#define NV0073_CTRL_DP_ERR_CLOCK_RECOVERY_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_CLOCK_RECOVERY_ERR (0x00000001U) +#define NV0073_CTRL_DP_ERR_CHANNEL_EQUALIZATION 5:5 +#define NV0073_CTRL_DP_ERR_CHANNEL_EQUALIZATION_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_CHANNEL_EQUALIZATION_ERR (0x00000001U) +#define NV0073_CTRL_DP_ERR_TRAIN_PHY_REPEATER 6:6 +#define NV0073_CTRL_DP_ERR_TRAIN_PHY_REPEATER_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_TRAIN_PHY_REPEATER_ERR (0x00000001U) +#define NV0073_CTRL_DP_ERR_ENABLE_FEC 7:7 +#define NV0073_CTRL_DP_ERR_ENABLE_FEC_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_ENABLE_FEC_ERR (0x00000001U) +#define NV0073_CTRL_DP_ERR_CR_DONE_LANE 11:8 +#define NV0073_CTRL_DP_ERR_CR_DONE_LANE_0_LANE (0x00000000U) +#define NV0073_CTRL_DP_ERR_CR_DONE_LANE_1_LANE (0x00000001U) +#define NV0073_CTRL_DP_ERR_CR_DONE_LANE_2_LANE (0x00000002U) +#define NV0073_CTRL_DP_ERR_CR_DONE_LANE_4_LANE (0x00000004U) +#define NV0073_CTRL_DP_ERR_CR_DONE_LANE_8_LANE (0x00000008U) +#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE 15:12 +#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE_0_LANE (0x00000000U) +#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE_1_LANE (0x00000001U) +#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE_2_LANE (0x00000002U) +#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE_4_LANE (0x00000004U) +#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE_8_LANE (0x00000008U) +#define NV0073_CTRL_DP_ERR_INVALID_PARAMETER 30:30 +#define NV0073_CTRL_DP_ERR_INVALID_PARAMETER_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_INVALID_PARAMETER_ERR (0x00000001U) +#define NV0073_CTRL_DP_ERR_LINK_TRAINING 31:31 +#define NV0073_CTRL_DP_ERR_LINK_TRAINING_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_LINK_TRAINING_ERR (0x00000001U) + +/* + * NV0073_CTRL_DP_LANE_DATA_PARAMS + * + * This structure provides lane characteristics. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must a dfp display. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * numLanes + * Indicates number of lanes for which the data is valid + * data + * This parameter is an input to this command. + * Here are the current defined fields: + * NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS + * This field specifies the preemphasis level set in the lane. + * The valid values for this field are: + * NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_NONE + * No-preemphais for this lane. + * NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL1 + * Preemphasis set to 3.5 dB. + * NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL2 + * Preemphasis set to 6.0 dB. + * NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL3 + * Preemphasis set to 9.5 dB. + * NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT + * This field specifies the drive current set in the lane. + * The valid values for this field are: + * NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL0 + * Drive current level is set to 8 mA + * NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL1 + * Drive current level is set to 12 mA + * NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL2 + * Drive current level is set to 16 mA + * NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL3 + * Drive current level is set to 24 mA + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_MAX_LANES 8U + +typedef struct NV0073_CTRL_DP_LANE_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 numLanes; + NvU32 data[NV0073_CTRL_MAX_LANES]; +} NV0073_CTRL_DP_LANE_DATA_PARAMS; + +#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS 1:0 +#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_NONE (0x00000000U) +#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL1 (0x00000001U) +#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL2 (0x00000002U) +#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL3 (0x00000003U) +#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT 3:2 +#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL0 (0x00000000U) +#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL1 (0x00000001U) +#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL2 (0x00000002U) +#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL3 (0x00000003U) + +/* + * NV0073_CTRL_CMD_GET_DP_LANE_DATA + * + * This command is used to get the current pre-emphasis and drive current + * level values for the specified number of lanes. + * + * The command takes a NV0073_CTRL_DP_LANE_DATA_PARAMS structure as the + * argument with the appropriate subDeviceInstance and displayId filled. + * The arguments of this structure and the format of preemphasis and drive- + * current levels are described above. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * NOTE: This control call is only for testing purposes and + * should not be used in normal DP operations. Preemphais + * and drive current level will be set during Link training + * in normal DP operations + * + */ + +#define NV0073_CTRL_CMD_DP_GET_LANE_DATA (0x731345U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | 0x45" */ + + +/* + * NV0073_CTRL_CMD_SET_DP_LANE_DATA + * + * This command is used to set the pre-emphasis and drive current + * level values for the specified number of lanes. + * + * The command takes a NV0073_CTRL_DP_LANE_DATA_PARAMS structure as the + * argument with the appropriate subDeviceInstance, displayId, number of + * lanes, preemphasis and drive current values filled in. + * The arguments of this structure and the format of preemphasis and drive- + * current levels are described above. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * NOTE: This control call is only for testing purposes and + * should not be used in normal DP operations. Preemphais + * and drivecurrent will be set during Link training in + * normal DP operations + * + */ + +#define NV0073_CTRL_CMD_DP_SET_LANE_DATA (0x731346U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | 0x46" */ + +/* + * NV0073_CTRL_DP_CSTM + * + * This structure specifies the 80 bit DP CSTM Test Pattern data + * The fields of this structure are to be specified as follows: + * lower takes bits 31:0 + * middle takes bits 63:32 + * upper takes bits 79:64 + * + */ +typedef struct NV0073_CTRL_DP_CSTM { + NvU32 lower; + NvU32 middle; + NvU32 upper; +} NV0073_CTRL_DP_CSTM; + +/* + * NV0073_CTRL_DP_TESTPATTERN + * + * This structure specifies the possible test patterns available in + * display port. The field testPattern can be one of the following + * values. + * NV0073_CTRL_DP_SET_TESTPATTERN_DATA_NONE + * No test pattern on the main link + * NV0073_CTRL_DP_SET_TESTPATTERN_DATA_D10_2 + * D10.2 pattern on the main link + * NV0073_CTRL_DP_SET_TESTPATTERN_DATA_SERMP + * SERMP pattern on main link + * NV0073_CTRL_DP_SET_TESTPATTERN_DATA_PRBS_7 + * PRBS7 pattern on the main link + * + */ + +typedef struct NV0073_CTRL_DP_TESTPATTERN { + NvU32 testPattern; +} NV0073_CTRL_DP_TESTPATTERN; + +#define NV0073_CTRL_DP_TESTPATTERN_DATA 2:0 +#define NV0073_CTRL_DP_TESTPATTERN_DATA_NONE (0x00000000U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_D10_2 (0x00000001U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_SERMP (0x00000002U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_7 (0x00000003U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_CSTM (0x00000004U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_HBR2COMPLIANCE (0x00000005U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_CP2520PAT3 (0x00000006U) + +/* + * NV0073_CTRL_CMD_DP_SET_TESTPATTERN + * + * This command forces the main link to output the selected test patterns + * supported in DP specs. + * + * The command takes a NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS structure as the + * argument with the appropriate subDeviceInstance, displayId and test pattern + * to be set as inputs. + * The arguments of this structure and the format of test patterns are + * described above. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must a dfp display. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * testPattern + * This parameter is of type NV0073_CTRL_DP_TESTPATTERN and specifies + * the testpattern to set on displayport. The format of this structure + * is described above. + * laneMask + * This parameter specifies the bit mask of DP lanes on which test + * pattern is to be applied. + * lower + * This parameter specifies the lower 64 bits of the CSTM test pattern + * upper + * This parameter specifies the upper 16 bits of the CSTM test pattern + * bIsHBR2 + * This Boolean parameter is set to TRUE if HBR2 compliance test is + * being performed. + * bSkipLaneDataOverride + * skip override of pre-emp and drive current + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * NOTE: This control call is only for testing purposes and + * should not be used in normal DP operations. Preemphais + * and drivecurrent will be set during Link training in + * normal DP operations + * + */ + +#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_MESSAGE_ID (0x47U) + +typedef struct NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NV0073_CTRL_DP_TESTPATTERN testPattern; + NvU8 laneMask; + NV0073_CTRL_DP_CSTM cstm; + NvBool bIsHBR2; + NvBool bSkipLaneDataOverride; +} NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS; + +#define NV0073_CTRL_CMD_DP_SET_TESTPATTERN (0x731347U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_CSTM0 31:0 +#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_CSTM1 63:32 +#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_CSTM2 15:0 + +/* + * NV0073_CTRL_CMD_GET_DP_TESTPATTERN + * + * This command returns the current test pattern set on the main link of + * Display Port. + * + * The command takes a NV0073_CTRL_DP_GET_TESTPATTERN_PARAMS structure as the + * argument with the appropriate subDeviceInstance, displayId as inputs and + * returns the current test pattern in testPattern field of the structure. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must a dfp display. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * testPattern + * This parameter is of type NV0073_CTRL_DP_TESTPATTERN and specifies the + * testpattern set on displayport. The format of this structure is + * described above. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * NOTE: This control call is only for testing purposes and + * should not be used in normal DP operations. + * + */ + +#define NV0073_CTRL_DP_GET_TESTPATTERN_PARAMS_MESSAGE_ID (0x48U) + +typedef struct NV0073_CTRL_DP_GET_TESTPATTERN_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NV0073_CTRL_DP_TESTPATTERN testPattern; +} NV0073_CTRL_DP_GET_TESTPATTERN_PARAMS; + + +#define NV0073_CTRL_CMD_DP_GET_TESTPATTERN (0x731348U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_TESTPATTERN_PARAMS_MESSAGE_ID" */ + +/* + * NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA + * + * This structure specifies the Pre-emphasis/Drive Current/Postcursor2/TxPu information + * for a display port device. These are the the current values that RM is + * using to map the levels for Pre-emphasis and Drive Current for Link + * Training. + * preEmphasis + * This field specifies the preemphasis values. + * driveCurrent + * This field specifies the driveCurrent values. + * postcursor2 + * This field specifies the postcursor2 values. + * TxPu + * This field specifies the pull-up current source drive values. + */ +#define NV0073_CTRL_MAX_DRIVECURRENT_LEVELS 4U +#define NV0073_CTRL_MAX_PREEMPHASIS_LEVELS 4U +#define NV0073_CTRL_MAX_POSTCURSOR2_LEVELS 4U + +typedef struct NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_1 { + NvU32 preEmphasis; + NvU32 driveCurrent; + NvU32 postCursor2; + NvU32 TxPu; +} NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_1; + +typedef NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_1 NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_SLICE1[NV0073_CTRL_MAX_PREEMPHASIS_LEVELS]; + +typedef NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_SLICE1 NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_SLICE2[NV0073_CTRL_MAX_DRIVECURRENT_LEVELS]; + +typedef NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_SLICE2 NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA[NV0073_CTRL_MAX_POSTCURSOR2_LEVELS]; + + +/* + * NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA + * + * This command is used to override the Pre-emphasis/Drive Current/PostCursor2/TxPu + * data in the RM. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the digital display for which the + * data should be returned. The display ID must a digital display. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * dpData + * This parameter is of type NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA + * and specifies the Pre-emphasis/Drive Current/Postcursor2/TxPu information + * for a display port device. + * The command takes a NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS + * structure as the argument with the appropriate subDeviceInstance, displayId, + * and dpData. The fields of this structure are described above. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS_MESSAGE_ID (0x51U) + +typedef struct NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA dpData; +} NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS; + +#define NV0073_CTRL_CMD_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA (0x731351U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS_MESSAGE_ID" */ + +/* + * NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA + * + * This command is used to get the Pre-emphasis/Drive Current/PostCursor2/TxPu data. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the digital display for which the + * data should be returned. The display ID must a digital display. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * The command takes a NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS + * structure as the argument with the appropriate subDeviceInstance, displayId, + * and dpData. The fields of this structure are described above. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS_MESSAGE_ID (0x52U) + +typedef struct NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA dpData; +} NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS; + +#define NV0073_CTRL_CMD_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA (0x731352U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS_MESSAGE_ID" */ + + + +/* + * NV0073_CTRL_CMD_DP_MAIN_LINK_CTRL + * + * This command is used to set various Main Link configurations for + * the specified displayId such as powering up/down Main Link. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the DP display which owns + * the Main Link to be adjusted. The display ID must a DP display + * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * ctrl + * Here are the current defined fields: + * NV0073_CTRL_DP_MAIN_LINK_CTRL_POWER_STATE_POWERDOWN + * This value will power down Main Link. + * NV0073_CTRL_DP_MAIN_LINK_CTRL_POWER_STATE_POWERUP + * This value will power up Main Link. + * +*/ +#define NV0073_CTRL_CMD_DP_MAIN_LINK_CTRL (0x731356U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_MAIN_LINK_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_MAIN_LINK_CTRL_PARAMS_MESSAGE_ID (0x56U) + +typedef struct NV0073_CTRL_DP_MAIN_LINK_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 ctrl; +} NV0073_CTRL_DP_MAIN_LINK_CTRL_PARAMS; + +#define NV0073_CTRL_DP_MAIN_LINK_CTRL_POWER_STATE 0:0 +#define NV0073_CTRL_DP_MAIN_LINK_CTRL_POWER_STATE_POWERDOWN (0x00000000U) +#define NV0073_CTRL_DP_MAIN_LINK_CTRL_POWER_STATE_POWERUP (0x00000001U) + + + +/* + * NV0073_CTRL_CMD_DP_GET_AUDIO_MUTESTREAM + * + * This command returns the current audio mute state on the main link of Display Port + * + * The command takes a NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS structure as the + * argument with the appropriate subDeviceInstance, displayId as inputs and returns the + * current mute status in mute field of the structure. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the audio stream + * state should be returned. The display ID must a DP display. + * If the display ID is invalid or if it is not a DP display, + * this call will return NV_ERR_INVALID_ARGUMENT. + * mute + * This parameter will return one of the following values: + * NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_DISABLE + * Audio mute is currently disabled. + * NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_ENABLE + * Audio mute is currently enabled. + * NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_AUTO + * Audio mute is automatically controlled by hardware. + * NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_UNKNOWN + * Audio mute is currently in an unknown state. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * + */ +#define NV0073_CTRL_CMD_DP_GET_AUDIO_MUTESTREAM (0x731358U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID (0x58U) + +typedef struct NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 mute; +} NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS; + +#define NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_DISABLE (0x00000000U) +#define NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_ENABLE (0x00000001U) +#define NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_AUTO (0x00000002U) +#define NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_UNKNOWN (0x00000003U) + +/* + * NV0073_CTRL_CMD_DP_SET_AUDIO_MUTESTREAM + * + * This command sets the current audio mute state on the main link of Display Port + * + * The command takes a NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS structure as the + * argument with the appropriate subDeviceInstance, displayId as inputs and whether to enable + * or disable mute in the parameter - mute. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the audio stream + * state should be returned. The display ID must a DP display. + * If the display ID is invalid or if it is not a DP display, + * this call will return NV_ERR_INVALID_ARGUMENT. + * mute + * This parameter is an input to this command. + * Here are the current defined values: + * NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_DISABLE + * Audio mute will be disabled. + * NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_ENABLE + * Audio mute will be enabled. + * NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_AUTO + * Audio mute will be automatically controlled by hardware. + * + * Note: Any other value for mute in NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS is not allowed and + * the API will return an error. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * + */ +#define NV0073_CTRL_CMD_DP_SET_AUDIO_MUTESTREAM (0x731359U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID (0x59U) + +typedef struct NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 mute; +} NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_ASSR_CTRL + * + * This command is used to control and query DisplayPort ASSR + * settings for the specified displayId. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the DP display which owns + * the Main Link to be adjusted. The display ID must a DP display + * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * cmd + * This input parameter specifies the command to execute. Legal + * values for this parameter include: + * NV0073_CTRL_DP_ASSR_CMD_QUERY_STATE + * This field can be used to query ASSR state. When used the ASSR + * state value is returned in the data parameter. + * NV0073_CTRL_DP_ASSR_CMD_DISABLE + * This field can be used to control the ASSR disable state. + * NV0073_CTRL_DP_ASSR_CMD_FORCE_STATE + * This field can be used to control ASSR State without looking at + * whether the display supports it. Used in conjunction with + * Fake link training. Note that this updates the state on the + * source side only. The sink is assumed to be configured for ASSR + * by the client (DD). + * data + * This parameter specifies the data associated with the cmd + * parameter. + * NV0073_CTRL_DP_ASSR_DATA_STATE_ENABLED + * This field indicates the state of ASSR when queried using cmd + * parameter. When used to control the State, it indicates whether + * ASSR should be enabled or disabled. + * NV0073_CTRL_DP_ASSR_DATA_STATE_ENABLED_NO + * When queried this flag indicates that ASSR is not enabled on the sink. + * When used as the data for CMD_FORCE_STATE, it requests ASSR to + * to be disabled on the source side. + * NV0073_CTRL_DP_ASSR_DATA_STATE_ENABLED_YES + * When queried this flag indicates that ASSR is not enabled on the sink. + * When used as the data for CMD_FORCE_STATE, it requests ASSR to + * to be enabled on the source side. + * err + * This output parameter specifies any errors associated with the cmd + * parameter. + * NV0073_CTRL_DP_ASSR_ERR_CAP + * This field indicates the error pertaining to ASSR capability of + * the sink device. + * NV0073_CTRL_DP_ASSR_ERR_CAP_NOERR + * This flag indicates there is no error. + * NV0073_CTRL_DP_ASSR_ERR_CAP_ERR + * This flag indicates that the sink is not ASSR capable. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_CMD_DP_ASSR_CTRL (0x73135aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_ASSR_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_ASSR_CTRL_PARAMS_MESSAGE_ID (0x5AU) + +typedef struct NV0073_CTRL_DP_ASSR_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 cmd; + NvU32 data; + NvU32 err; +} NV0073_CTRL_DP_ASSR_CTRL_PARAMS; + +#define NV0073_CTRL_DP_ASSR_CMD 31:0 +#define NV0073_CTRL_DP_ASSR_CMD_QUERY_STATE (0x00000001U) +#define NV0073_CTRL_DP_ASSR_CMD_DISABLE (0x00000002U) +#define NV0073_CTRL_DP_ASSR_CMD_FORCE_STATE (0x00000003U) +#define NV0073_CTRL_DP_ASSR_CMD_ENABLE (0x00000004U) +#define NV0073_CTRL_DP_ASSR_DATA_STATE_ENABLED 0:0 +#define NV0073_CTRL_DP_ASSR_DATA_STATE_ENABLED_NO (0x00000000U) +#define NV0073_CTRL_DP_ASSR_DATA_STATE_ENABLED_YES (0x00000001U) +#define NV0073_CTRL_DP_ASSR_ERR_CAP 0:0 +#define NV0073_CTRL_DP_ASSR_ERR_CAP_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ASSR_ERR_CAP_ERR (0x00000001U) + +/* + * NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID + * + * This command is used to assign a displayId from the free pool + * to a specific AUX Address in a DP 1.2 topology. The topology + * is uniquely identified by the DisplayId of the DP connector. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This is the DisplayId of the DP connector to which the topology + * is rooted. + * preferredDisplayId + * Client can sent a preferredDisplayID which RM can use during allocation + * if available. If this Id is a part of allDisplayMask in RM then we return + * a free available Id to the client. However, if this is set to + * NV0073_CTRL_CMD_DP_INVALID_PREFERRED_DISPLAY_ID then we return allDisplayMask value. + * useBFM + * Set to true if DP-BFM is used during emulation/RTL Sim. + * + * [out] displayIdAssigned + * This is the out field that will receive the new displayId. If the + * function fails this is guaranteed to be 0. + * [out] allDisplayMask + * This is allDisplayMask RM variable which is returned only when + * preferredDisplayId is set to NV0073_CTRL_CMD_DP_INVALID_PREFERRED_DISPLAY_ID + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID (0x73135bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS_MESSAGE_ID" */ + +/* + * There cannot be more than 128 devices in a topology (also by DP 1.2 specification) + * NOTE: Temporarily lowered to pass XAPI RM tests. Should be reevaluated! + */ +#define NV0073_CTRL_CMD_DP_MAX_TOPOLOGY_NODES 120U +#define NV0073_CTRL_CMD_DP_INVALID_PREFERRED_DISPLAY_ID 0xffffffffU + +#define NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS_MESSAGE_ID (0x5BU) + +typedef struct NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 preferredDisplayId; + + NvBool force; + NvBool useBFM; + + NvU32 displayIdAssigned; + NvU32 allDisplayMask; +} NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID + * + * This command is used to return a multistream displayid to the unused pool. + * You must not call this function while either the ARM or ASSEMBLY state cache + * refers to this display-id. The head must not be attached. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This is the displayId to free. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + * + */ +#define NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID (0x73135cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS_MESSAGE_ID (0x5CU) + +typedef struct NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; +} NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS; + + + +/* + * NV0073_CTRL_CMD_DP_GET_LINK_CONFIG + * + * This command is used to query DisplayPort link config + * settings on the transmitter side. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the DP display which owns + * the Main Link to be queried. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * laneCount + * Number of lanes the DP transmitter hardware is set up to drive. + * linkBW + * The BW of each lane that the DP transmitter hardware is set up to drive. + * The values returned will be according to the DP specifications. + * + */ +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG (0x731360U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS_MESSAGE_ID (0x60U) + +typedef struct NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 laneCount; + NvU32 linkBW; +} NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS; + +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT 3:0 +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_0 (0x00000000U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_1 (0x00000001U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_2 (0x00000002U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_4 (0x00000004U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW 3:0 +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_1_62GBPS (0x00000006U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_2_70GBPS (0x0000000aU) + +/* + * NV0073_CTRL_CMD_DP_GET_EDP_DATA + * + * This command is used to query Embedded DisplayPort information. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the eDP display which owns + * the Main Link to be queried. + * If more than one displayId bit is set or the displayId is not a eDP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * data + * This output parameter specifies the data associated with the eDP display. + * It is only valid if this function returns NV_OK. + * NV0073_CTRL_CMD_DP_GET_EDP_DATA_PANEL_POWER + * This field indicates the state of the eDP panel power. + * NV0073_CTRL_CMD_DP_GET_EDP_DATA_PANEL_POWER_OFF + * This eDP panel is powered off. + * NV0073_CTRL_CMD_DP_GET_EDP_DATA_PANEL_POWER_ON + * This eDP panel is powered on. + * NV0073_CTRL_CMD_DP_GET_EDP_DATA_DPCD_POWER_OFF + * This field tells the client if DPCD power off command + * should be used for the current eDP panel. + * NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_OFF_ENABLE + * This eDP panel can use DPCD to power off the panel. + * NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_OFF_DISABLE + * This eDP panel cannot use DPCD to power off the panel. + * NV0073_CTRL_DP_GET_EDP_DATA_DPCD_SET_POWER + * This field tells the client current eDP panel DPCD SET_POWER (0x600) status + * NV0073_CTRL_DP_GET_EDP_DATA_DPCD_SET_POWER_D0 + * This eDP panel is current up and in full power mode. + * NV0073_CTRL_DP_GET_EDP_DATA_DPCD_SET_POWER_D3 + * This eDP panel is current standby. + */ +#define NV0073_CTRL_CMD_DP_GET_EDP_DATA (0x731361U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_EDP_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_GET_EDP_DATA_PARAMS_MESSAGE_ID (0x61U) + +typedef struct NV0073_CTRL_DP_GET_EDP_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 data; +} NV0073_CTRL_DP_GET_EDP_DATA_PARAMS; + +#define NV0073_CTRL_DP_GET_EDP_DATA_PANEL_POWER 0:0 +#define NV0073_CTRL_DP_GET_EDP_DATA_PANEL_POWER_OFF (0x00000000U) +#define NV0073_CTRL_DP_GET_EDP_DATA_PANEL_POWER_ON (0x00000001U) +#define NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_OFF 1:1 +#define NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_OFF_ENABLE (0x00000000U) +#define NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_OFF_DISABLE (0x00000001U) +#define NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_STATE 2:2 +#define NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_STATE_D0 (0x00000000U) +#define NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_STATE_D3 (0x00000001U) +/* + * NV0073_CTRL_CMD_DP_CONFIG_STREAM + * + * This command sets various multi/single stream related params for + * for a given head. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * Head + * Specifies the head index for the stream. + * sorIndex + * Specifies the SOR index for the stream. + * dpLink + * Specifies the DP link: either 0 or 1 (A , B) + * bEnableOverride + * Specifies whether we're manually configuring this stream. + * If not set, none of the remaining settings have any effect. + * bMST + * Specifies whether in Multistream or Singlestream mode. + * MST/SST + * Structures for passing in either Multistream or Singlestream params + * slotStart + * Specifies the start value of the timeslot + * slotEnd + * Specifies the end value of the timeslot + * PBN + * Specifies the PBN for the timeslot. + * minHBlank + * Specifies the min HBlank + * minVBlank + * Specifies the min VBlank + * sendACT -- deprecated. A new control call has been added. + * Specifies whether ACT has to be sent or not. + * tuSize + * Specifies TU size value + * watermark + * Specifies stream watermark. + * linkClkFreqHz -- moving to MvidWarParams. Use that instead. + * Specifies the link freq in Hz. Note that this is the byte clock. + * eg: = (5.4 Ghz / 10) + * actualPclkHz; -- moving to MvidWarParams. Use that instead. + * Specifies the actual pclk freq in Hz. + * mvidWarEnabled + * Specifies whether MVID WAR is enabled. + * MvidWarParams + * Is valid if mvidWarEnabled is true. + * bEnableTwoHeadOneOr + * Whether two head one OR is enabled. If this is set then RM will + * replicate SF settings of Master head on Slave head. Head index + * passed should be of Master Head. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC: when this command has already been called + * + */ +#define NV0073_CTRL_CMD_DP_CONFIG_STREAM (0x731362U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS_MESSAGE_ID (0x62U) + +typedef struct NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvU32 sorIndex; + NvU32 dpLink; + + NvBool bEnableOverride; + NvBool bMST; + NvU32 singleHeadMultistreamMode; + NvU32 hBlankSym; + NvU32 vBlankSym; + NvU32 colorFormat; + NvBool bEnableTwoHeadOneOr; + + struct { + NvU32 slotStart; + NvU32 slotEnd; + NvU32 PBN; + NvU32 Timeslice; + NvBool sendACT; // deprecated -Use NV0073_CTRL_CMD_DP_SEND_ACT + NvU32 singleHeadMSTPipeline; + NvBool bEnableAudioOverRightPanel; + } MST; + + struct { + NvBool bEnhancedFraming; + NvU32 tuSize; + NvU32 waterMark; + NvU32 actualPclkHz; // deprecated -Use MvidWarParams + NvU32 linkClkFreqHz; // deprecated -Use MvidWarParams + NvBool bEnableAudioOverRightPanel; + struct { + NvU32 activeCnt; + NvU32 activeFrac; + NvU32 activePolarity; + NvBool mvidWarEnabled; + struct { + NvU32 actualPclkHz; + NvU32 linkClkFreqHz; + } MvidWarParams; + } Legacy; + } SST; +} NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_SET_RATE_GOV + * + * This command enables rate governing for a MST. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * Head + * Specifies the head index for the stream. + * sorIndex + * Specifies the SOR index for the stream. + * flags + * Specifies Rate Governing, trigger type and wait on trigger and operation type. + * + * _FLAGS_OPERATION: whether this control call should program or check for status of previous operation. + * + * _FLAGS_STATUS: Out only. Caller should check the status for _FLAGS_OPERATION_CHECK_STATUS through + * this bit. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC: when this command has already been called + * + */ +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV (0x731363U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_RATE_GOV_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_PARAMS_MESSAGE_ID (0x63U) + +typedef struct NV0073_CTRL_CMD_DP_SET_RATE_GOV_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvU32 sorIndex; + NvU32 flags; +} NV0073_CTRL_CMD_DP_SET_RATE_GOV_PARAMS; + +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_ENABLE_RG 0:0 +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_ENABLE_RG_OFF (0x00000000U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_ENABLE_RG_ON (0x00000001U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_TRIGGER_MODE 1:1 +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_TRIGGER_MODE_LOADV (0x00000000U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_TRIGGER_MODE_IMMEDIATE (0x00000001U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_WAIT_TRIGGER 2:2 +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_WAIT_TRIGGER_OFF (0x00000000U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_WAIT_TRIGGER_ON (0x00000001U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_OPERATION 3:3 +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_OPERATION_PROGRAM (0x00000000U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_OPERATION_CHECK_STATUS (0x00000001U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_STATUS 31:31 +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_STATUS_FAIL (0x00000000U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_STATUS_PASS (0x00000001U) + +/* + * NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT + * + * This call is used by the displayport library. Once + * all of the platforms have ported, this call will be + * deprecated and made the default behavior. + * + * Disables automatic watermark programming + * Disables automatic DP IRQ handling (CP IRQ) + * Disables automatic retry on defers + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT (0x731365U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS_MESSAGE_ID (0x65U) + +typedef struct NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS { + NvU32 subDeviceInstance; +} NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_SET_ECF + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * sorIndex + * This parameter specifies the Index of sor for which ecf + * should be updated. + * ecf + * This parameter has the ECF bit mask. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_CMD_DP_SET_ECF (0x731366U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_ECF_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SET_ECF_PARAMS_MESSAGE_ID (0x66U) + +typedef struct NV0073_CTRL_CMD_DP_SET_ECF_PARAMS { + NvU32 subDeviceInstance; + NvU32 sorIndex; + NV_DECLARE_ALIGNED(NvU64 ecf, 8); + NvBool bForceClearEcf; + NvBool bAddStreamBack; +} NV0073_CTRL_CMD_DP_SET_ECF_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_SEND_ACT + * + * This command sends ACT. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * displayId + * Specifies the root port displayId for which the trigger has to be done. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC: when this command has already been called + * + */ +#define NV0073_CTRL_CMD_DP_SEND_ACT (0x731367U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS_MESSAGE_ID (0x67U) + +typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; +} NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS; + + + +/* + * NV0073_CTRL_CMD_DP_GET_CAPS + * + * This command returns the following info + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * sorIndex + * Specifies the SOR index. + * dpVersionsSupported + * Specified the DP versions supported by the GPU + * bIsMultistreamSupported + * Returns NV_TRUE if MST is supported by the GPU else NV_FALSE + * bIsSCEnabled + * Returns NV_TRUE if Stream cloning is supported by the GPU else NV_FALSE + * maxLinkRate + * Returns Maximum allowed orclk for DP mode of SOR + * 1 signifies 5.40(HBR2), 2 signifies 2.70(HBR), 3 signifies 1.62(RBR) + * bHasIncreasedWatermarkLimits + * Returns NV_TRUE if the GPU uses higher watermark limits, else NV_FALSE + * bIsPC2Disabled + * Returns NV_TRUE if VBIOS flag to disable PostCursor2 is set, else NV_FALSE + * bFECSupported + * Returns NV_TRUE if GPU supports FEC, else NV_FALSE + * bIsTrainPhyRepeater + * Returns NV_TRUE if LTTPR Link Training feature is set + * bOverrideLinkBw + * Returns NV_TRUE if DFP limits defined in DCB have to be honored, else NV_FALSE + * + * DSC caps - + * bDscSupported + * If GPU supports DSC or not + * + * encoderColorFormatMask + * Mask of all color formats for which DSC + * encoding is supported by GPU + * + * lineBufferSizeKB + * Size of line buffer. + * + * rateBufferSizeKB + * Size of rate buffer per slice. + * + * bitsPerPixelPrecision + * Bits per pixel precision for DSC e.g. 1/16, 1/8, 1/4, 1/2, 1bpp + * + * maxNumHztSlices + * Maximum number of horizontal slices supported by DSC encoder + * + * lineBufferBitDepth + * Bit depth used by the GPU to store the reconstructed pixels within + * the line buffer + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ + +#define NV0073_CTRL_CMD_DP_GET_CAPS (0x731369U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID (0x69U) + +typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS { + NvU32 subDeviceInstance; + NvU32 sorIndex; + NvU32 maxLinkRate; + NvU32 dpVersionsSupported; + NvBool bIsMultistreamSupported; + NvBool bIsSCEnabled; + NvBool bHasIncreasedWatermarkLimits; + NvBool bIsPC2Disabled; + NvBool isSingleHeadMSTSupported; + NvBool bFECSupported; + NvBool bIsTrainPhyRepeater; + NvBool bOverrideLinkBw; + + struct { + NvBool bDscSupported; + NvU32 encoderColorFormatMask; + NvU32 lineBufferSizeKB; + NvU32 rateBufferSizeKB; + NvU32 bitsPerPixelPrecision; + NvU32 maxNumHztSlices; + NvU32 lineBufferBitDepth; + } DSC; +} NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS; + +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2 0:0 +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2_NO (0x00000000U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2_YES (0x00000001U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4 1:1 +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_NO (0x00000000U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_YES (0x00000001U) + + + +#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE 2:0 +#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_NONE (0x00000000U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_1_62 (0x00000001U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_2_70 (0x00000002U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_5_40 (0x00000003U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_8_10 (0x00000004U) + +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_RGB (0x00000001U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_444 (0x00000002U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_422 (0x00000004U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_420 (0x00000008U) + +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_16 (0x00000001U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_8 (0x00000002U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_4 (0x00000003U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_2 (0x00000004U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1 (0x00000005U) + +#define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES (0x73136aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_MSA_PROPERTIES_SYNC_POLARITY_LOW (0U) +#define NV0073_CTRL_CMD_DP_MSA_PROPERTIES_SYNC_POLARITY_HIGH (1U) + +typedef struct NV0073_CTRL_DP_MSA_PROPERTIES_MASK { + NvU8 miscMask[2]; + NvBool bRasterTotalHorizontal; + NvBool bRasterTotalVertical; + NvBool bActiveStartHorizontal; + NvBool bActiveStartVertical; + NvBool bSurfaceTotalHorizontal; + NvBool bSurfaceTotalVertical; + NvBool bSyncWidthHorizontal; + NvBool bSyncPolarityHorizontal; + NvBool bSyncHeightVertical; + NvBool bSyncPolarityVertical; + NvBool bReservedEnable[3]; +} NV0073_CTRL_DP_MSA_PROPERTIES_MASK; + +typedef struct NV0073_CTRL_DP_MSA_PROPERTIES_VALUES { + NvU8 misc[2]; + NvU16 rasterTotalHorizontal; + NvU16 rasterTotalVertical; + NvU16 activeStartHorizontal; + NvU16 activeStartVertical; + NvU16 surfaceTotalHorizontal; + NvU16 surfaceTotalVertical; + NvU16 syncWidthHorizontal; + NvU16 syncPolarityHorizontal; + NvU16 syncHeightVertical; + NvU16 syncPolarityVertical; + NvU8 reserved[3]; +} NV0073_CTRL_DP_MSA_PROPERTIES_VALUES; + +#define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS_MESSAGE_ID (0x6AU) + +typedef struct NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bEnableMSA; + NvBool bStereoPhaseInverse; + NvBool bCacheMsaOverrideForNextModeset; + NV0073_CTRL_DP_MSA_PROPERTIES_MASK featureMask; + NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureValues; + NV_DECLARE_ALIGNED(struct NV0073_CTRL_DP_MSA_PROPERTIES_VALUES *pFeatureDebugValues, 8); +} NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT + * + * This command can be used to invoke a fake interrupt for the operation of DP1.2 branch device + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * interruptType + * This parameter specifies the type of fake interrupt to be invoked. Possible values are: + * 0 => IRQ + * 1 => HPDPlug + * 2 => HPDUnPlug + * displayId + * should be for DP only + * + */ + +#define NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT (0x73136bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_PARAMS_MESSAGE_ID (0x6BU) + +typedef struct NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 interruptType; +} NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_PARAMS; + +#define NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_IRQ (0x00000000U) +#define NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_PLUG (0x00000001U) +#define NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_UNPLUG (0x00000002U) + +/* + * NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG + * + * This command sets the MS displayId lit up by driver for further use of VBIOS + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * should be for DP only + * activeDevAddr + * Active MS panel address + * sorIndex + * SOR Index + * dpLink + * DP Sub Link Index + * hopCount + * Maximum hopcounts in MS address + * dpMsDevAddrState + * DP Multistream Device Address State. The values can be + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_TIMEOUT + * + */ +#define NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG (0x73136cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG_PARAMS_MESSAGE_ID (0x6CU) + +typedef struct NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 activeDevAddr; + NvU32 sorIndex; + NvU32 dpLink; + NvU32 hopCount; + NvU32 dpMsDevAddrState; +} NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG_PARAMS; + + + +/* +* NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT +* +* This command configures a new bit, NV_PDISP_SF_DP_LINKCTL_TRIGGER_SELECT +* to indicate which pipeline will handle the +* time slots allocation in single head MST mode +* +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. This parameter must specify a value between zero and the +* total number of subdevices within the parent device. This parameter +* should be set to zero for default behavior +* Head +* Specifies the head index for the stream +* sorIndex +* Specifies the SOR index for the stream +* streamIndex +* Stream Identifier +* +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_ARGUMENT +* NV_ERR_GENERIC: when this command has already been called +* +*/ +#define NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT (0x73136fU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT_PARAMS_MESSAGE_ID (0x6FU) + +typedef struct NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvU32 sorIndex; + NvU32 singleHeadMSTPipeline; +} NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT_PARAMS; + +/* +* NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM +* +* This call is used by the displayport library.& clients of RM +* Its main function is to configure single Head Multi stream mode + * this call configures internal RM datastructures to support required mode. +* +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. This parameter must specify a value between zero and the +* total number of subdevices within the parent device. This parameter +* should be set to zero for default behavior. +* +* displayIDs +* This parameter specifies array of DP displayIds to be configured which are driven out from a single head. +* +* numStreams +* This parameter specifies number of streams driven from a single head +* ex: for 2SST & 2MST its value is 2. +* +* mode +* This parameter specifies single head multi stream mode to be configured. +* +* bSetConfigure +* This parameter configures single head multistream mode +* if TRUE it sets SST or MST based on 'mode' parameter and updates internal driver data structures with the given information. +* if FALSE clears the configuration of single head multi stream mode. +* +* vbiosPrimaryDispIdIndex +* This parameter specifies vbios master displayID index in displayIDs input array. +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_ARGUMENT +* NV_ERR_NOT_SUPPORTED +* +*/ +#define NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM (0x73136eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SINGLE_HEAD_MAX_STREAMS (0x00000002U) +#define NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM_PARAMS_MESSAGE_ID (0x6EU) + +typedef struct NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayIDs[NV0073_CTRL_CMD_DP_SINGLE_HEAD_MAX_STREAMS]; + NvU32 numStreams; + NvU32 mode; + NvBool bSetConfig; + NvU8 vbiosPrimaryDispIdIndex; +} NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM_PARAMS; + +#define NV0073_CTRL_CMD_DP_SINGLE_HEAD_MULTI_STREAM_NONE (0x00000000U) +#define NV0073_CTRL_CMD_DP_SINGLE_HEAD_MULTI_STREAM_MODE_SST (0x00000001U) +#define NV0073_CTRL_CMD_DP_SINGLE_HEAD_MULTI_STREAM_MODE_MST (0x00000002U) + +/* +* NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL +* +* This command configures a new bit, NV_PDISP_SF_DP_LINKCTL_TRIGGER_ALL +* to indicate which if all the pipelines to take affect on ACT (sorFlushUpdates) +* in single head MST mode +* +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. This parameter must specify a value between zero and the +* total number of subdevices within the parent device. This parameter +* should be set to zero for default behavior +* Head +* Specifies the head index for the stream +* sorIndex +* Specifies the SOR index for the stream +* streamIndex +* Stream Identifier +* +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_ARGUMENT +* NV_ERR_GENERIC: when this command has already been called +* +*/ +#define NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL (0x731370U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL_PARAMS_MESSAGE_ID (0x70U) + +typedef struct NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvBool enable; +} NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL_PARAMS; + + + +/* +* NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA +* +* This command collects the DP AUX log from the RM aux buffer and +* sends it to the application. +* +* dpAuxBufferReadSize +* Specifies the number of logs to be read from the +* AUX buffer in RM +* dpNumMessagesRead +* Specifies the number of logs read from the AUX buffer +* dpAuxBuffer +* The local buffer to copy the specified number of logs +* from RM to user application +* +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_ARGUMENT +* NV_ERR_GENERIC: when this command has already been called +* +* +*DPAUXPACKET - This structure holds the log information +* auxPacket - carries the hex dump of the message transaction +* auxEvents - Contains the information as in what request and reply type where +* auxRequestTimeStamp - Request timestamp +* auxMessageReqSize - Request Message size +* auxMessageReplySize - Reply message size(how much information was actually send by receiver) +* auxOutPort - DP port number +* auxPortAddress - Address to which data was requested to be read or written +* auxReplyTimeStamp - Reply timestamp +* auxCount - Serial number to keep track of transactions +*/ + +/*Maximum dp messages size is 16 as per the protocol*/ +#define DP_MAX_MSG_SIZE 16U +#define MAX_LOGS_PER_POLL 50U + +/* Various kinds of DP Aux transactions */ +#define NV_DP_AUXLOGGER_REQUEST_TYPE 3:0 +#define NV_DP_AUXLOGGER_REQUEST_TYPE_NULL 0x00000000U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_I2CWR 0x00000001U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_I2CREQWSTAT 0x00000002U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_MOTWR 0x00000003U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_MOTREQWSTAT 0x00000004U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_AUXWR 0x00000005U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_I2CRD 0x00000006U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_MOTRD 0x00000007U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_AUXRD 0x00000008U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_UNKNOWN 0x00000009U + +#define NV_DP_AUXLOGGER_REPLY_TYPE 7:4 +#define NV_DP_AUXLOGGER_REPLY_TYPE_NULL 0x00000000U +#define NV_DP_AUXLOGGER_REPLY_TYPE_SB_ACK 0x00000001U +#define NV_DP_AUXLOGGER_REPLY_TYPE_RETRY 0x00000002U +#define NV_DP_AUXLOGGER_REPLY_TYPE_TIMEOUT 0x00000003U +#define NV_DP_AUXLOGGER_REPLY_TYPE_DEFER 0x00000004U +#define NV_DP_AUXLOGGER_REPLY_TYPE_DEFER_TO 0x00000005U +#define NV_DP_AUXLOGGER_REPLY_TYPE_ACK 0x00000006U +#define NV_DP_AUXLOGGER_REPLY_TYPE_ERROR 0x00000007U +#define NV_DP_AUXLOGGER_REPLY_TYPE_UNKNOWN 0x00000008U + +#define NV_DP_AUXLOGGER_EVENT_TYPE 9:8 +#define NV_DP_AUXLOGGER_EVENT_TYPE_AUX 0x00000000U +#define NV_DP_AUXLOGGER_EVENT_TYPE_HOT_PLUG 0x00000001U +#define NV_DP_AUXLOGGER_EVENT_TYPE_HOT_UNPLUG 0x00000002U +#define NV_DP_AUXLOGGER_EVENT_TYPE_IRQ 0x00000003U + +#define NV_DP_AUXLOGGER_AUXCTL_CMD 15:12 +#define NV_DP_AUXLOGGER_AUXCTL_CMD_INIT 0x00000000U +#define NV_DP_AUXLOGGER_AUXCTL_CMD_I2CWR 0x00000000U +#define NV_DP_AUXLOGGER_AUXCTL_CMD_I2CRD 0x00000001U +#define NV_DP_AUXLOGGER_AUXCTL_CMD_I2CREQWSTAT 0x00000002U +#define NV_DP_AUXLOGGER_AUXCTL_CMD_MOTWR 0x00000004U +#define NV_DP_AUXLOGGER_AUXCTL_CMD_MOTRD 0x00000005U +#define NV_DP_AUXLOGGER_AUXCTL_CMD_MOTREQWSTAT 0x00000006U +#define NV_DP_AUXLOGGER_AUXCTL_CMD_AUXWR 0x00000008U +#define NV_DP_AUXLOGGER_AUXCTL_CMD_AUXRD 0x00000009U + + +typedef struct DPAUXPACKET { + NvU32 auxEvents; + NvU32 auxRequestTimeStamp; + NvU32 auxMessageReqSize; + NvU32 auxMessageReplySize; + NvU32 auxOutPort; + NvU32 auxPortAddress; + NvU32 auxReplyTimeStamp; + NvU32 auxCount; + NvU8 auxPacket[DP_MAX_MSG_SIZE]; +} DPAUXPACKET; +typedef struct DPAUXPACKET *PDPAUXPACKET; + +#define NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA (0x731373U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA_PARAMS_MESSAGE_ID (0x73U) + +typedef struct NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA_PARAMS { + //In + NvU32 subDeviceInstance; + NvU32 dpAuxBufferReadSize; + + //Out + NvU32 dpNumMessagesRead; + DPAUXPACKET dpAuxBuffer[MAX_LOGS_PER_POLL]; +} NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA_PARAMS; + + + + +/* NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES + * + * This setup link rate table for target display to enable indexed link rate + * and export valid link rates back to client. Client may pass empty table to + * reset previous setting. + * + * subDeviceInstance + * client will give a subdevice to get right pGpu/pDisp for it + * displayId + * DisplayId of the display for which the client targets + * linkRateTbl + * Link rates in 200KHz as native granularity from eDP 1.4 + * linkBwTbl + * Link rates in 270MHz and valid for client to apply to + * linkBwCount + * Total valid link rates + * + * Possible status values returned include: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES (0x731377U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES 8U + +#define NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS_MESSAGE_ID (0x77U) + +typedef struct NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS { + // In + NvU32 subDeviceInstance; + NvU32 displayId; + NvU16 linkRateTbl[NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES]; + + // Out + NvU8 linkBwTbl[NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES]; + NvU8 linkBwCount; +} NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS; + + +/* + * NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES + * + * This command is used to not depend on supervisor interrupts for setting the + * stereo msa params. We will not cache the values and can toggle stereo using + * this ctrl call on demand. Note that this control call will only change stereo + * settings and will leave other settings as is. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * should be for DP only + * bEnableMSA + * To enable or disable MSA + * bStereoPhaseInverse + * To enable or disable Stereo Phase Inverse value + * featureMask + * Enable/Disable mask of individual MSA property. + * featureValues + * MSA property value to write + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_TIMEOUT + * + */ +#define NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES (0x731378U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES_PARAMS_MESSAGE_ID (0x78U) + +typedef struct NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bEnableMSA; + NvBool bStereoPhaseInverse; + NV0073_CTRL_DP_MSA_PROPERTIES_MASK featureMask; + NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureValues; +} NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES_PARAMS; + + + +/* + * NV0073_CTRL_CMD_DP_CONFIGURE_FEC + * + * This command is used to enable/disable FEC on DP Mainlink. + * FEC is a prerequisite to DSC. This should be called only + * after LT completes (including PostLT LQA) while enabling. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * displayId + * Can only be 1 and must be DP. + * + * bEnableFec + * To enable or disable FEC + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV0073_CTRL_CMD_DP_CONFIGURE_FEC (0x73137aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIGURE_FEC_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_CONFIGURE_FEC_PARAMS_MESSAGE_ID (0x7AU) + +typedef struct NV0073_CTRL_CMD_DP_CONFIGURE_FEC_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bEnableFec; +} NV0073_CTRL_CMD_DP_CONFIGURE_FEC_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior + * cmd + * This parameter is an input to this command. + * Here are the current defined fields: + * NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_CMD_POWER + * Set to specify what operation to run. + * NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_CMD_POWER_UP + * Request to power up pad. + * NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_CMD_POWER_DOWN + * Request to power down the pad. + * linkBw + * This parameter is used to pass in the link bandwidth required to run the + * power up sequence. Refer enum DP_LINK_BANDWIDTH for valid values. + * laneCount + * This parameter is used to pass the lanecount. + * sorIndex + * This parameter is used to pass the SOR index. + * sublinkIndex + * This parameter is used to pass the sublink index. Please refer + * enum DFPLINKINDEX for valid values + * priPadLinkIndex + * This parameter is used to pass the padlink index for primary link. + * Please refer enum DFPPADLINK for valid index values for Link A~F. + * secPadLinkIndex + * This parameter is used to pass the padlink index for secondary link. + * For Single SST pass in NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PADLINK_INDEX_INVALID + * bEnableSpread + * This parameter is boolean value used to indicate if spread is to be enabled or disabled. + */ + +#define NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD (0x73137bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PARAMS_MESSAGE_ID (0x7BU) + +typedef struct NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PARAMS { + NvU32 subDeviceInstance; + NvU32 cmd; + NvU32 linkBw; + NvU32 laneCount; + NvU32 sorIndex; + NvU32 sublinkIndex; // sublink A/B + NvU32 priPadLinkIndex; // padlink A/B/C/D/E/F + NvU32 secPadLinkIndex; // padlink A/B/C/D/E/F for secondary link in DualSST case. + NvBool bEnableSpread; +} NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PARAMS; + +#define NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_CMD_POWER 0:0 +#define NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_CMD_POWER_UP (0x00000000U) +#define NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_CMD_POWER_DOWN (0x00000001U) + +#define NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PADLINK_INDEX_INVALID (0x000000FFU) + +/* + * NV0073_CTRL_CMD_DP_AUXCH_CTRL + * + * This command can be used to perform the I2C Bulk transfer over + * DP Aux channel. This is the display port specific implementation + * for sending bulk data over the DpAux channel, by splitting up the + * data into pieces and retrying for pieces that aren't ACK'd. + * + * subDeviceInstance [IN] + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId [IN] + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must a dfp display. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * addr [IN] + * This parameter is an input to this command. The addr parameter follows + * Section 2.4 in DisplayPort spec and the client should refer to the valid + * address in DisplayPort spec. Only the first 20 bits are valid. + * bWrite [IN] + * This parameter specifies whether the command is a I2C write (NV_TRUE) or + * a I2C read (NV_FALSE). + * data [IN/OUT] + * In the case of a read transaction, this parameter returns the data from + * transaction request. In the case of a write transaction, the client + * should write to this buffer for the data to send. + * size [IN/OUT] + * Specifies how many data bytes to read/write depending on the + * transaction type. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_DP_AUXCH_I2C_TRANSFER_CTRL (0x73137cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_MAX_DATA_SIZE 256U + +#define NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_CTRL_PARAMS_MESSAGE_ID (0x7CU) + +typedef struct NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 addr; + NvBool bWrite; + NvU8 data[NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_MAX_DATA_SIZE]; + NvU32 size; +} NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_CTRL_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_ENABLE_VRR + * + * The command is used to enable VRR. + * + * subDeviceInstance [IN] + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior + * displayId [IN] + * This parameter is an input to this command, specifies the ID of the display + * for client targeted to. + * The display ID must a DP display. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * cmd [IN] + * This parameter is an input to this command. + * + * _STAGE: specifies the stage id to execute in the VRR enablement sequence. + * _MONITOR_ENABLE_BEGIN: Send command to the monitor to start monitor + * enablement procedure. + * _MONITOR_ENABLE_CHALLENGE: Send challenge to the monitor + * _MONITOR_ENABLE_CHECK: Read digest from the monitor, and verify + * if the result is valid. + * _DRIVER_ENABLE_BEGIN: Send command to the monitor to start driver + * enablement procedure. + * _DRIVER_ENABLE_CHALLENGE: Read challenge from the monitor and write back + * corresponding digest. + * _DRIVER_ENABLE_CHECK: Check if monitor enablement worked. + * _RESET_MONITOR: Set the FW state m/c to a known state. + * _INIT_PUBLIC_INFO: Send command to the monitor to prepare public info. + * _GET_PUBLIC_INFO: Read public info from the monitor. + * _STATUS_CHECK: Check if monitor is ready for next command. + * result [OUT] + * This is an output parameter to reflect the result of the operation. + */ +#define NV0073_CTRL_CMD_DP_ENABLE_VRR (0x73137dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS_MESSAGE_ID (0x7DU) + +typedef struct NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 cmd; + NvU32 result; +} NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS; + +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE 3:0 +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_MONITOR_ENABLE_BEGIN (0x00000000U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_MONITOR_ENABLE_CHALLENGE (0x00000001U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_MONITOR_ENABLE_CHECK (0x00000002U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_DRIVER_ENABLE_BEGIN (0x00000003U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_DRIVER_ENABLE_CHALLENGE (0x00000004U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_DRIVER_ENABLE_CHECK (0x00000005U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_RESET_MONITOR (0x00000006U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_INIT_PUBLIC_INFO (0x00000007U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_GET_PUBLIC_INFO (0x00000008U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_STATUS_CHECK (0x00000009U) + +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_OK (0x00000000U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_PENDING (0x80000001U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_READ_ERROR (0x80000002U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_WRITE_ERROR (0x80000003U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_DEVICE_ERROR (0x80000004U) + +/* + * NV0073_CTRL_CMD_DP_GET_GENERIC_INFOFRAME + * + * This command is used to capture the display output packets for DP protocol. + * Common supported packets are Dynamic Range and mastering infoframe SDP for HDR, + * VSC SDP for colorimetry and pixel encoding info. + * + * displayID (in) + * This parameter specifies the displayID for the display resource to configure. + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the NV04_DISPLAY_COMMON + * parent device to which the operation should be directed. + * infoframeIndex (in) + * HW provides support to program 2 generic infoframes per frame for DP. + * This parameter indicates which infoframe packet is to be captured. + * Possible flags are as follows: + * NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_CAPTURE_MODE + * This flag indicates the INFOFRAME that needs to be read. + * Set to _INFOFRAME0 if RM should read GENERIC_INFOFRAME + * Set to _INFOFRAME1 if RM should read GENERIC_INFOFRAME1 + * packet (out) + * pPacket points to the memory for reading the infoframe packet. + * bTransmitControl (out) + * This gives the transmit mode of infoframes. + * If set, means infoframe will be sent as soon as possible and then on + * every frame during vblank. + * If cleared, means the infoframe will be sent once as soon as possible. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_DP_GET_GENERIC_INFOFRAME (0x73137eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_GENERIC_INFOFRAME_MAX_PACKET_SIZE 36U + +#define NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_PARAMS_MESSAGE_ID (0x7EU) + +typedef struct NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 infoframeIndex; + NvU8 packet[NV0073_CTRL_DP_GENERIC_INFOFRAME_MAX_PACKET_SIZE]; + NvBool bTransmitControl; +} NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_PARAMS; + + +#define NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_CAPTURE_MODE 0:0 +#define NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_CAPTURE_MODE_INFOFRAME0 (0x0000000U) +#define NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_CAPTURE_MODE_INFOFRAME1 (0x0000001U) + + +/* + * NV0073_CTRL_CMD_DP_GET_MSA_ATTRIBUTES + * + * This command is used to capture the various data attributes sent in the MSA for DP protocol. + * Refer table 2-94 'MSA Data Fields' in DP1.4a spec document for MSA data field description. + * + * displayID (in) + * This parameter specifies the displayID for the display resource to configure. + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the NV04_DISPLAY_COMMON + * parent device to which the operation should be directed. + * mvid, nvid (out) + * Video timestamp used by DP sink for regenerating pixel clock. + * misc0, misc1 (out) + * Miscellaneous MSA attributes. + * hTotal, vTotal (out) + * Htotal measured in pixel count and vtotal measured in line count. + * hActiveStart, vActiveStart (out) + * Active start measured from start of leading edge of the sync pulse. + * hActiveWidth, vActiveWidth (out) + * Active video width and height. + * hSyncWidth, vSyncWidth (out) + * Width of sync pulse. + * hSyncPolarity, vSyncPolarity (out) + * Polarity of sync pulse. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_DP_GET_MSA_ATTRIBUTES (0x73137fU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_MSA_ATTRIBUTES_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_MSA_MAX_DATA_SIZE 7U + +#define NV0073_CTRL_DP_GET_MSA_ATTRIBUTES_PARAMS_MESSAGE_ID (0x7FU) + +typedef struct NV0073_CTRL_DP_GET_MSA_ATTRIBUTES_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 mvid; + NvU32 nvid; + NvU8 misc0; + NvU8 misc1; + NvU16 hTotal; + NvU16 vTotal; + NvU16 hActiveStart; + NvU16 vActiveStart; + NvU16 hActiveWidth; + NvU16 vActiveWidth; + NvU16 hSyncWidth; + NvU16 vSyncWidth; + NvBool hSyncPolarity; + NvBool vSyncPolarity; +} NV0073_CTRL_DP_GET_MSA_ATTRIBUTES_PARAMS; + +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_MVID 23:0 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_NVID 23:0 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_MISC0 7:0 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_MISC1 15:8 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_HTOTAL 15:0 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_VTOTAL 31:16 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_HACTIVE_START 15:0 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_VACTIVE_START 31:16 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_HACTIVE_WIDTH 15:0 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_VACTIVE_WIDTH 31:16 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_HSYNC_WIDTH 14:0 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_HSYNC_POLARITY 15:15 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_VSYNC_WIDTH 30:16 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_VSYNC_POLARITY 31:31 + +/* + * NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL + * + * This command is used to query OD capability and status as well as + * control OD functionality of eDP LCD panels. + * + * subDeviceInstance [in] + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId [in] + * This parameter specifies the ID of the DP display which owns + * the Main Link to be adjusted. The display ID must a DP display + * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * cmd [in] + * This parameter is an input to this command. The cmd parameter tells + * whether we have to get the value of a specific field or set the + * value in case of a writeable field. + * control [in] + * This parameter is input by the user. It is used by the user to decide the control + * value to be written to change the Sink OD mode. The command to write is + * the NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET command. + * bOdCapable [out] + * This parameter reflects the OD capability of the Sink which can be + * fetched by using the NV0073_CTRL_CMD_DP_AUXCH_OD_CAPABLE_QUERY command. + * bOdControlCapable [out] + * This parameter reflects the OD control capability of the Sink which can be + * fetched by using the NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_CAPABLE_QUERY command. + * bOdStatus [out] + * This parameter reflects the Sink OD status which can be + * fetched by using the NV0073_CTRL_CMD_DP_AUXCH_OD_STATUS_QUERY command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL (0x731380U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS_MESSAGE_ID (0x80U) + +typedef struct NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU8 control; + NvU8 cmd; + NvBool bOdCapable; + NvBool bOdControlCapable; + NvBool bOdStatus; +} NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS; + +/* valid commands */ +#define NV0073_CTRL_CMD_DP_AUXCHQUERY_OD_CAPABLE 0x00000000 +#define NV0073_CTRL_CMD_DP_AUXCHQUERY_OD_CTL_CAPABLE 0x00000001 +#define NV0073_CTRL_CMD_DP_AUXCHQUERY_OD_STATUS 0x00000002 +#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET 0x00000003 + +/* valid state values */ +#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET_AUTONOMOUS 0x00000000 +#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET_DISABLE_OD 0x00000002 +#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET_ENABLE_OD 0x00000003 + +/* + * NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES + * + * This command returns the following info + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * should be for DP only + * bEnableMSA + * To enable or disable MSA + * bStereoPhaseInverse + * To enable or disable Stereo Phase Inverse value + * bCacheMsaOverrideForNextModeset + * Cache the values and don't apply them until next modeset + * featureMask + * Enable/Disable mask of individual MSA property + * featureValues + * MSA property value to write + * bDebugValues + * To inform whether actual MSA values need to be returned + * pFeatureDebugValues + * It will actual MSA property value being written on HW. + * If its NULL then no error but return nothing + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_TIMEOUT + * + */ +#define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2 (0x731381U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bEnableMSA; + NvBool bStereoPhaseInverse; + NvBool bCacheMsaOverrideForNextModeset; + NV0073_CTRL_DP_MSA_PROPERTIES_MASK featureMask; + NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureValues; + NvBool bDebugValues; + NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureDebugValues; +} NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS; +/* _ctrl0073dp_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073dpu.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073dpu.h new file mode 100644 index 0000000..1ac3e6f --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073dpu.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073dpu.finn +// + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h new file mode 100644 index 0000000..a2423a8 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073event.finn +// + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h new file mode 100644 index 0000000..2b4965d --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073internal.finn +// + +#include "ctrl/ctrl0073/ctrl0073base.h" +#include "ctrl/ctrl0073/ctrl0073system.h" + +#define NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE (0x730401U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS_MESSAGE_ID" */ + + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS { + NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS params; +} NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS; + + +/* ctrl0073internal_h */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h new file mode 100644 index 0000000..7ac6f6e --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073psr.finn +// + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h new file mode 100644 index 0000000..74ace22 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h @@ -0,0 +1,1909 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073specific.finn +// + +#include "ctrl/ctrl0073/ctrl0073base.h" + +#include "ctrl/ctrlxxxx.h" +/* NV04_DISPLAY_COMMON display-specific control commands and parameters */ + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_TYPE + * + * This command can be used to determine the associated display type for + * the specified displayId. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the display + * type is to be returned. Only one display may be indicated in this + * parameter. + * displayType + * This parameter returns the display type associated with the specified + * displayId parameter. Valid displayType values are: + * NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_CRT + * NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_DFP + * NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_TV + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_TYPE (0x730240U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_TYPE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_GET_TYPE_PARAMS_MESSAGE_ID (0x40U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_TYPE_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 displayType; +} NV0073_CTRL_SPECIFIC_GET_TYPE_PARAMS; + +/* valid display types */ +#define NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_UNKNOWN (0x00000000U) +#define NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_CRT (0x00000001U) +#define NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_DFP (0x00000002U) +#define NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_TV (0x00000003U) + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_EDID_V2 + * + * This command can be used to request the EDID for the specified displayId. + * + * [in] subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the total + * number of subdevices within the parent device. This parameter should + * be set to zero for default behavior. + * [in] displayId + * This parameter specifies the display to read the EDID. The display ID + * must specify a display with a positive connect state as determined + * with the NV0073_CTRL_CMD_SYSTEM_GET_CONNECT_STATE command. Only one + * display may be indicated in this parameter. If a more than one + * display Id is used, the RM will return NV_ERR_INVALID_ARGUMENT. + * [out] bufferSize + * This parameter returns the number of bytes copied into edidBuffer after + * performing the requested EDID operations. + * [out] edidBuffer + * The array of EDIDs that RM will fill after the requested operations. If + * the size of the array is not large enough to hold the number of bytes to + * be copied, NV_ERR_INVALID_ARGUMENT will be returned. + * [in] flags + * This parameter defines the specific operations that will be performed + * in reading the EDID. + * Here are the current defined fields: + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_COPY_CACHE + * A client uses this field to indicate whether to return the cached + * copy of the EDID or to use DDC to read the EDID from the display. + * Possible values are: + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_COPY_CACHE_NO + * The RM will use DDC to grab the EDID. + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_COPY_CACHE_YES + * The RM will copy the last EDID found into the clients + * buffer. No DDC will be performed. + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_READ_MODE + * A client uses this field to indicate whether to read from + * the HW and return the EDID w/o any patching + * Possible values are: + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_READ_MODE_COOKED + * Use the _COPY_CACHE policy + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_READ_MODE_RAW + * Perform the read and return an unadulterated EDID. + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE + * A client uses this field to indicate whether to read EDID + * from SBIOS using ACPI sub function for display dynamic switching + * feature. This flag should only be set on internal display with + * dynamic switching feature enabled. + * Possible values are: + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE_ACPI + * RM reads the EDID from SBIOS and returns the raw EDID provided + * by SBIOS. + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE_DEFAULT + * EDID is read based on rest of the 'flags' that are passed to + * this function. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_EDID_V2 (0x730245U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_GET_EDID_MAX_EDID_BYTES 2048U + +#define NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS_MESSAGE_ID (0x45U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 bufferSize; + NvU32 flags; + NvU8 edidBuffer[NV0073_CTRL_SPECIFIC_GET_EDID_MAX_EDID_BYTES]; +} NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS; + +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_COPY_CACHE 0:0 +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_COPY_CACHE_NO 0x00000000U +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_COPY_CACHE_YES 0x00000001U + +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_READ_MODE 1:1 +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_READ_MODE_COOKED 0x00000000U +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_READ_MODE_RAW 0x00000001U + +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE 3:2 +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE_DEFAULT 0x00000000U +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE_ACPI 0x00000001U + +/* + * NV0073_CTRL_CMD_SPECIFIC_SET_EDID_V2 + * + * This command can be used to set or remove a complete EDID for the + * specified displayId. Once the EDID is set, any requests + * to read the EDID or use DDC detection will always use a cached copy of + * the EDID. That is, the EDID becomes static until disabled by calling + * this same function with edidBuffer. Note, that DDC based + * detection will always pass for any displayId that has set an EDID. Also, + * this path will not store any value across reboots. If an EDID needs to + * remain set after a reboot, RM clients must call this function again. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the total + * number of subdevices within the parent device. This parameter should + * be set to zero for default behavior. + * displayId + * This parameter specifies the display to store or the EDID. Only one + * display may be indicated in this parameter. If more than one displayId + * is used, the RM will return NV_ERR_INVALID_ARGUMENT. + * If the displayId does not use DDC and hence would not have an EDID, + * then the RM could also return NV_ERR_INVALID_ARGUMENT. + * bufferSize + * This parameter specifies the size of the EDID buffer pointed to by + * pEdidBuffer. If the EDID write contains more bytes than bufferSize, + * the RM will extend the bufferSize of the EDID inside the RM to match. + * Note a bufferSize of 0 would mean no bytes will be copied, but set the + * current cached EDID as static. + * edidBuffer + * This parameter specifies the EDID buffer that the RM will copy into + * the RM buffer. If the EDID buffer is empty, the RM will remove any + * previous set EDID and allow further detection and EDID reads to use DDC. + * The RM will not check to see if the EDID is valid here or not. + * The client should validate the EDID if needed before calling this function. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + */ + +#define NV0073_CTRL_CMD_SPECIFIC_SET_EDID_V2 (0x730246U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_EDID_V2_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_EDID_V2_PARAMS_MESSAGE_ID (0x46U) + +typedef struct NV0073_CTRL_SPECIFIC_SET_EDID_V2_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 bufferSize; + NvU8 edidBuffer[NV0073_CTRL_SPECIFIC_GET_EDID_MAX_EDID_BYTES]; +} NV0073_CTRL_SPECIFIC_SET_EDID_V2_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE + * + * This Control Cmd is for providing the Faking device(s) support from RM. + * This command serves as the entry point for all interaction of RM with + * user mode component of the any internal [test] tool. The Faking framework + * in RM will be activated only after the usermode app sends in a proper ENABLE + * cmd first. Any attempt to issue other cmds while the faking code has not + * been enabled will result in RM err _INVALID_DATA. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the total + * number of subdevices within the parent device. This parameter should + * be set to zero for default behavior. + * cmd + * This field will carry the command to be executed by the framework. + * This includes Enabling/Disabling the test framework and faking devices + * like CRT/DVI/TV. + * data + * This field is to carry the data required for executing the cmd. + * Except for Enable and Disable, the other faking device commands will + * require the device mask of the device to be faked/removed. + * tvType + * This field specifies a specific TV type while faking a TV. + * Possible values are: + * NV0073_FAKE_DEVICE_TV_NONE + * NV0073_FAKE_DEVICE_TV_SVIDEO + * NV0073_FAKE_DEVICE_TV_COMPOSITE + * NV0073_FAKE_DEVICE_TV_COMPONENT + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_DATA + * + */ + +#define NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE (0x730243U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE_PARAMS_MESSAGE_ID" */ + +/* valid fake device TV connector types */ +#define NV0073_FAKE_DEVICE_TV_NONE (0U) +#define NV0073_FAKE_DEVICE_TV_SVIDEO (1U) +#define NV0073_FAKE_DEVICE_TV_COMPOSITE (2U) +#define NV0073_FAKE_DEVICE_TV_COMPONENT (3U) + +#define NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE_PARAMS_MESSAGE_ID (0x43U) + +typedef struct NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE_PARAMS { + NvU32 subDeviceInstance; + NvU32 cmd; + NvU32 data; + NvU32 tvType; +} NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE_PARAMS; + +/* Faking Support commands */ +/* some random value to enable/disable test code */ +#define NV0073_FAKE_DEVICE_SUPPORT_ENABLE 0x11faU +#define NV0073_FAKE_DEVICE_SUPPORT_DISABLE 0x99ceU +#define NV0073_FAKE_DEVICE_SUPPORT_ATTACH_DEVICES 0x100U +#define NV0073_FAKE_DEVICE_SUPPORT_REMOVE_DEVICES 0x101U + + + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID + * + * This command returns the I2C portID for the specified display device. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the display for which information is to be + * returned. Only one display may be indicated in this parameter. + * If more than one displayId is used a failing status of + * NV_ERR_INVALID_ARGUMENT will be returned. + * commPortId + * This parameter returns the I2C communication port ID of the + * display device indicated by the displayId parameter. + * ddcPortId + * This parameter returns the I2C DDC port ID of the display device + * indicated by the displayId parameter. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID (0x730211U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 commPortId; + NvU32 ddcPortId; +} NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS; + +#define NV0073_CTRL_SPECIFIC_I2C_PORT_NONE (0x0U) + + + + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_CONNECTOR_DATA + * + * This command can be used to get display connector data. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the display for which information is to be + * returned. Only one display may be indicated in this parameter. + * If more than one displayId is used a failing status of + * NV_ERR_INVALID_ARGUMENT will be returned. + * DDCPartners + * This parameter specifies an NV0073_DISPLAY_MASK value describing + * the set of displays that share the same DDC line as displayId. This + * parameter will always be returned even if we also return the + * NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_FLAGS_PRESENT_NO flag. + * flags + * This parameter specifies optional flags to be used while retrieving + * the connector data for a given displayId. + * Legal values for this parameter include: + * NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_FLAGS_PRESENT + * This flag describes whether the connector data is present + * inside the firmware. + * count + * This parameter returns the number of connectors associated with + * the displayId argument. This value indicates the number of +* valid entries returned in the data parameter. + * data + * This parameter returns an array of structures containing the connector + * data associated with each connector for the given displayId argument. + * The count field specifies how many entries in this array are returned. + * Each entry in the array contains the following members: + * index + * This value is the index associated with the given connector. If + * two displayIds share the same index, then they share the same + * connector. + * type + * This value defines the type of connector associated with the + * displayId argument. + * location + * This value provides a possible means to determine the relative + * location of the connector in association to other connectors. + * For desktop boards, a value of zero defines the south most + * connector (the connector closest to the bus slot into which + * the board is inserted). + * platform + * This value defines the type of system with which to associate the + * location of each connector. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + */ + +#define NV0073_CTRL_CMD_SPECIFIC_GET_CONNECTOR_DATA (0x730250U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS_MESSAGE_ID" */ + +/* maximum number of connectors */ +#define NV0073_CTRL_MAX_CONNECTORS 4U + +#define NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS_MESSAGE_ID (0x50U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 flags; + NvU32 DDCPartners; + NvU32 count; + struct { + NvU32 index; + NvU32 type; + NvU32 location; + } data[NV0073_CTRL_MAX_CONNECTORS]; + NvU32 platform; +} NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS; + +/* defines for the flags field */ +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_FLAGS_PRESENT 0:0 +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_FLAGS_PRESENT_NO 0x00000000U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_FLAGS_PRESENT_YES 0x00000001U + +/* defines for the data[].type field */ +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_VGA_15_PIN 0x00000000U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_TV_COMPOSITE 0x00000010U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_TV_SVIDEO 0x00000011U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_TV_HDTV_COMPONENT 0x00000013U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_TV_SCART 0x00000014U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_TV_COMPOSITE_SCART_OVER_EIAJ4120_BLUE 0x00000016U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_TV_HDTV_EIAJ4120 0x00000017U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_PC_POD_HDTV_YPRPB 0x00000018U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_PC_POD_SVIDEO 0x00000019U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_PC_POD_COMPOSITE 0x0000001AU +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DVI_I_TV_SVIDEO 0x00000020U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DVI_I_TV_COMPOSITE 0x00000021U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DVI_I 0x00000030U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DVI_D 0x00000031U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_ADC 0x00000032U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_LFH_DVI_I_1 0x00000038U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_LFH_DVI_I_2 0x00000039U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_SPWG 0x00000040U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_OEM 0x00000041U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DP_EXT 0x00000046U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DP_INT 0x00000047U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DP_MINI_EXT 0x00000048U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DP_SERIALIZER 0x00000049U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_HDMI_A 0x00000061U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_HDMI_C_MINI 0x00000063U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_LFH_DP_1 0x00000064U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_LFH_DP_2 0x00000065U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_VIRTUAL_WFD 0x00000070U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_USB_C 0x00000071U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DSI 0x00000072U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_STEREO_3PIN_DIN 0x00000073U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_UNKNOWN 0xFFFFFFFFU + +/* defines for the platform field */ +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_DEFAULT_ADD_IN_CARD 0x00000000U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_TWO_PLATE_ADD_IN_CARD 0x00000001U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_CONFIGURABLE 0x00000002U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_DESKTOP_FULL_DP 0x00000007U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_MOBILE_ADD_IN_CARD 0x00000008U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_MXM 0x00000009U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_MOBILE_BACK 0x00000010U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_MOBILE_BACK_LEFT 0x00000011U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_MOBILE_BACK_DOCK 0x00000018U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_CRUSH_DEFAULT 0x00000020U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_UNKNOWN 0xFFFFFFFFU + + + +/* + * NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_ENABLE + * + * This command is used to signal the resource manager that the upcoming mode + * shall be hdmi vs dvi. This is required since the resource manager + * does not read the display edid. The resource manager shall enable hdmi + * components such as turning on the audio engine for instance. This should + * be called prior to every modeset in which the displayId is capable of hdmi. + * displayId + * This parameter specifies the displayId of HDMI resource to configure. + * This comes as input to this command. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which operation should be directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * enable + * This field specifies the legal values: + * NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_TRUE + * NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_FALSE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_ENABLE (0x730273U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS_MESSAGE_ID (0x73U) + +typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS { + NvU8 subDeviceInstance; + NvU32 displayId; + NvU8 enable; +} NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS; + +#define NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_FALSE (0x00000000U) +#define NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_TRUE (0x00000001U) + +/* + * NV0073_CTRL_CMD_SPECIFIC_CTRL_HDMI + * + * This command can be used to enable HDMI communication on the associated GPU. + * This should be called prior to every modeset in which the displayId is capable of HDMI. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which operation should be directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * displayId + * This parameter specifies the displayId of HDMI resource to configure. + * This comes as input to this command. + * enable + * This field specifies the legal values: + * NV0073_CTRL_SPECIFIC_CTRL_HDMI_DISABLE + * NV0073_CTRL_SPECIFIC_CTRL_HDMI_ENABLE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_CTRL_HDMI (0x730274U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_CTRL_HDMI_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_CTRL_HDMI_PARAMS_MESSAGE_ID (0x74U) + +typedef struct NV0073_CTRL_SPECIFIC_CTRL_HDMI_PARAMS { + NvU8 subDeviceInstance; + NvU32 displayId; + NvBool bEnable; +} NV0073_CTRL_SPECIFIC_CTRL_HDMI_PARAMS; + +#define NV0073_CTRL_SPECIFIC_CTRL_HDMI_DISABLE (0x00000000U) +#define NV0073_CTRL_SPECIFIC_CTRL_HDMI_ENABLE (0x00000001U) + + + +/* + * NV0073_CTRL_SPECIFIC_ACPI_ID_MAPPING + * + * This structure defines the mapping between the ACPI ID and the corresponding + * display ID of a display device + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * acpiId + * The ACPI ID of the display device + * displayId + * The corresponding display ID + * dodIndex + * The corresponding DOD index + */ +typedef struct NV0073_CTRL_SPECIFIC_ACPI_ID_MAPPING { + NvU32 subDeviceInstance; + NvU32 acpiId; + NvU32 displayId; + NvU32 dodIndex; +} NV0073_CTRL_SPECIFIC_ACPI_ID_MAPPING; + +/* + * NV0073_CTRL_CMD_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT + * + * This call will return the Display Port Attachment value + * per displayID as defined by Nvidia that is directly + * associated with the ACPI 3.0 _DOD entry's Display Port + * Attachment field. This should help clients map the + * _DOD ACPI ID to each displayID. Note, that some systems + * do not have a standard in place for this field. On those + * systems, the RM will return NV_ERR_NOT_SUPPORTED. + * + * Note that this "Display Port" attachment field has nothing + * to do with DisplayPort/DP. It's an unfortunate name inside + * the ACPI 3.0 spec that coincides with the name of DisplayPort. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_NOT_SUPPORTED + * +*/ + +#define NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS_MESSAGE_ID (0x85U) + +typedef struct NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 dispPortAttachment; +} NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS; + + +#define NV0073_CTRL_CMD_SPECIFIC_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT (0x730285U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS_MESSAGE_ID" */ + +// defines for dispPortAttachment +#define NV0073_DISPLAY_PORT_ATTACHMENT_ANALOG (0x00000000U) +#define NV0073_DISPLAY_PORT_ATTACHMENT_LVDS (0x00000001U) +#define NV0073_DISPLAY_PORT_ATTACHMENT_DP_A (0x00000002U) +#define NV0073_DISPLAY_PORT_ATTACHMENT_DP_B (0x00000003U) +#define NV0073_DISPLAY_PORT_ATTACHMENT_DP_C (0x00000004U) +#define NV0073_DISPLAY_PORT_ATTACHMENT_DP_D (0x00000005U) +#define NV0073_DISPLAY_PORT_ATTACHMENT_UNKNOWN (0xFFFFFFFFU) + +/* + * NV0073_CTRL_CMD_SPECIFIC_SET_ACPI_ID_MAPPING + * + * This call will update the RM data structure which holds the + * ACPI ID to display ID mapping of the display devices + * + * The input parameter is an array of structures of type + * NV0073_CTRL_SPECIFIC_ACPI_ID_MAPPING + * + * If some of the array elements remain unused, the acpiId field of the + * structure must be set to 0x0000 + * + * The size of the array is given by + * NV0073_CTRL_SPECIFIC_MAX_ACPI_DEVICES (defined below) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * +*/ +#define NV0073_CTRL_CMD_SPECIFIC_SET_ACPI_ID_MAPPING (0x730284U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_MAX_ACPI_DEVICES 16U + +#define NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS_MESSAGE_ID (0x84U) + +typedef struct NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS { + NV0073_CTRL_SPECIFIC_ACPI_ID_MAPPING mapTable[NV0073_CTRL_SPECIFIC_MAX_ACPI_DEVICES]; +} NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_ALL_HEAD_MASK + * + * This call will return all head mask. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * headMask + * headMask is the mask of all heads that are usable. For example, if + * head 0 and head 2 are present, headMask would be NVBIT(0)|NVBIT(2). This + * parameter returns to the client. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_ALL_HEAD_MASK (0x730287U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS_MESSAGE_ID (0x87U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS { + NvU32 subDeviceInstance; + NvU32 headMask; +} NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_SET_OD_PACKET + * + * This command is used to program the display output packets. + * Currently it supports DP and HDMI. + * Common supported packets are AVI infoframes, Audio Infoframes, Gamma + * Metadata, Vendor Specific infoframes and General Control Packets (GCP). + * + GCP AVMute Enable should be performed before the start of the modeset. + * + GCP AVMute Disable should be performed after the end of the modeset. + * GCP AVMute should contain HDR + 7 bytes. + * + AVI infoframes should occur after the modeset but before a GCP AVMute + * Disable. AVI infoframe should contain HDR + 14 bytes + * + Audio infoframes should occur after the modeset but before a GCP AVMute + * Enable. + * Audio infoframe should contain HDR + 11 bytes. + * + Gamma Metadata packets should contain HDR + 28 bytes. + * + Vendor Specific packets are variable length. + * By HDMI 1.4 June 5 2009 spec, payload can be 5 bytes, 6 bytes, 7 bytes or + * 16 bytes, depending on the packets spec. + * Unused data bytes should be zero-ed out. + * + * displayID + * This parameter specifies the displayID for the display resource to + * configure. + * This comes as input to this command. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * transmitControl + * This parameter controls how the packet is to be sent by setting the + * control bits. + * Possible flags are as follows: + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE + * Set to _ENABLE to start sending the packet at next frame, set to + * _DISABLE to stop sending. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME + * Set to _ENABLE to send the packet at other frame, set to _DISABLE to + * send at every frame. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME + * Set to _ENABLE to send once next frame, set to _DISABLE to send at + * every frame. + * Note: A setting to set both _OTHER_FRAME and _SINGLE_FRAME is invalid + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK + * Set to _ENABLE to send the packet once on next HBLANK, set to + * _DISABLE to send on VBLANK. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE + * Set to _ENABLE to send the info frame packet as soon as possible. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT + * Set to _SW_CONTROLLED to set HDMI_Video_Format field and 3D_Structure field + * from NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB4 and PB5, if it is set to _HW_CONTROLLED + * then HW will get them based on the state of the setHdmiCtrl method. + * Btw this applies only for stereo ovverides. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY + * Set to TRUE to send Vendor specific info frame used for 3D stereo LR sync. + * Set PACKET_TYPE=pktType_VendorSpecInfoFrame along with this flag. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING + * Set to TRUE to send Vendor specific info frame used for Self Refresh panels + * Set PACKET_TYPE=pktType_VendorSpecInfoFrame along with this flag. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE + * HW provides support to program 2 generic infoframes per frame for DP with GP10X+. + * This flag indicates the INFOFRAME that needs to be programmed. + * Set to _INFOFRAME0 if RM should program GENERIC_INFOFRAME + * Set to _INFOFRAME1 if RM should program GENERIC_INFOFRAME1 + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE + * This option is reserved for backward compatibility with + * NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_PACKET and + * NV0073_CTRL_CMD_DP_SET_PACKET. + * It is temporal and will be deprecated soon. + * packetSize + * packet size of packets in pPacket to send, including header and payload. + * targetHead + * Specifies the target head number for which SDP needs to be updated. + * bUsePsrHeadforSdp + * Indicates use targetHead field for setting SDP or infoframe packet instead + * of deriving the active head from displayID. + * pPacket + * pPacket points to the packets to send. + * For HDMI 1.1, the maximum allowed bytes is 31. + * The packet array includes the 3 bytes of header + data depending on + * the type of packet. For an infoframe, the header bytes refer to type, + * version and length respectively. This comes as input to this command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_SET_OD_PACKET (0x730288U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SET_OD_MAX_PACKET_SIZE 36U + +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS_MESSAGE_ID (0x88U) + +typedef struct NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 transmitControl; + NvU32 packetSize; + NvU32 targetHead; + NvBool bUsePsrHeadforSdp; + NvU8 aPacket[NV0073_CTRL_SET_OD_MAX_PACKET_SIZE]; +} NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS; + +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE 0:0 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME 1:1 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME_DISABLE (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME_ENABLE (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME 2:2 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME_DISABLE (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME_ENABLE (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK 3:3 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK_DISABLE (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK_ENABLE (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE 4:4 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE_DISABLE (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE_ENABLE (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT 5:5 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT_SW_CONTROLLED (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT_HW_CONTROLLED (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY 6:6 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY_FALSE (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY_TRUE (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING 7:7 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_FALSE (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_TRUE (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE 9:8 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE_INFOFRAME0 (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE_INFOFRAME1 (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE 31:31 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_YES (0x0000001U) + + +/* + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_PARAMS + * + * This command is used to enable/disable sending of display output packets. + * Currently it supports HDMI only. + * Unused data bytes should be zero-ed out. + * + * displayID + * This parameter specifies the displayID for the display output resource to + * configure. + * This comes as input to this command. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * type + * The client shall specify the type of display output packet. For HDMI, set + * this according to HDMI specification 1.4. + * This comes as input to this command. + * transmitControl + * This parameter controls how the packet is to be sent by setting the control + * bits. + * Possible flags are as follows: + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ENABLE + * Set to _ENABLE to start sending the packet at next frame, set to + * _DISABLE to stop sending. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_OTHER_FRAME + * Set to _ENABLE to send the packet at other frame, set to _DISABLE to + * send at every frame. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SINGLE_FRAME + * Set to _ENABLE to send once next frame, set to _DISABLE to send at + * every frame. + * Note: A setting to set both _OTHER_FRAME and _SINGLE_FRAME is invalid + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ON_HBLANK + * Set to _ENABLE to send the packet once on next HBLANK, set to _DISABLE + * to send on VBLANK. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_VIDEO_FMT + * Set to _SW_CONTROLLED to set HDMI_Video_Format field and 3D_Structure field + * from NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB4 and PB5, if it is set to _HW_CONTROLLED + * then HW will get them based on the state of the setHdmiCtrl method. + * Btw this applies only for stereo ovverides. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_STEREO_POLARITY + * Set to TRUE to enable Vendor specific info frame used for 3D stereo LR sync + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING + * Set to TRUE to enable Vendor specific info frame used for Self Refresh panels + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE + * This option is reserved for backward compatibility with + * NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_PACKET and + * NV0073_CTRL_CMD_DP_SET_PACKET. + * It is temporal and will be deprecated soon. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_SET_OD_PACKET_CTRL (0x730289U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_PARAMS_MESSAGE_ID (0x89U) + +typedef struct NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 type; + NvU32 transmitControl; +} NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_PARAMS; + +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ENABLE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ENABLE_NO NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE_NO +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ENABLE_YES NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE_YES +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_OTHER_FRAME NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_OTHER_FRAME_DISABLE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME_DISABLE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_OTHER_FRAME_ENABLE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME_ENABLE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SINGLE_FRAME NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SINGLE_FRAME_DISABLE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME_DISABLE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SINGLE_FRAME_ENABLE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME_ENABLE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ON_HBLANK NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ON_HBLANK_DISABLE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK_DISABLE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ON_HBLANK_ENABLE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK_ENABLE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_VIDEO_FMT NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_VIDEO_FMT_SW_CONTROLLED NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT_SW_CONTROLLED +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_VIDEO_FMT_HW_CONTROLLED NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT_HW_CONTROLLED +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_STEREO_POLARITY NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_STEREO_POLARITY_FALSE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY_FALSE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_STEREO_POLARITY_TRUE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY_TRUE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_TRUE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_FALSE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_FALSE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_TRUE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_NO NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_NO +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_YES NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_YES + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_PCLK_LIMIT + * + * This command returns the maximum supported pixel clock rate that is + * supported by the specified display device. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the display for which information is to be + * returned. Only one display may be indicated in this parameter. + * If more than one displayId is used a failing status of + * NV_ERR_INVALID_ARGUMENT will be returned. + * pclkLimit + * This parameter returns the min of orPclkLimit and vbPclkLimit in KHz. + * It may be used for SLI configs that use a video bridge. For non-SLI + * configs and bridgeless SLI configs, the client should use orPclkLimit instead. + * orPclkLimit + * This parameter returns the maximum pixel clock frequency of OR in KHz. + * vbPclkLimit + * This parameter returns the maximum pixel clock frequency of the + * video bridge (SLI) in KHz (or zero if there is no video bridge). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_PCLK_LIMIT (0x73028aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_PCLK_LIMIT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_GET_PCLK_LIMIT_PARAMS_MESSAGE_ID (0x8AU) + +typedef struct NV0073_CTRL_SPECIFIC_GET_PCLK_LIMIT_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 pclkLimit; + NvU32 orPclkLimit; + NvU32 vbPclkLimit; +} NV0073_CTRL_SPECIFIC_GET_PCLK_LIMIT_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_OR_GET_INFO + * + * This command returns output resource information for the specified display + * device. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the display for which information is to be + * returned. Only one display may be indicated in this parameter. + * If more than one displayId is used a failing status of + * NV_ERR_INVALID_ARGUMENT will be returned. + * type + * This parameter returns the output resource type. Legal values for + * this parameter include: + * NV0073_CTRL_SPECIFIC_OR_TYPE_DAC + * The output resource is a DAC. + * NV0073_CTRL_SPECIFIC_OR_TYPE_SOR + * The output resource is a serial output resource. + * NV0073_CTRL_SPECIFIC_OR_TYPE_DSI + * The output resource is a Display Serial Interface output resource. + * NV0073_CTRL_SPECIFIC_OR_TYPE_PIOR + * The output resource is a parallel input output resource. + * index + * This parameter returns the type-specific index of the output + * resource associated with the specified displayId. + * protocol + * This parameter returns the type-specific protocol used by the + * output resource. Legal values for this parameter include: + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_DAC_RGB_CRT + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_LVDS_CUSTOM + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_A + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_B + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DUAL_TMDS + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_A + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_B + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_PIOR_EXT_TMDS_ENC + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_DSI + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_UNKNOWN + * ditherType + * This parameter returns the dither type for the output resource. + * Legal values for this parameter include: + * NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_6_BITS + * NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_8_BITS + * NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_10_BITS + * NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_OFF + * ditherAlgo + * This parameter returns the dithering algorithm used by the output + * resource. Legal values for this parameter include: + * NV0073_CTRL_SPECIFIC_OR_DITHER_ALOGO_DYNAMIC_ERR_ACC + * NV0073_CTRL_SPECIFIC_OR_DITHER_ALOGO_STATIC_ERR_ACC + * NV0073_CTRL_SPECIFIC_OR_DITHER_ALOGO_DYNAMIC_2X2 + * NV0073_CTRL_SPECIFIC_OR_DITHER_ALOGO_STATIC_2X2 + * NV0073_CTRL_SPECIFIC_OR_DITHER_ALOGO_TEMPORAL + * NV0073_CTRL_SPECIFIC_OR_DITHER_ALOGO_UNKNOWN + * location + * This parameter returns the physical location of the output resource. + * Legal values for this parameter include: + * NV0073_CTRL_SPECIFIC_OR_LOCATION_CHIP + * NV0073_CTRL_SPECIFIC_OR_LOCATION_BOARD + * rootPortId + * This parameter specifies the Root-Port ID for the given display. + * dcbIndex + * This parameter returns the DCB index of the display device. + * vbiosAddress + * This parameter is the VBIOS IP address which will have valid value + * only if displayId is allocated by VBIOS. + * bIsLitByVbios + * This parameter specifies that whether displayID allocation was + * requested by VBIOS or not. + * bIsDispDynamic + * Returns NV_TRUE if DisplayID is allocated Dynamically else NV_FALSE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_OR_GET_INFO (0x73028bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS_MESSAGE_ID (0x8BU) + +typedef struct NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 index; + NvU32 type; + NvU32 protocol; + NvU32 ditherType; + NvU32 ditherAlgo; + NvU32 location; + NvU32 rootPortId; + NvU32 dcbIndex; + NV_DECLARE_ALIGNED(NvU64 vbiosAddress, 8); + NvBool bIsLitByVbios; + NvBool bIsDispDynamic; +} NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS; + +/* valid type values */ +#define NV0073_CTRL_SPECIFIC_OR_TYPE_NONE (0x00000000U) +#define NV0073_CTRL_SPECIFIC_OR_TYPE_DAC (0x00000001U) +#define NV0073_CTRL_SPECIFIC_OR_TYPE_SOR (0x00000002U) +#define NV0073_CTRL_SPECIFIC_OR_TYPE_PIOR (0x00000003U) + + +#define NV0073_CTRL_SPECIFIC_OR_TYPE_DSI (0x00000005U) + +/* valid DAC protocol values */ +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_DAC_RGB_CRT (0x00000000U) + + + +/* valid SOR protocol values */ +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_LVDS_CUSTOM (0x00000000U) +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_A (0x00000001U) +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_B (0x00000002U) +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DUAL_TMDS (0x00000005U) +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_A (0x00000008U) +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_B (0x00000009U) +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DSI (0x00000010U) + +/* valid DSI protocol values */ +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_DSI (0x00000011U) + +/* valid PIOR protocol values */ +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_PIOR_EXT_TMDS_ENC (0x00000000U) + +/* valid UNKNOWN protocol value */ +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_UNKNOWN (0xFFFFFFFFU) + +/* valid ditherType values */ +#define NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_6_BITS (0x00000000U) +#define NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_8_BITS (0x00000001U) +#define NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_10_BITS (0x00000002U) +#define NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_OFF (0x00000003U) + +/* valid ditherAlgo values */ +#define NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_DYNAMIC_ERR_ACC (0x00000000U) +#define NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_STATIC_ERR_ACC (0x00000001U) +#define NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_DYNAMIC_2X2 (0x00000002U) +#define NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_STATIC_2X2 (0x00000003U) +#define NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_TEMPORAL (0x00000004U) +#define NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_UNKNOWN (0xFFFFFFFFU) + +/* valid location values */ +#define NV0073_CTRL_SPECIFIC_OR_LOCATION_CHIP (0x00000000U) +#define NV0073_CTRL_SPECIFIC_OR_LOCATION_BOARD (0x00000001U) + + + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS + * NV0073_CTRL_CMD_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS + * + * These commands retrieve and set the user backlight brightness for + * the specified display. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId + * Display for which brightness is to be retrieved or set. + * brightness + * The backlight brightness in the range [0,100], inclusive. This + * is an input for SET_BACKLIGHT_BRIGHTNESS, and an output for + * GET_BACKLIGHT_BRIGHTNESS. + * + * + * Possible status values returned include: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS (0x730291U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | 0x91" */ + +#define NV0073_CTRL_CMD_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS (0x730292U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | 0x92" */ + +#define NV0073_CTRL_BACKLIGHT_BRIGHTNESS_MIN_VALUE 0U +#define NV0073_CTRL_BACKLIGHT_BRIGHTNESS_MAX_VALUE 100U + +typedef struct NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 brightness; +} NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS + * + * This command is used to inform RM about the scrambling, clock mode, FRL and + * DSC caps of the HDMI sink device. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed.. + * displayID + * This parameter specifies the displayID for the display output resource to + * configure. + * caps + * This parameter specifies the sink caps. + * GT_340MHZ_CLOCK_SUPPORTED refers to whether sink supports TMDS clock (sorClk) rate greater than 340 MHz + * LTE_340MHZ_SCRAMBLING_SUPPORTED refers to whether scrambling is supported for clock rate at or below 340 MHz + * SCDC_SUPPORTED refers to whether SCDC access is supported on sink + * MAX_FRL_RATE_SUPPORTED refers to the maximum HDMI 2.1 FRL rate supported + * DSC_12_SUPPORTED refers to whether VESA DSC v1.2a is supported + * DSC_12_MAX_FRL_RATE_SUPPORTED refers to the maximum HDMI 2.1 FRL rate supported when VESA DSC v1.2a is supported + * + * + * Possible status values returned include: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS (0x730293U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS_MESSAGE_ID (0x93U) + +typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 caps; +} NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS; + +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_GT_340MHZ_CLOCK_SUPPORTED 0:0 +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_GT_340MHZ_CLOCK_SUPPORTED_FALSE (0x00000000U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_GT_340MHZ_CLOCK_SUPPORTED_TRUE (0x00000001U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_LTE_340MHZ_SCRAMBLING_SUPPORTED 1:1 +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_LTE_340MHZ_SCRAMBLING_SUPPORTED_FALSE (0x00000000U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_LTE_340MHZ_SCRAMBLING_SUPPORTED_TRUE (0x00000001U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_SCDC_SUPPORTED 2:2 +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_SCDC_SUPPORTED_FALSE (0x00000000U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_SCDC_SUPPORTED_TRUE (0x00000001U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED 5:3 +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_NONE (0x00000000U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_3LANES_3G (0x00000001U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_3LANES_6G (0x00000002U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_6G (0x00000003U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_8G (0x00000004U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_10G (0x00000005U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_12G (0x00000006U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_12_SUPPORTED 6:6 +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_12_SUPPORTED_FALSE (0x00000000U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_12_SUPPORTED_TRUE (0x00000001U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED 9:7 +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_NONE (0x00000000U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_3LANES_3G (0x00000001U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_3LANES_6G (0x00000002U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_6G (0x00000003U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_8G (0x00000004U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_10G (0x00000005U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_12G (0x00000006U) + + + +/* + * NV0073_CTRL_CMD_SPECIFIC_SET_MONITOR_POWER + * + * This command sets monitor power on/off. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId + * This parameter specifies the displayID for the display output resource to + * configure. + * powerState + * This parameter should be one of the valid + * NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_* values. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_SET_MONITOR_POWER (0x730295U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS_MESSAGE_ID (0x95U) + +typedef struct NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 powerState; +} NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS; + +#define NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_OFF (0x00000000U) +#define NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_ON (0x00000001U) + + + +/* +* NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_CONFIG +* +* This command is used to perform HDMI FRL link training and enable FRL mode for +* the specified displayId. The link configuration will be returned after link +* training success. +* +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. +* displayID +* This parameter specifies the displayID for the display output resource to +* configure. +* data +* This parameter is an input and output to this command. +* Here are the current defined fields: +* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE +* This field specifies the desired setting for lane count. A client may +* choose any lane count as long as it does not exceed the capability of +* HDMI FRL sink as indicated in the sink capability field. +* The valid values for this field are: +* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_NONE +* For 0 lane configuration, link training is shut down (disable FRL). +* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_3G +* For FRL 3-lane configuration and 3 Gbps bandwidth per lane. +* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_6G +* For FRL 3-lane configuration and 6 Gbps bandwidth per lane. +* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_6G +* For FRL 4-lane configuration and 6 Gbps bandwidth per lane. +* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_8G +* For FRL 4-lane configuration and 8 Gbps bandwidth per lane. +* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_10G +* For FRL 4-lane configuration and 10 Gbps bandwidth per lane. +* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_12G +* For FRL 4-lane configuration and 12 Gbps bandwidth per lane. +* On return, the link bandwidth setting is returned which may be +* different from the requested input setting. +* bFakeLt +* This flag as input to this command. +* It indicates the FRL link training is a fake link training or not. +* TRUE if the FRL link training is fake and no real sink device attached. +* bLtSkipped +* The flag returned indicating whether link training is skipped or not. +* TRUE if link training is skipped due to the link config is not changed. +* +* Possible status values returned include: +* NV_OK - +* Affter finishing link tranning, NV_OK status will be returned along with +* the updated link congiration. In case of link training failure, FRL_RATE_NONE +* will be returned with NV_OK. +* NV_ERR_NOT_SUPPORTED - +* If the GPU/sink is not capable for HDMI FRL, NV_ERR_NOT_SUPPORTED status +* will be returned. +* NV_ERR_INVALID_ARGUMENT +* If any argument is valid for this control call, NV_ERR_INVALID_ARGUMENT +* status will be returned. +*/ +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_CONFIG (0x73029aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS_MESSAGE_ID (0x9AU) + +typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 data; + NvBool bFakeLt; + NvBool bLtSkipped; +} NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS; + +#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE 2:0 +#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_NONE (0x00000000U) +#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_3G (0x00000001U) +#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_6G (0x00000002U) +#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_6G (0x00000003U) +#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_8G (0x00000004U) +#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_10G (0x00000005U) +#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_12G (0x00000006U) + + + +#define NV0073_CTRL_SPECIFIC_MAX_CRC_REGIONS 9U + +#define NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS_PARAMS_MESSAGE_ID (0xA0U) + +typedef struct NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 regionCrcs[NV0073_CTRL_SPECIFIC_MAX_CRC_REGIONS]; + NvU16 reqRegionCrcMask; +} NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS + * + * This command is used to capture the active viewport region CRCs + * + * [in]subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * [in]displayId + * This parameter specifies the displayId of panel, for which region CRC to be captured +.* + * [out]regionCrcs + * This field holds the region CRC values to be returned after successful completion of the control command. + * + * [in]reqRegionCrcMask + * This parameter specifies BIT mask value of requested CRC regions. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS (0x7302a0U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS_PARAMS_MESSAGE_ID" */ + +/* +* NV0073_CTRL_CMD_SPECIFIC_APPLY_EDID_OVERRIDE_V2 +* +* Apply EDID override on specific OD. +* +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. +* displayId (in) +* ID of panel on which the operation is to be performed. +* bufferSize (in) +* Size of the EDID buffer. +* edidBuffer (in/out) +* The buffer which stores the EDID before and after override. +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_PARAMETER +*/ +#define NV0073_CTRL_CMD_SPECIFIC_APPLY_EDID_OVERRIDE_V2 (0x7302a1U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_APPLY_EDID_OVERRIDE_V2_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_APPLY_EDID_OVERRIDE_V2_PARAMS_MESSAGE_ID (0xA1U) + +typedef struct NV0073_CTRL_SPECIFIC_APPLY_EDID_OVERRIDE_V2_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 bufferSize; + NvU8 edidBuffer[NV0073_CTRL_SPECIFIC_GET_EDID_MAX_EDID_BYTES]; +} NV0073_CTRL_SPECIFIC_APPLY_EDID_OVERRIDE_V2_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS + * + * This command is used to get the HDMI FRL caps of GPU side. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * caps + * This parameter specifies the GPU caps. + * MAX_FRL_RATE_SUPPORTED refers to the maximum HDMI 2.1 FRL link rate supported + * + * + * Possible status values returned include: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS (0x7302a2U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_HDMI_GPU_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_GET_HDMI_GPU_CAPS_PARAMS_MESSAGE_ID (0xA2U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_HDMI_GPU_CAPS_PARAMS { + NvU32 subDeviceInstance; + NvU32 caps; +} NV0073_CTRL_SPECIFIC_GET_HDMI_GPU_CAPS_PARAMS; + +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED 2:0 +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_NONE (0x00000000U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_3LANES_3G (0x00000001U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_3LANES_6G (0x00000002U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_4LANES_6G (0x00000003U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_4LANES_8G (0x00000004U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_4LANES_10G (0x00000005U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_4LANES_12G (0x00000006U) + + + +/* + * NV0073_CTRL_CMD_SPECIFIC_DISPLAY_CHANGE + * + * Notifies the system that a display change is about to begin/end. + * Also performs the necessary synchronizations for the same. + * + * The command takes a NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS structure as an + * argument with appropriate subDeviceInstance. + * + * [in]subDeviceInstance + * The sub-device instance + * [in]newDevices + * Bitmask of devices that are planned on being enabled with the + * pending device change. See NV_CFGEX_GET_DEVICES_CONFIGURATION for bit defs. + * [in]properties + * Bitmask of display attributes for new configuration (none used at the moment). + * [in]enable + * Parameter to decide between display change start and end. Can take values + * NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_START or NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_END. + * Possible return values: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + */ + +#define NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS_MESSAGE_ID (0xA4U) + +typedef struct NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS { + + NvU32 subDeviceInstance; + NvU32 newDevices; + NvU32 properties; + NvU32 enable; +} NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS; + +#define NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_END (0x00000000U) +#define NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_START (0x00000001U) + +#define NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PROPERTIES_SPANNING (0x00000001U) + +#define NV0073_CTRL_CMD_SPECIFIC_DISPLAY_CHANGE (0x7302a4U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS_MESSAGE_ID" */ + + + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA + * + * This command is used to get the HDMI sink status/caps via Status and Control + * Data Channel (SCDC). + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId + * This parameter specifies the displayId of HDMI sink. + * offset + * This parameter specifies the SCDC offset which the read operation + * should be used. + * data + * This field specifies the return data from sink for reading the specified + * SCDC offset. + * + * + * Possible status values returned include: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA (0x7302a6U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_HDMI_SCDC_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_GET_HDMI_SCDC_DATA_PARAMS_MESSAGE_ID (0xA6U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_HDMI_SCDC_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU8 offset; + NvU8 data; +} NV0073_CTRL_SPECIFIC_GET_HDMI_SCDC_DATA_PARAMS; + +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET 7:0 +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_NONE (0x00000000U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_SINK_VERSION (0x00000001U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_SOURCE_VERSION (0x00000002U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_UPDATE_FLAGS_0 (0x00000010U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_TMDS_CONFIGURATION (0x00000020U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_SCRAMBLER_STATUS (0x00000021U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CONFIGURATION_0 (0x00000030U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CONFIGURATION_1 (0x00000031U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_SOURCE_TEST_CONFIGURATION (0x00000035U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_STATUS_FLAGS_0 (0x00000040U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_STATUS_FLAGS_1 (0x00000041U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_STATUS_FLAGS_2 (0x00000042U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_0 (0x00000050U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_1 (0x00000051U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_2 (0x00000052U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_3 (0x00000053U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_4 (0x00000054U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_5 (0x00000055U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_6 (0x00000056U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_7 (0x00000057U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_8 (0x00000058U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_RSED_0 (0x00000059U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_RSED_1 (0x0000005AU) + +/* + * NV0073_CTRL_CMD_SPECIFIC_IS_DIRECTMODE_DISPLAY + * + * This command is used to query whether the specified monitor should be used + * with directmode. + * + * [in]manufacturerID + * This parameter specifies the 16-bit EDID Manufacturer ID. + * [in]productID + * This parameter specifies the 16-bit EDID Product ID. + * [out]bIsDirectmode; + * This indicates whether the monitor should be used with directmode. + * Possible return values: + * NV_OK + */ + +#define NV0073_CTRL_CMD_SPECIFIC_IS_DIRECTMODE_DISPLAY (0x7302a7U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_IS_DIRECTMODE_DISPLAY_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_IS_DIRECTMODE_DISPLAY_PARAMS_MESSAGE_ID (0xA7U) + +typedef struct NV0073_CTRL_SPECIFIC_IS_DIRECTMODE_DISPLAY_PARAMS { + NvU16 manufacturerID; + NvU16 productID; + NvBool bIsDirectmode; +} NV0073_CTRL_SPECIFIC_IS_DIRECTMODE_DISPLAY_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION + * + * This command is used to get the HDMI FRL capacity computation result. + * + * [in] cmd + * This parameter specifies the command for the HDMI FRL capacity computation. + * [in] input + * This parameter specifies the input data for the HDMI FRL capacity + * computation. + * [out] result + * This indicates the computation result of HDMI FRL capacity computation. + * [in/out] preCalc + * This indicates the pre-caculation result of HDMI FRL capacity computation. + * [in/out] dsc + * This indicates the DSC parameters of HDMI FRL capacity computation. + * Possible return values: + * NV_OK + */ + +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION (0x7302a8U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS_MESSAGE_ID" */ + +typedef struct NV0073_CTRL_FRL_CAPACITY_COMPUTATION_PARAMS { + NvU32 numLanes; + NvU32 frlBitRateGbps; + NvU32 pclk10KHz; + NvU32 hTotal; + NvU32 hActive; + NvU32 bpc; + NvU32 pixelPacking; + NvU32 audioType; + NvU32 numAudioChannels; + NvU32 audioFreqKHz; + + struct { + NvU32 bppTargetx16; + NvU32 hSlices; + NvU32 sliceWidth; + NvU32 dscTotalChunkKBytes; + } compressionInfo; +} NV0073_CTRL_FRL_CAPACITY_COMPUTATION_PARAMS; + +typedef struct NV0073_CTRL_FRL_CAPACITY_COMPUTATION_RESULT { + NvU32 frlRate; + NvU32 bppTargetx16; + NvBool engageCompression; + NvBool isAudioSupported; + NvBool dataFlowDisparityReqMet; + NvBool dataFlowMeteringReqMet; + NvBool isVideoTransportSupported; + NvU32 triBytesBorrowed; + NvU32 hcActiveBytes; + NvU32 hcActiveTriBytes; + NvU32 hcBlankTriBytes; + NvU32 tBlankToTTotalX1k; +} NV0073_CTRL_FRL_CAPACITY_COMPUTATION_RESULT; + +typedef struct NV0073_CTRL_FRL_PRE_CALC_CONFIG { + NvU32 vic; + NvU32 packing; + NvU32 bpc; + NvU32 frlRate; + NvU32 bppX16; + NvBool bHasPreCalcFRLData; +} NV0073_CTRL_FRL_PRE_CALC_CONFIG; + +typedef struct NV0073_CTRL_IS_FRL_DSC_POSSIBLE_PARAMS { + NvU32 maxSliceCount; + NvU32 maxSliceWidth; + NvBool bIsDSCPossible; +} NV0073_CTRL_IS_FRL_DSC_POSSIBLE_PARAMS; + +#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS_MESSAGE_ID (0xA8U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS { + NvU8 cmd; + NV0073_CTRL_FRL_CAPACITY_COMPUTATION_PARAMS input; + NV0073_CTRL_FRL_CAPACITY_COMPUTATION_RESULT result; + NV0073_CTRL_FRL_PRE_CALC_CONFIG preCalc; + NV0073_CTRL_IS_FRL_DSC_POSSIBLE_PARAMS dsc; +} NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS; + +#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_NULL (0x00000000U) +#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_UNCOMPRESSED_VIDEO (0x00000001U) +#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_COMPRESSED_VIDEO (0x00000002U) +#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_HAS_PRECAL_FRL_DATA (0x00000003U) +#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_GET_PRECAL_UNCOMPRESSED_FRL_CONFIG (0x00000004U) +#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_GET_PRECAL_COMPRESSED_FRL_CONFIG (0x00000005U) +#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_IS_FRL_DSC_POSSIBLE (0x00000006U) + +/* + * NV0073_CTRL_CMD_SPECIFIC_SET_SHARED_GENERIC_PACKET + * + * This command is used to program the display output packets. + * This generic packets can be used for both HDMI and DP. + * HW has added 6 new generic packets for each head because some usecases have + * requirement to send infoframe in particular location (vsync, vblank, loadV). + * + * Note: 1. Client first needs to reserve or acquire a free infoframe index + * using NV0073_CTRL_CMD_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET. + * 2. Client needs to update the SDP index for head through control call + * NV0073_CTRL_CMD_SPECIFIC_SET_SHARED_GENERIC_PACKET + * 3. Client needs to Release the infoframe index using control call + * NV0073_CTRL_CMD_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET + * + * [in]subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * [in]transmitControl + * This parameter controls how the packet is to be sent by setting the + * control bits. + * Possible flags are as follows: + * NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_ENABLE + * Setting this field to _YES will enable this generic infoframe, + * Setting this field to _NO will disable this generic infoframe. + * NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_SINGLE + * Set to _YES will cause new infoframe to be transmitted exactly once. + * Set to _NO will cause new infoframe to be transmitted every frame. + * NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_LOC + * SDP can be sent in 3 different locations: + * VBLANK - new infoframe will be sent at Vblank. + * VSYNC - new infoframe will be sent at Vsync. + * LOADV - new infoframe will be triggered by LOADV, and sent at Vsync + * NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_UPDATE_RFB_OVERRIDE + * _ENABLE: override DB1 bit1 with existence of loadv (for Panel Self Refresh) + * _DISABLE: do not override shared generic infoframe subpacker DB1 bit1. + * NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_SU_COORDINATES_VALID_OVERRIDE + * _ENABLE: override DB1 bit3 with existence of loadv (for Panel Replay) + * _DISABLE: do not override shared generic infoframe subpacker DB1 bit3. + * [in]packetSize + * size of packets in Packet array to send, including header and payload. + * [in]infoframeIndex + * Specifies the target head number for which SDP needs to be updated. + * [in]infoframeIndex + * Specifies the index of infoframe. + * [in]packet + * pPacket points to the packets to send. + * For HDMI 1.1, the maximum allowed bytes is 31. + * The packet array includes the 3 bytes of header + data depending on + * the type of packet. For an infoframe, the header bytes refer to type, + * version and length respectively. This comes as input to this command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SPECIFIC_SET_SHARED_GENERIC_PACKET (0x7302a9) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_SHARED_GENERIC_PACKET_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_SHARED_GENERIC_PACKET_PARAMS_MESSAGE_ID (0xA9U) + +typedef struct NV0073_CTRL_SPECIFIC_SET_SHARED_GENERIC_PACKET_PARAMS { + NvU32 subDeviceInstance; + NvU32 transmitControl; + NvU32 packetSize; + NvU32 targetHeadIndex; + NvU32 infoframeIndex; + NvU8 packet[NV0073_CTRL_SET_OD_MAX_PACKET_SIZE]; +} NV0073_CTRL_SPECIFIC_SET_SHARED_GENERIC_PACKET_PARAMS; + +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_ENABLE 0:0 +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_ENABLE_NO (0x0000000) +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_ENABLE_YES (0x0000001) + +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_SINGLE 1:1 +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_SINGLE_NO (0x0000000) +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_SINGLE_YES (0x0000001) + +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_LOC 5:2 +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_LOC_VBLANK (0x0000000) +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_LOC_VSYNC (0x0000001) +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_LOC_LOADV (0x0000002) + +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_STATE_OVERRIDE 6:6 +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_STATE_OVERRIDE_DISABLE (0x0000000) +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_STATE_OVERRIDE_ENABLE (0x0000001) + +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_UPDATE_RFB_OVERRIDE 7:7 +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_UPDATE_RFB_OVERRIDE_DISABLE (0x0000000) +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_UPDATE_RFB_OVERRIDE_ENABLE (0x0000001) + +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_SU_COORDINATES_VALID_OVERRIDE 8:8 +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_SU_COORDINATES_VALID_OVERRIDE_DISABLE (0x0000000) +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_SU_COORDINATES_VALID_OVERRIDE_ENABLE (0x0000001) + +/* + * NV0073_CTRL_CMD_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET + * + * This command is used to reserve the infoframe for head and RM would assign + * free infoframe index and return the index of infoframe. Later client needs + * to call control call NV0073_CTRL_CMD_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET + * to release the index. + * + * [in]subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * [in]targetHeadIndex + * target Head for which SDP needs to be sent + * [out]infoframeIndex + * return Infoframe Index for head. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFIENT_RESOURCES + */ + +#define NV0073_CTRL_CMD_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET (0x7302aa) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET_PARAMS_MESSAGE_ID (0xAAU) + +typedef struct NV0073_CTRL_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET_PARAMS { + NvU32 subDeviceInstance; + NvU32 targetHeadIndex; + NvU32 infoframeIndex; +} NV0073_CTRL_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET + * + * This command is used to release the infoframe index which was acquired by + * client. + * + * [in]subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * [in]targetHeadIndex + * Specifies the target head number for which SDP needs to be updated. + * [in]infoframeIndex + * Infoframe index for the target head + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET (0x7302ab) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET_PARAMS_MESSAGE_ID (0xABU) + +typedef struct NV0073_CTRL_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET_PARAMS { + NvU32 subDeviceInstance; + NvU32 targetHeadIndex; + NvU32 infoframeIndex; +} NV0073_CTRL_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_DISP_I2C_READ_WRITE + * + * This command is used to do I2C R/W to slave on display i2c instance. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * i2cPort + * This parameter specifies the I2C CCB port ID. + * i2cSlaveAddress + * This parameter specifies the I2C slave address. + * readWriteFlag + * This parameter specifies whether its read/write operation. + * readWriteLen + * This parameter specifies the length of the read/write buffer + * readBuffer + * This parameter reads the data from slave address and copies to this + * buffer + * writeBuffer + * This parameter specifies this buffer data that would be written to + * slave address + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SPECIFIC_DISP_I2C_READ_WRITE (0x7302acU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_BUF_LEN 128U + +#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS_MESSAGE_ID (0xACU) + +typedef struct NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS { + NvU32 subDeviceInstance; + NvU32 i2cPort; + NvU32 i2cSlaveAddress; + NvU32 readWriteFlag; + NvU32 readWriteLen; + NvU8 readBuffer[NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_BUF_LEN]; + NvU8 writeBuffer[NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_BUF_LEN]; +} NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS; + +#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_MODE (0x00000001) +#define NV0073_CTRL_SPECIFIC_DISP_I2C_WRITE_MODE (0x00000000) + +/* + * NV0073_CTRL_CMD_GET_VALID_HEAD_WINDOW_ASSIGNMENT + * + * This command returns the valid window head assignment mask + * + * windowHeadMask [out] + * This out parameter is an array which holds the head mask for + * each window. The Nth element in the array would be a bitmask + * of which heads can possibly drive window N. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT (0x7302ad) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_MAX_WINDOWS 32U +#define NV0073_CTRL_SPECIFIC_FLEXIBLE_HEAD_WINDOW_ASSIGNMENT (0xFFU) + +#define NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS_MESSAGE_ID (0xADU) + +typedef struct NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS { + NvU32 subDeviceInstance; + NvU8 windowHeadMask[NV0073_CTRL_SPECIFIC_MAX_WINDOWS]; +} NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS; + +/* _ctrl0073specific_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h new file mode 100644 index 0000000..9a585aa --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h @@ -0,0 +1,166 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073stereo.finn +// + +#include "ctrl/ctrl0073/ctrl0073base.h" + + + +/* + * NV0073_CTRL_CMD_STEREO_DONGLE_SET_TIMINGS + * + * Sets new video mode timings + * E.g. from display driver on mode set + * + * Parameters: + * [IN] subDeviceInstance - This parameter specifies the subdevice instance + * within the NV04_DISPLAY_COMMON parent device to which the operation + * should be directed. This parameter must specify a value between + * zero and the total number of subdevices within the parent device. + * This parameter should be set to zero for default behavior. + * [IN] head - head to be passed to stereoDongleControl + * [IN] timings - new timings to be set + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED - stereo is not initialized on the GPU + */ +#define NV0073_CTRL_CMD_STEREO_DONGLE_SET_TIMINGS (0x731703U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID << 8) | NV0073_CTRL_STEREO_DONGLE_SET_TIMINGS_PARAMS_MESSAGE_ID" */ + +typedef struct NV0073_CTRL_STEREO_VIDEO_MODE_TIMINGS { + NvU32 PixelClock; + NvU16 TotalWidth; + NvU16 VisibleImageWidth; + NvU16 HorizontalBlankStart; + NvU16 HorizontalBlankWidth; + NvU16 HorizontalSyncStart; + NvU16 HorizontalSyncWidth; + NvU16 TotalHeight; + NvU16 VisibleImageHeight; + NvU16 VerticalBlankStart; + NvU16 VerticalBlankHeight; + NvU16 VerticalSyncStart; + NvU16 VerticalSyncHeight; + NvU16 InterlacedMode; + NvU16 DoubleScanMode; + + NvU16 MonitorVendorId; + NvU16 MonitorProductId; +} NV0073_CTRL_STEREO_VIDEO_MODE_TIMINGS; + +#define NV0073_CTRL_STEREO_DONGLE_SET_TIMINGS_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0073_CTRL_STEREO_DONGLE_SET_TIMINGS_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NV0073_CTRL_STEREO_VIDEO_MODE_TIMINGS timings; +} NV0073_CTRL_STEREO_DONGLE_SET_TIMINGS_PARAMS; + +/* + * NV0073_CTRL_CMD_STEREO_DONGLE_ACTIVATE + * + * stereoDongleActivate wrapper / NV_STEREO_DONGLE_ACTIVATE_DATA_ACTIVE_YES + * Updates sbios of 3D stereo state active + * + * Parameters: + * [IN] subDeviceInstance - This parameter specifies the subdevice instance + * within the NV04_DISPLAY_COMMON parent device to which the operation + * should be directed. This parameter must specify a value between + * zero and the total number of subdevices within the parent device. + * This parameter should be set to zero for default behavior. + * [IN] head - head to be passed to stereoDongleActivate + * [IN] bSDA - enable stereo on DDC SDA + * [IN] bWorkStation - is workstation stereo? + * [IN] bDLP - is checkerboard DLP Stereo? + * [IN] IRPower - IR power value + * [IN] flywheel - FlyWheel value + * [IN] bRegIgnore - use reg? + * [IN] bI2cEmitter - Sets NV_STEREO_DONGLE_ACTVATE_DATA_I2C_EMITTER_YES and pStereo->bAegisDT + * [IN] bForcedSupported - Sets NV_STEREO_DONGLE_FORCED_SUPPORTED_YES and pStereo->GPIOControlledDongle + * [IN] bInfoFrame - Aegis DT with DP InfoFrame + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT - if (head > OBJ_MAX_HEADS) + * NV_ERR_NOT_SUPPORTED - stereo is not initialized on the GPU + */ +#define NV0073_CTRL_CMD_STEREO_DONGLE_ACTIVATE (0x731704U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID << 8) | NV0073_CTRL_STEREO_DONGLE_ACTIVATE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_STEREO_DONGLE_ACTIVATE_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0073_CTRL_STEREO_DONGLE_ACTIVATE_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvBool bSDA; + NvBool bWorkStation; + NvBool bDLP; + NvU8 IRPower; + NvU8 flywheel; + NvBool bRegIgnore; + NvBool bI2cEmitter; + NvBool bForcedSupported; + NvBool bInfoFrame; +} NV0073_CTRL_STEREO_DONGLE_ACTIVATE_PARAMS; + +/* + * NV0073_CTRL_CMD_STEREO_DONGLE_DEACTIVATE + * + * stereoDongleActivate wrapper / NV_STEREO_DONGLE_ACTIVATE_DATA_ACTIVE_NO + * + * If active count<=0 then no 3D app is running which indicates + * that we have really deactivated the stereo, updates sbios of 3D stereo state NOT ACTIVE. + * + * Parameters: + * [IN] subDeviceInstance - This parameter specifies the subdevice instance + * within the NV04_DISPLAY_COMMON parent device to which the operation + * should be directed. This parameter must specify a value between + * zero and the total number of subdevices within the parent device. + * This parameter should be set to zero for default behavior. + * [IN] head - head to be passed to stereoDongleActivate + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT - if (head > OBJ_MAX_HEADS) + * NV_ERR_NOT_SUPPORTED - stereo is not initialized on the GPU + */ +#define NV0073_CTRL_CMD_STEREO_DONGLE_DEACTIVATE (0x731705U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID << 8) | NV0073_CTRL_STEREO_DONGLE_DEACTIVATE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_STEREO_DONGLE_DEACTIVATE_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0073_CTRL_STEREO_DONGLE_DEACTIVATE_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; +} NV0073_CTRL_STEREO_DONGLE_DEACTIVATE_PARAMS; + + + +/* _ctrl0073stereo_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073svp.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073svp.h new file mode 100644 index 0000000..08a06ae --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073svp.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073svp.finn +// + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h new file mode 100644 index 0000000..d25501a --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h @@ -0,0 +1,1480 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073system.finn +// + +#include "ctrl/ctrl0073/ctrl0073base.h" + +/* NV04_DISPLAY_COMMON system-level control commands and parameters */ + +/* extract cap bit setting from tbl */ +#define NV0073_CTRL_SYSTEM_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* Caps format is byte_index:bit_mask. + * Important: keep the number of bytes needed for these fields in sync with + * NV0073_CTRL_SYSTEM_CAPS_TBL_SIZE + */ +#define NV0073_CTRL_SYSTEM_CAPS_AA_FOS_GAMMA_COMP_SUPPORTED 0:0x01 +#define NV0073_CTRL_SYSTEM_CAPS_TV_LOWRES_BUG_85919 0:0x02 +#define NV0073_CTRL_SYSTEM_CAPS_DFP_GPU_SCALING_BUG_154102 0:0x04 +#define NV0073_CTRL_SYSTEM_CAPS_SLI_INTERLACED_MODE_BUG_235218 0:0x08 // Deprecated +#define NV0073_CTRL_SYSTEM_CAPS_STEREO_DIN_AVAILABLE 0:0x10 +#define NV0073_CTRL_SYSTEM_CAPS_OFFSET_PCLK_DFP_FOR_EMI_BUG_443891 0:0x20 +#define NV0073_CTRL_SYSTEM_CAPS_GET_DMI_SCANLINE_SUPPORTED 0:0x40 +/* + * Indicates support for HDCP Key Selection Vector (KSV) list and System + * Renewability Message (SRM) validation +*/ +#define NV0073_CTRL_SYSTEM_CAPS_KSV_SRM_VALIDATION_SUPPORTED 0:0x80 + +#define NV0073_CTRL_SYSTEM_CAPS_SINGLE_HEAD_MST_SUPPORTED 1:0x01 +#define NV0073_CTRL_SYSTEM_CAPS_SINGLE_HEAD_DUAL_SST_SUPPORTED 1:0x02 +#define NV0073_CTRL_SYSTEM_CAPS_HDMI_2_0_SUPPORTED 1:0x04 +#define NV0073_CTRL_SYSTEM_CAPS_CROSS_BAR_SUPPORTED 1:0x08 +#define NV0073_CTRL_SYSTEM_CAPS_RASTER_LOCK_NEEDS_MIO_POWER 1:0x10 +/* + * Indicates that modesets where no heads are increasing resource requirements, + * or no heads are decreasing resource requirements, can be done glitchlessly. + */ +#define NV0073_CTRL_SYSTEM_CAPS_GLITCHLESS_MODESET_SUPPORTED 1:0x20 +/* Indicates the SW ACR is enabled for HDMI 2.1 due to Bug 3275257. */ +#define NV0073_CTRL_SYSTEM_CAPS_HDMI21_SW_ACR_BUG_3275257 1:0x40 + +/* Size in bytes of display caps table. Keep in sync with # of fields above. */ +#define NV0073_CTRL_SYSTEM_CAPS_TBL_SIZE 2U + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_CAPS_V2 + * + * This command returns the set of display capabilities for the parent device + * in the form of an array of unsigned bytes. Display capabilities + * include supported features and required workarounds for the display + * engine(s) within the device, each represented by a byte offset into the + * table and a bit position within that byte. The set of display capabilities + * will be normalized across all GPUs within the device (a feature capability + * will be set only if it's supported on all GPUs while a required workaround + * capability will be set if any of the GPUs require it). + * + * [out] capsTbl + * The display caps bits will be transferred by the RM into this array of + * unsigned bytes. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_CAPS_V2 (0x730138U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x38U) + +typedef struct NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS { + NvU8 capsTbl[NV0073_CTRL_SYSTEM_CAPS_TBL_SIZE]; +} NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_NUM_HEADS + * + * This commands returns the number of heads supported by the specified + * subdevice and available for use by displays. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * flags + * This parameter specifies optional flags to be used to while retrieving + * the number of heads. + * Possible valid flags are: + * NV0073_CTRL_SYSTEM_GET_NUM_HEADS_CLIENT + * This flag is used to request the number of heads that are + * currently in use by an NV client using a user display class + * instance (see NV15_VIDEO_LUT_CURSOR_DAC for an examle). If this + * flag is disabled then the total number of heads supported is + * returned. + * numHeads + * This parameter returns the number of usable heads for the specified + * subdevice. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_NUM_HEADS (0x730102U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS { + NvU32 subDeviceInstance; + NvU32 flags; + NvU32 numHeads; +} NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS; + +/* valid get num heads flags */ +#define NV0073_CTRL_SYSTEM_GET_NUM_HEADS_FLAGS_CLIENT 0:0 +#define NV0073_CTRL_SYSTEM_GET_NUM_HEADS_FLAGS_CLIENT_DISABLE (0x00000000U) +#define NV0073_CTRL_SYSTEM_GET_NUM_HEADS_FLAGS_CLIENT_ENABLE (0x00000001U) + + + + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_SCANLINE + * + * This command returns the current RG scanline of the specified head on the + * specified subdevice. To get the DMI scanline on supported chips, use + * NV0073_CTRL_CMD_SYSTEM_GET_DMI_SCANLINE + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * head + * This parameter specifies the head for which the active display + * should be retrieved. This value must be between zero and the + * maximum number of heads supported by the subdevice. + * currentScanline + * This parameter returns the current RG scanline value for the specified + * head. If the head does not have a valid mode enabled then a scanline + * value of 0xffffffff is returned. + * bStereoEyeSupported (out) + * This parameter specifies whether stereoEye reporting is supported (this + * is hw dependent). Note that this value doesn't actually reflect whether + * given head is really in stereo mode. + * stereoEye (out) + * If supported (ie bStereoEyeSupported is TRUE), this parameter returns + * either NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS_RIGHT_EYE or + * NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS_LEFT_EYE, reflecting the + * stereo eye that is currently scanned out. Although this value typically + * changes at the beginning of vblank, the exact guarantee isn't more + * accurate than "somewhere in vblank". + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_SCANLINE (0x730108U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_GET_SCANLINE_RIGHT_EYE 0x00000000U +#define NV0073_CTRL_CMD_SYSTEM_GET_SCANLINE_LEFT_EYE 0x00000001U + +#define NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvU32 currentScanline; + NvBool bStereoEyeSupported; + NvU32 stereoEye; +} NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_VBLANK_COUNTER + * + * This command returns the current VBlank counter of the specified head on the + * specified subdevice. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * head + * This parameter specifies the head for which the vblank counter + * should be retrieved. This value must be between zero and the + * maximum number of heads supported by the subdevice. + * verticalBlankCounter + * This parameter returns the vblank counter value for the specified + * head. If the display mode is not valid or vblank not active then + * the verticalBlankCounter value is undefined. + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_VBLANK_COUNTER (0x730109U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvU32 verticalBlankCounter; +} NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_VBLANK_ENABLE + * + * This command returns the current VBlank enable status for the specified + * head. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * head + * This parameter specifies the head for which the vblank status + * should be retrieved. This value must be between zero and the + * maximum number of heads supported by the subdevice. + * bEnabled + * This parameter returns the vblank enable status for the specified head. + * A value of NV_FALSE indicates that vblank interrupts are not currently + * enabled while a value of NV_TRUE indicates that vblank are currently + * enabled. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_VBLANK_ENABLE (0x73010aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvBool bEnabled; +} NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED + * + * This command returns the set of supported display IDs for the specified + * subdevice in the form of a 32bit display mask. State from internal + * display connectivity tables is used to determine the set of possible + * display connections for the GPU. The presence of a display in the + * display mask only indicates the display is supported. The connectivity + * status of the display should be determined using the + * NV0073_CTRL_CMD_SYSTEM_GET_CONNECT_STATE command. The displayMask + * value returned by NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED is static + * and will remain consistent across boots of the system. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayMask + * This parameter returns a NV0073_DISPLAY_MASK value describing the set + * of displays supported by the subdevice. An enabled bit in displayMask + * indicates the support of a display device with that displayId. + * displayMaskDDC + * This parameter returns a NV0073_DISPLAY_MASK value, indicating the + * subset of displayMask that supports DDC. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED (0x730120U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayMask; + NvU32 displayMaskDDC; +} NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_CONNECT_STATE + * + * This command can be used to check the presence of a mask of display + * devices on the specified subdevice. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * flags + * This parameter specifies optional flags to be used while retrieving + * the connection state information. + * Here are the current defined fields: + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD + * A client uses this field to indicate what method it wishes the + * system to use when determining the presence of attached displays. + * Possible values are: + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD_DEFAULT + * The system decides what method to use. + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD_CACHED + * Return the last full detection state for the display mask. + * safety.) + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD_ECONODDC + * Ping the DDC address of the given display mask to check for + * a connected device. This is a lightweight method to check + * for a present device. + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_DDC + * A client uses this field to indicate whether to allow DDC during + * this detection or to not use it. + * Possible values are: + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_DDC_DEFAULT + * The system will use DDC as needed for each display. + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_DDC_DISABLE + * The system will not use DDC for any display. If DDC is + * disabled, this detection state will not be cached. + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_LOAD + * A client uses this field to indicate whether to detect loads + * during this detection or to not use it. + * Possible values are: + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_LOAD_DEFAULT + * The system will use load detection as needed for each display. + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_LOAD_DISABLE + * The system will not use load detection for any display. If + * load detection is disabled, this detection state will not + * be cached. + * displayMask + * This parameter specifies an NV0073_DISPLAY_MASK value describing + * the set of displays for which connectivity status is to be checked. + * If a display is present then the corresponding bit in the display + * mask is left enabled. If the display is not present then the + * corresponding bit in the display mask is disabled. Upon return this + * parameter contains the subset of displays in the mask that are + * connected. + * + * If displayMask includes bit(s) that correspond to a TV encoder, the + * result will be simply 'yes' or 'no' without any indication of which + * connector(s) are actually attached. For fine-grained TV attachment + * detection, please see NV0073_CTRL_CMD_TV_GET_ATTACHMENT_STATUS. + * retryTimeMs + * This parameter is an output to this command. In case of + * NVOS_STATUS_ERROR_RETRY return status, this parameter returns the time + * duration in milli-seconds after which client should retry this command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_ERROR_RETRY + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_CONNECT_STATE (0x730122U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS { + NvU32 subDeviceInstance; + NvU32 flags; + NvU32 displayMask; + NvU32 retryTimeMs; +} NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS; + +/* valid get connect state flags */ +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD 1:0 +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD_DEFAULT (0x00000000U) +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD_CACHED (0x00000001U) +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD_ECONODDC (0x00000002U) +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_DDC 4:4 +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_DDC_DEFAULT (0x00000000U) +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_DDC_DISABLE (0x00000001U) +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_LOAD 5:5 +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_LOAD_DEFAULT (0x00000000U) +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_LOAD_DISABLE (0x00000001U) +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_VBLANK 6:6 +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_VBLANK_DEFAULT (0x00000000U) +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_VBLANK_SAFE (0x00000001U) + + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_CONFIG + * + * This command can be used to retrieve dynamic hotplug state information that + * are currently recorded by the RM. This information can be used by the client + * to determine which displays to detect after a hotplug event occurs. Or if + * the client knows that this device generates a hot plug/unplug signal on all + * connectors, then this can be used to cull displays from detection. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * flags + * This parameter specifies optional flags to be used while retrieving + * or changing the hotplug configuration. + * No flags are currently defined. + * hotplugEventMask + * For _GET_HOTPLUG_CONFIG, this returns which connectors the client + * has asked for notifications for, when a hotplug event is detected. + * Events can only be provided for connectors whose displayID is set + * by the system in the hotplugInterruptible field. + * hotplugPollable + * For _GET_HOTPLUG_CONFIG, this returns which connectors are pollable + * in some non-destructive fashion. + * hotplugInterruptible + * For _GET_HOTPLUG_CONFIG, this returns which connectors are capable + * of generating interrupts. + * + * This display mask specifies an NV0073_DISPLAY_MASK value describing + * the set of displays that have seen a hotplug or hotunplug event + * sometime after the last valid EDID read. If the device never has + * a valid EDID read, then it will always be listed here. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + + +#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_CONFIG (0x730123U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS_MESSAGE_ID (0x23U) + +typedef struct NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS { + NvU32 subDeviceInstance; + NvU32 flags; + NvU32 hotplugEventMask; + NvU32 hotplugPollable; + NvU32 hotplugInterruptible; + NvU32 hotplugAlwaysAttached; +} NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS; + + + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_HEAD_ROUTING_MAP + * + * This command can be used to retrieve the suggested head routing map + * for the specified display mask. A head routing map describes the + * suggested crtc (or head) assignments for each display in the specified + * mask. + * + * Up to MAX_DISPLAYS displays may be specified in the display mask. Displays + * are numbered from zero beginning with the lowest bit position set in the + * mask. The corresponding head assignment for each of specified displays can + * then be found in the respective per-device field in the routing map. + * + * If a particular display cannot be successfully assigned a position in the + * head routing map then it is removed from the display mask. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayMask + * This parameter specifies the NV0073_DISPLAY_MASK value for which + * the head routing map is desired. Each enabled bit indicates + * a display device to include in the routing map. Enabled bits + * must represent supported displays as indicated by the + * NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED command. If a particular + * display cannot be included in the routing map then it's corresponding + * bit in the displayMask will be disabled. A return value of 0 in + * displayMask indicates that a head routing map could not be constructed + * with the given display devices. + * oldDisplayMask + * This optional parameter specifies a prior display mask to be + * used when generating the head routing map to be returned in + * headRoutingMap. Displays set in oldDisplayMask are retained + * if possible in the new routing map. + * oldHeadRoutingMap + * This optional parameter specifies a prior head routing map to be + * used when generating the new routing map to be returned in + * headRoutingMap. Head assignments in oldHeadRoutingMap are + * retained if possible in the new routing map. + * headRoutingMap + * This parameter returns the new head routing map. This parameter + * is organized into eight distinct fields, each containing the head + * assignment for the corresponding display in display mask. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_HEAD_ROUTING_MAP (0x730125U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_HEAD_ROUTING_MAP_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_HEAD_ROUTING_MAP_PARAMS_MESSAGE_ID (0x25U) + +typedef struct NV0073_CTRL_SYSTEM_GET_HEAD_ROUTING_MAP_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayMask; + NvU32 oldDisplayMask; + NvU32 oldHeadRoutingMap; + NvU32 headRoutingMap; +} NV0073_CTRL_SYSTEM_GET_HEAD_ROUTING_MAP_PARAMS; + +/* maximum number of allowed displays in a routing map */ +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_MAX_DISPLAYS (8U) + +/* per-display head assignments in a routing map */ +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY0 3:0 +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY1 7:4 +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY2 11:8 +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY3 15:12 +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY4 19:16 +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY5 23:20 +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY6 27:24 +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY7 31:28 + + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_ACTIVE + * + * This command returns the active display ID for the specified head + * on the specified subdevice. The active display may be established + * at system boot by low-level software and can then be later modified + * by an NV client using a user display class instance (see + * NV15_VIDEO_LUT_CURSOR_DAC). + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * head + * This parameter specifies the head for which the active display + * should be retrieved. This value must be between zero and the + * maximum number of heads supported by the subdevice. + * flags + * This parameter specifies optional flags to be used to while retrieving + * the active display information. + * Possible valid flags are: + * NV0073_CTRL_SYSTEM_GET_ACTIVE_FLAGS_CLIENT + * This flag is used to limit the search for the active display to + * that established by an NV client. If this flag is not specified, + * then any active display is returned (setup at system boot by + * low-level software or later by an NV client). + * displayId + * This parameter returns the displayId of the active display. A value + * of zero indicates no display is active. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_ACTIVE (0x730126U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS_MESSAGE_ID (0x26U) + +typedef struct NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvU32 flags; + NvU32 displayId; +} NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS; + +/* valid get active flags */ +#define NV0073_CTRL_SYSTEM_GET_ACTIVE_FLAGS_CLIENT 0:0 +#define NV0073_CTRL_SYSTEM_GET_ACTIVE_FLAGS_CLIENT_DISABLE (0x00000000U) +#define NV0073_CTRL_SYSTEM_GET_ACTIVE_FLAGS_CLIENT_ENABLE (0x00000001U) + + + +/* + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP + * + * This structure defines the mapping between the RM's displayId and the + * defined ACPI IDs for each display. + * displayId + * This parameter is a handle to a single display output path from the + * GPU pins to the display connector. Each display ID is defined by one bit. + * A zero in this parameter indicates a skip entry. + * acpiId + * This parameter defines the corresponding ACPI ID of the displayId. + * flags + * This parameter specifies optional flags that describe the association + * between the display ID and the ACPI ID. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN + * This field describes where the ACPI was found. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_RM + * The ACPI ID was generated by RM code. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_DOD + * The ACPI ID was found via the ACPI _DOD call. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_CLIENT + * The ACPI ID was generated by RM Client and sent to RM. Note this + * must be set on a NV0073_CTRL_CMD_SYSTEM_SET_ACPI_ID_MAP call. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_UNDOCKED + * This flag explains that the ACPI ID is only valid when the system + * is undocked. If this flag is not set, the ACPI ID is valid always. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_DOCKED + * This flag explains that the ACPI ID is only valid when the system + * is docked. If this flag is not set, the ACPI ID is valid always. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_BIOS_DETECT + * This flag is set only if the _DOD returns that the device can be + * detected by the system BIOS. This flag is copied directly from + * the ACPI spec. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_NON_VGA_OUTPUT + * This flag is set only if the _DOD returns that the device is + * a non-VGA device whose power is related to the VGA device. + * i.e. TV tuner, DVD decoder, Video capture. This flag is copied + * directly from the ACPI spec. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_MULTIHEAD_ID + * This value is set only if the _DOD returns it. The number + * indicates the head output of a multi-head device. This has no + * relation to the term, Head, currently used in the RM today. + * This is strictly a copy of the value directly from the ACPI spec. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_SCHEME + * This flag is set only if the _DOD returns that the acpiID follows + * the ACPI 3.0 spec. This flag is copied directly from + * the ACPI spec. + * + */ + +typedef struct NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS { + NvU32 displayId; + NvU32 acpiId; + NvU32 flags; +} NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS; + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN 1:0 +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_RM 0x00000000U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_DOD 0x00000001U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_CLIENT 0x00000002U + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_UNDOCKED 2:2 +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_UNDOCKED_FALSE 0x00000000U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_UNDOCKED_TRUE 0x00000001U + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_DOCKED 3:3 +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_DOCKED_FALSE 0x00000000U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_DOCKED_TRUE 0x00000001U + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_BIOS_DETECT 16:16 +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_BIOS_DETECT_FALSE 0x00000000U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_BIOS_DETECT_TRUE 0x00000001U + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_NON_VGA_OUTPUT 17:17 +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_NON_VGA_OUTPUT_FALSE 0x00000000U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_NON_VGA_OUTPUT_TRUE 0x00000001U + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_MULTIHEAD_ID 20:18 + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_SCHEME 31:31 +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_SCHEME_VENDOR 0x00000000U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_SCHEME_30 0x00000001U + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS (16U) + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_ACPI_ID_MAP + * + * This command retrieves the mapping between the RM's displayId and the + * defined ACPI IDs for each display. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and + * the total number of subdevices within the parent device. It should + * be set to zero for default behavior. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS + * An array of display ID to ACPI ids with flags for each description. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * Only returned if subdeviceInstance was not valid. + */ + +#define NV0073_CTRL_CMD_SYSTEM_GET_ACPI_ID_MAP (0x73015aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS_MESSAGE_ID" */ + + +#define NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS_MESSAGE_ID (0x5AU) + +typedef struct NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS { + NvU32 subDeviceInstance; + NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS acpiIdMap[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS]; +} NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_INTERNAL_DISPLAYS + * + * This command returns the set of internal (safe) display IDs for the specified + * subdevice in the form of a 32bit display mask. Safe means the displays do + * not require copy protection as they are on the motherboard. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * internalDisplaysMask + * This parameter returns a NV0073_DISPLAY_MASK value describing the set + * of displays that are internal (safe) and which do not require copy + * protection schemes. + * availableInternalDisplaysMask + * This parameter returns a NV0073_DISPLAY_MASK value describing the set + * of displays that are internal and available for use. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_INTERNAL_DISPLAYS (0x73015bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS_MESSAGE_ID (0x5BU) + +typedef struct NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS { + NvU32 subDeviceInstance; + NvU32 internalDisplaysMask; + NvU32 availableInternalDisplaysMask; +} NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS; + + + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_BOOT_DISPLAYS + * + * This command returns a mask of boot display IDs. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * bootDisplayMask + * This parameter returns the mask of boot display IDs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_BOOT_DISPLAYS (0x730166U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS_MESSAGE_ID (0x66U) + +typedef struct NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS { + NvU32 subDeviceInstance; + NvU32 bootDisplayMask; +} NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS; + + + +/* + * NV0073_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD + * + * This command is used to execute general MXM ACPI methods. + * + * method + * This parameter identifies the MXM ACPI API to be invoked. + * Valid values for this parameter are: + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMI + * This value specifies that the MXMI API is to invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMS + * This value specifies that the MXMS API is to invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX + * This value specifies that the MXMX API is to invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUON + * This value specifies that the Hybrid GPU ON API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUOFF + * This value specifies that the Hybrid GPU OFF API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUSTA + * This value specifies that the Hybrid GPU STA API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS + * This value specifies that the Hybrid GPU MXDS API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX + * This value specifies that the Hybrid GPU MXMX API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS + * This value specifies that the Hybrid GPU DOS API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_ROM + * This value specifies that the Hybrid GPU ROM API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOD + * This value specifies that the Hybrid GPU DOD API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_SUPPORT + * This value specifies that the Hybrid GPU DSM subfunction SUPPORT + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HYBRIDCAPS + * This value specifies that the Hybrid GPU DSM subfunction SUPPORT + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POLICYSELECT + * This value specifies that the Hybrid GPU DSM subfunction POLICYSELECT + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POWERCONTROL + * This value specifies that the Hybrid GPU DSM subfunction POWERCONTROL + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_PLATPOLICY + * This value specifies that the Hybrid GPU DSM subfunction PLATPOLICY + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_DISPLAYSTATUS + * This value specifies that the Hybrid GPU DSM subfunction DISPLAYSTATUS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MDTL + * This value specifies that the Hybrid GPU DSM subfunction MDTL + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBLIST + * This value specifies that the Hybrid GPU DSM subfunction HCSMBLIST + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBADDR + * This value specifies that the Hybrid GPU DSM subfunction HCSMBADDR + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCREADBYTE + * This value specifies that the Hybrid GPU DSM subfunction HCREADBYTE + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSENDBYTE + * This value specifies that the Hybrid GPU DSM subfunction HCSENDBYTES + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETSTATUS + * This value specifies that the Hybrid GPU DSM subfunction HCGETSTATUS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCTRIGDDC + * This value specifies that the Hybrid GPU DSM subfunction HCTRIGDDC + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETDDC + * This value specifies that the Hybrid GPU DSM subfunction HCGETDDC + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DCS + * This value specifies that the Hybrid GPU DCS API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXSS + * This value specifies that the DSM MXM subfunction MXSS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMI + * This value specifies that the DSM MXM subfunction MXMI + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMS + * This value specifies that the DSM MXM subfunction MXMS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXPP + * This value specifies that the DSM MXM subfunction MXPP + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXDP + * This value specifies that the DSM MXM subfunction MXDP + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MDTL + * This value specifies that the DSM MXM subfunction MDTL + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXCB + * This value specifies that the DSM MXM subfunction MXCB + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_REMAPFUNC + * This value specifies the DSM generic remapping should return function + * and subfunction when this API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_HYBRIDCAPS + * This value specifies that the generic DSM subfunction HYBRIDCAPS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_POLICYSELECT + * This value specifies that the generic DSM subfunction POLICYSELECT + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_PLATPOLICY + * This value specifies that the generic DSM subfunction PLATPOLICY + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_DISPLAYSTATUS + * This value specifies that the generic DSM subfunction DISPLAYSTATUS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_MDTL + * This value specifies that the generic DSM subfunction MDTL + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETOBJBYTYPE + * This value specifies that the generic DSM subfunction GETOBJBYTYPE + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETALLOBJS + * This value specifies that the generic DSM subfunction GETALLOBJS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETEVENTLIST + * This value specifies that the generic DSM subfunction GETEVENTLIST + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETBACKLIGHT + * This value specifies that the generic DSM subfunction GETBACKLIGHT + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_TESTSUBFUNCENABLED + * This value specifies the testIfDsmSubFunctionEnabled test should + * be done for the func/subfunction when this API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_GETSUPPORTEDFUNC + * This value specifies the list of supported generic dsm functions + * should be returned. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS + * This value specifies that the DSM NVOP subfunction OPTIMUSCAPS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG + * This value specifies that the DSM NVOP subfunction OPTIMUSFLAG + * API is to be invoked. This API will set a Flag in sbios to Indicate + * that HD Audio Controller is disable/Enabled from GPU Config space. + * This flag will be used by sbios to restore Audio state after resuming + * from s3/s4. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_WMMX_NVOP_GPUON + * This value specifies that the WMMX (WMI-ACPI) GPON methods has to be invoked + * this call should happen below DPC level from any client. + * inData + * This parameter specifies the method-specific input buffer. Data is + * passed to the specified API using this buffer. For display related + * APIs the associated display mask can be found at a byte offset within + * the inData buffer using the following method-specific values: + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX_DISP_MASK_OFFSET + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS_DISP_MASK_OFFSET + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX_DISP_MASK_OFFSET + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS_DISP_MASK_OFFSET + * inDataSize + * This parameter specifies the size of the inData buffer in bytes. + * outStatus + * This parameter returns the status code from the associated ACPI call. + * outData + * This parameter specifies the method-specific output buffer. Data + * is returned by the specified API using this buffer. + * outDataSize + * This parameter specifies the size of the outData buffer in bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD (0x730168U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID (0x68U) + +typedef struct NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS { + NvU32 method; + NV_DECLARE_ALIGNED(NvP64 inData, 8); + NvU16 inDataSize; + NvU32 outStatus; + NV_DECLARE_ALIGNED(NvP64 outData, 8); + NvU16 outDataSize; +} NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS; + + +/* valid method parameter values */ +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX (0x00000002U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX_DISP_MASK_OFFSET (0x00000001U) + +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUON (0x00000003U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUOFF (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUSTA (0x00000005U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS (0x00000006U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX (0x00000007U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS (0x00000008U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_ROM (0x00000009U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOD (0x0000000aU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_SUPPORT (0x0000000bU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HYBRIDCAPS (0x0000000cU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POLICYSELECT (0x0000000dU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POWERCONTROL (0x0000000eU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_PLATPOLICY (0x0000000fU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_DISPLAYSTATUS (0x00000010U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MDTL (0x00000011U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBLIST (0x00000012U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBADDR (0x00000013U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCREADBYTE (0x00000014U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSENDBYTE (0x00000015U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETSTATUS (0x00000016U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCTRIGDDC (0x00000017U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETDDC (0x00000018U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DCS (0x00000019U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXSS (0x0000001aU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMI (0x0000001bU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMS (0x0000001cU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXPP (0x0000001dU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXDP (0x0000001eU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MDTL (0x0000001fU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXCB (0x00000020U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_GETEVENTLIST (0x00000021U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETMEMTABLE (0x00000022U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETMEMCFG (0x00000023U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETOBJBYTYPE (0x00000024U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETALLOBJS (0x00000025U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_REMAPFUNC (0x00000026U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_DISPLAYSTATUS (0x0000002aU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_MDTL (0x0000002bU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETOBJBYTYPE (0x0000002cU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETALLOBJS (0x0000002dU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETEVENTLIST (0x0000002eU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETBACKLIGHT (0x0000002fU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_TESTSUBFUNCENABLED (0x00000030U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_GETSUPPORTEDFUNC (0x00000031U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS (0x00000032U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_WMMX_NVOP_GPUON (0x00000033U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG (0x00000034U) + + +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETCALLBACKS (0x00000036U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_SUPPORTFUNCS (0x00000037U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_PLATCAPS (0x00000038U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_PLATPOLICY (0x00000039U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_MSTL (0x0000003aU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVGPS_FUNC_SUPPORT (0x0000003bU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDS (0x0000003cU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDM (0x0000003dU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXID (0x0000003eU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_LRST (0x0000003fU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DDC_EDID (0x00000040U) + +/* valid input buffer offset values */ +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDS_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDM_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXID_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_LRST_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DDC_EDID_DISP_MASK_OFFSET (0x00000004U) + + + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_UNPLUG_STATE + * + * This command can be used to retrieve hotplug and unplug state + * information that are currently recorded by the RM. This information is + * used by the client to determine which displays to detect after a + * hotplug event occurs. Or if the client knows that this device generates + * a hot plug/unplug signal on all connectors, then this can be used to call + * displays from detection. The displayIds on which hotplug/unplug has + * happened will be reported only ONCE to the client. That is if the call + * is done multiple times for the same event update, then for consequent + * calls the display mask will be reported as 0. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * flags + * This parameter specifies optional flags to be used while retrieving + * the hotplug state information. + * Here are the current defined fields: + * NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID + * A client uses this field to determine the lid state. + * Possible values are: + * NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID_OPEN + * The lid is open. + * NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID_CLOSED + * The lid is closed. The client should remove devices a + * reported inside the + * NV0073_CTRL_SYSTEM_GET_CONNECT_POLICY_PARAMS.lidClosedMask. + * hotPlugMask + * This display mask specifies an NV0073_DISPLAY_MASK value describing + * the set of displays that have seen a hotplug. + * hotUnplugMask + * This display mask specifies an NV0073_DISPLAY_MASK value describing + * the set of displays that have seen a hot unplug + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_UNPLUG_STATE (0x73017bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | 0x7B" */ + +typedef struct NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS { + NvU32 subDeviceInstance; + NvU32 flags; + NvU32 hotPlugMask; + NvU32 hotUnplugMask; +} NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS; + +/* valid get hoplug state flags */ +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_FLAGS_LID 0:0 +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_FLAGS_LID_OPEN (0x00000000U) +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_FLAGS_LID_CLOSED (0x00000001U) + +/* + * NV0073_CTRL_CMD_SYSTEM_CLEAR_ELV_BLOCK + * + * This command instructs the RM to explicitly clear any + * ELV block. Clients should call this before attempting core-channel + * updates when in VRR one-shot mode. ELV block mode will be + * properly restored to its appropriate setting based on the stall-lock + * in Supervisor3 after the core channel update + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * displayId + * The public ID of the Output Display which is to be used for VRR. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ + +#define NV0073_CTRL_CMD_SYSTEM_CLEAR_ELV_BLOCK (0x73017dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS_MESSAGE_ID (0x7DU) + +typedef struct NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; +} NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR + * + * This command arms the display modeset supervisor to operate in + * a lightweight mode. By calling this, the client is implicitly + * promising not to make any changes in the next modeset that require + * the full supervisor. After SV3, the LWSV will disarm and any subsequent + * modesets will revert to full supervisors. This must be called separately + * for every display that will be part of the modeset. + * It is recommended that the client explicitly disarm the lightweight + * supervisor after every modeset as null modesets will not trigger the + * supervisor interrupts and the RM will not be able to disarm automatically + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * displayId + * The public ID of the Output Display which is to be used for VRR. + * + * bArmLWSV + * If this is set to NV_TRUE, the RM will arm the lightweight supervisor + * for the next modeset. + * If this is set to NV_FALSE, the RM will disarm the lightweight supervisor + * + * bVrrState + * VRR state to be changed. + * + * vActive + * GPU-SRC vertical active value + * + * vfp + * GPU-SRC vertical front porch + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ + +#define NV0073_CTRL_CMD_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR (0x73017eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR_PARAMS_MESSAGE_ID (0x7EU) + +typedef struct NV0073_CTRL_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bArmLWSV; + NvBool bVrrState; + NvU32 vActive; + NvU32 vfp; +} NV0073_CTRL_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR_PARAMS; + + + +/* +* NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS +* +* This command is used to configure pstate switch parameters on VRR monitors +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed.This parameter must specify a value between zero and the +* total number of subdevices within the parent device.This parameter +* should be set to zero for default behavior. +* +* displayId +* DisplayId of the monitor being vrr configured +* +* bVrrState +* When set to NV_TRUE, signifies that the vrr is about to become active. +* When set to NV_FALSE, signifies that the vrr is about to become suspended. +* +* bVrrDirty +* When set to NV_TRUE, indicates that vrr configuration has been changed +* When set to NV_FALSE, this will indicate transitions from One shot mode to +* Continuous mode and vice versa +* +* bVrrEnabled +* When set to NV_TRUE, indicates that vrr has been enabled, i.e. vBp extended by 2 lines +* +* maxVblankExtension +* When VRR is enabled, this is the maximum amount of lines that the vblank can be extended. +* Only updated when bVrrDirty = true +* +* internalVRRHeadVblankStretch +* When VRR is enabled, this is the maximum amount of lines that the vblank can be extended. +* On NVSR and DD panels . Only updated when bVrrDirty = true +* +* minVblankExtension +* When VRR is enabled, this is the minimum amount of lines that should be present in the Vblank. The purpose is to cap the maximum refresh (currently only for HDMI 2.1 VRR compliance) +*/ +#define NV0073_CTRL_CMD_SYSTEM_CONFIG_VRR_PSTATE_SWITCH (0x730184U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS_MESSAGE_ID (0x84U) + +typedef struct NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bVrrState; + NvBool bVrrDirty; + NvBool bVrrEnabled; + NvU32 maxVblankExtension; + NvU32 internalVRRHeadVblankStretch; + NvU32 minVblankExtension; +} NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS; + + + +/* + * NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX + * + * This command is used to query the display mask of all displays + * that support dynamic display MUX. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayMask (out) + * Mask of all displays that support dynamic display MUX + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX (0x730190U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS_MESSAGE_ID (0x90U) + +typedef struct NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS { + NvU32 subDeviceInstance; + NvU32 muxDisplayMask; +} NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS; + + + +/* + * NV0073_CTRL_CMD_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH + * + * This command allocates a specified amount of ISO memory bandwidth for + * display. If the requested amount of bandwidth cannot be allocated (either + * because it exceeds the total bandwidth available to the system, or because + * too much bandwidth is already allocated to other clients), the call will + * fail and NV_ERR_INSUFFICIENT_RESOURCES will be returned. + * + * If bandwidth has already been allocated via a prior call, and a new + * allocation is requested, the new allocation will replace the old one. (If + * the new allocation fails, the old allocation remains in effect.) + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * averageBandwidthKBPS + * This parameter specifies the amount of ISO memory bandwidth requested. + * floorBandwidthKBPS + * This parameter specifies the minimum required (i.e., floor) dramclk + * frequency, multiplied by the width of the pipe over which the display + * data will travel. (It is understood that the bandwidth calculated by + * multiplying the clock frequency by the pipe width will not be + * realistically achievable, due to overhead in the memory subsystem. The + * API will not actually use the bandwidth value, except to reverse the + * calculation to get the required dramclk frequency.) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INSUFFICIENT_RESOURCES + * NV_ERR_NOT_SUPPORTED + * NV_ERR_GENERIC + */ + +#define NV0073_CTRL_CMD_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH (0x730196U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_MESSAGE_ID (0x96U) + +typedef struct NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS { + NvU32 subDeviceInstance; + NvU32 averageBandwidthKBPS; + NvU32 floorBandwidthKBPS; +} NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS; + +/* + * NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS + * + * This structure represents the hotplug event config control parameters. + * + * subDeviceInstance + * This parameter should specify the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * + * deviceMapFilter + * This parameter returns (in GET) or should specify (in SET) a device map + * indicating device(s) to sense. + * + * hotPluginSense + * This parameter returns (in GET) or should specify (in SET) a device map + * indicating device(s) plugged in that caused the most recent hotplug + * event. + * + * hotUnplugSense + * This parameter returns (in GET) or should specify (in SET) a device map + * indicating device(s) un plugged that caused the most recent hotplug + * event. + */ + +typedef struct NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS { + NvU32 subDeviceInstance; + NvU32 deviceMapFilter; + NvU32 hotPluginSense; + NvU32 hotUnplugSense; +} NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_EVENT_CONFIG + * + * This command fetches the hotplug event configuration. + * + * See @ref NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS for documentation on + * the parameters. + */ + +#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_EVENT_CONFIG (0x730197U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | 0x97" */ + +/* + * NV0073_CTRL_CMD_SYSTEM_SET_HOTPLUG_EVENT_CONFIG + * + * This command sets the hotplug event configuration. + * + * See @ref NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS for documentation on + * the parameters. + */ + +#define NV0073_CTRL_CMD_SYSTEM_SET_HOTPLUG_EVENT_CONFIG (0x730198U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | 0x98" */ + + + +/* +* NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS +* +* This command is used to read Core channel, Cursor channel, Window channel, and Head register values and encode these values with ProtoDmp. +* +* subDeviceInstance (in) +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. +* headMask (in) +* Head mask representing which register values should be encoded +* windowMask (in) +* Window channel mask whose register values should be encoded +* bRecordCoreChannel (in) +* Indicates whether or not to encode core channel register values +* bRecordCursorChannel (in) +* Indicates whether or not to encode cursor channel register values +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_ARGUMENT +* NV_ERR_NOT_SUPPORTED +*/ +#define NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS (0x73019bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS_MESSAGE_ID (0x9BU) + +typedef struct NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS { + NvU32 subDeviceInstance; + NvU32 headMask; + NvU32 windowMask; + NvBool bRecordCoreChannel; + NvBool bRecordCursorChannel; +} NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT + * + * This command is used to query the display mux status for the given + * display device + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT (0x73019cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS_MESSAGE_ID (0x9CU) + +typedef struct NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS { + NvU32 subDeviceInstance; + NvBool bIsSidebandI2cSupported; +} NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT + * + * This command is used to query if SIDEBAND SR can be used with the + * given display device. If PSR API is supported on the system, + * then sideband SR support is set to false. + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation + * should be directed. + * displayId (in) + * This parameter inputs the displayId of the active display. A value + * of zero indicates no display is active. + * bIsSidebandSrSupported + * If it is true, it means that sideband is supported and not PSR API. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT (0x73019dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS_MESSAGE_ID (0x9DU) + +typedef struct NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bIsSidebandSrSupported; +} NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS; + +/* _ctrl0073system_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080.h new file mode 100644 index 0000000..238c0d6 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080.finn +// + + + + +#include "ctrl0080/ctrl0080bif.h" +#include "ctrl0080/ctrl0080gpu.h" +#include "ctrl0080/ctrl0080clk.h" +#include "ctrl0080/ctrl0080dma.h" +#include "ctrl0080/ctrl0080gr.h" +#include "ctrl0080/ctrl0080cipher.h" +#include "ctrl0080/ctrl0080fb.h" +#include "ctrl0080/ctrl0080fifo.h" +#include "ctrl0080/ctrl0080host.h" + + +#include "ctrl0080/ctrl0080perf.h" +#include "ctrl0080/ctrl0080msenc.h" +#include "ctrl0080/ctrl0080bsp.h" +#include "ctrl0080/ctrl0080rc.h" +#include "ctrl0080/ctrl0080nvjpg.h" +#include "ctrl0080/ctrl0080unix.h" +#include "ctrl0080/ctrl0080internal.h" diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h new file mode 100644 index 0000000..4b20dc1 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h @@ -0,0 +1,73 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080base.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV01_DEVICE_XX/NV03_DEVICE control commands and parameters */ + +#define NV0080_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0080, NV0080_CTRL_##cat, idx) + +/* GPU device command categories (6bits) */ +#define NV0080_CTRL_RESERVED (0x00) +#define NV0080_CTRL_BIF (0x01) +#define NV0080_CTRL_GPU (0x02) +#define NV0080_CTRL_CLK (0x10) +#define NV0080_CTRL_GR (0x11) +#define NV0080_CTRL_CIPHER (0x12) +#define NV0080_CTRL_FB (0x13) +#define NV0080_CTRL_HOST (0x14) +#define NV0080_CTRL_VIDEO (0x15) +#define NV0080_CTRL_FIFO (0x17) +#define NV0080_CTRL_DMA (0x18) +#define NV0080_CTRL_PERF (0x19) +#define NV0080_CTRL_PERF_LEGACY_NON_PRIVILEGED (0x99) /* finn: Evaluated from "(NV0080_CTRL_PERF | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV0080_CTRL_MSENC (0x1B) +#define NV0080_CTRL_BSP (0x1C) +#define NV0080_CTRL_RC (0x1D) +#define NV0080_CTRL_OS_UNIX (0x1E) +#define NV0080_CTRL_NVJPG (0x1F) +#define NV0080_CTRL_INTERNAL (0x20) +#define NV0080_CTRL_NVLINK (0x21) + +/* + * NV0080_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0080_CTRL_CMD_NULL (0x800000) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrl0080base_h_ */ + +/* extract device cap setting from specified category-specific caps table */ +#define NV0080_CTRL_GET_CAP(cat,tbl,c) \ + NV0080_CTRL_##cat##_GET_CAP(tbl, NV0080_CTRL_##cat##_CAPS_##c) diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h new file mode 100644 index 0000000..05a18bf --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h @@ -0,0 +1,138 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080bif.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* + * NV0080_CTRL_CMD_BIF_RESET + * + * This command initiates the specified reset type on the GPU. + * + * flags + * Specifies various arguments to the reset operation. + * + * Supported fields include: + * + * NV0080_CTRL_BIF_RESET_FLAGS_TYPE + * When set to _SW_RESET, a SW (fullchip) reset is performed. When set + * to _SBR, a secondary-bus reset is performed. When set to + * _FUNDAMENTAL, a fundamental reset is performed. + * + * NOTE: _FUNDAMENTAL is not yet supported. + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0080_CTRL_CMD_BIF_RESET (0x800102) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_RESET_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_BIF_RESET_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_BIF_RESET_PARAMS { + NvU32 flags; +} NV0080_CTRL_BIF_RESET_PARAMS; + +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE 2:0 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SW_RESET (0x00000001) +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SBR (0x00000002) +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_FUNDAMENTAL (0x00000003) + +/* + * NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR + * + * baseDmaSysmemAddr + * This parameter represents the base DMA address for sysmem which will be + * added to all DMA accesses issued by GPU. Currently GPUs do not support 64-bit physical address, + * hence if sysmem is greater than max GPU supported physical address width, this address + * will be non-zero + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_PARENT + */ + +#define NV0080_CTRL_CMD_BIF_GET_DMA_BASE_SYSMEM_ADDR (0x800103) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS { + NV_DECLARE_ALIGNED(NvU64 baseDmaSysmemAddr, 8); +} NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS; + +/* + * NV0080_CTRL_BIF_SET_ASPM_FEATURE + * + * aspmFeatureSupported + * ASPM feature override by client + * + * Possible status values returned are: + * NV_OK + */ + +#define NV0080_CTRL_CMD_BIF_SET_ASPM_FEATURE (0x800104) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS { + NvU32 aspmFeatureSupported; +} NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS; + +#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S 0:0 +#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_ENABLED 0x000000001 +#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_DISABLED 0x000000000 +#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1 1:1 +#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_ENABLED 0x000000001 +#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_DISABLED 0x000000000 + +/* + * NV0080_CTRL_BIF_ASPM_CYA_UPDATE + * + * bL0sEnable + * bL1Enable + * ASPM CYA update by client + * + * Possible status values returned are: + * NV_OK + */ + +#define NV0080_CTRL_CMD_BIF_ASPM_CYA_UPDATE (0x800105) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS { + NvBool bL0sEnable; + NvBool bL1Enable; +} NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS; + +/* _ctrl0080bif_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h new file mode 100644 index 0000000..d4911f5 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h @@ -0,0 +1,112 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080bsp.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE bit stream processor control commands and parameters */ + +/* + * NV0080_CTRL_CMD_BSP_GET_CAPS + * + * This command returns the set of BSP capabilities for the device + * in the form of an array of unsigned bytes. BSP capabilities + * include supported features and required workarounds for the decoder + * within the device, each represented by a byte offset into the + * table and a bit position within that byte. + * + * capsTblSize + * This parameter specifies the size in bytes of the caps table. + * This value should be set to NV0080_CTRL_BSP_CAPS_TBL_SIZE. + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the BSP caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + * instanceId + * This parameter specifies the instance Id of NVDEC for which + * cap bits are requested. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0080_CTRL_CMD_BSP_GET_CAPS (0x801c01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BSP_INTERFACE_ID << 8) | NV0080_CTRL_BSP_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_BSP_GET_CAPS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0080_CTRL_BSP_GET_CAPS_PARAMS { + NvU32 capsTblSize; + NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); + NvU32 instanceId; +} NV0080_CTRL_BSP_GET_CAPS_PARAMS; + + + +/* + * Size in bytes of bsp caps table. This value should be one greater + * than the largest byte_index value above. + */ +#define NV0080_CTRL_BSP_CAPS_TBL_SIZE 8 + +/* + * NV0080_CTRL_CMD_BSP_GET_CAPS_V2 + * + * This command returns the set of BSP capabilities for the device + * in the form of an array of unsigned bytes. BSP capabilities + * include supported features and required workarounds for the decoder + * within the device, each represented by a byte offset into the + * table and a bit position within that byte. + * (The V2 version flattens the capsTbl array pointer). + * + * capsTbl + * This parameter is an array of unsigned bytes where the BSP caps bits + * will be transferred by the RM. + * instanceId + * This parameter specifies the instance Id of NVDEC for which + * cap bits are requested. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0080_CTRL_CMD_BSP_GET_CAPS_V2 (0x801c02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BSP_INTERFACE_ID << 8) | NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2_MESSAGE_ID" */ + +#define NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2 { + NvU8 capsTbl[NV0080_CTRL_BSP_CAPS_TBL_SIZE]; + NvU32 instanceId; +} NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2; + +/* _ctrl0080bsp_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080cipher.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080cipher.h new file mode 100644 index 0000000..279151b --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080cipher.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080cipher.finn +// + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080clk.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080clk.h new file mode 100644 index 0000000..de61930 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080clk.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080clk.finn +// + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h new file mode 100644 index 0000000..b209ca2 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h @@ -0,0 +1,908 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080dma.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE dma control commands and parameters */ + +/* + * NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK + * + * This parameter returns the parameters specific to a PTE as follows: + * pageSize + * GET: This parameter returns the page size of the PTE information + * being returned. If 0, then this pteBlock[] array entry is + * invalid or not used. (pteBlock[0] is always used.) + * SET: This parameter specifies the page size of the PTE information + * to be set. If 0, then this pteBlock[] array entry is invalid + * or not used. (pteBlock[0] is always used.) + * pteEntrySize + * GET: This parameter returns the size of the PTE in bytes for this GPU. + * SET: N/A + * comptagLine + * GET: This parameter returns the comptagline field of the corresponding PTE. + * SET: This parameter sets the comptagline field of the corresponding PTE. + * Incorrect values may lead to dire consequences. + * kind + * GET: This parameter returns the kind field of the corresponding PTE. + * SET: This parameter sets the kind field of the corresponding PTE. + * Incorrect values may lead to undesirable consequences. + * pteFlags + * This parameter returns various fields from the PTE, these are: + * FLAGS_VALID: + * GET: This flag returns the valid bit of the PTE. + * SET: This flag sets the valid bit of the PTE. + * FLAGS_ENCRYPTED: + * GET: This flag returns the encrypted bit of the PTE. Not all GPUs + * support encryption. If not supported, this flag will be set to + * NOT_SUPPORTED. + * SET: This flag sets the encrypted bit of the PTE. + * FLAGS_APERTURE: + * GET: This flag returns the aperture field of the PTE. See + * NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_FLAGS_APERTURE_* for values. + * SET: This flag sets the aperture field of the PTE. See + * NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_FLAGS_APERTURE_* for values. + * FLAGS_COMPTAGS: + * GET: This flag returns the comptags field of the PTE. (Not used on Fermi) + * SET: N/A + * FLAGS_GPU_CACHED: + * GET: This flag returns the GPU cacheable bit of the PTE. GPU caching of + * sysmem was added in iGT21a and Fermi. If not supported, this flag + * will be set to NOT_SUPPORTED. + * SET: N/A for specific chips, e.g., GF100 + * FLAGS_SHADER_ACCESS: + * GET: This flag returns the shader access control of the PTE. This feature + * was introduced in Kepler. If not supported, this flag will be set to + * NOT_SUPPORTED. + * SET: N/A + */ + +typedef struct NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK { + NvU32 pageSize; + NV_DECLARE_ALIGNED(NvU64 pteEntrySize, 8); + NvU32 comptagLine; + NvU32 kind; + NvU32 pteFlags; +} NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK; + +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID 0:0 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_TRUE (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED 2:1 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_TRUE (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_NOT_SUPPORTED (0x00000002U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE 6:3 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_VIDEO_MEMORY (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_PEER_MEMORY (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_COHERENT_MEMORY (0x00000002U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_NON_COHERENT_MEMORY (0x00000003U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS 10:7 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_NONE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_1 (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_2 (0x00000002U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_4 (0x00000004U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED 12:11 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_TRUE (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_NOT_SUPPORTED (0x00000002U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS 14:13 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_WRITE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_ONLY (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_WRITE_ONLY (0x00000002U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_NOT_SUPPORTED (0x00000003U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY 15:15 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_TRUE (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC 16:16 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_DISABLE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_ENABLE (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING 17:17 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_DISABLE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_ENABLE (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED 18:18 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_TRUE (0x00000001U) + +/* + * NV0080_CTRL_DMA_GET_PTE_INFO + * + * This command queries PTE information for the specified GPU virtual address. + * + * gpuAddr + * This parameter specifies the GPU virtual address for which PTE + * information is to be returned. + * skipVASpaceInit + * This parameter specifies(true/false) whether the VA Space + * initialization should be skipped in this ctrl call. + * pteBlocks + * This parameter returns the page size-specific attributes of a PTE. + * Please see NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK. + * hVASpace + * handle for the allocated VA space that this control call should operate + * on. If it's 0, it assumes to use the implicit allocated VA space. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + * NV_ERR_GENERIC + */ + +#define NV0080_CTRL_CMD_DMA_GET_PTE_INFO (0x801801U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS 4U + +#define NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 gpuAddr, 8); + NvU32 subDeviceId; + NvU8 skipVASpaceInit; + NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK pteBlocks[NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS], 8); + NvHandle hVASpace; +} NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS; + +/* + * NV0080_CTRL_DMA_SET_PTE_INFO + * + * This command sets PTE information for the specified GPU virtual address. + * Usage of parameter and field definitions is identical to that of + * NV0080_CTRL_DMA_GET_PTE_INFO, with the following exception: + * + * - pteFlags field NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS is ignored, + * as this setting is specified via the kind specification. + * - pteEntrySize is ignored, as this setting is read-only in the GET case. + * - hVASpace + * handle for the allocated VA space that this control call should operate + * on. If it's 0, it assumes to use the implicit allocated VA space. + * + */ + +#define NV0080_CTRL_CMD_DMA_SET_PTE_INFO (0x80180aU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS 4U + +#define NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 gpuAddr, 8); + NvU32 subDeviceId; + NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK pteBlocks[NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS], 8); + NvHandle hVASpace; +} NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS; + + +#define NV0080_CTRL_CMD_DMA_FILL_PTE_MEM (0x801802U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS { + NvU32 pageCount; + struct { + NvHandle hClient; + NvHandle hDevice; + NvHandle hMemory; + NvU32 subDeviceId; + } hwResource; + struct { + NvU32 fbKind; + NvU32 sysKind; + NvU32 compTagStartOffset; + } comprInfo; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 gpuAddr, 8); + NV_DECLARE_ALIGNED(NvP64 pageArray, 8); + NV_DECLARE_ALIGNED(NvP64 pteMem, 8); + NvU32 pteMemPfn; + NvU32 pageSize; + NvU32 startPageIndex; + NvU32 flags; + NvHandle hSrcVASpace; + NvHandle hTgtVASpace; + NvU32 peerId; +} NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS; + + + +/* + * NV0080_CTRL_DMA_FLUSH + * + * This command flushes the specified target unit + * + * targetUnit + * The unit to flush, either L2 cache or compression tag cache. + * This field is a logical OR of the individual fields such as + * L2 cache or compression tag cache. Also L2 invalidation for + * either SYSMEM/PEERMEM is triggered. But this invalidation is + * for FERMI. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + * + * See Also: + * NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE + * Flushes the entire GPU cache or a set of physical addresses (if the + * hardware supports it). Use this call if you want to flush a set of + * addresses or the entire GPU cache in unicast mode. + * NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE + * Flushes memory associated with a single allocation if the hardware + * supports it. Use this call if you want to flush a single allocation and + * you have a memory object describing the physical memory. + */ +#define NV0080_CTRL_CMD_DMA_FLUSH (0x801805U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_FLUSH_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_FLUSH_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0080_CTRL_DMA_FLUSH_PARAMS { + NvU32 targetUnit; +} NV0080_CTRL_DMA_FLUSH_PARAMS; + +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2 0:0 +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_DISABLE (0x00000000U) +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_ENABLE (0x00000001U) +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG 1:1 +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_DISABLE (0x00000000U) +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_ENABLE (0x00000001U) +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB 2:2 +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_DISABLE (0x00000000U) +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_ENABLE (0x00000001U) + +// This is exclusively for Fermi +// The selection of non-zero valued bit-fields avoids the routing +// into the above cases and vice-versa +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE 4:3 +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_SYSMEM (0x00000001U) +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_PEERMEM (0x00000002U) + + +/** + * NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS + * + * This command returns information about the VA caps on the GPU + * + * vaBitCount + * Returns number of bits in a virtual address + * pdeCoverageBitCount + * Returns number of VA bits covered in each PDE. One PDE covers + * 2^pdeCoverageBitCount bytes. + * + * bigPageSize + * Size of the big page + * compressionPageSize + * Size of region each compression tag covers + * dualPageTableSupported + * TRUE if one page table can map with both 4KB and big pages + * + * numPageTableFormats + * Returns the number of different page table sizes supported by the RM + * pageTableBigFormat + * pageTable4KFormat[] + * Returns size in bytes and number of VA bits covered by each page table + * format. Up to MAX_NUM_PAGE_TABLE_FORMATS can be returned. The most + * compact format will be pageTableSize[0] and the least compact format + * will be last. + * hVASpace + * handle for the allocated VA space that this control call should operate + * on. If it's 0, it assumes to use the implicit allocated VA space. + * vaRangeLo + * Indicates the start of usable VA range. + * + * hugePageSize + * Size of the huge page if supported, 0 otherwise. + * + * vaSpaceId + * Virtual Address Space id assigned by RM. + * Only relevant on AMODEL. + * + * pageSize512MB + * Size of the 512MB page if supported, 0 otherwise. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS (0x801806U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_MESSAGE_ID" */ + +typedef struct NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT { + NvU32 pageTableSize; + NvU32 pageTableCoverage; +} NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT; + +#define NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS (16U) +#define NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS { + NvU32 vaBitCount; + NvU32 pdeCoverageBitCount; + NvU32 num4KPageTableFormats; + NvU32 bigPageSize; + NvU32 compressionPageSize; + NvU32 dualPageTableSupported; + NvU32 idealVRAMPageSize; + NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT pageTableBigFormat; + NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT pageTable4KFormat[NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS]; + NvHandle hVASpace; + NV_DECLARE_ALIGNED(NvU64 vaRangeLo, 8); + NvU32 hugePageSize; + NvU32 vaSpaceId; + NvU32 pageSize512MB; +} NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS; + +/* + * Adding a version define to allow clients to access valid + * parameters based on version. + */ +#define NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS_WITH_VA_RANGE_LO 0x1U + +/* + * NV0080_CTRL_DMA_GET_PDE_INFO + * + * This command queries PDE information for the specified GPU virtual address. + * + * gpuAddr + * This parameter specifies the GPU virtual address for which PDE + * information is to be returned. + * pdeVirtAddr + * This parameter returns the GPU virtual address of the PDE. + * pdeEntrySize + * This parameter returns the size of the PDE in bytes for this GPU. + * pdeAddrSpace + * This parameter returns the GPU address space of the PDE. + * pdeSize + * This parameter returns the fractional size of the page table(s) as + * actually set in the PDE, FULL, 1/2, 1/4 or 1/8. (This amount may + * differ from that derived from pdeVASpaceSize.) Intended for VERIF only. + * pteBlocks + * This parameter returns the page size-specific parameters as follows: + * ptePhysAddr + * This parameter returns the GPU physical address of the page table. + * pteCacheAttrib + * This parameter returns the caching attribute of the + * GPU physical address of the page table. + * pteEntrySize + * This parameter returns the size of the PTE in bytes for this GPU. + * pageSize + * This parameter returns the page size of the page table. + * If pageSize == 0, then this PTE block is not valid. + * pteAddrSpace + * This parameter returns the GPU address space of the page table. + * pdeVASpaceSize + * This parameter returns the size of the VA space addressable by + * the page table if fully used (i.e., if all PTEs marked VALID). + * pdbAddr + * This parameter returns the PDB address for the PDE. + * hVASpace + * handle for the allocated VA space that this control call should operate + * on. If it's 0, it assumes to use the implicit allocated VA space. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV0080_CTRL_CMD_DMA_GET_PDE_INFO (0x801809U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_MESSAGE_ID" */ + +typedef struct NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK { + NV_DECLARE_ALIGNED(NvU64 ptePhysAddr, 8); + NvU32 pteCacheAttrib; + NvU32 pteEntrySize; + NvU32 pageSize; + NvU32 pteAddrSpace; + NvU32 pdeVASpaceSize; + NvU32 pdeFlags; +} NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK; + +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_VIDEO_MEMORY (0x00000000U) +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY (0x00000001U) +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY (0x00000002U) + +#define NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS 4U + +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 gpuAddr, 8); + NV_DECLARE_ALIGNED(NvU64 pdeVirtAddr, 8); + NvU32 pdeEntrySize; + NvU32 pdeAddrSpace; + NvU32 pdeSize; + NvU32 subDeviceId; + NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK pteBlocks[NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS], 8); + NV_DECLARE_ALIGNED(NvU64 pdbAddr, 8); + NvHandle hVASpace; +} NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS; + +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_VIDEO_MEMORY (0x00000000U) +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY (0x00000001U) +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY (0x00000002U) +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_FULL 1U +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_HALF 2U +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_QUARTER 3U +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_EIGHTH 4U + +/* + * NV0080_CTRL_CMD_DMA_INVALIDATE_PDB_TARGET + * + * This command invalidates PDB target setting in hardware. + * After execeution of this command PDB target would be in undefined state. + * + * Returns error if the PDB target can not be invalidate. + * + * This call is only supported on chips fermi and later chips. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0080_CTRL_CMD_DMA_INVALIDATE_PDB_TARGET (0x80180bU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | 0xB" */ + +/* + * NV0080_CTRL_CMD_DMA_INVALIDATE_TLB + * + * This command invalidates the GPU TLB. This is intended to be used + * for RM clients that manage their own TLB consistency when updating + * page tables on their own, or with DEFER_TLB_INVALIDATION options + * to other RM APIs. + * + * hVASpace + * This parameter specifies the VASpace object whose MMU TLB entries + * needs to be invalidated, if the flag is set to NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_FALSE. + * Specifying a GMMU VASpace object handle will invalidate the GMMU TLB for the particular VASpace. + * Specifying a SMMU VASpace object handle will flush the entire SMMU TLB & PTC. + * + * flags + * This parameter can be used to specify any flags needed + * for the invlalidation request. + * NV0080_CTRL_DMA_INVALIDATE_TLB_ALL + * When set to TRUE this flag requests a global invalidate. + * When set to FALSE this flag requests a chip-specfic + * optimization to invalidate only the address space bound + * to the associated hDevice. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_TIMEOUT_RETRY + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0080_CTRL_CMD_DMA_INVALIDATE_TLB (0x80180cU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS { + NvHandle hVASpace; + NvU32 flags; +} NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS; + +#define NV0080_CTRL_DMA_INVALIDATE_TLB_ALL 0:0 +#define NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_TRUE (0x00000001U) + +/** + * NV0080_CTRL_CMD_DMA_GET_CAPS + * + * This command returns the set of DMA capabilities for the device + * in the form of an array of unsigned bytes. DMA capabilities + * include supported features and required workarounds for address + * translation system within the device, each represented by a byte + * offset into the table and a bit position within that byte. + * + * capsTblSize + * This parameter specifies the size in bytes of the caps table. + * This value should be set to NV0080_CTRL_DMA_CAPS_TBL_SIZE. + * + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the framebuffer caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + * + * 32BIT_POINTER_ENFORCED + * If this property is TRUE NVOS32 and NVOS46 calls with + * 32BIT_POINTER_DISABLED will return addresses above 4GB. + * + * SHADER_ACCESS_SUPPORTED + * If this property is set, the MMU in the system supports the independent + * access bits for the shader. This is accessed with the following fields: + * NVOS46_FLAGS_SHADER_ACCESS + * NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_FLAGS_SHADER_ACCESS + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_DMA_GET_CAPS (0x80180dU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_GET_CAPS_PARAMS_MESSAGE_ID" */ +/* size in bytes of fb caps table */ +#define NV0080_CTRL_DMA_CAPS_TBL_SIZE 8U +#define NV0080_CTRL_DMA_GET_CAPS_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV0080_CTRL_DMA_GET_CAPS_PARAMS { + NvU32 capsTblSize; + NvU8 capsTbl[NV0080_CTRL_DMA_CAPS_TBL_SIZE]; +} NV0080_CTRL_DMA_GET_CAPS_PARAMS; + +/* extract cap bit setting from tbl */ +#define NV0080_CTRL_DMA_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* caps format is byte_index:bit_mask */ +#define NV0080_CTRL_DMA_CAPS_32BIT_POINTER_ENFORCED 0:0x01 +#define NV0080_CTRL_DMA_CAPS_SHADER_ACCESS_SUPPORTED 0:0x04 +#define NV0080_CTRL_DMA_CAPS_SPARSE_VIRTUAL_SUPPORTED 0:0x08 +#define NV0080_CTRL_DMA_CAPS_MULTIPLE_VA_SPACES_SUPPORTED 0:0x10 + +/* + * NV0080_CTRL_DMA_SET_VA_SPACE_SIZE + * + * Change the size of an existing VA space. + * NOTE: Currently this only supports growing the size, not shrinking. + * + * 1. Allocate new page directory able to map extended range. + * 2. Copy existing PDEs from old directory to new directory. + * 3. Initialize new PDEs to invalid. + * 4. Update instmem to point to new page directory. + * 5. Free old page directory. + * + * vaSpaceSize + * On input, the requested size of the VA space in bytes. + * On output, the actual resulting VA space size. + * + * The actual size will be greater than or equal to the requested size, + * unless NV0080_CTRL_DMA_GROW_VA_SPACE_SIZE_MAX is requested, which + * requests the maximum available. + * + * NOTE: Specific size requests (e.g. other than SIZE_MAX) must account + * for the VA hole at the beginning of the range which is used to + * distinguish NULL pointers. This region is not counted as part + * of the vaSpaceSize since it is not allocatable. + * + * hVASpace + * handle for the allocated VA space that this control call should operate + * on. If it's 0, it assumes to use the implicit allocated VA space + * associated with the client/device pair. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_RESOURCES + */ +#define NV0080_CTRL_CMD_DMA_SET_VA_SPACE_SIZE (0x80180eU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 vaSpaceSize, 8); + NvHandle hVASpace; +} NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS; + +#define NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_MAX (0xFFFFFFFFFFFFFFFFULL) + +/* + * NV0080_CTRL_DMA_UPDATE_PDE_2 + * + * This command updates a single PDE for the given (hClient, hDevice) + * with specific attributes. + * This command is only available on Windows and MODS platforms. + * This command can be called by kernel clients only. + * + * The VA range the PDE maps must be contained by a VA allocation marked with + * NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED. + * However if the MODS-only FORCE_OVERRIDE flag is set this restriction is relaxed. + * + * RM does not track the PDE's attributes in SW - this control simply stuffs + * the PDE in memory after translating and checking the parameters. + * + * Parameters are checked for relative consistency (e.g. valid domains), + * but it is the client's responsibility to provide correct page table + * addresses, e.g. global consistency is not checked. + * + * It is also the client's responsibility to flush/invalidate the MMU + * when appropriate, either by setting the _FLUSH_PDE_CACHE flag for this + * call or by flushing through other APIs. + * This control does not flush automatically to allow batches of calls + * to be made before a single flush. + * + * ptParams + * Page-size-specific parameters, as follows: + * + * physAddr + * Base address of physically contiguous memory of page table. + * Must be aligned sufficiently for the PDE address field. + * numEntries + * Deprecated and ignored. + * Use FLAGS_PDE_SIZE that applies to the tables for all page sizes. + * aperture + * Address space the base address applies to. + * Can be left as INVALID to ignore this page table size. + * + * pdeIndex + * The PDE index this update applies to. + * flags + * See NV0080_CTRL_DMA_UPDATE_PDE_FLAGS_*. + * hVASpace + * handle for the allocated VA space that this control call should operate + * on. If it's 0, it assumes to use the implicit allocated VA space + * associated with the client/device pair. + * pPdeBuffer [out] + * Kernel pointer to 64 bit unsigned integer representing a Page Dir Entry + * that needs to be updated. It should point to memory as wide as the Page Dir + * Entry. + * + * If NULL, Page Dir Entry updates will go to the internally managed Page Dir. + * If not NULL, the updates will be written to this buffer. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_NOT_SUPPORTED + */ +#define NV0080_CTRL_CMD_DMA_UPDATE_PDE_2 (0x80180fU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_MESSAGE_ID" */ + +typedef struct NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 physAddr, 8); + NvU32 numEntries; // deprecated + NvU32 aperture; +} NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS; + +#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_INVALID (0x00000000U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_VIDEO_MEMORY (0x00000001U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_COHERENT_MEMORY (0x00000002U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_NON_COHERENT_MEMORY (0x00000003U) + +#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_SMALL 0U +#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_BIG 1U +#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE 2U + +#define NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS { + NvU32 pdeIndex; + NvU32 flags; + NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS ptParams[NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE], 8); + NvHandle hVASpace; + NV_DECLARE_ALIGNED(NvP64 pPdeBuffer, 8); // NV_MMU_VER2_DUAL_PDE__SIZE + NvU32 subDeviceId; // ID+1, 0 for BC +} NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS; + +/*! + * If set a PDE cache flush (MMU invalidate) will be performed. + */ +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE 0:0 +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_TRUE (0x00000001U) + +/*! + * For verification purposes (MODS-only) this flag may be set to modify any PDE + * in the VA space (RM managed or externally managed). + * It is up to caller to restore any changes properly (or to expect faults). + */ +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE 1:1 +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_TRUE (0x00000001U) + +/*! + * Directly controls the PDE_SIZE field (size of the page tables pointed to by this PDE). + */ +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE 3:2 +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_FULL (0x00000000U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_HALF (0x00000001U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_QUARTER (0x00000002U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_EIGHTH (0x00000003U) + +/*! + * Used to specify if the allocation is sparse. Applicable only in case of + * VA Space managed by OS, as in WDDM2.0 + */ +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE 4:4 +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_TRUE (0x00000001U) + +/* + * NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE + * This interface will create a corresponding privileged + * kernel address space that will mirror user space allocations in this + * VASPACE. + * The user can either pass a FERMI_VASPACE_A handle or RM will use the + * vaspace associated with the client/device if hVaspace is passed as + * NULL. + * Once this property is set, the user will not be able to make allocations + * from the top most PDE of this address space. + * + * The user is expected to call this function as soon as he has created + * the device/Vaspace object. If the user has already made VA allocations + * in this vaspace then this call will return a failure + * (NV_ERR_INVALID_STATE). + * The Vaspace should have no VA allocations when this call is made. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE +*/ +#define NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE (0x801810U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS { + NvHandle hVASpace; +} NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS; + +/* + * NV0080_CTRL_DMA_SET_DEFAULT_VASPACE + * This is a special control call provided for KMD to use. + * It will associate an allocated Address Space Object as the + * default address space of the device. + * + * This is added so that the USER can move to using address space objects when they + * want to specify the size of the big page size they want to use but still want + * to use the rest of the relevant RM apis without specifying the hVASpace. + * + * This call will succeed only if there is already no VASPACE associated with the + * device. This means the user will have to call this before he has made any allocations + * on this device/address space. + * + * The hVASpace that is passed in to be associated shoould belong to the parent device that + * this call is made for. This call will fail if we try to associate a VASpace belonging to + * some other client/device. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + * + */ +#define NV0080_CTRL_DMA_SET_DEFAULT_VASPACE (0x801812U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS { + NvHandle hVASpace; +} NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS; + +/*! + * NV0080_CTRL_DMA_SET_PAGE_DIRECTORY + * + * Move an existing VA space to an externally-managed top-level page directory. + * The VA space must have been created in SHARED_MANAGEMENT mode. + * For lifecycle details, see NV_VASPACE_ALLOCATION_PARAMETERS documentation in nvos.h. + * + * RM will propagate the update to all channels using the VA space. + * + * NOTE: All channels using this VA space are expected to be idle and unscheduled prior + * to and during this control call - it is responsibility of caller to ensure this. + * + * physAddress + * Physical address of the new page directory within the aperture specified by flags. + * numEntries + * Number of entries in the new page directory. + * The backing phyical memory must be at least this size (multiplied by entry size). + * flags + * APERTURE + * Specifies which physical aperture the page directory resides. + * PRESERVE_PDES + * Deprecated - RM will always copy the RM-managed PDEs from the old page directory + * to the new page directory. + * ALL_CHANNELS + * If true, RM will update the instance blocks for all channels using + * the VAS and ignore the chId parameter. + * EXTEND_VASPACE + * If true, RM will use the client VA for client VA requests in VASPACE_SHARED_MANAGEMENT mode + * If false, RM will use the internal VA for client VA requests. + * IGNORE_CHANNEL_BUSY + * If true, RM will ignore the channel busy status during set page + * directory operation. + * hVASpace + * handle for the allocated VA space that this control call should operate + * on. If it's 0, it assumes to use the implicit allocated VA space + * associated with the client/device pair. + * chId + * ID of the Channel to be updated. + * pasid + * PASID (Process Address Space IDentifier) of the process corresponding to + * the VA space. Ignored unless the VA space has ATS enabled. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_LIMIT + * NV_ERR_GENERIC + */ +#define NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY (0x801813U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS { + NV_DECLARE_ALIGNED(NvU64 physAddress, 8); + NvU32 numEntries; + NvU32 flags; + NvHandle hVASpace; + NvU32 chId; + NvU32 subDeviceId; // ID+1, 0 for BC + NvU32 pasid; +} NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS; + +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE 1:0 +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_VIDMEM (0x00000000U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_COH (0x00000001U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_NONCOH (0x00000002U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES 2:2 +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_TRUE (0x00000001U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS 3:3 +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_TRUE (0x00000001U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY 4:4 +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_TRUE (0x00000001U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE 5:5 +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_TRUE (0x00000001U) + +/*! + * NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY + * + * Restore an existing VA space to an RM-managed top-level page directory. + * The VA space must have been created in SHARED_MANAGEMENT mode and + * previously relocated to an externally-managed page directory with + * NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY (these two API are symmetric operations). + * For lifecycle details, see NV_VASPACE_ALLOCATION_PARAMETERS documentation in nvos.h. + * + * RM will propagate the update to all channels using the VA space. + * + * NOTE: All channels using this VA space are expected to be idle and unscheduled prior + * to and during this control call - it is responsibility of caller to ensure this. + * + * hVASpace + * handle for the allocated VA space that this control call should operate + * on. If it's 0, it assumes to use the implicit allocated VA space + * associated with the client/device pair. + */ +#define NV0080_CTRL_CMD_DMA_UNSET_PAGE_DIRECTORY (0x801814U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS { + NvHandle hVASpace; + NvU32 subDeviceId; // ID+1, 0 for BC +} NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS; + + + +/* _ctrl0080dma_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h new file mode 100644 index 0000000..7fcc696 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h @@ -0,0 +1,232 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080fb.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE fb control commands and parameters */ + +/** + * NV0080_CTRL_CMD_FB_GET_CAPS + * + * This command returns the set of framebuffer capabilities for the device + * in the form of an array of unsigned bytes. Framebuffer capabilities + * include supported features and required workarounds for the framebuffer + * engine(s) within the device, each represented by a byte offset into the + * table and a bit position within that byte. + * + * capsTblSize + * This parameter specifies the size in bytes of the caps table. + * This value should be set to NV0080_CTRL_FB_CAPS_TBL_SIZE. + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the framebuffer caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_POINTER + */ +#define NV0080_CTRL_CMD_FB_GET_CAPS (0x801301) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FB_GET_CAPS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0080_CTRL_FB_GET_CAPS_PARAMS { + NvU32 capsTblSize; + NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); +} NV0080_CTRL_FB_GET_CAPS_PARAMS; + +/* extract cap bit setting from tbl */ +#define NV0080_CTRL_FB_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* caps format is byte_index:bit_mask */ +#define NV0080_CTRL_FB_CAPS_SUPPORT_RENDER_TO_SYSMEM 0:0x01 +#define NV0080_CTRL_FB_CAPS_BLOCKLINEAR 0:0x02 +#define NV0080_CTRL_FB_CAPS_SUPPORT_SCANOUT_FROM_SYSMEM 0:0x04 +#define NV0080_CTRL_FB_CAPS_SUPPORT_CACHED_SYSMEM 0:0x08 +#define NV0080_CTRL_FB_CAPS_SUPPORT_C24_COMPRESSION 0:0x10 // Deprecated +#define NV0080_CTRL_FB_CAPS_SUPPORT_SYSMEM_COMPRESSION 0:0x20 +#define NV0080_CTRL_FB_CAPS_NISO_CFG0_BUG_534680 0:0x40 // Deprecated +#define NV0080_CTRL_FB_CAPS_ISO_FETCH_ALIGN_BUG_561630 0:0x80 // Deprecated + +#define NV0080_CTRL_FB_CAPS_BLOCKLINEAR_GOBS_512 1:0x01 +#define NV0080_CTRL_FB_CAPS_L2_TAG_BUG_632241 1:0x02 +#define NV0080_CTRL_FB_CAPS_SINGLE_FB_UNIT 1:0x04 // Deprecated +#define NV0080_CTRL_FB_CAPS_CE_RMW_DISABLE_BUG_897745 1:0x08 // Deprecated +#define NV0080_CTRL_FB_CAPS_OS_OWNS_HEAP_NEED_ECC_SCRUB 1:0x10 +#define NV0080_CTRL_FB_CAPS_ASYNC_CE_L2_BYPASS_SET 1:0x20 // Deprecated +#define NV0080_CTRL_FB_CAPS_DISABLE_TILED_CACHING_INVALIDATES_WITH_ECC_BUG_1521641 1:0x40 + +#define NV0080_CTRL_FB_CAPS_DISABLE_MSCG_WITH_VR_BUG_1681803 2:0x01 +#define NV0080_CTRL_FB_CAPS_VIDMEM_ALLOCS_ARE_CLEARED 2:0x02 +#define NV0080_CTRL_FB_CAPS_DISABLE_PLC_GLOBALLY 2:0x04 +#define NV0080_CTRL_FB_CAPS_PLC_BUG_3046774 2:0x08 + + +/* size in bytes of fb caps table */ +#define NV0080_CTRL_FB_CAPS_TBL_SIZE 3 + + + +/*! + * NV0080_CTRL_CMD_FB_COMPBIT_STORE_GET_INFO + * + * This command returns compbit backing store-related information. + * + * size + * [out] Size of compbit store, in bytes + * address + * [out] Address of compbit store + * addressSpace + * [out] Address space of compbit store (corresponds to type NV_ADDRESS_SPACE in nvrm.h) + * maxCompbitLine + * [out] Maximum compbitline possible, determined based on size + * comptagsPerCacheLine + * [out] Number of compression tags per compression cache line, across all + * L2 slices. + * cacheLineSize + * [out] Size of compression cache line, across all L2 slices. (bytes) + * cacheLineSizePerSlice + * [out] Size of the compression cache line per slice (bytes) + * cacheLineFetchAlignment + * [out] Alignment used while fetching the compression cacheline range in FB. + * If start offset of compcacheline in FB is S and end offset is E, then + * the range to fetch to ensure entire compcacheline data is extracted is: + * (align_down(S) , align_up(E)) + * This is needed in GM20X+ because of interleaving of data in Linear FB space. + * Example - In GM204 every other 1K FB chunk of data is offset by 16K. + * backingStoreBase + * [out] Address of start of Backing Store in linear FB Physical Addr space. + * This is the actual offset in FB which HW starts using as the Backing Store and + * in general will be different from the start of the region that driver allocates + * as the backing store. This address is expected to be 2K aligned. + * gobsPerComptagPerSlice + * [out] (Only on Pascal) Number of GOBS(512 bytes of surface PA) that correspond to one 64KB comptgaline, per slice. + * One GOB stores 1 byte of compression bits. + * 0 value means this field is not applicable for the current architecture. + * backingStoreCbcBase + * [out] 2KB aligned base address of CBC (post divide address) + * comptaglineAllocationPolicy + * [out] Policy used to allocate comptagline from CBC for the device + * privRegionStartOffset + * [out] Starting offset for any priv region allocated by clients. only used by MODS + * Possible status values returned are: + * NV_OK + */ +#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO (0x801306) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 Size, 8); + NV_DECLARE_ALIGNED(NvU64 Address, 8); + NvU32 AddressSpace; + NvU32 MaxCompbitLine; + NvU32 comptagsPerCacheLine; + NvU32 cacheLineSize; + NvU32 cacheLineSizePerSlice; + NvU32 cacheLineFetchAlignment; + NV_DECLARE_ALIGNED(NvU64 backingStoreBase, 8); + NvU32 gobsPerComptagPerSlice; + NvU32 backingStoreCbcBase; + NvU32 comptaglineAllocationPolicy; + NV_DECLARE_ALIGNED(NvU64 privRegionStartOffset, 8); +} NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS; + +#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_UNKNOWN 0 // ADDR_UNKNOWN +#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_SYSMEM 1 // ADDR_SYSMEM +#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_FBMEM 2 // ADDR_FBMEM + +// Policy used to allocate comptaglines +/** + * Legacy mode allocates a comptagline for 64kb page. This mode will always allocate + * contiguous comptaglines from a ctag heap. + */ +#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_LEGACY 0 +/** + * 1TO1 mode allocates a comptagline for 64kb page. This mode will calculate + * comptagline offset based on physical address. This mode will allocate + * contiguous comptaglines if the surface is contiguous and non-contiguous + * comptaglines for non-contiguous surfaces. + */ +#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO1 1 +/** + * 1TO4_Heap mode allocates a comptagline for 256kb page granularity. This mode + * will allocate comptagline from a heap. This mode will align the surface allocations + * to 256kb before allocating comptaglines. The comptaglines allocated will always be + * contiguous here. + * TODO: For GA10x, this mode will support < 256kb surface allocations, by sharing + * a comptagline with at most 3 different 64Kb allocations. This will result in + * miixed-contiguity config where comptaglines will be allocated contiguously as well + * as non-contiguous when shared with other allocations. + */ +#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO4 2 +/** + * Rawmode will transfer allocation of comptaglines to HW, where HW manages + * comptaglines based on physical offset. The comptaglines are cleared when SW + * issues physical/virtual scrub to the surface before reuse. + */ +#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_RAWMODE 3 + +/** + * NV0080_CTRL_CMD_FB_GET_CAPS_V2 + * + * This command returns the same set of framebuffer capabilities for the + * device as @ref NV0080_CTRL_CMD_FB_GET_CAPS. The difference is in the structure + * NV0080_CTRL_FB_GET_CAPS_V2_PARAMS, which contains a statically sized array, + * rather than a caps table pointer and a caps table size in + * NV0080_CTRL_FB_GET_CAPS_PARAMS. + * + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the framebuffer caps bits will be written by the RM. + * The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_POINTER + */ +#define NV0080_CTRL_CMD_FB_GET_CAPS_V2 (0x801307) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FB_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV0080_CTRL_FB_GET_CAPS_V2_PARAMS { + NvU8 capsTbl[NV0080_CTRL_FB_CAPS_TBL_SIZE]; +} NV0080_CTRL_FB_GET_CAPS_V2_PARAMS; + + + + +/* _ctrl0080fb_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h new file mode 100644 index 0000000..823cc0c --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h @@ -0,0 +1,642 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080fifo.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE fifo control commands and parameters */ + +/** + * NV0080_CTRL_FIFO_GET_CAPS + * + * This command returns the set of FIFO engine capabilities for the device + * in the form of an array of unsigned bytes. FIFO capabilities + * include supported features and required workarounds for the FIFO + * engine(s) within the device, each represented by a byte offset into the + * table and a bit position within that byte. + * + * capsTblSize + * This parameter specifies the size in bytes of the caps table. + * This value should be set to NV0080_CTRL_FIFO_CAPS_TBL_SIZE. + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the framebuffer caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_FIFO_GET_CAPS (0x801701) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_GET_CAPS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0080_CTRL_FIFO_GET_CAPS_PARAMS { + NvU32 capsTblSize; + NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); +} NV0080_CTRL_FIFO_GET_CAPS_PARAMS; + +/* extract cap bit setting from tbl */ +#define NV0080_CTRL_FIFO_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* caps format is byte_index:bit_mask */ +#define NV0080_CTRL_FIFO_CAPS_SUPPORT_SCHED_EVENT 0:0x01 +#define NV0080_CTRL_FIFO_CAPS_SUPPORT_PCI_PB 0:0x02 +#define NV0080_CTRL_FIFO_CAPS_SUPPORT_VID_PB 0:0x04 +#define NV0080_CTRL_FIFO_CAPS_USERD_IN_SYSMEM 0:0x40 +/* do not use pipelined PTE BLITs to update PTEs: call the RM */ +#define NV0080_CTRL_FIFO_CAPS_NO_PIPELINED_PTE_BLIT 0:0x80 +#define NV0080_CTRL_FIFO_CAPS_GPU_MAP_CHANNEL 1:0x01 +#define NV0080_CTRL_FIFO_CAPS_BUFFEREDMODE_SCHEDULING 1:0x02 // Deprecated +#define NV0080_CTRL_FIFO_CAPS_WFI_BUG_898467 1:0x08 // Deprecated +#define NV0080_CTRL_FIFO_CAPS_HAS_HOST_LB_OVERFLOW_BUG_1667921 1:0x10 +/* + * To indicate Volta subcontext support with multiple VA spaces in a TSG. + * We are not using "subcontext" tag for the property, since we also use + * subcontext to represent pre-VOlta SCG feature, which only allows a single + * VA space in a TSG. + */ +#define NV0080_CTRL_FIFO_CAPS_MULTI_VAS_PER_CHANGRP 1:0x20 + + +#define NV0080_CTRL_FIFO_CAPS_SUPPORT_WDDM_INTERLEAVING 1:0x40 + +/* size in bytes of fifo caps table */ +#define NV0080_CTRL_FIFO_CAPS_TBL_SIZE 2 + +/* + * NV0080_CTRL_CMD_FIFO_ENABLE_SCHED_EVENTS + * + * This command enables the GPU to place various scheduling events in the + * off chip event buffer (with optional interrupt) for those GPUs that support + * it. + * + * record + * This parameter specifies a mask of event types to record. + * interrupt + * This parameter specifies a mask of event types for which to interrupt + * the CPU when the event occurs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_FIFO_ENABLE_SCHED_EVENTS (0x801703) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0x3" */ + +typedef struct NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PARAMS { + NvU32 record; + NvU32 interrupt; +} NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PARAMS; + +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_START_CTX 0:0 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_START_CTX_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_START_CTX_ENABLE (0x00000001) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_END_CTX 1:1 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_END_CTX_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_END_CTX_ENABLE (0x00000001) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_NEW_RUNLIST 2:2 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_NEW_RUNLIST_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_NEW_RUNLIST_ENABLE (0x00000001) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_SEM_ACQUIRE 3:3 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_SEM_ACQUIRE_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_SEM_ACQUIRE_ENABLE (0x00000001) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PAGE_FAULT 4:4 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PAGE_FAULT_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PAGE_FAULT_ENABLE (0x00000001) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PREEMPT 5:5 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PREEMPT_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PREEMPT_ENABLE (0x00000001) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_YIELD 6:6 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_YIELD_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_YIELD_ENABLE (0x00000001) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_IDLE_CTX 7:7 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_IDLE_CTX_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_IDLE_CTX_ENABLE (0x00000001) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_HI_PRI 8:8 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_HI_PRI_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_HI_PRI_ENABLE (0x00000001) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ENG_STALLED 9:9 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ENG_STALLED_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ENG_STALLED_ENABLE (0x00000001) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_VSYNC 10:10 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_VSYNC_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_VSYNC_ENABLE (0x00000001) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_FGCS_FAULT 11:11 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_FGCS_FAULT_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_FGCS_FAULT_ENABLE (0x00000001) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ALL 11:0 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ALL_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ALL_ENABLE (0x00000fff) + +/* + * NV0080_CTRL_CMD_FIFO_START_SELECTED_CHANNELS + * + * This command allows the caller to request that a set of channels + * be added to the runlist. + * + * fifoStartChannelListSize + * Size of the fifoStartChannelList. The units are in entries, not + * bytes. + * fifoStartChannelList + * This will be a list of NV0080_CTRL_FIFO_CHANNEL data structures, + * one for each channel that is to be started. + * channelHandle + * deprecated + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +/* + * hChannel + * This is the handle to the channel that is scheduled to be started. + */ +typedef struct NV0080_CTRL_FIFO_CHANNEL { + NvHandle hChannel; +} NV0080_CTRL_FIFO_CHANNEL; + +#define NV0080_CTRL_CMD_FIFO_START_SELECTED_CHANNELS (0x801705) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS { + NvU32 fifoStartChannelListCount; + NvHandle channelHandle[8]; + NV_DECLARE_ALIGNED(NvP64 fifoStartChannelList, 8); +} NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS; + +#define NV0080_CTRL_FIFO_ENGINE_ID_GRAPHICS (0x00000000) +#define NV0080_CTRL_FIFO_ENGINE_ID_MPEG (0x00000001) +#define NV0080_CTRL_FIFO_ENGINE_ID_MOTION_ESTIMATION (0x00000002) +#define NV0080_CTRL_FIFO_ENGINE_ID_VIDEO (0x00000003) +#define NV0080_CTRL_FIFO_ENGINE_ID_BITSTREAM (0x00000004) +#define NV0080_CTRL_FIFO_ENGINE_ID_ENCRYPTION (0x00000005) +#define NV0080_CTRL_FIFO_ENGINE_ID_FGT (0x00000006) + +/* + * NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES + * + * This command is used to provide the caller with the alignment and size + * of the context save region for an engine + * + * engineId + * This parameter is an input parameter specifying the engineId for which + * the alignment/size is requested. + * alignment + * This parameter is an output parameter which will be filled in with the + * minimum alignment requirement. + * size + * This parameter is an output parameter which will be filled in with the + * minimum size of the context save region for the engine. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES (0x801707) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID 4:0 +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS (0x00000000) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VLD (0x00000001) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VIDEO (0x00000002) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_MPEG (0x00000003) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_CAPTURE (0x00000004) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_DISPLAY (0x00000005) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_ENCRYPTION (0x00000006) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_POSTPROCESS (0x00000007) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ZCULL (0x00000008) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PM (0x00000009) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COMPUTE_PREEMPT (0x0000000a) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PREEMPT (0x0000000b) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SPILL (0x0000000c) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL (0x0000000d) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BETACB (0x0000000e) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV (0x0000000f) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PATCH (0x00000010) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BUNDLE_CB (0x00000011) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL_GLOBAL (0x00000012) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ATTRIBUTE_CB (0x00000013) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV_CB_GLOBAL (0x00000014) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_POOL (0x00000015) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_CTRL_BLK (0x00000016) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_FECS_EVENT (0x00000017) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PRIV_ACCESS_MAP (0x00000018) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT (0x00000019) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS { + NvU32 engineId; + NvU32 alignment; + NvU32 size; +} NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS; + +/* + * NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS + * + * This command allows the caller to group two sets of channels. A channel + * set includes one or more channels. After grouping, the grouped channel IDs + * are set to next to each other in the runlist. This command can be used + * several times to group more than two channels. + * + * Using a NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE after + * NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS is the general usage. A + * NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS after a + * NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE for a channel handle is not + * allowed. + * + * NV0080_CTRL_FIFO_RUNLIST_GROUP_MAX_CHANNELS defines the max channels in a + * group. + * + * hChannel1 + * This parameter specifies the handle of the channel that belongs to the + * base set of channels. + * hChannel2 + * This parameter specifies the handle of the channel that belongs to the + * additional set of channels. + + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_CHANNEL + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS (0x801709) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0x9" */ + +typedef struct NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM { + NvHandle hChannel1; + NvHandle hChannel2; +} NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM; + +#define NV0080_CTRL_FIFO_RUNLIST_GROUP_MAX_CHANNELS (8) + +/* + * NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE + * + * This command allows the caller to divide the timeslice (DMA_TIMESLICE) of a + * channel between the channels in the group in which the channel resides. + * After applying this command, a timeslice divided channel (group) has a + * short timeslice and repeats more than once in the runlist. The total + * available execution time is not changed. + * + * Using this command after NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS is the + * general usage. A NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS after a + * NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE for a channel handle is not + * allowed. + * + * hChannel + * This parameter specifies the handle of the channel for the channel + * group to which the divided timeslice operation will apply. + * tsDivisor + * This parameter specifies the timeslice divisor value. This value + * should not exceed NV0080_CTRL_FIFO_RUNLIST_MAX_TIMESLICE_DIVISOR + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_CHANNEL + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_RESOURCES + */ +#define NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE (0x80170b) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0xB" */ + +typedef struct NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM { + NvHandle hChannel; + NvU32 tsDivisor; +} NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM; + +#define NV0080_CTRL_FIFO_RUNLIST_MAX_TIMESLICE_DIVISOR (12) + +/* + * NV0080_CTRL_CMD_FIFO_PREEMPT_RUNLIST + * + * This command preepmts the engine represented by the specified runlist. + * + * hRunlist + * This parameter specifies the per engine runlist handle. This + * parameter is being retained to maintain backwards compatibility + * with clients that have not transitioned over to using runlists + * on a per subdevice basis. + * + * engineID + * This parameter specifies the engine to be preempted. Engine defines + * can be found in cl2080.h. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_FIFO_PREEMPT_RUNLIST (0x80170c) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0xC" */ + +typedef struct NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS { + NvHandle hRunlist; + NvU32 engineID; +} NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS; + + +/* + * NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST + * + * Takes a list of hChannels as input and returns the + * corresponding Channel IDs that they corresponding to + * on hw. + * + * numChannels + * Size of input hChannellist + * pChannelHandleList + * List of input channel handles + * pChannelList + * List of Channel ID's corresponding to the + * each entry in the hChannelList. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST (0x80170d) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS { + NvU32 numChannels; + NV_DECLARE_ALIGNED(NvP64 pChannelHandleList, 8); + NV_DECLARE_ALIGNED(NvP64 pChannelList, 8); +} NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS; + + +/* + * NV0080_CTRL_CMD_FIFO_GET_LATENCY_BUFFER_SIZE + * + * This control call is used to return the number of gp methods(gpsize) and push buffer methods(pbsize) + * allocated to each engine. + * + *engineID + * The engine ID which is an input + * + *gpEntries + * number of gp entries + * + *pbEntries + * number of pb entries (in units of 32B rows) + * + */ + + +#define NV0080_CTRL_CMD_FIFO_GET_LATENCY_BUFFER_SIZE (0x80170e) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS { + NvU32 engineID; + NvU32 gpEntries; + NvU32 pbEntries; +} NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS; + +#define NV0080_CTRL_FIFO_GET_CHANNELLIST_INVALID_CHANNEL (0xffffffff) + +/* + * NV0080_CTRL_CMD_FIFO_SET_CHANNEL_PROPERTIES + * + * This command allows internal properties of the channel + * to be modified even when the channel is active. Most of these properties + * are not meant to be modified during normal runs hence have been + * kept separate from channel alloc params. It is the + * responsibility of the underlying hal routine to make + * sure the channel properties are changed while the channel + * is *NOT* in a transient state. + * + * hChannel + * The handle to the channel. + * + * property + * The channel property to be modified. + * NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_xxx provides the entire list + * of properties. + * + * value + * The new value for the property. + * When property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEINMICROSECONDS + * value = timeslice in microseconds + * desc: Used to change a channel's engine timeslice in microseconds + * + * property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEINMICROSECONDS + * value = timeslice in microseconds + * desc: Used to change a channel's pbdma timeslice in microseconds + * + * property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEDISABLE + * value is ignored + * desc: Disables a channel from being timesliced out from an engine. + * Other scheduling events like explicit yield, acquire failures will + * switch out the channel though. + * + * property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEDISABLE + * value is ignored + * desc: Disables a channel from being timesliced out from its pbdma. + * + * property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_INVALIDATE_PDB_TARGET + * value is ignored + * desc: Override the channel's page directory pointer table with an + * erroneous aperture value. (TODO: make test calls NV_VERIF_FEATURES + * only)(VERIF ONLY) + * + * property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT + * value = engineID of engine that will have its context pointer reset. + * engineID defines can be found in cl2080.h + * (e.g., NV2080_ENGINE_TYPE_GRAPHICS) + * desc: Override the channel's engine context pointer with a non existent + * buffer forcing it to fault. (VERIF ONLY) + * + * property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT_NOPREEMPT + * value = engineID of engine that will have its context pointer reset. + * engineID defines can be found in cl2080.h + * (e.g., NV2080_ENGINE_TYPE_GRAPHICS) + * desc: Override the channel's engine context pointer with a non existent + * buffer forcing it to fault. However the channel will not be preempted + * before having its channel state modified.(VERIF ONLY) + * + * property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_NOOP + * value is ignored + * desc: does not change any channel state exercises a full channel preempt/ + * unbind/bind op. (VERIF ONLY) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_CHANNEL + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0080_CTRL_CMD_FIFO_SET_CHANNEL_PROPERTIES (0x80170f) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS { + NvHandle hChannel; + NvU32 property; + NV_DECLARE_ALIGNED(NvU64 value, 8); +} NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS; + +#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEINMICROSECONDS (0x00000000) +#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEINMICROSECONDS (0x00000001) +#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEDISABLE (0x00000002) +#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEDISABLE (0x00000003) +#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_INVALIDATE_PDB_TARGET (0x00000004) +#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT (0x00000005) +#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_NOOP (0x00000007) +#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT_NOPREEMPT (0x00000008) + + + +/* + * NV0080_CTRL_CMD_FIFO_STOP_RUNLIST + * + * Stops all processing on the runlist for the given engine. This is only + * valid in per-engine round-robin scheduling mode. + * + * engineID + * This parameter specifies the engine to be stopped. Engine defines + * can be found in cl2080.h. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV0080_CTRL_CMD_FIFO_STOP_RUNLIST (0x801711) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS { + NvU32 engineID; +} NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS; + +/* + * NV0080_CTRL_CMD_FIFO_START_RUNLIST + * + * Restarts a runlist previously stopped with NV0080_CTRL_CMD_FIFO_STOP_RUNLIST. + * This is only valid for per-engine round-robin mode. + * + * engineID + * This parameter specifies the engine to be started. Engine defines + * can be found in cl2080.h. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV0080_CTRL_CMD_FIFO_START_RUNLIST (0x801712) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV0080_CTRL_FIFO_START_RUNLIST_PARAMS { + NvU32 engineID; +} NV0080_CTRL_FIFO_START_RUNLIST_PARAMS; + +/** + * NV0080_CTRL_FIFO_GET_CAPS_V2 + * + * This command returns the same set of FIFO engine capabilities for the device + * as @ref NV0080_CTRL_FIFO_GET_CAPS. The difference is in the structure + * NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS, which contains a statically sized array, + * rather than a caps table pointer and a caps table size in + * NV0080_CTRL_FIFO_GET_CAPS_PARAMS. + * + * capsTbl + * This parameter is an array of the client's caps table buffer. + * The framebuffer caps bits will be written by the RM. + * The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_FIFO_GET_CAPS_V2 (0x801713) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS { + NvU8 capsTbl[NV0080_CTRL_FIFO_CAPS_TBL_SIZE]; +} NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS; + +/** + * NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS + * + * @brief This command idles (deschedules and waits for pending work to complete) channels + * belonging to a particular device. + * + * numChannels + * Number of channels to idle + * + * hChannels + * Array of channel handles to idle + * + * flags + * NVOS30_FLAGS that control aspects of how the channel is idled + * + * timeout + * GPU timeout in microseconds, for each CHID Manager's idling operation + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_TIMEOUT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_LOCK_STATE + */ +#define NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS (0x801714) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS_MESSAGE_ID" */ +#define NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS_MAX_CHANNELS 4096 + +#define NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS { + NvU32 numChannels; + NvHandle hChannels[NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS_MAX_CHANNELS]; + NvU32 flags; + NvU32 timeout; +} NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS; + +/* _ctrl0080fifo_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h new file mode 100644 index 0000000..5ce19e5 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h @@ -0,0 +1,585 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080gpu.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" +#include "nvlimits.h" + + +/* NV01_DEVICE_XX/NV03_DEVICE gpu control commands and parameters */ + +/* + * NV0080_CTRL_CMD_GPU_GET_CLASSLIST + * + * This command returns supported class information for the specified device. + * If the device is comprised of more than one GPU, the class list represents + * the set of supported classes common to all GPUs within the device. + * + * It has two modes: + * + * If the classList pointer is NULL, then this command returns the number + * of classes supported by the device in the numClasses field. The value + * should then be used by the client to allocate a classList buffer + * large enough to hold one 32bit value per numClasses entry. + * + * If the classList pointer is non-NULL, then this command returns the + * set of supported class numbers in the specified buffer. + * + * numClasses + * If classList is NULL, then this parameter will return the + * number of classes supported by the device. If classList is non-NULL, + * then this parameter indicates the number of entries in classList. + * classList + * This parameter specifies a pointer to the client's buffer into + * which the supported class numbers should be returned. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV0080_CTRL_CMD_GPU_GET_CLASSLIST (0x800201) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS { + NvU32 numClasses; + NV_DECLARE_ALIGNED(NvP64 classList, 8); +} NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS; + +/** + * NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES + * + * This command returns the number of subdevices for the device. + * + * numSubDevices + * This parameter returns the number of subdevices within the device. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES (0x800280) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS_MESSAGE_ID (0x80U) + +typedef struct NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS { + NvU32 numSubDevices; +} NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS; + +/* + * NV0080_CTRL_CMD_GPU_GET_VIDLINK_ORDER + * + * This command returns the video link order of each subdevice id inside the + * device. This call can only be made after SLI is enabled. This call is + * intended for 3D clients to use to determine the vidlink order of the + * devices. The Display Output Parent will always be the first subdevice + * mask listed in the array. Note that this command should not be used in + * case of bridgeless SLI. The order of the subdevices returned by this + * command will not be correct in case of bridgeless SLI. + * + * ConnectionCount + * Each HW can provide 1 or 2 links between all GPUs in a device. This + * number tells how many links are available between GPUs. This data + * also represents the number of concurrent SLI heads that can run at + * the same time over this one device. + * + * Order + * This array returns the order of subdevices that are used through + * the vidlink for display output. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0080_CTRL_CMD_GPU_GET_VIDLINK_ORDER (0x800281) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS { + NvU32 ConnectionCount; + NvU32 Order[NV_MAX_SUBDEVICES]; +} NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS; + +/* + * NV0080_CTRL_CMD_GPU_SET_DISPLAY_OWNER + * + * This command sets display ownership within the device to the specified + * subdevice instance. The actual transfer of display ownership will take + * place at the next modeset. + * + * subDeviceInstance + * This member specifies the subdevice instance of the new display + * owner. The subdevice instance must be in the legal range + * indicated by the NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0080_CTRL_CMD_GPU_SET_DISPLAY_OWNER (0x800282) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS_MESSAGE_ID (0x82U) + +typedef struct NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS { + NvU32 subDeviceInstance; +} NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS; + +/* + * NV0080_CTRL_CMD_GPU_GET_DISPLAY_OWNER + * + * This command returns the subdevice instance of the current display owner + * within the device. + * + * subDeviceInstance + * This member returns the subdevice instance of the current display + * owner. The subdevice instance will be in the legal range + * indicated by the NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0080_CTRL_CMD_GPU_GET_DISPLAY_OWNER (0x800283) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS_MESSAGE_ID (0x83U) + +typedef struct NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS { + NvU32 subDeviceInstance; +} NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS; + +/* + * NV0080_CTRL_CMD_GPU_SET_VIDLINK + * + * This command enables or disables the VIDLINK of all subdevices in the + * current SLI configuration. + * + * enable + * Enables or disables the vidlink + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV0080_CTRL_CMD_GPU_SET_VIDLINK (0x800285) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_VIDLINK_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_SET_VIDLINK_PARAMS_MESSAGE_ID (0x85U) + +typedef struct NV0080_CTRL_GPU_SET_VIDLINK_PARAMS { + NvU32 enable; +} NV0080_CTRL_GPU_SET_VIDLINK_PARAMS; + +#define NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_FALSE (0x00000000) +#define NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_TRUE (0x00000001) + +/* commands */ +#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_GET_STATUS 0 +#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERDOWN 1 +#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERUP 2 + +/* status */ +#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWER_ON 0 +#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_DOWN 1 +#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_GATED 2 +#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_UP 3 + +/* + * NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE + * + * This command is used to enable or disable the persistence of a GPU's + * software state when no clients exist. With persistent software state enabled + * the GPU's software state is not torn down when the last client exits, but is + * retained until either the kernel module unloads or persistent software state + * is disabled. + * + * newState + * This input parameter is used to enable or disable the persistence of the + * software state of all subdevices within the device. + * Possible values are: + * NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED + * NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE (0x800287) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID" */ + +/* Possible values of persistentSwState */ +#define NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED (0x00000000) +#define NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED (0x00000001) + +#define NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID (0x87U) + +typedef struct NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS { + NvU32 newState; +} NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS; + +/* + * NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE + * + * swStatePersistence + * This parameter returns a value indicating if persistent software + * state is currently enabled or not for the specified GPU. See the + * description of NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE. + * Possible values are: + * NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED + * NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE (0x800288) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID (0x88U) + +typedef struct NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS { + NvU32 swStatePersistence; +} NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS; + +/** + * NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE + * + * This command returns a value indicating virtualization mode in + * which the GPU is running. + * + * virtualizationMode + * This parameter returns the virtualization mode of the device. + * Possible values are: + * NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE + * This value indicates that there is no virtualization mode associated with the + * device (i.e. it's a baremetal GPU). + * NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS + * This value indicates that the device is associated with the NMOS. + * NV0080_CTRL_GPU_VIRTUALIZATION_MODE_VGX + * This value indicates that the device is associated with VGX(guest GPU). + * NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST + * NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VGPU + * This value indicates that the device is associated with vGPU(host GPU). + * NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VSGA + * This value indicates that the device is associated with vSGA(host GPU). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE (0x800289) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE (0x00000000) +#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS (0x00000001) +#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_VGX (0x00000002) +#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST (0x00000003) +#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VGPU NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST +#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VSGA (0x00000004) + +#define NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS_MESSAGE_ID (0x89U) + +typedef struct NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS { + NvU32 virtualizationMode; +} NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS; + + + +/* + * NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE + * + * This command returns the setting information for sparse texture compute + * mode optimization on the associated GPU. This setting indicates how the + * large page size should be selected by the RM for the GPU. + * + * defaultSetting + * This field specifies what the OS default setting is for the associated + * GPU. See NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE for a list + * of possible values. + * currentSetting + * This field specifies which optimization mode was applied when the + * driver was loaded. See + * NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE for a list of + * possible values. + * pendingSetting + * This field specifies which optimization mode will be applied on the + * next driver reload. See + * NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE for a list of + * possible values. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE (0x80028c) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID (0x8CU) + +typedef struct NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS { + NvU32 defaultSetting; + NvU32 currentSetting; + NvU32 pendingSetting; +} NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS; + +/* + * NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE + * + * This command sets the pending setting for sparse texture compute mode. This + * setting indicates how the large page size should be selected by the RM for + * the GPU on the next driver reload. + * + * setting + * This field specifies which use case the RM should optimize the large + * page size for on the next driver reload. Possible values for this + * field are: + * NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_DEFAULT + * This value indicates that the RM should use the default setting for + * the GPU's large page size. The default setting is reported by + * NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE. + * NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_COMPUTE + * This value indicates that the RM should select the GPU's large page + * size to optimize for compute use cases. + * NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_SPARSE_TEXTURE + * This value indicates that the RM should select the GPU's large page + * size to optimize for sparse texture use cases. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +#define NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE (0x80028d) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID (0x8DU) + +typedef struct NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS { + NvU32 setting; +} NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS; + +/* Possible sparse texture compute mode setting values */ +#define NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_DEFAULT 0 +#define NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_COMPUTE 1 +#define NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_SPARSE_TEXTURE 2 + +/* + * NV0080_CTRL_CMD_GPU_GET_VGX_CAPS + * + * This command gets the VGX capability of the GPU depending on the status of + * the VGX hardware fuse. + * + * isVgx + * This field is set to NV_TRUE is VGX fuse is enabled for the GPU otherwise + * it is set to NV_FALSE. + * + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + * NVOS_STATUS_ERROR_NOT_SUPPORTED + */ +#define NV0080_CTRL_CMD_GPU_GET_VGX_CAPS (0x80028e) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS_MESSAGE_ID (0x8EU) + +typedef struct NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS { + NvBool isVgx; +} NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS; + + + +/* + * NV0080_CTRL_CMD_GPU_GET_SRIOV_CAPS + * + * This command is used to query GPU SRIOV capabilities + * totalVFs + * Total number of virtual functions supported. + * + * firstVfOffset + * Offset of the first VF. + * + * vfFeatureMask + * Bitmask of features managed by the guest + * + * FirstVFBar0Address + * Address of BAR0 region of first VF. + * + * FirstVFBar1Address + * Address of BAR1 region of first VF. + * + * FirstVFBar2Address + * Address of BAR2 region of first VF. + * + * bar0Size + * Size of BAR0 region on VF. + * + * bar1Size + * Size of BAR1 region on VF. + * + * bar2Size + * Size of BAR2 region on VF. + * + * b64bitBar0 + * If the VF BAR0 is 64-bit addressable. + * + * b64bitBar1 + * If the VF BAR1 is 64-bit addressable. + * + * b64bitBar2 + * If the VF BAR2 is 64-bit addressable. + * + * bSriovEnabled + * Flag for SR-IOV enabled or not. + * + * bSriovHeavyEnabled + * Flag for whether SR-IOV is enabled in standard or heavy mode. + * + * bEmulateVFBar0TlbInvalidationRegister + * Flag for whether VF's TLB Invalidate Register region needs emulation. + * + * bClientRmAllocatedCtxBuffer + * Flag for whether engine ctx buffer is managed by client RM. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV0080_CTRL_CMD_GPU_GET_SRIOV_CAPS (0x800291) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_MESSAGE_ID (0x91U) + +typedef struct NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS { + NvU32 totalVFs; + NvU32 firstVfOffset; + NvU32 vfFeatureMask; + NV_DECLARE_ALIGNED(NvU64 FirstVFBar0Address, 8); + NV_DECLARE_ALIGNED(NvU64 FirstVFBar1Address, 8); + NV_DECLARE_ALIGNED(NvU64 FirstVFBar2Address, 8); + NV_DECLARE_ALIGNED(NvU64 bar0Size, 8); + NV_DECLARE_ALIGNED(NvU64 bar1Size, 8); + NV_DECLARE_ALIGNED(NvU64 bar2Size, 8); + NvBool b64bitBar0; + NvBool b64bitBar1; + NvBool b64bitBar2; + NvBool bSriovEnabled; + NvBool bSriovHeavyEnabled; + NvBool bEmulateVFBar0TlbInvalidationRegister; + NvBool bClientRmAllocatedCtxBuffer; +} NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS; + + +// Update this macro if new HW exceeds GPU Classlist MAX_SIZE +#define NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE 160 + +#define NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 (0x800292) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID (0x92U) + +typedef struct NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS { + NvU32 numClasses; // __OUT__ + NvU32 classList[NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE]; // __OUT__ +} NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS; + +/* + * NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE + * + * Find a subdevice handle allocated under this device + */ +#define NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE (0x800293) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM_MESSAGE_ID (0x93U) + +typedef struct NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM { + NvU32 subDeviceInst; // [in] + NvHandle hSubDevice; // [out] +} NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM; + +/* + * NV0080_CTRL_CMD_GPU_GET_BRAND_CAPS + * + * This command gets branding information for the device. + * + * brands + * Mask containing branding information. A bit in this + * mask is set if the GPU has particular branding. + * + * Possible status values returned are: + * NV_OK + */ + +#define NV0080_CTRL_GPU_GET_BRAND_CAPS_QUADRO NVBIT(0) +#define NV0080_CTRL_GPU_GET_BRAND_CAPS_NVS NVBIT(1) +#define NV0080_CTRL_GPU_GET_BRAND_CAPS_TITAN NVBIT(2) + +#define NV0080_CTRL_CMD_GPU_GET_BRAND_CAPS (0x800294) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS_MESSAGE_ID (0x94U) + +typedef struct NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS { + NvU32 brands; +} NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS; + +/* + * These are the per-VF BAR1 sizes that we support in MB. + * They are used with the NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE control call and + * should match the NV_XVE_BAR1_CONFIG_SIZE register defines. + */ +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M 64 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128M 128 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256M 256 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_512M 512 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_1G 1024 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_2G 2048 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_4G 4096 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_8G 8192 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_16G 16384 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_32G 32768 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64G 65536 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G 131072 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MIN NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MAX NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G + +#define NV0080_CTRL_GPU_VGPU_NUM_VFS_INVALID NV_U32_MAX + +/* + * NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE + * + * @brief Resize BAR1 per-VF on the given GPU + * vfBar1SizeMB[in] size of per-VF BAR1 size in MB + * numVfs[out] number of VFs that can be created given the new BAR1 size + */ +#define NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE (0x800296) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS_MESSAGE_ID (0x96U) + +typedef struct NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS { + NvU32 vfBar1SizeMB; + NvU32 numVfs; +} NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS; + +/* _ctrl0080gpu_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h new file mode 100644 index 0000000..2592559 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h @@ -0,0 +1,275 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080gr.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +typedef struct NV0080_CTRL_GR_ROUTE_INFO { + NvU32 flags; + NV_DECLARE_ALIGNED(NvU64 route, 8); +} NV0080_CTRL_GR_ROUTE_INFO; + +/* NV01_DEVICE_XX/NV03_DEVICE gr engine control commands and parameters */ + +/** + * NV0080_CTRL_CMD_GR_GET_CAPS + * + * This command returns the set of graphics capabilities for the device + * in the form of an array of unsigned bytes. Graphics capabilities + * include supported features and required workarounds for the graphics + * engine(s) within the device, each represented by a byte offset into the + * table and a bit position within that byte. + * + * capsTblSize + * This parameter specifies the size in bytes of the caps table. + * This value should be set to NV0080_CTRL_GR_CAPS_TBL_SIZE. + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the graphics caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + */ +#define NV0080_CTRL_CMD_GR_GET_CAPS (0x801102) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GR_GET_CAPS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_GR_GET_CAPS_PARAMS { + NvU32 capsTblSize; + NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); +} NV0080_CTRL_GR_GET_CAPS_PARAMS; + +/* extract cap bit setting from tbl */ +#define NV0080_CTRL_GR_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + + + +/* + * Size in bytes of gr caps table. This value should be one greater + * than the largest byte_index value above. + */ +#define NV0080_CTRL_GR_CAPS_TBL_SIZE 23 + + + +/* + * NV0080_CTRL_CMD_GR_INFO + * + * This structure represents a single 32bit graphics engine value. Clients + * request a particular graphics engine value by specifying a unique bus + * information index. + * + * Legal graphics information index values are: + * NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS + * This index is used to request the number of clip IDs supported by + * the device. + * NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 + * This index is used to request the minimum number of attributes that + * need to be enabled to avoid bug 261894. A return value of 0 + * indicates that there is no minimum and the bug is not present on this + * system. + */ +typedef struct NV0080_CTRL_GR_INFO { + NvU32 index; + NvU32 data; +} NV0080_CTRL_GR_INFO; + +/* valid graphics info index values */ +#define NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS (0x00000000) +#define NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 (0x00000001) +#define NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK (0x00000002) +#define NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT (0x00000003) +#define NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT (0x00000004) +#define NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE (0x00000005) +#define NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT (0x00000006) +#define NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT (0x00000007) +#define NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR (0x00000008) +#define NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT (0x00000009) +#define NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT (0x0000000A) +#define NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT (0x0000000B) +#define NV0080_CTRL_GR_INFO_INDEX_SM_VERSION (0x0000000C) +#define NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM (0x0000000D) +#define NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP (0x0000000E) +#define NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES (0x0000000F) +#define NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES (0x00000010) +#define NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY (0x00000011) +#define NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY (0x00000012) +#define NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM (0x00000013) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS (0x00000014) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS (0x00000015) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS (0x00000016) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC (0x00000017) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS (0x00000018) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS (0x00000019) +#define NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED (0x0000001A) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS (0x0000001B) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC (0x0000001C) +#define NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT (0x0000001D) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES (0x0000001E) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS (0x0000001F) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC (0x00000020) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS (0x00000021) +#define NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT (0x00000022) +#define NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT (0x00000023) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS (0x00000024) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS (0x00000025) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES (0x00000026) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC (0x00000027) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP (0x00000028) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC (0x00000029) +#define NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC (0x0000002A) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP (0x0000002B) +#define NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT (0x0000002C) +#define NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT (0x0000002D) +#define NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT (0x0000002E) + + +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC (0x00000032) + +/* When adding a new INDEX, please update MAX_SIZE accordingly + * NOTE: 0080 functionality is merged with 2080 functionality, so this max size + * reflects that. + */ +#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000032) +#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x33) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */ + +/* + * NV0080_CTRL_CMD_GR_GET_INFO + * + * This command returns graphics engine information for the associate GPU. + * Request to retrieve graphics information use a list of one or more + * NV0080_CTRL_GR_INFO structures. + * + * grInfoListSize + * This field specifies the number of entries on the caller's + * grInfoList. + * grInfoList + * This field specifies a pointer in the caller's address space + * to the buffer into which the bus information is to be returned. + * This buffer must be at least as big as grInfoListSize multiplied + * by the size of the NV0080_CTRL_GR_INFO structure. + */ +#define NV0080_CTRL_CMD_GR_GET_INFO (0x801104) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0080_CTRL_GR_GET_INFO_PARAMS { + NvU32 grInfoListSize; + NV_DECLARE_ALIGNED(NvP64 grInfoList, 8); +} NV0080_CTRL_GR_GET_INFO_PARAMS; + +/* + * NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE + * This command gets the current partition mode of a TSG context. + * + * NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE + * This command sets the partition mode of a TSG context. + * + * NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS + * This structure defines the parameters used for TPC partitioning mode SET/GET commands + * + * hChannelGroup [IN] + * RM Handle to the TSG + * + * mode [IN/OUT] + * Partitioning mode enum value + * For the SET cmd, this is an input parameter + * For the GET cmd, this is an output parameter + * + * bEnableAllTpcs [IN] + * Flag to enable all TPCs by default + * + * grRouteInfo[IN] + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + */ +#define NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE (0x801107) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | 0x7" */ + +#define NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x801108) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | 0x8" */ + +/* Enum for listing TPC partitioning modes */ +typedef enum NV0080_CTRL_GR_TPC_PARTITION_MODE { + NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE = 0, + NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC = 1, + NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC = 2, +} NV0080_CTRL_GR_TPC_PARTITION_MODE; + +typedef struct NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS { + NvHandle hChannelGroup; // [in] + NV0080_CTRL_GR_TPC_PARTITION_MODE mode; // [in/out] + NvBool bEnableAllTpcs; // [in/out] + NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); // [in] +} NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS; + +/** + * NV0080_CTRL_CMD_GR_GET_CAPS_V2 + * + * This command returns the same set of graphics capabilities for the device + * as @ref NV0080_CTRL_CMD_GR_GET_CAPS. The difference is in the structure + * NV0080_CTRL_GR_GET_INFO_V2_PARAMS, which contains a statically sized array, + * rather than a caps table pointer and a caps table size in + * NV0080_CTRL_GR_GET_INFO_PARAMS. Additionally, + * NV0080_CTRL_GR_GET_INFO_V2_PARAMS contains a parameter for specifying routing + * information, used for MIG. + * + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the graphics caps bits will be written by the RM. + * The caps table is an array of unsigned bytes. + * + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + * bCapsPopulated + * This parameter indicates that the capsTbl has been partially populated by + * previous calls to NV0080_CTRL_CMD_GR_GET_CAPS_V2 on other subdevices. + */ +#define NV0080_CTRL_CMD_GR_GET_CAPS_V2 (0x801109) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV0080_CTRL_GR_GET_CAPS_V2_PARAMS { + NvU8 capsTbl[NV0080_CTRL_GR_CAPS_TBL_SIZE]; + NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvBool bCapsPopulated; +} NV0080_CTRL_GR_GET_CAPS_V2_PARAMS; + +#define NV0080_CTRL_CMD_GR_GET_INFO_V2 (0x801110) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV0080_CTRL_GR_GET_INFO_V2_PARAMS { + NvU32 grInfoListSize; + NV0080_CTRL_GR_INFO grInfoList[NV0080_CTRL_GR_INFO_MAX_SIZE]; + NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV0080_CTRL_GR_GET_INFO_V2_PARAMS; + +/* _ctrl0080gr_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h new file mode 100644 index 0000000..096c451 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h @@ -0,0 +1,112 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080host.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE host control commands and parameters */ + +/* + * NV0080_CTRL_CMD_HOST_GET_CAPS + * + * This command returns the set of host capabilities for the device + * in the form of an array of unsigned bytes. Host capabilities + * include supported features and required workarounds for the host-related + * engine(s) within the device, each represented by a byte offset into + * the table and a bit position within that byte. + * + * capsTblSize + * This parameter specifies the size in bytes of the caps table. + * This value should be set to NV0080_CTRL_HOST_CAPS_TBL_SIZE. + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the host caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_POINTER + */ +#define NV0080_CTRL_CMD_HOST_GET_CAPS (0x801401) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_HOST_INTERFACE_ID << 8) | NV0080_CTRL_HOST_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_HOST_GET_CAPS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0080_CTRL_HOST_GET_CAPS_PARAMS { + NvU32 capsTblSize; + NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); +} NV0080_CTRL_HOST_GET_CAPS_PARAMS; + +/* extract cap bit setting from tbl */ +#define NV0080_CTRL_HOST_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* caps format is byte_index:bit_mask */ +#define NV0080_CTRL_HOST_CAPS_SEMA_ACQUIRE_BUG_105665 0:0x01 +#define NV0080_CTRL_HOST_CAPS_DUP_CMPLT_BUG_126020 0:0x02 +/* + * This bit indicates whether CPU mappings obtained with NvRmMapMemory() are + * coherent with the GPU. When this bit is _not_ set, all mappings are to the + * "raw" memory; i.e., they behave as it the NVOS33_FLAGS_MAPPING_DIRECT flag + * were used on a sysmem mapping. + */ +#define NV0080_CTRL_HOST_CAPS_GPU_COHERENT_MAPPING_SUPPORTED 0:0x04 +#define NV0080_CTRL_HOST_CAPS_SYS_SEMA_DEADLOCK_BUG_148216 0:0x08 +#define NV0080_CTRL_HOST_CAPS_SLOWSLI 0:0x10 +#define NV0080_CTRL_HOST_CAPS_SEMA_READ_ONLY_BUG 0:0x20 +#define NV0080_CTRL_HOST_CAPS_LARGE_NONCOH_UPSTR_WRITE_BUG_114871 0:0x40 +#define NV0080_CTRL_HOST_CAPS_LARGE_UPSTREAM_WRITE_BUG_115115 0:0x80 +#define NV0080_CTRL_HOST_CAPS_SEP_VIDMEM_PB_NOTIFIERS_BUG_83923 1:0x02 +#define NV0080_CTRL_HOST_CAPS_P2P_4_WAY 1:0x08 // Deprecated +#define NV0080_CTRL_HOST_CAPS_P2P_8_WAY 1:0x10 // Deprecated +#define NV0080_CTRL_HOST_CAPS_P2P_DEADLOCK_BUG_203825 1:0x20 // Deprecated +#define NV0080_CTRL_HOST_CAPS_VIRTUAL_P2P 1:0x40 +#define NV0080_CTRL_HOST_CAPS_BUG_254580 1:0x80 +#define NV0080_CTRL_HOST_CAPS_COMPRESSED_BL_P2P_BUG_257072 2:0x02 // Deprecated +#define NV0080_CTRL_HOST_CAPS_CROSS_BLITS_BUG_270260 2:0x04 // Deprecated +/* unused 2:0x08 */ +#define NV0080_CTRL_HOST_CAPS_MEM2MEM_BUG_365782 2:0x10 +#define NV0080_CTRL_HOST_CAPS_CPU_WRITE_WAR_BUG_420495 2:0x20 +#define NV0080_CTRL_HOST_CAPS_EXPLICIT_CACHE_FLUSH_REQD 2:0x40 +#define NV0080_CTRL_HOST_CAPS_BAR1_READ_DEADLOCK_BUG_511418 2:0x80 // Deprecated + +/* size in bytes of host caps table */ +#define NV0080_CTRL_HOST_CAPS_TBL_SIZE 3 + +#define NV0080_CTRL_CMD_HOST_GET_CAPS_V2 (0x801402) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_HOST_INTERFACE_ID << 8) | NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS { + NvU8 capsTbl[NV0080_CTRL_HOST_CAPS_TBL_SIZE]; +} NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS; + +/* _ctrl0080host_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h new file mode 100644 index 0000000..8607cc2 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h @@ -0,0 +1,103 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080internal.finn +// + +#include "nvlimits.h" +#include "ctrl0080gr.h" +#include "ctrl/ctrl0080/ctrl0080base.h" +#include "ctrl/ctrl0080/ctrl0080perf.h" + + + + +/*! + * @ref NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE + */ +#define NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE (0x802002) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID" */ + + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS { + NV_DECLARE_ALIGNED(NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS params, 8); +} NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS; + + +/*! + * @ref NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE + */ +#define NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE (0x802003) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID" */ + + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS { + NV_DECLARE_ALIGNED(NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS params, 8); +} NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS; + + +/*! + * @ref NV0080_CTRL_CMD_PERF_CUDA_LIMIT_SET_CONTROL + */ +#define NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_SET_CONTROL (0x802009) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS_MESSAGE_ID" */ + + +/*! + * This command disables cuda limit activation at teardown of the client. + */ +#define NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE (0x802004) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x4" */ + +/*! + * @ref NV0080_CTRL_CMD_PERF_SLI_GPU_BOOST_SYNC_SET_CONTROL + */ +#define NV0080_CTRL_CMD_INTERNAL_PERF_SLI_GPU_BOOST_SYNC_SET_CONTROL (0x802007) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID" */ + + + +/*! + * @ref NV0080_CTRL_CMD_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT + */ +#define NV0080_CTRL_CMD_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT (0x802006) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS { + NvU8 powerDisconnectedGpuBus[NV_MAX_DEVICES]; + NvU8 powerDisconnectedGpuCount; +} NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS; + +/* ctrl0080internal_h */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h new file mode 100644 index 0000000..60af5a6 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h @@ -0,0 +1,73 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080msenc.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE MSENC control commands and parameters */ + +/* + * NV0080_CTRL_CMD_MSENC_GET_CAPS + * + * This command returns the set of MSENC capabilities for the device + * in the form of an array of unsigned bytes. MSENC capabilities + * include supported features and required workarounds for the MSENC-related + * engine(s) within the device, each represented by a byte offset into + * the table and a bit position within that byte. + * + * capsTblSize + * This parameter specifies the size in bytes of the caps table. + * This value should be set to NV0080_CTRL_MSENC_CAPS_TBL_SIZE. + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the MSENC caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_MSENC_GET_CAPS (0x801b01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_MSENC_INTERFACE_ID << 8) | NV0080_CTRL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0080_CTRL_MSENC_GET_CAPS_PARAMS { + NvU32 capsTblSize; + NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); +} NV0080_CTRL_MSENC_GET_CAPS_PARAMS; + + + +/* size in bytes of MSENC caps table */ +#define NV0080_CTRL_MSENC_CAPS_TBL_SIZE 4 + +/* _ctrl0080msenc_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h new file mode 100644 index 0000000..689fe4b --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h @@ -0,0 +1,75 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080nvjpg.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE NVJPG control commands and parameters */ + + + +/* + * Size in bytes of NVJPG caps table. This value should be one greater + * than the largest byte_index value above. + */ +#define NV0080_CTRL_NVJPG_CAPS_TBL_SIZE 9 + +/* + * NV0080_CTRL_CMD_NVJPG_GET_CAPS_V2 + * + * This command returns the set of NVJPG capabilities for the device + * in the form of an array of unsigned bytes. NVJPG capabilities + * include supported features of the NVJPG engine(s) within the device, + * each represented by a byte offset into the table and a bit position within + * that byte. + * + * [out] capsTbl + * This caps table array is where the NVJPG caps bits will be transferred + * by the RM. The caps table is an array of unsigned bytes. + * instanceId + * This parameter specifies the instance Id of NVDEC for which + * cap bits are requested. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_NVJPG_GET_CAPS_V2 (0x801f02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_NVJPG_INTERFACE_ID << 8) | NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS { + NvU8 capsTbl[NV0080_CTRL_NVJPG_CAPS_TBL_SIZE]; + NvU32 instanceId; +} NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS; + +/* _ctrl0080NVJPG_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h new file mode 100644 index 0000000..3001076 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080perf.finn +// + +#define NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS { + NvBool bActivate; +} NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS; + +#define NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS { + NvBool bCudaLimit; +} NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS; + + + +/* _ctrl0080perf_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h new file mode 100644 index 0000000..100a612 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h @@ -0,0 +1,57 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080rc.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE gpu control commands and parameters */ + +/* + * NV0080_CTRL_CMD_RC_DISABLE_RESET_CHANNEL_CALLBACK + * + * This command prevents RM from using callbacks when resetting a channel due + * to a page fault. + * + * Possible status return values are: + * NV_OK + */ +#define NV0080_CTRL_CMD_RC_DISABLE_RESET_CHANNEL_CALLBACK (0x801d01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_RC_INTERFACE_ID << 8) | 0x1" */ + +/* + * NV0080_CTRL_CMD_RC_ENABLE_RESET_CHANNEL_CALLBACK + * + * This command permits RM to use callbacks when resetting a channel due + * to a page fault. + * + * Possible status return values are: + * NV_OK + */ +#define NV0080_CTRL_CMD_RC_ENABLE_RESET_CHANNEL_CALLBACK (0x801d02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_RC_INTERFACE_ID << 8) | 0x2" */ + +/* _ctrl0080rc_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h new file mode 100644 index 0000000..fbbdf73 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h @@ -0,0 +1,93 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080unix.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE UNIX-specific control commands and parameters */ + +/* + * NV0080_CTRL_CMD_OS_UNIX_VT_SWITCH + * + * This command notifies RM to save or restore the current console state. It is + * intended to be called just before the display driver starts using the display + * engine, and after it has finished using it. + * + * cmd + * Indicates which operation should be performed. + * + * SAVE_VT_STATE + * Records the current state of the console, to be restored later. + * RESTORE_VT_STATE + * Restores the previously-saved console state. + * + * fbInfo + * Returns information about the system's framebuffer console, if one + * exists. If no console is present, all fields will be zero. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_OS_UNIX_VT_SWITCH (0x801e01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS { + NvU32 cmd; /* in */ +} NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS; + +/* Called when the display driver needs RM to save the console data, + * which will be used in RM based console restore */ +#define NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_SAVE_VT_STATE (0x00000001) + +/* Called when the display driver needs RM to restore the console */ +#define NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_RESTORE_VT_STATE (0x00000002) + +/* Called when the display driver has restored the console -- RM doesn't + * need to do anything further, but needs to be informed to avoid turning the + * GPU off and thus destroying the console state. */ +#define NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_CONSOLE_RESTORED (0x00000003) + +#define NV0080_CTRL_CMD_OS_UNIX_VT_GET_FB_INFO (0x801e02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS { + NvU32 subDeviceInstance; /* out */ + + NvU16 width; /* out */ + NvU16 height; /* out */ + NvU16 depth; /* out */ + NvU16 pitch; /* out */ +} NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS; + +/* _ctrl0080unix_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0090.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0090.h new file mode 100644 index 0000000..83af684 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl0090.h @@ -0,0 +1,130 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0090.finn +// + + + +// NV0080_CTRL_GR_TPC_PARTITION_MODE +#include "ctrl/ctrl0080/ctrl0080gr.h" + +/*! + * This file defines control call interfaces for the KernelGraphicsContext + * objects Each channel running within a TSG contains a HW context represented + * by the above object(s). GR permits multiple channels to share a single + * context, and these APIs operate upon that context and may be issued from any + * TSG, channel, or context handle. + */ + +/* + * NV0090_CTRL_CMD_NULL + * + * @brief This command does nothing. + * + * @return NV_OK + */ +#define NV0090_CTRL_CMD_NULL (0x900100) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x0" */ + +/*! + * NV0090_CTRL_CMD_SET_TPC_PARTITION_MODE + * NV0090_CTRL_CMD_GET_TPC_PARTITION_MODE + * + * @brief sets or gets the TPC partition mode for this context + * + * @param[in/out] mode Partitioning mode enum value + * @param[in/out] bEnableAllTpcs Flag to enable all TPCs by default + * + * @return NV_OK on success + * NV_ERR_OBJECT_NOT_FOUND if issued on non-GR ctx + */ +typedef struct NV0090_CTRL_TPC_PARTITION_MODE_PARAMS { + NV0080_CTRL_GR_TPC_PARTITION_MODE mode; + NvBool bEnableAllTpcs; +} NV0090_CTRL_TPC_PARTITION_MODE_PARAMS; + +#define NV0090_CTRL_CMD_SET_TPC_PARTITION_MODE (0x900101) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x1" */ +#define NV0090_CTRL_CMD_INTERNAL_SET_TPC_PARTITION_MODE (0x900102) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x2" */ +#define NV0090_CTRL_CMD_GET_TPC_PARTITION_MODE (0x900103) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x3" */ +#define NV0090_CTRL_CMD_INTERNAL_GET_TPC_PARTITION_MODE (0x900104) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x4" */ + +/** + * NV0090_CTRL_GET_MMU_DEBUG_MODE + * + * @brief retrieve the current MMU debug mode for the grctx according to the HW + * + * @param[out] bMode current MMU debug mode + */ +typedef struct NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS { + NvBool bMode; +} NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS; + +#define NV0090_CTRL_CMD_GET_MMU_DEBUG_MODE (0x900105) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x5" */ +#define NV0090_CTRL_CMD_INTERNAL_GET_MMU_DEBUG_MODE (0x900106) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x6" */ + +/** + * NV0090_CTRL_PROGRAM_VIDEMEM_PROMOTE + * + * @brief This control call is used to set the promotion policies to vidmem through + * per-TSG config + * + * If the request is for less bytes than the current PROMOTE setting, then + * the request is promoted. For example if the request size is for 32B and + * 64B promotion is turned on for that unit, then the request to FB will be + * for all the bytes to the 64B aligned address. + * + * @param[in] l1 + * An input parameter which represents VIDMEM_L1_PROMOTE[17:16]. + * @param[in] t1 + * An input parameter which represents VIDMEM_T1_PROMOTE[19:18]. + * + * @return NV_OK on success, or + * NV_ERR_INVALID_ARGUMENT or + * NV_ERR_INVALID_STATE + */ +typedef enum NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE { + NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_NONE = 0, + NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_64B = 1, + NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_128B = 2, +} NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE; + +typedef struct NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD { + NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE size; +} NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD; + +#define NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS { + NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD l1; + NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD t1; +} NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS; + +#define NV0090_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE (0x900107) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x7" */ +#define NV0090_CTRL_CMD_INTERNAL_PROGRAM_VIDMEM_PROMOTE (0x900108) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x8" */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl00f8.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl00f8.h new file mode 100644 index 0000000..595b021 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl00f8.h @@ -0,0 +1,218 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl00f8.finn +// + +#include "ctrl/ctrlxxxx.h" + +#define NV00F8_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x00f8, NV00F8_CTRL_##cat, idx) + +/* NV00F8 command categories (6bits) */ +#define NV00F8_CTRL_RESERVED (0x00U) +#define NV00F8_CTRL_FABRIC (0x01U) + +/* + * NV00F8_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV00F8_CTRL_CMD_NULL (0xf80000U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV00F8_CTRL_CMD_GET_INFO + * + * Queries memory allocation attributes. + * + * size [OUT] + * Size of the allocation. + * + * pageSize [OUT] + * Page size of the allocation. + * + * allocFlags [OUT] + * Flags passed during the allocation. + * + * physAttrs [OUT] + * Physical attributes associated with memory allocation. + * For flexible mappings, it is not possible to retrieve this information, + * behavior is undefined (returns all zeros). + */ +#define NV00F8_CTRL_CMD_GET_INFO (0xf80101U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_GET_INFO_PARAMS_MESSAGE_ID" */ + +/* + * addressSpace + * Same as NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE. + * + * compressionCoverage + * Same as NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE. + */ +typedef struct NV_PHYSICAL_MEMORY_ATTRS { + NvU32 addressSpace; + NvU32 compressionCoverage; +} NV_PHYSICAL_MEMORY_ATTRS; + +#define NV00F8_CTRL_GET_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV00F8_CTRL_GET_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 pageSize; + NvU32 allocFlags; + NV_PHYSICAL_MEMORY_ATTRS physAttrs; +} NV00F8_CTRL_GET_INFO_PARAMS; + +/* + * NV00F8_CTRL_CMD_DESCRIBE + * + * Queries the physical attributes of the fabric memory allocation. + * + * offset [IN] + * Offset into memory allocation to query physical addresses for. + * + * totalPfns [OUT] + * Number of PFNs in memory allocation. + * + * pfnArray [OUT] + * Array of PFNs in memory allocation (2MB page size shifted). + * + * numPfns [OUT] + * Number of valid entries in pfnArray. + * + * Note: This ctrl call is only available for kerenl mode client in vGPU platforms. + */ + +#define NV00F8_CTRL_CMD_DESCRIBE (0xf80102) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_DESCRIBE_PARAMS_MESSAGE_ID" */ + +#define NV00F8_CTRL_DESCRIBE_PFN_ARRAY_SIZE 512 + +#define NV00F8_CTRL_DESCRIBE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV00F8_CTRL_DESCRIBE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 totalPfns, 8); + NvU32 pfnArray[NV00F8_CTRL_DESCRIBE_PFN_ARRAY_SIZE]; + NvU32 numPfns; +} NV00F8_CTRL_DESCRIBE_PARAMS; + +/* + * hMemory [IN] + * Physical memory handle to be attached. + * + * offset [IN] + * Offset into the fabric object. + * Must be physical memory pagesize aligned (at least). + * + * mapOffSet [IN] + * Offset into the physical memory descriptor. + * Must be physical memory pagesize aligned. + * + * mapLength [IN] + * Length of physical memory handle to be mapped. + * Must be physical memory pagesize aligned and less than or equal to + * fabric alloc size. + */ +typedef struct NV00F8_CTRL_ATTACH_MEM_INFO { + NvHandle hMemory; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 mapOffset, 8); + NV_DECLARE_ALIGNED(NvU64 mapLength, 8); +} NV00F8_CTRL_ATTACH_MEM_INFO; + +/* + * NV00F8_CTRL_CMD_ATTACH_MEM + * + * Attaches physical memory info to the fabric object. + * + * memInfos [IN] + * Memory infos to be attached. + * + * numMemInfos [IN] + * Number of memory infos to be attached. + * + * flags [IN] + * For future use only. Must be zero for now. + * + * numAttached [OUT] + * Successful attach count (returns a valid value on error too) + * + * Restrictions: + * a. Physical memory with 2MB pagesize is allowed + * b. Only vidmem physical memory handle can be attached + * c. Supported only for flexible fabric objects. + */ +#define NV00F8_CTRL_CMD_ATTACH_MEM (0xf80103) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_ATTACH_MEM_PARAMS_MESSAGE_ID" */ + +#define NV00F8_MAX_ATTACHABLE_MEM_INFOS 64 + +#define NV00F8_CTRL_ATTACH_MEM_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV00F8_CTRL_ATTACH_MEM_PARAMS { + NV_DECLARE_ALIGNED(NV00F8_CTRL_ATTACH_MEM_INFO memInfos[NV00F8_MAX_ATTACHABLE_MEM_INFOS], 8); + NvU16 numMemInfos; + NvU32 flags; + NvU16 numAttached; +} NV00F8_CTRL_ATTACH_MEM_PARAMS; + +/* + * NV00F8_CTRL_CMD_DETACH_MEM + * + * Detaches physical memory handle from the fabric object. + * + * offsets [IN] + * Offsets at which memory was attached. + * + * numOffsets [IN] + * Number of offsets to be detached. + * + * flags [IN] + * For future use only. Must be zero for now. + * + * numDetached [OUT] + * Successful detach count (returns a valid value on error too) + */ +#define NV00F8_CTRL_CMD_DETACH_MEM (0xf80104) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_DETACH_MEM_PARAMS_MESSAGE_ID" */ + +#define NV00F8_MAX_DETACHABLE_OFFSETS 64 + +#define NV00F8_CTRL_DETACH_MEM_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV00F8_CTRL_DETACH_MEM_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offsets[NV00F8_MAX_DETACHABLE_OFFSETS], 8); + NvU16 numOffsets; + NvU32 flags; + NvU16 numDetached; +} NV00F8_CTRL_DETACH_MEM_PARAMS; + +/* _ctrl00f8_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl00fd.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl00fd.h new file mode 100644 index 0000000..7ba86f8 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl00fd.h @@ -0,0 +1,160 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl00fd.finn +// + +#include "ctrl/ctrlxxxx.h" + +#define NV00FD_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x00fd, NV00FD_CTRL_##cat, idx) + +/* NV00FD command categories (6bits) */ +#define NV00FD_CTRL_RESERVED (0x00) +#define NV00FD_CTRL_MULTICAST_FABRIC (0x01) + +/* + * NV00FD_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV00FD_CTRL_CMD_NULL (0xfd0000) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV00FD_CTRL_CMD_GET_INFO + * + * Queries multicast memory fabric allocation attributes. + * + * alignment [OUT] + * Alignment for the allocation. + * + * allocSize [OUT] + * Size of the allocation. + * + * pageSize [OUT] + * Page size of the allocation. + * + * numMaxGpus [OUT] + * Maximum number of attachable GPUs + * + * numAttachedGpus [OUT] + * Number of GPUs currently attached + * + */ +#define NV00FD_CTRL_CMD_GET_INFO (0xfd0101) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV00FD_CTRL_GET_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV00FD_CTRL_GET_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 alignment, 8); + NV_DECLARE_ALIGNED(NvU64 allocSize, 8); + NvU32 pageSize; + NvU32 numMaxGpus; + NvU32 numAttachedGpus; +} NV00FD_CTRL_GET_INFO_PARAMS; + +/* + * NV00FD_CTRL_CMD_ATTACH_MEM + * + * Attaches the physical memory handle and in turn the memory + * owner of the physical memory to the Multicast FLA object. + * + * hSubdevice [IN] + * Subdevice handle of the owner GPU + * + * hMemory [IN] + * Physical memory handle to be attached. + * + * offset [IN] + * Offset into the MCFLA object. (Must be zero for now, maybe used in future) + * Must be MCFLA pagesize aligned. + * + * mapOffSet [IN] + * Offset into the physical memory descriptor. + * Must be physical memory pagesize aligned. + * + * mapLength [IN] + * Length of physical memory handle to be mapped. + * Must be physical memory pagesize aligned and less than or equal to + * MCFLA alloc size + * + * flags [IN] + * For future use only. Must be zero for now. + * + * devDescriptor [IN] + * devDescriptor is a file descriptor for unix RM clients, but a void + * pointer for windows RM clients. It is transparent to RM clients i.e. RM's + * user-mode shim populates this field on behalf of clients. + * + * Restrictions: + * a. Memory belonging to only NVSwitch P2P supported GPUs + * which can do multicast can be attached + * b. Physical memory with 2MB pagesize is allowed + * c. Memory of an already attached GPU should not be attached + * d. Only vidmem physical memory handle can be attached + * + */ +#define NV00FD_CTRL_CMD_ATTACH_MEM (0xfd0102) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_ATTACH_MEM_PARAMS_MESSAGE_ID" */ + +#define NV00FD_CTRL_ATTACH_MEM_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV00FD_CTRL_ATTACH_MEM_PARAMS { + NvHandle hSubdevice; + NvHandle hMemory; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 mapOffset, 8); + NV_DECLARE_ALIGNED(NvU64 mapLength, 8); + NvU32 flags; + NV_DECLARE_ALIGNED(NvU64 devDescriptor, 8); +} NV00FD_CTRL_ATTACH_MEM_PARAMS; + +/* + * NV00FD_CTRL_CMD_REGISTER_EVENT + * + * Allows clients to optionally register for events after the Multicast + * FLA object is duped under another client. + * + * pOsEvent [IN] + * OS event handle created with NvRmAllocOsEvent(). + * + */ +#define NV00FD_CTRL_CMD_REGISTER_EVENT (0xfd0103) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_REGISTER_EVENT_PARAMS_MESSAGE_ID" */ + +#define NV00FD_CTRL_REGISTER_EVENT_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV00FD_CTRL_REGISTER_EVENT_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pOsEvent, 8); +} NV00FD_CTRL_REGISTER_EVENT_PARAMS; + +/* _ctrl00fd_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl00fe.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl00fe.h new file mode 100644 index 0000000..2be1a04 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl00fe.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl00fe.finn +// + +#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_FLAG_PAGE_KIND_SOURCE_ALLOCATION 0:0 +#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_FLAG_PAGE_KIND_SOURCE_ALLOCATION_PHYSICAL (0x00000000U) +#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_FLAG_PAGE_KIND_SOURCE_ALLOCATION_VIRTUAL (0x00000001U) + +typedef struct NV00FE_CTRL_PAGING_OPERATION { + NvHandle hVirtualMemory; + NV_DECLARE_ALIGNED(NvU64 virtualOffset, 8); + NvHandle hPhysicalMemory; + NV_DECLARE_ALIGNED(NvU64 physicalOffset, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 flags; +} NV00FE_CTRL_PAGING_OPERATION; + +/* + * NV00FE_CTRL_CMD_SUBMIT_PAGING_OPERATIONS + * + * Execute a list of paging operations + * Page size is determined by the virtual allocation + * Offsets/sizes must respect the page size + * + */ +#define NV00FE_CTRL_CMD_SUBMIT_PAGING_OPERATIONS (0xfe0002U) /* finn: Evaluated from "(FINN_NV_MEMORY_MAPPER_INTERFACE_ID << 8) | NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS_MESSAGE_ID" */ + +#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_MAX_COUNT (0x00010000U) + +#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS { + NvU32 pagingOpsCount; + NV_DECLARE_ALIGNED(NvP64 pagingOps, 8); +} NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS; + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080.h new file mode 100644 index 0000000..05f19cf --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080.h @@ -0,0 +1,84 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080.finn +// + + + + +#include "ctrl/ctrlxxxx.h" +#include "ctrl2080/ctrl2080gpu.h" +#include "ctrl2080/ctrl2080fuse.h" +#include "ctrl2080/ctrl2080event.h" +#include "ctrl2080/ctrl2080tmr.h" +#include "ctrl2080/ctrl2080bios.h" +#include "ctrl2080/ctrl2080mc.h" +#include "ctrl2080/ctrl2080fifo.h" +#include "ctrl2080/ctrl2080fb.h" + + +#include "ctrl2080/ctrl2080gr.h" +#include "ctrl2080/ctrl2080bus.h" +#include "ctrl2080/ctrl2080thermal.h" +#include "ctrl2080/ctrl2080fan.h" +#include "ctrl2080/ctrl2080i2c.h" +#include "ctrl2080/ctrl2080internal.h" +#include "ctrl2080/ctrl2080spi.h" +#include "ctrl2080/ctrl2080gpio.h" +#include "ctrl2080/ctrl2080clk.h" +#include "ctrl2080/ctrl2080perf.h" +#include "ctrl2080/ctrl2080perf_cf.h" + + +#include "ctrl2080/ctrl2080rc.h" +#include "ctrl2080/ctrl2080dma.h" +#include "ctrl2080/ctrl2080dmabuf.h" +#include "ctrl2080/ctrl2080nvd.h" +#include "ctrl2080/ctrl2080boardobj.h" +#include "ctrl2080/ctrl2080pmgr.h" +#include "ctrl2080/ctrl2080power.h" +#include "ctrl2080/ctrl2080lpwr.h" +#include "ctrl2080/ctrl2080acr.h" +#include "ctrl2080/ctrl2080ce.h" +#include "ctrl2080/ctrl2080nvlink.h" +#include "ctrl2080/ctrl2080flcn.h" +#include "ctrl2080/ctrl2080volt.h" +#include "ctrl2080/ctrl2080ecc.h" +#include "ctrl2080/ctrl2080cipher.h" +#include "ctrl2080/ctrl2080fla.h" +#include "ctrl2080/ctrl2080gsp.h" + + +#include "ctrl2080/ctrl2080grmgr.h" +#include "ctrl2080/ctrl2080ucodefuzzer.h" +#include "ctrl2080/ctrl2080vgpumgrinternal.h" +#include "ctrl2080/ctrl2080hshub.h" +/* include appropriate os-specific command header */ + + +#include "ctrl2080/ctrl2080unix.h" diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080acr.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080acr.h new file mode 100644 index 0000000..322e119 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080acr.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080acr.finn +// + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h new file mode 100644 index 0000000..7df6a6d --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h @@ -0,0 +1,112 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080base.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV20_SUBDEVICE_XX control commands and parameters */ + +#define NV2080_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x2080, NV2080_CTRL_##cat, idx) + +/* Subdevice command categories (6bits) */ +#define NV2080_CTRL_RESERVED (0x00) +#define NV2080_CTRL_GPU (0x01) +#define NV2080_CTRL_GPU_LEGACY_NON_PRIVILEGED (0x81) /* finn: Evaluated from "(NV2080_CTRL_GPU | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_FUSE (0x02) +#define NV2080_CTRL_FUSE_LEGACY_NON_PRIVILEGED (0x82) /* finn: Evaluated from "(NV2080_CTRL_FUSE | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_EVENT (0x03) +#define NV2080_CTRL_TIMER (0x04) +#define NV2080_CTRL_THERMAL (0x05) +#define NV2080_CTRL_THERMAL_LEGACY_PRIVILEGED (0xc5) /* finn: Evaluated from "(NV2080_CTRL_THERMAL | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */ +#define NV2080_CTRL_THERMAL_LEGACY_NON_PRIVILEGED (0x85) /* finn: Evaluated from "(NV2080_CTRL_THERMAL | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_I2C (0x06) +#define NV2080_CTRL_EXTI2C (0x07) +#define NV2080_CTRL_BIOS (0x08) +#define NV2080_CTRL_CIPHER (0x09) +#define NV2080_CTRL_INTERNAL (0x0A) +#define NV2080_CTRL_CLK_LEGACY_PRIVILEGED (0xd0) /* finn: Evaluated from "(NV2080_CTRL_CLK | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */ +#define NV2080_CTRL_CLK_LEGACY_NON_PRIVILEGED (0x90) /* finn: Evaluated from "(NV2080_CTRL_CLK | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_CLK (0x10) +#define NV2080_CTRL_FIFO (0x11) +#define NV2080_CTRL_GR (0x12) +#define NV2080_CTRL_FB (0x13) +#define NV2080_CTRL_MC (0x17) +#define NV2080_CTRL_BUS (0x18) +#define NV2080_CTRL_PERF_LEGACY_PRIVILEGED (0xe0) /* finn: Evaluated from "(NV2080_CTRL_PERF | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */ +#define NV2080_CTRL_PERF_LEGACY_NON_PRIVILEGED (0xa0) /* finn: Evaluated from "(NV2080_CTRL_PERF | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_PERF (0x20) +#define NV2080_CTRL_NVIF (0x21) +#define NV2080_CTRL_RC (0x22) +#define NV2080_CTRL_GPIO (0x23) +#define NV2080_CTRL_GPIO_LEGACY_NON_PRIVILEGED (0xa3) /* finn: Evaluated from "(NV2080_CTRL_GPIO | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_NVD (0x24) +#define NV2080_CTRL_DMA (0x25) +#define NV2080_CTRL_PMGR (0x26) +#define NV2080_CTRL_PMGR_LEGACY_PRIVILEGED (0xe6) /* finn: Evaluated from "(NV2080_CTRL_PMGR | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */ +#define NV2080_CTRL_PMGR_LEGACY_NON_PRIVILEGED (0xa6) /* finn: Evaluated from "(NV2080_CTRL_PMGR | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_POWER (0x27) +#define NV2080_CTRL_POWER_LEGACY_NON_PRIVILEGED (0xa7) /* finn: Evaluated from "(NV2080_CTRL_POWER | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_LPWR (0x28) +#define NV2080_CTRL_LPWR_LEGACY_NON_PRIVILEGED (0xa8) /* finn: Evaluated from "(NV2080_CTRL_LPWR | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_LPWR_LEGACY_PRIVILEGED (0xe8) /* finn: Evaluated from "(NV2080_CTRL_LPWR | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */ +#define NV2080_CTRL_ACR (0x29) +#define NV2080_CTRL_CE (0x2A) +#define NV2080_CTRL_SPI (0x2B) +#define NV2080_CTRL_NVLINK (0x30) +#define NV2080_CTRL_FLCN (0x31) +#define NV2080_CTRL_VOLT (0x32) +#define NV2080_CTRL_VOLT_LEGACY_PRIVILEGED (0xf2) /* finn: Evaluated from "(NV2080_CTRL_VOLT | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */ +#define NV2080_CTRL_VOLT_LEGACY_NON_PRIVILEGED (0xb2) /* finn: Evaluated from "(NV2080_CTRL_VOLT | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_FAS (0x33) +#define NV2080_CTRL_ECC (0x34) +#define NV2080_CTRL_ECC_NON_PRIVILEGED (0xb4) /* finn: Evaluated from "(NV2080_CTRL_ECC | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_FLA (0x35) +#define NV2080_CTRL_GSP (0x36) +#define NV2080_CTRL_NNE (0x37) +#define NV2080_CTRL_GRMGR (0x38) +#define NV2080_CTRL_UCODE_FUZZER (0x39) +#define NV2080_CTRL_DMABUF (0x3A) + +// per-OS categories start at highest category and work backwards +#define NV2080_CTRL_OS_WINDOWS (0x3F) +#define NV2080_CTRL_OS_MACOS (0x3E) +#define NV2080_CTRL_OS_UNIX (0x3D) + + +/* + * NV2080_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_NULL (0x20800000) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrl2080base_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h new file mode 100644 index 0000000..cf58350 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h @@ -0,0 +1,477 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080bios.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX bios-related control commands and parameters */ + + + +typedef struct NV2080_CTRL_BIOS_INFO { + NvU32 index; + NvU32 data; +} NV2080_CTRL_BIOS_INFO; + +/* Maximum number of bios infos that can be queried at once */ +#define NV2080_CTRL_BIOS_INFO_MAX_SIZE (0x0000000F) + +#define NV2080_CTRL_BIOS_INFO_INDEX_REVISION (0x00000000) +#define NV2080_CTRL_BIOS_INFO_INDEX_OEM_REVISION (0x00000001) + + + +/* + * NV2080_CTRL_CMD_BIOS_GET_INFO + * + * This command returns bios information for the associated GPU. + * Requests to retrieve bios information use a list of one or more + * NV2080_CTRL_BIOS_INFO structures. + * + * biosInfoListSize + * This field specifies the number of entries on the caller's + * biosInfoList. + * biosInfoList + * This field specifies a pointer in the caller's address space + * to the buffer into which the bios information is to be returned. + * This buffer must be at least as big as biosInfoListSize multiplied + * by the size of the NV2080_CTRL_BIOS_INFO structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV2080_CTRL_CMD_BIOS_GET_INFO (0x20800802) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | 0x2" */ + +typedef struct NV2080_CTRL_BIOS_GET_INFO_PARAMS { + NvU32 biosInfoListSize; + NV_DECLARE_ALIGNED(NvP64 biosInfoList, 8); +} NV2080_CTRL_BIOS_GET_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_BIOS_GET_INFO_V2 + * + * This command returns bios information for the associated GPU. + * Requests to retrieve bios information use a list of one or more + * NV2080_CTRL_BIOS_INFO structures. + * + * biosInfoListSize + * This field specifies the number of entries on the caller's + * biosInfoList. + * biosInfoList + * Bios information to be returned. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV2080_CTRL_CMD_BIOS_GET_INFO_V2 (0x20800810) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS { + NvU32 biosInfoListSize; + NV2080_CTRL_BIOS_INFO biosInfoList[NV2080_CTRL_BIOS_INFO_MAX_SIZE]; +} NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS; + +/* + * NV2080_CTRL_BIOS_NBSI + * + * NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH + * This is the maximum length of a given registry string input (in characters). + * + * NV2080_CTRL_BIOS_NBSI_STRING_TYPE_ASCII + * This is a value indicating the format of a registry string is ascii. + * NV2080_CTRL_BIOS_NBSI_STRING_TYPE_UNICODE + * This is a value indicating the format of a registry string is unicode. + * NV2080_CTRL_BIOS_NBSI_STRING_TYPE_HASH + * This is a value indicating a registry string is actually a pre-hashed value. + * + * NV2080_CTRL_BIOS_NBSI_REG_STRING + * This is a structure used to store a registry string object. + * The members are as follows: + * + * size + * This is the size (in bytes) of the data contained in the string. If this + * is greater than the maximum registry string length, an error will be + * returned. + * type + * This is the type of data contained in the registry string. It can be either + * ascii, unicode or a pre-hashed value. + * value + * This is the value of the string. Depending on the type, a different object + * will be used to access the data. + */ +#define NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH (0x00000100) + +#define NV2080_CTRL_BIOS_NBSI_STRING_TYPE_ASCII (0x00000000) +#define NV2080_CTRL_BIOS_NBSI_STRING_TYPE_UNICODE (0x00000001) +#define NV2080_CTRL_BIOS_NBSI_STRING_TYPE_HASH (0x00000002) + +#define NV2080_CTRL_BIOS_NBSI_MODULE_ROOT (0x00000000) +#define NV2080_CTRL_BIOS_NBSI_MODULE_RM (0x00000001) +#define NV2080_CTRL_BIOS_NBSI_MODULE_DISPLAYDRIVER (0x00000002) +#define NV2080_CTRL_BIOS_NBSI_MODULE_VIDEO (0x00000003) +#define NV2080_CTRL_BIOS_NBSI_MODULE_CPL (0x00000004) +#define NV2080_CTRL_BIOS_NBSI_MODULE_D3D (0x00000005) +#define NV2080_CTRL_BIOS_NBSI_MODULE_OGL (0x00000006) +#define NV2080_CTRL_BIOS_NBSI_MODULE_PMU (0x00000007) +#define NV2080_CTRL_BIOS_NBSI_MODULE_MODE (0x00000008) +// this should equal the last NBSI_MODULE plus 1. +#define NV2080_CTRL_BIOS_NBSI_NUM_MODULES (0x00000009) + +// +// Never use this value! It's needed for DD/Video modules, but does not correspond +// to a valid NBSI hive! +// +#define NV2080_CTRL_BIOS_NBSI_MODULE_UNKNOWN (0x80000000) + +typedef struct NV2080_CTRL_BIOS_NBSI_REG_STRING { + NvU32 size; + NvU32 type; + + union { + NvU8 ascii[NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH]; + NvU16 unicode[NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH]; + NvU16 hash; + } value; +} NV2080_CTRL_BIOS_NBSI_REG_STRING; + + +/* + * NV2080_CTRL_CMD_BIOS_GET_NBSI + * + * module + * This field specifies the given module per the MODULE_TYPES enum. + * path + * This field specifies the full path and registry node name for a + * given NBSI object. This is a maximum of 255 unicode characters, + * but may be provided as ascii or a pre-formed hash per the type + * member. The size (in bytes) of the given string/hash should be + * provided in the size member. + * + * NOTE: In the case of an incomplete path such as HKR, one may pass + * in simply the root node. E.g.: + * 1.) Normal case: HKLM\Path\Subpath + * 2.) Unknown case: HKR + * It is expected that all unknown/incomplete paths will be determined + * prior to NBSI programming! There is otherwise NO WAY to match + * the hash given by an incomplete path to that stored in NBSI! + * + * valueName + * This field specifies the registry name for a given NBSI object. + * This is a maximum of 255 unicode characters, but may be provided + * in ascii or a pre-formed hash per the type member. The size (in bytes) + * of the given string/hash should be provided in the size member. + * retBuf + * This field provides a pointer to a buffer into which the value + * retrieved from NBSI may be returned + * retSize + * This field is an input/output. It specifies the maximum size of the + * return buffer as an input, and the size of the returned data as an + * output. + * errorCode + * This field is a return value. It gives an error code representing + * failure to return a value (as opposed to failure of the call). + * This obeys the following: + * + * NV2080_CTRL_BIOS_GET_NBSI_SUCCESS + * The call has returned complete and valid data. + * NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE + * The call returned complete and valid data which is expected to override + * any stored registry settings. + * NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE + * The call returned data, but the size of the return buffer was + * insufficient to contain it. The value returned in retSize represents + * the total size necessary (in bytes) to contain the data. + * if the size was non-0, the buffer is filled with the object contents up + * to that size. Can be used with retBufOffset to use multiple calls to get + * tables of very large size. + * NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND + * The call did not find a valid NBSI object for this key. This indicates + * NBSI has no opinion and, more importantly, any data returned is identical + * to data passed in. + * + * Possible return values are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_BIOS_GET_NBSI_SUCCESS (0x00000000) +#define NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE (0x00000001) +#define NV2080_CTRL_BIOS_GET_NBSI_BAD_HASH (0xFFFFFFFA) +#define NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS (0xFFFFFFFB) +#define NV2080_CTRL_BIOS_GET_NBSI_BAD_TABLE (0xFFFFFFFC) +#define NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE (0xFFFFFFFD) +#define NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE (0xFFFFFFFE) +#define NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND (0xFFFFFFFF) + +#define NV2080_CTRL_CMD_BIOS_GET_NBSI (0x20800803) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_NBSI_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BIOS_GET_NBSI_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_BIOS_GET_NBSI_PARAMS { + NvU32 module; + NV2080_CTRL_BIOS_NBSI_REG_STRING path; + NV2080_CTRL_BIOS_NBSI_REG_STRING valueName; + NV_DECLARE_ALIGNED(NvP64 retBuf, 8); + NvU32 retSize; + NvU32 errorCode; +} NV2080_CTRL_BIOS_GET_NBSI_PARAMS; + +#define NV2080_CTRL_CMD_BIOS_GET_NBSI_V2 (0x2080080e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_BIOS_GET_NBSI_MAX_RET_SIZE (0x100) + +#define NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS { + NvU32 module; + NV2080_CTRL_BIOS_NBSI_REG_STRING path; + NV2080_CTRL_BIOS_NBSI_REG_STRING valueName; + NvU8 retBuf[NV2080_BIOS_GET_NBSI_MAX_RET_SIZE]; + NvU32 retSize; + NvU32 errorCode; +} NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS; + +/* + * NV2080_CTRL_CMD_BIOS_GET_NBSI_OBJ + * + * globType + * This field specifies the glob type wanted + * 0xffff: APItest... returns NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS + * globIndex + * Index for globType desired + * 0 = best fit + * 1..255 = actual index + * globSource + * Index to nbsi directory sources used when getting entire directory + * 0 = registry + * 1 = VBIOS + * 2 = SBIOS + * 3 = ACPI + * retBufOffset + * When making multiple calls to get the object (if retSize is too small) + * offset into real object (0=start of object) + * retBuf + * This field provides a pointer to a buffer into which the object + * retrieved from NBSI may be returned + * retSize + * This field is an input/output. It specifies the maximum size of the + * return buffer as an input, and the size of the returned data as an + * output. + * totalObjSize + * This field is an output, where the total size of the object being + * retrieved is returned. + * errorCode + * This field is a return value. It gives an error code representing + * failure to return a value (as opposed to failure of the call). + * This obeys the following: + * + * NV2080_CTRL_BIOS_GET_NBSI_SUCCESS + * The call has returned complete and valid data. + * NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE + * The call returned complete and valid data which is expected to override + * any stored registry settings. + * NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE + * The call returned data, but the size of the return buffer was + * insufficient to contain it. The value returned in retSize represents + * the total size necessary (in bytes) to contain the data. + * NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND + * The call did not find a valid NBSI object for this key. This indicates + * NBSI has no opinion and, more importantly, any data returned is identical + * to data passed in. + * + * Possible return values are: + * NV2080_CTRL_BIOS_GET_NBSI_SUCCESS + * NV2080_CTRL_BIOS_GET_NBSI_APITEST_NODIRACCESS + * NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS + * NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE + * NV2080_CTRL_BIOS_GET_NBSI_BAD_TABLE + * NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE + * NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND + */ +#define NV2080_CTRL_CMD_BIOS_GET_NBSI_OBJ (0x20800806) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS { + NvU16 globType; + NvU8 globIndex; + NvU16 globSource; + NvU32 retBufOffset; + NV_DECLARE_ALIGNED(NvP64 retBuf, 8); + NvU32 retSize; + NvU32 totalObjSize; + NvU32 errorCode; +} NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS; + +#define GLOB_TYPE_GET_NBSI_DIR 0xfffe +#define GLOB_TYPE_APITEST 0xffff +#define GLOB_TYPE_GET_NBSI_ACPI_RAW 0xfffd + + + +/* + * NV2080_CTRL_CMD_BIOS_GET_SKU_INFO + * + * This command returns information about the current board SKU. + * NV_ERR_INVALID_OWNER will be returned if the call + * isn't made with the OS as the administrator. + * + * chipSKU + * This field returns the sku for the current chip. + * chipSKUMod + * This field returns the SKU modifier. + * project + * This field returns the Project (Board) number. + * projectSKU + * This field returns the Project (Board) SKU number. + * CDP + * This field returns the Collaborative Design Project Number. + * projectSKUMod + * This field returns the Project (Board) SKU Modifier. + * businessCycle + * This field returns the business cycle the board is associated with. + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OWNER + */ +#define NV2080_CTRL_CMD_BIOS_GET_SKU_INFO (0x20800808) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID" */ + +/* maximum length of parameter strings */ + + +#define NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS { + NvU32 BoardID; + char chipSKU[4]; + char chipSKUMod[2]; + char project[5]; + char projectSKU[5]; + char CDP[6]; + char projectSKUMod[2]; + NvU32 businessCycle; +} NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_BIOS_GET_POST_TIME + + * This command is used to get the GPU POST time (in milliseconds). + * If the associated GPU is the master GPU this value will be recorded + * by the VBIOS and retrieved from the KDA buffer. If the associated + * GPU is a secondaryGPU then this value will reflect the devinit + * processing time. + * + * vbiosPostTime + * This parameter returns the vbios post time in msec. + * + * Possible return status values are + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV2080_CTRL_CMD_BIOS_GET_POST_TIME (0x20800809) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS { + NV_DECLARE_ALIGNED(NvU64 vbiosPostTime, 8); +} NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS; + + + +/* + * NV2080_CTRL_CMD_BIOS_GET_UEFI_SUPPORT + * + * This function is used to give out the UEFI version, UEFI image presence and + * Graphics Firmware Mode i.e. whether system is running in UEFI or not. + * + * version + * This parameter returns the UEFI version. + * + * flags + * This parameter indicates UEFI image presence and Graphics Firmware mode. + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE + * This field returns UEFI presence value. Legal values for this + * field include: + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_NO + * This value indicates that UEFI image is not present. + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_YES + * This value indicates that UEFI image is present. + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_PLACEHOLDER + * This value indicates that there is a dummy UEFI placeholder, + * which can later be updated with a valid UEFI image. + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_HIDDEN + * This value indicates that UEFI image is hidden. + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING + * This field indicates the UEFI running value. Legal values for + * this parameter include: + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_FALSE + * This value indicates that UEFI is not running. + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE + * This value indicates that UEFI is running. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_READY + * NV_ERR_INVALID_STATE + */ + +#define NV2080_CTRL_CMD_BIOS_GET_UEFI_SUPPORT (0x2080080b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS { + NvU32 version; + NvU32 flags; +} NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS; + +/* Legal values for flags parameter */ +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE 1:0 +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_NO (0x00000000) +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_YES (0x00000001) +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_PLACEHOLDER (0x00000002) +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_HIDDEN (0x00000003) +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING 2:2 +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_FALSE (0x00000000) +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE (0x00000001) + + + +/* _ctrl2080bios_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobj.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobj.h new file mode 100644 index 0000000..6f69c5c --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobj.h @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080boardobj.finn +// + + + +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h" + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h new file mode 100644 index 0000000..caafd74 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080boardobjgrpclasses.finn +// + + + +#include "nvtypes.h" + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h new file mode 100644 index 0000000..eb8d979 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h @@ -0,0 +1,1588 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080bus.finn +// + +#include "nvcfg_sdk.h" +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX bus control commands and parameters */ + +/** + * NV2080_CTRL_CMD_BUS_GET_PCI_INFO + * + * This command returns PCI bus identifier information for the specified GPU. + * + * pciDeviceId + * This parameter specifies the internal PCI device and vendor + * identifiers for the GPU. + * pciSubSystemId + * This parameter specifies the internal PCI subsystem identifier for + * the GPU. + * pciRevisionId + * This parameter specifies the internal PCI device-specific revision + * identifier for the GPU. + * pciExtDeviceId + * This parameter specifies the external PCI device identifier for + * the GPU. It contains only the 16-bit device identifier. This + * value is identical to the device identifier portion of + * pciDeviceId since non-transparent bridges are no longer supported. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_BUS_GET_PCI_INFO (0x20801801) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS { + NvU32 pciDeviceId; + NvU32 pciSubSystemId; + NvU32 pciRevisionId; + NvU32 pciExtDeviceId; +} NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS; + +/* + * NV2080_CTRL_BUS_INFO + * + * This structure represents a single 32bit bus engine value. Clients + * request a particular bus engine value by specifying a unique bus + * information index. + * + * Legal bus information index values are: + * NV2080_CTRL_BUS_INFO_INDEX_TYPE + * This index is used to request the bus type of the GPU. + * Legal return values for this index are: + * NV2080_CTRL_BUS_INFO_TYPE_PCI + * NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS + * NV2080_CTRL_BUS_INFO_TYPE_FPCI + * NV2080_CTRL_BUS_INFO_INDEX_INTLINE + * This index is used to request the interrupt line (or irq) assignment + * for the GPU. The return value is system-dependent. + * NV2080_CTRL_BUS_INFO_INDEX_CAPS + * This index is used to request the bus engine capabilities for the GPU. + * The return value is specified as a mask of capabilities. + * Legal return values for this index are: + * NV2080_CTRL_BUS_INFO_CAPS_NEED_IO_FLUSH + * NV2080_CTRL_BUS_INFO_CAPS_CHIP_INTEGRATED + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CAPS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CAPS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CAPS + * These indices are used to request PCI Express link-specific + * capabilities values. A value of zero is returned for non-PCIE GPUs. + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CTRL_STATUS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CTRL_STATUS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CTRL_STATUS + * These indices are used to request PCI Express link-specific + * control status values. A value of zero is returned for non-PCIE GPUs. + * NV2080_CTRL_BUS_INFO_INDEX_COHERENT_DMA_FLAGS + * This index is used to request coherent dma transfer flags. + * Valid coherent dma transfer flags include: + * NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA + * NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART + * NV2080_CTRL_BUS_INFO_INDEX_NONCOHERENT_DMA_FLAGS + * This index is used to request noncoherent dma transfer flags. + * Valid noncoherent dma transfer flags include: + * NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA + * NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART + * NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE + * NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE + * This index is used to request the size of the GPU GART in MBytes. + * NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_FLAGS + * This index is used to request GPU GART flags. + * Valid gart flags include: + * NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH + * This flag indicates that GPU GART clients need to do an explicit + * flush via an appropriate SetContextDma method. + * NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED + * This flag indicates that the GART address range includes both + * system and video memory. + * NV2080_CTRL_BUS_INFO_INDEX_BUS_NUMBER + * This index is used to request the PCI-based bus number of the GPU. + * Support for this index is platform-dependent. + * NV2080_CTRL_BUS_INFO_INDEX_DEVICE_NUMBER + * This index is used to request the PCI-based device number of the GPU. + * Support for this index is platform-dependent. + * NV2080_CTRL_BUS_INFO_INDEX_DOMAIN_NUMBER + * This index is used to request the PCI-based domain number of the GPU. + * Support for this index is platform-dependent. + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_ERRORS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_ERRORS + * These indices are used to request PCI Express error status. + * The current status is cleared as part of these requests. + * Valid PCI Express error status values include: + * NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR + * NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_NON_FATAL_ERROR + * NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_FATAL_ERROR + * NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_UNSUPP_REQUEST + * NV2080_CTRL_BUS_INFO_INDEX_INTERFACE_TYPE + * This index is used to request the bus interface type of the GPU. + * Legal return values for this index are: + * NV2080_CTRL_BUS_INFO_TYPE_PCI + * NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS + * NV2080_CTRL_BUS_INFO_TYPE_FPCI + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_INFO // DEPRECATED + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN_INFO // REPLACES "GEN2" variant + * This index is used to retrieve PCI Express Gen configuration support + * This index is used to retrieve PCI Express Gen2 configuration support + * for the GPU. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN1 + * The GPU is PCI Express Gen1 capable. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN2 + * The GPU is PCI Express Gen2 capable. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN3 + * The GPU is PCI Express Gen3 capable. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN4 + * The GPU is PCI Express Gen4 capable. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN5 + * The GPU is PCI Express Gen5 capable. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN1 + * The GPU is configured in PCI Express Gen1 mode. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN2 + * The GPU is configured in PCI Express Gen2 mode. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN3 + * The GPU is configured in PCI Express Gen3 mode. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN4 + * The GPU is configured in PCI Express Gen4 mode. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN5 + * The GPU is configured in PCI Express Gen5 mode. + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_AER + * This index retrieves PCI Express Advanced Error Reporting (AER) errors + * for the GPU. + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CAPS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CAPS + * This index retrieves the PCI Express link capabilities for the + * board. For example, a Quadro FX4700X2 has two GPUs and PCIe + * switch. With this board, this index returns the link + * capabilities of the PCIe switch. In a single GPU board, this + * index returns the link capabilities of the GPU. A value of + * zero is returned for non-PCIE GPUs. + * UPSTREAM_LINK_CAPS is kept for backwards compatibility. + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CTRL_STATUS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CTRL_STATUS + * This index retrieves the PCI Express link status for the board. + * For example, a Quadro FX4700X2 has two GPUs and PCIe switch. + * With this board, this index returns the link capabilities of + * the PCIe switch. In a single GPU board, this index returns the + * link status of the GPU. A value of zero is returned for + * non-PCIE GPUs. + * UPSTREAM_LINK_CTRL_STATUS is kept for backwards compatibility. + * NV2080_CTRL_BUS_INFO_INDEX_ASLM_STATUS + * This index is used to request the PCI Express ASLM settings. + * This index is only valid when NV2080_CTRL_BUS_INFO_TYPE indicates PCIE. + * A value of zero is returned for non-PCI Express bus type. + * _ASLM_STATUS_PCIE is always _PRESENT if PCI Express bus type. + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_WIDTH_SWITCH_ERROR_COUNT + * This index is used to get the ASLM switching error count. + * A value of zero will be returned if no errors occurs while + * ASLM switching + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_SWITCH_ERROR_COUNT + * This index is used to get the Gen1<-->Gen2 switching error count + * A value of zero will be returned in case speed change from Gen1 to + * Gen2 is clean or if chipset is not gen2 capable or if gen1<-->gen2 + * switching is disabled. + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_CYA_ASPM + * This index is used to get the ASPM CYA L0s\L1 enable\disable status. + * Legal return value is specified as a mask of valid and data field + * possible return values are: + * NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_NO + * NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_YES + * NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_DISABLED + * NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S + * NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L1 + * NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S_L1 + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS + * These indices are used to request detailed PCI Express error counters. + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS_CLEAR + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS_CLEAR + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED_CLEAR + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS_CLEAR + * These indices are used to clear detailed PCI Express error counters. + * NV2080_CTRL_BUS_INFO_INDEX_GPU_INTERFACE_TYPE + * This index is used to request the internal interface type of the GPU. + * Legal return values for this index are: + * NV2080_CTRL_BUS_INFO_TYPE_PCI + * NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS + * NV2080_CTRL_BUS_INFO_TYPE_FPCI + * NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE + * This index queries the type of sysmem connection to CPU + * NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE + * NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK + * NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C + * + */ + +typedef struct NV2080_CTRL_BUS_INFO { + NvU32 index; + NvU32 data; +} NV2080_CTRL_BUS_INFO; + +/* valid bus info index values */ + +/** + * This index is used to request the bus type of the GPU. + * Legal return values for this index are: + * NV2080_CTRL_BUS_INFO_TYPE_PCI + * NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS + * NV2080_CTRL_BUS_INFO_TYPE_FPCI + */ +#define NV2080_CTRL_BUS_INFO_INDEX_TYPE (0x00000000) +#define NV2080_CTRL_BUS_INFO_INDEX_INTLINE (0x00000001) +#define NV2080_CTRL_BUS_INFO_INDEX_CAPS (0x00000002) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CAPS (0x00000003) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CAPS (0x00000004) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CAPS (0x00000005) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CAPS (0x00000006) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CTRL_STATUS (0x00000007) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CTRL_STATUS (0x00000008) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CTRL_STATUS (0x00000009) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CTRL_STATUS (0x0000000A) +/** + * This index is used to request coherent dma transfer flags. + * Valid coherent dma transfer flags include: + * NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA + * NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART + */ +#define NV2080_CTRL_BUS_INFO_INDEX_COHERENT_DMA_FLAGS (0x0000000B) +/** + * This index is used to request noncoherent dma transfer flags. + * Valid noncoherent dma transfer flags include: + * NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA + * NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART + * NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE + */ +#define NV2080_CTRL_BUS_INFO_INDEX_NONCOHERENT_DMA_FLAGS (0x0000000C) +/** + * This index is used to request the size of the GPU GART in MBytes. + */ +#define NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE (0x0000000D) +/** + * This index is used to request GPU GART flags. + * Valid gart flags include: + * NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH + * This flag indicates that GPU GART clients need to do an explicit + * flush via an appropriate SetContextDma method. + * NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED + * This flag indicates that the GART address range includes both + * system and video memory. + */ +#define NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_FLAGS (0x0000000E) +#define NV2080_CTRL_BUS_INFO_INDEX_BUS_NUMBER (0x0000000F) +#define NV2080_CTRL_BUS_INFO_INDEX_DEVICE_NUMBER (0x00000010) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_ERRORS (0x00000011) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_ERRORS (0x00000012) +#define NV2080_CTRL_BUS_INFO_INDEX_INTERFACE_TYPE (0x00000013) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_INFO (0x00000014) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_AER (0x00000015) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CAPS (0x00000016) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CTRL_STATUS (0x00000017) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_ASLM_STATUS (0x00000018) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_WIDTH_SWITCH_ERROR_COUNT (0x00000019) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_SPEED_SWITCH_ERROR_COUNT (0x0000001A) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_CYA_ASPM (0x0000001B) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS (0x0000001C) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS (0x0000001D) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED (0x0000001E) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS (0x0000001F) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS_CLEAR (0x00000020) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS_CLEAR (0x00000021) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED_CLEAR (0x00000022) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS_CLEAR (0x00000023) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS (0x00000024) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS (0x00000025) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS (0x00000026) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS (0x00000027) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS_CLEAR (0x00000028) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS_CLEAR (0x00000029) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS_CLEAR (0x0000002A) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS_CLEAR (0x0000002B) +#define NV2080_CTRL_BUS_INFO_INDEX_DOMAIN_NUMBER (0x0000002C) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN_INFO (0x0000002D) +#define NV2080_CTRL_BUS_INFO_INDEX_GPU_INTERFACE_TYPE (0x0000002E) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_GEN_INFO (0x0000002F) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_GEN_INFO (0x00000030) +#define NV2080_CTRL_BUS_INFO_INDEX_MSI_INFO (0x00000031) +/** + * This index is used to request the top 32 bits of the size of the GPU + * GART in MBytes. + */ +#define NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE_HI (0x00000032) +#define NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE (0x00000033) +#define NV2080_CTRL_BUS_INFO_INDEX_MAX NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE +#define NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE (0x00000034) + +/* valid bus info type return values */ +#define NV2080_CTRL_BUS_INFO_TYPE_PCI (0x00000001) +#define NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS (0x00000003) +#define NV2080_CTRL_BUS_INFO_TYPE_FPCI (0x00000004) +#define NV2080_CTRL_BUS_INFO_TYPE_AXI (0x00000008) + +/* valid bus capability flags */ +#define NV2080_CTRL_BUS_INFO_CAPS_NEED_IO_FLUSH (0x00000001) +#define NV2080_CTRL_BUS_INFO_CAPS_CHIP_INTEGRATED (0x00000002) + +/* + * Format of PCIE link caps return values + * Note that Link Capabilities register format is followed only for bits 11:0 + */ +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED 3:0 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_2500MBPS (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_5000MBPS (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_8000MBPS (0x00000003) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_16000MBPS (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_32000MBPS (0x00000005) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_64000MBPS (0x00000006) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_WIDTH 9:4 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM 11:10 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_NONE (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S_L1 (0x00000003) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN 15:12 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN1 (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN2 (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN3 (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN4 (0x00000003) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN5 (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN6 (0x00000005) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL 19:16 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN1 (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN2 (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN3 (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN4 (0x00000003) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN5 (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN6 (0x00000005) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN 23:20 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN1 (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN2 (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN3 (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN4 (0x00000003) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN5 (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN6 (0x00000005) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES 24:24 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_ENABLED (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_DISABLED (0x00000001) + +/* format of PCIE control status return values */ +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM 1:0 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_DISABLED (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L1 (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S_L1 (0x00000003) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED 19:16 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_2500MBPS (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_5000MBPS (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_8000MBPS (0x00000003) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_16000MBPS (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_32000MBPS (0x00000005) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_64000MBPS (0x00000006) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH 25:20 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_UNDEFINED (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X1 (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X2 (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X4 (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X8 (0x00000008) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X12 (0x0000000C) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X16 (0x00000010) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X32 (0x00000020) + +/* coherent dma transfer flags */ +#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA 0:0 +#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_FALSE (0x00000000) +#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_TRUE (0x00000001) +#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART 2:2 +#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_FALSE (0x00000000) +#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_TRUE (0x00000001) + +/* noncoherent dma transfer flags */ +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA 0:0 +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_FALSE (0x00000000) +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_TRUE (0x00000001) +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART 2:2 +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_FALSE (0x00000000) +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_TRUE (0x00000001) +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE 3:3 +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_FALSE (0x00000000) +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_TRUE (0x00000001) + +/* GPU GART flags */ +#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH 0:0 +#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_FALSE (0x00000000) +#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_TRUE (0x00000001) +#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED 1:1 +#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_FALSE (0x00000000) +#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_TRUE (0x00000001) + +/* format of PCIE errors return values */ +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_NON_FATAL_ERROR (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_FATAL_ERROR (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_UNSUPP_REQUEST (0x00000008) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_ENTERED_RECOVERY (0x00000010) + +/* PCIE Gen2 capability and current level */ +#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP 0:0 +#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_FALSE (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_TRUE (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL 1:1 +#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN1 (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN2 (0x00000001) + +/* format of PCIE AER return values */ +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_TRAINING_ERR (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_DLINK_PROTO_ERR (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_POISONED_TLP (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_FC_PROTO_ERR (0x00000008) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_TIMEOUT (0x00000010) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_ABORT (0x00000020) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNEXP_CPL (0x00000040) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_RCVR_OVERFLOW (0x00000080) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_MALFORMED_TLP (0x00000100) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_ECRC_ERROR (0x00000200) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNSUPPORTED_REQ (0x00000400) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RCV_ERR (0x00010000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_TLP (0x00020000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_DLLP (0x00040000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_ROLLOVER (0x00080000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_TIMEOUT (0x00100000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_ADVISORY_NONFATAL (0x00200000) + +/* format of PCIE ASLM status return value */ +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE 0:0 +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_ERROR (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_PRESENT (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED 1:1 +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE 2:2 +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED 3:3 +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04 4:4 +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_MISSING (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_PRESENT (0x00000001) + +/* format of GPU CYA CAPS return value */ +#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID 0:0 +#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM 2:1 +#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_DISABLED (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L1 (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S_L1 (0x00000003) + +/* format of MSI INFO return value */ +#define NV2080_CTRL_BUS_INFO_MSI_STATUS 0:0 +#define NV2080_CTRL_BUS_INFO_MSI_STATUS_DISABLED (0x00000000) +#define NV2080_CTRL_BUS_INFO_MSI_STATUS_ENABLED (0x00000001) + +/*format of L1PM Substates capabilities information */ +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED 0:0 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED 1:1 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED 2:2 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED 3:3 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED 4:4 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_RESERVED 7:5 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PORT_RESTORE_TIME 15:8 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_T_POWER_ON_SCALE 17:16 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_T_POWER_ON_VALUE 23:19 + +/*format of L1 PM Substates Control 1 Register */ +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED 0:0 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED 1:1 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED 2:2 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED 3:3 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_COMMON_MODE_RESTORE_TIME 15:8 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_LTR_L1_2_THRESHOLD_VALUE 25:16 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_LTR_L1_2_THRESHOLD_SCALE 31:29 + +/*format of L1 PM Substates Control 2 Register */ +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL2_T_POWER_ON_SCALE 1:0 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL2_T_POWER_ON_VALUE 7:3 + +/* valid sysmem connection type values */ +#define NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE (0x00000000) +#define NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK (0x00000001) +#define NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C (0x00000002) + +/** + * NV2080_CTRL_CMD_BUS_GET_INFO + * + * This command returns bus engine information for the associated GPU. + * Requests to retrieve bus information use a list of one or more + * NV2080_CTRL_BUS_INFO structures. + * + * busInfoListSize + * This field specifies the number of entries on the caller's + * busInfoList. + * busInfoList + * This field specifies a pointer in the caller's address space + * to the buffer into which the bus information is to be returned. + * This buffer must be at least as big as busInfoListSize multiplied + * by the size of the NV2080_CTRL_BUS_INFO structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV2080_CTRL_CMD_BUS_GET_INFO (0x20801802) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_GET_INFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_BUS_GET_INFO_PARAMS { + NvU32 busInfoListSize; + NV_DECLARE_ALIGNED(NvP64 busInfoList, 8); +} NV2080_CTRL_BUS_GET_INFO_PARAMS; + +#define NV2080_CTRL_CMD_BUS_GET_INFO_V2 (0x20801823) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_MESSAGE_ID (0x23U) + +typedef struct NV2080_CTRL_BUS_GET_INFO_V2_PARAMS { + NvU32 busInfoListSize; + NV2080_CTRL_BUS_INFO busInfoList[NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE]; +} NV2080_CTRL_BUS_GET_INFO_V2_PARAMS; + +/* + * NV2080_CTRL_BUS_PCI_BAR_INFO + * + * This structure describes PCI bus BAR information. + * + * flags + * This field contains any flags for the associated BAR. + * barSize + * This field contains the size in megabytes of the associated BAR. + * DEPRECATED, please use barSizeBytes. + * barSizeBytes + * This field contains the size in bytes of the associated BAR. + * barOffset + * This field contains the PCI bus offset in bytes of the associated BAR. + */ +typedef struct NV2080_CTRL_BUS_PCI_BAR_INFO { + NvU32 flags; + NvU32 barSize; + NV_DECLARE_ALIGNED(NvU64 barSizeBytes, 8); + NV_DECLARE_ALIGNED(NvU64 barOffset, 8); +} NV2080_CTRL_BUS_PCI_BAR_INFO; + +/* + * NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO + * + * This command returns PCI bus BAR information. + * + * barCount + * This field returns the number of BARs for the associated subdevice. + * Legal values for this parameter will be between one to + * NV2080_CTRL_BUS_MAX_BARS. + * barInfo + * This field returns per-BAR information in the form of an array of + * NV2080_CTRL_BUS_PCI_BAR_INFO structures. Information for as many as + * NV2080_CTRL_BUS_MAX_PCI_BARS will be returned. Any unused entries will + * be initialized to zero. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO (0x20801803) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS_MESSAGE_ID" */ + +/* maximum number of BARs per subdevice */ +#define NV2080_CTRL_BUS_MAX_PCI_BARS (8) + +#define NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS { + NvU32 pciBarCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_BUS_PCI_BAR_INFO pciBarInfo[NV2080_CTRL_BUS_MAX_PCI_BARS], 8); +} NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_SET_PCIE_LINK_WIDTH + * + * This command sets PCI-E link width to the specified new value. + * + * pcieLinkWidth + * This field specifies the new PCI-E link width. + * + * failingReason + * This field specifies the reason why the change of link width fails. + * It is valid only when this routine returns NV_ERR_GENERIC. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_GENERIC + */ +#define NV2080_CTRL_CMD_BUS_SET_PCIE_LINK_WIDTH (0x20801804) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS { + NvU32 pcieLinkWidth; + NvU32 failingReason; +} NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS; + +#define NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PSTATE (0x00000001) +#define NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PCIE_CFG_ACCESS (0x00000002) +#define NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_TRAINING (0x00000004) + +/* + * NV2080_CTRL_CMD_BUS_SET_PCIE_SPEED + * + * This command Initiates a change in PCIE Bus Speed + * + * busSpeed + * This field is the target speed to train to. + * Legal values for this parameter are: + * NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS + * NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS + * NV2080_CTRL_BUS_SET_PCIE_SPEED_8000MBPS + * NV2080_CTRL_BUS_SET_PCIE_SPEED_16000MBPS + * NV2080_CTRL_BUS_SET_PCIE_SPEED_32000MBPS + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_BUS_SET_PCIE_SPEED (0x20801805) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS { + NvU32 busSpeed; +} NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS; + +#define NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS (0x00000001) +#define NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS (0x00000002) +#define NV2080_CTRL_BUS_SET_PCIE_SPEED_8000MBPS (0x00000003) +#define NV2080_CTRL_BUS_SET_PCIE_SPEED_16000MBPS (0x00000004) +#define NV2080_CTRL_BUS_SET_PCIE_SPEED_32000MBPS (0x00000005) +#define NV2080_CTRL_BUS_SET_PCIE_SPEED_64000MBPS (0x00000006) + +/* + * NV2080_CTRL_CMD_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED + * + * This command Initiates a change in PCIE Bus Speed for a HWBC device's upstream + * link. + * + * busSpeed + * This field specifies the target speed to which to train. + * Legal values for this parameter are: + * NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS + * NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS + * primaryBus + * This field is the PCI Express Primary Bus number that uniquely identifies + * a HWBC device's upstream port, i.e. the BR04 Upstream Port. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED (0x20801806) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS { + NvU32 busSpeed; + NvU8 primaryBus; +} NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS; + +#define NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_2500MBPS (0x00000001) +#define NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_5000MBPS (0x00000002) + +/* + * NV2080_CTRL_CMD_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED + * + * This command gets the current PCIE Bus Speed for a HWBC device's upstream + * link. + * + * primaryBus + * This field is the PCI Express Primary Bus number that uniquely identifies + * a HWBC device's upstream port, i.e. the BR04 Upstream Port. + * busSpeed + * This field specifies a pointer in the caller's address space + * to the NvU32 variable into which the bus speed is to be returned. + * On success, this parameter will contain one of the following values: + * NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS + * NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED (0x20801807) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS { + NvU32 busSpeed; + NvU8 primaryBus; +} NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS; + +#define NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_2500MBPS (0x00000001) +#define NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_5000MBPS (0x00000002) + +/* + * NV2080_CTRL_CMD_BUS_MAP_BAR2 + * + * This command sets up BAR2 page tables for passed-in memory handle. + * This command MUST be executed before NV2080_CTRL_CMD_BUS_UNMAP_BAR2 + * or NV2080_CTRL_CMD_BUS_VERIFY_BAR2. Not supported on SLI. + * + * hMemory + * This field is a handle to physical memory. + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV2080_CTRL_CMD_BUS_MAP_BAR2 (0x20801809) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_MAP_BAR2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_MAP_BAR2_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_BUS_MAP_BAR2_PARAMS { + NvHandle hMemory; +} NV2080_CTRL_BUS_MAP_BAR2_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_UNMAP_BAR2 + * + * This command unmaps any pending BAR2 page tables created with + * NV2080_CTRL_CMD_BUS_MAP_BAR2 command. The handle passed in must + * match the handle used to map the page tables. Not supported on SLI. + * + * hMemory + * This field is a handle to physical memory. + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV2080_CTRL_CMD_BUS_UNMAP_BAR2 (0x2080180a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS { + NvHandle hMemory; +} NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_VERIFY_BAR2 + * + * This command tests BAR2 against BAR0 if there are BAR2 page tables + * set up with NV2080_CTRL_CMD_BUS_MAP_BAR2 command. The handle passed + * in must match the handle used to map the page tables. Not supported on SLI. + * + * hMemory + * This field is a handle to physical memory. + * offset + * Base offset of the surface where the test will make its first dword write. + * size + * Test will write '(size/4)*4' bytes starting at surface offset `offset'. + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV2080_CTRL_CMD_BUS_VERIFY_BAR2 (0x2080180b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS { + NvHandle hMemory; + NvU32 offset; + NvU32 size; +} NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_HWBC_GET_UPSTREAM_BAR0 + * + * This command gets the BAR0 for a HWBC device's upstream port. + * + * primaryBus + * This field is the PCI Express Primary Bus number that uniquely identifies + * a HWBC device's upstream port, i.e. the BR04 Upstream Port. + * physBAR0 + * This field returns the BAR0 physical address of the HWBC device's + * upstream port. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_BUS_HWBC_GET_UPSTREAM_BAR0 (0x2080180e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_HWBC_GET_UPSTREAM_BAR0_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_HWBC_GET_UPSTREAM_BAR0_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV2080_CTRL_BUS_HWBC_GET_UPSTREAM_BAR0_PARAMS { + NV_DECLARE_ALIGNED(NvU64 physBAR0, 8); + NvU8 primaryBus; +} NV2080_CTRL_BUS_HWBC_GET_UPSTREAM_BAR0_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_SERVICE_GPU_MULTIFUNC_STATE + * This command would reports the current Audio device power state or Sets new power state. + * + * command + * This parametrer specifies the target GPU multifunction state. + * NV2080_CTRL_BUS_ENABLE_GPU_MULTIFUNC_STATE Enables the multi function state + * NV2080_CTRL_BUS_DISABLE_GPU_MULTIFUNC_STATE Disables the multi function state. + * NV2080_CTRL_BUS_GET_GPU_MULTIFUNC_STATE Get the Current device power state. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + */ + +#define NV2080_CTRL_CMD_BUS_SERVICE_GPU_MULTIFUNC_STATE (0x20801812) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS { + NvU8 command; + NvU32 deviceState; +} NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS; + +#define NV2080_CTRL_BUS_ENABLE_GPU_MULTIFUNC_STATE (0x00000000) +#define NV2080_CTRL_BUS_DISABLE_GPU_MULTIFUNC_STATE (0x00000001) +#define NV2080_CTRL_BUS_GET_GPU_MULTIFUNC_STATE (0x00000002) + +/* + * NV2080_CTRL_CMD_BUS_GET_PEX_COUNTERS + * This command gets the counts for different counter types. + * + * pexCounterMask + * This parameter specifies the input mask for desired counter types. + * + * pexTotalCorrectableErrors + * This parameter gives the total correctable errors which includes + * NV_XVE_ERROR_COUNTER1 plus LCRC Errors, 8B10B Errors, NAKS and Failed L0s + * + * pexCorrectableErrors + * This parameter only includes NV_XVE_ERROR_COUNTER1 value. + * + * pexTotalNonFatalErrors + * This parameter returns total Non-Fatal Errors which may or may not + * include Correctable Errors. + * + * pexTotalFatalErrors + * This parameter returns Total Fatal Errors + * + * pexTotalUnsupportedReqs + * This parameter returns Total Unsupported Requests + * + * pexErrors + * This array contains the error counts for each error type as requested from + * the pexCounterMask. The array indexes correspond to the mask bits one-to-one. + */ + +#define NV2080_CTRL_CMD_BUS_GET_PEX_COUNTERS (0x20801813) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PEX_MAX_COUNTER_TYPES 31 +#define NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS { + NvU32 pexCounterMask; + NvU32 pexTotalCorrectableErrors; + NvU16 pexCorrectableErrors; + NvU8 pexTotalNonFatalErrors; + NvU8 pexTotalFatalErrors; + NvU8 pexTotalUnsupportedReqs; + NvU16 pexCounters[NV2080_CTRL_PEX_MAX_COUNTER_TYPES]; +} NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS; + +/* + * Note that MAX_COUNTER_TYPES will need to be updated each time + * a new counter type gets added to the list below. The value + * depends on the bits set for the last valid define. Look + * at pexCounters[] comments above for details. + * + */ +#define NV2080_CTRL_BUS_PEX_COUNTER_TYPE 0x00000000 +#define NV2080_CTRL_BUS_PEX_COUNTER_RECEIVER_ERRORS 0x00000001 +#define NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_COUNT 0x00000002 +#define NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_ROLLOVER_COUNT 0x00000004 +#define NV2080_CTRL_BUS_PEX_COUNTER_BAD_DLLP_COUNT 0x00000008 +#define NV2080_CTRL_BUS_PEX_COUNTER_BAD_TLP_COUNT 0x00000010 +#define NV2080_CTRL_BUS_PEX_COUNTER_8B10B_ERRORS_COUNT 0x00000020 +#define NV2080_CTRL_BUS_PEX_COUNTER_SYNC_HEADER_ERRORS_COUNT 0x00000040 +#define NV2080_CTRL_BUS_PEX_COUNTER_LCRC_ERRORS_COUNT 0x00000080 +#define NV2080_CTRL_BUS_PEX_COUNTER_FAILED_L0S_EXITS_COUNT 0x00000100 +#define NV2080_CTRL_BUS_PEX_COUNTER_NAKS_SENT_COUNT 0x00000200 +#define NV2080_CTRL_BUS_PEX_COUNTER_NAKS_RCVD_COUNT 0x00000400 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_ERRORS 0x00000800 +#define NV2080_CTRL_BUS_PEX_COUNTER_L1_TO_RECOVERY_COUNT 0x00001000 +#define NV2080_CTRL_BUS_PEX_COUNTER_L0_TO_RECOVERY_COUNT 0x00002000 +#define NV2080_CTRL_BUS_PEX_COUNTER_RECOVERY_COUNT 0x00004000 +#define NV2080_CTRL_BUS_PEX_COUNTER_CHIPSET_XMIT_L0S_ENTRY_COUNT 0x00008000 +#define NV2080_CTRL_BUS_PEX_COUNTER_GPU_XMIT_L0S_ENTRY_COUNT 0x00010000 +#define NV2080_CTRL_BUS_PEX_COUNTER_L1_ENTRY_COUNT 0x00020000 +#define NV2080_CTRL_BUS_PEX_COUNTER_L1P_ENTRY_COUNT 0x00040000 +#define NV2080_CTRL_BUS_PEX_COUNTER_DEEP_L1_ENTRY_COUNT 0x00080000 +#define NV2080_CTRL_BUS_PEX_COUNTER_ASLM_COUNT 0x00100000 +#define NV2080_CTRL_BUS_PEX_COUNTER_TOTAL_CORR_ERROR_COUNT 0x00200000 +#define NV2080_CTRL_BUS_PEX_COUNTER_CORR_ERROR_COUNT 0x00400000 +#define NV2080_CTRL_BUS_PEX_COUNTER_NON_FATAL_ERROR_COUNT 0x00800000 +#define NV2080_CTRL_BUS_PEX_COUNTER_FATAL_ERROR_COUNT 0x01000000 +#define NV2080_CTRL_BUS_PEX_COUNTER_UNSUPP_REQ_COUNT 0x02000000 +#define NV2080_CTRL_BUS_PEX_COUNTER_L1_1_ENTRY_COUNT 0x04000000 +#define NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ENTRY_COUNT 0x08000000 +#define NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ABORT_COUNT 0x10000000 +#define NV2080_CTRL_BUS_PEX_COUNTER_L1SS_TO_DEEP_L1_TIMEOUT_COUNT 0x20000000 +#define NV2080_CTRL_BUS_PEX_COUNTER_L1_SHORT_DURATION_COUNT 0x40000000 + +/* + * NV2080_CTRL_CMD_BUS_CLEAR_PEX_COUNTER_COUNTERS + * This command gets the counts for different counter types. + * + * pexCounterMask + * This parameter specifies the input mask for desired counters to be + * cleared. Note that all counters cannot be cleared. + */ + +#define NV2080_CTRL_CMD_BUS_CLEAR_PEX_COUNTERS (0x20801814) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS { + NvU32 pexCounterMask; +} NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_FREEZE_PEX_COUNTERS + * This command gets the counts for different counter types. + * + * pexCounterMask + * This parameter specifies the input mask for desired counters to be + * freezed. Note that all counters cannot be frozen. + * + * bFreezeRmCounter + * This parameter decides whether API will freeze it or unfreeze it. + * NV_TRUE for freeze and NV_FALSE for unfreeze. + */ + +#define NV2080_CTRL_CMD_BUS_FREEZE_PEX_COUNTERS (0x20801815) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS { + NvU32 pexCounterMask; + NvBool bFreezeRmCounter; +} NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS + * This command gets the per Lane Counters and the type of errors. + * + * pexLaneErrorStatus + * This mask specifies the type of error detected on any of the Lanes. + * + * pexLaneCounter + * This array gives the counters per Lane. Each index corresponds to Lane + * index + 1 + */ + +#define NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS (0x20801816) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PEX_MAX_LANES 16 +#define NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS { + NvU16 pexLaneErrorStatus; + NvU8 pexLaneCounter[NV2080_CTRL_PEX_MAX_LANES]; +} NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS; + +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_TYPE 0x00000000 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_CODING_ERR 0x00000001 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_ORDER_ERR 0x00000002 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_OS_DATA_SEQ_ERR 0x00000004 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_TSX_DATA_SEQ_ERR 0x00000008 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_SKPOS_LFSR_ERR 0x00000010 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_RX_CLK_FIFO_OVERFLOW 0x00000020 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_ELASTIC_FIFO_OVERFLOW 0x00000040 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LINK_NUM_ERR 0x00000080 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LANE_NUM_ERR 0x00000100 + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY (0x20801817) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID (0x17U) + +typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS { + NvBool bPexLtrRegkeyOverride; + NvBool bPexRootPortLtrSupported; + NvBool bPexGpuLtrSupported; + NvU16 pexLtrSnoopLatencyValue; + NvU8 pexLtrSnoopLatencyScale; + NvU16 pexLtrNoSnoopLatencyValue; + NvU8 pexLtrNoSnoopLatencyScale; +} NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS; + +#define NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY (0x20801818) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS { + NvU16 pexLtrSnoopLatencyValue; + NvU8 pexLtrSnoopLatencyScale; + NvU16 pexLtrNoSnoopLatencyValue; + NvU8 pexLtrNoSnoopLatencyScale; +} NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_GET_PEX_UTIL_COUNTERS + * This command gets the counts for different counter types. + * + * pexCounterMask + * This parameter specifies the input mask for desired counter types. + * + */ +#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_BYTES 0x00000001 +#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_BYTES 0x00000002 +#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0 0x00000004 +#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0 0x00000008 +#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0S 0x00000010 +#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0S 0x00000020 +#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_NON_L0_L0S 0x00000040 +#define NV2080_CTRL_PEX_UTIL_MAX_COUNTER_TYPES 7 + +#define NV2080_CTRL_CMD_BUS_GET_PEX_UTIL_COUNTERS (0x20801819) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS { + NvU32 pexCounterMask; + NvU32 pexCounters[NV2080_CTRL_PEX_UTIL_MAX_COUNTER_TYPES]; +} NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_CLEAR_PEX_UTIL_COUNTER_COUNTERS + * This command gets the counts for different counter types. + * + * pexCounterMask + * This parameter specifies the input mask for desired counters to be + * cleared. Note that all counters cannot be cleared. + * + * NOTE: EX_UTIL_COUNTER_UPSTREAM & NV2080_CTRL_BUS_PEX_UTIL_COUNTER_DOWNSTREAM + * belongs to PMU. The ctrl function will not reset nor disable/enable them. + */ +#define NV2080_CTRL_CMD_BUS_CLEAR_PEX_UTIL_COUNTERS (0x20801820) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS { + NvU32 pexCounterMask; +} NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS; + +#define NV2080_CTRL_CMD_BUS_GET_BFD (0x20801821) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_BFD_PARAMSARR_MESSAGE_ID" */ + +typedef struct NV2080_CTRL_BUS_GET_BFD_PARAMS { + NvBool valid; + NvU16 deviceID; + NvU16 vendorID; + NvU32 domain; + NvU16 bus; + NvU16 device; + NvU8 function; +} NV2080_CTRL_BUS_GET_BFD_PARAMS; + +#define NV2080_CTRL_BUS_GET_BFD_PARAMSARR_MESSAGE_ID (0x21U) + +typedef struct NV2080_CTRL_BUS_GET_BFD_PARAMSARR { + NV2080_CTRL_BUS_GET_BFD_PARAMS params[32]; +} NV2080_CTRL_BUS_GET_BFD_PARAMSARR; + +/* + * NV2080_CTRL_CMD_BUS_GET_ASPM_DISABLE_FLAGS + * This command gets the following mentioned PDB Properties + * + * aspmDisableFlags[] + * NvBool array stores each of the properties' state. the array size can + * be increased as per requirement. + * + * NOTE: When adding more properties, increment NV2080_CTRL_ASPM_DISABLE_FLAGS_MAX_FLAGS. + */ + +#define NV2080_CTRL_ASPM_DISABLE_FLAGS_L1_MASK_REGKEY_OVERRIDE 0x00000000 +#define NV2080_CTRL_ASPM_DISABLE_FLAGS_OS_RM_MAKES_POLICY_DECISIONS 0x00000001 +#define NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_BEHIND_BRIDGE 0x00000002 +#define NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_UNSUPPORTED 0x00000003 +#define NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED 0x00000004 +#define NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_POR_MOBILE_ONLY 0x00000005 +#define NV2080_CTRL_ASPM_DISABLE_FLAGS_CL_ASPM_L1_CHIPSET_DISABLED 0x00000006 +#define NV2080_CTRL_ASPM_DISABLE_FLAGS_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY 0x00000007 +#define NV2080_CTRL_ASPM_DISABLE_FLAGS_BIF_ENABLE_ASPM_DT_L1 0x00000008 +//append properties here + +#define NV2080_CTRL_ASPM_DISABLE_FLAGS_MAX_FLAGS 9 + +#define NV2080_CTRL_CMD_BUS_GET_ASPM_DISABLE_FLAGS (0x20801822) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS { + NvBool aspmDisableFlags[NV2080_CTRL_ASPM_DISABLE_FLAGS_MAX_FLAGS]; +} NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS; + +#define NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS (0x20801824) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS_MESSAGE_ID (0x24U) + +typedef struct NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS { + NvBool bEnable; +} NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_GET_NVLINK_PEER_ID_MASK + * + * This command returns cached(SW only) NVLINK peer id mask. Currently, this control + * call is only needed inside a SR-IOV enabled guest where page table management is + * being done by the guest. Guest needs this mask to derive the peer id corresponding + * to the peer GPU. This peer id will then be programmed inside the PTEs by guest RM. + * + * nvlinkPeerIdMask[OUT] + * - The peer id mask is returned in this array. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_BUS_GET_NVLINK_PEER_ID_MASK (0x20801825) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_MAX_NUM_GPUS 32 + +#define NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_MESSAGE_ID (0x25U) + +typedef struct NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS { + NvU32 nvlinkPeerIdMask[NV2080_CTRL_BUS_MAX_NUM_GPUS]; +} NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS + * This command takes parameters eomMode, eomNblks and eomNerrs from the client + * and then sends it out to PMU. + */ +#define NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS (0x20801826) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS_MESSAGE_ID (0x26U) + +typedef struct NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS { + NvU8 eomMode; + NvU8 eomNblks; + NvU8 eomNerrs; +} NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE + * This command takes parameters UPHY register's address and lane from the client + * and then sends it out to PMU. + */ +#define NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE (0x20801827) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS_MESSAGE_ID (0x27U) + +typedef struct NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS { + NvU32 regAddress; + NvU32 laneSelectMask; + NvU16 regValue; +} NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_GET_EOM_STATUS + * + */ +#define NV2080_CTRL_CMD_BUS_GET_EOM_STATUS (0x20801828) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_MAX_NUM_LANES 32 + +#define NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS_MESSAGE_ID (0x28U) + +typedef struct NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS { + NvU8 eomMode; + NvU8 eomNblks; + NvU8 eomNerrs; + NvU8 eomBerEyeSel; + NvU8 eomPamEyeSel; + NvU32 laneMask; + NvU16 eomStatus[NV2080_CTRL_BUS_MAX_NUM_LANES]; +} NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS + * + * This command returns the PCIe requester atomics operation capabilities + * from GPU to coherent SYSMEM. + * + * atomicsCaps[OUT] + * Mask of supported PCIe atomic operations in the form of + * NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_* + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS (0x20801829) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID (0x29U) + +typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS { + NvU32 atomicsCaps; +} NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS; + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32 0:0 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64 1:1 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32 2:2 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64 3:3 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32 4:4 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64 5:5 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128 6:6 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_NO (0x00000000) + +/* + * NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS + * + * This command returns the supported GPU atomic operations + * that map to the capable PCIe atomic operations from GPU to + * coherent SYSMEM. + * + * atomicOp[OUT] + * Array of structure that contains the atomic operation + * supported status and its attributes. The array can be + * indexed using one of NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_* + * + * bSupported[OUT] + * Is the GPU atomic operation natively supported by the PCIe? + * + * attributes[OUT] + * Provides the attributes mask of the GPU atomic operation when supported + * in the form of + * NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_* + * + */ +#define NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS (0x2080182a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IADD 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMIN 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMAX 2 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_INC 3 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_DEC 4 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IAND 5 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IOR 6 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IXOR 7 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_EXCH 8 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_CAS 9 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FADD 10 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMIN 11 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMAX 12 + +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT 13 + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID (0x2AU) + +typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS { + struct { + NvBool bSupported; + NvU32 attributes; + } atomicOp[NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT]; +} NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS; + +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR 0:0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR 1:1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION 2:2 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32 3:3 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64 4:4 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128 5:5 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED 6:6 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED 7:7 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_NO 0 + +/* + * NV2080_CTRL_CMD_BUS_GET_C2C_INFO + * + * This command returns the C2C links information. + * + * bIsLinkUp[OUT] + * NV_TRUE if the C2C links are present and the links are up. + * The below remaining fields are valid only if return value is + * NV_OK and bIsLinkUp is NV_TRUE. + * nrLinks[OUT] + * Total number of C2C links that are up. + * linkMask[OUT] + * Bitmask of the C2C links present and up. + * perLinkBwMBps[OUT] + * Theoretical per link bandwidth in MBps. + * remoteType[OUT] + * Type of the device connected to the remote end of the C2C link. + * Valid values are : + * NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU - connected to a CPU + * NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU - connected to another GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * + * Please also review the information below for additional information on + * select fields: + * + * remoteType[OUT] + * NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU - connected to a CPU + */ + + + +#define NV2080_CTRL_CMD_BUS_GET_C2C_INFO (0x2080182b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID (0x2BU) + +typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS { + NvBool bIsLinkUp; + NvU32 nrLinks; + NvU32 linkMask; + NvU32 perLinkBwMBps; + NvU32 remoteType; +} NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS; + +#define NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU 1 +#define NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU 2 + +/* + * NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS + * + * This command disables the GPU system memory access after quiescing the GPU, + * or re-enables sysmem access. + * + * bDisable + * If NV_TRUE the GPU is quiesced and system memory access is disabled . + * If NV_FALSE the GPU system memory access is re-enabled and the GPU is resumed. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS (0x2080182c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS_MESSAGE_ID (0x2CU) + +typedef struct NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS { + NvBool bDisable; +} NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO + * + * This command returns the C2C error info for a C2C links. + * + * errCnts[OUT] + * Array of structure that contains the error counts for + * number of times one of C2C fatal error interrupt has happened. + * The array size should be NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES + * * NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE. + * + * nrCrcErrIntr[OUT] + * Number of times CRC error interrupt triggered. + * nrReplayErrIntr[OUT] + * Number of times REPLAY error interrupt triggered. + * nrReplayB2bErrIntr[OUT] + * Number of times REPLAY_B2B error interrupt triggered. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO (0x2080182d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES 2 +#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE 5 + +#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID (0x2DU) + +typedef struct NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS { + struct { + NvU32 nrCrcErrIntr; + NvU32 nrReplayErrIntr; + NvU32 nrReplayB2bErrIntr; + } errCnts[NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES * NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE]; +} NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS; + + +/* + * NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING + * + * This command sets P2P mapping. + * + * connectionType[IN] + * Connection type, one of NV2080_CTRL_CMD_BUS_SET_P2P_MAPPINGS_CONNECTION + * peerId[IN] + * peerId of remote GPU from local GPU on which call is made. + * bSpaAccessOnly[IN] + * SPA access only. SPA addressing mode is supported when we support ATS. + * bUseUuid [in] + * Option only available for Guest RPCs and is not avaliable for external clients. + * Set to NV_TRUE to use remoteGpuUuid in lieu of remoteGpuId to identify target GPU. + * remoteGpuId[IN] + * GPU ID of remote GPU. + * remoteGpuUuid [in] + * Alternative to gpuId; used to identify target GPU for which caps are being queried. + * Option only available for Guest RPCs. + * If bUseUuid == NV_TRUE, gpuUuid is used in lieu of gpuId to identify target GPU. + * If bUseUuid == NV_FALSE, gpuUuid is ignored and gpuId is used by default. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING (0x2080182e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_INVALID 0 +#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_NVLINK 1 +#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE 2 +#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE_BAR1 3 +#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_C2C 4 + +#define NV2080_SET_P2P_MAPPING_UUID_LEN 16U + +#define NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_MESSAGE_ID (0x2EU) + +typedef struct NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS { + NvU32 connectionType; + NvU32 peerId; + NvBool bSpaAccessOnly; + NvBool bUseUuid; + NvU32 remoteGpuId; + NvU8 remoteGpuUuid[NV2080_SET_P2P_MAPPING_UUID_LEN]; +} NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING + * + * This command unsets P2P mapping. + * + * connectionType[IN] + * Connection type, one of NV2080_CTRL_CMD_BUS_SET_P2P_MAPPINGS_CONNECTION + * peerId[IN] + * peerId of remote GPU from local GPU on which call is mad. + * bUseUuid [in] + * Option only available for Guest RPCs and is not avaliable for external clients. + * Set to NV_TRUE to use remoteGpuUuid in lieu of remoteGpuId to identify target GPU. + * remoteGpuId[IN] + * GPU ID of remote GPU. + * remoteGpuUuid [in] + * Alternative to gpuId; used to identify target GPU for which caps are being queried. + * Option only available for Guest RPCs. + * If bUseUuid == NV_TRUE, gpuUuid is used in lieu of gpuId to identify target GPU. + * If bUseUuid == NV_FALSE, gpuUuid is ignored and gpuId is used by default. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING (0x2080182f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_MESSAGE_ID (0x2FU) + +typedef struct NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS { + NvU32 connectionType; + NvU32 peerId; + NvBool bUseUuid; + NvU32 remoteGpuId; + NvU8 remoteGpuUuid[NV2080_SET_P2P_MAPPING_UUID_LEN]; +} NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS; + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h new file mode 100644 index 0000000..d2f5424 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h @@ -0,0 +1,329 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080ce.finn +// + + + +#include "nvcfg_sdk.h" + + +/* NV20_SUBDEVICE_XX ce control commands and parameters */ + +/* + * NV2080_CTRL_CMD_CE_GET_CAPS + * + * This command returns the set of CE capabilities for the device + * in the form of an array of unsigned bytes. + * + * ceEngineType + * This parameter specifies the copy engine type + * capsTblSize + * This parameter specifies the size in bytes of the caps table per CE. + * This value should be set to NV2080_CTRL_CE_CAPS_TBL_SIZE. + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the CE caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_CE_GET_CAPS (0x20802a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CAPS_PARAMS_MESSAGE_ID" */ + +/* + * Size in bytes of CE caps table. This value should be one greater + * than the largest byte_index value below. + */ +#define NV2080_CTRL_CE_CAPS_TBL_SIZE 2 + +#define NV2080_CTRL_CE_GET_CAPS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_CE_GET_CAPS_PARAMS { + NvU32 ceEngineType; + NvU32 capsTblSize; + NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); +} NV2080_CTRL_CE_GET_CAPS_PARAMS; + +#define NV2080_CTRL_CMD_CE_GET_CAPS_V2 (0x20802a03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS { + NvU32 ceEngineType; + NvU8 capsTbl[NV2080_CTRL_CE_CAPS_TBL_SIZE]; +} NV2080_CTRL_CE_GET_CAPS_V2_PARAMS; + +/* extract cap bit setting from tbl */ +#define NV2080_CTRL_CE_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* caps format is byte_index:bit_mask */ +#define NV2080_CTRL_CE_CAPS_CE_GRCE 0:0x01 +#define NV2080_CTRL_CE_CAPS_CE_SHARED 0:0x02 +#define NV2080_CTRL_CE_CAPS_CE_SYSMEM_READ 0:0x04 +#define NV2080_CTRL_CE_CAPS_CE_SYSMEM_WRITE 0:0x08 +#define NV2080_CTRL_CE_CAPS_CE_NVLINK_P2P 0:0x10 +#define NV2080_CTRL_CE_CAPS_CE_SYSMEM 0:0x20 +#define NV2080_CTRL_CE_CAPS_CE_P2P 0:0x40 +#define NV2080_CTRL_CE_CAPS_CE_BL_SIZE_GT_64K_SUPPORTED 0:0x80 +#define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_NONPIPELINED_BL 1:0x01 +#define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL 1:0x02 + + + +/* + * NV2080_CTRL_CE_CAPS_CE_GRCE + * Set if the CE is synchronous with GR + * + * NV2080_CTRL_CE_CAPS_CE_SHARED + * Set if the CE shares physical CEs with any other CE + * + * NV2080_CTRL_CE_CAPS_CE_SYSMEM_READ + * Set if the CE can give enhanced performance for SYSMEM reads over other CEs + * + * NV2080_CTRL_CE_CAPS_CE_SYSMEM_WRITE + * Set if the CE can give enhanced performance for SYSMEM writes over other CEs + * + * NV2080_CTRL_CE_CAPS_CE_NVLINK_P2P + * Set if the CE can be used for P2P transactions using NVLINK + * Once a CE is exposed for P2P over NVLINK, it will remain available for the life of RM + * PCE2LCE mapping may change based on the number of GPUs registered in RM however + * + * NV2080_CTRL_CE_CAPS_CE_SYSMEM + * Set if the CE can be used for SYSMEM transactions + * + * NV2080_CTRL_CE_CAPS_CE_P2P + * Set if the CE can be used for P2P transactions + * + * NV2080_CTRL_CE_CAPS_CE_BL_SIZE_GT_64K_SUPPORTED + * Set if the CE supports BL copy size greater than 64K + * + * NV2080_CTRL_CE_CAPS_CE_SUPPORTS_NONPIPELINED_BL + * Set if the CE supports non-pipelined Block linear + * + * NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL + * Set if the CE supports pipelined Block Linear + */ + + + +/* + * NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK + * + * This command returns the mapping of PCE's for the given LCE. + * + * ceEngineType + * This parameter specifies the copy engine type + * pceMask + * This parameter specifies a mask of PCEs that correspond + * to the LCE specified in ceEngineType + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + + + +#define NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK (0x20802a02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS { + NvU32 ceEngineType; + NvU32 pceMask; +} NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS; + +/* + * NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG + * + * This command sets the PCE2LCE configuration + * + * pceLceConfig[NV2080_CTRL_MAX_PCES] + * This parameter specifies the PCE-LCE mapping requested + * grceLceConfig[NV2080_CTRL_MAX_GRCES] + * This parameter specifies which LCE is the GRCE sharing with + * 0xF -> Does not share with any LCE + * 0-MAX_LCE -> Shares with the given LCE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG (0x20802a04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MAX_PCES 32 +#define NV2080_CTRL_MAX_GRCES 2 + +#define NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS { + NvU32 ceEngineType; + NvU32 pceLceMap[NV2080_CTRL_MAX_PCES]; + NvU32 grceSharedLceMap[NV2080_CTRL_MAX_GRCES]; +} NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS; + +/* + * NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS + * + * This command updates the PCE-LCE mappings + * + * pceLceMap [IN] + * This parameter contains the array of PCE to LCE mappings. + * The array is indexed by the PCE index, and contains the + * LCE index that the PCE is assigned to. A unused PCE is + * tagged with NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE. + * + * grceConfig [IN] + * This parameter contains the array of GRCE configs. + * 0xF -> GRCE does not share with any LCE + * 0-MAX_LCE -> GRCE shares with the given LCE + * + * exposeCeMask [IN] + * This parameter specifies the mask of LCEs to export to the + * clients after the update. + * + * bUpdateNvlinkPceLce [IN] + * Whether PCE-LCE mappings need to be updated for nvlink topology. + * If this is NV_FALSE, RM would ignore the above values. However, + * PCE-LCE mappings will still be updated if there were any regkey + * overrides. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ + +#define NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS (0x20802a05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS { + NvU32 pceLceMap[NV2080_CTRL_MAX_PCES]; + NvU32 grceConfig[NV2080_CTRL_MAX_GRCES]; + NvU32 exposeCeMask; + NvBool bUpdateNvlinkPceLce; +} NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS; + +#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE 0xf + +/* + * NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB + * + * This function triggers an update of the exported CE classes. CEs with + * no physical resources will not be exported. A record of these + * will be return in in the stubbedCeMask. + * + * An example if NV2080_ENGINE_TYPE_COPY4 is stubbed (1<<4) will be + * set in stubbedCeMask. + */ + + +#define NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB (0x20802a06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS { + NvU32 stubbedCeMask; +} NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS; + +/* + * NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS + * + * Query _CE_GRCE, _CE_SHARED, _CE_SUPPORTS_PIPELINED_BL, _CE_SUPPORTS_NONPIPELINED_BL bits of CE + * capabilities. + * + */ + +#define NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS (0x20802a07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | 0x7" */ + +#define NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS { + NvU32 size; +} NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS; + +#define NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE (0x20802a08) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASKS + * + * Get HSHUB and FBHUB PCE masks. + * + * [out] hshubPceMasks + * PCE mask for each HSHUB + * [out] fbhubPceMask + * FBHUB PCE mask + */ + +#define NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK (0x20802a09) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_MAX_HSHUBS 5 + +#define NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS { + NvU32 hshubPceMasks[NV2080_CTRL_CE_MAX_HSHUBS]; + NvU32 fbhubPceMask; +} NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS; + +/* + * NV2080_CTRL_CMD_CE_GET_ALL_CAPS + * + * Query caps of all CEs. + * + * [out] capsTbl + * Array of CE caps in the order of CEs. The caps bits interpretation is the same as in + * NV2080_CTRL_CMD_CE_GET_CAPS. + * [out] present + * Bit mask indicating which CEs are usable by the client and have their caps indicated in capsTbl. + * If a CE is not marked present, its caps bits should be ignored. + * If client is subscribed to a MIG instance, only the CEs present in the instance are tagged as such. + */ + +#define NV2080_CTRL_CMD_CE_GET_ALL_CAPS (0x20802a0a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID (0xaU) + +typedef struct NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS { + NvU8 capsTbl[NV2080_CTRL_MAX_PCES][NV2080_CTRL_CE_CAPS_TBL_SIZE]; + NvU32 present; +} NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS; + +#define NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS (0x20802a0b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | 0xb" */ + +/* _ctrl2080ce_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080cipher.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080cipher.h new file mode 100644 index 0000000..55b9964 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080cipher.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080cipher.finn +// + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h new file mode 100644 index 0000000..20b8f4f --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080clk.finn +// + + + +/* _ctrl2080clk_h_ */ +#include "nvfixedtypes.h" +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "ctrl/ctrl2080/ctrl2080boardobj.h" +#include "ctrl/ctrl2080/ctrl2080gpumon.h" +#include "ctrl/ctrl2080/ctrl2080clkavfs.h" +#include "ctrl/ctrl2080/ctrl2080volt.h" +#include "ctrl/ctrl2080/ctrl2080pmumon.h" + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h new file mode 100644 index 0000000..570987b --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h @@ -0,0 +1,36 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080clkavfs.finn +// + + + +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "ctrl/ctrl2080/ctrl2080boardobj.h" +#include "ctrl/ctrl2080/ctrl2080volt.h" + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h new file mode 100644 index 0000000..e72e63c --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h @@ -0,0 +1,183 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080dma.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX dma control commands and parameters */ + +/* + * NV2080_CTRL_CMD_DMA_INVALIDATE_TLB + * + * This command invalidates the GPU TLB. This is intended to be used + * by RM clients that manage their own TLB consistency when updating + * page tables on their own, or with DEFER_TLB_INVALIDATION options + * to other RM APIs. + * + * hVASpace + * This parameter specifies the VASpace object whose MMU TLB entries needs to be invalidated. + * Specifying a GMMU VASpace object handle will invalidate the GMMU TLB for the particular VASpace. + * Specifying a SMMU VASpace object handle will flush the entire SMMU TLB & PTC. + * + * This call can be used with the NV50_DEFERRED_API_CLASS (class 0x5080). + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_TIMEOUT_RETRY + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_DMA_INVALIDATE_TLB (0x20802502) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMA_INTERFACE_ID << 8) | NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS { + NvHandle hClient; // Deprecated. Kept here for compactibility with chips_GB9-2-1-1 + NvHandle hDevice; // Deprecated. Kept here for compactibility with chips_GB9-2-1-1 + NvU32 engine; // Deprecated. Kept here for compactibility with chips_GB9-2-1-1 + NvHandle hVASpace; +} NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS; + +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS 0:0 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO 1:1 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY 2:2 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE 3:3 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB 4:4 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV 5:5 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG 6:6 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD 7:7 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION 8:8 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON 9:9 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS 10:10 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR 11:11 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_TRUE (0x00000001) + +/* + * NV2080_CTRL_DMA_INFO + * + * This structure represents a single 32bit dma engine value. Clients + * request a particular DMA engine value by specifying a unique dma + * information index. + * + * Legal dma information index values are: + * NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE + * This index can be used to request the system address size in bits. + */ +typedef struct NV2080_CTRL_DMA_INFO { + NvU32 index; + NvU32 data; +} NV2080_CTRL_DMA_INFO; + +/* valid dma info index values */ +#define NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE (0x000000000) + +/* set INDEX_MAX to greatest possible index value */ +#define NV2080_CTRL_DMA_INFO_INDEX_MAX NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE + +/* + * NV2080_CTRL_CMD_DMA_GET_INFO + * + * This command returns dma engine information for the associated GPU. + * Requests to retrieve dma information use an array of one or more + * NV2080_CTRL_DMA_INFO structures. + * + * dmaInfoTblSize + * This field specifies the number of valid entries in the dmaInfoList + * array. This value cannot exceed NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES. + * dmaInfoTbl + * This parameter contains the client's dma info table into + * which the dma info values will be transferred by the RM. + * The dma info table is an array of NV2080_CTRL_DMA_INFO structures. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_DMA_GET_INFO (0x20802503) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMA_INTERFACE_ID << 8) | NV2080_CTRL_DMA_GET_INFO_PARAMS_MESSAGE_ID" */ + +/* maximum number of NV2080_CTRL_DMA_INFO entries per request */ +#define NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES (256) + +#define NV2080_CTRL_DMA_GET_INFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_DMA_GET_INFO_PARAMS { + NvU32 dmaInfoTblSize; + /* + * C form: + * NV2080_CTRL_DMA_INFO dmaInfoTbl[NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES]; + */ + NV2080_CTRL_DMA_INFO dmaInfoTbl[NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES]; +} NV2080_CTRL_DMA_GET_INFO_PARAMS; + +typedef struct NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO { + /*! + * 64KB aligned address of source 64KB tile for comptag reswizzle. + */ + NvU32 srcAddr; + + /*! + * 64KB aligned address of destination 64KB tile for comptag reswizzle. + */ + NvU32 dstAddr; + + /*! + * Comptag index assigned to the 64K sized tile relative to + * the compcacheline. Absolute comptag index would be: + * startComptagIndex + relComptagIndex. + */ + NvU16 relComptagIndex; +} NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO; + +// _ctrl2080dma_h_ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h new file mode 100644 index 0000000..982381f --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h @@ -0,0 +1,105 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080dmabuf.finn +// + + + +/* + * NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD + * + * Exports RM vidmem handles to a dma-buf fd. + * + * The objects in the 'handles' array are exported to the fd as range: + * [index, index + numObjects). + * + * A dma-buf fd is created the first time this control call is called. + * The fd is an input parameter for subsequent calls to attach additional handles + * over NV2080_CTRL_DMABUF_MAX_HANDLES. + * + * fd + * A dma-buf file descriptor. If -1, a new FD will be created. + * + * totalObjects + * The total number of objects that the client wishes to export to the FD. + * This parameter will be honored only when the FD is getting created. + * + * numObjects + * The number of handles the user wishes to export in this call. + * + * index + * The index into the export fd at which to start exporting the handles in + * 'handles'. This index cannot overlap a previously used index. + * + * totalSize + * The total size of memory being exported in bytes, needed to create the dma-buf. + * This size includes the memory that will be exported in future export calls + * for this dma-buf. + * + * handles + * An array of {handle, offset, size} that describes the dma-buf. + * The offsets and sizes must be OS page-size aligned. + * + * Limitations: + * 1. This call only supports vidmem objects for now. + * 2. All memory handles should belong to the same GPU or the same GPU MIG instance. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_NO_MEMORY + * NV_ERR_OPERATING_SYSTEM + * NV_ERR_IN_USE + * NV_ERR_INVALID_OBJECT + * NV_ERR_INVALID_OBJECT_PARENT + */ +#define NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD (0x20803a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMABUF_INTERFACE_ID << 8) | NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_DMABUF_MAX_HANDLES 128 + +typedef struct NV2080_CTRL_DMABUF_MEM_HANDLE_INFO { + NvHandle hMemory; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); +} NV2080_CTRL_DMABUF_MEM_HANDLE_INFO; + +#define NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS { + NvS32 fd; + NvU32 totalObjects; + NvU32 numObjects; + NvU32 index; + NV_DECLARE_ALIGNED(NvU64 totalSize, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_DMABUF_MEM_HANDLE_INFO handles[NV2080_CTRL_DMABUF_MAX_HANDLES], 8); +} NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS; + +// _ctrl2080dmabuf_h_ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h new file mode 100644 index 0000000..7d0fabe --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080ecc.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + + + +#define NV2080_CTRL_CMD_ECC_GET_CLIENT_EXPOSED_COUNTERS (0x20803400U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS + * + * sramLastClearedTimestamp [out] + * dramLastClearedTimestamp [out] + * unix-epoch based timestamp. These fields indicate when the error counters + * were last cleared by the user. + * + * sramErrorCounts [out] + * dramErrorCounts [out] + * Aggregate error counts for SRAM and DRAM + */ + +#define NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID (0x0U) + +typedef struct NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS { + NvU32 sramLastClearedTimestamp; + NvU32 dramLastClearedTimestamp; + + NV_DECLARE_ALIGNED(NvU64 sramCorrectedTotalCounts, 8); + NV_DECLARE_ALIGNED(NvU64 sramUncorrectedTotalCounts, 8); + NV_DECLARE_ALIGNED(NvU64 dramCorrectedTotalCounts, 8); + NV_DECLARE_ALIGNED(NvU64 dramUncorrectedTotalCounts, 8); +} NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS; +/* _ctrl2080ecc_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h new file mode 100644 index 0000000..e71eb81 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h @@ -0,0 +1,372 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080event.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +#include "nv_vgpu_types.h" +/* NV20_SUBDEVICE_XX event-related control commands and parameters */ + +/* + * NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * This command sets event notification state for the associated subdevice. + * This command requires that an instance of NV01_EVENT has been previously + * bound to the associated subdevice object. + * + * event + * This parameter specifies the type of event to which the specified + * action is to be applied. This parameter must specify a valid + * NV2080_NOTIFIERS value (see cl2080.h for more details) and should + * not exceed one less NV2080_NOTIFIERS_MAXCOUNT. + * action + * This parameter specifies the desired event notification action. + * Valid notification actions include: + * NV2080_CTRL_SET_EVENT_NOTIFICATION_DISABLE + * This action disables event notification for the specified + * event for the associated subdevice object. + * NV2080_CTRL_SET_EVENT_NOTIFICATION_SINGLE + * This action enables single-shot event notification for the + * specified event for the associated subdevice object. + * NV2080_CTRL_SET_EVENT_NOTIFICATION_REPEAT + * This action enables repeated event notification for the specified + * event for the associated system controller object. + * bNotifyState + * This boolean is used to indicate the current state of the notifier + * at the time of event registration. This is optional and its semantics + * needs to be agreed upon by the notifier and client using the notifier + * info32 + * This is used to send 32-bit initial state info with the notifier at + * time of event registration + * info16 + * This is used to send 16-bit initial state info with the notifier at + * time of event registration + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION (0x20800301) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS { + NvU32 event; + NvU32 action; + NvBool bNotifyState; + NvU32 info32; + NvU16 info16; +} NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001) +#define NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002) + +/* XUSB/PPC D-state defines */ +#define NV2080_EVENT_DSTATE_XUSB_D0 (0x00000000) +#define NV2080_EVENT_DSTATE_XUSB_D3 (0x00000003) +#define NV2080_EVENT_DSTATE_XUSB_INVALID (0xFFFFFFFF) +#define NV2080_EVENT_DSTATE_PPC_D0 (0x00000000) +#define NV2080_EVENT_DSTATE_PPC_D3 (0x00000003) +#define NV2080_EVENT_DSTATE_PPC_INVALID (0xFFFFFFFF) + +// HDACODEC Decice DState, D3_COLD is only for verbose mapping, it cannot be logged +typedef enum NV2080_EVENT_HDACODEC_DSTATE { + NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D0 = 0, + NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D1 = 1, + NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D2 = 2, + NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_HOT = 3, + NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_COLD = 4, + NV2080_EVENT_HDACODEC_DEVICE_DSTATE_DSTATE_MAX = 5, +} NV2080_EVENT_HDACODEC_DSTATE; + +/* + * NV2080_CTRL_CMD_EVENT_SET_TRIGGER + * + * This command triggers a software event for the associated subdevice. + * This command accepts no parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_EVENT_SET_TRIGGER (0x20800302) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | 0x2" */ + +/* + * NV2080_CTRL_CMD_EVENT_SET_NOTIFIER_MEMORY + * + * hMemory + * This parameter specifies the handle of the memory object + * that identifies the memory address translation for this + * subdevice instance's notification(s). The beginning of the + * translation points to an array of notification data structures. + * The size of the translation must be at least large enough to hold the + * maximum number of notification data structures identified by + * the NV2080_MAX_NOTIFIERS value. + * Legal argument values must be instances of the following classes: + * NV01_NULL + * NV04_MEMORY + * When hMemory specifies the NV01_NULL_OBJECT value then any existing + * memory translation connection is cleared. There must not be any + * pending notifications when this command is issued. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES (0x20800303) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS { + NvHandle hMemory; +} NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS; + +#define NV2080_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED 0 +#define NV2080_EVENT_MEMORY_NOTIFIES_STATUS_PENDING 1 +#define NV2080_EVENT_MEMORY_NOTIFIES_STATUS_ERROR 2 + +/* + * NV2080_CTRL_CMD_EVENT_SET_SEMAPHORE_MEMORY + * + * hSemMemory + * This parameter specifies the handle of the memory object that + * identifies the semaphore memory associated with this subdevice + * event notification. Once this is set RM will generate an event + * only when there is a change in the semaphore value. It is + * expected that the semaphore memory value will be updated by + * the GPU indicating that there is an event pending. This + * command is used by VGX plugin to determine which virtual + * machine has generated a particular event. + * + * semOffset + * This parameter indicates the memory offset of the semaphore. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_EVENT_SET_SEMAPHORE_MEMORY (0x20800304) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS { + NvHandle hSemMemory; + NvU32 semOffset; +} NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS; + +/* + * NV2080_CTRL_CMD_EVENT_SET_GUEST_MSI + * + * hSemMemory + * This parameter specifies the handle of the memory object that + * identifies the semaphore memory associated with this subdevice + * event notification. Once this is set RM will generate an event + * only when there is a change in the semaphore value. It is + * expected that the semaphore memory value will be updated by + * the GPU indicating that there is an event pending. This + * command is used by VGX plugin to determine which virtual + * machine has generated a particular event. + * + * guestMSIAddr + * This parameter indicates the guest allocated MSI address. + * + * guestMSIData + * This parameter indicates the MSI data set by the guest OS. + * + * vmIdType + * This parameter specifies the type of guest virtual machine identifier + * + * guestVmId + * This parameter specifies the guest virtual machine identifier + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_EVENT_SET_GUEST_MSI (0x20800305) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS { + NV_DECLARE_ALIGNED(NvU64 guestMSIAddr, 8); + NvU32 guestMSIData; + NvHandle hSemMemory; + NvBool isReset; + VM_ID_TYPE vmIdType; + NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); +} NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS; + + +/* + * NV2080_CTRL_CMD_EVENT_SET_SEMA_MEM_VALIDATION + * + * hSemMemory + * This parameter specifies the handle of the memory object that + * identifies the semaphore memory associated with this subdevice + * event notification. Once this is set RM will generate an event + * only when there is a change in the semaphore value. It is + * expected that the semaphore memory value will be updated by + * the GPU indicating that there is an event pending. This + * command is used by VGX plugin to determine which virtual + * machine has generated a particular event. + * + * isSemaMemValidationEnabled + * This parameter used to enable/disable change in sema value check + * while generating an event. + * + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + * NVOS_STATUS_ERROR_INVALID_OBJECT_HANDLE + * NVOS_STATUS_ERROR_INVALID_ARGUMENT + */ + + +#define NV2080_CTRL_CMD_EVENT_SET_SEMA_MEM_VALIDATION (0x20800306) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS { + NvHandle hSemMemory; + NvBool isSemaMemValidationEnabled; +} NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS; + + +/* + * NV2080_CTRL_CMD_EVENT_SET_VMBUS_CHANNEL + * + * hSemMemory + * This parameter specifies the handle of the memory object that + * identifies the semaphore memory associated with this subdevice + * event notification. Once this is set RM will generate an event + * only when there is a change in the semaphore value. It is + * expected that the semaphore memory value will be updated by + * the GPU indicating that there is an event pending. This + * command is used by VGX plugin to determine which virtual + * machine has generated a particular event. + * + * vmIdType + * This parameter specifies the type of guest virtual machine identifier + * + * guestVmId + * This parameter specifies the guest virtual machine identifier + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_EVENT_SET_VMBUS_CHANNEL (0x20800307) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS { + NvHandle hSemMemory; + VM_ID_TYPE vmIdType; + NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); +} NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS; + + +/* + * NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO + * + * This command triggers a FIFO event for the associated subdevice. + * + * hEvent + * Handle of the event that should be notified. If zero, all + * non-stall interrupt events for this subdevice will be notified. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO (0x20800308) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS { + NvHandle hEvent; +} NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS; + +/* + * NV2080_CTRL_CMD_EVENT_VIDEO_BIND_EVTBUF_FOR_UID + * + * This command is used to create a video bind-point to an event buffer that + * is filtered by UID. + * + * hEventBuffer[IN] + * The event buffer to bind to + * + * recordSize[IN] + * The size of the FECS record in bytes + * + * levelOfDetail[IN] + * One of NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_: + * FULL: Report all CtxSw events + * SIMPLE: Report engine start and engine end events only + * CUSTOM: Report events in the eventFilter field + * NOTE: RM may override the level-of-detail depending on the caller + * + * eventFilter[IN] + * Bitmask of events to report if levelOfDetail is CUSTOM + * + * bAllUsers[IN] + * Only report video data for the current user if false, for all users if true + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_EVENT_VIDEO_BIND_EVTBUF (0x20800309) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD { + NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_FULL = 0, + NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_SIMPLE = 1, + NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_CUSTOM = 2, +} NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD; + +#define NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS { + NvHandle hEventBuffer; + NvU32 recordSize; + NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD levelOfDetail; + NvU32 eventFilter; + NvBool bAllUsers; +} NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS; + +/* _ctrl2080event_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080fan.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080fan.h new file mode 100644 index 0000000..a338bab --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080fan.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080fan.finn +// + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h new file mode 100644 index 0000000..a883326 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h @@ -0,0 +1,2906 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080fb.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX fb control commands and parameters */ + +#include "nvlimits.h" + +/* + * NV2080_CTRL_FB_INFO + * + * This structure represents a single 32bit fb engine value. Clients + * request a particular fb engine value by specifying a unique fb + * information index. + * + * Legal fb information index values are: + * NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT + * This index is used to request the number of tiled regions supported + * by the associated subdevice. The return value is GPU + * implementation-dependent. A return value of 0 indicates the GPU + * does not support tiling. + * NV2080_CTRL_FB_INFO_INDEX_COMPRESSION_SIZE + * This index is used to request the amount of compression (in bytes) + * supported by the associated subdevice. The return value is GPU + * implementation-dependent. A return value of 0 indicates the GPU + * does not support compression. + * Nv2080_CTRL_FB_INFO_INDEX_DRAM_PAGE_STRIDE + * This index is used to request the DRAM page stride (in bytes) + * supported by the associated subdevice. The return value is GPU + * implementation-dependent. + * NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_FREE_COUNT + * This index is used to request the number of free tiled regions on + * the associated subdevice. The return value represents the current + * number of free tiled regions at the time the command is processed and + * is not guaranteed to remain unchanged. A return value of 0 indicates + * that there are no available tiled regions on the associated subdevice. + * NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT + * This index is used to request the number of frame buffer partitions + * on the associated subdevice. Starting with Fermi there are now two units + * with the name framebuffer partitions. On those chips this index returns + * the number of FBPAs. For number of FBPs use + * NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE + * This index is used to request the amount of framebuffer memory in + * kilobytes physically present on the associated subdevice. This + * value will never exceed the value reported by + * NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE. + * This an SMC aware attribute, so the per-partition framebuffer memory + * size will be returned when the client has a partition subscription. + * NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE + * This index is used to request the total amount of video memory in + * kilobytes for use with the associated subdevice. This value will + * reflect both framebuffer memory as well as any system memory dedicated + * for use with the subdevice. + * This an SMC aware attribute, so the per-partition video memory size + * will be returned when the client has a partition subscription. + * NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE + * This index is used to request the amount of total RAM in kilobytes + * available for user allocations. This value reflects the total ram + * size less the amount of memory reserved for internal use. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_HEAP_START + * This index is used to request the offset for start of heap in + * kilobytes. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE + * This index is used to request the available amount of video memory in + * kilobytes for use with the associated subdevice or the SMC partition. + * This an SMC aware attribute, thus necessary partition subscription is + * required to query per partition information, if the device is partitioned. + * Alternatively, the SMC/MIG monitor capability can be acquired to query + * aggregate available memory across all the valid partitions. + * NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE + * This index reflects the amount of heap memory in kilobytes that + * is accessible by the CPU. On subdevices with video memory sizes that + * exceed the amount that can be bus mappable this value will be less + * than that reported by NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_BUS_WIDTH + * This index is used to request the FB bus bandwidth on the associated + * subdevice. + * NV2080_CTRL_FB_INFO_INDEX_RAM_CFG + * This index is used to request the implementation-dependent RAM + * configuration value of the associated subdevice. + * NV2080_CTRL_FB_INFO_INDEX_RAM_TYPE + * This index is used to request the type of RAM used for the framebuffer + * on the associated subdevice. Legal RAM types include: + * NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN + * NV2080_CTRL_FB_INFO_RAM_TYPE_SDRAM + * NV2080_CTRL_FB_INFO_RAM_TYPE_DDR1 + * NV2080_CTRL_FB_INFO_RAM_TYPE_DDR2 + * NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR2 + * NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR3 + * NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR4 + * NV2080_CTRL_FB_INFO_RAM_TYPE_DDR3 + * NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5 + * NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5X + * NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6 + * NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6X + * NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR2 + * NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR4 + * NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5 + * NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT + * This index is used to request the number of FB banks on the associated + * subdevice. + * NV2080_CTRL_FB_INFO_INDEX_OVERLAY_OFFSET_ADJUSTMENT + * This index is used to request the offset relative to the start of the + * overlay surface(s), in bytes, at which scanout should happen if the + * primary and the overlay surfaces are all aligned on large page + * boundaries. + * NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_SPACE_SIZE_KB + * This index is used to request the size of the GPU's virtual address + * space in kilobytes. + * NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_HEAP_SIZE_KB + * This index is used to request the size of the GPU's virtual address + * space heap (minus RM-reserved space) in kilobytes. + * NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_MAPPBLE_SIZE_KB + * This index is used to request the size of the GPU's BAR1 mappable + * virtual address space in kilobytes. + * NV2080_CTRL_FB_INFO_INDEX_EFFECTIVE_BW + * This index is deprecated, and returns zero value. + * NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK + * This index is used to request the mask of currently active partitions. + * Each active partition has an ID that's equivalent to the corresponding + * bit position in the mask. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE + * This index is used to request the amount of total RAM in kilobytes + * reserved for internal RM allocations on Vista. This will need to + * be subtracted from the total heap size to get the amount available to + * KMD. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_RAM_LOCATION + * This index is used to distinguish between different memory + * configurations. + * NV2080_CTRL_FB_INFO_INDEX_FB_IS_BROKEN + * This index is used to check if the FB is functional + * NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT + * This index is used to get the number of FBPs on the subdevice. This + * field is not to be confused with + * NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT (returns number of FBPAs). + * Starting with Fermi the term partition is an ambiguous term, both FBP + * and FBPA mean FB partitions. The FBPA is the low level DRAM controller, + * while a FBP is the aggregation of one or more FBPAs, L2, ROP, and some + * other units. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_L2CACHE_SIZE + * This index is used to get the size of the L2 cache in Bytes. + * A value of zero indicates that the L2 cache isn't supported on the + * associated subdevice. + * NV2080_CTRL_FB_INFO_INDEX_MEMORYINFO_VENDOR_ID + * This index is used to get the memory vendor ID information from + * the Memory Information Table in the VBIOS. Legal memory Vendor ID + * values include: + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_UNKNOWN + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_RESERVED + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_SAMSUNG + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_QIMONDA + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ELPIDA + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ETRON + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_NANYA + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_HYNIX + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MOSEL + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_WINBOND + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ESMT + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MICRON + * NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE + * This index is used to request the amount of unused bar1 space. The + * data returned is a value in KB. It is not guaranteed to be entirely + * accurate since it is a snapshot at a particular time and can + * change quickly. + * NV2080_CTRL_FB_INFO_INDEX_BAR1_MAX_CONTIGUOUS_AVAIL_SIZE + * This index is used to request the amount of largest unused contiguous + * block in bar1 space. The data returned is a value in KB. It is not + * guaranteed to be entirely accurate since it is a snapshot at a particular + * time and can change quickly. + * NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE + * This index is used to request the amount of usable framebuffer memory in + * kilobytes physically present on the associated subdevice. This + * value will never exceed the value reported by + * NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_LTC_COUNT + * Returns the active LTC count across all active FBPs. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_LTS_COUNT + * Returns the active LTS count across all active LTCs. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_PSEUDO_CHANNEL_MODE + * This is used to identify if pseudo-channel mode is enabled for HBM + * NV2080_CTRL_FB_INFO_INDEX_SMOOTHDISP_RSVD_BAR1_SIZE + * This is used by WDDM-KMD to determine whether and how much RM reserved BAR1 for smooth transition + * NV2080_CTRL_FB_INFO_INDEX_HEAP_OFFLINE_SIZE + * Returns the total size of the all dynamically offlined pages in KiB + * NV2080_CTRL_FB_INFO_INDEX_1TO1_COMPTAG_ENABLED + * Returns true if 1to1 comptag is enabled + * NV2080_CTRL_FB_INFO_INDEX_SUSPEND_RESUME_RSVD_SIZE + * Returns the total size of the memory(FB) that will saved/restored during save/restore cycle + * NV2080_CTRL_FB_INFO_INDEX_ALLOW_PAGE_RETIREMENT + * Returns true if page retirement is allowed + * NV2080_CTRL_FB_INFO_POISON_FUSE_ENABLED + * Returns true if poison fuse is enabled + * NV2080_CTRL_FB_INFO_FBPA_ECC_ENABLED + * Returns true if ECC is enabled for FBPA + * NV2080_CTRL_FB_INFO_DYNAMIC_PAGE_OFFLINING_ENABLED + * Returns true if dynamic page blacklisting is enabled + * NV2080_CTRL_FB_INFO_INDEX_FORCED_BAR1_64KB_MAPPING_ENABLED + * Returns true if 64KB mapping on BAR1 is force-enabled + * NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_SIZE + * Returns the P2P mailbox size to be allocated by the client. + * Returns 0 if the P2P mailbox is allocated by RM. + * NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_ALIGNMENT_SIZE + * Returns the P2P mailbox alignment requirement. + * Returns 0 if the P2P mailbox is allocated by RM. + * NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_BAR1_MAX_OFFSET_64KB + * Returns the P2P mailbox max offset requirement. + * Returns 0 if the P2P mailbox is allocated by RM. + * NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB + * Returns total protected memory when memory protection is enabled + * Returns 0 when memory protection is not enabled. + * NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB + * Returns protected memory available for allocation when memory + * protection is enabled. + * Returns 0 when memory protection is not enabled. + * NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE + * Returns the ECC status size (corresponds to subpartitions or channels + * depending on architecture/memory type). + */ +typedef struct NV2080_CTRL_FB_INFO { + NvU32 index; + NvU32 data; +} NV2080_CTRL_FB_INFO; + +/* valid fb info index values */ +#define NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT (0x00000000U) // Deprecated +#define NV2080_CTRL_FB_INFO_INDEX_COMPRESSION_SIZE (0x00000001U) +#define NV2080_CTRL_FB_INFO_INDEX_DRAM_PAGE_STRIDE (0x00000002U) +#define NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_FREE_COUNT (0x00000003U) +#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT (0x00000004U) +#define NV2080_CTRL_FB_INFO_INDEX_BAR1_SIZE (0x00000005U) +#define NV2080_CTRL_FB_INFO_INDEX_BANK_SWIZZLE_ALIGNMENT (0x00000006U) +#define NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE (0x00000007U) +#define NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE (0x00000008U) +#define NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE (0x00000009U) +#define NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE (0x0000000AU) +#define NV2080_CTRL_FB_INFO_INDEX_BUS_WIDTH (0x0000000BU) +#define NV2080_CTRL_FB_INFO_INDEX_RAM_CFG (0x0000000CU) +#define NV2080_CTRL_FB_INFO_INDEX_RAM_TYPE (0x0000000DU) +#define NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT (0x0000000EU) +#define NV2080_CTRL_FB_INFO_INDEX_OVERLAY_OFFSET_ADJUSTMENT (0x0000000FU) // Deprecated (index reused to return 0) +#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_SPACE_SIZE_KB (0x0000000FU) // Deprecated (index reused to return 0) +#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_HEAP_SIZE_KB (0x0000000FU) // Deprecated (index reused to return 0) +#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_MAPPBLE_SIZE_KB (0x0000000FU) // Deprecated (index reused to return 0) +#define NV2080_CTRL_FB_INFO_INDEX_EFFECTIVE_BW (0x0000000FU) // Deprecated (index reused to return 0) +#define NV2080_CTRL_FB_INFO_INDEX_FB_TAX_SIZE_KB (0x00000010U) +#define NV2080_CTRL_FB_INFO_INDEX_HEAP_BASE_KB (0x00000011U) +#define NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_SIZE_KB (0x00000012U) +#define NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_BASE_KB (0x00000013U) +#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK (0x00000014U) +#define NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE (0x00000015U) +#define NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE (0x00000016U) +#define NV2080_CTRL_FB_INFO_INDEX_RAM_LOCATION (0x00000017U) +#define NV2080_CTRL_FB_INFO_INDEX_FB_IS_BROKEN (0x00000018U) +#define NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT (0x00000019U) +#define NV2080_CTRL_FB_INFO_INDEX_FBP_MASK (0x0000001AU) +#define NV2080_CTRL_FB_INFO_INDEX_L2CACHE_SIZE (0x0000001BU) +#define NV2080_CTRL_FB_INFO_INDEX_MEMORYINFO_VENDOR_ID (0x0000001CU) +#define NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE (0x0000001DU) +#define NV2080_CTRL_FB_INFO_INDEX_HEAP_START (0x0000001EU) +#define NV2080_CTRL_FB_INFO_INDEX_BAR1_MAX_CONTIGUOUS_AVAIL_SIZE (0x0000001FU) +#define NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE (0x00000020U) +#define NV2080_CTRL_FB_INFO_INDEX_TRAINIG_2T (0x00000021U) +#define NV2080_CTRL_FB_INFO_INDEX_LTC_COUNT (0x00000022U) +#define NV2080_CTRL_FB_INFO_INDEX_LTS_COUNT (0x00000023U) +#define NV2080_CTRL_FB_INFO_INDEX_L2CACHE_ONLY_MODE (0x00000024U) +#define NV2080_CTRL_FB_INFO_INDEX_PSEUDO_CHANNEL_MODE (0x00000025U) +#define NV2080_CTRL_FB_INFO_INDEX_SMOOTHDISP_RSVD_BAR1_SIZE (0x00000026U) +#define NV2080_CTRL_FB_INFO_INDEX_HEAP_OFFLINE_SIZE (0x00000027U) +#define NV2080_CTRL_FB_INFO_INDEX_1TO1_COMPTAG_ENABLED (0x00000028U) +#define NV2080_CTRL_FB_INFO_INDEX_SUSPEND_RESUME_RSVD_SIZE (0x00000029U) +#define NV2080_CTRL_FB_INFO_INDEX_ALLOW_PAGE_RETIREMENT (0x0000002AU) +#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK (0x0000002BU) +#define NV2080_CTRL_FB_INFO_POISON_FUSE_ENABLED (0x0000002CU) +#define NV2080_CTRL_FB_INFO_FBPA_ECC_ENABLED (0x0000002DU) +#define NV2080_CTRL_FB_INFO_DYNAMIC_PAGE_OFFLINING_ENABLED (0x0000002EU) +#define NV2080_CTRL_FB_INFO_INDEX_FORCED_BAR1_64KB_MAPPING_ENABLED (0x0000002FU) +#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_SIZE (0x00000030U) +#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_ALIGNMENT (0x00000031U) +#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_BAR1_MAX_OFFSET_64KB (0x00000032U) +#define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB (0x00000033U) +#define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB (0x00000034U) +#define NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE (0x00000035U) +#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE (0x00000036U) + +#define NV2080_CTRL_FB_INFO_INDEX_MAX (0x35U) /* finn: Evaluated from "(NV2080_CTRL_FB_INFO_MAX_LIST_SIZE - 1)" */ + +/* valid fb RAM type values */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN (0x00000000U) +#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDRAM (0x00000001U) +#define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR1 (0x00000002U) /* SDDR and GDDR (aka DDR1 and GDDR1) */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2 (0x00000003U) /* SDDR2 Used on NV43 and later */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR2 NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2 /* Deprecated alias */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR2 (0x00000004U) /* GDDR2 Used on NV30 and some NV36 */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR3 (0x00000005U) /* GDDR3 Used on NV40 and later */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR4 (0x00000006U) /* GDDR4 Used on G80 and later (deprecated) */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3 (0x00000007U) /* SDDR3 Used on G9x and later */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR3 NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3 /* Deprecated alias */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5 (0x00000008U) /* GDDR5 Used on GT21x and later */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR2 (0x00000009U) /* LPDDR (Low Power SDDR) used on T2x and later. */ + + +#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR4 (0x0000000CU) /* SDDR4 Used on Maxwell and later */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR4 (0x0000000DU) /* LPDDR (Low Power SDDR) used on T21x and later.*/ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM1 (0x0000000EU) /* HBM1 (High Bandwidth Memory) used on GP100 */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM2 (0x0000000FU) /* HBM2 (High Bandwidth Memory-pseudo channel) */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5X (0x00000010U) /* GDDR5X Used on GP10x */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6 (0x00000011U) /* GDDR6 Used on TU10x */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6X (0x00000012U) /* GDDR6X Used on GA10x */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5 (0x00000013U) /* LPDDR (Low Power SDDR) used on T23x and later.*/ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM3 (0x00000014U) /* HBM3 (High Bandwidth Memory) v3 */ + +/* valid RAM LOCATION types */ +#define NV2080_CTRL_FB_INFO_RAM_LOCATION_GPU_DEDICATED (0x00000000U) +#define NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_SHARED (0x00000001U) +#define NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_DEDICATED (0x00000002U) + +/* valid Memory Vendor ID values */ +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_SAMSUNG (0x00000001U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_QIMONDA (0x00000002U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ELPIDA (0x00000003U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ETRON (0x00000004U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_NANYA (0x00000005U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_HYNIX (0x00000006U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MOSEL (0x00000007U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_WINBOND (0x00000008U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ESMT (0x00000009U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MICRON (0x0000000FU) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_UNKNOWN (0xFFFFFFFFU) + +#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_UNSUPPORTED (0x00000000U) +#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_DISABLED (0x00000001U) +#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_ENABLED (0x00000002U) + +/** + * NV2080_CTRL_CMD_FB_GET_INFO + * + * This command returns fb engine information for the associated GPU. + * Requests to retrieve fb information use a list of one or more + * NV2080_CTRL_FB_INFO structures. + * + * fbInfoListSize + * This field specifies the number of entries on the caller's + * fbInfoList. + * fbInfoList + * This field specifies a pointer in the caller's address space + * to the buffer into which the fb information is to be returned. + * This buffer must be at least as big as fbInfoListSize multiplied + * by the size of the NV2080_CTRL_FB_INFO structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV2080_CTRL_CMD_FB_GET_INFO (0x20801301U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_FB_GET_INFO_PARAMS { + NvU32 fbInfoListSize; + NV_DECLARE_ALIGNED(NvP64 fbInfoList, 8); +} NV2080_CTRL_FB_GET_INFO_PARAMS; + +#define NV2080_CTRL_CMD_FB_GET_INFO_V2 (0x20801303U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_INFO_V2_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_FB_GET_INFO_V2_PARAMS { + NvU32 fbInfoListSize; + NV2080_CTRL_FB_INFO fbInfoList[NV2080_CTRL_FB_INFO_MAX_LIST_SIZE]; +} NV2080_CTRL_FB_GET_INFO_V2_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_GET_TILE_ADDRESS_INFO + * + * This command returns tile addressing information. + * + * StartAddr + * This parameter returns BAR1 plus the size of the local FB. + * SpaceSize + * This parameter returns the BAR1 aperture size less the size of the + * local FB. + * + * Note that both parameters will contain zero if there is no system tile + * address space. + */ +#define NV2080_CTRL_CMD_FB_GET_TILE_ADDRESS_INFO (0x20801302U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2" */ + +typedef struct NV2080_CTRL_FB_GET_SYSTEM_TILE_ADDRESS_SPACE_INFO { + NV_DECLARE_ALIGNED(NvU64 StartAddr, 8); + NV_DECLARE_ALIGNED(NvU64 SpaceSize, 8); +} NV2080_CTRL_FB_GET_SYSTEM_TILE_ADDRESS_SPACE_INFO; + +/* + * NV2080_CTRL_CMD_FB_GET_BAR1_OFFSET + * + * This command returns the GPU virtual address of a bar1 + * allocation, given the CPU virtual address. + * + * cpuVirtAddress + * This field specifies the associated CPU virtual address of the + * memory allocation. + * gpuVirtAddress + * The GPU virtual address associated with the allocation + * is returned in this field. + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_GET_BAR1_OFFSET (0x20801310U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS { + NV_DECLARE_ALIGNED(NvP64 cpuVirtAddress, 8); + NV_DECLARE_ALIGNED(NvU64 gpuVirtAddress, 8); +} NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS; + +/* + * Note: Returns Zeros if no System carveout address info + * + * NV2080_CTRL_CMD_FB_GET_CARVEOUT_ADDRESS_INFO + * + * This command returns FB carveout address space information + * + * StartAddr + * Returns the system memory address of the start of carveout space. + * SpaceSize + * Returns the size of carveout space. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_FB_GET_CARVEOUT_ADDRESS_INFO (0x2080130bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO_MESSAGE_ID (0xBU) + +typedef struct NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO { + NV_DECLARE_ALIGNED(NvU64 StartAddr, 8); + NV_DECLARE_ALIGNED(NvU64 SpaceSize, 8); +} NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO; + +/* + * NV2080_CTRL_FB_CMD_GET_CALIBRATION_LOCK_FAILED + * + * This command returns the failure counts for calibration. + * + * uFlags + * Just one for now -- ehether to reset the counts. + * driveStrengthRiseCount + * This parameter specifies the failure count for drive strength rising. + * driveStrengthFallCount + * This parameter specifies the failure count for drive strength falling. + * driveStrengthTermCount + * This parameter specifies the failure count for drive strength + * termination. + * slewStrengthRiseCount + * This parameter specifies the failure count for slew strength rising. + * slewStrengthFallCount + * This parameter specifies the failure count for slew strength falling. + * slewStrengthTermCount + * This parameter specifies the failure count for slew strength + * termination. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INVALID_PARAM_STRUCT + * NVOS_STATUS_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_GET_CALIBRATION_LOCK_FAILED (0x2080130cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS { + NvU32 flags; + NvU32 driveStrengthRiseCount; + NvU32 driveStrengthFallCount; + NvU32 driveStrengthTermCount; + NvU32 slewStrengthRiseCount; + NvU32 slewStrengthFallCount; +} NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS; + +/* valid flags parameter values */ +#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE (0x00000000U) +#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET (0x00000001U) + +/* + * NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOWED + * + * This command specifies to RM if scanout compaction feature is allowed or + * not in the current configuration. In hybrid mode when dGPU is rendering the + * image, the dGPU blit to the scanout surface happens without mGPU's + * knowledge (directly to system memory), which results in stale compacted + * data resulting in corruption. + * + * This control call can be used to disable the compaction whenever the KMD + * (client) is switching to the pref mode in Hybrid i.e., whenever there is a + * possibility of dGPU doing a blit to mGpu scanout surface. Compaction can + * be enabled when system is back in hybrid power mode as mGpu will be + * rendering the image. + * + * allowCompaction + * This parameter specifies if the display compaction feature is allowed + * or not allowed. + * immediate + * This parameter specifies whether compaction has to be enabled or + * disabled immediately (based on the value of allowCompaction field) or + * during the next modeset. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INVALID_PARAM_STRUCT + * NVOS_STATUS_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOWED (0x2080130dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0xD" */ // Deprecated, removed form RM + +typedef struct NV2080_CTRL_FB_SET_SCANOUT_COMPACTION_ALLOWED_PARAMS { + NvU32 allowCompaction; + NvU32 immediate; +} NV2080_CTRL_FB_SET_SCANOUT_COMPACTION_ALLOWED_PARAMS; + +/* valid allowCompaction values */ +#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOW (0x00000001U) +#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_DISALLOW (0x00000000U) + +/* valid immediate values */ +#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_IMMEDIATE (000000001U) +#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_NOT_IMMEDIATE (000000000U) + +/* + * NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE + * + * This command flushes a cache on the GPU which all memory accesses go + * through. The types of flushes supported by this API may not be supported by + * all hardware. Attempting an unsupported flush type will result in an error. + * + * addressArray + * An array of physical addresses in the aperture defined by + * NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE. Each entry points to a + * contiguous block of memory of size memBlockSizeBytes. The addresses are + * aligned down to addressAlign before coalescing adjacent addresses and + * sending flushes to hardware. + * addressAlign + * Used to align-down addresses held in addressArray. A value of 0 will be + * forced to 1 to avoid a divide by zero. Value is treated as minimum + * alignment and any hardware alignment requirements above this value will + * be honored. + * addressArraySize + * The number of entries in addressArray. + * memBlockSizeBytes + * The size in bytes of each memory block pointed to by addressArray. + * flags + * Contains flags to control various aspects of the flush. Valid values + * are defined in NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS*. Not all flags are + * valid for all defined FLUSH_MODEs or all GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + * + * See Also: + * NV0080_CTRL_CMD_DMA_FLUSH + * Performs flush operations in broadcast for the GPU cache and other hardware + * engines. Use this call if you want to flush all GPU caches in a + * broadcast device. + * NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE + * Flushes memory associated with a single allocation if the hardware + * supports it. Use this call if you want to flush a single allocation and + * you have a memory object describing the physical memory. + */ +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE (0x2080130eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES 500U + +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 addressArray[NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES], 8); + NvU32 addressArraySize; + NvU32 addressAlign; + NV_DECLARE_ALIGNED(NvU64 memBlockSizeBytes, 8); + NvU32 flags; +} NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS; + +/* valid fields and values for flags */ +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE 1:0 +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_VIDEO_MEMORY (0x00000000U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_SYSTEM_MEMORY (0x00000001U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_PEER_MEMORY (0x00000002U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK 2:2 +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_NO (0x00000000U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_YES (0x00000001U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE 3:3 +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_NO (0x00000000U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_YES (0x00000001U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE 4:4 +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_ADDRESS_ARRAY (0x00000000U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_FULL_CACHE (0x00000001U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH 5:5 +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_NO (0x00000000U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_YES (0x00000001U) + +/* + * NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY (deprecated; use NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2 instead) + * + * These commands access the cache allocation policy on a specific + * engine, if supported. + * + * engine + * Specifies the target engine. Possible values are defined in + * NV2080_ENGINE_TYPE. + * allocPolicy + * Specifies the read/write allocation policy of the cache on the specified + * engine. Possible values are defined in + * NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS and + * NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES. + * + */ +typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS { + NvU32 engine; + NvU32 allocPolicy; +} NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS; + +/* valid values for allocPolicy */ +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS 0:0 +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_NO (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_YES (0x00000001U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES 1:1 +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_NO (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_YES (0x00000001U) + + +/* + * NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY + * + * This command is deprecated. + * Use NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2 instead. + * + * This command sets the state of the cache allocation policy on a specific + * engine, if supported. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY (0x2080130fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0xF" */ + +/* + * NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAM + * + * These commands access the cache allocation policy on a specific + * client, if supported. + * + * count + * Specifies the number of entries in entry. + * entry + * Specifies an array of allocation policy entries. + * + * NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY + * + * clients + * Specifies the target client. Possible values are defined in + * NV2080_CLIENT_TYPE_*. + * allocPolicy + * Specifies the read/write allocation policy of the cache on the specified + * engine. Possible values are defined in + * NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS and + * NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES. + * + * NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY_SIZE + * + * Specifies the maximum number of allocation policy entries allowed + */ +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY_SIZE 11U + +typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY { + NvU32 client; + NvU32 allocPolicy; +} NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY; + +typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS { + NvU32 count; + NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY entry[NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY_SIZE]; +} NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS; + +/* valid values for allocPolicy */ +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS 0:0 +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_DISABLE (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ENABLE (0x00000001U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ALLOW 1:1 +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ALLOW_NO (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ALLOW_YES (0x00000001U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES 2:2 +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_DISABLE (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ENABLE (0x00000001U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ALLOW 3:3 +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ALLOW_NO (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ALLOW_YES (0x00000001U) + + +/* + * NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2 + * + * This command sets the state of the cache allocation policy on a specific + * engine, if supported. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801318U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x18" */ + +/* + * NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY (deprecated; use NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 instead) + * + * This command gets the state of the cache allocation policy on a specific + * engine, if supported. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY (0x20801312U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x12" */ + +/* + * NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 + * + * This command gets the state of the cache allocation policy on a specific + * engine, if supported. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801319U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x19" */ + + +/* + * NV2080_CTRL_CMD_FB_IS_KIND + * + * This command is used to perform various operations like 'IS_KIND_VALID', + * 'IS_KIND_COMPRESSIBLE'on the kind passed by the caller. The operation to be + * performed should be passed in the 'operation' parameter of + * NV2080_CTRL_FB_IS_KIND_PARAMS, the kind on which the operation is to be + * performed should be passed in the 'kind' parameter. The result of the + * operation (true/false) will be returned in the 'result' parameter. + * + * operation + * Specifies what operation is to be performed on the kind passed by the + * caller. The supported operations are + * NV2080_CTRL_FB_IS_KIND_OPERATION_SUPPORTED + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure is + * supported for this GPU. Returns nonzero value in 'result' parameter + * if the input kind is supported, else returns zero in the result. + * NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure is + * compressible. Returns nonzero value in 'result' parameter if the + * input kind is compressible, else returns zero in the result. + * NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_1 + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure supports + * 1 bit compression. Returns nonzero value in 'result' parameter if + * kind supports 1 bit compression, else returns zero in the result. + * NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_2 + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure supports + * 2 bit compression. Returns nonzero value in 'result' parameter if + * kind supports 1 bit compression, else returns zero in the result. + * NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_4 + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure supports + * 4 bit compression. Returns nonzero value in 'result' parameter if + * kind supports 4 bit compression, else returns zero in the result. + * NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure + * supports ZBC. Returns nonzero value in 'result' parameter if the + * input kind supports ZBC, else returns zero in the result. + * NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_1 + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure + * supports 1 bit ZBC. Returns nonzero value in 'result' parameter if + * the input kind supports 1 bit ZBC, else returns zero in the result. + * NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_2 + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure + * supports 2 bit ZBC. Returns nonzero value in 'result' parameter if + * the input kind supports 2 bit ZBC, else returns zero in the result. + * NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_4 + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure + * supports 4 bit ZBC. Returns nonzero value in 'result' parameter if + * the input kind supports 4 bit ZBC, else returns zero in the result. + * kind + * Specifies the kind on which the operation is to be carried out. The + * legal range of values for the kind parameter is different on different + * GPUs. For e.g. on Fermi, valid range is 0x00 to 0xfe. Still, some values + * inside this legal range can be invalid i.e. not defined. + * So its always better to first check if a particular kind is supported on + * the current GPU with 'NV2080_CTRL_FB_IS_KIND_SUPPORTED' operation. + * result + * Upon return, this parameter will hold the result (true/false) of the + * operation performed on the kind. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_IS_KIND (0x20801313U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV2080_CTRL_FB_IS_KIND_PARAMS { + NvU32 operation; + NvU32 kind; + NvBool result; +} NV2080_CTRL_FB_IS_KIND_PARAMS; + +/* valid values for operation */ +#define NV2080_CTRL_FB_IS_KIND_OPERATION_SUPPORTED (0x00000000U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE (0x00000001U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_1 (0x00000002U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_2 (0x00000003U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_4 (0x00000004U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC (0x00000005U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_1 (0x00000006U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_2 (0x00000007U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_4 (0x00000008U) + +/** + * NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO + * + * This command returns the state of a cache which all GPU memory accesess go + * through. + * + * powerState + * Returns the power state of the cache. Possible values are defined in + * NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE. + * + * writeMode + * Returns the write mode of the cache. Possible values are defined in + * NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE. + * + * bypassMode + * Returns the bypass mode of the L2 cache. Possible values are defined in + * NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE. + * + * rcmState + * Returns the RCM state of the cache. Possible values are defined in + * NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO (0x20801315U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS { + NvU32 powerState; + NvU32 writeMode; + NvU32 bypassMode; + NvU32 rcmState; +} NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS; + +/* valid values for powerState */ +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_ENABLED (0x00000000U) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_DISABLED (0x00000001U) +/* valid values for writeMode */ +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITETHROUGH (0x00000000U) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITEBACK (0x00000001U) +/* valid values for bypassMode */ +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_DISABLED (0x00000000U) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_ENABLED (0x00000001U) +/* valid values for rcmState */ +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_FULL (0x00000000U) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_TRANSITIONING (0x00000001U) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_REDUCED (0x00000002U) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_ZERO_CACHE (0x00000003U) + +/* + * NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY + * + * These commands access the cache promotion policy on a specific + * engine, if supported by the hardware. + * + * Cache promotion refers to the GPU promoting a memory read to a larger + * size to preemptively fill the cache so future reads to nearby memory + * addresses will hit in the cache. + * + * engine + * Specifies the target engine. Possible values are defined in + * NV2080_ENGINE_TYPE. + * promotionPolicy + * Specifies the promotion policy of the cache on the specified + * engine. Possible values are defined by + * NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_*. These values are in terms + * of the hardware cache line size. + * + */ +typedef struct NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS { + NvU32 engine; + NvU32 promotionPolicy; +} NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS; + +/* valid values for promotionPolicy */ +#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_NONE (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_QUARTER (0x00000001U) +#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_HALF (0x00000002U) +#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_FULL (0x00000003U) + + +/* + * NV2080_CTRL_CMD_FB_SET_GPU_CACHE_PROMOTION_POLICY + * + * This command sets the cache promotion policy on a specific engine, if + * supported by the hardware. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_PROMOTION_POLICY (0x20801316U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x16" */ // Deprecated, removed form RM + + +/* + * NV2080_CTRL_CMD_FB_GET_GPU_CACHE_PROMOTION_POLICY + * + * This command gets the cache promotion policy on a specific engine, if + * supported by the hardware. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_PROMOTION_POLICY (0x20801317U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x17" */ // Deprecated, removed form RM + +/* + * NV2080_CTRL_FB_CMD_GET_FB_REGION_INFO + * + * This command returns the FB memory region characteristics. + * + * numFBRegions + * Number of valid regions returned in fbRegion[] + * fbRegion[].base + * Base address of region. The first valid address in the range + * [base..limit]. + * fbRegion[].limit + * Last/end address of region. The last valid address in the range + * [base..limit]. + * (limit - base + 1) = size of the region + * fbRegion[].reserved + * Amount of memory that RM speculatively needs within the region. A + * client doing its own memory management should leave at least this much + * memory available for RM use. This particularly applies to a driver + * model like LDDM. + * fbRegion[].performance + * Relative performance of this region compared to other regions. + * The definition is vague, and only connotes relative bandwidth or + * performance. The higher the value, the higher the performance. + * fbRegion[].supportCompressed + * TRUE if compressed surfaces/kinds are supported + * FALSE if compressed surfaces/kinds are not allowed to be allocated in + * this region + * fbRegion[].supportISO + * TRUE if ISO surfaces/kinds are supported (Display, cursor, video) + * FALSE if ISO surfaces/kinds are not allowed to be allocated in this + * region + * fbRegion[].bProtected + * TRUE if this region is a protected memory region. If true only + * allocations marked as protected (NVOS32_ALLOC_FLAGS_PROTECTED) can be + * allocated in this region. + * fbRegion[].blackList[] - DEPRECATED: Use supportISO + * TRUE for each NVOS32_TYPE_IMAGE* that is NOT allowed in this region. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO (0x20801320U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES 17U + +typedef NvBool NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES]; + +typedef struct NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO { + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 limit, 8); + NV_DECLARE_ALIGNED(NvU64 reserved, 8); + NvU32 performance; + NvBool supportCompressed; + NvBool supportISO; + NvBool bProtected; + NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG blackList; +} NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO; + +#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES 16U + +#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS { + NvU32 numFBRegions; + NV_DECLARE_ALIGNED(NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO fbRegion[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES], 8); +} NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_OFFLINE_PAGES + * + * This command adds video memory page addresses to the list of offlined + * addresses so that they're not allocated to any client. The newly offlined + * addresses take effect after a reboot. + * + * offlined + * This input parameter is an array of NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO + * structures, containing the video memory physical page numbers that + * are to be blacklisted. This array can hold a maximum of NV2080_CTRL_FB_ + * BLACKLIST_PAGES_MAX_PAGES address pairs. Valid entries are adjacent. + * pageSize + * This input parameter contains the size of the page that is to be + * blacklisted. + * validEntries + * This input parameter specifies the number of valid entries in the + * offlined array. + * numPagesAdded + * This output parameter specifies how many of the validEntries were + * actually offlined. If numPagesAdded < validEntries, it + * means that only addresses from offlined[0] to offlined[numPagesAdded - 1] + * were added to the list of offlined addresses. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_OFFLINE_PAGES (0x20801321U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES (0x00000040U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_INVALID_ADDRESS (0xffffffffffffffffULL) +#define NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_4K (0x00000000U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_64K (0x00000001U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_128K (0x00000002U) + +/* + * NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO + * + * pageAddressWithEccOn + * Address of the memory page retired when ECC is enabled on the board. + * pageAddressWithEccOff + * Address of the memory page retired when ECC is disabled on the board. + * rbcAddress + * Row/Bank/Column Address of the faulty memory which caused the page to + * be retired + * source + * The reason for the page to be retired + * status + * Non-exceptional reasons for a page retirement failure + * NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_OK + * No error + * NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_PENDING_RETIREMENT + * The given address is already pending retirement or has + * been retired during the current driver run. The page + * will be offlined during the next driver run. + * NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_BLACKLISTING_FAILED + * The given page was retired on a previous driver run, + * so it should not be accessible unless offlining failed. + * Failing to offline a page is strongly indicative of a + * driver offlining bug. + * NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_TABLE_FULL + * The PBL is full and no more pages can be retired + * NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_INTERNAL_ERROR + * Internal driver error + * + */ + + + +typedef struct NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO { + NV_DECLARE_ALIGNED(NvU64 pageAddressWithEccOn, 8); + NV_DECLARE_ALIGNED(NvU64 pageAddressWithEccOff, 8); + NvU32 rbcAddress; + NvU32 source; + NvU32 status; + NvU32 timestamp; +} NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO; + +/* valid values for source */ +#define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE (0x00000002U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE (0x00000004U) + + + +/* valid values for status */ +#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_OK (0x00000000U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_PENDING_RETIREMENT (0x00000001U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_BLACKLISTING_FAILED (0x00000002U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_TABLE_FULL (0x00000003U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_INTERNAL_ERROR (0x00000004U) + +/* deprecated */ +#define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_MULTIPLE_SBE NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE +#define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DBE NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE + + +#define NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS_MESSAGE_ID (0x21U) + +typedef struct NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO offlined[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES], 8); + NvU32 pageSize; + NvU32 validEntries; + NvU32 numPagesAdded; +} NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_GET_OFFLINED_PAGES + * + * This command returns the list of video memory page addresses in the + * Inforom's blacklist. + * + * offlined + * This output parameter is an array of NV2080_CTRL_FB_BLACKLIST_ADDRESS_ + * INFO structures, containing the video memory physical page numbers that + * are blacklisted. This array can hold a maximum of NV2080_CTRL_FB_ + * BLACKLIST_PAGES_MAX_PAGES address pairs. Valid entries are adjacent. + * The array also contains the Row/Bank/Column Address and source. + * validEntries + * This output parameter specifies the number of valid entries in the + * offlined array. + * bRetirementPending (DEPRECATED, use retirementPending instead) + * This output parameter returns if any pages on the list are pending + * retirement. + * retirementPending + * Communicates to the caller whether retirement updates are pending and the + * reason for the updates. Possible fields are: + * NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_*: + * NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE: + * Indicates whether pages are pending retirement due to SBE. + * NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE: + * Indicates whether pages are pending retirement due to DBE. Driver + * reload needed to retire bad memory pages and allow compute app runs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + + + +#define NV2080_CTRL_CMD_FB_GET_OFFLINED_PAGES (0x20801322U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE 0:0 +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_FALSE 0U +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_TRUE 1U +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE 1:1 +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_FALSE 0U +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_TRUE 1U + + + +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO offlined[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES], 8); + NvU32 validEntries; + NvBool bRetirementPending; + NvU8 retirementPending; +} NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_QUERY_ACR_REGION + * + * This control command is used to query the secured region allocated + * + * queryType + * NV2080_CTRL_CMD_FB_ACR_QUERY_GET_REGION_STATUS: Provides the alloc + * status and ACR region ID. + * NV2080_CTRL_CMD_FB_QUERY_MAP_REGION : Maps the region on BAR1 + * it returns the "pCpuAddr" and pPriv to user. + * NV2080_CTRL_CMD_FB_QUERY_UNMAP_REGION: Unmaps the mapped region. + * it takes the pPriv as input + * + * clientReq : struct ACR_REQUEST_PARAMS + * It is used to find the allocated ACR region for that client + * clientId : ACR Client ID + * reqReadMask : read mask of ACR region + * reqWriteMask : Write mask of ACR region + * regionSize : ACR region Size + * + * clientReqStatus : struct ACR_STATUS_PARAMS + * This struct is stores the output of requested ACR region. + * allocStatus : Allocated Status of ACR region + * regionId : ACR region ID + * physicalAddress : Physical address on FB + * + * + * NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE + * NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_NONE : Control command executed successfully + * NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_INVALID_CLIENT_REQUEST : Please check the parameter + * for ACR client request + * NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_FAILED_TO_MAP_ON_BAR1 : RM Fails to map ACR region + * on BAR1 + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED +*/ +#define NV2080_CTRL_CMD_FB_QUERY_ACR_REGION (0x20801325U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS_MESSAGE_ID" */ + +// +// We can create an ACR region by using RMCreateAcrRegion[1|2] regkey or mods -acr[1|2]_size +// Client ID for such region is 2 in RM. +// +#define NV2080_CTRL_CMD_FB_ACR_CLIENT_ID 2U + +typedef enum NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE { + NV2080_CTRL_CMD_FB_ACR_QUERY_GET_CLIENT_REGION_STATUS = 0, + NV2080_CTRL_CMD_FB_ACR_QUERY_GET_REGION_PROPERTY = 1, + NV2080_CTRL_CMD_FB_ACR_QUERY_GET_FALCON_STATUS = 2, +} NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE; + +typedef enum NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE { + NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_NONE = 0, + NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_INVALID_CLIENT_REQUEST = 1, +} NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE; + +typedef struct ACR_REQUEST_PARAMS { + NvU32 clientId; + NvU32 reqReadMask; + NvU32 reqWriteMask; + NvU32 regionSize; +} ACR_REQUEST_PARAMS; + +typedef struct ACR_REGION_ID_PROP { + NvU32 regionId; + NvU32 readMask; + NvU32 writeMask; + NvU32 regionSize; + NvU32 clientMask; + NV_DECLARE_ALIGNED(NvU64 physicalAddress, 8); +} ACR_REGION_ID_PROP; + +typedef struct ACR_STATUS_PARAMS { + NvU32 allocStatus; + NvU32 regionId; + NV_DECLARE_ALIGNED(NvU64 physicalAddress, 8); +} ACR_STATUS_PARAMS; + +typedef struct ACR_REGION_HANDLE { + NvHandle hClient; + NvHandle hParent; + NvHandle hMemory; + NvU32 hClass; + NvHandle hDevice; +} ACR_REGION_HANDLE; + +typedef struct ACR_FALCON_LS_STATUS { + NvU16 falconId; + NvBool bIsInLs; +} ACR_FALCON_LS_STATUS; + +#define NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS_MESSAGE_ID (0x25U) + +typedef struct NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS { + NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE queryType; + NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE errorCode; + NV_DECLARE_ALIGNED(ACR_REGION_ID_PROP acrRegionIdProp, 8); + ACR_REQUEST_PARAMS clientReq; + NV_DECLARE_ALIGNED(ACR_STATUS_PARAMS clientReqStatus, 8); + ACR_REGION_HANDLE handle; + ACR_FALCON_LS_STATUS falconStatus; +} NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_CLEAR_OFFLINED_PAGES + * + * This command clears offlined video memory page addresses from the Inforom. + * + * sourceMask + * This is a bit mask of NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE. Pages + * offlined from the specified sources will be cleared/removed from the + * Inforom PBL object denylist. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_CLEAR_OFFLINED_PAGES (0x20801326U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS_MESSAGE_ID (0x26U) + +typedef struct NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS { + NvU32 sourceMask; +} NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO + * + * Gets pointer to then object of class CompBitCopy, which is used for swizzling + * compression bits in the compression backing store. The caller is expected to + * have the appropriate headers for class CompBitCopy. Also retrieves values of some + * parameters needed to call the compbit swizzling method. + * + * @params[out] void *pCompBitCopyObj + * Opaque pointer to object of class CompBitCopy + * @params[out] void *pSwizzleParams + * Opaque pointer to values needed to call the compbit + * swizzle method. + * + * Possible status values returned are: + * NV_OK NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO (0x20801327U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS_MESSAGE_ID (0x27U) + +typedef struct NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pCompBitCopyObj, 8); + NV_DECLARE_ALIGNED(NvP64 pSwizzleParams, 8); +} NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_GET_LTC_INFO_FOR_FBP + * + * Gets the count and mask of LTCs for a given FBP. + * + * fbpIndex + * The physical index of the FBP to get LTC info for. + * ltcMask + * The mask of active LTCs for the given FBP. + * ltcCount + * The count of active LTCs for the given FBP. + * ltsMask + * The mask of active LTSs for the given FBP + * ltsCount + * The count of active LTSs for the given FBP + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_GET_LTC_INFO_FOR_FBP (0x20801328U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_MESSAGE_ID (0x28U) + +typedef struct NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS { + NvU8 fbpIndex; + NvU32 ltcMask; + NvU32 ltcCount; + NvU32 ltsMask; + NvU32 ltsCount; +} NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS; + + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT < Deprecated > + * + * "set the context" for following CompBitCopy member functions. + * These are the CompBitCopy member variables that remain connstant + * over multiple CompBitCopy member function calls, yet stay the same + * throughout a single surface eviction. + * + * @params[in] UINT64 backingStorePA; + * Physical Address of the Backing Store + * @params[in] UINT08 *backingStoreVA; + * Virtual Address of the Backing Store + * @params[in] UINT64 backingStoreChunkPA; + * Physical Address of the "Chunk Buffer" + * @params[in] UINT08 *backingStoreChunkVA; + * Virtual Address of the "Chunk Buffer" + * @params[in] UINT32 backingStoreChunkSize; + * Size of the "Chunk Buffer" + * @params[in] UINT08 *cacheWriteBitMap; + * Pointer to the bitmap which parts of the + * "Chunk" was updated. + * @params[in] bool backingStoreChunkOverfetch; + * Overfetch factor. + * @params[in] UINT32 PageSizeSrc; + * Page size of Source Surface. + * @params[in] UINT32 PageSizeDest; + * page size of Destination Surface. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT (0x20801329U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x29" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS { + NvU32 CBCBaseAddress; + NV_DECLARE_ALIGNED(NvU64 backingStorePA, 8); + NV_DECLARE_ALIGNED(NvU8 *backingStoreVA, 8); + NV_DECLARE_ALIGNED(NvU64 backingStoreChunkPA, 8); + NV_DECLARE_ALIGNED(NvU8 *backingStoreChunkVA, 8); + NvU32 backingStoreChunkSize; + NV_DECLARE_ALIGNED(NvU8 *cacheWriteBitMap, 8); + NvBool backingStoreChunkOverfetch; + NvU32 PageSizeSrc; + NvU32 PageSizeDest; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS < Deprecated > + * + * Retrieves the Compression and Fast Clear bits for the surface+offset given. + * + * @params[out] NvU32 *fcbits; + * Fast Clear Bits returned + * @params[out] NvU32 *compbits; + * Compression Bits returned + * @params[in] NvU64 dataPhysicalStart; + * Start Address of Data + * @params[in] NvU64 surfaceOffset; + * Offset in the surface + * @params[in] NvU32 comptagLine; + * Compression Tag Number + * @params[in] NvBool upper64KBCompbitSel; + * Selects Upper or Lower 64K + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTEDD + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS (0x2080132aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2A" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS { + NV_DECLARE_ALIGNED(NvU32 *fcbits, 8); + NV_DECLARE_ALIGNED(NvU32 *compbits, 8); + NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8); + NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8); + NvU32 comptagLine; + NvBool upper64KBCompbitSel; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS < Deprecated > + * + * Sets the Compression and Fast Clear bits for the surface+offset given. + * + * @params[in] NvU32 fcbits; + * Fast Clear Bits to write. + * @params[in] NvU32 compbits; + * Compression Bits to write + * @params[in] NvBool writeFc; + * Indicates if Fast Clear Bits should be written + * @params[in] NvU64 dataPhysicalStart; + * Start Address of Data + * @params[in] NvU64 surfaceOffset; + * Offset in the surface + * @params[in] NvU32 comptagLine; + * Compression Tag Number + * @params[in] NvBool upper64KBCompbitSel; + * Selects Upper or Lower 64K + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS (0x2080132bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2B" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS { + NvU32 fcbits; + NvU32 compbits; + NvBool writeFc; + NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8); + NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8); + NvU32 comptagLine; + NvBool upper64KBCompbitSel; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB < Deprecated > + * + * Read 64KB chunk of CompBits + * + * @params[in] NvU64 SrcDataPhysicalStart; + * Start Address of Data + * @params[in] NvU32 SrcComptagLine; + * Compression Tag Number + * @params[in] NvU32 page64KB; + * Which 64K block to read from. + * @params[out] NvU32 *compbitBuffer; + * Buffer for CompBits read, + * @params[in] NvBool upper64KBCompbitSel; + * Selects Upper or Lower 64K + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB (0x2080132cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2C" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS { + NV_DECLARE_ALIGNED(NvU64 SrcDataPhysicalStart, 8); + NvU32 SrcComptagLine; + NvU32 page64KB; + NV_DECLARE_ALIGNED(NvU32 *compbitBuffer, 8); + NvBool upper64KBCompbitSel; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB < Deprecated > + * + * Write 64K chunk of COmpBits. + * + * @params[in] NvU64 SrcDataPhysicalStart; + * Start Address of Data + * @params[in] NvU32 SrcComptagLine; + * Compression Tag Number + * @params[in] NvU32 page64KB; + * Which 64K block to read from. + * @params[in] NvU32 *compbitBuffer; + * Buffer for CompBits to write. + * @params[in] NvBool upper64KBCompbitSel + * Selects Upper or Lower 64K + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB (0x2080132dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2D" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS { + NV_DECLARE_ALIGNED(NvU64 DstDataPhysicalStart, 8); + NvU32 DstComptagLine; + NvU32 page64KB; + NV_DECLARE_ALIGNED(NvU32 *compbitBuffer, 8); + NvBool upper64KBCompbitSel; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS < Deprecated > + * + * The PS (Performance Path, or Optimized path, or Per Slice version) + * of PutCompBits. + * + * @params[out] NvU32 *fcbits; + * Buffer to receive Fast Clear Bits. + * @params[out] NvU32 *compbits; + * Buffer to receive Compression Bits. + * @params[out] NvU32 *compCacheLine; + * Buffer to receive Comp Cache Line data. + * @params[in] NvU64 dataPhysicalStart; + * Start Address of Data + * @params[in] NvU64 surfaceOffset; + * Offset in the surface + * @params[in] NvU32 comptagLine; + * Compression Tag Line Number + * @params[in] NvU32 ROPTile_offset; + * Offset in the surface of the ROP tile. + * @params[in] NvBool upper64KBCompbitSel; + * Selects Upper or Lower 64K + * @params[in] NvBool getFcBits; + * Indicates if fast clear bits should be returned. + * @params[in] NvP64 derivedParams + * Actually a CompBitDerivedParams structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS (0x2080132eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2E" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS_PARAMS { + NV_DECLARE_ALIGNED(NvU32 *fcbits, 8); + NV_DECLARE_ALIGNED(NvU32 *compbits, 8); + NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8); + NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8); + NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8); + NvU32 comptagLine; + NvU32 ROPTile_offset; + NvBool upper64KBCompbitSel; + NvBool getFcBits; + NV_DECLARE_ALIGNED(NvP64 derivedParams, 8); +} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS < Deprecated > + * + * The PS (Performance Path, or Optimized path, or Per Slice version) + * of GetCompBits. + * + * @params[in] NvU32 fcbits; + * Buffer with Fast Clear Bits to write. + * @params[in] NvU32 compbits; + * Buffer to receive Compression Bits. + * @params[in] NvBool writeFc + * Indicates of Fast Clear Bits should be written. + * @params[in] NvU32 *compCacheLine; + * Buffer to receive Comp Cache Line data. + * @params[in] NvU64 dataPhysicalStart; + * Start Address of Data + * @params[in] NvU64 surfaceOffset; + * Offset in the surface + * @params[in] NvU32 comptagLine; + * Compression Tag Line Number + * @params[in] NvU32 ROPTile_offset; + * Offset in the surface of the ROP tile. + * @params[in] NvBool upper64KBCompbitSel; + * Selects Upper or Lower 64K + * @params[in] NvP64 derivedParams + * Actually a CompBitDerivedParams structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS (0x2080132fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2F" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS_PARAMS { + NvU32 fcbits; + NvU32 compbits; + NvBool writeFc; + NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8); + NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8); + NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8); + NvU32 comptagLine; + NvU32 ROPTile_offset; + NvBool upper64KBCompbitSel; + NV_DECLARE_ALIGNED(NvP64 derivedParams, 8); +} NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS < Deprecated > + * + * The PS (Performance Path, or Optimized path, or Per Slice version) + * of ReadCompCacheLine. + * + * @paramsNvU32 *compCacheLine; + * Buffer for Comp Cache Line Read + * @paramsNvU32 comptagLine; + * Comp Tag Line Number to read + * @paramsNvU32 partition; + * FB Partition of the desired Comp Cache Line + * @paramsNvU32 slice; + * Slice of the desired Comp Cache Line + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS (0x20801330U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x30" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS_PARAMS { + NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8); + NvU32 comptagLine; + NvU32 partition; + NvU32 slice; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS < Deprecated > + * + * The PS (Performance Path, or Optimized path, or Per Slice version) + * of WriteCompCacheLine. + * + * @params[in] NvU32 *compCacheLine; + * Buffer for Comp Cache Line to Write + * @params[in] NvU32 comptagLine; + * Comp Tag Line Number to Write + * @params[in] NvU32 partition; + * FB Partition of the desired Comp Cache Line + * @params[in] NvU32 slice; + * Slice of the desired Comp Cache Line + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS (0x20801331U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x31" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS_PARAMS { + NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8); + NvU32 comptagLine; + NvU32 partition; + NvU32 slice; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS < Deprecated > + * + * Used by PS (Performance Path, or Optimized path, or Per Slice version) + * to retrieve upper and lower Address of the CompCacheLine. + * + * @params[out] NvU64 *minCPUAddress; + * Minimum (lower bound) of the ComCacheLine. + * @params[out] NvU64 *minCPUAddress; + * Minimum (lower bound) of the ComCacheLine. + * @params[in] NvU32 comptagLine; + * CompTagLine to fetch the bounds of. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS (0x20801332U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x32" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 *minCPUAddress, 8); + NV_DECLARE_ALIGNED(NvU64 *maxCPUAddress, 8); + NvU32 comptagLine; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET < Deprecated > + * + * Used by PS (Performance Path, or Optimized path, or Per Slice version) + * to retrieve partition, slice and ROP Tile Offset of the passed in + * surface location. + * + * @params[out] NvU64 *part; + * Partition in which the target part of the surface resides. + * @params[out] NvU64 *slice; + * Slice in which the target part of the surface resides. + * @params[out] NvU64 *ropTileoffset; + * Offset to the start of the ROP Tile in which the target part of + * the surface resides. + * @params[in] NvU64 *dataPhysicalStart; + * Start address of data for which part/slice/offset is desired. + * @params[in] NvU64 surfaceOffset; + * Byte offset of data for which part/slice/offset is desired. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET (0x20801333U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x33" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET_PARAMS { + NV_DECLARE_ALIGNED(NvU64 *part, 8); + NV_DECLARE_ALIGNED(NvU64 *slice, 8); + NV_DECLARE_ALIGNED(NvU64 *ropTileoffset, 8); + NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8); + NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8); +} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS < Deprecated > + * + * Used by PS (Performance Path, or Optimized path, or Per Slice version) + * to create a CompBitCopy::CompBitDerivedParams object + * + * @params[out] NvP64 derivedParams + * Actually a CompBitDerivedParams structure. + * @params[in] NvU32 comptagLine; + * Compression Tag Line Number + * @params[in] NvU32 ROPTile_offset; + * Offset in the surface of the ROP tile. + * @params[in] NvBool upper64KBCompbitSel; + * Selects Upper or Lower 64K + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS (0x20801334U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x34" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS_PARAMS { + NV_DECLARE_ALIGNED(NvP64 derivedParams, 8); + NvU32 comptagLine; + NvBool upper64KBCompbitSel; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1 < Deprecated > + * + * Used by MODS (and possibly other clients) to have compbit code write + * write directly to BAR1, rather than a intermediate buffer. + * + * @params[in] NvBool bForceBar1; + * Enables or disables direct writes to BAR1. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1 (0x20801335U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x35" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS { + NvBool bForceBar1; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_GET_AMAP_CONF + * + * Fills in fields of a structure of class ConfParamsV1, which is used for + * swizzling compression bits in the compression backing store. + * The caller is expected to have the appropriate headers for class ConfParamsV1. + * + * @params[in|out] void *pAmapConfParms + * Opaque pointer to structure of values for ConfParamsV1 + * @params[in|out] void *pCbcSwizzleParms + * Opaque pointer to structure of values for CbcSwizzleParamsV1 + * + * Possible status values returned are: + * NV_OK NV_ERR_NOT_SUPPORTED + * + * pCbcSwizzleParams will be filled in with certain parameters from + * @CbcSwizzleParamsV1. However, the caller is responsible for making sure + * all parameters are filled in before using it. + */ +#define NV2080_CTRL_CMD_FB_GET_AMAP_CONF (0x20801336U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS_MESSAGE_ID (0x36U) + +typedef struct NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pAmapConfParams, 8); + NV_DECLARE_ALIGNED(NvP64 pCbcSwizzleParams, 8); +} NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_CBC_OP + * + * Provides a way for clients to request a CBC Operation + * + * @params[in] CTRL_CMD_FB_CBC_OP fbCBCOp + * CBC Operation requested. + * Valid Values: + * CTRL_CMD_FB_CBC_OP_CLEAN + * CTRL_CMD_FB_CBC_OP_INVALIDATE + * + * Possible status values returned are: + * NV_OK NV_ERR_NOT_SUPPORTED NV_ERR_INVALID_ARGUMENT NV_ERR_TIMEOUT + */ +#define NV2080_CTRL_CMD_FB_CBC_OP (0x20801337U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_CBC_OP_PARAMS_MESSAGE_ID" */ + +/*! + * Permitted CBC Operations + */ +typedef enum CTRL_CMD_FB_CBC_OP { + CTRL_CMD_FB_CBC_OP_CLEAN = 0, + CTRL_CMD_FB_CBC_OP_INVALIDATE = 1, +} CTRL_CMD_FB_CBC_OP; + +#define NV2080_CTRL_CMD_FB_CBC_OP_PARAMS_MESSAGE_ID (0x37U) + +typedef struct NV2080_CTRL_CMD_FB_CBC_OP_PARAMS { + CTRL_CMD_FB_CBC_OP fbCBCOp; +} NV2080_CTRL_CMD_FB_CBC_OP_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_GET_CTAGS_FOR_CBC_EVICTION + * + * The call will fetch the compression tags reserved for CBC eviction. + * + * Each comptag will correspond to a unique compression cacheline. The usage of + * these comptags is to evict the CBC by making accesses to a dummy compressed page, + * thereby evicting each CBC line. + * + * @param [in][out] NvU32 pCompTags + * Array of reserved compression tags of size @ref NV2080_MAX_CTAGS_FOR_CBC_EVICTION + * @param [out] numCompTags + * Number of entries returned in @ref pCompTags + * + * @returns + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_OUT_OF_RANGE + * NV_ERR_INVALID_PARAMETER + */ +#define NV2080_CTRL_CMD_FB_GET_CTAGS_FOR_CBC_EVICTION (0x20801338U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS_MESSAGE_ID" */ + +/*! + * Max size of @ref NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS::pCompTags + * Arbitrary, but sufficiently large number. Should be checked against CBC size. + */ +#define NV2080_MAX_CTAGS_FOR_CBC_EVICTION 0x7FU + + +#define NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS_MESSAGE_ID (0x38U) + +typedef struct NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS { + NvU32 pCompTags[NV2080_MAX_CTAGS_FOR_CBC_EVICTION]; + NvU32 numCompTags; +} NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE + * + * This Call will allocate compression tag + * + * @params[in] NvU32 attr + * Stores the information: + * 1. NVOS32_ATTR_COMPR_REQUIRED or not + * 2. NVOS32_ATTR_PAGE_SIZE + * @params[in] NvU32 attr2 + * Determine whether to allocate + * an entire cache line or allocate by size + * @params[in] NvU32 size + * Specify the size of allocation, in pages not bytes + * @params[in] NvU32 ctagOffset + * Determine the offset usage of the allocation + * @params[out] NvU32 hwResId + * Stores the result of the allocation + * @params[out] NvU32 RetcompTagLineMin + * The resulting min Ctag Number from the allocation + * @params[out] NvU32 RetcompTagLineMax + * The resulting max Ctag Number from the allocation + * @returns + * NV_OK + * NV_ERR_INSUFFICIENT_RESOURCES + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ + +#define NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE (0x20801339U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS_MESSAGE_ID (0x39U) + +typedef struct NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS { + NvU32 attr; + NvU32 attr2; + NvU32 size; + NvU32 ctagOffset; + NvU32 hwResId; + NvU32 retCompTagLineMin; + NvU32 retCompTagLineMax; +} NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_FREE_TILE + * + * This control call is used to release tile back to the free pool + * + * @params[in] NvU32 hwResId + * Stores the information of a previous allocation + * @returns + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ + +#define NV2080_CTRL_CMD_FB_FREE_TILE (0x2080133aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS_MESSAGE_ID (0x3AU) + +typedef struct NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS { + NvU32 hwResId; +} NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS; + + +/* + * NV2080_CTRL_CMD_FB_SETUP_VPR_REGION + * + * This control command is used to request vpr region setup + * + * requestType + * NV2080_CTRL_CMD_FB_SET_VPR: Request to setup VPR + * + * requestParams : struct VPR_REQUEST_PARAMS + * It contains the VPR region request details like, + * startAddr : FB offset from which we need to setup VPR + * size : required size of the region + * + * statusParams : struct VPR_STATUS_PARAMS + * This struct stores the output of requested VPR region + * status : Whether the request was successful + * + * NV2080_CTRL_CMD_FB_VPR_ERROR_CODE : + * NV2080_CTRL_CMD_FB_VPR_ERROR_GENERIC : Some unknown error occurred + * NV2080_CTRL_CMD_FB_VPR_ERROR_INVALID_CLIENT_REQUEST : Request was invalid + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_SETUP_VPR_REGION (0x2080133bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE { + NV2080_CTRL_CMD_FB_SET_VPR = 0, +} NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE; + +typedef enum NV2080_CTRL_CMD_FB_VPR_ERROR_CODE { + NV2080_CTRL_CMD_FB_VPR_ERROR_GENERIC = 0, + NV2080_CTRL_CMD_FB_VPR_ERROR_INVALID_CLIENT_REQUEST = 1, +} NV2080_CTRL_CMD_FB_VPR_ERROR_CODE; + +typedef struct VPR_REQUEST_PARAMS { + NvU32 startAddr; + NvU32 size; +} VPR_REQUEST_PARAMS; + +typedef struct VPR_STATUS_PARAMS { + NvU32 status; +} VPR_STATUS_PARAMS; + +#define NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS_MESSAGE_ID (0x3BU) + +typedef struct NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS { + NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE requestType; + VPR_REQUEST_PARAMS requestParams; + VPR_STATUS_PARAMS statusParams; +} NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS; +typedef struct NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS *PNV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_GET_CLI_MANAGED_OFFLINED_PAGES + * + * This command returns the list of offlined video memory page addresses in the + * region managed by Client + * + * offlinedPages + * This output parameter is an array of video memory physical page numbers that + * are offlined. This array can hold a maximum of NV2080_CTRL_FB_ + * OFFLINED_PAGES_MAX_PAGES addresses. + * pageSize + * This output parameter contains the size of the page that is offlined. + * validEntries + * This output parameter specifies the number of valid entries in the + * offlined array. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_FB_GET_CLI_MANAGED_OFFLINED_PAGES (0x2080133cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS_MESSAGE_ID (0x3CU) + +typedef struct NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS { + NvU32 offlinedPages[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES]; // A 32B can hold enough. + NvU32 pageSize; + NvU32 validEntries; +} NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO + * + * This command returns parameters required to initialize compbit copy object + * used by address mapping library + * + * defaultPageSize + * Page size used by @ref CompBitCopy methods + * comptagsPerCacheLine + * Number of compression tags in a single compression cache line. + * unpackedComptagLinesPerCacheLine; + * From hw (not adjusted for CompBits code) Number of compression tags + * in a single compression cache line. + * compCacheLineSizePerLTC; + * Size of compression cache line per L2 slice. Size in Bytes. + * unpackedCompCacheLineSizePerLTC; + * From hw (not adjusted for CompBits code) size of compression + * cache line per L2 slice. Size in Bytes + * slicesPerLTC; + * Number of L2 slices per L2 cache. + * numActiveLTCs; + * Number of active L2 caches. (Not floorswept) + * familyName; + * Family name for the GPU. + * chipName; + * Chip name for the GPU. + * bitsPerRAMEntry; + * Bits per RAM entry. (Need better doc) + * ramBankWidth; + * Width of RAM bank. (Need better doc) + * bitsPerComptagLine; + * Number of bits per compression tag line. + * ramEntriesPerCompCacheLine; + * Number of RAM entries spanned by 1 compression cache line. + * comptagLineSize; + * Size of compression tag line, in Bytes. + * + * Possible status values returned are: + * NV_OK + */ + +#define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO (0x2080133dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS_MESSAGE_ID (0x3DU) + +typedef struct NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS { + NvU32 defaultPageSize; + NvU32 comptagsPerCacheLine; + NvU32 unpackedComptagLinesPerCacheLine; + NvU32 compCacheLineSizePerLTC; + NvU32 unpackedCompCacheLineSizePerLTC; + NvU32 slicesPerLTC; + NvU32 numActiveLTCs; + NvU32 familyName; + NvU32 chipName; + NvU32 bitsPerRAMEntry; + NvU32 ramBankWidth; + NvU32 bitsPerComptagLine; + NvU32 ramEntriesPerCompCacheLine; + NvU32 comptagLineSize; +} NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_SET_RRD + * + * Sets the row-to-row delay on the GPU's FB + * + * Possible status values returned are: + * NV_OK + * Any error code + */ +#define NV2080_CTRL_CMD_FB_SET_RRD (0x2080133eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_RRD_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_SET_RRD_RESET_VALUE (~((NvU32)0)) +#define NV2080_CTRL_FB_SET_RRD_PARAMS_MESSAGE_ID (0x3EU) + +typedef struct NV2080_CTRL_FB_SET_RRD_PARAMS { + NvU32 rrd; +} NV2080_CTRL_FB_SET_RRD_PARAMS; + +/* + * NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS + * + * This is not a control call of it's own, but there are common definitions for + * the two NV2080_CTRL_CMD_FB_SET_READ/WRITE_LIMIT control calls. + */ +typedef struct NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS { + NvU8 limit; +} NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS; +#define NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE (0xffU) + +/* + * NV2080_CTRL_CMD_FB_SET_READ_LIMIT + * + * Sets the READ_LIMIT to be used in the NV_PFB_FBPA_DIR_ARB_CFG0 register + * + * limit + * The limit value to use + * + * Possible status values returned are: + * NV_OK + * Any error code + */ +#define NV2080_CTRL_CMD_FB_SET_READ_LIMIT (0x2080133fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_SET_READ_LIMIT_RESET_VALUE NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE +#define NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS_MESSAGE_ID (0x3FU) + +typedef NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_SET_WRITE_LIMIT + * + * Sets the WRITE_LIMIT to be used in the NV_PFB_FBPA_DIR_ARB_CFG0 register + * + * limit + * The limit value to us + * + * Possible status values returned are: + * NV_OK + * Any error code + */ +#define NV2080_CTRL_CMD_FB_SET_WRITE_LIMIT (0x20801340U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_SET_WRITE_LIMIT_RESET_VALUE NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE +#define NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS_MESSAGE_ID (0x40U) + +typedef NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_PATCH_PBR_FOR_MINING + * + * Patches some VBIOS values related to PBR to better suit mining applications + * + * bEnable + * Set the mining-specific values or reset to the original values + * + * Possible status values returned are: + * NV_OK + * Any error code + */ +#define NV2080_CTRL_CMD_FB_PATCH_PBR_FOR_MINING (0x20801341U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS_MESSAGE_ID (0x41U) + +typedef struct NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS { + NvBool bEnable; +} NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT + * + * Get memory alignment. Replacement for NVOS32_FUNCTION_GET_MEM_ALIGNMENT + */ +#define NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT (0x20801342U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS (4U) +#define NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID (0x42U) + +typedef struct NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS { + NvU32 alignType; // Input + NvU32 alignAttr; + NvU32 alignInputFlags; + NvU32 alignHead; + NV_DECLARE_ALIGNED(NvU64 alignSize, 8); + NvU32 alignHeight; + NvU32 alignWidth; + NvU32 alignPitch; + NvU32 alignPad; + NvU32 alignMask; + NvU32 alignOutputFlags[NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS]; + NvU32 alignBank[NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS]; + NvU32 alignKind; + NvU32 alignAdjust; // Output -- If non-zero the amount we need to adjust the offset + NvU32 alignAttr2; +} NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_GET_CBC_BASEADDR + * + * Get the CBC Base physical address + * This control call is required by error containment tests + * NV2080_CTRL_CMD_FB_GET_AMAP_CONF can also return CBC base address + * but it requires kernel privilege, and it not callalble from SRT test + * + * @params[out] NvU64 cbcBaseAddr + * Base physical address for CBC data. + * + * Possible status values returned are: + * NV_OK NV_ERR_NOT_SUPPORTED + * + */ +#define NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR (0x20801343U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS_MESSAGE_ID (0x43U) + +typedef struct NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS { + NvU32 cbcBaseAddress; + NvU32 compCacheLineSize; + NV_DECLARE_ALIGNED(NvU64 backingStoreStartPA, 8); + NV_DECLARE_ALIGNED(NvU64 backingStoreAllocPA, 8); + NvU32 backingStoreChunkOverfetch; +} NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS; + +#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING 0:0 +#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE 0U +#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE 1U + + + +typedef struct NV2080_CTRL_FB_REMAP_ENTRY { + NvU32 remapRegVal; + NvU32 timestamp; + NvU8 fbpa; + NvU8 sublocation; + NvU8 source; + NvU8 flags; +} NV2080_CTRL_FB_REMAP_ENTRY; + +/* valid values for source */ + + +#define NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_SBE_FIELD (0x00000002U) +#define NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_DBE_FIELD (0x00000003U) + +#define NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS (0x00000200U) + +/* + * NV2080_CTRL_CMD_FB_GET_REMAPPED_ROWS + * + * This command returns the list of remapped rows stored in the Inforom. + * + * entryCount + * This output parameter specifies the number of remapped rows + * flags + * This output parameter contains info on whether or not there are pending + * remappings and whether or not a remapping failed + * entries + * This output parameter is an array of NV2080_CTRL_FB_REMAP_ENTRY + * containing inforomation on the remapping that occurred. This array can + * hold a maximum of NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_POINTER + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_GET_REMAPPED_ROWS (0x20801344U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING \ + NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING +#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_FALSE NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE +#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_TRUE NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE +#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE 1:1 +#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_FALSE 0U +#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_TRUE 1U + +#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS_MESSAGE_ID (0x44U) + +typedef struct NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS { + NvU32 entryCount; + NvU8 flags; + NV2080_CTRL_FB_REMAP_ENTRY entries[NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS]; +} NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS; + +// Max size of the queryParams in Bytes, so that the NV2080_CTRL_FB_FS_INFO_QUERY struct is still 32B +#define NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE 24U + +/*! + * Structure holding the out params for NV2080_CTRL_FB_FS_INFO_INVALID_QUERY. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS { + // Unused param, will ensure the size of NV2080_CTRL_FB_FS_INFO_QUERY struct to be 32B + NvU8 data[NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE]; +} NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_FBP_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS { + /*! + * [IN]: swizzId + * PartitionID associated with a created smc partition. Currently used only for a + * device monitoring client to get the physical values of the FB. The client needs to pass + * 'NV2080_CTRL_GPU_PARTITION_ID_INVALID' explicitly if it wants RM to ignore the swizzId. + * RM will consider this request similar to a legacy case. + * The client's subscription is used only as a capability check and not as an input swizzId. + */ + NvU32 swizzId; + /*! + * [OUT]: physical/local fbp mask. + */ + NV_DECLARE_ALIGNED(NvU64 fbpEnMask, 8); +} NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_LTC_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS { + /*! + * [IN]: physical/local FB partition index. + */ + NvU32 fbpIndex; + /*! + * [OUT]: physical/local ltc mask. + */ + NvU32 ltcEnMask; +} NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_LTS_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS { + /*! + * [IN]: physical/local FB partition index. + */ + NvU32 fbpIndex; + /*! + * [OUT]: physical/local lts mask. + * Note that lts bits are flattened out for all ltc with in a fbp. + */ + NvU32 ltsEnMask; +} NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_FBPA_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS { + /*! + * [IN]: physical/local FB partition index. + */ + NvU32 fbpIndex; + /*! + * [OUT]: physical/local FBPA mask. + */ + NvU32 fbpaEnMask; +} NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS { + /*! + * [IN]: physical/local FB partition index. + */ + NvU32 fbpIndex; + /*! + * [OUT]: physical/local FBPA-SubPartition mask. + */ + NvU32 fbpaSubpEnMask; +} NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP + */ +typedef struct NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS { + /*! + * [IN]: physical/local FB partition index. + */ + NvU32 fbpIndex; + /*! + * [OUT]: Logical/local FBP index + */ + NvU32 fbpLogicalIndex; +} NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_ROP_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS { + /*! + * [IN]: physical/local FB partition index. + */ + NvU32 fbpIndex; + /*! + * [OUT]: physical/local ROP mask. + */ + NvU32 ropEnMask; +} NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS { + /*! + * [IN]: Physical FB partition index. + */ + NvU32 fbpIndex; + /*! + * [IN]: swizzId + * PartitionID associated with a created smc partition. + */ + NvU32 swizzId; + /*! + * [OUT]: physical ltc mask. + */ + NvU32 ltcEnMask; +} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS { + /*! + * [IN]: Physical FB partition index. + */ + NvU32 fbpIndex; + /*! + * [IN]: swizzId + * PartitionID associated with a created smc partition. + */ + NvU32 swizzId; + /*! + * [OUT]: physical lts mask. + */ + NvU32 ltsEnMask; +} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS { + /*! + * [IN]: Physical FB partition index. + */ + NvU32 fbpIndex; + /*! + * [IN]: swizzId + * PartitionID associated with a created smc partition. + */ + NvU32 swizzId; + /*! + * [OUT]: physical fbpa mask. + */ + NvU32 fbpaEnMask; +} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS { + /*! + * [IN]: Physical FB partition index. + */ + NvU32 fbpIndex; + /*! + * [IN]: swizzId + * PartitionID associated with a created smc partition. + */ + NvU32 swizzId; + /*! + * [OUT]: physical rop mask. + */ + NvU32 ropEnMask; +} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS { + /*! + * [IN]: Physical FB partition index. + */ + NvU32 fbpIndex; + /*! + * [IN]: swizzId + * PartitionID associated with a created smc partition. Currently used only for a + * device monitoring client to get the physical values of the FB. The client needs to pass + * 'NV2080_CTRL_GPU_PARTITION_ID_INVALID' explicitly if it wants RM to ignore the swizzId. + * RM will consider this request similar to a legacy case. + * The client's subscription is used only as a capability check and not as an input swizzId. + */ + NvU32 swizzId; + /*! + * [OUT]: physical FBPA_SubPartition mask associated with requested partition. + */ + NV_DECLARE_ALIGNED(NvU64 fbpaSubpEnMask, 8); +} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS; + +// Possible values for queryType +#define NV2080_CTRL_FB_FS_INFO_INVALID_QUERY 0x0U +#define NV2080_CTRL_FB_FS_INFO_FBP_MASK 0x1U +#define NV2080_CTRL_FB_FS_INFO_LTC_MASK 0x2U +#define NV2080_CTRL_FB_FS_INFO_LTS_MASK 0x3U +#define NV2080_CTRL_FB_FS_INFO_FBPA_MASK 0x4U +#define NV2080_CTRL_FB_FS_INFO_ROP_MASK 0x5U +#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK 0x6U +#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK 0x7U +#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK 0x8U +#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK 0x9U +#define NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK 0xAU +#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK 0xBU +#define NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP 0xCU + +typedef struct NV2080_CTRL_FB_FS_INFO_QUERY { + NvU16 queryType; + NvU8 reserved[2]; + NvU32 status; + union { + NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS inv; + NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS fbp, 8); + NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS ltc; + NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS lts; + NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS fbpa; + NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS rop; + NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS dmLtc; + NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS dmLts; + NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS dmFbpa; + NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS dmRop; + NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS dmFbpaSubp, 8); + NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS fbpaSubp; + NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS fbpLogicalMap; + } queryParams; +} NV2080_CTRL_FB_FS_INFO_QUERY; + +// Max number of queries that can be batched in a single call to NV2080_CTRL_CMD_FB_GET_FS_INFO +#define NV2080_CTRL_FB_FS_INFO_MAX_QUERIES 96U + +#define NV2080_CTRL_FB_GET_FS_INFO_PARAMS_MESSAGE_ID (0x46U) + +typedef struct NV2080_CTRL_FB_GET_FS_INFO_PARAMS { + NvU16 numQueries; + NvU8 reserved[6]; + NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_QUERY queries[NV2080_CTRL_FB_FS_INFO_MAX_QUERIES], 8); +} NV2080_CTRL_FB_GET_FS_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_GET_FS_INFO + * + * This control call returns the fb engine information for a partition/GPU. + * Supports an interface so that the caller can issue multiple queries by batching them + * in a single call. Returns the first error it encounters. + * + * numQueries[IN] + * - Specifies the number of valid queries. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_GET_FS_INFO (0x20801346U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_FS_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_HISTOGRAM_IDX_NO_REMAPPED_ROWS (0x0U) +#define NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAPPED_ROW (0x1U) +#define NV2080_CTRL_FB_HISTOGRAM_IDX_MIXED_REMAPPED_REMAINING_ROWS (0x2U) +#define NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAINING_ROW (0x3U) +#define NV2080_CTRL_FB_HISTOGRAM_IDX_MAX_REMAPPED_ROWS (0x4U) + +#define NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS_MESSAGE_ID (0x47U) + +typedef struct NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS { + NvU32 histogram[5]; +} NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM + * + * This control call returns stats on the number of banks that have a certain + * number of rows remapped in the bank. Specifically the number of banks that + * have 0, 1, 2 through (max-2), max-1 and max number of rows remapped in the + * bank. Values will be returned in an array. + * + * Index values are: + * + * NV2080_CTRL_FB_HISTOGRAM_IDX_NO_REMAPPED_ROWS + * Number of banks with zero rows remapped + NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAPPED_ROW + * Number of banks with one row remapped + NV2080_CTRL_FB_HISTOGRAM_IDX_MIXED_REMAPPED_REMAINING_ROWS + * Number of banks with 2 through (max-2) rows remapped + NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAINING_ROW + * Number of banks with (max-1) rows remapped + NV2080_CTRL_FB_HISTOGRAM_IDX_MAX_REMAPPED_ROWS + * Number of banks with max rows remapped + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM (0x20801347U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_FB_GET_DYNAMICALLY_BLACKLISTED_PAGES + * + * This command returns the list of dynamically blacklisted video memory page addresses + * after last driver load. + * + * blackList + * This output parameter is an array of NV2080_CTRL_FB_DYNAMIC_BLACKLIST_ADDRESS_INFO + * This array can hold a maximum of NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES. + * validEntries + * This output parameter specifies the number of valid entries in the + * blackList array. + * baseIndex + * With the limit of up to 512 blacklisted pages, the size of this array + * exceeds the rpc buffer limit. This control call will collect the data + * in multiple passes. This parameter indicates the start index of the + * data to be passed back to the caller + * This cannot be greater than NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES + * bMore + * This parameter indicates whether there are more valid elements to be + * fetched. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_FB_GET_DYNAMIC_OFFLINED_PAGES (0x20801348U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */ + +/* Maximum pages that can be dynamically blacklisted */ +#define NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES 512U + +/* + * Maximum entries that can be sent in a single pass of + * NV2080_CTRL_CMD_FB_GET_DYNAMIC_OFFLINED_PAGES + */ +#define NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES 64U + +/** + * NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO + * pageNumber + * This output parameter specifies the dynamically blacklisted page number. + * source + * The reason for the page to be retired. Valid values for + * this parameter include: + * NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_INVALID + * Invalid source. + * NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE + * Page retired by dynamic page retirement due to a double bit + * error seen. + */ +typedef struct NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO { + NV_DECLARE_ALIGNED(NvU64 pageNumber, 8); + NvU8 source; +} NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO; + +#define NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_MESSAGE_ID (0x48U) + +typedef struct NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO offlined[NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES], 8); + NvU32 validEntries; + NvU32 baseIndex; + NvBool bMore; +} NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS; + +/* valid values for source */ + +#define NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_INVALID (0x00000000U) +#define NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_DPR_DBE (0x00000001U) + +/* + * NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO + * + * This control command is used by clients to query information pertaining to client allocations. + * + * + * @params [IN/OUT] NvU64 allocCount: + * Client specifies the allocation count that it received using the + * previous NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO control call. + * RM will get the total number of allocations known by RM and fill + * allocCount with it. + * + * @params [IN] NvP64 pAllocInfo: + * Pointer to the buffer allocated by client of size NV2080_CTRL_CMD_FB_ALLOCATION_INFO * + * allocCount. RM returns the info pertaining to each of the contiguous client + * allocation chunks in pAllocInfo. The format of the allocation information is given by + * NV2080_CTRL_CMD_FB_ALLOCATION_INFO. The client has to sort the returned information if + * it wants to retain the legacy behavior of SORTED BY OFFSET. Information is only returned + * if and only if allocCount[IN]>=allocCount[OUT] and clientCount[IN]>=clientCount[OUT]. + * + * @params [IN/OUT] NvP64 clientCount: + * Client specifies the client count that it received using the + * previous NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO control call. + * RM will get the total number of clients that have allocations with RM + * and fill clientCount with it. + * + * @params [IN] NvP64 pClientInfo: + * Pointer to the buffer allocated by client of size NV2080_CTRL_CMD_FB_CLIENT_INFO * + * clientCount. RM returns the info pertaining to each of the clients that have allocations + * known about by RM in pClientInfo. The format of the allocation information is given by + * NV2080_CTRL_CMD_FB_CLIENT_INFO. Information is only returned if and only if + * allocCount[IN]>=allocCount[OUT] and clientCount[IN]>=clientCount[OUT]. + * + * @returns Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_POINTER + * NV_ERR_NO_MEMORY + * + * @Usage: All privileged RM clients for debugging only. Initially, call this with allocCount = + * clientCount = 0 to get client count, and then call again with allocated memory and sizes. + * Client can repeat with the new count-sized allocations until a maximum try count is + * reached or client is out of memory. + */ + +#define NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO (0x20801349U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS_MESSAGE_ID" */ + +/* + * These work with the FLD_SET_REF_NUM and FLD_TEST_REF macros and describe the 'flags' member + * of the NV2080_CTRL_CMD_FB_ALLOCATION_INFO struct. + */ + +// Address space of the allocation +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE 4:0 +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_SYSMEM 0U +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_VIDMEM 1U + +// Whether the allocation is shared +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED 5:5 +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_FALSE 0U +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_TRUE 1U + +// Whether this client owns this allocation +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER 6:6 +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_FALSE 0U +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_TRUE 1U + +typedef struct NV2080_CTRL_CMD_FB_ALLOCATION_INFO { + NvU32 client; /* [OUT] Identifies the client that made or shares the allocation (index into pClientInfo)*/ + NvU32 flags; /* [OUT] Flags associated with the allocation (see previous defines) */ + NV_DECLARE_ALIGNED(NvU64 beginAddr, 8); /* [OUT] Starting physical address of the chunk */ + NV_DECLARE_ALIGNED(NvU64 size, 8); /* [OUT] Size of the allocated contiguous chunk in bytes */ +} NV2080_CTRL_CMD_FB_ALLOCATION_INFO; + +typedef struct NV2080_CTRL_CMD_FB_CLIENT_INFO { + NvHandle handle; /* [OUT] Handle of the client that made or shares the allocation */ + NvU32 pid; /* [OUT] PID of the client that made or shares the allocation */ + + /* For the definition of the subprocessID and subprocessName params, see NV0000_CTRL_CMD_SET_SUB_PROCESS_ID */ + NvU32 subProcessID; /* [OUT] Subprocess ID of the client that made or shares the allocation */ + char subProcessName[NV_PROC_NAME_MAX_LENGTH]; /* [OUT] Subprocess Name of the client that made or shares the allocation */ +} NV2080_CTRL_CMD_FB_CLIENT_INFO; + +#define NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS_MESSAGE_ID (0x49U) + +typedef struct NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 allocCount, 8); + NV_DECLARE_ALIGNED(NvP64 pAllocInfo, 8); + NV_DECLARE_ALIGNED(NvU64 clientCount, 8); + NV_DECLARE_ALIGNED(NvP64 pClientInfo, 8); +} NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS + * + * This control command is used by clients to update the NUMA status. + * + * @params [IN] NvBool bOnline: + * + * @returns Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * + */ +#define NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS (0x20801350U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS_MESSAGE_ID (0x50U) + +typedef struct NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS { + NvBool bOnline; +} NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_GET_NUMA_INFO + * + * This control command is used by clients to get per-subdevice NUMA memory + * information as assigned by the system. + * + * numaNodeId[OUT] + * - Specifies the NUMA node ID. + * + * numaMemAddr[OUT] + * - Specifies the NUMA memory address. + * + * numaMemSize[OUT] + * - Specifies the NUMA memory size. + * + * numaOfflineAddressesCount[IN/OUT] + * - If non-zero, then it specifies the maximum number of entries in + * numaOfflineAddresses[] for which the information is required. + * It will be updated with the actual number of entries present in + * the numaOfflineAddresses[]. + * + * numaOfflineAddresses[OUT] + * - If numaOfflineAddressesCount is non-zero, it contains the addresses + * of offline pages in the NUMA region. + * + * @returns Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_GET_NUMA_INFO (0x20801351U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_NUMA_INFO_MAX_OFFLINE_ADDRESSES 64U + +#define NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS_MESSAGE_ID (0x51U) + +typedef struct NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS { + NvS32 numaNodeId; + NV_DECLARE_ALIGNED(NvU64 numaMemAddr, 8); + NV_DECLARE_ALIGNED(NvU64 numaMemSize, 8); + NvU32 numaOfflineAddressesCount; + NV_DECLARE_ALIGNED(NvU64 numaOfflineAddresses[NV2080_CTRL_FB_NUMA_INFO_MAX_OFFLINE_ADDRESSES], 8); +} NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS; + +/* _ctrl2080fb_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h new file mode 100644 index 0000000..b8341aa --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h @@ -0,0 +1,791 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080fifo.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* + * NV2080_CTRL_CMD_SET_GPFIFO + * + * This command set the GPFIFO offset and number of entries for a channel + * after it has been allocated. The channel must be idle and not pending, + * otherwise ERROR_IN_USE will be returned. + * + * hChannel + * The handle to the channel. + * base + * The base of the GPFIFO in the channel ctxdma. + * numEntries + * The number of entries in the GPFIFO. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_CHANNEL + * NV_ERR_STATE_IN_USE + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV2080_CTRL_CMD_SET_GPFIFO (0x20801102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_SET_GPFIFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_SET_GPFIFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_CMD_SET_GPFIFO_PARAMS { + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 base, 8); + NvU32 numEntries; +} NV2080_CTRL_CMD_SET_GPFIFO_PARAMS; + +/* + * NV2080_CTRL_FIFO_BIND_CHANNEL + * + * This structure is used to describe a channel that is to have + * it's bindable engines bound to those of other channels. + * + * hClient + * This structure member contains the handle of the client object + * that owns the channel object specified by hChannel. + * + * hChannel + * This structure member contains the channel handle of the channel + * object. + */ + +typedef struct NV2080_CTRL_FIFO_BIND_CHANNEL { + NvHandle hClient; + NvHandle hChannel; +} NV2080_CTRL_FIFO_BIND_CHANNEL; + +/* + * NV2080_CTRL_CMD_FIFO_BIND_ENGINES + * + * This control call is now deprecated. + * This command can be used to bind different video engines on G8X from separate + * channels together for operations such as idling. The set of bindable engines + * includes the NV2080_ENGINE_TYPE_BSP, NV2080_ENGINE_TYPE_VP and + * NV2080_ENGINE_TYPE_PPP engines. + * + * bindChannelCount + * This parameter specifies the number of channels to bind together. This + * parameter cannot exceed NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS. + * + * bindChannels + * The parameter specifies the array of channels to bind together. The first + * bindChannelCount entries are used in the bind channel operation. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_CHANNEL + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS (16) + +#define NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS { + NvU32 bindChannelCount; + NV2080_CTRL_FIFO_BIND_CHANNEL bindChannels[NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS]; +} NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS; + +#define NV2080_CTRL_CMD_FIFO_BIND_ENGINES (0x20801103) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES + * + * This command is used for a client to setup specialized custom operational + * properties that may be specific to an environment, or properties that + * should be set generally but are not for reasons of backward compatibility + * with previous chip generations + * + * flags + * This field specifies the operational properties to be applied + * + * Possible return status values returned are + * NV_OK + * NV_ERR_INVALID_CHANNEL + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES (0x20801104) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS { + NvU32 flags; +} NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS; + +#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE 0:0 +#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_FALSE (0x00000000) +#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_TRUE (0x00000001) + +/* + * NV2080_CTRL_CMD_FIFO_GET_PHYSICAL_CHANNEL_COUNT + * + * This command returns the maximum number of physical channels available for + * allocation on the current GPU. This may be less than or equal to the total + * number of channels supported by the current hardware. + * + * physChannelCount + * This output parameter contains the maximum physical channel count. + * + * physChannelCountInUse + * This output parameter contains the number of physical channels in use + * + * Possible return status values returned are + * NV_OK + * + */ +#define NV2080_CTRL_CMD_FIFO_GET_PHYSICAL_CHANNEL_COUNT (0x20801108) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS { + NvU32 physChannelCount; + NvU32 physChannelCountInUse; +} NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS; + +/* + * NV2080_CTRL_FIFO_INFO + * + * This structure represents a single 32bit fifo engine value. Clients + * request a particular FIFO engine value by specifying a unique fifo + * information index. + * + * Legal fifo information index values are: + * NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL + * This index can be used to request the amount of instance space + * in kilobytes reserved by the fifo engine. + * NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS + * This index can be used to query the maximum number of channel groups + * that can be allocated on the GPU. + * NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP + * This index can be used to query the maximum number of channels that can + * be allocated in a single channel group. + * NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP + * This index can be used to query the maximum number of subcontext that can + * be allocated in a single channel group. + * NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET + * This index can be used to query the starting offset of the RM + * pre-allocated USERD range in BAR1. This index query is honored only + * on Legacy-vGPU host RM. + * NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE + * This index can be used to query the default timeslice value + * (microseconds) used for a channel or channel group. + * NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE + * This index can be used to query the number of channel groups that are + * already allocated on the GPU. + * NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED + * This index can be used to check if per runlist channel ram is supported, and + * to query the supported number of channels per runlist. + * NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE + * This index can be used to get max channel groups supported per engine/runlist. + * NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE + * This index can be used too get channel groups currently in use per engine/runlist. + * + */ +typedef struct NV2080_CTRL_FIFO_INFO { + NvU32 index; + NvU32 data; +} NV2080_CTRL_FIFO_INFO; + +/* valid fifo info index values */ +#define NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL (0x000000000) +#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS (0x000000001) +#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP (0x000000002) +#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP (0x000000003) +#define NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET (0x000000004) +#define NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE (0x000000005) +#define NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE (0x000000006) +#define NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED (0x000000007) +#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE (0x000000008) +#define NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE (0x000000009) + + +/* set INDEX_MAX to greatest possible index value */ +#define NV2080_CTRL_FIFO_INFO_INDEX_MAX NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE + +#define NV2080_CTRL_FIFO_GET_INFO_USERD_OFFSET_SHIFT (12) + +/* + * NV2080_CTRL_CMD_FIFO_GET_INFO + * + * This command returns fifo engine information for the associated GPU. + * Requests to retrieve fifo information use an array of one or more + * NV2080_CTRL_FIFO_INFO structures. + * + * fifoInfoTblSize + * This field specifies the number of valid entries in the fifoInfoList + * array. This value cannot exceed NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES. + * fifoInfoTbl + * This parameter contains the client's fifo info table into + * which the fifo info values will be transferred by the RM. + * The fifo info table is an array of NV2080_CTRL_FIFO_INFO structures. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FIFO_GET_INFO (0x20801109) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_INFO_PARAMS_MESSAGE_ID" */ + +/* maximum number of NV2080_CTRL_FIFO_INFO entries per request */ +#define NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES (256) + +#define NV2080_CTRL_FIFO_GET_INFO_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_FIFO_GET_INFO_PARAMS { + NvU32 fifoInfoTblSize; + /* + * C form: + * NV2080_CTRL_FIFO_INFO fifoInfoTbl[NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES]; + */ + NV2080_CTRL_FIFO_INFO fifoInfoTbl[NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES]; + NvU32 engineType; +} NV2080_CTRL_FIFO_GET_INFO_PARAMS; + + + +/* + * NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL + * + * This command removes the specified channel from the associated GPU's runlist + * and then initiates RC recovery. If the channel is active it will first be preempted. + * hChannel + * The handle to the channel to be preempted. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_CHANNEL + */ +#define NV2080_CTRL_CMD_FIFO_CHANNEL_PREEMPTIVE_REMOVAL (0x2080110a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS { + NvHandle hChannel; +} NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS + * + * This command will disable or enable scheduling of channels described in the + * list provided. Whether or not the channels are also preempted off the GPU + * can be controlled by bOnlyDisableScheduling. By default channels are preempted + * off the GPU. + * + * bDisable + * This value determines whether to disable or + * enable the set of channels. + * numChannels + * The number of channels to be stopped. + * bOnlyDisableScheduling + * When false and bDisable=NV_TRUE,the call will ensure none of the listed + * channels are running in hardware and will not run until a call with + * bDisable=NV_FALSE is made. When true and bDisable=NV_TRUE, the control + * call will ensure that none of the listed channels can be scheduled on the + * GPU until a call with bDisable=NV_FALSE is made, but will not remove any + * of the listed channels from hardware if they are currently running. When + * bDisable=NV_FALSE this field is ignored. + * bRewindGpPut + * If a channel is being disabled and bRewindGpPut=NV_TRUE, the channel's RAMFC + * will be updated so that GP_PUT is reset to the value of GP_GET. + * hClientList + * An array of NvU32 listing the client handles + * hChannelList + * An array of NvU32 listing the channel handles + * to be stopped. + * pRunlistPreemptEvent + * KEVENT handle for Async HW runlist preemption (unused on preMaxwell) + * When NULL, will revert to synchronous preemption with spinloop + * + * Possible status values returned are: + * NV_OK + * NVOS_INVALID_STATE + */ + +#define NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS (0x2080110b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES (64) + +#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS { + NvBool bDisable; + NvU32 numChannels; + NvBool bOnlyDisableScheduling; + NvBool bRewindGpPut; + NV_DECLARE_ALIGNED(NvP64 pRunlistPreemptEvent, 8); + // C form: NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES] + NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES]; + // C form: NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES] + NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES]; +} NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS; + +#define NV2080_CTRL_FIFO_DISABLE_CHANNEL_FALSE (0x00000000) +#define NV2080_CTRL_FIFO_DISABLE_CHANNEL_TRUE (0x00000001) +#define NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_FALSE (0x00000000) +#define NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_TRUE (0x00000001) + +/* + * NV2080_CTRL_FIFO_MEM_INFO + * + * This structure describes the details of a block of memory. It consists + * of the following fields + * + * aperture + * One of the NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_* values + * base + * Physical base address of the memory + * size + * Size in bytes of the memory +*/ +typedef struct NV2080_CTRL_FIFO_MEM_INFO { + NvU32 aperture; + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); +} NV2080_CTRL_FIFO_MEM_INFO; + +/* + * NV2080_CTRL_FIFO_CHANNEL_MEM_INFO + * + * This structure describes the details of the instance memory, ramfc + * and method buffers a channel. It consists of the following fields + * + * inst + * Structure describing the details of instance memory + * ramfc + * Structure describing the details of ramfc + * methodBuf + * Array of structures describing the details of method buffers + * methodBufCount + * Number of method buffers(one per runqueue) + */ + +// max runqueues +#define NV2080_CTRL_FIFO_GET_CHANNEL_MEM_INFO_MAX_COUNT 0x2 + +typedef struct NV2080_CTRL_FIFO_CHANNEL_MEM_INFO { + NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_MEM_INFO inst, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_MEM_INFO ramfc, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_MEM_INFO methodBuf[NV2080_CTRL_FIFO_GET_CHANNEL_MEM_INFO_MAX_COUNT], 8); + NvU32 methodBufCount; +} NV2080_CTRL_FIFO_CHANNEL_MEM_INFO; + +/* + * NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM + * + * This command returns the memory aperture, physical base address and the + * size of each of the instance memory, cache1 and ramfc of a channel. + * + * hChannel + * The handle to the channel for which the memory information is desired. + * chMemInfo + * A NV2080_CTRL_FIFO_CHANNEL_MEM_INFO structure + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_CHANNEL +*/ + +#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO (0x2080110c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS { + NvHandle hChannel; + NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_CHANNEL_MEM_INFO chMemInfo, 8); +} NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS; + +#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_INVALID 0x00000000 +#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_VIDMEM 0x00000001 +#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_COH 0x00000002 +#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_NCOH 0x00000003 + +/* + * NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION + * + * This command determines the location (vidmem/sysmem) + * and attribute (cached/uncached/write combined) of memory where USERD is located. + * + * aperture + * One of the NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_* values. + * + * attribute + * One of the NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_* values. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_POINTER +*/ + +#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION (0x2080110d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS { + NvU32 aperture; + NvU32 attribute; +} NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS; + +// support for CPU coherent vidmem (VIDMEM_NVILINK_COH) is not yet available in RM + +#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_VIDMEM 0x00000000 +#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_SYSMEM 0x00000001 + +#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_CACHED 0x00000000 +#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_UNCACHED 0X00000001 +#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_WRITECOMBINED 0X00000002 + + + +/* + * NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE + * + * This command retrieves entries from the SW encoded GPU device info table + * from Host RM. + * + * Parameters: + * + * baseIndex [in] + * The starting index to read from the devinfo table. Must be a multiple of + * MAX_ENTRIES. + * + * entries [out] + * A buffer to store up to MAX_ENTRIES entries of the devinfo table. + * + * numEntries [out] + * Number of populated entries in the provided buffer. + * + * bMore [out] + * A boolean flag indicating whether more valid entries are available to be + * read. A value of NV_TRUE indicates that a further call to this control + * with baseIndex incremented by MAX_ENTRIES will yield further valid data. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE (0x20801112) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_DEVICES 256 +#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES 32 +#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES 16 +#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA 2 +#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN 16 + +/* + * NV2080_CTRL_FIFO_DEVICE_ENTRY + * + * This structure contains the engine, engine name and + * push buffers information of FIFO device entry. It consists of the following fields + * + * engineData + * Type of the engine + * pbdmaIds + * List of pbdma ids associated with engine + * pbdmaFaultIds + * List of pbdma fault ids associated with engine + * numPbdmas + * Number of pbdmas + * engineName + * Name of the engine + */ +typedef struct NV2080_CTRL_FIFO_DEVICE_ENTRY { + NvU32 engineData[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES]; + NvU32 pbdmaIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA]; + NvU32 pbdmaFaultIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA]; + NvU32 numPbdmas; + char engineName[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN]; +} NV2080_CTRL_FIFO_DEVICE_ENTRY; + +#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS { + NvU32 baseIndex; + NvU32 numEntries; + NvBool bMore; + // C form: NV2080_CTRL_FIFO_DEVICE_ENTRY entries[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES]; + NV2080_CTRL_FIFO_DEVICE_ENTRY entries[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES]; +} NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT + * + * This command clears the ENGINE or PBDMA FAULTED bit and reschedules the faulted channel + * by ringing channel's doorbell + * + * Parameters: + * + * engineType [in] + * The NV2080_ENGINE_TYPE of the engine to which the faulted + * channel is bound. This may be a logical id for guest RM in + * case of SMC. + * + * vChid [in] + * Virtual channel ID on which the fault occurred + * + * faultType [in] + * Whether fault was triggered by engine (_ENGINE_FAULTED) or PBDMA (_PBDMA_FAULTED) + * The value specified must be one of the NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_* values + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT (0x20801113) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_ENGINE 0x00000001 +#define NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_PBDMA 0x00000002 + +#define NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS { + NvU32 engineType; + NvU32 vChid; + NvU32 faultType; +} NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS; + + + +/* + * NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY + * + * Allows clients to set the global scheduling policy for all runlists + * associated to the given subdevice. + * + * Currently, this is only supported for HW runlists. + * + * Since this is a global setting, only privileged clients will be allowed to + * set it. Regular clients will get NV_ERR_INSUFFICIENT_PERMISSIONS error. + * + * Once a certain scheduling policy is set, that policy cannot be changed to a + * different one unless all clients which set it have either restored the policy + * (using the corresponding restore flag) or died. Clients trying to set a + * policy while a different one is locked by another client will get a + * NV_ERR_INVALID_STATE error. + * + * The same client can set a scheduling policy and later change to another one + * only when no other clients have set the same policy. Such sequence will be + * equivalent to restoring the policy in between. + * + * For instance, the following sequence: + * + * 1. Set policy A + * 2. Set policy B + * + * is equivalent to: + * + * 1. Set policy A + * 2. Restore policy + * 3. Set policy B + * + * Parameters: + * + * flags + * This field specifies the operational properties to be applied: + * + * - NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_FALSE + * Try to set the provided 'schedPolicy' scheduling policy. If the + * operation succeeds, other clients will be prevented from setting a + * different scheduling policy until all clients using it have either + * restored it or died. + * + * - NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_TRUE + * Let the scheduler know the client no longer requires the current + * scheduling policy. This may or may not actually change the + * scheduling policy, depending on how many other clients are also + * using the current policy. + * + * The 'schedPolicy' parameter is ignored when this flag is set. + * + * schedPolicy + * One of: + * + * - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_DEFAULT + * Set the default scheduling policy and prevent other clients from + * changing it. + * + * - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED + * This scheduling policy will make channels to be scheduled according + * to their interleave level. See NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL + * description for more details. + * - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM + * This scheduling policy will make channels to be scheduled according + * to their interleave level per WDDM policy. + * See NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL description for more details. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_INVALID_STATE + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY (0x20801115) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS_MESSAGE_ID" */ + +/* schedPolicy values */ +#define NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_DEFAULT 0x0 +#define NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED 0x1 +#define NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM 0x2 + +/* SET_SCHED_POLICY flags */ +#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE 0:0 +#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_FALSE (0x00000000) +#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_TRUE (0x00000001) + +#define NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS { + NvU32 flags; + NvU32 schedPolicy; +} NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_UPDATE_CHANNEL_INFO + * + * This command updates the channel info params for an existing channel + * + * Can be a deferred Api. The control call can be used for migrating a + * + * channel to a new userd and gpfifo + * + * Parameters: + * [in] hClient - Client handle + * [in] hChannel - Channel handle + * [in] hUserdMemory - UserD handle + * [in] gpFifoEntries - Number of Gpfifo Entries + * [in] gpFifoOffset - Gpfifo Virtual Offset + * [in] userdOffset - UserD offset + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FIFO_UPDATE_CHANNEL_INFO (0x20801116) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS { + NvHandle hClient; + NvHandle hChannel; + NvHandle hUserdMemory; + NvU32 gpFifoEntries; + NV_DECLARE_ALIGNED(NvU64 gpFifoOffset, 8); + NV_DECLARE_ALIGNED(NvU64 userdOffset, 8); +} NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS + * + * This command will disable or enable scheduling of all usermode channels. + * + * bDisable + * This value determines whether to disable or enable the usermode channels. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS (0x20801117) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS_MESSAGE_ID (0x17U) + +typedef struct NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS { + NvBool bDisable; +} NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB + * + * When a VF subcontext is marked as a zombie, host RM points its PDB to a dummy + * page allocated by guest RM in GPA space. This command provides the parameters + * of the guest RMs memory descriptor to be able to create a corresponding + * memory descriptor on the host RM. Host RM uses this to program the PDB of a + * zombie subcontext. + * + * Parameters: + * Input parameters to describe the memory descriptor + * [in] base + * [in] size + * [in] addressSpace + * [in] cacheAttrib + */ +#define NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB (0x20801118) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS { + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 addressSpace; + NvU32 cacheAttrib; +} NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_GET_ALLOCATED_CHANNELS + * + * Get's a bitmask of allocated channels. No guarantees are made about + * synchronization. A channel returned as allocated by this ctrl cmd might have + * already been destructed. + * + * Parameters: + * [in] runlistId + * [in,out] bitMask A 1 bit indicates that a channel with this index/id is + * allocated. This field is a multiple of 32 bits and each 32 + * bit group must be accessed as a platform 32 bit int to + * correctly map channel IDs. + * + */ +#define NV2080_CTRL_CMD_FIFO_GET_ALLOCATED_CHANNELS (0x20801119) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS_MESSAGE_ID" */ + +/* + * The maximum number than can be returned by + * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS + */ +#define NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS 4096 + +#define NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS { + NvU32 runlistId; + NvU32 bitMask[NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS / 32]; +} NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS; + + + +/* _ctrl2080fifo_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h new file mode 100644 index 0000000..3fe89b9 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h @@ -0,0 +1,208 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080fla.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX FLA control commands and parameters */ + +/* + * NV2080_CTRL_CMD_FLA_RANGE + * + * This command is used to initialize/destroy FLA VAS for a GPU.This is intended + * to be used by RM clients that manages the FLA VASpace range. The mode of the + * command is decided based on the parameter passed by the client. + * + * base + * This parameter specifies the base of the FLA VAS that needs to be allocated + * for this GPU + * + * size + * This parameter specifies the size of the FLA VAS that needs to be allocated + * for this GPU + * + * mode + * This parameter specifies the functionality of the command. + * MODE_INITIALIZE + * Setting this mode, will initialize the FLA VASpace for the gpu with + * base and size passed as arguments. FLA VASpace will be owned by RM. + * if the client calls the command more than once before destroying + * the FLA VAS, then this command will verify the range exported before and + * return success if it matches. If FLA is not supported for the platform, + * will return NV_ERR_NOT_SUPPORTED. + * MODE_DESTROY (deprecated) + * This command is NOP. + * MODE_HOST_MANAGED_VAS_INITIALIZE + * This mode will initialize the FLA VASpace for the gpu with hVASpace + * handle in addition to base and size arguments. FLA VASpace will be initiated + * and owned by guest RM. Used only in virtualization platforms by internal clients. + * MODE_HOST_MANAGED_VAS_DESTROY + * This mode will destroy the FLA VAS associated with the device. It will destruct + * only the resources associated with host RM side. Used only in virtualization platforms + * by internal clients. + * + * hVASpace + * This paramete specifies the FLA VAspace that needs to be associated with + * device. This parameter takes effect only for internal client in virtualization + * platforms. For any other platform and external clients, this parameter has no effect. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_IN_USE + * NV_ERR_INVALID_OWNER + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_FLA_RANGE (0x20803501) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_RANGE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLA_RANGE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_FLA_RANGE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 mode; + NvHandle hVASpace; +} NV2080_CTRL_FLA_RANGE_PARAMS; + +#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_NONE 0x00000000 +#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_INITIALIZE NVBIT(0) +#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_DESTROY NVBIT(1) +#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_INITIALIZE NVBIT(2) +#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_DESTROY NVBIT(3) + + +/* + * NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK + * + * This command is used to (un)bind FLA Instance Memory Block(IMB) with MMU. + * This control call is created for vGPU platform, when a FLA VAS is created/destroyed + * by Guest RM. Guest RM doesn't have privilege to (un)bind the IMB with MMU, hence + * need to be RPC-ed to Host RM to (un)bind + * The mode of the command is decided based on the actionParam passed by the client. + * + * imbPhysAddr + * This parameter specifies the FLA Instance Memory Block PA to be programmed + * to MMU. IMB address should be 4k aligned. This parameter is needed only + * for ACTION_BIND. + * + * addrSpace + * This parameter specifies the address space of FLA Instance Memory Block. This + * parmater is needed only for ACTION_BIND. + * Available options are: + * NV2080_CTRL_FLA_ADDRSPACE_SYSMEM + * Clients need to use this address space if the IMB is located in sysmem + * NV2080_CTRL_FLA_ADDRSPACE_FBMEM + * Clients need to use this address space if the IMB is located in FB + * + * actionParam + * This parameter specifies the functionality of the command. + * NV2080_CTRL_FLA_ACTION_BIND + * Setting this type, will call busBindFla helper HAL + * NV2080_CTRL_FLA_ACTION_UNBIND + * Setting this type, will call busUnbindFla helper HAL + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +typedef enum NV2080_CTRL_FLA_ADDRSPACE { + NV2080_CTRL_FLA_ADDRSPACE_SYSMEM = 0, + NV2080_CTRL_FLA_ADDRSPACE_FBMEM = 1, +} NV2080_CTRL_FLA_ADDRSPACE; + +typedef enum NV2080_CTRL_FLA_ACTION { + NV2080_CTRL_FLA_ACTION_BIND = 0, + NV2080_CTRL_FLA_ACTION_UNBIND = 1, +} NV2080_CTRL_FLA_ACTION; + +#define NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK (0x20803502) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS { + NV_DECLARE_ALIGNED(NvU64 imbPhysAddr, 8); + NV2080_CTRL_FLA_ADDRSPACE addrSpace; + NV2080_CTRL_FLA_ACTION flaAction; +} NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS; + + +/* + * NV2080_CTRL_CMD_FLA_GET_RANGE + * + * This command is used to query the FLA base and size from plugin to return as static info to Guest RM. + * + * base + * This parameter returns the base address of FLA range registered to the subdevice. + * size + * This parameter returns the size of FLA range registered to the subdevice. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FLA_GET_RANGE (0x20803503) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_GET_RANGE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLA_GET_RANGE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_FLA_GET_RANGE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); +} NV2080_CTRL_FLA_GET_RANGE_PARAMS; + +/* + * NV2080_CTRL_CMD_FLA_GET_FABRIC_MEM_STATS + * + * This command returns the total size and the free size of the fabric vaspace. + * Note: This returns the information for the FABRIC_VASPACE_A class. + * + * totalSize[OUT] + * - Total fabric vaspace. + * + * freeSize [OUT] + * - Available fabric vaspace. + * + * Possible status values returned are: + * + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FLA_GET_FABRIC_MEM_STATS (0x20803504) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 totalSize, 8); + NV_DECLARE_ALIGNED(NvU64 freeSize, 8); +} NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS; + +// _ctrl2080fla_h_ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h new file mode 100644 index 0000000..474f916 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h @@ -0,0 +1,444 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080flcn.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + + +// +// XAPICHK/XAPI_TEST breaks on including "nvmisc.h". Workaround: don't include +// the header in that case and just redefine the macros we need. +// +#include "nvmisc.h" +/* + * Obsolete Falcon ID type. Use NV2080_ENGINE_TYPE_ instead + */ +#define FALCON_ID_PMU (NV2080_ENGINE_TYPE_PMU) +#define FALCON_ID_DPU (NV2080_ENGINE_TYPE_DPU) +#define FALCON_ID_SEC2 (NV2080_ENGINE_TYPE_SEC2) +#define FALCON_ID_FBFLCN (NV2080_ENGINE_TYPE_FBFLCN) + +/* + * NV2080_CTRL_CMD_FLCN_GET_DMEM_USAGE + * + * This command returns total heap size and free heap size of a falcon engine + * + * flcnID + * The falcon ID + * + * heapSize + * Total heap size in byte + * + * heapFree + * Total free heap size in byte + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT + */ +#define NV2080_CTRL_CMD_FLCN_GET_DMEM_USAGE (0x20803101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS { + NvU32 flcnID; + NvU32 heapSize; + NvU32 heapFree; +} NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS; + +/*! + * @defgroup NVOS_INST_EVT Instrumentation event types. + * @{ + */ + +//! Reserved for uStreamer internal use. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RSVD_DO_NOT_USE 0x00U + +//! RTOS CTXSW includes next taskID and number of ODP for previous task. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_END 0x01U + +//! Begin of a HW IRQ. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_BEGIN 0x02U + +//! End of a HW IRQ, before stack pinning etc is performed. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_END 0x03U + +//! RTOS Timer tick slip. (Only for # tick processed > 1). +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TIMER_TICK 0x04U + +//! Task start processing an event, includes taskId, eventType and unitId (optional). +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_BEGIN 0x05U + +//! Task finished processing an event, incldues taskId. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_END 0x06U + +//! Latency for inserting response into RM queue. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RM_QUEUE_LATENCY 0x07U + +//! Special / multi-purpose event, see field definition below. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_SPECIAL_EVENT 0x08U + +//! Unused, recycle +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_UNUSED_0 0x09U + +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_DMA_END 0x0AU + +//! Begin/end for arbitrary block of code. The payload contains a sub-ID for each location profiled. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_BEGIN 0x0BU +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_END 0x0CU + +//! Queueing time for the most recent event. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_LATENCY 0x0DU +/*!@}*/ + +#define NV2080_CTRL_FLCN_NVOS_INST_INVALID_TASK_ID 0xFFU + +/* + * NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH + * + * Get the egine arch i.e FALCON, RISCV etc given the NV2080_ENGINE_TYPE_*. + * + */ +#define NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH (0x20803118) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS { + //! The engine type, from NV2080_ENGINE_TYPE_* + NvU32 engine; + + //! The engine architecture - FALCON or RISC-V + NvU32 engineArch; +} NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS; + +/*! + * @defgroup Engine Arch types + * @{ + */ +#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_DEFAULT 0x0 +#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_FALCON 0x1 +#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV 0x2 +/*!@}*/ + + +/* ----------------------- uStreamer (INST v2) ------------------------------ */ +/*! + * @defgroup NV2080_CTRL_FLCN_USTREAMER_EVENT uStreamer event fields. + * + * This is a binary-packed representation of uStreamer events. There are + * three main types of entry: Head, Payload, and Tail. COMM here is used + * when a field is shared among multiple event types. + * + * @{ + */ +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_COMM_FLAG 31:31 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_COMM_HEAD 30:30 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_VARIABLE 29:29 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EXTEND 28:28 + +/*! + * Below DRF's need constants assigned to start and end so they can be represented in FINN properly + * This is because FINN v1 will not have the ability to represent DRF's and bit fields yet. + */ +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT (27) +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE (20) +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID \ + (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT) : \ + (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE) +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT (28) +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE (24) +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT \ + (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT) : \ + (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE) + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_LENGTH 19:8 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOAD 7:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT 23:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_HEAD_TIME 29:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_DATA_PAYLOAD 30:0 +/*!@}*/ + + +/*! + * @defgroup NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_BREAKDOWN + * + * These DRFs define breakdown of the compact payload for various event IDs. + * + * @{ + */ + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_TASK_ID 7:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON 10:8 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_YIELD 0x0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_INT0 0x1 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_TIMER_TICK 0x2 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_QUEUE_BLOCK 0x3 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_DMA_SUSPENDED 0x4 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_ODP_MISS_COUNT 23:11 + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TIMER_TICK_TIME_SLIP 23:0 + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_TASK_ID 7:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_UNIT_ID 15:8 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_EVENT_TYPE 23:16 + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_TASK_ID 7:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_CALLBACK_ID 15:8 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC 15:8 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC_BOBJ_CMD_BASE 0xF0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_CLASS_ID 23:16 + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_RM_QUEUE_LATENCY_SHIFT 10U + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_TASK_ID 7:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID 23:8 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_RESERVED 0x000000 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_CB_ENQUEUE_FAIL 0x000001 + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_LATENCY_SHIFT 6U + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID 11:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_INVALID 0x000 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_VF_SWITCH_TOTAL 0x001 + +/*!@}*/ + + +/*! + * @defgroup NV2080_CTRL_FLCN_USTREAMER_FEATURE + * + * This defines all the features currently supported by uStreamer. For a new + * usecase of uStreamer, a feature should be defined here describing the usecase. + * This value should be unique for each queue. + * + * @{ + */ +#define NV2080_CTRL_FLCN_USTREAMER_FEATURE_DEFAULT 0U +#define NV2080_CTRL_FLCN_USTREAMER_FEATURE_PMUMON 1U +#define NV2080_CTRL_FLCN_USTREAMER_FEATURE__COUNT 2U +/*!@}*/ + +/*! + * @defgroup NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY + * + * This defines the DRF used for ustreamer queue policy + * + * @{ + */ + +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH 0:0 +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_DISABLED 0U +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_ENABLED 1U + +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH 1:1 +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_DISABLED 0U +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_ENABLED 1U + +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH 2:2 +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_DISABLED 0U +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_ENABLED 1U + +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_THRESHOLD 31:8 + +/*!@}*/ + +/*! + * The maximum number of compact event types, calculated from the number of bits + * in the event structure. + */ +#define NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES_COMPACT (0x20U) /* finn: Evaluated from "(1 << (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT - NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE + 1))" */ + +/*! + * The maximum number of event types, calculated from the number of bits in the + * event structure. + */ +#define NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES (0x120U) /* finn: Evaluated from "((1 << (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT - NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE + 1)) + NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES_COMPACT)" */ + +/*! + * The number of bytes required in the event mask to contain all event types. + */ +#define NV2080_CTRL_FLCN_USTREAMER_MASK_SIZE_BYTES (0x24U) /* finn: Evaluated from "((NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES + 7) / 8)" */ + +/*! + * uStreamer Event Filter type, stored as a bitmask. + */ +typedef struct NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER { + NvU8 mask[NV2080_CTRL_FLCN_USTREAMER_MASK_SIZE_BYTES]; +} NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER; + +/*! + * NV2080_CTRL_CMD_FLCN_USTREAMER_QUEUE_INFO + * Get queue info for mapping / unmapping + */ +#define NV2080_CTRL_CMD_FLCN_USTREAMER_QUEUE_INFO (0x20803120) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS { + //! The engine type, from NV2080_ENGINE_TYPE_* + NvU32 engine; + + //! + // The page size of the requested queue in bytes. + // + NvU32 pageSize; + + //! Offset of the queue buffer in FB. + NV_DECLARE_ALIGNED(NvUPtr offset, 8); + + //! + // The size of the user-mapped instrumentation buffer. Measured in bytes. + // + NvU32 size; + + //! + // The feature ID of the queue. + // + NvU8 queueFeatureId; +} NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET/SET + * + * Get/set the event bitmask for the default queue. + */ +#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET (0x20803122) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x22" */ + +#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_SET (0x20803123) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x23" */ + +typedef struct NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS { + //! The engine type, from NV2080_ENGINE_TYPE_* + NvU32 engine; + + /*! + * The bitmask of which event types to log. An event type corresponding to + * a bit with a zero will be ignored at the log site, which prevents it + * from filling up the resident buffer in the PMU. In general, set this to + * only log the event types you actually want to use. + * Refer to NVOS_BM_* in nvos_utility.h for usage. + */ + NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER eventFilter; + + //! The queueId of the queue whose eventFilter we want to interact with + NvU8 queueId; +} NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS; + +/* + * NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO + * + * This command provides the attributes of the falcon engine context buffer + * + * hUserClient [IN] + * This parameter specifies the client handle that owns this channel. + * hChannel [IN] + * This parameter specifies the channel or channel group (TSG) handle + * alignment + * Specifies the alignment requirement for each context buffer + * size + * Aligned size of context buffer + * bufferHandle + * Opaque pointer to memdesc. Used by kernel clients for tracking purpose only. + * pageCount + * allocation size in the form of pageCount + * physAddr + * Physical address of the buffer first page + * aperture + * allocation aperture. Could be SYSMEM, VIDMEM, UNKNOWN + * kind + * PTE kind of this allocation. + * pageSize + * Page size of the buffer. + * bIsContigous + * States if physical allocation for this buffer is contiguous. PageSize will + * have no meaning if this flag is set. + * bDeviceDescendant + * TRUE if the allocation is a constructed under a Device or Subdevice. + * uuid + * SHA1 UUID of the Device or Subdevice. Valid when bDeviceDescendant is TRUE. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO (0x20803124) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID (0x24U) + +typedef struct NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS { + NvHandle hUserClient; + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 alignment, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NV_DECLARE_ALIGNED(NvP64 bufferHandle, 8); + NV_DECLARE_ALIGNED(NvU64 pageCount, 8); + NV_DECLARE_ALIGNED(NvU64 physAddr, 8); + NvU32 aperture; + NvU32 kind; + NvU32 pageSize; + NvBool bIsContigous; + NvBool bDeviceDescendant; + NvU8 uuid[16]; +} NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS; + +// Aperture flags +#define NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_UNKNWON ADDR_UNKNOWN +#define NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_SYSMEM ADDR_SYSMEM +#define NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_FBMEM ADDR_FBMEM + +/* + * NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE + * + * This command provides the size of the falcon engine context buffer + * + * hChannel [IN] + * This parameter specifies the channel or channel group (TSG) handle + * totalBufferSize [OUT] + * This parameter returns the total context buffers size. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE (0x20803125) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x25U) + +typedef struct NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS { + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 totalBufferSize, 8); +} NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS; + + + +/* _ctrl2080flcn_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h new file mode 100644 index 0000000..2af63e7 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080fuse.finn +// + + + +/* _ctrl2080fuse_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h new file mode 100644 index 0000000..41f9767 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h @@ -0,0 +1,36 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080gpio.finn +// + + + +/* _ctrl2080gpio_h_ */ + +#include "ctrl/ctrl2080/ctrl2080base.h" + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h new file mode 100644 index 0000000..0b97569 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h @@ -0,0 +1,4115 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080gpu.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "ctrl/ctrl2080/ctrl2080gr.h" +#include "ctrl/ctrl0000/ctrl0000system.h" +#include "nvcfg_sdk.h" +#include "nvstatus.h" + +#define NV_GRID_LICENSE_INFO_MAX_LENGTH (128) + +/* License info strings for vGPU products */ +#define NV_GRID_LICENSE_FEATURE_VPC_EDITION "GRID-Virtual-PC,2.0;Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0" +#define NV_GRID_LICENSE_FEATURE_VAPPS_EDITION "GRID-Virtual-Apps,3.0" +#define NV_GRID_LICENSE_FEATURE_VIRTUAL_WORKSTATION_EDITION "Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0" +#define NV_GRID_LICENSE_FEATURE_GAMING_EDITION "GRID-vGaming,8.0" +#define NV_GRID_LICENSE_FEATURE_COMPUTE_EDITION "NVIDIA-vComputeServer,9.0;Quadro-Virtual-DWS,5.0" + +#define NV_GRID_LICENSED_PRODUCT_VWS "NVIDIA RTX Virtual Workstation" +#define NV_GRID_LICENSED_PRODUCT_GAMING "NVIDIA Cloud Gaming" +#define NV_GRID_LICENSED_PRODUCT_VPC "NVIDIA Virtual PC" +#define NV_GRID_LICENSED_PRODUCT_VAPPS "NVIDIA Virtual Applications" +#define NV_GRID_LICENSED_PRODUCT_COMPUTE "NVIDIA Virtual Compute Server" + + + +/* NV20_SUBDEVICE_XX gpu control commands and parameters */ + +/* Valid feature values */ +#define NV2080_CTRL_GPU_GET_FEATURES_CLK_ARCH_DOMAINS 0:0 +#define NV2080_CTRL_GPU_GET_FEATURES_CLK_ARCH_DOMAINS_FALSE (0x00000000U) +#define NV2080_CTRL_GPU_GET_FEATURES_CLK_ARCH_DOMAINS_TRUE (0x00000001U) + + + +typedef struct NV2080_CTRL_GPU_INFO { + NvU32 index; + NvU32 data; +} NV2080_CTRL_GPU_INFO; + +/* valid gpu info index values */ + + + +#define NV2080_CTRL_GPU_INFO_INDEX_MINOR_REVISION_EXT (0x00000004U) + + +#define NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV0 (0x00000012U) +#define NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV1 (0x00000013U) + + +#define NV2080_CTRL_GPU_INFO_INDEX_SYSMEM_ACCESS (0x0000001fU) + + +#define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD (0x00000022U) + + +#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE (0x00000025U) +#define NV2080_CTRL_GPU_INFO_INDEX_IBMNPU_RELAXED_ORDERING (0x00000026U) +#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED (0x00000027U) +#define NV2080_CTRL_GPU_INFO_INDEX_NVSWITCH_PROXY_DETECTED (0x00000028U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT (0x00000029U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SMC_MODE (0x0000002aU) +#define NV2080_CTRL_GPU_INFO_INDEX_SPLIT_VAS_MGMT_SERVER_CLIENT_RM (0x0000002bU) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SM_VERSION (0x0000002cU) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY (0x0000002dU) + + +#define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM (0x0000002fU) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY (0x00000030U) +#define NV2080_CTRL_GPU_INFO_INDEX_NVENC_STATS_REPORTING_STATE (0x00000031U) + + +#define NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED (0x00000033U) +#define NV2080_CTRL_GPU_INFO_INDEX_DISPLAY_ENABLED (0x00000034U) +#define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED (0x00000035U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY (0x00000036U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY (0x00000037U) + + +#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU (0x0000003cU) +#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY (0x0000003dU) +#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x0000003eU) + +/* valid minor revision extended values */ +#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE (0x00000000U) +#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_P (0x00000001U) +#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_V (0x00000002U) +#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_PV (0x00000003U) + + + +/* valid system memory access capability values */ +#define NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_YES (0x00000001U) + + + +/* valid gemini board values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_YES (0x00000001U) + +/* valid surprise removal values */ +#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_YES (0x00000001U) + +/* valid relaxed ordering values */ +#define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_DISABLED (0x00000000U) +#define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_ENABLED (0x00000001U) +#define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_UNSUPPORTED (0xFFFFFFFFU) + +/* valid poison fuse capability values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_YES (0x00000001U) + +/* valid nvswitch proxy detected values */ +#define NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_YES (0x00000001U) + +/* valid NVSR GPU support info values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_YES (0x00000001U) + +/* valid SMC mode values */ +#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_UNSUPPORTED (0x00000000U) +#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLED (0x00000001U) +#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLED (0x00000002U) +#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLE_PENDING (0x00000003U) +#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLE_PENDING (0x00000004U) + +/* valid split VAS mode values */ +#define NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_YES (0x00000001U) + +/* valid grid capability values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_YES (0x00000001U) + +/* valid per runlist channel ram capability values */ +#define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_DISABLED (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_ENABLED (0x00000001U) + +/* valid ATS capability values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_YES (0x00000001U) + +/* valid Nvenc Session Stats reporting state values */ +#define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_DISABLED (0x00000000U) +#define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED (0x00000001U) +#define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_NOT_SUPPORTED (0x00000002U) + +/* valid 4K PAGE isolation requirement values */ +#define NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_YES (0x00000001U) + +/* valid display enabled values */ +#define NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_YES (0x00000001U) + +/* valid mobile config enabled values */ +#define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_YES (0x00000001U) + + +/* valid profiling capability values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_DISABLED (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_ENABLED (0x00000001U) + +/* valid debugging capability values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_DISABLED (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_ENABLED (0x00000001U) + + + +/* valid CMP (Crypto Mining Processor) SKU values */ +#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_YES (0x00000001U) + + +/* valid dma-buf suport values */ +#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES (0x00000001U) + +/* + * NV2080_CTRL_CMD_GPU_GET_INFO + * + * This command returns gpu information for the associated GPU. Requests + * to retrieve gpu information use a list of one or more NV2080_CTRL_GPU_INFO + * structures. + * + * gpuInfoListSize + * This field specifies the number of entries on the caller's + * gpuInfoList. + * gpuInfoList + * This field specifies a pointer in the caller's address space + * to the buffer into which the gpu information is to be returned. + * This buffer must be at least as big as gpuInfoListSize multiplied + * by the size of the NV2080_CTRL_GPU_INFO structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_OPERATING_SYSTEM + */ +#define NV2080_CTRL_CMD_GPU_GET_INFO (0x20800101U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_GPU_GET_INFO_PARAMS { + NvU32 gpuInfoListSize; + NV_DECLARE_ALIGNED(NvP64 gpuInfoList, 8); +} NV2080_CTRL_GPU_GET_INFO_PARAMS; + +#define NV2080_CTRL_CMD_GPU_GET_INFO_V2 (0x20800102U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x2" */ + +typedef struct NV2080_CTRL_GPU_GET_INFO_V2_PARAMS { + NvU32 gpuInfoListSize; + NV2080_CTRL_GPU_INFO gpuInfoList[NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE]; +} NV2080_CTRL_GPU_GET_INFO_V2_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_NAME_STRING + * + * This command returns the name of the GPU in string form in either ASCII + * or UNICODE format. + * + * gpuNameStringFlags + * This field specifies flags to use while creating the GPU name string. + * Valid flags values: + * NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII + * The returned name string should be in standard ASCII format. + * NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE + * The returned name string should be in unicode format. + * gpuNameString + * This field contains the buffer into which the name string should be + * returned. The length of the returned string will be no more than + * NV2080_CTRL_GPU_MAX_NAME_STRING_LENGTH bytes in size. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV2080_CTRL_CMD_GPU_GET_NAME_STRING (0x20800110U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID" */ + +#define NV2080_GPU_MAX_NAME_STRING_LENGTH (0x0000040U) + +// This field is deprecated - 'gpuNameStringFlags' is now a simple scalar. +// Field maintained (and extended from 0:0) for compile-time compatibility. +#define NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE 31:0 + +/* valid gpu name string flags */ +#define NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII (0x00000000U) +#define NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE (0x00000001U) + +#define NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS { + NvU32 gpuNameStringFlags; + union { + NvU8 ascii[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + NvU16 unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + } gpuNameString; +} NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING + * + * This command returns the short name of the GPU in ASCII string form. + * + * gpuShortNameString + * This field contains the buffer into which the short name string should + * be returned. The length of the returned string will be no more than + * NV2080_MAX_NAME_STRING_LENGTH bytes in size. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING (0x20800111U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS { + NvU8 gpuShortNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH]; +} NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_SET_POWER + * + * This command sets the power state for the GPU as a whole, various engines, + * or clocks. + * + * target + * One of NV2080_CTRL_GPU_SET_POWER_TARGET_* + * + * newLevel + * One of NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_* + * NV2080_CTRL_GPU_SET_POWER_STATE_ENGINE_LEVEL_* + * NV2080_CTRL_GPU_SET_POWER_STATE_CLOCK_LEVEL_* + * depending on the target above. + * + * oldLevel + * Previous level as appropriate. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_GPU_SET_POWER (0x20800112U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV2080_CTRL_GPU_SET_POWER_PARAMS { + NvU32 target; + NvU32 newLevel; + NvU32 oldLevel; +} NV2080_CTRL_GPU_SET_POWER_PARAMS; + + + +#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_0 (0x00000000U) +#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_1 (0x00000001U) +#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_2 (0x00000002U) +#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3 (0x00000003U) +#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_4 (0x00000004U) +#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_7 (0x00000007U) + +/* + * NV2080_CTRL_CMD_GPU_GET_SDM + * + * This command returns the subdevice mask value for the associated subdevice. + * The subdevice mask value can be used with the SET_SUBDEVICE_MASK instruction + * provided by the NV36_CHANNEL_DMA and newer channel dma classes. + * + * subdeviceMask [out] + * This field return the subdevice mask value. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_GPU_GET_SDM (0x20800118U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV2080_CTRL_GPU_GET_SDM_PARAMS { + NvU32 subdeviceMask; +} NV2080_CTRL_GPU_GET_SDM_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_SET_SDM + * + * This command sets the subdevice instance and mask value for the associated subdevice. + * The subdevice mask value can be used with the SET_SUBDEVICE_MASK instruction + * provided by the NV36_CHANNEL_DMA and newer channel dma classes. + * It must be called before the GPU HW is initialized otherwise + * NV_ERR_INVALID_STATE is being returned. + * + * subdeviceMask [in] + * This field configures the subdevice mask value for the GPU/Subdevice + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_DATA + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_GPU_SET_SDM (0x20800120U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV2080_CTRL_GPU_SET_SDM_PARAMS { + NvU32 subdeviceMask; +} NV2080_CTRL_GPU_SET_SDM_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO + * + * This command returns the associated subdevices' simulation information. + * + * type + * This field returns the simulation type. + * One of NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_* + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO (0x20800119U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS { + NvU32 type; +} NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS; + +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_NONE (0x00000000U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_MODS_AMODEL (0x00000001U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_LIVE_AMODEL (0x00000002U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_FMODEL (0x00000003U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_RTL (0x00000004U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU (0x00000005U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU_LOW_POWER (0x00000006U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA (0x00000007U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_RTL (0x00000008U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_FMODEL (0x00000009U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_UNKNOWN (0xFFFFFFFFU) + +/* + * NV2080_CTRL_GPU_REG_OP + * + * This structure describes register operation information for use with + * the NV2080_CTRL_CMD_GPU_EXEC_REG_OPS command. The structure describes + * a single register operation. The operation can be a read or write and + * can involve either 32bits or 64bits of data. + * + * For 32bit read operations, the operation takes the following form: + * + * regValueLo = read(bar0 + regOffset) + * regValueHi = 0 + * + * For 64bit read operations, the operation takes the following form: + * + * regValueLo = read(bar0 + regOffset) + * regValueHi = read(bar0 + regOffset + 4) + * + * For 32bit write operations, the operation takes the following form: + * + * new = ((read(bar0 + regOffset) & ~regAndNMaskLo) | regValueLo) + * write(bar0 + regOffset, new) + * + * For 64bit write operations, the operation takes the following form: + * + * new_lo = ((read(bar0 + regOffset) & ~regAndNMaskLo) | regValueLo) + * new_hi = ((read(bar0 + regOffset + 4) & ~regAndNMaskHi) | regValueHi) + * write(bar0 + regOffset, new_lo) + * write(bar0 + regOffset + 4, new_hi) + * + * Details on the parameters follow: + * + * regOp + * This field specifies the operation to be applied to the register + * specified by the regOffset parameter. Valid values for this + * parameter are: + * NV2080_CTRL_GPU_REG_OP_READ_08 + * The register operation should be a 8bit global privileged register read. + * NV2080_CTRL_GPU_REG_OP_WRITE_08 + * The register operation should be a 8bit global privileged register write. + * NV2080_CTRL_GPU_REG_OP_READ_32 + * The register operation should be a 32bit register read. + * NV2080_CTRL_GPU_REG_OP_WRITE_32 + * The register operation should be a 32bit register write. + * NV2080_CTRL_GPU_REG_OP_READ_64 + * The register operation should be a 64bit register read. + * NV2080_CTRL_GPU_REG_OP_WRITE_64 + * The register operation should be a 64bit register write. + * regType + * This field specifies the type of the register specified by the + * regOffset parameter. Valid values for this parameter are: + * NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL + * The register is a global privileged register. Read operations + * return the current value from the associated global register. + * Write operations for registers of this type take effect immediately. + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX + * The register is a graphics context register. Read operations + * return the current value from the associated global register. + * Write operations are applied to all existing graphics engine + * contexts. Any newly created graphics engine contexts will also + * be modified. + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC + * This is a graphics context TPC register group. Write operations are + * applied to TPC group(s) specified by regGroupMask. + * This field is ignored for read operations. + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM + * This is a graphics context SM register group that is inside TPC + * group. Write operations are applied to SM group(s) specified by + * regGroupMask (TPC) and regSubGroupMask (SM). This field is ignored + * for read operations. + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP + * This is a graphics context CROP register group. Write operations + * are applied to registers specified by regGroupMask. This field is + * ignored for read operations. + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP + * This is a graphics context ZROP register group. Write operations + * are applied to registers specified by regGroupMask. This field is + * ignored for read operations. + * NV2080_CTRL_GPU_REG_OP_TYPE_FB + * This is a fb register group. Write operations are applied to + * registers specified by regGroupMask. This field is + * ignored for read operations. + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD + * This is a graphics context QUAD register group. Operations + * are applied to registers specified by regQuad value. + * regQuad + * This field specifies the quad to be accessed for register regOffsetwhen + * the regType specified is NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD. + * regGroupMask + * This field specifies which registers inside an array should be updated. + * This field is used when regType is one of below: + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP + * NV2080_CTRL_GPU_REG_OP_TYPE_FB + * When regGroupMask is used, the regOffset MUST be the first register in + * an array. + * regSubGroupMask + * This field specifies which registers inside a group should be updated. + * This field is used for updating SM registers when regType is: + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC + * When regSubGroupMask is used, regOffset MUST be the first register in an + * array AND also the first one in sub array. regGroupMask specifies + * TPC(X) and regSubGroupMask specifies SM_CTX_N(Y) + * regStatus + * This field returns the completion status for the associated register + * operation in the form of a bitmask. Possible status values for this + * field are: + * NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS + * This value indicates the operation completed successfully. + * NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OP + * This bit value indicates that the regOp value is not valid. + * NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_TYPE + * This bit value indicates that the regType value is not valid. + * NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OFFSET + * This bit value indicates that the regOffset value is invalid. + * The regOffset value must be within the legal BAR0 range for the + * associated GPU and must target a supported register with a + * supported operation. + * NV2080_CTRL_GPU_REG_OP_STATUS_UNSUPPORTED_OFFSET + * This bit value indicates that the operation to the register + * specified by the regOffset value is not supported for the + * associated GPU. + * NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_MASK + * This bit value indicates that the regTpcMask value is invalid. + * The regTpcMask must be a subset of TPCs that are enabled on the + * associated GPU. + * NV2080_CTRL_GPU_REG_OP_STATUS_NOACCESS + * The caller does not have access to the register at given offset + * regOffset + * This field specifies the register offset to access. The specified + * offset must be a valid BAR0 offset for the associated GPU. + * regValueLo + * This field contains the low 32bits of the register value. + * For read operations, this value returns the current value of the + * register specified by regOffset. For write operations, this field + * specifies the logical OR value applied to the current value + * contained in the register specified by regOffset. + * regValueHi + * This field contains the high 32bits of the register value. + * For read operations, this value returns the current value of the + * register specified by regOffset + 4. For write operations, this field + * specifies the logical OR value applied to the current value + * contained in the register specified by regOffset + 4. + * regAndNMaskLo + * This field contains the mask used to clear a desired field from + * the current value contained in the register specified by regOffsetLo. + * This field is negated and ANDed to this current register value. + * This field is only used for write operations. This field is ignored + * for read operations. + * regAndNMaskHi + * This field contains the mask used to clear a desired field from + * the current value contained in the register specified by regOffsetHi. + * This field is negated and ANDed to this current register value. + * This field is only used for write operations. This field is ignored + * for read operations. + */ +typedef struct NV2080_CTRL_GPU_REG_OP { + NvU8 regOp; + NvU8 regType; + NvU8 regStatus; + NvU8 regQuad; + NvU32 regGroupMask; + NvU32 regSubGroupMask; + NvU32 regOffset; + NvU32 regValueHi; + NvU32 regValueLo; + NvU32 regAndNMaskHi; + NvU32 regAndNMaskLo; +} NV2080_CTRL_GPU_REG_OP; + +/* valid regOp values */ +#define NV2080_CTRL_GPU_REG_OP_READ_32 (0x00000000U) +#define NV2080_CTRL_GPU_REG_OP_WRITE_32 (0x00000001U) +#define NV2080_CTRL_GPU_REG_OP_READ_64 (0x00000002U) +#define NV2080_CTRL_GPU_REG_OP_WRITE_64 (0x00000003U) +#define NV2080_CTRL_GPU_REG_OP_READ_08 (0x00000004U) +#define NV2080_CTRL_GPU_REG_OP_WRITE_08 (0x00000005U) + +/* valid regType values */ +#define NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL (0x00000000U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX (0x00000001U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC (0x00000002U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM (0x00000004U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP (0x00000008U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP (0x00000010U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_FB (0x00000020U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD (0x00000040U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_DEVICE (0x00000080U) + +/* valid regStatus values (note: NvU8 ie, 1 byte) */ +#define NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS (0x00U) +#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OP (0x01U) +#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_TYPE (0x02U) +#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OFFSET (0x04U) +#define NV2080_CTRL_GPU_REG_OP_STATUS_UNSUPPORTED_OP (0x08U) +#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_MASK (0x10U) +#define NV2080_CTRL_GPU_REG_OP_STATUS_NOACCESS (0x20U) + +/* + * NV2080_CTRL_CMD_GPU_EXEC_REG_OPS + * + * This command is used to submit a buffer containing one or more + * NV2080_CTRL_GPU_REG_OP structures for processing. Each entry in the + * buffer specifies a single read or write operation. Each entry is checked + * for validity in an initial pass over the buffer with the results for + * each operation stored in the corresponding regStatus field. Unless + * bNonTransactional flag is set to true, if any invalid entries are found + * during this initial pass then none of the operations are executed. Entries + * are processed in order within each regType with NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL + * entries processed first followed by NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX entries. + * + * hClientTarget + * This parameter specifies the handle of the client that owns the channel + * specified by hChannelTarget. If this parameter is set to 0 then the set + * of channel-specific register operations are applied to all current and + * future channels. + * hChannelTarget + * This parameter specifies the handle of the target channel (or channel + * group) object instance to which channel-specific register operations are + * to be directed. If hClientTarget is set to 0 then this parameter must + * also be set to 0. + * bNonTransactional + * This field specifies if command is non-transactional i.e. if set to + * true, all the valid operations will be executed. + * reserved00 + * This parameter is reserved for future use. It should be initialized to + * zero for correct operation. + * regOpCount + * This field specifies the number of entries on the caller's regOps + * list. + * regOps + * This field specifies a pointer in the caller's address space + * to the buffer from which the desired register information is to be + * retrieved. This buffer must be at least as big as regInfoCount + * multiplied by the size of the NV2080_CTRL_GPU_REG_OP structure. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. When SMC is enabled, this + * is a mandatory parameter. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS (0x20800122U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x22" */ + +typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS { + NvHandle hClientTarget; + NvHandle hChannelTarget; + NvU32 bNonTransactional; + NvU32 reserved00[2]; + NvU32 regOpCount; + NV_DECLARE_ALIGNED(NvP64 regOps, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_ENGINES + * + * Returns a list of supported engine types along with the number of instances + * of each type. Querying with engineList NULL returns engineCount. + * + * engineCount + * This field specifies the number of entries on the caller's engineList + * field. + * engineList + * This field is a pointer to a buffer of NvU32 values representing the + * set of engines supported by the associated subdevice. Refer to cl2080.h + * for the complete set of supported engine types. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_GPU_GET_ENGINES (0x20800123U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID (0x23U) + +typedef struct NV2080_CTRL_GPU_GET_ENGINES_PARAMS { + NvU32 engineCount; + NV_DECLARE_ALIGNED(NvP64 engineList, 8); +} NV2080_CTRL_GPU_GET_ENGINES_PARAMS; + +#define NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 (0x20800170U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID" */ + +/* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */ +#define NV2080_GPU_MAX_ENGINES_LIST_SIZE 0x3EU + +#define NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID (0x70U) + +typedef struct NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS { + NvU32 engineCount; + NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; +} NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST + * + * Returns a list of classes supported by a given engine type. + * + * engineType + * This field specifies the engine type being queried. + * NV2080_CTRL_ENGINE_TYPE_ALLENGINES will return classes + * supported by all engines. + * + * numClasses + * This field specifies the number of classes supported by + * engineType. + * + * classList + * This field is an array containing the list of supported + * classes. Is of type (NvU32*) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST (0x20800124U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID (0x24U) + +typedef struct NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS { + NvU32 engineType; + NvU32 numClasses; + NV_DECLARE_ALIGNED(NvP64 classList, 8); +} NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS; + + +/* + * NV2080_CTRL_CMD_GPU_GET_ENGINE_FAULT_INFO + * + * This command returns the fault properties of the specified engine type. + * + * engineType + * Input parameter. + * This field specifies the engine type being queried. + * Engine type is specified using the NV2080_ENGINE_TYPE_* defines in cl2080.h. + * The list of engines supported by a chip can be got using the + * NV2080_CTRL_CMD_GPU_GET_ENGINES ctrl call. + * + * mmuFaultId + * Output parameter. + * This field returns the MMU fault ID for the specified engine. + * If the engine supports subcontext, this field provides the base fault id. + * + * bSubcontextSupported + * Output parameter. + * Returns TRUE if subcontext faulting is supported by the engine. + * Engine that support subcontext use fault IDs in the range [mmuFaultId, mmuFaultId + maxSubCtx). + * "maxSubctx" can be found using the NV2080_CTRL_FIFO_INFO ctrl call with + * NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP as the index. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_GPU_GET_ENGINE_FAULT_INFO (0x20800125U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID (0x25U) + +typedef struct NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS { + NvU32 engineType; + NvU32 mmuFaultId; + NvBool bSubcontextSupported; +} NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GPU_QUERY_MODE + * + * This command is used to detect the mode of the GPU associated with the + * subdevice. + * + * mode + * This parameter returns the current mode of GPU. Legal values for + * this parameter include: + * NV2080_CTRL_GPU_QUERY_MODE_GRAPHICS_MODE + * The GPU is currently operating in graphics mode. + * NV2080_CTRL_GPU_QUERY_MODE_COMPUTE_MODE + * The GPU is currently operating in compute mode. + * NV2080_CTRL_GPU_QUERY_MODE_UNKNOWN_MODE + * The current mode of the GPU could not be determined. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_GPU_QUERY_MODE (0x20800128U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_MODE_PARAMS_MESSAGE_ID" */ + +/* valid mode parameter values */ +#define NV2080_CTRL_GPU_QUERY_MODE_UNKNOWN_MODE (0x00000000U) +#define NV2080_CTRL_GPU_QUERY_MODE_GRAPHICS_MODE (0x00000001U) +#define NV2080_CTRL_GPU_QUERY_MODE_COMPUTE_MODE (0x00000002U) + +#define NV2080_CTRL_GPU_QUERY_MODE_PARAMS_MESSAGE_ID (0x28U) + +typedef struct NV2080_CTRL_GPU_QUERY_MODE_PARAMS { + NvU32 mode; +} NV2080_CTRL_GPU_QUERY_MODE_PARAMS; + + + +/*! + * NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY + * Data block describing a virtual context buffer to be promoted + * + * gpuPhysAddr [IN] + * GPU Physical Address for the buffer + * gpuVirtAddr [IN] + * GPU Virtual Address for the buffer + * size[IN] + * Size of this virtual context buffer + * physAttr [IN] + * Physical memory attributes (aperture, cacheable) + * bufferId [IN] + * Virtual context buffer type, data type NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_* + * bInitialize [IN] + * Flag indicating that this virtual context buffer should be initialized prior to promotion. + * The client must clear (memset) the buffer to 0x0 prior to initialization. + * Following buffers need initialization: + * 1. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN + * 2. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH + * 3. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP + * 4. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP + * bNonmapped [IN] + * Flag indicating that the virtual address is not to be promoted with this + * call. It is illegal to set this flag and not set bInitialize. + */ +typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY { + NV_DECLARE_ALIGNED(NvU64 gpuPhysAddr, 8); + NV_DECLARE_ALIGNED(NvU64 gpuVirtAddr, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 physAttr; + NvU16 bufferId; + NvU8 bInitialize; + NvU8 bNonmapped; +} NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY; + +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN 0U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM 1U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH 2U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_BUFFER_BUNDLE_CB 3U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PAGEPOOL 4U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_ATTRIBUTE_CB 5U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_RTV_CB_GLOBAL 6U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_POOL 7U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_CTRL_BLK 8U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_FECS_EVENT 9U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP 10U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP 11U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GLOBAL_PRIV_ACCESS_MAP 12U + +#define NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES 16U + +/* + * NV2080_CTRL_CMD_GPU_PROMOTE_CTX + * + * This command is used to promote a Virtual Context + * + * engineType + * Engine Virtual Context is for + * hClient + * Client Handle for hVirtMemory + * ChID + * Hw Channel -- Actually hw index for channel (deprecated) + * hChanClient + * The client handle for hObject + * hObject + * Passed in object handle for either a single channel or a channel group + * hVirtMemory + * Virtual Address handle to map Virtual Context to + * virtAddress + * Virtual Address to map Virtual Context to + * size + * size of the Virtual Context + * entryCount + * Number of valid entries in the promotion entry list + * promoteEntry + * List of context buffer entries to issue promotions for. + * + * When not using promoteEntry, only hVirtMemory or (virtAddress, size) should be + * specified, the code cases based on hVirtMemory(NULL vs non-NULL) so + * if both are specified, hVirtMemory has precedence. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED - The Class does not support version info retrieval + * NV_ERR_INVALID_DEVICE - The Class/Device is not yet ready to provide this info. + * NV_ERR_INVALID_ARGUMENT - Bad/Unknown Class ID specified. + */ +#define NV2080_CTRL_CMD_GPU_PROMOTE_CTX (0x2080012bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID (0x2BU) + +typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS { + NvU32 engineType; + NvHandle hClient; + NvU32 ChID; + NvHandle hChanClient; + NvHandle hObject; + NvHandle hVirtMemory; + NV_DECLARE_ALIGNED(NvU64 virtAddress, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 entryCount; + // C form: NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY promoteEntry[NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES]; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY promoteEntry[NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES], 8); +} NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS; +typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS *PNV2080_CTRL_GPU_PROMOTE_CTX_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_EVICT_CTX + * + * This command is used to evict a Virtual Context + * + * engineType + * Engine Virtual Context is for + * hClient + * Client Handle + * ChID + * Hw Channel -- Actually hw index for channel (deprecated) + * hChanClient + * Client handle for hObject + * hObject + * Passed in object handle for either a single channel or a channel group + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED - The Class does not support version info retrieval + * NV_ERR_INVALID_DEVICE - The Class/Device is not yet ready to provide this info. + * NV_ERR_INVALID_ARGUMENT - Bad/Unknown Class ID specified. + */ +#define NV2080_CTRL_CMD_GPU_EVICT_CTX (0x2080012cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID (0x2CU) + +typedef struct NV2080_CTRL_GPU_EVICT_CTX_PARAMS { + NvU32 engineType; + NvHandle hClient; + NvU32 ChID; + NvHandle hChanClient; + NvHandle hObject; +} NV2080_CTRL_GPU_EVICT_CTX_PARAMS; +typedef struct NV2080_CTRL_GPU_EVICT_CTX_PARAMS *PNV2080_CTRL_GPU_EVICT_CTX_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_INITIALIZE_CTX + * + * This command is used to initialize a Virtual Context. The ctx buffer must be + * cleared (zerod) by the caller prior to invoking this method. + * + * engineType + * Engine Virtual Context is for + * hClient + * Client Handle for the hVirtMemory + * ChID + * Hw channel -- Actually channel index (deprecated) + * hChanClient + * The client handle for hObject + * hObject + * Passed in object handle for either a single channel or a channel group + * hVirtMemory + * Virtual Address where to map Virtual Context to + * physAddress + * Physical offset in FB to use as Virtual Context + * physAttr + * Physical memory attributes + * hDmaHandle + * Dma Handle when using discontiguous context buffers + * index + * Start offset in Virtual DMA Context + * size + * Size of the Virtual Context + * + * Only hVirtMemory or size should be specified, the code cases based on hVirtMemory + * (NULL vs non-NULL) so if both are specified, hVirtMemory has precedence. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED - The Class does not support version info retrieval + * NV_ERR_INVALID_DEVICE - The Class/Device is not yet ready to provide this info. + * NV_ERR_INVALID_ARGUMENT - Bad/Unknown Class ID specified. + */ +#define NV2080_CTRL_CMD_GPU_INITIALIZE_CTX (0x2080012dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID (0x2DU) + +typedef struct NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS { + NvU32 engineType; + NvHandle hClient; + NvU32 ChID; + NvHandle hChanClient; + NvHandle hObject; + NvHandle hVirtMemory; + NV_DECLARE_ALIGNED(NvU64 physAddress, 8); + NvU32 physAttr; + NvHandle hDmaHandle; + NvU32 index; + NV_DECLARE_ALIGNED(NvU64 size, 8); +} NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS; +typedef struct NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS *PNV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS; + +#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE 1:0 +#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_VIDMEM (0x00000000U) +#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_COH_SYS (0x00000001U) +#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_NCOH_SYS (0x00000002U) + +#define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE 2:2 +#define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_YES (0x00000000U) +#define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_NO (0x00000001U) + +/* + * NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX - Tells RM Whether this Ctx buffer needs to + * do a full initialization (Load the golden image). When a context is promoted on a different + * channel than it was originally inited, the client can use this flag to tell RM + * that this is an already inited Context. In such cases RM will update the internal state + * to update the context address and state variables. + */ + +#define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX 3:3 +#define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_NO (0x00000000U) +#define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_YES (0x00000001U) + +/* + * NV2080_CTRL_CMD_CPU_QUERY_ECC_INTR + * Queries the top level ECC PMC PRI register + * TODO remove these parameters, tracked in bug #1975721 + */ +#define NV2080_CTRL_CMD_GPU_QUERY_ECC_INTR (0x2080012eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x2E" */ + +typedef struct NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS { + NvU32 eccIntrStatus; +} NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS; + +/** + * NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS + * + * This command is used to query the ECC status of a GPU by a subdevice + * handle. Please see the NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS + * data structure description below for details on the data reported + * per hardware unit. + * + * units + * Array of structures used to describe per-unit state + * + * flags + * See interface flag definitions below. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + + + +#define NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS (0x2080012fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID" */ + + +#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x00000018U) + + + +// Deprecated do not use +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE 0:0 +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_FILTERED (0x00000000U) +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_RAW (0x00000001U) + +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_FALSE 0U +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_TRUE 1U +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_INDETERMINATE 2U + +/* + * NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS + * + * This structure represents the exception status of a class of per-unit + * exceptions + * + * count + * number of exceptions that have occurred since boot + */ +typedef struct NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS { + NV_DECLARE_ALIGNED(NvU64 count, 8); +} NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS; + +/* + * NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS + * + * This structure represents the per-unit ECC exception status + * + * enabled + * ECC enabled yes/no for this unit + * scrubComplete + * Scrub has completed yes/no. A scrub is performed for some units to ensure + * the checkbits are consistent with the protected data. + * supported + * Whether HW supports ECC in this unit for this GPU + * dbe + * Double bit error (DBE) status. The value returned reflects a counter + * that is monotonic, but can be reset by clients. + * dbeNonResettable (deprecated do not use) + * Double bit error (DBE) status, not client resettable. + * sbe + * Single bit error (SBE) status. The value returned reflects a counter + * that is monotonic, but can be reset by clients. + * sbeNonResettable (deprecated do not use) + * Single bit error (SBE) status, not client resettable. + * + */ +typedef struct NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS { + NvBool enabled; + NvBool scrubComplete; + NvBool supported; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS dbe, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS dbeNonResettable, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS sbe, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS sbeNonResettable, 8); +} NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS; + +/* + * NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS + * + * This structure returns ECC exception status and GPU Fatal Poison for all units + * + * units + * This structure represents ECC exception status for all Units. + * bFatalPoisonError + * Whether GPU Fatal poison error occurred in this GPU. This will be set for Ampere_and_later + * uncorrectableError + * Indicates whether any uncorrectable GR ECC errors have occurred. When + * SMC is enabled, uncorrectableError is only valid when the client is + * subscribed to a partition. Check QUERY_ECC_STATUS_UNC_ERR_* + * flags + * Flags passed by caller. Refer NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_* for details. + * grRouteInfo + * SMC partition information. This input is only valid when SMC is + * enabled on Ampere_and_later. + * + */ +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID (0x2FU) + +typedef struct NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS units[NV2080_CTRL_GPU_ECC_UNIT_COUNT], 8); + NvBool bFatalPoisonError; + NvU8 uncorrectableError; + NvU32 flags; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES + * + * This command sets the compute mode rules for the associated subdevice. The + * default mode is equivalent to NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE. This + * command is available to clients with administrator privileges only. An + * attempt to use this command by a client without administrator privileged + * results in the return of an NV_ERR_INSUFFICIENT_PERMISSIONS status. + * + * rules + * This parameter is used to specify the rules that govern the GPU with + * respect to NV50_COMPUTE objects. Legal values for this parameter include: + * + * NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE + * This mode indicate that no special restrictions apply to the + * allocation of NV50_COMPUTE objects. + * + * NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE + * This mode means that only one instance of NV50_COMPUTE will be + * allowed at a time. This restriction is enforced at each subsequent + * NV50_COMPUTE allocation attempt. Setting this mode will not affect + * any existing compute programs that may be running. For example, + * if this mode is set while three compute programs are running, then + * all of those programs will be allowed to continue running. However, + * until they all finish running, no new NV50_COMPUTE objects may be + * allocated. User-mode clients should treat this as restricting access + * to a NV50_COMPUTE object to a single thread within a process. + * + * NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED + * This mode means that that GPU is not ever allowed to instantiate an + * NV50_COMPUTE object, and thus cannot run any new compute programs. + * This restriction is enforced at each subsequent NV50_COMPUTE object + * allocation attempt. Setting this mode will not affect any existing + * compute programs that may be running. For example, if this mode is + * set while three compute programs are running, then all of those + * programs will be allowed to continue running. However, no new + * NV50_COMPUTE objects may be allocated. + * + * + * NV2080_CTRL_GPU_COMPUTE_MODE_EXCLUSIVE_COMPUTE_PROCESS + * This mode is identical to EXCLUSIVE_COMPUTE, where only one instance + * of NV50_COMPUTE will be allowed at a time. It is separate from + * EXCLUSIVE_COMPUTE to allow user-mode clients to differentiate + * exclusive access to a compute object from a single thread of a + * process from exclusive access to a compute object from all threads + * of a process. User-mode clients should not limit access to a + * NV50_COMPUTE object to a single thread when the GPU is set to + * EXCLUSIVE_COMPUTE_PROCESS. + * + * An invalid rules parameter value results in the return of an + * NV_ERR_INVALID_ARGUMENT status. + * + * flags + * Reserved. Caller should set this field to zero. + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT (if an invalid rule number is provided) + * NV_ERR_INSUFFICIENT_PERMISSIONS (if the user is not the Administrator or superuser) + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES (0x20800130U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID" */ + +/* valid rules parameter values */ +#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE (0x00000000U) +#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE (0x00000001U) +#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED (0x00000002U) +#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE_PROCESS (0x00000003U) + +#define NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID (0x30U) + +typedef struct NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS { + NvU32 rules; + NvU32 flags; +} NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES + * + * This command queries the compute mode rules for the associated subdevice. + * Please see the NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES command, above, for + * details as to what the rules mean. + * + * rules + * Specifies the rules that govern the GPU, with respect to NV50_COMPUTE + * objects. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES (0x20800131U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID (0x31U) + +typedef struct NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS { + NvU32 rules; +} NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION + * + * This command returns the current ECC configuration setting for + * a GPU given its subdevice handle. The value returned is + * the current ECC setting for the GPU stored in non-volatile + * memory on the board. + * + * currentConfiguration + * The current ECC configuration setting. + * + * defaultConfiguration + * The factory default ECC configuration setting. + * + * Please see the NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS command if + * you wish to determine if ECC is currently enabled. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION (0x20800133U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLED (0x00000000U) +#define NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLED (0x00000001U) + +#define NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID (0x33U) + +typedef struct NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS { + NvU32 currentConfiguration; + NvU32 defaultConfiguration; +} NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_SET_ECC_CONFIGURATION + * + * This command changes the ECC configuration setting for a GPU + * given its subdevice handle. The value specified is + * stored in non-volatile memory on the board and will take + * effect with the next GPU reset + * + * newConfiguration + * The new configuration setting to take effect with + * the next GPU reset. + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_SET_ECC_CONFIGURATION (0x20800134U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLE (0x00000000U) +#define NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLE (0x00000001U) + +#define NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID (0x34U) + +typedef struct NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS { + NvU32 newConfiguration; +} NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS + * + * This command resets volatile and/or persistent ECC error + * status information for a GPU given its subdevice + * handle. + * + * statuses + * The ECC error statuses (the current, volatile + * and/or the persistent error counter(s)) to + * be reset by the command. + * flags + * FORCE_PURGE + * Forcibly clean all the ECC InfoROM state if this flag is set + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS (0x20800136U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_ECC_ERROR_STATUS_NONE (0x00000000U) +#define NV2080_CTRL_GPU_ECC_ERROR_STATUS_VOLATILE (0x00000001U) +#define NV2080_CTRL_GPU_ECC_ERROR_STATUS_AGGREGATE (0x00000002U) + +#define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE 0:0 +#define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_FALSE 0U +#define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_TRUE 1U + +#define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID (0x36U) + +typedef struct NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS { + NvU32 statuses; + NvU8 flags; +} NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_FERMI_GPC_INFO + * + * This command returns a mask of enabled GPCs for the associated GPU. + * + * gpcMask + * This parameter returns a mask of enabled GPCs. Each GPC has an ID + * that's equivalent to the corresponding bit position in the mask. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_GPU_GET_FERMI_GPC_INFO (0x20800137U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID (0x37U) + +typedef struct NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS { + NvU32 gpcMask; +} NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_FERMI_TPC_INFO + * + * This command returns a mask of enabled TPCs for a specified GPC. + * + * gpcId + * This parameter specifies the GPC for which TPC information is + * to be retrieved. If the GPC with this ID is not enabled this command + * will return an tpcMask value of zero. + * + * tpcMask + * This parameter returns a mask of enabled TPCs for the specified GPC. + * Each TPC has an ID that's equivalent to the corresponding bit + * position in the mask. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_GPU_GET_FERMI_TPC_INFO (0x20800138U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID (0x38U) + +typedef struct NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS { + NvU32 gpcId; + NvU32 tpcMask; +} NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_FERMI_ZCULL_INFO + * + * This command returns a mask of enabled ZCULLs for a specified GPC. + * + * gpcId + * This parameter specifies the GPC for which ZCULL information is to be + * retrieved. If the GPC with this ID is not enabled this command will + * return an zcullMask value of zero. + * + * zcullMask + * This parameter returns a mask of enabled ZCULLs for the specified GPC. + * Each ZCULL has an ID that's equivalent to the corresponding bit + * position in the mask. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_PARAM_STRUCT + * + * Deprecated: Please use GR based control call + * NV2080_CTRL_CMD_GR_GET_ZCULL_MASK + * + */ +#define NV2080_CTRL_CMD_GPU_GET_FERMI_ZCULL_INFO (0x20800139U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID (0x39U) + +typedef struct NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS { + NvU32 gpcId; + NvU32 zcullMask; +} NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO + * + * If an InfoROM with a valid OEM Board Object is present, this + * command returns relevant information from the object to the + * caller. + * + * The following data are currently reported: + * + * buildDate + * The board's build date (8 digit BCD in format YYYYMMDD). + * + * marketingName + * The board's marketing name (24 ASCII letters e.g. "Quadro FX5800"). + * + * boardSerialNumber + * The board's serial number. + * + * memoryManufacturer + * The board's memory manufacturer ('S'amsung/'H'ynix/'I'nfineon). + * + * memoryDateCode + * The board's memory datecode (LSB justified ASCII field with 0x00 + * denoting empty space). + * + * productPartNumber + * The board's 900 product part number (LSB justified ASCII field with 0x00 + * denoting empty space e.g. "900-21228-0208-200"). + * + * boardRevision + * The board's revision (for e.g. A02, B01) + * + * boardType + * The board's type ('E'ngineering/'P'roduction) + * + * board699PartNumber + * The board's 699 product part number (LSB justified ASCII field with 0x00 + * denoting empty space e.g. "699-21228-0208-200"). + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO (0x2080013fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_GPU_MAX_MARKETING_NAME_LENGTH (0x00000018U) +#define NV2080_GPU_MAX_SERIAL_NUMBER_LENGTH (0x00000010U) +#define NV2080_GPU_MAX_MEMORY_PART_ID_LENGTH (0x00000014U) +#define NV2080_GPU_MAX_MEMORY_DATE_CODE_LENGTH (0x00000006U) +#define NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH (0x00000014U) + +#define NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID (0x3FU) + +typedef struct NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS { + NvU32 buildDate; + NvU8 marketingName[NV2080_GPU_MAX_MARKETING_NAME_LENGTH]; + NvU8 serialNumber[NV2080_GPU_MAX_SERIAL_NUMBER_LENGTH]; + NvU8 memoryManufacturer; + NvU8 memoryPartID[NV2080_GPU_MAX_MEMORY_PART_ID_LENGTH]; + NvU8 memoryDateCode[NV2080_GPU_MAX_MEMORY_DATE_CODE_LENGTH]; + NvU8 productPartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH]; + NvU8 boardRevision[3]; + NvU8 boardType; + NvU8 board699PartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH]; +} NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GPU_GET_ID + * + * This command returns the gpuId of the associated object. + * + * gpuId + * This field return the gpuId. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_ID (0x20800142U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID (0x42U) + +typedef struct NV2080_CTRL_GPU_GET_ID_PARAMS { + NvU32 gpuId; +} NV2080_CTRL_GPU_GET_ID_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE + * + * This command is used to enable or disable GPU debug mode. While this mode + * is enabled, some client RM calls that can potentially timeout return + * NV_ERR_BUSY_RETRY, signalling the client to try again once GPU + * debug mode is disabled. + * + * mode + * This parameter specifies whether GPU debug mode is to be enabled or + * disabled. Possible values are: + * + * NV2080_CTRL_GPU_DEBUG_MODE_ENABLED + * NV2080_CTRL_GPU_DEBUG_MODE_DISABLED + * + * Possible return status values are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE (0x20800143U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID (0x43U) + +typedef struct NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS { + NvU32 mode; +} NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS; + +#define NV2080_CTRL_GPU_DEBUG_MODE_ENABLED (0x00000001U) +#define NV2080_CTRL_GPU_DEBUG_MODE_DISABLED (0x00000002U) + +/* + * NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE + * + * This command is used to query whether debug mode is enabled on the current + * GPU. Please see the description of NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE + * for more details on GPU debug mode. + * + * currentMode + * This parameter returns the state of GPU debug mode for the current GPU. + * Possible values are: + * + * NV2080_CTRL_GPU_DEBUG_MODE_ENABLED + * NV2080_CTRL_GPU_DEBUG_MODE_DISABLED + * + * Possible return status values are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE (0x20800144U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID (0x44U) + +typedef struct NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS { + NvU32 currentMode; +} NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST + * + * Returns a list of engines that can partner or coexist + * when using the target channel or partnership class. + * This list may include all engines (pre-Kepler), or as few + * as 1 engine (Kepler and beyond). + * + * engineType + * This field specifies the target engine type. + * See cl2080.h for a list of valid engines. + * + * partnershipClassId + * This field specifies the target channel + * or partnership class ID. + * An example of such a class is GF100_CHANNEL_GPFIFO. + * + * runqueue + * This field is an index which indicates the runqueue to + * return the list of supported engines for. This is the + * same field as what NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE + * specifies. This is only valid for TSG. + * + * numPartners; + * This field returns the number of + * valid entries in the partnersList array + * + * partnerList + * This field is an array containing the list of supported + * partner engines types, in no particular order, and + * may even be empty (numPartners = 0). + * See cl2080.h for a list of possible engines. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST (0x20800147U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID" */ + +/* this macro specifies the maximum number of partner entries */ +#define NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS (0x00000020U) + +#define NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID (0x47U) + +typedef struct NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS { + NvU32 engineType; + NvU32 partnershipClassId; + NvU32 runqueue; + NvU32 numPartners; + // C form: NvU32 partnerList[NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS]; + NvU32 partnerList[NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS]; +} NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GPU_GET_GID_INFO + * + * This command returns the GPU ID (GID) string for the associated + * GPU. This value can be useful for GPU identification and security + * system validation. + * + * The GPU ID is a SHA-1 based 16 byte ID, formatted as a 32 character + * hexadecimal string as "GPU-%08x-%04x-%04x-%04x-%012x" (the + * canonical format of a UUID) + * + * The GPU IDs are generated using the ECID, PMC_BOOT_0, and + * PMC_BOOT_42 of the GPU as the hash message. + * + * index + * (Input) "Select which GID set to get." Or so the original documentation + * said. In reality, there is only one GID per GPU, and the implementation + * completely ignores this parameter. You can too. + * + * flags (Input) The _FORMAT* flags designate ascii or binary format. Binary + * format returns the raw bytes of either the 16-byte SHA-1 ID or the + * 32-byte SHA-256 ID. + * + * The _TYPE* flags needs to specify the _SHA1 type. + * + * length + * (Output) Actual GID length, in bytes. + * + * data[NV2080_BUS_MAX_GID_LENGTH] + * (Output) Result buffer: the GID itself, in a format that is determined by + * the "flags" field (described above). + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_GPU_GET_GID_INFO (0x2080014aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID" */ + +/* maximum possible number of bytes of GID information returned */ +#define NV2080_GPU_MAX_GID_LENGTH (0x000000100ULL) + +/* maximum possible number of bytes of GID information returned if given the BINARY and SHA1 flags */ +#define NV2080_GPU_MAX_SHA1_BINARY_GID_LENGTH (0x000000010ULL) + +#define NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID (0x4AU) + +typedef struct NV2080_CTRL_GPU_GET_GID_INFO_PARAMS { + NvU32 index; + NvU32 flags; + NvU32 length; + NvU8 data[NV2080_GPU_MAX_GID_LENGTH]; +} NV2080_CTRL_GPU_GET_GID_INFO_PARAMS; + +/* valid flags values */ +#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT 1:0 +#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_ASCII (0x00000000U) +#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_BINARY (0x00000002U) + +#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE 2:2 +#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE_SHA1 (0x00000000U) + +/* + * NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION + * + * This command can be used by clients to retrieve the version of an + * InfoROM object. + * + * objectType + * This parameter specifies the name of the InfoROM object whose version + * should be queried. + * + * version + * This parameter returns the version of the InfoROM object specified by + * the objectType parameter. + * + * subversion + * This parameter returns the subversion of the InfoROM object specified + * by the objectType parameter. + * + * Possible return status values: + * NV_OK + * NV_ERR_STATE_IN_USE + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION (0x2080014bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_INFOROM_OBJ_TYPE_LEN 3U + +#define NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID (0x4BU) + +typedef struct NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS { + char objectType[NV2080_CTRL_GPU_INFOROM_OBJ_TYPE_LEN]; + NvU8 version; + NvU8 subversion; +} NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS; + + +/* + * NV2080_CTRL_CMD_SET_GPU_OPTIMUS_INFO + * + * This command will specify that system is Optimus enabled. + * + * isOptimusEnabled + * Set NV_TRUE if system is Optimus enabled. + * + * Possible status return values are: + * NV_OK + */ +#define NV2080_CTRL_CMD_SET_GPU_OPTIMUS_INFO (0x2080014cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID (0x4CU) + +typedef struct NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS { + NvBool isOptimusEnabled; +} NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_IP_VERSION + * + * Will return the IP VERSION on the given engine for engines that support + * this capability. + * + * targetEngine + * This parameter specifies the target engine type to query for IP_VERSION. + * + * ipVersion + * This parameter returns the IP VERSION read from the unit's IP_VER + * register. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_GPU_GET_IP_VERSION (0x2080014dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID (0x4DU) + +typedef struct NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS { + NvU32 targetEngine; + NvU32 ipVersion; +} NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS; + +#define NV2080_CTRL_GPU_GET_IP_VERSION_DISPLAY (0x00000001U) +#define NV2080_CTRL_GPU_GET_IP_VERSION_HDACODEC (0x00000002U) +#define NV2080_CTRL_GPU_GET_IP_VERSION_PMGR (0x00000003U) +#define NV2080_CTRL_GPU_GET_IP_VERSION_PPWR_PMU (0x00000004U) +#define NV2080_CTRL_GPU_GET_IP_VERSION_DISP_FALCON (0x00000005U) + + + +/* + * NV2080_CTRL_CMD_GPU_ID_ILLUM_SUPPORT + * + * This command returns an indicator which reports if the specified Illumination control + * attribute is supported + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_GPU_ILLUM_ATTRIB_LOGO_BRIGHTNESS 0U +#define NV2080_CTRL_GPU_ILLUM_ATTRIB_SLI_BRIGHTNESS 1U +#define NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT (0x20800153U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID (0x53U) + +typedef struct NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS { + NvU32 attribute; + NvBool bSupported; +} NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_ID_ILLUM + * + * This command returns the current value of the specified Illumination control attribute. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_ILLUM (0x20800154U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x54" */ + +typedef struct NV2080_CTRL_CMD_GPU_ILLUM_PARAMS { + NvU32 attribute; + NvU32 value; +} NV2080_CTRL_CMD_GPU_ILLUM_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_SET_ID_ILLUM + * + * This command sets a new valuefor the specified Illumination control attribute. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_SET_ILLUM (0x20800155U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x55" */ + +/* + * NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION + * + * This command can be used by clients to retrieve the version of the entire + * InfoROM image. + * + * version + * This parameter returns the version of the InfoROM image as a NULL- + * terminated character string of the form "XXXX.XXXX.XX.XX" where each + * 'X' is an integer character. + * + * Possible status return values are: + * NVOS_STATUS_SUCCES + * NV_ERR_INSUFFICIENT_RESOURCES + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_DATA + */ +#define NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION (0x20800156U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_INFOROM_IMAGE_VERSION_LEN 16U + +#define NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID (0x56U) + +typedef struct NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS { + NvU8 version[NV2080_CTRL_GPU_INFOROM_IMAGE_VERSION_LEN]; +} NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT + * + * This command returns whether or not ECC is supported via the InfoROM. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT (0x20800157U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x57" */ + +/* + * NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION + * + * This structure contains information about a single physical bridge. + * + * fwVersion + * This field specifies Firmware Version of the bridge stored in + * bridge EEPROM. + * oemVersion + * This field specifies Oem Version of the firmware stored in + * bridge EEPROM. + * siliconRevision + * This field contains the silicon revision of the bridge hardware. + * It is set by the chip manufacturer. + * hwbcResourceType + * This field specifies the hardware broadcast resource type. + * Value denotes the kind of bridge - PLX or BR04 + * + */ + +typedef struct NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS { + NvU32 fwVersion; + NvU8 oemVersion; + NvU8 siliconRevision; + NvU8 hwbcResourceType; +} NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO + * + * This command returns physical bridge information in the system. + * Information consists of bridgeCount and a list of bridgeId's. + * The bridge Id's are used by NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION + * to get firmware version, oem version and silicon revision info. + * + * bridgeCount + * This field specifies the number of physical brides present + * in the system. + * hPhysicalBridges + * This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE. + * In this array, the bridge Id's are stored. + * bridgeList + * This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE. + * In this array, the bridge version details are stored. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO (0x2080015aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MAX_PHYSICAL_BRIDGE (100U) +#define NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID (0x5AU) + +typedef struct NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS { + NvU8 bridgeCount; + NvHandle hPhysicalBridges[NV2080_CTRL_MAX_PHYSICAL_BRIDGE]; + NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS bridgeList[NV2080_CTRL_MAX_PHYSICAL_BRIDGE]; +} NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS; + +/* + * NV2080_CTRL_GPU_BRIDGE_VERSION + * + * This structure contains information about a single physical bridge. + * + * bus + * This field specifies the bus id of the bridge. + * device + * This field specifies the device id of the bridge. + * func + * This field specifies the function id of the bridge. + * oemVersion + * This field specifies Oem Version of the firmware stored in + * bridge EEPROM. + * siliconRevision + * This field contains the silicon revision of the bridge hardware. + * It is set by the chip manufacturer. + * hwbcResourceType + * This field specifies the hardware broadcast resource type. + * Value denotes the kind of bridge - PLX or BR04 + * domain + * This field specifies the respective domain of the PCI device. + * fwVersion + * This field specifies Firmware Version of the bridge stored in + * bridge EEPROM. + * + * If (fwVersion, oemVersion, siliconRevision) == 0, it would mean that RM + * was unable to fetch the value from the bridge device. + * + */ + +typedef struct NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS { + NvU8 bus; + NvU8 device; + NvU8 func; + NvU8 oemVersion; + NvU8 siliconRevision; + NvU8 hwbcResourceType; + NvU32 domain; + NvU32 fwVersion; +} NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU + * + * This command returns information about all the upstream bridges of the GPU. + * Information consists of bridge firmware version and its bus topology. + * + * bridgeCount + * This field specifies the number of physical brides present + * in the system. + * physicalBridgeIds + * This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE. + * In this array, the bridge Ids are stored. + * bridgeList + * This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE. + * In this array, the bridge version details are stored. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU (0x2080015bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID (0x5BU) + +typedef struct NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS { + NvU8 bridgeCount; + NvU32 physicalBridgeIds[NV2080_CTRL_MAX_PHYSICAL_BRIDGE]; + NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS bridgeList[NV2080_CTRL_MAX_PHYSICAL_BRIDGE]; +} NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS + * + * This command is used to query the status of the HW scrubber. If a scrub is + * in progress then the range which is being scrubbed is also reported back. + * + * scrubberStatus + * Reports the status of the scrubber unit - running/idle. + * + * remainingtimeMs + * If scrubbing is going on, reports the remaining time in milliseconds + * required to finish the scrub. + * + * scrubStartAddr + * This parameter reports the start address of the ongoing scrub if scrub + * is going on, otherwise reports the start addr of the last finished scrub + * + * scrubEndAddr + * This parameter reports the end address of the ongoing scrub if scrub + * is going on, otherwise reports the end addr of the last finished scrub. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS (0x2080015fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID (0x5FU) + +typedef struct NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS { + NvU32 scrubberStatus; + NvU32 remainingTimeMs; + NV_DECLARE_ALIGNED(NvU64 scrubStartAddr, 8); + NV_DECLARE_ALIGNED(NvU64 scrubEndAddr, 8); +} NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS; + +/* valid values for scrubber status */ +#define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_RUNNING (0x00000000U) +#define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_IDLE (0x00000001U) + +/* + * NV2080_CTRL_CMD_GPU_GET_VPR_CAPS + * + * This command is used to query the VPR capability information for a + * GPU. If VPR is supported, the parameters are filled accordingly. + * The addresses returned are all physical addresses. + * + * minStartAddr + * Returns the minimum start address that can be possible for VPR. + * + * maxEndAddr + * Returns the maximum end address that can be possible for VPR. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_GPU_GET_VPR_CAPS (0x20800160U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID (0x60U) + +typedef struct NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 minStartAddr, 8); + NV_DECLARE_ALIGNED(NvU64 maxEndAddr, 8); +} NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GPU_HANDLE_GPU_SR + * + * Communicates to RM to handle GPU Surprise Removal + * Called from client when it receives SR IRP from OS + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + */ +#define NV2080_CTRL_CMD_GPU_HANDLE_GPU_SR (0x20800167U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x67" */ + + +/* + * NV2080_CTRL_CMD_GPU_GET_PES_INFO + * + * This command provides the PES count and mask of enabled PES for a + * specified GPC. It also returns the TPC to PES mapping information + * for a given GPU. + * + * gpcId[IN] + * This parameter specifies the GPC for which PES information is to be + * retrieved. If the GPC with this ID is not enabled this command will + * return an activePesMask of zero + * + * numPesInGpc[OUT] + * This parameter returns the number of PES in this GPC. + * + * activePesMask[OUT] + * This parameter returns a mask of enabled PESs for the specified GPC. + * Each PES has an ID that is equivalent to the corresponding bit position + * in the mask. + * + * maxTpcPerGpcCount[OUT] + * This parameter returns the max number of TPCs in a GPC. + * + * tpcToPesMap[OUT] + * This array stores the TPC to PES mappings. The value at tpcToPesMap[tpcIndex] + * is the index of the PES it belongs to. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_PES_INFO (0x20800168U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_GPU_GET_PES_INFO_MAX_TPC_PER_GPC_COUNT 10U + +#define NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID (0x68U) + +typedef struct NV2080_CTRL_GPU_GET_PES_INFO_PARAMS { + NvU32 gpcId; + NvU32 numPesInGpc; + NvU32 activePesMask; + NvU32 maxTpcPerGpcCount; + NvU32 tpcToPesMap[NV2080_CTRL_CMD_GPU_GET_PES_INFO_MAX_TPC_PER_GPC_COUNT]; +} NV2080_CTRL_GPU_GET_PES_INFO_PARAMS; + +/* NV2080_CTRL_CMD_GPU_GET_OEM_INFO + * + * If an InfoROM with a valid OEM Object is present, this + * command returns relevant information from the object to the + * caller. + * + * oemInfo + * This array stores information specifically for OEM use + * (e.g. "their own serial number", "lot codes", etc) + * "The byte definition is up to the OEM" + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_GPU_GET_OEM_INFO (0x20800169U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_GPU_MAX_OEM_INFO_LENGTH (0x000001F8U) + +#define NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID (0x69U) + +typedef struct NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS { + NvU8 oemInfo[NV2080_GPU_MAX_OEM_INFO_LENGTH]; +} NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS; + +/* NV2080_CTRL_CMD_GPU_PROCESS_POST_GC6_EXIT_TASKS + * + * Complete any pending tasks the need to be run after GC6 exit is complete at OS/KMD level + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_READY + */ +#define NV2080_CTRL_CMD_GPU_PROCESS_POST_GC6_EXIT_TASKS (0x2080016aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x6A" */ + +/* + * NV2080_CTRL_CMD_GPU_GET_VPR_INFO + * + * This command is used to query the VPR information for a GPU. + * The following VPR related information can be queried by selecting the queryType: + * 1. The current VPR range. + * 2. The max VPR range ever possible on this GPU. + * + * queryType [in] + * This input parameter is used to select the type of information to query. + * Possible values for this parameter are: + * 1. NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS: Use this to query the + * max VPR range ever possible on this GPU. + * 2. NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE: Use this to query + * the current VPR range on this GPU. + * + * bVprEnabled [out] + * For query type "NV2080_CTRL_GPU_GET_VPR_INFO_CUR_RANGE", this parameter + * returns if VPR is currently enabled or not. + * + * vprStartAddress [out] + * For NV2080_CTRL_GPU_GET_VPR_INFO_CAPS, it returns minimum allowed VPR start address. + * For NV2080_CTRL_GPU_GET_VPR_INFO_RANGE, it returns current VPR start address. + * + * vprEndAddress [out] + * For NV2080_CTRL_GPU_GET_VPR_INFO_CAPS, it returns maximum allowed VPR end address. + * For NV2080_CTRL_GPU_GET_VPR_INFO_RANGE, it returns current VPR end address. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_VPR_INFO (0x2080016bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID" */ + + +typedef enum NV2080_CTRL_VPR_INFO_QUERY_TYPE { + NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS = 0, + NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE = 1, +} NV2080_CTRL_VPR_INFO_QUERY_TYPE; + +#define NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID (0x6BU) + +typedef struct NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS { + NV2080_CTRL_VPR_INFO_QUERY_TYPE queryType; + NvBool bIsVprEnabled; + NV_DECLARE_ALIGNED(NvU64 vprStartAddressInBytes, 8); + NV_DECLARE_ALIGNED(NvU64 vprEndAddressInBytes, 8); +} NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_ENCODER_CAPACITY + * + * This command is used to query the encoder capacity of the GPU. + * + * queryType [in] + * This input parameter is used to select the type of information to query. + * Possible values for this parameter are: + * 1. NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264: Use this to query the + * H.264 encoding capacity on this GPU. + * 2. NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC: Use this to query the + * H.265/HEVC encoding capacity on this GPU. + * + * encoderCapacity [out] + * Encoder capacity value from 0 to 100. Value of 0x00 indicates encoder performance + * may be minimal for this GPU and software should fall back to CPU-based encode. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_GPU_GET_ENCODER_CAPACITY (0x2080016cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE { + NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264 = 0, + NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC = 1, +} NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE; + +#define NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID (0x6CU) + +typedef struct NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS { + NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE queryType; + NvU32 encoderCapacity; +} NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS; + +/* + * NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS + * + * This command is used to retrieve the GPU's count of encoder sessions, + * trailing average FPS and encode latency over all active sessions. + * + * encoderSessionCount + * This field specifies count of all active encoder sessions on this GPU. + * + * averageEncodeFps + * This field specifies the average encode FPS for this GPU. + * + * averageEncodeLatency + * This field specifies the average encode latency in microseconds for this GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS (0x2080016dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID (0x6DU) + +typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS { + NvU32 encoderSessionCount; + NvU32 averageEncodeFps; + NvU32 averageEncodeLatency; +} NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS; + +#define NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES 0x200U // 512 entries. + +/* + * NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO + * + * This command returns NVENC software sessions information for the associate GPU. + * Request to retrieve session information use a list of one or more + * NV2080_CTRL_NVENC_SW_SESSION_INFO structures. + * + * sessionInfoTblEntry + * This field specifies the number of entries on the that are filled inside + * sessionInfoTbl. Max value of this field once returned from RM would be + * NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES, + * + * sessionInfoTbl + * This field specifies a pointer in the caller's address space + * to the buffer into which the NVENC session information is to be returned. + * When buffer is NULL, RM assume that client is querying sessions count value + * and return the current encoder session counts in sessionInfoTblEntry field. + * To get actual buffer data, client should allocate sessionInfoTbl of size + * NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES multiplied by the + * size of the NV2080_CTRL_NVENC_SW_SESSION_INFO structure. RM will fill the + * current session data in sessionInfoTbl buffer and then update the + * sessionInfoTblEntry to reflect current session count value. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NO_MEMORY + * NV_ERR_INVALID_LOCK_STATE + * NV_ERR_INVALID_ARGUMENT + */ + +typedef struct NV2080_CTRL_NVENC_SW_SESSION_INFO { + NvU32 processId; + NvU32 subProcessId; + NvU32 sessionId; + NvU32 codecType; + NvU32 hResolution; + NvU32 vResolution; + NvU32 averageEncodeFps; + NvU32 averageEncodeLatency; +} NV2080_CTRL_NVENC_SW_SESSION_INFO; + +#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS_MESSAGE_ID (0x6EU) + +typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS { + NvU32 sessionInfoTblEntry; + NV_DECLARE_ALIGNED(NvP64 sessionInfoTbl, 8); +} NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS; + +#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO (0x2080016eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR + * + * The command sets fabric base address which represents top N bits of a + * peer memory address. These N bits will be used to index NvSwitch routing + * tables to forward peer memory accesses to associated GPUs. + * + * The command is available to clients with administrator privileges only. + * An attempt to use this command by a client without administrator privileged + * results in the return of NV_ERR_INSUFFICIENT_PERMISSIONS status. + * + * The command allows to set fabricAddr once in a lifetime of a GPU. A GPU must + * be destroyed in order to re-assign a different fabricAddr. An attempt to + * re-assign address without destroying a GPU would result in the return of + * NV_ERR_STATE_IN_USE status. + * + * fabricBaseAddr[IN] + * - An address with at least 32GB alignment. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_NOT_SUPPORTED + * NV_ERR_STATE_IN_USE + */ + +#define NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID (0x6FU) + +typedef struct NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS { + NV_DECLARE_ALIGNED(NvU64 fabricBaseAddr, 8); +} NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS; + +#define NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR (0x2080016fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT + * + * The command will trigger the specified interrupt on the host from a guest. + * + * handle[IN] + * - An opaque handle that will be passed in along with the interrupt + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS_MESSAGE_ID (0x72U) + +typedef struct NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS { + NvU32 handle; +} NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS; + +#define NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT (0x20800172U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS + * + * This control call is to query the status of gpu function registers + * + * statusMask[IN] + * - Input mask of required status registers + * xusbData[OUT] + * - data from querying XUSB status register + * ppcData[OUT] + * - data from querying PPC status register + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + + + +#define NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS_MESSAGE_ID (0x73U) + +typedef struct NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS { + NvU32 statusMask; + NvU32 xusbData; + NvU32 ppcData; +} NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS; + +#define NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS (0x20800173U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_GPU_PARTITION_SPAN + * + * This struct represents the span of a memory partition, which represents the + * slices a given partition occupies (or may occupy) within a fixed range which + * is defined per-chip. A partition containing more resources will cover more + * GPU slices and therefore cover a larger span. + * + * lo + * - The starting unit of this span, inclusive + * + * hi + * - The ending unit of this span, inclusive + * + */ +typedef struct NV2080_CTRL_GPU_PARTITION_SPAN { + NV_DECLARE_ALIGNED(NvU64 lo, 8); + NV_DECLARE_ALIGNED(NvU64 hi, 8); +} NV2080_CTRL_GPU_PARTITION_SPAN; + +/* + * NV2080_CTRL_GPU_SET_PARTITION_INFO + * + * This command partitions a GPU into different SMC-Memory partitions. + * The command will configure HW partition table to create work and memory + * isolation. + * + * The command is available to clients with administrator privileges only. + * An attempt to use this command by a client without administrator privileged + * results in the return of NV_ERR_INSUFFICIENT_PERMISSIONS status. + * + * The command allows partitioning an invalid partition only. An attempt to + * re-partition a valid partition will resule in NV_ERR_STATE_IN_USE. + * Repartitioning can be done only if a partition has been destroyed/invalidated + * before re-partitioning. + * + * swizzId[IN/OUT] + * - PartitionID associated with a newly created partition. Input in case + * of partition invalidation. + * + * partitionFlag[IN] + * - Flags to determine if GPU is requested to be partitioned in FULL, + * HALF, QUARTER or ONE_EIGHTHED and whether the partition requires + * any additional resources. + * When flags include NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA + * partition will be created with at least one video decode, jpeg and + * optical flow engines. This flag is valid only for partitions with + * a single GPC. + * + * bValid[IN] + * - NV_TRUE if creating a partition. NV_FALSE if destroying a partition. + * + * placement[IN] + * - Optional placement span to allocate the partition into. Valid + * placements are returned from NV2080_CTRL_CMD_GPU_GET_PARTITION_CAPACITY. + * The partition flag NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN must + * be set for this parameter to be used. If the flag is set and the given + * placement is not valid, an error will be returned. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_NOT_SUPPORTED + * NV_ERR_STATE_IN_USE + */ +typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO { + NvU32 swizzId; + NvU32 partitionFlag; + NvBool bValid; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN placement, 8); +} NV2080_CTRL_GPU_SET_PARTITION_INFO; + +#define PARTITIONID_INVALID NV2080_CTRL_GPU_PARTITION_ID_INVALID +#define NV2080_CTRL_GPU_PARTITION_ID_INVALID 0xFFFFFFFFU +#define NV2080_CTRL_GPU_MAX_PARTITIONS 0x00000008U +#define NV2080_CTRL_GPU_MAX_PARTITION_IDS 0x00000009U +#define NV2080_CTRL_GPU_MAX_SMC_IDS 0x00000008U +#define NV2080_CTRL_GPU_MAX_GPC_PER_SMC 0x0000000cU +#define NV2080_CTRL_GPU_MAX_CE_PER_SMC 0x00000008U + +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE 1:0 +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL 0x00000000U +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF 0x00000001U +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER 0x00000002U +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH 0x00000003U +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE 4U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE 4:2 +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL 0x00000000U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF 0x00000001U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF 0x00000002U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER 0x00000003U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER 0x00000004U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH 0x00000005U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE 6U + + +#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 8U +#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA 30:30 +#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE 0U +#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE 1U +#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN 31:31 +#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE 0U +#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE 1U + +// TODO XXX Bug 2657907 Remove these once clients update +#define NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _FULL) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _FULL)) +#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _HALF) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _HALF)) +#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _HALF) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _MINI_HALF)) +#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _QUARTER) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _QUARTER)) +#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _EIGHTH) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _EIGHTH)) + +#define NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID (0x74U) + +typedef struct NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS { + NvU32 partitionCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_SET_PARTITION_INFO partitionInfo[NV2080_CTRL_GPU_MAX_PARTITIONS], 8); +} NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS; + +#define NV2080_CTRL_CMD_GPU_SET_PARTITIONS (0x20800174U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_GPU_GET_PARTITION_INFO + * + * This command gets the partition information for requested partitions. + * If GPU is not partitioned, the control call will return NV_ERR_NOT_SUPPORTED. + * + * The command will can return global partition information as well as single + * partition information if global flag is not set. + * In bare-metal user-mode can request all partition info while in virtualization + * plugin should make an RPC with swizzId which is assigned to the requesting + * VM. + * + * swizzId[IN] + * - HW Partition ID associated with the requested partition. + * + * partitionFlag[OUT] + * - partitionFlag that was provided during partition creation. + * + * grEngCount[OUT] + * - Number of SMC engines/GR engines allocated in partition + * GrIDs in a partition will always start from 0 and end at grEngCount-1 + * + * veidCount[OUT] + * - VEID Count assigned to a partition. These will be divided across + * SMC engines once CONFIGURE_PARTITION call has been made. The current + * algorithm is to assign veidPerGpc * gpcCountPerSmc to a SMC engine. + * + * smCount[OUT] + * - SMs assigned to a partition. + * + * ceCount[OUT] + * - Copy Engines assigned to a partition. + * + * nvEncCount[OUT] + * - NvEnc Engines assigned to a partition. + * + * nvDecCount[OUT] + * - NvDec Engines assigned to a partition. + * + * nvJpgCount[OUT] + * - NvJpg Engines assigned to a partition. + * + * gpcCount[OUT] + * - Max GPCs assigned to a partition, including the GfxCapable ones. + * + * virtualGpcCount[OUT] + * - Virtualized GPC count assigned to partition + * + * gfxGpcCount[OUT] + * - Max GFX GPCs assigned to a partition. This is a subset of the GPCs incuded in gpcCount. + * + * gpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT] + * - GPC count associated with every valid SMC/Gr, including the GPCs capable of GFX + * + * virtualGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT] + * - Virtualized GPC count associated with every valid SMC/Gr, including the GPCs capable of GFX + * + * gfxGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT] + * - GFX GPC count associated with every valid SMC/Gr. This is a subset of the GPCs included in gfxGpcCount + * + * veidsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT] + * - VEID count associated with every valid SMC. VEIDs within this SMC + * will start from 0 and go till veidCount[SMC_ID] - 1. + * + * span[OUT] + * - The span covered by this partition + * + * bValid[OUT] + * - NV_TRUE if partition is valid else NV_FALSE. + * + * bPartitionError[OUT] + * - NV_TRUE if partition had poison error which requires drain and reset + * else NV_FALSE. + * + * validCTSIdMask[OUT] + * - Mask of CTS IDs usable by this partition, not reflecting current allocations + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_NOT_SUPPORTED + */ +typedef struct NV2080_CTRL_GPU_GET_PARTITION_INFO { + NvU32 swizzId; + NvU32 partitionFlag; + NvU32 grEngCount; + NvU32 veidCount; + NvU32 smCount; + NvU32 ceCount; + NvU32 nvEncCount; + NvU32 nvDecCount; + NvU32 nvJpgCount; + NvU32 nvOfaCount; + NvU32 gpcCount; + NvU32 virtualGpcCount; + NvU32 gfxGpcCount; + NvU32 gpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NvU32 virtualGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NvU32 gfxGpcPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NvU32 veidsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NV_DECLARE_ALIGNED(NvU64 memSize, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN span, 8); + NvBool bValid; + NvBool bPartitionError; + NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8); +} NV2080_CTRL_GPU_GET_PARTITION_INFO; + +/* + * NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS + * + * queryPartitionInfo[IN] + * - Max sized array of NV2080_CTRL_GPU_GET_PARTITION_INFO to get partition + * Info + * + * bGetAllPartitionInfo[In] + * - Flag to get all partitions info. Only root client will receive all + * partition's info. Non-Root clients should not use this flag + * + * validPartitionCount[Out] + * - Valid partition count which has been filled by RM as part of the call + * + */ +#define NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS_MESSAGE_ID (0x75U) + +typedef struct NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_GET_PARTITION_INFO queryPartitionInfo[NV2080_CTRL_GPU_MAX_PARTITIONS], 8); + NvU32 validPartitionCount; + NvBool bGetAllPartitionInfo; +} NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS; + +#define NV2080_CTRL_CMD_GPU_GET_PARTITIONS (0x20800175U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_GPU_CONFIGURE_PARTITION + * + * This command configures a partition by associating GPCs with SMC Engines + * available in that partition. Engines which are to have GPCs assigned to them + * shall not already have any GPCs assigned to them. It is not valid to both + * assign GPCs and remove GPCs as part of a single call to this function. + * + * swizzId[IN] + * - PartitionID for configuring partition. If partition has a valid + * context created, then configuration is not allowed. + * + * gpcCountPerSmcEng[IN] + * - Number of GPCs expected to be configured per SMC. Supported + * configurations are 0, 1, 2, 4 or 8. "0" means a particular SMC + * engine will be disabled with no GPC connected to it. + * + * updateSmcEngMask[IN] + * - Mask tracking valid entries of gpcCountPerSmcEng. A value of + * 0 in bit index i indicates that engine i will keep its current + * configuration. + * + * bUseAllGPCs[IN] + * - Flag specifying alternate configuration mode, indicating that in + * swizzid 0 only, all non-floorswept GPCs should be connected to the + * engine indicated by a raised bit in updateSmcEngMask. Only a single + * engine may be targeted by this operation. The gpcCountPerSmcEng + * parameter should not be used with this flag. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_INSUFFICIENT_RESOURCES + * NV_ERR_NOT_SUPPORTED + * NV_ERR_STATE_IN_USE + */ +#define NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION (0x20800176U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID (0x76U) + +typedef struct NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS { + NvU32 swizzId; + NvU32 gpcCountPerSmcEng[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NvU32 updateSmcEngMask; + NvBool bUseAllGPCs; +} NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS; + + +/* + * NV2080_CTRL_GPU_FAULT_PACKET + * + * This struct represents a GMMU fault packet. + * + */ +#define NV2080_CTRL_GPU_FAULT_PACKET_SIZE 32U +typedef struct NV2080_CTRL_GPU_FAULT_PACKET { + NvU8 data[NV2080_CTRL_GPU_FAULT_PACKET_SIZE]; +} NV2080_CTRL_GPU_FAULT_PACKET; + +/* + * NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT + * + * This command reports a nonreplayable fault packet to RM. + * It is only used by UVM. + * + * pFaultPacket[IN] + * - A fault packet that will be later cast to GMMU_FAULT_PACKET *. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_GPU_REPORT_NON_REPLAYABLE_FAULT (0x20800177U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID (0x77U) + +typedef struct NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS { + NV2080_CTRL_GPU_FAULT_PACKET faultPacket; +} NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU + * + * This command is similar to NV2080_CTRL_CMD_GPU_EXEC_REG_OPS, except it is used + * by the VGPU plugin client only. This command provides access to the subset of + * privileged registers. + * + * See confluence page "vGPU UMED Security" for details. + * + */ +#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU (0x20800178U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x78" */ + +/* + * NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE + * + * This command returns the runlist pri base of the specified engine(s). + * + * engineList + * Input array. + * This array specifies the engines being queried for information. + * The list of engines supported by a chip can be fetched using the + * NV2080_CTRL_CMD_GPU_GET_ENGINES/GET_ENGINES_V2 ctrl call. + * + * runlistPriBase + * Output array. + * Returns the runlist pri base for the specified engines + * Else, will return _NULL when the input is a NV2080_ENGINE_TYPE_NULL + * and will return _ERROR when the control call fails due to an invalid argument + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE (0x20800179U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID (0x79U) + +typedef struct NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS { + NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; + NvU32 runlistPriBase[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; +} NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS; + +#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_NULL (0xFFFFFFFFU) +#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_ERROR (0xFFFFFFFBU) + +/* + * NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID + * + * This command returns the host hardware defined engine ID of the specified engine(s). + * + * engineList + * Input array. + * This array specifies the engines being queried for information. + * The list of engines supported by a chip can be fetched using the + * NV2080_CTRL_CMD_GPU_GET_ENGINES/GET_ENGINES_V2 ctrl call. + * + * hwEngineID + * Output array. + * Returns the host hardware engine ID(s) for the specified engines + * Else, will return _NULL when the input is a NV2080_ENGINE_TYPE_NULL + * and will return _ERROR when the control call fails due to an invalid argument + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID (0x2080017aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID (0x7AU) + +typedef struct NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS { + NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; + NvU32 hwEngineID[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; +} NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS; + +#define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_NULL (0xFFFFFFFFU) +#define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_ERROR (0xFFFFFFFBU) + +/* + * NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS + * + * This command is used to retrieve the GPU's count of FBC sessions, + * average FBC calls and FBC latency over all active sessions. + * + * sessionCount + * This field specifies count of all active fbc sessions on this GPU. + * + * averageFPS + * This field specifies the average frames captured. + * + * averageLatency + * This field specifies the average FBC latency in microseconds. + * + * Possible status values returned are : + * NV_OK + * NV_ERR_INVALID_ARGUMENT +*/ +#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS (0x2080017bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID (0x7BU) + +typedef struct NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS { + NvU32 sessionCount; + NvU32 averageFPS; + NvU32 averageLatency; +} NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS; + +/* +* NV2080_CTRL_NVFBC_SW_SESSION_INFO +* +* processId[OUT] +* Process id of the process owning the NvFBC session. +* On VGX host, this will specify the vGPU plugin process id. +* subProcessId[OUT] +* Process id of the process owning the NvFBC session if the +* session is on VGX guest, else the value is zero. +* vgpuInstanceId[OUT] +* vGPU on which the process owning the NvFBC session +* is running if session is on VGX guest, else +* the value is zero. +* sessionId[OUT] +* Unique session id of the NvFBC session. +* sessionType[OUT] +* Type of NvFBC session. +* displayOrdinal[OUT] +* Display identifier associated with the NvFBC session. +* sessionFlags[OUT] +* One or more of NV2080_CTRL_NVFBC_SESSION_FLAG_xxx. +* hMaxResolution[OUT] +* Max horizontal resolution supported by the NvFBC session. +* vMaxResolution[OUT] +* Max vertical resolution supported by the NvFBC session. +* hResolution[OUT] +* Horizontal resolution requested by caller in grab call. +* vResolution[OUT] +* Vertical resolution requested by caller in grab call. +* averageFPS[OUT] +* Average no. of frames captured per second. +* averageLatency[OUT] +* Average frame capture latency in microseconds. +*/ + +#define NV2080_CTRL_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED 0x00000001U +#define NV2080_CTRL_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED 0x00000002U +#define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_NO_WAIT 0x00000004U +#define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_INFINITE 0x00000008U +#define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_TIMEOUT 0x00000010U + +typedef struct NV2080_CTRL_NVFBC_SW_SESSION_INFO { + NvU32 processId; + NvU32 subProcessId; + NvU32 vgpuInstanceId; + NvU32 sessionId; + NvU32 sessionType; + NvU32 displayOrdinal; + NvU32 sessionFlags; + NvU32 hMaxResolution; + NvU32 vMaxResolution; + NvU32 hResolution; + NvU32 vResolution; + NvU32 averageFPS; + NvU32 averageLatency; +} NV2080_CTRL_NVFBC_SW_SESSION_INFO; + +/* +* NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO +* +* This command returns NVFBC software sessions information for the associate GPU. +* +* sessionInfoCount +* This field specifies the number of entries that are filled inside +* sessionInfoTbl. Max value of this field once returned from RM would be +* NV2080_GPU_NVFBC_MAX_COUNT. +* +* sessionInfoTbl +* This field specifies the array in which the NVFBC session information is to +* be returned. RM will fill the current session data in sessionInfoTbl array +* and then update the sessionInfoCount to reflect current session count value. +* +* Possible status values returned are: +* NV_OK +* NV_ERR_NO_MEMORY +* NV_ERR_INVALID_LOCK_STATE +* NV_ERR_INVALID_ARGUMENT +*/ + +#define NV2080_GPU_NVFBC_MAX_SESSION_COUNT 256U + +#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID (0x7CU) + +typedef struct NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS { + NvU32 sessionInfoCount; + NV2080_CTRL_NVFBC_SW_SESSION_INFO sessionInfoTbl[NV2080_GPU_NVFBC_MAX_SESSION_COUNT]; +} NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS; + +#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO (0x2080017cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID" */ + + + +/* + * NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE + * + * This command returns the VMMU page size + * + * vmmuSegmentSize + * Output parameter. + * Returns the VMMU segment size (in bytes) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE (0x2080017eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID (0x7EU) + +typedef struct NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 vmmuSegmentSize, 8); +} NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS; + +#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_32MB 0x02000000U +#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_64MB 0x04000000U +#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_128MB 0x08000000U +#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_256MB 0x10000000U +#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_512MB 0x20000000U + + + +/* + * NV2080_CTRL_GPU_GET_PARTITION_CAPACITY + * + * This command returns the count of partitions of given size (represented by + * NV2080_CTRL_GPU_PARTITION_FLAG_*) which can be requested via + * NV2080_CTRL_GPU_SET_PARTITIONS ctrl call. + * Note that this API does not "reserve" any partitions, and there is no + * guarantee that the reported count of available partitions of a given size + * will remain consistent following creation of partitions of different size + * through NV2080_CTRL_GPU_SET_PARTITIONS. + * Note that this API is unsupported if SMC is feature-disabled. + * + * partitionFlag[IN] + * - Partition flag indicating size of requested partitions + * + * partitionCount[OUT] + * - Available number of partitions of the given size which can currently be created. + * + * availableSpans[OUT] + * - For each partition able to be created of the specified size, the span + * it could occupy. + * + * availableSpansCount[OUT] + * - Number of valid entries in availableSpans. + * + * totalPartitionCount[OUT] + * - Total number of partitions of the given size which can be created. + * + * totalSpans[OUT] + * - List of spans which can possibly be occupied by partitions of the + * given type. + * + * totalSpansCount[OUT] + * - Number of valid entries in totalSpans. + * + * bStaticInfo[IN] + * - Flag indicating that client requests only the information from + * totalPartitionCount and totalSpans. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_PARTITION_CAPACITY (0x20800181U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS { + NvU32 partitionFlag; + NvU32 partitionCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN availableSpans[NV2080_CTRL_GPU_MAX_PARTITIONS], 8); + NvU32 availableSpansCount; + NvU32 totalPartitionCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN totalSpans[NV2080_CTRL_GPU_MAX_PARTITIONS], 8); + NvU32 totalSpansCount; + NvBool bStaticInfo; +} NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_CACHED_INFO + * + * This command returns cached(SW only) gpu information for the associated GPU. + * Requests to retrieve gpu information use a list of one or more NV2080_CTRL_GPU_INFO + * structures. + * The gpuInfoList is aligned with NV2080_CTRL_GPU_GET_INFO_V2_PARAMS for security concern + * + * gpuInfoListSize + * This field specifies the number of entries on the caller's + * gpuInfoList. + * gpuInfoList + * This field specifies a pointer in the caller's address space + * to the buffer into which the gpu information is to be returned. + * This buffer must be at least as big as gpuInfoListSize multiplied + * by the size of the NV2080_CTRL_GPU_INFO structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_OPERATING_SYSTEM + */ +#define NV2080_CTRL_CMD_GPU_GET_CACHED_INFO (0x20800182U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x82" */ + +typedef struct NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS { + NvU32 gpuInfoListSize; + NV2080_CTRL_GPU_INFO gpuInfoList[NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE]; +} NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS; + +/* + * NV2080_CTRL_GPU_SET_PARTITIONING_MODE + * + * This command configures this GPU to control global mode for partitioning. + * This command may not be sent to a GPU with any active partitions. + * This command may be used to set the following modes: + * + * NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING + * NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_LEGACY + * This is the default mode. While this GPU is in this mode, no partitions + * will be allowed to be created via SET_PARTITIONS - a client must set one + * of the below modes prior to partitioning the GPU. When a client sets a + * GPU into this mode, any performance changes resulting from partitions + * made while in either of the below modes will be cleared. A + * physical-function-level reset is required after setting this mode. + * + * NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_MAX_PERF + * In this mode, when the GPU is partitioned, each partition will have the + * maximum possible performance which can be evenly distributed among all + * partitions. The total performance of the GPU, taking into account all + * partitions created in this mode, may be less than that of a GPU running + * in legacy non-SMC mode. Partitions created while in this mode require a + * physical-function-level reset before the partitioning may take full + * effect. Destroying all partitions while in this mode may be + * insufficient to restore full performance to the GPU - only by setting + * the mode to _LEGACY can this be achieved. A physical-function-level + * reset is NOT required after setting this mode. + * + * NV2080_CTRL_GPU_SET_PARTIITONING_MODE_REPARTITIONING_FAST_RECONFIG + * By setting this mode, the performance of the GPU will be restricted such + * that all partitions will have a consistent fraction of the total + * available performance, which may be less than the maximum possible + * performance available to each partition. Creating or destroying + * partitions on this GPU while in this mode will not require a + * physical-function-level reset, and will not affect other active + * partitions. Destroying all partitions while in this mode may be + * insufficient to restore full performance to the GPU - only by setting + * the mode to _LEGACY can this be achieved. A physical-function-level + * reset is required after setting this mode. + * + * Parameters: + * partitioningMode[IN] + * - Partitioning Mode to set for this GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE (0x20800183U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING 1:0 +#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_LEGACY 0U +#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_MAX_PERF 1U +#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_FAST_RECONFIG 2U + +#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID (0x83U) + +typedef struct NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS { + NvU32 partitioningMode; +} NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS; + + + +/* NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO + * + * This structure describes resources available in a partition requested of a + * given type. + * + * [OUT] partitionFlag + * - Flags to specify in NV2080_CTRL_CMD_GPU_SET_PARTITIONS to request this + * partition + * + * [OUT] grCount + * - Total Number of SMC engines/GR engines (including GFX capable ones in this parition) + * + * [OUT] gfxGrCount + * - Number of SMC engines/GR engines capable of GFX. This is a subset of the engines included in grCount + * + * [OUT] gpcCount + * - Number of GPCs in this partition, including the GFX Capable ones. + * + * [OUT] virtualGpcCount + * - Number of virtualized GPCs in this partition, including the GFX Capable ones. + * + * [OUT] gfxGpcCount + * - Number of GFX Capable GPCs in this partition. This is a subset of the GPCs included in gpcCount. + * + * [OUT] veidCount + * - Number of VEIDS in this partition + * + * [OUT] smCount + * - Number of SMs in this partition + * + * [OUT] ceCount + * - Copy Engines in this partition + * + * [OUT] nvEncCount + * - Encoder Engines in this partition + * + * [OUT] nvDecCount + * - Decoder Engines in this partition + * + * [OUT] nvJpgCount + * - Jpg Engines in this partition + * + * [OUT] nvOfaCount + * - Ofa engines in this partition + * [OUT] memorySize + * - Total available memory within this partition + */ +typedef struct NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO { + NvU32 partitionFlag; + NvU32 grCount; + NvU32 gfxGrCount; + NvU32 gpcCount; + NvU32 virtualGpcCount; + NvU32 grGpcCount; + NvU32 veidCount; + NvU32 smCount; + NvU32 ceCount; + NvU32 nvEncCount; + NvU32 nvDecCount; + NvU32 nvJpgCount; + NvU32 nvOfaCount; + NV_DECLARE_ALIGNED(NvU64 memorySize, 8); +} NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO; + +/* + * NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS + * + * This command returns information regarding GPU partitions which can be + * requested via NV2080_CTRL_CMD_GPU_SET_PARTITIONS. + * + * [OUT] descCount + * - Number of valid partition types + * + * [OUT] partitionDescs + * - Information describing available partitions + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS_MESSAGE_ID (0x85U) + +typedef struct NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS { + NvU32 descCount; + // C form: NV2080_CTRL_GPU_DESCRIBE_PARTITION_INFO partitionDescs[NV2080_CTRL_GPU_PARTITION_MAX_TYPES]; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO partitionDescs[NV2080_CTRL_GPU_PARTITION_MAX_TYPES], 8); +} NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS; + +#define NV2080_CTRL_CMD_GPU_DESCRIBE_PARTITIONS (0x20800185U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS_MESSAGE_ID" */ + + + +/* + * NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE + * + * This command returns information regarding maximum page size supported + * by GMMU on the platform on which RM is running. + * + * [OUT] maxSupportedPageSize + * - Maximum local vidmem page size supported by GMMU of a given GPU (HW) + * on a given platform (OS) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE (0x20800188U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID (0x88U) + +typedef struct NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS { + NvU32 maxSupportedPageSize; +} NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS; + + + +/* + * NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC + * + * This command returns the max number of MMUs per GPC + * + * gpcId [IN] + * Logical GPC id + * count [OUT] + * The number of MMUs per GPC + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. When SMC is enabled, this + * is a mandatory parameter. + */ +#define NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID (0x8AU) + +typedef struct NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS { + NvU32 gpcId; + NvU32 count; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS; + +#define NV2080_CTRL_CMD_GPU_GET_NUM_MMUS_PER_GPC (0x2080018aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS + * + * This command returns the GPU partition IDs for all active partitions + * If GPU is not partitioned, the control call will return partition count as "0" + * + * swizzId[OUT] + * - HW Partition ID associated with the active partitions + * + * partitionCount[OUT] + * - Number of active partitions in system + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS_MESSAGE_ID (0x8BU) + +typedef struct NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS { + NvU32 swizzId[NV2080_CTRL_GPU_MAX_PARTITION_IDS]; + NvU32 partitionCount; +} NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS; + +#define NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS (0x2080018bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS_MESSAGE_ID" */ + + + +/* + * NV2080_CTRL_CMD_GPU_GET_PIDS + * + * Given a resource identifier and its type, this command returns a set of + * process identifiers (PIDs) of processes that have instantiated this resource. + * For example, given a class number, this command returns a list of all + * processes with clients that have matching object allocations. + * This is a SMC aware call and the scope of the information gets restricted + * based on partition subscription. + * The call enforces partition subscription if SMC is enabled, and client is not + * a monitoring client. + * Monitoring clients get global information without any scope based filtering. + * Monitoring clients are also not expected to subscribe to a partition when + * SMC is enabled. + * + * idType + * Type of the resource identifier. See below for a list of valid types. + * id + * Resource identifier. + * pidTblCount + * Number of entries in the PID table. + * pidTbl + * Table which will contain the PIDs. Each table entry is of type NvU32. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_GPU_GET_PIDS (0x2080018dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID" */ + +/* max size of pidTable */ +#define NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT 950U + +#define NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID (0x8DU) + +typedef struct NV2080_CTRL_GPU_GET_PIDS_PARAMS { + NvU32 idType; + NvU32 id; + NvU32 pidTblCount; + NvU32 pidTbl[NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT]; +} NV2080_CTRL_GPU_GET_PIDS_PARAMS; + +/* + * Use class NV20_SUBDEVICE_0 with NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_CLASS to query + * PIDs with or without GPU contexts. For any other class id, PIDs only with GPU + * contexts are returned. + */ +#define NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_CLASS (0x00000000U) +#define NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_VGPU_GUEST (0x00000001U) + +/* + * NV2080_CTRL_SMC_SUBSCRIPTION_INFO + * + * This structure contains information about the SMC subscription type. + * If MIG is enabled a valid ID is returned, it is set to PARTITIONID_INVALID otherwise. + * + * computeInstanceId + * This parameter returns a valid compute instance ID + * gpuInstanceId + * This parameter returns a valid GPU instance ID + */ +typedef struct NV2080_CTRL_SMC_SUBSCRIPTION_INFO { + NvU32 computeInstanceId; + NvU32 gpuInstanceId; +} NV2080_CTRL_SMC_SUBSCRIPTION_INFO; + +/* + * NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA + * + * This structure contains the video memory usage information. + * + * memPrivate + * This parameter returns the amount of memory exclusively owned + * (i.e. private) to the client + * memSharedOwned + * This parameter returns the amount of shared memory owned by the client + * memSharedDuped + * This parameter returns the amount of shared memory duped by the client + * protectedMemPrivate + * This parameter returns the amount of protected memory exclusively owned + * (i.e. private) to the client whenever memory protection is enabled + * protectedMemSharedOwned + * This parameter returns the amount of shared protected memory owned by the + * client whenever memory protection is enabled + * protectedMemSharedDuped + * This parameter returns the amount of shared protected memory duped by the + * client whenever memory protection is enabled + */ +typedef struct NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA { + NV_DECLARE_ALIGNED(NvU64 memPrivate, 8); + NV_DECLARE_ALIGNED(NvU64 memSharedOwned, 8); + NV_DECLARE_ALIGNED(NvU64 memSharedDuped, 8); + NV_DECLARE_ALIGNED(NvU64 protectedMemPrivate, 8); + NV_DECLARE_ALIGNED(NvU64 protectedMemSharedOwned, 8); + NV_DECLARE_ALIGNED(NvU64 protectedMemSharedDuped, 8); +} NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA; + +#define NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE (0x00000000U) + +#define NV2080_CTRL_GPU_PID_INFO_INDEX_MAX NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE + +typedef union NV2080_CTRL_GPU_PID_INFO_DATA { + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA vidMemUsage, 8); +} NV2080_CTRL_GPU_PID_INFO_DATA; + + +/* + * NV2080_CTRL_GPU_PID_INFO + * + * This structure contains the per pid information. Each type of information + * retrievable via NV2080_CTRL_CMD_GET_PID_INFO is assigned a unique index + * below. In addition the process for which the lookup is for is also defined. + * This is a SMC aware call and the scope of the information gets restricted + * based on partition subscription. + * The call enforces partition subscription if SMC is enabled, and client is not + * a monitoring client. + * Monitoring clients get global information without any scope based filtering. + * Monitoring clients are also not expected to subscribe to a partition when + * SMC is enabled. + * + * pid + * This parameter specifies the PID of the process for which information is + * to be queried. + * index + * This parameter specifies the type of information being queried for the + * process of interest. + * result + * This parameter returns the result of the instruction's execution. + * data + * This parameter returns the data corresponding to the information which is + * being queried. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + * + * Valid PID information indices are: + * + * NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE + * This index is used to request the amount of video memory on this GPU + * allocated to the process. + */ +typedef struct NV2080_CTRL_GPU_PID_INFO { + NvU32 pid; + NvU32 index; + NvU32 result; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PID_INFO_DATA data, 8); + NV2080_CTRL_SMC_SUBSCRIPTION_INFO smcSubscription; +} NV2080_CTRL_GPU_PID_INFO; + +/* + * NV2080_CTRL_CMD_GPU_GET_PID_INFO + * + * This command allows querying per-process information from the RM. Clients + * request information by specifying a unique informational index and the + * Process ID of the process in question. The result is set to indicate success + * and the information queried (if available) is returned in the data parameter. + * + * pidInfoListCount + * The number of valid entries in the pidInfoList array. + * pidInfoList + * An array of NV2080_CTRL_GPU_PID_INFO of maximum length + * NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_GPU_GET_PID_INFO (0x2080018eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID" */ + +/* max size of pidInfoList */ +#define NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT 200U + +#define NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID (0x8EU) + +typedef struct NV2080_CTRL_GPU_GET_PID_INFO_PARAMS { + NvU32 pidInfoListCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PID_INFO pidInfoList[NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT], 8); +} NV2080_CTRL_GPU_GET_PID_INFO_PARAMS; + + + +/*! + * NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT + * + * @brief Handle VF PRI faults + * + * faultType + * BAR1, BAR2, PHYSICAL or UNBOUND_INSTANCE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * + */ + +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT (0x20800192U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_INVALID 0U +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR1 1U +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR2 2U +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_PHYSICAL 3U +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_UNBOUND_INSTANCE 4U + +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_MESSAGE_ID (0x92U) + +typedef struct NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS { + NvU32 faultType; +} NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS; + + +/*! + * Compute policy types to be specified by callers to set a config. + * + * _TIMESLICE + * Set the timeslice config for the requested GPU. + * Check @ref NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE for + * permissible timeslice values. + */ +#define NV2080_CTRL_GPU_COMPUTE_POLICY_TIMESLICE 0U +#define NV2080_CTRL_GPU_COMPUTE_POLICY_MAX 1U + +/*! + * Enum consisting of permissible timeslice options that can configured + * for a GPU. These can be queried by compute clients and the exact + * timeslice values can be chosen appropriately as per GPU support + */ +typedef enum NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE { + NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_DEFAULT = 0, + NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_SHORT = 1, + NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MEDIUM = 2, + NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_LONG = 3, + NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MAX = 4, +} NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE; + +typedef struct NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG { + /*! + * NV2080_CTRL_GPU_COMPUTE_POLICY_ + */ + NvU32 type; + + /*! + * Union of type-specific data + */ + union { + NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE timeslice; + } data; +} NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG; + +#define NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID (0x94U) + +typedef struct NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS { + NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG config; +} NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG + * + * This command retrieves all compute policies configs for the associated gpu. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG (0x20800195U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID" */ + +/*! + * This define limits the max number of policy configs that can be handled by + * NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG command. + * + * @note Needs to be in sync (greater or equal) to NV2080_CTRL_GPU_COMPUTE_POLICY_MAX. + */ + +#define NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX 32U + +#define NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID (0x95U) + +typedef struct NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS { + NvU32 numConfigs; + + /*! + * C form: + * NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG configList[NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX]; + */ + NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG configList[NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX]; +} NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_GFID + * + * This command returns the GFID (GPU Function ID) for a given SR-IOV + * Virtual Function (VF) of the physical GPU. + * + * domain [IN] + * This field specifies the respective domain of the PCI device. + * bus [IN] + * This field specifies the bus id for a given VF. + * device [IN] + * This field specifies the device id for a given VF. + * func [IN] + * This field specifies the function id for a given VF. + * gfid[OUT] + * - This field returns GFID for a given VF BDF. + * gfidMask[OUT] + * - This field returns GFID mask value. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ + +#define NV2080_CTRL_CMD_GPU_GET_GFID (0x20800196U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GFID_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_GFID_PARAMS_MESSAGE_ID (0x96U) + +typedef struct NV2080_CTRL_GPU_GET_GFID_PARAMS { + NvU32 domain; + NvU8 bus; + NvU8 device; + NvU8 func; + NvU32 gfid; + NvU32 gfidMask; +} NV2080_CTRL_GPU_GET_GFID_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY + * + * This command informs the GPU driver that the GPU partition associated with + * a given GFID has been activated or will be deactivated. + * + * gfid[IN] + * - The GPU function identifier for a given VF BDF + * bEnable [IN] + * - Set to NV_TRUE if the GPU partition has been activated. + * - Set to NV_FALSE if the GPU partition will be deactivated. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ + +#define NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY (0x20800197U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS_MESSAGE_ID (0x97U) + +typedef struct NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS { + NvU32 gfid; + NvBool bEnable; +} NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS; + +/*! + * NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST + * + * @brief Validate the address range for memory map request by comparing the + * user supplied address range with GPU BAR0/BAR1 range. + * + * @param[in] addressStart Start address for memory map request + * @param[in] addressLength Length for for memory map request + * @param[out] protection NV_PROTECT_READ_WRITE, if both read/write is allowed + * NV_PROTECT_READABLE, if only read is allowed + * + * Possible status values returned are: + * NV_OK + * NV_ERR_PROTECTION_FAULT + * + */ +#define NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST (0x20800198U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID (0x98U) + +typedef struct NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS { + NV_DECLARE_ALIGNED(NvU64 addressStart, 8); + NV_DECLARE_ALIGNED(NvU64 addressLength, 8); + NvU32 protection; +} NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES + * + * This command is used to retrieve the load time (latency) of each engine. + * + * engineCount + * This field specifies the number of entries of the following + * three arrays. + * + * engineList[NV2080_GPU_MAX_ENGINE_OBJECTS] + * An array of NvU32 which stores each engine's descriptor. + * + * engineStateLoadTime[NV2080_GPU_MAX_ENGINE_OBJECTS] + * A array of NvU64 which stores each engine's load time. + * + * engineIsInit[NV2080_GPU_MAX_ENGINE_OBJECTS] + * A array of NvBool which stores each engine's initialization status. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES (0x2080019bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS 0xA0U + +#define NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID (0x9BU) + +typedef struct NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS { + NvU32 engineCount; + NvU32 engineList[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS]; + NV_DECLARE_ALIGNED(NvU64 engineStateLoadTime[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS], 8); + NvBool engineIsInit[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS]; +} NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING + * + * This command is used to retrieve the mapping of engine ID and engine Name. + * + * engineCount + * This field specifies the size of the mapping. + * + * engineID + * An array of NvU32 which stores each engine's descriptor. + * + * engineName + * An array of char[100] which stores each engine's name. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING (0x2080019cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID (0x9CU) + +typedef struct NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS { + NvU32 engineCount; + NvU32 engineID[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS]; + char engineName[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS][100]; +} NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_NOPTRS + * + * Same as above NV2080_CTRL_CMD_GPU_EXEC_REG_OPS except that this CTRL CMD will + * not allow any embedded pointers. The regOps array is inlined as part of the + * struct. + * NOTE: This intended for gsp plugin only as it may override regOp access + * restrictions + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_NOPTRS (0x2080019dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID" */ + +/* setting this to 100 keeps it right below 4k in size */ +#define NV2080_CTRL_REG_OPS_ARRAY_MAX 100U +#define NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID (0x9DU) + +typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS { + NvHandle hClientTarget; + NvHandle hChannelTarget; + NvU32 bNonTransactional; + NvU32 reserved00[2]; + NvU32 regOpCount; + NV2080_CTRL_GPU_REG_OP regOps[NV2080_CTRL_REG_OPS_ARRAY_MAX]; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS; + + + + +/*! + * NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO + * + * [in/out] gpuId + * GPU ID for which the capabilities are queried. + * For the NV2080_CTRL_CMD_GET_P2P_CAPS control: + * If bAllCaps == NV_TRUE, this parameter is an out parameter and equals to + * the GPU ID of an attached GPU. + * If bAllCaps == NV_FALSE, this parameter is an in parameter and the requester + * should set it to the ID of the GPU that needs to be queried from. + * [in] gpuUuid + * Alternative to gpuId; used to identify target GPU for which caps are being queried. + * Option only available for Guest RPCs. + * If bUseUuid == NV_TRUE, gpuUuid is used in lieu of gpuId to identify target GPU. + * If bUseUuid == NV_FALSE, gpuUuid is ignored and gpuId is used by default. + * If bAllCaps == NV_TRUE, gpuUuid is ignored. + * [out] p2pCaps + * Peer to peer capabilities discovered between the GPUs. + * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. + * [out] p2pOptimalReadCEs + * Mask of CEs to use for p2p reads over Nvlink. + * [out] p2pOptimalWriteCEs + * Mask of CEs to use for p2p writes over Nvlink. + * [out] p2pCapsStatus + * Status of all supported p2p capabilities. + * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. + * [out] busPeerId + * Bus peer ID. For an invalid or a non-existent peer this field + * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. + */ +#define NV2080_GET_P2P_CAPS_UUID_LEN 16U + +typedef struct NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO { + NvU32 gpuId; + NvU8 gpuUuid[NV2080_GET_P2P_CAPS_UUID_LEN]; + NvU32 p2pCaps; + NvU32 p2pOptimalReadCEs; + NvU32 p2pOptimalWriteCEs; + NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; + NvU32 busPeerId; +} NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO; + +/*! + * NV2080_CTRL_CMD_GET_P2P_CAPS + * + * Returns peer to peer capabilities present between GPUs. + * The caller must either specify bAllCaps to query the capabilities for + * all the attached GPUs or they must pass a valid list of GPU IDs. + * + * [in] bAllCaps + * Set to NV_TRUE to query the capabilities for all the attached GPUs. + * Set to NV_FALSE and specify peerGpuCount and peerGpuCaps[].gpuId + * to retrieve the capabilities only for the specified GPUs. + * [in] bUseUuid + * Option only available for Guest RPCs. + * Set to NV_TRUE to use gpuUuid in lieu of gpuId to identify target GPU. + * If bAllCaps == NV_TRUE, bUseUuid is ignored. + * [in/out] peerGpuCount + * The number of the peerGpuCaps entries. + * If bAllCaps == NV_TRUE, this parameter is an out parameter and equals to + * the total number of the attached GPUs. + * If bAllCaps == NV_FALSE, this parameter is an in parameter and the requester + * should set it to the number of the peerGpuCaps entries. + * [in/out] peerGpuCaps + * The array of NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO entries, describing + * the peer to peer capabilities of the GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT - Invalid peerGpuCount + * NV_ERR_OBJECT_NOT_FOUND - Invalid peerGpuCaps[].gpuId + */ +#define NV2080_CTRL_CMD_GET_P2P_CAPS (0x208001a0U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID (0xA0U) + +typedef struct NV2080_CTRL_GET_P2P_CAPS_PARAMS { + NvBool bAllCaps; + NvBool bUseUuid; + NvU32 peerGpuCount; + NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO peerGpuCaps[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; +} NV2080_CTRL_GET_P2P_CAPS_PARAMS; + + + +/*! + * NV2080_CTRL_GPU_COMPUTE_PROFILE + * + * This structure specifies resources in an execution partition + * + * id[OUT] + * - Total Number of GPCs in this partition + * + * computeSize[OUT] + * - NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* associated with this profile + * + * gpcCount[OUT] + * - Total Number of GPCs in this partition (including GFX Supported GPCs) + * + * veidCount[OUT] + * - Number of VEIDs allocated to this profile + * + * smCount[OUT] + * - Number of SMs usable in this profile + */ +typedef struct NV2080_CTRL_GPU_COMPUTE_PROFILE { + NvU8 computeSize; + NvU32 gfxGpcCount; + NvU32 gpcCount; + NvU32 veidCount; + NvU32 smCount; +} NV2080_CTRL_GPU_COMPUTE_PROFILE; + +/*! + * NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS + * + * This structure specifies resources in an execution partition + * + * profileCount[OUT] + * - Total Number of profiles filled + * + * profiles[OUT] + * - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles + */ +#define NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xA2U) + +typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS { + NvU32 profileCount; + NV2080_CTRL_GPU_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE]; +} NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS; + +#define NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILES (0x208001a2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_UNSUPPORTED 0U +#define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_NOT_STARTED 1U +#define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_IN_PROGRESS 2U +#define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE 3U + +#define NV2080_GPU_FABRIC_CLUSTER_UUID_LEN 16U + +#define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_SUPPORTED NVBIT64(0) + +/*! + * NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS + * + * This structure provides the GPU<-->FM probe state info on NVSwitch based + * systems + * + * state[OUT] + * - Current state of GPU<-->FM probe req/rsp + * Following values can be returned + * _UNSUPPORTED - system does not support this feature + * _NOT_STARTED - probe request is not yet sent to the FM + * _IN_PROGRESS - probe response is not yet received + * _COMPLETE - probe response is received + * When state is NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE + * status has to be checked for probe response success/failure + * status[OUT] + * - Inband Probe response status + * A GPU which returns NV_OK status upon receiving the probe response + * can participate in P2P + * clusterUuid[OUT] + * - Uuid of the cluster to which this node belongs + * fabricPartitionId[OUT] + * - Fabric partition Id + * fabricCaps[OUT] + * - Summary of fabric capabilities received from probe resp + * Possible values are + * NV2080_CTRL_GPU_FABRIC_PROBE_CAP_* + */ +#define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xA3U) + +typedef struct NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS { + NvU8 state; + NV_STATUS status; + NvU8 clusterUuid[NV2080_GPU_FABRIC_CLUSTER_UUID_LEN]; + NvU16 fabricPartitionId; + NV_DECLARE_ALIGNED(NvU64 fabricCaps, 8); +} NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS; + +#define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO (0x208001a3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS + * + * This command retrieves and constructs the GPU partnumber from the VBIOS. + * + * The following data are currently supported: + * + * pciDevId + * The PCI device ID + * + * chipSku + * The chip SKU information + * + * chipMajor + * The chip major number + * + * chipMinor + * The chip minor number + * + */ +#define NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS (0x208001a4U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID" */ + +/* + * The string format for a GPU part number + * The GPU part number is formatted with 4 hexadecimal digits for the PCI device ID, the chip SKU string, + * the chip major number, and then the chip minor number. + * Ordering of the fields for the string format must be synced with the NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS + * struct fields. + */ +#define GPU_PART_NUMBER_FMT "%04X-%s-%X%X" + +/* The maximum length for the chip sku */ +#define NV2080_MAX_CHIP_SKU_LENGTH 0x00000004U + +#define NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID (0xA4U) + +typedef struct NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS { + NvU32 pciDevId; + NvU8 chipSku[NV2080_MAX_CHIP_SKU_LENGTH]; + NvU32 chipMajor; + NvU32 chipMinor; +} NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP + * + * This command returns the host hardware defined engine ID of the specified engine(s). + * + * swizzId[IN] + * - HW Partition ID associated with the requested partition. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP (0x208001a5U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS_MESSAGE_ID (0xA5U) + +typedef struct NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS { + NvU32 swizzId; +} NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS; + +#define NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS (0x208001a6U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_GSP (0x208001a7U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_VGPU (0x208001a8U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID" */ + +/* setting this to 100 keeps it right below 4k in size */ +#define NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX 50U +typedef struct NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS { + NvHandle hClientTarget; + NvHandle hChannelTarget; + NvU32 bNonTransactional; + NvU32 regOpCount; + NvU32 smIds[NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX]; + NV2080_CTRL_GPU_REG_OP regOps[NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX]; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS; + +#define NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_MESSAGE_ID (0xA6U) + +typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS; +#define NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS_MESSAGE_ID (0xA7U) + +typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS; +#define NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID (0xA8U) + +typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS; +/* _ctrl2080gpu_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080gpumon.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080gpumon.h new file mode 100644 index 0000000..742b21a --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080gpumon.h @@ -0,0 +1,96 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080gpumon.finn +// + + + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/*! + * This structure represents base class of GPU monitoring sample. + */ +typedef struct NV2080_CTRL_GPUMON_SAMPLE { + /*! + * Timestamps in nano-seconds. + */ + NV_DECLARE_ALIGNED(NvU64 timeStamp, 8); +} NV2080_CTRL_GPUMON_SAMPLE; + +/*! + * This structure represents base GPU monitoring sample. + */ +typedef struct NV2080_CTRL_GPUMON_SAMPLES { + /*! + * Type of the sample, see NV2080_CTRL_GPUMON_SAMPLE_TYPE_* for reference. + */ + NvU8 type; + /*! + * Size of the buffer, this should be + * bufSize == NV2080_CTRL_*_GPUMON_SAMPLE_COUNT_* + * sizeof(derived type of NV2080_CTRL_GPUMON_SAMPLE). + */ + NvU32 bufSize; + /*! + * Number of samples in ring buffer. + */ + NvU32 count; + /*! + * tracks the offset of the tail in the circular queue array pSamples. + */ + NvU32 tracker; + /*! + * Pointer to a circular queue based on array of NV2080_CTRL_GPUMON_SAMPLE + * or its derived types structs with size == bufSize. + * + * @note This circular queue wraps around after 10 seconds of sampling, + * and it is clients' responsibility to query within this time frame in + * order to avoid losing samples. + * @note With one exception, this queue contains last 10 seconds of samples + * with tracker poiniting to oldest entry and entry before tracker as the + * newest entry. Exception is when queue is not full (i.e. tracker is + * pointing to a zeroed out entry), in that case valid entries are between 0 + * and tracker. + * @note Clients can store tracker from previous query in order to provide + * samples since last read. + */ + NV_DECLARE_ALIGNED(NvP64 pSamples, 8); +} NV2080_CTRL_GPUMON_SAMPLES; + +/*! + * Enumeration of GPU monitoring sample types. + */ +#define NV2080_CTRL_GPUMON_SAMPLE_TYPE_PWR_MONITOR_STATUS 0x00000001 +#define NV2080_CTRL_GPUMON_SAMPLE_TYPE_PERFMON_UTIL 0x00000002 + +/*! + * Macro for invalid PID. + */ +#define NV2080_GPUMON_PID_INVALID ((NvU32)(~0)) diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h new file mode 100644 index 0000000..dde6eed --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h @@ -0,0 +1,1820 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080gr.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +#include "ctrl/ctrl0080/ctrl0080gr.h" /* 2080 is partially derivative of 0080 */ +#include "nvcfg_sdk.h" + +/* + * NV2080_CTRL_GR_ROUTE_INFO + * + * This structure specifies the routing information used to + * disambiguate the target GR engine. + * + * flags + * This field decides how the route field is interpreted + * + * route + * This field has the data to identify target GR engine + * + */ +#define NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE 1:0 +#define NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_NONE 0x0U +#define NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_ENGID 0x1U +#define NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_CHANNEL 0x2U + +#define NV2080_CTRL_GR_ROUTE_INFO_DATA_CHANNEL_HANDLE 31:0 +#define NV2080_CTRL_GR_ROUTE_INFO_DATA_ENGID 31:0 + +typedef NV0080_CTRL_GR_ROUTE_INFO NV2080_CTRL_GR_ROUTE_INFO; + +/* NV20_SUBDEVICE_XX gr control commands and parameters */ + +/* + * NV2080_CTRL_GR_INFO + * + * This structure represents a single 32bit gr engine value. Clients + * request a particular gr engine value by specifying a unique gr + * information index. + * + * Legal gr information index values are: + * NV2080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT + * This index is used to request the surface buffer alignment (in bytes) + * required by the associated subdevice. The return value is GPU + * implementation-dependent. + * NV2080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT + * This index is used to request the required swizzled surface alignment + * (in bytes) supported by the associated subdevice. The return value + * is GPU implementation-dependent. A return value of 0 indicates the GPU + * does not support swizzled surfaces. + * NV2080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE + * This index is used to request the vertex cache size (in entries) + * supported by the associated subdevice. The return value is GPU + * implementation-dependent. A value of 0 indicates the GPU does + * have a vertex cache. + * NV2080_CTRL_GR_INFO_INDEX_VPE_COUNT + * This index is used to request the number of VPE units supported by the + * associated subdevice. The return value is GPU implementation-dependent. + * A return value of 0 indicates the GPU does not contain VPE units. + * NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT + * This index is used to request the number of shader pipes supported by + * the associated subdevice. The return value is GPU + * implementation-dependent. A return value of 0 indicates the GPU does + * not contain dedicated shader units. + * For tesla: this value is the number of enabled TPCs + * NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT + * This index is used to request the number of sub units per + * shader pipes supported by the associated subdevice. The return + * value is GPU implementation-dependent. A return value of 0 indicates + * the GPU does not contain dedicated shader units. + * For tesla: this value is the number of enabled SMs (per TPC) + * NV2080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR + * This index is used to request the scaling factor for thread stack + * memory. + * A value of 0 indicates the GPU does not support this function. + * NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT + * This index is used to request the number of SM register banks supported. + * A value of 0 indicates the GPU does not support this function. + * NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT + * This index is used to request the number of registers per SM register + * bank. A value of 0 indicates the GPU does not support this function. + * NV2080_CTRL_GR_INFO_INDEX_SM_VERSION + * This index is used to determine the SM version. + * A value of 0 indicates the GPU does not support this function. + * Otherwise one of NV2080_CTRL_GR_INFO_SM_VERSION_*. + * NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM + * This index is used to determine the maximum number of warps + * (thread groups) per SM. + * A value of 0 indicates the GPU does not support this function. + * NV2080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP + * This index is used to determine the maximum number of threads + * in each warp (thread group). + * A value of 0 indicates the GPU does not support this function. + * NV2080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY + * This index is used to request the default fb memory read/write request + * size in bytes (typically based on the memory configuration/controller). + * Smaller memory requests are likely to take as long as a full one. + * A value of 0 indicates the GPU does not support this function. + * NV2080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY + * This index is used to request the default host memory read/write request + * size in bytes (typically based on the memory configuration/controller). + * Smaller memory requests are likely to take as long as a full one. + * A value of 0 indicates the GPU does not support this function. + * NV2080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM + * This index is used to request the maximum number of streaming processors + * per SM. + * NV2080_CTRL_GR_INFO_INDEX_LITTER_* + * This index is used to query the various LITTER size information from + * the chip. + * NV2080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED + * This index is used to query whether the chip has timeslice mode enabled. + * NV2080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT + * This index is used to return the number of "GPU Cores" + * supported by the graphics pipeline + * NV2080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT + * This index is used to return the number of "Ray Tracing Cores" + * supported by the graphics pipeline + * NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT + * This index is used to return the number of "Tensor Cores" + * supported by the graphics pipeline + */ +typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO; + +/* + * Valid GR info index values + * These indices are offset from supporting the 0080 version of this call + */ +#define NV2080_CTRL_GR_INFO_INDEX_MAXCLIPS NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS +#define NV2080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 +#define NV2080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK +/** + * This index is used to request the surface buffer alignment (in bytes) + * required by the associated subdevice. The return value is GPU + * implementation-dependent. + */ +#define NV2080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT +#define NV2080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT +#define NV2080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE +/** + * This index is used to request the number of VPE units supported by the + * associated subdevice. The return value is GPU implementation-dependent. + * A return value of 0 indicates the GPU does not contain VPE units. + */ +#define NV2080_CTRL_GR_INFO_INDEX_VPE_COUNT NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT +/** + * This index is used to request the number of shader pipes supported by + * the associated subdevice. The return value is GPU + * implementation-dependent. A return value of 0 indicates the GPU does + * not contain dedicated shader units. + * For tesla: this value is the number of enabled TPCs + */ +#define NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT +/** + * This index is used to request the scaling factor for thread stack + * memory. + * A value of 0 indicates the GPU does not support this function. + */ +#define NV2080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR +/** + * This index is used to request the number of sub units per + * shader pipes supported by the associated subdevice. The return + * value is GPU implementation-dependent. A return value of 0 indicates + * the GPU does not contain dedicated shader units. + * For tesla: this value is the number of enabled SMs (per TPC) + */ +#define NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT +#define NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT +#define NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT +/** + * This index is used to determine the SM version. + * A value of 0 indicates the GPU does not support this function. + * Otherwise one of NV2080_CTRL_GR_INFO_SM_VERSION_*. + */ +#define NV2080_CTRL_GR_INFO_INDEX_SM_VERSION NV0080_CTRL_GR_INFO_INDEX_SM_VERSION +/** + * This index is used to determine the maximum number of warps + * (thread groups) per SM. + * A value of 0 indicates the GPU does not support this function. + */ +#define NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM +/** + * This index is used to determine the maximum number of threads + * in each warp (thread group). + * A value of 0 indicates the GPU does not support this function. + */ +#define NV2080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP +#define NV2080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES +#define NV2080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES +#define NV2080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY +#define NV2080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY +#define NV2080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS +#define NV2080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC +#define NV2080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS +/** + * This index is used to return the number of "Ray Tracing Cores" + * supported by the graphics pipeline + */ +#define NV2080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT +#define NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC +#define NV2080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP +#define NV2080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT +#define NV2080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT +#define NV2080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC + +/* When adding a new INDEX, please update INDEX_MAX and MAX_SIZE accordingly + * NOTE: 0080 functionality is merged with 2080 functionality, so this max size + * reflects that. + */ +#define NV2080_CTRL_GR_INFO_INDEX_MAX NV0080_CTRL_GR_INFO_INDEX_MAX +#define NV2080_CTRL_GR_INFO_MAX_SIZE NV0080_CTRL_GR_INFO_MAX_SIZE + +/* valid SM version return values */ + +#define NV2080_CTRL_GR_INFO_SM_VERSION_NONE (0x00000000U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_1_05 (0x00000105U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_1_1 (0x00000110U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_1_2 (0x00000120U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_1_3 (0x00000130U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_1_4 (0x00000140U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_1_5 (0x00000150U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_2_0 (0x00000200U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_2_1 (0x00000210U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_2_2 (0x00000220U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_3_0 (0x00000300U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_3_1 (0x00000310U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_3_2 (0x00000320U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_3_3 (0x00000330U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_3_5 (0x00000350U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_3_6 (0x00000360U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_3_8 (0x00000380U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_3_9 (0x00000390U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_4_0 (0x00000400U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_5_0 (0x00000500U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_5_02 (0x00000502U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_5_03 (0x00000503U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_6_0 (0x00000600U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_6_01 (0x00000601U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_6_02 (0x00000602U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_0 (0x00000700U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_01 (0x00000701U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_02 (0x00000702U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_03 (0x00000703U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_05 (0x00000705U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_02 (0x00000802U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_06 (0x00000806U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_07 (0x00000807U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_08 (0x00000808U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_09 (0x00000809U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_9_00 (0x00000900U) + + + +/* compatibility SM versions to match the official names in the ISA (e.g., SM5.2) */ +#define NV2080_CTRL_GR_INFO_SM_VERSION_5_2 (NV2080_CTRL_GR_INFO_SM_VERSION_5_02) +#define NV2080_CTRL_GR_INFO_SM_VERSION_5_3 (NV2080_CTRL_GR_INFO_SM_VERSION_5_03) +#define NV2080_CTRL_GR_INFO_SM_VERSION_6_1 (NV2080_CTRL_GR_INFO_SM_VERSION_6_01) +#define NV2080_CTRL_GR_INFO_SM_VERSION_6_2 (NV2080_CTRL_GR_INFO_SM_VERSION_6_02) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_1 (NV2080_CTRL_GR_INFO_SM_VERSION_7_01) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_2 (NV2080_CTRL_GR_INFO_SM_VERSION_7_02) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_3 (NV2080_CTRL_GR_INFO_SM_VERSION_7_03) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_5 (NV2080_CTRL_GR_INFO_SM_VERSION_7_05) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_2 (NV2080_CTRL_GR_INFO_SM_VERSION_8_02) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_6 (NV2080_CTRL_GR_INFO_SM_VERSION_8_06) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_7 (NV2080_CTRL_GR_INFO_SM_VERSION_8_07) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_8 (NV2080_CTRL_GR_INFO_SM_VERSION_8_08) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_9 (NV2080_CTRL_GR_INFO_SM_VERSION_8_09) +#define NV2080_CTRL_GR_INFO_SM_VERSION_9_0 (NV2080_CTRL_GR_INFO_SM_VERSION_9_00) + + + +/** + * NV2080_CTRL_CMD_GR_GET_INFO + * + * This command returns gr engine information for the associated GPU. + * Requests to retrieve gr information use a list of one or more + * NV2080_CTRL_GR_INFO structures. + * + * grInfoListSize + * This field specifies the number of entries on the caller's + * grInfoList. + * grInfoList + * This field specifies a pointer in the caller's address space + * to the buffer into which the gr information is to be returned. + * This buffer must be at least as big as grInfoListSize multiplied + * by the size of the NV2080_CTRL_GR_INFO structure. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. When MIG is enabled, this + * is a mandatory parameter. + */ +#define NV2080_CTRL_CMD_GR_GET_INFO (0x20801201U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_GR_GET_INFO_PARAMS { + NvU32 grInfoListSize; + NV_DECLARE_ALIGNED(NvP64 grInfoList, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_GET_INFO_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE + * + * This command is used to set the zcull context switch mode for the specified + * channel. A value of NV_ERR_NOT_SUPPORTED is returned if the + * target channel does not support zcull context switch mode changes. + * + * hChannel + * This parameter specifies the channel handle of + * the channel that is to have it's zcull context switch mode changed. + * hShareClient + * Support for sharing zcull buffers across RM clients is no longer + * supported. To maintain API compatibility, this field must match + * the hClient used in the control call. + * hShareChannel + * This parameter specifies the channel handle of + * the channel with which the zcull context buffer is to be shared. This + * parameter is valid when zcullMode is set to SEPARATE_BUFFER. This + * parameter should be set to the same value as hChannel if no + * sharing is intended. + * zcullMode + * This parameter specifies the new zcull context switch mode. + * Legal values for this parameter include: + * NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_GLOBAL + * This mode is the normal zcull operation where it is not + * context switched and there is one set of globally shared + * zcull memory and tables. This mode is only supported as + * long as all channels use this mode. + * NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_NO_CTXSW + * This mode causes the zcull tables to be reset on a context + * switch, but the zcull buffer will not be saved/restored. + * NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_SEPARATE_BUFFER + * This mode will cause the zcull buffers and tables to be + * saved/restored on context switches. If a share channel + * ID is given (shareChID), then the 2 channels will share + * the zcull context buffers. + */ +#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE (0x20801205U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x5" */ + +typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS { + NvHandle hChannel; + NvHandle hShareClient; + NvHandle hShareChannel; + NvU32 zcullMode; +} NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS; +/* valid zcullMode values */ +#define NV2080_CTRL_CTXSW_ZCULL_MODE_GLOBAL (0x00000000U) +#define NV2080_CTRL_CTXSW_ZCULL_MODE_NO_CTXSW (0x00000001U) +#define NV2080_CTRL_CTXSW_ZCULL_MODE_SEPARATE_BUFFER (0x00000002U) + +/** + * NV2080_CTRL_CMD_GR_GET_ZCULL_INFO + * + * This command is used to query the RM for zcull information that the + * driver will need to allocate and manage the zcull regions. + * + * widthAlignPixels + * This parameter returns the width alignment restrictions in pixels + * used to adjust a surface for proper aliquot coverage (typically + * #TPC's * 16). + * + * heightAlignPixels + * This parameter returns the height alignment restrictions in pixels + * used to adjust a surface for proper aliquot coverage (typically 32). + * + * pixelSquaresByAliquots + * This parameter returns the pixel area covered by an aliquot + * (typically #Zcull_banks * 16 * 16). + * + * aliquotTotal + * This parameter returns the total aliquot pool available in HW. + * + * zcullRegionByteMultiplier + * This parameter returns multiplier used to convert aliquots in a region + * to the number of bytes required to save/restore them. + * + * zcullRegionHeaderSize + * This parameter returns the region header size which is required to be + * allocated and accounted for in any save/restore operation on a region. + * + * zcullSubregionHeaderSize + * This parameter returns the subregion header size which is required to be + * allocated and accounted for in any save/restore operation on a region. + * + * subregionCount + * This parameter returns the subregion count. + * + * subregionWidthAlignPixels + * This parameter returns the subregion width alignment restrictions in + * pixels used to adjust a surface for proper aliquot coverage + * (typically #TPC's * 16). + * + * subregionHeightAlignPixels + * This parameter returns the subregion height alignment restrictions in + * pixels used to adjust a surface for proper aliquot coverage + * (typically 62). + * + * The callee should compute the size of a zcull region as follows. + * (numBytes = aliquots * zcullRegionByteMultiplier + + * zcullRegionHeaderSize + zcullSubregionHeaderSize) + */ +#define NV2080_CTRL_CMD_GR_GET_ZCULL_INFO (0x20801206U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_SUBREGION_SUPPORTED +#define NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS { + NvU32 widthAlignPixels; + NvU32 heightAlignPixels; + NvU32 pixelSquaresByAliquots; + NvU32 aliquotTotal; + NvU32 zcullRegionByteMultiplier; + NvU32 zcullRegionHeaderSize; + NvU32 zcullSubregionHeaderSize; + NvU32 subregionCount; + NvU32 subregionWidthAlignPixels; + NvU32 subregionHeightAlignPixels; +} NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_CTXSW_PM_MODE + * + * This command is used to set the pm context switch mode for the specified + * channel. A value of NV_ERR_NOT_SUPPORTED is returned if the + * target channel does not support pm context switch mode changes. + * + * hChannel + * This parameter specifies the channel handle of + * the channel that is to have its pm context switch mode changed. + * pmMode + * This parameter specifies the new pm context switch mode. + * Legal values for this parameter include: + * NV2080_CTRL_CTXSW_PM_MODE_NO_CTXSW + * This mode says that the pms are not to be context switched. + * NV2080_CTRL_CTXSW_PM_MODE_CTXSW + * This mode says that the pms in Mode-B are to be context switched. + * NV2080_CTRL_CTXSW_PM_MODE_STREAM_OUT_CTXSW + * This mode says that the pms in Mode-E (stream out) are to be context switched. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_CTXSW_PM_MODE (0x20801207U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x7" */ + +typedef struct NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS { + NvHandle hChannel; + NvU32 pmMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS; + +/* valid pmMode values */ +#define NV2080_CTRL_CTXSW_PM_MODE_NO_CTXSW (0x00000000U) +#define NV2080_CTRL_CTXSW_PM_MODE_CTXSW (0x00000001U) +#define NV2080_CTRL_CTXSW_PM_MODE_STREAM_OUT_CTXSW (0x00000002U) + +/* + * NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND + * + * This command is used to set the zcull context switch mode and virtual address + * for the specified channel. A value of NV_ERR_NOT_SUPPORTED is + * returned if the target channel does not support zcull context switch mode + * changes. + * + * hClient + * This parameter specifies the client handle of + * that owns the zcull context buffer. This field must match + * the hClient used in the control call for non-kernel clients. + * hChannel + * This parameter specifies the channel handle of + * the channel that is to have its zcull context switch mode changed. + * vMemPtr + * This parameter specifies the 64 bit virtual address + * for the allocated zcull context buffer. + * zcullMode + * This parameter specifies the new zcull context switch mode. + * Legal values for this parameter include: + * NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_GLOBAL + * This mode is the normal zcull operation where it is not + * context switched and there is one set of globally shared + * zcull memory and tables. This mode is only supported as + * long as all channels use this mode. + * NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_NO_CTXSW + * This mode causes the zcull tables to be reset on a context + * switch, but the zcull buffer will not be saved/restored. + * NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_SEPARATE_BUFFER + * This mode will cause the zcull buffers and tables to be + * saved/restored on context switches. If a share channel + * ID is given (shareChID), then the 2 channels will share + * the zcull context buffers. + */ +#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND (0x20801208U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x8" */ + +typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS { + NvHandle hClient; + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 vMemPtr, 8); + NvU32 zcullMode; +} NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS; +/* valid zcullMode values same as above NV2080_CTRL_CTXSW_ZCULL_MODE */ + +/* + * NV2080_CTRL_CMD_GR_CTXSW_PM_BIND + * + * This command is used to set the PM context switch mode and virtual address + * for the specified channel. A value of NV_ERR_NOT_SUPPORTED is + * returned if the target channel does not support PM context switch mode + * changes. + * + * hClient + * This parameter specifies the client handle of + * that owns the PM context buffer. + * hChannel + * This parameter specifies the channel handle of + * the channel that is to have its PM context switch mode changed. + * vMemPtr + * This parameter specifies the 64 bit virtual address + * for the allocated PM context buffer. + * pmMode + * This parameter specifies the new PM context switch mode. + * Legal values for this parameter include: + * NV2080_CTRL_GR_SET_CTXSW_PM_MODE_NO_CTXSW + * This mode says that the pms are not to be context switched + * NV2080_CTRL_GR_SET_CTXSW_PM_MODE_CTXSW + * This mode says that the pms are to be context switched + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_CTXSW_PM_BIND (0x20801209U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x9" */ + +typedef struct NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS { + NvHandle hClient; + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 vMemPtr, 8); + NvU32 pmMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS; +/* valid pmMode values same as above NV2080_CTRL_CTXSW_PM_MODE */ + +/* + * NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP + * + * Send a list of values used to describe GPC/TPC tile mapping tables. + * + * mapValueCount + * This field specifies the number of actual map entries. This count + * should equal the number of TPCs in the system. + * mapValues + * This field is a pointer to a buffer of NvU08 values representing map + * data. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_GR_SET_GPC_TILE_MAP_MAX_VALUES 128U +#define NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP (0x2080120aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0xA" */ + +typedef struct NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS { + NvU32 mapValueCount; + NvU8 mapValues[NV2080_CTRL_GR_SET_GPC_TILE_MAP_MAX_VALUES]; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE + * + * This command is used to set the SMPC context switch mode for the specified + * channel or channel group (TSG). A value of NV_ERR_NOT_SUPPORTED + * is returned if the target channel/TSG does not support SMPC context switch + * mode changes. If a channel is part of a TSG, the user must send in the TSG + * handle and not an individual channel handle, an error will be returned if a + * channel handle is used in this case. + * + * SMPC = SM Performance Counters + * + * hChannel + * This parameter specifies the channel or channel group (TSG) handle + * that is to have its SMPC context switch mode changed. + * If this parameter is set to 0, then the mode below applies to all current + * and future channels (i.e. we will be enabling/disabling global mode) + * smpcMode + * This parameter specifies the new SMPC context switch mode. + * Legal values for this parameter include: + * NV2080_CTRL_GR_SET_CTXSW_SMPC_MODE_NO_CTXSW + * This mode says that the SMPC data is not to be context switched. + * NV2080_CTRL_GR_SET_CTXSW_SMPC_MODE_CTXSW + * This mode says that the SMPC data is to be context switched. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE (0x2080120eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0xE" */ + +typedef struct NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS { + NvHandle hChannel; + NvU32 smpcMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS; + +/* valid smpcMode values */ +#define NV2080_CTRL_CTXSW_SMPC_MODE_NO_CTXSW (0x00000000U) +#define NV2080_CTRL_CTXSW_SMPC_MODE_CTXSW (0x00000001U) + +/* + * NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS + * + * This command returns an array of the mappings between SMs and GPC/TPCs. + * + * smId + * An array of the mappings between SMs and GPC/TPCs. + * smCount + * Returns the number of valid mappings in the array. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS (0x2080120fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_MAX_SM_COUNT 144U +#define NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS { + struct { + NvU32 gpcId; + NvU32 tpcId; + } smId[NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_MAX_SM_COUNT]; + NvU32 smCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE + * + * This command is used to set the preemption context switch mode for the specified + * channel. A value of NV_ERR_NOT_SUPPORTED is returned if the + * target channel does not support preemption context switch mode changes. + * + * flags + * This field specifies flags for the preemption mode changes. + * These flags can tell callee which mode is valid in the call + * since we handle graphics and/or compute + * hChannel + * This parameter specifies the channel handle of the channel + * that is to have it's preemption context switch mode set. + * gfxpPreemptMode + * This parameter specifies the new Graphics preemption context switch + * mode. Legal values for this parameter include: + * NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_WFI + * This mode is the normal wait-for-idle context switch mode. + * NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP + * This mode causes the graphics engine to allow preempting the + * channel mid-triangle. + * NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP_POOL + * This mode causes the graphics engine to use a shared pool of buffers + * to support GfxP with lower memory overhead + * cilpPreemptMode + * This parameter specifies the new Compute preemption context switch + * mode. Legal values for this parameter include: + * NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_WFI + * This mode is the normal wait-for-idle context switch mode. + * NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CTA + * This mode causes the compute engine to allow preempting the channel + * at the instruction level. + * NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CILP + * This mode causes the compute engine to allow preempting the channel + * at the instruction level. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE (0x20801210U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x10" */ + +typedef struct NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS { + NvU32 flags; + NvHandle hChannel; + NvU32 gfxpPreemptMode; + NvU32 cilpPreemptMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS; + +/* valid preemption flags */ +#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP 0:0 +#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_IGNORE (0x00000000U) +#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_SET (0x00000001U) +#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP 1:1 +#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_IGNORE (0x00000000U) +#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_SET (0x00000001U) + +/* valid Graphics mode values */ +#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_WFI (0x00000000U) +#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP (0x00000001U) +#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP_POOL (0x00000002U) + +/* valid Compute mode values */ +#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_WFI (0x00000000U) +#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CTA (0x00000001U) +#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CILP (0x00000002U) + +/* valid preemption buffers */ +typedef enum NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS { + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_MAIN = 0, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SPILL = 1, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_PAGEPOOL = 2, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_BETACB = 3, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_RTV = 4, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL = 5, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL = 6, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL_CPU = 7, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END = 8, +} NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS; + +/* + * NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND + * + * This command is used to set the preemption context switch mode and virtual + * addresses of the preemption buffers for the specified channel. A value of + * NV_ERR_NOT_SUPPORTED is returned if the target channel does not + * support preemption context switch mode changes. + * + * flags + * This field specifies flags for the preemption mode changes. + * These flags can tell callee which mode is valid in the call + * since we handle graphics and/or compute + * hClient + * This parameter specifies the client handle of + * that owns the preemption context buffer. + * hChannel + * This parameter specifies the channel handle of the channel + * that is to have its preemption context switch mode set. + * vMemPtr + * This parameter specifies the 64 bit virtual address + * for the allocated preemption context buffer. + * gfxpPreemptMode + * This parameter specifies the new Graphics preemption context switch + * mode. Legal values for this parameter include: + * NV2080_CTRL_CTXSW_PREEMPTION_MODE_GFX_WFI + * This mode is the normal wait-for-idle context switch mode. + * NV2080_CTRL_CTXSW_PREEMPTION_MODE_GFX_GFXP + * This mode causes the graphics engine to allow preempting the + * channel mid-triangle. + * cilpPreemptMode + * This parameter specifies the new Compute preemption context switch + * mode. Legal values for this parameter include: + * NV2080_CTRL_CTXSW_PREEMPTION_MODE_COMPUTE_WFI + * This mode is the normal wait-for-idle context switch mode. + * NV2080_CTRL_CTXSW_PREEMPTION_MODE_COMPUTE_CTA + * This mode causes the compute engine to allow preempting the channel + * at the instruction level. + * NV2080_CTRL_CTXSW_PREEMPTION_MODE_COMPUTE_CILP + * This mode causes the compute engine to allow preempting the channel + * at the instruction level. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND (0x20801211U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x11" */ + +typedef struct NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS { + NvU32 flags; + NvHandle hClient; + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 vMemPtrs[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END], 8); + NvU32 gfxpPreemptMode; + NvU32 cilpPreemptMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS; +/* valid mode and flag values same as above NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE */ + +/* + * NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE + * + * This command is used to apply the WAR for PC sampling to avoid hang in + * multi-ctx scenario. + * + * hChannel + * This parameter specifies the channel or channel group (TSG) handle + * that is to have its PC Sampling mode changed. + * samplingMode + * This parameter specifies whether sampling is turned ON or OFF. + * Legal values for this parameter include: + * NV2080_CTRL_GR_SET_PC_SAMPLING_MODE_DISABLED + * This mode says that PC sampling is disabled for current context. + * NV2080_CTRL_GR_SET_PC_SAMPLING_MODE_ENABLED + * This mode says that PC sampling is disabled for current context. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE (0x20801212U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x12" */ + +typedef struct NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS { + NvHandle hChannel; + NvU32 samplingMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS; + +/* valid samplingMode values */ +#define NV2080_CTRL_PC_SAMPLING_MODE_DISABLED (0x00000000U) +#define NV2080_CTRL_PC_SAMPLING_MODE_ENABLED (0x00000001U) + +/* + * NV2080_CTRL_CMD_GR_GET_ROP_INFO + * + * Gets information about ROPs including the ROP unit count and information + * about ROP operations per clock. + * + * ropUnitCount + * The count of active ROP units. + * ropOperationsFactor. + * The number of ROP operations per clock for a single ROP unit. + * ropOperationsCount + * The number of ROP operations per clock across all active ROP units. + */ +#define NV2080_CTRL_CMD_GR_GET_ROP_INFO (0x20801213U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV2080_CTRL_GR_GET_ROP_INFO_PARAMS { + NvU32 ropUnitCount; + NvU32 ropOperationsFactor; + NvU32 ropOperationsCount; +} NV2080_CTRL_GR_GET_ROP_INFO_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GR_GET_CTXSW_STATS + * + * This command is used to get the context switch statistics. The user can + * also add a flag to tell RM to reset the stats counters back to 0. + * + * hChannel + * This parameter specifies the channel or channel group (TSG) handle + * that is to have the stats returned. Note, must be the TSG handle if + * channel is part of a TSG. + * flags + * This parameter specifies processing flags. See possible flags below. + * saveCnt + * This parameter returns the number of saves on the channel. + * restoreCnt + * This parameter returns the number of restores on the channel. + * wfiSaveCnt + * This parameter returns the number of WFI saves on the channel. + * ctaSaveCnt + * This parameter returns the number of CTA saves on the channel. + * cilpSaveCnt + * This parameter returns the number of CILP saves on the channel. + * gfxpSaveCnt + * This parameter returns the number of GfxP saves on the channel. + */ +#define NV2080_CTRL_CMD_GR_GET_CTXSW_STATS (0x20801215U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x15" */ + +typedef struct NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS { + NvHandle hChannel; + NvU32 flags; + NvU32 saveCnt; + NvU32 restoreCnt; + NvU32 wfiSaveCnt; + NvU32 ctaSaveCnt; + NvU32 cilpSaveCnt; + NvU32 gfxpSaveCnt; +} NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS; +/* valid GET_CTXSW_STATS flags settings */ +#define NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET 0:0 +#define NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_FALSE (0x00000000U) +#define NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_TRUE (0x00000001U) + + + +/* + * NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE + * + * This command provides the size, alignment of all context buffers including global and + * local context buffers which has been created & will be mapped on a context + * + * hChannel [IN] + * This parameter specifies the channel or channel group (TSG) handle + * totalBufferSize [OUT] + * This parameter returns the total context buffers size. + */ +#define NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE (0x20801218U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS { + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 totalBufferSize, 8); +} NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS; + +/* + * NV2080_CTRL_GR_CTX_BUFFER_INFO + * alignment + * Specifies the alignment requirement for each context buffer + * size + * Aligned size of context buffer + * bufferHandle [deprecated] + * Opaque pointer to memdesc. Used by kernel clients for tracking purpose only. + * pageCount + * allocation size in the form of pageCount + * physAddr + * Physical address of the buffer first page + * bufferType + * NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID type of this buffer + * aperture + * allocation aperture. Could be SYSMEM, VIDMEM, UNKNOWN + * kind + * PTE kind of this allocation. + * pageSize + * Page size of the buffer. + * bIsContigous + * States if physical allocation for this buffer is contiguous. PageSize will + * have no meaning if this flag is set. + * bGlobalBuffer + * States if a defined buffer is global as global buffers need to be mapped + * only once in TSG. + * bLocalBuffer + * States if a buffer is local to a channel. + * bDeviceDescendant + * TRUE if the allocation is a constructed under a Device or Subdevice. + * uuid + * SHA1 UUID of the Device or Subdevice. Valid when deviceDescendant is TRUE. + */ +typedef struct NV2080_CTRL_GR_CTX_BUFFER_INFO { + NV_DECLARE_ALIGNED(NvU64 alignment, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NV_DECLARE_ALIGNED(NvP64 bufferHandle, 8); + NV_DECLARE_ALIGNED(NvU64 pageCount, 8); + NV_DECLARE_ALIGNED(NvU64 physAddr, 8); + NvU32 bufferType; + NvU32 aperture; + NvU32 kind; + NvU32 pageSize; + NvBool bIsContigous; + NvBool bGlobalBuffer; + NvBool bLocalBuffer; + NvBool bDeviceDescendant; + NvU8 uuid[16]; +} NV2080_CTRL_GR_CTX_BUFFER_INFO; +typedef struct NV2080_CTRL_GR_CTX_BUFFER_INFO *PNV2080_CTRL_GR_CTX_BUFFER_INFO; + +#define NV2080_CTRL_GR_MAX_CTX_BUFFER_COUNT 64U + +/* + * NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_INFO + * + * This command provides the size, alignment of all context buffers including global and + * local context buffers which has been created & will be mapped on a context. + * If the client invoking the command is a kernel client, the buffers are retained. + * + * hUserClient [IN] + * This parameter specifies the client handle that owns this channel. + * hChannel [IN] + * This parameter specifies the channel or channel group (TSG) handle + * bufferCount [OUT] + * This parameter specifies the number of entries in ctxBufferInfo filled + * by the command. + * ctxBufferInfo [OUT] + * Array of context buffer info containing alignment, size etc. + */ +#define NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_INFO (0x20801219U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS { + NvHandle hUserClient; + NvHandle hChannel; + NvU32 bufferCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTX_BUFFER_INFO ctxBufferInfo[NV2080_CTRL_GR_MAX_CTX_BUFFER_COUNT], 8); +} NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS; + +// Aperture flags +#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_UNKNWON ADDR_UNKNOWN +#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_SYSMEM ADDR_SYSMEM +#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_FBMEM ADDR_FBMEM + +/* + * NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER + * This command returns the global logical ordering of SM w.r.t GPCs/TPCs. + * + * NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS + * This structure holds the TPC/SM ordering info. + * + * gpcId + * Logical GPC Id. + * This is the ordering of enabled GPCs post floor sweeping. + * The GPCs are numbered from 0 to N-1, where N is the enabled GPC count. + * + * localTpcId + * Local Logical TPC Id. + * This is the ordering of enabled TPCs within a GPC post floor sweeping. + * This ID is used in conjunction with the gpcId. + * The TPCs are numbered from 0 to N-1, where N is the enabled TPC count for the given GPC. + * + * localSmId + * Local Logical SM Id. + * This is the ordering of enabled SMs within a TPC post floor sweeping. + * This ID is used in conjunction with the localTpcId. + * The SMs are numbered from 0 to N-1, where N is the enabled SM count for the given TPC. + * + * globalTpcId + * Global Logical TPC Id. + * This is the ordering of all enabled TPCs in the GPU post floor sweeping. + * The TPCs are numbered from 0 to N-1, where N is the enabled TPC count across all GPCs + * + * globalSmId + * Global Logical SM Id array. + * This is the global ordering of all enabled SMs in the GPU post floor sweeping. + * The SMs are numbered from 0 to N-1, where N is the enabled SM count across all GPCs. + * + * virtualGpcId + * Virtual GPC Id. + * This is the ordering of enabled GPCs post floor sweeping (ordered in increasing + * number of TPC counts) The GPCs are numbered from 0 to N-1, where N is the + * enabled GPC count and 8-23 for singleton TPC holders. + * + * migratableTpcId + * Migratable TPC Id. + * This is the same as the Local Tpc Id for virtual GPC 0-8 (true physical gpcs) and 0 for + * virtual gpcs 8-23 that represent singleton tpcs. + * + * numSm + * Enabled SM count across all GPCs. + * This represent the valid entries in the globalSmId array + * + * numTpc + * Enabled TPC count across all GPCs. + * + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + */ +#define NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER (0x2080121bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER_MAX_SM_COUNT 512U + +#define NV2080_CTRL_GR_DISABLED_SM_VGPC_ID 0xFFU + +#define NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x1BU) + +typedef struct NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS { + struct { + NvU16 gpcId; + NvU16 localTpcId; + NvU16 localSmId; + NvU16 globalTpcId; + NvU16 virtualGpcId; + NvU16 migratableTpcId; + } globalSmId[NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER_MAX_SM_COUNT]; + + NvU16 numSm; + NvU16 numTpc; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS; + +/* +* NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL +* +* This command gives current resident channel on GR engine +* +* chID [OUT] +* RM returns current resident channel on GR engine +* grRouteInfo [IN] +* This parameter specifies the routing information used to +* disambiguate the target GR engine. +*/ +#define NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL (0x2080121cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x1C" */ + +typedef struct NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS { + NvU32 chID; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA + * + * This command provides the _VAT_ALARM data i.e. error and warning, counter and + * timestamps along with max GPC and TPC per GPC count. + * + * smVatAlarm [OUT] + * VAT Alarm data array per SM containing per GPC per TPC, counter and + * timestamp values for error and warning alarms. + * maxGpcCount [OUT] + * This parameter returns max GPC count. + * maxTpcPerGpcCount [OUT] + * This parameter returns the max TPC per GPC count. + */ +#define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_GPC_COUNT 10U +#define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_TPC_PER_GPC_COUNT 10U + +#define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA (0x2080121dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x1D" */ + +typedef struct NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC { + NV_DECLARE_ALIGNED(NvU64 errorCounter, 8); + NV_DECLARE_ALIGNED(NvU64 errorTimestamp, 8); + NV_DECLARE_ALIGNED(NvU64 warningCounter, 8); + NV_DECLARE_ALIGNED(NvU64 warningTimestamp, 8); +} NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC; + +typedef struct NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC tpc[NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_TPC_PER_GPC_COUNT], 8); +} NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC; + +typedef struct NV2080_CTRL_GR_VAT_ALARM_DATA { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC gpc[NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_GPC_COUNT], 8); +} NV2080_CTRL_GR_VAT_ALARM_DATA; + +typedef struct NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_VAT_ALARM_DATA smVatAlarm, 8); + NvU32 maxGpcCount; + NvU32 maxTpcPerGpcCount; +} NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS; +typedef struct NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS *PNV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE + * + * This command provides the size of GR attribute buffer. + * + * attribBufferSize [OUT] + * This parameter returns the attribute buffer size. + */ +#define NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE (0x2080121eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x1EU) + +typedef struct NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS { + NvU32 attribBufferSize; +} NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE + * + * This API queries size parameters for a request maximum graphics preemption + * pool size. It is only available to kernel callers + * + * NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS + * struct to return the size parameters + * + * maxSlots + * Input specifying the maximum number of slots, RM will calculate the output + * parameters based on this. Must be non-zero + * ctrlStructSize + * Output indicating the required size in bytes of the control structure to + * support a pool of maxSlots size. + * ctrlStructAlign + * Output indicating the required alignment of the control structure + * poolSize + * Output indicating the required size in bytes of the GfxP Pool. + * poolAlign + * Output indicating the required alignment of the GfxP Pool + * slotStride + * The number of bytes in each slot, i * slotStride gives the offset from the + * base of the pool to a given slot + */ +#define NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE (0x2080121fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x1F" */ + +typedef struct NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS { + NvU32 maxSlots; + NvU32 slotStride; + NV_DECLARE_ALIGNED(NvU64 ctrlStructSize, 8); + NV_DECLARE_ALIGNED(NvU64 ctrlStructAlign, 8); + NV_DECLARE_ALIGNED(NvU64 poolSize, 8); + NV_DECLARE_ALIGNED(NvU64 poolAlign, 8); +} NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE + * + * This API takes a CPU pointer to a GFxP Pool Control Structure and does the + * required onetime initialization. It should be called once and only once + * before a pool is used. It is only accessible to kernel callers. + * + * NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS + * struct to hand in the required info to RM + * + * pControlStructure + * This input is the kernel CPU pointer to the control structure. + */ +#define NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE (0x20801220U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x20" */ + +typedef struct NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8); + NvU32 maxSlots; +} NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS; + +#define NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS 64U + +/* + * NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS + * + * This API adds a list of buffer slots to a given control structure. It can + * only be called when no channel using the given pool is running or may become + * running for the duration of this call. If more slots are added than there + * is room for in the control structure the behavior is undefined. It is only + * accessible to kernel callers. + * + * NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS + * + * pControlStructure + * This input is the kernel CPU pointer to the control structure + * numSlots + * This input indicates how many slots are being added and are contained in the slots parameter + * slots + * This input contains an array of the slots to be added to the control structure + */ +#define NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS (0x20801221U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x21" */ + +typedef struct NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8); + NvU32 numSlots; + NvU32 slots[NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS]; +} NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS + * + * This API removes buffer slots from a given control structure. It can + * only be called when no channel using the given pool is running or may become + * running for the duration of this call. It can operate in two modes, either + * it will a specified number of slots, or a specified list of slots. + * + * It is only accessible to kernel callers. + * + * NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS_PARAMS + * + * pControlStructure + * This input is the kernel CPU pointer to the control structure + * numSlots + * This input indicates how many slots are being removed. if + * bRemoveSpecificSlots is true, then it also indicates how many entries in + * the slots array are populated. + * slots + * This array is either an input or output. If bRemoveSpecificSlots is true, + * then this will contain the list of slots to remove. If it is false, then + * it will be populated by RM with the indexes of the slots that were + * removed. + * bRemoveSpecificSlots + * This input determines which mode the call will run in. If true the caller + * will specify the list of slots they want removed, if any of those slots + * are not on the freelist, the call will fail. If false they only specify + * the number of slots they want removed and RM will pick up to that + * many. If there are not enough slots on the freelist to remove the + * requested amount, RM will return the number it was able to remove. + */ +#define NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS (0x20801222U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x22" */ + +typedef struct NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8); + NvU32 numSlots; + NvU32 slots[NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS]; + NvBool bRemoveSpecificSlots; +} NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS; + + + +#define NV2080_CTRL_CMD_GR_GET_CAPS_V2 (0x20801227U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x27U) + +typedef NV0080_CTRL_GR_GET_CAPS_V2_PARAMS NV2080_CTRL_GR_GET_CAPS_V2_PARAMS; + +#define NV2080_CTRL_CMD_GR_GET_INFO_V2 (0x20801228U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID (0x28U) + +typedef NV0080_CTRL_GR_GET_INFO_V2_PARAMS NV2080_CTRL_GR_GET_INFO_V2_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GR_GET_GPC_MASK + * + * This command returns a mask of enabled GPCs for the associated subdevice. + * + * grRouteInfo[IN] + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + * gpcMask[OUT] + * This parameter returns a mask of enabled GPCs. Each GPC has an ID + * that's equivalent to the corresponding bit position in the mask. + */ +#define NV2080_CTRL_CMD_GR_GET_GPC_MASK (0x2080122aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GPC_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_GPC_MASK_PARAMS_MESSAGE_ID (0x2AU) + +typedef struct NV2080_CTRL_GR_GET_GPC_MASK_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvU32 gpcMask; +} NV2080_CTRL_GR_GET_GPC_MASK_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_TPC_MASK + * + * This command returns a mask of enabled TPCs for a specified GPC. + * + * grRouteInfo[IN] + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + * gpcId[IN] + * This parameter specifies the GPC for which TPC information is + * to be retrieved. If the GPC with this ID is not enabled this command + * will return an tpcMask value of zero. + * + * tpcMask[OUT] + * This parameter returns a mask of enabled TPCs for the specified GPC. + * Each TPC has an ID that's equivalent to the corresponding bit + * position in the mask. + */ +#define NV2080_CTRL_CMD_GR_GET_TPC_MASK (0x2080122bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_TPC_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_TPC_MASK_PARAMS_MESSAGE_ID (0x2BU) + +typedef struct NV2080_CTRL_GR_GET_TPC_MASK_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvU32 gpcId; + NvU32 tpcMask; +} NV2080_CTRL_GR_GET_TPC_MASK_PARAMS; + +#define NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x2080122cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x2C" */ + +typedef NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID (0x2CU) + +typedef struct NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS params, 8); +} NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES + * + * This command is used to provide the caller with the alignment and size + * of the context save region for an engine + * + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * engineId + * This parameter is an input parameter specifying the engineId for which + * the alignment/size is requested. + * alignment + * This parameter is an output parameter which will be filled in with the + * minimum alignment requirement. + * size + * This parameter is an output parameter which will be filled in with the + * minimum size of the context save region for the engine. + * bInfoPopulated + * This parameter will be set if alignment and size are already set with + * valid values from a previous call. + */ + +#define NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES (0x2080122dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID (0x2DU) + +typedef struct NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvU32 engineId; + NvU32 alignment; + NvU32 size; + NvBool bInfoPopulated; +} NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER + * + * This command provides an interface to retrieve the speed select values of + * various instruction types. + * + * grRouteInfo[IN] + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + * imla0[OUT] + * The current speed select for IMLA0. + * + * fmla16[OUT] + * The current speed select for FMLA16. + * + * dp[OUT] + * The current speed select for DP. + * + * fmla32[OUT] + * The current speed select for FMLA32. + * + * ffma[OUT] + * The current speed select for FFMA. + * + * imla1[OUT] + * The current speed select for IMLA1. + * + * imla2[OUT] + * The current speed select for IMLA2. + * + * imla3[OUT] + * The current speed select for IMLA3. + * + * imla4[OUT] + * The current speed select for IMLA4. + */ +#define NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER (0x20801230U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_2 (0x1U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_4 (0x2U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_8 (0x3U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_16 (0x4U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_32 (0x5U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_64 (0x6U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_2 (0x1U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_4 (0x2U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_8 (0x3U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_16 (0x4U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_32 (0x5U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_REDUCED_SPEED (0x1U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_2 (0x1U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_4 (0x2U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_8 (0x3U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_16 (0x4U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_32 (0x5U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_2 (0x1U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_4 (0x2U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_8 (0x3U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_16 (0x4U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_32 (0x5U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_2 (0x1U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_4 (0x2U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_8 (0x3U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_16 (0x4U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_32 (0x5U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_64 (0x6U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_2 (0x1U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_4 (0x2U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_8 (0x3U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_16 (0x4U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_32 (0x5U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_64 (0x6U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_2 (0x1U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_4 (0x2U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_8 (0x3U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_16 (0x4U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_32 (0x5U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_64 (0x6U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_2 (0x1U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_4 (0x2U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_8 (0x3U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_16 (0x4U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_32 (0x5U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_64 (0x6U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x30U) + +typedef struct NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvU8 imla0; + NvU8 fmla16; + NvU8 dp; + NvU8 fmla32; + NvU8 ffma; + NvU8 imla1; + NvU8 imla2; + NvU8 imla3; + NvU8 imla4; +} NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID + * + * *DEPRECATED* Use NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID_V2 instead + * + * This command is used to create a FECS bind-point to an event buffer that + * is filtered by UID. + * + * hEventBuffer[IN] + * The event buffer to bind to + * + * recordSize[IN] + * The size of the FECS record in bytes + * + * levelOfDetail[IN] + * One of NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_: + * FULL: Report all CtxSw events + * SIMPLE: Report ACTIVE_REGION_START and ACTIVE_REGION_END only + * COMPAT: Events that KMD is interested in (for backwards compatibility) + * CUSTOM: Report events in the eventFilter field + * NOTE: RM may override the level-of-detail depending on the caller + * + * eventFilter[IN] + * Bitmask of events to report if levelOfDetail is CUSTOM + * + * bAllUsers[IN] + * Only report FECS CtxSw data for the current user if false, for all users if true + */ + +#define NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID (0x20801231U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD { + NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_FULL = 0, + NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_SIMPLE = 1, + NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_COMPAT = 2, + NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_CUSTOM = 3, +} NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD; + +#define NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS_MESSAGE_ID (0x31U) + +typedef struct NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS { + NvHandle hEventBuffer; + NvU32 recordSize; + NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD levelOfDetail; + NvU32 eventFilter; + NvBool bAllUsers; +} NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK + * + * This command returns a mask of physical GPC Ids for the associated syspipe + * + * physSyspipeId[IN] + * This parameter specifies syspipe for which phys GPC mask is requested + * + * gpcMask[OUT] + * This parameter returns a mask of mapped GPCs to provided syspipe. + * Each GPC-ID has a corresponding bit position in the mask. + */ +#define NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK (0x20801232U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS_MESSAGE_ID (0x32U) + +typedef struct NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS { + NvU32 physSyspipeId; + NvU32 gpcMask; +} NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_PPC_MASK + * + * This command returns a mask of enabled PPCs for a specified GPC. + * + * grRouteInfo[IN] + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + * gpcId[IN] + * This parameter specifies the GPC for which TPC information is + * to be retrieved. If the GPC with this ID is not enabled this command + * will return an ppcMask value of zero. + * + * ppcMask[OUT] + * This parameter returns a mask of enabled PPCs for the specified GPC. + * Each PPC has an ID that's equivalent to the corresponding bit + * position in the mask. + */ +#define NV2080_CTRL_CMD_GR_GET_PPC_MASK (0x20801233U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_PPC_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_PPC_MASK_PARAMS_MESSAGE_ID (0x33U) + +typedef struct NV2080_CTRL_GR_GET_PPC_MASK_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvU32 gpcId; + NvU32 ppcMask; +} NV2080_CTRL_GR_GET_PPC_MASK_PARAMS; + +#define NV2080_CTRL_CMD_GR_GET_NUM_TPCS_FOR_GPC (0x20801234U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS_MESSAGE_ID (0x34U) + +typedef struct NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS { + NvU32 gpcId; + NvU32 numTpcs; +} NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_CTXSW_MODES + * + * This command is used to get context switch modes for the specified + * channel. A value of NV_ERR_NOT_SUPPORTED is returned if the + * target channel does not support context switch mode changes. + * + * hChannel + * This parameter specifies the channel handle of + * the channel that is to have its context switch modes retrieved. + * zcullMode + * See NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE for possible return values + * pmMode + * See NV2080_CTRL_CMD_GR_CTXSW_PM_MODE for possible return values + * smpcMode + * See NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE for possible return values + * cilpPreemptMode + * See NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE for possible return values + * gfxpPreemptMode + * See NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE for possible return values + */ +#define NV2080_CTRL_CMD_GR_GET_CTXSW_MODES (0x20801235U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID (0x35U) + +typedef struct NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS { + NvHandle hChannel; + NvU32 zcullMode; + NvU32 pmMode; + NvU32 smpcMode; + NvU32 cilpPreemptMode; + NvU32 gfxpPreemptMode; +} NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP + * + * Get a list of values used to describe GPC/TPC tile mapping tables. + * + * mapValueCount + * This field specifies the number of actual map entries. This count + * should equal the number of TPCs in the system. + * mapValues + * This field is a pointer to a buffer of NvU08 values representing map + * data. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP (0x20801236U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x36" */ + +typedef NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP_FINN_PARAMS_MESSAGE_ID (0x36U) + +typedef struct NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP_FINN_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS params, 8); +} NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP_FINN_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GR_GET_ZCULL_MASK + * + * This command returns a mask of enabled ZCULLs for a specified GPC. + * + * gpcId[IN] + * This parameter, physical GPC index, specifies the GPC for which ZCULL + * information is to be retrieved. If the GPC with this ID is not enabled + * this command will return a zcullMask value of zero. + * + * zcullMask[OUT] + * This parameter returns a mask of enabled ZCULLs for the specified GPC. + * Each ZCULL has an ID that's equivalent to the corresponding bit + * position in the mask. + */ + +#define NV2080_CTRL_CMD_GR_GET_ZCULL_MASK (0x20801237U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS_MESSAGE_ID (0x37U) + +typedef struct NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS { + NvU32 gpcId; + NvU32 zcullMask; +} NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID_V2 + * + * This command is used to create a FECS bind-point to an event buffer that + * is filtered by UID. + * + * hEventBuffer[IN] + * The event buffer to bind to + * + * recordSize[IN] + * The size of the FECS record in bytes + * + * levelOfDetail[IN] + * One of NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_: + * FULL: Report all CtxSw events + * SIMPLE: Report ACTIVE_REGION_START and ACTIVE_REGION_END only + * COMPAT: Events that KMD is interested in (for backwards compatibility) + * CUSTOM: Report events in the eventFilter field + * NOTE: RM may override the level-of-detail depending on the caller + * + * eventFilter[IN] + * Bitmask of events to report if levelOfDetail is CUSTOM + * + * bAllUsers[IN] + * Only report FECS CtxSw data for the current user if false, for all users if true + * + * reasonCode [OUT] + * Reason for failure + */ +#define NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID_V2 (0x20801238U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE { + NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NONE = 0, + NV2080_CTRL_GR_FECS_BIND_REASON_CODE_GPU_TOO_OLD = 1, + NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED_GPU = 2, + NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED = 3, + NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_ADMIN = 4, + NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_CAPABILITY = 5, +} NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE; + +#define NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS_MESSAGE_ID (0x38U) + +typedef struct NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS { + NvHandle hEventBuffer; + NvU32 recordSize; + NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD levelOfDetail; + NvU32 eventFilter; + NvBool bAllUsers; + NvU32 reasonCode; +} NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_GFX_GPC_AND_TPC_INFO + * + * This command grabs information on GFX capable GPC's and TPC's for a specifc GR engine + * + * grRouteInfo[IN] + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + * physGfxGpcMask [OUT] + * Physical mask of Gfx capable GPC's + * + * numGfxTpc [OUT] + * Total number of Gfx capable TPC's + */ +#define NV2080_CTRL_CMD_GR_GET_GFX_GPC_AND_TPC_INFO (0x20801239U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS_MESSAGE_ID (0x39U) + +typedef struct NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvU32 physGfxGpcMask; + NvU32 numGfxTpc; +} NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS; + +/* _ctrl2080gr_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h new file mode 100644 index 0000000..481b59a --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h @@ -0,0 +1,263 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080grmgr.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX grmgr control commands and parameters */ + +// +// NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO +// +// This control call works as a batched query interface where we +// have multiple different queries that can be passed in +// and RM will return the associated data and status type +// If there is any error in NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS, +// we will immediately fail the call. +// However, if there is an error in the query-specific calls, we will +// log the error and march on. +// +// NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS +// numQueries[IN] +// - Specifies the number of valid queries that the caller will be passing in +// +// Possible status values returned are: +// NV_OK +// NV_ERR_INVALID_ARGUMENT +// NV_ERR_INVALID_STATE +// +#define NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO (0x20803801) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GRMGR_INTERFACE_ID << 8) | NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_MESSAGE_ID" */ + +// Max number of queries that can be batched in a single call to NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO +#define NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES 96 + +// +// Preference is to keep max.size of union at 24 bytes (i.e. 6 32-bit members) +// so that the size of entire query struct is maintained at 32 bytes, to ensure +// that overall params struct does not exceed 4kB +// +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_MAX_SIZE 32 +#define NV2080_CTRL_GRMGR_MAX_SMC_IDS 8 + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS + * gpcCount[OUT] + * - No. of logical/local GPCs which client can use to create the + * logical/local mask respectively + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS { + NvU32 gpcCount; // param[out] - logical/local GPC mask +} NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS + * gpcId[IN] + * - Logical/local GPC ID + * chipletGpcMap[OUT] + * - Returns chiplet GPC ID for legacy case and device monitoring client + * - Returns local GPC ID (== input gpcId) for SMC client + * - Does not support DM attribution case + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS { + NvU32 gpcId; // param[in] - logical/local GPC ID + NvU32 chipletGpcMap; // param[out] - chiplet GPC ID +} NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS + * gpcId[IN] + * - Logical/local GPC ID + * tpcMask[OUT] + * - Returns physical TPC mask for legacy, DM client and SMC cases + * - Does not support DM attribution case + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS { + NvU32 gpcId; // param[in] - logical/local GPC ID + NvU32 tpcMask; // param[out] - physical TPC mask +} NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS + * gpcId[IN] + * - Logical/local GPC ID + * ppcMask[OUT] + * - Returns physical PPC mask for legacy, DM client and SMC cases + * - Does not support DM attribution case + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS { + NvU32 gpcId; // param[in] - logical/local GPC ID + NvU32 ppcMask; // param[out] - physical PPC mask +} NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS; + +/*! + * !!! DEPRECATED - This query will return NV_ERR_NOT_SUPPORTED since deleting + * it would break driver compatibility !!! + * + * NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS + * swizzId[IN] + * - Swizz ID of partition + * - A DM client with an invalid swizz ID, will fail this call + * - This parameter is not compulsory for an SMC client; the subscription + * itself will do the necessary validation. + * gpcId[IN] + * - Logical/local GPC ID + * chipletGpcMap[OUT] + * - Returns chiplet GPC ID for legacy case and device monitoring client + * - Returns local GPC ID (== input gpcId) for SMC client + * - Does not support non-attribution case for DM client + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS { + NvU32 swizzId; // param[in] - swizz ID of partition + NvU32 gpcId; // param[in] - logical/local GPC ID + NvU32 chipletGpcMap; // param[out] - chiplet GPC ID +} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS + * gpcId[IN] + * - Logical/local GPC ID + * ropMask[OUT] + * - Returns physical ROP mask for legacy, DM client + * - Returns logical ROP mask for SMC + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS { + NvU32 gpcId; // param[in] - logical/local GPC ID + NvU32 ropMask; // param[out] - physical ROP mask +} NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS + * chipletSyspipeMask [OUT] + * - Mask of chiplet SMC-IDs for DM client attribution case + * - Mask of local SMC-IDs for SMC client + * - Legacy case returns 1 GR + * - Does not support attribution case for DM client + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS { + NvU32 chipletSyspipeMask; // param[out] - Mask of chiplet SMC IDs +} NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS + * swizzId[IN] + * - Swizz ID of partition + * - A DM client with an invalid swizz ID, will fail this call + * physSyspipeId[GRMGR_MAX_SMC_IDS] [OUT] + * - Physical SMC-IDs mapped to partition local idx for DM client attribution case + * - Does not support non-attribution case for DM client, SMC clients, legacy case + * physSyspipeIdCount[OUT] + * - Valid count of physSmcIds which has been populated in above array. + * - Failure case will return 0 + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS { + NvU16 swizzId; // param[in] - swizz ID of partition + NvU16 physSyspipeIdCount; // param[out] - Count of physSmcIds in above array + NvU8 physSyspipeId[NV2080_CTRL_GRMGR_MAX_SMC_IDS]; // param[out] - physical/local SMC IDs +} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS + * swizzId[IN] + * - Swizz ID of partition + * - Mandatory parameter + * - A DM client with an invalid swizz ID, will fail this call + * grIdx[IN] + * - Local grIdx for a partition + * - Mandatory parameter + * gpcEnMask[OUT] + * - Logical enabled GPC mask associated with requested grIdx of the partition i.e swizzid->engineId->gpcMask + * - These Ids should be used as input further + * - Does not support non-attribution case for DM client, SMC clients, legacy case + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS { + NvU32 swizzId; // param[in] - swizz ID of partition + NvU32 grIdx; // param[in] - partition local GR ID + NvU32 gpcEnMask; // param[out] - logical enabled GPC mask +} NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID + * syspipeId[OUT] + * - Partition-local GR idx for client subscribed to exec partition + * - Does not support legacy case, DM client, or SMC client subscribed only to partition + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS { + NvU32 syspipeId; // param[out] - partition-local Gr idx +} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS; + +/*! + * queryType[IN] + * - Use queryType defines to specify what information is being requested + * status[OUT] + * - Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS { + NvU16 queryType; + NvU8 reserved[2]; // To keep the struct aligned for now and available for future use (if needed) + NvU32 status; + union { + NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS gpcCountData; + NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS chipletGpcMapData; + NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS tpcMaskData; + NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS ppcMaskData; + NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS partitionGpcMapData; + NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS syspipeMaskData; + NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS partitionChipletSyspipeData; + NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS dmGpcMaskData; + NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS partitionSyspipeIdData; + NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS ropMaskData; + } queryData; +} NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS; + +#define NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS { + NvU16 numQueries; + NvU8 reserved[6]; // To keep the struct aligned for now and available for future use (if needed) + NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS queries[NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES]; +} NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS; + +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_INVALID 0 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GPC_COUNT 1 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GPC_MAP 2 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_TPC_MASK 3 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PPC_MASK 4 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_GPC_MAP 5 /* deprecated */ +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_SYSPIPE_MASK 6 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_SYSPIPE_IDS 7 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PROFILER_MON_GPC_MASK 8 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_SYSPIPE_ID 9 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_ROP_MASK 10 + +/* _ctrl2080grmgr_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h new file mode 100644 index 0000000..ee04d61 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h @@ -0,0 +1,82 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080gsp.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX GSP control commands and parameters */ + +/* + * NV2080_CTRL_CMD_GSP_GET_FEATURES + * + * This command is used to determine which GSP features are + * supported on this GPU. + * + * gspFeatures + * Bit mask that specifies GSP features supported. + * bValid + * If this field is set to NV_TRUE, then above bit mask is + * considered valid. Otherwise, bit mask should be ignored + * as invalid. bValid will be set to NV_TRUE when RM is a + * GSP client with GPU support offloaded to GSP firmware. + * bDefaultGspRmGpu + * If this field is set to NV_TRUE, it indicates that the + * underlying GPU has GSP-RM enabled by default. If set to NV_FALSE, + * it indicates that the GPU has GSP-RM disabled by default. + * firmwareVersion + * This field contains the buffer into which the firmware build version + * should be returned, if GPU is offloaded. Otherwise, the buffer + * will remain untouched. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_GSP_GET_FEATURES (0x20803601) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_GSP_GET_FEATURES_PARAMS_MESSAGE_ID" */ + +#define NV2080_GSP_MAX_BUILD_VERSION_LENGTH (0x0000040) + +#define NV2080_CTRL_GSP_GET_FEATURES_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_GSP_GET_FEATURES_PARAMS { + NvU32 gspFeatures; + NvBool bValid; + NvBool bDefaultGspRmGpu; + NvU8 firmwareVersion[NV2080_GSP_MAX_BUILD_VERSION_LENGTH]; +} NV2080_CTRL_GSP_GET_FEATURES_PARAMS; + +/* Valid feature values */ +#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED 0:0 +#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE (0x00000000) +#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE (0x00000001) + +// _ctrl2080gsp_h_ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h new file mode 100644 index 0000000..f0df6c5 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080hshub.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* + * NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK + * + * This command get active HSHUB masks. + * + * hshubNcisocMask + * NCISOC enabled active HSHUBs + * hshubNvlMask + * NVLINK capable active HSHUBs. + */ + +#define NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS { + NvU32 hshubNcisocMask; + NvU32 hshubNvlMask; +} NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS; + +#define NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK (0x20804101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_HSHUB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID" */ + +/* _ctrl2080hshub_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h new file mode 100644 index 0000000..b3314d9 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h @@ -0,0 +1,365 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080i2c.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX i2c-related control commands and parameters */ + +/* + * NV2080_CTRL_I2C_VERSION + * + * NV2080_CTRL_I2C_VERSION_0_0: + * This return state specifies that support is only available + * for single subAddr reads. + * + */ +#define NV2080_CTRL_I2C_VERSION_0 0x00 + +/* maximum number of i2c entries support */ +#define NV2080_CTRL_I2C_MAX_ENTRIES 256 +#define NV2080_CTRL_I2C_MAX_REG_LEN 8 +#define NV2080_CTRL_I2C_MAX_ADDR_ENTRIES 20 + +/* + * NV2080_CTRL_I2C_FLAGS + * + * NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC: + * This option specified that non-compliant i2c for SI1930UC is required + * + * NV2080_CTRL_I2C_FLAGS_PRIVILEGE + * This option specified that the i2c access is privileged + * + * NV2080_CTRL_I2C_FLAGS_PX3540 + * This option specified that the i2c device -PX3540/3544- is accessed + */ +#define NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC (0x00000001) +#define NV2080_CTRL_I2C_FLAGS_PRIVILEGE (0x00000002) +#define NV2080_CTRL_I2C_FLAGS_DATA_ENCRYPTED (0x00000004) +#define NV2080_CTRL_I2C_FLAGS_PX3540 (0x00000010) +#define NV2080_CTRL_I2C_FLAGS_ADDR_AUTO_INC_NOT_SUPPORTED (0x00000008) + +/* + * NV2080_CTRL_CMD_I2C_READ_BUFFER + * + * This command allocates video memory for a particular subset of microcode. + * + * version + * This field is returned to the client and indicates the current + * supported I2C controls available. + * + * port + * This field must be specified by the client to indicate which port/bus + * in which i2c access is desired. + * + * flags + * This field is specified by the client to request additional options + * as provided by NV2080_CTRL_I2C_FLAGS. + * + * inputCount + * This field specifies the total # of elements contained in inputBuffer + * + * inputBuffer + * This should contain the chipaddr as the first element, followed by + * the each subAddress in which to access the first element of data + * Eg. ... + * In general, client will only have 2 elements + * + * outputCount + * This field specifies how many registers from the start register index. + * The maximum values allow are NV2080_CTRL_I2C_MAX_ENTRIES. + * + * outputBuffer + * This buffer is returned to the client with the data read from + * the start register index. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_STATE_IN_USE + * NV_ERR_INVALID_STATE + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV2080_CTRL_I2C_READ_BUFFER_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_I2C_READ_BUFFER_PARAMS { + NvU32 version; + NvU32 port; + NvU32 flags; + NvU32 inputCount; + // C form: NvU8 inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES]; + NvU8 inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES]; + NvU32 outputCount; + // C form: NvU8 outputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES]; + NvU8 outputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES]; +} NV2080_CTRL_I2C_READ_BUFFER_PARAMS; + +#define NV2080_CTRL_CMD_I2C_READ_BUFFER (0x20800601) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_READ_BUFFER_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_I2C_WRITE_BUFFER + * + * This command allocates video memory for a particular subset of microcode. + * + * version + * This field is returned to the client and indicates the current + * supported I2C controls available. + * + * port + * This field must be specified by the client to indicate which port/bus + * in which i2c access is desired. + * + * flags + * This field is specified by the client to request additional options. + * NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC: + * - Specifies that non-compliant i2c access for SI1930UC is required + * + * inputCount + * This field specifies the total # of elements contained in inputBuffer + * + * inputBuffer + * This should contain the chipaddr as the first element, followed by + * the each subAddress in which to access the first element of data, + * and finally the data to be programmed. + * Eg. ... ... + * In general, client will have 2 elements + data to be programmed. + * ... + * + * encrClientID + * This field is specified by client, which is used to uniquely access + * the client's encryption context + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_STATE_IN_USE + * NV_ERR_INVALID_STATE + * + */ + +#define NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS { + NvU32 version; + NvU32 port; + NvU32 flags; + NvU32 inputCount; + // C form: NvU8 inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES]; + NvU8 inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES]; + NvU32 encrClientID; +} NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS; + +#define NV2080_CTRL_CMD_I2C_WRITE_BUFFER (0x20800602) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS_MESSAGE_ID" */ + + +/* + * NV2080_CTRL_CMD_I2C_READ_REG + * + * This command allocates video memory for a particular subset of microcode. + * + * version + * This field is returned to the client and indicates the current + * supported I2C controls available. + * + * port + * This field must be specified by the client to indicate which port/bus + * in which i2c access is desired. + * + * flags + * This field is specified by the client to request additional options. + * NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC: + * - Specifies that non-compliant i2c access for SI1930UC is required + * addr + * This field is specified by the client to target address. + * reg + * This field is specified by the client to target register address. + * + * bufsize + * This field specifies the total bytes # of register size + * + * buffer + * when used for read, it used as buffer that store returned register content + * when used for write, It include data that will be written. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_STATE_IN_USE + * NV_ERR_INVALID_STATE + * + */ +typedef struct NV2080_CTRL_I2C_RW_REG_PARAMS { + NvU32 version; + NvU32 port; + NvU32 flags; + NvU32 addr; + NvU8 reg; + NvU8 bufsize; + // C form: NvU8 buffer[NV2080_CTRL_I2C_MAX_ENTRIES - 1]; + NvU8 buffer[(NV2080_CTRL_I2C_MAX_ENTRIES - 1)]; +} NV2080_CTRL_I2C_RW_REG_PARAMS; + +// provide NV2080_CTRL_I2C_READ_REG_PARAMS as the historical name +typedef NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_READ_REG_PARAMS; +#define NV2080_CTRL_CMD_I2C_READ_REG (0x20800603) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | 0x3" */ + +#define NV2080_CTRL_CMD_I2C_WRITE_REG (0x20800604) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | 0x4" */ + +/* + * NV006F_CTRL_CMD_SYSTEM_I2C_ACCESS + * + * This command allows Clients to read and write data using the I2C ports + * + * token [IN] + * This used in i2cAcquirePort + * + * cmd [IN] + * The I2CAccess command + * + * port [IN] + * The port ID of the concerned display + * + * flags [IN] + * The I2CAccess Flags such ack,start,stop + * + * data [OUT/IN] + * Data that needs to be pass or read out + * + * dataBuffSize [IN] + * Size of the data buffer. + * + * speed [IN] + * Speed of transaction. + * + * status [OUT] + * The I2CAccess Status returned + * + * encrClientID [IN] + * This field is specified by client, which is used to uniquely access + * the client's encryption context + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_I2C_ACCESS (0x20800610) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV2080_CTRL_I2C_ACCESS_PARAMS { + NvU32 token; + NvU32 cmd; + NvU32 port; + NvU32 flags; + NV_DECLARE_ALIGNED(NvP64 data, 8); + NvU32 status; + NvU32 dataBuffSize; + NvU32 speed; + NvU32 encrClientID; +} NV2080_CTRL_I2C_ACCESS_PARAMS; + +// commands +#define NV2080_CTRL_I2C_ACCESS_CMD_ACQUIRE 0x1 +#define NV2080_CTRL_I2C_ACCESS_CMD_RELEASE 0x2 +#define NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BYTE 0x3 +#define NV2080_CTRL_I2C_ACCESS_CMD_READ_BYTE 0x4 +#define NV2080_CTRL_I2C_ACCESS_CMD_NULL 0x5 +#define NV2080_CTRL_I2C_ACCESS_CMD_RESET 0x6 +#define NV2080_CTRL_I2C_ACCESS_CMD_TEST_PORT 0x11 +#define NV2080_CTRL_I2C_ACCESS_CMD_SET_FAST_MODE 0x12 +#define NV2080_CTRL_I2C_ACCESS_CMD_SET_NORMAL_MODE 0x13 +#define NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BUFFER 0x14 +#define NV2080_CTRL_I2C_ACCESS_CMD_READ_BUFFER 0x15 +#define NV2080_CTRL_I2C_ACCESS_CMD_START 0x17 +#define NV2080_CTRL_I2C_ACCESS_CMD_STOP 0x18 +#define NV2080_CTRL_I2C_ACCESS_CMD_SET_SLOW_MODE 0x20 + +// flags +#define NV2080_CTRL_I2C_ACCESS_FLAG_START 0x1 +#define NV2080_CTRL_I2C_ACCESS_FLAG_STOP 0x2 +#define NV2080_CTRL_I2C_ACCESS_FLAG_ACK 0x4 +#define NV2080_CTRL_I2C_ACCESS_FLAG_RAB 0x8 +#define NV2080_CTRL_I2C_ACCESS_FLAG_ADDR_10BITS 0x10 +#define NV2080_CTRL_I2C_ACCESS_FLAG_PRIVILEGE 0x20 +#define NV2080_CTRL_I2C_ACCESS_FLAG_DATA_ENCRYPTED 0x40 +#define NV2080_CTRL_I2C_ACCESS_FLAG_RESTART 0x80 +#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33_33PCT 0x100 +#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33PCT 0x200 +#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_10PCT 0x400 +#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3_33PCT 0x800 +#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3PCT 0x1000 + +// port +#define NV2080_CTRL_I2C_ACCESS_PORT_DYNAMIC 0x0 +#define NV2080_CTRL_I2C_ACCESS_PORT_PRIMARY 0x1 +#define NV2080_CTRL_I2C_ACCESS_PORT_SECONDARY 0x2 +#define NV2080_CTRL_I2C_ACCESS_PORT_TERTIARY 0x3 +#define NV2080_CTRL_I2C_ACCESS_PORT_QUARTIARY 0x4 + +// Alternate numeric port designators +#define NV2080_CTRL_I2C_ACCESS_PORT_1 0x1 +#define NV2080_CTRL_I2C_ACCESS_PORT_2 0x2 +#define NV2080_CTRL_I2C_ACCESS_PORT_3 0x3 +#define NV2080_CTRL_I2C_ACCESS_PORT_4 0x4 +#define NV2080_CTRL_I2C_ACCESS_PORT_5 0x5 +#define NV2080_CTRL_I2C_ACCESS_PORT_6 0x6 +#define NV2080_CTRL_I2C_ACCESS_PORT_7 0x7 +#define NV2080_CTRL_I2C_ACCESS_PORT_8 0x8 +#define NV2080_CTRL_I2C_ACCESS_PORT_9 0x9 +#define NV2080_CTRL_I2C_ACCESS_PORT_10 0x10 + +// Total ports count +#define NV2080_CTRL_I2C_ACCESS_NUM_PORTS NV2080_CTRL_I2C_ACCESS_PORT_10 + +// status +#define NV2080_CTRL_I2C_ACCESS_STATUS_SUCCESS 0x0 +#define NV2080_CTRL_I2C_ACCESS_STATUS_ERROR 0x1 +#define NV2080_CTRL_I2C_ACCESS_STATUS_PROTOCOL_ERROR 0x2 +#define NV2080_CTRL_I2C_ACCESS_STATUS_DEVICE_BUSY 0x3 +#define NV2080_CTRL_I2C_ACCESS_STATUS_NACK_AFTER_SEND 0x4 +#define NV2080_CTRL_I2C_ACCESS_STATUS_DP2TMDS_DONGLE_MISSING 0x5 + +#define NV2080_CTRL_CMD_I2C_ENABLE_MONITOR_3D_MODE (0x20800620) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS { + NvU32 head; + NvU32 authType; + NvU32 status; +} NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS; + +/* _ctrl2080i2c_h_ */ + + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h new file mode 100644 index 0000000..54a762a --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080illum.finn +// + + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h new file mode 100644 index 0000000..5307f5d --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h @@ -0,0 +1,3176 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080internal.finn +// + +#include "nvimpshared.h" +#include "ctrl/ctrl2080/ctrl2080base.h" + +#include "ctrl/ctrl2080/ctrl2080gpu.h" +#include "ctrl/ctrl2080/ctrl2080gr.h" /* Some controls derivative of 2080gr */ +#include "ctrl/ctrl0080/ctrl0080msenc.h" /* NV0080_CTRL_MSENC_CAPS_TBL_SIZE */ +#include "ctrl/ctrl0080/ctrl0080bsp.h" /* NV0080_CTRL_BSP_CAPS_TBL_SIZE */ +#include "ctrl/ctrl2080/ctrl2080fifo.h" /* NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO */ +#include "ctrl/ctrl0000/ctrl0000system.h" +#include "ctrl/ctrl90f1.h" +#include "ctrl/ctrl30f1.h" + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO + * + * This command obtains information from physical RM for use by CPU-RM. + * + * feHwSysCap + * Display IP v03_00 and later. + * Contents of capability register. + * + * windowPresentMask + * Display IP v03_00 and later. + * Mask for the present WINDOWs actually on the current chip. + * bFbRemapperEnabled + * Display IP v02_01 and later. + * Indicates that the display remapper HW exists and is enabled. + * numHeads + * Display IP v02_01 and later. + * Provides the number of heads HW support. + */ + +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO (0x20800a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS { + NvU32 feHwSysCap; + NvU32 windowPresentMask; + NvBool bFbRemapperEnabled; + NvU32 numHeads; + NvBool bPrimaryVga; + NvU32 i2cPort; + NvU32 internalDispActiveMask; +} NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS; + + + +// +// MemorySystem settings that are static after GPU state init/load is finished. +// +// Fields are shared between the VGPU guest/GSP Client as well as the VGPU +// host/GSP-RM. +// +#define NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID (0x1CU) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS { + /*! Determines if RM should use 1 to 1 Comptagline allocation policy */ + NvBool bOneToOneComptagLineAllocation; + + /*! Determines if RM should use 1 to 4 Comptagline allocation policy */ + NvBool bUseOneToFourComptagLineAllocation; + + /*! Determines if RM should use raw Comptagline allocation policy */ + NvBool bUseRawModeComptaglineAllocation; + + /*! Has COMPBIT_BACKING_SIZE been overridden to zero (i.e. disabled)? */ + NvBool bDisableCompbitBacking; + + /*! Determine if we need to disable post L2 compression */ + NvBool bDisablePostL2Compression; + + /*! Is ECC DRAM feature supported? */ + NvBool bEnabledEccFBPA; + + NvBool bL2PreFill; + + /*! L2 cache size */ + NV_DECLARE_ALIGNED(NvU64 l2CacheSize, 8); + + NvBool bReservedMemAtBottom; + + /*! Indicate whether fpba is present or not */ + NvBool bFbpaPresent; + + /*! Size covered by one comptag */ + NvU32 comprPageSize; + + /*! log32(comprPageSize) */ + NvU32 comprPageShift; + + /*! Maximum number of pages that can be dynamaically blacklisted */ + NvU16 maximumBlacklistPages; + + /*! RAM type */ + NvU32 ramType; + + /*! LTC count */ + NvU32 ltcCount; + + /*! LTS per LTC count */ + NvU32 ltsPerLtcCount; + + /*! Ampere PLC bug */ + NvBool bDisablePlcForCertainOffsetsBug3046774; +} NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS; + +/*! + * Retrieve Memory System Static data. + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_STATIC_CONFIG (0x20800a1c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_REGISTER_UVM_ACCESS_CNTR_BUFFER + * + * This command sends access counter buffer pages allocated by CPU-RM + * to be setup and enabled in physical RM. + * + * bufferSize + * Size of the access counter buffer to register. + * + * bufferPteArray + * Pages of access counter buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER (0x20800a1d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES 64 +#define NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID (0x1DU) + +typedef struct NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS { + NvU32 bufferSize; + NV_DECLARE_ALIGNED(NvU64 bufferPteArray[NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES], 8); +} NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER + * + * This command requests physical RM to disable the access counter buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER (0x20800a1e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x1E" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_UVM_SERVICE_ACCESS_CNTR_BUFFER + * + * This command requests physical RM to service the access counter buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_UVM_SERVICE_ACCESS_CNTR_BUFFER (0x20800a21) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x21" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE + * + * This command retrieves the access counter buffer size from physical RM. + * + * bufferSize[OUT] + * Size of the access counter buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE (0x20800a29) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x29U) + +typedef struct NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS { + NvU32 bufferSize; +} NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS; + +#define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES 8 + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_CAPS_V2 + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS (0x20800a1f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x1F" */ + + + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CAPS { + NvU8 capsTbl[NV0080_CTRL_GR_CAPS_TBL_SIZE]; +} NV2080_CTRL_INTERNAL_STATIC_GR_CAPS; +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_CAPS engineCaps[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER + * @ref NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER (0x20800a22) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x22" */ + + + +#define NV2080_CTRL_INTERNAL_GR_MAX_SM 240 + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER { + struct { + NvU16 gpcId; + NvU16 localTpcId; + NvU16 localSmId; + NvU16 globalTpcId; + NvU16 virtualGpcId; + NvU16 migratableTpcId; + } globalSmId[NV2080_CTRL_INTERNAL_GR_MAX_SM]; + + NvU16 numSm; + NvU16 numTpc; +} NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER globalSmOrder[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS; + + +/*! + * Retrieve BSP Static data. + */ +#define NV2080_CTRL_CMD_INTERNAL_BSP_GET_CAPS (0x20800a24) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_MAX_BSPS 8 + +typedef struct NV2080_CTRL_INTERNAL_BSP_CAPS { + NvU8 capsTbl[NV0080_CTRL_BSP_CAPS_TBL_SIZE]; +} NV2080_CTRL_INTERNAL_BSP_CAPS; + +#define NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS_MESSAGE_ID (0x24U) + +typedef struct NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS { + NV2080_CTRL_INTERNAL_BSP_CAPS caps[NV2080_CTRL_CMD_INTERNAL_MAX_BSPS]; + NvBool valid[NV2080_CTRL_CMD_INTERNAL_MAX_BSPS]; +} NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS; + +/*! + * Retrieve MSENC Static data. + */ +#define NV2080_CTRL_CMD_INTERNAL_MSENC_GET_CAPS (0x20800a25) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS 3 + +typedef struct NV2080_CTRL_INTERNAL_MSENC_CAPS { + NvU8 capsTbl[NV0080_CTRL_MSENC_CAPS_TBL_SIZE]; +} NV2080_CTRL_INTERNAL_MSENC_CAPS; + +#define NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID (0x25U) + +typedef struct NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS { + NV2080_CTRL_INTERNAL_MSENC_CAPS caps[NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS]; + NvBool valid[NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS]; +} NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS; + + +#define NV2080_CTRL_INTERNAL_GR_MAX_GPC 12 +#define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT 10 + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_GPC_MASK + * @ref NV2080_CTRL_CMD_GR_GET_TPC_MASK + * @ref NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS (0x20800a26) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x26" */ + + + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS { + NvU32 gpcMask; + + /*! + * tpcMask is indexed by logical GPC ID for MIG case + * and indexed by physical GPC ID for non-MIG case + */ + NvU32 tpcMask[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; + + /*! + * tpcCount is always indexed by logical GPC ID + */ + NvU32 tpcCount[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; + NvU32 physGpcMask; + NvU32 mmuPerGpc[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; + + NvU32 tpcToPesMap[NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT]; + NvU32 numPesPerGpc[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; + + /*! + * zcullMask is always indexed by physical GPC ID + */ + NvU32 zcullMask[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; + + NvU32 physGfxGpcMask; + NvU32 numGfxTpc; +} NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS { + /*! + * floorsweeping masks which are indexed via local GR index + */ + NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS floorsweepingMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS; + +/* + * NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES + * + * This command returns physical addresses of specified context buffer. + * To obtain addresses of whole buffer firstPage has to be advanced on + * subsequent invocations of the control until whole buffer is probed. + * If the buffer is contiguous, only single address will be returned by + * this control. + * + * bufferType[IN] + * Buffer type as returned by GET_CTX_BUFFER_INFO. + * + * firstPage[IN] + * Index of the first page to return in 'physAddrs' array. + * + * numPages[OUT] + * Number of entries filled in 'physAddrs' array. This will be 0 + * if firstPage is greater or equal to number of pages managed by 'hBuffer'. + * + * physAddrs[OUT] + * Physical addresses of pages comprising specified buffer. + * + * bNoMorePages[OUT] + * End of buffer reached. Either 'physAddrs' contains last page of the + * buffer or 'firstPage' specifies index past the buffer. + */ +#define NV2080_CTRL_KGR_MAX_BUFFER_PTES 128 +#define NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES (0x20800a28) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID (0x28U) + +typedef struct NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS { + NvHandle hUserClient; + NvHandle hChannel; + NvU32 bufferType; + NvU32 firstPage; + NvU32 numPages; + NV_DECLARE_ALIGNED(NvU64 physAddrs[NV2080_CTRL_KGR_MAX_BUFFER_PTES], 8); + NvBool bNoMorePages; +} NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS; + +/*! + * @ref NV0080_CTRL_CMD_GR_GET_INFO + * @ref NV0080_CTRL_CMD_GR_GET_INFO_V2 + * @ref NV2080_CTRL_CMD_GR_GET_INFO + * @ref NV2080_CTRL_CMD_GR_GET_INFO_V2 + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO (0x20800a2a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x2A" */ + + + +/*! + * @ref NV2080_CTRL_GR_INFO + */ +typedef struct NV2080_CTRL_INTERNAL_GR_INFO { + NvU32 index; + NvU32 data; +} NV2080_CTRL_INTERNAL_GR_INFO; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_INFO { + NV2080_CTRL_INTERNAL_GR_INFO infoList[NV0080_CTRL_GR_INFO_MAX_SIZE]; +} NV2080_CTRL_INTERNAL_STATIC_GR_INFO; +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_INFO engineInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_ZCULL_INFO + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO (0x20800a2c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x2C" */ + + + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO { + NvU32 widthAlignPixels; + NvU32 heightAlignPixels; + NvU32 pixelSquaresByAliquots; + NvU32 aliquotTotal; + NvU32 zcullRegionByteMultiplier; + NvU32 zcullRegionHeaderSize; + NvU32 zcullSubregionHeaderSize; + NvU32 subregionCount; + NvU32 subregionWidthAlignPixels; + NvU32 subregionHeightAlignPixels; +} NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO engineZcullInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_ROP_INFO + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO (0x20800a2e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x2E" */ + + + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO { + NvU32 ropUnitCount; + NvU32 ropOperationsFactor; + NvU32 ropOperationsCount; +} NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO engineRopInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_PPC_MASK + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS (0x20800a30) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x30" */ + + + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS { + NvU32 mask[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; +} NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS enginePpcMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES + * @ref NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO (0x20800a32) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x32" */ + + + +#define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT 0x19 + +typedef struct NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO { + NvU32 size; + NvU32 alignment; +} NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO { + NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO engine[NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT]; +} NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO engineContextBuffersInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER (0x20800a34) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x34" */ + + + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER { + NvU8 imla0; + NvU8 fmla16; + NvU8 dp; + NvU8 fmla32; + NvU8 ffma; + NvU8 imla1; + NvU8 imla2; + NvU8 imla3; + NvU8 imla4; +} NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER smIssueRateModifier[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS; + +/* + * NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS + * + * This command obtains information from physical RM for use by CPU-RM. + */ + +#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_CHIP_INFO (0x20800a36) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID" */ + +/* + * Maximum number of register bases to return. + * These are indexed by NV_REG_BASE_* constants from gpu.h, and this value needs + * to be updated if NV_REG_BASE_LAST ever goes over it. See the ct_assert() in gpu.h + */ +#define NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX 16 +#define NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID (0x36U) + +typedef struct NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS { + NvU8 chipSubRev; + NvU32 emulationRev1; + NvBool isCmpSku; + NvU32 bar1Size; + NvU32 pciDeviceId; + NvU32 pciSubDeviceId; + NvU32 pciRevisionId; + NvU32 regBases[NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX]; +} NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS; + +/** + * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE + * + * Set whether or not context switch logging is enabled + * + * bEnable + * Enable/Disable status for context switch logging + */ +#define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE (0x20800a37) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID" */ + +/** + * NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE + * + * Retrieve whether or not context switch logging is enabled + * + * bEnable + * Enable/Disable status for context switch logging + */ +#define NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE (0x20800a38) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID" */ + +typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvBool bEnable; +} NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS; +#define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x37U) + +typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS; +#define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x38U) + +typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS; + +/** + * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET + * + * Set read offset into FECS context switch trace record + * + * offset + * Value indicating number of records by which to offset + */ +#define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET (0x20800a39) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID" */ + +/** + * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET + * + * Set write offset into FECS context switch trace record + * + * offset + * Value indicating number of records by which to offset + */ +#define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET (0x20800a3a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID" */ + +/** + * NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET + * + * Get read offset into FECS context switch trace record + * + * offset + * Value indicating number of records by which to offset + */ + +#define NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET (0x20800a3b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID" */ + +typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvU32 offset; +} NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS; + +#define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x39U) + +typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS; +#define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID (0x3AU) + +typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS; +#define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x3BU) + +typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS; + +/** + * NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE + * + * Get size of FECS record + * + * fecsRecordSize + * Size of FECS record + */ + + + +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE (0x20800a3d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID" */ + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE { + NvU32 fecsRecordSize; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE; + +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID (0x3CU) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE fecsRecordSize[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID (0x3DU) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS; + +/** + * NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES + * + * Get HW defines used to extract information from FECS records + * + * fecsRecordSize + * Size of FECS record + * + * timestampHiTagMask + * Mask for high bits of raw timestamp to extract tag + * + * timestampHiTagShift + * Shift for high bits of raw timestamp to extract tag + * + * timestampVMask + * Mask to extract timestamp from raw timestamp + * + * numLowerBitsZeroShift + * Number of bits timestamp is shifted by + */ + + + +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES (0x20800a3f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x3F" */ + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES { + NvU32 fecsRecordSize; + NvU32 timestampHiTagMask; + NvU8 timestampHiTagShift; + NV_DECLARE_ALIGNED(NvU64 timestampVMask, 8); + NvU8 numLowerBitsZeroShift; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES fecsTraceDefines[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES], 8); +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS; + +/** + * NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE + * + * Parse the DEVICE_INFO2_TABLE on the physical side and return it to kernel. + */ +typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO { + NvU32 faultId; + NvU32 instanceId; + NvU32 typeEnum; + NvU32 resetId; + NvU32 devicePriBase; + NvU32 isEngine; + NvU32 rlEngId; + NvU32 runlistPriBase; + NvU32 groupId; +} NV2080_CTRL_INTERNAL_DEVICE_INFO; +#define NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES 88 + +#define NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE (0x20800a40) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID (0x40U) + +typedef struct NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS { + NvU32 numEntries; + NV2080_CTRL_INTERNAL_DEVICE_INFO deviceInfoTable[NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES]; +} NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP (0x20800a41) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE 4096 +#define NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES 4096 + +#define NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID (0x41U) + +typedef struct NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS { + NvU32 userRegisterAccessMapSize; + NvU32 compressedSize; + NvU8 compressedData[NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE]; + NvU32 profilingRangesSize; + NvU8 profilingRanges[NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES]; +} NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS; + +typedef struct NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO { + NvU32 engDesc; + NvU32 ctxAttr; + NvU32 ctxBufferSize; + NvU32 addrSpaceList; + NvU32 registerBase; +} NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO; +#define NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS 0x40 + +#define NV2080_CTRL_CMD_INTERNAL_GET_CONSTRUCTED_FALCON_INFO (0x20800a42) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID (0x42U) + +typedef struct NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS { + NvU32 numConstructedFalcons; + NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS]; +} NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS; + +/** + * Get GR PDB properties synchronized between Kernel and Physical + * + * bPerSubCtxheaderSupported + * @ref PDB_PROP_GR_SUPPORTS_PER_SUBCONTEXT_CONTEXT_HEADER + */ + + + +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES (0x20800a48) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x48" */ + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES { + NvBool bPerSubCtxheaderSupported; +} NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES pdbTable[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM + * + * This command writes instance memory information in the display hardware registers. + * + * instMemPhysAddr + * GPU physical address or IOVA address of the display instance memory. + * + * instMemSize + * Size of the display instance memory. + * + * instMemAddrSpace + * Address space of the display instance memory. + * + * instMemCpuCacheAttr + * Cache attribute of the display instance memory. + */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM (0x20800a49) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID (0x49U) + +typedef struct NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS { + NV_DECLARE_ALIGNED(NvU64 instMemPhysAddr, 8); + NV_DECLARE_ALIGNED(NvU64 instMemSize, 8); + NvU32 instMemAddrSpace; + NvU32 instMemCpuCacheAttr; +} NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS; + +/* + * NV2080_CTRL_INTERNAL_GPU_RECOVER_ALL_COMPUTE_CONTEXTS + * + * This command issues RC recovery for all compute contexts running on the given GPU. + */ +#define NV2080_CTRL_CMD_INTERNAL_RECOVER_ALL_COMPUTE_CONTEXTS (0x20800a4a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x4A" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION + * + * This command obtains IP version of display engine for use by Kernel RM. + * + * ipVersion + * IP Version of display engine. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED - DISP has been disabled + */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION (0x20800a4b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID (0x4BU) + +typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS { + NvU32 ipVersion; +} NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE + * + * This command determines the current status of MIG MODE from Physical RM. + * + * smcMode [OUT] + * Current MIG MODE of the GPU. Values range NV2080_CTRL_GPU_INFO_GPU_SMC_MODE* + */ +#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE (0x20800a4c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID (0x4CU) + +typedef struct NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS { + NvU32 smcMode; +} NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR + * + * head + * This parameter specifies the head for which the callback is to be registered/unregistered. This value must be + * less than the maximum number of heads supported by the GPU subdevice. + * + * rgLineNum + * This indicates the RG scanout line number on which the callback will be executed. + * + * intrLine + * Enable: [out] Which interrupt line was allocated for this head. + * Disable: [in] Which interrupt line to deallocate. + * + * bEnable + * Should we allocate or deallocate an interrupt line? + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC - There was no available interrupt to allocate. + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR (0x20800a4d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID (0x4DU) + +typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS { + NvU32 head; + NvU32 rgLineNum; + NvU32 intrLine; + NvBool bEnable; +} NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS; + +/*! + * NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO + * + * Description of a supported GPU instance. + * + * partitionFlag [OUT] + * Allocation flag to be used to allocate a partition with this profile. + * + * grCount [OUT] + * # GR engines, including the GFX capable ones. + * + * gfxGrCount [OUT] + * # GR engines capable of Gfx, which is a subset of the GR engines included in grCount + * + * gpcCount [OUT] + * # total gpcs, including the GFX capable ones. + * + * virtualGpcCount [OUT] + * # virtualized gpcs, including the GFX capable ones. + * + * gfxGpcCount [OUT] + * # total gpcs capable of Gfx. This is a subset of the GPCs included in gpcCount. + * + * veidCount [OUT] + * # total veids + * + * smCount [OUT] + * # total SMs + * + * ceCount [OUT] + * # CE engines + * + * nvEncCount [OUT] + * # NVENC engines + * + * nvDecCount [OUT] + * # NVDEC engines + * + * nvJpgCount [OUT] + * # NVJPG engines + * + * nvOfaCount [OUT] + * # NVOFA engines + * + * validCTSIdMask [OUT] + * # mask of CTS IDs which can be assigned under this profile + */ +#define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 20 + + + +typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO { + NvU32 partitionFlag; + NvU32 grCount; + NvU32 gfxGrCount; + NvU32 gpcCount; + NvU32 virtualGpcCount; + NvU32 gfxGpcCount; + NvU32 veidCount; + NvU32 smCount; + NvU32 ceCount; + NvU32 nvEncCount; + NvU32 nvDecCount; + NvU32 nvJpgCount; + NvU32 nvOfaCount; + NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8); +} NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO; + +/*! + * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS + * + * Returns the list of supported GPU instance profiles. + * + * count [OUT] + * Number of supported profiles. + * + * table [OUT] + * Supported profiles. + */ +typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS { + NvU32 count; + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO table[NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES], 8); +} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM + * + * This command instructs the physical MemorySystem to set up memory partitioning + * exterior boundaries in hardware. + * + * partitionableMemSize [input] + * Size of the partitionable memory in bytes + * + * bottomRsvdSize [input] + * Size of the reserved region below partitionable memory in bytes + * + * topRsvdSize [input] + * Size of the reserved region above partitionable memory in bytes + * + * partitionableStartAddr [output] + * Start address of the partitionable memory, aligned to HW constraints + * + * partitionableEndAddr [output] + * End address of the partitionable memory, aligned to HW constraints + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM (0x20800a51) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID (0x51U) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS { + NV_DECLARE_ALIGNED(NvU64 partitionableMemSize, 8); + NV_DECLARE_ALIGNED(NvU64 bottomRsvdSize, 8); + NV_DECLARE_ALIGNED(NvU64 topRsvdSize, 8); + NV_DECLARE_ALIGNED(NvU64 partitionableStartAddr, 8); + NV_DECLARE_ALIGNED(NvU64 partitionableEndAddr, 8); +} NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS; + + + +typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS { + NV_DECLARE_ALIGNED(NvU64 engineMask, 8); +} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS; + + +/*! + * NV2080_CTRL_INTERNAL_MEMDESC_INFO + * + * A generic container structure representing a memory region to be used as a + * component of other control call parameters. + * + */ +typedef struct NV2080_CTRL_INTERNAL_MEMDESC_INFO { + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NV_DECLARE_ALIGNED(NvU64 alignment, 8); + NvU32 addressSpace; + NvU32 cpuCacheAttrib; +} NV2080_CTRL_INTERNAL_MEMDESC_INFO; + +#define NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS 2 +#define NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID 64 +/*! + * NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS + * + * Promote a single partition's runlist buffers allocated by kernel Client RM to Physical RM + * + * rlBuffers [IN] + * 2D array of runlist buffers for a single partition + * + * runlistIdMask [IN] + * Mask of runlists belonging to partition + * + */ +#define NV2080_CTRL_CMD_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS (0x20800a53) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID (0x53U) + +typedef struct NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MEMDESC_INFO rlBuffers[NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID][NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS], 8); + NV_DECLARE_ALIGNED(NvU64 runlistIdMask, 8); + NvU32 swizzId; +} NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_SET_IMP_INIT_INFO (0x20800a54) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID (0x54U) + +typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS { + TEGRA_IMP_IMPORT_DATA tegraImpImportData; +} NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR + * + * This command triggers a sysmembar to flush VIDMEM writes. + * This command accepts no parameters. + * + */ +#define NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR (0x20800a70) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x70" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL + * + * Setup local PCIE P2P Mailbox + * + * local2Remote[IN] + * Local peer ID of remote gpu on local gpu + * + * remote2Local[IN] + * Remote peer ID of local gpu on remote gpu + * + * localP2PDomainRemoteAddr[IN] + * P2P domain remote address on local gpu + * + * remoteP2PDomainLocalAddr[IN] + * P2P domain local address on remote gpu + * + * remoteWMBoxLocalAddr[IN] + * Local mailbox address on remote gpu + * + * p2pWmbTag[OUT] + * Tag for mailbox to transport from local to remote GPU + * + * bNeedWarBug999673[IN] + * Set to true if WAR for bug 999673 is required + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL (0x20800a71) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID (0x71U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS { + NvU32 local2Remote; + NvU32 remote2Local; + NV_DECLARE_ALIGNED(NvU64 localP2PDomainRemoteAddr, 8); + NV_DECLARE_ALIGNED(NvU64 remoteP2PDomainLocalAddr, 8); + NV_DECLARE_ALIGNED(NvU64 remoteWMBoxLocalAddr, 8); + NV_DECLARE_ALIGNED(NvU64 p2pWmbTag, 8); + NvBool bNeedWarBug999673; +} NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS; + + /* + * NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE + * + * Setup remote PCIE P2P Mailbox + * + * local2Remote[IN] + * Local peer ID of remote gpu on local gpu + * + * remote2Local[IN] + * Remote peer ID of local gpu on remote gpu + * + * localP2PDomainRemoteAddr[IN] + * P2P domain remote address on local gpu + * + * remoteP2PDomainLocalAddr[IN] + * P2P domain local address on remote gpu + * + * remoteWMBoxAddrU64[IN] + * Mailbox address on remote gpu + * + * p2pWmbTag[IN] + * Tag for mailbox to transport from local to remote GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE (0x20800a72) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID (0x72U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS { + NvU32 local2Remote; + NvU32 remote2Local; + NV_DECLARE_ALIGNED(NvU64 localP2PDomainRemoteAddr, 8); + NV_DECLARE_ALIGNED(NvU64 remoteP2PDomainLocalAddr, 8); + NV_DECLARE_ALIGNED(NvU64 remoteWMBoxAddrU64, 8); + NV_DECLARE_ALIGNED(NvU64 p2pWmbTag, 8); +} NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX + * + * Destroy PCIE P2P Mailbox + * + * peerIdx[IN] + * Peer ID of the P2P destination GPU + * + * bNeedWarBug999673[IN] + * Set to true if WAR for bug 999673 is required + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX (0x20800a73) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID (0x73U) + +typedef struct NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS { + NvU32 peerIdx; + NvBool bNeedWarBug999673; +} NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING + * + * Create C2C mapping to a given peer GPU + * + * peerId[IN] + * Peer ID for local to remote GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING (0x20800a74) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID (0x74U) + +typedef struct NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS { + NvU32 peerId; +} NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING + * + * Remove C2C mapping to a given peer GPU + * + * peerId[IN] + * Peer ID for local to remote GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING (0x20800a75) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID (0x75U) + +typedef struct NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS { + NvU32 peerId; +} NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES + * + * Retrieves the corresponding SPAs (per the given GFID's VMMU mappings) + * for the given array of GPAs. + * + * gfid [IN] + * GFID to translate GPAs for + * + * numEntries [IN] + * Number of entries (<= NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES) + * to translate (i.e. number of elements in gpaEntries) + * + * gpaEntries [IN] + * Array of GPAs to translate + * + * spaEntries [OUT] + * Resulting array of SPAs + */ +#define NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES (0x20800a57) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES 128 + +#define NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID (0x57U) + +typedef struct NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS { + NvU32 gfid; + NvU32 numEntries; + NV_DECLARE_ALIGNED(NvU64 gpaEntries[NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES], 8); + NV_DECLARE_ALIGNED(NvU64 spaEntries[NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES], 8); +} NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER + * + * Pass required pushbuffer parameters from kernel RM to Physical RM + * + * addressSpace [IN] + * Address space of pushbuffer whtether it is ADDR_SYSMEM or ADDR_FBMEM + * + * physicalAddr [IN] + * Physical address of pushbuffer + * + * addressSpace [IN] + * Limit of the pushbuffer address, it should be less than 4K + * + * cacheSnoop [IN] + * Cachesnoop supported or not + * + * channelInstance [IN] + * Channel instance pass by the client to get corresponding dispchannel + * + * hclass [IN] + * External class ID pass by the client to get the channel class + * + * valid [IN] + * This bit indicates whether pushbuffer parameters are valid or not + * + */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER (0x20800a58) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID (0x58U) + +typedef struct NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS { + NvU32 addressSpace; + NV_DECLARE_ALIGNED(NvU64 physicalAddr, 8); + NV_DECLARE_ALIGNED(NvU64 limit, 8); + NvU32 cacheSnoop; + NvU32 hclass; + NvU32 channelInstance; + NvBool valid; +} NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO + * + * This command obtains information from physical RM for use by CPU-RM. + * + * replayableFaultBufferSize + * Default size of replayable fault buffer + * + * nonReplayableFaultBufferSize + * Default size of non-replayable fault buffer + * + */ + +#define NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO (0x20800a59) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0x59U) + +typedef struct NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS { + NvU32 replayableFaultBufferSize; + NvU32 nonReplayableFaultBufferSize; +} NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_CTXSW_MODES + */ +#define NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES (0x20800a5a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x5A" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE + * + * Get heap reservation size needed by different module + */ +#define NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE (0x20800a5b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID (0x5BU) + +typedef struct NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS { + NvU32 moduleIndex; + NvU32 size; +} NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE + * + * tableLen [OUT] + * Number of valid records in table field. + * + * table [OUT] + * Interrupt table for Kernel RM. + */ +#define NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE (0x20800a5c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE 128 + +typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY { + NvU16 engineIdx; + NvU32 pmcIntrMask; + NvU32 vectorStall; + NvU32 vectorNonStall; +} NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY; + +#define NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID (0x5CU) + +typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS { + NvU32 tableLen; + NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY table[NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE]; +} NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS; + +/* Index to retrieve the needed heap space for specific module */ +#define NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_GR (0x00000000) + +/* + * NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK + * + * Checking if the reservation / release of the PERFMON HW is possible + * + * bReservation [IN] + * NV_TRUE -> request for reservation, NV_FALSE -> request for release + * + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK (0x20800a98) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID" */ + + +#define NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID (0x98U) + +typedef struct NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS { + NvBool bReservation; +} NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET + * + * Reserving / Releasing PERFMON HW + * + * bReservation [IN] + * NV_TRUE -> request for reservation, NV_FALSE -> request for release + * + * bClientHandlesGrGating [IN] + * DM-TODO: Add comment for this + * + * bRmHandlesIdleSlow [IN] + * If the IDLE slowdown is required + * + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET (0x20800a99) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID (0x99U) + +typedef struct NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS { + NvBool bReservation; + NvBool bClientHandlesGrGating; + NvBool bRmHandlesIdleSlow; +} NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES + * + * Get active display devices + * + * displayMask [OUT] + * Get the mask of the active display devices in VBIOS + * + * numHeads [OUT] + * Number of heads display supported. + * + */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES (0x20800a5d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID (0x5DU) + +typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS { + + NvU32 displayMask; + NvU32 numHeads; +} NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS; + + + +/* + * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES + * + * Get FB Mem page ranges for all possible swizzIds + * + * fbMemPageRanges [OUT] + * Mem page ranges for each swizzId in the form of {lo, hi} + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a60) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID 15 + +typedef struct NV2080_CTRL_INTERNAL_NV_RANGE { + NV_DECLARE_ALIGNED(NvU64 lo, 8); + NV_DECLARE_ALIGNED(NvU64 hi, 8); +} NV2080_CTRL_INTERNAL_NV_RANGE; + +#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x60U) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NV_RANGE fbMemPageRanges[NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID], 8); +} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS + * + * This command is an internal command sent from Kernel RM to Physical RM + * to get number of channels for a given runlist ID + * + * runlistId [IN] + * numChannels [OUT] + */ +#define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS (0x20800a61) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID (0x61U) + +typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS { + NvU32 runlistId; + NvU32 numChannels; +} NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES + * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PROFILES + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES (0x20800a63) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x63" */ + +/*! + * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK + * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_VALID_SWIZZID_MASK + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK (0x20800a64) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x64" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES + * NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES (0x20800a65) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x65" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES + * NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a66) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x66" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG + * + * This command retrieves memory config from HW + * + * memBoundaryCfgA [OUT] + * Memory boundary config A (4KB aligned) + * + * memBoundaryCfgB [OUT] + * Memory boundary config B (4KB aligned) + * + * memBoundaryCfgC [OUT] + * Memory boundary config C (64KB aligned) + * + * memBoundaryCfg [OUT] + * Memory boundary config (64KB aligned) + * + * memBoundaryCfgValInit [OUT] + * Memory boundary config initial value (64KB aligned) + */ +#define NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a67) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x67" */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a68) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x68" */ + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS { + NV_DECLARE_ALIGNED(NvU64 memBoundaryCfgA, 8); + NV_DECLARE_ALIGNED(NvU64 memBoundaryCfgB, 8); + NvU32 memBoundaryCfgC; + NvU32 memBoundaryCfg; + NvU32 memBoundaryCfgValInit; +} NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE (0x20800a6b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE 8 + +#define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID (0x6BU) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS { + NvU32 data[NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE]; +} NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT + * + * Invoke RC recovery after watchdog timeout is hit. + */ +#define NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT (0x20800a6a) /* finn: Evaluated from "((FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6a)" */ + +/* ! + * This command disables cuda limit activation at teardown of the client. + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE (0x20800a7a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7A" */ + +/* + * This command is cleaning up OPTP when a client is found to have + * been terminated unexpectedly. + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_OPTP_CLI_CLEAR (0x20800a7c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7C" */ + +/* ! + * This command is used to get the current AUX power state of the sub-device. + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_GET_AUX_POWER_STATE (0x20800a81) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS { + NvU32 powerState; +} NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS; + +/*! + * This command can be used to boost P-State up one level or to the highest for a limited + * duration for the associated subdevice. Boosts from different clients are being tracked + * independently. Note that there are other factors that can limit P-States so the resulting + * P-State may differ from expectation. + * + * flags + * This parameter specifies the actual command. _CLEAR is to clear existing boost. + * _BOOST_1LEVEL is to boost P-State one level higher. _BOOST_TO_MAX is to boost + * to the highest P-State. + * duration + * This parameter specifies the duration of the boost in seconds. This has to be less + * than NV2080_CTRL_PERF_BOOST_DURATION_MAX. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_2X (0x20800a9a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID (0x9AU) + +typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X { + + NvBool flags; + NvU32 duration; +} NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X; + +#define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_PSTATE 0U +#define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK 1U +#define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK +#define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM (0x2U) /* finn: Evaluated from "NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST + 1" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL + * + * Activate/Deactivate GPU Boost Sync algorithm + * + * bActivate [IN] + * GPU Boost Sync algorithm: + * NV_TRUE -> activate + * NV_FALSE -> deactivate + * + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL (0x20800a7e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID (0x7EU) + +typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS { + NvBool bActivate; +} NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS + * + * Apply given limits to a specific subdevice + * + * flags [IN] + * DM-TODO: write description here + * + * bBridgeless [IN] + * Bridgeless information, for now supporting only MIO bridges + * + * currLimits + * Array of limits that will be applied + * + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS (0x20800a7f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID (0x7FU) + +typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS { + NvU32 flags; + NvBool bBridgeless; + NvU32 currLimits[NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM]; +} NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO + * + * Data for GPU Boost Sync structure initialization + * + * hysteresisus [OUT] + * Hysteresis value for GPU Boost synchronization hysteresis algorithm. + * + * bHystersisEnable [OUT] + * hysteresis algorithm for SLI GPU Boost synchronization: + * NV_TRUE -> enabled, + * NV_FALSE -> disabled + * + * bSliGpuBoostSyncEnable [OUT] + * SLI GPU Boost feature is: + * NV_TRUE -> enabled, + * NV_FALSE -> disabled + * + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO (0x20800a80) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID (0x80U) + +typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 hysteresisus, 8); + NvBool bHystersisEnable; + NvBool bSliGpuBoostSyncEnable; +} NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER + * + * This command sends replayable fault buffer pages allocated by CPU-RM + * to be setup and enabled in physical RM. + * + * hClient + * Client handle. + * + * hObject + * Object handle. + * + * faultBufferSize + * Size of the replayable fault buffer to register. + * + * faultBufferPteArray + * Pages of replayable fault buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER (0x20800a9b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES 256 +#define NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9BU) + +typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS { + NvHandle hClient; + NvHandle hObject; + NvU32 faultBufferSize; + NV_DECLARE_ALIGNED(NvU64 faultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES], 8); +} NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER + * + * This command requests physical RM to disable the replayable fault buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER (0x20800a9c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x9C" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER + * + * This command sends client shadow fault buffer pages allocated by CPU-RM + * to be setup and enabled in physical RM. + * + * shadowFaultBufferQueuePhysAddr + * Physical address of shadow fault buffer queue. + * + * faultBufferSize + * Size of the client shadow fault buffer to register. + * + * shadowFaultBufferPteArray + * Pages of client shadow fault buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES 1500 +#define NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9DU) + +typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS { + NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferQueuePhysAddr, 8); + NvU32 shadowFaultBufferSize; + NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES], 8); +} NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER + * + * Pin PDEs for Global VA range on the server RM and then mirror the client's page + * directory/tables in the server. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER (0x20800a9f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID (0x9FU) + +typedef struct NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS { + NV_DECLARE_ALIGNED(NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS PdeCopyParams, 8); +} NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER + * + * This command requests physical RM to disable the client shadow fault buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x9E" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X + * + * This command can be used to boost P-State the highest for a limited + * duration for the associated subdevice. Boosts from different clients are being tracked + * independently. Note that there are other factors that can limit P-States so the resulting + * P-State may differ from expectation. + * + * flags [IN] + * This parameter specifies the actual command. _CLEAR is to clear existing boost. + * and _BOOST_TO_MAX is to boost to the highest P-State. + * + * boostDuration [IN] + * This parameter specifies the duration of the boost in seconds. This has to be less + * than NV2080_CTRL_PERF_BOOST_DURATION_MAX. + * + * gfId [IN] + * This specifies Id of the Kernel RM that is requesting the Boost + * + * bOverrideInfinite[IN] + * This parameter specifies if we want to override already registered infinite boost for the specific Kernel RM. + * This should be NV_TRUE only in case when we are removing the current infinite boost for a specific Kernel RM + * and setting the boost duration to a next maximum duration registered for the Kernel RM in question. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X (0x20800aa0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID (0xA0U) + +typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X { + NvU32 flags; + NvU32 boostDuration; + NvU32 gfId; + NvBool bOverrideInfinite; +} NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X + * + * Clear the boost for specific Kernel RM + * + * bIsCudaClient [IN] + * Specifies if the request is for clearing the CUDA boost or regular boost + * NV_TRUE -> CUDA boost, NV_FALSE otherwise + * + * gfId [IN] + * Specifies Id of the Kernel RM that is requesting Boost clear + * + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X (0x20800aa1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID (0xA1U) + +typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X { + + NvBool bIsCudaClient; + NvU32 gfId; +} NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X; + +/* + * NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO + * + * Retrieves skyline information about the GPU. Params are sized to currently known max + * values, but will need to be modified in the future should that change. + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO (0x20800aa2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES 8 +#define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS 8 +/*! + * NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO + * skylineVgpcSize[OUT] + * - TPC count of non-singleton VGPCs + * singletonVgpcMask[OUT] + * - Mask of active Singletons + * maxInstances[OUT] + * - Max allowed instances of this skyline concurrently on a GPU + * computeSizeFlag + * - One of NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* flags which is associated with this skyline + * numNonSingletonVgpcs + * - Number of VGPCs with non-zero TPC counts which are not singletons + */ +typedef struct NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO { + NvU8 skylineVgpcSize[NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS]; + NvU32 singletonVgpcMask; + NvU32 maxInstances; + NvU32 computeSizeFlag; + NvU32 numNonSingletonVgpcs; +} NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO; + +/*! + * NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS + * skylineTable[OUT] + * - TPC count of non-singleton VGPCs + * - Mask of singleton vGPC IDs active + * - Max Instances of this skyline possible concurrently + * - Associated compute size with the indexed skyline + * - Number of VGPCs with non-zero TPC counts which are not singletons + * validEntries[OUT] + * - Number of entries which contain valid info in skylineInfo + */ +#define NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID (0xA2U) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS { + NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO skylineTable[NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES]; + NvU32 validEntries; +} NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE + */ +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE (0x20800aa3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA3" */ + +/*! + * @ref NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION + */ +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE (0x20800aa4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA4" */ + +/*! + * @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONS + */ +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES (0x20800aa5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA5" */ + +/*! + * @ref NV2080_CTRL_CMD_GPU_GET_PARTITIONS + */ +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES (0x20800aa6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA6" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED + * + * Tell Physical RM whether any ZBC-kind surfaces are allocated. + * If PF and all VFs report false, ZBC table can be flushed by Physical RM. + * + * bZbcReferenced [IN] + * NV_TRUE -> ZBC-kind (and no _SKIP_ZBCREFCOUNT flag) are allocated in Kernel RM + * + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED (0x20800a69) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID (0x69U) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS { + NvBool bZbcSurfacesExist; +} NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE + * + * Export the resource and placement information about a gpu instance such that a + * similar gpu instance can be recreated from scratch in the same position on the + * same or similar GPU. Note that different GPUs may have different physical + * resources due to floorsweeping, and an imported gpu instance is not guaranteed + * to get the exact same resources as the exported gpu instance, but the imported + * gpu instance should behave identically with respect to fragmentation and + * placement / span positioning. + */ +#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE (0x20800aa7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA7" */ +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE (0x20800aa8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA8" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE + * + * Create a gpu instance resembling the exported instance info. Note that + * different GPUs may have different physical resources due to floorsweeping, + * and an imported gpu instance is not guaranteed to get the exact same resources + * as the exported gpu instance, but the imported gpu instance should behave + * identically with respect to fragmentation and placement / span positioning. + */ +#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE (0x20800aa9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA9" */ +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE (0x20800aaa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xAA" */ + +#define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE 4 +typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO { + NV_DECLARE_ALIGNED(NvU64 enginesMask[NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE], 8); + NvU32 partitionFlags; + NvU32 gpcMask; + NvU32 virtualGpcCount; + NvU32 veidOffset; + NvU32 veidCount; +} NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO; + +typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS { + NvU32 swizzId; + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO info, 8); +} NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT + * + * Invalidate and/or evict the L2 cache + * + * flags [IN] + * flags that specify required actions + * + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT (0x20800a6c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID (0x6cU) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS { + NvU32 flags; +} NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS; + +#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL (0x00000001) +#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_FIRST (0x00000002) +#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_LAST (0x00000004) +#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_NORMAL (0x00000008) +#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_CLEAN (0x00000010) +#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_WAIT_FB_PULL (0x00000020) + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES + * + * Flush all L2 Rams and Caches using the ELPG flush + * + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES (0x20800a6d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6D" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO + * + * This command obtains information from physical RM for use by CPU-RM + * + * Data fields -> + * bPcieGen4Capable - tells whether PCIe is Gen4 capable + */ +#define NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO (0x20800aac) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0xacU) + +typedef struct NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS { + NvBool bPcieGen4Capable; + NvBool bIsC2CLinkUp; + NV_DECLARE_ALIGNED(NvU64 dmaWindowStartAddress, 8); +} NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG + * + * Program HSHUB Peer Conn Config space. + * + * programPeerMask[IN] + * If nonzero, the peer mask for programming peers based on hshub connectivity. + * + * invalidatePeerMask[IN] + * If nonzero, the peer mask for invalidating peers. + * + * programPciePeerMask[IN] + * If nonzero, the peer mask for programming peers in pcie case. + * + * Possible status values returned are: + * NV_OK + * NV_WARN_NOTHING_TO_DO + * If all peer masks are zero. + */ +#define NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG (0x20800a88) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID (0x88U) + +typedef struct NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS { + NvU32 programPeerMask; + NvU32 invalidatePeerMask; + NvU32 programPciePeerMask; +} NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_HSHUB_FIRST_LINK_PEER_ID + * + * Given a mask of link ids, find the first with a valid peerId. + * + * linkMask[IN] + * Mask of linkIds to check. + * + * peerId[OUT] + * The peerId for the lowest-index link with a valid peerId, if any. + * If none found, NV2080_CTRLINTERNAL_HSHUB_FIRST_LINK_PEER_ID_INVALID_PEER (return value will still be NV_OK). + * + * Possible status values returned are: + * NV_OK + * + */ +#define NV2080_CTRL_CMD_INTERNAL_HSHUB_FIRST_LINK_PEER_ID (0x20800a89) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_INVALID_PEER 0xffffffff + +#define NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS_MESSAGE_ID (0x89U) + +typedef struct NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS { + NvU32 linkMask; + NvU32 peerId; +} NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS + * + * Get the Hshub Ids connected to the other end of links. + * + * linkMask[IN] + * A mask of link ids to query. + * + * hshubIds[OUT] + * For each set bit in the link mask, the peer Hshub Id. + * + * Possible status values returned are: + * NV_OK + * NV_WARN_NOTHING_TO_DO + * If the mask is zero. + */ +#define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS (0x20800a8a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE 32 + +#define NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID (0x8aU) + +typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS { + NvU32 linkMask; + NvU8 hshubIds[NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE]; +} NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS + * + * Return the number of HSHUB units. + * + * numHshubs[OUT] + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS (0x20800a8b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID (0x8bU) + +typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS { + NvU32 numHshubs; +} NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID + * + * Return the next hshubId after the given hshubId. + * + * hshubId[IN/OUT] + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID (0x20800a8c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID (0x8cU) + +typedef struct NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS { + NvU8 hshubId; +} NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR + * + * Enable compute peer addressing mode + * This command accepts no parameters. + */ + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR (0x20800aad) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xad" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR + * + * Get/Set NVSwitch fabric address for FLA + * + * [In] bGet + * Whether to get or set the NVSwitch fabric address + * [In/Out] addr + * Address that is to be set or retrieved. + */ +#define NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID (0xaeU) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS { + NvBool bGet; + NV_DECLARE_ALIGNED(NvU64 addr, 8); +} NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR (0x20800aae) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_BIF_GET_ASPM_L1_FLAGS + * + * This command obtains information from physical RM for use by CPU-RM + * + * Data fields -> + * bCyaMaskL1 + * bEnableAspmDtL1 + */ +#define NV2080_CTRL_CMD_INTERNAL_BIF_GET_ASPM_L1_FLAGS (0x20800ab0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS_MESSAGE_ID (0xb0U) + +typedef struct NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS { + NvBool bCyaMaskL1; + NvBool bEnableAspmDtL1; +} NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT + * + * Sets number of VM slots that are active in VGPU's scheduler + * + * maxActiveVGpuVMCount [IN] + * Number of VM slots that are active in vGPU's scheduler. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OUT_OF_RANGE - Passed value is out of range + * NV_ERR_NO_MEMORY - Out of memory + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT (0x20800ab1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID" */ + +/*! + * Maximum value of VM slots that are active in vGPU's scheduler. + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_MAX_ACTIVE_VGPU_VM_COUNT_MAX_VALUE 32 + +#define NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID (0xB1U) + +typedef struct NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS { + NvU8 maxActiveVGpuVMCount; +} NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS + * + * Disable all NVLINK FB peers + * + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS (0x20800a6e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6E" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE + * + * Program GPU in raw / legacy compression mode + * + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE (0x20800a6f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID (0x6fU) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS { + NvBool bRawMode; +} NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_CCU_MAP + * + * This command gets the shared buffer memory descriptor from the CPU-RM and maps to it + * in physical-RM. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_ADDRESS + */ +#define NV2080_CTRL_CMD_INTERNAL_CCU_MAP (0x20800ab3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX 1 +#define NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID (0xB3U) + +typedef struct NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 phyAddr[NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE + NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX], 8); +} NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS; +/* + * NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP + * + * This command unmaps the shared buffer memory mapping in physical-RM + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP (0x20800ab4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID (0xB4U) + +typedef struct NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS { + NvBool bDevShrBuf; + NvBool bMigShrBuf; +} NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS; + +/*! + * NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO + * + * [in] gpuId + * GPU ID. + * [in] gpuInstance + * GPU instance. + * [in] p2pCaps + * Peer to peer capabilities discovered between the GPUs. + * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. + * [in] p2pOptimalReadCEs + * Mask of CEs to use for p2p reads over Nvlink. + * [in] p2pOptimalWriteCEs + * Mask of CEs to use for p2p writes over Nvlink. + * [in] p2pCapsStatus + * Status of all supported p2p capabilities. + * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. + * [in] busPeerId + * Bus peer ID. For an invalid or a non-existent peer this field + * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. + */ +typedef struct NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO { + NvU32 gpuId; + NvU32 gpuInstance; + NvU32 p2pCaps; + NvU32 p2pOptimalReadCEs; + NvU32 p2pOptimalWriteCEs; + NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; + NvU32 busPeerId; +} NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO; + +/*! + * NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS + * + * An internal call to propagate the peer to peer capabilities of peer GPUs + * to the Physical RM. These capabilities are to be consumed by the vGPU GSP plugin. + * This control is used to both add and and update the peer to peer capabilities. + * The existing GPU entries will be updated and those which don't exist will be added. + * Use NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS to remove the added entries. + * + * [in] peerGpuCount + * The number of the peerGpuInfos entries. + * [in] peerGpuInfos + * The array of NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS entries, describing + * the peer to peer capabilities of the specified GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT - Invalid peerGpuCount + * NV_ERR_INSUFFICIENT_RESOURCES - Total GPU count exceeds the maximum value + */ +#define NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS (0x20800ab5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID (0xB5U) + +typedef struct NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS { + NvU32 peerGpuCount; + NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO peerGpuInfos[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; +} NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS + * + * An internal call to remove the cached peer to peer capabilities of peer GPUs + * from the Physical RM. + * + * [in] peerGpuIdCount + * The number of the peerGpuIds entries. + * [in] peerGpuIds + * The array of GPU IDs, specifying the GPU for which the entries need to be removed. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT - Invalid peerGpuIdCount + * NV_ERR_OBJECT_NOT_FOUND - Invalid peerGpuIds[] entry + */ +#define NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS (0x20800ab6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID (0xB6U) + +typedef struct NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS { + NvU32 peerGpuIdCount; + NvU32 peerGpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; +} NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS; + + + +/*! + * NV2080_CTRL_CMD_INTERNAL_BUS_GET_PCIE_P2P_CAPS + * + * This command returns the GPU's PCIE P2P caps + * + * [in] bCommonPciSwitchFound + * All GPUs are under the same PCI switch + * [out] p2pReadCapsStatus + * [out] p2pWriteCapsStatus + * These members returns status of all supported p2p capabilities. Valid + * status values include: + * NV0000_P2P_CAPS_STATUS_OK + * P2P capability is supported. + * NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED + * Chipset doesn't support p2p capability. + * NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED + * GPU doesn't support p2p capability. + * NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED + * IOH topology isn't supported. For e.g. root ports are on different + * IOH. + * NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY + * P2P Capability is disabled by a regkey. + * NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED + * P2P Capability is not supported. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_INTERNAL_GET_PCIE_P2P_CAPS (0x20800ab8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID (0xB8U) + +typedef struct NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS { + NvBool bCommonPciSwitchFound; + NvU8 p2pReadCapsStatus; + NvU8 p2pWriteCapsStatus; +} NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO + * + * Enable/disable PCIe Relaxed Ordering. + * + */ +#define NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO (0x20800ab9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID (0xB9U) + +typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS { + // Enable/disable PCIe relaxed ordering + NvBool enableRo; +} NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE + * + * An internal call to invoke the sequence VGA register reads & writes to + * perform save and restore of VGA + * + * [in] saveOrRestore + * To indicate whether save or restore needs to be performed. + * [in] useVbios + * Primary VGA indication from OS. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE (0x20800a76) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS_MESSAGE_ID (0x76U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS { + + NvBool bSaveOrRestore; + NvBool bUseVbios; +} NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE + * + * To perform restore operation from saved fonts. + * + * [in] saveOrRestore + * To indicate whether save or restore needs to be performed. + * [in] useVbios + * Primary VGA indication from OS. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE (0x20800a77) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS_MESSAGE_ID (0x77U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS { + + NvBool bWriteCr; +} NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES + * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xba" */ + +/*! + * NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE + * + * This structure specifies resources in an execution partition + * + * computeSize[OUT] + * - NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* associated with this profile + * + * gfxGpcCount[OUT] + * - Total Number of GFX Supporting GPCs in this partition + * + * gpcCount[OUT] + * - Total Number of GPCs in this partition (including GFX Supported GPCs) + * + * veidCount[OUT] + * - Number of VEIDs allocated to this profile + * + * smCount[OUT] + * - Number of SMs usable in this profile + */ +typedef struct NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE { + NvU8 computeSize; + NvU32 gfxGpcCount; + NvU32 gpcCount; + NvU32 veidCount; + NvU32 smCount; + NvU32 physicalSlots; +} NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE; + +/*! + * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS + * + * This structure specifies resources in an execution partition + * + * profileCount[OUT] + * - Total Number of profiles filled + * + * profiles[OUT] + * - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles + */ +#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBBU) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS { + NvU32 profileCount; + NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE]; +} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS; + + + +/* + * NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE + * + * This command sets the ccu stream to enable/disable state. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE (0x20800abd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID (0xBDU) + +typedef struct NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS { + NvBool bStreamState; +} NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT + * + * Attach GPU to the external device. + * + * [in] bExtDevFound + * To enable GPIO interrupts. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT (0x20800abe) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID (0xBEU) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS { + NvBool bExtDevFound; +} NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS + * + * Optimize the Gsync timing parameters + * + * [in] timingParameters + * Timing parameters passed by client. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS (0x20800abf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID (0xBFU) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS { + NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS timingParameters; +} NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS + * + * Get displayIDs supported by the display. + * + * [out] displayIds + * Associated display ID with head. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS (0x20800ac0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID" */ + +#define NV2080_MAX_NUM_HEADS 4 + +#define NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID (0xC0U) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS { + NvU32 displayIds[NV2080_MAX_NUM_HEADS]; +} NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC + * + * Set the Stereo sync for Gsync + * + * [in] slave + * Slave GPU head status. + * [in] localSlave + * Slave GPU head status but are not coupled. + * [in] master + * Master GPU head status. + * [in] regstatus + * Register status of status1 register. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC (0x20800ac1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID (0xC1U) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS { + NvU32 slave[NV2080_MAX_NUM_HEADS]; + NvU32 localSlave[NV2080_MAX_NUM_HEADS]; + NvU32 master[NV2080_MAX_NUM_HEADS]; + NvU32 regStatus; +} NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES + * + * Get vertical active lines for given head. + * + * [in] head + * For the headIdx which we need active. + * [out] vActiveLines + * Vertical active lines. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES (0x20800ac4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID (0xC4U) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS { + NvU32 headIdx; + NvU32 vActiveLines; +} NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID + * + * Verifies if this displayId is valid. + * + * [in] displays + * Displays given by the client + * + * [out] displayId + * DisplayId for the given display + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID (0x20800ac9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID (0xC9U) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS { + NvU32 displays; + NvU32 displayId; +} NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC + * + * Disable the raster sync gpio on the other P2060 GPU + * that's connected to master over Video bridge. + * + * [in] bEnableMaster + * If it is master gpu. + * + * [out] bRasterSyncGpioSaved + * If raster sync GPIO direction is saved or not. + * + * [in/out] bRasterSyncGpioDirection + * During save it gets the direction. + * In restores it sets the direction. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC (0x20800aca) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID (0xCAU) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS { + NvBool bEnableMaster; + NvBool bRasterSyncGpioSaved; + NvU32 bRasterSyncGpioDirection; +} NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_FBSR_INIT + * + * Initialize FBSR on GSP to prepare for suspend-resume + * + * [in] fbsrType + * Fbsr object type + * [in] numRegions + * Number of regions that GSP should allocate records for + * [in] hClient + * Handle to client of SYSMEM memlist object + * [in] hSysMem + * Handle to SYSMEM memlist object + * [in] gspFbAllocsSysOffset + * Offset in SYSMEM for GSP's FB Allocations + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_FBSR_INIT (0x20800ac2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID (0xC2U) + +typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS { + NvU32 fbsrType; + NvU32 numRegions; + NvHandle hClient; + NvHandle hSysMem; + NV_DECLARE_ALIGNED(NvU64 gspFbAllocsSysOffset, 8); +} NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO + * + * Send info of FB region that will be saved/restored by GSP on suspend-resume + * + * [in] fbsrType + * Fbsr object type + * [in] hClient + * Handle to client of FBMEM memlist object + * [in] hVidMem + * Handle to FBMEM memlist object + * [in] vidOffset + * Offset in FBMEM region to save/restore + * [in] sysOffset + * Offset in SYSMEM region to save to/restore from + * [in] size + * Size of region being saved/restored + */ +#define NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO (0x20800ac3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID (0xC3U) + +typedef struct NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS { + NvU32 fbsrType; + NvHandle hClient; + NvHandle hVidMem; + NV_DECLARE_ALIGNED(NvU64 vidOffset, 8); + NV_DECLARE_ALIGNED(NvU64 sysOffset, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); +} NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB + * + * This command is used to get the amount of host reserved FB + * + * hostReservedFb [OUT] + * Amount of FB reserved for the host + * vgpuTypeId [IN] + * The Type ID for VGPU profile + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB (0x20800ac5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID (0xC5U) + +typedef struct NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS { + NV_DECLARE_ALIGNED(NvU64 hostReservedFb, 8); + NvU32 vgpuTypeId; +} NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD + * + * This command initiates brightc module state load. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD (0x20800ac6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_ACPI_DSM_READ_SIZE (0x1000) /* finn: Evaluated from "(4 * 1024)" */ + +#define NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID (0xC6U) + +typedef struct NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS { + NvU32 status; + NvU16 backLightDataSize; + NvU8 backLightData[NV2080_CTRL_ACPI_DSM_READ_SIZE]; +} NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS; + +/* + * NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL + * + * Returns number of active links allowed per IOCTRL + * + * [Out] numActiveLinksPerIoctrl + */ +#define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xC7U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS { + NvU32 numActiveLinksPerIoctrl; +} NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS; +#define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL (0x20800ac7U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */ +/* + * NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL + * + * Returns number of links per IOCTRL + * + * [Out] numLinksPerIoctrl + */ +#define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xC8U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS { + NvU32 numLinksPerIoctrl; +} NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS; +#define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL (0x20800ac8U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE + * + * Update the system control capability + * + * bIsSysCtrlSupported [IN] + If the system control is supported + * bIsPlatformLegacy [OUT] + If the platform is legacy + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE (0x20800acb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID (0xCBU) + +typedef struct NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS { + NvBool bIsSysCtrlSupported; + NvBool bIsPlatformLegacy; +} NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS; + +/*! + * Macros for PFM_REQ_HNDLR_STATE_SYNC data types. + */ +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_PMGR 0x00U +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_THERM 0x01U +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_SMBPBI 0x02U + +/*! + * Structure representing static data for a PFM_REQ_HNDLR_STATE_SYNC_SMBPBI. + */ +typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI { + /*! + * PFM sensor ID + */ + NvU32 sensorId; + + /*! + * PFM sensor limit value if required + */ + NvU32 limit; +} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI; + +/*! + * Structure of static information describing PFM_REQ_HNDLR_STATE_SYNC data types. + */ +typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA { + /*! + * @ref NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_ + */ + NvU8 type; + + /*! + * Type-specific information. + */ + union { + NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI smbpbi; + } data; +} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA; + +/*! + * Macros for PFM_REQ_HNDLR_STATE_SYNC flags for specific operation. + */ +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_PMGR_LOAD 0x00U +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_THERM_INIT 0x01U +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_CLEAR 0x02U +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_SET 0x03U + +/*! + * Structure of static information describing PFM_REQ_HNDLR_STATE_SYNC params. + */ +typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS { + /*! + * @ref NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_ + */ + NvU8 flags; + + /*! + * Type-specific information. + */ + NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA syncData; +} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC + * + * State sync with platform req handler and SMBPBI + * + * flags [IN] + * Flags that needs sync operation between physical and kernel + * + * syncData [IN] + * Sync payload data + * + */ +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC (0x20800acc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xCC" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC + * + * State sync with platform req handler and SMBPBI + * + * flags [IN] + * Flags that needs sync operation between physical and kernel + * + * syncData [IN] + * Sync payload data + * + */ +#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC (0x20800acd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xCD" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE + * + * Query Coherent FB Aperture Size. + * + */ +#define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID (0xDAU) + +typedef struct NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS { + // Get Coherent Fb Aperture Size + NV_DECLARE_ALIGNED(NvU64 coherentFbApertureSize, 8); +} NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS; + + +/*! + * Macros for NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE flag + */ +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_FORCED_OFF_STATUS 0x00U +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_STATUS 0x01U + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE + * + * Queries PM1 Forced off / PM1 Available status + * + * flag [IN] + * Fetch PM1 Forced off / PM1 Available status based on value. + * bStatus [OUT] + * PM1 Forced off / PM1 Available is true or false. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMETS + */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE (0x20800ace) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID (0xCEU) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS { + /*! + * Fetch PM1 Forced off / PM1 Available status based on value. + */ + NvU8 flag; + + /*! + * PM1 Forced off / PM1 Available status + */ + NvBool bStatus; +} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE + * + * Set PM1 state to enabled / disabled (boost clocks). + * + * bEnable [IN] + * NV_TRUE means enable PM1, NV_FALSE means disable. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE (0x20800acf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID (0xCFU) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS { + + /*! + * NV_TRUE means enable PM1, NV_FALSE means disable. + */ + NvBool bEnable; +} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT + * + * Updates EDPpeak Limit of GPU + * + * bEnable [IN] + * Enable or Reset the settings + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + * NV_ERR_NOT_READY + */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT (0x20800ad0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID (0xD0U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS { + NvBool bEnable; +} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT + * + * Updates Target Temperature of GPU + * + * targetTemp [IN] + * Target Temperature Set from SBIOS + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT (0x20800ad1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID (0xD1U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS { + NvS32 targetTemp; +} NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE + * + * Enable / disable CTGP MODE + * + * bEnable [IN] + * Enable or Reset the settings + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE (0x20800ad2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID (0xD2U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS { + NvBool bEnable; +} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2 + * + * Configuration of the turbo v2 parameters for NVPCF-Turbo arb control + * + * ctgpOffsetmW [IN] + * TGP MODE Offset in mW + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2 (0x20800ad3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID (0xD3U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS { + NvU32 ctgpOffsetmW; +} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO + * + * Query VPstatese info. Get VPS PS2.0 support / get highest VP State Idx and requested VP State Idx + * + * bVpsPs20Supported [OUT] + * Reflects Vpstates PS20 support + * vPstateIdxHighest [OUT} + * Reflects Highest VPstate Idx + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO (0x20800ad4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID (0xD4U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS { + /*! + * Reflects Vpstates PS20 support + */ + NvBool bVpsPs20Supported; + + /*! + * Get highest VPState Idx from VBIOS + */ + NvU32 vPstateIdxHighest; +} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING + * + * Get vPstate mapping for requested pStateIdx + * + * pStateIdx [IN] + * Requested PState Idx + * vPstateIdx [OUT} + * Mapped VPstate Idx + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING (0x20800ad5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID (0xD5U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS { + /*! + * Requested PState Idx + */ + NvU32 pStateIdx; + + /*! + * Mapped VPstate Idx + */ + NvU32 vPstateIdxMapping; +} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE + * + * Set requested VPstate + * + * vPstateIdx [IN] + * VPstate Idx to be set + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE (0x20800ad6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID (0xD6U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS { + + /*! + * NV_TRUE means enable PM1, NV_FALSE means disable. + */ + NvU32 vPstateIdx; +} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS; + +/* + * This command unsets Dynamic Boost limit when nvidia-powerd is terminated unexpectedly. + */ +#define NV2080_CTRL_CMD_INTERNAL_PMGR_UNSET_DYNAMIC_BOOST_LIMIT (0x20800a7b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7B" */ + +/* ctrl2080internal_h */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h new file mode 100644 index 0000000..9a121f9 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h @@ -0,0 +1,100 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080lpwr.finn +// + + + +/*! + * NV2080_CTRL_CMD_LPWR_DIFR_CTRL + * + * This command is used to control the DIFR + * feature behavior. + * + */ +#define NV2080_CTRL_CMD_LPWR_DIFR_CTRL (0x20802801) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_LPWR_INTERFACE_ID << 8) | NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS_MESSAGE_ID" */ + +/*! + * @brief Various Values for control + */ +// Disable the DIFR +#define NV2080_CTRL_LPWR_DIFR_CTRL_DISABLE (0x00000001) +// Enable the DIFR +#define NV2080_CTRL_LPWR_DIFR_CTRL_ENABLE (0x00000002) + +// Support status for DIFR +#define NV2080_CTRL_LPWR_DIFR_CTRL_SUPPORT_STATUS (0x00000003) + +/*! + * Structure containing DIFR control call Parameters + */ +#define NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS { + NvU32 ctrlParamVal; +} NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS; + +// Values for the SUPPORT Control Status +#define NV2080_CTRL_LPWR_DIFR_SUPPORTED (0x00000001) +#define NV2080_CTRL_LPWR_DIFR_NOT_SUPPORTED (0x00000002) + +/*! + * NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE + * + * This control call is used to send the prefetch response + * + */ +#define NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE (0x20802802) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_LPWR_INTERFACE_ID << 8) | NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS_MESSAGE_ID" */ + +/*! + * @brief Various Values of Reponses for Prefetch Status + */ + +// Prefetch is successfull. +#define NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS (0x00000001) +// OS Filps are enabled, so prefetch can not be done. +#define NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_OS_FLIPS_ENABLED (0x00000002) +// Current Display surface can not fit in L2 +#define NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_INSUFFICIENT_L2_SIZE (0x00000003) +// Fatal and un recoverable Error +#define NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_CE_HW_ERROR (0x00000004) + +/*! + * Structure containing DIFR prefetch response control call Parameters + */ +#define NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS { + NvU32 responseVal; +} NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS; + + +// _ctrl2080lpwr_h_ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h new file mode 100644 index 0000000..2bb1c30 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h @@ -0,0 +1,325 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080mc.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "nvcfg_sdk.h" + +/* NV20_SUBDEVICE_XX mc control commands and parameters */ + +/** + * NV2080_CTRL_CMD_MC_GET_ARCH_INFO + * + * This command returns chip architecture information from the + * master control engine in the specified GPU. + * + * architecture + * This parameter specifies the architecture level for the GPU. + * implementation + * This parameter specifies the implementation of the architecture + * for the GPU. + * revision + * This parameter specifies the revision of the mask used to produce + * the GPU. + * subRevision + * This parameter specific the sub revision of the GPU. Value is one of + * NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_* + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_MC_GET_ARCH_INFO (0x20801701) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS { + NvU32 architecture; + NvU32 implementation; + NvU32 revision; + NvU8 subRevision; +} NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS; + +/* valid architecture values */ + + +#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_T23X (0xE0000023) + + +#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100 (0x00000160) +#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100 (0x00000170) + + + +/* valid ARCHITECTURE_T23X implementation values */ + + +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234 (0x00000004) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234D (0x00000005) + + +/* valid ARCHITECTURE_TU10x implementation values */ +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU100 (0x00000000) + + +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU102 (0x00000002) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU104 (0x00000004) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU106 (0x00000006) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU116 (0x00000008) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU117 (0x00000007) + + +/* valid ARCHITECTURE_GA10x implementation values */ +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA100 (0x00000000) + + +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA102 (0x00000002) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA103 (0x00000003) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA104 (0x00000004) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA106 (0x00000006) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA107 (0x00000007) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA10B (0x0000000B) + + + +/* Valid Chip sub revisions */ +#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_NO_SUBREVISION (0x00000000) +#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_P (0x00000001) +#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_Q (0x00000002) +#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_R (0x00000003) + +/* + * NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS + * + * This command instructs the RM to service interrupts for the specified + * engine(s). + * + * engines + * This parameter specifies which engines should have their interrupts + * serviced. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS (0x20801702) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MC_ENGINE_ID_GRAPHICS 0x00000001 +#define NV2080_CTRL_MC_ENGINE_ID_ALL 0xFFFFFFFF + +#define NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS { + NvU32 engines; +} NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS; + + +/* + * NV2080_CTRL_CMD_MC_GET_MANUFACTURER + * + * This command returns the GPU manufacturer information for the associated + * subdevice. + * + * manufacturer + * This parameter returns the manufacturer value for the GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_MC_GET_MANUFACTURER (0x20801703) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS { + NvU32 manufacturer; +} NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS; + + + +/* + * NV2080_CTRL_CMD_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS + * + * This command is used to allow clients to query whether hostclk slowdown is + * disabled. + * + * bDisabled + * This parameter will hold the status of hostclk slowdown + * + * Possible status values returned are: + * NV_OK + * + */ +#define NV2080_CTRL_CMD_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS (0x20801708) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS { + NvBool bDisabled; +} NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_MC_SET_HOSTCLK_SLOWDOWN_STATUS + * + * This command is used to allow clients to disable/enable hostclk slowdown. + * + * bDisable + * When this parameter is set to TRUE, RM should disable hostclk slowdown. + * If it is set to FALSE, RM will attempt to enable hostclk slowdown, but + * in this case, slowdown is NOT guaranteed to be enabled since there may + * be other reason (like regkey) preventing slowdown. + * + * Possible status values returned are: + * NV_OK + * + */ +#define NV2080_CTRL_CMD_MC_SET_HOSTCLK_SLOWDOWN_STATUS (0x20801709) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS { + NvBool bDisable; +} NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS; + + + +/* + * NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP + * + * This call will setup RM to either service or ignore the + * repayable fault interrupt. + * This is a privileged call that can only be called by the UVM driver + * when it will take ownership of the repalayable fault interrupt. + * + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + * NVOS_STATUS_ERROR_INVALID_ARGUMENT + * NVOS_STATUS_ERROR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP (0x2080170c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS { + NvBool bOwnedByRm; +} NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS; + +/* + * NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS + * + * This command gets the notification interrupt vectors device for all VGPU engines from Host RM. + * + * Parameters: + * + * entries [out] + * A buffer to store up to MAX_ENGINES entries of type + * NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY. + * + * numEntries [out] + * Number of populated entries in the provided buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS (0x2080170d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES 256 + +typedef struct NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY { + NvU32 nv2080EngineType; + NvU32 notificationIntrVector; +} NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY; + +#define NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS { + NvU32 numEntries; + NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY entries[NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES]; +} NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS; + +/* + * NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE + * + * This command gets the static interrupts needed by VGPU from Host RM. + * + * Parameters: + * + * entries [out] + * A buffer to store up to MAX_ENGINES entries of type + * NV2080_CTRL_MC_STATIC_INTR_ENTRY. + * + * numEntries [out] + * Number of populated entries in the provided buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE (0x2080170e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX 32 + +// Interface defines for static MC_ENGINE_IDX defines +#define NV2080_INTR_TYPE_NULL (0x00000000) +#define NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT (0x00000001) +#define NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT_ERROR (0x00000002) +#define NV2080_INTR_TYPE_INFO_FAULT (0x00000003) +#define NV2080_INTR_TYPE_REPLAYABLE_FAULT (0x00000004) +#define NV2080_INTR_TYPE_REPLAYABLE_FAULT_ERROR (0x00000005) +#define NV2080_INTR_TYPE_ACCESS_CNTR (0x00000006) +#define NV2080_INTR_TYPE_TMR (0x00000007) +#define NV2080_INTR_TYPE_CPU_DOORBELL (0x00000008) +#define NV2080_INTR_TYPE_GR0_FECS_LOG (0x00000009) +#define NV2080_INTR_TYPE_GR1_FECS_LOG (0x0000000A) +#define NV2080_INTR_TYPE_GR2_FECS_LOG (0x0000000B) +#define NV2080_INTR_TYPE_GR3_FECS_LOG (0x0000000C) +#define NV2080_INTR_TYPE_GR4_FECS_LOG (0x0000000D) +#define NV2080_INTR_TYPE_GR5_FECS_LOG (0x0000000E) +#define NV2080_INTR_TYPE_GR6_FECS_LOG (0x0000000F) +#define NV2080_INTR_TYPE_GR7_FECS_LOG (0x00000010) + +typedef struct NV2080_CTRL_MC_STATIC_INTR_ENTRY { + NvU32 nv2080IntrType; + NvU32 pmcIntrMask; + NvU32 intrVectorStall; + NvU32 intrVectorNonStall; +} NV2080_CTRL_MC_STATIC_INTR_ENTRY; + +#define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS { + NvU32 numEntries; + NV2080_CTRL_MC_STATIC_INTR_ENTRY entries[NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX]; +} NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS; + +/* _ctrl2080mc_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h new file mode 100644 index 0000000..f1e490b --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h @@ -0,0 +1,338 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080nvd.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +#include "ctrl/ctrlxxxx.h" +/* + * NV2080_CTRL_CMD_NVD_GET_DUMP_SIZE + * + * This command gets the expected dump size of a particular GPU dump component. + * Note that events that occur between this command and a later + * NV2080_CTRL_CMD_NVD_GET_DUMP command could alter the size of + * the buffer required. + * + * component + * One of NVDUMP_COMPONENT < 0x400 defined in nvdump.h to estimate + * the size of. + * size + * This parameter returns the expected size. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT if component is invalid. + * + */ + +#define NV2080_CTRL_CMD_NVD_GET_DUMP_SIZE (0x20802401) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS { + NvU32 component; + NvU32 size; +} NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS; + +/* + * NV2080_CTRL_CMD_NVD_GET_DUMP + * + * This command gets a dump of a particular GPU dump component. If triggers + * is non-zero, the command waits for the trigger to occur + * before it returns. + * + * pBuffer + * This parameter points to the buffer for the data. + * component + * One of NVDUMP_COMPONENT < 0x400 defined in nvdump.h to select + * for dumping. + * size + * On entry, this parameter specifies the maximum length for + * the returned data. On exit, it specifies the number of bytes + * returned. + * + * Possible status values returned are: + * NV_OK + * NVOS_ERROR_INVALID_ARGUMENT if component is invalid. + * NVOS_ERROR_INVALID_ADDRESS if pBuffer is invalid + * NVOS_ERROR_INVALID_???? if the buffer was too small + * + * + */ +#define NV2080_CTRL_CMD_NVD_GET_DUMP (0x20802402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_NVD_GET_DUMP_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pBuffer, 8); + NvU32 component; + NvU32 size; +} NV2080_CTRL_NVD_GET_DUMP_PARAMS; + +/* + * NV2080_CTRL_CMD_NVD_GET_NOCAT_JOURNAL + * + * This command returns the contents of the Journal used by NOCAT, and + * optionally clears the data + * + * clear: + * [IN] indicates if should the data be cleared after reporting + * + * JournalRecords : + * [OUT] an array of Journal records reported. + * + * outstandingAssertCount: + * [OUT] number of asserts that remain to be reported on. + * + * reportedAssertCount: + * [OUT] the number of asserts contained in the report + * + * asserts: + * [OUT] an array of up to NV2080_NOCAT_JOURNAL_MAX_ASSERT_RECORDS assert reports + */ + + +#define NV2080_CTRL_CMD_NVD_GET_NOCAT_JOURNAL (0x20802409) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID" */ + +#define NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER 1024 +#define NV2080_NOCAT_JOURNAL_MAX_STR_LEN 65 +#define NV2080_NOCAT_JOURNAL_MAX_JOURNAL_RECORDS 10 +#define NV2080_NOCAT_JOURNAL_MAX_ASSERT_RECORDS 32 + +// structure to hold clock details. +typedef struct NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS { + NvS32 userMinOffset; + NvS32 userMaxOffset; + NvU32 factoryMinOffset; + NvU32 factoryMaxOffset; + NvU32 lastActiveClock; + NvU32 lastActiveVolt; + NvU32 lastActivePoint; + NvU32 kappa; +} NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS; + + +// structure to hold clock configuration & state. +typedef struct NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG { + NvU32 pstateVer; + NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS gpcOverclock; + NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS mclkOverclock; + NvBool bUserOverclocked; + NvBool bFactoryOverclocked; +} NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG; + +// structure to hold the GPU context at the time of the report. +typedef struct NV2080_NOCAT_JOURNAL_GPU_STATE { + NvBool bValid; + NvU32 strap; + NvU16 deviceId; + NvU16 vendorId; + NvU16 subsystemVendor; + NvU16 subsystemId; + NvU16 revision; + NvU16 type; + NvU32 vbiosVersion; + NvBool bOptimus; + NvBool bMsHybrid; + NvBool bFullPower; + NvU32 vbiosOemVersion; + NvU16 memoryType; + NvU8 tag[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; + NvU8 vbiosProject[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; + NvBool bInFullchipReset; + NvBool bInSecBusReset; + NvBool bInGc6Reset; + NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG overclockCfg; +} NV2080_NOCAT_JOURNAL_GPU_STATE; + +#define NV2080_NOCAT_JOURNAL_REC_TYPE_UNKNOWN 0 +#define NV2080_NOCAT_JOURNAL_REC_TYPE_BUGCHECK 1 +#define NV2080_NOCAT_JOURNAL_REC_TYPE_ENGINE 2 +#define NV2080_NOCAT_JOURNAL_REC_TYPE_TDR 3 +#define NV2080_NOCAT_JOURNAL_REC_TYPE_RC 4 +#define NV2080_NOCAT_JOURNAL_REC_TYPE_ASSERT 5 +#define NV2080_NOCAT_JOURNAL_REC_TYPE_ANY 6 + +// this should be relative to the highest type value +#define NV2080_NOCAT_JOURNAL_REC_TYPE_COUNT (0x7) /* finn: Evaluated from "NV2080_NOCAT_JOURNAL_REC_TYPE_ANY + 1" */ +typedef struct NV2080_NOCAT_JOURNAL_ENTRY { + NvU8 recType; + NvU32 bugcheck; + NvU32 tdrBucketId; + NvU8 source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; + NvU32 subsystem; + NV_DECLARE_ALIGNED(NvU64 errorCode, 8); + NvU32 diagBufferLen; + NvU8 diagBuffer[NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER]; + NvU8 faultingEngine[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; + NvU32 mmuFaultType; + NvU32 mmuErrorSrc; + NvU8 tdrReason[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; +} NV2080_NOCAT_JOURNAL_ENTRY; + +typedef struct NV2080_NOCAT_JOURNAL_RECORD { + NvU32 GPUTag; + NV_DECLARE_ALIGNED(NvU64 loadAddress, 8); + NV_DECLARE_ALIGNED(NvU64 timeStamp, 8); + NV_DECLARE_ALIGNED(NvU64 stateMask, 8); + NV2080_NOCAT_JOURNAL_GPU_STATE nocatGpuState; + NV_DECLARE_ALIGNED(NV2080_NOCAT_JOURNAL_ENTRY nocatJournalEntry, 8); +} NV2080_NOCAT_JOURNAL_RECORD; + +// NOCAT activity counter indexes +// collection activity +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_IDX 0 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX 1 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECTED_IDX 2 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX 3 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX 4 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_DROPPED_IDX 5 + +// reporting activity +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX 6 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX 7 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX 8 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MISSED_IDX 9 + +// update activity +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX 10 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX 11 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX 12 + +// general errors +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX 13 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX 14 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX 15 + +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX 16 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES2_IDX 17 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CACHE_UPDATE_IDX 18 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_INSERT_RECORDS_IDX 19 + +// this should be relative to the highest counter index +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT (0x14) /* finn: Evaluated from "NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_INSERT_RECORDS_IDX + 1" */ + +#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY 0:0 +#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_YES 1 +#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_NO 0 + +#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS 1:1 +#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_YES 1 +#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_NO 0 + + +#define NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS { + NvU32 flags; + NvU32 nocatRecordCount; + NvU32 nocatOutstandingRecordCount; + NV_DECLARE_ALIGNED(NV2080_NOCAT_JOURNAL_RECORD journalRecords[NV2080_NOCAT_JOURNAL_MAX_JOURNAL_RECORDS], 8); + NvU32 activityCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT]; + NvU8 reserved[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; +} NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS; + + /* + * NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA + * + * This command reports the TDR data collected by KMD to be added to the + * nocat record + * + * dataType: + * [IN] specifies the type of data provided. + * targetRecordType + * [IN] specifies record type the data is intended for. + * nocatJournalData + * [IN] specifies the data to be added. + */ + +#define NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA (0x2080240b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID" */ + +// data types & structures +#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_EMPTY 0 +#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_TDR_REASON 1 +#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_INSERT_RECORD 2 +#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG 3 + +#define NV2080_CTRL_NOCAT_TDR_TYPE_NONE 0 +#define NV2080_CTRL_NOCAT_TDR_TYPE_LEGACY 1 +#define NV2080_CTRL_NOCAT_TDR_TYPE_FULLCHIP 2 +#define NV2080_CTRL_NOCAT_TDR_TYPE_BUSRESET 3 +#define NV2080_CTRL_NOCAT_TDR_TYPE_GC6_RESET 4 +#define NV2080_CTRL_NOCAT_TDR_TYPE_SURPRISE_REMOVAL 5 +#define NV2080_CTRL_NOCAT_TDR_TYPE_UCODE_RESET 6 +#define NV2080_CTRL_NOCAT_TDR_TYPE_TEST 7 + +typedef struct NV2080CtrlNocatJournalDataTdrReason { + NvU32 flags; + NvU8 source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; + NvU32 subsystem; + NV_DECLARE_ALIGNED(NvU64 errorCode, 8); + NvU32 reasonCode; +} NV2080CtrlNocatJournalDataTdrReason; + +#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR 0:0 +#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_YES 1 +#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_NO 0 +#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER 1:1 +#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_YES 1 +#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_NO 0 +typedef struct NV2080CtrlNocatJournalInsertRecord { + NvU32 flags; + NvU8 recType; + NvU32 bugcheck; + NvU8 source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; + NvU32 subsystem; + NV_DECLARE_ALIGNED(NvU64 errorCode, 8); + NvU8 faultingEngine[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; + NvU32 tdrReason; +} NV2080CtrlNocatJournalInsertRecord; + +#define NV2080_CTRL_NOCAT_TAG_CLEAR 0:0 +#define NV2080_CTRL_NOCAT_TAG_CLEAR_YES 1 +#define NV2080_CTRL_NOCAT_TAG_CLEAR_NO 0 +typedef struct NV2080CtrlNocatJournalSetTag { + NvU32 flags; + NvU8 tag[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; +} NV2080CtrlNocatJournalSetTag; + +#define NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS { + NvU32 dataType; + NvU32 targetRecordType; + union { + NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalDataTdrReason tdrReason, 8); + NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalInsertRecord insertData, 8); + NV2080CtrlNocatJournalSetTag tagData; + } nocatJournalData; +} NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS; +/* _ctr2080nvd_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h new file mode 100644 index 0000000..090f813 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h @@ -0,0 +1,2950 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080nvlink.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX bus control commands and parameters */ + +/* + * NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS + * + * This command returns the NVLink capabilities supported by the subdevice. + * + * capsTbl + * This is bit field for getting different global caps. The individual bitfields are specified by NV2080_CTRL_NVLINK_CAPS_* + * lowestNvlinkVersion + * This field specifies the lowest supported NVLink version for this subdevice. + * highestNvlinkVersion + * This field specifies the highest supported NVLink version for this subdevice. + * lowestNciVersion + * This field specifies the lowest supported NCI version for this subdevice. + * highestNciVersion + * This field specifies the highest supported NCI version for this subdevice. + * discoveredLinkMask + * This field provides a bitfield mask of NVLink links discovered on this subdevice. + * enabledLinkMask + * This field provides a bitfield mask of NVLink links enabled on this subdevice. + * + */ +#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS { + NvU32 capsTbl; + + NvU8 lowestNvlinkVersion; + NvU8 highestNvlinkVersion; + NvU8 lowestNciVersion; + NvU8 highestNciVersion; + + NvU32 discoveredLinkMask; + NvU32 enabledLinkMask; +} NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS; + +/* extract cap bit setting from tbl */ +#define NV2080_CTRL_NVLINK_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* + * NV2080_CTRL_NVLINK_CAPS + * + * SUPPORTED + * Set if NVLink is present and supported on this subdevice, NV_FALSE otherwise. This field is used for *global* caps only and NOT for per-link caps + * P2P_SUPPORTED + * Set if P2P over NVLink is supported on this subdevice, NV_FALSE otherwise. + * SYSMEM_ACCESS + * Set if sysmem can be accessed over NVLink on this subdevice, NV_FALSE otherwise. + * PEER_ATOMICS + * Set if P2P atomics are supported over NVLink on this subdevice, NV_FALSE otherwise. + * SYSMEM_ATOMICS + * Set if sysmem atomic transcations are supported over NVLink on this subdevice, NV_FALSE otherwise. + * PEX_TUNNELING + * Set if PEX tunneling over NVLink is supported on this subdevice, NV_FALSE otherwise. + * SLI_BRIDGE + * GLOBAL: Set if SLI over NVLink is supported on this subdevice, NV_FALSE otherwise. + * LINK: Set if SLI over NVLink is supported on a link, NV_FALSE otherwise. + * SLI_BRIDGE_SENSABLE + * GLOBAL: Set if the subdevice is capable of sensing SLI bridges, NV_FALSE otherwise. + * LINK: Set if the link is capable of sensing an SLI bridge, NV_FALSE otherwise. + * POWER_STATE_L0 + * Set if L0 is a supported power state on this subdevice/link, NV_FALSE otherwise. + * POWER_STATE_L1 + * Set if L1 is a supported power state on this subdevice/link, NV_FALSE otherwise. + * POWER_STATE_L2 + * Set if L2 is a supported power state on this subdevice/link, NV_FALSE otherwise. + * POWER_STATE_L3 + * Set if L3 is a supported power state on this subdevice/link, NV_FALSE otherwise. + * VALID + * Set if this link is supported on this subdevice, NV_FALSE otherwise. This field is used for *per-link* caps only and NOT for global caps. + * + */ + +/* caps format is byte_index:bit_mask */ +#define NV2080_CTRL_NVLINK_CAPS_SUPPORTED 0:0x01 +#define NV2080_CTRL_NVLINK_CAPS_P2P_SUPPORTED 0:0x02 +#define NV2080_CTRL_NVLINK_CAPS_SYSMEM_ACCESS 0:0x04 +#define NV2080_CTRL_NVLINK_CAPS_P2P_ATOMICS 0:0x08 +#define NV2080_CTRL_NVLINK_CAPS_SYSMEM_ATOMICS 0:0x10 +#define NV2080_CTRL_NVLINK_CAPS_PEX_TUNNELING 0:0x20 +#define NV2080_CTRL_NVLINK_CAPS_SLI_BRIDGE 0:0x40 +#define NV2080_CTRL_NVLINK_CAPS_SLI_BRIDGE_SENSABLE 0:0x80 +#define NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L0 1:0x01 +#define NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L1 1:0x02 +#define NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L2 1:0x04 +#define NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L3 1:0x08 +#define NV2080_CTRL_NVLINK_CAPS_VALID 1:0x10 + +/* + * Size in bytes of nvlink caps table. This value should be one greater + * than the largest byte_index value above. + */ +#define NV2080_CTRL_NVLINK_CAPS_TBL_SIZE 2U + +#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_INVALID (0x00000000U) +#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0 (0x00000001U) +#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0 (0x00000002U) +#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2 (0x00000004U) +#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0 (0x00000005U) +#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1 (0x00000006U) +#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0 (0x00000007U) + +#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID (0x00000000U) +#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0 (0x00000001U) +#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_0 (0x00000002U) +#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_2 (0x00000004U) +#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_0 (0x00000005U) +#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1 (0x00000006U) +#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0 (0x00000007U) + + +/* + * NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS (0x20803001U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_NVLINK_DEVICE_INFO + * + * This structure stores information about the device to which this link is associated + * + * deviceIdFlags + * Bitmask that specifies which IDs are valid for the device + * Refer NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_* for possible values + * If NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI is set, PCI information is valid + * If NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID is set, UUID is valid + * domain, bus, device, function, pciDeviceId + * PCI information for the device + * deviceType + * Type of the device + * See NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_* for possible values + * deviceUUID + * This field specifies the device UUID of the device. Useful for identifying the device (or version) + */ +typedef struct NV2080_CTRL_NVLINK_DEVICE_INFO { + // ID Flags + NvU32 deviceIdFlags; + + // PCI Information + NvU32 domain; + NvU16 bus; + NvU16 device; + NvU16 function; + NvU32 pciDeviceId; + + // Device Type + NV_DECLARE_ALIGNED(NvU64 deviceType, 8); + + // Device UUID + NvU8 deviceUUID[16]; +} NV2080_CTRL_NVLINK_DEVICE_INFO; + +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS 31:0 +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_NONE (0x00000000U) +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI (0x00000001U) +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID (0x00000002U) + +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_EBRIDGE (0x00000000U) +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU (0x00000001U) +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU (0x00000002U) +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH (0x00000003U) +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA (0x00000004U) +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE (0x000000FFU) + +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_UUID_INVALID (0xFFFFFFFFU) + +/* + * NV2080_CTRL_NVLINK_NVLINK_LINK_STATUS_INFO + * + * This structure stores the per-link status of different NVLink parameters. + * + * capsTbl + * This is bit field for getting different global caps. The individual bitfields + * are specified by NV2080_CTRL_NVLINK_CAPS_* + * phyType + * This field specifies the type of PHY (NVHS or GRS) being used for this link. + * subLinkWidth + * This field specifies the no. of lanes per sublink. + * linkState + * This field specifies the current state of the link. + * See NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_LINK_STATE_* for possible values. + * rxSublinkStatus + * This field specifies the current state of RX sublink. + * See NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_SUBLINK_RX_STATE_* for possible values. + * txSublinkStatus + * This field specifies the current state of TX sublink. + * See NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_SUBLINK_TX_STATE_* for possible values. + * bLaneReversal + * This field indicates that lane reversal is in effect on this link. + * nvlinkVersion + * This field specifies the NVLink version supported by the link. + * nciVersion + * This field specifies the NCI version supported by the link. + * phyVersion + * This field specifies the version of PHY being used by the link. + * nvlinkLineRateMbps + * Bit rate at which bits toggle on wires in megabits per second. + * NOTE: This value is the full speed line rate, not the instantaneous line rate of the link. + * nvlinkLinkClockMhz + * Clock corresponding to link logic in mega hertz + * nvlinkRefClkType + * This field specifies whether the link clock is taken from NVHS reflck + * or PEX refclk for the current GPU. + * nvlinkLinkDataRateKiBps + * Effective rate available for transactions after subtracting overhead, + * as seen at Data Layer in kibibytes (1024 bytes) per second. + * Only valid in GA100+, reported as 0 otherwise + * NOTE: Because minion calculates these values, it will only be valid if + * links are in ACTIVE state + * nvlinkRefClkSpeedMhz + * The input reference frequency to the PLL + * connected + * This field specifies if any device is connected on the other end of the link + * loopProperty + * This field specifies if the link is a loopback/loopout link. See NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_* for possible values. + * remoteDeviceLinkNumber + * This field specifies the link number on the remote end of the link + * remoteDeviceInfo + * This field stores the device information for the remote end of the link + * + */ +typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO { + // Top level capablilites + NvU32 capsTbl; + + NvU8 phyType; + NvU8 subLinkWidth; + + // Link and sublink states + NvU32 linkState; + NvU8 rxSublinkStatus; + NvU8 txSublinkStatus; + + // Indicates that lane reversal is in effect on this link. + NvBool bLaneReversal; + + NvU8 nvlinkVersion; + NvU8 nciVersion; + NvU8 phyVersion; + + // Legacy clock information (to be deprecated) + NvU32 nvlinkLinkClockKHz; + NvU32 nvlinkCommonClockSpeedKHz; + NvU32 nvlinkRefClkSpeedKHz; + + NvU32 nvlinkCommonClockSpeedMhz; + + // Clock Speed and Data Rate Reporting + NvU32 nvlinkLineRateMbps; + NvU32 nvlinkLinkClockMhz; + NvU8 nvlinkRefClkType; + NvU32 nvlinkLinkDataRateKiBps; + NvU32 nvlinkRefClkSpeedMhz; + + // Connection information + NvBool connected; + NvU8 loopProperty; + NvU8 remoteDeviceLinkNumber; + NvU8 localDeviceLinkNumber; + + // + // Added as part of NvLink 3.0 + // Note: SID has link info appended to it when provided by minion + // + NV_DECLARE_ALIGNED(NvU64 remoteLinkSid, 8); + NV_DECLARE_ALIGNED(NvU64 localLinkSid, 8); + + // Ampere+ only + NvU32 laneRxdetStatusMask; + + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_DEVICE_INFO remoteDeviceInfo, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_DEVICE_INFO localDeviceInfo, 8); +} NV2080_CTRL_NVLINK_LINK_STATUS_INFO; + +// NVLink link states +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INIT (0x00000000U) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_HWCFG (0x00000001U) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SWCFG (0x00000002U) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_ACTIVE (0x00000003U) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_FAULT (0x00000004U) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SLEEP (0x00000005U) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY (0x00000006U) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_AC (0x00000008U) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_RX (0x0000000aU) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INVALID (0xFFFFFFFFU) + +// NVLink Rx sublink states +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_HIGH_SPEED_1 (0x00000000U) +// TODO: @achaudhry remove SINGLE_LANE define once references switch to LOW_POWER +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SINGLE_LANE (0x00000004) // Deprecated +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_LOW_POWER (0x00000004) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TRAINING (0x00000005U) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SAFE_MODE (0x00000006U) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_OFF (0x00000007U) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TEST (0x00000008U) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_FAULT (0x0000000eU) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_INVALID (0x000000FFU) + +// NVLink Tx sublink states +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_HIGH_SPEED_1 (0x00000000U) +// TODO: @achaudhry remove SINGLE_LANE define once references switch to LOW_POWER +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SINGLE_LANE (0x00000004) // Deprecated +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_LOW_POWER (0x00000004) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TRAINING (0x00000005U) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SAFE_MODE (0x00000006U) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_OFF (0x00000007U) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TEST (0x00000008U) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_FAULT (0x0000000eU) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_INVALID (0x000000FFU) + +#define NV2080_CTRL_NVLINK_STATUS_PHY_NVHS (0x00000001U) +#define NV2080_CTRL_NVLINK_STATUS_PHY_GRS (0x00000002U) +#define NV2080_CTRL_NVLINK_STATUS_PHY_INVALID (0x000000FFU) + +// Version information +#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_1_0 (0x00000001U) +#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_0 (0x00000002U) +#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_2 (0x00000004U) +#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_0 (0x00000005U) +#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_1 (0x00000006U) +#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_4_0 (0x00000007U) +#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID (0x000000FFU) + +#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_1_0 (0x00000001U) +#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_0 (0x00000002U) +#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_2 (0x00000004U) +#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_0 (0x00000005U) +#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_1 (0x00000006U) +#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_4_0 (0x00000007U) +#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_INVALID (0x000000FFU) + +#define NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_1_0 (0x00000001U) +#define NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_INVALID (0x000000FFU) + +#define NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_1_0 (0x00000001U) +#define NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_INVALID (0x000000FFU) + +// Connection properties +#define NV2080_CTRL_NVLINK_STATUS_CONNECTED_TRUE (0x00000001U) +#define NV2080_CTRL_NVLINK_STATUS_CONNECTED_FALSE (0x00000000U) + +#define NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPBACK (0x00000001U) +#define NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPOUT (0x00000002U) +#define NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_NONE (0x00000000U) + +#define NV2080_CTRL_NVLINK_STATUS_REMOTE_LINK_NUMBER_INVALID (0x000000FFU) + +#define NV2080_CTRL_NVLINK_MAX_LINKS 32 + +// NVLink REFCLK types +#define NV2080_CTRL_NVLINK_REFCLK_TYPE_INVALID (0x00U) +#define NV2080_CTRL_NVLINK_REFCLK_TYPE_NVHS (0x01U) +#define NV2080_CTRL_NVLINK_REFCLK_TYPE_PEX (0x02U) + +#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS { + NvU32 enabledLinkMask; + NvBool bSublinkStateInst; // whether instantaneous sublink state is needed + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_STATUS_INFO linkInfo[NV2080_CTRL_NVLINK_MAX_LINKS], 8); +} NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS + * + * enabledLinkMask + * This field specifies the mask of available links on this subdevice. + * linkInfo + * This structure stores the per-link status of different NVLink parameters. The link is identified using an index. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS (0x20803002U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_NVLINK_ERR_INFO + * Error information per link + * + * TLErrlog + * Returns the error mask for NVLINK TL errors + * Used in Pascal + * + * TLIntrEn + * Returns the intr enable mask for NVLINK TL errors + * Used in Pascal + * + * TLCTxErrStatus0 + * Returns the TLC Tx Error Mask 0 + * Used in Volta and later + * + * TLCTxErrStatus1 + * Returns the TLC Tx Error Mask 1 + * Used in Ampere and later + * + * TLCTxSysErrStatus0 + * Returns the TLC Tx Sys Error Mask 0 + * Used in Ampere and later. + * + * TLCRxErrStatus0 + * Returns the TLC Rx Error Mask 0 + * Used in Volta and later + * + * TLCRxErrStatus1 + * Returns the TLC Rx Error Mask 1 + * Used in Volta and later + * + * TLCRxSysErrStatus0 + * Returns the TLC Rx Sys Error Mask 0 + * Used in Ampere and later. + * + * TLCTxErrLogEn0 + * Returns the TLC Tx Error Log En 0 + * Used in Volta and later + * + * TLCTxErrLogEn1 + * Returns the TLC Tx Error Log En 1 + * Used in Ampere and later + * + * TLCTxSysErrLogEn0 + * Returns the TLC Tx Sys Error Log En 0 + * Used in Ampere and later + * + * TLCRxErrLogEn0 + * Returns the TLC Rx Error Log En 0 + * Used in Volta and later + * + * TLCRxErrLogEn1 + * Returns the TLC Rx Error Log En 1 + * Used in Volta and later + * + * TLCRxSysErrLogEn0 + * Returns the TLC Rx Sys Error Log En 0 + * Used in Ampere and later + * + * MIFTxErrStatus0 + * Returns the MIF Rx Error Mask 0 + * Used in Volta and Turing + * + * MIFRxErrStatus0 + * Returns the MIF Tx Error Mask 0 + * Used in Volta and Turing + * + * NVLIPTLnkErrStatus0 + * Returns the NVLIPT_LNK Error Mask 0 + * Used in Ampere and later + * + * NVLIPTLnkErrLogEn0 + * Returns the NVLIPT_LNK Log En Mask 0 + * Used in Ampere and later + * + * NVLIPTLnkCtrlLinkStateRequest + * Returns the NVLIPT_LNK Control Link State Request value + * Used in Ampere and later + * + * DLSpeedStatusTx + * Returns the NVLINK DL speed status for sublink Tx + * + * DLSpeedStatusRx + * Returns the NVLINK DL speed status for sublink Rx + * + * NVLDLRxSlsmErrCntl + * Returns the NVLDL_RXSLSM_ERR_CNTL value + * Used in Hopper and later + * + * NVLDLTopLinkState + * Returns the NVLDL_TOP_LINK_STATE value + * Used in Hopper and later + * + * NVLDLTopIntr + * Returns the NVLDL_TOP_INTR value + * Used in Hopper and later + * + * DLStatMN00 + * Returns the DLSTAT MN00 Code and subcode + * Used in Hopper and later + * + * DLStatUC01 + * Returns the DLSTAT UC01 value + * Used in Hopper and later + * + * MinionNvlinkLinkIntr + * Returns the MINION_NVLINK_LINK_INTR code and subcode + * Used in Hopper and later + * + * bExcessErrorDL + * Returns true for excessive error rate interrupt from DL + */ +typedef struct NV2080_CTRL_NVLINK_ERR_INFO { + NvU32 TLErrlog; + NvU32 TLIntrEn; + NvU32 TLCTxErrStatus0; + NvU32 TLCTxErrStatus1; + NvU32 TLCTxSysErrStatus0; + NvU32 TLCRxErrStatus0; + NvU32 TLCRxErrStatus1; + NvU32 TLCRxSysErrStatus0; + NvU32 TLCTxErrLogEn0; + NvU32 TLCTxErrLogEn1; + NvU32 TLCTxSysErrLogEn0; + NvU32 TLCRxErrLogEn0; + NvU32 TLCRxErrLogEn1; + NvU32 TLCRxSysErrLogEn0; + NvU32 MIFTxErrStatus0; + NvU32 MIFRxErrStatus0; + NvU32 NVLIPTLnkErrStatus0; + NvU32 NVLIPTLnkErrLogEn0; + NvU32 NVLIPTLnkCtrlLinkStateRequest; + NvU32 DLSpeedStatusTx; + NvU32 DLSpeedStatusRx; + NvU32 NVLDLRxSlsmErrCntl; + NvU32 NVLDLTopLinkState; + NvU32 NVLDLTopIntr; + NvU32 DLStatMN00; + NvU32 DLStatUC01; + NvU32 MinionNvlinkLinkIntr; + NvBool bExcessErrorDL; +} NV2080_CTRL_NVLINK_ERR_INFO; + +/* + * NV2080_CTRL_NVLINK_COMMON_ERR_INFO + * Error information per IOCTRL + * + * NVLIPTErrStatus0 + * Returns the NVLIPT_COMMON Error Mask 0 + * Used in Ampere and later + * + * NVLIPTErrLogEn0 + * Returns the NVLIPT_COMMON Log En Mask 0 + * Used in Ampere and later + */ +typedef struct NV2080_CTRL_NVLINK_COMMON_ERR_INFO { + NvU32 NVLIPTErrStatus0; + NvU32 NVLIPTErrLogEn0; +} NV2080_CTRL_NVLINK_COMMON_ERR_INFO; + +/* Extract the error status bit for a given TL error index i */ +#define NV2080_CTRL_NVLINK_GET_TL_ERRLOG_BIT(intr, i) (((1U << i) & (intr)) >> i) + +/* Extract the intr enable bit for a given TL error index i */ +#define NV2080_CTRL_NVLINK_GET_TL_INTEN_BIT(intr, i) NV2080_CTRL_NVLINK_GET_TL_ERRLOG_BIT(intr, i) + +/* Error status values for a given NVLINK TL error */ +#define NV2080_CTRL_NVLINK_TL_ERRLOG_TRUE (0x00000001U) +#define NV2080_CTRL_NVLINK_TL_ERRLOG_FALSE (0x00000000U) + +/* Intr enable/disable for a given NVLINK TL error */ +#define NV2080_CTRL_NVLINK_TL_INTEN_TRUE (0x00000001U) +#define NV2080_CTRL_NVLINK_TL_INTEN_FALSE (0x00000000U) + +/* NVLINK TL interrupt enable fields for errors */ +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLDATAPARITYEN 0U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLCTRLPARITYEN 1U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPROTOCOLEN 2U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXOVERFLOWEN 3U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMDATAPARITYEN 4U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMHDRPARITYEN 5U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRESPEN 6U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPOISONEN 7U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMDATAPARITYEN 8U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMHDRPARITYEN 9U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLFLOWPARITYEN 10U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLHDRPARITYEN 12U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXCREDITEN 13U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_MAX 14U + +/* NVLINK TL error fields */ +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLDATAPARITYERR 0U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLCTRLPARITYERR 1U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPROTOCOLERR 2U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXOVERFLOWERR 3U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMDATAPARITYERR 4U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMHDRPARITYERR 5U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRESPERR 6U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPOISONERR 7U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMDATAPARITYERR 8U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMHDRPARITYERR 9U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLFLOWPARITYERR 10U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLHDRPARITYERR 12U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXCREDITERR 13U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_MAX 14U + +/* NVLINK DL speed status for sublink Tx*/ +#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_HS (0x00000000U) +#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SINGLE_LANE (0x00000004U) +#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_TRAIN (0x00000005U) +#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SAFE (0x00000006U) +#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_OFF (0x00000007U) + +/* NVLINK DL speed status for sublink Rx*/ +#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_HS (0x00000000U) +#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SINGLE_LANE (0x00000004U) +#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_TRAIN (0x00000005U) +#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SAFE (0x00000006U) +#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_OFF (0x00000007U) + +/* Flags to query different debug registers */ +#define NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_DEFAULT (0x0U) +#define NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_INTR_STATUS (0x1U) +#define NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_ALI_STATUS (0x2U) + +#define NV2080_CTRL_NVLINK_MAX_IOCTRLS 3U +/* + * NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS + * + * linkMask + * Returns the mask of links enabled + * + * linkErrInfo + * Returns the error information for all the links + * + * ioctrlMask + * Returns the mask of ioctrls + * + * commonErrInfo + * Returns the error information common to each IOCTRL + * + * ErrInfoFlags + * Input for determining which values to query. Possible values: + * NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_INTR_STATUS + * NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_ALI_STATUS + * + */ +#define NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS { + NvU32 linkMask; + NV2080_CTRL_NVLINK_ERR_INFO linkErrInfo[NV2080_CTRL_NVLINK_MAX_LINKS]; + NvU32 ioctrlMask; + NV2080_CTRL_NVLINK_COMMON_ERR_INFO commonErrInfo[NV2080_CTRL_NVLINK_MAX_IOCTRLS]; + NvU8 ErrInfoFlags; +} NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_ERR_INFO + * This command is used to query the NVLINK error information + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_NVLINK_GET_ERR_INFO (0x20803003U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS_MESSAGE_ID" */ + +/* + * APIs for getting NVLink counters + */ + +// These are the bitmask definitions for different counter types + +#define NV2080_CTRL_NVLINK_COUNTER_INVALID 0x00000000U + +#define NV2080_CTRL_NVLINK_COUNTER_TL_TX0 0x00000001U +#define NV2080_CTRL_NVLINK_COUNTER_TL_TX1 0x00000002U +#define NV2080_CTRL_NVLINK_COUNTER_TL_RX0 0x00000004U +#define NV2080_CTRL_NVLINK_COUNTER_TL_RX1 0x00000008U + +#define NV2080_CTRL_NVLINK_LP_COUNTERS_DL 0x00000010U + +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L(i) (1 << (i + 8)) +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE__SIZE 4U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L0 0x00000100U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L1 0x00000200U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L2 0x00000400U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L3 0x00000800U + +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT 0x00010000U + +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L(i) (1 << (i + 17)) +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE__SIZE 8U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0 0x00020000U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1 0x00040000U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2 0x00080000U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3 0x00100000U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4 0x00200000U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5 0x00400000U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6 0x00800000U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7 0x01000000U + +#define NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_REPLAY 0x02000000U +#define NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_RECOVERY 0x04000000U + +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_REPLAY 0x08000000U + +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_MASKED 0x10000000U + +/* + * Note that COUNTER_MAX_TYPES will need to be updated each time + * a new counter type gets added to the list above. + * + */ +#define NV2080_CTRL_NVLINK_COUNTER_MAX_TYPES 32U + +/* + * NV2080_CTRL_CMD_NVLINK_GET_COUNTERS + * This command gets the counts for different counter types. + * + * [in] counterMask + * Mask of counter types to be queried + * One of NV2080_CTRL_NVLINK_COUNTERS_TYPE_* macros + * + * [in] linkMask + * Mask of links to be queried + * + * [out] counters + * Counter value returned + * + * [out] bTx0TlCounterOverflow + * This boolean is set to NV_TRUE if TX Counter 0 has rolled over. + * + * [out] bTx1TlCounterOverflow + * This boolean is set to NV_TRUE if TX Counter 1 has rolled over. + * + * [out] bRx0TlCounterOverflow + * This boolean is set to NV_TRUE if RX Counter 0 has rolled over. + * + * [out] bRx1TlCounterOverflow + * This boolean is set to NV_TRUE if RX Counter 1 has rolled over. + * + * [out] value + * This array contains the error counts for each error type as requested from + * the counterMask. The array indexes correspond to the mask bits one-to-one. + */ +typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES { + NvBool bTx0TlCounterOverflow; + NvBool bTx1TlCounterOverflow; + NvBool bRx0TlCounterOverflow; + NvBool bRx1TlCounterOverflow; + NV_DECLARE_ALIGNED(NvU64 value[NV2080_CTRL_NVLINK_COUNTER_MAX_TYPES], 8); +} NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES; + +#define NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS { + NvU32 counterMask; + NV_DECLARE_ALIGNED(NvU64 linkMask, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES counters[NV2080_CTRL_NVLINK_MAX_LINKS], 8); +} NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_COUNTERS (0x20803004U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS_MESSAGE_ID" */ + + +/* + * NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS + * This command clears/resets the counters for the specified types. + * + * [in] linkMask + * This parameter specifies for which links we want to clear the + * counters. + * + * [in] counterMask + * This parameter specifies the input mask for desired counters to be + * cleared. Note that all counters cannot be cleared. + * + * NOTE: Bug# 2098529: On Turing all DL errors and LP counters are cleared + * together. They cannot be cleared individually per error type. RM + * would possibly move to a new API on Ampere and beyond + */ + +#define NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS (0x20803005U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS { + NvU32 counterMask; + NV_DECLARE_ALIGNED(NvU64 linkMask, 8); +} NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_INJECT_ERROR + * This command causes all the same actions to occur as if the related + * error were to occur, either fatal or recoverable. + * + * [in] linkMask size: 32 bits + * Controls which links to apply error injection to. + * [in] bFatal + * This parameter specifies that the error should be fatal. + * + */ +#define NV2080_CTRL_CMD_NVLINK_INJECT_ERROR (0x20803006U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS { + NvU32 linkMask; + NvBool bFatalError; +} NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS; + +/* NVLINK unit list - to be used with error notifiers */ +#define NV2080_CTRL_NVLINK_UNIT_DL 0x01U +#define NV2080_CTRL_NVLINK_UNIT_TL 0x02U +#define NV2080_CTRL_NVLINK_UNIT_TLC_RX_0 0x03U +#define NV2080_CTRL_NVLINK_UNIT_TLC_RX_1 0x04U +#define NV2080_CTRL_NVLINK_UNIT_TLC_TX_0 0x05U +#define NV2080_CTRL_NVLINK_UNIT_MIF_RX_0 0x06U +#define NV2080_CTRL_NVLINK_UNIT_MIF_TX_0 0x07U + +/* + * NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES + * This command gets the number of successful error recoveries + * + * [in] linkMask size: 32 bits + * This parameter controls which links to get recoveries for. + * [out] numRecoveries + * This parameter specifies the number of successful per link error recoveries + */ +#define NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES (0x20803007U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS { + NvU32 linkMask; + NvU32 numRecoveries[NV2080_CTRL_NVLINK_MAX_LINKS]; +} NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE + * + * This command queries the remote endpoint type of the link recorded at the + * time the last error occurred on the link. + * + * [in] linkId + * This parameter specifies the link to get the last remote endpoint type + * recorded for. + * + * [out] remoteType + * This parameter returns the remote endpoint type of the link recorded at + * the time the last error occurred on the link. Possible values are: + * NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE + * The link is not connected to an active remote endpoint. + * NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU + * The remote endpoint of the link is a peer GPU. + * NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU + * The remote endpoint of the link is the host system (e.g., an NPU + * on IBM POWER platforms). + * NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA + * The remote endpoint of the link a tegra device + * + * Possible return status values are: + * NV_OK + * If the remoteType parameter value is valid upon return. + * NV_ERR_INVALID_ARGUMENT + * If the linkId parameter does not specify a valid link. + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on this GPU or the remote endpoint type is + * not recorded in non-volatile storage. + */ +#define NV2080_CTRL_CMD_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE (0x20803008U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS { + NvU32 linkId; + NvU32 remoteType; +} NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_LINK_FATAL_ERROR_COUNTS + * + * This command queries the number of each type of fatal errors that have + * occurred on the given link. + * + * [in] linkId + * This parameter specifies the link to get the fatal error information + * for. + * + * [out] supportedCounts + * This parameter identifies which counts in the fatalErrorCounts array + * are valid for the given link. A bit set in this field means that the + * corresponding index is valid in the fatalErrorCounts array. + * + * [out] fatalErrorCounts + * This parameter returns an array of 8-bit counts, one for each type of + * fatal error that can occur on the link. The valid indices of this array + * are: + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_RX_DL_DATA_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_RX_DL_CTRL_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_PROTOCOL + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_OVERFLOW + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_RX_RAM_DATA_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_RX_RAM_HDR_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RESP + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_POISON + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_POISONED_PKT_RCVD + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_TX_RAM_DATA_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_TX_RAM_HDR_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_CREDIT + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_FLOW_CTRL_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_FLOW_CTRL_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_HDR_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_RECOVERY_LONG + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_RAM + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_INTERFACE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_DL_PROTOCOL + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_HDR_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_AE_FLIT_RCVD + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_BE_FLIT_RCVD + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_ADDR_ALIGN + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_PKT_LEN + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CMD_ENC + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_DAT_LEN_ENC + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_ADDR_TYPE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_RSP_STATUS + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_PKT_STATUS + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_PO_FOR_CACHE_ATTR + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COMPRESSED_RESP + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_TARGET + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_HDR_OVERFLOW + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_OVERFLOW + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_STOMPED_PKT_RCVD + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_CORRECTABLE_INTERNAL + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_VC_OVERFLOW + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_HDR_CREDIT_OVERFLOW + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_CREDIT_OVERFLOW + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_REPLAY_CREDIT_OVERFLOW + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_UNSUPPORTED_VC_OVERFLOW + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_STOMPED_PKT_SENT + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_POISONED_PKT_SENT + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_TARGET + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_DATA_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_HDR_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_DATA_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_HDR_PARITY + * + * Possible return status values are: + * NV_OK + * If the values in the fatalErrorCounts array are valid upon return. + * NV_ERR_INVALID_ARGUMENT + * If the linkId parameter does not specify a valid link. + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on this GPU or aggregate NVLINK fatal error + * counts are not recorded in non-volatile storage. + */ +#define NV2080_CTRL_CMD_NVLINK_GET_LINK_FATAL_ERROR_COUNTS (0x20803009U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS_MESSAGE_ID" */ + +/* + * NVLink 1 Fatal Error Types + */ +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_DATA_PARITY 0U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_CTRL_PARITY 1U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_PROTOCOL 2U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_OVERFLOW 3U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_DATA_PARITY 4U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_HDR_PARITY 5U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RESP 6U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_POISON 7U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_DATA_PARITY 8U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_HDR_PARITY 9U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_CREDIT 10U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_FLOW_CTRL_PARITY 11U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_HDR_PARITY 12U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_RECOVERY_LONG 13U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_RAM 14U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_INTERFACE 15U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE 16U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE 17U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_DL_PROTOCOL 18U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT 19U + +/* + * NVLink 2 Fatal Error Types + */ +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_DATA_PARITY 0U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_CTRL_PARITY 1U +// No direct equivalent to: TL_RX_PROTOCOL 2 +// No direct equivalent to: TL_RX_OVERFLOW 3 +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_DATA_PARITY 4U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_HDR_PARITY 5U +// No direct equivalent to: TL_RX_RESP 6 +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_POISONED_PKT_RCVD 7U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_DATA_PARITY 8U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_HDR_PARITY 9U +// No direct equivalent to: TL_TX_CREDIT 10 +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_FLOW_CONTROL_PARITY 11U +// No direct equivalent to: TL_DL_HDR_PARITY 12 +// Identical to NVLink 1: DL_TX_RECOVERY_LONG 13 +// Identical to NVLink 1: DL_TX_FAULT_RAM 14 +// Identical to NVLink 1: DL_TX_FAULT_INTERFACE 15 +// Identical to NVLink 1: DL_TX_FAULT_SUBLINK_CHANGE 16 +// Identical to NVLink 1: DL_RX_FAULT_SUBLINK_CHANGE 17 +// Identical to NVLink 1: DL_RX_FAULT_DL_PROTOCOL 18 +// Identical to NVLink 1: DL_LTSSM_FAULT 19 +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_HDR_PARITY 20U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_AE_FLIT_RCVD 21U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_BE_FLIT_RCVD 22U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_ADDR_ALIGN 23U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_PKT_LEN 24U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CMD_ENC 25U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_DAT_LEN_ENC 26U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_ADDR_TYPE 27U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_RSP_STATUS 28U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_PKT_STATUS 29U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ 30U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP 31U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE 32U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE 33U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE 34U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_PO_FOR_CACHE_ATTR 35U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COMPRESSED_RESP 36U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_TARGET 37U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST 38U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_HDR_OVERFLOW 39U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_OVERFLOW 40U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_STOMPED_PKT_RCVD 41U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_CORRECTABLE_INTERNAL 42U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_VC_OVERFLOW 43U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE 44U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE 45U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_HDR_CREDIT_OVERFLOW 46U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_CREDIT_OVERFLOW 47U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_REPLAY_CREDIT_OVERFLOW 48U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_UNSUPPORTED_VC_OVERFLOW 49U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_STOMPED_PKT_SENT 50U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_POISONED_PKT_SENT 51U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_TARGET 52U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST 53U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_DATA_PARITY 54U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_HDR_PARITY 55U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_DATA_PARITY 56U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_HDR_PARITY 57U + +/* + * NVLink 3 Fatal Error Types + */ +// Identical to NVLink 2: TLC_RX_DL_DATA_PARITY 0 +// Identical to NVLink 2: TLC_RX_DL_CTRL_PARITY 1 +// No direct equivalent to: TL_RX_PROTOCOL 2 +// No direct equivalent to: TL_RX_OVERFLOW 3 +// No direct equivalent to: TLC_RX_RAM_DATA_PARITY 4 +// No direct equivalent to: RX_RAM_HDR_PARITY 5 +// No direct equivalent to: TL_RX_RESP 6 +// No direct equivalent to: TLC_RX_DATA_POISONED_PKT_RCVD 7 +// No direct equivalent to: TLC_TX_RAM_DATA_PARITY 8 +// No direct equivalent to: TLC_TX_RAM_HDR_PARITY 9 +// No direct equivalent to: TL_TX_CREDIT 10 +// Identical to NVLink 2: TLC_TX_DL_FLOW_CONTROL_PARITY 11 +// No direct equivalent to: TL_DL_HDR_PARITY 12 +// No direct equivalent to: DL_TX_RECOVERY_LONG 13 +// Identical to NVLink 1: DL_TX_FAULT_RAM 14 +// Identical to NVLink 1: DL_TX_FAULT_INTERFACE 15 +// Identical to NVLink 1: DL_TX_FAULT_SUBLINK_CHANGE 16 +// Identical to NVLink 1: DL_RX_FAULT_SUBLINK_CHANGE 17 +// Identical to NVLink 1: DL_RX_FAULT_DL_PROTOCOL 18 +// No direct equivalent to: DL_LTSSM_FAULT 19 +// Identical to NVLink 2: TLC_RX_DL_HDR_PARITY 20 +// Identical to NVLink 2: TLC_RX_INVALID_AE_FLIT_RCVD 21 +// Identical to NVLink 2: TLC_RX_INVALID_BE_FLIT_RCVD 22 +// Identical to NVLink 2: TLC_RX_INVALID_ADDR_ALIGN 23 +// Identical to NVLink 2: TLC_RX_PKT_LEN 24 +// Identical to NVLink 2: TLC_RX_RSVD_CMD_ENC 25 +// Identical to NVLink 2: TLC_RX_RSVD_DAT_LEN_ENC 26 +// No direct equivalent to: TLC_RX_RSVD_ADDR_TYPE 27 +// No direct equivalent to: TLC_RX_RSVD_RSP_STATUS 28 +// Identical to NVLink 2: TLC_RX_RSVD_PKT_STATUS 29 +// Identical to NVLink 2: TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ 30 +// Identical to NVLink 2: TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP 31 +// No direct equivalent to: TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE 32 +// Identical to NVLink 2: TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE 33 +// Identical to NVLink 2: TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE 34 +// Identical to NVLink 2: TLC_RX_INVALID_PO_FOR_CACHE_ATTR 35 +// Identical to NVLink 2: TLC_RX_INVALID_COMPRESSED_RESP 36 +// No direct equivalent to: TLC_RX_RESP_STATUS_TARGET 37 +// No direct equivalent to: TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST 38 +// Identical to NVLink 2: TLC_RX_HDR_OVERFLOW 39 +// Identical to NVLink 2: TLC_RX_DATA_OVERFLOW 40 +// Identical to NVLink 2: TLC_RX_STOMPED_PKT_RCVD 41 +// No direct equivalent to: TLC_RX_CORRECTABLE_INTERNAL 42 +// No direct equivalent to: TLC_RX_UNSUPPORTED_VC_OVERFLOW 43 +// No direct equivalent to: TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE 44 +// No direct equivalent to: TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE 45 +// No direct equivalent to: TLC_TX_HDR_CREDIT_OVERFLOW 46 +// No direct equivalent to: TLC_TX_DATA_CREDIT_OVERFLOW 47 +// No direct equivalent to: TLC_TX_DL_REPLAY_CREDIT_OVERFLOW 48 +// No direct equivalent to: TLC_TX_UNSUPPORTED_VC_OVERFLOW 49 +// No direct equivalent to: TLC_TX_STOMPED_PKT_SENT 50 +// No direct equivalent to: TLC_TX_DATA_POISONED_PKT_SENT 51 +// No direct equivalent to: TLC_TX_RESP_STATUS_TARGET 52 +// No direct equivalent to: TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST 53 +// No direct equivalent to: MIF_RX_RAM_DATA_PARITY 54 +// No direct equivalent to: MIF_RX_RAM_HDR_PARITY 55 +// No direct equivalent to: MIF_TX_RAM_DATA_PARITY 56 +// No direct equivalent to: MIF_TX_RAM_HDR_PARITY 57 +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COLLAPSED_RESPONSE 58U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_HDR_ECC_DBE 59U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_PARITY 60U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_UP 61U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_DOWN 62U + +#define NV2080_CTRL_NVLINK_NUM_FATAL_ERROR_TYPES 63U + +#define NV2080_CTRL_NVLINK_IS_FATAL_ERROR_COUNT_VALID(count, supportedCounts) \ + (!!((supportedCounts) & NVBIT64(count))) + +#define NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS { + NvU32 linkId; + NV_DECLARE_ALIGNED(NvU64 supportedCounts, 8); + NvU8 fatalErrorCounts[NV2080_CTRL_NVLINK_NUM_FATAL_ERROR_TYPES]; +} NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_LINK_NONFATAL_ERROR_RATES + * + * This command queries recent non-fatal error rates for the given link. + * + * The error rates specify the maximum number of errors per minute recorded + * for the given link within a 24-hour period for daily maximums or a 30-day + * period for monthly maximums. + * + * [in] linkId + * This parameter specifies the link to get the nonfatal error information + * for. + * + * [out] numDailyMaxNonfatalErrorRates + * This parameter returns the number of valid nonfatal error rate entries + * in the dailyMaxNonfatalErrorRates parameter. + * + * [out] dailyMaxNonfatalErrorRates + * This parameter returns maximum nonfatal error rate entries recorded + * over the last few 24-hour periods. For example, index 0 contains the + * maximum nonfatal error rate recorded in the current day, index 1 + * contains the maximum nonfatal error rate recorded yesterday ago, etc. + * + * [out] numMonthlyMaxNonfatalErrorRates + * This parameter returns the number of valid nonfatal error rate entries + * in the monthlyMaxNonfatalErrorRates parameter. + * + * [out] monthlyMaxNonfatalErrorRates + * THis parameter returns maximum nonfatal error rate entries recorded + * over the last few 30-day periods. For example, index 0 contains the + * maximum nonfatal error rate recorded in the current month, index 1 + * contains the maximum nonfatal error recorded last month, etc. + * + * Possible status values returned are: + * NV_OK + * If any nonfatal error rates are valid upon return. + * NV_ERR_INVALID_ARGUMENT + * If the linkId parameter does not specify a valid link. + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on this GPU or NVLINK nonfatal error rates + * are not recorded in non-volatile storage. + */ +#define NV2080_CTRL_CMD_NVLINK_GET_LINK_NONFATAL_ERROR_RATES (0x2080300aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS_MESSAGE_ID" */ + +typedef struct NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE { + NvU32 errorsPerMinute; + NvU32 timestamp; +} NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE; + +#define NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE_ENTRIES 5U + +#define NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS { + NvU32 linkId; + NvU32 numDailyMaxNonfatalErrorRates; + NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE dailyMaxNonfatalErrorRates[NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE_ENTRIES]; + NvU32 numMonthlyMaxNonfatalErrorRates; + NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE monthlyMaxNonfatalErrorRates[NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE_ENTRIES]; +} NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_SET_ERROR_INJECTION_MODE + * + * This command sets the injection mode so that error handling and error + * logging software can be aware that errors cropping up on links are + * intentional and not due to HW failures. + * + * [in] bEnabled + * This parameter specifies whether injection mode should be enabled or + * disabled. + * + * Possible status values returned are: + * NV_OK + * If injection mode is enabled or disabled according to the parameters. + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on this GPU. + */ +#define NV2080_CTRL_CMD_NVLINK_SET_ERROR_INJECTION_MODE (0x2080300bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS { + NvBool bEnabled; +} NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_SETUP_EOM + * + * This command passes a packed 32bit params value to NV_PMINION_MISC_0_SCRATCH_SWRW_0 + * and then issues an EOM DLCMD to minion for the desired link. Only one DLCMD + * at a time can be issued to any given link. + * + * Params Packing is specified in Minion IAS + */ +#define NV2080_CTRL_CMD_NVLINK_SETUP_EOM (0x2080300cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS { + NvU8 linkId; + NvU32 params; +} NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_SET_POWER_STATE + * + * This command sets the mask of links associated with the GPU + * to a target power state + * + * [in] linkMask + * Mask of links that will be put to desired power state + * Note: In Turing RM supports only tansitions into/out of L2 + * [in] powerState + * Target power state to which the links will transition + * This can be any one of NV2080_CTRL_NVLINK_POWER_STATE_* states + * + * Possible status values returned are: + * NV_OK + * If all links transitioned successfully to the target state + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip or if the power state + * is not enabled on the chip + * NV_ERR_INVALID_ARGUMENT + * If the any of the links in the mask is not enabled + * NV_ERR_INVALID_REQUEST + * If the power state transition is not supported + * NV_WARN_MORE_PROCESSING_REQUIRED + * Link has received the request for the power transition + * The transition will happen when the remote end also agrees + * + * Note: Currently only L0->L2 and L2->L0 is supported + */ +#define NV2080_CTRL_CMD_NVLINK_SET_POWER_STATE (0x2080300dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS { + NvU32 linkMask; + NvU32 powerState; +} NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS; + +// NVLink Power States +#define NV2080_CTRL_NVLINK_POWER_STATE_L0 (0x00U) +#define NV2080_CTRL_NVLINK_POWER_STATE_L1 (0x01U) +#define NV2080_CTRL_NVLINK_POWER_STATE_L2 (0x02U) +#define NV2080_CTRL_NVLINK_POWER_STATE_L3 (0x03U) + +/* + * NV2080_CTRL_CMD_NVLINK_GET_POWER_STATE + * + * This command gets the power state of a link associated + * with the GPU + * + * [in] linkId + * Link whose power state is being requested + * [out] powerState + * Current power state of the link + * Is any one the NV2080_CTRL_NVLINK_POWER_STATE_* states + * + * Possible status values returned are: + * NV_OK + * If the power state is retrieved successfully + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip + * NV_ERR_INVALID_ARGUMENT + * If the link is not enabled on the GPU + * NV_ERR_INVALID_STATE + * If the link is in an invalid state + */ +#define NV2080_CTRL_CMD_NVLINK_GET_POWER_STATE (0x2080300eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS { + NvU32 linkId; + NvU32 powerState; +} NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_INJECT_TLC_ERROR + * + * This command injects TLC_*_REPORT_INJECT error. An RM interrupt + * will be triggered after injection. Currently the injection call + * only deals with HW_ERR, UR_ERR, PRIV_ERR in TX_SYS and RX_LNK devices + * + * [in] linkId + * Link whose power state is being requested. + * [in] errorType + * error type that needs to be injected. + * [in] device + * The device this injection is intended for. + * [in] bBroadcast + * Whether the link report error should be fired in multiple links. + + * Possible status values returned are: + * NV_OK + * If the injection succeeds. + * NV_ERR_NOT_SUPPORTED + * If the error type of NVLINK is not supported on the chip + */ +#define NV2080_CTRL_CMD_NVLINK_INJECT_TLC_ERROR (0x2080300fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE { + TLC_RX_LNK = 0, + TLC_TX_SYS = 1, +} NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE; + +typedef enum NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE { + TX_SYS_TX_RSP_STATUS_HW_ERR = 0, + TX_SYS_TX_RSP_STATUS_UR_ERR = 1, + TX_SYS_TX_RSP_STATUS_PRIV_ERR = 2, +} NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE; + +typedef enum NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE { + RX_LNK_RX_RSP_STATUS_HW_ERR = 0, + RX_LNK_RX_RSP_STATUS_UR_ERR = 1, + RX_LNK_RX_RSP_STATUS_PRIV_ERR = 2, +} NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE; + +typedef union NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE { + NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE txSysErrorType; + NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE rxLnkErrorType; +} NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE; + + +#define NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS { + NvU32 linkId; + NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE device; + NvBool bBroadcast; + NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE errorType; +} NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS; + + + +/* + * NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES + * + * This command returns the per-lane Figure Of Merit (FOM) Values from a link + * + * [in] linkId + * The NVLink link ID to report FOM values for + * [out] numLanes + * This field specifies the no. of lanes per link + * [out] figureOfMeritValues + * This field contains the FOM values per lane + * + */ +#define NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES (0x20803011U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_MAX_LANES 4U + +#define NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS { + NvU32 linkId; + NvU8 numLanes; + NvU16 figureOfMeritValues[NV2080_CTRL_NVLINK_MAX_LANES]; +} NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS; + +/* + * NV2080_CTRL_NVLINK_SET_NVLINK_PEER + * + * This command sets/unsets the USE_NVLINK_PEER bit for a given + * mask of peers + * + * [in] peerMask + * Mask of Peer IDs for which USE_NVLINK_PEER needs to be updated + * [in] bEnable + * Whether the bit needs to be set or unset + * + * Possible status values returned are: + * NV_OK + * If the USE_NVLINK_PEER bit was updated successfully + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip, or + * If unsetting USE_NVLINK_PEER bit is not supported + * + * NOTE: This is only supported on Windows + * + */ +#define NV2080_CTRL_CMD_NVLINK_SET_NVLINK_PEER (0x20803012U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS { + NvU32 peerMask; + NvBool bEnable; +} NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_READ_UPHY_PAD_LANE_REG + * + * This command packs the lane and addr values into NV_PMINION_MISC_0_SCRATCH_SWRW_0 + * and then issues a READPADLANEREG DLCMD to minion for the desired link. Only one DLCMD + * at a time can be issued to any given link. + * + * After this command completes it is necessary to read the appropriate + * NV_PNVL_BR0_PAD_CTL_7_CFG_RDATA register to retrieve the results of the read + * Only GV100 should read NV_PNVL_BR0_PAD_CTL_7_CFG_RDATA. + * From TU102+ the ctrl the required data would be updated in phyConfigData. + * + * [in] linkId + * Link whose pad lane register is being read + * [in] lane + * Lane whose pad lane register is being read + * [in] addr + * Address of the pad lane register to read + * [out] phyConfigData + * Provides phyconfigaddr and landid + * + * Possible status values returned are: + * NV_OK + * If the minion command completed successfully + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip + * NV_ERR_INVALID_ARGUMENT + * If the link is not enabled on the GPU or the lane is invalid + * NV_ERR_TIMEOUT + * If a timeout occurred waiting for minion response + */ +#define NV2080_CTRL_CMD_NVLINK_READ_UPHY_PAD_LANE_REG (0x20803013U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS { + NvU8 linkId; + NvU8 lane; + NvU16 addr; + NvU32 phyConfigData; +} NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS; + +/* + * Structure to store the ECC error data. + * valid + * Is the lane valid or not + * eccErrorValue + * Value of the Error. + * overflowed + * If the error overflowed or not + */ +typedef struct NV2080_CTRL_NVLINK_LANE_ERROR { + NvBool bValid; + NvU32 eccErrorValue; + NvBool overflowed; +} NV2080_CTRL_NVLINK_LANE_ERROR; + +/* + * Structure to store ECC error data for Links + * errorLane array index corresponds to the lane number. + * + * errorLane[] + * Stores the ECC error data per lane. + */ +typedef struct NV2080_CTRL_NVLINK_LINK_ECC_ERROR { + NV2080_CTRL_NVLINK_LANE_ERROR errorLane[NV2080_CTRL_NVLINK_MAX_LANES]; + NvU32 eccDecFailed; + NvBool eccDecFailedOverflowed; +} NV2080_CTRL_NVLINK_LINK_ECC_ERROR; + +/* + * NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS + * + * Control to get the values of ECC ERRORS + * + * Parameters: + * linkMask [IN] + * Links on which the ECC error data requested + * A valid link/port mask returned by the port masks returned by + * NVSWITCH_GET_INFO + * errorLink[] [OUT] + * Stores the ECC error related information for each link. + * errorLink array index corresponds to the link Number. + */ + +#define NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS { + NvU32 linkMask; + NV2080_CTRL_NVLINK_LINK_ECC_ERROR errorLink[NV2080_CTRL_NVLINK_MAX_LINKS]; +} NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS; + + +#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_ECC_ERRORS (0x20803014U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS_MESSAGE_ID" */ + +// Nvlink throughput counters reading data flits in TX +#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_TX 0U + +// Nvlink throughput counters reading data flits in RX +#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_RX 1U + +// Nvlink throughput counters reading all flits in TX +#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_TX 2U + +// Nvlink throughput counters reading all flits in RX +#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_RX 3U + +#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_MAX 4U + +/* + * NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS + * + * Reads reserved monotonically increasing NVLINK throughput counters for given linkIds + * + * [in] counterMask + * Mask of counter types to be queried + * One of NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_* macros + * [in] linkMask + * Mask of links to be queried + * [out] value + * Throughput counter value returned + * + * Possible status values returned are: + * NV_OK + * If command completed successfully + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip + * NV_ERR_INVALID_ARGUMENT + * If numLinks is out-of-range or requested link is inactive + * + * Note: + * The following commands will be deprecated in favor of NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS: + * NV90CC_CTRL_CMD_NVLINK_GET_COUNTERS + * NV2080_CTRL_CMD_NVLINK_GET_COUNTERS + * Other commands that will be deprecated due to the change in design: + * NV90CC_CTRL_CMD_NVLINK_RESERVE_COUNTERS + * NV90CC_CTRL_CMD_NVLINK_RELEASE_COUNTERS + * NV90CC_CTRL_CMD_NVLINK_SET_COUNTERS_FROZEN + * NV90CC_CTRL_CMD_NVLINK_GET_TL_COUNTER_CFG + * NV90CC_CTRL_CMD_NVLINK_SET_TL_COUNTER_CFG + * NV90CC_CTRL_CMD_NVLINK_CLEAR_COUNTERS + * + * Also, note that there is no counter overflow handling for these calls. + * These counters would be counting in flits and assuming 25GB/s bandwidth per link, + * with traffic flowing continuously, it would take 174 years for overflow to happen. + * It is reasonable to assume an overflow will not occur within the GPU operation, + * given that the counters get reset at system reboot or GPU reset. Counters are 63-bit. + */ + +typedef struct NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES { + NV_DECLARE_ALIGNED(NvU64 value[NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_MAX], 8); +} NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES; + +#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS { + NvU16 counterMask; + NV_DECLARE_ALIGNED(NvU64 linkMask, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES counters[NV2080_CTRL_NVLINK_MAX_LINKS], 8); +} NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS (0x20803015U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE + * + * This command locks the link power state so that RM doesn't modify the state + * of the link during pstate switch. + * + * [in] linkMask Links for which power mode needs to be locked. + */ +#define NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE (0x20803016U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS { + NvBool bLockPowerMode; +} NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_ENABLE_NVLINK_PEER + * + * This command is used to enable RM NVLink enabled peer state. + * Note: This just updates the RM state. To reflect the state in the registers, + * use NV2080_CTRL_CMD_NVLINK_SET_NVLINK_PEER + * + * [in] peerMask + * Mask of Peer IDs for which USE_NVLINK_PEER needs to be enabled + * [in] bEnable + * Whether the bit needs to be set or unset + * + * Possible status values returned are: + * NV_OK + * If the USE_NVLINK_PEER bit was enabled successfully + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip, or + * If unsetting USE_NVLINK_PEER bit is not supported + * + */ +#define NV2080_CTRL_CMD_NVLINK_ENABLE_NVLINK_PEER (0x20803017U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID (0x17U) + +typedef struct NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS { + NvU32 peerMask; + NvBool bEnable; +} NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS; + +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_NVHS 0U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_EIGHTH 1U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_OTHER 2U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_ENTER 3U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_EXIT 4U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_SLEEP 5U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS 6U + +/* + * NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS + * + * Reads NVLINK low power counters for given linkId + * + * [in] linkId + * ID of the link to be queried + * [in,out] counterValidMask + * Mask of valid counters + * [out] counterValues + * Low power counter values returned + * + * Possible status values returned are: + * NV_OK + * If command completed successfully + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip + * NV_ERR_INVALID_ARGUMENT + * If linkId is out-of-range or requested link is inactive + */ + +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS { + NvU32 linkId; + NvU32 counterValidMask; + NvU32 counterValues[NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS]; +} NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS (0x20803018U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID" */ + +/* + * NVLINK Link states + * These should ALWAYS match the nvlink core library defines in nvlink.h + */ +#define NV2080_NVLINK_CORE_LINK_STATE_OFF 0x00U +#define NV2080_NVLINK_CORE_LINK_STATE_HS 0x01U +#define NV2080_NVLINK_CORE_LINK_STATE_SAFE 0x02U +#define NV2080_NVLINK_CORE_LINK_STATE_FAULT 0x03U +#define NV2080_NVLINK_CORE_LINK_STATE_RECOVERY 0x04U +#define NV2080_NVLINK_CORE_LINK_STATE_FAIL 0x05U +#define NV2080_NVLINK_CORE_LINK_STATE_DETECT 0x06U +#define NV2080_NVLINK_CORE_LINK_STATE_RESET 0x07U +#define NV2080_NVLINK_CORE_LINK_STATE_ENABLE_PM 0x08U +#define NV2080_NVLINK_CORE_LINK_STATE_DISABLE_PM 0x09U +#define NV2080_NVLINK_CORE_LINK_STATE_SLEEP 0x0AU +#define NV2080_NVLINK_CORE_LINK_STATE_SAVE_STATE 0x0BU +#define NV2080_NVLINK_CORE_LINK_STATE_RESTORE_STATE 0x0CU +#define NV2080_NVLINK_CORE_LINK_STATE_PRE_HS 0x0EU +#define NV2080_NVLINK_CORE_LINK_STATE_DISABLE_ERR_DETECT 0x0FU +#define NV2080_NVLINK_CORE_LINK_STATE_LANE_DISABLE 0x10U +#define NV2080_NVLINK_CORE_LINK_STATE_LANE_SHUTDOWN 0x11U +#define NV2080_NVLINK_CORE_LINK_STATE_TRAFFIC_SETUP 0x12U +#define NV2080_NVLINK_CORE_LINK_STATE_INITPHASE1 0x13U +#define NV2080_NVLINK_CORE_LINK_STATE_INITNEGOTIATE 0x14U +#define NV2080_NVLINK_CORE_LINK_STATE_POST_INITNEGOTIATE 0x15U +#define NV2080_NVLINK_CORE_LINK_STATE_INITOPTIMIZE 0x16U +#define NV2080_NVLINK_CORE_LINK_STATE_POST_INITOPTIMIZE 0x17U +#define NV2080_NVLINK_CORE_LINK_STATE_DISABLE_HEARTBEAT 0x18U +#define NV2080_NVLINK_CORE_LINK_STATE_CONTAIN 0x19U +#define NV2080_NVLINK_CORE_LINK_STATE_INITTL 0x1AU +#define NV2080_NVLINK_CORE_LINK_STATE_INITPHASE5 0x1BU +#define NV2080_NVLINK_CORE_LINK_STATE_ALI 0x1CU +#define NV2080_NVLINK_CORE_LINK_STATE_ACTIVE_PENDING 0x1DU +#define NV2080_NVLINK_CORE_LINK_STATE_INVALID 0xFFU + +/* + * NVLINK TX Sublink states + * These should ALWAYS match the nvlink core library defines in nvlink.h + */ +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_HS 0x00U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SINGLE_LANE 0x04U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_LOW_POWER 0x04U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_TRAIN 0x05U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SAFE 0x06U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_OFF 0x07U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE 0x08U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE_DISABLE 0x09U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_DATA_READY 0x0AU +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_EQ 0x0BU +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_PRBS_EN 0x0CU +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_POST_HS 0x0DU + +/* + * NVLINK RX Sublink states + * These should ALWAYS match the nvlink core library defines in nvlink.h + */ +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_HS 0x00U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SINGLE_LANE 0x04U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_LOW_POWER 0x04U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_TRAIN 0x05U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SAFE 0x06U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_OFF 0x07U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_RXCAL 0x08U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_INIT_TERM 0x09U + +/* + * Link training seed values + * These should ALWAYS match the values defined in nvlink.h + */ +#define NV2080_CTRL_NVLINK_MAX_SEED_NUM 6U +#define NV2080_CTRL_NVLINK_MAX_SEED_BUFFER_SIZE (0x7U) /* finn: Evaluated from "NV2080_CTRL_NVLINK_MAX_SEED_NUM + 1" */ + +// NVLINK callback types +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_DL_LINK_MODE 0x00U +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_DL_LINK_MODE 0x01U +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_TL_LINK_MODE 0x02U +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_TL_LINK_MODE 0x03U +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_TX_SUBLINK_MODE 0x04U +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_TX_SUBLINK_MODE 0x05U +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_MODE 0x06U +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_MODE 0x07U +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_DETECT 0x08U +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_DETECT 0x09U +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_WRITE_DISCOVERY_TOKEN 0x0AU +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_READ_DISCOVERY_TOKEN 0x0BU +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_TRAINING_COMPLETE 0x0CU +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_UPHY_LOAD 0x0DU + +/* + * Structure to store the GET_DL_MODE callback params. + * mode + * The current Nvlink DL mode + */ +typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS { + NvU32 mode; +} NV2080_CTRL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS; + +/* + * Structure to store the SET_DL_LINK_MODE callback OFF params + * seedData + * The output seed data + */ +typedef struct NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS { + NvU32 seedData[NV2080_CTRL_NVLINK_MAX_SEED_BUFFER_SIZE]; +} NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS; + +/* + * Structure to store the SET_DL_LINK_MODE callback PRE_HS params + * remoteDeviceType + * The input remote Device Type + * ipVerDlPl + * The input DLPL version + */ +typedef struct NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS { + NvU32 remoteDeviceType; + NvU32 ipVerDlPl; +} NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS; + +/* + * Structure to store SET_DL_LINK_MODE callback INIT_PHASE1 params + * seedData[] + * The input seed data + */ +typedef struct NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS { + NvU32 seedData[NV2080_CTRL_NVLINK_MAX_SEED_BUFFER_SIZE]; +} NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS; + +/* + * Structure to store the Nvlink Remote and Local SID info + * remoteSid + * The output remote SID + * remoteDeviceType + * The output remote Device Type + * remoteLinkId + * The output remote link ID + * localSid + * The output local SID + */ +typedef struct NV2080_CTRL_NVLINK_REMOTE_LOCAL_SID_INFO { + NV_DECLARE_ALIGNED(NvU64 remoteSid, 8); + NvU32 remoteDeviceType; + NvU32 remoteLinkId; + NV_DECLARE_ALIGNED(NvU64 localSid, 8); +} NV2080_CTRL_NVLINK_REMOTE_LOCAL_SID_INFO; + +/* + * Structure to store the SET_DL_LINK_MODE callback POST_INITNEGOTIATE params + * bInitnegotiateConfigGood + * The output bool if the config is good + * remoteLocalSidInfo + * The output structure containing the Nvlink Remote/Local SID info + */ +typedef struct NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS { + NvBool bInitnegotiateConfigGood; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_REMOTE_LOCAL_SID_INFO remoteLocalSidInfo, 8); +} NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS; + +/* + * Structure to store the SET_DL_LINK_MODE callback POST_INITOPTIMIZE params + * bPollDone + * The output bool if the polling has finished + */ +typedef struct NV2080_CTRLNVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS { + NvBool bPollDone; +} NV2080_CTRLNVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS; + +/* + * Structure to store the SET_DL_LINK_MODE callback params + * mode + * The input nvlink state to set + * bSync + * The input sync boolean + * linkMode + * The input link mode to be set for the callback + */ +typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 mode, 8); + NvBool bSync; + NvU32 linkMode; + union { + NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS linkModeOffParams; + NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS linkModePreHsParams; + NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS linkModeInitPhase1Params; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS linkModePostInitNegotiateParams, 8); + NV2080_CTRLNVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS linkModePostInitOptimizeParams; + } linkModeParams; +} NV2080_CTRL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS; + +/* + * Structure to store the GET_TL_MODE callback params. + * mode + * The current Nvlink TL mode + */ +typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS { + NvU32 mode; +} NV2080_CTRL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS; + +/* + * Structure to store the SET_TL_LINK_MODE callback params + * mode + * The input nvlink mode to set + * bSync + * The input sync boolean + */ +typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 mode, 8); + NvBool bSync; +} NV2080_CTRL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS; + +/* + * Structure to store the GET_RX/TX_SUBLINK_MODE callback params + * sublinkMode + * The current Sublink mode + * sublinkSubMode + * The current Sublink sub mode + */ +typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS { + NvU32 sublinkMode; + NvU32 sublinkSubMode; +} NV2080_CTRL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS; + +/* + * Structure to store the SET_TL_LINK_MODE callback params + * mode + * The input nvlink mode to set + * bSync + * The input sync boolean + */ +typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 mode, 8); + NvBool bSync; +} NV2080_CTRL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS; + +/* + * Structure to store the SET_RX_SUBLINK_MODE callback params + * mode + * The input nvlink mode to set + * bSync + * The input sync boolean + */ +typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 mode, 8); + NvBool bSync; +} NV2080_CTRL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS; + +/* + * Structure to store the GET_RX_SUBLINK_DETECT callback params + * laneRxdetStatusMask + * The output RXDET per-lane status mask + */ +typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS { + NvU32 laneRxdetStatusMask; +} NV2080_CTRL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS; + +/* + * Structure to store the SET_RX_DETECT callback params + * bSync + * The input bSync boolean + */ +typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS { + NvBool bSync; +} NV2080_CTRL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS; + +/* + * Structure to store the RD_WR_DISCOVERY_TOKEN callback params + * ipVerDlPl + * The input DLPL version + * token + * The output token + */ +typedef struct NV2080_CTRL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS { + NvU32 ipVerDlPl; + NV_DECLARE_ALIGNED(NvU64 token, 8); +} NV2080_CTRL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS; + +/* + * Structure to store the GET_UPHY_LOAD callback params + * bUnlocked + * The output unlocked boolean + */ +typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS { + NvBool bUnlocked; +} NV2080_CTRL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS; + +/* + * Structure to store the Union of Callback params + * type + * The input type of callback to be executed + */ +typedef struct NV2080_CTRL_NVLINK_CALLBACK_TYPE { + NvU8 type; + union { + NV2080_CTRL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS getDlLinkMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS setDlLinkMode, 8); + NV2080_CTRL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS getTlLinkMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS setTlLinkMode, 8); + NV2080_CTRL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS getTxSublinkMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS setTxSublinkMode, 8); + NV2080_CTRL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS getRxSublinkMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS setRxSublinkMode, 8); + NV2080_CTRL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS getRxSublinkDetect; + NV2080_CTRL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS setRxSublinkDetect; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS writeDiscoveryToken, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS readDiscoveryToken, 8); + NV2080_CTRL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS getUphyLoad; + } callbackParams; +} NV2080_CTRL_NVLINK_CALLBACK_TYPE; + +/* + * NV2080_CTRL_CMD_NVLINK_CORE_CALLBACK + * + * Generic NvLink callback RPC to route commands to GSP + * + * [In] linkdId + * ID of the link to be used + * [In/Out] callBackType + * Callback params + */ +#define NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS { + NvU32 linkId; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_TYPE callbackType, 8); +} NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_CORE_CALLBACK (0x20803019U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_GET_ALI_ENABLED + * + * Returns if ALI is enabled + * + * [Out] bEnableAli + * Output boolean for ALI enablement + */ +#define NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID (0x1aU) + +typedef struct NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS { + NvBool bEnableAli; +} NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_ALI_ENABLED (0x2080301aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_UPDATE_REMOTE_LOCAL_SID + * + * Update Remote and Local Sid info via GSP + * + * [In] linkId + * ID of the link to be used + * [Out] remoteLocalSidInfo + * The output structure containing the Nvlink Remote/Local SID info + */ +#define NV2080_CTRL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID (0x1bU) + +typedef struct NV2080_CTRL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS { + NvU32 linkId; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_REMOTE_LOCAL_SID_INFO remoteLocalSidInfo, 8); +} NV2080_CTRL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_UPDATE_REMOTE_LOCAL_SID (0x2080301bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_TYPE_PROGRAM 0x0U +#define NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_TYPE_RESET 0x1U + +/* + * NV2080_CTRL_CMD_NVLINK_UPDATE_HSHUB_MUX + * + * Generic Hshub Mux Update RPC to route commands to GSP + * + * [In] updateType + * HSHUB Mux update type to program or reset Mux + * [In] bSysMem + * Boolean to differentiate between sysmen and peer mem + * [In] peerMask + * Mask of peer IDs. Only parsed when bSysMem is false + */ +#define NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID (0x1cU) + +typedef struct NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_PARAMS { + NvBool updateType; + NvBool bSysMem; + NvU32 peerMask; +} NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_UPDATE_HSHUB_MUX (0x2080301cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_PRE_SETUP_NVLINK_PEER + * + * Performs all the necessary actions required before setting a peer on NVLink + * + * [In] peerId + * Peer ID which will be set on NVLink + * [In] peerLinkMask + * Mask of links that connects the given peer + * [In] bNvswitchConn + * Is the GPU connected to NVSwitch + */ +#define NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID (0x1dU) + +typedef struct NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS { + NvU32 peerId; + NvU32 peerLinkMask; + NvBool bNvswitchConn; +} NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS; +#define NV2080_CTRL_CMD_NVLINK_PRE_SETUP_NVLINK_PEER (0x2080301dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_POST_SETUP_NVLINK_PEER + * + * Performs all the necessary actions required after setting a peer on NVLink + * + * [In] peerMask + * Mask of Peer IDs which has been set on NVLink + */ +#define NV2080_CTRL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID (0x1eU) + +typedef struct NV2080_CTRL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS { + NvU32 peerMask; +} NV2080_CTRL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS; +#define NV2080_CTRL_CMD_NVLINK_POST_SETUP_NVLINK_PEER (0x2080301eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_SYSMEM 0x1U +#define NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_PEER 0x2U + +/* + * NV2080_CTRL_CMD_NVLINK_REMOVE_NVLINK_MAPPING + * + * Performs all the necessary actions required to remove NVLink mapping (sysmem or peer or both) + * + * [In] mapTypeMask + * Remove NVLink mapping for the given map types (sysmem or peer or both) + * [In] peerMask + * Mask of Peer IDs which needs to be removed on NVLink + * Only parsed if mapTypeMask accounts peer + * [In] bL2Entry + * Is the peer removal happening because links are entering L2 low power state? + * Only parsed if mapTypeMask accounts peer + */ +#define NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID (0x1fU) + +typedef struct NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS { + NvU32 mapTypeMask; + NvU32 peerMask; + NvBool bL2Entry; +} NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS; +#define NV2080_CTRL_CMD_NVLINK_REMOVE_NVLINK_MAPPING (0x2080301fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_SAVE_RESTORE_HSHUB_STATE + * + * Performs all the necessary actions required to save/restore HSHUB state during NVLink L2 entry/exit + * + * [In] bSave + * Whether this is a save/restore operation + * [In] linkMask + * Mask of links for which HSHUB config registers need to be saved/restored + */ +#define NV2080_CTRL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV2080_CTRL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS { + NvBool bSave; + NvU32 linkMask; +} NV2080_CTRL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS; +#define NV2080_CTRL_CMD_NVLINK_SAVE_RESTORE_HSHUB_STATE (0x20803020U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SET (0x00000000) +#define NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SAVE (0x00000001) +#define NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_RESTORE (0x00000002) + +/* + * NV2080_CTRL_CMD_NVLINK_PROGRAM_BUFFERREADY + * + * Performs all the necessary actions required to save/restore bufferready state during NVLink L2 entry/exit + * + * [In] flags + * Whether to set, save or restore bufferready + * [In] bSysmem + * Whether to perform the operation for sysmem links or peer links + * [In] peerLinkMask + * Mask of peer links for which bufferready state need to be set/saved/restored + */ +#define NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID (0x21U) + +typedef struct NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_PARAMS { + NvU32 flags; + NvBool bSysmem; + NvU32 peerLinkMask; +} NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_PARAMS; +#define NV2080_CTRL_CMD_NVLINK_PROGRAM_BUFFERREADY (0x20803021U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_UPDATE_CURRENT_CONFIG + * + * Performs all the necessary actions required to update the current Nvlink configuration + * + * [out] bNvlinkSysmemEnabled + * Whether sysmem nvlink support was enabled + */ +#define NV2080_CTRL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NV2080_CTRL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS { + NvBool bNvlinkSysmemEnabled; +} NV2080_CTRL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS; +#define NV2080_CTRL_CMD_NVLINK_UPDATE_CURRENT_CONFIG (0x20803022U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID" */ + +// +// Set the near end loopback mode using the following +// Currently, three modes - NEA, NEDR, NEW +// +#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_DEFAULT (0x00000000) +#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEA (0x00000001) +#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDR (0x00000002) +#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDW (0x00000003) + +/* + * NV2080_CTRL_CMD_NVLINK_SET_LOOPBACK_MODE + * + * Generic NvLink callback for MODS + * + * [In] linkdId + * ID of the link to be used + * [In] loopbackMode + * This value will decide which loopback mode need to + * set on the specified link. + * Modes are NEA / NEDR / NEDW + */ +#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS_MESSAGE_ID (0x23U) + +typedef struct NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS { + NvU32 linkId; + NvU8 loopbackMode; +} NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_SET_LOOPBACK_MODE (0x20803023U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_UPDATE_PEER_LINK_MASK + * + * Synchronizes the peerLinkMask between CPU-RM and GSP-RM + * + * [In] gpuInst + * Gpu instance + * [In] peerLinkMask + * Mask of links to the given peer GPU + */ +#define NV2080_CTRL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID (0x24U) + +typedef struct NV2080_CTRL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS { + NvU32 gpuInst; + NvU32 peerLinkMask; +} NV2080_CTRL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_UPDATE_PEER_LINK_MASK (0x20803024U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_UPDATE_LINK_CONNECTION + * + * Updates the remote connection information for a link + * + * [In] linkId + * Id of the link to be used + * [In] bConnected + * Boolean that tracks whether the link is connected + * [In] remoteDeviceType + * Tracks whether the remote device is switch/gpu/ibmnpu/tegra + * [In] remoteLinkNumber + * Tracks the link number for the connected remote device + */ +#define NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID (0x25U) + +typedef struct NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS { + NV_DECLARE_ALIGNED(NvU64 remoteDeviceType, 8); + NV_DECLARE_ALIGNED(NvU64 remoteChipSid, 8); + NvU32 linkId; + NvU32 laneRxdetStatusMask; + NvU32 remoteLinkNumber; + NvU32 remotePciDeviceId; + NvU32 remoteDomain; + NvU8 remoteBus; + NvU8 remoteDevice; + NvU8 remoteFunction; + NvBool bConnected; +} NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_UPDATE_LINK_CONNECTION (0x20803025U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS_POST_TOPOLOGY + * + * Enable links post topology via GSP + * + * [In] linkMask + * Mask of links to enable + * [Out] initializedLinks + * Mask of links that were initialized + */ +#define NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID (0x26U) + +typedef struct NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS { + NvU32 linkMask; + NvU32 initializedLinks; +} NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS_POST_TOPOLOGY (0x20803026U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_PRE_LINK_TRAIN_ALI + * + * [In] linkMask + * Mask of enabled links to train + * [In] bSync + * The input sync boolean + */ +#define NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID (0x27U) + +typedef struct NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS { + NvU32 linkMask; + NvBool bSync; +} NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_PRE_LINK_TRAIN_ALI (0x20803027U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID" */ + +// +// Read Refresh counter - the pass/fail occurrences +// + +typedef struct NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO { + // requested links or not + NvBool bValid; + + // counters + NvU16 passCount; + NvU16 failCount; +} NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO; + +#define NV2080_CTRL_NVLINK_MAX_LINK_COUNT 32 + +/* + * NV2080_CTRL_CMD_NVLINK_GET_REFRESH_COUNTERS + * + * + * [In] linkMask + * Specifies for which links we want to read the counters + * [Out] refreshCountPass + * Count of number of times PHY refresh pass + * [Out] refreshCountFail + * Count of number of times PHY refresh fail + */ +#define NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS_MESSAGE_ID (0x28U) + +typedef struct NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS { + NvU32 linkMask; + NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO refreshCount[NV2080_CTRL_NVLINK_MAX_LINK_COUNT]; +} NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_REFRESH_COUNTERS (0x20803028U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS_MESSAGE_ID" */ + +// +// Clear Refresh counter - the pass/fail occurrences +// + +/* + * NV2080_CTRL_CMD_NVLINK_CLEAR_REFRESH_COUNTERS + * + * + * [In] linkMask + * Specifies for which links we want to clear the counters + */ +#define NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS_MESSAGE_ID (0x29U) + +typedef struct NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS { + NvU32 linkMask; +} NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_CLEAR_REFRESH_COUNTERS (0x20803029U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_GET_LINK_MASK_POST_RX_DET + * + * Get link mask post Rx detection + * + * [Out] postRxDetLinkMask + * Mask of links discovered + */ +#define NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID (0x2aU) + +typedef struct NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS { + NvU32 postRxDetLinkMask; +} NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_LINK_MASK_POST_RX_DET (0x2080302aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_LINK_TRAIN_ALI + * + * [In] linkMask + * Mask of enabled links to train + * [In] bSync + * The input sync boolean + */ +#define NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID (0x2bU) + +typedef struct NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS { + NvU32 linkMask; + NvBool bSync; +} NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_LINK_TRAIN_ALI (0x2080302bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID" */ + +typedef struct NV2080_CTRL_NVLINK_DEVICE_LINK_VALUES { + NvBool bValid; + NvU8 linkId; + NvU32 ioctrlId; + NvU8 pllMasterLinkId; + NvU8 pllSlaveLinkId; + NvU32 ipVerDlPl; +} NV2080_CTRL_NVLINK_DEVICE_LINK_VALUES; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_NVLINK_DEVICE_INFO + * + * [Out] ioctrlMask + * Mask of IOCTRLs discovered from PTOP device info table + * [Out] ioctrlNumEntries + * Number of IOCTRL entries in the PTOP device info table + * [Out] ioctrlSize + * Maximum number of entries in the PTOP device info table + * [Out] discoveredLinks + * Mask of links discovered from all the IOCTRLs + * [Out] ipVerNvlink + * IP revision of the NVLink HW + * [Out] linkInfo + * Per link information + */ + +#define NV2080_CTRL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID (0x2cU) + +typedef struct NV2080_CTRL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS { + NvU32 ioctrlMask; + NvU8 ioctrlNumEntries; + NvU32 ioctrlSize; + NvU32 discoveredLinks; + NvU32 ipVerNvlink; + NV2080_CTRL_NVLINK_DEVICE_LINK_VALUES linkInfo[NV2080_CTRL_NVLINK_MAX_LINKS]; +} NV2080_CTRL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_DEVICE_INFO (0x2080302cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_MAX_LINKS_PER_IOCTRL_SW 6U + +typedef struct NV2080_CTRL_NVLINK_DEVICE_IP_REVISION_VALUES { + NvU32 ipVerIoctrl; + NvU32 ipVerMinion; +} NV2080_CTRL_NVLINK_DEVICE_IP_REVISION_VALUES; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_IOCTRL_DEVICE_INFO + * + * [In] ioctrlIdx + * IOCTRL index + * [Out] PublicId + * PublicId of the IOCTRL discovered + * [Out] localDiscoveredLinks + * Mask of discovered links local to the IOCTRL + * [Out] localGlobalLinkOffset + * Global link offsets for the locally discovered links + * [Out] ioctrlDiscoverySize + * IOCTRL table size + * [Out] numDevices + * Number of devices discovered from the IOCTRL + * [Out] deviceIpRevisions + * IP revisions for the devices discovered in the IOCTRL + */ + +#define NV2080_CTRL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID (0x2dU) + +typedef struct NV2080_CTRL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS { + NvU32 ioctrlIdx; + NvU32 PublicId; + NvU32 localDiscoveredLinks; + NvU32 localGlobalLinkOffset; + NvU32 ioctrlDiscoverySize; + NvU8 numDevices; + NV2080_CTRL_NVLINK_DEVICE_IP_REVISION_VALUES ipRevisions; +} NV2080_CTRL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_IOCTRL_DEVICE_INFO (0x2080302dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_PROGRAM_LINK_SPEED + * + * Program NVLink Speed from OS/VBIOS + * + * [In] bPlatformLinerateDefined + * Whether line rate is defined in the platform + * [In] platformLineRate + * Platform defined line rate + * [Out] nvlinkLinkSpeed + * The line rate that was programmed for the links + */ +#define NV2080_CTRL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID (0x2eU) + +typedef struct NV2080_CTRL_NVLINK_PROGRAM_LINK_SPEED_PARAMS { + NvBool bPlatformLinerateDefined; + NvU32 platformLineRate; + NvU32 nvlinkLinkSpeed; +} NV2080_CTRL_NVLINK_PROGRAM_LINK_SPEED_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_PROGRAM_LINK_SPEED (0x2080302eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_ARE_LINKS_TRAINED + * + * [In] linkMask + * Mask of links whose state will be checked + * [In] bActiveOnly + * The input boolean to check for Link Active state + * [Out] bIsLinkActive + * Boolean array to track if the link is trained + */ +#define NV2080_CTRL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID (0x2fU) + +typedef struct NV2080_CTRL_NVLINK_ARE_LINKS_TRAINED_PARAMS { + NvU32 linkMask; + NvBool bActiveOnly; + NvBool bIsLinkActive[NV2080_CTRL_NVLINK_MAX_LINKS]; +} NV2080_CTRL_NVLINK_ARE_LINKS_TRAINED_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_ARE_LINKS_TRAINED (0x2080302fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_RESET_FLAGS_ASSERT (0x00000000) +#define NV2080_CTRL_NVLINK_RESET_FLAGS_DEASSERT (0x00000001) +#define NV2080_CTRL_NVLINK_RESET_FLAGS_TOGGLE (0x00000002) + +/* + * NV2080_CTRL_CMD_NVLINK_RESET_LINKS + * + * [In] linkMask + * Mask of links which need to be reset + * [In] flags + * Whether to assert, de-assert or toggle the Nvlink reset + */ + +#define NV2080_CTRL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID (0x30U) + +typedef struct NV2080_CTRL_NVLINK_RESET_LINKS_PARAMS { + NvU32 linkMask; + NvU32 flags; +} NV2080_CTRL_NVLINK_RESET_LINKS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_RESET_LINKS (0x20803030U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_DISABLE_DL_INTERRUPTS + * + * [In] linkMask + * Mask of links for which DL interrrupts need to be disabled + */ +#define NV2080_CTRL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID (0x31U) + +typedef struct NV2080_CTRL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS { + NvU32 linkMask; +} NV2080_CTRL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_DISABLE_DL_INTERRUPTS (0x20803031U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID" */ + +/* + * Structure to store the GET_LINK_AND_CLOCK__INFO params + * + * [Out] bLinkConnectedToSystem + * Boolean indicating sysmem connection of a link + * [Out] bLinkConnectedToPeer + * Boolean indicating peer connection of a link + * [Out] bLinkReset + * Whether the link is in reset + * [Out] subLinkWidth + * Number of lanes per sublink + * [Out] linkState + * Mode of the link + * [Out] txSublinkState + * Tx sublink state + * [Out] rxSublinkState + * Rx sublink state + * [Out] bLaneReversal + * Boolean indicating if a link's lanes are reversed + * [Out] nvlinkLinkClockKHz + * Link clock value in KHz + * [Out] nvlinkLineRateMbps + * Link line rate in Mbps + * [Out] nvlinkLinkClockMhz + * Link clock in MHz + * [Out] nvlinkLinkDataRateKiBps + * Link Data rate in KiBps + * [Out] nvlinkRefClkType + * Current Nvlink refclk source + * [Out] nvlinkReqLinkClockMhz + * Requested link clock value + */ +typedef struct NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES { + NvBool bLinkConnectedToSystem; + NvBool bLinkConnectedToPeer; + NvBool bLinkReset; + NvU8 subLinkWidth; + NvU32 linkState; + NvU32 txSublinkState; + NvU32 rxSublinkState; + NvBool bLaneReversal; + NvU32 nvlinkLinkClockKHz; + NvU32 nvlinkLineRateMbps; + NvU32 nvlinkLinkClockMhz; + NvU32 nvlinkLinkDataRateKiBps; + NvU8 nvlinkRefClkType; + NvU32 nvlinkReqLinkClockMhz; +} NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_LINK_AND_CLOCK_INFO + * + * [In] linkMask + * Mask of enabled links to loop over + * [Out] nvlinkRefClkSpeedKHz + * Ref clock value n KHz + * [Out] linkInfo + * Per link information + */ +#define NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID (0x32U) + +typedef struct NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS { + NvU32 linkMask; + NvU32 nvlinkRefClkSpeedKHz; + NvBool bSublinkStateInst; // whether instantaneous sublink state is needed + NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES linkInfo[NV2080_CTRL_NVLINK_MAX_LINKS]; +} NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_LINK_AND_CLOCK_INFO (0x20803032U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_SETUP_NVLINK_SYSMEM + * + * Updates the HSHUB sysmem config resgister state to reflect sysmem NVLinks + * + * [In] sysmemLinkMask + * Mask of discovered sysmem NVLinks + */ +#define NV2080_CTRL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID (0x33U) + +typedef struct NV2080_CTRL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS { + NvU32 sysmemLinkMask; +} NV2080_CTRL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS; +#define NV2080_CTRL_CMD_NVLINK_SETUP_NVLINK_SYSMEM (0x20803033U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_PROCESS_FORCED_CONFIGS + * + * Process NVLink forced configurations which includes setting of HSHUB and memory system + * + * [In] bLegacyForcedConfig + * Tracks whether the forced config is legacy forced config or chiplib config + * [Out] bOverrideComputePeerMode + * Whether compute peer mode was enabled + * [In] phase + * Only applicable when bLegacyForcedConfig is true + * Tracks the set of registers to program from the NVLink table + * [In] linkConnection + * Array of chiplib configurations + */ +#define NV2080_CTRL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID (0x34U) + +typedef struct NV2080_CTRL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS { + NvBool bLegacyForcedConfig; + NvBool bOverrideComputePeerMode; + NvU32 phase; + NvU32 linkConnection[NV2080_CTRL_NVLINK_MAX_LINKS]; +} NV2080_CTRL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_PROCESS_FORCED_CONFIGS (0x20803034U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS + * + * Sync the NVLink lane shutdown properties with GSP-RM + * + * [In] bLaneShutdownEnabled + * Whether nvlink shutdown is enabled for the chip + * [In] bLaneShutdownOnUnload + * Whether nvlink shutdown should be triggered on driver unload + */ +#define NV2080_CTRL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID (0x35U) + +typedef struct NV2080_CTRL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS { + NvBool bLaneShutdownEnabled; + NvBool bLaneShutdownOnUnload; +} NV2080_CTRL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS (0x20803035U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_ENABLE_SYSMEM_NVLINK_ATS + * + * Enable ATS functionality related to NVLink sysmem if hardware support is available + * + * [In] notUsed + */ +#define NV2080_CTRL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID (0x36U) + +typedef struct NV2080_CTRL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS { + NvU32 notUsed; +} NV2080_CTRL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_ENABLE_SYSMEM_NVLINK_ATS (0x20803036U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK + * + * Get the mask of Nvlink links connected to system + * + * [Out] sysmemLinkMask + * Mask of Nvlink links connected to system + */ +#define NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID (0x37U) + +typedef struct NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS { + NvU32 sysmemLinkMask; +} NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK (0x20803037U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_GET_SET_NVSWITCH_FLA_ADDR + * + * Get/Set NVSwitch FLA address + * + * [In] bGet + * Whether to get or set the NVSwitch FLA address + * [In/Out] addr + * Address that is to be set or retrieved. + */ +#define NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS_MESSAGE_ID (0x38U) + +typedef struct NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS { + NvBool bGet; + NV_DECLARE_ALIGNED(NvU64 addr, 8); +} NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_SET_NVSWITCH_FLA_ADDR (0x20803038) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO + * + * Syncs the different link masks and vbios defined values between CPU-RM and GSP-RM + * + * [in] discoveredLinks + * Mask of links discovered from IOCTRLs + * + * [in] connectedLinksMask + * Mask of links which are connected (remote present) + * + * [in] bridgeSensableLinks + * Mask of links whose remote endpoint presence can be sensed + * + * [in] bridgedLinks + * Mask of links which are connected (remote present) + * Same as connectedLinksMask, but also tracks the case where link + * is connected but marginal and could not initialize + * + * [out] initDisabledLinksMask + * Mask of links for which initialization is disabled + * + * [out] vbiosDisabledLinkMask + * Mask of links disabled in the VBIOS + * + * [out] initializedLinks + * Mask of initialized links + * + * [out] bEnableTrainingAtLoad + * Whether the links should be trained to active during driver load + * + * [out] bEnableSafeModeAtLoad + * Whether the links should be initialized to swcfg during driver load + */ + +#define NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS_MESSAGE_ID (0x39U) + +typedef struct NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS { + NvU32 discoveredLinks; + NvU32 connectedLinksMask; + NvU32 bridgeSensableLinks; + NvU32 bridgedLinks; + NvU32 initDisabledLinksMask; + NvU32 vbiosDisabledLinkMask; + NvU32 initializedLinks; + NvBool bEnableTrainingAtLoad; + NvBool bEnableSafeModeAtLoad; +} NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO (0x20803039U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS + * + * Enable pre-topology setup on the mask of enabled links + * This command accepts no parameters. + */ + +#define NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS (0x2080303aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | 0x3a" */ + +/* + * NV2080_CTRL_CMD_NVLINK_PROCESS_INIT_DISABLED_LINKS + * + * Process the init disabled NVLinks and filter those out + * + * [in/out] initDisabledLinksMask + * Mask of links initdisabled on a given GPU + * + * [in] bSkipHwNvlinkDisable + * Whether to consider skipping the HW initdisable links + */ + +#define NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS_MESSAGE_ID (0x3bU) + +typedef struct NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS { + NvU32 initDisabledLinksMask; + NvBool bSkipHwNvlinkDisable; +} NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_PROCESS_INIT_DISABLED_LINKS (0x2080303bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_EOM_CONTROL + * + * cmd [IN] enum identifying the EOM related command for the driver to process + * link [IN] linkId + * params [IN] NvU32 word that is written into NV_PMINION_SCRATCH_SWRW_0 before calling CONFIGEOM dlcmd + * + * Params Packing is specified in Minion IAS + */ + +typedef enum NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND { + NVLINK_EOM_CONTROL_START_EOM = 0, + NVLINK_EOM_CONTROL_END_EOM = 1, + NVLINK_EOM_CONTROL_CONFIG_EOM = 2, + NVLINK_EOM_CONTROL_FULL_EOM_SEQUENCE = 3, +} NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND; + +#define NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID (0x3cU) + +typedef struct NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS { + NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND cmd; + NvU32 linkId; + NvU32 params; +} NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_EOM_CONTROL (0x2080303c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID" */ + +/*! + * Inband Recieved Data + */ +#define NV2080_CTRL_NVLINK_INBAND_MAX_MSG_SIZE 4096 +#define NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_MESSAGE_ID (0x3dU) + +typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS { + NvU8 data[NV2080_CTRL_NVLINK_INBAND_MAX_MSG_SIZE]; + NvU32 dataSize; +} NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS; + +#define NV2080_CTRL_NVLINK_L1_THRESHOLD_SET (0x00000000U) +#define NV2080_CTRL_NVLINK_L1_THRESHOLD_GET (0x00000001U) + +/* + * NV2080_CTRL_CMD_NVLINK_L1_THRESHOLD + * + * This command is used to get/set the L1 threshold value + * + * [in] flag + * Whether to set or get the L1 threshold value + * + * [in/out] l1Threshold + * Used to set or get the L1 threshold value + * + */ +#define NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS_MESSAGE_ID (0x3eU) + +typedef struct NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS { + NvU32 flag; + NvU32 l1Threshold; +} NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_L1_THRESHOLD (0x2080303eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_INBAND_SEND_DATA + * + * RPC for sending Inband data + * + * [In] data[] + * data to be sent over inband + * [In] dataSize + * Size of valid data in data array + */ +#define NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID (0x3fU) + +typedef struct NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS { + NvU8 buffer[NV2080_CTRL_NVLINK_INBAND_MAX_MSG_SIZE]; + NvU32 dataSize; +} NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_INBAND_SEND_DATA (0x2080303fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_IS_GPU_DEGRADED + * + * RPC for Getting GPU degraded status upon link error + * + * [In] linkId + * Id of the link on which error occured + * [In] bIsGpuDegraded + * Boolean to track corresponding GPU is degraded or not + */ +#define NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID (0x40U) + +typedef struct NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS { + NvU32 linkId; + NvBool bIsGpuDegraded; +} NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_IS_GPU_DEGRADED (0x20803040U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_DIRECT_CONNECT_CHECK + * + * This command is used to check for missing + * bridge/nvlink for direct connect GPU + * + * [out] bIsEnoughNvLink + * Check if number of active nvlink meet the minimum requirements. + * [out] numBridge + * Number of NVLink bridge + * [out] bridgePresenceMask + * Bit mask of NVLink bridges's presence + */ +#define NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS_MESSAGE_ID (0x41U) + +typedef struct NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS { + NvBool bIsEnoughNvLink; + NvU32 numBridge; + NvU32 bridgePresenceMask; +} NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_DIRECT_CONNECT_CHECK (0x20803041U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS_MESSAGE_ID" */ + + +/* _ctrl2080nvlink_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h new file mode 100644 index 0000000..b12521d --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h @@ -0,0 +1,578 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080perf.finn +// + +#include "nvfixedtypes.h" +#include "ctrl/ctrl2080/ctrl2080base.h" + +#define NV_SUBPROC_NAME_MAX_LENGTH 100 + +#include "nvmisc.h" + +#include "ctrl/ctrl2080/ctrl2080clk.h" +#include "ctrl/ctrl2080/ctrl2080gpumon.h" +#include "ctrl/ctrl2080/ctrl2080volt.h" +#include "ctrl/ctrl2080/ctrl2080vfe.h" +#include "ctrl/ctrl2080/ctrl2080pmumon.h" +#include "ctrl/ctrl0080/ctrl0080perf.h" +// +// XAPICHK/XAPI_TEST chokes on the "static NVINLINE" defines in nvmisc.h. +// However, we don't need any of those definitions for those tests (XAPICHK is a +// syntactical check, not a functional test). So, instead, just #define out the +// macros referenced below. +// + +/* + * NV2080_CTRL_CMD_PERF_BOOST + * + * This command can be used to boost P-State up one level or to the highest for a limited + * duration for the associated subdevice. Boosts from different clients are being tracked + * independently. Note that there are other factors that can limit P-States so the resulting + * P-State may differ from expectation. + * + * flags + * This parameter specifies the actual command. _CLEAR is to clear existing boost. + * _BOOST_1LEVEL is to boost P-State one level higher. _BOOST_TO_MAX is to boost + * to the highest P-State. + * duration + * This parameter specifies the duration of the boost in seconds. This has to be less + * than NV2080_CTRL_PERF_BOOST_DURATION_MAX. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD 1:0 +#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_CLEAR (0x00000000) +#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_1LEVEL (0x00000001) +#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_TO_MAX (0x00000002) + +#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA 4:4 +#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_NO (0x00000000) +#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_YES (0x00000001) + +#define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC 5:5 +#define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_NO (0x00000000) +#define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_YES (0x00000001) + +#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY 6:6 +#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_DEFAULT (0x00000000) +#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_HIGH (0x00000001) + +#define NV2080_CTRL_PERF_BOOST_DURATION_MAX 3600 //The duration can be specified up to 1 hour +#define NV2080_CTRL_PERF_BOOST_DURATION_INFINITE 0xffffffff // If set this way, the boost will last until cleared. + +#define NV2080_CTRL_CMD_PERF_BOOST (0x2080200a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_BOOST_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_BOOST_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV2080_CTRL_PERF_BOOST_PARAMS { + NvU32 flags; + NvU32 duration; +} NV2080_CTRL_PERF_BOOST_PARAMS; + +/* + * NV2080_CTRL_CMD_PERF_RESERVE_PERFMON_HW + * + * This command reserves HW Performance Monitoring capabilities for exclusive + * use by the requester. If the HW Performance Monitoring capabilities are + * currently in use then NVOS_STATUS_ERROR_STATE_IN_USE is returned. + * + * bAcquire + * When set to TRUE this parameter indicates that the client wants to + * acquire the Performance Monitoring capabilities on the subdevice. + * When set to FALSE this parameter releases the Performance Monitoring + * capabilities on the subdevice. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_ERROR_STATE_IN_USE + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_PERF_RESERVE_PERFMON_HW (0x20802093) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS_MESSAGE_ID (0x93U) + +typedef struct NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS { + NvBool bAcquire; +} NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS; + +/* + * NV2080_CTRL_PERF_POWERSTATE + * + * This structure describes power state information. + * + * powerState + * This parameter specifies the type of power source. + * Legal values for this parameter include: + * NV2080_CTRL_PERF_POWER_SOURCE_AC + * This values indicates that the power state is AC. + * NV2080_CTRL_PERF_POWER_SOURCE_BATTERY + * This values indicates that the power state is battery. + */ +#define NV2080_CTRL_PERF_POWER_SOURCE_AC (0x00000000) +#define NV2080_CTRL_PERF_POWER_SOURCE_BATTERY (0x00000001) + +typedef struct NV2080_CTRL_PERF_POWERSTATE_PARAMS { + NvU32 powerState; +} NV2080_CTRL_PERF_POWERSTATE_PARAMS; + +/* + * NV2080_CTRL_CMD_PERF_SET_POWERSTATE + * + * This command can be used to set the perf power state as AC or battery. + * + * powerStateInfo + * This parameter specifies the power source type to set. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_PERF_SET_POWERSTATE (0x2080205b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS_MESSAGE_ID (0x5BU) + +typedef struct NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS { + NV2080_CTRL_PERF_POWERSTATE_PARAMS powerStateInfo; +} NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS; + +/* + * NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE + * + * This command allows the forcing of a performance level based on auxiliary + * power-states. + * + * powerState + * This parameter specifies the target auxiliary Power state. Legal aux + * power-states for this parameter are defined by the + * NV2080_CTRL_PERF_AUX_POWER_STATE_P* definitions that follow. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE (0x20802092) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS_MESSAGE_ID (0x92U) + +typedef struct NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS { + NvU32 powerState; +} NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS; + +#define NV2080_CTRL_PERF_AUX_POWER_STATE_P0 (0x00000000) +#define NV2080_CTRL_PERF_AUX_POWER_STATE_P1 (0x00000001) +#define NV2080_CTRL_PERF_AUX_POWER_STATE_P2 (0x00000002) +#define NV2080_CTRL_PERF_AUX_POWER_STATE_P3 (0x00000003) +#define NV2080_CTRL_PERF_AUX_POWER_STATE_P4 (0x00000004) +#define NV2080_CTRL_PERF_AUX_POWER_STATE_COUNT (0x00000005) + +/*! + * Enumeration of the RATED_TDP arbitration clients which make requests to force + * enable/disable VF points above the RATED_TDP point. + * + * These clients are sorted in descending priority - the RM will arbitrate + * between all clients in order of priority, taking as output the first client + * whose input action != @ref NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT. + */ +typedef enum NV2080_CTRL_PERF_RATED_TDP_CLIENT { + /*! + * Internal RM client corresponding to the RM's internal state and features. + * The RM client will either allow default behavior (@ref + * NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT) or will limit to RATED_TDP + * (@ref NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT) when no power + * controllers are active. + */ + NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM = 0, + /*! + * This Client is specifically for Bug 1785342 where we need to limit the TDP + * to Min value on boot. And clear the Max TDP limit. + */ + NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342 = 1, + /*! + * Global client request. This client is expected to be used by a global + * switch functionality in an end-user tool, such as EVGA Precision, to + * either force enabling boost above RATED_TDP (@ref + * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED) or to force limiting to + * RATED_TDP (@ref NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT) across the + * board, regardless of any app-profie settings. + */ + NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL = 2, + /*! + * Operating system request. This client is expected to be used by the + * operating system to set @ref NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK + * for performance profiling. + */ + NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS = 3, + /*! + * App profile client requests. This client is expected to be used by the + * app-profile settings to either default to whatever was requested by + * higher-priority clients (@ref NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT) + * or to limit to RATED_TDP (@ref + * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT) for apps which have shown + * bad behavior when boosting. + */ + NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE = 4, + /*! + * Number of supported clients. + * + * @Note MUST ALWAYS BE LAST! + */ + NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS = 5, +} NV2080_CTRL_PERF_RATED_TDP_CLIENT; + +/*! + * Enumeration RATED_TDP actions - these are the requested actions clients can + * make to change the behavior of the RATED_TDP functionality. + */ +typedef enum NV2080_CTRL_PERF_RATED_TDP_ACTION { + /*! + * The default action - meaning no explicit request from the client other + * than to take the default behavior (allowing boosting above RATED_TDP) or + * any explicit actions from lower priority clients. + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT = 0, + /*! + * Force allow boosting above RATED_TDP - this action explicitly requests + * boosting above RATED_TDP, preventing lower priority clients to limit to + * RATED_TDP. + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED = 1, + /*! + * Force to limit above RATED_TDP - this action explicitly requests to limit + * to RATED_TDP. This is the opposite of the default behavior to allow + * boosting above RATED_TDP. Clients specify this action when they + * explicitly need boost to be disabled (e.g. eliminating perf variation, + * special apps which exhibit bad behavior, etc.). + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT = 2, + /*! + * Lock to RATED_TDP - this action requests the clocks to be fixed at the + * RATED_TDP. Used for achieving stable clocks required for profiling. + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK = 3, + /*! + * Lock to Min TDP - This requests min to be fixed at RATED_TDP but allow + * boosting for max + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR = 4, +} NV2080_CTRL_PERF_RATED_TDP_ACTION; + +/*! + * Structure describing dynamic state of the RATED_TDP feature. + */ +#define NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_MESSAGE_ID (0x6DU) + +typedef struct NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS { + /*! + * Structure of internal RM state - these values are used to determine the + * behavior of NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM per the RM's @ref + * perfPwrRatedTdpLimitRegisterClientActive() interface. + */ + struct { + /*! + * [out] - Mask of active client controllers (@ref + * PERF_PWR_RATED_TDP_CLIENT) which are currently regulating TDP. When + * this mask is zero, NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM will request + * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT. + */ + NvU32 clientActiveMask; + /*! + * [out] - Boolean indicating that user has requested locking to + * RATED_TDP vPstate via corresponding regkey + * NV_REG_STR_RM_PERF_RATED_TDP_LIMIT. When the boolean value is true, + * NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM will request + * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT. + */ + NvU8 bRegkeyLimitRatedTdp; + } rm; + + /*! + * [out] - Arbitrated output action of all client requests (@ref inputs). + * This is the current state of the RATED_TDP feature. Will only be @ref + * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED or @ref + * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT. + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION output; + /*! + * [out] - Array of input client request actions, indexed via @ref + * NV2080_CTRL_PERF_RATED_TDP_CLIENT_. RM will arbitrate between these + * requests, choosing the highest priority request != @ref + * NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT or fallback to choosing @ref + * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED. + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION inputs[NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS]; +} NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS; + +/*! + * NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL + * + * This command retrieves the current requested RATED_TDP action corresponding + * to the specified client. + * + * See @ref NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS for documentation of + * parameters. + * + * Possible status values returned are + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL (0x2080206e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | 0x6E" */ + +/*! + * NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL + * + * This command sets the requested RATED_TDP action corresponding to the + * specified client. @Note, however, that this command is unable to set @ref + * NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM. + * + * See @ref NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS for documentation of + * parameters. + * + * Possible status values returned are + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL (0x2080206f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | 0x6F" */ + +/*! + * Structure containing the requested action for a RATED_TDP client (@ref + * NV2080_CTRL_PERF_RATED_TDP_CLIENT). + */ +typedef struct NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS { + /*! + * [in] - Specified client for request. + */ + NV2080_CTRL_PERF_RATED_TDP_CLIENT client; + /*! + * [in/out] - Client's requested action. + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION input; +} NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS; + +/*! + * This struct represents the GPU monitoring perfmon sample for an engine. + */ +typedef struct NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE { + /*! + * Percentage during the sample that the engine remains busy. This + * is in units of pct*100. + */ + NvU32 util; + /*! + * Scaling factor to convert utilization from full GPU to per vGPU. + */ + NvU32 vgpuScale; + /*! + * Process ID of the process that was active on the engine when the + * sample was taken. If no process is active then NV2080_GPUMON_PID_INVALID + * will be returned. + */ + NvU32 procId; + /*! + * Process ID of the process in the vGPU VM that was active on the engine when + * the sample was taken. If no process is active then NV2080_GPUMON_PID_INVALID + * will be returned. + */ + NvU32 subProcessID; + /*! + * Process name of the process in the vGPU VM that was active on the engine when + * the sample was taken. If no process is active then NULL will be returned. + */ + char subProcessName[NV_SUBPROC_NAME_MAX_LENGTH]; +} NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE; + +/*! + * This struct represents the GPU monitoring perfmon sample. + */ +typedef struct NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE { + /*! + * Base GPU monitoring sample. + */ + NV_DECLARE_ALIGNED(NV2080_CTRL_GPUMON_SAMPLE base, 8); + /*! + * FB bandwidth utilization sample. + */ + NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE fb; + /*! + * GR utilization sample. + */ + NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE gr; + /*! + * NV ENCODER utilization sample. + */ + NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvenc; + /*! + * NV DECODER utilization sample. + */ + NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvdec; +} NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE; + +/*! + * This struct represents the GPU monitoring samples of perfmon values that + * client wants the access to. + */ +#define NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM_MESSAGE_ID (0x83U) + +typedef NV2080_CTRL_GPUMON_SAMPLES NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM; + +/*! + * Number of GPU monitoring sample in their respective buffers. + */ +#define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL 72 + +#define NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_BUFFER_SIZE \ + NV_SIZEOF32(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE) * \ + NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL + +/*! + * NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2 + * + * This command returns perfmon gpu monitoring utilization samples. + * This command is not supported with SMC enabled. + * + * See NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM_V2 for documentation + * on the parameters. + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + * Note this is the same as NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES + * but without the embedded pointer. + * + */ +#define NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2 (0x20802096) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_MESSAGE_ID" */ + +/*! + * This structure represents the GPU monitoring samples of utilization values that + * the client wants access to. + */ +#define NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_MESSAGE_ID (0x96U) + +typedef struct NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS { + /*! + * Type of the sample, see NV2080_CTRL_GPUMON_SAMPLE_TYPE_* for reference. + */ + NvU8 type; + /*! + * Size of the buffer, this should be + * bufSize == NV2080_CTRL_*_GPUMON_SAMPLE_COUNT_* + * sizeof(derived type of NV2080_CTRL_GPUMON_SAMPLE). + */ + NvU32 bufSize; + /*! + * Number of samples in ring buffer. + */ + NvU32 count; + /*! + * tracks the offset of the tail in the circular queue array pSamples. + */ + NvU32 tracker; + /*! + * A circular queue with size == bufSize. + * + * @note This circular queue wraps around after 10 seconds of sampling, + * and it is clients' responsibility to query within this time frame in + * order to avoid losing samples. + * @note With one exception, this queue contains last 10 seconds of samples + * with tracker poiniting to oldest entry and entry before tracker as the + * newest entry. Exception is when queue is not full (i.e. tracker is + * pointing to a zeroed out entry), in that case valid entries are between 0 + * and tracker. + * @note Clients can store tracker from previous query in order to provide + * samples since last read. + */ + NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE samples[NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL], 8); +} NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS; + +/* + * NV2080_CTRL_CMD_PERF_GPU_IS_IDLE + * + * This command notifies RM to make p state switching aggressive by setting + * required limiting factors to speed up GC6 Entry initiation. + * + * prevPstate [out] + * This parameter will contain the pstate before the switch was initiated + * + * Possible status return values are: + * NV_OK : If P State Switch is successful + * NV_INVALID_STATE : If unable to access P State structure + * NVOS_STATUS_ERROR : If P State Switch is unsuccessful + */ +#define NV2080_CTRL_CMD_PERF_GPU_IS_IDLE (0x20802089) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS_MESSAGE_ID (0x89U) + +typedef struct NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS { + NvU32 prevPstate; + NvU32 action; +} NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS; + +#define NV2080_CTRL_PERF_GPU_IS_IDLE_TRUE (0x00000001) +#define NV2080_CTRL_PERF_GPU_IS_IDLE_FALSE (0x00000002) + +/* + * NV2080_CTRL_CMD_PERF_AGGRESSIVE_PSTATE_NOTIFY + * + * This command is for the KMD Aggressive P-state feature. + * + * bGpuIsIdle [in] + * When true, applies cap to lowest P-state/GPCCLK. When false, releases cap. + * idleTimeUs [in] + * The amount of time (in microseconds) the GPU was idle since previous + * call, part of the GPU utilization data from KMD. + * busyTimeUs [in] + * The amount of time (in microseconds) the GPU was not idle since + * previous call, part of the GPU utilization data from KMD. + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + + +#define NV2080_CTRL_CMD_PERF_AGGRESSIVE_PSTATE_NOTIFY (0x2080208f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS_MESSAGE_ID (0x8FU) + +typedef struct NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS { + NvBool bGpuIsIdle; + NvBool bRestoreToMax; + NV_DECLARE_ALIGNED(NvU64 idleTimeUs, 8); + NV_DECLARE_ALIGNED(NvU64 busyTimeUs, 8); +} NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS; + + +/* _ctrl2080perf_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h new file mode 100644 index 0000000..8eb6c01 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080perf_cf.finn +// + + +/* _ctrl2080perf_cf_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h new file mode 100644 index 0000000..0a3e6b2 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.finn +// + + + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h new file mode 100644 index 0000000..fa476b5 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h @@ -0,0 +1,67 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080pmgr.finn +// + + + +#define NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED 0U +#define NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED 1U +#define NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_APPLICABLE 2U + +/*! + * NV2080_CTRL_PMGR_MODULE_INFO_PARAMS + * + * This provides information about different module properties + * + * moduleId[OUT] + * - This is a static HW identifier that is unique for each module on a given baseboard. + * For non-baseboard products this would always be 0. + * nvswitchSupport[OUT] + * - NVSwitch present or not. Possible values are + * NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED + * NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED + * NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_APPLICABLE + */ +#define NV2080_CTRL_PMGR_MODULE_INFO_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_PMGR_MODULE_INFO_PARAMS { + NvU32 moduleId; + NvU8 nvswitchSupport; +} NV2080_CTRL_PMGR_MODULE_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_PMGR_GET_MODULE_INFO + * + * Control call to query the subdevice module INFO. + * + */ +#define NV2080_CTRL_CMD_PMGR_GET_MODULE_INFO (0x20802609) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PMGR_INTERFACE_ID << 8) | NV2080_CTRL_PMGR_MODULE_INFO_PARAMS_MESSAGE_ID" */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080pmumon.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080pmumon.h new file mode 100644 index 0000000..53cb620 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080pmumon.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080pmumon.finn +// + + + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080power.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080power.h new file mode 100644 index 0000000..2d01ed5 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080power.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080power.finn +// + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h new file mode 100644 index 0000000..e2471c3 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h @@ -0,0 +1,368 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080rc.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* + * NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM + * + * This command returns data read from the specified virtual memory address for + * the associated subdevice. + * + * hChannel + * This parameter specifies the channel object handle from which the virtual + * memory range applies. + * virtAddress + * This parameter specifies the GPU base virtual memory address from which data should + * be read. The amount of data read is specified by the bufferSize parameter. + * bufferPtr + * This parameter specifies the buffer address in the caller's address space into which + * the data is to be returned. The address must be aligned on an 8-byte boundary. + * The buffer must be at least as big as the value specified bufferSize parameter (in bytes). + * bufferSize + * This parameter specifies the size of the buffer referenced by the bufferPtr parameter. + * This parameter also indicates the total number of bytes to be returned. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_XLATE + */ +#define NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS { + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 virtAddress, 8); + NV_DECLARE_ALIGNED(NvP64 bufferPtr, 8); + NvU32 bufferSize; +} NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS; + +#define NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM (0x20802204) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_RC_GET_ERROR_COUNT + * + * This command returns the number of RC errors. + * + * errorCount + * Number of RC errors. + * + * Note: If SMC is enabled, mig/monitor capability must be acquired to query + * aggregate information. Otherwise, the control call returns + * NV_ERR_INSUFFICIENT_PERMISSIONS. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INSUFFICIENT_PERMISSIONS. + */ +#define NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS { + NvU32 errorCount; +} NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS; + +#define NV2080_CTRL_CMD_RC_GET_ERROR_COUNT (0x20802205) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_RC_ERROR_PARAMS_BUFFER_SIZE (0x2000) /* finn: Evaluated from "(8 * 1024)" */ + +#define NV2080_CTRL_CMD_RC_GET_ERROR (0x20802206) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x6" */ + +/* + * NV2080_CTRL_CMD_RC_GET_ERROR_V2 + * + * This command returns an error element in the RC error list. + * + * whichBuffer + * Which Error to return (0 is oldest) + * outputRecordSize + * Output Size of Buffer -- Zero if error record doesn't exist + * recordBuffer + * buffer + * + * Note: If SMC is enabled, mig/monitor capability must be acquired to query + * aggregate information. Otherwise, the control call returns + * NV_ERR_INSUFFICIENT_PERMISSIONS. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INSUFFICIENT_PERMISSIONS. + * + */ + +#define NV2080_CTRL_RC_GET_ERROR_V2_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV2080_CTRL_RC_GET_ERROR_V2_PARAMS { + + NvU32 whichBuffer; // [IN] - which error to return (0 is oldest) + NvU32 outputRecordSize; // [OUT] + NvU8 recordBuffer[NV2080_CTRL_RC_ERROR_PARAMS_BUFFER_SIZE]; +} NV2080_CTRL_RC_GET_ERROR_V2_PARAMS; + +#define NV2080_CTRL_CMD_RC_GET_ERROR_V2 (0x20802213) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_GET_ERROR_V2_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_RC_SET_CLEAN_ERROR_HISTORY + * + * This command cleans error history. + * + * This command has no input parameters. + * + * Possible status values returned are: + * NV_OK + */ + +#define NV2080_CTRL_CMD_RC_SET_CLEAN_ERROR_HISTORY (0x20802207) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x7" */ + +/* + * NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO + * + * This command returns information about the RC watchdog. + * + * watchdogStatusFlags + * This output parameter is a combination of one or more of the following: + * + * NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_NONE + * This is the value of watchdogStatusFlags if no flags are set. + * + * NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_DISABLED + * This means that the watchdog is disabled. + * + * NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_RUNNING + * This means that the watchdog is running. + * + * NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_INITIALIZED + * This means that the watchdog has been initialized. + * + * A typical result would be either "running and initialized", or + * "disabled". However, "initialized, but not running, and not disabled" + * is also quite reasonable (if the computer is hibernating, for example). + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS { + NvU32 watchdogStatusFlags; +} NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS; + +#define NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO (0x20802209) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS_MESSAGE_ID" */ + +/* valid values for watchdogStatusFlags */ +#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_NONE (0x00000000) +#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_DISABLED (0x00000001) +#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_RUNNING (0x00000002) +#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_INITIALIZED (0x00000004) + +/* + * NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG + * + * This command disables the RC watchdog, if possible. + * If, however, another RM client has already explicitly (via NV2080 call) enabled + * the RC watchdog, then this method returns NV_ERR_STATE_IN_USE. + * + * This command, if successful, will prevent other clients from enabling the + * watchdog until the calling RM client releases its request with + * NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS or frees its NV20_SUBDEVICE. + * + * See NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG for disabling the watchdog + * without preventing other clients from enabling it. + * + * Possible status return values are: + * NV_OK + * NV_ERR_STATE_IN_USE + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG (0x2080220a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xA" */ + +/* + * NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG + * + * This command enables the RC watchdog, if possible. + * If, however, another RM client has already explicitly (via NV2080 call) disabled + * the RC watchdog, then this method returns NV_ERR_STATE_IN_USE. + * + * Possible status return values are: + * NV_OK + * NV_ERR_STATE_IN_USE + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG (0x2080220b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xB" */ + +/* + * NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS + * + * This command releases all of the RM client's outstanding requests to enable + * or disable the watchdog. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS (0x2080220c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xC" */ + +/* + * NV2080_CTRL_CMD_SET_RC_RECOVERY/NV2080_CTRL_CMD_GET_RC_RECOVERY + * + * This command disables/enables RC recovery. + * + * rcEnable + * NV2080_CTRL_CMD_SET_RC_RECOVERY_DISABLED + * Disable robust channel recovery. + * + * NV2080_CTRL_CMD_SET_RC_RECOVERY_ENABLED + * Enable robust channel recovery with default breakpoint handling. + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +typedef struct NV2080_CTRL_CMD_RC_RECOVERY_PARAMS { + NvU32 rcEnable; +} NV2080_CTRL_CMD_RC_RECOVERY_PARAMS; + +#define NV2080_CTRL_CMD_SET_RC_RECOVERY (0x2080220d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xD" */ + +#define NV2080_CTRL_CMD_GET_RC_RECOVERY (0x2080220e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xE" */ + +/* valid values for rcEnable */ +#define NV2080_CTRL_CMD_RC_RECOVERY_DISABLED (0x00000000) +#define NV2080_CTRL_CMD_RC_RECOVERY_ENABLED (0x00000001) + +/* + * NV2080_CTRL_CMD_TDR_SET_TIMEOUT_STATE + * + * This command can be used to set TDR timeout state. + * + * It can be used to indicate that a timeout has occurred and that a GPU + * reset will start. It can also be used to indicate that the reset has + * completed along with the corresponding complition status. + * + * cmd + * This parameter is used to indicate the stage of the TDR recovery + * process. Legal values for this parameter are: + * NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_BEGIN + * This value indicates that TDR recovery is about to begin. + * NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END + * This value indicates that TDR recovery has completed. + * + * status + * This parameter is valid when the cmd parameter is set to + * NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END. It is used + * to specify the completion status of the TDR recovery. Legal + * values for this parameter include: + * NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_FAIL + * This value indicates the recovery failed. + * NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_SUCCESS + * This value indicates the recovery succeeded. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_COMMAND + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_TDR_SET_TIMEOUT_STATE (0x2080220f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS { + NvU32 cmd; + NvS32 status; +} NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS; + +/* valid cmd values */ +#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_BEGIN (0x00000000) +#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END (0x00000001) + +/* valid status values */ +#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_SUCCESS (0x00000000) +#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_FAIL (0x00000001) + +/* + * NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG + * + * This command disables the RC watchdog, similarly to how + * NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG does. However, unlike that command, this + * command will not prevent another RM client from explicitly enabling the RC + * watchdog with NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG. + * + * Possible status return values are: + * NV_OK + * NV_ERR_STATE_IN_USE + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG (0x20802210) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x10" */ + +/* + * NV2080_CTRL_CMD_GET_RC_INFO/NV2080_CTRL_CMD_SET_RC_INFO + * + * This command can be used to set robust channel parameters. + * + * rcMode + * NV2080_CTRL_CMD_SET_RC_INFO_MODE_DISABLE + * Disable robust channel operation. + * + * NV2080_CTRL_CMD_SET_RC_INFO_MODE_ENABLE + * Enable robust channel operation. + * + * rcBreak + * NV2080_CTRL_CMD_SET_RC_INFO_BREAK_DISABLE + * Disable breakpoint handling during robust channel operation. + * + * NV2080_CTRL_CMD_SET_RC_INFO_BREAK_ENABLE + * Enable breakpoint handling during robust channel operation. + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +typedef struct NV2080_CTRL_CMD_RC_INFO_PARAMS { + NvU32 rcMode; + NvU32 rcBreak; +} NV2080_CTRL_CMD_RC_INFO_PARAMS; + +#define NV2080_CTRL_CMD_SET_RC_INFO (0x20802211) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x11" */ + +#define NV2080_CTRL_CMD_GET_RC_INFO (0x20802212) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x12" */ + +/* valid rcMode values */ +#define NV2080_CTRL_CMD_RC_INFO_MODE_DISABLE (0x00000000) +#define NV2080_CTRL_CMD_RC_INFO_MODE_ENABLE (0x00000001) + +/* valid rcBreak values */ +#define NV2080_CTRL_CMD_RC_INFO_BREAK_DISABLE (0x00000000) +#define NV2080_CTRL_CMD_RC_INFO_BREAK_ENABLE (0x00000001) + +/* _ctrl2080rc_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080spi.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080spi.h new file mode 100644 index 0000000..448723c --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080spi.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080spi.finn +// + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080thermal.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080thermal.h new file mode 100644 index 0000000..abe66ef --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080thermal.h @@ -0,0 +1,30 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080thermal.finn +// + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h new file mode 100644 index 0000000..d018e20 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h @@ -0,0 +1,233 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2008-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080tmr.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_TIMER related control commands and parameters */ + +/* + * NV2080_CTRL_CMD_TIMER_SCHEDULE + * + * This command schedules a GPU timer event to fire at the specified time interval. + * Can be called without API & GPU locks if NVOS54_FLAGS_IRQL_RAISED and + * NVOS54_FLAGS_LOCK_BYPASS are set in NVOS54_PARAMETERS.flags + * + * time_nsec + * This parameter specifies the time in nanoseconds at which the GPU timer + * event is to fire. + * flags + * This parameter determines the interpretation of the value specified by + * the time_nsec parameter: + * NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_ABS + * This flag indicates that time_nsec is in absolute time. + * NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_REL + * This flag indicates that time_nsec is in relative time. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_TIMER_SCHEDULE (0x20800401) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 time_nsec, 8); + NvU32 flags; +} NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS; + +/* valid flag values */ +#define NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME 0:0 +#define NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_ABS (0x00000000) +#define NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_REL (0x00000001) + +/* + * NV2080_CTRL_CMD_TIMER_CANCEL + * + * This command cancels any pending timer events initiated with the + * NV2080_CTRL_CMD_TIMER_SCHEDULE command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_TIMER_CANCEL (0x20800402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | 0x2" */ + +/* + * NV2080_CTRL_CMD_TIMER_GET_TIME + * + * This command returns the current GPU timer value. The current time is + * expressed in elapsed nanoseconds since 00:00 GMT, January 1, 1970 + * (zero hour) with a resolution of 32 nanoseconds. + * + * Can be called without API & GPU locks if NVOS54_FLAGS_IRQL_RAISED and + * NVOS54_FLAGS_LOCK_BYPASS are set in NVOS54_PARAMETERS.flags + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_TIMER_GET_TIME (0x20800403) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_TIMER_GET_TIME_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_TIMER_GET_TIME_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_TIMER_GET_TIME_PARAMS { + NV_DECLARE_ALIGNED(NvU64 time_nsec, 8); +} NV2080_CTRL_TIMER_GET_TIME_PARAMS; + +/* + * NV2080_CTRL_CMD_TIMER_GET_REGISTER_OFFSET + * + * The command returns the offset of the timer registers, so that clients may + * map them directly. + * + * Possible status values returned are: + * NV_OK + */ + +#define NV2080_CTRL_CMD_TIMER_GET_REGISTER_OFFSET (0x20800404) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS { + NvU32 tmr_offset; +} NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS; + +/* + * NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE + * + * This structure describes the information obtained with + * NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO command. + * + * gpuTime + * GPU time is the value of GPU global timer (PTIMER) with a resolution + * of 32 nano seconds. + * cpuTime + * CPU time. Resolution of the cpu time depends on its source. Refer to + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_* for more information. + + */ +typedef struct NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE { + NV_DECLARE_ALIGNED(NvU64 cpuTime, 8); + NV_DECLARE_ALIGNED(NvU64 gpuTime, 8); +} NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE; + + +/* + * NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO + * + * This command returns correlation information between GPU time and CPU time + * for a given CPU clock type. + * + * cpuClkId + * This parameter specifies the source of the CPU clock. Legal values for + * this parameter include: + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME + * This clock id will provide real time in microseconds since + * 00:00:00 UTC on January 1, 1970. + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API + * This clock id will provide time stamp that is constant-rate, high + * precision using platform API that is also available in the user mode. + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC + * This clock id will provide time stamp using CPU's time stamp counter. + * + * sampleCount + * This field specifies the number of clock samples to be taken. + * This value cannot exceed NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES. + * + * samples + * This field returns an array of requested samples. Refer to + * NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE to get details about each entry + * in the array. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO (0x20800406) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES 16 + +#define NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS { + NvU8 cpuClkId; + NvU8 sampleCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE samples[NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES], 8); +} NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS; + +/* Legal cpuClkId values */ +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME (0x00000001) +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC (0x00000002) +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API (0x00000003) +/*! + * NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ + * + * This command changes the frequency at which Graphics Engine time stamp is + * updated. Frequency can either be set to max or restored to default. + * Clients can independently use this call to increase the timer frequency + * as a global reference count is maintained for requests to Max frequency. + * Client is assured that the system stays in this state till the requested + * client releases the state or is killed. Timer frequency will automatically + * be restored to default when there is no pending request to increase. + * + * Note that recursive requests for the same state from the same client + * are considered invalid. + * + * bSetMaxFreq + * Set to NV_TRUE if GR tick frequency needs to be set to Max. + * + * See @ref NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS for + * documentation of parameters. + * + * Possible status values returned are + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_STATE_IN_USE + * NV_ERR_INVALID_OPERATION + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ (0x20800407) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID" */ + +/*! + * This struct contains bSetMaxFreq flag. + */ +#define NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS { + NvBool bSetMaxFreq; +} NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS; + +/* _ctrl2080tmr_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h new file mode 100644 index 0000000..e4995b8 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080ucodefuzzer.finn +// + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h new file mode 100644 index 0000000..782e182 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h @@ -0,0 +1,190 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080unix.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX OS control commands and parameters */ + +/* + * NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT + * + * This command increases or decreases the value of the per-GPU GC6 blocker + * refCount used by Linux kernel clients to prevent the GPU from entering GC6. + * + * When the refCount is non-zero, the GPU cannot enter GC6. When the refCount + * transitions from zero to non-zero as a result of this command, the GPU will + * automatically come out of GC6. + * + * action Whether to increment or decrement the value of the refCount. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT (0x20803d01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS { + NvU32 action; +} NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS; + +// Possible values for action +#define NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_INC (0x00000001) +#define NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_DEC (0x00000002) + +/* + * NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF + * + * RM by default allows GCOFF but when the X driver disallows to enter in GCOFF + * then this rmcontrol sets flag as NV_FALSE and if it allows to enter in GCOFF + * then the flag is set as NV_TRUE. + * + * action Whether to allow or disallow the user mode clients to enter in GCOFF. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF (0x20803d02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS { + NvU32 action; +} NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS; + +// Possible values for action +#define NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_ALLOW (0x00000001) +#define NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_DISALLOW (0x00000002) + +/* + * NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER + * + * GPU can have integrated HDA (High Definition Audio) controller which + * can be in active or suspended state during dynamic power management. + * This command will perform HDA controller wakeup (if bEnter is false) or + * suspend (if bEnter is true). + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER (0x20803d03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS { + NvBool bEnter; +} NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS; + +/* + * NV2080_CTRL_CMD_OS_UNIX_INSTALL_PROFILER_HOOKS + * + * Initialize cyclestats HWPM support in the kernel. This will set up a callback + * event for the channel indicated by hNotifierResource. This callback will execute + * perf register read / write commands enqueued in the shared buffer indicated by + * hNotifyDataMemory. Only one client may use HWPM functionality at a time. + * + * Additionally, if perfmonIdCount is greater than zero, mode-e HWPM streaming into + * the buffer indicated by hSnapshotMemory will be initialized (but not turned on). + * Data will be copied into the provided buffer every 10ms, or whenever a + * NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER command is issued. + */ +#define NV2080_CTRL_CMD_OS_UNIX_INSTALL_PROFILER_HOOKS (0x20803d04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS { + NvHandle hNotifierResource; + NvU32 notifyDataSize; + NvHandle hNotifyDataMemory; + NvU32 perfmonIdCount; + NvU32 snapshotBufferSize; + NvHandle hSnapshotMemory; +} NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS; + +/* + * NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER + * + * Immediately copies any pending mode-e HWPM data into the previously + * installed snapshot buffer instead of waiting for the timer. + */ +#define NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER (0x20803d05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | 0x5" */ + +/* + * NV2080_CTRL_CMD_OS_UNIX_STOP_PROFILER + * + * Stop the timer responsible for copying mode-e HWPM data to the snapshot buffer. + * The snapshot buffer must not be freed by the client before this command is issued. + */ +#define NV2080_CTRL_CMD_OS_UNIX_STOP_PROFILER (0x20803d06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | 0x6" */ + +/* + * NV2080_CTRL_CMD_OS_UNIX_VIDMEM_PERSISTENCE_STATUS + * + * This command will be used by clients to check if the GPU video memory will + * be persistent during system suspend/resume cycle. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_OS_UNIX_VIDMEM_PERSISTENCE_STATUS (0x20803d07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS { + NvBool bVidmemPersistent; +} NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_OS_UNIX_UPDATE_TGP_STATUS + * + * This command will be used by clients to set restore TGP flag which will + * help to restore TGP limits when clients are destroyed. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_OS_UNIX_UPDATE_TGP_STATUS (0x20803d08) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS { + NvBool bUpdateTGP; +} NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS; +/* _ctrl2080unix_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h new file mode 100644 index 0000000..a5a9db1 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h @@ -0,0 +1,42 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080vfe.finn +// + + + +/* _ctrl2080vfe_h_ */ +#include "nvfixedtypes.h" +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "ctrl/ctrl2080/ctrl2080boardobj.h" +#include "ctrl/ctrl2080/ctrl2080bios.h" + +/* --------------------------- Forward Defines ----------------------------- */ +/* --------------------------- VFE Variable -------------------------------- */ +/* --------------------------- VFE Equation -------------------------------- */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h new file mode 100644 index 0000000..2da2c80 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h @@ -0,0 +1,407 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080vgpumgrinternal.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "ctrl/ctrla081.h" + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK + * + * This command is used to bootload GSP VGPU plugin task. + * Can be called only with SR-IOV and with VGPU_GSP_PLUGIN_OFFLOAD feature. + * + * dbdf - domain (31:16), bus (15:8), device (7:3), function (2:0) + * gfid - Gfid + * vgpuType - The Type ID for VGPU profile + * vmPid - Plugin process ID of vGPU guest instance + * swizzId - SwizzId + * numChannels - Number of channels + * numPluginChannels - Number of plugin channels + * bDisableSmcPartitionRestore - If set to true, SMC default execution partition + * save/restore will not be done in host-RM + * guestFbPhysAddrList - list of VMMU segment aligned physical address of guest FB memory + * guestFbLengthList - list of guest FB memory length in bytes + * pluginHeapMemoryPhysAddr - plugin heap memory offset + * pluginHeapMemoryLength - plugin heap memory length in bytes + * bDeviceProfilingEnabled - If set to true, profiling is allowed + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK (0x20804001) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MAX_VMMU_SEGMENTS 384 + +/* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */ +#define NV2080_GPU_MAX_ENGINES 0x3e + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS { + NvU32 dbdf; + NvU32 gfid; + NvU32 vgpuType; + NvU32 vmPid; + NvU32 swizzId; + NvU32 numChannels; + NvU32 numPluginChannels; + NvU32 chidOffset[NV2080_GPU_MAX_ENGINES]; + NvBool bDisableDefaultSmcExecPartRestore; + NvU32 numGuestFbSegments; + NV_DECLARE_ALIGNED(NvU64 guestFbPhysAddrList[NV2080_CTRL_MAX_VMMU_SEGMENTS], 8); + NV_DECLARE_ALIGNED(NvU64 guestFbLengthList[NV2080_CTRL_MAX_VMMU_SEGMENTS], 8); + NV_DECLARE_ALIGNED(NvU64 pluginHeapMemoryPhysAddr, 8); + NV_DECLARE_ALIGNED(NvU64 pluginHeapMemoryLength, 8); + NV_DECLARE_ALIGNED(NvU64 ctrlBuffOffset, 8); + NvBool bDeviceProfilingEnabled; +} NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK + * + * This command is used to shutdown GSP VGPU plugin task. + * Can be called only with SR-IOV and with VGPU_GSP_PLUGIN_OFFLOAD feature. + * + * gfid - Gfid + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK (0x20804002) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS { + NvU32 gfid; +} NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE + * + * This command is used to add a new vGPU config to the pGPU in physical RM. + * Unlike NVA081_CTRL_CMD_VGPU_CONFIG_SET_INFO, it does no validation + * and is only to be used internally. + * + * discardVgpuTypes [IN] + * This parameter specifies if existing vGPU configuration should be + * discarded for given pGPU + * + * vgpuInfoCount [IN] + * This parameter specifies the number of entries of virtual GPU type +* information + * + * vgpuInfo [IN] + * This parameter specifies virtual GPU type information + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE (0x20804003) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS { + NvBool discardVgpuTypes; + NvU32 vgpuInfoCount; + NV_DECLARE_ALIGNED(NVA081_CTRL_VGPU_INFO vgpuInfo[NVA081_MAX_VGPU_TYPES_PER_PGPU], 8); +} NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS; + +/* + * NV2080_GUEST_VM_INFO + * + * This structure represents vGPU guest's (VM's) information + * + * vmPid [OUT] + * This param specifies the vGPU plugin process ID + * guestOs [OUT] + * This param specifies the vGPU guest OS type + * migrationProhibited [OUT] + * This flag indicates whether migration is prohibited for VM or not + * guestNegotiatedVgpuVersion [OUT] + * This param specifies the vGPU version of guest driver after negotiation + * frameRateLimit [OUT] + * This param specifies the current value of FRL set for guest + * licensed [OUT] + * This param specifies whether the VM is Unlicensed/Licensed + * licenseState [OUT] + * This param specifies the current state of the GRID license state machine + * licenseExpiryTimestamp [OUT] + * License expiry time in seconds since UNIX epoch + * licenseExpiryStatus [OUT] + * License expiry status + * guestDriverVersion [OUT] + * This param specifies the driver version of the driver installed on the VM + * guestDriverBranch [OUT] + * This param specifies the driver branch of the driver installed on the VM + * guestVmInfoState [OUT] + * This param stores the current state of guest dependent fields + * + */ +typedef struct NV2080_GUEST_VM_INFO { + NvU32 vmPid; + NvU32 guestOs; + NvU32 migrationProhibited; + NvU32 guestNegotiatedVgpuVersion; + NvU32 frameRateLimit; + NvBool licensed; + NvU32 licenseState; + NvU32 licenseExpiryTimestamp; + NvU8 licenseExpiryStatus; + NvU8 guestDriverVersion[NVA081_VGPU_STRING_BUFFER_SIZE]; + NvU8 guestDriverBranch[NVA081_VGPU_STRING_BUFFER_SIZE]; + GUEST_VM_INFO_STATE guestVmInfoState; +} NV2080_GUEST_VM_INFO; + +/* + * NV2080_GUEST_VGPU_DEVICE + * + * This structure represents host vgpu device's (assigned to VM) information + * + * gfid [OUT] + * This parameter specifies the gfid of vGPU assigned to VM. + * vgpuPciId [OUT] + * This parameter specifies vGPU PCI ID + * vgpuDeviceInstanceId [OUT] + * This paramter specifies the vGPU device instance per VM to be used for supporting + * multiple vGPUs per VM. + * fbUsed [OUT] + * This parameter specifies FB usage in bytes + * eccState [OUT] + * This parameter specifies the ECC state of the virtual GPU. + * One of NVA081_CTRL_ECC_STATE_xxx values. + * bDriverLoaded [OUT] + * This parameter specifies whether driver is loaded on this particular vGPU. + * + */ +typedef struct NV2080_HOST_VGPU_DEVICE { + NvU32 gfid; + NV_DECLARE_ALIGNED(NvU64 vgpuPciId, 8); + NvU32 vgpuDeviceInstanceId; + NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); + NvU32 encoderCapacity; + NvU32 eccState; + NvBool bDriverLoaded; +} NV2080_HOST_VGPU_DEVICE; + +/* + * NV2080_VGPU_GUEST + * + * This structure represents a vGPU guest + * + */ +typedef struct NV2080_VGPU_GUEST { + NV2080_GUEST_VM_INFO guestVmInfo; + NV_DECLARE_ALIGNED(NV2080_HOST_VGPU_DEVICE vgpuDevice, 8); +} NV2080_VGPU_GUEST; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU + * + * This command enumerates list of vGPU guest instances per pGpu + * + * numVgpu [OUT] + * This parameter specifies the number of virtual GPUs created on this physical GPU + * + * vgpuGuest [OUT] + * This parameter specifies an array containing guest vgpu's information for + * all vGPUs created on this physical GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU (0x20804004) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS { + NvU32 numVgpu; + NV_DECLARE_ALIGNED(NV2080_VGPU_GUEST vgpuGuest[NVA081_MAX_VGPU_PER_PGPU], 8); +} NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO + * + * This command is used clear guest vm info. It should be used when + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE + * is called with NVA081_NOTIFIERS_EVENT_VGPU_GUEST_DESTROYED state. + * + * gfid [IN] + * This parameter specifies the gfid of vGPU assigned to VM. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO (0x20804005) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS { + NvU32 gfid; +} NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE + * + * This command is used to get the FB usage of all vGPU instances running on a GPU. + * + * vgpuCount [OUT] + * This field specifies the number of vGPU devices for which FB usage is returned. + * vgpuFbUsage [OUT] + * This is an array of type NV2080_VGPU_FB_USAGE, which contains a list of vGPU gfid + * and their corresponding FB usage in bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE (0x20804006) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID" */ + +typedef struct NV2080_VGPU_FB_USAGE { + NvU32 gfid; + NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); +} NV2080_VGPU_FB_USAGE; + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS { + NvU32 vgpuCount; + NV_DECLARE_ALIGNED(NV2080_VGPU_FB_USAGE vgpuFbUsage[NVA081_MAX_VGPU_PER_PGPU], 8); +} NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY + * + * This command is used to set vGPU instance's (represented by gfid) encoder Capacity. + * + * gfid [IN] + * This parameter specifies the gfid of vGPU assigned to VM. + * encoderCapacity [IN] + * Encoder capacity value from 0 to 100. Value of 0x00 indicates encoder performance + * may be minimal for this GPU and software should fall back to CPU-based encode. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY (0x20804007) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS { + NvU32 gfid; + NvU32 encoderCapacity; +} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP + * + * This command is used to cleanup all the GSP VGPU plugin task allocated resources after its shutdown. + * Can be called only with SR-IOV and with VGPU_GSP_PLUGIN_OFFLOAD feature. + * + * gfid [IN] + * This parameter specifies the gfid of vGPU assigned to VM. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP (0x20804008) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS { + NvU32 gfid; +} NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS; + +#define NV2080_CTRL_MAX_NVU32_TO_CONVERTED_STR_LEN 8 +#define NV2080_CTRL_MAX_GPC_COUNT 32 + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING + * + * Reroutes kvgpumgrGetPgpuFSEncoding to vgpuMgrGetPgpuFSEncoding. + * + * pgpuString [OUT] + * Resulting PGPU string + * pgpuStringSize + * PGPU string size + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING (0x20804009) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS { + NvU8 pgpuString[NVA081_PGPU_METADATA_STRING_SIZE]; + NvU32 pgpuStringSize; +} NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT + * + * Reroutes kvgpumgrCheckPgpuMigrationSupport to vgpuMgrCheckPgpuMigrationSupport. + * + * bIsMigrationSupported [OUT] + * Resulting status of the migration support + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT (0x2080400a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS { + NvBool bIsMigrationSupported; +} NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG + * + * Sets vgpu manager parameters. This control is used after GSP initialization. + * + * bSupportHeterogeneousTimeSlicedVgpuTypes [IN] + * Enable/disable heterogeneous time-sliced vgpu types + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG (0x2080400b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS { + NvBool bSupportHeterogeneousTimeSlicedVgpuTypes; +} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS; + +/* _ctrl2080vgpumgrinternal_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h new file mode 100644 index 0000000..eacd596 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h @@ -0,0 +1,38 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080volt.finn +// + + + +/* _ctrl2080volt_h_ */ + +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "ctrl/ctrl2080/ctrl2080boardobj.h" +#include "ctrl/ctrl2080/ctrl2080pmumon.h" + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f.h new file mode 100644 index 0000000..b526aa3 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f.finn +// + + + + +#include "ctrl/ctrlxxxx.h" +#include "ctrl208f/ctrl208fpower.h" +#include "ctrl208f/ctrl208ffifo.h" +#include "ctrl208f/ctrl208ffb.h" +#include "ctrl208f/ctrl208ffbio.h" + + +#include "ctrl208f/ctrl208fbif.h" +#include "ctrl208f/ctrl208fbus.h" +#include "ctrl208f/ctrl208fevent.h" +#include "ctrl208f/ctrl208fgpu.h" +#include "ctrl208f/ctrl208fgr.h" +#include "ctrl208f/ctrl208fclk.h" +#include "ctrl208f/ctrl208fpmgr.h" +#include "ctrl208f/ctrl208fdma.h" +#include "ctrl208f/ctrl208fmmu.h" + + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fbase.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fbase.h new file mode 100644 index 0000000..eb08864 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fbase.h @@ -0,0 +1,71 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fbase.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV20_SUBDEVICE_DIAG: diagnostic class control commands and parameters */ + +#define NV208F_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x208F, NV208F_CTRL_##cat, idx) + +/* Subdevice diag command categories (6bits) */ +#define NV208F_CTRL_RESERVED (0x00) +#define NV208F_CTRL_POWER (0x01) +#define NV208F_CTRL_THERMAL (0x02) +#define NV208F_CTRL_SEQ (0x03) +#define NV208F_CTRL_FIFO (0x04) +#define NV208F_CTRL_FB (0x05) +#define NV208F_CTRL_MC (0x06) +#define NV208F_CTRL_BIF (0x07) +#define NV208F_CTRL_CLK (0x08) +#define NV208F_CTRL_PERF (0x09) +#define NV208F_CTRL_FBIO (0x0A) +#define NV208F_CTRL_MMU (0x0B) +#define NV208F_CTRL_PMU (0x0C) +#define NV208F_CTRL_EVENT (0x10) +#define NV208F_CTRL_GPU (0x11) +#define NV208F_CTRL_GR (0x12) +#define NV208F_CTRL_PMGR (0x13) +#define NV208F_CTRL_DMA (0x14) +// const NV208F_CTRL_TMR = (0x15); // not supported +#define NV208F_CTRL_RMFS (0x16) +#define NV208F_CTRL_GSPMSGTIMING (0x17) +#define NV208F_CTRL_BUS (0x18) + +/* + * NV208F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV208F_CTRL_CMD_NULL (0x208f0000) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrl208fbase_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h new file mode 100644 index 0000000..3499ef9 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h @@ -0,0 +1,194 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fbif.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* +* NV208F_CTRL_CMD_BIF_PBI_WRITE_COMMAND +* +* Control command to send a write command to the Post Box Interface +* +* Parameters: +* +*cmdFuncId +* this specifies the function that needs to be performed on pbi +*data +* the data to be set in the data in register +* status +* this corresponds to pbi status register +* sysNotify +* this corresponds to system notify event, i.e. whether system +* needs to be notified of command completion +* drvNotify +* this corresponds to driver notify event, i.e. whether driver +* needs to be notified of command completion +* +* For the possible values of the above parameters refer rmpbicmdif.h +*/ +#define NV208F_CTRL_CMD_BIF_PBI_WRITE_COMMAND (0x208f0701) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_PBI_WRITE_COMMAND_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_BIF_PBI_WRITE_COMMAND_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV208F_CTRL_BIF_PBI_WRITE_COMMAND_PARAMS { + NvU8 cmdFuncId; + NvU32 data; + NvU8 status; + NvBool sysNotify; + NvBool drvNotify; +} NV208F_CTRL_BIF_PBI_WRITE_COMMAND_PARAMS; + +/* +* NV208F_CTRL_CMD_BIF_CONFIG_REG_READ +* This command is used to read any of the PBI registers in the config space +* +* Parameters: +* +* RegIndex +* Defines the index of the PBI register +* data +* Data that is read +*/ +#define NV208F_CTRL_CMD_BIF_CONFIG_REG_READ (0x208f0702) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_CONFIG_REG_READ_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_BIF_CONFIG_REG_READ_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV208F_CTRL_BIF_CONFIG_REG_READ_PARAMS { + NvU8 RegIndex; + NvU32 data; +} NV208F_CTRL_BIF_CONFIG_REG_READ_PARAMS; + +/* +* NV208F_CTRL_CMD_BIF_CONFIG_REG_WRITE +* This command is used to write any of the PBI registers in the config space +* +* Parameters: +* +* RegIndex +* Defines the index of the PBI register +* data +* Data that is to be written +*/ +#define NV208F_CTRL_CMD_BIF_CONFIG_REG_WRITE (0x208f0703) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_CONFIG_REG_WRITE_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_BIF_CONFIG_REG_WRITE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV208F_CTRL_BIF_CONFIG_REG_WRITE_PARAMS { + NvU8 RegIndex; + NvU32 data; +} NV208F_CTRL_BIF_CONFIG_REG_WRITE_PARAMS; + +/* +* NV208F_CTRL_CMD_BIF_INFO +* This command is used to read a bif property +* +* Parameters: +* +* index +* Defines the index of the property to read +* data +* Data that is read +*/ +#define NV208F_CTRL_CMD_BIF_INFO (0x208f0704) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_INFO_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_BIF_INFO_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV208F_CTRL_BIF_INFO_PARAMS { + NvU32 index; + NvU32 data; +} NV208F_CTRL_BIF_INFO_PARAMS; + +/* valid bif info index values */ +#define NV208F_CTRL_BIF_INFO_INDEX_L0S_ENABLED (0x00000000) +#define NV208F_CTRL_BIF_INFO_INDEX_L1_ENABLED (0x00000001) + +/* + * NV208F_CTRL_CMD_BIF_ECC_INJECT_ERROR + * + * This ctrl call injects PCI-E XPL-EP ECC errors. Please see the confluence + * page "ECC" for more information on ECC and ECC injection: + * + * Parameters: + * + * errorUnit + * Specifies the HW unit where the injection will occur. + * + * errorType + * Specifies whether the injected error will be correctable or uncorrectable. + * Correctable errors have no effect on running programs while uncorrectable + * errors will cause all channels to be torn down. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_BIF_ECC_INJECT_ERROR (0x208f0705) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */ + + + +#define NV208F_CTRL_BIF_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV208F_CTRL_BIF_ECC_INJECT_ERROR_PARAMS { + NvU8 errorType; + NvU8 errorUnit; +} NV208F_CTRL_BIF_ECC_INJECT_ERROR_PARAMS; + +/* + * NV208F_CTRL_CMD_BIF_ECC_INJECTION_SUPPORTED + * + * Reports if error injection is supported for XPL-EP + * + * bCorrectableSupported [out]: + * Boolean value that shows if correcatable errors can be injected. + * + * bUncorrectableSupported [out]: + * Boolean value that shows if uncorrecatable errors can be injected. + * + * Return values: + * NV_OK on success + * NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled. + * NV_ERR_NOT_SUPPORTED otherwise + * + * + */ +#define NV208F_CTRL_CMD_BIF_ECC_INJECTION_SUPPORTED (0x208f0706) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_BIF_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV208F_CTRL_BIF_ECC_INJECTION_SUPPORTED_PARAMS { + NvU8 errorUnit; + NvBool bCorrectableSupported; + NvBool bUncorrectableSupported; +} NV208F_CTRL_BIF_ECC_INJECTION_SUPPORTED_PARAMS; + +/* _ctrl208fbif_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fbus.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fbus.h new file mode 100644 index 0000000..11fd26e --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fbus.h @@ -0,0 +1,113 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fbus.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* + * NV208F_CTRL_CMD_BUS_IS_BAR1_VIRTUAL + * + * This command checks whether or not BAR1 is in virtual mode. + * This API is intended for internal testing only. + * + * bIsVirtual + * Whether or not Bar1 is in virtual mode. + */ +#define NV208F_CTRL_CMD_BUS_IS_BAR1_VIRTUAL (0x208f1801) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BUS_INTERFACE_ID << 8) | NV208F_CTRL_BUS_IS_BAR1_VIRTUAL_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_BUS_IS_BAR1_VIRTUAL_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV208F_CTRL_BUS_IS_BAR1_VIRTUAL_PARAMS { + NvBool bIsVirtual; +} NV208F_CTRL_BUS_IS_BAR1_VIRTUAL_PARAMS; + +/* + * NV208F_CTRL_CMD_BUS_ECC_INJECT_ERROR + * + * This ctrl call injects BUS ECC errors. Please see the confluence + * page "ECC" for more information on ECC and ECC injection: + * + * Parameters: + * + * location + * Specifies the BUS HW unit where the injection will occur. + * + * errorType + * Specifies whether the injected error will be correctable or uncorrectable. + * Correctable errors have no effect on running programs while uncorrectable + * errors will cause all channels to be torn down. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_BUS_ECC_INJECT_ERROR (0x208f1802) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BUS_INTERFACE_ID << 8) | NV208F_CTRL_BUS_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */ + + + +#define NV208F_CTRL_BUS_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV208F_CTRL_BUS_ECC_INJECT_ERROR_PARAMS { + NvU8 errorType; + NvU8 errorUnit; +} NV208F_CTRL_BUS_ECC_INJECT_ERROR_PARAMS; + +/* + * NV208F_CTRL_CMD_BUS_ECC_INJECTION_SUPPORTED + * + * Reports if error injection is supported for BUS units + * + * bCorrectableSupported [out]: + * Boolean value that shows if correcatable errors can be injected. + * + * bUncorrectableSupported [out]: + * Boolean value that shows if uncorrecatable errors can be injected. + * + * Return values: + * NV_OK on success + * NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled. + * NV_ERR_NOT_SUPPORTED otherwise + * + * + */ +#define NV208F_CTRL_CMD_BUS_ECC_INJECTION_SUPPORTED (0x208f1803) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BUS_INTERFACE_ID << 8) | NV208F_CTRL_BUS_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_BUS_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV208F_CTRL_BUS_ECC_INJECTION_SUPPORTED_PARAMS { + NvU8 errorUnit; + NvBool bCorrectableSupported; + NvBool bUncorrectableSupported; +} NV208F_CTRL_BUS_ECC_INJECTION_SUPPORTED_PARAMS; + +/* _ctrl208fbus_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fclk.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fclk.h new file mode 100644 index 0000000..450d881 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fclk.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fclk.finn +// + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fdma.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fdma.h new file mode 100644 index 0000000..a302d42 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fdma.h @@ -0,0 +1,92 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fdma.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* + * NV208F_CTRL_CMD_DMA_IS_SUPPORTED_SPARSE_VIRTUAL + * + * This command checks whether or not "sparse" virtual address ranges are + * supported for a given chip. This API is intended for debug-use only. + * + * bIsSupported + * Whether or not "sparse" virtual address ranges are supported. + */ +#define NV208F_CTRL_CMD_DMA_IS_SUPPORTED_SPARSE_VIRTUAL (0x208f1401) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_DMA_INTERFACE_ID << 8) | NV208F_CTRL_DMA_IS_SUPPORTED_SPARSE_VIRTUAL_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_DMA_IS_SUPPORTED_SPARSE_VIRTUAL_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV208F_CTRL_DMA_IS_SUPPORTED_SPARSE_VIRTUAL_PARAMS { + NvBool bIsSupported; +} NV208F_CTRL_DMA_IS_SUPPORTED_SPARSE_VIRTUAL_PARAMS; + +/* + * NV208F_CTRL_CMD_DMA_GET_VAS_BLOCK_DETAILS + * + * This command retrieves various details of the virtual address space block + * allocated from the virtual address space heap for the given virtual address. + * + * virtualAddress + * Virtual address to get information about. + * + * beginAddress + * Start address of the corresponding virtual address space block. + * + * endAddress + * End address (inclusive) of the corresponding virtual address space + * block. + * + * alignedAddress + * Aligned address of the corresponding virtual address space block. + * + * pageSize + * Page size of the virtual address space block. + * + * hVASpace + * Handle to an allocated VA space. If 0, it is assumed that the device's + * VA space should be used. + */ +#define NV208F_CTRL_CMD_DMA_GET_VAS_BLOCK_DETAILS (0x208f1402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_DMA_INTERFACE_ID << 8) | NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 virtualAddress, 8); + NV_DECLARE_ALIGNED(NvU64 beginAddress, 8); + NV_DECLARE_ALIGNED(NvU64 endAddress, 8); + NV_DECLARE_ALIGNED(NvU64 alignedAddress, 8); + NvU32 pageSize; + NvHandle hVASpace; +} NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS; + +/* _ctrl208fdma_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fevent.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fevent.h new file mode 100644 index 0000000..3777829 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fevent.h @@ -0,0 +1,93 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fevent.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* NV20_SUBDEVICE_DIAG event-related control commands and parameters */ + +/* + * NV208F_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * This command sets event notification state for the associated subdevice. + * This command requires that an instance of NV01_EVENT has been previously + * bound to the associated subdevice object. + * + * event + * This parameter specifies the type of event to which the specified + * action is to be applied. This parameter must specify a valid + * NV208F_NOTIFIERS value (see cl208f.h for more details) and should + * not exceed one less NV208F_NOTIFIERS_MAXCOUNT. + * action + * This parameter specifies the desired event notification action. + * Valid notification actions include: + * NV208F_CTRL_SET_EVENT_NOTIFICATION_DISABLE + * This action disables event notification for the specified + * event for the associated subdevice object. + * NV208F_CTRL_SET_EVENT_NOTIFICATION_SINGLE + * This action enables single-shot event notification for the + * specified event for the associated subdevice object. + * NV208F_CTRL_SET_EVENT_NOTIFICATION_REPEAT + * This action enables repeated event notification for the specified + * event for the associated system controller object. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV208F_CTRL_CMD_EVENT_SET_NOTIFICATION (0x208f1001) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_EVENT_INTERFACE_ID << 8) | NV208F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV208F_CTRL_EVENT_SET_NOTIFICATION_PARAMS { + NvU32 event; + NvU32 action; +} NV208F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NV208F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NV208F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001) +#define NV208F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002) + +/* + * NV208F_CTRL_CMD_EVENT_SET_TRIGGER + * + * This command triggers a software event for the associated subdevice. + * This command accepts no parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV208F_CTRL_CMD_EVENT_SET_TRIGGER (0x208f1002) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_EVENT_INTERFACE_ID << 8) | 0x2" */ + +/* _ctrl208fevent_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h new file mode 100644 index 0000000..ec16916 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h @@ -0,0 +1,611 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208ffb.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* + * NV208F_CTRL_CMD_FB_GET_INFO + * + * This command returns fb engine information for the associated GPU. + * The client specifies what information to query through 'index' param. + * On success, the information is stored in the 'data' param. + * + * index + * Specify what information to query. Please see below for valid values of + * indexes for this command. + * data + * On success, this param will hold the data that the client queried for. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_FB_GET_INFO (0x208f0501) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV208F_CTRL_FB_GET_INFO_PARAMS { + NvU32 index; + NV_DECLARE_ALIGNED(NvU64 data, 8); +} NV208F_CTRL_FB_GET_INFO_PARAMS; + +/* valid fb info index values */ +#define NV208F_CTRL_FB_INFO_INDEX_FREE_CONTIG_COMPRESSION_SIZE (0x00000001) + +#define NV208F_CTRL_FB_INFO_INDEX_MAX NV208F_CTRL_FB_INFO_INDEX_FREE_CONTIG_COMPRESSION_SIZE + +/* + * NV208F_CTRL_CMD_FB_GET_ZBC_REFCOUNT + * + * This command gets the ZBC reference count associated with a given + * compression tag address. It is not supported on GPUs which support class + * GF100_ZBC_CLEAR as it is specific to a different hardware implementation. + * + * compTagAddress + * The input parameter indicating the compression tag address for which the + * associated ZBC refcount should be looked up. + * zbcRefCount + * An array of reference counts for the ZBC clear values associated with + * compTagAddress. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_FB_GET_ZBC_REFCOUNT (0x208f0505) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | 0x5" */ // Deprecated, removed form RM + +#define NV208F_CTRL_FB_GET_ZBC_REFCOUNT_MAX_REFCOUNTS 2 +typedef struct NV208F_CTRL_FB_GET_ZBC_REFCOUNT_PARAMS { + NvU32 compTagAddress; + NvU32 zbcRefCount[NV208F_CTRL_FB_GET_ZBC_REFCOUNT_MAX_REFCOUNTS]; +} NV208F_CTRL_FB_GET_ZBC_REFCOUNT_PARAMS; + +/* + * NV208F_CTRL_CMD_FB_CTRL_GPU_CACHE + * + * This command controls the state of a cache which all GPU memory accesses go + * through. If supported, it allows changing of the power state and the write + * mode. This is only supported when NV_VERIF_FEATURES is defined. An error + * will be returned if the requested combination of settings is not possible. + * + * writeMode + * Specifies the write mode of the cache. Possible values are defined in + * NV208F_CTRL_FB_CTRL_GPU_CACHE_WRITE_MODE. Passing _DEFAULT means to + * maintain the current write mode. It is illegal to change the write mode + * while the cache is disabled or in the same call as a request to disable + * it. + * powerState + * Specifies the power state of the cache. Possible values are defined in + * NV208F_CTRL_FB_CTRL_GPU_CACHE_POWER_STATE. Passing _DEFAULT means + * to maintain the current power state. + * rcmState + * Specifies the reduced cache mode of the cache. Possible values are + * defined in NV208F_CTRL_FB_CTRL_GPU_CACHE_RCM_STATE. Passing _DEFAULT + * means to maintain the current RCM state. + * vgaCacheMode + * Specifies whether or not to enable VGA out-of-cache mode. Possible + * values are defined in NV208F_CTRL_FB_CTRL_GPU_CACHE_VGA_MODE. Passing + * _DEFAULT means to maintain the current VGA caching mode. + * cacheReset + * Triggers a hardware reset of the cache. Possible values are defined in + * NV208F_CTRL_FB_CTRL_GPU_CACHE_CACHE_RESET. Passing _DEFAULT does + * nothing while passing _RESET clears all data in the cache. + * flags + * Contains flags to control the details of how transitions should be + * handled. Possible values are defined in + * NV208F_CTRL_FB_CTRL_GPU_CACHE_FLAGS. Passing _DEFAULT for any of + * the fields means to use the defaults specified by the Resource Manager. + * Note not all options are available for all transitions. Flags that are + * set but not applicable will be silently ignored. + * bypassMode + * (Fermi only) Specifies the bypass mode of the L2 cache. Normal GPU + * operation is _DISABLE. For TEST ONLY, setting _ENABLE enables a debug + * mode where all transactions miss in L2 and no writes are combined, + * essentially disabling the caching feature of the L2 cache. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV208F_CTRL_CMD_FB_CTRL_GPU_CACHE (0x208f0506) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_CTRL_GPU_CACHE_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV208F_CTRL_FB_CTRL_GPU_CACHE_PARAMS { + NvU32 writeMode; + NvU32 powerState; + NvU32 rcmState; + NvU32 vgaCacheMode; + NvU32 cacheReset; + NvU32 flags; + NvU32 bypassMode; +} NV208F_CTRL_FB_CTRL_GPU_CACHE_PARAMS; + +/* valid values for writeMode */ +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_WRITE_MODE_DEFAULT (0x00000000) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_WRITE_MODE_WRITETHROUGH (0x00000001) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_WRITE_MODE_WRITEBACK (0x00000002) + +/* valid values for powerState */ +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_POWER_STATE_DEFAULT (0x00000000) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_POWER_STATE_ENABLED (0x00000001) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_POWER_STATE_DISABLED (0x00000002) + +/* valid values for rcmState */ +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_RCM_STATE_DEFAULT (0x00000000) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_RCM_STATE_FULL (0x00000001) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_RCM_STATE_REDUCED (0x00000002) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_RCM_STATE_ZERO_CACHE (0x00000003) + +/* valid values for vgaCacheMode */ +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_VGA_MODE_DEFAULT (0x00000000) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_VGA_MODE_ENABLED (0x00000001) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_VGA_MODE_DISABLED (0x00000002) + +/* valid values for cacheReset */ +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_CACHE_RESET_DEFAULT (0x00000000) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_CACHE_RESET_RESET (0x00000001) + +/* valid fields and values for flags */ +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_FLAGS_MODE 1:0 +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_FLAGS_MODE_DEFAULT (0x00000000) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_FLAGS_MODE_RM (0x00000001) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_FLAGS_MODE_PMU (0x00000002) + +/* valid values for bypassMode */ +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_BYPASS_MODE_DEFAULT (0x00000000) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_BYPASS_MODE_DISABLED (0x00000001) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_BYPASS_MODE_ENABLED (0x00000002) + + + +/* + * NV208F_CTRL_CMD_FB_SET_STATE + * + * This command is used to put fb engine in a state requested by the caller. + * + * state + * This parameter specifies the desired engine state: + * NV208F_CTRL_FB_SET_STATE_STOPPED + * This value stops/halts the fb engine. + * NV208F_CTRL_FB_SET_STATE_RESTART + * This value restarts fb from a stopped state. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_FB_SET_STATE (0x208f0508) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_SET_STATE_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_SET_STATE_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV208F_CTRL_FB_SET_STATE_PARAMS { + NvU32 state; +} NV208F_CTRL_FB_SET_STATE_PARAMS; + +/* valid values for state */ +#define NV208F_CTRL_FB_SET_STATE_STOPPED (0x00000000) +#define NV208F_CTRL_FB_SET_STATE_RESTART (0x00000001) + +/* + * NV208F_CTRL_CMD_GPU_ECC_SCRUB_DIAG + * + * This command reads all the settings internal to scrubbing (both asynchronous + * and synchronous. + * + * Currently implemented: FB offset scrubber has completed, FB offset that scrubber + * is completing to, whether or not asynchronous scrubbing is enabled. + * + * fbOffsetCompleted + * This is the offset into FB that the scrubber has completed up to at the + * time this function is invoked. Note that the scrubber is top-down. Therefore + * the memory that remains unscrubbed is from 0x0 to fbOffsetCompleted. + * + * fbEndOffset + * This is the offset of the base of the last block that ECC asynchronous + * scrubber has been tasked to scrub. + * + * bAsyncScru bDisabled + * This is NV_TRUE if asynchronous scrubbing is disabled and NV_FALSE if + * asynchronous scrubbing is enabled. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV208F_CTRL_CMD_FB_ECC_SCRUB_DIAG (0x208f0509) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_CMD_FB_ECC_SCRUB_DIAG_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_CMD_FB_ECC_SCRUB_DIAG_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV208F_CTRL_CMD_FB_ECC_SCRUB_DIAG_PARAMS { + NV_DECLARE_ALIGNED(NvU64 fbOffsetCompleted, 8); + NV_DECLARE_ALIGNED(NvU64 fbEndOffset, 8); + NvBool bAsyncScrubDisabled; +} NV208F_CTRL_CMD_FB_ECC_SCRUB_DIAG_PARAMS; + +/* + * NV208F_CTRL_CMD_GPU_ECC_ASYNCH_SCRUB_REGION + * + * This command launches the ECC scrubber in asynchronous mode. The scrubber, as + * in normal operation, will continue to operate until all of FB (excluding + * dedicated system memory) has been scrubbed. Like usual operation, scrubbing is + * only done on silicon. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV208F_CTRL_CMD_FB_ECC_ASYNC_SCRUB_REGION (0x208f050a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_CMD_FB_ECC_ASYNC_SCRUB_REGION_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_CMD_FB_ECC_ASYNC_SCRUB_REGION_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV208F_CTRL_CMD_FB_ECC_ASYNC_SCRUB_REGION_PARAMS { + NV_DECLARE_ALIGNED(NvU64 startBlock, 8); + NV_DECLARE_ALIGNED(NvU64 endBlock, 8); +} NV208F_CTRL_CMD_FB_ECC_ASYNC_SCRUB_REGION_PARAMS; + +/* + * NV208F_CTRL_CMD_GPU_ECC_ERROR_INFO + * This is a structure that is defined here for diag/debug purposes in mods. + * It is used to return the error information as part of the callback to + * kernel clients registering for SBE/DBE callbacks. + */ + +typedef struct NV208F_CTRL_CMD_FB_ECC_ERROR_INFO { + NvU32 row; + NvU32 bank; + NvU32 col; + NvU32 extBank; + NvU32 xbarAddress; + NV_DECLARE_ALIGNED(NvU64 physAddress, 8); +} NV208F_CTRL_CMD_FB_ECC_ERROR_INFO; + + +#define NV208F_CTRL_CMD_FB_ECC_GET_FORWARD_MAP_ADDRESS (0x208f050c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_CMD_FB_ECC_GET_FORWARD_MAP_ADDRESS_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_CMD_FB_ECC_GET_FORWARD_MAP_ADDRESS_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV208F_CTRL_CMD_FB_ECC_GET_FORWARD_MAP_ADDRESS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 pAddr, 8); + NvU32 row; + NvU32 bank; + NvU32 col; + NvU32 extBank; + NvU32 rank; + NvU32 sublocation; + NvU32 partition; + NvU32 writeKillPtr0; + NvU32 injectionAddr; + NvU32 injectionAddrExt; + NvU32 rbcAddress; + NvU32 rbcAddressExt; + NvU32 rbcAddressExt2; + NvU32 eccCol; +} NV208F_CTRL_CMD_FB_ECC_GET_FORWARD_MAP_ADDRESS_PARAMS; + +/* + * NV208F_CTRL_CMD_FB_ECC_SET_KILL_PTR + * + * This command sets the kill pointer for the specified DRAM address. If + * the kill pointer is set to NV208F_CTRL_FB_ERROR_TYPE_CORRECTABLE + * or NV208F_CTRL_FB_ERROR_TYPE_UNCORRECTABLE, accesses to the specified + * address will result in ECC errors until all kill pointers are unset + * using NV208F_CTRL_FB_ERROR_TYPE_NONE. + * + * Only one kill pointer can be set at a time. Setting a kill pointer will + * clear all currently set kill pointers and set the new kill pointer. + * Calling NV208F_CTRL_FB_ERROR_TYPE_NONE simply clears all currently set + * kill pointers. + * + * errorType + * The type of kill pointer to set. NV208F_CTRL_FB_ERROR_TYPE_CORRECTABLE + * will set a single kill pointer resulting in a correctable error. + * NV208F_CTRL_FB_ERROR_TYPE_UNCORRECTABLE will set both kill pointers + * resulting in an uncorrectable error. NV208F_CTRL_FB_ERROR_TYPE_NONE + * will clear all kill pointers, which stops the associated addresses + * from generating ECC errors if NV208F_CTRL_FB_ERROR_TYPE_CORRECTABLE + * or NV208F_CTRL_FB_ERROR_TYPE_UNCORRECTABLE was previously set. + * Only one kill pointer can be set at a time and setting a new + * kill pointer will clear the previous kill pointer. + * + * address + * The physical DRAM address to be targeted by the kill pointer + * + * bProdInjection + * Whether the kill pointer is set through the production injection flow or not + */ +#define NV208F_CTRL_CMD_FB_ECC_SET_KILL_PTR (0x208f050e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_ECC_SET_KILL_PTR_PARAMS_MESSAGE_ID" */ + +typedef enum NV208F_CTRL_FB_ERROR_TYPE { + NV208F_CTRL_FB_ERROR_TYPE_CORRECTABLE = 0, + NV208F_CTRL_FB_ERROR_TYPE_UNCORRECTABLE = 1, + NV208F_CTRL_FB_ERROR_TYPE_NONE = 2, +} NV208F_CTRL_FB_ERROR_TYPE; + +#define NV208F_CTRL_FB_ECC_SET_KILL_PTR_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV208F_CTRL_FB_ECC_SET_KILL_PTR_PARAMS { + NV208F_CTRL_FB_ERROR_TYPE errorType; + NV_DECLARE_ALIGNED(NvU64 address, 8); + NvBool bProdInjection; +} NV208F_CTRL_FB_ECC_SET_KILL_PTR_PARAMS; + + + +/* + * NV208F_CTRL_CMD_FB_INJECT_LTC_ECC_ERROR + * + * This API allows a client to inject ECC errors in the L2. + * + * ltc: + * The physical LTC number to inject the error into. + * slice: + * THe physical slice number within the LTC to inject the error into. + * locationMask + * LTC location subtype(s) where error is to be injected. (Valid on Ampere and later) + * errorType + * Type of error to inject + * NV208F_CTRL_FB_ERROR_TYPE_CORRECTABLE for SBE. + * NV208F_CTRL_FB_ERROR_TYPE_UNCORRECTABLE for DBE. + * + */ +#define NV208F_CTRL_CMD_FB_INJECT_LTC_ECC_ERROR (0x208f050f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_INJECT_LTC_ECC_ERROR_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_INJECT_LTC_ECC_ERROR_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NV208F_CTRL_FB_INJECT_LTC_ECC_ERROR_PARAMS { + NvU8 ltc; + NvU8 slice; + NvU8 locationMask; + NV208F_CTRL_FB_ERROR_TYPE errorType; +} NV208F_CTRL_FB_INJECT_LTC_ECC_ERROR_PARAMS; + +/* + * NV208F_CTRL_CMD_FB_ECC_INJECTION_SUPPORTED + * + * Reports if error injection is supported for a given HW unit + * + * location [in]: + * The ECC protected unit for which ECC injection support is being checked. + * The location type is defined by NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC. + * + * bCorrectableSupported [out]: + * Boolean value that shows if correcatable errors can be injected. + * + * bUncorrectableSupported [out]: + * Boolean value that shows if uncorrecatable errors can be injected. + * + * Return values: + * NV_OK on success + * NV_ERR_INVALID_ARGUMENT if the requested location is invalid. + * NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled. + * NV_ERR_NOT_SUPPORTED otherwise + * + * + */ +#define NV208F_CTRL_CMD_FB_ECC_INJECTION_SUPPORTED (0x208f0510) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_PARAMS { + NvU8 location; + NvBool bCorrectableSupported; + NvBool bUncorrectableSupported; +} NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_PARAMS; + +#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC 0:0 +#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC_LTC (0x00000000) +#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC_DRAM (0x00000001) + +/* + * NV208F_CTRL_CMD_FB_ECC_SET_WRITE_KILL + * + * This command sets the write kill for the specified DRAM address. If set, + * writes to the specified address won't update the ECC checkbits. When unset, + * writes the specified address will update the ECC checkbits. + * + * Only one write kill register can be set at a time. Setting a write kill + * will clear all currently set write kills and set the new write kill. + * Calling this ctrl call with setWriteKill = false simply clears all currently + * set write kills. + * + * setWriteKill + * When true, the ECC checkbits for the specified address won't update on + * writes. When false, the ECC checkbits for the specified address will + * revert to normal behavior and update on all writes. + * + * address + * The physical DRAM address to be targeted by the write kill + */ +#define NV208F_CTRL_CMD_FB_ECC_SET_WRITE_KILL (0x208f0511) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS { + NvBool setWriteKill; + NV_DECLARE_ALIGNED(NvU64 address, 8); +} NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS; + +/* + * NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO + * + * physicalAddress + * Physical address to be remapped + * source + * The reason for retirement. Valid values for this parameter are + * from NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_* + * status + * Reason for row remapping failure. Valid values are: + * NV208F_CTRL_FB_REMAP_ROW_STATUS_OK + * No error + * NV208F_CTRL_FB_REMAP_ROW_STATUS_REMAPPING_PENDING + * The remapping is pending + * NV208F_CTRL_FB_REMAP_ROW_STATUS_TABLE_FULL + * Table full + * NV208F_CTRL_FB_REMAP_ROW_STATUS_ALREADY_REMAPPED + * Attempting to remap a reserved row + * NV208F_CTRL_FB_REMAP_ROW_STATUS_INTERNAL_ERROR + * Some other RM failure + */ +typedef struct NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO { + NV_DECLARE_ALIGNED(NvU64 physicalAddress, 8); + NvU8 source; + NvU32 status; +} NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO; + +/* valid values for status */ +#define NV208F_CTRL_FB_REMAP_ROW_STATUS_OK (0x00000000) +#define NV208F_CTRL_FB_REMAP_ROW_STATUS_REMAPPING_PENDING (0x00000001) +#define NV208F_CTRL_FB_REMAP_ROW_STATUS_TABLE_FULL (0x00000002) +#define NV208F_CTRL_FB_REMAP_ROW_STATUS_ALREADY_REMAPPED (0x00000003) +#define NV208F_CTRL_FB_REMAP_ROW_STATUS_INTERNAL_ERROR (0x00000004) + +#define NV208F_CTRL_FB_REMAPPED_ROWS_MAX_ROWS (0x00000200) +/* + * NV208F_CTRL_CMD_FB_REMAP_ROW + * + * This command will write entries to Inforom. During init the entries will be + * read and used to remap a row. + * + * addressList + * This input parameter is an array of NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO + * structures containing information used for row remapping. Valid entries + * are adjacent + * validEntries + * This input parameter specifies the number of valid entries in the + * address array + * numEntriesAdded + * This output parameter specifies how many validEntries were successfully + * added to the Inforom + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_FB_REMAP_ROW (0x208f0512) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_REMAP_ROW_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_REMAP_ROW_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV208F_CTRL_FB_REMAP_ROW_PARAMS { + NV_DECLARE_ALIGNED(NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO addressList[NV208F_CTRL_FB_REMAPPED_ROWS_MAX_ROWS], 8); + NvU32 validEntries; + NvU32 numEntriesAdded; +} NV208F_CTRL_FB_REMAP_ROW_PARAMS; + + +#define NV208F_CTRL_CMD_FB_REVERSE_MAP_RBC_ADDR_TO_PA (0x208f0513) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_REVERSE_MAP_RBC_ADDR_TO_PA_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_REVERSE_MAP_RBC_ADDR_TO_PA_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV208F_CTRL_FB_REVERSE_MAP_RBC_ADDR_TO_PA_PARAMS { + NV_DECLARE_ALIGNED(NvU64 address, 8); + NvU32 rbcAddress; + NvU32 rbcAddressExt; + NvU32 rbcAddressExt2; + NvU32 partition; + NvU32 sublocation; +} NV208F_CTRL_FB_REVERSE_MAP_RBC_ADDR_TO_PA_PARAMS; + +/** + * NV208F_CTRL_CMD_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF + * + * This command will convert a physical address when ECC is on to the physical + * address when ECC is off or vice versa + * + * @params[in] NvU64 inputAddress + * Input physical address + * + * @params[in] NvBool eccOn + * Whether or not input physical address is with ECC on or off + * + * @params[out] NvU64 outputAddress + * Output physical address + */ +#define NV208F_CTRL_CMD_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF (0x208f0514) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV208F_CTRL_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF_PARAMS { + NV_DECLARE_ALIGNED(NvU64 inputAddress, 8); + NvBool eccOn; + NV_DECLARE_ALIGNED(NvU64 outputAddress, 8); +} NV208F_CTRL_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF_PARAMS; + +/* + * NV208F_CTRL_CMD_FB_CLEAR_REMAPPED_ROWS + * + * This command clears remapping entries from the Inforom's row remapping table. + * + * sourceMask + * This is a bit mask of NV2080_CTRL_FB_REMAPPED_ROW_SOURCE. Rows + * remapped from the specified sources will be cleared/removed from the + * Inforom RRL object entries list. + * + * Possbile status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV208F_CTRL_CMD_FB_CLEAR_REMAPPED_ROWS (0x208f0515) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS { + NvU32 sourceMask; +} NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS; + +/* + * NV208F_CTRL_CMD_FB_GET_FLOORSWEPT_FBPA_MASK + * + * This command calculates the floorswept fbpa mask by taking 1/2 HBM + * floorsweeping into account + * + * fbpaMask + * This value of the mask. + * + * Possbile status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV208F_CTRL_CMD_FB_GET_FLOORSWEPT_FBPA_MASK (0x208f0516) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_GET_FLOORSWEPT_FBPA_MASK_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_GET_FLOORSWEPT_FBPA_MASK_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV208F_CTRL_FB_GET_FLOORSWEPT_FBPA_MASK_PARAMS { + NvU32 fbpaMask; +} NV208F_CTRL_FB_GET_FLOORSWEPT_FBPA_MASK_PARAMS; + +/* _ctrl208ffb_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208ffbio.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208ffbio.h new file mode 100644 index 0000000..a523160 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208ffbio.h @@ -0,0 +1,249 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208ffbio.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* + * NV208F_CTRL_CMD_FBIO_SETUP_TRAINING_EXP + * + * This command defines an fbio training experiment for later use. + * + * This command has the form of a 'cmd' operation descriminant + * followed by a union populated with an operand to match the 'cmd'. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_COMMAND + * + */ +#define NV208F_CTRL_CMD_FBIO_SETUP_TRAINING_EXP (0x208f0a03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FBIO_INTERFACE_ID << 8) | NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_PARAMS_MESSAGE_ID" */ + +/* + * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_NULL + * + * This command has no effect when used. + */ +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_NULL 0 + +/* + * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS + * + * This command defines the number of register modification slots to be used + * in the setup phase of the pass/fail training exercise. Using this cmd + * causes any previously defined modification table to be cleared/released. + * The maximum size of the table is defined by + * _SETUP_FBIO_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS__MAX + * Using the value of zero for number of mod slots is valid. "Mod slots" + * are defined below. + * + * Possible status values returned are: + * NV_ERR_INVALID_LIMIT + * if modSlots is > __MAX + * NV_ERR_INSUFFICIENT_RESOURCES + * if we're out of memory setting up the mod slot table + */ +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS 1 +typedef struct NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS_OPERANDS { + NvU32 modSlots; +} NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS_OPERANDS; + +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS__MAX 256 + +/* + * NV208F_CTRL_FBIO_SETUPFBIO_TRAINING_EXP_SET_MOD_SLOT + * + * This command is used to define each individual element of the the sequence + * of operations which will be performed before running the pass/fail training + * exercise. Note that this cmd is multi-cmd (with a null cmd all its own, + * etc). + * + * Possible status values returned are: + * NV_ERR_INVALID_INDEX + * if seq is out of range for previously set SET_NUMBER_OF_MOD_SLOTS + * operation. + * NV_ERR_INVALID_COMMAND + * if cmd isn't recognized + */ +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT 2 + +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_NULL 0 + +/* + * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_SET_REGISTER + * + * This cmd is used to define a register transaction to be applied in + * sequence before running the pass/fail experiment. This is where + * NV_PFB_TRAINING_ADR, NV_PFB_TRAINING_CMD, NV_PFB_TRAINING_DP(i), + * NV_PFB_TRAINING_THRESHOLD and NV_PFB_TRAINING_MASK, etc. should be + * configured before calling back with cmd + * NV208F_CTRL_CMD_FBIO_RUN_TRAINING_EXP. + * + * reg + * This parameter specifies the BAR0 register offset to affect. + * andMask + * orMask + * These parameter specify the RMW values to be used in the following: + * write32(reg, (read32(reg) & andMask) | orMask) + */ +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_SET_REGISTER 1 +typedef struct NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_SET_REGISTER_OPERANDS { + NvU32 reg; + NvU32 andMask; + NvU32 orMask; +} NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_SET_REGISTER_OPERANDS; + +/* + * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_DELAY + * + * This cmd is used to define a delay to be applied in the setup sequence + * before running the pass/fail experiment. + * + * usec + * Specifies delay to be used in microseconds. + */ + +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_DELAY 2 +typedef struct NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_DELAY_OPERANDS { + NvU32 usec; +} NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_DELAY_OPERANDS; + +/* + * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_INIT_LT + * + * This cmd is used to define a point where normal link training initialization + * may be executed in the sequence before running the pass/fail experiment. + * In general, this is not needed since it is done during normal + * initialization, but does allow re-initialization during the sequence. + */ +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_INIT_LT 3 + +/* + * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_RUN_LT + * + * This cmd is used to define a point where normal link training may be + * executed in the sequence before running the pass/fail experiment. + * In general, this is not needed since it is somewhat redundant. + */ +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_RUN_LT 4 + +/* + * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_STOP_SEQ + * + * This cmd is used to define a point where the sequence stops without + * running the pass/fail experiment. + */ +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_STOP_SEQ 5 + + + +typedef struct NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_PARAMS { + NvU32 cmd; + /* C form: NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_OPERANDS op; */ + union { + + NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_SET_REGISTER_OPERANDS setRegister; + + NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_DELAY_OPERANDS delay; + } op; + NvU32 seq; +} NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_PARAMS; + + + +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_PARAMS { + NvU32 cmd; + + /* C form: NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_OPERANDS op; */ + union { + + NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS_OPERANDS setNumberOfModSlots; + + NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_PARAMS setModSlot; + } op; +} NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_PARAMS; + +/* + * NV208F_CTRL_CMD_FBIO_RUN_TRAINING_EXP + * + * This command runs the previously defined experiment and returns status on + * pass/fail. NV_OK is returned in the case of both pass + * and fail. + * + * The risingPasses and fallingPasses outputs represents the results across + * all partitions and bytelanes. Each array entry corresponds to a partition + * and the bits within each member represent the bytelane. So e.g.: + * risingPasses[4] represents the rising pass results for all of partition 4's + * byte lanes. + * + * The partitionsValid bitmask represents the partitions for which the results + * in risingPasses and fallingPasses are valid (not floorswept). + * + * The bytelanesValid bitmask represents the bytelanes for which the results + * are valid (available bytelanes). + * + * The failingDebug[] represent debug data for why (if so) a test fails. + * This is basically NV_PFB_TRAINING_DEBUG(i) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_TIMEOUT + * if hardware doesn't respond to request in a timely manner. + * NV_ERR_INVALID_DATA + * if there was some sort of very weird data corruption issue. + */ +#define NV208F_CTRL_CMD_FBIO_RUN_TRAINING_EXP (0x208f0a04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FBIO_INTERFACE_ID << 8) | NV208F_CTRL_FBIO_RUN_TRAINING_EXP_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FBIO_RUN_TRAINING_EXP_RESULT__SIZE 8 +#define NV208F_CTRL_FBIO_RUN_TRAINING_EXP_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV208F_CTRL_FBIO_RUN_TRAINING_EXP_PARAMS {NvU32 risingPasses[NV208F_CTRL_FBIO_RUN_TRAINING_EXP_RESULT__SIZE]; + NvU32 fallingPasses[NV208F_CTRL_FBIO_RUN_TRAINING_EXP_RESULT__SIZE]; + NvU32 failingDebug[NV208F_CTRL_FBIO_RUN_TRAINING_EXP_RESULT__SIZE]; + NvU32 partitionsValid; + NvU32 bytelanesValid; +} NV208F_CTRL_FBIO_RUN_TRAINING_EXP_PARAMS; + +#define NV208F_CTRL_CMD_FBIO_GET_TRAINING_CAPS (0x208f0a05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FBIO_INTERFACE_ID << 8) | NV208F_CTRL_FBIO_GET_TRAINING_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FBIO_GET_TRAINING_CAPS_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV208F_CTRL_FBIO_GET_TRAINING_CAPS_PARAMS { + NvU32 supported; +} NV208F_CTRL_FBIO_GET_TRAINING_CAPS_PARAMS; + +// _ctrl208ffbio_h_ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208ffifo.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208ffifo.h new file mode 100644 index 0000000..dba64cd --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208ffifo.h @@ -0,0 +1,159 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208ffifo.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* + * NV208F_CTRL_CMD_FIFO_CHECK_ENGINE_CONTEXT + * + * This command checks whether or not engine context exists for a given + * engine for the channel with a given channel ID. This API is intended + * for testing virtual context. For debug only. + * + * hChannel + * The handle to the channel. + * engine + * The engine ID. + * Valid values are: + * NV2080_ENGINE_TYPE_GRAPHICS + * exists + * The output are TRUE or FALSE. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_CHANNEL + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_FIFO_CHECK_ENGINE_CONTEXT (0x208f0401) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FIFO_INTERFACE_ID << 8) | NV208F_CTRL_FIFO_CHECK_ENGINE_CONTEXT_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FIFO_CHECK_ENGINE_CONTEXT_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV208F_CTRL_FIFO_CHECK_ENGINE_CONTEXT_PARAMS { + NvHandle hChannel; + NvU32 engine; + NvBool exists; +} NV208F_CTRL_FIFO_CHECK_ENGINE_CONTEXT_PARAMS; + +/* + * NV208F_CTRL_CMD_FIFO_ENABLE_VIRTUAL_CONTEXT + * + * This command enables virtual context for a given channel (for all engines). + * This API is intended for testing virtual context. For debug only. + * + * hChannel + * The handle to the channel. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_CHANNEL + */ +#define NV208F_CTRL_CMD_FIFO_ENABLE_VIRTUAL_CONTEXT (0x208f0402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FIFO_INTERFACE_ID << 8) | NV208F_CTRL_FIFO_ENABLE_VIRTUAL_CONTEXT_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FIFO_ENABLE_VIRTUAL_CONTEXT_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV208F_CTRL_FIFO_ENABLE_VIRTUAL_CONTEXT_PARAMS { + NvHandle hChannel; +} NV208F_CTRL_FIFO_ENABLE_VIRTUAL_CONTEXT_PARAMS; + +/* + * NV208F_CTRL_CMD_FIFO_GET_CHANNEL_STATE + * + * This command returns the fifo channel state for the given channel. + * This is for testing channel behavior. For debug only. + * + * hChannel + * The handle to the channel + * hClient + * The handle to the client + * bound + * The channel has been bound to channel RAM + * enabled + * The channel is able to run. + * scheduled + * The channel has been scheduled to run. + * cpuMap + * There is a cpu mapping available to this channel. + * contention + * The virtual channel is under contention + * runlistSet + * A runlist has been chosen for this channel + * deferRC + * An RC error has occurred, but recovery will occur at channel teardown. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_CHANNEL + */ +#define NV208F_CTRL_CMD_FIFO_GET_CHANNEL_STATE (0x208f0403) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FIFO_INTERFACE_ID << 8) | NV208F_CTRL_FIFO_GET_CHANNEL_STATE_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FIFO_GET_CHANNEL_STATE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV208F_CTRL_FIFO_GET_CHANNEL_STATE_PARAMS { + NvHandle hChannel; + NvHandle hClient; + NvBool bBound; + NvBool bEnabled; + NvBool bScheduled; + NvBool bCpuMap; + NvBool bContention; + NvBool bRunlistSet; + NvBool bDeferRC; +} NV208F_CTRL_FIFO_GET_CHANNEL_STATE_PARAMS; + +/* + * NV208F_CTRL_CMD_FIFO_GET_CONTIG_RUNLIST_POOL + * + * This command returns the location of the pool runlists are allocated from for + * WPR testing. + * For debug only. + * + * physAddr [out] + * Physical address of the pool + * + * size [out] + * Size in bytes of the pool + * + */ +#define NV208F_CTRL_CMD_FIFO_GET_CONTIG_RUNLIST_POOL (0x208f0404) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FIFO_INTERFACE_ID << 8) | NV208F_CTRL_FIFO_GET_CONTIG_RUNLIST_POOL_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FIFO_GET_CONTIG_RUNLIST_POOL_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV208F_CTRL_FIFO_GET_CONTIG_RUNLIST_POOL_PARAMS { + NV_DECLARE_ALIGNED(NvU64 physAddr, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); +} NV208F_CTRL_FIFO_GET_CONTIG_RUNLIST_POOL_PARAMS; + +/* _ctrl208ffifo_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h new file mode 100644 index 0000000..d473f11 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h @@ -0,0 +1,161 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fgpu.finn +// + +#include "ctrl/ctrl2080/ctrl2080gr.h" /* 208F is partially derivative of 2080 */ +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* + * NV208F_CTRL_CMD_GPU_GET_RAM_SVOP_VALUES + * + * This command can be used to get the RAM SVOP values. + * + * sp + * This field outputs RAM_SVOP_SP + * rg + * This field outputs RAM_SVOP_REG + * pdp + * This field outputs RAM_SVOP_PDP + * dp + * This field outputs RAM_SVOP_DP + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV208F_CTRL_CMD_GPU_GET_RAM_SVOP_VALUES (0x208f1101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | 0x1" */ + +typedef struct NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS { + NvU32 sp; + NvU32 rg; + NvU32 pdp; + NvU32 dp; +} NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS; + +/* + * NV208F_CTRL_CMD_GPU_SET_RAM_SVOP_VALUES + * + * This command can be used to set the RAM SVOP values. + * + * sp + * Input for RAM_SVOP_SP + * rg + * Input for RAM_SVOP_REG + * pdp + * Input for RAM_SVOP_PDP + * dp + * Input for RAM_SVOP_DP + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV208F_CTRL_CMD_GPU_SET_RAM_SVOP_VALUES (0x208f1102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | 0x2" */ + + + +/* + * NV208F_CTRL_CMD_GPU_VERIFY_INFOROM + * + * This command can be used by clients to determine if an InfoROM + * with a valid image is present. If the SKU in question does + * not feature an InfoROM, the NV_ERR_NOT_SUPPORTED + * error is returned. Else the RM attempts to read the ROM object + * and any objects listed in the ROM object. The checksum of + * each object read is verified. If all checksums are valid, the + * RM will report the InfoROM as being valid. If image is valid then + * RM will return a checksum for all of the dynamically configurable + * data in InfoROM. This checksum is expected to be same for all the + * boards with an identical InfoROM version and similarly configured. + * + * result + * The result of the InfoROM verification attempt. Possible + * values are: + * NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULTS_NONE + * This value indicates that a validation couldn't be done + * due to some software/OS related error. + * NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULTS_IO_ERROR + * This value indicates that a validation couldn't be done + * due to some IO error. + * NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULTS_VALID + * This value indicates that all InfoROM objects have valid + * checksum. + * NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULTS_INVALID + * This value indicates that some InfoROM objects have invalid + * checksum. + * checksum + * Checksum for all of the dynamically configurable data + * in InfoROM for e.g. PWR and CFG objects. + * + * NOTE: For the result values to be valid, return status should be: + * NV_OK + * + * Possible return status values: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV208F_CTRL_CMD_GPU_VERIFY_INFOROM (0x208f1105) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | NV208F_CTRL_GPU_VERIFY_INFOROM_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_GPU_VERIFY_INFOROM_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV208F_CTRL_GPU_VERIFY_INFOROM_PARAMS { + NvU32 result; + NvU32 checksum; +} NV208F_CTRL_GPU_VERIFY_INFOROM_PARAMS; + +/* valid result values */ +#define NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULT_NONE (0x00000000) +#define NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULT_IO_ERROR (0x00000001) +#define NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULT_VALID (0x00000002) +#define NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULT_INVALID (0x00000003) + +/* + * NV208F_CTRL_CMD_GPU_DISABLE_ECC_INFOROM_REPORTING + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + + + +#define NV208F_CTRL_CMD_GPU_DISABLE_ECC_INFOROM_REPORTING (0x208f1107) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | 0x7" */ + + + +/* _ctrl208fgpu_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fgr.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fgr.h new file mode 100644 index 0000000..357ac1f --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fgr.h @@ -0,0 +1,109 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fgr.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +#include "ctrl/ctrl2080/ctrl2080gr.h" + + + +/* + * NV208F_CTRL_CMD_GR_ECC_INJECT_ERROR + * + * Control command to inject a gr ecc error + * + * Parameters: + * + * location + * location index + * sublocation + * sublocation index + * unit + * unit to inject error into + * errorType + * SBE or DBE + * grRouteInfo + * Routing info for SMC + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_GR_ECC_INJECT_ERROR (0x208f1203) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GR_INTERFACE_ID << 8) | NV208F_CTRL_GR_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_GR_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV208F_CTRL_GR_ECC_INJECT_ERROR_PARAMS { + NvU32 location; + NvU32 sublocation; + NvU8 unit; + NvU8 errorType; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV208F_CTRL_GR_ECC_INJECT_ERROR_PARAMS; + + + +/* + * NV208F_CTRL_CMD_GR_ECC_INJECTION_SUPPORTED + * + * Reports if error injection is supported for a given HW unit + * + * unit [in]: + * The ECC protected unit for which ECC injection support is being checked. + * + * bCorrectableSupported [out]: + * Boolean value that shows if correcatable errors can be injected. + * + * bUncorrectableSupported [out]: + * Boolean value that shows if uncorrecatable errors can be injected. + * + * Return values: + * NV_OK on success + * NV_ERR_INVALID_ARGUMENT if the requested unit is invalid. + * NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled. + * NV_ERR_NOT_SUPPORTED otherwise + * + * + */ +#define NV208F_CTRL_CMD_GR_ECC_INJECTION_SUPPORTED (0x208f1204) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GR_INTERFACE_ID << 8) | NV208F_CTRL_GR_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_GR_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV208F_CTRL_GR_ECC_INJECTION_SUPPORTED_PARAMS { + NvU8 unit; + NvBool bCorrectableSupported; + NvBool bUncorrectableSupported; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV208F_CTRL_GR_ECC_INJECTION_SUPPORTED_PARAMS; + +/* _ctrl208fgr_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h new file mode 100644 index 0000000..2b298e6 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h @@ -0,0 +1,128 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fmmu.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* + * NV208F_CTRL_CMD_MMU_ECC_INJECT_ERROR + * + * This ctrl call injects MMU ECC errors. Please see the confluence + * page "ECC" for more information on ECC and ECC injection: + * + * Parameters: + * + * location + * Only used for HSHUBMMU. + * + * sublocation + * Only used for HSHUBMMU. + * + * unit + * Specifies the MMU HW unit where the injection will occur. + * + * errorType + * Specifies whether the injected error will be correctable or uncorrectable. + * Correctable errors have no effect on running programs while uncorrectable + * errors will cause all channels to be torn down. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_MMU_ECC_INJECT_ERROR (0x208f0b01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID << 8) | NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS { + NvU32 location; + NvU32 sublocation; + NvU8 unit; + NvU8 errorType; +} NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS; + + + +/* + * NV208F_CTRL_CMD_MMU_ECC_INJECTION_SUPPORTED + * + * Reports if error injection is supported for a given HW unit + * + * unit [in]: + * The ECC protected unit for which ECC injection support is being checked. + * + * bCorrectableSupported [out]: + * Boolean value that shows if correcatable errors can be injected. + * + * bUncorrectableSupported [out]: + * Boolean value that shows if uncorrecatable errors can be injected. + * + * Return values: + * NV_OK on success + * NV_ERR_INVALID_ARGUMENT if the requested location is invalid. + * NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled. + * NV_ERR_NOT_SUPPORTED otherwise + * + */ +#define NV208F_CTRL_CMD_MMU_ECC_INJECTION_SUPPORTED (0x208f0b02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID << 8) | NV208F_CTRL_MMU_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */ + + + +#define NV208F_CTRL_MMU_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV208F_CTRL_MMU_ECC_INJECTION_SUPPORTED_PARAMS { + NvU8 unit; + NvBool bCorrectableSupported; + NvBool bUncorrectableSupported; +} NV208F_CTRL_MMU_ECC_INJECTION_SUPPORTED_PARAMS; + +/* + * NV208F_CTRL_CMD_MMU_GET_NUM_HSHUBMMUS + * + * Returns the number of ECC Capable HSHUBMMUS. + * + * numHshubmmus [out] + * Number of Hshubmmus + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV208F_CTRL_CMD_MMU_GET_NUM_HSHUBMMUS (0x208f0b03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID << 8) | NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS { + NvU32 numHshubmmus; +} NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS; + +/* _ctrl208fmmu_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fpmgr.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fpmgr.h new file mode 100644 index 0000000..d7ea299 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fpmgr.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fpmgr.finn +// + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fpower.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fpower.h new file mode 100644 index 0000000..e225c7b --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl208f/ctrl208fpower.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fpower.finn +// + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl30f1.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl30f1.h new file mode 100644 index 0000000..fdfa8fb --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl30f1.h @@ -0,0 +1,1493 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl30f1.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV30_GSYNC_CTRL control commands and parameters */ + +#define NV30F1_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x30F1, NV30F1_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NV30F1_CTRL_RESERVED (0x00) +#define NV30F1_CTRL_GSYNC (0x01) + +/* + * NV30F1_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV30F1_CTRL_CMD_NULL (0x30f10000) /* finn: Evaluated from "(FINN_NV30_GSYNC_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* NV30F1_CTRL_GSYNC + * + * Gsync board access/control functionality. + * + */ + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_VERSION + * + * This command will get the current gsync api version info. + * + * version + * The api's major version. Does not change often. + * + * revision + * The api's minor version. + * Bumped with each change, no matter how minor. + * + * Possible status values returned are: + * NV_OK + * + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_VERSION (0x30f10101) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS { + NvU32 version; + NvU32 revision; +} NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS; + +#define NV30F1_CTRL_GSYNC_API_VER 1 +#define NV30F1_CTRL_GSYNC_API_REV 0 + +/* + * NV30F1_CTRL_GSYNC api + * + * The gsync interface provides access to gsync devices in the system. + * + * There are commands: + * NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SIGNALS + * Status on input sync signals. + * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_PARAMS + * Get gsync parameters. + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_PARAMS + * Get gsync parameters. + * NV30F1_CTRL_CMD_GSYNC_GET_INFO_CAPS + * Get basic info about the device and its connected displays + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SYNC + * Enable frame sync. + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_UNSYNC + * Disable frame sync. + * NV30F1_CTRL_CMD_GSYNC_GET_STATUS + * Get status info relevant for the control panel + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_TESTING + * Test signal enabling/disabling + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_WATCHDOG + * Control the gsync watchdog + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_INTERLACE_MODE + * Set the interlace mode + * + */ + + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SIGNALS + * + * This command returns information associated with incoming signals to the + * gsync device. + * + * RJ45 + * This parameter contains the signal information for each of the two RJ45 + * ports on the gsync device. A value of ~0 indicates that a signal is + * detected, but no rate information is available. Anything else is a rate + * in units of 10e-4 Hz. + * house + * This parameter contains the signal information for the house sync signal + * (i.e. the bnc port). A value of 0 means that no signal is present. A value + * of ~0 indicates that a signal is detected, but no rate information is + * available. Anything else is a rate in units of 10e-4 Hz. + * rate + * A mask representing signals for which we would like rate information (if + * available). + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + * + */ + +#define NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SIGNALS (0x30f10102) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS { + NvU32 RJ45[2]; + NvU32 house; + NvU32 rate; +} NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS; + +/* + * rate values + * + */ + +#define NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_RJ45_0 (0x00000001) +#define NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_RJ45_1 (0x00000002) +#define NV30F1_CTRL_GSYNC_GET_SIGNALS_HOUSE (0x00000004) + + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_PARAMS + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_PARAMS + * + * These commands respectively return and set state related to the operation + * of the gsync device. + * + * which + * This value is a mask set by the client representing which parameters are + * to be updated. In the case of a GET command, these parameters will + * be used to change the state of the hardware. For both a GET + * command and a SET command, the hardware state will be returned by + * the RM in the respective parameter. All other parameters are untouched. + * syncPolarity + * This parameter specifies which edge of the house sync signal to sync with. + * videoMode + * This parameter specifies which video mode to use to decode the house sync + * signal. + * nSync + * This parameter specifies the number of pulses to wait between frame lock + * signal generation. 0 indicates that every incomming pulse should result in + * a frame lock sync pulse being generated (i.e. the input and output rate + * matches). + * syncSkew + * This parameter specifies the time delay between the frame sync signal and + * the GPUs signal in units of 0.977 us. Maximum value for SyncSkew is defined + * in respective header files of gsync boards. e.g. For P2060 board value + * is defined in drivers/resman/kernel/inc/dacp2060.h + * syncStartDelay + * In master mode, the amount of time to wait before generating the first + * sync pulse in units of 7.81 us, max 512 ms (i.e 65535 units). + * useHouseSync + * When a house sync signal is detected, this parameter indicates that it + * should be used as the reference to generate the frame sync signal. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ + +#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_PARAMS (0x30f10103) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_PARAMS (0x30f10104) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS { + NvU32 which; + NvU32 syncPolarity; + NvU32 syncVideoMode; + NvU32 nSync; + NvU32 syncSkew; + NvU32 syncStartDelay; + NvU32 useHouseSync; +} NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS; +#define NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS_MESSAGE_ID (0x4U) + +typedef NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS; + +/* + * which values + * + */ + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY 0x0001 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE 0x0002 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC 0x0004 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW 0x0008 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY 0x0010 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE 0x0020 + +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_POLARITY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE +#define NV30F1_CTRL_GSYNC_GET_CONTROL_NSYNC NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_SKEW NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_START_DELAY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_USE_HOUSE NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE + +/* + * syncPolarity values + * + */ + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_RISING_EDGE 0 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_FALLING_EDGE 1 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_BOTH_EDGES 2 + +/* + * syncVideoMode values + * Video_Mode_Composite is valid for P2060 only. + * + */ + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE 0 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL 1 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM 2 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV 3 + +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NONE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_TTL NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NTSCPALSECAM NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_HDTV NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_COMPOSITE 4 + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_CAPS + * + * This command returns the capabilities of this gsync device. + * + * revId + * This parameter is set by the RM to indicate the combined + * FPGA revision (low 4 bits) and board ID (high 4 bits). + * + * boardId + * This parameter is set by the RM to indicate the board ID, + * allowing disambiguation of P2060 and so forth. + * + * minRevRequired + * This parameter is set by the RM to indicate the minimum + * Qsync FPGA revision required for a specific CHIP Familiy + * + * isFirmwareRevMismatch + * This parameter is set to TRUE by RM when the Qsync Firmware + * Revision is incompatibled with the connected GPU chip family. + * + * revision + * This parameter is set by the RM to indicate the device revision, + * also known as major version. + * + * extendedRevision + * This parameter is set by the RM to indicate the device extended + * revision, also known as minor version. + * + * capFlags + * This parameter is set by the RM to indicate capabilities of + * the board, preventing the client from needing to keep track + * of the feature lists supported by each revision of each board. + * + * maxSyncSkew + * This parameter returns that maximum units of sync skew the + * board supports. The value prgrammed into the board has to be + * between 0 and maxSyncSkew, inclusive. The value of each unit + * can be learned from the syncSkewResolution parameter. + * + * syncSkewResolution + * This parameter returns the number of nanoseconds that one unit + * of sync skew corresponds to. + * + * maxStartDelay + * This parameter returns that maximum units of sync start delay + * the board supports. The value prgrammed into the board has to be + * between 0 and maxStartDelay, inclusive. The value of each unit + * can be learned from the startDelayResolution parameter. + * + * startDelayResolution + * This parameter returns the number of nanoseconds that one unit + * of sync start delay corresponds to. + * + * maxSyncInterval + * This parameter returns the maximum duration of house sync interval + * between frame lock sync cycle that the board supports. The value + * programmed into the board has to be between 0 and maxSyncInterval, + * inclusive. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV30F1_CTRL_CMD_GSYNC_GET_CAPS (0x30f10105) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS { + NvU32 revId; + NvU32 boardId; + NvU32 minRevRequired; + NvBool isFirmwareRevMismatch; + NvU32 revision; + NvU32 extendedRevision; + NvU32 capFlags; + NvU32 maxSyncSkew; + NvU32 syncSkewResolution; + NvU32 maxStartDelay; + NvU32 startDelayResolution; + NvU32 maxSyncInterval; +} NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS; + +#define NV30F1_CTRL_GSYNC_GET_CAPS_BOARD_ID_P2060 (0x00002060) +#define NV30F1_CTRL_GSYNC_GET_CAPS_BOARD_ID_P2061 (0x00002061) + +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_FREQ_ACCURACY_2DPS (0x00000001) +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_FREQ_ACCURACY_3DPS (0x00000002) +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_FREQ_ACCURACY_4DPS (0x00000004) + +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_NEED_MASTER_BARRIER_WAR (0x00000010) + +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_SYNC_LOCK_EVENT (0x10000000) +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_HOUSE_SYNC_EVENT (0x20000000) +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_FRAME_COUNT_EVENT (0x40000000) + +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_ONLY_PRIMARY_CONNECTOR_EVENT (0x01000000) +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_ALL_CONNECTOR_EVENT (0x02000000) + +// For P2060, clients can only request for video modes at BNC connector +// e.g. NO HS, TTL and Composite etc. +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_ONLY_GET_VIDEO_MODE (0x00100000) + +/* + * NV30F1_CTRL_CMD_GET_GSYNC_GPU_TOPOLOGY + * + * This command returns the list of GPU IDs connected with the associated + * gsync device. + * + * gpus + * This array is set by RM to contain the gpu connection information + * for gpus attached to the gsync device. Valid entries are contiguous, + * beginning with the first entry in the list. The elements of this array contain + * the following fields: + * gpuId + * This field contains the ID of the connected GPU. If the entry in the + * table is invalid, this fields contains NV30F1_CTRL_GPU_INVALID_ID. + * connector + * This field indicates which connector on the device the GPU is connected + * to (i.e. the primary or secondary connector), if any. + * proxyGpuId + * If the 'connector' field indicates that the GPU is not connected to + * a G-Sync device directly, then this field contains the ID of the + * GPU that acts as a proxy, i.e. the GPU to which this GPU should be + * a RasterLock slave. + * connectorCount + * This parameter indicates the number of GPU connectors available on + * the gsync device. The connector count of the gsync device may be + * less than NV30F1_CTRL_MAX_GPUS_PER_GSYNC. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV30F1_CTRL_CMD_GET_GSYNC_GPU_TOPOLOGY (0x30f10106) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_MAX_GPUS_PER_GSYNC 4 +#define NV30F1_CTRL_GPU_INVALID_ID (0xffffffff) + +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS { + struct { + NvU32 gpuId; + NvU32 connector; + NvU32 proxyGpuId; + } gpus[NV30F1_CTRL_MAX_GPUS_PER_GSYNC]; + NvU32 connectorCount; +} NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS; + +/* + * connector values + * + */ +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_ONE 1 +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_TWO 2 +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_THREE 3 +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_FOUR 4 + +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_NONE 0 +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PRIMARY NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_ONE +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_SECONDARY NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_TWO + + + + +/* + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SYNC + * + * This command enables frame sync on displays. + * + * gpuId + * The parameter is set by the client to indicate the gpuId on which + * frame lock will be enabled. + * master + * This parameter is set by the client to specify whether this/these + * displays should be set as the master or as slaves. If this is a GET + * and displays is not 0, this will be set by the RM to indicate if + * the display can be the master. + * displays + * This is a device mask set by the client to indicate which display(s) + * are to be synched. Note that only one display may be set as master. + * If this is a GET, this set by the client to indicate which display + * is to be queried. If the display cannot be synched to this device, + * the RM will overwrite the mask with a 0. + * validateExternal + * This parameter is set by the client to tell the RM to validate the + * presence of an external sync source when enabling a master. + * refresh + * This parameter is set by the client to indicate the desired refresh rate + * The value is in 0.0001 Hertz (i.e. it has been multiplied by 10000). + * configFlags + * contains flags for specific options. So far only + * NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_CONFIG_FLAGS_KEEP_MASTER_SWAPBARRIER_DISABLED + * is supported which allows the caller to prevent the rm code to automatically + * enable the swapbarrier on framelock masters on fpga revisions <= 5. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SYNC (0x30f10110) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SYNC (0x30f10111) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS_MESSAGE_ID" */ + +// If set the swapbarrier is not enable automatically when enablign a framelock master on fpga revs <= 5. +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_CONFIG_FLAGS_KEEP_MASTER_SWAPBARRIER_DISABLED (0x00000001) + +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS { + NvU32 gpuId; + NvU32 master; + NvU32 displays; + NvU32 validateExternal; + NvU32 refresh; + NvU32 configFlags; +} NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS; +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS_MESSAGE_ID (0x11U) + +typedef NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS; + +/* + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_UNSYNC + * + * This command disables frame sync on displays + * + * gpuId + * The parameter is set by the client to indicate the gpuId on which + * frame lock will be disabled. + * master + * This parameter is set by the client to specify whether this/these + * display(s) to be unset is a master/are slaves. + * displays + * This is a device mask set by the client to indicate which display(s) + * are to be unsynched. + * retainMaster + * Retain the designation as master, but unsync the displays. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + */ +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_UNSYNC (0x30f10112) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS { + NvU32 gpuId; + NvU32 master; + NvU32 displays; + NvU32 retainMaster; +} NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS; + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SYNC + * + * This command gets the sync state for the gpus attached to the + * framelock device. Note that the frame lock device only has + * knowledge of sync status at the gpu level, not the display + * device level. + * + * gpuId + * The parameter is set by the client to indicate which gpuId is to be + * queried. + * bTiming + * This parameter is set by the RM to indicate that timing on the GPU is + * in sync with the master sync signal. + * bStereoSync + * This parameter is set by the RM to indicate whether the phase of the + * timing signal coming from the GPU is the same as the phase of the + * master sync signal. + * bSyncReady + * This parameter is set by the RM to indicate if a sync signal has + * been detected. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ + +#define NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SYNC (0x30f10113) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS { + NvU32 gpuId; + NvU32 bTiming; + NvU32 bStereoSync; + NvU32 bSyncReady; +} NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS; + + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_STATUS + * + * This command gets status information for the frame lock device + * relevant to a control panel. + * + * which + * This is a mask set by the client describing which of the other + * parameters we should collect status information for. + * bLeadingEdge + * This parameter is set by the RM to indicate that the gsync device is + * set to sync to the leading edge of a house sync signal. Note that + * this does not mean that house sync is the signal source. + * bFallingEdge + * This parameter is set by the RM to indicate that the gsync device is + * set to sync to the falling edge of a house sync signal. Note that + * this does not mean that house sync is the signal source. + * syncDelay + * This parameter is set by the RM to indicate the sync delay in + * microseconds, + * refresh + * This parameter is set by the RM to indicate the rate of frame sync pulse in + * 0.0001 Hertz (i.e. it has been multiplied by 10000). This is not the refresh + * rate of display device. This is same as incoming house sync rate if + * framelocked to an external house sync signal. Otherwise, this is same + * as the refresh rate of the master display device. + * houseSyncIncomming + * This parameter is set by the RM to indicate the rate of an incomming + * house sync signal in 0.0001 Hertz (i.e. it has been multiplied by 10000). + * syncInterval + * This parameter is set by the RM to indicate the number of incoming + * sync pulses to wait before the generation of the frame sync pulse. + * bSyncReady + * This paramater is set by the RM to indicate if a sync signal has + * been detected (this parameter is also available from the + * NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SYNC method). + * bSwapReady + * This paramater is set by the RM to indicate if the hardware is + * ready to swap. + * bHouseSync + * This parameter is set by the RM to indicate that a house sync signal + * should be used as the source signal if it is available. + * bPort0Input + * This parameter is set by the RM to indicate that RJ45 port 0 is + * configured as an input. + * bPort1Input + * This parameter is set by the RM to indicate that RJ45 port 1 is + * configured as an input + * bPort0Ehternet + * This parameter is set by the RM to indicate that RJ45 port 0 has + * been connected to an ethernet hub (this is not the right thing to do). + * bPort1Ehternet + * This parameter is set by the RM to indicate that RJ45 port 1 has + * been connected to an ethernet hub (this is not the right thing to do). + * universalFrameCount + * This parameter is set by the RM to indicate the value of the + * Universal frame counter. + * bInternalSlave + * This parameter is set by the RM to indicate that a p2061 has been + * configured as internal slave. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_STATUS (0x30f10114) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS { + NvU32 which; + NvU32 bLeadingEdge; + NvU32 bFallingEdge; + NvU32 syncDelay; + NvU32 refresh; + NvU32 houseSyncIncoming; + NvU32 syncInterval; + NvU32 bSyncReady; + NvU32 bSwapReady; + NvU32 bHouseSync; + NvU32 bPort0Input; + NvU32 bPort1Input; + NvU32 bPort0Ethernet; + NvU32 bPort1Ethernet; + NvU32 universalFrameCount; + NvU32 bInternalSlave; +} NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS; + +/* + * which values + * + */ + +#define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_POLARITY (0x00000001) +#define NV30F1_CTRL_GSYNC_GET_STATUS_LEADING_EDGE (0x00000001) +#define NV30F1_CTRL_GSYNC_GET_STATUS_FALLING_EDGE (0x00000001) +#define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_DELAY (0x00000002) +#define NV30F1_CTRL_GSYNC_GET_STATUS_REFRESH (0x00000004) +#define NV30F1_CTRL_GSYNC_GET_STATUS_HOUSE_SYNC_INCOMING (0x00000008) +#define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_INTERVAL (0x00000010) +#define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_READY (0x00000020) +#define NV30F1_CTRL_GSYNC_GET_STATUS_SWAP_READY (0x00000040) +#define NV30F1_CTRL_GSYNC_GET_STATUS_TIMING (0x00000080) +#define NV30F1_CTRL_GSYNC_GET_STATUS_STEREO_SYNC (0x00000100) +#define NV30F1_CTRL_GSYNC_GET_STATUS_HOUSE_SYNC (0x00000200) +#define NV30F1_CTRL_GSYNC_GET_STATUS_PORT_INPUT (0x00000400) +#define NV30F1_CTRL_GSYNC_GET_STATUS_PORT0_INPUT (0x00000400) +#define NV30F1_CTRL_GSYNC_GET_STATUS_PORT1_INPUT (0x00000400) +#define NV30F1_CTRL_GSYNC_GET_STATUS_PORT_ETHERNET (0x00000800) +#define NV30F1_CTRL_GSYNC_GET_STATUS_PORT0_ETHERNET (0x00000800) +#define NV30F1_CTRL_GSYNC_GET_STATUS_PORT1_ETHERNET (0x00000800) +#define NV30F1_CTRL_GSYNC_GET_STATUS_UNIVERSAL_FRAME_COUNT (0x00001000) +#define NV30F1_CTRL_GSYNC_GET_STATUS_INTERNAL_SLAVE (0x00002000) + +/* + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_TESTING + * + * This command controls the test signal on the gsync device. + * + * bEmitTestSignal + * This parameter is set by the client to emit or stop emitting the test + * signal. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_TESTING (0x30f10120) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_TESTING (0x30f10121) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS_MESSAGE_ID (0x21U) + +typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS { + NvU32 bEmitTestSignal; +} NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS; +#define NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS_MESSAGE_ID (0x20U) + +typedef NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS; + +/* + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_WATCHDOG + * + * This command enables and disables the gsync watchdog + * + * enable + * This parameter is set by the client to enable or disable the + * gsync watchdog. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + */ +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_WATCHDOG (0x30f10130) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS_MESSAGE_ID (0x30U) + +typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS { + NvU32 enable; +} NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS; + + +/* + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_INTERLACE_MODE + * + * This command enables or disables interlace mode. + * + * enable + * This parameter is set by the client to enable or disable + * interlace mode + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_INTERLACE_MODE (0x30f10140) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_INTERLACE_MODE (0x30f10141) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID (0x41U) + +typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS { + NvU32 enable; +} NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS; +#define NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID (0x40U) + +typedef NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS; + +/* + * + * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SWAP_BARRIER + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SWAP_BARRIER + * + * These commands enables or disables the swap barrier + * connection between a GPU and the rest of the gsync + * network + * + * gpuId + * The parameter is set by the client to indicate which gpuId is to be + * queried. + * enable + * In a set command, this parameter is set by the client to + * indicate if the barrier should be enabled (i.e. connected + * to the rest of the network) or disabled (disconnected). + * In both a set and a get command, if successful, the RM + * uses this parameter to return the current (i.e. post-set) + * value. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SWAP_BARRIER (0x30f10150) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SWAP_BARRIER (0x30f10151) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID (0x51U) + +typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS { + NvU32 gpuId; + NvBool enable; +} NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS; +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID (0x50U) + +typedef NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS; + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW + * + * This command allow clients to obtain time period for which SwapLock window will + * remain HIGH for GSYNC III (P2060) i.e. TswapRdyHi. RM clients will use this value + * for programming SWAP_LOCKOUT_START on all heads of GPU connected to P2060. + * + * tSwapRdyHi + * RM will return swap lock window High time period in this variable. By default + * tSwapRdyHi is 250 micro seconds. RM also provide regkey to change this value. + * tSwapRdyHi also used by RM to configure value of LSR_MIN_TIME while programming + * swap barrier. + * Client should consider tSwapRdyHi only for Gsync III (P2060) network. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW (0x30f10153) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS_MESSAGE_ID (0x53U) + +typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS { + NvU32 tSwapRdyHi; +} NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS; + + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_OPTIMIZED_TIMING + * + * This command allows the client to obtain suggested + * adjustments to vertical and horizontal timing values + * that will improve the ability of gsync to lock. + * + * gpuId + * This parameter is set by the client to indicate the + * gpuId of the GPU to which the display to be optimized + * is attached. + * display + * This parameter is not used by RM currently. + * Clients can ignore this parameter. Note that this + * parameter will be removed in future. + * output + * This parameter is set by the client to indicate the + * output resource type of the display to be optimized. + * For example, CRTs use DAC output, while DFPs use SOR + * (Serial Output Resource) type. + * protocol + * This parameter is set by the client to indicate the + * data protocol of output resource. For DAC displays, + * the format of the standard mode most closely matching + * the desired mode is used. For SOR display devices, + * the LVDS/TMDS/etc format is the protocol. + * structure + * This parameter is set by the client to indicate the + * raster structure of the mode, either progressive or + * interlaced. Diagrams of the raster structures are + * provided below. + * adjust + * This parameter is set by the client to specify which + * of the timing values, other than hTotal and vTotal, + * may be adjusted during optimization. + * If the client does not obtain instructions from the + * user about where adjustments should be applied, safe + * default values for progressive/interlaced modes are + * provided below. + * hTotal + * This parameter is set by the client to specify the + * initial Horizontal Pixel Total, from which the + * RM will begin optimizing. The RM also uses the + * parameter to return the optimized value. + * vTotal + * This parameter is set by the client to specify the + * initial Vertical Pixel Total, from which the + * RM will begin optimizing. The RM also uses the + * parameter to return the optimized value. + * hBlankStart + * This parameter is set by the client to specify the + * initial Horizontal Blanking Start, from which the + * RM will begin optimizing. The RM also uses the + * parameter to return the optimized value. + * vBlankStart + * This parameter is set by the client to specify the + * initial Vertical Blanking Start, from which the + * RM will begin optimizing. The RM also uses the + * parameter to return the optimized value. + * hBlankEnd + * This parameter is set by the client to specify the + * initial Horizontal Blanking End, from which the + * RM will begin optimizing. The RM also uses the + * parameter to return the optimized value. + * vBlankEnd + * This parameter is set by the client to specify the + * initial Vertical Blanking End, from which the + * RM will begin optimizing. The RM also uses the + * parameter to return the optimized value. + * vInterlacedBlankStart + * This parameter is set by the client to specify the + * initial Interlaced Vertical Blanking Start, from + * which the RM will begin optimizing. The RM will + * ignore this parameter for non-interlaced modes, as + * it has no meaning in those modes. In modes where + * it is meaningful, the RM also uses the parameter + * to return the optimized value. + * vInterlacedBlankEnd + * This parameter is set by the client to specify the + * initial Interlaced Vertical Blanking End, from + * which the RM will begin optimizing. The RM will + * ignore this parameter for non-interlaced modes, as + * it has no meaning in those modes. In modes where + * it is meaningful, the RM also uses the parameter + * to return the optimized value. + * hSyncEnd + * This parameter is set by the client to specify the + * initial Horizontal Raster Sync End, from which the + * RM will begin optimizing. The RM also uses the + * parameter to return the optimized value. + * vSyncEnd + * This parameter is set by the client to specify the + * initial Vertical Raster Sync End, from which the + * RM will begin optimizing. The RM also uses the + * parameter to return the optimized value. + * hDeltaStep + * This parameter is set by the client to specify the + * increments by which the Horizontal Pixel Total may + * be adjusted by the RM, during optimization. + * If the client does not obtain a custom value for + * this parameter from the user, setting all four of + * hDeltaStep, vDeltaStep, hDeltaMax, and vDeltaMax + * to zero will result in a safe default for all four. + * vDeltaStep + * This parameter is set by the client to specify the + * increments by which the vertical timings of each + * frame (in interlaced modes, each field) may be + * adjusted by the RM, during optimization. + * In interlaced modes, the adjustments to vTotal, + * vInterlacedBlankStart, and vInterlacedBlankEnd may + * be in increments of vDeltaStep or twice vDeltaStep, + * depending on where adjustments are made. + * In progressive modes, the adjustment to the vTotal + * will simply be in increments of vDeltaStep. + * If the client does not obtain a custom value for + * this parameter from the user, setting all four of + * hDeltaStep, vDeltaStep, hDeltaMax, and vDeltaMax + * to zero will result in a safe default for all four. + * hDeltaMax + * This parameter is set by the client to specify the + * maximum amount that the Horizontal Pixel Total may + * be adjusted by the RM, during optimization. + * If the client does not obtain a custom value for + * this parameter from the user, setting all four of + * hDeltaStep, vDeltaStep, hDeltaMax, and vDeltaMax + * to zero will result in a safe default for all four. + * vDeltaMax + * This parameter is set by the client to specify the + * maximum amount that vertical timings of each frame + * (in interlaced modes, each field) may be adjusted + * by the RM, during optimization. + * In interlaced modes, the adjustments to vTotal, + * vInterlacedBlankStart, and vInterlacedBlankEnd may + * be up to twice vDeltaMax. + * In progressive modes, the adjustment to the vTotal + * may simply be up to vDeltaMax. + * If the client does not obtain a custom value for + * this parameter from the user, setting all four of + * hDeltaStep, vDeltaStep, hDeltaMax, and vDeltaMax + * to zero will result in a safe default for all four. + * refreshX10K + * This parameter is set by the client to specify the + * desired refresh rate, multiplied by 10000. This + * allows refresh rate to be set in units of 0.0001 Hz. + * For example, a 59.94 Hz rate would be set as 599400. + * The client can alternatively specify a the + * pixelClockHz parameter (if the passed in refreshX10K + * parameter is set to 0, the pixelClockHz parameter + * will be used). + * pixelClockHz + * This parameter is set by the client to specify the + * desired pixel clock frequency in units of Hz. The + * client can alternatively specify the refreshX10K parameter. + * This parameter is returned by the RM to report the + * optimal pixel clock to use with the adjusted mode, + * in units of Hz. + * + * Progressive Raster Structure + * + * hSyncEnd hTotal + * 0 | hBlankEnd hBlankStart | + * | | | | | vSync vBlank + * 0--+--------------------------------------------+ +-+ | + * | Sync | | | + * vSyncEnd--| +----------------------------------------+ +-+ | + * | | Back Porch | | | + * vBlankEnd--| | +--------------------------------+ | | +-+ + * | | | Active Area | | | | + * | | | +------------------------+ | | | | + * | | | | | | | | | + * | S | B | A | | A | F | | | + * | y | a | c | | c | r | | | + * | n | c | t | | t | o | | | + * | c | k | i | | i | n | | | + * | | | v | | v | t | | | + * | | P | e | Output Viewport | e | | | | + * | | o | | | | P | | | + * | | r | A | | A | o | | | + * | | c | r | | r | r | | | + * | | h | e | | e | c | | | + * | | | a | | a | h | | | + * | | | | | | | | | + * | | | +------------------------+ | | | | + * | | | Active Area | | | | + * vBlankStart-| | +--------------------------------+ | | +-+ + * | | Front Porch | | | + * vTotal--+---+----------------------------------------+ +-+ | + * ___ + * / \________________________________________/ hSync + * ________ ____ + * \________________________________/ hBlank + * + * + * + * Interlaced Raster Structure + * + * hSyncEnd hTotal + * 0 | hBlankEnd hBlankStart | + * | | | | | vSync vBlank + * 0--+--------------------------------------------+ +-+ | + * | Sync | | | + * vSyncEnd--| +----------------------------------------+ +-+ | + * | | Back Porch | | | + * vBlankEnd--| | +--------------------------------+ | | +-+ + * | | | Active Area | | | | + * | | | +------------------------+ | | | | + * | | | | | | | | | + * | S | B | A | | A | F | | | + * | y | a | c | | c | r | | | + * | n | c | t | | t | o | | | + * | c | k | i | | i | n | | | + * | | | v | | v | t | | | + * | | P | e | Output Viewport | e | | | | + * | | o | | | | P | | | + * | | r | A | | A | o | | | + * | | c | r | | r | r | | | + * | | h | e | | e | c | | | + * | | | a | | a | h | | | + * | | | | | | | | | + * | | | +------------------------+ | | | | + * | | | Active Area | | | | + * vBlankStart-| | +--------------------------------+ | | +-+ + * | | | | | + * | | Front Porch +--------------------+ | | + * | | | | +-+ | + * | +-------------------+ | | | + * | | | | + * | Sync +--------------------+ | | + * | | | +-+ | + * | +-------------------+ | | | + * vInterlaced | | Back Porch | | | + * BlankEnd--| | +--------------------------------+ | | +-+ + * | | | Active Area | | | | + * | | | +------------------------+ | | | | + * | | | | | | | | | + * | S | B | A | | A | F | | | + * | y | a | c | | c | r | | | + * | n | c | t | | t | o | | | + * | c | k | i | | i | n | | | + * | | | v | | v | t | | | + * | | P | e | Output Viewport | e | | | | + * | | o | | | | P | | | + * | | r | A | | A | o | | | + * | | c | r | | r | r | | | + * | | h | e | | e | c | | | + * | | | a | | a | h | | | + * | | | | | | | | | + * | | | +------------------------+ | | | | + * vInterlaced | | | Active Area | | | | + * BlankStart-| | +--------------------------------+ | | +-+ + * | | Front Porch | | | + * vTotal--+---+----------------------------------------+ +-+ | + * ___ + * / \________________________________________/ hSync + * ________ ____ + * \________________________________/ hBlank + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * +*/ + +#define NV30F1_CTRL_CMD_GSYNC_GET_OPTIMIZED_TIMING (0x30f10160) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS_MESSAGE_ID (0x60U) + +typedef struct NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS { + NvU32 gpuId; + NvU32 display; + NvU32 output; + NvU32 protocol; + NvU32 structure; + NvU32 adjust; + NvU32 hDeltaStep; + NvU32 hDeltaMax; + NvU32 vDeltaStep; + NvU32 vDeltaMax; + NvU32 hSyncEnd; + NvU32 hBlankEnd; + NvU32 hBlankStart; + NvU32 hTotal; + NvU32 vSyncEnd; + NvU32 vBlankEnd; + NvU32 vBlankStart; + NvU32 vInterlacedBlankEnd; + NvU32 vInterlacedBlankStart; + NvU32 vTotal; + NvU32 refreshX10K; + NvU32 pixelClockHz; +} NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS; + +/* output values */ +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_OUTPUT_DAC (0x00000001) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_OUTPUT_SOR (0x00000004) + +/* protocol values for DAC displays (e.g. CRTs) */ +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_DAC_RGB_CRT (0x00000000) + +/* protocol values for SOR displays (e.g. DFPs) */ +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_LVDS_CUSTOM (0x00000000) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_SINGLE_TMDS_A (0x00000001) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_SINGLE_TMDS_B (0x00000002) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_DUAL_TMDS (0x00000005) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_DP_A (0x00000008) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_DP_B (0x00000009) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_HDMI_FRL (0x0000000C) + +/* structure values */ +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_STRUCTURE_INTERLACED (0x00000001) + +/* adjust values */ +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_H_FRONT_PORCH (0x00000001) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_V_FRONT_PORCH (0x00000002) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_H_ACTIVE_AREA (0x00000004) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_V_ACTIVE_AREA (0x00000008) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_H_BACK_PORCH (0x00000010) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_V_BACK_PORCH (0x00000020) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_H_RASTER_SYNC (0x00000040) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_V_RASTER_SYNC (0x00000080) + +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_DEFAULT_CRT (0x00000030) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_DEFAULT_DFP (0x00000020) + +/* DeltaStep and DeltaMax values to trigger default settings */ +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_H_DELTA_STEP_USE_DEFAULTS (0x00000000) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_H_DELTA_MAX_USE_DEFAULTS (0x00000000) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_V_DELTA_STEP_USE_DEFAULTS (0x00000000) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_V_DELTA_MAX_USE_DEFAULTS (0x00000000) + +/* + * NV30F1_CTRL_CMD_GSYNC_SET_EVENT_NOTIFICATION + * + * This command sets event notification state for the associated Gsync + * object. This command requires that an instance of NV01_EVENT has + * been previously bound to the associated Gsync object. + * + * If one or more of the "smart event notification" options are set in the + * action parameter, multiple sequential events of the same type will only + * trigger one notification. After that, only an event of a different type + * will trigger a new notification. + * + * action + * This member specifies the desired event notification action. + * Valid notification actions include: + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_DISABLE + * This action disables event notification for the associated + * Gsync object. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_LOSS + * This action enables smart event notification for the + * associated Gsync object, for "sync loss" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_GAIN + * This action enables smart event notification for the + * associated Gsync object, for "sync gained" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_STEREO_LOSS + * This action enables smart event notification for the + * associated Gsync object, for "stereo lost" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_STEREO_GAIN + * This action enables smart event notification for the + * associated Gsync object, for "stereo gained" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_HOUSE_GAIN + * This action enables smart event notification for the + * associated Gsync object, for "house sync (BNC) plug in" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_HOUSE_LOSS + * This action enables smart event notification for the + * associated Gsync object, for "house sync (BNC) plug out" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_RJ45_GAIN + * This action enables smart event notification for the + * associated Gsync object, for "ethernet (RJ45) plug in" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_RJ45_LOSS + * This action enables smart event notification for the + * associated Gsync object, for "ethernet (RJ45) plug out" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_COUNT_MATCH + * This action enables smart event notification for the + * associated Gsync object, for "frame counter match" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_ALL + * This action enables smart event notification for the + * associated Gsync object, for any type of event. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV30F1_CTRL_CMD_GSYNC_SET_EVENT_NOTIFICATION (0x30f10170) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS_MESSAGE_ID (0x70U) + +typedef struct NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS { + NvU32 action; +} NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS; + +/* valid action values */ + +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_LOSS (0x00000001) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_GAIN (0x00000002) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_STEREO_LOSS (0x00000004) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_STEREO_GAIN (0x00000008) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_HOUSE_GAIN (0x00000010) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_HOUSE_LOSS (0x00000020) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_RJ45_GAIN (0x00000040) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_RJ45_LOSS (0x00000080) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_COUNT_MATCH (0x00000100) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_ALL (0x000001FF) + +#define NV30F1_CTRL_GSYNC_EVENT_TYPES 9 + +/* + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE + * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE + * + * These commands can be used to get/set the stereo lock assistance mode of + * the GSYNC device. This is supported by GSYNC III device only. + * 1] In this mode the GSYNC recreates the hidden VS either by -> + * (a) using local stereo edge if stereo is toggle or + * (b) counting lines and generate the missing VS. + * 2] Master GSYNC card recreates the stereo and passes it along to + * the slave GSYNC cards. + * 3] Slave GSYNC cards generates the stereo raster sync structure to + * synchronize the GPU. + * 4] For stereo sync status reporting, under this mode, the GSYNC automatically + * reports stereo lock whenever it gets the master stereo signal. The + * assumption is local stereo will be in synced with the new structure. + * 5] If the slave GSYNC card does not observed master stereo for any reason, + * (a) it clears the stereo sync bit and + * (b) it generates its own version of stereo and sync the GPU. + * + * Parameters: + * gpuId + * This parameter is set by the client to indicate the gpuId on which + * the stereo lock mode should be enabled/disabled. + * + * enable + * In SET query, this parameter is set by the client to indicate whether + * RM should enable or disable stereo lock mode for GPU specified in gpuId. + * 1 and 0 indicates enable and disable stereo lock mode respectively. In + * GET query, RM will set this parameter to 1 or 0 depending on StereoLock + * mode is enabled or not respectively for specified GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE (0x30f10172) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE (0x30f10173) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID (0x72U) + +typedef struct NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS { + NvU32 gpuId; + NvU32 enable; +} NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS; +#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID (0x73U) + +typedef NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS; + +/* + * NV30F1_CTRL_CMD_GSYNC_READ_REGISTER + * + * This command is used to read raw i2c registers from the gsync device, via + * the given GPU (registers on the same gsync device may have different values + * depending on which GPU is used to do the read). + * + * This may only be used by a privileged client. + * + * Parameters: + * gpuId + * This parameter is set by the client to specify which GPU to use to + * perform the read. + * + * reg + * This parameter is set by the client to specify which i2c register to + * read. + * + * data + * This parameter is written by the RM and returned to the client upon a + * successful read. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +#define NV30F1_CTRL_CMD_GSYNC_READ_REGISTER (0x30f10180) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS_MESSAGE_ID (0x80U) + +typedef struct NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS { + NvU32 gpuId; + NvU8 reg; + NvU8 data; +} NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS; + +/* + * NV30F1_CTRL_CMD_GSYNC_WRITE_REGISTER + * + * This command is used to write raw i2c registers on the gsync device, via the + * given GPU (registers on the same gsync device may have different values + * depending on which GPU is used to do the write). + * + * This may only be used by a privileged client. + * + * Parameters: + * gpuId + * This parameter is set by the client to specify which GPU to use to + * perform the write. + * + * reg + * This parameter is set by the client to specify which i2c register to + * write. + * + * data + * This parameter is set by the client to specify what data to write to the + * given i2c register. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ + +#define NV30F1_CTRL_CMD_GSYNC_WRITE_REGISTER (0x30f10181) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS { + NvU32 gpuId; + NvU8 reg; + NvU8 data; +} NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS; + + + +/* + * NV30F1_CTRL_CMD_GSYNC_SET_LOCAL_SYNC + * + * This command enables/disables raster sync on displays i.e. + * mosaic groups between gpus. + * + * gpuTimingSource + * The parameter is set by the client to indicate the gpuId of the + * Timing Source gpu for specified mosaic group. + * gpuTimingSlaves[] + * This parameter is set by the client to indicate the gpuIds of the + * timing slave gpus for specified mosaic group. It should not contain + * more gpuids than slaveGpuCount. + * slaveGpuCount + * This parameter is set by the client to indicate the count of timing + * slave gpus under specified group. + * Referring to gsync3-P2060, slaveGpuCount can vary from 0x01 to 0x03 + * as maximum possible connected gpus are four and one gpu must be + * timing master for mosaic group. + * mosaicGroupNumber + * This parameter is set by the client to tell the RM to which mosaic + * group it should refer. + * Referring to gsync3-P2060, mosaicGroupNumber can contain 0x00 or + * 0x01 as only two mosaic groups are possible. + * enableMosaic + * This parameter is set by the client to indicate RM that whether RM + * should enable mosaic or disable mosaic. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV30F1_CTRL_CMD_GSYNC_SET_LOCAL_SYNC (0x30f10185) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS_MESSAGE_ID (0x85U) + +typedef struct NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS { + NvU32 gpuTimingSource; + NvU32 gpuTimingSlaves[NV30F1_CTRL_MAX_GPUS_PER_GSYNC]; + NvU32 slaveGpuCount; + NvU32 mosaicGroupNumber; + NvBool enableMosaic; +} NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS; + +/* + * NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH + * + * This command configure GSYNC registers for pre-flash and post-flash + * operations. This is currenly used for GSYNC-3 (P2060) only. RM clients + * has to make sure that they perform both pre-flash and post-flash + * operations on GSYNC board. Avoiding, post-flash will cause mismatch + * between RM cached-data and GSYNC register values. + * + * Parameters: + * gpuId + * This parameter is set by the client to indicate the gpuId for which + * GSYNC board connected to that GPU will be configured for pre-flash + * or post-flash operation depending on preFlash value. + * + * preFlash + * This parameter is set by the client to indicate whether RM has to configure + * GSYNC registers and SW state for pre-flash or post-flash operation. Values + * 1 and 0 indicates that RM will configure GSYNC board for pre-flash and + * post-flash operations respectively. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH (0x30f10186) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS_MESSAGE_ID (0x86U) + +typedef struct NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS { + NvU32 gpuId; + NvU32 preFlash; +} NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS; + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_HOUSE_SYNC_MODE + * NV30F1_CTRL_CMD_GSYNC_SET_HOUSE_SYNC_MODE + * + * These two commands gets/sets house sync mode as input or output. + * + * Parameters: + * houseSyncMode + * This parameter indicates whether the house sync mode is input or + * output. For GET_HOUSE_SYNC_MODE, the current mode will be written + * by RM and returned to the client; for SET_HOUSE_SYNC_MODE, the client + * will write the new mode value to this parameter and pass it to RM + * for execution. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_STATE + * + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_HOUSE_SYNC_MODE (0x30f10187) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | 0x87" */ + +#define NV30F1_CTRL_CMD_GSYNC_SET_HOUSE_SYNC_MODE (0x30f10188) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | 0x88" */ + +typedef struct NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS { + NvU8 houseSyncMode; +} NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS; + + +#define NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_INPUT (0x00) +#define NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_OUTPUT (0x01) + +/* _ctrl30f1_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl402c.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl402c.h new file mode 100644 index 0000000..eb9bef5 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl402c.h @@ -0,0 +1,971 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl402c.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV40_I2C control commands and parameters */ +#define NV402C_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0x402C, NV402C_CTRL_##cat, idx) + +/* I2C command categories (6 bits) */ +#define NV402C_CTRL_RESERVED (0x00) +#define NV402C_CTRL_I2C (0x01) + + +/* This field specifies the maximum regular port identifier allowed. */ +#define NV402C_CTRL_NUM_I2C_PORTS 16 +/* This temporary field specifies the dynamic port identifier. */ +#define NV402C_CTRL_DYNAMIC_PORT NV_U8_MAX + +/* + * NV402C_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV402C_CTRL_CMD_NULL (0x402c0000) /* finn: Evaluated from "(FINN_NV40_I2C_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV402C_CTRL_I2C_GET_PORT_INFO_IMPLEMENTED + * The port exists on this hardware. + * NV402C_CTRL_I2C_GET_PORT_INFO_DCB_DECLARED + * The port has an entry in the DCB. + * NV402C_CTRL_I2C_GET_PORT_INFO_DDC_CHANNEL + * The port is used to read EDIDs via DDC. + * NV402C_CTRL_I2C_GET_PORT_INFO_CRTC_MAPPED + * The port is accessible via the CRTC register space. + * NV402C_CTRL_I2C_GET_PORT_INFO_VALID + * The port is validated using I2C device. + */ +#define NV402C_CTRL_I2C_GET_PORT_INFO_IMPLEMENTED 0:0 +#define NV402C_CTRL_I2C_GET_PORT_INFO_IMPLEMENTED_NO 0x00 +#define NV402C_CTRL_I2C_GET_PORT_INFO_IMPLEMENTED_YES 0x01 +#define NV402C_CTRL_I2C_GET_PORT_INFO_DCB_DECLARED 1:1 +#define NV402C_CTRL_I2C_GET_PORT_INFO_DCB_DECLARED_NO 0x00 +#define NV402C_CTRL_I2C_GET_PORT_INFO_DCB_DECLARED_YES 0x01 +#define NV402C_CTRL_I2C_GET_PORT_INFO_DDC_CHANNEL 2:2 +#define NV402C_CTRL_I2C_GET_PORT_INFO_DDC_CHANNEL_ABSENT 0x00 +#define NV402C_CTRL_I2C_GET_PORT_INFO_DDC_CHANNEL_PRESENT 0x01 +#define NV402C_CTRL_I2C_GET_PORT_INFO_CRTC_MAPPED 3:3 +#define NV402C_CTRL_I2C_GET_PORT_INFO_CRTC_MAPPED_NO 0x00 +#define NV402C_CTRL_I2C_GET_PORT_INFO_CRTC_MAPPED_YES 0x01 +#define NV402C_CTRL_I2C_GET_PORT_INFO_VALID 4:4 +#define NV402C_CTRL_I2C_GET_PORT_INFO_VALID_NO 0x00 +#define NV402C_CTRL_I2C_GET_PORT_INFO_VALID_YES 0x01 +#define NV402C_CTRL_I2C_GET_PORT_INFO_ALL 4:0 +#define NV402C_CTRL_I2C_GET_PORT_INFO_ALL_DEFAULT 0x00 + +/* + * NV402C_CTRL_CMD_I2C_GET_PORT_INFO + * + * Returns information for the first eight I2C ports. + * + * info + * This parameter is an output from the command and is ignored as an + * input. Each element contains the flags described previously named + * NV402C_CTRL_I2C_GET_PORT_INFO*. Note that the index into the info + * array is one less than the port identifier that would be returned from + * NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID; the port numbers here are + * 0-indexed as opposed to 1-indexed. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + + +#define NV402C_CTRL_CMD_I2C_GET_PORT_INFO (0x402c0101) /* finn: Evaluated from "(FINN_NV40_I2C_I2C_INTERFACE_ID << 8) | NV402C_CTRL_I2C_GET_PORT_INFO_PARAMS_MESSAGE_ID" */ + + + +#define NV402C_CTRL_I2C_GET_PORT_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV402C_CTRL_I2C_GET_PORT_INFO_PARAMS { + NvU8 info[NV402C_CTRL_NUM_I2C_PORTS]; +} NV402C_CTRL_I2C_GET_PORT_INFO_PARAMS; +#define NV402C_CTRL_I2C_INDEX_LENGTH_MAX 4 +#define NV402C_CTRL_I2C_MESSAGE_LENGTH_MAX 4096 + +//! Minimum and maximum valid read/write message length for block process protocol. +#define NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MIN 3 +#define NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX 32 + +/* + * NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE + * A client uses this field to indicate the I2C addressing mode to be + * used. + * Possible values are: + * NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE_7BIT + * The default, this value specifies the master to operate in the + * basic 7-bit addressing mode, which is available on all + * implementations. + * NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE_10BIT + * This I2C mode allows for 10 bits of addressing space and is + * reverse compatible with 7-bit addressing. + */ +#define NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE 0:0 +#define NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE_7BIT (0x00000000) +#define NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE_10BIT (0x00000001) +#define NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE_DEFAULT NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE_7BIT +/* + * NV402C_CTRL_I2C_FLAGS_SPEED_MODE + * A client uses this field to indicate the target speed at which the + * I2C master should attempt to drive the bus. The master may throttle + * its own speed for various reasons, and devices may slow the bus + * using clock-streching. Neither of these possibilities are + * considered failures. + */ +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE 4:1 +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_100KHZ (0x00000000) +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_200KHZ (0x00000001) +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_400KHZ (0x00000002) +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_33KHZ (0x00000003) +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_10KHZ (0x00000004) +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_3KHZ (0x00000005) +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_DEFAULT (0x00000006) +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_300KHZ (0x00000007) + + +/* + * NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE + * A client uses this field to specify a transaction mode. + * Possible values are: + * NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE_NORMAL + * The default, this value indicates to use the normal I2C transaction + * mode which will involve read/write operations depending on client's + * needs. + * NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE_PING + * This value specifies that the device only needs to be pinged. No need + * of performing a complete read/write transaction. This will send a + * single byte to the device to be pinged. On receiving an ACK, we will + * get a confirmation on the device's availability. + */ +#define NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE 11:10 +#define NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE_NORMAL (0x00000000) +#define NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE_PING (0x00000001) +#define NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE_DEFAULT NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE_NORMAL +/*! + * NV402C_CTRL_I2C_FLAGS_RESERVED + * A client must leave this field as 0, as it is reserved for future use. + */ +#define NV402C_CTRL_I2C_FLAGS_RESERVED 31:12 + +/*! + * The following defines specify WAR flags that can be specified during + * I2C Quick Read or Write command (Refer NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW). + * + * _NONE + * No workaround is needed. + * + * _TEST_PORT + * Use this flag to have the client sent a request to test a port instead + * of performing any transaction on it. Transaction type has to be + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW. + */ +#define NV402C_CTRL_I2C_SMBUS_QUICK_RW_WAR_FLAGS 0:0 +#define NV402C_CTRL_I2C_SMBUS_QUICK_RW_WAR_FLAGS_NONE 0x00000000 +#define NV402C_CTRL_I2C_SMBUS_QUICK_RW_WAR_FLAGS_TEST_PORT 0x00000001 + +/*! + * The following defines specify WAR flags that can be specified during + * I2C Register Read or Write buffer command + * (Refer NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW) + * + * _NONE + * No workaround is needed. + * + * _SI1930 + * SI1930 microcontroller register read or write requested by a client. + * Transaction type has to be NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW. + * + * _PX3540 + * Register read from PX3540 or PX3544 device. Transaction type has to be + * NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW and bWrite must be TRUE to + * indicate READ operation + */ +#define NV402C_CTRL_I2C_BUFFER_RW_WAR_FLAGS 1:0 +#define NV402C_CTRL_I2C_BUFFER_RW_WAR_FLAGS_NONE 0x00000000 +#define NV402C_CTRL_I2C_BUFFER_RW_WAR_FLAGS_SI1930 0x00000001 +#define NV402C_CTRL_I2C_BUFFER_RW_WAR_FLAGS_PX3540 0x00000002 + +/*! + * The following defines specify WAR flags that can be specified during + * I2C buffer Read or Write to Multibyte Register + * (Refer NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW) + * + * _NONE + * No workaround is needed. + * + * _NO_AUTO_INC + * This value specifies that the device does not support auto-increment. + * Most devices allow you to write multiple bytes after specifying a + * register address, and the subsequent bytes will go to incremented + * addresses. Without auto-increment, we write a buffer of data as a + * sequence of address-register-value triplets separated by starts. + */ +#define NV402C_CTRL_I2C_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW_WAR_FLAGS 0:0 +#define NV402C_CTRL_I2C_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW_WAR_FLAGS_NONE 0x00000000 +#define NV402C_CTRL_I2C_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW_WAR_FLAGS_NO_AUTO_INC 0x00000001 + +/* + * NV402C_CTRL_CMD_I2C_SYNC + * + * Perform a basic I2C transaction synchronously. + * + * portId + * This field must be specified by the client to indicate the logical + * port/bus for which the transaction is requested. The port identifier + * is one less than the value returned by + * NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID unless that value was 0 (the + * 'dynamic' port). For the 'dynamic' port, this should be 0xFF. Note + * that future versions of the API may obsolete use of the 'dynamic' port; + * please contact the RM if you begin using this portion of the API so we + * can help you migrate when the time comes. + * + * bIsWrite + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + * + * flags + * This parameter specifies optional flags used to control certain modal + * features such as target speed and addressing mode. The currently + * defined fields are described previously; see NV402C_I2C_FLAGS_*. + * + * address + * The address of the I2C slave. The address should be shifted left by + * one. For example, the I2C address 0x50, often used for reading EDIDs, + * would be stored here as 0xA0. This matches the position within the + * byte sent by the master, as the last bit is reserved to specify the + * read or write direction. + * + * indexLength + * This required parameter specifies how many bytes to write as part of the + * first index. If zero is specified, then no index will be sent. + * + * index + * This parameter, required of the client if index is one or more, + * specifies the index to be written. The buffer should be arranged such + * that index[0] will be the first byte sent. + * + * messageLength + * This parameter, required of the client, specifies the number of bytes to + * read or write from the slave after the index is written. + * + * pMessage + * This parameter, required of the client, specifies the data to be written + * to the slave. The buffer should be arranged such that pMessage[0] will + * be the first byte read or written. If the transaction is a read, then + * it will follow the combined format described in the I2C specification. + * If the transaction is a write, the message will immediately follow the + * index without a restart. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_STATE_IN_USE + * NV_ERR_GENERIC, if the I2C transaction fails. + */ +#define NV402C_CTRL_I2C_INDEXED_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV402C_CTRL_I2C_INDEXED_PARAMS { + NvU8 portId; + NvU8 bIsWrite; + NvU16 address; + NvU32 flags; + + NvU32 indexLength; + NvU8 index[NV402C_CTRL_I2C_INDEX_LENGTH_MAX]; + + NvU32 messageLength; + NV_DECLARE_ALIGNED(NvP64 pMessage, 8); +} NV402C_CTRL_I2C_INDEXED_PARAMS; + +#define NV402C_CTRL_CMD_I2C_INDEXED (0x402c0102) /* finn: Evaluated from "(FINN_NV40_I2C_I2C_INTERFACE_ID << 8) | NV402C_CTRL_I2C_INDEXED_PARAMS_MESSAGE_ID" */ + +/* + * NV402C_CTRL_CMD_I2C_GET_PORT_SPEED + * + * Returns information for the I2C ports. + * + * portSpeed + * This parameter is an output from the command and is ignored as an + * input. Each element contains the current I2C speed of the port. + * Note that the index into the info array is one less than the + * port identifier that would be returned from + * NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID; the port numbers here are + * 0-indexed as opposed to 1-indexed. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV402C_CTRL_I2C_GET_PORT_SPEED_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV402C_CTRL_I2C_GET_PORT_SPEED_PARAMS { + NvU32 portSpeed[NV402C_CTRL_NUM_I2C_PORTS]; +} NV402C_CTRL_I2C_GET_PORT_SPEED_PARAMS; + +#define NV402C_CTRL_CMD_I2C_GET_PORT_SPEED (0x402c0103) /* finn: Evaluated from "(FINN_NV40_I2C_I2C_INTERFACE_ID << 8) | NV402C_CTRL_I2C_GET_PORT_SPEED_PARAMS_MESSAGE_ID" */ + +/* + * NV402C_CTRL_I2C_DEVICE_INFO + * + * This structure describes the basic I2C Device information. + * + * type + * This field return the type of device NV_DCB4X_I2C_DEVICE_TYPE_ + * i2cAddress + * This field contains the 7 bit/10 bit address of the I2C device. + * i2cLogicalPort + * This field contains the Logical port of the I2C device. + */ +typedef struct NV402C_CTRL_I2C_DEVICE_INFO { + NvU8 type; + NvU16 i2cAddress; + NvU8 i2cLogicalPort; + NvU8 i2cDevIdx; +} NV402C_CTRL_I2C_DEVICE_INFO; + +/* Maximum number of I2C devices in DCB */ +#define NV402C_CTRL_I2C_MAX_DEVICES 32 + +/* + * NV402C_CTRL_CMD_I2C_TABLE_GET_DEV_INFO + * + * RM Control to get I2C device info from the DCB I2C Devices Table. + * + * i2cDevCount + * The value of this parameter will give the number of + * I2C devices found in DCB. + * + * i2cDevInfo + * For each device found in DCB the control call will write the info + * in this parameter. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV402C_CTRL_I2C_TABLE_GET_DEV_INFO_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV402C_CTRL_I2C_TABLE_GET_DEV_INFO_PARAMS { + NvU8 i2cDevCount; + NV402C_CTRL_I2C_DEVICE_INFO i2cDevInfo[NV402C_CTRL_I2C_MAX_DEVICES]; +} NV402C_CTRL_I2C_TABLE_GET_DEV_INFO_PARAMS; + +#define NV402C_CTRL_CMD_I2C_TABLE_GET_DEV_INFO (0x402c0104) /* finn: Evaluated from "(FINN_NV40_I2C_I2C_INTERFACE_ID << 8) | NV402C_CTRL_I2C_TABLE_GET_DEV_INFO_PARAMS_MESSAGE_ID" */ + +/*! + * The IDs of each type of I2C command available. + */ +typedef enum NV402C_CTRL_I2C_TRANSACTION_TYPE { + /*! + * This transaction type is used to perform the Quick SMBus Read/write command + * on a slave device. No data is sent or received, just used to verify the + * presence of the device. + * Refer SMBus spec 2.0 (section 5.5.1 Quick Command) + * SMBus Quick Write : S Addr|Wr [A] P + * SMBus Quick Read : S Addr|Rd [A] P + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW = 0, + /*! + * This transaction type is used to perform the I2C byte read/write from/to + * a slave device. As per the spec last byte should be NA (Not Acknolwedged) + * by slave. + * Refer I2CBus spec 3.0 (section 9 Fig 11 and Fig 12) or Refer SMBus spec + * 2.0 (section 5.5.2 Send Byte and 5.5.3 Receive Byte). + * I2C Byte Write : S Addr|Wr [A] Data [NA] P + * I2C Byte Read : S Addr|Rd [A] Data NA P + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW = 1, + /*! + * This transaction type is used to perform the I2C block (buffer) + * read/write from/to a slave device. As per the spec last byte should be NA + * (Not Acknolwedged) by slave. + * Refer I2CBus spec 3.0 (section 9 Fig 11 and Fig 12) + * I2C Byte Write : S Addr|Wr [A] Data1 [A]...Data(N-1) [A] DataN [NA] P + * I2C Byte Read : S Addr|Rd [A] Data1 A...Data(N-1) A DataN NA P + * + * Distinction between I2C_BLOCK and SMBUS_BLOCK protocol: + * In I2C Block write it is the slave device (and in I2C Block read it's + * the master device) that determines the number of bytes to transfer by + * asserting the NAK at last bit before stop. This differs from the SMBus + * block mode write command in which the master determines the block + * write transfer size. In I2c Block read there is no limit to maximum size + * of data that could be transferred whereas in SMBus block it is restricted + * to 255 bytes (0xFF). + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW = 2, + /*! + * This transaction type is used to perform the I2C Buffer read/write + * from/to a register of a slave device. It does not send bytecount as + * part of data buffer. + * Not a part of SMBus spec. + * I2C Buffer Write : S Addr|Wr [A] cmd [A] Data1 [A]...DataN[A] P + * I2C Buffer Read : S Addr|Wr [A] cmd [A] Sr Addr|Rd [A] Data1 A... + * DataN-1 A DataN A P + * + * Distinction between SMBUS_BLOCK and I2C_BUFFER protocol: + * In SMBUS_BLOCK Read/write the first byte of data buffer contains the + * count size (The number of bytes to be transferred) and it is restricted + * to 255 bytes whereas in I2C_BUFFER, count size is not sent during the + * transfer and there is no restriction in terms of size. + * + * Distinction between I2C_BLOCK and I2C_BUFFER protocol: + * I2C_BUFFER takes the register address as argument whereas I2C_BLOCK does + * not have any register or command provision. + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW = 3, + /*! + * This transaction type is used to perform the I2C byte read/write from/to + * a slave device + * Refer SMBus spec 2.0 (section 5.5.4 Write Byte and 5.5.5 Read Byte) + * SMBus Byte Write : S Addr|Wr [A] cmd [A] Data [A] P + * SMBus Byte Read : S Addr|Wr [A] cmd [A] Sr Addr|Rd [A] Data A P + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW = 4, + /*! + * This transaction type is used to perform the SMBus byte read/write + * from/to a register of a slave device + * Refer SMBus spec 2.0 (section 5.5.4 Write Word and 5.5.5 Read Word) + * SMBus Word Write : S Addr|Wr [A] cmd [A] DataLow [A] DataHigh [A] P + * SMBus Word Read : S Addr|Wr [A] cmd [A] Sr Addr|Rd [A] DataLow A + * DataHigh A P + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW = 5, + /*! + * This transaction type is used to perform the SMBus Block read/write + * from/to a register of a slave device + * Refer SMBus spec 2.0 (section 5.5.7 Block Write/Read) + * SMBus Block Write : S Addr|Wr [A] cmd [A] ByteCount [A] Data1 [A]... + * DataN-1 [A] DataN[A] P + * SMBus Block Read : S Addr|Wr [A] cmd [A] Sr Addr|Rd [A] ByteCount A + * Data1 A...DataN-1 A DataN A P + * + * Distinction between I2C_BLOCK and SMBUS_BLOCK protocol: + * In I2C Block write it is the slave device (and in I2C Block read it's + * the master device) that determines the number of bytes to transfer by + * asserting the NAK at last bit before stop. This differs from the SMBus + * block mode write/Read command in which the master determines the block + * write transfer size. In I2c Block read/Write there is no limit to maximum + * size of data that could be transferred whereas in SMBus block it is + * restricted to 255 bytes (0xFF). + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW = 6, + /*! + * This transaction type is used to perform the SMBus process call. It sends + * data and waits for the slave to return a value dependent on that data. + * The protocol is simply a SMBus write Word followed by a SMBus Read Word + * without the Read-Word command field and the Write-Word STOP bit. + * Note that there is no STOP condition before the repeated START condition, + * and that a NACK signifies the end of the read transfer. + * + * Refer SMBus spec 2.0 (section 5.5.6 Process Call) + * SMBus Process Call : S Addr|Wr [A] cmd [A] DataLow [A] DataHigh [A] + * Sr Addr|Rd [A] DataLow [A] DataHigh [NA] P + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL = 7, + /*! + * This transaction type is used to perform the SMBus Block Write Block Read + * process call. + * The block write-block read process call is a two-part message. The call + * begins with a slave address and a write condition. After the command code + * the host issues a write byte count (M) that describes how many more bytes + * will be written in the first part of the message. + * If a master has 6 bytes to send, the byte count field will have the value + * 6 (0000 0110b), followed by the 6 bytes of data. The write byte count (M) + * cannot be zero. + * The second part of the message is a block of read data beginning with a + * repeated start condition followed by the slave address and a Read bit. + * The next byte is the read byte count (N), which may differ from the write + * byte count (M). The read byte count (N) cannot be zero. The combined data + * payload must not exceed 32 bytes. + * The byte length restrictions of this process call are summarized as + * follows: + * M >= 1 byte + * N >= 1 byte + * M + N <= 32 bytes + * Note that there is no STOP condition before the repeated START condition, + * and that a NACK signifies the end of the read transfer. + * + * Refer SMBus spec 2.0 (section 5.5.8 Block Write Block Read Process Call) + * SMBus Process Call : S Addr|Wr [A] cmd [A] ByteCount=M [A] Data1 [A]... + * DataN-1 [A] DataM[A] Sr Addr|Rd [A] ByteCount=N [A] + * Data1 [A]...DataN [NA] P + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL = 8, + /*! + * This transaction type is used to perform SMBus buffer read/write + * from/to multiple registers of a slave device known as Auto Increment. + * It is not a part of any standard I2C/SMBus spec but a feature of many + * SMBus devices like EEPROM. + * It is also used for reading a block of bytes from a designated register + * that is specified through the two Comm bytes.of a slave device or writing + * a block of bytes from a designated register of a slave device (Note : The + * command byte in this case could be 0, 2 or 4 Bytes) + * SMBus Multi-Byte Register Block Write : S Addr|Wr [A] cmd1 A cmd 2 [A]... + * cmdN [A] data1 [A] Data2 [A].....DataN [A] P + * SMBus Multi-Byte Register Block Read : S Addr|Rd [A] cmd1 A cmd 2 [A]... + * cmdN [A] data1 [A] Sr Addr [A] Data1 A Data2 A...DataN A P + * + * This transaction type could be also used for those devices which supports + * AUTO_INC. Even though it is frequently related to I2C/SMBus, automatic + * incrementation is not part of any I2C standard but rather a common + * feature found in many I2C devices. What it means is that the device + * maintains in internal pointer which is automatically incremented upon + * data read or write activities and which can be manually set to a fixed + * value. This comes in handy when storing larger amounts of data for + * instance in an ordinary I2C RAM or EEPROM. + * SMBus AUTO_INC Write : S Addr|Wr [A] cmd1 A Data1 [A] Data2 [A]... + * DataN [A] P + * SMBus AUTO_INC Read : S Addr|Rd [A] cmd1 A data1 [A] Sr Addr [A] Data1 A + * Data2 A...DataN A P + * If the device does not support AUTO_INC set warFlags of + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW to + * NV402C_CTRL_I2C_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW_WAR_FLAGS_NO_AUTO_INC. + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW = 9, + /*! + * This transaction type is used to perform the EDID read via DDC. + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC = 10, +} NV402C_CTRL_I2C_TRANSACTION_TYPE; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW. + * + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW { + /*! + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + */ + NvBool bWrite; + /*! + * Transaction specific flags + * (see NV402C_CTRL_I2C_SMBUS_QUICK_RW_WAR_FLAGS_*). + */ + NvU32 warFlags; +} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW. + * + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW { + /*! + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + */ + NvBool bWrite; + /*! + * The main message data. + */ + NvU8 message; +} NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW + * + * Specifies the structure of data filled by the client for I2C transaction + * when the transaction type is NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW. + * + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW { + /*! + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + */ + NvBool bWrite; + /*! + * This parameter specifies the number of bytes to read or + * write from the slave after the register address is written. + */ + NvU32 messageLength; + /*! + * The main message data. + */ + NV_DECLARE_ALIGNED(NvP64 pMessage, 8); +} NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW. + * + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW { + /*! + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + */ + NvBool bWrite; + /*! + * The address of the register. + */ + NvU8 registerAddress; + /*! + * The main message data. + */ + NvU8 message; +} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW. + * + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW { + /*! + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + */ + NvBool bWrite; + /*! + * The address of the register. + */ + NvU8 registerAddress; + /*! + * The main message data. + */ + NvU16 message; +} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BUFFER_RW + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BUFFER_RW. + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW { + /*! + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + */ + NvBool bWrite; + /*! + * Transaction specific flags to be set (see + * NV_NV402C_CTRL_I2C_BUFFER_RW_WAR_FLAGS_*) + */ + NvU32 warFlags; + /*! + * This parameter specifies how many bytes to write as part of the + * register address. If zero is specified, then no index will be sent. + */ + NvU8 registerAddress; + /*! + * This parameter specifies the number of bytes to read or + * write from the slave after the register address is written. + */ + NvU32 messageLength; + /*! + * The main message data. + * C form: NvU8 message[NV402C_CTRL_I2C_MESSAGE_LENGTH_MAX] + */ + NV_DECLARE_ALIGNED(NvP64 pMessage, 8); +} NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW. + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW { + /*! + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + */ + NvBool bWrite; + /*! + * This parameter specifies how many bytes to write as part of the + * register address. If zero is specified, then no index will be sent. + */ + NvU8 registerAddress; + /*! + * This parameter specifies the number of bytes to read or + * write from the slave after the register address is written. + */ + NvU32 messageLength; + /*! + * The main message data. + * C form: NvU8 message[NV402C_CTRL_I2C_MESSAGE_LENGTH_MAX] + */ + NV_DECLARE_ALIGNED(NvP64 pMessage, 8); +} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL. + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL { + /*! + * This parameter specifies how many bytes to write as part of the + * register address. If zero is specified, then no index will be sent. + */ + NvU8 registerAddress; + /*! + * The message data to be written to the slave. + */ + NvU16 writeMessage; + /*! + * The message data to be read from the slave. + */ + NvU16 readMessage; +} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL. + * + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL { + /*! + * This parameter specifies how many bytes to write as part of the + * register address. If zero is specified, then no index will be sent. + */ + NvU8 registerAddress; + /*! + * This parameter specifies the number of bytes to write the the slave + * after the writeByteCount is sent to the slave. + */ + NvU32 writeMessageLength; + /*! + * The message buffer to be written to the slave. + * C form: NvU8 writeMessage[NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX] + */ + NvU8 writeMessage[NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX]; + /*! + * This parameter specifies the number of bytes to read from the slave + * after the readByteCount is sent to the slave. + */ + NvU32 readMessageLength; + /*! + * The message buffer to be read from the slave. + * C form: NvU8 readMessage[NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX] + */ + NvU8 readMessage[NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX]; +} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW. + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW { + /*! + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + */ + NvBool bWrite; + /*! + * Transaction specific flags (see + * NV402C_CTRL_I2C_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW_WAR_FLAGS_*) + */ + NvU32 warFlags; + /*! + * This parameter specifies how many bytes to write as part of the + * register address. If zero is specified, then no index will be sent. + */ + NvU32 indexLength; + /*! + * Optional indexing data; aka register address. + * C form: NvU8 index[NV402C_CTRL_I2C_INDEX_LENGTH_MAX] + */ + NvU8 index[NV402C_CTRL_I2C_INDEX_LENGTH_MAX]; + /*! + * This parameter specifies the number of bytes to read or + * write from the slave after the register address is written. + */ + NvU32 messageLength; + /*! + * The main message data. + * C form: NvU8 message[NV402C_CTRL_I2C_MESSAGE_LENGTH_MAX] + */ + NV_DECLARE_ALIGNED(NvP64 pMessage, 8); +} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC. + * + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC { + /*! + * The segment number of the EDID block which is to be read. + */ + NvU8 segmentNumber; + /*! + * The address of the register. + */ + NvU8 registerAddress; + /*! + * This parameter specifies the number of bytes to read or + * write from the slave after the register address is written. + */ + NvU32 messageLength; + /*! + * The main message data. + * C form: NvU8 message[NV402C_CTRL_I2C_MESSAGE_LENGTH_MAX] + */ + NV_DECLARE_ALIGNED(NvP64 pMessage, 8); +} NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA + * + * This union encapsulates the transaction data corresponding to the + * transaction type enlisted above. + */ +typedef union NV402C_CTRL_I2C_TRANSACTION_DATA { + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW. + */ + NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW smbusQuickData; + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW. + */ + NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW i2cByteData; + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW. + */ + NV_DECLARE_ALIGNED(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW i2cBlockData, 8); + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW. + */ + NV_DECLARE_ALIGNED(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW i2cBufferData, 8); + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW. + */ + NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW smbusByteData; + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW. + */ + NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW smbusWordData; + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW. + */ + NV_DECLARE_ALIGNED(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW smbusBlockData, 8); + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL. + */ + NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL smbusProcessData; + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL. + */ + NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL smbusBlockProcessData; + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW. + */ + NV_DECLARE_ALIGNED(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW smbusMultibyteRegisterData, 8); + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC. + */ + NV_DECLARE_ALIGNED(NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC edidData, 8); +} NV402C_CTRL_I2C_TRANSACTION_DATA; + + +/*! + * NV402C_CTRL_I2C_TRANSACTION_PARAMS + * + * The params data structure for NV402C_CTRL_CMD_I2C_TRANSACTION. + */ +#define NV402C_CTRL_I2C_TRANSACTION_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV402C_CTRL_I2C_TRANSACTION_PARAMS { + /*! + * The logical port ID. + */ + NvU8 portId; + /*! + * This parameter specifies optional flags used to control certain modal + * features such as target speed and addressing mode. The currently + * defined fields are described previously; see NV402C_CTRL_I2C_FLAGS_* + */ + NvU32 flags; + /*! + * The address of the I2C slave. + */ + NvU16 deviceAddress; + /*! + * The transaction type. + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE transType; + /*! + * The transaction data corresponding transaction type. + */ + NV_DECLARE_ALIGNED(NV402C_CTRL_I2C_TRANSACTION_DATA transData, 8); +} NV402C_CTRL_I2C_TRANSACTION_PARAMS; + +#define NV402C_CTRL_CMD_I2C_TRANSACTION (0x402c0105) /* finn: Evaluated from "(FINN_NV40_I2C_I2C_INTERFACE_ID << 8) | NV402C_CTRL_I2C_TRANSACTION_PARAMS_MESSAGE_ID" */ + + +/* _ctrl402c_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl503c.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl503c.h new file mode 100644 index 0000000..e3a9532 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl503c.h @@ -0,0 +1,200 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl503c.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl503c/ctrl503cbase.h" + +/* + * NV503C_CTRL_CMD_REGISTER_VA_SPACE + * + * This command registers the specified GPU VA space with the given + * NV50_THIRD_PARTY_P2P object, and returns a token that + * uniquely identifies the VA space within the object's parent + * client. + * + * Its parameter structure has the following fields: + * + * hVASpace + * This field specifies the GPU VA space to be registered + * with the third-party P2P object. + * + * vaSpaceToken + * Upon successful completion of the regristration attempt, + * this field holds the new VA space identifier. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INVALID_OBJECT_HANDLE + * NVOS_STATUS_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_RESOURCES + */ +#define NV503C_CTRL_CMD_REGISTER_VA_SPACE (0x503c0102) /* finn: Evaluated from "(FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID << 8) | NV503C_CTRL_REGISTER_VA_SPACE_PARAMS_MESSAGE_ID" */ + +#define NV503C_CTRL_REGISTER_VA_SPACE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV503C_CTRL_REGISTER_VA_SPACE_PARAMS { + NvHandle hVASpace; + NV_DECLARE_ALIGNED(NvU64 vaSpaceToken, 8); +} NV503C_CTRL_REGISTER_VA_SPACE_PARAMS; + + +/* + * NV503C_CTRL_CMD_UNREGISTER_VA_SPACE + * + * This command unregisters (a previously registered) GPU VA space. + * + * Its parameter structure has the following field: + * + * hVASpace + * This field specifies the GPU VA space to be + * unregistered. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV503C_CTRL_CMD_UNREGISTER_VA_SPACE (0x503c0103) /* finn: Evaluated from "(FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID << 8) | NV503C_CTRL_UNREGISTER_VA_SPACE_PARAMS_MESSAGE_ID" */ + +#define NV503C_CTRL_UNREGISTER_VA_SPACE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV503C_CTRL_UNREGISTER_VA_SPACE_PARAMS { + NvHandle hVASpace; +} NV503C_CTRL_UNREGISTER_VA_SPACE_PARAMS; + + +/* + * NV503C_CTRL_CMD_REGISTER_VIDMEM + * + * This command registers a video memory allocation with the given + * NV50_THIRD_PARTY_P2P object. Registration of video memory + * allocations is required if they are to be made accessible via the + * third-party P2P infrastructure. + * + * The vidmem allocation is made available to the users of the third-party P2P + * APIs. It's exposed at the range specified by address and size starting at the + * specified offset within the physical allocation. The same physical memory is + * exposed as the NvRmMapMemoryDma() API would make accessible to the GPU if + * used with equivalent parameters. Notably this API doesn't create any virtual + * mappings nor verifies that any mappings are present, it only registers the + * memory for the purpose of the third-party P2P infrastructure. + * + * The address range specified by address and size cannot overlap any previously + * registered ranges for the given NV50_THIRD_PARTY_P2P object. + * + * Its parameter structure has the following field: + * + * hMemory + * This field specifies the video memory allocation to be + * registered with the third-party P2P object. + * + * address + * The address to register the video memory allocation at. Has to be + * aligned to 64K. + * + * size + * Size in bytes, has to be non-0 and aligned to 64K. Offset + size cannot + * be larger than the vidmem allocation. + * + * offset + * Offset within the video memory allocation where the registered address + * range starts. Has to be aligned to 64K. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_RESOURCES + */ +#define NV503C_CTRL_CMD_REGISTER_VIDMEM (0x503c0104) /* finn: Evaluated from "(FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID << 8) | NV503C_CTRL_REGISTER_VIDMEM_PARAMS_MESSAGE_ID" */ + +#define NV503C_CTRL_REGISTER_VIDMEM_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV503C_CTRL_REGISTER_VIDMEM_PARAMS { + NvHandle hMemory; + NV_DECLARE_ALIGNED(NvU64 address, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NV_DECLARE_ALIGNED(NvU64 offset, 8); +} NV503C_CTRL_REGISTER_VIDMEM_PARAMS; + + +/* + * NV503C_CTRL_CMD_UNREGISTER_VIDMEM + * + * This command unregisters (a previously registered) video memory + * allocation. + * + * Its parameter structure has the following field: + * + * hMemory + * This field specifies the video memory allocation to be + * unregistered. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV503C_CTRL_CMD_UNREGISTER_VIDMEM (0x503c0105) /* finn: Evaluated from "(FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID << 8) | NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS_MESSAGE_ID" */ + +#define NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS { + NvHandle hMemory; +} NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS; + +/* + * NV503C_CTRL_CMD_REGISTER_PID + * + * This command registers the PID of the process that allocated + * the RM client identified by the hClient argument with the + * third-party P2P object, granting this process access to any + * underlying video memory. + * + * Its parameter structure has the following field: + * + * hClient + * This field specifies the client id and should be the handle + * to a valid NV01_ROOT_USER instance. + * + * Possible status values returned are: + * NVOS_STATUS_SUCCES + * NV_ERR_INVALID_ARGUMENT + */ +#define NV503C_CTRL_CMD_REGISTER_PID (0x503c0106) /* finn: Evaluated from "(FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID << 8) | NV503C_CTRL_REGISTER_PID_PARAMS_MESSAGE_ID" */ + +#define NV503C_CTRL_REGISTER_PID_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV503C_CTRL_REGISTER_PID_PARAMS { + NvHandle hClient; +} NV503C_CTRL_REGISTER_PID_PARAMS; + +/* _ctrl503c_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl503c/ctrl503cbase.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl503c/ctrl503cbase.h new file mode 100644 index 0000000..22f3fbe --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl503c/ctrl503cbase.h @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl503c/ctrl503cbase.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV50_THIRD_PARTY_P2P control commands and parameters */ +#define NV503C_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x503C,NV503C_CTRL_##cat,idx) + +/* NV50_THIRD_PARTY_P2P command categories (6bits) */ +#define NV503C_CTRL_RESERVED (0x00) +#define NV503C_CTRL_P2P (0x01) + +/* + * NV503C_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV503C_CTRL_CMD_NULL (0x503c0000) /* finn: Evaluated from "(FINN_NV50_THIRD_PARTY_P2P_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrl503cbase_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl506f.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl506f.h new file mode 100644 index 0000000..7fd7c36 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl506f.h @@ -0,0 +1,96 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl506f.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV50_GPFIFO control commands and parameters */ + +#define NV506F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0x506F, NV506F_CTRL_##cat, idx) + +/* NV50_GPFIFO command categories (6bits) */ +#define NV506F_CTRL_RESERVED (0x00) +#define NV506F_CTRL_GPFIFO (0x01) +#define NV506F_CTRL_EVENT (0x02) + +/* + * NV506F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV506F_CTRL_CMD_NULL (0x506f0000) /* finn: Evaluated from "(FINN_NV50_CHANNEL_GPFIFO_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* + * NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL + * + * This command resets a channel which was isolated previously by RC recovery. + * + * exceptType + * This input parameter specifies the type of RC error that occurred. See the + * description of the ROBUST_CHANNEL_* values in nverror.h for valid exceptType + * values. info32 field of the error notifier is set with the exceptType when + * the error notifier is signaled. + * + * engineID + * This input parameter specifies the engine to be reset. See the description + * of the NV2080_ENGINE_TYPE values in cl2080.h for valid engineID values. info16 + * field of the error notifier is set with the engineID when the error notifier is + * signaled. + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + + +#define NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL (0x506f0105) /* finn: Evaluated from "(FINN_NV50_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_MESSAGE_ID" */ + +/* + * NV506F_CTRL_CMD_EVENT_SET_TRIGGER (deprecated on Fermi+) + * + * This command triggers a software event for the associated channel. + * This command accepts no parameters. + * + * Possible status values returned are: + * NV_OK + */ +// #define NV506F_CTRL_CMD_EVENT_SET_TRIGGER NV506F_CTRL_CMD(EVENT, 0x09) + +#define NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS { + NvU32 exceptType; + NvU32 engineID; +} NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS;/* _ctrl506f.h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070base.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070base.h new file mode 100644 index 0000000..49297f7 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070base.h @@ -0,0 +1,67 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070base.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV5070_DISPLAY control commands and parameters */ + +#define NV5070_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x5070, NV5070_CTRL_##cat, idx) + +/* Display command categories (6bits) */ +#define NV5070_CTRL_RESERVED (0x00) +#define NV5070_CTRL_CHNCTL (0x01) +#define NV5070_CTRL_RG (0x02) +#define NV5070_CTRL_SEQ (0x03) +#define NV5070_CTRL_OR (0x04) +#define NV5070_CTRL_INST (0x05) +#define NV5070_CTRL_VERIF (0x06) +#define NV5070_CTRL_SYSTEM (0x07) +#define NV5070_CTRL_EVENT (0x09) + +/* + * NV5070_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV5070_CTRL_CMD_NULL (0x50700000) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + +// This struct must be the first member of all +// 5070 control calls +typedef struct NV5070_CTRL_CMD_BASE_PARAMS { + NvU32 subdeviceIndex; +} NV5070_CTRL_CMD_BASE_PARAMS; + +/* _ctrl5070base_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070chnc.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070chnc.h new file mode 100644 index 0000000..1916d7f --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070chnc.h @@ -0,0 +1,1181 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070chnc.finn +// + +#include "ctrl/ctrl5070/ctrl5070base.h" +#include "ctrl5070common.h" +#include "nvdisptypes.h" + +#define NV5070_CTRL_CMD_NUM_DISPLAY_ID_DWORDS_PER_HEAD 2 + + + +#define NV5070_CTRL_IDLE_CHANNEL_ACCL_NONE (0x00000000) +#define NV5070_CTRL_IDLE_CHANNEL_ACCL_IGNORE_PI (NVBIT(0)) +#define NV5070_CTRL_IDLE_CHANNEL_ACCL_SKIP_NOTIF (NVBIT(1)) +#define NV5070_CTRL_IDLE_CHANNEL_ACCL_SKIP_SEMA (NVBIT(2)) +#define NV5070_CTRL_IDLE_CHANNEL_ACCL_IGNORE_INTERLOCK (NVBIT(3)) +#define NV5070_CTRL_IDLE_CHANNEL_ACCL_IGNORE_FLIPLOCK (NVBIT(4)) +#define NV5070_CTRL_IDLE_CHANNEL_ACCL_TRASH_ONLY (NVBIT(5)) +#define NV5070_CTRL_IDLE_CHANNEL_ACCL_TRASH_AND_ABORT (NVBIT(6)) + +#define NV5070_CTRL_IDLE_CHANNEL_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV5070_CTRL_IDLE_CHANNEL_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 channelClass; + NvU32 channelInstance; + + NvU32 desiredChannelStateMask; + NvU32 accelerators; // For future expansion. Not yet implemented + NvU32 timeout; // For future expansion. Not yet implemented + NvBool restoreDebugMode; +} NV5070_CTRL_IDLE_CHANNEL_PARAMS; + +/* + * NV5070_CTRL_CMD_STOP_OVERLAY + * + * This command tries to turn the overlay off ASAP. + * + * channelInstance + * This field indicates which of the two instances of the overlay + * channel the cmd is meant for. + * + * notifyMode + * This field indicates the action RM should take once the overlay has + * been successfully stopped. The options are (1) Set a notifier + * (2) Set the notifier and generate and OS event + * + * hNotifierCtxDma + * Handle to the ctx dma for the notifier that must be written once + * overlay is stopped. The standard NvNotification notifier structure + * is used. + * + * offset + * Offset within the notifier context dma where the notifier begins + * Offset must be 16 byte aligned. + * + * hEvent + * Handle to the event that RM must use to awaken the client when + * notifyMode is WRITE_AWAKEN. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT: Invalid notify mode + * NV_ERR_INVALID_CHANNEL: When the overlay is unallocated + * NV_ERR_INVALID_OWNER: Callee isn't the owner of the channel + * NV_ERR_INVALID_OBJECT_HANDLE: Notif ctx dma not found + * NV_ERR_INVALID_OFFSET: Bad offset within notif ctx dma + * NV_ERR_INSUFFICIENT_RESOURCES + * NV_ERR_TIMEOUT: RM timedout waiting to inject methods + */ +#define NV5070_CTRL_CMD_STOP_OVERLAY (0x50700102) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_CMD_STOP_OVERLAY_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_STOP_OVERLAY_NOTIFY_MODE_WRITE (0x00000000) +#define NV5070_CTRL_CMD_STOP_OVERLAY_NOTIFY_MODE_WRITE_AWAKEN (0x00000001) + +#define NV5070_CTRL_CMD_STOP_OVERLAY_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV5070_CTRL_CMD_STOP_OVERLAY_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 channelInstance; + NvU32 notifyMode; + NvHandle hNotifierCtxDma; + NvU32 offset; + NV_DECLARE_ALIGNED(NvP64 hEvent, 8); +} NV5070_CTRL_CMD_STOP_OVERLAY_PARAMS; + + + +/* + * NV5070_CTRL_CMD_IS_MODE_POSSIBLE + * + * This command is used by DD to determine whether or not a given mode + * is possible given the current nvclk, mclk, dispclk and potentially some + * other parameters that are normally hidden from it. All the parameters + * except IsPossible (output), Force422(output), MinPstate (input/output), + * minPerfLevel (output), CriticalWatermark (output), worstCaseMargin (output), + * and worstCaseDomain (output) params are supplied by the caller. + * + * HeadActive + * Whether or not the params for this head are relevant. + * + * PixelClock + * Frequency: Pixel clk frequency in KHz. + * Adj1000Div1001: 1000/1001 multiplier for pixel clock. + * + * RasterSize + * Width: Total width of the raster. Also referred to as HTotal. + * Height: Total height of the raster. Also referred to as VTotal. + * + * RasterBlankStart + * X: Start of horizontal blanking for the raster. + * Y: Start of vertical blanking for the raster. + * + * RasterBlankEnd + * X: End of horizontal blanking for the raster. + * Y: End of vertical blanking for the raster. + * + * RasterVertBlank2 + * YStart: Start of second blanking for second field for an + * interlaced raster. This field is irrelevant when raster is + * progressive. + * YEnd: End of second blanking for second field for an + * interlaced raster. This field is irrelevant when raster is + * progressive. + * + * Control + * RasterStructure: Whether the raster ir progressive or interlaced. + * + * OutputScaler + * VerticalTaps: Vertical scaler taps. + * HorizontalTaps: Horizontal scaler taps. + * Force422: Whether OutputScaler is operating in 422 mode or not. + * + * ViewportSizeOut + * Width: Width of output viewport. + * Height: Height of output viewport. + * Both the above fields are irrelevant for G80. + * + * ViewportSizeOutMin + * Width: Minimum possible/expected width of output viewport. + * Height: Minimum possible/expected height of output viewport. + * + * ViewportSizeIn + * Width: Width of input viewport. + * Height: Height of input viewport. + * + * Params + * Format: Core channel's pixel format. See the enumerants following + * the variable declaration for possible options. + * SuperSample: Whether to use X1AA or X4AA in core channel. + * This parameter is ignored for G80. + * + * BaseUsageBounds + * Usable: Whether or not the base channel is expected to be used. + * PixelDepth: Maximum pixel depth allowed in base channel. + * SuperSample: Whether or not X4AA is allowed in base channel. + * BaseLutUsage: Base LUT Size + * OutputLutUsage: Output LUT size + * + * OverlayUsageBounds + * Usable: Whether or not the overlay channel is expected to be used. + * PixelDepth: Maximum pixel depth allowed in overlay channel. + * OverlayLutUsage: Overlay LUT Size + * + * BaseLutLo + * Enable: Specifies Core Channel's Base LUT is enable or not. + * Mode: Specifies the LUT Mode. + * NeverYieldToBase: Specifies whether NEVER_YIELD_TO_BASE is enabled or not. + * + * OutputLutLo + * Enable: Specifies Core Channel's Output LUT is enable or not. + * Mode: Specifies the LUT Mode. + * NeverYieldToBase: Specifies whether NEVER_YIELD_TO_BASE is enabled or not. + * + * outputResourcePixelDepthBPP + * Specifies the output pixel depth with scaler mode. + * + * CriticalWatermark + * If MinPState is set to _NEED_MIN_PSTATE, this will return the critical + * watermark level at the minimum Pstate. Otherwise, this will return + * the critical watermark at the level that the IMP calculations are + * otherwise performed at. + * + * pixelReplicateMode + * Specifies the replication mode whether it is X2 or X4. Need to set the parameter + * to OFF if there is no pixel replication. + * + * numSSTLinks + * Number of Single Stream Transport links which will be used by the + * SOR. "0" means to use the number indicated by the most recent + * NV0073_CTRL_CMD_DP_SINGLE_HEAD_MULTI_STREAM_MODE_SST call. + * + * RequestedOperation + * This parameter is used to determine whether + * 1. DD is simplying querying whether or not the specified mode is + * possible (REQUESTED_OPER = _QUERY) or + * 2. DD is about to set the specified mode and RM should make + * appropriate preparations to make the mode possible. DD should + * never pass in a mode that was never indicated by RM as possible + * when DD queried for the possibility of the mode. This + * corresponds to REQUESTED_OPER = _PRE_MODESET. + * 3. DD just finished setting the specified mode. RM can go ahead + * and make changes like lowering the perf level if desired. This + * corresponds to REQUESTED_OPER = _POST_MODESET. This parameter is + * useful when we are at a higher perf level in a mode that's not + * possible at a lower perf level and want to go to a mode that is + * possible even at a lower perf level. In such cases, lowering + * perf level before modeset is complete is dangerous as it will + * cause underflow. RM will wait until the end of modeset to lower + * the perf level. + * + * options + * Specifies a bitmask for options. + * NV5070_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN + * Tells IMP to calculate worstCaseMargin and worstCaseDomain. + * + * IsPossible + * This is the first OUT param for this call. It indicates whether + * or not the current mode is possible. + * + * MinPState + * MinPState is an IO (in/out) variable; it gives the minimum p-state + * value at which the mode is possible on a PStates 2.0 system if the + * parameter is initialized by the caller with _NEED_MIN_PSTATE. If + * _NEED_MIN_PSTATE is not specified, IMP query will just run at the + * max available perf level and return results for that pstate. + * + * If the minimum pstate is required, then MasterLockMode, + * MasterLockPin, SlaveLockMode, and SlaveLockPin must all be + * initialized. + * + * On a PStates 3.0 system, the return value for MinPState is + * undefined, but minPerfLevel can return the minimum IMP v-pstate. + * + * minPerfLevel + * On a PStates 3.0 system, minPerfLevel returns the minimum IMP + * v-pstate at which the mode is possible. On a PStates 2.0 system, + * minPerfLevel returns the minimum perf level at which the mode is + * possible. + * + * minPerfLevel is valid only if MinPState is initialized to + * _NEED_MIN_PSTATE. + * + * worstCaseMargin + * Returns the ratio of available bandwidth to required bandwidth, + * multiplied by NV5070_CTRL_IMP_MARGIN_MULTIPLIER. Available + * bandwidth is calculated in the worst case bandwidth domain, i.e., + * the domain with the least available margin. Bandwidth domains + * include the IMP-relevant clock domains, and possibly other virtual + * bandwidth domains such as AWP. + * + * Note that IMP checks additional parameters besides the bandwidth + * margins, but only the bandwidth margin is reported here, so it is + * possible for a mode to have a more restrictive domain that is not + * reflected in the reported margin result. + * + * This result is not guaranteed to be valid if the mode is not + * possible. + * + * Note also that the result is generally calculated for the highest + * pstate possible (usually P0). But if _NEED_MIN_PSTATE is specified + * with the MinPState parameter, the result will be calculated for the + * min possible pstate (or the highest possible pstate, if the mode is + * not possible). + * + * The result is valid only if + * NV5070_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN is set in + * "options". + * + * worstCaseDomain + * Returns a short text string naming the domain for the margin + * returned in "worstCaseMargin". See "worstCaseMargin" for more + * information. + * + * bUseCachedPerfState + * Indicates that RM should use cached values for the fastest + * available perf level (v-pstate for PStates 3.0 or pstate for + * PStates 2.0) and dispclk. This feature allows the query call to + * execute faster, and is intended to be used, for example, during + * mode enumeration, when many IMP query calls are made in close + * succession, and perf conditions are not expected to change between + * query calls. When IMP has not been queried recently, it is + * recommended to NOT use cached values, in case perf conditions have + * changed and the cached values no longer reflect the current + * conditions. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * + * Assumptions/Limitations: + * - If the caller sends any methods to alter the State Cache, before calling of + * the following functions: + * NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_QUERY_USE_SC + * NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_PRE_MODESET_USE_SC + * NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_POST_MODESET_USE_SC + * the caller must repeatedly issue NV5070_CTRL_CMD_GET_CHANNEL_INFO, and delay until the + * returned channelState is either: + * NV5070_CTRL_CMD_GET_CHANNEL_INFO_STATE_IDLE, + * NV5070_CTRL_CMD_GET_CHANNEL_INFO_STATE_WRTIDLE, or + * NV5070_CTRL_CMD_GET_CHANNEL_INFO_STATE_EMPTY. + * This ensures that all commands have reached the State Cache before RM reads + * them. + * + * + */ +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE (0x50700109) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_QUERY (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_PRE_MODESET (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_POST_MODESET (0x00000002) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_QUERY_USE_SC (0x00000003) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_PRE_MODESET_USE_SC (0x00000004) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_POST_MODESET_USE_SC (0x00000005) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_SUPERVISOR (0x00000007) + +#define NV5070_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN (0x00000001) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_IS_POSSIBLE_NO (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_IS_POSSIBLE_YES (0x00000001) + +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_UNDEFINED (0x00000000) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P0 (0x00000001) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P1 (0x00000002) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P2 (0x00000004) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P3 (0x00000008) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P8 (0x00000100) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P10 (0x00000400) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P12 (0x00001000) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P15 (0x00008000) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_MAX NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P15 +#define NV5070_CTRL_IS_MODE_POSSIBLE_NEED_MIN_PSTATE (0x10101010) +#define NV5070_CTRL_IS_MODE_POSSIBLE_NEED_MIN_PSTATE_DEFAULT (0x00000000) + +#define NV5070_CTRL_IMP_MARGIN_MULTIPLIER (0x00000400) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_HEAD_ACTIVE_NO (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_HEAD_ACTIVE_YES (0x00000001) + +#define NV5070_CTRL_IS_MODE_POSSIBLE_DISPLAY_ID_SKIP_IMP_OUTPUT_CHECK (0xAAAAAAAA) + +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000009) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PIXEL_CLOCK_ADJ1000DIV1001_NO (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PIXEL_CLOCK_ADJ1000DIV1001_YES (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_CONTROL_STRUCTURE_INTERLACED (0x00000001) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_VERTICAL_TAPS_1 (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_VERTICAL_TAPS_2 (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_VERTICAL_TAPS_3 (0x00000002) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_VERTICAL_TAPS_3_ADAPTIVE (0x00000003) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_VERTICAL_TAPS_5 (0x00000004) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_HORIZONTAL_TAPS_1 (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_HORIZONTAL_TAPS_2 (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_HORIZONTAL_TAPS_8 (0x00000002) + +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_SCALER_FORCE422_MODE_DISABLE (0x00000000) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_SCALER_FORCE422_MODE_ENABLE (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_I8 (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_VOID16 (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_VOID32 (0x00000002) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x00000003) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_A8R8G8B8 (0x00000004) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_A2B10G10R10 (0x00000005) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_A8B8G8R8 (0x00000006) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_R5G6B5 (0x00000007) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_A1R5G5B5 (0x00000008) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_SUPER_SAMPLE_X1AA (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_SUPER_SAMPLE_X4AA (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_USABLE_USE_CURRENT (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_USABLE_NO (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_USABLE_YES (0x00000002) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_PIXEL_DEPTH_USE_CURRENT (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_PIXEL_DEPTH_8 (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_PIXEL_DEPTH_16 (0x00000002) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_PIXEL_DEPTH_32 (0x00000003) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_PIXEL_DEPTH_64 (0x00000004) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_SUPER_SAMPLE_USE_CURRENT (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_SUPER_SAMPLE_X1AA (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_SUPER_SAMPLE_X4AA (0x00000002) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_BASE_LUT_USAGE_NONE (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_BASE_LUT_USAGE_257 (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_BASE_LUT_USAGE_1025 (0x00000002) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_USABLE_USE_CURRENT (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_USABLE_NO (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_USABLE_YES (0x00000002) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_USE_CURRENT (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_16 (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_32 (0x00000002) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_64 (0x00000003) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257 (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025 (0x00000002) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000002) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000003) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000004) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000005) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000006) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000007) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000002) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000003) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000004) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000005) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000006) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000007) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PIXEL_REPLICATE_MODE_X4 (0x00000002) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + struct { + NvU32 HeadActive; + struct { + NvU32 Frequency; + + NvU32 Adj1000Div1001; + } PixelClock; + + struct { + NvU32 Width; + NvU32 Height; + } RasterSize; + + struct { + NvU32 X; + NvU32 Y; + } RasterBlankStart; + + struct { + NvU32 X; + NvU32 Y; + } RasterBlankEnd; + + struct { + NvU32 YStart; + NvU32 YEnd; + } RasterVertBlank2; + + struct { + NvU32 Structure; +/* + * Note: For query calls, the lock modes and lock pins are used only if the min + * pstate is required (i.e., if MinPState is set to + * NV5070_CTRL_IS_MODE_POSSIBLE_NEED_MIN_PSTATE). + */ + NV_DISP_LOCK_MODE MasterLockMode; + NV_DISP_LOCK_PIN MasterLockPin; + NV_DISP_LOCK_MODE SlaveLockMode; + NV_DISP_LOCK_PIN SlaveLockPin; + } Control; + + struct { + NvU32 VerticalTaps; + NvU32 HorizontalTaps; + NvBool Force422; + } OutputScaler; + + struct { + NvU32 Width; + NvU32 Height; + } ViewportSizeOut; + + struct { + NvU32 Width; + NvU32 Height; + } ViewportSizeOutMin; + + struct { + NvU32 Width; + NvU32 Height; + } ViewportSizeOutMax; + + struct { + NvU32 Width; + NvU32 Height; + } ViewportSizeIn; + + struct { + NvU32 Format; + NvU32 SuperSample; + } Params; + + struct { + NvU32 Usable; + NvU32 PixelDepth; + NvU32 SuperSample; + NvU32 BaseLutUsage; + NvU32 OutputLutUsage; + } BaseUsageBounds; + + struct { + NvU32 Usable; + NvU32 PixelDepth; + NvU32 OverlayLutUsage; + } OverlayUsageBounds; + + struct { + NvBool Enable; + NvU32 Mode; + NvBool NeverYieldToBase; + } BaseLutLo; + + struct { + NvBool Enable; + NvU32 Mode; + NvBool NeverYieldToBase; + } OutputLutLo; + + NvU32 displayId[NV5070_CTRL_CMD_NUM_DISPLAY_ID_DWORDS_PER_HEAD]; + NvU32 outputResourcePixelDepthBPP; + + NvU32 CriticalWatermark; // in pixels + + } Head[NV5070_CTRL_CMD_MAX_HEADS]; + + struct { + NvU32 owner; + NvU32 protocol; + } Dac[NV5070_CTRL_CMD_MAX_DACS]; + + struct { +// +// owner field is deprecated. In the future, all client calls should set +// ownerMask and bUseSorOwnerMask. bUseSorOwnerMask must be set in order +// to use ownerMask. +// + NvU32 owner; + NvU32 ownerMask; // Head mask owned this sor + + NvU32 protocol; + NvU32 pixelReplicateMode; + + NvU8 numSSTLinks; + } Sor[NV5070_CTRL_CMD_MAX_SORS]; + + NvBool bUseSorOwnerMask; + + struct { + NvU32 owner; + NvU32 protocol; + } Pior[NV5070_CTRL_CMD_MAX_PIORS]; + + + NvU32 RequestedOperation; +// This argument is for VERIF and INTERNAL use only + NvU32 options; + NvU32 IsPossible; + NvU32 MinPState; + + NvU32 minPerfLevel; +// +// Below are the possible Output values for MinPState variable. +// Lower the p-state value higher the power consumption; if no p-states are defined on chip +// then it will return as zero. +// + +// +// Below are the possible input values for MinPstate Variable, by default it calculate +// mode is possible or not at max available p-state and return the same state in that variable. +// + NvU32 worstCaseMargin; + +// +// The calculated margin is multiplied by a constant, so that it can be +// represented as an integer with reasonable precision. "0x400" was chosen +// because it is a power of two, which might allow some compilers/CPUs to +// simplify the calculation by doing a shift instead of a multiply/divide. +// (And 0x400 is 1024, which is close to 1000, so that may simplify visual +// interpretation of the raw margin value.) +// + char worstCaseDomain[8]; + + NvBool bUseCachedPerfState; +} NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS; + + + +/* + * NV5070_CTRL_CMD_GET_CHANNEL_INFO + * + * This command returns the current channel state. + * + * channelClass + * This field indicates the hw class number (507A-507E) + * + * channelInstance + * This field indicates which of the two instances of the channel + * (in case there are two. ex: base, overlay etc) the cmd is meant for. + * Note that core channel has only one instance and the field should + * be set to 0 for core channel. + * + * channelState + * This field indicates the desired channel state in a mask form that + * is compatible with NV5070_CTRL_CMD_IDLE_CHANNEL. A mask format + * allows clients to check for one from a group of states. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + * + * Display driver uses this call to ensure that all it's methods have + * propagated through hardware's internal fifo + * (NV5070_CTRL_GET_CHANNEL_INFO_STATE_NO_METHOD_PENDING) before it calls + * RM to check whether or not the mode it set up in Assembly State Cache will + * be possible. Note that display driver can not use completion notifier in + * this case because completion notifier is associated with Update and Update + * will propagate the state from Assembly to Armed and when checking the + * possibility of a mode, display driver wouldn't want Armed state to be + * affected. + */ +#define NV5070_CTRL_CMD_GET_CHANNEL_INFO (0x5070010b) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_CHANNEL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_IDLE NV5070_CTRL_CMD_CHANNEL_STATE_IDLE +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_WRTIDLE NV5070_CTRL_CMD_CHANNEL_STATE_WRTIDLE +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_EMPTY NV5070_CTRL_CMD_CHANNEL_STATE_EMPTY +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_FLUSHED NV5070_CTRL_CMD_CHANNEL_STATE_FLUSHED +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_BUSY NV5070_CTRL_CMD_CHANNEL_STATE_BUSY +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_DEALLOC NV5070_CTRL_CMD_CHANNEL_STATE_DEALLOC +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_DEALLOC_LIMBO NV5070_CTRL_CMD_CHANNEL_STATE_DEALLOC_LIMBO +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_LIMBO1 NV5070_CTRL_CMD_CHANNEL_STATE_LIMBO1 +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_LIMBO2 NV5070_CTRL_CMD_CHANNEL_STATE_LIMBO2 +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_FCODEINIT NV5070_CTRL_CMD_CHANNEL_STATE_FCODEINIT +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_FCODE NV5070_CTRL_CMD_CHANNEL_STATE_FCODE +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_VBIOSINIT NV5070_CTRL_CMD_CHANNEL_STATE_VBIOSINIT +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_VBIOSOPER NV5070_CTRL_CMD_CHANNEL_STATE_VBIOSOPER +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_UNCONNECTED NV5070_CTRL_CMD_CHANNEL_STATE_UNCONNECTED +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_INITIALIZE NV5070_CTRL_CMD_CHANNEL_STATE_INITIALIZE +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_SHUTDOWN1 NV5070_CTRL_CMD_CHANNEL_STATE_SHUTDOWN1 +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_SHUTDOWN2 NV5070_CTRL_CMD_CHANNEL_STATE_SHUTDOWN2 +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_NO_METHOD_PENDING (NV5070_CTRL_GET_CHANNEL_INFO_STATE_EMPTY | NV5070_CTRL_GET_CHANNEL_INFO_STATE_WRTIDLE | NV5070_CTRL_GET_CHANNEL_INFO_STATE_IDLE) +#define NV5070_CTRL_CMD_GET_CHANNEL_INFO_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV5070_CTRL_CMD_GET_CHANNEL_INFO_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 channelClass; + NvU32 channelInstance; + NvBool IsChannelInDebugMode; + + NvU32 channelState; +} NV5070_CTRL_CMD_GET_CHANNEL_INFO_PARAMS; + + + +/* + * NV5070_CTRL_CMD_SET_ACCL + * + * This command turns accelerators on and off. The use of this command + * should be restricted as it may have undesirable effects. It's + * purpose is to provide a mechanism for clients to use the + * accelerator bits to get into states that are either not detectable + * by the RM or may take longer to reach than we think is reasonable + * to wait in the RM. + * + * NV5070_CTRL_CMD_GET_ACCL + * + * This command queries the current state of the accelerators. + * + * channelClass + * This field indicates the hw class number (507A-507E) + * + * channelInstance + * This field indicates which of the two instances of the channel + * (in case there are two. ex: base, overlay etc) the cmd is meant for. + * Note that core channel has only one instance and the field should + * be set to 0 for core channel. + * + * accelerators + * Accelerators to be set in the SET_ACCEL command. Returns the + * currently set accelerators on the GET_ACCEL command. + * + * accelMask + * A mask to specify which accelerators to change with the + * SET_ACCEL command. This field does nothing in the GET_ACCEL + * command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_CHANNEL + * NV_ERR_INVALID_OWNER + * NV_ERR_GENERIC + * + */ + +#define NV5070_CTRL_CMD_SET_ACCL (0x5070010c) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_SET_ACCL_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_ACCL (0x5070010d) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_GET_ACCL_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_ACCL_NONE NV5070_CTRL_IDLE_CHANNEL_ACCL_NONE +#define NV5070_CTRL_ACCL_IGNORE_PI NV5070_CTRL_IDLE_CHANNEL_ACCL_IGNORE_PI +#define NV5070_CTRL_ACCL_SKIP_NOTIF NV5070_CTRL_IDLE_CHANNEL_ACCL_SKIP_NOTIF +#define NV5070_CTRL_ACCL_SKIP_SEMA NV5070_CTRL_IDLE_CHANNEL_ACCL_SKIP_SEMA +#define NV5070_CTRL_ACCL_IGNORE_INTERLOCK NV5070_CTRL_IDLE_CHANNEL_ACCL_IGNORE_INTERLOCK +#define NV5070_CTRL_ACCL_IGNORE_FLIPLOCK NV5070_CTRL_IDLE_CHANNEL_ACCL_IGNORE_FLIPLOCK +#define NV5070_CTRL_ACCL_TRASH_ONLY NV5070_CTRL_IDLE_CHANNEL_ACCL_TRASH_ONLY +#define NV5070_CTRL_ACCL_TRASH_AND_ABORT NV5070_CTRL_IDLE_CHANNEL_ACCL_TRASH_AND_ABORT +#define NV5070_CTRL_SET_ACCL_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV5070_CTRL_SET_ACCL_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 channelClass; + NvU32 channelInstance; + + NvU32 accelerators; + NvU32 accelMask; +} NV5070_CTRL_SET_ACCL_PARAMS; +#define NV5070_CTRL_GET_ACCL_PARAMS_MESSAGE_ID (0xDU) + +typedef NV5070_CTRL_SET_ACCL_PARAMS NV5070_CTRL_GET_ACCL_PARAMS; + +/* + * NV5070_CTRL_CMD_STOP_BASE + * + * This command tries to turn the base channel off ASAP. + * + * channelInstance + * This field indicates which of the two instances of the base + * channel the cmd is meant for. + * + * notifyMode + * This field indicates the action RM should take once the base + * channel has been successfully stopped. The options are (1) Set a + * notifier (2) Set the notifier and generate and OS event + * + * hNotifierCtxDma + * Handle to the ctx dma for the notifier that must be written once + * base channel is stopped. The standard NvNotification notifier + * structure is used. + * + * offset + * Offset within the notifier context dma where the notifier begins + * Offset must be 16 byte aligned. + * + * hEvent + * Handle to the event that RM must use to awaken the client when + * notifyMode is WRITE_AWAKEN. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT: Invalid notify mode + * NV_ERR_INVALID_CHANNEL: When the overlay is unallocated + * NV_ERR_INVALID_OWNER: Callee isn't the owner of the channel + * NV_ERR_INVALID_OBJECT_HANDLE: Notif ctx dma not found + * NV_ERR_INVALID_OFFSET: Bad offset within notif ctx dma + * NV_ERR_INSUFFICIENT_RESOURCES + * NV_ERR_TIMEOUT: RM timedout waiting to inject methods + */ +#define NV5070_CTRL_CMD_STOP_BASE (0x5070010e) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_CMD_STOP_BASE_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_STOP_BASE_NOTIFY_MODE_WRITE (0x00000000) +#define NV5070_CTRL_CMD_STOP_BASE_NOTIFY_MODE_WRITE_AWAKEN (0x00000001) + +#define NV5070_CTRL_CMD_STOP_BASE_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV5070_CTRL_CMD_STOP_BASE_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 channelInstance; + NvU32 notifyMode; + NvHandle hNotifierCtxDma; + NvU32 offset; + NV_DECLARE_ALIGNED(NvP64 hEvent, 8); +} NV5070_CTRL_CMD_STOP_BASE_PARAMS; + + + +/* + * NV5070_CTRL_CMD_GET_PINSET_COUNT + * + * Get number of pinsets on this GPU. + * + * pinsetCount [out] + * Number of pinsets on this GPU is returned in this parameter. + * This count includes pinsets that are not connected. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV5070_CTRL_CMD_GET_PINSET_COUNT (0x50700115) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_GET_PINSET_COUNT_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_GET_PINSET_COUNT_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV5070_CTRL_GET_PINSET_COUNT_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 pinsetCount; +} NV5070_CTRL_GET_PINSET_COUNT_PARAMS; + +/* + * NV5070_CTRL_CMD_GET_PINSET_PEER + * + * Retrieve the pinset/GPU that is connected to the specified pinset on + * this GPU. + * + * pinset [in] + * Pinset on this GPU for which peer info is to be returned must be + * specified in this parameter. + * + * peerGpuId [out] + * Instance of the GPU on the other side of the connection is + * returned in this parameter. + * + * peerPinset [out] + * Pinset on the other side of the connection is returned in this + * parameter. If there is no connection then the value is + * NV5070_CTRL_CMD_GET_PINSET_PEER_PEER_PINSET_NONE. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV5070_CTRL_CMD_GET_PINSET_PEER (0x50700116) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_GET_PINSET_PEER_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_PINSET_PEER_PEER_GPUINSTANCE_NONE (0xffffffff) + +#define NV5070_CTRL_CMD_GET_PINSET_PEER_PEER_PINSET_NONE (0xffffffff) + +#define NV5070_CTRL_GET_PINSET_PEER_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV5070_CTRL_GET_PINSET_PEER_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 pinset; + + NvU32 peerGpuInstance; + NvU32 peerPinset; +} NV5070_CTRL_GET_PINSET_PEER_PARAMS; + +/* + * NV5070_CTRL_CMD_SET_RMFREE_FLAGS + * + * This command sets the flags for an upcoming call to RmFree(). + * After the RmFree() API runs successfully or not, the flags are cleared. + * + * flags + * This parameter holds the NV0000_CTRL_GPU_SET_RMFREE_FLAGS_* + * flags to be passed for the next RmFree() command only. + * The flags can be one of those: + * - NV0000_CTRL_GPU_SET_RMFREE_FLAGS_NONE: + * explicitly clears the flags + * - NV0000_CTRL_GPU_SET_RMFREE_FLAGS_FREE_PRESERVES_HW: + * instructs RmFree() to preserve the HW configuration. After + * RmFree() is run this flag is cleared. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV5070_CTRL_CMD_SET_RMFREE_FLAGS (0x50700117) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_SET_RMFREE_FLAGS_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_SET_RMFREE_FLAGS_NONE 0x00000000 +#define NV5070_CTRL_SET_RMFREE_FLAGS_PRESERVE_HW 0x00000001 +#define NV5070_CTRL_SET_RMFREE_FLAGS_PARAMS_MESSAGE_ID (0x17U) + +typedef struct NV5070_CTRL_SET_RMFREE_FLAGS_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 flags; +} NV5070_CTRL_SET_RMFREE_FLAGS_PARAMS; + + +/* + * NV5070_CTRL_CMD_IMP_SET_GET_PARAMETER + * + * This command allows to set or get certain IMP parameters. Change of + * values take effect on next modeset and is persistent across modesets + * until the driver is unloaded or user changes the override. + * + * index + * One of NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_XXX defines - + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IMP_ENABLE + * Only supports "get" operation. If FALSE, IMP is being bypassed and + * all Is Mode Possible queries are answered with "mode is possible" + * and registers normally set by IMP are not changed from their defaults. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED + * Should IMP consider using ASR. ASR won't be allowed unless it is set to + * "allowed" through both _IS_ASR_ALLOWED and _IS_ASR_ALLOWED_PER_PSTATE. + * Note that IMP will not run ASR and MSCG at the same time. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED_PER_PSTATE + * Should IMP consider using ASR when this pstate is being used. ASR won't + * be allowed unless it is set to "allowed" through both + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED and + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED_PER_PSTATE. + * So when NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED + * returns FALSE, IMP won't consider ASR for any p-state. Note that IMP + * will not run ASR and MSCG at the same time. This function is valid + * only on PStates 2.0 systems. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_MSCG_ALLOWED_PER_PSTATE + * Should IMP consider using MSCG when this pstate is being used. MSCG + * won't be allowed if the MSCG feature isn't enabled even if we set to + * "allowed" through + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_MSCG_ALLOWED_PER_PSTATE. + * Use NV2080_CTRL_CMD_MC_QUERY_POWERGATING_PARAMETER to query if MSCG is + * supported and enabled. Note that IMP will not run ASR and MSCG at the + * same time. This function is valid only on PStates 2.0 systems. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_STUTTER_FEATURE_PER_PSTATE + * Only supports "get" operation. Returns which stutter feature is being + * engaged in hardware when running on the given pstate. Valid values are: + * NV5070_CTRL_IMP_STUTTER_FEATURE_NONE + * This value indicates no stutter feature is enabled. + * NV5070_CTRL_IMP_STUTTER_FEATURE_ASR + * This value indicates ASR is the current enabled stutter feature. + * NV5070_CTRL_IMP_STUTTER_FEATURE_MSCG + * This value indicates MSCG is the current enabled stutter feature. + * Note that system will not run ASR and MSCG at the same time. This + * function is valid only on PStates 2.0 systems. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_STUTTER_FEATURE_PREDICTED_EFFICIENCY_PER_PSTATE + * Only supports "get" operation. Returns the efficiency which IMP + * predicted for the engaged stutter feature (ASR or MSCG) when running + * on the given pstate. Normally, the actual efficiency should be higher + * than the calculated predicted efficiency. For MSCG, the predicted + * efficiency assumes no mempool compression. If compression is enabled + * with MSCG, the actual efficiency may be significantly higher. Returns + * 0 if no stutter feature is running. On PStates 3.0 systems, the + * pstateApi parameter is ignored, and the result is returned for the min + * IMP v-pstate possible. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS + * Only supports "get" operation. Returns information about what the possible + * mclk switch is. Valid fields are: + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_POSSIBLE + * This field is not head-specific and indicates if mclk switch is + * possible with the current mode. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_OVERRIDE_MEMPOOL + * This field is not head-specific and indicates if mclk switch is + * possible with the nominal mempool settings (_NO) or if special + * settings are required in order for mclk switch to be possible (_YES). + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_MID_WATERMARK + * Each head has its own setting for this field. If this field is + * set to _YES, then the specified head will allow mclk switch to + * begin if mempool occupancy exceeds the MID_WATERMARK setting. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_DWCF + * Each head has its own setting for this field. If this field is + * set to _YES, then the specified head will allow mclk switch to + * begin if the head is in its DWCF interval, and the mempool + * occupancy is greater than or equal to the DWCF watermark. + * Note: If neither _MID_WATERMARK nor _DWCF is set to _YES, then the + * specified head is ignored when determining when it is OK to start an + * mclk switch. Mclk switch must be allowed (or ignored) by all heads + * before an mclk switch will actually begin. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_FORCE_MIN_MEMPOOL + * Should min mempool be forced. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MEMPOOL_COMPRESSION + * Should mempool compression be enabled. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_CURSOR_SIZE + * The cursor size (in horizontal pixels) used by IMP (rather than the + * actual cursor size) for its computation. + * A maximum value is in place for what can be set. It can be queried + * after resetting the value - it gets reset to the maximum possible + * value. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_ENABLE + * This is to Enable/Disable ISO FB Latency Test. + * The test records the max ISO FB latency for all heads during the test period (excluding modeset time). + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_WC_TOTAL_LATENCY + * This is used to retrieve calculated wcTotalLatency of ISO FB Latency Test. + * wcTotalLatency is the worst case time for a request's data to come back after the request is issued. + * It is the sum of IMP calculated FbLatency and stream delay. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_MAX_LATENCY + * This is used to retrieve the max latency among all heads during the whole ISO FB Latency Test. + * The max latency can be used to compare with the wcTotalLatency we calculated. + * It decides whether the ISO FB Latency Test is passed or not. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_MAX_TEST_PERIOD + * This is used to retrieve the max test period during the whole ISO FB Latency Test. + * By experimental result, the test period should be at least 10 secs to approximate the + * worst case Fb latency in real situation. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_GLITCHLESS_MODESET_ENABLE + * This enables or disables glitchless modesets. Modesets can be + * glitchless if: + * (1) There are no raster timing changes, and + * (2) The resource requirements of all bandwidth clients are either not + * changing, or they are all changing in the same direction (all + * increasing or all decreasing). + * If glitchless modeset is disabled, or is not possible, heads will be + * blanked during the modeset transition. + * pstateApi + * NV2080_CTRL_PERF_PSTATES_PXXX value. + * Required for NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED_PER_PSTATE, + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_MSCG_ALLOWED_PER_PSTATE, + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_STUTTER_FEATURE_PER_PSTATE and + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_STUTTER_FEATURE_PREDICTED_EFFICIENCY_PER_PSTATE + * on PStates 2.0 systems. For other indices must be + * NV2080_CTRL_PERF_PSTATES_UNDEFINED. Not used on PStates 3.0 systems. + * head + * Head index, which is required when querying Mclk switch feature. + * (index = NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS) + * operation + * NV5070_CTRL_IMP_SET_GET_PARAMETER_OPERATION_GET + * Indicates a "get" operation. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_OPERATION_SET + * Indicates a "set" operation. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_OPERATION_RESET + * Indicates a "reset" operation. This operation will reset the values for + * all indices to their RM defaults. + * value + * Value for new setting of a "set" operation, or the returned value of a + * "get" operation; for enable/disable operations, "enable" is non-zero, + * and "disable" is zero. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_POINTER + * NV_ERR_INVALID_INDEX specified index is not supported + * NV_ERR_INSUFFICIENT_RESOURCES cannot handle any more overrides + * NV_ERR_INVALID_OBJECT the struct needed to get the specified information + * is not marked as valid + * NV_ERR_INVALID_STATE the parameter has been set but resetting will + * not be possible + */ +#define NV5070_CTRL_CMD_IMP_SET_GET_PARAMETER (0x50700118) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_IMP_SET_GET_PARAMETER_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV5070_CTRL_IMP_SET_GET_PARAMETER_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 index; + NvU32 pstateApi; + NvU32 head; + NvU32 operation; + NvU32 value; +} NV5070_CTRL_IMP_SET_GET_PARAMETER_PARAMS; + +/* valid operation values */ +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_OPERATION_GET 0 +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_OPERATION_SET 1 +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_OPERATION_RESET 2 + +/* valid index value */ +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_NONE (0x00000000) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IMP_ENABLE (0x00000001) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED (0x00000002) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED_PER_PSTATE (0x00000003) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_MSCG_ALLOWED_PER_PSTATE (0x00000004) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_STUTTER_FEATURE_PER_PSTATE (0x00000005) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_STUTTER_FEATURE_PREDICTED_EFFICIENCY_PER_PSTATE (0x00000006) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS (0x00000007) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_FORCE_MIN_MEMPOOL (0x00000008) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MEMPOOL_COMPRESSION (0x00000009) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_CURSOR_SIZE (0x0000000A) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_ENABLE (0x0000000B) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_WC_TOTAL_LATENCY (0x0000000C) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_MAX_LATENCY (0x0000000D) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_MAX_TEST_PERIOD (0x0000000E) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_GLITCHLESS_MODESET_ENABLE (0x0000000F) + +/* valid NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOHUB_STUTTER_FEATURE values */ +#define NV5070_CTRL_IMP_STUTTER_FEATURE_NONE 0 +#define NV5070_CTRL_IMP_STUTTER_FEATURE_ASR 1 +#define NV5070_CTRL_IMP_STUTTER_FEATURE_MSCG 2 + +/* valid NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE values */ +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_POSSIBLE 0:0 +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_POSSIBLE_NO (0x00000000) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_POSSIBLE_YES (0x00000001) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_OVERRIDE_MEMPOOL 1:1 +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_OVERRIDE_MEMPOOL_NO (0x00000000) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_OVERRIDE_MEMPOOL_YES (0x00000001) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_MID_WATERMARK 2:2 +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_MID_WATERMARK_NO (0x00000000) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_MID_WATERMARK_YES (0x00000001) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_DWCF 3:3 +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_DWCF_NO (0x00000000) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_DWCF_YES (0x00000001) + +/* + * NV5070_CTRL_CMD_SET_MEMPOOL_WAR_FOR_BLIT_TEARING + * + * This command engages the WAR for blit tearing caused by huge mempool size and + * mempool compression. The EVR in aero off mode uses scanline info to predict + * where the scanline will be at a later time. Since RG scanline is used to perform + * front buffer blits and isohub buffers large amount of display data it may have + * fetched several lines of data ahead of where the RG is scanning out leading to + * video tearing. The WAR for this problem is to reduce the amount of data fetched. + * + * base + * This struct must be the first member of all 5070 control calls containing + * the subdeviceIndex. + * bEngageWAR + * Indicates if mempool WAR has to be engaged or disengaged. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV5070_CTRL_CMD_SET_MEMPOOL_WAR_FOR_BLIT_TEARING (0x50700119) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_SET_MEMPOOL_WAR_FOR_BLIT_TEARING_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_SET_MEMPOOL_WAR_FOR_BLIT_TEARING_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV5070_CTRL_SET_MEMPOOL_WAR_FOR_BLIT_TEARING_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvBool bEngageWAR; +} NV5070_CTRL_SET_MEMPOOL_WAR_FOR_BLIT_TEARING_PARAMS; +typedef struct NV5070_CTRL_SET_MEMPOOL_WAR_FOR_BLIT_TEARING_PARAMS *PNV5070_CTRL_SET_MEMPOOL_WAR_FOR_BLIT_TEARING_PARAMS; + +#define NV5070_CTRL_CMD_GET_ACTIVE_VIEWPORT_BASE (0x50700120) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_ACTIVE_VIEWPORT_BASE_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_ACTIVE_VIEWPORT_BASE_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV5070_CTRL_CMD_GET_ACTIVE_VIEWPORT_BASE_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 head; + NvU32 activeViewportBase; +} NV5070_CTRL_CMD_GET_ACTIVE_VIEWPORT_BASE_PARAMS; +typedef struct NV5070_CTRL_CMD_GET_ACTIVE_VIEWPORT_BASE_PARAMS *PNV5070_CTRL_CMD_GET_ACTIVE_VIEWPORT_BASE_PARAMS; + +/* _ctrl5070chnc_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070common.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070common.h new file mode 100644 index 0000000..bbfa794 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070common.h @@ -0,0 +1,79 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070common.finn +// + + + +#define NV5070_CTRL_CMD_CHANNEL_STATE_IDLE NVBIT(0) +#define NV5070_CTRL_CMD_CHANNEL_STATE_WRTIDLE NVBIT(1) +#define NV5070_CTRL_CMD_CHANNEL_STATE_QUIESCENT1 NVBIT(2) +#define NV5070_CTRL_CMD_CHANNEL_STATE_QUIESCENT2 NVBIT(3) +#define NV5070_CTRL_CMD_CHANNEL_STATE_EMPTY NVBIT(4) +#define NV5070_CTRL_CMD_CHANNEL_STATE_FLUSHED NVBIT(5) +#define NV5070_CTRL_CMD_CHANNEL_STATE_BUSY NVBIT(6) +#define NV5070_CTRL_CMD_CHANNEL_STATE_DEALLOC NVBIT(7) +#define NV5070_CTRL_CMD_CHANNEL_STATE_DEALLOC_LIMBO NVBIT(8) +#define NV5070_CTRL_CMD_CHANNEL_STATE_LIMBO1 NVBIT(9) +#define NV5070_CTRL_CMD_CHANNEL_STATE_LIMBO2 NVBIT(10) +#define NV5070_CTRL_CMD_CHANNEL_STATE_FCODEINIT NVBIT(11) +#define NV5070_CTRL_CMD_CHANNEL_STATE_FCODE NVBIT(12) +#define NV5070_CTRL_CMD_CHANNEL_STATE_VBIOSINIT NVBIT(13) +#define NV5070_CTRL_CMD_CHANNEL_STATE_VBIOSOPER NVBIT(14) +#define NV5070_CTRL_CMD_CHANNEL_STATE_UNCONNECTED NVBIT(15) +#define NV5070_CTRL_CMD_CHANNEL_STATE_INITIALIZE NVBIT(16) +#define NV5070_CTRL_CMD_CHANNEL_STATE_SHUTDOWN1 NVBIT(17) +#define NV5070_CTRL_CMD_CHANNEL_STATE_SHUTDOWN2 NVBIT(18) +#define NV5070_CTRL_CMD_CHANNEL_STATE_INIT NVBIT(19) + +#define NV5070_CTRL_CMD_MAX_HEADS 4U +#define NV5070_CTRL_CMD_MAX_DACS 4U +#define NV5070_CTRL_CMD_MAX_SORS 8U +#define NV5070_CTRL_CMD_MAX_PIORS 4U + +#define NV5070_CTRL_CMD_OR_OWNER_NONE (0xFFFFFFFFU) +#define NV5070_CTRL_CMD_OR_OWNER_HEAD(i) (i) +#define NV5070_CTRL_CMD_OR_OWNER_HEAD__SIZE_1 NV5070_CTRL_CMD_MAX_HEADS + +#define NV5070_CTRL_CMD_SOR_OWNER_MASK_NONE (0x00000000U) +#define NV5070_CTRL_CMD_SOR_OWNER_MASK_HEAD(i) (1 << i) + +#define NV5070_CTRL_CMD_DAC_PROTOCOL_RGB_CRT (0x00000000U) + + + +#define NV5070_CTRL_CMD_SOR_PROTOCOL_SINGLE_TMDS_A (0x00000000U) +#define NV5070_CTRL_CMD_SOR_PROTOCOL_SINGLE_TMDS_B (0x00000001U) +#define NV5070_CTRL_CMD_SOR_PROTOCOL_DUAL_TMDS (0x00000002U) +#define NV5070_CTRL_CMD_SOR_PROTOCOL_LVDS_CUSTOM (0x00000003U) +#define NV5070_CTRL_CMD_SOR_PROTOCOL_DP_A (0x00000004U) +#define NV5070_CTRL_CMD_SOR_PROTOCOL_DP_B (0x00000005U) +#define NV5070_CTRL_CMD_SOR_PROTOCOL_SUPPORTED (0xFFFFFFFFU) + +#define NV5070_CTRL_CMD_PIOR_PROTOCOL_EXT_TMDS_ENC (0x00000000U) + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070event.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070event.h new file mode 100644 index 0000000..5154638 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070event.h @@ -0,0 +1,143 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070event.finn +// + +#include "ctrl/ctrl5070/ctrl5070base.h" + +/* NV50_DISPLAY event-related control commands and parameters */ + +/* + * NV5070_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * This command sets event notification state for the NV50_DISPLAY object. + * This command requires that an instance of NV01_EVENT has been previously + * bound to the NV50_DISPLAY object. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the NV50_DISPLAY + * parent device to which the operation should be directed. This parameter + * must specify a value between zero and the total number of subdevices + * within the parent device. This parameter should be set to zero for + * default behavior. + * hEvent + * This parameter specifies the handle of the NV01_EVENT instance + * to be bound to the given subDeviceInstance. + * event + * This parameter specifies the type of event to which the specified + * action is to be applied. This parameter must specify a valid + * NOTIFIERS value of display class. + * action + * This parameter specifies the desired event notification action. + * Valid notification actions include: + * NV5070_CTRL_SET_EVENT_NOTIFICATION_DISABLE + * This action disables event notification for the specified + * event for the associated subdevice object. + * NV5070_CTRL_SET_EVENT_NOTIFICATION_SINGLE + * This action enables single-shot event notification for the + * specified event for the associated subdevice object. + * NV5070_CTRL_SET_EVENT_NOTIFICATION_REPEAT + * This action enables repeated event notification for the specified + * event for the associated system controller object. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV5070_CTRL_CMD_EVENT_SET_NOTIFICATION (0x50700901) /* finn: Evaluated from "(FINN_NV50_DISPLAY_EVENT_INTERFACE_ID << 8) | NV5070_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV5070_CTRL_EVENT_SET_NOTIFICATION_PARAMS { + NvU32 subDeviceInstance; + NvHandle hEvent; + NvU32 event; + NvU32 action; +} NV5070_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001) +#define NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002) + + +/* + * NV5070_CTRL_CMD_EVENT_SET_TRIGGER + * + * This command triggers a software event for the NV50_DISPLAY object. + * This command accepts no parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV5070_CTRL_CMD_EVENT_SET_TRIGGER (0x50700902) /* finn: Evaluated from "(FINN_NV50_DISPLAY_EVENT_INTERFACE_ID << 8) | 0x2" */ + + +/* + * NV5070_CTRL_CMD_EVENT_SET_NOTIFIER_MEMORY + * + * hMemory + * This parameter specifies the handle of the memory object + * that identifies the memory address translation for this + * subdevice instance's notification(s). The beginning of the + * translation points to an array of notification data structures. + * The size of the translation must be at least large enough to hold the + * maximum number of notification data structures. + * Legal argument values must be instances of the following classes: + * NV01_NULL + * NV04_MEMORY + * When hMemory specifies the NV01_NULL_OBJECT value then any existing + * memory translation connection is cleared. There must not be any + * pending notifications when this command is issued. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV5070_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES (0x50700903) /* finn: Evaluated from "(FINN_NV50_DISPLAY_EVENT_INTERFACE_ID << 8) | NV5070_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV5070_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS { + NvU32 subDeviceInstance; + NvHandle hMemory; +} NV5070_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS; + +#define NV5070_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED 0 +#define NV5070_EVENT_MEMORY_NOTIFIES_STATUS_PENDING 1 +#define NV5070_EVENT_MEMORY_NOTIFIES_STATUS_ERROR 2 + + + +/* _ctrl5070event_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070impoverrides.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070impoverrides.h new file mode 100644 index 0000000..11b79b2 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070impoverrides.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070impoverrides.finn +// + + + + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h new file mode 100644 index 0000000..0052168 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h @@ -0,0 +1,936 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070or.finn +// + +#include "ctrl5070common.h" +#include "ctrl/ctrl5070/ctrl5070base.h" + + + +/* + * NV5070_CTRL_CMD_SET_DAC_PWR + * + * This command sets the DAC power control register. orNumber, normalPower, + * and safePower will always have to be specified. However, HSync, VSync, + * and data for normal and/or safe mode can be empty, leaving the current + * values intact. + * + * orNumber + * The dac for which the settings need to be programmed. + * + * normalHSync + * The normal operating state for the H sync signal. + * + * normalVSync + * The normal operating state for the V sync signal. + * + * normalData + * The normal video data input pin of the d/a converter. + * + * normalPower + * The normal state of the dac macro power. + * + * safeHSync + * The safe operating state for the H sync signal. + * + * safeVSync + * The safe operating state for the V sync signal. + * + * safeData + * The safe video data input pin of the d/a converter. + * + * safePower + * The safe state of the dac macro power. + * + * flags + * The following flags have been defined: + * (1) SPECIFIED_NORMAL: Indicates whether HSync, VSync, data, + * for normal state have been specified in the parameters. + * (2) SPECIFIED_SAFE: Indicates whether HSync, VSync, data, + * for safe state have been specified in the parameters. + * (3) SPECIFIED_FORCE_SWITCH: Indicates whether to force the + * change immediately instead of waiting for VSync + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + * NV_ERR_TIMEOUT + */ +#define NV5070_CTRL_CMD_SET_DAC_PWR (0x50700404) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_DAC_PWR_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_HSYNC 1:0 +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_HSYNC_ENABLE (0x00000000) +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_HSYNC_LO (0x00000001) +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_HSYNC_HI (0x00000002) + +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_VSYNC 1:0 +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_VSYNC_ENABLE (0x00000000) +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_VSYNC_LO (0x00000001) +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_VSYNC_HI (0x00000002) + +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_DATA 1:0 +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_DATA_ENABLE (0x00000000) +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_DATA_LO (0x00000001) +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_DATA_HI (0x00000002) + +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_PWR 0:0 +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_PWR_OFF (0x00000000) +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_PWR_ON (0x00000001) + +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_HSYNC 1:0 +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_HSYNC_ENABLE (0x00000000) +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_HSYNC_LO (0x00000001) +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_HSYNC_HI (0x00000002) + +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_VSYNC 1:0 +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_VSYNC_ENABLE (0x00000000) +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_VSYNC_LO (0x00000001) +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_VSYNC_HI (0x00000002) + +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_DATA 1:0 +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_DATA_ENABLE (0x00000000) +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_DATA_LO (0x00000001) +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_DATA_HI (0x00000002) + +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_PWR 0:0 +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_PWR_OFF (0x00000000) +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_PWR_ON (0x00000001) + +#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_SPECIFIED_NORMAL 0:0 +#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_SPECIFIED_NORMAL_NO (0x00000000) +#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_SPECIFIED_NORMAL_YES (0x00000001) +#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_SPECIFIED_SAFE 1:1 +#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_SPECIFIED_SAFE_NO (0x00000000) +#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_SPECIFIED_SAFE_YES (0x00000001) +#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_FORCE_SWITCH 2:2 +#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_FORCE_SWITCH_NO (0x00000000) +#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_FORCE_SWITCH_YES (0x00000001) +#define NV5070_CTRL_CMD_SET_DAC_PWR_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV5070_CTRL_CMD_SET_DAC_PWR_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 orNumber; + + NvU32 normalHSync; + NvU32 normalVSync; + NvU32 normalData; + NvU32 normalPower; + NvU32 safeHSync; + NvU32 safeVSync; + NvU32 safeData; + NvU32 safePower; + NvU32 flags; +} NV5070_CTRL_CMD_SET_DAC_PWR_PARAMS; + + + +/* + * NV5070_CTRL_CMD_GET_SOR_PWM + * + * This command returns SOR's current PWM settings. + * + * orNumber + * The OR number for which the seq ctrls are to be modified. + * + * targetFreq + * The target PWM freq. This is the PWM frequency we planned on + * programming. + * + * actualFreq + * Actual PWM freq programmed into PWM. + * + * div + * The divider being used currently for generating PWM clk. + * A valued of 0 means that PWM is disabled. + * + * resolution + * The resolution of steps currently programmed or the max number of + * clocks per cycle. The possible values for NV50 are 128, 256, 512 + * and 1024. This field is irrelevant when div is 0. + * + * dutyCycle + * Duty cycle in range 0-1024 + * + * sourcePCLK (OUT) + * The PWM source clock selector. This field is non-zero if the PCLK + * is selected as the PWM source clock. Otherwise, the PWM source + * clock is XTAL. + * + * head (IN) + * The head for which the pixel clock is sourced from. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_GET_SOR_PWM (0x50700420) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_SOR_PWM_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_SOR_PWM_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV5070_CTRL_CMD_GET_SOR_PWM_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 orNumber; + NvU32 targetFreq; + NvU32 actualFreq; + NvU32 div; + NvU32 resolution; + NvU32 dutyCycle; + NvU32 sourcePCLK; + NvU32 head; +} NV5070_CTRL_CMD_GET_SOR_PWM_PARAMS; + + +/* + * NV5070_CTRL_CMD_SET_SOR_PWM + * + * This command returns SOR's current PWM settings. + * + * orNumber + * The OR number for which the seq ctrls are to be modified. + * + * targetFreq + * The target PWM freq to be programmed. + * + * actualFreq + * Actual PWM freq programmed into PWM after all the specified + * settings have been applied. + * + * div + * The divider to use for generating PWM clk. + * Set this to 0 to disable PWM. Note that only one of div + * or targetFreq can be specified at a time since specifying one + * automatically determines the value of the other. Selection is + * done via USE_SPECIFIED_DIV flag. + * + * resolution + * The resolution or the max number of clocks per cycle desired. + * Note that if it's not possible to program the given resolution + * and frequency (or div) combination, RM would not attempt to + * smartly lower the resolution. The call would return failure. + * The possible values for NV50 are 128, 256, 512 and 1024. This + * field is irrelevant when div is 0. + * + * dutyCycle + * Duty cycle in range 0-1024 + * + * flags + * The following flags have been defined: + * (1) USE_SPECIFIED_DIV: Indicates whether RM should use + * specified div or targetFreq when determining the divider + * for xtal clock. + * (2) PROG_DUTY_CYCLE: Indicates whether or not the caller + * desires to program duty cycle. Normally whenever pwm freq + * and range need to be programmed, it's expected that duty + * cycle would be reprogrammed as well but this is not + * enforced. + * (3) PROG_FREQ_AND_RANGE: Indicates whether or not the caller + * desires to program a new PWM setting (div and resolution). + * (4) SOURCE_CLOCK: Indicates whether the PCLK or XTAL is used + * as the PWM clock source. GT21x and better. + * + * head (IN) + * The head for which the pixel clock is sourced from. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_SET_SOR_PWM (0x50700421) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_SOR_PWM_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_USE_SPECIFIED_DIV 0:0 +#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_USE_SPECIFIED_DIV_NO (0x00000000) +#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_USE_SPECIFIED_DIV_YES (0x00000001) +#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_PROG_DUTY_CYCLE 1:1 +#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_PROG_DUTY_CYCLE_NO (0x00000000) +#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_PROG_DUTY_CYCLE_YES (0x00000001) +#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_PROG_FREQ_AND_RANGE 2:2 +#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_PROG_FREQ_AND_RANGE_NO (0x00000000) +#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_PROG_FREQ_AND_RANGE_YES (0x00000001) +#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_SOURCE_CLOCK 3:3 +#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_SOURCE_CLOCK_XTAL (0x00000000) +#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_SOURCE_CLOCK_PCLK (0x00000001) + +#define NV5070_CTRL_CMD_SET_SOR_PWM_PARAMS_MESSAGE_ID (0x21U) + +typedef struct NV5070_CTRL_CMD_SET_SOR_PWM_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 orNumber; + NvU32 targetFreq; + NvU32 actualFreq; + NvU32 div; // equivalent of NV_PDISP_SOR_PWM_DIV_DIVIDE + NvU32 resolution; // equivalent of NV_PDISP_SOR_PWM_DIV_RANGE + NvU32 dutyCycle; + NvU32 flags; + NvU32 head; +} NV5070_CTRL_CMD_SET_SOR_PWM_PARAMS; + + +/* + * NV5070_CTRL_CMD_GET_SOR_OP_MODE + * + * This command returns current settings for the specified SOR. + * + * orNumber + * The OR number for which the operating mode needs to be read. + * + * category + * Whether LVDS or CSTM setting are desired. + * + * puTxda + * Status of data pins of link A + * + * puTxdb + * Status of data pins of link B + * + * puTxca + * Status of link A clock + * + * puTxcb + * Status of link B clock + * + * upper + * Whether LVDS bank A is the upper, odd, or first pixel. + * + * mode + * Current protocol. + * + * linkActA + * Status of link B clock + * + * linkActB + * Status of link B clock + * + * lvdsEn + * Output driver configuration. + * + * lvdsDual + * Whether LVDS dual-link mode is turned on or not. + * + * dupSync + * Whether DE, HSYNC, and VSYNC are used for encoding instead of + * RES, CNTLE, and CNTLF. + * + * newMode + * Whether new or old mode is being used. + * + * balanced + * Whether balanced encoding is enabled. + * + * plldiv + * Feedback divider for the hi-speed pll + * + * rotClk + * Skew of TXC clock. + * + * rotDat + * How much are the 8 bits of each color channel rotated by + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE (0x50700422) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_SOR_OP_MODE_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_CATEGORY 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_CATEGORY_LVDS 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_CATEGORY_CUSTOM 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_0 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_0_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_0_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_1 1:1 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_1_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_1_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_2 2:2 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_2_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_2_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_3 3:3 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_3_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_3_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_0 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_0_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_0_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_1 1:1 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_1_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_1_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_2 2:2 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_2_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_2_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_3 3:3 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_3_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_3_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXCA 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXCA_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXCA_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXCB 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXCB_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXCB_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_UPPER 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_UPPER_UPPER_RESET 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_MODE 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_MODE_LVDS 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_MODE_TMDS 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LINKACTA 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LINKACTA_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LINKACTA_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LINKACTB 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LINKACTB_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LINKACTB_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LVDS_EN 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LVDS_EN_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LVDS_EN_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LVDS_DUAL 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LVDS_DUAL_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LVDS_DUAL_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_DUP_SYNC 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_DUP_SYNC_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_DUP_SYNC_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_NEW_MODE 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_NEW_MODE_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_NEW_MODE_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_BALANCED 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_BALANCED_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_BALANCED_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PLLDIV 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PLLDIV_BY_7 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PLLDIV_BY_10 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_ROTCLK 3:0 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_ROTDAT 2:0 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NV5070_CTRL_CMD_GET_SOR_OP_MODE_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 orNumber; + + NvU32 category; + NvU32 puTxda; + NvU32 puTxdb; + NvU32 puTxca; + NvU32 puTxcb; + NvU32 upper; + NvU32 mode; + NvU32 linkActA; + NvU32 linkActB; + NvU32 lvdsEn; + NvU32 lvdsDual; + NvU32 dupSync; + NvU32 newMode; + NvU32 balanced; + NvU32 plldiv; + NvU32 rotClk; + NvU32 rotDat; +} NV5070_CTRL_CMD_GET_SOR_OP_MODE_PARAMS; + + +/* + * NV5070_CTRL_CMD_SET_SOR_OP_MODE + * + * This command applies the specified settings to the specified SOR. + * + * orNumber + * The OR number for which the operating mode needs to be read. + * Note that if DCB doesn't report LVDS for the specified orNumber, + * the call will return failure. + * + * category + * Whether LVDS or CSTM settings are specified. + * + * puTxda + * Used to enable or disable the data pins of link A. + * + * puTxdb + * Used to enable or disable the data pins of link B. + * + * puTxca + * Used to enable or disable link A clock. + * + * puTxcb + * Used to enable or disable link B clock. + * + * upper + * Whether LVDS bank A should be the upper, odd, or first pixel. + * + * mode + * What protocol (LVDS/TMDS to use). + * + * linkActA + * Used to enable or disable the digital logic of link A. + * + * linkActB + * Used to enable or disable the digital logic of link B. + * + * lvdsEn + * Output driver configuration. + * + * lvdsDual + * Whether to turn on LVDS dual-link mode. + * + * dupSync + * Whether to use DE, HSYNC, and VSYNC for encoding instead of + * RES, CNTLE, and CNTLF. + * + * newMode + * Whether to use new or old mode. + * + * balanced + * Whether or not to use balanced encoding. + * + * plldiv + * Feedback divider to use for the hi-speed pll. + * + * rotClk + * How much to skew TXC clock. + * + * rotDat + * How much to rotate the 8 bits of each color channel by. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE (0x50700423) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_SOR_OP_MODE_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_CATEGORY 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_CATEGORY_LVDS 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_CATEGORY_CUSTOM 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_0 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_0_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_0_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_1 1:1 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_1_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_1_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_2 2:2 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_2_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_2_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_3 3:3 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_3_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_3_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_0 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_0_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_0_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_1 1:1 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_1_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_1_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_2 2:2 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_2_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_2_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_3 3:3 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_3_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_3_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXCA 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXCA_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXCA_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXCB 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXCB_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXCB_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_UPPER 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_UPPER_UPPER_RESET 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_MODE 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_MODE_LVDS 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_MODE_TMDS 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LINKACTA 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LINKACTA_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LINKACTA_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LINKACTB 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LINKACTB_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LINKACTB_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LVDS_EN 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LVDS_EN_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LVDS_EN_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LVDS_DUAL 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LVDS_DUAL_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LVDS_DUAL_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_DUP_SYNC 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_DUP_SYNC_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_DUP_SYNC_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_NEW_MODE 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_NEW_MODE_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_NEW_MODE_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_BALANCED 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_BALANCED_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_BALANCED_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PLLDIV 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PLLDIV_BY_7 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PLLDIV_BY_10 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_ROTCLK 3:0 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_ROTDAT 2:0 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PARAMS_MESSAGE_ID (0x23U) + +typedef struct NV5070_CTRL_CMD_SET_SOR_OP_MODE_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 orNumber; + + NvU32 category; + NvU32 puTxda; + NvU32 puTxdb; + NvU32 puTxca; + NvU32 puTxcb; + NvU32 upper; + NvU32 mode; + NvU32 linkActA; + NvU32 linkActB; + NvU32 lvdsEn; + NvU32 lvdsDual; + NvU32 dupSync; + NvU32 newMode; + NvU32 balanced; + NvU32 plldiv; + NvU32 rotClk; + NvU32 rotDat; +} NV5070_CTRL_CMD_SET_SOR_OP_MODE_PARAMS; + +/* + * NV5070_CTRL_CMD_GET_PIOR_OP_MODE + * + * This command returns current settings for the specified PIOR. + * + * orNumber + * The OR number for which the operating mode needs to be programmed. + * + * category + * Whether ext TMDS, TV, DRO or DRI settings are desired. + * EXT TV is not supported at the moment. + * EXT DisplayPort is specified through EXT 10BPC 444. + * + * clkPolarity + * Whether or not output clock is inverted relative to generated clock. + * + * clkMode + * Whether data being transmitted is SDR or DDR. + * + * clkPhs + * Position of the edge on which data is launched. + * + * unusedPins + * Status of unused pins of this PIOR. + * + * polarity + * Whether or not sync and DE pin polarities are inverted. + * + * dataMuxing + * How are the bits are multiplexed together. + * + * clkDelay + * Extra delay for the clock. + * + * dataDelay + * Extra delay for the data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE (0x50700430) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_PIOR_OP_MODE_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CATEGORY 2:0 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CATEGORY_EXT_TMDS 0x00000000 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CATEGORY_EXT_TV 0x00000001 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CATEGORY_DRO 0x00000003 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CATEGORY_DRI 0x00000004 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CATEGORY_EXT_10BPC_444 0x00000005 + +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_POLARITY 0:0 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_POLARITY_NORMAL 0x00000000 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_POLARITY_INV 0x00000001 + +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_MODE 0:0 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_MODE_SDR 0x00000000 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_MODE_DDR 0x00000001 + +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_PHS 1:0 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_PHS_0 0x00000000 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_PHS_1 0x00000001 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_PHS_2 0x00000002 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_PHS_3 0x00000003 + +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_UNUSED_PINS 0:0 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_UNUSED_PINS_LO 0x00000000 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_UNUSED_PINS_TS 0x00000001 + +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_H 0:0 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_H_NORMAL 0x00000000 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_H_INV 0x00000001 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_V 1:1 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_V_NORMAL 0x00000000 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_V_INV 0x00000001 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_DE 2:2 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_DE_NORMAL 0x00000000 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_DE_INV 0x00000001 + +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_MUXING 3:0 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_MUXING_RGB_0 0x00000000 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_MUXING_RGB_1 0x00000001 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_MUXING_DIST_RNDR 0x00000003 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_MUXING_YUV_0 0x00000004 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_MUXING_UYVY 0x00000005 + +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_DLY 2:0 + +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_DLY 2:0 + +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_PARAMS_MESSAGE_ID (0x30U) + +typedef struct NV5070_CTRL_CMD_GET_PIOR_OP_MODE_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 orNumber; + + NvU32 category; + NvU32 clkPolarity; + NvU32 clkMode; + NvU32 clkPhs; + NvU32 unusedPins; + NvU32 polarity; + NvU32 dataMuxing; + NvU32 clkDelay; + NvU32 dataDelay; +} NV5070_CTRL_CMD_GET_PIOR_OP_MODE_PARAMS; + + +/* + * NV5070_CTRL_CMD_SET_PIOR_OP_MODE + * + * This command applies the specified settings to the specified PIOR. + * + * orNumber + * The OR number for which the operating mode needs to be programmed. + * + * category + * Whether ext TMDS, TV, DRO or DRI settings are to be programmed. + * EXT TV is not supported at the moment. + * EXT DisplayPort is specified through EXT 10BPC 444. + * + * clkPolarity + * Whether or not to invert output clock relative to generated clock. + * + * clkMode + * Whether data being transmitted should be SDR or DDR. + * + * clkPhs + * Position of the edge on which data should be launched. + * + * unusedPins + * What to do with unused pins of this PIOR. + * + * polarity + * Whether or not to invert sync and DE pin polarities. + * + * dataMuxing + * How to multiplex the bits together. + * + * clkDelay + * Extra delay for the clock. + * + * dataDelay + * Extra delay for the data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE (0x50700431) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_PIOR_OP_MODE_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CATEGORY 2:0 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CATEGORY_EXT_TMDS 0x00000000 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CATEGORY_EXT_TV 0x00000001 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CATEGORY_DRO 0x00000003 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CATEGORY_DRI 0x00000004 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CATEGORY_EXT_10BPC_444 0x00000005 + +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_POLARITY 0:0 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_POLARITY_NORMAL 0x00000000 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_POLARITY_INV 0x00000001 + +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_MODE 0:0 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_MODE_SDR 0x00000000 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_MODE_DDR 0x00000001 + +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_PHS 1:0 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_PHS_0 0x00000000 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_PHS_1 0x00000001 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_PHS_2 0x00000002 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_PHS_3 0x00000003 + +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_UNUSED_PINS 0:0 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_UNUSED_PINS_LO 0x00000000 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_UNUSED_PINS_TS 0x00000001 + +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_H 0:0 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_H_NORMAL 0x00000000 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_H_INV 0x00000001 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_V 1:1 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_V_NORMAL 0x00000000 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_V_INV 0x00000001 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_DE 2:2 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_DE_NORMAL 0x00000000 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_DE_INV 0x00000001 + +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_MUXING 3:0 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_MUXING_RGB_0 0x00000000 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_MUXING_RGB_1 0x00000001 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_MUXING_DIST_RNDR 0x00000003 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_MUXING_YUV_0 0x00000004 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_MUXING_UYVY 0x00000005 + +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_DLY 2:0 + +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_DLY 2:0 + +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DRO_MASTER 1:0 + +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DRO_DRIVE_PIN_SET 2:0 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DRO_DRIVE_PIN_SET_NEITHER 0 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DRO_DRIVE_PIN_SET_A 1 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DRO_DRIVE_PIN_SET_B 2 + + +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_PARAMS_MESSAGE_ID (0x31U) + +typedef struct NV5070_CTRL_CMD_SET_PIOR_OP_MODE_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 orNumber; + + NvU32 category; + NvU32 clkPolarity; + NvU32 clkMode; + NvU32 clkPhs; + NvU32 unusedPins; + NvU32 polarity; + NvU32 dataMuxing; + NvU32 clkDelay; + NvU32 dataDelay; + NvU32 dro_master; + NvU32 dro_drive_pin_set; +} NV5070_CTRL_CMD_SET_PIOR_OP_MODE_PARAMS; + +/* + * NV5070_CTRL_CMD_SET_SOR_FLUSH_MODE + * + * Set the given SOR number into flush mode in preparation for DP link training. + * + * orNumber [in] + * The SOR number to set into flush mode. + * + * bEnable [in] + * Whether to enable or disable flush mode on this SOR. + * + * bImmediate [in] + * If set to true, will enable flush in immediate mode. + * If not, will enable flush in loadv mode. + * NOTE: We do not support exit flush in LoadV mode. + * + * headMask [in] + * Optional. If set brings only the heads in the head mask out of flush + * OR will stay in flush mode until last head is out of flush mode. + * Caller can use _HEAD__ALL to specify all the heads are to be brought out. + * NOTE: headMask would be considered only while exiting from flush mode. + * + * bForceRgDiv [in] + * If set forces RgDiv. Should be used only for HW/SW testing + * + * bUseBFM [in] + * If Set then it mean we are using BFM else executing on non-BFM paltforms. + * + * bFireAndForget [in] + * Fire the flush mode & perform post-processing without waiting for it + * to be done. This is required for special cases like GC5 where we have + * ELV blocked, RG stall & we trigger flush for one shot mode & then do + * a modeset by disabling it without actually waiting for it to get + * disabled. We will not get any vblank interrupt in this case as we have + * stalled RG. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV5070_CTRL_CMD_SET_SOR_FLUSH_MODE (0x50700457) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS_MESSAGE_ID (0x57U) + +typedef struct NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 sorNumber; + NvBool bEnable; + NvBool bImmediate; + NvU32 headMask; + NvBool bForceRgDiv; + NvBool bUseBFM; + NvBool bFireAndForget; +} NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS; + +#define NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS_HEADMASK_HEAD(i) (i):(i) +#define NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS_HEADMASK_HEAD__SIZE_1 NV5070_CTRL_CMD_MAX_HEADS +#define NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS_HEADMASK_HEAD_ALL 0xFFFFFFFF + + + +/* _ctrl5070or_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h new file mode 100644 index 0000000..64269d8 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h @@ -0,0 +1,578 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070rg.finn +// + +#include "ctrl/ctrl5070/ctrl5070base.h" + + + +/* + * NV5070_CTRL_CMD_GET_RG_STATUS + * + * This 'get' command returns the status of raster generator + * + * head + * The head for which RG status is desired. + * + * scanLocked + * Whether or not RG is scan (raster or frame) locked. + * flipLocked + * Whether or not RG is flip locked. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_GET_RG_STATUS (0x50700202) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_RG_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_RG_STATUS_SCANLOCKED_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_STATUS_SCANLOCKED_YES (0x00000001) + +#define NV5070_CTRL_CMD_GET_RG_STATUS_FLIPLOCKED_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_STATUS_FLIPLOCKED_YES (0x00000001) + +#define NV5070_CTRL_CMD_GET_RG_STATUS_STALLED_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_STATUS_STALLED_YES (0x00000001) + +#define NV5070_CTRL_CMD_GET_RG_STATUS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV5070_CTRL_CMD_GET_RG_STATUS_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 head; + + NvU32 scanLocked; // [OUT] + NvU32 flipLocked; // [OUT] + NvU32 rgStalled; +} NV5070_CTRL_CMD_GET_RG_STATUS_PARAMS; + +/* + * NV5070_CTRL_CMD_UNDERFLOW_PARAMS + * + * This structure contains data for + * NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP and + * NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP CTRL calls + * + * head + * The head for which RG underflow properties needed to be set/get. + * Valid values for this parameter are 0 to NV5070_CTRL_CMD_MAX_HEADS. + * enable + * _SET_RG_: Whether to enable or disable RG underflow reporting. + * _GET_RG_: Whether or not RG underflow reporting is enabled. + * underflow + * _SET_RG_: Clear underflow (CLEAR_UNDERFLOW_YES) or leave it alone + * (CLEAR_UNDERFLOW_NO). + * Note: The GET_RG function automatically clears the underflow. + * It is recommended that GET_RG be used to clear any initial + * underflows, and that the "underflow" field be set to + * CLEAR_UNDERFLOW_NO in any SET_RG calls. This field may be + * deprecated in the future, for SET_RG calls. + * _GET_RG_: UNDERFLOWED_YES if an RG underflow occurred since the most + * recent prior call to to NV5070_CTRL_CMD_GET_RG_STATUS. + * epfifoUnderflow + * _SET_RG_: Not used. + * _GET_RG_: EPFIFO_UNDERFLOWED_YES if an EPFIFO underflow occurred since + * the most recent prior call to NV5070_CTRL_CMD_GET_RG_STATUS. + * mode + * _SET_RG_: What mode to use when underflow occurs. This is + * independent from enable field. This is always active. + * _GET_RG_: What mode is used when underflow occurs. This is + * independent from enable field. This is always active. + */ +typedef struct NV5070_CTRL_CMD_UNDERFLOW_PARAMS { + NvU32 head; + NvU32 enable; + NvU32 underflow; + NvU32 epfifoUnderflow; + NvU32 mode; +} NV5070_CTRL_CMD_UNDERFLOW_PARAMS; + +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_ENABLED_NO (0x00000000) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_ENABLED_YES (0x00000001) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_UNDERFLOWED_NO (0x00000000) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_UNDERFLOWED_YES (0x00000001) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_EPFIFO_UNDERFLOWED_NO (0x00000000) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_EPFIFO_UNDERFLOWED_YES (0x00000001) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_MODE_REPEAT (0x00000000) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_MODE_RED (0x00000001) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_ENABLE_NO (0x00000000) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_ENABLE_YES (0x00000001) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_CLEAR_UNDERFLOW_NO (0x00000000) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_CLEAR_UNDERFLOW_YES (0x00000001) + +/* + * NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP + * + * This command returns the underflow reporting parameters inside + * NV5070_CTRL_CMD_UNDERFLOW_PARAMS structure + * + * underflowParams + * Contains data for underflow logging. + * Check NV5070_CTRL_CMD_UNDERFLOW_PARAMS structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP (0x50700203) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NV5070_CTRL_CMD_UNDERFLOW_PARAMS underflowParams; +} NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP_PARAMS; + + +/* + * NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP + * + * This command sets up the underflow parameters using + * NV5070_CTRL_CMD_UNDERFLOW_PARAMS structure + * + * underflowParams + * Contains data for underflow logging. + * Check NV5070_CTRL_CMD_UNDERFLOW_PARAMS structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP (0x50700204) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NV5070_CTRL_CMD_UNDERFLOW_PARAMS underflowParams; +} NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP_PARAMS; + + +/* + * NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP + * + * This command gets the timing parameters associated with the lockout period. + * + * head + * The head for which RG fliplock properties are desired. + * + * maxSwapLockoutSkew + * The maximum possible skew between the swap lockout signals for all + * heads which are fliplocked to this head. + * + * swapLockoutStart + * Determines the start of the start lockout period, expressed as the + * number of lines before the end of the frame. The minimum allowed + * value is 1. + + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP (0x50700205) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_MAX_SWAP_LOCKOUT_SKEW 9:0 + +#define NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_SWAP_LOCKOUT_START 15:0 + +#define NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 head; + + NvU32 maxSwapLockoutSkew; + NvU32 swapLockoutStart; +} NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_PARAMS; + +/* + * NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP + * + * This command sets the timing parameters associated with the lockout period. + * + * head + * The head for which RG fliplock properties are desired. + * + * maxSwapLockoutSkew + * The maximum possible skew between the swap lockout signals for all + * heads which are fliplocked to this head. + * + * swapLockoutStart + * Determines the start of the start lockout period, expressed as the + * number of lines before the end of the frame. The minimum allowed + * value is 1. + + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP (0x50700206) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_MAX_SWAP_LOCKOUT_SKEW 9:0 +#define NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_MAX_SWAP_LOCKOUT_SKEW_INIT (0x00000000) + +#define NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_SWAP_LOCKOUT_START 15:0 +#define NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_SWAP_LOCKOUT_START_INIT (0x00000000) + +#define NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 head; + + NvU32 maxSwapLockoutSkew; + NvU32 swapLockoutStart; +} NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS; + +/* + * NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN + * + * This command returns which lockpin has been connected for the specified + * subdevice in the current SLI and/or framelock configuration. + * + * head + * The head for which the locking is associated with + * + * masterScanLock + * Indicate the connection status and pin number of master scanlock + * + * slaveScanLock + * Indicate the connection status and pin number of slave scanlock + * + * flipLock + * Indicate the connection status and pin number of fliplock + * + * stereoLock + * Indicate the connection status and pin number of stereo lock + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN (0x50700207) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_MASTER_SCAN_LOCK_CONNECTED 0:0 +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_MASTER_SCAN_LOCK_CONNECTED_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_MASTER_SCAN_LOCK_CONNECTED_YES (0x00000001) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_MASTER_SCAN_LOCK_PIN 3:1 + +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_SLAVE_SCAN_LOCK_CONNECTED 0:0 +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_SLAVE_SCAN_LOCK_CONNECTED_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_SLAVE_SCAN_LOCK_CONNECTED_YES (0x00000001) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_SLAVE_SCAN_LOCK_PIN 3:1 + +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_FLIP_LOCK_CONNECTED 0:0 +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_FLIP_LOCK_CONNECTED_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_FLIP_LOCK_CONNECTED_YES (0x00000001) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_FLIP_LOCK_PIN 3:1 + +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STEREO_LOCK_CONNECTED 0:0 +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STEREO_LOCK_CONNECTED_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STEREO_LOCK_CONNECTED_YES (0x00000001) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STEREO_LOCK_PIN 3:1 + +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 head; + + NvU32 masterScanLock; + NvU32 slaveScanLock; + NvU32 flipLock; + NvU32 stereoLock; +} NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS; + +/* + * NV5070_CTRL_CMD_SET_VIDEO_STATUS + * + * This command is used to set the current video playback status for use + * by the Display Power Saving (nvDPS) feature. The playback status is + * used to maximize power savings by altering the DFP refresh rate used for + * video playback. + * + * displayId + * This parameter specifies the ID of the video playback display. + * Only one display may be indicated in this parameter. + * clientId + * This parameter specifies the opaque client ID associated with + * the video playback application. + * mode + * This parameter specifies the video playback mode. Valid values + * for this parameter include: + * NV5070_CTRL_DFP_SET_VIDEO_STATUS_MODE_NON_FULLSCREEN + * This value indicates that there is either no video playback or + * that video playback is windowed. + * NV5070_CTRL_DFP_SET_VIDEO_STATUS_MODE_FULLSCREEN + * This value indicates that video playback is fullscreen. + * NV5070_CTRL_DFP_SET_VIDEO_STATUS_MODE_D3D + * This value indicates that there is a D3D app started. + * frameRate + * The parameter indicates the current video playback frame rate. + * The value is a 32 bit unsigned fixed point number, 24 bit unsigned + * integer (bits 31:7), and 8 fraction bits (bits 7:0), measured in + * number of frames per second. + * A value of 0 indicates that video playback is stopped or not playing. + * frameRateAlarmUpperLimit + * The parameter indicates the upper limit which will can be tolerated in + * notifying frame rate change. If the frame rate changed but is still + * below the limit. The newer frame rate doesn't have to be set till it's + * over the limit. + * The value is a 32 bit unsigned fixed point number, 24 bit unsigned + * integer (bits 31:7), and 8 fraction bits (bits 7:0), measured in + * number of frames per second. + * A value of 0 indicates no tolerance of frame rate notifying. Instant + * frame rate has to be set when it has changed. + * frameRateAlarmLowerLimit + * The parameter indicates the lower limit which will can be tolerated in + * notifying frame rate change. If the frame rate changed but is still + * above the limit. The newer frame rate doesn't have to be set till it's + * below the limit. + * The value is a 32 bit unsigned fixed point number, 24 bit unsigned + * integer (bits 31:7), and 8 fraction bits (bits 7:0), measured in + * number of frames per second. + * A value of 0 indicates no tolerance of frame rate notifying. Instant + * frame rate has to be set when it has changed. + * + * The frameRateAlarm limit values can be used by the video client to + * indicate the the range in which frame rate changes do not require + * notification (i.e. frame rates outside these limits will result in + * notification). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV5070_CTRL_CMD_SET_VIDEO_STATUS (0x50700209) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_DFP_SET_VIDEO_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_DFP_SET_VIDEO_STATUS_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV5070_CTRL_DFP_SET_VIDEO_STATUS_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + + NvU32 displayId; + NvU32 clientId; + NvU32 mode; + NvU32 frameRate; + NvU32 frameRateAlarmUpperLimit; + NvU32 frameRateAlarmLowerLimit; +} NV5070_CTRL_DFP_SET_VIDEO_STATUS_PARAMS; + +/* valid mode flags */ +#define NV5070_CTRL_DFP_SET_VIDEO_STATUS_MODE_NON_FULLSCREEN (0x00000000) +#define NV5070_CTRL_DFP_SET_VIDEO_STATUS_MODE_FULLSCREEEN (0x00000001) +#define NV5070_CTRL_DFP_SET_VIDEO_STATUS_MODE_D3D (0x00000002) + +/* + * NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS + * + * This command returns which set of lockpins needs to be used in order to + * successfully raster lock two heads on different GPUs together. The + * second GPU is not inferred from linked SLI state, if any, and needs to + * be specified explicitly. + * + * head + * The local head to be locked with the peer head. + * + * peer.hDisplay + * The handle identifying a display object allocated on another + * GPU. It specifies the peer of interest with a subdevice + * index (see below) and needs to be be distinct from the handle + * supplied directly to NvRmControl(). + * + * peer.subdeviceIndex + * The index of the peer subdevice of interest. + * + * peer.head + * The peer head to be locked with the local head. + * + * masterScanLockPin + * slaveScanLockPin + * Returns the master and slave scanlock pins that would need to + * be used to lock the specified heads together, if any. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_OBJECT_PARENT + */ +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS (0x5070020a) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_MASTER_SCAN_LOCK_CONNECTED 0:0 +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_MASTER_SCAN_LOCK_CONNECTED_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_MASTER_SCAN_LOCK_CONNECTED_YES (0x00000001) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_MASTER_SCAN_LOCK_PIN 2:1 + +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_SLAVE_SCAN_LOCK_CONNECTED 0:0 +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_SLAVE_SCAN_LOCK_CONNECTED_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_SLAVE_SCAN_LOCK_CONNECTED_YES (0x00000001) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_SLAVE_SCAN_LOCK_PIN 2:1 + +#define NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 head; + + struct { + NvHandle hDisplay; + NvU32 subdeviceIndex; + NvU32 head; + } peer; + + NvU32 masterScanLock; + NvU32 slaveScanLock; +} NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS; + +/* + * NV5070_CTRL_CMD_GET_PINSET_LOCKPINS + * + * Get the lockpins for the specified pinset. + * + * pinset [in] + * The pinset whose corresponding lockpin numbers need to be determined + * must be specified with this parameter. + * + * scanLockPin [out] + * The scanlock lockpin (rasterlock or framelock) index, which can be + * either master or slave, is returned in this parameter. + * + * flipLockPin [out] + * The fliplock lockpin index, is returned in this parameter. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV5070_CTRL_CMD_GET_PINSET_LOCKPINS (0x5070020b) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_GET_PINSET_LOCKPINS_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_GET_PINSET_LOCKPINS_SCAN_LOCK_PIN_NONE 0xffffffff + +#define NV5070_CTRL_GET_PINSET_LOCKPINS_FLIP_LOCK_PIN_NONE 0xffffffff + +#define NV5070_CTRL_GET_PINSET_LOCKPINS_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV5070_CTRL_GET_PINSET_LOCKPINS_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 pinset; + NvU32 scanLockPin; + NvU32 flipLockPin; +} NV5070_CTRL_GET_PINSET_LOCKPINS_PARAMS; + +/* + * NV5070_CTRL_CMD_GET_RG_SCAN_LINE + * + * This 'get' command returns the current scan line value from raster generator + * + * head + * The head for which current scan line number is desired. + * + * scanLine + * Current scan line number. + * + * inVblank + * Whether or not in vblank. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_GET_RG_SCAN_LINE (0x5070020c) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_RG_SCAN_LINE_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_RG_SCAN_LINE_IN_VBLANK_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_SCAN_LINE_IN_VBLANK_YES (0x00000001) + +#define NV5070_CTRL_CMD_GET_RG_SCAN_LINE_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV5070_CTRL_CMD_GET_RG_SCAN_LINE_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 head; + NvU32 scanLine; // [OUT] + NvU32 inVblank; // [OUT] +} NV5070_CTRL_CMD_GET_RG_SCAN_LINE_PARAMS; + +/* + * NV5070_CTRL_CMD_GET_FRAMELOCK_HEADER_LOCKPINS + * + * This command returns FrameLock header lock pin information. + * Lock pin index returned by this command corresponds to the + * evo lock pin number. Example - lock pin index 0 means + * LOCKPIN_0. + * + * frameLockPin [out] + * This parameter returns the FrameLock pin index + * connected to FrameLock header. + * + * rasterLockPin [out] + * This parameter returns the RasterLock pin index + * connected to FrameLock header. + * + * flipLockPin [out] + * This parameter returns the FlipLock pin index + * connected to FrameLock header. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV5070_CTRL_CMD_GET_FRAMELOCK_HEADER_LOCKPINS (0x5070020d) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_FRAME_LOCK_PIN_NONE (0xffffffff) +#define NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_RASTER_LOCK_PIN_NONE (0xffffffff) +#define NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_FLIP_LOCK_PIN_NONE (0xffffffff) +#define NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 frameLockPin; + NvU32 rasterLockPin; + NvU32 flipLockPin; +} NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_PARAMS; + + + +/* _ctrl5070rg_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070seq.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070seq.h new file mode 100644 index 0000000..0da723f --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070seq.h @@ -0,0 +1,521 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070seq.finn +// + +#include "ctrl/ctrl5070/ctrl5070base.h" + +/* + * NV5070_CTRL_CMD_GET_SOR_SEQ_CTL + * + * This command returns SOR sequencer's power up and down PCs and sequencer + * program to be used for power up and dowm. + * + * orNumber + * The OR number for which the seq ctrls are to be modified. + * + * puPcAlt + * Alternate power up PC. + * + * pdPc + * Power down PC. + * + * pdPcAlt + * Alternate power down PC. + * + * normalStart + * Whether normal mode is using normal or alt PC + * + * safeStart + * Whether safe mode is using normal or alt PC + * + * normalState + * Whether normal state is PD or PU. + * + * safeState + * Whether safe state is PD or PU. + * + * flags + * There is only one flag defined currently + * 1. GET_SEQ_PROG: Whether or not current seq program must be + * return back. Caller should set this to _YES to read the + * current seq program. + * + * seqProgram + * The sequencer program consisting of power up and down sequences. + * For NV50, this consists of 16 DWORDS. The program is + * relevant only when GET_SEQ_PROG flags is set to _YES. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL (0x50700301U) /* finn: Evaluated from "(FINN_NV50_DISPLAY_SEQ_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PU_PC_ALT_VALUE 3:0 + +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PD_PC_VALUE 3:0 + +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PD_PC_ALT_VALUE 3:0 + +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_NORMAL_START_VAL 0:0 +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_NORMAL_START_VAL_NORMAL (0x00000000U) +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_NORMAL_START_VAL_ALT (0x00000001U) + +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SAFE_START_VAL 0:0 +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SAFE_START_VAL_NORMAL (0x00000000U) +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SAFE_START_VAL_ALT (0x00000001U) + +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_NORMAL_STATE_VAL 0:0 +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_NORMAL_STATE_VAL_PD (0x00000000U) +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_NORMAL_STATE_VAL_PU (0x00000001U) + +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SAFE_STATE_VAL 0:0 +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SAFE_STATE_VAL_PD (0x00000000U) +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SAFE_STATE_VAL_PU (0x00000001U) + +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_FLAGS_GET_SEQ_PROG 0:0 +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_FLAGS_GET_SEQ_PROG_NO (0x00000000U) +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_FLAGS_GET_SEQ_PROG_YES (0x00000001U) + +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SEQ_PROG_SIZE 16U +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 orNumber; + + NvU32 puPcAlt; + NvU32 pdPc; + NvU32 pdPcAlt; + NvU32 normalStart; + NvU32 safeStart; + NvU32 normalState; + NvU32 safeState; + NvU32 flags; + NvU32 seqProgram[NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SEQ_PROG_SIZE]; +} NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PARAMS; + +/* + * NV5070_CTRL_CMD_SET_SOR_SEQ_CTL + * + * This command does the following in that order + * (a) Loads a specified sequencer program for power up and down. + * (b) Updates SOR sequencer's power up and down PCs, tells seq to SKIP + * current wait for vsync and waits until sequencer actually SKIPs or halts + * (see more below under SKIP_WAIT_FOR_VSYNC flag) and + * (c) Update power settings (safe/normal start and state). + * + * orNumber + * The OR number for which the seq ctrls are to be modified. + * + * puPcAlt + * Alternate power up PC. + * + * pdPc + * Power down PC. + * + * pdPcAlt + * Alternate power down PC. + * + * normalStart + * Whether normal mode should use normal or alt PC. + * + * safeStart + * Whether safe mode should use normal or alt PC. + * + * normalState + * Whether normal state should be PD or PU. + * + * safeState + * Whether safe state should be PD or PU. + * + * flags + * The following flags have been defined + * 1. SKIP_WAIT_FOR_VSYNC: Should seq be forced to skip waiting + * for vsync if it's currently waiting on such an instruction. + * If the current instruction doesn't have a wait for vsync, + * SKIP will be applied to the next one and so on until + * either sequencer halts or an instruction with a wait for + * vsync is found. The call will block until seq halts or + * SKIPs a wait for vsync. + * 2. SEQ_PROG_PRESENT: Whether or not a new seq program has + * been specified. + * + * seqProgram + * The sequencer program consisting of power up and down sequences. + * For NV50, this consists of 16 DWORDS. The program is + * relevant only when SEQ_PROG_PRESENT flags is set to _YES. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL (0x50700302U) /* finn: Evaluated from "(FINN_NV50_DISPLAY_SEQ_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PU_PC_ALT_VALUE 3:0 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PU_PC_ALT_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PU_PC_ALT_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PU_PC_ALT_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_VALUE 3:0 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_ALT_VALUE 3:0 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_ALT_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_ALT_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_ALT_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_START_VAL 0:0 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_START_VAL_NORMAL (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_START_VAL_ALT (0x00000001U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_START_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_START_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_START_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_START_VAL 0:0 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_START_VAL_NORMAL (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_START_VAL_ALT (0x00000001U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_START_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_START_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_START_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_STATE_VAL 0:0 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_STATE_VAL_PD (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_STATE_VAL_PU (0x00000001U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_STATE_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_STATE_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_STATE_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_STATE_VAL 0:0 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_STATE_VAL_PD (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_STATE_VAL_PU (0x00000001U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_STATE_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_STATE_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_STATE_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_FLAGS_SKIP_WAIT_FOR_VSYNC 0:0 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_FLAGS_SKIP_WAIT_FOR_VSYNC_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_FLAGS_SKIP_WAIT_FOR_VSYNC_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_FLAGS_SEQ_PROG_PRESENT 1:1 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_FLAGS_SEQ_PROG_PRESENT_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_FLAGS_SEQ_PROG_PRESENT_YES (0x00000001U) + + +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SEQ_PROG_SIZE 16U +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 orNumber; + + NvU32 puPcAlt; + NvU32 pdPc; + NvU32 pdPcAlt; + NvU32 normalStart; + NvU32 safeStart; + NvU32 normalState; + NvU32 safeState; + NvU32 flags; + NvU32 seqProgram[NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SEQ_PROG_SIZE]; +} NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PARAMS; + +/* + * NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL + * + * This command returns PIOR sequencer's power up and down PCs and sequencer + * program to be used for power up and dowm. + * + * orNumber + * The OR number for which the seq ctrls are to be modified. + * + * puPcAlt + * Alternate power up PC. + * + * pdPc + * Power down PC. + * + * pdPcAlt + * Alternate power down PC. + * + * normalStart + * Whether normal mode is using normal or alt PC + * + * safeStart + * Whether safe mode is using normal or alt PC + * + * normalState + * Whether normal state is PD or PU. + * + * safeState + * Whether safe state is PD or PU. + * + * flags + * There is only one flag defined currently + * 1. GET_SEQ_PROG: Whether or not current seq program must be + * return back. Caller should set this to _YES to read the + * current seq program. + * + * seqProgram + * The sequencer program consisting of power up and down sequences. + * For NV50, this consists of 16 DWORDS. The program is + * relevant only when GET_SEQ_PROG flags is set to _YES. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL (0x50700303U) /* finn: Evaluated from "(FINN_NV50_DISPLAY_SEQ_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PU_PC_ALT_VALUE 3:0 + +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PD_PC_VALUE 3:0 + +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PD_PC_ALT_VALUE 3:0 + +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_NORMAL_START_VAL 0:0 +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_NORMAL_START_VAL_NORMAL (0x00000000U) +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_NORMAL_START_VAL_ALT (0x00000001U) + +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SAFE_START_VAL 0:0 +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SAFE_START_VAL_NORMAL (0x00000000U) +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SAFE_START_VAL_ALT (0x00000001U) + +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_NORMAL_STATE_VAL 0:0 +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_NORMAL_STATE_VAL_PD (0x00000000U) +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_NORMAL_STATE_VAL_PU (0x00000001U) + +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SAFE_STATE_VAL 0:0 +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SAFE_STATE_VAL_PD (0x00000000U) +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SAFE_STATE_VAL_PU (0x00000001U) + +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_FLAGS_GET_SEQ_PROG 0:0 +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_FLAGS_GET_SEQ_PROG_NO (0x00000000U) +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_FLAGS_GET_SEQ_PROG_YES (0x00000001U) + +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SEQ_PROG_SIZE 8U +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 orNumber; + + NvU32 puPcAlt; + NvU32 pdPc; + NvU32 pdPcAlt; + NvU32 normalStart; + NvU32 safeStart; + NvU32 normalState; + NvU32 safeState; + NvU32 flags; + NvU32 seqProgram[NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SEQ_PROG_SIZE]; +} NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PARAMS; + +/* + * NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL + * + * This command does the following in that order + * (a) Loads a specified sequencer program for power up and down. + * (b) Updates PIOR sequencer's power up and down PCs, tells seq to SKIP + * current wait for vsync and waits until sequencer actually SKIPs or halts + * (see more below under SKIP_WAIT_FOR_VSYNC flag) and + * (c) Update power settings (safe/normal start and state). + * + * orNumber + * The OR number for which the seq ctrls are to be modified. + * + * puPcAlt + * Alternate power up PC. + * + * pdPc + * Power down PC. + * + * pdPcAlt + * Alternate power down PC. + * + * normalStart + * Whether normal mode should use normal or alt PC + * + * safeStart + * Whether safe mode should use normal or alt PC + * + * normalState + * Whether normal state should be PD or PU. + * + * safeState + * Whether safe state should be PD or PU. + * + * flags + * The following flags have been defined + * 1. SKIP_WAIT_FOR_VSYNC: Should seq be forced to skip waiting + * for vsync if it's currently waiting on such an instruction. + * If the current instruction doesn't have a wait for vsync, + * SKIP will be applied to the next one and so on until + * either sequencer halts or an instruction with a wait for + * vsync is found. The call will block until seq halts or + * SKIPs a wait for vsync. + * 2. SEQ_PROG_PRESENT: Whether or not a new seq program has + * been specified. + * + * seqProgram + * The sequencer program consisting of power up and down sequences. + * For NV50, this consists of 8 DWORDS. The program is + * relevant only when SEQ_PROG_PRESENT flags is set to _YES. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL (0x50700304U) /* finn: Evaluated from "(FINN_NV50_DISPLAY_SEQ_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PU_PC_ALT_VALUE 3:0 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PU_PC_ALT_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PU_PC_ALT_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PU_PC_ALT_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_VALUE 3:0 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_ALT_VALUE 3:0 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_ALT_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_ALT_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_ALT_SPECIFIED_YES (0x00000001U) + + +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_START_VAL 0:0 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_START_VAL_NORMAL (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_START_VAL_ALT (0x00000001U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_START_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_START_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_START_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_START_VAL 0:0 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_START_VAL_NORMAL (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_START_VAL_ALT (0x00000001U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_START_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_START_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_START_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_STATE_VAL 0:0 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_STATE_VAL_PD (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_STATE_VAL_PU (0x00000001U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_STATE_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_STATE_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_STATE_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_STATE_VAL 0:0 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_STATE_VAL_PD (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_STATE_VAL_PU (0x00000001U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_STATE_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_STATE_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_STATE_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_FLAGS_SKIP_WAIT_FOR_VSYNC 0:0 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_FLAGS_SKIP_WAIT_FOR_VSYNC_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_FLAGS_SKIP_WAIT_FOR_VSYNC_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_FLAGS_SEQ_PROG_PRESENT 1:1 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_FLAGS_SEQ_PROG_PRESENT_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_FLAGS_SEQ_PROG_PRESENT_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SEQ_PROG_SIZE 8U +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 orNumber; + + NvU32 puPcAlt; + NvU32 pdPc; + NvU32 pdPcAlt; + NvU32 normalStart; + NvU32 safeStart; + NvU32 normalState; + NvU32 safeState; + NvU32 flags; + NvU32 seqProgram[NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SEQ_PROG_SIZE]; +} NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PARAMS; + +/* + * NV5070_CTRL_CMD_CTRL_SEQ_PROG_SPEED + * + * This call allows a fast sequencer program to be selected. It's intended for + * situations where panel sequencing is not required and the usual sequencing + * delays cost too much time. + * + * displayId + * The corresponding display ID. (Note that this call is currently only + * supported for LVDS on an internal encoder, i.e. a SOR.) + * cmd + * The command to perform. Valid values are: + * NV5070_CTRL_SEQ_PROG_SPEED_CMD_GET + * Get the current state. + * NV5070_CTRL_SEQ_PROG_SPEED_CMD_SET + * Set the current state. + * state + * The state of panel sequencing for this displayId. This is an input + * when cmd = SET and an output when cmd = GET. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_NOT_SUPPORTED + * + */ + +#define NV5070_CTRL_CMD_CTRL_SEQ_PROG_SPEED (0x50700305U) /* finn: Evaluated from "(FINN_NV50_DISPLAY_SEQ_INTERFACE_ID << 8) | NV5070_CTRL_SEQ_PROG_SPEED_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_SEQ_PROG_SPEED_CMD_GET (0x00000000U) +#define NV5070_CTRL_SEQ_PROG_SPEED_CMD_SET (0x00000001U) + +#define NV5070_CTRL_SEQ_PROG_SPEED_STATE_NORMAL (0x00000000U) +#define NV5070_CTRL_SEQ_PROG_SPEED_STATE_FAST (0x00000001U) + +#define NV5070_CTRL_SEQ_PROG_SPEED_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV5070_CTRL_SEQ_PROG_SPEED_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + + NvU32 displayId; + + NvU32 cmd; + NvU32 state; +} NV5070_CTRL_SEQ_PROG_SPEED_PARAMS; + +/* _ctrl5070seq_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070system.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070system.h new file mode 100644 index 0000000..bbb07e6 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070system.h @@ -0,0 +1,81 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070system.finn +// + +#include "ctrl/ctrl5070/ctrl5070base.h" +#include "ctrl/ctrl5070/ctrl5070common.h" // NV5070_CTRL_CMD_MAX_HEADS + +/* extract cap bit setting from tbl */ +#define NV5070_CTRL_SYSTEM_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* caps format is byte_index:bit_mask */ +#define NV5070_CTRL_SYSTEM_CAPS_BUG_237734_REQUIRES_DMI_WAR 0:0x01 // Deprecated +#define NV5070_CTRL_SYSTEM_CAPS_STEREO_DIN_AVAILABLE 0:0x02 +#define NV5070_CTRL_SYSTEM_CAPS_BUG_381003_MULTIWAY_AFR_WAR 0:0x04 +#define NV5070_CTRL_SYSTEM_CAPS_BUG_538079_COLOR_COMPRESSION_SUPPORTED 0:0x08 // Deprecated +#define NV5070_CTRL_SYSTEM_CAPS_BUG_2052012_GLITCHY_MCLK_SWITCH 0:0x10 +#define NV5070_CTRL_SYSTEM_CAPS_DEEP_COLOR_SUPPORT 0:0x20 +#define NV5070_CTRL_SYSTEM_CAPS_BUG_644815_DNISO_VIDMEM_ONLY 0:0x40 + + +/* size in bytes of display caps table */ +#define NV5070_CTRL_SYSTEM_CAPS_TBL_SIZE 1 + +/* + * NV5070_CTRL_CMD_SYSTEM_GET_CAPS_V2 + * + * This command returns the set of display capabilities for the parent device + * in the form of an array of unsigned bytes. Display capabilities + * include supported features and required workarounds for the display + * engine(s) within the device, each represented by a byte offset into the + * table and a bit position within that byte. The set of display capabilities + * will be normalized across all GPUs within the device (a feature capability + * will be set only if it's supported on all GPUs while a required workaround + * capability will be set if any of the GPUs require it). + * + * [out] capsTbl + * This caps table array is where the display cap bits will be transferred + * by the RM. The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + */ +#define NV5070_CTRL_CMD_SYSTEM_GET_CAPS_V2 (0x50700709) /* finn: Evaluated from "(FINN_NV50_DISPLAY_SYSTEM_INTERFACE_ID << 8) | NV5070_CTRL_SYSTEM_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_SYSTEM_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV5070_CTRL_SYSTEM_GET_CAPS_V2_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + + NvU8 capsTbl[NV5070_CTRL_SYSTEM_CAPS_TBL_SIZE]; +} NV5070_CTRL_SYSTEM_GET_CAPS_V2_PARAMS; + +/* _ctrl5070system_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070verif.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070verif.h new file mode 100644 index 0000000..6741891 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5070/ctrl5070verif.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070verif.finn +// + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5080.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5080.h new file mode 100644 index 0000000..777bdab --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl5080.h @@ -0,0 +1,212 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5080.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl0080/ctrl0080dma.h" /* NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS */ +#include "ctrl/ctrl2080/ctrl2080dma.h" /* NV2080_CTRL_DMA_* */ +#include "ctrl/ctrl2080/ctrl2080fb.h" /* NV2080_CTRL_FB_* */ +#include "ctrl/ctrl2080/ctrl2080fifo.h" /* NV2080_CTRL_FIFO_* */ +#include "ctrl/ctrl2080/ctrl2080gpu.h" /* NV2080_CTRL_GPU_* */ +#include "ctrl/ctrl2080/ctrl2080gr.h" /* NV2080_CTRL_GR_* */ +/* NV5080_DEFERRED_API - deferred RmControl commands */ + + +#define NV5080_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x5080, NV5080_CTRL_##cat,idx) + +/* Command categories (6bits) */ +#define NV5080_CTRL_RESERVED (0x00) +#define NV5080_CTRL_DEFERRED (0x01) + +/* + * NV5080_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV5080_CTRL_CMD_NULL (0x50800000) /* finn: Evaluated from "(FINN_NV50_DEFERRED_API_CLASS_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + + +/* + * NV5080_CTRL_CMD_DEFERRED_API (deprecated; use NV5080_CTRL_CMD_DEFERRED_API_V2 instead) + * + * This command sets up a deferred api call. + * hApiHandle + * Client Unique Handle which is used as the data of a sw method to invoke + * the api in the future + * cmd + * The rmcontrol cmd to invoke as a deferred api. + * flags_delete + * Indicates if an explicit delete is needed (default behavior is to + * auto delete after SW method has executed/completed). + * flags_wait_for_tlb_flush + * Indicates if the API should wait for an InvalidateTlb to also occur + * (not just that it's executed) before being considered completed and + * works in conjunction with flags_delete. + * hClientVA, hDeviceVA + * Client/Device handles of the owner of the virtual address space to + * to be updated (used with the FillPteMem API bundle) + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV5080_CTRL_CMD_DEFERRED_API (0x50800101) /* finn: Evaluated from "(FINN_NV50_DEFERRED_API_CLASS_DEFERRED_INTERFACE_ID << 8) | NV5080_CTRL_DEFERRED_API_PARAMS_MESSAGE_ID" */ + +#define NV5080_CTRL_DEFERRED_API_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV5080_CTRL_DEFERRED_API_PARAMS { + NvHandle hApiHandle; + NvU32 cmd; + NvU32 flags; + NvHandle hClientVA; + NvHandle hDeviceVA; + + union { + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS InitCtx, 8); + + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS PromoteCtx, 8); + + NV2080_CTRL_GPU_EVICT_CTX_PARAMS EvictCtx; + + NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS InvalidateTlb; + + NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS FillPteMem, 8); + + NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS CacheAllocPolicy; + + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS ZcullCtxsw, 8); + + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS PmCtxsw, 8); + + NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS CachePromotePolicy; + + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS PreemptionCtxsw, 8); + } api_bundle; +} NV5080_CTRL_DEFERRED_API_PARAMS; + +#define NV5080_CTRL_CMD_DEFERRED_API_FLAGS_DELETE 0:0 +#define NV5080_CTRL_CMD_DEFERRED_API_FLAGS_DELETE_EXPLICIT (0x00000001) +#define NV5080_CTRL_CMD_DEFERRED_API_FLAGS_DELETE_IMPLICIT (0x00000000) + +#define NV5080_CTRL_CMD_DEFERRED_API_FLAGS_WAIT_FOR_TLB_FLUSH 1:1 +#define NV5080_CTRL_CMD_DEFERRED_API_FLAGS_WAIT_FOR_TLB_FLUSH_FALSE (0x00000000) +#define NV5080_CTRL_CMD_DEFERRED_API_FLAGS_WAIT_FOR_TLB_FLUSH_TRUE (0x00000001) +/* + * NV5080_CTRL_CMD_DEFERRED_API_V2 + * + * This command sets up a deferred api call. + * hApiHandle + * Client Unique Handle which is used as the data of a sw method to invoke + * the api in the future + * cmd + * The rmcontrol cmd to invoke as a deferred api. + * flags_delete + * Indicates if an explicit delete is needed (default behavior is to + * auto delete after SW method has executed/completed). + * flags_wait_for_tlb_flush + * Indicates if the API should wait for an InvalidateTlb to also occur + * (not just that it's executed) before being considered completed and + * works in conjunction with flags_delete. + * hClientVA, hDeviceVA + * Client/Device handles of the owner of the virtual address space to + * to be updated (used with the FillPteMem API bundle) + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV5080_CTRL_CMD_DEFERRED_API_V2 (0x50800103) /* finn: Evaluated from "(FINN_NV50_DEFERRED_API_CLASS_DEFERRED_INTERFACE_ID << 8) | NV5080_CTRL_DEFERRED_API_V2_PARAMS_MESSAGE_ID" */ + +#define NV5080_CTRL_DEFERRED_API_V2_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV5080_CTRL_DEFERRED_API_V2_PARAMS { + NvHandle hApiHandle; + NvU32 cmd; + NvU32 flags; + NvHandle hClientVA; + NvHandle hDeviceVA; + + union { + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS InitCtx, 8); + + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS PromoteCtx, 8); + + NV2080_CTRL_GPU_EVICT_CTX_PARAMS EvictCtx; + + NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS InvalidateTlb; + + NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS FillPteMem, 8); + + NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS CacheAllocPolicy; + + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS ZcullCtxsw, 8); + + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS PmCtxsw, 8); + + NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS CachePromotePolicy; + + NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS DisableChannels, 8); + + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS PreemptionCtxsw, 8); + + NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS ChannelInfoUpdate, 8); + } api_bundle; +} NV5080_CTRL_DEFERRED_API_V2_PARAMS; + +/* + * NV5080_CTRL_CMD_REMOVE_API + * + * This command removes an explicit deferred api call. + * hApiHandle + * Client Unique Handle which is used as the data of a sw method to invoke + * the api in the future + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV5080_CTRL_CMD_REMOVE_API (0x50800102) /* finn: Evaluated from "(FINN_NV50_DEFERRED_API_CLASS_DEFERRED_INTERFACE_ID << 8) | NV5080_CTRL_REMOVE_API_PARAMS_MESSAGE_ID" */ + +#define NV5080_CTRL_REMOVE_API_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV5080_CTRL_REMOVE_API_PARAMS { + NvHandle hApiHandle; +} NV5080_CTRL_REMOVE_API_PARAMS; + +/* _ctrl5080_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl83de.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl83de.h new file mode 100644 index 0000000..12d792a --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl83de.h @@ -0,0 +1,36 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl83de.finn +// + + + + +#include "ctrl/ctrlxxxx.h" +#include "ctrl83de/ctrl83dedebug.h" + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl83de/ctrl83debase.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl83de/ctrl83debase.h new file mode 100644 index 0000000..6ab74be --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl83de/ctrl83debase.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl83de/ctrl83debase.finn +// + +#include "ctrl/ctrlxxxx.h" +/* GT200_DEBUG control commands and parameters */ + +#define NV83DE_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x83DEU, NV83DE_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NV83DE_CTRL_RESERVED (0x00) +#define NV83DE_CTRL_GR (0x01) +#define NV83DE_CTRL_FIFO (0x02) +#define NV83DE_CTRL_DEBUG (0x03) +#define NV83DE_CTRL_INTERNAL (0x04) + + +/* + * NV83DE_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV83DE_CTRL_CMD_NULL (0x83de0000) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrl83debase_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h new file mode 100644 index 0000000..c4c36b0 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h @@ -0,0 +1,1106 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl83de/ctrl83dedebug.finn +// + +#include "ctrl/ctrl83de/ctrl83debase.h" +#include "nvstatus.h" + +#include "ctrl/ctrl2080/ctrl2080gpu.h" + + + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG + * + * This command sets the MMU DEBUG mode. This is Fermi-onwards feature. + * If the query is made on an incorrect platform (for example, pre-Fermi) + * the call will return with an NV_ERR_NOT_SUPPORTED error. + * + * action + * The possible action values are: + * - NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_ENABLE + * This enables the MMU debug mode if possible. If however, any another + * client has already disabled the mode (via NV83DE call) then this + * operation returns NV_ERR_STATE_IN_USE. + * + * - NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_DISABLE + * This disables the MMU debug mode if possible. If however, any another + * client has already enabled the mode (via NV83DE call) then this + * operation returns NV_ERR_STATE_IN_USE. + * + * - NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_DEBUG_REQUESTS + * This operation releases all the client's outstanding requests to enable + * or disable the MMU debug mode. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG (0x83de0307) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS { + NvU32 action; +} NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS; + +#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_ENABLE (0x00000001) +#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_DISABLE (0x00000002) +#define NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_DEBUG_REQUESTS (0x00000003) + +/* + * NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG + * + * This command gets the value of currently configured MMU DEBUG mode. + * This is Fermi-onwards feature. If the query is made on an incorrect + * platform (for example, pre-Fermi) the call will return with an + * NV_ERR_NOT_SUPPORTED error. + * + * value + * This parameter returns the configured value. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG (0x83de0308) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS { + NvU32 value; +} NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS; + +#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG_ENABLED (0x00000001) +#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG_DISABLED (0x00000002) + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_EXCEPTION_MASK + * + * This command allows the caller to filter events (which are also referred to + * as "notifications", not to be confused with true notifiers), in the RM, + * fairly close to the source of the events. In other words, depending on the + * value of the exceptionMask, some events may not be raised. + * + * The original reason for creating this command is that the CUDA driver needs + * to place the RM and the GPU(s) into SM debug mode, for some GPUs, in order to + * activate various features and HW bug WARs. Being in SM debug mode has the + * side effect of exposing the caller to debug events, which are generally + * undesirable for the CUDA driver, but desirable for the CUDA debugger. This + * command allows each client to receive only the events that it is + * specifically interested in. + * + * If this command is never invoked, then the RM will behave as if + * exceptionMask==NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_ALL. + * + * As with many of the debugger features, this is Fermi-onwards feature. If this + * API call is issued on an earlier platform, it will return an + * NV_ERR_NOT_SUPPORTED error. + * + * exceptionMask + * This identifies the category of notifications that the debug client + * is interested in. + * + * Here are the allowed values for exceptionMask: + * + * - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_FATAL + * This means that the caller wishes to receive events for any exceptions + * that are classified as fatal. For example, + * HWW_WARP_ESR_ERROR_PC_OVERFLOW is one such exception. + * + * If any debug object, in any channel, has registered to receive events + * for _FATAL exceptions, then RC recovery will be deferred if such an + * exception occurs. + * + * Also, if a client is registered for fatal exceptions, RC error recovery + * will be deferred. If not registered for fatal exceptions, then fatal + * errors will (as usual) cause RC recovery to run immediately. + * + * - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_TRAP + * This means that an event will be raised when an SM executes a bpt.pause + * instruction. Note that on Fermi, the SM raises HWW when bpt.trap is + * executed as well, so this event will also be raised in that situation. + * + * - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_SINGLE_STEP + * This means that an event will be raised a single step completion + * interrupt is received. + * + * - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_INT + * This means that an event will be raised when an SM executes a bpt.int + * instruction. + * + * - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_NONE + * This means that no debug events will be raised. + * + * - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_ALL + * This means that an event will be raised for any and all debug + * exceptions. This is the default behavior. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_EXCEPTION_MASK (0x83de0309) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS { + NvU32 exceptionMask; +} NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS; + +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_FATAL (0x00000001) +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_TRAP (0x00000002) +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_SINGLE_STEP (0x00000004) +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_INT (0x00000008) +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_CILP (0x00000010) +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PREEMPTION_STARTED (0x00000020) +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_NONE (0x00000000) +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_ALL (0x0000FFFF) + + + +/* + * NV83DE_CTRL_CMD_READ_SINGLE_SM_ERROR_STATE + * + * This command reads the SM error state of a single SM. The error state + * consists of several 32-bit values. + * + * Note that this acts upon the currently resident GR (graphics) context. It is + * up to the RM client to ensure that the desired GR context is resident, before + * making this API call. + * + * See also: NV83DE_CTRL_CMD_READ_ALL_SM_ERROR_STATES. + * + * This is a Fermi-and-later feature. If this API call is issued on an earlier + * platform, it will return an NV_ERR_NOT_SUPPORTED error. + * + * Parameters: + * + * hTargetChannel (input) + * This identifies the channel. + * + * smID (input) + * This identifies the SM. Allowed values are any valid SM ID. The RM + * grProgramSmIdNumbering_HAL() routines are a good place to look, in order + * to see how SM IDs are set up. The main idea is that the RM chooses a + * numbering scheme, and then informs the GPU hardware of that scheme, by + * actually recording each SM ID into the GPU, via a series of PRI (GPU + * register) writes. + * + * smErrorState.hwwGlobalEsr (output) + * Value of the Global Error Status Register. + * + * smErrorState.hwwWarpEsr (output) + * Value of the Warp Error Status Register. + * + * smErrorState.hwwWarpEsrPc (output) : DEPRECATED for 64b PC below, will hold low 32b for now + * Value of the Warp Error Status Register Program Counter. + * + * smErrorState.hwwGlobalEsrReportMask (output) + * Value of the Global Error Status Register Report Mask. + * + * smErrorState.hwwWarpEsrReportMask (output) + * Value of the Error Status Register Report Mask. + * + * smErrorState.hwwWarpEsrPc64 (output) + * Value of the 64b Warp Error Status Register Program Counter. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_READ_SINGLE_SM_ERROR_STATE (0x83de030b) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID" */ + +typedef struct NV83DE_SM_ERROR_STATE_REGISTERS { + NvU32 hwwGlobalEsr; + NvU32 hwwWarpEsr; + NvU32 hwwWarpEsrPc; + NvU32 hwwGlobalEsrReportMask; + NvU32 hwwWarpEsrReportMask; + NV_DECLARE_ALIGNED(NvU64 hwwEsrAddr, 8); + NV_DECLARE_ALIGNED(NvU64 hwwWarpEsrPc64, 8); + NvU32 hwwCgaEsr; + NvU32 hwwCgaEsrReportMask; +} NV83DE_SM_ERROR_STATE_REGISTERS; + +#define NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS { + NvHandle hTargetChannel; + NvU32 smID; + NV_DECLARE_ALIGNED(NV83DE_SM_ERROR_STATE_REGISTERS smErrorState, 8); +} NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS; + +/* + * NV83DE_CTRL_CMD_READ_ALL_SM_ERROR_STATES + * + * This command reads the SM error state of all SMs. + * + * Note that this acts upon the currently resident GR (graphics) context. It is + * up to the RM client to ensure that the desired GR context is resident, before + * making this API call. + * + * Parameters: + * + * hTargetChannel (input) + * This identifies the channel. + * + * numSMsToRead (input) + * This should be set to the number of SMs that the RM is supposed to read. + * It will typically be the total number of SMs in the GPU. For best + * results, you should not pass in a value that is greater than the number + * of SMs that the GPU actually contains. + * + * startingSM (input) + * This should be set to the starting index of the first SM to read. + * Clients may use this to read data from SMs beyond the maximum specified + * in NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL. + * + * smErrorStateArray (output) + * This is an array of NV83DE_SM_ERROR_STATE_REGISTERS structs. Please see + * the description of NV83DE_CTRL_CMD_READ_SINGLE_SM_ERROR_STATE, above, for + * a description of the individual fields. + * + * mmuFault.valid (output) + * This is NV_TRUE if an MMU fault occurred on the target channel since the last call to + * NV83DE_CTRL_CMD_CLEAR_ALL_SM_ERROR_STATES to this channel. + * + * mmuFault.faultInfo (output) + * This is the value of the first NV_PFIFO_INTR_MMU_FAULT_INFO that caused the MMU fault. + * + * mmuFaultInfo (output) + * Deprecated field, see mmuFault.faultInfo + * + * This is a Fermi-and-later feature. If this API call is issued on an earlier + * platform, it will return an NV_ERR_NOT_SUPPORTED error. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_READ_ALL_SM_ERROR_STATES (0x83de030c) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL 100 + +typedef struct NV83DE_MMU_FAULT_INFO { + NvBool valid; + NvU32 faultInfo; +} NV83DE_MMU_FAULT_INFO; + +#define NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS { + NvHandle hTargetChannel; + NvU32 numSMsToRead; + NV_DECLARE_ALIGNED(NV83DE_SM_ERROR_STATE_REGISTERS smErrorStateArray[NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL], 8); + NvU32 mmuFaultInfo; // Deprecated, use mmuFault field instead + NV83DE_MMU_FAULT_INFO mmuFault; + NvU32 startingSM; +} NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS; + +/* + * NV83DE_CTRL_CMD_CLEAR_SINGLE_SM_ERROR_STATE + * + * This command clears the SM error state of a single SM. The error state + * consists of several 32-bit values. + * + * Note that this acts upon the currently resident GR (graphics) context. It is + * up to the RM client to ensure that the desired GR context is resident, before + * making this API call. + * + * See also: NV83DE_CTRL_CMD_CLEAR_ALL_SM_ERROR_STATES. + * + * This API call has a slightly different effect than what would occur as a + * result of issuing a read-modify-write via _READ_SINGLE_SM_ERROR_STATE and + * _WRITE_SINGLE_SM_ERROR_STATE. The difference arises due to the fact that RM + * is caching the error state, to compensate for the fact that the real GPU + * error state must be cleared very early on in the exception handling routine. + * + * In other words, the _READ data is stale by design, and cannot be used in a + * read-modify-write routine from user space. Therefore, in order to clear the + * SM error state, a separate RM API call is required. + * + * This is a Fermi-and-later feature. If this API call is issued on an earlier + * platform, it will return an NV_ERR_NOT_SUPPORTED error. + * + * Parameters: + * + * hTargetChannel (input) + * This identifies the channel. + * + * smID (input) + * This identifies the SM. Allowed values are any valid SM ID. Please see + * NV83DE_CTRL_CMD_READ_SINGLE_SM_ERROR_STATE for further details. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE (0x83de030f) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS { + NvHandle hTargetChannel; + NvU32 smID; +} NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS; + +/* + * NV83DE_CTRL_CMD_CLEAR_ALL_SM_ERROR_STATES + * + * This command clears the SM error state of all SMs. + * + * Note that this acts upon the currently resident GR (graphics) context. It is + * up to the RM client to ensure that the desired GR context is resident, before + * making this API call. + * + * Parameters: + * + * hTargetChannel (input) + * This identifies the channel. + * + * numSMsToClear (input) + * This should be set to the number of SMs that the RM is supposed to write. + * It will typically be the total number of SMs in the GPU. For best + * results, you should not pass in a value that is greater than the number + * of SMs that the GPU actually contains. + * + * Please see the description of + * NV83DE_CTRL_CMD_CLEAR_SINGLE_SM_ERROR_STATE, above, for a description of + * why these two _CLEAR API calls are required. + * + * This is a Fermi-and-later feature. If this API call is issued on an earlier + * platform, it will return an NV_ERR_NOT_SUPPORTED error. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_CLEAR_ALL_SM_ERROR_STATES (0x83de0310) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS { + NvHandle hTargetChannel; + NvU32 numSMsToClear; +} NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS; + + + +#define NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS_DEFINED 1 +#define NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_HAS_RESIDENT_CHANNEL 1 +typedef struct NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS { + NvU32 waitForEvent; + NvHandle hResidentChannel; +} NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS; + + + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE + * + * This command set the type of action we want on RM encountering an error + * and issuing a STOP_TRIGGER. The action will be to either braodcast the + * STOP_TRIGGER to all SM's, or just send to the SM hitting an exception. + * + * stopTriggerType + * This identifies trigger type to initiate. + * + * Here are the allowed values for stopTriggerType: + * + * - NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_SINGLE_SM + * This means that we will issue STOP_TRIGGER to the single SM + * noted in the exception + * + * - NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_BROADCAST + * This means that we will issue STOP_TRIGGER to all SM's + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE (0x83de0313) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS { + NvU32 stopTriggerType; +} NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS; + +#define NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_SINGLE_SM (0x00000001) +#define NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_BROADCSAT (0x00000002) + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING + * + * This command sets the type of action we want on RM encountering a + * SINGLE_STEP exception while in CILP debug mode. In the normal case, + * non-pausing, we ignore these exceptions as on prior chips. When the + * user selects pausing, it will cause the exception to be treated just + * like we had seen an SM error or BPT_PAUSE. + * + * singleStepHandling + * This identifies single step handling type to use. + * + * Here are the allowed values for singleStepHandling: + * + * - NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_NONPAUSING + * Treat SINGLE_STEP exceptions while in debug mode as non-pausing, + * which is the default/normal mode in the interrupt pre-process + * function, where they are ignored. + * + * - NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PAUSING + * Treat SINGLE_STEP exceptions while in debug mode as pausing, + * which means in the interrupt pre-process function they will + * be treated like BPT_PAUSE and SM error exceptions + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING (0x83de0314) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS { + NvU32 singleStepHandling; +} NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS; + +#define NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_NONPAUSING (0x00000001) +#define NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PAUSING (0x00000002) + +/* + * NV83DE_CTRL_CMD_DEBUG_READ_MEMORY + * + * This command reads a block of memory. + * This command is deprecated in favor of NV83DE_CTRL_CMD_DEBUG_READ_BATCH_MEMORY + * + * hMemory [IN] + * The handle to the memory being accessed. If hMemory is not accessible + * from the caller's address space, NV_ERR_INSUFFICIENT_PERMISSIONS + * is returned. + * + * length [IN/OUT] + * Number of bytes to read, as well as the number of bytes actually read + * returned. + * + * offset [IN] + * The offset into the physical memory region given by the handle above. + * + * buffer [OUT] + * The data read is returned in this buffer. + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ACCESS_TYPE + * NV_ERR_INSUFFICIENT_PERMISSIONS + * + */ +#define NV83DE_CTRL_CMD_DEBUG_READ_MEMORY (0x83de0315) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS { + NvU32 hMemory; + NvU32 length; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvP64 buffer, 8); +} NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_WRITE_MEMORY + * + * This command writes a block of memory. + * This command is deprecated in favor of NV83DE_CTRL_CMD_DEBUG_WRITE_BATCH_MEMORY + * + * hMemory [IN] + * The handle to the memory being accessed. If hMemory is not accessible + * from the caller's address space, NV_ERR_INSUFFICIENT_PERMISSIONS + * is returned. + * + * length [IN/OUT] + * Number of bytes to write, as well as the number of bytes actually + * written. + * + * offset [IN] + * The offset into the physical memory region given by the handle above. + * + * buffer [IN] + * The data to be written is sent in this buffer. + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ACCESS_TYPE + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +#define NV83DE_CTRL_CMD_DEBUG_WRITE_MEMORY (0x83de0316) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS { + NvU32 hMemory; + NvU32 length; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvP64 buffer, 8); +} NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT + * + * This command suspends a SM context associated with the debugger object. + * + * When the suspend call returns, context associated with the debugger object + * should not be actively executing any code on any SM. The channel will have + * been disabled if not resident on GR, or have its SM suspended if it was resident. + * + * This is a Fermi-and-later feature. If this API call is issued on an earlier + * platform, it will return an NV_ERR_NOT_SUPPORTED error. + * + * waitForEvent + * This return param indicates if the call had to issue a Preempt, + * therefore it is in process and user may need to wait for it. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_STATE + */ +#define NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT (0x83de0317) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_MESSAGE_ID (0x17U) + +typedef NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_RESUME_CONTEXT + * + * This command safely resumes the SM context associated with the debugger object. + * + * This is a Fermi-and-later feature. If this API call is issued on an earlier + * platform, it will return an NV_ERR_NOT_SUPPORTED error. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_STATE + */ +#define NV83DE_CTRL_CMD_DEBUG_RESUME_CONTEXT (0x83de0318) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x18" */ + +/* + * NV83DE_CTRL_CMD_DEBUG_GET_HANDLES + * + * This command returns relevant handles for the debug object + * This command is only available on debug and develop builds. + * + * Possible return values: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_CLIENT + * NV_ERR_INVALID_OBJECT_HANDLE + * + */ +#define NV83DE_CTRL_CMD_DEBUG_GET_HANDLES (0x83de0319) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x19" */ + +typedef struct NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS { + NvHandle hChannel; + NvHandle hSubdevice; +} NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS; + +/* + * NV83DE_CTRL_CMD_READ_SURFACE + * + * This command allows the caller to copy the data from a specified gpuVA + * to a usermode buffer. Before copying, this command validates whether or + * not the virtual address (VA) range provided as input has valid and allocated + * pages mapped to it in its entirety. + * + * This command's input is NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS which + * contains a buffer of NV83DE_CTRL_DEBUG_ACCESS_OPs + * + * Possible return values: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_XLATE + */ +#define NV83DE_CTRL_CMD_READ_SURFACE (0x83de031a) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x1A" */ + +/* + * NV83DE_CTRL_CMD_WRITE_SURFACE + * + * This command allows the caller to copy the data from a provided usermode + * buffer to a specified GPU VA. Before copying, this command validates whether or + * not the virtual address (VA) range provided as input has valid and allocated + * pages mapped to it in its entirety. + * + * This command's input is NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS which + * contains a buffer of NV83DE_CTRL_DEBUG_ACCESS_OPs + * + * Possible return values: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_XLATE + */ +#define NV83DE_CTRL_CMD_WRITE_SURFACE (0x83de031b) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x1B" */ + +#define MAX_ACCESS_OPS 64 + +typedef struct NV83DE_CTRL_DEBUG_ACCESS_OP { + NV_DECLARE_ALIGNED(NvU64 gpuVA, 8); // IN + NV_DECLARE_ALIGNED(NvP64 pCpuVA, 8); // IN/OUT Debugger CPU Pointer of buffer + NvU32 size; // IN Size in bytes + NvU32 valid; // OUT Whether the GpuVA is accessible +} NV83DE_CTRL_DEBUG_ACCESS_OP; + +typedef struct NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS { + NvU32 count; // IN Number of ops in this call + NV_DECLARE_ALIGNED(NV83DE_CTRL_DEBUG_ACCESS_OP opsBuffer[MAX_ACCESS_OPS], 8); +} NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS; + +/* + * NV83DE_CTRL_CMD_GET_MAPPINGS + * + * This command traverses through the virtual memory page hierarchy and + * fetches the valid virtual mappings and their sizes for a provided virtual + * address (VA) range. + * If a given VA range has more than MAX_GET_MAPPINGS_OPS valid mappings, + * hasMore is set to 1, and opsBuffer is still filled with MAX_GET_MAPPINGS_OPS + * valid mappings. In this case, this command should be called again with + * vaLo = opsBuffer[MAX_GET_MAPPINGS_OPS - 1].gpuVA + + * opsBuffer[MAX_GET_MAPPINGS_OPS - 1].size; + * and vaHi set to the next desired upper limit. + * + * This command's input is NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS which + * contains a buffer of NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP + * + * Possible return values: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_XLATE + */ +#define NV83DE_CTRL_CMD_GET_MAPPINGS (0x83de031c) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x1C" */ + +#define MAX_GET_MAPPINGS_OPS 64 + +typedef struct NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP { + NV_DECLARE_ALIGNED(NvU64 gpuVA, 8); // OUT Start of GPU VA for this mapping + NvU32 size; // OUT Size in bytes of this mapping +} NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP; + +typedef struct NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS { + NV_DECLARE_ALIGNED(NvU64 vaLo, 8); // IN Lower VA range, inclusive + NV_DECLARE_ALIGNED(NvU64 vaHi, 8); // IN Upper VA range, inclusive + NvU32 count; // OUT Number of ops in this call + NvU32 hasMore; // OUT Whether there are more valid mappings in this range than MAX_GET_MAPPINGS_OPS + NV_DECLARE_ALIGNED(NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP opsBuffer[MAX_GET_MAPPINGS_OPS], 8); +} NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS; + +/* + * NV83DE_CTRL_CMD_DEBUG_EXEC_REG_OPS + * + * This command is used to submit a buffer containing one or more + * NV2080_CTRL_GPU_REG_OP structures for processing. Each entry in the + * buffer specifies a single read or write operation. Each entry is checked + * for validity in an initial pass over the buffer with the results for + * each operation stored in the corresponding regStatus field. Unless + * bNonTransactional flag is set to true, if any invalid entries are found + * during this initial pass then none of the operations are executed. Entries + * are processed in order within each regType with NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL + * entries processed first followed by NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX entries. + * + * [IN] bNonTransactional + * This field specifies if command is non-transactional i.e. if set to + * true, all the valid operations will be executed. + * + * [IN] regOpCount + * This field specifies the number of valid entries in the regops list. + * + * [IN/OUT] regOps + * This field is to be filled with the desired register information that is + * to be retrieved. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV83DE_CTRL_CMD_DEBUG_EXEC_REG_OPS (0x83de031d) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_GPU_EXEC_REG_OPS_MAX_OPS 100 +#define NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_MESSAGE_ID (0x1DU) + +typedef struct NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS { + NvBool bNonTransactional; + NvU32 regOpCount; + // C form: NV2080_CTRL_GPU_REG_OP regOps[NV2080_CTRL_GPU_EXEC_REG_OPS_MAX_OPS] + NV2080_CTRL_GPU_REG_OP regOps[NV83DE_CTRL_GPU_EXEC_REG_OPS_MAX_OPS]; +} NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR + * + * This command sets the Errbar Debug mode. This is Volta-onwards feature. + * If the query is made on an incorrect platform (for example, pre-Volta) + * the call will return with an NV_ERR_NOT_SUPPORTED error. + * + * action + * The possible action values are: + * - NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_ENABLE + * This enables the Errbar debug mode. + * + * - NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DISABLE + * This disables the Errbar debug mode. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_WRITE + * NV_ERR_INVALID_ARGUMENT + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG (0x83de031f) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID (0x1FU) + +typedef struct NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS { + NvU32 action; +} NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS; + +#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG_DISABLE (0x00000000) +#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG_ENABLE (0x00000001) + +/* + * NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR + * + * This command gets the value of currently configured Errbar DEBUG mode. + * This is Volta-onwards feature. If the query is made on an incorrect + * platform (for example, pre-Volta) the call will return with an + * NV_ERR_NOT_SUPPORTED error. + * + * value + * This parameter returns the configured value. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_READ + * NV_ERR_INVALID_ARGUMENT + */ +#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG (0x83de0320) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS { + NvU32 value; +} NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS; + +#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG_DISABLED (0x00000000) +#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG_ENABLED (0x00000001) + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SINGLE_STEP + * + * This command either enables or disables single step mode for the given SM. + * + * smID (input) + * This identifies the SM. + * bSingleStep (input) + * This indicates the single step mode. NV_TRUE for ENABLED. + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SINGLE_STEP (0x83de0321) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_MESSAGE_ID (0x21U) + +typedef struct NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS { + NvU32 smID; + NvBool bSingleStep; +} NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_STOP_TRIGGER + * + * This command sets or clears the stop trigger for the given SM. + * + * smID (input) + * This identifies the SM. + * bStopTrigger (input) + * This indicates whether to set or clear the trigger. NV_TRUE for ENABLED. + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_STOP_TRIGGER (0x83de0322) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_BROADCAST ((NvU32)~0) + +#define NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS { + NvU32 smID; + NvBool bStopTrigger; +} NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_RUN_TRIGGER + * + * This command sets or clears the run trigger for the given SM. + * + * smID (input) + * This identifies the SM. + * bRunTrigger (input) + * This indicates whether to set or clear the trigger. NV_TRUE for ENABLED. + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_RUN_TRIGGER (0x83de0323) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS_MESSAGE_ID (0x23U) + +typedef struct NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS { + NvU32 smID; + NvBool bRunTrigger; +} NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT + * + * This command enables or disables skip idle warp detect for the given sm. + * + * smID (input) + * This identifies the SM. + * bSkipIdleWarpDetect (input) + * This indicates whether to enable or disable the mode. NV_TRUE for ENABLED. + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT (0x83de0324) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS_MESSAGE_ID (0x24U) + +typedef struct NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS { + NvU32 smID; + NvBool bSkipIdleWarpDetect; +} NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS + * + * This command retrieves the debugger status states of the given SM. + * + * smID (input) + * This identifies the SM. + * bInTrapMode (output) + * This indicates whether the SM is in trap mode. + * bCrsFlushDone (output) + * Deprecated GK110+. Always 0 Volta+. + * bRunTriggerInProgress (output) + * Deprecated GM10X+. Always 0 Volta+. + * bComputeContext (output) + * Deprecated GM10X+. Always 0 Volta+. + * bLockedDown (output) + * This indicates whether the SM is locked down. + */ +#define NV83DE_CTRL_CMD_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS (0x83de0325) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS_MESSAGE_ID" */ + +typedef struct NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS { + NvBool bInTrapMode; + NvBool bCrsFlushDone; + NvBool bRunTriggerInProgress; + NvBool bComputeContext; + NvBool bLockedDown; +} NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS; + +#define NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS_MESSAGE_ID (0x25U) + +typedef struct NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS { + NvU32 smID; + NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS smDebuggerStatus; +} NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS; + +/*! + * NV83DE_CTRL_CMD_DEBUG_ACCESS_MEMORY_ENTRY + * + * This struct represents a requet to read/write a block of memory. + * + * hMemory [IN] + * The handle to the memory being accessed. If hMemory is not accessible + * from the caller's address space, NV_ERR_INSUFFICIENT_PERMISSIONS + * is returned. + * + * length [IN] + * Number of bytes to read/write + * + * memOffset [IN] + * The offset into the physical memory region given by the handle above. + * + * dataOffset [IN] + * An offset into the usermode memory region provided by the enclosing + * params indicating where to read/write data from/to. + * + * status [OUT] + * The result status of the operation will be output. If NV_OK, even if + * command returned error status, the given operation was successful. If + * not NV_OK, it is guaranteed that the command will return error status. + */ +typedef struct NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY { + NvHandle hMemory; + NvU32 length; + NV_DECLARE_ALIGNED(NvU64 memOffset, 8); + NvU32 dataOffset; + NV_STATUS status; +} NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY; + +/*! + * NV83DE_CTRL_CMD_DEBUG_READ_BATCH_MEMORY + * + * Execute a batch of read memory operations. + * + * count [IN] + * Number of read/write operations to perform. + * + * dataLength [IN] + * Length of the usermode buffer passed in, in bytes. + * + * pData [OUT] + * Usermode buffer to store the output of the read operations. Each + * operation is expected to provide an offset into this buffer. + * + * entries [IN] + * List of operations to perform. First `count` entries are used. + */ +#define NV83DE_CTRL_CMD_DEBUG_READ_BATCH_MEMORY (0x83de0326) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x26" */ + +/*! + * NV83DE_CTRL_CMD_DEBUG_WRITE_BATCH_MEMORY + * + * Execute a batch of write memory operations. + * + * count [IN] + * Number of read/write operations to perform. + * + * dataLength [IN] + * Length of the usermode buffer passed in, in bytes. + * + * pData [IN] + * Usermode buffer to store the input of the write operations. Each + * operation is expected to provide an offset into this buffer. + * + * entries [IN] + * List of operations to perform. First `count` entries are used. + */ +#define NV83DE_CTRL_CMD_DEBUG_WRITE_BATCH_MEMORY (0x83de0327) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x27" */ + +#define MAX_ACCESS_MEMORY_OPS 150 +typedef struct NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pData, 8); + NvU32 dataLength; + NvU32 count; + NV_DECLARE_ALIGNED(NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY entries[MAX_ACCESS_MEMORY_OPS], 8); +} NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS; + +/* + * NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY + * + * faultAddress (OUT) + * Faulting address + * faultType (OUT) + * Type of MMU fault + * accessType (OUT) + * Type of access that caused this fault + */ +#define NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_MAX_ENTRIES 4 +typedef struct NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY { + NV_DECLARE_ALIGNED(NvU64 faultAddress, 8); + NvU32 faultType; + NvU32 accessType; +} NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY; + +/* + * NV83DE_CTRL_CMD_DEBUG_READ_MMU_FAULT_INFO + * + * mmuFaultInfoList (OUT) + * Entries of MMU faults recorded for the attached context. The cached data is only cleared via LRU policy when new MMU faults arrive so repeat data may be returned by this command. + * count (OUT) + * Number of MMU fault entries contain valid data. + */ +#define NV83DE_CTRL_CMD_DEBUG_READ_MMU_FAULT_INFO (0x83de0328) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x28U) + +typedef struct NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS { + NV_DECLARE_ALIGNED(NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY mmuFaultInfoList[NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_MAX_ENTRIES], 8); + NvU32 count; +} NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS; + +/* _ctrl83dedebug_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl9010.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl9010.h new file mode 100644 index 0000000..43dada9 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl9010.h @@ -0,0 +1,83 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl9010.finn +// + +#include "ctrl/ctrlxxxx.h" +#define NV9010_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0x9010, NV9010_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NV9010_CTRL_RESERVED (0x00) +#define NV9010_CTRL_VBLANK_CALLBACK (0x01) + + +/* + * NV9010_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV9010_CTRL_CMD_NULL (0x90100000) /* finn: Evaluated from "(FINN_NV9010_VBLANK_CALLBACK_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION + * + * This command is used to enable and disable vblank notifications. This + * is specially intended for cases where the RM client is calling from a + * high IRQL context, where other mechanisms to toggle vblank notification + * (such as freeing and reallocating the NV9010_VBLANK_CALLBACK object) + * would not be suitable. As this is being invoked at the high IRQL, + * locking can be bypassed, if the NVOS54_FLAGS_LOCK_BYPASS flag is set on + * the control call.Here the OS will take care of the synchronization. + * The Windows Display Driver for Cobalt requires this, for example. + * + * bSetVBlankNotifyEnable + * This parameter tell whether to enable or disable the Vblank notification + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION (0x90100101) /* finn: Evaluated from "(FINN_NV9010_VBLANK_CALLBACK_INTERFACE_ID << 8) | NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION_PARAMS_MESSAGE_ID (0x01U) + +typedef struct NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION_PARAMS { + NvBool bSetVBlankNotifyEnable; +} NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION_PARAMS; + +/* _ctrl9010_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl9067.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl9067.h new file mode 100644 index 0000000..62cb948 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl9067.h @@ -0,0 +1,150 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl9067.finn +// + +#include "ctrl/ctrlxxxx.h" +/* Subcontext control commands and parameters */ +#define NV9067_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x9067, NV9067_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NV9067_CTRL_RESERVED (0x00) +#define NV9067_CTRL_TPC_PARTITION (0x01) +#define NV9067_CTRL_CWD_WATERMARK (0x02) + +/*! + * Does nothing. + */ +#define NV9067_CTRL_CMD_NULL (0x90670000) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/*! + * NV9067_CTRL_CMD_GET_TPC_PARTITION_TABLE + * This command gets the current partition table configuration of a subcontext + * + * NV9067_CTRL_CMD_SET_TPC_PARTITION_TABLE + * This command sets the partition table of a subcontext + * + * NV9067_CTRL_TPC_PARTITION_TABLE_PARAMS + * This structure defines the parameters used for SET/GET per-subcontext TPC partitioning table configuration + * + * numUsedTpc [in/out] + * Specifies the number of TPCs used by the subcontext + * While querying the enabled TPCs, this is an output paramter + * While configuring the TPCs, this is an input parameter + * + * tpcList [in/out] + * Array containing the TPCs enabled for the subcontext. + * The first numUsedTpc in the array interpreted as the valid entries. + * + * Only applicable for STATIC and DYNAMIC modes. + * + * NV9067_CTRL_TPC_PARTITION_TABLE_MAX_TPC_COUNT + * Max TPC count supported by this ctrl call + * + * NV9067_CTRL_TPC_PARTITION_TABLE_TPC_INFO + * This structure defines the parameters for a TPC + * + * globalTpcIndex + * Global logical index of the enabled TPC + * + * lmemBlockIndex + * Block index of the Local memory backing store for the enabled TPC. + * For GET command, we will return the current lmem block assigment for STATIC & DYNAMIC modes. + * For SET command, this index is relevant only for STATIC mode. + * HW automatically assign it for other modes. So should be zeroed out for other modes. + * + */ +#define NV9067_CTRL_CMD_GET_TPC_PARTITION_TABLE (0x90670101) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_TPC_PARTITION_INTERFACE_ID << 8) | 0x1" */ + +#define NV9067_CTRL_CMD_SET_TPC_PARTITION_TABLE (0x90670102) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_TPC_PARTITION_INTERFACE_ID << 8) | NV9067_CTRL_TPC_PARTITION_TABLE_PARAMS_MESSAGE_ID" */ + +#define NV9067_CTRL_TPC_PARTITION_TABLE_TPC_COUNT_MAX 256 + +typedef struct NV9067_CTRL_TPC_PARTITION_TABLE_TPC_INFO { + NvU16 globalTpcIndex; + NvU16 lmemBlockIndex; +} NV9067_CTRL_TPC_PARTITION_TABLE_TPC_INFO; + +#define NV9067_CTRL_TPC_PARTITION_TABLE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV9067_CTRL_TPC_PARTITION_TABLE_PARAMS { + NvU16 numUsedTpc; + NV9067_CTRL_TPC_PARTITION_TABLE_TPC_INFO tpcList[NV9067_CTRL_TPC_PARTITION_TABLE_TPC_COUNT_MAX]; +} NV9067_CTRL_TPC_PARTITION_TABLE_PARAMS; + + +/*! + * NV9067_CTRL_CMD_GET_CWD_WATERMARK + * This command gets the cached watermark value for a subcontext + * + * NV9067_CTRL_CMD_SET_CWD_WATERMARK + * This command sets the watermark value for a subcontexts + * + * NV9067_CTRL_CWD_WATERMARK_PARAMS + * This structure defines the parameters used to SET/GET watermark value per-subcontext. + * + * watermarkValue [in/out] + * Value of watermark per-subcontext + * Acts as a output parameter to get the current value of watermark for a subcontext. + * Acts as a input parameter to set the current value of watermark for a subcontexts. + * + * NV9067_CTRL_CWD_WATERMARK_VALUE_MIN + * Minimum value of watermark for any subcontext + * RM will throw an error if any value less than this value is specified + * + * NV9067_CTRL_CWD_WATERMARK_VALUE_DEFAULT + * Default value of watermark for any subcontext + * RM will set watermark of a subcontext to this value when the subcontext + * is created/initialized for the first time + * + * NV9067_CTRL_CWD_WATERMARK_VALUE_MAX + * Maximum value of watermark for any subcontext + * RM will throw an error if any value more than this value is specified + * + */ + +#define NV9067_CTRL_CMD_GET_CWD_WATERMARK (0x90670201) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID << 8) | 0x1" */ + +#define NV9067_CTRL_CMD_SET_CWD_WATERMARK (0x90670202) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID << 8) | 0x2" */ + +#define NV9067_CTRL_CWD_WATERMARK_VALUE_MIN 1 +#define NV9067_CTRL_CWD_WATERMARK_VALUE_DEFAULT 2 +#define NV9067_CTRL_CWD_WATERMARK_VALUE_MAX 256 + +typedef struct NV9067_CTRL_CWD_WATERMARK_PARAMS { + NvU32 watermarkValue; +} NV9067_CTRL_CWD_WATERMARK_PARAMS; + + +/* _ctrl9067_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl906f.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl906f.h new file mode 100644 index 0000000..8be99d2 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl906f.h @@ -0,0 +1,261 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl906f.finn +// + + + + +/* GF100_GPFIFO control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#define NV906F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0x906F, NV906F_CTRL_##cat, idx) + +/* GF100_GPFIFO command categories (6bits) */ +#define NV906F_CTRL_RESERVED (0x00) +#define NV906F_CTRL_GPFIFO (0x01) +#define NV906F_CTRL_EVENT (0x02) + + +/* + * NV906F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV906F_CTRL_CMD_NULL (0x906f0000) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + + +/* + * NV906F_CTRL_GET_CLASS_ENGINEID + * + * Takes an object handle as input and returns + * the Class and Engine that this object uses. + * + * hObject + * Handle to an object created. For example a + * handle to object of type FERMI_A created by + * the client. This is supplied by the client + * of this call. + * + * classEngineID + * A concatenation of class and engineid + * that the object with handle hObject + * belongs to. This is returned by RM. The internal + * format of this data structure is opaque to clients. + * + * classID + * ClassID for object represented by hObject + * + * engineID + * EngineID for object represented by hObject + * + * Possible status values returned are: + * NV_OK + * If the call was successful. + * + * NV_ERR_INVALID_OBJECT_HANDLE + * No object of handle hObject was found. + */ +#define NV906F_CTRL_GET_CLASS_ENGINEID (0x906f0101) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */ + +#define NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS { + NvHandle hObject; + NvU32 classEngineID; + NvU32 classID; + NvU32 engineID; +} NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS; + +/* + * NV906F_CTRL_RESET_CHANNEL + * + * This command resets the channel corresponding to specified engine and also + * resets the specified engine. + * + * Takes an engine ID as input. + * + * engineID + * This parameter specifies the engine to be reset. See the description of the + * NV2080_ENGINE_TYPE values in cl2080.h for more information. + * subdeviceInstance + * This parameter specifies the subdevice to be reset when in SLI. + * resetReason + * Specifies reason to reset a channel. + * + * Possible status values returned are: + * NV_OK + */ +#define NV906F_CTRL_CMD_RESET_CHANNEL_REASON_DEFAULT 0 +#define NV906F_CTRL_CMD_RESET_CHANNEL_REASON_VERIF 1 +#define NV906F_CTRL_CMD_RESET_CHANNEL_REASON_MMU_FLT 2 +#define NV906F_CTRL_CMD_RESET_CHANNEL_REASON_ENUM_MAX 3 +/* + * Internal values for NV906F_CTRL_CMD_RESET_REASON. External values will be + * checked and enforced to be < NV906F_CTRL_CMD_RESET_CHANNEL_REASON_ENUM_MAX + */ +#define NV906F_CTRL_CMD_INTERNAL_RESET_CHANNEL_REASON_FAKE_ERROR (0x4) /* finn: Evaluated from "NV906F_CTRL_CMD_RESET_CHANNEL_REASON_ENUM_MAX + 1" */ + + +#define NV906F_CTRL_CMD_RESET_CHANNEL (0x906f0102) /* finn: Evaluated from "((FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID)" */ + +#define NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS { + NvU32 engineID; + NvU32 subdeviceInstance; + NvU32 resetReason; +} NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS; + +/* + * NV906F_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * This command sets event notification state for the associated channel. + * This command requires that an instance of NV01_EVENT has been previously + * bound to the associated channel object. + * + * event + * This parameter specifies the type of event to which the specified + * action is to be applied. This parameter must specify a valid + * NV906F_NOTIFIERS value (see cl906f.h for more details) and should + * not exceed one less NV906F_NOTIFIERS_MAXCOUNT. + * action + * This parameter specifies the desired event notification action. + * Valid notification actions include: + * NV906F_CTRL_SET_EVENT_NOTIFICATION_ACTION_DISABLE + * This action disables event notification for the specified + * event for the associated channel object. + * NV906F_CTRL_SET_EVENT_NOTIFICATION_ACTION_SINGLE + * This action enables single-shot event notification for the + * specified event for the associated channel object. + * NV906F_CTRL_SET_EVENT_NOTIFICATION_ACTION_REPEAT + * This action enables repeated event notification for the specified + * event for the associated channel object. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV906F_CTRL_CMD_EVENT_SET_NOTIFICATION (0x906f0203) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_EVENT_INTERFACE_ID << 8) | NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS { + NvU32 event; + NvU32 action; +} NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NV906F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NV906F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001) +#define NV906F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002) + +/* + * NV906F_CTRL_CMD_GET_DEFER_RC_STATE + * + * If SM Debugger is attached then on a MMU fault, RM defers the RC error + * recovery and keeps a flag indicating that RC is deferred. This command + * checks whether or not deferred RC is pending in RM for the associated + * channel. + * + * bDeferRCPending + * The output are TRUE and FALSE. + * + * Possible status values returned are: + * NV_OK + */ +#define NV906F_CTRL_CMD_GET_DEFER_RC_STATE (0x906f0105) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV906F_CTRL_CMD_GET_DEFER_RC_STATE_PARAMS_MESSAGE_ID" */ + +#define NV906F_CTRL_CMD_GET_DEFER_RC_STATE_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV906F_CTRL_CMD_GET_DEFER_RC_STATE_PARAMS { + NvBool bDeferRCPending; +} NV906F_CTRL_CMD_GET_DEFER_RC_STATE_PARAMS; + +#define NV906F_CTRL_CMD_GET_MMU_FAULT_INFO (0x906f0106) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */ + +/* + * Shader types supported by MMU fault info + * The types before compute shader refer to NV9097_SET_PIPELINE_SHADER_TYPE + */ +#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_VERTEX 0x00000001 +#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_TESSELLATION 0x00000003 +#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_GEOMETRY 0x00000004 +#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_PIXEL 0x00000005 +#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_COMPUTE 0x00000006 +#define NV906F_CTRL_MMU_FAULT_SHADER_TYPES 7 + +/* + * NV906F_CTRL_CMD_GET_MMU_FAULT_INFO + * + * This command returns MMU fault information for a given channel. The MMU + * fault information will be cleared once this command is executed. + * + * addrHi - [out] + * Upper 32 bits of faulting address + * addrLo [out] + * Lower 32 bits of faulting address + * faultType [out] + * MMU fault type. Please see NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE_* in + * dev_fifo.h for details about MMU fault type. + * faultString [out] + * String indicating the MMU fault type + * shaderProgramVA [out] + * an array of shader program virtual addresses to indicate faulted shaders in the pipeline + * + * Possible status values returned are: + * NV_OK + */ +#define NV906F_CTRL_MMU_FAULT_STRING_LEN 32 +#define NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS { + NvU32 addrHi; + NvU32 addrLo; + NvU32 faultType; + char faultString[NV906F_CTRL_MMU_FAULT_STRING_LEN]; + NV_DECLARE_ALIGNED(NvU64 shaderProgramVA[NV906F_CTRL_MMU_FAULT_SHADER_TYPES], 8); +} NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS; + + +/* _ctrl906f.h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl9072.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl9072.h new file mode 100644 index 0000000..8c3cceb --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl9072.h @@ -0,0 +1,86 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl9072.finn +// + +#include "ctrl/ctrlxxxx.h" +#define NV9072_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0x9072, NV9072_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NV9072_CTRL_RESERVED (0x00) +#define NV9072_CTRL_DISP_SW (0x01) + + +/* + * NV9072_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV9072_CTRL_CMD_NULL (0x90720000) /* finn: Evaluated from "(FINN_GF100_DISP_SW_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV9072_CTRL_CMD_NOTIFY_ON_VBLANK + * + * This command implements an out-of-band version of the + * GF100_DISP_SW class's NV9072_NOTIFY_ON_VBLANK method. + * + * Parameters: + * + * data + * Valid data accepted by the NV9072_NOTIFY_ON_VBLANK method. + * bHeadDisabled + * Specifies whether head is active while adding vblank + * callback. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ +#define NV9072_CTRL_CMD_NOTIFY_ON_VBLANK (0x90720101) /* finn: Evaluated from "(FINN_GF100_DISP_SW_DISP_SW_INTERFACE_ID << 8) | NV9072_CTRL_CMD_NOTIFY_ON_VBLANK_PARAMS_MESSAGE_ID" */ + +#define NV9072_CTRL_CMD_NOTIFY_ON_VBLANK_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV9072_CTRL_CMD_NOTIFY_ON_VBLANK_PARAMS { + NvU32 data; + NvBool bHeadDisabled; +} NV9072_CTRL_CMD_NOTIFY_ON_VBLANK_PARAMS; + +/* _ctrl9072.h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl9074.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl9074.h new file mode 100644 index 0000000..47b8d2f --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl9074.h @@ -0,0 +1,148 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl9074.finn +// + +#include "ctrl/ctrlxxxx.h" +#define NV9074_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x9074, NV9074_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NV9074_CTRL_RESERVED (0x00) +#define NV9074_CTRL_SEM (0x01) + +/* + * NV9074_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV9074_CTRL_CMD_NULL (0x90740000) /* finn: Evaluated from "(FINN_GF100_TIMED_SEMAPHORE_SW_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV9074_CTRL_CMD_FLUSH + * + * This command is intended to aid in idling/flushing a channel containing + * methods invoked against a specific NV9074 object. + * + * This control manipulates an NV9074 object's "flushing" state. + * + * Typical usage is: + * NvRmControl(NV9074_CTRL_CMD_FLUSH, {TRUE, flushDelay}); + * NvRmIdleChannel(channel_containing_the_9074_object); + * NvRmControl(NV9074_CTRL_CMD_FLUSH, {FALSE, 0}); + * + * When an NV9074 object is placed into the flushing state, a snaphot of the + * current timer value is taken, and "maxFlushTime" is added to this. This + * value is the "flush limit timestamp". Any previously or newly invoked + * NV9074_SEMAPHORE_SCHED methods and NV9074_CTRL_CMD_RELEASE requests that + * specify a release timestamp at or after this "flush limit timestamp" will + * immediately release the specified semaphore, without waiting for the + * specified timestamp, and write a DONE_FORCED value to the specified notifier. + */ +#define NV9074_CTRL_CMD_FLUSH (0x90740101) /* finn: Evaluated from "(FINN_GF100_TIMED_SEMAPHORE_SW_SEM_INTERFACE_ID << 8) | NV9074_CTRL_CMD_FLUSH_PARAMS_MESSAGE_ID" */ + +#define NV9074_CTRL_CMD_FLUSH_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV9074_CTRL_CMD_FLUSH_PARAMS { + NvU32 isFlushing; + NV_DECLARE_ALIGNED(NvU64 maxFlushTime, 8); +} NV9074_CTRL_CMD_FLUSH_PARAMS; + +/* + * NV9074_CTRL_CMD_GET_TIME + * + * Retrieve the current time value. + */ +#define NV9074_CTRL_CMD_GET_TIME (0x90740102) /* finn: Evaluated from "(FINN_GF100_TIMED_SEMAPHORE_SW_SEM_INTERFACE_ID << 8) | NV9074_CTRL_CMD_GET_TIME_PARAMS_MESSAGE_ID" */ + +#define NV9074_CTRL_CMD_GET_TIME_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV9074_CTRL_CMD_GET_TIME_PARAMS { + NV_DECLARE_ALIGNED(NvU64 currentTime, 8); +} NV9074_CTRL_CMD_GET_TIME_PARAMS; + +/* + * NV9074_CTRL_CMD_RELEASE + * + * This command adds a timed semaphore release request. When the desired time is + * reached, the semaphore is written with the release value, the notifier is + * filled with status and timestamp, and optionally an event is sent to all the + * client waiting on it. + * + * notifierGPUVA + * This parameter specifies the GPU VA of the notifier to receive the status + * for this particular release. + * + * semaphoreGPUVA + * This parameter specifies the GPU VA of the semaphore to release. + * + * waitTimestamp + * This parameter specifies the timestamp at which to release the semaphore. + * + * releaseValue + * This parameter specifies the semaphore value to release. + * + * releaseFlags + * This parameter specifies the flags: + * _NOTIFY wake client or not. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ADDRESS + * NV_ERR_INVALID_EVENT + * NV_ERR_INVALID_STATE + * + */ +#define NV9074_CTRL_CMD_RELEASE (0x90740103) /* finn: Evaluated from "(FINN_GF100_TIMED_SEMAPHORE_SW_SEM_INTERFACE_ID << 8) | NV9074_CTRL_CMD_RELEASE_PARAMS_MESSAGE_ID" */ + +#define NV9074_CTRL_CMD_RELEASE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV9074_CTRL_CMD_RELEASE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 notifierGPUVA, 8); + NV_DECLARE_ALIGNED(NvU64 semaphoreGPUVA, 8); + NV_DECLARE_ALIGNED(NvU64 waitTimestamp, 8); + NvU32 releaseValue; + NvU32 releaseFlags; +} NV9074_CTRL_CMD_RELEASE_PARAMS; + +#define NV9074_CTRL_CMD_RELEASE_FLAGS +#define NV9074_CTRL_CMD_RELEASE_FLAGS_NOTIFY 1:0 +#define NV9074_CTRL_CMD_RELEASE_FLAGS_NOTIFY_WRITE_ONLY (0x00000000) +#define NV9074_CTRL_CMD_RELEASE_FLAGS_NOTIFY_WRITE_THEN_AWAKEN (0x00000001) + +/* _ctrl9074.h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl9096.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl9096.h new file mode 100644 index 0000000..4aaca21 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl9096.h @@ -0,0 +1,444 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl9096.finn +// + +#include "ctrl/ctrlxxxx.h" +#define NV9096_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0x9096, NV9096_CTRL_##cat, idx) + +/* NV9096 command categories (6bits) */ +#define NV9096_CTRL_RESERVED (0x00U) +#define NV9096_CTRL_ZBC (0x01U) + + +/* + * NV9096_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV9096_CTRL_CMD_NULL (0x90960000U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* + * NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_ + * These are various possible CtFormats which + * the Client passes down to RM to set in the DS + * Color Table. + */ + + + +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_INVALID 0x00000000U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_ZERO 0x00000001U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_UNORM_ONE 0x00000002U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_RF32_GF32_BF32_AF32 0x00000004U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_R16_G16_B16_A16 0x00000008U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_RN16_GN16_BN16_AN16 0x0000000cU +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_RS16_GS16_BS16_AS16 0x00000010U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_RU16_GU16_BU16_AU16 0x00000014U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_RF16_GF16_BF16_AF16 0x00000016U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_A8R8G8B8 0x00000018U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_A8RL8GL8BL8 0x0000001cU +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_A2B10G10R10 0x00000020U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_AU2BU10GU10RU10 0x00000024U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_A8B8G8R8 0x00000028U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_A8BL8GL8RL8 0x0000002cU +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_AN8BN8GN8RN8 0x00000030U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_AS8BS8GS8RS8 0x00000034U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_AU8BU8GU8RU8 0x00000038U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_A2R10G10B10 0x0000003cU +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_BF10GF11RF11 0x00000040U + +/* + * NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR + * + * This command attempts to add a new entry to Color ZBC Tables. + * + * colorFB + * This field sets the raw framebuffer values for the ZBC table entries. Prior to + * GA10x, these values are written into the "L2" table. + * From GA10x and later, these values are written in "CROP" table. + * colorDS + * This field sets format-independent values for ZBC table entries. Prior to GA10X, + * these values are written in the "DS" table and matched with the format-independent + * clear color sent in the 3D class. These values are ignored on GA10X and later + * format + * This field specifies color format for ZBC table entries and should be one of the + * NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT* enums. Prior to GA10X, these values + * are written in the format field of the hardware ZBC table entry and are matched + * against the color format sent in the 3D class. These values are ignored on GA10X and later. + * bSkipL2Table + * This parameter specifies if the L2 ZBC table should be updated or not. If + * this parameter is set to a non-zero value, the L2 ZBC table will not be + * updated. If this parameter is set to 0, the L2 ZBC table will be updated. This + * parameter will skip programming DS table values in Pre-GA10x. From GA10x and later + * this parameter will skip programming CROP table entries. + * Note: This parameter will only be supported in verification platforms. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INSUFFICIENT_RESOURCES + */ +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR (0x90960101U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_MESSAGE_ID" */ + +#define NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE 4U +#define NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS { + NvU32 colorFB[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 colorDS[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 format; + NvBool bSkipL2Table; +} NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS; + + +/* + * NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR_FMT_VAL + * These are various possible formats which the Client passes down to RM to set in the ZBC clear + * Table. + * + * Though the "Depth" data written in both the DS as well as L2 Version of the + * depth table are of (only available!) FP32 Format. Still the format + * support is currently given with _CTRL_CMD_SET_ZBC_DEPTH_CLEAR as this format will + * be used later on to disable/remove an entry from the table. + * In future this field is going to be significant for + * "Depth" entries too. + */ + +#define NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR_FMT_VAL_INVALID 0x00000000U +// Fix me: Fix the name to FMT_VAL_FP32 +#define NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR_FMT_FP32 0x00000001U + +/* + * NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR + * + * This command attempts to add a new entry to Depth ZBC Tables. + * + * depth + * This field specifies the ZBC depth clear value to be set. + * format + * This field specifies the Depth format for the data send in by the client. + * bSkipL2Table + * This parameter specifies if the L2 ZBC table should be updated or not. If + * this parameter is set to a non-zero value, the L2 ZBC table will not be + * updated. If this parameter is set to 0, the L2 ZBC table will be updated. + * Note: This parameter will only be supported in verification platforms. + * + + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INSUFFICIENT_RESOURCES + */ +#define NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR (0x90960102U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_MESSAGE_ID" */ + +#define NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS { + NvU32 depth; + NvU32 format; + NvBool bSkipL2Table; +} NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS; + +/* + * NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE + * + * + * This command is used to get the ZBC Clear Color/Depth/Stencil table data i.e. color + * values and the status "Use-satatus" of each value in the table from RM. + * + * colorFB + * This value returns raw framebuffer values for color ZBC table entries. Pre-GA10x, these values + * are taken from the "L2" table. From GA10x+, these values are taken from CROP table. This value is + * set only when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_COLOR" + * colorDS + * Pre-GA10x, returns the DS color value set for ZBC. From GA10x+, returns zeroes since this format is + * deprecated in HW. This value is set only when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_COLOR" + * depth + * This field returns the ZBC depth clear value set, when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_DEPTH". + * stencil + * This field returns the ZBC stencil clear value set, when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_STENCIL" + * format + * This field returns the format of color, depth, or stencil ZBC table entries, using the + * NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT, + * NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR_FMT, + * NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR_FMT* enums depending on the table identified by valType. + * On GA10X and later, color ZBC table entries do not have a format in hardware and this query + * returns a format of "INVALID". + * valType + * This filed specifies the type of the Table data to be fetched. + * Possible Types are : + * NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_COLOR + * NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_DEPTH + * NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_STENCIL + * indexUsed + * This boolean parameter indicates if a particular index of the table is valid or not. + * + * Note: The following parameters are deprecated after Tegra interface is also changed. Clients need + * to use NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_SIZE to query the (start, end) indexes of respective ZBC tables + * + * indexSize + * This parameter is used to fetch the table size when "valType" parameter + * is specified as " 0 ".(INVALID TYPE). It is also used to pass in the + * index of the ZBC table for which we want the COLOR/DEPTH info. + * indexStart + * This parameter is used to return the valid starting index of ZBC table, when + * "valType" parameter is specified as "INVALID_TYPE". It will also be used + * as input index to query the ZBC table for COLOR/QUERY/STENCIL Info. + * indexEnd + * This parameter is used to return the valid ending index of ZBC table, when + * "valType" parameter is specified as "INVALID_TYPE". + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE (0x90960103U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_MESSAGE_ID" */ + +#define NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_INVALID 0U +#define NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_COLOR 1U +#define NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_DEPTH 2U +#define NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_STENCIL 3U +#define NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS { + struct { + NvU32 colorFB[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 colorDS[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 depth; + NvU32 stencil; + } value; + NvU32 indexSize; + NvU32 indexStart; + NvU32 indexEnd; + NvU32 indexUsed; /* TODO: Change to NvBool, need to fix the tegra interface too */ + NvU32 format; + NvU32 valType; +} NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS; + +/* + * Note: This ctrl call is deprecated. To program ZBC table entries, please use + * NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR + * NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR + * NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR + * which will update a single entry in single table at a time. + * + * + * NV9096_CTRL_CMD_SET_ZBC_CLEAR_TABLE + * + * This command is used to set the ZBC Clear Color/Depth/Stencil table data at a specified + * index. The parameters to this command are described below. + * + * colorFB + * This array field specifies the L2 color value to be written to the ZBC table. + * colorDS + * This array field specifies the DS color value to be written to the ZBC table. + * colorFormat + * This field specifies the ZBC color format to be set. This field must be set + * to one of the valid NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL* defines. + * depth + * This field specifies the ZBC depth clear value to be set. + * depthFormat + * This field specifies the ZBC depth format to be set. This field must be set + * to one of the valid NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR_FMT_VAL* defines. + * stencil + * This field specifies the ZBC stencil clear value to be set. + * stencilFormat + * This field specifies the ZBC stencil format to be set. This field must be set + * to one of the valid NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR_FMT_VAL* defines. + * index + * This field specifies the index at which the color/depth data is to be + * written into the ZBC table. Legal values for this field must lie between + * 1 and the value returned in the indexSize parameter of the + * NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE control call when called with the + * parameter valType set to NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_INVALID. + * bSkipL2Table + * This parameter specifies if the L2 ZBC table should be updated or not. If + * this parameter is set to a non-zero value, the L2 ZBC table will not be + * updated. If this parameter is set to 0, the L2 ZBC table will be updated. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_RESOURCES + */ +#define NV9096_CTRL_CMD_SET_ZBC_CLEAR_TABLE (0x90960104U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_SET_ZBC_CLEAR_TABLE_PARAMS_MESSAGE_ID" */ + +#define NV9096_CTRL_SET_ZBC_CLEAR_TABLE_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV9096_CTRL_SET_ZBC_CLEAR_TABLE_PARAMS { + NvU32 colorFB[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 colorDS[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 colorFormat; + NvU32 depth; + NvU32 depthFormat; + NvU32 stencil; + NvU32 stencilFormat; + NvU32 index; + NvBool bSkipL2Table; +} NV9096_CTRL_SET_ZBC_CLEAR_TABLE_PARAMS; + +/* + * NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR_FMT_VAL_ + * These are various possible Formats which the Client passes down to RM to set in the + * ZBC clear(DSS) Table. + */ + +#define NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR_FMT_VAL_INVALID 0x00000000U +// Fix me: Change it to CLEAR_FMT_VAL_U8 +#define NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR_FMT_U8 0x00000001U + +/* + * NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR + * + * This command attempts to add a new entry to Stencil ZBC Tables. + * + * stencil + * This field specifies the ZBC stencil clear value to be set. + * format + * This field specifies the stencil format for the data send in by the client. + * bSkipL2Table + * This parameter specifies if the L2 ZBC table should be updated or not. If + * this parameter is set to a non-zero value, the L2 ZBC table will not be + * updated. If this parameter is set to 0, the L2 ZBC table will be updated. + * Note: This parameter will only be supported in verification platforms. + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INSUFFICIENT_RESOURCES + */ +#define NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR (0x90960105U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_MESSAGE_ID" */ + +#define NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS { + NvU32 stencil; + NvU32 format; + NvBool bSkipL2Table; +} NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS; + +/* + * NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_SIZE + * This command returns the range of valid indices in the color, depth, or stencil ZBC tables. + * + * indexStart + * This parameter is used to return the first valid index in the color, depth, or stencil ZBC table, + * depending on the value passed in the tableType + * indexEnd + * This parameter is used to return the last valid index in the color, depth, or stencil ZBC table, + * depending on the value passed in the tableType + * tableType + * This field specifies the type of the Table data to be fetched. + * Possible Types are : + * NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR + * NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_DEPTH + * NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_STENCIL + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +typedef enum NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE { + NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_INVALID = 0, + NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR = 1, + NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_DEPTH = 2, + NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_STENCIL = 3, + NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT = 4, +} NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE; + +#define NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_SIZE (0x90960106U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS { + NvU32 indexStart; + NvU32 indexEnd; + NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE tableType; +} NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS; + +/* + * NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_ENTRY + * This command returns the ZBC entry stored in the color, depth or stencil ZBC tables + * + * colorFB[out] + * This value returns raw framebuffer values for color ZBC table entries. Pre-GA10x, these values + * are taken from the "L2" table. From GA10x+, these values are taken from CROP table. This value is + * set only when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR" + * colorDS[out] + * Pre-GA10x, returns the DS color value set for ZBC. From GA10x+, returns zeroes since this format is + * deprecated in HW. This value is set only when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR" + * depth[out] + * This field specifies the ZBC depth clear value set, when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_DEPTH". + * stencil[out] + * This field specifies the ZBC stencil clear value set, when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_STENCIL" + * format + * This field returns the format of color, depth, or stencil ZBC table entries, using the + * NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL*, + * NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR_FMT*, + * NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR_FMT* enums depending on the table identified by valType. + * On GA10X and later, color ZBC table entries do not have a format in hardware and this query + * returns a format of "INVALID". + * index[in] + * This field specifies table index for which the ZBC entry information needs to be fetched. + * bIndexValid[out] + * This field specifies whether the entry is valid or not. + * tableType[in] + * This field specifies the type of the Table data to be fetched. + * Possible Types are : + * NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR + * NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_DEPTH + * NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_STENCIL + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_ENTRY (0x90960107U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_MESSAGE_ID" */ + +#define NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS { + struct { + NvU32 colorFB[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 colorDS[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 depth; + NvU32 stencil; + } value; + NvU32 format; + NvU32 index; + NvBool bIndexValid; + NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE tableType; +} NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS; + +/* _ctrl9096_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90cc.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90cc.h new file mode 100644 index 0000000..fa02e75 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90cc.h @@ -0,0 +1,455 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90cc.finn +// + + + + +#include "ctrl/ctrlxxxx.h" +#include "ctrl90cc/ctrl90ccbase.h" + +#include "ctrl90cc/ctrl90cchwpm.h" + + +#include "ctrl90cc/ctrl90ccpower.h" + + +/* + * NV90CC_CTRL_CMD_PROFILER_RESERVE_HWPM + * + * This command is deprecated; please use NV90CC_CTRL_CMD_HWPM_RESERVE. + * + * This command attempts to reserve the perfmon for use by the calling client. + * If this object was allocated as a child of a subdevice, then the + * reservation will be global among all contexts on that subdevice. If this + * object was allocated as a child of a channel group or a channel, then the + * reservation will only be for the hardware context of that channel group or + * channel. + * + * If the global reservation is held on a subdevice by another client, then + * this command will fail, regardless of the parent class. + * + * If one or more per-context reservations are held by other clients, then + * this command will fail if the parent object is a subdevice or another + * client already holds the perfmon reservation for the parent context. + * + * This command will return NV_ERR_STATE_IN_USE for all of the failure + * cases described above. A return status of NV_OK guarantees + * that the client holds the perfmon reservation of the appropriate scope. + * + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_STATE_IN_USE + */ +#define NV90CC_CTRL_CMD_PROFILER_RESERVE_HWPM NV90CC_CTRL_CMD_HWPM_RESERVE + +/* + * NV90CC_CTRL_CMD_PROFILER_RELEASE_HWPM + * + * This command is deprecated; please use NV90CC_CTRL_CMD_HWPM_RELEASE. + * + * This command releases an existing reservation of the perfmon for the + * calling client. If the calling client does not currently have the perfmon + * reservation as acquired by NV90CC_CTRL_CMD_PROFILER_RESERVE_HWPM, this + * command will return NV_ERR_INVALID_REQUEST. + * + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + */ +#define NV90CC_CTRL_CMD_PROFILER_RELEASE_HWPM NV90CC_CTRL_CMD_HWPM_RELEASE + + + +/* + * NV90CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS + * + * This command is deprecated; please use + * NV90CC_CTRL_CMD_POWER_REQUEST_POWER_FEATURES. + * + * This command attempts to enable or disable various clock-gating features of + * the GPU on behalf of the profiler. If this command is unable to set the + * clock-gating feature state of any of the requested features, this command + * will fail and none of the requested features will be modified. If this + * command fails because one or more clock-gating feature requests were + * rejected, it will return NV_ERR_STATE_IN_USE in the globalStatus + * parameter and the fields in the statusMask parameter for the features for + * which the requests were rejected will have the value + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_REJECTED. + * If a given feature is not supported on the GPU, the field for that clock- + * gating feature will have the value + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_NOT_SUPPORTED in the + * statusMask parameter, but this condition by itself will not cause the + * command to fail. Even if this command fails, the field for clock-gating + * features which would have successfully changed will have the value + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_FULFILLED in the statusMask + * parameter. + * + * Each of the clock-gating features is reference-counted individually, so + * that multiple GF100_PROFILER objects may request and rely on the same + * settings for the features simultaneously. Each clock-gating feature is + * locked to the requested state until the GF100_PROFILER object is freed or + * the NV90CC_CTRL_CMD_PROFILER_RELEASE_CG_CONTROLS command is called for that + * feature. + * + * Currently, only GF100_PROFILER requests for power features using this + * command are reference counted. Changes to the power feature settings made + * either by other control commands or the RM itself may interfere with the + * settings requested by GF100_PROFILER instances. + * + * This command will always return NV_OK when given valid + * parameters. If there is any other failure that prevents the clock-gating + * features from being set appropriately, the globalStatus parameter will + * indicate this and the statusMask parameter will indicate which clock-gating + * feature requests failed and why. + * + * controlMask + * This parameter indicates which clock-gating features the request should + * apply to. This parameter has the following fields: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG + * The value of this field indicates whether this request should apply + * to engine-level clock-gating of the GR engine. Valid values for + * this field are: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_IGNORE + * This value indicates that the GR engine-level clock-gating + * should be ignored. This will not affect the reference count for + * this feature. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_DISABLE + * This value indicates that the GR engine-level clock-gating + * should be disabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_ENABLE + * This value indicates that the GR engine-level clock-gating + * should be enabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG + * The value of this field indicates whether this request should apply + * to block-level clock-gating. Valid values for this field are: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_IGNORE + * This value indicates that block-level clock-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_DISABLE + * This value indicates that block-level clock-gating should be + * disabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_ENABLE + * This value indicates that block-level clock-gating should be + * enabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG + * The value of this field indicates whether this request should apply + * to second-level clock-gating. Valid values for this field are: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_IGNORE + * This value indicates that second-level clock-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_DISABLE + * This value indicates that second-level clock-gating should be + * disabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_ENABLE + * This value indicates that second-level clock-gating should be + * enabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG + * The value of this field indicates whether this request should apply + * to GR engine-level power-gating. Valid values for this field are: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_IGNORE + * This value indicates that engine-level power-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_DISABLE + * This value indicates that engine-level power-gating should be + * disabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_ENABLE + * This value indicates that engine-level power-gating should be + * enabled. + * Note that this field is only temporary to allow reference counting + * restricted to GF100_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN + * The value of this field indicates whether this request should apply + * to SM idle slowdown. Valid values for this field are: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_IGNORE + * This value indicates that SM idle slowdown should be ignored. + * This will not affect the reference count for this feature. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_DISABLE + * This value indicates that SM idle slowdown should be disabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_ENABLE + * This value indicates that SM idle slowdown should be enabled. + * Note that this field is only temporary to allow reference counting + * restricted to GF100_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT + * The value of this field indicates whether this request should apply + * to VAT. Valid values for this field are: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_IGNORE + * This value indicates that VAT should be ignored. + * This will not affect the reference count for this feature. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_DISABLE + * This value indicates that VAT should be disabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_ENABLE + * This value indicates that VAT should be enabled. + * Note that this field is only temporary to allow reference counting + * restricted to GF100_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * globalStatus + * This parameter returns the overall status of the requests for all + * clock-gating controls. If the value of this parameter is not + * NV_OK, none of the clock-gating controls will be set as + * requested. Possible values for this parameter are: + * NV_OK + * This value indicates that all of the clock-gating control requests + * were either fulfilled or not supported on the hardware. + * NV_ERR_INVALID_REQUEST + * This value indicates that at least one of the clock-gating control + * requests were invalid given the GF100_PROFILER instance's + * outstanding requests. + * NV_ERR_STATE_IN_USE + * This value indicates that at least one of the clock-gating controls + * has already been locked to a conflicting state by another + * GF100_PROFILER instance or the RM itself. + * statusMask + * This parameter returns the status of the request to set each clock- + * gating control specified by the controlMask parameter. The fields are + * identical to those of the controlMask parameter. For each field for + * which the corresponding field in the controlMask parameter has the + * value NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_IGNORE, the value is + * undefined. For each field for which the corresponding field in the + * controlMask parameter has the value + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST, the value will be + * one of the following: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_FULFILLED + * This value indicates that the clock-gating feature corresponding to + * the field in question was enabled or disabled according to the + * controlMask parameter, and the reference count for the feature was + * incremented accordingly. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_REJECTED + * This value indicates that the clock-gating feature corresponding to + * the field in question was not set to the expected state according + * to the controlMask parameter because another conflicting request is + * currently outstanding for the clock-gating feature. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_FAILED + * This value indicates that the clock-gating feature corresponding to + * the field in question was not set to the expected state according + * to the controlMask parameter because the attempt to do so failed + * with an error other than a conflicting request. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_NOT_SUPPORTED + * This value indicates that the clock-gating feature corresponding to + * the field in question is not supported on this GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV90CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES + +typedef NV90CC_CTRL_POWER_REQUEST_FEATURES_PARAMS NV90CC_CTRL_PROFILER_REQUEST_CG_CONTROLS_PARAMS; + +/* valid fields for the controlMask and statusMask parameters */ +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG 1:0 +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG 3:2 +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG 5:4 + +/* + * The following are temporary fields for the controlMask and statusMask + * parameters. They are required to reference count their respective features + * until the existing RM controls can be safely updated, and the definitions + * for these features will be removed soon after that. + */ +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG 7:6 +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN 9:8 +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT 11:10 + +/* valid values for fields in the controlMask parameter */ +#define NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE (0x00000000) +#define NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE (0x00000001) +#define NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE (0x00000002) + +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_IGNORE NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_DISABLE NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_ENABLE NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_IGNORE NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_DISABLE NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_ENABLE NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_IGNORE NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_DISABLE NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_ENABLE NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_IGNORE NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_DISABLE NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_ENABLE NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_IGNORE NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_DISABLE NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_ENABLE NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_IGNORE NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_DISABLE NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_ENABLE NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE +/* possible values for fields in the statusMask parameter */ +#define NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED (0x00000000) +#define NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED (0x00000001) +#define NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED (0x00000002) +#define NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED (0x00000003) + +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_FULFILLED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_REJECTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_NOT_SUPPORTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_FAILED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_FULFILLED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_REJECTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_NOT_SUPPORTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_FAILED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_FULFILLED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_REJECTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_NOT_SUPPORTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_FAILED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_FULFILLED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_REJECTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_NOT_SUPPORTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_FAILED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_FULFILLED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_REJECTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_NOT_SUPPORTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_FAILED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_FULFILLED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_REJECTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_NOT_SUPPORTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_FAILED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED + +/* utility masks for the controlMask parameter for all controls */ +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL \ + DRF_SHIFTMASK(NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG) | \ + DRF_SHIFTMASK(NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG) | \ + DRF_SHIFTMASK(NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG) | \ + DRF_SHIFTMASK(NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG) | \ + DRF_SHIFTMASK(NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN) | \ + DRF_SHIFTMASK(NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT) +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_IGNORE \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _IGNORE) +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_DISABLE \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _DISABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _DISABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _DISABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _DISABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _DISABLE)| \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _DISABLE) +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_ENABLE \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _ENABLE) + +/* + * NV90CC_CTRL_CMD_PROFILER_RELEASE_CG_CONTROLS + * + * This command is deprecated; please us + * NV90CC_CTRL_CMD_POWER_RELEASE_FEATURES. + * + * This command releases the GF100_PROFILER's request for the given clock- + * gating features that was previously created by the + * NV90CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS command. If the GF100_PROFILER + * object does not have an outstanding request to one or more of the given + * clock-gating features, those features will be ignored while the other + * feature requests will be released. + * + * After calling this command, the calling client may not rely on the current + * value of any of the released clock-gating features to remain, even if + * several identical requests for the given clock-gating features were made + * using NV90CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS. The RM only reference- + * counts the settings requested by GF100_PROFILER instances - it does not + * reference-count multiple identical requests made using the same + * GF100_PROFILER instance. + * + * All outstanding requests made using this GF100_PROFILER object are + * implicitly released when the GF100_PROFILER is freed. + * + * controlMask + * This parameter indicates which clock-gating features the RM should + * release the GF100_PROFILER's reference to. See + * NV90CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS for valid fields. Valid + * values for each field are: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_IGNORE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_IGNORE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_IGNORE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_IGNORE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_IGNORE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_IGNORE + * This value indicates that the clock-gating feature associated with + * the field should not be released, even if the GF100_PROFILER has an + * outstanding request for it. This will not affect the reference + * count for the feature. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_RELEASE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_RELEASE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_RELEASE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_RELEASE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_RELEASE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_RELEASE + * This value indicates that the GF100_PROFILER's outstanding request + * for the clock-gating feature associated with the field should be + * released. This will decrement the reference count for the feature + * if the GF100_PROFILER has an outstanding request for it. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV90CC_CTRL_CMD_PROFILER_RELEASE_CG_CONTROLS NV90CC_CTRL_CMD_POWER_RELEASE_FEATURES + +typedef NV90CC_CTRL_POWER_RELEASE_FEATURES_PARAMS NV90CC_CTRL_PROFILER_RELEASE_CG_CONTROLS_PARAMS; + +/* + * valid values for the controlMask parameter in addition to + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_IGNORE + */ +#define NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE (0x00000003) + +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_RELEASE NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_RELEASE NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_RELEASE NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_RELEASE NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_RELEASE NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_RELEASE NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE + +/* utility mask for the controlMask parameter for all fields */ +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_RELEASE \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _RELEASE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _RELEASE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _RELEASE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _RELEASE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _RELEASE)| \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _RELEASE) + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90cc/ctrl90ccbase.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90cc/ctrl90ccbase.h new file mode 100644 index 0000000..707ec03 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90cc/ctrl90ccbase.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90cc/ctrl90ccbase.finn +// + +#include "ctrl/ctrlxxxx.h" +/* GF100_PROFILER control commands and parameters */ + +#define NV90CC_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x90CC, NV90CC_CTRL_##cat, idx) + +/* GF100_PROFILER command categories (6 bits) */ +#define NV90CC_CTRL_RESERVED (0x00) +#define NV90CC_CTRL_HWPM (0x01) + + +#define NV90CC_CTRL_POWER (0x03) + +/* + * NV90CC_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV90CC_CTRL_CMD_NULL (0x90cc0000) /* finn: Evaluated from "(FINN_GF100_PROFILER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrl90ccbase_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90cc/ctrl90cchwpm.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90cc/ctrl90cchwpm.h new file mode 100644 index 0000000..b1013f2 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90cc/ctrl90cchwpm.h @@ -0,0 +1,135 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90cc/ctrl90cchwpm.finn +// + +#include "ctrl/ctrl90cc/ctrl90ccbase.h" + +/* GF100_PROFILER HWPM control commands and parameters */ + +/* + * NV90CC_CTRL_CMD_HWPM_RESERVE + * + * This command attempts to reserve the perfmon for use by the calling client. + * If this object was allocated as a child of a subdevice, then the + * reservation will be global among all contexts on that subdevice. If this + * object was allocated as a child of a channel group or a channel, then the + * reservation will only be for the hardware context of that channel group or + * channel. + * + * If the global reservation is held on a subdevice by another client, then + * this command will fail, regardless of the parent class. + * + * If one or more per-context reservations are held by other clients, then + * this command will fail if the parent object is a subdevice or another + * client already holds the perfmon reservation for the parent context. + * + * This command will return NV_ERR_STATE_IN_USE for all of the failure + * cases described above. A return status of NV_OK guarantees + * that the client holds the perfmon reservation of the appropriate scope. + * + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_STATE_IN_USE + */ +#define NV90CC_CTRL_CMD_HWPM_RESERVE (0x90cc0101) /* finn: Evaluated from "(FINN_GF100_PROFILER_HWPM_INTERFACE_ID << 8) | 0x1" */ + +/* + * NV90CC_CTRL_CMD_HWPM_RELEASE + * + * This command releases an existing reservation of the perfmon for the + * calling client. If the calling client does not currently have the perfmon + * reservation as acquired by NV90CC_CTRL_CMD_PROFILER_RESERVE_HWPM, this + * command will return NV_ERR_INVALID_REQUEST. + * + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + */ +#define NV90CC_CTRL_CMD_HWPM_RELEASE (0x90cc0102) /* finn: Evaluated from "(FINN_GF100_PROFILER_HWPM_INTERFACE_ID << 8) | 0x2" */ + +/* + * NV90CC_CTRL_CMD_HWPM_GET_RESERVATION_INFO + * + * This command returns information about any outstanding perfmon + * reservations. If this object was allocated as a child of a subdevice, then + * this command will return information about all reservations on the + * subdevice (global or per-context). If this object was allocated as a child + * of a channel group or channel, then this command will only return + * information about the per-context reservation for that context or the + * global reservation, if one exists. + * + * reservationCount + * This parameter returns the number of outstanding perfmon reservations + * in the applicable scope. If the value of the bGlobal parameter is + * NV_TRUE, then this parameter will have a value of 1. If this object was + * allocated as a child of a channel group or channel, then this parameter + * will have a value of either 0 or 1. If this object was allocated as a + * child of a subdevice and the bGlobal parameter is NV_FALSE, then this + * parameter will return the number of per-context reservations on the + * subdevice. + * pid + * This parameter returns the PID of a process that holds a reservation in + * the applicable scope. If the value of the bGlobal parameter is NV_TRUE, + * then this parameter will be the PID of the process holding the global + * perfmon reservation on the subdevice. Otherwise, if the value of + * reservationCount is greater than 0, the value of this parameter will be + * the PID of one of the process that holds the per-context lock in the + * applicable scope. If the value of the reservationCount parameter is 0, + * the value of this parameter is undefined. + * bGlobal + * This parameter returns whether the outstanding perfmon reservation held + * by any client is global or per-context. If the value of this parameter + * is NV_TRUE, then the value of the reservationCount parameter should be 1 + * and the value of the pid parameter should be the pid of the process + * that holds the global perfmon reservation. The value of this parameter + * will be NV_FALSE when there is no global perfmon reservation. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV90CC_CTRL_CMD_HWPM_GET_RESERVATION_INFO (0x90cc0103) /* finn: Evaluated from "(FINN_GF100_PROFILER_HWPM_INTERFACE_ID << 8) | NV90CC_CTRL_HWPM_GET_RESERVATION_INFO_PARAMS_MESSAGE_ID" */ + +#define NV90CC_CTRL_HWPM_GET_RESERVATION_INFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV90CC_CTRL_HWPM_GET_RESERVATION_INFO_PARAMS { + NvU32 reservationCount; + NvU32 pid; + NvBool bGlobal; +} NV90CC_CTRL_HWPM_GET_RESERVATION_INFO_PARAMS; + + + +/* _ctrl90cchwpm_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90cc/ctrl90ccpower.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90cc/ctrl90ccpower.h new file mode 100644 index 0000000..aa25ceb --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90cc/ctrl90ccpower.h @@ -0,0 +1,403 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90cc/ctrl90ccpower.finn +// + +#include "ctrl/ctrl90cc/ctrl90ccbase.h" + +/* GF100_PROFILER GPU control commands and parameters */ +/* + * NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES + * + * This command attempts to enable or disable various clock-gating features of + * the GPU on behalf of the profiler. If this command is unable to set the + * clock-gating feature state of any of the requested features, this command + * will fail and none of the requested features will be modified. If this + * command fails because one or more clock-gating feature requests were + * rejected, it will return NV_ERR_STATE_IN_USE in the globalStatus + * parameter and the fields in the statusMask parameter for the features for + * which the requests were rejected will have the value + * NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_REJECTED. + * If a given feature is not supported on the GPU, the field for that clock- + * gating feature will have the value + * NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_NOT_SUPPORTED in the + * statusMask parameter, but this condition by itself will not cause the + * command to fail. Even if this command fails, the field for clock-gating + * features which would have successfully changed will have the value + * NV90CC_CTRL_POWER_FEATURE_MASK_*_FULFILLED in the statusMask + * parameter. + * + * Each of the clock-gating features is reference-counted individually, so + * that multiple GF100_PROFILER objects may request and rely on the same + * settings for the features simultaneously. Each clock-gating feature is + * locked to the requested state until the GF100_PROFILER object is freed or + * the NV90CC_CTRL_CMD_POWER_RELEASE_FEATURES command is called for that + * feature. + * + * Currently, only GF100_PROFILER requests for power features using this + * command are reference counted. Changes to the power feature settings made + * either by other control commands or the RM itself may interfere with the + * settings requested by GF100_PROFILER instances. + * + * This command will always return NV_OK when given valid + * parameters. If there is any other failure that prevents the clock-gating + * features from being set appropriately, the globalStatus parameter will + * indicate this and the statusMask parameter will indicate which clock-gating + * feature requests failed and why. + * + * controlMask + * This parameter indicates which clock-gating features the request should + * apply to. This parameter has the following fields: + * NV90CC_CTRL_POWER_FEATURE_MASK_ELCG + * The value of this field indicates whether this request should apply + * to engine-level clock-gating of the GR engine. Valid values for + * this field are: + * NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE + * This value indicates that the GR engine-level clock-gating + * should be ignored. This will not affect the reference count for + * this feature. + * NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_DISABLE + * This value indicates that the GR engine-level clock-gating + * should be disabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_ENABLE + * This value indicates that the GR engine-level clock-gating + * should be enabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_BLCG + * The value of this field indicates whether this request should apply + * to block-level clock-gating. Valid values for this field are: + * NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE + * This value indicates that block-level clock-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_DISABLE + * This value indicates that block-level clock-gating should be + * disabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_ENABLE + * This value indicates that block-level clock-gating should be + * enabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_SLCG + * The value of this field indicates whether this request should apply + * to second-level clock-gating. Valid values for this field are: + * NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE + * This value indicates that second-level clock-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_DISABLE + * This value indicates that second-level clock-gating should be + * disabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_ENABLE + * This value indicates that second-level clock-gating should be + * enabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_ELPG + * The value of this field indicates whether this request should apply + * to GR engine-level power-gating. Valid values for this field are: + * NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE + * This value indicates that engine-level power-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_DISABLE + * This value indicates that engine-level power-gating should be + * disabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_ENABLE + * This value indicates that engine-level power-gating should be + * enabled. + * Note that this field is only temporary to allow reference counting + * restricted to GF100_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN + * The value of this field indicates whether this request should apply + * to SM idle slowdown. Valid values for this field are: + * NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE + * This value indicates that SM idle slowdown should be ignored. + * This will not affect the reference count for this feature. + * NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_DISABLE + * This value indicates that SM idle slowdown should be disabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_ENABLE + * This value indicates that SM idle slowdown should be enabled. + * Note that this field is only temporary to allow reference counting + * restricted to GF100_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * NV90CC_CTRL_POWER_FEATURE_MASK_VAT + * The value of this field indicates whether this request should apply + * to VAT. Valid values for this field are: + * NV90CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE + * This value indicates that VAT should be ignored. + * This will not affect the reference count for this feature. + * NV90CC_CTRL_POWER_FEATURE_MASK_VAT_DISABLE + * This value indicates that VAT should be disabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_VAT_ENABLE + * This value indicates that VAT should be enabled. + * Note that this field is only temporary to allow reference counting + * restricted to GF100_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * globalStatus + * This parameter returns the overall status of the requests for all + * clock-gating controls. If the value of this parameter is not + * NV_OK, none of the clock-gating controls will be set as + * requested. Possible values for this parameter are: + * NV_OK + * This value indicates that all of the clock-gating control requests + * were either fulfilled or not supported on the hardware. + * NV_ERR_INVALID_REQUEST + * This value indicates that at least one of the clock-gating control + * requests were invalid given the GF100_PROFILER instance's + * outstanding requests. + * NV_ERR_STATE_IN_USE + * This value indicates that at least one of the clock-gating controls + * has already been locked to a conflicting state by another + * GF100_PROFILER instance or the RM itself. + * statusMask + * This parameter returns the status of the request to set each clock- + * gating control specified by the controlMask parameter. The fields are + * identical to those of the controlMask parameter. For each field for + * which the corresponding field in the controlMask parameter has the + * value NV90CC_CTRL_POWER_FEATURE_MASK_*_IGNORE, the value is + * undefined. For each field for which the corresponding field in the + * controlMask parameter has the value + * NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST, the value will be + * one of the following: + * NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_FULFILLED + * This value indicates that the clock-gating feature corresponding to + * the field in question was enabled or disabled according to the + * controlMask parameter, and the reference count for the feature was + * incremented accordingly. + * NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_REJECTED + * This value indicates that the clock-gating feature corresponding to + * the field in question was not set to the expected state according + * to the controlMask parameter because another conflicting request is + * currently outstanding for the clock-gating feature. + * NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_FAILED + * This value indicates that the clock-gating feature corresponding to + * the field in question was not set to the expected state according + * to the controlMask parameter because the attempt to do so failed + * with an error other than a conflicting request. + * NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_NOT_SUPPORTED + * This value indicates that the clock-gating feature corresponding to + * the field in question is not supported on this GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES (0x90cc0301) /* finn: Evaluated from "(FINN_GF100_PROFILER_POWER_INTERFACE_ID << 8) | NV90CC_CTRL_POWER_REQUEST_FEATURES_PARAMS_MESSAGE_ID" */ + +#define NV90CC_CTRL_POWER_REQUEST_FEATURES_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV90CC_CTRL_POWER_REQUEST_FEATURES_PARAMS { + NvU32 globalStatus; + NvU32 controlMask; + NvU32 statusMask; +} NV90CC_CTRL_POWER_REQUEST_FEATURES_PARAMS; + +/* valid fields for the controlMask and statusMask parameters */ +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG 1:0 +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG 3:2 +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG 5:4 + +/* + * The following are temporary fields for the controlMask and statusMask + * parameters. They are required to reference count their respective features + * until the existing RM controls can be safely updated, and the definitions + * for these features will be removed soon after that. + */ +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG 7:6 +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN 9:8 +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT 11:10 + +/* valid values for fields in the controlMask parameter */ +#define NV90CC_CTRL_POWER_FEATURE_IGNORE (0x00000000) +#define NV90CC_CTRL_POWER_FEATURE_DISABLE (0x00000001) +#define NV90CC_CTRL_POWER_FEATURE_ENABLE (0x00000002) + +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE NV90CC_CTRL_POWER_FEATURE_IGNORE +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_DISABLE NV90CC_CTRL_POWER_FEATURE_DISABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_ENABLE NV90CC_CTRL_POWER_FEATURE_ENABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE NV90CC_CTRL_POWER_FEATURE_IGNORE +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_DISABLE NV90CC_CTRL_POWER_FEATURE_DISABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_ENABLE NV90CC_CTRL_POWER_FEATURE_ENABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE NV90CC_CTRL_POWER_FEATURE_IGNORE +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_DISABLE NV90CC_CTRL_POWER_FEATURE_DISABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_ENABLE NV90CC_CTRL_POWER_FEATURE_ENABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE NV90CC_CTRL_POWER_FEATURE_IGNORE +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_DISABLE NV90CC_CTRL_POWER_FEATURE_DISABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_ENABLE NV90CC_CTRL_POWER_FEATURE_ENABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE NV90CC_CTRL_POWER_FEATURE_IGNORE +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_DISABLE NV90CC_CTRL_POWER_FEATURE_DISABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_ENABLE NV90CC_CTRL_POWER_FEATURE_ENABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE NV90CC_CTRL_POWER_FEATURE_IGNORE +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_DISABLE NV90CC_CTRL_POWER_FEATURE_DISABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_ENABLE NV90CC_CTRL_POWER_FEATURE_ENABLE +/* possible values for fields in the statusMask parameter */ +#define NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED (0x00000000) +#define NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED (0x00000001) +#define NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED (0x00000002) +#define NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED (0x00000003) + +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_FULFILLED NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_REJECTED NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_NOT_SUPPORTED NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_FAILED NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_FULFILLED NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_REJECTED NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_NOT_SUPPORTED NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_FAILED NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_FULFILLED NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_REJECTED NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_NOT_SUPPORTED NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_FAILED NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_FULFILLED NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_REJECTED NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_NOT_SUPPORTED NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_FAILED NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_FULFILLED NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_REJECTED NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_NOT_SUPPORTED NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_FAILED NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_FULFILLED NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_REJECTED NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_NOT_SUPPORTED NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_FAILED NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED + +/* utility masks for the controlMask parameter for all controls */ +#define NV90CC_CTRL_POWER_FEATURE_MASK_ALL \ + DRF_SHIFTMASK(NV90CC_CTRL_POWER_FEATURE_MASK_ELCG) | \ + DRF_SHIFTMASK(NV90CC_CTRL_POWER_FEATURE_MASK_BLCG) | \ + DRF_SHIFTMASK(NV90CC_CTRL_POWER_FEATURE_MASK_SLCG) | \ + DRF_SHIFTMASK(NV90CC_CTRL_POWER_FEATURE_MASK_ELPG) | \ + DRF_SHIFTMASK(NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN) | \ + DRF_SHIFTMASK(NV90CC_CTRL_POWER_FEATURE_MASK_VAT) +#define NV90CC_CTRL_POWER_FEATURE_MASK_ALL_IGNORE \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _VAT, _IGNORE) +#define NV90CC_CTRL_POWER_FEATURE_MASK_ALL_DISABLE \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _DISABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _DISABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _DISABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _DISABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _DISABLE)| \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _VAT, _DISABLE) +#define NV90CC_CTRL_POWER_FEATURE_MASK_ALL_ENABLE \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _VAT, _ENABLE) + +/* + * NV90CC_CTRL_CMD_POWER_RELEASE_FEATUERS + * + * This command releases the GF100_PROFILER's request for the given clock- + * gating features that was previously created by the + * NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES command. If the GF100_PROFILER + * object does not have an outstanding request to one or more of the given + * clock-gating features, those features will be ignored while the other + * feature requests will be released. + * + * After calling this command, the calling client may not rely on the current + * value of any of the released clock-gating features to remain, even if + * several identical requests for the given clock-gating features were made + * using NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES. The RM only reference- + * counts the settings requested by GF100_PROFILER instances - it does not + * reference-count multiple identical requests made using the same + * GF100_PROFILER instance. + * + * All outstanding requests made using this GF100_PROFILER object are + * implicitly released when the GF100_PROFILER is freed. + * + * controlMask + * This parameter indicates which clock-gating features the RM should + * release the GF100_PROFILER's reference to. See + * NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES for valid fields. Valid + * values for each field are: + * NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE + * NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE + * NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE + * NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE + * NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE + * NV90CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE + * This value indicates that the clock-gating feature associated with + * the field should not be released, even if the GF100_PROFILER has an + * outstanding request for it. This will not affect the reference + * count for the feature. + * NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_RELEASE + * NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_RELEASE + * NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_RELEASE + * NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_RELEASE + * NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_RELEASE + * NV90CC_CTRL_POWER_FEATURE_MASK_VAT_RELEASE + * This value indicates that the GF100_PROFILER's outstanding request + * for the clock-gating feature associated with the field should be + * released. This will decrement the reference count for the feature + * if the GF100_PROFILER has an outstanding request for it. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV90CC_CTRL_CMD_POWER_RELEASE_FEATURES (0x90cc0302) /* finn: Evaluated from "(FINN_GF100_PROFILER_POWER_INTERFACE_ID << 8) | NV90CC_CTRL_POWER_RELEASE_FEATURES_PARAMS_MESSAGE_ID" */ + +#define NV90CC_CTRL_POWER_RELEASE_FEATURES_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV90CC_CTRL_POWER_RELEASE_FEATURES_PARAMS { + NvU32 controlMask; +} NV90CC_CTRL_POWER_RELEASE_FEATURES_PARAMS; + +/* + * valid values for the controlMask parameter in addition to + * NV90CC_CTRL_POWER_FEATURE_MASK_*_IGNORE + */ +#define NV90CC_CTRL_POWER_FEATURE_RELEASE (0x00000003) + +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_RELEASE NV90CC_CTRL_POWER_FEATURE_RELEASE +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_RELEASE NV90CC_CTRL_POWER_FEATURE_RELEASE +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_RELEASE NV90CC_CTRL_POWER_FEATURE_RELEASE +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_RELEASE NV90CC_CTRL_POWER_FEATURE_RELEASE +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_RELEASE NV90CC_CTRL_POWER_FEATURE_RELEASE +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_RELEASE NV90CC_CTRL_POWER_FEATURE_RELEASE + + +/* _ctrl90ccpower_h_ */ + +/* utility mask for the controlMask parameter for all fields */ +#define NV90CC_CTRL_POWER_FEATURE_MASK_ALL_RELEASE \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _RELEASE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _RELEASE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _RELEASE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _RELEASE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _RELEASE)| \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _VAT, _RELEASE) diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90cd.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90cd.h new file mode 100644 index 0000000..29449ab --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90cd.h @@ -0,0 +1,174 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90cd.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV_EVENT_BUFFER control commands and parameters */ + +#define NV_EVENT_BUFFER_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x90CD, NV90CD_CTRL_##cat, idx) + +#define NV90CD_CTRL_RESERVED (0x00) +#define NV90CD_CTRL_EVENT (0x01) + +/* +* NV_EVENT_BUFFER_CTRL_CMD_NULL +* +* This command does nothing. +* This command does not take any parameters. +* +* Possible status values returned are: +* NV_OK +*/ +#define NV_EVENT_BUFFER_CTRL_CMD_NULL (0x90cd0000) /* finn: Evaluated from "(FINN_NV_EVENT_BUFFER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* +* NV_EVENT_BUFFER_CTRL_CMD_ENABLE_EVENTS +* This interface enables all the events that are associated to the event buffer +*/ +#define NV_EVENT_BUFFER_CTRL_CMD_ENABLE_EVENTS (0x90cd0101) /* finn: Evaluated from "(FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID << 8) | 0x1" */ + +#define NV_EVENT_BUFFER_FLAG 0:32 + +/* +* NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY +* This flag defines the kernel behavior when the buffer is full +* +* DEFAULT/DISABLED: By default kernel doesn't assume any policy. To enable events +* an overflow policy has to be set to retain older or newer events +* +* KEEP_OLDEST: kernel would retain older events and drop newer events if the buffer is full +* +* KEEP_NEWEST: kernel would retain newer events and drop older events if the buffer is full +* +*/ +#define NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY 0:1 +#define NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY_DISABLED 0 +#define NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY_KEEP_OLDEST 1 +#define NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY_KEEP_NEWEST 2 +#define NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY_DEFAULT NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY_DISABLED + +/* +* NV_EVENT_BUFFER_CTRL_CMD_ENABLE_EVENTS_PARAMS +* +* enable [IN] +* This field is used to enable or disable events +* +* flags[IN] +* This field sets NV_EVENT_BUFFER_FLAG parameter used to configure event buffer overflow options +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_ARGUMENT +*/ +typedef struct NV_EVENT_BUFFER_CTRL_CMD_ENABLE_EVENTS_PARAMS { + NvBool enable; + NvU32 flags; +} NV_EVENT_BUFFER_CTRL_CMD_ENABLE_EVENTS_PARAMS; + +/* +* NV_EVENT_BUFFER_CTRL_CMD_UPDATE_GET +* This interface allows the user to update get pointers. +* This call is useful in the KEEP_OLDEST policy to update free space available in the buffer. +* In keep oldest policy, kernel adds new entries in the buffer only if there is free space. +* The full/empty decision is made as follows: +* - when GET==PUT, the fifo is empty +* - when GET==PUT+1, the fifo is full +*/ +#define NV_EVENT_BUFFER_CTRL_CMD_UPDATE_GET (0x90cd0102) /* finn: Evaluated from "(FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID << 8) | 0x2" */ + +/* +* NV_EVENT_BUFFER_CTRL_CMD_UPDATE_GET_PARAMS +* +* recordBufferGet [IN] +* Value to be used to update the get offset of record buffer +* +* varDataBufferGet[IN] +* This is the buffer offset up to which user has consumed the vardataBuffer +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_ARGUMENT: if any of the get offsets is greater than respective bufferSize. +*/ +typedef struct NV_EVENT_BUFFER_CTRL_CMD_UPDATE_GET_PARAMS { + NvU32 recordBufferGet; + NvU32 varDataBufferGet; +} NV_EVENT_BUFFER_CTRL_CMD_UPDATE_GET_PARAMS; + +/* + * Send a test event-buffer notification (verification-only) + */ +#define NV_EVENT_BUFFER_CTRL_CMD_VERIF_NOTIFY (0x90cd0103) /* finn: Evaluated from "(FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID << 8) | 0x3" */ + +/* + * Synchronous flush + */ +#define NV_EVENT_BUFFER_CTRL_CMD_FLUSH (0x90cd0104) /* finn: Evaluated from "(FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID << 8) | 0x4" */ + +/* + * post event + */ +#define NV_EVENT_BUFFER_CTRL_CMD_POST_TELEMETRY_EVENT (0x90cd0105) /* finn: Evaluated from "(FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID << 8) | 0x5" */ + + /* + * NV_EVENT_BUFFER_CTRL_CMD_POST_TELEMETRY_EVENT_PARAMS + * + * eventType [IN] + * the NvTelemetry event type. + * typeVersion [IN] + * the version of the event structure + * eventData [IN] + * an array of 256 bytes used to hold the event data. + * eventDataSz [IN] + * the amount of valid data in the eventData buffer. + * varData [IN] + * an array of 256 bytes used to hold the var data. + * varDataSz [IN] + * the amount of valid data in the varData buffer. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +typedef struct NV_EVENT_BUFFER_CTRL_CMD_POST_TELEMETRY_EVENT_PARAMS { + NvU32 eventType; + NvU16 typeVersion; + NvU8 eventData[256]; + NvU16 eventDataSz; + NvU8 varData[256]; + NvU16 varDataSz; +} NV_EVENT_BUFFER_CTRL_CMD_POST_TELEMETRY_EVENT_PARAMS; + +/* _ctr l90cd_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90e6.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90e6.h new file mode 100644 index 0000000..ad1d9fb --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90e6.h @@ -0,0 +1,137 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90e6.finn +// + +#include "ctrl/ctrlxxxx.h" +#define NV90E6_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0x90E6, NV90E6_CTRL_##cat, idx) + + +/* NV90E6 command categories (6bits) */ +#define NV90E6_CTRL_RESERVED (0x00) +#define NV90E6_CTRL_MASTER (0x01) + + +/* + * NV90E6_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ + +#define NV90E6_CTRL_CMD_NULL (0x90e60000) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_MASTER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV90E6_CTRL_CMD_MASTER_GET_ERROR_INTR_OFFSET_MASK + * + * This command is used to query the offset and mask within the object mapping + * that can be used to query for ECC and NVLINK interrupts. + * + * If a read of the given offset+mask is non-zero then it is possible an ECC or + * an NVLINK error has been reported and not yet handled. If this is true then + * the caller must either wait until the read returns zero or call into the + * corresponding count reporting APIs to get updated counts. + * + * offset + * The offset into a GF100_SUBDEVICE_MASTSER's mapping where the top level + * interrupt register can be found. + * mask + * Compatibility field that contains the same bits as eccMask. This field is + * deprecated and will be removed. + * eccMask + * The mask to AND with the value found at offset to determine if any ECC + * interrupts are pending. + * nvlinkMask + * The mask to AND with the value found at offset to determine if any NVLINK + * interrupts are pending. + * + * Possible return status values are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV90E6_CTRL_CMD_MASTER_GET_ERROR_INTR_OFFSET_MASK (0x90e60101) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_MASTER_MASTER_INTERFACE_ID << 8) | NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS_MESSAGE_ID" */ + +#define NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS { + NvU32 offset; + NvU32 mask; // TODO: remove after all users have switched to use eccMask + NvU32 eccMask; + NvU32 nvlinkMask; +} NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS; + +// TODO: remove once users of this interface have switched to the new name. +#define NV90E6_CTRL_CMD_MASTER_GET_ECC_INTR_OFFSET_MASK NV90E6_CTRL_CMD_MASTER_GET_ERROR_INTR_OFFSET_MASK + +typedef NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS NV90E6_CTRL_MASTER_GET_ECC_INTR_OFFSET_MASK_PARAMS; + +/* + * NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK + * + * This command is used to query the mask within the fastpath register + * (VIRTUAL_FUNCTION_ERR_CONT) that can be used to query for ECC and NVLINK interrupts. + * + * If a read of the given mask is non-zero then it is possible an ECC or + * an NVLINK error has been reported and not yet handled. If this is true then + * the caller must either wait until the read returns zero or call into the + * corresponding count reporting APIs to get updated counts. + * + * [out] eccMask + * The mask to AND with the value found at offset to determine if any ECC + * interrupts are possibly pending. + * [out] nvlinkMask + * The mask to AND with the value found at offset to determine if any NVLINK + * interrupts are possibly pending. + * + * Possible return status values are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK (0x90e60102) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_MASTER_MASTER_INTERFACE_ID << 8) | NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_MESSAGE_ID" */ + +#define NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS { + NvU32 eccMask; + NvU32 nvlinkMask; +} NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS; + +/* _ctrl90e6_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90ec.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90ec.h new file mode 100644 index 0000000..00094c1 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90ec.h @@ -0,0 +1,124 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90ec.finn +// + +#include "ctrl/ctrlxxxx.h" +/* GK104 HDACODEC control commands and parameters */ + +#define NV90EC_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x90EC, NV90EC_CTRL_##cat, idx) + +/* NV04_DISPLAY_COMMON command categories (6bits) */ +#define NV90EC_CTRL_RESERVED (0x00) +#define NV90EC_CTRL_HDACODEC (0x01) + +/* + * NV90EC_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV90EC_CTRL_CMD_NULL (0x90ec0000) /* finn: Evaluated from "(FINN_GF100_HDACODEC_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV90EC_CTRL_CMD_HDACODEC_SET_CP_READY_ENABLE + * + * This command sets the CP_READY bit. It basically informs RM whether + * the DD has worked upon the HDCP request requested by the Audio driver + * or not. DD asks RM to enable CP_READY bit (by setting CpReadyEnable to NV_TRUE) + * once it is done honouring/dishonouring the request. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the cp ready + * bit should be enabled. The display ID must a dfp display. + * If the displayId is not a dfp, this call will return + * NV_ERR_INVALID_ARGUMENT. + * CpReadyEnable + * This parameter specifies whether to enable (NV_TRUE) or not. If CpReady + * is enabled then AudioCodec can send more HDCP requests. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + * + */ +#define NV90EC_CTRL_CMD_HDACODEC_SET_CP_READY_ENABLE (0x90ec0101) /* finn: Evaluated from "(FINN_GF100_HDACODEC_HDACODEC_INTERFACE_ID << 8) | NV90EC_CTRL_CMD_HDACODEC_SET_CP_READY_ENABLE_PARAMS_MESSAGE_ID" */ + +#define NV90EC_CTRL_CMD_HDACODEC_SET_CP_READY_ENABLE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV90EC_CTRL_CMD_HDACODEC_SET_CP_READY_ENABLE_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bCpReadyEnable; +} NV90EC_CTRL_CMD_HDACODEC_SET_CP_READY_ENABLE_PARAMS; + +/* + * NV90EC_CTRL_CMD_HDACODEC_NOTIFY_AUDIO_EVENT + * + * This command notifies Audio of any events to audio + * like notification of PD bit being set. + * + * audioEvent + * This parameter specifies the event type. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + * + */ +#define NV90EC_CTRL_CMD_HDACODEC_NOTIFY_AUDIO_EVENT (0x90ec0102) /* finn: Evaluated from "(FINN_GF100_HDACODEC_HDACODEC_INTERFACE_ID << 8) | NV90EC_CTRL_HDACODEC_NOTIFY_AUDIO_EVENT_PARAMS_MESSAGE_ID" */ + +#define NV90EC_CTRL_HDACODEC_NOTIFY_AUDIO_EVENT_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV90EC_CTRL_HDACODEC_NOTIFY_AUDIO_EVENT_PARAMS { + NvU32 audioEvent; +} NV90EC_CTRL_HDACODEC_NOTIFY_AUDIO_EVENT_PARAMS; + +/* + * This command notifies audio driver that PD bit is set by DD, by writing to scratch register + */ +#define NV90EC_CTRL_HDACODEC_AUDIOEVENT_PD_BIT_SET (0x00000001) + +/* _ctrl90ec_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90f1.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90f1.h new file mode 100644 index 0000000..20d94dd --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrl90f1.h @@ -0,0 +1,309 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90f1.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "mmu_fmt_types.h" + +#define GMMU_FMT_MAX_LEVELS 6U + +/* Fermi+ GPU VASpace control commands and parameters */ +#define NV90F1_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x90F1, NV90F1_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NV90F1_CTRL_RESERVED (0x00U) +#define NV90F1_CTRL_VASPACE (0x01U) + +/*! + * Does nothing. + */ +#define NV90F1_CTRL_CMD_NULL (0x90f10000U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/*! + * Get VAS GPU MMU format. + */ +#define NV90F1_CTRL_CMD_VASPACE_GET_GMMU_FORMAT (0x90f10101U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS_MESSAGE_ID" */ + +#define NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS { + /*! + * [in] GPU sub-device handle - this API only supports unicast. + * Pass 0 to use subDeviceId instead. + */ + NvHandle hSubDevice; + + /*! + * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. + */ + NvU32 subDeviceId; + + /*! + * [out] GMMU format struct. This is of RM-internal type "struct GMMU_FMT*" + * which can only be accessed by kernel builds since this is a kernel + * only API. + */ + NV_DECLARE_ALIGNED(NvP64 pFmt, 8); +} NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS; + +/*! + * Get VAS page level information. + */ +#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO (0x90f10102U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | 0x2" */ + +typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS { + /*! + * [in] GPU sub-device handle - this API only supports unicast. + * Pass 0 to use subDeviceId instead. + */ + NvHandle hSubDevice; + + /*! + * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. + */ + NvU32 subDeviceId; + + /*! + * [in] GPU virtual address to query. + */ + NV_DECLARE_ALIGNED(NvU64 virtAddress, 8); + + /*! + * [in] Page size to query. + */ + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); + + /*! + * [out] Number of levels populated. + */ + NvU32 numLevels; + + /*! + * [out] Per-level information. + */ + struct { + /*! + * Format of this level. + */ + NV_DECLARE_ALIGNED(struct MMU_FMT_LEVEL *pFmt, 8); + + /*! + * Level/Sublevel Formats flattened + */ + NV_DECLARE_ALIGNED(MMU_FMT_LEVEL levelFmt, 8); + NV_DECLARE_ALIGNED(MMU_FMT_LEVEL sublevelFmt[MMU_FMT_MAX_SUB_LEVELS], 8); + + /*! + * Physical address of this page level instance. + */ + NV_DECLARE_ALIGNED(NvU64 physAddress, 8); + + /*! + * Aperture in which this page level instance resides. + */ + NvU32 aperture; + + /*! + * Size in bytes allocated for this level instance. + */ + NV_DECLARE_ALIGNED(NvU64 size, 8); + } levels[GMMU_FMT_MAX_LEVELS]; +} NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS; + +/*! + * Reserve (allocate and bind) page directory/table entries up to + * a given level of the MMU format. Also referred to as "lock-down". + * + * Each range that has been reserved must be released + * eventually with @ref NV90F1_CTRL_CMD_VASPACE_RELEASE_ENTRIES. + * A particular VA range and level (page size) combination may only be + * locked down once at a given time, but each level is independent. + */ +#define NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES (0x90f10103U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID" */ + +#define NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS { + /*! + * [in] GPU sub-device handle - this API only supports unicast. + * Pass 0 to use subDeviceId instead. + */ + NvHandle hSubDevice; + + /*! + * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. + */ + NvU32 subDeviceId; + + /*! + * [in] Page size (VA coverage) of the level to reserve. + * This need not be a leaf (page table) page size - it can be + * the coverage of an arbitrary level (including root page directory). + */ + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); + + /*! + * [in] First GPU virtual address of the range to reserve. + * This must be aligned to pageSize. + */ + NV_DECLARE_ALIGNED(NvU64 virtAddrLo, 8); + + /*! + * [in] Last GPU virtual address of the range to reserve. + * This (+1) must be aligned to pageSize. + */ + NV_DECLARE_ALIGNED(NvU64 virtAddrHi, 8); +} NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS; + +/*! + * Release (unbind and free) page directory/table entries up to + * a given level of the MMU format that has been reserved through a call to + * @ref NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES. Also referred to as "unlock". + */ +#define NV90F1_CTRL_CMD_VASPACE_RELEASE_ENTRIES (0x90f10104U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_MESSAGE_ID" */ + +#define NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS { + /*! + * [in] GPU sub-device handle - this API only supports unicast. + * Pass 0 to use subDeviceId instead. + */ + NvHandle hSubDevice; + + /*! + * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. + */ + NvU32 subDeviceId; + + /*! + * [in] Page size (VA coverage) of the level to release. + * This need not be a leaf (page table) page size - it can be + * the coverage of an arbitrary level (including root page directory). + */ + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); + + /*! + * [in] First GPU virtual address of the range to release. + * This must be aligned to pageSize. + */ + NV_DECLARE_ALIGNED(NvU64 virtAddrLo, 8); + + /*! + * [in] Last GPU virtual address of the range to release. + * This (+1) must be aligned to pageSize. + */ + NV_DECLARE_ALIGNED(NvU64 virtAddrHi, 8); +} NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS; + +/*! + * Get VAS page level information without kernel priviledge. This will internally call + * NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO. + */ +#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO_VERIF (0x90f10105U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | 0x5" */ + +/*! + * Pin PDEs for a given VA range on the server RM and then mirror the client's page + * directory/tables in the server. + * + * @ref + */ +#define NV90F1_CTRL_CMD_VASPACE_COPY_SERVER_RESERVED_PDES (0x90f10106U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID" */ + +#define NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS { + /*! + * [in] GPU sub-device handle - this API only supports unicast. + * Pass 0 to use subDeviceId instead. + */ + NvHandle hSubDevice; + + /*! + * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. + */ + NvU32 subDeviceId; + + /*! + * [in] Page size (VA coverage) of the level to reserve. + * This need not be a leaf (page table) page size - it can be + * the coverage of an arbitrary level (including root page directory). + */ + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); + + /*! + * [in] First GPU virtual address of the range to reserve. + * This must be aligned to pageSize. + */ + NV_DECLARE_ALIGNED(NvU64 virtAddrLo, 8); + + /*! + * [in] Last GPU virtual address of the range to reserve. + * This (+1) must be aligned to pageSize. + */ + NV_DECLARE_ALIGNED(NvU64 virtAddrHi, 8); + + /*! + * [in] Number of PDE levels to copy. + */ + NvU32 numLevelsToCopy; + + /*! + * [in] Per-level information. + */ + struct { + /*! + * Physical address of this page level instance. + */ + NV_DECLARE_ALIGNED(NvU64 physAddress, 8); + + /*! + * Size in bytes allocated for this level instance. + */ + NV_DECLARE_ALIGNED(NvU64 size, 8); + + /*! + * Aperture in which this page level instance resides. + */ + NvU32 aperture; + + /*! + * Page shift corresponding to the level + */ + NvU8 pageShift; + } levels[GMMU_FMT_MAX_LEVELS]; +} NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS; + +/* _ctrl90f1_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla06c.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla06c.h new file mode 100644 index 0000000..775ce94 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla06c.h @@ -0,0 +1,421 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla06c.finn +// + + + + +/* + * KEPLER_CHANNEL_GROUP_A control commands and parameters + * + * A channel group is a collection of channels which are executed in a specific + * order by hardware. Hardware will not move from one channel in the group + * until it is finished executing all its work or gives up control to the next + * channel. + * + * Channels are added to the group by allocating them as a child of the + * KEPLER_CHANNEL_GROUP_A object. + * + * A channel in a channel group may be restricted with respect to what objects + * can be allocated on it and what APIs are allowed to operate on the channel. + * For more details on specifics of how groups behave see the Software and + * Hardware documetation for the specific architecture in which you are + * interested. + * + */ + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrla06f.h" /* A06C is partially derived from A06F */ + +#include "ctrl/ctrl2080/ctrl2080internal.h" /* For NV2080_CTRL_INTERNAL_MEMDESC_INFO */ +#include "ctrl/ctrlc36f.h" /* For NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES */ + +#define NVA06C_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xA06C, NVA06C_CTRL_##cat, idx) + +/* KEPLER_CHANNEL_GROUP_A command categories (6bits) */ +#define NVA06C_CTRL_RESERVED (0x00) +#define NVA06C_CTRL_GPFIFO (0x01) +#define NVA06C_CTRL_INTERNAL (0x02) + +/* + * NVA06C_CTRL_CMD_NULL + * + * Please see description of NV906D_CTRL_CMD_NULL. + * + */ +#define NVA06C_CTRL_CMD_NULL (0xa06c0000) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NVA06C_CTRL_CMD_GPFIFO_SCHEDULE + * + * This command schedules a channel group in hardware. This command should be + * called after objects have been allocated on the channel or a call to + * NVA06C_CTRL_CMD_BIND has been made. + * + * See NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for parameter definitions. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_OPERATION + * + */ +#define NVA06C_CTRL_CMD_GPFIFO_SCHEDULE (0xa06c0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */ +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA06C_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA06C_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS { + NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS params; +} NVA06C_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS; + + + + +/* + * NVA06C_CTRL_CMD_BIND + * + * This command uses the given engine to configure the group for scheduling. + * It alleviates the need to call NVA06C_CTRL_CMD_GPFIFO_SCHEDULE after objects + * have been allocated. However, it requires that the caller know which engine + * they want to be able to execute in the group. Once this has been called + * only objects that can be allocated on the specified engine or other engines + * allowed to coexist in the group will be allowed. See + * NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST to determine which engines can + * share a parent. + * + * See NVA06F_CTRL_CMD_BIND for parameter definitions. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06C_CTRL_CMD_BIND (0xa06c0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_BIND_PARAMS_MESSAGE_ID" */ + +#define NVA06C_CTRL_BIND_PARAMS_MESSAGE_ID (0x2U) + +typedef NVA06F_CTRL_BIND_PARAMS NVA06C_CTRL_BIND_PARAMS; + +/* + * NVA06C_CTRL_CMD_SET_TIMESLICE + * + * This command modifies the timeslice for a channel group. Hardware may not + * support all possible values, so the input will be rounded down to a valid + * hardware value. + * + * This takes effect immediately, meaning the channel may be forced off of the + * GPU so the change can be made. + * + * timesliceUs + * This parameter is an input containing the desired timeslice in microseconds + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06C_CTRL_CMD_SET_TIMESLICE (0xa06c0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */ + +/* + * NVA06C_CTRL_CMD_GET_TIMESLICE + * + * This command returns the timeslice for a channel group. If + * NVA06C_CTRL_CMD_SET_TIMESLICE has been used this call will return the exact + * value passed to that function, which may not be exactly what is programmed + * to hardware (see NVA06C_CTRL_CMD_SET_TIMESLICE for more details). + * + * timesliceUs + * This parameter is an output containing current timeslice in microseconds. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06C_CTRL_CMD_GET_TIMESLICE (0xa06c0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */ + +typedef struct NVA06C_CTRL_TIMESLICE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 timesliceUs, 8); +} NVA06C_CTRL_TIMESLICE_PARAMS; + +/* + * NVA06C_CTRL_CMD_PREEMPT + * + * This command preempts a channel group. It optionally waits for the preempt to + * complete before returning. + * + * bWait + * If bWait evaluates to NV_TRUE then this control call waits till the preempt + * completes, else it returns immediately after issuing the preempt. Calling + * this control call multiple times with bWait = NV_FALSE without waiting for + * the preempt to complete by some other means can lead to undefined results. + * bManualTimeout + * If bManualTimer evaluates to NV_TRUE then timeoutUs will be used as the + * timeout value. + * timeoutUs + * The desired timeout in microseconds. Only used if bManualTimeout evaluates + * to NV_TRUE. The maximum value of timeoutUs is + * NVA06C_CTRL_CMD_PREEMPT_MAX_MANUAL_TIMEOUT_US. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + * + */ +#define NVA06C_CTRL_CMD_PREEMPT (0xa06c0105) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_PREEMPT_PARAMS_MESSAGE_ID" */ + +#define NVA06C_CTRL_PREEMPT_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVA06C_CTRL_PREEMPT_PARAMS { + NvBool bWait; + NvBool bManualTimeout; + NvU32 timeoutUs; +} NVA06C_CTRL_PREEMPT_PARAMS; + +#define NVA06C_CTRL_CMD_PREEMPT_MAX_MANUAL_TIMEOUT_US (1000000) // 1 second + +/* + * NVA06C_CTRL_CMD_GET_INFO + * + * This command returns information about the channel group. + * + * tsgID + * Output parameter containing the hardware TSG ID for this channel group. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NVA06C_CTRL_CMD_GET_INFO (0xa06c0106) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NVA06C_CTRL_GET_INFO_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NVA06C_CTRL_GET_INFO_PARAMS { + NvU32 tsgID; +} NVA06C_CTRL_GET_INFO_PARAMS; + +/* + * NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL + * + * Used to change the target TSG's interleave level in the runlist. The + * interleave level indicates how often channels in the TSG appear in the + * runlist according to the following policy: + * + * - LOW: Appear once + * - MEDIUM: If L > 0, appear L times + * Else, appear once + * - HIGH: If L > 0, appear (M + 1) * L times + * Else if M > 0, appear M times + * Else, appear once + * where + * - L = # of LOW interleave level TSGs + * - M = # of MEDIUM interleave level TSGs + * + * For safety reasons, setting this property requires PRIVILEGED user level. + * + * tsgInterleaveLevel + * Input parameter. One of: + * - NVA06C_CTRL_INTERLEAVE_LEVEL_LOW + * - NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM + * - NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +#define NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL (0xa06c0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */ + +/* + * NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL + * + * Returns the target TSG's interleave level. + * + * tsgInterleaveLevel + * Output parameter. One of: + * - NVA06C_CTRL_INTERLEAVE_LEVEL_LOW + * - NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM + * - NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL (0xa06c0108) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x8" */ + +typedef struct NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS { + NvU32 tsgInterleaveLevel; +} NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS; + +#define NVA06C_CTRL_INTERLEAVE_LEVEL_LOW (0x00000000) +#define NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM (0x00000001) +#define NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH (0x00000002) + +/* + * NVA06C_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE + * This ctrl call is deprecated in favor of NV0090_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE. + * @see NV0090_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE + */ +#define NVA06C_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE (0xa06c0109) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS_MESSAGE_ID" */ + +typedef enum NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE { + NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_NONE = 0, + NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_64B = 1, + NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_128B = 2, +} NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE; + +typedef struct NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD { + NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE size; +} NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD; + +#define NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS { + NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD l1; + NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD t1; +} NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS; + +/*! + * NVA06C_CTRL_CMD_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS + * + * This control call is used to + * - set the fault method buffer addresses in vGpu host / GSP after the fault + * method buffers are allocated by vGpu guest / GSP_CLIENT during channel + * group allocation + * - destroy the method buffer memory descriptors during channel group free + * + * methodBufferMemdesc [input] + * Details about the memory allocated for method buffer for each runqueue. + * If the size of the memory region is zero, the descriptor will be destroyed. + * + * bar2Addr [input] + * CPU invisible BAR2 address that the method buffer is mapped to for each + * runqueue + * + * numValidEntries [input] + * The number of valid entries upto + * NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES actually filled in + * the control call parameters. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA06C_CTRL_CMD_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS (0xa06c010a) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8 | NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_MESSAGE_ID)" */ + +#define NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES (NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES) + +#define NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_MESSAGE_ID (0xaU) + +typedef struct NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MEMDESC_INFO methodBufferMemdesc[NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES], 8); + NV_DECLARE_ALIGNED(NvU64 bar2Addr[NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES], 8); + NvU32 numValidEntries; +} NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS; + +/* + * NVA06C_CTRL_CMD_MAKE_REALTIME + * + * Promote the specified TSG to realtime, or demote to non-realtime, + * depending on the given bRealtime parameter. A realtime TSG will have the + * highest interleave level when the scheduling policy is CHANNEL_INTERLEAVED, + * and will also precede any non-realtime channel/TSG in the order channels are + * added to the corresponding runlist. + * + * Whenever a realtime TSG is added to a runlist, all non-realtime channels/TSGs + * are made preemptible by setting a COMPUTE preemption mode to CTA. + * + * Preemption modes for realtime TSGs remain WFI. + * + * A client must then issue a NVA06F_CTRL_CMD_RESTART_RUNLIST control call when + * kicking off work on a realtime TSG to preempt non-realtime channels and + * restart the runlist such that the realtime TSG will start executing next. + * + * bRealtime + * Whether the TSG is to be promoted to/demoted from realtime. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAMETER + * NV_ERR_INVALID_OBJECT + * NV_ERR_INVALID_STATE + * NV_ERR_NOT_SUPPORTED + */ +#define NVA06C_CTRL_CMD_MAKE_REALTIME (0xa06c0110) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_MAKE_REALTIME_PARAMS_MESSAGE_ID" */ + +#define NVA06C_CTRL_MAKE_REALTIME_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NVA06C_CTRL_MAKE_REALTIME_PARAMS { + NvBool bRealtime; +} NVA06C_CTRL_MAKE_REALTIME_PARAMS; + + + +/* + * NVA06C_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE + * + * This command is an internal command sent from Kernel RM to Physical RM + * to schedule a channel group in hardware. + * + * Please see description of NVA06C_CTRL_CMD_GPFIFO_SCHEDULE for more information. + * + */ +#define NVA06C_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE (0xa06c0201) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID << 8) | 0x1" */ + +/* + * NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE + * + * This command is an internal command sent from Kernel RM to Physical RM + * to modify the timeslice for a channel group in hardware. + * + * Please see description of NVA06C_CTRL_CMD_SET_TIMESLICE for more information. + * + */ +#define NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE (0xa06c0202) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID << 8) | 0x2" */ + +/* _ctrla06c.h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla06f.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla06f.h new file mode 100644 index 0000000..b768326 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla06f.h @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla06f.finn +// + + + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrla06f/ctrla06fbase.h" +#include "ctrl/ctrla06f/ctrla06fgpfifo.h" +#include "ctrl/ctrla06f/ctrla06fevent.h" +#include "ctrl/ctrla06f/ctrla06finternal.h" diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla06f/ctrla06fbase.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla06f/ctrla06fbase.h new file mode 100644 index 0000000..39c977a --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla06f/ctrla06fbase.h @@ -0,0 +1,60 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla06f/ctrla06fbase.finn +// + + + + +/* GK100_GPFIFO control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl906f.h" /* A06F is partially derived from 906F */ + +#define NVA06F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xA06F, NVA06F_CTRL_##cat, idx) + +/* GK100_GPFIFO command categories (6bits) */ +#define NVA06F_CTRL_RESERVED (0x00) +#define NVA06F_CTRL_GPFIFO (0x01) +#define NVA06F_CTRL_EVENT (0x02) +#define NVA06F_CTRL_INTERNAL (0x03) + +/* + * NVA06F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + * + */ +#define NVA06F_CTRL_CMD_NULL (0xa06f0000) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrla06fbase_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla06f/ctrla06fevent.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla06f/ctrla06fevent.h new file mode 100644 index 0000000..245673b --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla06f/ctrla06fevent.h @@ -0,0 +1,92 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla06f/ctrla06fevent.finn +// + +#include "ctrl/ctrla06f/ctrla06fbase.h" + +/* + * NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * This command sets event notification state for the associated channel. + * This command requires that an instance of NV01_EVENT has been previously + * bound to the associated channel object. + * + * event + * This parameter specifies the type of event to which the specified + * action is to be applied. This parameter must specify a valid + * NVA06F_NOTIFIERS value (see cla06f.h for more details) and should + * not exceed one less NVA06F_NOTIFIERS_MAXCOUNT. + * action + * This parameter specifies the desired event notification action. + * Valid notification actions include: + * NVA06F_CTRL_SET_EVENT_NOTIFICATION_ACTION_DISABLE + * This action disables event notification for the specified + * event for the associated channel object. + * NVA06F_CTRL_SET_EVENT_NOTIFICATION_ACTION_SINGLE + * This action enables single-shot event notification for the + * specified event for the associated channel object. + * NVA06F_CTRL_SET_EVENT_NOTIFICATION_ACTION_REPEAT + * This action enables repeated event notification for the specified + * event for the associated channel object. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa06f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS { + NvU32 event; + NvU32 action; +} NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001) +#define NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002) + +/* + * NVA06F_CTRL_CMD_EVENT_SET_TRIGGER + * + * This command triggers a software event for the associated channel. + * This command accepts no parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVA06F_CTRL_CMD_EVENT_SET_TRIGGER (0xa06f0206) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */ + + +/* _ctrla06fevent_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h new file mode 100644 index 0000000..699e6c6 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h @@ -0,0 +1,288 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla06f/ctrla06fgpfifo.finn +// + +#include "ctrl/ctrla06f/ctrla06fbase.h" + +/* + * NVA06F_CTRL_GET_CLASS_ENGINEID + * + * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. + * + */ +#define NVA06F_CTRL_GET_CLASS_ENGINEID (0xa06f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */ + +typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS { + NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS params; +} NVA06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS; + + + +/* + * NVA06F_CTRL_RESET_CHANNEL + * + * Please see description of NV906F_CTRL_RESET_CHANNEL for more information. + */ +#define NVA06F_CTRL_CMD_RESET_CHANNEL (0xa06f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */ + +typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVA06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS { + NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS params; +} NVA06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS; + + + +/* + * NVA06F_CTRL_CMD_GPFIFO_SCHEDULE + * + * This command schedules a channel in hardware. This command should be called + * after objects have been allocated on the channel or a call to + * NVA06F_CTRL_CMD_BIND has been made. + * + * bEnable + * This parameter indicates whether or not the channel should be scheduled in hardware. + * When set, the channel will be enabled in addition to being added to the appropriate runlist. + * When not set, the channel will be disabled and removed from runlist. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_OPERATION + * + */ +#define NVA06F_CTRL_CMD_GPFIFO_SCHEDULE (0xa06f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */ +#define NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS { + NvBool bEnable; + NvBool bSkipSubmit; +} NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS; + +/* + * NVA06F_CTRL_CMD_BIND + * + * This command uses the given engine to configure the channel for scheduling. + * It alleviates the need to call NVA06F_CTRL_CMD_GPFIFO_SCHEDULE after objects + * have been allocated. However, it requires that the caller know which engine + * they want to be able to execute on the channel. Once this has been called + * only objects that can be allocated on the specified engine or other engines + * allowed to coexist on the channel will be allowed. See + * NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST to determine which engines can + * share a parent. + * + * engineType + * This parameter specifies an NV2080_ENGINE_TYPE value indicating the + * engine to which this channel should be bound. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06F_CTRL_CMD_BIND (0xa06f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_BIND_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_BIND_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVA06F_CTRL_BIND_PARAMS { + NvU32 engineType; +} NVA06F_CTRL_BIND_PARAMS; + + + +/* + * NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO + * + * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. + * + */ +#define NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa06f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */ + +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA06F_CTRL_GET_MMU_FAULT_INFO_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS { + NV_DECLARE_ALIGNED(NVA06F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8); +} NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS; + + + +/* + * NVA06F_CTRL_CMD_SET_ERROR_NOTIFIER + * + * This command sets the channel error notifier of the target channel. + * bNotifyEachChannelInTSG + * When true, the error notifier will be set on every channel in + * the TSG that contains the channel. + * + * Possible status values returned are: + * NV_OK + */ +#define NVA06F_CTRL_CMD_SET_ERROR_NOTIFIER (0xa06f0108) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS { + NvBool bNotifyEachChannelInTSG; +} NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS; + +/* + * NVA06F_CTRL_CMD_SET_INTERLEAVE_LEVEL + * + * Symmetric to NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL, applied to the individual + * target channel. + * + * When belonging to a TSG, same interleave level will be set to every channel + * in the TSG. + * + * channelInterleaveLevel + * Input parameter. One of: + * - NVA06C_CTRL_INTERLEAVE_LEVEL_LOW + * - NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM + * - NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +#define NVA06F_CTRL_CMD_SET_INTERLEAVE_LEVEL (0xa06f0109) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x9" */ + +/* + * NVA06F_CTRL_CMD_GET_INTERLEAVE_LEVEL + * + * Returns the target channel's interleave level. + * + * channelInterleaveLevel + * Output parameter. One of: + * - NVA06C_CTRL_INTERLEAVE_LEVEL_LOW + * - NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM + * - NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06F_CTRL_CMD_GET_INTERLEAVE_LEVEL (0xa06f0110) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x10" */ + +typedef struct NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS { + NvU32 channelInterleaveLevel; +} NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS; + +/* + * NVA06F_CTRL_CMD_RESTART_RUNLIST + * + * This command expires the current timeslice and restarts the runlist the given + * channel belongs to. This effectively preempts the current channel on the + * corresponding engine. + * + * This is useful for clients to trigger preemption manually and reduce start + * latency for higher priority channels as they are added first to the runlist + * if NV0080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED policy is + * configured. + * + * This command interacts with the scheduler and may cause certain low priority + * channels to starve under certain circumstances. Therefore, it is only + * available to privileged clients. + * + * bForceRestart + * Input parameter. If NV_FALSE, the runlist restart will be skipped + * whenever the given channel (or its group) is already running on the + * corresponding engine. + * + * bBypassWait + * Input parameter. If NV_TRUE, the command will return immediately after + * issuing the hardware preemption request, without actually waiting for the + * context switch to complete. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06F_CTRL_CMD_RESTART_RUNLIST (0xa06f0111) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_RESTART_RUNLIST_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_RESTART_RUNLIST_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NVA06F_CTRL_RESTART_RUNLIST_PARAMS { + NvBool bForceRestart; + NvBool bBypassWait; +} NVA06F_CTRL_RESTART_RUNLIST_PARAMS; + +/* + * NVA06F_CTRL_CMD_STOP_CHANNEL + * + * This command is used to stop the channel + * + * Stopping the channel here means disabling and unbinding the channel and removing it from runlist. + * So, if the channel needs to run again, it has to be scheduled, bound and enabled again. + * If we fail to preempt channel or remove it from runlist, then we RC the channel. + * Also set an error notifier to notify user space that channel is stopped. + * + * bImmediate + * Input parameter. If NV_FALSE, we will wait for default RM timeout + * for channel to idle. If NV_TRUE, we don't wait for channel to idle. + * If channel is not idle, we forcefully preempt it off the runlist. + * If the preempt times out, we will RC the channel. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06F_CTRL_CMD_STOP_CHANNEL (0xa06f0112) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_STOP_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_STOP_CHANNEL_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NVA06F_CTRL_STOP_CHANNEL_PARAMS { + NvBool bImmediate; +} NVA06F_CTRL_STOP_CHANNEL_PARAMS; + +/* _ctrla06fgpfifo_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h new file mode 100644 index 0000000..7a37815 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h @@ -0,0 +1,67 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla06f/ctrla06finternal.finn +// + +#include "ctrl/ctrla06f/ctrla06fbase.h" +#include "ctrl/ctrla06f/ctrla06fgpfifo.h" + +/* + * NVA06F_CTRL_CMD_INTERNAL_STOP_CHANNEL + * + * This command is an internal command sent from Kernel RM to Physical RM + * to stop the channel in hardware + * + * Please see description of NVA06F_CTRL_CMD_STOP_CHANNEL for more information. + * + */ +#define NVA06F_CTRL_CMD_INTERNAL_STOP_CHANNEL (0xa06f0301) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | 0x1" */ + +/* + * NVA06F_CTRL_CMD_INTERNAL_RESET_CHANNEL + * + * This command is an internal command sent from Kernel RM to Physical RM + * to perform the channel reset operations in hardware + * + * Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information. + * + */ +#define NVA06F_CTRL_CMD_INTERNAL_RESET_CHANNEL (0xa06f0302) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | 0x2" */ + +/* + * NVA06F_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE + * + * This command is an internal command sent from Kernel RM to Physical RM + * to schedule the channel in hardware + * + * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. + * + */ +#define NVA06F_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE (0xa06f0303) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | 0x3" */ + +/* ctrla06finternal_h */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla080.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla080.h new file mode 100644 index 0000000..b956ab9 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla080.h @@ -0,0 +1,658 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla080.finn +// + + + + + +/* + * NVA080_CTRL_CMD_VGPU_DISPLAY_SET_SURFACE_PROPERTIES + * + * This command sets primary surface properties on a virtual GPU in displayless mode + * + * Parameters: + * headIndex + * This parameter specifies the head for which surface properties are + * + * isPrimary + * This parameter indicates whether surface information is for primary surface. set to 1 if its a primary surface. + * + * hMemory + * Memory handle containing the surface (only for RM-managed heaps) + * + * offset + * Offset from base of allocation (hMemory for RM-managed heaps; physical + * memory otherwise) + * + * surfaceType + * This parameter indicates whether surface type is block linear or pitch + * + * surfaceBlockHeight + * This parameter indicates block height for the surface + * + * surfacePitch + * This parameter indicates pitch value for the surface + * + * surfaceFormat + * This parameter indicates surface format (A8R8G8B8/A1R5G5B5) + * + * surfaceWidth + * This parameter indicates width value for the surface + * + * surfaceHeight + * This parameter indicates height value for the surface + * + * surfaceSize + * This parameter indicates size of the surface + * + * surfaceKind + * This parameter indicates surface kind (only for externally-managed + * heaps) + * + * rectX [unused] + * This parameter indicates X coordinate of the region to be displayed + * + * rectY [unused] + * This parameter indicates Y coordinate of the region to be displayed + * + * rectWidth + * This parameter indicates width of the region to be displayed + * + * rectHeight + * This parameter indicates height of the region to be displayed + * + * hHwResDevice + * This parameter indicates the device associated with surface + * + * hHwResHandle + * This parameter indicates the handle to hardware resources allocated to surface + * + * effectiveFbPageSize + * This parameter indicates the actual page size used by KMD for the surface + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_NOT_SUPPORTED + */ + +#define NVA080_CTRL_CMD_VGPU_DISPLAY_SET_SURFACE_PROPERTIES (0xa0800103) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MESSAGE_ID" */ + +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MESSAGE_ID (0x3U) + +typedef struct NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES { + NvU32 headIndex; + NvU32 isPrimary; + NvU32 hMemory; + NvU32 offset; + NvU32 surfaceType; + NvU32 surfaceBlockHeight; + NvU32 surfacePitch; + NvU32 surfaceFormat; + NvU32 surfaceWidth; + NvU32 surfaceHeight; + NvU32 rectX; + NvU32 rectY; + NvU32 rectWidth; + NvU32 rectHeight; + NvU32 surfaceSize; + NvU32 surfaceKind; + NvU32 hHwResDevice; + NvU32 hHwResHandle; + NvU32 effectiveFbPageSize; +} NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES; + +/* valid surfaceType values */ +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MEMORY_LAYOUT 0:0 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MEMORY_LAYOUT_PITCH 0x00000001 +/* valid surfaceBlockHeight values */ +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +/* valid surfaceFormat values */ +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_I8 0x0000001E +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_RF16_GF16_BF16_AF16 0x000000CA +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A8R8G8B8 0x000000CF +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A2B10G10R10 0x000000D1 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_X2BL10GL10RL10_XRBIAS 0x00000022 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A8B8G8R8 0x000000D5 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_R5G6B5 0x000000E8 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A1R5G5B5 0x000000E9 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_R16_G16_B16_A16 0x000000C6 + +/* + * NVA080_CTRL_CMD_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS + * + * This command clears surface information related to head. + * It should be called while shutting down head in displayless mode on virtual GPU + * + * Parameters: + * headIndex + * This parameter specifies the head for which cleanup is requested. + * + * blankingEnabled + * This parameter must be set to 1 to enable blanking. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_NOT_SUPPORTED + */ +#define NVA080_CTRL_CMD_VGPU_DISPLAY_CLEANUP_SURFACE (0xa0800104) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS { + NvU32 headIndex; + NvU32 blankingEnabled; +} NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS; + +/* + * NVA080_CTRL_CMD_VGPU_DISPLAY_GET_POINTER_ADDRESS + * + * This command returns CPU virtual address of the mouse pointer mapping for VGPU. + * The address returned by this command is the pointer address for the head 0. + * VGPU_POINTER_OFFSET_HEAD(i) should be added to this address to get the address of head i. + * VGPU mouse pointer is a 32 bit value, X location of the mouse pointer is stored in + * 15:0 and Y location is stored in 31:16 bits. X location value of the mouse pointer is + * negative if bit 15 is set. Similarly, Y location value is negative if bit 31 is set. + * + * Parameters: + * pPointerAddress + * CPU virtual address of the mouse pointer mapping for VGPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_NOT_SUPPORTED + */ + +#define NVA080_CTRL_CMD_VGPU_DISPLAY_GET_POINTER_ADDRESS (0xa0800105) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pPointerAddress, 8); +} NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS; + +#define VGPU_POINTER_OFFSET_HEAD0_VALUE 0x00000000 +#define VGPU_POINTER_OFFSET_HEAD0_FLAG 0x00000004 +#define VGPU_POINTER_OFFSET_HEAD1_VALUE 0x00000008 +#define VGPU_POINTER_OFFSET_HEAD1_FLAG 0x0000000c +#define VGPU_POINTER_OFFSET_HEAD2_VALUE 0x00000010 +#define VGPU_POINTER_OFFSET_HEAD2_FLAG 0x00000014 +#define VGPU_POINTER_OFFSET_HEAD3_VALUE 0x00000018 +#define VGPU_POINTER_OFFSET_HEAD3_FLAG 0x0000001c +#define VGPU_POINTER_OFFSET_HEAD_VALUE(i) (i * 8) +#define VGPU_POINTER_OFFSET_HEAD_FLAG(i) (4 + i * 8) +#define VGPU_POINTER_OFFSET_HEAD_SIZE 4 + +/* + * NVA080_CTRL_CMD_GET_MAPPABLE_VIDEO_SIZE + * + * This command returns mappable video size to be used by each VM. + * + * Parameters: + * mappableVideoSize + * This parameter returns mappable video size in bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_NOT_SUPPORTED + */ + + +#define NV_VGPU_POINTER_X_LOCATION 15:0 +#define NV_VGPU_POINTER_Y_LOCATION 31:16 +#define NVA080_CTRL_CMD_GET_MAPPABLE_VIDEO_SIZE (0xa0800201) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 mappableVideoSize, 8); +} NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS; + +/* + * NVA080_CTRL_CMD_MAP_SEMA_MEM + * + * This command returns GPU VA for the channel with 'hCtxDma' handle + * where per VM semaphore memory is mapped which is used for tracking + * non-stall interrupt of each VM. + * + * Parameters: + * hClient [in] + * This parameter specifies the handle to the NV01_ROOT object of + * the client. This object should be the parent of the object + * specified by hDevice. + * hDevice [in] + * This parameter specifies the handle of the NV01_DEVICE object + * representing the desired GPU. + * hMemory [in] + * This parameter specifies the handle for semaphore memory + * hCtxDma [in] + * This parameter specifies the handle of the NV01_CONTEXT_DMA + * object through which bufferId is written in semaphore memory for + * non-stall interrupt tracking. + * semaAddress [out] + * This parameter returns the GPU virtual address of the semaphore + * memory. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INVALID_DATA + * NV_ERR_INVALID_CLIENT + * NV_ERR_INVALID_OBJECT_HANDLE + * + */ + +#define NVA080_CTRL_CMD_MAP_SEMA_MEM (0xa0800202) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | 0x2" */ + +typedef struct NVA080_CTRL_MAP_SEMA_MEM_PARAMS { + NvHandle hClient; + NvHandle hDevice; + NvHandle hMemory; + NvHandle hCtxDma; + NV_DECLARE_ALIGNED(NvU64 semaAddress, 8); +} NVA080_CTRL_MAP_SEMA_MEM_PARAMS; + +/* + * NVA080_CTRL_CMD_UNMAP_SEMA_MEM + * + * This command unmaps per VM semaphore memory from GPU VA space, mapped by + * NVA080_CTRL_CMD_MAP_SEMA_MEM command. + * + * Parameters: + * Same as NVA080_CTRL_MAP_SEMA_MEM_PARAMS, except semaAddress is input + * parameter here. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INVALID_DATA + * NV_ERR_INVALID_CLIENT + * NV_ERR_INVALID_OBJECT_HANDLE + * + */ + +#define NVA080_CTRL_CMD_UNMAP_SEMA_MEM (0xa0800203) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | 0x3" */ + +/*! + * NVA080_CTRL_CMD_SET_FB_USAGE + * + * This command sets the current framebuffer usage value in the plugin. + * + * Parameters: + * fbUsed [in] + * This parameter holds the current FB usage value in bytes. + * + * Possible status values returned are: + * NV_OK + */ +#define NVA080_CTRL_CMD_SET_FB_USAGE (0xa0800204) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVA080_CTRL_SET_FB_USAGE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); +} NVA080_CTRL_SET_FB_USAGE_PARAMS; + +/*! +* NVA080_CTRL_CMD_MAP_PER_ENGINE_SEMA_MEM +* +* This command allocates the per engine vGPU semaphore memory and map it to +* GPU/CPU VA. +* +* Calculate engine's semaphore GPU VA = +* semaAddress + semaStride * NV2080_ENGINE_TYPE_ of that engine +* +* Parameters: +* hClient [in] +* This parameter specifies the handle to the NV01_ROOT object of +* the client. This object should be the parent of the object +* specified by hDevice. +* hDevice [in] +* This parameter specifies the handle of the NV01_DEVICE object +* representing the desired GPU. +* hMemory [in] +* This parameter specifies the handle for semaphore memory +* hCtxDma [in] +* This parameter specifies the handle of the NV01_CONTEXT_DMA +* object through which bufferId is written in semaphore memory for +* non-stall interrupt tracking. +* semaAddress [out] +* This parameter returns the GPU VA of the per engine semaphore memory. +* semaStride [out] +* This parameter specifies the stride of each engine's semaphore offset within this memory. +* +* Possible status values returned are: +* NV_OK +*/ + +#define NVA080_CTRL_CMD_MAP_PER_ENGINE_SEMA_MEM (0xa0800205) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS { + NvU32 hClient; + NvU32 hDevice; + NvHandle hMemory; + NvU32 hCtxDma; + NV_DECLARE_ALIGNED(NvU64 semaAddress, 8); + NvU32 semaStride; +} NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS; + +/*! +* NVA080_CTRL_CMD_UNMAP_PER_ENGINE_SEMA_MEM +* +* This command unmaps and frees the per engine vGPU semaphore memory. +* +* Parameters: +* Same as NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS, except semaAddress is input +* parameter here. +* +* Possible status values returned are: +* NV_OK +*/ + +#define NVA080_CTRL_CMD_UNMAP_PER_ENGINE_SEMA_MEM (0xa0800206) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x6U) + +typedef NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS; + +/* + * NVA080_CTRL_CMD_UPDATE_SYSMEM_BITMAP + * + * This command provides the guest RM with PFN information, so that it can + * update the shared memory with the plugin, which keeps track of guest sysmem. + * + * Parameters: + * destPhysAddr + * Start address of the segment to be tracked + * + * pageCount + * Number of pages in the segment + * + * pageSize + * Size of pages in the segment + * + * isValid: + * TRUE : Set bits corresponding to PFNs in bitmap and increase segment refcount + * FALSE: Decrease segment refcount and then unset bits if refcount is 0 + * + * pfnList + * List of PFNs in the segment + * + * flags + * FLAGS_DST_PHYS_ADDR_BAR1_OFFSET + * Flag set to TRUE if pteMem is CPU VA pointing to BAR1 and + * dstPhysAddr contains BAR1 offset. + * + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + */ + +#define NVA080_CTRL_CMD_UPDATE_SYSMEM_BITMAP (0xa0800207) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_FLAGS_DST_PHYS_ADDR_BAR1_OFFSET 0:0 +#define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_FLAGS_DST_PHYS_ADDR_BAR1_OFFSET_FALSE (0x00000000) +#define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_FLAGS_DST_PHYS_ADDR_BAR1_OFFSET_TRUE (0x00000001) + +#define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS { + NV_DECLARE_ALIGNED(NvU64 destPhysAddr, 8); + NvU32 pageCount; + NvU32 pageSize; + NvBool isValid; + NV_DECLARE_ALIGNED(NvP64 pfnList, 8); + NvU32 flags; +} NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS; + +/* + * Blit semaphore offset location + */ +#define VGPU_BLIT_RESTORE_SEMA_MEM_OFFSET 0x200 +#define VGPU_BLIT_RESTORE_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_BLIT_RESTORE_SEMA_MEM_OFFSET) + +#define VGPU_BLIT_SEMA_MEM_OFFSET 0x400 +#define VGPU_BLIT_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_BLIT_SEMA_MEM_OFFSET) + +#define VGPU_FBMEMCE_PUSH_SEMA_MEM_OFFSET 0x800 +#define VGPU_FBMEMCE_PUSH_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_PUSH_SEMA_MEM_OFFSET) + +#define VGPU_FBMEMCE_SEMA_MEM_OFFSET 0x810 +#define VGPU_FBMEMCE_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_SEMA_MEM_OFFSET) + +#define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_LOWER_OFFSET 0x820 +#define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_LOWER_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_PIPELINED_SEMA_MEM_LOWER_OFFSET) + +#define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_UPPER_OFFSET 0x824 + +/* + * NVA080_CTRL_CMD_VGPU_GET_CONFIG + * + * This command returns VGPU configuration information for the associated GPU. + * + * Parameters: + * frameRateLimiter + * This parameter returns value of frame rate limiter + * swVSyncEnabled + * This parameter returns value of SW VSync flag (zero for disabled, + * non-zero for enabled) + * cudaEnabled + * This parameter returns whether CUDA is enabled or not + * pluginPteBlitEnabled + * This parameter returns whether to use plugin pte blit path + * disableWddm1xPreemption + * This parameter returns whether to disable WDDM 1.x Preemption or not + * debugBuffer + * This parameter specifies a pointer to memory which is filled with + * debugging information. + * debugBufferSize + * This parameter specifies the size of the debugging buffer in bytes. + * guestFbOffset + * This parameter returns FB offset start address for VM + * mappableCpuHostAperture + * This parameter returns mappable CPU host aperture size + * linuxInterruptOptimization + * This parameter returns whether stall interrupts are enabled/disabled for + * Linux VM + * vgpuDeviceCapsBits + * This parameter specifies CAP bits to ON/OFF features from guest OS. + * CAPS_SW_VSYNC_ENABLED + * cap bit to indicate if SW VSync flag enabled/disabled. + * Please note, currently, guest doesn't honour this bit. + * CAPS_CUDA_ENABLED + * cap bit to indicate if CUDA enabled/disabled. + * Please note, currently, guest doesn't honour this bit. + * CAPS_WDDM1_PREEMPTION_DISABLED + * cap bit to indicate if WDDM 1.x Preemption disabled/enabled. + * Please note, currently, guest doesn't honour this bit. + * CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED + * cap bit to indicate if stall interrupts are enabled/disabled for + * Linux VM. Please note, currently, guest doesn't honour this bit. + * CAPS_PTE_BLIT_ENABLED + * cap bit to indicate if PTE blit is enabled/disabled. + * Please note, currently, guest doesn't honour this bit. + * CAPS_PDE_BLIT_ENABLED + * cap bit to indicate if PDE blit is enabled/disabled. + * CAPS_GET_PDE_INFO_CTRL_DISABLED + * cap bit to indicate if GET_PDE_INFO RM Ctrl is disabled/enabled. + * CAPS_GUEST_FB_OFFSET_DISABLED + * cap bit to indicate if FB Offset is exposed to guest or not. + * If set, FB Offset is not exposed to guest. + * CAPS_CILP_DISABLED_ON_WDDM + * cap bit to indicate if CILP on WDDM disabled/enabled. + * CAPS_UPDATE_DOORBELL_TOKEN_ENABLED + * cap bit to indicate if guest needs to use doorbell token value updated + * dynamically by host after migration. + * CAPS_SRIOV_ENABLED + * Cap bit to indicate if the vGPU is running in SRIOV mode or not. + * CAPS_GUEST_MANAGED_VA_ENABLED + * Cap bit to indicate if the Guest is managing the VA. + * CAPS_VGPU_1TO1_COMPTAG_ENABLED + * Cap bit to indicate if the 1to1 comptag enabled. This is always TRUE + * when SR-IOV is enabled. + * CAPS_MBP_ENABLED + * Cap bit to indicate if the Mid Buffer Preemption enabled. + * CAPS_ASYNC_MBP_ENABLED + * Cap bit to indicate if the asynchronus Mid buffer Preemption enabled. + * CAPS_TLB_INVALIDATE_ENABLED + * Cap bit to indicate if the vGPU supports TLB Invalidation operation or not. + * CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED + * Cap bit to indicate if the vGPU supports PTE blit for page table updates using BAR1 + * CAPS_SRIOV_HEAVY_ENABLED + * Cap bit to indicate if vGPU is running in SRIOV Heavy mode or not. + * When set true SRIOV Heavy is enabled. + * When set false and CAPS_SRIOV_ENABLED is set true, SRIOV Standard is enabled. + * CAPS_TIMESLICE_OVERRIDE_ENABLED + * Cap bit to indicate whether TSG timeslice override is enabled or not. + * When set true, TSG timeslice override is enabled. + * When false, TSG timeslice override is disabled. + * uvmEnabledFeatures + * This parameter returns mask of UVM enabled features on vGPU. It comprises of + * UVM managed APIs and replayable faults that are enabled or disabled based on + * vGPU version. + * enableKmdSysmemScratch + * This parameter is used to overwrite guest regkey PreferSystemMemoryScratch. + * Setting vgpu parameter "vgpu_enable_kmd_sysmem_scratch" in plugin will + * set this parameter. If the parameter is set, guest moves shader buffer + * allocation from FB to sysmem. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_UPPER_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_PIPELINED_SEMA_MEM_UPPER_OFFSET) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG (0xa0800301) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_OTHERS_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED 0:0 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CUDA_ENABLED 1:1 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CUDA_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CUDA_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_WDDM1_PREEMPTION_DISABLED 2:2 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_WDDM1_PREEMPTION_DISABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_WDDM1_PREEMPTION_DISABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED 3:3 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_ENABLED 4:4 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PDE_BLIT_ENABLED 5:5 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PDE_BLIT_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PDE_BLIT_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GET_PDE_INFO_CTRL_DISABLED 6:6 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GET_PDE_INFO_CTRL_DISABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GET_PDE_INFO_CTRL_DISABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_FB_OFFSET_DISABLED 7:7 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_FB_OFFSET_DISABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_FB_OFFSET_DISABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CILP_DISABLED_ON_WDDM 8:8 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CILP_DISABLED_ON_WDDM_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CILP_DISABLED_ON_WDDM_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_SEMAPHORE_DISABLED 9:9 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_SEMAPHORE_DISABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_SEMAPHORE_DISABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_UPDATE_DOORBELL_TOKEN_ENABLED 10:10 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_UPDATE_DOORBELL_TOKEN_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_UPDATE_DOORBELL_TOKEN_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED 11:11 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_MANAGED_VA_ENABLED 12:12 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_MANAGED_VA_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_MANAGED_VA_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_1TO1_COMPTAG_ENABLED 13:13 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_1TO1_COMPTAG_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_1TO1_COMPTAG_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_MBP_ENABLED 14:14 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_MBP_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_MBP_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_ASYNC_MBP_ENABLED 15:15 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_ASYNC_MBP_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_ASYNC_MBP_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TLB_INVALIDATE_ENABLED 16:16 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TLB_INVALIDATE_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TLB_INVALIDATE_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED 17:17 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED 18:18 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED 19:19 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED 20:20 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED_TRUE (0x00000001) + +/* UVM supported features */ +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED 0:0 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_API_ENABLED 1:1 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_API_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_API_ENABLED_TRUE (0x00000001) + +#define NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA080_CTRL_VGPU_GET_CONFIG_PARAMS { + NvU32 frameRateLimiter; + NvU32 swVSyncEnabled; + NvU32 cudaEnabled; + NvU32 pluginPteBlitEnabled; + NvU32 disableWddm1xPreemption; + NvU32 debugBufferSize; + NV_DECLARE_ALIGNED(NvP64 debugBuffer, 8); + NV_DECLARE_ALIGNED(NvU64 guestFbOffset, 8); + NV_DECLARE_ALIGNED(NvU64 mappableCpuHostAperture, 8); + NvU32 linuxInterruptOptimization; + NvU32 vgpuDeviceCapsBits; + NvU32 maxPixels; + NvU32 uvmEnabledFeatures; + NvBool enableKmdSysmemScratch; +} NVA080_CTRL_VGPU_GET_CONFIG_PARAMS; + + + +/* _ctrla080_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla081.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla081.h new file mode 100644 index 0000000..35876db --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla081.h @@ -0,0 +1,716 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla081.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl2080/ctrl2080gpu.h" +#include "nv_vgpu_types.h" +/* NVA081_VGPU_CONFIG control commands and parameters */ + +#define NVA081_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xA081, NVA081_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NVA081_CTRL_RESERVED (0x00) +#define NVA081_CTRL_VGPU_CONFIG (0x01) + +#define NVA081_CTRL_VGPU_CONFIG_INVALID_TYPE 0x00 +#define NVA081_MAX_VGPU_TYPES_PER_PGPU 0x40 +#define NVA081_MAX_VGPU_PER_PGPU 32 +#define NVA081_VM_UUID_SIZE 16 +#define NVA081_VGPU_STRING_BUFFER_SIZE 32 +#define NVA081_VGPU_SIGNATURE_SIZE 128 +#define NVA081_VM_NAME_SIZE 128 +#define NVA081_PCI_CONFIG_SPACE_SIZE 0x100 +#define NVA081_PGPU_METADATA_STRING_SIZE 256 +#define NVA081_EXTRA_PARAMETERS_SIZE 1024 + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_SET_INFO + * + * This command sets the vGPU config information in RM + * + * Parameters: + * + * discardVgpuTypes [IN] + * This parameter specifies if existing vGPU configuration should be + * discarded for given pGPU + * + * vgpuInfo [IN] + * This parameter specifies virtual GPU type information + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_SET_INFO (0xa0810101) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NVA081_CTRL_VGPU_CONFIG_INFO + * + * This structure represents the per vGPU information + * + */ +typedef struct NVA081_CTRL_VGPU_INFO { + // This structure should be in sync with NVA082_CTRL_CMD_HOST_VGPU_DEVICE_GET_VGPU_TYPE_INFO_PARAMS + NvU32 vgpuType; + NvU8 vgpuName[NVA081_VGPU_STRING_BUFFER_SIZE]; + NvU8 vgpuClass[NVA081_VGPU_STRING_BUFFER_SIZE]; + NvU8 vgpuSignature[NVA081_VGPU_SIGNATURE_SIZE]; + NvU8 license[NV_GRID_LICENSE_INFO_MAX_LENGTH]; + NvU32 maxInstance; + NvU32 numHeads; + NvU32 maxResolutionX; + NvU32 maxResolutionY; + NvU32 maxPixels; + NvU32 frlConfig; + NvU32 cudaEnabled; + NvU32 eccSupported; + NvU32 gpuInstanceSize; + NvU32 multiVgpuSupported; + NV_DECLARE_ALIGNED(NvU64 vdevId, 8); + NV_DECLARE_ALIGNED(NvU64 pdevId, 8); + NV_DECLARE_ALIGNED(NvU64 profileSize, 8); + NV_DECLARE_ALIGNED(NvU64 fbLength, 8); + NV_DECLARE_ALIGNED(NvU64 gspHeapSize, 8); + NV_DECLARE_ALIGNED(NvU64 fbReservation, 8); + NV_DECLARE_ALIGNED(NvU64 mappableVideoSize, 8); + NvU32 encoderCapacity; + NV_DECLARE_ALIGNED(NvU64 bar1Length, 8); + NvU32 frlEnable; + NvU8 adapterName[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + NvU16 adapterName_Unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + NvU8 shortGpuNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + NvU8 licensedProductName[NV_GRID_LICENSE_INFO_MAX_LENGTH]; + NvU32 vgpuExtraParams[NVA081_EXTRA_PARAMETERS_SIZE]; + NvU32 ftraceEnable; + NvU32 gpuDirectSupported; + NvU32 nvlinkP2PSupported; + NvU32 multiVgpuExclusive; + NvU32 exclusiveType; + NvU32 exclusiveSize; + // used only by NVML + NvU32 gpuInstanceProfileId; +} NVA081_CTRL_VGPU_INFO; + +/* + * NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS + * + * This structure represents the vGPU configuration information + * + */ +#define NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS { + NvBool discardVgpuTypes; + NV_DECLARE_ALIGNED(NVA081_CTRL_VGPU_INFO vgpuInfo, 8); + NvU32 vgpuConfigState; +} NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS; + +/* VGPU Config state values */ +#define NVA081_CTRL_VGPU_CONFIG_STATE_UNINITIALIZED 0 +#define NVA081_CTRL_VGPU_CONFIG_STATE_IN_PROGRESS 1 +#define NVA081_CTRL_VGPU_CONFIG_STATE_READY 2 + +/* + * NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU + * + * This command enumerates list of vGPU guest instances per pGpu + * + * Parameters: + * + * vgpuType [OUT] + * This parameter specifies the virtual GPU type for this physical GPU + * + * numVgpu [OUT] + * This parameter specifies the number of virtual GPUs created on this physical GPU + * + * guestInstanceInfo [OUT] + * This parameter specifies an array containing guest instance's information for + * all instances created on this physical GPU + * + * guestVgpuInfo [OUT] + * This parameter specifies an array containing guest vgpu's information for + * all vGPUs created on this physical GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU (0xa0810102) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID" */ + +/* + * NVA081_GUEST_VM_INFO + * + * This structure represents vGPU guest's (VM's) information + * + * vmPid [OUT] + * This param specifies the vGPU plugin process ID + * vmIdType [OUT] + * This param specifies the VM ID type, i.e. DOMAIN_ID or UUID + * guestOs [OUT] + * This param specifies the vGPU guest OS type + * migrationProhibited [OUT] + * This flag indicates whether migration is prohibited for VM or not + * guestNegotiatedVgpuVersion [OUT] + * This param specifies the vGPU version of guest driver after negotiation + * frameRateLimit [OUT] + * This param specifies the current value of FRL set for guest + * licensed [OUT] + * This param specifies whether the VM is Unlicensed/Licensed + * licenseState [OUT] + * This param specifies the current state of the GRID license state machine + * licenseExpiryTimestamp [OUT] + * License expiry time in seconds since UNIX epoch + * licenseExpiryStatus [OUT] + * License expiry status + * guestDriverVersion [OUT] + * This param specifies the driver version of the driver installed on the VM + * guestDriverBranch [OUT] + * This param specifies the driver branch of the driver installed on the VM + * vmName [OUT] + * This param stores the name assigned to VM (KVM only) + * guestVmInfoState [OUT] + * This param stores the current state of guest dependent fields + * + */ +typedef struct NVA081_GUEST_VM_INFO { + NvU32 vmPid; + VM_ID_TYPE vmIdType; + NvU32 guestOs; + NvU32 migrationProhibited; + NvU32 guestNegotiatedVgpuVersion; + NvU32 frameRateLimit; + NvBool licensed; + NvU32 licenseState; + NvU32 licenseExpiryTimestamp; + NvU8 licenseExpiryStatus; + NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); + NvU8 guestDriverVersion[NVA081_VGPU_STRING_BUFFER_SIZE]; + NvU8 guestDriverBranch[NVA081_VGPU_STRING_BUFFER_SIZE]; + NvU8 vmName[NVA081_VM_NAME_SIZE]; + GUEST_VM_INFO_STATE guestVmInfoState; +} NVA081_GUEST_VM_INFO; + +/* + * NVA081_GUEST_VGPU_DEVICE + * + * This structure represents host vgpu device's (assigned to VM) information + * + * eccState [OUT] + * This parameter specifies the ECC state of the virtual GPU. + * One of NVA081_CTRL_ECC_STATE_xxx values. + * bDriverLoaded [OUT] + * This parameter specifies whether driver is loaded on this particular vGPU. + * swizzId [OUT] + * This param specifies the GPU Instance ID or Swizz ID + * + */ +typedef struct NVA081_HOST_VGPU_DEVICE { + NvU32 vgpuType; + NvU32 vgpuDeviceInstanceId; + NV_DECLARE_ALIGNED(NvU64 vgpuPciId, 8); + NvU8 vgpuUuid[VM_UUID_SIZE]; + NvU8 mdevUuid[VM_UUID_SIZE]; + NvU32 encoderCapacity; + NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); + NvU32 eccState; + NvBool bDriverLoaded; + NvU32 swizzId; +} NVA081_HOST_VGPU_DEVICE; + +/* ECC state values */ +#define NVA081_CTRL_ECC_STATE_UNKNOWN 0 +#define NVA081_CTRL_ECC_STATE_NOT_SUPPORTED 1 +#define NVA081_CTRL_ECC_STATE_DISABLED 2 +#define NVA081_CTRL_ECC_STATE_ENABLED 3 + +/* + * NVA081_VGPU_GUEST + * + * This structure represents a vGPU guest + * + */ +typedef struct NVA081_VGPU_GUEST { + NV_DECLARE_ALIGNED(NVA081_GUEST_VM_INFO guestVmInfo, 8); + NV_DECLARE_ALIGNED(NVA081_HOST_VGPU_DEVICE vgpuDevice, 8); +} NVA081_VGPU_GUEST; + +/* + * NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS + * + * This structure represents the information of vGPU guest instances per pGpu + * + */ +#define NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS { + NvU32 vgpuType; + NvU32 numVgpu; + NV_DECLARE_ALIGNED(NVA081_VGPU_GUEST vgpuGuest[NVA081_MAX_VGPU_PER_PGPU], 8); +} NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_VGPU_TYPE_INFO + * + * This command fetches vGPU type info from RM. + * + * Parameters: + * + * vgpuType [IN] + * This parameter specifies the virtual GPU type for which vGPU info should be returned. + * + * vgpuTypeInfo [OUT] + * This parameter returns NVA081_CTRL_VGPU_INFO data for the vGPU type specified by vgpuType. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ + +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_VGPU_TYPE_INFO (0xa0810103) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS + * + */ +#define NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS { + NvU32 vgpuType; + NV_DECLARE_ALIGNED(NVA081_CTRL_VGPU_INFO vgpuTypeInfo, 8); +} NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS; + +/* + * NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS + * This structure represents supported/creatable vGPU types on a pGPU + */ +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS { + /* + * [OUT] vGPU config state on a pGPU + */ + NvU32 vgpuConfigState; + + /* + * [OUT] Count of supported/creatable vGPU types on a pGPU + */ + NvU32 numVgpuTypes; + + /* + * [OUT] - Array of vGPU type ids supported/creatable on a pGPU + */ + NvU32 vgpuTypes[NVA081_MAX_VGPU_TYPES_PER_PGPU]; +} NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS; + + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES + * + * This command fetches count and list of vGPU types supported on a pGpu from RM + * + * Parameters: + * + * numVgpuTypes [OUT] + * This parameter returns the number of vGPU types supported on this pGPU + * + * vgpuTypes [OUT] + * This parameter returns list of supported vGPUs types on this pGPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + */ + +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES (0xa0810104) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | 0x4" */ + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES + * + * This command fetches count and list of vGPU types creatable on a pGpu from RM + * + * Parameters: + * + * numVgpuTypes [OUT] + * This parameter returns the number of vGPU types creatable on this pGPU + * + * vgpuTypes [OUT] + * This parameter returns list of creatable vGPUs types on this pGPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + */ + +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES (0xa0810105) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | 0x5" */ + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_EVENT_SET_NOTIFICATION + * + * This command sets event notification state for the associated subdevice/pGPU. + * This command requires that an instance of NV01_EVENT has been previously + * bound to the associated subdevice object. + * + * event + * This parameter specifies the type of event to which the specified + * action is to be applied. This parameter must specify a valid + * NVA081_NOTIFIERS value (see cla081.h for more details) and should + * not exceed one less NVA081_NOTIFIERS_MAXCOUNT. + * action + * This parameter specifies the desired event notification action. + * Valid notification actions include: + * NVA081_CTRL_SET_EVENT_NOTIFICATION_DISABLE + * This action disables event notification for the specified + * event for the associated subdevice object. + * NVA081_CTRL_SET_EVENT_NOTIFICATION_SINGLE + * This action enables single-shot event notification for the + * specified event for the associated subdevice object. + * NVA081_CTRL_SET_EVENT_NOTIFICATION_REPEAT + * This action enables repeated event notification for the specified + * event for the associated system controller object. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_EVENT_SET_NOTIFICATION (0xa0810106) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS { + NvU32 event; + NvU32 action; +} NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS; + + +/* valid event action values */ +#define NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001) +#define NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002) + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_NOTIFY_START + * + * This command notifies the nvidia-vgpu-vfio module with start status. + * It notifies whether start has been successful or not. + * + * mdevUuid + * This parameter specifies the uuid of the mdev device for which start has + * been called. + * vmUuid + * The UUID of VM for which vGPU has been created. + * vmName + * The name of VM for which vGPU has been created. + * returnStatus + * This parameter species whether the vGPU plugin is initialized or not. + * it specifies the error code in case plugin initialization has failed + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_NOTIFY_START (0xa0810107) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS_MESSAGE_ID" */ + +/* + * NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS + * This structure represents information of plugin init status. + */ +#define NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS { + NvU8 mdevUuid[VM_UUID_SIZE]; + NvU8 vmUuid[VM_UUID_SIZE]; + NvU8 vmName[NVA081_VM_NAME_SIZE]; + NvU32 returnStatus; +} NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_MDEV_REGISTER + * + * This command register the GPU to Linux kernel's mdev module for vGPU on KVM. + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_MDEV_REGISTER (0xa0810109) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | 0x9" */ + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_SET_VGPU_INSTANCE_ENCODER_CAPACITY + * + * This command is used to set vGPU instance's (represented by vgpuUuid) encoder Capacity. + * + * vgpuUuid + * This parameter specifies the uuid of vGPU assigned to VM. + * encoderCapacity + * Encoder capacity value from 0 to 100. Value of 0x00 indicates encoder performance + * may be minimal for this GPU and software should fall back to CPU-based encode. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVA081_CTRL_CMD_VGPU_CONFIG_SET_VGPU_INSTANCE_ENCODER_CAPACITY (0xa0810110) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS_MESSAGE_ID" */ + +/* + * NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS + * + * This structure represents encoder capacity for vgpu instance. + */ +#define NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS { + NvU8 vgpuUuid[VM_UUID_SIZE]; + NvU32 encoderCapacity; +} NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_VGPU_FB_USAGE + * + * This command is used to get the FB usage of all vGPU instances running on a GPU. + * + * vgpuCount + * This field specifies the number of vGPU devices for which FB usage is returned. + * vgpuFbUsage + * This is an array of type NVA081_VGPU_FB_USAGE, which contains a list of vGPUs + * and their corresponding FB usage in bytes; + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_VGPU_FB_USAGE (0xa0810111) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID" */ + +typedef struct NVA081_VGPU_FB_USAGE { + NvU8 vgpuUuid[VM_UUID_SIZE]; + NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); +} NVA081_VGPU_FB_USAGE; + +/* + * NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS + * + * This structure represents the FB usage information of vGPU instances running on a GPU. + */ +#define NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS { + NvU32 vgpuCount; + NV_DECLARE_ALIGNED(NVA081_VGPU_FB_USAGE vgpuFbUsage[NVA081_MAX_VGPU_PER_PGPU], 8); +} NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP + * + * This command is used to query whether pGPU is live migration capable or not. + * + * bMigrationCap + * Set to NV_TRUE if pGPU is migration capable. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_REQUEST + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP (0xa0810112) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS_MESSAGE_ID" */ + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS { + NvBool bMigrationCap; +} NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_HOST_FB_RESERVATION + * + * This command is used to get the host FB requirements + * + * hostReservedFb [OUT] + * Amount of FB reserved for the host + * eccAndPrReservedFb [OUT] + * Amount of FB reserved for the ecc and page retirement + * totalReservedFb [OUT] + * Total FB reservation + * vgpuTypeId [IN] + * The Type ID for VGPU profile + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_HOST_FB_RESERVATION (0xa0810113) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS { + NV_DECLARE_ALIGNED(NvU64 hostReservedFb, 8); + NV_DECLARE_ALIGNED(NvU64 eccAndPrReservedFb, 8); + NV_DECLARE_ALIGNED(NvU64 totalReservedFb, 8); + NvU32 vgpuTypeId; +} NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_PGPU_METADATA_STRING + * + * This command is used to get the pGpu metadata string. + * + * pGpuString + * String holding pGpu Metadata + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_STATE + * NV_ERR_INSUFFICIENT_RESOURCES + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_PGPU_METADATA_STRING (0xa0810114) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS { + NvU8 pGpuString[NVA081_PGPU_METADATA_STRING_SIZE]; +} NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS; + +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT (0xa0810115) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS { + NvBool doorbellEmulationEnabled; +} NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_FREE_SWIZZID + * + * This command is used to get free swizzid from RM + * + * gpuPciId [IN] + * This param specifies the PCI device ID of VF on which VM is running + * + * vgpuTypeId [IN] + * This param specifies the Type ID for VGPU profile + * + * swizzId [OUT] + * This param specifies the GPU Instance ID or Swizz ID + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_FREE_SWIZZID (0xa0810116) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS { + NvU32 gpuPciId; + NvU32 vgpuTypeId; + NvU32 swizzId; +} NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS; + +/* + * NVA081_CTRL_CMD_PGPU_GET_MULTI_VGPU_SUPPORT_INFO + * + * This command is used to get multi vGPU related info for the physical GPU. + * + * fractionalmultiVgpuSupported [OUT] + * This param specifies whether fractional multi-vGPU is supported + * + * heterogeneousTimesliceProfilesSupported [OUT] + * This param specifies whether concurrent execution of timesliced vGPU profiles of differing types is supported + * + * heterogeneousTimesliceSizesSupported [OUT] + * This param specifies whether concurrent execution of timesliced vGPU profiles of differing framebuffer sizes is supported + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVA081_CTRL_CMD_PGPU_GET_MULTI_VGPU_SUPPORT_INFO (0xa0810117) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS_MESSAGE_ID (0x17U) + +typedef struct NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS { + NvU32 fractionalmultiVgpuSupported; + NvU32 heterogeneousTimesliceProfilesSupported; + NvU32 heterogeneousTimesliceSizesSupported; +} NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS; + +/* + * NVA081_CTRL_CMD_GET_VGPU_DRIVER_CAPS + * + * This command is used to get vGPU driver capabilities. + * + * heterogeneousMultiVgpuSupported [OUT] + * This param specifies whether heterogeneous multi-vGPU is supported + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVA081_CTRL_CMD_GET_VGPU_DRIVER_CAPS (0xa0810118) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS { + NvU32 heterogeneousMultiVgpuSupported; +} NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_SET_PGPU_INFO + * + * This command is to set pgpu info + * + * fractionalMultiVgpu [IN] + * This param specifies the fractional multivgpu is enabled or disabled on GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ + +#define NVA081_CTRL_CMD_VGPU_CONFIG_SET_PGPU_INFO (0xa0810119) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS { + NvU32 fractionalMultiVgpu; +} NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS; + +/* _ctrlA081vgpuconfig_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla084.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla084.h new file mode 100644 index 0000000..f5a5146 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla084.h @@ -0,0 +1,302 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla084.finn +// + +#include "nv_vgpu_types.h" +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl2080/ctrl2080gpu.h" // NV2080_GPU_MAX_GID_LENGTH +#include "ctrl/ctrl2080/ctrl2080fb.h" // NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES + +/* NVA084_KERNEL_HOST_VGPU_DEVICE control commands and parameters */ +#define NVA084_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xA084U, NVA084_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NVA084_CTRL_RESERVED (0x00) +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE (0x01) + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO + * + * This command sets the guest vgpu device's information + * + * Parameter: + * + * vgpuUuid [IN] + * This parameter specifies the universaly unique identifier of the guest vGPU device + * + * vgpuDeviceInstanceId [IN] + * This parameter specifies the vGPU device instance + * + * Possible status values returned are: + * NV_OK + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO (0xa0840101) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS { + NvU8 vgpuUuid[NV2080_GPU_MAX_GID_LENGTH]; + NvU32 vgpuDeviceInstanceId; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS; + +/* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE + * + * This command triggers the notifier for vGPU guest. + * + * Parameters: + * + * vmLifeCycleState[IN] + * The life cycle event of the vGPU guest. This can be: + * NVA081_NOTIFIERS_EVENT_VGPU_GUEST_DESTROYED + * NVA081_NOTIFIERS_EVENT_VGPU_GUEST_CREATED + * + * Possible status values returned are: + * NV_OK + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE (0xa0840102) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS { + NvU32 vmLifeCycleState; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS; + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO + * + * This command is used to copy offlined page mapping info from plugin to host vgpu device + * + * guestFbSegmentPageSize [in] + * Guest FB segment page size + * + * offlinedPageCount [in] + * Offlined page count in the guest FB range + * + * gpa [in] + * This array represents guest page address list of offlined page + * + * hMemory [in] + * This array represents memory handle list of good page + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO (0xa0840103) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS { + NvU32 guestFbSegmentPageSize; + NvU32 offlinedPageCount; + NV_DECLARE_ALIGNED(NvU64 gpa[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES], 8); + NvHandle hMemory[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES]; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS; + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS + * + * Config space access for the virtual function + * + * Parameters: + * + * offset [IN] + * Offset within the config space + * + * numBytes [IN] + * Number of bytes to be read/written: 1/2/4 + * + * accessType [IN] + * To indicate whether it is a read operation or a write operation + * + * value [INOUT] + * Value to be read or written + * + * Possible status values returned are: + * NV_OK + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS (0xa0840104) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_VF_CONFIG_SPACE_ACCESS_TYPE_READ 0x1 +#define NVA084_CTRL_VF_CONFIG_SPACE_ACCESS_TYPE_WRITE 0x2 + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS { + NvU16 offset; + NvU8 numBytes; + NvU8 accessType; + NvU32 value; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS; + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF + * + * This command is used to create a bind-point on a host system + * for the collection of guest VM FECS events + * + * hEventBufferClient[IN] + * The client of the event buffer to bind to + * + * hEventBufferSubdevice[IN] + * The subdevice of the event buffer to bind to + * + * hEventBuffer[IN] + * The event buffer to bind to + * + * reasonCode[OUT] + * The reason for failure (if any); see NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF (0xa0840105) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS { + NvHandle hEventBufferClient; + NvHandle hEventBufferSubdevice; + NvHandle hEventBuffer; + NvU32 reasonCode; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS; + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL + * + * The command will trigger the specified interrupt on the host from CPU Plugin. + * + * handle[IN] + * - An opaque handle that will be passed in along with the interrupt + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL (0xa0840106) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS { + NvU32 handle; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS; + +/* valid action values */ +#define NVA084_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NVA084_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001) +#define NVA084_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002) + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION + * + * This command sets event notification state for the associated host vgpu device. + * This command requires that an instance of NV01_EVENT has been previously + * bound to the associated host vgpu device object. + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION (0xa0840107) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS { + // + // @todo: We will define the actual event values later based on the use case. + // These event values are only for Test purpose. + // + NvU32 event; + NvU32 action; + NvBool bNotifyState; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS; + +/* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE + * + * This command is used to set SRIOV state parameters in RM. + * + * Parameters: + * + * numPluginChannels [IN] + * Number of channels required by plugin + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE (0xa0840108) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_MAX_PLUGIN_CHANNELS 5 + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS { + NvU32 numPluginChannels; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS; + +/* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID + * + * This command is used to set/unset VM ID parameters in host vgpu device in RM. + * + * Parameters: + * + * action + * This parameter specifies the desired set guest id action. + * Valid set guest id actions include: + * NVA084_CTRL_HOST_VGPU_DEVICE_KERNEL_SET_GUEST_ID_ACTION_SET + * This action sets the VM ID information in host vgpu device. + * NVA084_CTRL_HOST_VGPU_DEVICE_KERNEL_SET_GUEST_ID_ACTION_UNSET + * This action unsets the VM ID information in host vgpu device. + * vmPid [IN] + * VM process ID + * vmIdType[IN] + * VM ID type whether it's UUID or DOMAIN_ID + * guestVmId[IN] + * VM ID + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID (0xa0840109) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS { + NvU8 action; + NvU32 vmPid; + VM_ID_TYPE vmIdType; + NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS; + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_ACTION_SET (0x00000000) +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_ACTION_UNSET (0x00000001) + +/* _ctrla084_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla16f.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla16f.h new file mode 100644 index 0000000..7cf7069 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla16f.h @@ -0,0 +1,200 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla16f.finn +// + + + + +/* GK100_GPFIFO control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrla06f.h" /* A16F is partially derived from A06F */ +#include "ctrl/ctrl906f.h" /* A16F is partially derived from 906F */ +#define NVA16F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xA16F, NVA16F_CTRL_##cat, idx) + +/* GK100_GPFIFO command categories (6bits) */ +#define NVA16F_CTRL_RESERVED (0x00) +#define NVA16F_CTRL_GPFIFO (0x01) +#define NVA16F_CTRL_EVENT (0x02) + +/* + * NVA16F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVA16F_CTRL_CMD_NULL (0xa16f0000) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NVA16F_CTRL_GET_CLASS_ENGINEID + * + * Please see description of NVA06F_CTRL_GET_CLASS_ENGINEID for more information. + * + */ +#define NVA16F_CTRL_GET_CLASS_ENGINEID (0xa16f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x1" */ + +typedef NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS NVA16F_CTRL_GET_CLASS_ENGINEID_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA16F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA16F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS { + NVA16F_CTRL_GET_CLASS_ENGINEID_PARAMS params; +} NVA16F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS; + + + +/* + * NVA16F_CTRL_RESET_CHANNEL + * + * Please see description of NVA06F_CTRL_RESET_CHANNEL for more information. + * + */ +#define NVA16F_CTRL_CMD_RESET_CHANNEL (0xa16f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x2" */ +typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA16F_CTRL_CMD_RESET_CHANNEL_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA16F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVA16F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS { + NVA16F_CTRL_CMD_RESET_CHANNEL_PARAMS params; +} NVA16F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS; + + + +/* + * NVA16F_CTRL_CMD_GPFIFO_SCHEDULE + * + * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. + * + */ +#define NVA16F_CTRL_CMD_GPFIFO_SCHEDULE (0xa16f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x3" */ +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA16F_CTRL_GPFIFO_SCHEDULE_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA16F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVA16F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS { + NVA16F_CTRL_GPFIFO_SCHEDULE_PARAMS params; +} NVA16F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS; + + + +/* + * NVA16F_CTRL_CMD_BIND + * + * Please see description of NVA06F_CTRL_CMD_BIND for more information. + */ +#define NVA16F_CTRL_CMD_BIND (0xa16f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x4" */ + +typedef NVA06F_CTRL_BIND_PARAMS NVA16F_CTRL_BIND_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA16F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVA16F_CTRL_CMD_BIND_FINN_PARAMS { + NVA16F_CTRL_BIND_PARAMS params; +} NVA16F_CTRL_CMD_BIND_FINN_PARAMS; + + + +/* + * NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. +*/ +#define NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa16f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID << 8) | 0x5" */ + +typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVA16F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS { + NVA16F_CTRL_EVENT_SET_NOTIFICATION_PARAMS params; +} NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS; + + + +/* valid action values */ +#define NVA16F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE +#define NVA16F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE +#define NVA16F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT + +/* + * NVA16F_CTRL_CMD_EVENT_SET_TRIGGER + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information. + */ +#define NVA16F_CTRL_CMD_EVENT_SET_TRIGGER (0xa16f0206) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID << 8) | 0x6" */ + + + + + +/* + * NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO + * + * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. + * + */ +#define NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa16f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x7" */ + +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA16F_CTRL_GET_MMU_FAULT_INFO_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS { + NV_DECLARE_ALIGNED(NVA16F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8); +} NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS; + + + +/* _ctrla16f.h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla26f.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla26f.h new file mode 100644 index 0000000..6dcf930 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrla26f.h @@ -0,0 +1,200 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla26f.finn +// + + + + +/* GK20A_GPFIFO control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrla06f.h" /* A26F is partially derived from A06F */ +#include "ctrl/ctrl906f.h" /* A26F is partially derived from 906F */ +#define NVA26F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xA26F, NVA26F_CTRL_##cat, idx) + +/* GK20A_GPFIFO command categories (6bits) */ +#define NVA26F_CTRL_RESERVED (0x00) +#define NVA26F_CTRL_GPFIFO (0x01) +#define NVA26F_CTRL_EVENT (0x02) + +/* + * NVA26F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVA26F_CTRL_CMD_NULL (0xa26f0000) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NVA26F_CTRL_GET_CLASS_ENGINEID + * + * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. + * + */ +#define NVA26F_CTRL_GET_CLASS_ENGINEID (0xa26f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x1" */ + +typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVA26F_CTRL_GET_CLASS_ENGINEID_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA26F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA26F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS { + NVA26F_CTRL_GET_CLASS_ENGINEID_PARAMS params; +} NVA26F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS; + + + +/* + * NVA26F_CTRL_RESET_CHANNEL + * + * Please see description of NVA06F_CTRL_CMD_RESET_CHANNEL for more information. + * + */ +#define NVA26F_CTRL_CMD_RESET_CHANNEL (0xa26f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x2" */ +typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA26F_CTRL_CMD_RESET_CHANNEL_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA26F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVA26F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS { + NVA26F_CTRL_CMD_RESET_CHANNEL_PARAMS params; +} NVA26F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS; + + + +/* + * NVA26F_CTRL_CMD_GPFIFO_SCHEDULE + * + * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. + * + */ +#define NVA26F_CTRL_CMD_GPFIFO_SCHEDULE (0xa26f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x3" */ +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA26F_CTRL_GPFIFO_SCHEDULE_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA26F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVA26F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS { + NVA26F_CTRL_GPFIFO_SCHEDULE_PARAMS params; +} NVA26F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS; + + + +/* + * NVA26F_CTRL_CMD_BIND + * + * Please see description of NVA06F_CTRL_CMD_BIND for more information. + */ +#define NVA26F_CTRL_CMD_BIND (0xa26f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x4" */ + +typedef NVA06F_CTRL_BIND_PARAMS NVA26F_CTRL_BIND_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA26F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVA26F_CTRL_CMD_BIND_FINN_PARAMS { + NVA26F_CTRL_BIND_PARAMS params; +} NVA26F_CTRL_CMD_BIND_FINN_PARAMS; + + + +/* + * NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. +*/ +#define NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa26f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID << 8) | 0x5" */ + +typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVA26F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS { + NVA26F_CTRL_EVENT_SET_NOTIFICATION_PARAMS params; +} NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS; + + + +/* valid action values */ +#define NVA26F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE +#define NVA26F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE +#define NVA26F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT + +/* + * NVA26F_CTRL_CMD_EVENT_SET_TRIGGER + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information. + */ +#define NVA26F_CTRL_CMD_EVENT_SET_TRIGGER (0xa26f0206) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID << 8) | 0x6" */ + + + + + +/* + * NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO + * + * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. + * + */ +#define NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa26f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x7" */ + +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA26F_CTRL_GET_MMU_FAULT_INFO_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS { + NV_DECLARE_ALIGNED(NVA26F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8); +} NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS; + + + +/* _ctrla26f.h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlb069.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlb069.h new file mode 100644 index 0000000..66eb26d --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlb069.h @@ -0,0 +1,180 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlb069.finn +// + +#include "ctrl/ctrlxxxx.h" +/* MAXWELL_FAULT_BUFFER_A control commands and parameters */ + +#define NVB069_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xB069, NVB069_CTRL_##cat, idx) + +/* MAXWELL_FAULT_BUFFER_A command categories (6bits) */ +#define NVB069_CTRL_RESERVED (0x00) +#define NVB069_CTRL_FAULTBUFFER (0x01) + +/* + * NVB069_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVB069_CTRL_CMD_NULL (0xb0690000) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + + +/* + * NVB069_CTRL_CMD_FAULTBUFFER_READ_GET + * + * This command returns the current HW GET pointer for the requested type fault buffer + * + * faultBufferGetOffset + * Value of current HW GET pointer + * faultBufferType + * Type of fault buffer. FAULT_BUFFER_REPLAYABLE or FAULT_BUFFER_NON_REPLAYABLE + */ +#define NVB069_CTRL_CMD_FAULTBUFFER_READ_GET (0xb0690101) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_FAULTBUFFER_READ_GET_PARAMS_MESSAGE_ID" */ + +#define NVB069_CTRL_FAULTBUFFER_READ_GET_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVB069_CTRL_FAULTBUFFER_READ_GET_PARAMS { + NvU32 faultBufferGetOffset; + NvU32 faultBufferType; +} NVB069_CTRL_FAULTBUFFER_READ_GET_PARAMS; + +// +// Valid Fault buffer Types +// NON_REPLAYABLE is only supported in Volta+ GPUs. +// +#define NVB069_CTRL_FAULT_BUFFER_NON_REPLAYABLE (0x00000000) +#define NVB069_CTRL_FAULT_BUFFER_REPLAYABLE (0x00000001) + +/* + * NVB069_CTRL_CMD_FAULTBUFFER_WRITE_GET + * + * This command writes the HW GET pointer for the requested type of fault buffer + * + * NOTE: The caller must issue a write barrier before this function to + * ensure modifications to the current buffer entry are committed before + * the GET pointer is updated. + * + * faultBufferGetOffset + * Value to be written to HW GET pointer + * faultBufferType + * Type of fault buffer. FAULT_BUFFER_REPLAYABLE or FAULT_BUFFER_NON_REPLAYABLE + */ +#define NVB069_CTRL_CMD_FAULTBUFFER_WRITE_GET (0xb0690102) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_FAULTBUFFER_WRITE_GET_PARAMS_MESSAGE_ID" */ + +#define NVB069_CTRL_FAULTBUFFER_WRITE_GET_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVB069_CTRL_FAULTBUFFER_WRITE_GET_PARAMS { + NvU32 faultBufferGetOffset; + NvU32 faultBufferType; +} NVB069_CTRL_FAULTBUFFER_WRITE_GET_PARAMS; + +/* + * NVB069_CTRL_CMD_FAULTBUFFER_READ_PUT + * + * This command returns the current HW PUT pointer for the requested type fault buffer + * + * faultBufferGetOffset + * Value of current HW PUT pointer + * faultBufferType + * Type of fault buffer. FAULT_BUFFER_REPLAYABLE or FAULT_BUFFER_NON_REPLAYABLE + */ +#define NVB069_CTRL_CMD_FAULTBUFFER_READ_PUT (0xb0690103) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_FAULTBUFFER_READ_PUT_PARAMS_MESSAGE_ID" */ + +#define NVB069_CTRL_FAULTBUFFER_READ_PUT_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVB069_CTRL_FAULTBUFFER_READ_PUT_PARAMS { + NvU32 faultBufferPutOffset; + NvU32 faultBufferType; +} NVB069_CTRL_FAULTBUFFER_READ_PUT_PARAMS; + +#define NVB069_CTRL_CMD_FAULTBUFFER_ENABLE_NOTIFICATION (0xb0690104) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_FAULTBUFFER_ENABLE_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NVB069_CTRL_FAULTBUFFER_ENABLE_NOTIFICATION_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVB069_CTRL_FAULTBUFFER_ENABLE_NOTIFICATION_PARAMS { + NvBool Enable; +} NVB069_CTRL_FAULTBUFFER_ENABLE_NOTIFICATION_PARAMS; + +#define NVB069_CTRL_CMD_FAULTBUFFER_GET_SIZE (0xb0690105) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_FAULTBUFFER_GET_SIZE_PARAMS_MESSAGE_ID" */ + +#define NVB069_CTRL_FAULTBUFFER_GET_SIZE_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVB069_CTRL_FAULTBUFFER_GET_SIZE_PARAMS { + NvU32 faultBufferSize; +} NVB069_CTRL_FAULTBUFFER_GET_SIZE_PARAMS; + + +/* + * NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS + * + * This command provides kernel mapping to a few registers. + * These mappings are needed by UVM driver to handle non fatal gpu faults + * + * pFaultBufferGet + * Mapping for fault buffer's get pointer (NV_PFIFO_REPLAYABLE_FAULT_BUFFER_GET) + * pFaultBufferPut + * Mapping for fault buffer's put pointer (NV_PFIFO_REPLAYABLE_FAULT_BUFFER_PUT) + * pFaultBufferInfo + * Mapping for fault buffer's Info pointer (NV_PFIFO_REPLAYABLE_FAULT_BUFFER_INFO) + * Note: this variable is deprecated since buffer overflow is not a seperate register from Volta + * pPmcIntr + * Mapping for PMC intr register (NV_PMC_INTR(0)) + * pPmcIntrEnSet + * Mapping for PMC intr set register - used to enable an intr (NV_PMC_INTR_EN_SET(0)) + * pPmcIntrEnClear + * Mapping for PMC intr clear register - used to disable an intr (NV_PMC_INTR_EN_CLEAR(0)) + * replayableFaultMask + * Mask for the replayable fault bit(NV_PMC_INTR_REPLAYABLE_FAULT) + */ +#define NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS (0xb0690106) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS_MESSAGE_ID" */ + +#define NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pFaultBufferGet, 8); + NV_DECLARE_ALIGNED(NvP64 pFaultBufferPut, 8); + NV_DECLARE_ALIGNED(NvP64 pFaultBufferInfo, 8); + NV_DECLARE_ALIGNED(NvP64 pPmcIntr, 8); + NV_DECLARE_ALIGNED(NvP64 pPmcIntrEnSet, 8); + NV_DECLARE_ALIGNED(NvP64 pPmcIntrEnClear, 8); + NvU32 replayableFaultMask; + NV_DECLARE_ALIGNED(NvP64 pPrefetchCtrl, 8); +} NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS; + +/* _ctrlb069_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlb06f.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlb06f.h new file mode 100644 index 0000000..14a6199 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlb06f.h @@ -0,0 +1,527 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlb06f.finn +// + + + + +/* MAXWELL_CHANNEL_GPFIFO_A control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrla06f.h" /* B06F is partially derived from A06F */ +#include "ctrl/ctrl906f.h" /* B06F is partially derived from 906F */ +#define NVB06F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xB06F, NVB06F_CTRL_##cat, idx) + +/* MAXWELL_CHANNEL_GPFIFO_A command categories (6bits) */ +#define NVB06F_CTRL_RESERVED (0x00) +#define NVB06F_CTRL_GPFIFO (0x01) +#define NVB06F_CTRL_EVENT (0x02) + +/* + * NVB06F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVB06F_CTRL_CMD_NULL (0xb06f0000) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NVB06F_CTRL_GET_CLASS_ENGINEID + * + * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. + * + */ +#define NVB06F_CTRL_GET_CLASS_ENGINEID (0xb06f0101) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */ + +typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVB06F_CTRL_GET_CLASS_ENGINEID_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVB06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVB06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS { + NVB06F_CTRL_GET_CLASS_ENGINEID_PARAMS params; +} NVB06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS; + + + +/* + * NVB06F_CTRL_RESET_CHANNEL + * + * Please see description of NVA06F_CTRL_RESET_CHANNEL for more information. + * + */ +#define NVB06F_CTRL_CMD_RESET_CHANNEL (0xb06f0102) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */ + +typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVB06F_CTRL_CMD_RESET_CHANNEL_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVB06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVB06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS { + NVB06F_CTRL_CMD_RESET_CHANNEL_PARAMS params; +} NVB06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS; + + + +/* + * NVB06F_CTRL_CMD_GPFIFO_SCHEDULE + * + * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. + * + */ +#define NVB06F_CTRL_CMD_GPFIFO_SCHEDULE (0xb06f0103) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */ + +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVB06F_CTRL_GPFIFO_SCHEDULE_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVB06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVB06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS { + NVB06F_CTRL_GPFIFO_SCHEDULE_PARAMS params; +} NVB06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS; + + + +/* + * NVB06F_CTRL_CMD_BIND + * + * Please see description of NVA06F_CTRL_CMD_BIND for more information. + */ +#define NVB06F_CTRL_CMD_BIND (0xb06f0104) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */ + +typedef NVA06F_CTRL_BIND_PARAMS NVB06F_CTRL_BIND_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVB06F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVB06F_CTRL_CMD_BIND_FINN_PARAMS { + NVB06F_CTRL_BIND_PARAMS params; +} NVB06F_CTRL_CMD_BIND_FINN_PARAMS; + + + +/* + * NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. +*/ +#define NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xb06f0205) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x5" */ + +typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVB06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS { + NVB06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS params; +} NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS; + + + +/* valid action values */ +#define NVB06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE +#define NVB06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE +#define NVB06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT + +/* + * NVB06F_CTRL_CMD_EVENT_SET_TRIGGER + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information. + */ +#define NVB06F_CTRL_CMD_EVENT_SET_TRIGGER (0xb06f0206) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */ + + + + + +/* + * NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO + * + * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. + * + */ +#define NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xb06f0107) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */ + +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVB06F_CTRL_GET_MMU_FAULT_INFO_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS { + NV_DECLARE_ALIGNED(NVB06F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8); +} NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS; + + + +/* + * NVB06F_CTRL_CMD_GET_ENGINE_CTX_SIZE + * + * This command returns the size of the engine context. + * + * engineID + * This parameter specifies the engine context size to be retrieved. + * + * See the description of the NV2080_ENGINE_TYPE values in cl2080.h for more + * information + * + * size + * This parameter returns the size of the engine context + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVB06F_CTRL_CMD_GET_ENGINE_CTX_SIZE (0xb06f010b) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GET_ENGINE_CTX_SIZE_PARAMS_MESSAGE_ID" */ + +#define NVB06F_CTRL_GET_ENGINE_CTX_SIZE_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NVB06F_CTRL_GET_ENGINE_CTX_SIZE_PARAMS { + NvU32 engineID; + NvU32 size; +} NVB06F_CTRL_GET_ENGINE_CTX_SIZE_PARAMS; + +/* + * NVB06F_CTRL_CMD_GET_ENGINE_CTX_DATA + * + * This command returns the context buffer data for the given engine for vGPU motion. + * + * engineID + * This parameter specifies the engine context to be retrieved. + * + * See the description of the NV2080_ENGINE_TYPE values in cl2080.h for + * more information + * + * size + * This parameter specifies the size of the context buffer. + * + * pEngineCtxBuff + * This parameter specifies the context buffer for motion operation to be filled in. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ + +#define NVB06F_CTRL_CMD_GET_ENGINE_CTX_DATA (0xb06f010c) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID" */ + +typedef struct SW_OBJECT_ENGINE_CTX { + NvU32 hObject; + NvU32 subCh; +} SW_OBJECT_ENGINE_CTX; + +#define NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS { + NvU32 engineID; + NvU32 size; + NV_DECLARE_ALIGNED(NvP64 pEngineCtxBuff, 8); +} NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS; + +/* + * NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA + * + * This command restores the context buffer for the given engine for vGPU motion. + * + * engineID + * This parameter specifies the engine context to be restored. + * + * See the description of the NV2080_ENGINE_TYPE values in cl2080.h for + * more information + * + * size + * This parameter specifies the size of the context buffer. + * + * pEngineCtxBuff + * This parameter specifies the context buffer for motion operation restore. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ + +#define NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA (0xb06f010d) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS_MESSAGE_ID" */ + +typedef NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS { + NV_DECLARE_ALIGNED(NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS params, 8); +} NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS; + + + +/* + * NVB06F_CTRL_CMD_GET_ENGINE_CTX_STATE + * + * This command returns the context buffer state of the given engine for vGPU motion. + * + * engineID + * This input parameter specifies the engine context to be restored. + * + * See the description of the NV2080_ENGINE_TYPE values in cl2080.h for + * more information + * + * hObject + * This parameter specifies the channel object that is running on the SW engine. + * + * engineCtxState + * This parameter specifies the engine context state. For SW engine, the only meaningful + * field is INVALID, INITIALIZED and the subch. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ + +#define NVB06F_CTRL_CMD_GET_ENGINE_CTX_STATE (0xb06f010e) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GET_ENGINE_CTX_STATE_PARAMS_MESSAGE_ID" */ + +#define NVB06F_CTRL_GET_ENGINE_CTX_STATE_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NVB06F_CTRL_GET_ENGINE_CTX_STATE_PARAMS { + NvU32 engineID; + NvU32 hObject; + NvU32 engineCtxState; +} NVB06F_CTRL_GET_ENGINE_CTX_STATE_PARAMS; + +#define NVB06F_CTRL_GET_ENGINE_CTX_VIRTUAL_CONTEXT 0:0 +#define NVB06F_CTRL_GET_ENGINE_CTX_VIRTUAL_CONTEXT_DISABLED (0x00000000) +#define NVB06F_CTRL_GET_ENGINE_CTX_VIRTUAL_CONTEXT_ENABLED (0x00000001) +#define NVB06F_CTRL_GET_ENGINE_CTX_STATE 2:1 +#define NVB06F_CTRL_GET_ENGINE_CTX_STATE_INVALID (0x00000000) +#define NVB06F_CTRL_GET_ENGINE_CTX_STATE_INITIALIZED (0x00000001) +#define NVB06F_CTRL_GET_ENGINE_CTX_STATE_PROMOTED (0x00000002) +#define NVB06F_CTRL_GET_ENGINE_CTX_STATE_EVICTED (0x00000003) +#define NVB06F_CTRL_GET_ENGINE_CTX_SUBCH 6:4 + +/* + * NVB06F_CTRL_CMD_GET_CHANNEL_HW_STATE + * + * This command returns the channel HW state. + * + * state + * This parameter stores single bit-fields corresponding to the following + * channel HW states: + * NEXT + * A value of NV_TRUE indicates that this channel should be scheduled + * first when GPU Host chooses this TSG to run next on the runlist. + * + * CTX_RELOAD + * A value of NV_TRUE indicates that this channel's context was + * preempted and needs to be reloaded. + * + * PENDING + * A value of NV_TRUE indicates that this channel is not loaded on the + * PBDMA but methods still remain. This includes the completion of + * semaphores acquires and WFI methods. This field is deprecated + * from Volta onwards, and can be ignored. + * + * ENG_FAULTED + * A value of NV_TRUE indicates that the channel's engine has faulted, + * and the channel will not be rescheduled until the fault has been + * cleared. This bit should only be set as part of migration, and will + * not necessarily cause the channel to be prevented from being + * scheduled. + * + * PBDMA_FAULTED + * A value of NV_TRUE indicates that the channel's PBDMA has faulted, + * and the channel will not be rescheduled until the fault has been + * cleared. This bit should only be set as part of migration, and will + * not necessarily cause the channel to be prevented from being + * scheduled. + * + * ACQUIRE_FAIL + * A value of NV_TRUE indicates that the engine scheduler failed to + * acquire a semaphore for this channel. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ +#define NVB06F_CTRL_CMD_GET_CHANNEL_HW_STATE (0xb06f010f) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS_MESSAGE_ID" */ + +#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_NEXT 0:0 +#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_CTX_RELOAD 1:1 +#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_PENDING 2:2 +#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_ENG_FAULTED 3:3 +#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_PBDMA_FAULTED 4:4 +#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_ACQUIRE_FAIL 5:5 + +#define NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS { + NvU32 state; +} NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS; + +/* + * NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE + * + * This command restores the channel HW state. + * + * state + * This parameter stores single bit-fields corresponding to the following + * channel HW states: + * NEXT + * A value of NV_TRUE indicates that this channel should be scheduled + * first when GPU Host chooses this TSG to run next on the runlist. + * + * CTX_RELOAD + * A value of NV_TRUE indicates that this channel's context was + * preempted and needs to be reloaded. + * + * PENDING + * A value of NV_TRUE indicates that this channel is not loaded on the + * PBDMA but methods still remain. This includes the completion of + * semaphores acquires and WFI methods. This field is deprecated + * from Volta onwards, and can be ignored. + * + * ENG_FAULTED + * A value of NV_TRUE indicates that the channel's engine has faulted, + * and the channel will not be rescheduled until the fault has been + * cleared. This bit should only be set as part of migration, and will + * not necessarily cause the channel to be prevented from being + * scheduled. + * + * PBDMA_FAULTED + * A value of NV_TRUE indicates that the channel's PBDMA has faulted, + * and the channel will not be rescheduled until the fault has been + * cleared. This bit should only be set as part of migration, and will + * not necessarily cause the channel to be prevented from being + * scheduled. + * + * ACQUIRE_FAIL + * A value of NV_TRUE indicates that the engine scheduler failed to + * acquire a semaphore for this channel. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ +#define NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE (0xb06f0110) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x10" */ + +typedef NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE_FINN_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE_FINN_PARAMS { + NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS params; +} NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE_FINN_PARAMS; + +/* + * NVB06F_CTRL_CMD_SAVE_ENGINE_CTX_DATA + * + * This command returns the context buffer data for the given engine for vGPU migration. + * + * engineID + * This parameter specifies the engine context to be retrieved. + * + * See the description of the NV2080_ENGINE_TYPE values in cl2080.h for + * more information + * + * size + * This parameter specifies the size of the context buffer. The maximum size + * of engine context buffer is choosen to support only RAMFC and instance + * memory block. To use this RmCtrl for a higher sized buffer, like the GR + * context, the max size would have to be increased. + * + * engineCtxBuff + * This parameter specifies the context buffer data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ + +#define NVB06F_CTRL_CMD_SAVE_ENGINE_CTX_DATA (0xb06f0111) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID" */ + +#define NVB06F_CTRL_ENGINE_CTX_BUFFER_SIZE_MAX 4096 + +#define NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS { + NvU32 engineID; + NvU32 size; + NvU8 engineCtxBuff[NVB06F_CTRL_ENGINE_CTX_BUFFER_SIZE_MAX]; +} NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS; + +/* + * NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA + * + * This command restores the context buffer for the given engine for vGPU migration. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ + +#define NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA (0xb06f0112) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS_MESSAGE_ID" */ + +typedef NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS NVB06F_CTRL_RESTORE_ENGINE_CTX_DATA_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS { + NVB06F_CTRL_RESTORE_ENGINE_CTX_DATA_PARAMS params; +} NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS; + + + +/* _ctrlb06f.h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlb0cc.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlb0cc.h new file mode 100644 index 0000000..decc79a --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlb0cc.h @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlb0cc.finn +// + + + + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl2080/ctrl2080gpu.h" // NV2080_CTRL_GPU_REG_OP +#include "ctrlb0cc/ctrlb0ccprofiler.h" +#include "ctrlb0cc/ctrlb0ccinternal.h" diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h new file mode 100644 index 0000000..a6d2929 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlb0cc/ctrlb0ccbase.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl2080/ctrl2080gpu.h" // NV2080_CTRL_GPU_REG_OP +#define NVB0CC_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xB0CC, NVB0CC_CTRL_##cat, idx) + +/* MAXWELL_PROFILER command categories (6 bits) */ +#define NVB0CC_CTRL_RESERVED (0x00) +#define NVB0CC_CTRL_PROFILER (0x01) +#define NVB0CC_CTRL_INTERNAL (0x02) + +/*! + * NVB0CC_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVB0CC_CTRL_CMD_NULL (0xb0cc0000) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + +/* _ctrlb0ccbase_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h new file mode 100644 index 0000000..54e2dbd --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h @@ -0,0 +1,79 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlb0cc/ctrlb0ccinternal.finn +// + +#include "ctrl/ctrlb0cc/ctrlb0ccbase.h" + +#include "ctrl/ctrlb0cc/ctrlb0ccprofiler.h" /* Some controls derivative of b0ccprofiler */ +/*! + * @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM + */ +#define NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM (0xb0cc0200) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS_MESSAGE_ID" */ + + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS_MESSAGE_ID (0x0U) + +typedef struct NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS { + NV_DECLARE_ALIGNED(NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS params, 8); +} NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS; + + + +/*! + * NVB0CC_CTRL_CMD_INTERNAL_PERMISSIONS_INIT + * + * This command is used to convey the client permissions for appropriate + * profiling capability initialization + */ +#define NVB0CC_CTRL_CMD_INTERNAL_PERMISSIONS_INIT (0xb0cc0203) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS { + /*! + * [in] Is Admin profiling permitted + */ + NvBool bAdminProfilingPermitted; + /*! + * [in] Is Device profiling permitted + */ + NvBool bDevProfilingPermitted; + + /*! + * [in] Is Memory profiling permitted + */ + NvBool bMemoryProfilingPermitted; +} NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS; + +/* _ctrlb0ccinternal_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h new file mode 100644 index 0000000..d456c63 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h @@ -0,0 +1,479 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlb0cc/ctrlb0ccprofiler.finn +// + +#include "ctrl/ctrlb0cc/ctrlb0ccbase.h" + + +/*! + * NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY + * + * Reserves the HWPM legacy PM system for use by the calling client. + * This PM system will only be accessible if this reservation is + * taken. + * + * If a device level reservation is held by another client, then this command + * will fail regardless of reservation scope. + * + * This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_HWPM_LEGACY. + * + */ + + +#define NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY (0xb0cc0101) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS { + /*! + * [in] Enable ctxsw for HWPM. + */ + NvBool ctxsw; +} NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_RELEASE_HWPM_LEGACY + * + * Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY. + * + * This command does not take any parameters. + * + */ +#define NVB0CC_CTRL_CMD_RELEASE_HWPM_LEGACY (0xb0cc0102) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x2" */ + +/*! + * NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC + * + * Reserves the SMPC PM system for use by the calling client. + * This PM system will only be accessible if this reservation is + * taken. + * + * Reservation scope and rules are same as for @ref NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY. + * + * This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_PM_AREA_SMPC. + * + */ +#define NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC (0xb0cc0103) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS { + /*! + * [in] Enable ctxsw for SMPC. + */ + NvBool ctxsw; +} NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_RELEASE_PM_AREA_SMPC + * + * Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC. + * + * This command does not take any parameters. + * + */ +#define NVB0CC_CTRL_CMD_RELEASE_PM_AREA_SMPC (0xb0cc0104) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x4" */ + +/*! + * NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM + * + * Allocates PMA VA and map it to the buffers for streaming records and for + * for streaming the updated bytes available in the buffer. + * + */ +#define NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM (0xb0cc0105) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x5" */ + +/*! + * Defines the maximum size of PMA buffer for streamout. It can be up to 4GB minus one page + * reserved for streaming mem_bytes (see @ref NVB0CC_PMA_BYTES_AVAILABLE_SIZE). + */ +#define NVB0CC_PMA_BUFFER_SIZE_MAX (0xffe00000ULL) /* finn: Evaluated from "(4 * 1024 * 1024 * 1024 - 2 * 1024 * 1024)" */ +#define NVB0CC_PMA_BYTES_AVAILABLE_SIZE (0x1000) /* finn: Evaluated from "(4 * 1024)" */ + +typedef struct NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS { + /*! + * [in] Memory handle (RW memory) for streaming records. + * Size of this must be >= @ref pmaBufferOffset + @ref pmaBufferSize. + */ + NvHandle hMemPmaBuffer; + + /*! + * [in] Start offset of PMA buffer (offset in @ref hMemPmaBuffer). + */ + NV_DECLARE_ALIGNED(NvU64 pmaBufferOffset, 8); + + /*! + * [in] size of the buffer. This must be <= NVB0CC_PMA_BUFFER_SIZE_MAX. + */ + NV_DECLARE_ALIGNED(NvU64 pmaBufferSize, 8); + + /*! + * [in] Memory handle (RO memory) for streaming number of bytes available. + * Size of this must be of at least @ref pmaBytesAvailableOffset + + * @ref NVB0CC_PMA_BYTES_AVAILABLE_SIZE. + */ + NvHandle hMemPmaBytesAvailable; + + /*! + * [in] Start offset of PMA bytes available buffer (offset in @ref hMemPmaBytesAvailable). + */ + NV_DECLARE_ALIGNED(NvU64 pmaBytesAvailableOffset, 8); + + /*! + * [in] Enable ctxsw for PMA stream. + */ + NvBool ctxsw; + + /*! + * [out] The PMA Channel Index associated with a given PMA stream. + */ + NvU32 pmaChannelIdx; + + /*! + * [out] PMA buffer VA. Note that this is a HWPM Virtual address. + */ + NV_DECLARE_ALIGNED(NvU64 pmaBufferVA, 8); +} NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_FREE_PMA_STREAM + * + * Releases (unmap and free) PMA stream allocated through + * @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM. + * + */ +#define NVB0CC_CTRL_CMD_FREE_PMA_STREAM (0xb0cc0106) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS { + /*! + * [in] The PMA channel index associated with a given PMA stream. + */ + NvU32 pmaChannelIdx; +} NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_BIND_PM_RESOURCES + * + * Binds all PM resources reserved through @ref NVB0CC_CTRL_CMD_RESERVE_* + * and with @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM with PMA engine. + * After this call, interface is ready for programming a collection + * of counters. + * @Note: Any new PM resource reservation via NVB0CC_CTRL_CMD_RESERVE_* or + * @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM request after this call will fail, + * clients need to unbind (see @ref NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES) to + * reserve more resources. + * + * This can be unbound with @ref NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES. + * + */ +#define NVB0CC_CTRL_CMD_BIND_PM_RESOURCES (0xb0cc0107) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x7" */ + +/*! + * NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES + * + * Unbinds PM resources that were bound with @ref NVB0CC_CTRL_CMD_BIND_PM_RESOURCES + * + */ +#define NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES (0xb0cc0108) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x8" */ + +/*! + * NVB0CC_CTRL_CMD_PMA_STREAM_UPDATE_GET_PUT + * + * This command updates bytes consumed by the SW and optionally gets the + * current available bytes in the buffer. + * + */ +#define NVB0CC_CTRL_CMD_PMA_STREAM_UPDATE_GET_PUT (0xb0cc0109) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_AVAILABLE_BYTES_DEFAULT_VALUE 0xFFFFFFFF +#define NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS { + /*! + * [in] Total bytes consumed by SW since last update. + */ + NV_DECLARE_ALIGNED(NvU64 bytesConsumed, 8); + + /*! + * [in] Initiate streaming of the bytes available (see @ref hMemPmaBytesAvailable). + * RM will set the memory for streaming (see @ref hMemPmaBytesAvailable) to NVB0CC_AVAILABLE_BYTES_DEFAULT_VALUE and + * client can optionally wait (see @ref bWait) for it to change from this value. + */ + NvBool bUpdateAvailableBytes; + + /*! + * [in] Waits for available bytes to get updated + */ + NvBool bWait; + + /*! + * [out] Bytes available in the PMA buffer (see @ref hMemPmaBuffer) for SW to consume. + * This will only be populated if both bUpdateAvailableBytes and bWait are set + * to TRUE. + */ + NV_DECLARE_ALIGNED(NvU64 bytesAvailable, 8); + + /*! + * [in] If set to TRUE, current put pointer will be returned in @ref putPtr. + */ + NvBool bReturnPut; + + /*! + * [out] Current PUT pointer (MEM_HEAD). + * This will only be populated if bReturnPut is set to TRUE. + */ + NV_DECLARE_ALIGNED(NvU64 putPtr, 8); + + /*! + * [in] The PMA Channel Index associated with a given PMA stream. + */ + NvU32 pmaChannelIdx; +} NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS; + +/*! + * Maximum number of register operations allowed in a single request. + * @NOTE: @ref NVB0CC_REGOPS_MAX_COUNT is chosen to keep struct size + * of @ref NVB0CC_CTRL_EXEC_REG_OPS_PARAMS under 4KB. + */ +#define NVB0CC_REGOPS_MAX_COUNT (124) + +/*! + * NVB0CC_CTRL_CMD_EXEC_REG_OPS + * + * This command is used to submit an array containing one or more + * register operations for processing. Each entry in the + * array specifies a single read or write operation. Each entry is + * checked for validity in the initial pass: Only registers from PM area + * are allowed using this interface and only register from PM systems for + * which user has a valid reservation are allowed (see @ref NVB0CC_CTRL_CMD_RESERVE_*). + * Operation type (@ref NV2080_CTRL_GPU_REG_OP_TYPE_*) is not required to be passed in. + */ +#define NVB0CC_CTRL_CMD_EXEC_REG_OPS (0xb0cc010a) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_MESSAGE_ID" */ + +/*! + * Structure definition for register operation. See @ref NV2080_CTRL_GPU_REG_OP. + */ +typedef NV2080_CTRL_GPU_REG_OP NVB0CC_GPU_REG_OP; + +/*! + * Enumeration of different REG_OPS modes. This mode determines how a failure + * of a regop is handled in a batch of regops. + */ +typedef enum NVB0CC_REGOPS_MODE { + + /*! + * Either all regops will be executed or none of them will be executed. + * Failing regop will have the appropriate status (see @ref NVB0CC_GPU_REG_OP::regStatus). + */ + NVB0CC_REGOPS_MODE_ALL_OR_NONE = 0, + /*! + * All regops will be attempted and the ones that failed will have the + * the appropriate status (see @ref NVB0CC_GPU_REG_OP::regStatus). + */ + NVB0CC_REGOPS_MODE_CONTINUE_ON_ERROR = 1, +} NVB0CC_REGOPS_MODE; + +#define NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NVB0CC_CTRL_EXEC_REG_OPS_PARAMS { + /*! + * [in] Number of valid entries in the regOps array. This value cannot + * exceed NVB0CC_REGOPS_MAX_COUNT. + */ + NvU32 regOpCount; + + /*! + * [in] Specifies the mode for the entire operation see @ref NVB0CC_REGOPS_MODE. + */ + NVB0CC_REGOPS_MODE mode; + + /*! + * [out] Provides status for the entire operation. This is only valid for + * mode @ref NVB0CC_REGOPS_MODE_CONTINUE_ON_ERROR. + */ + NvBool bPassed; + + /*! + * [out] This is currently not populated. + */ + NvBool bDirect; + + /*! + * [in/out] An array (of fixed size NVB0CC_REGOPS_MAX_COUNT) of register read or write + * operations (see @ref NVB0CC_GPU_REG_OP) + * + */ + NVB0CC_GPU_REG_OP regOps[NVB0CC_REGOPS_MAX_COUNT]; +} NVB0CC_CTRL_EXEC_REG_OPS_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_RESERVE_PM_AREA_PC_SAMPLER + * + * Reserves the PC sampler system for use by the calling client. + * + * This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_PM_AREA_PC_SAMPLER. + * + * This command does not take any parameters. + * + * PC sampler is always context switched with a GR context, so reservation scope is + * always context. This requires that profiler object is instantiated with a valid GR + * context. See @ref NVB2CC_ALLOC_PARAMETERS. + */ + +#define NVB0CC_CTRL_CMD_RESERVE_PM_AREA_PC_SAMPLER (0xb0cc010b) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0xB" */ + +/*! + * NVB0CC_CTRL_CMD_RELEASE_PM_AREA_PC_SAMPLER + * + * Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_PM_AREA_PC_SAMPLER. + * + * This command does not take any parameters. + * + */ +#define NVB0CC_CTRL_CMD_RELEASE_PM_AREA_PC_SAMPLER (0xb0cc010c) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0xC" */ + +/*! + * NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS + * + * Gets the total high speed streaming credits available for the client. + * + * This command can only be performed after a bind using NVB0CC_CTRL_CMD_BIND_PM_RESOURCES. + * + */ +#define NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS (0xb0cc010d) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS { + NvU32 numCredits; +} NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_SET_HS_CREDITS_CHIPLET + * + * Sets per chiplet (pmm router) credits for high speed streaming for a pma channel. + * + * @note: This command resets the current credits to 0 before setting the new values also + * if programming fails, it will reset credits to 0 for all the chiplets. + * + */ +#define NVB0CC_CTRL_CMD_SET_HS_CREDITS (0xb0cc010e) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_MESSAGE_ID" */ + +typedef enum NVB0CC_CHIPLET_TYPE { + NVB0CC_CHIPLET_TYPE_INVALID = 0, + NVB0CC_CHIPLET_TYPE_FBP = 1, + NVB0CC_CHIPLET_TYPE_GPC = 2, + NVB0CC_CHIPLET_TYPE_SYS = 3, +} NVB0CC_CHIPLET_TYPE; + +typedef enum NVB0CC_HS_CREDITS_CMD_STATUS { + NVB0CC_HS_CREDITS_CMD_STATUS_OK = 0, + /*! + * More credits are requested than the total credits. Total credits can be queried using @ref NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS + */ + NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CREDITS = 1, + /*! + * Chiplet index is invalid. + */ + NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CHIPLET = 2, +} NVB0CC_HS_CREDITS_CMD_STATUS; + +typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO { + /*! + * Specifies the chiplet type @ref NVB0CC_CHIPLET_TYPE. + */ + NvU8 chipletType; + + /*! + * Specifies the logical index of the chiplet. + */ + NvU8 chipletIndex; + + /*! + * Specifies the number of credits for the chiplet. + */ + NvU16 numCredits; +} NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO; + +typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS { + /*! + * Status for the command @ref NVB0CC_HS_CREDITS_CMD_STATUS. + */ + NvU8 status; + + /*! + * Index of the failing @ref NVB0CC_CTRL_SET_HS_CREDITS_PARAMS::creditInfo entry. This + * is only relevant if status is NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CHIPLET. + */ + NvU8 entryIndex; +} NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS; + +#define NVB0CC_MAX_CREDIT_INFO_ENTRIES (63) + +#define NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NVB0CC_CTRL_SET_HS_CREDITS_PARAMS { + /*! + * [in] The PMA Channel Index associated with a given PMA stream. + */ + NvU8 pmaChannelIdx; + + /*! + * [in] Number of valid entries in creditInfo. + */ + NvU8 numEntries; + + /*! + * [out] Provides status for the entire operation. + */ + NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS statusInfo; + + /*! + * [in] Credit programming per chiplet + */ + NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO creditInfo[NVB0CC_MAX_CREDIT_INFO_ENTRIES]; +} NVB0CC_CTRL_SET_HS_CREDITS_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_GET_HS_CREDITS + * + * Gets per chiplet (pmm router) high speed streaming credits for a pma channel. + * + */ +#define NVB0CC_CTRL_CMD_GET_HS_CREDITS (0xb0cc010f) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0xF" */ + +typedef NVB0CC_CTRL_SET_HS_CREDITS_PARAMS NVB0CC_CTRL_GET_HS_CREDITS_PARAMS; + + + +/* _ctrlb0ccprofiler_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc06f.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc06f.h new file mode 100644 index 0000000..1b493c7 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc06f.h @@ -0,0 +1,200 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc06f.finn +// + + + + +/* PASCAL_CHANNEL_GPFIFO_A control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrla06f.h" /* C06F is partially derived from A06F */ +#include "ctrl/ctrl906f.h" /* C06F is partially derived from 906F */ +#define NVC06F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xC06F, NVC06F_CTRL_##cat, idx) + +/* PASCAL_CHANNEL_GPFIFO_B command categories (6bits) */ +#define NVC06F_CTRL_RESERVED (0x00) +#define NVC06F_CTRL_GPFIFO (0x01) +#define NVC06F_CTRL_EVENT (0x02) + +/* + * NVC06F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVC06F_CTRL_CMD_NULL (0xc06f0000) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NVC06F_CTRL_GET_CLASS_ENGINEID + * + * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. + * + */ +#define NVC06F_CTRL_GET_CLASS_ENGINEID (0xc06f0101) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */ + +typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC06F_CTRL_GET_CLASS_ENGINEID_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVC06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS { + NVC06F_CTRL_GET_CLASS_ENGINEID_PARAMS params; +} NVC06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS; + + + +/* + * NVC06F_CTRL_RESET_CHANNEL + * + * Please see description of NVA06F_CTRL_RESET_CHANNEL for more information. + * + */ +#define NVC06F_CTRL_CMD_RESET_CHANNEL (0xc06f0102) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */ +typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC06F_CTRL_CMD_RESET_CHANNEL_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVC06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVC06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS { + NVC06F_CTRL_CMD_RESET_CHANNEL_PARAMS params; +} NVC06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS; + + + +/* + * NVC06F_CTRL_CMD_GPFIFO_SCHEDULE + * + * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. + * + */ +#define NVC06F_CTRL_CMD_GPFIFO_SCHEDULE (0xc06f0103) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */ +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC06F_CTRL_GPFIFO_SCHEDULE_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVC06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVC06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS { + NVC06F_CTRL_GPFIFO_SCHEDULE_PARAMS params; +} NVC06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS; + + + +/* + * NVC06F_CTRL_CMD_BIND + * + * Please see description of NVA06F_CTRL_CMD_BIND for more information. + */ +#define NVC06F_CTRL_CMD_BIND (0xc06f0104) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */ + +typedef NVA06F_CTRL_BIND_PARAMS NVC06F_CTRL_BIND_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVC06F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVC06F_CTRL_CMD_BIND_FINN_PARAMS { + NVC06F_CTRL_BIND_PARAMS params; +} NVC06F_CTRL_CMD_BIND_FINN_PARAMS; + + + +/* + * NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. +*/ +#define NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xc06f0205) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x5" */ + +typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS { + NVC06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS params; +} NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS; + + + +/* valid action values */ +#define NVC06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE +#define NVC06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE +#define NVC06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT + +/* + * NVC06F_CTRL_CMD_EVENT_SET_TRIGGER + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information. + */ +#define NVC06F_CTRL_CMD_EVENT_SET_TRIGGER (0xc06f0206) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */ + + + + + +/* + * NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO + * + * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. + * + */ +#define NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xc06f0107) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */ + +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC06F_CTRL_GET_MMU_FAULT_INFO_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS { + NV_DECLARE_ALIGNED(NVC06F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8); +} NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS; + + + +/* _ctrlc06f.h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc365.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc365.h new file mode 100644 index 0000000..fc23e13 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc365.h @@ -0,0 +1,331 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc365.finn +// + +#include "ctrl/ctrlxxxx.h" +#define NVC365_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xC365, NVC365_CTRL_##cat, idx) + + +#define NVC365_CTRL_RESERVED (0x00) +#define NVC365_CTRL_ACCESS_CNTR_BUFFER (0x01) + + +/* + * NVC365_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVC365_CTRL_CMD_NULL (0xc3650000) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_READ_GET + * + * This command provides the value of the GET register + * + * accessCntrBufferGetOffset [OUT] + * This parameter returns the value of the GET register + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_READ_GET (0xc3650101) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_GET_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_GET_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_GET_PARAMS { + NvU32 accessCntrBufferGetOffset; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_GET_PARAMS; + + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_WRITE_GET + * + * This command writes a value into the GET register + * + * accessCntrBufferGetValue [IN] + * This parameter specifies the new value of the GET register + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_WRITE_GET (0xc3650102) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_WRITE_GET_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_WRITE_GET_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_WRITE_GET_PARAMS { + NvU32 accessCntrBufferGetValue; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_WRITE_GET_PARAMS; + + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_READ_PUT + * + * This command provides the value of the PUT register + * + * accessCntrBufferPutOffset [OUT] + * This parameter returns the value of the PUT register + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_READ_PUT (0xc3650103) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_PUT_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_PUT_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_PUT_PARAMS { + NvU32 accessCntrBufferPutOffset; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_PUT_PARAMS; + + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_ENABLE + * + * This command enables/disables the access counters + * It also sets up RM to either service or ignore the Access Counter interrupts. + * + * intrOwnership [IN] + * This parameter specifies whether RM should own the interrupt upon return + * enable [IN] + * NV_TRUE = Access counters will be enabled + * NV_FALSE = Access counters will be disabled + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_ENABLE (0xc3650104) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_PARAMS { + NvU32 intrOwnership; + NvBool enable; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_PARAMS; + +#define NVC365_CTRL_ACCESS_COUNTER_INTERRUPT_OWNERSHIP_NO_CHANGE (0x0) +#define NVC365_CTRL_ACCESS_COUNTER_INTERRUPT_OWNERSHIP_RM (0x1) +#define NVC365_CTRL_ACCESS_COUNTER_INTERRUPT_OWNERSHIP_NOT_RM (0x2) + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_SIZE + * + * This command provides the size of the notification buffer + * + * accessCntrBufferSize [OUT] + * This parameter returns the size of the notification buffer + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_SIZE (0xc3650105) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_SIZE_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_SIZE_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_SIZE_PARAMS { + NvU32 accessCntrBufferSize; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_SIZE_PARAMS; + + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS + * + * This command provides the access counter register mappings + * + * pAccessCntrBufferGet [OUT] + * This parameter returns the pointer to the GET register + * pAccessCntrBufferPut [OUT] + * This parameter returns the pointer to the PUT register + * pAccessCntrlBufferFull [OUT] + * This parameter returns the pointer to the FULL register + * pHubIntr [OUT] + * This parameter returns the pointer to the hub interrupt register + * pHubIntrEnSet [OUT] + * This parameter returns the pointer to the set register + * pHubIntrEnClear [OUT] + * This parameter returns the pointer to the clear register + * accessCntrMask [OUT] + * This parameter returns the interrupt mask + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS (0xc3650106) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pAccessCntrBufferGet, 8); + NV_DECLARE_ALIGNED(NvP64 pAccessCntrBufferPut, 8); + NV_DECLARE_ALIGNED(NvP64 pAccessCntrBufferFull, 8); + NV_DECLARE_ALIGNED(NvP64 pHubIntr, 8); + NV_DECLARE_ALIGNED(NvP64 pHubIntrEnSet, 8); + NV_DECLARE_ALIGNED(NvP64 pHubIntrEnClear, 8); + NvU32 accessCntrMask; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS_PARAMS; + + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_FULL_INFO + * + * This command gives information whether the buffer is full + * + * fullFlag [OUT] + * This parameter specifies whether the buffer is full + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_FULL_INFO (0xc3650107) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_FULL_INFO_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_FULL_INFO_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_FULL_INFO_PARAMS { + NvBool fullFlag; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_FULL_INFO_PARAMS; + + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_RESET_COUNTERS + * + * This command resets access counters of specified type + * + * resetFlag [OUT] + * This parameter specifies that counters have been reset + * counterType [IN] + * This parameter specifies the type of counters that should be reset (MIMC, MOMC or ALL) + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_RESET_COUNTERS (0xc3650108) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_RESET_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_RESET_COUNTERS_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_RESET_COUNTERS_PARAMS { + NvBool resetFlag; + NvU32 counterType; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_RESET_COUNTERS_PARAMS; + +#define NVC365_CTRL_ACCESS_COUNTER_TYPE_MIMC (0x0) +#define NVC365_CTRL_ACCESS_COUNTER_TYPE_MOMC (0x1) +#define NVC365_CTRL_ACCESS_COUNTER_TYPE_ALL (0x2) + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_SET_CONFIG + * + * This command configures the access counters + * + * mimcGranularity [IN] + * This parameter specifies the desired granularity for mimc (64K, 2M, 16M, 16G) + * momcGranularity [IN] + * This parameter specifies the desired granularity for momc (64K, 2M, 16M, 16G) + * mimcLimit [IN] + * This parameter specifies mimc limit (none, qtr, half, full) + * momcLimit [IN] + * This parameter specifies momc limit (none, qtr, half, full) + * threshold [IN] + * This parameter specifies the threshold + * flag [IN] + * This parameter is a bitmask denoting what configurations should be made + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_SET_CONFIG (0xc3650109) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_SET_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_SET_CONFIG_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_SET_CONFIG_PARAMS { + NvU32 mimcGranularity; + NvU32 momcGranularity; + NvU32 mimcLimit; + NvU32 momcLimit; + NvU32 threshold; + NvU32 cmd; +} NVC365_CTRL_ACCESS_CNTR_SET_CONFIG_PARAMS; + +#define NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_64K (0x0) +#define NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_2M (0x1) +#define NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_16M (0x2) +#define NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_16G (0x3) + +#define NVC365_CTRL_ACCESS_COUNTER_MIMC_LIMIT (0x0) +#define NVC365_CTRL_ACCESS_COUNTER_MOMC_LIMIT (0x1) + +#define NVC365_CTRL_ACCESS_COUNTER_USE_LIMIT_NONE (0x0) +#define NVC365_CTRL_ACCESS_COUNTER_USE_LIMIT_QTR (0x1) +#define NVC365_CTRL_ACCESS_COUNTER_USE_LIMIT_HALF (0x2) +#define NVC365_CTRL_ACCESS_COUNTER_USE_LIMIT_FULL (0x3) + +#define NVC365_CTRL_ACCESS_COUNTER_SET_MIMC_GRANULARITY (0x1) +#define NVC365_CTRL_ACCESS_COUNTER_SET_MOMC_GRANULARITY (0x2) +#define NVC365_CTRL_ACCESS_COUNTER_SET_MIMC_LIMIT (0x4) +#define NVC365_CTRL_ACCESS_COUNTER_SET_MOMC_LIMIT (0x8) +#define NVC365_CTRL_ACCESS_COUNTER_SET_THRESHOLD (0x10) + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_ENABLE_INTR + * + * This command enables the access counters interrupts + * + * enable [OUT] + * This parameter specifies that the access counters interrupts are enabled + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_ENABLE_INTR (0xc365010b) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_INTR_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_INTR_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_INTR_PARAMS { + NvBool enable; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_INTR_PARAMS; +/* _ctrlc365_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc369.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc369.h new file mode 100644 index 0000000..135de33 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc369.h @@ -0,0 +1,109 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc369.finn +// + +#include "ctrl/ctrlxxxx.h" +/* MMU_FAULT_BUFFER control commands and parameters */ + +#define NVC369_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xC369, NVC369_CTRL_##cat, idx) + +/* MMU_FAULT_BUFFER command categories (6bits) */ +#define NVC369_CTRL_RESERVED (0x00) +#define NVC369_CTRL_MMU_FAULT_BUFFER (0x01) + +/* + * NVC369_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVC369_CTRL_CMD_NULL (0xc3690000) /* finn: Evaluated from "(FINN_MMU_FAULT_BUFFER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + + +/* + * NVC369_CTRL_CMD_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUFFER + * + * This call creates and registers a client buffer for the non replayable faults + * + * pShadowBuffer [OUT] + * This parameter represents the pointer to the shadow buffer + * + * pShadowBufferContext [OUT] + * Execution context for pShadowBuffer queue + * + * bufferSize [OUT] + * Size in bytes of the shadow buffer for non replayable faults + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC369_CTRL_CMD_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF (0xc3690101) /* finn: Evaluated from "(FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER_INTERFACE_ID << 8) | NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF_PARAMS_MESSAGE_ID" */ + +#define NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pShadowBuffer, 8); + NV_DECLARE_ALIGNED(NvP64 pShadowBufferContext, 8); + NvU32 bufferSize; +} NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF_PARAMS; + + +/* + * NVC369_CTRL_CMD_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUFFER + * + * This call unregisters and destroys a client buffer for the non replayable + * faults + * + * pShadowBuffer [IN] + * This parameter represents the pointer to the shadow buffer + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVC369_CTRL_CMD_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF (0xc3690102) /* finn: Evaluated from "(FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER_INTERFACE_ID << 8) | NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS_MESSAGE_ID" */ + +#define NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pShadowBuffer, 8); +} NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS; + +/* _ctrlc369_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc36f.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc36f.h new file mode 100644 index 0000000..ddfce20 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc36f.h @@ -0,0 +1,275 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc36f.finn +// + + + + +/* VOLTA_CHANNEL_GPFIFO_A control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl906f.h" /* C36F is partially derived from 906F */ +#include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */ +#define NVC36F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xC36F, NVC36F_CTRL_##cat, idx) + +/* VOLTA_CHANNEL_GPFIFO_A command categories (6bits) */ +#define NVC36F_CTRL_RESERVED (0x00) +#define NVC36F_CTRL_GPFIFO (0x01) +#define NVC36F_CTRL_EVENT (0x02) + +/* + * NVC36F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned is: NV_OK +*/ +#define NVC36F_CTRL_CMD_NULL (0xc36f0000) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + + +/* + * NVC36F_CTRL_GET_CLASS_ENGINEID + * + * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. + * + */ +#define NVC36F_CTRL_GET_CLASS_ENGINEID (0xc36f0101) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */ + +typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC36F_CTRL_GET_CLASS_ENGINEID_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVC36F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC36F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS { + NVC36F_CTRL_GET_CLASS_ENGINEID_PARAMS params; +} NVC36F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS; + + + +/* + * NVC36F_CTRL_RESET_CHANNEL + * + * Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information. + * + */ +#define NVC36F_CTRL_CMD_RESET_CHANNEL (0xc36f0102) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */ + +typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC36F_CTRL_CMD_RESET_CHANNEL_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVC36F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVC36F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS { + NVC36F_CTRL_CMD_RESET_CHANNEL_PARAMS params; +} NVC36F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS; + + + +/* + * NVC36F_CTRL_CMD_GPFIFO_SCHEDULE + * + * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. + * + */ +#define NVC36F_CTRL_CMD_GPFIFO_SCHEDULE (0xc36f0103) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */ + +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC36F_CTRL_GPFIFO_SCHEDULE_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVC36F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVC36F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS { + NVC36F_CTRL_GPFIFO_SCHEDULE_PARAMS params; +} NVC36F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS; + + + +/* + * NVC36F_CTRL_CMD_BIND + * + * Please see description of NVA06F_CTRL_CMD_BIND for more information. + */ +#define NVC36F_CTRL_CMD_BIND (0xc36f0104) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */ + +typedef NVA06F_CTRL_BIND_PARAMS NVC36F_CTRL_BIND_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVC36F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVC36F_CTRL_CMD_BIND_FINN_PARAMS { + NVC36F_CTRL_BIND_PARAMS params; +} NVC36F_CTRL_CMD_BIND_FINN_PARAMS; + + + +/* + * NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. +*/ +#define NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xc36f0205) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x5" */ + +typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC36F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NVC36F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE +#define NVC36F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE +#define NVC36F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT + +/* + * NVC36F_CTRL_CMD_EVENT_SET_TRIGGER + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information. + */ +#define NVC36F_CTRL_CMD_EVENT_SET_TRIGGER (0xc36f0206) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */ + + + + + +/* + * NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO + * + * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. + * + */ +#define NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO (0xc36f0107) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */ + +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC36F_CTRL_GET_MMU_FAULT_INFO_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS { + NV_DECLARE_ALIGNED(NVC36F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8); +} NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS; + + + +/* + * NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN + * + * This command returns an opaque work submit token to the caller which + * can be used to write to doorbell register to finish submitting work. If + * the client has provided an error context handle during channel allocation, + * and the error context is large enough to write the doorbell token, a + * notification at index NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN + * will be sent with the work submit token value. This index may be modified + * by NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX. + * + * workSubmitToken The 32-bit work submit token + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + * + */ + +#define NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN (0xc36f0108) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID" */ + +#define NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS { + NvU32 workSubmitToken; +} NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS; + +/** + * NVC36F_CTRL_CMD_GPFIFO_UPDATE_FAULT_METHOD_BUFFER + * + * This command updates the HOST CE Fault method buffer + * data structure of Virtual channel created for SR-IOV guest. It will also + * update the fault method buffer address in the instance block of the channel + * + * bar2Addr[] + * Array contains the Virtual BAR2 address mapped by the Guest during channel + * creation. + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_INSUFFICIENT_RESOURCES + * + */ +#define NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES 0x2 +#define NVC36F_CTRL_CMD_GPFIFO_UPDATE_FAULT_METHOD_BUFFER (0xc36f0109) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS_MESSAGE_ID" */ + +#define NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS { + NV_DECLARE_ALIGNED(NvU64 bar2Addr[NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES], 8); +} NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS; + +/* + * NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX + * + * This command updates the notifier index within the error context notifier + * to write the doorbell token to. This interface cannot be used to cause the + * token to overwrite the RC notification slot. The notification slot + * referred to by the passed index must be within the bounds of the error + * context notifier object. In the case that multiple channels share the same + * error context, it is not illegal for the client to set the same index for + * multiple channels (however it is not recommended). + * + * [IN] index + * Notification slot to write the doorbell token. The initial value of this + * index is NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX (0xc36f010a) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_MESSAGE_ID" */ + +#define NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS { + NvU32 index; +} NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS; + +/* _ctrlc36f.h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc370/ctrlc370base.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc370/ctrlc370base.h new file mode 100644 index 0000000..c132cc0 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc370/ctrlc370base.h @@ -0,0 +1,67 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc370/ctrlc370base.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NVC370_DISPLAY control commands and parameters */ + +#define NVC370_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0XC370, NVC370_CTRL_##cat, idx) + +/* NVC370_DISPLAY command categories (6bits) */ +#define NVC370_CTRL_RESERVED (0x00) +#define NVC370_CTRL_CHNCTL (0x01) +#define NVC370_CTRL_RG (0x02) +#define NVC370_CTRL_SEQ (0x03) +#define NVC370_CTRL_OR (0x04) +#define NVC370_CTRL_INST (0x05) +#define NVC370_CTRL_VERIF (0x06) +#define NVC370_CTRL_SYSTEM (0x07) +#define NVC370_CTRL_EVENT (0x09) + +// This struct must be the first member of all C370 control calls +typedef struct NVC370_CTRL_CMD_BASE_PARAMS { + NvU32 subdeviceIndex; +} NVC370_CTRL_CMD_BASE_PARAMS; + + +/* + * NVC370_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVC370_CTRL_CMD_NULL (0xc3700000) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + +/* _ctrlc370base_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h new file mode 100644 index 0000000..a231232 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h @@ -0,0 +1,300 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc370/ctrlc370chnc.finn +// + +#include "ctrl/ctrlc370/ctrlc370base.h" +/* C370 is partially derived from 5070 */ +#include "ctrl/ctrl5070/ctrl5070chnc.h" + + + + +#define NVC370_CTRL_CMD_CHANNEL_STATE_IDLE NVBIT(0) +#define NVC370_CTRL_CMD_CHANNEL_STATE_QUIESCENT1 NVBIT(2) +#define NVC370_CTRL_CMD_CHANNEL_STATE_QUIESCENT2 NVBIT(3) +#define NVC370_CTRL_CMD_CHANNEL_STATE_BUSY NVBIT(6) +#define NVC370_CTRL_CMD_CHANNEL_STATE_DEALLOC NVBIT(7) +#define NVC370_CTRL_CMD_CHANNEL_STATE_DEALLOC_LIMBO NVBIT(8) +#define NVC370_CTRL_CMD_CHANNEL_STATE_EFI_INIT1 NVBIT(11) +#define NVC370_CTRL_CMD_CHANNEL_STATE_EFI_INIT2 NVBIT(12) +#define NVC370_CTRL_CMD_CHANNEL_STATE_EFI_OPERATION NVBIT(13) +#define NVC370_CTRL_CMD_CHANNEL_STATE_VBIOS_INIT1 NVBIT(14) +#define NVC370_CTRL_CMD_CHANNEL_STATE_VBIOS_INIT2 NVBIT(15) +#define NVC370_CTRL_CMD_CHANNEL_STATE_VBIOS_OPERATION NVBIT(16) +#define NVC370_CTRL_CMD_CHANNEL_STATE_UNCONNECTED NVBIT(17) +#define NVC370_CTRL_CMD_CHANNEL_STATE_INIT1 NVBIT(18) +#define NVC370_CTRL_CMD_CHANNEL_STATE_INIT2 NVBIT(19) +#define NVC370_CTRL_CMD_CHANNEL_STATE_SHUTDOWN1 NVBIT(20) +#define NVC370_CTRL_CMD_CHANNEL_STATE_SHUTDOWN2 NVBIT(21) + +#define NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CORE 1 +#define NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW 32 +#define NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW_IMM 32 +#define NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WRITEBACK 8 +#define NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CURSOR 8 + +/* + * NVC370_CTRL_CMD_IDLE_CHANNEL + * + * This command tries to wait or forces the desired channel state. + * + * channelClass + * This field indicates the hw class number (0xC378 - 0xC37E). + * It's defined in the h/w header (i.e. clc37d.h, etc.). + * + * channelInstance + * This field indicates which instance of the channelClass the cmd is + * meant for. (zero-based) + * + * desiredChannelStateMask + * This field indicates the desired channel states. When more than + * one bit is set, RM will return whenever it finds hardware on one + * of the states in the bistmask. + * Normal options are IDLE, QUIESCENT1 and QUIESCENT2. + * Verif only option includes BUSY as well. + * Note: + * (1) When QUIESCENT1 or QUIESCENT2 is chosen only one bit should + * be set in the bitmask. RM will ignore any other state. + * (2) Accelerators should not be required for QUIESCENT states as + * RM tries to ensure QUIESCENT forcibly on it's own. + * + * accelerators + * What accelerator bits should be used if RM timesout trying to + * wait for the desired state. This is not yet implemented since it + * should normally not be required to use these. Usage of accelerators + * should be restricted and be done very carefully as they may have + * undesirable effects. + * NOTE: accelerators should not be used directly in production code. + * + * timeout + * Timeout to use when waiting for the desired state. This is also for + * future expansion and not yet implemented. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_TIMEOUT + */ +#define NVC370_CTRL_CMD_IDLE_CHANNEL (0xc3700101) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NVC370_CTRL_IDLE_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NVC370_CTRL_IDLE_CHANNEL_MAX_INSTANCE_CORE NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CORE +#define NVC370_CTRL_IDLE_CHANNEL_MAX_INSTANCE_WINDOW NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW +#define NVC370_CTRL_IDLE_CHANNEL_MAX_INSTANCE_WINDOW_IMM NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW_IMM +#define NVC370_CTRL_IDLE_CHANNEL_MAX_INSTANCE_WRITEBACK NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WRITEBACK +#define NVC370_CTRL_IDLE_CHANNEL_MAX_INSTANCE_CURSOR NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CURSOR + +#define NVC370_CTRL_IDLE_CHANNEL_STATE_IDLE NVC370_CTRL_CMD_CHANNEL_STATE_IDLE +#define NVC370_CTRL_IDLE_CHANNEL_STATE_QUIESCENT1 NVC370_CTRL_CMD_CHANNEL_STATE_QUIESCENT1 +#define NVC370_CTRL_IDLE_CHANNEL_STATE_QUIESCENT2 NVC370_CTRL_CMD_CHANNEL_STATE_QUIESCENT2 + +#define NVC370_CTRL_IDLE_CHANNEL_STATE_BUSY NVC370_CTRL_CMD_CHANNEL_STATE_BUSY + +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_NONE (0x00000000) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_PI (NVBIT(0)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_NOTIF (NVBIT(1)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_SEMA (NVBIT(2)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_INTERLOCK (NVBIT(3)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_FLIPLOCK (NVBIT(4)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_TRASH_ONLY (NVBIT(5)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_TRASH_AND_ABORT (NVBIT(6)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_SYNCPOINT (NVBIT(7)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_TIMESTAMP (NVBIT(8)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_MGI (NVBIT(9)) + +#define NVC370_CTRL_IDLE_CHANNEL_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC370_CTRL_IDLE_CHANNEL_PARAMS { + NVC370_CTRL_CMD_BASE_PARAMS base; + NvU32 channelClass; + NvU32 channelInstance; + NvU32 desiredChannelStateMask; + NvU32 accelerators; // For future expansion. Not yet implemented + NvU32 timeout; // For future expansion. Not yet implemented + NvBool restoreDebugMode; +} NVC370_CTRL_IDLE_CHANNEL_PARAMS; + +/* + * NVC370_CTRL_CMD_SET_ACCL + * + * This command turns accelerators on and off. The use of this command + * should be restricted as it may have undesirable effects. It's + * purpose is to provide a mechanism for clients to use the + * accelerator bits to get into states that are either not detectable + * by the RM or may take longer to reach than we think is reasonable + * to wait in the RM. + * + * NVC370_CTRL_CMD_GET_ACCL + * + * This command queries the current state of the accelerators. + * + * channelClass + * This field indicates the hw class number (0xC378 - 0xC37E). + * It's defined in the h/w header (i.e. clc37d.h, etc.). + * + * channelInstance + * This field indicates which instance of the channelClass the cmd is + * meant for. (zero-based) + * + * accelerators + * Accelerators to be set in the SET_ACCEL command. Returns the + * currently set accelerators on the GET_ACCEL command. + */ + + +/* + * + * accelMask + * A mask to specify which accelerators to change with the + * SET_ACCEL command. This field does nothing in the GET_ACCEL + * command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_CHANNEL + * NV_ERR_INVALID_OWNER + * NV_ERR_GENERIC + * + */ + +#define NVC370_CTRL_CMD_SET_ACCL (0xc3700102) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NVC370_CTRL_SET_ACCL_PARAMS_MESSAGE_ID" */ + +#define NVC370_CTRL_CMD_GET_ACCL (0xc3700103) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | 0x3" */ + +#define NVC370_CTRL_ACCL_MAX_INSTANCE_CORE NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CORE +#define NVC370_CTRL_ACCL_MAX_INSTANCE_WINDOW NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW +#define NVC370_CTRL_ACCL_MAX_INSTANCE_WINDOW_IMM NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW_IMM +#define NVC370_CTRL_ACCL_MAX_INSTANCE_WRITEBACK NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WRITEBACK +#define NVC370_CTRL_ACCL_MAX_INSTANCE_CURSOR NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CURSOR + +#define NVC370_CTRL_ACCL_NONE NVC370_CTRL_IDLE_CHANNEL_ACCL_NONE +#define NVC370_CTRL_ACCL_IGNORE_PI NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_PI +#define NVC370_CTRL_ACCL_SKIP_NOTIF NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_NOTIF +#define NVC370_CTRL_ACCL_SKIP_SEMA NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_SEMA +#define NVC370_CTRL_ACCL_IGNORE_INTERLOCK NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_INTERLOCK +#define NVC370_CTRL_ACCL_IGNORE_FLIPLOCK NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_FLIPLOCK +#define NVC370_CTRL_ACCL_TRASH_ONLY NVC370_CTRL_IDLE_CHANNEL_ACCL_TRASH_ONLY +#define NVC370_CTRL_ACCL_TRASH_AND_ABORT NVC370_CTRL_IDLE_CHANNEL_ACCL_TRASH_AND_ABORT +#define NVC370_CTRL_ACCL_SKIP_SYNCPOINT NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_SYNCPOINT +#define NVC370_CTRL_ACCL_IGNORE_TIMESTAMP NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_TIMESTAMP +#define NVC370_CTRL_ACCL_IGNORE_MGI NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_MGI +#define NVC370_CTRL_SET_ACCL_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVC370_CTRL_SET_ACCL_PARAMS { + NVC370_CTRL_CMD_BASE_PARAMS base; + NvU32 channelClass; + NvU32 channelInstance; + NvU32 accelerators; + NvU32 accelMask; +} NVC370_CTRL_SET_ACCL_PARAMS; +typedef NVC370_CTRL_SET_ACCL_PARAMS NVC370_CTRL_GET_ACCL_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVC370_CTRL_CMD_GET_ACCL_FINN_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVC370_CTRL_CMD_GET_ACCL_FINN_PARAMS { + NVC370_CTRL_GET_ACCL_PARAMS params; +} NVC370_CTRL_CMD_GET_ACCL_FINN_PARAMS; + + + + +/* + * NVC370_CTRL_CMD_GET_CHANNEL_INFO + * + * This command returns the current channel state. + * + * channelClass + * This field indicates the hw class number (0xC378 - 0xC37E). + * It's defined in the h/w header (i.e. clc37d.h, etc.). + * + * channelInstance + * This field indicates which instance of the channelClass the cmd is + * meant for. (zero-based) + * + * channelState + * This field indicates the desired channel state in a mask form that + * is compatible with NVC370_CTRL_CMD_IDLE_CHANNEL. A mask format + * allows clients to check for one from a group of states. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + * + * Display driver uses this call to ensure that all it's methods have + * propagated through hardware's internal fifo + * (NVC370_CTRL_GET_CHANNEL_INFO_STATE_NO_METHOD_PENDING) before it calls + * RM to check whether or not the mode it set up in Assembly State Cache will + * be possible. Note that display driver can not use completion notifier in + * this case because completion notifier is associated with Update and Update + * will propagate the state from Assembly to Armed and when checking the + * possibility of a mode, display driver wouldn't want Armed state to be + * affected. + */ + + + +#define NVC370_CTRL_CMD_GET_CHANNEL_INFO (0xc3700104) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NVC370_CTRL_CMD_GET_CHANNEL_INFO_PARAMS_MESSAGE_ID" */ + +#define NVC370_CTRL_GET_CHANNEL_INFO_MAX_INSTANCE_CORE NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CORE +#define NVC370_CTRL_GET_CHANNEL_INFO_MAX_INSTANCE_WINDOW NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW +#define NVC370_CTRL_GET_CHANNEL_INFO_MAX_INSTANCE_WINDOW_IMM NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW_IMM +#define NVC370_CTRL_GET_CHANNEL_INFO_MAX_INSTANCE_WRITEBACK NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WRITEBACK +#define NVC370_CTRL_GET_CHANNEL_INFO_MAX_INSTANCE_CURSOR NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CURSOR + +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_IDLE NVC370_CTRL_CMD_CHANNEL_STATE_IDLE +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_BUSY NVC370_CTRL_CMD_CHANNEL_STATE_BUSY +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_DEALLOC NVC370_CTRL_CMD_CHANNEL_STATE_DEALLOC +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_DEALLOC_LIMBO NVC370_CTRL_CMD_CHANNEL_STATE_DEALLOC_LIMBO +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_EFI_INIT1 NVC370_CTRL_CMD_CHANNEL_STATE_EFI_INIT1 +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_EFI_INIT2 NVC370_CTRL_CMD_CHANNEL_STATE_EFI_INIT2 +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_EFI_OPERATION NVC370_CTRL_CMD_CHANNEL_STATE_EFI_OPERATION +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_VBIOS_INIT1 NVC370_CTRL_CMD_CHANNEL_STATE_VBIOS_INIT1 +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_VBIOS_INIT2 NVC370_CTRL_CMD_CHANNEL_STATE_VBIOS_INIT2 +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_VBIOS_OPERATION NVC370_CTRL_CMD_CHANNEL_STATE_VBIOS_OPERATION +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_UNCONNECTED NVC370_CTRL_CMD_CHANNEL_STATE_UNCONNECTED +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_INIT1 NVC370_CTRL_CMD_CHANNEL_STATE_INIT1 +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_INIT2 NVC370_CTRL_CMD_CHANNEL_STATE_INIT2 +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_SHUTDOWN1 NVC370_CTRL_CMD_CHANNEL_STATE_SHUTDOWN1 +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_SHUTDOWN2 NVC370_CTRL_CMD_CHANNEL_STATE_SHUTDOWN2 +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_NO_METHOD_PENDING NVC370_CTRL_GET_CHANNEL_INFO_STATE_IDLE +#define NVC370_CTRL_CMD_GET_CHANNEL_INFO_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVC370_CTRL_CMD_GET_CHANNEL_INFO_PARAMS { + NVC370_CTRL_CMD_BASE_PARAMS base; + NvU32 channelClass; + NvU32 channelInstance; + NvBool IsChannelInDebugMode; + NvU32 channelState; +} NVC370_CTRL_CMD_GET_CHANNEL_INFO_PARAMS; + + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h new file mode 100644 index 0000000..ef18c7d --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc370/ctrlc370event.finn +// + +#include "ctrl/ctrlc370/ctrlc370base.h" +/* C370 is partially derived from 5070 */ +#include "ctrl/ctrl5070/ctrl5070event.h" + + + + + +/* valid action values */ +#define NVC370_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE +#define NVC370_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE +#define NVC370_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT + +/* _ctrlc370event_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc370/ctrlc370rg.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc370/ctrlc370rg.h new file mode 100644 index 0000000..2a49284 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc370/ctrlc370rg.h @@ -0,0 +1,123 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc370/ctrlc370rg.finn +// + +#include "ctrl/ctrlc370/ctrlc370base.h" +/* C370 is partially derived from 5070 */ +#include "ctrl/ctrl5070/ctrl5070rg.h" + + + + +/* + * NVC370_CTRL_CMD_GET_LOCKPINS_CAPS + * + * This command returns lockpins for the specified pinset, + * as well as lockpins' HW capabilities. + * + * pinset [in] + * This parameter takes the pinset whose corresponding + * lockpin numbers need to be determined. This only affects + * the return value for the RaterLock and FlipLock pins. + * + * frameLockPin [out] + * This parameter returns the FrameLock pin index. + * + * rasterLockPin [out] + * This parameter returns the RasterLock pin index. + * + * flipLockPin [out] + * This parameter returns the FlipLock pin index. + * + * stereoPin [out] + * This parameter returns the Stereo pin index. + * + * numScanLockPins [out] + * This parameter returns the HW capability of ScanLock pins. + * + * numFlipLockPins [out] + * This parameter returns the HW capability of FlipLock pins. + * + * numStereoPins [out] + * This parameter returns the HW capability of Stereo pins. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NVC370_CTRL_CMD_GET_LOCKPINS_CAPS (0xc3700201) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_RG_INTERFACE_ID << 8) | NVC370_CTRL_GET_LOCKPINS_CAPS_PARAMS_MESSAGE_ID" */ + +#define NVC370_CTRL_GET_LOCKPINS_CAPS_FRAME_LOCK_PIN_NONE (0xffffffff) +#define NVC370_CTRL_GET_LOCKPINS_CAPS_RASTER_LOCK_PIN_NONE (0xffffffff) +#define NVC370_CTRL_GET_LOCKPINS_CAPS_FLIP_LOCK_PIN_NONE (0xffffffff) +#define NVC370_CTRL_GET_LOCKPINS_CAPS_STEREO_PIN_NONE (0xffffffff) +#define NVC370_CTRL_GET_LOCKPINS_CAPS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC370_CTRL_GET_LOCKPINS_CAPS_PARAMS { + NVC370_CTRL_CMD_BASE_PARAMS base; + NvU32 pinset; + NvU32 frameLockPin; + NvU32 rasterLockPin; + NvU32 flipLockPin; + NvU32 stereoPin; + NvU32 numScanLockPins; + NvU32 numFlipLockPins; + NvU32 numStereoPins; +} NVC370_CTRL_GET_LOCKPINS_CAPS_PARAMS; + +/* + * NVC370_CTRL_CMD_SET_SWAPRDY_GPIO_WAR + * + * This command switches SWAP_READY_OUT GPIO between SW + * and HW control to WAR bug 200374184 + * + * bEnable [in]: + * This parameter indicates enable/disable external fliplock + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ + +#define NVC370_CTRL_CMD_SET_SWAPRDY_GPIO_WAR (0xc3700202) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_RG_INTERFACE_ID << 8) | NVC370_CTRL_SET_SWAPRDY_GPIO_WAR_PARAMS_MESSAGE_ID" */ + +#define NVC370_CTRL_SET_SWAPRDY_GPIO_WAR_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVC370_CTRL_SET_SWAPRDY_GPIO_WAR_PARAMS { + NVC370_CTRL_CMD_BASE_PARAMS base; + NvBool bEnable; +} NVC370_CTRL_SET_SWAPRDY_GPIO_WAR_PARAMS; + + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc370/ctrlc370verif.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc370/ctrlc370verif.h new file mode 100644 index 0000000..d891974 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc370/ctrlc370verif.h @@ -0,0 +1,133 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc370/ctrlc370verif.finn +// + +#include "ctrl/ctrlc370/ctrlc370base.h" +/* C370 is partially derived from 5070 */ +#include "ctrl/ctrl5070/ctrl5070verif.h" + + + + +#define NVC370_CTRL_CMD_GET_FORCE_MODESWITCH_FLAGS_OVERRIDES (0xc3700601) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_VERIF_INTERFACE_ID << 8) | NVC370_CTRL_CMD_GET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS_MESSAGE_ID" */ + +#define NVC370_CTRL_CMD_GET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC370_CTRL_CMD_GET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS { + NVC370_CTRL_CMD_BASE_PARAMS base; + NvU32 headInstance; + NvU32 modesetValue; +} NVC370_CTRL_CMD_GET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS; + +/* + * NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES + * + * This command sets modeswitch flags, prior to a modeset. The flags will be + * automatically cleared at the end of each modeset, so this function must be + * called for each modeset where overrides are desired. + * + * headInstance + * this field specifies the head for which modeswitch flags will be overridden + * + * modesetMaskValid + * this field specifies the maskset at which modeswitch flags will be overridden + * + * modesetValue + * this field specifies the override value + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES (0xc3700602) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_VERIF_INTERFACE_ID << 8) | NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS_MESSAGE_ID" */ + +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS { + NVC370_CTRL_CMD_BASE_PARAMS base; + NvU32 headInstance; + NvU32 modesetMaskValid; + NvU32 modesetValue; +} NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS; + +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_BLANK 0:0 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_BLANK_VALID 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_BLANK_INVALID 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK 1:1 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_VALID 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_INVALID 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_SHUTDOWN 2:2 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_SHUTDOWN_VALID 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_SHUTDOWN_INVALID 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOSHUTDOWN 3:3 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOSHUTDOWN_VALID 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOSHUTDOWN_INVALID 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_CHANGE_VPLL 4:4 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_CHANGE_VPLL_VALID 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_CHANGE_VPLL_INVALID 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOCHANGE_VPLL 5:5 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOCHANGE_VPLL_VALID 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOCHANGE_VPLL_INVALID 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_WAKEUP 6:6 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_WAKEUP_VALID 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_WAKEUP_INVALID 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_SHUTDOWN 7:7 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_SHUTDOWN_VALID 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_SHUTDOWN_INVALID 0x00000000 + + +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_BLANK 0:0 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_BLANK_YES 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_BLANK_NO 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK 1:1 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_YES 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_NO 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_SHUTDOWN 2:2 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_SHUTDOWN_YES 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_SHUTDOWN_NO 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOSHUTDOWN 3:3 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOSHUTDOWN_YES 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOSHUTDOWN_NO 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_CHANGE_VPLL 4:4 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_CHANGE_VPLL_YES 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_CHANGE_VPLL_NO 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOCHANGE_VPLL 5:5 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOCHANGE_VPLL_YES 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOCHANGE_VPLL_NO 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_WAKEUP 6:6 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_WAKEUP_YES 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_WAKEUP_NO 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_SHUTDOWN 7:7 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_SHUTDOWN_YES 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_SHUTDOWN_NO 0x00000000 + + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc372/ctrlc372base.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc372/ctrlc372base.h new file mode 100644 index 0000000..2d4aea5 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc372/ctrlc372base.h @@ -0,0 +1,61 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc372/ctrlc372base.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NVC372_DISPLAY_SW control commands and parameters */ + +#define NVC372_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0XC372, NVC372_CTRL_##cat, idx) + +/* NVC372_DISPLAY_SW command categories (6 bits) */ +#define NVC372_CTRL_RESERVED (0x00) +#define NVC372_CTRL_CHNCTL (0x01) +#define NVC372_CTRL_VERIF (0x02) + +/* + * NVC372_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVC372_CTRL_CMD_NULL (0xc3720000) /* finn: Evaluated from "(FINN_NVC372_DISPLAY_SW_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + +// This struct must be the first member of all +// C372 control calls +typedef struct NVC372_CTRL_CMD_BASE_PARAMS { + NvU32 subdeviceIndex; +} NVC372_CTRL_CMD_BASE_PARAMS; + +/* _ctrlc372base_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h new file mode 100644 index 0000000..743663c --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h @@ -0,0 +1,721 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc372/ctrlc372chnc.finn +// + +#include "nvdisptypes.h" +#include "ctrl/ctrlc372/ctrlc372base.h" + +#define NVC372_CTRL_MAX_POSSIBLE_HEADS 8 +#define NVC372_CTRL_MAX_POSSIBLE_WINDOWS 32 + +#define NVC372_CTRL_CMD_IS_MODE_POSSIBLE (0xc3720101) /* finn: Evaluated from "(FINN_NVC372_DISPLAY_SW_CHNCTL_INTERFACE_ID << 8) | NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS_MESSAGE_ID" */ + +/* + * NVC372_CTRL_CMD_IS_MODE_POSSIBLE + * + * This command tells whether or not the specified display config is possible. + * A config might not be possible if the display requirements exceed the GPU + * capabilities. Display requirements will be higher with more display + * surfaces, higher resolutions, higher downscaling factors, etc. GPU + * capabilities are determined by clock frequencies, the width of data pipes, + * amount of mempool available, number of thread groups available, etc. + * + * Inputs: + * head.headIndex + * This is the hardware index number for the head. Only active heads + * should be included in the input structure. + * + * head.maxPixelClkKHz + * This parameter specifies the pixel scanout rate (in KHz). + * + * head.rasterSize + * This structure specifies the total width and height of the raster that + * is sent to the display. (The width and height are also referred to as + * HTotal and VTotal, respectively.) + * + * head.rasterBlankStart + * X specifies the pixel column where horizontal blanking begins; + * Y specifies the pixel row where vertical blanking begins. + * + * head.rasterBlankEnd + * X specifies the pixel column where horizontal blanking ends; + * Y specifies the pixel row where vertical blanking ends. + * + * head.rasterVertBlank2 + * X and Y specify the pixel column/row where horizontal/vertical blanking + * ends on the second field of every pair for an interlaced raster. This + * field is not used when the raster is progressive. + * + * head.control.masterLockMode + * head.control.masterLockPin + * head.control.slaveLockMode + * head.control.slaveLockPin + * Heads that are raster locked or frame locked together will have + * synchronized timing. For example, vblank will occur at the same time on + * all of the heads that are locked together. + * + * "LockMode" tells if a head is raster locked, frame locked, or not locked. + * + * "LockPin" tells which heads are in a group of locked heads. There + * should be one master per group, and all slave heads that are locked to + * that master should have the same slaveLockPin number as the master's + * masterLockPin number. + * + * Note: The LockModes and LockPins are used only if the min v-pstate is + * required (i.e., if NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE + * is set). + * + * head.maxDownscaleFactorH + * head.maxDownscaleFactorV + * maxDownscaleFactorH and maxDownscaleFactorV represent the maximum amount + * by which the the composited image can be reduced in size, horizontally + * and vertically, respectively, multiplied by 0x400. For example, if the + * scaler input width is 1024, and the scaler output width is 2048, the + * downscale factor would be 1024 / 2048 = 0.5, and multiplying by 0x400 + * would give 512. + * + * head.outputScalerVerticalTaps + * scalerVerticalTaps indicates the maximum number of vertical taps + * allowed in the output scaler. + * + * Note that there are no #defines for tap values; the parameter is simply + * the number of taps (e.g., "2" for 2 taps). + * + * head.bUpscalingAllowedV + * bUpscalingAllowed indicates whether or not the composited image can be + * increased in size, vertically. + * + * head.bOverfetchEnabled + * bOverfetchEnabled indicates whether or not the vertical overfetch is + * enabled in postcomp scaler. + * + * head.minFrameIdle.leadingRasterLines + * leadingRasterLines defines the number of lines between the start of the + * frame (vsync) and the start of the active region. This includes Vsync, + * Vertical Back Porch, and the top part of the overscan border. The + * minimum value is 2 because vsync and VBP must be at least 1 line each. + * + * head.minFrameIdle.trailingRasterLines + * trailingRasterLines defines the number of lines between the end of the + * active region and the end of the frame. This includes the bottom part + * of the overscan border and the Vertical Front Porch. + * + * head.lut + * This parameter specifies whether or not the output LUT is enabled, and + * the size of the LUT. The parameter should be an + * NVC372_CTRL_IMP_LUT_USAGE_xxx value. + * + * head.cursorSize32p + * This parameter specifies the width of the cursor, in units of 32 pixels. + * So, for example, "8" would mean 8 * 32 = 256, for a 256x256 cursor. Zero + * means the cursor is disabled. + * + * head.bEnableDsc + * bEnableDsc indicates whether or not DSC is enabled + * + * head.bYUV420Format + * This parameter indicates output format is YUV420. + * Refer to NVD_YUV420_Output_Functional_Description.docx for more details. + * + * head.bIs2Head1Or + * This parameter specifies if the head operates in 2Head1Or mode. + * Refer to NVD_2_Heads_Driving_1_OR_Functional_Description.docx for more details. + * + * head.bGetOSLDOutput + * This parameter specifies if the client requires output for the OSLD + * (One Shot Mode with Stall Lock Disabled) mode along with legacy outputs. + * + * head.bDisableMidFrameAndDWCFWatermark + * WAR for bug 200508242. + * In linux it is possible that there will be no fullscreen window visible + * for a head. For these cases we would not hit dwcf or midframe watermarks + * leading to fbflcn timing out waiting on ok_to_switch and forcing mclk + * switch. This could lead to underflows. So if that scenario is caught (by + * Display Driver) bDisableMidFrameAndDWCFWatermark will be set to true and + * IMP will exclude dwcf and midframe contribution from the "is mclk switch + * guaranteed" calculation for the bandwidth clients of that head. + * + * window.windowIndex + * This is the hardware index number for the window. Only active windows + * should be included in the input structure. + * + * window.owningHead + * This is the hardware index of the head that will receive the window's + * output. + * + * window.formatUsageBound + * This parameter is a bitmask of all possible non-rotated mode data + * formats (NVC372_CTRL_FORMAT_xxx values). + * + * window.rotatedFormatUsageBound + * This parameter is a bitmask of all possible rotated mode data formats + * (NVC372_CTRL_FORMAT_xxx values). + * + * window.maxPixelsFetchedPerLine + * This parameter defines the maximum number of pixels that may need to be + * fetched in a single line for this window. Often, this can be set to the + * viewportSizeIn.Width. But if the window is known to be clipped, such + * that an entire line will never be fetched, then this parameter can be + * set to the clipped size (to improve the chances of the mode being + * possible, or possible at a lower v-pstate). + * + * In some cases, the value of this parameter must be increased by a few + * pixels in order to account for scaling overfetch, input chroma overfetch + * (420/422->444), and/or chroma output low pass filter overfetch + * (444->422/420). This value is chip dependent; refer to the + * MaxPixelsFetchedPerLine parameter in nvdClass_01.mfs for the exact + * value. In no case does the maxPixelsFetchedPerLine value need to exceed + * the surface width. + * + * window.maxDownscaleFactorH + * window.maxDownscaleFactorV + * maxDownscaleFactorH and maxDownscaleFactorV represent the maximum amount + * by which the the window image can be reduced in size, horizontally and + * vertically, respectively, multiplied by + * NVC372_CTRL_SCALING_FACTOR_MULTIPLIER. For example, + * if the scaler input width is 1024, and the scaler output width is 2048, + * the downscale factor would be 1024 / 2048 = 0.5, and multiplying by + * NVC372_CTRL_SCALING_FACTOR_MULTIPLIER if 0x400 would give 512. + * + * window.inputScalerVerticalTaps + * scalerVerticalTaps indicates the maximum number of vertical taps + * allowed in the input scaler. + * + * Note that there are no #defines for tap values; the parameter is simply + * the number of taps (e.g., "2" for 2 taps). + * + * window.bUpscalingAllowedV + * bUpscalingAllowed indicates whether or not the composited image can be + * increased in size, vertically. + * + * window.bOverfetchEnabled + * bOverfetchEnabled indicates whether or not the vertical overfetch is + * enabled in precomp scaler. + * + * window.lut + * This parameter specifies whether or not the input LUT is enabled, and + * the size of the LUT. The parameter should be an + * NVC372_CTRL_IMP_LUT_USAGE_xxx value. + * + * window.tmoLut + * This parameter specifies whether or not the tmo LUT is enabled, and + * the size of the LUT. This lut is used for HDR. The parameter should be + * an NVC372_CTRL_IMP_LUT_USAGE_xxx value. + * + * numHeads + * This is the number of heads in the "head" array of the + * NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS struct. Only active heads should be + * included in the struct. + * + * numWindows + * This is the number of windows in the "window" array of the + * NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS struct. Only active windows should + * be included in the struct. + * + * options + * This parameter specifies a bitmask for options. + * + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN + * tells IMP to calculate worstCaseMargin and worstCaseDomain. + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE + * tells IMP to calculate and report the minimum v-pstate at which the + * mode is possible. + * + * bUseCachedPerfState + * Indicates that RM should use cached values for the fastest + * available perf level (v-pstate for PStates 3.0 or pstate for + * PStates 2.0) and dispclk. This feature allows the query call to + * execute faster, and is intended to be used, for example, during + * mode enumeration, when many IMP query calls are made in close + * succession, and perf conditions are not expected to change between + * query calls. When IMP has not been queried recently, it is + * recommended to NOT use cached values, in case perf conditions have + * changed and the cached values no longer reflect the current + * conditions. + * + * testMclkFreqKHz + * This is the mclk frequency specified by the client, in KHz. RM will + * use this value to compare with the minimum dramclk required by the + * given mode. The parameter will have value 0 if the client doesn't want + * IMP query to consider this. This input is valid only on Tegra and only + * for verification purposes on internal builds. + * For this input to work, client must set + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE in the + * "options" field. + * + * Outputs: + * bIsPossible + * This output tells if the specified mode can be supported. To know if + * the mode is possible with OSLD, the bIsOSLDPossible result must + * be checked. + * + * bIsOSLDPossible + * This output is returned for each head and suggests to the clients + * if the mode will be possible or not on that head when OSLD is enabled. + * The output is only valid if bGetOSLDOutput is set in the head input. + * Note that with OSLD output, RM will also return the legacy output + * values. + * + * minImpVPState + * minImpVPState returns the minimum v-pstate at which the mode is possible + * (assuming bIsPossible is TRUE). This output is valid only on dGPU, and + * only if NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in + * the "options" field. + * + * If the minimum v-pstate is required for a multi-head config, then + * masterLockMode, masterLockPin, slaveLockMode, and slaveLockPin must all + * be initialized. + * minPState + * minPState returns the pstate value corresponding to minImpVPState. It + * is returned as the numeric value of the pstate (P0 -> 0, P1 -> 1, etc.). + * This output is valid only on dGPU, and only if + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set + * in the "options" field. + * + * Note that the pstate returned by minPstateForGlitchless is not + * necessarily sufficient to meet IMP requirements. The pstate corresponds + * to the vpstate returned by minImpVPState, and this vpstate represents + * clocks that are sufficient for IMP requirements, but the pstate + * typically covers a range of frequencies (depending on the clock), and it + * is possible that only part of the range is sufficient for IMP. + * + * minRequiredBandwidthKBPS + * minRequiredBandwidthKBPS returns the minimum bandwidth that must be + * allocated to display in order to make the mode possible (assuming + * bIsPossible is TRUE). This output is valid only on Tegra, and only if + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in the + * "options" field. + * + * floorBandwidthKBPS + * floorBandwidthKBPS returns the minimum mclk frequency that can support + * the mode, and allow glitchless mclk switch, multiplied by the width of + * the data pipe. (This is an approximation of the bandwidth that can be + * provided by the min required mclk frequency, ignoring overhead.) If the + * mode is possible, but glitchless mclk switch is not, floorBandwidthKBPS + * will be calculated based on the maximum possible mclk frequency. This + * output is valid only on Tegra, and only if + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in the + * "options" field. + * + * minRequiredHubclkKHz + * minRequiredHubclkKHz returns the minimum hubclk frequency that can + * support the mode. This output is valid only on Tegra, and only if + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in the + * "options" field. + * + * vblankIncreaseInLinesForOSLDMode + * vblankIncreaseInLinesForOSLDMode returns the amount, in lines, by + * which vblank needs to be extended to achieve optimized MSCG when OSLD + * Mode is enabled (assuming bIsPossible is TRUE). Features like Panel + * Replay and Panel Self Refresh enable OSLD mode. This value is 0 if + * the vblank is large enough to accommodate spool up and MSCG latencies. + * This output is valid only if + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in the + * "options" field and bGetOSLDOutput was specified in the head input. + * + * wakeUpRgLineForOSLDMode + * wakeUpRgLineForOSLDMode returns the rg line in the vblank region at which + * the clients will be required to send a timestamped update to achieve + * optimized MSCG when OSLD Mode is enabled (assuming bIsPossible is + * is TRUE). Features like Panel Replay and Panel Self Refresh enable + * OSLD mode. This output is valid only if + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in the + * "options" field and bGetOSLDOutput was specified in the head input. + * + * worstCaseMargin + * worstCaseMargin returns the ratio of available bandwidth to required + * bandwidth, multiplied by NV5070_CTRL_IMP_MARGIN_MULTIPLIER. Available + * bandwidth is calculated in the worst case bandwidth domain, i.e., the + * domain with the least available margin. Bandwidth domains include the + * IMP-relevant clock domains, and possibly other virtual bandwidth + * domains such as AWP. + * + * Note that IMP checks additional parameters besides the bandwidth margins + * but only the bandwidth margin is reported here, so it is possible for a + * mode to have a more restrictive domain that is not reflected in the + * reported margin result. + * + * This result is not guaranteed to be valid if the mode is not possible. + * + * Note also that the result is generally calculated for the highest + * v-pstate possible (usually P0). But if the _NEED_MIN_VPSTATE is + * specified, the result will be calculated for the min possible v-pstate + * (or the highest possible v-pstate, if the mode is not possible). + * + * The result is valid only if + * NV5070_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN is set in "options". + * + * dispClkKHz + * This is the dispclk frequency selected by IMP for this mode. For dGPU, + * it will be one of the fixed frequencies from the list of frequencies + * supported by the vbios. + * + * worstCaseDomain + * Returns a short text string naming the domain for the margin returned in + * "worstCaseMargin". See "worstCaseMargin" for more information. + * + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + * NVOS_STATUS_ERROR_GENERIC + */ +#define NVC372_CTRL_IMP_LUT_USAGE_NONE 0 +#define NVC372_CTRL_IMP_LUT_USAGE_257 1 +#define NVC372_CTRL_IMP_LUT_USAGE_1025 2 + +typedef struct NVC372_CTRL_IMP_HEAD { + NvU8 headIndex; + + NvU32 maxPixelClkKHz; + + struct { + NvU32 width; + NvU32 height; + } rasterSize; + + struct { + NvU32 X; + NvU32 Y; + } rasterBlankStart; + + struct { + NvU32 X; + NvU32 Y; + } rasterBlankEnd; + + struct { + NvU32 yStart; + NvU32 yEnd; + } rasterVertBlank2; + + struct { + NV_DISP_LOCK_MODE masterLockMode; + NV_DISP_LOCK_PIN masterLockPin; + NV_DISP_LOCK_MODE slaveLockMode; + NV_DISP_LOCK_PIN slaveLockPin; + } control; + + NvU32 maxDownscaleFactorH; + NvU32 maxDownscaleFactorV; + NvU8 outputScalerVerticalTaps; + NvBool bUpscalingAllowedV; + NvBool bOverfetchEnabled; + + struct { + NvU16 leadingRasterLines; + NvU16 trailingRasterLines; + } minFrameIdle; + + NvU8 lut; + NvU8 cursorSize32p; + + NvBool bEnableDsc; + + NvBool bYUV420Format; + + NvBool bIs2Head1Or; + + NvBool bGetOSLDOutput; + + NvBool bDisableMidFrameAndDWCFWatermark; +} NVC372_CTRL_IMP_HEAD; +typedef struct NVC372_CTRL_IMP_HEAD *PNVC372_CTRL_IMP_HEAD; + +typedef struct NVC372_CTRL_IMP_WINDOW { + NvU32 windowIndex; + NvU32 owningHead; + NvU32 formatUsageBound; + NvU32 rotatedFormatUsageBound; + NvU32 maxPixelsFetchedPerLine; + NvU32 maxDownscaleFactorH; + NvU32 maxDownscaleFactorV; + NvU8 inputScalerVerticalTaps; + NvBool bUpscalingAllowedV; + NvBool bOverfetchEnabled; + NvU8 lut; + NvU8 tmoLut; +} NVC372_CTRL_IMP_WINDOW; +typedef struct NVC372_CTRL_IMP_WINDOW *PNVC372_CTRL_IMP_WINDOW; + +#define NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN (0x00000001) +#define NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE (0x00000002) + +#define NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS { + NVC372_CTRL_CMD_BASE_PARAMS base; + + NvU8 numHeads; + NvU8 numWindows; + + NVC372_CTRL_IMP_HEAD head[NVC372_CTRL_MAX_POSSIBLE_HEADS]; + + // C form: NVC372_CTRL_IMP_WINDOW window[NVC372_CTRL_MAX_POSSIBLE_WINDOWS]; + NVC372_CTRL_IMP_WINDOW window[NVC372_CTRL_MAX_POSSIBLE_WINDOWS]; + + NvU32 options; + + NvU32 testMclkFreqKHz; + + NvBool bIsPossible; + + NvBool bIsOSLDPossible[NVC372_CTRL_MAX_POSSIBLE_HEADS]; + + NvU32 minImpVPState; + + NvU32 minPState; + + NvU32 minRequiredBandwidthKBPS; + + NvU32 floorBandwidthKBPS; + + NvU32 minRequiredHubclkKHz; + + NvU32 vblankIncreaseInLinesForOSLDMode[NVC372_CTRL_MAX_POSSIBLE_HEADS]; + + NvU32 wakeUpRgLineForOSLDMode[NVC372_CTRL_MAX_POSSIBLE_HEADS]; + + NvU32 worstCaseMargin; + + NvU32 dispClkKHz; + + char worstCaseDomain[8]; + + NvBool bUseCachedPerfState; +} NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS; +typedef struct NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS *PNVC372_CTRL_IS_MODE_POSSIBLE_PARAMS; + +/* valid format values */ +#define NVC372_CTRL_FORMAT_RGB_PACKED_1_BPP (0x00000001) +#define NVC372_CTRL_FORMAT_RGB_PACKED_2_BPP (0x00000002) +#define NVC372_CTRL_FORMAT_RGB_PACKED_4_BPP (0x00000004) +#define NVC372_CTRL_FORMAT_RGB_PACKED_8_BPP (0x00000008) +#define NVC372_CTRL_FORMAT_YUV_PACKED_422 (0x00000010) +#define NVC372_CTRL_FORMAT_YUV_PLANAR_420 (0x00000020) +#define NVC372_CTRL_FORMAT_YUV_PLANAR_444 (0x00000040) +#define NVC372_CTRL_FORMAT_YUV_SEMI_PLANAR_420 (0x00000080) +#define NVC372_CTRL_FORMAT_YUV_SEMI_PLANAR_422 (0x00000100) +#define NVC372_CTRL_FORMAT_YUV_SEMI_PLANAR_422R (0x00000200) +#define NVC372_CTRL_FORMAT_YUV_SEMI_PLANAR_444 (0x00000400) +#define NVC372_CTRL_FORMAT_EXT_YUV_PLANAR_420 (0x00000800) +#define NVC372_CTRL_FORMAT_EXT_YUV_PLANAR_444 (0x00001000) +#define NVC372_CTRL_FORMAT_EXT_YUV_SEMI_PLANAR_420 (0x00002000) +#define NVC372_CTRL_FORMAT_EXT_YUV_SEMI_PLANAR_422 (0x00004000) +#define NVC372_CTRL_FORMAT_EXT_YUV_SEMI_PLANAR_422R (0x00008000) +#define NVC372_CTRL_FORMAT_EXT_YUV_SEMI_PLANAR_444 (0x00010000) + +/* valid impResult values */ +#define NVC372_CTRL_IMP_MODE_POSSIBLE 0 +#define NVC372_CTRL_IMP_NOT_ENOUGH_MEMPOOL 1 +#define NVC372_CTRL_IMP_REQ_LIMIT_TOO_HIGH 2 +#define NVC372_CTRL_IMP_VBLANK_TOO_SMALL 3 +#define NVC372_CTRL_IMP_HUBCLK_TOO_LOW 4 +#define NVC372_CTRL_IMP_INSUFFICIENT_BANDWIDTH 5 +#define NVC372_CTRL_IMP_DISPCLK_TOO_LOW 6 +#define NVC372_CTRL_IMP_ELV_START_TOO_HIGH 7 +#define NVC372_CTRL_IMP_OSLD_ELV_START_TOO_HIGH 8 +#define NVC372_CTRL_IMP_INSUFFICIENT_THREAD_GROUPS 9 +#define NVC372_CTRL_IMP_INVALID_PARAMETER 10 +#define NVC372_CTRL_IMP_UNRECOGNIZED_FORMAT 11 +#define NVC372_CTRL_IMP_UNSPECIFIED 12 + +/* + * The calculated margin is multiplied by a constant, so that it can be + * represented as an integer with reasonable precision. "0x400" was chosen + * because it is a power of two, which might allow some compilers/CPUs to + * simplify the calculation by doing a shift instead of a multiply/divide. + * (And 0x400 is 1024, which is close to 1000, so that may simplify visual + * interpretation of the raw margin value.) + */ +#define NVC372_CTRL_IMP_MARGIN_MULTIPLIER (0x00000400) + +/* scaling factor */ +#define NVC372_CTRL_SCALING_FACTOR_MULTIPLIER (0x00000400) + +#define NVC372_CTRL_CMD_NUM_DISPLAY_ID_DWORDS_PER_HEAD 2 +#define NVC372_CTRL_CMD_MAX_SORS 4 + +#define NVC372_CTRL_CMD_IS_MODE_POSSIBLE_OR_SETTINGS (0xc3720102) /* finn: Evaluated from "(FINN_NVC372_DISPLAY_SW_CHNCTL_INTERFACE_ID << 8) | NVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS_MESSAGE_ID" */ + +/* + * NVC372_CTRL_CMD_IS_MODE_POSSIBLE_OR_SETTINGS + * + * This command tells us if output resource pixel clocks requested by client + * is possible or not. Note that this will not be used for displayport sor as + * it will be handled by displayport library. + * + * Inputs: + * numHeads + * This is the number of heads in the "head" array of the + * NVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS struct. Only active heads + * should be included in the struct. + * + * head.headIndex + * This is the hardware index number for the head. Only an active head + * should be included in the input structure. + * + * head.maxPixelClkKHz + * This parameter specifies the pixel scanout rate (in KHz). + * + * head.displayId + * Array of displayId's associated with the head. This is limited by + * NVC372_CTRL_CMD_NUM_DISPLAY_ID_DWORDS_PER_HEAD. + * + * sor.ownerMask + * Consists of a mask of all heads that drive this sor. + * + * sor.protocol + * Defines the protocol of the sor in question. + * + * sor.pixelReplicateMode + * Defines which pixel replication mode is requested. This can be off + * or X2 or X4 mode. + * + * Outputs: + * bIsPossible + * This tells us that the requested pixel clock can be supported. + */ + + +#define NVC372_CTRL_IS_MODE_POSSIBLE_DISPLAY_ID_SKIP_IMP_OUTPUT_CHECK (0xAAAAAAAA) + +typedef struct NVC372_CTRL_IMP_OR_SETTINGS_HEAD { + NvU8 headIndex; + NvU32 maxPixelClkKhz; + + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP outputResourcePixelDepthBPP; + + NvU32 displayId[NVC372_CTRL_CMD_NUM_DISPLAY_ID_DWORDS_PER_HEAD]; +} NVC372_CTRL_IMP_OR_SETTINGS_HEAD; +typedef struct NVC372_CTRL_IMP_OR_SETTINGS_HEAD *PNVC372_CTRL_IMP_OR_SETTINGS_HEAD; + +#define NVC372_CTRL_CMD_SOR_OWNER_MASK_NONE (0x00000000) +#define NVC372_CTRL_CMD_SOR_OWNER_MASK_HEAD(i) (1 << i) + +#define NVC372_CTRL_CMD_SOR_PROTOCOL_SINGLE_TMDS_A (0x00000000) +#define NVC372_CTRL_CMD_SOR_PROTOCOL_SINGLE_TMDS_B (0x00000001) +#define NVC372_CTRL_CMD_SOR_PROTOCOL_DUAL_TMDS (0x00000002) +#define NVC372_CTRL_CMD_SOR_PROTOCOL_SUPPORTED (0xFFFFFFFF) + +#define NVC372_CTRL_IS_MODE_POSSIBLE_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NVC372_CTRL_IS_MODE_POSSIBLE_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NVC372_CTRL_IS_MODE_POSSIBLE_PIXEL_REPLICATE_MODE_X4 (0x00000002) + +typedef struct NVC372_CTRL_IMP_OR_SETTINGS_SOR { + NvU32 ownerMask; + NvU32 protocol; + NvU32 pixelReplicateMode; +} NVC372_CTRL_IMP_OR_SETTINGS_SOR; +typedef struct NVC372_CTRL_IMP_OR_SETTINGS_SOR *PNVC372_CTRL_IMP_OR_SETTINGS_SOR; + +#define NVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS { + NVC372_CTRL_CMD_BASE_PARAMS base; + + NvU32 numHeads; + + NVC372_CTRL_IMP_OR_SETTINGS_HEAD head[NVC372_CTRL_MAX_POSSIBLE_HEADS]; + + NVC372_CTRL_IMP_OR_SETTINGS_SOR sor[NVC372_CTRL_CMD_MAX_SORS]; + + NvBool bIsPossible; +} NVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS; +typedef struct NVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS *PNVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS; + +#define NVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE (0xc3720103) /* finn: Evaluated from "(FINN_NVC372_DISPLAY_SW_CHNCTL_INTERFACE_ID << 8) | NVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE_PARAMS_MESSAGE_ID" */ + +/* + * NVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE + * + * This control call is used by clients to inform RM about video adaptive refresh rate enable/disable. + * Based on the state, RM will enable/disable supported low power features. + * + * Inputs: + * displayID + * displayId of panel on which video adaptive refresh rate is enabled/disabled. + * + * bEnable + * NV_TRUE to enable video adaptive refresh rate mode. + * NV_FALSE to disable video adaptive refresh rate mode. + * + * Outputs: + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE_PARAMS { + NvU32 displayID; + NvBool bEnable; +} NVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE_PARAMS; +typedef struct NVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE_PARAMS *PNVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE_PARAMS; + + +#define NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN (0xc3720104) /* finn: Evaluated from "(FINN_NVC372_DISPLAY_SW_CHNCTL_INTERFACE_ID << 8) | NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS_MESSAGE_ID" */ + +/* + * NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN + * + * This control call is used by clients to query the active viewport for the + * provided window precalculated at the beginning of each frame. + * + * Inputs: + * windowIndex + * Index of the window to be queried. Must be connected to an active head. + * + * Outputs: + * activeViewportPointIn + * X and Y coordinates of the active viewport on the provided window for + * the most recent frame. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT if the window index is invalid + * NV_ERR_INVALID_STATE if the window index isn't connected to a head + * NV_ERR_NOT_SUPPORTED + */ +#define NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS { + NVC372_CTRL_CMD_BASE_PARAMS base; + + NvU32 windowIndex; + + struct { + NvU32 x; + NvU32 y; + } activeViewportPointIn; +} NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS; +typedef struct NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS *PNVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS; + +/* _ctrlc372chnc_h_ */ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc46f.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc46f.h new file mode 100644 index 0000000..c53e217 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc46f.h @@ -0,0 +1,162 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc46f.finn +// + + + + +/* TURING_CHANNEL_GPFIFO_A control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl906f.h" /* C36F is partially derived from 906F */ +#include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */ +#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F + +#define NVC46F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xC36F, NVC46F_CTRL_##cat, idx) + +/* TURING_CHANNEL_GPFIFO_A command categories (6bits) */ +#define NVC46F_CTRL_RESERVED (0x00) +#define NVC46F_CTRL_GPFIFO (0x01) +#define NVC46F_CTRL_EVENT (0x02) + +/* + * NVC46F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned is: NV_OK +*/ +#define NVC46F_CTRL_CMD_NULL (NVC36F_CTRL_CMD_NULL) + + + + + + +/* + * NVC46F_CTRL_GET_CLASS_ENGINEID + * + * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. + * + */ +#define NVC46F_CTRL_GET_CLASS_ENGINEID (NVC36F_CTRL_GET_CLASS_ENGINEID) + +typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC46F_CTRL_GET_CLASS_ENGINEID_PARAMS; + +/* + * NVC46F_CTRL_RESET_CHANNEL + * + * Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information. + * + */ +#define NVC46F_CTRL_CMD_RESET_CHANNEL (NVC36F_CTRL_CMD_RESET_CHANNEL) + +typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC46F_CTRL_CMD_RESET_CHANNEL_PARAMS; + +/* + * NVC46F_CTRL_CMD_GPFIFO_SCHEDULE + * + * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. + * + */ +#define NVC46F_CTRL_CMD_GPFIFO_SCHEDULE (NVC36F_CTRL_CMD_GPFIFO_SCHEDULE) + +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC46F_CTRL_GPFIFO_SCHEDULE_PARAMS; + +/* + * NVC46F_CTRL_CMD_BIND + * + * Please see description of NVA06F_CTRL_CMD_BIND for more information. + */ +#define NVC46F_CTRL_CMD_BIND (NVC36F_CTRL_CMD_BIND) + +typedef NVA06F_CTRL_BIND_PARAMS NVC46F_CTRL_BIND_PARAMS; + +/* + * NVC46F_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. +*/ +#define NVC46F_CTRL_CMD_EVENT_SET_NOTIFICATION (NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION) + +typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC46F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NVC46F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE +#define NVC46F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE +#define NVC46F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT + +/* + * NVC46F_CTRL_CMD_EVENT_SET_TRIGGER + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information. + */ +#define NVC46F_CTRL_CMD_EVENT_SET_TRIGGER (NVC36F_CTRL_CMD_EVENT_SET_TRIGGER) + + + + + +/* + * NVC46F_CTRL_CMD_GET_MMU_FAULT_INFO + * + * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. + * + */ +#define NVC46F_CTRL_CMD_GET_MMU_FAULT_INFO (NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO) + +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC46F_CTRL_GET_MMU_FAULT_INFO_PARAMS; + +/* + * NVC46F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN + * + * This command returns an opaque work submit token to the caller which + * can be used to write to doorbell register to finish submitting work. + * + * workSubmitToken The 32-bit work submit token + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + * + */ + +#define NVC46F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN (NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN) + +typedef struct NVC46F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS { + NvU32 workSubmitToken; +} NVC46F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS; + +/* _ctrlc46f.h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc56f.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc56f.h new file mode 100644 index 0000000..a781b1a --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc56f.h @@ -0,0 +1,166 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc56f.finn +// + + + + +/* AMPERE_CHANNEL_GPFIFO_A control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl906f.h" /* C36F is partially derived from 906F */ +#include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */ +#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F + + + +#define NVC56F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xC36F, NVC56F_CTRL_##cat, idx) + +/* AMPERE_CHANNEL_GPFIFO_A command categories (6bits) */ +#define NVC56F_CTRL_RESERVED (0x00) +#define NVC56F_CTRL_GPFIFO (0x01) +#define NVC56F_CTRL_EVENT (0x02) + +/* + * NVC56F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned is: NV_OK +*/ +#define NVC56F_CTRL_CMD_NULL (NVC36F_CTRL_CMD_NULL) + + + + + + +/* + * NVC56F_CTRL_GET_CLASS_ENGINEID + * + * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. + * + */ +#define NVC56F_CTRL_GET_CLASS_ENGINEID (NVC36F_CTRL_GET_CLASS_ENGINEID) + +typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC56F_CTRL_GET_CLASS_ENGINEID_PARAMS; + +/* + * NVC56F_CTRL_RESET_CHANNEL + * + * Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information. + * + */ +#define NVC56F_CTRL_CMD_RESET_CHANNEL (NVC36F_CTRL_CMD_RESET_CHANNEL) + +typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC56F_CTRL_CMD_RESET_CHANNEL_PARAMS; + +/* + * NVC56F_CTRL_CMD_GPFIFO_SCHEDULE + * + * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. + * + */ +#define NVC56F_CTRL_CMD_GPFIFO_SCHEDULE (NVC36F_CTRL_CMD_GPFIFO_SCHEDULE) + +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC56F_CTRL_GPFIFO_SCHEDULE_PARAMS; + +/* + * NVC56F_CTRL_CMD_BIND + * + * Please see description of NVA06F_CTRL_CMD_BIND for more information. + */ +#define NVC56F_CTRL_CMD_BIND (NVC36F_CTRL_CMD_BIND) + +typedef NVA06F_CTRL_BIND_PARAMS NVC56F_CTRL_BIND_PARAMS; + +/* + * NVC56F_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. +*/ +#define NVC56F_CTRL_CMD_EVENT_SET_NOTIFICATION (NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION) + +typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC56F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NVC56F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE +#define NVC56F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE +#define NVC56F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT + +/* + * NVC56F_CTRL_CMD_EVENT_SET_TRIGGER + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information. + */ +#define NVC56F_CTRL_CMD_EVENT_SET_TRIGGER (NVC36F_CTRL_CMD_EVENT_SET_TRIGGER) + + + + + +/* + * NVC56F_CTRL_CMD_GET_MMU_FAULT_INFO + * + * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. + * + */ +#define NVC56F_CTRL_CMD_GET_MMU_FAULT_INFO (NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO) + +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC56F_CTRL_GET_MMU_FAULT_INFO_PARAMS; + +/* + * NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN + * + * This command returns an opaque work submit token to the caller which + * can be used to write to doorbell register to finish submitting work. + * + * workSubmitToken The 32-bit work submit token + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + * + */ + +#define NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN (NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN) + +typedef struct NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS { + NvU32 workSubmitToken; +} NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS; + + + +/* _ctrlc56f.h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc637.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc637.h new file mode 100644 index 0000000..155d639 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc637.h @@ -0,0 +1,392 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc637.finn +// + +#include "ctrl/ctrlxxxx.h" +/* AMPERE_SMC_PARTITION_REF commands and parameters */ + +#define NVC637_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xC637, NVC637_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NVC637_CTRL_RESERVED (0x00) +#define NVC637_CTRL_EXEC_PARTITIONS (0x01) + + +/*! + * NVC637_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVC637_CTRL_CMD_NULL (0xc6370000) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/*! + * NVC637_CTRL_EXEC_PARTITIONS_INFO + * + * This structure specifies resources in an execution partition + * + * gpcCount[IN/OUT] + * - Total Number of GPCs in this partition (including GFX Supported GPCs) + * + * gfxGpcCount[IN/OUT] + * - Number of GFX GPCs in this partition. This should be a subset of gpcs inlcuded in gpcCount + * + * VeidCount[OUT] + * - Number of VEIDs available in this partition. + * + * ceCount[IN/OUT] + * - Copy Engines in this partition + * + * nvEncCount[IN/OUT] + * - Encoder Engines in this partition + * + * nvDecCount[IN/OUT] + * - Decoder Engines in this partition + * + * nvJpgCount[IN/OUT] + * - Jpg Engines in this partition + * + * nvOfaCount[IN/OUT] + * - Ofa engines in this partition + * + * sharedEngFlags[IN/OUT] + * - Flags determining whether above engines are shared with other execution partitions + * + * veidStartOffset[OUT] + * - VEID start offset within GPU partition + * + * smCount[IN/OUT] + * - Number of active SMs in this partition + * + * spanStart[IN/OUT] + * - First slot in the span for an execution partition placement + * + * computeSize[IN/OUT] + * - Flag corresponding to the compute profile used + * + */ +typedef struct NVC637_CTRL_EXEC_PARTITIONS_INFO { + NvU32 gpcCount; + NvU32 gfxGpcCount; + NvU32 veidCount; + NvU32 ceCount; + NvU32 nvEncCount; + NvU32 nvDecCount; + NvU32 nvJpgCount; + NvU32 ofaCount; + NvU32 sharedEngFlag; + NvU32 veidStartOffset; + NvU32 smCount; + NvU32 spanStart; + NvU32 computeSize; +} NVC637_CTRL_EXEC_PARTITIONS_INFO; + +#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG 31:0 +#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NONE 0x0 +#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_CE NVBIT(0) +#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVDEC NVBIT(1) +#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVENC NVBIT(2) +#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_OFA NVBIT(3) +#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVJPG NVBIT(4) + +#define NVC637_CTRL_MAX_EXEC_PARTITIONS 8 +#define NVC637_CTRL_EXEC_PARTITIONS_ID_INVALID 0xFFFFFFFF + +/*! + * NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS + * + * This command will create requested execution partitions under the subscribed + * memory partition. The memory partition is expected to be configured before + * execution partition creation. + * + * bQuery[IN] + * - If NV_TRUE, execution partitions will not be created, but return + * status of NV_OK will indicate that the request is valid and can + * currently be fulfilled + * flag [IN] + * REQUEST_WITH_PART_ID + * - If set, RM will try to assign execution partition id requested by clients. + * This flag is only supported on vGPU enabled RM build and will be removed + * when vgpu plugin implements virtualized execution partition ID support. + * (bug 2938187) + * + * REQUEST_AT_SPAN + * - If set, RM will try to assign execution partition resources at the specified span. + * This flag currently is only useful for chips in which CTS IDs are mandatory in RM, + * as it allows the requester to position compute instances without using RM best fit + * allocation. + * + * execPartCount[IN] + * - Number of execution partitions requested + * + * execPartInfo[IN] + * - Requested execution partition resources for each requested partition + * + * execPartId[OUT] + * - ID of each requested execution partition + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_WITH_PART_ID 0:0 +#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_WITH_PART_ID_FALSE (0x00000000) +#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_WITH_PART_ID_TRUE (0x00000001) +#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_AT_SPAN 1:1 +#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_AT_SPAN_FALSE (0x00000000) +#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_AT_SPAN_TRUE (0x00000001) + +#define NVC637_CTRL_CMD_EXEC_PARTITIONS_CREATE (0xc6370101) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_MESSAGE_ID" */ + +/*! + * NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS + * + * This command will delete requested execution partitions. + * + * execPartCount[IN] + * - Number of execution partitions to delete. + * + * execPartId[IN] + * - Execution partition IDs to delete + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS { + NvBool bQuery; + NvU32 flags; + NvU32 execPartCount; + // C form: NVC637_CTRL_EXEC_PARTITIONS_INFO execPartInfo[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + NVC637_CTRL_EXEC_PARTITIONS_INFO execPartInfo[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + // C form: NvU32 execPartId[NVC637_CTRL_MAX_EXECUTION_PARTITIONS]; + NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS]; +} NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS; +#define NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS { + NvU32 execPartCount; + NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS]; +} NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS; + +#define NVC637_CTRL_CMD_EXEC_PARTITIONS_DELETE (0xc6370102) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_MESSAGE_ID" */ + +/*! + * NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS + * + * This command will return information about execution partitions which + * currently exist within the subscribed memory partition. + * + * execPartCount[OUT] + * - Number of existing execution partitions + * + * execPartId[OUT] + * - ID of existing execution partitions + * + * execPartInfo[OUT] + * - Resources within each existing execution partition + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS { + NvU32 execPartCount; + // C form: NvU32 execPartId[NVC637_CTRL_MAX_EXECUTION_PARTITIONS]; + NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + // C form: NVC637_CTRL_EXEC_PARTITIONS_INFO execPartInfo[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + NVC637_CTRL_EXEC_PARTITIONS_INFO execPartInfo[NVC637_CTRL_MAX_EXEC_PARTITIONS]; +} NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS; + +#define NVC637_CTRL_CMD_EXEC_PARTITIONS_GET (0xc6370103) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_MESSAGE_ID" */ + +/*! + * NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS + * + * This command will return IDs of all active execution partitions in a memory + * partition + * + * execPartCount[OUT] + * - Number of existing execution partitions + * + * execPartId[OUT] + * - ID of existing execution partitions + * + * execPartUuid[OUT] + * - ASCII UUID string of existing execution partitions + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +/* 'M' 'I' 'G' '-'(x5), '\0x0', extra = 9 */ +#define NVC637_UUID_LEN 16 +#define NVC637_UUID_STR_LEN (0x29) /* finn: Evaluated from "((NVC637_UUID_LEN << 1) + 9)" */ + +typedef struct NVC637_EXEC_PARTITION_UUID { + // C form: char str[NVC638_UUID_STR_LEN]; + char str[NVC637_UUID_STR_LEN]; +} NVC637_EXEC_PARTITION_UUID; + +#define NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS { + NvU32 execPartCount; + + // C form: NvU32 execPartId[NVC637_CTRL_MAX_EXECUTION_PARTITIONS]; + NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + + // C form: NVC637_EXEC_PARTITION_UUID execPartUuid[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + NVC637_EXEC_PARTITION_UUID execPartUuid[NVC637_CTRL_MAX_EXEC_PARTITIONS]; +} NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS; + +#define NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS (0xc6370104) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS_MESSAGE_ID" */ + +/* + * NVC637_CTRL_CMD_EXEC_PARTITIONS_EXPORT + * + * Export the resource and placement information about an exec partition such + * that a similar partition can be recreated from scratch in the same position. + */ +#define NVC637_CTRL_CMD_EXEC_PARTITIONS_EXPORT (0xc6370105) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | 0x5" */ + +/* + * NVC637_CTRL_CMD_EXEC_PARTITIONS_IMPORT + * + * Create an exec partition resembling the exported partition info. The imported + * partition should behave identically with respect to fragmentation. + */ +#define NVC637_CTRL_CMD_EXEC_PARTITIONS_IMPORT (0xc6370106) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | 0x6" */ + +#define NVC637_CTRL_EXEC_PARTITIONS_EXPORT_MAX_ENGINES_MASK_SIZE 4 +typedef struct NVC637_CTRL_EXEC_PARTITIONS_EXPORTED_INFO { + NV_DECLARE_ALIGNED(NvU64 enginesMask[NVC637_CTRL_EXEC_PARTITIONS_EXPORT_MAX_ENGINES_MASK_SIZE], 8); + NvU8 uuid[NVC637_UUID_LEN]; + NvU32 sharedEngFlags; + NvU32 gpcMask; + NvU32 veidOffset; + NvU32 veidCount; + NvU32 smCount; + NvU32 spanStart; + NvU32 computeSize; +} NVC637_CTRL_EXEC_PARTITIONS_EXPORTED_INFO; + +typedef struct NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS { + NvU32 id; + NV_DECLARE_ALIGNED(NVC637_CTRL_EXEC_PARTITIONS_EXPORTED_INFO info, 8); +} NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS; + +/* + * NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN + * + * This struct represents the span of a compute instance, which represents the + * resource slots a given partition occupies (or may occupy) within a fixed range which + * is defined per-chip. A partition containing more resources will cover more + * resource slots and therefore cover a larger span. + * + * lo + * - The starting unit of this span, inclusive + * + * hi + * - The ending unit of this span, inclusive + * + */ +typedef struct NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN { + NV_DECLARE_ALIGNED(NvU64 lo, 8); + NV_DECLARE_ALIGNED(NvU64 hi, 8); +} NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN; + +/* + * NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY + * + * This command returns the count of compute instances which can be created + * of the given commpute profile size (represented by the computeSize field + * within a profile) which can be requested via NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILES + * Note that this API does not "reserve" any partitions, and there is no + * guarantee that the reported count of available partitions of a given size + * will remain consistent following creation of partitions of different size + * through NV2080_CTRL_GPU_SET_PARTITIONS. + * Note that this API is unsupported if SMC is feature-disabled. + * Note that the caller of this CTRL must be subscribed to a valid GPU instance + * + * computeSize[IN] + * - Partition flag indicating size of requested profile + * + * profileCount[OUT] + * - Available number of profiles of the given size which can currently be created. + * + * availableSpans[OUT] + * - For each profile able to be created of the specified size, the span + * it could occupy. + * + * availableSpansCount[OUT] + * - Number of valid entries in availableSpans. + * + * totalProfileCount[OUT] + * - Total number of profiles of the given size which can be created. + * + * totalSpans[OUT] + * - List of spans which can possibly be occupied by profiles of the + * given type. + * + * totalSpansCount[OUT] + * - Number of valid entries in totalSpans. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NVC637_CTRL_CMD_EXEC_PARTITIONS_GET_PROFILE_CAPACITY (0xc63701a9U) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS_MESSAGE_ID" */ + +#define NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS_MESSAGE_ID (0xA9U) + +typedef struct NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS { + NvU32 computeSize; + NvU32 profileCount; + NV_DECLARE_ALIGNED(NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN availableSpans[NVC637_CTRL_MAX_EXEC_PARTITIONS], 8); + NvU32 availableSpansCount; + NvU32 totalProfileCount; + NV_DECLARE_ALIGNED(NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN totalSpans[NVC637_CTRL_MAX_EXEC_PARTITIONS], 8); + NvU32 totalSpansCount; +} NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS; + +// _ctrlc637_h_ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc638.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc638.h new file mode 100644 index 0000000..f9cf5fb --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc638.h @@ -0,0 +1,91 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc638.finn +// + +#include "ctrl/ctrlxxxx.h" +/* AMPERE_SMC_EXEC_PARTITION_REF commands and parameters */ + +#define NVC638_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xC638, NVC638_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NVC638_CTRL_RESERVED (0x00) +#define NVC638_CTRL_EXEC_PARTITION (0x01) + +/*! + * NVC638_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVC638_CTRL_CMD_NULL (0xc6380000) /* finn: Evaluated from "(FINN_AMPERE_SMC_EXEC_PARTITION_REF_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/*! + * NVC638_CTRL_CMD_GET_UUID + * + * This command returns SHA1 ASCII UUID string as well as the binary UUID for + * the execution partition. The ASCII string format is, + * "MIG-%16x-%08x-%08x-%08x-%024x" (the canonical format of a UUID) + * + * uuid[OUT] + * - Raw UUID bytes + * + * uuidStr[OUT] + * - ASCII UUID string + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + */ + +#define NVC638_UUID_LEN 16 + +/* 'M' 'I' 'G' '-'(x5), '\0x0', extra = 9 */ +#define NVC638_UUID_STR_LEN (0x29) /* finn: Evaluated from "((NVC638_UUID_LEN << 1) + 9)" */ + + + +#define NVC638_CTRL_CMD_GET_UUID (0xc6380101) /* finn: Evaluated from "(FINN_AMPERE_SMC_EXEC_PARTITION_REF_EXEC_PARTITION_INTERFACE_ID << 8) | NVC638_CTRL_GET_UUID_PARAMS_MESSAGE_ID" */ + + + +#define NVC638_CTRL_GET_UUID_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC638_CTRL_GET_UUID_PARAMS { + // C form: NvU8 uuid[NVC638_UUID_LEN]; + NvU8 uuid[NVC638_UUID_LEN]; + + // C form: char uuidStr[NVC638_UUID_STR_LEN]; + char uuidStr[NVC638_UUID_STR_LEN]; +} NVC638_CTRL_GET_UUID_PARAMS;// _ctrlc638_h_ diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc86f.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc86f.h new file mode 100644 index 0000000..eeb8923 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlc86f.h @@ -0,0 +1,165 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. +*/ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc86f.finn +// + + + +#include "nvcfg_sdk.h" + + + +/* HOPPER_CHANNEL_GPFIFO_A control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl906f.h" /* C36F is partially derived from 906F */ +#include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */ +#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F + +#define NVC86F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xC36F, NVC86F_CTRL_##cat, idx) + +/* HOPPER_CHANNEL_GPFIFO_A command categories (6bits) */ +#define NVC86F_CTRL_RESERVED (0x00) +#define NVC86F_CTRL_GPFIFO (0x01) +#define NVC86F_CTRL_EVENT (0x02) + +/* + * NVC86F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned is: NV_OK +*/ +#define NVC86F_CTRL_CMD_NULL (NVC36F_CTRL_CMD_NULL) + + + + + + +/* + * NVC86F_CTRL_GET_CLASS_ENGINEID + * + * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. + * + */ +#define NVC86F_CTRL_GET_CLASS_ENGINEID (NVC36F_CTRL_GET_CLASS_ENGINEID) + +typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC86F_CTRL_GET_CLASS_ENGINEID_PARAMS; + +/* + * NVC86F_CTRL_RESET_CHANNEL + * + * Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information. + * + */ +#define NVC86F_CTRL_CMD_RESET_CHANNEL (NVC36F_CTRL_CMD_RESET_CHANNEL) + +typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC86F_CTRL_CMD_RESET_CHANNEL_PARAMS; + +/* + * NVC86F_CTRL_CMD_GPFIFO_SCHEDULE + * + * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. + * + */ +#define NVC86F_CTRL_CMD_GPFIFO_SCHEDULE (NVC36F_CTRL_CMD_GPFIFO_SCHEDULE) + +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC86F_CTRL_GPFIFO_SCHEDULE_PARAMS; + +/* + * NVC86F_CTRL_CMD_BIND + * + * Please see description of NVA06F_CTRL_CMD_BIND for more information. + */ +#define NVC86F_CTRL_CMD_BIND (NVC36F_CTRL_CMD_BIND) + +typedef NVA06F_CTRL_BIND_PARAMS NVC86F_CTRL_BIND_PARAMS; + +/* + * NVC86F_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. +*/ +#define NVC86F_CTRL_CMD_EVENT_SET_NOTIFICATION (NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION) + +typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC86F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NVC86F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE +#define NVC86F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE +#define NVC86F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT + +/* + * NVC86F_CTRL_CMD_EVENT_SET_TRIGGER + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information. + */ +#define NVC86F_CTRL_CMD_EVENT_SET_TRIGGER (NVC36F_CTRL_CMD_EVENT_SET_TRIGGER) + + + + + +/* + * NVC86F_CTRL_CMD_GET_MMU_FAULT_INFO + * + * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. + * + */ +#define NVC86F_CTRL_CMD_GET_MMU_FAULT_INFO (NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO) + +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC86F_CTRL_GET_MMU_FAULT_INFO_PARAMS; + +/* + * NVC86F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN + * + * This command returns an opaque work submit token to the caller which + * can be used to write to doorbell register to finish submitting work. + * + * workSubmitToken The 32-bit work submit token + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + * + */ + +#define NVC86F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN (NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN) + +typedef struct NVC86F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS { + NvU32 workSubmitToken; +} NVC86F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS; + +/* _ctrlC86F.h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlcbca.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlcbca.h new file mode 100644 index 0000000..1e47dec --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlcbca.h @@ -0,0 +1,120 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlcbca.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV_COUNTER_COLLECTION_UNIT control commands and parameters */ + +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xCBCA, NVCBCA_CTRL_##cat, idx) + +#define NVCBCA_CTRL_RESERVED (0x00) +#define NVCBCA_CTRL_COUNTER_COLLECTION_UNIT (0x01) + +/* + * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible return values: + * NV_OK + */ +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_NULL (0xcbca0000) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_SUBSCRIBE + * + * This command is used to subscribe performance counter data + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_SUBSCRIBE (0xcbca0101) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID << 8) | NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS_MESSAGE_ID" */ + +#define NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 bufferSize, 8); + NvU32 counterBlockSize; +} NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS; + +/* + * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_UNSUBSCRIBE + * + * This command is used to unsubscribe performance counter data + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_UNSUBSCRIBE (0xcbca0102) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID << 8) | 0x2" */ + +/* + * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_SET_STREAM_STATE + * + * This command is used to set the counter collection unit stream state + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_SET_STREAM_STATE (0xcbca0103) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID << 8) | NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS_MESSAGE_ID" */ + +#define NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS { + NvBool bStreamState; +} NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS; + +/* + * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_GET_STREAM_STATE + * + * This command is used to get the counter collection unit stream state + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_GET_STREAM_STATE (0xcbca0104) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID << 8) | 0x4" */ + +/* _ctrlcbca_h_ */ + diff --git a/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlxxxx.h b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlxxxx.h new file mode 100644 index 0000000..efe0c58 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/ctrl/ctrlxxxx.h @@ -0,0 +1,67 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2008,2013,2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlxxxx.finn +// + + + +#include "nvtypes.h" + +/* definitions shared by all CTRL interfaces */ + +/* Basic command format: +* cmd_class [31:16], +* cmd_reserved [15:15], +* cmd_reserved [14:14], +* cmd_category [13:8], +* cmd_index [7:0] +*/ + +#define NVXXXX_CTRL_CMD_CLASS 31:16 + +#define NVXXXX_CTRL_CMD_CATEGORY 13:8 +#define NVXXXX_CTRL_CMD_INDEX 7:0 + +/* don't use DRF_NUM - not always available */ +# define NVXXXX_CTRL_CMD(cls,cat,idx) \ + (((cls) << 16) | ((0) << 15) | ((0) << 14) \ + | ((cat) << 8) | ((idx) & 0xFF)) +/* + * NVXXXX_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * This command is valid for all classes. + * + * Possible status values returned are: + * NV_OK + */ +#define NVXXXX_CTRL_CMD_NULL (0x00000000) + +#define NVxxxx_CTRL_LEGACY_PRIVILEGED (0xC0) +#define NVxxxx_CTRL_LEGACY_NON_PRIVILEGED (0x80) diff --git a/userspace/sdks/nv525/nvidia/inc/dpringbuffertypes.h b/userspace/sdks/nv525/nvidia/inc/dpringbuffertypes.h new file mode 100644 index 0000000..b61abaf --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/dpringbuffertypes.h @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2002-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef INCLUDED_DPRINGBUFFERTYPES_H +#define INCLUDED_DPRINGBUFFERTYPES_H + +#define MAX_MESSAGE_LEN 100 +#define MAX_RECORD_COUNT 15 + +typedef enum _DP_RECORD_TYPE +{ + ASSERT_HIT = 135, + LOG_CALL = 136, +} DP_RECORD_TYPE; + +typedef struct _DpAssertHitRecord +{ + NvU64 breakpointAddr; +} DpAssertHitRecord, *PDpAssertHitRecord; + +typedef struct _DpLogCallRecord +{ + char msg[MAX_MESSAGE_LEN]; + NvU64 addr; +} DpLogCallRecord, *PDpLogCallRecord; + +typedef union _DpLogRecord +{ + DpAssertHitRecord dpAssertHitRecord; + DpLogCallRecord dpLogCallRecord; +} DpLogRecord, *PDpLogRecord; + +typedef enum _DpLogQueryType +{ + DpLogQueryTypeAssert = 1, + DpLogQueryTypeCallLog = 2, +} DpLogQueryType, *PDpLogQueryType; + +#endif //INCLUDED_DPRINGBUFFERTYPES_H diff --git a/userspace/sdks/nv525/nvidia/inc/finn_rm_api.h b/userspace/sdks/nv525/nvidia/inc/finn_rm_api.h new file mode 100644 index 0000000..0722dd9 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/finn_rm_api.h @@ -0,0 +1,709 @@ +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// + + +#include + + +#include +#include + +#define FINN_INTERFACE_ID(T) (T ## _INTERFACE_ID) +#define FINN_MESSAGE_ID(T) (T ## _MESSAGE_ID) + +#if (defined(__cplusplus) && __cplusplus >= 201103L) || (defined(_MSVC_LANG) && _MSVC_LANG >= 201103L) +#define FINN_OFFSETOF(T,f) (offsetof(T, f)) +#else +#define FINN_OFFSETOF(T,f) ((NvU64)&((T*)0)->f) +#endif + +#if !defined(_MSC_VER) && (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L) && !defined(__arm) +#define FINN_PACK_COMPOSITE(b) b __attribute__ ((packed)) +#else +#define FINN_PACK_COMPOSITE(b) b +#endif + +/* + * FINN serialization version. A version mismatch indicates incompatibility + * between the serializer and the deserializer. + * + * WARNING: Current serialization version is 0. This is a pre-release version of + * serialization and is only intended to be used in a driver and client compiled + * together. DO NOT use this in firmware or versioned clients. + */ +#define FINN_SERIALIZATION_VERSION 0 + +/* + * FINN compiler version + */ +#define FINN_VERSION_MAJOR 1 +#define FINN_VERSION_MINOR 14 +#define FINN_VERSION_PATCH 0 + +typedef struct FINN_RM_API +{ + NV_DECLARE_ALIGNED(NvU64 version, 8); + NV_DECLARE_ALIGNED(NvU64 payloadSize, 8); + NV_DECLARE_ALIGNED(NvU64 interface, 8); + NV_DECLARE_ALIGNED(NvU64 message, 8); +} FINN_RM_API; + + +/*! + * @brief Serializes an RM API control params struct and copies it into the + * serialization buffer as a FINN message. + * + * @note FinnRmApiSerializeDown is for serializing down the call stack. + * + * FinnRmApiSerializeUp is for serializing up the call stack. It + * frees memory allocated by FinnRmApiDeserializeDown. Use only + * when handling RM API control requests. + * + * @warning One of these may be unimplemented depending on platform. If both + * are implemented, misuse causes memory corruption and memory leaks. + * + * @param[in] interface FINN interface ID of the param struct. + * @param[in] message FINN message ID of the param struct. + * @param[in] src Pointer to the source param struct from which to + * copy the data. + * @param[in, out] dst Double pointer to the destination buffer into + * which to copy the data. *dst will be set to + * *dst + serialized size on success and to the + * location of failed serialization on failure. + * @param[in] dst_size Maximum size of the destination buffer measured in + * `NvU8` units. + * + * @retval NV_OK Serialization successful. + * @retval NV_ERR_INVALID_ARGUMENT Bad function arguments, invalid union + * selector, or invalid enum value. + * @retval NV_ERR_NOT_SUPPORTED Unserializable or nonexistent ID. + * @retval NV_ERR_NOT_COMPATIBLE Container count too large. + * @retval NV_ERR_OUT_OF_RANGE Ranged field exceeded bounds. + * @retval NV_ERR_BUFFER_TOO_SMALL Destination buffer size too small. + */ +/**@{*/ +NV_STATUS FinnRmApiSerializeUp(NvU64 interface, NvU64 message, const void *src, NvU8 **dst, NvLength dst_size); +NV_STATUS FinnRmApiSerializeDown(NvU64 interface, NvU64 message, const void *src, NvU8 **dst, NvLength dst_size); +/**@}*/ + + +/*! + * @brief The following APIs deserialize a FINN message from the serialization + * buffer and copy it into an RM API control params struct. + * + * @note FinnRmApiDeserializeDown is for deserializing down the call stack. It + * allocates deep buffers for primitive pointers in the serialization + * buffer, assuming that it remains in memory. Use only when handling + * RM API control requests. + * + * FinnRmApiDeserializeUp is for deserializing up the call stack. It + * copies deep buffers of primitive pointers into the params struct, + * assuming that memory is already allocated for them. Use only when + * receiving RM API control results. + * + * @warning One of these may be unimplemented depending on platform. If both + * are implemented, misuse causes memory corruption and memory leaks. + * + * @param[in, out] src Double pointer to the source buffer from which to + * copy the data. *src is set to *src + serialized + * size on success and to the location of failed + * deserialization on failure. + * @param[in] src_size Maximum size of the source buffer measured in + * `NvU8` units. + * @param[in, out] dst Pointer to the destination param struct into which + * to copy the data. + * @param[in] dst_size Size of the destination param struct measured in + * `char` units per `sizeof` operator. + * + * @retval NV_OK Deserialization successful. + * @retval NV_ERR_INVALID_ARGUMENT Bad function arguments, invalid union + * selector, invalid enum value, or + * mismatch between expected and actual + * serialized size. + * @retval NV_ERR_NOT_SUPPORTED Unserializable or nonexistent ID. + * @retval NV_ERR_OUT_OF_RANGE Ranged field exceeded bounds. + * @retval NV_ERR_BUFFER_TOO_SMALL Source/destination buffer too small. + * @retval NV_ERR_LIB_RM_VERSION_MISMATCH Version mismatch. + */ +/**@{*/ +NV_STATUS FinnRmApiDeserializeDown(NvU8 **src, NvLength src_size, void *dst, NvLength dst_size); +NV_STATUS FinnRmApiDeserializeUp(NvU8 * const *src, NvLength src_size, void *dst, NvLength dst_size); +/**@}*/ + +/*! + * @brief Calculates the serialized size of an RM API param struct. + * + * @param[in] interface FINN interface ID of the param struct. + * @param[in] message FINN message ID of the param struct. + * @param[in] src Pointer to the param struct. + * + * @retval Non-zero serialized size of param struct on success. + * @retval 0 if the API is unsupported by serialization or src is NULL. + */ +NvU64 FinnRmApiGetSerializedSize(NvU64 interface, NvU64 message, const NvP64 src); + +/*! + * @brief Fetches the unserialized size of an API param struct. + * + * @note The size is measured in `char` units like the `sizeof` operator. + * + * @param[in] interface FINN interface ID of the param struct. + * @param[in] message FINN message ID of the param struct. + * + * @retval Non-zero sizeof param struct on success. + * @retval 0 if the API is unsupported by serialization. + */ +NvU64 FinnRmApiGetUnserializedSize(NvU64 interface, NvU64 message); + +#define NV_RM_ALLOC_INTERFACE_INTERFACE_ID (0xA000U) +typedef FINN_RM_API NV_RM_ALLOC_INTERFACE; +#define FINN_NV01_ROOT_RESERVED_INTERFACE_ID (0x0U) +typedef FINN_RM_API FINN_NV01_ROOT_RESERVED; +#define FINN_NV01_ROOT_CLIENT_INTERFACE_ID (0xdU) +typedef FINN_RM_API FINN_NV01_ROOT_CLIENT; +#define FINN_NV01_ROOT_DIAG_INTERFACE_ID (0x4U) +typedef FINN_RM_API FINN_NV01_ROOT_DIAG; +#define FINN_NV01_ROOT_EVENT_INTERFACE_ID (0x5U) +typedef FINN_RM_API FINN_NV01_ROOT_EVENT; +#define FINN_NV01_ROOT_GPU_INTERFACE_ID (0x2U) +typedef FINN_RM_API FINN_NV01_ROOT_GPU; +#define FINN_NV01_ROOT_GPUACCT_INTERFACE_ID (0xbU) +typedef FINN_RM_API FINN_NV01_ROOT_GPUACCT; +#define FINN_NV01_ROOT_GSYNC_INTERFACE_ID (0x3U) +typedef FINN_RM_API FINN_NV01_ROOT_GSYNC; +#define FINN_NV01_ROOT_NVD_INTERFACE_ID (0x6U) +typedef FINN_RM_API FINN_NV01_ROOT_NVD; +#define FINN_NV01_ROOT_PROC_INTERFACE_ID (0x9U) +typedef FINN_RM_API FINN_NV01_ROOT_PROC; + +#define FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID (0xaU) +typedef FINN_RM_API FINN_NV01_ROOT_SYNC_GPU_BOOST; +#define FINN_NV01_ROOT_SYSTEM_INTERFACE_ID (0x1U) +typedef FINN_RM_API FINN_NV01_ROOT_SYSTEM; +#define FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID (0x3dU) +typedef FINN_RM_API FINN_NV01_ROOT_OS_UNIX; +#define FINN_NV01_ROOT_VGPU_INTERFACE_ID (0xcU) +typedef FINN_RM_API FINN_NV01_ROOT_VGPU; +#define FINN_NV01_ROOT_OS_WINDOWS_INTERFACE_ID (0x3fU) +typedef FINN_RM_API FINN_NV01_ROOT_OS_WINDOWS; +#define FINN_NV01_CONTEXT_DMA_RESERVED_INTERFACE_ID (0x200U) +typedef FINN_RM_API FINN_NV01_CONTEXT_DMA_RESERVED; +#define FINN_NV01_CONTEXT_DMA_DMA_INTERFACE_ID (0x201U) +typedef FINN_RM_API FINN_NV01_CONTEXT_DMA_DMA; +#define FINN_NV01_TIMER_RESERVED_INTERFACE_ID (0x400U) +typedef FINN_RM_API FINN_NV01_TIMER_RESERVED; +#define FINN_NV01_TIMER_TMR_INTERFACE_ID (0x401U) +typedef FINN_RM_API FINN_NV01_TIMER_TMR; +#define FINN_FABRIC_MANAGER_SESSION_RESERVED_INTERFACE_ID (0xf00U) +typedef FINN_RM_API FINN_FABRIC_MANAGER_SESSION_RESERVED; +#define FINN_FABRIC_MANAGER_SESSION_FM_INTERFACE_ID (0xf01U) +typedef FINN_RM_API FINN_FABRIC_MANAGER_SESSION_FM; +#define FINN_FABRIC_MANAGER_SESSION_IMEX_INTERFACE_ID (0xf02U) +typedef FINN_RM_API FINN_FABRIC_MANAGER_SESSION_IMEX; +#define FINN_NV0020_GPU_MANAGEMENT_RESERVED_INTERFACE_ID (0x2000U) +typedef FINN_RM_API FINN_NV0020_GPU_MANAGEMENT_RESERVED; +#define FINN_NV0020_GPU_MANAGEMENT_GPU_MGMT_INTERFACE_ID (0x2001U) +typedef FINN_RM_API FINN_NV0020_GPU_MANAGEMENT_GPU_MGMT; +#define FINN_NV01_MEMORY_SYSTEM_RESERVED_INTERFACE_ID (0x3e00U) +typedef FINN_RM_API FINN_NV01_MEMORY_SYSTEM_RESERVED; +#define FINN_NV01_MEMORY_SYSTEM_MEMORY_INTERFACE_ID (0x3e01U) +typedef FINN_RM_API FINN_NV01_MEMORY_SYSTEM_MEMORY; +#define FINN_NV01_ROOT_USER_RESERVED_INTERFACE_ID (0x4100U) +typedef FINN_RM_API FINN_NV01_ROOT_USER_RESERVED; +#define FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID (0x4101U) +typedef FINN_RM_API FINN_NV01_ROOT_USER_MEMORY; +#define FINN_NV04_DISPLAY_COMMON_RESERVED_INTERFACE_ID (0x7300U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_RESERVED; +#define FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID (0x7311U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_DFP; +#define FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID (0x7313U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_DP; + +#define FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID (0x7304U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_INTERNAL; + +#define FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID (0x7302U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_SPECIFIC; +#define FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID (0x7317U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_STEREO; + +#define FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID (0x7301U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_SYSTEM; +#define FINN_NV01_DEVICE_0_RESERVED_INTERFACE_ID (0x8000U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_RESERVED; +#define FINN_NV01_DEVICE_0_BIF_INTERFACE_ID (0x8001U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_BIF; +#define FINN_NV01_DEVICE_0_BSP_INTERFACE_ID (0x801cU) +typedef FINN_RM_API FINN_NV01_DEVICE_0_BSP; + +#define FINN_NV01_DEVICE_0_DMA_INTERFACE_ID (0x8018U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_DMA; +#define FINN_NV01_DEVICE_0_FB_INTERFACE_ID (0x8013U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_FB; +#define FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID (0x8017U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_FIFO; +#define FINN_NV01_DEVICE_0_GPU_INTERFACE_ID (0x8002U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_GPU; +#define FINN_NV01_DEVICE_0_GR_INTERFACE_ID (0x8011U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_GR; +#define FINN_NV01_DEVICE_0_HOST_INTERFACE_ID (0x8014U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_HOST; +#define FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID (0x8020U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_INTERNAL; +#define FINN_NV01_DEVICE_0_MSENC_INTERFACE_ID (0x801bU) +typedef FINN_RM_API FINN_NV01_DEVICE_0_MSENC; +#define FINN_NV01_DEVICE_0_NVJPG_INTERFACE_ID (0x801fU) +typedef FINN_RM_API FINN_NV01_DEVICE_0_NVJPG; +#define FINN_NV01_DEVICE_0_PERF_INTERFACE_ID (0x8019U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_PERF; + +#define FINN_NV01_DEVICE_0_RC_INTERFACE_ID (0x801dU) +typedef FINN_RM_API FINN_NV01_DEVICE_0_RC; +#define FINN_NV01_DEVICE_0_OS_UNIX_INTERFACE_ID (0x801eU) +typedef FINN_RM_API FINN_NV01_DEVICE_0_OS_UNIX; + +#define FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID (0x9001U) +typedef FINN_RM_API FINN_NV0090_KERNEL_GRAPHICS_CONTEXT; +#define FINN_IMEX_SESSION_INTERFACE_ID (0xf100U) +typedef FINN_RM_API FINN_IMEX_SESSION; +#define FINN_NV01_MEMORY_FABRIC_EXPORT_RESERVED_INTERFACE_ID (0xf400U) +typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_EXPORT_RESERVED; +#define FINN_NV01_MEMORY_FABRIC_EXPORT_EXPORT_INTERFACE_ID (0xf401U) +typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_EXPORT_EXPORT; +#define FINN_NV01_MEMORY_FABRIC_IMPORT_RESERVED_INTERFACE_ID (0xf500U) +typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_IMPORT_RESERVED; +#define FINN_NV01_MEMORY_FABRIC_IMPORT_IMPORT_INTERFACE_ID (0xf501U) +typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_IMPORT_IMPORT; +#define FINN_NV_MEMORY_FABRIC_EXPORT_RESERVED_INTERFACE_ID (0xf700U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORT_RESERVED; +#define FINN_NV_MEMORY_FABRIC_EXPORT_INTERFACE_ID (0xf701U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORT; +#define FINN_NV_MEMORY_FABRIC_RESERVED_INTERFACE_ID (0xf800U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_RESERVED; +#define FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID (0xf801U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_FABRIC; +#define FINN_NV_MEMORY_FABRIC_IMPORT_V2_RESERVED_INTERFACE_ID (0xf900U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORT_V2_RESERVED; +#define FINN_NV_MEMORY_FABRIC_IMPORT_V2_IMPORT_INTERFACE_ID (0xf901U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORT_V2_IMPORT; +#define FINN_NV_MEMORY_FABRIC_EXPORTED_REF_RESERVED_INTERFACE_ID (0xfa00U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORTED_REF_RESERVED; +#define FINN_NV_MEMORY_FABRIC_EXPORTED_REF_EXPORT_REF_INTERFACE_ID (0xfa01U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORTED_REF_EXPORT_REF; +#define FINN_NV_MEMORY_FABRIC_IMPORTED_REF_RESERVED_INTERFACE_ID (0xfb00U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORTED_REF_RESERVED; +#define FINN_NV_MEMORY_FABRIC_IMPORTED_REF_IMPORT_REF_INTERFACE_ID (0xfb01U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORTED_REF_IMPORT_REF; +#define FINN_NV_MEMORY_MULTICAST_FABRIC_RESERVED_INTERFACE_ID (0xfd00U) +typedef FINN_RM_API FINN_NV_MEMORY_MULTICAST_FABRIC_RESERVED; +#define FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID (0xfd01U) +typedef FINN_RM_API FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC; +#define FINN_NV_MEMORY_MAPPER_INTERFACE_ID (0x00FE00U) +typedef FINN_RM_API FINN_NV_MEMORY_MAPPER; + +#define FINN_NV20_SUBDEVICE_0_RESERVED_INTERFACE_ID (0x208000U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_RESERVED; +#define FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID (0x208008U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_BIOS; +#define FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID (0x208018U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_BUS; +#define FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID (0x20802aU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_CE; + +#define FINN_NV20_SUBDEVICE_0_CLK_INTERFACE_ID (0x208010U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_CLK; + +#define FINN_NV20_SUBDEVICE_0_DMA_INTERFACE_ID (0x208025U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_DMA; +#define FINN_NV20_SUBDEVICE_0_DMABUF_INTERFACE_ID (0x20803AU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_DMABUF; +#define FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID (0x208034U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_ECC; + +#define FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID (0x208003U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_EVENT; + +#define FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID (0x208013U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FB; +#define FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID (0x208011U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FIFO; +#define FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID (0x208035U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FLA; +#define FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID (0x208031U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FLCN; +#define FINN_NV20_SUBDEVICE_0_FUSE_INTERFACE_ID (0x208002U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FUSE; + +#define FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID (0x208023U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GPIO; + +#define FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID (0x208001U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GPU; + +#define FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID (0x208012U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GR; +#define FINN_NV20_SUBDEVICE_0_GRMGR_INTERFACE_ID (0x208038U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GRMGR; +#define FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID (0x208036U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GSP; +#define FINN_NV20_SUBDEVICE_0_HSHUB_INTERFACE_ID (0x208041U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_HSHUB; +#define FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID (0x208006U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_I2C; +#define FINN_NV20_SUBDEVICE_0_PMGR_INTERFACE_ID (0x208026U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_PMGR; + +#define FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID (0x20800aU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_INTERNAL; +#define FINN_NV20_SUBDEVICE_0_LPWR_INTERFACE_ID (0x208028U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_LPWR; + +#define FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID (0x208017U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_MC; + +#define FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID (0x208024U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_NVD; + +#define FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID (0x208030U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_NVLINK; + +#define FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID (0x208020U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_PERF; + +#define FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID (0x208022U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_RC; +#define FINN_NV20_SUBDEVICE_0_SEC2_INTERFACE_ID (0x208042U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_SEC2; + +#define FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID (0x208004U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_TIMER; + +#define FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID (0x20803dU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_OS_UNIX; +#define FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID (0x208040U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL; +#define FINN_NV20_SUBDEVICE_0_VOLT_INTERFACE_ID (0x208032U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_VOLT; + +#define FINN_NV2081_BINAPI_RESERVED_INTERFACE_ID (0x208100U) +typedef FINN_RM_API FINN_NV2081_BINAPI_RESERVED; +#define FINN_NV2081_BINAPI_INTERFACE_ID (0x208101U) +typedef FINN_RM_API FINN_NV2081_BINAPI; +#define FINN_NV2082_BINAPI_RESERVED_INTERFACE_ID (0x208200U) +typedef FINN_RM_API FINN_NV2082_BINAPI_RESERVED; +#define FINN_NV2082_BINAPI_INTERFACE_ID (0x208201U) +typedef FINN_RM_API FINN_NV2082_BINAPI; +#define FINN_NV20_SUBDEVICE_DIAG_RESERVED_INTERFACE_ID (0x208f00U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_RESERVED; +#define FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID (0x208f07U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_BIF; +#define FINN_NV20_SUBDEVICE_DIAG_BUS_INTERFACE_ID (0x208f18U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_BUS; + +#define FINN_NV20_SUBDEVICE_DIAG_DMA_INTERFACE_ID (0x208f14U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_DMA; +#define FINN_NV20_SUBDEVICE_DIAG_EVENT_INTERFACE_ID (0x208f10U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_EVENT; +#define FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID (0x208f05U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_FB; +#define FINN_NV20_SUBDEVICE_DIAG_FBIO_INTERFACE_ID (0x208f0aU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_FBIO; +#define FINN_NV20_SUBDEVICE_DIAG_FIFO_INTERFACE_ID (0x208f04U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_FIFO; +#define FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID (0x208f11U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_GPU; +#define FINN_NV20_SUBDEVICE_DIAG_GR_INTERFACE_ID (0x208f12U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_GR; + +#define FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID (0x208f0bU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_MMU; + +#define FINN_NV30_GSYNC_RESERVED_INTERFACE_ID (0x30f100U) +typedef FINN_RM_API FINN_NV30_GSYNC_RESERVED; +#define FINN_NV30_GSYNC_GSYNC_INTERFACE_ID (0x30f101U) +typedef FINN_RM_API FINN_NV30_GSYNC_GSYNC; +#define FINN_NV40_I2C_RESERVED_INTERFACE_ID (0x402c00U) +typedef FINN_RM_API FINN_NV40_I2C_RESERVED; +#define FINN_NV40_I2C_I2C_INTERFACE_ID (0x402c01U) +typedef FINN_RM_API FINN_NV40_I2C_I2C; +#define FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID (0x503c01U) +typedef FINN_RM_API FINN_NV50_THIRD_PARTY_P2P_P2P; +#define FINN_NV50_THIRD_PARTY_P2P_RESERVED_INTERFACE_ID (0x503c00U) +typedef FINN_RM_API FINN_NV50_THIRD_PARTY_P2P_RESERVED; +#define FINN_NV50_CHANNEL_GPFIFO_RESERVED_INTERFACE_ID (0x506f00U) +typedef FINN_RM_API FINN_NV50_CHANNEL_GPFIFO_RESERVED; +#define FINN_NV50_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID (0x506f01U) +typedef FINN_RM_API FINN_NV50_CHANNEL_GPFIFO_GPFIFO; +#define FINN_NV50_DISPLAY_RESERVED_INTERFACE_ID (0x507000U) +typedef FINN_RM_API FINN_NV50_DISPLAY_RESERVED; +#define FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID (0x507001U) +typedef FINN_RM_API FINN_NV50_DISPLAY_CHNCTL; +#define FINN_NV50_DISPLAY_EVENT_INTERFACE_ID (0x507009U) +typedef FINN_RM_API FINN_NV50_DISPLAY_EVENT; +#define FINN_NV50_DISPLAY_OR_INTERFACE_ID (0x507004U) +typedef FINN_RM_API FINN_NV50_DISPLAY_OR; +#define FINN_NV50_DISPLAY_RG_INTERFACE_ID (0x507002U) +typedef FINN_RM_API FINN_NV50_DISPLAY_RG; +#define FINN_NV50_DISPLAY_SEQ_INTERFACE_ID (0x507003U) +typedef FINN_RM_API FINN_NV50_DISPLAY_SEQ; +#define FINN_NV50_DISPLAY_SYSTEM_INTERFACE_ID (0x507007U) +typedef FINN_RM_API FINN_NV50_DISPLAY_SYSTEM; + +#define FINN_NV50_DEFERRED_API_CLASS_RESERVED_INTERFACE_ID (0x508000U) +typedef FINN_RM_API FINN_NV50_DEFERRED_API_CLASS_RESERVED; +#define FINN_NV50_DEFERRED_API_CLASS_DEFERRED_INTERFACE_ID (0x508001U) +typedef FINN_RM_API FINN_NV50_DEFERRED_API_CLASS_DEFERRED; +#define FINN_GT200_DEBUGGER_RESERVED_INTERFACE_ID (0x83de00U) +typedef FINN_RM_API FINN_GT200_DEBUGGER_RESERVED; +#define FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID (0x83de03U) +typedef FINN_RM_API FINN_GT200_DEBUGGER_DEBUG; +#define FINN_GT200_DEBUGGER_FIFO_INTERFACE_ID (0x83de02U) +typedef FINN_RM_API FINN_GT200_DEBUGGER_FIFO; +#define FINN_GT200_DEBUGGER_INTERNAL_INTERFACE_ID (0x83de04U) +typedef FINN_RM_API FINN_GT200_DEBUGGER_INTERNAL; + +#define FINN_NV9010_VBLANK_CALLBACK_RESERVED_INTERFACE_ID (0x901000U) +typedef FINN_RM_API FINN_NV9010_VBLANK_CALLBACK_RESERVED; +#define FINN_NV9010_VBLANK_CALLBACK_INTERFACE_ID (0x901001U) +typedef FINN_RM_API FINN_NV9010_VBLANK_CALLBACK; +#define FINN_FERMI_CONTEXT_SHARE_A_RESERVED_INTERFACE_ID (0x906700U) +typedef FINN_RM_API FINN_FERMI_CONTEXT_SHARE_A_RESERVED; +#define FINN_FERMI_CONTEXT_SHARE_A_TPC_PARTITION_INTERFACE_ID (0x906701U) +typedef FINN_RM_API FINN_FERMI_CONTEXT_SHARE_A_TPC_PARTITION; +#define FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID (0x906702U) +typedef FINN_RM_API FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK; +#define FINN_GF100_CHANNEL_GPFIFO_RESERVED_INTERFACE_ID (0x906f00U) +typedef FINN_RM_API FINN_GF100_CHANNEL_GPFIFO_RESERVED; +#define FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID (0x906f01U) +typedef FINN_RM_API FINN_GF100_CHANNEL_GPFIFO_GPFIFO; +#define FINN_GF100_CHANNEL_GPFIFO_EVENT_INTERFACE_ID (0x906f02U) +typedef FINN_RM_API FINN_GF100_CHANNEL_GPFIFO_EVENT; +#define FINN_GF100_DISP_SW_RESERVED_INTERFACE_ID (0x907200U) +typedef FINN_RM_API FINN_GF100_DISP_SW_RESERVED; +#define FINN_GF100_DISP_SW_DISP_SW_INTERFACE_ID (0x907201U) +typedef FINN_RM_API FINN_GF100_DISP_SW_DISP_SW; +#define FINN_GF100_TIMED_SEMAPHORE_SW_RESERVED_INTERFACE_ID (0x907400U) +typedef FINN_RM_API FINN_GF100_TIMED_SEMAPHORE_SW_RESERVED; +#define FINN_GF100_TIMED_SEMAPHORE_SW_SEM_INTERFACE_ID (0x907401U) +typedef FINN_RM_API FINN_GF100_TIMED_SEMAPHORE_SW_SEM; +#define FINN_GF100_REMAPPER_RESERVED_INTERFACE_ID (0x907f00U) +typedef FINN_RM_API FINN_GF100_REMAPPER_RESERVED; +#define FINN_GF100_REMAPPER_REMAPPER_INTERFACE_ID (0x907f01U) +typedef FINN_RM_API FINN_GF100_REMAPPER_REMAPPER; +#define FINN_GF100_ZBC_CLEAR_RESERVED_INTERFACE_ID (0x909600U) +typedef FINN_RM_API FINN_GF100_ZBC_CLEAR_RESERVED; +#define FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID (0x909601U) +typedef FINN_RM_API FINN_GF100_ZBC_CLEAR_ZBC; +#define FINN_GF100_PROFILER_RESERVED_INTERFACE_ID (0x90cc00U) +typedef FINN_RM_API FINN_GF100_PROFILER_RESERVED; +#define FINN_GF100_PROFILER_HWPM_INTERFACE_ID (0x90cc01U) +typedef FINN_RM_API FINN_GF100_PROFILER_HWPM; +#define FINN_GF100_PROFILER_NVLINK_INTERFACE_ID (0x90cc02U) +typedef FINN_RM_API FINN_GF100_PROFILER_NVLINK; +#define FINN_GF100_PROFILER_POWER_INTERFACE_ID (0x90cc03U) +typedef FINN_RM_API FINN_GF100_PROFILER_POWER; +#define FINN_NV_EVENT_BUFFER_RESERVED_INTERFACE_ID (0x90cd00U) +typedef FINN_RM_API FINN_NV_EVENT_BUFFER_RESERVED; +#define FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID (0x90cd01U) +typedef FINN_RM_API FINN_NV_EVENT_BUFFER_EVENT; +#define FINN_GF100_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0x90e000U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_GRAPHICS_RESERVED; +#define FINN_GF100_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0x90e001U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_GRAPHICS_GRAPHICS; +#define FINN_GF100_SUBDEVICE_FB_RESERVED_INTERFACE_ID (0x90e100U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_FB_RESERVED; +#define FINN_GF100_SUBDEVICE_FB_FB_INTERFACE_ID (0x90e101U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_FB_FB; +#define FINN_GF100_SUBDEVICE_MASTER_RESERVED_INTERFACE_ID (0x90e600U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_MASTER_RESERVED; +#define FINN_GF100_SUBDEVICE_MASTER_MASTER_INTERFACE_ID (0x90e601U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_MASTER_MASTER; +#define FINN_GF100_SUBDEVICE_INFOROM_RESERVED_INTERFACE_ID (0x90e700U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_RESERVED; +#define FINN_GF100_SUBDEVICE_INFOROM_BBX_INTERFACE_ID (0x90e701U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_BBX; +#define FINN_GF100_SUBDEVICE_INFOROM_RPR_INTERFACE_ID (0x90e702U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_RPR; + +#define FINN_GF100_HDACODEC_RESERVED_INTERFACE_ID (0x90ec00U) +typedef FINN_RM_API FINN_GF100_HDACODEC_RESERVED; +#define FINN_GF100_HDACODEC_HDACODEC_INTERFACE_ID (0x90ec01U) +typedef FINN_RM_API FINN_GF100_HDACODEC_HDACODEC; +#define FINN_FERMI_VASPACE_A_RESERVED_INTERFACE_ID (0x90f100U) +typedef FINN_RM_API FINN_FERMI_VASPACE_A_RESERVED; +#define FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID (0x90f101U) +typedef FINN_RM_API FINN_FERMI_VASPACE_A_VASPACE; +#define FINN_KEPLER_CHANNEL_GROUP_A_RESERVED_INTERFACE_ID (0xa06c00U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GROUP_A_RESERVED; +#define FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID (0xa06c01U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO; +#define FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID (0xa06c02U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL; +#define FINN_KEPLER_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xa06f00U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_KEPLER_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xa06f02U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_EVENT; +#define FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xa06f01U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID (0xa06f03U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL; + +#define FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID (0xa08001U) +typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY; +#define FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID (0xa08002U) +typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY; +#define FINN_KEPLER_DEVICE_VGPU_VGPU_OTHERS_INTERFACE_ID (0xa08003U) +typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_VGPU_OTHERS; +#define FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID (0xa08101U) +typedef FINN_RM_API FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG; + +#define FINN_NVA083_GRID_DISPLAYLESS_RESERVED_INTERFACE_ID (0xa08300U) +typedef FINN_RM_API FINN_NVA083_GRID_DISPLAYLESS_RESERVED; +#define FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY_INTERFACE_ID (0xa08301U) +typedef FINN_RM_API FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY; +#define FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID (0xa08401U) +typedef FINN_RM_API FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE; +#define FINN_NVENC_SW_SESSION_NVENC_SW_SESSION_INTERFACE_ID (0xa0bc01U) +typedef FINN_RM_API FINN_NVENC_SW_SESSION_NVENC_SW_SESSION; +#define FINN_NVFBC_SW_SESSION_NVFBC_SW_SESSION_INTERFACE_ID (0xa0bd01U) +typedef FINN_RM_API FINN_NVFBC_SW_SESSION_NVFBC_SW_SESSION; +#define FINN_GK110_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0xa0e000U) +typedef FINN_RM_API FINN_GK110_SUBDEVICE_GRAPHICS_RESERVED; +#define FINN_GK110_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0xa0e001U) +typedef FINN_RM_API FINN_GK110_SUBDEVICE_GRAPHICS_GRAPHICS; +#define FINN_GK110_SUBDEVICE_FB_RESERVED_INTERFACE_ID (0xa0e100U) +typedef FINN_RM_API FINN_GK110_SUBDEVICE_FB_RESERVED; +#define FINN_GK110_SUBDEVICE_FB_FB_INTERFACE_ID (0xa0e101U) +typedef FINN_RM_API FINN_GK110_SUBDEVICE_FB_FB; +#define FINN_KEPLER_CHANNEL_GPFIFO_B_RESERVED_INTERFACE_ID (0xa16f00U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_B_RESERVED; +#define FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID (0xa16f01U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO; +#define FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID (0xa16f02U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT; +#define FINN_KEPLER_CHANNEL_GPFIFO_C_RESERVED_INTERFACE_ID (0xa26f00U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_C_RESERVED; +#define FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID (0xa26f01U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO; +#define FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID (0xa26f02U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT; +#define FINN_MAXWELL_FAULT_BUFFER_A_RESERVED_INTERFACE_ID (0xb06900U) +typedef FINN_RM_API FINN_MAXWELL_FAULT_BUFFER_A_RESERVED; +#define FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID (0xb06901U) +typedef FINN_RM_API FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER; +#define FINN_MAXWELL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xb06f00U) +typedef FINN_RM_API FINN_MAXWELL_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xb06f01U) +typedef FINN_RM_API FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xb06f02U) +typedef FINN_RM_API FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT; +#define FINN_MAXWELL_PROFILER_RESERVED_INTERFACE_ID (0xb0cc00U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_RESERVED; +#define FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID (0xb0cc02U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_INTERNAL; +#define FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID (0xb0cc01U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_PROFILER; +#define FINN_MAXWELL_PROFILER_CONTEXT_RESERVED_INTERFACE_ID (0xb1cc00U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_CONTEXT_RESERVED; +#define FINN_MAXWELL_PROFILER_CONTEXT_PROFILER_INTERFACE_ID (0xb1cc01U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_CONTEXT_PROFILER; +#define FINN_MAXWELL_PROFILER_DEVICE_RESERVED_INTERFACE_ID (0xb2cc00U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_DEVICE_RESERVED; + +#define FINN_MAXWELL_SEC2_SEC2_INTERFACE_ID (0xb6b901U) +typedef FINN_RM_API FINN_MAXWELL_SEC2_SEC2; +#define FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc06f00U) +typedef FINN_RM_API FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc06f01U) +typedef FINN_RM_API FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc06f02U) +typedef FINN_RM_API FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT; +#define FINN_GP100_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0xc0e000U) +typedef FINN_RM_API FINN_GP100_SUBDEVICE_GRAPHICS_RESERVED; +#define FINN_GP100_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0xc0e001U) +typedef FINN_RM_API FINN_GP100_SUBDEVICE_GRAPHICS_GRAPHICS; +#define FINN_GP100_SUBDEVICE_FB_RESERVED_INTERFACE_ID (0xc0e100U) +typedef FINN_RM_API FINN_GP100_SUBDEVICE_FB_RESERVED; +#define FINN_GP100_SUBDEVICE_FB_FB_INTERFACE_ID (0xc0e101U) +typedef FINN_RM_API FINN_GP100_SUBDEVICE_FB_FB; +#define FINN_VOLTA_GSP_GSP_INTERFACE_ID (0xc31001U) +typedef FINN_RM_API FINN_VOLTA_GSP_GSP; +#define FINN_ACCESS_COUNTER_NOTIFY_BUFFER_RESERVED_INTERFACE_ID (0xc36500U) +typedef FINN_RM_API FINN_ACCESS_COUNTER_NOTIFY_BUFFER_RESERVED; +#define FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID (0xc36501U) +typedef FINN_RM_API FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER; +#define FINN_MMU_FAULT_BUFFER_RESERVED_INTERFACE_ID (0xc36900U) +typedef FINN_RM_API FINN_MMU_FAULT_BUFFER_RESERVED; +#define FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER_INTERFACE_ID (0xc36901U) +typedef FINN_RM_API FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER; +#define FINN_VOLTA_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc36f00U) +typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc36f01U) +typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc36f02U) +typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT; +#define FINN_NVC370_DISPLAY_RESERVED_INTERFACE_ID (0xc37000U) +typedef FINN_RM_API FINN_NVC370_DISPLAY_RESERVED; +#define FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID (0xc37001U) +typedef FINN_RM_API FINN_NVC370_DISPLAY_CHNCTL; +#define FINN_NVC370_DISPLAY_EVENT_INTERFACE_ID (0xc37009U) +typedef FINN_RM_API FINN_NVC370_DISPLAY_EVENT; +#define FINN_NVC370_DISPLAY_RG_INTERFACE_ID (0xc37002U) +typedef FINN_RM_API FINN_NVC370_DISPLAY_RG; +#define FINN_NVC370_DISPLAY_VERIF_INTERFACE_ID (0xc37006U) +typedef FINN_RM_API FINN_NVC370_DISPLAY_VERIF; +#define FINN_NVC372_DISPLAY_SW_RESERVED_INTERFACE_ID (0xc37200U) +typedef FINN_RM_API FINN_NVC372_DISPLAY_SW_RESERVED; +#define FINN_NVC372_DISPLAY_SW_CHNCTL_INTERFACE_ID (0xc37201U) +typedef FINN_RM_API FINN_NVC372_DISPLAY_SW_CHNCTL; + +#define FINN_GV100_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0xc3e000U) +typedef FINN_RM_API FINN_GV100_SUBDEVICE_GRAPHICS_RESERVED; +#define FINN_GV100_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0xc3e001U) +typedef FINN_RM_API FINN_GV100_SUBDEVICE_GRAPHICS_GRAPHICS; +#define FINN_GV100_SUBDEVICE_FB_RESERVED_INTERFACE_ID (0xc3e100U) +typedef FINN_RM_API FINN_GV100_SUBDEVICE_FB_RESERVED; +#define FINN_GV100_SUBDEVICE_FB_FB_INTERFACE_ID (0xc3e101U) +typedef FINN_RM_API FINN_GV100_SUBDEVICE_FB_FB; +#define FINN_TURING_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc46f00U) +typedef FINN_RM_API FINN_TURING_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_TURING_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc46f01U) +typedef FINN_RM_API FINN_TURING_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_TURING_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc46f02U) +typedef FINN_RM_API FINN_TURING_CHANNEL_GPFIFO_A_EVENT; +#define FINN_AMPERE_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc56f00U) +typedef FINN_RM_API FINN_AMPERE_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc56f01U) +typedef FINN_RM_API FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_AMPERE_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc56f02U) +typedef FINN_RM_API FINN_AMPERE_CHANNEL_GPFIFO_A_EVENT; +#define FINN_AMPERE_SMC_PARTITION_REF_RESERVED_INTERFACE_ID (0xc63700U) +typedef FINN_RM_API FINN_AMPERE_SMC_PARTITION_REF_RESERVED; +#define FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID (0xc63701U) +typedef FINN_RM_API FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS; +#define FINN_AMPERE_SMC_EXEC_PARTITION_REF_RESERVED_INTERFACE_ID (0xc63800U) +typedef FINN_RM_API FINN_AMPERE_SMC_EXEC_PARTITION_REF_RESERVED; +#define FINN_AMPERE_SMC_EXEC_PARTITION_REF_EXEC_PARTITION_INTERFACE_ID (0xc63801U) +typedef FINN_RM_API FINN_AMPERE_SMC_EXEC_PARTITION_REF_EXEC_PARTITION; +#define FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_RESERVED_INTERFACE_ID (0xc76300U) +typedef FINN_RM_API FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_RESERVED; +#define FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER_INTERFACE_ID (0xc76301U) +typedef FINN_RM_API FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER; +#define FINN_HOPPER_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc86f00U) +typedef FINN_RM_API FINN_HOPPER_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_HOPPER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc86f01U) +typedef FINN_RM_API FINN_HOPPER_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_HOPPER_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc86f02U) +typedef FINN_RM_API FINN_HOPPER_CHANNEL_GPFIFO_A_EVENT; + +#define FINN_NV_COUNTER_COLLECTION_UNIT_RESERVED_INTERFACE_ID (0xcbca00U) +typedef FINN_RM_API FINN_NV_COUNTER_COLLECTION_UNIT_RESERVED; +#define FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID (0xcbca01U) +typedef FINN_RM_API FINN_NV_COUNTER_COLLECTION_UNIT_CCU; +#define FINN_NVE2_SYNCPOINT_BASE_RESERVED_INTERFACE_ID (0xe2ad00U) +typedef FINN_RM_API FINN_NVE2_SYNCPOINT_BASE_RESERVED; +#define FINN_NVE2_SYNCPOINT_BASE_SYNCPOINT_BASE_INTERFACE_ID (0xe2ad01U) +typedef FINN_RM_API FINN_NVE2_SYNCPOINT_BASE_SYNCPOINT_BASE; diff --git a/userspace/sdks/nv525/nvidia/inc/mmu_fmt_types.h b/userspace/sdks/nv525/nvidia/inc/mmu_fmt_types.h new file mode 100644 index 0000000..ecbe2aa --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/mmu_fmt_types.h @@ -0,0 +1,151 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: mmu_fmt_types.finn +// + + + + +/*! + * @file mmu_fmt_types.h + * + * @brief Types used to describre MMU HW formats. + */ +#include "nvtypes.h" + +// Forward declarations. + + +/*! + * Generic MMU page directory/table level format description. + * + * Since the terminology of page directories and tables varies, + * the following describes the interpretation assumed here. + * + * Each level of virtual address translation is described by a range of + * virtual address bits. + * These bits index into a contiguous range of physical memory referred to + * generally as a "page level." + * Page level memory is interpreted as an array of entries, with each entry + * describing the next step of virtual to physical translation. + * + * Each entry in a given level may be interpreted as either a PDE or PTE. + * 1. A PDE (page directory entry) points to one or more "sub-levels" that + * continue the VA translation recursively. + * 2. A PTE (page table entry) is the base case, pointing to a physical page. + * + * The decision to treat an entry as a PDE or PTE may be static for a level. + * Levels that only contain PDEs are referred to as page directories. + * Levels that only contain PTEs are referred to as page tables. + * + * However, some formats have levels that may contain a mix of PDEs and PTEs, + * with the intpretation based on a "cutoff" bit in each entry (e.g. PTE valid bit). + * Such levels are referred to as "polymorphic page levels" since they can be + * viewed as both a page directory and a page table. + */ +typedef struct MMU_FMT_LEVEL { + /*! + * First virtual address bit that this page level covers. + */ + NvU8 virtAddrBitLo; + + /*! + * Last virtual address bit that this page level covers. + */ + NvU8 virtAddrBitHi; + + /*! + * Size in bytes of each entry within a level instance. + */ + NvU8 entrySize; + + /*! + * Indicates if this level can contain PTEs. + */ + NvBool bPageTable; + + /*! + * Number of sub-levels pointed to by PDEs in this level in + * range [0, MMU_FMT_MAX_SUB_LEVELS]. + * 0 indicates this level cannot contain PDEs. + */ + NvU8 numSubLevels; + + /*! + * Information tag used to decode internal level naming. + * Used for verif. + * */ + NvU32 pageLevelIdTag; + + + /*! + * Array of sub-level formats of length numSubLevels. + * + * @warning This array results in a circular reference to MMU_FMT_LEVEL. + * This can present an issue for FINN serialization and may have to + * be refactored before MMU_FMT_LEVEL can be serialized. + */ + NV_DECLARE_ALIGNED(struct MMU_FMT_LEVEL *subLevels, 8); +} MMU_FMT_LEVEL; + +/*! + * Maximum number of pointers to sub-levels within a page directory entry. + * + * Standard page directory entries (PDEs) point to a single sub-level, + * either the next page directory level in the topology or a leaf page table. + * + * However, some formats contain PDEs that point to more than one sub-level. + * These sub-levels are translated by HW in parallel to support multiple + * page sizes at a higher granularity (e.g. for migration between + * 4K system memory pages and big video memory pages for GPU MMU). + * + * The current supported formats have a maximum of 2 parallel sub-levels, + * often referred to as "dual PDE" or "dual page table" support. + * + * Example for Fermi GPU HW: + * Sub-level 0 corresponds to big page table pointer. + * Sub-level 1 corresponds to small page table pointer. + * + * This number is very unlikely to change, but it is defined to + * simplify SW handling, encouraging loops over "dual copy-paste." + */ +#define MMU_FMT_MAX_SUB_LEVELS 2 + +/*! + * Valid values for the pageLevelIdTag field. + * These values are used to identify the internal naming of the page level. + * Used for verif purposes. + */ +#define MMU_FMT_PT_SURF_ID_PD0 0 +#define MMU_FMT_PT_SURF_ID_PD1 1 +#define MMU_FMT_PT_SURF_ID_PD2 2 +#define MMU_FMT_PT_SURF_ID_PD3 3 +#define MMU_FMT_PT_SURF_ID_PD4 4 +#define MMU_FMT_PT_SURF_ID_PT_4K 5 +#define MMU_FMT_PT_SURF_ID_PT_BIG 6 diff --git a/userspace/sdks/nv525/nvidia/inc/nv-hypervisor.h b/userspace/sdks/nv525/nvidia/inc/nv-hypervisor.h new file mode 100644 index 0000000..6ee37f7 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/nv-hypervisor.h @@ -0,0 +1,123 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NV_HYPERVISOR_H_ +#define _NV_HYPERVISOR_H_ + +#include + +// Enums for supported hypervisor types. +// New hypervisor type should be added before OS_HYPERVISOR_UNKNOWN +typedef enum _HYPERVISOR_TYPE +{ + OS_HYPERVISOR_XEN = 0, + OS_HYPERVISOR_VMWARE, + OS_HYPERVISOR_HYPERV, + OS_HYPERVISOR_KVM, + OS_HYPERVISOR_UNKNOWN +} HYPERVISOR_TYPE; + +#define CMD_VGPU_VFIO_WAKE_WAIT_QUEUE 0 +#define CMD_VGPU_VFIO_INJECT_INTERRUPT 1 +#define CMD_VGPU_VFIO_REGISTER_MDEV 2 +#define CMD_VGPU_VFIO_PRESENT 3 + +#define MAX_VF_COUNT_PER_GPU 64 + +typedef enum _VGPU_TYPE_INFO +{ + VGPU_TYPE_NAME = 0, + VGPU_TYPE_DESCRIPTION, + VGPU_TYPE_INSTANCES, +} VGPU_TYPE_INFO; + +typedef struct +{ + void *vgpuVfioRef; + void *waitQueue; + void *nv; + NvU32 *vgpuTypeIds; + NvU32 numVgpuTypes; + NvU32 domain; + NvU8 bus; + NvU8 slot; + NvU8 function; + NvBool is_virtfn; +} vgpu_vfio_info; + +typedef struct +{ + NvU32 domain; + NvU8 bus; + NvU8 slot; + NvU8 function; + NvBool isNvidiaAttached; + NvBool isMdevAttached; +} vgpu_vf_pci_info; + +typedef enum VGPU_CMD_PROCESS_VF_INFO_E +{ + NV_VGPU_SAVE_VF_INFO = 0, + NV_VGPU_REMOVE_VF_PCI_INFO = 1, + NV_VGPU_REMOVE_VF_MDEV_INFO = 2, + NV_VGPU_GET_VF_INFO = 3 +} VGPU_CMD_PROCESS_VF_INFO; + +typedef enum VGPU_DEVICE_STATE_E +{ + NV_VGPU_DEV_UNUSED = 0, + NV_VGPU_DEV_OPENED = 1, + NV_VGPU_DEV_IN_USE = 2 +} VGPU_DEVICE_STATE; + +typedef enum _VMBUS_CMD_TYPE +{ + VMBUS_CMD_TYPE_INVALID = 0, + VMBUS_CMD_TYPE_SETUP = 1, + VMBUS_CMD_TYPE_SENDPACKET = 2, + VMBUS_CMD_TYPE_CLEANUP = 3, +} VMBUS_CMD_TYPE; + +typedef struct +{ + NvU32 request_id; + NvU32 page_count; + NvU64 *pPfns; + void *buffer; + NvU32 bufferlen; +} vmbus_send_packet_cmd_params; + + +typedef struct +{ + NvU32 override_sint; + NvU8 *nv_guid; +} vmbus_setup_cmd_params; + +/* + * Function prototypes + */ + +HYPERVISOR_TYPE NV_API_CALL nv_get_hypervisor_type(void); + +#endif // _NV_HYPERVISOR_H_ diff --git a/userspace/sdks/nv525/nvidia/inc/nv-kernel-interface-api.h b/userspace/sdks/nv525/nvidia/inc/nv-kernel-interface-api.h new file mode 100644 index 0000000..183f9b4 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/nv-kernel-interface-api.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NV_KERNEL_INTERFACE_API_H +#define _NV_KERNEL_INTERFACE_API_H +/************************************************************************************************************** +* +* File: nv-kernel-interface-api.h +* +* Description: +* Defines the NV API related macros. +* +**************************************************************************************************************/ + +#if NVOS_IS_UNIX && NVCPU_IS_X86_64 && defined(__use_altstack__) +#define NV_API_CALL __attribute__((altstack(0))) +#else +#define NV_API_CALL +#endif + +#endif /* _NV_KERNEL_INTERFACE_API_H */ diff --git a/userspace/sdks/nv525/nvidia/inc/nv_stdarg.h b/userspace/sdks/nv525/nvidia/inc/nv_stdarg.h new file mode 100644 index 0000000..b23f7f7 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/nv_stdarg.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _NV_STDARG_H_ +#define _NV_STDARG_H_ + +#if defined(NV_KERNEL_INTERFACE_LAYER) && defined(NV_LINUX) + #include "conftest.h" + #if defined(NV_LINUX_STDARG_H_PRESENT) + #include + #else + #include + #endif +#else + #include +#endif + +#endif // _NV_STDARG_H_ diff --git a/userspace/sdks/nv525/nvidia/inc/nv_vgpu_types.h b/userspace/sdks/nv525/nvidia/inc/nv_vgpu_types.h new file mode 100644 index 0000000..fae9985 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/nv_vgpu_types.h @@ -0,0 +1,61 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: nv_vgpu_types.finn +// + + + + +/* XAPIGEN - this file is not suitable for (nor needed by) xapigen. */ +/* Rather than #ifdef out every such include in every sdk */ +/* file, punt here. */ +#include "nvtypes.h" + /* ! XAPIGEN */ + +#define VM_UUID_SIZE 16 +#define INVALID_VGPU_DEV_INST 0xFFFFFFFFU +#define MAX_VGPU_DEVICES_PER_VM 16U + +/* This enum represents the current state of guest dependent fields */ +typedef enum GUEST_VM_INFO_STATE { + GUEST_VM_INFO_STATE_UNINITIALIZED = 0, + GUEST_VM_INFO_STATE_INITIALIZED = 1, +} GUEST_VM_INFO_STATE; + +/* This enum represents types of VM identifiers */ +typedef enum VM_ID_TYPE { + VM_ID_DOMAIN_ID = 0, + VM_ID_UUID = 1, +} VM_ID_TYPE; + +/* This structure represents VM identifier */ +typedef union VM_ID { + NvU8 vmUuid[VM_UUID_SIZE]; + NV_DECLARE_ALIGNED(NvU64 vmId, 8); +} VM_ID; diff --git a/userspace/sdks/nv525/nvidia/inc/nvcd.h b/userspace/sdks/nv525/nvidia/inc/nvcd.h new file mode 100644 index 0000000..6c462eb --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/nvcd.h @@ -0,0 +1,159 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2002-2002 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVCD_H +#define NVCD_H + +//****************************************************************************** +// +// Module Name: NVCD.H +// +// This file contains structures and constants that define the NV specific +// data to be returned by the miniport's new VideoBugCheckCallback. The callback +// can return up to 4k bytes of data that will be appended to the dump file. +// The bugcheck callback is currently only invoked for bugcheck 0xEA failures. +// The buffer returned contains a top level header, followed by a variable +// number of data records. The top level header contains an ASCII signature +// that can be located with a search as well as a GUID for unique identification +// of the crash dump layout, i.e. future bugcheck callbacks can define a new +// GUID to redefine the entire crash dump layout. A checksum and crash dump +// size values are also included to insure crash dump data integrity. The +// data records each contain a header indicating what group the data belongs to +// as well as the actual record type and size. This flexibility allows groups +// to define and extend the information in their records without adversely +// affecting the code in the debugger extension that has to parse and display +// this information. The structures for these individual data records are +// contained in separate header files for each group. +// +//****************************************************************************** +#include "nvtypes.h" + +// Define the GUID type for non-Windows OSes + +#ifndef GUID_DEFINED +#define GUID_DEFINED +typedef struct _GUID { + NvU32 Data1; + NvU16 Data2; + NvU16 Data3; + NvU8 Data4[8]; +} GUID, *LPGUID; +#endif + +// Define the crash dump ASCII tag value and the dump format GUIDs +#define NVCD_SIGNATURE 0x4443564E /* ASCII crash dump signature "NVCD" */ + +#define GUID_NVCD_DUMP_V1 { /* e3d5dc6e-db7d-4e28-b09e-f59a942f4a24 */ \ + 0xe3d5dc6e, 0xdb7d, 0x4e28, \ + {0xb0, 0x9e, 0xf5, 0x9a, 0x94, 0x2f, 0x4a, 0x24}\ +}; +#define GUID_NVCD_DUMP_V2 { /* cd978ac1-3aa1-494b-bb5b-e93daf2b0536 */ \ + 0xcd978ac1, 0x3aa1, 0x494b, \ + {0xbb, 0x5b, 0xe9, 0x3d, 0xaf, 0x2b, 0x05, 0x36}\ +}; +#define GUID_NVCDMP_RSVD1 { /* 391fc656-a37c-4574-8d57-b29a562f909b */ \ + 0x391fc656, 0xa37c, 0x4574, \ + {0x8d, 0x57, 0xb2, 0x9a, 0x56, 0x2f, 0x90, 0x9b}\ +}; +#define GUID_NVCDMP_RSVD2 { /* c6d9982d-1ba9-4f80-badd-3dc992d41b46 */ \ + 0xc6d9982d, 0x1ba9, 0x4f80, \ + {0xba, 0xdd, 0x3d, 0xc9, 0x92, 0xd4, 0x1b, 0x46}\ +}; + +// RC 2.0 NVCD (NV crash dump) GUID +#define GUID_NVCD_RC2_V1 { /* d3793533-a4a6-46d3-97f2-1446cfdc1ee7 */ \ + 0xd3793533, 0xa4a6, 0x46d3, \ + {0x97, 0xf2, 0x14, 0x46, 0xcf, 0xdc, 0x1e, 0xe7}\ +}; + + +// Define NVIDIA crash dump header structure (First data block in crash dump) +typedef struct +{ + NvU32 dwSignature; // ASCII crash dump signature "NVCD" + GUID gVersion; // GUID for crashdump file (Version) + NvU32 dwSize; // Size of the crash dump data + NvU8 cCheckSum; // Crash dump checksum (Zero = ignore) + NvU8 cFiller[3]; // Filler (Possible CRC value) +} NVCD_HEADER; +typedef NVCD_HEADER *PNVCD_HEADER; + +// Define the crash dump record groups +typedef enum +{ + NvcdGroup = 0, // NVIDIA crash dump group (System NVCD records) + RmGroup = 1, // Resource manager group (RM records) + DriverGroup = 2, // Driver group (Driver/miniport records) + HardwareGroup = 3, // Hardware group (Hardware records) + InstrumentationGroup = 4, // Instrumentation group (Special records) +} NVCD_GROUP_TYPE; + +// Define the crash dump group record types (Single end of data record type) +typedef enum +{ + EndOfData = 0, // End of crash dump data record + CompressedDataHuffman = 1, // Compressed huffman data +} NVCD_RECORD_TYPE; + +// Define the crash dump data record header +typedef struct +{ + NvU8 cRecordGroup; // Data record group (NVCD_GROUP_TYPE) + NvU8 cRecordType; // Data record type (See group header) + NvU16 wRecordSize; // Size of the data record in bytes +} NVCD_RECORD; +typedef NVCD_RECORD *PNVCD_RECORD; + +// Define the EndOfData record structure +typedef struct +{ + NVCD_RECORD Header; // End of data record header +} EndOfData_RECORD; +typedef EndOfData_RECORD *PEndOfData_RECORD; + +// +// Generic mini-record type (keep the size at 64bits) +// +typedef struct +{ + NVCD_RECORD Header; // header for mini record + NvU32 Payload; // 32 bit payload value +} NVCDMiniRecord; +typedef NVCDMiniRecord *PNVCDMiniRecord; + +// +// Generic record collection type +// +typedef struct +{ + NVCD_RECORD Header; // generic header to binary type this in OCA buffer + // size is actual size of this struct + all items in collection + NvU32 NumRecords; // number of records this collection contain + NVCD_RECORD FirstRecord; // first record, its data follow +} NVCDRecordCollection; +typedef NVCDRecordCollection *PNVCDRecordCollection; + +#define COLL_HEADER_SIZEOF (sizeof(NVCDRecordCollection) - sizeof(NVCD_RECORD)) + + +#endif // NVCD_H diff --git a/userspace/sdks/nv525/nvidia/inc/nvcfg_sdk.h b/userspace/sdks/nv525/nvidia/inc/nvcfg_sdk.h new file mode 100644 index 0000000..4ce8d4b --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/nvcfg_sdk.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef NV_CFG_SDK_INCLUDED +#define NV_CFG_SDK_INCLUDED + + +#endif // NV_CFG_SDK_INCLUDED diff --git a/userspace/sdks/nv525/nvidia/inc/nvdeprecated.h b/userspace/sdks/nv525/nvidia/inc/nvdeprecated.h new file mode 100644 index 0000000..75d99cc --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/nvdeprecated.h @@ -0,0 +1,133 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NV_DEPRECATED_H +#define NV_DEPRECATED_H + +/*! + * @file nvdeprecated.h + * + * @brief Deprecation in the NVIDIA SDK + * + * Why deprecate: + * Code is deprecated when you want to remove a feature entirely, but cannot + * do so immediately, nor in a single step, due to a requirement to remain + * backward compatible (keep older clients working). + * + * Backwards compatibility: + * Deprecated symbols and features may be supported for an unknown amount of + * time. "Deprecated" means that we want that time interval to be small, but + * that may not be under our control. + * + * This file provides the following ways to support deprecated features: + * + * 1) Defining NV_STRICT_SDK before including a SDK headers. This will + * remove *all* deprecated APIs from the NV SDK, for example: + * + * #define NV_STRICT_SDK + * #include "sdk/foo.h" + * + * 2) Defining the per-feature compatibility setting before including the + * SDK, for example: + * + * #define NV_DEPRECATED_NVOS_STATUS 0 // enable compatibility mode + * #include "sdk/foo.h" + * + * How to deprecate a feature in the SDK: + * + * 1) Define the deprecated feature in this file. Often, you'll want to + * start with SDK compatibility enabled by default, for example: + * + * #ifndef NV_DEPRECATED_FEATURE_NAME + * #define NV_DEPRECATED_FEATURE_NAME 0 + * #endif + * + * 2) Wrap SDK definitions with compatibility #ifdefs: + * + * #if NV_DEPRECATED_COMPAT(FEATURE_NAME) + * ...legacy definitions... + * #endif + * + * 3) In the API implementation, consider stubbing or wrapping the new API. + * + * 4) Update older clients: file bugs to track this effort. Bug numbers + * should be placed in comments near the deprecated features that RM is + * supporting. That way, people reading the code can easily find the + * bug(s) that show the status of completely removing the deprecated + * feature. + * + * 5) Once all the client (calling) code has been upgraded, change the + * macro to "compatibility off". This is a little more cautious and + * conservative than jumping directly to step (6), because it allows you + * to recover from a test failure (remember, there are extended, offline + * tests that are not, unfortunately, run in DVS, nor per-CL checkin) + * with a tiny change in code. + * + * 6) Once the code base has migrated, remove all definitions from the SDK. + */ + +/* + * \defgroup Deprecated SDK Features + * + * 0 = Compatibility on by default (i.e.: defines present in SDK) + * 1 = Compatibility off by default (i.e.: defines NOT in SDK) + * + * @{ + */ + +/*! + * RM Config Get/Set API is deprecated and RmControl should be used instead. + * Bugs: XXXXXX, XXXXXX, etc + */ +#ifndef NV_DEPRECATED_RM_CONFIG_GET_SET +#define NV_DEPRECATED_RM_CONFIG_GET_SET 0 +#endif + +#ifndef NV_DEPRECATED_NVOS_STATUS +/* NVOS_STATUS codes is deprecated. NV_STATUS to be used instead */ +#define NV_DEPRECATED_NVOS_STATUS 0 +#endif + +#ifndef NV_DEPRECATED_RM_STATUS +/* RM_STATUS codes is deprecated. NV_STATUS to be used instead */ +#define NV_DEPRECATED_RM_STATUS 0 +#endif + +#ifndef NV_DEPRECATED_UNSAFE_HANDLES +/* Using NvU32 for handles is deprecated. NvHandle to be used instead */ +#define NV_DEPRECATED_UNSAFE_HANDLES 0 +#endif + +/**@}*/ + +/*! + * Utility Macros + */ + +#ifdef NV_STRICT_SDK +// In strict mode, all obsolete features are unavailable in the SDK. +#define NV_DEPRECATED_COMPAT(feature) 0 +#else +#define NV_DEPRECATED_COMPAT(feature) (!NV_DEPRECATED_##feature) +#endif + +#endif diff --git a/userspace/sdks/nv525/nvidia/inc/nvdisptypes.h b/userspace/sdks/nv525/nvidia/inc/nvdisptypes.h new file mode 100644 index 0000000..90d8ac0 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/nvdisptypes.h @@ -0,0 +1,92 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + /***************************************************************************\ +|* *| +|* NV Display Common Types *| +|* *| +|* defines the common display types. *| +|* *| + \***************************************************************************/ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: nvdisptypes.finn +// + + + + +#include "nvtypes.h" + + + +typedef enum NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP { + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_DEFAULT = 0, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 = 1, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 = 2, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 = 3, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 = 4, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 = 5, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 = 6, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 = 7, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 = 8, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 = 9, +} NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP; + + + +typedef NvU32 NV_DISP_LOCK_PIN; + +#define NV_DISP_LOCK_PIN_0 0x0 +#define NV_DISP_LOCK_PIN_1 0x1 +#define NV_DISP_LOCK_PIN_2 0x2 +#define NV_DISP_LOCK_PIN_3 0x3 +#define NV_DISP_LOCK_PIN_4 0x4 +#define NV_DISP_LOCK_PIN_5 0x5 +#define NV_DISP_LOCK_PIN_6 0x6 +#define NV_DISP_LOCK_PIN_7 0x7 +#define NV_DISP_LOCK_PIN_8 0x8 +#define NV_DISP_LOCK_PIN_9 0x9 +#define NV_DISP_LOCK_PIN_A 0xA +#define NV_DISP_LOCK_PIN_B 0xB +#define NV_DISP_LOCK_PIN_C 0xC +#define NV_DISP_LOCK_PIN_D 0xD +#define NV_DISP_LOCK_PIN_E 0xE +#define NV_DISP_LOCK_PIN_F 0xF + +// Value used solely for HW initialization +#define NV_DISP_LOCK_PIN_UNSPECIFIED 0x10 + + + +typedef NvU32 NV_DISP_LOCK_MODE; + +#define NV_DISP_LOCK_MODE_NO_LOCK 0x0 +#define NV_DISP_LOCK_MODE_FRAME_LOCK 0x1 +#define NV_DISP_LOCK_MODE_RASTER_LOCK 0x3 + diff --git a/userspace/sdks/nv525/nvidia/inc/nvdump.h b/userspace/sdks/nv525/nvidia/inc/nvdump.h new file mode 100644 index 0000000..32c6c76 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/nvdump.h @@ -0,0 +1,163 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +//////////////////////////////////////////////////////////////////////////////// +// +// Module: nvDump.h +// Shared definitions for HW/SW dumping facility residing in resman/rc. +// +// ************************************************************************** + +#ifndef _NVDUMP_H_ +#define _NVDUMP_H_ + +#include "nvtypes.h" + +//------------------------------------------------------------------------- +// DEFINTIONS +//------------------------------------------------------------------------- + +#define NVDUMP_SUB_ALLOC_NOT_ENCODED 0x01 +#define NVDUMP_SUB_ALLOC_VALID 0x02 +#define NVDUMP_SUB_ALLOC_HAS_MORE 0x04 + +#define NVDUMP_DEBUG_BUFFER_MAX_SIZE 4096 // max of 4K per buffer +#define NVDUMP_DEBUG_BUFFER_MAX_SUBALLOCATIONS 256 + +#define NVDUMP_CONFIG_SIGNATURE "NVDUMPCONFIGSIG" // multiple of 8 bytes + +typedef enum +{ + // The following components are GPU instance specific: + NVDUMP_COMPONENT_DEBUG_BUFFERS = 0, + NVDUMP_COMPONENT_ENG_MC, + NVDUMP_COMPONENT_ENG_FIFO, + NVDUMP_COMPONENT_ENG_GRAPHICS, + NVDUMP_COMPONENT_ENG_FB, + NVDUMP_COMPONENT_ENG_DISP, + NVDUMP_COMPONENT_ENG_FAN, + NVDUMP_COMPONENT_ENG_THERMAL, + NVDUMP_COMPONENT_ENG_FUSE, + NVDUMP_COMPONENT_ENG_VBIOS, + NVDUMP_COMPONENT_ENG_PERF, + NVDUMP_COMPONENT_ENG_BUS, + NVDUMP_COMPONENT_ENG_PMU, + NVDUMP_COMPONENT_ENG_ALL, + NVDUMP_COMPONENT_ENG_CE, + NVDUMP_COMPONENT_ENG_GPU, + NVDUMP_COMPONENT_ENG_LPWR, + NVDUMP_COMPONENT_ENG_NVD, + NVDUMP_COMPONENT_ENG_VOLT, + NVDUMP_COMPONENT_ENG_CLK, + NVDUMP_COMPONENT_ENG_SEC2, + NVDUMP_COMPONENT_ENG_NVLINK, + NVDUMP_COMPONENT_ENG_BSP, + NVDUMP_COMPONENT_ENG_DPU, + NVDUMP_COMPONENT_ENG_FBFLCN, + NVDUMP_COMPONENT_ENG_HDA, + NVDUMP_COMPONENT_ENG_MSENC, + NVDUMP_COMPONENT_ENG_GSP, + NVDUMP_COMPONENT_ENG_INFOROM, + NVDUMP_COMPONENT_ENG_GCX, + // The following components are global to the system: + NVDUMP_COMPONENT_SYS_RCDB = 0x400, + NVDUMP_COMPONENT_SYS_SYSINFO, + NVDUMP_COMPONENT_SYS_ALL, + // The following components are nvlog related. + NVDUMP_COMPONENT_NVLOG_RM = 0x800, + NVDUMP_COMPONENT_NVLOG_ALL, + // Reserved + NVDUMP_COMPONENT_NVLOG_RESERVED = 0xB00, +} NVDUMP_COMPONENT; + +#define NVDUMP_IS_GPU_COMPONENT(c) ((c) < NVDUMP_COMPONENT_SYS_RCDB) +#define NVDUMP_IS_SYS_COMPONENT(c) (((c) >= NVDUMP_COMPONENT_SYS_RCDB) && \ + ((c) < NVDUMP_COMPONENT_NVLOG_RM)) +#define NVDUMP_IS_NVLOG_COMPONENT(c) (((c) >= NVDUMP_COMPONENT_NVLOG_RM) && \ + ((c) < NVDUMP_COMPONENT_NVLOG_RESERVED)) + +typedef enum +{ + NVDUMP_BUFFER_PROVIDED = 0, // Dump buffer provided by caller + NVDUMP_BUFFER_ALLOCATE, // Dump buffer to be allocated + NVDUMP_BUFFER_COUNT, // Just count, no buffer needed +} NVDUMP_BUFFER_POLICY; + +typedef enum +{ + NVDUMP_STATUS_IDLE, + NVDUMP_STATUS_ERROR, + NVDUMP_STATUS_COUNT_REQUESTED, + NVDUMP_STATUS_COUNT_COMPLETE, + NVDUMP_STATUS_DUMP_REQUESTED, + NVDUMP_STATUS_DUMP_BUFFER_FULL, + NVDUMP_STATUS_DUMP_END_OF_MSG, + NVDUMP_STATUS_DUMP_COMPLETE, +} NVDUMP_STATUS; + +// +// The following structures require that all elements are precisely sized +// and aligned on natural boundaries. +// + +typedef struct +{ + NvP64 address NV_ALIGN_BYTES(8); + NvU32 size; + NvU32 curNumBytes; +} NVDUMP_BUFFER; + +// Max number of bytes that can be returned in a dump buffer +#define NVDUMP_MAX_DUMP_SIZE (1 << 20) // 1 MB + +typedef struct +{ + NvU8 sigHead[sizeof(NVDUMP_CONFIG_SIGNATURE)] NV_ALIGN_BYTES(8); + + NvP64 debuggerControlFuncAddr NV_ALIGN_BYTES(8); + NVDUMP_BUFFER buffer; + NvU32 gpuSelect; + NvU32 component; + NvU32 dumpStatus; + NvU32 rmStatus; + + NvU8 sigTail[sizeof(NVDUMP_CONFIG_SIGNATURE)] NV_ALIGN_BYTES(8); +} NVDUMP_CONFIG; + +typedef struct +{ + NvU16 length; + NvU16 start; + NvU16 end; + NvU16 flags; + NvU16 tag; +} NVDUMP_SUB_ALLOC_HEADER; + +// +// Export is needed to allow remote kernel debuggers without symbols +// to find global NVDUMP_CONFIG variables in driver export address table. +// +#define NVDUMP_EXPORT + +#endif // _NVDUMP_H_ + diff --git a/userspace/sdks/nv525/nvidia/inc/nverror.h b/userspace/sdks/nv525/nvidia/inc/nverror.h new file mode 100644 index 0000000..a7fef7d --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/nverror.h @@ -0,0 +1,224 @@ +/* + * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVERROR_H +#define NVERROR_H +/****************************************************************************** +* +* File: nverror.h +* +* Description: +* This file contains the error codes set when the error notifier +* is signaled. +* +******************************************************************************/ + +#include "nvcfg_sdk.h" + +#define ROBUST_CHANNEL_GR_EXCEPTION (13) +#define ROBUST_CHANNEL_GR_ERROR_SW_NOTIFY (13) +#define ROBUST_CHANNEL_FAKE_ERROR (14) +#define ROBUST_CHANNEL_VBLANK_CALLBACK_TIMEOUT (16) +#define ROBUST_CHANNEL_DISP_MISSED_NOTIFIER (19) +#define ROBUST_CHANNEL_MPEG_ERROR_SW_METHOD (20) +#define ROBUST_CHANNEL_ME_ERROR_SW_METHOD (21) +#define ROBUST_CHANNEL_VP_ERROR_SW_METHOD (22) +#define ROBUST_CHANNEL_RC_LOGGING_ENABLED (23) +#define ROBUST_CHANNEL_VP_ERROR (27) +#define ROBUST_CHANNEL_VP2_ERROR (28) +#define ROBUST_CHANNEL_BSP_ERROR (29) +#define ROBUST_CHANNEL_BAD_ADDR_ACCESS (30) +#define ROBUST_CHANNEL_FIFO_ERROR_MMU_ERR_FLT (31) +#define ROBUST_CHANNEL_PBDMA_ERROR (32) +#define ROBUST_CHANNEL_SEC_ERROR (33) +#define ROBUST_CHANNEL_MSVLD_ERROR (34) +#define ROBUST_CHANNEL_MSPDEC_ERROR (35) +#define ROBUST_CHANNEL_MSPPP_ERROR (36) +#define ROBUST_CHANNEL_CE0_ERROR (39) +#define ROBUST_CHANNEL_CE1_ERROR (40) +#define ROBUST_CHANNEL_CE2_ERROR (41) +#define ROBUST_CHANNEL_VIC_ERROR (42) +#define ROBUST_CHANNEL_RESETCHANNEL_VERIF_ERROR (43) +#define ROBUST_CHANNEL_GR_FAULT_DURING_CTXSW (44) +#define ROBUST_CHANNEL_PREEMPTIVE_REMOVAL (45) +#define ROBUST_CHANNEL_NVENC0_ERROR (47) +#define ROBUST_CHANNEL_GPU_ECC_DBE (48) +#define PMU_ERROR (59) +#define ROBUST_CHANNEL_SEC2_ERROR (60) +#define PMU_BREAKPOINT (61) +#define PMU_HALT_ERROR (62) +#define INFOROM_PAGE_RETIREMENT_EVENT (63) +#define INFOROM_PAGE_RETIREMENT_FAILURE (64) +#define INFOROM_DRAM_RETIREMENT_EVENT (63) +#define INFOROM_DRAM_RETIREMENT_FAILURE (64) +#define ROBUST_CHANNEL_NVENC1_ERROR (65) +#define ROBUST_CHANNEL_NVDEC0_ERROR (68) +#define ROBUST_CHANNEL_GR_CLASS_ERROR (69) +#define ROBUST_CHANNEL_CE3_ERROR (70) +#define ROBUST_CHANNEL_CE4_ERROR (71) +#define ROBUST_CHANNEL_CE5_ERROR (72) +#define ROBUST_CHANNEL_NVENC2_ERROR (73) +#define NVLINK_ERROR (74) +#define ROBUST_CHANNEL_CE6_ERROR (75) +#define ROBUST_CHANNEL_CE7_ERROR (76) +#define ROBUST_CHANNEL_CE8_ERROR (77) +#define VGPU_START_ERROR (78) +#define ROBUST_CHANNEL_GPU_HAS_FALLEN_OFF_THE_BUS (79) +#define PBDMA_PUSHBUFFER_CRC_MISMATCH (80) +#define ROBUST_CHANNEL_VGA_SUBSYSTEM_ERROR (81) +#define ROBUST_CHANNEL_NVJPG0_ERROR (82) +#define ROBUST_CHANNEL_NVDEC1_ERROR (83) +#define ROBUST_CHANNEL_NVDEC2_ERROR (84) +#define ROBUST_CHANNEL_CE9_ERROR (85) +#define ROBUST_CHANNEL_OFA0_ERROR (86) +#define NVTELEMETRY_DRIVER_REPORT (87) +#define ROBUST_CHANNEL_NVDEC3_ERROR (88) +#define ROBUST_CHANNEL_NVDEC4_ERROR (89) +#define LTC_ERROR (90) +#define RESERVED_XID (91) +#define EXCESSIVE_SBE_INTERRUPTS (92) +#define INFOROM_ERASE_LIMIT_EXCEEDED (93) +#define ROBUST_CHANNEL_CONTAINED_ERROR (94) +#define ROBUST_CHANNEL_UNCONTAINED_ERROR (95) +#define ROBUST_CHANNEL_NVDEC5_ERROR (96) +#define ROBUST_CHANNEL_NVDEC6_ERROR (97) +#define ROBUST_CHANNEL_NVDEC7_ERROR (98) +#define ROBUST_CHANNEL_NVJPG1_ERROR (99) +#define ROBUST_CHANNEL_NVJPG2_ERROR (100) +#define ROBUST_CHANNEL_NVJPG3_ERROR (101) +#define ROBUST_CHANNEL_NVJPG4_ERROR (102) +#define ROBUST_CHANNEL_NVJPG5_ERROR (103) +#define ROBUST_CHANNEL_NVJPG6_ERROR (104) +#define ROBUST_CHANNEL_NVJPG7_ERROR (105) +#define SEC_FAULT_ERROR (110) +#define GSP_RPC_TIMEOUT (119) +#define GSP_ERROR (120) +#define C2C_ERROR (121) +#define SPI_PMU_RPC_READ_FAIL (122) +#define SPI_PMU_RPC_WRITE_FAIL (123) +#define SPI_PMU_RPC_ERASE_FAIL (124) +#define INFOROM_FS_ERROR (125) +#define ALI_TRAINING_FAIL (136) +#define ROBUST_CHANNEL_LAST_ERROR (ALI_TRAINING_FAIL) + + + +// Indexed CE reference +#define ROBUST_CHANNEL_CE_ERROR(x) \ + ((x < 3) ? \ + (ROBUST_CHANNEL_CE0_ERROR + (x)) : \ + ((x < 6) ? \ + (ROBUST_CHANNEL_CE3_ERROR + (x - 3)) : \ + ((x < 9) ? \ + (ROBUST_CHANNEL_CE6_ERROR + (x - 6)) : \ + (ROBUST_CHANNEL_CE9_ERROR)))) + +#define ROBUST_CHANNEL_IS_CE_ERROR(x) \ + ((x == ROBUST_CHANNEL_CE0_ERROR) || (x == ROBUST_CHANNEL_CE1_ERROR) || \ + (x == ROBUST_CHANNEL_CE2_ERROR) || (x == ROBUST_CHANNEL_CE3_ERROR) || \ + (x == ROBUST_CHANNEL_CE4_ERROR) || (x == ROBUST_CHANNEL_CE5_ERROR) || \ + (x == ROBUST_CHANNEL_CE6_ERROR) || (x == ROBUST_CHANNEL_CE7_ERROR) || \ + (x == ROBUST_CHANNEL_CE8_ERROR) || (x == ROBUST_CHANNEL_CE9_ERROR)) + +#define ROBUST_CHANNEL_CE_ERROR_IDX(x) \ + (((x >= ROBUST_CHANNEL_CE0_ERROR) && (x <= ROBUST_CHANNEL_CE2_ERROR)) ? \ + (x - ROBUST_CHANNEL_CE0_ERROR) : \ + (((x >= ROBUST_CHANNEL_CE3_ERROR) && (x <= ROBUST_CHANNEL_CE5_ERROR)) ? \ + (x - ROBUST_CHANNEL_CE3_ERROR + 3) : \ + (((x >= ROBUST_CHANNEL_CE6_ERROR) && (x <= ROBUST_CHANNEL_CE8_ERROR)) ? \ + (x - ROBUST_CHANNEL_CE6_ERROR + 6) : \ + (x - ROBUST_CHANNEL_CE9_ERROR + 9)))) + +// Indexed NVDEC reference +#define ROBUST_CHANNEL_NVDEC_ERROR(x) \ + ((x < 1) ? \ + (ROBUST_CHANNEL_NVDEC0_ERROR) : \ + ((x < 3) ? \ + (ROBUST_CHANNEL_NVDEC1_ERROR + (x - 1)) : \ + ((x < 5) ? \ + (ROBUST_CHANNEL_NVDEC3_ERROR + (x - 3)): \ + (ROBUST_CHANNEL_NVDEC5_ERROR + (x - 5))))) + +#define ROBUST_CHANNEL_IS_NVDEC_ERROR(x) \ + ((x == ROBUST_CHANNEL_NVDEC0_ERROR) || \ + (x == ROBUST_CHANNEL_NVDEC1_ERROR) || \ + (x == ROBUST_CHANNEL_NVDEC2_ERROR) || \ + (x == ROBUST_CHANNEL_NVDEC3_ERROR) || \ + (x == ROBUST_CHANNEL_NVDEC4_ERROR) || \ + (x == ROBUST_CHANNEL_NVDEC5_ERROR) || \ + (x == ROBUST_CHANNEL_NVDEC6_ERROR) || \ + (x == ROBUST_CHANNEL_NVDEC7_ERROR)) + +#define ROBUST_CHANNEL_NVDEC_ERROR_IDX(x) \ + ((x == ROBUST_CHANNEL_NVDEC0_ERROR) ? \ + (x - ROBUST_CHANNEL_NVDEC0_ERROR) : \ + (((x >= ROBUST_CHANNEL_NVDEC1_ERROR) && (x <= ROBUST_CHANNEL_NVDEC2_ERROR)) ? \ + (x - ROBUST_CHANNEL_NVDEC1_ERROR + 1) : \ + (((x >= ROBUST_CHANNEL_NVDEC3_ERROR) && (x <= ROBUST_CHANNEL_NVDEC4_ERROR)) ? \ + (x - ROBUST_CHANNEL_NVDEC3_ERROR + 3) : \ + (x - ROBUST_CHANNEL_NVDEC5_ERROR + 5)))) + +// Indexed NVENC reference +#define ROBUST_CHANNEL_NVENC_ERROR(x) \ + ((x == 0) ? (ROBUST_CHANNEL_NVENC0_ERROR) : \ + ((x == 1) ? (ROBUST_CHANNEL_NVENC1_ERROR) : \ + (ROBUST_CHANNEL_NVENC2_ERROR))) + +#define ROBUST_CHANNEL_IS_NVENC_ERROR(x) \ + ((x == ROBUST_CHANNEL_NVENC0_ERROR) || \ + (x == ROBUST_CHANNEL_NVENC1_ERROR) || \ + (x == ROBUST_CHANNEL_NVENC2_ERROR)) + +#define ROBUST_CHANNEL_NVENC_ERROR_IDX(x) \ + (((x == ROBUST_CHANNEL_NVENC0_ERROR)) ? \ + (x - ROBUST_CHANNEL_NVENC0_ERROR) : \ + (((x == ROBUST_CHANNEL_NVENC1_ERROR)) ? \ + (x - ROBUST_CHANNEL_NVENC1_ERROR + 1) : \ + (x - ROBUST_CHANNEL_NVENC2_ERROR + 2))) + +// Indexed NVJPG reference +#define ROBUST_CHANNEL_NVJPG_ERROR(x) \ + ((x < 1) ? \ + (ROBUST_CHANNEL_NVJPG0_ERROR) : \ + (ROBUST_CHANNEL_NVJPG1_ERROR + (x - 1))) + +#define ROBUST_CHANNEL_IS_NVJPG_ERROR(x) \ + ((x == ROBUST_CHANNEL_NVJPG0_ERROR) || \ + (x == ROBUST_CHANNEL_NVJPG1_ERROR) || \ + (x == ROBUST_CHANNEL_NVJPG2_ERROR) || \ + (x == ROBUST_CHANNEL_NVJPG3_ERROR) || \ + (x == ROBUST_CHANNEL_NVJPG4_ERROR) || \ + (x == ROBUST_CHANNEL_NVJPG5_ERROR) || \ + (x == ROBUST_CHANNEL_NVJPG6_ERROR) || \ + (x == ROBUST_CHANNEL_NVJPG7_ERROR)) + +#define ROBUST_CHANNEL_NVJPG_ERROR_IDX(x) \ + ((x == ROBUST_CHANNEL_NVJPG0_ERROR) ? \ + (x - ROBUST_CHANNEL_NVJPG0_ERROR) : \ + (x - ROBUST_CHANNEL_NVJPG1_ERROR + 1)) + +// Error Levels +#define ROBUST_CHANNEL_ERROR_RECOVERY_LEVEL_INFO (0) +#define ROBUST_CHANNEL_ERROR_RECOVERY_LEVEL_NON_FATAL (1) +#define ROBUST_CHANNEL_ERROR_RECOVERY_LEVEL_FATAL (2) + +#endif // NVERROR_H diff --git a/userspace/sdks/nv525/nvidia/inc/nvfixedtypes.h b/userspace/sdks/nv525/nvidia/inc/nvfixedtypes.h new file mode 100644 index 0000000..73c7923 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/nvfixedtypes.h @@ -0,0 +1,379 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVFIXEDTYPES_INCLUDED +#define NVFIXEDTYPES_INCLUDED + +#include "nvtypes.h" + +/*! + * Fixed-point master data types. + * + * These are master-types represent the total number of bits contained within + * the FXP type. All FXP types below should be based on one of these master + * types. + */ +typedef NvS16 NvSFXP16; +typedef NvS32 NvSFXP32; +typedef NvS64 NvSFXP64; +typedef NvU16 NvUFXP16; +typedef NvU32 NvUFXP32; +typedef NvU64 NvUFXP64; + + +/*! + * Fixed-point data types. + * + * These are all integer types with precision indicated in the naming of the + * form: NvFXP_. The actual + * size of the data type is calculated as num_bits_above_radix + + * num_bit_below_radix. + * + * All of these FXP types should be based on one of the master types above. + */ +typedef NvSFXP16 NvSFXP11_5; +typedef NvSFXP16 NvSFXP4_12; +typedef NvSFXP16 NvSFXP8_8; +typedef NvSFXP32 NvSFXP8_24; +typedef NvSFXP32 NvSFXP10_22; +typedef NvSFXP32 NvSFXP16_16; +typedef NvSFXP32 NvSFXP18_14; +typedef NvSFXP32 NvSFXP20_12; +typedef NvSFXP32 NvSFXP24_8; +typedef NvSFXP32 NvSFXP27_5; +typedef NvSFXP32 NvSFXP28_4; +typedef NvSFXP32 NvSFXP29_3; +typedef NvSFXP32 NvSFXP31_1; +typedef NvSFXP64 NvSFXP52_12; + +typedef NvUFXP16 NvUFXP0_16; +typedef NvUFXP16 NvUFXP4_12; +typedef NvUFXP16 NvUFXP8_8; +typedef NvUFXP32 NvUFXP3_29; +typedef NvUFXP32 NvUFXP4_28; +typedef NvUFXP32 NvUFXP7_25; +typedef NvUFXP32 NvUFXP8_24; +typedef NvUFXP32 NvUFXP9_23; +typedef NvUFXP32 NvUFXP10_22; +typedef NvUFXP32 NvUFXP15_17; +typedef NvUFXP32 NvUFXP16_16; +typedef NvUFXP32 NvUFXP18_14; +typedef NvUFXP32 NvUFXP20_12; +typedef NvUFXP32 NvUFXP24_8; +typedef NvUFXP32 NvUFXP25_7; +typedef NvUFXP32 NvUFXP26_6; +typedef NvUFXP32 NvUFXP28_4; + +typedef NvUFXP64 NvUFXP40_24; +typedef NvUFXP64 NvUFXP48_16; +typedef NvUFXP64 NvUFXP52_12; + +/*! + * Utility macros used in converting between signed integers and fixed-point + * notation. + * + * - COMMON - These are used by both signed and unsigned. + */ +#define NV_TYPES_FXP_INTEGER(x, y) ((x)+(y)-1):(y) +#define NV_TYPES_FXP_FRACTIONAL(x, y) ((y)-1):0 +#define NV_TYPES_FXP_FRACTIONAL_MSB(x, y) ((y)-1):((y)-1) +#define NV_TYPES_FXP_FRACTIONAL_MSB_ONE 0x00000001 +#define NV_TYPES_FXP_FRACTIONAL_MSB_ZERO 0x00000000 +#define NV_TYPES_FXP_ZERO (0) + +/*! + * - UNSIGNED - These are only used for unsigned. + */ +#define NV_TYPES_UFXP_INTEGER_MAX(x, y) (~(NVBIT((y))-1U)) +#define NV_TYPES_UFXP_INTEGER_MIN(x, y) (0U) + +/*! + * - SIGNED - These are only used for signed. + */ +#define NV_TYPES_SFXP_INTEGER_SIGN(x, y) ((x)+(y)-1):((x)+(y)-1) +#define NV_TYPES_SFXP_INTEGER_SIGN_NEGATIVE 0x00000001 +#define NV_TYPES_SFXP_INTEGER_SIGN_POSITIVE 0x00000000 +#define NV_TYPES_SFXP_S32_SIGN_EXTENSION(x, y) 31:(x) +#define NV_TYPES_SFXP_S32_SIGN_EXTENSION_POSITIVE(x, y) 0x00000000 +#define NV_TYPES_SFXP_S32_SIGN_EXTENSION_NEGATIVE(x, y) (NVBIT(32-(x))-1U) +#define NV_TYPES_SFXP_INTEGER_MAX(x, y) (NVBIT((x))-1U) +#define NV_TYPES_SFXP_INTEGER_MIN(x, y) (~(NVBIT((x))-1U)) +#define NV_TYPES_SFXP_S64_SIGN_EXTENSION(x, y) 63:(x) +#define NV_TYPES_SFXP_S64_SIGN_EXTENSION_POSITIVE(x, y) 0x0000000000000000 +#define NV_TYPES_SFXP_S64_SIGN_EXTENSION_NEGATIVE(x, y) (NVBIT64(64-(x))-1U) +#define NV_TYPES_SFXP_S64_INTEGER_MAX(x, y) (NVBIT64((x)-1)-1U) +#define NV_TYPES_SFXP_S64_INTEGER_MIN(x, y) (~(NVBIT64((x)-1)-1U)) + +/*! + * Conversion macros used for converting between integer and fixed point + * representations. Both signed and unsigned variants. + * + * Warning: + * Note that most of the macros below can overflow if applied on values that can + * not fit the destination type. It's caller responsibility to ensure that such + * situations will not occur. + * + * Some conversions perform some commonly performed tasks other than just + * bit-shifting: + * + * - _SCALED: + * For integer -> fixed-point we add handling divisors to represent + * non-integer values. + * + * - _ROUNDED: + * For fixed-point -> integer we add rounding to integer values. + */ + +// 32-bit Unsigned FXP: +#define NV_TYPES_U32_TO_UFXP_X_Y(x, y, integer) \ + ((NvUFXP##x##_##y) (((NvU32) (integer)) << \ + DRF_SHIFT(NV_TYPES_FXP_INTEGER((x), (y))))) + +#define NV_TYPES_U32_TO_UFXP_X_Y_SCALED(x, y, integer, scale) \ + ((NvUFXP##x##_##y) ((((((NvU32) (integer)) << \ + DRF_SHIFT(NV_TYPES_FXP_INTEGER((x), (y))))) / \ + (scale)) + \ + ((((((NvU32) (integer)) << \ + DRF_SHIFT(NV_TYPES_FXP_INTEGER((x), (y)))) % \ + (scale)) > ((scale) >> 1)) ? 1U : 0U))) + +#define NV_TYPES_UFXP_X_Y_TO_U32(x, y, fxp) \ + ((NvU32) (DRF_VAL(_TYPES, _FXP, _INTEGER((x), (y)), \ + ((NvUFXP##x##_##y) (fxp))))) + +#define NV_TYPES_UFXP_X_Y_TO_U32_ROUNDED(x, y, fxp) \ + (NV_TYPES_UFXP_X_Y_TO_U32(x, y, (fxp)) + \ + (FLD_TEST_DRF_NUM(_TYPES, _FXP, _FRACTIONAL_MSB((x), (y)), \ + NV_TYPES_FXP_FRACTIONAL_MSB_ONE, ((NvUFXP##x##_##y) (fxp))) ? \ + 1U : 0U)) + +// 64-bit Unsigned FXP +#define NV_TYPES_U64_TO_UFXP_X_Y(x, y, integer) \ + ((NvUFXP##x##_##y) (((NvU64) (integer)) << \ + DRF_SHIFT64(NV_TYPES_FXP_INTEGER((x), (y))))) + +#define NV_TYPES_U64_TO_UFXP_X_Y_SCALED(x, y, integer, scale) \ + ((NvUFXP##x##_##y) (((((NvU64) (integer)) << \ + DRF_SHIFT64(NV_TYPES_FXP_INTEGER((x), (y)))) + \ + ((scale) >> 1)) / \ + (scale))) + +#define NV_TYPES_UFXP_X_Y_TO_U64(x, y, fxp) \ + ((NvU64) (DRF_VAL64(_TYPES, _FXP, _INTEGER((x), (y)), \ + ((NvUFXP##x##_##y) (fxp))))) + +#define NV_TYPES_UFXP_X_Y_TO_U64_ROUNDED(x, y, fxp) \ + (NV_TYPES_UFXP_X_Y_TO_U64(x, y, (fxp)) + \ + (FLD_TEST_DRF_NUM64(_TYPES, _FXP, _FRACTIONAL_MSB((x), (y)), \ + NV_TYPES_FXP_FRACTIONAL_MSB_ONE, ((NvUFXP##x##_##y) (fxp))) ? \ + 1U : 0U)) + +// +// 32-bit Signed FXP: +// Some compilers do not support left shift negative values +// so typecast integer to NvU32 instead of NvS32 +// +// Note that there is an issue with the rounding in +// NV_TYPES_S32_TO_SFXP_X_Y_SCALED. In particular, when the signs of the +// numerator and denominator don't match, the rounding is done towards positive +// infinity, rather than away from 0. This will need to be fixed in a follow-up +// change. +// +#define NV_TYPES_S32_TO_SFXP_X_Y(x, y, integer) \ + ((NvSFXP##x##_##y) (((NvU32) (integer)) << \ + DRF_SHIFT(NV_TYPES_FXP_INTEGER((x), (y))))) + +#define NV_TYPES_S32_TO_SFXP_X_Y_SCALED(x, y, integer, scale) \ + ((NvSFXP##x##_##y) (((((NvS32) (integer)) << \ + DRF_SHIFT(NV_TYPES_FXP_INTEGER((x), (y)))) + \ + ((scale) >> 1)) / \ + (scale))) + +#define NV_TYPES_SFXP_X_Y_TO_S32(x, y, fxp) \ + ((NvS32) ((DRF_VAL(_TYPES, _FXP, _INTEGER((x), (y)), \ + ((NvSFXP##x##_##y) (fxp)))) | \ + ((DRF_VAL(_TYPES, _SFXP, _INTEGER_SIGN((x), (y)), (fxp)) == \ + NV_TYPES_SFXP_INTEGER_SIGN_NEGATIVE) ? \ + DRF_NUM(_TYPES, _SFXP, _S32_SIGN_EXTENSION((x), (y)), \ + NV_TYPES_SFXP_S32_SIGN_EXTENSION_NEGATIVE((x), (y))) : \ + DRF_NUM(_TYPES, _SFXP, _S32_SIGN_EXTENSION((x), (y)), \ + NV_TYPES_SFXP_S32_SIGN_EXTENSION_POSITIVE((x), (y)))))) + +/*! + * Note: The rounding action for signed numbers should ideally round away from + * 0 in both the positive and the negative regions. + * For positive numbers, we add 1 if the fractional MSb is 1. + * For negative numbers, we add -1 (equivalent to subtracting 1) if the + * fractional MSb is 1. + */ +#define NV_TYPES_SFXP_X_Y_TO_S32_ROUNDED(x, y, fxp) \ + (NV_TYPES_SFXP_X_Y_TO_S32(x, y, (fxp)) + \ + (FLD_TEST_DRF_NUM(_TYPES, _FXP, _FRACTIONAL_MSB((x), (y)), \ + NV_TYPES_FXP_FRACTIONAL_MSB_ONE, ((NvSFXP##x##_##y) (fxp))) ? \ + ((DRF_VAL(_TYPES, _SFXP, _INTEGER_SIGN((x), (y)), (fxp)) == \ + NV_TYPES_SFXP_INTEGER_SIGN_POSITIVE) ? 1 : -1) : 0)) + +#define NV_TYPES_SFXP_X_Y_TO_FLOAT32(x, y, fxp) \ + ((NvF32) NV_TYPES_SFXP_X_Y_TO_S32(x, y, (fxp)) + \ + ((NvF32) DRF_NUM(_TYPES, _FXP, _FRACTIONAL((x), (y)), \ + ((NvSFXP##x##_##y) (fxp))) / (NvF32) (1 << (y)))) + +// +// 64-bit Signed FXP: +// Some compilers do not support left shift negative values +// so typecast integer to NvU64 instead of NvS64 +// +// Note that there is an issue with the rounding in +// NV_TYPES_S64_TO_SFXP_X_Y_SCALED. In particular, when the signs of the +// numerator and denominator don't match, the rounding is done towards positive +// infinity, rather than away from 0. This will need to be fixed in a follow-up +// change. +// +#define NV_TYPES_S64_TO_SFXP_X_Y(x, y, integer) \ + ((NvSFXP##x##_##y) (((NvU64) (integer)) << \ + DRF_SHIFT64(NV_TYPES_FXP_INTEGER((x), (y))))) + +#define NV_TYPES_S64_TO_SFXP_X_Y_SCALED(x, y, integer, scale) \ + ((NvSFXP##x##_##y) (((((NvS64) (integer)) << \ + DRF_SHIFT64(NV_TYPES_FXP_INTEGER((x), (y)))) + \ + ((scale) >> 1)) / \ + (scale))) + +#define NV_TYPES_SFXP_X_Y_TO_S64(x, y, fxp) \ + ((NvS64) ((DRF_VAL64(_TYPES, _FXP, _INTEGER((x), (y)), \ + ((NvSFXP##x##_##y) (fxp)))) | \ + ((DRF_VAL64(_TYPES, _SFXP, _INTEGER_SIGN((x), (y)), (fxp)) == \ + NV_TYPES_SFXP_INTEGER_SIGN_NEGATIVE) ? \ + DRF_NUM64(_TYPES, _SFXP, _S64_SIGN_EXTENSION((x), (y)), \ + NV_TYPES_SFXP_S64_SIGN_EXTENSION_NEGATIVE((x), (y))) : \ + DRF_NUM64(_TYPES, _SFXP, _S64_SIGN_EXTENSION((x), (y)), \ + NV_TYPES_SFXP_S64_SIGN_EXTENSION_POSITIVE((x), (y)))))) + +/*! + * Note: The rounding action for signed numbers should ideally round away from + * 0 in both the positive and the negative regions. + * For positive numbers, we add 1 if the fractional MSb is 1. + * For negative numbers, we add -1 (equivalent to subtracting 1) if the + * fractional MSb is 1. + */ +#define NV_TYPES_SFXP_X_Y_TO_S64_ROUNDED(x, y, fxp) \ + (NV_TYPES_SFXP_X_Y_TO_S64(x, y, (fxp)) + \ + (FLD_TEST_DRF_NUM64(_TYPES, _FXP, _FRACTIONAL_MSB((x), (y)), \ + NV_TYPES_FXP_FRACTIONAL_MSB_ONE, ((NvSFXP##x##_##y) (fxp))) ? \ + ((DRF_VAL64(_TYPES, _SFXP, _INTEGER_SIGN((x), (y)), (fxp)) == \ + NV_TYPES_SFXP_INTEGER_SIGN_POSITIVE) ? 1 : -1) : 0)) + +/*! + * Macros representing the single-precision IEEE 754 floating point format for + * "binary32", also known as "single" and "float". + * + * Single precision floating point format wiki [1] + * + * _SIGN + * Single bit representing the sign of the number. + * _EXPONENT + * Unsigned 8-bit number representing the exponent value by which to scale + * the mantissa. + * _BIAS - The value by which to offset the exponent to account for sign. + * _MANTISSA + * Explicit 23-bit significand of the value. When exponent != 0, this is an + * implicitly 24-bit number with a leading 1 prepended. This 24-bit number + * can be conceptualized as FXP 9.23. + * + * With these definitions, the value of a floating point number can be + * calculated as: + * (-1)^(_SIGN) * + * 2^(_EXPONENT - _EXPONENT_BIAS) * + * (1 + _MANTISSA / (1 << 23)) + */ +// [1] : https://en.wikipedia.org/wiki/Single_precision_floating-point_format +#define NV_TYPES_SINGLE_SIGN 31:31 +#define NV_TYPES_SINGLE_SIGN_POSITIVE 0x00000000 +#define NV_TYPES_SINGLE_SIGN_NEGATIVE 0x00000001 +#define NV_TYPES_SINGLE_EXPONENT 30:23 +#define NV_TYPES_SINGLE_EXPONENT_ZERO 0x00000000 +#define NV_TYPES_SINGLE_EXPONENT_BIAS 0x0000007F +#define NV_TYPES_SINGLE_MANTISSA 22:0 + + +/*! + * Helper macro to return a IEEE 754 single-precision value's mantissa as an + * unsigned FXP 9.23 value. + * + * @param[in] single IEEE 754 single-precision value to manipulate. + * + * @return IEEE 754 single-precision values mantissa represented as an unsigned + * FXP 9.23 value. + */ +#define NV_TYPES_SINGLE_MANTISSA_TO_UFXP9_23(single) \ + ((NvUFXP9_23)(FLD_TEST_DRF(_TYPES, _SINGLE, _EXPONENT, _ZERO, single) ? \ + NV_TYPES_U32_TO_UFXP_X_Y(9, 23, 0) : \ + (NV_TYPES_U32_TO_UFXP_X_Y(9, 23, 1) + \ + DRF_VAL(_TYPES, _SINGLE, _MANTISSA, single)))) + +/*! + * Helper macro to return an IEEE 754 single-precision value's exponent, + * including the bias. + * + * @param[in] single IEEE 754 single-precision value to manipulate. + * + * @return Signed exponent value for IEEE 754 single-precision. + */ +#define NV_TYPES_SINGLE_EXPONENT_BIASED(single) \ + ((NvS32)(DRF_VAL(_TYPES, _SINGLE, _EXPONENT, single) - \ + NV_TYPES_SINGLE_EXPONENT_BIAS)) + +/*! + * NvTemp - temperature data type introduced to avoid bugs in conversion between + * various existing notations. + */ +typedef NvSFXP24_8 NvTemp; + +/*! + * Macros for NvType <-> Celsius temperature conversion. + */ +#define NV_TYPES_CELSIUS_TO_NV_TEMP(cel) \ + NV_TYPES_S32_TO_SFXP_X_Y(24,8,(cel)) +#define NV_TYPES_NV_TEMP_TO_CELSIUS_TRUNCED(nvt) \ + NV_TYPES_SFXP_X_Y_TO_S32(24,8,(nvt)) +#define NV_TYPES_NV_TEMP_TO_CELSIUS_ROUNDED(nvt) \ + NV_TYPES_SFXP_X_Y_TO_S32_ROUNDED(24,8,(nvt)) +#define NV_TYPES_NV_TEMP_TO_CELSIUS_FLOAT(nvt) \ + NV_TYPES_SFXP_X_Y_TO_FLOAT32(24,8,(nvt)) + +/*! + * Macro for NvType -> number of bits conversion + */ +#define NV_NBITS_IN_TYPE(type) (8 * sizeof(type)) + +/*! + * Macro to convert SFXP 11.5 to NvTemp. + */ +#define NV_TYPES_NVSFXP11_5_TO_NV_TEMP(x) ((NvTemp)(x) << 3) + +/*! + * Macro to convert UFXP11.5 Watts to NvU32 milli-Watts. + */ +#define NV_TYPES_NVUFXP11_5_WATTS_TO_NVU32_MILLI_WATTS(x) ((((NvU32)(x)) * ((NvU32)1000)) >> 5) + +#endif /* NVFIXEDTYPES_INCLUDED */ diff --git a/userspace/sdks/nv525/nvidia/inc/nvgputypes.h b/userspace/sdks/nv525/nvidia/inc/nvgputypes.h new file mode 100644 index 0000000..d018414 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/nvgputypes.h @@ -0,0 +1,177 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2006 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + + /***************************************************************************\ +|* *| +|* NV GPU Types *| +|* *| +|* This header contains definitions describing NVIDIA's GPU hardware state. *| +|* *| + \***************************************************************************/ + + +#ifndef NVGPUTYPES_INCLUDED +#define NVGPUTYPES_INCLUDED +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + + /***************************************************************************\ +|* NvNotification *| + \***************************************************************************/ + +/***** NvNotification Structure *****/ +/* + * NV objects return information about method completion to clients via an + * array of notification structures in main memory. + * + * The client sets the status field to NV???_NOTIFICATION_STATUS_IN_PROGRESS. + * NV fills in the NvNotification[] data structure in the following order: + * timeStamp, otherInfo32, otherInfo16, and then status. + */ + +/* memory data structures */ +typedef volatile struct NvNotificationRec { + struct { /* 0000- */ + NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/ + } timeStamp; /* -0007*/ + NvV32 info32; /* info returned depends on method 0008-000b*/ + NvV16 info16; /* info returned depends on method 000c-000d*/ + NvV16 status; /* user sets bit 15, NV sets status 000e-000f*/ +} NvNotification; + + /***************************************************************************\ +|* NvGpuSemaphore *| + \***************************************************************************/ + +/***** NvGpuSemaphore Structure *****/ +/* + * NvGpuSemaphore objects are used by the GPU to synchronize multiple + * command-streams. + * + * Please refer to class documentation for details regarding the content of + * the data[] field. + */ + +/* memory data structures */ +typedef volatile struct NvGpuSemaphoreRec { + NvV32 data[2]; /* Payload/Report data 0000-0007*/ + struct { /* 0008- */ + NvV32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 8- f*/ + } timeStamp; /* -000f*/ +} NvGpuSemaphore; + + /***************************************************************************\ +|* NvGetReport *| + \***************************************************************************/ + +/* + * NV objects, starting with Kelvin, return information such as pixel counts to + * the user via the NV*_GET_REPORT method. + * + * The client fills in the "zero" field to any nonzero value and waits until it + * becomes zero. NV fills in the timeStamp, value, and zero fields. + */ +typedef volatile struct NVGetReportRec { + struct { /* 0000- */ + NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/ + } timeStamp; /* -0007*/ + NvU32 value; /* info returned depends on method 0008-000b*/ + NvU32 zero; /* always written to zero 000c-000f*/ +} NvGetReport; + + /***************************************************************************\ +|* NvRcNotification *| + \***************************************************************************/ + +/* + * NV robust channel notification information is reported to clients via + * standard NV01_EVENT objects bound to instance of the NV*_CHANNEL_DMA and + * NV*_CHANNEL_GPFIFO objects. + */ +typedef struct NvRcNotificationRec { + struct { + NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/ + } timeStamp; /* -0007*/ + NvU32 exceptLevel; /* exception level 000c-000f*/ + NvU32 exceptType; /* exception type 0010-0013*/ +} NvRcNotification; + + /***************************************************************************\ +|* NvSyncPointFence *| + \***************************************************************************/ + +/***** NvSyncPointFence Structure *****/ +/* + * NvSyncPointFence objects represent a syncpoint event. The syncPointID + * identifies the syncpoint register and the value is the value that the + * register will contain right after the event occurs. + * + * If syncPointID contains NV_INVALID_SYNCPOINT_ID then this is an invalid + * event. This is often used to indicate an event in the past (i.e. no need to + * wait). + * + * For more info on syncpoints refer to Mobile channel and syncpoint + * documentation. + */ +typedef struct NvSyncPointFenceRec { + NvU32 syncPointID; + NvU32 value; +} NvSyncPointFence; + +#define NV_INVALID_SYNCPOINT_ID ((NvU32)-1) + + /***************************************************************************\ +|* *| +|* 64 bit type definitions for use in interface structures. *| +|* *| + \***************************************************************************/ + +typedef NvU64 NvOffset; /* GPU address */ + +#define NvOffset_HI32(n) ((NvU32)(((NvU64)(n)) >> 32)) +#define NvOffset_LO32(n) ((NvU32)((NvU64)(n))) + +/* +* There are two types of GPU-UUIDs available: +* +* (1) a SHA-256 based 32 byte ID, formatted as a 64 character +* hexadecimal string as "GPU-%16x-%08x-%08x-%08x-%024x"; this is +* deprecated. +* +* (2) a SHA-1 based 16 byte ID, formatted as a 32 character +* hexadecimal string as "GPU-%08x-%04x-%04x-%04x-%012x" (the +* canonical format of a UUID); this is the default. +*/ +#define NV_GPU_UUID_SHA1_LEN (16) +#define NV_GPU_UUID_SHA256_LEN (32) +#define NV_GPU_UUID_LEN NV_GPU_UUID_SHA1_LEN + +#ifdef __cplusplus +}; +#endif + +#endif /* NVGPUTYPES_INCLUDED */ diff --git a/userspace/sdks/nv525/nvidia/inc/nvi2c.h b/userspace/sdks/nv525/nvidia/inc/nvi2c.h new file mode 100644 index 0000000..28c1ba5 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/nvi2c.h @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef _NV_I2C_H_ +#define _NV_I2C_H_ + +#define NV_I2C_MSG_WR 0x0000 +#define NV_I2C_MSG_RD 0x0001 + +typedef struct nv_i2c_msg_s +{ + NvU16 addr; + NvU16 flags; + NvU16 len; + NvU8* buf; +} nv_i2c_msg_t; + +#endif diff --git a/userspace/sdks/nv525/nvidia/inc/nvimpshared.h b/userspace/sdks/nv525/nvidia/inc/nvimpshared.h new file mode 100644 index 0000000..eb4dc72 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/nvimpshared.h @@ -0,0 +1,98 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/******************************************************************************\ +* * +* Description: * +* Accommodates sharing of IMP-related structures between kernel interface * +* files and core RM. * +* * +\******************************************************************************/ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: nvimpshared.finn +// + + + + +// +// There are only a small number of discrete dramclk frequencies available on +// the system. This structure contains IMP-relevant information associated +// with a specific dramclk frequency. +// +typedef struct DRAM_CLK_INSTANCE { + NvU32 dram_clk_freq_khz; + + NvU32 mchub_clk_khz; + + NvU32 mc_clk_khz; + + NvU32 max_iso_bw_kbps; + + // + // switch_latency_ns is the maximum time required to switch the dramclk + // frequency to the frequency specified in dram_clk_freq_khz. + // + NvU32 switch_latency_ns; +} DRAM_CLK_INSTANCE; + +// +// This table is used to collect information from other modules that is needed +// for RM IMP calculations. (Used on Tegra only.) +// +#define TEGRA_IMP_IMPORT_DATA_DRAM_TYPE_UNKNOWN 0U +#define TEGRA_IMP_IMPORT_DATA_DRAM_TYPE_LPDDR4 1U +#define TEGRA_IMP_IMPORT_DATA_DRAM_TYPE_LPDDR5 2U + +typedef struct TEGRA_IMP_IMPORT_DATA { + // + // max_iso_bw_kbps stores the maximum possible ISO bandwidth available to + // display, assuming display is the only active ISO client. (Note that ISO + // bandwidth will typically be allocated to multiple clients, so display + // will generally not have access to the maximum possible bandwidth.) + // + NvU32 max_iso_bw_kbps; + + NvU32 dram_type; + // On Orin, each dram channel is 16 bits wide. + NvU32 num_dram_channels; + + // + // dram_clk_instance stores entries for all possible dramclk frequencies, + // sorted by dramclk frequency in increasing order. + // + // "24" is expected to be larger than the actual number of required entries + // (which is provided by a BPMP API), but it can be increased if necessary. + // + // num_dram_clk_entries is filled in with the actual number of distinct + // dramclk entries. + // + NvU32 num_dram_clk_entries; + DRAM_CLK_INSTANCE dram_clk_instance[24]; +} TEGRA_IMP_IMPORT_DATA; diff --git a/userspace/sdks/nv525/nvidia/inc/nvlimits.h b/userspace/sdks/nv525/nvidia/inc/nvlimits.h new file mode 100644 index 0000000..a896adf --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/nvlimits.h @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: nvlimits.finn +// + + + + +/* + * This is the maximum number of GPUs supported in a single system. + */ +#define NV_MAX_DEVICES 32 + +/* + * This is the maximum number of subdevices within a single device. + */ +#define NV_MAX_SUBDEVICES 8 + +/* + * This is the maximum length of the process name string. + */ +#define NV_PROC_NAME_MAX_LENGTH 100U + +/* + * This is the maximum number of heads per GPU. + */ +#define NV_MAX_HEADS 4 diff --git a/userspace/sdks/nv525/nvidia/inc/nvmisc.h b/userspace/sdks/nv525/nvidia/inc/nvmisc.h new file mode 100644 index 0000000..fa33a9f --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/nvmisc.h @@ -0,0 +1,927 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * nvmisc.h + */ +#ifndef __NV_MISC_H +#define __NV_MISC_H + +#ifdef __cplusplus +extern "C" { +#endif //__cplusplus + +#include "nvtypes.h" + +#if !defined(NVIDIA_UNDEF_LEGACY_BIT_MACROS) +// +// Miscellaneous macros useful for bit field manipulations +// +// STUPID HACK FOR CL 19434692. Will revert when fix CL is delivered bfm -> chips_a. +#ifndef BIT +#define BIT(b) (1U<<(b)) +#endif +#ifndef BIT32 +#define BIT32(b) ((NvU32)1U<<(b)) +#endif +#ifndef BIT64 +#define BIT64(b) ((NvU64)1U<<(b)) +#endif + +#endif + +// +// It is recommended to use the following bit macros to avoid macro name +// collisions with other src code bases. +// +#ifndef NVBIT +#define NVBIT(b) (1U<<(b)) +#endif +#ifndef NVBIT_TYPE +#define NVBIT_TYPE(b, t) (((t)1U)<<(b)) +#endif +#ifndef NVBIT32 +#define NVBIT32(b) NVBIT_TYPE(b, NvU32) +#endif +#ifndef NVBIT64 +#define NVBIT64(b) NVBIT_TYPE(b, NvU64) +#endif + +// Helper macro's for 32 bit bitmasks +#define NV_BITMASK32_ELEMENT_SIZE (sizeof(NvU32) << 3) +#define NV_BITMASK32_IDX(chId) (((chId) & ~(0x1F)) >> 5) +#define NV_BITMASK32_OFFSET(chId) ((chId) & (0x1F)) +#define NV_BITMASK32_SET(pChannelMask, chId) \ + (pChannelMask)[NV_BITMASK32_IDX(chId)] |= NVBIT(NV_BITMASK32_OFFSET(chId)) +#define NV_BITMASK32_GET(pChannelMask, chId) \ + ((pChannelMask)[NV_BITMASK32_IDX(chId)] & NVBIT(NV_BITMASK32_OFFSET(chId))) + + +// Index of the 'on' bit (assuming that there is only one). +// Even if multiple bits are 'on', result is in range of 0-31. +#define BIT_IDX_32(n) \ + (((((n) & 0xFFFF0000U) != 0U) ? 0x10U: 0U) | \ + ((((n) & 0xFF00FF00U) != 0U) ? 0x08U: 0U) | \ + ((((n) & 0xF0F0F0F0U) != 0U) ? 0x04U: 0U) | \ + ((((n) & 0xCCCCCCCCU) != 0U) ? 0x02U: 0U) | \ + ((((n) & 0xAAAAAAAAU) != 0U) ? 0x01U: 0U) ) + +// Index of the 'on' bit (assuming that there is only one). +// Even if multiple bits are 'on', result is in range of 0-63. +#define BIT_IDX_64(n) \ + (((((n) & 0xFFFFFFFF00000000ULL) != 0U) ? 0x20U: 0U) | \ + ((((n) & 0xFFFF0000FFFF0000ULL) != 0U) ? 0x10U: 0U) | \ + ((((n) & 0xFF00FF00FF00FF00ULL) != 0U) ? 0x08U: 0U) | \ + ((((n) & 0xF0F0F0F0F0F0F0F0ULL) != 0U) ? 0x04U: 0U) | \ + ((((n) & 0xCCCCCCCCCCCCCCCCULL) != 0U) ? 0x02U: 0U) | \ + ((((n) & 0xAAAAAAAAAAAAAAAAULL) != 0U) ? 0x01U: 0U) ) + +/*! + * DRF MACRO README: + * + * Glossary: + * DRF: Device, Register, Field + * FLD: Field + * REF: Reference + * + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA 0xDEADBEEF + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_GAMMA 27:0 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA 31:28 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_ZERO 0x00000000 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_ONE 0x00000001 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_TWO 0x00000002 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_THREE 0x00000003 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_FOUR 0x00000004 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_FIVE 0x00000005 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_SIX 0x00000006 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_SEVEN 0x00000007 + * + * + * Device = _DEVICE_OMEGA + * This is the common "base" that a group of registers in a manual share + * + * Register = _REGISTER_ALPHA + * Register for a given block of defines is the common root for one or more fields and constants + * + * Field(s) = _FIELD_GAMMA, _FIELD_ZETA + * These are the bit ranges for a given field within the register + * Fields are not required to have defined constant values (enumerations) + * + * Constant(s) = _ZERO, _ONE, _TWO, ... + * These are named values (enums) a field can contain; the width of the constants should not be larger than the field width + * + * MACROS: + * + * DRF_SHIFT: + * Bit index of the lower bound of a field + * DRF_SHIFT(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 28 + * + * DRF_SHIFT_RT: + * Bit index of the higher bound of a field + * DRF_SHIFT_RT(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 31 + * + * DRF_MASK: + * Produces a mask of 1-s equal to the width of a field + * DRF_MASK(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 0xF (four 1s starting at bit 0) + * + * DRF_SHIFTMASK: + * Produces a mask of 1s equal to the width of a field at the location of the field + * DRF_SHIFTMASK(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 0xF0000000 + * + * DRF_DEF: + * Shifts a field constant's value to the correct field offset + * DRF_DEF(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, _THREE) == 0x30000000 + * + * DRF_NUM: + * Shifts a number to the location of a particular field + * DRF_NUM(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, 3) == 0x30000000 + * NOTE: If the value passed in is wider than the field, the value's high bits will be truncated + * + * DRF_SIZE: + * Provides the width of the field in bits + * DRF_SIZE(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 4 + * + * DRF_VAL: + * Provides the value of an input within the field specified + * DRF_VAL(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, 0xABCD1234) == 0xA + * This is sort of like the inverse of DRF_NUM + * + * DRF_IDX...: + * These macros are similar to the above but for fields that accept an index argumment + * + * FLD_SET_DRF: + * Set the field bits in a given value with the given field constant + * NvU32 x = 0x00001234; + * x = FLD_SET_DRF(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, _THREE, x); + * x == 0x30001234; + * + * FLD_SET_DRF_NUM: + * Same as FLD_SET_DRF but instead of using a field constant a literal/variable is passed in + * NvU32 x = 0x00001234; + * x = FLD_SET_DRF_NUM(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, 0xF, x); + * x == 0xF0001234; + * + * FLD_IDX...: + * These macros are similar to the above but for fields that accept an index argumment + * + * FLD_TEST_DRF: + * Test if location specified by drf in 'v' has the same value as NV_drfc + * FLD_TEST_DRF(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, _THREE, 0x3000ABCD) == NV_TRUE + * + * FLD_TEST_DRF_NUM: + * Test if locations specified by drf in 'v' have the same value as n + * FLD_TEST_DRF_NUM(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, 0x3, 0x3000ABCD) == NV_TRUE + * + * REF_DEF: + * Like DRF_DEF but maintains full symbol name (use in cases where "NV" is not prefixed to the field) + * REF_DEF(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, _THREE) == 0x30000000 + * + * REF_VAL: + * Like DRF_VAL but maintains full symbol name (use in cases where "NV" is not prefixed to the field) + * REF_VAL(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, 0xABCD1234) == 0xA + * + * REF_NUM: + * Like DRF_NUM but maintains full symbol name (use in cases where "NV" is not prefixed to the field) + * REF_NUM(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, 0xA) == 0xA00000000 + * + * FLD_SET_REF_NUM: + * Like FLD_SET_DRF_NUM but maintains full symbol name (use in cases where "NV" is not prefixed to the field) + * NvU32 x = 0x00001234; + * x = FLD_SET_REF_NUM(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, 0xF, x); + * x == 0xF0001234; + * + * FLD_TEST_REF: + * Like FLD_TEST_DRF but maintains full symbol name (use in cases where "NV" is not prefixed to the field) + * FLD_TEST_REF(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, _THREE, 0x3000ABCD) == NV_TRUE + * + * Other macros: + * There a plethora of other macros below that extend the above (notably Multi-Word (MW), 64-bit, and some + * reg read/write variations). I hope these are self explanatory. If you have a need to use them, you + * probably have some knowledge of how they work. + */ + +// tegra mobile uses nvmisc_macros.h and can't access nvmisc.h... and sometimes both get included. +#ifndef _NVMISC_MACROS_H +// Use Coverity Annotation to mark issues as false positives/ignore when using single bit defines. +#define DRF_ISBIT(bitval,drf) \ + ( /* coverity[identical_branches] */ \ + (bitval != 0) ? drf ) +#define DEVICE_BASE(d) (0?d) // what's up with this name? totally non-parallel to the macros below +#define DEVICE_EXTENT(d) (1?d) // what's up with this name? totally non-parallel to the macros below +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +#ifdef MISRA_14_3 +#define DRF_BASE(drf) (drf##_LOW_FIELD) +#define DRF_EXTENT(drf) (drf##_HIGH_FIELD) +#define DRF_SHIFT(drf) ((drf##_LOW_FIELD) % 32U) +#define DRF_SHIFT_RT(drf) ((drf##_HIGH_FIELD) % 32U) +#define DRF_SIZE(drf) ((drf##_HIGH_FIELD)-(drf##_LOW_FIELD)+1U) +#define DRF_MASK(drf) (0xFFFFFFFFU >> (31U - ((drf##_HIGH_FIELD) % 32U) + ((drf##_LOW_FIELD) % 32U))) +#else +#define DRF_BASE(drf) (NV_FALSE?drf) // much better +#define DRF_EXTENT(drf) (NV_TRUE?drf) // much better +#define DRF_SHIFT(drf) (((NvU32)DRF_BASE(drf)) % 32U) +#define DRF_SHIFT_RT(drf) (((NvU32)DRF_EXTENT(drf)) % 32U) +#define DRF_SIZE(drf) (DRF_EXTENT(drf)-DRF_BASE(drf)+1U) +#define DRF_MASK(drf) (0xFFFFFFFFU>>(31U - DRF_SHIFT_RT(drf) + DRF_SHIFT(drf))) +#endif +#define DRF_DEF(d,r,f,c) (((NvU32)(NV ## d ## r ## f ## c))<>(31-((DRF_ISBIT(1,drf)) % 32)+((DRF_ISBIT(0,drf)) % 32))) +#define DRF_DEF(d,r,f,c) ((NV ## d ## r ## f ## c)<>DRF_SHIFT(NV ## d ## r ## f))&DRF_MASK(NV ## d ## r ## f)) +#endif + +// Signed version of DRF_VAL, which takes care of extending sign bit. +#define DRF_VAL_SIGNED(d,r,f,v) (((DRF_VAL(d,r,f,(v)) ^ (NVBIT(DRF_SIZE(NV ## d ## r ## f)-1U)))) - (NVBIT(DRF_SIZE(NV ## d ## r ## f)-1U))) +#define DRF_IDX_DEF(d,r,f,i,c) ((NV ## d ## r ## f ## c)<>DRF_SHIFT(NV##d##r##f(i)))&DRF_MASK(NV##d##r##f(i))) +#define DRF_IDX_OFFSET_VAL(d,r,f,i,o,v) (((v)>>DRF_SHIFT(NV##d##r##f(i,o)))&DRF_MASK(NV##d##r##f(i,o))) +// Fractional version of DRF_VAL which reads Fx.y fixed point number (x.y)*z +#define DRF_VAL_FRAC(d,r,x,y,v,z) ((DRF_VAL(d,r,x,(v))*z) + ((DRF_VAL(d,r,y,v)*z) / (1<>(63-((DRF_ISBIT(1,drf)) % 64)+((DRF_ISBIT(0,drf)) % 64))) +#define DRF_SHIFTMASK64(drf) (DRF_MASK64(drf)<<(DRF_SHIFT64(drf))) + +#define DRF_DEF64(d,r,f,c) (((NvU64)(NV ## d ## r ## f ## c))<>DRF_SHIFT64(NV ## d ## r ## f))&DRF_MASK64(NV ## d ## r ## f)) + +#define DRF_VAL_SIGNED64(d,r,f,v) (((DRF_VAL64(d,r,f,(v)) ^ (NVBIT64(DRF_SIZE(NV ## d ## r ## f)-1)))) - (NVBIT64(DRF_SIZE(NV ## d ## r ## f)-1))) +#define DRF_IDX_DEF64(d,r,f,i,c) (((NvU64)(NV ## d ## r ## f ## c))<>DRF_SHIFT64(NV##d##r##f(i)))&DRF_MASK64(NV##d##r##f(i))) +#define DRF_IDX_OFFSET_VAL64(d,r,f,i,o,v) (((NvU64)(v)>>DRF_SHIFT64(NV##d##r##f(i,o)))&DRF_MASK64(NV##d##r##f(i,o))) + +#define FLD_SET_DRF64(d,r,f,c,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f)) | DRF_DEF64(d,r,f,c)) +#define FLD_SET_DRF_NUM64(d,r,f,n,v) ((((NvU64)(v)) & ~DRF_SHIFTMASK64(NV##d##r##f)) | DRF_NUM64(d,r,f,n)) +#define FLD_IDX_SET_DRF64(d,r,f,i,c,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f(i))) | DRF_IDX_DEF64(d,r,f,i,c)) +#define FLD_IDX_OFFSET_SET_DRF64(d,r,f,i,o,c,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f(i,o))) | DRF_IDX_OFFSET_DEF64(d,r,f,i,o,c)) +#define FLD_IDX_SET_DRF_DEF64(d,r,f,i,c,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f(i))) | DRF_IDX_DEF64(d,r,f,i,c)) +#define FLD_IDX_SET_DRF_NUM64(d,r,f,i,n,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f(i))) | DRF_IDX_NUM64(d,r,f,i,n)) +#define FLD_SET_DRF_IDX64(d,r,f,c,i,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f)) | DRF_DEF64(d,r,f,c(i))) + +#define FLD_TEST_DRF64(d,r,f,c,v) (DRF_VAL64(d, r, f, (v)) == NV##d##r##f##c) +#define FLD_TEST_DRF_AND64(d,r,f,c,v) (DRF_VAL64(d, r, f, (v)) & NV##d##r##f##c) +#define FLD_TEST_DRF_NUM64(d,r,f,n,v) (DRF_VAL64(d, r, f, (v)) == (n)) +#define FLD_IDX_TEST_DRF64(d,r,f,i,c,v) (DRF_IDX_VAL64(d, r, f, i, (v)) == NV##d##r##f##c) +#define FLD_IDX_OFFSET_TEST_DRF64(d,r,f,i,o,c,v) (DRF_IDX_OFFSET_VAL64(d, r, f, i, o, (v)) == NV##d##r##f##c) + +#define REF_DEF64(drf,d) (((drf ## d)&DRF_MASK64(drf))<>DRF_SHIFT64(drf))&DRF_MASK64(drf)) +#if defined(NV_MISRA_COMPLIANCE_REQUIRED) && defined(MISRA_14_3) +#define REF_NUM64(drf,n) (((NvU64)(n)&(0xFFFFFFFFFFFFFFFFU>>(63U-((drf##_HIGH_FIELD) % 63U)+((drf##_LOW_FIELD) % 63U)))) << ((drf##_LOW_FIELD) % 63U)) +#else +#define REF_NUM64(drf,n) (((NvU64)(n)&DRF_MASK64(drf))<>DRF_SHIFT(drf))&DRF_MASK(drf)) +#if defined(NV_MISRA_COMPLIANCE_REQUIRED) && defined(MISRA_14_3) +#define REF_NUM(drf,n) (((n)&(0xFFFFFFFFU>>(31U-((drf##_HIGH_FIELD) % 32U)+((drf##_LOW_FIELD) % 32U)))) << ((drf##_LOW_FIELD) % 32U)) +#else +#define REF_NUM(drf,n) (((n)&DRF_MASK(drf))<>DRF_SHIFT(CR ## d ## r ## f))&DRF_MASK(CR ## d ## r ## f)) + +// Multi-word (MW) field manipulations. For multi-word structures (e.g., Fermi SPH), +// fields may have bit numbers beyond 32. To avoid errors using "classic" multi-word macros, +// all the field extents are defined as "MW(X)". For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. +// +// DRF_VAL_MW() macro is meant to be used for native endian 32-bit aligned 32-bit word data, +// not for byte stream data. +// +// DRF_VAL_BS() macro is for byte stream data used in fbQueryBIOS_XXX(). +// +#define DRF_EXPAND_MW(drf) drf // used to turn "MW(a:b)" into "a:b" +#define DRF_PICK_MW(drf,v) ((v)? DRF_EXPAND_##drf) // picks low or high bits +#define DRF_WORD_MW(drf) (DRF_PICK_MW(drf,0)/32) // which word in a multi-word array +#define DRF_BASE_MW(drf) (DRF_PICK_MW(drf,0)%32) // which start bit in the selected word? +#define DRF_EXTENT_MW(drf) (DRF_PICK_MW(drf,1)%32) // which end bit in the selected word +#define DRF_SHIFT_MW(drf) (DRF_PICK_MW(drf,0)%32) +#define DRF_MASK_MW(drf) (0xFFFFFFFFU>>((31-(DRF_EXTENT_MW(drf))+(DRF_BASE_MW(drf)))%32)) +#define DRF_SHIFTMASK_MW(drf) ((DRF_MASK_MW(drf))<<(DRF_SHIFT_MW(drf))) +#define DRF_SIZE_MW(drf) (DRF_EXTENT_MW(drf)-DRF_BASE_MW(drf)+1) + +#define DRF_DEF_MW(d,r,f,c) ((NV##d##r##f##c) << DRF_SHIFT_MW(NV##d##r##f)) +#define DRF_NUM_MW(d,r,f,n) (((n)&DRF_MASK_MW(NV##d##r##f))<>DRF_SHIFT_MW(NV##d##r##f))&DRF_MASK_MW(NV##d##r##f)) +#define DRF_SPANS(drf) ((DRF_PICK_MW(drf,0)/32) != (DRF_PICK_MW(drf,1)/32)) +#define DRF_WORD_MW_LOW(drf) (DRF_PICK_MW(drf,0)/32) +#define DRF_WORD_MW_HIGH(drf) (DRF_PICK_MW(drf,1)/32) +#define DRF_MASK_MW_LOW(drf) (0xFFFFFFFFU) +#define DRF_MASK_MW_HIGH(drf) (0xFFFFFFFFU>>(31-(DRF_EXTENT_MW(drf)))) +#define DRF_SHIFT_MW_LOW(drf) (DRF_PICK_MW(drf,0)%32) +#define DRF_SHIFT_MW_HIGH(drf) (0) +#define DRF_MERGE_SHIFT(drf) ((32-((DRF_PICK_MW(drf,0)%32)))%32) +#define DRF_VAL_MW_2WORD(d,r,f,v) (((((v)[DRF_WORD_MW_LOW(NV##d##r##f)])>>DRF_SHIFT_MW_LOW(NV##d##r##f))&DRF_MASK_MW_LOW(NV##d##r##f)) | \ + (((((v)[DRF_WORD_MW_HIGH(NV##d##r##f)])>>DRF_SHIFT_MW_HIGH(NV##d##r##f))&DRF_MASK_MW_HIGH(NV##d##r##f)) << DRF_MERGE_SHIFT(NV##d##r##f))) +#define DRF_VAL_MW(d,r,f,v) ( DRF_SPANS(NV##d##r##f) ? DRF_VAL_MW_2WORD(d,r,f,v) : DRF_VAL_MW_1WORD(d,r,f,v) ) + +#define DRF_IDX_DEF_MW(d,r,f,i,c) ((NV##d##r##f##c)<>DRF_SHIFT_MW(NV##d##r##f(i)))&DRF_MASK_MW(NV##d##r##f(i))) + +// +// Logically OR all DRF_DEF constants indexed from zero to s (semiinclusive). +// Caution: Target variable v must be pre-initialized. +// +#define FLD_IDX_OR_DRF_DEF(d,r,f,c,s,v) \ +do \ +{ NvU32 idx; \ + for (idx = 0; idx < (NV ## d ## r ## f ## s); ++idx)\ + { \ + v |= DRF_IDX_DEF(d,r,f,idx,c); \ + } \ +} while(0) + + +#define FLD_MERGE_MW(drf,n,v) (((v)[DRF_WORD_MW(drf)] & ~DRF_SHIFTMASK_MW(drf)) | n) +#define FLD_ASSIGN_MW(drf,n,v) ((v)[DRF_WORD_MW(drf)] = FLD_MERGE_MW(drf, n, v)) +#define FLD_IDX_MERGE_MW(drf,i,n,v) (((v)[DRF_WORD_MW(drf(i))] & ~DRF_SHIFTMASK_MW(drf(i))) | n) +#define FLD_IDX_ASSIGN_MW(drf,i,n,v) ((v)[DRF_WORD_MW(drf(i))] = FLD_MERGE_MW(drf(i), n, v)) + +#define FLD_SET_DRF_MW(d,r,f,c,v) FLD_MERGE_MW(NV##d##r##f, DRF_DEF_MW(d,r,f,c), v) +#define FLD_SET_DRF_NUM_MW(d,r,f,n,v) FLD_ASSIGN_MW(NV##d##r##f, DRF_NUM_MW(d,r,f,n), v) +#define FLD_SET_DRF_DEF_MW(d,r,f,c,v) FLD_ASSIGN_MW(NV##d##r##f, DRF_DEF_MW(d,r,f,c), v) +#define FLD_IDX_SET_DRF_MW(d,r,f,i,c,v) FLD_IDX_MERGE_MW(NV##d##r##f, i, DRF_IDX_DEF_MW(d,r,f,i,c), v) +#define FLD_IDX_SET_DRF_DEF_MW(d,r,f,i,c,v) FLD_IDX_MERGE_MW(NV##d##r##f, i, DRF_IDX_DEF_MW(d,r,f,i,c), v) +#define FLD_IDX_SET_DRF_NUM_MW(d,r,f,i,n,v) FLD_IDX_ASSIGN_MW(NV##d##r##f, i, DRF_IDX_NUM_MW(d,r,f,i,n), v) + +#define FLD_TEST_DRF_MW(d,r,f,c,v) ((DRF_VAL_MW(d, r, f, (v)) == NV##d##r##f##c)) +#define FLD_TEST_DRF_NUM_MW(d,r,f,n,v) ((DRF_VAL_MW(d, r, f, (v)) == n)) +#define FLD_IDX_TEST_DRF_MW(d,r,f,i,c,v) ((DRF_IDX_VAL_MW(d, r, f, i, (v)) == NV##d##r##f##c)) + +#define DRF_VAL_BS(d,r,f,v) ( DRF_SPANS(NV##d##r##f) ? DRF_VAL_BS_2WORD(d,r,f,(v)) : DRF_VAL_BS_1WORD(d,r,f,(v)) ) + +//------------------------------------------------------------------------// +// // +// Common defines for engine register reference wrappers // +// // +// New engine addressing can be created like: // +// \#define ENG_REG_PMC(o,d,r) NV##d##r // +// \#define ENG_IDX_REG_CE(o,d,i,r) CE_MAP(o,r,i) // +// // +// See FB_FBPA* for more examples // +//------------------------------------------------------------------------// + +#define ENG_RD_REG(g,o,d,r) GPU_REG_RD32(g, ENG_REG##d(o,d,r)) +#define ENG_WR_REG(g,o,d,r,v) GPU_REG_WR32(g, ENG_REG##d(o,d,r), (v)) +#define ENG_RD_DRF(g,o,d,r,f) ((GPU_REG_RD32(g, ENG_REG##d(o,d,r))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) +#define ENG_WR_DRF_DEF(g,o,d,r,f,c) GPU_REG_WR32(g, ENG_REG##d(o,d,r),(GPU_REG_RD32(g,ENG_REG##d(o,d,r))&~(GPU_DRF_MASK(NV##d##r##f)<>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) +#define ENG_TEST_IDX_DRF_DEF(g,o,d,r,f,c,i) (ENG_RD_IDX_DRF(g, o, d, r, f, (i)) == NV##d##r##f##c) + +#define ENG_IDX_RD_REG(g,o,d,i,r) GPU_REG_RD32(g, ENG_IDX_REG##d(o,d,i,r)) +#define ENG_IDX_WR_REG(g,o,d,i,r,v) GPU_REG_WR32(g, ENG_IDX_REG##d(o,d,i,r), (v)) + +#define ENG_IDX_RD_DRF(g,o,d,i,r,f) ((GPU_REG_RD32(g, ENG_IDX_REG##d(o,d,i,r))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) + +// +// DRF_READ_1WORD_BS() and DRF_READ_1WORD_BS_HIGH() do not read beyond the bytes that contain +// the requested value. Reading beyond the actual data causes a page fault panic when the +// immediately following page happened to be protected or not mapped. +// +#define DRF_VAL_BS_1WORD(d,r,f,v) ((DRF_READ_1WORD_BS(d,r,f,v)>>DRF_SHIFT_MW(NV##d##r##f))&DRF_MASK_MW(NV##d##r##f)) +#define DRF_VAL_BS_2WORD(d,r,f,v) (((DRF_READ_4BYTE_BS(NV##d##r##f,v)>>DRF_SHIFT_MW_LOW(NV##d##r##f))&DRF_MASK_MW_LOW(NV##d##r##f)) | \ + (((DRF_READ_1WORD_BS_HIGH(d,r,f,v)>>DRF_SHIFT_MW_HIGH(NV##d##r##f))&DRF_MASK_MW_HIGH(NV##d##r##f)) << DRF_MERGE_SHIFT(NV##d##r##f))) + +#define DRF_READ_1BYTE_BS(drf,v) ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW(drf)*4])) +#define DRF_READ_2BYTE_BS(drf,v) (DRF_READ_1BYTE_BS(drf,v)| \ + ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW(drf)*4+1])<<8)) +#define DRF_READ_3BYTE_BS(drf,v) (DRF_READ_2BYTE_BS(drf,v)| \ + ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW(drf)*4+2])<<16)) +#define DRF_READ_4BYTE_BS(drf,v) (DRF_READ_3BYTE_BS(drf,v)| \ + ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW(drf)*4+3])<<24)) + +#define DRF_READ_1BYTE_BS_HIGH(drf,v) ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW_HIGH(drf)*4])) +#define DRF_READ_2BYTE_BS_HIGH(drf,v) (DRF_READ_1BYTE_BS_HIGH(drf,v)| \ + ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW_HIGH(drf)*4+1])<<8)) +#define DRF_READ_3BYTE_BS_HIGH(drf,v) (DRF_READ_2BYTE_BS_HIGH(drf,v)| \ + ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW_HIGH(drf)*4+2])<<16)) +#define DRF_READ_4BYTE_BS_HIGH(drf,v) (DRF_READ_3BYTE_BS_HIGH(drf,v)| \ + ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW_HIGH(drf)*4+3])<<24)) + +// Calculate 2^n - 1 and avoid shift counter overflow +// +// On Windows amd64, 64 << 64 => 1 +// +#define NV_TWO_N_MINUS_ONE(n) (((1ULL<<(n/2))<<((n+1)/2))-1) + +#define DRF_READ_1WORD_BS(d,r,f,v) \ + ((DRF_EXTENT_MW(NV##d##r##f)<8)?DRF_READ_1BYTE_BS(NV##d##r##f,(v)): \ + ((DRF_EXTENT_MW(NV##d##r##f)<16)?DRF_READ_2BYTE_BS(NV##d##r##f,(v)): \ + ((DRF_EXTENT_MW(NV##d##r##f)<24)?DRF_READ_3BYTE_BS(NV##d##r##f,(v)): \ + DRF_READ_4BYTE_BS(NV##d##r##f,(v))))) + +#define DRF_READ_1WORD_BS_HIGH(d,r,f,v) \ + ((DRF_EXTENT_MW(NV##d##r##f)<8)?DRF_READ_1BYTE_BS_HIGH(NV##d##r##f,(v)): \ + ((DRF_EXTENT_MW(NV##d##r##f)<16)?DRF_READ_2BYTE_BS_HIGH(NV##d##r##f,(v)): \ + ((DRF_EXTENT_MW(NV##d##r##f)<24)?DRF_READ_3BYTE_BS_HIGH(NV##d##r##f,(v)): \ + DRF_READ_4BYTE_BS_HIGH(NV##d##r##f,(v))))) + +#define LOWESTBIT(x) ( (x) & (((x) - 1U) ^ (x)) ) +// Destructive operation on n32 +#define HIGHESTBIT(n32) \ +{ \ + HIGHESTBITIDX_32(n32); \ + n32 = NVBIT(n32); \ +} +#define ONEBITSET(x) ( ((x) != 0U) && (((x) & ((x) - 1U)) == 0U) ) + +// Destructive operation on n32 +#define NUMSETBITS_32(n32) \ +{ \ + n32 = n32 - ((n32 >> 1) & 0x55555555); \ + n32 = (n32 & 0x33333333) + ((n32 >> 2) & 0x33333333); \ + n32 = (((n32 + (n32 >> 4)) & 0x0F0F0F0F) * 0x01010101) >> 24; \ +} + +/*! + * Calculate number of bits set in a 32-bit unsigned integer. + * Pure typesafe alternative to @ref NUMSETBITS_32. + */ +static NV_FORCEINLINE NvU32 +nvPopCount32(const NvU32 x) +{ + NvU32 temp = x; + temp = temp - ((temp >> 1) & 0x55555555U); + temp = (temp & 0x33333333U) + ((temp >> 2) & 0x33333333U); + temp = (((temp + (temp >> 4)) & 0x0F0F0F0FU) * 0x01010101U) >> 24; + return temp; +} + +/*! + * Calculate number of bits set in a 64-bit unsigned integer. + */ +static NV_FORCEINLINE NvU32 +nvPopCount64(const NvU64 x) +{ + NvU64 temp = x; + temp = temp - ((temp >> 1) & 0x5555555555555555ULL); + temp = (temp & 0x3333333333333333ULL) + ((temp >> 2) & 0x3333333333333333ULL); + temp = (temp + (temp >> 4)) & 0x0F0F0F0F0F0F0F0FULL; + temp = (temp * 0x0101010101010101ULL) >> 56; + return (NvU32)temp; +} + +/*! + * Determine how many bits are set below a bit index within a mask. + * This assigns a dense ordering to the set bits in the mask. + * + * For example the mask 0xCD contains 5 set bits: + * nvMaskPos32(0xCD, 0) == 0 + * nvMaskPos32(0xCD, 2) == 1 + * nvMaskPos32(0xCD, 3) == 2 + * nvMaskPos32(0xCD, 6) == 3 + * nvMaskPos32(0xCD, 7) == 4 + */ +static NV_FORCEINLINE NvU32 +nvMaskPos32(const NvU32 mask, const NvU32 bitIdx) +{ + return nvPopCount32(mask & (NVBIT32(bitIdx) - 1U)); +} + +// Destructive operation on n32 +#define LOWESTBITIDX_32(n32) \ +{ \ + n32 = BIT_IDX_32(LOWESTBIT(n32));\ +} + +// Destructive operation on n32 +#define HIGHESTBITIDX_32(n32) \ +{ \ + NvU32 count = 0; \ + while (n32 >>= 1) \ + { \ + count++; \ + } \ + n32 = count; \ +} + +// Destructive operation on n32 +#define ROUNDUP_POW2(n32) \ +{ \ + n32--; \ + n32 |= n32 >> 1; \ + n32 |= n32 >> 2; \ + n32 |= n32 >> 4; \ + n32 |= n32 >> 8; \ + n32 |= n32 >> 16; \ + n32++; \ +} + +/*! + * Round up a 32-bit unsigned integer to the next power of 2. + * Pure typesafe alternative to @ref ROUNDUP_POW2. + * + * param[in] x must be in range [0, 2^31] to avoid overflow. + */ +static NV_FORCEINLINE NvU32 +nvNextPow2_U32(const NvU32 x) +{ + NvU32 y = x; + y--; + y |= y >> 1; + y |= y >> 2; + y |= y >> 4; + y |= y >> 8; + y |= y >> 16; + y++; + return y; +} + + +static NV_FORCEINLINE NvU32 +nvPrevPow2_U32(const NvU32 x ) +{ + NvU32 y = x; + y |= (y >> 1); + y |= (y >> 2); + y |= (y >> 4); + y |= (y >> 8); + y |= (y >> 16); + return y - (y >> 1); +} + +static NV_FORCEINLINE NvU64 +nvPrevPow2_U64(const NvU64 x ) +{ + NvU64 y = x; + y |= (y >> 1); + y |= (y >> 2); + y |= (y >> 4); + y |= (y >> 8); + y |= (y >> 16); + y |= (y >> 32); + return y - (y >> 1); +} + +// Destructive operation on n64 +#define ROUNDUP_POW2_U64(n64) \ +{ \ + n64--; \ + n64 |= n64 >> 1; \ + n64 |= n64 >> 2; \ + n64 |= n64 >> 4; \ + n64 |= n64 >> 8; \ + n64 |= n64 >> 16; \ + n64 |= n64 >> 32; \ + n64++; \ +} + +#define NV_SWAP_U8(a,b) \ +{ \ + NvU8 temp; \ + temp = a; \ + a = b; \ + b = temp; \ +} + +#define NV_SWAP_U32(a,b) \ +{ \ + NvU32 temp; \ + temp = a; \ + a = b; \ + b = temp; \ +} + +/*! + * @brief Macros allowing simple iteration over bits set in a given mask. + * + * @param[in] maskWidth bit-width of the mask (allowed: 8, 16, 32, 64) + * + * @param[in,out] index lvalue that is used as a bit index in the loop + * (can be declared as any NvU* or NvS* variable) + * @param[in] mask expression, loop will iterate over set bits only + */ +#define FOR_EACH_INDEX_IN_MASK(maskWidth,index,mask) \ +{ \ + NvU##maskWidth lclMsk = (NvU##maskWidth)(mask); \ + for ((index) = 0U; lclMsk != 0U; (index)++, lclMsk >>= 1U)\ + { \ + if (((NvU##maskWidth)NVBIT64(0) & lclMsk) == 0U) \ + { \ + continue; \ + } +#define FOR_EACH_INDEX_IN_MASK_END \ + } \ +} + +// +// Size to use when declaring variable-sized arrays +// +#define NV_ANYSIZE_ARRAY 1 + +// +// Returns ceil(a/b) +// +#define NV_CEIL(a,b) (((a)+(b)-1)/(b)) + +// Clearer name for NV_CEIL +#ifndef NV_DIV_AND_CEIL +#define NV_DIV_AND_CEIL(a, b) NV_CEIL(a,b) +#endif + +#ifndef NV_MIN +#define NV_MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef NV_MAX +#define NV_MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +// +// Returns absolute value of provided integer expression +// +#define NV_ABS(a) ((a)>=0?(a):(-(a))) + +// +// Returns 1 if input number is positive, 0 if 0 and -1 if negative. Avoid +// macro parameter as function call which will have side effects. +// +#define NV_SIGN(s) ((NvS8)(((s) > 0) - ((s) < 0))) + +// +// Returns 1 if input number is >= 0 or -1 otherwise. This assumes 0 has a +// positive sign. +// +#define NV_ZERO_SIGN(s) ((NvS8)((((s) >= 0) * 2) - 1)) + +// Returns the offset (in bytes) of 'member' in struct 'type'. +#ifndef NV_OFFSETOF + #if defined(__GNUC__) && (__GNUC__ > 3) + #define NV_OFFSETOF(type, member) ((NvU32)__builtin_offsetof(type, member)) + #else + #define NV_OFFSETOF(type, member) ((NvU32)(NvU64)&(((type *)0)->member)) // shouldn't we use PtrToUlong? But will need to include windows header. + #endif +#endif + +// +// Performs a rounded division of b into a (unsigned). For SIGNED version of +// NV_ROUNDED_DIV() macro check the comments in bug 769777. +// +#define NV_UNSIGNED_ROUNDED_DIV(a,b) (((a) + ((b) / 2U)) / (b)) + +/*! + * Performs a ceiling division of b into a (unsigned). A "ceiling" division is + * a division is one with rounds up result up if a % b != 0. + * + * @param[in] a Numerator + * @param[in] b Denominator + * + * @return a / b + a % b != 0 ? 1 : 0. + */ +#define NV_UNSIGNED_DIV_CEIL(a, b) (((a) + (b - 1)) / (b)) + +/*! + * Performs subtraction where a negative difference is raised to zero. + * Can be used to avoid underflowing an unsigned subtraction. + * + * @param[in] a Minuend + * @param[in] b Subtrahend + * + * @return a > b ? a - b : 0. + */ +#define NV_SUBTRACT_NO_UNDERFLOW(a, b) ((a)>(b) ? (a)-(b) : 0) + +/*! + * Performs a rounded right-shift of 32-bit unsigned value "a" by "shift" bits. + * Will round result away from zero. + * + * @param[in] a 32-bit unsigned value to shift. + * @param[in] shift Number of bits by which to shift. + * + * @return Resulting shifted value rounded away from zero. + */ +#define NV_RIGHT_SHIFT_ROUNDED(a, shift) \ + (((a) >> (shift)) + !!((NVBIT((shift) - 1) & (a)) == NVBIT((shift) - 1))) + +// +// Power of 2 alignment. +// (Will give unexpected results if 'gran' is not a power of 2.) +// +#ifndef NV_ALIGN_DOWN +// +// Notably using v - v + gran ensures gran gets promoted to the same type as v if gran has a smaller type. +// Otherwise, if aligning a NVU64 with NVU32 granularity, the top 4 bytes get zeroed. +// +#define NV_ALIGN_DOWN(v, gran) ((v) & ~((v) - (v) + (gran) - 1)) +#endif + +#ifndef NV_ALIGN_UP +// +// Notably using v - v + gran ensures gran gets promoted to the same type as v if gran has a smaller type. +// Otherwise, if aligning a NVU64 with NVU32 granularity, the top 4 bytes get zeroed. +// +#define NV_ALIGN_UP(v, gran) (((v) + ((gran) - 1)) & ~((v) - (v) + (gran) - 1)) +#endif + +#ifndef NV_ALIGN_DOWN64 +#define NV_ALIGN_DOWN64(v, gran) ((v) & ~(((NvU64)gran) - 1)) +#endif + +#ifndef NV_ALIGN_UP64 +#define NV_ALIGN_UP64(v, gran) (((v) + ((gran) - 1)) & ~(((NvU64)gran)-1)) +#endif + +#ifndef NV_IS_ALIGNED +#define NV_IS_ALIGNED(v, gran) (0U == ((v) & ((gran) - 1U))) +#endif + +#ifndef NV_IS_ALIGNED64 +#define NV_IS_ALIGNED64(v, gran) (0U == ((v) & (((NvU64)gran) - 1U))) +#endif + +#ifndef NVMISC_MEMSET +static NV_FORCEINLINE void *NVMISC_MEMSET(void *s, NvU8 c, NvLength n) +{ + NvU8 *b = (NvU8 *) s; + NvLength i; + + for (i = 0; i < n; i++) + { + b[i] = c; + } + + return s; +} +#endif + +#ifndef NVMISC_MEMCPY +static NV_FORCEINLINE void *NVMISC_MEMCPY(void *dest, const void *src, NvLength n) +{ + NvU8 *destByte = (NvU8 *) dest; + const NvU8 *srcByte = (const NvU8 *) src; + NvLength i; + + for (i = 0; i < n; i++) + { + destByte[i] = srcByte[i]; + } + + return dest; +} +#endif + +static NV_FORCEINLINE char *NVMISC_STRNCPY(char *dest, const char *src, NvLength n) +{ + NvLength i; + + for (i = 0; i < n; i++) + { + dest[i] = src[i]; + if (src[i] == '\0') + { + break; + } + } + + for (; i < n; i++) + { + dest[i] = '\0'; + } + + return dest; +} + +/*! + * Convert a void* to an NvUPtr. This is used when MISRA forbids us from doing a direct cast. + * + * @param[in] ptr Pointer to be converted + * + * @return Resulting NvUPtr + */ +static NV_FORCEINLINE NvUPtr NV_PTR_TO_NVUPTR(void *ptr) +{ + union + { + NvUPtr v; + void *p; + } uAddr; + + uAddr.p = ptr; + return uAddr.v; +} + +/*! + * Convert an NvUPtr to a void*. This is used when MISRA forbids us from doing a direct cast. + * + * @param[in] ptr Pointer to be converted + * + * @return Resulting void * + */ +static NV_FORCEINLINE void *NV_NVUPTR_TO_PTR(NvUPtr address) +{ + union + { + NvUPtr v; + void *p; + } uAddr; + + uAddr.v = address; + return uAddr.p; +} + +// Get bit at pos (k) from x +#define NV_BIT_GET(k, x) (((x) >> (k)) & 1) +// Get bit at pos (n) from (hi) if >= 64, otherwise from (lo). This is paired with NV_BIT_SET_128 which sets the bit. +#define NV_BIT_GET_128(n, lo, hi) (((n) < 64) ? NV_BIT_GET((n), (lo)) : NV_BIT_GET((n) - 64, (hi))) +// +// Set the bit at pos (b) for U64 which is < 128. Since the (b) can be >= 64, we need 2 U64 to store this. +// Use (lo) if (b) is less than 64, and (hi) if >= 64. +// +#define NV_BIT_SET_128(b, lo, hi) { nvAssert( (b) < 128 ); if ( (b) < 64 ) (lo) |= NVBIT64(b); else (hi) |= NVBIT64( b & 0x3F ); } + +#ifdef __cplusplus +} +#endif //__cplusplus + +#endif // __NV_MISC_H + diff --git a/userspace/sdks/nv525/nvidia/inc/nvos.h b/userspace/sdks/nv525/nvidia/inc/nvos.h new file mode 100644 index 0000000..4fb1870 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/nvos.h @@ -0,0 +1,2909 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + /***************************************************************************\ +|* *| +|* NV Architecture Interface *| +|* *| +|* defines the Operating System function and ioctl interfaces to *| +|* NVIDIA's Unified Media Architecture (TM). *| +|* *| + \***************************************************************************/ + +#ifndef NVOS_INCLUDED +#define NVOS_INCLUDED +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvstatus.h" + +#include "nvgputypes.h" +#include "rs_access.h" +#include "nvcfg_sdk.h" + + +// Temporary include. Please include this directly instead of nvos.h +#include "alloc/alloc_channel.h" + +/* local defines here */ +#define FILE_DEVICE_NV 0x00008000 +#define NV_IOCTL_FCT_BASE 0x00000800 + +// This is the maximum number of subdevices supported in an SLI +// configuration. +#define NVOS_MAX_SUBDEVICES 8 + +/* Define to indicate the use of Unified status codes - bug 200043705*/ +#define UNIFIED_NV_STATUS 1 + + /***************************************************************************\ +|* NV OS Functions *| + \***************************************************************************/ + +/* + Result codes for RM APIs, shared for all the APIs + + *** IMPORTANT *** + + Ensure that no NVOS_STATUS value has the highest bit set. That bit + is used to passthrough the NVOS_STATUS on code expecting an RM_STATUS. +*/ +#define NVOS_STATUS NV_STATUS + +#define NVOS_STATUS_SUCCESS NV_OK +#define NVOS_STATUS_ERROR_CARD_NOT_PRESENT NV_ERR_CARD_NOT_PRESENT +#define NVOS_STATUS_ERROR_DUAL_LINK_INUSE NV_ERR_DUAL_LINK_INUSE +#define NVOS_STATUS_ERROR_GENERIC NV_ERR_GENERIC +#define NVOS_STATUS_ERROR_GPU_NOT_FULL_POWER NV_ERR_GPU_NOT_FULL_POWER +#define NVOS_STATUS_ERROR_ILLEGAL_ACTION NV_ERR_ILLEGAL_ACTION +#define NVOS_STATUS_ERROR_IN_USE NV_ERR_STATE_IN_USE +#define NVOS_STATUS_ERROR_INSUFFICIENT_RESOURCES NV_ERR_INSUFFICIENT_RESOURCES +#define NVOS_STATUS_ERROR_INVALID_ACCESS_TYPE NV_ERR_INVALID_ACCESS_TYPE +#define NVOS_STATUS_ERROR_INVALID_ARGUMENT NV_ERR_INVALID_ARGUMENT +#define NVOS_STATUS_ERROR_INVALID_BASE NV_ERR_INVALID_BASE +#define NVOS_STATUS_ERROR_INVALID_CHANNEL NV_ERR_INVALID_CHANNEL +#define NVOS_STATUS_ERROR_INVALID_CLASS NV_ERR_INVALID_CLASS +#define NVOS_STATUS_ERROR_INVALID_CLIENT NV_ERR_INVALID_CLIENT +#define NVOS_STATUS_ERROR_INVALID_COMMAND NV_ERR_INVALID_COMMAND +#define NVOS_STATUS_ERROR_INVALID_DATA NV_ERR_INVALID_DATA +#define NVOS_STATUS_ERROR_INVALID_DEVICE NV_ERR_INVALID_DEVICE +#define NVOS_STATUS_ERROR_INVALID_DMA_SPECIFIER NV_ERR_INVALID_DMA_SPECIFIER +#define NVOS_STATUS_ERROR_INVALID_EVENT NV_ERR_INVALID_EVENT +#define NVOS_STATUS_ERROR_INVALID_FLAGS NV_ERR_INVALID_FLAGS +#define NVOS_STATUS_ERROR_INVALID_FUNCTION NV_ERR_INVALID_FUNCTION +#define NVOS_STATUS_ERROR_INVALID_HEAP NV_ERR_INVALID_HEAP +#define NVOS_STATUS_ERROR_INVALID_INDEX NV_ERR_INVALID_INDEX +#define NVOS_STATUS_ERROR_INVALID_LIMIT NV_ERR_INVALID_LIMIT +#define NVOS_STATUS_ERROR_INVALID_METHOD NV_ERR_INVALID_METHOD +#define NVOS_STATUS_ERROR_INVALID_OBJECT_BUFFER NV_ERR_BUFFER_TOO_SMALL +#define NVOS_STATUS_ERROR_INVALID_OBJECT_ERROR NV_ERR_INVALID_OBJECT +#define NVOS_STATUS_ERROR_INVALID_OBJECT_HANDLE NV_ERR_INVALID_OBJECT_HANDLE +#define NVOS_STATUS_ERROR_INVALID_OBJECT_NEW NV_ERR_INVALID_OBJECT_NEW +#define NVOS_STATUS_ERROR_INVALID_OBJECT_OLD NV_ERR_INVALID_OBJECT_OLD +#define NVOS_STATUS_ERROR_INVALID_OBJECT_PARENT NV_ERR_INVALID_OBJECT_PARENT +#define NVOS_STATUS_ERROR_INVALID_OFFSET NV_ERR_INVALID_OFFSET +#define NVOS_STATUS_ERROR_INVALID_OWNER NV_ERR_INVALID_OWNER +#define NVOS_STATUS_ERROR_INVALID_PARAM_STRUCT NV_ERR_INVALID_PARAM_STRUCT +#define NVOS_STATUS_ERROR_INVALID_PARAMETER NV_ERR_INVALID_PARAMETER +#define NVOS_STATUS_ERROR_INVALID_POINTER NV_ERR_INVALID_POINTER +#define NVOS_STATUS_ERROR_INVALID_REGISTRY_KEY NV_ERR_INVALID_REGISTRY_KEY +#define NVOS_STATUS_ERROR_INVALID_STATE NV_ERR_INVALID_STATE +#define NVOS_STATUS_ERROR_INVALID_STRING_LENGTH NV_ERR_INVALID_STRING_LENGTH +#define NVOS_STATUS_ERROR_INVALID_XLATE NV_ERR_INVALID_XLATE +#define NVOS_STATUS_ERROR_IRQ_NOT_FIRING NV_ERR_IRQ_NOT_FIRING +#define NVOS_STATUS_ERROR_MULTIPLE_MEMORY_TYPES NV_ERR_MULTIPLE_MEMORY_TYPES +#define NVOS_STATUS_ERROR_NOT_SUPPORTED NV_ERR_NOT_SUPPORTED +#define NVOS_STATUS_ERROR_OPERATING_SYSTEM NV_ERR_OPERATING_SYSTEM +#define NVOS_STATUS_ERROR_LIB_RM_VERSION_MISMATCH NV_ERR_LIB_RM_VERSION_MISMATCH +#define NVOS_STATUS_ERROR_PROTECTION_FAULT NV_ERR_PROTECTION_FAULT +#define NVOS_STATUS_ERROR_TIMEOUT NV_ERR_TIMEOUT +#define NVOS_STATUS_ERROR_TOO_MANY_PRIMARIES NV_ERR_TOO_MANY_PRIMARIES +#define NVOS_STATUS_ERROR_IRQ_EDGE_TRIGGERED NV_ERR_IRQ_EDGE_TRIGGERED +#define NVOS_STATUS_ERROR_INVALID_OPERATION NV_ERR_INVALID_OPERATION +#define NVOS_STATUS_ERROR_NOT_COMPATIBLE NV_ERR_NOT_COMPATIBLE +#define NVOS_STATUS_ERROR_MORE_PROCESSING_REQUIRED NV_WARN_MORE_PROCESSING_REQUIRED +#define NVOS_STATUS_ERROR_INSUFFICIENT_PERMISSIONS NV_ERR_INSUFFICIENT_PERMISSIONS +#define NVOS_STATUS_ERROR_TIMEOUT_RETRY NV_ERR_TIMEOUT_RETRY +#define NVOS_STATUS_ERROR_NOT_READY NV_ERR_NOT_READY +#define NVOS_STATUS_ERROR_GPU_IS_LOST NV_ERR_GPU_IS_LOST +#define NVOS_STATUS_ERROR_IN_FULLCHIP_RESET NV_ERR_GPU_IN_FULLCHIP_RESET +#define NVOS_STATUS_ERROR_INVALID_LOCK_STATE NV_ERR_INVALID_LOCK_STATE +#define NVOS_STATUS_ERROR_INVALID_ADDRESS NV_ERR_INVALID_ADDRESS +#define NVOS_STATUS_ERROR_INVALID_IRQ_LEVEL NV_ERR_INVALID_IRQ_LEVEL +#define NVOS_STATUS_ERROR_MEMORY_TRAINING_FAILED NV_ERR_MEMORY_TRAINING_FAILED +#define NVOS_STATUS_ERROR_BUSY_RETRY NV_ERR_BUSY_RETRY +#define NVOS_STATUS_ERROR_INSUFFICIENT_POWER NV_ERR_INSUFFICIENT_POWER +#define NVOS_STATUS_ERROR_OBJECT_NOT_FOUND NV_ERR_OBJECT_NOT_FOUND +#define NVOS_STATUS_ERROR_RESOURCE_LOST NV_ERR_RESOURCE_LOST +#define NVOS_STATUS_ERROR_BUFFER_TOO_SMALL NV_ERR_BUFFER_TOO_SMALL +#define NVOS_STATUS_ERROR_RESET_REQUIRED NV_ERR_RESET_REQUIRED +#define NVOS_STATUS_ERROR_INVALID_REQUEST NV_ERR_INVALID_REQUEST + +#define NVOS_STATUS_ERROR_PRIV_SEC_VIOLATION NV_ERR_PRIV_SEC_VIOLATION +#define NVOS_STATUS_ERROR_GPU_IN_DEBUG_MODE NV_ERR_GPU_IN_DEBUG_MODE + +/* + Note: + This version of the architecture has been changed to allow the + RM to return a client handle that will subsequently used to + identify the client. NvAllocRoot() returns the handle. All + other functions must specify this client handle. + +*/ +/* macro NV01_FREE */ +#define NV01_FREE (0x00000000) + +/* NT ioctl data structure */ +typedef struct +{ + NvHandle hRoot; + NvHandle hObjectParent; + NvHandle hObjectOld; + NvV32 status; +} NVOS00_PARAMETERS; + +/* valid hClass values. */ +#define NV01_ROOT (0x0U) +// +// Redefining it here to maintain consistency with current code +// This is also defined in class cl0001.h +// +#define NV01_ROOT_NON_PRIV (0x00000001) + +// Deprecated, please use NV01_ROOT_CLIENT +#define NV01_ROOT_USER NV01_ROOT_CLIENT + +// +// This will eventually replace NV01_ROOT_USER in RM client code. Please use this +// RM client object type for any new RM client object allocations that are being +// added. +// +#define NV01_ROOT_CLIENT (0x00000041) + +/* macro NV01_ALLOC_MEMORY */ +#define NV01_ALLOC_MEMORY (0x00000002) + +/* parameter values */ +#define NVOS02_FLAGS_PHYSICALITY 7:4 +#define NVOS02_FLAGS_PHYSICALITY_CONTIGUOUS (0x00000000) +#define NVOS02_FLAGS_PHYSICALITY_NONCONTIGUOUS (0x00000001) +#define NVOS02_FLAGS_LOCATION 11:8 +#define NVOS02_FLAGS_LOCATION_PCI (0x00000000) +#define NVOS02_FLAGS_LOCATION_AGP (0x00000001) +#define NVOS02_FLAGS_LOCATION_VIDMEM (0x00000002) +#define NVOS02_FLAGS_COHERENCY 15:12 +#define NVOS02_FLAGS_COHERENCY_UNCACHED (0x00000000) +#define NVOS02_FLAGS_COHERENCY_CACHED (0x00000001) +#define NVOS02_FLAGS_COHERENCY_WRITE_COMBINE (0x00000002) +#define NVOS02_FLAGS_COHERENCY_WRITE_THROUGH (0x00000003) +#define NVOS02_FLAGS_COHERENCY_WRITE_PROTECT (0x00000004) +#define NVOS02_FLAGS_COHERENCY_WRITE_BACK (0x00000005) +#define NVOS02_FLAGS_ALLOC 17:16 +#define NVOS02_FLAGS_ALLOC_NONE (0x00000001) +#define NVOS02_FLAGS_GPU_CACHEABLE 18:18 +#define NVOS02_FLAGS_GPU_CACHEABLE_NO (0x00000000) +#define NVOS02_FLAGS_GPU_CACHEABLE_YES (0x00000001) +// If requested, RM will create a kernel mapping of this memory. +// Default is no map. +#define NVOS02_FLAGS_KERNEL_MAPPING 19:19 +#define NVOS02_FLAGS_KERNEL_MAPPING_NO_MAP (0x00000000) +#define NVOS02_FLAGS_KERNEL_MAPPING_MAP (0x00000001) +#define NVOS02_FLAGS_ALLOC_NISO_DISPLAY 20:20 +#define NVOS02_FLAGS_ALLOC_NISO_DISPLAY_NO (0x00000000) +#define NVOS02_FLAGS_ALLOC_NISO_DISPLAY_YES (0x00000001) + +// +// If the flag is set, the RM will only allow read-only CPU user mappings to the +// allocation. +// +#define NVOS02_FLAGS_ALLOC_USER_READ_ONLY 21:21 +#define NVOS02_FLAGS_ALLOC_USER_READ_ONLY_NO (0x00000000) +#define NVOS02_FLAGS_ALLOC_USER_READ_ONLY_YES (0x00000001) + +// +// If the flag is set, the RM will only allow read-only DMA mappings to the +// allocation. +// +#define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY 22:22 +#define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_NO (0x00000000) +#define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_YES (0x00000001) + +// +// If the flag is set, the IO memory allocation can be registered with the RM if +// the RM regkey peerMappingOverride is set or the client is privileged. +// +// See Bug 1630288 "[PeerSync] threat related to GPU.." for more details. +// +#define NVOS02_FLAGS_PEER_MAP_OVERRIDE 23:23 +#define NVOS02_FLAGS_PEER_MAP_OVERRIDE_DEFAULT (0x00000000) +#define NVOS02_FLAGS_PEER_MAP_OVERRIDE_REQUIRED (0x00000001) + +// If the flag is set RM will assume the memory pages are of type syncpoint. +#define NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT 24:24 +#define NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT_APERTURE (0x00000001) + +// +// If _NO_MAP is requested, the RM in supported platforms will not map the +// allocated system or IO memory into user space. The client can later map +// memory through the RmMapMemory() interface. +// If _NEVER_MAP is requested, the RM will never map the allocated system or +// IO memory into user space +// +#define NVOS02_FLAGS_MAPPING 31:30 +#define NVOS02_FLAGS_MAPPING_DEFAULT (0x00000000) +#define NVOS02_FLAGS_MAPPING_NO_MAP (0x00000001) +#define NVOS02_FLAGS_MAPPING_NEVER_MAP (0x00000002) + +// ------------------------------------------------------------------------------------- + +/* parameters */ +typedef struct +{ + NvHandle hRoot; + NvHandle hObjectParent; + NvHandle hObjectNew; + NvV32 hClass; + NvV32 flags; + NvP64 pMemory NV_ALIGN_BYTES(8); + NvU64 limit NV_ALIGN_BYTES(8); + NvV32 status; +} NVOS02_PARAMETERS; + +/* parameter values */ +#define NVOS03_FLAGS_ACCESS 1:0 +#define NVOS03_FLAGS_ACCESS_READ_WRITE (0x00000000) +#define NVOS03_FLAGS_ACCESS_READ_ONLY (0x00000001) +#define NVOS03_FLAGS_ACCESS_WRITE_ONLY (0x00000002) + +#define NVOS03_FLAGS_PREALLOCATE 2:2 +#define NVOS03_FLAGS_PREALLOCATE_DISABLE (0x00000000) +#define NVOS03_FLAGS_PREALLOCATE_ENABLE (0x00000001) + +#define NVOS03_FLAGS_GPU_MAPPABLE 15:15 +#define NVOS03_FLAGS_GPU_MAPPABLE_DISABLE (0x00000000) +#define NVOS03_FLAGS_GPU_MAPPABLE_ENABLE (0x00000001) + +// ------------------------------------------------------------------------------------ +// This flag is required for a hack to be placed inside DD that allows it to +// access a dummy ctxdma as a block linear surface. Refer bug 1562766 for details. +// +// This flag is deprecated, use NVOS03_FLAGS_PTE_KIND. +// +#define NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE 16:16 +#define NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE_FALSE (0x00000000) +#define NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE_TRUE (0x00000001) + +/* + * This field allows to specify the page kind. If the page kind + * is not specified then the page kind associated with the memory will be used. + * + * In tegra display driver stack, the page kind remains unknown at the time + * of memory allocation/import, the page kind can only be known when display + * driver client creates a framebuffer from allocated/imported memory. + * + * This field compatible with NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE flag. + */ +#define NVOS03_FLAGS_PTE_KIND 17:16 +#define NVOS03_FLAGS_PTE_KIND_NONE (0x00000000) +#define NVOS03_FLAGS_PTE_KIND_BL (0x00000001) +#define NVOS03_FLAGS_PTE_KIND_PITCH (0x00000002) + +#define NVOS03_FLAGS_TYPE 23:20 +#define NVOS03_FLAGS_TYPE_NOTIFIER (0x00000001) + +/* + * This is an alias into the LSB of the TYPE field which + * actually indicates if a Kernel Mapping should be created. + * If the RM should have access to the memory then Enable this + * flag. + * + * Note that the NV_OS03_FLAGS_MAPPING is an alias to + * the LSB of the NV_OS03_FLAGS_TYPE. And in fact if + * type is NV_OS03_FLAGS_TYPE_NOTIFIER (bit 20 set) + * then it implicitly means that NV_OS03_FLAGS_MAPPING + * is _MAPPING_KERNEL. If the client wants to have a + * Kernel Mapping, it should use the _MAPPING_KERNEL + * flag set and the _TYPE_NOTIFIER should be used only + * with NOTIFIERS. + */ + +#define NVOS03_FLAGS_MAPPING 20:20 +#define NVOS03_FLAGS_MAPPING_NONE (0x00000000) +#define NVOS03_FLAGS_MAPPING_KERNEL (0x00000001) + +#define NVOS03_FLAGS_CACHE_SNOOP 28:28 +#define NVOS03_FLAGS_CACHE_SNOOP_ENABLE (0x00000000) +#define NVOS03_FLAGS_CACHE_SNOOP_DISABLE (0x00000001) + +// HASH_TABLE:ENABLE means that the context DMA is automatically bound into all +// channels in the client. This can lead to excessive hash table usage. +// HASH_TABLE:DISABLE means that the context DMA must be explicitly bound into +// any channel that needs to use it via NvRmBindContextDma. +// HASH_TABLE:ENABLE is not supported on NV50 and up, and HASH_TABLE:DISABLE should +// be preferred for all new code. +#define NVOS03_FLAGS_HASH_TABLE 29:29 +#define NVOS03_FLAGS_HASH_TABLE_ENABLE (0x00000000) +#define NVOS03_FLAGS_HASH_TABLE_DISABLE (0x00000001) + +/* macro NV01_ALLOC_OBJECT */ +#define NV01_ALLOC_OBJECT (0x00000005) + +/* parameters */ +typedef struct +{ + NvHandle hRoot; + NvHandle hObjectParent; + NvHandle hObjectNew; + NvV32 hClass; + NvV32 status; +} NVOS05_PARAMETERS; + +/* Valid values for hClass in Nv01AllocEvent */ +/* Note that NV01_EVENT_OS_EVENT is same as NV01_EVENT_WIN32_EVENT */ +/* TODO: delete the WIN32 name */ +#define NV01_EVENT_KERNEL_CALLBACK (0x00000078) +#define NV01_EVENT_OS_EVENT (0x00000079) +#define NV01_EVENT_WIN32_EVENT NV01_EVENT_OS_EVENT +#define NV01_EVENT_KERNEL_CALLBACK_EX (0x0000007E) + +/* NOTE: NV01_EVENT_KERNEL_CALLBACK is deprecated. Please use NV01_EVENT_KERNEL_CALLBACK_EX. */ +/* For use with NV01_EVENT_KERNEL_CALLBACK. */ +/* NVOS10_EVENT_KERNEL_CALLBACK data structure storage needs to be retained by the caller. */ +typedef void (*Callback1ArgVoidReturn)(void *arg); +typedef void (*Callback5ArgVoidReturn)(void *arg1, void *arg2, NvHandle hEvent, NvU32 data, NvU32 status); + +/* NOTE: the 'void* arg' below is ok (but unfortunate) since this interface + can only be used by other kernel drivers which must share the same ptr-size */ +typedef struct +{ + Callback1ArgVoidReturn func; + void *arg; +} NVOS10_EVENT_KERNEL_CALLBACK; + +/* For use with NV01_EVENT_KERNEL_CALLBACK_EX. */ +/* NVOS10_EVENT_KERNEL_CALLBACK_EX data structure storage needs to be retained by the caller. */ +/* NOTE: the 'void* arg' below is ok (but unfortunate) since this interface + can only be used by other kernel drivers which must share the same ptr-size */ +typedef struct +{ + Callback5ArgVoidReturn func; + void *arg; +} NVOS10_EVENT_KERNEL_CALLBACK_EX; + +/* Setting this bit in index will set the Event to a Broadcast type */ +/* i.e. each subdevice under a device needs to see the Event before it's signaled */ +#define NV01_EVENT_BROADCAST (0x80000000) + +/* allow non-root resman client to create NV01_EVENT_KERNEL_CALLBACK events */ +/* -- this works in debug/develop drivers only (for security reasons)*/ +#define NV01_EVENT_PERMIT_NON_ROOT_EVENT_KERNEL_CALLBACK_CREATION (0x40000000) + +/* RM event should be triggered only by the specified subdevice; see cl0005.h + * for details re: how to specify subdevice. */ +#define NV01_EVENT_SUBDEVICE_SPECIFIC (0x20000000) + +/* RM should trigger the event but shouldn't do the book-keeping of data + * associated with that event */ +#define NV01_EVENT_WITHOUT_EVENT_DATA (0x10000000) + +/* RM event should be triggered only by the non-stall interrupt */ +#define NV01_EVENT_NONSTALL_INTR (0x08000000) + +/* RM event was allocated from client RM, post events back to client RM */ +#define NV01_EVENT_CLIENT_RM (0x04000000) + +/* function OS19 */ +#define NV04_I2C_ACCESS (0x00000013) + +#define NVOS_I2C_ACCESS_MAX_BUFFER_SIZE 2048 + +/* parameters */ +typedef struct +{ + NvHandle hClient; + NvHandle hDevice; + NvU32 paramSize; + NvP64 paramStructPtr NV_ALIGN_BYTES(8); + NvV32 status; +} NVOS_I2C_ACCESS_PARAMS; + +/* current values for command */ +#define NVOS20_COMMAND_unused0001 0x0001 +#define NVOS20_COMMAND_unused0002 0x0002 +#define NVOS20_COMMAND_STRING_PRINT 0x0003 + +/* function OS21 */ +#define NV04_ALLOC (0x00000015) + +/* parameters */ +typedef struct +{ + NvHandle hRoot; + NvHandle hObjectParent; + NvHandle hObjectNew; + NvV32 hClass; + NvP64 pAllocParms NV_ALIGN_BYTES(8); + NvV32 status; +} NVOS21_PARAMETERS; + +#define NVOS64_FLAGS_NONE (0x00000000) +#define NVOS64_FLAGS_FINN_SERIALIZED (0x00000001) + +/* New struct with rights requested */ +typedef struct +{ + NvHandle hRoot; // [IN] client handle + NvHandle hObjectParent; // [IN] parent handle of new object + NvHandle hObjectNew; // [INOUT] new object handle, 0 to generate + NvV32 hClass; // [in] class num of new object + NvP64 pAllocParms NV_ALIGN_BYTES(8); // [IN] class-specific alloc parameters + NvP64 pRightsRequested NV_ALIGN_BYTES(8); // [IN] RS_ACCESS_MASK to request rights, or NULL + NvU32 flags; // [IN] flags for FINN serialization + NvV32 status; // [OUT] status +} NVOS64_PARAMETERS; + +/* RM Alloc header + * + * Replacement for NVOS21/64_PARAMETERS where embedded pointers are not allowed. + * Input layout for RM Alloc user space calls should be + * + * +--- NVOS62_PARAMETERS ---+--- RM Alloc parameters ---+ + * +--- NVOS65_PARAMETERS ---+--- Rights Requested ---+--- RM Alloc parameters ---+ + * + * NVOS62_PARAMETERS::paramsSize is the size of RM Alloc parameters + * If NVOS65_PARAMETERS::maskSize is 0, Rights Requested will not be present in memory. + * + */ +typedef struct +{ + NvHandle hRoot; // [IN] client handle + NvHandle hObjectParent; // [IN] parent handle of the new object + NvHandle hObjectNew; // [IN] new object handle + NvV32 hClass; // [IN] class num of the new object + NvU32 paramSize; // [IN] size in bytes of the RM alloc parameters + NvV32 status; // [OUT] status +} NVOS62_PARAMETERS; + +#define NVOS65_PARAMETERS_VERSION_MAGIC 0x77FEF81E + +typedef struct +{ + NvHandle hRoot; // [IN] client handle + NvHandle hObjectParent; // [IN] parent handle of the new object + NvHandle hObjectNew; // [INOUT] new object handle, 0 to generate + NvV32 hClass; // [IN] class num of the new object + NvU32 paramSize; // [IN] size in bytes of the RM alloc parameters + NvU32 versionMagic; // [IN] NVOS65_PARAMETERS_VERISON_MAGIC + NvU32 maskSize; // [IN] size in bytes of access mask, or 0 if NULL + NvV32 status; // [OUT] status +} NVOS65_PARAMETERS; + +/* function OS30 */ +#define NV04_IDLE_CHANNELS (0x0000001E) + +/* parameter values */ +#define NVOS30_FLAGS_BEHAVIOR 3:0 +#define NVOS30_FLAGS_BEHAVIOR_SPIN (0x00000000) +#define NVOS30_FLAGS_BEHAVIOR_SLEEP (0x00000001) +#define NVOS30_FLAGS_BEHAVIOR_QUERY (0x00000002) +#define NVOS30_FLAGS_BEHAVIOR_FORCE_BUSY_CHECK (0x00000003) +#define NVOS30_FLAGS_CHANNEL 7:4 +#define NVOS30_FLAGS_CHANNEL_LIST (0x00000000) +#define NVOS30_FLAGS_CHANNEL_SINGLE (0x00000001) +#define NVOS30_FLAGS_IDLE 30:8 +#define NVOS30_FLAGS_IDLE_PUSH_BUFFER (0x00000001) +#define NVOS30_FLAGS_IDLE_CACHE1 (0x00000002) +#define NVOS30_FLAGS_IDLE_GRAPHICS (0x00000004) +#define NVOS30_FLAGS_IDLE_MPEG (0x00000008) +#define NVOS30_FLAGS_IDLE_MOTION_ESTIMATION (0x00000010) +#define NVOS30_FLAGS_IDLE_VIDEO_PROCESSOR (0x00000020) +#define NVOS30_FLAGS_IDLE_MSPDEC (0x00000020) +#define NVOS30_FLAGS_IDLE_BITSTREAM_PROCESSOR (0x00000040) +#define NVOS30_FLAGS_IDLE_MSVLD (0x00000040) +#define NVOS30_FLAGS_IDLE_NVDEC0 NVOS30_FLAGS_IDLE_MSVLD +#define NVOS30_FLAGS_IDLE_CIPHER_DMA (0x00000080) +#define NVOS30_FLAGS_IDLE_SEC (0x00000080) +#define NVOS30_FLAGS_IDLE_CALLBACKS (0x00000100) +#define NVOS30_FLAGS_IDLE_MSPPP (0x00000200) +#define NVOS30_FLAGS_IDLE_CE0 (0x00000400) +#define NVOS30_FLAGS_IDLE_CE1 (0x00000800) +#define NVOS30_FLAGS_IDLE_CE2 (0x00001000) +#define NVOS30_FLAGS_IDLE_CE3 (0x00002000) +#define NVOS30_FLAGS_IDLE_CE4 (0x00004000) +#define NVOS30_FLAGS_IDLE_CE5 (0x00008000) +#define NVOS30_FLAGS_IDLE_VIC (0x00010000) +#define NVOS30_FLAGS_IDLE_MSENC (0x00020000) +#define NVOS30_FLAGS_IDLE_NVENC0 NVOS30_FLAGS_IDLE_MSENC +#define NVOS30_FLAGS_IDLE_NVENC1 (0x00040000) +#define NVOS30_FLAGS_IDLE_NVENC2 (0x00080000) +#define NVOS30_FLAGS_IDLE_NVJPG (0x00100000) +#define NVOS30_FLAGS_IDLE_NVDEC1 (0x00200000) +#define NVOS30_FLAGS_IDLE_NVDEC2 (0x00400000) +#define NVOS30_FLAGS_IDLE_ACTIVECHANNELS (0x00800000) +#define NVOS30_FLAGS_IDLE_ALL_ENGINES (NVOS30_FLAGS_IDLE_GRAPHICS | \ + NVOS30_FLAGS_IDLE_MPEG | \ + NVOS30_FLAGS_IDLE_MOTION_ESTIMATION | \ + NVOS30_FLAGS_IDLE_VIDEO_PROCESSOR | \ + NVOS30_FLAGS_IDLE_BITSTREAM_PROCESSOR | \ + NVOS30_FLAGS_IDLE_CIPHER_DMA | \ + NVOS30_FLAGS_IDLE_MSPDEC | \ + NVOS30_FLAGS_IDLE_NVDEC0 | \ + NVOS30_FLAGS_IDLE_SEC | \ + NVOS30_FLAGS_IDLE_MSPPP | \ + NVOS30_FLAGS_IDLE_CE0 | \ + NVOS30_FLAGS_IDLE_CE1 | \ + NVOS30_FLAGS_IDLE_CE2 | \ + NVOS30_FLAGS_IDLE_CE3 | \ + NVOS30_FLAGS_IDLE_CE4 | \ + NVOS30_FLAGS_IDLE_CE5 | \ + NVOS30_FLAGS_IDLE_NVENC0 | \ + NVOS30_FLAGS_IDLE_NVENC1 | \ + NVOS30_FLAGS_IDLE_NVENC2 | \ + NVOS30_FLAGS_IDLE_VIC | \ + NVOS30_FLAGS_IDLE_NVJPG | \ + NVOS30_FLAGS_IDLE_NVDEC1 | \ + NVOS30_FLAGS_IDLE_NVDEC2) +#define NVOS30_FLAGS_WAIT_FOR_ELPG_ON 31:31 +#define NVOS30_FLAGS_WAIT_FOR_ELPG_ON_NO (0x00000000) +#define NVOS30_FLAGS_WAIT_FOR_ELPG_ON_YES (0x00000001) + +/* parameters */ +typedef struct +{ + NvHandle hClient; + NvHandle hDevice; + NvHandle hChannel; + NvV32 numChannels; + + NvP64 phClients NV_ALIGN_BYTES(8); + NvP64 phDevices NV_ALIGN_BYTES(8); + NvP64 phChannels NV_ALIGN_BYTES(8); + + NvV32 flags; + NvV32 timeout; + NvV32 status; +} NVOS30_PARAMETERS; + +/* function OS32 */ +typedef void (*BindResultFunc)(void * pVoid, NvU32 gpuMask, NvU32 bState, NvU32 bResult); + +#define NV04_VID_HEAP_CONTROL (0x00000020) +/************************************************************************* +************************ New Heap Interface ****************************** +*************************************************************************/ +// NVOS32 Descriptor types +// +// NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR: The dma-buf object +// pointer, provided by the linux kernel buffer sharing sub-system. +// This descriptor can only be used by kernel space rm-clients. +// +#define NVOS32_DESCRIPTOR_TYPE_VIRTUAL_ADDRESS 0 +#define NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY 1 +#define NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY 2 +#define NVOS32_DESCRIPTOR_TYPE_OS_PHYS_ADDR 3 +#define NVOS32_DESCRIPTOR_TYPE_OS_FILE_HANDLE 4 +#define NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR 5 +#define NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR 6 +#define NVOS32_DESCRIPTOR_TYPE_KERNEL_VIRTUAL_ADDRESS 7 +// NVOS32 function +#define NVOS32_FUNCTION_ALLOC_DEPTH_WIDTH_HEIGHT 1 +#define NVOS32_FUNCTION_ALLOC_SIZE 2 +#define NVOS32_FUNCTION_FREE 3 +// #define NVOS32_FUNCTION_HEAP_PURGE 4 +#define NVOS32_FUNCTION_INFO 5 +#define NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT 6 +// #define NVOS32_FUNCTION_DESTROY 7 +// #define NVOS32_FUNCTION_RETAIN 9 +// #define NVOS32_FUNCTION_REALLOC 10 +#define NVOS32_FUNCTION_DUMP 11 +// #define NVOS32_FUNCTION_INFO_TYPE_ALLOC_BLOCKS 12 +#define NVOS32_FUNCTION_ALLOC_SIZE_RANGE 14 +#define NVOS32_FUNCTION_REACQUIRE_COMPR 15 +#define NVOS32_FUNCTION_RELEASE_COMPR 16 +// #define NVOS32_FUNCTION_MODIFY_DEFERRED_TILES 17 +#define NVOS32_FUNCTION_GET_MEM_ALIGNMENT 18 +#define NVOS32_FUNCTION_HW_ALLOC 19 +#define NVOS32_FUNCTION_HW_FREE 20 +// #define NVOS32_FUNCTION_SET_OFFSET 21 +// #define NVOS32_FUNCTION_IS_TILED 22 +// #define NVOS32_FUNCTION_ENABLE_RESOURCE 23 +// #define NVOS32_FUNCTION_BIND_COMPR 24 +#define NVOS32_FUNCTION_ALLOC_OS_DESCRIPTOR 27 + +typedef struct +{ + NvP64 sgt NV_ALIGN_BYTES(8); + NvP64 gem NV_ALIGN_BYTES(8); +} NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS; + +#define NVOS32_FLAGS_BLOCKINFO_VISIBILITY_CPU (0x00000001) +typedef struct +{ + NvU64 startOffset NV_ALIGN_BYTES(8); + NvU64 size NV_ALIGN_BYTES(8); + NvU32 flags; +} NVOS32_BLOCKINFO; + +// NVOS32 IVC-heap number delimiting value +#define NVOS32_IVC_HEAP_NUMBER_DONT_ALLOCATE_ON_IVC_HEAP 0 // When IVC heaps are present, + // IVC-heap number specified + // as part of 'NVOS32_PARAMETERS' + // which is less or equal to this + // constant indicates that allocation + // should not be done on IVC heap. + // Explanation of IVC-heap number is + // under 'AllocSize' structure below. + +typedef struct +{ + NvHandle hRoot; // [IN] - root object handle + NvHandle hObjectParent; // [IN] - device handle + NvU32 function; // [IN] - heap function, see below FUNCTION* defines + NvHandle hVASpace; // [IN] - VASpace handle + NvS16 ivcHeapNumber; // [IN] - When IVC heaps are present: either 1) number of the IVC heap + // shared between two VMs or 2) number indicating that allocation + // should not be done on an IVC heap. Values greater than constant + // 'NVOS32_IVC_HEAP_NUMBER_DONT_ALLOCATE_ON_IVC_HEAP' define set 1) + // and values less or equal to that constant define set 2). + // When IVC heaps are present, correct IVC-heap number must be specified. + // When IVC heaps are absent, IVC-heap number is diregarded. + // RM provides for each VM a bitmask of heaps with each bit + // specifying the other peer that can use the partition. + // Each bit set to one can be enumerated, such that the bit + // with lowest significance is enumerated with one. + // 'ivcHeapNumber' parameter specifies this enumeration value. + // This value is used to uniquely identify a heap shared between + // two particular VMs. + // Illustration: + // bitmask: 1 1 0 1 0 = 0x1A + // possible 'ivcHeapNumber' values: 3, 2, 1 + NvV32 status; // [OUT] - returned NVOS32* status code, see below STATUS* defines + NvU64 total NV_ALIGN_BYTES(8); // [OUT] - returned total size of heap + NvU64 free NV_ALIGN_BYTES(8); // [OUT] - returned free space available in heap + + union + { + // NVOS32_FUNCTION_ALLOC_DEPTH_WIDTH_HEIGHT + struct + { + NvU32 owner; // [IN] - memory owner ID + NvHandle hMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated) + NvU32 type; // [IN] - surface type, see below TYPE* defines + NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines + NvU32 depth; // [IN] - depth of surface in bits + NvU32 width; // [IN] - width of surface in pixels + NvU32 height; // [IN] - height of surface in pixels + NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 format; // [IN/OUT] - format requested, and format allocated + NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated + NvU32 zcullCovg; // [OUT] - zcull covg allocated + NvU32 partitionStride; // [IN/OUT] - 0 means "RM" chooses + NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated + NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on + NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset + NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit + NvP64 address NV_ALIGN_BYTES(8);// [OUT] - returned address + NvU64 rangeBegin NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range + NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive. + NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET) + } AllocDepthWidthHeight; + + // NVOS32_FUNCTION_ALLOC_SIZE + struct + { + NvU32 owner; // [IN] - memory owner ID + NvHandle hMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated) + NvU32 type; // [IN] - surface type, see below TYPE* defines + NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines + NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 format; // [IN/OUT] - format requested, and format allocated + NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated + NvU32 zcullCovg; // [OUT] - zcull covg allocated + NvU32 partitionStride; // [IN/OUT] - 0 means "RM" chooses + NvU32 width; // [IN] - width "hint" used for zcull region allocations + NvU32 height; // [IN] - height "hint" used for zcull region allocations + NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated + NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on + NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset + NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit + NvP64 address NV_ALIGN_BYTES(8);// [OUT] - returned address + NvU64 rangeBegin NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range + NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive. + NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET) + } AllocSize; + + // NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT + struct + { + NvU32 owner; // [IN] - memory owner ID + NvHandle hMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated) + NvU32 type; // [IN] - surface type, see below TYPE* defines + NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines + NvU32 height; // [IN] - height of surface in pixels + NvS32 pitch; // [IN/OUT] - desired pitch AND returned actual pitch allocated + NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 width; //[IN] - width of surface in pixels + NvU32 format; // [IN/OUT] - format requested, and format allocated + NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated + NvU32 zcullCovg; // [OUT] - zcull covg allocated + NvU32 partitionStride; // [IN/OUT] - 0 means "RM" chooses + NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated + NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on + NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset + NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit + NvP64 address NV_ALIGN_BYTES(8);// [OUT] - returned address + NvU64 rangeBegin NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range + NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive. + NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET) + } AllocTiledPitchHeight; + + // NVOS32_FUNCTION_FREE + struct + { + NvU32 owner; // [IN] - memory owner ID + NvHandle hMemory; // [IN] - unique memory handle + NvU32 flags; // [IN] - heap free flags (must be NVOS32_FREE_FLAGS_MEMORY_HANDLE_PROVIDED) + } Free; + + // NVOS32_FUNCTION_RELEASE_COMPR + struct + { + NvU32 owner; // [IN] - memory owner ID + NvU32 flags; // [IN] - must be NVOS32_RELEASE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED + NvHandle hMemory; // [IN] - unique memory handle (valid if _RELEASE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED + } ReleaseCompr; + + // NVOS32_FUNCTION_REACQUIRE_COMPR + struct + { + NvU32 owner; // [IN] - memory owner ID + NvU32 flags; // [IN] - must be NVOS32_REACQUIRE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED + NvHandle hMemory; // [IN] - unique memory handle (valid if _REACQUIRE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED + } ReacquireCompr; + + // NVOS32_FUNCTION_INFO + struct + { + NvU32 attr; // [IN] - memory heap attributes requested + NvU64 offset NV_ALIGN_BYTES(8); // [OUT] - base of largest free block + NvU64 size NV_ALIGN_BYTES(8); // [OUT] - size of largest free block + NvU64 base NV_ALIGN_BYTES(8); // [OUT] - returned heap phys base + } Info; + + // NVOS32_FUNCTION_DUMP + struct + { + NvU32 flags; // [IN] - see _DUMP_FLAGS + // [IN] - if NULL, numBlocks is the returned number of blocks in + // heap, else returns all blocks in eHeap + // if non-NULL points to a buffer that is at least numBlocks + // * sizeof(NVOS32_HEAP_DUMP_BLOCK) bytes. + NvP64 pBuffer NV_ALIGN_BYTES(8); + // [IN/OUT] - if pBuffer is NULL, will number of blocks in heap + // if pBuffer is non-NULL, is input containing the size of + // pBuffer in units of NVOS32_HEAP_DUMP_BLOCK. This must + // be greater than or equal to the number of blocks in the + // heap. + NvU32 numBlocks; + } Dump; + + // NVOS32_FUNCTION_DESTROY - no extra parameters needed + + // NVOS32_FUNCTION_ALLOC_SIZE_RANGE + struct + { + NvU32 owner; // [IN] - memory owner ID + NvHandle hMemory; // [IN] - unique memory handle + NvU32 type; // [IN] - surface type, see below TYPE* defines + NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines + NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 format; // [IN/OUT] - format requested, and format allocated + NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated + NvU32 zcullCovg; // [OUT] - zcull covg allocated + NvU32 partitionStride; // [IN/OUT] - 0 means "RM" chooses + NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated + NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on + NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset + NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit + NvU64 rangeBegin NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range + NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive. + NvP64 address NV_ALIGN_BYTES(8);// [OUT] - returned address + NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET) + } AllocSizeRange; + + // additions for Longhorn +#define NVAL_MAX_BANKS (4) +#define NVAL_MAP_DIRECTION 0:0 +#define NVAL_MAP_DIRECTION_DOWN 0x00000000 +#define NVAL_MAP_DIRECTION_UP 0x00000001 + + // NVOS32_FUNCTION_GET_MEM_ALIGNMENT + struct + { + NvU32 alignType; // Input + NvU32 alignAttr; + NvU32 alignInputFlags; + NvU64 alignSize NV_ALIGN_BYTES(8); + NvU32 alignHeight; + NvU32 alignWidth; + NvU32 alignPitch; + NvU32 alignPad; + NvU32 alignMask; + NvU32 alignOutputFlags[NVAL_MAX_BANKS]; // We could compress this information but it is probably not that big of a deal + NvU32 alignBank[NVAL_MAX_BANKS]; + NvU32 alignKind; + NvU32 alignAdjust; // Output -- If non-zero the amount we need to adjust the offset + NvU32 alignAttr2; + } AllocHintAlignment; + + struct + { + NvU32 allocOwner; // [IN] - memory owner ID + NvHandle allochMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated) + NvU32 flags; + NvU32 allocType; // Input + NvU32 allocAttr; + NvU32 allocInputFlags; + NvU64 allocSize NV_ALIGN_BYTES(8); + NvU32 allocHeight; + NvU32 allocWidth; + NvU32 allocPitch; + NvU32 allocMask; + NvU32 allocComprCovg; + NvU32 allocZcullCovg; + NvP64 bindResultFunc NV_ALIGN_BYTES(8); // BindResultFunc + NvP64 pHandle NV_ALIGN_BYTES(8); + NvHandle hResourceHandle; // Handle to RM container + NvU32 retAttr; // Output Indicates the resources that we allocated + NvU32 kind; + NvU64 osDeviceHandle NV_ALIGN_BYTES(8); + NvU32 allocAttr2; + NvU32 retAttr2; // Output Indicates the resources that we allocated + NvU64 allocAddr NV_ALIGN_BYTES(8); + // [out] from GMMU_COMPR_INFO in drivers/common/shared/inc/mmu/gmmu_fmt.h + struct + { + NvU32 compPageShift; + NvU32 compressedKind; + NvU32 compTagLineMin; + NvU32 compPageIndexLo; + NvU32 compPageIndexHi; + NvU32 compTagLineMultiplier; + } comprInfo; + // [out] fallback uncompressed kind. + NvU32 uncompressedKind; + } HwAlloc; + + // NVOS32_FUNCTION_HW_FREE + struct + { + NvHandle hResourceHandle; // Handle to RM Resource Info + NvU32 flags; // Indicate if HW Resources and/or Memory + } HwFree; +// Updated interface check. +#define NV_RM_OS32_ALLOC_OS_DESCRIPTOR_WITH_OS32_ATTR 1 + + // NVOS32_FUNCTION_ALLOC_OS_DESCRIPTOR + struct + { + NvHandle hMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated) + NvU32 type; // [IN] - surface type, see below TYPE* defines + NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines + NvU32 attr; // [IN] - attributes for memory placement/properties, see below + NvU32 attr2; // [IN] - attributes GPU_CACHEABLE + NvP64 descriptor NV_ALIGN_BYTES(8); // [IN] - descriptor address + NvU64 limit NV_ALIGN_BYTES(8); // [IN] - allocated size -1 + NvU32 descriptorType; // [IN] - descriptor type(Virtual | nvmap Handle) + } AllocOsDesc; + + } data; +} NVOS32_PARAMETERS; + +typedef struct +{ + NvU32 owner; // owner id - NVOS32_BLOCK_TYPE_FREE or defined by client during heap_alloc + NvU32 format; // arch specific format/kind + NvU64 begin NV_ALIGN_BYTES(8); // start of allocated memory block + NvU64 align NV_ALIGN_BYTES(8); // actual start of usable memory, aligned to chip specific boundary + NvU64 end NV_ALIGN_BYTES(8); // end of usable memory. end - align + 1 = size of block +} NVOS32_HEAP_DUMP_BLOCK; + + +#define NVOS32_DELETE_RESOURCES_ALL 0 + +// type field +#define NVOS32_TYPE_IMAGE 0 +#define NVOS32_TYPE_DEPTH 1 +#define NVOS32_TYPE_TEXTURE 2 +#define NVOS32_TYPE_VIDEO 3 +#define NVOS32_TYPE_FONT 4 +#define NVOS32_TYPE_CURSOR 5 +#define NVOS32_TYPE_DMA 6 +#define NVOS32_TYPE_INSTANCE 7 +#define NVOS32_TYPE_PRIMARY 8 +#define NVOS32_TYPE_ZCULL 9 +#define NVOS32_TYPE_UNUSED 10 +#define NVOS32_TYPE_SHADER_PROGRAM 11 +#define NVOS32_TYPE_OWNER_RM 12 +#define NVOS32_TYPE_NOTIFIER 13 +#define NVOS32_TYPE_RESERVED 14 +#define NVOS32_TYPE_PMA 15 +#define NVOS32_TYPE_STENCIL 16 +#define NVOS32_NUM_MEM_TYPES 17 + +// Surface attribute field - bitmask of requested attributes the surface +// should have. +// This value is updated to reflect what was actually allocated, and so this +// field must be checked after every allocation to determine what was +// allocated. Pass in the ANY tags to indicate that RM should fall back but +// still succeed the alloc. +// for example, if tiled_any is passed in, but no tile ranges are available, +// RM will allocate normal memory and indicate that in the returned attr field. +// Each returned attribute will have the REQUIRED field set if that attribute +// applies to the allocated surface. + +#define NVOS32_ATTR_NONE 0x00000000 + +#define NVOS32_ATTR_DEPTH 2:0 +#define NVOS32_ATTR_DEPTH_UNKNOWN 0x00000000 +#define NVOS32_ATTR_DEPTH_8 0x00000001 +#define NVOS32_ATTR_DEPTH_16 0x00000002 +#define NVOS32_ATTR_DEPTH_24 0x00000003 +#define NVOS32_ATTR_DEPTH_32 0x00000004 +#define NVOS32_ATTR_DEPTH_64 0x00000005 +#define NVOS32_ATTR_DEPTH_128 0x00000006 + +#define NVOS32_ATTR_COMPR_COVG 3:3 +#define NVOS32_ATTR_COMPR_COVG_DEFAULT 0x00000000 +#define NVOS32_ATTR_COMPR_COVG_PROVIDED 0x00000001 + +// Surface description - number of AA samples +// This number should only reflect AA done in hardware, not in software. For +// example, OpenGL's 8x AA mode is a mix of 2x hardware multisample and 2x2 +// software supersample. +// OpenGL should specify ATTR_AA_SAMPLES of 2 in this case, not 8, because +// the hardware will be programmed to run in 2x AA mode. +// Note that X_VIRTUAL_Y means X real samples with Y samples total (i.e. Y +// does not indicate the number of virtual samples). For instance, what +// arch and HW describe as NV_PGRAPH_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 +// corresponds to NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_16 here. + +#define NVOS32_ATTR_AA_SAMPLES 7:4 +#define NVOS32_ATTR_AA_SAMPLES_1 0x00000000 +#define NVOS32_ATTR_AA_SAMPLES_2 0x00000001 +#define NVOS32_ATTR_AA_SAMPLES_4 0x00000002 +#define NVOS32_ATTR_AA_SAMPLES_4_ROTATED 0x00000003 +#define NVOS32_ATTR_AA_SAMPLES_6 0x00000004 +#define NVOS32_ATTR_AA_SAMPLES_8 0x00000005 +#define NVOS32_ATTR_AA_SAMPLES_16 0x00000006 +#define NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_8 0x00000007 +#define NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_16 0x00000008 +#define NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_16 0x00000009 +#define NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_32 0x0000000A + +// Tiled region +#define NVOS32_ATTR_TILED 9:8 +#define NVOS32_ATTR_TILED_NONE 0x00000000 +#define NVOS32_ATTR_TILED_REQUIRED 0x00000001 +#define NVOS32_ATTR_TILED_ANY 0x00000002 +#define NVOS32_ATTR_TILED_DEFERRED 0x00000003 + +// Zcull region (NV40 and up) +// If ATTR_ZCULL is REQUIRED or ANY and ATTR_DEPTH is UNKNOWN, the +// allocation will fail. +// If ATTR_DEPTH or ATTR_AA_SAMPLES is not accurate, erroneous rendering +// may result. +#define NVOS32_ATTR_ZCULL 11:10 +#define NVOS32_ATTR_ZCULL_NONE 0x00000000 +#define NVOS32_ATTR_ZCULL_REQUIRED 0x00000001 +#define NVOS32_ATTR_ZCULL_ANY 0x00000002 +#define NVOS32_ATTR_ZCULL_SHARED 0x00000003 + +// Compression (NV20 and up) +// If ATTR_COMPR is REQUIRED or ANY and ATTR_DEPTH is UNKNOWN, the +// allocation will fail. +// If ATTR_DEPTH or ATTR_AA_SAMPLES is not accurate, performance will +// suffer heavily +#define NVOS32_ATTR_COMPR 13:12 +#define NVOS32_ATTR_COMPR_NONE 0x00000000 +#define NVOS32_ATTR_COMPR_REQUIRED 0x00000001 +#define NVOS32_ATTR_COMPR_ANY 0x00000002 +#define NVOS32_ATTR_COMPR_PLC_REQUIRED NVOS32_ATTR_COMPR_REQUIRED +#define NVOS32_ATTR_COMPR_PLC_ANY NVOS32_ATTR_COMPR_ANY +#define NVOS32_ATTR_COMPR_DISABLE_PLC_ANY 0x00000003 + +// Format +// _BLOCK_LINEAR is only available for nv50+. +#define NVOS32_ATTR_FORMAT 17:16 +// Macros representing the low/high bits of NVOS32_ATTR_FORMAT +// bit range. These provide direct access to the range limits +// without needing to split the low:high representation via +// ternary operator, thereby avoiding MISRA 14.3 violation. +#define NVOS32_ATTR_FORMAT_LOW_FIELD 16 +#define NVOS32_ATTR_FORMAT_HIGH_FIELD 17 +#define NVOS32_ATTR_FORMAT_PITCH 0x00000000 +#define NVOS32_ATTR_FORMAT_SWIZZLED 0x00000001 +#define NVOS32_ATTR_FORMAT_BLOCK_LINEAR 0x00000002 + +#define NVOS32_ATTR_Z_TYPE 18:18 +#define NVOS32_ATTR_Z_TYPE_FIXED 0x00000000 +#define NVOS32_ATTR_Z_TYPE_FLOAT 0x00000001 + +#define NVOS32_ATTR_ZS_PACKING 21:19 +#define NVOS32_ATTR_ZS_PACKING_S8 0x00000000 // Z24S8 and S8 share definition +#define NVOS32_ATTR_ZS_PACKING_Z24S8 0x00000000 +#define NVOS32_ATTR_ZS_PACKING_S8Z24 0x00000001 +#define NVOS32_ATTR_ZS_PACKING_Z32 0x00000002 +#define NVOS32_ATTR_ZS_PACKING_Z24X8 0x00000003 +#define NVOS32_ATTR_ZS_PACKING_X8Z24 0x00000004 +#define NVOS32_ATTR_ZS_PACKING_Z32_X24S8 0x00000005 +#define NVOS32_ATTR_ZS_PACKING_X8Z24_X24S8 0x00000006 +#define NVOS32_ATTR_ZS_PACKING_Z16 0x00000007 +// NOTE: ZS packing and color packing fields are overlaid +#define NVOS32_ATTR_COLOR_PACKING NVOS32_ATTR_ZS_PACKING +#define NVOS32_ATTR_COLOR_PACKING_A8R8G8B8 0x00000000 +#define NVOS32_ATTR_COLOR_PACKING_X8R8G8B8 0x00000001 + + + +// +// For virtual allocs to choose page size for the region. Specifying +// _DEFAULT will select a virtual page size that allows for a surface +// to be mixed between video and system memory and allow the surface +// to be migrated between video and system memory. For tesla chips, +// 4KB will be used. For fermi chips with dual page tables, a virtual +// address with both page tables will be used. +// +// For physical allocation on chips with page swizzle this field is +// used to select the page swizzle. This later also sets the virtual +// page size, but does not have influence over selecting a migratable +// virtual address. That must be selected when mapping the physical +// memory. +// +// BIG_PAGE = 64 KB on PASCAL +// = 64 KB or 128 KB on pre_PASCAL chips +// +// HUGE_PAGE = 2 MB on PASCAL+ +// = 2 MB or 512 MB on AMPERE+ +// = not supported on pre_PASCAL chips. +// +// To request for a HUGE page size, +// set NVOS32_ATTR_PAGE_SIZE to _HUGE and NVOS32_ATTR2_PAGE_SIZE_HUGE to +// the desired size. +// +#define NVOS32_ATTR_PAGE_SIZE 24:23 +#define NVOS32_ATTR_PAGE_SIZE_DEFAULT 0x00000000 +#define NVOS32_ATTR_PAGE_SIZE_4KB 0x00000001 +#define NVOS32_ATTR_PAGE_SIZE_BIG 0x00000002 +#define NVOS32_ATTR_PAGE_SIZE_HUGE 0x00000003 + +#define NVOS32_ATTR_LOCATION 26:25 +#define NVOS32_ATTR_LOCATION_VIDMEM 0x00000000 +#define NVOS32_ATTR_LOCATION_PCI 0x00000001 +#define NVOS32_ATTR_LOCATION_AGP 0x00000002 +#define NVOS32_ATTR_LOCATION_ANY 0x00000003 + +// +// _DEFAULT implies _CONTIGUOUS for video memory currently, but +// may be changed to imply _NONCONTIGUOUS in the future. +// _ALLOW_NONCONTIGUOUS enables falling back to the noncontiguous +// vidmem allocator if contig allocation fails. +// +#define NVOS32_ATTR_PHYSICALITY 28:27 +#define NVOS32_ATTR_PHYSICALITY_DEFAULT 0x00000000 +#define NVOS32_ATTR_PHYSICALITY_NONCONTIGUOUS 0x00000001 +#define NVOS32_ATTR_PHYSICALITY_CONTIGUOUS 0x00000002 +#define NVOS32_ATTR_PHYSICALITY_ALLOW_NONCONTIGUOUS 0x00000003 + +#define NVOS32_ATTR_COHERENCY 31:29 +#define NVOS32_ATTR_COHERENCY_UNCACHED 0x00000000 +#define NVOS32_ATTR_COHERENCY_CACHED 0x00000001 +#define NVOS32_ATTR_COHERENCY_WRITE_COMBINE 0x00000002 +#define NVOS32_ATTR_COHERENCY_WRITE_THROUGH 0x00000003 +#define NVOS32_ATTR_COHERENCY_WRITE_PROTECT 0x00000004 +#define NVOS32_ATTR_COHERENCY_WRITE_BACK 0x00000005 + +// ATTR2 fields +#define NVOS32_ATTR2_NONE 0x00000000 + +// +// DEFAULT - Let lower level drivers pick optimal page kind. +// PREFER_NO_ZBC - Prefer other types of compression over ZBC when +// selecting page kind. +// PREFER_ZBC - Prefer ZBC over other types of compression when +// selecting page kind. +// REQUIRE_ONLY_ZBC - Require a page kind that enables ZBC but disables +// other types of compression (i.e. 2C page kind). +// INVALID - Aliases REQUIRE_ONLY_ZBC, which is not supported +// by all RM implementations. +// +#define NVOS32_ATTR2_ZBC 1:0 +#define NVOS32_ATTR2_ZBC_DEFAULT 0x00000000 +#define NVOS32_ATTR2_ZBC_PREFER_NO_ZBC 0x00000001 +#define NVOS32_ATTR2_ZBC_PREFER_ZBC 0x00000002 +#define NVOS32_ATTR2_ZBC_REQUIRE_ONLY_ZBC 0x00000003 +#define NVOS32_ATTR2_ZBC_INVALID 0x00000003 + +// +// DEFAULT - Highest performance cache policy that is coherent with the highest +// performance CPU mapping. Typically this is gpu cached for video +// memory and gpu uncached for system memory. +// YES - Enable gpu caching if supported on this surface type. For system +// memory this will not be coherent with direct CPU mappings. +// NO - Disable gpu caching if supported on this surface type. +// INVALID - Clients should never set YES and NO simultaneously. +// +#define NVOS32_ATTR2_GPU_CACHEABLE 3:2 +#define NVOS32_ATTR2_GPU_CACHEABLE_DEFAULT 0x00000000 +#define NVOS32_ATTR2_GPU_CACHEABLE_YES 0x00000001 +#define NVOS32_ATTR2_GPU_CACHEABLE_NO 0x00000002 +#define NVOS32_ATTR2_GPU_CACHEABLE_INVALID 0x00000003 + +// +// DEFAULT - GPU-dependent cache policy +// YES - Enable gpu caching for p2p mem +// NO - Disable gpu caching for p2p mem +// +#define NVOS32_ATTR2_P2P_GPU_CACHEABLE 5:4 +#define NVOS32_ATTR2_P2P_GPU_CACHEABLE_DEFAULT 0x00000000 +#define NVOS32_ATTR2_P2P_GPU_CACHEABLE_YES 0x00000001 +#define NVOS32_ATTR2_P2P_GPU_CACHEABLE_NO 0x00000002 + +// This applies to virtual allocs only. See NVOS46_FLAGS_32BIT_POINTER. +#define NVOS32_ATTR2_32BIT_POINTER 6:6 +#define NVOS32_ATTR2_32BIT_POINTER_DISABLE 0x00000000 +#define NVOS32_ATTR2_32BIT_POINTER_ENABLE 0x00000001 + +// +// Indicates address conversion to be used, which affects what +// pitch alignment needs to be used +// +#define NVOS32_ATTR2_TILED_TYPE 7:7 +#define NVOS32_ATTR2_TILED_TYPE_LINEAR 0x00000000 +#define NVOS32_ATTR2_TILED_TYPE_XY 0x00000001 + +// +// Force SMMU mapping on GPU physical allocation in Tegra +// SMMU mapping for GPU physical allocation decided internally by RM +// This attribute provide an override to RM policy for verification purposes. +// +#define NVOS32_ATTR2_SMMU_ON_GPU 10:8 +#define NVOS32_ATTR2_SMMU_ON_GPU_DEFAULT 0x00000000 +#define NVOS32_ATTR2_SMMU_ON_GPU_DISABLE 0x00000001 +#define NVOS32_ATTR2_SMMU_ON_GPU_ENABLE 0x00000002 + +// +// Make comptag allocation aligned to compression cacheline size. +// Specifying this attribute will make RM allocate comptags worth an entire +// comp cacheline. The allocation will be offset aligned to number of comptags/comp cacheline. +// +#define NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN 11:11 +#define NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_OFF 0x0 +#define NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_ON 0x1 +#define NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_DEFAULT \ + NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_OFF + +// Allocation preferred in high or low priority memory +#define NVOS32_ATTR2_PRIORITY 13:12 +#define NVOS32_ATTR2_PRIORITY_DEFAULT 0x0 +#define NVOS32_ATTR2_PRIORITY_HIGH 0x1 +#define NVOS32_ATTR2_PRIORITY_LOW 0x2 + +// PMA: Allocation is an RM internal allocation (RM-only) +#define NVOS32_ATTR2_INTERNAL 14:14 +#define NVOS32_ATTR2_INTERNAL_NO 0x0 +#define NVOS32_ATTR2_INTERNAL_YES 0x1 + +// Allocate 2C instead of 2CZ +#define NVOS32_ATTR2_PREFER_2C 15:15 +#define NVOS32_ATTR2_PREFER_2C_NO 0x00000000 +#define NVOS32_ATTR2_PREFER_2C_YES 0x00000001 + +// Allocation used by display engine; RM verifies display engine has enough +// address bits or remapper available. +#define NVOS32_ATTR2_NISO_DISPLAY 16:16 +#define NVOS32_ATTR2_NISO_DISPLAY_NO 0x00000000 +#define NVOS32_ATTR2_NISO_DISPLAY_YES 0x00000001 + +// +// !!WARNING!!! +// +// This flag is introduced as a temporary WAR to enable color compression +// without ZBC. +// +// This dangerous flag can be used by UMDs to instruct RM to skip the zbc +// table refcounting that RM does today, when the chosen PTE kind has ZBC +// support. +// +// Currently we do not have a safe per process zbc slot management and +// refcounting mechanism between RM and UMD and hence, any process can +// access any other process's zbc entry in the global zbc table (without mask) +// Inorder to flush the ZBC table for slot reuse RM cannot track which +// process is using which zbc slot. Hence RM has a global refcount for the +// zbc table to flush and reuse the entries if the PTE kind supports zbc. +// +// This scheme poses a problem if there are apps that are persistent such as +// the desktop components that can have color compression enabled which will +// always keep the refcount active. Since these apps can live without +// ZBC, UMD can disable ZBC using masks. +// +// In such a case, if UMD so chooses to disable ZBC, this flag should be used +// to skip refcounting as by default RM would refcount the ZBC table. +// +// NOTE: There is no way for RM to enforce/police this, and we totally rely +// on UMD to use a zbc mask in the pushbuffer method to prevent apps from +// accessing the ZBC table. +// +#define NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT 17:17 +#define NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_NO 0x00000000 +#define NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_YES 0x00000001 + +// Allocation requires ISO bandwidth guarantees +#define NVOS32_ATTR2_ISO 18:18 +#define NVOS32_ATTR2_ISO_NO 0x00000000 +#define NVOS32_ATTR2_ISO_YES 0x00000001 + +// +// Turn off blacklist feature for video memory allocation +// This attribute should be used only by Kernel client (KMD), to mask +// the blacklisted pages for the allocation. This is done so that the clients +// will manage the above masked blacklisted pages after the allocation. It will +// return to RM's pool after the allocation was free-d.RmVidHeapCtrl returns +// NV_ERR_INSUFFICIENT_PERMISSIONS if it is being called by non-kernel clients. +// + +// TODO: Project ReLingo - This term is marked for deletion. Use PAGE_OFFLINING. +#define NVOS32_ATTR2_BLACKLIST 19:19 +#define NVOS32_ATTR2_BLACKLIST_ON 0x00000000 +#define NVOS32_ATTR2_BLACKLIST_OFF 0x00000001 +#define NVOS32_ATTR2_PAGE_OFFLINING 19:19 +#define NVOS32_ATTR2_PAGE_OFFLINING_ON 0x00000000 +#define NVOS32_ATTR2_PAGE_OFFLINING_OFF 0x00000001 + +// +// For virtual allocs to choose the HUGE page size for the region. +// NVOS32_ATTR_PAGE_SIZE must be set to _HUGE to use this. +// Currently, the default huge page is 2MB, so a request with _DEFAULT +// set will always be interpreted as 2MB. +// Not supported on pre_AMPERE chips. +// +#define NVOS32_ATTR2_PAGE_SIZE_HUGE 21:20 +#define NVOS32_ATTR2_PAGE_SIZE_HUGE_DEFAULT 0x00000000 +#define NVOS32_ATTR2_PAGE_SIZE_HUGE_2MB 0x00000001 +#define NVOS32_ATTR2_PAGE_SIZE_HUGE_512MB 0x00000002 + +// Allow read-only or read-write user CPU mappings +#define NVOS32_ATTR2_PROTECTION_USER 22:22 +#define NVOS32_ATTR2_PROTECTION_USER_READ_WRITE 0x00000000 +#define NVOS32_ATTR2_PROTECTION_USER_READ_ONLY 0x00000001 + +// Allow read-only or read-write device mappings +#define NVOS32_ATTR2_PROTECTION_DEVICE 23:23 +#define NVOS32_ATTR2_PROTECTION_DEVICE_READ_WRITE 0x00000000 +#define NVOS32_ATTR2_PROTECTION_DEVICE_READ_ONLY 0x00000001 + +// +// Force the allocation to go to guest subheap. +// This flag is used by vmiop plugin to allocate from GPA +// +#define NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP 27:27 +#define NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_NO 0x00000000 +#define NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_YES 0x00000001 + +/** + * NVOS32 ALLOC_FLAGS + * + * NVOS32_ALLOC_FLAGS_IGNORE_BANK_PLACEMENT + * + * NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_UP + * + * NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN + * + * NVOS32_ALLOC_FLAGS_FORCE_ALIGN_HOST_PAGE + * + * NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE + * + * NVOS32_ALLOC_FLAGS_BANK_HINT + * + * NVOS32_ALLOC_FLAGS_BANK_FORCE + * + * NVOS32_ALLOC_FLAGS_ALIGNMENT_HINT + * + * NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE + * + * NVOS32_ALLOC_FLAGS_BANK_GROW_UP + * Only relevant if bank_hint or bank_force are set + * + * NVOS32_ALLOC_FLAGS_BANK_GROW_DOWN + * Only relevant if bank_hint or bank_force are set + * + * NVOS32_ALLOC_FLAGS_LAZY + * Lazy allocation (deferred pde, pagetable creation) + * + * NVOS32_ALLOC_FLAGS_NO_SCANOUT + * Set if surface will never be scanned out + * + * NVOS32_ALLOC_FLAGS_PITCH_FORCE + * Fail alloc if supplied pitch is not aligned + * + * NVOS32_ALLOC_FLAGS_MEMORY_HANDLE_PROVIDED + * Memory handle provided to be associated with this allocation + * + * NVOS32_ALLOC_FLAGS_MAP_NOT_REQUIRED + * By default memory is mapped into the CPU address space + * + * NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM + * Allocate persistent video memory + * + * NVOS32_ALLOC_FLAGS_USE_BEGIN_END + * Use rangeBegin & rangeEnd fields in allocs other than size/range + * + * NVOS32_ALLOC_FLAGS_TURBO_CIPHER_ENCRYPTED + * Allocate TurboCipher encrypted region + * + * NVOS32_ALLOC_FLAGS_VIRTUAL + * Allocate virtual memory address space + * + * NVOS32_ALLOC_FLAGS_FORCE_INTERNAL_INDEX + * Force allocation internal index + * + * NVOS32_ALLOC_FLAGS_ZCULL_COVG_SPECIFIED + * This flag is depreciated and allocations will fail. + * + * NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED + * Must be used with NVOS32_ALLOC_FLAGS_VIRTUAL. + * Page tables for this allocation will be managed outside of RM. + * + * NVOS32_ALLOC_FLAGS_FORCE_DEDICATED_PDE + * + * NVOS32_ALLOC_FLAGS_PROTECTED + * Allocate in a protected memory region if available + * + * NVOS32_ALLOC_FLAGS_KERNEL_MAPPING_MAP + * Map kernel os descriptor + * + * NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE + * On WDDM all address spaces are created with MINIMIZE_PTETABLE_SIZE + * to reduce the overhead of private address spaces per application, + * at the cost of holes in the virtual address space. + * + * Shaders have short pointers that are required to be within a + * GPU dependent 32b range. + * + * MAXIMIZE_ADDRESS_SPACE will reverse the MINIMIZE_PTE_TABLE_SIZE + * flag with certain restrictions: + * - This flag only has an effect when the allocation has the side + * effect of creating a new PDE. It does not affect existing PDEs. + * - The first few PDEs of the address space are kept minimum to allow + * small applications to use fewer resources. + * - By default this operations on the 0-4GB address range. + * - If USE_BEGIN_END is specified the setting will apply to the + * specified range instead of the first 4GB. + * + * NVOS32_ALLOC_FLAGS_SPARSE + * Denote that a virtual address range is "sparse". Must be used with + * NVOS32_ALLOC_FLAGS_VIRTUAL. Creation of a "sparse" virtual address range + * denotes that an unmapped virtual address range should "not" fault but simply + * return 0's. + * + * NVOS32_ALLOC_FLAGS_ALLOCATE_KERNEL_PRIVILEGED + * This a special flag that can be used only by kernel(root) clients + * to allocate memory out of a protected region of the address space + * If this flag is set by non kernel clients then the allocation will + * fail. + * + * NVOS32_ALLOC_FLAGS_SKIP_RESOURCE_ALLOC + * + * NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY + * If new pagetable need to be allocated prefer them in sysmem (if supported by the gpu) + * + * NVOS32_ALLOC_FLAGS_SKIP_ALIGN_PAD + * As per KMD request to eliminate extra allocation + * + * NVOS32_ALLOC_FLAGS_WPR1 + * Allocate in a WPR1 region if available + * + * NVOS32_ALLOC_FLAGS_ZCULL_DONT_ALLOCATE_SHARED_1X + * If using zcull sharing and this surface is fsaa, then don't allocate an additional non-FSAA region. + * + * NVOS32_ALLOC_FLAGS_WPR2 + * Allocate in a WPR1 region if available + */ +#define NVOS32_ALLOC_FLAGS_IGNORE_BANK_PLACEMENT 0x00000001 +#define NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_UP 0x00000002 +#define NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN 0x00000004 +#define NVOS32_ALLOC_FLAGS_FORCE_ALIGN_HOST_PAGE 0x00000008 +#define NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE 0x00000010 +#define NVOS32_ALLOC_FLAGS_BANK_HINT 0x00000020 +#define NVOS32_ALLOC_FLAGS_BANK_FORCE 0x00000040 +#define NVOS32_ALLOC_FLAGS_ALIGNMENT_HINT 0x00000080 +#define NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE 0x00000100 +#define NVOS32_ALLOC_FLAGS_BANK_GROW_UP 0x00000000 +#define NVOS32_ALLOC_FLAGS_BANK_GROW_DOWN 0x00000200 +#define NVOS32_ALLOC_FLAGS_LAZY 0x00000400 +// unused 0x00000800 +#define NVOS32_ALLOC_FLAGS_NO_SCANOUT 0x00001000 +#define NVOS32_ALLOC_FLAGS_PITCH_FORCE 0x00002000 +#define NVOS32_ALLOC_FLAGS_MEMORY_HANDLE_PROVIDED 0x00004000 +#define NVOS32_ALLOC_FLAGS_MAP_NOT_REQUIRED 0x00008000 +#define NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM 0x00010000 +#define NVOS32_ALLOC_FLAGS_USE_BEGIN_END 0x00020000 +#define NVOS32_ALLOC_FLAGS_TURBO_CIPHER_ENCRYPTED 0x00040000 +#define NVOS32_ALLOC_FLAGS_VIRTUAL 0x00080000 +#define NVOS32_ALLOC_FLAGS_FORCE_INTERNAL_INDEX 0x00100000 +#define NVOS32_ALLOC_FLAGS_ZCULL_COVG_SPECIFIED 0x00200000 +#define NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED 0x00400000 +#define NVOS32_ALLOC_FLAGS_FORCE_DEDICATED_PDE 0x00800000 +#define NVOS32_ALLOC_FLAGS_PROTECTED 0x01000000 +#define NVOS32_ALLOC_FLAGS_KERNEL_MAPPING_MAP 0x02000000 // TODO BUG 2488679: fix alloc flag aliasing +#define NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE 0x02000000 +#define NVOS32_ALLOC_FLAGS_SPARSE 0x04000000 +#define NVOS32_ALLOC_FLAGS_USER_READ_ONLY 0x04000000 // TODO BUG 2488682: remove this after KMD transition +#define NVOS32_ALLOC_FLAGS_DEVICE_READ_ONLY 0x08000000 // TODO BUG 2488682: remove this after KMD transition +#define NVOS32_ALLOC_FLAGS_ALLOCATE_KERNEL_PRIVILEGED 0x08000000 +#define NVOS32_ALLOC_FLAGS_SKIP_RESOURCE_ALLOC 0x10000000 +#define NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY 0x20000000 +#define NVOS32_ALLOC_FLAGS_SKIP_ALIGN_PAD 0x40000000 +#define NVOS32_ALLOC_FLAGS_WPR1 0x40000000 // TODO BUG 2488672: fix alloc flag aliasing +#define NVOS32_ALLOC_FLAGS_ZCULL_DONT_ALLOCATE_SHARED_1X 0x80000000 +#define NVOS32_ALLOC_FLAGS_WPR2 0x80000000 // TODO BUG 2488672: fix alloc flag aliasing + +// Internal flags used for RM's allocation paths +#define NVOS32_ALLOC_INTERNAL_FLAGS_CLIENTALLOC 0x00000001 // RM internal flags - not sure if this should be exposed even. Keeping it here. +#define NVOS32_ALLOC_INTERNAL_FLAGS_SKIP_SCRUB 0x00000004 // RM internal flags - not sure if this should be exposed even. Keeping it here. +#define NVOS32_ALLOC_FLAGS_MAXIMIZE_4GB_ADDRESS_SPACE NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE // Legacy name + +// +// Bitmask of flags that are only valid for virtual allocations. +// +#define NVOS32_ALLOC_FLAGS_VIRTUAL_ONLY ( \ + NVOS32_ALLOC_FLAGS_VIRTUAL | \ + NVOS32_ALLOC_FLAGS_LAZY | \ + NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED | \ + NVOS32_ALLOC_FLAGS_SPARSE | \ + NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE | \ + NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY ) + +// COMPR_COVG_* allows for specification of what compression resources +// are required (_MIN) and necessary (_MAX). Default behavior is for +// RM to provide as much as possible, including none if _ANY is allowed. +// Values for min/max are (0-100, a %) * _COVG_SCALE (so max value is +// 100*100==10000). _START is used to specify the % offset into the +// region to begin the requested coverage. +// _COVG_BITS allows specification of the number of comptags per ROP tile. +// A value of 0 is default and allows RM to choose based upon MMU/FB rules. +// All other values for _COVG_BITS are arch-specific. +// Note: NVOS32_ATTR_COMPR_COVG_PROVIDED must be set for this feature +// to be available (verif-only). +#define NVOS32_ALLOC_COMPR_COVG_SCALE 10 +#define NVOS32_ALLOC_COMPR_COVG_BITS 1:0 +#define NVOS32_ALLOC_COMPR_COVG_BITS_DEFAULT 0x00000000 +#define NVOS32_ALLOC_COMPR_COVG_BITS_1 0x00000001 +#define NVOS32_ALLOC_COMPR_COVG_BITS_2 0x00000002 +#define NVOS32_ALLOC_COMPR_COVG_BITS_4 0x00000003 +#define NVOS32_ALLOC_COMPR_COVG_MAX 11:2 +#define NVOS32_ALLOC_COMPR_COVG_MIN 21:12 +#define NVOS32_ALLOC_COMPR_COVG_START 31:22 + + +// Note: NVOS32_ALLOC_FLAGS_ZCULL_COVG_SPECIFIED must be set for this feature +// to be enabled. +// If FALLBACK_ALLOW is set, a fallback from LOW_RES_Z or LOW_RES_ZS +// to HIGH_RES_Z is allowed if the surface can't be fully covered. +#define NVOS32_ALLOC_ZCULL_COVG_FORMAT 3:0 +#define NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_Z 0x00000000 +#define NVOS32_ALLOC_ZCULL_COVG_FORMAT_HIGH_RES_Z 0x00000002 +#define NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_ZS 0x00000003 +#define NVOS32_ALLOC_ZCULL_COVG_FALLBACK 4:4 +#define NVOS32_ALLOC_ZCULL_COVG_FALLBACK_DISALLOW 0x00000000 +#define NVOS32_ALLOC_ZCULL_COVG_FALLBACK_ALLOW 0x00000001 + + +// _ALLOC_COMPTAG_OFFSET allows the caller to specify the starting +// offset for the comptags for a given surface, primarily for test only. +// To specify an offset, set _USAGE_FIXED or _USAGE_MIN in conjunction +// with _START. +// +// _USAGE_FIXED sets a surface's comptagline to start at the given +// starting value. If the offset has already been assigned, then +// the alloc call fails. +// +// _USAGE_MIN sets a surface's comptagline to start at the given +// starting value or higher, depending on comptagline availability. +// In this case, if the offset has already been assigned, the next +// available comptagline (in increasing order) will be assigned. +// +// For Fermi, up to 2^17 comptags may be allowed, but the actual, +// usable limit depends on the size of the compbit backing store. +// +// For Pascal, up to 2 ^ 18 comptags may be allowed +// From Turing. up to 2 ^ 20 comptags may be allowed +// +// See also field ctagOffset in struct NVOS32_PARAMETERS. +#define NVOS32_ALLOC_COMPTAG_OFFSET_START 19:0 +#define NVOS32_ALLOC_COMPTAG_OFFSET_START_DEFAULT 0x00000000 +#define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE 31:30 +#define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_DEFAULT 0x00000000 +#define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_OFF 0x00000000 +#define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_FIXED 0x00000001 +#define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_MIN 0x00000002 + + +// REALLOC flags field +#define NVOS32_REALLOC_FLAGS_GROW_ALLOCATION 0x00000000 +#define NVOS32_REALLOC_FLAGS_SHRINK_ALLOCATION 0x00000001 +#define NVOS32_REALLOC_FLAGS_REALLOC_UP 0x00000000 // towards/from high memory addresses +#define NVOS32_REALLOC_FLAGS_REALLOC_DOWN 0x00000002 // towards/from memory address 0 + +// RELEASE_COMPR, REACQUIRE_COMPR flags field +#define NVOS32_RELEASE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED 0x000000001 + +#define NVOS32_REACQUIRE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED 0x000000001 + + +// FREE flags field +#define NVOS32_FREE_FLAGS_MEMORY_HANDLE_PROVIDED 0x00000001 + +// DUMP flags field +#define NVOS32_DUMP_FLAGS_TYPE 1:0 +#define NVOS32_DUMP_FLAGS_TYPE_FB 0x00000000 +#define NVOS32_DUMP_FLAGS_TYPE_CLIENT_PD 0x00000001 +#define NVOS32_DUMP_FLAGS_TYPE_CLIENT_VA 0x00000002 +#define NVOS32_DUMP_FLAGS_TYPE_CLIENT_VAPTE 0x00000003 + +#define NVOS32_BLOCK_TYPE_FREE 0xFFFFFFFF +#define NVOS32_INVALID_BLOCK_FREE_OFFSET 0xFFFFFFFF + +#define NVOS32_MEM_TAG_NONE 0x00000000 + +/* + * NV_CONTEXT_DMA_ALLOCATION_PARAMS - Allocation params to create context dma + through NvRmAlloc. + */ +typedef struct +{ + NvHandle hSubDevice; + NvV32 flags; + NvHandle hMemory; + NvU64 offset NV_ALIGN_BYTES(8); + NvU64 limit NV_ALIGN_BYTES(8); +} NV_CONTEXT_DMA_ALLOCATION_PARAMS; + +/* + * NV_MEMORY_ALLOCATION_PARAMS - Allocation params to create memory through + * NvRmAlloc. Flags are populated with NVOS32_ defines. + */ +typedef struct +{ + NvU32 owner; // [IN] - memory owner ID + NvU32 type; // [IN] - surface type, see below TYPE* defines + NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines + + NvU32 width; // [IN] - width of surface in pixels + NvU32 height; // [IN] - height of surface in pixels + NvS32 pitch; // [IN/OUT] - desired pitch AND returned actual pitch allocated + + NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated + + NvU32 format; // [IN/OUT] - format requested, and format allocated + NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated + NvU32 zcullCovg; // [OUT] - zcull covg allocated + + NvU64 rangeLo NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range + NvU64 rangeHi NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive. + + NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated + NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on + NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset + NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit + NvP64 address NV_ALIGN_BYTES(8); // [OUT] - returned address + + NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET) + NvHandle hVASpace; // [IN] - VASpace handle. Used when flag is VIRTUAL. + + NvU32 internalflags; // [IN] - internal flags to change allocation behaviors from internal paths + + NvU32 tag; // [IN] - memory tag used for debugging +} NV_MEMORY_ALLOCATION_PARAMS; + +/* + * NV_OS_DESC_MEMORY_ALLOCATION_PARAMS - Allocation params to create OS + * described memory through NvRmAlloc. Flags are populated with NVOS32_ defines. + */ +typedef struct +{ + NvU32 type; // [IN] - surface type, see below TYPE* defines + NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines + NvU32 attr; // [IN] - attributes for memory placement/properties, see below + NvU32 attr2; // [IN] - attributes GPU_CACHEABLE + NvP64 descriptor NV_ALIGN_BYTES(8); // [IN] - descriptor address + NvU64 limit NV_ALIGN_BYTES(8); // [IN] - allocated size -1 + NvU32 descriptorType; // [IN] - descriptor type(Virtual | nvmap Handle) + NvU32 tag; // [IN] - memory tag used for debugging +} NV_OS_DESC_MEMORY_ALLOCATION_PARAMS; + +/* + * NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS - Allocation params to create a memory + * object from user allocated video memory. Flags are populated with NVOS32_* + * defines. + */ +typedef struct +{ + NvU32 flags; // [IN] - allocation modifier flags, see NVOS02_FLAGS* defines + NvU64 physAddr NV_ALIGN_BYTES(8); // [IN] - physical address + NvU64 size NV_ALIGN_BYTES(8); // [IN] - mem size + NvU32 tag; // [IN] - memory tag used for debugging + NvBool bGuestAllocated; // [IN] - Set if memory is guest allocated (mapped by VMMU) +} NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS; + +/* + * NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS - Allocation params to create + * memory HW resources through NvRmAlloc. Flags are populated with NVOS32_ + * defines. + */ +typedef struct +{ + NvU32 owner; // [IN] - memory owner ID + NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines + NvU32 type; // [IN] - surface type, see below TYPE* defines + + NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated + + NvU32 height; + NvU32 width; + NvU32 pitch; + NvU32 alignment; + NvU32 comprCovg; + NvU32 zcullCovg; + + NvU32 kind; + + NvP64 bindResultFunc NV_ALIGN_BYTES(8); // BindResultFunc + NvP64 pHandle NV_ALIGN_BYTES(8); + NvU64 osDeviceHandle NV_ALIGN_BYTES(8); + NvU64 size NV_ALIGN_BYTES(8); + NvU64 allocAddr NV_ALIGN_BYTES(8); + + // [out] from GMMU_COMPR_INFO in drivers/common/shared/inc/mmu/gmmu_fmt.h + NvU32 compPageShift; + NvU32 compressedKind; + NvU32 compTagLineMin; + NvU32 compPageIndexLo; + NvU32 compPageIndexHi; + NvU32 compTagLineMultiplier; + + // [out] fallback uncompressed kind. + NvU32 uncompressedKind; + + NvU32 tag; // [IN] - memory tag used for debugging +} NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS; + +/* function OS33 */ +#define NV04_MAP_MEMORY (0x00000021) + +// Legacy map and unmap memory flags that don't use DRF_DEF scheme +#define NV04_MAP_MEMORY_FLAGS_NONE (0x00000000) +#define NV04_MAP_MEMORY_FLAGS_USER (0x00004000) + +// New map and unmap memory flags. These flags are used for both NvRmMapMemory +// and for NvRmUnmapMemory. + +// Mappings can have restricted permissions (read-only, write-only). Some +// RM implementations may choose to ignore these flags, or they may work +// only for certain memory spaces (system, AGP, video memory); in such cases, +// you may get a read/write mapping even if you asked for a read-only or +// write-only mapping. +#define NVOS33_FLAGS_ACCESS 1:0 +#define NVOS33_FLAGS_ACCESS_READ_WRITE (0x00000000) +#define NVOS33_FLAGS_ACCESS_READ_ONLY (0x00000001) +#define NVOS33_FLAGS_ACCESS_WRITE_ONLY (0x00000002) + +// Persistent mappings are no longer supported +#define NVOS33_FLAGS_PERSISTENT 4:4 +#define NVOS33_FLAGS_PERSISTENT_DISABLE (0x00000000) +#define NVOS33_FLAGS_PERSISTENT_ENABLE (0x00000001) + +// This flag is a hack to work around bug 150889. It disables the error +// checking in the RM that verifies that the client is not trying to map +// memory past the end of the memory object. This error checking needs to +// be shut off in some cases for a PAE bug workaround in certain kernels. +#define NVOS33_FLAGS_SKIP_SIZE_CHECK 8:8 +#define NVOS33_FLAGS_SKIP_SIZE_CHECK_DISABLE (0x00000000) +#define NVOS33_FLAGS_SKIP_SIZE_CHECK_ENABLE (0x00000001) + +// Normally, a mapping is created in the same memory space as the client -- in +// kernel space for a kernel RM client, or in user space for a user RM client. +// However, a kernel RM client can specify MEM_SPACE:USER to create a user-space +// mapping in the current RM client. +#define NVOS33_FLAGS_MEM_SPACE 14:14 +#define NVOS33_FLAGS_MEM_SPACE_CLIENT (0x00000000) +#define NVOS33_FLAGS_MEM_SPACE_USER (0x00000001) + +// The client can ask for direct memory mapping (i.e. no BAR1) if remappers and +// blocklinear are not required. RM can do direct mapping in this case if +// carveout is available. +// DEFAULT: Use direct mapping if available and no address/data translation +// is necessary; reflected otherwise +// DIRECT: Use direct mapping if available, even if some translation is +// necessary (the client is responsible for translation) +// REFLECTED: Always use reflected mapping +#define NVOS33_FLAGS_MAPPING 16:15 +#define NVOS33_FLAGS_MAPPING_DEFAULT (0x00000000) +#define NVOS33_FLAGS_MAPPING_DIRECT (0x00000001) +#define NVOS33_FLAGS_MAPPING_REFLECTED (0x00000002) + +// The client requests a fifo mapping but doesn't know the offset or length +// DEFAULT: Do error check length and offset +// ENABLE: Don't error check length and offset but have the RM fill them in +#define NVOS33_FLAGS_FIFO_MAPPING 17:17 +#define NVOS33_FLAGS_FIFO_MAPPING_DEFAULT (0x00000000) +#define NVOS33_FLAGS_FIFO_MAPPING_ENABLE (0x00000001) + +// The client can require that the CPU mapping be to a specific CPU address +// (akin to MAP_FIXED for mmap). +// DISABLED: RM will map the allocation at a CPU VA that RM selects. +// ENABLED: RM will map the allocation at the CPU VA specified by the address +// pass-back parameter to NvRmMapMemory +// NOTES: +// - Used for controlling CPU addresses in CUDA's unified CPU+GPU virtual +// address space +// - Only valid on NvRmMapMemory +// - Only implemented on Linux +#define NVOS33_FLAGS_MAP_FIXED 18:18 +#define NVOS33_FLAGS_MAP_FIXED_DISABLE (0x00000000) +#define NVOS33_FLAGS_MAP_FIXED_ENABLE (0x00000001) + +// The client can specify to the RM that the CPU virtual address range for an +// allocation should remain reserved after the allocation is unmapped. +// DISABLE: When this mapping is destroyed, RM will unmap the CPU virtual +// address space used by this allocation. On Linux this corresponds +// to calling munmap on the CPU VA region. +// ENABLE: When the map object is freed, RM will leave the CPU virtual +// address space used by allocation reserved. On Linux this means +// that RM will overwrite the previous mapping with an anonymous +// mapping of instead calling munmap. +// NOTES: +// - When combined with MAP_FIXED, this allows the client to exert +// significant control over the CPU heap +// - Used in CUDA's unified CPU+GPU virtual address space +// - Only valid on NvRmMapMemory (specifies RM's behavior whenever the +// mapping is destroyed, regardless of mechanism) +// - Only implemented on Linux +#define NVOS33_FLAGS_RESERVE_ON_UNMAP 19:19 +#define NVOS33_FLAGS_RESERVE_ON_UNMAP_DISABLE (0x00000000) +#define NVOS33_FLAGS_RESERVE_ON_UNMAP_ENABLE (0x00000001) + +// Systems with a coherent NVLINK2 connection between the CPU and GPU +// have the option of directly mapping video memory over that connection. +// During mapping you may specify a preference. +// +#define NVOS33_FLAGS_BUS 21:20 +#define NVOS33_FLAGS_BUS_ANY 0 +#define NVOS33_FLAGS_BUS_NVLINK_COHERENT 1 +#define NVOS33_FLAGS_BUS_PCIE 2 + +// Internal use only +#define NVOS33_FLAGS_OS_DESCRIPTOR 22:22 +#define NVOS33_FLAGS_OS_DESCRIPTOR_DISABLE (0x00000000) +#define NVOS33_FLAGS_OS_DESCRIPTOR_ENABLE (0x00000001) + +// +// For use in the linux mapping path. This flag sets the +// caching mode for pcie BAR mappings (from nv_memory_type.h). +// Internal use only. +// +#define NVOS33_FLAGS_CACHING_TYPE 25:23 +#define NVOS33_FLAGS_CACHING_TYPE_CACHED 0 +#define NVOS33_FLAGS_CACHING_TYPE_UNCACHED 1 +#define NVOS33_FLAGS_CACHING_TYPE_WRITECOMBINED 2 +#define NVOS33_FLAGS_CACHING_TYPE_WRITEBACK 5 +#define NVOS33_FLAGS_CACHING_TYPE_DEFAULT 6 +#define NVOS33_FLAGS_CACHING_TYPE_UNCACHED_WEAK 7 + +/* parameters */ +typedef struct +{ + NvHandle hClient; + NvHandle hDevice; // device or sub-device handle + NvHandle hMemory; // handle to memory object if provided -- NULL if not + NvU64 offset NV_ALIGN_BYTES(8); + NvU64 length NV_ALIGN_BYTES(8); + NvP64 pLinearAddress NV_ALIGN_BYTES(8); // pointer for returned address + NvU32 status; + NvU32 flags; +} NVOS33_PARAMETERS; + + +/* function OS34 */ +#define NV04_UNMAP_MEMORY (0x00000022) + +/* parameters */ +typedef struct +{ + NvHandle hClient; + NvHandle hDevice; + NvHandle hMemory; + NvP64 pLinearAddress NV_ALIGN_BYTES(8); // ptr to virtual address of mapped memory + NvU32 status; + NvU32 flags; +} NVOS34_PARAMETERS; + +/* function OS38 */ +#define NV04_ACCESS_REGISTRY (0x00000026) + +/* parameter values */ +#define NVOS38_ACCESS_TYPE_READ_DWORD 1 +#define NVOS38_ACCESS_TYPE_WRITE_DWORD 2 +#define NVOS38_ACCESS_TYPE_READ_BINARY 6 +#define NVOS38_ACCESS_TYPE_WRITE_BINARY 7 + +#define NVOS38_MAX_REGISTRY_STRING_LENGTH 256 +#define NVOS38_MAX_REGISTRY_BINARY_LENGTH 256 + +/* parameters */ +typedef struct +{ + NvHandle hClient; + NvHandle hObject; + NvV32 AccessType; + + NvV32 DevNodeLength; + NvP64 pDevNode NV_ALIGN_BYTES(8); + + NvV32 ParmStrLength; + NvP64 pParmStr NV_ALIGN_BYTES(8); + + NvV32 BinaryDataLength; + NvP64 pBinaryData NV_ALIGN_BYTES(8); + + NvV32 Data; + NvV32 Entry; + NvV32 status; +} NVOS38_PARAMETERS; + +#define NV04_ALLOC_CONTEXT_DMA (0x00000027) + +/* parameter values are the same as NVOS03 -- not repeated here */ + +/* parameters */ +typedef struct +{ + NvHandle hObjectParent; + NvHandle hSubDevice; + NvHandle hObjectNew; + NvV32 hClass; + NvV32 flags; + NvU32 selector; + NvHandle hMemory; + NvU64 offset NV_ALIGN_BYTES(8); + NvU64 limit NV_ALIGN_BYTES(8); + NvV32 status; +} NVOS39_PARAMETERS; + + +#define NV04_GET_EVENT_DATA (0x00000028) + +typedef struct +{ + NvHandle hObject; + NvV32 NotifyIndex; + + // + // Holds same information as that of nvgputypes.h::NvNotification's + // info32 and info16. + // + NvV32 info32; + NvU16 info16; +} NvUnixEvent; + +/* parameters */ +typedef struct +{ + NvP64 pEvent NV_ALIGN_BYTES(8); + NvV32 MoreEvents; + NvV32 status; +} NVOS41_PARAMETERS; + +/* function NVOS43 -- deleted 4/09 */ +/* #define NV04_UNIFIED_FREE (0x0000002B) */ + + +#define NVSIM01_BUS_XACT (0x0000002C) + +/* parameters */ +typedef struct +{ + NvHandle hClient; // n/a currently + NvHandle hDevice; // n/a currently + NvU32 offset; // phy bus offset + NvU32 bar; // ~0 := phy addr, {0..2} specify gpu bar + NvU32 bytes; // # of bytes + NvU32 write; // 0 := read request + NvU32 data; // in/out based upon 'write' + NvU32 status; +} NVOS2C_PARAMETERS; + +/* function NVOS2D -- deleted 4/09 */ +/* #define NVSIM01_BUS_GET_IFACES (0x0000002D) */ + + +/* function OS46 */ +#define NV04_MAP_MEMORY_DMA (0x0000002E) + +/* parameter values */ +#define NVOS46_FLAGS_ACCESS 1:0 +#define NVOS46_FLAGS_ACCESS_READ_WRITE (0x00000000) +#define NVOS46_FLAGS_ACCESS_READ_ONLY (0x00000001) +#define NVOS46_FLAGS_ACCESS_WRITE_ONLY (0x00000002) + +// +// Compute shaders support both 32b and 64b pointers. This allows mappings +// to be restricted to the bottom 4GB of the address space. How _DISABLE +// is handled is chip specific and may force a pointer above 4GB. +// +#define NVOS46_FLAGS_32BIT_POINTER 2:2 +#define NVOS46_FLAGS_32BIT_POINTER_DISABLE (0x00000000) +#define NVOS46_FLAGS_32BIT_POINTER_ENABLE (0x00000001) + +#define NVOS46_FLAGS_PAGE_KIND 3:3 +#define NVOS46_FLAGS_PAGE_KIND_PHYSICAL (0x00000000) +#define NVOS46_FLAGS_PAGE_KIND_VIRTUAL (0x00000001) + +#define NVOS46_FLAGS_CACHE_SNOOP 4:4 +#define NVOS46_FLAGS_CACHE_SNOOP_DISABLE (0x00000000) +#define NVOS46_FLAGS_CACHE_SNOOP_ENABLE (0x00000001) + +// The client requests a CPU kernel mapping so that SW class could use it +// DEFAULT: Don't map CPU address +// ENABLE: Map CPU address +#define NVOS46_FLAGS_KERNEL_MAPPING 5:5 +#define NVOS46_FLAGS_KERNEL_MAPPING_NONE (0x00000000) +#define NVOS46_FLAGS_KERNEL_MAPPING_ENABLE (0x00000001) + +// +// Compute shader access control. +// GPUs that support this feature set the NV0080_CTRL_DMA_CAPS_SHADER_ACCESS_SUPPORTED +// property. These were first supported in Kepler. _DEFAULT will match the ACCESS field. +// +#define NVOS46_FLAGS_SHADER_ACCESS 7:6 +#define NVOS46_FLAGS_SHADER_ACCESS_DEFAULT (0x00000000) +#define NVOS46_FLAGS_SHADER_ACCESS_READ_ONLY (0x00000001) +#define NVOS46_FLAGS_SHADER_ACCESS_WRITE_ONLY (0x00000002) +#define NVOS46_FLAGS_SHADER_ACCESS_READ_WRITE (0x00000003) + +// +// How the PAGE_SIZE field is interpreted is architecture specific. +// +// On Curie chips it is ignored. +// +// On Tesla it is used to guide is used to select which type PDE +// to use. By default the RM will select 4KB for system memory +// and BIG (64KB) for video memory. BOTH is not supported. +// +// Likewise on Fermi this used to select the PDE type. Fermi cannot +// mix page sizes to a single mapping so the page size is determined +// at surface alloation time. 4KB or BIG may be specified but they +// must match the page size selected at allocation time. DEFAULT +// allows the RM to select either a single page size or both PDE, +// while BOTH forces the RM to select a dual page size PDE. +// +// BIG_PAGE = 64 KB on PASCAL +// = 64 KB or 128 KB on pre_PASCAL chips +// +// HUGE_PAGE = 2 MB on PASCAL +// = not supported on pre_PASCAL chips. +// +#define NVOS46_FLAGS_PAGE_SIZE 11:8 +#define NVOS46_FLAGS_PAGE_SIZE_DEFAULT (0x00000000) +#define NVOS46_FLAGS_PAGE_SIZE_4KB (0x00000001) +#define NVOS46_FLAGS_PAGE_SIZE_BIG (0x00000002) +#define NVOS46_FLAGS_PAGE_SIZE_BOTH (0x00000003) +#define NVOS46_FLAGS_PAGE_SIZE_HUGE (0x00000004) + +// Some systems allow the device to use the system L3 cache when accessing the +// system memory. For example, the iGPU on T19X can allocate from the system L3 +// provided the SoC L3 cache is configured for device allocation. +// +// NVOS46_FLAGS_SYSTEM_L3_ALLOC_DEFAULT - Use the default L3 allocation +// policy. When using this policy, device memory access will be coherent with +// non-snooping devices such as the display on Tegra. +// +// NVOS46_FLAGS_SYSTEM_L3_ALLOC_ENABLE_HINT - Enable L3 allocation if possible. +// When L3 allocation is enabled, device memory access may be cached, and the +// memory access will be coherent only with other snoop-enabled access. This +// flag is a hint and will be ignored if the system does not support L3 +// allocation for the device. NVOS46_FLAGS_CACHE_SNOOP_ENABLE must also be set +// for this flag to be effective. +// +// Note: This flag is implemented only by rmapi_tegra. It is not implemented by +// Resman. +// +#define NVOS46_FLAGS_SYSTEM_L3_ALLOC 13:13 +#define NVOS46_FLAGS_SYSTEM_L3_ALLOC_DEFAULT (0x00000000) +#define NVOS46_FLAGS_SYSTEM_L3_ALLOC_ENABLE_HINT (0x00000001) + +#define NVOS46_FLAGS_DMA_OFFSET_GROWS 14:14 +#define NVOS46_FLAGS_DMA_OFFSET_GROWS_UP (0x00000000) +#define NVOS46_FLAGS_DMA_OFFSET_GROWS_DOWN (0x00000001) + +// +// DMA_OFFSET_FIXED is overloaded for two purposes. +// +// 1. For CTXDMA mappings that use DMA_UNICAST_REUSE_ALLOC_FALSE, +// DMA_OFFSET_FIXED_TRUE indicates to use the dmaOffset parameter +// for a fixed address allocation out of the VA space heap. +// DMA_OFFSET_FIXED_FALSE indicates dmaOffset input will be ignored. +// +// 2. For CTXDMA mappings that use DMA_UNICAST_REUSE_ALLOC_TRUE and +// for *ALL* non-CTXDMA mappings, DMA_OFFSET_FIXED_TRUE indicates +// to treat the input dmaOffset as an absolute virtual address +// instead of an offset relative to the virtual allocation being +// mapped into. Whether relative or absolute, the resulting +// virtual address *must* be contained within the specified +// virtual allocation. +// +// Internally, it is also required that the virtual address be aligned +// to the page size of the mapping (obviously cannot map sub-pages). +// For client flexibility the physical offset does not require page alignment. +// This is handled by adding the physical misalignment +// (internally called pteAdjust) to the returned virtual address. +// The *input* dmaOffset can account for this pteAdjust (or not), +// but the returned virtual address always will. +// +#define NVOS46_FLAGS_DMA_OFFSET_FIXED 15:15 +#define NVOS46_FLAGS_DMA_OFFSET_FIXED_FALSE (0x00000000) +#define NVOS46_FLAGS_DMA_OFFSET_FIXED_TRUE (0x00000001) + +#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP 19:16 +#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_DEFAULT (0x00000000) +#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_1 (0x00000001) +#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_2 (0x00000002) +#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_4 (0x00000003) +#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_8 (0x00000004) +#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_16 (0x00000005) +#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_32 (0x00000006) +#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_64 (0x00000007) +#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_128 (0x00000008) +#define NVOS46_FLAGS_P2P 27:20 + +#define NVOS46_FLAGS_P2P_ENABLE 21:20 +#define NVOS46_FLAGS_P2P_ENABLE_NO (0x00000000) +#define NVOS46_FLAGS_P2P_ENABLE_YES (0x00000001) +#define NVOS46_FLAGS_P2P_ENABLE_NONE NVOS46_FLAGS_P2P_ENABLE_NO +#define NVOS46_FLAGS_P2P_ENABLE_SLI NVOS46_FLAGS_P2P_ENABLE_YES +#define NVOS46_FLAGS_P2P_ENABLE_NOSLI (0x00000002) +// Subdevice ID. Reserved 3 bits for the possibility of 8-way SLI +#define NVOS46_FLAGS_P2P_SUBDEVICE_ID 24:22 +#define NVOS46_FLAGS_P2P_SUBDEV_ID_SRC NVOS46_FLAGS_P2P_SUBDEVICE_ID +#define NVOS46_FLAGS_P2P_SUBDEV_ID_TGT 27:25 +#define NVOS46_FLAGS_TLB_LOCK 28:28 +#define NVOS46_FLAGS_TLB_LOCK_DISABLE (0x00000000) +#define NVOS46_FLAGS_TLB_LOCK_ENABLE (0x00000001) +#define NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC 29:29 +#define NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_FALSE (0x00000000) +#define NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_TRUE (0x00000001) +// +// This flag must be used with caution. Improper use can leave stale entries in the TLB, +// and allow access to memory no longer owned by the RM client or cause page faults. +// Also see corresponding flag for NvUnmapMemoryDma. +// +#define NVOS46_FLAGS_DEFER_TLB_INVALIDATION 31:31 +#define NVOS46_FLAGS_DEFER_TLB_INVALIDATION_FALSE (0x00000000) +#define NVOS46_FLAGS_DEFER_TLB_INVALIDATION_TRUE (0x00000001) + +/* parameters */ +typedef struct +{ + NvHandle hClient; // [IN] client handle + NvHandle hDevice; // [IN] device handle for mapping + NvHandle hDma; // [IN] dma handle for mapping + NvHandle hMemory; // [IN] memory handle for mapping + NvU64 offset NV_ALIGN_BYTES(8); // [IN] offset of region + NvU64 length NV_ALIGN_BYTES(8); // [IN] limit of region + NvV32 flags; // [IN] flags + NvU64 dmaOffset NV_ALIGN_BYTES(8); // [OUT] offset of mapping + // [IN] if FLAGS_DMA_OFFSET_FIXED_TRUE + // *OR* hDma is NOT a CTXDMA handle + // (see NVOS46_FLAGS_DMA_OFFSET_FIXED) + NvV32 status; // [OUT] status +} NVOS46_PARAMETERS; + + +/* function OS47 */ +#define NV04_UNMAP_MEMORY_DMA (0x0000002F) + +#define NVOS47_FLAGS_DEFER_TLB_INVALIDATION 0:0 +#define NVOS47_FLAGS_DEFER_TLB_INVALIDATION_FALSE (0x00000000) +#define NVOS47_FLAGS_DEFER_TLB_INVALIDATION_TRUE (0x00000001) + +/* parameters */ +typedef struct +{ + NvHandle hClient; // [IN] client handle + NvHandle hDevice; // [IN] device handle for mapping + NvHandle hDma; // [IN] dma handle for mapping + NvHandle hMemory; // [IN] memory handle for mapping + NvV32 flags; // [IN] flags + NvU64 dmaOffset NV_ALIGN_BYTES(8); // [IN] dma offset from NV04_MAP_MEMORY_DMA + NvV32 status; // [OUT] status +} NVOS47_PARAMETERS; + + +#define NV04_BIND_CONTEXT_DMA (0x00000031) +/* parameters */ +typedef struct +{ + NvHandle hClient; // [IN] client handle + NvHandle hChannel; // [IN] channel handle for binding + NvHandle hCtxDma; // [IN] ctx dma handle for binding + NvV32 status; // [OUT] status +} NVOS49_PARAMETERS; + + +/* function OS54 */ +#define NV04_CONTROL (0x00000036) + +#define NVOS54_FLAGS_NONE (0x00000000) +#define NVOS54_FLAGS_IRQL_RAISED (0x00000001) +#define NVOS54_FLAGS_LOCK_BYPASS (0x00000002) +#define NVOS54_FLAGS_FINN_SERIALIZED (0x00000004) + +/* parameters */ +typedef struct +{ + NvHandle hClient; + NvHandle hObject; + NvV32 cmd; + NvU32 flags; + NvP64 params NV_ALIGN_BYTES(8); + NvU32 paramsSize; + NvV32 status; +} NVOS54_PARAMETERS; + +/* RM Control header + * + * Replacement for NVOS54_PARAMETERS where embedded pointers are not allowed. + * Input layout for user space RM Control calls should be: + * + * +--- NVOS63_PARAMETERS ---+--- RM Control parameters ---+ + * + * NVOS63_PARAMETERS::paramsSize is the size of RM Control parameters + * + */ +typedef struct +{ + NvHandle hClient; // [IN] client handle + NvHandle hObject; // [IN] object handle + NvV32 cmd; // [IN] control command ID + NvU32 paramsSize; // [IN] size in bytes of the RM Control parameters + NvV32 status; // [OUT] status +} NVOS63_PARAMETERS; + + +/* function OS55 */ +#define NV04_DUP_OBJECT (0x00000037) + +/* parameters */ +typedef struct +{ + NvHandle hClient; // [IN] destination client handle + NvHandle hParent; // [IN] parent of new object + NvHandle hObject; // [INOUT] destination (new) object handle + NvHandle hClientSrc; // [IN] source client handle + NvHandle hObjectSrc; // [IN] source (old) object handle + NvU32 flags; // [IN] flags + NvU32 status; // [OUT] status +} NVOS55_PARAMETERS; + +#define NV04_DUP_HANDLE_FLAGS_NONE (0x00000000) +#define NV04_DUP_HANDLE_FLAGS_REJECT_KERNEL_DUP_PRIVILEGE (0x00000001) // If set, prevents an RM kernel client from duping unconditionally + // NOTE: Do not declare a NV04_DUP_HANDLE_FLAGS_* value of 0x00000008 + // until Bug 2859347 is resolved! This is due to conflicting usage + // of RS_RES_DUP_PARAMS_INTERNAL.flags to pass + // NVOS32_ALLOC_INTERNAL_FLAGS_FLA_MEMORY to an object constructor. + +/* function OS56 */ +#define NV04_UPDATE_DEVICE_MAPPING_INFO (0x00000038) + +/* parameters */ +typedef struct +{ + NvHandle hClient; + NvHandle hDevice; + NvHandle hMemory; + NvP64 pOldCpuAddress NV_ALIGN_BYTES(8); + NvP64 pNewCpuAddress NV_ALIGN_BYTES(8); + NvV32 status; +} NVOS56_PARAMETERS; + +/* function OS57 */ +#define NV04_SHARE (0x0000003E) + +/* parameters */ +typedef struct +{ + NvHandle hClient; // [IN] owner client handle + NvHandle hObject; // [IN] resource to share + RS_SHARE_POLICY sharePolicy; // [IN] share policy entry + NvU32 status; // [OUT] status +} NVOS57_PARAMETERS; + +/* parameters */ +typedef struct +{ + NvU32 deviceReference; + NvU32 head; + NvU32 state; + NvU8 forceMonitorState; + NvU8 bForcePerfBiosLevel; + NvU8 bIsD3HotTransition; // [OUT] To tell client if it's a D3Hot transition + NvU32 fastBootPowerState; +} NVPOWERSTATE_PARAMETERS, *PNVPOWERSTATE_PARAMETERS; + + /***************************************************************************\ +|* Object Allocation Parameters *| + \***************************************************************************/ + +// GR engine creation parameters +typedef struct { + NvU32 version; // set to 0x2 + NvU32 flags; // input param from a rm client (no flags are currently defined) + NvU32 size; // sizeof(NV_GR_ALLOCATION_PARAMETERS) + NvU32 caps; // output param for a rm client - class dependent +} NV_GR_ALLOCATION_PARAMETERS; + +// +// NvAlloc parameters for NV03_DEVICE_XX class +// hClientShare +// For NV50+ this can be set to virtual address space for this +// device. On previous chips this field is ignored. There are +// three possible settings +// NV01_NULL_OBJECT - Use the default global VA space +// Handle to current client - Create a new private address space +// Handle to another client - Attach to other clients address space +// flags +// MAP_PTE_GLOBALLY Deprecated. +// MINIMIZE_PTETABLE_SIZE Pass hint to DMA HAL to use partial page +// tables. Depending on allocation pattern +// this may actually use more instance memory. +// RETRY_PTE_ALLOC_IN_SYS Fallback to PTEs allocation in sysmem. This +// is now enabled by default. +// VASPACE_SIZE Honor vaSpaceSize field. +// +// MAP_PTE Deprecated. +// +// VASPACE_IS_MIRRORED This flag will tell RM to create a mirrored +// kernel PDB for the address space associated +// with this device. When this flag is set +// the address space covered by the top PDE +// is restricted and cannot be allocated out of. +// +// +// VASPACE_BIG_PAGE_SIZE_64k ***Warning this flag will be deprecated do not use***** +// VASPACE_BIG_PAGE_SIZE_128k This flag will choose the big page size of the VASPace +// to 64K/128k if the system supports a configurable size. +// If the system does not support a configurable size then +// defaults will be chosen. +// If the user sets both these bits then this API will fail. +// +// SHARED_MANAGEMENT +// *** Warning: This will be deprecated - see NV_VASPACE_ALLOCATION_PARAMETERS. *** +// +// +// hTargetClient/hTargetDevice +// Deprecated. Can be deleted once client code has removed references. +// +// vaBase +// *** Warning: This will be deprecated - see NV_VASPACE_ALLOCATION_PARAMETERS. *** +// +// vaSpaceSize +// Set the size of the VA space used for this client if allocating +// a new private address space. Is expressed as a size such as +// (1<<32) for a 32b address space. Reducing the size of the address +// space allows the dma chip specific code to reduce the instance memory +// used for page tables. +// +// vaMode +// The vaspace allocation mode. There are three modes supported: +// 1. SINGLE_VASPACE +// An old abstraction that provides a single VA space under a +// device and it's allocated implicityly when an object requires a VA +// space. Typically, this VA space is also shared across clients. +// +// 2. OPTIONAL_MULTIPLE_VASPACES +// Global + multiple private va spaces. In this mode, the old abstraction, +// a single vaspace under a device that is allocated implicitly is still +// being supported. A private VA space is an entity under a device, which/ +// cannot be shared with other clients, but multiple channels under the +// same device can still share a private VA space. +// Private VA spaces (class:90f1,FERMI_VASPACE_A) can be allocated as +// objects through RM APIs. This mode requires the users to know what they +// are doing in terms of using VA spaces. Page fault can easily occur if +// one is not careful with a mixed of an implicit VA space and multiple +// VA spaces. +// +// 3. MULTIPLE_VASPACES +// In this mode, all VA spaces have to be allocated explicitly through RM +// APIs and users have to specify which VA space to use for each object. +// This case prevents users to use context dma, which is not supported and +// can be misleading if used. Therefore, it's more a safeguard mode to +// prevent people making mistakes that are hard to debug. +// +// DEFAULT MODE: 2. OPTIONAL_MULTIPLE_VASPACES +// +// See NV0080_ALLOC_PARAMETERS for allocation parameter structure. +// + +#define NV_DEVICE_ALLOCATION_SZNAME_MAXLEN 128 +#define NV_DEVICE_ALLOCATION_FLAGS_NONE (0x00000000) +#define NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE_GLOBALLY (0x00000001) +#define NV_DEVICE_ALLOCATION_FLAGS_MINIMIZE_PTETABLE_SIZE (0x00000002) +#define NV_DEVICE_ALLOCATION_FLAGS_RETRY_PTE_ALLOC_IN_SYS (0x00000004) +#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SIZE (0x00000008) +#define NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE (0x00000010) +#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_IS_TARGET (0x00000020) +#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SHARED_MANAGEMENT (0x00000100) +#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_64k (0x00000200) +#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_128k (0x00000400) +#define NV_DEVICE_ALLOCATION_FLAGS_RESTRICT_RESERVED_VALIMITS (0x00000800) + +/* + *TODO: Delete this flag once CUDA moves to the ctrl call + */ +#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_IS_MIRRORED (0x00000040) + +// XXX NV_DEVICE_ALLOCATION_FLAGS_VASPACE_PTABLE_PMA_MANAGED should not +// should not be exposed to clients. It should be the default RM +// behavior. +// +// Until it is made the default, certain clients such as OpenGL +// might still need PTABLE allocations to go through PMA, so this +// flag has been temporary exposed. +// +// See bug 1880192 +#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_PTABLE_PMA_MANAGED (0x00001000) + +// +// Indicates this device is being created by guest and requires a +// KernelHostVgpuDeviceApi creation in client. +// +#define NV_DEVICE_ALLOCATION_FLAGS_HOST_VGPU_DEVICE (0x00002000) + +// +// Indicates this device is being created for VGPU plugin use. +// Requires a HostVgpuDevice handle to indicate the guest on which +// this plugin operates. +// +#define NV_DEVICE_ALLOCATION_FLAGS_PLUGIN_CONTEXT (0x00004000) + +// +// For clients using unlinked SLI to catch allocations attempts on secondary GPUs +// not accompanied by a fixed offset. +// +#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_REQUIRE_FIXED_OFFSET (0x00008000) + +#define NV_DEVICE_ALLOCATION_VAMODE_OPTIONAL_MULTIPLE_VASPACES (0x00000000) +#define NV_DEVICE_ALLOCATION_VAMODE_SINGLE_VASPACE (0x00000001) +#define NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES (0x00000002) + + +#define NV_CHANNELGPFIFO_NOTIFICATION_TYPE_ERROR 0x00000000 +#define NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN 0x00000001 +#define NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1 2 +#define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_VALUE 14:0 +#define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS 15:15 +#define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_TRUE 0x1 +#define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_FALSE 0x0 + +typedef struct +{ + NvV32 channelInstance; // One of the n channel instances of a given channel type. + // Note that core channel has only one instance + // while all others have two (one per head). + NvHandle hObjectBuffer; // ctx dma handle for DMA push buffer + NvHandle hObjectNotify; // ctx dma handle for an area (of type NvNotification defined in sdk/nvidia/inc/nvtypes.h) where RM can write errors/notifications + NvU32 offset; // Initial offset for put/get, usually zero. + NvP64 pControl NV_ALIGN_BYTES(8); // pControl gives virt addr of UDISP GET/PUT regs + + NvU32 flags; +#define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB 1:1 +#define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_YES 0x00000000 +#define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_NO 0x00000001 + +} NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS; + +typedef struct +{ + NvV32 channelInstance; // One of the n channel instances of a given channel type. + // All PIO channels have two instances (one per head). + NvHandle hObjectNotify; // ctx dma handle for an area (of type NvNotification defined in sdk/nvidia/inc/nvtypes.h) where RM can write errors. + NvP64 pControl NV_ALIGN_BYTES(8); // pControl gives virt addr of control region for PIO channel +} NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS; + +// Used for allocating a channel group +typedef struct +{ + NvHandle hObjectError; // Error notifier for TSG + NvHandle hObjectEccError; // ECC Error notifier for TSG + NvHandle hVASpace; // VA space handle for TSG + NvU32 engineType; // Engine to which all channels in this TSG are associated with + NvBool bIsCallingContextVgpuPlugin; +} NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS; + +/* +* @params: +* @engineId : Engine to which the software runlist be associated with. +* @maxTSGs : Maximum number of TSG entries that will be submitted in this software runlist +* The size of the runlist buffer will be determined by +* 2 * // double buffer +* maxTSGs * // determined by KMD +* maxChannelPerTSG * // Determined by RM +* sizeof(RunlistEntry) // Determined by HW format +* @qosIntrEnableMask: QOS Interrupt bitmask that needs to be enabled for the SW runlist defined below. +*/ +typedef struct +{ + NvU32 engineId; //(IN) + NvU32 maxTSGs; //(IN) // Size of the RM could return error if the request cannot be accommodated. + NvU32 qosIntrEnableMask; //(IN) // Bitmask for QOS interrupts that needs to be enabled +} NV_SWRUNLIST_ALLOCATION_PARAMS; + +#define NV_SWRUNLIST_QOS_INTR_NONE 0x00000000 +#define NV_SWRUNLIST_QOS_INTR_RUNLIST_AND_ENG_IDLE_ENABLE NVBIT32(0) +#define NV_SWRUNLIST_QOS_INTR_RUNLIST_IDLE_ENABLE NVBIT32(1) +#define NV_SWRUNLIST_QOS_INTR_RUNLIST_ACQUIRE_ENABLE NVBIT32(2) +#define NV_SWRUNLIST_QOS_INTR_RUNLIST_ACQUIRE_AND_ENG_IDLE_ENABLE NVBIT32(3) + +typedef struct +{ + NvU32 size; + NvU32 caps; +} NV_ME_ALLOCATION_PARAMETERS; + +typedef struct +{ + NvU32 size; + NvU32 prohibitMultipleInstances; + NvU32 engineInstance; // Select NVDEC0 or NVDEC1 or NVDEC2 +} NV_BSP_ALLOCATION_PARAMETERS; + +// +// These are referenced by mdiag mods tests, but do not appear to be used during +// in the RM any longer +// +#define NV_VP_ALLOCATION_FLAGS_STANDARD_UCODE (0x00000000) +#define NV_VP_ALLOCATION_FLAGS_STATIC_UCODE (0x00000001) +#define NV_VP_ALLOCATION_FLAGS_DYNAMIC_UCODE (0x00000002) + +// +// NV_VP_ALLOCATION_PARAMETERS.flags +// +// NV_VP_ALLOCATION_FLAGS_AVP_CLIENT are used by Tegra to specify if +// the current allocation with be used by Video or Audio +// +#define NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_VIDEO (0x00000000) +#define NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_AUDIO (0x00000001) + +typedef struct +{ + NvU32 size; + NvU32 caps; + NvU32 flags; + NvU32 altUcode; + NvP64 rawUcode NV_ALIGN_BYTES(8); + NvU32 rawUcodeSize; + NvU32 numSubClasses; + NvU32 numSubSets; + NvP64 subClasses NV_ALIGN_BYTES(8); + NvU32 prohibitMultipleInstances; + NvP64 pControl NV_ALIGN_BYTES(8); // Used by Tegra to return a mapping to NvE276Control + NvHandle hMemoryCmdBuffer NV_ALIGN_BYTES(8); // Used by Tegra to specify cmd buffer + NvU64 offset NV_ALIGN_BYTES(8); // Used by Tegra to specify an offset into the cmd buffer + +} NV_VP_ALLOCATION_PARAMETERS; + +typedef struct +{ + NvU32 size; + NvU32 prohibitMultipleInstances; +} NV_PPP_ALLOCATION_PARAMETERS; + +typedef struct +{ + NvU32 size; + NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of MSENC? + NvU32 engineInstance; // Select MSENC/NVENC0 or NVENC1 or NVENC2 +} NV_MSENC_ALLOCATION_PARAMETERS; + +typedef struct +{ + NvU32 size; + NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of SEC2? +} NV_SEC2_ALLOCATION_PARAMETERS; + +typedef struct +{ + NvU32 size; + NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of NVJPG? + NvU32 engineInstance; +} NV_NVJPG_ALLOCATION_PARAMETERS; + +typedef struct +{ + NvU32 size; + NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of OFA? +} NV_OFA_ALLOCATION_PARAMETERS; + +#define NV04_ADD_VBLANK_CALLBACK (0x0000003D) + +#include "class/cl9010.h" // for OSVBLANKCALLBACKPROC + +/* parameters */ +/* NOTE: the "void* pParm's" below are ok (but unfortunate) since this interface + can only be used by other kernel drivers which must share the same ptr-size */ +typedef struct +{ + NvHandle hClient; // [IN] client handle + NvHandle hDevice; // [IN] device handle for mapping + NvHandle hVblank; // [IN] Vblank handle for control + OSVBLANKCALLBACKPROC pProc; // Routine to call at vblank time + + NvV32 LogicalHead; // Logical Head + void *pParm1; + void *pParm2; + NvU32 bAdd; // Add or Delete + NvV32 status; // [OUT] status +} NVOS61_PARAMETERS; + +/** + * @brief NvAlloc parameters for VASPACE classes + * + * Used to create a new private virtual address space. + * + * index + * Tegra: With TEGRA_VASPACE_A, index specifies the IOMMU + * virtual address space to be created. Based on the + * index, RM/NVMEM will decide the HW ASID to be used with + * this VA Space. "index" takes values from the + * NVMEM_CLIENT_* defines in + * "drivers/common/inc/tegra/memory/ioctl.h". + * + * Big GPU: With FERMI_VASPACE_A, see NV_VASPACE_ALLOCATION_INDEX_GPU_*. + * + * flags + * MINIMIZE_PTETABLE_SIZE Pass hint to DMA HAL to use partial page tables. + * Depending on allocation pattern this may actually + * use more instance memory. + * + * RETRY_PTE_ALLOC_IN_SYS Fallback to PTEs allocation in sysmem. This is now + * enabled by default. + * + * SHARED_MANAGEMENT + * Indicates management of the VA space is shared with another + * component (e.g. driver layer, OS, etc.). + * + * The initial VA range from vaBase (inclusive) through vaSize (exclusive) + * is managed by RM. The range must be aligned to a top-level PDE's VA + * coverage since backing page table levels for this range are managed by RM. + * All normal RM virtual memory management APIs work within this range. + * + * An external component can manage the remaining VA ranges, + * from 0 (inclusive) to vaBase (exclusive) and from vaSize (inclusive) up to the + * maximum VA limit supported by HW. + * Management of these ranges includes VA sub-allocation and the + * backing lower page table levels. + * + * The top-level page directory is special since it is a shared resource. + * Management of the page directory is as follows: + * 1. Initially RM allocates a page directory for RM-managed PDEs. + * 2. The external component may create a full page directory and commit it + * with NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY. + * This will copy the RM-managed PDEs from the RM-managed page directory + * into the external page directory and commit channels to the external page directory. + * After this point RM will update the external page directory directly for + * operations that modify RM-managed PDEs. + * 3. The external component may use NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY repeatedly + * if it needs to update the page directory again (e.g. to resize or migrate). + * This will copy the RM-managed PDEs from the old external page directory + * into the new external page directory and commit channels to the new page directory. + * 4. The external component may restore management of the page directory back to + * RM with NV0080_CTRL_CMD_DMA_UNSET_PAGE_DIRECTORY. + * This will copy the RM-managed PDEs from the external page directory + * into the RM-managed page directory and commit channels to the RM-managed page directory. + * After this point RM will update the RM-managed page directory for + * operations that modify RM-managed PDEs. + * Note that operations (2) and (4) are symmetric - the RM perspective of management is identical + * before and after a sequence of SET => ... => UNSET. + * + * IS_MIRRORED + * This flag will tell RM to create a mirrored + * kernel PDB for the address space associated + * with this device. When this flag is set + * the address space covered by the top PDE + * is restricted and cannot be allocated out of. + * ENABLE_PAGE_FAULTING + * Enable page faulting if the architecture supports it. + * As of now page faulting is only supported for compute on pascal+. + * IS_EXTERNALLY_OWNED + * This vaspace that has been allocated will be managed by + * an external driver. RM will not own the pagetables for this vaspace. + * + * ENABLE_NVLINK_ATS + * Enables VA translation for this address space using NVLINK ATS. + * Note, the GMMU page tables still exist and take priority over NVLINK ATS. + * VA space object creation will fail if: + * - hardware support is not available (NV_ERR_NOT_SUPPORTED) + * - incompatible options IS_MIRRORED or IS_EXTERNALLY_OWNED are set (NV_ERR_INVALID_ARGUMENT) + * IS_FLA + * Sets FLA flag for this VASPACE + * + * ALLOW_ZERO_ADDRESS + * Allows VASPACE Range to start from zero + * SKIP_SCRUB_MEMPOOL + * Skip scrubbing in MemPool + * + * vaBase [in, out] + * On input, the lowest usable base address of the VA space. + * If 0, RM will pick a default value - 0 is always reserved to respresent NULL pointers. + * The value must be aligned to the largest page size of the VA space. + * Larger values aid in debug since offsets added to NULL pointers will still fault. + * + * On output, the actual usable base address is returned. + * + * vaSize [in,out] + * On input, requested size of the virtual address space in bytes. + * Requesting a smaller size reduces the memory required for the initial + * page directory, but the VAS may be resized later (NV0080_CTRL_DMA_SET_VA_SPACE_SIZE). + * If 0, the default VA space size will be used. + * + * On output, the actual size of the VAS in bytes. + * NOTE: This corresponds to the VA_LIMIT + 1, so the usable size is (vaSize - vaBase). + * + * bigPageSIze + * Set the size of the big page in this address space object. Current HW supports + * either 64k or 128k as the size of the big page. HW that support multiple big + * page size per address space will use this size. Hw that do not support this feature + * will override to the default big page size that is supported by the system. + * If the big page size value is set to ZERO then we will pick the default page size + * of the system. + **/ +typedef struct +{ + NvU32 index; + NvV32 flags; + NvU64 vaSize NV_ALIGN_BYTES(8); + NvU64 vaStartInternal NV_ALIGN_BYTES(8); + NvU64 vaLimitInternal NV_ALIGN_BYTES(8); + NvU32 bigPageSize; + NvU64 vaBase NV_ALIGN_BYTES(8); +} NV_VASPACE_ALLOCATION_PARAMETERS; + +#define NV_VASPACE_ALLOCATION_FLAGS_NONE (0x00000000) +#define NV_VASPACE_ALLOCATION_FLAGS_MINIMIZE_PTETABLE_SIZE BIT(0) +#define NV_VASPACE_ALLOCATION_FLAGS_RETRY_PTE_ALLOC_IN_SYS BIT(1) +#define NV_VASPACE_ALLOCATION_FLAGS_SHARED_MANAGEMENT BIT(2) +#define NV_VASPACE_ALLOCATION_FLAGS_IS_EXTERNALLY_OWNED BIT(3) +#define NV_VASPACE_ALLOCATION_FLAGS_ENABLE_NVLINK_ATS BIT(4) +#define NV_VASPACE_ALLOCATION_FLAGS_IS_MIRRORED BIT(5) +#define NV_VASPACE_ALLOCATION_FLAGS_ENABLE_PAGE_FAULTING BIT(6) +#define NV_VASPACE_ALLOCATION_FLAGS_VA_INTERNAL_LIMIT BIT(7) +#define NV_VASPACE_ALLOCATION_FLAGS_ALLOW_ZERO_ADDRESS BIT(8) +#define NV_VASPACE_ALLOCATION_FLAGS_IS_FLA BIT(9) +#define NV_VASPACE_ALLOCATION_FLAGS_SKIP_SCRUB_MEMPOOL BIT(10) +#define NV_VASPACE_ALLOCATION_FLAGS_OPTIMIZE_PTETABLE_MEMPOOL_USAGE BIT(11) +#define NV_VASPACE_ALLOCATION_FLAGS_REQUIRE_FIXED_OFFSET BIT(12) + +#define NV_VASPACE_ALLOCATION_INDEX_GPU_NEW 0x00 // NV_STATUS_LEVEL_WARN + * to determine success v. failure of a call. + */ +#define NV_STATUS_LEVEL_WARN 1 + +/*! + * @def NV_STATUS_LEVEL_ERR + * @see NV_STATUS_LEVEL + * @brief Unrecoverable error condition + */ +#define NV_STATUS_LEVEL_ERR 3 + +/*! + * @def NV_STATUS_LEVEL + * @see NV_STATUS_LEVEL_OK + * @see NV_STATUS_LEVEL_WARN + * @see NV_STATUS_LEVEL_ERR + * @brief Level of the status code + * + * @warning IMPORTANT: When comparing NV_STATUS_LEVEL(_S) against one of + * these constants, it is important to use '<=' or '>' (rather + * than '<' or '>='). + * + * For example. do: + * if (NV_STATUS_LEVEL(status) <= NV_STATUS_LEVEL_WARN) + * rather than: + * if (NV_STATUS_LEVEL(status) < NV_STATUS_LEVEL_ERR) + * + * By being consistent in this manner, it is easier to systematically + * add additional level constants. New levels are likely to lower + * (rather than raise) the severity of _ERR codes. For example, + * if we were to add NV_STATUS_LEVEL_RETRY to indicate hardware + * failures that may be recoverable (e.g. RM_ERR_TIMEOUT_RETRY + * or RM_ERR_BUSY_RETRY), it would be less severe than + * NV_STATUS_LEVEL_ERR the level to which these status codes now + * belong. Using '<=' and '>' ensures your code is not broken in + * cases like this. + */ +#define NV_STATUS_LEVEL(_S) \ + ((_S) == NV_OK? NV_STATUS_LEVEL_OK: \ + ((_S) != NV_ERR_GENERIC && (_S) & 0x00010000? NV_STATUS_LEVEL_WARN: \ + NV_STATUS_LEVEL_ERR)) + +/*! + * @def NV_STATUS_LEVEL + * @see NV_STATUS_LEVEL_OK + * @see NV_STATUS_LEVEL_WARN + * @see NV_STATUS_LEVEL_ERR + * @brief Character representing status code level + */ +#define NV_STATUS_LEVEL_CHAR(_S) \ + ((_S) == NV_OK? '0': \ + ((_S) != NV_ERR_GENERIC && (_S) & 0x00010000? 'W': \ + 'E')) + +// Function definitions +const char *nvstatusToString(NV_STATUS nvStatusIn); + +#ifdef __cplusplus +} +#endif + +#endif /* SDK_NVSTATUS_H */ diff --git a/userspace/sdks/nv525/nvidia/inc/nvstatuscodes.h b/userspace/sdks/nv525/nvidia/inc/nvstatuscodes.h new file mode 100644 index 0000000..517a8ce --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/nvstatuscodes.h @@ -0,0 +1,163 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef SDK_NVSTATUSCODES_H +#define SDK_NVSTATUSCODES_H + +NV_STATUS_CODE(NV_OK, 0x00000000, "Success") +NV_STATUS_CODE(NV_ERR_GENERIC, 0x0000FFFF, "Failure: Generic Error") + +NV_STATUS_CODE(NV_ERR_BROKEN_FB, 0x00000001, "Frame-Buffer broken") +NV_STATUS_CODE(NV_ERR_BUFFER_TOO_SMALL, 0x00000002, "Buffer passed in is too small") +NV_STATUS_CODE(NV_ERR_BUSY_RETRY, 0x00000003, "System is busy, retry later") +NV_STATUS_CODE(NV_ERR_CALLBACK_NOT_SCHEDULED, 0x00000004, "The requested callback API not scheduled") +NV_STATUS_CODE(NV_ERR_CARD_NOT_PRESENT, 0x00000005, "Card not detected") +NV_STATUS_CODE(NV_ERR_CYCLE_DETECTED, 0x00000006, "Call cycle detected") +NV_STATUS_CODE(NV_ERR_DMA_IN_USE, 0x00000007, "Requested DMA is in use") +NV_STATUS_CODE(NV_ERR_DMA_MEM_NOT_LOCKED, 0x00000008, "Requested DMA memory is not locked") +NV_STATUS_CODE(NV_ERR_DMA_MEM_NOT_UNLOCKED, 0x00000009, "Requested DMA memory is not unlocked") +NV_STATUS_CODE(NV_ERR_DUAL_LINK_INUSE, 0x0000000A, "Dual-Link is in use") +NV_STATUS_CODE(NV_ERR_ECC_ERROR, 0x0000000B, "Generic ECC error") +NV_STATUS_CODE(NV_ERR_FIFO_BAD_ACCESS, 0x0000000C, "FIFO: Invalid access") +NV_STATUS_CODE(NV_ERR_FREQ_NOT_SUPPORTED, 0x0000000D, "Requested frequency is not supported") +NV_STATUS_CODE(NV_ERR_GPU_DMA_NOT_INITIALIZED, 0x0000000E, "Requested DMA not initialized") +NV_STATUS_CODE(NV_ERR_GPU_IS_LOST, 0x0000000F, "GPU lost from the bus") +NV_STATUS_CODE(NV_ERR_GPU_IN_FULLCHIP_RESET, 0x00000010, "GPU currently in full-chip reset") +NV_STATUS_CODE(NV_ERR_GPU_NOT_FULL_POWER, 0x00000011, "GPU not in full power") +NV_STATUS_CODE(NV_ERR_GPU_UUID_NOT_FOUND, 0x00000012, "GPU UUID not found") +NV_STATUS_CODE(NV_ERR_HOT_SWITCH, 0x00000013, "System in hot switch") +NV_STATUS_CODE(NV_ERR_I2C_ERROR, 0x00000014, "I2C Error") +NV_STATUS_CODE(NV_ERR_I2C_SPEED_TOO_HIGH, 0x00000015, "I2C Error: Speed too high") +NV_STATUS_CODE(NV_ERR_ILLEGAL_ACTION, 0x00000016, "Current action is not allowed") +NV_STATUS_CODE(NV_ERR_IN_USE, 0x00000017, "Generic busy error") +NV_STATUS_CODE(NV_ERR_INFLATE_COMPRESSED_DATA_FAILED, 0x00000018, "Failed to inflate compressed data") +NV_STATUS_CODE(NV_ERR_INSERT_DUPLICATE_NAME, 0x00000019, "Found a duplicate entry in the requested btree") +NV_STATUS_CODE(NV_ERR_INSUFFICIENT_RESOURCES, 0x0000001A, "Ran out of a critical resource, other than memory") +NV_STATUS_CODE(NV_ERR_INSUFFICIENT_PERMISSIONS, 0x0000001B, "The requester does not have sufficient permissions") +NV_STATUS_CODE(NV_ERR_INSUFFICIENT_POWER, 0x0000001C, "Generic Error: Low power") +NV_STATUS_CODE(NV_ERR_INVALID_ACCESS_TYPE, 0x0000001D, "This type of access is not allowed") +NV_STATUS_CODE(NV_ERR_INVALID_ADDRESS, 0x0000001E, "Address not valid") +NV_STATUS_CODE(NV_ERR_INVALID_ARGUMENT, 0x0000001F, "Invalid argument to call") +NV_STATUS_CODE(NV_ERR_INVALID_BASE, 0x00000020, "Invalid base") +NV_STATUS_CODE(NV_ERR_INVALID_CHANNEL, 0x00000021, "Given channel-id not valid") +NV_STATUS_CODE(NV_ERR_INVALID_CLASS, 0x00000022, "Given class-id not valid") +NV_STATUS_CODE(NV_ERR_INVALID_CLIENT, 0x00000023, "Given client not valid") +NV_STATUS_CODE(NV_ERR_INVALID_COMMAND, 0x00000024, "Command passed is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_DATA, 0x00000025, "Invalid data passed") +NV_STATUS_CODE(NV_ERR_INVALID_DEVICE, 0x00000026, "Current device is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_DMA_SPECIFIER, 0x00000027, "The requested DMA specifier is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_EVENT, 0x00000028, "Invalid event occurred") +NV_STATUS_CODE(NV_ERR_INVALID_FLAGS, 0x00000029, "Invalid flags passed") +NV_STATUS_CODE(NV_ERR_INVALID_FUNCTION, 0x0000002A, "Called function is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_HEAP, 0x0000002B, "Heap corrupted") +NV_STATUS_CODE(NV_ERR_INVALID_INDEX, 0x0000002C, "Index invalid") +NV_STATUS_CODE(NV_ERR_INVALID_IRQ_LEVEL, 0x0000002D, "Requested IRQ level is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_LIMIT, 0x0000002E, "Generic Error: Invalid limit") +NV_STATUS_CODE(NV_ERR_INVALID_LOCK_STATE, 0x0000002F, "Requested lock state not valid") +NV_STATUS_CODE(NV_ERR_INVALID_METHOD, 0x00000030, "Requested method not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OBJECT, 0x00000031, "Object not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_BUFFER, 0x00000032, "Object buffer passed is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_HANDLE, 0x00000033, "Object handle is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_NEW, 0x00000034, "New object is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_OLD, 0x00000035, "Old object is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_PARENT, 0x00000036, "Object parent is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OFFSET, 0x00000037, "The offset passed is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OPERATION, 0x00000038, "Requested operation is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OWNER, 0x00000039, "Owner not valid") +NV_STATUS_CODE(NV_ERR_INVALID_PARAM_STRUCT, 0x0000003A, "Invalid structure parameter") +NV_STATUS_CODE(NV_ERR_INVALID_PARAMETER, 0x0000003B, "At least one of the parameters passed is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_PATH, 0x0000003C, "The requested path is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_POINTER, 0x0000003D, "Pointer not valid") +NV_STATUS_CODE(NV_ERR_INVALID_REGISTRY_KEY, 0x0000003E, "Found an invalid registry key") +NV_STATUS_CODE(NV_ERR_INVALID_REQUEST, 0x0000003F, "Generic Error: Invalid request") +NV_STATUS_CODE(NV_ERR_INVALID_STATE, 0x00000040, "Generic Error: Invalid state") +NV_STATUS_CODE(NV_ERR_INVALID_STRING_LENGTH, 0x00000041, "The string length is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_READ, 0x00000042, "The requested read operation is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_WRITE, 0x00000043, "The requested write operation is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_XLATE, 0x00000044, "The requested translate operation is not valid") +NV_STATUS_CODE(NV_ERR_IRQ_NOT_FIRING, 0x00000045, "Requested IRQ is not firing") +NV_STATUS_CODE(NV_ERR_IRQ_EDGE_TRIGGERED, 0x00000046, "IRQ is edge triggered") +NV_STATUS_CODE(NV_ERR_MEMORY_TRAINING_FAILED, 0x00000047, "Failed memory training sequence") +NV_STATUS_CODE(NV_ERR_MISMATCHED_SLAVE, 0x00000048, "Slave mismatch") +NV_STATUS_CODE(NV_ERR_MISMATCHED_TARGET, 0x00000049, "Target mismatch") +NV_STATUS_CODE(NV_ERR_MISSING_TABLE_ENTRY, 0x0000004A, "Requested entry missing not found in the table") +NV_STATUS_CODE(NV_ERR_MODULE_LOAD_FAILED, 0x0000004B, "Failed to load the requested module") +NV_STATUS_CODE(NV_ERR_MORE_DATA_AVAILABLE, 0x0000004C, "There is more data available") +NV_STATUS_CODE(NV_ERR_MORE_PROCESSING_REQUIRED, 0x0000004D, "More processing required for the given call") +NV_STATUS_CODE(NV_ERR_MULTIPLE_MEMORY_TYPES, 0x0000004E, "Multiple memory types found") +NV_STATUS_CODE(NV_ERR_NO_FREE_FIFOS, 0x0000004F, "No more free FIFOs found") +NV_STATUS_CODE(NV_ERR_NO_INTR_PENDING, 0x00000050, "No interrupt pending") +NV_STATUS_CODE(NV_ERR_NO_MEMORY, 0x00000051, "Out of memory") +NV_STATUS_CODE(NV_ERR_NO_SUCH_DOMAIN, 0x00000052, "Requested domain does not exist") +NV_STATUS_CODE(NV_ERR_NO_VALID_PATH, 0x00000053, "Caller did not specify a valid path") +NV_STATUS_CODE(NV_ERR_NOT_COMPATIBLE, 0x00000054, "Generic Error: Incompatible types") +NV_STATUS_CODE(NV_ERR_NOT_READY, 0x00000055, "Generic Error: Not ready") +NV_STATUS_CODE(NV_ERR_NOT_SUPPORTED, 0x00000056, "Call not supported") +NV_STATUS_CODE(NV_ERR_OBJECT_NOT_FOUND, 0x00000057, "Requested object not found") +NV_STATUS_CODE(NV_ERR_OBJECT_TYPE_MISMATCH, 0x00000058, "Specified objects do not match") +NV_STATUS_CODE(NV_ERR_OPERATING_SYSTEM, 0x00000059, "Generic operating system error") +NV_STATUS_CODE(NV_ERR_OTHER_DEVICE_FOUND, 0x0000005A, "Found other device instead of the requested one") +NV_STATUS_CODE(NV_ERR_OUT_OF_RANGE, 0x0000005B, "The specified value is out of bounds") +NV_STATUS_CODE(NV_ERR_OVERLAPPING_UVM_COMMIT, 0x0000005C, "Overlapping unified virtual memory commit") +NV_STATUS_CODE(NV_ERR_PAGE_TABLE_NOT_AVAIL, 0x0000005D, "Requested page table not available") +NV_STATUS_CODE(NV_ERR_PID_NOT_FOUND, 0x0000005E, "Process-Id not found") +NV_STATUS_CODE(NV_ERR_PROTECTION_FAULT, 0x0000005F, "Protection fault") +NV_STATUS_CODE(NV_ERR_RC_ERROR, 0x00000060, "Generic RC error") +NV_STATUS_CODE(NV_ERR_REJECTED_VBIOS, 0x00000061, "Given Video BIOS rejected/invalid") +NV_STATUS_CODE(NV_ERR_RESET_REQUIRED, 0x00000062, "Reset required") +NV_STATUS_CODE(NV_ERR_STATE_IN_USE, 0x00000063, "State in use") +NV_STATUS_CODE(NV_ERR_SIGNAL_PENDING, 0x00000064, "Signal pending") +NV_STATUS_CODE(NV_ERR_TIMEOUT, 0x00000065, "Call timed out") +NV_STATUS_CODE(NV_ERR_TIMEOUT_RETRY, 0x00000066, "Call timed out, please retry later") +NV_STATUS_CODE(NV_ERR_TOO_MANY_PRIMARIES, 0x00000067, "Too many primaries") +NV_STATUS_CODE(NV_ERR_UVM_ADDRESS_IN_USE, 0x00000068, "Unified virtual memory requested address already in use") +NV_STATUS_CODE(NV_ERR_MAX_SESSION_LIMIT_REACHED, 0x00000069, "Maximum number of sessions reached") +NV_STATUS_CODE(NV_ERR_LIB_RM_VERSION_MISMATCH, 0x0000006A, "Library version doesn't match driver version") //Contained within the RMAPI library +NV_STATUS_CODE(NV_ERR_PRIV_SEC_VIOLATION, 0x0000006B, "Priv security violation") +NV_STATUS_CODE(NV_ERR_GPU_IN_DEBUG_MODE, 0x0000006C, "GPU currently in debug mode") +NV_STATUS_CODE(NV_ERR_FEATURE_NOT_ENABLED, 0x0000006D, "Requested Feature functionality is not enabled") +NV_STATUS_CODE(NV_ERR_RESOURCE_LOST, 0x0000006E, "Requested resource has been destroyed") +NV_STATUS_CODE(NV_ERR_PMU_NOT_READY, 0x0000006F, "PMU is not ready or has not yet been initialized") +NV_STATUS_CODE(NV_ERR_FLCN_ERROR, 0x00000070, "Generic falcon assert or halt") +NV_STATUS_CODE(NV_ERR_FATAL_ERROR, 0x00000071, "Fatal/unrecoverable error") +NV_STATUS_CODE(NV_ERR_MEMORY_ERROR, 0x00000072, "Generic memory error") +NV_STATUS_CODE(NV_ERR_INVALID_LICENSE, 0x00000073, "License provided is rejected or invalid") +NV_STATUS_CODE(NV_ERR_NVLINK_INIT_ERROR, 0x00000074, "Nvlink Init Error") +NV_STATUS_CODE(NV_ERR_NVLINK_MINION_ERROR, 0x00000075, "Nvlink Minion Error") +NV_STATUS_CODE(NV_ERR_NVLINK_CLOCK_ERROR, 0x00000076, "Nvlink Clock Error") +NV_STATUS_CODE(NV_ERR_NVLINK_TRAINING_ERROR, 0x00000077, "Nvlink Training Error") +NV_STATUS_CODE(NV_ERR_NVLINK_CONFIGURATION_ERROR, 0x00000078, "Nvlink Configuration Error") +NV_STATUS_CODE(NV_ERR_RISCV_ERROR, 0x00000079, "Generic RISC-V assert or halt") +NV_STATUS_CODE(NV_ERR_FABRIC_MANAGER_NOT_PRESENT, 0x0000007A, "Fabric Manager is not loaded") + +// Warnings: +NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch") +NV_STATUS_CODE(NV_WARN_INCORRECT_PERFMON_DATA, 0x00010002, "WARNING Incorrect performance monitor data") +NV_STATUS_CODE(NV_WARN_MISMATCHED_SLAVE, 0x00010003, "WARNING Slave mismatch") +NV_STATUS_CODE(NV_WARN_MISMATCHED_TARGET, 0x00010004, "WARNING Target mismatch") +NV_STATUS_CODE(NV_WARN_MORE_PROCESSING_REQUIRED, 0x00010005, "WARNING More processing required for the call") +NV_STATUS_CODE(NV_WARN_NOTHING_TO_DO, 0x00010006, "WARNING Nothing to do") +NV_STATUS_CODE(NV_WARN_NULL_OBJECT, 0x00010007, "WARNING NULL object found") +NV_STATUS_CODE(NV_WARN_OUT_OF_RANGE, 0x00010008, "WARNING value out of range") + +#endif /* SDK_NVSTATUSCODES_H */ diff --git a/userspace/sdks/nv525/nvidia/inc/nvtypes.h b/userspace/sdks/nv525/nvidia/inc/nvtypes.h new file mode 100644 index 0000000..53a60f9 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/nvtypes.h @@ -0,0 +1,625 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVTYPES_INCLUDED +#define NVTYPES_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include "cpuopsys.h" + +#ifndef NVTYPES_USE_STDINT +#define NVTYPES_USE_STDINT 0 +#endif + +#if NVTYPES_USE_STDINT +#ifdef __cplusplus +#include +#include +#else +#include +#include +#endif // __cplusplus +#endif // NVTYPES_USE_STDINT + +#ifndef __cplusplus +// Header includes to make sure wchar_t is defined for C-file compilation +// (C++ is not affected as it is a fundamental type there) +// _MSC_VER is a hack to avoid failures for old setup of UEFI builds which are +// currently set to msvc100 but do not properly set the include paths +#endif // __cplusplus + +#if defined(MAKE_NV64TYPES_8BYTES_ALIGNED) && defined(__i386__) +// ensure or force 8-bytes alignment of NV 64-bit types +#define OPTIONAL_ALIGN8_ATTR __attribute__((aligned(8))) +#else +// nothing needed +#define OPTIONAL_ALIGN8_ATTR +#endif // MAKE_NV64TYPES_8BYTES_ALIGNED && i386 + + /***************************************************************************\ +|* Typedefs *| + \***************************************************************************/ + +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +//Typedefs for MISRA COMPLIANCE +typedef unsigned long long UInt64; +typedef signed long long Int64; +typedef unsigned int UInt32; +typedef signed int Int32; +typedef unsigned short UInt16; +typedef signed short Int16; +typedef unsigned char UInt8 ; +typedef signed char Int8 ; + +typedef void Void; +typedef float float32_t; +typedef double float64_t; +#endif + + +// Floating point types +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +typedef float32_t NvF32; /* IEEE Single Precision (S1E8M23) */ +typedef float64_t NvF64 OPTIONAL_ALIGN8_ATTR; /* IEEE Double Precision (S1E11M52) */ +#else +typedef float NvF32; /* IEEE Single Precision (S1E8M23) */ +typedef double NvF64 OPTIONAL_ALIGN8_ATTR; /* IEEE Double Precision (S1E11M52) */ +#endif + + +// 8-bit: 'char' is the only 8-bit in the C89 standard and after. +#if NVTYPES_USE_STDINT +typedef uint8_t NvV8; /* "void": enumerated or multiple fields */ +typedef uint8_t NvU8; /* 0 to 255 */ +typedef int8_t NvS8; /* -128 to 127 */ +#else +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +typedef UInt8 NvV8; /* "void": enumerated or multiple fields */ +typedef UInt8 NvU8; /* 0 to 255 */ +typedef Int8 NvS8; /* -128 to 127 */ +#else +typedef unsigned char NvV8; /* "void": enumerated or multiple fields */ +typedef unsigned char NvU8; /* 0 to 255 */ +typedef signed char NvS8; /* -128 to 127 */ +#endif +#endif // NVTYPES_USE_STDINT + + +#if NVTYPES_USE_STDINT +typedef uint16_t NvV16; /* "void": enumerated or multiple fields */ +typedef uint16_t NvU16; /* 0 to 65535 */ +typedef int16_t NvS16; /* -32768 to 32767 */ +#else +// 16-bit: If the compiler tells us what we can use, then use it. +#ifdef __INT16_TYPE__ +typedef unsigned __INT16_TYPE__ NvV16; /* "void": enumerated or multiple fields */ +typedef unsigned __INT16_TYPE__ NvU16; /* 0 to 65535 */ +typedef signed __INT16_TYPE__ NvS16; /* -32768 to 32767 */ + +// The minimal standard for C89 and after +#else // __INT16_TYPE__ +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +typedef UInt16 NvV16; /* "void": enumerated or multiple fields */ +typedef UInt16 NvU16; /* 0 to 65535 */ +typedef Int16 NvS16; /* -32768 to 32767 */ +#else +typedef unsigned short NvV16; /* "void": enumerated or multiple fields */ +typedef unsigned short NvU16; /* 0 to 65535 */ +typedef signed short NvS16; /* -32768 to 32767 */ +#endif +#endif // __INT16_TYPE__ +#endif // NVTYPES_USE_STDINT + +// wchar type (fixed size types consistent across Linux/Windows boundaries) +#if defined(NV_HAS_WCHAR_T_TYPEDEF) + typedef wchar_t NvWchar; +#else + typedef NvV16 NvWchar; +#endif + +// Macro to build an NvU32 from four bytes, listed from msb to lsb +#define NvU32_BUILD(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d)) + +#if NVTYPES_USE_STDINT +typedef uint32_t NvV32; /* "void": enumerated or multiple fields */ +typedef uint32_t NvU32; /* 0 to 4294967295 */ +typedef int32_t NvS32; /* -2147483648 to 2147483647 */ +#else +// 32-bit: If the compiler tells us what we can use, then use it. +#ifdef __INT32_TYPE__ +typedef unsigned __INT32_TYPE__ NvV32; /* "void": enumerated or multiple fields */ +typedef unsigned __INT32_TYPE__ NvU32; /* 0 to 4294967295 */ +typedef signed __INT32_TYPE__ NvS32; /* -2147483648 to 2147483647 */ + +// Older compilers +#else // __INT32_TYPE__ + +// For historical reasons, NvU32/NvV32 are defined to different base intrinsic +// types than NvS32 on some platforms. +// Mainly for 64-bit linux, where long is 64 bits and win9x, where int is 16 bit. +#if (defined(NV_UNIX) || defined(vxworks) || defined(NV_WINDOWS_CE) || \ + defined(__arm) || defined(__IAR_SYSTEMS_ICC__) || defined(NV_QNX) || \ + defined(NV_INTEGRITY) || defined(NV_MODS) || \ + defined(__GNUC__) || defined(__clang__) || defined(NV_MACINTOSH_64)) && \ + (!defined(NV_MACINTOSH) || defined(NV_MACINTOSH_64)) +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +typedef UInt32 NvV32; /* "void": enumerated or multiple fields */ +typedef UInt32 NvU32; /* 0 to 4294967295 */ +#else +typedef unsigned int NvV32; /* "void": enumerated or multiple fields */ +typedef unsigned int NvU32; /* 0 to 4294967295 */ +#endif + +// The minimal standard for C89 and after +#else // (defined(NV_UNIX) || defined(vxworks) || ... +typedef unsigned long NvV32; /* "void": enumerated or multiple fields */ +typedef unsigned long NvU32; /* 0 to 4294967295 */ +#endif // (defined(NV_UNIX) || defined(vxworks) || ... + +// Mac OS 32-bit still needs this +#if defined(NV_MACINTOSH) && !defined(NV_MACINTOSH_64) +typedef signed long NvS32; /* -2147483648 to 2147483647 */ +#else +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +typedef Int32 NvS32; /* -2147483648 to 2147483647 */ +#else +typedef signed int NvS32; /* -2147483648 to 2147483647 */ +#endif +#endif // defined(NV_MACINTOSH) && !defined(NV_MACINTOSH_64) +#endif // __INT32_TYPE__ +#endif // NVTYPES_USE_STDINT + + + +#if NVTYPES_USE_STDINT +typedef uint64_t NvU64 OPTIONAL_ALIGN8_ATTR; /* 0 to 18446744073709551615 */ +typedef int64_t NvS64 OPTIONAL_ALIGN8_ATTR; /* -9223372036854775808 to 9223372036854775807 */ + +#define NvU64_fmtX PRIX64 +#define NvU64_fmtx PRIx64 +#define NvU64_fmtu PRIu64 +#define NvU64_fmto PRIo64 +#define NvS64_fmtd PRId64 +#define NvS64_fmti PRIi64 +#else +// 64-bit types for compilers that support them, plus some obsolete variants +#if defined(__GNUC__) || defined(__clang__) || defined(__arm) || \ + defined(__IAR_SYSTEMS_ICC__) || defined(__ghs__) || defined(_WIN64) || \ + defined(__SUNPRO_C) || defined(__SUNPRO_CC) || defined (__xlC__) +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +typedef UInt64 NvU64 OPTIONAL_ALIGN8_ATTR; /* 0 to 18446744073709551615 */ +typedef Int64 NvS64 OPTIONAL_ALIGN8_ATTR; /* -9223372036854775808 to 9223372036854775807 */ +#else +typedef unsigned long long NvU64 OPTIONAL_ALIGN8_ATTR; /* 0 to 18446744073709551615 */ +typedef long long NvS64 OPTIONAL_ALIGN8_ATTR; /* -9223372036854775808 to 9223372036854775807 */ +#endif + +#define NvU64_fmtX "llX" +#define NvU64_fmtx "llx" +#define NvU64_fmtu "llu" +#define NvU64_fmto "llo" +#define NvS64_fmtd "lld" +#define NvS64_fmti "lli" + +// Microsoft since 2003 -- https://msdn.microsoft.com/en-us/library/29dh1w7z.aspx +#else +typedef unsigned __int64 NvU64 OPTIONAL_ALIGN8_ATTR; /* 0 to 18446744073709551615 */ +typedef __int64 NvS64 OPTIONAL_ALIGN8_ATTR; /* -9223372036854775808 to 9223372036854775807 */ + +#define NvU64_fmtX "I64X" +#define NvU64_fmtx "I64x" +#define NvU64_fmtu "I64u" +#define NvU64_fmto "I64o" +#define NvS64_fmtd "I64d" +#define NvS64_fmti "I64i" + +#endif +#endif // NVTYPES_USE_STDINT + +#ifdef NV_TYPESAFE_HANDLES +/* + * Can't use opaque pointer as clients might be compiled with mismatched + * pointer sizes. TYPESAFE check will eventually be removed once all clients + * have transistioned safely to NvHandle. + * The plan is to then eventually scale up the handle to be 64-bits. + */ +typedef struct +{ + NvU32 val; +} NvHandle; +#else +/* + * For compatibility with modules that haven't moved typesafe handles. + */ +typedef NvU32 NvHandle; +#endif // NV_TYPESAFE_HANDLES + +/* Boolean type */ +typedef NvU8 NvBool; +#define NV_TRUE ((NvBool)(0 == 0)) +#define NV_FALSE ((NvBool)(0 != 0)) + +/* Tristate type: NV_TRISTATE_FALSE, NV_TRISTATE_TRUE, NV_TRISTATE_INDETERMINATE */ +typedef NvU8 NvTristate; +#define NV_TRISTATE_FALSE ((NvTristate) 0) +#define NV_TRISTATE_TRUE ((NvTristate) 1) +#define NV_TRISTATE_INDETERMINATE ((NvTristate) 2) + +/* Macros to extract the low and high parts of a 64-bit unsigned integer */ +/* Also designed to work if someone happens to pass in a 32-bit integer */ +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +#define NvU64_HI32(n) ((NvU32)((((NvU64)(n)) >> 32) & 0xffffffffU)) +#define NvU64_LO32(n) ((NvU32)(( (NvU64)(n)) & 0xffffffffU)) +#else +#define NvU64_HI32(n) ((NvU32)((((NvU64)(n)) >> 32) & 0xffffffff)) +#define NvU64_LO32(n) ((NvU32)(( (NvU64)(n)) & 0xffffffff)) +#endif +#define NvU40_HI32(n) ((NvU32)((((NvU64)(n)) >> 8) & 0xffffffffU)) +#define NvU40_HI24of32(n) ((NvU32)( (NvU64)(n) & 0xffffff00U)) + +/* Macros to get the MSB and LSB of a 32 bit unsigned number */ +#define NvU32_HI16(n) ((NvU16)((((NvU32)(n)) >> 16) & 0xffffU)) +#define NvU32_LO16(n) ((NvU16)(( (NvU32)(n)) & 0xffffU)) + + /***************************************************************************\ +|* *| +|* 64 bit type definitions for use in interface structures. *| +|* *| + \***************************************************************************/ + +#if defined(NV_64_BITS) + +typedef void* NvP64; /* 64 bit void pointer */ +typedef NvU64 NvUPtr; /* pointer sized unsigned int */ +typedef NvS64 NvSPtr; /* pointer sized signed int */ +typedef NvU64 NvLength; /* length to agree with sizeof */ + +#define NvP64_VALUE(n) (n) +#define NvP64_fmt "%p" + +#define KERNEL_POINTER_FROM_NvP64(p,v) ((p)(v)) +#define NvP64_PLUS_OFFSET(p,o) (NvP64)((NvU64)(p) + (NvU64)(o)) + +#define NvUPtr_fmtX NvU64_fmtX +#define NvUPtr_fmtx NvU64_fmtx +#define NvUPtr_fmtu NvU64_fmtu +#define NvUPtr_fmto NvU64_fmto +#define NvSPtr_fmtd NvS64_fmtd +#define NvSPtr_fmti NvS64_fmti + +#else + +typedef NvU64 NvP64; /* 64 bit void pointer */ +typedef NvU32 NvUPtr; /* pointer sized unsigned int */ +typedef NvS32 NvSPtr; /* pointer sized signed int */ +typedef NvU32 NvLength; /* length to agree with sizeof */ + +#define NvP64_VALUE(n) ((void *)(NvUPtr)(n)) +#define NvP64_fmt "0x%llx" + +#define KERNEL_POINTER_FROM_NvP64(p,v) ((p)(NvUPtr)(v)) +#define NvP64_PLUS_OFFSET(p,o) ((p) + (NvU64)(o)) + +#define NvUPtr_fmtX "X" +#define NvUPtr_fmtx "x" +#define NvUPtr_fmtu "u" +#define NvUPtr_fmto "o" +#define NvSPtr_fmtd "d" +#define NvSPtr_fmti "i" + +#endif + +#define NvP64_NULL (NvP64)0 + +/*! + * Helper macro to pack an @ref NvU64_ALIGN32 structure from a @ref NvU64. + * + * @param[out] pDst Pointer to NvU64_ALIGN32 structure to pack + * @param[in] pSrc Pointer to NvU64 with which to pack + */ +#define NvU64_ALIGN32_PACK(pDst, pSrc) \ +do { \ + (pDst)->lo = NvU64_LO32(*(pSrc)); \ + (pDst)->hi = NvU64_HI32(*(pSrc)); \ +} while (NV_FALSE) + +/*! + * Helper macro to unpack a @ref NvU64_ALIGN32 structure into a @ref NvU64. + * + * @param[out] pDst Pointer to NvU64 in which to unpack + * @param[in] pSrc Pointer to NvU64_ALIGN32 structure from which to unpack + */ +#define NvU64_ALIGN32_UNPACK(pDst, pSrc) \ +do { \ + (*(pDst)) = NvU64_ALIGN32_VAL(pSrc); \ +} while (NV_FALSE) + +/*! + * Helper macro to unpack a @ref NvU64_ALIGN32 structure as a @ref NvU64. + * + * @param[in] pSrc Pointer to NvU64_ALIGN32 structure to unpack + */ +#define NvU64_ALIGN32_VAL(pSrc) \ + ((NvU64) ((NvU64)((pSrc)->lo) | (((NvU64)(pSrc)->hi) << 32U))) + +/*! + * Helper macro to check whether the 32 bit aligned 64 bit number is zero. + * + * @param[in] _pU64 Pointer to NvU64_ALIGN32 structure. + * + * @return + * NV_TRUE _pU64 is zero. + * NV_FALSE otherwise. + */ +#define NvU64_ALIGN32_IS_ZERO(_pU64) \ + (((_pU64)->lo == 0U) && ((_pU64)->hi == 0U)) + +/*! + * Helper macro to sub two 32 aligned 64 bit numbers on 64 bit processor. + * + * @param[in] pSrc1 Pointer to NvU64_ALIGN32 source 1 structure. + * @param[in] pSrc2 Pointer to NvU64_ALIGN32 source 2 structure. + * @param[in/out] pDst Pointer to NvU64_ALIGN32 dest. structure. + */ +#define NvU64_ALIGN32_ADD(pDst, pSrc1, pSrc2) \ +do { \ + NvU64 __dst, __src1, __scr2; \ + \ + NvU64_ALIGN32_UNPACK(&__src1, (pSrc1)); \ + NvU64_ALIGN32_UNPACK(&__scr2, (pSrc2)); \ + __dst = __src1 + __scr2; \ + NvU64_ALIGN32_PACK((pDst), &__dst); \ +} while (NV_FALSE) + +/*! + * Helper macro to sub two 32 aligned 64 bit numbers on 64 bit processor. + * + * @param[in] pSrc1 Pointer to NvU64_ALIGN32 source 1 structure. + * @param[in] pSrc2 Pointer to NvU64_ALIGN32 source 2 structure. + * @param[in/out] pDst Pointer to NvU64_ALIGN32 dest. structure. + */ +#define NvU64_ALIGN32_SUB(pDst, pSrc1, pSrc2) \ +do { \ + NvU64 __dst, __src1, __scr2; \ + \ + NvU64_ALIGN32_UNPACK(&__src1, (pSrc1)); \ + NvU64_ALIGN32_UNPACK(&__scr2, (pSrc2)); \ + __dst = __src1 - __scr2; \ + NvU64_ALIGN32_PACK((pDst), &__dst); \ +} while (NV_FALSE) + +/*! + * Structure for representing 32 bit aligned NvU64 (64-bit unsigned integer) + * structures. This structure must be used because the 32 bit processor and + * 64 bit processor compilers will pack/align NvU64 differently. + * + * One use case is RM being 64 bit proc whereas PMU being 32 bit proc, this + * alignment difference will result in corrupted transactions between the RM + * and PMU. + * + * See the @ref NvU64_ALIGN32_PACK and @ref NvU64_ALIGN32_UNPACK macros for + * packing and unpacking these structures. + * + * @note The intention of this structure is to provide a datatype which will + * packed/aligned consistently and efficiently across all platforms. + * We don't want to use "NV_DECLARE_ALIGNED(NvU64, 8)" because that + * leads to memory waste on our 32-bit uprocessors (e.g. FALCONs) where + * DMEM efficiency is vital. + */ +typedef struct +{ + /*! + * Low 32 bits. + */ + NvU32 lo; + /*! + * High 32 bits. + */ + NvU32 hi; +} NvU64_ALIGN32; + +/* Useful macro to hide required double cast */ +#define NV_PTR_TO_NvP64(n) (NvP64)(NvUPtr)(n) +#define NV_SIGN_EXT_PTR_TO_NvP64(p) ((NvP64)(NvS64)(NvSPtr)(p)) +#define KERNEL_POINTER_TO_NvP64(p) ((NvP64)(uintptr_t)(p)) + + /***************************************************************************\ +|* *| +|* Limits for common types. *| +|* *| + \***************************************************************************/ + +/* Explanation of the current form of these limits: + * + * - Decimal is used, as hex values are by default positive. + * - Casts are not used, as usage in the preprocessor itself (#if) ends poorly. + * - The subtraction of 1 for some MIN values is used to get around the fact + * that the C syntax actually treats -x as NEGATE(x) instead of a distinct + * number. Since 214748648 isn't a valid positive 32-bit signed value, we + * take the largest valid positive signed number, negate it, and subtract 1. + */ +#define NV_S8_MIN (-128) +#define NV_S8_MAX (+127) +#define NV_U8_MIN (0U) +#define NV_U8_MAX (+255U) +#define NV_S16_MIN (-32768) +#define NV_S16_MAX (+32767) +#define NV_U16_MIN (0U) +#define NV_U16_MAX (+65535U) +#define NV_S32_MIN (-2147483647 - 1) +#define NV_S32_MAX (+2147483647) +#define NV_U32_MIN (0U) +#define NV_U32_MAX (+4294967295U) +#define NV_S64_MIN (-9223372036854775807LL - 1LL) +#define NV_S64_MAX (+9223372036854775807LL) +#define NV_U64_MIN (0ULL) +#define NV_U64_MAX (+18446744073709551615ULL) + +/* Aligns fields in structs so they match up between 32 and 64 bit builds */ +#if defined(__GNUC__) || defined(__clang__) || defined(NV_QNX) +#define NV_ALIGN_BYTES(size) __attribute__ ((aligned (size))) +#elif defined(__arm) +#define NV_ALIGN_BYTES(size) __align(ALIGN) +#else +// XXX This is dangerously nonportable! We really shouldn't provide a default +// version of this that doesn't do anything. +#define NV_ALIGN_BYTES(size) +#endif + +// NV_DECLARE_ALIGNED() can be used on all platforms. +// This macro form accounts for the fact that __declspec on Windows is required +// before the variable type, +// and NV_ALIGN_BYTES is required after the variable name. +#if defined(__GNUC__) || defined(__clang__) || defined(NV_QNX) +#define NV_DECLARE_ALIGNED(TYPE_VAR, ALIGN) TYPE_VAR __attribute__ ((aligned (ALIGN))) +#elif defined(__arm) +#define NV_DECLARE_ALIGNED(TYPE_VAR, ALIGN) __align(ALIGN) TYPE_VAR +#endif + + /***************************************************************************\ +|* Function Declaration Types *| + \***************************************************************************/ + +// stretching the meaning of "nvtypes", but this seems to least offensive +// place to re-locate these from nvos.h which cannot be included by a number +// of builds that need them + + #if defined(__GNUC__) + #if (__GNUC__ > 3) || \ + ((__GNUC__ == 3) && (__GNUC_MINOR__ >= 1) && (__GNUC_PATCHLEVEL__ >= 1)) + #define NV_NOINLINE __attribute__((__noinline__)) + #endif + #elif defined(__clang__) + #if __has_attribute(noinline) + #define NV_NOINLINE __attribute__((__noinline__)) + #endif + #elif defined(__arm) && (__ARMCC_VERSION >= 300000) + #define NV_NOINLINE __attribute__((__noinline__)) + #elif (defined(__SUNPRO_C) && (__SUNPRO_C >= 0x590)) ||\ + (defined(__SUNPRO_CC) && (__SUNPRO_CC >= 0x590)) + #define NV_NOINLINE __attribute__((__noinline__)) + #elif defined (__INTEL_COMPILER) + #define NV_NOINLINE __attribute__((__noinline__)) + #endif + + #if !defined(NV_NOINLINE) + #define NV_NOINLINE + #endif + + /* GreenHills compiler defines __GNUC__, but doesn't support + * __inline__ keyword. */ + #if defined(__ghs__) + #define NV_INLINE inline + #elif defined(__GNUC__) || defined(__clang__) || defined(__INTEL_COMPILER) + #define NV_INLINE __inline__ + #elif defined (macintosh) || defined(__SUNPRO_C) || defined(__SUNPRO_CC) + #define NV_INLINE inline + #elif defined(__arm) + #define NV_INLINE __inline + #else + #define NV_INLINE + #endif + + /* Don't force inline on DEBUG builds -- it's annoying for debuggers. */ + #if !defined(DEBUG) + /* GreenHills compiler defines __GNUC__, but doesn't support + * __attribute__ or __inline__ keyword. */ + #if defined(__ghs__) + #define NV_FORCEINLINE inline + #elif defined(__GNUC__) + // GCC 3.1 and beyond support the always_inline function attribute. + #if (__GNUC__ > 3) || ((__GNUC__ == 3) && (__GNUC_MINOR__ >= 1)) + #define NV_FORCEINLINE __attribute__((__always_inline__)) __inline__ + #else + #define NV_FORCEINLINE __inline__ + #endif + #elif defined(__clang__) + #if __has_attribute(always_inline) + #define NV_FORCEINLINE __attribute__((__always_inline__)) __inline__ + #else + #define NV_FORCEINLINE __inline__ + #endif + #elif defined(__arm) && (__ARMCC_VERSION >= 220000) + // RVDS 2.2 also supports forceinline, but ADS 1.2 does not + #define NV_FORCEINLINE __forceinline + #else /* defined(__GNUC__) */ + #define NV_FORCEINLINE NV_INLINE + #endif + #else + #define NV_FORCEINLINE NV_INLINE + #endif + + #define NV_APIENTRY + #define NV_FASTCALL + #define NV_CDECLCALL + #define NV_STDCALL + + /* + * The 'warn_unused_result' function attribute prompts GCC to issue a + * warning if the result of a function tagged with this attribute + * is ignored by a caller. In combination with '-Werror', it can be + * used to enforce result checking in RM code; at this point, this + * is only done on UNIX. + */ + #if defined(__GNUC__) && defined(NV_UNIX) + #if (__GNUC__ > 3) || ((__GNUC__ == 3) && (__GNUC_MINOR__ >= 4)) + #define NV_FORCERESULTCHECK __attribute__((__warn_unused_result__)) + #else + #define NV_FORCERESULTCHECK + #endif + #elif defined(__clang__) + #if __has_attribute(warn_unused_result) + #define NV_FORCERESULTCHECK __attribute__((__warn_unused_result__)) + #else + #define NV_FORCERESULTCHECK + #endif + #else /* defined(__GNUC__) */ + #define NV_FORCERESULTCHECK + #endif + + #if defined(__GNUC__) || defined(__clang__) || defined(__INTEL_COMPILER) + #define NV_ATTRIBUTE_UNUSED __attribute__((__unused__)) + #else + #define NV_ATTRIBUTE_UNUSED + #endif + + /* + * Functions decorated with NV_FORMAT_PRINTF(f, a) have a format string at + * parameter number 'f' and variadic arguments start at parameter number 'a'. + * (Note that for C++ methods, there is an implicit 'this' parameter so + * explicit parameters are numbered from 2.) + */ + #if defined(__GNUC__) + #define NV_FORMAT_PRINTF(_f, _a) __attribute__((format(printf, _f, _a))) + #else + #define NV_FORMAT_PRINTF(_f, _a) + #endif + +#ifdef __cplusplus +} +#endif + +#endif /* NVTYPES_INCLUDED */ diff --git a/userspace/sdks/nv525/nvidia/inc/rmcd.h b/userspace/sdks/nv525/nvidia/inc/rmcd.h new file mode 100644 index 0000000..07d29ac --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/rmcd.h @@ -0,0 +1,393 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2002-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef RMCD_H +#define RMCD_H + +//****************************************************************************** +// +// Module Name: RMCD.H +// +// This file contains structures and constants that define the resource manager +// specific data for the crash dump file. The record definitions defined here +// are always stored after the crash dump file header. Each record defined here +// is preceded by the NVCD_RECORD structure. +// +//****************************************************************************** + +#include "nvgputypes.h" +#include "nvcd.h" + +#define NV_RMCD_VERSION (20) + +// Define RC Reset Callback function type +#define RM_RC_CALLBACK_HANDLE_UPDATE 1 +#if RM_RC_CALLBACK_HANDLE_UPDATE +typedef NvU32 RC_RESET_CALLBACK(NvHandle hClient, NvHandle hDevice, NvHandle hFifo, NvHandle hChannel, + void *pContext, NvBool clearRc); +#else +typedef NvU32 RC_RESET_CALLBACK(NvHandle hClient, NvHandle hDevice, NvHandle hChannel, void *pContext, NvBool clearRc); +#endif + +typedef struct _rc_error_context { + struct OBJGPU *pGpu; // GPU device + NvU32 ChId; // Channel ID of channel in RC recovery + NvU32 secChId; // Channel ID of secondary channel + NvHandle sechClient; // Client handle of secondary channel + NvU32 exceptType; // ROBUST_CHANNEL_* error identifier + NvU32 EngineId; // Engine ID of faulting engine + NvU32 subdeviceInstance; // This parameter returns the unicast subdevice instance number + // associated with the specified GPU. This value can be used to + // instantiate a unicast reference to the GPU using the NV20_SUBDEVICE + // classes. + + // FIFO_MMU_EXCEPTION_DATA + NvU32 addrLo; // MMU fault address (Lo) + NvU32 addrHi; // MMU fault address (Hi) + NvU32 faultType; // MMU fault code + const char *faultStr; // MMU fault string + +} RC_ERROR_CONTEXT, *PRC_ERROR_CONTEXT; + +#define MAX_FBBAS 0x2 +#define FBBA_MUX_SEL_MAX 0xF +#define FBBA_RXB_STATUS_SEL_MAX 0x10 +#define RDSTAT_MAX 0x2 + +// Define the resource manager group record types +typedef enum +{ + RmCurrentStateInfo_V2 = 4, // Revised Version 2 RM current state info. record + RmMissedNotifierInfo = 9, // RM Driver Indicates Missed Notifier + RmGlobalInfo_V3 = 10, // Revised Version 3 of Global Info + + RmProtoBuf = 131, // ProtoBuf + RmProtoBuf_V2 = 132, // ProtoBuf + NvDump + RmDclMsg = 133, // One of the optional DlcMsg fields, encoded + RmJournalEngDump = 134, + DP_ASSERT_HIT = 135, + DP_LOG_CALL = 136, + RmPrbFullDump = 137, // Full NvDump protobuf message + + // Includes RmRCCommonJournal_RECORD structure. + RmJournalBugCheck = 138, // Bugcheck record + RmRC2SwRmAssert_V3 = 139, // Retail logged RM_ASSERT info + RmRC2GpuTimeout_V3 = 140, // Retail logged RM_TIMEOUT events + RmRC2SwDbgBreakpoint_V3 = 141, // Uses same format as RmRC2SwRmAssert_V3 + RmBadRead_V2 = 142, // Record with Bad Read Information + RmSurpriseRemoval_V2 = 143, // Surprise Removal + RmPowerState = 144, // PowerState + RmPrbErrorInfo_V2 = 145, // Protobuf error record + RmPrbFullDump_V2 = 146, // Full NvDump protobuf message + RmRcDiagReport = 147, // Rc Diagnostic report message + RmNocatReport = 149, // Nocat reports. + RmDispState = 150, // Display error record + +} RMCD_RECORD_TYPE; + +typedef struct { + NVCD_RECORD Header; // Global information record header + NvU32 dwSize; // Total Protobuf Message Size +} RmProtoBuf_RECORD; +typedef RmProtoBuf_RECORD *PRmProtoBuf_RECORD; + +// +// Please include RmRCCommonJournal_RECORD structure at the top of all new and +// revised journal record structures. +// +#define NV_RM_JOURNAL_STATE_MASK_GC6_STATE 3:0 + +#define NV_RM_JOURNAL_STATE_MASK_IS_NOT_FULL_POWER 0x00000010 +#define NV_RM_JOURNAL_STATE_MASK_IS_NOT_CONNECTED 0x00000020 +#define NV_RM_JOURNAL_STATE_MASK_IS_IN_STANDBY 0x00000040 +#define NV_RM_JOURNAL_STATE_MASK_IS_IN_HIBERNATE 0x00000080 +#define NV_RM_JOURNAL_STATE_MASK_IS_IN_PM_CODEPATH 0x00000100 +#define NV_RM_JOURNAL_STATE_MASK_IS_IN_GC6_RESET 0x00000200 +#define NV_RM_JOURNAL_STATE_MASK_IS_IN_FULLCHIP_RESET 0x00000400 +#define NV_RM_JOURNAL_STATE_MASK_IS_IN_SEC_BUS_RESET 0x00000800 +#define NV_RM_JOURNAL_STATE_MASK_IS_IN_TIMEOUT_RECOVERY 0x00001000 +#define NV_RM_JOURNAL_STATE_MASK_IS_LOST 0x00002000 +#define NV_RM_JOURNAL_STATE_MASK_VIDMEM_FAILED_BAR0 0x00004000 +#define NV_RM_JOURNAL_STATE_MASK_VIDMEM_FAILED_BAR2 0x00008000 +#define NV_RM_JOURNAL_STATE_MASK_VIDMEM_FAILED_FBHUB 0x00010000 + + +typedef struct _RmRCCommonJournal_RECORD +{ + NVCD_RECORD Header; + NvU32 GPUTag; + NvU64 CPUTag; + NvU64 timeStamp NV_ALIGN_BYTES(8); + NvU64 stateMask; + NvU8 *pNext; // temporary link used for sorting. + // note using type NvU8 because Linux + // generated code does not properly + // resove the refeerence to the struct type. + // & balks about void * type. +} RmRCCommonJournal_RECORD; +typedef RmRCCommonJournal_RECORD *PRmRCCommonJournal_RECORD; + +// RM_ASSERT + DBG_BREAKPOINT info +typedef struct +{ + RmRCCommonJournal_RECORD common; + NvU64 lastTimeStamp NV_ALIGN_BYTES(8); + NvU64 breakpointAddrHint NV_ALIGN_BYTES(8); // address that can identify bp module + NvU64 callStack[10] NV_ALIGN_BYTES(8); // Call stack when the assert occurred. + NvU32 count; + NvU32 lineNum; + NvU32 lastReportedCount; // last count reported to NOCAT + NvU64 nextReportedTimeStamp; // time stamp to use as start time for the + // next NOCAT report. +} RmRCCommonAssert_RECORD; +typedef RmRCCommonAssert_RECORD *PRmRCCommonAssert_RECORD; +#define NV_RM_ASSERT_UNKNOWN_LINE_NUM 0 + +typedef RmRCCommonAssert_RECORD RmRC2GpuTimeout3_RECORD; +typedef RmRC2GpuTimeout3_RECORD *PRmRC2GpuTimeout3_RECORD; + +// How Serious is this RM_ASSERT/DBG_BREAKPOINT +// (1) Info -- This is unexpected but we should continue to run +// (2) Error -- +// (3) Fatal -- This is hopeless -- FBI Timeout, Bus Error Etc +#define NV_RM_ASSERT_TYPE 3:0 +#define NV_RM_ASSERT_TYPE_INFO 0x00000001 +#define NV_RM_ASSERT_TYPE_ERROR 0x00000002 +#define NV_RM_ASSERT_TYPE_FATAL 0x00000003 + +// HW Unit which is having the issue +#define NV_RM_ASSERT_HW_UNIT 15:8 +#define NV_RM_ASSERT_HW_UNIT_NULL (0x00) +#define NV_RM_ASSERT_HW_UNIT_GRAPHICS (0x01) +#define NV_RM_ASSERT_HW_UNIT_COPY0 (0x02) +#define NV_RM_ASSERT_HW_UNIT_COPY1 (0x03) +#define NV_RM_ASSERT_HW_UNIT_VP (0x04) +#define NV_RM_ASSERT_HW_UNIT_ME (0x05) +#define NV_RM_ASSERT_HW_UNIT_PPP (0x06) +#define NV_RM_ASSERT_HW_UNIT_BSP (0x07) +#define NV_RM_ASSERT_HW_UNIT_NVDEC0 NV_RM_ASSERT_HW_UNIT_BSP +#define NV_RM_ASSERT_HW_UNIT_MPEG (0x08) +#define NV_RM_ASSERT_HW_UNIT_SW (0x09) +#define NV_RM_ASSERT_HW_UNIT_CIPHER (0x0a) +#define NV_RM_ASSERT_HW_UNIT_VIC (0x0b) +#define NV_RM_ASSERT_HW_UNIT_MSENC (0x0c) +#define NV_RM_ASSERT_HW_UNIT_NVENC0 NV_RM_ASSERT_HW_UNIT_MSENC +#define NV_RM_ASSERT_HW_UNIT_NVENC1 (0x0d) +#define NV_RM_ASSERT_HW_UNIT_HOST (0x0e) +#define NV_RM_ASSERT_HW_UNIT_ROM (0x0f) +#define NV_RM_ASSERT_HW_UNIT_INSTMEM (0x10) +#define NV_RM_ASSERT_HW_UNIT_DISP (0x11) +#define NV_RM_ASSERT_HW_UNIT_NVENC2 (0x12) +#define NV_RM_ASSERT_HW_UNIT_NVDEC1 (0x13) +#define NV_RM_ASSERT_HW_UNIT_NVDEC2 (0x14) +#define NV_RM_ASSERT_HW_UNIT_NVDEC3 (0x15) +#define NV_RM_ASSERT_HW_UNIT_NVDEC4 (0x16) +#define NV_RM_ASSERT_HW_UNIT_NVDEC5 (0x17) +#define NV_RM_ASSERT_HW_UNIT_NVDEC6 (0x18) +#define NV_RM_ASSERT_HW_UNIT_NVDEC7 (0x19) +#define NV_RM_ASSERT_HW_UNIT_ALLENGINES (0xff) +// SW Module which generated the error +#define NV_RM_ASSERT_SW_MODULE 15:8 + +// This is a specific error number which we wish to follow regardless of builds +// We want to use this for backend processing +// This is also a compromise. Ideally, each event would have a unique id but +// instead of doing this we use EIP which is unique per load. If we subtracted off +// the Module Load Address then it would be unique per build, Using EIP allows us +// to use the debugger to lookup the source code that corresponds to the event. +#define NV_RM_ASSERT_LEVEL_TAG 30:16 +// Host Errors +#define NV_RM_ASSERT_LEVEL_TAG_BAR1_PAGE_FAULT (0x0001) +#define NV_RM_ASSERT_LEVEL_TAG_IFB_PAGE_FAULT (0x0002) +#define NV_RM_ASSERT_LEVEL_TAG_PIO_ERROR (0x0003) +#define NV_RM_ASSERT_LEVEL_TAG_CHSW_SAVE_INVALID (0x0004) +#define NV_RM_ASSERT_LEVEL_TAG_CHSW_ERROR (0x0005) +#define NV_RM_ASSERT_LEVEL_TAG_FBIRD_TIMEOUT (0x0006) +#define NV_RM_ASSERT_LEVEL_TAG_CPUQ_FBIBUSY_TIMEOUT (0x0007) +#define NV_RM_ASSERT_LEVEL_TAG_CHSW_FSM_TIMEOUT (0x0008) +#define NV_RM_ASSERT_LEVEL_TAG_FB_FLUSH_TIMEOUT (0x0009) +#define NV_RM_ASSERT_LEVEL_TAG_P2PSTATE_TIMEOUT (0x000a) +#define NV_RM_ASSERT_LEVEL_TAG_VBIOS_CHECKSUM (0x000b) +#define NV_RM_ASSERT_LEVEL_TAG_DISP_SYNC (0x000c) + +// What is the generating Source -- GPU or SW +#define NV_RM_ASSERT_LEVEL_SOURCE 31:31 +#define NV_RM_ASSERT_LEVEL_SOURCE_SW 0x00000000 +#define NV_RM_ASSERT_LEVEL_SOURCE_HW 0x00000001 + + +// RM_ASSERT + DBG_BREAKPOINT info +typedef struct +{ + RmRCCommonAssert_RECORD commonAssert; + NvU32 level; +} RmRC2SwRmAssert3_RECORD; +typedef RmRC2SwRmAssert3_RECORD *PRmRC2SwRmAssert3_RECORD; + +// RM JOURNAL BUG CHECK +typedef struct +{ + RmRCCommonJournal_RECORD common; + NvU32 bugCheckCode; +} RmJournalBugcheck_RECORD, *PRmJournalBugcheck_RECORD; + +typedef struct +{ + NVCD_RECORD Header; + NvS32 GpuTemp; + NvS32 LocTemp; +} RmRC2TempReading_RECORD; +typedef RmRC2TempReading_RECORD *PRmRC2TempReading_RECORD; + +typedef enum { + MEMORY_BAR0 = 1, + MEMORY_FB, + MEMORY_INSTANCE, + MEMORY_PCI, +} RMCD_BAD_READ_SPACE; + +typedef struct +{ + RmRCCommonJournal_RECORD common; + NvU32 MemorySpace; // Which Memory Space + NvU32 Offset; // Offset in Memory Space + NvU32 Mask; // Mask used to detect bad read + NvU32 Value; // Value Return + NvU32 Reason; // Potential Reason why this might have happened +} RmRC2BadRead2_RECORD; + +typedef RmRC2BadRead2_RECORD *PRmRC2BadRead2_RECORD; + +typedef struct +{ + RmRCCommonJournal_RECORD common; + NvU32 hostEngTag; + NvU32 exceptType; + NvU32 exceptLevel; +} RmRCRecovery_RECORD; + +typedef RmRCRecovery_RECORD *PRmRCRecovery_RECORD; + +typedef struct +{ + RmRCCommonJournal_RECORD common; +} RmPrbInfo_RECORD_V2, *PRmPrbInfo_RECORD_V2; + +// Counters per type of RC Error. WIll only keep first n (10) types. +#define MAX_RC_ERROR_COUNTER 10 +#define RC_ERROR_COUNTER_OTHER_INDEX MAX_RC_ERROR_COUNTER-1 +#define RC_ERROR_COUNTER_TYPE_INVALID ((NvU32)(~0)) +#define RC_ERROR_COUNTER_OTHER_TYPE 1024 + +typedef struct +{ + NvU32 rcFaultType; + NvU32 rcErrorSrc; + NvU64 mmuFaultVA; + NvU32 mmuAccessType; +} rcExtraMMUInfo; + +typedef struct +{ + NvU32 rcGRErrType; + NvU32 rcGRExcptnSubTyp; +} rcExtraGRInfo; + +typedef struct +{ + NvU32 rcPBDMAID; + NvU64 rcPBDMAErrFlag; +} rcExtraPBDMAInfo; + +/* +* Union for storing extra data values for each kind of RC Error +* +* MMU +* ===== +* rcFaultType +* rcErrorSrc +* +* GR +* ======= +* rcGRErrType +* rcGRExcptnSubTyp +* +* PBDMA +* ========= +* rcPBDMAID +* rcPBDMAErrFlag +*/ + +typedef union +{ + rcExtraMMUInfo rcMMUData; + rcExtraGRInfo rcGRData; + rcExtraPBDMAInfo rcPBDMAData; +} rcExtraInfo; + +typedef struct +{ + NvU32 rcErrorType; + NvU32 rcErrorCount; + NvU32 rcLastCHID; + NvU64 rcLastTime; + rcExtraInfo rcExtrInfo; +} rcErrorCounterEntry; + +typedef struct +{ + NvU32 powerEvent; // The name of the point we are tracing + // Such as NVRM_OCA_PWR_EVENT_SET_POWER_ENTRY + NvU32 powerState; + NvU32 fastBootPowerState; // Tracking fast boot shutdown/hibernate states +} RmPowerState_RECORD, *PRmPowerState_RECORD; + +#define MAX_RCDB_RCDIAG_ENTRIES 200 +typedef struct +{ + NvU32 offset; + NvU32 tag; + NvU32 value; + NvU32 attribute; +} RmRcDiagRecordEntry; + +#define RCDB_RCDIAG_DEFAULT_OWNER 0 +typedef struct +{ + NvU16 idx; + NvU32 timeStamp; // time in seconds since 1/1/1970 + NvU16 type; + NvU32 flags; + NvU16 count; + NvU32 owner; // a handle indicating the ownership + NvU32 processId; // process Id of the originating process. + RmRcDiagRecordEntry data[MAX_RCDB_RCDIAG_ENTRIES]; +} RmRcDiag_RECORD, *PRmRcDiag_RECORD; + +#define MAX_RCDB_RCDIAG_WRAP_BUFF 32 +#define INVALID_RCDB_RCDIAG_INDEX 0xffffffff + +#define MAX_RCDB_NOCAT_WRAP_BUFF 100 +#define INVALID_RCDB_NOCAT_ID 0xffffffff + +#endif // RMCD_H diff --git a/userspace/sdks/nv525/nvidia/inc/rs_access.h b/userspace/sdks/nv525/nvidia/inc/rs_access.h new file mode 100644 index 0000000..7c71a78 --- /dev/null +++ b/userspace/sdks/nv525/nvidia/inc/rs_access.h @@ -0,0 +1,272 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: rs_access.finn +// + + + + +#include "nvtypes.h" +#include "nvmisc.h" + + +/****************************************************************************/ +/* Access right definitions */ +/****************************************************************************/ + +// +// The meaning of each access right is documented in +// resman/docs/rmapi/resource_server/rm_capabilities.adoc +// +// RS_ACCESS_COUNT is the number of access rights that have been defined +// and are in use. All integers in the range [0, RS_ACCESS_COUNT) should +// represent valid access rights. +// +// When adding a new access right, don't forget to update +// 1) The descriptions in the resman/docs/rmapi/resource_server/rm_capabilities.adoc +// 2) RS_ACCESS_COUNT, defined below +// 3) The declaration of g_rsAccessMetadata in rs_access_rights.c +// 4) The list of access rights in drivers/common/chip-config/Chipcontrols.pm +// 5) Any relevant access right callbacks +// + +#define RS_ACCESS_DUP_OBJECT 0U +#define RS_ACCESS_NICE 1U +#define RS_ACCESS_DEBUG 2U +#define RS_ACCESS_COUNT 3U + + +/****************************************************************************/ +/* Access right data structures */ +/****************************************************************************/ + +/*! + * @brief A type that can be used to represent any access right. + */ +typedef NvU16 RsAccessRight; + +/*! + * @brief An internal type used to represent one limb in an access right mask. + */ +typedef NvU32 RsAccessLimb; +#define SDK_RS_ACCESS_LIMB_BITS 32 + +/*! + * @brief The number of limbs in the RS_ACCESS_MASK struct. + */ +#define SDK_RS_ACCESS_MAX_LIMBS 1 + +/*! + * @brief The maximum number of possible access rights supported by the + * current data structure definition. + * + * You probably want RS_ACCESS_COUNT instead, which is the number of actual + * access rights defined. + */ +#define SDK_RS_ACCESS_MAX_COUNT (0x20) /* finn: Evaluated from "(SDK_RS_ACCESS_LIMB_BITS * SDK_RS_ACCESS_MAX_LIMBS)" */ + +/** + * @brief A struct representing a set of access rights. + * + * Note that the values of bit positions larger than RS_ACCESS_COUNT is + * undefined, and should not be assumed to be 0 (see RS_ACCESS_MASK_FILL). + */ +typedef struct RS_ACCESS_MASK { + RsAccessLimb limbs[SDK_RS_ACCESS_MAX_LIMBS]; +} RS_ACCESS_MASK; + +/** + * @brief A struct representing auxiliary information about each access right. + */ +typedef struct RS_ACCESS_INFO { + NvU32 flags; +} RS_ACCESS_INFO; + + +/****************************************************************************/ +/* Access right macros */ +/****************************************************************************/ + +#define SDK_RS_ACCESS_LIMB_INDEX(index) ((index) / SDK_RS_ACCESS_LIMB_BITS) +#define SDK_RS_ACCESS_LIMB_POS(index) ((index) % SDK_RS_ACCESS_LIMB_BITS) + +#define SDK_RS_ACCESS_LIMB_ELT(pAccessMask, index) \ + ((pAccessMask)->limbs[SDK_RS_ACCESS_LIMB_INDEX(index)]) +#define SDK_RS_ACCESS_OFFSET_MASK(index) \ + NVBIT_TYPE(SDK_RS_ACCESS_LIMB_POS(index), RsAccessLimb) + +/*! + * @brief Checks that accessRight represents a valid access right. + * + * The valid range of access rights is [0, RS_ACCESS_COUNT). + * + * @param[in] accessRight The access right value to check + * + * @return true if accessRight is valid + * @return false otherwise + */ +#define RS_ACCESS_BOUNDS_CHECK(accessRight) \ + (accessRight < RS_ACCESS_COUNT) + +/*! + * @brief Test whether an access right is present in a set + * + * @param[in] pAccessMask The set of access rights to read + * @param[in] index The access right to examine + * + * @return NV_TRUE if the access right specified by index was present in the set, + * and NV_FALSE otherwise + */ +#define RS_ACCESS_MASK_TEST(pAccessMask, index) \ + (RS_ACCESS_BOUNDS_CHECK(index) && \ + (SDK_RS_ACCESS_LIMB_ELT(pAccessMask, index) & SDK_RS_ACCESS_OFFSET_MASK(index)) != 0) + +/*! + * @brief Add an access right to a mask + * + * @param[in] pAccessMask The set of access rights to modify + * @param[in] index The access right to set + */ +#define RS_ACCESS_MASK_ADD(pAccessMask, index) \ + do \ + { \ + if (RS_ACCESS_BOUNDS_CHECK(index)) { \ + SDK_RS_ACCESS_LIMB_ELT(pAccessMask, index) |= SDK_RS_ACCESS_OFFSET_MASK(index); \ + } \ + } while (NV_FALSE) + +/*! + * @brief Remove an access right from a mask + * + * @param[in] pAccessMask The set of access rights to modify + * @param[in] index The access right to unset + */ +#define RS_ACCESS_MASK_REMOVE(pAccessMask, index) \ + do \ + { \ + if (RS_ACCESS_BOUNDS_CHECK(index)) { \ + SDK_RS_ACCESS_LIMB_ELT(pAccessMask, index) &= ~SDK_RS_ACCESS_OFFSET_MASK(index); \ + } \ + } while (NV_FALSE) + +/*! + * @brief Performs an in-place union between two access right masks + * + * @param[in,out] pMaskOut The access rights mask to be updated + * @param[in] pMaskIn The set of access rights to be added to pMaskOut + */ +#define RS_ACCESS_MASK_UNION(pMaskOut, pMaskIn) \ + do \ + { \ + NvLength limb; \ + for (limb = 0; limb < SDK_RS_ACCESS_MAX_LIMBS; limb++) \ + { \ + SDK_RS_ACCESS_LIMB_ELT(pMaskOut, limb) |= SDK_RS_ACCESS_LIMB_ELT(pMaskIn, limb); \ + } \ + } while (NV_FALSE) + +/*! + * @brief Performs an in-place subtract of one mask's rights from another + * + * @param[in,out] pMaskOut The access rights mask to be updated + * @param[in] pMaskIn The set of access rights to be removed from pMaskOut + */ +#define RS_ACCESS_MASK_SUBTRACT(pMaskOut, pMaskIn) \ + do \ + { \ + NvLength limb; \ + for (limb = 0; limb < SDK_RS_ACCESS_MAX_LIMBS; limb++) \ + { \ + SDK_RS_ACCESS_LIMB_ELT(pMaskOut, limb) &= ~SDK_RS_ACCESS_LIMB_ELT(pMaskIn, limb); \ + } \ + } while (NV_FALSE) + +/*! + * @brief Removes all rights from an access rights mask + * + * @param[in,out] pAccessMask The access rights mask to be updated + */ +#define RS_ACCESS_MASK_CLEAR(pAccessMask) \ + do \ + { \ + portMemSet(pAccessMask, 0, sizeof(*pAccessMask)); \ + } while (NV_FALSE) + +/*! + * @brief Adds all rights to an access rights mask + * + * @param[in,out] pAccessMask The access rights mask to be updated + */ +#define RS_ACCESS_MASK_FILL(pAccessMask) \ + do \ + { \ + portMemSet(pAccessMask, 0xff, sizeof(*pAccessMask)); \ + } while (NV_FALSE) + + +/****************************************************************************/ +/* Share definitions */ +/****************************************************************************/ + +// +// The usage of Share Policy and the meaning of each share type is documented in +// resman/docs/rmapi/resource_server/rm_capabilities.adoc +// +#define RS_SHARE_TYPE_NONE (0U) +#define RS_SHARE_TYPE_ALL (1U) +#define RS_SHARE_TYPE_OS_SECURITY_TOKEN (2U) +#define RS_SHARE_TYPE_CLIENT (3U) +#define RS_SHARE_TYPE_PID (4U) +#define RS_SHARE_TYPE_SMC_PARTITION (5U) +#define RS_SHARE_TYPE_GPU (6U) +#define RS_SHARE_TYPE_FM_CLIENT (7U) +// Must be last. Update when a new SHARE_TYPE is added +#define RS_SHARE_TYPE_MAX (8U) + + +// +// Use Revoke to remove an existing policy from the list. +// Allow is based on OR logic, Require is based on AND logic. +// To share a right, at least one Allow (non-Require) must match, and all Require must pass. +// If Compose is specified, policies will be added to the list. Otherwise, they will replace the list. +// +#define RS_SHARE_ACTION_FLAG_REVOKE NVBIT(0) +#define RS_SHARE_ACTION_FLAG_REQUIRE NVBIT(1) +#define RS_SHARE_ACTION_FLAG_COMPOSE NVBIT(2) + +/****************************************************************************/ +/* Share flag data structures */ +/****************************************************************************/ + +typedef struct RS_SHARE_POLICY { + NvU32 target; + RS_ACCESS_MASK accessMask; + NvU16 type; ///< RS_SHARE_TYPE_ + NvU8 action; ///< RS_SHARE_ACTION_ +} RS_SHARE_POLICY; diff --git a/userspace/sdks/nv525/nvml/nvml.h b/userspace/sdks/nv525/nvml/nvml.h new file mode 100644 index 0000000..03e092d --- /dev/null +++ b/userspace/sdks/nv525/nvml/nvml.h @@ -0,0 +1,9664 @@ +/*** NVML VERSION: 12.0.76 ***/ +/*** From https://api.anaconda.org/download/nvidia/cuda-nvml-dev/12.0.76/linux-64/cuda-nvml-dev-12.0.76-0.tar.bz2 ***/ +/* + * Copyright 1993-2022 NVIDIA Corporation. All rights reserved. + * + * NOTICE TO USER: + * + * This source code is subject to NVIDIA ownership rights under U.S. and + * international Copyright laws. Users and possessors of this source code + * are hereby granted a nonexclusive, royalty-free license to use this code + * in individual and commercial software. + * + * NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE + * CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR + * IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE. + * IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS + * OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE + * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE + * OR PERFORMANCE OF THIS SOURCE CODE. + * + * U.S. Government End Users. This source code is a "commercial item" as + * that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of + * "commercial computer software" and "commercial computer software + * documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995) + * and is provided to the U.S. Government only as a commercial end item. + * Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through + * 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the + * source code with only those rights set forth herein. + * + * Any use of this source code in individual and commercial software must + * include, in the user documentation and internal comments to the code, + * the above Disclaimer and U.S. Government End Users Notice. + */ + +/* +NVML API Reference + +The NVIDIA Management Library (NVML) is a C-based programmatic interface for monitoring and +managing various states within NVIDIA Tesla &tm; GPUs. It is intended to be a platform for building +3rd party applications, and is also the underlying library for the NVIDIA-supported nvidia-smi +tool. NVML is thread-safe so it is safe to make simultaneous NVML calls from multiple threads. + +API Documentation + +Supported platforms: +- Windows: Windows Server 2008 R2 64bit, Windows Server 2012 R2 64bit, Windows 7 64bit, Windows 8 64bit, Windows 10 64bit +- Linux: 32-bit and 64-bit +- Hypervisors: Windows Server 2008R2/2012 Hyper-V 64bit, Citrix XenServer 6.2 SP1+, VMware ESX 5.1/5.5 + +Supported products: +- Full Support + - All Tesla products, starting with the Fermi architecture + - All Quadro products, starting with the Fermi architecture + - All vGPU Software products, starting with the Kepler architecture + - Selected GeForce Titan products +- Limited Support + - All Geforce products, starting with the Fermi architecture + +The NVML library can be found at \%ProgramW6432\%\\"NVIDIA Corporation"\\NVSMI\\ on Windows. It is +not be added to the system path by default. To dynamically link to NVML, add this path to the PATH +environmental variable. To dynamically load NVML, call LoadLibrary with this path. + +On Linux the NVML library will be found on the standard library path. For 64 bit Linux, both the 32 bit +and 64 bit NVML libraries will be installed. + +Online documentation for this library is available at http://docs.nvidia.com/deploy/nvml-api/index.html +*/ + +#ifndef __nvml_nvml_h__ +#define __nvml_nvml_h__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * On Windows, set up methods for DLL export + * define NVML_STATIC_IMPORT when using nvml_loader library + */ +#if defined _WINDOWS + #if !defined NVML_STATIC_IMPORT + #if defined NVML_LIB_EXPORT + #define DECLDIR __declspec(dllexport) + #else + #define DECLDIR __declspec(dllimport) + #endif + #else + #define DECLDIR + #endif +#else + #define DECLDIR +#endif + +/** + * NVML API versioning support + */ +#define NVML_API_VERSION 11 +#define NVML_API_VERSION_STR "11" +/** + * Defining NVML_NO_UNVERSIONED_FUNC_DEFS will disable "auto upgrading" of APIs. + * e.g. the user will have to call nvmlInit_v2 instead of nvmlInit. Enable this + * guard if you need to support older versions of the API + */ +#ifndef NVML_NO_UNVERSIONED_FUNC_DEFS + #define nvmlInit nvmlInit_v2 + #define nvmlDeviceGetPciInfo nvmlDeviceGetPciInfo_v3 + #define nvmlDeviceGetCount nvmlDeviceGetCount_v2 + #define nvmlDeviceGetHandleByIndex nvmlDeviceGetHandleByIndex_v2 + #define nvmlDeviceGetHandleByPciBusId nvmlDeviceGetHandleByPciBusId_v2 + #define nvmlDeviceGetNvLinkRemotePciInfo nvmlDeviceGetNvLinkRemotePciInfo_v2 + #define nvmlDeviceRemoveGpu nvmlDeviceRemoveGpu_v2 + #define nvmlDeviceGetGridLicensableFeatures nvmlDeviceGetGridLicensableFeatures_v4 + #define nvmlEventSetWait nvmlEventSetWait_v2 + #define nvmlDeviceGetAttributes nvmlDeviceGetAttributes_v2 + #define nvmlComputeInstanceGetInfo nvmlComputeInstanceGetInfo_v2 + #define nvmlDeviceGetComputeRunningProcesses nvmlDeviceGetComputeRunningProcesses_v3 + #define nvmlDeviceGetGraphicsRunningProcesses nvmlDeviceGetGraphicsRunningProcesses_v3 + #define nvmlDeviceGetMPSComputeRunningProcesses nvmlDeviceGetMPSComputeRunningProcesses_v3 + #define nvmlBlacklistDeviceInfo_t nvmlExcludedDeviceInfo_t + #define nvmlGetBlacklistDeviceCount nvmlGetExcludedDeviceCount + #define nvmlGetBlacklistDeviceInfoByIndex nvmlGetExcludedDeviceInfoByIndex + #define nvmlDeviceGetGpuInstancePossiblePlacements nvmlDeviceGetGpuInstancePossiblePlacements_v2 + #define nvmlVgpuInstanceGetLicenseInfo nvmlVgpuInstanceGetLicenseInfo_v2 +#endif // #ifndef NVML_NO_UNVERSIONED_FUNC_DEFS + +#define NVML_STRUCT_VERSION(data, ver) (unsigned int)(sizeof(nvml ## data ## _v ## ver ## _t) | \ + (ver << 24U)) + +/***************************************************************************************************/ +/** @defgroup nvmlDeviceStructs Device Structs + * @{ + */ +/***************************************************************************************************/ + +/** + * Special constant that some fields take when they are not available. + * Used when only part of the struct is not available. + * + * Each structure explicitly states when to check for this value. + */ +#define NVML_VALUE_NOT_AVAILABLE (-1) + +typedef struct nvmlDevice_st* nvmlDevice_t; + +/** + * Buffer size guaranteed to be large enough for pci bus id + */ +#define NVML_DEVICE_PCI_BUS_ID_BUFFER_SIZE 32 + +/** + * Buffer size guaranteed to be large enough for pci bus id for ::busIdLegacy + */ +#define NVML_DEVICE_PCI_BUS_ID_BUFFER_V2_SIZE 16 + +/** + * PCI information about a GPU device. + */ +typedef struct nvmlPciInfo_st +{ + char busIdLegacy[NVML_DEVICE_PCI_BUS_ID_BUFFER_V2_SIZE]; //!< The legacy tuple domain:bus:device.function PCI identifier (& NULL terminator) + unsigned int domain; //!< The PCI domain on which the device's bus resides, 0 to 0xffffffff + unsigned int bus; //!< The bus on which the device resides, 0 to 0xff + unsigned int device; //!< The device's id on the bus, 0 to 31 + unsigned int pciDeviceId; //!< The combined 16-bit device id and 16-bit vendor id + + // Added in NVML 2.285 API + unsigned int pciSubSystemId; //!< The 32-bit Sub System Device ID + + char busId[NVML_DEVICE_PCI_BUS_ID_BUFFER_SIZE]; //!< The tuple domain:bus:device.function PCI identifier (& NULL terminator) +} nvmlPciInfo_t; + +/** + * PCI format string for ::busIdLegacy + */ +#define NVML_DEVICE_PCI_BUS_ID_LEGACY_FMT "%04X:%02X:%02X.0" + +/** + * PCI format string for ::busId + */ +#define NVML_DEVICE_PCI_BUS_ID_FMT "%08X:%02X:%02X.0" + +/** + * Utility macro for filling the pci bus id format from a nvmlPciInfo_t + */ +#define NVML_DEVICE_PCI_BUS_ID_FMT_ARGS(pciInfo) (pciInfo)->domain, \ + (pciInfo)->bus, \ + (pciInfo)->device + +/** + * Detailed ECC error counts for a device. + * + * @deprecated Different GPU families can have different memory error counters + * See \ref nvmlDeviceGetMemoryErrorCounter + */ +typedef struct nvmlEccErrorCounts_st +{ + unsigned long long l1Cache; //!< L1 cache errors + unsigned long long l2Cache; //!< L2 cache errors + unsigned long long deviceMemory; //!< Device memory errors + unsigned long long registerFile; //!< Register file errors +} nvmlEccErrorCounts_t; + +/** + * Utilization information for a device. + * Each sample period may be between 1 second and 1/6 second, depending on the product being queried. + */ +typedef struct nvmlUtilization_st +{ + unsigned int gpu; //!< Percent of time over the past sample period during which one or more kernels was executing on the GPU + unsigned int memory; //!< Percent of time over the past sample period during which global (device) memory was being read or written +} nvmlUtilization_t; + +/** + * Memory allocation information for a device (v1). + * The total amount is equal to the sum of the amounts of free and used memory. + */ +typedef struct nvmlMemory_st +{ + unsigned long long total; //!< Total physical device memory (in bytes) + unsigned long long free; //!< Unallocated device memory (in bytes) + unsigned long long used; //!< Sum of Reserved and Allocated device memory (in bytes). + //!< Note that the driver/GPU always sets aside a small amount of memory for bookkeeping +} nvmlMemory_t; + +/** + * Memory allocation information for a device (v2). + * + * Version 2 adds versioning for the struct and the amount of system-reserved memory as an output. + * @note The \ref nvmlMemory_v2_t.used amount also includes the \ref nvmlMemory_v2_t.reserved amount. + */ +typedef struct nvmlMemory_v2_st +{ + unsigned int version; //!< Structure format version (must be 2) + unsigned long long total; //!< Total physical device memory (in bytes) + unsigned long long reserved; //!< Device memory (in bytes) reserved for system use (driver or firmware) + unsigned long long free; //!< Unallocated device memory (in bytes) + unsigned long long used; //!< Allocated device memory (in bytes). Note that the driver/GPU always sets aside a small amount of memory for bookkeeping +} nvmlMemory_v2_t; + +#define nvmlMemory_v2 NVML_STRUCT_VERSION(Memory, 2) + +/** + * BAR1 Memory allocation Information for a device + */ +typedef struct nvmlBAR1Memory_st +{ + unsigned long long bar1Total; //!< Total BAR1 Memory (in bytes) + unsigned long long bar1Free; //!< Unallocated BAR1 Memory (in bytes) + unsigned long long bar1Used; //!< Allocated Used Memory (in bytes) +}nvmlBAR1Memory_t; + +/** + * Information about running compute processes on the GPU, legacy version + * for older versions of the API. + */ +typedef struct nvmlProcessInfo_v1_st +{ + unsigned int pid; //!< Process ID + unsigned long long usedGpuMemory; //!< Amount of used GPU memory in bytes. + //! Under WDDM, \ref NVML_VALUE_NOT_AVAILABLE is always reported + //! because Windows KMD manages all the memory and not the NVIDIA driver +} nvmlProcessInfo_v1_t; + +/** + * Information about running compute processes on the GPU + */ +typedef struct nvmlProcessInfo_v2_st +{ + unsigned int pid; //!< Process ID + unsigned long long usedGpuMemory; //!< Amount of used GPU memory in bytes. + //! Under WDDM, \ref NVML_VALUE_NOT_AVAILABLE is always reported + //! because Windows KMD manages all the memory and not the NVIDIA driver + unsigned int gpuInstanceId; //!< If MIG is enabled, stores a valid GPU instance ID. gpuInstanceId is set to + // 0xFFFFFFFF otherwise. + unsigned int computeInstanceId; //!< If MIG is enabled, stores a valid compute instance ID. computeInstanceId is set to + // 0xFFFFFFFF otherwise. +} nvmlProcessInfo_v2_t; + +/** + * Information about running compute processes on the GPU + * Version 2 adds versioning for the struct + */ +typedef struct nvmlProcessInfo_st +{ + unsigned int pid; //!< Process ID + unsigned long long usedGpuMemory; //!< Amount of used GPU memory in bytes. + //! Under WDDM, \ref NVML_VALUE_NOT_AVAILABLE is always reported + //! because Windows KMD manages all the memory and not the NVIDIA driver + unsigned int gpuInstanceId; //!< If MIG is enabled, stores a valid GPU instance ID. gpuInstanceId is set to + // 0xFFFFFFFF otherwise. + unsigned int computeInstanceId; //!< If MIG is enabled, stores a valid compute instance ID. computeInstanceId is set to + // 0xFFFFFFFF otherwise. +} nvmlProcessInfo_t; + +typedef struct nvmlDeviceAttributes_st +{ + unsigned int multiprocessorCount; //!< Streaming Multiprocessor count + unsigned int sharedCopyEngineCount; //!< Shared Copy Engine count + unsigned int sharedDecoderCount; //!< Shared Decoder Engine count + unsigned int sharedEncoderCount; //!< Shared Encoder Engine count + unsigned int sharedJpegCount; //!< Shared JPEG Engine count + unsigned int sharedOfaCount; //!< Shared OFA Engine count + unsigned int gpuInstanceSliceCount; //!< GPU instance slice count + unsigned int computeInstanceSliceCount; //!< Compute instance slice count + unsigned long long memorySizeMB; //!< Device memory size (in MiB) +} nvmlDeviceAttributes_t; + +/** + * Possible values that classify the remap availability for each bank. The max + * field will contain the number of banks that have maximum remap availability + * (all reserved rows are available). None means that there are no reserved + * rows available. + */ +typedef struct nvmlRowRemapperHistogramValues_st +{ + unsigned int max; + unsigned int high; + unsigned int partial; + unsigned int low; + unsigned int none; +} nvmlRowRemapperHistogramValues_t; + +/** + * Enum to represent type of bridge chip + */ +typedef enum nvmlBridgeChipType_enum +{ + NVML_BRIDGE_CHIP_PLX = 0, + NVML_BRIDGE_CHIP_BRO4 = 1 +}nvmlBridgeChipType_t; + +/** + * Maximum number of NvLink links supported + */ +#define NVML_NVLINK_MAX_LINKS 18 + +/** + * Enum to represent the NvLink utilization counter packet units + */ +typedef enum nvmlNvLinkUtilizationCountUnits_enum +{ + NVML_NVLINK_COUNTER_UNIT_CYCLES = 0, // count by cycles + NVML_NVLINK_COUNTER_UNIT_PACKETS = 1, // count by packets + NVML_NVLINK_COUNTER_UNIT_BYTES = 2, // count by bytes + NVML_NVLINK_COUNTER_UNIT_RESERVED = 3, // count reserved for internal use + // this must be last + NVML_NVLINK_COUNTER_UNIT_COUNT +} nvmlNvLinkUtilizationCountUnits_t; + +/** + * Enum to represent the NvLink utilization counter packet types to count + * ** this is ONLY applicable with the units as packets or bytes + * ** as specified in \a nvmlNvLinkUtilizationCountUnits_t + * ** all packet filter descriptions are target GPU centric + * ** these can be "OR'd" together + */ +typedef enum nvmlNvLinkUtilizationCountPktTypes_enum +{ + NVML_NVLINK_COUNTER_PKTFILTER_NOP = 0x1, // no operation packets + NVML_NVLINK_COUNTER_PKTFILTER_READ = 0x2, // read packets + NVML_NVLINK_COUNTER_PKTFILTER_WRITE = 0x4, // write packets + NVML_NVLINK_COUNTER_PKTFILTER_RATOM = 0x8, // reduction atomic requests + NVML_NVLINK_COUNTER_PKTFILTER_NRATOM = 0x10, // non-reduction atomic requests + NVML_NVLINK_COUNTER_PKTFILTER_FLUSH = 0x20, // flush requests + NVML_NVLINK_COUNTER_PKTFILTER_RESPDATA = 0x40, // responses with data + NVML_NVLINK_COUNTER_PKTFILTER_RESPNODATA = 0x80, // responses without data + NVML_NVLINK_COUNTER_PKTFILTER_ALL = 0xFF // all packets +} nvmlNvLinkUtilizationCountPktTypes_t; + +/** + * Struct to define the NVLINK counter controls + */ +typedef struct nvmlNvLinkUtilizationControl_st +{ + nvmlNvLinkUtilizationCountUnits_t units; + nvmlNvLinkUtilizationCountPktTypes_t pktfilter; +} nvmlNvLinkUtilizationControl_t; + +/** + * Enum to represent NvLink queryable capabilities + */ +typedef enum nvmlNvLinkCapability_enum +{ + NVML_NVLINK_CAP_P2P_SUPPORTED = 0, // P2P over NVLink is supported + NVML_NVLINK_CAP_SYSMEM_ACCESS = 1, // Access to system memory is supported + NVML_NVLINK_CAP_P2P_ATOMICS = 2, // P2P atomics are supported + NVML_NVLINK_CAP_SYSMEM_ATOMICS= 3, // System memory atomics are supported + NVML_NVLINK_CAP_SLI_BRIDGE = 4, // SLI is supported over this link + NVML_NVLINK_CAP_VALID = 5, // Link is supported on this device + // should be last + NVML_NVLINK_CAP_COUNT +} nvmlNvLinkCapability_t; + +/** + * Enum to represent NvLink queryable error counters + */ +typedef enum nvmlNvLinkErrorCounter_enum +{ + NVML_NVLINK_ERROR_DL_REPLAY = 0, // Data link transmit replay error counter + NVML_NVLINK_ERROR_DL_RECOVERY = 1, // Data link transmit recovery error counter + NVML_NVLINK_ERROR_DL_CRC_FLIT = 2, // Data link receive flow control digit CRC error counter + NVML_NVLINK_ERROR_DL_CRC_DATA = 3, // Data link receive data CRC error counter + NVML_NVLINK_ERROR_DL_ECC_DATA = 4, // Data link receive data ECC error counter + + // this must be last + NVML_NVLINK_ERROR_COUNT +} nvmlNvLinkErrorCounter_t; + +/** + * Enum to represent NvLink's remote device type + */ +typedef enum nvmlIntNvLinkDeviceType_enum +{ + NVML_NVLINK_DEVICE_TYPE_GPU = 0x00, + NVML_NVLINK_DEVICE_TYPE_IBMNPU = 0x01, + NVML_NVLINK_DEVICE_TYPE_SWITCH = 0x02, + NVML_NVLINK_DEVICE_TYPE_UNKNOWN = 0xFF +} nvmlIntNvLinkDeviceType_t; + +/** + * Represents level relationships within a system between two GPUs + * The enums are spaced to allow for future relationships + */ +typedef enum nvmlGpuLevel_enum +{ + NVML_TOPOLOGY_INTERNAL = 0, // e.g. Tesla K80 + NVML_TOPOLOGY_SINGLE = 10, // all devices that only need traverse a single PCIe switch + NVML_TOPOLOGY_MULTIPLE = 20, // all devices that need not traverse a host bridge + NVML_TOPOLOGY_HOSTBRIDGE = 30, // all devices that are connected to the same host bridge + NVML_TOPOLOGY_NODE = 40, // all devices that are connected to the same NUMA node but possibly multiple host bridges + NVML_TOPOLOGY_SYSTEM = 50 // all devices in the system + + // there is purposefully no COUNT here because of the need for spacing above +} nvmlGpuTopologyLevel_t; + +/* Compatibility for CPU->NODE renaming */ +#define NVML_TOPOLOGY_CPU NVML_TOPOLOGY_NODE + +/* P2P Capability Index Status*/ +typedef enum nvmlGpuP2PStatus_enum +{ + NVML_P2P_STATUS_OK = 0, + NVML_P2P_STATUS_CHIPSET_NOT_SUPPORED, + NVML_P2P_STATUS_GPU_NOT_SUPPORTED, + NVML_P2P_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED, + NVML_P2P_STATUS_DISABLED_BY_REGKEY, + NVML_P2P_STATUS_NOT_SUPPORTED, + NVML_P2P_STATUS_UNKNOWN + +} nvmlGpuP2PStatus_t; + +/* P2P Capability Index*/ +typedef enum nvmlGpuP2PCapsIndex_enum +{ + NVML_P2P_CAPS_INDEX_READ = 0, + NVML_P2P_CAPS_INDEX_WRITE, + NVML_P2P_CAPS_INDEX_NVLINK, + NVML_P2P_CAPS_INDEX_ATOMICS, + NVML_P2P_CAPS_INDEX_PROP, + NVML_P2P_CAPS_INDEX_UNKNOWN +}nvmlGpuP2PCapsIndex_t; + +/** + * Maximum limit on Physical Bridges per Board + */ +#define NVML_MAX_PHYSICAL_BRIDGE (128) + +/** + * Information about the Bridge Chip Firmware + */ +typedef struct nvmlBridgeChipInfo_st +{ + nvmlBridgeChipType_t type; //!< Type of Bridge Chip + unsigned int fwVersion; //!< Firmware Version. 0=Version is unavailable +}nvmlBridgeChipInfo_t; + +/** + * This structure stores the complete Hierarchy of the Bridge Chip within the board. The immediate + * bridge is stored at index 0 of bridgeInfoList, parent to immediate bridge is at index 1 and so forth. + */ +typedef struct nvmlBridgeChipHierarchy_st +{ + unsigned char bridgeCount; //!< Number of Bridge Chips on the Board + nvmlBridgeChipInfo_t bridgeChipInfo[NVML_MAX_PHYSICAL_BRIDGE]; //!< Hierarchy of Bridge Chips on the board +}nvmlBridgeChipHierarchy_t; + +/** + * Represents Type of Sampling Event + */ +typedef enum nvmlSamplingType_enum +{ + NVML_TOTAL_POWER_SAMPLES = 0, //!< To represent total power drawn by GPU + NVML_GPU_UTILIZATION_SAMPLES = 1, //!< To represent percent of time during which one or more kernels was executing on the GPU + NVML_MEMORY_UTILIZATION_SAMPLES = 2, //!< To represent percent of time during which global (device) memory was being read or written + NVML_ENC_UTILIZATION_SAMPLES = 3, //!< To represent percent of time during which NVENC remains busy + NVML_DEC_UTILIZATION_SAMPLES = 4, //!< To represent percent of time during which NVDEC remains busy + NVML_PROCESSOR_CLK_SAMPLES = 5, //!< To represent processor clock samples + NVML_MEMORY_CLK_SAMPLES = 6, //!< To represent memory clock samples + + // Keep this last + NVML_SAMPLINGTYPE_COUNT +}nvmlSamplingType_t; + +/** + * Represents the queryable PCIe utilization counters + */ +typedef enum nvmlPcieUtilCounter_enum +{ + NVML_PCIE_UTIL_TX_BYTES = 0, // 1KB granularity + NVML_PCIE_UTIL_RX_BYTES = 1, // 1KB granularity + + // Keep this last + NVML_PCIE_UTIL_COUNT +} nvmlPcieUtilCounter_t; + +/** + * Represents the type for sample value returned + */ +typedef enum nvmlValueType_enum +{ + NVML_VALUE_TYPE_DOUBLE = 0, + NVML_VALUE_TYPE_UNSIGNED_INT = 1, + NVML_VALUE_TYPE_UNSIGNED_LONG = 2, + NVML_VALUE_TYPE_UNSIGNED_LONG_LONG = 3, + NVML_VALUE_TYPE_SIGNED_LONG_LONG = 4, + + // Keep this last + NVML_VALUE_TYPE_COUNT +}nvmlValueType_t; + + +/** + * Union to represent different types of Value + */ +typedef union nvmlValue_st +{ + double dVal; //!< If the value is double + unsigned int uiVal; //!< If the value is unsigned int + unsigned long ulVal; //!< If the value is unsigned long + unsigned long long ullVal; //!< If the value is unsigned long long + signed long long sllVal; //!< If the value is signed long long +}nvmlValue_t; + +/** + * Information for Sample + */ +typedef struct nvmlSample_st +{ + unsigned long long timeStamp; //!< CPU Timestamp in microseconds + nvmlValue_t sampleValue; //!< Sample Value +}nvmlSample_t; + +/** + * Represents type of perf policy for which violation times can be queried + */ +typedef enum nvmlPerfPolicyType_enum +{ + NVML_PERF_POLICY_POWER = 0, //!< How long did power violations cause the GPU to be below application clocks + NVML_PERF_POLICY_THERMAL = 1, //!< How long did thermal violations cause the GPU to be below application clocks + NVML_PERF_POLICY_SYNC_BOOST = 2, //!< How long did sync boost cause the GPU to be below application clocks + NVML_PERF_POLICY_BOARD_LIMIT = 3, //!< How long did the board limit cause the GPU to be below application clocks + NVML_PERF_POLICY_LOW_UTILIZATION = 4, //!< How long did low utilization cause the GPU to be below application clocks + NVML_PERF_POLICY_RELIABILITY = 5, //!< How long did the board reliability limit cause the GPU to be below application clocks + + NVML_PERF_POLICY_TOTAL_APP_CLOCKS = 10, //!< Total time the GPU was held below application clocks by any limiter (0 - 5 above) + NVML_PERF_POLICY_TOTAL_BASE_CLOCKS = 11, //!< Total time the GPU was held below base clocks + + // Keep this last + NVML_PERF_POLICY_COUNT +}nvmlPerfPolicyType_t; + +/** + * Struct to hold perf policy violation status data + */ +typedef struct nvmlViolationTime_st +{ + unsigned long long referenceTime; //!< referenceTime represents CPU timestamp in microseconds + unsigned long long violationTime; //!< violationTime in Nanoseconds +}nvmlViolationTime_t; + +#define NVML_MAX_THERMAL_SENSORS_PER_GPU 3 + +typedef enum +{ + NVML_THERMAL_TARGET_NONE = 0, + NVML_THERMAL_TARGET_GPU = 1, //!< GPU core temperature requires NvPhysicalGpuHandle + NVML_THERMAL_TARGET_MEMORY = 2, //!< GPU memory temperature requires NvPhysicalGpuHandle + NVML_THERMAL_TARGET_POWER_SUPPLY = 4, //!< GPU power supply temperature requires NvPhysicalGpuHandle + NVML_THERMAL_TARGET_BOARD = 8, //!< GPU board ambient temperature requires NvPhysicalGpuHandle + NVML_THERMAL_TARGET_VCD_BOARD = 9, //!< Visual Computing Device Board temperature requires NvVisualComputingDeviceHandle + NVML_THERMAL_TARGET_VCD_INLET = 10, //!< Visual Computing Device Inlet temperature requires NvVisualComputingDeviceHandle + NVML_THERMAL_TARGET_VCD_OUTLET = 11, //!< Visual Computing Device Outlet temperature requires NvVisualComputingDeviceHandle + + NVML_THERMAL_TARGET_ALL = 15, + NVML_THERMAL_TARGET_UNKNOWN = -1, +} nvmlThermalTarget_t; + +typedef enum +{ + NVML_THERMAL_CONTROLLER_NONE = 0, + NVML_THERMAL_CONTROLLER_GPU_INTERNAL, + NVML_THERMAL_CONTROLLER_ADM1032, + NVML_THERMAL_CONTROLLER_ADT7461, + NVML_THERMAL_CONTROLLER_MAX6649, + NVML_THERMAL_CONTROLLER_MAX1617, + NVML_THERMAL_CONTROLLER_LM99, + NVML_THERMAL_CONTROLLER_LM89, + NVML_THERMAL_CONTROLLER_LM64, + NVML_THERMAL_CONTROLLER_G781, + NVML_THERMAL_CONTROLLER_ADT7473, + NVML_THERMAL_CONTROLLER_SBMAX6649, + NVML_THERMAL_CONTROLLER_VBIOSEVT, + NVML_THERMAL_CONTROLLER_OS, + NVML_THERMAL_CONTROLLER_NVSYSCON_CANOAS, + NVML_THERMAL_CONTROLLER_NVSYSCON_E551, + NVML_THERMAL_CONTROLLER_MAX6649R, + NVML_THERMAL_CONTROLLER_ADT7473S, + NVML_THERMAL_CONTROLLER_UNKNOWN = -1, +} nvmlThermalController_t; + +typedef struct +{ + unsigned int count; + struct + { + nvmlThermalController_t controller; + int defaultMinTemp; + int defaultMaxTemp; + int currentTemp; + nvmlThermalTarget_t target; + } sensor[NVML_MAX_THERMAL_SENSORS_PER_GPU]; + +} nvmlGpuThermalSettings_t; + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlDeviceEnumvs Device Enums + * @{ + */ +/***************************************************************************************************/ + +/** + * Generic enable/disable enum. + */ +typedef enum nvmlEnableState_enum +{ + NVML_FEATURE_DISABLED = 0, //!< Feature disabled + NVML_FEATURE_ENABLED = 1 //!< Feature enabled +} nvmlEnableState_t; + +//! Generic flag used to specify the default behavior of some functions. See description of particular functions for details. +#define nvmlFlagDefault 0x00 +//! Generic flag used to force some behavior. See description of particular functions for details. +#define nvmlFlagForce 0x01 + +/** + * * The Brand of the GPU + * */ +typedef enum nvmlBrandType_enum +{ + NVML_BRAND_UNKNOWN = 0, + NVML_BRAND_QUADRO = 1, + NVML_BRAND_TESLA = 2, + NVML_BRAND_NVS = 3, + NVML_BRAND_GRID = 4, // Deprecated from API reporting. Keeping definition for backward compatibility. + NVML_BRAND_GEFORCE = 5, + NVML_BRAND_TITAN = 6, + NVML_BRAND_NVIDIA_VAPPS = 7, // NVIDIA Virtual Applications + NVML_BRAND_NVIDIA_VPC = 8, // NVIDIA Virtual PC + NVML_BRAND_NVIDIA_VCS = 9, // NVIDIA Virtual Compute Server + NVML_BRAND_NVIDIA_VWS = 10, // NVIDIA RTX Virtual Workstation + NVML_BRAND_NVIDIA_CLOUD_GAMING = 11, // NVIDIA Cloud Gaming + NVML_BRAND_NVIDIA_VGAMING = NVML_BRAND_NVIDIA_CLOUD_GAMING, // Deprecated from API reporting. Keeping definition for backward compatibility. + NVML_BRAND_QUADRO_RTX = 12, + NVML_BRAND_NVIDIA_RTX = 13, + NVML_BRAND_NVIDIA = 14, + NVML_BRAND_GEFORCE_RTX = 15, // Unused + NVML_BRAND_TITAN_RTX = 16, // Unused + + // Keep this last + NVML_BRAND_COUNT +} nvmlBrandType_t; + +/** + * Temperature thresholds. + */ +typedef enum nvmlTemperatureThresholds_enum +{ + NVML_TEMPERATURE_THRESHOLD_SHUTDOWN = 0, // Temperature at which the GPU will + // shut down for HW protection + NVML_TEMPERATURE_THRESHOLD_SLOWDOWN = 1, // Temperature at which the GPU will + // begin HW slowdown + NVML_TEMPERATURE_THRESHOLD_MEM_MAX = 2, // Memory Temperature at which the GPU will + // begin SW slowdown + NVML_TEMPERATURE_THRESHOLD_GPU_MAX = 3, // GPU Temperature at which the GPU + // can be throttled below base clock + NVML_TEMPERATURE_THRESHOLD_ACOUSTIC_MIN = 4, // Minimum GPU Temperature that can be + // set as acoustic threshold + NVML_TEMPERATURE_THRESHOLD_ACOUSTIC_CURR = 5, // Current temperature that is set as + // acoustic threshold. + NVML_TEMPERATURE_THRESHOLD_ACOUSTIC_MAX = 6, // Maximum GPU temperature that can be + // set as acoustic threshold. + // Keep this last + NVML_TEMPERATURE_THRESHOLD_COUNT +} nvmlTemperatureThresholds_t; + +/** + * Temperature sensors. + */ +typedef enum nvmlTemperatureSensors_enum +{ + NVML_TEMPERATURE_GPU = 0, //!< Temperature sensor for the GPU die + + // Keep this last + NVML_TEMPERATURE_COUNT +} nvmlTemperatureSensors_t; + +/** + * Compute mode. + * + * NVML_COMPUTEMODE_EXCLUSIVE_PROCESS was added in CUDA 4.0. + * Earlier CUDA versions supported a single exclusive mode, + * which is equivalent to NVML_COMPUTEMODE_EXCLUSIVE_THREAD in CUDA 4.0 and beyond. + */ +typedef enum nvmlComputeMode_enum +{ + NVML_COMPUTEMODE_DEFAULT = 0, //!< Default compute mode -- multiple contexts per device + NVML_COMPUTEMODE_EXCLUSIVE_THREAD = 1, //!< Support Removed + NVML_COMPUTEMODE_PROHIBITED = 2, //!< Compute-prohibited mode -- no contexts per device + NVML_COMPUTEMODE_EXCLUSIVE_PROCESS = 3, //!< Compute-exclusive-process mode -- only one context per device, usable from multiple threads at a time + + // Keep this last + NVML_COMPUTEMODE_COUNT +} nvmlComputeMode_t; + +/** + * Max Clock Monitors available + */ +#define MAX_CLK_DOMAINS 32 + +/** + * Clock Monitor error types + */ +typedef struct nvmlClkMonFaultInfo_struct { + /** + * The Domain which faulted + */ + unsigned int clkApiDomain; + + /** + * Faults Information + */ + unsigned int clkDomainFaultMask; +} nvmlClkMonFaultInfo_t; + +/** + * Clock Monitor Status + */ +typedef struct nvmlClkMonStatus_status { + /** + * Fault status Indicator + */ + unsigned int bGlobalStatus; + + /** + * Total faulted domain numbers + */ + unsigned int clkMonListSize; + + /** + * The fault Information structure + */ + nvmlClkMonFaultInfo_t clkMonList[MAX_CLK_DOMAINS]; +} nvmlClkMonStatus_t; + +/** + * ECC bit types. + * + * @deprecated See \ref nvmlMemoryErrorType_t for a more flexible type + */ +#define nvmlEccBitType_t nvmlMemoryErrorType_t + +/** + * Single bit ECC errors + * + * @deprecated Mapped to \ref NVML_MEMORY_ERROR_TYPE_CORRECTED + */ +#define NVML_SINGLE_BIT_ECC NVML_MEMORY_ERROR_TYPE_CORRECTED + +/** + * Double bit ECC errors + * + * @deprecated Mapped to \ref NVML_MEMORY_ERROR_TYPE_UNCORRECTED + */ +#define NVML_DOUBLE_BIT_ECC NVML_MEMORY_ERROR_TYPE_UNCORRECTED + +/** + * Memory error types + */ +typedef enum nvmlMemoryErrorType_enum +{ + /** + * A memory error that was corrected + * + * For ECC errors, these are single bit errors + * For Texture memory, these are errors fixed by resend + */ + NVML_MEMORY_ERROR_TYPE_CORRECTED = 0, + /** + * A memory error that was not corrected + * + * For ECC errors, these are double bit errors + * For Texture memory, these are errors where the resend fails + */ + NVML_MEMORY_ERROR_TYPE_UNCORRECTED = 1, + + + // Keep this last + NVML_MEMORY_ERROR_TYPE_COUNT //!< Count of memory error types + +} nvmlMemoryErrorType_t; + +/** + * ECC counter types. + * + * Note: Volatile counts are reset each time the driver loads. On Windows this is once per boot. On Linux this can be more frequent. + * On Linux the driver unloads when no active clients exist. If persistence mode is enabled or there is always a driver + * client active (e.g. X11), then Linux also sees per-boot behavior. If not, volatile counts are reset each time a compute app + * is run. + */ +typedef enum nvmlEccCounterType_enum +{ + NVML_VOLATILE_ECC = 0, //!< Volatile counts are reset each time the driver loads. + NVML_AGGREGATE_ECC = 1, //!< Aggregate counts persist across reboots (i.e. for the lifetime of the device) + + // Keep this last + NVML_ECC_COUNTER_TYPE_COUNT //!< Count of memory counter types +} nvmlEccCounterType_t; + +/** + * Clock types. + * + * All speeds are in Mhz. + */ +typedef enum nvmlClockType_enum +{ + NVML_CLOCK_GRAPHICS = 0, //!< Graphics clock domain + NVML_CLOCK_SM = 1, //!< SM clock domain + NVML_CLOCK_MEM = 2, //!< Memory clock domain + NVML_CLOCK_VIDEO = 3, //!< Video encoder/decoder clock domain + + // Keep this last + NVML_CLOCK_COUNT //!< Count of clock types +} nvmlClockType_t; + +/** + * Clock Ids. These are used in combination with nvmlClockType_t + * to specify a single clock value. + */ +typedef enum nvmlClockId_enum +{ + NVML_CLOCK_ID_CURRENT = 0, //!< Current actual clock value + NVML_CLOCK_ID_APP_CLOCK_TARGET = 1, //!< Target application clock + NVML_CLOCK_ID_APP_CLOCK_DEFAULT = 2, //!< Default application clock target + NVML_CLOCK_ID_CUSTOMER_BOOST_MAX = 3, //!< OEM-defined maximum clock rate + + //Keep this last + NVML_CLOCK_ID_COUNT //!< Count of Clock Ids. +} nvmlClockId_t; + +/** + * Driver models. + * + * Windows only. + */ + +typedef enum nvmlDriverModel_enum +{ + NVML_DRIVER_WDDM = 0, //!< WDDM driver model -- GPU treated as a display device + NVML_DRIVER_WDM = 1 //!< WDM (TCC) model (recommended) -- GPU treated as a generic device +} nvmlDriverModel_t; + +#define NVML_MAX_GPU_PERF_PSTATES 16 + +/** + * Allowed PStates. + */ +typedef enum nvmlPStates_enum +{ + NVML_PSTATE_0 = 0, //!< Performance state 0 -- Maximum Performance + NVML_PSTATE_1 = 1, //!< Performance state 1 + NVML_PSTATE_2 = 2, //!< Performance state 2 + NVML_PSTATE_3 = 3, //!< Performance state 3 + NVML_PSTATE_4 = 4, //!< Performance state 4 + NVML_PSTATE_5 = 5, //!< Performance state 5 + NVML_PSTATE_6 = 6, //!< Performance state 6 + NVML_PSTATE_7 = 7, //!< Performance state 7 + NVML_PSTATE_8 = 8, //!< Performance state 8 + NVML_PSTATE_9 = 9, //!< Performance state 9 + NVML_PSTATE_10 = 10, //!< Performance state 10 + NVML_PSTATE_11 = 11, //!< Performance state 11 + NVML_PSTATE_12 = 12, //!< Performance state 12 + NVML_PSTATE_13 = 13, //!< Performance state 13 + NVML_PSTATE_14 = 14, //!< Performance state 14 + NVML_PSTATE_15 = 15, //!< Performance state 15 -- Minimum Performance + NVML_PSTATE_UNKNOWN = 32 //!< Unknown performance state +} nvmlPstates_t; + +/** + * GPU Operation Mode + * + * GOM allows to reduce power usage and optimize GPU throughput by disabling GPU features. + * + * Each GOM is designed to meet specific user needs. + */ +typedef enum nvmlGom_enum +{ + NVML_GOM_ALL_ON = 0, //!< Everything is enabled and running at full speed + + NVML_GOM_COMPUTE = 1, //!< Designed for running only compute tasks. Graphics operations + //!< are not allowed + + NVML_GOM_LOW_DP = 2 //!< Designed for running graphics applications that don't require + //!< high bandwidth double precision +} nvmlGpuOperationMode_t; + +/** + * Available infoROM objects. + */ +typedef enum nvmlInforomObject_enum +{ + NVML_INFOROM_OEM = 0, //!< An object defined by OEM + NVML_INFOROM_ECC = 1, //!< The ECC object determining the level of ECC support + NVML_INFOROM_POWER = 2, //!< The power management object + + // Keep this last + NVML_INFOROM_COUNT //!< This counts the number of infoROM objects the driver knows about +} nvmlInforomObject_t; + +/** + * Return values for NVML API calls. + */ +typedef enum nvmlReturn_enum +{ + // cppcheck-suppress * + NVML_SUCCESS = 0, //!< The operation was successful + NVML_ERROR_UNINITIALIZED = 1, //!< NVML was not first initialized with nvmlInit() + NVML_ERROR_INVALID_ARGUMENT = 2, //!< A supplied argument is invalid + NVML_ERROR_NOT_SUPPORTED = 3, //!< The requested operation is not available on target device + NVML_ERROR_NO_PERMISSION = 4, //!< The current user does not have permission for operation + NVML_ERROR_ALREADY_INITIALIZED = 5, //!< Deprecated: Multiple initializations are now allowed through ref counting + NVML_ERROR_NOT_FOUND = 6, //!< A query to find an object was unsuccessful + NVML_ERROR_INSUFFICIENT_SIZE = 7, //!< An input argument is not large enough + NVML_ERROR_INSUFFICIENT_POWER = 8, //!< A device's external power cables are not properly attached + NVML_ERROR_DRIVER_NOT_LOADED = 9, //!< NVIDIA driver is not loaded + NVML_ERROR_TIMEOUT = 10, //!< User provided timeout passed + NVML_ERROR_IRQ_ISSUE = 11, //!< NVIDIA Kernel detected an interrupt issue with a GPU + NVML_ERROR_LIBRARY_NOT_FOUND = 12, //!< NVML Shared Library couldn't be found or loaded + NVML_ERROR_FUNCTION_NOT_FOUND = 13, //!< Local version of NVML doesn't implement this function + NVML_ERROR_CORRUPTED_INFOROM = 14, //!< infoROM is corrupted + NVML_ERROR_GPU_IS_LOST = 15, //!< The GPU has fallen off the bus or has otherwise become inaccessible + NVML_ERROR_RESET_REQUIRED = 16, //!< The GPU requires a reset before it can be used again + NVML_ERROR_OPERATING_SYSTEM = 17, //!< The GPU control device has been blocked by the operating system/cgroups + NVML_ERROR_LIB_RM_VERSION_MISMATCH = 18, //!< RM detects a driver/library version mismatch + NVML_ERROR_IN_USE = 19, //!< An operation cannot be performed because the GPU is currently in use + NVML_ERROR_MEMORY = 20, //!< Insufficient memory + NVML_ERROR_NO_DATA = 21, //!< No data + NVML_ERROR_VGPU_ECC_NOT_SUPPORTED = 22, //!< The requested vgpu operation is not available on target device, becasue ECC is enabled + NVML_ERROR_INSUFFICIENT_RESOURCES = 23, //!< Ran out of critical resources, other than memory + NVML_ERROR_FREQ_NOT_SUPPORTED = 24, //!< Ran out of critical resources, other than memory + NVML_ERROR_ARGUMENT_VERSION_MISMATCH = 25, //!< The provided version is invalid/unsupported + NVML_ERROR_DEPRECATED = 26, //!< The requested functionality has been deprecated + NVML_ERROR_UNKNOWN = 999 //!< An internal driver error occurred +} nvmlReturn_t; + +/** + * See \ref nvmlDeviceGetMemoryErrorCounter + */ +typedef enum nvmlMemoryLocation_enum +{ + NVML_MEMORY_LOCATION_L1_CACHE = 0, //!< GPU L1 Cache + NVML_MEMORY_LOCATION_L2_CACHE = 1, //!< GPU L2 Cache + NVML_MEMORY_LOCATION_DRAM = 2, //!< Turing+ DRAM + NVML_MEMORY_LOCATION_DEVICE_MEMORY = 2, //!< GPU Device Memory + NVML_MEMORY_LOCATION_REGISTER_FILE = 3, //!< GPU Register File + NVML_MEMORY_LOCATION_TEXTURE_MEMORY = 4, //!< GPU Texture Memory + NVML_MEMORY_LOCATION_TEXTURE_SHM = 5, //!< Shared memory + NVML_MEMORY_LOCATION_CBU = 6, //!< CBU + NVML_MEMORY_LOCATION_SRAM = 7, //!< Turing+ SRAM + // Keep this last + NVML_MEMORY_LOCATION_COUNT //!< This counts the number of memory locations the driver knows about +} nvmlMemoryLocation_t; + +/** + * Causes for page retirement + */ +typedef enum nvmlPageRetirementCause_enum +{ + NVML_PAGE_RETIREMENT_CAUSE_MULTIPLE_SINGLE_BIT_ECC_ERRORS = 0, //!< Page was retired due to multiple single bit ECC error + NVML_PAGE_RETIREMENT_CAUSE_DOUBLE_BIT_ECC_ERROR = 1, //!< Page was retired due to double bit ECC error + + // Keep this last + NVML_PAGE_RETIREMENT_CAUSE_COUNT +} nvmlPageRetirementCause_t; + +/** + * API types that allow changes to default permission restrictions + */ +typedef enum nvmlRestrictedAPI_enum +{ + NVML_RESTRICTED_API_SET_APPLICATION_CLOCKS = 0, //!< APIs that change application clocks, see nvmlDeviceSetApplicationsClocks + //!< and see nvmlDeviceResetApplicationsClocks + NVML_RESTRICTED_API_SET_AUTO_BOOSTED_CLOCKS = 1, //!< APIs that enable/disable Auto Boosted clocks + //!< see nvmlDeviceSetAutoBoostedClocksEnabled + // Keep this last + NVML_RESTRICTED_API_COUNT +} nvmlRestrictedAPI_t; + +/** @} */ + +/***************************************************************************************************/ +/** @addtogroup virtualGPU + * @{ + */ +/***************************************************************************************************/ +/** @defgroup nvmlVirtualGpuEnums vGPU Enums + * @{ + */ +/***************************************************************************************************/ + +/*! + * GPU virtualization mode types. + */ +typedef enum nvmlGpuVirtualizationMode { + NVML_GPU_VIRTUALIZATION_MODE_NONE = 0, //!< Represents Bare Metal GPU + NVML_GPU_VIRTUALIZATION_MODE_PASSTHROUGH = 1, //!< Device is associated with GPU-Passthorugh + NVML_GPU_VIRTUALIZATION_MODE_VGPU = 2, //!< Device is associated with vGPU inside virtual machine. + NVML_GPU_VIRTUALIZATION_MODE_HOST_VGPU = 3, //!< Device is associated with VGX hypervisor in vGPU mode + NVML_GPU_VIRTUALIZATION_MODE_HOST_VSGA = 4 //!< Device is associated with VGX hypervisor in vSGA mode +} nvmlGpuVirtualizationMode_t; + +/** + * Host vGPU modes + */ +typedef enum nvmlHostVgpuMode_enum +{ + NVML_HOST_VGPU_MODE_NON_SRIOV = 0, //!< Non SR-IOV mode + NVML_HOST_VGPU_MODE_SRIOV = 1 //!< SR-IOV mode +} nvmlHostVgpuMode_t; + +/*! + * Types of VM identifiers + */ +typedef enum nvmlVgpuVmIdType { + NVML_VGPU_VM_ID_DOMAIN_ID = 0, //!< VM ID represents DOMAIN ID + NVML_VGPU_VM_ID_UUID = 1 //!< VM ID represents UUID +} nvmlVgpuVmIdType_t; + +/** + * vGPU GUEST info state + */ +typedef enum nvmlVgpuGuestInfoState_enum +{ + NVML_VGPU_INSTANCE_GUEST_INFO_STATE_UNINITIALIZED = 0, //!< Guest-dependent fields uninitialized + NVML_VGPU_INSTANCE_GUEST_INFO_STATE_INITIALIZED = 1 //!< Guest-dependent fields initialized +} nvmlVgpuGuestInfoState_t; + +/** + * vGPU software licensable features + */ +typedef enum { + NVML_GRID_LICENSE_FEATURE_CODE_UNKNOWN = 0, //!< Unknown + NVML_GRID_LICENSE_FEATURE_CODE_VGPU = 1, //!< Virtual GPU + NVML_GRID_LICENSE_FEATURE_CODE_NVIDIA_RTX = 2, //!< Nvidia RTX + NVML_GRID_LICENSE_FEATURE_CODE_VWORKSTATION = NVML_GRID_LICENSE_FEATURE_CODE_NVIDIA_RTX, //!< Deprecated, do not use. + NVML_GRID_LICENSE_FEATURE_CODE_GAMING = 3, //!< Gaming + NVML_GRID_LICENSE_FEATURE_CODE_COMPUTE = 4 //!< Compute +} nvmlGridLicenseFeatureCode_t; + +/** + * Status codes for license expiry + */ +#define NVML_GRID_LICENSE_EXPIRY_NOT_AVAILABLE 0 //!< Expiry information not available +#define NVML_GRID_LICENSE_EXPIRY_INVALID 1 //!< Invalid expiry or error fetching expiry +#define NVML_GRID_LICENSE_EXPIRY_VALID 2 //!< Valid expiry +#define NVML_GRID_LICENSE_EXPIRY_NOT_APPLICABLE 3 //!< Expiry not applicable +#define NVML_GRID_LICENSE_EXPIRY_PERMANENT 4 //!< Permanent expiry + +/** + * vGPU queryable capabilities + */ +typedef enum nvmlVgpuCapability_enum +{ + NVML_VGPU_CAP_NVLINK_P2P = 0, //!< P2P over NVLink is supported + NVML_VGPU_CAP_GPUDIRECT = 1, //!< GPUDirect capability is supported + NVML_VGPU_CAP_MULTI_VGPU_EXCLUSIVE = 2, //!< vGPU profile cannot be mixed with other vGPU profiles in same VM + NVML_VGPU_CAP_EXCLUSIVE_TYPE = 3, //!< vGPU profile cannot run on a GPU alongside other profiles of different type + NVML_VGPU_CAP_EXCLUSIVE_SIZE = 4, //!< vGPU profile cannot run on a GPU alongside other profiles of different size + // Keep this last + NVML_VGPU_CAP_COUNT +} nvmlVgpuCapability_t; + + +/** +* vGPU driver queryable capabilities +*/ +typedef enum nvmlVgpuDriverCapability_enum +{ + NVML_VGPU_DRIVER_CAP_HETEROGENEOUS_MULTI_VGPU = 0, //!< Supports mixing of different vGPU profiles within one guest VM + // Keep this last + NVML_VGPU_DRIVER_CAP_COUNT +} nvmlVgpuDriverCapability_t; + + +/** +* Device vGPU queryable capabilities +*/ +typedef enum nvmlDeviceVgpuCapability_enum +{ + NVML_DEVICE_VGPU_CAP_FRACTIONAL_MULTI_VGPU = 0, //!< Fractional vGPU profiles on this GPU can be used in multi-vGPU configurations + NVML_DEVICE_VGPU_CAP_HETEROGENEOUS_TIMESLICE_PROFILES = 1, //!< Supports concurrent execution of timesliced vGPU profiles of differing types + NVML_DEVICE_VGPU_CAP_HETEROGENEOUS_TIMESLICE_SIZES = 2, //!< Supports concurrent execution of timesliced vGPU profiles of differing framebuffer sizes + // Keep this last + NVML_DEVICE_VGPU_CAP_COUNT +} nvmlDeviceVgpuCapability_t; + +/** @} */ + +/***************************************************************************************************/ + +/** @defgroup nvmlVgpuConstants vGPU Constants + * @{ + */ +/***************************************************************************************************/ + +/** + * Buffer size guaranteed to be large enough for \ref nvmlVgpuTypeGetLicense + */ +#define NVML_GRID_LICENSE_BUFFER_SIZE 128 + +#define NVML_VGPU_NAME_BUFFER_SIZE 64 + +#define NVML_GRID_LICENSE_FEATURE_MAX_COUNT 3 + +#define INVALID_GPU_INSTANCE_PROFILE_ID 0xFFFFFFFF + +#define INVALID_GPU_INSTANCE_ID 0xFFFFFFFF + +/*! + * Macros for vGPU instance's virtualization capabilities bitfield. + */ +#define NVML_VGPU_VIRTUALIZATION_CAP_MIGRATION 0:0 +#define NVML_VGPU_VIRTUALIZATION_CAP_MIGRATION_NO 0x0 +#define NVML_VGPU_VIRTUALIZATION_CAP_MIGRATION_YES 0x1 + +/*! + * Macros for pGPU's virtualization capabilities bitfield. + */ +#define NVML_VGPU_PGPU_VIRTUALIZATION_CAP_MIGRATION 0:0 +#define NVML_VGPU_PGPU_VIRTUALIZATION_CAP_MIGRATION_NO 0x0 +#define NVML_VGPU_PGPU_VIRTUALIZATION_CAP_MIGRATION_YES 0x1 + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlVgpuStructs vGPU Structs + * @{ + */ +/***************************************************************************************************/ + +typedef unsigned int nvmlVgpuTypeId_t; + +typedef unsigned int nvmlVgpuInstance_t; + +/** + * Structure to store Utilization Value and vgpuInstance + */ +typedef struct nvmlVgpuInstanceUtilizationSample_st +{ + nvmlVgpuInstance_t vgpuInstance; //!< vGPU Instance + unsigned long long timeStamp; //!< CPU Timestamp in microseconds + nvmlValue_t smUtil; //!< SM (3D/Compute) Util Value + nvmlValue_t memUtil; //!< Frame Buffer Memory Util Value + nvmlValue_t encUtil; //!< Encoder Util Value + nvmlValue_t decUtil; //!< Decoder Util Value +} nvmlVgpuInstanceUtilizationSample_t; + +/** + * Structure to store Utilization Value, vgpuInstance and subprocess information + */ +typedef struct nvmlVgpuProcessUtilizationSample_st +{ + nvmlVgpuInstance_t vgpuInstance; //!< vGPU Instance + unsigned int pid; //!< PID of process running within the vGPU VM + char processName[NVML_VGPU_NAME_BUFFER_SIZE]; //!< Name of process running within the vGPU VM + unsigned long long timeStamp; //!< CPU Timestamp in microseconds + unsigned int smUtil; //!< SM (3D/Compute) Util Value + unsigned int memUtil; //!< Frame Buffer Memory Util Value + unsigned int encUtil; //!< Encoder Util Value + unsigned int decUtil; //!< Decoder Util Value +} nvmlVgpuProcessUtilizationSample_t; + +/** + * vGPU scheduler policies + */ +#define NVML_VGPU_SCHEDULER_POLICY_UNKNOWN 0 +#define NVML_VGPU_SCHEDULER_POLICY_BEST_EFFORT 1 +#define NVML_VGPU_SCHEDULER_POLICY_EQUAL_SHARE 2 +#define NVML_VGPU_SCHEDULER_POLICY_FIXED_SHARE 3 + +#define NVML_SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT 3 + +#define NVML_SCHEDULER_SW_MAX_LOG_ENTRIES 200 + +/** + * Union to represent the vGPU Scheduler Parameters + */ +typedef union +{ + struct + { + unsigned int avgFactor; //!< Average factor in compensating the timeslice for Adaptive Round Robin mode + unsigned int timeslice; //!< The timeslice in ns for each software run list as configured, or the default value otherwise + } vgpuSchedDataWithARR; + + struct + { + unsigned int timeslice; //!< The timeslice in ns for each software run list as configured, or the default value otherwise + } vgpuSchedData; + +} nvmlVgpuSchedulerParams_t; + +/** + * Structure to store the state and logs of a software runlist + */ +typedef struct nvmlVgpuSchedulerLogEntries_st +{ + unsigned long long timestamp; //!< Timestamp in ns when this software runlist was preeempted + unsigned long long timeRunTotal; //!< Total time in ns this software runlist has run + unsigned long long timeRun; //!< Time in ns this software runlist ran before preemption + unsigned int swRunlistId; //!< Software runlist Id + unsigned long long targetTimeSlice; //!< The actual timeslice after deduction + unsigned long long cumulativePreemptionTime; //!< Preemption time in ns for this SW runlist +} nvmlVgpuSchedulerLogEntry_t; + +/** + * Structure to store a vGPU software scheduler log + */ +typedef struct nvmlVgpuSchedulerLog_st +{ + unsigned int engineId; //!< Engine whose software runlist log entries are fetched + unsigned int schedulerPolicy; //!< Scheduler policy + unsigned int isEnabledARR; //!< Flag to check Adaptive Round Robin scheduler mode + nvmlVgpuSchedulerParams_t schedulerParams; + unsigned int entriesCount; //!< Count of log entries fetched + nvmlVgpuSchedulerLogEntry_t logEntries[NVML_SCHEDULER_SW_MAX_LOG_ENTRIES]; +} nvmlVgpuSchedulerLog_t; + +/** + * Structure to store the vGPU scheduler state + */ +typedef struct nvmlVgpuSchedulerGetState_st +{ + unsigned int schedulerPolicy; //!< Scheduler policy + unsigned int isEnabledARR; //!< Flag to check Adaptive Round Robin scheduler mode + nvmlVgpuSchedulerParams_t schedulerParams; +} nvmlVgpuSchedulerGetState_t; + +/** + * Union to represent the vGPU Scheduler set Parameters + */ +typedef union +{ + struct + { + unsigned int avgFactor; //!< Average factor in compensating the timeslice for Adaptive Round Robin mode + unsigned int frequency; //!< Frequency for Adaptive Round Robin mode + } vgpuSchedDataWithARR; + + struct + { + unsigned int timeslice; //!< The timeslice in ms(milliseconds) for each software run list as configured, or the default value otherwise + } vgpuSchedData; + +} nvmlVgpuSchedulerSetParams_t; + +/** + * Structure to set the vGPU scheduler state + */ +typedef struct nvmlVgpuSchedulerSetState_st +{ + unsigned int schedulerPolicy; //!< Scheduler policy + unsigned int enableARRMode; //!< Flag to enable/disable Adaptive Round Robin scheduler + nvmlVgpuSchedulerSetParams_t schedulerParams; +} nvmlVgpuSchedulerSetState_t; + +/** + * Structure to store the vGPU scheduler capabilities + */ +typedef struct nvmlVgpuSchedulerCapabilities_st +{ + unsigned int supportedSchedulers[NVML_SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT]; //!< List the supported vGPU schedulers on the device + unsigned int maxTimeslice; //!< Maximum timeslice value in ns + unsigned int minTimeslice; //!< Minimum timeslice value in ns + unsigned int isArrModeSupported; //!< Flag to check Adaptive Round Robin mode enabled/disabled. + unsigned int maxFrequencyForARR; //!< Maximum frequency for Adaptive Round Robin mode + unsigned int minFrequencyForARR; //!< Minimum frequency for Adaptive Round Robin mode + unsigned int maxAvgFactorForARR; //!< Maximum averaging factor for Adaptive Round Robin mode + unsigned int minAvgFactorForARR; //!< Minimum averaging factor for Adaptive Round Robin mode +} nvmlVgpuSchedulerCapabilities_t; + +/** + * Structure to store the vGPU license expiry details + */ +typedef struct nvmlVgpuLicenseExpiry_st +{ + unsigned int year; //!< Year of license expiry + unsigned short month; //!< Month of license expiry + unsigned short day; //!< Day of license expiry + unsigned short hour; //!< Hour of license expiry + unsigned short min; //!< Minutes of license expiry + unsigned short sec; //!< Seconds of license expiry + unsigned char status; //!< License expiry status +} nvmlVgpuLicenseExpiry_t; + +/** + * vGPU license state + */ +#define NVML_GRID_LICENSE_STATE_UNKNOWN 0 //!< Unknown state +#define NVML_GRID_LICENSE_STATE_UNINITIALIZED 1 //!< Uninitialized state +#define NVML_GRID_LICENSE_STATE_UNLICENSED_UNRESTRICTED 2 //!< Unlicensed unrestricted state +#define NVML_GRID_LICENSE_STATE_UNLICENSED_RESTRICTED 3 //!< Unlicensed restricted state +#define NVML_GRID_LICENSE_STATE_UNLICENSED 4 //!< Unlicensed state +#define NVML_GRID_LICENSE_STATE_LICENSED 5 //!< Licensed state + +typedef struct nvmlVgpuLicenseInfo_st +{ + unsigned char isLicensed; //!< License status + nvmlVgpuLicenseExpiry_t licenseExpiry; //!< License expiry information + unsigned int currentState; //!< Current license state +} nvmlVgpuLicenseInfo_t; + +/** + * Structure to store utilization value and process Id + */ +typedef struct nvmlProcessUtilizationSample_st +{ + unsigned int pid; //!< PID of process + unsigned long long timeStamp; //!< CPU Timestamp in microseconds + unsigned int smUtil; //!< SM (3D/Compute) Util Value + unsigned int memUtil; //!< Frame Buffer Memory Util Value + unsigned int encUtil; //!< Encoder Util Value + unsigned int decUtil; //!< Decoder Util Value +} nvmlProcessUtilizationSample_t; + +/** + * Structure to store license expiry date and time values + */ +typedef struct nvmlGridLicenseExpiry_st +{ + unsigned int year; //!< Year value of license expiry + unsigned short month; //!< Month value of license expiry + unsigned short day; //!< Day value of license expiry + unsigned short hour; //!< Hour value of license expiry + unsigned short min; //!< Minutes value of license expiry + unsigned short sec; //!< Seconds value of license expiry + unsigned char status; //!< License expiry status +} nvmlGridLicenseExpiry_t; + +/** + * Structure containing vGPU software licensable feature information + */ +typedef struct nvmlGridLicensableFeature_st +{ + nvmlGridLicenseFeatureCode_t featureCode; //!< Licensed feature code + unsigned int featureState; //!< Non-zero if feature is currently licensed, otherwise zero + char licenseInfo[NVML_GRID_LICENSE_BUFFER_SIZE]; //!< Deprecated. + char productName[NVML_GRID_LICENSE_BUFFER_SIZE]; //!< Product name of feature + unsigned int featureEnabled; //!< Non-zero if feature is enabled, otherwise zero + nvmlGridLicenseExpiry_t licenseExpiry; //!< License expiry structure containing date and time +} nvmlGridLicensableFeature_t; + +/** + * Structure to store vGPU software licensable features + */ +typedef struct nvmlGridLicensableFeatures_st +{ + int isGridLicenseSupported; //!< Non-zero if vGPU Software Licensing is supported on the system, otherwise zero + unsigned int licensableFeaturesCount; //!< Entries returned in \a gridLicensableFeatures array + nvmlGridLicensableFeature_t gridLicensableFeatures[NVML_GRID_LICENSE_FEATURE_MAX_COUNT]; //!< Array of vGPU software licensable features. +} nvmlGridLicensableFeatures_t; + +/** + * GSP firmware + */ +#define NVML_GSP_FIRMWARE_VERSION_BUF_SIZE 0x40 + +/** + * Simplified chip architecture + */ +#define NVML_DEVICE_ARCH_KEPLER 2 // Devices based on the NVIDIA Kepler architecture +#define NVML_DEVICE_ARCH_MAXWELL 3 // Devices based on the NVIDIA Maxwell architecture +#define NVML_DEVICE_ARCH_PASCAL 4 // Devices based on the NVIDIA Pascal architecture +#define NVML_DEVICE_ARCH_VOLTA 5 // Devices based on the NVIDIA Volta architecture +#define NVML_DEVICE_ARCH_TURING 6 // Devices based on the NVIDIA Turing architecture + +#define NVML_DEVICE_ARCH_AMPERE 7 // Devices based on the NVIDIA Ampere architecture + +#define NVML_DEVICE_ARCH_ADA 8 // Devices based on the NVIDIA Ada architecture + +#define NVML_DEVICE_ARCH_HOPPER 9 // Devices based on the NVIDIA Hopper architecture + +#define NVML_DEVICE_ARCH_UNKNOWN 0xffffffff // Anything else, presumably something newer + +typedef unsigned int nvmlDeviceArchitecture_t; + +/** + * PCI bus types + */ +#define NVML_BUS_TYPE_UNKNOWN 0 +#define NVML_BUS_TYPE_PCI 1 +#define NVML_BUS_TYPE_PCIE 2 +#define NVML_BUS_TYPE_FPCI 3 +#define NVML_BUS_TYPE_AGP 4 + +typedef unsigned int nvmlBusType_t; + +/** + * Device Power Modes + */ + +/** + * Device Fan control policy + */ +#define NVML_FAN_POLICY_TEMPERATURE_CONTINOUS_SW 0 +#define NVML_FAN_POLICY_MANUAL 1 + +typedef unsigned int nvmlFanControlPolicy_t; + +/** + * Device Power Source + */ +#define NVML_POWER_SOURCE_AC 0x00000000 +#define NVML_POWER_SOURCE_BATTERY 0x00000001 + +typedef unsigned int nvmlPowerSource_t; + +/* + * Device PCIE link Max Speed + */ +#define NVML_PCIE_LINK_MAX_SPEED_INVALID 0x00000000 +#define NVML_PCIE_LINK_MAX_SPEED_2500MBPS 0x00000001 +#define NVML_PCIE_LINK_MAX_SPEED_5000MBPS 0x00000002 +#define NVML_PCIE_LINK_MAX_SPEED_8000MBPS 0x00000003 +#define NVML_PCIE_LINK_MAX_SPEED_16000MBPS 0x00000004 +#define NVML_PCIE_LINK_MAX_SPEED_32000MBPS 0x00000005 +#define NVML_PCIE_LINK_MAX_SPEED_64000MBPS 0x00000006 + +/* + * Adaptive clocking status + */ +#define NVML_ADAPTIVE_CLOCKING_INFO_STATUS_DISABLED 0x00000000 +#define NVML_ADAPTIVE_CLOCKING_INFO_STATUS_ENABLED 0x00000001 + +#define NVML_MAX_GPU_UTILIZATIONS 8 +typedef enum nvmlGpuUtilizationDomainId_t +{ + NVML_GPU_UTILIZATION_DOMAIN_GPU = 0, //!< Graphics engine domain + NVML_GPU_UTILIZATION_DOMAIN_FB = 1, //!< Frame buffer domain + NVML_GPU_UTILIZATION_DOMAIN_VID = 2, //!< Video engine domain + NVML_GPU_UTILIZATION_DOMAIN_BUS = 3, //!< Bus interface domain +} nvmlGpuUtilizationDomainId_t; + +typedef struct nvmlGpuDynamicPstatesInfo_st +{ + unsigned int flags; //!< Reserved for future use + struct + { + unsigned int bIsPresent; //!< Set if this utilization domain is present on this GPU + unsigned int percentage; //!< Percentage of time where the domain is considered busy in the last 1-second interval + unsigned int incThreshold; //!< Utilization threshold that can trigger a perf-increasing P-State change when crossed + unsigned int decThreshold; //!< Utilization threshold that can trigger a perf-decreasing P-State change when crossed + } utilization[NVML_MAX_GPU_UTILIZATIONS]; +} nvmlGpuDynamicPstatesInfo_t; + +/** @} */ +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlFieldValueEnums Field Value Enums + * @{ + */ +/***************************************************************************************************/ + +/** + * Field Identifiers. + * + * All Identifiers pertain to a device. Each ID is only used once and is guaranteed never to change. + */ +#define NVML_FI_DEV_ECC_CURRENT 1 //!< Current ECC mode. 1=Active. 0=Inactive +#define NVML_FI_DEV_ECC_PENDING 2 //!< Pending ECC mode. 1=Active. 0=Inactive +/* ECC Count Totals */ +#define NVML_FI_DEV_ECC_SBE_VOL_TOTAL 3 //!< Total single bit volatile ECC errors +#define NVML_FI_DEV_ECC_DBE_VOL_TOTAL 4 //!< Total double bit volatile ECC errors +#define NVML_FI_DEV_ECC_SBE_AGG_TOTAL 5 //!< Total single bit aggregate (persistent) ECC errors +#define NVML_FI_DEV_ECC_DBE_AGG_TOTAL 6 //!< Total double bit aggregate (persistent) ECC errors +/* Individual ECC locations */ +#define NVML_FI_DEV_ECC_SBE_VOL_L1 7 //!< L1 cache single bit volatile ECC errors +#define NVML_FI_DEV_ECC_DBE_VOL_L1 8 //!< L1 cache double bit volatile ECC errors +#define NVML_FI_DEV_ECC_SBE_VOL_L2 9 //!< L2 cache single bit volatile ECC errors +#define NVML_FI_DEV_ECC_DBE_VOL_L2 10 //!< L2 cache double bit volatile ECC errors +#define NVML_FI_DEV_ECC_SBE_VOL_DEV 11 //!< Device memory single bit volatile ECC errors +#define NVML_FI_DEV_ECC_DBE_VOL_DEV 12 //!< Device memory double bit volatile ECC errors +#define NVML_FI_DEV_ECC_SBE_VOL_REG 13 //!< Register file single bit volatile ECC errors +#define NVML_FI_DEV_ECC_DBE_VOL_REG 14 //!< Register file double bit volatile ECC errors +#define NVML_FI_DEV_ECC_SBE_VOL_TEX 15 //!< Texture memory single bit volatile ECC errors +#define NVML_FI_DEV_ECC_DBE_VOL_TEX 16 //!< Texture memory double bit volatile ECC errors +#define NVML_FI_DEV_ECC_DBE_VOL_CBU 17 //!< CBU double bit volatile ECC errors +#define NVML_FI_DEV_ECC_SBE_AGG_L1 18 //!< L1 cache single bit aggregate (persistent) ECC errors +#define NVML_FI_DEV_ECC_DBE_AGG_L1 19 //!< L1 cache double bit aggregate (persistent) ECC errors +#define NVML_FI_DEV_ECC_SBE_AGG_L2 20 //!< L2 cache single bit aggregate (persistent) ECC errors +#define NVML_FI_DEV_ECC_DBE_AGG_L2 21 //!< L2 cache double bit aggregate (persistent) ECC errors +#define NVML_FI_DEV_ECC_SBE_AGG_DEV 22 //!< Device memory single bit aggregate (persistent) ECC errors +#define NVML_FI_DEV_ECC_DBE_AGG_DEV 23 //!< Device memory double bit aggregate (persistent) ECC errors +#define NVML_FI_DEV_ECC_SBE_AGG_REG 24 //!< Register File single bit aggregate (persistent) ECC errors +#define NVML_FI_DEV_ECC_DBE_AGG_REG 25 //!< Register File double bit aggregate (persistent) ECC errors +#define NVML_FI_DEV_ECC_SBE_AGG_TEX 26 //!< Texture memory single bit aggregate (persistent) ECC errors +#define NVML_FI_DEV_ECC_DBE_AGG_TEX 27 //!< Texture memory double bit aggregate (persistent) ECC errors +#define NVML_FI_DEV_ECC_DBE_AGG_CBU 28 //!< CBU double bit aggregate ECC errors + +/* Page Retirement */ +#define NVML_FI_DEV_RETIRED_SBE 29 //!< Number of retired pages because of single bit errors +#define NVML_FI_DEV_RETIRED_DBE 30 //!< Number of retired pages because of double bit errors +#define NVML_FI_DEV_RETIRED_PENDING 31 //!< If any pages are pending retirement. 1=yes. 0=no. + +/* NvLink Flit Error Counters */ +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L0 32 //!< NVLink flow control CRC Error Counter for Lane 0 +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L1 33 //!< NVLink flow control CRC Error Counter for Lane 1 +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L2 34 //!< NVLink flow control CRC Error Counter for Lane 2 +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L3 35 //!< NVLink flow control CRC Error Counter for Lane 3 +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L4 36 //!< NVLink flow control CRC Error Counter for Lane 4 +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L5 37 //!< NVLink flow control CRC Error Counter for Lane 5 +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_TOTAL 38 //!< NVLink flow control CRC Error Counter total for all Lanes + +/* NvLink CRC Data Error Counters */ +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L0 39 //!< NVLink data CRC Error Counter for Lane 0 +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L1 40 //!< NVLink data CRC Error Counter for Lane 1 +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L2 41 //!< NVLink data CRC Error Counter for Lane 2 +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L3 42 //!< NVLink data CRC Error Counter for Lane 3 +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L4 43 //!< NVLink data CRC Error Counter for Lane 4 +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L5 44 //!< NVLink data CRC Error Counter for Lane 5 +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_TOTAL 45 //!< NvLink data CRC Error Counter total for all Lanes + +/* NvLink Replay Error Counters */ +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L0 46 //!< NVLink Replay Error Counter for Lane 0 +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L1 47 //!< NVLink Replay Error Counter for Lane 1 +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L2 48 //!< NVLink Replay Error Counter for Lane 2 +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L3 49 //!< NVLink Replay Error Counter for Lane 3 +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L4 50 //!< NVLink Replay Error Counter for Lane 4 +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L5 51 //!< NVLink Replay Error Counter for Lane 5 +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_TOTAL 52 //!< NVLink Replay Error Counter total for all Lanes + +/* NvLink Recovery Error Counters */ +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L0 53 //!< NVLink Recovery Error Counter for Lane 0 +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L1 54 //!< NVLink Recovery Error Counter for Lane 1 +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L2 55 //!< NVLink Recovery Error Counter for Lane 2 +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L3 56 //!< NVLink Recovery Error Counter for Lane 3 +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L4 57 //!< NVLink Recovery Error Counter for Lane 4 +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L5 58 //!< NVLink Recovery Error Counter for Lane 5 +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_TOTAL 59 //!< NVLink Recovery Error Counter total for all Lanes + +/* NvLink Bandwidth Counters */ +/* + * NVML_FI_DEV_NVLINK_BANDWIDTH_* field values are now deprecated. + * Please use the following field values instead: + * NVML_FI_DEV_NVLINK_THROUGHPUT_DATA_TX + * NVML_FI_DEV_NVLINK_THROUGHPUT_DATA_RX + * NVML_FI_DEV_NVLINK_THROUGHPUT_RAW_TX + * NVML_FI_DEV_NVLINK_THROUGHPUT_RAW_RX + */ +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L0 60 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 0 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L1 61 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 1 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L2 62 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 2 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L3 63 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 3 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L4 64 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 4 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L5 65 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 5 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_TOTAL 66 //!< NVLink Bandwidth Counter Total for Counter Set 0, All Lanes + +/* NvLink Bandwidth Counters */ +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L0 67 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 0 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L1 68 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 1 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L2 69 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 2 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L3 70 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 3 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L4 71 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 4 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L5 72 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 5 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_TOTAL 73 //!< NVLink Bandwidth Counter Total for Counter Set 1, All Lanes + +/* NVML Perf Policy Counters */ +#define NVML_FI_DEV_PERF_POLICY_POWER 74 //!< Perf Policy Counter for Power Policy +#define NVML_FI_DEV_PERF_POLICY_THERMAL 75 //!< Perf Policy Counter for Thermal Policy +#define NVML_FI_DEV_PERF_POLICY_SYNC_BOOST 76 //!< Perf Policy Counter for Sync boost Policy +#define NVML_FI_DEV_PERF_POLICY_BOARD_LIMIT 77 //!< Perf Policy Counter for Board Limit +#define NVML_FI_DEV_PERF_POLICY_LOW_UTILIZATION 78 //!< Perf Policy Counter for Low GPU Utilization Policy +#define NVML_FI_DEV_PERF_POLICY_RELIABILITY 79 //!< Perf Policy Counter for Reliability Policy +#define NVML_FI_DEV_PERF_POLICY_TOTAL_APP_CLOCKS 80 //!< Perf Policy Counter for Total App Clock Policy +#define NVML_FI_DEV_PERF_POLICY_TOTAL_BASE_CLOCKS 81 //!< Perf Policy Counter for Total Base Clocks Policy + +/* Memory temperatures */ +#define NVML_FI_DEV_MEMORY_TEMP 82 //!< Memory temperature for the device + +/* Energy Counter */ +#define NVML_FI_DEV_TOTAL_ENERGY_CONSUMPTION 83 //!< Total energy consumption for the GPU in mJ since the driver was last reloaded + +/* NVLink Speed */ +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L0 84 //!< NVLink Speed in MBps for Link 0 +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L1 85 //!< NVLink Speed in MBps for Link 1 +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L2 86 //!< NVLink Speed in MBps for Link 2 +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L3 87 //!< NVLink Speed in MBps for Link 3 +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L4 88 //!< NVLink Speed in MBps for Link 4 +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L5 89 //!< NVLink Speed in MBps for Link 5 +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_COMMON 90 //!< Common NVLink Speed in MBps for active links + +#define NVML_FI_DEV_NVLINK_LINK_COUNT 91 //!< Number of NVLinks present on the device + +#define NVML_FI_DEV_RETIRED_PENDING_SBE 92 //!< If any pages are pending retirement due to SBE. 1=yes. 0=no. +#define NVML_FI_DEV_RETIRED_PENDING_DBE 93 //!< If any pages are pending retirement due to DBE. 1=yes. 0=no. + +#define NVML_FI_DEV_PCIE_REPLAY_COUNTER 94 //!< PCIe replay counter +#define NVML_FI_DEV_PCIE_REPLAY_ROLLOVER_COUNTER 95 //!< PCIe replay rollover counter + +/* NvLink Flit Error Counters */ +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L6 96 //!< NVLink flow control CRC Error Counter for Lane 6 +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L7 97 //!< NVLink flow control CRC Error Counter for Lane 7 +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L8 98 //!< NVLink flow control CRC Error Counter for Lane 8 +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L9 99 //!< NVLink flow control CRC Error Counter for Lane 9 +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L10 100 //!< NVLink flow control CRC Error Counter for Lane 10 +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L11 101 //!< NVLink flow control CRC Error Counter for Lane 11 + +/* NvLink CRC Data Error Counters */ +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L6 102 //!< NVLink data CRC Error Counter for Lane 6 +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L7 103 //!< NVLink data CRC Error Counter for Lane 7 +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L8 104 //!< NVLink data CRC Error Counter for Lane 8 +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L9 105 //!< NVLink data CRC Error Counter for Lane 9 +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L10 106 //!< NVLink data CRC Error Counter for Lane 10 +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L11 107 //!< NVLink data CRC Error Counter for Lane 11 + +/* NvLink Replay Error Counters */ +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L6 108 //!< NVLink Replay Error Counter for Lane 6 +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L7 109 //!< NVLink Replay Error Counter for Lane 7 +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L8 110 //!< NVLink Replay Error Counter for Lane 8 +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L9 111 //!< NVLink Replay Error Counter for Lane 9 +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L10 112 //!< NVLink Replay Error Counter for Lane 10 +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L11 113 //!< NVLink Replay Error Counter for Lane 11 + +/* NvLink Recovery Error Counters */ +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L6 114 //!< NVLink Recovery Error Counter for Lane 6 +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L7 115 //!< NVLink Recovery Error Counter for Lane 7 +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L8 116 //!< NVLink Recovery Error Counter for Lane 8 +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L9 117 //!< NVLink Recovery Error Counter for Lane 9 +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L10 118 //!< NVLink Recovery Error Counter for Lane 10 +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L11 119 //!< NVLink Recovery Error Counter for Lane 11 + +/* NvLink Bandwidth Counters */ +/* + * NVML_FI_DEV_NVLINK_BANDWIDTH_* field values are now deprecated. + * Please use the following field values instead: + * NVML_FI_DEV_NVLINK_THROUGHPUT_DATA_TX + * NVML_FI_DEV_NVLINK_THROUGHPUT_DATA_RX + * NVML_FI_DEV_NVLINK_THROUGHPUT_RAW_TX + * NVML_FI_DEV_NVLINK_THROUGHPUT_RAW_RX + */ +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L6 120 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 6 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L7 121 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 7 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L8 122 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 8 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L9 123 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 9 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L10 124 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 10 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L11 125 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 11 + +/* NvLink Bandwidth Counters */ +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L6 126 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 6 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L7 127 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 7 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L8 128 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 8 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L9 129 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 9 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L10 130 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 10 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L11 131 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 11 + +/* NVLink Speed */ +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L6 132 //!< NVLink Speed in MBps for Link 6 +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L7 133 //!< NVLink Speed in MBps for Link 7 +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L8 134 //!< NVLink Speed in MBps for Link 8 +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L9 135 //!< NVLink Speed in MBps for Link 9 +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L10 136 //!< NVLink Speed in MBps for Link 10 +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L11 137 //!< NVLink Speed in MBps for Link 11 + +/** + * NVLink throughput counters field values + * + * Link ID needs to be specified in the scopeId field in nvmlFieldValue_t. + * A scopeId of UINT_MAX returns aggregate value summed up across all links + * for the specified counter type in fieldId. + */ +#define NVML_FI_DEV_NVLINK_THROUGHPUT_DATA_TX 138 //!< NVLink TX Data throughput in KiB +#define NVML_FI_DEV_NVLINK_THROUGHPUT_DATA_RX 139 //!< NVLink RX Data throughput in KiB +#define NVML_FI_DEV_NVLINK_THROUGHPUT_RAW_TX 140 //!< NVLink TX Data + protocol overhead in KiB +#define NVML_FI_DEV_NVLINK_THROUGHPUT_RAW_RX 141 //!< NVLink RX Data + protocol overhead in KiB + +/* Row Remapper */ +#define NVML_FI_DEV_REMAPPED_COR 142 //!< Number of remapped rows due to correctable errors +#define NVML_FI_DEV_REMAPPED_UNC 143 //!< Number of remapped rows due to uncorrectable errors +#define NVML_FI_DEV_REMAPPED_PENDING 144 //!< If any rows are pending remapping. 1=yes 0=no +#define NVML_FI_DEV_REMAPPED_FAILURE 145 //!< If any rows failed to be remapped 1=yes 0=no + +/** + * Remote device NVLink ID + * + * Link ID needs to be specified in the scopeId field in nvmlFieldValue_t. + */ +#define NVML_FI_DEV_NVLINK_REMOTE_NVLINK_ID 146 //!< Remote device NVLink ID + +/** + * NVSwitch: connected NVLink count + */ +#define NVML_FI_DEV_NVSWITCH_CONNECTED_LINK_COUNT 147 //!< Number of NVLinks connected to NVSwitch + +/* NvLink ECC Data Error Counters + * + * Lane ID needs to be specified in the scopeId field in nvmlFieldValue_t. + * + */ +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L0 148 //!< NVLink data ECC Error Counter for Link 0 +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L1 149 //!< NVLink data ECC Error Counter for Link 1 +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L2 150 //!< NVLink data ECC Error Counter for Link 2 +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L3 151 //!< NVLink data ECC Error Counter for Link 3 +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L4 152 //!< NVLink data ECC Error Counter for Link 4 +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L5 153 //!< NVLink data ECC Error Counter for Link 5 +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L6 154 //!< NVLink data ECC Error Counter for Link 6 +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L7 155 //!< NVLink data ECC Error Counter for Link 7 +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L8 156 //!< NVLink data ECC Error Counter for Link 8 +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L9 157 //!< NVLink data ECC Error Counter for Link 9 +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L10 158 //!< NVLink data ECC Error Counter for Link 10 +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L11 159 //!< NVLink data ECC Error Counter for Link 11 +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_TOTAL 160 //!< NvLink data ECC Error Counter total for all Links + +#define NVML_FI_DEV_NVLINK_ERROR_DL_REPLAY 161 +#define NVML_FI_DEV_NVLINK_ERROR_DL_RECOVERY 162 +#define NVML_FI_DEV_NVLINK_ERROR_DL_CRC 163 +#define NVML_FI_DEV_NVLINK_GET_SPEED 164 +#define NVML_FI_DEV_NVLINK_GET_STATE 165 +#define NVML_FI_DEV_NVLINK_GET_VERSION 166 + +#define NVML_FI_DEV_NVLINK_GET_POWER_STATE 167 +#define NVML_FI_DEV_NVLINK_GET_POWER_THRESHOLD 168 + +#define NVML_FI_DEV_PCIE_L0_TO_RECOVERY_COUNTER 169 + +#define NVML_FI_MAX 170 //!< One greater than the largest field ID defined above + +/** + * Information for a Field Value Sample + */ +typedef struct nvmlFieldValue_st +{ + unsigned int fieldId; //!< ID of the NVML field to retrieve. This must be set before any call that uses this struct. See the constants starting with NVML_FI_ above. + unsigned int scopeId; //!< Scope ID can represent data used by NVML depending on fieldId's context. For example, for NVLink throughput counter data, scopeId can represent linkId. + long long timestamp; //!< CPU Timestamp of this value in microseconds since 1970 + long long latencyUsec; //!< How long this field value took to update (in usec) within NVML. This may be averaged across several fields that are serviced by the same driver call. + nvmlValueType_t valueType; //!< Type of the value stored in value + nvmlReturn_t nvmlReturn; //!< Return code for retrieving this value. This must be checked before looking at value, as value is undefined if nvmlReturn != NVML_SUCCESS + nvmlValue_t value; //!< Value for this field. This is only valid if nvmlReturn == NVML_SUCCESS +} nvmlFieldValue_t; + + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlUnitStructs Unit Structs + * @{ + */ +/***************************************************************************************************/ + +typedef struct nvmlUnit_st* nvmlUnit_t; + +/** + * Description of HWBC entry + */ +typedef struct nvmlHwbcEntry_st +{ + unsigned int hwbcId; + char firmwareVersion[32]; +} nvmlHwbcEntry_t; + +/** + * Fan state enum. + */ +typedef enum nvmlFanState_enum +{ + NVML_FAN_NORMAL = 0, //!< Fan is working properly + NVML_FAN_FAILED = 1 //!< Fan has failed +} nvmlFanState_t; + +/** + * Led color enum. + */ +typedef enum nvmlLedColor_enum +{ + NVML_LED_COLOR_GREEN = 0, //!< GREEN, indicates good health + NVML_LED_COLOR_AMBER = 1 //!< AMBER, indicates problem +} nvmlLedColor_t; + + +/** + * LED states for an S-class unit. + */ +typedef struct nvmlLedState_st +{ + char cause[256]; //!< If amber, a text description of the cause + nvmlLedColor_t color; //!< GREEN or AMBER +} nvmlLedState_t; + +/** + * Static S-class unit info. + */ +typedef struct nvmlUnitInfo_st +{ + char name[96]; //!< Product name + char id[96]; //!< Product identifier + char serial[96]; //!< Product serial number + char firmwareVersion[96]; //!< Firmware version +} nvmlUnitInfo_t; + +/** + * Power usage information for an S-class unit. + * The power supply state is a human readable string that equals "Normal" or contains + * a combination of "Abnormal" plus one or more of the following: + * + * - High voltage + * - Fan failure + * - Heatsink temperature + * - Current limit + * - Voltage below UV alarm threshold + * - Low-voltage + * - SI2C remote off command + * - MOD_DISABLE input + * - Short pin transition +*/ +typedef struct nvmlPSUInfo_st +{ + char state[256]; //!< The power supply state + unsigned int current; //!< PSU current (A) + unsigned int voltage; //!< PSU voltage (V) + unsigned int power; //!< PSU power draw (W) +} nvmlPSUInfo_t; + +/** + * Fan speed reading for a single fan in an S-class unit. + */ +typedef struct nvmlUnitFanInfo_st +{ + unsigned int speed; //!< Fan speed (RPM) + nvmlFanState_t state; //!< Flag that indicates whether fan is working properly +} nvmlUnitFanInfo_t; + +/** + * Fan speed readings for an entire S-class unit. + */ +typedef struct nvmlUnitFanSpeeds_st +{ + nvmlUnitFanInfo_t fans[24]; //!< Fan speed data for each fan + unsigned int count; //!< Number of fans in unit +} nvmlUnitFanSpeeds_t; + +/** @} */ + +/***************************************************************************************************/ +/** @addtogroup nvmlEvents + * @{ + */ +/***************************************************************************************************/ + +/** + * Handle to an event set + */ +typedef struct nvmlEventSet_st* nvmlEventSet_t; + +/** @defgroup nvmlEventType Event Types + * @{ + * Event Types which user can be notified about. + * See description of particular functions for details. + * + * See \ref nvmlDeviceRegisterEvents and \ref nvmlDeviceGetSupportedEventTypes to check which devices + * support each event. + * + * Types can be combined with bitwise or operator '|' when passed to \ref nvmlDeviceRegisterEvents + */ +//! Event about single bit ECC errors +/** + * \note A corrected texture memory error is not an ECC error, so it does not generate a single bit event + */ +#define nvmlEventTypeSingleBitEccError 0x0000000000000001LL + +//! Event about double bit ECC errors +/** + * \note An uncorrected texture memory error is not an ECC error, so it does not generate a double bit event + */ +#define nvmlEventTypeDoubleBitEccError 0x0000000000000002LL + +//! Event about PState changes +/** + * \note On Fermi architecture PState changes are also an indicator that GPU is throttling down due to + * no work being executed on the GPU, power capping or thermal capping. In a typical situation, + * Fermi-based GPU should stay in P0 for the duration of the execution of the compute process. + */ +#define nvmlEventTypePState 0x0000000000000004LL + +//! Event that Xid critical error occurred +#define nvmlEventTypeXidCriticalError 0x0000000000000008LL + +//! Event about clock changes +/** + * Kepler only + */ +#define nvmlEventTypeClock 0x0000000000000010LL + +//! Event about AC/Battery power source changes +#define nvmlEventTypePowerSourceChange 0x0000000000000080LL + +//! Event about MIG configuration changes +#define nvmlEventMigConfigChange 0x0000000000000100LL + +//! Mask with no events +#define nvmlEventTypeNone 0x0000000000000000LL + +//! Mask of all events +#define nvmlEventTypeAll (nvmlEventTypeNone \ + | nvmlEventTypeSingleBitEccError \ + | nvmlEventTypeDoubleBitEccError \ + | nvmlEventTypePState \ + | nvmlEventTypeClock \ + | nvmlEventTypeXidCriticalError \ + | nvmlEventTypePowerSourceChange \ + | nvmlEventMigConfigChange \ + ) +/** @} */ + +/** + * Information about occurred event + */ +typedef struct nvmlEventData_st +{ + nvmlDevice_t device; //!< Specific device where the event occurred + unsigned long long eventType; //!< Information about what specific event occurred + unsigned long long eventData; //!< Stores XID error for the device in the event of nvmlEventTypeXidCriticalError, + // eventData is 0 for any other event. eventData is set as 999 for unknown xid error. + unsigned int gpuInstanceId; //!< If MIG is enabled and nvmlEventTypeXidCriticalError event is attributable to a GPU + // instance, stores a valid GPU instance ID. gpuInstanceId is set to 0xFFFFFFFF + // otherwise. + unsigned int computeInstanceId; //!< If MIG is enabled and nvmlEventTypeXidCriticalError event is attributable to a + // compute instance, stores a valid compute instance ID. computeInstanceId is set to + // 0xFFFFFFFF otherwise. +} nvmlEventData_t; + +/** @} */ + +/***************************************************************************************************/ +/** @addtogroup nvmlClocksThrottleReasons + * @{ + */ +/***************************************************************************************************/ + +/** Nothing is running on the GPU and the clocks are dropping to Idle state + * \note This limiter may be removed in a later release + */ +#define nvmlClocksThrottleReasonGpuIdle 0x0000000000000001LL + +/** GPU clocks are limited by current setting of applications clocks + * + * @see nvmlDeviceSetApplicationsClocks + * @see nvmlDeviceGetApplicationsClock + */ +#define nvmlClocksThrottleReasonApplicationsClocksSetting 0x0000000000000002LL + +/** + * @deprecated Renamed to \ref nvmlClocksThrottleReasonApplicationsClocksSetting + * as the name describes the situation more accurately. + */ +#define nvmlClocksThrottleReasonUserDefinedClocks nvmlClocksThrottleReasonApplicationsClocksSetting + +/** SW Power Scaling algorithm is reducing the clocks below requested clocks + * + * @see nvmlDeviceGetPowerUsage + * @see nvmlDeviceSetPowerManagementLimit + * @see nvmlDeviceGetPowerManagementLimit + */ +#define nvmlClocksThrottleReasonSwPowerCap 0x0000000000000004LL + +/** HW Slowdown (reducing the core clocks by a factor of 2 or more) is engaged + * + * This is an indicator of: + * - temperature being too high + * - External Power Brake Assertion is triggered (e.g. by the system power supply) + * - Power draw is too high and Fast Trigger protection is reducing the clocks + * - May be also reported during PState or clock change + * - This behavior may be removed in a later release. + * + * @see nvmlDeviceGetTemperature + * @see nvmlDeviceGetTemperatureThreshold + * @see nvmlDeviceGetPowerUsage + */ +#define nvmlClocksThrottleReasonHwSlowdown 0x0000000000000008LL + +/** Sync Boost + * + * This GPU has been added to a Sync boost group with nvidia-smi or DCGM in + * order to maximize performance per watt. All GPUs in the sync boost group + * will boost to the minimum possible clocks across the entire group. Look at + * the throttle reasons for other GPUs in the system to see why those GPUs are + * holding this one at lower clocks. + * + */ +#define nvmlClocksThrottleReasonSyncBoost 0x0000000000000010LL + +/** SW Thermal Slowdown + * + * This is an indicator of one or more of the following: + * - Current GPU temperature above the GPU Max Operating Temperature + * - Current memory temperature above the Memory Max Operating Temperature + * + */ +#define nvmlClocksThrottleReasonSwThermalSlowdown 0x0000000000000020LL + +/** HW Thermal Slowdown (reducing the core clocks by a factor of 2 or more) is engaged + * + * This is an indicator of: + * - temperature being too high + * + * @see nvmlDeviceGetTemperature + * @see nvmlDeviceGetTemperatureThreshold + * @see nvmlDeviceGetPowerUsage + */ +#define nvmlClocksThrottleReasonHwThermalSlowdown 0x0000000000000040LL + +/** HW Power Brake Slowdown (reducing the core clocks by a factor of 2 or more) is engaged + * + * This is an indicator of: + * - External Power Brake Assertion being triggered (e.g. by the system power supply) + * + * @see nvmlDeviceGetTemperature + * @see nvmlDeviceGetTemperatureThreshold + * @see nvmlDeviceGetPowerUsage + */ +#define nvmlClocksThrottleReasonHwPowerBrakeSlowdown 0x0000000000000080LL + +/** GPU clocks are limited by current setting of Display clocks + * + * @see bug 1997531 + */ +#define nvmlClocksThrottleReasonDisplayClockSetting 0x0000000000000100LL + +/** Bit mask representing no clocks throttling + * + * Clocks are as high as possible. + * */ +#define nvmlClocksThrottleReasonNone 0x0000000000000000LL + +/** Bit mask representing all supported clocks throttling reasons + * New reasons might be added to this list in the future + */ +#define nvmlClocksThrottleReasonAll (nvmlClocksThrottleReasonNone \ + | nvmlClocksThrottleReasonGpuIdle \ + | nvmlClocksThrottleReasonApplicationsClocksSetting \ + | nvmlClocksThrottleReasonSwPowerCap \ + | nvmlClocksThrottleReasonHwSlowdown \ + | nvmlClocksThrottleReasonSyncBoost \ + | nvmlClocksThrottleReasonSwThermalSlowdown \ + | nvmlClocksThrottleReasonHwThermalSlowdown \ + | nvmlClocksThrottleReasonHwPowerBrakeSlowdown \ + | nvmlClocksThrottleReasonDisplayClockSetting \ +) +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlAccountingStats Accounting Statistics + * @{ + * + * Set of APIs designed to provide per process information about usage of GPU. + * + * @note All accounting statistics and accounting mode live in nvidia driver and reset + * to default (Disabled) when driver unloads. + * It is advised to run with persistence mode enabled. + * + * @note Enabling accounting mode has no negative impact on the GPU performance. + */ +/***************************************************************************************************/ + +/** + * Describes accounting statistics of a process. + */ +typedef struct nvmlAccountingStats_st { + unsigned int gpuUtilization; //!< Percent of time over the process's lifetime during which one or more kernels was executing on the GPU. + //! Utilization stats just like returned by \ref nvmlDeviceGetUtilizationRates but for the life time of a + //! process (not just the last sample period). + //! Set to NVML_VALUE_NOT_AVAILABLE if nvmlDeviceGetUtilizationRates is not supported + + unsigned int memoryUtilization; //!< Percent of time over the process's lifetime during which global (device) memory was being read or written. + //! Set to NVML_VALUE_NOT_AVAILABLE if nvmlDeviceGetUtilizationRates is not supported + + unsigned long long maxMemoryUsage; //!< Maximum total memory in bytes that was ever allocated by the process. + //! Set to NVML_VALUE_NOT_AVAILABLE if nvmlProcessInfo_t->usedGpuMemory is not supported + + + unsigned long long time; //!< Amount of time in ms during which the compute context was active. The time is reported as 0 if + //!< the process is not terminated + + unsigned long long startTime; //!< CPU Timestamp in usec representing start time for the process + + unsigned int isRunning; //!< Flag to represent if the process is running (1 for running, 0 for terminated) + + unsigned int reserved[5]; //!< Reserved for future use +} nvmlAccountingStats_t; + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlEncoderStructs Encoder Structs + * @{ + */ +/***************************************************************************************************/ + +/** + * Represents type of encoder for capacity can be queried + */ +typedef enum nvmlEncoderQueryType_enum +{ + NVML_ENCODER_QUERY_H264 = 0, //!< H264 encoder + NVML_ENCODER_QUERY_HEVC = 1 //!< HEVC encoder +}nvmlEncoderType_t; + +/** + * Structure to hold encoder session data + */ +typedef struct nvmlEncoderSessionInfo_st +{ + unsigned int sessionId; //!< Unique session ID + unsigned int pid; //!< Owning process ID + nvmlVgpuInstance_t vgpuInstance; //!< Owning vGPU instance ID (only valid on vGPU hosts, otherwise zero) + nvmlEncoderType_t codecType; //!< Video encoder type + unsigned int hResolution; //!< Current encode horizontal resolution + unsigned int vResolution; //!< Current encode vertical resolution + unsigned int averageFps; //!< Moving average encode frames per second + unsigned int averageLatency; //!< Moving average encode latency in microseconds +}nvmlEncoderSessionInfo_t; + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlFBCStructs Frame Buffer Capture Structures +* @{ +*/ +/***************************************************************************************************/ + +/** + * Represents frame buffer capture session type + */ +typedef enum nvmlFBCSessionType_enum +{ + NVML_FBC_SESSION_TYPE_UNKNOWN = 0, //!< Unknwon + NVML_FBC_SESSION_TYPE_TOSYS, //!< ToSys + NVML_FBC_SESSION_TYPE_CUDA, //!< Cuda + NVML_FBC_SESSION_TYPE_VID, //!< Vid + NVML_FBC_SESSION_TYPE_HWENC //!< HEnc +} nvmlFBCSessionType_t; + +/** + * Structure to hold frame buffer capture sessions stats + */ +typedef struct nvmlFBCStats_st +{ + unsigned int sessionsCount; //!< Total no of sessions + unsigned int averageFPS; //!< Moving average new frames captured per second + unsigned int averageLatency; //!< Moving average new frame capture latency in microseconds +} nvmlFBCStats_t; + +#define NVML_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED 0x00000001 //!< Bit specifying differential map state. +#define NVML_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED 0x00000002 //!< Bit specifying classification map state. +#define NVML_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_NO_WAIT 0x00000004 //!< Bit specifying if capture was requested as non-blocking call. +#define NVML_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_INFINITE 0x00000008 //!< Bit specifying if capture was requested as blocking call. +#define NVML_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_TIMEOUT 0x00000010 //!< Bit specifying if capture was requested as blocking call with timeout period. + +/** + * Structure to hold FBC session data + */ +typedef struct nvmlFBCSessionInfo_st +{ + unsigned int sessionId; //!< Unique session ID + unsigned int pid; //!< Owning process ID + nvmlVgpuInstance_t vgpuInstance; //!< Owning vGPU instance ID (only valid on vGPU hosts, otherwise zero) + unsigned int displayOrdinal; //!< Display identifier + nvmlFBCSessionType_t sessionType; //!< Type of frame buffer capture session + unsigned int sessionFlags; //!< Session flags (one or more of NVML_NVFBC_SESSION_FLAG_XXX). + unsigned int hMaxResolution; //!< Max horizontal resolution supported by the capture session + unsigned int vMaxResolution; //!< Max vertical resolution supported by the capture session + unsigned int hResolution; //!< Horizontal resolution requested by caller in capture call + unsigned int vResolution; //!< Vertical resolution requested by caller in capture call + unsigned int averageFPS; //!< Moving average new frames captured per second + unsigned int averageLatency; //!< Moving average new frame capture latency in microseconds +} nvmlFBCSessionInfo_t; + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlDrainDefs definitions related to the drain state + * @{ + */ +/***************************************************************************************************/ + +/** + * Is the GPU device to be removed from the kernel by nvmlDeviceRemoveGpu() + */ +typedef enum nvmlDetachGpuState_enum +{ + NVML_DETACH_GPU_KEEP = 0, + NVML_DETACH_GPU_REMOVE +} nvmlDetachGpuState_t; + +/** + * Parent bridge PCIe link state requested by nvmlDeviceRemoveGpu() + */ +typedef enum nvmlPcieLinkState_enum +{ + NVML_PCIE_LINK_KEEP = 0, + NVML_PCIE_LINK_SHUT_DOWN +} nvmlPcieLinkState_t; + +/** @} */ + +#define NVML_GPU_FABRIC_UUID_LEN 16 + +#define NVML_GPU_FABRIC_STATE_NOT_SUPPORTED 0 +#define NVML_GPU_FABRIC_STATE_NOT_STARTED 1 +#define NVML_GPU_FABRIC_STATE_IN_PROGRESS 2 +#define NVML_GPU_FABRIC_STATE_COMPLETED 3 + +typedef unsigned char nvmlGpuFabricState_t; + +typedef struct { + char clusterUuid[NVML_GPU_FABRIC_UUID_LEN]; //!< Uuid of the cluster to which this GPU belongs + nvmlReturn_t status; //!< Error status, if any. Must be checked only if state returns "complete". + unsigned int partitionId; //!< ID of the fabric partition to which this GPU belongs + nvmlGpuFabricState_t state; //!< Current state of GPU registration process +} nvmlGpuFabricInfo_t; +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlInitializationAndCleanup Initialization and Cleanup + * This chapter describes the methods that handle NVML initialization and cleanup. + * It is the user's responsibility to call \ref nvmlInit_v2() before calling any other methods, and + * nvmlShutdown() once NVML is no longer being used. + * @{ + */ +/***************************************************************************************************/ + +#define NVML_INIT_FLAG_NO_GPUS 1 //!< Don't fail nvmlInit() when no GPUs are found +#define NVML_INIT_FLAG_NO_ATTACH 2 //!< Don't attach GPUs + +/** + * Initialize NVML, but don't initialize any GPUs yet. + * + * \note nvmlInit_v3 introduces a "flags" argument, that allows passing boolean values + * modifying the behaviour of nvmlInit(). + * \note In NVML 5.319 new nvmlInit_v2 has replaced nvmlInit"_v1" (default in NVML 4.304 and older) that + * did initialize all GPU devices in the system. + * + * This allows NVML to communicate with a GPU + * when other GPUs in the system are unstable or in a bad state. When using this API, GPUs are + * discovered and initialized in nvmlDeviceGetHandleBy* functions instead. + * + * \note To contrast nvmlInit_v2 with nvmlInit"_v1", NVML 4.304 nvmlInit"_v1" will fail when any detected GPU is in + * a bad or unstable state. + * + * For all products. + * + * This method, should be called once before invoking any other methods in the library. + * A reference count of the number of initializations is maintained. Shutdown only occurs + * when the reference count reaches zero. + * + * @return + * - \ref NVML_SUCCESS if NVML has been properly initialized + * - \ref NVML_ERROR_DRIVER_NOT_LOADED if NVIDIA driver is not running + * - \ref NVML_ERROR_NO_PERMISSION if NVML does not have permission to talk to the driver + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlInit_v2(void); + +/** + * nvmlInitWithFlags is a variant of nvmlInit(), that allows passing a set of boolean values + * modifying the behaviour of nvmlInit(). + * Other than the "flags" parameter it is completely similar to \ref nvmlInit_v2. + * + * For all products. + * + * @param flags behaviour modifier flags + * + * @return + * - \ref NVML_SUCCESS if NVML has been properly initialized + * - \ref NVML_ERROR_DRIVER_NOT_LOADED if NVIDIA driver is not running + * - \ref NVML_ERROR_NO_PERMISSION if NVML does not have permission to talk to the driver + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlInitWithFlags(unsigned int flags); + +/** + * Shut down NVML by releasing all GPU resources previously allocated with \ref nvmlInit_v2(). + * + * For all products. + * + * This method should be called after NVML work is done, once for each call to \ref nvmlInit_v2() + * A reference count of the number of initializations is maintained. Shutdown only occurs + * when the reference count reaches zero. For backwards compatibility, no error is reported if + * nvmlShutdown() is called more times than nvmlInit(). + * + * @return + * - \ref NVML_SUCCESS if NVML has been properly shut down + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlShutdown(void); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlErrorReporting Error reporting + * This chapter describes helper functions for error reporting routines. + * @{ + */ +/***************************************************************************************************/ + +/** + * Helper method for converting NVML error codes into readable strings. + * + * For all products. + * + * @param result NVML error code to convert + * + * @return String representation of the error. + * + */ +const DECLDIR char* nvmlErrorString(nvmlReturn_t result); +/** @} */ + + +/***************************************************************************************************/ +/** @defgroup nvmlConstants Constants + * @{ + */ +/***************************************************************************************************/ + +/** + * Buffer size guaranteed to be large enough for \ref nvmlDeviceGetInforomVersion and \ref nvmlDeviceGetInforomImageVersion + */ +#define NVML_DEVICE_INFOROM_VERSION_BUFFER_SIZE 16 + +/** + * Buffer size guaranteed to be large enough for storing GPU identifiers. + */ +#define NVML_DEVICE_UUID_BUFFER_SIZE 80 + +/** + * Buffer size guaranteed to be large enough for \ref nvmlDeviceGetUUID + */ +#define NVML_DEVICE_UUID_V2_BUFFER_SIZE 96 + +/** + * Buffer size guaranteed to be large enough for \ref nvmlDeviceGetBoardPartNumber + */ +#define NVML_DEVICE_PART_NUMBER_BUFFER_SIZE 80 + +/** + * Buffer size guaranteed to be large enough for \ref nvmlSystemGetDriverVersion + */ +#define NVML_SYSTEM_DRIVER_VERSION_BUFFER_SIZE 80 + +/** + * Buffer size guaranteed to be large enough for \ref nvmlSystemGetNVMLVersion + */ +#define NVML_SYSTEM_NVML_VERSION_BUFFER_SIZE 80 + +/** + * Buffer size guaranteed to be large enough for storing GPU device names. + */ +#define NVML_DEVICE_NAME_BUFFER_SIZE 64 + +/** + * Buffer size guaranteed to be large enough for \ref nvmlDeviceGetName + */ +#define NVML_DEVICE_NAME_V2_BUFFER_SIZE 96 + +/** + * Buffer size guaranteed to be large enough for \ref nvmlDeviceGetSerial + */ +#define NVML_DEVICE_SERIAL_BUFFER_SIZE 30 + +/** + * Buffer size guaranteed to be large enough for \ref nvmlDeviceGetVbiosVersion + */ +#define NVML_DEVICE_VBIOS_VERSION_BUFFER_SIZE 32 + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlSystemQueries System Queries + * This chapter describes the queries that NVML can perform against the local system. These queries + * are not device-specific. + * @{ + */ +/***************************************************************************************************/ + +/** + * Retrieves the version of the system's graphics driver. + * + * For all products. + * + * The version identifier is an alphanumeric string. It will not exceed 80 characters in length + * (including the NULL terminator). See \ref nvmlConstants::NVML_SYSTEM_DRIVER_VERSION_BUFFER_SIZE. + * + * @param version Reference in which to return the version identifier + * @param length The maximum allowed length of the string returned in \a version + * + * @return + * - \ref NVML_SUCCESS if \a version has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a version is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a length is too small + */ +nvmlReturn_t DECLDIR nvmlSystemGetDriverVersion(char *version, unsigned int length); + +/** + * Retrieves the version of the NVML library. + * + * For all products. + * + * The version identifier is an alphanumeric string. It will not exceed 80 characters in length + * (including the NULL terminator). See \ref nvmlConstants::NVML_SYSTEM_NVML_VERSION_BUFFER_SIZE. + * + * @param version Reference in which to return the version identifier + * @param length The maximum allowed length of the string returned in \a version + * + * @return + * - \ref NVML_SUCCESS if \a version has been set + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a version is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a length is too small + */ +nvmlReturn_t DECLDIR nvmlSystemGetNVMLVersion(char *version, unsigned int length); + +/** + * Retrieves the version of the CUDA driver. + * + * For all products. + * + * The CUDA driver version returned will be retreived from the currently installed version of CUDA. + * If the cuda library is not found, this function will return a known supported version number. + * + * @param cudaDriverVersion Reference in which to return the version identifier + * + * @return + * - \ref NVML_SUCCESS if \a cudaDriverVersion has been set + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a cudaDriverVersion is NULL + */ +nvmlReturn_t DECLDIR nvmlSystemGetCudaDriverVersion(int *cudaDriverVersion); + +/** + * Retrieves the version of the CUDA driver from the shared library. + * + * For all products. + * + * The returned CUDA driver version by calling cuDriverGetVersion() + * + * @param cudaDriverVersion Reference in which to return the version identifier + * + * @return + * - \ref NVML_SUCCESS if \a cudaDriverVersion has been set + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a cudaDriverVersion is NULL + * - \ref NVML_ERROR_LIBRARY_NOT_FOUND if \a libcuda.so.1 or libcuda.dll is not found + * - \ref NVML_ERROR_FUNCTION_NOT_FOUND if \a cuDriverGetVersion() is not found in the shared library + */ +nvmlReturn_t DECLDIR nvmlSystemGetCudaDriverVersion_v2(int *cudaDriverVersion); + +/** + * Macros for converting the CUDA driver version number to Major and Minor version numbers. + */ +#define NVML_CUDA_DRIVER_VERSION_MAJOR(v) ((v)/1000) +#define NVML_CUDA_DRIVER_VERSION_MINOR(v) (((v)%1000)/10) + +/** + * Gets name of the process with provided process id + * + * For all products. + * + * Returned process name is cropped to provided length. + * name string is encoded in ANSI. + * + * @param pid The identifier of the process + * @param name Reference in which to return the process name + * @param length The maximum allowed length of the string returned in \a name + * + * @return + * - \ref NVML_SUCCESS if \a name has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a name is NULL or \a length is 0. + * - \ref NVML_ERROR_NOT_FOUND if process doesn't exists + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlSystemGetProcessName(unsigned int pid, char *name, unsigned int length); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlUnitQueries Unit Queries + * This chapter describes that queries that NVML can perform against each unit. For S-class systems only. + * In each case the device is identified with an nvmlUnit_t handle. This handle is obtained by + * calling \ref nvmlUnitGetHandleByIndex(). + * @{ + */ +/***************************************************************************************************/ + + /** + * Retrieves the number of units in the system. + * + * For S-class products. + * + * @param unitCount Reference in which to return the number of units + * + * @return + * - \ref NVML_SUCCESS if \a unitCount has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a unitCount is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlUnitGetCount(unsigned int *unitCount); + +/** + * Acquire the handle for a particular unit, based on its index. + * + * For S-class products. + * + * Valid indices are derived from the \a unitCount returned by \ref nvmlUnitGetCount(). + * For example, if \a unitCount is 2 the valid indices are 0 and 1, corresponding to UNIT 0 and UNIT 1. + * + * The order in which NVML enumerates units has no guarantees of consistency between reboots. + * + * @param index The index of the target unit, >= 0 and < \a unitCount + * @param unit Reference in which to return the unit handle + * + * @return + * - \ref NVML_SUCCESS if \a unit has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a index is invalid or \a unit is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlUnitGetHandleByIndex(unsigned int index, nvmlUnit_t *unit); + +/** + * Retrieves the static information associated with a unit. + * + * For S-class products. + * + * See \ref nvmlUnitInfo_t for details on available unit info. + * + * @param unit The identifier of the target unit + * @param info Reference in which to return the unit information + * + * @return + * - \ref NVML_SUCCESS if \a info has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a unit is invalid or \a info is NULL + */ +nvmlReturn_t DECLDIR nvmlUnitGetUnitInfo(nvmlUnit_t unit, nvmlUnitInfo_t *info); + +/** + * Retrieves the LED state associated with this unit. + * + * For S-class products. + * + * See \ref nvmlLedState_t for details on allowed states. + * + * @param unit The identifier of the target unit + * @param state Reference in which to return the current LED state + * + * @return + * - \ref NVML_SUCCESS if \a state has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a unit is invalid or \a state is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this is not an S-class product + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlUnitSetLedState() + */ +nvmlReturn_t DECLDIR nvmlUnitGetLedState(nvmlUnit_t unit, nvmlLedState_t *state); + +/** + * Retrieves the PSU stats for the unit. + * + * For S-class products. + * + * See \ref nvmlPSUInfo_t for details on available PSU info. + * + * @param unit The identifier of the target unit + * @param psu Reference in which to return the PSU information + * + * @return + * - \ref NVML_SUCCESS if \a psu has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a unit is invalid or \a psu is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this is not an S-class product + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlUnitGetPsuInfo(nvmlUnit_t unit, nvmlPSUInfo_t *psu); + +/** + * Retrieves the temperature readings for the unit, in degrees C. + * + * For S-class products. + * + * Depending on the product, readings may be available for intake (type=0), + * exhaust (type=1) and board (type=2). + * + * @param unit The identifier of the target unit + * @param type The type of reading to take + * @param temp Reference in which to return the intake temperature + * + * @return + * - \ref NVML_SUCCESS if \a temp has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a unit or \a type is invalid or \a temp is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this is not an S-class product + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlUnitGetTemperature(nvmlUnit_t unit, unsigned int type, unsigned int *temp); + +/** + * Retrieves the fan speed readings for the unit. + * + * For S-class products. + * + * See \ref nvmlUnitFanSpeeds_t for details on available fan speed info. + * + * @param unit The identifier of the target unit + * @param fanSpeeds Reference in which to return the fan speed information + * + * @return + * - \ref NVML_SUCCESS if \a fanSpeeds has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a unit is invalid or \a fanSpeeds is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this is not an S-class product + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlUnitGetFanSpeedInfo(nvmlUnit_t unit, nvmlUnitFanSpeeds_t *fanSpeeds); + +/** + * Retrieves the set of GPU devices that are attached to the specified unit. + * + * For S-class products. + * + * The \a deviceCount argument is expected to be set to the size of the input \a devices array. + * + * @param unit The identifier of the target unit + * @param deviceCount Reference in which to provide the \a devices array size, and + * to return the number of attached GPU devices + * @param devices Reference in which to return the references to the attached GPU devices + * + * @return + * - \ref NVML_SUCCESS if \a deviceCount and \a devices have been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a deviceCount indicates that the \a devices array is too small + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a unit is invalid, either of \a deviceCount or \a devices is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlUnitGetDevices(nvmlUnit_t unit, unsigned int *deviceCount, nvmlDevice_t *devices); + +/** + * Retrieves the IDs and firmware versions for any Host Interface Cards (HICs) in the system. + * + * For S-class products. + * + * The \a hwbcCount argument is expected to be set to the size of the input \a hwbcEntries array. + * The HIC must be connected to an S-class system for it to be reported by this function. + * + * @param hwbcCount Size of hwbcEntries array + * @param hwbcEntries Array holding information about hwbc + * + * @return + * - \ref NVML_SUCCESS if \a hwbcCount and \a hwbcEntries have been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if either \a hwbcCount or \a hwbcEntries is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a hwbcCount indicates that the \a hwbcEntries array is too small + */ +nvmlReturn_t DECLDIR nvmlSystemGetHicVersion(unsigned int *hwbcCount, nvmlHwbcEntry_t *hwbcEntries); +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlDeviceQueries Device Queries + * This chapter describes that queries that NVML can perform against each device. + * In each case the device is identified with an nvmlDevice_t handle. This handle is obtained by + * calling one of \ref nvmlDeviceGetHandleByIndex_v2(), \ref nvmlDeviceGetHandleBySerial(), + * \ref nvmlDeviceGetHandleByPciBusId_v2(). or \ref nvmlDeviceGetHandleByUUID(). + * @{ + */ +/***************************************************************************************************/ + + /** + * Retrieves the number of compute devices in the system. A compute device is a single GPU. + * + * For all products. + * + * Note: New nvmlDeviceGetCount_v2 (default in NVML 5.319) returns count of all devices in the system + * even if nvmlDeviceGetHandleByIndex_v2 returns NVML_ERROR_NO_PERMISSION for such device. + * Update your code to handle this error, or use NVML 4.304 or older nvml header file. + * For backward binary compatibility reasons _v1 version of the API is still present in the shared + * library. + * Old _v1 version of nvmlDeviceGetCount doesn't count devices that NVML has no permission to talk to. + * + * @param deviceCount Reference in which to return the number of accessible devices + * + * @return + * - \ref NVML_SUCCESS if \a deviceCount has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a deviceCount is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetCount_v2(unsigned int *deviceCount); + +/** + * Get attributes (engine counts etc.) for the given NVML device handle. + * + * @note This API currently only supports MIG device handles. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device NVML device handle + * @param attributes Device attributes + * + * @return + * - \ref NVML_SUCCESS if \a device attributes were successfully retrieved + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device handle is invalid + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetAttributes_v2(nvmlDevice_t device, nvmlDeviceAttributes_t *attributes); + +/** + * Acquire the handle for a particular device, based on its index. + * + * For all products. + * + * Valid indices are derived from the \a accessibleDevices count returned by + * \ref nvmlDeviceGetCount_v2(). For example, if \a accessibleDevices is 2 the valid indices + * are 0 and 1, corresponding to GPU 0 and GPU 1. + * + * The order in which NVML enumerates devices has no guarantees of consistency between reboots. For that reason it + * is recommended that devices be looked up by their PCI ids or UUID. See + * \ref nvmlDeviceGetHandleByUUID() and \ref nvmlDeviceGetHandleByPciBusId_v2(). + * + * Note: The NVML index may not correlate with other APIs, such as the CUDA device index. + * + * Starting from NVML 5, this API causes NVML to initialize the target GPU + * NVML may initialize additional GPUs if: + * - The target GPU is an SLI slave + * + * Note: New nvmlDeviceGetCount_v2 (default in NVML 5.319) returns count of all devices in the system + * even if nvmlDeviceGetHandleByIndex_v2 returns NVML_ERROR_NO_PERMISSION for such device. + * Update your code to handle this error, or use NVML 4.304 or older nvml header file. + * For backward binary compatibility reasons _v1 version of the API is still present in the shared + * library. + * Old _v1 version of nvmlDeviceGetCount doesn't count devices that NVML has no permission to talk to. + * + * This means that nvmlDeviceGetHandleByIndex_v2 and _v1 can return different devices for the same index. + * If you don't touch macros that map old (_v1) versions to _v2 versions at the top of the file you don't + * need to worry about that. + * + * @param index The index of the target GPU, >= 0 and < \a accessibleDevices + * @param device Reference in which to return the device handle + * + * @return + * - \ref NVML_SUCCESS if \a device has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a index is invalid or \a device is NULL + * - \ref NVML_ERROR_INSUFFICIENT_POWER if any attached devices have improperly attached external power cables + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to talk to this device + * - \ref NVML_ERROR_IRQ_ISSUE if NVIDIA kernel detected an interrupt issue with the attached GPUs + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetIndex + * @see nvmlDeviceGetCount + */ +nvmlReturn_t DECLDIR nvmlDeviceGetHandleByIndex_v2(unsigned int index, nvmlDevice_t *device); + +/** + * Acquire the handle for a particular device, based on its board serial number. + * + * For Fermi &tm; or newer fully supported devices. + * + * This number corresponds to the value printed directly on the board, and to the value returned by + * \ref nvmlDeviceGetSerial(). + * + * @deprecated Since more than one GPU can exist on a single board this function is deprecated in favor + * of \ref nvmlDeviceGetHandleByUUID. + * For dual GPU boards this function will return NVML_ERROR_INVALID_ARGUMENT. + * + * Starting from NVML 5, this API causes NVML to initialize the target GPU + * NVML may initialize additional GPUs as it searches for the target GPU + * + * @param serial The board serial number of the target GPU + * @param device Reference in which to return the device handle + * + * @return + * - \ref NVML_SUCCESS if \a device has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a serial is invalid, \a device is NULL or more than one + * device has the same serial (dual GPU boards) + * - \ref NVML_ERROR_NOT_FOUND if \a serial does not match a valid device on the system + * - \ref NVML_ERROR_INSUFFICIENT_POWER if any attached devices have improperly attached external power cables + * - \ref NVML_ERROR_IRQ_ISSUE if NVIDIA kernel detected an interrupt issue with the attached GPUs + * - \ref NVML_ERROR_GPU_IS_LOST if any GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetSerial + * @see nvmlDeviceGetHandleByUUID + */ +nvmlReturn_t DECLDIR nvmlDeviceGetHandleBySerial(const char *serial, nvmlDevice_t *device); + +/** + * Acquire the handle for a particular device, based on its globally unique immutable UUID associated with each device. + * + * For all products. + * + * @param uuid The UUID of the target GPU or MIG instance + * @param device Reference in which to return the device handle or MIG device handle + * + * Starting from NVML 5, this API causes NVML to initialize the target GPU + * NVML may initialize additional GPUs as it searches for the target GPU + * + * @return + * - \ref NVML_SUCCESS if \a device has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a uuid is invalid or \a device is null + * - \ref NVML_ERROR_NOT_FOUND if \a uuid does not match a valid device on the system + * - \ref NVML_ERROR_INSUFFICIENT_POWER if any attached devices have improperly attached external power cables + * - \ref NVML_ERROR_IRQ_ISSUE if NVIDIA kernel detected an interrupt issue with the attached GPUs + * - \ref NVML_ERROR_GPU_IS_LOST if any GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetUUID + */ +nvmlReturn_t DECLDIR nvmlDeviceGetHandleByUUID(const char *uuid, nvmlDevice_t *device); + +/** + * Acquire the handle for a particular device, based on its PCI bus id. + * + * For all products. + * + * This value corresponds to the nvmlPciInfo_t::busId returned by \ref nvmlDeviceGetPciInfo_v3(). + * + * Starting from NVML 5, this API causes NVML to initialize the target GPU + * NVML may initialize additional GPUs if: + * - The target GPU is an SLI slave + * + * \note NVML 4.304 and older version of nvmlDeviceGetHandleByPciBusId"_v1" returns NVML_ERROR_NOT_FOUND + * instead of NVML_ERROR_NO_PERMISSION. + * + * @param pciBusId The PCI bus id of the target GPU + * @param device Reference in which to return the device handle + * + * @return + * - \ref NVML_SUCCESS if \a device has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a pciBusId is invalid or \a device is NULL + * - \ref NVML_ERROR_NOT_FOUND if \a pciBusId does not match a valid device on the system + * - \ref NVML_ERROR_INSUFFICIENT_POWER if the attached device has improperly attached external power cables + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to talk to this device + * - \ref NVML_ERROR_IRQ_ISSUE if NVIDIA kernel detected an interrupt issue with the attached GPUs + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetHandleByPciBusId_v2(const char *pciBusId, nvmlDevice_t *device); + +/** + * Retrieves the name of this device. + * + * For all products. + * + * The name is an alphanumeric string that denotes a particular product, e.g. Tesla &tm; C2070. It will not + * exceed 96 characters in length (including the NULL terminator). See \ref + * nvmlConstants::NVML_DEVICE_NAME_V2_BUFFER_SIZE. + * + * When used with MIG device handles the API returns MIG device names which can be used to identify devices + * based on their attributes. + * + * @param device The identifier of the target device + * @param name Reference in which to return the product name + * @param length The maximum allowed length of the string returned in \a name + * + * @return + * - \ref NVML_SUCCESS if \a name has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a name is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a length is too small + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetName(nvmlDevice_t device, char *name, unsigned int length); + +/** + * Retrieves the brand of this device. + * + * For all products. + * + * The type is a member of \ref nvmlBrandType_t defined above. + * + * @param device The identifier of the target device + * @param type Reference in which to return the product brand type + * + * @return + * - \ref NVML_SUCCESS if \a name has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a type is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetBrand(nvmlDevice_t device, nvmlBrandType_t *type); + +/** + * Retrieves the NVML index of this device. + * + * For all products. + * + * Valid indices are derived from the \a accessibleDevices count returned by + * \ref nvmlDeviceGetCount_v2(). For example, if \a accessibleDevices is 2 the valid indices + * are 0 and 1, corresponding to GPU 0 and GPU 1. + * + * The order in which NVML enumerates devices has no guarantees of consistency between reboots. For that reason it + * is recommended that devices be looked up by their PCI ids or GPU UUID. See + * \ref nvmlDeviceGetHandleByPciBusId_v2() and \ref nvmlDeviceGetHandleByUUID(). + * + * When used with MIG device handles this API returns indices that can be + * passed to \ref nvmlDeviceGetMigDeviceHandleByIndex to retrieve an identical handle. + * MIG device indices are unique within a device. + * + * Note: The NVML index may not correlate with other APIs, such as the CUDA device index. + * + * @param device The identifier of the target device + * @param index Reference in which to return the NVML index of the device + * + * @return + * - \ref NVML_SUCCESS if \a index has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a index is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetHandleByIndex() + * @see nvmlDeviceGetCount() + */ +nvmlReturn_t DECLDIR nvmlDeviceGetIndex(nvmlDevice_t device, unsigned int *index); + +/** + * Retrieves the globally unique board serial number associated with this device's board. + * + * For all products with an inforom. + * + * The serial number is an alphanumeric string that will not exceed 30 characters (including the NULL terminator). + * This number matches the serial number tag that is physically attached to the board. See \ref + * nvmlConstants::NVML_DEVICE_SERIAL_BUFFER_SIZE. + * + * @param device The identifier of the target device + * @param serial Reference in which to return the board/module serial number + * @param length The maximum allowed length of the string returned in \a serial + * + * @return + * - \ref NVML_SUCCESS if \a serial has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a serial is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a length is too small + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetSerial(nvmlDevice_t device, char *serial, unsigned int length); + + +/***************************************************************************************************/ + +/** @defgroup nvmlAffinity CPU and Memory Affinity + * This chapter describes NVML operations that are associated with CPU and memory + * affinity. + * @{ + */ +/***************************************************************************************************/ + +//! Scope of NUMA node for affinity queries +#define NVML_AFFINITY_SCOPE_NODE 0 +//! Scope of processor socket for affinity queries +#define NVML_AFFINITY_SCOPE_SOCKET 1 + +typedef unsigned int nvmlAffinityScope_t; + +/** + * Retrieves an array of unsigned ints (sized to nodeSetSize) of bitmasks with + * the ideal memory affinity within node or socket for the device. + * For example, if NUMA node 0, 1 are ideal within the socket for the device and nodeSetSize == 1, + * result[0] = 0x3 + * + * \note If requested scope is not applicable to the target topology, the API + * will fall back to reporting the memory affinity for the immediate non-I/O + * ancestor of the device. + * + * For Kepler &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device The identifier of the target device + * @param nodeSetSize The size of the nodeSet array that is safe to access + * @param nodeSet Array reference in which to return a bitmask of NODEs, 64 NODEs per + * unsigned long on 64-bit machines, 32 on 32-bit machines + * @param scope Scope that change the default behavior + * + * @return + * - \ref NVML_SUCCESS if \a NUMA node Affinity has been filled + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, nodeSetSize == 0, nodeSet is NULL or scope is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ + +nvmlReturn_t DECLDIR nvmlDeviceGetMemoryAffinity(nvmlDevice_t device, unsigned int nodeSetSize, unsigned long *nodeSet, nvmlAffinityScope_t scope); + +/** + * Retrieves an array of unsigned ints (sized to cpuSetSize) of bitmasks with the + * ideal CPU affinity within node or socket for the device. + * For example, if processors 0, 1, 32, and 33 are ideal for the device and cpuSetSize == 2, + * result[0] = 0x3, result[1] = 0x3 + * + * \note If requested scope is not applicable to the target topology, the API + * will fall back to reporting the CPU affinity for the immediate non-I/O + * ancestor of the device. + * + * For Kepler &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device The identifier of the target device + * @param cpuSetSize The size of the cpuSet array that is safe to access + * @param cpuSet Array reference in which to return a bitmask of CPUs, 64 CPUs per + * unsigned long on 64-bit machines, 32 on 32-bit machines + * @param scope Scope that change the default behavior + * + * @return + * - \ref NVML_SUCCESS if \a cpuAffinity has been filled + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, cpuSetSize == 0, cpuSet is NULL or sope is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ + +nvmlReturn_t DECLDIR nvmlDeviceGetCpuAffinityWithinScope(nvmlDevice_t device, unsigned int cpuSetSize, unsigned long *cpuSet, nvmlAffinityScope_t scope); + +/** + * Retrieves an array of unsigned ints (sized to cpuSetSize) of bitmasks with the ideal CPU affinity for the device + * For example, if processors 0, 1, 32, and 33 are ideal for the device and cpuSetSize == 2, + * result[0] = 0x3, result[1] = 0x3 + * This is equivalent to calling \ref nvmlDeviceGetCpuAffinityWithinScope with \ref NVML_AFFINITY_SCOPE_NODE. + * + * For Kepler &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device The identifier of the target device + * @param cpuSetSize The size of the cpuSet array that is safe to access + * @param cpuSet Array reference in which to return a bitmask of CPUs, 64 CPUs per + * unsigned long on 64-bit machines, 32 on 32-bit machines + * + * @return + * - \ref NVML_SUCCESS if \a cpuAffinity has been filled + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, cpuSetSize == 0, or cpuSet is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetCpuAffinity(nvmlDevice_t device, unsigned int cpuSetSize, unsigned long *cpuSet); + +/** + * Sets the ideal affinity for the calling thread and device using the guidelines + * given in nvmlDeviceGetCpuAffinity(). Note, this is a change as of version 8.0. + * Older versions set the affinity for a calling process and all children. + * Currently supports up to 1024 processors. + * + * For Kepler &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device The identifier of the target device + * + * @return + * - \ref NVML_SUCCESS if the calling process has been successfully bound + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceSetCpuAffinity(nvmlDevice_t device); + +/** + * Clear all affinity bindings for the calling thread. Note, this is a change as of version + * 8.0 as older versions cleared the affinity for a calling process and all children. + * + * For Kepler &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device The identifier of the target device + * + * @return + * - \ref NVML_SUCCESS if the calling process has been successfully unbound + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceClearCpuAffinity(nvmlDevice_t device); + +/** + * Retrieve the common ancestor for two devices + * For all products. + * Supported on Linux only. + * + * @param device1 The identifier of the first device + * @param device2 The identifier of the second device + * @param pathInfo A \ref nvmlGpuTopologyLevel_t that gives the path type + * + * @return + * - \ref NVML_SUCCESS if \a pathInfo has been set + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device1, or \a device2 is invalid, or \a pathInfo is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device or OS does not support this feature + * - \ref NVML_ERROR_UNKNOWN an error has occurred in underlying topology discovery + */ + +/** @} */ +nvmlReturn_t DECLDIR nvmlDeviceGetTopologyCommonAncestor(nvmlDevice_t device1, nvmlDevice_t device2, nvmlGpuTopologyLevel_t *pathInfo); + +/** + * Retrieve the set of GPUs that are nearest to a given device at a specific interconnectivity level + * For all products. + * Supported on Linux only. + * + * @param device The identifier of the first device + * @param level The \ref nvmlGpuTopologyLevel_t level to search for other GPUs + * @param count When zero, is set to the number of matching GPUs such that \a deviceArray + * can be malloc'd. When non-zero, \a deviceArray will be filled with \a count + * number of device handles. + * @param deviceArray An array of device handles for GPUs found at \a level + * + * @return + * - \ref NVML_SUCCESS if \a deviceArray or \a count (if initially zero) has been set + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a level, or \a count is invalid, or \a deviceArray is NULL with a non-zero \a count + * - \ref NVML_ERROR_NOT_SUPPORTED if the device or OS does not support this feature + * - \ref NVML_ERROR_UNKNOWN an error has occurred in underlying topology discovery + */ +nvmlReturn_t DECLDIR nvmlDeviceGetTopologyNearestGpus(nvmlDevice_t device, nvmlGpuTopologyLevel_t level, unsigned int *count, nvmlDevice_t *deviceArray); + +/** + * Retrieve the set of GPUs that have a CPU affinity with the given CPU number + * For all products. + * Supported on Linux only. + * + * @param cpuNumber The CPU number + * @param count When zero, is set to the number of matching GPUs such that \a deviceArray + * can be malloc'd. When non-zero, \a deviceArray will be filled with \a count + * number of device handles. + * @param deviceArray An array of device handles for GPUs found with affinity to \a cpuNumber + * + * @return + * - \ref NVML_SUCCESS if \a deviceArray or \a count (if initially zero) has been set + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a cpuNumber, or \a count is invalid, or \a deviceArray is NULL with a non-zero \a count + * - \ref NVML_ERROR_NOT_SUPPORTED if the device or OS does not support this feature + * - \ref NVML_ERROR_UNKNOWN an error has occurred in underlying topology discovery + */ +nvmlReturn_t DECLDIR nvmlSystemGetTopologyGpuSet(unsigned int cpuNumber, unsigned int *count, nvmlDevice_t *deviceArray); + +/** + * Retrieve the status for a given p2p capability index between a given pair of GPU + * + * @param device1 The first device + * @param device2 The second device + * @param p2pIndex p2p Capability Index being looked for between \a device1 and \a device2 + * @param p2pStatus Reference in which to return the status of the \a p2pIndex + * between \a device1 and \a device2 + * @return + * - \ref NVML_SUCCESS if \a p2pStatus has been populated + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device1 or \a device2 or \a p2pIndex is invalid or \a p2pStatus is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetP2PStatus(nvmlDevice_t device1, nvmlDevice_t device2, nvmlGpuP2PCapsIndex_t p2pIndex,nvmlGpuP2PStatus_t *p2pStatus); + +/** + * Retrieves the globally unique immutable UUID associated with this device, as a 5 part hexadecimal string, + * that augments the immutable, board serial identifier. + * + * For all products. + * + * The UUID is a globally unique identifier. It is the only available identifier for pre-Fermi-architecture products. + * It does NOT correspond to any identifier printed on the board. It will not exceed 96 characters in length + * (including the NULL terminator). See \ref nvmlConstants::NVML_DEVICE_UUID_V2_BUFFER_SIZE. + * + * When used with MIG device handles the API returns globally unique UUIDs which can be used to identify MIG + * devices across both GPU and MIG devices. UUIDs are immutable for the lifetime of a MIG device. + * + * @param device The identifier of the target device + * @param uuid Reference in which to return the GPU UUID + * @param length The maximum allowed length of the string returned in \a uuid + * + * @return + * - \ref NVML_SUCCESS if \a uuid has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a uuid is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a length is too small + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetUUID(nvmlDevice_t device, char *uuid, unsigned int length); + +/** + * Retrieve the MDEV UUID of a vGPU instance. + * + * The MDEV UUID is a globally unique identifier of the mdev device assigned to the VM, and is returned as a 5-part hexadecimal string, + * not exceeding 80 characters in length (including the NULL terminator). + * MDEV UUID is displayed only on KVM platform. + * See \ref nvmlConstants::NVML_DEVICE_UUID_BUFFER_SIZE. + * + * For Maxwell &tm; or newer fully supported devices. + * + * @param vgpuInstance Identifier of the target vGPU instance + * @param mdevUuid Pointer to caller-supplied buffer to hold MDEV UUID + * @param size Size of buffer in bytes + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_NOT_SUPPORTED on any hypervisor other than KVM + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a mdevUuid is NULL + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a size is too small + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetMdevUUID(nvmlVgpuInstance_t vgpuInstance, char *mdevUuid, unsigned int size); + +/** + * Retrieves minor number for the device. The minor number for the device is such that the Nvidia device node file for + * each GPU will have the form /dev/nvidia[minor number]. + * + * For all products. + * Supported only for Linux + * + * @param device The identifier of the target device + * @param minorNumber Reference in which to return the minor number for the device + * @return + * - \ref NVML_SUCCESS if the minor number is successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a minorNumber is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMinorNumber(nvmlDevice_t device, unsigned int *minorNumber); + +/** + * Retrieves the the device board part number which is programmed into the board's InfoROM + * + * For all products. + * + * @param device Identifier of the target device + * @param partNumber Reference to the buffer to return + * @param length Length of the buffer reference + * + * @return + * - \ref NVML_SUCCESS if \a partNumber has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_NOT_SUPPORTED if the needed VBIOS fields have not been filled + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a serial is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetBoardPartNumber(nvmlDevice_t device, char* partNumber, unsigned int length); + +/** + * Retrieves the version information for the device's infoROM object. + * + * For all products with an inforom. + * + * Fermi and higher parts have non-volatile on-board memory for persisting device info, such as aggregate + * ECC counts. The version of the data structures in this memory may change from time to time. It will not + * exceed 16 characters in length (including the NULL terminator). + * See \ref nvmlConstants::NVML_DEVICE_INFOROM_VERSION_BUFFER_SIZE. + * + * See \ref nvmlInforomObject_t for details on the available infoROM objects. + * + * @param device The identifier of the target device + * @param object The target infoROM object + * @param version Reference in which to return the infoROM version + * @param length The maximum allowed length of the string returned in \a version + * + * @return + * - \ref NVML_SUCCESS if \a version has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a version is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a length is too small + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not have an infoROM + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetInforomImageVersion + */ +nvmlReturn_t DECLDIR nvmlDeviceGetInforomVersion(nvmlDevice_t device, nvmlInforomObject_t object, char *version, unsigned int length); + +/** + * Retrieves the global infoROM image version + * + * For all products with an inforom. + * + * Image version just like VBIOS version uniquely describes the exact version of the infoROM flashed on the board + * in contrast to infoROM object version which is only an indicator of supported features. + * Version string will not exceed 16 characters in length (including the NULL terminator). + * See \ref nvmlConstants::NVML_DEVICE_INFOROM_VERSION_BUFFER_SIZE. + * + * @param device The identifier of the target device + * @param version Reference in which to return the infoROM image version + * @param length The maximum allowed length of the string returned in \a version + * + * @return + * - \ref NVML_SUCCESS if \a version has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a version is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a length is too small + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not have an infoROM + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetInforomVersion + */ +nvmlReturn_t DECLDIR nvmlDeviceGetInforomImageVersion(nvmlDevice_t device, char *version, unsigned int length); + +/** + * Retrieves the checksum of the configuration stored in the device's infoROM. + * + * For all products with an inforom. + * + * Can be used to make sure that two GPUs have the exact same configuration. + * Current checksum takes into account configuration stored in PWR and ECC infoROM objects. + * Checksum can change between driver releases or when user changes configuration (e.g. disable/enable ECC) + * + * @param device The identifier of the target device + * @param checksum Reference in which to return the infoROM configuration checksum + * + * @return + * - \ref NVML_SUCCESS if \a checksum has been set + * - \ref NVML_ERROR_CORRUPTED_INFOROM if the device's checksum couldn't be retrieved due to infoROM corruption + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a checksum is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetInforomConfigurationChecksum(nvmlDevice_t device, unsigned int *checksum); + +/** + * Reads the infoROM from the flash and verifies the checksums. + * + * For all products with an inforom. + * + * @param device The identifier of the target device + * + * @return + * - \ref NVML_SUCCESS if infoROM is not corrupted + * - \ref NVML_ERROR_CORRUPTED_INFOROM if the device's infoROM is corrupted + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceValidateInforom(nvmlDevice_t device); + +/** + * Retrieves the display mode for the device. + * + * For all products. + * + * This method indicates whether a physical display (e.g. monitor) is currently connected to + * any of the device's connectors. + * + * See \ref nvmlEnableState_t for details on allowed modes. + * + * @param device The identifier of the target device + * @param display Reference in which to return the display mode + * + * @return + * - \ref NVML_SUCCESS if \a display has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a display is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetDisplayMode(nvmlDevice_t device, nvmlEnableState_t *display); + +/** + * Retrieves the display active state for the device. + * + * For all products. + * + * This method indicates whether a display is initialized on the device. + * For example whether X Server is attached to this device and has allocated memory for the screen. + * + * Display can be active even when no monitor is physically attached. + * + * See \ref nvmlEnableState_t for details on allowed modes. + * + * @param device The identifier of the target device + * @param isActive Reference in which to return the display active state + * + * @return + * - \ref NVML_SUCCESS if \a isActive has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a isActive is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetDisplayActive(nvmlDevice_t device, nvmlEnableState_t *isActive); + +/** + * Retrieves the persistence mode associated with this device. + * + * For all products. + * For Linux only. + * + * When driver persistence mode is enabled the driver software state is not torn down when the last + * client disconnects. By default this feature is disabled. + * + * See \ref nvmlEnableState_t for details on allowed modes. + * + * @param device The identifier of the target device + * @param mode Reference in which to return the current driver persistence mode + * + * @return + * - \ref NVML_SUCCESS if \a mode has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a mode is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceSetPersistenceMode() + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPersistenceMode(nvmlDevice_t device, nvmlEnableState_t *mode); + +/** + * Retrieves the PCI attributes of this device. + * + * For all products. + * + * See \ref nvmlPciInfo_t for details on the available PCI info. + * + * @param device The identifier of the target device + * @param pci Reference in which to return the PCI info + * + * @return + * - \ref NVML_SUCCESS if \a pci has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a pci is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPciInfo_v3(nvmlDevice_t device, nvmlPciInfo_t *pci); + +/** + * Retrieves the maximum PCIe link generation possible with this device and system + * + * I.E. for a generation 2 PCIe device attached to a generation 1 PCIe bus the max link generation this function will + * report is generation 1. + * + * For Fermi &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param maxLinkGen Reference in which to return the max PCIe link generation + * + * @return + * - \ref NVML_SUCCESS if \a maxLinkGen has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a maxLinkGen is null + * - \ref NVML_ERROR_NOT_SUPPORTED if PCIe link information is not available + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMaxPcieLinkGeneration(nvmlDevice_t device, unsigned int *maxLinkGen); + +/** + * Retrieves the maximum PCIe link generation supported by this device + * + * For Fermi &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param maxLinkGenDevice Reference in which to return the max PCIe link generation + * + * @return + * - \ref NVML_SUCCESS if \a maxLinkGenDevice has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a maxLinkGenDevice is null + * - \ref NVML_ERROR_NOT_SUPPORTED if PCIe link information is not available + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGpuMaxPcieLinkGeneration(nvmlDevice_t device, unsigned int *maxLinkGenDevice); + +/** + * Retrieves the maximum PCIe link width possible with this device and system + * + * I.E. for a device with a 16x PCIe bus width attached to a 8x PCIe system bus this function will report + * a max link width of 8. + * + * For Fermi &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param maxLinkWidth Reference in which to return the max PCIe link generation + * + * @return + * - \ref NVML_SUCCESS if \a maxLinkWidth has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a maxLinkWidth is null + * - \ref NVML_ERROR_NOT_SUPPORTED if PCIe link information is not available + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMaxPcieLinkWidth(nvmlDevice_t device, unsigned int *maxLinkWidth); + +/** + * Retrieves the current PCIe link generation + * + * For Fermi &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param currLinkGen Reference in which to return the current PCIe link generation + * + * @return + * - \ref NVML_SUCCESS if \a currLinkGen has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a currLinkGen is null + * - \ref NVML_ERROR_NOT_SUPPORTED if PCIe link information is not available + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetCurrPcieLinkGeneration(nvmlDevice_t device, unsigned int *currLinkGen); + +/** + * Retrieves the current PCIe link width + * + * For Fermi &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param currLinkWidth Reference in which to return the current PCIe link generation + * + * @return + * - \ref NVML_SUCCESS if \a currLinkWidth has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a currLinkWidth is null + * - \ref NVML_ERROR_NOT_SUPPORTED if PCIe link information is not available + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetCurrPcieLinkWidth(nvmlDevice_t device, unsigned int *currLinkWidth); + +/** + * Retrieve PCIe utilization information. + * This function is querying a byte counter over a 20ms interval and thus is the + * PCIe throughput over that interval. + * + * For Maxwell &tm; or newer fully supported devices. + * + * This method is not supported in virtual machines running virtual GPU (vGPU). + * + * @param device The identifier of the target device + * @param counter The specific counter that should be queried \ref nvmlPcieUtilCounter_t + * @param value Reference in which to return throughput in KB/s + * + * @return + * - \ref NVML_SUCCESS if \a value has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device or \a counter is invalid, or \a value is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPcieThroughput(nvmlDevice_t device, nvmlPcieUtilCounter_t counter, unsigned int *value); + +/** + * Retrieve the PCIe replay counter. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param value Reference in which to return the counter's value + * + * @return + * - \ref NVML_SUCCESS if \a value has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a value is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPcieReplayCounter(nvmlDevice_t device, unsigned int *value); + +/** + * Retrieves the current clock speeds for the device. + * + * For Fermi &tm; or newer fully supported devices. + * + * See \ref nvmlClockType_t for details on available clock information. + * + * @param device The identifier of the target device + * @param type Identify which clock domain to query + * @param clock Reference in which to return the clock speed in MHz + * + * @return + * - \ref NVML_SUCCESS if \a clock has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a clock is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device cannot report the specified clock + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetClockInfo(nvmlDevice_t device, nvmlClockType_t type, unsigned int *clock); + +/** + * Retrieves the maximum clock speeds for the device. + * + * For Fermi &tm; or newer fully supported devices. + * + * See \ref nvmlClockType_t for details on available clock information. + * + * \note On GPUs from Fermi family current P0 clocks (reported by \ref nvmlDeviceGetClockInfo) can differ from max clocks + * by few MHz. + * + * @param device The identifier of the target device + * @param type Identify which clock domain to query + * @param clock Reference in which to return the clock speed in MHz + * + * @return + * - \ref NVML_SUCCESS if \a clock has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a clock is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device cannot report the specified clock + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMaxClockInfo(nvmlDevice_t device, nvmlClockType_t type, unsigned int *clock); + +/** + * Retrieves the current setting of a clock that applications will use unless an overspec situation occurs. + * Can be changed using \ref nvmlDeviceSetApplicationsClocks. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param clockType Identify which clock domain to query + * @param clockMHz Reference in which to return the clock in MHz + * + * @return + * - \ref NVML_SUCCESS if \a clockMHz has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a clockMHz is NULL or \a clockType is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetApplicationsClock(nvmlDevice_t device, nvmlClockType_t clockType, unsigned int *clockMHz); + +/** + * Retrieves the default applications clock that GPU boots with or + * defaults to after \ref nvmlDeviceResetApplicationsClocks call. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param clockType Identify which clock domain to query + * @param clockMHz Reference in which to return the default clock in MHz + * + * @return + * - \ref NVML_SUCCESS if \a clockMHz has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a clockMHz is NULL or \a clockType is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * \see nvmlDeviceGetApplicationsClock + */ +nvmlReturn_t DECLDIR nvmlDeviceGetDefaultApplicationsClock(nvmlDevice_t device, nvmlClockType_t clockType, unsigned int *clockMHz); + +/** + * Resets the application clock to the default value + * + * This is the applications clock that will be used after system reboot or driver reload. + * Default value is constant, but the current value an be changed using \ref nvmlDeviceSetApplicationsClocks. + * + * On Pascal and newer hardware, if clocks were previously locked with \ref nvmlDeviceSetApplicationsClocks, + * this call will unlock clocks. This returns clocks their default behavior ofautomatically boosting above + * base clocks as thermal limits allow. + * + * @see nvmlDeviceGetApplicationsClock + * @see nvmlDeviceSetApplicationsClocks + * + * For Fermi &tm; or newer non-GeForce fully supported devices and Maxwell or newer GeForce devices. + * + * @param device The identifier of the target device + * + * @return + * - \ref NVML_SUCCESS if new settings were successfully set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceResetApplicationsClocks(nvmlDevice_t device); + +/** + * Retrieves the clock speed for the clock specified by the clock type and clock ID. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param clockType Identify which clock domain to query + * @param clockId Identify which clock in the domain to query + * @param clockMHz Reference in which to return the clock in MHz + * + * @return + * - \ref NVML_SUCCESS if \a clockMHz has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a clockMHz is NULL or \a clockType is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetClock(nvmlDevice_t device, nvmlClockType_t clockType, nvmlClockId_t clockId, unsigned int *clockMHz); + +/** + * Retrieves the customer defined maximum boost clock speed specified by the given clock type. + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param clockType Identify which clock domain to query + * @param clockMHz Reference in which to return the clock in MHz + * + * @return + * - \ref NVML_SUCCESS if \a clockMHz has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a clockMHz is NULL or \a clockType is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device or the \a clockType on this device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMaxCustomerBoostClock(nvmlDevice_t device, nvmlClockType_t clockType, unsigned int *clockMHz); + +/** + * Retrieves the list of possible memory clocks that can be used as an argument for \ref nvmlDeviceSetApplicationsClocks. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param count Reference in which to provide the \a clocksMHz array size, and + * to return the number of elements + * @param clocksMHz Reference in which to return the clock in MHz + * + * @return + * - \ref NVML_SUCCESS if \a count and \a clocksMHz have been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a count is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a count is too small (\a count is set to the number of + * required elements) + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceSetApplicationsClocks + * @see nvmlDeviceGetSupportedGraphicsClocks + */ +nvmlReturn_t DECLDIR nvmlDeviceGetSupportedMemoryClocks(nvmlDevice_t device, unsigned int *count, unsigned int *clocksMHz); + +/** + * Retrieves the list of possible graphics clocks that can be used as an argument for \ref nvmlDeviceSetApplicationsClocks. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param memoryClockMHz Memory clock for which to return possible graphics clocks + * @param count Reference in which to provide the \a clocksMHz array size, and + * to return the number of elements + * @param clocksMHz Reference in which to return the clocks in MHz + * + * @return + * - \ref NVML_SUCCESS if \a count and \a clocksMHz have been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_NOT_FOUND if the specified \a memoryClockMHz is not a supported frequency + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a clock is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a count is too small + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceSetApplicationsClocks + * @see nvmlDeviceGetSupportedMemoryClocks + */ +nvmlReturn_t DECLDIR nvmlDeviceGetSupportedGraphicsClocks(nvmlDevice_t device, unsigned int memoryClockMHz, unsigned int *count, unsigned int *clocksMHz); + +/** + * Retrieve the current state of Auto Boosted clocks on a device and store it in \a isEnabled + * + * For Kepler &tm; or newer fully supported devices. + * + * Auto Boosted clocks are enabled by default on some hardware, allowing the GPU to run at higher clock rates + * to maximize performance as thermal limits allow. + * + * On Pascal and newer hardware, Auto Aoosted clocks are controlled through application clocks. + * Use \ref nvmlDeviceSetApplicationsClocks and \ref nvmlDeviceResetApplicationsClocks to control Auto Boost + * behavior. + * + * @param device The identifier of the target device + * @param isEnabled Where to store the current state of Auto Boosted clocks of the target device + * @param defaultIsEnabled Where to store the default Auto Boosted clocks behavior of the target device that the device will + * revert to when no applications are using the GPU + * + * @return + * - \ref NVML_SUCCESS If \a isEnabled has been been set with the Auto Boosted clocks state of \a device + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a isEnabled is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support Auto Boosted clocks + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + */ +nvmlReturn_t DECLDIR nvmlDeviceGetAutoBoostedClocksEnabled(nvmlDevice_t device, nvmlEnableState_t *isEnabled, nvmlEnableState_t *defaultIsEnabled); + +/** + * Try to set the current state of Auto Boosted clocks on a device. + * + * For Kepler &tm; or newer fully supported devices. + * + * Auto Boosted clocks are enabled by default on some hardware, allowing the GPU to run at higher clock rates + * to maximize performance as thermal limits allow. Auto Boosted clocks should be disabled if fixed clock + * rates are desired. + * + * Non-root users may use this API by default but can be restricted by root from using this API by calling + * \ref nvmlDeviceSetAPIRestriction with apiType=NVML_RESTRICTED_API_SET_AUTO_BOOSTED_CLOCKS. + * Note: Persistence Mode is required to modify current Auto Boost settings, therefore, it must be enabled. + * + * On Pascal and newer hardware, Auto Boosted clocks are controlled through application clocks. + * Use \ref nvmlDeviceSetApplicationsClocks and \ref nvmlDeviceResetApplicationsClocks to control Auto Boost + * behavior. + * + * @param device The identifier of the target device + * @param enabled What state to try to set Auto Boosted clocks of the target device to + * + * @return + * - \ref NVML_SUCCESS If the Auto Boosted clocks were successfully set to the state specified by \a enabled + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support Auto Boosted clocks + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + */ +nvmlReturn_t DECLDIR nvmlDeviceSetAutoBoostedClocksEnabled(nvmlDevice_t device, nvmlEnableState_t enabled); + +/** + * Try to set the default state of Auto Boosted clocks on a device. This is the default state that Auto Boosted clocks will + * return to when no compute running processes (e.g. CUDA application which have an active context) are running + * + * For Kepler &tm; or newer non-GeForce fully supported devices and Maxwell or newer GeForce devices. + * Requires root/admin permissions. + * + * Auto Boosted clocks are enabled by default on some hardware, allowing the GPU to run at higher clock rates + * to maximize performance as thermal limits allow. Auto Boosted clocks should be disabled if fixed clock + * rates are desired. + * + * On Pascal and newer hardware, Auto Boosted clocks are controlled through application clocks. + * Use \ref nvmlDeviceSetApplicationsClocks and \ref nvmlDeviceResetApplicationsClocks to control Auto Boost + * behavior. + * + * @param device The identifier of the target device + * @param enabled What state to try to set default Auto Boosted clocks of the target device to + * @param flags Flags that change the default behavior. Currently Unused. + * + * @return + * - \ref NVML_SUCCESS If the Auto Boosted clock's default state was successfully set to the state specified by \a enabled + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_NO_PERMISSION If the calling user does not have permission to change Auto Boosted clock's default state. + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support Auto Boosted clocks + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + */ +nvmlReturn_t DECLDIR nvmlDeviceSetDefaultAutoBoostedClocksEnabled(nvmlDevice_t device, nvmlEnableState_t enabled, unsigned int flags); + + +/** + * Retrieves the intended operating speed of the device's fan. + * + * Note: The reported speed is the intended fan speed. If the fan is physically blocked and unable to spin, the + * output will not match the actual fan speed. + * + * For all discrete products with dedicated fans. + * + * The fan speed is expressed as a percentage of the product's maximum noise tolerance fan speed. + * This value may exceed 100% in certain cases. + * + * @param device The identifier of the target device + * @param speed Reference in which to return the fan speed percentage + * + * @return + * - \ref NVML_SUCCESS if \a speed has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a speed is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not have a fan + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetFanSpeed(nvmlDevice_t device, unsigned int *speed); + + +/** + * Retrieves the intended operating speed of the device's specified fan. + * + * Note: The reported speed is the intended fan speed. If the fan is physically blocked and unable to spin, the + * output will not match the actual fan speed. + * + * For all discrete products with dedicated fans. + * + * The fan speed is expressed as a percentage of the product's maximum noise tolerance fan speed. + * This value may exceed 100% in certain cases. + * + * @param device The identifier of the target device + * @param fan The index of the target fan, zero indexed. + * @param speed Reference in which to return the fan speed percentage + * + * @return + * - \ref NVML_SUCCESS if \a speed has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a fan is not an acceptable index, or \a speed is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not have a fan or is newer than Maxwell + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetFanSpeed_v2(nvmlDevice_t device, unsigned int fan, unsigned int * speed); + +/** + * Retrieves the intended target speed of the device's specified fan. + * + * Normally, the driver dynamically adjusts the fan based on + * the needs of the GPU. But when user set fan speed using nvmlDeviceSetFanSpeed_v2, + * the driver will attempt to make the fan achieve the setting in + * nvmlDeviceSetFanSpeed_v2. The actual current speed of the fan + * is reported in nvmlDeviceGetFanSpeed_v2. + * + * For all discrete products with dedicated fans. + * + * The fan speed is expressed as a percentage of the product's maximum noise tolerance fan speed. + * This value may exceed 100% in certain cases. + * + * @param device The identifier of the target device + * @param fan The index of the target fan, zero indexed. + * @param targetSpeed Reference in which to return the fan speed percentage + * + * @return + * - \ref NVML_SUCCESS if \a speed has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a fan is not an acceptable index, or \a speed is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not have a fan or is newer than Maxwell + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetTargetFanSpeed(nvmlDevice_t device, unsigned int fan, unsigned int *targetSpeed); + +/** + * Sets the speed of the fan control policy to default. + * + * For all cuda-capable discrete products with fans + * + * @param device The identifier of the target device + * @param fan The index of the fan, starting at zero + * + * return + * NVML_SUCCESS if speed has been adjusted + * NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * NVML_ERROR_INVALID_ARGUMENT if device is invalid + * NVML_ERROR_NOT_SUPPORTED if the device does not support this + * (doesn't have fans) + * NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceSetDefaultFanSpeed_v2(nvmlDevice_t device, unsigned int fan); + +/** + * Retrieves the min and max fan speed that user can set for the GPU fan. + * + * For all cuda-capable discrete products with fans + * + * @param device The identifier of the target device + * @param minSpeed The minimum speed allowed to set + * @param maxSpeed The maximum speed allowed to set + * + * return + * NVML_SUCCESS if speed has been adjusted + * NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * NVML_ERROR_INVALID_ARGUMENT if device is invalid + * NVML_ERROR_NOT_SUPPORTED if the device does not support this + * (doesn't have fans) + * NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMinMaxFanSpeed(nvmlDevice_t device, unsigned int * minSpeed, + unsigned int * maxSpeed); + +/** + * Gets current fan control policy. + * + * For Maxwell &tm; or newer fully supported devices. + * + * For all cuda-capable discrete products with fans + * + * device The identifier of the target \a device + * policy Reference in which to return the fan control \a policy + * + * return + * NVML_SUCCESS if \a policy has been populated + * NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a policy is null or the \a fan given doesn't reference + * a fan that exists. + * NVML_ERROR_NOT_SUPPORTED if the \a device is older than Maxwell + * NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetFanControlPolicy_v2(nvmlDevice_t device, unsigned int fan, + nvmlFanControlPolicy_t *policy); + +/** + * Sets current fan control policy. + * + * For Maxwell &tm; or newer fully supported devices. + * + * Requires privileged user. + * + * For all cuda-capable discrete products with fans + * + * device The identifier of the target \a device + * policy The fan control \a policy to set + * + * return + * NVML_SUCCESS if \a policy has been set + * NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a policy is null or the \a fan given doesn't reference + * a fan that exists. + * NVML_ERROR_NOT_SUPPORTED if the \a device is older than Maxwell + * NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceSetFanControlPolicy(nvmlDevice_t device, unsigned int fan, + nvmlFanControlPolicy_t policy); + +/** + * Retrieves the number of fans on the device. + * + * For all discrete products with dedicated fans. + * + * @param device The identifier of the target device + * @param numFans The number of fans + * + * @return + * - \ref NVML_SUCCESS if \a fan number query was successful + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a numFans is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not have a fan + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetNumFans(nvmlDevice_t device, unsigned int *numFans); + +/** + * Retrieves the current temperature readings for the device, in degrees C. + * + * For all products. + * + * See \ref nvmlTemperatureSensors_t for details on available temperature sensors. + * + * @param device The identifier of the target device + * @param sensorType Flag that indicates which sensor reading to retrieve + * @param temp Reference in which to return the temperature reading + * + * @return + * - \ref NVML_SUCCESS if \a temp has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a sensorType is invalid or \a temp is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not have the specified sensor + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetTemperature(nvmlDevice_t device, nvmlTemperatureSensors_t sensorType, unsigned int *temp); + +/** + * Retrieves the temperature threshold for the GPU with the specified threshold type in degrees C. + * + * For Kepler &tm; or newer fully supported devices. + * + * See \ref nvmlTemperatureThresholds_t for details on available temperature thresholds. + * + * @param device The identifier of the target device + * @param thresholdType The type of threshold value queried + * @param temp Reference in which to return the temperature reading + * @return + * - \ref NVML_SUCCESS if \a temp has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a thresholdType is invalid or \a temp is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not have a temperature sensor or is unsupported + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetTemperatureThreshold(nvmlDevice_t device, nvmlTemperatureThresholds_t thresholdType, unsigned int *temp); + +/** + * Sets the temperature threshold for the GPU with the specified threshold type in degrees C. + * + * For Maxwell &tm; or newer fully supported devices. + * + * See \ref nvmlTemperatureThresholds_t for details on available temperature thresholds. + * + * @param device The identifier of the target device + * @param thresholdType The type of threshold value to be set + * @param temp Reference which hold the value to be set + * @return + * - \ref NVML_SUCCESS if \a temp has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a thresholdType is invalid or \a temp is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not have a temperature sensor or is unsupported + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceSetTemperatureThreshold(nvmlDevice_t device, nvmlTemperatureThresholds_t thresholdType, int *temp); + +/** + * Used to execute a list of thermal system instructions. + * + * @param device The identifier of the target device + * @param sensorIndex The index of the thermal sensor + * @param pThermalSettings Reference in which to return the thermal sensor information + * + * @return + * - \ref NVML_SUCCESS if \a pThermalSettings has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a pThermalSettings is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetThermalSettings(nvmlDevice_t device, unsigned int sensorIndex, nvmlGpuThermalSettings_t *pThermalSettings); + +/** + * Retrieves the current performance state for the device. + * + * For Fermi &tm; or newer fully supported devices. + * + * See \ref nvmlPstates_t for details on allowed performance states. + * + * @param device The identifier of the target device + * @param pState Reference in which to return the performance state reading + * + * @return + * - \ref NVML_SUCCESS if \a pState has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a pState is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPerformanceState(nvmlDevice_t device, nvmlPstates_t *pState); + +/** + * Retrieves current clocks throttling reasons. + * + * For all fully supported products. + * + * \note More than one bit can be enabled at the same time. Multiple reasons can be affecting clocks at once. + * + * @param device The identifier of the target device + * @param clocksThrottleReasons Reference in which to return bitmask of active clocks throttle + * reasons + * + * @return + * - \ref NVML_SUCCESS if \a clocksThrottleReasons has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a clocksThrottleReasons is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlClocksThrottleReasons + * @see nvmlDeviceGetSupportedClocksThrottleReasons + */ +nvmlReturn_t DECLDIR nvmlDeviceGetCurrentClocksThrottleReasons(nvmlDevice_t device, unsigned long long *clocksThrottleReasons); + +/** + * Retrieves bitmask of supported clocks throttle reasons that can be returned by + * \ref nvmlDeviceGetCurrentClocksThrottleReasons + * + * For all fully supported products. + * + * This method is not supported in virtual machines running virtual GPU (vGPU). + * + * @param device The identifier of the target device + * @param supportedClocksThrottleReasons Reference in which to return bitmask of supported + * clocks throttle reasons + * + * @return + * - \ref NVML_SUCCESS if \a supportedClocksThrottleReasons has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a supportedClocksThrottleReasons is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlClocksThrottleReasons + * @see nvmlDeviceGetCurrentClocksThrottleReasons + */ +nvmlReturn_t DECLDIR nvmlDeviceGetSupportedClocksThrottleReasons(nvmlDevice_t device, unsigned long long *supportedClocksThrottleReasons); + +/** + * Deprecated: Use \ref nvmlDeviceGetPerformanceState. This function exposes an incorrect generalization. + * + * Retrieve the current performance state for the device. + * + * For Fermi &tm; or newer fully supported devices. + * + * See \ref nvmlPstates_t for details on allowed performance states. + * + * @param device The identifier of the target device + * @param pState Reference in which to return the performance state reading + * + * @return + * - \ref NVML_SUCCESS if \a pState has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a pState is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPowerState(nvmlDevice_t device, nvmlPstates_t *pState); + +/** + * This API has been deprecated. + * + * Retrieves the power management mode associated with this device. + * + * For products from the Fermi family. + * - Requires \a NVML_INFOROM_POWER version 3.0 or higher. + * + * For from the Kepler or newer families. + * - Does not require \a NVML_INFOROM_POWER object. + * + * This flag indicates whether any power management algorithm is currently active on the device. An + * enabled state does not necessarily mean the device is being actively throttled -- only that + * that the driver will do so if the appropriate conditions are met. + * + * See \ref nvmlEnableState_t for details on allowed modes. + * + * @param device The identifier of the target device + * @param mode Reference in which to return the current power management mode + * + * @return + * - \ref NVML_SUCCESS if \a mode has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a mode is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPowerManagementMode(nvmlDevice_t device, nvmlEnableState_t *mode); + +/** + * Retrieves the power management limit associated with this device. + * + * For Fermi &tm; or newer fully supported devices. + * + * The power limit defines the upper boundary for the card's power draw. If + * the card's total power draw reaches this limit the power management algorithm kicks in. + * + * This reading is only available if power management mode is supported. + * See \ref nvmlDeviceGetPowerManagementMode. + * + * @param device The identifier of the target device + * @param limit Reference in which to return the power management limit in milliwatts + * + * @return + * - \ref NVML_SUCCESS if \a limit has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a limit is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPowerManagementLimit(nvmlDevice_t device, unsigned int *limit); + +/** + * Retrieves information about possible values of power management limits on this device. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param minLimit Reference in which to return the minimum power management limit in milliwatts + * @param maxLimit Reference in which to return the maximum power management limit in milliwatts + * + * @return + * - \ref NVML_SUCCESS if \a minLimit and \a maxLimit have been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a minLimit or \a maxLimit is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceSetPowerManagementLimit + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPowerManagementLimitConstraints(nvmlDevice_t device, unsigned int *minLimit, unsigned int *maxLimit); + +/** + * Retrieves default power management limit on this device, in milliwatts. + * Default power management limit is a power management limit that the device boots with. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param defaultLimit Reference in which to return the default power management limit in milliwatts + * + * @return + * - \ref NVML_SUCCESS if \a defaultLimit has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a defaultLimit is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPowerManagementDefaultLimit(nvmlDevice_t device, unsigned int *defaultLimit); + +/** + * Retrieves power usage for this GPU in milliwatts and its associated circuitry (e.g. memory) + * + * For Fermi &tm; or newer fully supported devices. + * + * On Fermi and Kepler GPUs the reading is accurate to within +/- 5% of current power draw. + * + * It is only available if power management mode is supported. See \ref nvmlDeviceGetPowerManagementMode. + * + * @param device The identifier of the target device + * @param power Reference in which to return the power usage information + * + * @return + * - \ref NVML_SUCCESS if \a power has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a power is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support power readings + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPowerUsage(nvmlDevice_t device, unsigned int *power); + +/** + * Retrieves total energy consumption for this GPU in millijoules (mJ) since the driver was last reloaded + * + * For Volta &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param energy Reference in which to return the energy consumption information + * + * @return + * - \ref NVML_SUCCESS if \a energy has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a energy is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support energy readings + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetTotalEnergyConsumption(nvmlDevice_t device, unsigned long long *energy); + +/** + * Get the effective power limit that the driver enforces after taking into account all limiters + * + * Note: This can be different from the \ref nvmlDeviceGetPowerManagementLimit if other limits are set elsewhere + * This includes the out of band power limit interface + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The device to communicate with + * @param limit Reference in which to return the power management limit in milliwatts + * + * @return + * - \ref NVML_SUCCESS if \a limit has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a limit is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetEnforcedPowerLimit(nvmlDevice_t device, unsigned int *limit); + +/** + * Retrieves the current GOM and pending GOM (the one that GPU will switch to after reboot). + * + * For GK110 M-class and X-class Tesla &tm; products from the Kepler family. + * Modes \ref NVML_GOM_LOW_DP and \ref NVML_GOM_ALL_ON are supported on fully supported GeForce products. + * Not supported on Quadro ® and Tesla &tm; C-class products. + * + * @param device The identifier of the target device + * @param current Reference in which to return the current GOM + * @param pending Reference in which to return the pending GOM + * + * @return + * - \ref NVML_SUCCESS if \a mode has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a current or \a pending is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlGpuOperationMode_t + * @see nvmlDeviceSetGpuOperationMode + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGpuOperationMode(nvmlDevice_t device, nvmlGpuOperationMode_t *current, nvmlGpuOperationMode_t *pending); + +/** + * Retrieves the amount of used, free, reserved and total memory available on the device, in bytes. + * The reserved amount is supported on version 2 only. + * + * For all products. + * + * Enabling ECC reduces the amount of total available memory, due to the extra required parity bits. + * Under WDDM most device memory is allocated and managed on startup by Windows. + * + * Under Linux and Windows TCC, the reported amount of used memory is equal to the sum of memory allocated + * by all active channels on the device. + * + * See \ref nvmlMemory_v2_t for details on available memory info. + * + * @note In MIG mode, if device handle is provided, the API returns aggregate + * information, only if the caller has appropriate privileges. Per-instance + * information can be queried by using specific MIG device handles. + * + * @note nvmlDeviceGetMemoryInfo_v2 adds additional memory information. + * + * @param device The identifier of the target device + * @param memory Reference in which to return the memory information + * + * @return + * - \ref NVML_SUCCESS if \a memory has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a memory is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMemoryInfo(nvmlDevice_t device, nvmlMemory_t *memory); +nvmlReturn_t DECLDIR nvmlDeviceGetMemoryInfo_v2(nvmlDevice_t device, nvmlMemory_v2_t *memory); + +/** + * Retrieves the current compute mode for the device. + * + * For all products. + * + * See \ref nvmlComputeMode_t for details on allowed compute modes. + * + * @param device The identifier of the target device + * @param mode Reference in which to return the current compute mode + * + * @return + * - \ref NVML_SUCCESS if \a mode has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a mode is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceSetComputeMode() + */ +nvmlReturn_t DECLDIR nvmlDeviceGetComputeMode(nvmlDevice_t device, nvmlComputeMode_t *mode); + +/** + * Retrieves the CUDA compute capability of the device. + * + * For all products. + * + * Returns the major and minor compute capability version numbers of the + * device. The major and minor versions are equivalent to the + * CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MINOR and + * CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MAJOR attributes that would be + * returned by CUDA's cuDeviceGetAttribute(). + * + * @param device The identifier of the target device + * @param major Reference in which to return the major CUDA compute capability + * @param minor Reference in which to return the minor CUDA compute capability + * + * @return + * - \ref NVML_SUCCESS if \a major and \a minor have been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a major or \a minor are NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetCudaComputeCapability(nvmlDevice_t device, int *major, int *minor); + +/** + * Retrieves the current and pending ECC modes for the device. + * + * For Fermi &tm; or newer fully supported devices. + * Only applicable to devices with ECC. + * Requires \a NVML_INFOROM_ECC version 1.0 or higher. + * + * Changing ECC modes requires a reboot. The "pending" ECC mode refers to the target mode following + * the next reboot. + * + * See \ref nvmlEnableState_t for details on allowed modes. + * + * @param device The identifier of the target device + * @param current Reference in which to return the current ECC mode + * @param pending Reference in which to return the pending ECC mode + * + * @return + * - \ref NVML_SUCCESS if \a current and \a pending have been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or either \a current or \a pending is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceSetEccMode() + */ +nvmlReturn_t DECLDIR nvmlDeviceGetEccMode(nvmlDevice_t device, nvmlEnableState_t *current, nvmlEnableState_t *pending); + +/** + * Retrieves the default ECC modes for the device. + * + * For Fermi &tm; or newer fully supported devices. + * Only applicable to devices with ECC. + * Requires \a NVML_INFOROM_ECC version 1.0 or higher. + * + * See \ref nvmlEnableState_t for details on allowed modes. + * + * @param device The identifier of the target device + * @param defaultMode Reference in which to return the default ECC mode + * + * @return + * - \ref NVML_SUCCESS if \a current and \a pending have been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a default is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceSetEccMode() + */ +nvmlReturn_t DECLDIR nvmlDeviceGetDefaultEccMode(nvmlDevice_t device, nvmlEnableState_t *defaultMode); + +/** + * Retrieves the device boardId from 0-N. + * Devices with the same boardId indicate GPUs connected to the same PLX. Use in conjunction with + * \ref nvmlDeviceGetMultiGpuBoard() to decide if they are on the same board as well. + * The boardId returned is a unique ID for the current configuration. Uniqueness and ordering across + * reboots and system configurations is not guaranteed (i.e. if a Tesla K40c returns 0x100 and + * the two GPUs on a Tesla K10 in the same system returns 0x200 it is not guaranteed they will + * always return those values but they will always be different from each other). + * + * + * For Fermi &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param boardId Reference in which to return the device's board ID + * + * @return + * - \ref NVML_SUCCESS if \a boardId has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a boardId is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetBoardId(nvmlDevice_t device, unsigned int *boardId); + +/** + * Retrieves whether the device is on a Multi-GPU Board + * Devices that are on multi-GPU boards will set \a multiGpuBool to a non-zero value. + * + * For Fermi &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param multiGpuBool Reference in which to return a zero or non-zero value + * to indicate whether the device is on a multi GPU board + * + * @return + * - \ref NVML_SUCCESS if \a multiGpuBool has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a multiGpuBool is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMultiGpuBoard(nvmlDevice_t device, unsigned int *multiGpuBool); + +/** + * Retrieves the total ECC error counts for the device. + * + * For Fermi &tm; or newer fully supported devices. + * Only applicable to devices with ECC. + * Requires \a NVML_INFOROM_ECC version 1.0 or higher. + * Requires ECC Mode to be enabled. + * + * The total error count is the sum of errors across each of the separate memory systems, i.e. the total set of + * errors across the entire device. + * + * See \ref nvmlMemoryErrorType_t for a description of available error types.\n + * See \ref nvmlEccCounterType_t for a description of available counter types. + * + * @param device The identifier of the target device + * @param errorType Flag that specifies the type of the errors. + * @param counterType Flag that specifies the counter-type of the errors. + * @param eccCounts Reference in which to return the specified ECC errors + * + * @return + * - \ref NVML_SUCCESS if \a eccCounts has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a errorType or \a counterType is invalid, or \a eccCounts is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceClearEccErrorCounts() + */ +nvmlReturn_t DECLDIR nvmlDeviceGetTotalEccErrors(nvmlDevice_t device, nvmlMemoryErrorType_t errorType, nvmlEccCounterType_t counterType, unsigned long long *eccCounts); + +/** + * Retrieves the detailed ECC error counts for the device. + * + * @deprecated This API supports only a fixed set of ECC error locations + * On different GPU architectures different locations are supported + * See \ref nvmlDeviceGetMemoryErrorCounter + * + * For Fermi &tm; or newer fully supported devices. + * Only applicable to devices with ECC. + * Requires \a NVML_INFOROM_ECC version 2.0 or higher to report aggregate location-based ECC counts. + * Requires \a NVML_INFOROM_ECC version 1.0 or higher to report all other ECC counts. + * Requires ECC Mode to be enabled. + * + * Detailed errors provide separate ECC counts for specific parts of the memory system. + * + * Reports zero for unsupported ECC error counters when a subset of ECC error counters are supported. + * + * See \ref nvmlMemoryErrorType_t for a description of available bit types.\n + * See \ref nvmlEccCounterType_t for a description of available counter types.\n + * See \ref nvmlEccErrorCounts_t for a description of provided detailed ECC counts. + * + * @param device The identifier of the target device + * @param errorType Flag that specifies the type of the errors. + * @param counterType Flag that specifies the counter-type of the errors. + * @param eccCounts Reference in which to return the specified ECC errors + * + * @return + * - \ref NVML_SUCCESS if \a eccCounts has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a errorType or \a counterType is invalid, or \a eccCounts is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceClearEccErrorCounts() + */ +nvmlReturn_t DECLDIR nvmlDeviceGetDetailedEccErrors(nvmlDevice_t device, nvmlMemoryErrorType_t errorType, nvmlEccCounterType_t counterType, nvmlEccErrorCounts_t *eccCounts); + +/** + * Retrieves the requested memory error counter for the device. + * + * For Fermi &tm; or newer fully supported devices. + * Requires \a NVML_INFOROM_ECC version 2.0 or higher to report aggregate location-based memory error counts. + * Requires \a NVML_INFOROM_ECC version 1.0 or higher to report all other memory error counts. + * + * Only applicable to devices with ECC. + * + * Requires ECC Mode to be enabled. + * + * @note On MIG-enabled GPUs, per instance information can be queried using specific + * MIG device handles. Per instance information is currently only supported for + * non-DRAM uncorrectable volatile errors. Querying volatile errors using device + * handles is currently not supported. + * + * See \ref nvmlMemoryErrorType_t for a description of available memory error types.\n + * See \ref nvmlEccCounterType_t for a description of available counter types.\n + * See \ref nvmlMemoryLocation_t for a description of available counter locations.\n + * + * @param device The identifier of the target device + * @param errorType Flag that specifies the type of error. + * @param counterType Flag that specifies the counter-type of the errors. + * @param locationType Specifies the location of the counter. + * @param count Reference in which to return the ECC counter + * + * @return + * - \ref NVML_SUCCESS if \a count has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a bitTyp,e \a counterType or \a locationType is + * invalid, or \a count is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support ECC error reporting in the specified memory + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMemoryErrorCounter(nvmlDevice_t device, nvmlMemoryErrorType_t errorType, + nvmlEccCounterType_t counterType, + nvmlMemoryLocation_t locationType, unsigned long long *count); + +/** + * Retrieves the current utilization rates for the device's major subsystems. + * + * For Fermi &tm; or newer fully supported devices. + * + * See \ref nvmlUtilization_t for details on available utilization rates. + * + * \note During driver initialization when ECC is enabled one can see high GPU and Memory Utilization readings. + * This is caused by ECC Memory Scrubbing mechanism that is performed during driver initialization. + * + * @note On MIG-enabled GPUs, querying device utilization rates is not currently supported. + * + * @param device The identifier of the target device + * @param utilization Reference in which to return the utilization information + * + * @return + * - \ref NVML_SUCCESS if \a utilization has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a utilization is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetUtilizationRates(nvmlDevice_t device, nvmlUtilization_t *utilization); + +/** + * Retrieves the current utilization and sampling size in microseconds for the Encoder + * + * For Kepler &tm; or newer fully supported devices. + * + * @note On MIG-enabled GPUs, querying encoder utilization is not currently supported. + * + * @param device The identifier of the target device + * @param utilization Reference to an unsigned int for encoder utilization info + * @param samplingPeriodUs Reference to an unsigned int for the sampling period in US + * + * @return + * - \ref NVML_SUCCESS if \a utilization has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a utilization is NULL, or \a samplingPeriodUs is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetEncoderUtilization(nvmlDevice_t device, unsigned int *utilization, unsigned int *samplingPeriodUs); + +/** + * Retrieves the current capacity of the device's encoder, as a percentage of maximum encoder capacity with valid values in the range 0-100. + * + * For Maxwell &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param encoderQueryType Type of encoder to query + * @param encoderCapacity Reference to an unsigned int for the encoder capacity + * + * @return + * - \ref NVML_SUCCESS if \a encoderCapacity is fetched + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a encoderCapacity is NULL, or \a device or \a encoderQueryType + * are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if device does not support the encoder specified in \a encodeQueryType + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetEncoderCapacity (nvmlDevice_t device, nvmlEncoderType_t encoderQueryType, unsigned int *encoderCapacity); + +/** + * Retrieves the current encoder statistics for a given device. + * + * For Maxwell &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param sessionCount Reference to an unsigned int for count of active encoder sessions + * @param averageFps Reference to an unsigned int for trailing average FPS of all active sessions + * @param averageLatency Reference to an unsigned int for encode latency in microseconds + * + * @return + * - \ref NVML_SUCCESS if \a sessionCount, \a averageFps and \a averageLatency is fetched + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a sessionCount, or \a device or \a averageFps, + * or \a averageLatency is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetEncoderStats (nvmlDevice_t device, unsigned int *sessionCount, + unsigned int *averageFps, unsigned int *averageLatency); + +/** + * Retrieves information about active encoder sessions on a target device. + * + * An array of active encoder sessions is returned in the caller-supplied buffer pointed at by \a sessionInfos. The + * array elememt count is passed in \a sessionCount, and \a sessionCount is used to return the number of sessions + * written to the buffer. + * + * If the supplied buffer is not large enough to accomodate the active session array, the function returns + * NVML_ERROR_INSUFFICIENT_SIZE, with the element count of nvmlEncoderSessionInfo_t array required in \a sessionCount. + * To query the number of active encoder sessions, call this function with *sessionCount = 0. The code will return + * NVML_SUCCESS with number of active encoder sessions updated in *sessionCount. + * + * For Maxwell &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param sessionCount Reference to caller supplied array size, and returns the number of sessions. + * @param sessionInfos Reference in which to return the session information + * + * @return + * - \ref NVML_SUCCESS if \a sessionInfos is fetched + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a sessionCount is too small, array element count is returned in \a sessionCount + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a sessionCount is NULL. + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by \a device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetEncoderSessions(nvmlDevice_t device, unsigned int *sessionCount, nvmlEncoderSessionInfo_t *sessionInfos); + +/** + * Retrieves the current utilization and sampling size in microseconds for the Decoder + * + * For Kepler &tm; or newer fully supported devices. + * + * @note On MIG-enabled GPUs, querying decoder utilization is not currently supported. + * + * @param device The identifier of the target device + * @param utilization Reference to an unsigned int for decoder utilization info + * @param samplingPeriodUs Reference to an unsigned int for the sampling period in US + * + * @return + * - \ref NVML_SUCCESS if \a utilization has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a utilization is NULL, or \a samplingPeriodUs is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetDecoderUtilization(nvmlDevice_t device, unsigned int *utilization, unsigned int *samplingPeriodUs); + +/** +* Retrieves the active frame buffer capture sessions statistics for a given device. +* +* For Maxwell &tm; or newer fully supported devices. +* +* @param device The identifier of the target device +* @param fbcStats Reference to nvmlFBCStats_t structure contianing NvFBC stats +* +* @return +* - \ref NVML_SUCCESS if \a fbcStats is fetched +* - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized +* - \ref NVML_ERROR_INVALID_ARGUMENT if \a fbcStats is NULL +* - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible +* - \ref NVML_ERROR_UNKNOWN on any unexpected error +*/ +nvmlReturn_t DECLDIR nvmlDeviceGetFBCStats(nvmlDevice_t device, nvmlFBCStats_t *fbcStats); + +/** +* Retrieves information about active frame buffer capture sessions on a target device. +* +* An array of active FBC sessions is returned in the caller-supplied buffer pointed at by \a sessionInfo. The +* array element count is passed in \a sessionCount, and \a sessionCount is used to return the number of sessions +* written to the buffer. +* +* If the supplied buffer is not large enough to accomodate the active session array, the function returns +* NVML_ERROR_INSUFFICIENT_SIZE, with the element count of nvmlFBCSessionInfo_t array required in \a sessionCount. +* To query the number of active FBC sessions, call this function with *sessionCount = 0. The code will return +* NVML_SUCCESS with number of active FBC sessions updated in *sessionCount. +* +* For Maxwell &tm; or newer fully supported devices. +* +* @note hResolution, vResolution, averageFPS and averageLatency data for a FBC session returned in \a sessionInfo may +* be zero if there are no new frames captured since the session started. +* +* @param device The identifier of the target device +* @param sessionCount Reference to caller supplied array size, and returns the number of sessions. +* @param sessionInfo Reference in which to return the session information +* +* @return +* - \ref NVML_SUCCESS if \a sessionInfo is fetched +* - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized +* - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a sessionCount is too small, array element count is returned in \a sessionCount +* - \ref NVML_ERROR_INVALID_ARGUMENT if \a sessionCount is NULL. +* - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible +* - \ref NVML_ERROR_UNKNOWN on any unexpected error +*/ +nvmlReturn_t DECLDIR nvmlDeviceGetFBCSessions(nvmlDevice_t device, unsigned int *sessionCount, nvmlFBCSessionInfo_t *sessionInfo); + +/** + * Retrieves the current and pending driver model for the device. + * + * For Fermi &tm; or newer fully supported devices. + * For windows only. + * + * On Windows platforms the device driver can run in either WDDM or WDM (TCC) mode. If a display is attached + * to the device it must run in WDDM mode. TCC mode is preferred if a display is not attached. + * + * See \ref nvmlDriverModel_t for details on available driver models. + * + * @param device The identifier of the target device + * @param current Reference in which to return the current driver model + * @param pending Reference in which to return the pending driver model + * + * @return + * - \ref NVML_SUCCESS if either \a current and/or \a pending have been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or both \a current and \a pending are NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the platform is not windows + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceSetDriverModel() + */ +nvmlReturn_t DECLDIR nvmlDeviceGetDriverModel(nvmlDevice_t device, nvmlDriverModel_t *current, nvmlDriverModel_t *pending); + +/** + * Get VBIOS version of the device. + * + * For all products. + * + * The VBIOS version may change from time to time. It will not exceed 32 characters in length + * (including the NULL terminator). See \ref nvmlConstants::NVML_DEVICE_VBIOS_VERSION_BUFFER_SIZE. + * + * @param device The identifier of the target device + * @param version Reference to which to return the VBIOS version + * @param length The maximum allowed length of the string returned in \a version + * + * @return + * - \ref NVML_SUCCESS if \a version has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a version is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a length is too small + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetVbiosVersion(nvmlDevice_t device, char *version, unsigned int length); + +/** + * Get Bridge Chip Information for all the bridge chips on the board. + * + * For all fully supported products. + * Only applicable to multi-GPU products. + * + * @param device The identifier of the target device + * @param bridgeHierarchy Reference to the returned bridge chip Hierarchy + * + * @return + * - \ref NVML_SUCCESS if bridge chip exists + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a bridgeInfo is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if bridge chip not supported on the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + */ +nvmlReturn_t DECLDIR nvmlDeviceGetBridgeChipInfo(nvmlDevice_t device, nvmlBridgeChipHierarchy_t *bridgeHierarchy); + +/** + * Get information about processes with a compute context on a device + * + * For Fermi &tm; or newer fully supported devices. + * + * This function returns information only about compute running processes (e.g. CUDA application which have + * active context). Any graphics applications (e.g. using OpenGL, DirectX) won't be listed by this function. + * + * To query the current number of running compute processes, call this function with *infoCount = 0. The + * return code will be NVML_ERROR_INSUFFICIENT_SIZE, or NVML_SUCCESS if none are running. For this call + * \a infos is allowed to be NULL. + * + * The usedGpuMemory field returned is all of the memory used by the application. + * + * Keep in mind that information returned by this call is dynamic and the number of elements might change in + * time. Allocate more space for \a infos table in case new compute processes are spawned. + * + * @note In MIG mode, if device handle is provided, the API returns aggregate information, only if + * the caller has appropriate privileges. Per-instance information can be queried by using + * specific MIG device handles. + * Querying per-instance information using MIG device handles is not supported if the device is in vGPU Host virtualization mode. + * + * @param device The device handle or MIG device handle + * @param infoCount Reference in which to provide the \a infos array size, and + * to return the number of returned elements + * @param infos Reference in which to return the process information + * + * @return + * - \ref NVML_SUCCESS if \a infoCount and \a infos have been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a infoCount indicates that the \a infos array is too small + * \a infoCount will contain minimal amount of space necessary for + * the call to complete + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, either of \a infoCount or \a infos is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by \a device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see \ref nvmlSystemGetProcessName + */ +nvmlReturn_t DECLDIR nvmlDeviceGetComputeRunningProcesses_v3(nvmlDevice_t device, unsigned int *infoCount, nvmlProcessInfo_t *infos); + +/** + * Get information about processes with a graphics context on a device + * + * For Kepler &tm; or newer fully supported devices. + * + * This function returns information only about graphics based processes + * (eg. applications using OpenGL, DirectX) + * + * To query the current number of running graphics processes, call this function with *infoCount = 0. The + * return code will be NVML_ERROR_INSUFFICIENT_SIZE, or NVML_SUCCESS if none are running. For this call + * \a infos is allowed to be NULL. + * + * The usedGpuMemory field returned is all of the memory used by the application. + * + * Keep in mind that information returned by this call is dynamic and the number of elements might change in + * time. Allocate more space for \a infos table in case new graphics processes are spawned. + * + * @note In MIG mode, if device handle is provided, the API returns aggregate information, only if + * the caller has appropriate privileges. Per-instance information can be queried by using + * specific MIG device handles. + * Querying per-instance information using MIG device handles is not supported if the device is in vGPU Host virtualization mode. + * + * @param device The device handle or MIG device handle + * @param infoCount Reference in which to provide the \a infos array size, and + * to return the number of returned elements + * @param infos Reference in which to return the process information + * + * @return + * - \ref NVML_SUCCESS if \a infoCount and \a infos have been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a infoCount indicates that the \a infos array is too small + * \a infoCount will contain minimal amount of space necessary for + * the call to complete + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, either of \a infoCount or \a infos is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by \a device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see \ref nvmlSystemGetProcessName + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGraphicsRunningProcesses_v3(nvmlDevice_t device, unsigned int *infoCount, nvmlProcessInfo_t *infos); + +/** + * Get information about processes with a MPS compute context on a device + * + * For Volta &tm; or newer fully supported devices. + * + * This function returns information only about compute running processes (e.g. CUDA application which have + * active context) utilizing MPS. Any graphics applications (e.g. using OpenGL, DirectX) won't be listed by + * this function. + * + * To query the current number of running compute processes, call this function with *infoCount = 0. The + * return code will be NVML_ERROR_INSUFFICIENT_SIZE, or NVML_SUCCESS if none are running. For this call + * \a infos is allowed to be NULL. + * + * The usedGpuMemory field returned is all of the memory used by the application. + * + * Keep in mind that information returned by this call is dynamic and the number of elements might change in + * time. Allocate more space for \a infos table in case new compute processes are spawned. + * + * @note In MIG mode, if device handle is provided, the API returns aggregate information, only if + * the caller has appropriate privileges. Per-instance information can be queried by using + * specific MIG device handles. + * Querying per-instance information using MIG device handles is not supported if the device is in vGPU Host virtualization mode. + * + * @param device The device handle or MIG device handle + * @param infoCount Reference in which to provide the \a infos array size, and + * to return the number of returned elements + * @param infos Reference in which to return the process information + * + * @return + * - \ref NVML_SUCCESS if \a infoCount and \a infos have been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a infoCount indicates that the \a infos array is too small + * \a infoCount will contain minimal amount of space necessary for + * the call to complete + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, either of \a infoCount or \a infos is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by \a device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see \ref nvmlSystemGetProcessName + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMPSComputeRunningProcesses_v3(nvmlDevice_t device, unsigned int *infoCount, nvmlProcessInfo_t *infos); + +/** + * Check if the GPU devices are on the same physical board. + * + * For all fully supported products. + * + * @param device1 The first GPU device + * @param device2 The second GPU device + * @param onSameBoard Reference in which to return the status. + * Non-zero indicates that the GPUs are on the same board. + * + * @return + * - \ref NVML_SUCCESS if \a onSameBoard has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a dev1 or \a dev2 are invalid or \a onSameBoard is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this check is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the either GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceOnSameBoard(nvmlDevice_t device1, nvmlDevice_t device2, int *onSameBoard); + +/** + * Retrieves the root/admin permissions on the target API. See \a nvmlRestrictedAPI_t for the list of supported APIs. + * If an API is restricted only root users can call that API. See \a nvmlDeviceSetAPIRestriction to change current permissions. + * + * For all fully supported products. + * + * @param device The identifier of the target device + * @param apiType Target API type for this operation + * @param isRestricted Reference in which to return the current restriction + * NVML_FEATURE_ENABLED indicates that the API is root-only + * NVML_FEATURE_DISABLED indicates that the API is accessible to all users + * + * @return + * - \ref NVML_SUCCESS if \a isRestricted has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a apiType incorrect or \a isRestricted is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device or the device does not support + * the feature that is being queried (E.G. Enabling/disabling Auto Boosted clocks is + * not supported by the device) + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlRestrictedAPI_t + */ +nvmlReturn_t DECLDIR nvmlDeviceGetAPIRestriction(nvmlDevice_t device, nvmlRestrictedAPI_t apiType, nvmlEnableState_t *isRestricted); + +/** + * Gets recent samples for the GPU. + * + * For Kepler &tm; or newer fully supported devices. + * + * Based on type, this method can be used to fetch the power, utilization or clock samples maintained in the buffer by + * the driver. + * + * Power, Utilization and Clock samples are returned as type "unsigned int" for the union nvmlValue_t. + * + * To get the size of samples that user needs to allocate, the method is invoked with samples set to NULL. + * The returned samplesCount will provide the number of samples that can be queried. The user needs to + * allocate the buffer with size as samplesCount * sizeof(nvmlSample_t). + * + * lastSeenTimeStamp represents CPU timestamp in microseconds. Set it to 0 to fetch all the samples maintained by the + * underlying buffer. Set lastSeenTimeStamp to one of the timeStamps retrieved from the date of the previous query + * to get more recent samples. + * + * This method fetches the number of entries which can be accommodated in the provided samples array, and the + * reference samplesCount is updated to indicate how many samples were actually retrieved. The advantage of using this + * method for samples in contrast to polling via existing methods is to get get higher frequency data at lower polling cost. + * + * @note On MIG-enabled GPUs, querying the following sample types, NVML_GPU_UTILIZATION_SAMPLES, NVML_MEMORY_UTILIZATION_SAMPLES + * NVML_ENC_UTILIZATION_SAMPLES and NVML_DEC_UTILIZATION_SAMPLES, is not currently supported. + * + * @param device The identifier for the target device + * @param type Type of sampling event + * @param lastSeenTimeStamp Return only samples with timestamp greater than lastSeenTimeStamp. + * @param sampleValType Output parameter to represent the type of sample value as described in nvmlSampleVal_t + * @param sampleCount Reference to provide the number of elements which can be queried in samples array + * @param samples Reference in which samples are returned + + * @return + * - \ref NVML_SUCCESS if samples are successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a samplesCount is NULL or + * reference to \a sampleCount is 0 for non null \a samples + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_NOT_FOUND if sample entries are not found + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetSamples(nvmlDevice_t device, nvmlSamplingType_t type, unsigned long long lastSeenTimeStamp, + nvmlValueType_t *sampleValType, unsigned int *sampleCount, nvmlSample_t *samples); + +/** + * Gets Total, Available and Used size of BAR1 memory. + * + * BAR1 is used to map the FB (device memory) so that it can be directly accessed by the CPU or by 3rd party + * devices (peer-to-peer on the PCIE bus). + * + * @note In MIG mode, if device handle is provided, the API returns aggregate + * information, only if the caller has appropriate privileges. Per-instance + * information can be queried by using specific MIG device handles. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param bar1Memory Reference in which BAR1 memory + * information is returned. + * + * @return + * - \ref NVML_SUCCESS if BAR1 memory is successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a bar1Memory is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + */ +nvmlReturn_t DECLDIR nvmlDeviceGetBAR1MemoryInfo(nvmlDevice_t device, nvmlBAR1Memory_t *bar1Memory); + +/** + * Gets the duration of time during which the device was throttled (lower than requested clocks) due to power + * or thermal constraints. + * + * The method is important to users who are tying to understand if their GPUs throttle at any point during their applications. The + * difference in violation times at two different reference times gives the indication of GPU throttling event. + * + * Violation for thermal capping is not supported at this time. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param perfPolicyType Represents Performance policy which can trigger GPU throttling + * @param violTime Reference to which violation time related information is returned + * + * + * @return + * - \ref NVML_SUCCESS if violation time is successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a perfPolicyType is invalid, or \a violTime is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * + */ +nvmlReturn_t DECLDIR nvmlDeviceGetViolationStatus(nvmlDevice_t device, nvmlPerfPolicyType_t perfPolicyType, nvmlViolationTime_t *violTime); + +/** + * Gets the device's interrupt number + * + * @param device The identifier of the target device + * @param irqNum The interrupt number associated with the specified device + * + * @return + * - \ref NVML_SUCCESS if irq number is successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a irqNum is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * + */ +nvmlReturn_t DECLDIR nvmlDeviceGetIrqNum(nvmlDevice_t device, unsigned int *irqNum); + +/** + * Gets the device's core count + * + * @param device The identifier of the target device + * @param numCores The number of cores for the specified device + * + * @return + * - \ref NVML_SUCCESS if Gpu core count is successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a numCores is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * + */ +nvmlReturn_t DECLDIR nvmlDeviceGetNumGpuCores(nvmlDevice_t device, unsigned int *numCores); + +/** + * Gets the devices power source + * + * @param device The identifier of the target device + * @param powerSource The power source of the device + * + * @return + * - \ref NVML_SUCCESS if the current power source was successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a powerSource is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPowerSource(nvmlDevice_t device, nvmlPowerSource_t *powerSource); + +/** + * Gets the device's memory bus width + * + * @param device The identifier of the target device + * @param busWidth The devices's memory bus width + * + * @return + * - \ref NVML_SUCCESS if the memory bus width is successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a busWidth is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMemoryBusWidth(nvmlDevice_t device, unsigned int *busWidth); + +/** + * Gets the device's PCIE Max Link speed in MBPS + * + * @param device The identifier of the target device + * @param maxSpeed The devices's PCIE Max Link speed in MBPS + * + * @return + * - \ref NVML_SUCCESS if Pcie Max Link Speed is successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a maxSpeed is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPcieLinkMaxSpeed(nvmlDevice_t device, unsigned int *maxSpeed); + +/** + * Gets the device's PCIe Link speed in Mbps + * + * @param device The identifier of the target device + * @param pcieSpeed The devices's PCIe Max Link speed in Mbps + * + * @return + * - \ref NVML_SUCCESS if \a pcieSpeed has been retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a pcieSpeed is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support PCIe speed getting + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPcieSpeed(nvmlDevice_t device, unsigned int *pcieSpeed); + +/** + * Gets the device's Adaptive Clock status + * + * @param device The identifier of the target device + * @param adaptiveClockStatus The current adaptive clocking status + * + * @return + * - \ref NVML_SUCCESS if the current adaptive clocking status is successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a adaptiveClockStatus is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * + */ +nvmlReturn_t DECLDIR nvmlDeviceGetAdaptiveClockInfoStatus(nvmlDevice_t device, unsigned int *adaptiveClockStatus); + +/** + * @} + */ + +/** @addtogroup nvmlAccountingStats + * @{ + */ + +/** + * Queries the state of per process accounting mode. + * + * For Kepler &tm; or newer fully supported devices. + * + * See \ref nvmlDeviceGetAccountingStats for more details. + * See \ref nvmlDeviceSetAccountingMode + * + * @param device The identifier of the target device + * @param mode Reference in which to return the current accounting mode + * + * @return + * - \ref NVML_SUCCESS if the mode has been successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a mode are NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetAccountingMode(nvmlDevice_t device, nvmlEnableState_t *mode); + +/** + * Queries process's accounting stats. + * + * For Kepler &tm; or newer fully supported devices. + * + * Accounting stats capture GPU utilization and other statistics across the lifetime of a process. + * Accounting stats can be queried during life time of the process and after its termination. + * The time field in \ref nvmlAccountingStats_t is reported as 0 during the lifetime of the process and + * updated to actual running time after its termination. + * Accounting stats are kept in a circular buffer, newly created processes overwrite information about old + * processes. + * + * See \ref nvmlAccountingStats_t for description of each returned metric. + * List of processes that can be queried can be retrieved from \ref nvmlDeviceGetAccountingPids. + * + * @note Accounting Mode needs to be on. See \ref nvmlDeviceGetAccountingMode. + * @note Only compute and graphics applications stats can be queried. Monitoring applications stats can't be + * queried since they don't contribute to GPU utilization. + * @note In case of pid collision stats of only the latest process (that terminated last) will be reported + * + * @warning On Kepler devices per process statistics are accurate only if there's one process running on a GPU. + * + * @param device The identifier of the target device + * @param pid Process Id of the target process to query stats for + * @param stats Reference in which to return the process's accounting stats + * + * @return + * - \ref NVML_SUCCESS if stats have been successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a stats are NULL + * - \ref NVML_ERROR_NOT_FOUND if process stats were not found + * - \ref NVML_ERROR_NOT_SUPPORTED if \a device doesn't support this feature or accounting mode is disabled + * or on vGPU host. + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetAccountingBufferSize + */ +nvmlReturn_t DECLDIR nvmlDeviceGetAccountingStats(nvmlDevice_t device, unsigned int pid, nvmlAccountingStats_t *stats); + +/** + * Queries list of processes that can be queried for accounting stats. The list of processes returned + * can be in running or terminated state. + * + * For Kepler &tm; or newer fully supported devices. + * + * To just query the number of processes ready to be queried, call this function with *count = 0 and + * pids=NULL. The return code will be NVML_ERROR_INSUFFICIENT_SIZE, or NVML_SUCCESS if list is empty. + * + * For more details see \ref nvmlDeviceGetAccountingStats. + * + * @note In case of PID collision some processes might not be accessible before the circular buffer is full. + * + * @param device The identifier of the target device + * @param count Reference in which to provide the \a pids array size, and + * to return the number of elements ready to be queried + * @param pids Reference in which to return list of process ids + * + * @return + * - \ref NVML_SUCCESS if pids were successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a count is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if \a device doesn't support this feature or accounting mode is disabled + * or on vGPU host. + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a count is too small (\a count is set to + * expected value) + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetAccountingBufferSize + */ +nvmlReturn_t DECLDIR nvmlDeviceGetAccountingPids(nvmlDevice_t device, unsigned int *count, unsigned int *pids); + +/** + * Returns the number of processes that the circular buffer with accounting pids can hold. + * + * For Kepler &tm; or newer fully supported devices. + * + * This is the maximum number of processes that accounting information will be stored for before information + * about oldest processes will get overwritten by information about new processes. + * + * @param device The identifier of the target device + * @param bufferSize Reference in which to provide the size (in number of elements) + * of the circular buffer for accounting stats. + * + * @return + * - \ref NVML_SUCCESS if buffer size was successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a bufferSize is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature or accounting mode is disabled + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetAccountingStats + * @see nvmlDeviceGetAccountingPids + */ +nvmlReturn_t DECLDIR nvmlDeviceGetAccountingBufferSize(nvmlDevice_t device, unsigned int *bufferSize); + +/** @} */ + +/** @addtogroup nvmlDeviceQueries + * @{ + */ + +/** + * Returns the list of retired pages by source, including pages that are pending retirement + * The address information provided from this API is the hardware address of the page that was retired. Note + * that this does not match the virtual address used in CUDA, but will match the address information in XID 63 + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param cause Filter page addresses by cause of retirement + * @param pageCount Reference in which to provide the \a addresses buffer size, and + * to return the number of retired pages that match \a cause + * Set to 0 to query the size without allocating an \a addresses buffer + * @param addresses Buffer to write the page addresses into + * + * @return + * - \ref NVML_SUCCESS if \a pageCount was populated and \a addresses was filled + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a pageCount indicates the buffer is not large enough to store all the + * matching page addresses. \a pageCount is set to the needed size. + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a pageCount is NULL, \a cause is invalid, or + * \a addresses is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetRetiredPages(nvmlDevice_t device, nvmlPageRetirementCause_t cause, + unsigned int *pageCount, unsigned long long *addresses); + +/** + * Returns the list of retired pages by source, including pages that are pending retirement + * The address information provided from this API is the hardware address of the page that was retired. Note + * that this does not match the virtual address used in CUDA, but will match the address information in XID 63 + * + * \note nvmlDeviceGetRetiredPages_v2 adds an additional timestamps paramter to return the time of each page's + * retirement. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param cause Filter page addresses by cause of retirement + * @param pageCount Reference in which to provide the \a addresses buffer size, and + * to return the number of retired pages that match \a cause + * Set to 0 to query the size without allocating an \a addresses buffer + * @param addresses Buffer to write the page addresses into + * @param timestamps Buffer to write the timestamps of page retirement, additional for _v2 + * + * @return + * - \ref NVML_SUCCESS if \a pageCount was populated and \a addresses was filled + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a pageCount indicates the buffer is not large enough to store all the + * matching page addresses. \a pageCount is set to the needed size. + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a pageCount is NULL, \a cause is invalid, or + * \a addresses is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetRetiredPages_v2(nvmlDevice_t device, nvmlPageRetirementCause_t cause, + unsigned int *pageCount, unsigned long long *addresses, unsigned long long *timestamps); + +/** + * Check if any pages are pending retirement and need a reboot to fully retire. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param isPending Reference in which to return the pending status + * + * @return + * - \ref NVML_SUCCESS if \a isPending was populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a isPending is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetRetiredPagesPendingStatus(nvmlDevice_t device, nvmlEnableState_t *isPending); + +/** + * Get number of remapped rows. The number of rows reported will be based on + * the cause of the remapping. isPending indicates whether or not there are + * pending remappings. A reset will be required to actually remap the row. + * failureOccurred will be set if a row remapping ever failed in the past. A + * pending remapping won't affect future work on the GPU since + * error-containment and dynamic page blacklisting will take care of that. + * + * @note On MIG-enabled GPUs with active instances, querying the number of + * remapped rows is not supported + * + * For Ampere &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param corrRows Reference for number of rows remapped due to correctable errors + * @param uncRows Reference for number of rows remapped due to uncorrectable errors + * @param isPending Reference for whether or not remappings are pending + * @param failureOccurred Reference that is set when a remapping has failed in the past + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a corrRows, \a uncRows, \a isPending or \a failureOccurred is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If MIG is enabled or if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN Unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetRemappedRows(nvmlDevice_t device, unsigned int *corrRows, unsigned int *uncRows, + unsigned int *isPending, unsigned int *failureOccurred); + +/** + * Get the row remapper histogram. Returns the remap availability for each bank + * on the GPU. + * + * @param device Device handle + * @param values Histogram values + * + * @return + * - \ref NVML_SUCCESS On success + * - \ref NVML_ERROR_UNKNOWN On any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetRowRemapperHistogram(nvmlDevice_t device, nvmlRowRemapperHistogramValues_t *values); + +/** + * Get architecture for device + * + * @param device The identifier of the target device + * @param arch Reference where architecture is returned, if call successful. + * Set to NVML_DEVICE_ARCH_* upon success + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a device or \a arch (output refererence) are invalid + */ +nvmlReturn_t DECLDIR nvmlDeviceGetArchitecture(nvmlDevice_t device, nvmlDeviceArchitecture_t *arch); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlUnitCommands Unit Commands + * This chapter describes NVML operations that change the state of the unit. For S-class products. + * Each of these requires root/admin access. Non-admin users will see an NVML_ERROR_NO_PERMISSION + * error code when invoking any of these methods. + * @{ + */ +/***************************************************************************************************/ + +/** + * Set the LED state for the unit. The LED can be either green (0) or amber (1). + * + * For S-class products. + * Requires root/admin permissions. + * + * This operation takes effect immediately. + * + * + * Current S-Class products don't provide unique LEDs for each unit. As such, both front + * and back LEDs will be toggled in unison regardless of which unit is specified with this command. + * + * See \ref nvmlLedColor_t for available colors. + * + * @param unit The identifier of the target unit + * @param color The target LED color + * + * @return + * - \ref NVML_SUCCESS if the LED color has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a unit or \a color is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if this is not an S-class product + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlUnitGetLedState() + */ +nvmlReturn_t DECLDIR nvmlUnitSetLedState(nvmlUnit_t unit, nvmlLedColor_t color); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlDeviceCommands Device Commands + * This chapter describes NVML operations that change the state of the device. + * Each of these requires root/admin access. Non-admin users will see an NVML_ERROR_NO_PERMISSION + * error code when invoking any of these methods. + * @{ + */ +/***************************************************************************************************/ + +/** + * Set the persistence mode for the device. + * + * For all products. + * For Linux only. + * Requires root/admin permissions. + * + * The persistence mode determines whether the GPU driver software is torn down after the last client + * exits. + * + * This operation takes effect immediately. It is not persistent across reboots. After each reboot the + * persistence mode is reset to "Disabled". + * + * See \ref nvmlEnableState_t for available modes. + * + * After calling this API with mode set to NVML_FEATURE_DISABLED on a device that has its own NUMA + * memory, the given device handle will no longer be valid, and to continue to interact with this + * device, a new handle should be obtained from one of the nvmlDeviceGetHandleBy*() APIs. This + * limitation is currently only applicable to devices that have a coherent NVLink connection to + * system memory. + * + * @param device The identifier of the target device + * @param mode The target persistence mode + * + * @return + * - \ref NVML_SUCCESS if the persistence mode was set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a mode is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetPersistenceMode() + */ +nvmlReturn_t DECLDIR nvmlDeviceSetPersistenceMode(nvmlDevice_t device, nvmlEnableState_t mode); + +/** + * Set the compute mode for the device. + * + * For all products. + * Requires root/admin permissions. + * + * The compute mode determines whether a GPU can be used for compute operations and whether it can + * be shared across contexts. + * + * This operation takes effect immediately. Under Linux it is not persistent across reboots and + * always resets to "Default". Under windows it is persistent. + * + * Under windows compute mode may only be set to DEFAULT when running in WDDM + * + * @note On MIG-enabled GPUs, compute mode would be set to DEFAULT and changing it is not supported. + * + * See \ref nvmlComputeMode_t for details on available compute modes. + * + * @param device The identifier of the target device + * @param mode The target compute mode + * + * @return + * - \ref NVML_SUCCESS if the compute mode was set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a mode is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetComputeMode() + */ +nvmlReturn_t DECLDIR nvmlDeviceSetComputeMode(nvmlDevice_t device, nvmlComputeMode_t mode); + +/** + * Set the ECC mode for the device. + * + * For Kepler &tm; or newer fully supported devices. + * Only applicable to devices with ECC. + * Requires \a NVML_INFOROM_ECC version 1.0 or higher. + * Requires root/admin permissions. + * + * The ECC mode determines whether the GPU enables its ECC support. + * + * This operation takes effect after the next reboot. + * + * See \ref nvmlEnableState_t for details on available modes. + * + * @param device The identifier of the target device + * @param ecc The target ECC mode + * + * @return + * - \ref NVML_SUCCESS if the ECC mode was set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a ecc is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetEccMode() + */ +nvmlReturn_t DECLDIR nvmlDeviceSetEccMode(nvmlDevice_t device, nvmlEnableState_t ecc); + +/** + * Clear the ECC error and other memory error counts for the device. + * + * For Kepler &tm; or newer fully supported devices. + * Only applicable to devices with ECC. + * Requires \a NVML_INFOROM_ECC version 2.0 or higher to clear aggregate location-based ECC counts. + * Requires \a NVML_INFOROM_ECC version 1.0 or higher to clear all other ECC counts. + * Requires root/admin permissions. + * Requires ECC Mode to be enabled. + * + * Sets all of the specified ECC counters to 0, including both detailed and total counts. + * + * This operation takes effect immediately. + * + * See \ref nvmlMemoryErrorType_t for details on available counter types. + * + * @param device The identifier of the target device + * @param counterType Flag that indicates which type of errors should be cleared. + * + * @return + * - \ref NVML_SUCCESS if the error counts were cleared + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a counterType is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see + * - nvmlDeviceGetDetailedEccErrors() + * - nvmlDeviceGetTotalEccErrors() + */ +nvmlReturn_t DECLDIR nvmlDeviceClearEccErrorCounts(nvmlDevice_t device, nvmlEccCounterType_t counterType); + +/** + * Set the driver model for the device. + * + * For Fermi &tm; or newer fully supported devices. + * For windows only. + * Requires root/admin permissions. + * + * On Windows platforms the device driver can run in either WDDM or WDM (TCC) mode. If a display is attached + * to the device it must run in WDDM mode. + * + * It is possible to force the change to WDM (TCC) while the display is still attached with a force flag (nvmlFlagForce). + * This should only be done if the host is subsequently powered down and the display is detached from the device + * before the next reboot. + * + * This operation takes effect after the next reboot. + * + * Windows driver model may only be set to WDDM when running in DEFAULT compute mode. + * + * Change driver model to WDDM is not supported when GPU doesn't support graphics acceleration or + * will not support it after reboot. See \ref nvmlDeviceSetGpuOperationMode. + * + * See \ref nvmlDriverModel_t for details on available driver models. + * See \ref nvmlFlagDefault and \ref nvmlFlagForce + * + * @param device The identifier of the target device + * @param driverModel The target driver model + * @param flags Flags that change the default behavior + * + * @return + * - \ref NVML_SUCCESS if the driver model has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a driverModel is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the platform is not windows or the device does not support this feature + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetDriverModel() + */ +nvmlReturn_t DECLDIR nvmlDeviceSetDriverModel(nvmlDevice_t device, nvmlDriverModel_t driverModel, unsigned int flags); + +typedef enum nvmlClockLimitId_enum { + NVML_CLOCK_LIMIT_ID_RANGE_START = 0xffffff00, + NVML_CLOCK_LIMIT_ID_TDP, + NVML_CLOCK_LIMIT_ID_UNLIMITED +} nvmlClockLimitId_t; + +/** + * Set clocks that device will lock to. + * + * Sets the clocks that the device will be running at to the value in the range of minGpuClockMHz to maxGpuClockMHz. + * Setting this will supercede application clock values and take effect regardless if a cuda app is running. + * See /ref nvmlDeviceSetApplicationsClocks + * + * Can be used as a setting to request constant performance. + * + * This can be called with a pair of integer clock frequencies in MHz, or a pair of /ref nvmlClockLimitId_t values. + * See the table below for valid combinations of these values. + * + * minGpuClock | maxGpuClock | Effect + * ------------+-------------+-------------------------------------------------- + * tdp | tdp | Lock clock to TDP + * unlimited | tdp | Upper bound is TDP but clock may drift below this + * tdp | unlimited | Lower bound is TDP but clock may boost above this + * unlimited | unlimited | Unlocked (== nvmlDeviceResetGpuLockedClocks) + * + * If one arg takes one of these values, the other must be one of these values as + * well. Mixed numeric and symbolic calls return NVML_ERROR_INVALID_ARGUMENT. + * + * Requires root/admin permissions. + * + * After system reboot or driver reload applications clocks go back to their default value. + * See \ref nvmlDeviceResetGpuLockedClocks. + * + * For Volta &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param minGpuClockMHz Requested minimum gpu clock in MHz + * @param maxGpuClockMHz Requested maximum gpu clock in MHz + * + * @return + * - \ref NVML_SUCCESS if new settings were successfully set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a minGpuClockMHz and \a maxGpuClockMHz + * is not a valid clock combination + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceSetGpuLockedClocks(nvmlDevice_t device, unsigned int minGpuClockMHz, unsigned int maxGpuClockMHz); + +/** + * Resets the gpu clock to the default value + * + * This is the gpu clock that will be used after system reboot or driver reload. + * Default values are idle clocks, but the current values can be changed using \ref nvmlDeviceSetApplicationsClocks. + * + * @see nvmlDeviceSetGpuLockedClocks + * + * For Volta &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * + * @return + * - \ref NVML_SUCCESS if new settings were successfully set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceResetGpuLockedClocks(nvmlDevice_t device); + +/** + * Set memory clocks that device will lock to. + * + * Sets the device's memory clocks to the value in the range of minMemClockMHz to maxMemClockMHz. + * Setting this will supersede application clock values and take effect regardless of whether a cuda app is running. + * See /ref nvmlDeviceSetApplicationsClocks + * + * Can be used as a setting to request constant performance. + * + * Requires root/admin permissions. + * + * After system reboot or driver reload applications clocks go back to their default value. + * See \ref nvmlDeviceResetMemoryLockedClocks. + * + * For Ampere &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param minMemClockMHz Requested minimum memory clock in MHz + * @param maxMemClockMHz Requested maximum memory clock in MHz + * + * @return + * - \ref NVML_SUCCESS if new settings were successfully set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a minGpuClockMHz and \a maxGpuClockMHz + * is not a valid clock combination + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceSetMemoryLockedClocks(nvmlDevice_t device, unsigned int minMemClockMHz, unsigned int maxMemClockMHz); + +/** + * Resets the memory clock to the default value + * + * This is the memory clock that will be used after system reboot or driver reload. + * Default values are idle clocks, but the current values can be changed using \ref nvmlDeviceSetApplicationsClocks. + * + * @see nvmlDeviceSetMemoryLockedClocks + * + * For Ampere &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * + * @return + * - \ref NVML_SUCCESS if new settings were successfully set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceResetMemoryLockedClocks(nvmlDevice_t device); + +/** + * Set clocks that applications will lock to. + * + * Sets the clocks that compute and graphics applications will be running at. + * e.g. CUDA driver requests these clocks during context creation which means this property + * defines clocks at which CUDA applications will be running unless some overspec event + * occurs (e.g. over power, over thermal or external HW brake). + * + * Can be used as a setting to request constant performance. + * + * On Pascal and newer hardware, this will automatically disable automatic boosting of clocks. + * + * On K80 and newer Kepler and Maxwell GPUs, users desiring fixed performance should also call + * \ref nvmlDeviceSetAutoBoostedClocksEnabled to prevent clocks from automatically boosting + * above the clock value being set. + * + * For Kepler &tm; or newer non-GeForce fully supported devices and Maxwell or newer GeForce devices. + * Requires root/admin permissions. + * + * See \ref nvmlDeviceGetSupportedMemoryClocks and \ref nvmlDeviceGetSupportedGraphicsClocks + * for details on how to list available clocks combinations. + * + * After system reboot or driver reload applications clocks go back to their default value. + * See \ref nvmlDeviceResetApplicationsClocks. + * + * @param device The identifier of the target device + * @param memClockMHz Requested memory clock in MHz + * @param graphicsClockMHz Requested graphics clock in MHz + * + * @return + * - \ref NVML_SUCCESS if new settings were successfully set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a memClockMHz and \a graphicsClockMHz + * is not a valid clock combination + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceSetApplicationsClocks(nvmlDevice_t device, unsigned int memClockMHz, unsigned int graphicsClockMHz); + +/** + * Retrieves the frequency monitor fault status for the device. + * + * For Ampere &tm; or newer fully supported devices. + * Requires root user. + * + * See \ref nvmlClkMonStatus_t for details on decoding the status output. + * + * @param device The identifier of the target device + * @param status Reference in which to return the clkmon fault status + * + * @return + * - \ref NVML_SUCCESS if \a status has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a status is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetClkMonStatus() + */ +nvmlReturn_t DECLDIR nvmlDeviceGetClkMonStatus(nvmlDevice_t device, nvmlClkMonStatus_t *status); + +/** + * Set new power limit of this device. + * + * For Kepler &tm; or newer fully supported devices. + * Requires root/admin permissions. + * + * See \ref nvmlDeviceGetPowerManagementLimitConstraints to check the allowed ranges of values. + * + * \note Limit is not persistent across reboots or driver unloads. + * Enable persistent mode to prevent driver from unloading when no application is using the device. + * + * @param device The identifier of the target device + * @param limit Power management limit in milliwatts to set + * + * @return + * - \ref NVML_SUCCESS if \a limit has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a defaultLimit is out of range + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetPowerManagementLimitConstraints + * @see nvmlDeviceGetPowerManagementDefaultLimit + */ +nvmlReturn_t DECLDIR nvmlDeviceSetPowerManagementLimit(nvmlDevice_t device, unsigned int limit); + +/** + * Sets new GOM. See \a nvmlGpuOperationMode_t for details. + * + * For GK110 M-class and X-class Tesla &tm; products from the Kepler family. + * Modes \ref NVML_GOM_LOW_DP and \ref NVML_GOM_ALL_ON are supported on fully supported GeForce products. + * Not supported on Quadro ® and Tesla &tm; C-class products. + * Requires root/admin permissions. + * + * Changing GOMs requires a reboot. + * The reboot requirement might be removed in the future. + * + * Compute only GOMs don't support graphics acceleration. Under windows switching to these GOMs when + * pending driver model is WDDM is not supported. See \ref nvmlDeviceSetDriverModel. + * + * @param device The identifier of the target device + * @param mode Target GOM + * + * @return + * - \ref NVML_SUCCESS if \a mode has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a mode incorrect + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support GOM or specific mode + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlGpuOperationMode_t + * @see nvmlDeviceGetGpuOperationMode + */ +nvmlReturn_t DECLDIR nvmlDeviceSetGpuOperationMode(nvmlDevice_t device, nvmlGpuOperationMode_t mode); + +/** + * Changes the root/admin restructions on certain APIs. See \a nvmlRestrictedAPI_t for the list of supported APIs. + * This method can be used by a root/admin user to give non-root/admin access to certain otherwise-restricted APIs. + * The new setting lasts for the lifetime of the NVIDIA driver; it is not persistent. See \a nvmlDeviceGetAPIRestriction + * to query the current restriction settings. + * + * For Kepler &tm; or newer fully supported devices. + * Requires root/admin permissions. + * + * @param device The identifier of the target device + * @param apiType Target API type for this operation + * @param isRestricted The target restriction + * + * @return + * - \ref NVML_SUCCESS if \a isRestricted has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a apiType incorrect + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support changing API restrictions or the device does not support + * the feature that api restrictions are being set for (E.G. Enabling/disabling auto + * boosted clocks is not supported by the device) + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlRestrictedAPI_t + */ +nvmlReturn_t DECLDIR nvmlDeviceSetAPIRestriction(nvmlDevice_t device, nvmlRestrictedAPI_t apiType, nvmlEnableState_t isRestricted); + +/** + * @} + */ + +/** @addtogroup nvmlAccountingStats + * @{ + */ + +/** + * Enables or disables per process accounting. + * + * For Kepler &tm; or newer fully supported devices. + * Requires root/admin permissions. + * + * @note This setting is not persistent and will default to disabled after driver unloads. + * Enable persistence mode to be sure the setting doesn't switch off to disabled. + * + * @note Enabling accounting mode has no negative impact on the GPU performance. + * + * @note Disabling accounting clears all accounting pids information. + * + * @note On MIG-enabled GPUs, accounting mode would be set to DISABLED and changing it is not supported. + * + * See \ref nvmlDeviceGetAccountingMode + * See \ref nvmlDeviceGetAccountingStats + * See \ref nvmlDeviceClearAccountingPids + * + * @param device The identifier of the target device + * @param mode The target accounting mode + * + * @return + * - \ref NVML_SUCCESS if the new mode has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device or \a mode are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceSetAccountingMode(nvmlDevice_t device, nvmlEnableState_t mode); + +/** + * Clears accounting information about all processes that have already terminated. + * + * For Kepler &tm; or newer fully supported devices. + * Requires root/admin permissions. + * + * See \ref nvmlDeviceGetAccountingMode + * See \ref nvmlDeviceGetAccountingStats + * See \ref nvmlDeviceSetAccountingMode + * + * @param device The identifier of the target device + * + * @return + * - \ref NVML_SUCCESS if accounting information has been cleared + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceClearAccountingPids(nvmlDevice_t device); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup NvLink NvLink Methods + * This chapter describes methods that NVML can perform on NVLINK enabled devices. + * @{ + */ +/***************************************************************************************************/ + +/** + * Retrieves the state of the device's NvLink for the link specified + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param link Specifies the NvLink link to be queried + * @param isActive \a nvmlEnableState_t where NVML_FEATURE_ENABLED indicates that + * the link is active and NVML_FEATURE_DISABLED indicates it + * is inactive + * + * @return + * - \ref NVML_SUCCESS if \a isActive has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device or \a link is invalid or \a isActive is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetNvLinkState(nvmlDevice_t device, unsigned int link, nvmlEnableState_t *isActive); + +/** + * Retrieves the version of the device's NvLink for the link specified + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param link Specifies the NvLink link to be queried + * @param version Requested NvLink version + * + * @return + * - \ref NVML_SUCCESS if \a version has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device or \a link is invalid or \a version is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetNvLinkVersion(nvmlDevice_t device, unsigned int link, unsigned int *version); + +/** + * Retrieves the requested capability from the device's NvLink for the link specified + * Please refer to the \a nvmlNvLinkCapability_t structure for the specific caps that can be queried + * The return value should be treated as a boolean. + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param link Specifies the NvLink link to be queried + * @param capability Specifies the \a nvmlNvLinkCapability_t to be queried + * @param capResult A boolean for the queried capability indicating that feature is available + * + * @return + * - \ref NVML_SUCCESS if \a capResult has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a link, or \a capability is invalid or \a capResult is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetNvLinkCapability(nvmlDevice_t device, unsigned int link, + nvmlNvLinkCapability_t capability, unsigned int *capResult); + +/** + * Retrieves the PCI information for the remote node on a NvLink link + * Note: pciSubSystemId is not filled in this function and is indeterminate + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param link Specifies the NvLink link to be queried + * @param pci \a nvmlPciInfo_t of the remote node for the specified link + * + * @return + * - \ref NVML_SUCCESS if \a pci has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device or \a link is invalid or \a pci is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetNvLinkRemotePciInfo_v2(nvmlDevice_t device, unsigned int link, nvmlPciInfo_t *pci); + +/** + * Retrieves the specified error counter value + * Please refer to \a nvmlNvLinkErrorCounter_t for error counters that are available + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param link Specifies the NvLink link to be queried + * @param counter Specifies the NvLink counter to be queried + * @param counterValue Returned counter value + * + * @return + * - \ref NVML_SUCCESS if \a counter has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a link, or \a counter is invalid or \a counterValue is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetNvLinkErrorCounter(nvmlDevice_t device, unsigned int link, + nvmlNvLinkErrorCounter_t counter, unsigned long long *counterValue); + +/** + * Resets all error counters to zero + * Please refer to \a nvmlNvLinkErrorCounter_t for the list of error counters that are reset + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param link Specifies the NvLink link to be queried + * + * @return + * - \ref NVML_SUCCESS if the reset is successful + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device or \a link is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceResetNvLinkErrorCounters(nvmlDevice_t device, unsigned int link); + +/** + * Deprecated: Setting utilization counter control is no longer supported. + * + * Set the NVLINK utilization counter control information for the specified counter, 0 or 1. + * Please refer to \a nvmlNvLinkUtilizationControl_t for the structure definition. Performs a reset + * of the counters if the reset parameter is non-zero. + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param counter Specifies the counter that should be set (0 or 1). + * @param link Specifies the NvLink link to be queried + * @param control A reference to the \a nvmlNvLinkUtilizationControl_t to set + * @param reset Resets the counters on set if non-zero + * + * @return + * - \ref NVML_SUCCESS if the control has been set successfully + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a counter, \a link, or \a control is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceSetNvLinkUtilizationControl(nvmlDevice_t device, unsigned int link, unsigned int counter, + nvmlNvLinkUtilizationControl_t *control, unsigned int reset); + +/** + * Deprecated: Getting utilization counter control is no longer supported. + * + * Get the NVLINK utilization counter control information for the specified counter, 0 or 1. + * Please refer to \a nvmlNvLinkUtilizationControl_t for the structure definition + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param counter Specifies the counter that should be set (0 or 1). + * @param link Specifies the NvLink link to be queried + * @param control A reference to the \a nvmlNvLinkUtilizationControl_t to place information + * + * @return + * - \ref NVML_SUCCESS if the control has been set successfully + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a counter, \a link, or \a control is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetNvLinkUtilizationControl(nvmlDevice_t device, unsigned int link, unsigned int counter, + nvmlNvLinkUtilizationControl_t *control); + + +/** + * Deprecated: Use \ref nvmlDeviceGetFieldValues with NVML_FI_DEV_NVLINK_THROUGHPUT_* as field values instead. + * + * Retrieve the NVLINK utilization counter based on the current control for a specified counter. + * In general it is good practice to use \a nvmlDeviceSetNvLinkUtilizationControl + * before reading the utilization counters as they have no default state + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param link Specifies the NvLink link to be queried + * @param counter Specifies the counter that should be read (0 or 1). + * @param rxcounter Receive counter return value + * @param txcounter Transmit counter return value + * + * @return + * - \ref NVML_SUCCESS if \a rxcounter and \a txcounter have been successfully set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a counter, or \a link is invalid or \a rxcounter or \a txcounter are NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetNvLinkUtilizationCounter(nvmlDevice_t device, unsigned int link, unsigned int counter, + unsigned long long *rxcounter, unsigned long long *txcounter); + +/** + * Deprecated: Freezing NVLINK utilization counters is no longer supported. + * + * Freeze the NVLINK utilization counters + * Both the receive and transmit counters are operated on by this function + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param link Specifies the NvLink link to be queried + * @param counter Specifies the counter that should be frozen (0 or 1). + * @param freeze NVML_FEATURE_ENABLED = freeze the receive and transmit counters + * NVML_FEATURE_DISABLED = unfreeze the receive and transmit counters + * + * @return + * - \ref NVML_SUCCESS if counters were successfully frozen or unfrozen + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a link, \a counter, or \a freeze is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceFreezeNvLinkUtilizationCounter (nvmlDevice_t device, unsigned int link, + unsigned int counter, nvmlEnableState_t freeze); + +/** + * Deprecated: Resetting NVLINK utilization counters is no longer supported. + * + * Reset the NVLINK utilization counters + * Both the receive and transmit counters are operated on by this function + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param link Specifies the NvLink link to be reset + * @param counter Specifies the counter that should be reset (0 or 1) + * + * @return + * - \ref NVML_SUCCESS if counters were successfully reset + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a link, or \a counter is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceResetNvLinkUtilizationCounter (nvmlDevice_t device, unsigned int link, unsigned int counter); + +/** +* Get the NVLink device type of the remote device connected over the given link. +* +* @param device The device handle of the target GPU +* @param link The NVLink link index on the target GPU +* @param pNvLinkDeviceType Pointer in which the output remote device type is returned +* +* @return +* - \ref NVML_SUCCESS if \a pNvLinkDeviceType has been set +* - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized +* - \ref NVML_ERROR_NOT_SUPPORTED if NVLink is not supported +* - \ref NVML_ERROR_INVALID_ARGUMENT if \a device or \a link is invalid, or +* \a pNvLinkDeviceType is NULL +* - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is +* otherwise inaccessible +* - \ref NVML_ERROR_UNKNOWN on any unexpected error +*/ +nvmlReturn_t DECLDIR nvmlDeviceGetNvLinkRemoteDeviceType(nvmlDevice_t device, unsigned int link, nvmlIntNvLinkDeviceType_t *pNvLinkDeviceType); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlEvents Event Handling Methods + * This chapter describes methods that NVML can perform against each device to register and wait for + * some event to occur. + * @{ + */ +/***************************************************************************************************/ + +/** + * Create an empty set of events. + * Event set should be freed by \ref nvmlEventSetFree + * + * For Fermi &tm; or newer fully supported devices. + * @param set Reference in which to return the event handle + * + * @return + * - \ref NVML_SUCCESS if the event has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a set is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlEventSetFree + */ +nvmlReturn_t DECLDIR nvmlEventSetCreate(nvmlEventSet_t *set); + +/** + * Starts recording of events on a specified devices and add the events to specified \ref nvmlEventSet_t + * + * For Fermi &tm; or newer fully supported devices. + * Ecc events are available only on ECC enabled devices (see \ref nvmlDeviceGetTotalEccErrors) + * Power capping events are available only on Power Management enabled devices (see \ref nvmlDeviceGetPowerManagementMode) + * + * For Linux only. + * + * \b IMPORTANT: Operations on \a set are not thread safe + * + * This call starts recording of events on specific device. + * All events that occurred before this call are not recorded. + * Checking if some event occurred can be done with \ref nvmlEventSetWait_v2 + * + * If function reports NVML_ERROR_UNKNOWN, event set is in undefined state and should be freed. + * If function reports NVML_ERROR_NOT_SUPPORTED, event set can still be used. None of the requested eventTypes + * are registered in that case. + * + * @param device The identifier of the target device + * @param eventTypes Bitmask of \ref nvmlEventType to record + * @param set Set to which add new event types + * + * @return + * - \ref NVML_SUCCESS if the event has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a eventTypes is invalid or \a set is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the platform does not support this feature or some of requested event types + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlEventType + * @see nvmlDeviceGetSupportedEventTypes + * @see nvmlEventSetWait + * @see nvmlEventSetFree + */ +nvmlReturn_t DECLDIR nvmlDeviceRegisterEvents(nvmlDevice_t device, unsigned long long eventTypes, nvmlEventSet_t set); + +/** + * Returns information about events supported on device + * + * For Fermi &tm; or newer fully supported devices. + * + * Events are not supported on Windows. So this function returns an empty mask in \a eventTypes on Windows. + * + * @param device The identifier of the target device + * @param eventTypes Reference in which to return bitmask of supported events + * + * @return + * - \ref NVML_SUCCESS if the eventTypes has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a eventType is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlEventType + * @see nvmlDeviceRegisterEvents + */ +nvmlReturn_t DECLDIR nvmlDeviceGetSupportedEventTypes(nvmlDevice_t device, unsigned long long *eventTypes); + +/** + * Waits on events and delivers events + * + * For Fermi &tm; or newer fully supported devices. + * + * If some events are ready to be delivered at the time of the call, function returns immediately. + * If there are no events ready to be delivered, function sleeps till event arrives + * but not longer than specified timeout. This function in certain conditions can return before + * specified timeout passes (e.g. when interrupt arrives) + * + * On Windows, in case of xid error, the function returns the most recent xid error type seen by the system. + * If there are multiple xid errors generated before nvmlEventSetWait is invoked then the last seen xid error + * type is returned for all xid error events. + * + * On Linux, every xid error event would return the associated event data and other information if applicable. + * + * In MIG mode, if device handle is provided, the API reports all the events for the available instances, + * only if the caller has appropriate privileges. In absence of required privileges, only the events which + * affect all the instances (i.e. whole device) are reported. + * + * This API does not currently support per-instance event reporting using MIG device handles. + * + * @param set Reference to set of events to wait on + * @param data Reference in which to return event data + * @param timeoutms Maximum amount of wait time in milliseconds for registered event + * + * @return + * - \ref NVML_SUCCESS if the data has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a data is NULL + * - \ref NVML_ERROR_TIMEOUT if no event arrived in specified timeout or interrupt arrived + * - \ref NVML_ERROR_GPU_IS_LOST if a GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlEventType + * @see nvmlDeviceRegisterEvents + */ +nvmlReturn_t DECLDIR nvmlEventSetWait_v2(nvmlEventSet_t set, nvmlEventData_t * data, unsigned int timeoutms); + +/** + * Releases events in the set + * + * For Fermi &tm; or newer fully supported devices. + * + * @param set Reference to events to be released + * + * @return + * - \ref NVML_SUCCESS if the event has been successfully released + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceRegisterEvents + */ +nvmlReturn_t DECLDIR nvmlEventSetFree(nvmlEventSet_t set); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlZPI Drain states + * This chapter describes methods that NVML can perform against each device to control their drain state + * and recognition by NVML and NVIDIA kernel driver. These methods can be used with out-of-band tools to + * power on/off GPUs, enable robust reset scenarios, etc. + * @{ + */ +/***************************************************************************************************/ + +/** + * Modify the drain state of a GPU. This method forces a GPU to no longer accept new incoming requests. + * Any new NVML process will no longer see this GPU. Persistence mode for this GPU must be turned off before + * this call is made. + * Must be called as administrator. + * For Linux only. + * + * For Pascal &tm; or newer fully supported devices. + * Some Kepler devices supported. + * + * @param pciInfo The PCI address of the GPU drain state to be modified + * @param newState The drain state that should be entered, see \ref nvmlEnableState_t + * + * @return + * - \ref NVML_SUCCESS if counters were successfully reset + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a nvmlIndex or \a newState is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_NO_PERMISSION if the calling process has insufficient permissions to perform operation + * - \ref NVML_ERROR_IN_USE if the device has persistence mode turned on + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceModifyDrainState (nvmlPciInfo_t *pciInfo, nvmlEnableState_t newState); + +/** + * Query the drain state of a GPU. This method is used to check if a GPU is in a currently draining + * state. + * For Linux only. + * + * For Pascal &tm; or newer fully supported devices. + * Some Kepler devices supported. + * + * @param pciInfo The PCI address of the GPU drain state to be queried + * @param currentState The current drain state for this GPU, see \ref nvmlEnableState_t + * + * @return + * - \ref NVML_SUCCESS if counters were successfully reset + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a nvmlIndex or \a currentState is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceQueryDrainState (nvmlPciInfo_t *pciInfo, nvmlEnableState_t *currentState); + +/** + * This method will remove the specified GPU from the view of both NVML and the NVIDIA kernel driver + * as long as no other processes are attached. If other processes are attached, this call will return + * NVML_ERROR_IN_USE and the GPU will be returned to its original "draining" state. Note: the + * only situation where a process can still be attached after nvmlDeviceModifyDrainState() is called + * to initiate the draining state is if that process was using, and is still using, a GPU before the + * call was made. Also note, persistence mode counts as an attachment to the GPU thus it must be disabled + * prior to this call. + * + * For long-running NVML processes please note that this will change the enumeration of current GPUs. + * For example, if there are four GPUs present and GPU1 is removed, the new enumeration will be 0-2. + * Also, device handles after the removed GPU will not be valid and must be re-established. + * Must be run as administrator. + * For Linux only. + * + * For Pascal &tm; or newer fully supported devices. + * Some Kepler devices supported. + * + * @param pciInfo The PCI address of the GPU to be removed + * @param gpuState Whether the GPU is to be removed, from the OS + * see \ref nvmlDetachGpuState_t + * @param linkState Requested upstream PCIe link state, see \ref nvmlPcieLinkState_t + * + * @return + * - \ref NVML_SUCCESS if counters were successfully reset + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a nvmlIndex is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_IN_USE if the device is still in use and cannot be removed + */ +nvmlReturn_t DECLDIR nvmlDeviceRemoveGpu_v2(nvmlPciInfo_t *pciInfo, nvmlDetachGpuState_t gpuState, nvmlPcieLinkState_t linkState); + +/** + * Request the OS and the NVIDIA kernel driver to rediscover a portion of the PCI subsystem looking for GPUs that + * were previously removed. The portion of the PCI tree can be narrowed by specifying a domain, bus, and device. + * If all are zeroes then the entire PCI tree will be searched. Please note that for long-running NVML processes + * the enumeration will change based on how many GPUs are discovered and where they are inserted in bus order. + * + * In addition, all newly discovered GPUs will be initialized and their ECC scrubbed which may take several seconds + * per GPU. Also, all device handles are no longer guaranteed to be valid post discovery. + * + * Must be run as administrator. + * For Linux only. + * + * For Pascal &tm; or newer fully supported devices. + * Some Kepler devices supported. + * + * @param pciInfo The PCI tree to be searched. Only the domain, bus, and device + * fields are used in this call. + * + * @return + * - \ref NVML_SUCCESS if counters were successfully reset + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a pciInfo is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the operating system does not support this feature + * - \ref NVML_ERROR_OPERATING_SYSTEM if the operating system is denying this feature + * - \ref NVML_ERROR_NO_PERMISSION if the calling process has insufficient permissions to perform operation + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceDiscoverGpus (nvmlPciInfo_t *pciInfo); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlFieldValueQueries Field Value Queries + * This chapter describes NVML operations that are associated with retrieving Field Values from NVML + * @{ + */ +/***************************************************************************************************/ + +/** + * Request values for a list of fields for a device. This API allows multiple fields to be queried at once. + * If any of the underlying fieldIds are populated by the same driver call, the results for those field IDs + * will be populated from a single call rather than making a driver call for each fieldId. + * + * @param device The device handle of the GPU to request field values for + * @param valuesCount Number of entries in values that should be retrieved + * @param values Array of \a valuesCount structures to hold field values. + * Each value's fieldId must be populated prior to this call + * + * @return + * - \ref NVML_SUCCESS if any values in \a values were populated. Note that you must + * check the nvmlReturn field of each value for each individual + * status + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a values is NULL + */ +nvmlReturn_t DECLDIR nvmlDeviceGetFieldValues(nvmlDevice_t device, int valuesCount, nvmlFieldValue_t *values); + +/** + * Clear values for a list of fields for a device. This API allows multiple fields to be cleared at once. + * + * @param device The device handle of the GPU to request field values for + * @param valuesCount Number of entries in values that should be cleared + * @param values Array of \a valuesCount structures to hold field values. + * Each value's fieldId must be populated prior to this call + * + * @return + * - \ref NVML_SUCCESS if any values in \a values were cleared. Note that you must + * check the nvmlReturn field of each value for each individual + * status + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a values is NULL + */ +nvmlReturn_t DECLDIR nvmlDeviceClearFieldValues(nvmlDevice_t device, int valuesCount, nvmlFieldValue_t *values); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup vGPU Enums, Constants and Structs + * @{ + */ +/** @} */ +/***************************************************************************************************/ + +/***************************************************************************************************/ +/** @defgroup nvmlVirtualGpuQueries vGPU APIs + * This chapter describes operations that are associated with NVIDIA vGPU Software products. + * @{ + */ +/***************************************************************************************************/ + +/** + * This method is used to get the virtualization mode corresponding to the GPU. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device Identifier of the target device + * @param pVirtualMode Reference to virtualization mode. One of NVML_GPU_VIRTUALIZATION_? + * + * @return + * - \ref NVML_SUCCESS if \a pVirtualMode is fetched + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a pVirtualMode is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetVirtualizationMode(nvmlDevice_t device, nvmlGpuVirtualizationMode_t *pVirtualMode); + +/** + * Queries if SR-IOV host operation is supported on a vGPU supported device. + * + * Checks whether SR-IOV host capability is supported by the device and the + * driver, and indicates device is in SR-IOV mode if both of these conditions + * are true. + * + * @param device The identifier of the target device + * @param pHostVgpuMode Reference in which to return the current vGPU mode + * + * @return + * - \ref NVML_SUCCESS if device's vGPU mode has been successfully retrieved + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device handle is 0 or \a pVgpuMode is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if \a device doesn't support this feature. + * - \ref NVML_ERROR_UNKNOWN if any unexpected error occurred + */ +nvmlReturn_t DECLDIR nvmlDeviceGetHostVgpuMode(nvmlDevice_t device, nvmlHostVgpuMode_t *pHostVgpuMode); + +/** + * This method is used to set the virtualization mode corresponding to the GPU. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device Identifier of the target device + * @param virtualMode virtualization mode. One of NVML_GPU_VIRTUALIZATION_? + * + * @return + * - \ref NVML_SUCCESS if \a pVirtualMode is set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a pVirtualMode is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_NOT_SUPPORTED if setting of virtualization mode is not supported. + * - \ref NVML_ERROR_NO_PERMISSION if setting of virtualization mode is not allowed for this client. + */ +nvmlReturn_t DECLDIR nvmlDeviceSetVirtualizationMode(nvmlDevice_t device, nvmlGpuVirtualizationMode_t virtualMode); + +/** + * Retrieve the vGPU Software licensable features. + * + * Identifies whether the system supports vGPU Software Licensing. If it does, return the list of licensable feature(s) + * and their current license status. + * + * @param device Identifier of the target device + * @param pGridLicensableFeatures Pointer to structure in which vGPU software licensable features are returned + * + * @return + * - \ref NVML_SUCCESS if licensable features are successfully retrieved + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a pGridLicensableFeatures is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGridLicensableFeatures_v4(nvmlDevice_t device, nvmlGridLicensableFeatures_t *pGridLicensableFeatures); + +/** + * Retrieves the current utilization and process ID + * + * For Maxwell &tm; or newer fully supported devices. + * + * Reads recent utilization of GPU SM (3D/Compute), framebuffer, video encoder, and video decoder for processes running. + * Utilization values are returned as an array of utilization sample structures in the caller-supplied buffer pointed at + * by \a utilization. One utilization sample structure is returned per process running, that had some non-zero utilization + * during the last sample period. It includes the CPU timestamp at which the samples were recorded. Individual utilization values + * are returned as "unsigned int" values. + * + * To read utilization values, first determine the size of buffer required to hold the samples by invoking the function with + * \a utilization set to NULL. The caller should allocate a buffer of size + * processSamplesCount * sizeof(nvmlProcessUtilizationSample_t). Invoke the function again with the allocated buffer passed + * in \a utilization, and \a processSamplesCount set to the number of entries the buffer is sized for. + * + * On successful return, the function updates \a processSamplesCount with the number of process utilization sample + * structures that were actually written. This may differ from a previously read value as instances are created or + * destroyed. + * + * lastSeenTimeStamp represents the CPU timestamp in microseconds at which utilization samples were last read. Set it to 0 + * to read utilization based on all the samples maintained by the driver's internal sample buffer. Set lastSeenTimeStamp + * to a timeStamp retrieved from a previous query to read utilization since the previous query. + * + * @note On MIG-enabled GPUs, querying process utilization is not currently supported. + * + * @param device The identifier of the target device + * @param utilization Pointer to caller-supplied buffer in which guest process utilization samples are returned + * @param processSamplesCount Pointer to caller-supplied array size, and returns number of processes running + * @param lastSeenTimeStamp Return only samples with timestamp greater than lastSeenTimeStamp. + + * @return + * - \ref NVML_SUCCESS if \a utilization has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a utilization is NULL, or \a samplingPeriodUs is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_NOT_FOUND if sample entries are not found + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetProcessUtilization(nvmlDevice_t device, nvmlProcessUtilizationSample_t *utilization, + unsigned int *processSamplesCount, unsigned long long lastSeenTimeStamp); + +/** + * Retrieve GSP firmware version. + * + * The caller passes in buffer via \a version and corresponding GSP firmware numbered version + * is returned with the same parameter in string format. + * + * @param device Device handle + * @param version The retrieved GSP firmware version + * + * @return + * - \ref NVML_SUCCESS if GSP firmware version is sucessfully retrieved + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or GSP \a version pointer is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if GSP firmware is not enabled for GPU + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGspFirmwareVersion(nvmlDevice_t device, char *version); + +/** + * Retrieve GSP firmware mode. + * + * The caller passes in integer pointers. GSP firmware enablement and default mode information is returned with + * corresponding parameters. The return value in \a isEnabled and \a defaultMode should be treated as boolean. + * + * @param device Device handle + * @param isEnabled Pointer to specify if GSP firmware is enabled + * @param defaultMode Pointer to specify if GSP firmware is supported by default on \a device + * + * @return + * - \ref NVML_SUCCESS if GSP firmware mode is sucessfully retrieved + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or any of \a isEnabled or \a defaultMode is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGspFirmwareMode(nvmlDevice_t device, unsigned int *isEnabled, unsigned int *defaultMode); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlVgpu vGPU Management + * @{ + * + * This chapter describes APIs supporting NVIDIA vGPU. + */ +/***************************************************************************************************/ + +/** + * Retrieve the requested vGPU driver capability. + * + * Refer to the \a nvmlVgpuDriverCapability_t structure for the specific capabilities that can be queried. + * The return value in \a capResult should be treated as a boolean, with a non-zero value indicating that the capability + * is supported. + * + * For Maxwell &tm; or newer fully supported devices. + * + * @param capability Specifies the \a nvmlVgpuDriverCapability_t to be queried + * @param capResult A boolean for the queried capability indicating that feature is supported + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a capability is invalid, or \a capResult is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED the API is not supported in current state or \a devices not in vGPU mode + * - \ref NVML_ERROR_UNKNOWN on any unexpected error +*/ +nvmlReturn_t DECLDIR nvmlGetVgpuDriverCapabilities(nvmlVgpuDriverCapability_t capability, unsigned int *capResult); + +/** + * Retrieve the requested vGPU capability for GPU. + * + * Refer to the \a nvmlDeviceVgpuCapability_t structure for the specific capabilities that can be queried. + * The return value in \a capResult should be treated as a boolean, with a non-zero value indicating that the capability + * is supported. + * + * For Maxwell &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param capability Specifies the \a nvmlDeviceVgpuCapability_t to be queried + * @param capResult A boolean for the queried capability indicating that feature is supported + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a capability is invalid, or \a capResult is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED the API is not supported in current state or \a device not in vGPU mode + * - \ref NVML_ERROR_UNKNOWN on any unexpected error +*/ +nvmlReturn_t DECLDIR nvmlDeviceGetVgpuCapabilities(nvmlDevice_t device, nvmlDeviceVgpuCapability_t capability, unsigned int *capResult); + +/** + * Retrieve the supported vGPU types on a physical GPU (device). + * + * An array of supported vGPU types for the physical GPU indicated by \a device is returned in the caller-supplied buffer + * pointed at by \a vgpuTypeIds. The element count of nvmlVgpuTypeId_t array is passed in \a vgpuCount, and \a vgpuCount + * is used to return the number of vGPU types written to the buffer. + * + * If the supplied buffer is not large enough to accomodate the vGPU type array, the function returns + * NVML_ERROR_INSUFFICIENT_SIZE, with the element count of nvmlVgpuTypeId_t array required in \a vgpuCount. + * To query the number of vGPU types supported for the GPU, call this function with *vgpuCount = 0. + * The code will return NVML_ERROR_INSUFFICIENT_SIZE, or NVML_SUCCESS if no vGPU types are supported. + * + * @param device The identifier of the target device + * @param vgpuCount Pointer to caller-supplied array size, and returns number of vGPU types + * @param vgpuTypeIds Pointer to caller-supplied array in which to return list of vGPU types + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_INSUFFICIENT_SIZE \a vgpuTypeIds buffer is too small, array element count is returned in \a vgpuCount + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuCount is NULL or \a device is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if vGPU is not supported by the device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetSupportedVgpus(nvmlDevice_t device, unsigned int *vgpuCount, nvmlVgpuTypeId_t *vgpuTypeIds); + +/** + * Retrieve the currently creatable vGPU types on a physical GPU (device). + * + * An array of creatable vGPU types for the physical GPU indicated by \a device is returned in the caller-supplied buffer + * pointed at by \a vgpuTypeIds. The element count of nvmlVgpuTypeId_t array is passed in \a vgpuCount, and \a vgpuCount + * is used to return the number of vGPU types written to the buffer. + * + * The creatable vGPU types for a device may differ over time, as there may be restrictions on what type of vGPU types + * can concurrently run on a device. For example, if only one vGPU type is allowed at a time on a device, then the creatable + * list will be restricted to whatever vGPU type is already running on the device. + * + * If the supplied buffer is not large enough to accomodate the vGPU type array, the function returns + * NVML_ERROR_INSUFFICIENT_SIZE, with the element count of nvmlVgpuTypeId_t array required in \a vgpuCount. + * To query the number of vGPU types createable for the GPU, call this function with *vgpuCount = 0. + * The code will return NVML_ERROR_INSUFFICIENT_SIZE, or NVML_SUCCESS if no vGPU types are creatable. + * + * @param device The identifier of the target device + * @param vgpuCount Pointer to caller-supplied array size, and returns number of vGPU types + * @param vgpuTypeIds Pointer to caller-supplied array in which to return list of vGPU types + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_INSUFFICIENT_SIZE \a vgpuTypeIds buffer is too small, array element count is returned in \a vgpuCount + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuCount is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if vGPU is not supported by the device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetCreatableVgpus(nvmlDevice_t device, unsigned int *vgpuCount, nvmlVgpuTypeId_t *vgpuTypeIds); + +/** + * Retrieve the class of a vGPU type. It will not exceed 64 characters in length (including the NUL terminator). + * See \ref nvmlConstants::NVML_DEVICE_NAME_BUFFER_SIZE. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuTypeId Handle to vGPU type + * @param vgpuTypeClass Pointer to string array to return class in + * @param size Size of string + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuTypeId is invalid, or \a vgpuTypeClass is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a size is too small + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuTypeGetClass(nvmlVgpuTypeId_t vgpuTypeId, char *vgpuTypeClass, unsigned int *size); + +/** + * Retrieve the vGPU type name. + * + * The name is an alphanumeric string that denotes a particular vGPU, e.g. GRID M60-2Q. It will not + * exceed 64 characters in length (including the NUL terminator). See \ref + * nvmlConstants::NVML_DEVICE_NAME_BUFFER_SIZE. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuTypeId Handle to vGPU type + * @param vgpuTypeName Pointer to buffer to return name + * @param size Size of buffer + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuTypeId is invalid, or \a name is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a size is too small + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuTypeGetName(nvmlVgpuTypeId_t vgpuTypeId, char *vgpuTypeName, unsigned int *size); + +/** + * Retrieve the GPU Instance Profile ID for the given vGPU type ID. + * The API will return a valid GPU Instance Profile ID for the MIG capable vGPU types, else INVALID_GPU_INSTANCE_PROFILE_ID is + * returned. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuTypeId Handle to vGPU type + * @param gpuInstanceProfileId GPU Instance Profile ID + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_NOT_SUPPORTED if \a device is not in vGPU Host virtualization mode + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuTypeId is invalid, or \a gpuInstanceProfileId is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuTypeGetGpuInstanceProfileId(nvmlVgpuTypeId_t vgpuTypeId, unsigned int *gpuInstanceProfileId); + +/** + * Retrieve the device ID of a vGPU type. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuTypeId Handle to vGPU type + * @param deviceID Device ID and vendor ID of the device contained in single 32 bit value + * @param subsystemID Subsytem ID and subsytem vendor ID of the device contained in single 32 bit value + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuTypeId is invalid, or \a deviceId or \a subsystemID are NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuTypeGetDeviceID(nvmlVgpuTypeId_t vgpuTypeId, unsigned long long *deviceID, unsigned long long *subsystemID); + +/** + * Retrieve the vGPU framebuffer size in bytes. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuTypeId Handle to vGPU type + * @param fbSize Pointer to framebuffer size in bytes + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuTypeId is invalid, or \a fbSize is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuTypeGetFramebufferSize(nvmlVgpuTypeId_t vgpuTypeId, unsigned long long *fbSize); + +/** + * Retrieve count of vGPU's supported display heads. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuTypeId Handle to vGPU type + * @param numDisplayHeads Pointer to number of display heads + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuTypeId is invalid, or \a numDisplayHeads is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuTypeGetNumDisplayHeads(nvmlVgpuTypeId_t vgpuTypeId, unsigned int *numDisplayHeads); + +/** + * Retrieve vGPU display head's maximum supported resolution. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuTypeId Handle to vGPU type + * @param displayIndex Zero-based index of display head + * @param xdim Pointer to maximum number of pixels in X dimension + * @param ydim Pointer to maximum number of pixels in Y dimension + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuTypeId is invalid, or \a xdim or \a ydim are NULL, or \a displayIndex + * is out of range. + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuTypeGetResolution(nvmlVgpuTypeId_t vgpuTypeId, unsigned int displayIndex, unsigned int *xdim, unsigned int *ydim); + +/** + * Retrieve license requirements for a vGPU type + * + * The license type and version required to run the specified vGPU type is returned as an alphanumeric string, in the form + * ",", for example "GRID-Virtual-PC,2.0". If a vGPU is runnable with* more than one type of license, + * the licenses are delimited by a semicolon, for example "GRID-Virtual-PC,2.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0". + * + * The total length of the returned string will not exceed 128 characters, including the NUL terminator. + * See \ref nvmlVgpuConstants::NVML_GRID_LICENSE_BUFFER_SIZE. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuTypeId Handle to vGPU type + * @param vgpuTypeLicenseString Pointer to buffer to return license info + * @param size Size of \a vgpuTypeLicenseString buffer + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuTypeId is invalid, or \a vgpuTypeLicenseString is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a size is too small + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuTypeGetLicense(nvmlVgpuTypeId_t vgpuTypeId, char *vgpuTypeLicenseString, unsigned int size); + +/** + * Retrieve the static frame rate limit value of the vGPU type + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuTypeId Handle to vGPU type + * @param frameRateLimit Reference to return the frame rate limit value + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_NOT_SUPPORTED if frame rate limiter is turned off for the vGPU type + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuTypeId is invalid, or \a frameRateLimit is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuTypeGetFrameRateLimit(nvmlVgpuTypeId_t vgpuTypeId, unsigned int *frameRateLimit); + +/** + * Retrieve the maximum number of vGPU instances creatable on a device for given vGPU type + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param vgpuTypeId Handle to vGPU type + * @param vgpuInstanceCount Pointer to get the max number of vGPU instances + * that can be created on a deicve for given vgpuTypeId + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuTypeId is invalid or is not supported on target device, + * or \a vgpuInstanceCount is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuTypeGetMaxInstances(nvmlDevice_t device, nvmlVgpuTypeId_t vgpuTypeId, unsigned int *vgpuInstanceCount); + +/** + * Retrieve the maximum number of vGPU instances supported per VM for given vGPU type + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuTypeId Handle to vGPU type + * @param vgpuInstanceCountPerVm Pointer to get the max number of vGPU instances supported per VM for given \a vgpuTypeId + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuTypeId is invalid, or \a vgpuInstanceCountPerVm is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuTypeGetMaxInstancesPerVm(nvmlVgpuTypeId_t vgpuTypeId, unsigned int *vgpuInstanceCountPerVm); + +/** + * Retrieve the active vGPU instances on a device. + * + * An array of active vGPU instances is returned in the caller-supplied buffer pointed at by \a vgpuInstances. The + * array elememt count is passed in \a vgpuCount, and \a vgpuCount is used to return the number of vGPU instances + * written to the buffer. + * + * If the supplied buffer is not large enough to accomodate the vGPU instance array, the function returns + * NVML_ERROR_INSUFFICIENT_SIZE, with the element count of nvmlVgpuInstance_t array required in \a vgpuCount. + * To query the number of active vGPU instances, call this function with *vgpuCount = 0. The code will return + * NVML_ERROR_INSUFFICIENT_SIZE, or NVML_SUCCESS if no vGPU Types are supported. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param vgpuCount Pointer which passes in the array size as well as get + * back the number of types + * @param vgpuInstances Pointer to array in which to return list of vGPU instances + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a vgpuCount is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a size is too small + * - \ref NVML_ERROR_NOT_SUPPORTED if vGPU is not supported by the device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetActiveVgpus(nvmlDevice_t device, unsigned int *vgpuCount, nvmlVgpuInstance_t *vgpuInstances); + +/** + * Retrieve the VM ID associated with a vGPU instance. + * + * The VM ID is returned as a string, not exceeding 80 characters in length (including the NUL terminator). + * See \ref nvmlConstants::NVML_DEVICE_UUID_BUFFER_SIZE. + * + * The format of the VM ID varies by platform, and is indicated by the type identifier returned in \a vmIdType. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuInstance Identifier of the target vGPU instance + * @param vmId Pointer to caller-supplied buffer to hold VM ID + * @param size Size of buffer in bytes + * @param vmIdType Pointer to hold VM ID type + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vmId or \a vmIdType is NULL, or \a vgpuInstance is 0 + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a size is too small + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetVmID(nvmlVgpuInstance_t vgpuInstance, char *vmId, unsigned int size, nvmlVgpuVmIdType_t *vmIdType); + +/** + * Retrieve the UUID of a vGPU instance. + * + * The UUID is a globally unique identifier associated with the vGPU, and is returned as a 5-part hexadecimal string, + * not exceeding 80 characters in length (including the NULL terminator). + * See \ref nvmlConstants::NVML_DEVICE_UUID_BUFFER_SIZE. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuInstance Identifier of the target vGPU instance + * @param uuid Pointer to caller-supplied buffer to hold vGPU UUID + * @param size Size of buffer in bytes + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a uuid is NULL + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a size is too small + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetUUID(nvmlVgpuInstance_t vgpuInstance, char *uuid, unsigned int size); + +/** + * Retrieve the NVIDIA driver version installed in the VM associated with a vGPU. + * + * The version is returned as an alphanumeric string in the caller-supplied buffer \a version. The length of the version + * string will not exceed 80 characters in length (including the NUL terminator). + * See \ref nvmlConstants::NVML_SYSTEM_DRIVER_VERSION_BUFFER_SIZE. + * + * nvmlVgpuInstanceGetVmDriverVersion() may be called at any time for a vGPU instance. The guest VM driver version is + * returned as "Not Available" if no NVIDIA driver is installed in the VM, or the VM has not yet booted to the point where the + * NVIDIA driver is loaded and initialized. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuInstance Identifier of the target vGPU instance + * @param version Caller-supplied buffer to return driver version string + * @param length Size of \a version buffer + * + * @return + * - \ref NVML_SUCCESS if \a version has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0 + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a length is too small + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetVmDriverVersion(nvmlVgpuInstance_t vgpuInstance, char* version, unsigned int length); + +/** + * Retrieve the framebuffer usage in bytes. + * + * Framebuffer usage is the amont of vGPU framebuffer memory that is currently in use by the VM. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuInstance The identifier of the target instance + * @param fbUsage Pointer to framebuffer usage in bytes + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a fbUsage is NULL + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetFbUsage(nvmlVgpuInstance_t vgpuInstance, unsigned long long *fbUsage); + +/** + * @deprecated Use \ref nvmlVgpuInstanceGetLicenseInfo_v2. + * + * Retrieve the current licensing state of the vGPU instance. + * + * If the vGPU is currently licensed, \a licensed is set to 1, otherwise it is set to 0. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuInstance Identifier of the target vGPU instance + * @param licensed Reference to return the licensing status + * + * @return + * - \ref NVML_SUCCESS if \a licensed has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a licensed is NULL + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetLicenseStatus(nvmlVgpuInstance_t vgpuInstance, unsigned int *licensed); + +/** + * Retrieve the vGPU type of a vGPU instance. + * + * Returns the vGPU type ID of vgpu assigned to the vGPU instance. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuInstance Identifier of the target vGPU instance + * @param vgpuTypeId Reference to return the vgpuTypeId + * + * @return + * - \ref NVML_SUCCESS if \a vgpuTypeId has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a vgpuTypeId is NULL + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetType(nvmlVgpuInstance_t vgpuInstance, nvmlVgpuTypeId_t *vgpuTypeId); + +/** + * Retrieve the frame rate limit set for the vGPU instance. + * + * Returns the value of the frame rate limit set for the vGPU instance + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuInstance Identifier of the target vGPU instance + * @param frameRateLimit Reference to return the frame rate limit + * + * @return + * - \ref NVML_SUCCESS if \a frameRateLimit has been set + * - \ref NVML_ERROR_NOT_SUPPORTED if frame rate limiter is turned off for the vGPU type + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a frameRateLimit is NULL + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetFrameRateLimit(nvmlVgpuInstance_t vgpuInstance, unsigned int *frameRateLimit); + +/** + * Retrieve the current ECC mode of vGPU instance. + * + * @param vgpuInstance The identifier of the target vGPU instance + * @param eccMode Reference in which to return the current ECC mode + * + * @return + * - \ref NVML_SUCCESS if the vgpuInstance's ECC mode has been successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a mode is NULL + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_NOT_SUPPORTED if the vGPU doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetEccMode(nvmlVgpuInstance_t vgpuInstance, nvmlEnableState_t *eccMode); + +/** + * Retrieve the encoder capacity of a vGPU instance, as a percentage of maximum encoder capacity with valid values in the range 0-100. + * + * For Maxwell &tm; or newer fully supported devices. + * + * @param vgpuInstance Identifier of the target vGPU instance + * @param encoderCapacity Reference to an unsigned int for the encoder capacity + * + * @return + * - \ref NVML_SUCCESS if \a encoderCapacity has been retrived + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a encoderQueryType is invalid + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetEncoderCapacity(nvmlVgpuInstance_t vgpuInstance, unsigned int *encoderCapacity); + +/** + * Set the encoder capacity of a vGPU instance, as a percentage of maximum encoder capacity with valid values in the range 0-100. + * + * For Maxwell &tm; or newer fully supported devices. + * + * @param vgpuInstance Identifier of the target vGPU instance + * @param encoderCapacity Unsigned int for the encoder capacity value + * + * @return + * - \ref NVML_SUCCESS if \a encoderCapacity has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a encoderCapacity is out of range of 0-100. + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceSetEncoderCapacity(nvmlVgpuInstance_t vgpuInstance, unsigned int encoderCapacity); + +/** + * Retrieves the current encoder statistics of a vGPU Instance + * + * For Maxwell &tm; or newer fully supported devices. + * + * @param vgpuInstance Identifier of the target vGPU instance + * @param sessionCount Reference to an unsigned int for count of active encoder sessions + * @param averageFps Reference to an unsigned int for trailing average FPS of all active sessions + * @param averageLatency Reference to an unsigned int for encode latency in microseconds + * + * @return + * - \ref NVML_SUCCESS if \a sessionCount, \a averageFps and \a averageLatency is fetched + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a sessionCount , or \a averageFps or \a averageLatency is NULL + * or \a vgpuInstance is 0. + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetEncoderStats(nvmlVgpuInstance_t vgpuInstance, unsigned int *sessionCount, + unsigned int *averageFps, unsigned int *averageLatency); + +/** + * Retrieves information about all active encoder sessions on a vGPU Instance. + * + * An array of active encoder sessions is returned in the caller-supplied buffer pointed at by \a sessionInfo. The + * array element count is passed in \a sessionCount, and \a sessionCount is used to return the number of sessions + * written to the buffer. + * + * If the supplied buffer is not large enough to accomodate the active session array, the function returns + * NVML_ERROR_INSUFFICIENT_SIZE, with the element count of nvmlEncoderSessionInfo_t array required in \a sessionCount. + * To query the number of active encoder sessions, call this function with *sessionCount = 0. The code will return + * NVML_SUCCESS with number of active encoder sessions updated in *sessionCount. + * + * For Maxwell &tm; or newer fully supported devices. + * + * @param vgpuInstance Identifier of the target vGPU instance + * @param sessionCount Reference to caller supplied array size, and returns + * the number of sessions. + * @param sessionInfo Reference to caller supplied array in which the list + * of session information us returned. + * + * @return + * - \ref NVML_SUCCESS if \a sessionInfo is fetched + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a sessionCount is too small, array element count is + returned in \a sessionCount + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a sessionCount is NULL, or \a vgpuInstance is 0. + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetEncoderSessions(nvmlVgpuInstance_t vgpuInstance, unsigned int *sessionCount, nvmlEncoderSessionInfo_t *sessionInfo); + +/** +* Retrieves the active frame buffer capture sessions statistics of a vGPU Instance +* +* For Maxwell &tm; or newer fully supported devices. +* +* @param vgpuInstance Identifier of the target vGPU instance +* @param fbcStats Reference to nvmlFBCStats_t structure contianing NvFBC stats +* +* @return +* - \ref NVML_SUCCESS if \a fbcStats is fetched +* - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized +* - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a fbcStats is NULL +* - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system +* - \ref NVML_ERROR_UNKNOWN on any unexpected error +*/ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetFBCStats(nvmlVgpuInstance_t vgpuInstance, nvmlFBCStats_t *fbcStats); + +/** +* Retrieves information about active frame buffer capture sessions on a vGPU Instance. +* +* An array of active FBC sessions is returned in the caller-supplied buffer pointed at by \a sessionInfo. The +* array element count is passed in \a sessionCount, and \a sessionCount is used to return the number of sessions +* written to the buffer. +* +* If the supplied buffer is not large enough to accomodate the active session array, the function returns +* NVML_ERROR_INSUFFICIENT_SIZE, with the element count of nvmlFBCSessionInfo_t array required in \a sessionCount. +* To query the number of active FBC sessions, call this function with *sessionCount = 0. The code will return +* NVML_SUCCESS with number of active FBC sessions updated in *sessionCount. +* +* For Maxwell &tm; or newer fully supported devices. +* +* @note hResolution, vResolution, averageFPS and averageLatency data for a FBC session returned in \a sessionInfo may +* be zero if there are no new frames captured since the session started. +* +* @param vgpuInstance Identifier of the target vGPU instance +* @param sessionCount Reference to caller supplied array size, and returns the number of sessions. +* @param sessionInfo Reference in which to return the session information +* +* @return +* - \ref NVML_SUCCESS if \a sessionInfo is fetched +* - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized +* - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a sessionCount is NULL. +* - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system +* - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a sessionCount is too small, array element count is returned in \a sessionCount +* - \ref NVML_ERROR_UNKNOWN on any unexpected error +*/ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetFBCSessions(nvmlVgpuInstance_t vgpuInstance, unsigned int *sessionCount, nvmlFBCSessionInfo_t *sessionInfo); + +/** +* Retrieve the GPU Instance ID for the given vGPU Instance. +* The API will return a valid GPU Instance ID for MIG backed vGPU Instance, else INVALID_GPU_INSTANCE_ID is returned. +* +* For Kepler &tm; or newer fully supported devices. +* +* @param vgpuInstance Identifier of the target vGPU instance +* @param gpuInstanceId GPU Instance ID +* +* @return +* - \ref NVML_SUCCESS successful completion +* - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized +* - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a gpuInstanceId is NULL. +* - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system +* - \ref NVML_ERROR_UNKNOWN on any unexpected error +*/ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetGpuInstanceId(nvmlVgpuInstance_t vgpuInstance, unsigned int *gpuInstanceId); + +/** +* Retrieves the PCI Id of the given vGPU Instance i.e. the PCI Id of the GPU as seen inside the VM. +* +* The vGPU PCI id is returned as "00000000:00:00.0" if NVIDIA driver is not installed on the vGPU instance. +* +* @param vgpuInstance Identifier of the target vGPU instance +* @param vgpuPciId Caller-supplied buffer to return vGPU PCI Id string +* @param length Size of the vgpuPciId buffer +* +* @return +* - \ref NVML_SUCCESS if vGPU PCI Id is sucessfully retrieved +* - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized +* - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a vgpuPciId is NULL +* - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system +* - \ref NVML_ERROR_DRIVER_NOT_LOADED if NVIDIA driver is not running on the vGPU instance +* - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a length is too small, \a length is set to required length +* - \ref NVML_ERROR_UNKNOWN on any unexpected error +*/ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetGpuPciId(nvmlVgpuInstance_t vgpuInstance, char *vgpuPciId, unsigned int *length); + +/** +* Retrieve the requested capability for a given vGPU type. Refer to the \a nvmlVgpuCapability_t structure +* for the specific capabilities that can be queried. The return value in \a capResult should be treated as +* a boolean, with a non-zero value indicating that the capability is supported. +* +* For Maxwell &tm; or newer fully supported devices. +* +* @param vgpuTypeId Handle to vGPU type +* @param capability Specifies the \a nvmlVgpuCapability_t to be queried +* @param capResult A boolean for the queried capability indicating that feature is supported +* +* @return +* - \ref NVML_SUCCESS successful completion +* - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized +* - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuTypeId is invalid, or \a capability is invalid, or \a capResult is NULL +* - \ref NVML_ERROR_UNKNOWN on any unexpected error +*/ +nvmlReturn_t DECLDIR nvmlVgpuTypeGetCapabilities(nvmlVgpuTypeId_t vgpuTypeId, nvmlVgpuCapability_t capability, unsigned int *capResult); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvml vGPU Migration + * This chapter describes operations that are associated with vGPU Migration. + * @{ + */ +/***************************************************************************************************/ + +/** + * Structure representing range of vGPU versions. + */ +typedef struct nvmlVgpuVersion_st +{ + unsigned int minVersion; //!< Minimum vGPU version. + unsigned int maxVersion; //!< Maximum vGPU version. +} nvmlVgpuVersion_t; + +/** + * vGPU metadata structure. + */ +typedef struct nvmlVgpuMetadata_st +{ + unsigned int version; //!< Current version of the structure + unsigned int revision; //!< Current revision of the structure + nvmlVgpuGuestInfoState_t guestInfoState; //!< Current state of Guest-dependent fields + char guestDriverVersion[NVML_SYSTEM_DRIVER_VERSION_BUFFER_SIZE]; //!< Version of driver installed in guest + char hostDriverVersion[NVML_SYSTEM_DRIVER_VERSION_BUFFER_SIZE]; //!< Version of driver installed in host + unsigned int reserved[6]; //!< Reserved for internal use + unsigned int vgpuVirtualizationCaps; //!< vGPU virtualizaion capabilities bitfileld + unsigned int guestVgpuVersion; //!< vGPU version of guest driver + unsigned int opaqueDataSize; //!< Size of opaque data field in bytes + char opaqueData[4]; //!< Opaque data +} nvmlVgpuMetadata_t; + +/** + * Physical GPU metadata structure + */ +typedef struct nvmlVgpuPgpuMetadata_st +{ + unsigned int version; //!< Current version of the structure + unsigned int revision; //!< Current revision of the structure + char hostDriverVersion[NVML_SYSTEM_DRIVER_VERSION_BUFFER_SIZE]; //!< Host driver version + unsigned int pgpuVirtualizationCaps; //!< Pgpu virtualizaion capabilities bitfileld + unsigned int reserved[5]; //!< Reserved for internal use + nvmlVgpuVersion_t hostSupportedVgpuRange; //!< vGPU version range supported by host driver + unsigned int opaqueDataSize; //!< Size of opaque data field in bytes + char opaqueData[4]; //!< Opaque data +} nvmlVgpuPgpuMetadata_t; + +/** + * vGPU VM compatibility codes + */ +typedef enum nvmlVgpuVmCompatibility_enum +{ + NVML_VGPU_VM_COMPATIBILITY_NONE = 0x0, //!< vGPU is not runnable + NVML_VGPU_VM_COMPATIBILITY_COLD = 0x1, //!< vGPU is runnable from a cold / powered-off state (ACPI S5) + NVML_VGPU_VM_COMPATIBILITY_HIBERNATE = 0x2, //!< vGPU is runnable from a hibernated state (ACPI S4) + NVML_VGPU_VM_COMPATIBILITY_SLEEP = 0x4, //!< vGPU is runnable from a sleeped state (ACPI S3) + NVML_VGPU_VM_COMPATIBILITY_LIVE = 0x8 //!< vGPU is runnable from a live/paused (ACPI S0) +} nvmlVgpuVmCompatibility_t; + +/** + * vGPU-pGPU compatibility limit codes + */ +typedef enum nvmlVgpuPgpuCompatibilityLimitCode_enum +{ + NVML_VGPU_COMPATIBILITY_LIMIT_NONE = 0x0, //!< Compatibility is not limited. + NVML_VGPU_COMPATIBILITY_LIMIT_HOST_DRIVER = 0x1, //!< ompatibility is limited by host driver version. + NVML_VGPU_COMPATIBILITY_LIMIT_GUEST_DRIVER = 0x2, //!< Compatibility is limited by guest driver version. + NVML_VGPU_COMPATIBILITY_LIMIT_GPU = 0x4, //!< Compatibility is limited by GPU hardware. + NVML_VGPU_COMPATIBILITY_LIMIT_OTHER = 0x80000000 //!< Compatibility is limited by an undefined factor. +} nvmlVgpuPgpuCompatibilityLimitCode_t; + +/** + * vGPU-pGPU compatibility structure + */ +typedef struct nvmlVgpuPgpuCompatibility_st +{ + nvmlVgpuVmCompatibility_t vgpuVmCompatibility; //!< Compatibility of vGPU VM. See \ref nvmlVgpuVmCompatibility_t + nvmlVgpuPgpuCompatibilityLimitCode_t compatibilityLimitCode; //!< Limiting factor for vGPU-pGPU compatibility. See \ref nvmlVgpuPgpuCompatibilityLimitCode_t +} nvmlVgpuPgpuCompatibility_t; + +/** + * Returns vGPU metadata structure for a running vGPU. The structure contains information about the vGPU and its associated VM + * such as the currently installed NVIDIA guest driver version, together with host driver version and an opaque data section + * containing internal state. + * + * nvmlVgpuInstanceGetMetadata() may be called at any time for a vGPU instance. Some fields in the returned structure are + * dependent on information obtained from the guest VM, which may not yet have reached a state where that information + * is available. The current state of these dependent fields is reflected in the info structure's \ref nvmlVgpuGuestInfoState_t field. + * + * The VMM may choose to read and save the vGPU's VM info as persistent metadata associated with the VM, and provide + * it to Virtual GPU Manager when creating a vGPU for subsequent instances of the VM. + * + * The caller passes in a buffer via \a vgpuMetadata, with the size of the buffer in \a bufferSize. If the vGPU Metadata structure + * is too large to fit in the supplied buffer, the function returns NVML_ERROR_INSUFFICIENT_SIZE with the size needed + * in \a bufferSize. + * + * @param vgpuInstance vGPU instance handle + * @param vgpuMetadata Pointer to caller-supplied buffer into which vGPU metadata is written + * @param bufferSize Size of vgpuMetadata buffer + * + * @return + * - \ref NVML_SUCCESS vGPU metadata structure was successfully returned + * - \ref NVML_ERROR_INSUFFICIENT_SIZE vgpuMetadata buffer is too small, required size is returned in \a bufferSize + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a bufferSize is NULL or \a vgpuInstance is 0; if \a vgpuMetadata is NULL and the value of \a bufferSize is not 0. + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetMetadata(nvmlVgpuInstance_t vgpuInstance, nvmlVgpuMetadata_t *vgpuMetadata, unsigned int *bufferSize); + +/** + * Returns a vGPU metadata structure for the physical GPU indicated by \a device. The structure contains information about + * the GPU and the currently installed NVIDIA host driver version that's controlling it, together with an opaque data section + * containing internal state. + * + * The caller passes in a buffer via \a pgpuMetadata, with the size of the buffer in \a bufferSize. If the \a pgpuMetadata + * structure is too large to fit in the supplied buffer, the function returns NVML_ERROR_INSUFFICIENT_SIZE with the size needed + * in \a bufferSize. + * + * @param device The identifier of the target device + * @param pgpuMetadata Pointer to caller-supplied buffer into which \a pgpuMetadata is written + * @param bufferSize Pointer to size of \a pgpuMetadata buffer + * + * @return + * - \ref NVML_SUCCESS GPU metadata structure was successfully returned + * - \ref NVML_ERROR_INSUFFICIENT_SIZE pgpuMetadata buffer is too small, required size is returned in \a bufferSize + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a bufferSize is NULL or \a device is invalid; if \a pgpuMetadata is NULL and the value of \a bufferSize is not 0. + * - \ref NVML_ERROR_NOT_SUPPORTED vGPU is not supported by the system + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetVgpuMetadata(nvmlDevice_t device, nvmlVgpuPgpuMetadata_t *pgpuMetadata, unsigned int *bufferSize); + +/** + * Takes a vGPU instance metadata structure read from \ref nvmlVgpuInstanceGetMetadata(), and a vGPU metadata structure for a + * physical GPU read from \ref nvmlDeviceGetVgpuMetadata(), and returns compatibility information of the vGPU instance and the + * physical GPU. + * + * The caller passes in a buffer via \a compatibilityInfo, into which a compatibility information structure is written. The + * structure defines the states in which the vGPU / VM may be booted on the physical GPU. If the vGPU / VM compatibility + * with the physical GPU is limited, a limit code indicates the factor limiting compability. + * (see \ref nvmlVgpuPgpuCompatibilityLimitCode_t for details). + * + * Note: vGPU compatibility does not take into account dynamic capacity conditions that may limit a system's ability to + * boot a given vGPU or associated VM. + * + * @param vgpuMetadata Pointer to caller-supplied vGPU metadata structure + * @param pgpuMetadata Pointer to caller-supplied GPU metadata structure + * @param compatibilityInfo Pointer to caller-supplied buffer to hold compatibility info + * + * @return + * - \ref NVML_SUCCESS vGPU metadata structure was successfully returned + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuMetadata or \a pgpuMetadata or \a bufferSize are NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlGetVgpuCompatibility(nvmlVgpuMetadata_t *vgpuMetadata, nvmlVgpuPgpuMetadata_t *pgpuMetadata, nvmlVgpuPgpuCompatibility_t *compatibilityInfo); + +/** + * Returns the properties of the physical GPU indicated by the device in an ascii-encoded string format. + * + * The caller passes in a buffer via \a pgpuMetadata, with the size of the buffer in \a bufferSize. If the + * string is too large to fit in the supplied buffer, the function returns NVML_ERROR_INSUFFICIENT_SIZE with the size needed + * in \a bufferSize. + * + * @param device The identifier of the target device + * @param pgpuMetadata Pointer to caller-supplied buffer into which \a pgpuMetadata is written + * @param bufferSize Pointer to size of \a pgpuMetadata buffer + * + * @return + * - \ref NVML_SUCCESS GPU metadata structure was successfully returned + * - \ref NVML_ERROR_INSUFFICIENT_SIZE \a pgpuMetadata buffer is too small, required size is returned in \a bufferSize + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a bufferSize is NULL or \a device is invalid; if \a pgpuMetadata is NULL and the value of \a bufferSize is not 0. + * - \ref NVML_ERROR_NOT_SUPPORTED if vGPU is not supported by the system + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPgpuMetadataString(nvmlDevice_t device, char *pgpuMetadata, unsigned int *bufferSize); + +/** + * Returns the vGPU Software scheduler logs. + * \a pSchedulerLog points to a caller-allocated structure to contain the logs. The number of elements returned will + * never exceed \a NVML_SCHEDULER_SW_MAX_LOG_ENTRIES. + * + * To get the entire logs, call the function atleast 5 times a second. + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target \a device + * @param pSchedulerLog Reference in which \a pSchedulerLog is written + * + * @return + * - \ref NVML_SUCCESS vGPU scheduler logs were successfully obtained + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a pSchedulerLog is NULL or \a device is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED The API is not supported in current state or \a device not in vGPU host mode + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetVgpuSchedulerLog(nvmlDevice_t device, nvmlVgpuSchedulerLog_t *pSchedulerLog); + +/** + * Returns the vGPU scheduler state. + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target \a device + * @param pSchedulerState Reference in which \a pSchedulerState is returned + * + * @return + * - \ref NVML_SUCCESS vGPU scheduler state is successfully obtained + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a pSchedulerState is NULL or \a device is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED The API is not supported in current state or \a device not in vGPU host mode + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetVgpuSchedulerState(nvmlDevice_t device, nvmlVgpuSchedulerGetState_t *pSchedulerState); + +/** + * Sets the vGPU scheduler state. + * + * For Pascal &tm; or newer fully supported devices. + * + * The scheduler state change won’t persist across module load/unload. + * Scheduler state and params will be allowed to set only when no VM is running. + * In \a nvmlVgpuSchedulerSetState_t, IFF enableARRMode=1 then + * provide avgFactorForARR and frequency as input. If enableARRMode is disabled + * then provide timeslice as input. + * + * @param device The identifier of the target \a device + * @param pSchedulerState vGPU \a pSchedulerState to set + * + * @return + * - \ref NVML_SUCCESS vGPU scheduler state has been successfully set + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a pSchedulerState is NULL or \a device is invalid + * - \ref NVML_ERROR_RESET_REQUIRED if setting \a pSchedulerState failed with fatal error, + * reboot is required to overcome from this error. + * - \ref NVML_ERROR_NOT_SUPPORTED The API is not supported in current state or \a device not in vGPU host mode + * or if any vGPU instance currently exists on the \a device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceSetVgpuSchedulerState(nvmlDevice_t device, nvmlVgpuSchedulerSetState_t *pSchedulerState); + +/** + * Returns the vGPU scheduler capabilities. + * The list of supported vGPU schedulers returned in \a nvmlVgpuSchedulerCapabilities_t is from + * the NVML_VGPU_SCHEDULER_POLICY_*. This list enumerates the supported scheduler policies + * if the engine is Graphics type. + * The other values in \a nvmlVgpuSchedulerCapabilities_t are also applicable if the engine is + * Graphics type. For other engine types, it is BEST EFFORT policy. + * If ARR is supported and enabled, scheduling frequency and averaging factor are applicable + * else timeSlice is applicable. + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target \a device + * @param pCapabilities Reference in which \a pCapabilities is written + * + * @return + * - \ref NVML_SUCCESS vGPU scheduler capabilities were successfully obtained + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a pCapabilities is NULL or \a device is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED The API is not supported in current state or \a device not in vGPU host mode + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetVgpuSchedulerCapabilities(nvmlDevice_t device, nvmlVgpuSchedulerCapabilities_t *pCapabilities); + +/* + * Virtual GPU (vGPU) version + * + * The NVIDIA vGPU Manager and the guest drivers are tagged with a range of supported vGPU versions. This determines the range of NVIDIA guest driver versions that + * are compatible for vGPU feature support with a given NVIDIA vGPU Manager. For vGPU feature support, the range of supported versions for the NVIDIA vGPU Manager + * and the guest driver must overlap. Otherwise, the guest driver fails to load in the VM. + * + * When the NVIDIA guest driver loads, either when the VM is booted or when the driver is installed or upgraded, a negotiation occurs between the guest driver + * and the NVIDIA vGPU Manager to select the highest mutually compatible vGPU version. The negotiated vGPU version stays the same across VM migration. + */ + +/** + * Query the ranges of supported vGPU versions. + * + * This function gets the linear range of supported vGPU versions that is preset for the NVIDIA vGPU Manager and the range set by an administrator. + * If the preset range has not been overridden by \ref nvmlSetVgpuVersion, both ranges are the same. + * + * The caller passes pointers to the following \ref nvmlVgpuVersion_t structures, into which the NVIDIA vGPU Manager writes the ranges: + * 1. \a supported structure that represents the preset range of vGPU versions supported by the NVIDIA vGPU Manager. + * 2. \a current structure that represents the range of supported vGPU versions set by an administrator. By default, this range is the same as the preset range. + * + * @param supported Pointer to the structure in which the preset range of vGPU versions supported by the NVIDIA vGPU Manager is written + * @param current Pointer to the structure in which the range of supported vGPU versions set by an administrator is written + * + * @return + * - \ref NVML_SUCCESS The vGPU version range structures were successfully obtained. + * - \ref NVML_ERROR_NOT_SUPPORTED The API is not supported. + * - \ref NVML_ERROR_INVALID_ARGUMENT The \a supported parameter or the \a current parameter is NULL. + * - \ref NVML_ERROR_UNKNOWN An error occurred while the data was being fetched. + */ +nvmlReturn_t DECLDIR nvmlGetVgpuVersion(nvmlVgpuVersion_t *supported, nvmlVgpuVersion_t *current); + +/** + * Override the preset range of vGPU versions supported by the NVIDIA vGPU Manager with a range set by an administrator. + * + * This function configures the NVIDIA vGPU Manager with a range of supported vGPU versions set by an administrator. This range must be a subset of the + * preset range that the NVIDIA vGPU Manager supports. The custom range set by an administrator takes precedence over the preset range and is advertised to + * the guest VM for negotiating the vGPU version. See \ref nvmlGetVgpuVersion for details of how to query the preset range of versions supported. + * + * This function takes a pointer to vGPU version range structure \ref nvmlVgpuVersion_t as input to override the preset vGPU version range that the NVIDIA vGPU Manager supports. + * + * After host system reboot or driver reload, the range of supported versions reverts to the range that is preset for the NVIDIA vGPU Manager. + * + * @note 1. The range set by the administrator must be a subset of the preset range that the NVIDIA vGPU Manager supports. Otherwise, an error is returned. + * 2. If the range of supported guest driver versions does not overlap the range set by the administrator, the guest driver fails to load. + * 3. If the range of supported guest driver versions overlaps the range set by the administrator, the guest driver will load with a negotiated + * vGPU version that is the maximum value in the overlapping range. + * 4. No VMs must be running on the host when this function is called. If a VM is running on the host, the call to this function fails. + * + * @param vgpuVersion Pointer to a caller-supplied range of supported vGPU versions. + * + * @return + * - \ref NVML_SUCCESS The preset range of supported vGPU versions was successfully overridden. + * - \ref NVML_ERROR_NOT_SUPPORTED The API is not supported. + * - \ref NVML_ERROR_IN_USE The range was not overridden because a VM is running on the host. + * - \ref NVML_ERROR_INVALID_ARGUMENT The \a vgpuVersion parameter specifies a range that is outside the range supported by the NVIDIA vGPU Manager or if \a vgpuVersion is NULL. + */ +nvmlReturn_t DECLDIR nvmlSetVgpuVersion(nvmlVgpuVersion_t *vgpuVersion); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlUtil vGPU Utilization and Accounting + * This chapter describes operations that are associated with vGPU Utilization and Accounting. + * @{ + */ +/***************************************************************************************************/ + +/** + * Retrieves current utilization for vGPUs on a physical GPU (device). + * + * For Kepler &tm; or newer fully supported devices. + * + * Reads recent utilization of GPU SM (3D/Compute), framebuffer, video encoder, and video decoder for vGPU instances running + * on a device. Utilization values are returned as an array of utilization sample structures in the caller-supplied buffer + * pointed at by \a utilizationSamples. One utilization sample structure is returned per vGPU instance, and includes the + * CPU timestamp at which the samples were recorded. Individual utilization values are returned as "unsigned int" values + * in nvmlValue_t unions. The function sets the caller-supplied \a sampleValType to NVML_VALUE_TYPE_UNSIGNED_INT to + * indicate the returned value type. + * + * To read utilization values, first determine the size of buffer required to hold the samples by invoking the function with + * \a utilizationSamples set to NULL. The function will return NVML_ERROR_INSUFFICIENT_SIZE, with the current vGPU instance + * count in \a vgpuInstanceSamplesCount, or NVML_SUCCESS if the current vGPU instance count is zero. The caller should allocate + * a buffer of size vgpuInstanceSamplesCount * sizeof(nvmlVgpuInstanceUtilizationSample_t). Invoke the function again with + * the allocated buffer passed in \a utilizationSamples, and \a vgpuInstanceSamplesCount set to the number of entries the + * buffer is sized for. + * + * On successful return, the function updates \a vgpuInstanceSampleCount with the number of vGPU utilization sample + * structures that were actually written. This may differ from a previously read value as vGPU instances are created or + * destroyed. + * + * lastSeenTimeStamp represents the CPU timestamp in microseconds at which utilization samples were last read. Set it to 0 + * to read utilization based on all the samples maintained by the driver's internal sample buffer. Set lastSeenTimeStamp + * to a timeStamp retrieved from a previous query to read utilization since the previous query. + * + * @param device The identifier for the target device + * @param lastSeenTimeStamp Return only samples with timestamp greater than lastSeenTimeStamp. + * @param sampleValType Pointer to caller-supplied buffer to hold the type of returned sample values + * @param vgpuInstanceSamplesCount Pointer to caller-supplied array size, and returns number of vGPU instances + * @param utilizationSamples Pointer to caller-supplied buffer in which vGPU utilization samples are returned + + * @return + * - \ref NVML_SUCCESS if utilization samples are successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a vgpuInstanceSamplesCount or \a sampleValType is + * NULL, or a sample count of 0 is passed with a non-NULL \a utilizationSamples + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if supplied \a vgpuInstanceSamplesCount is too small to return samples for all + * vGPU instances currently executing on the device + * - \ref NVML_ERROR_NOT_SUPPORTED if vGPU is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_NOT_FOUND if sample entries are not found + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetVgpuUtilization(nvmlDevice_t device, unsigned long long lastSeenTimeStamp, + nvmlValueType_t *sampleValType, unsigned int *vgpuInstanceSamplesCount, + nvmlVgpuInstanceUtilizationSample_t *utilizationSamples); + +/** + * Retrieves current utilization for processes running on vGPUs on a physical GPU (device). + * + * For Maxwell &tm; or newer fully supported devices. + * + * Reads recent utilization of GPU SM (3D/Compute), framebuffer, video encoder, and video decoder for processes running on + * vGPU instances active on a device. Utilization values are returned as an array of utilization sample structures in the + * caller-supplied buffer pointed at by \a utilizationSamples. One utilization sample structure is returned per process running + * on vGPU instances, that had some non-zero utilization during the last sample period. It includes the CPU timestamp at which + * the samples were recorded. Individual utilization values are returned as "unsigned int" values. + * + * To read utilization values, first determine the size of buffer required to hold the samples by invoking the function with + * \a utilizationSamples set to NULL. The function will return NVML_ERROR_INSUFFICIENT_SIZE, with the current vGPU instance + * count in \a vgpuProcessSamplesCount. The caller should allocate a buffer of size + * vgpuProcessSamplesCount * sizeof(nvmlVgpuProcessUtilizationSample_t). Invoke the function again with + * the allocated buffer passed in \a utilizationSamples, and \a vgpuProcessSamplesCount set to the number of entries the + * buffer is sized for. + * + * On successful return, the function updates \a vgpuSubProcessSampleCount with the number of vGPU sub process utilization sample + * structures that were actually written. This may differ from a previously read value depending on the number of processes that are active + * in any given sample period. + * + * lastSeenTimeStamp represents the CPU timestamp in microseconds at which utilization samples were last read. Set it to 0 + * to read utilization based on all the samples maintained by the driver's internal sample buffer. Set lastSeenTimeStamp + * to a timeStamp retrieved from a previous query to read utilization since the previous query. + * + * @param device The identifier for the target device + * @param lastSeenTimeStamp Return only samples with timestamp greater than lastSeenTimeStamp. + * @param vgpuProcessSamplesCount Pointer to caller-supplied array size, and returns number of processes running on vGPU instances + * @param utilizationSamples Pointer to caller-supplied buffer in which vGPU sub process utilization samples are returned + + * @return + * - \ref NVML_SUCCESS if utilization samples are successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a vgpuProcessSamplesCount or a sample count of 0 is + * passed with a non-NULL \a utilizationSamples + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if supplied \a vgpuProcessSamplesCount is too small to return samples for all + * vGPU instances currently executing on the device + * - \ref NVML_ERROR_NOT_SUPPORTED if vGPU is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_NOT_FOUND if sample entries are not found + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetVgpuProcessUtilization(nvmlDevice_t device, unsigned long long lastSeenTimeStamp, + unsigned int *vgpuProcessSamplesCount, + nvmlVgpuProcessUtilizationSample_t *utilizationSamples); +/** + * Queries the state of per process accounting mode on vGPU. + * + * For Maxwell &tm; or newer fully supported devices. + * + * @param vgpuInstance The identifier of the target vGPU instance + * @param mode Reference in which to return the current accounting mode + * + * @return + * - \ref NVML_SUCCESS if the mode has been successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a mode is NULL + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_NOT_SUPPORTED if the vGPU doesn't support this feature + * - \ref NVML_ERROR_DRIVER_NOT_LOADED if NVIDIA driver is not running on the vGPU instance + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetAccountingMode(nvmlVgpuInstance_t vgpuInstance, nvmlEnableState_t *mode); + +/** + * Queries list of processes running on vGPU that can be queried for accounting stats. The list of processes + * returned can be in running or terminated state. + * + * For Maxwell &tm; or newer fully supported devices. + * + * To just query the maximum number of processes that can be queried, call this function with *count = 0 and + * pids=NULL. The return code will be NVML_ERROR_INSUFFICIENT_SIZE, or NVML_SUCCESS if list is empty. + * + * For more details see \ref nvmlVgpuInstanceGetAccountingStats. + * + * @note In case of PID collision some processes might not be accessible before the circular buffer is full. + * + * @param vgpuInstance The identifier of the target vGPU instance + * @param count Reference in which to provide the \a pids array size, and + * to return the number of elements ready to be queried + * @param pids Reference in which to return list of process ids + * + * @return + * - \ref NVML_SUCCESS if pids were successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a count is NULL + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_NOT_SUPPORTED if the vGPU doesn't support this feature or accounting mode is disabled + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a count is too small (\a count is set to expected value) + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlVgpuInstanceGetAccountingPids + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetAccountingPids(nvmlVgpuInstance_t vgpuInstance, unsigned int *count, unsigned int *pids); + +/** + * Queries process's accounting stats. + * + * For Maxwell &tm; or newer fully supported devices. + * + * Accounting stats capture GPU utilization and other statistics across the lifetime of a process, and + * can be queried during life time of the process or after its termination. + * The time field in \ref nvmlAccountingStats_t is reported as 0 during the lifetime of the process and + * updated to actual running time after its termination. + * Accounting stats are kept in a circular buffer, newly created processes overwrite information about old + * processes. + * + * See \ref nvmlAccountingStats_t for description of each returned metric. + * List of processes that can be queried can be retrieved from \ref nvmlVgpuInstanceGetAccountingPids. + * + * @note Accounting Mode needs to be on. See \ref nvmlVgpuInstanceGetAccountingMode. + * @note Only compute and graphics applications stats can be queried. Monitoring applications stats can't be + * queried since they don't contribute to GPU utilization. + * @note In case of pid collision stats of only the latest process (that terminated last) will be reported + * + * @param vgpuInstance The identifier of the target vGPU instance + * @param pid Process Id of the target process to query stats for + * @param stats Reference in which to return the process's accounting stats + * + * @return + * - \ref NVML_SUCCESS if stats have been successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a stats is NULL + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * or \a stats is not found + * - \ref NVML_ERROR_NOT_SUPPORTED if the vGPU doesn't support this feature or accounting mode is disabled + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetAccountingStats(nvmlVgpuInstance_t vgpuInstance, unsigned int pid, nvmlAccountingStats_t *stats); + +/** + * Clears accounting information of the vGPU instance that have already terminated. + * + * For Maxwell &tm; or newer fully supported devices. + * Requires root/admin permissions. + * + * @note Accounting Mode needs to be on. See \ref nvmlVgpuInstanceGetAccountingMode. + * @note Only compute and graphics applications stats are reported and can be cleared since monitoring applications + * stats don't contribute to GPU utilization. + * + * @param vgpuInstance The identifier of the target vGPU instance + * + * @return + * - \ref NVML_SUCCESS if accounting information has been cleared + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is invalid + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_NOT_SUPPORTED if the vGPU doesn't support this feature or accounting mode is disabled + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceClearAccountingPids(nvmlVgpuInstance_t vgpuInstance); + +/** + * Query the license information of the vGPU instance. + * + * For Maxwell &tm; or newer fully supported devices. + * + * @param vgpuInstance Identifier of the target vGPU instance + * @param licenseInfo Pointer to vGPU license information structure + * + * @return + * - \ref NVML_SUCCESS if information is successfully retrieved + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a licenseInfo is NULL + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_DRIVER_NOT_LOADED if NVIDIA driver is not running on the vGPU instance + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetLicenseInfo_v2(nvmlVgpuInstance_t vgpuInstance, nvmlVgpuLicenseInfo_t *licenseInfo); +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlExcludedGpuQueries Excluded GPU Queries + * This chapter describes NVML operations that are associated with excluded GPUs. + * @{ + */ +/***************************************************************************************************/ + +/** + * Excluded GPU device information + **/ +typedef struct nvmlExcludedDeviceInfo_st +{ + nvmlPciInfo_t pciInfo; //!< The PCI information for the excluded GPU + char uuid[NVML_DEVICE_UUID_BUFFER_SIZE]; //!< The ASCII string UUID for the excluded GPU +} nvmlExcludedDeviceInfo_t; + + /** + * Retrieves the number of excluded GPU devices in the system. + * + * For all products. + * + * @param deviceCount Reference in which to return the number of excluded devices + * + * @return + * - \ref NVML_SUCCESS if \a deviceCount has been set + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a deviceCount is NULL + */ +nvmlReturn_t DECLDIR nvmlGetExcludedDeviceCount(unsigned int *deviceCount); + +/** + * Acquire the device information for an excluded GPU device, based on its index. + * + * For all products. + * + * Valid indices are derived from the \a deviceCount returned by + * \ref nvmlGetExcludedDeviceCount(). For example, if \a deviceCount is 2 the valid indices + * are 0 and 1, corresponding to GPU 0 and GPU 1. + * + * @param index The index of the target GPU, >= 0 and < \a deviceCount + * @param info Reference in which to return the device information + * + * @return + * - \ref NVML_SUCCESS if \a device has been set + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a index is invalid or \a info is NULL + * + * @see nvmlGetExcludedDeviceCount + */ +nvmlReturn_t DECLDIR nvmlGetExcludedDeviceInfoByIndex(unsigned int index, nvmlExcludedDeviceInfo_t *info); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlMultiInstanceGPU Multi Instance GPU Management + * This chapter describes NVML operations that are associated with Multi Instance GPU management. + * @{ + */ +/***************************************************************************************************/ + +/** + * Disable Multi Instance GPU mode. + */ +#define NVML_DEVICE_MIG_DISABLE 0x0 + +/** + * Enable Multi Instance GPU mode. + */ +#define NVML_DEVICE_MIG_ENABLE 0x1 + +/** + * GPU instance profiles. + * + * These macros should be passed to \ref nvmlDeviceGetGpuInstanceProfileInfo to retrieve the + * detailed information about a GPU instance such as profile ID, engine counts. + */ +#define NVML_GPU_INSTANCE_PROFILE_1_SLICE 0x0 +#define NVML_GPU_INSTANCE_PROFILE_2_SLICE 0x1 +#define NVML_GPU_INSTANCE_PROFILE_3_SLICE 0x2 +#define NVML_GPU_INSTANCE_PROFILE_4_SLICE 0x3 +#define NVML_GPU_INSTANCE_PROFILE_7_SLICE 0x4 +#define NVML_GPU_INSTANCE_PROFILE_8_SLICE 0x5 +#define NVML_GPU_INSTANCE_PROFILE_6_SLICE 0x6 +#define NVML_GPU_INSTANCE_PROFILE_1_SLICE_REV1 0x7 +#define NVML_GPU_INSTANCE_PROFILE_2_SLICE_REV1 0x8 +#define NVML_GPU_INSTANCE_PROFILE_1_SLICE_REV2 0x9 +#define NVML_GPU_INSTANCE_PROFILE_COUNT 0xA + +typedef struct nvmlGpuInstancePlacement_st +{ + unsigned int start; //!< Index of first occupied memory slice + unsigned int size; //!< Number of memory slices occupied +} nvmlGpuInstancePlacement_t; + +/** + * GPU instance profile information. + */ +typedef struct nvmlGpuInstanceProfileInfo_st +{ + unsigned int id; //!< Unique profile ID within the device + unsigned int isP2pSupported; //!< Peer-to-Peer support + unsigned int sliceCount; //!< GPU Slice count + unsigned int instanceCount; //!< GPU instance count + unsigned int multiprocessorCount; //!< Streaming Multiprocessor count + unsigned int copyEngineCount; //!< Copy Engine count + unsigned int decoderCount; //!< Decoder Engine count + unsigned int encoderCount; //!< Encoder Engine count + unsigned int jpegCount; //!< JPEG Engine count + unsigned int ofaCount; //!< OFA Engine count + unsigned long long memorySizeMB; //!< Memory size in MBytes +} nvmlGpuInstanceProfileInfo_t; + +/** + * GPU instance profile information (v2). + * + * Version 2 adds the \ref nvmlGpuInstanceProfileInfo_v2_t.version field + * to the start of the structure, and the \ref nvmlGpuInstanceProfileInfo_v2_t.name + * field to the end. This structure is not backwards-compatible with + * \ref nvmlGpuInstanceProfileInfo_t. + */ +typedef struct nvmlGpuInstanceProfileInfo_v2_st +{ + unsigned int version; //!< Structure version identifier (set to \ref nvmlGpuInstanceProfileInfo_v2) + unsigned int id; //!< Unique profile ID within the device + unsigned int isP2pSupported; //!< Peer-to-Peer support + unsigned int sliceCount; //!< GPU Slice count + unsigned int instanceCount; //!< GPU instance count + unsigned int multiprocessorCount; //!< Streaming Multiprocessor count + unsigned int copyEngineCount; //!< Copy Engine count + unsigned int decoderCount; //!< Decoder Engine count + unsigned int encoderCount; //!< Encoder Engine count + unsigned int jpegCount; //!< JPEG Engine count + unsigned int ofaCount; //!< OFA Engine count + unsigned long long memorySizeMB; //!< Memory size in MBytes + char name[NVML_DEVICE_NAME_V2_BUFFER_SIZE]; //!< Profile name +} nvmlGpuInstanceProfileInfo_v2_t; + +/** + * Version identifier value for \ref nvmlGpuInstanceProfileInfo_v2_t.version. + */ +#define nvmlGpuInstanceProfileInfo_v2 NVML_STRUCT_VERSION(GpuInstanceProfileInfo, 2) + +typedef struct nvmlGpuInstanceInfo_st +{ + nvmlDevice_t device; //!< Parent device + unsigned int id; //!< Unique instance ID within the device + unsigned int profileId; //!< Unique profile ID within the device + nvmlGpuInstancePlacement_t placement; //!< Placement for this instance +} nvmlGpuInstanceInfo_t; + +typedef struct nvmlGpuInstance_st* nvmlGpuInstance_t; + +/** + * Compute instance profiles. + * + * These macros should be passed to \ref nvmlGpuInstanceGetComputeInstanceProfileInfo to retrieve the + * detailed information about a compute instance such as profile ID, engine counts + */ +#define NVML_COMPUTE_INSTANCE_PROFILE_1_SLICE 0x0 +#define NVML_COMPUTE_INSTANCE_PROFILE_2_SLICE 0x1 +#define NVML_COMPUTE_INSTANCE_PROFILE_3_SLICE 0x2 +#define NVML_COMPUTE_INSTANCE_PROFILE_4_SLICE 0x3 +#define NVML_COMPUTE_INSTANCE_PROFILE_7_SLICE 0x4 +#define NVML_COMPUTE_INSTANCE_PROFILE_8_SLICE 0x5 +#define NVML_COMPUTE_INSTANCE_PROFILE_6_SLICE 0x6 +#define NVML_COMPUTE_INSTANCE_PROFILE_1_SLICE_REV1 0x7 +#define NVML_COMPUTE_INSTANCE_PROFILE_COUNT 0x8 + +#define NVML_COMPUTE_INSTANCE_ENGINE_PROFILE_SHARED 0x0 //!< All the engines except multiprocessors would be shared +#define NVML_COMPUTE_INSTANCE_ENGINE_PROFILE_COUNT 0x1 + +typedef struct nvmlComputeInstancePlacement_st +{ + unsigned int start; //!< Index of first occupied compute slice + unsigned int size; //!< Number of compute slices occupied +} nvmlComputeInstancePlacement_t; + +/** + * Compute instance profile information. + */ +typedef struct nvmlComputeInstanceProfileInfo_st +{ + unsigned int id; //!< Unique profile ID within the GPU instance + unsigned int sliceCount; //!< GPU Slice count + unsigned int instanceCount; //!< Compute instance count + unsigned int multiprocessorCount; //!< Streaming Multiprocessor count + unsigned int sharedCopyEngineCount; //!< Shared Copy Engine count + unsigned int sharedDecoderCount; //!< Shared Decoder Engine count + unsigned int sharedEncoderCount; //!< Shared Encoder Engine count + unsigned int sharedJpegCount; //!< Shared JPEG Engine count + unsigned int sharedOfaCount; //!< Shared OFA Engine count +} nvmlComputeInstanceProfileInfo_t; + +/** + * Compute instance profile information (v2). + * + * Version 2 adds the \ref nvmlComputeInstanceProfileInfo_v2_t.version field + * to the start of the structure, and the \ref nvmlComputeInstanceProfileInfo_v2_t.name + * field to the end. This structure is not backwards-compatible with + * \ref nvmlComputeInstanceProfileInfo_t. + */ +typedef struct nvmlComputeInstanceProfileInfo_v2_st +{ + unsigned int version; //!< Structure version identifier (set to \ref nvmlComputeInstanceProfileInfo_v2) + unsigned int id; //!< Unique profile ID within the GPU instance + unsigned int sliceCount; //!< GPU Slice count + unsigned int instanceCount; //!< Compute instance count + unsigned int multiprocessorCount; //!< Streaming Multiprocessor count + unsigned int sharedCopyEngineCount; //!< Shared Copy Engine count + unsigned int sharedDecoderCount; //!< Shared Decoder Engine count + unsigned int sharedEncoderCount; //!< Shared Encoder Engine count + unsigned int sharedJpegCount; //!< Shared JPEG Engine count + unsigned int sharedOfaCount; //!< Shared OFA Engine count + char name[NVML_DEVICE_NAME_V2_BUFFER_SIZE]; //!< Profile name +} nvmlComputeInstanceProfileInfo_v2_t; + +/** + * Version identifier value for \ref nvmlComputeInstanceProfileInfo_v2_t.version. + */ +#define nvmlComputeInstanceProfileInfo_v2 NVML_STRUCT_VERSION(ComputeInstanceProfileInfo, 2) + +typedef struct nvmlComputeInstanceInfo_st +{ + nvmlDevice_t device; //!< Parent device + nvmlGpuInstance_t gpuInstance; //!< Parent GPU instance + unsigned int id; //!< Unique instance ID within the GPU instance + unsigned int profileId; //!< Unique profile ID within the GPU instance + nvmlComputeInstancePlacement_t placement; //!< Placement for this instance within the GPU instance's compute slice range {0, sliceCount} +} nvmlComputeInstanceInfo_t; + +typedef struct nvmlComputeInstance_st* nvmlComputeInstance_t; + +/** + * Set MIG mode for the device. + * + * For Ampere &tm; or newer fully supported devices. + * Requires root user. + * + * This mode determines whether a GPU instance can be created. + * + * This API may unbind or reset the device to activate the requested mode. Thus, the attributes associated with the + * device, such as minor number, might change. The caller of this API is expected to query such attributes again. + * + * On certain platforms like pass-through virtualization, where reset functionality may not be exposed directly, VM + * reboot is required. \a activationStatus would return \ref NVML_ERROR_RESET_REQUIRED for such cases. + * + * \a activationStatus would return the appropriate error code upon unsuccessful activation. For example, if device + * unbind fails because the device isn't idle, \ref NVML_ERROR_IN_USE would be returned. The caller of this API + * is expected to idle the device and retry setting the \a mode. + * + * @note On Windows, only disabling MIG mode is supported. \a activationStatus would return \ref + * NVML_ERROR_NOT_SUPPORTED as GPU reset is not supported on Windows through this API. + * + * @param device The identifier of the target device + * @param mode The mode to be set, \ref NVML_DEVICE_MIG_DISABLE or + * \ref NVML_DEVICE_MIG_ENABLE + * @param activationStatus The activationStatus status + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a device,\a mode or \a activationStatus are invalid + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't support MIG mode + */ +nvmlReturn_t DECLDIR nvmlDeviceSetMigMode(nvmlDevice_t device, unsigned int mode, nvmlReturn_t *activationStatus); + +/** + * Get MIG mode for the device. + * + * For Ampere &tm; or newer fully supported devices. + * + * Changing MIG modes may require device unbind or reset. The "pending" MIG mode refers to the target mode following the + * next activation trigger. + * + * @param device The identifier of the target device + * @param currentMode Returns the current mode, \ref NVML_DEVICE_MIG_DISABLE or + * \ref NVML_DEVICE_MIG_ENABLE + * @param pendingMode Returns the pending mode, \ref NVML_DEVICE_MIG_DISABLE or + * \ref NVML_DEVICE_MIG_ENABLE + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a device, \a currentMode or \a pendingMode are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't support MIG mode + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMigMode(nvmlDevice_t device, unsigned int *currentMode, unsigned int *pendingMode); + +/** + * Get GPU instance profile information. + * + * Information provided by this API is immutable throughout the lifetime of a MIG mode. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device The identifier of the target device + * @param profile One of the NVML_GPU_INSTANCE_PROFILE_* + * @param info Returns detailed profile information + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a device, \a profile or \a info are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't have MIG mode enabled or \a profile isn't supported + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGpuInstanceProfileInfo(nvmlDevice_t device, unsigned int profile, + nvmlGpuInstanceProfileInfo_t *info); + +/** + * Versioned wrapper around \ref nvmlDeviceGetGpuInstanceProfileInfo that accepts a versioned + * \ref nvmlGpuInstanceProfileInfo_v2_t or later output structure. + * + * @note The caller must set the \ref nvmlGpuInstanceProfileInfo_v2_t.version field to the + * appropriate version prior to calling this function. For example: + * \code + * nvmlGpuInstanceProfileInfo_v2_t profileInfo = + * { .version = nvmlGpuInstanceProfileInfo_v2 }; + * nvmlReturn_t result = nvmlDeviceGetGpuInstanceProfileInfoV(device, + * profile, + * &profileInfo); + * \endcode + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device The identifier of the target device + * @param profile One of the NVML_GPU_INSTANCE_PROFILE_* + * @param info Returns detailed profile information + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a device, \a profile, \a info, or \a info->version are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't have MIG mode enabled or \a profile isn't supported + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGpuInstanceProfileInfoV(nvmlDevice_t device, unsigned int profile, + nvmlGpuInstanceProfileInfo_v2_t *info); + +/** + * Get GPU instance placements. + * + * A placement represents the location of a GPU instance within a device. This API only returns all the possible + * placements for the given profile. + * A created GPU instance occupies memory slices described by its placement. Creation of new GPU instance will + * fail if there is overlap with the already occupied memory slices. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * @param device The identifier of the target device + * @param profileId The GPU instance profile ID. See \ref nvmlDeviceGetGpuInstanceProfileInfo + * @param placements Returns placements allowed for the profile. Can be NULL to discover number + * of allowed placements for this profile. If non-NULL must be large enough + * to accommodate the placements supported by the profile. + * @param count Returns number of allowed placemenets for the profile. + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a device, \a profileId or \a count are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't have MIG mode enabled or \a profileId isn't supported + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGpuInstancePossiblePlacements_v2(nvmlDevice_t device, unsigned int profileId, + nvmlGpuInstancePlacement_t *placements, + unsigned int *count); + +/** + * Get GPU instance profile capacity. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * @param device The identifier of the target device + * @param profileId The GPU instance profile ID. See \ref nvmlDeviceGetGpuInstanceProfileInfo + * @param count Returns remaining instance count for the profile ID + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a device, \a profileId or \a count are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't have MIG mode enabled or \a profileId isn't supported + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGpuInstanceRemainingCapacity(nvmlDevice_t device, unsigned int profileId, + unsigned int *count); + +/** + * Create GPU instance. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * If the parent device is unbound, reset or the GPU instance is destroyed explicitly, the GPU instance handle would + * become invalid. The GPU instance must be recreated to acquire a valid handle. + * + * @param device The identifier of the target device + * @param profileId The GPU instance profile ID. See \ref nvmlDeviceGetGpuInstanceProfileInfo + * @param gpuInstance Returns the GPU instance handle + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a device, \a profile, \a profileId or \a gpuInstance are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't have MIG mode enabled or in vGPU guest + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + * - \ref NVML_ERROR_INSUFFICIENT_RESOURCES If the requested GPU instance could not be created + */ +nvmlReturn_t DECLDIR nvmlDeviceCreateGpuInstance(nvmlDevice_t device, unsigned int profileId, + nvmlGpuInstance_t *gpuInstance); + +/** + * Create GPU instance with the specified placement. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * If the parent device is unbound, reset or the GPU instance is destroyed explicitly, the GPU instance handle would + * become invalid. The GPU instance must be recreated to acquire a valid handle. + * + * @param device The identifier of the target device + * @param profileId The GPU instance profile ID. See \ref nvmlDeviceGetGpuInstanceProfileInfo + * @param placement The requested placement. See \ref nvmlDeviceGetGpuInstancePossiblePlacements_v2 + * @param gpuInstance Returns the GPU instance handle + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a device, \a profile, \a profileId, \a placement or \a gpuInstance + * are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't have MIG mode enabled or in vGPU guest + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + * - \ref NVML_ERROR_INSUFFICIENT_RESOURCES If the requested GPU instance could not be created + */ +nvmlReturn_t DECLDIR nvmlDeviceCreateGpuInstanceWithPlacement(nvmlDevice_t device, unsigned int profileId, + const nvmlGpuInstancePlacement_t *placement, + nvmlGpuInstance_t *gpuInstance); +/** + * Destroy GPU instance. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * @param gpuInstance The GPU instance handle + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a gpuInstance is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't have MIG mode enabled or in vGPU guest + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + * - \ref NVML_ERROR_IN_USE If the GPU instance is in use. This error would be returned if processes + * (e.g. CUDA application) or compute instances are active on the + * GPU instance. + */ +nvmlReturn_t DECLDIR nvmlGpuInstanceDestroy(nvmlGpuInstance_t gpuInstance); + +/** + * Get GPU instances for given profile ID. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * @param device The identifier of the target device + * @param profileId The GPU instance profile ID. See \ref nvmlDeviceGetGpuInstanceProfileInfo + * @param gpuInstances Returns pre-exiting GPU instances, the buffer must be large enough to + * accommodate the instances supported by the profile. + * See \ref nvmlDeviceGetGpuInstanceProfileInfo + * @param count The count of returned GPU instances + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a device, \a profileId, \a gpuInstances or \a count are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't have MIG mode enabled + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGpuInstances(nvmlDevice_t device, unsigned int profileId, + nvmlGpuInstance_t *gpuInstances, unsigned int *count); + +/** + * Get GPU instances for given instance ID. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * @param device The identifier of the target device + * @param id The GPU instance ID + * @param gpuInstance Returns GPU instance + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a device, \a id or \a gpuInstance are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't have MIG mode enabled + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + * - \ref NVML_ERROR_NOT_FOUND If the GPU instance is not found. + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGpuInstanceById(nvmlDevice_t device, unsigned int id, nvmlGpuInstance_t *gpuInstance); + +/** + * Get GPU instance information. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param gpuInstance The GPU instance handle + * @param info Return GPU instance information + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a gpuInstance or \a info are invalid + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + */ +nvmlReturn_t DECLDIR nvmlGpuInstanceGetInfo(nvmlGpuInstance_t gpuInstance, nvmlGpuInstanceInfo_t *info); + +/** + * Get compute instance profile information. + * + * Information provided by this API is immutable throughout the lifetime of a MIG mode. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param gpuInstance The identifier of the target GPU instance + * @param profile One of the NVML_COMPUTE_INSTANCE_PROFILE_* + * @param engProfile One of the NVML_COMPUTE_INSTANCE_ENGINE_PROFILE_* + * @param info Returns detailed profile information + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a gpuInstance, \a profile, \a engProfile or \a info are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a profile isn't supported + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + */ +nvmlReturn_t DECLDIR nvmlGpuInstanceGetComputeInstanceProfileInfo(nvmlGpuInstance_t gpuInstance, unsigned int profile, + unsigned int engProfile, + nvmlComputeInstanceProfileInfo_t *info); + +/** + * Versioned wrapper around \ref nvmlGpuInstanceGetComputeInstanceProfileInfo that accepts a versioned + * \ref nvmlComputeInstanceProfileInfo_v2_t or later output structure. + * + * @note The caller must set the \ref nvmlGpuInstanceProfileInfo_v2_t.version field to the + * appropriate version prior to calling this function. For example: + * \code + * nvmlComputeInstanceProfileInfo_v2_t profileInfo = + * { .version = nvmlComputeInstanceProfileInfo_v2 }; + * nvmlReturn_t result = nvmlGpuInstanceGetComputeInstanceProfileInfoV(gpuInstance, + * profile, + * engProfile, + * &profileInfo); + * \endcode + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param gpuInstance The identifier of the target GPU instance + * @param profile One of the NVML_COMPUTE_INSTANCE_PROFILE_* + * @param engProfile One of the NVML_COMPUTE_INSTANCE_ENGINE_PROFILE_* + * @param info Returns detailed profile information + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a gpuInstance, \a profile, \a engProfile, \a info, or \a info->version are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a profile isn't supported + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + */ +nvmlReturn_t DECLDIR nvmlGpuInstanceGetComputeInstanceProfileInfoV(nvmlGpuInstance_t gpuInstance, unsigned int profile, + unsigned int engProfile, + nvmlComputeInstanceProfileInfo_v2_t *info); + +/** + * Get compute instance profile capacity. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * @param gpuInstance The identifier of the target GPU instance + * @param profileId The compute instance profile ID. + * See \ref nvmlGpuInstanceGetComputeInstanceProfileInfo + * @param count Returns remaining instance count for the profile ID + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a gpuInstance, \a profileId or \a availableCount are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a profileId isn't supported + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + */ +nvmlReturn_t DECLDIR nvmlGpuInstanceGetComputeInstanceRemainingCapacity(nvmlGpuInstance_t gpuInstance, + unsigned int profileId, unsigned int *count); + +/** + * Get compute instance placements. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * A placement represents the location of a compute instance within a GPU instance. This API only returns all the possible + * placements for the given profile. + * A created compute instance occupies compute slices described by its placement. Creation of new compute instance will + * fail if there is overlap with the already occupied compute slices. + * + * @param gpuInstance The identifier of the target GPU instance + * @param profileId The compute instance profile ID. See \ref nvmlGpuInstanceGetComputeInstanceProfileInfo + * @param placements Returns placements allowed for the profile. Can be NULL to discover number + * of allowed placements for this profile. If non-NULL must be large enough + * to accommodate the placements supported by the profile. + * @param count Returns number of allowed placemenets for the profile. + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a gpuInstance, \a profileId or \a count are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't have MIG mode enabled or \a profileId isn't supported + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + */ +nvmlReturn_t DECLDIR nvmlGpuInstanceGetComputeInstancePossiblePlacements(nvmlGpuInstance_t gpuInstance, + unsigned int profileId, + nvmlComputeInstancePlacement_t *placements, + unsigned int *count); + +/** + * Create compute instance. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * If the parent device is unbound, reset or the parent GPU instance is destroyed or the compute instance is destroyed + * explicitly, the compute instance handle would become invalid. The compute instance must be recreated to acquire + * a valid handle. + * + * @param gpuInstance The identifier of the target GPU instance + * @param profileId The compute instance profile ID. + * See \ref nvmlGpuInstanceGetComputeInstanceProfileInfo + * @param computeInstance Returns the compute instance handle + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a gpuInstance, \a profile, \a profileId or \a computeInstance + * are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a profileId isn't supported + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + * - \ref NVML_ERROR_INSUFFICIENT_RESOURCES If the requested compute instance could not be created + */ +nvmlReturn_t DECLDIR nvmlGpuInstanceCreateComputeInstance(nvmlGpuInstance_t gpuInstance, unsigned int profileId, + nvmlComputeInstance_t *computeInstance); + +/** + * Create compute instance with the specified placement. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * If the parent device is unbound, reset or the parent GPU instance is destroyed or the compute instance is destroyed + * explicitly, the compute instance handle would become invalid. The compute instance must be recreated to acquire + * a valid handle. + * + * @param gpuInstance The identifier of the target GPU instance + * @param profileId The compute instance profile ID. + * See \ref nvmlGpuInstanceGetComputeInstanceProfileInfo + * @param placement The requested placement. See \ref nvmlGpuInstanceGetComputeInstancePossiblePlacements + * @param computeInstance Returns the compute instance handle + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a gpuInstance, \a profile, \a profileId or \a computeInstance + * are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a profileId isn't supported + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + * - \ref NVML_ERROR_INSUFFICIENT_RESOURCES If the requested compute instance could not be created + */ +nvmlReturn_t DECLDIR nvmlGpuInstanceCreateComputeInstanceWithPlacement(nvmlGpuInstance_t gpuInstance, unsigned int profileId, + const nvmlComputeInstancePlacement_t *placement, + nvmlComputeInstance_t *computeInstance); + +/** + * Destroy compute instance. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * @param computeInstance The compute instance handle + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a computeInstance is invalid + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + * - \ref NVML_ERROR_IN_USE If the compute instance is in use. This error would be returned if + * processes (e.g. CUDA application) are active on the compute instance. + */ +nvmlReturn_t DECLDIR nvmlComputeInstanceDestroy(nvmlComputeInstance_t computeInstance); + +/** + * Get compute instances for given profile ID. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * @param gpuInstance The identifier of the target GPU instance + * @param profileId The compute instance profile ID. + * See \ref nvmlGpuInstanceGetComputeInstanceProfileInfo + * @param computeInstances Returns pre-exiting compute instances, the buffer must be large enough to + * accommodate the instances supported by the profile. + * See \ref nvmlGpuInstanceGetComputeInstanceProfileInfo + * @param count The count of returned compute instances + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a gpuInstance, \a profileId, \a computeInstances or \a count + * are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a profileId isn't supported + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + */ +nvmlReturn_t DECLDIR nvmlGpuInstanceGetComputeInstances(nvmlGpuInstance_t gpuInstance, unsigned int profileId, + nvmlComputeInstance_t *computeInstances, unsigned int *count); + +/** + * Get compute instance for given instance ID. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * @param gpuInstance The identifier of the target GPU instance + * @param id The compute instance ID + * @param computeInstance Returns compute instance + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a device, \a ID or \a computeInstance are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't have MIG mode enabled + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + * - \ref NVML_ERROR_NOT_FOUND If the compute instance is not found. + */ +nvmlReturn_t DECLDIR nvmlGpuInstanceGetComputeInstanceById(nvmlGpuInstance_t gpuInstance, unsigned int id, + nvmlComputeInstance_t *computeInstance); + +/** + * Get compute instance information. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param computeInstance The compute instance handle + * @param info Return compute instance information + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a computeInstance or \a info are invalid + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + */ +nvmlReturn_t DECLDIR nvmlComputeInstanceGetInfo_v2(nvmlComputeInstance_t computeInstance, nvmlComputeInstanceInfo_t *info); + +/** + * Test if the given handle refers to a MIG device. + * + * A MIG device handle is an NVML abstraction which maps to a MIG compute instance. + * These overloaded references can be used (with some restrictions) interchangeably + * with a GPU device handle to execute queries at a per-compute instance granularity. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device NVML handle to test + * @param isMigDevice True when handle refers to a MIG device + * + * @return + * - \ref NVML_SUCCESS if \a device status was successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device handle or \a isMigDevice reference is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if this check is not supported by the device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceIsMigDeviceHandle(nvmlDevice_t device, unsigned int *isMigDevice); + +/** + * Get GPU instance ID for the given MIG device handle. + * + * GPU instance IDs are unique per device and remain valid until the GPU instance is destroyed. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device Target MIG device handle + * @param id GPU instance ID + * + * @return + * - \ref NVML_SUCCESS if instance ID was successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device or \a id reference is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGpuInstanceId(nvmlDevice_t device, unsigned int *id); + +/** + * Get compute instance ID for the given MIG device handle. + * + * Compute instance IDs are unique per GPU instance and remain valid until the compute instance + * is destroyed. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device Target MIG device handle + * @param id Compute instance ID + * + * @return + * - \ref NVML_SUCCESS if instance ID was successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device or \a id reference is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetComputeInstanceId(nvmlDevice_t device, unsigned int *id); + +/** + * Get the maximum number of MIG devices that can exist under a given parent NVML device. + * + * Returns zero if MIG is not supported or enabled. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device Target device handle + * @param count Count of MIG devices + * + * @return + * - \ref NVML_SUCCESS if \a count was successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device or \a count reference is invalid + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMaxMigDeviceCount(nvmlDevice_t device, unsigned int *count); + +/** + * Get MIG device handle for the given index under its parent NVML device. + * + * If the compute instance is destroyed either explicitly or by destroying, + * resetting or unbinding the parent GPU instance or the GPU device itself + * the MIG device handle would remain invalid and must be requested again + * using this API. Handles may be reused and their properties can change in + * the process. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device Reference to the parent GPU device handle + * @param index Index of the MIG device + * @param migDevice Reference to the MIG device handle + * + * @return + * - \ref NVML_SUCCESS if \a migDevice handle was successfully created + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a index or \a migDevice reference is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_NOT_FOUND if no valid MIG device was found at \a index + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMigDeviceHandleByIndex(nvmlDevice_t device, unsigned int index, + nvmlDevice_t *migDevice); + +/** + * Get parent device handle from a MIG device handle. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param migDevice MIG device handle + * @param device Device handle + * + * @return + * - \ref NVML_SUCCESS if \a device handle was successfully created + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a migDevice or \a device is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetDeviceHandleFromMigDeviceHandle(nvmlDevice_t migDevice, nvmlDevice_t *device); + +/** + * Get the type of the GPU Bus (PCIe, PCI, ...) + * + * @param device The identifier of the target device + * @param type The PCI Bus type + * + * return + * - \ref NVML_SUCCESS if the bus \a type is successfully retreived + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \device is invalid or \type is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetBusType(nvmlDevice_t device, nvmlBusType_t *type); + +/** + * Retrieve performance monitor samples from the associated subdevice. + * + * @param device + * @param pDynamicPstatesInfo + * + * @return + * - \ref NVML_SUCCESS if \a pDynamicPstatesInfo has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a pDynamicPstatesInfo is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetDynamicPstatesInfo(nvmlDevice_t device, nvmlGpuDynamicPstatesInfo_t *pDynamicPstatesInfo); + +/** + * Sets the speed of a specified fan. + * + * WARNING: This function changes the fan control policy to manual. It means that YOU have to monitor + * the temperature and adjust the fan speed accordingly. + * If you set the fan speed too low you can burn your GPU! + * Use nvmlDeviceSetDefaultFanSpeed_v2 to restore default control policy. + * + * For all cuda-capable discrete products with fans that are Maxwell or Newer. + * + * device The identifier of the target device + * fan The index of the fan, starting at zero + * speed The target speed of the fan [0-100] in % of max speed + * + * return + * NVML_SUCCESS if the fan speed has been set + * NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * NVML_ERROR_INVALID_ARGUMENT if the device is not valid, or the speed is outside acceptable ranges, + * or if the fan index doesn't reference an actual fan. + * NVML_ERROR_NOT_SUPPORTED if the device is older than Maxwell. + * NVML_ERROR_UNKNOWN if there was an unexpected error. + */ +nvmlReturn_t DECLDIR nvmlDeviceSetFanSpeed_v2(nvmlDevice_t device, unsigned int fan, unsigned int speed); + +/** + * Retrieve the GPCCLK VF offset value + * @param[in] device The identifier of the target device + * @param[out] offset The retrieved GPCCLK VF offset value + * + * @return + * - \ref NVML_SUCCESS if \a offset has been successfully queried + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a offset is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGpcClkVfOffset(nvmlDevice_t device, int *offset); + +/** + * Set the GPCCLK VF offset value + * @param[in] device The identifier of the target device + * @param[in] offset The GPCCLK VF offset value to set + * + * @return + * - \ref NVML_SUCCESS if \a offset has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a offset is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceSetGpcClkVfOffset(nvmlDevice_t device, int offset); + +/** + * Retrieve the MemClk (Memory Clock) VF offset value. + * @param[in] device The identifier of the target device + * @param[out] offset The retrieved MemClk VF offset value + * + * @return + * - \ref NVML_SUCCESS if \a offset has been successfully queried + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a offset is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMemClkVfOffset(nvmlDevice_t device, int *offset); + +/** + * Set the MemClk (Memory Clock) VF offset value. It requires elevated privileges. + * @param[in] device The identifier of the target device + * @param[in] offset The MemClk VF offset value to set + * + * @return + * - \ref NVML_SUCCESS if \a offset has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a offset is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceSetMemClkVfOffset(nvmlDevice_t device, int offset); + +/** + * Retrieve min and max clocks of some clock domain for a given PState + * + * @param device The identifier of the target device + * @param type Clock domain + * @param pstate PState to query + * @param minClockMHz Reference in which to return min clock frequency + * @param maxClockMHz Reference in which to return max clock frequency + * + * @return + * - \ref NVML_SUCCESS if everything worked + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a type or \a pstate are invalid or both + * \a minClockMHz and \a maxClockMHz are NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMinMaxClockOfPState(nvmlDevice_t device, nvmlClockType_t type, nvmlPstates_t pstate, + unsigned int * minClockMHz, unsigned int * maxClockMHz); + +/** + * Get all supported Performance States (P-States) for the device. + * + * The returned array would contain a contiguous list of valid P-States supported by + * the device. If the number of supported P-States is fewer than the size of the array + * supplied missing elements would contain \a NVML_PSTATE_UNKNOWN. + * + * The number of elements in the returned list will never exceed \a NVML_MAX_GPU_PERF_PSTATES. + * + * @param device The identifier of the target device + * @param pstates Container to return the list of performance states + * supported by device + * @param size Size of the supplied \a pstates array in bytes + * + * @return + * - \ref NVML_SUCCESS if \a pstates array has been retrieved + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if the the container supplied was not large enough to + * hold the resulting list + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device or \a pstates is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support performance state readings + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetSupportedPerformanceStates(nvmlDevice_t device, + nvmlPstates_t *pstates, unsigned int size); + +/** + * Retrieve the GPCCLK min max VF offset value. + * @param[in] device The identifier of the target device + * @param[out] minOffset The retrieved GPCCLK VF min offset value + * @param[out] maxOffset The retrieved GPCCLK VF max offset value + * + * @return + * - \ref NVML_SUCCESS if \a offset has been successfully queried + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a offset is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGpcClkMinMaxVfOffset(nvmlDevice_t device, + int *minOffset, int *maxOffset); + +/** + * Retrieve the MemClk (Memory Clock) min max VF offset value. + * @param[in] device The identifier of the target device + * @param[out] minOffset The retrieved MemClk VF min offset value + * @param[out] maxOffset The retrieved MemClk VF max offset value + * + * @return + * - \ref NVML_SUCCESS if \a offset has been successfully queried + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a offset is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMemClkMinMaxVfOffset(nvmlDevice_t device, + int *minOffset, int *maxOffset); + +/** + * Get fabric information associated with the device. + * + * %HOPPER_OR_NEWER% + * + * On Hopper + NVSwitch systems, GPU is registered with the NVIDIA Fabric Manager + * Upon successful registration, the GPU is added to the NVLink fabric to enable + * peer-to-peer communication. + * This API reports the current state of the GPU in the NVLink fabric + * along with other useful information. + * + * @param device The identifier of the target device + * @param gpuFabricInfo Information about GPU fabric state + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't support gpu fabric + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGpuFabricInfo(nvmlDevice_t device, nvmlGpuFabricInfo_t *gpuFabricInfo); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup GPM NVML GPM + * @{ + */ +/***************************************************************************************************/ +/** @defgroup nvmlGpmEnums GPM Enums + * @{ + */ +/***************************************************************************************************/ + +/* GPM Metric Identifiers */ +typedef enum +{ + NVML_GPM_METRIC_GRAPHICS_UTIL = 1, /* Percentage of time any compute/graphics app was active on the GPU. 0.0 - 100.0 */ + NVML_GPM_METRIC_SM_UTIL = 2, /* Percentage of SMs that were busy. 0.0 - 100.0 */ + NVML_GPM_METRIC_SM_OCCUPANCY = 3, /* Percentage of warps that were active vs theoretical maximum. 0.0 - 100.0 */ + NVML_GPM_METRIC_INTEGER_UTIL = 4, /* Percentage of time the GPU's SMs were doing integer operations. 0.0 - 100.0 */ + NVML_GPM_METRIC_ANY_TENSOR_UTIL = 5, /* Percentage of time the GPU's SMs were doing ANY tensor operations. 0.0 - 100.0 */ + NVML_GPM_METRIC_DFMA_TENSOR_UTIL = 6, /* Percentage of time the GPU's SMs were doing DFMA tensor operations. 0.0 - 100.0 */ + NVML_GPM_METRIC_HMMA_TENSOR_UTIL = 7, /* Percentage of time the GPU's SMs were doing HMMA tensor operations. 0.0 - 100.0 */ + NVML_GPM_METRIC_IMMA_TENSOR_UTIL = 9, /* Percentage of time the GPU's SMs were doing IMMA tensor operations. 0.0 - 100.0 */ + NVML_GPM_METRIC_DRAM_BW_UTIL = 10, /* Percentage of DRAM bw used vs theoretical maximum. 0.0 - 100.0 */ + NVML_GPM_METRIC_FP64_UTIL = 11, /* Percentage of time the GPU's SMs were doing non-tensor FP64 math. 0.0 - 100.0 */ + NVML_GPM_METRIC_FP32_UTIL = 12, /* Percentage of time the GPU's SMs were doing non-tensor FP32 math. 0.0 - 100.0 */ + NVML_GPM_METRIC_FP16_UTIL = 13, /* Percentage of time the GPU's SMs were doing non-tensor FP16 math. 0.0 - 100.0 */ + NVML_GPM_METRIC_PCIE_TX_PER_SEC = 20, /* PCIe traffic from this GPU in MiB/sec */ + NVML_GPM_METRIC_PCIE_RX_PER_SEC = 21, /* PCIe traffic to this GPU in MiB/sec */ + NVML_GPM_METRIC_NVDEC_0_UTIL = 30, /* Percent utilization of NVDEC 0. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVDEC_1_UTIL = 31, /* Percent utilization of NVDEC 1. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVDEC_2_UTIL = 32, /* Percent utilization of NVDEC 2. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVDEC_3_UTIL = 33, /* Percent utilization of NVDEC 3. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVDEC_4_UTIL = 34, /* Percent utilization of NVDEC 4. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVDEC_5_UTIL = 35, /* Percent utilization of NVDEC 5. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVDEC_6_UTIL = 36, /* Percent utilization of NVDEC 6. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVDEC_7_UTIL = 37, /* Percent utilization of NVDEC 7. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVJPG_0_UTIL = 40, /* Percent utilization of NVJPG 0. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVJPG_1_UTIL = 41, /* Percent utilization of NVJPG 1. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVJPG_2_UTIL = 42, /* Percent utilization of NVJPG 2. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVJPG_3_UTIL = 43, /* Percent utilization of NVJPG 3. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVJPG_4_UTIL = 44, /* Percent utilization of NVJPG 4. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVJPG_5_UTIL = 45, /* Percent utilization of NVJPG 5. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVJPG_6_UTIL = 46, /* Percent utilization of NVJPG 6. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVJPG_7_UTIL = 47, /* Percent utilization of NVJPG 7. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVOFA_0_UTIL = 50, /* Percent utilization of NVOFA 0. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVLINK_TOTAL_RX_PER_SEC = 60, /* NvLink read bandwidth for all links in MiB/sec */ + NVML_GPM_METRIC_NVLINK_TOTAL_TX_PER_SEC = 61, /* NvLink write bandwidth for all links in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L0_RX_PER_SEC = 62, /* NvLink read bandwidth for link 0 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L0_TX_PER_SEC = 63, /* NvLink write bandwidth for link 0 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L1_RX_PER_SEC = 64, /* NvLink read bandwidth for link 1 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L1_TX_PER_SEC = 65, /* NvLink write bandwidth for link 1 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L2_RX_PER_SEC = 66, /* NvLink read bandwidth for link 2 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L2_TX_PER_SEC = 67, /* NvLink write bandwidth for link 2 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L3_RX_PER_SEC = 68, /* NvLink read bandwidth for link 3 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L3_TX_PER_SEC = 69, /* NvLink write bandwidth for link 3 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L4_RX_PER_SEC = 70, /* NvLink read bandwidth for link 4 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L4_TX_PER_SEC = 71, /* NvLink write bandwidth for link 4 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L5_RX_PER_SEC = 72, /* NvLink read bandwidth for link 5 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L5_TX_PER_SEC = 73, /* NvLink write bandwidth for link 5 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L6_RX_PER_SEC = 74, /* NvLink read bandwidth for link 6 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L6_TX_PER_SEC = 75, /* NvLink write bandwidth for link 6 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L7_RX_PER_SEC = 76, /* NvLink read bandwidth for link 7 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L7_TX_PER_SEC = 77, /* NvLink write bandwidth for link 7 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L8_RX_PER_SEC = 78, /* NvLink read bandwidth for link 8 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L8_TX_PER_SEC = 79, /* NvLink write bandwidth for link 8 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L9_RX_PER_SEC = 80, /* NvLink read bandwidth for link 9 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L9_TX_PER_SEC = 81, /* NvLink write bandwidth for link 9 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L10_RX_PER_SEC = 82, /* NvLink read bandwidth for link 10 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L10_TX_PER_SEC = 83, /* NvLink write bandwidth for link 10 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L11_RX_PER_SEC = 84, /* NvLink read bandwidth for link 11 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L11_TX_PER_SEC = 85, /* NvLink write bandwidth for link 11 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L12_RX_PER_SEC = 86, /* NvLink read bandwidth for link 12 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L12_TX_PER_SEC = 87, /* NvLink write bandwidth for link 12 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L13_RX_PER_SEC = 88, /* NvLink read bandwidth for link 13 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L13_TX_PER_SEC = 89, /* NvLink write bandwidth for link 13 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L14_RX_PER_SEC = 90, /* NvLink read bandwidth for link 14 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L14_TX_PER_SEC = 91, /* NvLink write bandwidth for link 14 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L15_RX_PER_SEC = 92, /* NvLink read bandwidth for link 15 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L15_TX_PER_SEC = 93, /* NvLink write bandwidth for link 15 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L16_RX_PER_SEC = 94, /* NvLink read bandwidth for link 16 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L16_TX_PER_SEC = 95, /* NvLink write bandwidth for link 16 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L17_RX_PER_SEC = 96, /* NvLink read bandwidth for link 17 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L17_TX_PER_SEC = 97, /* NvLink write bandwidth for link 17 in MiB/sec */ + NVML_GPM_METRIC_MAX = 98, /* Maximum value above +1. Note that changing this + should also change NVML_GPM_METRICS_GET_VERSION + due to struct size change */ +} nvmlGpmMetricId_t; + +/** @} */ // @defgroup nvmlGpmEnums + + +/***************************************************************************************************/ +/** @defgroup nvmlGpmStructs GPM Structs + * @{ + */ +/***************************************************************************************************/ + +/* Handle to an allocated GPM sample allocated with nvmlGpmSampleAlloc() + Free this with nvmlGpmSampleFree() */ +typedef struct nvmlGpmSample_st* nvmlGpmSample_t; + +typedef struct +{ + unsigned int metricId; /* IN: NVML_GPM_METRIC_? #define of which metric to retrieve */ + nvmlReturn_t nvmlReturn; /* OUT: Status of this metric. If this is nonzero, then value is not valid */ + double value; /* OUT: Value of this metric. Is only valid if nvmlReturn is 0 (NVML_SUCCESS) */ + struct + { + char *shortName; + char *longName; + char *unit; + } metricInfo; /* OUT: Metric name and unit. Those can be NULL if not defined */ +} nvmlGpmMetric_t; + +typedef struct +{ + unsigned int version; /* IN: Set to NVML_GPM_METRICS_GET_VERSION */ + unsigned int numMetrics; /* IN: How many metrics to retrieve in metrics[] */ + nvmlGpmSample_t sample1; /* IN: Sample buffer */ + nvmlGpmSample_t sample2; /* IN: Sample buffer */ + nvmlGpmMetric_t metrics[NVML_GPM_METRIC_MAX]; /* IN/OUT: Array of metrics. Set metricId on call. + see nvmlReturn and value on return */ +} nvmlGpmMetricsGet_t; + +#define NVML_GPM_METRICS_GET_VERSION 1 + +typedef struct +{ + unsigned int version; /* IN: Set to NVML_GPM_SUPPORT_VERSION */ + unsigned int isSupportedDevice; /* OUT: Indicates device support */ +} nvmlGpmSupport_t; + +#define NVML_GPM_SUPPORT_VERSION 1 + +/** @} */ // @defgroup nvmlGPMStructs + +/***************************************************************************************************/ +/** @defgroup nvmlGpmFunctions GPM Functions + * @{ + */ +/***************************************************************************************************/ + +/** + * Calculate GPM metrics from two samples. + * + * + * @param metricsGet IN/OUT: populated nvmlGpmMetricsGet_t struct + * + * %HOPPER_OR_NEWER% + * + * @return + * - \ref NVML_SUCCESS on success + * - Nonzero NVML_ERROR_? enum on error + */ +nvmlReturn_t DECLDIR nvmlGpmMetricsGet(nvmlGpmMetricsGet_t *metricsGet); + + +/** + * Free an allocated sample buffer that was allocated with \ref nvmlGpmSampleAlloc() + * + * %HOPPER_OR_NEWER% + * + * @param gpmSample Sample to free + * + * @return + * - \ref NVML_SUCCESS on success + * - \ref NVML_ERROR_INVALID_ARGUMENT if an invalid pointer is provided + */ +nvmlReturn_t DECLDIR nvmlGpmSampleFree(nvmlGpmSample_t gpmSample); + + +/** + * Allocate a sample buffer to be used with NVML GPM . You will need to allocate + * at least two of these buffers to use with the NVML GPM feature + * + * %HOPPER_OR_NEWER% + * + * @param gpmSample Where the allocated sample will be stored + * + * @return + * - \ref NVML_SUCCESS on success + * - \ref NVML_ERROR_INVALID_ARGUMENT if an invalid pointer is provided + * - \ref NVML_ERROR_MEMORY if system memory is insufficient + */ +nvmlReturn_t DECLDIR nvmlGpmSampleAlloc(nvmlGpmSample_t *gpmSample); + +/** + * Read a sample of GPM metrics into the provided \a gpmSample buffer. After + * two samples are gathered, you can call nvmlGpmMetricGet on those samples to + * retrive metrics + * + * %HOPPER_OR_NEWER% + * + * @param device Device to get samples for + * @param gpmSample Buffer to read samples into + * + * @return + * - \ref NVML_SUCCESS on success + * - Nonzero NVML_ERROR_? enum on error + */ +nvmlReturn_t DECLDIR nvmlGpmSampleGet(nvmlDevice_t device, nvmlGpmSample_t gpmSample); + +/** + * Read a sample of GPM metrics into the provided \a gpmSample buffer for a MIG GPU Instance. + * + * After two samples are gathered, you can call nvmlGpmMetricGet on those + * samples to retrive metrics + * + * %HOPPER_OR_NEWER% + * + * @param device Device to get samples for + * @param gpuInstanceId MIG GPU Instance ID + * @param gpmSample Buffer to read samples into + * + * @return + * - \ref NVML_SUCCESS on success + * - Nonzero NVML_ERROR_? enum on error + */ +nvmlReturn_t DECLDIR nvmlGpmMigSampleGet(nvmlDevice_t device, unsigned int gpuInstanceId, nvmlGpmSample_t gpmSample); + +/** + * Indicate whether the supplied device supports GPM + * + * @param device NVML device to query for + * @param gpmSupport Structure to indicate GPM support. Indicates + * GPM support per system for the supplied device + * + * @return + * - NVML_SUCCESS on success + * - Nonzero NVML_ERROR_? enum if there is an error in processing the query + */ +nvmlReturn_t DECLDIR nvmlGpmQueryDeviceSupport(nvmlDevice_t device, nvmlGpmSupport_t *gpmSupport); + +/** @} */ // @defgroup nvmlGpmFunctions +/** @} */ // @defgroup GPM + +/***************************************************************************************************/ +/** @defgroup nvmlDevice definitions related to Counter Collection Unit + * @{ + */ +/***************************************************************************************************/ + +/* CCU Stream State */ +#define NVML_COUNTER_COLLECTION_UNIT_STREAM_STATE_DISABLE 0 +#define NVML_COUNTER_COLLECTION_UNIT_STREAM_STATE_ENABLE 1 + +/** + * Get counter collection unit stream state. + * + * %HOPPER_OR_NEWER% + * Supported on Linux, Windows TCC. + * + * @param device The identifier of the target device + * @param state Returns counter collection unit stream state + * NVML_COUNTER_COLLECTION_UNIT_STREAM_STATE_DISABLE or + * NVML_COUNTER_COLLECTION_UNIT_STREAM_STATE_ENABLE + * + * @return + * - \ref NVML_SUCCESS if \a current counter collection unit stream state were successfully queried + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a state is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + */ +nvmlReturn_t DECLDIR nvmlDeviceCcuGetStreamState(nvmlDevice_t device, unsigned int *state); + +/** + * Set counter collection unit stream state. + * + * %HOPPER_OR_NEWER% + * Supported on Linux, Windows TCC. + * + * @param device The identifier of the target device + * @param state Counter collection unit stream state, + * NVML_COUNTER_COLLECTION_UNIT_STREAM_STATE_DISABLE or + * NVML_COUNTER_COLLECTION_UNIT_STREAM_STATE_ENABLE + * + * @return + * - \ref NVML_SUCCESS if \a current counter collection unit stream state is successfully set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + */ +nvmlReturn_t DECLDIR nvmlDeviceCcuSetStreamState(nvmlDevice_t device, unsigned int state); + +/** @} */ // @defgroup CCU + +#define NVML_NVLINK_POWER_STATE_HIGH_SPEED 0x0 +#define NVML_NVLINK_POWER_STATE_LOW 0x1 + +#define NVML_NVLINK_LOW_POWER_THRESHOLD_MIN 0x1 +#define NVML_NVLINK_LOW_POWER_THRESHOLD_MAX 0x1FFF +#define NVML_NVLINK_LOW_POWER_THRESHOLD_RESET 0xFFFFFFFF + +/* Structure containing Low Power parameters */ +typedef struct nvmlNvLinkPowerThres_st +{ + unsigned int lowPwrThreshold; //!< Low power threshold (in units of 100us) +} nvmlNvLinkPowerThres_t; + +/** + * Set NvLink Low Power Threshold for device. + * + * %HOPPER_OR_NEWER% + * + * @param device The identifier of the target device + * @param info Reference to \a nvmlNvLinkPowerThres_t struct + * input parameters + * + * @return + * - \ref NVML_SUCCESS if the \a Threshold is successfully set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a Threshold is not within range + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * + **/ +nvmlReturn_t DECLDIR nvmlDeviceSetNvLinkDeviceLowPowerThreshold(nvmlDevice_t device, nvmlNvLinkPowerThres_t *info); + +/** + * NVML API versioning support + */ + +#ifdef NVML_NO_UNVERSIONED_FUNC_DEFS +nvmlReturn_t DECLDIR nvmlInit(void); +nvmlReturn_t DECLDIR nvmlDeviceGetCount(unsigned int *deviceCount); +nvmlReturn_t DECLDIR nvmlDeviceGetHandleByIndex(unsigned int index, nvmlDevice_t *device); +nvmlReturn_t DECLDIR nvmlDeviceGetHandleByPciBusId(const char *pciBusId, nvmlDevice_t *device); +nvmlReturn_t DECLDIR nvmlDeviceGetPciInfo(nvmlDevice_t device, nvmlPciInfo_t *pci); +nvmlReturn_t DECLDIR nvmlDeviceGetPciInfo_v2(nvmlDevice_t device, nvmlPciInfo_t *pci); +nvmlReturn_t DECLDIR nvmlDeviceGetNvLinkRemotePciInfo(nvmlDevice_t device, unsigned int link, nvmlPciInfo_t *pci); +nvmlReturn_t DECLDIR nvmlDeviceGetGridLicensableFeatures(nvmlDevice_t device, nvmlGridLicensableFeatures_t *pGridLicensableFeatures); +nvmlReturn_t DECLDIR nvmlDeviceGetGridLicensableFeatures_v2(nvmlDevice_t device, nvmlGridLicensableFeatures_t *pGridLicensableFeatures); +nvmlReturn_t DECLDIR nvmlDeviceGetGridLicensableFeatures_v3(nvmlDevice_t device, nvmlGridLicensableFeatures_t *pGridLicensableFeatures); +nvmlReturn_t DECLDIR nvmlDeviceRemoveGpu(nvmlPciInfo_t *pciInfo); +nvmlReturn_t DECLDIR nvmlEventSetWait(nvmlEventSet_t set, nvmlEventData_t * data, unsigned int timeoutms); +nvmlReturn_t DECLDIR nvmlDeviceGetAttributes(nvmlDevice_t device, nvmlDeviceAttributes_t *attributes); +nvmlReturn_t DECLDIR nvmlComputeInstanceGetInfo(nvmlComputeInstance_t computeInstance, nvmlComputeInstanceInfo_t *info); +nvmlReturn_t DECLDIR nvmlDeviceGetComputeRunningProcesses(nvmlDevice_t device, unsigned int *infoCount, nvmlProcessInfo_v1_t *infos); +nvmlReturn_t DECLDIR nvmlDeviceGetComputeRunningProcesses_v2(nvmlDevice_t device, unsigned int *infoCount, nvmlProcessInfo_v2_t *infos); +nvmlReturn_t DECLDIR nvmlDeviceGetGraphicsRunningProcesses(nvmlDevice_t device, unsigned int *infoCount, nvmlProcessInfo_v1_t *infos); +nvmlReturn_t DECLDIR nvmlDeviceGetGraphicsRunningProcesses_v2(nvmlDevice_t device, unsigned int *infoCount, nvmlProcessInfo_v2_t *infos); +nvmlReturn_t DECLDIR nvmlDeviceGetMPSComputeRunningProcesses(nvmlDevice_t device, unsigned int *infoCount, nvmlProcessInfo_v1_t *infos); +nvmlReturn_t DECLDIR nvmlDeviceGetMPSComputeRunningProcesses_v2(nvmlDevice_t device, unsigned int *infoCount, nvmlProcessInfo_v2_t *infos); +nvmlReturn_t DECLDIR nvmlDeviceGetGpuInstancePossiblePlacements(nvmlDevice_t device, unsigned int profileId, nvmlGpuInstancePlacement_t *placements, unsigned int *count); +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetLicenseInfo(nvmlVgpuInstance_t vgpuInstance, nvmlVgpuLicenseInfo_t *licenseInfo); + +#endif // #ifdef NVML_NO_UNVERSIONED_FUNC_DEFS + +#if defined(NVML_NO_UNVERSIONED_FUNC_DEFS) +// We don't define APIs to run new versions if this guard is present so there is +// no need to undef +#elif defined(__NVML_API_VERSION_INTERNAL) +#undef nvmlDeviceGetGraphicsRunningProcesses +#undef nvmlDeviceGetComputeRunningProcesses +#undef nvmlDeviceGetMPSComputeRunningProcesses +#undef nvmlDeviceGetAttributes +#undef nvmlComputeInstanceGetInfo +#undef nvmlEventSetWait +#undef nvmlDeviceGetGridLicensableFeatures +#undef nvmlDeviceRemoveGpu +#undef nvmlDeviceGetNvLinkRemotePciInfo +#undef nvmlDeviceGetPciInfo +#undef nvmlDeviceGetCount +#undef nvmlDeviceGetHandleByIndex +#undef nvmlDeviceGetHandleByPciBusId +#undef nvmlInit +#undef nvmlBlacklistDeviceInfo_t +#undef nvmlGetBlacklistDeviceCount +#undef nvmlGetBlacklistDeviceInfoByIndex +#undef nvmlDeviceGetGpuInstancePossiblePlacements +#undef nvmlVgpuInstanceGetLicenseInfo + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/userspace/sdks/nv570/inc/alloc/alloc_access_counter_buffer.h b/userspace/sdks/nv570/inc/alloc/alloc_access_counter_buffer.h new file mode 100644 index 0000000..f55c326 --- /dev/null +++ b/userspace/sdks/nv570/inc/alloc/alloc_access_counter_buffer.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: alloc/alloc_access_counter_buffer.finn +// + +#include "class/clc365.h" + + +/* + * NV_ACCESS_COUNTER_NOTIFY_BUFFER_ALLOC_PARAMS + * + * Allocation params for ACCESS_COUNTER_NOTIFY_BUFFER. + * This class provides an interface to access counter buffers. + + * accessCounterIndex [IN] + * This parameter specifies index of access counter to which the object should be assigned + * + */ +#define NV_ACCESS_COUNTER_NOTIFY_BUFFER_ALLOC_PARAMS_MESSAGE_ID (0xC365U) + +typedef struct NV_ACCESS_COUNTER_NOTIFY_BUFFER_ALLOC_PARAMS { + NvU32 accessCounterIndex; +} NV_ACCESS_COUNTER_NOTIFY_BUFFER_ALLOC_PARAMS; + diff --git a/userspace/sdks/nv570/inc/alloc/alloc_channel.h b/userspace/sdks/nv570/inc/alloc/alloc_channel.h new file mode 100644 index 0000000..6ceb14f --- /dev/null +++ b/userspace/sdks/nv570/inc/alloc/alloc_channel.h @@ -0,0 +1,350 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: alloc/alloc_channel.finn +// + +#include "nvlimits.h" +#include "nvcfg_sdk.h" + +typedef struct NV_MEMORY_DESC_PARAMS { + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 addressSpace; + NvU32 cacheAttrib; +} NV_MEMORY_DESC_PARAMS; + +/* + * NV_CHANNEL_ALLOC_PARAMS.flags values. + * + * These flags may apply to all channel types: PIO, DMA, and GPFIFO. + * They are also designed so that zero is always the correct default. + * + * NVOS04_FLAGS_CHANNEL_TYPE: + * This flag specifies the type of channel to allocate. Legal values + * for this flag include: + * + * NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL: + * This flag specifies that a physical channel is to be allocated. + * + * NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL: + * OBSOLETE - NOT SUPPORTED + * + * NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL: + * OBSOLETE - NOT SUPPORTED + */ + +/* valid NVOS04_FLAGS_CHANNEL_TYPE values */ +#define NVOS04_FLAGS_CHANNEL_TYPE 1:0 +#define NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL 0x00000000 +#define NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL 0x00000001 // OBSOLETE +#define NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL 0x00000002 // OBSOLETE + +/* + * NVOS04_FLAGS_VPR: + * This flag specifies if channel is intended for work with + * Video Protected Regions (VPR) + * + * NVOS04_FLAGS_VPR_TRUE: + * The channel will only write to protected memory regions. + * + * NVOS04_FLAGS_VPR_FALSE: + * The channel will never read from protected memory regions. + */ +#define NVOS04_FLAGS_VPR 2:2 +#define NVOS04_FLAGS_VPR_FALSE 0x00000000 +#define NVOS04_FLAGS_VPR_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_CC_SECURE: + * This flag specifies if channel is intended to be used for + * encryption/decryption of data between SYSMEM <-> VIDMEM. Only CE + * & SEC2 Channels are capable of handling encrypted content and this + * flag will be ignored when CC is disabled or for chips that are not CC + * Capable. + * Reusing VPR index since VPR & CC are mutually exclusive. + * + * NVOS04_FLAGS_CC_SECURE_TRUE: + * The channel will support CC Encryption/Decryption + * + * NVOS04_FLAGS_CC_SECURE_FALSE: + * The channel will not support CC Encryption/Decryption + */ +#define NVOS04_FLAGS_CC_SECURE 2:2 +#define NVOS04_FLAGS_CC_SECURE_FALSE 0x00000000 +#define NVOS04_FLAGS_CC_SECURE_TRUE 0x00000001 + + + +/* + * NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING: + * This flag specifies if the channel can skip refcounting of potentially + * accessed mappings on job kickoff. This flag is only meaningful for + * kernel drivers which perform refcounting of memory mappings. + * + * NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE: + * The channel cannot not skip refcounting of memory mappings + * + * NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE: + * The channel can skip refcounting of memory mappings + */ +#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING 3:3 +#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE: + * This flag specifies which "runqueue" the allocated channel will be + * executed on in a TSG. Channels on different runqueues within a TSG + * may be able to feed methods into the engine simultaneously. + * Non-default values are only supported on GP10x and later and only for + * channels within a TSG. + */ +#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE 4:4 +#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_DEFAULT 0x00000000 +#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_ONE 0x00000001 + +/* + * NVOS04_FLAGS_PRIVILEGED_CHANNEL: + * This flag tells RM whether to give the channel admin privilege. This + * flag will only take effect if the client is GSP-vGPU plugin. It is + * needed so that guest can update page tables in physical mode and do + * scrubbing. + */ +#define NVOS04_FLAGS_PRIVILEGED_CHANNEL 5:5 +#define NVOS04_FLAGS_PRIVILEGED_CHANNEL_FALSE 0x00000000 +#define NVOS04_FLAGS_PRIVILEGED_CHANNEL_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING: + * This flags tells RM not to schedule a newly created channel within a + * channel group immediately even if channel group is currently scheduled. + * Channel will not be scheduled until NVA06F_CTRL_GPFIFO_SCHEDULE is + * invoked. This is used eg. for CUDA which needs to do additional + * initialization before starting up a channel. + * Default is FALSE. + */ +#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING 6:6 +#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_FALSE 0x00000000 +#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_DENY_PHYSICAL_MODE_CE: + * This flag specifies whether or not to deny access to the physical + * mode of CopyEngine regardless of whether or not the client handle + * is admin. If set to true, this channel allocation will always result + * in an unprivileged channel. If set to false, the privilege of the channel + * will depend on the privilege level of the client handle. + * This is primarily meant for vGPU since all client handles + * granted to guests are admin. + */ +#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE 7:7 +#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_CHANNEL_USERD_INDEX_VALUE + * + * This flag specifies the channel offset in terms of within a page of + * USERD. For example, value 3 means the 4th channel within a USERD page. + * Given the USERD size is 512B, we will have 8 channels total, so 3 bits + * are reserved. + * + * When _USERD_INDEX_FIXED_TRUE is set but INDEX_PAGE_FIXED_FALSE is set, + * it will ask for a new USERD page. + * + */ +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_VALUE 10:8 + +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED 11:11 +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_VALUE + * + * This flag specifies the channel offset in terms of USERD page. When + * this PAGE_FIXED_TRUE is set, the INDEX_FIXED_FALSE bit should also + * be set, otherwise INVALID_STATE will be returned. + * + * And the field _USERD_INDEX_VALUE will be used to request the specific + * offset within a USERD page. + */ + +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_VALUE 20:12 + +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED 21:21 +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_DENY_AUTH_LEVEL_PRIV + * This flag specifies whether or not to deny access to the privileged + * host methods TLB_INVALIDATE and ACCESS_COUNTER_CLR + */ +#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV 22:22 +#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER + * + * This flag specifies scrubbing should be skipped for any internal + * allocations made for this channel from PMA using ctx buf pools. + * Only kernel clients are allowed to use this setting. + */ +#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER 23:23 +#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO + * + * This flag specifies that the client is expected to map USERD themselves + * and RM need not do so. + */ +#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO 24:24 +#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL + */ +#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL 25:25 +#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_FALSE 0x00000000 +#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT + * + * This flag specifies whether the channel calling context is from CPU + * VGPU plugin. + */ +#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT 26:26 +#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_TRUE 0x00000001 + + /* + * NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT + * + * This flag specifies the channel PBDMA ACQUIRE timeout option. + * _FALSE to disable it, _TRUE to enable it. + * When this flag is enabled, if a host semaphore acquire does not + * complete in about 2 sec, it will time out and trigger a RC error. + */ +#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT 27:27 +#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_GROUP_CHANNEL_THREAD: + * This flags specifies the thread id in which an allocated channel + * will be executed in a TSG. The relationship between the thread id + * in A TSG and respective definitions are implementation specific. + * Also, not all classes will be supported at thread > 0. + * This field cannot be used on non-TSG channels and must be set to + * the default value (0) in that case. If thread > 0 on a non-TSG + * channel, the allocation will fail + */ +#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD 29:28 +#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_DEFAULT 0x00000000 +#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_ONE 0x00000001 +#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_TWO 0x00000002 + +#define NVOS04_FLAGS_MAP_CHANNEL 30:30 +#define NVOS04_FLAGS_MAP_CHANNEL_FALSE 0x00000000 +#define NVOS04_FLAGS_MAP_CHANNEL_TRUE 0x00000001 + +#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC 31:31 +#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_FALSE 0x00000000 +#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_TRUE 0x00000001 + + + +#define CC_CHAN_ALLOC_IV_SIZE_DWORD 3U +#define CC_CHAN_ALLOC_NONCE_SIZE_DWORD 8U + +#define NV_CHANNEL_ALLOC_PARAMS_MESSAGE_ID (0x906fU) + +typedef struct NV_CHANNEL_ALLOC_PARAMS { + + NvHandle hObjectError; // error context DMA + NvHandle hObjectBuffer; // no longer used + NV_DECLARE_ALIGNED(NvU64 gpFifoOffset, 8); // offset to beginning of GP FIFO + NvU32 gpFifoEntries; // number of GP FIFO entries + + NvU32 flags; + + + NvHandle hContextShare; // context share handle + + // Pointer-based VASpace for the channel. + NvHandle hVASpace; + + // Handle-based VASpace for the channel. + NvHandle hHandleVASpace; + + // handle to UserD memory object for channel, ignored if hUserdMemory[0]=0 + NvHandle hUserdMemory[NV_MAX_SUBDEVICES]; + + // offset to beginning of UserD within hUserdMemory[x] + NV_DECLARE_ALIGNED(NvU64 userdOffset[NV_MAX_SUBDEVICES], 8); + + // engine type(NV2080_ENGINE_TYPE_*) with which this channel is associated + NvU32 engineType; + // Channel identifier that is unique for the duration of a RM session + NvU32 cid; + // One-hot encoded bitmask to match SET_SUBDEVICE_MASK methods + NvU32 subDeviceId; + NvHandle hObjectEccError; // ECC error context DMA + + NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS instanceMem, 8); + NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS userdMem, 8); + NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS ramfcMem, 8); + NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS mthdbufMem, 8); + + NvHandle hPhysChannelGroup; // reserved + NvU32 internalFlags; // reserved + NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS errorNotifierMem, 8); // reserved + NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS eccErrorNotifierMem, 8); // reserved + NvU32 ProcessID; // reserved + NvU32 SubProcessID; // reserved + + // IV used for CPU-side encryption / GPU-side decryption. + NvU32 encryptIv[CC_CHAN_ALLOC_IV_SIZE_DWORD]; // reserved + // IV used for CPU-side decryption / GPU-side encryption. + NvU32 decryptIv[CC_CHAN_ALLOC_IV_SIZE_DWORD]; // reserved + // Nonce used CPU-side signing / GPU-side signature verification. + NvU32 hmacNonce[CC_CHAN_ALLOC_NONCE_SIZE_DWORD]; // reserved + NvU32 tpcConfigID; // TPC Configuration Id as supported by DTD-PG Feature +} NV_CHANNEL_ALLOC_PARAMS; + +typedef NV_CHANNEL_ALLOC_PARAMS NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/cc_drv.h b/userspace/sdks/nv570/inc/cc_drv.h new file mode 100644 index 0000000..6d7a09a --- /dev/null +++ b/userspace/sdks/nv570/inc/cc_drv.h @@ -0,0 +1,101 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: cc_drv.finn +// + + + +#include "nvtypes.h" +#include "nvcfg_sdk.h" + +// CLASS NV_CONF_COMPUTE +#define CC_AES_256_GCM_IV_SIZE_BYTES (0xcU) /* finn: Evaluated from "(96 / 8)" */ +#define CC_AES_256_GCM_IV_SIZE_DWORD (0x3U) /* finn: Evaluated from "(CC_AES_256_GCM_IV_SIZE_BYTES / 4)" */ +#define CC_AES_256_GCM_KEY_SIZE_BYTES (0x20U) /* finn: Evaluated from "(256 / 8)" */ +#define CC_AES_256_GCM_KEY_SIZE_DWORD (0x8U) /* finn: Evaluated from "(CC_AES_256_GCM_KEY_SIZE_BYTES / 4)" */ + +#define CC_HMAC_NONCE_SIZE_BYTES (0x20U) /* finn: Evaluated from "(256 / 8)" */ +#define CC_HMAC_NONCE_SIZE_DWORD (0x8U) /* finn: Evaluated from "(CC_HMAC_NONCE_SIZE_BYTES / 4)" */ +#define CC_HMAC_KEY_SIZE_BYTES (0x20U) /* finn: Evaluated from "(256 / 8)" */ +#define CC_HMAC_KEY_SIZE_DWORD (0x8U) /* finn: Evaluated from "(CC_HMAC_KEY_SIZE_BYTES / 4)" */ + + +// Type is shared between CC control calls and RMKeyStore +typedef enum ROTATE_IV_TYPE { + ROTATE_IV_ENCRYPT = 0, // Rotate the IV for encryptBundle + ROTATE_IV_DECRYPT = 1, // Rotate the IV for decryptBundle + ROTATE_IV_HMAC = 2, // Rotate the IV for hmacBundle + ROTATE_IV_ALL_VALID = 3, // Rotate the IV for all valid bundles in the KMB +} ROTATE_IV_TYPE; + +// Status value written into NvNotification.Info16 +typedef enum KEY_ROTATION_STATUS { + KEY_ROTATION_STATUS_IDLE = 0, // Key rotation complete/not in progress + KEY_ROTATION_STATUS_PENDING = 1, // RM is waiting for clients to report their channels are idle for key rotation + KEY_ROTATION_STATUS_IN_PROGRESS = 2, // Key rotation is in progress + KEY_ROTATION_STATUS_FAILED_TIMEOUT = 3, // Key rotation timeout failure, RM will RC non-idle channels + KEY_ROTATION_STATUS_FAILED_THRESHOLD = 4, // Key rotation failed because upper threshold was crossed, RM will RC non-idle channels + KEY_ROTATION_STATUS_FAILED_ROTATION = 5, // Internal RM failure while rotating keys for a certain channel, RM will RC the channel + KEY_ROTATION_STATUS_PENDING_TIMER_SUSPENDED = 6, // Key rotation timer suspended waiting for kernel key rotation to complete + KEY_ROTATION_STATUS_MAX_COUNT = 7, +} KEY_ROTATION_STATUS; + +typedef struct CC_AES_CRYPTOBUNDLE { + NvU32 iv[CC_AES_256_GCM_IV_SIZE_DWORD]; + NvU32 key[CC_AES_256_GCM_KEY_SIZE_DWORD]; + NvU32 ivMask[CC_AES_256_GCM_IV_SIZE_DWORD]; +} CC_AES_CRYPTOBUNDLE; +typedef struct CC_AES_CRYPTOBUNDLE *PCC_AES_CRYPTOBUNDLE; + +typedef struct CC_HMAC_CRYPTOBUNDLE { + NvU32 nonce[CC_HMAC_NONCE_SIZE_DWORD]; + NvU32 key[CC_HMAC_KEY_SIZE_DWORD]; +} CC_HMAC_CRYPTOBUNDLE; +typedef struct CC_HMAC_CRYPTOBUNDLE *PCC_HMAC_CRYPTOBUNDLE; + +typedef struct CC_KMB { + CC_AES_CRYPTOBUNDLE encryptBundle; // Bundle of encyption material + + union { + CC_HMAC_CRYPTOBUNDLE hmacBundle; // HMAC bundle used for method stream authenticity + CC_AES_CRYPTOBUNDLE decryptBundle; // Bundle of decryption material + }; + NvBool bIsWorkLaunch; // False if decryption parameters are valid +} CC_KMB; +typedef struct CC_KMB *PCC_KMB; + +typedef struct CC_CRYPTOBUNDLE_STATS { + NV_DECLARE_ALIGNED(NvU64 numEncryptionsH2D, 8); + NV_DECLARE_ALIGNED(NvU64 numEncryptionsD2H, 8); + NV_DECLARE_ALIGNED(NvU64 bytesEncryptedH2D, 8); + NV_DECLARE_ALIGNED(NvU64 bytesEncryptedD2H, 8); +} CC_CRYPTOBUNDLE_STATS; +typedef struct CC_CRYPTOBUNDLE_STATS *PCC_CRYPTOBUNDLE_STATS; + diff --git a/userspace/sdks/nv570/inc/class/cl0000.h b/userspace/sdks/nv570/inc/class/cl0000.h new file mode 100644 index 0000000..b56b157 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl0000.h @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0000.finn +// + +#include "nvlimits.h" +#include "cl0000_notification.h" + +/* object NV01_NULL_OBJECT */ +#define NV01_NULL_OBJECT (0x0) /* finn: Evaluated from "NV0000_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* obsolete alises */ +#define NV1_NULL_OBJECT NV01_NULL_OBJECT + +#define NV01_ROOT (0x0U) /* finn: Evaluated from "NV0000_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* NvAlloc parameteters */ +#define NV0000_ALLOC_PARAMETERS_MESSAGE_ID (0x0000U) + +typedef struct NV0000_ALLOC_PARAMETERS { + NvHandle hClient; /* CORERM-2934: hClient must remain the first member until all allocations use these params */ + NvU32 processID; + char processName[NV_PROC_NAME_MAX_LENGTH]; + NV_DECLARE_ALIGNED(NvP64 pOsPidInfo, 8); +} NV0000_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/cl0000_notification.h b/userspace/sdks/nv570/inc/class/cl0000_notification.h new file mode 100644 index 0000000..9c91de3 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl0000_notification.h @@ -0,0 +1,60 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0000_notification_h_ +#define _cl0000_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/*Status definitions for NV0000_NOTIFIERS_DISPLAY_CHANGE event*/ + +#define NV0000_NOTIFIERS_STATUS_ACPI_DISPLAY_DEVICE_CYCLE (0) + +//--------------------------------------------------------------------------- + +/* NvNotification[] fields and values */ +#define NV000_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + + +/* pio method data structure */ +typedef volatile struct _cl0000_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv000Typedef, Nv01Root; + +/* obsolete aliases */ +#define NV000_TYPEDEF Nv01Root +#define Nv1Root Nv01Root +#define nv1Root Nv01Root +#define nv01Root Nv01Root + +/*event values*/ +#define NV0000_NOTIFIERS_ENABLE_CPU_UTIL_CTRL (1) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0000_notification_h_ */ + diff --git a/userspace/sdks/nv570/inc/class/cl0001.h b/userspace/sdks/nv570/inc/class/cl0001.h new file mode 100644 index 0000000..10a8af4 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl0001.h @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2013 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0001_h_ +#define _cl0001_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV01_ROOT_NON_PRIV (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0001_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl0002.h b/userspace/sdks/nv570/inc/class/cl0002.h new file mode 100644 index 0000000..dd1d6c6 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl0002.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2001-2001, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0002_h_ +#define _cl0002_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV01_CONTEXT_DMA_FROM_MEMORY (0x00000002) +/* NvNotification[] fields and values */ +#define NV002_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +typedef volatile struct _cl0002_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv002Typedef, Nv01ContextDmaFromMemory; +#define NV002_TYPEDEF Nv01ContextDmaFromMemory +/* obsolete stuff */ +#define NV1_CONTEXT_DMA_FROM_MEMORY (0x00000002) +#define NV01_CONTEXT_DMA (0x00000002) +#define Nv1ContextDmaFromMemory Nv01ContextDmaFromMemory +#define nv1ContextDmaFromMemory Nv01ContextDmaFromMemory +#define nv01ContextDmaFromMemory Nv01ContextDmaFromMemory + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0002_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl0004.h b/userspace/sdks/nv570/inc/class/cl0004.h new file mode 100644 index 0000000..32e25e7 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl0004.h @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0004_h_ +#define _cl0004_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV01_TIMER (0x00000004) +/* NvNotification[] elements */ +#define NV004_NOTIFIERS_SET_ALARM_NOTIFY (0) +#define NV004_NOTIFIERS_MAXCOUNT (1) + +/* mapped timer registers */ +typedef volatile struct _Nv01TimerMapTypedef { + NvU32 Reserved00[0x100]; + NvU32 PTimerTime0; /* 0x00009400 */ + NvU32 Reserved01[0x3]; + NvU32 PTimerTime1; /* 0x00009410 */ +} Nv01TimerMap; + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0004_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl0005.h b/userspace/sdks/nv570/inc/class/cl0005.h new file mode 100644 index 0000000..f3f5b53 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl0005.h @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0005.finn +// + +#include "cl0005_notification.h" + +#define NV01_EVENT (0x5U) /* finn: Evaluated from "NV0005_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* NvRmAlloc() parameters */ +#define NV0005_ALLOC_PARAMETERS_MESSAGE_ID (0x0005U) + +typedef struct NV0005_ALLOC_PARAMETERS { + NvHandle hParentClient; + NvHandle hSrcResource; + + NvV32 hClass; + NvV32 notifyIndex; + NV_DECLARE_ALIGNED(NvP64 data, 8); +} NV0005_ALLOC_PARAMETERS; + + +/* NV0005_ALLOC_PARAMETERS's notifyIndex field is overloaded to contain the + * notifyIndex value itself, plus flags, and optionally a subdevice field if + * flags contains NV01_EVENT_SUBDEVICE_SPECIFIC. Note that NV01_EVENT_* + * contain the full 32-bit flag value that is OR'd into notifyIndex, not the + * contents of the FLAGS field (i.e. NV01_EVENT_* are pre-shifted into place). + */ +#define NV0005_NOTIFY_INDEX_INDEX 15:0 +#define NV0005_NOTIFY_INDEX_SUBDEVICE 23:16 +#define NV0005_NOTIFY_INDEX_FLAGS 31:24 diff --git a/userspace/sdks/nv570/inc/class/cl0005_notification.h b/userspace/sdks/nv570/inc/class/cl0005_notification.h new file mode 100644 index 0000000..5e6b32e --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl0005_notification.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0005_notification_h_ +#define _cl0005_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* NvNotification[] fields and values */ +#define NV003_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +/* pio method data structure */ +typedef volatile struct _cl0005_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv005Typedef, Nv01Event; + +#define NV005_TYPEDEF Nv01Event + +/* obsolete stuff */ +#define NV1_TIMER (0x00000004) +#define Nv1Event Nv01Event +#define nv1Event Nv01Event +#define nv01Event Nv01Event + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0005_notification_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl000f.h b/userspace/sdks/nv570/inc/class/cl000f.h new file mode 100644 index 0000000..3182bec --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl000f.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl000f.finn +// + +#define FABRIC_MANAGER_SESSION (0xfU) /* finn: Evaluated from "NV000F_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV000F_NOTIFIERS_FABRIC_EVENT (0) + +#define NV000F_FLAGS_CHANNEL_RECOVERY 0:0 +#define NV000F_FLAGS_CHANNEL_RECOVERY_ENABLED 0x0 +#define NV000F_FLAGS_CHANNEL_RECOVERY_DISABLED 0x1 + +#define NV000F_ALLOCATION_PARAMETERS_MESSAGE_ID (0x000fU) + +typedef struct NV000F_ALLOCATION_PARAMETERS { + // + // capDescriptor is a file descriptor for unix RM clients, but a void + // pointer for windows RM clients. + // + // capDescriptor is transparent to RM clients i.e. RM's user-mode shim + // populates this field on behalf of clients. + // + NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8); + + NvU32 flags; +} NV000F_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/cl0020.h b/userspace/sdks/nv570/inc/class/cl0020.h new file mode 100644 index 0000000..87154a9 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl0020.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0020_h_ +#define _cl0020_h_ + +#include "nvtypes.h" + +#define NV0020_GPU_MANAGEMENT (0x00000020) + +#endif /* _cl0020_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl0030.h b/userspace/sdks/nv570/inc/class/cl0030.h new file mode 100644 index 0000000..9a0000e --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl0030.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0030_h_ +#define _cl0030_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV01_NULL (0x00000030) +/* NvNotification[] fields and values */ +#define NV030_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +typedef volatile struct _cl0030_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv030Typedef, Nv01Null; +#define NV030_TYPEDEF Nv01Null +/* obsolete stuff */ +#define NV1_NULL (0x00000030) +#define Nv1Null Nv01Null +#define nv1Null Nv01Null +#define nv01Null Nv01Null + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0030_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl003e.h b/userspace/sdks/nv570/inc/class/cl003e.h new file mode 100644 index 0000000..d23e642 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl003e.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2001-2001, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl003e_h_ +#define _cl003e_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV01_CONTEXT_ERROR_TO_MEMORY (0x0000003E) +#define NV01_MEMORY_SYSTEM (0x0000003E) +/* NvNotification[] fields and values */ +#define NV03E_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +typedef volatile struct _cl003e_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv03eTypedef, Nv01ContextErrorToMemory; +#define NV03E_TYPEDEF Nv01ContextErrorToMemory +/* obsolete stuff */ +#define NV1_CONTEXT_ERROR_TO_MEMORY (0x0000003E) +#define Nv1ContextErrorToMemory Nv01ContextErrorToMemory +#define nv1ContextErrorToMemory Nv01ContextErrorToMemory +#define nv01ContextErrorToMemory Nv01ContextErrorToMemory + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl003e_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl003f.h b/userspace/sdks/nv570/inc/class/cl003f.h new file mode 100644 index 0000000..b124538 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl003f.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2001-2001, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl003f_h_ +#define _cl003f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV01_MEMORY_LOCAL_PRIVILEGED (0x0000003F) +/* NvNotification[] fields and values */ +#define NV03F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +#ifndef AMD64 +typedef volatile struct _cl003f_tag0 { +#else +typedef struct { +#endif + NvV32 Reserved00[0x7c0]; +} Nv01MemoryLocalPrivileged; +#define NV03F_TYPEDEF Nv01MemoryLocalPrivileged +typedef Nv01MemoryLocalPrivileged Nv03fTypedef; +/* obsolete stuff */ +#define NV01_MEMORY_PRIVILEGED (0x0000003F) +#define NV1_MEMORY_PRIVILEGED (0x0000003F) +#define Nv01MemoryPrivileged Nv01MemoryLocalPrivileged +#define nv01MemoryPrivileged Nv01MemoryLocalPrivileged +#define Nv1MemoryPrivileged Nv01MemoryLocalPrivileged +#define nv1MemoryPrivileged Nv01MemoryLocalPrivileged +#define nv01MemoryLocalPrivileged Nv01MemoryLocalPrivileged + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl003f_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl0040.h b/userspace/sdks/nv570/inc/class/cl0040.h new file mode 100644 index 0000000..103ec3a --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl0040.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2001 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl0040_h_ +#define _cl0040_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV01_MEMORY_LOCAL_USER (0x00000040) +/* NvNotification[] fields and values */ +#define NV040_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +typedef volatile struct _cl0040_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv040Typedef, Nv01MemoryLocalUser; +#define NV040_TYPEDEF Nv01MemoryLocalUser +/* obsolete stuff */ +#define NV01_MEMORY_USER (0x00000040) +#define NV1_MEMORY_USER (0x00000040) +#define Nv01MemoryUser Nv01MemoryLocalUser +#define nv01MemoryUser Nv01MemoryLocalUser +#define Nv1MemoryUser Nv01MemoryLocalUser +#define nv1MemoryUser Nv01MemoryLocalUser +#define nv01MemoryLocalUser Nv01MemoryLocalUser + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0040_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl0041.h b/userspace/sdks/nv570/inc/class/cl0041.h new file mode 100644 index 0000000..fa8707a --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl0041.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2001-2005, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0041_h_ +#define _cl0041_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV04_MEMORY (0x00000041) +/* NvNotification[] fields and values */ +#define NV041_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +typedef volatile struct _cl0041_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv041Typedef, Nv04Memory; +#define NV041_TYPEDEF Nv04Memory; + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0041_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl0050.h b/userspace/sdks/nv570/inc/class/cl0050.h new file mode 100644 index 0000000..4181b98 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl0050.h @@ -0,0 +1,81 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0050.finn +// + +#include "nvcfg_sdk.h" + +#define NV_CE_UTILS (0x50U) /* finn: Evaluated from "NV0050_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV0050_ALLOCATION_PARAMETERS_MESSAGE_ID (0x0050U) + +typedef struct NV0050_ALLOCATION_PARAMETERS { + NvHandle hVaspace; + NV_DECLARE_ALIGNED(NvU64 flags, 8); + NvU32 forceCeId; +} NV0050_ALLOCATION_PARAMETERS; + + +// Whether the CeUtils will allocate everything with RM client or external client +#define NV0050_CEUTILS_FLAGS_EXTERNAL 0:0 +#define NV0050_CEUTILS_FLAGS_EXTERNAL_FALSE (0x00000000) +#define NV0050_CEUTILS_FLAGS_EXTERNAL_TRUE (0x00000001) + +// Whether CeUtils will use virtual copy +#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE 1:1 +#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE_FALSE (0x00000000) +#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE_TRUE (0x00000001) + +// Whether the CeUtils is using fifo lite mode. Has to be internal +#define NV0050_CEUTILS_FLAGS_FIFO_LITE 2:2 +#define NV0050_CEUTILS_FLAGS_FIFO_LITE_FALSE (0x00000000) +#define NV0050_CEUTILS_FLAGS_FIFO_LITE_TRUE (0x00000001) + +// Whether the CeUtils will use BAR1 or BAR2 for data copy +#define NV0050_CEUTILS_FLAGS_NO_BAR1_USE 3:3 +#define NV0050_CEUTILS_FLAGS_NO_BAR1_USE_FALSE (0x00000000) +#define NV0050_CEUTILS_FLAGS_NO_BAR1_USE_TRUE (0x00000001) + +// Force a specific CE engine to be used be setting forceCeId +#define NV0050_CEUTILS_FLAGS_FORCE_CE_ID 4:4 +#define NV0050_CEUTILS_FLAGS_FORCE_CE_ID_FALSE (0x00000000) +#define NV0050_CEUTILS_FLAGS_FORCE_CE_ID_TRUE (0x00000001) + +// Use a CC secure channel +#define NV0050_CEUTILS_FLAGS_CC_SECURE 5:5 +#define NV0050_CEUTILS_FLAGS_CC_SECURE_FALSE (0x00000000) +#define NV0050_CEUTILS_FLAGS_CC_SECURE_TRUE (0x00000001) + + + +// Enable callbacks at work completion +#define NV0050_CEUTILS_FLAGS_ENABLE_COMPLETION_CB 6:6 +#define NV0050_CEUTILS_FLAGS_ENABLE_COMPLETION_CB_FALSE (0x00000000) +#define NV0050_CEUTILS_FLAGS_ENABLE_COMPLETION_CB_TRUE (0x00000001) diff --git a/userspace/sdks/nv570/inc/class/cl0060.h b/userspace/sdks/nv570/inc/class/cl0060.h new file mode 100644 index 0000000..cfa88ff --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl0060.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0060.finn +// + +#define NV0060_SYNC_GPU_BOOST (0x60U) /* finn: Evaluated from "NV0060_ALLOC_PARAMETERS_MESSAGE_ID" */ + +#define NV0060_ALLOC_PARAMETERS_MESSAGE_ID (0x0060U) + +typedef struct NV0060_ALLOC_PARAMETERS { + NvU32 gpuBoostGroupId; +} NV0060_ALLOC_PARAMETERS; diff --git a/userspace/sdks/nv570/inc/class/cl0070.h b/userspace/sdks/nv570/inc/class/cl0070.h new file mode 100644 index 0000000..95d173e --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl0070.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2001-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0070.finn +// + +#define NV01_MEMORY_VIRTUAL (0x70U) /* finn: Evaluated from "NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_MESSAGE_ID" */ +#define NV01_MEMORY_SYSTEM_DYNAMIC (0x70U) /* finn: Evaluated from "NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_MESSAGE_ID" */ + +/* + * NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS + * + * Allocation params for NV01_MEMORY_VIRTUAL. + * + * NV01_MEMORY_SYSTEM_DYNAMIC is an alias for NV01_MEMORY_VIRTUAL. This + * was traditionally allocated with RmAllocMemory64(). The default GPU + * virtual address space is used, and the limit of this address space is + * returned in limit. The NV01_MEMORY_SYSTEM_DYNAMIC handle can be + * passed to RmAllocContextDma2() with an offset/limit. The context dma + * handle can then be used as the hDma handle for RmMapMemoryDma. + * + * This behavior is maintained in the RM compatibility shim. + * + * NV01_MEMORY_VIRTUAL replaces this behavior with a single object. + * + * hVASpace - if hVASpace is NV01_NULL_OBJECT the default GPU VA space is + * selected. Alternatively a FERMI_VASPACE_A handle may be specified. + * + * The NV_MEMORY_VIRTUAL_SYSMEM_DYNAMIC_HVASPACE is used for by the + * compatibility layer to emulate NV01_MEMORY_SYSTEM_DYNAMIC semantics. + * + * offset - An offset into the virtual address space may be specified. This + * will limit range of the GPU VA returned by RmMapMemoryDma to be + * above offset. + * + * limit - When limit is zero the maximum limit used. If a non-zero limit + * is specified then it will be used. The final limit is returned. + */ +#define NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_MESSAGE_ID (0x0070U) + +typedef struct NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offset, 8); // [IN] - offset into address space + NV_DECLARE_ALIGNED(NvU64 limit, 8); // [IN/OUT] - limit of address space + NvHandle hVASpace; // [IN] - Address space handle +} NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS; + +#define NV_MEMORY_VIRTUAL_SYSMEM_DYNAMIC_HVASPACE 0xffffffffU + diff --git a/userspace/sdks/nv570/inc/class/cl0071.h b/userspace/sdks/nv570/inc/class/cl0071.h new file mode 100644 index 0000000..be106d3 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl0071.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2001-2001, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0071_h_ +#define _cl0071_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV01_MEMORY_SYSTEM_OS_DESCRIPTOR (0x00000071) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0071_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl0073.h b/userspace/sdks/nv570/inc/class/cl0073.h new file mode 100644 index 0000000..d6a7ec2 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl0073.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2001-2021, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0073_h_ +#define _cl0073_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV04_DISPLAY_COMMON (0x00000073) + +/* event values */ +#define NV0073_NOTIFIERS_SW (0) +#define NV0073_NOTIFIERS_LTM_CALC_TIMEOUT (5) +#define NV0073_NOTIFIERS_MAXCOUNT (6) + + +#define NV0073_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NV0073_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000) +#define NV0073_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000) +#define NV0073_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000) +#define NV0073_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) + +/* pio method data structure */ +typedef volatile struct _cl0073_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv073Typedef, Nv04DisplayCommon; +#define NV073_TYPEDEF Nv04DisplayCommon + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0073_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl0076.h b/userspace/sdks/nv570/inc/class/cl0076.h new file mode 100644 index 0000000..50bd0a9 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl0076.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0076_h_ +#define _cl0076_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV01_MEMORY_FRAMEBUFFER_CONSOLE (0x00000076) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0076_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl007d.h b/userspace/sdks/nv570/inc/class/cl007d.h new file mode 100644 index 0000000..f9d25d9 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl007d.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl007d_h_ +#define _cl007d_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV04_SOFTWARE_TEST (0x0000007D) +#define NV07D 0x00001fff:0x00000000 +/* NvNotification[] elements */ +#define NV07D_NOTIFIERS_NOTIFY (0) +#define NV07D_NOTIFIERS_MAXCOUNT (1) +/* NvNotification[] fields and values */ +#define NV07D_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NV07D_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +#define NV07D_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NV07D_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x1000) +#define NV07D_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x0800) +#define NV07D_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) + +/* pio method data structures */ +typedef volatile struct _cl007d_tag0 { + NvV32 NoOperation; /* ignored 0100-0103*/ + NvV32 Notify; /* NV07D_NOTIFY_* 0104-0107*/ + NvV32 Reserved0104[0x78/4]; + NvV32 SetContextDmaNotifies; /* NV01_CONTEXT_DMA 0180-0183*/ + NvV32 Reserved0184[0x1f7c/4]; +} Nv07dTypedef, Nv04SoftwareTest; + +#define NV07D_TYPEDEF Nv04SoftwareTest +/* dma method offsets, fields, and values */ +#define NV07D_SET_OBJECT (0x00000000) +#define NV07D_NO_OPERATION (0x00000100) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl007d_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl0080.h b/userspace/sdks/nv570/inc/class/cl0080.h new file mode 100644 index 0000000..9e9aad2 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl0080.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0080.finn +// + +#include "nvlimits.h" +#include "cl0080_notification.h" + +#define NV01_DEVICE_0 (0x80U) /* finn: Evaluated from "NV0080_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* NvAlloc parameteters */ +#define NV0080_MAX_DEVICES NV_MAX_DEVICES + +/** + * @brief Alloc param + * + * @param vaMode mode for virtual address space allocation + * Three modes: + * NV_DEVICE_ALLOCATION_VAMODE_OPTIONAL_MULTIPLE_VASPACES + * NV_DEVICE_ALLOCATION_VAMODE_SINGLE_VASPACE + * NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES + * Detailed description of these modes is in nvos.h + **/ + +#define NV0080_ALLOC_PARAMETERS_MESSAGE_ID (0x0080U) + +typedef struct NV0080_ALLOC_PARAMETERS { + NvU32 deviceId; + NvHandle hClientShare; + NvHandle hTargetClient; + NvHandle hTargetDevice; + NvV32 flags; + NV_DECLARE_ALIGNED(NvU64 vaSpaceSize, 8); + NV_DECLARE_ALIGNED(NvU64 vaStartInternal, 8); + NV_DECLARE_ALIGNED(NvU64 vaLimitInternal, 8); + NvV32 vaMode; +} NV0080_ALLOC_PARAMETERS; diff --git a/userspace/sdks/nv570/inc/class/cl0080_notification.h b/userspace/sdks/nv570/inc/class/cl0080_notification.h new file mode 100644 index 0000000..a976d3f --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl0080_notification.h @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0080_notification_h_ +#define _cl0080_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* NvNotification[] fields and values */ +#define NV080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +/* pio method data structure */ +typedef volatile struct _cl0080_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv080Typedef, Nv01Device0; + +#define NV080_TYPEDEF Nv01Device0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0080_notification_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl008f.h b/userspace/sdks/nv570/inc/class/cl008f.h new file mode 100644 index 0000000..63f59e8 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl008f.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl008f.finn +// + +#define KERNEL_WATCHDOG 0x008FU + diff --git a/userspace/sdks/nv570/inc/class/cl0090.h b/userspace/sdks/nv570/inc/class/cl0090.h new file mode 100644 index 0000000..1ed7835 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl0090.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl0090_h_ +#define _cl0090_h_ + +#include "nvtypes.h" + +#define KERNEL_GRAPHICS_CONTEXT (0x00000090) + +#endif /* _cl0090_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl0092.h b/userspace/sdks/nv570/inc/class/cl0092.h new file mode 100644 index 0000000..3008277 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl0092.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0092.finn +// + +#include "class/cl0092_callback.h" + +/* + * This RgLineCallback class allows RM clients to register/unregister the RG line callback functions. + * + * Must be allocated with kernel access rights. + * + * Allocation params: + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the NV04_DISPLAY_COMMON parent device to which the + * operation should be directed. + * head + * This parameter specifies the head for which the callback is to be egistered/unregistered. This value must be + * less than the maximum number of heads supported by the GPU subdevice. + * rgLineNum + * This indicates the RG scanout line number on which the callback will be executed. + * 1/ Client should set the proper RG line number based on mode in which the display head is running and + * subsequent possible modeset that may affect the line number. + * 2/ Client is expected to clear/set the interrupts around modesets or power-transitions (like s3/hibernation). + * 3/ Client should make sure that this param does not exceed the raster settings. + * pCallbkFn + * Pointer to callback function. Cannot be NULL. + * pCallbkParams + * Pointer to the ctrl call param struct. + */ + +#define NV0092_RG_LINE_CALLBACK (0x92U) /* finn: Evaluated from "NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS_MESSAGE_ID (0x0092U) + +typedef struct NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS { + NvU32 subDeviceInstance; + NvU32 head; + NvU32 rgLineNum; + + NV_DECLARE_ALIGNED(NvP64 pCallbkFn, 8); /* A function pointer of NV0092_REGISTER_RG_LINE_CALLBACK_FN */ + + NV_DECLARE_ALIGNED(NvP64 pCallbkParams, 8); /* The param1 in NV0092_REGISTER_RG_LINE_CALLBACK_FN */ +} NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/cl0092_callback.h b/userspace/sdks/nv570/inc/class/cl0092_callback.h new file mode 100644 index 0000000..4cd86ad --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl0092_callback.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef SDK_CL0092_CALLBACK_H +#define SDK_CL0092_CALLBACK_H + +typedef void (*NV0092_REGISTER_RG_LINE_CALLBACK_FN)(NvU32 rgIntrLine, NvP64 param1, NvBool bIsIrqlIsr); + +#endif // SDK_CL0092_CALLBACK_H diff --git a/userspace/sdks/nv570/inc/class/cl00b1.h b/userspace/sdks/nv570/inc/class/cl00b1.h new file mode 100644 index 0000000..bc6e69f --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl00b1.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _CL00B1_H_ +#define _CL00B1_H_ + +#define NV01_MEMORY_HW_RESOURCES 0x00b1 + +#endif // _CL00B1_H_ diff --git a/userspace/sdks/nv570/inc/class/cl00c1.h b/userspace/sdks/nv570/inc/class/cl00c1.h new file mode 100644 index 0000000..d95e4fd --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl00c1.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00c1.finn +// + +#include "nvlimits.h" +#define NV_FB_SEGMENT (0xc1U) /* finn: Evaluated from "NV_FB_SEGMENT_ALLOCATION_PARAMS_MESSAGE_ID" */ + +/* + * NV_FB_SEGMENT_ALLOCATION_PARAMS - Allocation params to create FB segment through + * NvRmAlloc. + */ +#define NV_FB_SEGMENT_ALLOCATION_PARAMS_MESSAGE_ID (0x00C1U) + +typedef struct NV_FB_SEGMENT_ALLOCATION_PARAMS { + NvHandle hCtxDma; // unused + NvU32 subDeviceIDMask; + NV_DECLARE_ALIGNED(NvU64 dmaOffset, 8); // unused + NV_DECLARE_ALIGNED(NvU64 VidOffset, 8); + NV_DECLARE_ALIGNED(NvU64 Offset, 8); // To be deprecated + NV_DECLARE_ALIGNED(NvU64 pOffset[NV_MAX_SUBDEVICES], 8); + NV_DECLARE_ALIGNED(NvU64 Length, 8); + NV_DECLARE_ALIGNED(NvU64 ValidLength, 8); + NV_DECLARE_ALIGNED(NvP64 pPageArray, 8); + NvU32 startPageIndex; + NvHandle AllocHintHandle; + NvU32 Flags; + NvHandle hMemory; // Not used in NvRmAlloc path; only used in CTRL path + NvHandle hClient; // Not used in NvRmAlloc path; only used in CTRL path + NvHandle hDevice; // Not used in NvRmAlloc path; only used in CTRL path + NV_DECLARE_ALIGNED(NvP64 pCpuAddress, 8); // To be deprecated + NV_DECLARE_ALIGNED(NvP64 ppCpuAddress[NV_MAX_SUBDEVICES], 8); + NV_DECLARE_ALIGNED(NvU64 GpuAddress, 8); // To be deprecated + NV_DECLARE_ALIGNED(NvU64 pGpuAddress[NV_MAX_SUBDEVICES], 8); + NvHandle hAllocHintClient; + NvU32 kind; + NvU32 compTag; +} NV_FB_SEGMENT_ALLOCATION_PARAMS; + diff --git a/userspace/sdks/nv570/inc/class/cl00c2.h b/userspace/sdks/nv570/inc/class/cl00c2.h new file mode 100644 index 0000000..db3ea00 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl00c2.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00c2.finn +// + +#define NV01_MEMORY_LOCAL_PHYSICAL (0xc2U) /* finn: Evaluated from "NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID" */ + +#define NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID (0x00c2U) + +typedef struct NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS { + NV_DECLARE_ALIGNED(NvU64 memSize, 8); // [OUT] + NvU32 format; // [IN] - PTE format to use + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); // [IN] - Page size to use +} NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS; + diff --git a/userspace/sdks/nv570/inc/class/cl00c3.h b/userspace/sdks/nv570/inc/class/cl00c3.h new file mode 100644 index 0000000..eb9e1cb --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl00c3.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00c3.finn +// + +#define NV01_MEMORY_SYNCPOINT (0xc3U) /* finn: Evaluated from "NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS_MESSAGE_ID" */ + +/* + * NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS - Allocation params to create syncpoint + * through NvRmAlloc. + */ +#define NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS_MESSAGE_ID (0x00c3U) + +typedef struct NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS { + NvU32 syncpointId; +} NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS; + diff --git a/userspace/sdks/nv570/inc/class/cl00da.h b/userspace/sdks/nv570/inc/class/cl00da.h new file mode 100644 index 0000000..871f913 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl00da.h @@ -0,0 +1,85 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00da.finn +// + + + +/* +* NV_SEMAPHORE_SURFACE +* A semaphore surface object contains a GPU-and-CPU-accessible memory region +* containing semaphores, associated monitored fence values, and any other +* related data necessary to implement a circular 32-bit or monotonic 64-bit +* incrementing semaphore primitive and associated event delivery. +*/ +#define NV_SEMAPHORE_SURFACE (0xdaU) /* finn: Evaluated from "NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS_MESSAGE_ID" */ + + /* + * NV_SEMAPHORE_SURFACE_WAIT_VALUE + * The notification index used when registering events with the RM event + * subsystem. RM clients should not need to use this value, as they don't + * allocate events against this class themselves. Rather, they specify an + * OS event when registering a CPU waiter, and semaphore surface takes care + * of creating event objects internally as necessary, similar to the event + * buffer record notification OS event mechanism. + */ +#define NV_SEMAPHORE_SURFACE_WAIT_VALUE (0x00000000) + +/* +* NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS +* +* hSemaphoreMem [IN] +* The handle to the memory used for the semaphore value and, when +* supported, the monitored fence/conditional interrupt value. Must be +* accessible by the GPU corresponding to the parent of the semaphore +* surface, as well as the CPU. +* +* hMaxSubmittedMem [IN] +* The handle to the memory used to track the maximum signal value +* submitted to the GPU for processing for a given semaphore slot in +* hSemaphoreMem. This memory is only accessed by the CPU, but must +* support a CPU mapping that allows the use of 64-bit atomic exchange +* operations. This may be the same memory object as hSemaphoreMem if it is +* possible to create one memory object that supports all the requirements +* for a given GPU and CPU. This handle may be omitted/set to zero on GPUs +* that do not require maximum submitted value tracking. +* +* flags [IN] +* Flags affecting the semaphore surface allocation. Currently, there are +* not valid flags, so this value must be set to zero. +*/ +#define NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS_MESSAGE_ID (0x00DAU) + +typedef struct NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS { + NvHandle hSemaphoreMem; + NvHandle hMaxSubmittedMem; + NV_DECLARE_ALIGNED(NvU64 flags, 8); +} NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/cl00db.h b/userspace/sdks/nv570/inc/class/cl00db.h new file mode 100644 index 0000000..adb5c4f --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl00db.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00db.finn +// + +#define NV40_DEBUG_BUFFER (0xdbU) /* finn: Evaluated from "NV00DB_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* NvRmAlloc() parameters */ +#define NV00DB_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00dbU) + +typedef struct NV00DB_ALLOCATION_PARAMETERS { + NvU32 size; /* Desired message size / actual size returned */ + NvU32 tag; /* Protobuf tag for message location in dump message */ +} NV00DB_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/cl00de.h b/userspace/sdks/nv570/inc/class/cl00de.h new file mode 100644 index 0000000..c465c9f --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl00de.h @@ -0,0 +1,511 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl00de_h_ +#define _cl00de_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvmisc.h" +#include "nvfixedtypes.h" +#include "ctrl/ctrl2080/ctrl2080ecc.h" + +#define RM_USER_SHARED_DATA (0x000000de) + +#define RUSD_TIMESTAMP_WRITE_IN_PROGRESS (NV_U64_MAX) +#define RUSD_TIMESTAMP_INVALID 0 + +#define RUSD_SEQ_START (0xFF00000000000000LLU) + +#define RUSD_SEQ_DATA_VALID(x) \ + ((((x) < RUSD_SEQ_START) && ((x) != RUSD_TIMESTAMP_INVALID)) || \ + (((x) >= RUSD_SEQ_START) && (((x) & 0x1LLU) == 0x0LLU))) + +// +// Helper macros to check seq before reading RUSD. +// No dowhile wrap as it is using continue/break +// +#define RUSD_SEQ_CHECK1(dataField) \ + NvU64 RUSD_SEQ = (dataField)->lastModifiedTimestamp; \ + portAtomicMemoryFenceLoad(); \ + if (!RUSD_SEQ_DATA_VALID(RUSD_SEQ)) \ + continue; + +// Clear lastModifiedTimestamp on failure in case of reaching loop limit +#define RUSD_SEQ_CHECK2(dataField) \ + portAtomicMemoryFenceLoad(); \ + if (RUSD_SEQ == (dataField)->lastModifiedTimestamp) \ + break; \ + +// +// Read RUSD data field `dataField` from NV00DE_SHARED_DATA struct `pSharedData` into destination pointer `pDst` +// `pDst` should be the data struct type matching `dataField` +// Check (pDst)->lastModifiedTimestamp using RUSD_IS_DATA_STALE to verify data validity. +// +#define RUSD_READ_DATA(pSharedData,dataField,pDst) \ +do { \ + portMemSet((pDst), 0, sizeof(*pDst)); \ + for (NvU32 RUSD_READ_DATA_ATTEMPTS = 0; RUSD_READ_DATA_ATTEMPTS < 10; ++RUSD_READ_DATA_ATTEMPTS) \ + { \ + RUSD_SEQ_CHECK1(&((pSharedData)->dataField)); \ + portMemCopy((pDst), sizeof(*pDst), &((pSharedData)->dataField), sizeof(*pDst)); \ + RUSD_SEQ_CHECK2(&((pSharedData)->dataField)); \ + (pDst)->lastModifiedTimestamp = RUSD_TIMESTAMP_INVALID; \ + } \ +} while(0); + +// +// Check if RUSD data timestamp is stale. +// For polled data, returns true if data is older than `staleThreshold` +// For non-polled data, returns true if data was successfully read +// +#define RUSD_IS_DATA_STALE(timestamp,currentTime,staleThreshold) \ + ((((timestamp) < (RUSD_SEQ_START)) && /* Polled Data */ \ + (((timestamp) == (RUSD_TIMESTAMP_INVALID)) || /* Invalid */ \ + (((currentTime) - (timestamp)) > (staleThreshold)))) || \ + (((timestamp) >= (RUSD_SEQ_START)) && /* Non-Polled Data */ \ + (((timestamp) & (0x1LLU)) == 1LLU))) + +enum { + RUSD_CLK_THROTTLE_REASON_GPU_IDLE = NVBIT(0), + RUSD_CLK_THROTTLE_REASON_APPLICATION_CLOCK_SETTING = NVBIT(1), + RUSD_CLK_THROTTLE_REASON_SW_POWER_CAP = NVBIT(2), + RUSD_CLK_THROTTLE_REASON_HW_SLOWDOWN = NVBIT(3), + RUSD_CLK_THROTTLE_REASON_SYNC_BOOST = NVBIT(4), + RUSD_CLK_THROTTLE_REASON_SW_THERMAL_SLOWDOWN = NVBIT(5), + RUSD_CLK_THROTTLE_REASON_HW_THERMAL_SLOWDOWN = NVBIT(6), + RUSD_CLK_THROTTLE_REASON_HW_POWER_BRAKES_SLOWDOWN = NVBIT(7), + RUSD_CLK_THROTTLE_REASON_DISPLAY_CLOCK_SETTING = NVBIT(8), +}; + +typedef struct RUSD_BAR1_MEMORY_INFO { + volatile NvU64 lastModifiedTimestamp; + // + // Non-polled data, not tied to any specific RM API + // Total size and available memory in Bar1 + // + NvU32 bar1Size; + NvU32 bar1AvailSize; +} RUSD_BAR1_MEMORY_INFO; + +typedef struct RUSD_PMA_MEMORY_INFO { + volatile NvU64 lastModifiedTimestamp; + // + // Non-polled data, not tied to any specific RM API + // Total size and available memory in PMA + // + NvU64 totalPmaMemory; + NvU64 freePmaMemory; +} RUSD_PMA_MEMORY_INFO; + +enum { + RUSD_CLK_PUBLIC_DOMAIN_GRAPHICS = 0, + RUSD_CLK_PUBLIC_DOMAIN_MEMORY, + RUSD_CLK_PUBLIC_DOMAIN_VIDEO, + + // Put at the end. See bug 1000230 NVML doesn't report SM frequency on Kepler + RUSD_CLK_PUBLIC_DOMAIN_SM, + RUSD_CLK_PUBLIC_DOMAIN_MAX_TYPE, +}; + +typedef struct RUSD_CLK_PUBLIC_DOMAIN_INFO { + NvU32 targetClkMHz; + NvU32 actualClkKHz; +} RUSD_CLK_PUBLIC_DOMAIN_INFO; + +typedef struct RUSD_CLK_PUBLIC_DOMAIN_INFOS { + volatile NvU64 lastModifiedTimestamp; + RUSD_CLK_PUBLIC_DOMAIN_INFO info[RUSD_CLK_PUBLIC_DOMAIN_MAX_TYPE]; +} RUSD_CLK_PUBLIC_DOMAIN_INFOS; + +typedef struct RUSD_ENG_UTILIZATION { + NvU32 clkPercentBusy; + NvU32 samplingPeriodUs; +} RUSD_ENG_UTILIZATION; + +#define RUSD_ENG_UTILIZATION_VID_ENG_NVENC 0 +#define RUSD_ENG_UTILIZATION_VID_ENG_NVDEC 1 +#define RUSD_ENG_UTILIZATION_VID_ENG_NVJPG 2 +#define RUSD_ENG_UTILIZATION_VID_ENG_NVOFA 3 +#define RUSD_ENG_UTILIZATION_COUNT 4 + +typedef struct RUSD_PERF_DEVICE_UTILIZATION_INFO { + NvU32 gpuPercentBusy; + NvU32 memoryPercentBusy; + RUSD_ENG_UTILIZATION engUtil[RUSD_ENG_UTILIZATION_COUNT]; +} RUSD_PERF_DEVICE_UTILIZATION_INFO; + +typedef struct RUSD_PERF_DEVICE_UTILIZATION { + volatile NvU64 lastModifiedTimestamp; + RUSD_PERF_DEVICE_UTILIZATION_INFO info; +} RUSD_PERF_DEVICE_UTILIZATION; + +typedef struct RUSD_PERF_CURRENT_PSTATE { + volatile NvU64 lastModifiedTimestamp; + // Provided from NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE + NvU32 currentPstate; +} RUSD_PERF_CURRENT_PSTATE; + +#define RUSD_CLK_VIOLATION_NUM 32 + +#define RUSD_PERF_POINT_MAX_CLOCK 0 +#define RUSD_PERF_POINT_TURBO_BOOST 1 +#define RUSD_PERF_POINT_3D_BOOST 2 +#define RUSD_PERF_POINT_RATED_TDP 3 +#define RUSD_PERF_POINT_MAX_CUSTOMER_BOOST 4 +#define RUSD_PERF_POINT_DISPLAY_CLOCK_INTERSECT 5 +#define RUSD_PERF_POINT_NUM 6 + +typedef struct RUSD_CLK_VIOLATION_STATUS { + NvU32 perfPointMask; + NvU64 timeNs[RUSD_PERF_POINT_NUM]; +} RUSD_CLK_VIOLATION_STATUS; + +typedef struct RUSD_CLK_THROTTLE_INFO { + volatile NvU64 lastModifiedTimestamp; + NvU32 reasonMask; // Bitmask of RUSD_CLK_THROTTLE_REASON_* + + NvU64 referenceTimeNs; + NvU32 supportedViolationTimeMask; + RUSD_CLK_VIOLATION_STATUS violation[RUSD_CLK_VIOLATION_NUM]; + RUSD_CLK_VIOLATION_STATUS globalViolation; +} RUSD_CLK_THROTTLE_INFO; + +typedef struct RUSD_CLK_THROTTLE_INFO RUSD_CLK_THROTTLE_REASON; + +typedef struct RUSD_MEM_ERROR_COUNTS { + NvU64 correctedVolatile; + NvU64 correctedAggregate; + NvU64 uncorrectedVolatile; + NvU64 uncorrectedAggregate; +} RUSD_MEM_ERROR_COUNTS; + +#define RUSD_MEMORY_ERROR_TYPE_TOTAL 0 +#define RUSD_MEMORY_ERROR_TYPE_DRAM 1 +#define RUSD_MEMORY_ERROR_TYPE_SRAM 2 +#define RUSD_MEMORY_ERROR_TYPE_COUNT 3 + +typedef struct RUSD_ECC_COUNTS { + NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS volatileCounts; + NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS clientExposedCounts; +} RUSD_ECC_INFO; + +typedef struct RUSD_MEM_ECC { + volatile NvU64 lastModifiedTimestamp; + RUSD_MEM_ERROR_COUNTS count[RUSD_MEMORY_ERROR_TYPE_COUNT]; + // TODO: Due to incapability of getting voteup for X driver update with + // existing RM APIs, need to resolve bug 5138911 before fully updating + // RUSD_MEM_ECC and removing deprecated RUSD_MEM_ERROR_COUNTS. + RUSD_ECC_INFO info; +} RUSD_MEM_ECC; + +typedef struct RUSD_POWER_LIMIT_INFO { + NvU32 requestedmW; + NvU32 enforcedmW; +} RUSD_POWER_LIMIT_INFO; + +typedef struct RUSD_POWER_LIMITS { + volatile NvU64 lastModifiedTimestamp; + RUSD_POWER_LIMIT_INFO info; +} RUSD_POWER_LIMITS; + +typedef enum RUSD_TEMPERATURE_SENSOR { + RUSD_TEMPERATURE_SENSOR_GPU, + RUSD_TEMPERATURE_SENSOR_MEMORY, + RUSD_TEMPERATURE_SENSOR_BOARD, + RUSD_TEMPERATURE_SENSOR_POWER_SUPPLY, + + // Should always be last entry + RUSD_TEMPERATURE_SENSOR_MAX +} RUSD_TEMPERATURE_SENSOR; + +typedef enum RUSD_TEMPERATURE_TYPE { + RUSD_TEMPERATURE_TYPE_GPU, + RUSD_TEMPERATURE_TYPE_MEMORY, + RUSD_TEMPERATURE_TYPE_BOARD, + RUSD_TEMPERATURE_TYPE_POWER_SUPPLY, + RUSD_TEMPERATURE_TYPE_HBM, + RUSD_TEMPERATURE_TYPE_MAX +} RUSD_TEMPERATURE_TYPE; + +typedef struct RUSD_TEMPERATURE { + volatile NvU64 lastModifiedTimestamp; + NvTemp temperature; +} RUSD_TEMPERATURE; + +typedef struct RUSD_MEM_ROW_REMAP_INFO { + // Provided from NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM + NvU32 histogramMax; // No remapped row is used. + NvU32 histogramHigh; // One remapped row is used. + NvU32 histogramPartial; // More than one remapped rows are used. + NvU32 histogramLow; // One remapped row is available. + NvU32 histogramNone; // All remapped rows are used. + + NvU32 correctableRows; + NvU32 uncorrectableRows; + NvU32 correctableRowsInactive; + NvU32 uncorrectableRowsInactive; + NvBool isPending; + NvBool hasFailureOccurred; +} RUSD_MEM_ROW_REMAP_INFO; + +typedef struct RUSD_MEM_ROW_REMAP { + volatile NvU64 lastModifiedTimestamp; + RUSD_MEM_ROW_REMAP_INFO info; +} RUSD_MEM_ROW_REMAP; + +typedef struct RUSD_AVG_POWER_INFO { + NvU32 averageGpuPower; // mW + NvU32 averageModulePower; // mW + NvU32 averageMemoryPower; // mW +} RUSD_AVG_POWER_INFO; + +typedef struct RUSD_AVG_POWER_USAGE { + volatile NvU64 lastModifiedTimestamp; + RUSD_AVG_POWER_INFO info; +} RUSD_AVG_POWER_USAGE; + +typedef struct RUSD_INST_POWER_INFO { + NvU32 instGpuPower; // mW + NvU32 instModulePower; // mW + NvU32 instCpuPower; // mW +} RUSD_INST_POWER_INFO; + +typedef struct RUSD_INST_POWER_USAGE { + volatile NvU64 lastModifiedTimestamp; + RUSD_INST_POWER_INFO info; +} RUSD_INST_POWER_USAGE; + +typedef struct RUSD_POWER_POLICY_STATUS_INFO { + NvU32 tgpmW; // Total GPU power in mW +} RUSD_POWER_POLICY_STATUS_INFO; + +typedef struct RUSD_POWER_POLICY_STATUS { + volatile NvU64 lastModifiedTimestamp; + RUSD_POWER_POLICY_STATUS_INFO info; +} RUSD_POWER_POLICY_STATUS; + +#define RUSD_FAN_COOLER_MAX_COOLERS 16U + +typedef struct RUSD_FAN_COOLER_INFO { + NvU32 rpmCurr[RUSD_FAN_COOLER_MAX_COOLERS]; +} RUSD_FAN_COOLER_INFO; + +typedef struct RUSD_FAN_COOLER_STATUS { + volatile NvU64 lastModifiedTimestamp; + RUSD_FAN_COOLER_INFO info; +} RUSD_FAN_COOLER_STATUS; + +typedef struct RUSD_SHADOW_ERR_CONT { + volatile NvU64 lastModifiedTimestamp; + // + // Non-polled data, not tied to any specific RM API + // Shadowed ERR_CONT register value + // + NvU32 shadowErrContVal; +} RUSD_SHADOW_ERR_CONT; + +// Each RUSD_BUS_DATA_* define corresponds to the equivalent NV2080_CTRL_BUS_INFO_INDEX_* +#define RUSD_BUS_DATA_PCIE_GEN_INFO 0 +#define RUSD_BUS_DATA_PCIE_GPU_LINK_LINECODE_ERRORS 1 +#define RUSD_BUS_DATA_PCIE_GPU_LINK_CRC_ERRORS 2 +#define RUSD_BUS_DATA_PCIE_GPU_LINK_NAKS_RECEIVED 3 +#define RUSD_BUS_DATA_PCIE_GPU_LINK_FAILED_L0S_EXITS 4 +#define RUSD_BUS_DATA_PCIE_GPU_LINK_CORRECTABLE_ERRORS 5 +#define RUSD_BUS_DATA_PCIE_GPU_LINK_NONFATAL_ERRORS 6 +#define RUSD_BUS_DATA_PCIE_GPU_LINK_FATAL_ERRORS 7 +#define RUSD_BUS_DATA_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS 8 +#define RUSD_BUS_DATA_COUNT 9 + +typedef struct RUSD_PCIE_DATA_INFO { + // Provided from NV2080_CTRL_CMD_BUS_GET_INFO_V2 + NvU32 data[RUSD_BUS_DATA_COUNT]; +} RUSD_PCIE_DATA_INFO; + +typedef struct RUSD_PCIE_DATA { + volatile NvU64 lastModifiedTimestamp; + RUSD_PCIE_DATA_INFO info; +} RUSD_PCIE_DATA; + +typedef struct RUSD_GR_INFO +{ + volatile NvU64 lastModifiedTimestamp; + NvBool bCtxswLoggingEnabled; +} RUSD_GR_INFO; + +#define RUSD_PROC_UTIL_SAMPLE_COUNT 5 + +// +// RUSD_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE is NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE +// without subProcessName and pOsPidInfo +// +typedef struct { + /*! + * Percentage during the sample that the engine remains busy. This + * is in units of pct*100. + */ + NvU32 util; + /*! + * Scaling factor to convert utilization from full GPU to per vGPU. + */ + NvU32 vgpuScale; + /*! + * Process ID of the process that was active on the engine when the + * sample was taken. If no process is active then NV2080_GPUMON_PID_INVALID + * will be returned. + */ + NvU32 procId; + /*! + * Process ID of the process in the vGPU VM that was active on the engine when + * the sample was taken. If no process is active then NV2080_GPUMON_PID_INVALID + * will be returned. + */ + NvU32 subProcessID; +} RUSD_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE; + +typedef struct { + NvU64 timeStamp; // Original is NV2080_CTRL_GPUMON_SAMPLE + /*! + * FB bandwidth utilization sample. + */ + RUSD_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE fb; + /*! + * GR utilization sample. + */ + RUSD_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE gr; + /*! + * NV ENCODER utilization sample. + */ + RUSD_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvenc; + /*! + * NV DECODER utilization sample. + */ + RUSD_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvdec; + /*! + * NV JPEG utilization sample. + */ + RUSD_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvjpg; + /*! + * NV OFA utilization sample. + */ + RUSD_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvofa; +} RUSD_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE; + +typedef struct { + RUSD_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE samples[RUSD_PROC_UTIL_SAMPLE_COUNT]; +} RUSD_PROC_UTIL_INFO; + +typedef struct { + volatile NvU64 lastModifiedTimestamp; + RUSD_PROC_UTIL_INFO info; +} RUSD_PROC_UTIL; + +typedef struct NV00DE_SHARED_DATA { + NV_DECLARE_ALIGNED(RUSD_BAR1_MEMORY_INFO bar1MemoryInfo, 8); + + NV_DECLARE_ALIGNED(RUSD_PMA_MEMORY_INFO pmaMemoryInfo, 8); + + NV_DECLARE_ALIGNED(RUSD_SHADOW_ERR_CONT shadowErrCont, 8); + + NV_DECLARE_ALIGNED(RUSD_GR_INFO grInfo, 8); + + // gpuUpdateUserSharedData is sensitive to these two sections being contiguous + + // + // Polled data section + // All data structs are a volatile NvU64 timestamp followed by data contents. + // Access by reading timestamp, then copying the struct contents, then reading the timestamp again. + // If time0 matches time1, data has not changed during the read, and contents are valid. + // If timestamp is RUSD_TIMESTAMP_WRITE_IN_PROGRESS, data was edited during the read, retry. + // If timestamp is RUSD_TIMESTAMP_INVALID, data is not available or not supported on this platform. + // + + // POLL_CLOCK + NV_DECLARE_ALIGNED(RUSD_CLK_PUBLIC_DOMAIN_INFOS clkPublicDomainInfos, 8); + + // POLL_PERF + NV_DECLARE_ALIGNED(RUSD_CLK_THROTTLE_INFO clkThrottleInfo, 8); + + // POLL_PERF + NV_DECLARE_ALIGNED(RUSD_PERF_DEVICE_UTILIZATION perfDevUtil, 8); + + // POLL_MEMORY + NV_DECLARE_ALIGNED(RUSD_MEM_ECC memEcc, 8); + + // POLL_PERF + NV_DECLARE_ALIGNED(RUSD_PERF_CURRENT_PSTATE perfCurrentPstate, 8); + + // POLL_POWER + // Module Limit is not supported on Ampere/Hopper + NV_DECLARE_ALIGNED(RUSD_POWER_LIMITS powerLimitGpu, 8); + + // POLL_THERMAL + NV_DECLARE_ALIGNED(RUSD_TEMPERATURE temperatures[RUSD_TEMPERATURE_TYPE_MAX], 8); + + // POLL_MEMORY + NV_DECLARE_ALIGNED(RUSD_MEM_ROW_REMAP memRowRemap, 8); + + // POLL_POWER + NV_DECLARE_ALIGNED(RUSD_AVG_POWER_USAGE avgPowerUsage, 8); + + // POLL_POWER + NV_DECLARE_ALIGNED(RUSD_INST_POWER_USAGE instPowerUsage, 8); + + // POLL_POWER + NV_DECLARE_ALIGNED(RUSD_POWER_POLICY_STATUS powerPolicyStatus, 8); + + // POLL_PCI + NV_DECLARE_ALIGNED(RUSD_PCIE_DATA pciBusData, 8); + + // POLL_FAN + NV_DECLARE_ALIGNED(RUSD_FAN_COOLER_STATUS fanCoolerStatus, 8); + + // POLL_PROC_UTIL + NV_DECLARE_ALIGNED(RUSD_PROC_UTIL procUtil, 8); + +} NV00DE_SHARED_DATA; + +// +// Polling mask bits, pass into ALLOC_PARAMETERS or NV00DE_CTRL_REQEUSET_DATA_POLL +// to request above polled data to be provided +// +#define NV00DE_RUSD_POLL_CLOCK 0x1 +#define NV00DE_RUSD_POLL_PERF 0x2 +#define NV00DE_RUSD_POLL_MEMORY 0x4 +#define NV00DE_RUSD_POLL_POWER 0x8 +#define NV00DE_RUSD_POLL_THERMAL 0x10 +#define NV00DE_RUSD_POLL_PCI 0x20 +#define NV00DE_RUSD_POLL_FAN 0x40 +#define NV00DE_RUSD_POLL_PROC_UTIL 0x80 + +typedef struct NV00DE_ALLOC_PARAMETERS { + NvU64 polledDataMask; // Bitmask of data to request polling at alloc time, 0 if not needed +} NV00DE_ALLOC_PARAMETERS; + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl00de_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl00e0.h b/userspace/sdks/nv570/inc/class/cl00e0.h new file mode 100644 index 0000000..8fac1e3 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl00e0.h @@ -0,0 +1,111 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00e0.finn +// + +#include "cl0080.h" + +/* + * Class definition for exporting memory handles to a different RM client on the + * same or another node (OS). + * + * No memory is allocated or mapped using this class. + * Parented by hClient. + * NvRmDupObject() is not supported. Use NV_MEM_EXPORT_FLAGS_DUP_BY_UUID instead. + */ + +#define NV_MEMORY_EXPORT (0xe0U) /* finn: Evaluated from "NV00E0_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV_MEM_EXPORT_UUID_LEN 16 +#define NV_MEM_EXPORT_PACKET_LEN 32 +#define NV_MEM_EXPORT_METADATA_LEN 64 + +typedef struct NV_EXPORT_MEM_PACKET { + NvU8 uuid[NV_MEM_EXPORT_UUID_LEN]; + NvU8 opaque[16]; +} NV_EXPORT_MEM_PACKET; + +#define NV_MEM_EXPORT_FLAGS_DEFAULT 0x00000000 +#define NV_MEM_EXPORT_FLAGS_DUP_BY_UUID 0x00000001 + +/* + * imexChannel [IN] + * Used to associated export object with an IMEX channel. + * When duping, + * - If the caller is not the privileged IMEX daemon, validate the caller + * is subscribed to the channel. + * - Validate that the imexChannel matches with that of the export object being + * duped. + * + * packet [IN/OUT] + * Bag of bits which uniquely identifies this object universally. + * - When a new object is allocated, "packet" is returned as output. + * - If NV_MEM_EXPORT_FLAGS_DUP_BY_UUID is provided, "packet" is used as + * input to duplicate the existing object. + * + * numMaxHandles [IN/OUT] + * Max number of memory handles to be attached to the export object. + * - Input when a new object is allocated. + * - Output When duplicating. + * + * flags [IN/OUT] + * One of NV_MEM_EXPORT_FLAGS_* + * - Input when a new object is allocated or duplicated. + * - Output when duplicating. The flags at the time of allocation are + * returned. + * + * metadata [IN/OUT] + * Private data about the export object (opaque to kernel mode) + * - Input when a new object is allocated. + * - Output When duplicating. + * + * deviceInstanceMask [OUT] + * Attached device instance mask + * + * giIdMasks [OUT] + * Attached GPU instance ID mask (MIG is currently not supported) + * Must be indexed using deviceInstanceMask. + * + * numCurHandles [OUT] + * Number of memory handles currently attached to the export object. + */ + +#define NV00E0_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00e0U) + +typedef struct NV00E0_ALLOCATION_PARAMETERS { + NvU32 imexChannel; + NV_EXPORT_MEM_PACKET packet; + NvU16 numMaxHandles; + NvU32 flags; + NvU8 metadata[NV_MEM_EXPORT_METADATA_LEN]; + NvU32 deviceInstanceMask; + NvU32 giIdMasks[NV_MAX_DEVICES]; + NvU16 numCurHandles; +} NV00E0_ALLOCATION_PARAMETERS; diff --git a/userspace/sdks/nv570/inc/class/cl00f1.h b/userspace/sdks/nv570/inc/class/cl00f1.h new file mode 100644 index 0000000..c2b35ae --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl00f1.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00f1.finn +// + +#define NV_IMEX_SESSION (0xf1U) /* finn: Evaluated from "NV00F1_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV00F1_ALLOC_FLAGS_DEFAULT 0 + +// +// Disables channel recovery on IMEX shutdown. This can lead to security +// issues. The flag is intended to be used for testing purpose only. +// +#define NV00F1_ALLOC_DISABLE_CHANNEL_RECOVERY NVBIT(0) + +#define NV00F1_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00f1U) + +typedef struct NV00F1_ALLOCATION_PARAMETERS { + // + // capDescriptor is a file descriptor for UNIX RM clients, but a void + // pointer for windows RM clients. + // + // capDescriptor is transparent to RM clients i.e. RM's user-mode shim + // populates this field on behalf of clients. + // + NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8); + + // See NV00F1_ALLOC_FLAGS_xxx + NvU32 flags; + + // OS event handle created with NvRmAllocOsEvent(). + NV_DECLARE_ALIGNED(NvP64 pOsEvent, 8); + + // Node ID which represent this OS/RM instance + NvU16 nodeId; +} NV00F1_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/cl00f2.h b/userspace/sdks/nv570/inc/class/cl00f2.h new file mode 100644 index 0000000..13b0624 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl00f2.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _cl00f2_h_ +#define _cl00f2_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define IO_VASPACE_A (0x000000f2) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl00f2_h + diff --git a/userspace/sdks/nv570/inc/class/cl00f8.h b/userspace/sdks/nv570/inc/class/cl00f8.h new file mode 100644 index 0000000..be0b7dc --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl00f8.h @@ -0,0 +1,133 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00f8.finn +// + + + +#include "nvcfg_sdk.h" + + +/* + * Class definition for allocating a contiguous or discontiguous FLA. + */ + +#define NV_MEMORY_FABRIC (0xf8U) /* finn: Evaluated from "NV00F8_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* + * alignment [IN] + * Alignment for the allocation. + * Should be at least the requested page size. + * + * allocSize [IN] + * Size of the FLA VA. + * + * pageSize [IN] + * Requested page size. Can be any of the NV_MEMORY_FABRIC_PAGE_SIZE_* + * + * allocFlags [IN] + * Can be any of the NV00F8_ALLOC_FLAGS_* + * DEFAULT (sticky) + * The FLA -> PA mappings will be stuck to the object, i.e, once the mapping is created + * there is no way to unmap it explicitly. + * The FLA object must be destroyed to release the mappings. + * The FLA object can't be duped or exported until it has a mapping associated with it. + * Partial FLA->PA mappings will NOT be allowed. + * FLEXIBLE_FLA + * The FLA -> PA mappings can be modified anytime irrespective of the FLA object is duped + * or exported. + * Partial FLA mappings are allowed. + * FORCE_NONCONTIGUOUS + * The allocator may pick contiguous memory whenever possible. This flag forces the + * allocator to always allocate noncontiguous memory. This flag is mainly used for + * testing purpose. So, use with caution. + * FORCE_CONTIGUOUS + * This flag forces the allocator to always allocate contiguous memory. + * READ_ONLY + * The FLA -> PA mappings will be created read-only. This option is only available on + * debug/develop builds due to security concerns. The security concerns are due to the + * fact that FLA access errors (a.k.a PRIV errors) are not aways context attributable. + * FORCE_UC_LOOPBACK + * Sticky FLA allocations fallback to GVA->GPA/SPA mappings as an optimization when + * mapped on the FLA owner GPU. However, if HW/FW supports loopback, this flag can be + * used to force create GVA->FLA loopback mappings. This flag is a NOP for flexible FLA + * allocations. + * + * + * map.offset [IN] + * Offset into the physical memory descriptor. + * Must be physical memory page size aligned. + * + * map.hVidMem [IN] + * - Handle to the physical memory. + * - Must be passed so that the FLA -> GPA mapping can happen during object creation. + * - For sticky allocations, physical memory being mapped should be large enough + * (accounting map.offset) to cover the whole fabric object allocation size. + * - For flexible allocations, physical memory handle should be zero. + * - Phys memory with 2MB and 512MB pages is supported. + * - hVidMem should belong the same device and client which is allocating FLA. + * + * map.flags [IN] + * Reserved for future use. + * Clients should pass 0 as of now. + */ + +#define NV_MEMORY_FABRIC_PAGE_SIZE_2M 0x200000 +#define NV_MEMORY_FABRIC_PAGE_SIZE_512M 0x20000000 +#define NV_MEMORY_FABRIC_PAGE_SIZE_256G 0x4000000000 + +#define NV00F8_ALLOC_FLAGS_DEFAULT 0 +#define NV00F8_ALLOC_FLAGS_FLEXIBLE_FLA NVBIT(0) +#define NV00F8_ALLOC_FLAGS_FORCE_NONCONTIGUOUS NVBIT(1) +#define NV00F8_ALLOC_FLAGS_FORCE_CONTIGUOUS NVBIT(2) +#define NV00F8_ALLOC_FLAGS_READ_ONLY NVBIT(3) +#define NV00F8_ALLOC_FLAGS_FORCE_UC_LOOPBACK NVBIT(4) + + + +#define NV00F8_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00f8U) + +typedef struct NV00F8_ALLOCATION_PARAMETERS { + + NV_DECLARE_ALIGNED(NvU64 alignment, 8); + NV_DECLARE_ALIGNED(NvU64 allocSize, 8); + + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); + NvU32 allocFlags; + + struct { + NV_DECLARE_ALIGNED(NvU64 offset, 8); + + NvHandle hVidMem; + NvU32 flags; + } map; + +} NV00F8_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/cl00f9.h b/userspace/sdks/nv570/inc/class/cl00f9.h new file mode 100644 index 0000000..8f37e0a --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl00f9.h @@ -0,0 +1,82 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00f9.finn +// + +#include "cl00e0.h" + +/* + * Class definition for importing memory handles from a different RM client on + * the same or another node (OS). + */ + +#define NV_MEMORY_FABRIC_IMPORT_V2 (0xf9U) /* finn: Evaluated from "NV00F9_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* + * imexChannel [IN] + * IMEX channel to be used for import. (Currently ignored, driver picks the + * appropriate channel) + * + * packet [DEPRECATED, use expPacket instead] + * Fabric packet which uniquely identifies this object universally. + * + * expPacket [IN] + * Export object (see cl00e0.h) identifier from which memory will be imported. + * + * index [IN] + * Index into the FLA handle array associated with the export UUID. + * + * flags [IN] + * For future use. + * Set to zero for default behavior. + * + * pOsEvent [IN] + * Optional OS event handle created with NvRmAllocOsEvent(). + * + * id [IN] + * A 48-bit ID for this import call. The caller has freedom to uniqueness + * of the ID. RM would track the object uniquely using + * . + */ + +#define NV00F9_IMPORT_ID_MAX (NVBIT64(48) - 1) +#define NV00F9_IMPORT_ID_SHIFT 16 + +#define NV00F9_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00f9U) + +typedef struct NV00F9_ALLOCATION_PARAMETERS { + NvU32 imexChannel; + NV_EXPORT_MEM_PACKET expPacket; + NvU16 index; + NvU32 flags; + NV_DECLARE_ALIGNED(NvP64 pOsEvent, 8); + NV_DECLARE_ALIGNED(NvU64 id, 8); +} NV00F9_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/cl00fb.h b/userspace/sdks/nv570/inc/class/cl00fb.h new file mode 100644 index 0000000..181d3e3 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl00fb.h @@ -0,0 +1,71 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00fb.finn +// + +#include "cl00e0.h" + +/* + * Class definition for referencing the imported fabric memory, + * NV_MEMORY_FABRIC_IMPORT_V2, using the export object UUID. + * + * A privileged fabric manager only class, parented by client. + * + * No fabric events will be generated during creation or destruction of + * this class. + */ + +#define NV_MEMORY_FABRIC_IMPORTED_REF (0xfbU) /* finn: Evaluated from "NV00FB_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* + * exportUuid [IN] + * Universally unique identifier of the export object. This is extracted + * from a fabric packet. + * + * index [IN] + * Index of the export object to which the memory object is attached. + * + * flags [IN] + * Currently unused. Must be zero for now. + * + * id [IN] + * Import ID. An import request is uniquely identified using, + * . + */ + +#define NV00FB_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00fbU) + +typedef struct NV00FB_ALLOCATION_PARAMETERS { + NvU8 exportUuid[NV_MEM_EXPORT_UUID_LEN]; + NvU16 index; + NvU32 flags; + NV_DECLARE_ALIGNED(NvU64 id, 8); +} NV00FB_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/cl00fc.h b/userspace/sdks/nv570/inc/class/cl00fc.h new file mode 100644 index 0000000..aa50ead --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl00fc.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _cl00fc_h_ +#define _cl00fc_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define FABRIC_VASPACE_A (0x000000fc) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl00fc_h + diff --git a/userspace/sdks/nv570/inc/class/cl00fd.h b/userspace/sdks/nv570/inc/class/cl00fd.h new file mode 100644 index 0000000..bd598c7 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl00fd.h @@ -0,0 +1,99 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * Class definition for allocating a contiguous or discontiguous Multicast FLA. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00fd.finn +// + +#include "cl00e0.h" + + + +#define NV_MEMORY_MULTICAST_FABRIC (0xfdU) /* finn: Evaluated from "NV00FD_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* + * expPacket [IN] + * Export object (see cl00e0.h) identifier from which memory will be imported. + * + * index [IN] + * Index of the export object to which the memory object is attached. + */ + + +/* + * alignment [IN] + * Alignment for the allocation. + * Should be at least the requested page size. + * + * allocSize [IN] + * Size of the Multicast FLA VA. + * + * pageSize [IN] + * Requested page size. Can be any of the NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_* + * + * allocFlags [IN] + * Should be one of NV_MEMORY_MULTICAST_FABRIC_ALLOC_FLAGS_* + * + * numGpus [IN] + * Number of unique GPUs to be attached. + * + * pOsEvent [IN] + * Optional OS event handle created with NvRmAllocOsEvent(). + */ + +#define NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_512M 0x20000000 +#define NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_256G 0x1000000000000 + +/* + * This flag must be passed if the object is created using export packet. Note + * when this flag is provided, the input params: alignment, allocSize, + * numGpus, pageSize won't be honored. + */ +#define NV_MEMORY_MULTICAST_FABRIC_ALLOC_FLAGS_USE_EXPORT_PACKET 0x00000001 + + + +#define NV00FD_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00fdU) + +typedef struct NV00FD_ALLOCATION_PARAMETERS { + NV_EXPORT_MEM_PACKET expPacket; + NvU16 index; + + + NV_DECLARE_ALIGNED(NvU64 alignment, 8); + NV_DECLARE_ALIGNED(NvU64 allocSize, 8); + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); + NvU32 allocFlags; + NvU32 numGpus; + NV_DECLARE_ALIGNED(NvP64 pOsEvent, 8); +} NV00FD_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/cl00fe.h b/userspace/sdks/nv570/inc/class/cl00fe.h new file mode 100644 index 0000000..c76d509 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl00fe.h @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00fe.finn +// + +#define NV_MEMORY_MAPPER (0xfeU) /* finn: Evaluated from "NV_MEMORY_MAPPER_ALLOCATION_PARAMS_MESSAGE_ID" */ + +/* + * NV_MEMORY_MAPPER_ALLOCATION_PARAMS + * + * Allocation params for NV_MEMORY_MAPPER. + * This class provides paging operations channel interface to userspace clients. + */ +#define NV_MEMORY_MAPPER_ALLOCATION_PARAMS_MESSAGE_ID (0x00FEU) + +typedef struct NV_MEMORY_MAPPER_ALLOCATION_PARAMS { + NvHandle hSemaphoreSurface; + NvU32 maxQueueSize; + NvHandle hNotificationMemory; + NV_DECLARE_ALIGNED(NvU64 notificationOffset, 8); +} NV_MEMORY_MAPPER_ALLOCATION_PARAMS; + +typedef struct NV_MEMORY_MAPPER_NOTIFICATION { + NvU32 status; // NV_STATUS error code +} NV_MEMORY_MAPPER_NOTIFICATION; + diff --git a/userspace/sdks/nv570/inc/class/cl0100.h b/userspace/sdks/nv570/inc/class/cl0100.h new file mode 100644 index 0000000..a23f4b9 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl0100.h @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0100.finn +// + + + +/* + * The lock stress object (LOCK_STRESS_OBJECT) is a test-only object that exports + * multiple RM controls which exercise acquiring different combinations of RM locks in + * order to stress and properly test RM locking specifically. These API's only exercise + * legal combinations of RM locks that are in use elsewhere in RM but they are intended + * to be exhaustive in covering all possible combinations of RM locks. The API's + * themselves, don't do much outside of incrementing/decrementing global integers that + * can be validated later on within a test executable to ensure that all accesses to + * these global integers were synchronous. + * + * The lock stress object is not allocatable without the "EnableRmTestOnlyCode" registry + * key being turned on, which is off by default. The creation/destruction of the object + * has no functional impact to RM. The constructor simply allocate test only resources + * and checks for the regisry enablement. + */ + +#define LOCK_STRESS_OBJECT 0x0100U + diff --git a/userspace/sdks/nv570/inc/class/cl0101.h b/userspace/sdks/nv570/inc/class/cl0101.h new file mode 100644 index 0000000..8aba267 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl0101.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0101.finn +// + + + +/* + * LOCK_TEST_RELAXED_DUP_OBJECT + * An object used for testing the relaxed GPU lock for RMDUP operation. + * Can be allocated only if PDB_PROP_SYS_ENABLE_RM_TEST_ONLY_CODE is set. + */ +#define LOCK_TEST_RELAXED_DUP_OBJECT 0x0101U + diff --git a/userspace/sdks/nv570/inc/class/cl2080.h b/userspace/sdks/nv570/inc/class/cl2080.h new file mode 100644 index 0000000..a85a662 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl2080.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2002-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl2080.finn +// + +#include "nvlimits.h" +#include "cl2080_notification.h" + +#define NV20_SUBDEVICE_0 (0x2080U) /* finn: Evaluated from "NV2080_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* NvAlloc parameteters */ +#define NV2080_MAX_SUBDEVICES NV_MAX_SUBDEVICES + +#define NV2080_ALLOC_PARAMETERS_MESSAGE_ID (0x2080U) + +typedef struct NV2080_ALLOC_PARAMETERS { + NvU32 subDeviceId; +} NV2080_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/cl2080_notification.h b/userspace/sdks/nv570/inc/class/cl2080_notification.h new file mode 100644 index 0000000..fe39a82 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl2080_notification.h @@ -0,0 +1,612 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl2080_notification_h_ +#define _cl2080_notification_h_ + +#include "nvcfg_sdk.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvcfg_sdk.h" + +/* event values */ +#define NV2080_NOTIFIERS_SW (0) +#define NV2080_NOTIFIERS_HOTPLUG (1) +#define NV2080_NOTIFIERS_POWER_CONNECTOR (2) +#define NV2080_NOTIFIERS_THERMAL_SW (3) +#define NV2080_NOTIFIERS_THERMAL_HW (4) +#define NV2080_NOTIFIERS_FULL_SCREEN_CHANGE (5) +#define NV2080_NOTIFIERS_EVENTBUFFER (6) +#define NV2080_NOTIFIERS_DP_IRQ (7) +#define NV2080_NOTIFIERS_GR_DEBUG_INTR (8) +#define NV2080_NOTIFIERS_PMU_EVENT (9) +#define NV2080_NOTIFIERS_PMU_COMMAND (10) +#define NV2080_NOTIFIERS_TIMER (11) +#define NV2080_NOTIFIERS_GRAPHICS (12) +#define NV2080_NOTIFIERS_PPP (13) +#define NV2080_NOTIFIERS_VLD (14) // also known as BSP +#define NV2080_NOTIFIERS_NVDEC0 NV2080_NOTIFIERS_VLD +#define NV2080_NOTIFIERS_NVDEC1 (15) +#define NV2080_NOTIFIERS_NVDEC2 (16) +#define NV2080_NOTIFIERS_NVDEC3 (17) +#define NV2080_NOTIFIERS_NVDEC4 (18) +#define NV2080_NOTIFIERS_NVDEC5 (19) +#define NV2080_NOTIFIERS_NVDEC6 (20) +#define NV2080_NOTIFIERS_NVDEC7 (21) +#define NV2080_NOTIFIERS_PDEC (22) // also known as VP +#define NV2080_NOTIFIERS_CE0 (23) +#define NV2080_NOTIFIERS_CE1 (24) +#define NV2080_NOTIFIERS_CE2 (25) +#define NV2080_NOTIFIERS_CE3 (26) +#define NV2080_NOTIFIERS_CE4 (27) +#define NV2080_NOTIFIERS_CE5 (28) +#define NV2080_NOTIFIERS_CE6 (29) +#define NV2080_NOTIFIERS_CE7 (30) +#define NV2080_NOTIFIERS_CE8 (31) +#define NV2080_NOTIFIERS_CE9 (32) +#define NV2080_NOTIFIERS_PSTATE_CHANGE (33) +#define NV2080_NOTIFIERS_HDCP_STATUS_CHANGE (34) +#define NV2080_NOTIFIERS_FIFO_EVENT_MTHD (35) +#define NV2080_NOTIFIERS_PRIV_RING_HANG (36) +#define NV2080_NOTIFIERS_RC_ERROR (37) +#define NV2080_NOTIFIERS_MSENC (38) +#define NV2080_NOTIFIERS_NVENC0 NV2080_NOTIFIERS_MSENC +#define NV2080_NOTIFIERS_NVENC1 (39) +#define NV2080_NOTIFIERS_NVENC2 (40) +#define NV2080_NOTIFIERS_UNUSED_0 (41) // Unused +#define NV2080_NOTIFIERS_ACPI_NOTIFY (42) +#define NV2080_NOTIFIERS_COOLER_DIAG_ZONE (43) +#define NV2080_NOTIFIERS_THERMAL_DIAG_ZONE (44) +#define NV2080_NOTIFIERS_AUDIO_HDCP_REQUEST (45) +#define NV2080_NOTIFIERS_WORKLOAD_MODULATION_CHANGE (46) +#define NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT (47) +#define NV2080_NOTIFIERS_GPIO_1_RISING_INTERRUPT (48) +#define NV2080_NOTIFIERS_GPIO_2_RISING_INTERRUPT (49) +#define NV2080_NOTIFIERS_GPIO_3_RISING_INTERRUPT (50) +#define NV2080_NOTIFIERS_GPIO_4_RISING_INTERRUPT (51) +#define NV2080_NOTIFIERS_GPIO_5_RISING_INTERRUPT (52) +#define NV2080_NOTIFIERS_GPIO_6_RISING_INTERRUPT (53) +#define NV2080_NOTIFIERS_GPIO_7_RISING_INTERRUPT (54) +#define NV2080_NOTIFIERS_GPIO_8_RISING_INTERRUPT (55) +#define NV2080_NOTIFIERS_GPIO_9_RISING_INTERRUPT (56) +#define NV2080_NOTIFIERS_GPIO_10_RISING_INTERRUPT (57) +#define NV2080_NOTIFIERS_GPIO_11_RISING_INTERRUPT (58) +#define NV2080_NOTIFIERS_GPIO_12_RISING_INTERRUPT (59) +#define NV2080_NOTIFIERS_GPIO_13_RISING_INTERRUPT (60) +#define NV2080_NOTIFIERS_GPIO_14_RISING_INTERRUPT (61) +#define NV2080_NOTIFIERS_GPIO_15_RISING_INTERRUPT (62) +#define NV2080_NOTIFIERS_GPIO_16_RISING_INTERRUPT (63) +#define NV2080_NOTIFIERS_GPIO_17_RISING_INTERRUPT (64) +#define NV2080_NOTIFIERS_GPIO_18_RISING_INTERRUPT (65) +#define NV2080_NOTIFIERS_GPIO_19_RISING_INTERRUPT (66) +#define NV2080_NOTIFIERS_GPIO_20_RISING_INTERRUPT (67) +#define NV2080_NOTIFIERS_GPIO_21_RISING_INTERRUPT (68) +#define NV2080_NOTIFIERS_GPIO_22_RISING_INTERRUPT (69) +#define NV2080_NOTIFIERS_GPIO_23_RISING_INTERRUPT (70) +#define NV2080_NOTIFIERS_GPIO_24_RISING_INTERRUPT (71) +#define NV2080_NOTIFIERS_GPIO_25_RISING_INTERRUPT (72) +#define NV2080_NOTIFIERS_GPIO_26_RISING_INTERRUPT (73) +#define NV2080_NOTIFIERS_GPIO_27_RISING_INTERRUPT (74) +#define NV2080_NOTIFIERS_GPIO_28_RISING_INTERRUPT (75) +#define NV2080_NOTIFIERS_GPIO_29_RISING_INTERRUPT (76) +#define NV2080_NOTIFIERS_GPIO_30_RISING_INTERRUPT (77) +#define NV2080_NOTIFIERS_GPIO_31_RISING_INTERRUPT (78) +#define NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT (79) +#define NV2080_NOTIFIERS_GPIO_1_FALLING_INTERRUPT (80) +#define NV2080_NOTIFIERS_GPIO_2_FALLING_INTERRUPT (81) +#define NV2080_NOTIFIERS_GPIO_3_FALLING_INTERRUPT (82) +#define NV2080_NOTIFIERS_GPIO_4_FALLING_INTERRUPT (83) +#define NV2080_NOTIFIERS_GPIO_5_FALLING_INTERRUPT (84) +#define NV2080_NOTIFIERS_GPIO_6_FALLING_INTERRUPT (85) +#define NV2080_NOTIFIERS_GPIO_7_FALLING_INTERRUPT (86) +#define NV2080_NOTIFIERS_GPIO_8_FALLING_INTERRUPT (87) +#define NV2080_NOTIFIERS_GPIO_9_FALLING_INTERRUPT (88) +#define NV2080_NOTIFIERS_GPIO_10_FALLING_INTERRUPT (89) +#define NV2080_NOTIFIERS_GPIO_11_FALLING_INTERRUPT (90) +#define NV2080_NOTIFIERS_GPIO_12_FALLING_INTERRUPT (91) +#define NV2080_NOTIFIERS_GPIO_13_FALLING_INTERRUPT (92) +#define NV2080_NOTIFIERS_GPIO_14_FALLING_INTERRUPT (93) +#define NV2080_NOTIFIERS_GPIO_15_FALLING_INTERRUPT (94) +#define NV2080_NOTIFIERS_GPIO_16_FALLING_INTERRUPT (95) +#define NV2080_NOTIFIERS_GPIO_17_FALLING_INTERRUPT (96) +#define NV2080_NOTIFIERS_GPIO_18_FALLING_INTERRUPT (97) +#define NV2080_NOTIFIERS_GPIO_19_FALLING_INTERRUPT (98) +#define NV2080_NOTIFIERS_GPIO_20_FALLING_INTERRUPT (99) +#define NV2080_NOTIFIERS_GPIO_21_FALLING_INTERRUPT (100) +#define NV2080_NOTIFIERS_GPIO_22_FALLING_INTERRUPT (101) +#define NV2080_NOTIFIERS_GPIO_23_FALLING_INTERRUPT (102) +#define NV2080_NOTIFIERS_GPIO_24_FALLING_INTERRUPT (103) +#define NV2080_NOTIFIERS_GPIO_25_FALLING_INTERRUPT (104) +#define NV2080_NOTIFIERS_GPIO_26_FALLING_INTERRUPT (105) +#define NV2080_NOTIFIERS_GPIO_27_FALLING_INTERRUPT (106) +#define NV2080_NOTIFIERS_GPIO_28_FALLING_INTERRUPT (107) +#define NV2080_NOTIFIERS_GPIO_29_FALLING_INTERRUPT (108) +#define NV2080_NOTIFIERS_GPIO_30_FALLING_INTERRUPT (109) +#define NV2080_NOTIFIERS_GPIO_31_FALLING_INTERRUPT (110) +#define NV2080_NOTIFIERS_ECC_SBE (111) +#define NV2080_NOTIFIERS_ECC_DBE (112) +#define NV2080_NOTIFIERS_STEREO_EMITTER_DETECTION (113) +#define NV2080_NOTIFIERS_GC5_GPU_READY (114) +#define NV2080_NOTIFIERS_SEC2 (115) +#define NV2080_NOTIFIERS_GC6_REFCOUNT_INC (116) +#define NV2080_NOTIFIERS_GC6_REFCOUNT_DEC (117) +#define NV2080_NOTIFIERS_POWER_EVENT (118) +#define NV2080_NOTIFIERS_CLOCKS_CHANGE (119) +#define NV2080_NOTIFIERS_HOTPLUG_PROCESSING_COMPLETE (120) +#define NV2080_NOTIFIERS_PHYSICAL_PAGE_FAULT (121) +#define NV2080_NOTIFIERS_RESERVED122 (122) +#define NV2080_NOTIFIERS_NVLINK_ERROR_FATAL (123) +#define NV2080_NOTIFIERS_PRIV_REG_ACCESS_FAULT (124) +#define NV2080_NOTIFIERS_NVLINK_ERROR_RECOVERY_REQUIRED (125) +#define NV2080_NOTIFIERS_NVJPG (126) +#define NV2080_NOTIFIERS_NVJPEG0 NV2080_NOTIFIERS_NVJPG +#define NV2080_NOTIFIERS_NVJPEG1 (127) +#define NV2080_NOTIFIERS_NVJPEG2 (128) +#define NV2080_NOTIFIERS_NVJPEG3 (129) +#define NV2080_NOTIFIERS_NVJPEG4 (130) +#define NV2080_NOTIFIERS_NVJPEG5 (131) +#define NV2080_NOTIFIERS_NVJPEG6 (132) +#define NV2080_NOTIFIERS_NVJPEG7 (133) +#define NV2080_NOTIFIERS_RUNLIST_AND_ENG_IDLE (134) +#define NV2080_NOTIFIERS_RUNLIST_ACQUIRE (135) +#define NV2080_NOTIFIERS_RUNLIST_ACQUIRE_AND_ENG_IDLE (136) +#define NV2080_NOTIFIERS_RUNLIST_IDLE (137) +#define NV2080_NOTIFIERS_TSG_PREEMPT_COMPLETE (138) +#define NV2080_NOTIFIERS_RUNLIST_PREEMPT_COMPLETE (139) +#define NV2080_NOTIFIERS_CTXSW_TIMEOUT (140) +#define NV2080_NOTIFIERS_INFOROM_ECC_OBJECT_UPDATED (141) +#define NV2080_NOTIFIERS_NVTELEMETRY_REPORT_EVENT (142) +#define NV2080_NOTIFIERS_DSTATE_XUSB_PPC (143) +#define NV2080_NOTIFIERS_FECS_CTX_SWITCH (144) +#define NV2080_NOTIFIERS_XUSB_PPC_CONNECTED (145) +#define NV2080_NOTIFIERS_GR0 NV2080_NOTIFIERS_GRAPHICS +#define NV2080_NOTIFIERS_GR1 (146) +#define NV2080_NOTIFIERS_GR2 (147) +#define NV2080_NOTIFIERS_GR3 (148) +#define NV2080_NOTIFIERS_GR4 (149) +#define NV2080_NOTIFIERS_GR5 (150) +#define NV2080_NOTIFIERS_GR6 (151) +#define NV2080_NOTIFIERS_GR7 (152) +#define NV2080_NOTIFIERS_OFA (153) +#define NV2080_NOTIFIERS_OFA0 NV2080_NOTIFIERS_OFA +#define NV2080_NOTIFIERS_DSTATE_HDA (154) +#define NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL (155) +#define NV2080_NOTIFIERS_POISON_ERROR_FATAL (156) +#define NV2080_NOTIFIERS_UCODE_RESET (157) +#define NV2080_NOTIFIERS_PLATFORM_POWER_MODE_CHANGE (158) +#define NV2080_NOTIFIERS_SMC_CONFIG_UPDATE (159) +#define NV2080_NOTIFIERS_INFOROM_RRL_OBJECT_UPDATED (160) +#define NV2080_NOTIFIERS_INFOROM_PBL_OBJECT_UPDATED (161) +#define NV2080_NOTIFIERS_LPWR_DIFR_PREFETCH_REQUEST (162) +#define NV2080_NOTIFIERS_SEC_FAULT_ERROR (163) +#define NV2080_NOTIFIERS_UNUSED_1 (164) // Unused +#define NV2080_NOTIFIERS_NVLINK_INFO_LINK_UP (165) +#define NV2080_NOTIFIERS_CE10 (166) +#define NV2080_NOTIFIERS_CE11 (167) +#define NV2080_NOTIFIERS_CE12 (168) +#define NV2080_NOTIFIERS_CE13 (169) +#define NV2080_NOTIFIERS_CE14 (170) +#define NV2080_NOTIFIERS_CE15 (171) +#define NV2080_NOTIFIERS_CE16 (172) +#define NV2080_NOTIFIERS_CE17 (173) +#define NV2080_NOTIFIERS_CE18 (174) +#define NV2080_NOTIFIERS_CE19 (175) +#define NV2080_NOTIFIERS_NVLINK_INFO_LINK_DOWN (176) +#define NV2080_NOTIFIERS_NVPCF_EVENTS (177) +#define NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST (178) +// unused (179) +#define NV2080_NOTIFIERS_OFA1 (180) +#define NV2080_NOTIFIERS_AUX_POWER_EVENT (181) +#define NV2080_NOTIFIERS_AUX_POWER_STATE_CHANGE (182) +#define NV2080_NOTIFIERS_NVENC3 (183) +#define NV2080_NOTIFIERS_GSP_PERF_TRACE (184) +#define NV2080_NOTIFIERS_INBAND_RESPONSE (185) +#define NV2080_NOTIFIERS_RESERVED_186 (186) // Unused +#define NV2080_NOTIFIERS_ECC_SBE_STORM (187) +#define NV2080_NOTIFIERS_DRAM_RETIREMENT_EVENT (188) +#define NV2080_NOTIFIERS_DRAM_RETIREMENT_FAILURE (189) +#define NV2080_NOTIFIERS_NVLINK_UNCONTAINED_ERROR (190) +#define NV2080_NOTIFIERS_GPU_UNAVAILABLE (191) +#define NV2080_NOTIFIERS_GPU_RECOVERY_ACTION (192) +#define NV2080_NOTIFIERS_POWER_SUSPEND (193) +#define NV2080_NOTIFIERS_POWER_RESUME (194) +#define NV2080_NOTIFIERS_CTXSW_UCODE_ERROR (195) +#define NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD (196) +#define NV2080_NOTIFIERS_GPU_RC_RESET (197) +#define NV2080_NOTIFIERS_RESERVED_198 (198) // Unused +#define NV2080_NOTIFIERS_INFOROM_BRL_OBJECT_UPDATED (199) +#define NV2080_NOTIFIERS_MAXCOUNT (200) + +// Indexed GR notifier reference +#define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x - 1))) +#define NV2080_NOTIFIERS_GR_IDX(x) ((x) - NV2080_NOTIFIERS_GR0) +#define NV2080_NOTIFIER_TYPE_IS_GR(x) (((x) == NV2080_NOTIFIERS_GR0) || (((x) >= NV2080_NOTIFIERS_GR1) && ((x) <= NV2080_NOTIFIERS_GR7))) + +// Indexed CE notifier reference +#define NV2080_NOTIFIERS_CE(x) (((x) < 10) ? (NV2080_NOTIFIERS_CE0 + (x)) : (NV2080_NOTIFIERS_CE10 + (x) - 10)) +#define NV2080_NOTIFIERS_CE_IDX(x) (((x) <= NV2080_NOTIFIERS_CE9) ? ((x) - NV2080_NOTIFIERS_CE0) : ((x) - NV2080_NOTIFIERS_CE10 + 10)) +#define NV2080_NOTIFIER_TYPE_IS_CE(x) ((((x) >= NV2080_NOTIFIERS_CE0) && ((x) <= NV2080_NOTIFIERS_CE9)) || \ + (((x) >= NV2080_NOTIFIERS_CE10) && ((x) <= NV2080_NOTIFIERS_CE19))) + +// Indexed MSENC notifier reference +#define NV2080_NOTIFIERS_NVENC(x) (((x) < 3) ? (NV2080_NOTIFIERS_NVENC0 + (x)) : (NV2080_NOTIFIERS_NVENC3 + (x) - 3)) +#define NV2080_NOTIFIERS_NVENC_IDX(x) (((x) <= NV2080_NOTIFIERS_NVENC2) ? ((x) - NV2080_NOTIFIERS_NVENC0) : ((x) - NV2080_NOTIFIERS_NVENC3 + 3)) +#define NV2080_NOTIFIER_TYPE_IS_NVENC(x) ((((x) >= NV2080_NOTIFIERS_NVENC0) && ((x) <= NV2080_NOTIFIERS_NVENC2)) || \ + (((x) == NV2080_NOTIFIERS_NVENC3))) +// Indexed NVDEC notifier reference +#define NV2080_NOTIFIERS_NVDEC(x) (NV2080_NOTIFIERS_NVDEC0 + (x)) +#define NV2080_NOTIFIERS_NVDEC_IDX(x) ((x) - NV2080_NOTIFIERS_NVDEC0) +#define NV2080_NOTIFIER_TYPE_IS_NVDEC(x) (((x) >= NV2080_NOTIFIERS_NVDEC0) && ((x) <= NV2080_NOTIFIERS_NVDEC7)) +// Indexed NVJPEG notifier reference +#define NV2080_NOTIFIERS_NVJPEG(x) (NV2080_NOTIFIERS_NVJPEG0 + (x)) +#define NV2080_NOTIFIERS_NVJPEG_IDX(x) ((x) - NV2080_NOTIFIERS_NVJPEG0) +#define NV2080_NOTIFIER_TYPE_IS_NVJPEG(x) (((x) >= NV2080_NOTIFIERS_NVJPEG0) && ((x) <= NV2080_NOTIFIERS_NVJPEG7)) + +// Indexed OFA notifier reference +#define NV2080_NOTIFIERS_OFAn(x) ((x == 0) ? (NV2080_NOTIFIERS_OFA0) : (NV2080_NOTIFIERS_OFA1)) +#define NV2080_NOTIFIERS_OFA_IDX(x) ((x == NV2080_NOTIFIERS_OFA0) ? ((x) - NV2080_NOTIFIERS_OFA0) : ((x) - NV2080_NOTIFIERS_OFA1 + 1)) +#define NV2080_NOTIFIER_TYPE_IS_OFA(x) (((x) == NV2080_NOTIFIERS_OFA0) || ((x) == NV2080_NOTIFIERS_OFA1)) + +#define NV2080_NOTIFIERS_GPIO_RISING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT + (pin)) +#define NV2080_NOTIFIERS_GPIO_FALLING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT + (pin)) + +#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000) +#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000) +#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000) +#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) + +/* exported engine defines */ +#define NV2080_ENGINE_TYPE_NULL (0x00000000) +#define NV2080_ENGINE_TYPE_GRAPHICS (0x00000001) +#define NV2080_ENGINE_TYPE_GR0 NV2080_ENGINE_TYPE_GRAPHICS +#define NV2080_ENGINE_TYPE_GR1 (0x00000002) +#define NV2080_ENGINE_TYPE_GR2 (0x00000003) +#define NV2080_ENGINE_TYPE_GR3 (0x00000004) +#define NV2080_ENGINE_TYPE_GR4 (0x00000005) +#define NV2080_ENGINE_TYPE_GR5 (0x00000006) +#define NV2080_ENGINE_TYPE_GR6 (0x00000007) +#define NV2080_ENGINE_TYPE_GR7 (0x00000008) +#define NV2080_ENGINE_TYPE_COPY0 (0x00000009) +#define NV2080_ENGINE_TYPE_COPY1 (0x0000000a) +#define NV2080_ENGINE_TYPE_COPY2 (0x0000000b) +#define NV2080_ENGINE_TYPE_COPY3 (0x0000000c) +#define NV2080_ENGINE_TYPE_COPY4 (0x0000000d) +#define NV2080_ENGINE_TYPE_COPY5 (0x0000000e) +#define NV2080_ENGINE_TYPE_COPY6 (0x0000000f) +#define NV2080_ENGINE_TYPE_COPY7 (0x00000010) +#define NV2080_ENGINE_TYPE_COPY8 (0x00000011) +#define NV2080_ENGINE_TYPE_COPY9 (0x00000012) +#define NV2080_ENGINE_TYPE_BSP (0x00000013) +#define NV2080_ENGINE_TYPE_NVDEC0 NV2080_ENGINE_TYPE_BSP +#define NV2080_ENGINE_TYPE_NVDEC1 (0x00000014) +#define NV2080_ENGINE_TYPE_NVDEC2 (0x00000015) +#define NV2080_ENGINE_TYPE_NVDEC3 (0x00000016) +#define NV2080_ENGINE_TYPE_NVDEC4 (0x00000017) +#define NV2080_ENGINE_TYPE_NVDEC5 (0x00000018) +#define NV2080_ENGINE_TYPE_NVDEC6 (0x00000019) +#define NV2080_ENGINE_TYPE_NVDEC7 (0x0000001a) +#define NV2080_ENGINE_TYPE_MSENC (0x0000001b) +#define NV2080_ENGINE_TYPE_NVENC0 NV2080_ENGINE_TYPE_MSENC /* Mutually exclusive alias */ +#define NV2080_ENGINE_TYPE_NVENC1 (0x0000001c) +#define NV2080_ENGINE_TYPE_NVENC2 (0x0000001d) +#define NV2080_ENGINE_TYPE_VP (0x0000001e) +#define NV2080_ENGINE_TYPE_ME (0x0000001f) +#define NV2080_ENGINE_TYPE_PPP (0x00000020) +#define NV2080_ENGINE_TYPE_MPEG (0x00000021) +#define NV2080_ENGINE_TYPE_SW (0x00000022) +#define NV2080_ENGINE_TYPE_CIPHER (0x00000023) +#define NV2080_ENGINE_TYPE_TSEC NV2080_ENGINE_TYPE_CIPHER +#define NV2080_ENGINE_TYPE_VIC (0x00000024) +#define NV2080_ENGINE_TYPE_MP (0x00000025) +#define NV2080_ENGINE_TYPE_SEC2 (0x00000026) +#define NV2080_ENGINE_TYPE_HOST (0x00000027) +#define NV2080_ENGINE_TYPE_DPU (0x00000028) +#define NV2080_ENGINE_TYPE_PMU (0x00000029) +#define NV2080_ENGINE_TYPE_FBFLCN (0x0000002a) +#define NV2080_ENGINE_TYPE_NVJPG (0x0000002b) +#define NV2080_ENGINE_TYPE_NVJPEG0 NV2080_ENGINE_TYPE_NVJPG +#define NV2080_ENGINE_TYPE_NVJPEG1 (0x0000002c) +#define NV2080_ENGINE_TYPE_NVJPEG2 (0x0000002d) +#define NV2080_ENGINE_TYPE_NVJPEG3 (0x0000002e) +#define NV2080_ENGINE_TYPE_NVJPEG4 (0x0000002f) +#define NV2080_ENGINE_TYPE_NVJPEG5 (0x00000030) +#define NV2080_ENGINE_TYPE_NVJPEG6 (0x00000031) +#define NV2080_ENGINE_TYPE_NVJPEG7 (0x00000032) +#define NV2080_ENGINE_TYPE_OFA (0x00000033) +#define NV2080_ENGINE_TYPE_OFA0 NV2080_ENGINE_TYPE_OFA +// Update the TYPE_COMP_DECOMP_COPYN defines as well when you update COPYN defines +#define NV2080_ENGINE_TYPE_COPY10 (0x00000034) +#define NV2080_ENGINE_TYPE_COPY11 (0x00000035) +#define NV2080_ENGINE_TYPE_COPY12 (0x00000036) +#define NV2080_ENGINE_TYPE_COPY13 (0x00000037) +#define NV2080_ENGINE_TYPE_COPY14 (0x00000038) +#define NV2080_ENGINE_TYPE_COPY15 (0x00000039) +#define NV2080_ENGINE_TYPE_COPY16 (0x0000003a) +#define NV2080_ENGINE_TYPE_COPY17 (0x0000003b) +#define NV2080_ENGINE_TYPE_COPY18 (0x0000003c) +#define NV2080_ENGINE_TYPE_COPY19 (0x0000003d) +#define NV2080_ENGINE_TYPE_OFA1 (0x0000003e) +#define NV2080_ENGINE_TYPE_NVENC3 (0x0000003f) +// See TBD documentation for how these defines work with existing ENGINE_TYPE_COPYN defines +#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0 (0x00000040) +#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY1 (0x00000041) +#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY2 (0x00000042) +#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY3 (0x00000043) +#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY4 (0x00000044) +#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY5 (0x00000045) +#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY6 (0x00000046) +#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY7 (0x00000047) +#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY8 (0x00000048) +#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY9 (0x00000049) +#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY10 (0x0000004a) +#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY11 (0x0000004b) +#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY12 (0x0000004c) +#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY13 (0x0000004d) +#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY14 (0x0000004e) +#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY15 (0x0000004f) +#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY16 (0x00000050) +#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY17 (0x00000051) +#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY18 (0x00000052) +#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY19 (0x00000053) +#define NV2080_ENGINE_TYPE_LAST (0x00000054) +#define NV2080_ENGINE_TYPE_ALLENGINES (0xffffffff) + +// +// NV2080_ENGINE_TYPE_COPY_SIZE is now defined as the maximum possible CE size. +// It does not reflect the max supported NV2080_ENGINE_TYPE_COPY counts. Bug 3713687 #90. +// It needs to use NV2080_ENGINE_TYPE_IS_COPY() to check if a CE is valid when +// the clients try to enumerate all NV2080_ENGINE_TYPE_COPYs. +// +#define NV2080_ENGINE_TYPE_COPY_SIZE 64 + +// Bug 4175886 - Use this new value for all chips once GB20X is released +#define NV2080_ENGINE_TYPE_NVENC_SIZE 4 +#define NV2080_ENGINE_TYPE_NVJPEG_SIZE 8 +#define NV2080_ENGINE_TYPE_NVDEC_SIZE 8 +#define NV2080_ENGINE_TYPE_GR_SIZE 8 +#define NV2080_ENGINE_TYPE_OFA_SIZE 2 + +// Indexed engines +#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY(i) (NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0 + (i)) +#define NV2080_ENGINE_TYPE_IS_COMP_DECOMP_COPY(i) (((i) >= NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0) && ((i) <= NV2080_ENGINE_TYPE_COMP_DECOMP_COPY19)) +#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY_IDX(i) ((i) - NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0) + +#define NV2080_ENGINE_TYPE_COPY(i) (((i) < 10) ? (NV2080_ENGINE_TYPE_COPY0 + (i)) : (NV2080_ENGINE_TYPE_COPY10 + (i) - 10)) +#define NV2080_ENGINE_TYPE_IS_COPY(i) ((((i) >= NV2080_ENGINE_TYPE_COPY0) && ((i) <= NV2080_ENGINE_TYPE_COPY9)) || \ + (((i) >= NV2080_ENGINE_TYPE_COPY10) && ((i) <= NV2080_ENGINE_TYPE_COPY19))) +#define NV2080_ENGINE_TYPE_COPY_IDX(i) (((i) <= NV2080_ENGINE_TYPE_COPY9) ? \ + ((i) - NV2080_ENGINE_TYPE_COPY0) : ((i) - NV2080_ENGINE_TYPE_COPY10 + 10)) + +#define NV2080_ENGINE_TYPE_NVENC(i) (((i) < 3) ? (NV2080_ENGINE_TYPE_NVENC0 + (i)) : (NV2080_ENGINE_TYPE_NVENC3 + (i) - 3)) +#define NV2080_ENGINE_TYPE_IS_NVENC(i) ((((i) >= NV2080_ENGINE_TYPE_NVENC0) && ((i) <= NV2080_ENGINE_TYPE_NVENC2)) || \ + (((i) == NV2080_ENGINE_TYPE_NVENC3))) +#define NV2080_ENGINE_TYPE_NVENC_IDX(i) (((i) <= NV2080_ENGINE_TYPE_NVENC2) ? \ + ((i)-NV2080_ENGINE_TYPE_NVENC0) : ((i)-NV2080_ENGINE_TYPE_NVENC3 + 3)) + +#define NV2080_ENGINE_TYPE_NVDEC(i) (NV2080_ENGINE_TYPE_NVDEC0+(i)) +#define NV2080_ENGINE_TYPE_IS_NVDEC(i) (((i) >= NV2080_ENGINE_TYPE_NVDEC0) && ((i) < NV2080_ENGINE_TYPE_NVDEC(NV2080_ENGINE_TYPE_NVDEC_SIZE))) +#define NV2080_ENGINE_TYPE_NVDEC_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVDEC0) + +#define NV2080_ENGINE_TYPE_NVJPEG(i) (NV2080_ENGINE_TYPE_NVJPEG0+(i)) +#define NV2080_ENGINE_TYPE_IS_NVJPEG(i) (((i) >= NV2080_ENGINE_TYPE_NVJPEG0) && ((i) < NV2080_ENGINE_TYPE_NVJPEG(NV2080_ENGINE_TYPE_NVJPEG_SIZE))) +#define NV2080_ENGINE_TYPE_NVJPEG_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVJPEG0) + +#define NV2080_ENGINE_TYPE_GR(i) (NV2080_ENGINE_TYPE_GR0 + (i)) +#define NV2080_ENGINE_TYPE_IS_GR(i) (((i) >= NV2080_ENGINE_TYPE_GR0) && ((i) < NV2080_ENGINE_TYPE_GR(NV2080_ENGINE_TYPE_GR_SIZE))) +#define NV2080_ENGINE_TYPE_GR_IDX(i) ((i) - NV2080_ENGINE_TYPE_GR0) + +#define NV2080_ENGINE_TYPE_OFAn(i) ((i == 0) ? (NV2080_ENGINE_TYPE_OFA0) : (NV2080_ENGINE_TYPE_OFA1)) +#define NV2080_ENGINE_TYPE_IS_OFA(i) (((i) == NV2080_ENGINE_TYPE_OFA0) || ((i) == NV2080_ENGINE_TYPE_OFA1)) +#define NV2080_ENGINE_TYPE_OFA_IDX(i) ((i == NV2080_ENGINE_TYPE_OFA0) ? ((i) - NV2080_ENGINE_TYPE_OFA0) : ((i) - NV2080_ENGINE_TYPE_OFA1 + 1)) + +#define NV2080_ENGINE_TYPE_IS_VALID(i) (((i) > (NV2080_ENGINE_TYPE_NULL)) && ((i) < (NV2080_ENGINE_TYPE_LAST))) + +/* exported client defines */ +#define NV2080_CLIENT_TYPE_TEX (0x00000001) +#define NV2080_CLIENT_TYPE_COLOR (0x00000002) +#define NV2080_CLIENT_TYPE_DEPTH (0x00000003) +#define NV2080_CLIENT_TYPE_DA (0x00000004) +#define NV2080_CLIENT_TYPE_FE (0x00000005) +#define NV2080_CLIENT_TYPE_SCC (0x00000006) +#define NV2080_CLIENT_TYPE_WID (0x00000007) +#define NV2080_CLIENT_TYPE_MSVLD (0x00000008) +#define NV2080_CLIENT_TYPE_MSPDEC (0x00000009) +#define NV2080_CLIENT_TYPE_MSPPP (0x0000000a) +#define NV2080_CLIENT_TYPE_VIC (0x0000000b) +#define NV2080_CLIENT_TYPE_ALLCLIENTS (0xffffffff) + +/* GC5 Gpu Ready event defines */ +#define NV2080_GC5_EXIT_COMPLETE (0x00000001) +#define NV2080_GC5_ENTRY_ABORTED (0x00000002) + +/* Platform Power Mode event defines */ +#define NV2080_PLATFORM_POWER_MODE_CHANGE_COMPLETION (0x00000000) +#define NV2080_PLATFORM_POWER_MODE_CHANGE_ACPI_NOTIFICATION (0x00000001) + +/* NvNotification[] fields and values */ +#define NV2080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +typedef volatile struct _cl2080_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv2080Typedef, Nv20Subdevice0; +#define NV2080_TYPEDEF Nv20Subdevice0 + +/* HDCP Status change notification information */ +typedef struct Nv2080HdcpStatusChangeNotificationRec { + NvU32 displayId; + NvU32 hdcpStatusChangeNotif; +} Nv2080HdcpStatusChangeNotification; + +/* Pstate change notification information */ +typedef struct Nv2080PStateChangeNotificationRec { + struct { + NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/ + } timeStamp; /* -0007*/ + NvU32 NewPstate; +} Nv2080PStateChangeNotification; + +/* Clocks change notification information */ +typedef struct Nv2080ClocksChangeNotificationRec { + struct { + NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/ + } timeStamp; /* -0007*/ +} Nv2080ClocksChangeNotification; + +/* WorkLoad Modulation state change notification information*/ +typedef struct Nv2080WorkloadModulationChangeNotificationRec { + struct { + NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/ + } timeStamp; /* -0007*/ + NvBool WorkloadModulationEnabled; +} Nv2080WorkloadModulationChangeNotification; + +/* Hotplug notification information */ +typedef struct { + NvU32 plugDisplayMask; + NvU32 unplugDisplayMask; +} Nv2080HotplugNotification; + +/* Power state changing notification information */ +typedef struct { + NvBool bSwitchToAC; + NvBool bGPUCapabilityChanged; + NvU32 displayMaskAffected; +} Nv2080PowerEventNotification; + +/* DP IRQ notification information */ +typedef struct Nv2080DpIrqNotificationRec { + NvU32 displayId; +} Nv2080DpIrqNotification; + +/* XUSB/PPC D-State change notification information */ +typedef struct Nv2080DstateXusbPpcNotificationRec { + NvU32 dstateXusb; + NvU32 dstatePpc; +} Nv2080DstateXusbPpcNotification; + +/* XUSB/PPC Connection status notification information */ +typedef struct Nv2080XusbPpcConnectStateNotificationRec { + NvBool bConnected; +} Nv2080XusbPpcConnectStateNotification; + +/* ACPI event notification information */ +typedef struct Nv2080ACPIEvent { + NvU32 event; +} Nv2080ACPIEvent; + +/* Cooler Zone notification information */ +typedef struct _NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC { + NvU32 currentZone; +} NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC; + +/* Thermal Zone notification information */ +typedef struct _NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC { + NvU32 currentZone; +} NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC; + +/* HDCP ref count change notification information */ +typedef struct Nv2080AudioHdcpRequestRec { + NvU32 displayId; + NvU32 requestedState; +} Nv2080AudioHdcpRequest; + +/* Gpu ready event information */ +typedef struct Nv2080GC5GpuReadyParams { + NvU32 event; + NvU32 sciIntr0; + NvU32 sciIntr1; +} Nv2080GC5GpuReadyParams; + +/* Priv reg access fault notification information */ +typedef struct { + NvU32 errAddr; +} Nv2080PrivRegAccessFaultNotification; + +/* HDA D-State change notification information + * See @HDACODEC_DSTATE for definitions + */ +typedef struct Nv2080DstateHdaCodecNotificationRec { + NvU32 dstateHdaCodec; +} Nv2080DstateHdaCodecNotification; + +/* HDMI FRL retraining request notification information */ +typedef struct Nv2080HdmiFrlRequestNotificationRec { + NvU32 displayId; +} Nv2080HdmiFrlRequestNotification; + +/* + * Platform Power Mode event information + */ +typedef struct _NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS { + NvU8 platformPowerModeIndex; + NvU8 platformPowerModeMask; + NvU8 eventReason; +} NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS; + +/* + * Workload type update event information. Workload type is enumerated as per the + * NV2080_CTRL_PERF_PERF_CF_CONTROLLER_DLCC_WORKLOAD_TYPE_ENUM + */ +typedef struct _NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE { + NvU8 workloadType; +} NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE; + +#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_INDEX 7:0 +#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_MASK 15:8 +#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_REASON 23:16 + +/* + * ENGINE_INFO_TYPE_NV2080 of the engine for which the QOS interrupt has been raised + */ +typedef struct { + NvU32 engineType; +} Nv2080QosIntrNotification; + +typedef struct { + NvU64 physAddress NV_ALIGN_BYTES(8); +} Nv2080EccDbeNotification; + +/* + * LPWR DIFR Prefetch Request - Size of L2 Cache + */ +typedef struct { + NvU32 l2CacheSize; +} Nv2080LpwrDifrPrefetchNotification; + +/* + * Nvlink Link status change Notification + */ +typedef struct { + NvU32 GpuId; + NvU32 linkId; +} Nv2080NvlinkLnkChangeNotification; + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl2080_notification_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl2081.h b/userspace/sdks/nv570/inc/class/cl2081.h new file mode 100644 index 0000000..2d1cede --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl2081.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl2081.finn +// + +#define NV2081_BINAPI (0x2081U) /* finn: Evaluated from "NV2081_ALLOC_PARAMETERS_MESSAGE_ID" */ + +#define NV2081_ALLOC_PARAMETERS_MESSAGE_ID (0x2081U) + +typedef struct NV2081_ALLOC_PARAMETERS { + NvU32 reserved; +} NV2081_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/cl2082.h b/userspace/sdks/nv570/inc/class/cl2082.h new file mode 100644 index 0000000..0846209 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl2082.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl2082.finn +// + +#define NV2082_BINAPI_PRIVILEGED (0x2082U) /* finn: Evaluated from "NV2082_ALLOC_PARAMETERS_MESSAGE_ID" */ + +#define NV2082_ALLOC_PARAMETERS_MESSAGE_ID (0x2082U) + +typedef struct NV2082_ALLOC_PARAMETERS { + NvU32 reserved; +} NV2082_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/cl208f.h b/userspace/sdks/nv570/inc/class/cl208f.h new file mode 100644 index 0000000..d6dc3f3 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl208f.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2006 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl208f_h_ +#define _cl208f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Class within the subdevice used for diagnostic purpose*/ +#define NV20_SUBDEVICE_DIAG (0x0000208f) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl208f_h_ */ + diff --git a/userspace/sdks/nv570/inc/class/cl30f1.h b/userspace/sdks/nv570/inc/class/cl30f1.h new file mode 100644 index 0000000..ffba5e1 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl30f1.h @@ -0,0 +1,56 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl30f1.finn +// + +#include "cl30f1_notification.h" + +/* class NV30_GSYNC */ +#define NV30_GSYNC (0x30f1U) /* finn: Evaluated from "NV30F1_ALLOC_PARAMETERS_MESSAGE_ID" */ + +#define NV30F1_GSYNC_CONNECTOR_ONE (0) +#define NV30F1_GSYNC_CONNECTOR_TWO (1) +#define NV30F1_GSYNC_CONNECTOR_THREE (2) +#define NV30F1_GSYNC_CONNECTOR_FOUR (3) + +#define NV30F1_GSYNC_CONNECTOR_PRIMARY NV30F1_GSYNC_CONNECTOR_ONE +#define NV30F1_GSYNC_CONNECTOR_SECONDARY NV30F1_GSYNC_CONNECTOR_TWO + +#define NV30F1_GSYNC_CONNECTOR_COUNT (4) + +/* NvRmAlloc parameters */ +#define NV30F1_MAX_GSYNCS (0x0000004) + +#define NV30F1_ALLOC_PARAMETERS_MESSAGE_ID (0x30f1U) + +typedef struct NV30F1_ALLOC_PARAMETERS { + NvU32 gsyncInstance; +} NV30F1_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/cl30f1_notification.h b/userspace/sdks/nv570/inc/class/cl30f1_notification.h new file mode 100644 index 0000000..290eb5c --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl30f1_notification.h @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl30f1_notification_h_ +#define _cl30f1_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * A client should use NV01_EVENT_OS_EVENT as hClass and NV30F1_GSYNC_NOTIFIERS_* as + * notify index when allocating event, if separate event notifications are needed for + * separate event types. + * + * A client should use NV01_EVENT_KERNEL_CALLBACK as hClass and + * NV30F1_GSYNC_NOTIFIERS_ALL as notify index, if a single event is required. + * In this case RM would set event data equal to a pointer to NvNotification structure. + * The info32 field of NvNotification structure would be equal a bitmask of + * NV30F1_GSYNC_NOTIFIERS_* values. + */ + +/* NvNotification[] fields and values */ + +/* Framelock sync gain and loss events. These are connector specific events. */ +#define NV30F1_GSYNC_NOTIFIERS_SYNC_LOSS(c) (0x00+(c)) +#define NV30F1_GSYNC_NOTIFIERS_SYNC_GAIN(c) (0x04+(c)) + +/* Framelock stereo gain and loss events. These are connector specific events. */ +#define NV30F1_GSYNC_NOTIFIERS_STEREO_LOSS(c) (0x08+(c)) +#define NV30F1_GSYNC_NOTIFIERS_STEREO_GAIN(c) (0x0C+(c)) + +/* House cable gain(plug in) and loss(plug out) events. */ +#define NV30F1_GSYNC_NOTIFIERS_HOUSE_GAIN (0x10) +#define NV30F1_GSYNC_NOTIFIERS_HOUSE_LOSS (0x11) + +/* RJ45 cable gain(plug in) and loss(plug out) events. */ +#define NV30F1_GSYNC_NOTIFIERS_RJ45_GAIN (0x12) +#define NV30F1_GSYNC_NOTIFIERS_RJ45_LOSS (0x13) + +#define NV30F1_GSYNC_NOTIFIERS_MAXCOUNT (0x14) + +/* + * For handling all event types. + * Note for Windows, it only handles NV01_EVENT_KERNEL_CALLBACK_EX; as for NV01_EVENT_OS_EVENT, it can only + * signal an event but not handle over any information. + */ +#define NV30F1_GSYNC_NOTIFIERS_ALL NV30F1_GSYNC_NOTIFIERS_MAXCOUNT + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl30f1_notification_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl402c.h b/userspace/sdks/nv570/inc/class/cl402c.h new file mode 100644 index 0000000..9ba7c3b --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl402c.h @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2010 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl402c_h_ +#define _cl402c_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* I2C operations */ +#define NV40_I2C (0x0000402c) + +typedef volatile struct _cl402c_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv402cTypedef, Nv40I2c; +#define NV402C_TYPEDEF Nv40I2c + + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl402c_h_ */ + diff --git a/userspace/sdks/nv570/inc/class/cl503b.h b/userspace/sdks/nv570/inc/class/cl503b.h new file mode 100644 index 0000000..4fd9f61 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl503b.h @@ -0,0 +1,81 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl503b.finn +// + +#define NV50_P2P (0x503bU) /* finn: Evaluated from "NV503B_ALLOC_PARAMETERS_MESSAGE_ID" */ + +#define NV503B_FLAGS_P2P_TYPE 0:0 +#define NV503B_FLAGS_P2P_TYPE_GPA 0 +#define NV503B_FLAGS_P2P_TYPE_SPA 1 + +/* + * NV503B_BAR1_P2P_DMA_INFO + * + * The DMA information for BAR1 P2P. + * The default value for dma_address is NV_U64_MAX and dma_size is 0. + * This BAR1 P2P DMA information is only valid for the kernel-privileged clients. + * For unprivileged clients, all fields will be the default values. + * + */ +typedef struct NV503B_BAR1_P2P_DMA_INFO { + NV_DECLARE_ALIGNED(NvU64 dma_address, 8); + NV_DECLARE_ALIGNED(NvU64 dma_size, 8); +} NV503B_BAR1_P2P_DMA_INFO; + +typedef struct NV503B_FABRIC_P2P_DMA_INFO { + NV_DECLARE_ALIGNED(NvU64 gpa, 8); +} NV503B_FABRIC_P2P_DMA_INFO; + +/* NvRmAlloc parameters */ +#define NV503B_ALLOC_PARAMETERS_MESSAGE_ID (0x503bU) + +typedef struct NV503B_ALLOC_PARAMETERS { + NvHandle hSubDevice; /* subDevice handle of local GPU */ + NvHandle hPeerSubDevice; /* subDevice handle of peer GPU */ + NvU32 subDevicePeerIdMask; /* Bit mask of peer ID for SubDevice + * A value of 0 defaults to RM selected + * PeerIdMasks must match in loopback */ + NvU32 peerSubDevicePeerIdMask; /* Bit mask of peer ID for PeerSubDevice + * A value of 0 defaults to RM selected + * PeerIdMasks must match in loopback */ + NV_DECLARE_ALIGNED(NvU64 mailboxBar1Addr, 8); /* P2P Mailbox area base offset in BAR1 + * Must have the same value across the GPUs */ + NvU32 mailboxTotalSize; /* Size of the P2P Mailbox area + * Must have the same value across the GPUs */ + NvU32 flags; /* Flag to indicate types/attib of p2p */ + NvU32 subDeviceEgmPeerIdMask; /* Bit mask of EGM peer ID of SubDevice */ + NvU32 peerSubDeviceEgmPeerIdMask; /* Bit mask of EGM peer ID for PeerSubDevice */ + NV_DECLARE_ALIGNED(NV503B_BAR1_P2P_DMA_INFO l2pBar1P2PDmaInfo, 8); /* Bar1 DMA info from local GPU to peer GPU */ + NV_DECLARE_ALIGNED(NV503B_BAR1_P2P_DMA_INFO p2lBar1P2PDmaInfo, 8); /* Bar1 DMA info from peer GPU to local GPU */ + NV_DECLARE_ALIGNED(NV503B_FABRIC_P2P_DMA_INFO l2pFabricP2PInfo, 8); /* NVLink fabric base address of the local GPU. Used in switch systems */ + NV_DECLARE_ALIGNED(NV503B_FABRIC_P2P_DMA_INFO p2lFabricP2PInfo, 8); /* NVLink fabric base address of the remote GPU. Used in switch systems */ +} NV503B_ALLOC_PARAMETERS; diff --git a/userspace/sdks/nv570/inc/class/cl503c.h b/userspace/sdks/nv570/inc/class/cl503c.h new file mode 100644 index 0000000..6cfeabf --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl503c.h @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl503c.finn +// + +#define NV50_THIRD_PARTY_P2P (0x503cU) /* finn: Evaluated from "NV503C_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* NvRmAlloc parameters */ +#define NV503C_ALLOC_PARAMETERS_MESSAGE_ID (0x503cU) + +typedef struct NV503C_ALLOC_PARAMETERS { + NvU32 flags; +} NV503C_ALLOC_PARAMETERS; + +#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE 1:0 +#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_PROPRIETARY (0x00000000) +#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_BAR1 (0x00000001) +#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_NVLINK (0x00000002) + diff --git a/userspace/sdks/nv570/inc/class/cl506f.h b/userspace/sdks/nv570/inc/class/cl506f.h new file mode 100644 index 0000000..b086c43 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl506f.h @@ -0,0 +1,157 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl506f_h_ +#define _cl506f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class NV50_CHANNEL_GPFIFO */ +#define NV50_CHANNEL_GPFIFO (0x0000506F) + +/* NvNotification[] elements */ +#define NV506F_NOTIFIERS_RC (0) +#define NV506F_NOTIFIERS_SW (1) +#define NV506F_NOTIFIERS_GR_DEBUG_INTR (2) +#define NV506F_NOTIFIERS_MAXCOUNT (3) + +/* NvNotification[] fields and values */ +#define NV506f_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NV506f_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +typedef volatile struct _cl506f_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv506fTypedef, Nv50ChannelGPFifo; +#define NV506F_TYPEDEF Nv50ChannelGPFifo +/* pio flow control data structure */ +typedef volatile struct _cl506f_tag1 { + NvU32 Ignored00[0x010]; /* 0000-0039*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 SetReference; /* set reference value 0050-0053*/ + NvU32 Ignored02[0x001]; /* 0054-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored03[0x007]; /* 0064-007f*/ + NvU32 Yield; /* engine yield, write only 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x3dc]; +} Nv506fControl, Nv50ControlGPFifo; +/* fields and values */ +#define NV506F_NUMBER_OF_SUBCHANNELS (8) +#define NV506F_SET_OBJECT (0x00000000) +#define NV506F_SET_REFERENCE (0x00000050) +#define NV506F_SET_CONTEXT_DMA_SEMAPHORE (0x00000060) +#define NV506F_SEMAPHORE_OFFSET (0x00000064) +#define NV506F_SEMAPHORE_ACQUIRE (0x00000068) +#define NV506F_SEMAPHORE_RELEASE (0x0000006c) +#define NV506F_YIELD (0x00000080) + +// +// GPFIFO entry format +// +#define NV506F_GP_ENTRY__SIZE 8 +#define NV506F_GP_ENTRY0_DISABLE 0:0 +#define NV506F_GP_ENTRY0_DISABLE_NOT 0x00000000 +#define NV506F_GP_ENTRY0_DISABLE_SKIP 0x00000001 +#define NV506F_GP_ENTRY0_NO_CONTEXT_SWITCH 1:1 +#define NV506F_GP_ENTRY0_NO_CONTEXT_SWITCH_FALSE 0x00000000 +#define NV506F_GP_ENTRY0_NO_CONTEXT_SWITCH_TRUE 0x00000001 +#define NV506F_GP_ENTRY0_GET 31:2 +#define NV506F_GP_ENTRY1_GET_HI 7:0 +#define NV506F_GP_ENTRY1_PRIV 8:8 +#define NV506F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NV506F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NV506F_GP_ENTRY1_LEVEL 9:9 +#define NV506F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NV506F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NV506F_GP_ENTRY1_LENGTH 31:10 + +/* dma method descriptor formats */ +#define NV506F_DMA_PRIMARY_OPCODE 1:0 +#define NV506F_DMA_PRIMARY_OPCODE_USES_SECONDARY (0x00000000) +#define NV506F_DMA_PRIMARY_OPCODE_RESERVED (0x00000003) +#define NV506F_DMA_METHOD_ADDRESS 12:2 +#define NV506F_DMA_METHOD_SUBCHANNEL 15:13 +#define NV506F_DMA_TERT_OP 17:16 +#define NV506F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NV506F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NV506F_DMA_TERT_OP_GRP0_DOUBLE_HEADER (0x00000003) +#define NV506F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NV506F_DMA_TERT_OP_GRP2_RESERVED01 (0x00000001) +#define NV506F_DMA_TERT_OP_GRP2_RESERVED10 (0x00000002) +#define NV506F_DMA_TERT_OP_GRP2_RESERVED11 (0x00000003) +#define NV506F_DMA_METHOD_COUNT 28:18 +#define NV506F_DMA_SEC_OP 31:29 +#define NV506F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NV506F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NV506F_DMA_SEC_OP_GRP3_RESERVED (0x00000003) +#define NV506F_DMA_SEC_OP_GRP4_RESERVED (0x00000004) +#define NV506F_DMA_SEC_OP_GRP5_RESERVED (0x00000005) +#define NV506F_DMA_SEC_OP_GRP6_RESERVED (0x00000006) +#define NV506F_DMA_SEC_OP_GRP7_RESERVED (0x00000007) +#define NV506F_DMA_LONG_COUNT 31:0 +/* dma legacy method descriptor format */ +#define NV506F_DMA_OPCODE2 1:0 +#define NV506F_DMA_OPCODE2_NONE (0x00000000) +#define NV506F_DMA_OPCODE 31:29 +#define NV506F_DMA_OPCODE_METHOD (0x00000000) +#define NV506F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NV506F_DMA_OPCODE3_NONE (0x00000000) +/* dma data format */ +#define NV506F_DMA_DATA 31:0 +/* dma double header descriptor format */ +#define NV506F_DMA_DH_OPCODE2 1:0 +#define NV506F_DMA_DH_OPCODE2_NONE (0x00000000) +#define NV506F_DMA_DH_METHOD_ADDRESS 12:2 +#define NV506F_DMA_DH_METHOD_SUBCHANNEL 15:13 +#define NV506F_DMA_DH_OPCODE3 17:16 +#define NV506F_DMA_DH_OPCODE3_DOUBLE_HEADER (0x00000003) +#define NV506F_DMA_DH_OPCODE 31:29 +#define NV506F_DMA_DH_OPCODE_METHOD (0x00000000) +/* dma double header method count format */ +#define NV506F_DMA_DH_METHOD_COUNT 23:0 +/* dma double header data format */ +#define NV506F_DMA_DH_DATA 31:0 +/* dma nop format */ +#define NV506F_DMA_NOP (0x00000000) +/* dma set subdevice mask format */ +#define NV506F_DMA_SET_SUBDEVICE_MASK (0x00010000) +#define NV506F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NV506F_DMA_OPCODE3 17:16 +#define NV506F_DMA_OPCODE3_SET_SUBDEVICE_MASK (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl506f_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl5070.h b/userspace/sdks/nv570/inc/class/cl5070.h new file mode 100644 index 0000000..9d16514 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl5070.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl5070.finn +// + +#include "cl5070_notification.h" + +#define NV50_DISPLAY (0x5070U) /* finn: Evaluated from "NV5070_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV5070_ALLOCATION_PARAMETERS_MESSAGE_ID (0x5070U) + +typedef struct NV5070_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numDacs; // Number of DACs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NV5070_ALLOCATION_PARAMETERS; diff --git a/userspace/sdks/nv570/inc/class/cl5070_notification.h b/userspace/sdks/nv570/inc/class/cl5070_notification.h new file mode 100644 index 0000000..a23107d --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl5070_notification.h @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl5070_notification_h_ +#define _cl5070_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* event values */ +#define NV5070_NOTIFIERS_SW (0) +#define NV5070_NOTIFIERS_MAXCOUNT (1) + +#define NV5070_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NV5070_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000) +#define NV5070_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000) +#define NV5070_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000) +#define NV5070_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl5070_notification_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl5080.h b/userspace/sdks/nv570/inc/class/cl5080.h new file mode 100644 index 0000000..8411758 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl5080.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2002-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl5080.finn +// + +#include "cl5080_notification.h" + +#define NV50_DEFERRED_API_CLASS (0x5080U) /* finn: Evaluated from "NV5080_ALLOC_PARAMS_MESSAGE_ID" */ + +/* NvRmAlloc parameters */ +#define NV5080_ALLOC_PARAMS_MESSAGE_ID (0x5080U) + +typedef struct NV5080_ALLOC_PARAMS { + // Should the deferred api completion trigger an event + NvBool notifyCompletion; +} NV5080_ALLOC_PARAMS; + +// Class-specific allocation capabilities + diff --git a/userspace/sdks/nv570/inc/class/cl5080_notification.h b/userspace/sdks/nv570/inc/class/cl5080_notification.h new file mode 100644 index 0000000..170c8fb --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl5080_notification.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl5080_notification_h_ +#define _cl5080_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* dma method offsets, fields, and values */ +#define NV5080_SET_OBJECT (0x00000000) +#define NV5080_NO_OPERATION (0x00000100) +#define NV5080_DEFERRED_API (0x00000200) +#define NV5080_DEFERRED_API_HANDLE 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl5080_notification_h_ */ + diff --git a/userspace/sdks/nv570/inc/class/cl50a0.h b/userspace/sdks/nv570/inc/class/cl50a0.h new file mode 100644 index 0000000..5fec57e --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl50a0.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2005, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl50a0_h_ +#define _cl50a0_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV50_MEMORY_VIRTUAL (0x000050a0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl50a0_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl83de.h b/userspace/sdks/nv570/inc/class/cl83de.h new file mode 100644 index 0000000..6491622 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl83de.h @@ -0,0 +1,56 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl83de.finn +// + +#define GT200_DEBUGGER (0x83deU) /* finn: Evaluated from "NV83DE_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* + * Creating the GT200_DEBUGGER object: + * - The debug object is instantiated as a child of either the compute or the + * 3D-class object. + * - The Cuda/GR debugger uses the NV83DE_ALLOC_PARAMETERS to fill in the Client + * and 3D-Class handles of the debuggee and passes this to the NvRmAlloc. + * e.g: + NV83DE_ALLOC_PARAMETERS params; + * memset (¶ms, 0, sizeof (NV83DE_ALLOC_PARAMETERS)); + * params.hAppClient = DebuggeeClient; + * params.hClass3dObject = 3DClassHandle; + * NvRmAlloc(hDebuggerClient, hDebuggerClient, hDebugger, GT200_DEBUGGER, ¶ms); + */ + +#define NV83DE_ALLOC_PARAMETERS_MESSAGE_ID (0x83deU) + +typedef struct NV83DE_ALLOC_PARAMETERS { + NvHandle hDebuggerClient_Obsolete; // No longer supported (must be zero) + NvHandle hAppClient; + NvHandle hClass3dObject; +} NV83DE_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/cl844c.h b/userspace/sdks/nv570/inc/class/cl844c.h new file mode 100644 index 0000000..c4afe5f --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl844c.h @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl844c_h_ +#define _cl844c_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define G84_PERFBUFFER (0x0000844C) + +/* pio method data structure */ +typedef volatile struct _cl844c_tag0 { + NvV32 Reserved00[0x7c0]; +} G844cTypedef, G84PerfBuffer; +#define G844C_TYPEDEF G84PerfBuffer + +#define G844C_PERFBUFFER_MEMORY_HANDLE (0x844C0001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl844c_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl84a0.h b/userspace/sdks/nv570/inc/class/cl84a0.h new file mode 100644 index 0000000..a1f6d90 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl84a0.h @@ -0,0 +1,110 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl84a0.finn +// + +#include "cl84a0_deprecated.h" + +/* + * Class definitions for creating a memory descriptor from a list of page numbers + * in RmAllocMemory. No memory is allocated: only a memory descriptor and + * memory object are created for later use in other calls. These classes + * are used by vGPU to create references to memory assigned to a guest VM. + * In all cases, the list is passed as reference, in the pAddress argument + * of RmAllocMemory, to a Nv01MemoryList structure (cast to a void **). + */ + +/* List of system memory physical page numbers */ +#define NV01_MEMORY_LIST_SYSTEM (0x00000081) +/* List of frame buffer physical page numbers */ +#define NV01_MEMORY_LIST_FBMEM (0x00000082) +/* List of page numbers relative to the start of the specified object */ +#define NV01_MEMORY_LIST_OBJECT (0x00000083) + +/* + * List structure of NV01_MEMORY_LIST_* classes + * + * The pageNumber array is variable in length, with pageCount elements, + * so the allocated size of the structure must reflect that. + * + * FBMEM items apply only to NV01_MEMORY_LIST_FBMEM and to + * NV01_MEMORY_LIST_OBJECT when the underlying object is + * FBMEM (must be zero for other cases) + * + * NV_MEMORY_LIST_ALLOCATION_PARAMS - Allocation params to create memory list + * through NvRmAlloc. + */ +#define NV_MEMORY_LIST_ALLOCATION_PARAMS_MESSAGE_ID (0x84a0U) + +typedef struct NV_MEMORY_LIST_ALLOCATION_PARAMS { + NvHandle hClient; /* client to which object belongs + * (may differ from client creating the mapping). + * May be NV01_NULL_OBJECT, in which case client + * handle is used */ + NvHandle hParent; /* device with which object is associated. + * Must be NV01_NULL_OBJECT if hClient is NV01_NULL_OBJECT. + * Must not be NV01_NULL_OBJECT if hClient is + * not NV01_NULL_OBJECT. */ + NvHandle hObject; /* object to which pages are relative + * (NV01_NULL_OBJECT for NV01_MEMORY_LIST_SYSTEM + * and NV01_MEMORY_LIST_FBMEM) */ + NvHandle hHwResClient; /* client associated with the backdoor vnc surface*/ + NvHandle hHwResDevice; /* device associated to the bacdoor vnc surface*/ + NvHandle hHwResHandle; /* handle to hardware resources allocated to + * backdoor vnc surface*/ + NvU32 pteAdjust; /* offset of data in first page */ + NvU32 reserved_0; /* reserved: must be 0 */ + NvU32 type; /* FBMEM: NVOS32_TYPE_* */ + NvU32 flags; /* FBMEM: NVOS32_ALLOC_FLAGS_* */ + NvU32 attr; /* FBMEM: NVOS32_ATTR_* */ + NvU32 attr2; /* FBMEM: NVOS32_ATTR2_* */ + NvU32 height; /* FBMEM: height in pixels */ + NvU32 width; /* FBMEM: width in pixels */ + NvU32 format; /* FBMEM: memory kind */ + NvU32 comprcovg; /* FBMEM: compression coverage */ + NvU32 zcullcovg; /* FBMEM: Z-cull coverage */ + NvU32 pageCount; /* count of elements in pageNumber array */ + NvU32 heapOwner; /* heap owner information from client */ + + NV_DECLARE_ALIGNED(NvU64 guestId, 8); + /* ID of the guest VM. e.g., domain ID in case of Xen */ + NV_DECLARE_ALIGNED(NvU64 rangeBegin, 8); + /* preferred VA range start address */ + NV_DECLARE_ALIGNED(NvU64 rangeEnd, 8); + /* preferred VA range end address */ + NvU32 pitch; + NvU32 ctagOffset; + NV_DECLARE_ALIGNED(NvU64 size, 8); + NV_DECLARE_ALIGNED(NvU64 align, 8); + NV_DECLARE_ALIGNED(NvP64 pageNumberList, 8); + NV_DECLARE_ALIGNED(NvU64 limit, 8); + NvU32 flagsOs02; +} NV_MEMORY_LIST_ALLOCATION_PARAMS; + diff --git a/userspace/sdks/nv570/inc/class/cl84a0_deprecated.h b/userspace/sdks/nv570/inc/class/cl84a0_deprecated.h new file mode 100644 index 0000000..f1e7f0c --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl84a0_deprecated.h @@ -0,0 +1,90 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl84a0_deprecated_h_ +#define _cl84a0_deprecated_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * List structure of NV01_MEMORY_LIST_* classes + * + * The pageNumber array is variable in length, with pageCount elements, + * so the allocated size of the structure must reflect that. + * + * FBMEM items apply only to NV01_MEMORY_LIST_FBMEM and to + * NV01_MEMORY_LIST_OBJECT when the underlying object is + * FBMEM (must be zero for other cases) + * + * Nv01MemoryList is deprecated. NV_MEMORY_LIST_ALLOCATION_PARAMS should be used + * instead. + */ +typedef struct Nv01MemoryListRec { + NvHandle hClient; /* client to which object belongs + * (may differ from client creating the mapping). + * May be NV01_NULL_OBJECT, in which case client + * handle is used */ + NvHandle hParent; /* device with which object is associated. + * Must be NV01_NULL_OBJECT if hClient is NV01_NULL_OBJECT. + * Must not be NV01_NULL_OBJECT if hClient is + * not NV01_NULL_OBJECT. */ + NvHandle hObject; /* object to which pages are relative + * (NV01_NULL_OBJECT for NV01_MEMORY_LIST_SYSTEM + * and NV01_MEMORY_LIST_FBMEM) */ + NvHandle hHwResClient;/* client associated with the backdoor vnc surface*/ + NvHandle hHwResDevice;/* device associated to the bacdoor vnc surface*/ + NvHandle hHwResHandle;/* handle to hardware resources allocated to + * backdoor vnc surface*/ + NvU32 pteAdjust; /* offset of data in first page */ + NvU32 type; /* FBMEM: NVOS32_TYPE_* */ + NvU32 flags; /* FBMEM: NVOS32_ALLOC_FLAGS_* */ + NvU32 attr; /* FBMEM: NVOS32_ATTR_* */ + NvU32 attr2; /* FBMEM: NVOS32_ATTR2_* */ + NvU32 height; /* FBMEM: height in pixels */ + NvU32 width; /* FBMEM: width in pixels */ + NvU32 format; /* FBMEM: memory kind */ + NvU32 comprcovg; /* FBMEM: compression coverage */ + NvU32 zcullcovg; /* FBMEM: Z-cull coverage */ + NvU32 pageCount; /* count of elements in pageNumber array */ + NvU32 heapOwner; /* heap owner information from client */ + NvU32 reserved_1; /* reserved: must be 0 */ + NvU64 NV_DECLARE_ALIGNED(guestId,8); + /* ID of the guest VM. e.g., domain ID in case of Xen */ + NvU64 NV_DECLARE_ALIGNED(rangeBegin,8); + /* preferred VA range start address */ + NvU64 NV_DECLARE_ALIGNED(rangeEnd,8); + /* preferred VA range end address */ + NvU32 pitch; + NvU32 ctagOffset; + NvU64 size; + NvU64 align; + NvU64 pageNumber[1]; /* variable length array of page numbers */ +} Nv01MemoryList; + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl84a0_deprecated_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl85b5sw.h b/userspace/sdks/nv570/inc/class/cl85b5sw.h new file mode 100644 index 0000000..b741d52 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl85b5sw.h @@ -0,0 +1,38 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl85b5sw.finn +// + +#define NV85B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0x85b5U) + +typedef struct NV85B5_ALLOCATION_PARAMETERS { + NvU32 version; // set to 0 + NvU32 engineInstance; // CE instance +} NV85B5_ALLOCATION_PARAMETERS; diff --git a/userspace/sdks/nv570/inc/class/cl900e.h b/userspace/sdks/nv570/inc/class/cl900e.h new file mode 100644 index 0000000..6684889 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl900e.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl900e_h_ +#define _cl900e_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define MPS_COMPUTE (0x0000900E) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl900e_h_ */ + diff --git a/userspace/sdks/nv570/inc/class/cl9010.h b/userspace/sdks/nv570/inc/class/cl9010.h new file mode 100644 index 0000000..ad901c7 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl9010.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9010.finn +// + +#include "class/cl9010_callback.h" + +#define NV9010_VBLANK_CALLBACK (0x9010U) /* finn: Evaluated from "NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9010U) + +typedef struct NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS { + NV_DECLARE_ALIGNED(NvP64 pProc, 8); // Routine to call at vblank time + // A function pointer of OSVBLANKCALLBACKPROC + NvV32 LogicalHead; // Logical Head + NV_DECLARE_ALIGNED(NvP64 pParm1, 8); // pParm1 + NV_DECLARE_ALIGNED(NvP64 pParm2, 8); // pParm2 +} NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/cl9010_callback.h b/userspace/sdks/nv570/inc/class/cl9010_callback.h new file mode 100644 index 0000000..1945b68 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl9010_callback.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef SDK_CL9010_CALLBACK_H +#define SDK_CL9010_CALLBACK_H + +typedef void (*OSVBLANKCALLBACKPROC)(NvP64 pParm1, NvP64 pParm2); + +#endif // SDK_CL9010_CALLBACK_H diff --git a/userspace/sdks/nv570/inc/class/cl902d.h b/userspace/sdks/nv570/inc/class/cl902d.h new file mode 100644 index 0000000..38bd5cf --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl902d.h @@ -0,0 +1,1092 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_fermi_twod_a_h_ +#define _cl_fermi_twod_a_h_ + +#define FERMI_TWOD_A 0x902D + +typedef volatile struct fermi_twod_a_struct { + NvU32 SetObject; + NvU32 Reserved_0x04[0x3F]; + NvU32 NoOperation; + NvU32 SetNotifyA; + NvU32 SetNotifyB; + NvU32 Notify; + NvU32 WaitForIdle; + NvU32 LoadMmeInstructionRamPointer; + NvU32 LoadMmeInstructionRam; + NvU32 LoadMmeStartAddressRamPointer; + NvU32 LoadMmeStartAddressRam; + NvU32 SetMmeShadowRamControl; + NvU32 Reserved_0x128[0x2]; + NvU32 SetGlobalRenderEnableA; + NvU32 SetGlobalRenderEnableB; + NvU32 SetGlobalRenderEnableC; + NvU32 SendGoIdle; + NvU32 PmTrigger; + NvU32 Reserved_0x144[0x3]; + NvU32 SetInstrumentationMethodHeader; + NvU32 SetInstrumentationMethodData; + NvU32 Reserved_0x158[0x25]; + NvU32 SetMmeSwitchState; + NvU32 Reserved_0x1F0[0x4]; + NvU32 SetDstFormat; + NvU32 SetDstMemoryLayout; + NvU32 SetDstBlockSize; + NvU32 SetDstDepth; + NvU32 SetDstLayer; + NvU32 SetDstPitch; + NvU32 SetDstWidth; + NvU32 SetDstHeight; + NvU32 SetDstOffsetUpper; + NvU32 SetDstOffsetLower; + NvU32 FlushAndInvalidateRopMiniCache; + NvU32 SetSpareNoop06; + NvU32 SetSrcFormat; + NvU32 SetSrcMemoryLayout; + NvU32 SetSrcBlockSize; + NvU32 SetSrcDepth; + NvU32 TwodInvalidateTextureDataCache; + NvU32 SetSrcPitch; + NvU32 SetSrcWidth; + NvU32 SetSrcHeight; + NvU32 SetSrcOffsetUpper; + NvU32 SetSrcOffsetLower; + NvU32 SetPixelsFromMemorySectorPromotion; + NvU32 SetSpareNoop12; + NvU32 SetNumProcessingClusters; + NvU32 SetRenderEnableA; + NvU32 SetRenderEnableB; + NvU32 SetRenderEnableC; + NvU32 SetSpareNoop08; + NvU32 SetSpareNoop01; + NvU32 SetSpareNoop11; + NvU32 SetSpareNoop07; + NvU32 SetClipX0; + NvU32 SetClipY0; + NvU32 SetClipWidth; + NvU32 SetClipHeight; + NvU32 SetClipEnable; + NvU32 SetColorKeyFormat; + NvU32 SetColorKey; + NvU32 SetColorKeyEnable; + NvU32 SetRop; + NvU32 SetBeta1; + NvU32 SetBeta4; + NvU32 SetOperation; + NvU32 SetPatternOffset; + NvU32 SetPatternSelect; + NvU32 SetDstColorRenderToZetaSurface; + NvU32 SetSpareNoop04; + NvU32 SetSpareNoop15; + NvU32 SetSpareNoop13; + NvU32 SetSpareNoop03; + NvU32 SetSpareNoop14; + NvU32 SetSpareNoop02; + NvU32 SetCompression; + NvU32 SetSpareNoop09; + NvU32 SetRenderEnableOverride; + NvU32 SetPixelsFromMemoryDirection; + NvU32 SetSpareNoop10; + NvU32 SetMonochromePatternColorFormat; + NvU32 SetMonochromePatternFormat; + NvU32 SetMonochromePatternColor0; + NvU32 SetMonochromePatternColor1; + NvU32 SetMonochromePattern0; + NvU32 SetMonochromePattern1; + NvU32 ColorPatternX8R8G8B8[0x40]; + NvU32 ColorPatternR5G6B5[0x20]; + NvU32 ColorPatternX1R5G5B5[0x20]; + NvU32 ColorPatternY8[0x10]; + NvU32 SetRenderSolidPrimColor0; + NvU32 SetRenderSolidPrimColor1; + NvU32 SetRenderSolidPrimColor2; + NvU32 SetRenderSolidPrimColor3; + NvU32 SetMmeMemAddressA; + NvU32 SetMmeMemAddressB; + NvU32 SetMmeDataRamAddress; + NvU32 MmeDmaRead; + NvU32 MmeDmaReadFifoed; + NvU32 MmeDmaWrite; + NvU32 MmeDmaReduction; + NvU32 MmeDmaSysmembar; + NvU32 MmeDmaSync; + NvU32 SetMmeDataFifoConfig; + NvU32 Reserved_0x578[0x2]; + NvU32 RenderSolidPrimMode; + NvU32 SetRenderSolidPrimColorFormat; + NvU32 SetRenderSolidPrimColor; + NvU32 SetRenderSolidLineTieBreakBits; + NvU32 Reserved_0x590[0x14]; + NvU32 RenderSolidPrimPointXY; + NvU32 Reserved_0x5E4[0x7]; + struct { + NvU32 SetX; + NvU32 Y; + } RenderSolidPrimPoint[0x40]; + NvU32 SetPixelsFromCpuDataType; + NvU32 SetPixelsFromCpuColorFormat; + NvU32 SetPixelsFromCpuIndexFormat; + NvU32 SetPixelsFromCpuMonoFormat; + NvU32 SetPixelsFromCpuWrap; + NvU32 SetPixelsFromCpuColor0; + NvU32 SetPixelsFromCpuColor1; + NvU32 SetPixelsFromCpuMonoOpacity; + NvU32 Reserved_0x820[0x6]; + NvU32 SetPixelsFromCpuSrcWidth; + NvU32 SetPixelsFromCpuSrcHeight; + NvU32 SetPixelsFromCpuDxDuFrac; + NvU32 SetPixelsFromCpuDxDuInt; + NvU32 SetPixelsFromCpuDyDvFrac; + NvU32 SetPixelsFromCpuDyDvInt; + NvU32 SetPixelsFromCpuDstX0Frac; + NvU32 SetPixelsFromCpuDstX0Int; + NvU32 SetPixelsFromCpuDstY0Frac; + NvU32 SetPixelsFromCpuDstY0Int; + NvU32 PixelsFromCpuData; + NvU32 Reserved_0x864[0x3]; + NvU32 SetBigEndianControl; + NvU32 Reserved_0x874[0x3]; + NvU32 SetPixelsFromMemoryBlockShape; + NvU32 SetPixelsFromMemoryCorralSize; + NvU32 SetPixelsFromMemorySafeOverlap; + NvU32 SetPixelsFromMemorySampleMode; + NvU32 Reserved_0x890[0x8]; + NvU32 SetPixelsFromMemoryDstX0; + NvU32 SetPixelsFromMemoryDstY0; + NvU32 SetPixelsFromMemoryDstWidth; + NvU32 SetPixelsFromMemoryDstHeight; + NvU32 SetPixelsFromMemoryDuDxFrac; + NvU32 SetPixelsFromMemoryDuDxInt; + NvU32 SetPixelsFromMemoryDvDyFrac; + NvU32 SetPixelsFromMemoryDvDyInt; + NvU32 SetPixelsFromMemorySrcX0Frac; + NvU32 SetPixelsFromMemorySrcX0Int; + NvU32 SetPixelsFromMemorySrcY0Frac; + NvU32 PixelsFromMemorySrcY0Int; + NvU32 SetFalcon00; + NvU32 SetFalcon01; + NvU32 SetFalcon02; + NvU32 SetFalcon03; + NvU32 SetFalcon04; + NvU32 SetFalcon05; + NvU32 SetFalcon06; + NvU32 SetFalcon07; + NvU32 SetFalcon08; + NvU32 SetFalcon09; + NvU32 SetFalcon10; + NvU32 SetFalcon11; + NvU32 SetFalcon12; + NvU32 SetFalcon13; + NvU32 SetFalcon14; + NvU32 SetFalcon15; + NvU32 SetFalcon16; + NvU32 SetFalcon17; + NvU32 SetFalcon18; + NvU32 SetFalcon19; + NvU32 SetFalcon20; + NvU32 SetFalcon21; + NvU32 SetFalcon22; + NvU32 SetFalcon23; + NvU32 SetFalcon24; + NvU32 SetFalcon25; + NvU32 SetFalcon26; + NvU32 SetFalcon27; + NvU32 SetFalcon28; + NvU32 SetFalcon29; + NvU32 SetFalcon30; + NvU32 SetFalcon31; + NvU32 Reserved_0x960[0x123]; + NvU32 MmeDmaWriteMethodBarrier; + NvU32 Reserved_0xDF0[0x984]; + NvU32 SetMmeShadowScratch[0x100]; + struct { + NvU32 Macro; + NvU32 Data; + } CallMme[0xE0]; +} fermi_twod_a_t; + + +#define NV902D_SET_OBJECT 0x0000 +#define NV902D_SET_OBJECT_CLASS_ID 15:0 +#define NV902D_SET_OBJECT_ENGINE_ID 20:16 + +#define NV902D_NO_OPERATION 0x0100 +#define NV902D_NO_OPERATION_V 31:0 + +#define NV902D_SET_NOTIFY_A 0x0104 +#define NV902D_SET_NOTIFY_A_ADDRESS_UPPER 24:0 + +#define NV902D_SET_NOTIFY_B 0x0108 +#define NV902D_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NV902D_NOTIFY 0x010c +#define NV902D_NOTIFY_TYPE 31:0 +#define NV902D_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NV902D_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NV902D_WAIT_FOR_IDLE 0x0110 +#define NV902D_WAIT_FOR_IDLE_V 31:0 + +#define NV902D_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NV902D_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NV902D_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NV902D_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NV902D_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NV902D_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NV902D_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NV902D_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NV902D_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NV902D_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NV902D_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NV902D_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NV902D_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NV902D_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NV902D_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV902D_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV902D_SEND_GO_IDLE 0x013c +#define NV902D_SEND_GO_IDLE_V 31:0 + +#define NV902D_PM_TRIGGER 0x0140 +#define NV902D_PM_TRIGGER_V 31:0 + +#define NV902D_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NV902D_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NV902D_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NV902D_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NV902D_SET_MME_SWITCH_STATE 0x01ec +#define NV902D_SET_MME_SWITCH_STATE_VALID 0:0 +#define NV902D_SET_MME_SWITCH_STATE_VALID_FALSE 0x00000000 +#define NV902D_SET_MME_SWITCH_STATE_VALID_TRUE 0x00000001 +#define NV902D_SET_MME_SWITCH_STATE_SAVE_MACRO 11:4 +#define NV902D_SET_MME_SWITCH_STATE_RESTORE_MACRO 19:12 + +#define NV902D_SET_DST_FORMAT 0x0200 +#define NV902D_SET_DST_FORMAT_V 7:0 +#define NV902D_SET_DST_FORMAT_V_A8R8G8B8 0x000000CF +#define NV902D_SET_DST_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NV902D_SET_DST_FORMAT_V_A2R10G10B10 0x000000DF +#define NV902D_SET_DST_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV902D_SET_DST_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NV902D_SET_DST_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV902D_SET_DST_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV902D_SET_DST_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NV902D_SET_DST_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV902D_SET_DST_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NV902D_SET_DST_FORMAT_V_R5G6B5 0x000000E8 +#define NV902D_SET_DST_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV902D_SET_DST_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV902D_SET_DST_FORMAT_V_Y8 0x000000F3 +#define NV902D_SET_DST_FORMAT_V_Y16 0x000000EE +#define NV902D_SET_DST_FORMAT_V_Y32 0x000000FF +#define NV902D_SET_DST_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV902D_SET_DST_FORMAT_V_O1R5G5B5 0x000000FC +#define NV902D_SET_DST_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV902D_SET_DST_FORMAT_V_O8R8G8B8 0x000000FE +#define NV902D_SET_DST_FORMAT_V_Y1_8X8 0x0000001C +#define NV902D_SET_DST_FORMAT_V_RF16 0x000000F2 +#define NV902D_SET_DST_FORMAT_V_RF32 0x000000E5 +#define NV902D_SET_DST_FORMAT_V_RF32_GF32 0x000000CB +#define NV902D_SET_DST_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NV902D_SET_DST_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NV902D_SET_DST_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NV902D_SET_DST_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NV902D_SET_DST_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NV902D_SET_DST_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NV902D_SET_DST_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NV902D_SET_DST_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NV902D_SET_DST_FORMAT_V_RF16_GF16 0x000000DE +#define NV902D_SET_DST_FORMAT_V_R16_G16 0x000000DA +#define NV902D_SET_DST_FORMAT_V_RN16_GN16 0x000000DB +#define NV902D_SET_DST_FORMAT_V_G8R8 0x000000EA +#define NV902D_SET_DST_FORMAT_V_GN8RN8 0x000000EB +#define NV902D_SET_DST_FORMAT_V_RN16 0x000000EF +#define NV902D_SET_DST_FORMAT_V_RN8 0x000000F4 +#define NV902D_SET_DST_FORMAT_V_A8 0x000000F7 + +#define NV902D_SET_DST_MEMORY_LAYOUT 0x0204 +#define NV902D_SET_DST_MEMORY_LAYOUT_V 0:0 +#define NV902D_SET_DST_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000 +#define NV902D_SET_DST_MEMORY_LAYOUT_V_PITCH 0x00000001 + +#define NV902D_SET_DST_BLOCK_SIZE 0x0208 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT 6:4 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH 10:8 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NV902D_SET_DST_DEPTH 0x020c +#define NV902D_SET_DST_DEPTH_V 31:0 + +#define NV902D_SET_DST_LAYER 0x0210 +#define NV902D_SET_DST_LAYER_V 31:0 + +#define NV902D_SET_DST_PITCH 0x0214 +#define NV902D_SET_DST_PITCH_V 31:0 + +#define NV902D_SET_DST_WIDTH 0x0218 +#define NV902D_SET_DST_WIDTH_V 31:0 + +#define NV902D_SET_DST_HEIGHT 0x021c +#define NV902D_SET_DST_HEIGHT_V 31:0 + +#define NV902D_SET_DST_OFFSET_UPPER 0x0220 +#define NV902D_SET_DST_OFFSET_UPPER_V 7:0 + +#define NV902D_SET_DST_OFFSET_LOWER 0x0224 +#define NV902D_SET_DST_OFFSET_LOWER_V 31:0 + +#define NV902D_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x0228 +#define NV902D_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NV902D_SET_SPARE_NOOP06 0x022c +#define NV902D_SET_SPARE_NOOP06_V 31:0 + +#define NV902D_SET_SRC_FORMAT 0x0230 +#define NV902D_SET_SRC_FORMAT_V 7:0 +#define NV902D_SET_SRC_FORMAT_V_A8R8G8B8 0x000000CF +#define NV902D_SET_SRC_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NV902D_SET_SRC_FORMAT_V_A2R10G10B10 0x000000DF +#define NV902D_SET_SRC_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV902D_SET_SRC_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NV902D_SET_SRC_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV902D_SET_SRC_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV902D_SET_SRC_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NV902D_SET_SRC_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV902D_SET_SRC_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NV902D_SET_SRC_FORMAT_V_R5G6B5 0x000000E8 +#define NV902D_SET_SRC_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV902D_SET_SRC_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV902D_SET_SRC_FORMAT_V_Y8 0x000000F3 +#define NV902D_SET_SRC_FORMAT_V_AY8 0x0000001D +#define NV902D_SET_SRC_FORMAT_V_Y16 0x000000EE +#define NV902D_SET_SRC_FORMAT_V_Y32 0x000000FF +#define NV902D_SET_SRC_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV902D_SET_SRC_FORMAT_V_O1R5G5B5 0x000000FC +#define NV902D_SET_SRC_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV902D_SET_SRC_FORMAT_V_O8R8G8B8 0x000000FE +#define NV902D_SET_SRC_FORMAT_V_Y1_8X8 0x0000001C +#define NV902D_SET_SRC_FORMAT_V_RF16 0x000000F2 +#define NV902D_SET_SRC_FORMAT_V_RF32 0x000000E5 +#define NV902D_SET_SRC_FORMAT_V_RF32_GF32 0x000000CB +#define NV902D_SET_SRC_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NV902D_SET_SRC_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NV902D_SET_SRC_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NV902D_SET_SRC_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NV902D_SET_SRC_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NV902D_SET_SRC_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NV902D_SET_SRC_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NV902D_SET_SRC_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NV902D_SET_SRC_FORMAT_V_RF16_GF16 0x000000DE +#define NV902D_SET_SRC_FORMAT_V_R16_G16 0x000000DA +#define NV902D_SET_SRC_FORMAT_V_RN16_GN16 0x000000DB +#define NV902D_SET_SRC_FORMAT_V_G8R8 0x000000EA +#define NV902D_SET_SRC_FORMAT_V_GN8RN8 0x000000EB +#define NV902D_SET_SRC_FORMAT_V_RN16 0x000000EF +#define NV902D_SET_SRC_FORMAT_V_RN8 0x000000F4 +#define NV902D_SET_SRC_FORMAT_V_A8 0x000000F7 + +#define NV902D_SET_SRC_MEMORY_LAYOUT 0x0234 +#define NV902D_SET_SRC_MEMORY_LAYOUT_V 0:0 +#define NV902D_SET_SRC_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000 +#define NV902D_SET_SRC_MEMORY_LAYOUT_V_PITCH 0x00000001 + +#define NV902D_SET_SRC_BLOCK_SIZE 0x0238 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT 6:4 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH 10:8 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NV902D_SET_SRC_DEPTH 0x023c +#define NV902D_SET_SRC_DEPTH_V 31:0 + +#define NV902D_TWOD_INVALIDATE_TEXTURE_DATA_CACHE 0x0240 +#define NV902D_TWOD_INVALIDATE_TEXTURE_DATA_CACHE_V 1:0 +#define NV902D_TWOD_INVALIDATE_TEXTURE_DATA_CACHE_V_L1_ONLY 0x00000000 +#define NV902D_TWOD_INVALIDATE_TEXTURE_DATA_CACHE_V_L2_ONLY 0x00000001 +#define NV902D_TWOD_INVALIDATE_TEXTURE_DATA_CACHE_V_L1_AND_L2 0x00000002 + +#define NV902D_SET_SRC_PITCH 0x0244 +#define NV902D_SET_SRC_PITCH_V 31:0 + +#define NV902D_SET_SRC_WIDTH 0x0248 +#define NV902D_SET_SRC_WIDTH_V 31:0 + +#define NV902D_SET_SRC_HEIGHT 0x024c +#define NV902D_SET_SRC_HEIGHT_V 31:0 + +#define NV902D_SET_SRC_OFFSET_UPPER 0x0250 +#define NV902D_SET_SRC_OFFSET_UPPER_V 7:0 + +#define NV902D_SET_SRC_OFFSET_LOWER 0x0254 +#define NV902D_SET_SRC_OFFSET_LOWER_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION 0x0258 +#define NV902D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V 1:0 +#define NV902D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V_NO_PROMOTION 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V_PROMOTE_TO_2_V 0x00000001 +#define NV902D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V_PROMOTE_TO_2_H 0x00000002 +#define NV902D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V_PROMOTE_TO_4 0x00000003 + +#define NV902D_SET_SPARE_NOOP12 0x025c +#define NV902D_SET_SPARE_NOOP12_V 31:0 + +#define NV902D_SET_NUM_PROCESSING_CLUSTERS 0x0260 +#define NV902D_SET_NUM_PROCESSING_CLUSTERS_V 0:0 +#define NV902D_SET_NUM_PROCESSING_CLUSTERS_V_ALL 0x00000000 +#define NV902D_SET_NUM_PROCESSING_CLUSTERS_V_ONE 0x00000001 + +#define NV902D_SET_RENDER_ENABLE_A 0x0264 +#define NV902D_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV902D_SET_RENDER_ENABLE_B 0x0268 +#define NV902D_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV902D_SET_RENDER_ENABLE_C 0x026c +#define NV902D_SET_RENDER_ENABLE_C_MODE 2:0 +#define NV902D_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV902D_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV902D_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV902D_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV902D_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV902D_SET_SPARE_NOOP08 0x0270 +#define NV902D_SET_SPARE_NOOP08_V 31:0 + +#define NV902D_SET_SPARE_NOOP01 0x0274 +#define NV902D_SET_SPARE_NOOP01_V 31:0 + +#define NV902D_SET_SPARE_NOOP11 0x0278 +#define NV902D_SET_SPARE_NOOP11_V 31:0 + +#define NV902D_SET_SPARE_NOOP07 0x027c +#define NV902D_SET_SPARE_NOOP07_V 31:0 + +#define NV902D_SET_CLIP_X0 0x0280 +#define NV902D_SET_CLIP_X0_V 31:0 + +#define NV902D_SET_CLIP_Y0 0x0284 +#define NV902D_SET_CLIP_Y0_V 31:0 + +#define NV902D_SET_CLIP_WIDTH 0x0288 +#define NV902D_SET_CLIP_WIDTH_V 31:0 + +#define NV902D_SET_CLIP_HEIGHT 0x028c +#define NV902D_SET_CLIP_HEIGHT_V 31:0 + +#define NV902D_SET_CLIP_ENABLE 0x0290 +#define NV902D_SET_CLIP_ENABLE_V 0:0 +#define NV902D_SET_CLIP_ENABLE_V_FALSE 0x00000000 +#define NV902D_SET_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NV902D_SET_COLOR_KEY_FORMAT 0x0294 +#define NV902D_SET_COLOR_KEY_FORMAT_V 2:0 +#define NV902D_SET_COLOR_KEY_FORMAT_V_A16R5G6B5 0x00000000 +#define NV902D_SET_COLOR_KEY_FORMAT_V_A1R5G5B5 0x00000001 +#define NV902D_SET_COLOR_KEY_FORMAT_V_A8R8G8B8 0x00000002 +#define NV902D_SET_COLOR_KEY_FORMAT_V_A2R10G10B10 0x00000003 +#define NV902D_SET_COLOR_KEY_FORMAT_V_Y8 0x00000004 +#define NV902D_SET_COLOR_KEY_FORMAT_V_Y16 0x00000005 +#define NV902D_SET_COLOR_KEY_FORMAT_V_Y32 0x00000006 + +#define NV902D_SET_COLOR_KEY 0x0298 +#define NV902D_SET_COLOR_KEY_V 31:0 + +#define NV902D_SET_COLOR_KEY_ENABLE 0x029c +#define NV902D_SET_COLOR_KEY_ENABLE_V 0:0 +#define NV902D_SET_COLOR_KEY_ENABLE_V_FALSE 0x00000000 +#define NV902D_SET_COLOR_KEY_ENABLE_V_TRUE 0x00000001 + +#define NV902D_SET_ROP 0x02a0 +#define NV902D_SET_ROP_V 7:0 + +#define NV902D_SET_BETA1 0x02a4 +#define NV902D_SET_BETA1_V 31:0 + +#define NV902D_SET_BETA4 0x02a8 +#define NV902D_SET_BETA4_B 7:0 +#define NV902D_SET_BETA4_G 15:8 +#define NV902D_SET_BETA4_R 23:16 +#define NV902D_SET_BETA4_A 31:24 + +#define NV902D_SET_OPERATION 0x02ac +#define NV902D_SET_OPERATION_V 2:0 +#define NV902D_SET_OPERATION_V_SRCCOPY_AND 0x00000000 +#define NV902D_SET_OPERATION_V_ROP_AND 0x00000001 +#define NV902D_SET_OPERATION_V_BLEND_AND 0x00000002 +#define NV902D_SET_OPERATION_V_SRCCOPY 0x00000003 +#define NV902D_SET_OPERATION_V_ROP 0x00000004 +#define NV902D_SET_OPERATION_V_SRCCOPY_PREMULT 0x00000005 +#define NV902D_SET_OPERATION_V_BLEND_PREMULT 0x00000006 + +#define NV902D_SET_PATTERN_OFFSET 0x02b0 +#define NV902D_SET_PATTERN_OFFSET_X 5:0 +#define NV902D_SET_PATTERN_OFFSET_Y 13:8 + +#define NV902D_SET_PATTERN_SELECT 0x02b4 +#define NV902D_SET_PATTERN_SELECT_V 1:0 +#define NV902D_SET_PATTERN_SELECT_V_MONOCHROME_8x8 0x00000000 +#define NV902D_SET_PATTERN_SELECT_V_MONOCHROME_64x1 0x00000001 +#define NV902D_SET_PATTERN_SELECT_V_MONOCHROME_1x64 0x00000002 +#define NV902D_SET_PATTERN_SELECT_V_COLOR 0x00000003 + +#define NV902D_SET_DST_COLOR_RENDER_TO_ZETA_SURFACE 0x02b8 +#define NV902D_SET_DST_COLOR_RENDER_TO_ZETA_SURFACE_V 0:0 +#define NV902D_SET_DST_COLOR_RENDER_TO_ZETA_SURFACE_V_FALSE 0x00000000 +#define NV902D_SET_DST_COLOR_RENDER_TO_ZETA_SURFACE_V_TRUE 0x00000001 + +#define NV902D_SET_SPARE_NOOP04 0x02bc +#define NV902D_SET_SPARE_NOOP04_V 31:0 + +#define NV902D_SET_SPARE_NOOP15 0x02c0 +#define NV902D_SET_SPARE_NOOP15_V 31:0 + +#define NV902D_SET_SPARE_NOOP13 0x02c4 +#define NV902D_SET_SPARE_NOOP13_V 31:0 + +#define NV902D_SET_SPARE_NOOP03 0x02c8 +#define NV902D_SET_SPARE_NOOP03_V 31:0 + +#define NV902D_SET_SPARE_NOOP14 0x02cc +#define NV902D_SET_SPARE_NOOP14_V 31:0 + +#define NV902D_SET_SPARE_NOOP02 0x02d0 +#define NV902D_SET_SPARE_NOOP02_V 31:0 + +#define NV902D_SET_COMPRESSION 0x02d4 +#define NV902D_SET_COMPRESSION_ENABLE 0:0 +#define NV902D_SET_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NV902D_SET_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NV902D_SET_SPARE_NOOP09 0x02d8 +#define NV902D_SET_SPARE_NOOP09_V 31:0 + +#define NV902D_SET_RENDER_ENABLE_OVERRIDE 0x02dc +#define NV902D_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NV902D_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NV902D_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NV902D_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION 0x02e0 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_HORIZONTAL 1:0 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_HORIZONTAL_HW_DECIDES 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_HORIZONTAL_LEFT_TO_RIGHT 0x00000001 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_HORIZONTAL_RIGHT_TO_LEFT 0x00000002 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_VERTICAL 5:4 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_VERTICAL_HW_DECIDES 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_VERTICAL_TOP_TO_BOTTOM 0x00000001 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_VERTICAL_BOTTOM_TO_TOP 0x00000002 + +#define NV902D_SET_SPARE_NOOP10 0x02e4 +#define NV902D_SET_SPARE_NOOP10_V 31:0 + +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT 0x02e8 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V 2:0 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8X8R5G6B5 0x00000000 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A1R5G5B5 0x00000001 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8R8G8B8 0x00000002 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8Y8 0x00000003 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8X8Y16 0x00000004 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_Y32 0x00000005 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_BYTE_EXPAND 0x00000006 + +#define NV902D_SET_MONOCHROME_PATTERN_FORMAT 0x02ec +#define NV902D_SET_MONOCHROME_PATTERN_FORMAT_V 0:0 +#define NV902D_SET_MONOCHROME_PATTERN_FORMAT_V_CGA6_M1 0x00000000 +#define NV902D_SET_MONOCHROME_PATTERN_FORMAT_V_LE_M1 0x00000001 + +#define NV902D_SET_MONOCHROME_PATTERN_COLOR0 0x02f0 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR0_V 31:0 + +#define NV902D_SET_MONOCHROME_PATTERN_COLOR1 0x02f4 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR1_V 31:0 + +#define NV902D_SET_MONOCHROME_PATTERN0 0x02f8 +#define NV902D_SET_MONOCHROME_PATTERN0_V 31:0 + +#define NV902D_SET_MONOCHROME_PATTERN1 0x02fc +#define NV902D_SET_MONOCHROME_PATTERN1_V 31:0 + +#define NV902D_COLOR_PATTERN_X8R8G8B8(i) (0x0300+(i)*4) +#define NV902D_COLOR_PATTERN_X8R8G8B8_B0 7:0 +#define NV902D_COLOR_PATTERN_X8R8G8B8_G0 15:8 +#define NV902D_COLOR_PATTERN_X8R8G8B8_R0 23:16 +#define NV902D_COLOR_PATTERN_X8R8G8B8_IGNORE0 31:24 + +#define NV902D_COLOR_PATTERN_R5G6B5(i) (0x0400+(i)*4) +#define NV902D_COLOR_PATTERN_R5G6B5_B0 4:0 +#define NV902D_COLOR_PATTERN_R5G6B5_G0 10:5 +#define NV902D_COLOR_PATTERN_R5G6B5_R0 15:11 +#define NV902D_COLOR_PATTERN_R5G6B5_B1 20:16 +#define NV902D_COLOR_PATTERN_R5G6B5_G1 26:21 +#define NV902D_COLOR_PATTERN_R5G6B5_R1 31:27 + +#define NV902D_COLOR_PATTERN_X1R5G5B5(i) (0x0480+(i)*4) +#define NV902D_COLOR_PATTERN_X1R5G5B5_B0 4:0 +#define NV902D_COLOR_PATTERN_X1R5G5B5_G0 9:5 +#define NV902D_COLOR_PATTERN_X1R5G5B5_R0 14:10 +#define NV902D_COLOR_PATTERN_X1R5G5B5_IGNORE0 15:15 +#define NV902D_COLOR_PATTERN_X1R5G5B5_B1 20:16 +#define NV902D_COLOR_PATTERN_X1R5G5B5_G1 25:21 +#define NV902D_COLOR_PATTERN_X1R5G5B5_R1 30:26 +#define NV902D_COLOR_PATTERN_X1R5G5B5_IGNORE1 31:31 + +#define NV902D_COLOR_PATTERN_Y8(i) (0x0500+(i)*4) +#define NV902D_COLOR_PATTERN_Y8_Y0 7:0 +#define NV902D_COLOR_PATTERN_Y8_Y1 15:8 +#define NV902D_COLOR_PATTERN_Y8_Y2 23:16 +#define NV902D_COLOR_PATTERN_Y8_Y3 31:24 + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR0 0x0540 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR0_V 31:0 + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR1 0x0544 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR1_V 31:0 + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR2 0x0548 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR2_V 31:0 + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR3 0x054c +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR3_V 31:0 + +#define NV902D_SET_MME_MEM_ADDRESS_A 0x0550 +#define NV902D_SET_MME_MEM_ADDRESS_A_UPPER 24:0 + +#define NV902D_SET_MME_MEM_ADDRESS_B 0x0554 +#define NV902D_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NV902D_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NV902D_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NV902D_MME_DMA_READ 0x055c +#define NV902D_MME_DMA_READ_LENGTH 31:0 + +#define NV902D_MME_DMA_READ_FIFOED 0x0560 +#define NV902D_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NV902D_MME_DMA_WRITE 0x0564 +#define NV902D_MME_DMA_WRITE_LENGTH 31:0 + +#define NV902D_MME_DMA_REDUCTION 0x0568 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NV902D_MME_DMA_SYSMEMBAR 0x056c +#define NV902D_MME_DMA_SYSMEMBAR_V 0:0 + +#define NV902D_MME_DMA_SYNC 0x0570 +#define NV902D_MME_DMA_SYNC_VALUE 31:0 + +#define NV902D_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NV902D_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NV902D_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NV902D_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NV902D_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NV902D_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NV902D_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NV902D_RENDER_SOLID_PRIM_MODE 0x0580 +#define NV902D_RENDER_SOLID_PRIM_MODE_V 2:0 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_POINTS 0x00000000 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_LINES 0x00000001 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_POLYLINE 0x00000002 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_TRIANGLES 0x00000003 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_RECTS 0x00000004 + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT 0x0584 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V 7:0 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_RF32_GF32 0x000000CB +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A8R8G8B8 0x000000CF +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A2R10G10B10 0x000000DF +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_R5G6B5 0x000000E8 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y8 0x000000F3 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y16 0x000000EE +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y32 0x000000FF +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_O1R5G5B5 0x000000FC +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_O8R8G8B8 0x000000FE + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR 0x0588 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_V 31:0 + +#define NV902D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS 0x058c +#define NV902D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS_XMAJ__XINC__YINC 0:0 +#define NV902D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS_XMAJ__XDEC__YINC 4:4 +#define NV902D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS_YMAJ__XINC__YINC 8:8 +#define NV902D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS_YMAJ__XDEC__YINC 12:12 + +#define NV902D_RENDER_SOLID_PRIM_POINT_X_Y 0x05e0 +#define NV902D_RENDER_SOLID_PRIM_POINT_X_Y_X 15:0 +#define NV902D_RENDER_SOLID_PRIM_POINT_X_Y_Y 31:16 + +#define NV902D_RENDER_SOLID_PRIM_POINT_SET_X(j) (0x0600+(j)*8) +#define NV902D_RENDER_SOLID_PRIM_POINT_SET_X_V 31:0 + +#define NV902D_RENDER_SOLID_PRIM_POINT_Y(j) (0x0604+(j)*8) +#define NV902D_RENDER_SOLID_PRIM_POINT_Y_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE 0x0800 +#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE_V 0:0 +#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE_V_COLOR 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE_V_INDEX 0x00000001 + +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT 0x0804 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V 7:0 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A8R8G8B8 0x000000CF +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A2R10G10B10 0x000000DF +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_R5G6B5 0x000000E8 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y8 0x000000F3 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y16 0x000000EE +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y32 0x000000FF +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_O1R5G5B5 0x000000FC +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_O8R8G8B8 0x000000FE + +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT 0x0808 +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V 1:0 +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I1 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I4 0x00000001 +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I8 0x00000002 + +#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT 0x080c +#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V 0:0 +#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V_CGA6_M1 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V_LE_M1 0x00000001 + +#define NV902D_SET_PIXELS_FROM_CPU_WRAP 0x0810 +#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V 1:0 +#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_PIXEL 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_BYTE 0x00000001 +#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_DWORD 0x00000002 + +#define NV902D_SET_PIXELS_FROM_CPU_COLOR0 0x0814 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR0_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_COLOR1 0x0818 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR1_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY 0x081c +#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V 0:0 +#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V_TRANSPARENT 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V_OPAQUE 0x00000001 + +#define NV902D_SET_PIXELS_FROM_CPU_SRC_WIDTH 0x0838 +#define NV902D_SET_PIXELS_FROM_CPU_SRC_WIDTH_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_SRC_HEIGHT 0x083c +#define NV902D_SET_PIXELS_FROM_CPU_SRC_HEIGHT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_FRAC 0x0840 +#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_INT 0x0844 +#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_FRAC 0x0848 +#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_INT 0x084c +#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_FRAC 0x0850 +#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_INT 0x0854 +#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_FRAC 0x0858 +#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_INT 0x085c +#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_INT_V 31:0 + +#define NV902D_PIXELS_FROM_CPU_DATA 0x0860 +#define NV902D_PIXELS_FROM_CPU_DATA_V 31:0 + +#define NV902D_SET_BIG_ENDIAN_CONTROL 0x0870 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X32_SWAP_1 0:0 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X32_SWAP_4 1:1 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X32_SWAP_8 2:2 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X32_SWAP_16 3:3 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X16_SWAP_1 4:4 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X16_SWAP_4 5:5 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X16_SWAP_8 6:6 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X16_SWAP_16 7:7 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X8_SWAP_1 8:8 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X8_SWAP_4 9:9 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X8_SWAP_8 10:10 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X8_SWAP_16 11:11 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_CGA6_SWAP_1 12:12 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_CGA6_SWAP_4 13:13 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_CGA6_SWAP_8 14:14 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_CGA6_SWAP_16 15:15 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_LE_SWAP_1 16:16 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_LE_SWAP_4 17:17 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_LE_SWAP_8 18:18 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_LE_SWAP_16 19:19 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I4_SWAP_1 20:20 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I4_SWAP_4 21:21 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I4_SWAP_8 22:22 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I4_SWAP_16 23:23 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I8_SWAP_1 24:24 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I8_SWAP_4 25:25 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I8_SWAP_8 26:26 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I8_SWAP_16 27:27 +#define NV902D_SET_BIG_ENDIAN_CONTROL_OVERRIDE 28:28 + +#define NV902D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE 0x0880 +#define NV902D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE_V 2:0 +#define NV902D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE_V_AUTO 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE_V_SHAPE_8X8 0x00000001 +#define NV902D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE_V_SHAPE_16X4 0x00000002 + +#define NV902D_SET_PIXELS_FROM_MEMORY_CORRAL_SIZE 0x0884 +#define NV902D_SET_PIXELS_FROM_MEMORY_CORRAL_SIZE_V 9:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP 0x0888 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V 0:0 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V_FALSE 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V_TRUE 0x00000001 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE 0x088c +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_ORIGIN 0:0 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_ORIGIN_CENTER 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_ORIGIN_CORNER 0x00000001 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_FILTER 4:4 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_FILTER_POINT 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_FILTER_BILINEAR 0x00000001 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_X0 0x08b0 +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_X0_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_Y0 0x08b4 +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_Y0_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_WIDTH 0x08b8 +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_WIDTH_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_HEIGHT 0x08bc +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_HEIGHT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_FRAC 0x08c0 +#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_INT 0x08c4 +#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_FRAC 0x08c8 +#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_INT 0x08cc +#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC 0x08d0 +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_INT 0x08d4 +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC 0x08d8 +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC_V 31:0 + +#define NV902D_PIXELS_FROM_MEMORY_SRC_Y0_INT 0x08dc +#define NV902D_PIXELS_FROM_MEMORY_SRC_Y0_INT_V 31:0 + +#define NV902D_SET_FALCON00 0x08e0 +#define NV902D_SET_FALCON00_V 31:0 + +#define NV902D_SET_FALCON01 0x08e4 +#define NV902D_SET_FALCON01_V 31:0 + +#define NV902D_SET_FALCON02 0x08e8 +#define NV902D_SET_FALCON02_V 31:0 + +#define NV902D_SET_FALCON03 0x08ec +#define NV902D_SET_FALCON03_V 31:0 + +#define NV902D_SET_FALCON04 0x08f0 +#define NV902D_SET_FALCON04_V 31:0 + +#define NV902D_SET_FALCON05 0x08f4 +#define NV902D_SET_FALCON05_V 31:0 + +#define NV902D_SET_FALCON06 0x08f8 +#define NV902D_SET_FALCON06_V 31:0 + +#define NV902D_SET_FALCON07 0x08fc +#define NV902D_SET_FALCON07_V 31:0 + +#define NV902D_SET_FALCON08 0x0900 +#define NV902D_SET_FALCON08_V 31:0 + +#define NV902D_SET_FALCON09 0x0904 +#define NV902D_SET_FALCON09_V 31:0 + +#define NV902D_SET_FALCON10 0x0908 +#define NV902D_SET_FALCON10_V 31:0 + +#define NV902D_SET_FALCON11 0x090c +#define NV902D_SET_FALCON11_V 31:0 + +#define NV902D_SET_FALCON12 0x0910 +#define NV902D_SET_FALCON12_V 31:0 + +#define NV902D_SET_FALCON13 0x0914 +#define NV902D_SET_FALCON13_V 31:0 + +#define NV902D_SET_FALCON14 0x0918 +#define NV902D_SET_FALCON14_V 31:0 + +#define NV902D_SET_FALCON15 0x091c +#define NV902D_SET_FALCON15_V 31:0 + +#define NV902D_SET_FALCON16 0x0920 +#define NV902D_SET_FALCON16_V 31:0 + +#define NV902D_SET_FALCON17 0x0924 +#define NV902D_SET_FALCON17_V 31:0 + +#define NV902D_SET_FALCON18 0x0928 +#define NV902D_SET_FALCON18_V 31:0 + +#define NV902D_SET_FALCON19 0x092c +#define NV902D_SET_FALCON19_V 31:0 + +#define NV902D_SET_FALCON20 0x0930 +#define NV902D_SET_FALCON20_V 31:0 + +#define NV902D_SET_FALCON21 0x0934 +#define NV902D_SET_FALCON21_V 31:0 + +#define NV902D_SET_FALCON22 0x0938 +#define NV902D_SET_FALCON22_V 31:0 + +#define NV902D_SET_FALCON23 0x093c +#define NV902D_SET_FALCON23_V 31:0 + +#define NV902D_SET_FALCON24 0x0940 +#define NV902D_SET_FALCON24_V 31:0 + +#define NV902D_SET_FALCON25 0x0944 +#define NV902D_SET_FALCON25_V 31:0 + +#define NV902D_SET_FALCON26 0x0948 +#define NV902D_SET_FALCON26_V 31:0 + +#define NV902D_SET_FALCON27 0x094c +#define NV902D_SET_FALCON27_V 31:0 + +#define NV902D_SET_FALCON28 0x0950 +#define NV902D_SET_FALCON28_V 31:0 + +#define NV902D_SET_FALCON29 0x0954 +#define NV902D_SET_FALCON29_V 31:0 + +#define NV902D_SET_FALCON30 0x0958 +#define NV902D_SET_FALCON30_V 31:0 + +#define NV902D_SET_FALCON31 0x095c +#define NV902D_SET_FALCON31_V 31:0 + +#define NV902D_MME_DMA_WRITE_METHOD_BARRIER 0x0dec +#define NV902D_MME_DMA_WRITE_METHOD_BARRIER_V 0:0 + +#define NV902D_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NV902D_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NV902D_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NV902D_CALL_MME_MACRO_V 31:0 + +#define NV902D_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NV902D_CALL_MME_DATA_V 31:0 + +#endif /* _cl_fermi_twod_a_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl9067.h b/userspace/sdks/nv570/inc/class/cl9067.h new file mode 100644 index 0000000..5355f18 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl9067.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _cl9067_h_ +#define _cl9067_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define FERMI_CONTEXT_SHARE_A (0x00009067) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl9067_h + diff --git a/userspace/sdks/nv570/inc/class/cl906f.h b/userspace/sdks/nv570/inc/class/cl906f.h new file mode 100644 index 0000000..b20d8ff --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl906f.h @@ -0,0 +1,242 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl906f_h_ +#define _cl906f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class GF100_CHANNEL_GPFIFO */ +/* + * Documentation for GF100_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + */ +#define GF100_CHANNEL_GPFIFO (0x0000906F) + +/* pio method data structure */ +typedef volatile struct _cl906f_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv906fTypedef, GF100ChannelGPFifo; +#define NV906F_TYPEDEF GF100ChannelGPFifo +/* dma flow control data structure */ +typedef volatile struct _cl906f_tag1 { + NvU32 Ignored00[0x010]; /* 0000-0043*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 SetReferenceThreshold; /* set reference value threshold 0050-0053*/ + NvU32 Ignored01[0x001]; /* 0054-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x3dc]; +} Nv906fControl, GF100ControlGPFifo; +/* fields and values */ +#define NV906F_NUMBER_OF_SUBCHANNELS (8) +#define NV906F_SET_OBJECT (0x00000000) +#define NV906F_SET_OBJECT_NVCLASS 15:0 +#define NV906F_SET_OBJECT_ENGINE 20:16 +#define NV906F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NV906F_ILLEGAL (0x00000004) +#define NV906F_ILLEGAL_HANDLE 31:0 +#define NV906F_NOP (0x00000008) +#define NV906F_NOP_HANDLE 31:0 +#define NV906F_SEMAPHOREA (0x00000010) +#define NV906F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NV906F_SEMAPHOREB (0x00000014) +#define NV906F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NV906F_SEMAPHOREC (0x00000018) +#define NV906F_SEMAPHOREC_PAYLOAD 31:0 +#define NV906F_SEMAPHORED (0x0000001C) +#define NV906F_SEMAPHORED_OPERATION 3:0 +#define NV906F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NV906F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NV906F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NV906F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NV906F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NV906F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NV906F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NV906F_SEMAPHORED_RELEASE_WFI 20:20 +#define NV906F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NV906F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NV906F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NV906F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NV906F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NV906F_NON_STALL_INTERRUPT (0x00000020) +#define NV906F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NV906F_FB_FLUSH (0x00000024) +#define NV906F_FB_FLUSH_HANDLE 31:0 +#define NV906F_MEM_OP_A (0x00000028) +#define NV906F_MEM_OP_A_OPERAND_LOW 31:2 +#define NV906F_MEM_OP_A_TLB_INVALIDATE_ADDR 29:2 +#define NV906F_MEM_OP_A_TLB_INVALIDATE_TARGET 31:30 +#define NV906F_MEM_OP_A_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000 +#define NV906F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002 +#define NV906F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 +#define NV906F_MEM_OP_B (0x0000002c) +#define NV906F_MEM_OP_B_OPERAND_HIGH 7:0 +#define NV906F_MEM_OP_B_OPERATION 31:27 +#define NV906F_MEM_OP_B_OPERATION_SYSMEMBAR_FLUSH 0x00000005 +#define NV906F_MEM_OP_B_OPERATION_SOFT_FLUSH 0x00000006 +#define NV906F_MEM_OP_B_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NV906F_MEM_OP_B_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NV906F_MEM_OP_B_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +#define NV906F_MEM_OP_B_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NV906F_MEM_OP_B_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB 0:0 +#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ALL 0x00000001 +#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC 1:1 +#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NV906F_SET_REFERENCE (0x00000050) +#define NV906F_SET_REFERENCE_COUNT 31:0 +#define NV906F_CRC_CHECK (0x0000007c) +#define NV906F_CRC_CHECK_VALUE 31:0 +#define NV906F_YIELD (0x00000080) +#define NV906F_YIELD_OP 1:0 +#define NV906F_YIELD_OP_NOP 0x00000000 + +/* GPFIFO entry format */ +#define NV906F_GP_ENTRY__SIZE 8 +#define NV906F_GP_ENTRY0_FETCH 0:0 +#define NV906F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NV906F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NV906F_GP_ENTRY0_NO_CONTEXT_SWITCH 1:1 +#define NV906F_GP_ENTRY0_NO_CONTEXT_SWITCH_FALSE 0x00000000 +#define NV906F_GP_ENTRY0_NO_CONTEXT_SWITCH_TRUE 0x00000001 +#define NV906F_GP_ENTRY0_GET 31:2 +#define NV906F_GP_ENTRY0_OPERAND 31:0 +#define NV906F_GP_ENTRY1_GET_HI 7:0 +#define NV906F_GP_ENTRY1_PRIV 8:8 +#define NV906F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NV906F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NV906F_GP_ENTRY1_LEVEL 9:9 +#define NV906F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NV906F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NV906F_GP_ENTRY1_LENGTH 30:10 +#define NV906F_GP_ENTRY1_SYNC 31:31 +#define NV906F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NV906F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NV906F_GP_ENTRY1_OPCODE 7:0 +#define NV906F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NV906F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NV906F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NV906F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NV906F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NV906F_DMA_METHOD_ADDRESS 11:0 +#define NV906F_DMA_SUBDEVICE_MASK 15:4 +#define NV906F_DMA_METHOD_SUBCHANNEL 15:13 +#define NV906F_DMA_TERT_OP 17:16 +#define NV906F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NV906F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NV906F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NV906F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NV906F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NV906F_DMA_METHOD_COUNT_OLD 28:18 +#define NV906F_DMA_METHOD_COUNT 28:16 +#define NV906F_DMA_IMMD_DATA 28:16 +#define NV906F_DMA_SEC_OP 31:29 +#define NV906F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NV906F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NV906F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NV906F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NV906F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NV906F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NV906F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NV906F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NV906F_DMA_INCR_ADDRESS 11:0 +#define NV906F_DMA_INCR_SUBCHANNEL 15:13 +#define NV906F_DMA_INCR_COUNT 28:16 +#define NV906F_DMA_INCR_OPCODE 31:29 +#define NV906F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NV906F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NV906F_DMA_NONINCR_ADDRESS 11:0 +#define NV906F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NV906F_DMA_NONINCR_COUNT 28:16 +#define NV906F_DMA_NONINCR_OPCODE 31:29 +#define NV906F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NV906F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NV906F_DMA_ONEINCR_ADDRESS 11:0 +#define NV906F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NV906F_DMA_ONEINCR_COUNT 28:16 +#define NV906F_DMA_ONEINCR_OPCODE 31:29 +#define NV906F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NV906F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NV906F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NV906F_DMA_IMMD_ADDRESS 11:0 +#define NV906F_DMA_IMMD_SUBCHANNEL 15:13 +#define NV906F_DMA_IMMD_DATA 28:16 +#define NV906F_DMA_IMMD_OPCODE 31:29 +#define NV906F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NV906F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NV906F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NV906F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NV906F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NV906F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NV906F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NV906F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NV906F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NV906F_DMA_ENDSEG_OPCODE 31:29 +#define NV906F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NV906F_DMA_ADDRESS 12:2 +#define NV906F_DMA_SUBCH 15:13 +#define NV906F_DMA_OPCODE3 17:16 +#define NV906F_DMA_OPCODE3_NONE (0x00000000) +#define NV906F_DMA_COUNT 28:18 +#define NV906F_DMA_OPCODE 31:29 +#define NV906F_DMA_OPCODE_METHOD (0x00000000) +#define NV906F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NV906F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl906f_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl906fsw.h b/userspace/sdks/nv570/inc/class/cl906fsw.h new file mode 100644 index 0000000..465a91a --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl906fsw.h @@ -0,0 +1,42 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl906f_sw_h_ +#define _cl906f_sw_h_ + +/* NvNotification[] elements */ +#define NV906F_NOTIFIERS_RC (0) +#define NV906F_NOTIFIERS_REFCNT (1) +#define NV906F_NOTIFIERS_NONSTALL (2) +#define NV906F_NOTIFIERS_EVENTBUFFER (3) +#define NV906F_NOTIFIERS_IDLECHANNEL (4) +#define NV906F_NOTIFIERS_ENDCTX (5) +#define NV906F_NOTIFIERS_SW (6) +#define NV906F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NV906F_NOTIFIERS_MAXCOUNT (8) + +/* NvNotification[] fields and values */ +#define NV906f_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NV906f_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _cl906f_sw_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl9072.h b/userspace/sdks/nv570/inc/class/cl9072.h new file mode 100644 index 0000000..0d13a8a --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl9072.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9072.finn +// + +#include "cl9072_notification.h" + +#define GF100_DISP_SW (0x9072U) /* finn: Evaluated from "NV9072_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV9072_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9072U) + +typedef struct NV9072_ALLOCATION_PARAMETERS { + NvU32 logicalHeadId; + /* + * 0 implies use Head argument only (i.e. whatever is currently setup on this head) + */ + NvU32 displayMask; + NvU32 caps; +} NV9072_ALLOCATION_PARAMETERS; diff --git a/userspace/sdks/nv570/inc/class/cl9072_notification.h b/userspace/sdks/nv570/inc/class/cl9072_notification.h new file mode 100644 index 0000000..21b48f8 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl9072_notification.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl9072_notification_h_ +#define _cl9072_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV9072_NOTIFIERS_NOTIFY_ON_VBLANK (9) +#define NV9072_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl9072_notification_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl9074.h b/userspace/sdks/nv570/inc/class/cl9074.h new file mode 100644 index 0000000..60436ba --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl9074.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl9074_h_ +#define _cl9074_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define GF100_TIMED_SEMAPHORE_SW (0x00009074) + +/* NvNotification[] fields and values */ +#define NV9074_NOTIFICATION_STATUS_PENDING (0x8000) +#define NV9074_NOTIFICATION_STATUS_DONE_FLUSHED (0x0001) +#define NV9074_NOTIFICATION_STATUS_DONE (0x0000) + +#define NV9074_SET_NOTIFIER_HI_V 7:0 + +#define NV9074_SET_SEMAPHORE_HI_V 7:0 + +#define NV9074_SCHEDULE_SEMAPHORE_RELEASE_NOTIFY 1:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl9074_h_ */ + diff --git a/userspace/sdks/nv570/inc/class/cl9096.h b/userspace/sdks/nv570/inc/class/cl9096.h new file mode 100644 index 0000000..559216d --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl9096.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl9096_h_ +#define _cl9096_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define GF100_ZBC_CLEAR (0x00009096) +#define NV9096_TYPEDEF GF100ZBCClear + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl9096_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl9097.h b/userspace/sdks/nv570/inc/class/cl9097.h new file mode 100644 index 0000000..8bc7792 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl9097.h @@ -0,0 +1,3815 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_fermi_a_h_ +#define _cl_fermi_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl fermi_a */ + +#include "nvtypes.h" + +#define FERMI_A 0x9097 + +#define NV9097_SET_OBJECT 0x0000 +#define NV9097_SET_OBJECT_CLASS_ID 15:0 +#define NV9097_SET_OBJECT_ENGINE_ID 20:16 + +#define NV9097_NO_OPERATION 0x0100 +#define NV9097_NO_OPERATION_V 31:0 + +#define NV9097_SET_NOTIFY_A 0x0104 +#define NV9097_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NV9097_SET_NOTIFY_B 0x0108 +#define NV9097_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NV9097_NOTIFY 0x010c +#define NV9097_NOTIFY_TYPE 31:0 +#define NV9097_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NV9097_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NV9097_WAIT_FOR_IDLE 0x0110 +#define NV9097_WAIT_FOR_IDLE_V 31:0 + +#define NV9097_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NV9097_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NV9097_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NV9097_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NV9097_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NV9097_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NV9097_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NV9097_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NV9097_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NV9097_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NV9097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NV9097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NV9097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NV9097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NV9097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NV9097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NV9097_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NV9097_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NV9097_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV9097_SEND_GO_IDLE 0x013c +#define NV9097_SEND_GO_IDLE_V 31:0 + +#define NV9097_PM_TRIGGER 0x0140 +#define NV9097_PM_TRIGGER_V 31:0 + +#define NV9097_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NV9097_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NV9097_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NV9097_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NV9097_RUN_DS_NOW 0x0200 +#define NV9097_RUN_DS_NOW_V 31:0 + +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NV9097_SET_RASTER_PIPE_SYNC_CONTROL 0x0208 +#define NV9097_SET_RASTER_PIPE_SYNC_CONTROL_PRIM_AREA_THRESHOLD 21:0 +#define NV9097_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE 24:24 +#define NV9097_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE_FALSE 0x00000000 +#define NV9097_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NV9097_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NV9097_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_API_MANDATED_EARLY_Z 0x0210 +#define NV9097_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NV9097_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NV9097_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_GS_DM_FIFO 0x0214 +#define NV9097_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NV9097_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NV9097_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NV9097_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NV9097_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NV9097_INVALIDATE_SHADER_CACHES 0x021c +#define NV9097_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NV9097_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NV9097_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NV9097_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NV9097_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NV9097_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NV9097_INVALIDATE_SHADER_CACHES_UNIFORM 8:8 +#define NV9097_INVALIDATE_SHADER_CACHES_UNIFORM_FALSE 0x00000000 +#define NV9097_INVALIDATE_SHADER_CACHES_UNIFORM_TRUE 0x00000001 +#define NV9097_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NV9097_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NV9097_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NV9097_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NV9097_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NV9097_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NV9097_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NV9097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NV9097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NV9097_SET_VAB_VERTEX3F(i) (0x0220+(i)*4) +#define NV9097_SET_VAB_VERTEX3F_V 31:0 + +#define NV9097_SET_VAB_VERTEX4F(i) (0x0230+(i)*4) +#define NV9097_SET_VAB_VERTEX4F_V 31:0 + +#define NV9097_SET_VAB_NORMAL3F(i) (0x0240+(i)*4) +#define NV9097_SET_VAB_NORMAL3F_V 31:0 + +#define NV9097_SET_VAB_COLOR3F(i) (0x0250+(i)*4) +#define NV9097_SET_VAB_COLOR3F_V 31:0 + +#define NV9097_SET_VAB_COLOR4F(i) (0x0260+(i)*4) +#define NV9097_SET_VAB_COLOR4F_V 31:0 + +#define NV9097_SET_VAB_COLOR4UB(i) (0x0270+(i)*4) +#define NV9097_SET_VAB_COLOR4UB_V 31:0 + +#define NV9097_SET_VAB_TEX_COORD1F(i) (0x0280+(i)*4) +#define NV9097_SET_VAB_TEX_COORD1F_V 31:0 + +#define NV9097_SET_VAB_TEX_COORD2F(i) (0x0290+(i)*4) +#define NV9097_SET_VAB_TEX_COORD2F_V 31:0 + +#define NV9097_SET_VAB_TEX_COORD3F(i) (0x02a0+(i)*4) +#define NV9097_SET_VAB_TEX_COORD3F_V 31:0 + +#define NV9097_SET_VAB_TEX_COORD4F(i) (0x02b0+(i)*4) +#define NV9097_SET_VAB_TEX_COORD4F_V 31:0 + +#define NV9097_SET_GA_TO_VA_MAPPING_MODE 0x02c4 +#define NV9097_SET_GA_TO_VA_MAPPING_MODE_V 0:0 +#define NV9097_SET_GA_TO_VA_MAPPING_MODE_V_DISABLE 0x00000000 +#define NV9097_SET_GA_TO_VA_MAPPING_MODE_V_ENABLE 0x00000001 + +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY 0x02c8 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_VIRTUAL_ADDRESS_UPPER 7:0 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_GENERIC_ADDRESS_UPPER 23:16 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE 30:30 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_FALSE 0x00000000 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_TRUE 0x00000001 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE 31:31 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_FALSE 0x00000000 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_TASK_CIRCULAR_BUFFER_THROTTLE 0x02cc +#define NV9097_SET_TASK_CIRCULAR_BUFFER_THROTTLE_TASK_COUNT 21:0 + +#define NV9097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NV9097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NV9097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NV9097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NV9097_SET_RASTER_BOUNDING_BOX 0x02ec +#define NV9097_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NV9097_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NV9097_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NV9097_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NV9097_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NV9097_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NV9097_DRAW_ZERO_INDEX 0x0304 +#define NV9097_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NV9097_SET_L1_CONFIGURATION 0x0308 +#define NV9097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NV9097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NV9097_SET_RENDER_ENABLE_CONTROL 0x030c +#define NV9097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NV9097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NV9097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NV9097_X_X_X_SET_CT_ENABLE 0x0310 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET0 0:0 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET0_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET0_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET1 1:1 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET1_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET1_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET2 2:2 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET2_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET2_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET3 3:3 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET3_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET3_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET4 4:4 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET4_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET4_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET5 5:5 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET5_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET5_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET6 6:6 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET6_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET6_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET7 7:7 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET7_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET7_TRUE 0x00000001 + +#define NV9097_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NV9097_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NV9097_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SNAP_GRID_LINE 0x0318 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NV9097_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NV9097_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NV9097_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NV9097_SET_SNAP_GRID_NON_LINE 0x031c +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NV9097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NV9097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NV9097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NV9097_SET_TESSELLATION_PARAMETERS 0x0320 +#define NV9097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NV9097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NV9097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NV9097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NV9097_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NV9097_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NV9097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NV9097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NV9097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NV9097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NV9097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NV9097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NV9097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NV9097_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NV9097_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NV9097_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NV9097_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NV9097_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NV9097_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NV9097_SET_TESSELLATION_LOD_V1 0x0330 +#define NV9097_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NV9097_SET_TG_LOD_INTERIOR_U 0x0334 +#define NV9097_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NV9097_SET_TG_LOD_INTERIOR_V 0x0338 +#define NV9097_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NV9097_RESERVED_TG07 0x033c +#define NV9097_RESERVED_TG07_V 0:0 + +#define NV9097_RESERVED_TG08 0x0340 +#define NV9097_RESERVED_TG08_V 0:0 + +#define NV9097_RESERVED_TG09 0x0344 +#define NV9097_RESERVED_TG09_V 0:0 + +#define NV9097_RESERVED_TG10 0x0348 +#define NV9097_RESERVED_TG10_V 0:0 + +#define NV9097_RESERVED_TG11 0x034c +#define NV9097_RESERVED_TG11_V 0:0 + +#define NV9097_RESERVED_TG12 0x0350 +#define NV9097_RESERVED_TG12_V 0:0 + +#define NV9097_RESERVED_TG13 0x0354 +#define NV9097_RESERVED_TG13_V 0:0 + +#define NV9097_RESERVED_TG14 0x0358 +#define NV9097_RESERVED_TG14_V 0:0 + +#define NV9097_RESERVED_TG15 0x035c +#define NV9097_RESERVED_TG15_V 0:0 + +#define NV9097_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NV9097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NV9097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NV9097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NV9097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NV9097_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NV9097_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NV9097_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NV9097_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NV9097_SET_RASTER_ENABLE 0x037c +#define NV9097_SET_RASTER_ENABLE_V 0:0 +#define NV9097_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NV9097_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NV9097_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NV9097_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NV9097_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NV9097_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NV9097_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NV9097_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NV9097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NV9097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NV9097_SET_VAB_DATA_TYPELESS(i) (0x0400+(i)*4) +#define NV9097_SET_VAB_DATA_TYPELESS_V 31:0 + +#define NV9097_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NV9097_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NV9097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NV9097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NV9097_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NV9097_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NV9097_SET_RASTER_INPUT 0x0740 +#define NV9097_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NV9097_SET_STREAM_OUTPUT 0x0744 +#define NV9097_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NV9097_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NV9097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NV9097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_ALPHA_FRACTION 0x074c +#define NV9097_SET_ALPHA_FRACTION_V 7:0 + +#define NV9097_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NV9097_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NV9097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NV9097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NV9097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 + +#define NV9097_SET_MAX_TI_WARPS_PER_BATCH 0x075c +#define NV9097_SET_MAX_TI_WARPS_PER_BATCH_V 5:0 + +#define NV9097_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NV9097_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NV9097_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NV9097_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NV9097_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NV9097_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NV9097_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NV9097_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NV9097_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NV9097_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NV9097_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NV9097_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NV9097_SET_VAB_VERTEX2F(i) (0x07b0+(i)*4) +#define NV9097_SET_VAB_VERTEX2F_V 31:0 + +#define NV9097_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NV9097_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NV9097_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NV9097_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NV9097_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NV9097_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NV9097_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NV9097_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NV9097_SET_CULL_BEFORE_FETCH 0x07dc +#define NV9097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NV9097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NV9097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NV9097_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NV9097_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NV9097_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NV9097_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NV9097_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NV9097_SET_ZCULL_STORAGE_A 0x07e8 +#define NV9097_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NV9097_SET_ZCULL_STORAGE_B 0x07ec +#define NV9097_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NV9097_SET_ZCULL_STORAGE_C 0x07f0 +#define NV9097_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NV9097_SET_ZCULL_STORAGE_D 0x07f4 +#define NV9097_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NV9097_SET_ZT_READ_ONLY 0x07f8 +#define NV9097_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NV9097_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NV9097_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NV9097_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NV9097_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NV9097_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NV9097_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NV9097_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NV9097_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NV9097_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NV9097_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NV9097_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NV9097_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NV9097_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NV9097_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NV9097_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NV9097_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NV9097_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NV9097_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV9097_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NV9097_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV9097_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 + +#define NV9097_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NV9097_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NV9097_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NV9097_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NV9097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NV9097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NV9097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NV9097_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NV9097_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NV9097_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NV9097_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NV9097_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NV9097_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NV9097_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NV9097_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NV9097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NV9097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NV9097_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NV9097_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NV9097_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NV9097_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NV9097_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NV9097_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NV9097_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NV9097_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NV9097_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NV9097_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NV9097_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NV9097_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NV9097_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NV9097_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NV9097_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NV9097_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NV9097_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NV9097_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NV9097_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NV9097_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NV9097_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NV9097_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NV9097_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NV9097_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NV9097_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NV9097_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NV9097_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NV9097_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NV9097_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NV9097_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NV9097_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NV9097_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NV9097_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NV9097_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NV9097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NV9097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NV9097_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NV9097_SET_STATISTICS_COUNTER 0x0d68 +#define NV9097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NV9097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NV9097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NV9097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NV9097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NV9097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NV9097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NV9097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NV9097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NV9097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NV9097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NV9097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NV9097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NV9097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NV9097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NV9097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NV9097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NV9097_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NV9097_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NV9097_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NV9097_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NV9097_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NV9097_SET_VERTEX_ARRAY_START 0x0d74 +#define NV9097_SET_VERTEX_ARRAY_START_V 31:0 + +#define NV9097_DRAW_VERTEX_ARRAY 0x0d78 +#define NV9097_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NV9097_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NV9097_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NV9097_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NV9097_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NV9097_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NV9097_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NV9097_SET_Z_CLEAR_VALUE 0x0d90 +#define NV9097_SET_Z_CLEAR_VALUE_V 31:0 + +#define NV9097_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NV9097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NV9097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NV9097_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NV9097_SET_FRONT_POLYGON_MODE 0x0dac +#define NV9097_SET_FRONT_POLYGON_MODE_V 31:0 +#define NV9097_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NV9097_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NV9097_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NV9097_SET_BACK_POLYGON_MODE 0x0db0 +#define NV9097_SET_BACK_POLYGON_MODE_V 31:0 +#define NV9097_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NV9097_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NV9097_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NV9097_SET_POLY_SMOOTH 0x0db4 +#define NV9097_SET_POLY_SMOOTH_ENABLE 0:0 +#define NV9097_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NV9097_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_ZT_MARK 0x0db8 +#define NV9097_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NV9097_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NV9097_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NV9097_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NV9097_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NV9097_SET_POLY_OFFSET_POINT 0x0dc0 +#define NV9097_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NV9097_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_POLY_OFFSET_LINE 0x0dc4 +#define NV9097_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NV9097_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_POLY_OFFSET_FILL 0x0dc8 +#define NV9097_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NV9097_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NV9097_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_PATCH 0x0dcc +#define NV9097_SET_PATCH_SIZE 7:0 + +#define NV9097_SET_ZCULL_CRITERION 0x0dd8 +#define NV9097_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NV9097_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NV9097_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NV9097_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NV9097_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NV9097_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NV9097_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NV9097_SET_ZCULL_CRITERION_SREF 23:16 +#define NV9097_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NV9097_X_X_X_SET_DA_ATTRIBUTE_CACHE_LINE 0x0ddc +#define NV9097_X_X_X_SET_DA_ATTRIBUTE_CACHE_LINE_V 1:0 +#define NV9097_X_X_X_SET_DA_ATTRIBUTE_CACHE_LINE_V_SIZE128 0x00000000 +#define NV9097_X_X_X_SET_DA_ATTRIBUTE_CACHE_LINE_V_SIZE64 0x00000001 +#define NV9097_X_X_X_SET_DA_ATTRIBUTE_CACHE_LINE_V_SIZE32 0x00000002 + +#define NV9097_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NV9097_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NV9097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NV9097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NV9097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE 0x0dec +#define NV9097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE 0:0 +#define NV9097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE_TRUE 0x00000001 + +#define NV9097_X_X_X_SET_REDUCE_COLOR 0x0df4 +#define NV9097_X_X_X_SET_REDUCE_COLOR_U8_THRESHOLD 7:0 +#define NV9097_X_X_X_SET_REDUCE_COLOR_FP16_THRESHOLD 23:8 + +#define NV9097_SET_WINDOW_OFFSET_X 0x0df8 +#define NV9097_SET_WINDOW_OFFSET_X_V 16:0 + +#define NV9097_SET_WINDOW_OFFSET_Y 0x0dfc +#define NV9097_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NV9097_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NV9097_SET_SCISSOR_ENABLE_V 0:0 +#define NV9097_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NV9097_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NV9097_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NV9097_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NV9097_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NV9097_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NV9097_SET_VAB_NORMAL3S(i) (0x0f00+(i)*4) +#define NV9097_SET_VAB_NORMAL3S_V 31:0 + +#define NV9097_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NV9097_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NV9097_SET_BACK_STENCIL_MASK 0x0f58 +#define NV9097_SET_BACK_STENCIL_MASK_V 7:0 + +#define NV9097_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NV9097_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NV9097_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NV9097_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NV9097_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NV9097_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NV9097_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NV9097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NV9097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NV9097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NV9097_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NV9097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NV9097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NV9097_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NV9097_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NV9097_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NV9097_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NV9097_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NV9097_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NV9097_SET_CT_MRT_ENABLE 0x0fac +#define NV9097_SET_CT_MRT_ENABLE_V 0:0 +#define NV9097_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NV9097_SET_NONMULTISAMPLED_Z_V 0:0 +#define NV9097_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NV9097_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NV9097_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NV9097_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NV9097_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NV9097_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NV9097_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NV9097_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NV9097_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NV9097_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NV9097_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NV9097_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NV9097_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_BLEND_OPT_CONTROL 0x0fdc +#define NV9097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NV9097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NV9097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NV9097_SET_ZT_A 0x0fe0 +#define NV9097_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_ZT_B 0x0fe4 +#define NV9097_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_ZT_FORMAT 0x0fe8 +#define NV9097_SET_ZT_FORMAT_V 4:0 +#define NV9097_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NV9097_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NV9097_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NV9097_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NV9097_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NV9097_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NV9097_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NV9097_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NV9097_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NV9097_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NV9097_SET_ZT_BLOCK_SIZE 0x0fec +#define NV9097_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NV9097_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV9097_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NV9097_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NV9097_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NV9097_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NV9097_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NV9097_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NV9097_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NV9097_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NV9097_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NV9097_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NV9097_SET_FORCE_ONE_TEXTURE_UNIT 0x1004 +#define NV9097_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE 0:0 +#define NV9097_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NV9097_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NV9097_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NV9097_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NV9097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NV9097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NV9097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NV9097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NV9097_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NV9097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NV9097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NV9097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NV9097_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NV9097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NV9097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SPARE_NOOP00 0x1040 +#define NV9097_SET_SPARE_NOOP00_V 31:0 + +#define NV9097_SET_SPARE_NOOP01 0x1044 +#define NV9097_SET_SPARE_NOOP01_V 31:0 + +#define NV9097_SET_SPARE_NOOP02 0x1048 +#define NV9097_SET_SPARE_NOOP02_V 31:0 + +#define NV9097_SET_SPARE_NOOP03 0x104c +#define NV9097_SET_SPARE_NOOP03_V 31:0 + +#define NV9097_SET_SPARE_NOOP04 0x1050 +#define NV9097_SET_SPARE_NOOP04_V 31:0 + +#define NV9097_SET_SPARE_NOOP05 0x1054 +#define NV9097_SET_SPARE_NOOP05_V 31:0 + +#define NV9097_SET_SPARE_NOOP06 0x1058 +#define NV9097_SET_SPARE_NOOP06_V 31:0 + +#define NV9097_SET_SPARE_NOOP07 0x105c +#define NV9097_SET_SPARE_NOOP07_V 31:0 + +#define NV9097_SET_SPARE_NOOP08 0x1060 +#define NV9097_SET_SPARE_NOOP08_V 31:0 + +#define NV9097_SET_SPARE_NOOP09 0x1064 +#define NV9097_SET_SPARE_NOOP09_V 31:0 + +#define NV9097_SET_SPARE_NOOP10 0x1068 +#define NV9097_SET_SPARE_NOOP10_V 31:0 + +#define NV9097_SET_SPARE_NOOP11 0x106c +#define NV9097_SET_SPARE_NOOP11_V 31:0 + +#define NV9097_SET_SPARE_NOOP12 0x1070 +#define NV9097_SET_SPARE_NOOP12_V 31:0 + +#define NV9097_SET_SPARE_NOOP13 0x1074 +#define NV9097_SET_SPARE_NOOP13_V 31:0 + +#define NV9097_SET_SPARE_NOOP14 0x1078 +#define NV9097_SET_SPARE_NOOP14_V 31:0 + +#define NV9097_SET_SPARE_NOOP15 0x107c +#define NV9097_SET_SPARE_NOOP15_V 31:0 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NV9097_UNBIND_ALL 0x10f4 +#define NV9097_UNBIND_ALL_TEXTURE_HEADERS 0:0 +#define NV9097_UNBIND_ALL_TEXTURE_HEADERS_FALSE 0x00000000 +#define NV9097_UNBIND_ALL_TEXTURE_HEADERS_TRUE 0x00000001 +#define NV9097_UNBIND_ALL_TEXTURE_SAMPLERS 4:4 +#define NV9097_UNBIND_ALL_TEXTURE_SAMPLERS_FALSE 0x00000000 +#define NV9097_UNBIND_ALL_TEXTURE_SAMPLERS_TRUE 0x00000001 +#define NV9097_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NV9097_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NV9097_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NV9097_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NV9097_NO_OPERATION_DATA_HI 0x110c +#define NV9097_NO_OPERATION_DATA_HI_V 31:0 + +#define NV9097_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NV9097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NV9097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NV9097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NV9097_PM_TRIGGER_END 0x1114 +#define NV9097_PM_TRIGGER_END_V 31:0 + +#define NV9097_SET_VERTEX_ID_BASE 0x1118 +#define NV9097_SET_VERTEX_ID_BASE_V 31:0 + +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NV9097_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NV9097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NV9097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NV9097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NV9097_FLUSH_PENDING_WRITES 0x1144 +#define NV9097_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NV9097_SET_VAB_DATA_CONTROL 0x114c +#define NV9097_SET_VAB_DATA_CONTROL_VAB_INDEX 7:0 +#define NV9097_SET_VAB_DATA_CONTROL_COMPONENT_COUNT 10:8 +#define NV9097_SET_VAB_DATA_CONTROL_COMPONENT_BYTE_WIDTH 14:12 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT 18:16 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_SNORM 0x00000001 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_UNORM 0x00000002 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_SINT 0x00000003 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_UINT 0x00000004 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_USCALED 0x00000005 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_SSCALED 0x00000006 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_FLOAT 0x00000007 + +#define NV9097_SET_VAB_DATA(i) (0x1150+(i)*4) +#define NV9097_SET_VAB_DATA_V 31:0 + +#define NV9097_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NV9097_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NV9097_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NV9097_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_SET_CT_SELECT 0x121c +#define NV9097_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NV9097_SET_CT_SELECT_TARGET0 6:4 +#define NV9097_SET_CT_SELECT_TARGET1 9:7 +#define NV9097_SET_CT_SELECT_TARGET2 12:10 +#define NV9097_SET_CT_SELECT_TARGET3 15:13 +#define NV9097_SET_CT_SELECT_TARGET4 18:16 +#define NV9097_SET_CT_SELECT_TARGET5 21:19 +#define NV9097_SET_CT_SELECT_TARGET6 24:22 +#define NV9097_SET_CT_SELECT_TARGET7 27:25 + +#define NV9097_SET_COMPRESSION_THRESHOLD 0x1220 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NV9097_SET_ZT_SIZE_A 0x1228 +#define NV9097_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NV9097_SET_ZT_SIZE_B 0x122c +#define NV9097_SET_ZT_SIZE_B_HEIGHT 16:0 + +#define NV9097_SET_ZT_SIZE_C 0x1230 +#define NV9097_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NV9097_SET_ZT_SIZE_C_CONTROL 16:16 +#define NV9097_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NV9097_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NV9097_SET_SAMPLER_BINDING 0x1234 +#define NV9097_SET_SAMPLER_BINDING_V 0:0 +#define NV9097_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NV9097_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NV9097_DRAW_AUTO 0x123c +#define NV9097_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NV9097_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NV9097_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 9:0 + +#define NV9097_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NV9097_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NV9097_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NV9097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NV9097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NV9097_SET_SHADER_SCHEDULING 0x12ac +#define NV9097_SET_SHADER_SCHEDULING_MODE 0:0 +#define NV9097_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 +#define NV9097_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 + +#define NV9097_CLEAR_ZCULL_REGION 0x12c8 +#define NV9097_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NV9097_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NV9097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NV9097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NV9097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NV9097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NV9097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NV9097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NV9097_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NV9097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NV9097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NV9097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NV9097_SET_DEPTH_TEST 0x12cc +#define NV9097_SET_DEPTH_TEST_ENABLE 0:0 +#define NV9097_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_FILL_MODE 0x12d0 +#define NV9097_SET_FILL_MODE_V 31:0 +#define NV9097_SET_FILL_MODE_V_POINT 0x00000001 +#define NV9097_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NV9097_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NV9097_SET_SHADE_MODE 0x12d4 +#define NV9097_SET_SHADE_MODE_V 31:0 +#define NV9097_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NV9097_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NV9097_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NV9097_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NV9097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NV9097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NV9097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NV9097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NV9097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NV9097_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NV9097_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NV9097_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NV9097_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_DEPTH_WRITE 0x12e8 +#define NV9097_SET_DEPTH_WRITE_ENABLE 0:0 +#define NV9097_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_ALPHA_TEST 0x12ec +#define NV9097_SET_ALPHA_TEST_ENABLE 0:0 +#define NV9097_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NV9097_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NV9097_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NV9097_DRAW_INLINE_INDEX4X8 0x1304 +#define NV9097_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NV9097_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NV9097_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NV9097_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NV9097_D3D_SET_CULL_MODE 0x1308 +#define NV9097_D3D_SET_CULL_MODE_V 31:0 +#define NV9097_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NV9097_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NV9097_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NV9097_SET_DEPTH_FUNC 0x130c +#define NV9097_SET_DEPTH_FUNC_V 31:0 +#define NV9097_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NV9097_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NV9097_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NV9097_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NV9097_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NV9097_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NV9097_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NV9097_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NV9097_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NV9097_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NV9097_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NV9097_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NV9097_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NV9097_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NV9097_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NV9097_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NV9097_SET_ALPHA_REF 0x1310 +#define NV9097_SET_ALPHA_REF_V 31:0 + +#define NV9097_SET_ALPHA_FUNC 0x1314 +#define NV9097_SET_ALPHA_FUNC_V 31:0 +#define NV9097_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NV9097_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NV9097_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NV9097_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NV9097_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NV9097_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NV9097_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NV9097_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NV9097_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NV9097_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NV9097_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NV9097_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NV9097_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NV9097_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NV9097_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NV9097_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NV9097_SET_DRAW_AUTO_STRIDE 0x1318 +#define NV9097_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NV9097_SET_BLEND_CONST_RED 0x131c +#define NV9097_SET_BLEND_CONST_RED_V 31:0 + +#define NV9097_SET_BLEND_CONST_GREEN 0x1320 +#define NV9097_SET_BLEND_CONST_GREEN_V 31:0 + +#define NV9097_SET_BLEND_CONST_BLUE 0x1324 +#define NV9097_SET_BLEND_CONST_BLUE_V 31:0 + +#define NV9097_SET_BLEND_CONST_ALPHA 0x1328 +#define NV9097_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NV9097_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NV9097_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NV9097_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NV9097_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NV9097_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS 2:1 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY 0x00000000 + +#define NV9097_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NV9097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NV9097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NV9097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_BLEND_COLOR_OP 0x1340 +#define NV9097_SET_BLEND_COLOR_OP_V 31:0 +#define NV9097_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NV9097_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NV9097_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NV9097_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NV9097_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NV9097_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NV9097_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NV9097_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NV9097_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NV9097_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_BLEND_ALPHA_OP 0x134c +#define NV9097_SET_BLEND_ALPHA_OP_V 31:0 +#define NV9097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NV9097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NV9097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NV9097_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NV9097_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NV9097_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NV9097_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NV9097_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NV9097_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NV9097_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_GLOBAL_COLOR_KEY 0x1354 +#define NV9097_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NV9097_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NV9097_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_SINGLE_ROP_CONTROL 0x135c +#define NV9097_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NV9097_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_BLEND(i) (0x1360+(i)*4) +#define NV9097_SET_BLEND_ENABLE 0:0 +#define NV9097_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NV9097_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_STENCIL_TEST 0x1380 +#define NV9097_SET_STENCIL_TEST_ENABLE 0:0 +#define NV9097_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_STENCIL_OP_FAIL 0x1384 +#define NV9097_SET_STENCIL_OP_FAIL_V 31:0 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NV9097_SET_STENCIL_OP_ZFAIL 0x1388 +#define NV9097_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NV9097_SET_STENCIL_OP_ZPASS 0x138c +#define NV9097_SET_STENCIL_OP_ZPASS_V 31:0 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NV9097_SET_STENCIL_FUNC 0x1390 +#define NV9097_SET_STENCIL_FUNC_V 31:0 +#define NV9097_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NV9097_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NV9097_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NV9097_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NV9097_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NV9097_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NV9097_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NV9097_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NV9097_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NV9097_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NV9097_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NV9097_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NV9097_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NV9097_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NV9097_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NV9097_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NV9097_SET_STENCIL_FUNC_REF 0x1394 +#define NV9097_SET_STENCIL_FUNC_REF_V 7:0 + +#define NV9097_SET_STENCIL_FUNC_MASK 0x1398 +#define NV9097_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NV9097_SET_STENCIL_MASK 0x139c +#define NV9097_SET_STENCIL_MASK_V 7:0 + +#define NV9097_SET_DRAW_AUTO_START 0x13a4 +#define NV9097_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NV9097_SET_PS_SATURATE 0x13a8 +#define NV9097_SET_PS_SATURATE_OUTPUT0 0:0 +#define NV9097_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT1 4:4 +#define NV9097_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT2 8:8 +#define NV9097_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT3 12:12 +#define NV9097_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT4 16:16 +#define NV9097_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT5 20:20 +#define NV9097_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT6 24:24 +#define NV9097_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT7 28:28 +#define NV9097_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 + +#define NV9097_SET_WINDOW_ORIGIN 0x13ac +#define NV9097_SET_WINDOW_ORIGIN_MODE 0:0 +#define NV9097_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NV9097_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NV9097_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NV9097_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NV9097_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NV9097_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NV9097_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NV9097_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NV9097_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NV9097_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NV9097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NV9097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_ALPHA_HYSTERESIS 0x1420 +#define NV9097_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NV9097_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NV9097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NV9097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NV9097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NV9097_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NV9097_INVALIDATE_DA_DMA_CACHE 0x142c +#define NV9097_INVALIDATE_DA_DMA_CACHE_V 0:0 + +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR 0x1430 +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR_UNORM_ENABLE 4:4 +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR_UNORM_ENABLE_FALSE 0x00000000 +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR_UNORM_ENABLE_TRUE 0x00000001 +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR_SRGB_ENABLE 8:8 +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR_SRGB_ENABLE_FALSE 0x00000000 +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR_SRGB_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NV9097_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NV9097_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NV9097_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NV9097_X_X_X_SET_CLEAR_CONTROL 0x143c +#define NV9097_X_X_X_SET_CLEAR_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NV9097_X_X_X_SET_CLEAR_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CLEAR_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CLEAR_CONTROL_USE_CLEAR_RECT 4:4 +#define NV9097_X_X_X_SET_CLEAR_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CLEAR_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 + +#define NV9097_SET_PS_WARP_WATERMARKS 0x1450 +#define NV9097_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NV9097_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NV9097_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NV9097_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NV9097_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NV9097_STORE_ZCULL 0x1464 +#define NV9097_STORE_ZCULL_V 0:0 + +#define NV9097_LOAD_ZCULL 0x1500 +#define NV9097_LOAD_ZCULL_V 0:0 + +#define NV9097_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NV9097_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NV9097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NV9097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NV9097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NV9097_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NV9097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NV9097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NV9097_SET_USER_CLIP_ENABLE 0x1510 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NV9097_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NV9097_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NV9097_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_POINT_SIZE 0x1518 +#define NV9097_SET_POINT_SIZE_V 31:0 + +#define NV9097_SET_ZCULL_STATS 0x151c +#define NV9097_SET_ZCULL_STATS_ENABLE 0:0 +#define NV9097_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_POINT_SPRITE 0x1520 +#define NV9097_SET_POINT_SPRITE_ENABLE 0:0 +#define NV9097_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SHADER_EXCEPTIONS 0x1528 +#define NV9097_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NV9097_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NV9097_CLEAR_REPORT_VALUE 0x1530 +#define NV9097_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NV9097_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NV9097_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NV9097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NV9097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NV9097_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NV9097_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 + +#define NV9097_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NV9097_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NV9097_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_ZT_SELECT 0x1538 +#define NV9097_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NV9097_SET_RENDER_ENABLE_A 0x1550 +#define NV9097_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_RENDER_ENABLE_B 0x1554 +#define NV9097_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_RENDER_ENABLE_C 0x1558 +#define NV9097_SET_RENDER_ENABLE_C_MODE 2:0 +#define NV9097_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV9097_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV9097_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV9097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV9097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV9097_SET_TEX_SAMPLER_POOL_A 0x155c +#define NV9097_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NV9097_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NV9097_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NV9097_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NV9097_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NV9097_SET_ANTI_ALIASED_LINE 0x1570 +#define NV9097_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NV9097_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_TEX_HEADER_POOL_A 0x1574 +#define NV9097_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_TEX_HEADER_POOL_B 0x1578 +#define NV9097_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_TEX_HEADER_POOL_C 0x157c +#define NV9097_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NV9097_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NV9097_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NV9097_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NV9097_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NV9097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NV9097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NV9097_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NV9097_SET_BACK_STENCIL_FUNC 0x15a4 +#define NV9097_SET_BACK_STENCIL_FUNC_V 31:0 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NV9097_SET_SRGB_WRITE 0x15b8 +#define NV9097_SET_SRGB_WRITE_ENABLE 0:0 +#define NV9097_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_DEPTH_BIAS 0x15bc +#define NV9097_SET_DEPTH_BIAS_V 31:0 + +#define NV9097_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NV9097_SET_ZCULL_REGION_FORMAT_TYPE 1:0 +#define NV9097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NV9097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NV9097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NV9097_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 + +#define NV9097_SET_RT_LAYER 0x15cc +#define NV9097_SET_RT_LAYER_V 15:0 +#define NV9097_SET_RT_LAYER_CONTROL 16:16 +#define NV9097_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NV9097_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NV9097_SET_ANTI_ALIAS 0x15d0 +#define NV9097_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NV9097_SET_EDGE_FLAG 0x15e4 +#define NV9097_SET_EDGE_FLAG_V 0:0 +#define NV9097_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NV9097_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NV9097_DRAW_INLINE_INDEX 0x15e8 +#define NV9097_DRAW_INLINE_INDEX_V 31:0 + +#define NV9097_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NV9097_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NV9097_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NV9097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NV9097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NV9097_DRAW_INLINE_INDEX2X16 0x15f0 +#define NV9097_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NV9097_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NV9097_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NV9097_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NV9097_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NV9097_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NV9097_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NV9097_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NV9097_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NV9097_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NV9097_SET_POINT_SPRITE_SELECT 0x1604 +#define NV9097_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NV9097_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NV9097_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NV9097_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NV9097_SET_PROGRAM_REGION_A 0x1608 +#define NV9097_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NV9097_SET_PROGRAM_REGION_B 0x160c +#define NV9097_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NV9097_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NV9097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NV9097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NV9097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NV9097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NV9097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NV9097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NV9097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NV9097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NV9097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NV9097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NV9097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NV9097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NV9097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NV9097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NV9097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NV9097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NV9097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NV9097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NV9097_END 0x1614 +#define NV9097_END_V 0:0 + +#define NV9097_BEGIN 0x1618 +#define NV9097_BEGIN_OP 15:0 +#define NV9097_BEGIN_OP_POINTS 0x00000000 +#define NV9097_BEGIN_OP_LINES 0x00000001 +#define NV9097_BEGIN_OP_LINE_LOOP 0x00000002 +#define NV9097_BEGIN_OP_LINE_STRIP 0x00000003 +#define NV9097_BEGIN_OP_TRIANGLES 0x00000004 +#define NV9097_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NV9097_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NV9097_BEGIN_OP_QUADS 0x00000007 +#define NV9097_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NV9097_BEGIN_OP_POLYGON 0x00000009 +#define NV9097_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NV9097_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NV9097_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_BEGIN_OP_PATCH 0x0000000E +#define NV9097_BEGIN_PRIMITIVE_ID 24:24 +#define NV9097_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NV9097_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NV9097_BEGIN_INSTANCE_ID 27:26 +#define NV9097_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NV9097_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NV9097_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NV9097_BEGIN_SPLIT_MODE 30:29 +#define NV9097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NV9097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NV9097_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NV9097_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 + +#define NV9097_SET_VERTEX_ID_COPY 0x161c +#define NV9097_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NV9097_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NV9097_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NV9097_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NV9097_ADD_TO_PRIMITIVE_ID 0x1620 +#define NV9097_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NV9097_LOAD_PRIMITIVE_ID 0x1624 +#define NV9097_LOAD_PRIMITIVE_ID_V 31:0 + +#define NV9097_SET_SHADER_BASED_CULL 0x162c +#define NV9097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NV9097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NV9097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NV9097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SHADER_ISA_VERSION 0x1634 +#define NV9097_SET_SHADER_ISA_VERSION_MINOR_SUB 7:0 +#define NV9097_SET_SHADER_ISA_VERSION_MINOR 15:8 +#define NV9097_SET_SHADER_ISA_VERSION_MAJOR 23:16 + +#define NV9097_SET_FERMI_CLASS_VERSION 0x1638 +#define NV9097_SET_FERMI_CLASS_VERSION_CURRENT 15:0 +#define NV9097_SET_FERMI_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NV9097_SET_VAB_PAGE 0x163c +#define NV9097_SET_VAB_PAGE_READ_SELECT 0:0 +#define NV9097_SET_VAB_PAGE_READ_SELECT_PAGES_0_AND_1 0x00000000 +#define NV9097_SET_VAB_PAGE_READ_SELECT_PAGES_0_AND_2 0x00000001 + +#define NV9097_DRAW_INLINE_VERTEX 0x1640 +#define NV9097_DRAW_INLINE_VERTEX_V 31:0 + +#define NV9097_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NV9097_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NV9097_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NV9097_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NV9097_SET_DA_OUTPUT 0x164c +#define NV9097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NV9097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NV9097_SET_ANTI_ALIASED_POINT 0x1658 +#define NV9097_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NV9097_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_POINT_CENTER_MODE 0x165c +#define NV9097_SET_POINT_CENTER_MODE_V 31:0 +#define NV9097_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NV9097_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NV9097_SET_CUBEMAP_INTER_FACE_FILTERING 0x1664 +#define NV9097_SET_CUBEMAP_INTER_FACE_FILTERING_MODE 2:1 +#define NV9097_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_USE_WRAP 0x00000000 +#define NV9097_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_OVERRIDE_WRAP 0x00000001 +#define NV9097_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_SPAN_SEAM 0x00000002 +#define NV9097_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_CROSS_SEAM 0x00000003 + +#define NV9097_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NV9097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NV9097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NV9097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NV9097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NV9097_SET_LINE_STIPPLE 0x166c +#define NV9097_SET_LINE_STIPPLE_ENABLE 0:0 +#define NV9097_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NV9097_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NV9097_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NV9097_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NV9097_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NV9097_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NV9097_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NV9097_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NV9097_SET_PROVOKING_VERTEX 0x1684 +#define NV9097_SET_PROVOKING_VERTEX_V 0:0 +#define NV9097_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NV9097_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NV9097_SET_TWO_SIDED_LIGHT 0x1688 +#define NV9097_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NV9097_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_POLYGON_STIPPLE 0x168c +#define NV9097_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NV9097_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SHADER_CONTROL 0x1690 +#define NV9097_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NV9097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NV9097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NV9097_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO 16:16 +#define NV9097_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NV9097_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NV9097_LAUNCH_VERTEX 0x169c +#define NV9097_LAUNCH_VERTEX_V 0:0 + +#define NV9097_CHECK_FERMI_CLASS_VERSION 0x16a0 +#define NV9097_CHECK_FERMI_CLASS_VERSION_CURRENT 15:0 +#define NV9097_CHECK_FERMI_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NV9097_SET_SPH_VERSION 0x16a4 +#define NV9097_SET_SPH_VERSION_CURRENT 15:0 +#define NV9097_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NV9097_CHECK_SPH_VERSION 0x16a8 +#define NV9097_CHECK_SPH_VERSION_CURRENT 15:0 +#define NV9097_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NV9097_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NV9097_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NV9097_SET_AAM_VERSION 0x1790 +#define NV9097_SET_AAM_VERSION_CURRENT 15:0 +#define NV9097_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NV9097_CHECK_AAM_VERSION 0x1794 +#define NV9097_CHECK_AAM_VERSION_CURRENT 15:0 +#define NV9097_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NV9097_SET_ZT_LAYER 0x179c +#define NV9097_SET_ZT_LAYER_OFFSET 15:0 + +#define NV9097_SET_VAB_MEMORY_AREA_A 0x17bc +#define NV9097_SET_VAB_MEMORY_AREA_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_VAB_MEMORY_AREA_B 0x17c0 +#define NV9097_SET_VAB_MEMORY_AREA_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_VAB_MEMORY_AREA_C 0x17c4 +#define NV9097_SET_VAB_MEMORY_AREA_C_SIZE 1:0 +#define NV9097_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_64K 0x00000001 +#define NV9097_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_128K 0x00000002 +#define NV9097_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_256K 0x00000003 + +#define NV9097_SET_INDEX_BUFFER_A 0x17c8 +#define NV9097_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NV9097_SET_INDEX_BUFFER_B 0x17cc +#define NV9097_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NV9097_SET_INDEX_BUFFER_C 0x17d0 +#define NV9097_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NV9097_SET_INDEX_BUFFER_D 0x17d4 +#define NV9097_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NV9097_SET_INDEX_BUFFER_E 0x17d8 +#define NV9097_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NV9097_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NV9097_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NV9097_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NV9097_SET_INDEX_BUFFER_F 0x17dc +#define NV9097_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NV9097_DRAW_INDEX_BUFFER 0x17e0 +#define NV9097_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_SET_DEPTH_BIAS_CLAMP 0x187c +#define NV9097_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NV9097_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NV9097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NV9097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NV9097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NV9097_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NV9097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NV9097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NV9097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NV9097_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NV9097_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NV9097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NV9097_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NV9097_OGL_SET_CULL 0x1918 +#define NV9097_OGL_SET_CULL_ENABLE 0:0 +#define NV9097_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NV9097_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NV9097_OGL_SET_FRONT_FACE 0x191c +#define NV9097_OGL_SET_FRONT_FACE_V 31:0 +#define NV9097_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NV9097_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NV9097_OGL_SET_CULL_FACE 0x1920 +#define NV9097_OGL_SET_CULL_FACE_V 31:0 +#define NV9097_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NV9097_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NV9097_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NV9097_SET_VIEWPORT_PIXEL 0x1924 +#define NV9097_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NV9097_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NV9097_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NV9097_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NV9097_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NV9097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NV9097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NV9097_INVALIDATE_CONSTANT_BUFFER_CACHE 0x1930 +#define NV9097_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2 0:0 +#define NV9097_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_FALSE 0x00000000 +#define NV9097_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_TRUE 0x00000001 + +#define NV9097_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NV9097_SET_USER_CLIP_OP 0x1940 +#define NV9097_SET_USER_CLIP_OP_PLANE0 0:0 +#define NV9097_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE1 4:4 +#define NV9097_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE2 8:8 +#define NV9097_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE3 12:12 +#define NV9097_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE4 16:16 +#define NV9097_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE5 20:20 +#define NV9097_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE6 24:24 +#define NV9097_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE7 28:28 +#define NV9097_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NV9097_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NV9097_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NV9097_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NV9097_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NV9097_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NV9097_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NV9097_SET_WINDOW_CLIP_ENABLE 0x194c +#define NV9097_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NV9097_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_WINDOW_CLIP_TYPE 0x1950 +#define NV9097_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NV9097_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NV9097_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NV9097_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NV9097_INVALIDATE_ZCULL 0x1958 +#define NV9097_INVALIDATE_ZCULL_V 31:0 +#define NV9097_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NV9097_SET_ZCULL 0x1968 +#define NV9097_SET_ZCULL_Z_ENABLE 0:0 +#define NV9097_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NV9097_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NV9097_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_ZCULL_BOUNDS 0x196c +#define NV9097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NV9097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NV9097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NV9097_ZCULL_SYNC 0x1978 +#define NV9097_ZCULL_SYNC_V 31:0 + +#define NV9097_SET_CLIP_ID_TEST 0x197c +#define NV9097_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NV9097_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NV9097_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NV9097_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NV9097_SET_CLIP_ID 0x1984 +#define NV9097_SET_CLIP_ID_V 31:0 + +#define NV9097_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NV9097_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NV9097_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NV9097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NV9097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NV9097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NV9097_SET_LOGIC_OP 0x19c4 +#define NV9097_SET_LOGIC_OP_ENABLE 0:0 +#define NV9097_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NV9097_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_LOGIC_OP_FUNC 0x19c8 +#define NV9097_SET_LOGIC_OP_FUNC_V 31:0 +#define NV9097_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NV9097_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NV9097_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NV9097_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NV9097_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NV9097_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NV9097_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NV9097_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NV9097_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NV9097_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NV9097_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NV9097_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NV9097_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NV9097_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NV9097_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NV9097_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NV9097_SET_Z_COMPRESSION 0x19cc +#define NV9097_SET_Z_COMPRESSION_ENABLE 0:0 +#define NV9097_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NV9097_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NV9097_CLEAR_SURFACE 0x19d0 +#define NV9097_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NV9097_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NV9097_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_SURFACE_R_ENABLE 2:2 +#define NV9097_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_SURFACE_G_ENABLE 3:3 +#define NV9097_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_SURFACE_B_ENABLE 4:4 +#define NV9097_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_SURFACE_A_ENABLE 5:5 +#define NV9097_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NV9097_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NV9097_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NV9097_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NV9097_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NV9097_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NV9097_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NV9097_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NV9097_SET_CT_WRITE_R_ENABLE 0:0 +#define NV9097_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NV9097_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NV9097_SET_CT_WRITE_G_ENABLE 4:4 +#define NV9097_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NV9097_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NV9097_SET_CT_WRITE_B_ENABLE 8:8 +#define NV9097_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NV9097_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NV9097_SET_CT_WRITE_A_ENABLE 12:12 +#define NV9097_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NV9097_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NV9097_PIPE_NOP 0x1a2c +#define NV9097_PIPE_NOP_V 31:0 + +#define NV9097_SET_SPARE00 0x1a30 +#define NV9097_SET_SPARE00_V 31:0 + +#define NV9097_SET_SPARE01 0x1a34 +#define NV9097_SET_SPARE01_V 31:0 + +#define NV9097_SET_SPARE02 0x1a38 +#define NV9097_SET_SPARE02_V 31:0 + +#define NV9097_SET_SPARE03 0x1a3c +#define NV9097_SET_SPARE03_V 31:0 + +#define NV9097_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NV9097_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NV9097_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NV9097_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NV9097_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NV9097_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NV9097_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NV9097_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NV9097_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NV9097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NV9097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NV9097_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NV9097_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NV9097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NV9097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NV9097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NV9097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NV9097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 + +#define NV9097_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NV9097_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NV9097_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NV9097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NV9097_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NV9097_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NV9097_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NV9097_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NV9097_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NV9097_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NV9097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NV9097_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NV9097_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NV9097_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NV9097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NV9097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NV9097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NV9097_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NV9097_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NV9097_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NV9097_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NV9097_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NV9097_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NV9097_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NV9097_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NV9097_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NV9097_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NV9097_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NV9097_SET_PIPELINE_SHADER_TYPE 7:4 +#define NV9097_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NV9097_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NV9097_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NV9097_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NV9097_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NV9097_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NV9097_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NV9097_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NV9097_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NV9097_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NV9097_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NV9097_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NV9097_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NV9097_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NV9097_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NV9097_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NV9097_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NV9097_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NV9097_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NV9097_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NV9097_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NV9097_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NV9097_SET_BINDING_CONTROL_TEXTURE(j) (0x2200+(j)*16) +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS 3:0 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__1 0x00000000 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__2 0x00000001 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__4 0x00000002 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__8 0x00000003 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__16 0x00000004 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS 7:4 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__1 0x00000000 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__2 0x00000001 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__4 0x00000002 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__8 0x00000003 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__16 0x00000004 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__32 0x00000005 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__64 0x00000006 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__128 0x00000007 + +#define NV9097_SET_BINDING_CONTROL_RESERVED_A(j) (0x2204+(j)*16) +#define NV9097_SET_BINDING_CONTROL_RESERVED_A_V 0:0 + +#define NV9097_SET_BINDING_CONTROL_RESERVED_B(j) (0x2208+(j)*16) +#define NV9097_SET_BINDING_CONTROL_RESERVED_B_V 0:0 + +#define NV9097_SET_FALCON00 0x2300 +#define NV9097_SET_FALCON00_V 31:0 + +#define NV9097_SET_FALCON01 0x2304 +#define NV9097_SET_FALCON01_V 31:0 + +#define NV9097_SET_FALCON02 0x2308 +#define NV9097_SET_FALCON02_V 31:0 + +#define NV9097_SET_FALCON03 0x230c +#define NV9097_SET_FALCON03_V 31:0 + +#define NV9097_SET_FALCON04 0x2310 +#define NV9097_SET_FALCON04_V 31:0 + +#define NV9097_SET_FALCON05 0x2314 +#define NV9097_SET_FALCON05_V 31:0 + +#define NV9097_SET_FALCON06 0x2318 +#define NV9097_SET_FALCON06_V 31:0 + +#define NV9097_SET_FALCON07 0x231c +#define NV9097_SET_FALCON07_V 31:0 + +#define NV9097_SET_FALCON08 0x2320 +#define NV9097_SET_FALCON08_V 31:0 + +#define NV9097_SET_FALCON09 0x2324 +#define NV9097_SET_FALCON09_V 31:0 + +#define NV9097_SET_FALCON10 0x2328 +#define NV9097_SET_FALCON10_V 31:0 + +#define NV9097_SET_FALCON11 0x232c +#define NV9097_SET_FALCON11_V 31:0 + +#define NV9097_SET_FALCON12 0x2330 +#define NV9097_SET_FALCON12_V 31:0 + +#define NV9097_SET_FALCON13 0x2334 +#define NV9097_SET_FALCON13_V 31:0 + +#define NV9097_SET_FALCON14 0x2338 +#define NV9097_SET_FALCON14_V 31:0 + +#define NV9097_SET_FALCON15 0x233c +#define NV9097_SET_FALCON15_V 31:0 + +#define NV9097_SET_FALCON16 0x2340 +#define NV9097_SET_FALCON16_V 31:0 + +#define NV9097_SET_FALCON17 0x2344 +#define NV9097_SET_FALCON17_V 31:0 + +#define NV9097_SET_FALCON18 0x2348 +#define NV9097_SET_FALCON18_V 31:0 + +#define NV9097_SET_FALCON19 0x234c +#define NV9097_SET_FALCON19_V 31:0 + +#define NV9097_SET_FALCON20 0x2350 +#define NV9097_SET_FALCON20_V 31:0 + +#define NV9097_SET_FALCON21 0x2354 +#define NV9097_SET_FALCON21_V 31:0 + +#define NV9097_SET_FALCON22 0x2358 +#define NV9097_SET_FALCON22_V 31:0 + +#define NV9097_SET_FALCON23 0x235c +#define NV9097_SET_FALCON23_V 31:0 + +#define NV9097_SET_FALCON24 0x2360 +#define NV9097_SET_FALCON24_V 31:0 + +#define NV9097_SET_FALCON25 0x2364 +#define NV9097_SET_FALCON25_V 31:0 + +#define NV9097_SET_FALCON26 0x2368 +#define NV9097_SET_FALCON26_V 31:0 + +#define NV9097_SET_FALCON27 0x236c +#define NV9097_SET_FALCON27_V 31:0 + +#define NV9097_SET_FALCON28 0x2370 +#define NV9097_SET_FALCON28_V 31:0 + +#define NV9097_SET_FALCON29 0x2374 +#define NV9097_SET_FALCON29_V 31:0 + +#define NV9097_SET_FALCON30 0x2378 +#define NV9097_SET_FALCON30_V 31:0 + +#define NV9097_SET_FALCON31 0x237c +#define NV9097_SET_FALCON31_V 31:0 + +#define NV9097_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NV9097_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NV9097_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NV9097_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NV9097_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NV9097_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NV9097_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NV9097_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NV9097_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NV9097_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NV9097_BIND_GROUP_TEXTURE_SAMPLER(j) (0x2400+(j)*32) +#define NV9097_BIND_GROUP_TEXTURE_SAMPLER_VALID 0:0 +#define NV9097_BIND_GROUP_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 +#define NV9097_BIND_GROUP_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 +#define NV9097_BIND_GROUP_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 +#define NV9097_BIND_GROUP_TEXTURE_SAMPLER_INDEX 24:12 + +#define NV9097_BIND_GROUP_TEXTURE_HEADER(j) (0x2404+(j)*32) +#define NV9097_BIND_GROUP_TEXTURE_HEADER_VALID 0:0 +#define NV9097_BIND_GROUP_TEXTURE_HEADER_VALID_FALSE 0x00000000 +#define NV9097_BIND_GROUP_TEXTURE_HEADER_VALID_TRUE 0x00000001 +#define NV9097_BIND_GROUP_TEXTURE_HEADER_TEXTURE_SLOT 8:1 +#define NV9097_BIND_GROUP_TEXTURE_HEADER_INDEX 30:9 + +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_SAMPLER(j) (0x2408+(j)*32) +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_SAMPLER_VALID 0:0 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_SAMPLER_INDEX 24:12 + +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_HEADER(j) (0x240c+(j)*32) +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_HEADER_VALID 0:0 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_HEADER_VALID_FALSE 0x00000000 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_HEADER_VALID_TRUE 0x00000001 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_HEADER_TEXTURE_SLOT 8:1 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_HEADER_INDEX 30:9 + +#define NV9097_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NV9097_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NV9097_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NV9097_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NV9097_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NV9097_RESERVED_GROUP_B_RESERVED_A(j) (0x2500+(j)*32) +#define NV9097_RESERVED_GROUP_B_RESERVED_A_V 0:0 + +#define NV9097_RESERVED_GROUP_B_RESERVED_B(j) (0x2504+(j)*32) +#define NV9097_RESERVED_GROUP_B_RESERVED_B_V 0:0 + +#define NV9097_RESERVED_GROUP_B_RESERVED_C(j) (0x2508+(j)*32) +#define NV9097_RESERVED_GROUP_B_RESERVED_C_V 0:0 + +#define NV9097_RESERVED_GROUP_B_RESERVED_D(j) (0x250c+(j)*32) +#define NV9097_RESERVED_GROUP_B_RESERVED_D_V 0:0 + +#define NV9097_RESERVED_GROUP_B_RESERVED_E(j) (0x2510+(j)*32) +#define NV9097_RESERVED_GROUP_B_RESERVED_E_V 0:0 + +#define NV9097_SET_COLOR_CLAMP 0x2600 +#define NV9097_SET_COLOR_CLAMP_ENABLE 0:0 +#define NV9097_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NV9097_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SU_LD_ST_TARGET_A(j) (0x2700+(j)*32) +#define NV9097_SET_SU_LD_ST_TARGET_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_SU_LD_ST_TARGET_B(j) (0x2704+(j)*32) +#define NV9097_SET_SU_LD_ST_TARGET_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_SU_LD_ST_TARGET_C(j) (0x2708+(j)*32) +#define NV9097_SET_SU_LD_ST_TARGET_C_WIDTH 31:0 + +#define NV9097_SET_SU_LD_ST_TARGET_D(j) (0x270c+(j)*32) +#define NV9097_SET_SU_LD_ST_TARGET_D_HEIGHT 16:0 +#define NV9097_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY 20:20 +#define NV9097_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_BLOCKLINEAR 0x00000000 +#define NV9097_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_PITCH 0x00000001 + +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT(j) (0x2710+(j)*32) +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_TYPE 0:0 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_TYPE_COLOR 0x00000000 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_TYPE_ZETA 0x00000001 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR 11:4 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_DISABLED 0x00000000 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_AF32 0x000000C0 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_AS32 0x000000C1 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_AU32 0x000000C2 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_X32 0x000000C3 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_X32 0x000000C4 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_X32 0x000000C5 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16_B16_A16 0x000000C6 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16_BN16_AN16 0x000000C7 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16_BS16_AS16 0x000000C8 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16_BU16_AU16 0x000000C9 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_AF16 0x000000CA +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32 0x000000CB +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32 0x000000CC +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32 0x000000CD +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_X16 0x000000CE +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8G8B8 0x000000CF +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8RL8GL8BL8 0x000000D0 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2B10G10R10 0x000000D1 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU2BU10GU10RU10 0x000000D2 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8B8G8R8 0x000000D5 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8BL8GL8RL8 0x000000D6 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AN8BN8GN8RN8 0x000000D7 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AS8BS8GS8RS8 0x000000D8 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU8BU8GU8RU8 0x000000D9 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16 0x000000DA +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16 0x000000DB +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16 0x000000DC +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16 0x000000DD +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16 0x000000DE +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2R10G10B10 0x000000DF +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_BF10GF11RF11 0x000000E0 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32 0x000000E3 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32 0x000000E4 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32 0x000000E5 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8R8G8B8 0x000000E6 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8RL8GL8BL8 0x000000E7 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R5G6B5 0x000000E8 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A1R5G5B5 0x000000E9 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_G8R8 0x000000EA +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GN8RN8 0x000000EB +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GS8RS8 0x000000EC +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GU8RU8 0x000000ED +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16 0x000000EE +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16 0x000000EF +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16 0x000000F0 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16 0x000000F1 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16 0x000000F2 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R8 0x000000F3 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN8 0x000000F4 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS8 0x000000F5 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU8 0x000000F6 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8 0x000000F7 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X1R5G5B5 0x000000F8 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8B8G8R8 0x000000F9 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8BL8GL8RL8 0x000000FA +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z1R5G5B5 0x000000FB +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O1R5G5B5 0x000000FC +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z8R8G8B8 0x000000FD +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O8R8G8B8 0x000000FE +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R32 0x000000FF +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A16 0x00000040 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF16 0x00000041 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF32 0x00000042 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8 0x00000043 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_A16 0x00000044 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_AF16 0x00000045 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_AF32 0x00000046 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA 16:12 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z16 0x00000013 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z24S8 0x00000014 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24 0x00000015 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_S8Z24 0x00000016 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_V8Z24 0x00000018 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32 0x0000000A +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X24S8 0x00000019 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24_X16V8S8 0x0000001D +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8X8 0x0000001E +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8S8 0x0000001F + +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE(j) (0x2714+(j)*32) +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH 3:0 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT 7:4 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 + +#define NV9097_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NV9097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NV9097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NV9097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NV9097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 2:0 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 6:4 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 10:8 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 14:12 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 18:16 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 22:20 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 26:24 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 30:28 + +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NV9097_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NV9097_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NV9097_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NV9097_CALL_MME_MACRO_V 31:0 + +#define NV9097_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NV9097_CALL_MME_DATA_V 31:0 + +#endif /* _cl_fermi_a_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl90cc.h b/userspace/sdks/nv570/inc/class/cl90cc.h new file mode 100644 index 0000000..25d8570 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl90cc.h @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl90cc_h_ +#define _cl90cc_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define GF100_PROFILER (0x000090CC) + +/* + * Creating the GF100_PROFILER object: + * - The profiler object is instantiated as a child of either the subdevice or + * a channel group or channel, depending on whether reservations + * should be global to the subdevice or per-context. When the profiler + * requests a reservation or information about outstanding reservations, the + * scope of the request is determined by the profiler object's parent class. + */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl90cc_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl90cd.h b/userspace/sdks/nv570/inc/class/cl90cd.h new file mode 100644 index 0000000..4c732eb --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl90cd.h @@ -0,0 +1,237 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * NV_EVENT_BUFFER + * An event buffer is shared between user (RO) and kernel(RW). + * It holds debug/profile event data provided by the kernel. + * + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl90cd.finn +// + +#define NV_EVENT_BUFFER (0x90cdU) /* finn: Evaluated from "NV_EVENT_BUFFER_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* + * NV_EVENT_BUFFER_HEADER + * This structure holds the get and put values used to index/consume event buffer. + * Along with other RO data shared with the user. + * + * recordGet/Put: These "pointers" work in the traditional sense: + * - when GET==PUT, the fifo is empty + * - when GET==PUT+1, the fifo is full + * This implies a full fifo always has one "wasted" element. + * + * recordCount: This is the total number of records added to the buffer by the kernel + * This information is filled out when the buffer is setup to keep newest records. + * recordCount = number of records currently in the buffer + overflow count. + * + * recordDropcount: This is the number of event records that are dropped because the + * buffer is full. + * This information is filled out when event buffer is setup to keep oldest records. + * + * vardataDropcount: Event buffer provides a dual stream of data, where the record can contain + * an optional offset to a variable length data buffer. + * This is the number of variable data records that are dropped because the + * buffer is full. + * This information is filled out when event buffer is setup to keep oldest records. + */ +typedef struct NV_EVENT_BUFFER_HEADER { + NvU32 recordGet; + NvU32 recordPut; + NV_DECLARE_ALIGNED(NvU64 recordCount, 8); + NV_DECLARE_ALIGNED(NvU64 recordDropcount, 8); + NV_DECLARE_ALIGNED(NvU64 vardataDropcount, 8); +} NV_EVENT_BUFFER_HEADER; + +/* + * NV_EVENT_BUFFER_RECORD_HEADER + * This is the header added to each event record. + * This helps identify the event type and variable length data is associated with it. + */ +typedef struct NV_EVENT_BUFFER_RECORD_HEADER { + NvU16 type; + NvU16 subtype; + NvU32 varData; // [31: 5] = (varDataOffset >> 5); 0 < vardataOffset <= vardataBufferSize + // [ 4: 1] = reserved for future use + // [ 0: 0] = isVardataStartOffsetZero +} NV_EVENT_BUFFER_RECORD_HEADER; + +/* + * NV_EVENT_BUFFER_RECORD + * This structure defines a generic event record. + * The size of this record is fixed for a given event buffer. + * It is configured by the user during allocation. + */ +typedef struct NV_EVENT_BUFFER_RECORD { + NV_EVENT_BUFFER_RECORD_HEADER recordHeader; + NV_DECLARE_ALIGNED(NvU64 inlinePayload[1], 8); // 1st element of the payload/data + // Do not add more elements here, inlinePayload can contain more than one elements +} NV_EVENT_BUFFER_RECORD; + +#define NV_EVENT_VARDATA_GRANULARITY 32 +#define NV_EVENT_VARDATA_OFFSET_MASK (~(NV_EVENT_VARDATA_GRANULARITY - 1)) +#define NV_EVENT_VARDATA_START_OFFSET_ZERO 0x01 + +/* + * NV_EVENT_BUFFER_ALLOC_PARAMETERS + * + * bufferHeader [OUT] + * This is the user VA offset pointing to the base of NV_EVENT_BUFFER_HEADER. + * + * recordBuffer [OUT] + * This is the user VA offset pointing to the base of the event record buffer. + * This buffer will contain NV_EVENT_BUFFER_RECORDs added by the kernel. + * + * recordSize [IN] + * This is the size of NV_EVENT_BUFFER_RECORD used by this buffer + * + * recordCount [IN] + * This is the number of records that recordBuffer can hold. + * + * vardataBuffer [OUT] + * This is the user VA offset pointing to the base of the variable data buffer. + * + * vardataBufferSize [IN] + * Size of the variable data buffer in bytes. + * + * recordsFreeThreshold [IN] + * This is the notification threshold for the event record buffer. + * This felid specifies the number of records that the buffer can + * still hold before it gets full. + * + * vardataFreeThreshold [IN] + * This is the notification threshold for the vardata buffer. + * This felid specifies the number of bytes that the buffer can + * still hold before it gets full. + * + * notificationHandle [IN] + * When recordsFreeThreshold or vardataFreeThreshold is met, kernel will notify + * user on this handle. If notificationHandle = NULL, event notification + * is disabled. This is an OS specific notification handle. + * It is a Windows event handle or a fd pointer on Linux. + * + * hSubDevice [IN] + * An event buffer can either hold sub-device related events or system events. + * This handle specifies the sub-device to associate this buffer with. + * If this parameter is NULL, then the buffer is tied to the client instead. + * + * flags [IN] + * Set to 0 by default. + * This field can hold any future flags to configure the buffer if needed. + * + * hBufferHeader [IN] + * The backing memory object for the buffer header. Must be a NV01_MEMORY_DEVICELESS object. + * On Windows platforms, a buffer will be internally generated if hBufferHeader is 0. + * + * hRecordBuffer [IN] + * The backing memory object for the record buffer. Must be a NV01_MEMORY_DEVICELESS object. + * On Windows platforms, a buffer will be internally generated if hRecordBuffer is 0. + * + * hVardataBuffer [IN] + * The backing memory object for the vardata buffer. Must be a NV01_MEMORY_DEVICELESS object. + * On Windows platforms, a buffer will be internally generated if hVardataBuffer is 0. + * + */ +#define NV_EVENT_BUFFER_ALLOC_PARAMETERS_MESSAGE_ID (0x90cdU) + +typedef struct NV_EVENT_BUFFER_ALLOC_PARAMETERS { + NV_DECLARE_ALIGNED(NvP64 bufferHeader, 8); + NV_DECLARE_ALIGNED(NvP64 recordBuffer, 8); + NvU32 recordSize; + NvU32 recordCount; + NV_DECLARE_ALIGNED(NvP64 vardataBuffer, 8); + NvU32 vardataBufferSize; + NvU32 recordsFreeThreshold; + NV_DECLARE_ALIGNED(NvU64 notificationHandle, 8); + NvU32 vardataFreeThreshold; + NvHandle hSubDevice; + NvU32 flags; + + NvHandle hBufferHeader; + NvHandle hRecordBuffer; + NvHandle hVardataBuffer; +} NV_EVENT_BUFFER_ALLOC_PARAMETERS; + +/* + * NV_EVENT_BUFFER_BIND + * This class is used to allocate an Event Type object bound to a given event buffer. + * This allocation call associates an event type with an event buffer. + * Multiple event types can be associated with the same buffer as long as they belong to + * the same category i.e. either sub-device or system. + * When event buffer is enabled, if an event bound to this buffer occurs, + * some relevant data gets added to it. + * cl2080.h has a list of sub-device events that can be associated with a buffer + * cl0000.h has a list of system events that can be associated with a buffer + * These defines are also used in class NV01_EVENT_OS_EVENT (0x79) to get event notification + * and class NV01_EVENT_KERNEL_CALLBACK_EX (0x7E) to get kernel callbacks. + * This class extends that support to additionally get relevant data in an event buffer + * + */ +#define NV_EVENT_BUFFER_BIND (0x0000007F) + +/* + * NV_EVENT_BUFFER_BIND_PARAMETERS + * + * bufferHandle [IN] + * Event buffer handle used to bind the given event type + * + * eventType [IN] + * This is one of the eventTypeIDs from cl2080.h/cl000.h + * e.g. NV2080_NOTIFIERS_PSTATE_CHANGE + * + * eventSubtype [IN] + * Event subtype for a given type of event. + * This field is optional depending on if an eventtype has a subtype. + * + * hClientTarget [IN] + * Handle of the target client whose events are to be bound to the given buffer + * e.g. context switch events can be tracked for a given client. + * This field is optional depending on the event type. + * e.g. pstate change events are per gpu but do not depend on a client. + * + * hSrcResource [IN] + * source resource handle for the event type + * e.g. channel handle: RC/context switch can be tracked for a given channel + * This field is optional depending on the event type. + * e.g. pstate change events are per gpu and cannot be sub-categorized + * + * KernelCallbackdata [IN] + * This field is reserved for KERNEL ONLY clients. + * + */ +typedef struct NV_EVENT_BUFFER_BIND_PARAMETERS { + NvHandle bufferHandle; + NvU16 eventType; + NvU16 eventSubtype; + NvHandle hClientTarget; + NvHandle hSrcResource; + NV_DECLARE_ALIGNED(NvP64 KernelCallbackdata, 8); +} NV_EVENT_BUFFER_BIND_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/cl90cdfecs.h b/userspace/sdks/nv570/inc/class/cl90cdfecs.h new file mode 100644 index 0000000..5118249 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl90cdfecs.h @@ -0,0 +1,112 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl90cdFecs_h_ +#define _cl90cdFecs_h_ + +/* This file defines parameters for FECS context switch events*/ + +#define NV_EVENT_BUFFER_FECS_VERSION 2 + +/* + * These are the types of context switch events + * This field gets added to NV_EVENT_BUFFER_FECS_RECORD to specify the sub type of fecs event + * Do *not* edit these as they are defined to maintain consistency with Tegra tools + */ +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_SO 0x00 +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_CTXSW_REQ_BY_HOST 0x01 +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_FE_ACK 0x02 +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_FE_ACK_WFI 0x0a +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_FE_ACK_GFXP 0x0b +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_FE_ACK_CTAP 0x0c +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_FE_ACK_CILP 0x0d +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_SAVE_END 0x03 +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_RESTORE_START 0x04 +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_CONTEXT_START 0x05 +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_SIMPLE_START 0x06 +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_SIMPLE_END 0x07 +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_ENGINE_RESET 0xfe +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_INVALID_TIMESTAMP 0xff +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_LAST NV_EVENT_BUFFER_FECS_EVENTS_CTXSWTAG_INVALID_TIMESTAMP + +/* + * Bit fields used to enable a particular sub type of event + */ +#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_SO NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_SO) +#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_CTXSW_REQ_BY_HOST NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_CTXSW_REQ_BY_HOST) +#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_FE_ACK NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_FE_ACK) +#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_SAVE_END NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_SAVE_END) +#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_RESTORE_START NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_RESTORE_START) +#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_CONTEXT_START NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_CONTEXT_START) +#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_SIMPLE_START NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_SIMPLE_START) +#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_SIMPLE_END NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_SIMPLE_END) + +/* context_id is set to this value if fecs info doesn't match a known channel/tsg handle*/ +#define NV_EVENT_BUFFER_INVALID_CONTEXT 0xFFFFFFFF + +/* + * PID/context_id are set to these values if the data is from another user's + * client and the current user is not an administrator + */ +#define NV_EVENT_BUFFER_HIDDEN_PID 0x0 +#define NV_EVENT_BUFFER_HIDDEN_CONTEXT 0x0 + +/* + * PID/context_id are set to these values if the data is from a kernel client + * and the data is being read by a user client + */ +#define NV_EVENT_BUFFER_KERNEL_PID 0xFFFFFFFF +#define NV_EVENT_BUFFER_KERNEL_CONTEXT 0xFFFFFFFF + +// V1 ------------------------------------------------------------------------ +typedef struct +{ + NvU8 tag; ///< NV_EVENT_BUFFER_FECS_CTXSWTAG_* + NvU8 vmid; + NvU16 seqno; ///< used to detect drop + NvU32 context_id; ///< channel/tsg handle + NvU64 pid NV_ALIGN_BYTES(8); ///< process id + NvU64 timestamp NV_ALIGN_BYTES(8); + /* Do *not* edit items above this to maintain consistency with tegra tools + Always add to the end of this structure to retain backward compatibility */ +} NV_EVENT_BUFFER_FECS_RECORD_V1; + +// V2 ------------------------------------------------------------------------ +typedef struct +{ + NvU8 tag; ///< NV_EVENT_BUFFER_FECS_CTXSWTAG_* + NvU8 vmid; + NvU16 seqno; ///< used to detect drop + NvU32 context_id; ///< channel/tsg handle + NvU32 pid; ///< process id + NvU16 reserved0; + NvU8 migGpuInstanceId; + NvU8 migComputeInstanceId; + NvU64 timestamp NV_ALIGN_BYTES(8); + /* Do *not* edit items above this to maintain consistency with tegra tools + Always add to the end of this structure to retain backward compatibility */ +} NV_EVENT_BUFFER_FECS_RECORD_V2; + +typedef NV_EVENT_BUFFER_FECS_RECORD_V1 NV_EVENT_BUFFER_FECS_RECORD_V0; +typedef NV_EVENT_BUFFER_FECS_RECORD_V1 NV_EVENT_BUFFER_FECS_RECORD; +#endif /* _cl90cdFecs_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl90cdtrace.h b/userspace/sdks/nv570/inc/class/cl90cdtrace.h new file mode 100644 index 0000000..f184719 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl90cdtrace.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl90cdtrace_h_ +#define _cl90cdtrace_h_ + +#include + +/* This file defines parameters for RATS/RM tracing */ + +typedef struct NV_RATS_GSP_TRACE_RECORD_V1 +{ + NvU16 seqNo; + NvU16 gspSeqNo; + NvU8 threadId; + NvU8 partitionId; + NvU16 reserved0; + NvU64 info; + NvU64 timeStamp; + NvU64 recordType; +} NV_RATS_GSP_TRACE_RECORD_V1; + +typedef NV_RATS_GSP_TRACE_RECORD_V1 NV_RATS_GSP_TRACE_RECORD; + +#define VGPU_TRACING_BUFFER_KEEP_OLDEST 0 +#define VGPU_TRACING_BUFFER_KEEP_NEWEST 1 + +typedef struct NV_RATS_VGPU_GSP_TRACING_BUFFER_V1{ + NvU8 policy; + + NvBool bGuestNotifInProgress; + + NvU16 seqNo; + NvU32 bufferSize; + NvU32 bufferWatermark; + NvU32 recordCount; + + NvU64 tracepointMask; + NvU32 read; + NvU32 write; + + NvU64 lastReadTimestamp; + + NV_RATS_GSP_TRACE_RECORD *buffer; +} NV_RATS_VGPU_GSP_TRACING_BUFFER_V1; + +typedef NV_RATS_VGPU_GSP_TRACING_BUFFER_V1 NV_RATS_VGPU_GSP_TRACING_BUFFER; + +#endif diff --git a/userspace/sdks/nv570/inc/class/cl90cdtypes.h b/userspace/sdks/nv570/inc/class/cl90cdtypes.h new file mode 100644 index 0000000..8190645 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl90cdtypes.h @@ -0,0 +1,49 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl90cdtypes_h_ +#define _cl90cdtypes_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Legacy values record type values have been kept for backward +// compatibility. New values should be added sequentially. +// +#define NV_EVENT_BUFFER_RECORD_TYPE_INVALID (0) +#define NV_EVENT_BUFFER_RECORD_TYPE_VIDEO_TRACE (1) +#define NV_EVENT_BUFFER_RECORD_TYPE_FECS_CTX_SWITCH_V2 (2) +#define NV_EVENT_BUFFER_RECORD_TYPE_NVTELEMETRY_REPORT_EVENT_SYSTEM (4) +#define NV_EVENT_BUFFER_RECORD_TYPE_RATS_GSP_TRACE (8) +#define NV_EVENT_BUFFER_RECORD_TYPE_NVTELEMETRY_REPORT_EVENT_SUBDEVICE (132) +#define NV_EVENT_BUFFER_RECORD_TYPE_FECS_CTX_SWITCH (134) +#define NV_EVENT_BUFFER_RECORD_TYPE_NOCAT_NOTIFY (16) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _cl90cdtypes_h_ + diff --git a/userspace/sdks/nv570/inc/class/cl90cdvideo.h b/userspace/sdks/nv570/inc/class/cl90cdvideo.h new file mode 100644 index 0000000..0d6f49f --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl90cdvideo.h @@ -0,0 +1,129 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl90cdvideo_h_ +#define _cl90cdvideo_h_ + +/* This file defines parameters for FECS context switch events*/ + +#define NV_EVENT_BUFFER_VIDEO_VERSION 1 + +#define NV_EVENT_BUFFER_VIDEO_TAG_ENGINE_START 0x00 +#define NV_EVENT_BUFFER_VIDEO_TAG_ENGINE_END 0x01 +#define NV_EVENT_BUFFER_VIDEO_TAG_PSTATE_CHANGE 0x02 +#define NV_EVENT_BUFFER_VIDEO_TAG_LOG_DATA 0x03 +#define NV_EVENT_BUFFER_VIDEO_TAG_LAST NV_EVENT_BUFFER_VIDEO_TAG_LOG_DATA + +#define NV_EVENT_BUFFER_VIDEO_BITMASK_TAG_ENGINE_START NVBIT(NV_EVENT_BUFFER_VIDEO_TAG_ENGINE_START) +#define NV_EVENT_BUFFER_VIDEO_BITMASK_TAG_ENGINE_END NVBIT(NV_EVENT_BUFFER_VIDEO_TAG_ENGINE_END) +#define NV_EVENT_BUFFER_VIDEO_BITMASK_TAG_PSTATE_CHANGE NVBIT(NV_EVENT_BUFFER_VIDEO_TAG_PSTATE_CHANGE) +#define NV_EVENT_BUFFER_VIDEO_BITMASK_TAG_LOG_DATA NVBIT(NV_EVENT_BUFFER_VIDEO_TAG_LOG_DATA) + +/* context_id is set to this value if fecs info doesn't match a known channel/tsg handle*/ +#define NV_EVENT_BUFFER_VIDEO_INVALID_CONTEXT 0xFFFFFFFF + +/* + * PID/context_id are set to these values if the data is from another user's + * client and the current user is not an administrator + */ +#define NV_EVENT_BUFFER_VIDEO_HIDDEN_PID 0x0 +#define NV_EVENT_BUFFER_VIDEO_HIDDEN_CONTEXT 0x0 + +/* + * PID/context_id are set to these values if the data is from a kernel client + * and the data is being read by a user client + */ +#define NV_EVENT_BUFFER_VIDEO_KERNEL_PID 0xFFFFFFFF +#define NV_EVENT_BUFFER_VIDEO_KERNEL_CONTEXT 0xFFFFFFFF + +typedef enum +{ + NV_EVENT_BUFFER_VIDEO_ENGINE_TYPE__NVDEC = 0, + NV_EVENT_BUFFER_VIDEO_ENGINE_TYPE__NVENC, + NV_EVENT_BUFFER_VIDEO_ENGINE_TYPE__NVJPEG, + NV_EVENT_BUFFER_VIDEO_ENGINE_TYPE__OFA, + NV_EVENT_BUFFER_VIDEO_ENGINE_TYPE__LAST = NV_EVENT_BUFFER_VIDEO_ENGINE_TYPE__OFA, +} NV_EVENT_BUFFER_VIDEO_ENGINE_TYPE; + +typedef enum +{ + NV_EVENT_BUFFER_VIDEO_CODEC_ID__MPEG2 = 0, + NV_EVENT_BUFFER_VIDEO_CODEC_ID__VC1, + NV_EVENT_BUFFER_VIDEO_CODEC_ID__H264, + NV_EVENT_BUFFER_VIDEO_CODEC_ID__MPEG4, + NV_EVENT_BUFFER_VIDEO_CODEC_ID__VP8, + NV_EVENT_BUFFER_VIDEO_CODEC_ID__VP9, + NV_EVENT_BUFFER_VIDEO_CODEC_ID__HEVC, + NV_EVENT_BUFFER_VIDEO_CODEC_ID__AVD, + NV_EVENT_BUFFER_VIDEO_CODEC_ID__LAST = NV_EVENT_BUFFER_VIDEO_CODEC_ID__AVD, +} NV_EVENT_BUFFER_VIDEO_ENGINE_CODEC_ID; + +typedef enum +{ + NV_EVENT_BUFFER_VIDEO_ENGINE_LOG_DATA_TYPE__GENERIC = 0, /* Generic opaque data */ + NV_EVENT_BUFFER_VIDEO_ENGINE_LOG_DATA_TYPE__STR, /* Log data can be interpreted as string */ + NV_EVENT_BUFFER_VIDEO_ENGINE_LOG_DATA_TYPE__BIN, /* Log data is binary data */ + NV_EVENT_BUFFER_VIDEO_ENGINE_LOG_DATA_TYPE__NUM +} NV_EVENT_BUFFER_VIDEO_ENGINE_LOG_DATA_TYPE; + +// V1 ------------------------------------------------------------------------ +typedef struct +{ + NvU8 event_id; ///< NV_EVENT_BUFFER_VIDEO_TAG_* + NvU8 vmid; + NvU16 seqno; + NvU32 context_id; ///< channel/tsg handle + NvU64 pid NV_ALIGN_BYTES(8); ///< process id + NvU64 timestamp NV_ALIGN_BYTES(8); + NvU64 api_id NV_ALIGN_BYTES(8); + union + { + NvU64 event_data; + + struct + { + NvU8 engine_type; + NvU8 engine_id; + NvU16 codec_id; + NvU32 status; + } session; + + struct + { + NvU16 from; + NvU16 to; + } stateChange; + + struct + { + NvU8 engine_type; + NvU8 engine_id; + NvU16 type; + NvU32 size; + } logData; + }; +} NV_EVENT_BUFFER_VIDEO_RECORD_V1; + +typedef NV_EVENT_BUFFER_VIDEO_RECORD_V1 NV_EVENT_BUFFER_VIDEO_RECORD; +#endif /* _cl90cdvideo_h_ */ + diff --git a/userspace/sdks/nv570/inc/class/cl90ce.h b/userspace/sdks/nv570/inc/class/cl90ce.h new file mode 100644 index 0000000..b4506df --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl90ce.h @@ -0,0 +1,42 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl90ce_h_ +#define _cl90ce_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* +* NV_MEMORY_DEVICELESS +* Memory that is not associated with a device +*/ +#define NV01_MEMORY_DEVICELESS (0x000090CE) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _cl90ce_h_ + diff --git a/userspace/sdks/nv570/inc/class/cl90e6.h b/userspace/sdks/nv570/inc/class/cl90e6.h new file mode 100644 index 0000000..63348ea --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl90e6.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl90e6_h_ +#define _cl90e6_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define GF100_SUBDEVICE_MASTER (0x000090e6) + +typedef struct { + NvU32 Reserved00[0x400]; /* NV_PMC 0x00000FFF:0x00000000 */ +} Nv90e6MapTypedef, GF100MASTERMap; + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl90e6_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl90e7.h b/userspace/sdks/nv570/inc/class/cl90e7.h new file mode 100644 index 0000000..3219f13 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl90e7.h @@ -0,0 +1,38 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl90e7_h_ +#define _cl90e7_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define GF100_SUBDEVICE_INFOROM (0x000090e7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _cl90e7_h + diff --git a/userspace/sdks/nv570/inc/class/cl90ec.h b/userspace/sdks/nv570/inc/class/cl90ec.h new file mode 100644 index 0000000..182640a --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl90ec.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl90ec_h_ +#define _cl90ec_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* Class within the subdevice used for communicating with HDACODEC*/ +#define GF100_HDACODEC (0x000090EC) + + /* pio method data structure */ +typedef volatile struct _cl90ec_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv90ECTypedef, GF100Hdacodec; +#define NV90EC_TYPEDEF GF100Hdacodec + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl9071_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cl90f1.h b/userspace/sdks/nv570/inc/class/cl90f1.h new file mode 100644 index 0000000..7523ef1 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl90f1.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _cl90f1_h_ +#define _cl90f1_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define FERMI_VASPACE_A (0x000090f1) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl90f1_h + diff --git a/userspace/sdks/nv570/inc/class/cl9170.h b/userspace/sdks/nv570/inc/class/cl9170.h new file mode 100644 index 0000000..64e520c --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl9170.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9170.finn +// + +#define NV9170_DISPLAY (0x9170U) /* finn: Evaluated from "NV9170_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV9170_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9170U) + +typedef struct NV9170_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numDacs; // Number of DACs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NV9170_ALLOCATION_PARAMETERS; diff --git a/userspace/sdks/nv570/inc/class/cl9171.h b/userspace/sdks/nv570/inc/class/cl9171.h new file mode 100644 index 0000000..731157a --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl9171.h @@ -0,0 +1,317 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl9171_h_ +#define _cl9171_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV9171_DISP_SF_USER 0x9171 + +typedef volatile struct _cl9171_tag0 { + NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x00690FFF:0x00690000 */ +} _Nv9171DispSfUser, Nv9171DispSfUserMap; + +#define NV9171_SF_HDMI_INFO_IDX_AVI_INFOFRAME 0x00000000 /* */ +#define NV9171_SF_HDMI_INFO_IDX_GENERIC_INFOFRAME 0x00000001 /* */ +#define NV9171_SF_HDMI_INFO_IDX_GCP 0x00000003 /* */ +#define NV9171_SF_HDMI_INFO_IDX_VSI 0x00000004 /* */ +#define NV9171_SF_HDMI_INFO_CTRL(i,j) (0x00690000-0x00690000+(i)*1024+(j)*64) /* RWX4A */ +#define NV9171_SF_HDMI_INFO_CTRL__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_INFO_CTRL__SIZE_2 5 /* */ +#define NV9171_SF_HDMI_INFO_CTRL_ENABLE 0:0 /* RWIVF */ +#define NV9171_SF_HDMI_INFO_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_INFO_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_OTHER 4:4 /* RWIVF */ +#define NV9171_SF_HDMI_INFO_CTRL_OTHER_DIS 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_INFO_CTRL_OTHER_EN 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_SINGLE 8:8 /* RWIVF */ +#define NV9171_SF_HDMI_INFO_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_INFO_CTRL_SINGLE_EN 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_CHKSUM_HW 9:9 /* RWIVF */ +#define NV9171_SF_HDMI_INFO_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_CHKSUM_HW_EN 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_CHKSUM_HW_DIS 0x00000000 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */ +#define NV9171_SF_HDMI_INFO_CTRL_HBLANK 12:12 /* RWIVF */ +#define NV9171_SF_HDMI_INFO_CTRL_HBLANK_DIS 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_INFO_CTRL_HBLANK_EN 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_VIDEO_FMT 16:16 /* RWIVF */ +#define NV9171_SF_HDMI_INFO_CTRL_VIDEO_FMT_SW_CONTROLLED 0x00000000 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_VIDEO_FMT_HW_CONTROLLED 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_VIDEO_FMT_INIT 0x00000001 /* RWI-V */ +#define NV9171_SF_HDMI_INFO_STATUS(i,j) (0x00690004-0x00690000+(i)*1024+(j)*64) /* R--4A */ +#define NV9171_SF_HDMI_INFO_STATUS__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_INFO_STATUS__SIZE_2 5 /* */ +#define NV9171_SF_HDMI_INFO_STATUS_SENT 0:0 /* R--VF */ +#define NV9171_SF_HDMI_INFO_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NV9171_SF_HDMI_INFO_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NV9171_SF_HDMI_INFO_STATUS_SENT_INIT 0x00000000 /* R-I-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x00690000-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER 4:4 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_DIS 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_EN 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE 8:8 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_EN 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW 9:9 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_STATUS(i) (0x00690004-0x00690000+(i)*1024) /* R--4A */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_STATUS_SENT 0:0 /* R--VF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT 0x00000000 /* R-I-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x00690008-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x0069000C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x00690010-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x00690014-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x00690018-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_HEADER(i) (0x00690048-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_HEADER__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_HEADER_HB0 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_HEADER_HB1 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_HEADER_HB2 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW(i) (0x0069004C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH(i) (0x00690050-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW(i) (0x00690054-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH(i) (0x00690058-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW(i) (0x0069005C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH(i) (0x00690060-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW(i) (0x00690064-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH(i) (0x00690068-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GCP_SUBPACK(i) (0x006900CC-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GCP_SUBPACK__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GCP_SUBPACK_SB0 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GCP_SUBPACK_SB0_INIT 0x00000001 /* RWI-V */ +#define NV9171_SF_HDMI_GCP_SUBPACK_SB0_SET_AVMUTE 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_GCP_SUBPACK_SB0_CLR_AVMUTE 0x00000010 /* RW--V */ +#define NV9171_SF_HDMI_GCP_SUBPACK_SB1 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GCP_SUBPACK_SB1_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GCP_SUBPACK_SB2 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GCP_SUBPACK_SB2_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_HEADER(i) (0x00690108-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_HEADER__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_HEADER_HB0 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_HEADER_HB1 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_HEADER_HB2 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW(i) (0x0069010C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH(i) (0x00690110-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW(i) (0x00690114-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH(i) (0x00690118-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW(i) (0x0069011C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH(i) (0x00690120-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW(i) (0x00690124-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB21 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB22 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB23 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB24 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH(i) (0x00690128-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _cl9171_h_ diff --git a/userspace/sdks/nv570/inc/class/cl917d.h b/userspace/sdks/nv570/inc/class/cl917d.h new file mode 100644 index 0000000..4f70d81 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cl917d.h @@ -0,0 +1,1551 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl917d_h_ +#define _cl917d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV917D_CORE_CHANNEL_DMA (0x0000917D) + +#define NV917D_CORE_NOTIFIER_3 0x00000000 +#define NV917D_CORE_NOTIFIER_3_SIZEOF 0x00000150 +#define NV917D_CORE_NOTIFIER_3_COMPLETION_0 0x00000000 +#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_DONE 0:0 +#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_R0 15:1 +#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP 29:16 +#define NV917D_CORE_NOTIFIER_3__1 0x00000001 +#define NV917D_CORE_NOTIFIER_3__1_R1 31:0 +#define NV917D_CORE_NOTIFIER_3__2 0x00000002 +#define NV917D_CORE_NOTIFIER_3__2_R2 31:0 +#define NV917D_CORE_NOTIFIER_3__3 0x00000003 +#define NV917D_CORE_NOTIFIER_3__3_R3 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_R0 19:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA 20:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_R1 29:21 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE 30:30 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5 0x00000005 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE 3:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE 11:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE 15:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE 19:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE 27:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE 31:28 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6 0x00000006 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE 3:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE 11:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE 15:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE 19:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE 27:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE 31:28 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_7 0x00000007 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_7_R4 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_8 0x00000008 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_8_R5 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_9 0x00000009 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_9_R6 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_10 0x0000000A +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_10_R7 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_11 0x0000000B +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_11_R8 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12 0x0000000C +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0 31:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13 0x0000000D +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14 0x0000000E +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0 31:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15 0x0000000F +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16 0x00000010 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0 31:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17 0x00000011 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18 0x00000012 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0 31:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19 0x00000013 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21 0x00000015 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22 0x00000016 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23 0x00000017 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24 0x00000018 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25 0x00000019 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26 0x0000001A +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27 0x0000001B +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28 0x0000001C +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29 0x0000001D +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30 0x0000001E +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31 0x0000001F +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32 0x00000020 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33 0x00000021 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34 0x00000022 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35 0x00000023 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36 0x00000024 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0 31:7 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37 0x00000025 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38 0x00000026 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0 31:7 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39 0x00000027 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40 0x00000028 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0 31:7 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41 0x00000029 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42 0x0000002A +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0 31:7 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43 0x0000002B +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44 0x0000002C +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45 0x0000002D +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45_R1 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46 0x0000002E +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47 0x0000002F +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47_R1 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48 0x00000030 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49 0x00000031 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49_R1 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50 0x00000032 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51 0x00000033 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51_R1 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52 0x00000034 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53 0x00000035 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54 0x00000036 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55 0x00000037 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56 0x00000038 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57 0x00000039 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58 0x0000003A +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59 0x0000003B +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60 0x0000003C +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61 0x0000003D +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62 0x0000003E +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63 0x0000003F +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64 0x00000040 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65 0x00000041 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66 0x00000042 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67 0x00000043 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68 0x00000044 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69 0x00000045 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70 0x00000046 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71 0x00000047 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72 0x00000048 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73 0x00000049 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74 0x0000004A +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75 0x0000004B +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76 0x0000004C +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77 0x0000004D +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78 0x0000004E +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79 0x0000004F +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80 0x00000050 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81 0x00000051 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82 0x00000052 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83 0x00000053 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10 31:0 + + +// dma opcode instructions +#define NV917D_DMA 0x00000000 +#define NV917D_DMA_OPCODE 31:29 +#define NV917D_DMA_OPCODE_METHOD 0x00000000 +#define NV917D_DMA_OPCODE_JUMP 0x00000001 +#define NV917D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV917D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV917D_DMA_OPCODE 31:29 +#define NV917D_DMA_OPCODE_METHOD 0x00000000 +#define NV917D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV917D_DMA_METHOD_COUNT 27:18 +#define NV917D_DMA_METHOD_OFFSET 11:2 +#define NV917D_DMA_DATA 31:0 +#define NV917D_DMA_DATA_NOP 0x00000000 +#define NV917D_DMA_OPCODE 31:29 +#define NV917D_DMA_OPCODE_JUMP 0x00000001 +#define NV917D_DMA_JUMP_OFFSET 11:2 +#define NV917D_DMA_OPCODE 31:29 +#define NV917D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV917D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV917D_PUT (0x00000000) +#define NV917D_PUT_PTR 11:2 +#define NV917D_GET (0x00000004) +#define NV917D_GET_PTR 11:2 +#define NV917D_UPDATE (0x00000080) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR(i) (0 +(i)*4):(0 +(i)*4) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1 4 +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0 +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR1 4:4 +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR2 8:8 +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR3 12:12 +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE(i) (1 +(i)*4):(1 +(i)*4) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1 4 +#define NV917D_UPDATE_INTERLOCK_WITH_BASE_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE0 1:1 +#define NV917D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE1 5:5 +#define NV917D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE2 9:9 +#define NV917D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE3 13:13 +#define NV917D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY(i) (2 +(i)*4):(2 +(i)*4) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1 4 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY1 6:6 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY2 10:10 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY3 14:14 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i) (3 +(i)*4):(3 +(i)*4) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1 4 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 7:7 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2 11:11 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3 15:15 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE (0x00000001) +#define NV917D_UPDATE_SPECIAL_HANDLING 25:24 +#define NV917D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV917D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV917D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV917D_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV917D_UPDATE_NOT_DRIVER_FRIENDLY 31:31 +#define NV917D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000) +#define NV917D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001) +#define NV917D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30 +#define NV917D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000) +#define NV917D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001) +#define NV917D_UPDATE_INHIBIT_INTERRUPTS 29:29 +#define NV917D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NV917D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NV917D_SET_NOTIFIER_CONTROL (0x00000084) +#define NV917D_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV917D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV917D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV917D_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV917D_SET_NOTIFIER_CONTROL_NOTIFY 31:31 +#define NV917D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NV917D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NV917D_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV917D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV917D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV917D_SET_CONTEXT_DMA_NOTIFIER (0x00000088) +#define NV917D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV917D_GET_CAPABILITIES (0x0000008C) +#define NV917D_GET_CAPABILITIES_DUMMY 31:0 +#define NV917D_SET_SPARE (0x0000016C) +#define NV917D_SET_SPARE_UNUSED 31:0 +#define NV917D_SET_SPARE_NOOP(b) (0x00000170 + (b)*0x00000004) +#define NV917D_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV917D_DAC_SET_CONTROL(a) (0x00000180 + (a)*0x00000020) +#define NV917D_DAC_SET_CONTROL_OWNER_MASK 3:0 +#define NV917D_DAC_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV917D_DAC_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV917D_DAC_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV917D_DAC_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV917D_DAC_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV917D_DAC_SET_CONTROL_PROTOCOL 12:8 +#define NV917D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV917D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT (0x00000013) +#define NV917D_DAC_SET_SW_SPARE_A(a) (0x00000184 + (a)*0x00000020) +#define NV917D_DAC_SET_SW_SPARE_A_CODE 31:0 +#define NV917D_DAC_SET_SW_SPARE_B(a) (0x00000188 + (a)*0x00000020) +#define NV917D_DAC_SET_SW_SPARE_B_CODE 31:0 +#define NV917D_DAC_SET_CUSTOM_REASON(a) (0x00000190 + (a)*0x00000020) +#define NV917D_DAC_SET_CUSTOM_REASON_CODE 31:0 + +#define NV917D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV917D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV917D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NV917D_SOR_SET_SW_SPARE_A(a) (0x00000204 + (a)*0x00000020) +#define NV917D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NV917D_SOR_SET_SW_SPARE_B(a) (0x00000208 + (a)*0x00000020) +#define NV917D_SOR_SET_SW_SPARE_B_CODE 31:0 +#define NV917D_SOR_SET_CUSTOM_REASON(a) (0x00000210 + (a)*0x00000020) +#define NV917D_SOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV917D_PIOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NV917D_PIOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV917D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV917D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV917D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV917D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV917D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV917D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV917D_PIOR_SET_SW_SPARE_A(a) (0x00000304 + (a)*0x00000020) +#define NV917D_PIOR_SET_SW_SPARE_A_CODE 31:0 +#define NV917D_PIOR_SET_SW_SPARE_B(a) (0x00000308 + (a)*0x00000020) +#define NV917D_PIOR_SET_SW_SPARE_B_CODE 31:0 +#define NV917D_PIOR_SET_CUSTOM_REASON(a) (0x00000310 + (a)*0x00000020) +#define NV917D_PIOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV917D_HEAD_SET_PRESENT_CONTROL(a) (0x00000400 + (a)*0x00000300) +#define NV917D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NV917D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 8:8 +#define NV917D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NV917D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NV917D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00000404 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 3:3 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 4:4 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 9:6 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000009) +#define NV917D_HEAD_SET_CONTROL(a) (0x00000408 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTROL_STRUCTURE 0:0 +#define NV917D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 3:2 +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 19:15 +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 7:4 +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 9:8 +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 14:10 +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK 1:1 +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_ENABLE (0x00000001) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN 24:20 +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN 29:25 +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000003) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000004) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000005) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000006) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000007) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000008) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x00000009) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000A) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000B) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000C) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000D) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000E) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x0000000F) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_UNSPECIFIED (0x00000010) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV917D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NV917D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NV917D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000410 + (a)*0x00000300) +#define NV917D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV917D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV917D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV917D_HEAD_SET_RASTER_SIZE(a) (0x00000414 + (a)*0x00000300) +#define NV917D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV917D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV917D_HEAD_SET_RASTER_SYNC_END(a) (0x00000418 + (a)*0x00000300) +#define NV917D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV917D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV917D_HEAD_SET_RASTER_BLANK_END(a) (0x0000041C + (a)*0x00000300) +#define NV917D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV917D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV917D_HEAD_SET_RASTER_BLANK_START(a) (0x00000420 + (a)*0x00000300) +#define NV917D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV917D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV917D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000424 + (a)*0x00000300) +#define NV917D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV917D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV917D_HEAD_SET_LOCK_CHAIN(a) (0x00000428 + (a)*0x00000300) +#define NV917D_HEAD_SET_LOCK_CHAIN_POSITION 27:24 +#define NV917D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000042C + (a)*0x00000300) +#define NV917D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV917D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV917D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV917D_HEAD_SET_CRC_CONTROL(a) (0x00000430 + (a)*0x00000300) +#define NV917D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 1:0 +#define NV917D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000000) +#define NV917D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_BASE (0x00000001) +#define NV917D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_OVERLAY (0x00000002) +#define NV917D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 2:2 +#define NV917D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NV917D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NV917D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE 3:3 +#define NV917D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_FALSE (0x00000000) +#define NV917D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_TRUE (0x00000001) +#define NV917D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE 4:4 +#define NV917D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_FALSE (0x00000000) +#define NV917D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_TRUE (0x00000001) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT 19:8 +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC__SIZE_1 4 +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC0 (0x00000FF0) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC1 (0x00000FF1) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC2 (0x00000FF2) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC3 (0x00000FF3) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG__SIZE_1 4 +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG0 (0x00000FF8) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG1 (0x00000FF9) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG2 (0x00000FFA) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG3 (0x00000FFB) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR__SIZE_1 8 +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR0 (0x00000F0F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR1 (0x00000F1F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR2 (0x00000F2F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR3 (0x00000F3F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR4 (0x00000F4F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR5 (0x00000F5F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR6 (0x00000F6F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR7 (0x00000F7F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF__SIZE_1 4 +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF0 (0x00000F8F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF1 (0x00000F9F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF2 (0x00000FAF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF3 (0x00000FBF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR__SIZE_1 8 +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR0 (0x000000FF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR1 (0x000001FF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR2 (0x000002FF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR3 (0x000003FF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR4 (0x000004FF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR5 (0x000005FF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR6 (0x000006FF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR7 (0x000007FF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_NONE (0x00000FFF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT 31:20 +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC__SIZE_1 4 +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC0 (0x00000FF0) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC1 (0x00000FF1) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC2 (0x00000FF2) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC3 (0x00000FF3) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG__SIZE_1 4 +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG0 (0x00000FF8) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG1 (0x00000FF9) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG2 (0x00000FFA) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG3 (0x00000FFB) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR__SIZE_1 8 +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR0 (0x00000F0F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR1 (0x00000F1F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR2 (0x00000F2F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR3 (0x00000F3F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR4 (0x00000F4F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR5 (0x00000F5F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR6 (0x00000F6F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR7 (0x00000F7F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF__SIZE_1 4 +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF0 (0x00000F8F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF1 (0x00000F9F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF2 (0x00000FAF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF3 (0x00000FBF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR__SIZE_1 8 +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR0 (0x000000FF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR1 (0x000001FF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR2 (0x000002FF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR3 (0x000003FF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR4 (0x000004FF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR5 (0x000005FF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR6 (0x000006FF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR7 (0x000007FF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_NONE (0x00000FFF) +#define NV917D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 5:5 +#define NV917D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC 6:6 +#define NV917D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_ENABLE (0x00000001) +#define NV917D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00000438 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NV917D_HEAD_SET_BASE_LUT_LO(a) (0x00000440 + (a)*0x00000300) +#define NV917D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV917D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE 27:24 +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV917D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV917D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_BASE_LUT_HI(a) (0x00000444 + (a)*0x00000300) +#define NV917D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV917D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000448 + (a)*0x00000300) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000044C + (a)*0x00000300) +#define NV917D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x00000450 + (a)*0x00000300) +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x00000454 + (a)*0x00000300) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE 21:20 +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25 (0x00000000) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28 (0x00000001) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM (0x00000002) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 24:24 +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING 25:25 +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE (0x00000000) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE (0x00000001) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 26:26 +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00000458 + (a)*0x00000300) +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NV917D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000045C + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV917D_HEAD_SET_OFFSET(a) (0x00000460 + (a)*0x00000300) +#define NV917D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV917D_HEAD_SET_SIZE(a) (0x00000468 + (a)*0x00000300) +#define NV917D_HEAD_SET_SIZE_WIDTH 15:0 +#define NV917D_HEAD_SET_SIZE_HEIGHT 31:16 +#define NV917D_HEAD_SET_STORAGE(a) (0x0000046C + (a)*0x00000300) +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV917D_HEAD_SET_STORAGE_PITCH 20:8 +#define NV917D_HEAD_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV917D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV917D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV917D_HEAD_SET_PARAMS(a) (0x00000470 + (a)*0x00000300) +#define NV917D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV917D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV917D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV917D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV917D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV917D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV917D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV917D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV917D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV917D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV917D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV917D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV917D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV917D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV917D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV917D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV917D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV917D_HEAD_SET_PARAMS_GAMMA 2:2 +#define NV917D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV917D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV917D_HEAD_SET_CONTEXT_DMAS_ISO(a) (0x00000474 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV917D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x0000047C + (a)*0x00000300) +#define NV917D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 1:0 +#define NV917D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NV917D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NV917D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_SPEC_FLIP (0x00000002) +#define NV917D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE 27:26 +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NV917D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 15:8 +#define NV917D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 23:16 +#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV917D_HEAD_SET_OFFSETS_CURSOR(a,b) (0x00000484 + (a)*0x00000300 + (b)*0x00000004) +#define NV917D_HEAD_SET_OFFSETS_CURSOR_ORIGIN 31:0 +#define NV917D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b) (0x0000048C + (a)*0x00000300 + (b)*0x00000004) +#define NV917D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE 31:0 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00000494 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422 8:8 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE (0x00000001) +#define NV917D_HEAD_SET_PROCAMP(a) (0x00000498 + (a)*0x00000300) +#define NV917D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV917D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV917D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV917D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV917D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV917D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV917D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV917D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV917D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV917D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 5:5 +#define NV917D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NV917D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NV917D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 6:6 +#define NV917D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) +#define NV917D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) +#define NV917D_HEAD_SET_DITHER_CONTROL(a) (0x000004A0 + (a)*0x00000300) +#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NV917D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV917D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x000004B0 + (a)*0x00000300) +#define NV917D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV917D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000004B8 + (a)*0x00000300) +#define NV917D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV917D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x000004BC + (a)*0x00000300) +#define NV917D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NV917D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000004C0 + (a)*0x00000300) +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000004C4 + (a)*0x00000300) +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a) (0x000004C8 + (a)*0x00000300) +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH 14:0 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT 30:16 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT 17:16 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257 (0x00000001) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025 (0x00000002) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT 21:20 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x000004D4 + (a)*0x00000300) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT 13:12 +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE (0x00000000) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257 (0x00000001) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025 (0x00000002) +#define NV917D_HEAD_SET_PROCESSING(a) (0x000004E0 + (a)*0x00000300) +#define NV917D_HEAD_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV917D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV917D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV917D_HEAD_SET_CONVERSION_RED(a) (0x000004E4 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONVERSION_RED_GAIN 15:0 +#define NV917D_HEAD_SET_CONVERSION_RED_OFS 31:16 +#define NV917D_HEAD_SET_CONVERSION_GRN(a) (0x000004E8 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONVERSION_GRN_GAIN 15:0 +#define NV917D_HEAD_SET_CONVERSION_GRN_OFS 31:16 +#define NV917D_HEAD_SET_CONVERSION_BLU(a) (0x000004EC + (a)*0x00000300) +#define NV917D_HEAD_SET_CONVERSION_BLU_GAIN 15:0 +#define NV917D_HEAD_SET_CONVERSION_BLU_OFS 31:16 +#define NV917D_HEAD_SET_CSC_RED2RED(a) (0x000004F0 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE 31:31 +#define NV917D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_CSC_RED2RED_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_GRN2RED(a) (0x000004F4 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_GRN2RED_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_BLU2RED(a) (0x000004F8 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_BLU2RED_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_CONSTANT2RED(a) (0x000004FC + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_RED2GRN(a) (0x00000500 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_RED2GRN_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_GRN2GRN(a) (0x00000504 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_BLU2GRN(a) (0x00000508 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_CONSTANT2GRN(a) (0x0000050C + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_RED2BLU(a) (0x00000510 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_RED2BLU_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_GRN2BLU(a) (0x00000514 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_BLU2BLU(a) (0x00000518 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_CONSTANT2BLU(a) (0x0000051C + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_CONSTANT2BLU_COEFF 18:0 +#define NV917D_HEAD_SET_HDMI_CTRL(a) (0x00000520 + (a)*0x00000300) +#define NV917D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NV917D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NV917D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NV917D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NV917D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE 15:12 +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000000) +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FIELD_ALTERNATIVE (0x00000001) +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_LINE_ALTERNATIVE (0x00000002) +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_FULL (0x00000003) +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH (0x00000004) +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH_GRAPHICS (0x00000005) +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_TOP_AND_BOTTOM (0x00000006) +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_HALF (0x00000008) +#define NV917D_HEAD_SET_VACTIVE_SPACE_COLOR(a) (0x00000524 + (a)*0x00000300) +#define NV917D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR 9:0 +#define NV917D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y 19:10 +#define NV917D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB 29:20 +#define NV917D_HEAD_SET_DISPLAY_ID(a,b) (0x0000052C + (a)*0x00000300 + (b)*0x00000004) +#define NV917D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NV917D_HEAD_SET_SW_SPARE_A(a) (0x0000054C + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NV917D_HEAD_SET_SW_SPARE_B(a) (0x00000550 + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NV917D_HEAD_SET_SW_SPARE_C(a) (0x00000554 + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NV917D_HEAD_SET_SW_SPARE_D(a) (0x00000558 + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NV917D_HEAD_SET_GET_BLANKING_CTRL(a) (0x0000055C + (a)*0x00000300) +#define NV917D_HEAD_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NV917D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NV917D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NV917D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NV917D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NV917D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a) (0x000006D0 + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED 31:0 +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a) (0x000006D4 + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED 31:0 +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a) (0x000006D8 + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED 31:0 +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a) (0x000006DC + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED 31:0 +#define NV917D_HEAD_SET_SPARE(a) (0x000006EC + (a)*0x00000300) +#define NV917D_HEAD_SET_SPARE_UNUSED 31:0 +#define NV917D_HEAD_SET_SPARE_NOOP(a,b) (0x000006F0 + (a)*0x00000300 + (b)*0x00000004) +#define NV917D_HEAD_SET_SPARE_NOOP_UNUSED 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl917d_h diff --git a/userspace/sdks/nv570/inc/class/cla06c.h b/userspace/sdks/nv570/inc/class/cla06c.h new file mode 100644 index 0000000..0b4f5c9 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cla06c.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _cla06c_h_ +#define _cla06c_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define KEPLER_CHANNEL_GROUP_A (0x0000A06C) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cla06c_h + diff --git a/userspace/sdks/nv570/inc/class/cla06f.h b/userspace/sdks/nv570/inc/class/cla06f.h new file mode 100644 index 0000000..336cab5 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cla06f.h @@ -0,0 +1,240 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clA06f_h_ +#define _clA06f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class KEPLER_CHANNEL_GPFIFO */ +/* + * Documentation for KEPLER_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + */ +#define KEPLER_CHANNEL_GPFIFO_A (0x0000A06F) + + +/* pio method data structure */ +typedef volatile struct _cla06f_tag0 { + NvV32 Reserved00[0x7c0]; +} NvA06FTypedef, KEPLER_ChannelGPFifo; +#define NVA06F_TYPEDEF KEPLER_CHANNELChannelGPFifo +/* dma flow control data structure */ +typedef volatile struct _cla06f_tag1 { + NvU32 Ignored00[0x010]; /* 0000-0043*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} NvA06FControl, KeplerAControlGPFifo; +/* fields and values */ +#define NVA06F_NUMBER_OF_SUBCHANNELS (8) +#define NVA06F_SET_OBJECT (0x00000000) +#define NVA06F_SET_OBJECT_NVCLASS 15:0 +#define NVA06F_SET_OBJECT_ENGINE 20:16 +#define NVA06F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVA06F_ILLEGAL (0x00000004) +#define NVA06F_ILLEGAL_HANDLE 31:0 +#define NVA06F_NOP (0x00000008) +#define NVA06F_NOP_HANDLE 31:0 +#define NVA06F_SEMAPHOREA (0x00000010) +#define NVA06F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVA06F_SEMAPHOREB (0x00000014) +#define NVA06F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVA06F_SEMAPHOREC (0x00000018) +#define NVA06F_SEMAPHOREC_PAYLOAD 31:0 +#define NVA06F_SEMAPHORED (0x0000001C) +#define NVA06F_SEMAPHORED_OPERATION 3:0 +#define NVA06F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVA06F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVA06F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVA06F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVA06F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVA06F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVA06F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVA06F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVA06F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVA06F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVA06F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVA06F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVA06F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVA06F_NON_STALL_INTERRUPT (0x00000020) +#define NVA06F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVA06F_FB_FLUSH (0x00000024) +#define NVA06F_FB_FLUSH_HANDLE 31:0 +#define NVA06F_MEM_OP_A (0x00000028) +#define NVA06F_MEM_OP_A_OPERAND_LOW 31:2 +#define NVA06F_MEM_OP_A_TLB_INVALIDATE_ADDR 29:2 +#define NVA06F_MEM_OP_A_TLB_INVALIDATE_TARGET 31:30 +#define NVA06F_MEM_OP_A_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000 +#define NVA06F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002 +#define NVA06F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 +#define NVA06F_MEM_OP_B (0x0000002c) +#define NVA06F_MEM_OP_B_OPERAND_HIGH 7:0 +#define NVA06F_MEM_OP_B_OPERATION 31:27 +#define NVA06F_MEM_OP_B_OPERATION_SYSMEMBAR_FLUSH 0x00000005 +#define NVA06F_MEM_OP_B_OPERATION_SOFT_FLUSH 0x00000006 +#define NVA06F_MEM_OP_B_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVA06F_MEM_OP_B_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NVA06F_MEM_OP_B_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +#define NVA06F_MEM_OP_B_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVA06F_MEM_OP_B_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB 0:0 +#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ALL 0x00000001 +#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC 1:1 +#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVA06F_SET_REFERENCE (0x00000050) +#define NVA06F_SET_REFERENCE_COUNT 31:0 +#define NVA06F_CRC_CHECK (0x0000007c) +#define NVA06F_CRC_CHECK_VALUE 31:0 +#define NVA06F_YIELD (0x00000080) +#define NVA06F_YIELD_OP 1:0 +#define NVA06F_YIELD_OP_NOP 0x00000000 + + +/* GPFIFO entry format */ +#define NVA06F_GP_ENTRY__SIZE 8 +#define NVA06F_GP_ENTRY0_FETCH 0:0 +#define NVA06F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVA06F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVA06F_GP_ENTRY0_GET 31:2 +#define NVA06F_GP_ENTRY0_OPERAND 31:0 +#define NVA06F_GP_ENTRY1_GET_HI 7:0 +#define NVA06F_GP_ENTRY1_PRIV 8:8 +#define NVA06F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NVA06F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NVA06F_GP_ENTRY1_LEVEL 9:9 +#define NVA06F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVA06F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVA06F_GP_ENTRY1_LENGTH 30:10 +#define NVA06F_GP_ENTRY1_SYNC 31:31 +#define NVA06F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVA06F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVA06F_GP_ENTRY1_OPCODE 7:0 +#define NVA06F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVA06F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVA06F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVA06F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVA06F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVA06F_DMA_METHOD_ADDRESS 11:0 +#define NVA06F_DMA_SUBDEVICE_MASK 15:4 +#define NVA06F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVA06F_DMA_TERT_OP 17:16 +#define NVA06F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVA06F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVA06F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVA06F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVA06F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVA06F_DMA_METHOD_COUNT_OLD 28:18 +#define NVA06F_DMA_METHOD_COUNT 28:16 +#define NVA06F_DMA_IMMD_DATA 28:16 +#define NVA06F_DMA_SEC_OP 31:29 +#define NVA06F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVA06F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVA06F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVA06F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVA06F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVA06F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVA06F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVA06F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVA06F_DMA_INCR_ADDRESS 11:0 +#define NVA06F_DMA_INCR_SUBCHANNEL 15:13 +#define NVA06F_DMA_INCR_COUNT 28:16 +#define NVA06F_DMA_INCR_OPCODE 31:29 +#define NVA06F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVA06F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVA06F_DMA_NONINCR_ADDRESS 11:0 +#define NVA06F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVA06F_DMA_NONINCR_COUNT 28:16 +#define NVA06F_DMA_NONINCR_OPCODE 31:29 +#define NVA06F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVA06F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVA06F_DMA_ONEINCR_ADDRESS 11:0 +#define NVA06F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVA06F_DMA_ONEINCR_COUNT 28:16 +#define NVA06F_DMA_ONEINCR_OPCODE 31:29 +#define NVA06F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVA06F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVA06F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVA06F_DMA_IMMD_ADDRESS 11:0 +#define NVA06F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVA06F_DMA_IMMD_DATA 28:16 +#define NVA06F_DMA_IMMD_OPCODE 31:29 +#define NVA06F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVA06F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVA06F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA06F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVA06F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVA06F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA06F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVA06F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA06F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVA06F_DMA_ENDSEG_OPCODE 31:29 +#define NVA06F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVA06F_DMA_ADDRESS 12:2 +#define NVA06F_DMA_SUBCH 15:13 +#define NVA06F_DMA_OPCODE3 17:16 +#define NVA06F_DMA_OPCODE3_NONE (0x00000000) +#define NVA06F_DMA_COUNT 28:18 +#define NVA06F_DMA_OPCODE 31:29 +#define NVA06F_DMA_OPCODE_METHOD (0x00000000) +#define NVA06F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVA06F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clA06F_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cla06fsubch.h b/userspace/sdks/nv570/inc/class/cla06fsubch.h new file mode 100644 index 0000000..330a681 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cla06fsubch.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cla06fsubch_h_ +#define _cla06fsubch_h_ + +#define NVA06F_SUBCHANNEL_2D 3 +#define NVA06F_SUBCHANNEL_3D 0 +#define NVA06F_SUBCHANNEL_COMPUTE 1 +#define NVA06F_SUBCHANNEL_COPY_ENGINE 4 +#define NVA06F_SUBCHANNEL_I2M 2 + +#endif // _cla06fsubch_h_ diff --git a/userspace/sdks/nv570/inc/class/cla06fsw.h b/userspace/sdks/nv570/inc/class/cla06fsw.h new file mode 100644 index 0000000..99c3b8a --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cla06fsw.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cla06f_sw_h_ +#define _cla06f_sw_h_ + +#define NVA06F_NOTIFIERS_RC (0) +#define NVA06F_NOTIFIERS_REFCNT (1) +#define NVA06F_NOTIFIERS_NONSTALL (2) +#define NVA06F_NOTIFIERS_EVENTBUFFER (3) +#define NVA06F_NOTIFIERS_IDLECHANNEL (4) +#define NVA06F_NOTIFIERS_ENDCTX (5) +#define NVA06F_NOTIFIERS_SW (6) +#define NVA06F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVA06F_NOTIFIERS_MAXCOUNT (8) + +/* NvNotification[] fields and values */ +#define NVA06F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVA06F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _cla06f_sw_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cla080.h b/userspace/sdks/nv570/inc/class/cla080.h new file mode 100644 index 0000000..95bbf1d --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cla080.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cla080.finn +// + +#define KEPLER_DEVICE_VGPU 0x0000a080U + diff --git a/userspace/sdks/nv570/inc/class/cla081.h b/userspace/sdks/nv570/inc/class/cla081.h new file mode 100644 index 0000000..d17271a --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cla081.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cla081_h_ +#define _cla081_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVA081_VGPU_CONFIG (0x0000a081) + +/*event values*/ +#define NVA081_NOTIFIERS_EVENT_VGPU_GUEST_CREATED (0) +#define NVA081_NOTIFIERS_EVENT_VGPU_GUEST_INITIALISING (1) +#define NVA081_NOTIFIERS_EVENT_VGPU_GUEST_DESTROYED (2) +#define NVA081_NOTIFIERS_MAXCOUNT (5) + + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cla081_h diff --git a/userspace/sdks/nv570/inc/class/cla083.h b/userspace/sdks/nv570/inc/class/cla083.h new file mode 100644 index 0000000..4bff2e4 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cla083.h @@ -0,0 +1,36 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cla083_h_ +#define _cla083_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVA083_GRID_DISPLAYLESS (0x0000a083) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cla083_h diff --git a/userspace/sdks/nv570/inc/class/cla084.h b/userspace/sdks/nv570/inc/class/cla084.h new file mode 100644 index 0000000..a3c9346 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cla084.h @@ -0,0 +1,82 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cla084.finn +// + +#include "nv_vgpu_types.h" +#include "cla084_notification.h" + +#define NVA084_KERNEL_HOST_VGPU_DEVICE (0xa084U) /* finn: Evaluated from "NVA084_ALLOC_PARAMETERS_MESSAGE_ID" */ + +#define NVA084_MAX_VMMU_SEGMENTS 384 + +/* + * NVA084_ALLOC_PARAMETERS + * + * This structure represents vGPU host device KERNEL object allocation parameters. + * dbdf -> domain (31:16), bus (15:8), device (7:3), function (2:0) + * gfid -> Used only when SRIOV is enabled otherwise set to 0. + * swizzId [IN] -> Used only when MIG mode is enabled otherwise set + * to NV2080_CTRL_GPU_PARTITION_ID_INVALID. + * numChannels -> Used only when SRIOV is enabled. Must be a power of 2. + * placementId [IN] -> Used to provide placement ID of with heterogeneous timesliced vGPUs. + * Otherwise set to NVA081_PLACEMENT_ID_INVALID. + * bDisableDefaultSmcExecPartRestore - If set to true, SMC default execution partition + * save/restore will not be done in host-RM + * vgpuDeviceInstanceId -> Specifies the vGPU device instance per VM to be used + * for supporting multiple vGPUs per VM. + * hPluginClient -> handle to the plugin client + * numGuestFbHandles -> number of guest memory handles, the client handle is hPluginClient + * guestFbHandleList -> handle list to guest memory + * hPluginHeapMemory -> plugin heap memory handle, the client handle is hPluginClient + * hMigRmHeapMemory -> MIG-RM heap memory handle + * bDeviceProfilingEnabled -> If set to true, profiling is allowed + * bGpupLiveMigrationEnabled -> True if GPUP LM is supported + */ +#define NVA084_ALLOC_PARAMETERS_MESSAGE_ID (0xa084U) + +typedef struct NVA084_ALLOC_PARAMETERS { + NvU32 dbdf; + NvU32 gfid; + NvU32 swizzId; + NvU32 vgpuType; + NvU32 vmPid; + NvU32 accountingPid; + NvU32 numChannels; + NvU32 numPluginChannels; + NvU16 placementId; + VM_ID_TYPE vmIdType; + NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); + NvBool bDisableDefaultSmcExecPartRestore; + NvU32 vgpuDeviceInstanceId; + NvHandle hPluginClient; + NvU8 vgpuDevName[VM_UUID_SIZE]; + NvBool bGpupLiveMigrationEnabled; +} NVA084_ALLOC_PARAMETERS; diff --git a/userspace/sdks/nv570/inc/class/cla084_notification.h b/userspace/sdks/nv570/inc/class/cla084_notification.h new file mode 100644 index 0000000..d83ea89 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cla084_notification.h @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cla084_notification_h_ +#define _cla084_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +// +// @todo: We will define the actual event values later based on the use case. +// These event values are only for Test purpose. +// +/* event values */ +#define NVA084_NOTIFIERS_EVENT_VGPU_PLUGIN_TASK_BOOTLOADED (0) +#define NVA084_NOTIFIERS_EVENT_VGPU_PLUGIN_TASK_UNLOADED (1) +#define NVA084_NOTIFIERS_EVENT_VGPU_PLUGIN_TASK_CRASHED (2) +#define NVA084_NOTIFIERS_EVENT_GUEST_DRIVER_LOADED (3) +#define NVA084_NOTIFIERS_EVENT_GUEST_DRIVER_UNLOADED (4) +#define NVA084_NOTIFIERS_EVENT_PRINT_ERROR_MESSAGE (5) +#define NVA084_NOTIFIERS_EVENT_GUEST_LICENSE_STATE_CHANGED (6) +#define NVA084_NOTIFIERS_EVENT_UPDATE_GUEST_OS_TYPE (7) +#define NVA084_NOTIFIERS_EVENT_PRINT_GUEST_RPC_TRACE_LOG_MESSAGE (8) +#define NVA084_NOTIFIERS_EVENT_INIT_GR_ENGINE (9) +#define NVA084_NOTIFIERS_MAXCOUNT (10) + +#define NVA084_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NVA084_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000) +#define NVA084_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000) +#define NVA084_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000) +#define NVA084_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cla084_notification_h_ diff --git a/userspace/sdks/nv570/inc/class/cla097.h b/userspace/sdks/nv570/inc/class/cla097.h new file mode 100644 index 0000000..9ebbcfd --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cla097.h @@ -0,0 +1,3817 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_kepler_a_h_ +#define _cl_kepler_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl kepler_a */ + +#include "nvtypes.h" + +#define KEPLER_A 0xA097 + +#define NVA097_SET_OBJECT 0x0000 +#define NVA097_SET_OBJECT_CLASS_ID 15:0 +#define NVA097_SET_OBJECT_ENGINE_ID 20:16 + +#define NVA097_NO_OPERATION 0x0100 +#define NVA097_NO_OPERATION_V 31:0 + +#define NVA097_SET_NOTIFY_A 0x0104 +#define NVA097_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVA097_SET_NOTIFY_B 0x0108 +#define NVA097_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVA097_NOTIFY 0x010c +#define NVA097_NOTIFY_TYPE 31:0 +#define NVA097_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVA097_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVA097_WAIT_FOR_IDLE 0x0110 +#define NVA097_WAIT_FOR_IDLE_V 31:0 + +#define NVA097_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVA097_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVA097_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVA097_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVA097_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVA097_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVA097_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVA097_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVA097_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVA097_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVA097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVA097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVA097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVA097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVA097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVA097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVA097_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVA097_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVA097_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA097_SEND_GO_IDLE 0x013c +#define NVA097_SEND_GO_IDLE_V 31:0 + +#define NVA097_PM_TRIGGER 0x0140 +#define NVA097_PM_TRIGGER_V 31:0 + +#define NVA097_PM_TRIGGER_WFI 0x0144 +#define NVA097_PM_TRIGGER_WFI_V 31:0 + +#define NVA097_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVA097_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVA097_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVA097_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVA097_LINE_LENGTH_IN 0x0180 +#define NVA097_LINE_LENGTH_IN_VALUE 31:0 + +#define NVA097_LINE_COUNT 0x0184 +#define NVA097_LINE_COUNT_VALUE 31:0 + +#define NVA097_OFFSET_OUT_UPPER 0x0188 +#define NVA097_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVA097_OFFSET_OUT 0x018c +#define NVA097_OFFSET_OUT_VALUE 31:0 + +#define NVA097_PITCH_OUT 0x0190 +#define NVA097_PITCH_OUT_VALUE 31:0 + +#define NVA097_SET_DST_BLOCK_SIZE 0x0194 +#define NVA097_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVA097_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVA097_SET_DST_WIDTH 0x0198 +#define NVA097_SET_DST_WIDTH_V 31:0 + +#define NVA097_SET_DST_HEIGHT 0x019c +#define NVA097_SET_DST_HEIGHT_V 31:0 + +#define NVA097_SET_DST_DEPTH 0x01a0 +#define NVA097_SET_DST_DEPTH_V 31:0 + +#define NVA097_SET_DST_LAYER 0x01a4 +#define NVA097_SET_DST_LAYER_V 31:0 + +#define NVA097_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVA097_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVA097_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVA097_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVA097_LAUNCH_DMA 0x01b0 +#define NVA097_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVA097_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA097_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA097_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVA097_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVA097_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVA097_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVA097_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVA097_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVA097_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVA097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVA097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVA097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVA097_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVA097_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA097_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA097_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA097_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVA097_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA097_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA097_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVA097_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVA097_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVA097_LOAD_INLINE_DATA 0x01b4 +#define NVA097_LOAD_INLINE_DATA_V 31:0 + +#define NVA097_SET_I2M_SEMAPHORE_A 0x01dc +#define NVA097_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVA097_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVA097_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA097_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVA097_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVA097_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVA097_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVA097_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVA097_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVA097_SET_I2M_SPARE_NOOP03 0x01fc +#define NVA097_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVA097_RUN_DS_NOW 0x0200 +#define NVA097_RUN_DS_NOW_V 31:0 + +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVA097_SET_RASTER_PIPE_SYNC_CONTROL 0x0208 +#define NVA097_SET_RASTER_PIPE_SYNC_CONTROL_PRIM_AREA_THRESHOLD 21:0 +#define NVA097_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE 24:24 +#define NVA097_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE_FALSE 0x00000000 +#define NVA097_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVA097_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVA097_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVA097_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVA097_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVA097_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_GS_DM_FIFO 0x0214 +#define NVA097_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVA097_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVA097_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVA097_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVA097_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA097_INVALIDATE_SHADER_CACHES 0x021c +#define NVA097_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVA097_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVA097_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVA097_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVA097_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVA097_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVA097_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVA097_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVA097_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVA097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVA097_SET_VAB_VERTEX3F(i) (0x0220+(i)*4) +#define NVA097_SET_VAB_VERTEX3F_V 31:0 + +#define NVA097_SET_VAB_VERTEX4F(i) (0x0230+(i)*4) +#define NVA097_SET_VAB_VERTEX4F_V 31:0 + +#define NVA097_SET_VAB_NORMAL3F(i) (0x0240+(i)*4) +#define NVA097_SET_VAB_NORMAL3F_V 31:0 + +#define NVA097_SET_VAB_COLOR3F(i) (0x0250+(i)*4) +#define NVA097_SET_VAB_COLOR3F_V 31:0 + +#define NVA097_SET_VAB_COLOR4F(i) (0x0260+(i)*4) +#define NVA097_SET_VAB_COLOR4F_V 31:0 + +#define NVA097_SET_VAB_COLOR4UB(i) (0x0270+(i)*4) +#define NVA097_SET_VAB_COLOR4UB_V 31:0 + +#define NVA097_SET_VAB_TEX_COORD1F(i) (0x0280+(i)*4) +#define NVA097_SET_VAB_TEX_COORD1F_V 31:0 + +#define NVA097_SET_VAB_TEX_COORD2F(i) (0x0290+(i)*4) +#define NVA097_SET_VAB_TEX_COORD2F_V 31:0 + +#define NVA097_SET_VAB_TEX_COORD3F(i) (0x02a0+(i)*4) +#define NVA097_SET_VAB_TEX_COORD3F_V 31:0 + +#define NVA097_SET_VAB_TEX_COORD4F(i) (0x02b0+(i)*4) +#define NVA097_SET_VAB_TEX_COORD4F_V 31:0 + +#define NVA097_SET_TASK_CIRCULAR_BUFFER_THROTTLE 0x02cc +#define NVA097_SET_TASK_CIRCULAR_BUFFER_THROTTLE_TASK_COUNT 21:0 + +#define NVA097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NVA097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NVA097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVA097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVA097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVA097_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 9:0 + +#define NVA097_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVA097_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVA097_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVA097_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVA097_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVA097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVA097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVA097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVA097_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVA097_SET_ZCULL_SUBREGION 0x02e8 +#define NVA097_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVA097_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVA097_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVA097_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVA097_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVA097_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVA097_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVA097_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVA097_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVA097_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVA097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVA097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVA097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVA097_DRAW_ZERO_INDEX 0x0304 +#define NVA097_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVA097_SET_L1_CONFIGURATION 0x0308 +#define NVA097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVA097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVA097_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVA097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVA097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVA097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVA097_SET_SPA_VERSION 0x0310 +#define NVA097_SET_SPA_VERSION_MINOR 7:0 +#define NVA097_SET_SPA_VERSION_MAJOR 15:8 + +#define NVA097_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NVA097_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NVA097_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_SNAP_GRID_LINE 0x0318 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVA097_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVA097_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVA097_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVA097_SET_SNAP_GRID_NON_LINE 0x031c +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVA097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVA097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVA097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVA097_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVA097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVA097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVA097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVA097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVA097_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVA097_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVA097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVA097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVA097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVA097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVA097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVA097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVA097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVA097_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVA097_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVA097_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVA097_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVA097_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVA097_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVA097_SET_TESSELLATION_LOD_V1 0x0330 +#define NVA097_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVA097_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVA097_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVA097_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVA097_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVA097_RESERVED_TG07 0x033c +#define NVA097_RESERVED_TG07_V 0:0 + +#define NVA097_RESERVED_TG08 0x0340 +#define NVA097_RESERVED_TG08_V 0:0 + +#define NVA097_RESERVED_TG09 0x0344 +#define NVA097_RESERVED_TG09_V 0:0 + +#define NVA097_RESERVED_TG10 0x0348 +#define NVA097_RESERVED_TG10_V 0:0 + +#define NVA097_RESERVED_TG11 0x034c +#define NVA097_RESERVED_TG11_V 0:0 + +#define NVA097_RESERVED_TG12 0x0350 +#define NVA097_RESERVED_TG12_V 0:0 + +#define NVA097_RESERVED_TG13 0x0354 +#define NVA097_RESERVED_TG13_V 0:0 + +#define NVA097_RESERVED_TG14 0x0358 +#define NVA097_RESERVED_TG14_V 0:0 + +#define NVA097_RESERVED_TG15 0x035c +#define NVA097_RESERVED_TG15_V 0:0 + +#define NVA097_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVA097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVA097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVA097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVA097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVA097_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVA097_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVA097_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVA097_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVA097_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVA097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVA097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVA097_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVA097_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVA097_SET_RASTER_ENABLE 0x037c +#define NVA097_SET_RASTER_ENABLE_V 0:0 +#define NVA097_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVA097_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVA097_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVA097_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVA097_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVA097_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVA097_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVA097_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVA097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVA097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVA097_SET_VAB_DATA_TYPELESS(i) (0x0400+(i)*4) +#define NVA097_SET_VAB_DATA_TYPELESS_V 31:0 + +#define NVA097_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVA097_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVA097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVA097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVA097_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVA097_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVA097_SET_RASTER_INPUT 0x0740 +#define NVA097_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVA097_SET_STREAM_OUTPUT 0x0744 +#define NVA097_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVA097_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVA097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVA097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_ALPHA_FRACTION 0x074c +#define NVA097_SET_ALPHA_FRACTION_V 7:0 + +#define NVA097_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVA097_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVA097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVA097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVA097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 + +#define NVA097_SET_MAX_TI_WARPS_PER_BATCH 0x075c +#define NVA097_SET_MAX_TI_WARPS_PER_BATCH_V 5:0 + +#define NVA097_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVA097_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA097_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVA097_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVA097_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVA097_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVA097_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVA097_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVA097_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVA097_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVA097_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVA097_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVA097_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVA097_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVA097_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVA097_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVA097_SET_ISBE_SAVE_RESTORE_PROGRAM 0x07ac +#define NVA097_SET_ISBE_SAVE_RESTORE_PROGRAM_OFFSET 31:0 + +#define NVA097_SET_VAB_VERTEX2F(i) (0x07b0+(i)*4) +#define NVA097_SET_VAB_VERTEX2F_V 31:0 + +#define NVA097_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVA097_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVA097_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVA097_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVA097_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVA097_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVA097_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVA097_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVA097_SET_CULL_BEFORE_FETCH 0x07dc +#define NVA097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVA097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVA097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVA097_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVA097_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVA097_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVA097_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVA097_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVA097_SET_ZCULL_STORAGE_A 0x07e8 +#define NVA097_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVA097_SET_ZCULL_STORAGE_B 0x07ec +#define NVA097_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVA097_SET_ZCULL_STORAGE_C 0x07f0 +#define NVA097_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVA097_SET_ZCULL_STORAGE_D 0x07f4 +#define NVA097_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVA097_SET_ZT_READ_ONLY 0x07f8 +#define NVA097_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVA097_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVA097_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVA097_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVA097_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVA097_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVA097_SET_TEXTURE_INSTRUCTION_OPERAND 0x07fc +#define NVA097_SET_TEXTURE_INSTRUCTION_OPERAND_ORDERING 0:0 +#define NVA097_SET_TEXTURE_INSTRUCTION_OPERAND_ORDERING_FERMI_ORDER 0x00000000 +#define NVA097_SET_TEXTURE_INSTRUCTION_OPERAND_ORDERING_KEPLER_ORDER 0x00000001 + +#define NVA097_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVA097_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVA097_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVA097_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVA097_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVA097_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVA097_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVA097_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVA097_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVA097_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVA097_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVA097_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVA097_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVA097_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVA097_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVA097_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVA097_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVA097_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVA097_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA097_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVA097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVA097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVA097_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVA097_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVA097_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVA097_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVA097_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVA097_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVA097_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NVA097_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NVA097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVA097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVA097_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVA097_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVA097_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVA097_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVA097_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVA097_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVA097_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVA097_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVA097_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVA097_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVA097_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVA097_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVA097_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVA097_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVA097_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVA097_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVA097_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVA097_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVA097_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVA097_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVA097_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVA097_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVA097_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVA097_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVA097_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVA097_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVA097_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVA097_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVA097_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVA097_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVA097_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVA097_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVA097_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVA097_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVA097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVA097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVA097_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVA097_SET_STATISTICS_COUNTER 0x0d68 +#define NVA097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVA097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVA097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVA097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVA097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVA097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVA097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVA097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVA097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVA097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVA097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVA097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVA097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVA097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVA097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVA097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVA097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVA097_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVA097_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVA097_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVA097_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVA097_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVA097_SET_VERTEX_ARRAY_START 0x0d74 +#define NVA097_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVA097_DRAW_VERTEX_ARRAY 0x0d78 +#define NVA097_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVA097_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVA097_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVA097_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVA097_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVA097_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVA097_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVA097_SET_Z_CLEAR_VALUE 0x0d90 +#define NVA097_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVA097_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVA097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVA097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVA097_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVA097_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVA097_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVA097_SET_FRONT_POLYGON_MODE 0x0dac +#define NVA097_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVA097_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVA097_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVA097_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVA097_SET_BACK_POLYGON_MODE 0x0db0 +#define NVA097_SET_BACK_POLYGON_MODE_V 31:0 +#define NVA097_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVA097_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVA097_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVA097_SET_POLY_SMOOTH 0x0db4 +#define NVA097_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVA097_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVA097_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_ZT_MARK 0x0db8 +#define NVA097_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NVA097_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVA097_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVA097_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVA097_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVA097_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVA097_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVA097_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVA097_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVA097_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVA097_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVA097_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVA097_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_PATCH 0x0dcc +#define NVA097_SET_PATCH_SIZE 7:0 + +#define NVA097_SET_ZCULL_CRITERION 0x0dd8 +#define NVA097_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVA097_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVA097_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVA097_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVA097_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVA097_SET_ZCULL_CRITERION_SREF 23:16 +#define NVA097_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVA097_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVA097_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVA097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVA097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVA097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE 0x0dec +#define NVA097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE 0:0 +#define NVA097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_WINDOW_OFFSET_X 0x0df8 +#define NVA097_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVA097_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVA097_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVA097_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVA097_SET_SCISSOR_ENABLE_V 0:0 +#define NVA097_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVA097_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVA097_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVA097_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVA097_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVA097_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVA097_SET_VAB_NORMAL3S(i) (0x0f00+(i)*4) +#define NVA097_SET_VAB_NORMAL3S_V 31:0 + +#define NVA097_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVA097_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVA097_SET_BACK_STENCIL_MASK 0x0f58 +#define NVA097_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVA097_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVA097_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVA097_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVA097_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVA097_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVA097_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVA097_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVA097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVA097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVA097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVA097_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVA097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVA097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVA097_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVA097_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVA097_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVA097_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVA097_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVA097_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVA097_SET_CT_MRT_ENABLE 0x0fac +#define NVA097_SET_CT_MRT_ENABLE_V 0:0 +#define NVA097_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVA097_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVA097_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVA097_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVA097_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVA097_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVA097_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVA097_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVA097_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVA097_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVA097_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVA097_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVA097_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVA097_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVA097_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVA097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVA097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVA097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVA097_SET_ZT_A 0x0fe0 +#define NVA097_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_ZT_B 0x0fe4 +#define NVA097_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_ZT_FORMAT 0x0fe8 +#define NVA097_SET_ZT_FORMAT_V 4:0 +#define NVA097_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVA097_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVA097_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVA097_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVA097_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVA097_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVA097_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVA097_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVA097_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVA097_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVA097_SET_ZT_BLOCK_SIZE 0x0fec +#define NVA097_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVA097_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA097_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVA097_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVA097_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVA097_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVA097_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVA097_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVA097_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVA097_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVA097_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVA097_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA097_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVA097_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVA097_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVA097_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVA097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVA097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVA097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVA097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVA097_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVA097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVA097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVA097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVA097_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVA097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVA097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_SPARE_NOOP00 0x1040 +#define NVA097_SET_SPARE_NOOP00_V 31:0 + +#define NVA097_SET_SPARE_NOOP01 0x1044 +#define NVA097_SET_SPARE_NOOP01_V 31:0 + +#define NVA097_SET_SPARE_NOOP02 0x1048 +#define NVA097_SET_SPARE_NOOP02_V 31:0 + +#define NVA097_SET_SPARE_NOOP03 0x104c +#define NVA097_SET_SPARE_NOOP03_V 31:0 + +#define NVA097_SET_SPARE_NOOP04 0x1050 +#define NVA097_SET_SPARE_NOOP04_V 31:0 + +#define NVA097_SET_SPARE_NOOP05 0x1054 +#define NVA097_SET_SPARE_NOOP05_V 31:0 + +#define NVA097_SET_SPARE_NOOP06 0x1058 +#define NVA097_SET_SPARE_NOOP06_V 31:0 + +#define NVA097_SET_SPARE_NOOP07 0x105c +#define NVA097_SET_SPARE_NOOP07_V 31:0 + +#define NVA097_SET_SPARE_NOOP08 0x1060 +#define NVA097_SET_SPARE_NOOP08_V 31:0 + +#define NVA097_SET_SPARE_NOOP09 0x1064 +#define NVA097_SET_SPARE_NOOP09_V 31:0 + +#define NVA097_SET_SPARE_NOOP10 0x1068 +#define NVA097_SET_SPARE_NOOP10_V 31:0 + +#define NVA097_SET_SPARE_NOOP11 0x106c +#define NVA097_SET_SPARE_NOOP11_V 31:0 + +#define NVA097_SET_SPARE_NOOP12 0x1070 +#define NVA097_SET_SPARE_NOOP12_V 31:0 + +#define NVA097_SET_SPARE_NOOP13 0x1074 +#define NVA097_SET_SPARE_NOOP13_V 31:0 + +#define NVA097_SET_SPARE_NOOP14 0x1078 +#define NVA097_SET_SPARE_NOOP14_V 31:0 + +#define NVA097_SET_SPARE_NOOP15 0x107c +#define NVA097_SET_SPARE_NOOP15_V 31:0 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVA097_UNBIND_ALL 0x10f4 +#define NVA097_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVA097_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVA097_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVA097_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA097_NO_OPERATION_DATA_HI 0x110c +#define NVA097_NO_OPERATION_DATA_HI_V 31:0 + +#define NVA097_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVA097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVA097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVA097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVA097_PM_TRIGGER_END 0x1114 +#define NVA097_PM_TRIGGER_END_V 31:0 + +#define NVA097_SET_VERTEX_ID_BASE 0x1118 +#define NVA097_SET_VERTEX_ID_BASE_V 31:0 + +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVA097_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVA097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVA097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVA097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVA097_FLUSH_PENDING_WRITES 0x1144 +#define NVA097_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVA097_SET_VAB_DATA_CONTROL 0x114c +#define NVA097_SET_VAB_DATA_CONTROL_VAB_INDEX 7:0 +#define NVA097_SET_VAB_DATA_CONTROL_COMPONENT_COUNT 10:8 +#define NVA097_SET_VAB_DATA_CONTROL_COMPONENT_BYTE_WIDTH 14:12 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT 18:16 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_SNORM 0x00000001 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_UNORM 0x00000002 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_SINT 0x00000003 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_UINT 0x00000004 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_USCALED 0x00000005 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_SSCALED 0x00000006 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_FLOAT 0x00000007 + +#define NVA097_SET_VAB_DATA(i) (0x1150+(i)*4) +#define NVA097_SET_VAB_DATA_V 31:0 + +#define NVA097_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVA097_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVA097_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVA097_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_SET_CT_SELECT 0x121c +#define NVA097_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVA097_SET_CT_SELECT_TARGET0 6:4 +#define NVA097_SET_CT_SELECT_TARGET1 9:7 +#define NVA097_SET_CT_SELECT_TARGET2 12:10 +#define NVA097_SET_CT_SELECT_TARGET3 15:13 +#define NVA097_SET_CT_SELECT_TARGET4 18:16 +#define NVA097_SET_CT_SELECT_TARGET5 21:19 +#define NVA097_SET_CT_SELECT_TARGET6 24:22 +#define NVA097_SET_CT_SELECT_TARGET7 27:25 + +#define NVA097_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVA097_SET_ZT_SIZE_A 0x1228 +#define NVA097_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVA097_SET_ZT_SIZE_B 0x122c +#define NVA097_SET_ZT_SIZE_B_HEIGHT 16:0 + +#define NVA097_SET_ZT_SIZE_C 0x1230 +#define NVA097_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVA097_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVA097_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVA097_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVA097_SET_SAMPLER_BINDING 0x1234 +#define NVA097_SET_SAMPLER_BINDING_V 0:0 +#define NVA097_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVA097_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVA097_DRAW_AUTO 0x123c +#define NVA097_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVA097_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVA097_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 9:0 + +#define NVA097_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVA097_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVA097_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVA097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVA097_SET_SHADER_SCHEDULING 0x12ac +#define NVA097_SET_SHADER_SCHEDULING_MODE 0:0 +#define NVA097_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 +#define NVA097_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 + +#define NVA097_CLEAR_ZCULL_REGION 0x12c8 +#define NVA097_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVA097_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVA097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVA097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVA097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVA097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVA097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVA097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVA097_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVA097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVA097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVA097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVA097_SET_DEPTH_TEST 0x12cc +#define NVA097_SET_DEPTH_TEST_ENABLE 0:0 +#define NVA097_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_FILL_MODE 0x12d0 +#define NVA097_SET_FILL_MODE_V 31:0 +#define NVA097_SET_FILL_MODE_V_POINT 0x00000001 +#define NVA097_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVA097_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVA097_SET_SHADE_MODE 0x12d4 +#define NVA097_SET_SHADE_MODE_V 31:0 +#define NVA097_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVA097_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVA097_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVA097_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVA097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVA097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVA097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVA097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVA097_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVA097_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVA097_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVA097_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_DEPTH_WRITE 0x12e8 +#define NVA097_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVA097_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_ALPHA_TEST 0x12ec +#define NVA097_SET_ALPHA_TEST_ENABLE 0:0 +#define NVA097_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVA097_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVA097_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVA097_DRAW_INLINE_INDEX4X8 0x1304 +#define NVA097_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVA097_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVA097_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVA097_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVA097_D3D_SET_CULL_MODE 0x1308 +#define NVA097_D3D_SET_CULL_MODE_V 31:0 +#define NVA097_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVA097_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVA097_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVA097_SET_DEPTH_FUNC 0x130c +#define NVA097_SET_DEPTH_FUNC_V 31:0 +#define NVA097_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVA097_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVA097_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA097_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA097_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVA097_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA097_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA097_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA097_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVA097_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVA097_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA097_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA097_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVA097_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA097_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA097_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA097_SET_ALPHA_REF 0x1310 +#define NVA097_SET_ALPHA_REF_V 31:0 + +#define NVA097_SET_ALPHA_FUNC 0x1314 +#define NVA097_SET_ALPHA_FUNC_V 31:0 +#define NVA097_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVA097_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVA097_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA097_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA097_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVA097_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA097_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA097_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA097_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVA097_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVA097_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA097_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA097_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVA097_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA097_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA097_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA097_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVA097_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVA097_SET_BLEND_CONST_RED 0x131c +#define NVA097_SET_BLEND_CONST_RED_V 31:0 + +#define NVA097_SET_BLEND_CONST_GREEN 0x1320 +#define NVA097_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVA097_SET_BLEND_CONST_BLUE 0x1324 +#define NVA097_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVA097_SET_BLEND_CONST_ALPHA 0x1328 +#define NVA097_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVA097_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVA097_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVA097_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVA097_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVA097_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVA097_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVA097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVA097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVA097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_BLEND_COLOR_OP 0x1340 +#define NVA097_SET_BLEND_COLOR_OP_V 31:0 +#define NVA097_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA097_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA097_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA097_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVA097_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVA097_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVA097_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA097_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA097_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVA097_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_BLEND_ALPHA_OP 0x134c +#define NVA097_SET_BLEND_ALPHA_OP_V 31:0 +#define NVA097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA097_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVA097_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVA097_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVA097_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA097_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA097_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVA097_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVA097_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVA097_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVA097_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_SINGLE_ROP_CONTROL 0x135c +#define NVA097_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVA097_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_BLEND(i) (0x1360+(i)*4) +#define NVA097_SET_BLEND_ENABLE 0:0 +#define NVA097_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVA097_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_STENCIL_TEST 0x1380 +#define NVA097_SET_STENCIL_TEST_ENABLE 0:0 +#define NVA097_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_STENCIL_OP_FAIL 0x1384 +#define NVA097_SET_STENCIL_OP_FAIL_V 31:0 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVA097_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVA097_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVA097_SET_STENCIL_OP_ZPASS 0x138c +#define NVA097_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVA097_SET_STENCIL_FUNC 0x1390 +#define NVA097_SET_STENCIL_FUNC_V 31:0 +#define NVA097_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVA097_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVA097_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA097_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA097_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVA097_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA097_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA097_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA097_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVA097_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVA097_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA097_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA097_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVA097_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA097_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA097_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA097_SET_STENCIL_FUNC_REF 0x1394 +#define NVA097_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVA097_SET_STENCIL_FUNC_MASK 0x1398 +#define NVA097_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVA097_SET_STENCIL_MASK 0x139c +#define NVA097_SET_STENCIL_MASK_V 7:0 + +#define NVA097_SET_DRAW_AUTO_START 0x13a4 +#define NVA097_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVA097_SET_PS_SATURATE 0x13a8 +#define NVA097_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVA097_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVA097_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVA097_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVA097_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVA097_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVA097_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVA097_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVA097_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 + +#define NVA097_SET_WINDOW_ORIGIN 0x13ac +#define NVA097_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVA097_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVA097_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVA097_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVA097_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVA097_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVA097_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVA097_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVA097_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVA097_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVA097_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVA097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVA097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_ALPHA_HYSTERESIS 0x1420 +#define NVA097_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NVA097_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVA097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVA097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA097_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVA097_INVALIDATE_DA_DMA_CACHE 0x142c +#define NVA097_INVALIDATE_DA_DMA_CACHE_V 0:0 + +#define NVA097_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVA097_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVA097_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVA097_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVA097_SET_PS_WARP_WATERMARKS 0x1450 +#define NVA097_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVA097_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVA097_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVA097_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVA097_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVA097_STORE_ZCULL 0x1464 +#define NVA097_STORE_ZCULL_V 0:0 + +#define NVA097_LOAD_ZCULL 0x1500 +#define NVA097_LOAD_ZCULL_V 0:0 + +#define NVA097_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVA097_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVA097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVA097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVA097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVA097_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVA097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVA097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVA097_SET_USER_CLIP_ENABLE 0x1510 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVA097_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVA097_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVA097_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_POINT_SIZE 0x1518 +#define NVA097_SET_POINT_SIZE_V 31:0 + +#define NVA097_SET_ZCULL_STATS 0x151c +#define NVA097_SET_ZCULL_STATS_ENABLE 0:0 +#define NVA097_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_POINT_SPRITE 0x1520 +#define NVA097_SET_POINT_SPRITE_ENABLE 0:0 +#define NVA097_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_SHADER_EXCEPTIONS 0x1528 +#define NVA097_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVA097_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVA097_CLEAR_REPORT_VALUE 0x1530 +#define NVA097_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVA097_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVA097_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVA097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVA097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVA097_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVA097_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 + +#define NVA097_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVA097_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVA097_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_ZT_SELECT 0x1538 +#define NVA097_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVA097_SET_RENDER_ENABLE_A 0x1550 +#define NVA097_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_RENDER_ENABLE_B 0x1554 +#define NVA097_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_RENDER_ENABLE_C 0x1558 +#define NVA097_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVA097_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA097_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA097_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA097_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVA097_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVA097_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVA097_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVA097_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVA097_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVA097_SET_ANTI_ALIASED_LINE 0x1570 +#define NVA097_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVA097_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_TEX_HEADER_POOL_A 0x1574 +#define NVA097_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_TEX_HEADER_POOL_B 0x1578 +#define NVA097_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_TEX_HEADER_POOL_C 0x157c +#define NVA097_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVA097_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVA097_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVA097_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVA097_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVA097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVA097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVA097_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVA097_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVA097_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA097_SET_SRGB_WRITE 0x15b8 +#define NVA097_SET_SRGB_WRITE_ENABLE 0:0 +#define NVA097_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_DEPTH_BIAS 0x15bc +#define NVA097_SET_DEPTH_BIAS_V 31:0 + +#define NVA097_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVA097_SET_RT_LAYER 0x15cc +#define NVA097_SET_RT_LAYER_V 15:0 +#define NVA097_SET_RT_LAYER_CONTROL 16:16 +#define NVA097_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVA097_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVA097_SET_ANTI_ALIAS 0x15d0 +#define NVA097_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVA097_SET_EDGE_FLAG 0x15e4 +#define NVA097_SET_EDGE_FLAG_V 0:0 +#define NVA097_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVA097_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVA097_DRAW_INLINE_INDEX 0x15e8 +#define NVA097_DRAW_INLINE_INDEX_V 31:0 + +#define NVA097_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVA097_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVA097_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVA097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVA097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVA097_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVA097_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVA097_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVA097_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVA097_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVA097_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVA097_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVA097_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVA097_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVA097_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVA097_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVA097_SET_POINT_SPRITE_SELECT 0x1604 +#define NVA097_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVA097_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVA097_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVA097_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVA097_SET_PROGRAM_REGION_A 0x1608 +#define NVA097_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVA097_SET_PROGRAM_REGION_B 0x160c +#define NVA097_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVA097_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVA097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVA097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVA097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVA097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVA097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVA097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVA097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVA097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVA097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVA097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVA097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVA097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVA097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVA097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVA097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVA097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVA097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVA097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVA097_END 0x1614 +#define NVA097_END_V 0:0 + +#define NVA097_BEGIN 0x1618 +#define NVA097_BEGIN_OP 15:0 +#define NVA097_BEGIN_OP_POINTS 0x00000000 +#define NVA097_BEGIN_OP_LINES 0x00000001 +#define NVA097_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVA097_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVA097_BEGIN_OP_TRIANGLES 0x00000004 +#define NVA097_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVA097_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVA097_BEGIN_OP_QUADS 0x00000007 +#define NVA097_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVA097_BEGIN_OP_POLYGON 0x00000009 +#define NVA097_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVA097_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVA097_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_BEGIN_OP_PATCH 0x0000000E +#define NVA097_BEGIN_PRIMITIVE_ID 24:24 +#define NVA097_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVA097_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVA097_BEGIN_INSTANCE_ID 27:26 +#define NVA097_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVA097_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVA097_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVA097_BEGIN_SPLIT_MODE 30:29 +#define NVA097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVA097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVA097_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVA097_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 + +#define NVA097_SET_VERTEX_ID_COPY 0x161c +#define NVA097_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVA097_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVA097_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVA097_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVA097_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVA097_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVA097_LOAD_PRIMITIVE_ID 0x1624 +#define NVA097_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVA097_SET_SHADER_BASED_CULL 0x162c +#define NVA097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVA097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVA097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVA097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_CLASS_VERSION 0x1638 +#define NVA097_SET_CLASS_VERSION_CURRENT 15:0 +#define NVA097_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA097_SET_VAB_PAGE 0x163c +#define NVA097_SET_VAB_PAGE_READ_SELECT 0:0 +#define NVA097_SET_VAB_PAGE_READ_SELECT_PAGES_0_AND_1 0x00000000 +#define NVA097_SET_VAB_PAGE_READ_SELECT_PAGES_0_AND_2 0x00000001 + +#define NVA097_DRAW_INLINE_VERTEX 0x1640 +#define NVA097_DRAW_INLINE_VERTEX_V 31:0 + +#define NVA097_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVA097_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVA097_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVA097_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVA097_SET_DA_OUTPUT 0x164c +#define NVA097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVA097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVA097_SET_ANTI_ALIASED_POINT 0x1658 +#define NVA097_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVA097_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_POINT_CENTER_MODE 0x165c +#define NVA097_SET_POINT_CENTER_MODE_V 31:0 +#define NVA097_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVA097_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVA097_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVA097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVA097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVA097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVA097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVA097_SET_LINE_STIPPLE 0x166c +#define NVA097_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVA097_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVA097_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVA097_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVA097_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVA097_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVA097_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVA097_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVA097_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVA097_SET_PROVOKING_VERTEX 0x1684 +#define NVA097_SET_PROVOKING_VERTEX_V 0:0 +#define NVA097_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVA097_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVA097_SET_TWO_SIDED_LIGHT 0x1688 +#define NVA097_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVA097_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_POLYGON_STIPPLE 0x168c +#define NVA097_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVA097_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_SHADER_CONTROL 0x1690 +#define NVA097_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVA097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVA097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVA097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVA097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVA097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVA097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVA097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVA097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVA097_LAUNCH_VERTEX 0x169c +#define NVA097_LAUNCH_VERTEX_V 0:0 + +#define NVA097_CHECK_CLASS_VERSION 0x16a0 +#define NVA097_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVA097_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA097_SET_SPH_VERSION 0x16a4 +#define NVA097_SET_SPH_VERSION_CURRENT 15:0 +#define NVA097_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA097_CHECK_SPH_VERSION 0x16a8 +#define NVA097_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVA097_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVA097_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVA097_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVA097_SET_AAM_VERSION 0x1790 +#define NVA097_SET_AAM_VERSION_CURRENT 15:0 +#define NVA097_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA097_CHECK_AAM_VERSION 0x1794 +#define NVA097_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVA097_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA097_SET_ZT_LAYER 0x179c +#define NVA097_SET_ZT_LAYER_OFFSET 15:0 + +#define NVA097_SET_VAB_MEMORY_AREA_A 0x17bc +#define NVA097_SET_VAB_MEMORY_AREA_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_VAB_MEMORY_AREA_B 0x17c0 +#define NVA097_SET_VAB_MEMORY_AREA_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_VAB_MEMORY_AREA_C 0x17c4 +#define NVA097_SET_VAB_MEMORY_AREA_C_SIZE 1:0 +#define NVA097_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_64K 0x00000001 +#define NVA097_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_128K 0x00000002 +#define NVA097_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_256K 0x00000003 + +#define NVA097_SET_INDEX_BUFFER_A 0x17c8 +#define NVA097_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVA097_SET_INDEX_BUFFER_B 0x17cc +#define NVA097_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVA097_SET_INDEX_BUFFER_C 0x17d0 +#define NVA097_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVA097_SET_INDEX_BUFFER_D 0x17d4 +#define NVA097_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVA097_SET_INDEX_BUFFER_E 0x17d8 +#define NVA097_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVA097_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVA097_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVA097_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVA097_SET_INDEX_BUFFER_F 0x17dc +#define NVA097_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVA097_DRAW_INDEX_BUFFER 0x17e0 +#define NVA097_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVA097_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVA097_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVA097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVA097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVA097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVA097_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVA097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVA097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVA097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVA097_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVA097_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVA097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVA097_OGL_SET_CULL 0x1918 +#define NVA097_OGL_SET_CULL_ENABLE 0:0 +#define NVA097_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVA097_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVA097_OGL_SET_FRONT_FACE 0x191c +#define NVA097_OGL_SET_FRONT_FACE_V 31:0 +#define NVA097_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVA097_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVA097_OGL_SET_CULL_FACE 0x1920 +#define NVA097_OGL_SET_CULL_FACE_V 31:0 +#define NVA097_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVA097_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVA097_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVA097_SET_VIEWPORT_PIXEL 0x1924 +#define NVA097_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVA097_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVA097_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVA097_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVA097_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVA097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVA097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVA097_INVALIDATE_CONSTANT_BUFFER_CACHE 0x1930 +#define NVA097_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2 0:0 +#define NVA097_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_FALSE 0x00000000 +#define NVA097_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_TRUE 0x00000001 + +#define NVA097_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVA097_SET_USER_CLIP_OP 0x1940 +#define NVA097_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVA097_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVA097_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVA097_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVA097_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVA097_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVA097_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVA097_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVA097_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVA097_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVA097_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVA097_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVA097_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVA097_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVA097_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVA097_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVA097_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVA097_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVA097_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVA097_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVA097_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVA097_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVA097_INVALIDATE_ZCULL 0x1958 +#define NVA097_INVALIDATE_ZCULL_V 31:0 +#define NVA097_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVA097_SET_ZCULL 0x1968 +#define NVA097_SET_ZCULL_Z_ENABLE 0:0 +#define NVA097_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVA097_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_ZCULL_BOUNDS 0x196c +#define NVA097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVA097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVA097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVA097_ZCULL_SYNC 0x1978 +#define NVA097_ZCULL_SYNC_V 31:0 + +#define NVA097_SET_CLIP_ID_TEST 0x197c +#define NVA097_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVA097_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVA097_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVA097_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVA097_SET_CLIP_ID 0x1984 +#define NVA097_SET_CLIP_ID_V 31:0 + +#define NVA097_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVA097_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVA097_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVA097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVA097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVA097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVA097_SET_LOGIC_OP 0x19c4 +#define NVA097_SET_LOGIC_OP_ENABLE 0:0 +#define NVA097_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVA097_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_LOGIC_OP_FUNC 0x19c8 +#define NVA097_SET_LOGIC_OP_FUNC_V 31:0 +#define NVA097_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVA097_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVA097_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVA097_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVA097_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVA097_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVA097_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVA097_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVA097_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVA097_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVA097_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVA097_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVA097_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVA097_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVA097_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVA097_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVA097_SET_Z_COMPRESSION 0x19cc +#define NVA097_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVA097_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVA097_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVA097_CLEAR_SURFACE 0x19d0 +#define NVA097_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVA097_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVA097_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVA097_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVA097_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVA097_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVA097_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVA097_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVA097_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVA097_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVA097_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVA097_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVA097_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVA097_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVA097_SET_CT_WRITE_R_ENABLE 0:0 +#define NVA097_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVA097_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVA097_SET_CT_WRITE_G_ENABLE 4:4 +#define NVA097_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVA097_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVA097_SET_CT_WRITE_B_ENABLE 8:8 +#define NVA097_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVA097_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVA097_SET_CT_WRITE_A_ENABLE 12:12 +#define NVA097_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVA097_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVA097_PIPE_NOP 0x1a2c +#define NVA097_PIPE_NOP_V 31:0 + +#define NVA097_SET_SPARE00 0x1a30 +#define NVA097_SET_SPARE00_V 31:0 + +#define NVA097_SET_SPARE01 0x1a34 +#define NVA097_SET_SPARE01_V 31:0 + +#define NVA097_SET_SPARE02 0x1a38 +#define NVA097_SET_SPARE02_V 31:0 + +#define NVA097_SET_SPARE03 0x1a3c +#define NVA097_SET_SPARE03_V 31:0 + +#define NVA097_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVA097_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVA097_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVA097_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA097_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVA097_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVA097_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVA097_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVA097_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVA097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVA097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVA097_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVA097_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVA097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVA097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVA097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVA097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVA097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVA097_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVA097_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVA097_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVA097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVA097_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVA097_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVA097_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVA097_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVA097_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVA097_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVA097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVA097_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVA097_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVA097_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVA097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVA097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVA097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVA097_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVA097_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVA097_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVA097_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVA097_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVA097_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVA097_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVA097_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVA097_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVA097_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVA097_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVA097_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVA097_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVA097_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVA097_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVA097_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVA097_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVA097_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVA097_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NVA097_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NVA097_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVA097_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVA097_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVA097_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NVA097_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVA097_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVA097_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NVA097_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVA097_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NVA097_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NVA097_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVA097_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVA097_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVA097_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVA097_SET_FALCON00 0x2300 +#define NVA097_SET_FALCON00_V 31:0 + +#define NVA097_SET_FALCON01 0x2304 +#define NVA097_SET_FALCON01_V 31:0 + +#define NVA097_SET_FALCON02 0x2308 +#define NVA097_SET_FALCON02_V 31:0 + +#define NVA097_SET_FALCON03 0x230c +#define NVA097_SET_FALCON03_V 31:0 + +#define NVA097_SET_FALCON04 0x2310 +#define NVA097_SET_FALCON04_V 31:0 + +#define NVA097_SET_FALCON05 0x2314 +#define NVA097_SET_FALCON05_V 31:0 + +#define NVA097_SET_FALCON06 0x2318 +#define NVA097_SET_FALCON06_V 31:0 + +#define NVA097_SET_FALCON07 0x231c +#define NVA097_SET_FALCON07_V 31:0 + +#define NVA097_SET_FALCON08 0x2320 +#define NVA097_SET_FALCON08_V 31:0 + +#define NVA097_SET_FALCON09 0x2324 +#define NVA097_SET_FALCON09_V 31:0 + +#define NVA097_SET_FALCON10 0x2328 +#define NVA097_SET_FALCON10_V 31:0 + +#define NVA097_SET_FALCON11 0x232c +#define NVA097_SET_FALCON11_V 31:0 + +#define NVA097_SET_FALCON12 0x2330 +#define NVA097_SET_FALCON12_V 31:0 + +#define NVA097_SET_FALCON13 0x2334 +#define NVA097_SET_FALCON13_V 31:0 + +#define NVA097_SET_FALCON14 0x2338 +#define NVA097_SET_FALCON14_V 31:0 + +#define NVA097_SET_FALCON15 0x233c +#define NVA097_SET_FALCON15_V 31:0 + +#define NVA097_SET_FALCON16 0x2340 +#define NVA097_SET_FALCON16_V 31:0 + +#define NVA097_SET_FALCON17 0x2344 +#define NVA097_SET_FALCON17_V 31:0 + +#define NVA097_SET_FALCON18 0x2348 +#define NVA097_SET_FALCON18_V 31:0 + +#define NVA097_SET_FALCON19 0x234c +#define NVA097_SET_FALCON19_V 31:0 + +#define NVA097_SET_FALCON20 0x2350 +#define NVA097_SET_FALCON20_V 31:0 + +#define NVA097_SET_FALCON21 0x2354 +#define NVA097_SET_FALCON21_V 31:0 + +#define NVA097_SET_FALCON22 0x2358 +#define NVA097_SET_FALCON22_V 31:0 + +#define NVA097_SET_FALCON23 0x235c +#define NVA097_SET_FALCON23_V 31:0 + +#define NVA097_SET_FALCON24 0x2360 +#define NVA097_SET_FALCON24_V 31:0 + +#define NVA097_SET_FALCON25 0x2364 +#define NVA097_SET_FALCON25_V 31:0 + +#define NVA097_SET_FALCON26 0x2368 +#define NVA097_SET_FALCON26_V 31:0 + +#define NVA097_SET_FALCON27 0x236c +#define NVA097_SET_FALCON27_V 31:0 + +#define NVA097_SET_FALCON28 0x2370 +#define NVA097_SET_FALCON28_V 31:0 + +#define NVA097_SET_FALCON29 0x2374 +#define NVA097_SET_FALCON29_V 31:0 + +#define NVA097_SET_FALCON30 0x2378 +#define NVA097_SET_FALCON30_V 31:0 + +#define NVA097_SET_FALCON31 0x237c +#define NVA097_SET_FALCON31_V 31:0 + +#define NVA097_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVA097_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVA097_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVA097_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVA097_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVA097_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVA097_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVA097_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVA097_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVA097_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVA097_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVA097_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVA097_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVA097_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVA097_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVA097_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVA097_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVA097_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVA097_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVA097_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVA097_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA097_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA097_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVA097_SET_COLOR_CLAMP 0x2600 +#define NVA097_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVA097_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVA097_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVA097_NOOP_X_X_X_SET_VALVE 0x2604 +#define NVA097_NOOP_X_X_X_SET_VALVE_HIGHER_PRIORITY 0:0 +#define NVA097_NOOP_X_X_X_SET_VALVE_HIGHER_PRIORITY_COMPUTE 0x00000000 +#define NVA097_NOOP_X_X_X_SET_VALVE_HIGHER_PRIORITY_GRAPHICS 0x00000001 + +#define NVA097_SET_BINDLESS_TEXTURE 0x2608 +#define NVA097_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVA097_SET_TRAP_HANDLER 0x260c +#define NVA097_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVA097_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVA097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVA097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVA097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVA097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVA097_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVA097_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVA097_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVA097_CALL_MME_MACRO_V 31:0 + +#define NVA097_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVA097_CALL_MME_DATA_V 31:0 + +#endif /* _cl_kepler_a_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cla0b0.h b/userspace/sdks/nv570/inc/class/cla0b0.h new file mode 100644 index 0000000..ef4faa8 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cla0b0.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "nvtypes.h" + +#ifndef _cla0b0_h_ +#define _cla0b0_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVA0B0_VIDEO_DECODER (0x0000A0B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cla0b0_h diff --git a/userspace/sdks/nv570/inc/class/cla0b5.h b/userspace/sdks/nv570/inc/class/cla0b5.h new file mode 100644 index 0000000..92076c6 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cla0b5.h @@ -0,0 +1,262 @@ +/******************************************************************************* + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _cla0b5_h_ +#define _cla0b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define KEPLER_DMA_COPY_A (0x0000A0B5) + +#define NVA0B5_NOP (0x00000100) +#define NVA0B5_NOP_PARAMETER 31:0 +#define NVA0B5_PM_TRIGGER (0x00000140) +#define NVA0B5_PM_TRIGGER_V 31:0 +#define NVA0B5_SET_SEMAPHORE_A (0x00000240) +#define NVA0B5_SET_SEMAPHORE_A_UPPER 7:0 +#define NVA0B5_SET_SEMAPHORE_B (0x00000244) +#define NVA0B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVA0B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVA0B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVA0B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVA0B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVA0B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVA0B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVA0B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVA0B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVA0B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVA0B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVA0B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVA0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVA0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVA0B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVA0B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVA0B5_SET_DST_PHYS_MODE (0x00000264) +#define NVA0B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVA0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVA0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVA0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVA0B5_LAUNCH_DMA (0x00000300) +#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVA0B5_LAUNCH_DMA_BYPASS_L2 11:11 +#define NVA0B5_LAUNCH_DMA_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVA0B5_LAUNCH_DMA_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVA0B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVA0B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVA0B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVA0B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVA0B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVA0B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN (0x0000000B) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX (0x0000000C) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMUL (0x0000000D) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMUL (0x0000000E) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVA0B5_OFFSET_IN_UPPER (0x00000400) +#define NVA0B5_OFFSET_IN_UPPER_UPPER 7:0 +#define NVA0B5_OFFSET_IN_LOWER (0x00000404) +#define NVA0B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVA0B5_OFFSET_OUT_UPPER (0x00000408) +#define NVA0B5_OFFSET_OUT_UPPER_UPPER 7:0 +#define NVA0B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVA0B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVA0B5_PITCH_IN (0x00000410) +#define NVA0B5_PITCH_IN_VALUE 31:0 +#define NVA0B5_PITCH_OUT (0x00000414) +#define NVA0B5_PITCH_OUT_VALUE 31:0 +#define NVA0B5_LINE_LENGTH_IN (0x00000418) +#define NVA0B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVA0B5_LINE_COUNT (0x0000041C) +#define NVA0B5_LINE_COUNT_VALUE 31:0 +#define NVA0B5_SET_REMAP_CONST_A (0x00000700) +#define NVA0B5_SET_REMAP_CONST_A_V 31:0 +#define NVA0B5_SET_REMAP_CONST_B (0x00000704) +#define NVA0B5_SET_REMAP_CONST_B_V 31:0 +#define NVA0B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVA0B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVA0B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVA0B5_SET_DST_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) +#define NVA0B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVA0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVA0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) +#define NVA0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVA0B5_SET_DST_WIDTH (0x00000710) +#define NVA0B5_SET_DST_WIDTH_V 31:0 +#define NVA0B5_SET_DST_HEIGHT (0x00000714) +#define NVA0B5_SET_DST_HEIGHT_V 31:0 +#define NVA0B5_SET_DST_DEPTH (0x00000718) +#define NVA0B5_SET_DST_DEPTH_V 31:0 +#define NVA0B5_SET_DST_LAYER (0x0000071C) +#define NVA0B5_SET_DST_LAYER_V 31:0 +#define NVA0B5_SET_DST_ORIGIN (0x00000720) +#define NVA0B5_SET_DST_ORIGIN_X 15:0 +#define NVA0B5_SET_DST_ORIGIN_Y 31:16 +#define NVA0B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVA0B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVA0B5_SET_SRC_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) +#define NVA0B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVA0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVA0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) +#define NVA0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVA0B5_SET_SRC_WIDTH (0x0000072C) +#define NVA0B5_SET_SRC_WIDTH_V 31:0 +#define NVA0B5_SET_SRC_HEIGHT (0x00000730) +#define NVA0B5_SET_SRC_HEIGHT_V 31:0 +#define NVA0B5_SET_SRC_DEPTH (0x00000734) +#define NVA0B5_SET_SRC_DEPTH_V 31:0 +#define NVA0B5_SET_SRC_LAYER (0x00000738) +#define NVA0B5_SET_SRC_LAYER_V 31:0 +#define NVA0B5_SET_SRC_ORIGIN (0x0000073C) +#define NVA0B5_SET_SRC_ORIGIN_X 15:0 +#define NVA0B5_SET_SRC_ORIGIN_Y 31:16 +#define NVA0B5_PM_TRIGGER_END (0x00001114) +#define NVA0B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cla0b5_h + diff --git a/userspace/sdks/nv570/inc/class/cla0bc.h b/userspace/sdks/nv570/inc/class/cla0bc.h new file mode 100644 index 0000000..bc26819 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cla0bc.h @@ -0,0 +1,209 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cla0bc.finn +// + +#define NVENC_SW_SESSION (0xa0bcU) /* finn: Evaluated from "NVA0BC_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* + * NVENC_SESSION_INFO_REGION_MAX_COUNT_V1 + * Number of regions. + * Currently we have two regions. + * +---------+ <== Region 1 Start + * | Entry 1 | + * | Entry 2 | + * | ... | + * | Entry N | + * +---------+ <== Region 1 End, Region 2 Start. + * | Entry 1 | + * | Entry 2 | + * | ... | + * | Entry N | + * +---------+ <== Region 2 End + * Region 1 : Contains GPU timestamp of each frame when frame was submitted + * to encode by UMD. + * Region 2 : Two entries in this region for each frame. Start and end GPU + * timestamps of when GPU started and ended encoding a frame. + */ +#define NVENC_SESSION_INFO_REGION_MAX_COUNT_V1 2 + +/* + * NVENC_SESSION_INFO_ENTRY_V1 + * This structure represents a single timestamp entry for a frame. + * frameId + * Frame id of the frame being submitted for encoding by UMD. + * reserved + * This is a reserved field. Unused. + * timestamp + * GPU timestamp. + */ + +typedef struct NVENC_SESSION_INFO_ENTRY_V1 { + NvU32 frameId; + NvU32 reserved; + NV_DECLARE_ALIGNED(NvU64 timestamp, 8); +} NVENC_SESSION_INFO_ENTRY_V1; + +/* + * NVENC_SESSION_INFO_REGION_1_ENTRY_V1 + * This structure represents an entry in Region 1. + * submissionTSEntry + * Frame id and GPU timestamp of the time when the frame was submitted to + * encode by UMD. + * + * NVENC_SESSION_INFO_REGION_1_ENTRY_SIZE_V1 + * Size of each entry in region 1. + * + * NVENC_SESSION_INFO_REGION_1_MAX_ENTRIES_COUNT_V1 + * No of entries in region 1. + * + * NVENC_SESSION_INFO_REGION_1_V1 + * This structure represents Region 1. + * + * NVENC_SESSION_INFO_REGION_1_SIZE_V1 + * Size of region 1. + * + * NVENC_SESSION_INFO_REGION_1_OFFSET_V1 + * First region, so offset is 0. + */ + +typedef struct NVENC_SESSION_INFO_REGION_1_ENTRY_V1 { + NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_ENTRY_V1 submissionTSEntry, 8); +} NVENC_SESSION_INFO_REGION_1_ENTRY_V1; + +#define NVENC_SESSION_INFO_REGION_1_ENTRY_SIZE_V1 sizeof(NVENC_SESSION_INFO_REGION_1_ENTRY_V1) + +#define NVENC_SESSION_INFO_REGION_1_MAX_ENTRIES_COUNT_V1 256 + +typedef struct NVENC_SESSION_INFO_REGION_1_V1 { + NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_REGION_1_ENTRY_V1 frameInfo[NVENC_SESSION_INFO_REGION_1_MAX_ENTRIES_COUNT_V1], 8); +} NVENC_SESSION_INFO_REGION_1_V1; + +#define NVENC_SESSION_INFO_REGION_1_SIZE_V1 sizeof(NVENC_SESSION_INFO_REGION_1_V1) + +#define NVENC_SESSION_INFO_REGION_1_OFFSET_V1 0 + +/* + * NVENC_SESSION_INFO_REGION_2_ENTRY_V1 + * This structure represents a complete entry in Region 2. + * startTSEntry + * Frame id and GPU timestamp of the time when frame encoding started. + * endTSEntry + * Frame id and GPU timestamp of the time when frame encoding ended. + * + * NVENC_SESSION_INFO_REGION_2_ENTRY_SIZE_V1 + * Size of each entry in region 2. + * + * NVENC_SESSION_INFO_REGION_2_MAX_ENTRIES_COUNT_V1 + * No of entries in region 2. + * + * NVENC_SESSION_INFO_REGION_2_V1 + * This structure represents Region 2. + * + * NVENC_SESSION_INFO_REGION_2_SIZE_V1 + * Size of region 2. + * + * NVENC_SESSION_INFO_REGION_2_OFFSET_V1 + * Offset of region 2 from base. + */ + +typedef struct NVENC_SESSION_INFO_REGION_2_ENTRY_V1 { + NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_ENTRY_V1 startTSEntry, 8); + NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_ENTRY_V1 endTSEntry, 8); +} NVENC_SESSION_INFO_REGION_2_ENTRY_V1; + +#define NVENC_SESSION_INFO_REGION_2_ENTRY_SIZE_V1 sizeof(NVENC_SESSION_INFO_REGION_2_ENTRY_V1) + +#define NVENC_SESSION_INFO_REGION_2_MAX_ENTRIES_COUNT_V1 NVENC_SESSION_INFO_REGION_1_MAX_ENTRIES_COUNT_V1 + +typedef struct NVENC_SESSION_INFO_REGION_2_V1 { + NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_REGION_2_ENTRY_V1 frameInfo[NVENC_SESSION_INFO_REGION_2_MAX_ENTRIES_COUNT_V1], 8); +} NVENC_SESSION_INFO_REGION_2_V1; + +#define NVENC_SESSION_INFO_REGION_2_SIZE_V1 sizeof(NVENC_SESSION_INFO_REGION_2_V1) + +#define NVENC_SESSION_INFO_REGION_2_OFFSET_V1 (NVENC_SESSION_INFO_REGION_1_OFFSET_V1 + \ + NVENC_SESSION_INFO_REGION_1_SIZE_V1) + +/* + * NVENC_SESSION_INFO_V1 + * This structure represents the complete memory allocated to store the per + * frame submission-start-end timestamps data. + * + * NVENC_SESSION_INFO_SIZE_V1 + * Size of complete memory. + */ + +typedef struct NVENC_SESSION_INFO_V1 { + NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_REGION_1_V1 region1, 8); + NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_REGION_2_V1 region2, 8); +} NVENC_SESSION_INFO_V1; + +#define NVENC_SESSION_INFO_SIZE_V1 sizeof(NVENC_SESSION_INFO_V1) + +/* + * NVA0BC_ALLOC_PARAMETERS + * + * This structure represents NVENC SW session allocation parameters. + * + * codecType + * Codec type to be used to do the encoding. + * hResolution + * Width of frames to be encoded. + * vResolution + * Height of frames to be encoded. + * version + * Adding version to handle any future changes to struct. + * In future we can extend this struct to notify RM that UMD needs to send + * other data. Versioning will help in identifying the difference in structs. + * Values are defined by NVA0BC_ALLOC_PARAMS_VER_xxx. + * hMem + * Handle to the system memory allocated by UMD. + * RM needs to access the memory to get the raw timestamp data and process it. + */ + +#define NVA0BC_ALLOC_PARAMETERS_MESSAGE_ID (0xa0bcU) + +typedef struct NVA0BC_ALLOC_PARAMETERS { + NvU32 codecType; + NvU32 hResolution; + NvU32 vResolution; + + NvU32 version; + NvHandle hMem; +} NVA0BC_ALLOC_PARAMETERS; + +#define NVA0BC_ALLOC_PARAMS_VER_0 0x00000000 +#define NVA0BC_ALLOC_PARAMS_VER_1 0x00000001 + +#define NVA0BC_NVENC_SESSION_CODEC_TYPE_H264 0x000000 +#define NVA0BC_NVENC_SESSION_CODEC_TYPE_HEVC 0x000001 +#define NVA0BC_NVENC_SESSION_CODEC_TYPE_AV1 0x000002 +#define NVA0BC_NVENC_SESSION_CODEC_TYPE_UNKNOWN 0x0000FF diff --git a/userspace/sdks/nv570/inc/class/cla0bd.h b/userspace/sdks/nv570/inc/class/cla0bd.h new file mode 100644 index 0000000..fb91d2d --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cla0bd.h @@ -0,0 +1,81 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cla0bd.finn +// + +#define NVFBC_SW_SESSION (0xa0bdU) /* finn: Evaluated from "NVA0BD_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* + * NVA0BD_ALLOC_PARAMETERS + * + * displayOrdinal + * This parameter specifies the display identifier. + * sessionType + * This parameter NVFBC session type. Possible values are specified + * by NVA0BD_NVFBC_SESSION_TYPE_* macros. + * sessionFlags + * This parameter returns various flags values of the NVFBC session. + * Valid flag values include: + * NVA0BD_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED + * When true this flag indicates there are user has enabled + * diff map feature for the session. + * NVA0BD_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED + * When true this flag indicates there are user has enabled + * diff map feature for the session. + * hMaxResolution + * This parameter returns the max horizontal resolution supported by + * the NvFBC session. + * vMaxResolution + * This parameter returns the max vertical resolution supported by + * the NvFBC session. + */ + +#define NVA0BD_ALLOC_PARAMETERS_MESSAGE_ID (0xa0bdU) + +typedef struct NVA0BD_ALLOC_PARAMETERS { + NvU32 displayOrdinal; + NvU32 sessionType; + NvU32 sessionFlags; + NvU32 hMaxResolution; + NvU32 vMaxResolution; +} NVA0BD_ALLOC_PARAMETERS; + +#define NVA0BD_NVFBC_SESSION_TYPE_UNKNOWN 0x000000 +#define NVA0BD_NVFBC_SESSION_TYPE_TOSYS 0x000001 +#define NVA0BD_NVFBC_SESSION_TYPE_CUDA 0x000002 +#define NVA0BD_NVFBC_SESSION_TYPE_VID 0x000003 +#define NVA0BD_NVFBC_SESSION_TYPE_HWENC 0x000004 + +#define NVA0BD_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED 0:0 +#define NVA0BD_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED_FALSE (0x00000000) +#define NVA0BD_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED_TRUE (0x00000001) +#define NVA0BD_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED 1:1 +#define NVA0BD_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED_FALSE (0x00000000) +#define NVA0BD_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED_TRUE (0x00000001) + diff --git a/userspace/sdks/nv570/inc/class/cla0c0.h b/userspace/sdks/nv570/inc/class/cla0c0.h new file mode 100644 index 0000000..bc73e40 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cla0c0.h @@ -0,0 +1,646 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_kepler_compute_a_h_ +#define _cl_kepler_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl kepler_compute_a */ + +#include "nvtypes.h" + +#define KEPLER_COMPUTE_A 0xA0C0 + +#define NVA0C0_SET_OBJECT 0x0000 +#define NVA0C0_SET_OBJECT_CLASS_ID 15:0 +#define NVA0C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVA0C0_NO_OPERATION 0x0100 +#define NVA0C0_NO_OPERATION_V 31:0 + +#define NVA0C0_SET_NOTIFY_A 0x0104 +#define NVA0C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVA0C0_SET_NOTIFY_B 0x0108 +#define NVA0C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVA0C0_NOTIFY 0x010c +#define NVA0C0_NOTIFY_TYPE 31:0 +#define NVA0C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVA0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVA0C0_WAIT_FOR_IDLE 0x0110 +#define NVA0C0_WAIT_FOR_IDLE_V 31:0 + +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA0C0_SEND_GO_IDLE 0x013c +#define NVA0C0_SEND_GO_IDLE_V 31:0 + +#define NVA0C0_PM_TRIGGER 0x0140 +#define NVA0C0_PM_TRIGGER_V 31:0 + +#define NVA0C0_PM_TRIGGER_WFI 0x0144 +#define NVA0C0_PM_TRIGGER_WFI_V 31:0 + +#define NVA0C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVA0C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVA0C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVA0C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVA0C0_LINE_LENGTH_IN 0x0180 +#define NVA0C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVA0C0_LINE_COUNT 0x0184 +#define NVA0C0_LINE_COUNT_VALUE 31:0 + +#define NVA0C0_OFFSET_OUT_UPPER 0x0188 +#define NVA0C0_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVA0C0_OFFSET_OUT 0x018c +#define NVA0C0_OFFSET_OUT_VALUE 31:0 + +#define NVA0C0_PITCH_OUT 0x0190 +#define NVA0C0_PITCH_OUT_VALUE 31:0 + +#define NVA0C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVA0C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVA0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVA0C0_SET_DST_WIDTH 0x0198 +#define NVA0C0_SET_DST_WIDTH_V 31:0 + +#define NVA0C0_SET_DST_HEIGHT 0x019c +#define NVA0C0_SET_DST_HEIGHT_V 31:0 + +#define NVA0C0_SET_DST_DEPTH 0x01a0 +#define NVA0C0_SET_DST_DEPTH_V 31:0 + +#define NVA0C0_SET_DST_LAYER 0x01a4 +#define NVA0C0_SET_DST_LAYER_V 31:0 + +#define NVA0C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVA0C0_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVA0C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVA0C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVA0C0_LAUNCH_DMA 0x01b0 +#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVA0C0_LOAD_INLINE_DATA 0x01b4 +#define NVA0C0_LOAD_INLINE_DATA_V 31:0 + +#define NVA0C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVA0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVA0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVA0C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA0C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVA0C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVA0C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVA0C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVA0C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVA0C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVA0C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVA0C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVA0C0_PERFMON_TRANSFER 0x0210 +#define NVA0C0_PERFMON_TRANSFER_V 31:0 + +#define NVA0C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVA0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA0C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVA0C0_SET_CWD_CONTROL 0x0240 +#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVA0C0_SET_CWD_REF_COUNTER 0x0248 +#define NVA0C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVA0C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0 + +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVA0C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVA0C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVA0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA0C0_SET_QMD_VERSION 0x0288 +#define NVA0C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVA0C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA0C0_CHECK_QMD_VERSION 0x0290 +#define NVA0C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVA0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA0C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVA0C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVA0C0_SEND_PCAS_A 0x02b4 +#define NVA0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVA0C0_SEND_PCAS_B 0x02b8 +#define NVA0C0_SEND_PCAS_B_FROM 23:0 +#define NVA0C0_SEND_PCAS_B_DELTA 31:24 + +#define NVA0C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVA0C0_SET_SPA_VERSION 0x0310 +#define NVA0C0_SET_SPA_VERSION_MINOR 7:0 +#define NVA0C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVA0C0_SET_FALCON00 0x0500 +#define NVA0C0_SET_FALCON00_V 31:0 + +#define NVA0C0_SET_FALCON01 0x0504 +#define NVA0C0_SET_FALCON01_V 31:0 + +#define NVA0C0_SET_FALCON02 0x0508 +#define NVA0C0_SET_FALCON02_V 31:0 + +#define NVA0C0_SET_FALCON03 0x050c +#define NVA0C0_SET_FALCON03_V 31:0 + +#define NVA0C0_SET_FALCON04 0x0510 +#define NVA0C0_SET_FALCON04_V 31:0 + +#define NVA0C0_SET_FALCON05 0x0514 +#define NVA0C0_SET_FALCON05_V 31:0 + +#define NVA0C0_SET_FALCON06 0x0518 +#define NVA0C0_SET_FALCON06_V 31:0 + +#define NVA0C0_SET_FALCON07 0x051c +#define NVA0C0_SET_FALCON07_V 31:0 + +#define NVA0C0_SET_FALCON08 0x0520 +#define NVA0C0_SET_FALCON08_V 31:0 + +#define NVA0C0_SET_FALCON09 0x0524 +#define NVA0C0_SET_FALCON09_V 31:0 + +#define NVA0C0_SET_FALCON10 0x0528 +#define NVA0C0_SET_FALCON10_V 31:0 + +#define NVA0C0_SET_FALCON11 0x052c +#define NVA0C0_SET_FALCON11_V 31:0 + +#define NVA0C0_SET_FALCON12 0x0530 +#define NVA0C0_SET_FALCON12_V 31:0 + +#define NVA0C0_SET_FALCON13 0x0534 +#define NVA0C0_SET_FALCON13_V 31:0 + +#define NVA0C0_SET_FALCON14 0x0538 +#define NVA0C0_SET_FALCON14_V 31:0 + +#define NVA0C0_SET_FALCON15 0x053c +#define NVA0C0_SET_FALCON15_V 31:0 + +#define NVA0C0_SET_FALCON16 0x0540 +#define NVA0C0_SET_FALCON16_V 31:0 + +#define NVA0C0_SET_FALCON17 0x0544 +#define NVA0C0_SET_FALCON17_V 31:0 + +#define NVA0C0_SET_FALCON18 0x0548 +#define NVA0C0_SET_FALCON18_V 31:0 + +#define NVA0C0_SET_FALCON19 0x054c +#define NVA0C0_SET_FALCON19_V 31:0 + +#define NVA0C0_SET_FALCON20 0x0550 +#define NVA0C0_SET_FALCON20_V 31:0 + +#define NVA0C0_SET_FALCON21 0x0554 +#define NVA0C0_SET_FALCON21_V 31:0 + +#define NVA0C0_SET_FALCON22 0x0558 +#define NVA0C0_SET_FALCON22_V 31:0 + +#define NVA0C0_SET_FALCON23 0x055c +#define NVA0C0_SET_FALCON23_V 31:0 + +#define NVA0C0_SET_FALCON24 0x0560 +#define NVA0C0_SET_FALCON24_V 31:0 + +#define NVA0C0_SET_FALCON25 0x0564 +#define NVA0C0_SET_FALCON25_V 31:0 + +#define NVA0C0_SET_FALCON26 0x0568 +#define NVA0C0_SET_FALCON26_V 31:0 + +#define NVA0C0_SET_FALCON27 0x056c +#define NVA0C0_SET_FALCON27_V 31:0 + +#define NVA0C0_SET_FALCON28 0x0570 +#define NVA0C0_SET_FALCON28_V 31:0 + +#define NVA0C0_SET_FALCON29 0x0574 +#define NVA0C0_SET_FALCON29_V 31:0 + +#define NVA0C0_SET_FALCON30 0x0578 +#define NVA0C0_SET_FALCON30_V 31:0 + +#define NVA0C0_SET_FALCON31 0x057c +#define NVA0C0_SET_FALCON31_V 31:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVA0C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVA0C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVA0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVA0C0_SET_SPARE_NOOP12 0x0f44 +#define NVA0C0_SET_SPARE_NOOP12_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP13 0x0f48 +#define NVA0C0_SET_SPARE_NOOP13_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP14 0x0f4c +#define NVA0C0_SET_SPARE_NOOP14_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP15 0x0f50 +#define NVA0C0_SET_SPARE_NOOP15_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP00 0x1040 +#define NVA0C0_SET_SPARE_NOOP00_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP01 0x1044 +#define NVA0C0_SET_SPARE_NOOP01_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP02 0x1048 +#define NVA0C0_SET_SPARE_NOOP02_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP03 0x104c +#define NVA0C0_SET_SPARE_NOOP03_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP04 0x1050 +#define NVA0C0_SET_SPARE_NOOP04_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP05 0x1054 +#define NVA0C0_SET_SPARE_NOOP05_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP06 0x1058 +#define NVA0C0_SET_SPARE_NOOP06_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP07 0x105c +#define NVA0C0_SET_SPARE_NOOP07_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP08 0x1060 +#define NVA0C0_SET_SPARE_NOOP08_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP09 0x1064 +#define NVA0C0_SET_SPARE_NOOP09_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP10 0x1068 +#define NVA0C0_SET_SPARE_NOOP10_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP11 0x106c +#define NVA0C0_SET_SPARE_NOOP11_V 31:0 + +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVA0C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVA0C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVA0C0_SET_RENDER_ENABLE_A 0x1550 +#define NVA0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_RENDER_ENABLE_B 0x1554 +#define NVA0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_RENDER_ENABLE_C 0x1558 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA0C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVA0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVA0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVA0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVA0C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVA0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVA0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVA0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVA0C0_SET_PROGRAM_REGION_A 0x1608 +#define NVA0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVA0C0_SET_PROGRAM_REGION_B 0x160c +#define NVA0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVA0C0_SET_SHADER_CONTROL 0x1690 +#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 + +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVA0C0_PIPE_NOP 0x1a2c +#define NVA0C0_PIPE_NOP_V 31:0 + +#define NVA0C0_SET_SPARE00 0x1a30 +#define NVA0C0_SET_SPARE00_V 31:0 + +#define NVA0C0_SET_SPARE01 0x1a34 +#define NVA0C0_SET_SPARE01_V 31:0 + +#define NVA0C0_SET_SPARE02 0x1a38 +#define NVA0C0_SET_SPARE02_V 31:0 + +#define NVA0C0_SET_SPARE03 0x1a3c +#define NVA0C0_SET_SPARE03_V 31:0 + +#define NVA0C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVA0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVA0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVA0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA0C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVA0C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVA0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVA0C0_SET_TRAP_HANDLER 0x260c +#define NVA0C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVA0C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVA0C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_kepler_compute_a_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cla0c0qmd.h b/userspace/sdks/nv570/inc/class/cla0c0qmd.h new file mode 100644 index 0000000..b04ce5b --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cla0c0qmd.h @@ -0,0 +1,658 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __CLA0C0QMD_H__ +#define __CLA0C0QMD_H__ + +/* +** Queue Meta Data, Version 00_06 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_A MW(30:0) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_B MW(31:31) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_C MW(62:32) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_D MW(63:63) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_E MW(94:64) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_F MW(95:95) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_G MW(126:96) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_H MW(127:127) +#define NVA0C0_QMDV00_06_QMD_RESERVED_A_A MW(159:128) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_I MW(191:160) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_J MW(196:192) +#define NVA0C0_QMDV00_06_QMD_RESERVED_A MW(199:197) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K MW(200:200) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L MW(201:201) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_B MW(207:204) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_M MW(222:208) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N MW(223:223) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_O MW(248:224) +#define NVA0C0_QMDV00_06_QMD_RESERVED_C MW(249:249) +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_PROGRAM_OFFSET MW(287:256) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_P MW(319:288) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_Q MW(327:320) +#define NVA0C0_QMDV00_06_QMD_RESERVED_D MW(335:328) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_R MW(351:336) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_S MW(357:352) +#define NVA0C0_QMDV00_06_QMD_RESERVED_E MW(365:358) +#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE MW(369:368) +#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T MW(370:370) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U MW(371:371) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_THROTTLED MW(372:372) +#define NVA0C0_QMDV00_06_THROTTLED_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_THROTTLED_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_E2_A MW(376:376) +#define NVA0C0_QMDV00_06_QMD_RESERVED_E2_B MW(377:377) +#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVA0C0_QMDV00_06_SAMPLER_INDEX MW(382:382) +#define NVA0C0_QMDV00_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVA0C0_QMDV00_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_E3_A MW(383:383) +#define NVA0C0_QMDV00_06_CTA_RASTER_WIDTH MW(415:384) +#define NVA0C0_QMDV00_06_CTA_RASTER_HEIGHT MW(431:416) +#define NVA0C0_QMDV00_06_CTA_RASTER_DEPTH MW(447:432) +#define NVA0C0_QMDV00_06_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVA0C0_QMDV00_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVA0C0_QMDV00_06_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_V MW(535:512) +#define NVA0C0_QMDV00_06_QMD_RESERVED_F MW(542:536) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W MW(543:543) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_SHARED_MEMORY_SIZE MW(561:544) +#define NVA0C0_QMDV00_06_QMD_RESERVED_G MW(575:562) +#define NVA0C0_QMDV00_06_QMD_VERSION MW(579:576) +#define NVA0C0_QMDV00_06_QMD_MAJOR_VERSION MW(583:580) +#define NVA0C0_QMDV00_06_QMD_RESERVED_H MW(591:584) +#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_I MW(668:648) +#define NVA0C0_QMDV00_06_L1_CONFIGURATION MW(671:669) +#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_X MW(703:672) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_Y MW(735:704) +#define NVA0C0_QMDV00_06_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVA0C0_QMDV00_06_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVA0C0_QMDV00_06_QMD_RESERVED_J MW(783:776) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP MW(790:788) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV00_06_QMD_RESERVED_K MW(791:791) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE0_PAYLOAD MW(831:800) +#define NVA0C0_QMDV00_06_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVA0C0_QMDV00_06_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVA0C0_QMDV00_06_QMD_RESERVED_L MW(879:872) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP MW(886:884) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV00_06_QMD_RESERVED_M MW(887:887) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE1_PAYLOAD MW(927:896) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVA0C0_QMDV00_06_QMD_RESERVED_N MW(1466:1464) +#define NVA0C0_QMDV00_06_BARRIER_COUNT MW(1471:1467) +#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVA0C0_QMDV00_06_REGISTER_COUNT MW(1503:1496) +#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVA0C0_QMDV00_06_SASS_VERSION MW(1535:1528) +#define NVA0C0_QMDV00_06_QMD_SPARE_A MW(1567:1536) +#define NVA0C0_QMDV00_06_QMD_SPARE_B MW(1599:1568) +#define NVA0C0_QMDV00_06_QMD_SPARE_C MW(1631:1600) +#define NVA0C0_QMDV00_06_QMD_SPARE_D MW(1663:1632) +#define NVA0C0_QMDV00_06_QMD_SPARE_E MW(1695:1664) +#define NVA0C0_QMDV00_06_QMD_SPARE_F MW(1727:1696) +#define NVA0C0_QMDV00_06_QMD_SPARE_G MW(1759:1728) +#define NVA0C0_QMDV00_06_QMD_SPARE_H MW(1791:1760) +#define NVA0C0_QMDV00_06_QMD_SPARE_I MW(1823:1792) +#define NVA0C0_QMDV00_06_QMD_SPARE_J MW(1855:1824) +#define NVA0C0_QMDV00_06_QMD_SPARE_K MW(1887:1856) +#define NVA0C0_QMDV00_06_QMD_SPARE_L MW(1919:1888) +#define NVA0C0_QMDV00_06_QMD_SPARE_M MW(1951:1920) +#define NVA0C0_QMDV00_06_QMD_SPARE_N MW(1983:1952) +#define NVA0C0_QMDV00_06_DEBUG_ID_UPPER MW(2015:1984) +#define NVA0C0_QMDV00_06_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 01_06 + */ + +#define NVA0C0_QMDV01_06_OUTER_PUT MW(30:0) +#define NVA0C0_QMDV01_06_OUTER_OVERFLOW MW(31:31) +#define NVA0C0_QMDV01_06_OUTER_GET MW(62:32) +#define NVA0C0_QMDV01_06_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVA0C0_QMDV01_06_INNER_GET MW(94:64) +#define NVA0C0_QMDV01_06_INNER_OVERFLOW MW(95:95) +#define NVA0C0_QMDV01_06_INNER_PUT MW(126:96) +#define NVA0C0_QMDV01_06_INNER_STICKY_OVERFLOW MW(127:127) +#define NVA0C0_QMDV01_06_QMD_RESERVED_A_A MW(159:128) +#define NVA0C0_QMDV01_06_SCHEDULER_NEXT_QMD_POINTER MW(191:160) +#define NVA0C0_QMDV01_06_QMD_GROUP_ID MW(197:192) +#define NVA0C0_QMDV01_06_QMD_RESERVED_A MW(199:198) +#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE MW(200:200) +#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_QMD_RESERVED_B MW(207:205) +#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_ADDR MW(222:208) +#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID MW(223:223) +#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVA0C0_QMDV01_06_QMD_RESERVED_C MW(249:249) +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_PROGRAM_OFFSET MW(287:256) +#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVA0C0_QMDV01_06_QMD_RESERVED_D MW(335:328) +#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE MW(369:368) +#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_THROTTLED MW(372:372) +#define NVA0C0_QMDV01_06_THROTTLED_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_THROTTLED_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR MW(376:376) +#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVA0C0_QMDV01_06_SAMPLER_INDEX MW(382:382) +#define NVA0C0_QMDV01_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVA0C0_QMDV01_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVA0C0_QMDV01_06_CTA_RASTER_WIDTH MW(415:384) +#define NVA0C0_QMDV01_06_CTA_RASTER_HEIGHT MW(431:416) +#define NVA0C0_QMDV01_06_CTA_RASTER_DEPTH MW(447:432) +#define NVA0C0_QMDV01_06_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVA0C0_QMDV01_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVA0C0_QMDV01_06_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVA0C0_QMDV01_06_LAUNCH_QUOTA MW(535:512) +#define NVA0C0_QMDV01_06_QMD_RESERVED_F MW(542:536) +#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE MW(543:543) +#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_SHARED_MEMORY_SIZE MW(561:544) +#define NVA0C0_QMDV01_06_QMD_RESERVED_G MW(575:562) +#define NVA0C0_QMDV01_06_QMD_VERSION MW(579:576) +#define NVA0C0_QMDV01_06_QMD_MAJOR_VERSION MW(583:580) +#define NVA0C0_QMDV01_06_QMD_RESERVED_H MW(591:584) +#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_QMD_RESERVED_I MW(668:648) +#define NVA0C0_QMDV01_06_L1_CONFIGURATION MW(671:669) +#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVA0C0_QMDV01_06_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVA0C0_QMDV01_06_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVA0C0_QMDV01_06_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVA0C0_QMDV01_06_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVA0C0_QMDV01_06_QMD_RESERVED_J MW(783:776) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP MW(790:788) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV01_06_QMD_RESERVED_K MW(791:791) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE0_PAYLOAD MW(831:800) +#define NVA0C0_QMDV01_06_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVA0C0_QMDV01_06_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVA0C0_QMDV01_06_QMD_RESERVED_L MW(879:872) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP MW(886:884) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV01_06_QMD_RESERVED_M MW(887:887) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE1_PAYLOAD MW(927:896) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVA0C0_QMDV01_06_QMD_RESERVED_N MW(1466:1464) +#define NVA0C0_QMDV01_06_BARRIER_COUNT MW(1471:1467) +#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVA0C0_QMDV01_06_REGISTER_COUNT MW(1503:1496) +#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVA0C0_QMDV01_06_SASS_VERSION MW(1535:1528) +#define NVA0C0_QMDV01_06_HW_ONLY_INNER_GET MW(1566:1536) +#define NVA0C0_QMDV01_06_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVA0C0_QMDV01_06_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVA0C0_QMDV01_06_HW_ONLY_SCHEDULE_ON_PUT_UPDATE_ENABLE MW(1599:1599) +#define NVA0C0_QMDV01_06_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(1606:1600) +#define NVA0C0_QMDV01_06_QMD_RESERVED_Q MW(1609:1607) +#define NVA0C0_QMDV01_06_COALESCE_WAITING_PERIOD MW(1617:1610) +#define NVA0C0_QMDV01_06_QMD_RESERVED_R MW(1631:1618) +#define NVA0C0_QMDV01_06_QMD_SPARE_D MW(1663:1632) +#define NVA0C0_QMDV01_06_QMD_SPARE_E MW(1695:1664) +#define NVA0C0_QMDV01_06_QMD_SPARE_F MW(1727:1696) +#define NVA0C0_QMDV01_06_QMD_SPARE_G MW(1759:1728) +#define NVA0C0_QMDV01_06_QMD_SPARE_H MW(1791:1760) +#define NVA0C0_QMDV01_06_QMD_SPARE_I MW(1823:1792) +#define NVA0C0_QMDV01_06_QMD_SPARE_J MW(1855:1824) +#define NVA0C0_QMDV01_06_QMD_SPARE_K MW(1887:1856) +#define NVA0C0_QMDV01_06_QMD_SPARE_L MW(1919:1888) +#define NVA0C0_QMDV01_06_QMD_SPARE_M MW(1951:1920) +#define NVA0C0_QMDV01_06_QMD_SPARE_N MW(1983:1952) +#define NVA0C0_QMDV01_06_DEBUG_ID_UPPER MW(2015:1984) +#define NVA0C0_QMDV01_06_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 01_07 + */ + +#define NVA0C0_QMDV01_07_OUTER_PUT MW(30:0) +#define NVA0C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) +#define NVA0C0_QMDV01_07_OUTER_GET MW(62:32) +#define NVA0C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVA0C0_QMDV01_07_INNER_GET MW(94:64) +#define NVA0C0_QMDV01_07_INNER_OVERFLOW MW(95:95) +#define NVA0C0_QMDV01_07_INNER_PUT MW(126:96) +#define NVA0C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) +#define NVA0C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) +#define NVA0C0_QMDV01_07_QMD_GROUP_ID MW(197:192) +#define NVA0C0_QMDV01_07_QMD_RESERVED_A MW(200:198) +#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_QMD_RESERVED_B MW(223:208) +#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVA0C0_QMDV01_07_QMD_RESERVED_C MW(249:249) +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) +#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVA0C0_QMDV01_07_QMD_RESERVED_D MW(335:328) +#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) +#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_THROTTLED MW(372:372) +#define NVA0C0_QMDV01_07_THROTTLED_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_THROTTLED_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) +#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVA0C0_QMDV01_07_SAMPLER_INDEX MW(382:382) +#define NVA0C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVA0C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVA0C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) +#define NVA0C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) +#define NVA0C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) +#define NVA0C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVA0C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVA0C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVA0C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVA0C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) +#define NVA0C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) +#define NVA0C0_QMDV01_07_QMD_RESERVED_G MW(575:562) +#define NVA0C0_QMDV01_07_QMD_VERSION MW(579:576) +#define NVA0C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) +#define NVA0C0_QMDV01_07_QMD_RESERVED_H MW(591:584) +#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_QMD_RESERVED_I MW(668:648) +#define NVA0C0_QMDV01_07_L1_CONFIGURATION MW(671:669) +#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVA0C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVA0C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVA0C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVA0C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVA0C0_QMDV01_07_QMD_RESERVED_J MW(783:776) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV01_07_QMD_RESERVED_K MW(791:791) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) +#define NVA0C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVA0C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVA0C0_QMDV01_07_QMD_RESERVED_L MW(879:872) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV01_07_QMD_RESERVED_M MW(887:887) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVA0C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) +#define NVA0C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) +#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVA0C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) +#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVA0C0_QMDV01_07_SASS_VERSION MW(1535:1528) +#define NVA0C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) +#define NVA0C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVA0C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVA0C0_QMDV01_07_QMD_RESERVED_P MW(1599:1599) +#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVA0C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) +#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVA0C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) +#define NVA0C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) +#define NVA0C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) +#define NVA0C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) +#define NVA0C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) +#define NVA0C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) +#define NVA0C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) +#define NVA0C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) +#define NVA0C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) +#define NVA0C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) +#define NVA0C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) +#define NVA0C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLA0C0QMD_H__ diff --git a/userspace/sdks/nv570/inc/class/cla140.h b/userspace/sdks/nv570/inc/class/cla140.h new file mode 100644 index 0000000..08b8fc1 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cla140.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cla140_h_ +#define _cla140_h_ + +#define KEPLER_INLINE_TO_MEMORY_B 0xA140 + +#endif // _cla140_h_ diff --git a/userspace/sdks/nv570/inc/class/cla16f.h b/userspace/sdks/nv570/inc/class/cla16f.h new file mode 100644 index 0000000..66e7594 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cla16f.h @@ -0,0 +1,254 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cla16f_h_ +#define _cla16f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class KEPLER_CHANNEL_GPFIFO */ +/* + * Documentation for KEPLER_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + */ +#define KEPLER_CHANNEL_GPFIFO_B (0x0000A16F) + +/* pio method data structure */ +typedef volatile struct _cla16f_tag0 { + NvV32 Reserved00[0x7c0]; +} NvA16FTypedef, KEPLER_ChannelGPFifoB; +#define NVA16F_TYPEDEF KEPLER_CHANNELChannelGPFifo +/* dma flow control data structure */ +typedef volatile struct _cla16f_tag1 { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} NvA16FControl, KeplerBControlGPFifo; +/* fields and values */ +#define NVA16F_NUMBER_OF_SUBCHANNELS (8) +#define NVA16F_SET_OBJECT (0x00000000) +#define NVA16F_SET_OBJECT_NVCLASS 15:0 +#define NVA16F_SET_OBJECT_ENGINE 20:16 +#define NVA16F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVA16F_ILLEGAL (0x00000004) +#define NVA16F_ILLEGAL_HANDLE 31:0 +#define NVA16F_NOP (0x00000008) +#define NVA16F_NOP_HANDLE 31:0 +#define NVA16F_SEMAPHOREA (0x00000010) +#define NVA16F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVA16F_SEMAPHOREB (0x00000014) +#define NVA16F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVA16F_SEMAPHOREC (0x00000018) +#define NVA16F_SEMAPHOREC_PAYLOAD 31:0 +#define NVA16F_SEMAPHORED (0x0000001C) +#define NVA16F_SEMAPHORED_OPERATION 4:0 +#define NVA16F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVA16F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVA16F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVA16F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVA16F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 +#define NVA16F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVA16F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVA16F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVA16F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVA16F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVA16F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVA16F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVA16F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVA16F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVA16F_SEMAPHORED_REDUCTION 30:27 +#define NVA16F_SEMAPHORED_REDUCTION_MIN 0x00000000 +#define NVA16F_SEMAPHORED_REDUCTION_MAX 0x00000001 +#define NVA16F_SEMAPHORED_REDUCTION_XOR 0x00000002 +#define NVA16F_SEMAPHORED_REDUCTION_AND 0x00000003 +#define NVA16F_SEMAPHORED_REDUCTION_OR 0x00000004 +#define NVA16F_SEMAPHORED_REDUCTION_ADD 0x00000005 +#define NVA16F_SEMAPHORED_REDUCTION_INC 0x00000006 +#define NVA16F_SEMAPHORED_REDUCTION_DEC 0x00000007 +#define NVA16F_SEMAPHORED_FORMAT 31:31 +#define NVA16F_SEMAPHORED_FORMAT_SIGNED 0x00000000 +#define NVA16F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 +#define NVA16F_NON_STALL_INTERRUPT (0x00000020) +#define NVA16F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVA16F_FB_FLUSH (0x00000024) +#define NVA16F_FB_FLUSH_HANDLE 31:0 +#define NVA16F_MEM_OP_A (0x00000028) +#define NVA16F_MEM_OP_A_OPERAND_LOW 31:2 +#define NVA16F_MEM_OP_A_TLB_INVALIDATE_ADDR 29:2 +#define NVA16F_MEM_OP_A_TLB_INVALIDATE_TARGET 31:30 +#define NVA16F_MEM_OP_A_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000 +#define NVA16F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002 +#define NVA16F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 +#define NVA16F_MEM_OP_B (0x0000002c) +#define NVA16F_MEM_OP_B_OPERAND_HIGH 7:0 +#define NVA16F_MEM_OP_B_OPERATION 31:27 +#define NVA16F_MEM_OP_B_OPERATION_SYSMEMBAR_FLUSH 0x00000005 +#define NVA16F_MEM_OP_B_OPERATION_SOFT_FLUSH 0x00000006 +#define NVA16F_MEM_OP_B_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVA16F_MEM_OP_B_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NVA16F_MEM_OP_B_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +#define NVA16F_MEM_OP_B_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVA16F_MEM_OP_B_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB 0:0 +#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ALL 0x00000001 +#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC 1:1 +#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVA16F_SET_REFERENCE (0x00000050) +#define NVA16F_SET_REFERENCE_COUNT 31:0 +#define NVA16F_WFI (0x00000078) +#define NVA16F_WFI_HANDLE 31:0 +#define NVA16F_CRC_CHECK (0x0000007c) +#define NVA16F_CRC_CHECK_VALUE 31:0 +#define NVA16F_YIELD (0x00000080) +#define NVA16F_YIELD_OP 1:0 +#define NVA16F_YIELD_OP_NOP 0x00000000 + + +/* GPFIFO entry format */ +#define NVA16F_GP_ENTRY__SIZE 8 +#define NVA16F_GP_ENTRY0_FETCH 0:0 +#define NVA16F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVA16F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVA16F_GP_ENTRY0_GET 31:2 +#define NVA16F_GP_ENTRY0_OPERAND 31:0 +#define NVA16F_GP_ENTRY1_GET_HI 7:0 +#define NVA16F_GP_ENTRY1_PRIV 8:8 +#define NVA16F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NVA16F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NVA16F_GP_ENTRY1_LEVEL 9:9 +#define NVA16F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVA16F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVA16F_GP_ENTRY1_LENGTH 30:10 +#define NVA16F_GP_ENTRY1_SYNC 31:31 +#define NVA16F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVA16F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVA16F_GP_ENTRY1_OPCODE 7:0 +#define NVA16F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVA16F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVA16F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVA16F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVA16F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVA16F_DMA_METHOD_ADDRESS 11:0 +#define NVA16F_DMA_SUBDEVICE_MASK 15:4 +#define NVA16F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVA16F_DMA_TERT_OP 17:16 +#define NVA16F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVA16F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVA16F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVA16F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVA16F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVA16F_DMA_METHOD_COUNT_OLD 28:18 +#define NVA16F_DMA_METHOD_COUNT 28:16 +#define NVA16F_DMA_IMMD_DATA 28:16 +#define NVA16F_DMA_SEC_OP 31:29 +#define NVA16F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVA16F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVA16F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVA16F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVA16F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVA16F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVA16F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVA16F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVA16F_DMA_INCR_ADDRESS 11:0 +#define NVA16F_DMA_INCR_SUBCHANNEL 15:13 +#define NVA16F_DMA_INCR_COUNT 28:16 +#define NVA16F_DMA_INCR_OPCODE 31:29 +#define NVA16F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVA16F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVA16F_DMA_NONINCR_ADDRESS 11:0 +#define NVA16F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVA16F_DMA_NONINCR_COUNT 28:16 +#define NVA16F_DMA_NONINCR_OPCODE 31:29 +#define NVA16F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVA16F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVA16F_DMA_ONEINCR_ADDRESS 11:0 +#define NVA16F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVA16F_DMA_ONEINCR_COUNT 28:16 +#define NVA16F_DMA_ONEINCR_OPCODE 31:29 +#define NVA16F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVA16F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVA16F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVA16F_DMA_IMMD_ADDRESS 11:0 +#define NVA16F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVA16F_DMA_IMMD_DATA 28:16 +#define NVA16F_DMA_IMMD_OPCODE 31:29 +#define NVA16F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVA16F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVA16F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA16F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVA16F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVA16F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA16F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVA16F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA16F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVA16F_DMA_ENDSEG_OPCODE 31:29 +#define NVA16F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVA16F_DMA_ADDRESS 12:2 +#define NVA16F_DMA_SUBCH 15:13 +#define NVA16F_DMA_OPCODE3 17:16 +#define NVA16F_DMA_OPCODE3_NONE (0x00000000) +#define NVA16F_DMA_COUNT 28:18 +#define NVA16F_DMA_OPCODE 31:29 +#define NVA16F_DMA_OPCODE_METHOD (0x00000000) +#define NVA16F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVA16F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cla16F_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cla16fsw.h b/userspace/sdks/nv570/inc/class/cla16fsw.h new file mode 100644 index 0000000..cea256f --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cla16fsw.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cla16f_sw_h_ +#define _cla16f_sw_h_ + +#define NVA16F_NOTIFIERS_RC (0) +#define NVA16F_NOTIFIERS_REFCNT (1) +#define NVA16F_NOTIFIERS_NONSTALL (2) +#define NVA16F_NOTIFIERS_EVENTBUFFER (3) +#define NVA16F_NOTIFIERS_IDLECHANNEL (4) +#define NVA16F_NOTIFIERS_ENDCTX (5) +#define NVA16F_NOTIFIERS_SW (6) +#define NVA16F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVA16F_NOTIFIERS_MAXCOUNT (8) + +/* NvNotification[] fields and values */ +#define NVA16F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVA16F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _cla16f_sw_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cla197.h b/userspace/sdks/nv570/inc/class/cla197.h new file mode 100644 index 0000000..deae603 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cla197.h @@ -0,0 +1,3826 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_kepler_b_h_ +#define _cl_kepler_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl kepler_b */ + +#include "nvtypes.h" + +#define KEPLER_B 0xA197 + +#define NVA197_SET_OBJECT 0x0000 +#define NVA197_SET_OBJECT_CLASS_ID 15:0 +#define NVA197_SET_OBJECT_ENGINE_ID 20:16 + +#define NVA197_NO_OPERATION 0x0100 +#define NVA197_NO_OPERATION_V 31:0 + +#define NVA197_SET_NOTIFY_A 0x0104 +#define NVA197_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVA197_SET_NOTIFY_B 0x0108 +#define NVA197_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVA197_NOTIFY 0x010c +#define NVA197_NOTIFY_TYPE 31:0 +#define NVA197_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVA197_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVA197_WAIT_FOR_IDLE 0x0110 +#define NVA197_WAIT_FOR_IDLE_V 31:0 + +#define NVA197_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVA197_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVA197_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVA197_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVA197_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVA197_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVA197_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVA197_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVA197_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVA197_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVA197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVA197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVA197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVA197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVA197_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVA197_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVA197_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVA197_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVA197_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA197_SEND_GO_IDLE 0x013c +#define NVA197_SEND_GO_IDLE_V 31:0 + +#define NVA197_PM_TRIGGER 0x0140 +#define NVA197_PM_TRIGGER_V 31:0 + +#define NVA197_PM_TRIGGER_WFI 0x0144 +#define NVA197_PM_TRIGGER_WFI_V 31:0 + +#define NVA197_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVA197_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVA197_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVA197_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVA197_LINE_LENGTH_IN 0x0180 +#define NVA197_LINE_LENGTH_IN_VALUE 31:0 + +#define NVA197_LINE_COUNT 0x0184 +#define NVA197_LINE_COUNT_VALUE 31:0 + +#define NVA197_OFFSET_OUT_UPPER 0x0188 +#define NVA197_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVA197_OFFSET_OUT 0x018c +#define NVA197_OFFSET_OUT_VALUE 31:0 + +#define NVA197_PITCH_OUT 0x0190 +#define NVA197_PITCH_OUT_VALUE 31:0 + +#define NVA197_SET_DST_BLOCK_SIZE 0x0194 +#define NVA197_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVA197_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVA197_SET_DST_WIDTH 0x0198 +#define NVA197_SET_DST_WIDTH_V 31:0 + +#define NVA197_SET_DST_HEIGHT 0x019c +#define NVA197_SET_DST_HEIGHT_V 31:0 + +#define NVA197_SET_DST_DEPTH 0x01a0 +#define NVA197_SET_DST_DEPTH_V 31:0 + +#define NVA197_SET_DST_LAYER 0x01a4 +#define NVA197_SET_DST_LAYER_V 31:0 + +#define NVA197_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVA197_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVA197_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVA197_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVA197_LAUNCH_DMA 0x01b0 +#define NVA197_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVA197_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA197_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA197_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVA197_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVA197_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVA197_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVA197_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVA197_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVA197_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVA197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVA197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVA197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVA197_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVA197_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA197_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA197_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA197_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVA197_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA197_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA197_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVA197_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVA197_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVA197_LOAD_INLINE_DATA 0x01b4 +#define NVA197_LOAD_INLINE_DATA_V 31:0 + +#define NVA197_SET_I2M_SEMAPHORE_A 0x01dc +#define NVA197_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVA197_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVA197_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA197_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVA197_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVA197_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVA197_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVA197_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVA197_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVA197_SET_I2M_SPARE_NOOP03 0x01fc +#define NVA197_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVA197_RUN_DS_NOW 0x0200 +#define NVA197_RUN_DS_NOW_V 31:0 + +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVA197_SET_RASTER_PIPE_SYNC_CONTROL 0x0208 +#define NVA197_SET_RASTER_PIPE_SYNC_CONTROL_PRIM_AREA_THRESHOLD 21:0 +#define NVA197_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE 24:24 +#define NVA197_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE_FALSE 0x00000000 +#define NVA197_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVA197_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVA197_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVA197_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVA197_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVA197_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_GS_DM_FIFO 0x0214 +#define NVA197_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVA197_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVA197_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVA197_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVA197_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA197_INVALIDATE_SHADER_CACHES 0x021c +#define NVA197_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVA197_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVA197_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVA197_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVA197_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVA197_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVA197_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVA197_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVA197_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVA197_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVA197_SET_VAB_VERTEX3F(i) (0x0220+(i)*4) +#define NVA197_SET_VAB_VERTEX3F_V 31:0 + +#define NVA197_SET_VAB_VERTEX4F(i) (0x0230+(i)*4) +#define NVA197_SET_VAB_VERTEX4F_V 31:0 + +#define NVA197_SET_VAB_NORMAL3F(i) (0x0240+(i)*4) +#define NVA197_SET_VAB_NORMAL3F_V 31:0 + +#define NVA197_SET_VAB_COLOR3F(i) (0x0250+(i)*4) +#define NVA197_SET_VAB_COLOR3F_V 31:0 + +#define NVA197_SET_VAB_COLOR4F(i) (0x0260+(i)*4) +#define NVA197_SET_VAB_COLOR4F_V 31:0 + +#define NVA197_SET_VAB_COLOR4UB(i) (0x0270+(i)*4) +#define NVA197_SET_VAB_COLOR4UB_V 31:0 + +#define NVA197_SET_VAB_TEX_COORD1F(i) (0x0280+(i)*4) +#define NVA197_SET_VAB_TEX_COORD1F_V 31:0 + +#define NVA197_SET_VAB_TEX_COORD2F(i) (0x0290+(i)*4) +#define NVA197_SET_VAB_TEX_COORD2F_V 31:0 + +#define NVA197_SET_VAB_TEX_COORD3F(i) (0x02a0+(i)*4) +#define NVA197_SET_VAB_TEX_COORD3F_V 31:0 + +#define NVA197_SET_VAB_TEX_COORD4F(i) (0x02b0+(i)*4) +#define NVA197_SET_VAB_TEX_COORD4F_V 31:0 + +#define NVA197_SET_GLOBAL_LOAD_VIA_TEXTURE 0x02c4 +#define NVA197_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE 0:0 +#define NVA197_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE_TRUE 0x00000001 +#define NVA197_SET_GLOBAL_LOAD_VIA_TEXTURE_HEADER_INDEX 23:4 + +#define NVA197_SET_TASK_CIRCULAR_BUFFER_THROTTLE 0x02cc +#define NVA197_SET_TASK_CIRCULAR_BUFFER_THROTTLE_TASK_COUNT 21:0 + +#define NVA197_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NVA197_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NVA197_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVA197_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVA197_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVA197_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 9:0 + +#define NVA197_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVA197_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVA197_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVA197_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVA197_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVA197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVA197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVA197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVA197_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVA197_SET_ZCULL_SUBREGION 0x02e8 +#define NVA197_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVA197_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVA197_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVA197_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVA197_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVA197_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVA197_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVA197_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVA197_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVA197_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVA197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVA197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVA197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVA197_DRAW_ZERO_INDEX 0x0304 +#define NVA197_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVA197_SET_L1_CONFIGURATION 0x0308 +#define NVA197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVA197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVA197_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVA197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVA197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVA197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVA197_SET_SPA_VERSION 0x0310 +#define NVA197_SET_SPA_VERSION_MINOR 7:0 +#define NVA197_SET_SPA_VERSION_MAJOR 15:8 + +#define NVA197_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NVA197_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NVA197_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_SNAP_GRID_LINE 0x0318 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVA197_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVA197_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVA197_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVA197_SET_SNAP_GRID_NON_LINE 0x031c +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVA197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVA197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVA197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVA197_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVA197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVA197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVA197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVA197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVA197_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVA197_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVA197_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVA197_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVA197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVA197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVA197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVA197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVA197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVA197_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVA197_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVA197_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVA197_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVA197_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVA197_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVA197_SET_TESSELLATION_LOD_V1 0x0330 +#define NVA197_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVA197_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVA197_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVA197_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVA197_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVA197_RESERVED_TG07 0x033c +#define NVA197_RESERVED_TG07_V 0:0 + +#define NVA197_RESERVED_TG08 0x0340 +#define NVA197_RESERVED_TG08_V 0:0 + +#define NVA197_RESERVED_TG09 0x0344 +#define NVA197_RESERVED_TG09_V 0:0 + +#define NVA197_RESERVED_TG10 0x0348 +#define NVA197_RESERVED_TG10_V 0:0 + +#define NVA197_RESERVED_TG11 0x034c +#define NVA197_RESERVED_TG11_V 0:0 + +#define NVA197_RESERVED_TG12 0x0350 +#define NVA197_RESERVED_TG12_V 0:0 + +#define NVA197_RESERVED_TG13 0x0354 +#define NVA197_RESERVED_TG13_V 0:0 + +#define NVA197_RESERVED_TG14 0x0358 +#define NVA197_RESERVED_TG14_V 0:0 + +#define NVA197_RESERVED_TG15 0x035c +#define NVA197_RESERVED_TG15_V 0:0 + +#define NVA197_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVA197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVA197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVA197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVA197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVA197_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVA197_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVA197_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVA197_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVA197_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVA197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVA197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVA197_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVA197_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVA197_SET_RASTER_ENABLE 0x037c +#define NVA197_SET_RASTER_ENABLE_V 0:0 +#define NVA197_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVA197_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVA197_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVA197_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVA197_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVA197_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVA197_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVA197_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVA197_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVA197_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVA197_SET_VAB_DATA_TYPELESS(i) (0x0400+(i)*4) +#define NVA197_SET_VAB_DATA_TYPELESS_V 31:0 + +#define NVA197_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVA197_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVA197_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVA197_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVA197_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVA197_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVA197_SET_RASTER_INPUT 0x0740 +#define NVA197_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVA197_SET_STREAM_OUTPUT 0x0744 +#define NVA197_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVA197_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVA197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVA197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_ALPHA_FRACTION 0x074c +#define NVA197_SET_ALPHA_FRACTION_V 7:0 + +#define NVA197_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVA197_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVA197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVA197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVA197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 + +#define NVA197_SET_MAX_TI_WARPS_PER_BATCH 0x075c +#define NVA197_SET_MAX_TI_WARPS_PER_BATCH_V 5:0 + +#define NVA197_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVA197_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA197_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVA197_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVA197_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVA197_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVA197_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVA197_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVA197_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVA197_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVA197_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVA197_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVA197_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVA197_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVA197_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVA197_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVA197_SET_ISBE_SAVE_RESTORE_PROGRAM 0x07ac +#define NVA197_SET_ISBE_SAVE_RESTORE_PROGRAM_OFFSET 31:0 + +#define NVA197_SET_VAB_VERTEX2F(i) (0x07b0+(i)*4) +#define NVA197_SET_VAB_VERTEX2F_V 31:0 + +#define NVA197_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVA197_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVA197_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVA197_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVA197_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVA197_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVA197_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVA197_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVA197_SET_CULL_BEFORE_FETCH 0x07dc +#define NVA197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVA197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVA197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVA197_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVA197_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVA197_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVA197_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVA197_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVA197_SET_ZCULL_STORAGE_A 0x07e8 +#define NVA197_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVA197_SET_ZCULL_STORAGE_B 0x07ec +#define NVA197_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVA197_SET_ZCULL_STORAGE_C 0x07f0 +#define NVA197_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVA197_SET_ZCULL_STORAGE_D 0x07f4 +#define NVA197_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVA197_SET_ZT_READ_ONLY 0x07f8 +#define NVA197_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVA197_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVA197_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVA197_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVA197_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVA197_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVA197_SET_TEXTURE_INSTRUCTION_OPERAND 0x07fc +#define NVA197_SET_TEXTURE_INSTRUCTION_OPERAND_ORDERING 0:0 +#define NVA197_SET_TEXTURE_INSTRUCTION_OPERAND_ORDERING_FERMI_ORDER 0x00000000 +#define NVA197_SET_TEXTURE_INSTRUCTION_OPERAND_ORDERING_KEPLER_ORDER 0x00000001 + +#define NVA197_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVA197_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVA197_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVA197_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVA197_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVA197_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVA197_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVA197_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVA197_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVA197_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVA197_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVA197_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVA197_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVA197_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVA197_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVA197_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVA197_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVA197_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVA197_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA197_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVA197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVA197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVA197_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVA197_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVA197_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVA197_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVA197_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVA197_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVA197_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NVA197_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NVA197_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVA197_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVA197_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVA197_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVA197_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVA197_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVA197_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVA197_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVA197_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVA197_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVA197_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVA197_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVA197_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVA197_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVA197_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVA197_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVA197_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVA197_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVA197_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVA197_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVA197_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVA197_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVA197_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVA197_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVA197_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVA197_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVA197_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVA197_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVA197_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVA197_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVA197_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVA197_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVA197_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVA197_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVA197_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVA197_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVA197_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVA197_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVA197_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVA197_SET_STATISTICS_COUNTER 0x0d68 +#define NVA197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVA197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVA197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVA197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVA197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVA197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVA197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVA197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVA197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVA197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVA197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVA197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVA197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVA197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVA197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVA197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVA197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVA197_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVA197_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVA197_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVA197_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVA197_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVA197_SET_VERTEX_ARRAY_START 0x0d74 +#define NVA197_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVA197_DRAW_VERTEX_ARRAY 0x0d78 +#define NVA197_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVA197_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVA197_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVA197_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVA197_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVA197_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVA197_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVA197_SET_Z_CLEAR_VALUE 0x0d90 +#define NVA197_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVA197_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVA197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVA197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVA197_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVA197_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVA197_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVA197_SET_FRONT_POLYGON_MODE 0x0dac +#define NVA197_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVA197_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVA197_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVA197_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVA197_SET_BACK_POLYGON_MODE 0x0db0 +#define NVA197_SET_BACK_POLYGON_MODE_V 31:0 +#define NVA197_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVA197_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVA197_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVA197_SET_POLY_SMOOTH 0x0db4 +#define NVA197_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVA197_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVA197_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_ZT_MARK 0x0db8 +#define NVA197_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NVA197_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVA197_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVA197_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVA197_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVA197_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVA197_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVA197_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVA197_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVA197_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVA197_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVA197_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVA197_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_PATCH 0x0dcc +#define NVA197_SET_PATCH_SIZE 7:0 + +#define NVA197_SET_ZCULL_CRITERION 0x0dd8 +#define NVA197_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVA197_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVA197_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVA197_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVA197_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVA197_SET_ZCULL_CRITERION_SREF 23:16 +#define NVA197_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVA197_SET_SM_QUADRANT_SELECTION_CONTROL 0x0ddc +#define NVA197_SET_SM_QUADRANT_SELECTION_CONTROL_MAX_PIXEL_WARPS 7:0 + +#define NVA197_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVA197_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVA197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVA197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVA197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_DRAW_INLINE_VERTEX_VAB_UPDATE 0x0dec +#define NVA197_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE 0:0 +#define NVA197_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_WINDOW_OFFSET_X 0x0df8 +#define NVA197_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVA197_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVA197_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVA197_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVA197_SET_SCISSOR_ENABLE_V 0:0 +#define NVA197_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVA197_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVA197_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVA197_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVA197_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVA197_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVA197_SET_VAB_NORMAL3S(i) (0x0f00+(i)*4) +#define NVA197_SET_VAB_NORMAL3S_V 31:0 + +#define NVA197_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVA197_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVA197_SET_BACK_STENCIL_MASK 0x0f58 +#define NVA197_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVA197_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVA197_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVA197_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVA197_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVA197_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVA197_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVA197_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVA197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVA197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVA197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVA197_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVA197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVA197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVA197_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVA197_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVA197_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVA197_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVA197_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVA197_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVA197_SET_CT_MRT_ENABLE 0x0fac +#define NVA197_SET_CT_MRT_ENABLE_V 0:0 +#define NVA197_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVA197_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVA197_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVA197_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVA197_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVA197_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVA197_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVA197_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVA197_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVA197_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVA197_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVA197_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVA197_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVA197_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVA197_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVA197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVA197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVA197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVA197_SET_ZT_A 0x0fe0 +#define NVA197_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_ZT_B 0x0fe4 +#define NVA197_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_ZT_FORMAT 0x0fe8 +#define NVA197_SET_ZT_FORMAT_V 4:0 +#define NVA197_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVA197_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVA197_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVA197_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVA197_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVA197_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVA197_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVA197_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVA197_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVA197_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVA197_SET_ZT_BLOCK_SIZE 0x0fec +#define NVA197_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVA197_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA197_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVA197_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVA197_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVA197_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVA197_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVA197_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVA197_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVA197_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVA197_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVA197_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA197_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVA197_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVA197_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVA197_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVA197_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVA197_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVA197_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVA197_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVA197_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVA197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVA197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVA197_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVA197_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVA197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVA197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_SPARE_NOOP00 0x1040 +#define NVA197_SET_SPARE_NOOP00_V 31:0 + +#define NVA197_SET_SPARE_NOOP01 0x1044 +#define NVA197_SET_SPARE_NOOP01_V 31:0 + +#define NVA197_SET_SPARE_NOOP02 0x1048 +#define NVA197_SET_SPARE_NOOP02_V 31:0 + +#define NVA197_SET_SPARE_NOOP03 0x104c +#define NVA197_SET_SPARE_NOOP03_V 31:0 + +#define NVA197_SET_SPARE_NOOP04 0x1050 +#define NVA197_SET_SPARE_NOOP04_V 31:0 + +#define NVA197_SET_SPARE_NOOP05 0x1054 +#define NVA197_SET_SPARE_NOOP05_V 31:0 + +#define NVA197_SET_SPARE_NOOP06 0x1058 +#define NVA197_SET_SPARE_NOOP06_V 31:0 + +#define NVA197_SET_SPARE_NOOP07 0x105c +#define NVA197_SET_SPARE_NOOP07_V 31:0 + +#define NVA197_SET_SPARE_NOOP08 0x1060 +#define NVA197_SET_SPARE_NOOP08_V 31:0 + +#define NVA197_SET_SPARE_NOOP09 0x1064 +#define NVA197_SET_SPARE_NOOP09_V 31:0 + +#define NVA197_SET_SPARE_NOOP10 0x1068 +#define NVA197_SET_SPARE_NOOP10_V 31:0 + +#define NVA197_SET_SPARE_NOOP11 0x106c +#define NVA197_SET_SPARE_NOOP11_V 31:0 + +#define NVA197_SET_SPARE_NOOP12 0x1070 +#define NVA197_SET_SPARE_NOOP12_V 31:0 + +#define NVA197_SET_SPARE_NOOP13 0x1074 +#define NVA197_SET_SPARE_NOOP13_V 31:0 + +#define NVA197_SET_SPARE_NOOP14 0x1078 +#define NVA197_SET_SPARE_NOOP14_V 31:0 + +#define NVA197_SET_SPARE_NOOP15 0x107c +#define NVA197_SET_SPARE_NOOP15_V 31:0 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVA197_UNBIND_ALL 0x10f4 +#define NVA197_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVA197_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVA197_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVA197_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA197_NO_OPERATION_DATA_HI 0x110c +#define NVA197_NO_OPERATION_DATA_HI_V 31:0 + +#define NVA197_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVA197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVA197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVA197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVA197_PM_TRIGGER_END 0x1114 +#define NVA197_PM_TRIGGER_END_V 31:0 + +#define NVA197_SET_VERTEX_ID_BASE 0x1118 +#define NVA197_SET_VERTEX_ID_BASE_V 31:0 + +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVA197_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVA197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVA197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVA197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVA197_FLUSH_PENDING_WRITES 0x1144 +#define NVA197_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVA197_SET_VAB_DATA_CONTROL 0x114c +#define NVA197_SET_VAB_DATA_CONTROL_VAB_INDEX 7:0 +#define NVA197_SET_VAB_DATA_CONTROL_COMPONENT_COUNT 10:8 +#define NVA197_SET_VAB_DATA_CONTROL_COMPONENT_BYTE_WIDTH 14:12 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT 18:16 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_SNORM 0x00000001 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_UNORM 0x00000002 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_SINT 0x00000003 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_UINT 0x00000004 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_USCALED 0x00000005 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_SSCALED 0x00000006 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_FLOAT 0x00000007 + +#define NVA197_SET_VAB_DATA(i) (0x1150+(i)*4) +#define NVA197_SET_VAB_DATA_V 31:0 + +#define NVA197_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVA197_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVA197_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVA197_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_SET_CT_SELECT 0x121c +#define NVA197_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVA197_SET_CT_SELECT_TARGET0 6:4 +#define NVA197_SET_CT_SELECT_TARGET1 9:7 +#define NVA197_SET_CT_SELECT_TARGET2 12:10 +#define NVA197_SET_CT_SELECT_TARGET3 15:13 +#define NVA197_SET_CT_SELECT_TARGET4 18:16 +#define NVA197_SET_CT_SELECT_TARGET5 21:19 +#define NVA197_SET_CT_SELECT_TARGET6 24:22 +#define NVA197_SET_CT_SELECT_TARGET7 27:25 + +#define NVA197_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVA197_SET_ZT_SIZE_A 0x1228 +#define NVA197_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVA197_SET_ZT_SIZE_B 0x122c +#define NVA197_SET_ZT_SIZE_B_HEIGHT 16:0 + +#define NVA197_SET_ZT_SIZE_C 0x1230 +#define NVA197_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVA197_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVA197_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVA197_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVA197_SET_SAMPLER_BINDING 0x1234 +#define NVA197_SET_SAMPLER_BINDING_V 0:0 +#define NVA197_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVA197_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVA197_DRAW_AUTO 0x123c +#define NVA197_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVA197_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVA197_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 9:0 + +#define NVA197_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVA197_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVA197_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA197_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVA197_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVA197_SET_SHADER_SCHEDULING 0x12ac +#define NVA197_SET_SHADER_SCHEDULING_MODE 0:0 +#define NVA197_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 +#define NVA197_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 + +#define NVA197_CLEAR_ZCULL_REGION 0x12c8 +#define NVA197_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVA197_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVA197_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVA197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVA197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVA197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVA197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVA197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVA197_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVA197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVA197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVA197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVA197_SET_DEPTH_TEST 0x12cc +#define NVA197_SET_DEPTH_TEST_ENABLE 0:0 +#define NVA197_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_FILL_MODE 0x12d0 +#define NVA197_SET_FILL_MODE_V 31:0 +#define NVA197_SET_FILL_MODE_V_POINT 0x00000001 +#define NVA197_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVA197_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVA197_SET_SHADE_MODE 0x12d4 +#define NVA197_SET_SHADE_MODE_V 31:0 +#define NVA197_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVA197_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVA197_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVA197_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVA197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVA197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVA197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVA197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVA197_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVA197_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVA197_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVA197_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_DEPTH_WRITE 0x12e8 +#define NVA197_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVA197_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_ALPHA_TEST 0x12ec +#define NVA197_SET_ALPHA_TEST_ENABLE 0:0 +#define NVA197_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVA197_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVA197_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVA197_DRAW_INLINE_INDEX4X8 0x1304 +#define NVA197_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVA197_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVA197_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVA197_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVA197_D3D_SET_CULL_MODE 0x1308 +#define NVA197_D3D_SET_CULL_MODE_V 31:0 +#define NVA197_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVA197_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVA197_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVA197_SET_DEPTH_FUNC 0x130c +#define NVA197_SET_DEPTH_FUNC_V 31:0 +#define NVA197_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVA197_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVA197_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA197_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA197_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVA197_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA197_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA197_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA197_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVA197_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVA197_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA197_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA197_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVA197_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA197_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA197_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA197_SET_ALPHA_REF 0x1310 +#define NVA197_SET_ALPHA_REF_V 31:0 + +#define NVA197_SET_ALPHA_FUNC 0x1314 +#define NVA197_SET_ALPHA_FUNC_V 31:0 +#define NVA197_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVA197_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVA197_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA197_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA197_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVA197_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA197_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA197_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA197_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVA197_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVA197_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA197_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA197_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVA197_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA197_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA197_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA197_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVA197_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVA197_SET_BLEND_CONST_RED 0x131c +#define NVA197_SET_BLEND_CONST_RED_V 31:0 + +#define NVA197_SET_BLEND_CONST_GREEN 0x1320 +#define NVA197_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVA197_SET_BLEND_CONST_BLUE 0x1324 +#define NVA197_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVA197_SET_BLEND_CONST_ALPHA 0x1328 +#define NVA197_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVA197_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVA197_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVA197_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVA197_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVA197_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVA197_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVA197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVA197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVA197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_BLEND_COLOR_OP 0x1340 +#define NVA197_SET_BLEND_COLOR_OP_V 31:0 +#define NVA197_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA197_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA197_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA197_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVA197_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVA197_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVA197_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA197_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA197_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVA197_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_BLEND_ALPHA_OP 0x134c +#define NVA197_SET_BLEND_ALPHA_OP_V 31:0 +#define NVA197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA197_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVA197_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVA197_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVA197_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA197_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA197_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVA197_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVA197_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVA197_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVA197_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_SINGLE_ROP_CONTROL 0x135c +#define NVA197_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVA197_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_BLEND(i) (0x1360+(i)*4) +#define NVA197_SET_BLEND_ENABLE 0:0 +#define NVA197_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVA197_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_STENCIL_TEST 0x1380 +#define NVA197_SET_STENCIL_TEST_ENABLE 0:0 +#define NVA197_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_STENCIL_OP_FAIL 0x1384 +#define NVA197_SET_STENCIL_OP_FAIL_V 31:0 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVA197_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVA197_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVA197_SET_STENCIL_OP_ZPASS 0x138c +#define NVA197_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVA197_SET_STENCIL_FUNC 0x1390 +#define NVA197_SET_STENCIL_FUNC_V 31:0 +#define NVA197_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVA197_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVA197_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA197_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA197_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVA197_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA197_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA197_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA197_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVA197_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVA197_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA197_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA197_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVA197_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA197_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA197_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA197_SET_STENCIL_FUNC_REF 0x1394 +#define NVA197_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVA197_SET_STENCIL_FUNC_MASK 0x1398 +#define NVA197_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVA197_SET_STENCIL_MASK 0x139c +#define NVA197_SET_STENCIL_MASK_V 7:0 + +#define NVA197_SET_DRAW_AUTO_START 0x13a4 +#define NVA197_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVA197_SET_PS_SATURATE 0x13a8 +#define NVA197_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVA197_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVA197_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVA197_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVA197_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVA197_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVA197_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVA197_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVA197_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 + +#define NVA197_SET_WINDOW_ORIGIN 0x13ac +#define NVA197_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVA197_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVA197_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVA197_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVA197_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVA197_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVA197_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVA197_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVA197_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVA197_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVA197_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVA197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVA197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_ALPHA_HYSTERESIS 0x1420 +#define NVA197_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NVA197_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVA197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVA197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA197_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVA197_INVALIDATE_DA_DMA_CACHE 0x142c +#define NVA197_INVALIDATE_DA_DMA_CACHE_V 0:0 + +#define NVA197_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVA197_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVA197_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVA197_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVA197_SET_PS_WARP_WATERMARKS 0x1450 +#define NVA197_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVA197_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVA197_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVA197_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVA197_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVA197_STORE_ZCULL 0x1464 +#define NVA197_STORE_ZCULL_V 0:0 + +#define NVA197_LOAD_ZCULL 0x1500 +#define NVA197_LOAD_ZCULL_V 0:0 + +#define NVA197_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVA197_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVA197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVA197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVA197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVA197_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVA197_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVA197_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVA197_SET_USER_CLIP_ENABLE 0x1510 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVA197_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVA197_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVA197_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_POINT_SIZE 0x1518 +#define NVA197_SET_POINT_SIZE_V 31:0 + +#define NVA197_SET_ZCULL_STATS 0x151c +#define NVA197_SET_ZCULL_STATS_ENABLE 0:0 +#define NVA197_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_POINT_SPRITE 0x1520 +#define NVA197_SET_POINT_SPRITE_ENABLE 0:0 +#define NVA197_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_SHADER_EXCEPTIONS 0x1528 +#define NVA197_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVA197_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVA197_CLEAR_REPORT_VALUE 0x1530 +#define NVA197_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVA197_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVA197_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVA197_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVA197_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVA197_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVA197_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 + +#define NVA197_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVA197_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVA197_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_ZT_SELECT 0x1538 +#define NVA197_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVA197_SET_RENDER_ENABLE_A 0x1550 +#define NVA197_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_RENDER_ENABLE_B 0x1554 +#define NVA197_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_RENDER_ENABLE_C 0x1558 +#define NVA197_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVA197_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA197_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA197_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA197_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA197_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA197_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVA197_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVA197_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVA197_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVA197_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVA197_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVA197_SET_ANTI_ALIASED_LINE 0x1570 +#define NVA197_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVA197_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_TEX_HEADER_POOL_A 0x1574 +#define NVA197_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_TEX_HEADER_POOL_B 0x1578 +#define NVA197_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_TEX_HEADER_POOL_C 0x157c +#define NVA197_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVA197_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVA197_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVA197_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVA197_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVA197_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVA197_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVA197_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVA197_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVA197_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA197_SET_SRGB_WRITE 0x15b8 +#define NVA197_SET_SRGB_WRITE_ENABLE 0:0 +#define NVA197_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_DEPTH_BIAS 0x15bc +#define NVA197_SET_DEPTH_BIAS_V 31:0 + +#define NVA197_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVA197_SET_RT_LAYER 0x15cc +#define NVA197_SET_RT_LAYER_V 15:0 +#define NVA197_SET_RT_LAYER_CONTROL 16:16 +#define NVA197_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVA197_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVA197_SET_ANTI_ALIAS 0x15d0 +#define NVA197_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVA197_SET_EDGE_FLAG 0x15e4 +#define NVA197_SET_EDGE_FLAG_V 0:0 +#define NVA197_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVA197_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVA197_DRAW_INLINE_INDEX 0x15e8 +#define NVA197_DRAW_INLINE_INDEX_V 31:0 + +#define NVA197_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVA197_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVA197_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVA197_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVA197_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVA197_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVA197_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVA197_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVA197_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVA197_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVA197_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVA197_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVA197_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVA197_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVA197_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVA197_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVA197_SET_POINT_SPRITE_SELECT 0x1604 +#define NVA197_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVA197_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVA197_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVA197_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVA197_SET_PROGRAM_REGION_A 0x1608 +#define NVA197_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVA197_SET_PROGRAM_REGION_B 0x160c +#define NVA197_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVA197_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVA197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVA197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVA197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVA197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVA197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVA197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVA197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVA197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVA197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVA197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVA197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVA197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVA197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVA197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVA197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVA197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVA197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVA197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVA197_END 0x1614 +#define NVA197_END_V 0:0 + +#define NVA197_BEGIN 0x1618 +#define NVA197_BEGIN_OP 15:0 +#define NVA197_BEGIN_OP_POINTS 0x00000000 +#define NVA197_BEGIN_OP_LINES 0x00000001 +#define NVA197_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVA197_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVA197_BEGIN_OP_TRIANGLES 0x00000004 +#define NVA197_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVA197_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVA197_BEGIN_OP_QUADS 0x00000007 +#define NVA197_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVA197_BEGIN_OP_POLYGON 0x00000009 +#define NVA197_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVA197_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVA197_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_BEGIN_OP_PATCH 0x0000000E +#define NVA197_BEGIN_PRIMITIVE_ID 24:24 +#define NVA197_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVA197_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVA197_BEGIN_INSTANCE_ID 27:26 +#define NVA197_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVA197_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVA197_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVA197_BEGIN_SPLIT_MODE 30:29 +#define NVA197_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVA197_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVA197_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVA197_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 + +#define NVA197_SET_VERTEX_ID_COPY 0x161c +#define NVA197_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVA197_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVA197_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVA197_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVA197_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVA197_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVA197_LOAD_PRIMITIVE_ID 0x1624 +#define NVA197_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVA197_SET_SHADER_BASED_CULL 0x162c +#define NVA197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVA197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVA197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVA197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_CLASS_VERSION 0x1638 +#define NVA197_SET_CLASS_VERSION_CURRENT 15:0 +#define NVA197_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA197_SET_VAB_PAGE 0x163c +#define NVA197_SET_VAB_PAGE_READ_SELECT 0:0 +#define NVA197_SET_VAB_PAGE_READ_SELECT_PAGES_0_AND_1 0x00000000 +#define NVA197_SET_VAB_PAGE_READ_SELECT_PAGES_0_AND_2 0x00000001 + +#define NVA197_DRAW_INLINE_VERTEX 0x1640 +#define NVA197_DRAW_INLINE_VERTEX_V 31:0 + +#define NVA197_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVA197_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVA197_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVA197_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVA197_SET_DA_OUTPUT 0x164c +#define NVA197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVA197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVA197_SET_ANTI_ALIASED_POINT 0x1658 +#define NVA197_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVA197_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_POINT_CENTER_MODE 0x165c +#define NVA197_SET_POINT_CENTER_MODE_V 31:0 +#define NVA197_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVA197_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVA197_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVA197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVA197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVA197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVA197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVA197_SET_LINE_STIPPLE 0x166c +#define NVA197_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVA197_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVA197_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVA197_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVA197_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVA197_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVA197_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVA197_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVA197_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVA197_SET_PROVOKING_VERTEX 0x1684 +#define NVA197_SET_PROVOKING_VERTEX_V 0:0 +#define NVA197_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVA197_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVA197_SET_TWO_SIDED_LIGHT 0x1688 +#define NVA197_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVA197_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_POLYGON_STIPPLE 0x168c +#define NVA197_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVA197_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_SHADER_CONTROL 0x1690 +#define NVA197_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVA197_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVA197_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVA197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVA197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVA197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVA197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVA197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVA197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVA197_LAUNCH_VERTEX 0x169c +#define NVA197_LAUNCH_VERTEX_V 0:0 + +#define NVA197_CHECK_CLASS_VERSION 0x16a0 +#define NVA197_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVA197_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA197_SET_SPH_VERSION 0x16a4 +#define NVA197_SET_SPH_VERSION_CURRENT 15:0 +#define NVA197_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA197_CHECK_SPH_VERSION 0x16a8 +#define NVA197_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVA197_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVA197_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVA197_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVA197_SET_AAM_VERSION 0x1790 +#define NVA197_SET_AAM_VERSION_CURRENT 15:0 +#define NVA197_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA197_CHECK_AAM_VERSION 0x1794 +#define NVA197_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVA197_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA197_SET_ZT_LAYER 0x179c +#define NVA197_SET_ZT_LAYER_OFFSET 15:0 + +#define NVA197_SET_VAB_MEMORY_AREA_A 0x17bc +#define NVA197_SET_VAB_MEMORY_AREA_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_VAB_MEMORY_AREA_B 0x17c0 +#define NVA197_SET_VAB_MEMORY_AREA_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_VAB_MEMORY_AREA_C 0x17c4 +#define NVA197_SET_VAB_MEMORY_AREA_C_SIZE 1:0 +#define NVA197_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_64K 0x00000001 +#define NVA197_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_128K 0x00000002 +#define NVA197_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_256K 0x00000003 + +#define NVA197_SET_INDEX_BUFFER_A 0x17c8 +#define NVA197_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVA197_SET_INDEX_BUFFER_B 0x17cc +#define NVA197_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVA197_SET_INDEX_BUFFER_C 0x17d0 +#define NVA197_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVA197_SET_INDEX_BUFFER_D 0x17d4 +#define NVA197_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVA197_SET_INDEX_BUFFER_E 0x17d8 +#define NVA197_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVA197_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVA197_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVA197_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVA197_SET_INDEX_BUFFER_F 0x17dc +#define NVA197_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVA197_DRAW_INDEX_BUFFER 0x17e0 +#define NVA197_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVA197_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVA197_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVA197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVA197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVA197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVA197_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVA197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVA197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVA197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVA197_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVA197_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVA197_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVA197_OGL_SET_CULL 0x1918 +#define NVA197_OGL_SET_CULL_ENABLE 0:0 +#define NVA197_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVA197_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVA197_OGL_SET_FRONT_FACE 0x191c +#define NVA197_OGL_SET_FRONT_FACE_V 31:0 +#define NVA197_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVA197_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVA197_OGL_SET_CULL_FACE 0x1920 +#define NVA197_OGL_SET_CULL_FACE_V 31:0 +#define NVA197_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVA197_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVA197_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVA197_SET_VIEWPORT_PIXEL 0x1924 +#define NVA197_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVA197_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVA197_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVA197_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVA197_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVA197_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVA197_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVA197_INVALIDATE_CONSTANT_BUFFER_CACHE 0x1930 +#define NVA197_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2 0:0 +#define NVA197_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_FALSE 0x00000000 +#define NVA197_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_TRUE 0x00000001 + +#define NVA197_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVA197_SET_USER_CLIP_OP 0x1940 +#define NVA197_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVA197_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVA197_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVA197_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVA197_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVA197_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVA197_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVA197_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVA197_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVA197_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVA197_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVA197_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVA197_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVA197_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVA197_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVA197_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVA197_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVA197_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVA197_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVA197_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVA197_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVA197_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVA197_INVALIDATE_ZCULL 0x1958 +#define NVA197_INVALIDATE_ZCULL_V 31:0 +#define NVA197_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVA197_SET_ZCULL 0x1968 +#define NVA197_SET_ZCULL_Z_ENABLE 0:0 +#define NVA197_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVA197_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_ZCULL_BOUNDS 0x196c +#define NVA197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVA197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVA197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVA197_ZCULL_SYNC 0x1978 +#define NVA197_ZCULL_SYNC_V 31:0 + +#define NVA197_SET_CLIP_ID_TEST 0x197c +#define NVA197_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVA197_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVA197_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVA197_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVA197_SET_CLIP_ID 0x1984 +#define NVA197_SET_CLIP_ID_V 31:0 + +#define NVA197_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVA197_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVA197_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVA197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVA197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVA197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVA197_SET_LOGIC_OP 0x19c4 +#define NVA197_SET_LOGIC_OP_ENABLE 0:0 +#define NVA197_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVA197_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_LOGIC_OP_FUNC 0x19c8 +#define NVA197_SET_LOGIC_OP_FUNC_V 31:0 +#define NVA197_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVA197_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVA197_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVA197_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVA197_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVA197_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVA197_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVA197_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVA197_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVA197_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVA197_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVA197_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVA197_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVA197_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVA197_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVA197_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVA197_SET_Z_COMPRESSION 0x19cc +#define NVA197_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVA197_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVA197_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVA197_CLEAR_SURFACE 0x19d0 +#define NVA197_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVA197_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVA197_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVA197_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVA197_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVA197_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVA197_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVA197_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVA197_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVA197_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVA197_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVA197_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVA197_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVA197_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVA197_SET_CT_WRITE_R_ENABLE 0:0 +#define NVA197_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVA197_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVA197_SET_CT_WRITE_G_ENABLE 4:4 +#define NVA197_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVA197_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVA197_SET_CT_WRITE_B_ENABLE 8:8 +#define NVA197_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVA197_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVA197_SET_CT_WRITE_A_ENABLE 12:12 +#define NVA197_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVA197_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVA197_PIPE_NOP 0x1a2c +#define NVA197_PIPE_NOP_V 31:0 + +#define NVA197_SET_SPARE00 0x1a30 +#define NVA197_SET_SPARE00_V 31:0 + +#define NVA197_SET_SPARE01 0x1a34 +#define NVA197_SET_SPARE01_V 31:0 + +#define NVA197_SET_SPARE02 0x1a38 +#define NVA197_SET_SPARE02_V 31:0 + +#define NVA197_SET_SPARE03 0x1a3c +#define NVA197_SET_SPARE03_V 31:0 + +#define NVA197_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVA197_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVA197_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVA197_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA197_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVA197_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVA197_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVA197_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVA197_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVA197_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVA197_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVA197_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVA197_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVA197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVA197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVA197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVA197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVA197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVA197_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVA197_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVA197_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVA197_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVA197_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVA197_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVA197_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVA197_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVA197_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVA197_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVA197_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVA197_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVA197_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVA197_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVA197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVA197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVA197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVA197_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVA197_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVA197_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVA197_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVA197_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVA197_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVA197_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVA197_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVA197_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVA197_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVA197_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVA197_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVA197_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVA197_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVA197_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVA197_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVA197_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVA197_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVA197_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NVA197_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NVA197_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVA197_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVA197_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVA197_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NVA197_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVA197_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVA197_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NVA197_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVA197_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NVA197_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NVA197_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVA197_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVA197_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVA197_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVA197_SET_FALCON00 0x2300 +#define NVA197_SET_FALCON00_V 31:0 + +#define NVA197_SET_FALCON01 0x2304 +#define NVA197_SET_FALCON01_V 31:0 + +#define NVA197_SET_FALCON02 0x2308 +#define NVA197_SET_FALCON02_V 31:0 + +#define NVA197_SET_FALCON03 0x230c +#define NVA197_SET_FALCON03_V 31:0 + +#define NVA197_SET_FALCON04 0x2310 +#define NVA197_SET_FALCON04_V 31:0 + +#define NVA197_SET_FALCON05 0x2314 +#define NVA197_SET_FALCON05_V 31:0 + +#define NVA197_SET_FALCON06 0x2318 +#define NVA197_SET_FALCON06_V 31:0 + +#define NVA197_SET_FALCON07 0x231c +#define NVA197_SET_FALCON07_V 31:0 + +#define NVA197_SET_FALCON08 0x2320 +#define NVA197_SET_FALCON08_V 31:0 + +#define NVA197_SET_FALCON09 0x2324 +#define NVA197_SET_FALCON09_V 31:0 + +#define NVA197_SET_FALCON10 0x2328 +#define NVA197_SET_FALCON10_V 31:0 + +#define NVA197_SET_FALCON11 0x232c +#define NVA197_SET_FALCON11_V 31:0 + +#define NVA197_SET_FALCON12 0x2330 +#define NVA197_SET_FALCON12_V 31:0 + +#define NVA197_SET_FALCON13 0x2334 +#define NVA197_SET_FALCON13_V 31:0 + +#define NVA197_SET_FALCON14 0x2338 +#define NVA197_SET_FALCON14_V 31:0 + +#define NVA197_SET_FALCON15 0x233c +#define NVA197_SET_FALCON15_V 31:0 + +#define NVA197_SET_FALCON16 0x2340 +#define NVA197_SET_FALCON16_V 31:0 + +#define NVA197_SET_FALCON17 0x2344 +#define NVA197_SET_FALCON17_V 31:0 + +#define NVA197_SET_FALCON18 0x2348 +#define NVA197_SET_FALCON18_V 31:0 + +#define NVA197_SET_FALCON19 0x234c +#define NVA197_SET_FALCON19_V 31:0 + +#define NVA197_SET_FALCON20 0x2350 +#define NVA197_SET_FALCON20_V 31:0 + +#define NVA197_SET_FALCON21 0x2354 +#define NVA197_SET_FALCON21_V 31:0 + +#define NVA197_SET_FALCON22 0x2358 +#define NVA197_SET_FALCON22_V 31:0 + +#define NVA197_SET_FALCON23 0x235c +#define NVA197_SET_FALCON23_V 31:0 + +#define NVA197_SET_FALCON24 0x2360 +#define NVA197_SET_FALCON24_V 31:0 + +#define NVA197_SET_FALCON25 0x2364 +#define NVA197_SET_FALCON25_V 31:0 + +#define NVA197_SET_FALCON26 0x2368 +#define NVA197_SET_FALCON26_V 31:0 + +#define NVA197_SET_FALCON27 0x236c +#define NVA197_SET_FALCON27_V 31:0 + +#define NVA197_SET_FALCON28 0x2370 +#define NVA197_SET_FALCON28_V 31:0 + +#define NVA197_SET_FALCON29 0x2374 +#define NVA197_SET_FALCON29_V 31:0 + +#define NVA197_SET_FALCON30 0x2378 +#define NVA197_SET_FALCON30_V 31:0 + +#define NVA197_SET_FALCON31 0x237c +#define NVA197_SET_FALCON31_V 31:0 + +#define NVA197_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVA197_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVA197_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVA197_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVA197_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVA197_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVA197_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVA197_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVA197_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVA197_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVA197_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVA197_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVA197_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVA197_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVA197_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVA197_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVA197_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVA197_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVA197_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVA197_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVA197_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA197_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA197_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVA197_SET_COLOR_CLAMP 0x2600 +#define NVA197_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVA197_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVA197_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVA197_NOOP_X_X_X_SET_VALVE 0x2604 +#define NVA197_NOOP_X_X_X_SET_VALVE_HIGHER_PRIORITY 0:0 +#define NVA197_NOOP_X_X_X_SET_VALVE_HIGHER_PRIORITY_COMPUTE 0x00000000 +#define NVA197_NOOP_X_X_X_SET_VALVE_HIGHER_PRIORITY_GRAPHICS 0x00000001 + +#define NVA197_SET_BINDLESS_TEXTURE 0x2608 +#define NVA197_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVA197_SET_TRAP_HANDLER 0x260c +#define NVA197_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVA197_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVA197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVA197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVA197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVA197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVA197_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVA197_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVA197_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVA197_CALL_MME_MACRO_V 31:0 + +#define NVA197_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVA197_CALL_MME_DATA_V 31:0 + +#endif /* _cl_kepler_b_h_ */ diff --git a/userspace/sdks/nv570/inc/class/cla1c0.h b/userspace/sdks/nv570/inc/class/cla1c0.h new file mode 100644 index 0000000..2b904c0 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cla1c0.h @@ -0,0 +1,669 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_kepler_compute_b_h_ +#define _cl_kepler_compute_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl kepler_compute_b */ + +#include "nvtypes.h" + +#define KEPLER_COMPUTE_B 0xA1C0 + +#define NVA1C0_SET_OBJECT 0x0000 +#define NVA1C0_SET_OBJECT_CLASS_ID 15:0 +#define NVA1C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVA1C0_NO_OPERATION 0x0100 +#define NVA1C0_NO_OPERATION_V 31:0 + +#define NVA1C0_SET_NOTIFY_A 0x0104 +#define NVA1C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_SET_NOTIFY_B 0x0108 +#define NVA1C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_NOTIFY 0x010c +#define NVA1C0_NOTIFY_TYPE 31:0 +#define NVA1C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVA1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVA1C0_WAIT_FOR_IDLE 0x0110 +#define NVA1C0_WAIT_FOR_IDLE_V 31:0 + +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA1C0_SEND_GO_IDLE 0x013c +#define NVA1C0_SEND_GO_IDLE_V 31:0 + +#define NVA1C0_PM_TRIGGER 0x0140 +#define NVA1C0_PM_TRIGGER_V 31:0 + +#define NVA1C0_PM_TRIGGER_WFI 0x0144 +#define NVA1C0_PM_TRIGGER_WFI_V 31:0 + +#define NVA1C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVA1C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVA1C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVA1C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVA1C0_LINE_LENGTH_IN 0x0180 +#define NVA1C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVA1C0_LINE_COUNT 0x0184 +#define NVA1C0_LINE_COUNT_VALUE 31:0 + +#define NVA1C0_OFFSET_OUT_UPPER 0x0188 +#define NVA1C0_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVA1C0_OFFSET_OUT 0x018c +#define NVA1C0_OFFSET_OUT_VALUE 31:0 + +#define NVA1C0_PITCH_OUT 0x0190 +#define NVA1C0_PITCH_OUT_VALUE 31:0 + +#define NVA1C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVA1C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVA1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVA1C0_SET_DST_WIDTH 0x0198 +#define NVA1C0_SET_DST_WIDTH_V 31:0 + +#define NVA1C0_SET_DST_HEIGHT 0x019c +#define NVA1C0_SET_DST_HEIGHT_V 31:0 + +#define NVA1C0_SET_DST_DEPTH 0x01a0 +#define NVA1C0_SET_DST_DEPTH_V 31:0 + +#define NVA1C0_SET_DST_LAYER 0x01a4 +#define NVA1C0_SET_DST_LAYER_V 31:0 + +#define NVA1C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVA1C0_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVA1C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVA1C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVA1C0_LAUNCH_DMA 0x01b0 +#define NVA1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVA1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVA1C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVA1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVA1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVA1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVA1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVA1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVA1C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVA1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA1C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVA1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVA1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVA1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVA1C0_LOAD_INLINE_DATA 0x01b4 +#define NVA1C0_LOAD_INLINE_DATA_V 31:0 + +#define NVA1C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVA1C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVA1C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVA1C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA1C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVA1C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVA1C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVA1C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVA1C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVA1C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVA1C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVA1C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVA1C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVA1C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVA1C0_PERFMON_TRANSFER 0x0210 +#define NVA1C0_PERFMON_TRANSFER_V 31:0 + +#define NVA1C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVA1C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA1C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVA1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVA1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVA1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVA1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVA1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVA1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVA1C0_SET_CWD_CONTROL 0x0240 +#define NVA1C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVA1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVA1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVA1C0_SET_CWD_REF_COUNTER 0x0248 +#define NVA1C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVA1C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVA1C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVA1C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVA1C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA1C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVA1C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVA1C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA1C0_SET_QMD_VERSION 0x0288 +#define NVA1C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVA1C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA1C0_CHECK_QMD_VERSION 0x0290 +#define NVA1C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVA1C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA1C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVA1C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVA1C0_SEND_PCAS_A 0x02b4 +#define NVA1C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVA1C0_SEND_PCAS_B 0x02b8 +#define NVA1C0_SEND_PCAS_B_FROM 23:0 +#define NVA1C0_SEND_PCAS_B_DELTA 31:24 + +#define NVA1C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVA1C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVA1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVA1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVA1C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVA1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVA1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE 0x02c4 +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE 0:0 +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE_TRUE 0x00000001 +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_HEADER_INDEX 23:4 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVA1C0_SET_SPA_VERSION 0x0310 +#define NVA1C0_SET_SPA_VERSION_MINOR 7:0 +#define NVA1C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVA1C0_SET_FALCON00 0x0500 +#define NVA1C0_SET_FALCON00_V 31:0 + +#define NVA1C0_SET_FALCON01 0x0504 +#define NVA1C0_SET_FALCON01_V 31:0 + +#define NVA1C0_SET_FALCON02 0x0508 +#define NVA1C0_SET_FALCON02_V 31:0 + +#define NVA1C0_SET_FALCON03 0x050c +#define NVA1C0_SET_FALCON03_V 31:0 + +#define NVA1C0_SET_FALCON04 0x0510 +#define NVA1C0_SET_FALCON04_V 31:0 + +#define NVA1C0_SET_FALCON05 0x0514 +#define NVA1C0_SET_FALCON05_V 31:0 + +#define NVA1C0_SET_FALCON06 0x0518 +#define NVA1C0_SET_FALCON06_V 31:0 + +#define NVA1C0_SET_FALCON07 0x051c +#define NVA1C0_SET_FALCON07_V 31:0 + +#define NVA1C0_SET_FALCON08 0x0520 +#define NVA1C0_SET_FALCON08_V 31:0 + +#define NVA1C0_SET_FALCON09 0x0524 +#define NVA1C0_SET_FALCON09_V 31:0 + +#define NVA1C0_SET_FALCON10 0x0528 +#define NVA1C0_SET_FALCON10_V 31:0 + +#define NVA1C0_SET_FALCON11 0x052c +#define NVA1C0_SET_FALCON11_V 31:0 + +#define NVA1C0_SET_FALCON12 0x0530 +#define NVA1C0_SET_FALCON12_V 31:0 + +#define NVA1C0_SET_FALCON13 0x0534 +#define NVA1C0_SET_FALCON13_V 31:0 + +#define NVA1C0_SET_FALCON14 0x0538 +#define NVA1C0_SET_FALCON14_V 31:0 + +#define NVA1C0_SET_FALCON15 0x053c +#define NVA1C0_SET_FALCON15_V 31:0 + +#define NVA1C0_SET_FALCON16 0x0540 +#define NVA1C0_SET_FALCON16_V 31:0 + +#define NVA1C0_SET_FALCON17 0x0544 +#define NVA1C0_SET_FALCON17_V 31:0 + +#define NVA1C0_SET_FALCON18 0x0548 +#define NVA1C0_SET_FALCON18_V 31:0 + +#define NVA1C0_SET_FALCON19 0x054c +#define NVA1C0_SET_FALCON19_V 31:0 + +#define NVA1C0_SET_FALCON20 0x0550 +#define NVA1C0_SET_FALCON20_V 31:0 + +#define NVA1C0_SET_FALCON21 0x0554 +#define NVA1C0_SET_FALCON21_V 31:0 + +#define NVA1C0_SET_FALCON22 0x0558 +#define NVA1C0_SET_FALCON22_V 31:0 + +#define NVA1C0_SET_FALCON23 0x055c +#define NVA1C0_SET_FALCON23_V 31:0 + +#define NVA1C0_SET_FALCON24 0x0560 +#define NVA1C0_SET_FALCON24_V 31:0 + +#define NVA1C0_SET_FALCON25 0x0564 +#define NVA1C0_SET_FALCON25_V 31:0 + +#define NVA1C0_SET_FALCON26 0x0568 +#define NVA1C0_SET_FALCON26_V 31:0 + +#define NVA1C0_SET_FALCON27 0x056c +#define NVA1C0_SET_FALCON27_V 31:0 + +#define NVA1C0_SET_FALCON28 0x0570 +#define NVA1C0_SET_FALCON28_V 31:0 + +#define NVA1C0_SET_FALCON29 0x0574 +#define NVA1C0_SET_FALCON29_V 31:0 + +#define NVA1C0_SET_FALCON30 0x0578 +#define NVA1C0_SET_FALCON30_V 31:0 + +#define NVA1C0_SET_FALCON31 0x057c +#define NVA1C0_SET_FALCON31_V 31:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVA1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVA1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVA1C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVA1C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVA1C0_SET_SPARE_NOOP12 0x0f44 +#define NVA1C0_SET_SPARE_NOOP12_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP13 0x0f48 +#define NVA1C0_SET_SPARE_NOOP13_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP14 0x0f4c +#define NVA1C0_SET_SPARE_NOOP14_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP15 0x0f50 +#define NVA1C0_SET_SPARE_NOOP15_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP00 0x1040 +#define NVA1C0_SET_SPARE_NOOP00_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP01 0x1044 +#define NVA1C0_SET_SPARE_NOOP01_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP02 0x1048 +#define NVA1C0_SET_SPARE_NOOP02_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP03 0x104c +#define NVA1C0_SET_SPARE_NOOP03_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP04 0x1050 +#define NVA1C0_SET_SPARE_NOOP04_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP05 0x1054 +#define NVA1C0_SET_SPARE_NOOP05_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP06 0x1058 +#define NVA1C0_SET_SPARE_NOOP06_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP07 0x105c +#define NVA1C0_SET_SPARE_NOOP07_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP08 0x1060 +#define NVA1C0_SET_SPARE_NOOP08_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP09 0x1064 +#define NVA1C0_SET_SPARE_NOOP09_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP10 0x1068 +#define NVA1C0_SET_SPARE_NOOP10_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP11 0x106c +#define NVA1C0_SET_SPARE_NOOP11_V 31:0 + +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVA1C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVA1C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVA1C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVA1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVA1C0_SET_RENDER_ENABLE_A 0x1550 +#define NVA1C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_RENDER_ENABLE_B 0x1554 +#define NVA1C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_RENDER_ENABLE_C 0x1558 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA1C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVA1C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVA1C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVA1C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVA1C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVA1C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVA1C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVA1C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVA1C0_SET_PROGRAM_REGION_A 0x1608 +#define NVA1C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_SET_PROGRAM_REGION_B 0x160c +#define NVA1C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_SET_SHADER_CONTROL 0x1690 +#define NVA1C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVA1C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVA1C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 + +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVA1C0_PIPE_NOP 0x1a2c +#define NVA1C0_PIPE_NOP_V 31:0 + +#define NVA1C0_SET_SPARE00 0x1a30 +#define NVA1C0_SET_SPARE00_V 31:0 + +#define NVA1C0_SET_SPARE01 0x1a34 +#define NVA1C0_SET_SPARE01_V 31:0 + +#define NVA1C0_SET_SPARE02 0x1a38 +#define NVA1C0_SET_SPARE02_V 31:0 + +#define NVA1C0_SET_SPARE03 0x1a3c +#define NVA1C0_SET_SPARE03_V 31:0 + +#define NVA1C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVA1C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVA1C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVA1C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA1C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVA1C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVA1C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVA1C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVA1C0_SET_TRAP_HANDLER 0x260c +#define NVA1C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVA1C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVA1C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_kepler_compute_b_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clb069.h b/userspace/sdks/nv570/inc/class/clb069.h new file mode 100644 index 0000000..94140dd --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clb069.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clb069_h_ +#define _clb069_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define MAXWELL_FAULT_BUFFER_A (0xb069) + +#define NVB069_FAULT_BUF_ENTRY 0x0000001f:0x00000000 +#define NVB069_FAULT_BUF_SIZE 32 +#define NVB069_FAULT_BUF_ENTRY_INST_APERTURE MW((9+0*32):(0*32+8)) +#define NVB069_FAULT_BUF_ENTRY_INST_APERTURE_VID_MEM 0x00000000 +#define NVB069_FAULT_BUF_ENTRY_INST_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVB069_FAULT_BUF_ENTRY_INST_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVB069_FAULT_BUF_ENTRY_INST_LO MW((31+0*32):(0*32+12)) +#define NVB069_FAULT_BUF_ENTRY_INST_HI MW((31+1*32):(1*32+0)) +#define NVB069_FAULT_BUF_ENTRY_INST MW((31+1*32):(0*32+12)) +#define NVB069_FAULT_BUF_ENTRY_ADDR_LO MW((31+2*32):(2*32+0)) +#define NVB069_FAULT_BUF_ENTRY_ADDR_HI MW((31+3*32):(3*32+0)) +#define NVB069_FAULT_BUF_ENTRY_ADDR MW((31+3*32):(2*32+0)) +#define NVB069_FAULT_BUF_ENTRY_TIMESTAMP_LO MW((31+4*32):(4*32+0)) +#define NVB069_FAULT_BUF_ENTRY_TIMESTAMP_HI MW((31+5*32):(5*32+0)) +#define NVB069_FAULT_BUF_ENTRY_TIMESTAMP MW((31+5*32):(4*32+0)) +#define NVB069_FAULT_BUF_ENTRY_RESERVED MW((31+6*32):(6*32+0)) +#define NVB069_FAULT_BUF_ENTRY_FAULT_TYPE MW((4+7*32):(7*32+0)) +#define NVB069_FAULT_BUF_ENTRY_CLIENT MW((14+7*32):(7*32+8)) +#define NVB069_FAULT_BUF_ENTRY_ACCESS_TYPE MW((18+7*32):(7*32+16)) +#define NVB069_FAULT_BUF_ENTRY_MMU_CLIENT_TYPE MW((20+7*32):(7*32+20)) +#define NVB069_FAULT_BUF_ENTRY_GPC_ID MW((28+7*32):(7*32+24)) +#define NVB069_FAULT_BUF_ENTRY_VALID MW((31+7*32):(7*32+31)) +#define NVB069_FAULT_BUF_ENTRY_VALID_FALSE 0x00000000 +#define NVB069_FAULT_BUF_ENTRY_VALID_TRUE 0x00000001 +#define NVB069_NOTIFIERS_REPLAYABLE_FAULT (0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clb069_h_ */ + diff --git a/userspace/sdks/nv570/inc/class/clb069sw.h b/userspace/sdks/nv570/inc/class/clb069sw.h new file mode 100644 index 0000000..37e8ad4 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clb069sw.h @@ -0,0 +1,38 @@ +/******************************************************************************* + Copyright (c) 2008-2022 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clb069sw.finn +// + +#define NVB069_ALLOCATION_PARAMETERS_MESSAGE_ID (0xb069U) + +typedef struct NVB069_ALLOCATION_PARAMETERS { + NvU32 flags; // set to 0 +} NVB069_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clb06f.h b/userspace/sdks/nv570/inc/class/clb06f.h new file mode 100644 index 0000000..b2b51e0 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clb06f.h @@ -0,0 +1,260 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clb06f_h_ +#define _clb06f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class MAXWELL_CHANNEL_GPFIFO */ +/* + * Documentation for MAXWELL_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + */ +#define MAXWELL_CHANNEL_GPFIFO_A (0x0000B06F) + +#define NVB06F_TYPEDEF MAXWELL_CHANNELChannelGPFifoA + +/* dma flow control data structure */ +typedef volatile struct _clb06f_tag0 { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} Nvb06FControl, MaxwellAControlGPFifo; + +/* fields and values */ +#define NVB06F_NUMBER_OF_SUBCHANNELS (8) +#define NVB06F_SET_OBJECT (0x00000000) +#define NVB06F_SET_OBJECT_NVCLASS 15:0 +#define NVB06F_SET_OBJECT_ENGINE 20:16 +#define NVB06F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVB06F_ILLEGAL (0x00000004) +#define NVB06F_ILLEGAL_HANDLE 31:0 +#define NVB06F_NOP (0x00000008) +#define NVB06F_NOP_HANDLE 31:0 +#define NVB06F_SEMAPHOREA (0x00000010) +#define NVB06F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVB06F_SEMAPHOREB (0x00000014) +#define NVB06F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVB06F_SEMAPHOREC (0x00000018) +#define NVB06F_SEMAPHOREC_PAYLOAD 31:0 +#define NVB06F_SEMAPHORED (0x0000001C) +#define NVB06F_SEMAPHORED_OPERATION 4:0 +#define NVB06F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVB06F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVB06F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVB06F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVB06F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 +#define NVB06F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVB06F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVB06F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVB06F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVB06F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVB06F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVB06F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVB06F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVB06F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVB06F_SEMAPHORED_REDUCTION 30:27 +#define NVB06F_SEMAPHORED_REDUCTION_MIN 0x00000000 +#define NVB06F_SEMAPHORED_REDUCTION_MAX 0x00000001 +#define NVB06F_SEMAPHORED_REDUCTION_XOR 0x00000002 +#define NVB06F_SEMAPHORED_REDUCTION_AND 0x00000003 +#define NVB06F_SEMAPHORED_REDUCTION_OR 0x00000004 +#define NVB06F_SEMAPHORED_REDUCTION_ADD 0x00000005 +#define NVB06F_SEMAPHORED_REDUCTION_INC 0x00000006 +#define NVB06F_SEMAPHORED_REDUCTION_DEC 0x00000007 +#define NVB06F_SEMAPHORED_FORMAT 31:31 +#define NVB06F_SEMAPHORED_FORMAT_SIGNED 0x00000000 +#define NVB06F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 +#define NVB06F_NON_STALL_INTERRUPT (0x00000020) +#define NVB06F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVB06F_FB_FLUSH (0x00000024) +#define NVB06F_FB_FLUSH_HANDLE 31:0 +// NOTE - MEM_OP_A and MEM_OP_B have been removed for gm20x to make room for +// possible future MEM_OP features. MEM_OP_C/D have identical functionality +// to the previous MEM_OP_A/B methods. +#define NVB06F_MEM_OP_C (0x00000030) +#define NVB06F_MEM_OP_C_OPERAND_LOW 31:2 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_TARGET 11:10 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_ADDR_LO 31:12 +#define NVB06F_MEM_OP_D (0x00000034) +#define NVB06F_MEM_OP_D_OPERAND_HIGH 7:0 +#define NVB06F_MEM_OP_D_OPERATION 31:27 +#define NVB06F_MEM_OP_D_OPERATION_MEMBAR 0x00000005 +#define NVB06F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVB06F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NVB06F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +#define NVB06F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVB06F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVB06F_MEM_OP_D_TLB_INVALIDATE_ADDR_HI 7:0 +#define NVB06F_SET_REFERENCE (0x00000050) +#define NVB06F_SET_REFERENCE_COUNT 31:0 +#define NVB06F_WFI (0x00000078) +#define NVB06F_WFI_SCOPE 0:0 +#define NVB06F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000 +#define NVB06F_WFI_SCOPE_ALL 0x00000001 +#define NVB06F_CRC_CHECK (0x0000007c) +#define NVB06F_CRC_CHECK_VALUE 31:0 +#define NVB06F_YIELD (0x00000080) +#define NVB06F_YIELD_OP 1:0 +#define NVB06F_YIELD_OP_NOP 0x00000000 +#define NVB06F_YIELD_OP_PBDMA_TIMESLICE 0x00000001 +#define NVB06F_YIELD_OP_RUNLIST_TIMESLICE 0x00000002 +#define NVB06F_YIELD_OP_TSG 0x00000003 + + +/* GPFIFO entry format */ +#define NVB06F_GP_ENTRY__SIZE 8 +#define NVB06F_GP_ENTRY0_FETCH 0:0 +#define NVB06F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVB06F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVB06F_GP_ENTRY0_GET 31:2 +#define NVB06F_GP_ENTRY0_OPERAND 31:0 +#define NVB06F_GP_ENTRY1_GET_HI 7:0 +#define NVB06F_GP_ENTRY1_PRIV 8:8 +#define NVB06F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NVB06F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NVB06F_GP_ENTRY1_LEVEL 9:9 +#define NVB06F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVB06F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVB06F_GP_ENTRY1_LENGTH 30:10 +#define NVB06F_GP_ENTRY1_SYNC 31:31 +#define NVB06F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVB06F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVB06F_GP_ENTRY1_OPCODE 7:0 +#define NVB06F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVB06F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVB06F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVB06F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVB06F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVB06F_DMA_METHOD_ADDRESS 11:0 +#define NVB06F_DMA_SUBDEVICE_MASK 15:4 +#define NVB06F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVB06F_DMA_TERT_OP 17:16 +#define NVB06F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVB06F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVB06F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVB06F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVB06F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVB06F_DMA_METHOD_COUNT_OLD 28:18 +#define NVB06F_DMA_METHOD_COUNT 28:16 +#define NVB06F_DMA_IMMD_DATA 28:16 +#define NVB06F_DMA_SEC_OP 31:29 +#define NVB06F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVB06F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVB06F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVB06F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVB06F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVB06F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVB06F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVB06F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVB06F_DMA_INCR_ADDRESS 11:0 +#define NVB06F_DMA_INCR_SUBCHANNEL 15:13 +#define NVB06F_DMA_INCR_COUNT 28:16 +#define NVB06F_DMA_INCR_OPCODE 31:29 +#define NVB06F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVB06F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVB06F_DMA_NONINCR_ADDRESS 11:0 +#define NVB06F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVB06F_DMA_NONINCR_COUNT 28:16 +#define NVB06F_DMA_NONINCR_OPCODE 31:29 +#define NVB06F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVB06F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVB06F_DMA_ONEINCR_ADDRESS 11:0 +#define NVB06F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVB06F_DMA_ONEINCR_COUNT 28:16 +#define NVB06F_DMA_ONEINCR_OPCODE 31:29 +#define NVB06F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVB06F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVB06F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVB06F_DMA_IMMD_ADDRESS 11:0 +#define NVB06F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVB06F_DMA_IMMD_DATA 28:16 +#define NVB06F_DMA_IMMD_OPCODE 31:29 +#define NVB06F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVB06F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVB06F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVB06F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVB06F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVB06F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVB06F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVB06F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVB06F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVB06F_DMA_ENDSEG_OPCODE 31:29 +#define NVB06F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVB06F_DMA_ADDRESS 12:2 +#define NVB06F_DMA_SUBCH 15:13 +#define NVB06F_DMA_OPCODE3 17:16 +#define NVB06F_DMA_OPCODE3_NONE (0x00000000) +#define NVB06F_DMA_COUNT 28:18 +#define NVB06F_DMA_OPCODE 31:29 +#define NVB06F_DMA_OPCODE_METHOD (0x00000000) +#define NVB06F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVB06F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clb06f_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clb06fsw.h b/userspace/sdks/nv570/inc/class/clb06fsw.h new file mode 100644 index 0000000..3e1c74b --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clb06fsw.h @@ -0,0 +1,42 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clb06f_sw_h_ +#define _clb06f_sw_h_ + +#define NVB06F_NOTIFIERS_RC (0) +#define NVB06F_NOTIFIERS_REFCNT (1) +#define NVB06F_NOTIFIERS_NONSTALL (2) +#define NVB06F_NOTIFIERS_EVENTBUFFER (3) +#define NVB06F_NOTIFIERS_IDLECHANNEL (4) +#define NVB06F_NOTIFIERS_ENDCTX (5) +#define NVB06F_NOTIFIERS_SW (6) +#define NVB06F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVB06F_NOTIFIERS_REPLAYABLE_FAULT (8) +#define NVB06F_NOTIFIERS_MAXCOUNT (9) + +/* NvNotification[] fields and values */ +#define NVB06F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVB06F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _clb06f_sw_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clb097.h b/userspace/sdks/nv570/inc/class/clb097.h new file mode 100644 index 0000000..52ee310 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clb097.h @@ -0,0 +1,3966 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_maxwell_a_h_ +#define _cl_maxwell_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl maxwell_a */ + +#include "nvtypes.h" + +#define MAXWELL_A 0xB097 + +#define NVB097_SET_OBJECT 0x0000 +#define NVB097_SET_OBJECT_CLASS_ID 15:0 +#define NVB097_SET_OBJECT_ENGINE_ID 20:16 + +#define NVB097_NO_OPERATION 0x0100 +#define NVB097_NO_OPERATION_V 31:0 + +#define NVB097_SET_NOTIFY_A 0x0104 +#define NVB097_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVB097_SET_NOTIFY_B 0x0108 +#define NVB097_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVB097_NOTIFY 0x010c +#define NVB097_NOTIFY_TYPE 31:0 +#define NVB097_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVB097_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVB097_WAIT_FOR_IDLE 0x0110 +#define NVB097_WAIT_FOR_IDLE_V 31:0 + +#define NVB097_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVB097_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVB097_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVB097_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVB097_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVB097_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVB097_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVB097_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVB097_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVB097_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVB097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVB097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVB097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVB097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVB097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVB097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVB097_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVB097_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVB097_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB097_SEND_GO_IDLE 0x013c +#define NVB097_SEND_GO_IDLE_V 31:0 + +#define NVB097_PM_TRIGGER 0x0140 +#define NVB097_PM_TRIGGER_V 31:0 + +#define NVB097_PM_TRIGGER_WFI 0x0144 +#define NVB097_PM_TRIGGER_WFI_V 31:0 + +#define NVB097_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVB097_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVB097_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVB097_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVB097_LINE_LENGTH_IN 0x0180 +#define NVB097_LINE_LENGTH_IN_VALUE 31:0 + +#define NVB097_LINE_COUNT 0x0184 +#define NVB097_LINE_COUNT_VALUE 31:0 + +#define NVB097_OFFSET_OUT_UPPER 0x0188 +#define NVB097_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVB097_OFFSET_OUT 0x018c +#define NVB097_OFFSET_OUT_VALUE 31:0 + +#define NVB097_PITCH_OUT 0x0190 +#define NVB097_PITCH_OUT_VALUE 31:0 + +#define NVB097_SET_DST_BLOCK_SIZE 0x0194 +#define NVB097_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVB097_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVB097_SET_DST_WIDTH 0x0198 +#define NVB097_SET_DST_WIDTH_V 31:0 + +#define NVB097_SET_DST_HEIGHT 0x019c +#define NVB097_SET_DST_HEIGHT_V 31:0 + +#define NVB097_SET_DST_DEPTH 0x01a0 +#define NVB097_SET_DST_DEPTH_V 31:0 + +#define NVB097_SET_DST_LAYER 0x01a4 +#define NVB097_SET_DST_LAYER_V 31:0 + +#define NVB097_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVB097_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVB097_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVB097_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVB097_LAUNCH_DMA 0x01b0 +#define NVB097_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVB097_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB097_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB097_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVB097_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVB097_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVB097_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVB097_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVB097_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVB097_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVB097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVB097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVB097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVB097_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVB097_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB097_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB097_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB097_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVB097_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB097_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB097_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVB097_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVB097_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVB097_LOAD_INLINE_DATA 0x01b4 +#define NVB097_LOAD_INLINE_DATA_V 31:0 + +#define NVB097_SET_I2M_SEMAPHORE_A 0x01dc +#define NVB097_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVB097_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVB097_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB097_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVB097_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVB097_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVB097_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVB097_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVB097_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVB097_SET_I2M_SPARE_NOOP03 0x01fc +#define NVB097_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVB097_RUN_DS_NOW 0x0200 +#define NVB097_RUN_DS_NOW_V 31:0 + +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVB097_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVB097_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVB097_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVB097_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVB097_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVB097_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_GS_DM_FIFO 0x0214 +#define NVB097_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVB097_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVB097_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVB097_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVB097_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB097_INVALIDATE_SHADER_CACHES 0x021c +#define NVB097_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVB097_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVB097_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVB097_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVB097_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVB097_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVB097_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVB097_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVB097_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVB097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVB097_INCREMENT_SYNC_POINT 0x02c8 +#define NVB097_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVB097_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVB097_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVB097_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVB097_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVB097_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVB097_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVB097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NVB097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NVB097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVB097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVB097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVB097_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVB097_DECOMPRESS_SURFACE 0x02e0 +#define NVB097_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVB097_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVB097_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVB097_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVB097_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVB097_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVB097_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVB097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVB097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVB097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVB097_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVB097_SET_ZCULL_SUBREGION 0x02e8 +#define NVB097_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVB097_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVB097_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVB097_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVB097_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVB097_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVB097_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVB097_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVB097_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVB097_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVB097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVB097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVB097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVB097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVB097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVB097_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVB097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVB097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVB097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVB097_DRAW_ZERO_INDEX 0x0304 +#define NVB097_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVB097_SET_L1_CONFIGURATION 0x0308 +#define NVB097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVB097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVB097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVB097_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVB097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVB097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVB097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVB097_SET_SPA_VERSION 0x0310 +#define NVB097_SET_SPA_VERSION_MINOR 7:0 +#define NVB097_SET_SPA_VERSION_MAJOR 15:8 + +#define NVB097_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NVB097_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NVB097_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_SNAP_GRID_LINE 0x0318 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVB097_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVB097_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVB097_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVB097_SET_SNAP_GRID_NON_LINE 0x031c +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVB097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVB097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVB097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVB097_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVB097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVB097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVB097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVB097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVB097_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVB097_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVB097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVB097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVB097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVB097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVB097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVB097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVB097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVB097_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVB097_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVB097_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVB097_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVB097_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVB097_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVB097_SET_TESSELLATION_LOD_V1 0x0330 +#define NVB097_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVB097_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVB097_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVB097_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVB097_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVB097_RESERVED_TG07 0x033c +#define NVB097_RESERVED_TG07_V 0:0 + +#define NVB097_RESERVED_TG08 0x0340 +#define NVB097_RESERVED_TG08_V 0:0 + +#define NVB097_RESERVED_TG09 0x0344 +#define NVB097_RESERVED_TG09_V 0:0 + +#define NVB097_RESERVED_TG10 0x0348 +#define NVB097_RESERVED_TG10_V 0:0 + +#define NVB097_RESERVED_TG11 0x034c +#define NVB097_RESERVED_TG11_V 0:0 + +#define NVB097_RESERVED_TG12 0x0350 +#define NVB097_RESERVED_TG12_V 0:0 + +#define NVB097_RESERVED_TG13 0x0354 +#define NVB097_RESERVED_TG13_V 0:0 + +#define NVB097_RESERVED_TG14 0x0358 +#define NVB097_RESERVED_TG14_V 0:0 + +#define NVB097_RESERVED_TG15 0x035c +#define NVB097_RESERVED_TG15_V 0:0 + +#define NVB097_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVB097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVB097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVB097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVB097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVB097_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVB097_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVB097_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVB097_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVB097_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVB097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVB097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVB097_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVB097_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVB097_SET_RASTER_ENABLE 0x037c +#define NVB097_SET_RASTER_ENABLE_V 0:0 +#define NVB097_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVB097_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVB097_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVB097_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVB097_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVB097_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVB097_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVB097_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVB097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVB097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVB097_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVB097_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVB097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVB097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVB097_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVB097_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVB097_SET_RASTER_INPUT 0x0740 +#define NVB097_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVB097_SET_STREAM_OUTPUT 0x0744 +#define NVB097_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVB097_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVB097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVB097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_ALPHA_FRACTION 0x074c +#define NVB097_SET_ALPHA_FRACTION_V 7:0 + +#define NVB097_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVB097_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVB097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVB097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVB097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 + +#define NVB097_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVB097_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB097_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVB097_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVB097_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVB097_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVB097_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVB097_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVB097_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVB097_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVB097_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVB097_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVB097_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVB097_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVB097_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVB097_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVB097_SET_ISBE_SAVE_RESTORE_PROGRAM 0x07ac +#define NVB097_SET_ISBE_SAVE_RESTORE_PROGRAM_OFFSET 31:0 + +#define NVB097_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVB097_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVB097_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVB097_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVB097_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVB097_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVB097_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVB097_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVB097_SET_CULL_BEFORE_FETCH 0x07dc +#define NVB097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVB097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVB097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVB097_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVB097_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVB097_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVB097_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVB097_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVB097_SET_ZCULL_STORAGE_A 0x07e8 +#define NVB097_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVB097_SET_ZCULL_STORAGE_B 0x07ec +#define NVB097_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVB097_SET_ZCULL_STORAGE_C 0x07f0 +#define NVB097_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVB097_SET_ZCULL_STORAGE_D 0x07f4 +#define NVB097_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVB097_SET_ZT_READ_ONLY 0x07f8 +#define NVB097_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVB097_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVB097_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVB097_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVB097_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVB097_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVB097_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVB097_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVB097_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVB097_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVB097_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVB097_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVB097_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVB097_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVB097_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVB097_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVB097_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVB097_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVB097_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVB097_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVB097_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVB097_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVB097_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVB097_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVB097_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB097_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVB097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVB097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVB097_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVB097_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVB097_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVB097_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVB097_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVB097_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVB097_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NVB097_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NVB097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVB097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVB097_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVB097_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVB097_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVB097_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVB097_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVB097_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVB097_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVB097_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVB097_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVB097_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVB097_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVB097_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVB097_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVB097_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVB097_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVB097_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVB097_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVB097_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVB097_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVB097_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVB097_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVB097_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVB097_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVB097_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVB097_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVB097_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVB097_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVB097_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVB097_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVB097_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVB097_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVB097_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVB097_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVB097_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVB097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVB097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVB097_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVB097_SET_STATISTICS_COUNTER 0x0d68 +#define NVB097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVB097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVB097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVB097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVB097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVB097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVB097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVB097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVB097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVB097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVB097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVB097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVB097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVB097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVB097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVB097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVB097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVB097_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVB097_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVB097_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVB097_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVB097_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVB097_SET_VERTEX_ARRAY_START 0x0d74 +#define NVB097_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVB097_DRAW_VERTEX_ARRAY 0x0d78 +#define NVB097_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVB097_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVB097_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVB097_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVB097_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVB097_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVB097_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVB097_SET_Z_CLEAR_VALUE 0x0d90 +#define NVB097_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVB097_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVB097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVB097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVB097_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVB097_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVB097_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVB097_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVB097_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVB097_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVB097_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVB097_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVB097_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVB097_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVB097_SET_FRONT_POLYGON_MODE 0x0dac +#define NVB097_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVB097_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVB097_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVB097_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVB097_SET_BACK_POLYGON_MODE 0x0db0 +#define NVB097_SET_BACK_POLYGON_MODE_V 31:0 +#define NVB097_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVB097_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVB097_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVB097_SET_POLY_SMOOTH 0x0db4 +#define NVB097_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVB097_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVB097_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_ZT_MARK 0x0db8 +#define NVB097_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NVB097_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVB097_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVB097_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVB097_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVB097_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVB097_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVB097_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVB097_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVB097_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVB097_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVB097_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVB097_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_PATCH 0x0dcc +#define NVB097_SET_PATCH_SIZE 7:0 + +#define NVB097_SET_ITERATED_BLEND 0x0dd0 +#define NVB097_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVB097_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVB097_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVB097_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVB097_SET_ZCULL_CRITERION 0x0dd8 +#define NVB097_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVB097_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVB097_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVB097_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVB097_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVB097_SET_ZCULL_CRITERION_SREF 23:16 +#define NVB097_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVB097_PIXEL_SHADER_BARRIER 0x0de0 +#define NVB097_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVB097_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVB097_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVB097_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVB097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVB097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVB097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVB097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVB097_SET_WINDOW_OFFSET_X 0x0df8 +#define NVB097_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVB097_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVB097_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVB097_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVB097_SET_SCISSOR_ENABLE_V 0:0 +#define NVB097_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVB097_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVB097_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVB097_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVB097_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVB097_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVB097_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0f10 +#define NVB097_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVB097_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVB097_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVB097_SET_VPC_PERF_KNOB 0x0f14 +#define NVB097_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVB097_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVB097_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVB097_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVB097_PM_LOCAL_TRIGGER 0x0f18 +#define NVB097_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVB097_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVB097_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVB097_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVB097_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVB097_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVB097_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVB097_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVB097_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVB097_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVB097_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVB097_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVB097_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVB097_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVB097_SET_BACK_STENCIL_MASK 0x0f58 +#define NVB097_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVB097_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVB097_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVB097_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVB097_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVB097_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVB097_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVB097_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVB097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVB097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVB097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVB097_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVB097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVB097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVB097_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVB097_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVB097_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVB097_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVB097_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVB097_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVB097_SET_CT_MRT_ENABLE 0x0fac +#define NVB097_SET_CT_MRT_ENABLE_V 0:0 +#define NVB097_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVB097_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVB097_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVB097_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVB097_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVB097_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVB097_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVB097_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVB097_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVB097_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVB097_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVB097_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVB097_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVB097_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVB097_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVB097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVB097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVB097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVB097_SET_ZT_A 0x0fe0 +#define NVB097_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_ZT_B 0x0fe4 +#define NVB097_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_ZT_FORMAT 0x0fe8 +#define NVB097_SET_ZT_FORMAT_V 4:0 +#define NVB097_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVB097_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVB097_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVB097_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVB097_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVB097_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVB097_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVB097_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVB097_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVB097_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVB097_SET_ZT_BLOCK_SIZE 0x0fec +#define NVB097_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVB097_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVB097_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVB097_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVB097_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVB097_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVB097_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVB097_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVB097_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVB097_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVB097_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVB097_SET_TILED_CACHE_BUNDLE_CONTROL 0x0ffc +#define NVB097_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT 0:0 +#define NVB097_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_FALSE 0x00000000 +#define NVB097_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_TRUE 0x00000001 + +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB097_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVB097_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVB097_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVB097_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVB097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVB097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVB097_SET_RESERVED_SW_METHOD00 0x1014 +#define NVB097_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVB097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVB097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVB097_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVB097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVB097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVB097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVB097_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVB097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVB097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_RESERVED_SW_METHOD01 0x1028 +#define NVB097_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD02 0x102c +#define NVB097_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVB097_SET_SPARE_NOOP01 0x1044 +#define NVB097_SET_SPARE_NOOP01_V 31:0 + +#define NVB097_SET_SPARE_NOOP02 0x1048 +#define NVB097_SET_SPARE_NOOP02_V 31:0 + +#define NVB097_SET_SPARE_NOOP03 0x104c +#define NVB097_SET_SPARE_NOOP03_V 31:0 + +#define NVB097_SET_SPARE_NOOP04 0x1050 +#define NVB097_SET_SPARE_NOOP04_V 31:0 + +#define NVB097_SET_SPARE_NOOP05 0x1054 +#define NVB097_SET_SPARE_NOOP05_V 31:0 + +#define NVB097_SET_SPARE_NOOP06 0x1058 +#define NVB097_SET_SPARE_NOOP06_V 31:0 + +#define NVB097_SET_SPARE_NOOP07 0x105c +#define NVB097_SET_SPARE_NOOP07_V 31:0 + +#define NVB097_SET_SPARE_NOOP08 0x1060 +#define NVB097_SET_SPARE_NOOP08_V 31:0 + +#define NVB097_SET_SPARE_NOOP09 0x1064 +#define NVB097_SET_SPARE_NOOP09_V 31:0 + +#define NVB097_SET_SPARE_NOOP10 0x1068 +#define NVB097_SET_SPARE_NOOP10_V 31:0 + +#define NVB097_SET_SPARE_NOOP11 0x106c +#define NVB097_SET_SPARE_NOOP11_V 31:0 + +#define NVB097_SET_SPARE_NOOP12 0x1070 +#define NVB097_SET_SPARE_NOOP12_V 31:0 + +#define NVB097_SET_SPARE_NOOP13 0x1074 +#define NVB097_SET_SPARE_NOOP13_V 31:0 + +#define NVB097_SET_SPARE_NOOP14 0x1078 +#define NVB097_SET_SPARE_NOOP14_V 31:0 + +#define NVB097_SET_SPARE_NOOP15 0x107c +#define NVB097_SET_SPARE_NOOP15_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVB097_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVB097_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVB097_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD06 0x10bc +#define NVB097_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVB097_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVB097_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVB097_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVB097_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVB097_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVB097_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVB097_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD13 0x10dc +#define NVB097_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVB097_UNBIND_ALL 0x10f4 +#define NVB097_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVB097_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVB097_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVB097_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB097_SET_RESERVED_SW_METHOD14 0x1100 +#define NVB097_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD15 0x1104 +#define NVB097_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVB097_NO_OPERATION_DATA_HI 0x110c +#define NVB097_NO_OPERATION_DATA_HI_V 31:0 + +#define NVB097_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVB097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVB097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVB097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVB097_PM_TRIGGER_END 0x1114 +#define NVB097_PM_TRIGGER_END_V 31:0 + +#define NVB097_SET_VERTEX_ID_BASE 0x1118 +#define NVB097_SET_VERTEX_ID_BASE_V 31:0 + +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVB097_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVB097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVB097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVB097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVB097_FLUSH_PENDING_WRITES 0x1144 +#define NVB097_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVB097_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVB097_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVB097_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVB097_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_SET_CT_SELECT 0x121c +#define NVB097_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVB097_SET_CT_SELECT_TARGET0 6:4 +#define NVB097_SET_CT_SELECT_TARGET1 9:7 +#define NVB097_SET_CT_SELECT_TARGET2 12:10 +#define NVB097_SET_CT_SELECT_TARGET3 15:13 +#define NVB097_SET_CT_SELECT_TARGET4 18:16 +#define NVB097_SET_CT_SELECT_TARGET5 21:19 +#define NVB097_SET_CT_SELECT_TARGET6 24:22 +#define NVB097_SET_CT_SELECT_TARGET7 27:25 + +#define NVB097_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVB097_SET_ZT_SIZE_A 0x1228 +#define NVB097_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVB097_SET_ZT_SIZE_B 0x122c +#define NVB097_SET_ZT_SIZE_B_HEIGHT 16:0 + +#define NVB097_SET_ZT_SIZE_C 0x1230 +#define NVB097_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVB097_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVB097_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVB097_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVB097_SET_SAMPLER_BINDING 0x1234 +#define NVB097_SET_SAMPLER_BINDING_V 0:0 +#define NVB097_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVB097_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVB097_DRAW_AUTO 0x123c +#define NVB097_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVB097_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVB097_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVB097_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVB097_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVB097_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVB097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVB097_CLEAR_ZCULL_REGION 0x12c8 +#define NVB097_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVB097_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVB097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVB097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVB097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVB097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVB097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVB097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVB097_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVB097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVB097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVB097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVB097_SET_DEPTH_TEST 0x12cc +#define NVB097_SET_DEPTH_TEST_ENABLE 0:0 +#define NVB097_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVB097_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_FILL_MODE 0x12d0 +#define NVB097_SET_FILL_MODE_V 31:0 +#define NVB097_SET_FILL_MODE_V_POINT 0x00000001 +#define NVB097_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVB097_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVB097_SET_SHADE_MODE 0x12d4 +#define NVB097_SET_SHADE_MODE_V 31:0 +#define NVB097_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVB097_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVB097_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVB097_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVB097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVB097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVB097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVB097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVB097_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVB097_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVB097_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVB097_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_DEPTH_WRITE 0x12e8 +#define NVB097_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVB097_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_ALPHA_TEST 0x12ec +#define NVB097_SET_ALPHA_TEST_ENABLE 0:0 +#define NVB097_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVB097_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVB097_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVB097_DRAW_INLINE_INDEX4X8 0x1304 +#define NVB097_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVB097_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVB097_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVB097_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVB097_D3D_SET_CULL_MODE 0x1308 +#define NVB097_D3D_SET_CULL_MODE_V 31:0 +#define NVB097_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVB097_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVB097_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVB097_SET_DEPTH_FUNC 0x130c +#define NVB097_SET_DEPTH_FUNC_V 31:0 +#define NVB097_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVB097_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVB097_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB097_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB097_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVB097_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB097_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB097_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB097_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVB097_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVB097_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB097_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB097_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVB097_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB097_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB097_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB097_SET_ALPHA_REF 0x1310 +#define NVB097_SET_ALPHA_REF_V 31:0 + +#define NVB097_SET_ALPHA_FUNC 0x1314 +#define NVB097_SET_ALPHA_FUNC_V 31:0 +#define NVB097_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVB097_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVB097_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB097_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB097_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVB097_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB097_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB097_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB097_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVB097_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVB097_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB097_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB097_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVB097_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB097_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB097_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB097_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVB097_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVB097_SET_BLEND_CONST_RED 0x131c +#define NVB097_SET_BLEND_CONST_RED_V 31:0 + +#define NVB097_SET_BLEND_CONST_GREEN 0x1320 +#define NVB097_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVB097_SET_BLEND_CONST_BLUE 0x1324 +#define NVB097_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVB097_SET_BLEND_CONST_ALPHA 0x1328 +#define NVB097_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVB097_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVB097_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVB097_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVB097_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVB097_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVB097_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVB097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVB097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVB097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BLEND_COLOR_OP 0x1340 +#define NVB097_SET_BLEND_COLOR_OP_V 31:0 +#define NVB097_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB097_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB097_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB097_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVB097_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVB097_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVB097_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB097_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB097_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVB097_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_BLEND_ALPHA_OP 0x134c +#define NVB097_SET_BLEND_ALPHA_OP_V 31:0 +#define NVB097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB097_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVB097_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVB097_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVB097_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB097_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB097_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVB097_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVB097_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVB097_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVB097_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_SINGLE_ROP_CONTROL 0x135c +#define NVB097_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVB097_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BLEND(i) (0x1360+(i)*4) +#define NVB097_SET_BLEND_ENABLE 0:0 +#define NVB097_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVB097_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_STENCIL_TEST 0x1380 +#define NVB097_SET_STENCIL_TEST_ENABLE 0:0 +#define NVB097_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_STENCIL_OP_FAIL 0x1384 +#define NVB097_SET_STENCIL_OP_FAIL_V 31:0 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVB097_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVB097_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVB097_SET_STENCIL_OP_ZPASS 0x138c +#define NVB097_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVB097_SET_STENCIL_FUNC 0x1390 +#define NVB097_SET_STENCIL_FUNC_V 31:0 +#define NVB097_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVB097_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVB097_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB097_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB097_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVB097_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB097_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB097_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB097_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVB097_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVB097_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB097_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB097_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVB097_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB097_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB097_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB097_SET_STENCIL_FUNC_REF 0x1394 +#define NVB097_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVB097_SET_STENCIL_FUNC_MASK 0x1398 +#define NVB097_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVB097_SET_STENCIL_MASK 0x139c +#define NVB097_SET_STENCIL_MASK_V 7:0 + +#define NVB097_SET_DRAW_AUTO_START 0x13a4 +#define NVB097_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVB097_SET_PS_SATURATE 0x13a8 +#define NVB097_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVB097_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVB097_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVB097_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVB097_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVB097_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVB097_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVB097_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVB097_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVB097_SET_WINDOW_ORIGIN 0x13ac +#define NVB097_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVB097_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVB097_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVB097_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVB097_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVB097_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVB097_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVB097_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVB097_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVB097_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVB097_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVB097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVB097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_ALPHA_HYSTERESIS 0x1420 +#define NVB097_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NVB097_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVB097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVB097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB097_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVB097_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVB097_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVB097_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVB097_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVB097_SET_PS_WARP_WATERMARKS 0x1450 +#define NVB097_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVB097_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVB097_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVB097_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVB097_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVB097_STORE_ZCULL 0x1464 +#define NVB097_STORE_ZCULL_V 0:0 + +#define NVB097_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVB097_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVB097_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVB097_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVB097_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVB097_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVB097_LOAD_ZCULL 0x1500 +#define NVB097_LOAD_ZCULL_V 0:0 + +#define NVB097_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVB097_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVB097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVB097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVB097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVB097_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVB097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVB097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVB097_SET_USER_CLIP_ENABLE 0x1510 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVB097_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVB097_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVB097_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_POINT_SIZE 0x1518 +#define NVB097_SET_POINT_SIZE_V 31:0 + +#define NVB097_SET_ZCULL_STATS 0x151c +#define NVB097_SET_ZCULL_STATS_ENABLE 0:0 +#define NVB097_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_POINT_SPRITE 0x1520 +#define NVB097_SET_POINT_SPRITE_ENABLE 0:0 +#define NVB097_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_SHADER_EXCEPTIONS 0x1528 +#define NVB097_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVB097_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVB097_CLEAR_REPORT_VALUE 0x1530 +#define NVB097_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVB097_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVB097_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVB097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVB097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVB097_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVB097_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 + +#define NVB097_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVB097_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVB097_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_ZT_SELECT 0x1538 +#define NVB097_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVB097_SET_RENDER_ENABLE_A 0x1550 +#define NVB097_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_RENDER_ENABLE_B 0x1554 +#define NVB097_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_RENDER_ENABLE_C 0x1558 +#define NVB097_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVB097_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB097_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB097_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB097_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVB097_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVB097_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVB097_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVB097_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVB097_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVB097_SET_ANTI_ALIASED_LINE 0x1570 +#define NVB097_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVB097_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_TEX_HEADER_POOL_A 0x1574 +#define NVB097_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_TEX_HEADER_POOL_B 0x1578 +#define NVB097_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_TEX_HEADER_POOL_C 0x157c +#define NVB097_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVB097_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVB097_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVB097_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVB097_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVB097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVB097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVB097_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVB097_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVB097_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB097_SET_SRGB_WRITE 0x15b8 +#define NVB097_SET_SRGB_WRITE_ENABLE 0:0 +#define NVB097_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_DEPTH_BIAS 0x15bc +#define NVB097_SET_DEPTH_BIAS_V 31:0 + +#define NVB097_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVB097_SET_RT_LAYER 0x15cc +#define NVB097_SET_RT_LAYER_V 15:0 +#define NVB097_SET_RT_LAYER_CONTROL 16:16 +#define NVB097_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVB097_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVB097_SET_ANTI_ALIAS 0x15d0 +#define NVB097_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVB097_SET_EDGE_FLAG 0x15e4 +#define NVB097_SET_EDGE_FLAG_V 0:0 +#define NVB097_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVB097_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVB097_DRAW_INLINE_INDEX 0x15e8 +#define NVB097_DRAW_INLINE_INDEX_V 31:0 + +#define NVB097_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVB097_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVB097_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVB097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVB097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVB097_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVB097_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVB097_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVB097_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVB097_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVB097_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVB097_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVB097_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVB097_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVB097_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVB097_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVB097_SET_POINT_SPRITE_SELECT 0x1604 +#define NVB097_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVB097_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVB097_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVB097_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVB097_SET_PROGRAM_REGION_A 0x1608 +#define NVB097_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVB097_SET_PROGRAM_REGION_B 0x160c +#define NVB097_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVB097_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVB097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVB097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVB097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVB097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVB097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVB097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVB097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVB097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVB097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVB097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVB097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVB097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVB097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVB097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVB097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVB097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVB097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVB097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVB097_END 0x1614 +#define NVB097_END_V 0:0 + +#define NVB097_BEGIN 0x1618 +#define NVB097_BEGIN_OP 15:0 +#define NVB097_BEGIN_OP_POINTS 0x00000000 +#define NVB097_BEGIN_OP_LINES 0x00000001 +#define NVB097_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVB097_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVB097_BEGIN_OP_TRIANGLES 0x00000004 +#define NVB097_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVB097_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVB097_BEGIN_OP_QUADS 0x00000007 +#define NVB097_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVB097_BEGIN_OP_POLYGON 0x00000009 +#define NVB097_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVB097_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVB097_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_BEGIN_OP_PATCH 0x0000000E +#define NVB097_BEGIN_PRIMITIVE_ID 24:24 +#define NVB097_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVB097_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVB097_BEGIN_INSTANCE_ID 27:26 +#define NVB097_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVB097_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVB097_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVB097_BEGIN_SPLIT_MODE 30:29 +#define NVB097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVB097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVB097_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVB097_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 + +#define NVB097_SET_VERTEX_ID_COPY 0x161c +#define NVB097_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVB097_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVB097_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVB097_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVB097_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVB097_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVB097_LOAD_PRIMITIVE_ID 0x1624 +#define NVB097_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVB097_SET_SHADER_BASED_CULL 0x162c +#define NVB097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVB097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVB097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVB097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_CLASS_VERSION 0x1638 +#define NVB097_SET_CLASS_VERSION_CURRENT 15:0 +#define NVB097_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB097_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVB097_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVB097_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVB097_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVB097_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVB097_SET_DA_OUTPUT 0x164c +#define NVB097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVB097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVB097_SET_ANTI_ALIASED_POINT 0x1658 +#define NVB097_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVB097_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_POINT_CENTER_MODE 0x165c +#define NVB097_SET_POINT_CENTER_MODE_V 31:0 +#define NVB097_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVB097_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVB097_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVB097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVB097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVB097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVB097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVB097_SET_LINE_STIPPLE 0x166c +#define NVB097_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVB097_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVB097_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVB097_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVB097_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVB097_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVB097_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVB097_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVB097_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVB097_SET_PROVOKING_VERTEX 0x1684 +#define NVB097_SET_PROVOKING_VERTEX_V 0:0 +#define NVB097_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVB097_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVB097_SET_TWO_SIDED_LIGHT 0x1688 +#define NVB097_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVB097_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_POLYGON_STIPPLE 0x168c +#define NVB097_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVB097_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_SHADER_CONTROL 0x1690 +#define NVB097_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVB097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVB097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVB097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVB097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVB097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVB097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVB097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVB097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVB097_CHECK_CLASS_VERSION 0x16a0 +#define NVB097_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVB097_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB097_SET_SPH_VERSION 0x16a4 +#define NVB097_SET_SPH_VERSION_CURRENT 15:0 +#define NVB097_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB097_CHECK_SPH_VERSION 0x16a8 +#define NVB097_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVB097_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVB097_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVB097_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVB097_SET_AAM_VERSION 0x1790 +#define NVB097_SET_AAM_VERSION_CURRENT 15:0 +#define NVB097_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB097_CHECK_AAM_VERSION 0x1794 +#define NVB097_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVB097_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB097_SET_ZT_LAYER 0x179c +#define NVB097_SET_ZT_LAYER_OFFSET 15:0 + +#define NVB097_SET_INDEX_BUFFER_A 0x17c8 +#define NVB097_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVB097_SET_INDEX_BUFFER_B 0x17cc +#define NVB097_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVB097_SET_INDEX_BUFFER_C 0x17d0 +#define NVB097_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVB097_SET_INDEX_BUFFER_D 0x17d4 +#define NVB097_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVB097_SET_INDEX_BUFFER_E 0x17d8 +#define NVB097_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVB097_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVB097_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVB097_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVB097_SET_INDEX_BUFFER_F 0x17dc +#define NVB097_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVB097_DRAW_INDEX_BUFFER 0x17e0 +#define NVB097_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVB097_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVB097_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVB097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVB097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVB097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVB097_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVB097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVB097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVB097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVB097_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVB097_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVB097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVB097_OGL_SET_CULL 0x1918 +#define NVB097_OGL_SET_CULL_ENABLE 0:0 +#define NVB097_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVB097_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVB097_OGL_SET_FRONT_FACE 0x191c +#define NVB097_OGL_SET_FRONT_FACE_V 31:0 +#define NVB097_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVB097_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVB097_OGL_SET_CULL_FACE 0x1920 +#define NVB097_OGL_SET_CULL_FACE_V 31:0 +#define NVB097_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVB097_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVB097_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVB097_SET_VIEWPORT_PIXEL 0x1924 +#define NVB097_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVB097_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVB097_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVB097_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVB097_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVB097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVB097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVB097_SET_USER_CLIP_OP 0x1940 +#define NVB097_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVB097_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVB097_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVB097_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVB097_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVB097_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVB097_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVB097_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVB097_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVB097_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVB097_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVB097_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVB097_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVB097_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVB097_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVB097_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVB097_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVB097_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVB097_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVB097_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVB097_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVB097_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVB097_INVALIDATE_ZCULL 0x1958 +#define NVB097_INVALIDATE_ZCULL_V 31:0 +#define NVB097_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVB097_SET_ZCULL 0x1968 +#define NVB097_SET_ZCULL_Z_ENABLE 0:0 +#define NVB097_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVB097_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_ZCULL_BOUNDS 0x196c +#define NVB097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVB097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVB097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVB097_ZCULL_SYNC 0x1978 +#define NVB097_ZCULL_SYNC_V 31:0 + +#define NVB097_SET_CLIP_ID_TEST 0x197c +#define NVB097_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVB097_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVB097_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVB097_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVB097_SET_CLIP_ID 0x1984 +#define NVB097_SET_CLIP_ID_V 31:0 + +#define NVB097_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVB097_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVB097_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVB097_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVB097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVB097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVB097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVB097_SET_LOGIC_OP 0x19c4 +#define NVB097_SET_LOGIC_OP_ENABLE 0:0 +#define NVB097_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVB097_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_LOGIC_OP_FUNC 0x19c8 +#define NVB097_SET_LOGIC_OP_FUNC_V 31:0 +#define NVB097_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVB097_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVB097_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVB097_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVB097_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVB097_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVB097_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVB097_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVB097_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVB097_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVB097_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVB097_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVB097_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVB097_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVB097_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVB097_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVB097_SET_Z_COMPRESSION 0x19cc +#define NVB097_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVB097_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVB097_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVB097_CLEAR_SURFACE 0x19d0 +#define NVB097_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVB097_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVB097_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVB097_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVB097_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVB097_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVB097_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVB097_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVB097_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVB097_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVB097_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVB097_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVB097_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVB097_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVB097_SET_CT_WRITE_R_ENABLE 0:0 +#define NVB097_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVB097_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVB097_SET_CT_WRITE_G_ENABLE 4:4 +#define NVB097_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVB097_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVB097_SET_CT_WRITE_B_ENABLE 8:8 +#define NVB097_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVB097_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVB097_SET_CT_WRITE_A_ENABLE 12:12 +#define NVB097_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVB097_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVB097_PIPE_NOP 0x1a2c +#define NVB097_PIPE_NOP_V 31:0 + +#define NVB097_SET_SPARE00 0x1a30 +#define NVB097_SET_SPARE00_V 31:0 + +#define NVB097_SET_SPARE01 0x1a34 +#define NVB097_SET_SPARE01_V 31:0 + +#define NVB097_SET_SPARE02 0x1a38 +#define NVB097_SET_SPARE02_V 31:0 + +#define NVB097_SET_SPARE03 0x1a3c +#define NVB097_SET_SPARE03_V 31:0 + +#define NVB097_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVB097_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVB097_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVB097_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB097_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVB097_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVB097_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVB097_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVB097_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVB097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVB097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVB097_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVB097_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVB097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVB097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVB097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVB097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVB097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVB097_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVB097_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVB097_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVB097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVB097_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVB097_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVB097_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVB097_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVB097_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVB097_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVB097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVB097_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVB097_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVB097_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVB097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVB097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVB097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVB097_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVB097_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVB097_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVB097_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVB097_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVB097_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVB097_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVB097_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVB097_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVB097_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVB097_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVB097_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVB097_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVB097_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVB097_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVB097_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVB097_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVB097_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVB097_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NVB097_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NVB097_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVB097_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVB097_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVB097_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NVB097_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVB097_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVB097_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NVB097_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVB097_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NVB097_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NVB097_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVB097_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVB097_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVB097_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVB097_SET_FALCON00 0x2300 +#define NVB097_SET_FALCON00_V 31:0 + +#define NVB097_SET_FALCON01 0x2304 +#define NVB097_SET_FALCON01_V 31:0 + +#define NVB097_SET_FALCON02 0x2308 +#define NVB097_SET_FALCON02_V 31:0 + +#define NVB097_SET_FALCON03 0x230c +#define NVB097_SET_FALCON03_V 31:0 + +#define NVB097_SET_FALCON04 0x2310 +#define NVB097_SET_FALCON04_V 31:0 + +#define NVB097_SET_FALCON05 0x2314 +#define NVB097_SET_FALCON05_V 31:0 + +#define NVB097_SET_FALCON06 0x2318 +#define NVB097_SET_FALCON06_V 31:0 + +#define NVB097_SET_FALCON07 0x231c +#define NVB097_SET_FALCON07_V 31:0 + +#define NVB097_SET_FALCON08 0x2320 +#define NVB097_SET_FALCON08_V 31:0 + +#define NVB097_SET_FALCON09 0x2324 +#define NVB097_SET_FALCON09_V 31:0 + +#define NVB097_SET_FALCON10 0x2328 +#define NVB097_SET_FALCON10_V 31:0 + +#define NVB097_SET_FALCON11 0x232c +#define NVB097_SET_FALCON11_V 31:0 + +#define NVB097_SET_FALCON12 0x2330 +#define NVB097_SET_FALCON12_V 31:0 + +#define NVB097_SET_FALCON13 0x2334 +#define NVB097_SET_FALCON13_V 31:0 + +#define NVB097_SET_FALCON14 0x2338 +#define NVB097_SET_FALCON14_V 31:0 + +#define NVB097_SET_FALCON15 0x233c +#define NVB097_SET_FALCON15_V 31:0 + +#define NVB097_SET_FALCON16 0x2340 +#define NVB097_SET_FALCON16_V 31:0 + +#define NVB097_SET_FALCON17 0x2344 +#define NVB097_SET_FALCON17_V 31:0 + +#define NVB097_SET_FALCON18 0x2348 +#define NVB097_SET_FALCON18_V 31:0 + +#define NVB097_SET_FALCON19 0x234c +#define NVB097_SET_FALCON19_V 31:0 + +#define NVB097_SET_FALCON20 0x2350 +#define NVB097_SET_FALCON20_V 31:0 + +#define NVB097_SET_FALCON21 0x2354 +#define NVB097_SET_FALCON21_V 31:0 + +#define NVB097_SET_FALCON22 0x2358 +#define NVB097_SET_FALCON22_V 31:0 + +#define NVB097_SET_FALCON23 0x235c +#define NVB097_SET_FALCON23_V 31:0 + +#define NVB097_SET_FALCON24 0x2360 +#define NVB097_SET_FALCON24_V 31:0 + +#define NVB097_SET_FALCON25 0x2364 +#define NVB097_SET_FALCON25_V 31:0 + +#define NVB097_SET_FALCON26 0x2368 +#define NVB097_SET_FALCON26_V 31:0 + +#define NVB097_SET_FALCON27 0x236c +#define NVB097_SET_FALCON27_V 31:0 + +#define NVB097_SET_FALCON28 0x2370 +#define NVB097_SET_FALCON28_V 31:0 + +#define NVB097_SET_FALCON29 0x2374 +#define NVB097_SET_FALCON29_V 31:0 + +#define NVB097_SET_FALCON30 0x2378 +#define NVB097_SET_FALCON30_V 31:0 + +#define NVB097_SET_FALCON31 0x237c +#define NVB097_SET_FALCON31_V 31:0 + +#define NVB097_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVB097_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVB097_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVB097_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVB097_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVB097_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVB097_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVB097_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVB097_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVB097_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVB097_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVB097_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVB097_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVB097_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVB097_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVB097_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVB097_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVB097_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVB097_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVB097_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVB097_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVB097_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVB097_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVB097_SET_COLOR_CLAMP 0x2600 +#define NVB097_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVB097_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVB097_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BINDLESS_TEXTURE 0x2608 +#define NVB097_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVB097_SET_TRAP_HANDLER 0x260c +#define NVB097_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVB097_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVB097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVB097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVB097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVB097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVB097_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVB097_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB097_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVB097_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB097_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVB097_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVB097_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVB097_CALL_MME_MACRO_V 31:0 + +#define NVB097_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVB097_CALL_MME_DATA_V 31:0 + +#endif /* _cl_maxwell_a_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clb0b0.h b/userspace/sdks/nv570/inc/class/clb0b0.h new file mode 100644 index 0000000..030040c --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clb0b0.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "nvtypes.h" + +#ifndef _clb0b0_h_ +#define _clb0b0_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVB0B0_VIDEO_DECODER (0x0000B0B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clb0b0_h diff --git a/userspace/sdks/nv570/inc/class/clb0b5.h b/userspace/sdks/nv570/inc/class/clb0b5.h new file mode 100644 index 0000000..63fe695 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clb0b5.h @@ -0,0 +1,261 @@ +/******************************************************************************* + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clb0b5_h_ +#define _clb0b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define MAXWELL_DMA_COPY_A (0x0000B0B5) + +#define NVB0B5_NOP (0x00000100) +#define NVB0B5_NOP_PARAMETER 31:0 +#define NVB0B5_PM_TRIGGER (0x00000140) +#define NVB0B5_PM_TRIGGER_V 31:0 +#define NVB0B5_SET_SEMAPHORE_A (0x00000240) +#define NVB0B5_SET_SEMAPHORE_A_UPPER 7:0 +#define NVB0B5_SET_SEMAPHORE_B (0x00000244) +#define NVB0B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVB0B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVB0B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVB0B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVB0B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVB0B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVB0B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVB0B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVB0B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVB0B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVB0B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVB0B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVB0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVB0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVB0B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVB0B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVB0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVB0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVB0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVB0B5_SET_DST_PHYS_MODE (0x00000264) +#define NVB0B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVB0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVB0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVB0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVB0B5_LAUNCH_DMA (0x00000300) +#define NVB0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVB0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVB0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVB0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVB0B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVB0B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVB0B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVB0B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVB0B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVB0B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVB0B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVB0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVB0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVB0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVB0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVB0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVB0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVB0B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVB0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVB0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVB0B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVB0B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVB0B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVB0B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVB0B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVB0B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVB0B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVB0B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVB0B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVB0B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVB0B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVB0B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVB0B5_LAUNCH_DMA_BYPASS_L2 20:20 +#define NVB0B5_LAUNCH_DMA_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVB0B5_LAUNCH_DMA_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVB0B5_OFFSET_IN_UPPER (0x00000400) +#define NVB0B5_OFFSET_IN_UPPER_UPPER 7:0 +#define NVB0B5_OFFSET_IN_LOWER (0x00000404) +#define NVB0B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVB0B5_OFFSET_OUT_UPPER (0x00000408) +#define NVB0B5_OFFSET_OUT_UPPER_UPPER 7:0 +#define NVB0B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVB0B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVB0B5_PITCH_IN (0x00000410) +#define NVB0B5_PITCH_IN_VALUE 31:0 +#define NVB0B5_PITCH_OUT (0x00000414) +#define NVB0B5_PITCH_OUT_VALUE 31:0 +#define NVB0B5_LINE_LENGTH_IN (0x00000418) +#define NVB0B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVB0B5_LINE_COUNT (0x0000041C) +#define NVB0B5_LINE_COUNT_VALUE 31:0 +#define NVB0B5_SET_REMAP_CONST_A (0x00000700) +#define NVB0B5_SET_REMAP_CONST_A_V 31:0 +#define NVB0B5_SET_REMAP_CONST_B (0x00000704) +#define NVB0B5_SET_REMAP_CONST_B_V 31:0 +#define NVB0B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVB0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVB0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVB0B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVB0B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVB0B5_SET_DST_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) +#define NVB0B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVB0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVB0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) +#define NVB0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVB0B5_SET_DST_WIDTH (0x00000710) +#define NVB0B5_SET_DST_WIDTH_V 31:0 +#define NVB0B5_SET_DST_HEIGHT (0x00000714) +#define NVB0B5_SET_DST_HEIGHT_V 31:0 +#define NVB0B5_SET_DST_DEPTH (0x00000718) +#define NVB0B5_SET_DST_DEPTH_V 31:0 +#define NVB0B5_SET_DST_LAYER (0x0000071C) +#define NVB0B5_SET_DST_LAYER_V 31:0 +#define NVB0B5_SET_DST_ORIGIN (0x00000720) +#define NVB0B5_SET_DST_ORIGIN_X 15:0 +#define NVB0B5_SET_DST_ORIGIN_Y 31:16 +#define NVB0B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVB0B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVB0B5_SET_SRC_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) +#define NVB0B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVB0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVB0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) +#define NVB0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVB0B5_SET_SRC_WIDTH (0x0000072C) +#define NVB0B5_SET_SRC_WIDTH_V 31:0 +#define NVB0B5_SET_SRC_HEIGHT (0x00000730) +#define NVB0B5_SET_SRC_HEIGHT_V 31:0 +#define NVB0B5_SET_SRC_DEPTH (0x00000734) +#define NVB0B5_SET_SRC_DEPTH_V 31:0 +#define NVB0B5_SET_SRC_LAYER (0x00000738) +#define NVB0B5_SET_SRC_LAYER_V 31:0 +#define NVB0B5_SET_SRC_ORIGIN (0x0000073C) +#define NVB0B5_SET_SRC_ORIGIN_X 15:0 +#define NVB0B5_SET_SRC_ORIGIN_Y 31:16 +#define NVB0B5_PM_TRIGGER_END (0x00001114) +#define NVB0B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clb0b5_h + diff --git a/userspace/sdks/nv570/inc/class/clb0b5sw.h b/userspace/sdks/nv570/inc/class/clb0b5sw.h new file mode 100644 index 0000000..06fba11 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clb0b5sw.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clb0b5sw.finn +// + + + +// +// Using VERSION_0 will cause the API to interpret +// engineType as a CE engine instance. This allows +// for backward compatibility with 85B5sw and 90B5sw. +// +#define NVB0B5_ALLOCATION_PARAMETERS_VERSION_0 0 + +// +// Using VERSION_1 will cause the API to interpret +// engineType as an NV2080_ENGINE_TYPE ordinal. +// +#define NVB0B5_ALLOCATION_PARAMETERS_VERSION_1 1 + +#define NVB0B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xb0b5U) + +typedef struct NVB0B5_ALLOCATION_PARAMETERS { + NvU32 version; + NvU32 engineType; +} NVB0B5_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clb0c0.h b/userspace/sdks/nv570/inc/class/clb0c0.h new file mode 100644 index 0000000..c343c51 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clb0c0.h @@ -0,0 +1,720 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_maxwell_compute_a_h_ +#define _cl_maxwell_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl maxwell_compute_a */ + +#include "nvtypes.h" + +#define MAXWELL_COMPUTE_A 0xB0C0 + +#define NVB0C0_SET_OBJECT 0x0000 +#define NVB0C0_SET_OBJECT_CLASS_ID 15:0 +#define NVB0C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVB0C0_NO_OPERATION 0x0100 +#define NVB0C0_NO_OPERATION_V 31:0 + +#define NVB0C0_SET_NOTIFY_A 0x0104 +#define NVB0C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_SET_NOTIFY_B 0x0108 +#define NVB0C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_NOTIFY 0x010c +#define NVB0C0_NOTIFY_TYPE 31:0 +#define NVB0C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVB0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVB0C0_WAIT_FOR_IDLE 0x0110 +#define NVB0C0_WAIT_FOR_IDLE_V 31:0 + +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB0C0_SEND_GO_IDLE 0x013c +#define NVB0C0_SEND_GO_IDLE_V 31:0 + +#define NVB0C0_PM_TRIGGER 0x0140 +#define NVB0C0_PM_TRIGGER_V 31:0 + +#define NVB0C0_PM_TRIGGER_WFI 0x0144 +#define NVB0C0_PM_TRIGGER_WFI_V 31:0 + +#define NVB0C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVB0C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVB0C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVB0C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVB0C0_LINE_LENGTH_IN 0x0180 +#define NVB0C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVB0C0_LINE_COUNT 0x0184 +#define NVB0C0_LINE_COUNT_VALUE 31:0 + +#define NVB0C0_OFFSET_OUT_UPPER 0x0188 +#define NVB0C0_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVB0C0_OFFSET_OUT 0x018c +#define NVB0C0_OFFSET_OUT_VALUE 31:0 + +#define NVB0C0_PITCH_OUT 0x0190 +#define NVB0C0_PITCH_OUT_VALUE 31:0 + +#define NVB0C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVB0C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVB0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVB0C0_SET_DST_WIDTH 0x0198 +#define NVB0C0_SET_DST_WIDTH_V 31:0 + +#define NVB0C0_SET_DST_HEIGHT 0x019c +#define NVB0C0_SET_DST_HEIGHT_V 31:0 + +#define NVB0C0_SET_DST_DEPTH 0x01a0 +#define NVB0C0_SET_DST_DEPTH_V 31:0 + +#define NVB0C0_SET_DST_LAYER 0x01a4 +#define NVB0C0_SET_DST_LAYER_V 31:0 + +#define NVB0C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVB0C0_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVB0C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVB0C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVB0C0_LAUNCH_DMA 0x01b0 +#define NVB0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVB0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVB0C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVB0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVB0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVB0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVB0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVB0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVB0C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVB0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB0C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVB0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVB0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVB0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVB0C0_LOAD_INLINE_DATA 0x01b4 +#define NVB0C0_LOAD_INLINE_DATA_V 31:0 + +#define NVB0C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVB0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVB0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVB0C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB0C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVB0C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVB0C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVB0C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVB0C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVB0C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVB0C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVB0C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVB0C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVB0C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVB0C0_PERFMON_TRANSFER 0x0210 +#define NVB0C0_PERFMON_TRANSFER_V 31:0 + +#define NVB0C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVB0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0218 +#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVB0C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVB0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVB0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVB0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVB0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVB0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVB0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVB0C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVB0C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVB0C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVB0C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVB0C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVB0C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVB0C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVB0C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVB0C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVB0C0_SET_CWD_CONTROL 0x0240 +#define NVB0C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVB0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVB0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVB0C0_SET_CWD_REF_COUNTER 0x0248 +#define NVB0C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVB0C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVB0C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVB0C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVB0C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVB0C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVB0C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVB0C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVB0C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVB0C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVB0C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVB0C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVB0C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVB0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB0C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVB0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVB0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB0C0_SET_QMD_VERSION 0x0288 +#define NVB0C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVB0C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB0C0_CHECK_QMD_VERSION 0x0290 +#define NVB0C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVB0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB0C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVB0C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVB0C0_SEND_PCAS_A 0x02b4 +#define NVB0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVB0C0_SEND_PCAS_B 0x02b8 +#define NVB0C0_SEND_PCAS_B_FROM 23:0 +#define NVB0C0_SEND_PCAS_B_DELTA 31:24 + +#define NVB0C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVB0C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVB0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVB0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVB0C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVB0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVB0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVB0C0_SET_SPA_VERSION 0x0310 +#define NVB0C0_SET_SPA_VERSION_MINOR 7:0 +#define NVB0C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVB0C0_SET_FALCON00 0x0500 +#define NVB0C0_SET_FALCON00_V 31:0 + +#define NVB0C0_SET_FALCON01 0x0504 +#define NVB0C0_SET_FALCON01_V 31:0 + +#define NVB0C0_SET_FALCON02 0x0508 +#define NVB0C0_SET_FALCON02_V 31:0 + +#define NVB0C0_SET_FALCON03 0x050c +#define NVB0C0_SET_FALCON03_V 31:0 + +#define NVB0C0_SET_FALCON04 0x0510 +#define NVB0C0_SET_FALCON04_V 31:0 + +#define NVB0C0_SET_FALCON05 0x0514 +#define NVB0C0_SET_FALCON05_V 31:0 + +#define NVB0C0_SET_FALCON06 0x0518 +#define NVB0C0_SET_FALCON06_V 31:0 + +#define NVB0C0_SET_FALCON07 0x051c +#define NVB0C0_SET_FALCON07_V 31:0 + +#define NVB0C0_SET_FALCON08 0x0520 +#define NVB0C0_SET_FALCON08_V 31:0 + +#define NVB0C0_SET_FALCON09 0x0524 +#define NVB0C0_SET_FALCON09_V 31:0 + +#define NVB0C0_SET_FALCON10 0x0528 +#define NVB0C0_SET_FALCON10_V 31:0 + +#define NVB0C0_SET_FALCON11 0x052c +#define NVB0C0_SET_FALCON11_V 31:0 + +#define NVB0C0_SET_FALCON12 0x0530 +#define NVB0C0_SET_FALCON12_V 31:0 + +#define NVB0C0_SET_FALCON13 0x0534 +#define NVB0C0_SET_FALCON13_V 31:0 + +#define NVB0C0_SET_FALCON14 0x0538 +#define NVB0C0_SET_FALCON14_V 31:0 + +#define NVB0C0_SET_FALCON15 0x053c +#define NVB0C0_SET_FALCON15_V 31:0 + +#define NVB0C0_SET_FALCON16 0x0540 +#define NVB0C0_SET_FALCON16_V 31:0 + +#define NVB0C0_SET_FALCON17 0x0544 +#define NVB0C0_SET_FALCON17_V 31:0 + +#define NVB0C0_SET_FALCON18 0x0548 +#define NVB0C0_SET_FALCON18_V 31:0 + +#define NVB0C0_SET_FALCON19 0x054c +#define NVB0C0_SET_FALCON19_V 31:0 + +#define NVB0C0_SET_FALCON20 0x0550 +#define NVB0C0_SET_FALCON20_V 31:0 + +#define NVB0C0_SET_FALCON21 0x0554 +#define NVB0C0_SET_FALCON21_V 31:0 + +#define NVB0C0_SET_FALCON22 0x0558 +#define NVB0C0_SET_FALCON22_V 31:0 + +#define NVB0C0_SET_FALCON23 0x055c +#define NVB0C0_SET_FALCON23_V 31:0 + +#define NVB0C0_SET_FALCON24 0x0560 +#define NVB0C0_SET_FALCON24_V 31:0 + +#define NVB0C0_SET_FALCON25 0x0564 +#define NVB0C0_SET_FALCON25_V 31:0 + +#define NVB0C0_SET_FALCON26 0x0568 +#define NVB0C0_SET_FALCON26_V 31:0 + +#define NVB0C0_SET_FALCON27 0x056c +#define NVB0C0_SET_FALCON27_V 31:0 + +#define NVB0C0_SET_FALCON28 0x0570 +#define NVB0C0_SET_FALCON28_V 31:0 + +#define NVB0C0_SET_FALCON29 0x0574 +#define NVB0C0_SET_FALCON29_V 31:0 + +#define NVB0C0_SET_FALCON30 0x0578 +#define NVB0C0_SET_FALCON30_V 31:0 + +#define NVB0C0_SET_FALCON31 0x057c +#define NVB0C0_SET_FALCON31_V 31:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVB0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVB0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVB0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVB0C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVB0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVB0C0_SET_SPARE_NOOP12 0x0f44 +#define NVB0C0_SET_SPARE_NOOP12_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP13 0x0f48 +#define NVB0C0_SET_SPARE_NOOP13_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP14 0x0f4c +#define NVB0C0_SET_SPARE_NOOP14_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP15 0x0f50 +#define NVB0C0_SET_SPARE_NOOP15_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP00 0x1040 +#define NVB0C0_SET_SPARE_NOOP00_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP01 0x1044 +#define NVB0C0_SET_SPARE_NOOP01_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP02 0x1048 +#define NVB0C0_SET_SPARE_NOOP02_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP03 0x104c +#define NVB0C0_SET_SPARE_NOOP03_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP04 0x1050 +#define NVB0C0_SET_SPARE_NOOP04_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP05 0x1054 +#define NVB0C0_SET_SPARE_NOOP05_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP06 0x1058 +#define NVB0C0_SET_SPARE_NOOP06_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP07 0x105c +#define NVB0C0_SET_SPARE_NOOP07_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP08 0x1060 +#define NVB0C0_SET_SPARE_NOOP08_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP09 0x1064 +#define NVB0C0_SET_SPARE_NOOP09_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP10 0x1068 +#define NVB0C0_SET_SPARE_NOOP10_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP11 0x106c +#define NVB0C0_SET_SPARE_NOOP11_V 31:0 + +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVB0C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVB0C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVB0C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVB0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVB0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVB0C0_SET_RENDER_ENABLE_A 0x1550 +#define NVB0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_RENDER_ENABLE_B 0x1554 +#define NVB0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_RENDER_ENABLE_C 0x1558 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB0C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVB0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVB0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVB0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVB0C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVB0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVB0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVB0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVB0C0_SET_PROGRAM_REGION_A 0x1608 +#define NVB0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_SET_PROGRAM_REGION_B 0x160c +#define NVB0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVB0C0_PIPE_NOP 0x1a2c +#define NVB0C0_PIPE_NOP_V 31:0 + +#define NVB0C0_SET_SPARE00 0x1a30 +#define NVB0C0_SET_SPARE00_V 31:0 + +#define NVB0C0_SET_SPARE01 0x1a34 +#define NVB0C0_SET_SPARE01_V 31:0 + +#define NVB0C0_SET_SPARE02 0x1a38 +#define NVB0C0_SET_SPARE02_V 31:0 + +#define NVB0C0_SET_SPARE03 0x1a3c +#define NVB0C0_SET_SPARE03_V 31:0 + +#define NVB0C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVB0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVB0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVB0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB0C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVB0C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVB0C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVB0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVB0C0_SET_TRAP_HANDLER 0x260c +#define NVB0C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVB0C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVB0C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB0C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVB0C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB0C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVB0C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_maxwell_compute_a_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clb0cc.h b/userspace/sdks/nv570/inc/class/clb0cc.h new file mode 100644 index 0000000..61ee79f --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clb0cc.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clb0cc_h_ +#define _clb0cc_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define MAXWELL_PROFILER (0x0000B0CC) + +/* + * This is an interface definition for MAXWELL_PROFILER class and cannot + * be instantiated by clients. + * MAXWELL_PROFILER_DEVICE extends this interface to define interface for + * device level profiling + */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clb0cc_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clb0cd.h b/userspace/sdks/nv570/inc/class/clb0cd.h new file mode 100644 index 0000000..c47c899 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clb0cd.h @@ -0,0 +1,49 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clb0cd.finn +// + +#include "nvcfg_sdk.h" + +#define PROFILER_DEVICE_EVENT (0xb0cdU) /* finn: Evaluated from "NVB0CD_ALLOC_PARAMETERS_MESSAGE_ID" */ + +#define NVB0CD_ALLOC_PARAMETERS_MESSAGE_ID (0xb0cdU) + +typedef struct NVB0CD_ALLOC_PARAMETERS { + // + // capDescriptor is a file descriptor for unix RM clients, but a void + // pointer for windows RM clients. + // + // capDescriptor is transparent to RM clients i.e. RM's user-mode shim + // populates this field on behalf of clients. + // + NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8); +} NVB0CD_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clb0ce.h b/userspace/sdks/nv570/inc/class/clb0ce.h new file mode 100644 index 0000000..5371cc9 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clb0ce.h @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clb0ce.finn +// + +#define PROFILER_CONTEXT_EVENT (0xb0ceU) /* finn: Evaluated from "NVB0CE_ALLOC_PARAMETERS_MESSAGE_ID" */ + +#define NVB0CE_ALLOC_PARAMETERS_MESSAGE_ID (0xb0ceU) + +typedef struct NVB0CE_ALLOC_PARAMETERS { + // + // capDescriptor is a file descriptor for unix RM clients, but a void + // pointer for windows RM clients. + // + // capDescriptor is transparent to RM clients i.e. RM's user-mode shim + // populates this field on behalf of clients. + // + NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8); + // + // When set to TRUE, this parameter indicates that the client aquires + // a file descriptor that correspond with PROFILER_DEVICE_EVENT instead + // of PROFILER_CONTEXT_EVENT. + // + NvBool bIsDeviceEventCap; +} NVB0CE_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clb197.h b/userspace/sdks/nv570/inc/class/clb197.h new file mode 100644 index 0000000..f8c976c --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clb197.h @@ -0,0 +1,4160 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_maxwell_b_h_ +#define _cl_maxwell_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl maxwell_b */ + +#include "nvtypes.h" + +#define MAXWELL_B 0xB197 + +#define NVB197_SET_OBJECT 0x0000 +#define NVB197_SET_OBJECT_CLASS_ID 15:0 +#define NVB197_SET_OBJECT_ENGINE_ID 20:16 + +#define NVB197_NO_OPERATION 0x0100 +#define NVB197_NO_OPERATION_V 31:0 + +#define NVB197_SET_NOTIFY_A 0x0104 +#define NVB197_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVB197_SET_NOTIFY_B 0x0108 +#define NVB197_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVB197_NOTIFY 0x010c +#define NVB197_NOTIFY_TYPE 31:0 +#define NVB197_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVB197_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVB197_WAIT_FOR_IDLE 0x0110 +#define NVB197_WAIT_FOR_IDLE_V 31:0 + +#define NVB197_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVB197_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVB197_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVB197_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVB197_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVB197_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVB197_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVB197_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVB197_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVB197_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVB197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVB197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVB197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVB197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVB197_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVB197_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVB197_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVB197_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVB197_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB197_SEND_GO_IDLE 0x013c +#define NVB197_SEND_GO_IDLE_V 31:0 + +#define NVB197_PM_TRIGGER 0x0140 +#define NVB197_PM_TRIGGER_V 31:0 + +#define NVB197_PM_TRIGGER_WFI 0x0144 +#define NVB197_PM_TRIGGER_WFI_V 31:0 + +#define NVB197_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVB197_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVB197_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVB197_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVB197_LINE_LENGTH_IN 0x0180 +#define NVB197_LINE_LENGTH_IN_VALUE 31:0 + +#define NVB197_LINE_COUNT 0x0184 +#define NVB197_LINE_COUNT_VALUE 31:0 + +#define NVB197_OFFSET_OUT_UPPER 0x0188 +#define NVB197_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVB197_OFFSET_OUT 0x018c +#define NVB197_OFFSET_OUT_VALUE 31:0 + +#define NVB197_PITCH_OUT 0x0190 +#define NVB197_PITCH_OUT_VALUE 31:0 + +#define NVB197_SET_DST_BLOCK_SIZE 0x0194 +#define NVB197_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVB197_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVB197_SET_DST_WIDTH 0x0198 +#define NVB197_SET_DST_WIDTH_V 31:0 + +#define NVB197_SET_DST_HEIGHT 0x019c +#define NVB197_SET_DST_HEIGHT_V 31:0 + +#define NVB197_SET_DST_DEPTH 0x01a0 +#define NVB197_SET_DST_DEPTH_V 31:0 + +#define NVB197_SET_DST_LAYER 0x01a4 +#define NVB197_SET_DST_LAYER_V 31:0 + +#define NVB197_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVB197_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVB197_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVB197_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVB197_LAUNCH_DMA 0x01b0 +#define NVB197_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVB197_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB197_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB197_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVB197_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVB197_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVB197_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVB197_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVB197_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVB197_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVB197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVB197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVB197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVB197_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVB197_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB197_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB197_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB197_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVB197_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB197_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB197_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVB197_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVB197_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVB197_LOAD_INLINE_DATA 0x01b4 +#define NVB197_LOAD_INLINE_DATA_V 31:0 + +#define NVB197_SET_I2M_SEMAPHORE_A 0x01dc +#define NVB197_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVB197_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVB197_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB197_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVB197_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVB197_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVB197_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVB197_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVB197_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVB197_SET_I2M_SPARE_NOOP03 0x01fc +#define NVB197_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVB197_RUN_DS_NOW 0x0200 +#define NVB197_RUN_DS_NOW_V 31:0 + +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVB197_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVB197_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVB197_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVB197_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVB197_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVB197_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_GS_DM_FIFO 0x0214 +#define NVB197_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVB197_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVB197_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVB197_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVB197_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB197_INVALIDATE_SHADER_CACHES 0x021c +#define NVB197_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVB197_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVB197_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVB197_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVB197_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVB197_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVB197_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVB197_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVB197_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVB197_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVB197_INCREMENT_SYNC_POINT 0x02c8 +#define NVB197_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVB197_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVB197_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVB197_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVB197_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVB197_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVB197_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVB197_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NVB197_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NVB197_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVB197_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVB197_DECOMPRESS_SURFACE 0x02e0 +#define NVB197_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVB197_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVB197_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVB197_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVB197_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVB197_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVB197_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVB197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVB197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVB197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVB197_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVB197_SET_ZCULL_SUBREGION 0x02e8 +#define NVB197_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVB197_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVB197_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVB197_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVB197_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVB197_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVB197_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVB197_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVB197_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVB197_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVB197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVB197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVB197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVB197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVB197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVB197_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVB197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVB197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVB197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVB197_DRAW_ZERO_INDEX 0x0304 +#define NVB197_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVB197_SET_L1_CONFIGURATION 0x0308 +#define NVB197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVB197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVB197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVB197_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVB197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVB197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVB197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVB197_SET_SPA_VERSION 0x0310 +#define NVB197_SET_SPA_VERSION_MINOR 7:0 +#define NVB197_SET_SPA_VERSION_MAJOR 15:8 + +#define NVB197_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NVB197_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NVB197_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_SNAP_GRID_LINE 0x0318 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVB197_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVB197_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVB197_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVB197_SET_SNAP_GRID_NON_LINE 0x031c +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVB197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVB197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVB197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVB197_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVB197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVB197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVB197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVB197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVB197_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVB197_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVB197_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVB197_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVB197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVB197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVB197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVB197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVB197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVB197_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVB197_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVB197_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVB197_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVB197_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVB197_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVB197_SET_TESSELLATION_LOD_V1 0x0330 +#define NVB197_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVB197_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVB197_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVB197_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVB197_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVB197_RESERVED_TG07 0x033c +#define NVB197_RESERVED_TG07_V 0:0 + +#define NVB197_RESERVED_TG08 0x0340 +#define NVB197_RESERVED_TG08_V 0:0 + +#define NVB197_RESERVED_TG09 0x0344 +#define NVB197_RESERVED_TG09_V 0:0 + +#define NVB197_RESERVED_TG10 0x0348 +#define NVB197_RESERVED_TG10_V 0:0 + +#define NVB197_RESERVED_TG11 0x034c +#define NVB197_RESERVED_TG11_V 0:0 + +#define NVB197_RESERVED_TG12 0x0350 +#define NVB197_RESERVED_TG12_V 0:0 + +#define NVB197_RESERVED_TG13 0x0354 +#define NVB197_RESERVED_TG13_V 0:0 + +#define NVB197_RESERVED_TG14 0x0358 +#define NVB197_RESERVED_TG14_V 0:0 + +#define NVB197_RESERVED_TG15 0x035c +#define NVB197_RESERVED_TG15_V 0:0 + +#define NVB197_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVB197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVB197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVB197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVB197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVB197_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVB197_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVB197_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVB197_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVB197_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVB197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVB197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVB197_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVB197_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVB197_SET_RASTER_ENABLE 0x037c +#define NVB197_SET_RASTER_ENABLE_V 0:0 +#define NVB197_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVB197_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVB197_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVB197_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVB197_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVB197_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVB197_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVB197_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVB197_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVB197_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVB197_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVB197_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVB197_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVB197_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVB197_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVB197_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVB197_SET_RASTER_INPUT 0x0740 +#define NVB197_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVB197_SET_STREAM_OUTPUT 0x0744 +#define NVB197_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVB197_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVB197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVB197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ALPHA_FRACTION 0x074c +#define NVB197_SET_ALPHA_FRACTION_V 7:0 + +#define NVB197_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVB197_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVB197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVB197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVB197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVB197_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVB197_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVB197_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB197_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVB197_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVB197_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVB197_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVB197_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVB197_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVB197_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVB197_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVB197_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVB197_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVB197_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVB197_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVB197_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVB197_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVB197_SET_ISBE_SAVE_RESTORE_PROGRAM 0x07ac +#define NVB197_SET_ISBE_SAVE_RESTORE_PROGRAM_OFFSET 31:0 + +#define NVB197_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVB197_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVB197_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVB197_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVB197_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVB197_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVB197_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVB197_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVB197_SET_CULL_BEFORE_FETCH 0x07dc +#define NVB197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVB197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVB197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVB197_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVB197_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVB197_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVB197_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVB197_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVB197_SET_ZCULL_STORAGE_A 0x07e8 +#define NVB197_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVB197_SET_ZCULL_STORAGE_B 0x07ec +#define NVB197_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVB197_SET_ZCULL_STORAGE_C 0x07f0 +#define NVB197_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVB197_SET_ZCULL_STORAGE_D 0x07f4 +#define NVB197_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVB197_SET_ZT_READ_ONLY 0x07f8 +#define NVB197_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVB197_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVB197_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVB197_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVB197_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVB197_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVB197_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVB197_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVB197_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVB197_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVB197_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVB197_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVB197_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVB197_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVB197_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVB197_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVB197_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVB197_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVB197_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVB197_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVB197_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVB197_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVB197_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVB197_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVB197_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB197_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVB197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVB197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVB197_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVB197_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVB197_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVB197_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVB197_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVB197_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVB197_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NVB197_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NVB197_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVB197_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVB197_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVB197_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVB197_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVB197_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVB197_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVB197_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVB197_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVB197_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVB197_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVB197_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVB197_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVB197_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVB197_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVB197_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVB197_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVB197_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVB197_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVB197_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVB197_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVB197_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVB197_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVB197_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVB197_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVB197_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVB197_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVB197_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVB197_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVB197_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVB197_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVB197_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVB197_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVB197_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVB197_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVB197_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVB197_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVB197_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVB197_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVB197_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVB197_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVB197_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVB197_SET_STATISTICS_COUNTER 0x0d68 +#define NVB197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVB197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVB197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVB197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVB197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVB197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVB197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVB197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVB197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVB197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVB197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVB197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVB197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVB197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVB197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVB197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVB197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVB197_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVB197_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVB197_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVB197_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVB197_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVB197_SET_VERTEX_ARRAY_START 0x0d74 +#define NVB197_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVB197_DRAW_VERTEX_ARRAY 0x0d78 +#define NVB197_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVB197_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVB197_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVB197_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVB197_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVB197_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVB197_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVB197_SET_Z_CLEAR_VALUE 0x0d90 +#define NVB197_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVB197_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVB197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVB197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVB197_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVB197_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVB197_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVB197_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVB197_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVB197_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVB197_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVB197_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVB197_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVB197_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVB197_SET_FRONT_POLYGON_MODE 0x0dac +#define NVB197_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVB197_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVB197_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVB197_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVB197_SET_BACK_POLYGON_MODE 0x0db0 +#define NVB197_SET_BACK_POLYGON_MODE_V 31:0 +#define NVB197_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVB197_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVB197_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVB197_SET_POLY_SMOOTH 0x0db4 +#define NVB197_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVB197_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ZT_MARK 0x0db8 +#define NVB197_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NVB197_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVB197_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVB197_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVB197_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVB197_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVB197_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVB197_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVB197_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVB197_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVB197_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVB197_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_PATCH 0x0dcc +#define NVB197_SET_PATCH_SIZE 7:0 + +#define NVB197_SET_ITERATED_BLEND 0x0dd0 +#define NVB197_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVB197_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVB197_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVB197_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVB197_SET_ZCULL_CRITERION 0x0dd8 +#define NVB197_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVB197_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVB197_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVB197_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVB197_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVB197_SET_ZCULL_CRITERION_SREF 23:16 +#define NVB197_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVB197_PIXEL_SHADER_BARRIER 0x0de0 +#define NVB197_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVB197_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVB197_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVB197_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVB197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVB197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVB197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVB197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVB197_SET_WINDOW_OFFSET_X 0x0df8 +#define NVB197_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVB197_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVB197_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVB197_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVB197_SET_SCISSOR_ENABLE_V 0:0 +#define NVB197_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVB197_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVB197_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVB197_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVB197_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVB197_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVB197_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0f10 +#define NVB197_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVB197_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVB197_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVB197_SET_VPC_PERF_KNOB 0x0f14 +#define NVB197_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVB197_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVB197_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVB197_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVB197_PM_LOCAL_TRIGGER 0x0f18 +#define NVB197_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVB197_SET_POST_Z_PS_IMASK 0x0f1c +#define NVB197_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVB197_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVB197_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVB197_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVB197_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVB197_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVB197_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVB197_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVB197_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVB197_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVB197_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVB197_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVB197_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVB197_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVB197_SET_BACK_STENCIL_MASK 0x0f58 +#define NVB197_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVB197_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVB197_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVB197_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVB197_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVB197_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVB197_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVB197_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVB197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVB197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVB197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVB197_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVB197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVB197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVB197_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVB197_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVB197_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVB197_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVB197_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVB197_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVB197_SET_SAMPLE_MASK 0x0fa4 +#define NVB197_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVB197_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVB197_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVB197_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVB197_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVB197_SET_CT_MRT_ENABLE 0x0fac +#define NVB197_SET_CT_MRT_ENABLE_V 0:0 +#define NVB197_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVB197_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVB197_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVB197_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVB197_SET_TIR 0x0fb4 +#define NVB197_SET_TIR_MODE 1:0 +#define NVB197_SET_TIR_MODE_DISABLED 0x00000000 +#define NVB197_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVB197_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVB197_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVB197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVB197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVB197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVB197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVB197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVB197_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVB197_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVB197_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVB197_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVB197_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVB197_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVB197_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVB197_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVB197_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVB197_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVB197_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_TIR_MODULATION 0x0fd4 +#define NVB197_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVB197_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVB197_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVB197_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVB197_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVB197_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVB197_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVB197_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVB197_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVB197_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVB197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVB197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVB197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVB197_SET_ZT_A 0x0fe0 +#define NVB197_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_ZT_B 0x0fe4 +#define NVB197_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_ZT_FORMAT 0x0fe8 +#define NVB197_SET_ZT_FORMAT_V 4:0 +#define NVB197_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVB197_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVB197_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVB197_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVB197_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVB197_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVB197_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVB197_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVB197_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVB197_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVB197_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVB197_SET_ZT_BLOCK_SIZE 0x0fec +#define NVB197_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVB197_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB197_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVB197_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVB197_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVB197_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVB197_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVB197_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVB197_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVB197_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVB197_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVB197_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVB197_SET_TILED_CACHE_BUNDLE_CONTROL 0x0ffc +#define NVB197_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT 0:0 +#define NVB197_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_FALSE 0x00000000 +#define NVB197_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_TRUE 0x00000001 + +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB197_SET_VIEWPORT_MULTICAST 0x1004 +#define NVB197_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVB197_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVB197_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVB197_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVB197_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVB197_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVB197_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVB197_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVB197_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVB197_SET_RESERVED_SW_METHOD00 0x1014 +#define NVB197_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVB197_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVB197_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVB197_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVB197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVB197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVB197_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVB197_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVB197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVB197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_RESERVED_SW_METHOD01 0x1028 +#define NVB197_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD02 0x102c +#define NVB197_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVB197_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVB197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVB197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVB197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVB197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVB197_SET_SPARE_NOOP01 0x1044 +#define NVB197_SET_SPARE_NOOP01_V 31:0 + +#define NVB197_SET_SPARE_NOOP02 0x1048 +#define NVB197_SET_SPARE_NOOP02_V 31:0 + +#define NVB197_SET_SPARE_NOOP03 0x104c +#define NVB197_SET_SPARE_NOOP03_V 31:0 + +#define NVB197_SET_SPARE_NOOP04 0x1050 +#define NVB197_SET_SPARE_NOOP04_V 31:0 + +#define NVB197_SET_SPARE_NOOP05 0x1054 +#define NVB197_SET_SPARE_NOOP05_V 31:0 + +#define NVB197_SET_SPARE_NOOP06 0x1058 +#define NVB197_SET_SPARE_NOOP06_V 31:0 + +#define NVB197_SET_SPARE_NOOP07 0x105c +#define NVB197_SET_SPARE_NOOP07_V 31:0 + +#define NVB197_SET_SPARE_NOOP08 0x1060 +#define NVB197_SET_SPARE_NOOP08_V 31:0 + +#define NVB197_SET_SPARE_NOOP09 0x1064 +#define NVB197_SET_SPARE_NOOP09_V 31:0 + +#define NVB197_SET_SPARE_NOOP10 0x1068 +#define NVB197_SET_SPARE_NOOP10_V 31:0 + +#define NVB197_SET_SPARE_NOOP11 0x106c +#define NVB197_SET_SPARE_NOOP11_V 31:0 + +#define NVB197_SET_SPARE_NOOP12 0x1070 +#define NVB197_SET_SPARE_NOOP12_V 31:0 + +#define NVB197_SET_SPARE_NOOP13 0x1074 +#define NVB197_SET_SPARE_NOOP13_V 31:0 + +#define NVB197_SET_SPARE_NOOP14 0x1078 +#define NVB197_SET_SPARE_NOOP14_V 31:0 + +#define NVB197_SET_SPARE_NOOP15 0x107c +#define NVB197_SET_SPARE_NOOP15_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVB197_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVB197_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVB197_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD06 0x10bc +#define NVB197_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVB197_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVB197_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVB197_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVB197_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVB197_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVB197_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVB197_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD13 0x10dc +#define NVB197_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVB197_UNBIND_ALL 0x10f4 +#define NVB197_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVB197_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVB197_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVB197_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB197_SET_RESERVED_SW_METHOD14 0x1100 +#define NVB197_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD15 0x1104 +#define NVB197_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVB197_NO_OPERATION_DATA_HI 0x110c +#define NVB197_NO_OPERATION_DATA_HI_V 31:0 + +#define NVB197_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVB197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVB197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVB197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVB197_PM_TRIGGER_END 0x1114 +#define NVB197_PM_TRIGGER_END_V 31:0 + +#define NVB197_SET_VERTEX_ID_BASE 0x1118 +#define NVB197_SET_VERTEX_ID_BASE_V 31:0 + +#define NVB197_SET_STENCIL_COMPRESSION 0x111c +#define NVB197_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVB197_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVB197_SET_TIR_CONTROL 0x1130 +#define NVB197_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVB197_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVB197_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVB197_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVB197_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVB197_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVB197_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVB197_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVB197_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 + +#define NVB197_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVB197_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVB197_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVB197_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVB197_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVB197_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVB197_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVB197_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVB197_SET_FILL_VIA_TRIANGLE 0x113c +#define NVB197_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVB197_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVB197_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVB197_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVB197_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVB197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVB197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVB197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVB197_FLUSH_PENDING_WRITES 0x1144 +#define NVB197_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVB197_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVB197_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVB197_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVB197_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVB197_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVB197_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVB197_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVB197_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVB197_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVB197_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVB197_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVB197_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVB197_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVB197_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVB197_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVB197_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVB197_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVB197_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVB197_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVB197_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVB197_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB197_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ZT_SPARSE 0x1208 +#define NVB197_SET_ZT_SPARSE_ENABLE 0:0 +#define NVB197_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVB197_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVB197_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVB197_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVB197_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_SET_CT_SELECT 0x121c +#define NVB197_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVB197_SET_CT_SELECT_TARGET0 6:4 +#define NVB197_SET_CT_SELECT_TARGET1 9:7 +#define NVB197_SET_CT_SELECT_TARGET2 12:10 +#define NVB197_SET_CT_SELECT_TARGET3 15:13 +#define NVB197_SET_CT_SELECT_TARGET4 18:16 +#define NVB197_SET_CT_SELECT_TARGET5 21:19 +#define NVB197_SET_CT_SELECT_TARGET6 24:22 +#define NVB197_SET_CT_SELECT_TARGET7 27:25 + +#define NVB197_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVB197_SET_ZT_SIZE_A 0x1228 +#define NVB197_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVB197_SET_ZT_SIZE_B 0x122c +#define NVB197_SET_ZT_SIZE_B_HEIGHT 16:0 + +#define NVB197_SET_ZT_SIZE_C 0x1230 +#define NVB197_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVB197_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVB197_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVB197_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVB197_SET_SAMPLER_BINDING 0x1234 +#define NVB197_SET_SAMPLER_BINDING_V 0:0 +#define NVB197_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVB197_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVB197_DRAW_AUTO 0x123c +#define NVB197_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVB197_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVB197_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVB197_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVB197_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVB197_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVB197_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVB197_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVB197_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVB197_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVB197_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB197_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVB197_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVB197_CLEAR_ZCULL_REGION 0x12c8 +#define NVB197_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVB197_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVB197_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVB197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVB197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVB197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVB197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVB197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVB197_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVB197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVB197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVB197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVB197_SET_DEPTH_TEST 0x12cc +#define NVB197_SET_DEPTH_TEST_ENABLE 0:0 +#define NVB197_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVB197_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_FILL_MODE 0x12d0 +#define NVB197_SET_FILL_MODE_V 31:0 +#define NVB197_SET_FILL_MODE_V_POINT 0x00000001 +#define NVB197_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVB197_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVB197_SET_SHADE_MODE 0x12d4 +#define NVB197_SET_SHADE_MODE_V 31:0 +#define NVB197_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVB197_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVB197_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVB197_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVB197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVB197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVB197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVB197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVB197_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVB197_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVB197_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVB197_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_DEPTH_WRITE 0x12e8 +#define NVB197_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVB197_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ALPHA_TEST 0x12ec +#define NVB197_SET_ALPHA_TEST_ENABLE 0:0 +#define NVB197_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVB197_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVB197_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVB197_DRAW_INLINE_INDEX4X8 0x1304 +#define NVB197_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVB197_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVB197_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVB197_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVB197_D3D_SET_CULL_MODE 0x1308 +#define NVB197_D3D_SET_CULL_MODE_V 31:0 +#define NVB197_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVB197_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVB197_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVB197_SET_DEPTH_FUNC 0x130c +#define NVB197_SET_DEPTH_FUNC_V 31:0 +#define NVB197_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVB197_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVB197_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB197_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB197_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVB197_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB197_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB197_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB197_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVB197_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVB197_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB197_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB197_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVB197_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB197_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB197_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB197_SET_ALPHA_REF 0x1310 +#define NVB197_SET_ALPHA_REF_V 31:0 + +#define NVB197_SET_ALPHA_FUNC 0x1314 +#define NVB197_SET_ALPHA_FUNC_V 31:0 +#define NVB197_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVB197_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVB197_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB197_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB197_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVB197_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB197_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB197_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB197_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVB197_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVB197_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB197_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB197_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVB197_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB197_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB197_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB197_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVB197_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVB197_SET_BLEND_CONST_RED 0x131c +#define NVB197_SET_BLEND_CONST_RED_V 31:0 + +#define NVB197_SET_BLEND_CONST_GREEN 0x1320 +#define NVB197_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVB197_SET_BLEND_CONST_BLUE 0x1324 +#define NVB197_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVB197_SET_BLEND_CONST_ALPHA 0x1328 +#define NVB197_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVB197_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVB197_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVB197_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVB197_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVB197_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVB197_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVB197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVB197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVB197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BLEND_COLOR_OP 0x1340 +#define NVB197_SET_BLEND_COLOR_OP_V 31:0 +#define NVB197_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB197_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB197_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB197_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVB197_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVB197_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVB197_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB197_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB197_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVB197_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_BLEND_ALPHA_OP 0x134c +#define NVB197_SET_BLEND_ALPHA_OP_V 31:0 +#define NVB197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB197_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVB197_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVB197_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVB197_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB197_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB197_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVB197_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVB197_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVB197_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVB197_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_SINGLE_ROP_CONTROL 0x135c +#define NVB197_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVB197_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BLEND(i) (0x1360+(i)*4) +#define NVB197_SET_BLEND_ENABLE 0:0 +#define NVB197_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVB197_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_STENCIL_TEST 0x1380 +#define NVB197_SET_STENCIL_TEST_ENABLE 0:0 +#define NVB197_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_STENCIL_OP_FAIL 0x1384 +#define NVB197_SET_STENCIL_OP_FAIL_V 31:0 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVB197_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVB197_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVB197_SET_STENCIL_OP_ZPASS 0x138c +#define NVB197_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVB197_SET_STENCIL_FUNC 0x1390 +#define NVB197_SET_STENCIL_FUNC_V 31:0 +#define NVB197_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVB197_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVB197_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB197_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB197_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVB197_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB197_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB197_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB197_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVB197_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVB197_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB197_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB197_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVB197_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB197_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB197_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB197_SET_STENCIL_FUNC_REF 0x1394 +#define NVB197_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVB197_SET_STENCIL_FUNC_MASK 0x1398 +#define NVB197_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVB197_SET_STENCIL_MASK 0x139c +#define NVB197_SET_STENCIL_MASK_V 7:0 + +#define NVB197_SET_DRAW_AUTO_START 0x13a4 +#define NVB197_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVB197_SET_PS_SATURATE 0x13a8 +#define NVB197_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVB197_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVB197_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVB197_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVB197_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVB197_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVB197_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVB197_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVB197_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVB197_SET_WINDOW_ORIGIN 0x13ac +#define NVB197_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVB197_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVB197_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVB197_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVB197_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVB197_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVB197_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVB197_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVB197_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVB197_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVB197_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVB197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVB197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ALPHA_HYSTERESIS 0x1420 +#define NVB197_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NVB197_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVB197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVB197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB197_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVB197_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVB197_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVB197_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVB197_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVB197_SET_PS_WARP_WATERMARKS 0x1450 +#define NVB197_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVB197_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVB197_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVB197_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVB197_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVB197_STORE_ZCULL 0x1464 +#define NVB197_STORE_ZCULL_V 0:0 + +#define NVB197_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVB197_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVB197_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVB197_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVB197_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVB197_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVB197_LOAD_ZCULL 0x1500 +#define NVB197_LOAD_ZCULL_V 0:0 + +#define NVB197_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVB197_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVB197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVB197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVB197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVB197_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVB197_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVB197_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVB197_SET_USER_CLIP_ENABLE 0x1510 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVB197_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVB197_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVB197_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_POINT_SIZE 0x1518 +#define NVB197_SET_POINT_SIZE_V 31:0 + +#define NVB197_SET_ZCULL_STATS 0x151c +#define NVB197_SET_ZCULL_STATS_ENABLE 0:0 +#define NVB197_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_POINT_SPRITE 0x1520 +#define NVB197_SET_POINT_SPRITE_ENABLE 0:0 +#define NVB197_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_SHADER_EXCEPTIONS 0x1528 +#define NVB197_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVB197_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVB197_CLEAR_REPORT_VALUE 0x1530 +#define NVB197_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVB197_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVB197_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVB197_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVB197_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVB197_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVB197_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 + +#define NVB197_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVB197_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVB197_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_ZT_SELECT 0x1538 +#define NVB197_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVB197_SET_RENDER_ENABLE_A 0x1550 +#define NVB197_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_RENDER_ENABLE_B 0x1554 +#define NVB197_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_RENDER_ENABLE_C 0x1558 +#define NVB197_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVB197_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB197_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB197_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB197_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB197_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB197_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVB197_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVB197_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVB197_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVB197_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVB197_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVB197_SET_ANTI_ALIASED_LINE 0x1570 +#define NVB197_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVB197_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_TEX_HEADER_POOL_A 0x1574 +#define NVB197_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_TEX_HEADER_POOL_B 0x1578 +#define NVB197_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_TEX_HEADER_POOL_C 0x157c +#define NVB197_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVB197_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVB197_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVB197_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVB197_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVB197_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVB197_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVB197_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVB197_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVB197_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB197_SET_SRGB_WRITE 0x15b8 +#define NVB197_SET_SRGB_WRITE_ENABLE 0:0 +#define NVB197_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_DEPTH_BIAS 0x15bc +#define NVB197_SET_DEPTH_BIAS_V 31:0 + +#define NVB197_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVB197_SET_RT_LAYER 0x15cc +#define NVB197_SET_RT_LAYER_V 15:0 +#define NVB197_SET_RT_LAYER_CONTROL 16:16 +#define NVB197_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVB197_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVB197_SET_ANTI_ALIAS 0x15d0 +#define NVB197_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVB197_SET_EDGE_FLAG 0x15e4 +#define NVB197_SET_EDGE_FLAG_V 0:0 +#define NVB197_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVB197_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVB197_DRAW_INLINE_INDEX 0x15e8 +#define NVB197_DRAW_INLINE_INDEX_V 31:0 + +#define NVB197_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVB197_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVB197_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVB197_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVB197_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVB197_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVB197_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVB197_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVB197_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVB197_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVB197_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVB197_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVB197_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVB197_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVB197_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVB197_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVB197_SET_POINT_SPRITE_SELECT 0x1604 +#define NVB197_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVB197_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVB197_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVB197_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVB197_SET_PROGRAM_REGION_A 0x1608 +#define NVB197_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVB197_SET_PROGRAM_REGION_B 0x160c +#define NVB197_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVB197_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVB197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVB197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVB197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVB197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVB197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVB197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVB197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVB197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVB197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVB197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVB197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVB197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVB197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVB197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVB197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVB197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVB197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVB197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVB197_END 0x1614 +#define NVB197_END_V 0:0 + +#define NVB197_BEGIN 0x1618 +#define NVB197_BEGIN_OP 15:0 +#define NVB197_BEGIN_OP_POINTS 0x00000000 +#define NVB197_BEGIN_OP_LINES 0x00000001 +#define NVB197_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVB197_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVB197_BEGIN_OP_TRIANGLES 0x00000004 +#define NVB197_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVB197_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVB197_BEGIN_OP_QUADS 0x00000007 +#define NVB197_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVB197_BEGIN_OP_POLYGON 0x00000009 +#define NVB197_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVB197_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVB197_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_BEGIN_OP_PATCH 0x0000000E +#define NVB197_BEGIN_PRIMITIVE_ID 24:24 +#define NVB197_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVB197_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVB197_BEGIN_INSTANCE_ID 27:26 +#define NVB197_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVB197_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVB197_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVB197_BEGIN_SPLIT_MODE 30:29 +#define NVB197_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVB197_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVB197_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVB197_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 + +#define NVB197_SET_VERTEX_ID_COPY 0x161c +#define NVB197_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVB197_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVB197_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVB197_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVB197_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVB197_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVB197_LOAD_PRIMITIVE_ID 0x1624 +#define NVB197_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVB197_SET_SHADER_BASED_CULL 0x162c +#define NVB197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVB197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVB197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVB197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_CLASS_VERSION 0x1638 +#define NVB197_SET_CLASS_VERSION_CURRENT 15:0 +#define NVB197_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB197_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVB197_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVB197_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVB197_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVB197_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVB197_SET_DA_OUTPUT 0x164c +#define NVB197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVB197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVB197_SET_ANTI_ALIASED_POINT 0x1658 +#define NVB197_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVB197_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_POINT_CENTER_MODE 0x165c +#define NVB197_SET_POINT_CENTER_MODE_V 31:0 +#define NVB197_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVB197_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVB197_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVB197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVB197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVB197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVB197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVB197_SET_LINE_STIPPLE 0x166c +#define NVB197_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVB197_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVB197_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVB197_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVB197_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVB197_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVB197_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVB197_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVB197_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVB197_SET_PROVOKING_VERTEX 0x1684 +#define NVB197_SET_PROVOKING_VERTEX_V 0:0 +#define NVB197_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVB197_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVB197_SET_TWO_SIDED_LIGHT 0x1688 +#define NVB197_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVB197_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_POLYGON_STIPPLE 0x168c +#define NVB197_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVB197_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_SHADER_CONTROL 0x1690 +#define NVB197_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVB197_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVB197_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVB197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVB197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVB197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVB197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVB197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVB197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVB197_CHECK_CLASS_VERSION 0x16a0 +#define NVB197_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVB197_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB197_SET_SPH_VERSION 0x16a4 +#define NVB197_SET_SPH_VERSION_CURRENT 15:0 +#define NVB197_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB197_CHECK_SPH_VERSION 0x16a8 +#define NVB197_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVB197_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVB197_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVB197_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVB197_SET_AAM_VERSION 0x1790 +#define NVB197_SET_AAM_VERSION_CURRENT 15:0 +#define NVB197_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB197_CHECK_AAM_VERSION 0x1794 +#define NVB197_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVB197_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB197_SET_ZT_LAYER 0x179c +#define NVB197_SET_ZT_LAYER_OFFSET 15:0 + +#define NVB197_SET_INDEX_BUFFER_A 0x17c8 +#define NVB197_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVB197_SET_INDEX_BUFFER_B 0x17cc +#define NVB197_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVB197_SET_INDEX_BUFFER_C 0x17d0 +#define NVB197_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVB197_SET_INDEX_BUFFER_D 0x17d4 +#define NVB197_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVB197_SET_INDEX_BUFFER_E 0x17d8 +#define NVB197_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVB197_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVB197_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVB197_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVB197_SET_INDEX_BUFFER_F 0x17dc +#define NVB197_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVB197_DRAW_INDEX_BUFFER 0x17e0 +#define NVB197_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVB197_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVB197_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVB197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVB197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVB197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVB197_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVB197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVB197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVB197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVB197_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVB197_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVB197_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVB197_OGL_SET_CULL 0x1918 +#define NVB197_OGL_SET_CULL_ENABLE 0:0 +#define NVB197_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVB197_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVB197_OGL_SET_FRONT_FACE 0x191c +#define NVB197_OGL_SET_FRONT_FACE_V 31:0 +#define NVB197_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVB197_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVB197_OGL_SET_CULL_FACE 0x1920 +#define NVB197_OGL_SET_CULL_FACE_V 31:0 +#define NVB197_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVB197_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVB197_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVB197_SET_VIEWPORT_PIXEL 0x1924 +#define NVB197_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVB197_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVB197_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVB197_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVB197_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVB197_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVB197_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVB197_SET_USER_CLIP_OP 0x1940 +#define NVB197_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVB197_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVB197_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVB197_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVB197_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVB197_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVB197_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVB197_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVB197_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVB197_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVB197_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVB197_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVB197_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVB197_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVB197_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVB197_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVB197_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVB197_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVB197_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVB197_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVB197_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVB197_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVB197_INVALIDATE_ZCULL 0x1958 +#define NVB197_INVALIDATE_ZCULL_V 31:0 +#define NVB197_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVB197_SET_ZCULL 0x1968 +#define NVB197_SET_ZCULL_Z_ENABLE 0:0 +#define NVB197_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVB197_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ZCULL_BOUNDS 0x196c +#define NVB197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVB197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVB197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVB197_ZCULL_SYNC 0x1978 +#define NVB197_ZCULL_SYNC_V 31:0 + +#define NVB197_SET_CLIP_ID_TEST 0x197c +#define NVB197_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVB197_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVB197_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVB197_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVB197_SET_CLIP_ID 0x1984 +#define NVB197_SET_CLIP_ID_V 31:0 + +#define NVB197_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVB197_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVB197_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVB197_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVB197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVB197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVB197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVB197_SET_LOGIC_OP 0x19c4 +#define NVB197_SET_LOGIC_OP_ENABLE 0:0 +#define NVB197_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVB197_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_LOGIC_OP_FUNC 0x19c8 +#define NVB197_SET_LOGIC_OP_FUNC_V 31:0 +#define NVB197_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVB197_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVB197_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVB197_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVB197_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVB197_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVB197_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVB197_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVB197_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVB197_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVB197_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVB197_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVB197_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVB197_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVB197_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVB197_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVB197_SET_Z_COMPRESSION 0x19cc +#define NVB197_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVB197_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVB197_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVB197_CLEAR_SURFACE 0x19d0 +#define NVB197_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVB197_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVB197_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVB197_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVB197_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVB197_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVB197_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVB197_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVB197_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVB197_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVB197_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVB197_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVB197_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVB197_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVB197_SET_CT_WRITE_R_ENABLE 0:0 +#define NVB197_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVB197_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVB197_SET_CT_WRITE_G_ENABLE 4:4 +#define NVB197_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVB197_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVB197_SET_CT_WRITE_B_ENABLE 8:8 +#define NVB197_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVB197_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVB197_SET_CT_WRITE_A_ENABLE 12:12 +#define NVB197_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVB197_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVB197_PIPE_NOP 0x1a2c +#define NVB197_PIPE_NOP_V 31:0 + +#define NVB197_SET_SPARE00 0x1a30 +#define NVB197_SET_SPARE00_V 31:0 + +#define NVB197_SET_SPARE01 0x1a34 +#define NVB197_SET_SPARE01_V 31:0 + +#define NVB197_SET_SPARE02 0x1a38 +#define NVB197_SET_SPARE02_V 31:0 + +#define NVB197_SET_SPARE03 0x1a3c +#define NVB197_SET_SPARE03_V 31:0 + +#define NVB197_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVB197_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVB197_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVB197_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB197_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVB197_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVB197_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVB197_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVB197_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVB197_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVB197_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVB197_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVB197_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVB197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVB197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVB197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVB197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVB197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVB197_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVB197_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVB197_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVB197_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVB197_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVB197_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVB197_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVB197_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVB197_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVB197_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVB197_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVB197_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVB197_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVB197_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVB197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVB197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVB197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVB197_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVB197_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVB197_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVB197_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVB197_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVB197_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVB197_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVB197_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVB197_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVB197_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVB197_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVB197_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVB197_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVB197_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVB197_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVB197_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVB197_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVB197_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVB197_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NVB197_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NVB197_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVB197_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVB197_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVB197_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NVB197_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVB197_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVB197_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NVB197_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVB197_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NVB197_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NVB197_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVB197_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVB197_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVB197_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVB197_SET_FALCON00 0x2300 +#define NVB197_SET_FALCON00_V 31:0 + +#define NVB197_SET_FALCON01 0x2304 +#define NVB197_SET_FALCON01_V 31:0 + +#define NVB197_SET_FALCON02 0x2308 +#define NVB197_SET_FALCON02_V 31:0 + +#define NVB197_SET_FALCON03 0x230c +#define NVB197_SET_FALCON03_V 31:0 + +#define NVB197_SET_FALCON04 0x2310 +#define NVB197_SET_FALCON04_V 31:0 + +#define NVB197_SET_FALCON05 0x2314 +#define NVB197_SET_FALCON05_V 31:0 + +#define NVB197_SET_FALCON06 0x2318 +#define NVB197_SET_FALCON06_V 31:0 + +#define NVB197_SET_FALCON07 0x231c +#define NVB197_SET_FALCON07_V 31:0 + +#define NVB197_SET_FALCON08 0x2320 +#define NVB197_SET_FALCON08_V 31:0 + +#define NVB197_SET_FALCON09 0x2324 +#define NVB197_SET_FALCON09_V 31:0 + +#define NVB197_SET_FALCON10 0x2328 +#define NVB197_SET_FALCON10_V 31:0 + +#define NVB197_SET_FALCON11 0x232c +#define NVB197_SET_FALCON11_V 31:0 + +#define NVB197_SET_FALCON12 0x2330 +#define NVB197_SET_FALCON12_V 31:0 + +#define NVB197_SET_FALCON13 0x2334 +#define NVB197_SET_FALCON13_V 31:0 + +#define NVB197_SET_FALCON14 0x2338 +#define NVB197_SET_FALCON14_V 31:0 + +#define NVB197_SET_FALCON15 0x233c +#define NVB197_SET_FALCON15_V 31:0 + +#define NVB197_SET_FALCON16 0x2340 +#define NVB197_SET_FALCON16_V 31:0 + +#define NVB197_SET_FALCON17 0x2344 +#define NVB197_SET_FALCON17_V 31:0 + +#define NVB197_SET_FALCON18 0x2348 +#define NVB197_SET_FALCON18_V 31:0 + +#define NVB197_SET_FALCON19 0x234c +#define NVB197_SET_FALCON19_V 31:0 + +#define NVB197_SET_FALCON20 0x2350 +#define NVB197_SET_FALCON20_V 31:0 + +#define NVB197_SET_FALCON21 0x2354 +#define NVB197_SET_FALCON21_V 31:0 + +#define NVB197_SET_FALCON22 0x2358 +#define NVB197_SET_FALCON22_V 31:0 + +#define NVB197_SET_FALCON23 0x235c +#define NVB197_SET_FALCON23_V 31:0 + +#define NVB197_SET_FALCON24 0x2360 +#define NVB197_SET_FALCON24_V 31:0 + +#define NVB197_SET_FALCON25 0x2364 +#define NVB197_SET_FALCON25_V 31:0 + +#define NVB197_SET_FALCON26 0x2368 +#define NVB197_SET_FALCON26_V 31:0 + +#define NVB197_SET_FALCON27 0x236c +#define NVB197_SET_FALCON27_V 31:0 + +#define NVB197_SET_FALCON28 0x2370 +#define NVB197_SET_FALCON28_V 31:0 + +#define NVB197_SET_FALCON29 0x2374 +#define NVB197_SET_FALCON29_V 31:0 + +#define NVB197_SET_FALCON30 0x2378 +#define NVB197_SET_FALCON30_V 31:0 + +#define NVB197_SET_FALCON31 0x237c +#define NVB197_SET_FALCON31_V 31:0 + +#define NVB197_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVB197_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVB197_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVB197_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVB197_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVB197_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVB197_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVB197_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVB197_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVB197_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVB197_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVB197_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVB197_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVB197_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVB197_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVB197_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVB197_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVB197_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVB197_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVB197_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVB197_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVB197_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVB197_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVB197_SET_COLOR_CLAMP 0x2600 +#define NVB197_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVB197_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVB197_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BINDLESS_TEXTURE 0x2608 +#define NVB197_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVB197_SET_TRAP_HANDLER 0x260c +#define NVB197_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVB197_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVB197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVB197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVB197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVB197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVB197_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVB197_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB197_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVB197_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB197_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVB197_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVB197_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVB197_CALL_MME_MACRO_V 31:0 + +#define NVB197_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVB197_CALL_MME_DATA_V 31:0 + +#endif /* _cl_maxwell_b_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clb1c0.h b/userspace/sdks/nv570/inc/class/clb1c0.h new file mode 100644 index 0000000..8d7aaac --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clb1c0.h @@ -0,0 +1,750 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_maxwell_compute_b_h_ +#define _cl_maxwell_compute_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl maxwell_compute_b */ + +#include "nvtypes.h" + +#define MAXWELL_COMPUTE_B 0xB1C0 + +#define NVB1C0_SET_OBJECT 0x0000 +#define NVB1C0_SET_OBJECT_CLASS_ID 15:0 +#define NVB1C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVB1C0_NO_OPERATION 0x0100 +#define NVB1C0_NO_OPERATION_V 31:0 + +#define NVB1C0_SET_NOTIFY_A 0x0104 +#define NVB1C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_SET_NOTIFY_B 0x0108 +#define NVB1C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_NOTIFY 0x010c +#define NVB1C0_NOTIFY_TYPE 31:0 +#define NVB1C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVB1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVB1C0_WAIT_FOR_IDLE 0x0110 +#define NVB1C0_WAIT_FOR_IDLE_V 31:0 + +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB1C0_SEND_GO_IDLE 0x013c +#define NVB1C0_SEND_GO_IDLE_V 31:0 + +#define NVB1C0_PM_TRIGGER 0x0140 +#define NVB1C0_PM_TRIGGER_V 31:0 + +#define NVB1C0_PM_TRIGGER_WFI 0x0144 +#define NVB1C0_PM_TRIGGER_WFI_V 31:0 + +#define NVB1C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVB1C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVB1C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVB1C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVB1C0_LINE_LENGTH_IN 0x0180 +#define NVB1C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVB1C0_LINE_COUNT 0x0184 +#define NVB1C0_LINE_COUNT_VALUE 31:0 + +#define NVB1C0_OFFSET_OUT_UPPER 0x0188 +#define NVB1C0_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVB1C0_OFFSET_OUT 0x018c +#define NVB1C0_OFFSET_OUT_VALUE 31:0 + +#define NVB1C0_PITCH_OUT 0x0190 +#define NVB1C0_PITCH_OUT_VALUE 31:0 + +#define NVB1C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVB1C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVB1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVB1C0_SET_DST_WIDTH 0x0198 +#define NVB1C0_SET_DST_WIDTH_V 31:0 + +#define NVB1C0_SET_DST_HEIGHT 0x019c +#define NVB1C0_SET_DST_HEIGHT_V 31:0 + +#define NVB1C0_SET_DST_DEPTH 0x01a0 +#define NVB1C0_SET_DST_DEPTH_V 31:0 + +#define NVB1C0_SET_DST_LAYER 0x01a4 +#define NVB1C0_SET_DST_LAYER_V 31:0 + +#define NVB1C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVB1C0_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVB1C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVB1C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVB1C0_LAUNCH_DMA 0x01b0 +#define NVB1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVB1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVB1C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVB1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVB1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVB1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVB1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVB1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVB1C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVB1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB1C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVB1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVB1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVB1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVB1C0_LOAD_INLINE_DATA 0x01b4 +#define NVB1C0_LOAD_INLINE_DATA_V 31:0 + +#define NVB1C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVB1C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVB1C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVB1C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB1C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVB1C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVB1C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVB1C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVB1C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVB1C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVB1C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVB1C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVB1C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVB1C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVB1C0_PERFMON_TRANSFER 0x0210 +#define NVB1C0_PERFMON_TRANSFER_V 31:0 + +#define NVB1C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVB1C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0218 +#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVB1C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVB1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVB1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVB1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVB1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVB1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVB1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVB1C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVB1C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVB1C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVB1C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVB1C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVB1C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVB1C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVB1C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVB1C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVB1C0_SET_CWD_CONTROL 0x0240 +#define NVB1C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVB1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVB1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVB1C0_SET_CWD_REF_COUNTER 0x0248 +#define NVB1C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVB1C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVB1C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVB1C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVB1C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVB1C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVB1C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVB1C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVB1C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVB1C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVB1C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVB1C0_SET_GWC_SCG_TYPE 0x026c +#define NVB1C0_SET_GWC_SCG_TYPE_SCG_TYPE 0:0 +#define NVB1C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0 0x00000000 +#define NVB1C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1 0x00000001 + +#define NVB1C0_SET_SCG_CONTROL 0x0270 +#define NVB1C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 + +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVB1C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVB1C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVB1C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB1C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVB1C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVB1C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB1C0_SET_QMD_VERSION 0x0288 +#define NVB1C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVB1C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB1C0_SET_WFI_CONFIG 0x028c +#define NVB1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI 0:0 +#define NVB1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE 0x00000000 +#define NVB1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE 0x00000001 + +#define NVB1C0_CHECK_QMD_VERSION 0x0290 +#define NVB1C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVB1C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB1C0_WAIT_FOR_IDLE_SCG_TYPE 0x0294 +#define NVB1C0_WAIT_FOR_IDLE_SCG_TYPE_V 31:0 + +#define NVB1C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVB1C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL 0x029c +#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE 0:0 +#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE 0x00000001 + +#define NVB1C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVB1C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVB1C0_SEND_PCAS_A 0x02b4 +#define NVB1C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVB1C0_SEND_PCAS_B 0x02b8 +#define NVB1C0_SEND_PCAS_B_FROM 23:0 +#define NVB1C0_SEND_PCAS_B_DELTA 31:24 + +#define NVB1C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVB1C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVB1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVB1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVB1C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVB1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVB1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVB1C0_SET_SPA_VERSION 0x0310 +#define NVB1C0_SET_SPA_VERSION_MINOR 7:0 +#define NVB1C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVB1C0_SET_FALCON00 0x0500 +#define NVB1C0_SET_FALCON00_V 31:0 + +#define NVB1C0_SET_FALCON01 0x0504 +#define NVB1C0_SET_FALCON01_V 31:0 + +#define NVB1C0_SET_FALCON02 0x0508 +#define NVB1C0_SET_FALCON02_V 31:0 + +#define NVB1C0_SET_FALCON03 0x050c +#define NVB1C0_SET_FALCON03_V 31:0 + +#define NVB1C0_SET_FALCON04 0x0510 +#define NVB1C0_SET_FALCON04_V 31:0 + +#define NVB1C0_SET_FALCON05 0x0514 +#define NVB1C0_SET_FALCON05_V 31:0 + +#define NVB1C0_SET_FALCON06 0x0518 +#define NVB1C0_SET_FALCON06_V 31:0 + +#define NVB1C0_SET_FALCON07 0x051c +#define NVB1C0_SET_FALCON07_V 31:0 + +#define NVB1C0_SET_FALCON08 0x0520 +#define NVB1C0_SET_FALCON08_V 31:0 + +#define NVB1C0_SET_FALCON09 0x0524 +#define NVB1C0_SET_FALCON09_V 31:0 + +#define NVB1C0_SET_FALCON10 0x0528 +#define NVB1C0_SET_FALCON10_V 31:0 + +#define NVB1C0_SET_FALCON11 0x052c +#define NVB1C0_SET_FALCON11_V 31:0 + +#define NVB1C0_SET_FALCON12 0x0530 +#define NVB1C0_SET_FALCON12_V 31:0 + +#define NVB1C0_SET_FALCON13 0x0534 +#define NVB1C0_SET_FALCON13_V 31:0 + +#define NVB1C0_SET_FALCON14 0x0538 +#define NVB1C0_SET_FALCON14_V 31:0 + +#define NVB1C0_SET_FALCON15 0x053c +#define NVB1C0_SET_FALCON15_V 31:0 + +#define NVB1C0_SET_FALCON16 0x0540 +#define NVB1C0_SET_FALCON16_V 31:0 + +#define NVB1C0_SET_FALCON17 0x0544 +#define NVB1C0_SET_FALCON17_V 31:0 + +#define NVB1C0_SET_FALCON18 0x0548 +#define NVB1C0_SET_FALCON18_V 31:0 + +#define NVB1C0_SET_FALCON19 0x054c +#define NVB1C0_SET_FALCON19_V 31:0 + +#define NVB1C0_SET_FALCON20 0x0550 +#define NVB1C0_SET_FALCON20_V 31:0 + +#define NVB1C0_SET_FALCON21 0x0554 +#define NVB1C0_SET_FALCON21_V 31:0 + +#define NVB1C0_SET_FALCON22 0x0558 +#define NVB1C0_SET_FALCON22_V 31:0 + +#define NVB1C0_SET_FALCON23 0x055c +#define NVB1C0_SET_FALCON23_V 31:0 + +#define NVB1C0_SET_FALCON24 0x0560 +#define NVB1C0_SET_FALCON24_V 31:0 + +#define NVB1C0_SET_FALCON25 0x0564 +#define NVB1C0_SET_FALCON25_V 31:0 + +#define NVB1C0_SET_FALCON26 0x0568 +#define NVB1C0_SET_FALCON26_V 31:0 + +#define NVB1C0_SET_FALCON27 0x056c +#define NVB1C0_SET_FALCON27_V 31:0 + +#define NVB1C0_SET_FALCON28 0x0570 +#define NVB1C0_SET_FALCON28_V 31:0 + +#define NVB1C0_SET_FALCON29 0x0574 +#define NVB1C0_SET_FALCON29_V 31:0 + +#define NVB1C0_SET_FALCON30 0x0578 +#define NVB1C0_SET_FALCON30_V 31:0 + +#define NVB1C0_SET_FALCON31 0x057c +#define NVB1C0_SET_FALCON31_V 31:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVB1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVB1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVB1C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVB1C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVB1C0_SET_SPARE_NOOP12 0x0f44 +#define NVB1C0_SET_SPARE_NOOP12_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP13 0x0f48 +#define NVB1C0_SET_SPARE_NOOP13_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP14 0x0f4c +#define NVB1C0_SET_SPARE_NOOP14_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP15 0x0f50 +#define NVB1C0_SET_SPARE_NOOP15_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP00 0x1040 +#define NVB1C0_SET_SPARE_NOOP00_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP01 0x1044 +#define NVB1C0_SET_SPARE_NOOP01_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP02 0x1048 +#define NVB1C0_SET_SPARE_NOOP02_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP03 0x104c +#define NVB1C0_SET_SPARE_NOOP03_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP04 0x1050 +#define NVB1C0_SET_SPARE_NOOP04_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP05 0x1054 +#define NVB1C0_SET_SPARE_NOOP05_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP06 0x1058 +#define NVB1C0_SET_SPARE_NOOP06_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP07 0x105c +#define NVB1C0_SET_SPARE_NOOP07_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP08 0x1060 +#define NVB1C0_SET_SPARE_NOOP08_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP09 0x1064 +#define NVB1C0_SET_SPARE_NOOP09_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP10 0x1068 +#define NVB1C0_SET_SPARE_NOOP10_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP11 0x106c +#define NVB1C0_SET_SPARE_NOOP11_V 31:0 + +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVB1C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVB1C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVB1C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVB1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVB1C0_SET_RENDER_ENABLE_A 0x1550 +#define NVB1C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_RENDER_ENABLE_B 0x1554 +#define NVB1C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_RENDER_ENABLE_C 0x1558 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB1C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVB1C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVB1C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVB1C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVB1C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVB1C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVB1C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVB1C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVB1C0_SET_PROGRAM_REGION_A 0x1608 +#define NVB1C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_SET_PROGRAM_REGION_B 0x160c +#define NVB1C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVB1C0_PIPE_NOP 0x1a2c +#define NVB1C0_PIPE_NOP_V 31:0 + +#define NVB1C0_SET_SPARE00 0x1a30 +#define NVB1C0_SET_SPARE00_V 31:0 + +#define NVB1C0_SET_SPARE01 0x1a34 +#define NVB1C0_SET_SPARE01_V 31:0 + +#define NVB1C0_SET_SPARE02 0x1a38 +#define NVB1C0_SET_SPARE02_V 31:0 + +#define NVB1C0_SET_SPARE03 0x1a3c +#define NVB1C0_SET_SPARE03_V 31:0 + +#define NVB1C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVB1C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVB1C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVB1C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB1C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVB1C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVB1C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVB1C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVB1C0_SET_TRAP_HANDLER 0x260c +#define NVB1C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVB1C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVB1C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB1C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVB1C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB1C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVB1C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_maxwell_compute_b_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clb1cc.h b/userspace/sdks/nv570/inc/class/clb1cc.h new file mode 100644 index 0000000..4e3e226 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clb1cc.h @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clb1cc.finn +// + +#include "clb0cc.h" + +#define MAXWELL_PROFILER_CONTEXT (0xb1ccU) /* finn: Evaluated from "NVB1CC_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* + * Creating the MAXWELL_PROFILER_CONTEXT object: + * - The profiler object is instantiated as a child of either a bc channel + * group or bc channel. + */ +#define NVB1CC_ALLOC_PARAMETERS_MESSAGE_ID (0xb1ccU) + +typedef struct NVB1CC_ALLOC_PARAMETERS { + /* + * Handle of a specific subdevice of a broadcast device. + */ + NvHandle hSubDevice; +} NVB1CC_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clb2cc.h b/userspace/sdks/nv570/inc/class/clb2cc.h new file mode 100644 index 0000000..f3ba26f --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clb2cc.h @@ -0,0 +1,60 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clb2cc.finn +// + +#include "clb0cc.h" + +#define MAXWELL_PROFILER_DEVICE (0xb2ccU) /* finn: Evaluated from "NVB2CC_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* + * Creating the MAXWELL_PROFILER_DEVICE object: + * - The profiler object is instantiated as a child of subdevice. + */ +#define NVB2CC_ALLOC_PARAMETERS_MESSAGE_ID (0xb2ccU) + +typedef struct NVB2CC_ALLOC_PARAMETERS { + /* + * This parameter specifies the handle of the client that owns the context + * specified by hContextTarget. This can set it to 0 where a context + * specific operation is not needed. For context level operations see: + * @ref NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY, @ref NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC, + * @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM. + */ + NvHandle hClientTarget; + + /* + * This parameter specifies the handle of the BC channel (or BC channel + * group) object instance to which context-specific operations are to be + * directed. If hClientTarget is set to 0 then this parameter is ignored. + */ + NvHandle hContextTarget; +} NVB2CC_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clb4b7.h b/userspace/sdks/nv570/inc/class/clb4b7.h new file mode 100644 index 0000000..e015151 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clb4b7.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clb4b7_h_ +#define clb4b7_h_ + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVB4B7_VIDEO_ENCODER (0x0000B4B7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clb4b7_h + diff --git a/userspace/sdks/nv570/inc/class/clb6b0.h b/userspace/sdks/nv570/inc/class/clb6b0.h new file mode 100644 index 0000000..d79dcb4 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clb6b0.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "nvtypes.h" + +#ifndef _clb6b0_h_ +#define _clb6b0_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVB6B0_VIDEO_DECODER (0x0000B6B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clb6b0_h diff --git a/userspace/sdks/nv570/inc/class/clb8b0.h b/userspace/sdks/nv570/inc/class/clb8b0.h new file mode 100644 index 0000000..b2d0e09 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clb8b0.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clb8b0_h__ +#define __gh100_clb8b0_h__ +#define NVB8B0_VIDEO_DECODER (0x0000B8B0) +#endif // __gh100_clb8b0_h__ diff --git a/userspace/sdks/nv570/inc/class/clb8d1.h b/userspace/sdks/nv570/inc/class/clb8d1.h new file mode 100644 index 0000000..e6c8e4c --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clb8d1.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clb8d1_h__ +#define __gh100_clb8d1_h__ +#define NVB8D1_VIDEO_NVJPG (0x0000B8D1) +#endif // __gh100_clb8d1_h__ diff --git a/userspace/sdks/nv570/inc/class/clb8fa.h b/userspace/sdks/nv570/inc/class/clb8fa.h new file mode 100644 index 0000000..19edb23 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clb8fa.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clb8fa_h_ +#define _clb8fa_h_ + +#define NVB8FA_VIDEO_OFA (0x0000B8FA) + +#endif /* _clb8fa_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc06f.h b/userspace/sdks/nv570/inc/class/clc06f.h new file mode 100644 index 0000000..d8b8607 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc06f.h @@ -0,0 +1,312 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc06f_h_ +#define _clc06f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class PASCAL_CHANNEL_GPFIFO */ +/* + * Documentation for PASCAL_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + * Note there is no .mfs file for this class. + */ +#define PASCAL_CHANNEL_GPFIFO_A (0x0000C06F) + +#define NVC06F_TYPEDEF PASCAL_CHANNELChannelGPFifoA + +/* dma flow control data structure */ +typedef volatile struct Nvc06fControl_struct { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} Nvc06fControl, PascalAControlGPFifo; + +/* fields and values */ +#define NVC06F_NUMBER_OF_SUBCHANNELS (8) +#define NVC06F_SET_OBJECT (0x00000000) +#define NVC06F_SET_OBJECT_NVCLASS 15:0 +#define NVC06F_SET_OBJECT_ENGINE 20:16 +#define NVC06F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVC06F_ILLEGAL (0x00000004) +#define NVC06F_ILLEGAL_HANDLE 31:0 +#define NVC06F_NOP (0x00000008) +#define NVC06F_NOP_HANDLE 31:0 +#define NVC06F_SEMAPHOREA (0x00000010) +#define NVC06F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVC06F_SEMAPHOREB (0x00000014) +#define NVC06F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVC06F_SEMAPHOREC (0x00000018) +#define NVC06F_SEMAPHOREC_PAYLOAD 31:0 +#define NVC06F_SEMAPHORED (0x0000001C) +#define NVC06F_SEMAPHORED_OPERATION 4:0 +#define NVC06F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVC06F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVC06F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVC06F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVC06F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 +#define NVC06F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVC06F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVC06F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVC06F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVC06F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVC06F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVC06F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVC06F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVC06F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVC06F_SEMAPHORED_REDUCTION 30:27 +#define NVC06F_SEMAPHORED_REDUCTION_MIN 0x00000000 +#define NVC06F_SEMAPHORED_REDUCTION_MAX 0x00000001 +#define NVC06F_SEMAPHORED_REDUCTION_XOR 0x00000002 +#define NVC06F_SEMAPHORED_REDUCTION_AND 0x00000003 +#define NVC06F_SEMAPHORED_REDUCTION_OR 0x00000004 +#define NVC06F_SEMAPHORED_REDUCTION_ADD 0x00000005 +#define NVC06F_SEMAPHORED_REDUCTION_INC 0x00000006 +#define NVC06F_SEMAPHORED_REDUCTION_DEC 0x00000007 +#define NVC06F_SEMAPHORED_FORMAT 31:31 +#define NVC06F_SEMAPHORED_FORMAT_SIGNED 0x00000000 +#define NVC06F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 +#define NVC06F_NON_STALL_INTERRUPT (0x00000020) +#define NVC06F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVC06F_FB_FLUSH (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR +#define NVC06F_FB_FLUSH_HANDLE 31:0 +// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for +// specifying the page address for a targeted TLB invalidate and the uTLB for +// a targeted REPLAY_CANCEL for UVM. +// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly +// rearranged fields. +#define NVC06F_MEM_OP_A (0x00000028) +#define NVC06F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC06F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC06F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11 +#define NVC06F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001 +#define NVC06F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000 +#define NVC06F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12 +#define NVC06F_MEM_OP_B (0x0000002c) +#define NVC06F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0 +#define NVC06F_MEM_OP_C (0x00000030) +#define NVC06F_MEM_OP_C_MEMBAR_TYPE 2:0 +#define NVC06F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000 +#define NVC06F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE +// MEM_OP_D MUST be preceded by MEM_OPs A-C. +#define NVC06F_MEM_OP_D (0x00000034) +#define NVC06F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE +#define NVC06F_MEM_OP_D_OPERATION 31:27 +#define NVC06F_MEM_OP_D_OPERATION_MEMBAR 0x00000005 +#define NVC06F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVC06F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a +#define NVC06F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NVC06F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +// CLEAN_LINES is an alias for Tegra/GPU IP usage +#define NVC06F_MEM_OP_D_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e +// This B alias is confusing but it was missed as part of the update. Left here +// for compatibility. +#define NVC06F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e +#define NVC06F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVC06F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVC06F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015 +#define NVC06F_SET_REFERENCE (0x00000050) +#define NVC06F_SET_REFERENCE_COUNT 31:0 +// Syncpoint methods are only available on Tegra parts. Attempting to use +// them on discrete GPUs will result in Host raising NV_PPBDMA_INTR_0_METHOD. +#define NVC06F_SYNCPOINTA (0x00000070) +#define NVC06F_SYNCPOINTA_PAYLOAD 31:0 +#define NVC06F_SYNCPOINTB (0x00000074) +#define NVC06F_SYNCPOINTB_OPERATION 0:0 +#define NVC06F_SYNCPOINTB_OPERATION_WAIT 0x00000000 +#define NVC06F_SYNCPOINTB_OPERATION_INCR 0x00000001 +#define NVC06F_SYNCPOINTB_WAIT_SWITCH 4:4 +#define NVC06F_SYNCPOINTB_WAIT_SWITCH_DIS 0x00000000 +#define NVC06F_SYNCPOINTB_WAIT_SWITCH_EN 0x00000001 +#define NVC06F_SYNCPOINTB_SYNCPT_INDEX 19:8 +#define NVC06F_WFI (0x00000078) +#define NVC06F_WFI_SCOPE 0:0 +#define NVC06F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000 +#define NVC06F_WFI_SCOPE_ALL 0x00000001 +#define NVC06F_CRC_CHECK (0x0000007c) +#define NVC06F_CRC_CHECK_VALUE 31:0 +#define NVC06F_YIELD (0x00000080) +#define NVC06F_YIELD_OP 1:0 +#define NVC06F_YIELD_OP_NOP 0x00000000 +#define NVC06F_YIELD_OP_PBDMA_TIMESLICE 0x00000001 +#define NVC06F_YIELD_OP_RUNLIST_TIMESLICE 0x00000002 +#define NVC06F_YIELD_OP_TSG 0x00000003 + + +/* GPFIFO entry format */ +#define NVC06F_GP_ENTRY__SIZE 8 +#define NVC06F_GP_ENTRY0_FETCH 0:0 +#define NVC06F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVC06F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVC06F_GP_ENTRY0_GET 31:2 +#define NVC06F_GP_ENTRY0_OPERAND 31:0 +#define NVC06F_GP_ENTRY1_GET_HI 7:0 +#define NVC06F_GP_ENTRY1_PRIV 8:8 +#define NVC06F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NVC06F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NVC06F_GP_ENTRY1_LEVEL 9:9 +#define NVC06F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVC06F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVC06F_GP_ENTRY1_LENGTH 30:10 +#define NVC06F_GP_ENTRY1_SYNC 31:31 +#define NVC06F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVC06F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVC06F_GP_ENTRY1_OPCODE 7:0 +#define NVC06F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVC06F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVC06F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVC06F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVC06F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVC06F_DMA_METHOD_ADDRESS 11:0 +#define NVC06F_DMA_SUBDEVICE_MASK 15:4 +#define NVC06F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVC06F_DMA_TERT_OP 17:16 +#define NVC06F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVC06F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVC06F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVC06F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVC06F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVC06F_DMA_METHOD_COUNT_OLD 28:18 +#define NVC06F_DMA_METHOD_COUNT 28:16 +#define NVC06F_DMA_IMMD_DATA 28:16 +#define NVC06F_DMA_SEC_OP 31:29 +#define NVC06F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVC06F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVC06F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVC06F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVC06F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVC06F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVC06F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVC06F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVC06F_DMA_INCR_ADDRESS 11:0 +#define NVC06F_DMA_INCR_SUBCHANNEL 15:13 +#define NVC06F_DMA_INCR_COUNT 28:16 +#define NVC06F_DMA_INCR_OPCODE 31:29 +#define NVC06F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVC06F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVC06F_DMA_NONINCR_ADDRESS 11:0 +#define NVC06F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVC06F_DMA_NONINCR_COUNT 28:16 +#define NVC06F_DMA_NONINCR_OPCODE 31:29 +#define NVC06F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVC06F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVC06F_DMA_ONEINCR_ADDRESS 11:0 +#define NVC06F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVC06F_DMA_ONEINCR_COUNT 28:16 +#define NVC06F_DMA_ONEINCR_OPCODE 31:29 +#define NVC06F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVC06F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVC06F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVC06F_DMA_IMMD_ADDRESS 11:0 +#define NVC06F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVC06F_DMA_IMMD_DATA 28:16 +#define NVC06F_DMA_IMMD_OPCODE 31:29 +#define NVC06F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVC06F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVC06F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC06F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVC06F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVC06F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC06F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVC06F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC06F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVC06F_DMA_ENDSEG_OPCODE 31:29 +#define NVC06F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVC06F_DMA_ADDRESS 12:2 +#define NVC06F_DMA_SUBCH 15:13 +#define NVC06F_DMA_OPCODE3 17:16 +#define NVC06F_DMA_OPCODE3_NONE (0x00000000) +#define NVC06F_DMA_COUNT 28:18 +#define NVC06F_DMA_OPCODE 31:29 +#define NVC06F_DMA_OPCODE_METHOD (0x00000000) +#define NVC06F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVC06F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc06f_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc06fsw.h b/userspace/sdks/nv570/inc/class/clc06fsw.h new file mode 100644 index 0000000..4e000c6 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc06fsw.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* This file is *not* auto-generated. */ + +#ifndef _clc06f_sw_h_ +#define _clc06f_sw_h_ + +#define NVC06F_NOTIFIERS_RC (0) +#define NVC06F_NOTIFIERS_REFCNT (1) +#define NVC06F_NOTIFIERS_NONSTALL (2) +#define NVC06F_NOTIFIERS_EVENTBUFFER (3) +#define NVC06F_NOTIFIERS_IDLECHANNEL (4) +#define NVC06F_NOTIFIERS_ENDCTX (5) +#define NVC06F_NOTIFIERS_SW (6) +#define NVC06F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVC06F_NOTIFIERS_REPLAYABLE_FAULT (8) +#define NVC06F_NOTIFIERS_MAXCOUNT (9) + +/* NvNotification[] fields and values */ +#define NVC06F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVC06F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _clc06f_sw_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc076.h b/userspace/sdks/nv570/inc/class/clc076.h new file mode 100644 index 0000000..284c57a --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc076.h @@ -0,0 +1,82 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc076_h_ +#define _clc076_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define GP100_UVM_SW (0x0000c076) + +#define NVC076_SET_OBJECT (0x00000000) +#define NVC076_NO_OPERATION (0x00000100) + +/* Method data fields to support gpu fault cancel. These are pushed in order by UVM */ + +#define NVC076_FAULT_CANCEL_A (0x00000104) +#define NVC076_FAULT_CANCEL_A_INST_APERTURE 1:0 +#define NVC076_FAULT_CANCEL_A_INST_APERTURE_VID_MEM 0x00000000 +#define NVC076_FAULT_CANCEL_A_INST_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC076_FAULT_CANCEL_A_INST_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 + +/* instance pointer is 4k aligned so those bits are reused to store the aperture */ +#define NVC076_FAULT_CANCEL_A_INST_LOW 31:12 + +#define NVC076_FAULT_CANCEL_B (0x00000108) +#define NVC076_FAULT_CANCEL_B_INST_HI 31:0 + +#define NVC076_FAULT_CANCEL_C (0x0000010c) +#define NVC076_FAULT_CANCEL_C_CLIENT_ID 5:0 +#define NVC076_FAULT_CANCEL_C_GPC_ID 10:6 +#define NVC076_FAULT_CANCEL_C_MODE 31:30 +#define NVC076_FAULT_CANCEL_C_MODE_TARGETED 0x00000000 +#define NVC076_FAULT_CANCEL_C_MODE_GLOBAL 0x00000001 + +/* Method data fields to support clearing faulted bit. These are pushed in order by UVM */ + +#define NVC076_CLEAR_FAULTED_A (0x00000110) + +#define NVC076_CLEAR_FAULTED_A_INST_APERTURE 1:0 +#define NVC076_CLEAR_FAULTED_A_INST_APERTURE_VID_MEM 0x00000000 +#define NVC076_CLEAR_FAULTED_A_INST_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC076_CLEAR_FAULTED_A_INST_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 + +#define NVC076_CLEAR_FAULTED_A_TYPE 2:2 +#define NVC076_CLEAR_FAULTED_A_TYPE_PBDMA_FAULTED 0x00000000 +#define NVC076_CLEAR_FAULTED_A_TYPE_ENG_FAULTED 0x00000001 + +/* instance pointer is 4k aligned */ +#define NVC076_CLEAR_FAULTED_A_INST_LOW 31:12 + +#define NVC076_CLEAR_FAULTED_B (0x00000114) +#define NVC076_CLEAR_FAULTED_B_INST_HI 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc076_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc097.h b/userspace/sdks/nv570/inc/class/clc097.h new file mode 100644 index 0000000..129056b --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc097.h @@ -0,0 +1,4191 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_pascal_a_h_ +#define _cl_pascal_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl pascal_a */ + +#include "nvtypes.h" + +#define PASCAL_A 0xC097 + +#define NVC097_SET_OBJECT 0x0000 +#define NVC097_SET_OBJECT_CLASS_ID 15:0 +#define NVC097_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC097_NO_OPERATION 0x0100 +#define NVC097_NO_OPERATION_V 31:0 + +#define NVC097_SET_NOTIFY_A 0x0104 +#define NVC097_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC097_SET_NOTIFY_B 0x0108 +#define NVC097_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC097_NOTIFY 0x010c +#define NVC097_NOTIFY_TYPE 31:0 +#define NVC097_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC097_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC097_WAIT_FOR_IDLE 0x0110 +#define NVC097_WAIT_FOR_IDLE_V 31:0 + +#define NVC097_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC097_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC097_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC097_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC097_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC097_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC097_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC097_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC097_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC097_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC097_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC097_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC097_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC097_SEND_GO_IDLE 0x013c +#define NVC097_SEND_GO_IDLE_V 31:0 + +#define NVC097_PM_TRIGGER 0x0140 +#define NVC097_PM_TRIGGER_V 31:0 + +#define NVC097_PM_TRIGGER_WFI 0x0144 +#define NVC097_PM_TRIGGER_WFI_V 31:0 + +#define NVC097_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC097_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC097_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC097_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC097_LINE_LENGTH_IN 0x0180 +#define NVC097_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC097_LINE_COUNT 0x0184 +#define NVC097_LINE_COUNT_VALUE 31:0 + +#define NVC097_OFFSET_OUT_UPPER 0x0188 +#define NVC097_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC097_OFFSET_OUT 0x018c +#define NVC097_OFFSET_OUT_VALUE 31:0 + +#define NVC097_PITCH_OUT 0x0190 +#define NVC097_PITCH_OUT_VALUE 31:0 + +#define NVC097_SET_DST_BLOCK_SIZE 0x0194 +#define NVC097_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC097_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC097_SET_DST_WIDTH 0x0198 +#define NVC097_SET_DST_WIDTH_V 31:0 + +#define NVC097_SET_DST_HEIGHT 0x019c +#define NVC097_SET_DST_HEIGHT_V 31:0 + +#define NVC097_SET_DST_DEPTH 0x01a0 +#define NVC097_SET_DST_DEPTH_V 31:0 + +#define NVC097_SET_DST_LAYER 0x01a4 +#define NVC097_SET_DST_LAYER_V 31:0 + +#define NVC097_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC097_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC097_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC097_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC097_LAUNCH_DMA 0x01b0 +#define NVC097_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC097_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC097_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC097_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC097_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC097_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC097_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC097_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC097_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC097_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC097_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC097_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC097_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC097_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC097_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC097_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC097_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC097_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC097_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC097_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC097_LOAD_INLINE_DATA 0x01b4 +#define NVC097_LOAD_INLINE_DATA_V 31:0 + +#define NVC097_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC097_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC097_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC097_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC097_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC097_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC097_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC097_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC097_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC097_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC097_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC097_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC097_RUN_DS_NOW 0x0200 +#define NVC097_RUN_DS_NOW_V 31:0 + +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC097_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC097_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC097_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC097_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC097_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC097_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_GS_DM_FIFO 0x0214 +#define NVC097_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC097_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC097_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC097_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC097_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC097_INVALIDATE_SHADER_CACHES 0x021c +#define NVC097_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC097_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC097_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC097_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC097_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC097_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC097_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC097_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC097_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC097_INCREMENT_SYNC_POINT 0x02c8 +#define NVC097_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC097_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC097_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC097_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC097_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC097_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC097_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NVC097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NVC097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 21:0 + +#define NVC097_DECOMPRESS_SURFACE 0x02e0 +#define NVC097_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC097_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC097_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC097_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC097_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC097_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC097_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC097_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC097_SET_ZCULL_SUBREGION 0x02e8 +#define NVC097_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC097_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC097_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC097_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC097_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC097_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC097_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC097_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC097_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC097_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC097_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC097_DRAW_ZERO_INDEX 0x0304 +#define NVC097_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC097_SET_L1_CONFIGURATION 0x0308 +#define NVC097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC097_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC097_SET_SPA_VERSION 0x0310 +#define NVC097_SET_SPA_VERSION_MINOR 7:0 +#define NVC097_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC097_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NVC097_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NVC097_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_SNAP_GRID_LINE 0x0318 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC097_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC097_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC097_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC097_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC097_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC097_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC097_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC097_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC097_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC097_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC097_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC097_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC097_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC097_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC097_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC097_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC097_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC097_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC097_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC097_RESERVED_TG07 0x033c +#define NVC097_RESERVED_TG07_V 0:0 + +#define NVC097_RESERVED_TG08 0x0340 +#define NVC097_RESERVED_TG08_V 0:0 + +#define NVC097_RESERVED_TG09 0x0344 +#define NVC097_RESERVED_TG09_V 0:0 + +#define NVC097_RESERVED_TG10 0x0348 +#define NVC097_RESERVED_TG10_V 0:0 + +#define NVC097_RESERVED_TG11 0x034c +#define NVC097_RESERVED_TG11_V 0:0 + +#define NVC097_RESERVED_TG12 0x0350 +#define NVC097_RESERVED_TG12_V 0:0 + +#define NVC097_RESERVED_TG13 0x0354 +#define NVC097_RESERVED_TG13_V 0:0 + +#define NVC097_RESERVED_TG14 0x0358 +#define NVC097_RESERVED_TG14_V 0:0 + +#define NVC097_RESERVED_TG15 0x035c +#define NVC097_RESERVED_TG15_V 0:0 + +#define NVC097_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC097_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC097_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC097_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC097_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC097_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC097_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC097_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC097_SET_RASTER_ENABLE 0x037c +#define NVC097_SET_RASTER_ENABLE_V 0:0 +#define NVC097_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC097_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC097_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC097_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC097_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC097_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC097_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC097_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC097_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC097_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC097_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC097_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC097_SET_RASTER_INPUT 0x0740 +#define NVC097_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC097_SET_STREAM_OUTPUT 0x0744 +#define NVC097_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC097_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_ALPHA_FRACTION 0x074c +#define NVC097_SET_ALPHA_FRACTION_V 7:0 + +#define NVC097_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC097_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC097_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC097_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC097_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC097_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC097_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC097_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC097_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC097_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC097_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC097_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC097_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC097_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC097_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC097_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC097_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC097_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC097_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC097_SET_ISBE_SAVE_RESTORE_PROGRAM 0x07ac +#define NVC097_SET_ISBE_SAVE_RESTORE_PROGRAM_OFFSET 31:0 + +#define NVC097_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC097_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC097_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC097_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC097_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC097_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC097_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC097_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC097_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC097_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC097_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC097_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC097_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC097_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC097_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC097_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC097_SET_ZCULL_STORAGE_B 0x07ec +#define NVC097_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC097_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC097_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC097_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC097_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC097_SET_ZT_READ_ONLY 0x07f8 +#define NVC097_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC097_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC097_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC097_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC097_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC097_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC097_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC097_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC097_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC097_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC097_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC097_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC097_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC097_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC097_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC097_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC097_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC097_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC097_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC097_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC097_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC097_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC097_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC097_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC097_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC097_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC097_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC097_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC097_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC097_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC097_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC097_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC097_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NVC097_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NVC097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVC097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVC097_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC097_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC097_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC097_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC097_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC097_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC097_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC097_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC097_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC097_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC097_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC097_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC097_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC097_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC097_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC097_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC097_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC097_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC097_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC097_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC097_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC097_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC097_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC097_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC097_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC097_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC097_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC097_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC097_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC097_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC097_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC097_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC097_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC097_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC097_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC097_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC097_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC097_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC097_SET_STATISTICS_COUNTER 0x0d68 +#define NVC097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC097_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC097_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC097_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC097_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC097_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC097_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC097_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC097_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC097_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC097_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC097_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC097_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC097_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC097_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC097_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC097_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC097_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC097_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC097_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC097_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC097_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC097_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC097_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC097_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC097_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC097_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC097_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC097_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC097_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC097_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC097_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC097_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC097_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC097_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC097_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC097_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC097_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC097_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC097_SET_POLY_SMOOTH 0x0db4 +#define NVC097_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC097_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_ZT_MARK 0x0db8 +#define NVC097_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NVC097_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVC097_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVC097_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC097_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC097_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC097_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC097_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC097_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC097_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC097_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC097_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_PATCH 0x0dcc +#define NVC097_SET_PATCH_SIZE 7:0 + +#define NVC097_SET_ITERATED_BLEND 0x0dd0 +#define NVC097_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC097_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC097_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC097_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC097_SET_ZCULL_CRITERION 0x0dd8 +#define NVC097_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC097_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC097_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC097_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC097_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC097_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC097_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC097_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC097_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC097_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC097_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC097_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC097_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC097_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC097_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC097_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC097_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC097_SET_SCISSOR_ENABLE_V 0:0 +#define NVC097_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC097_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC097_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC097_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC097_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC097_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC097_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0f10 +#define NVC097_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVC097_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVC097_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVC097_SET_VPC_PERF_KNOB 0x0f14 +#define NVC097_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC097_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC097_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC097_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC097_PM_LOCAL_TRIGGER 0x0f18 +#define NVC097_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC097_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC097_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC097_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC097_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC097_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC097_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC097_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC097_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC097_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC097_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC097_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC097_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC097_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC097_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC097_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC097_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC097_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC097_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC097_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC097_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC097_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC097_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC097_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC097_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC097_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC097_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC097_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC097_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC097_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC097_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC097_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC097_SET_SAMPLE_MASK 0x0fa4 +#define NVC097_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC097_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC097_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC097_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC097_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC097_SET_CT_MRT_ENABLE 0x0fac +#define NVC097_SET_CT_MRT_ENABLE_V 0:0 +#define NVC097_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC097_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC097_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC097_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC097_SET_TIR 0x0fb4 +#define NVC097_SET_TIR_MODE 1:0 +#define NVC097_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC097_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC097_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC097_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC097_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC097_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC097_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC097_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC097_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC097_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC097_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC097_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC097_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC097_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC097_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC097_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC097_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC097_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC097_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC097_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_TIR_MODULATION 0x0fd4 +#define NVC097_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC097_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC097_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC097_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC097_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC097_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC097_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC097_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC097_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC097_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC097_SET_ZT_A 0x0fe0 +#define NVC097_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_ZT_B 0x0fe4 +#define NVC097_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_ZT_FORMAT 0x0fe8 +#define NVC097_SET_ZT_FORMAT_V 4:0 +#define NVC097_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC097_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC097_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC097_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC097_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC097_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC097_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC097_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC097_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC097_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC097_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC097_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC097_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC097_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC097_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC097_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC097_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC097_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC097_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC097_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC097_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC097_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC097_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC097_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC097_SET_TILED_CACHE_BUNDLE_CONTROL 0x0ffc +#define NVC097_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT 0:0 +#define NVC097_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_FALSE 0x00000000 +#define NVC097_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_TRUE 0x00000001 + +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC097_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC097_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC097_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC097_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC097_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC097_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC097_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC097_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC097_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC097_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC097_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC097_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC097_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD02 0x102c +#define NVC097_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC097_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC097_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC097_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC097_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC097_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC097_SET_SPARE_NOOP01 0x1044 +#define NVC097_SET_SPARE_NOOP01_V 31:0 + +#define NVC097_SET_SPARE_NOOP02 0x1048 +#define NVC097_SET_SPARE_NOOP02_V 31:0 + +#define NVC097_SET_SPARE_NOOP03 0x104c +#define NVC097_SET_SPARE_NOOP03_V 31:0 + +#define NVC097_SET_SPARE_NOOP04 0x1050 +#define NVC097_SET_SPARE_NOOP04_V 31:0 + +#define NVC097_SET_SPARE_NOOP05 0x1054 +#define NVC097_SET_SPARE_NOOP05_V 31:0 + +#define NVC097_SET_SPARE_NOOP06 0x1058 +#define NVC097_SET_SPARE_NOOP06_V 31:0 + +#define NVC097_SET_SPARE_NOOP07 0x105c +#define NVC097_SET_SPARE_NOOP07_V 31:0 + +#define NVC097_SET_SPARE_NOOP08 0x1060 +#define NVC097_SET_SPARE_NOOP08_V 31:0 + +#define NVC097_SET_SPARE_NOOP09 0x1064 +#define NVC097_SET_SPARE_NOOP09_V 31:0 + +#define NVC097_SET_SPARE_NOOP10 0x1068 +#define NVC097_SET_SPARE_NOOP10_V 31:0 + +#define NVC097_SET_SPARE_NOOP11 0x106c +#define NVC097_SET_SPARE_NOOP11_V 31:0 + +#define NVC097_SET_SPARE_NOOP12 0x1070 +#define NVC097_SET_SPARE_NOOP12_V 31:0 + +#define NVC097_SET_SPARE_NOOP13 0x1074 +#define NVC097_SET_SPARE_NOOP13_V 31:0 + +#define NVC097_SET_SPARE_NOOP14 0x1078 +#define NVC097_SET_SPARE_NOOP14_V 31:0 + +#define NVC097_SET_SPARE_NOOP15 0x107c +#define NVC097_SET_SPARE_NOOP15_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC097_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC097_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC097_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC097_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC097_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC097_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC097_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC097_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC097_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC097_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC097_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC097_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC097_UNBIND_ALL 0x10f4 +#define NVC097_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC097_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC097_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC097_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC097_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC097_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC097_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC097_NO_OPERATION_DATA_HI 0x110c +#define NVC097_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC097_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC097_PM_TRIGGER_END 0x1114 +#define NVC097_PM_TRIGGER_END_V 31:0 + +#define NVC097_SET_VERTEX_ID_BASE 0x1118 +#define NVC097_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC097_SET_STENCIL_COMPRESSION 0x111c +#define NVC097_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC097_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC097_SET_TIR_CONTROL 0x1130 +#define NVC097_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC097_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC097_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC097_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC097_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC097_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC097_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC097_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC097_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 + +#define NVC097_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC097_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC097_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC097_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC097_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC097_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC097_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC097_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC097_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC097_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC097_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC097_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC097_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC097_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC097_FLUSH_PENDING_WRITES 0x1144 +#define NVC097_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC097_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC097_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC097_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC097_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC097_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC097_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC097_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC097_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC097_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC097_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC097_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC097_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC097_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC097_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC097_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC097_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC097_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC097_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC097_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC097_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC097_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC097_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_SCREEN_STATE_MASK 0x1204 +#define NVC097_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC097_SET_ZT_SPARSE 0x1208 +#define NVC097_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC097_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC097_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC097_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC097_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC097_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_SET_CT_SELECT 0x121c +#define NVC097_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC097_SET_CT_SELECT_TARGET0 6:4 +#define NVC097_SET_CT_SELECT_TARGET1 9:7 +#define NVC097_SET_CT_SELECT_TARGET2 12:10 +#define NVC097_SET_CT_SELECT_TARGET3 15:13 +#define NVC097_SET_CT_SELECT_TARGET4 18:16 +#define NVC097_SET_CT_SELECT_TARGET5 21:19 +#define NVC097_SET_CT_SELECT_TARGET6 24:22 +#define NVC097_SET_CT_SELECT_TARGET7 27:25 + +#define NVC097_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC097_SET_ZT_SIZE_A 0x1228 +#define NVC097_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC097_SET_ZT_SIZE_B 0x122c +#define NVC097_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC097_SET_ZT_SIZE_C 0x1230 +#define NVC097_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC097_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC097_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC097_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC097_SET_SAMPLER_BINDING 0x1234 +#define NVC097_SET_SAMPLER_BINDING_V 0:0 +#define NVC097_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC097_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC097_DRAW_AUTO 0x123c +#define NVC097_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC097_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC097_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC097_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC097_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC097_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC097_SET_BACK_END_COPY_A 0x1264 +#define NVC097_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC097_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC097_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC097_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC097_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BACK_END_COPY_B 0x1268 +#define NVC097_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC097_SET_BACK_END_COPY_C 0x126c +#define NVC097_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC097_SET_BACK_END_COPY_D 0x1270 +#define NVC097_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC097_SET_BACK_END_COPY_E 0x1274 +#define NVC097_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC097_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC097_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 21:0 + +#define NVC097_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC097_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC097_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC097_CLEAR_ZCULL_REGION 0x12c8 +#define NVC097_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC097_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC097_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC097_SET_DEPTH_TEST 0x12cc +#define NVC097_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC097_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC097_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_FILL_MODE 0x12d0 +#define NVC097_SET_FILL_MODE_V 31:0 +#define NVC097_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC097_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC097_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC097_SET_SHADE_MODE 0x12d4 +#define NVC097_SET_SHADE_MODE_V 31:0 +#define NVC097_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC097_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC097_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC097_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC097_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC097_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC097_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_DEPTH_WRITE 0x12e8 +#define NVC097_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC097_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_ALPHA_TEST 0x12ec +#define NVC097_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC097_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC097_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC097_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC097_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC097_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC097_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC097_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC097_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC097_D3D_SET_CULL_MODE 0x1308 +#define NVC097_D3D_SET_CULL_MODE_V 31:0 +#define NVC097_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC097_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC097_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC097_SET_DEPTH_FUNC 0x130c +#define NVC097_SET_DEPTH_FUNC_V 31:0 +#define NVC097_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC097_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC097_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC097_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC097_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC097_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC097_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC097_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC097_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC097_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC097_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC097_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC097_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC097_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC097_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC097_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC097_SET_ALPHA_REF 0x1310 +#define NVC097_SET_ALPHA_REF_V 31:0 + +#define NVC097_SET_ALPHA_FUNC 0x1314 +#define NVC097_SET_ALPHA_FUNC_V 31:0 +#define NVC097_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC097_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC097_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC097_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC097_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC097_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC097_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC097_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC097_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC097_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC097_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC097_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC097_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC097_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC097_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC097_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC097_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC097_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC097_SET_BLEND_CONST_RED 0x131c +#define NVC097_SET_BLEND_CONST_RED_V 31:0 + +#define NVC097_SET_BLEND_CONST_GREEN 0x1320 +#define NVC097_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC097_SET_BLEND_CONST_BLUE 0x1324 +#define NVC097_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC097_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC097_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC097_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC097_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC097_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC097_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC097_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC097_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BLEND_COLOR_OP 0x1340 +#define NVC097_SET_BLEND_COLOR_OP_V 31:0 +#define NVC097_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC097_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC097_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC097_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC097_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC097_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC097_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC097_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC097_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC097_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_BLEND_ALPHA_OP 0x134c +#define NVC097_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC097_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC097_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC097_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC097_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC097_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC097_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC097_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC097_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC097_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC097_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC097_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC097_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BLEND(i) (0x1360+(i)*4) +#define NVC097_SET_BLEND_ENABLE 0:0 +#define NVC097_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_STENCIL_TEST 0x1380 +#define NVC097_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC097_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_STENCIL_OP_FAIL 0x1384 +#define NVC097_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC097_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC097_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC097_SET_STENCIL_OP_ZPASS 0x138c +#define NVC097_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC097_SET_STENCIL_FUNC 0x1390 +#define NVC097_SET_STENCIL_FUNC_V 31:0 +#define NVC097_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC097_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC097_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC097_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC097_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC097_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC097_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC097_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC097_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC097_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC097_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC097_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC097_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC097_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC097_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC097_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC097_SET_STENCIL_FUNC_REF 0x1394 +#define NVC097_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC097_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC097_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC097_SET_STENCIL_MASK 0x139c +#define NVC097_SET_STENCIL_MASK_V 7:0 + +#define NVC097_SET_DRAW_AUTO_START 0x13a4 +#define NVC097_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC097_SET_PS_SATURATE 0x13a8 +#define NVC097_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC097_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC097_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC097_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC097_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC097_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC097_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC097_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC097_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC097_SET_WINDOW_ORIGIN 0x13ac +#define NVC097_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC097_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC097_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC097_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC097_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC097_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC097_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC097_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC097_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC097_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC097_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_ALPHA_HYSTERESIS 0x1420 +#define NVC097_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NVC097_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC097_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC097_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC097_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC097_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC097_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC097_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC097_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC097_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC097_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC097_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC097_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC097_STORE_ZCULL 0x1464 +#define NVC097_STORE_ZCULL_V 0:0 + +#define NVC097_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC097_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC097_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC097_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC097_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC097_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC097_LOAD_ZCULL 0x1500 +#define NVC097_LOAD_ZCULL_V 0:0 + +#define NVC097_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC097_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC097_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC097_SET_USER_CLIP_ENABLE 0x1510 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC097_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC097_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC097_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_POINT_SIZE 0x1518 +#define NVC097_SET_POINT_SIZE_V 31:0 + +#define NVC097_SET_ZCULL_STATS 0x151c +#define NVC097_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC097_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_POINT_SPRITE 0x1520 +#define NVC097_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC097_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC097_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC097_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC097_CLEAR_REPORT_VALUE 0x1530 +#define NVC097_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC097_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC097_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC097_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC097_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 + +#define NVC097_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC097_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC097_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_ZT_SELECT 0x1538 +#define NVC097_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC097_SET_RENDER_ENABLE_A 0x1550 +#define NVC097_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_RENDER_ENABLE_B 0x1554 +#define NVC097_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_RENDER_ENABLE_C 0x1558 +#define NVC097_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC097_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC097_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC097_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC097_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC097_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC097_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC097_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC097_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC097_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC097_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC097_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC097_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC097_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC097_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_TEX_HEADER_POOL_C 0x157c +#define NVC097_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC097_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC097_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC097_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC097_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC097_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC097_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC097_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC097_SET_SRGB_WRITE 0x15b8 +#define NVC097_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC097_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_DEPTH_BIAS 0x15bc +#define NVC097_SET_DEPTH_BIAS_V 31:0 + +#define NVC097_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC097_SET_RT_LAYER 0x15cc +#define NVC097_SET_RT_LAYER_V 15:0 +#define NVC097_SET_RT_LAYER_CONTROL 16:16 +#define NVC097_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC097_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC097_SET_ANTI_ALIAS 0x15d0 +#define NVC097_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC097_SET_EDGE_FLAG 0x15e4 +#define NVC097_SET_EDGE_FLAG_V 0:0 +#define NVC097_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC097_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC097_DRAW_INLINE_INDEX 0x15e8 +#define NVC097_DRAW_INLINE_INDEX_V 31:0 + +#define NVC097_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC097_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC097_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC097_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC097_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC097_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC097_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC097_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC097_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC097_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC097_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC097_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC097_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC097_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC097_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC097_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC097_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC097_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC097_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC097_SET_PROGRAM_REGION_A 0x1608 +#define NVC097_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVC097_SET_PROGRAM_REGION_B 0x160c +#define NVC097_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVC097_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC097_END 0x1614 +#define NVC097_END_V 0:0 + +#define NVC097_BEGIN 0x1618 +#define NVC097_BEGIN_OP 15:0 +#define NVC097_BEGIN_OP_POINTS 0x00000000 +#define NVC097_BEGIN_OP_LINES 0x00000001 +#define NVC097_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC097_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC097_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC097_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC097_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC097_BEGIN_OP_QUADS 0x00000007 +#define NVC097_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC097_BEGIN_OP_POLYGON 0x00000009 +#define NVC097_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC097_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC097_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_BEGIN_OP_PATCH 0x0000000E +#define NVC097_BEGIN_PRIMITIVE_ID 24:24 +#define NVC097_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC097_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC097_BEGIN_INSTANCE_ID 27:26 +#define NVC097_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC097_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC097_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC097_BEGIN_SPLIT_MODE 30:29 +#define NVC097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC097_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC097_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 + +#define NVC097_SET_VERTEX_ID_COPY 0x161c +#define NVC097_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC097_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC097_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC097_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC097_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC097_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC097_LOAD_PRIMITIVE_ID 0x1624 +#define NVC097_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC097_SET_SHADER_BASED_CULL 0x162c +#define NVC097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_CLASS_VERSION 0x1638 +#define NVC097_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC097_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC097_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC097_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC097_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC097_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC097_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC097_SET_DA_OUTPUT 0x164c +#define NVC097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC097_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC097_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC097_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_POINT_CENTER_MODE 0x165c +#define NVC097_SET_POINT_CENTER_MODE_V 31:0 +#define NVC097_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC097_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC097_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC097_SET_LINE_STIPPLE 0x166c +#define NVC097_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC097_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC097_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC097_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC097_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC097_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC097_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC097_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC097_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC097_SET_PROVOKING_VERTEX 0x1684 +#define NVC097_SET_PROVOKING_VERTEX_V 0:0 +#define NVC097_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC097_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC097_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC097_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC097_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_POLYGON_STIPPLE 0x168c +#define NVC097_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC097_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_SHADER_CONTROL 0x1690 +#define NVC097_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC097_CHECK_CLASS_VERSION 0x16a0 +#define NVC097_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC097_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC097_SET_SPH_VERSION 0x16a4 +#define NVC097_SET_SPH_VERSION_CURRENT 15:0 +#define NVC097_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC097_CHECK_SPH_VERSION 0x16a8 +#define NVC097_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC097_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC097_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC097_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC097_SET_AAM_VERSION 0x1790 +#define NVC097_SET_AAM_VERSION_CURRENT 15:0 +#define NVC097_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC097_CHECK_AAM_VERSION 0x1794 +#define NVC097_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC097_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC097_SET_ZT_LAYER 0x179c +#define NVC097_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC097_SET_INDEX_BUFFER_A 0x17c8 +#define NVC097_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC097_SET_INDEX_BUFFER_B 0x17cc +#define NVC097_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC097_SET_INDEX_BUFFER_C 0x17d0 +#define NVC097_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC097_SET_INDEX_BUFFER_D 0x17d4 +#define NVC097_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC097_SET_INDEX_BUFFER_E 0x17d8 +#define NVC097_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC097_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC097_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC097_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC097_SET_INDEX_BUFFER_F 0x17dc +#define NVC097_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC097_DRAW_INDEX_BUFFER 0x17e0 +#define NVC097_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC097_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC097_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC097_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC097_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC097_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC097_OGL_SET_CULL 0x1918 +#define NVC097_OGL_SET_CULL_ENABLE 0:0 +#define NVC097_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC097_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC097_OGL_SET_FRONT_FACE 0x191c +#define NVC097_OGL_SET_FRONT_FACE_V 31:0 +#define NVC097_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC097_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC097_OGL_SET_CULL_FACE 0x1920 +#define NVC097_OGL_SET_CULL_FACE_V 31:0 +#define NVC097_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC097_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC097_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC097_SET_VIEWPORT_PIXEL 0x1924 +#define NVC097_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC097_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC097_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC097_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC097_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC097_SET_USER_CLIP_OP 0x1940 +#define NVC097_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC097_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC097_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC097_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC097_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC097_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC097_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC097_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC097_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC097_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC097_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC097_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC097_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC097_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC097_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC097_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC097_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC097_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC097_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC097_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC097_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC097_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC097_INVALIDATE_ZCULL 0x1958 +#define NVC097_INVALIDATE_ZCULL_V 31:0 +#define NVC097_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC097_SET_ZCULL 0x1968 +#define NVC097_SET_ZCULL_Z_ENABLE 0:0 +#define NVC097_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC097_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_ZCULL_BOUNDS 0x196c +#define NVC097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC097_ZCULL_SYNC 0x1978 +#define NVC097_ZCULL_SYNC_V 31:0 + +#define NVC097_SET_CLIP_ID_TEST 0x197c +#define NVC097_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC097_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC097_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC097_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC097_SET_CLIP_ID 0x1984 +#define NVC097_SET_CLIP_ID_V 31:0 + +#define NVC097_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC097_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC097_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC097_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC097_SET_LOGIC_OP 0x19c4 +#define NVC097_SET_LOGIC_OP_ENABLE 0:0 +#define NVC097_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC097_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC097_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC097_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC097_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC097_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC097_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC097_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC097_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC097_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC097_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC097_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC097_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC097_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC097_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC097_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC097_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC097_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC097_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC097_SET_Z_COMPRESSION 0x19cc +#define NVC097_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC097_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC097_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC097_CLEAR_SURFACE 0x19d0 +#define NVC097_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC097_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC097_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC097_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC097_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC097_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC097_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC097_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC097_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC097_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC097_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC097_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC097_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC097_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC097_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC097_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC097_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC097_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC097_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC097_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC097_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC097_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC097_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC097_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC097_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC097_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC097_PIPE_NOP 0x1a2c +#define NVC097_PIPE_NOP_V 31:0 + +#define NVC097_SET_SPARE00 0x1a30 +#define NVC097_SET_SPARE00_V 31:0 + +#define NVC097_SET_SPARE01 0x1a34 +#define NVC097_SET_SPARE01_V 31:0 + +#define NVC097_SET_SPARE02 0x1a38 +#define NVC097_SET_SPARE02_V 31:0 + +#define NVC097_SET_SPARE03 0x1a3c +#define NVC097_SET_SPARE03_V 31:0 + +#define NVC097_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC097_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC097_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC097_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC097_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC097_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC097_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC097_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC097_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC097_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC097_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC097_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC097_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC097_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC097_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC097_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC097_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC097_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC097_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC097_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC097_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC097_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC097_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVC097_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVC097_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVC097_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVC097_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVC097_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVC097_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVC097_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVC097_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC097_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC097_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC097_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC097_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC097_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC097_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC097_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC097_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC097_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC097_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC097_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NVC097_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NVC097_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC097_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC097_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC097_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NVC097_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC097_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC097_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NVC097_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVC097_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NVC097_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NVC097_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVC097_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVC097_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC097_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC097_SET_FALCON00 0x2300 +#define NVC097_SET_FALCON00_V 31:0 + +#define NVC097_SET_FALCON01 0x2304 +#define NVC097_SET_FALCON01_V 31:0 + +#define NVC097_SET_FALCON02 0x2308 +#define NVC097_SET_FALCON02_V 31:0 + +#define NVC097_SET_FALCON03 0x230c +#define NVC097_SET_FALCON03_V 31:0 + +#define NVC097_SET_FALCON04 0x2310 +#define NVC097_SET_FALCON04_V 31:0 + +#define NVC097_SET_FALCON05 0x2314 +#define NVC097_SET_FALCON05_V 31:0 + +#define NVC097_SET_FALCON06 0x2318 +#define NVC097_SET_FALCON06_V 31:0 + +#define NVC097_SET_FALCON07 0x231c +#define NVC097_SET_FALCON07_V 31:0 + +#define NVC097_SET_FALCON08 0x2320 +#define NVC097_SET_FALCON08_V 31:0 + +#define NVC097_SET_FALCON09 0x2324 +#define NVC097_SET_FALCON09_V 31:0 + +#define NVC097_SET_FALCON10 0x2328 +#define NVC097_SET_FALCON10_V 31:0 + +#define NVC097_SET_FALCON11 0x232c +#define NVC097_SET_FALCON11_V 31:0 + +#define NVC097_SET_FALCON12 0x2330 +#define NVC097_SET_FALCON12_V 31:0 + +#define NVC097_SET_FALCON13 0x2334 +#define NVC097_SET_FALCON13_V 31:0 + +#define NVC097_SET_FALCON14 0x2338 +#define NVC097_SET_FALCON14_V 31:0 + +#define NVC097_SET_FALCON15 0x233c +#define NVC097_SET_FALCON15_V 31:0 + +#define NVC097_SET_FALCON16 0x2340 +#define NVC097_SET_FALCON16_V 31:0 + +#define NVC097_SET_FALCON17 0x2344 +#define NVC097_SET_FALCON17_V 31:0 + +#define NVC097_SET_FALCON18 0x2348 +#define NVC097_SET_FALCON18_V 31:0 + +#define NVC097_SET_FALCON19 0x234c +#define NVC097_SET_FALCON19_V 31:0 + +#define NVC097_SET_FALCON20 0x2350 +#define NVC097_SET_FALCON20_V 31:0 + +#define NVC097_SET_FALCON21 0x2354 +#define NVC097_SET_FALCON21_V 31:0 + +#define NVC097_SET_FALCON22 0x2358 +#define NVC097_SET_FALCON22_V 31:0 + +#define NVC097_SET_FALCON23 0x235c +#define NVC097_SET_FALCON23_V 31:0 + +#define NVC097_SET_FALCON24 0x2360 +#define NVC097_SET_FALCON24_V 31:0 + +#define NVC097_SET_FALCON25 0x2364 +#define NVC097_SET_FALCON25_V 31:0 + +#define NVC097_SET_FALCON26 0x2368 +#define NVC097_SET_FALCON26_V 31:0 + +#define NVC097_SET_FALCON27 0x236c +#define NVC097_SET_FALCON27_V 31:0 + +#define NVC097_SET_FALCON28 0x2370 +#define NVC097_SET_FALCON28_V 31:0 + +#define NVC097_SET_FALCON29 0x2374 +#define NVC097_SET_FALCON29_V 31:0 + +#define NVC097_SET_FALCON30 0x2378 +#define NVC097_SET_FALCON30_V 31:0 + +#define NVC097_SET_FALCON31 0x237c +#define NVC097_SET_FALCON31_V 31:0 + +#define NVC097_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC097_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC097_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC097_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC097_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC097_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC097_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC097_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC097_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC097_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC097_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC097_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC097_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC097_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC097_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC097_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC097_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC097_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC097_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC097_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC097_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC097_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC097_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC097_SET_COLOR_CLAMP 0x2600 +#define NVC097_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC097_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC097_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BINDLESS_TEXTURE 0x2608 +#define NVC097_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVC097_SET_TRAP_HANDLER 0x260c +#define NVC097_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVC097_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC097_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC097_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC097_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC097_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC097_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC097_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC097_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC097_CALL_MME_MACRO_V 31:0 + +#define NVC097_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC097_CALL_MME_DATA_V 31:0 + +#endif /* _cl_pascal_a_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc0b5.h b/userspace/sdks/nv570/inc/class/clc0b5.h new file mode 100644 index 0000000..d1fa85a --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc0b5.h @@ -0,0 +1,261 @@ +/******************************************************************************* + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clc0b5_h_ +#define _clc0b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define PASCAL_DMA_COPY_A (0x0000C0B5) + +#define NVC0B5_NOP (0x00000100) +#define NVC0B5_NOP_PARAMETER 31:0 +#define NVC0B5_PM_TRIGGER (0x00000140) +#define NVC0B5_PM_TRIGGER_V 31:0 +#define NVC0B5_SET_SEMAPHORE_A (0x00000240) +#define NVC0B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC0B5_SET_SEMAPHORE_B (0x00000244) +#define NVC0B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC0B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC0B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC0B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC0B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC0B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC0B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC0B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC0B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC0B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC0B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC0B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC0B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC0B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC0B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC0B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC0B5_LAUNCH_DMA (0x00000300) +#define NVC0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC0B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC0B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC0B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC0B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC0B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC0B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC0B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC0B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC0B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC0B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC0B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC0B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC0B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC0B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC0B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC0B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC0B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC0B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC0B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC0B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC0B5_LAUNCH_DMA_SRC_BYPASS_L2 20:20 +#define NVC0B5_LAUNCH_DMA_SRC_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC0B5_LAUNCH_DMA_SRC_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC0B5_LAUNCH_DMA_DST_BYPASS_L2 21:21 +#define NVC0B5_LAUNCH_DMA_DST_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC0B5_LAUNCH_DMA_DST_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC0B5_LAUNCH_DMA_RESERVED 31:28 +#define NVC0B5_OFFSET_IN_UPPER (0x00000400) +#define NVC0B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC0B5_OFFSET_IN_LOWER (0x00000404) +#define NVC0B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC0B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC0B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC0B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC0B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC0B5_PITCH_IN (0x00000410) +#define NVC0B5_PITCH_IN_VALUE 31:0 +#define NVC0B5_PITCH_OUT (0x00000414) +#define NVC0B5_PITCH_OUT_VALUE 31:0 +#define NVC0B5_LINE_LENGTH_IN (0x00000418) +#define NVC0B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC0B5_LINE_COUNT (0x0000041C) +#define NVC0B5_LINE_COUNT_VALUE 31:0 +#define NVC0B5_SET_REMAP_CONST_A (0x00000700) +#define NVC0B5_SET_REMAP_CONST_A_V 31:0 +#define NVC0B5_SET_REMAP_CONST_B (0x00000704) +#define NVC0B5_SET_REMAP_CONST_B_V 31:0 +#define NVC0B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC0B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC0B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC0B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC0B5_SET_DST_WIDTH (0x00000710) +#define NVC0B5_SET_DST_WIDTH_V 31:0 +#define NVC0B5_SET_DST_HEIGHT (0x00000714) +#define NVC0B5_SET_DST_HEIGHT_V 31:0 +#define NVC0B5_SET_DST_DEPTH (0x00000718) +#define NVC0B5_SET_DST_DEPTH_V 31:0 +#define NVC0B5_SET_DST_LAYER (0x0000071C) +#define NVC0B5_SET_DST_LAYER_V 31:0 +#define NVC0B5_SET_DST_ORIGIN (0x00000720) +#define NVC0B5_SET_DST_ORIGIN_X 15:0 +#define NVC0B5_SET_DST_ORIGIN_Y 31:16 +#define NVC0B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC0B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC0B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC0B5_SET_SRC_WIDTH (0x0000072C) +#define NVC0B5_SET_SRC_WIDTH_V 31:0 +#define NVC0B5_SET_SRC_HEIGHT (0x00000730) +#define NVC0B5_SET_SRC_HEIGHT_V 31:0 +#define NVC0B5_SET_SRC_DEPTH (0x00000734) +#define NVC0B5_SET_SRC_DEPTH_V 31:0 +#define NVC0B5_SET_SRC_LAYER (0x00000738) +#define NVC0B5_SET_SRC_LAYER_V 31:0 +#define NVC0B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC0B5_SET_SRC_ORIGIN_X 15:0 +#define NVC0B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC0B5_PM_TRIGGER_END (0x00001114) +#define NVC0B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc0b5_h + diff --git a/userspace/sdks/nv570/inc/class/clc0b5sw.h b/userspace/sdks/nv570/inc/class/clc0b5sw.h new file mode 100644 index 0000000..01ebd05 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc0b5sw.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc0b5sw.finn +// + + + +// +// Using VERSION_0 will cause the API to interpret +// engineType as a CE engine instance. This allows +// for backward compatibility with 85B5sw and 90B5sw. +// +#define NVC0B5_ALLOCATION_PARAMETERS_VERSION_0 0 + +// +// Using VERSION_1 will cause the API to interpret +// engineType as an NV2080_ENGINE_TYPE ordinal. +// +#define NVC0B5_ALLOCATION_PARAMETERS_VERSION_1 1 + +#define NVC0B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc0b5U) + +typedef struct NVC0B5_ALLOCATION_PARAMETERS { + NvU32 version; + NvU32 engineType; +} NVC0B5_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clc0b7.h b/userspace/sdks/nv570/inc/class/clc0b7.h new file mode 100644 index 0000000..bdb9bba --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc0b7.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clc0b7_h +#define clc0b7_h + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC0B7_VIDEO_ENCODER (0x0000C0B7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc0b7_h + diff --git a/userspace/sdks/nv570/inc/class/clc0c0.h b/userspace/sdks/nv570/inc/class/clc0c0.h new file mode 100644 index 0000000..fde8702 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc0c0.h @@ -0,0 +1,777 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_pascal_compute_a_h_ +#define _cl_pascal_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl pascal_compute_a */ + +#include "nvtypes.h" + +#define PASCAL_COMPUTE_A 0xC0C0 + +#define NVC0C0_SET_OBJECT 0x0000 +#define NVC0C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC0C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC0C0_NO_OPERATION 0x0100 +#define NVC0C0_NO_OPERATION_V 31:0 + +#define NVC0C0_SET_NOTIFY_A 0x0104 +#define NVC0C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC0C0_SET_NOTIFY_B 0x0108 +#define NVC0C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_NOTIFY 0x010c +#define NVC0C0_NOTIFY_TYPE 31:0 +#define NVC0C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC0C0_WAIT_FOR_IDLE 0x0110 +#define NVC0C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC0C0_SEND_GO_IDLE 0x013c +#define NVC0C0_SEND_GO_IDLE_V 31:0 + +#define NVC0C0_PM_TRIGGER 0x0140 +#define NVC0C0_PM_TRIGGER_V 31:0 + +#define NVC0C0_PM_TRIGGER_WFI 0x0144 +#define NVC0C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC0C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC0C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC0C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC0C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC0C0_LINE_LENGTH_IN 0x0180 +#define NVC0C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC0C0_LINE_COUNT 0x0184 +#define NVC0C0_LINE_COUNT_VALUE 31:0 + +#define NVC0C0_OFFSET_OUT_UPPER 0x0188 +#define NVC0C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC0C0_OFFSET_OUT 0x018c +#define NVC0C0_OFFSET_OUT_VALUE 31:0 + +#define NVC0C0_PITCH_OUT 0x0190 +#define NVC0C0_PITCH_OUT_VALUE 31:0 + +#define NVC0C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC0C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC0C0_SET_DST_WIDTH 0x0198 +#define NVC0C0_SET_DST_WIDTH_V 31:0 + +#define NVC0C0_SET_DST_HEIGHT 0x019c +#define NVC0C0_SET_DST_HEIGHT_V 31:0 + +#define NVC0C0_SET_DST_DEPTH 0x01a0 +#define NVC0C0_SET_DST_DEPTH_V 31:0 + +#define NVC0C0_SET_DST_LAYER 0x01a4 +#define NVC0C0_SET_DST_LAYER_V 31:0 + +#define NVC0C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC0C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC0C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC0C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC0C0_LAUNCH_DMA 0x01b0 +#define NVC0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC0C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC0C0_LOAD_INLINE_DATA 0x01b4 +#define NVC0C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC0C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC0C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC0C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC0C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC0C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC0C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC0C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC0C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC0C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC0C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC0C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC0C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVC0C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVC0C0_PERFMON_TRANSFER 0x0210 +#define NVC0C0_PERFMON_TRANSFER_V 31:0 + +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0218 +#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVC0C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC0C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC0C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC0C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC0C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC0C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC0C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC0C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC0C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC0C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC0C0_SET_CWD_CONTROL 0x0240 +#define NVC0C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVC0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVC0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC0C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC0C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC0C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC0C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC0C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC0C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC0C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC0C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC0C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC0C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC0C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC0C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC0C0_SET_GWC_SCG_TYPE 0x026c +#define NVC0C0_SET_GWC_SCG_TYPE_SCG_TYPE 0:0 +#define NVC0C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0 0x00000000 +#define NVC0C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1 0x00000001 + +#define NVC0C0_SET_SCG_CONTROL 0x0270 +#define NVC0C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 + +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 16:0 + +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVC0C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC0C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC0C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC0C0_SET_QMD_VERSION 0x0288 +#define NVC0C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC0C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC0C0_SET_WFI_CONFIG 0x028c +#define NVC0C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI 0:0 +#define NVC0C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE 0x00000000 +#define NVC0C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE 0x00000001 + +#define NVC0C0_CHECK_QMD_VERSION 0x0290 +#define NVC0C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC0C0_WAIT_FOR_IDLE_SCG_TYPE 0x0294 +#define NVC0C0_WAIT_FOR_IDLE_SCG_TYPE_V 31:0 + +#define NVC0C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC0C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL 0x029c +#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE 0:0 +#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE 0x00000001 + +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC0C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC0C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC0C0_SEND_PCAS_A 0x02b4 +#define NVC0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC0C0_SEND_PCAS_B 0x02b8 +#define NVC0C0_SEND_PCAS_B_FROM 23:0 +#define NVC0C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC0C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC0C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC0C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC0C0_SET_SPA_VERSION 0x0310 +#define NVC0C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC0C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC0C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC0C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC0C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC0C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC0C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC0C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC0C0_SET_FALCON00 0x0500 +#define NVC0C0_SET_FALCON00_V 31:0 + +#define NVC0C0_SET_FALCON01 0x0504 +#define NVC0C0_SET_FALCON01_V 31:0 + +#define NVC0C0_SET_FALCON02 0x0508 +#define NVC0C0_SET_FALCON02_V 31:0 + +#define NVC0C0_SET_FALCON03 0x050c +#define NVC0C0_SET_FALCON03_V 31:0 + +#define NVC0C0_SET_FALCON04 0x0510 +#define NVC0C0_SET_FALCON04_V 31:0 + +#define NVC0C0_SET_FALCON05 0x0514 +#define NVC0C0_SET_FALCON05_V 31:0 + +#define NVC0C0_SET_FALCON06 0x0518 +#define NVC0C0_SET_FALCON06_V 31:0 + +#define NVC0C0_SET_FALCON07 0x051c +#define NVC0C0_SET_FALCON07_V 31:0 + +#define NVC0C0_SET_FALCON08 0x0520 +#define NVC0C0_SET_FALCON08_V 31:0 + +#define NVC0C0_SET_FALCON09 0x0524 +#define NVC0C0_SET_FALCON09_V 31:0 + +#define NVC0C0_SET_FALCON10 0x0528 +#define NVC0C0_SET_FALCON10_V 31:0 + +#define NVC0C0_SET_FALCON11 0x052c +#define NVC0C0_SET_FALCON11_V 31:0 + +#define NVC0C0_SET_FALCON12 0x0530 +#define NVC0C0_SET_FALCON12_V 31:0 + +#define NVC0C0_SET_FALCON13 0x0534 +#define NVC0C0_SET_FALCON13_V 31:0 + +#define NVC0C0_SET_FALCON14 0x0538 +#define NVC0C0_SET_FALCON14_V 31:0 + +#define NVC0C0_SET_FALCON15 0x053c +#define NVC0C0_SET_FALCON15_V 31:0 + +#define NVC0C0_SET_FALCON16 0x0540 +#define NVC0C0_SET_FALCON16_V 31:0 + +#define NVC0C0_SET_FALCON17 0x0544 +#define NVC0C0_SET_FALCON17_V 31:0 + +#define NVC0C0_SET_FALCON18 0x0548 +#define NVC0C0_SET_FALCON18_V 31:0 + +#define NVC0C0_SET_FALCON19 0x054c +#define NVC0C0_SET_FALCON19_V 31:0 + +#define NVC0C0_SET_FALCON20 0x0550 +#define NVC0C0_SET_FALCON20_V 31:0 + +#define NVC0C0_SET_FALCON21 0x0554 +#define NVC0C0_SET_FALCON21_V 31:0 + +#define NVC0C0_SET_FALCON22 0x0558 +#define NVC0C0_SET_FALCON22_V 31:0 + +#define NVC0C0_SET_FALCON23 0x055c +#define NVC0C0_SET_FALCON23_V 31:0 + +#define NVC0C0_SET_FALCON24 0x0560 +#define NVC0C0_SET_FALCON24_V 31:0 + +#define NVC0C0_SET_FALCON25 0x0564 +#define NVC0C0_SET_FALCON25_V 31:0 + +#define NVC0C0_SET_FALCON26 0x0568 +#define NVC0C0_SET_FALCON26_V 31:0 + +#define NVC0C0_SET_FALCON27 0x056c +#define NVC0C0_SET_FALCON27_V 31:0 + +#define NVC0C0_SET_FALCON28 0x0570 +#define NVC0C0_SET_FALCON28_V 31:0 + +#define NVC0C0_SET_FALCON29 0x0574 +#define NVC0C0_SET_FALCON29_V 31:0 + +#define NVC0C0_SET_FALCON30 0x0578 +#define NVC0C0_SET_FALCON30_V 31:0 + +#define NVC0C0_SET_FALCON31 0x057c +#define NVC0C0_SET_FALCON31_V 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC0C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC0C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC0C0_SET_SPARE_NOOP12 0x0f44 +#define NVC0C0_SET_SPARE_NOOP12_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP13 0x0f48 +#define NVC0C0_SET_SPARE_NOOP13_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP14 0x0f4c +#define NVC0C0_SET_SPARE_NOOP14_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP15 0x0f50 +#define NVC0C0_SET_SPARE_NOOP15_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP00 0x1040 +#define NVC0C0_SET_SPARE_NOOP00_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP01 0x1044 +#define NVC0C0_SET_SPARE_NOOP01_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP02 0x1048 +#define NVC0C0_SET_SPARE_NOOP02_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP03 0x104c +#define NVC0C0_SET_SPARE_NOOP03_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP04 0x1050 +#define NVC0C0_SET_SPARE_NOOP04_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP05 0x1054 +#define NVC0C0_SET_SPARE_NOOP05_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP06 0x1058 +#define NVC0C0_SET_SPARE_NOOP06_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP07 0x105c +#define NVC0C0_SET_SPARE_NOOP07_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP08 0x1060 +#define NVC0C0_SET_SPARE_NOOP08_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP09 0x1064 +#define NVC0C0_SET_SPARE_NOOP09_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP10 0x1068 +#define NVC0C0_SET_SPARE_NOOP10_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP11 0x106c +#define NVC0C0_SET_SPARE_NOOP11_V 31:0 + +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC0C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC0C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC0C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC0C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC0C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC0C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC0C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC0C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC0C0_SET_PROGRAM_REGION_A 0x1608 +#define NVC0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 16:0 + +#define NVC0C0_SET_PROGRAM_REGION_B 0x160c +#define NVC0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC0C0_PIPE_NOP 0x1a2c +#define NVC0C0_PIPE_NOP_V 31:0 + +#define NVC0C0_SET_SPARE00 0x1a30 +#define NVC0C0_SET_SPARE00_V 31:0 + +#define NVC0C0_SET_SPARE01 0x1a34 +#define NVC0C0_SET_SPARE01_V 31:0 + +#define NVC0C0_SET_SPARE02 0x1a38 +#define NVC0C0_SET_SPARE02_V 31:0 + +#define NVC0C0_SET_SPARE03 0x1a3c +#define NVC0C0_SET_SPARE03_V 31:0 + +#define NVC0C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC0C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC0C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC0C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC0C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC0C0_SET_TRAP_HANDLER 0x260c +#define NVC0C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC0C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC0C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC0C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC0C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC0C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC0C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_pascal_compute_a_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc197.h b/userspace/sdks/nv570/inc/class/clc197.h new file mode 100644 index 0000000..b03d735 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc197.h @@ -0,0 +1,4242 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_pascal_b_h_ +#define _cl_pascal_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl pascal_b */ + +#include "nvtypes.h" + +#define PASCAL_B 0xC197 + +#define NVC197_SET_OBJECT 0x0000 +#define NVC197_SET_OBJECT_CLASS_ID 15:0 +#define NVC197_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC197_NO_OPERATION 0x0100 +#define NVC197_NO_OPERATION_V 31:0 + +#define NVC197_SET_NOTIFY_A 0x0104 +#define NVC197_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC197_SET_NOTIFY_B 0x0108 +#define NVC197_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC197_NOTIFY 0x010c +#define NVC197_NOTIFY_TYPE 31:0 +#define NVC197_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC197_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC197_WAIT_FOR_IDLE 0x0110 +#define NVC197_WAIT_FOR_IDLE_V 31:0 + +#define NVC197_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC197_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC197_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC197_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC197_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC197_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC197_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC197_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC197_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC197_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC197_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC197_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC197_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC197_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC197_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC197_SEND_GO_IDLE 0x013c +#define NVC197_SEND_GO_IDLE_V 31:0 + +#define NVC197_PM_TRIGGER 0x0140 +#define NVC197_PM_TRIGGER_V 31:0 + +#define NVC197_PM_TRIGGER_WFI 0x0144 +#define NVC197_PM_TRIGGER_WFI_V 31:0 + +#define NVC197_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC197_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC197_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC197_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC197_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC197_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC197_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC197_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC197_LINE_LENGTH_IN 0x0180 +#define NVC197_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC197_LINE_COUNT 0x0184 +#define NVC197_LINE_COUNT_VALUE 31:0 + +#define NVC197_OFFSET_OUT_UPPER 0x0188 +#define NVC197_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC197_OFFSET_OUT 0x018c +#define NVC197_OFFSET_OUT_VALUE 31:0 + +#define NVC197_PITCH_OUT 0x0190 +#define NVC197_PITCH_OUT_VALUE 31:0 + +#define NVC197_SET_DST_BLOCK_SIZE 0x0194 +#define NVC197_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC197_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC197_SET_DST_WIDTH 0x0198 +#define NVC197_SET_DST_WIDTH_V 31:0 + +#define NVC197_SET_DST_HEIGHT 0x019c +#define NVC197_SET_DST_HEIGHT_V 31:0 + +#define NVC197_SET_DST_DEPTH 0x01a0 +#define NVC197_SET_DST_DEPTH_V 31:0 + +#define NVC197_SET_DST_LAYER 0x01a4 +#define NVC197_SET_DST_LAYER_V 31:0 + +#define NVC197_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC197_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC197_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC197_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC197_LAUNCH_DMA 0x01b0 +#define NVC197_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC197_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC197_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC197_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC197_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC197_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC197_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC197_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC197_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC197_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC197_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC197_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC197_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC197_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC197_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC197_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC197_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC197_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC197_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC197_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC197_LOAD_INLINE_DATA 0x01b4 +#define NVC197_LOAD_INLINE_DATA_V 31:0 + +#define NVC197_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC197_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC197_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC197_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC197_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC197_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC197_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC197_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC197_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC197_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC197_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC197_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC197_RUN_DS_NOW 0x0200 +#define NVC197_RUN_DS_NOW_V 31:0 + +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC197_SET_GS_MODE 0x0208 +#define NVC197_SET_GS_MODE_TYPE 0:0 +#define NVC197_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVC197_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVC197_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC197_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC197_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC197_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC197_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC197_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_GS_DM_FIFO 0x0214 +#define NVC197_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC197_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC197_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC197_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC197_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC197_INVALIDATE_SHADER_CACHES 0x021c +#define NVC197_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC197_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC197_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC197_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC197_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC197_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC197_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC197_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC197_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC197_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC197_SET_INSTANCE_COUNT 0x0220 +#define NVC197_SET_INSTANCE_COUNT_V 31:0 + +#define NVC197_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVC197_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVC197_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC197_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVC197_INCREMENT_SYNC_POINT 0x02c8 +#define NVC197_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC197_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC197_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC197_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC197_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC197_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC197_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC197_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NVC197_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NVC197_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC197_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC197_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC197_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVC197_DECOMPRESS_SURFACE 0x02e0 +#define NVC197_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC197_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC197_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC197_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC197_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC197_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC197_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC197_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC197_SET_ZCULL_SUBREGION 0x02e8 +#define NVC197_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC197_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC197_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC197_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC197_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC197_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC197_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC197_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC197_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC197_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC197_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC197_DRAW_ZERO_INDEX 0x0304 +#define NVC197_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC197_SET_L1_CONFIGURATION 0x0308 +#define NVC197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC197_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC197_SET_SPA_VERSION 0x0310 +#define NVC197_SET_SPA_VERSION_MINOR 7:0 +#define NVC197_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC197_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NVC197_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NVC197_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_SNAP_GRID_LINE 0x0318 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC197_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC197_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC197_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC197_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC197_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC197_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC197_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC197_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC197_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC197_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC197_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC197_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC197_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC197_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC197_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC197_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC197_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC197_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC197_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC197_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC197_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC197_RESERVED_TG07 0x033c +#define NVC197_RESERVED_TG07_V 0:0 + +#define NVC197_RESERVED_TG08 0x0340 +#define NVC197_RESERVED_TG08_V 0:0 + +#define NVC197_RESERVED_TG09 0x0344 +#define NVC197_RESERVED_TG09_V 0:0 + +#define NVC197_RESERVED_TG10 0x0348 +#define NVC197_RESERVED_TG10_V 0:0 + +#define NVC197_RESERVED_TG11 0x034c +#define NVC197_RESERVED_TG11_V 0:0 + +#define NVC197_RESERVED_TG12 0x0350 +#define NVC197_RESERVED_TG12_V 0:0 + +#define NVC197_RESERVED_TG13 0x0354 +#define NVC197_RESERVED_TG13_V 0:0 + +#define NVC197_RESERVED_TG14 0x0358 +#define NVC197_RESERVED_TG14_V 0:0 + +#define NVC197_RESERVED_TG15 0x035c +#define NVC197_RESERVED_TG15_V 0:0 + +#define NVC197_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC197_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC197_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC197_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC197_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC197_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC197_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC197_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC197_SET_RASTER_ENABLE 0x037c +#define NVC197_SET_RASTER_ENABLE_V 0:0 +#define NVC197_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC197_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC197_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC197_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC197_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC197_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC197_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC197_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC197_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC197_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC197_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVC197_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVC197_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVC197_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVC197_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVC197_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVC197_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVC197_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVC197_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC197_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC197_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC197_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC197_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC197_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC197_SET_RASTER_INPUT 0x0740 +#define NVC197_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC197_SET_STREAM_OUTPUT 0x0744 +#define NVC197_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC197_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_ALPHA_FRACTION 0x074c +#define NVC197_SET_ALPHA_FRACTION_V 7:0 + +#define NVC197_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC197_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC197_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC197_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC197_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC197_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC197_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC197_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC197_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC197_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC197_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC197_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC197_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC197_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC197_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC197_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC197_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC197_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC197_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC197_SET_ISBE_SAVE_RESTORE_PROGRAM 0x07ac +#define NVC197_SET_ISBE_SAVE_RESTORE_PROGRAM_OFFSET 31:0 + +#define NVC197_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVC197_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC197_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC197_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC197_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC197_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC197_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC197_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC197_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC197_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC197_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC197_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC197_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC197_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC197_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC197_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC197_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC197_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC197_SET_ZCULL_STORAGE_B 0x07ec +#define NVC197_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC197_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC197_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC197_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC197_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC197_SET_ZT_READ_ONLY 0x07f8 +#define NVC197_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC197_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC197_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC197_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC197_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC197_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC197_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC197_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC197_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC197_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC197_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC197_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC197_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC197_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC197_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC197_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC197_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC197_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC197_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC197_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC197_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC197_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC197_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC197_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC197_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC197_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC197_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC197_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC197_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC197_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC197_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC197_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC197_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NVC197_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NVC197_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVC197_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVC197_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC197_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC197_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC197_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC197_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC197_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC197_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC197_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC197_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC197_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC197_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC197_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC197_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC197_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC197_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC197_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC197_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC197_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC197_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC197_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC197_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC197_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC197_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC197_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC197_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC197_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC197_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC197_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC197_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC197_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC197_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC197_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC197_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC197_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC197_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC197_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC197_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC197_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC197_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC197_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC197_SET_STATISTICS_COUNTER 0x0d68 +#define NVC197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVC197_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC197_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC197_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC197_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC197_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC197_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC197_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC197_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC197_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC197_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC197_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC197_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC197_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC197_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC197_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC197_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC197_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC197_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC197_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC197_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC197_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC197_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC197_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC197_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC197_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC197_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC197_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC197_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC197_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC197_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC197_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC197_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC197_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC197_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC197_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC197_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC197_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC197_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC197_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC197_SET_POLY_SMOOTH 0x0db4 +#define NVC197_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC197_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_ZT_MARK 0x0db8 +#define NVC197_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NVC197_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVC197_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVC197_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC197_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC197_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC197_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC197_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC197_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC197_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC197_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC197_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_PATCH 0x0dcc +#define NVC197_SET_PATCH_SIZE 7:0 + +#define NVC197_SET_ITERATED_BLEND 0x0dd0 +#define NVC197_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC197_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC197_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC197_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC197_SET_ZCULL_CRITERION 0x0dd8 +#define NVC197_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC197_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC197_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC197_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC197_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC197_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC197_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC197_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC197_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC197_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC197_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC197_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC197_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC197_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC197_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC197_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC197_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC197_SET_SCISSOR_ENABLE_V 0:0 +#define NVC197_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC197_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC197_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC197_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC197_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC197_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC197_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0f10 +#define NVC197_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVC197_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVC197_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVC197_SET_VPC_PERF_KNOB 0x0f14 +#define NVC197_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC197_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC197_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC197_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC197_PM_LOCAL_TRIGGER 0x0f18 +#define NVC197_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC197_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC197_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC197_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC197_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC197_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC197_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC197_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC197_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC197_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC197_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC197_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC197_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC197_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC197_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC197_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC197_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC197_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC197_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC197_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC197_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC197_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC197_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC197_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC197_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC197_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC197_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC197_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC197_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC197_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC197_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC197_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC197_SET_SAMPLE_MASK 0x0fa4 +#define NVC197_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC197_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC197_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC197_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC197_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC197_SET_CT_MRT_ENABLE 0x0fac +#define NVC197_SET_CT_MRT_ENABLE_V 0:0 +#define NVC197_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC197_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC197_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC197_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC197_SET_TIR 0x0fb4 +#define NVC197_SET_TIR_MODE 1:0 +#define NVC197_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC197_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC197_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC197_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC197_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC197_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC197_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC197_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC197_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC197_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC197_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC197_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC197_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC197_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC197_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_TIR_MODULATION 0x0fd4 +#define NVC197_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC197_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC197_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC197_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC197_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC197_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC197_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC197_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC197_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC197_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC197_SET_ZT_A 0x0fe0 +#define NVC197_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_ZT_B 0x0fe4 +#define NVC197_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_ZT_FORMAT 0x0fe8 +#define NVC197_SET_ZT_FORMAT_V 4:0 +#define NVC197_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC197_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC197_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC197_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC197_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC197_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC197_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC197_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC197_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC197_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC197_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC197_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC197_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC197_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC197_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC197_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC197_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC197_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC197_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC197_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC197_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC197_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC197_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC197_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC197_SET_TILED_CACHE_BUNDLE_CONTROL 0x0ffc +#define NVC197_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT 0:0 +#define NVC197_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_FALSE 0x00000000 +#define NVC197_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_TRUE 0x00000001 + +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC197_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC197_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC197_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC197_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC197_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC197_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC197_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC197_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC197_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC197_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC197_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC197_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC197_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC197_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC197_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC197_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC197_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC197_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD02 0x102c +#define NVC197_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC197_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC197_SET_SPARE_NOOP01 0x1044 +#define NVC197_SET_SPARE_NOOP01_V 31:0 + +#define NVC197_SET_SPARE_NOOP02 0x1048 +#define NVC197_SET_SPARE_NOOP02_V 31:0 + +#define NVC197_SET_SPARE_NOOP03 0x104c +#define NVC197_SET_SPARE_NOOP03_V 31:0 + +#define NVC197_SET_SPARE_NOOP04 0x1050 +#define NVC197_SET_SPARE_NOOP04_V 31:0 + +#define NVC197_SET_SPARE_NOOP05 0x1054 +#define NVC197_SET_SPARE_NOOP05_V 31:0 + +#define NVC197_SET_SPARE_NOOP06 0x1058 +#define NVC197_SET_SPARE_NOOP06_V 31:0 + +#define NVC197_SET_SPARE_NOOP07 0x105c +#define NVC197_SET_SPARE_NOOP07_V 31:0 + +#define NVC197_SET_SPARE_NOOP08 0x1060 +#define NVC197_SET_SPARE_NOOP08_V 31:0 + +#define NVC197_SET_SPARE_NOOP09 0x1064 +#define NVC197_SET_SPARE_NOOP09_V 31:0 + +#define NVC197_SET_SPARE_NOOP10 0x1068 +#define NVC197_SET_SPARE_NOOP10_V 31:0 + +#define NVC197_SET_SPARE_NOOP11 0x106c +#define NVC197_SET_SPARE_NOOP11_V 31:0 + +#define NVC197_SET_SPARE_NOOP12 0x1070 +#define NVC197_SET_SPARE_NOOP12_V 31:0 + +#define NVC197_SET_SPARE_NOOP13 0x1074 +#define NVC197_SET_SPARE_NOOP13_V 31:0 + +#define NVC197_SET_SPARE_NOOP14 0x1078 +#define NVC197_SET_SPARE_NOOP14_V 31:0 + +#define NVC197_SET_SPARE_NOOP15 0x107c +#define NVC197_SET_SPARE_NOOP15_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC197_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC197_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC197_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC197_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC197_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC197_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC197_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC197_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC197_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC197_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC197_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC197_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC197_UNBIND_ALL 0x10f4 +#define NVC197_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC197_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC197_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC197_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC197_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC197_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC197_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC197_NO_OPERATION_DATA_HI 0x110c +#define NVC197_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC197_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC197_PM_TRIGGER_END 0x1114 +#define NVC197_PM_TRIGGER_END_V 31:0 + +#define NVC197_SET_VERTEX_ID_BASE 0x1118 +#define NVC197_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC197_SET_STENCIL_COMPRESSION 0x111c +#define NVC197_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC197_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC197_SET_TIR_CONTROL 0x1130 +#define NVC197_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC197_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC197_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC197_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC197_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC197_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC197_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC197_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC197_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 + +#define NVC197_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC197_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC197_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC197_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC197_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC197_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC197_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC197_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC197_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC197_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC197_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC197_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC197_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC197_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC197_FLUSH_PENDING_WRITES 0x1144 +#define NVC197_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC197_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC197_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC197_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC197_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC197_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC197_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC197_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC197_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC197_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC197_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC197_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC197_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC197_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC197_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC197_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC197_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC197_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC197_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC197_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC197_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC197_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC197_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_SCREEN_STATE_MASK 0x1204 +#define NVC197_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC197_SET_ZT_SPARSE 0x1208 +#define NVC197_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC197_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC197_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC197_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC197_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC197_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_SET_CT_SELECT 0x121c +#define NVC197_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC197_SET_CT_SELECT_TARGET0 6:4 +#define NVC197_SET_CT_SELECT_TARGET1 9:7 +#define NVC197_SET_CT_SELECT_TARGET2 12:10 +#define NVC197_SET_CT_SELECT_TARGET3 15:13 +#define NVC197_SET_CT_SELECT_TARGET4 18:16 +#define NVC197_SET_CT_SELECT_TARGET5 21:19 +#define NVC197_SET_CT_SELECT_TARGET6 24:22 +#define NVC197_SET_CT_SELECT_TARGET7 27:25 + +#define NVC197_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC197_SET_ZT_SIZE_A 0x1228 +#define NVC197_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC197_SET_ZT_SIZE_B 0x122c +#define NVC197_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC197_SET_ZT_SIZE_C 0x1230 +#define NVC197_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC197_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC197_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC197_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC197_SET_SAMPLER_BINDING 0x1234 +#define NVC197_SET_SAMPLER_BINDING_V 0:0 +#define NVC197_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC197_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC197_DRAW_AUTO 0x123c +#define NVC197_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC197_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC197_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC197_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC197_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC197_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC197_SET_BACK_END_COPY_A 0x1264 +#define NVC197_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC197_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC197_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC197_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC197_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BACK_END_COPY_B 0x1268 +#define NVC197_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC197_SET_BACK_END_COPY_C 0x126c +#define NVC197_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC197_SET_BACK_END_COPY_D 0x1270 +#define NVC197_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC197_SET_BACK_END_COPY_E 0x1274 +#define NVC197_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC197_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC197_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVC197_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC197_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC197_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC197_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC197_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC197_CLEAR_ZCULL_REGION 0x12c8 +#define NVC197_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC197_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC197_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC197_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC197_SET_DEPTH_TEST 0x12cc +#define NVC197_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC197_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC197_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_FILL_MODE 0x12d0 +#define NVC197_SET_FILL_MODE_V 31:0 +#define NVC197_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC197_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC197_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC197_SET_SHADE_MODE 0x12d4 +#define NVC197_SET_SHADE_MODE_V 31:0 +#define NVC197_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC197_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC197_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC197_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC197_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC197_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC197_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_DEPTH_WRITE 0x12e8 +#define NVC197_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC197_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_ALPHA_TEST 0x12ec +#define NVC197_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC197_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC197_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC197_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC197_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC197_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC197_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC197_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC197_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC197_D3D_SET_CULL_MODE 0x1308 +#define NVC197_D3D_SET_CULL_MODE_V 31:0 +#define NVC197_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC197_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC197_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC197_SET_DEPTH_FUNC 0x130c +#define NVC197_SET_DEPTH_FUNC_V 31:0 +#define NVC197_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC197_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC197_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC197_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC197_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC197_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC197_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC197_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC197_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC197_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC197_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC197_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC197_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC197_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC197_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC197_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC197_SET_ALPHA_REF 0x1310 +#define NVC197_SET_ALPHA_REF_V 31:0 + +#define NVC197_SET_ALPHA_FUNC 0x1314 +#define NVC197_SET_ALPHA_FUNC_V 31:0 +#define NVC197_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC197_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC197_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC197_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC197_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC197_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC197_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC197_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC197_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC197_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC197_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC197_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC197_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC197_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC197_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC197_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC197_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC197_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC197_SET_BLEND_CONST_RED 0x131c +#define NVC197_SET_BLEND_CONST_RED_V 31:0 + +#define NVC197_SET_BLEND_CONST_GREEN 0x1320 +#define NVC197_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC197_SET_BLEND_CONST_BLUE 0x1324 +#define NVC197_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC197_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC197_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC197_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC197_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC197_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC197_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC197_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC197_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BLEND_COLOR_OP 0x1340 +#define NVC197_SET_BLEND_COLOR_OP_V 31:0 +#define NVC197_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC197_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC197_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC197_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC197_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC197_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC197_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC197_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC197_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC197_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_BLEND_ALPHA_OP 0x134c +#define NVC197_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC197_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC197_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC197_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC197_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC197_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC197_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC197_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC197_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC197_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC197_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC197_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC197_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BLEND(i) (0x1360+(i)*4) +#define NVC197_SET_BLEND_ENABLE 0:0 +#define NVC197_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_STENCIL_TEST 0x1380 +#define NVC197_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC197_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_STENCIL_OP_FAIL 0x1384 +#define NVC197_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC197_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC197_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC197_SET_STENCIL_OP_ZPASS 0x138c +#define NVC197_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC197_SET_STENCIL_FUNC 0x1390 +#define NVC197_SET_STENCIL_FUNC_V 31:0 +#define NVC197_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC197_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC197_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC197_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC197_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC197_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC197_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC197_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC197_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC197_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC197_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC197_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC197_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC197_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC197_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC197_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC197_SET_STENCIL_FUNC_REF 0x1394 +#define NVC197_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC197_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC197_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC197_SET_STENCIL_MASK 0x139c +#define NVC197_SET_STENCIL_MASK_V 7:0 + +#define NVC197_SET_DRAW_AUTO_START 0x13a4 +#define NVC197_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC197_SET_PS_SATURATE 0x13a8 +#define NVC197_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC197_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC197_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC197_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC197_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC197_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC197_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC197_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC197_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC197_SET_WINDOW_ORIGIN 0x13ac +#define NVC197_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC197_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC197_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC197_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC197_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC197_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC197_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC197_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC197_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC197_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC197_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_ALPHA_HYSTERESIS 0x1420 +#define NVC197_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NVC197_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC197_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC197_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC197_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC197_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC197_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC197_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC197_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC197_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC197_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC197_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC197_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC197_STORE_ZCULL 0x1464 +#define NVC197_STORE_ZCULL_V 0:0 + +#define NVC197_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC197_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC197_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC197_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC197_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC197_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC197_LOAD_ZCULL 0x1500 +#define NVC197_LOAD_ZCULL_V 0:0 + +#define NVC197_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC197_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC197_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC197_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC197_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC197_SET_USER_CLIP_ENABLE 0x1510 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC197_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC197_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC197_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_POINT_SIZE 0x1518 +#define NVC197_SET_POINT_SIZE_V 31:0 + +#define NVC197_SET_ZCULL_STATS 0x151c +#define NVC197_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC197_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_POINT_SPRITE 0x1520 +#define NVC197_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC197_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC197_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC197_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC197_CLEAR_REPORT_VALUE 0x1530 +#define NVC197_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC197_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC197_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC197_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC197_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC197_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC197_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVC197_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC197_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC197_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_ZT_SELECT 0x1538 +#define NVC197_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC197_SET_RENDER_ENABLE_A 0x1550 +#define NVC197_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_RENDER_ENABLE_B 0x1554 +#define NVC197_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_RENDER_ENABLE_C 0x1558 +#define NVC197_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC197_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC197_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC197_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC197_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC197_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC197_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC197_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC197_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC197_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC197_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC197_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC197_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC197_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC197_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC197_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC197_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_TEX_HEADER_POOL_C 0x157c +#define NVC197_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC197_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC197_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC197_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC197_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC197_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC197_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC197_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC197_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC197_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC197_SET_SRGB_WRITE 0x15b8 +#define NVC197_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC197_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_DEPTH_BIAS 0x15bc +#define NVC197_SET_DEPTH_BIAS_V 31:0 + +#define NVC197_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC197_SET_RT_LAYER 0x15cc +#define NVC197_SET_RT_LAYER_V 15:0 +#define NVC197_SET_RT_LAYER_CONTROL 16:16 +#define NVC197_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC197_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC197_SET_ANTI_ALIAS 0x15d0 +#define NVC197_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC197_SET_EDGE_FLAG 0x15e4 +#define NVC197_SET_EDGE_FLAG_V 0:0 +#define NVC197_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC197_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC197_DRAW_INLINE_INDEX 0x15e8 +#define NVC197_DRAW_INLINE_INDEX_V 31:0 + +#define NVC197_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC197_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC197_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC197_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC197_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC197_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC197_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC197_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC197_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC197_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC197_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC197_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC197_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC197_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC197_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC197_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC197_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC197_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC197_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC197_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC197_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC197_SET_PROGRAM_REGION_A 0x1608 +#define NVC197_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVC197_SET_PROGRAM_REGION_B 0x160c +#define NVC197_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVC197_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC197_END 0x1614 +#define NVC197_END_V 0:0 + +#define NVC197_BEGIN 0x1618 +#define NVC197_BEGIN_OP 15:0 +#define NVC197_BEGIN_OP_POINTS 0x00000000 +#define NVC197_BEGIN_OP_LINES 0x00000001 +#define NVC197_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC197_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC197_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC197_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC197_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC197_BEGIN_OP_QUADS 0x00000007 +#define NVC197_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC197_BEGIN_OP_POLYGON 0x00000009 +#define NVC197_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC197_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC197_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_BEGIN_OP_PATCH 0x0000000E +#define NVC197_BEGIN_PRIMITIVE_ID 24:24 +#define NVC197_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC197_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC197_BEGIN_INSTANCE_ID 27:26 +#define NVC197_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC197_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC197_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC197_BEGIN_SPLIT_MODE 30:29 +#define NVC197_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC197_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC197_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC197_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC197_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVC197_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC197_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_VERTEX_ID_COPY 0x161c +#define NVC197_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC197_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC197_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC197_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC197_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC197_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC197_LOAD_PRIMITIVE_ID 0x1624 +#define NVC197_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC197_SET_SHADER_BASED_CULL 0x162c +#define NVC197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_CLASS_VERSION 0x1638 +#define NVC197_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC197_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC197_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC197_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC197_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC197_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC197_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC197_SET_DA_OUTPUT 0x164c +#define NVC197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC197_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC197_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC197_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_POINT_CENTER_MODE 0x165c +#define NVC197_SET_POINT_CENTER_MODE_V 31:0 +#define NVC197_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC197_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC197_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC197_SET_LINE_STIPPLE 0x166c +#define NVC197_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC197_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC197_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC197_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC197_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC197_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC197_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC197_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC197_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC197_SET_PROVOKING_VERTEX 0x1684 +#define NVC197_SET_PROVOKING_VERTEX_V 0:0 +#define NVC197_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC197_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC197_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC197_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC197_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_POLYGON_STIPPLE 0x168c +#define NVC197_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC197_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_SHADER_CONTROL 0x1690 +#define NVC197_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC197_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC197_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC197_CHECK_CLASS_VERSION 0x16a0 +#define NVC197_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC197_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC197_SET_SPH_VERSION 0x16a4 +#define NVC197_SET_SPH_VERSION_CURRENT 15:0 +#define NVC197_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC197_CHECK_SPH_VERSION 0x16a8 +#define NVC197_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC197_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC197_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC197_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC197_SET_AAM_VERSION 0x1790 +#define NVC197_SET_AAM_VERSION_CURRENT 15:0 +#define NVC197_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC197_CHECK_AAM_VERSION 0x1794 +#define NVC197_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC197_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC197_SET_ZT_LAYER 0x179c +#define NVC197_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC197_SET_INDEX_BUFFER_A 0x17c8 +#define NVC197_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC197_SET_INDEX_BUFFER_B 0x17cc +#define NVC197_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC197_SET_INDEX_BUFFER_C 0x17d0 +#define NVC197_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC197_SET_INDEX_BUFFER_D 0x17d4 +#define NVC197_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC197_SET_INDEX_BUFFER_E 0x17d8 +#define NVC197_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC197_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC197_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC197_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC197_SET_INDEX_BUFFER_F 0x17dc +#define NVC197_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC197_DRAW_INDEX_BUFFER 0x17e0 +#define NVC197_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC197_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC197_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC197_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC197_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC197_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC197_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC197_OGL_SET_CULL 0x1918 +#define NVC197_OGL_SET_CULL_ENABLE 0:0 +#define NVC197_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC197_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC197_OGL_SET_FRONT_FACE 0x191c +#define NVC197_OGL_SET_FRONT_FACE_V 31:0 +#define NVC197_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC197_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC197_OGL_SET_CULL_FACE 0x1920 +#define NVC197_OGL_SET_CULL_FACE_V 31:0 +#define NVC197_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC197_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC197_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC197_SET_VIEWPORT_PIXEL 0x1924 +#define NVC197_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC197_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC197_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC197_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC197_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC197_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC197_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC197_SET_USER_CLIP_OP 0x1940 +#define NVC197_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC197_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC197_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC197_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC197_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC197_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC197_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC197_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC197_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC197_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC197_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC197_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC197_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC197_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC197_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC197_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC197_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC197_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC197_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC197_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC197_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC197_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC197_INVALIDATE_ZCULL 0x1958 +#define NVC197_INVALIDATE_ZCULL_V 31:0 +#define NVC197_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC197_SET_ZCULL 0x1968 +#define NVC197_SET_ZCULL_Z_ENABLE 0:0 +#define NVC197_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC197_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_ZCULL_BOUNDS 0x196c +#define NVC197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC197_ZCULL_SYNC 0x1978 +#define NVC197_ZCULL_SYNC_V 31:0 + +#define NVC197_SET_CLIP_ID_TEST 0x197c +#define NVC197_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC197_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC197_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC197_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC197_SET_CLIP_ID 0x1984 +#define NVC197_SET_CLIP_ID_V 31:0 + +#define NVC197_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC197_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC197_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC197_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC197_SET_LOGIC_OP 0x19c4 +#define NVC197_SET_LOGIC_OP_ENABLE 0:0 +#define NVC197_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC197_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC197_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC197_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC197_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC197_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC197_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC197_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC197_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC197_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC197_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC197_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC197_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC197_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC197_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC197_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC197_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC197_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC197_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC197_SET_Z_COMPRESSION 0x19cc +#define NVC197_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC197_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC197_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC197_CLEAR_SURFACE 0x19d0 +#define NVC197_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC197_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC197_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC197_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC197_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC197_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC197_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC197_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC197_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC197_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC197_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC197_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC197_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC197_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC197_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC197_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC197_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC197_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC197_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC197_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC197_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC197_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC197_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC197_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC197_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC197_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC197_PIPE_NOP 0x1a2c +#define NVC197_PIPE_NOP_V 31:0 + +#define NVC197_SET_SPARE00 0x1a30 +#define NVC197_SET_SPARE00_V 31:0 + +#define NVC197_SET_SPARE01 0x1a34 +#define NVC197_SET_SPARE01_V 31:0 + +#define NVC197_SET_SPARE02 0x1a38 +#define NVC197_SET_SPARE02_V 31:0 + +#define NVC197_SET_SPARE03 0x1a3c +#define NVC197_SET_SPARE03_V 31:0 + +#define NVC197_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC197_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC197_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC197_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC197_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC197_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC197_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC197_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC197_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC197_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC197_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC197_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC197_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC197_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC197_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC197_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC197_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC197_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC197_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC197_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC197_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC197_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC197_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC197_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC197_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC197_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC197_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVC197_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVC197_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVC197_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVC197_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVC197_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVC197_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVC197_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVC197_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC197_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC197_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC197_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC197_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC197_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC197_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC197_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC197_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC197_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC197_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC197_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NVC197_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NVC197_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC197_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC197_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC197_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NVC197_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC197_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC197_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NVC197_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVC197_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NVC197_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NVC197_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVC197_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVC197_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC197_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC197_SET_FALCON00 0x2300 +#define NVC197_SET_FALCON00_V 31:0 + +#define NVC197_SET_FALCON01 0x2304 +#define NVC197_SET_FALCON01_V 31:0 + +#define NVC197_SET_FALCON02 0x2308 +#define NVC197_SET_FALCON02_V 31:0 + +#define NVC197_SET_FALCON03 0x230c +#define NVC197_SET_FALCON03_V 31:0 + +#define NVC197_SET_FALCON04 0x2310 +#define NVC197_SET_FALCON04_V 31:0 + +#define NVC197_SET_FALCON05 0x2314 +#define NVC197_SET_FALCON05_V 31:0 + +#define NVC197_SET_FALCON06 0x2318 +#define NVC197_SET_FALCON06_V 31:0 + +#define NVC197_SET_FALCON07 0x231c +#define NVC197_SET_FALCON07_V 31:0 + +#define NVC197_SET_FALCON08 0x2320 +#define NVC197_SET_FALCON08_V 31:0 + +#define NVC197_SET_FALCON09 0x2324 +#define NVC197_SET_FALCON09_V 31:0 + +#define NVC197_SET_FALCON10 0x2328 +#define NVC197_SET_FALCON10_V 31:0 + +#define NVC197_SET_FALCON11 0x232c +#define NVC197_SET_FALCON11_V 31:0 + +#define NVC197_SET_FALCON12 0x2330 +#define NVC197_SET_FALCON12_V 31:0 + +#define NVC197_SET_FALCON13 0x2334 +#define NVC197_SET_FALCON13_V 31:0 + +#define NVC197_SET_FALCON14 0x2338 +#define NVC197_SET_FALCON14_V 31:0 + +#define NVC197_SET_FALCON15 0x233c +#define NVC197_SET_FALCON15_V 31:0 + +#define NVC197_SET_FALCON16 0x2340 +#define NVC197_SET_FALCON16_V 31:0 + +#define NVC197_SET_FALCON17 0x2344 +#define NVC197_SET_FALCON17_V 31:0 + +#define NVC197_SET_FALCON18 0x2348 +#define NVC197_SET_FALCON18_V 31:0 + +#define NVC197_SET_FALCON19 0x234c +#define NVC197_SET_FALCON19_V 31:0 + +#define NVC197_SET_FALCON20 0x2350 +#define NVC197_SET_FALCON20_V 31:0 + +#define NVC197_SET_FALCON21 0x2354 +#define NVC197_SET_FALCON21_V 31:0 + +#define NVC197_SET_FALCON22 0x2358 +#define NVC197_SET_FALCON22_V 31:0 + +#define NVC197_SET_FALCON23 0x235c +#define NVC197_SET_FALCON23_V 31:0 + +#define NVC197_SET_FALCON24 0x2360 +#define NVC197_SET_FALCON24_V 31:0 + +#define NVC197_SET_FALCON25 0x2364 +#define NVC197_SET_FALCON25_V 31:0 + +#define NVC197_SET_FALCON26 0x2368 +#define NVC197_SET_FALCON26_V 31:0 + +#define NVC197_SET_FALCON27 0x236c +#define NVC197_SET_FALCON27_V 31:0 + +#define NVC197_SET_FALCON28 0x2370 +#define NVC197_SET_FALCON28_V 31:0 + +#define NVC197_SET_FALCON29 0x2374 +#define NVC197_SET_FALCON29_V 31:0 + +#define NVC197_SET_FALCON30 0x2378 +#define NVC197_SET_FALCON30_V 31:0 + +#define NVC197_SET_FALCON31 0x237c +#define NVC197_SET_FALCON31_V 31:0 + +#define NVC197_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC197_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC197_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC197_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC197_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC197_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC197_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC197_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC197_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC197_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC197_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC197_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC197_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC197_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC197_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC197_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC197_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC197_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC197_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC197_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC197_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC197_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC197_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC197_SET_COLOR_CLAMP 0x2600 +#define NVC197_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC197_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC197_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BINDLESS_TEXTURE 0x2608 +#define NVC197_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVC197_SET_TRAP_HANDLER 0x260c +#define NVC197_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVC197_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC197_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC197_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC197_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC197_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC197_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC197_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC197_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC197_CALL_MME_MACRO_V 31:0 + +#define NVC197_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC197_CALL_MME_DATA_V 31:0 + +#endif /* _cl_pascal_b_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc1b0.h b/userspace/sdks/nv570/inc/class/clc1b0.h new file mode 100644 index 0000000..ec139e9 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc1b0.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "nvtypes.h" + +#ifndef _clc1b0_h_ +#define _clc1b0_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC1B0_VIDEO_DECODER (0x0000C1B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc1b0_h + diff --git a/userspace/sdks/nv570/inc/class/clc1b5.h b/userspace/sdks/nv570/inc/class/clc1b5.h new file mode 100644 index 0000000..fff8467 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc1b5.h @@ -0,0 +1,273 @@ +/******************************************************************************* + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clc1b5_h_ +#define _clc1b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define PASCAL_DMA_COPY_B (0x0000C1B5) + +#define NVC1B5_NOP (0x00000100) +#define NVC1B5_NOP_PARAMETER 31:0 +#define NVC1B5_PM_TRIGGER (0x00000140) +#define NVC1B5_PM_TRIGGER_V 31:0 +#define NVC1B5_SET_SEMAPHORE_A (0x00000240) +#define NVC1B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC1B5_SET_SEMAPHORE_B (0x00000244) +#define NVC1B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC1B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC1B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC1B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC1B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC1B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC1B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC1B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC1B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC1B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC1B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC1B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC1B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC1B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC1B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC1B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC1B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC1B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC1B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC1B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC1B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC1B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC1B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC1B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC1B5_LAUNCH_DMA (0x00000300) +#define NVC1B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC1B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC1B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC1B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC1B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC1B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC1B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC1B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC1B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC1B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC1B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC1B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC1B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC1B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC1B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC1B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC1B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC1B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC1B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC1B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC1B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC1B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC1B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC1B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC1B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC1B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC1B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC1B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC1B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC1B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC1B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC1B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC1B5_LAUNCH_DMA_SRC_BYPASS_L2 20:20 +#define NVC1B5_LAUNCH_DMA_SRC_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC1B5_LAUNCH_DMA_SRC_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC1B5_LAUNCH_DMA_DST_BYPASS_L2 21:21 +#define NVC1B5_LAUNCH_DMA_DST_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC1B5_LAUNCH_DMA_DST_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC1B5_LAUNCH_DMA_VPRMODE 23:22 +#define NVC1B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVC1B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC1B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC1B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 +#define NVC1B5_OFFSET_IN_UPPER (0x00000400) +#define NVC1B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC1B5_OFFSET_IN_LOWER (0x00000404) +#define NVC1B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC1B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC1B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC1B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC1B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC1B5_PITCH_IN (0x00000410) +#define NVC1B5_PITCH_IN_VALUE 31:0 +#define NVC1B5_PITCH_OUT (0x00000414) +#define NVC1B5_PITCH_OUT_VALUE 31:0 +#define NVC1B5_LINE_LENGTH_IN (0x00000418) +#define NVC1B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC1B5_LINE_COUNT (0x0000041C) +#define NVC1B5_LINE_COUNT_VALUE 31:0 +#define NVC1B5_SET_REMAP_CONST_A (0x00000700) +#define NVC1B5_SET_REMAP_CONST_A_V 31:0 +#define NVC1B5_SET_REMAP_CONST_B (0x00000704) +#define NVC1B5_SET_REMAP_CONST_B_V 31:0 +#define NVC1B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC1B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC1B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC1B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC1B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC1B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC1B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC1B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC1B5_SET_DST_WIDTH (0x00000710) +#define NVC1B5_SET_DST_WIDTH_V 31:0 +#define NVC1B5_SET_DST_HEIGHT (0x00000714) +#define NVC1B5_SET_DST_HEIGHT_V 31:0 +#define NVC1B5_SET_DST_DEPTH (0x00000718) +#define NVC1B5_SET_DST_DEPTH_V 31:0 +#define NVC1B5_SET_DST_LAYER (0x0000071C) +#define NVC1B5_SET_DST_LAYER_V 31:0 +#define NVC1B5_SET_DST_ORIGIN (0x00000720) +#define NVC1B5_SET_DST_ORIGIN_X 15:0 +#define NVC1B5_SET_DST_ORIGIN_Y 31:16 +#define NVC1B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC1B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC1B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC1B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC1B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC1B5_SET_SRC_WIDTH (0x0000072C) +#define NVC1B5_SET_SRC_WIDTH_V 31:0 +#define NVC1B5_SET_SRC_HEIGHT (0x00000730) +#define NVC1B5_SET_SRC_HEIGHT_V 31:0 +#define NVC1B5_SET_SRC_DEPTH (0x00000734) +#define NVC1B5_SET_SRC_DEPTH_V 31:0 +#define NVC1B5_SET_SRC_LAYER (0x00000738) +#define NVC1B5_SET_SRC_LAYER_V 31:0 +#define NVC1B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC1B5_SET_SRC_ORIGIN_X 15:0 +#define NVC1B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC1B5_SRC_ORIGIN_X (0x00000744) +#define NVC1B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC1B5_SRC_ORIGIN_Y (0x00000748) +#define NVC1B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC1B5_DST_ORIGIN_X (0x0000074C) +#define NVC1B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC1B5_DST_ORIGIN_Y (0x00000750) +#define NVC1B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC1B5_PM_TRIGGER_END (0x00001114) +#define NVC1B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc1b5_h + diff --git a/userspace/sdks/nv570/inc/class/clc1b5sw.h b/userspace/sdks/nv570/inc/class/clc1b5sw.h new file mode 100644 index 0000000..08da246 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc1b5sw.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc1b5sw.finn +// + + + +// +// Using VERSION_0 will cause the API to interpret +// engineType as a CE engine instance. This allows +// for backward compatibility with 85B5sw and 90B5sw. +// +#define NVC1B5_ALLOCATION_PARAMETERS_VERSION_0 0 + +// +// Using VERSION_1 will cause the API to interpret +// engineType as an NV2080_ENGINE_TYPE ordinal. +// +#define NVC1B5_ALLOCATION_PARAMETERS_VERSION_1 1 + +#define NVC1B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc1b5U) + +typedef struct NVC1B5_ALLOCATION_PARAMETERS { + NvU32 version; + NvU32 engineType; +} NVC1B5_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clc1b7.h b/userspace/sdks/nv570/inc/class/clc1b7.h new file mode 100644 index 0000000..14d94ed --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc1b7.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clc1b7_h +#define clc1b7_h + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC1B7_VIDEO_ENCODER (0x0000C1B7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc1b7_h + diff --git a/userspace/sdks/nv570/inc/class/clc1c0.h b/userspace/sdks/nv570/inc/class/clc1c0.h new file mode 100644 index 0000000..f2569bf --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc1c0.h @@ -0,0 +1,795 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_pascal_compute_b_h_ +#define _cl_pascal_compute_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl pascal_compute_b */ + +#include "nvtypes.h" + +#define PASCAL_COMPUTE_B 0xC1C0 + +#define NVC1C0_SET_OBJECT 0x0000 +#define NVC1C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC1C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC1C0_NO_OPERATION 0x0100 +#define NVC1C0_NO_OPERATION_V 31:0 + +#define NVC1C0_SET_NOTIFY_A 0x0104 +#define NVC1C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC1C0_SET_NOTIFY_B 0x0108 +#define NVC1C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_NOTIFY 0x010c +#define NVC1C0_NOTIFY_TYPE 31:0 +#define NVC1C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC1C0_WAIT_FOR_IDLE 0x0110 +#define NVC1C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC1C0_SEND_GO_IDLE 0x013c +#define NVC1C0_SEND_GO_IDLE_V 31:0 + +#define NVC1C0_PM_TRIGGER 0x0140 +#define NVC1C0_PM_TRIGGER_V 31:0 + +#define NVC1C0_PM_TRIGGER_WFI 0x0144 +#define NVC1C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC1C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC1C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC1C0_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC1C0_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC1C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC1C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC1C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC1C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC1C0_LINE_LENGTH_IN 0x0180 +#define NVC1C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC1C0_LINE_COUNT 0x0184 +#define NVC1C0_LINE_COUNT_VALUE 31:0 + +#define NVC1C0_OFFSET_OUT_UPPER 0x0188 +#define NVC1C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC1C0_OFFSET_OUT 0x018c +#define NVC1C0_OFFSET_OUT_VALUE 31:0 + +#define NVC1C0_PITCH_OUT 0x0190 +#define NVC1C0_PITCH_OUT_VALUE 31:0 + +#define NVC1C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC1C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC1C0_SET_DST_WIDTH 0x0198 +#define NVC1C0_SET_DST_WIDTH_V 31:0 + +#define NVC1C0_SET_DST_HEIGHT 0x019c +#define NVC1C0_SET_DST_HEIGHT_V 31:0 + +#define NVC1C0_SET_DST_DEPTH 0x01a0 +#define NVC1C0_SET_DST_DEPTH_V 31:0 + +#define NVC1C0_SET_DST_LAYER 0x01a4 +#define NVC1C0_SET_DST_LAYER_V 31:0 + +#define NVC1C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC1C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC1C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC1C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC1C0_LAUNCH_DMA 0x01b0 +#define NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC1C0_LOAD_INLINE_DATA 0x01b4 +#define NVC1C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC1C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC1C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC1C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC1C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC1C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC1C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC1C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC1C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC1C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC1C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC1C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC1C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC1C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC1C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVC1C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVC1C0_PERFMON_TRANSFER 0x0210 +#define NVC1C0_PERFMON_TRANSFER_V 31:0 + +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0218 +#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVC1C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC1C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC1C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC1C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC1C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC1C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC1C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC1C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC1C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC1C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC1C0_SET_CWD_CONTROL 0x0240 +#define NVC1C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVC1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVC1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC1C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC1C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC1C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC1C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC1C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC1C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC1C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC1C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC1C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC1C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC1C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC1C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC1C0_SET_GWC_SCG_TYPE 0x026c +#define NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE 0:0 +#define NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0 0x00000000 +#define NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1 0x00000001 + +#define NVC1C0_SET_SCG_CONTROL 0x0270 +#define NVC1C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 +#define NVC1C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 +#define NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 +#define NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 +#define NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 + +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 16:0 + +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVC1C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC1C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC1C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC1C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC1C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC1C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC1C0_SET_QMD_VERSION 0x0288 +#define NVC1C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC1C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC1C0_SET_WFI_CONFIG 0x028c +#define NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI 0:0 +#define NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE 0x00000000 +#define NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE 0x00000001 + +#define NVC1C0_CHECK_QMD_VERSION 0x0290 +#define NVC1C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC1C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC1C0_WAIT_FOR_IDLE_SCG_TYPE 0x0294 +#define NVC1C0_WAIT_FOR_IDLE_SCG_TYPE_V 31:0 + +#define NVC1C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC1C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL 0x029c +#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE 0:0 +#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE 0x00000001 + +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC1C0_SCG_HYSTERESIS_CONTROL 0x02a8 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 + +#define NVC1C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC1C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC1C0_SEND_PCAS_A 0x02b4 +#define NVC1C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC1C0_SEND_PCAS_B 0x02b8 +#define NVC1C0_SEND_PCAS_B_FROM 23:0 +#define NVC1C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC1C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC1C0_SET_SPA_VERSION 0x0310 +#define NVC1C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC1C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC1C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC1C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC1C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC1C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC1C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC1C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC1C0_SET_FALCON00 0x0500 +#define NVC1C0_SET_FALCON00_V 31:0 + +#define NVC1C0_SET_FALCON01 0x0504 +#define NVC1C0_SET_FALCON01_V 31:0 + +#define NVC1C0_SET_FALCON02 0x0508 +#define NVC1C0_SET_FALCON02_V 31:0 + +#define NVC1C0_SET_FALCON03 0x050c +#define NVC1C0_SET_FALCON03_V 31:0 + +#define NVC1C0_SET_FALCON04 0x0510 +#define NVC1C0_SET_FALCON04_V 31:0 + +#define NVC1C0_SET_FALCON05 0x0514 +#define NVC1C0_SET_FALCON05_V 31:0 + +#define NVC1C0_SET_FALCON06 0x0518 +#define NVC1C0_SET_FALCON06_V 31:0 + +#define NVC1C0_SET_FALCON07 0x051c +#define NVC1C0_SET_FALCON07_V 31:0 + +#define NVC1C0_SET_FALCON08 0x0520 +#define NVC1C0_SET_FALCON08_V 31:0 + +#define NVC1C0_SET_FALCON09 0x0524 +#define NVC1C0_SET_FALCON09_V 31:0 + +#define NVC1C0_SET_FALCON10 0x0528 +#define NVC1C0_SET_FALCON10_V 31:0 + +#define NVC1C0_SET_FALCON11 0x052c +#define NVC1C0_SET_FALCON11_V 31:0 + +#define NVC1C0_SET_FALCON12 0x0530 +#define NVC1C0_SET_FALCON12_V 31:0 + +#define NVC1C0_SET_FALCON13 0x0534 +#define NVC1C0_SET_FALCON13_V 31:0 + +#define NVC1C0_SET_FALCON14 0x0538 +#define NVC1C0_SET_FALCON14_V 31:0 + +#define NVC1C0_SET_FALCON15 0x053c +#define NVC1C0_SET_FALCON15_V 31:0 + +#define NVC1C0_SET_FALCON16 0x0540 +#define NVC1C0_SET_FALCON16_V 31:0 + +#define NVC1C0_SET_FALCON17 0x0544 +#define NVC1C0_SET_FALCON17_V 31:0 + +#define NVC1C0_SET_FALCON18 0x0548 +#define NVC1C0_SET_FALCON18_V 31:0 + +#define NVC1C0_SET_FALCON19 0x054c +#define NVC1C0_SET_FALCON19_V 31:0 + +#define NVC1C0_SET_FALCON20 0x0550 +#define NVC1C0_SET_FALCON20_V 31:0 + +#define NVC1C0_SET_FALCON21 0x0554 +#define NVC1C0_SET_FALCON21_V 31:0 + +#define NVC1C0_SET_FALCON22 0x0558 +#define NVC1C0_SET_FALCON22_V 31:0 + +#define NVC1C0_SET_FALCON23 0x055c +#define NVC1C0_SET_FALCON23_V 31:0 + +#define NVC1C0_SET_FALCON24 0x0560 +#define NVC1C0_SET_FALCON24_V 31:0 + +#define NVC1C0_SET_FALCON25 0x0564 +#define NVC1C0_SET_FALCON25_V 31:0 + +#define NVC1C0_SET_FALCON26 0x0568 +#define NVC1C0_SET_FALCON26_V 31:0 + +#define NVC1C0_SET_FALCON27 0x056c +#define NVC1C0_SET_FALCON27_V 31:0 + +#define NVC1C0_SET_FALCON28 0x0570 +#define NVC1C0_SET_FALCON28_V 31:0 + +#define NVC1C0_SET_FALCON29 0x0574 +#define NVC1C0_SET_FALCON29_V 31:0 + +#define NVC1C0_SET_FALCON30 0x0578 +#define NVC1C0_SET_FALCON30_V 31:0 + +#define NVC1C0_SET_FALCON31 0x057c +#define NVC1C0_SET_FALCON31_V 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC1C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC1C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC1C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC1C0_SET_SPARE_NOOP12 0x0f44 +#define NVC1C0_SET_SPARE_NOOP12_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP13 0x0f48 +#define NVC1C0_SET_SPARE_NOOP13_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP14 0x0f4c +#define NVC1C0_SET_SPARE_NOOP14_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP15 0x0f50 +#define NVC1C0_SET_SPARE_NOOP15_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP00 0x1040 +#define NVC1C0_SET_SPARE_NOOP00_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP01 0x1044 +#define NVC1C0_SET_SPARE_NOOP01_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP02 0x1048 +#define NVC1C0_SET_SPARE_NOOP02_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP03 0x104c +#define NVC1C0_SET_SPARE_NOOP03_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP04 0x1050 +#define NVC1C0_SET_SPARE_NOOP04_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP05 0x1054 +#define NVC1C0_SET_SPARE_NOOP05_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP06 0x1058 +#define NVC1C0_SET_SPARE_NOOP06_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP07 0x105c +#define NVC1C0_SET_SPARE_NOOP07_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP08 0x1060 +#define NVC1C0_SET_SPARE_NOOP08_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP09 0x1064 +#define NVC1C0_SET_SPARE_NOOP09_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP10 0x1068 +#define NVC1C0_SET_SPARE_NOOP10_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP11 0x106c +#define NVC1C0_SET_SPARE_NOOP11_V 31:0 + +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC1C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC1C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC1C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC1C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC1C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC1C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC1C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC1C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC1C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC1C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC1C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC1C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC1C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC1C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC1C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC1C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC1C0_SET_PROGRAM_REGION_A 0x1608 +#define NVC1C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 16:0 + +#define NVC1C0_SET_PROGRAM_REGION_B 0x160c +#define NVC1C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC1C0_PIPE_NOP 0x1a2c +#define NVC1C0_PIPE_NOP_V 31:0 + +#define NVC1C0_SET_SPARE00 0x1a30 +#define NVC1C0_SET_SPARE00_V 31:0 + +#define NVC1C0_SET_SPARE01 0x1a34 +#define NVC1C0_SET_SPARE01_V 31:0 + +#define NVC1C0_SET_SPARE02 0x1a38 +#define NVC1C0_SET_SPARE02_V 31:0 + +#define NVC1C0_SET_SPARE03 0x1a3c +#define NVC1C0_SET_SPARE03_V 31:0 + +#define NVC1C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC1C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC1C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC1C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC1C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC1C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC1C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC1C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC1C0_SET_TRAP_HANDLER 0x260c +#define NVC1C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC1C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC1C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC1C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC1C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC1C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC1C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_pascal_compute_b_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc2b0.h b/userspace/sdks/nv570/inc/class/clc2b0.h new file mode 100644 index 0000000..9961f82 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc2b0.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _clc2b0_h_ +#define _clc2b0_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC2B0_VIDEO_DECODER (0x0000C2B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc2b0_h + diff --git a/userspace/sdks/nv570/inc/class/clc2b7.h b/userspace/sdks/nv570/inc/class/clc2b7.h new file mode 100644 index 0000000..4c4e37d --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc2b7.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clc2b7_h +#define clc2b7_h + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC2B7_VIDEO_ENCODER (0x0000C2B7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc2b7_h + diff --git a/userspace/sdks/nv570/inc/class/clc361.h b/userspace/sdks/nv570/inc/class/clc361.h new file mode 100644 index 0000000..daa8841 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc361.h @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc361_h_ +#define _clc361_h_ + +#define VOLTA_USERMODE_A (0xc361) + +#define NVC361 0x0081ffff:0x00810000 +#define NVC361_NV_USERMODE__SIZE 65536 +#define NVC361_TIME_0 0x00000080 +#define NVC361_TIME_1 0x00000084 +#define NVC361_NOTIFY_CHANNEL_PENDING 0x00000090 + +#endif // _clc361_h_ diff --git a/userspace/sdks/nv570/inc/class/clc365.h b/userspace/sdks/nv570/inc/class/clc365.h new file mode 100644 index 0000000..2bbd766 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc365.h @@ -0,0 +1,88 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc365_h_ +#define _clc365_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define ACCESS_COUNTER_NOTIFY_BUFFER (0xc365) + +#define NVC365_NOTIFY_BUF +#define NVC365_NOTIFY_BUF_ENTRY 0x0000001f:0x00000000 +#define NVC365_NOTIFY_BUF_SIZE 32 +#define NVC365_NOTIFY_BUF_ENTRY_TYPE MW((0+0*32):(0*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_TYPE_CPU 0x00000000 +#define NVC365_NOTIFY_BUF_ENTRY_TYPE_GPU 0x00000001 +#define NVC365_NOTIFY_BUF_ENTRY_ADDR_TYPE MW((1+0*32):(0*32+1)) +#define NVC365_NOTIFY_BUF_ENTRY_ADDR_TYPE_GVA 0x00000000 +#define NVC365_NOTIFY_BUF_ENTRY_ADDR_TYPE_GPA 0x00000001 +#define NVC365_NOTIFY_BUF_ENTRY_BANK MW((5+0*32):(0*32+2)) +#define NVC365_NOTIFY_BUF_ENTRY_BANK_0 0x00000000 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_1 0x00000001 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_2 0x00000002 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_3 0x00000003 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_4 0x00000004 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_5 0x00000005 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_6 0x00000006 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_7 0x00000007 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_8 0x00000008 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_9 0x00000009 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_10 0x0000000a +#define NVC365_NOTIFY_BUF_ENTRY_BANK_11 0x0000000b +#define NVC365_NOTIFY_BUF_ENTRY_BANK_12 0x0000000c +#define NVC365_NOTIFY_BUF_ENTRY_BANK_13 0x0000000d +#define NVC365_NOTIFY_BUF_ENTRY_BANK_14 0x0000000e +#define NVC365_NOTIFY_BUF_ENTRY_BANK_15 0x0000000f +#define NVC365_NOTIFY_BUF_ENTRY_APERTURE MW((9+0*32):(0*32+8)) +#define NVC365_NOTIFY_BUF_ENTRY_APERTURE_VID_MEM 0x00000000 +#define NVC365_NOTIFY_BUF_ENTRY_APERTURE_PEER_MEM 0x00000001 +#define NVC365_NOTIFY_BUF_ENTRY_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC365_NOTIFY_BUF_ENTRY_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVC365_NOTIFY_BUF_ENTRY_INST_APERTURE MW((11+0*32):(0*32+10)) +#define NVC365_NOTIFY_BUF_ENTRY_INST_APERTURE_VID_MEM 0x00000000 +#define NVC365_NOTIFY_BUF_ENTRY_INST_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC365_NOTIFY_BUF_ENTRY_INST_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVC365_NOTIFY_BUF_ENTRY_INST_LO MW((31+0*32):(0*32+12)) +#define NVC365_NOTIFY_BUF_ENTRY_INST_HI MW((31+1*32):(1*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_INST MW((31+1*32):(0*32+12)) +#define NVC365_NOTIFY_BUF_ENTRY_ADDR_LO MW((31+2*32):(2*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_ADDR_HI MW((31+3*32):(3*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_ADDR MW((31+3*32):(2*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_SUB_GRANULARITY MW((31+4*32):(4*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_NOTIFY_TAG MW((19+5*32):(5*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_COUNTER_VAL MW((15+6*32):(6*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_PEER_ID MW((2+7*32):(7*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_MMU_ENGINE_ID MW((28+7*32):(7*32+20)) +#define NVC365_NOTIFY_BUF_ENTRY_VALID MW((31+7*32):(7*32+31)) +#define NVC365_NOTIFY_BUF_ENTRY_VALID_FALSE 0x00000000 +#define NVC365_NOTIFY_BUF_ENTRY_VALID_TRUE 0x00000001 +#define NVC365_NOTIFIERS_ACCESS_COUNTER (0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc365_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc369.h b/userspace/sdks/nv570/inc/class/clc369.h new file mode 100644 index 0000000..a73e182 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc369.h @@ -0,0 +1,77 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc369_h_ +#define _clc369_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define MMU_FAULT_BUFFER (0xc369) + +#define NVC369_BUF +#define NVC369_BUF_ENTRY 0x0000001f:0x00000000 +#define NVC369_BUF_SIZE 32 +#define NVC369_BUF_ENTRY_INST_APERTURE MW((9+0*32):(0*32+8)) +#define NVC369_BUF_ENTRY_INST_APERTURE_VID_MEM 0x00000000 +#define NVC369_BUF_ENTRY_INST_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC369_BUF_ENTRY_INST_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVC369_BUF_ENTRY_INST_LO MW((31+0*32):(0*32+12)) +#define NVC369_BUF_ENTRY_INST_HI MW((31+1*32):(1*32+0)) +#define NVC369_BUF_ENTRY_INST MW((31+1*32):(0*32+12)) +#define NVC369_BUF_ENTRY_ADDR_PHYS_APERTURE MW((1+2*32):(2*32+0)) +#define NVC369_BUF_ENTRY_ADDR_LO MW((31+2*32):(2*32+12)) +#define NVC369_BUF_ENTRY_ADDR_HI MW((31+3*32):(3*32+0)) +#define NVC369_BUF_ENTRY_ADDR MW((31+3*32):(2*32+12)) +#define NVC369_BUF_ENTRY_TIMESTAMP_LO MW((31+4*32):(4*32+0)) +#define NVC369_BUF_ENTRY_TIMESTAMP_HI MW((31+5*32):(5*32+0)) +#define NVC369_BUF_ENTRY_TIMESTAMP MW((31+5*32):(4*32+0)) +#define NVC369_BUF_ENTRY_ENGINE_ID MW((8+6*32):(6*32+0)) +#define NVC369_BUF_ENTRY_FAULT_TYPE MW((4+7*32):(7*32+0)) +#define NVC369_BUF_ENTRY_REPLAYABLE_FAULT MW((7+7*32):(7*32+7)) +#define NVC369_BUF_ENTRY_REPLAYABLE_FAULT_FALSE 0x00000000 +#define NVC369_BUF_ENTRY_REPLAYABLE_FAULT_TRUE 0x00000001 +#define NVC369_BUF_ENTRY_CLIENT MW((14+7*32):(7*32+8)) +#define NVC369_BUF_ENTRY_ACCESS_TYPE MW((19+7*32):(7*32+16)) +#define NVC369_BUF_ENTRY_MMU_CLIENT_TYPE MW((20+7*32):(7*32+20)) +#define NVC369_BUF_ENTRY_GPC_ID MW((28+7*32):(7*32+24)) +#define NVC369_BUF_ENTRY_PROTECTED_MODE MW((29+7*32):(7*32+29)) +#define NVC369_BUF_ENTRY_PROTECTED_MODE_FALSE 0x00000000 +#define NVC369_BUF_ENTRY_PROTECTED_MODE_TRUE 0x00000001 +#define NVC369_BUF_ENTRY_REPLAYABLE_FAULT_EN MW((30+7*32):(7*32+30)) +#define NVC369_BUF_ENTRY_REPLAYABLE_FAULT_EN_FALSE 0x00000000 +#define NVC369_BUF_ENTRY_REPLAYABLE_FAULT_EN_TRUE 0x00000001 +#define NVC369_BUF_ENTRY_VALID MW((31+7*32):(7*32+31)) +#define NVC369_BUF_ENTRY_VALID_FALSE 0x00000000 +#define NVC369_BUF_ENTRY_VALID_TRUE 0x00000001 +#define NVC369_NOTIFIER_MMU_FAULT_NON_REPLAYABLE 0 +#define NVC369_NOTIFIER_MMU_FAULT_REPLAYABLE 1 +#define NVC369_NOTIFIER_MMU_FAULT_ERROR 2 +#define NVC369_NOTIFIER_MMU_FAULT_NON_REPLAYABLE_IN_PRIV 3 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc369_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc36f.h b/userspace/sdks/nv570/inc/class/clc36f.h new file mode 100644 index 0000000..cae1c68 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc36f.h @@ -0,0 +1,366 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc36f_h_ +#define _clc36f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class VOLTA_CHANNEL_GPFIFO */ +/* + * Documentation for VOLTA_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + * Note there is no .mfs file for this class. + */ +#define VOLTA_CHANNEL_GPFIFO_A (0x0000C36F) + +#define NVC36F_TYPEDEF VOLTA_CHANNELChannelGPFifoA + +/* dma flow control data structure */ +typedef volatile struct Nvc36fControl_struct { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} Nvc36fControl, VoltaAControlGPFifo; + +/* fields and values */ +#define NVC36F_NUMBER_OF_SUBCHANNELS (8) +#define NVC36F_SET_OBJECT (0x00000000) +#define NVC36F_SET_OBJECT_NVCLASS 15:0 +#define NVC36F_SET_OBJECT_ENGINE 20:16 +#define NVC36F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVC36F_ILLEGAL (0x00000004) +#define NVC36F_ILLEGAL_HANDLE 31:0 +#define NVC36F_NOP (0x00000008) +#define NVC36F_NOP_HANDLE 31:0 +#define NVC36F_SEMAPHOREA (0x00000010) +#define NVC36F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVC36F_SEMAPHOREB (0x00000014) +#define NVC36F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVC36F_SEMAPHOREC (0x00000018) +#define NVC36F_SEMAPHOREC_PAYLOAD 31:0 +#define NVC36F_SEMAPHORED (0x0000001C) +#define NVC36F_SEMAPHORED_OPERATION 4:0 +#define NVC36F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVC36F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVC36F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVC36F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVC36F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 +#define NVC36F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVC36F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVC36F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVC36F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVC36F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVC36F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVC36F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVC36F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVC36F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVC36F_SEMAPHORED_REDUCTION 30:27 +#define NVC36F_SEMAPHORED_REDUCTION_MIN 0x00000000 +#define NVC36F_SEMAPHORED_REDUCTION_MAX 0x00000001 +#define NVC36F_SEMAPHORED_REDUCTION_XOR 0x00000002 +#define NVC36F_SEMAPHORED_REDUCTION_AND 0x00000003 +#define NVC36F_SEMAPHORED_REDUCTION_OR 0x00000004 +#define NVC36F_SEMAPHORED_REDUCTION_ADD 0x00000005 +#define NVC36F_SEMAPHORED_REDUCTION_INC 0x00000006 +#define NVC36F_SEMAPHORED_REDUCTION_DEC 0x00000007 +#define NVC36F_SEMAPHORED_FORMAT 31:31 +#define NVC36F_SEMAPHORED_FORMAT_SIGNED 0x00000000 +#define NVC36F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 +#define NVC36F_NON_STALL_INTERRUPT (0x00000020) +#define NVC36F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVC36F_FB_FLUSH (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR +#define NVC36F_FB_FLUSH_HANDLE 31:0 +// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for +// specifying the page address for a targeted TLB invalidate and the uTLB for +// a targeted REPLAY_CANCEL for UVM. +// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly +// rearranged fields. +#define NVC36F_MEM_OP_A (0x00000028) +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID 6:0 // only relevant for REPLAY_CANCEL_VA_GLOBAL +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11 +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001 +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000 +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12 +#define NVC36F_MEM_OP_B (0x0000002c) +#define NVC36F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0 +#define NVC36F_MEM_OP_C (0x00000030) +#define NVC36F_MEM_OP_C_MEMBAR_TYPE 2:0 +#define NVC36F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000 +#define NVC36F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE 9:7 //only relevant for REPLAY_CANCEL_VA_GLOBAL +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ 0 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE 1 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG 2 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD 3 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK 4 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL 5 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC 6 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL 7 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE +#define NVC36F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG 19:0 +// MEM_OP_D MUST be preceded by MEM_OPs A-C. +#define NVC36F_MEM_OP_D (0x00000034) +#define NVC36F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE +#define NVC36F_MEM_OP_D_OPERATION 31:27 +#define NVC36F_MEM_OP_D_OPERATION_MEMBAR 0x00000005 +#define NVC36F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVC36F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a +#define NVC36F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NVC36F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +// CLEAN_LINES is an alias for Tegra/GPU IP usage +#define NVC36F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e +#define NVC36F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVC36F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVC36F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015 +#define NVC36F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR 0x00000016 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE 1:0 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC 0x00000000 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC 0x00000001 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL 0x00000002 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED 0x00000003 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE 2:2 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC 0x00000000 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC 0x00000001 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK 6:3 +#define NVC36F_SET_REFERENCE (0x00000050) +#define NVC36F_SET_REFERENCE_COUNT 31:0 +#define NVC36F_SEM_ADDR_LO (0x0000005c) +#define NVC36F_SEM_ADDR_LO_OFFSET 31:2 +#define NVC36F_SEM_ADDR_HI (0x00000060) +#define NVC36F_SEM_ADDR_HI_OFFSET 7:0 +#define NVC36F_SEM_PAYLOAD_LO (0x00000064) +#define NVC36F_SEM_PAYLOAD_LO_PAYLOAD 31:0 +#define NVC36F_SEM_PAYLOAD_HI (0x00000068) +#define NVC36F_SEM_PAYLOAD_HI_PAYLOAD 31:0 +#define NVC36F_SEM_EXECUTE (0x0000006c) +#define NVC36F_SEM_EXECUTE_OPERATION 2:0 +#define NVC36F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000 +#define NVC36F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001 +#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ 0x00000002 +#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003 +#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_AND 0x00000004 +#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_NOR 0x00000005 +#define NVC36F_SEM_EXECUTE_OPERATION_REDUCTION 0x00000006 +#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12 +#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS 0x00000000 +#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001 +#define NVC36F_SEM_EXECUTE_RELEASE_WFI 20:20 +#define NVC36F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000 +#define NVC36F_SEM_EXECUTE_RELEASE_WFI_EN 0x00000001 +#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE 24:24 +#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000 +#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT 0x00000001 +#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25 +#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000 +#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001 +#define NVC36F_SEM_EXECUTE_REDUCTION 30:27 +#define NVC36F_SEM_EXECUTE_REDUCTION_IMIN 0x00000000 +#define NVC36F_SEM_EXECUTE_REDUCTION_IMAX 0x00000001 +#define NVC36F_SEM_EXECUTE_REDUCTION_IXOR 0x00000002 +#define NVC36F_SEM_EXECUTE_REDUCTION_IAND 0x00000003 +#define NVC36F_SEM_EXECUTE_REDUCTION_IOR 0x00000004 +#define NVC36F_SEM_EXECUTE_REDUCTION_IADD 0x00000005 +#define NVC36F_SEM_EXECUTE_REDUCTION_INC 0x00000006 +#define NVC36F_SEM_EXECUTE_REDUCTION_DEC 0x00000007 +#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT 31:31 +#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000000 +#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000001 +#define NVC36F_WFI (0x00000078) +#define NVC36F_WFI_SCOPE 0:0 +#define NVC36F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000 +#define NVC36F_WFI_SCOPE_CURRENT_VEID 0x00000000 +#define NVC36F_WFI_SCOPE_ALL 0x00000001 +#define NVC36F_CRC_CHECK (0x0000007c) +#define NVC36F_CRC_CHECK_VALUE 31:0 +#define NVC36F_YIELD (0x00000080) +#define NVC36F_YIELD_OP 1:0 +#define NVC36F_YIELD_OP_NOP 0x00000000 +#define NVC36F_YIELD_OP_RUNLIST_TIMESLICE 0x00000002 +#define NVC36F_YIELD_OP_TSG 0x00000003 +#define NVC36F_CLEAR_FAULTED (0x00000084) +#define NVC36F_CLEAR_FAULTED_CHID 11:0 +#define NVC36F_CLEAR_FAULTED_TYPE 31:31 +#define NVC36F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED 0x00000000 +#define NVC36F_CLEAR_FAULTED_TYPE_ENG_FAULTED 0x00000001 + + +/* GPFIFO entry format */ +#define NVC36F_GP_ENTRY__SIZE 8 +#define NVC36F_GP_ENTRY0_FETCH 0:0 +#define NVC36F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVC36F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVC36F_GP_ENTRY0_GET 31:2 +#define NVC36F_GP_ENTRY0_OPERAND 31:0 +#define NVC36F_GP_ENTRY1_GET_HI 7:0 +#define NVC36F_GP_ENTRY1_PRIV 8:8 +#define NVC36F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NVC36F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NVC36F_GP_ENTRY1_LEVEL 9:9 +#define NVC36F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVC36F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVC36F_GP_ENTRY1_LENGTH 30:10 +#define NVC36F_GP_ENTRY1_SYNC 31:31 +#define NVC36F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVC36F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVC36F_GP_ENTRY1_OPCODE 7:0 +#define NVC36F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVC36F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVC36F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVC36F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVC36F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVC36F_DMA_METHOD_ADDRESS 11:0 +#define NVC36F_DMA_SUBDEVICE_MASK 15:4 +#define NVC36F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVC36F_DMA_TERT_OP 17:16 +#define NVC36F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVC36F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVC36F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVC36F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVC36F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVC36F_DMA_METHOD_COUNT_OLD 28:18 +#define NVC36F_DMA_METHOD_COUNT 28:16 +#define NVC36F_DMA_IMMD_DATA 28:16 +#define NVC36F_DMA_SEC_OP 31:29 +#define NVC36F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVC36F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVC36F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVC36F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVC36F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVC36F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVC36F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVC36F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVC36F_DMA_INCR_ADDRESS 11:0 +#define NVC36F_DMA_INCR_SUBCHANNEL 15:13 +#define NVC36F_DMA_INCR_COUNT 28:16 +#define NVC36F_DMA_INCR_OPCODE 31:29 +#define NVC36F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVC36F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVC36F_DMA_NONINCR_ADDRESS 11:0 +#define NVC36F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVC36F_DMA_NONINCR_COUNT 28:16 +#define NVC36F_DMA_NONINCR_OPCODE 31:29 +#define NVC36F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVC36F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVC36F_DMA_ONEINCR_ADDRESS 11:0 +#define NVC36F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVC36F_DMA_ONEINCR_COUNT 28:16 +#define NVC36F_DMA_ONEINCR_OPCODE 31:29 +#define NVC36F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVC36F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVC36F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVC36F_DMA_IMMD_ADDRESS 11:0 +#define NVC36F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVC36F_DMA_IMMD_DATA 28:16 +#define NVC36F_DMA_IMMD_OPCODE 31:29 +#define NVC36F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVC36F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVC36F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC36F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVC36F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVC36F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC36F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVC36F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC36F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVC36F_DMA_ENDSEG_OPCODE 31:29 +#define NVC36F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVC36F_DMA_ADDRESS 12:2 +#define NVC36F_DMA_SUBCH 15:13 +#define NVC36F_DMA_OPCODE3 17:16 +#define NVC36F_DMA_OPCODE3_NONE (0x00000000) +#define NVC36F_DMA_COUNT 28:18 +#define NVC36F_DMA_OPCODE 31:29 +#define NVC36F_DMA_OPCODE_METHOD (0x00000000) +#define NVC36F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVC36F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc36f_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc36fsw.h b/userspace/sdks/nv570/inc/class/clc36fsw.h new file mode 100644 index 0000000..b54c505 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc36fsw.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* This file is *not* auto-generated. */ + +#ifndef _clc36f_sw_h_ +#define _clc36f_sw_h_ + +#define NVC36F_NOTIFIERS_RC (0) +#define NVC36F_NOTIFIERS_REFCNT (1) +#define NVC36F_NOTIFIERS_NONSTALL (2) +#define NVC36F_NOTIFIERS_EVENTBUFFER (3) +#define NVC36F_NOTIFIERS_IDLECHANNEL (4) +#define NVC36F_NOTIFIERS_ENDCTX (5) +#define NVC36F_NOTIFIERS_SW (6) +#define NVC36F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVC36F_NOTIFIERS_REPLAYABLE_FAULT (8) +#define NVC36F_NOTIFIERS_MAXCOUNT (9) + +/* NvNotification[] fields and values */ +#define NVC36F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVC36F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _clc36f_sw_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc370.h b/userspace/sdks/nv570/inc/class/clc370.h new file mode 100644 index 0000000..762ecf0 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc370.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc370.finn +// + +#include "clc370_notification.h" + +#define NVC370_DISPLAY (0xc370U) /* finn: Evaluated from "NVC370_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NVC370_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc370U) + +typedef struct NVC370_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NVC370_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clc370_notification.h b/userspace/sdks/nv570/inc/class/clc370_notification.h new file mode 100644 index 0000000..c94556e --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc370_notification.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc370_notification_h_ +#define _clc370_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "class/cl5070.h" + +/* event values */ +#define NVC370_NOTIFIERS_SW NV5070_NOTIFIERS_SW +#define NVC370_NOTIFIERS_BEGIN NV5070_NOTIFIERS_MAXCOUNT +#define NVC370_NOTIFIERS_RG_SEM_NOTIFICATION NVC370_NOTIFIERS_BEGIN + (0) +#define NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION NVC370_NOTIFIERS_RG_SEM_NOTIFICATION + (1) +#define NVC370_NOTIFIERS_MAXCOUNT NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION + (1) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc370_notification_h_ */ + diff --git a/userspace/sdks/nv570/inc/class/clc371.h b/userspace/sdks/nv570/inc/class/clc371.h new file mode 100644 index 0000000..e8f9977 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc371.h @@ -0,0 +1,109 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc371_h_ +#define _clc371_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC371_DISP_SF_USER (0x000C371) + +typedef volatile struct _clc371_tag0 { + NvU32 dispSfUserOffset[0x400]; +} _NvC371DispSfUser, NvC371DispSfUserMap; + +#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x00690000-0x00690000+(i)*1024) /* RWX4A */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 4 /* */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER 4:4 /* RWIVF */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_DIS 0x00000000 /* RWI-V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_EN 0x00000001 /* RW--V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE 8:8 /* RWIVF */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_EN 0x00000001 /* RW--V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW 9:9 /* RWIVF */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_STATUS(i) (0x00690004-0x00690000+(i)*1024) /* R--4A */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1 4 /* */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_STATUS_SENT 0:0 /* R--VF */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT 0x00000000 /* R-I-V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x00690008-0x00690000+(i)*1024) /* RWX4A */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 4 /* */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x0069000C-0x00690000+(i)*1024) /* RWX4A */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x00690010-0x00690000+(i)*1024) /* RWX4A */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x00690014-0x00690000+(i)*1024) /* RWX4A */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x00690018-0x00690000+(i)*1024) /* RWX4A */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _clc371_h_ diff --git a/userspace/sdks/nv570/inc/class/clc372sw.h b/userspace/sdks/nv570/inc/class/clc372sw.h new file mode 100644 index 0000000..552ea08 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc372sw.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc372sw_h_ +#define _clc372sw_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC372_DISPLAY_SW (0x0000C372) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc372sw_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc373.h b/userspace/sdks/nv570/inc/class/clc373.h new file mode 100644 index 0000000..c707022 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc373.h @@ -0,0 +1,350 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc373_h_ +#define _clc373_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC373_DISP_CAPABILITIES 0xC373 + +typedef volatile struct _clc373_tag0 { + NvU32 dispCapabilities[0x400]; +} _NvC373DispCapabilities,NvC373DispCapabilities_Map ; + + +#define NVC373_SYS_CAP 0x0 /* RW-4R */ +#define NVC373_SYS_CAP_HEAD0_EXISTS 0:0 /* RWIVF */ +#define NVC373_SYS_CAP_HEAD0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_HEAD1_EXISTS 1:1 /* RWIVF */ +#define NVC373_SYS_CAP_HEAD1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_HEAD2_EXISTS 2:2 /* RWIVF */ +#define NVC373_SYS_CAP_HEAD2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_HEAD3_EXISTS 3:3 /* RWIVF */ +#define NVC373_SYS_CAP_HEAD3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_HEAD4_EXISTS 4:4 /* RWIVF */ +#define NVC373_SYS_CAP_HEAD4_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_HEAD5_EXISTS 5:5 /* RWIVF */ +#define NVC373_SYS_CAP_HEAD5_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_HEAD6_EXISTS 6:6 /* RWIVF */ +#define NVC373_SYS_CAP_HEAD6_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_HEAD7_EXISTS 7:7 /* RWIVF */ +#define NVC373_SYS_CAP_HEAD7_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVC373_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */ +#define NVC373_SYS_CAP_HEAD_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR0_EXISTS 8:8 /* RWIVF */ +#define NVC373_SYS_CAP_SOR0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR1_EXISTS 9:9 /* RWIVF */ +#define NVC373_SYS_CAP_SOR1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR2_EXISTS 10:10 /* RWIVF */ +#define NVC373_SYS_CAP_SOR2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR3_EXISTS 11:11 /* RWIVF */ +#define NVC373_SYS_CAP_SOR3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR4_EXISTS 12:12 /* RWIVF */ +#define NVC373_SYS_CAP_SOR4_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR5_EXISTS 13:13 /* RWIVF */ +#define NVC373_SYS_CAP_SOR5_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR6_EXISTS 14:14 /* RWIVF */ +#define NVC373_SYS_CAP_SOR6_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR7_EXISTS 15:15 /* RWIVF */ +#define NVC373_SYS_CAP_SOR7_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* RWIVF */ +#define NVC373_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */ +#define NVC373_SYS_CAP_SOR_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB 0x4 /* RW-4R */ +#define NVC373_SYS_CAPB_WINDOW0_EXISTS 0:0 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW1_EXISTS 1:1 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW2_EXISTS 2:2 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW3_EXISTS 3:3 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW4_EXISTS 4:4 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW4_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW5_EXISTS 5:5 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW5_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW6_EXISTS 6:6 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW6_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW7_EXISTS 7:7 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW7_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW8_EXISTS 8:8 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW8_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW8_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW8_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW9_EXISTS 9:9 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW9_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW9_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW9_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW10_EXISTS 10:10 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW10_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW10_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW10_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW11_EXISTS 11:11 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW11_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW11_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW11_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW12_EXISTS 12:12 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW12_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW12_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW12_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW13_EXISTS 13:13 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW13_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW13_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW13_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW14_EXISTS 14:14 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW14_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW14_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW14_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW15_EXISTS 15:15 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW15_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW15_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW15_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW16_EXISTS 16:16 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW16_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW16_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW16_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW17_EXISTS 17:17 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW17_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW17_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW17_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW18_EXISTS 18:18 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW18_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW18_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW18_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW19_EXISTS 19:19 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW19_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW19_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW19_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW20_EXISTS 20:20 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW20_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW20_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW20_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW21_EXISTS 21:21 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW21_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW21_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW21_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW22_EXISTS 22:22 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW22_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW22_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW22_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW23_EXISTS 23:23 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW23_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW23_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW23_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW24_EXISTS 24:24 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW24_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW24_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW24_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW25_EXISTS 25:25 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW25_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW25_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW25_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW26_EXISTS 26:26 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW26_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW26_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW26_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW27_EXISTS 27:27 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW27_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW27_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW27_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW28_EXISTS 28:28 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW28_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW28_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW28_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW29_EXISTS 29:29 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW29_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW29_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW29_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW30_EXISTS 30:30 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW30_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW30_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW30_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW31_EXISTS 31:31 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW31_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW31_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW31_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW_EXISTS__SIZE_1 32 /* */ +#define NVC373_SYS_CAPB_WINDOW_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_HEAD_CAPA(i) (0x30+(i)*32) /* RW-4A */ +#define NVC373_HEAD_CAPA__SIZE_1 8 /* */ +#define NVC373_HEAD_CAPA_SCALER 0:0 /* RWIVF */ +#define NVC373_HEAD_CAPA_SCALER_TRUE 0x00000001 /* RW--V */ +#define NVC373_HEAD_CAPA_SCALER_FALSE 0x00000000 /* RW--V */ +#define NVC373_HEAD_CAPA_SCALER_INIT 0x00000000 /* RWI-V */ +#define NVC373_HEAD_CAPA_SCALER_HAS_YUV422 1:1 /* RWIVF */ +#define NVC373_HEAD_CAPA_SCALER_HAS_YUV422_TRUE 0x00000001 /* RW--V */ +#define NVC373_HEAD_CAPA_SCALER_HAS_YUV422_FALSE 0x00000000 /* RW--V */ +#define NVC373_HEAD_CAPA_SCALER_HAS_YUV422_INIT 0x00000000 /* RWI-V */ +#define NVC373_HEAD_CAPA_HSAT 2:2 /* RWIVF */ +#define NVC373_HEAD_CAPA_HSAT_TRUE 0x00000001 /* RW--V */ +#define NVC373_HEAD_CAPA_HSAT_FALSE 0x00000000 /* RW--V */ +#define NVC373_HEAD_CAPA_HSAT_INIT 0x00000000 /* RWI-V */ +#define NVC373_HEAD_CAPA_OCSC 3:3 /* RWIVF */ +#define NVC373_HEAD_CAPA_OCSC_TRUE 0x00000001 /* RW--V */ +#define NVC373_HEAD_CAPA_OCSC_FALSE 0x00000000 /* RW--V */ +#define NVC373_HEAD_CAPA_OCSC_INIT 0x00000000 /* RWI-V */ +#define NVC373_HEAD_CAPA_YUV422 4:4 /* RWIVF */ +#define NVC373_HEAD_CAPA_YUV422_TRUE 0x00000001 /* RW--V */ +#define NVC373_HEAD_CAPA_YUV422_FALSE 0x00000000 /* RW--V */ +#define NVC373_HEAD_CAPA_YUV422_INIT 0x00000000 /* RWI-V */ +#define NVC373_HEAD_CAPA_LUT_TYPE 6:5 /* RWIVF */ +#define NVC373_HEAD_CAPA_LUT_TYPE_NONE 0x00000000 /* RW--V */ +#define NVC373_HEAD_CAPA_LUT_TYPE_257 0x00000001 /* RW--V */ +#define NVC373_HEAD_CAPA_LUT_TYPE_1025 0x00000002 /* RW--V */ +#define NVC373_HEAD_CAPA_LUT_TYPE_INIT 0x00000000 /* RWI-V */ +#define NVC373_HEAD_CAPA_LUT_LOCATION 7:7 /* RWIVF */ +#define NVC373_HEAD_CAPA_LUT_LOCATION_EARLY 0x00000000 /* RW--V */ +#define NVC373_HEAD_CAPA_LUT_LOCATION_LATE 0x00000001 /* RW--V */ +#define NVC373_HEAD_CAPA_LUT_LOCATION_INIT 0x00000000 /* RWI-V */ +#define NVC373_HEAD_CAPD(i) (0x3c+(i)*32) /* RW-4A */ +#define NVC373_HEAD_CAPD__SIZE_1 8 /* */ +#define NVC373_HEAD_CAPD_MAX_PIXELS_2TAP422 15:0 /* RWIUF */ +#define NVC373_HEAD_CAPD_MAX_PIXELS_2TAP422_INIT 0x00000000 /* RWI-V */ +#define NVC373_HEAD_CAPD_MAX_PIXELS_2TAP444 31:16 /* RWIUF */ +#define NVC373_HEAD_CAPD_MAX_PIXELS_2TAP444_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP(i) (0x144+(i)*8) /* RW-4A */ +#define NVC373_SOR_CAP__SIZE_1 8 /* */ +#define NVC373_SOR_CAP_SINGLE_LVDS_18 0:0 /* RWIVF */ +#define NVC373_SOR_CAP_SINGLE_LVDS_18_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_SINGLE_LVDS_24 1:1 /* RWIVF */ +#define NVC373_SOR_CAP_SINGLE_LVDS_24_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_DUAL_LVDS_18 2:2 /* RWIVF */ +#define NVC373_SOR_CAP_DUAL_LVDS_18_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_DUAL_LVDS_24 3:3 /* RWIVF */ +#define NVC373_SOR_CAP_DUAL_LVDS_24_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_SINGLE_TMDS_A 8:8 /* RWIVF */ +#define NVC373_SOR_CAP_SINGLE_TMDS_A_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_SINGLE_TMDS_B 9:9 /* RWIVF */ +#define NVC373_SOR_CAP_SINGLE_TMDS_B_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_DUAL_TMDS 11:11 /* RWIVF */ +#define NVC373_SOR_CAP_DUAL_TMDS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* RWIVF */ +#define NVC373_SOR_CAP_DISPLAY_OVER_PCIE_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_SDI 16:16 /* RWIVF */ +#define NVC373_SOR_CAP_SDI_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_SDI_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_SDI_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_DP_A 24:24 /* RWIVF */ +#define NVC373_SOR_CAP_DP_A_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_DP_A_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_DP_A_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_DP_B 25:25 /* RWIVF */ +#define NVC373_SOR_CAP_DP_B_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_DP_B_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_DP_B_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_DP_INTERLACE 26:26 /* RWIVF */ +#define NVC373_SOR_CAP_DP_INTERLACE_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_DP_8_LANES 27:27 /* RWIVF */ +#define NVC373_SOR_CAP_DP_8_LANES_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CLK_CAP(i) (0x608+(i)*4) /* RW-4A */ +#define NVC373_SOR_CLK_CAP__SIZE_1 8 /* */ +#define NVC373_SOR_CLK_CAP_DP_MAX 7:0 /* RWIUF */ +#define NVC373_SOR_CLK_CAP_DP_MAX_INIT 0x00000036 /* RWI-V */ +#define NVC373_SOR_CLK_CAP_TMDS_MAX 23:16 /* RWIUF */ +#define NVC373_SOR_CLK_CAP_TMDS_MAX_INIT 0x0000003C /* RWI-V */ +#define NVC373_SOR_CLK_CAP_LVDS_MAX 31:24 /* RWIUF */ +#define NVC373_SOR_CLK_CAP_LVDS_MAX_INIT 0x00000000 /* RWI-V */ + +#ifdef __cplusplus +}; +#endif /* extern C */ +#endif //_clc373_h_ diff --git a/userspace/sdks/nv570/inc/class/clc37b.h b/userspace/sdks/nv570/inc/class/clc37b.h new file mode 100644 index 0000000..05f47a2 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc37b.h @@ -0,0 +1,68 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _clC37b_h_ +#define _clC37b_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC37B_WINDOW_IMM_CHANNEL_DMA (0x0000C37B) + +// dma opcode instructions +#define NVC37B_DMA +#define NVC37B_DMA_OPCODE 31:29 +#define NVC37B_DMA_OPCODE_METHOD 0x00000000 +#define NVC37B_DMA_OPCODE_JUMP 0x00000001 +#define NVC37B_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC37B_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC37B_DMA_METHOD_COUNT 27:18 +#define NVC37B_DMA_METHOD_OFFSET 13:2 +#define NVC37B_DMA_DATA 31:0 +#define NVC37B_DMA_DATA_NOP 0x00000000 +#define NVC37B_DMA_JUMP_OFFSET 11:2 +#define NVC37B_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVC37B_PUT (0x00000000) +#define NVC37B_PUT_PTR 9:0 +#define NVC37B_GET (0x00000004) +#define NVC37B_GET_PTR 9:0 +#define NVC37B_UPDATE (0x00000200) +#define NVC37B_UPDATE_RELEASE_ELV 0:0 +#define NVC37B_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC37B_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC37B_UPDATE_INTERLOCK_WITH_WINDOW 1:1 +#define NVC37B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC37B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC37B_SET_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVC37B_SET_POINT_OUT_X 15:0 +#define NVC37B_SET_POINT_OUT_Y 31:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC37b_h diff --git a/userspace/sdks/nv570/inc/class/clc37d.h b/userspace/sdks/nv570/inc/class/clc37d.h new file mode 100644 index 0000000..9ac7050 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc37d.h @@ -0,0 +1,953 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _clC37d_h_ +#define _clC37d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC37D_CORE_CHANNEL_DMA (0x0000C37D) + +#define NV_DISP_NOTIFIER 0x00000000 +#define NV_DISP_NOTIFIER_SIZEOF 0x00000010 +#define NV_DISP_NOTIFIER__0 0x00000000 +#define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFIER__0_FIELD 8:8 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE 9:9 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001 +#define NV_DISP_NOTIFIER__0_R1 15:10 +#define NV_DISP_NOTIFIER__0_R2 23:16 +#define NV_DISP_NOTIFIER__0_R3 29:24 +#define NV_DISP_NOTIFIER__0_STATUS 31:30 +#define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002 +#define NV_DISP_NOTIFIER__1 0x00000001 +#define NV_DISP_NOTIFIER__1_R4 31:0 +#define NV_DISP_NOTIFIER__2 0x00000002 +#define NV_DISP_NOTIFIER__2_TIMESTAMP_LO 31:0 +#define NV_DISP_NOTIFIER__3 0x00000003 +#define NV_DISP_NOTIFIER__3_TIMESTAMP_HI 31:0 + + +// dma opcode instructions +#define NVC37D_DMA +#define NVC37D_DMA_OPCODE 31:29 +#define NVC37D_DMA_OPCODE_METHOD 0x00000000 +#define NVC37D_DMA_OPCODE_JUMP 0x00000001 +#define NVC37D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC37D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC37D_DMA_METHOD_COUNT 27:18 +#define NVC37D_DMA_METHOD_OFFSET 13:2 +#define NVC37D_DMA_DATA 31:0 +#define NVC37D_DMA_DATA_NOP 0x00000000 +#define NVC37D_DMA_JUMP_OFFSET 11:2 +#define NVC37D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// if cap SUPPORT_FLEXIBLE_WIN_MAPPING is FALSE, this define can be used to obtain which head a window is mapped to +#define NVC37D_WINDOW_MAPPED_TO_HEAD(w) ((w)>>1) +#define NVC37D_GET_VALID_WINDOWMASK_FOR_HEAD(h) ((1<<((h)*2)) | (1<<((h)*2+1))) + +// class methods +#define NVC37D_PUT (0x00000000) +#define NVC37D_PUT_PTR 9:0 +#define NVC37D_GET (0x00000004) +#define NVC37D_GET_PTR 9:0 +#define NVC37D_UPDATE (0x00000200) +#define NVC37D_UPDATE_SPECIAL_HANDLING 21:20 +#define NVC37D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NVC37D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NVC37D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NVC37D_UPDATE_SPECIAL_HANDLING_REASON 19:12 +#define NVC37D_UPDATE_INHIBIT_INTERRUPTS 24:24 +#define NVC37D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NVC37D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NVC37D_UPDATE_RELEASE_ELV 0:0 +#define NVC37D_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC37D_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC37D_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC37D_SET_CONTEXT_DMA_NOTIFIER (0x00000208) +#define NVC37D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NVC37D_SET_NOTIFIER_CONTROL (0x0000020C) +#define NVC37D_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC37D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC37D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC37D_SET_NOTIFIER_CONTROL_OFFSET 11:4 +#define NVC37D_SET_NOTIFIER_CONTROL_NOTIFY 12:12 +#define NVC37D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NVC37D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NVC37D_SET_CONTROL (0x00000210) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN(i) ((i)+0):((i)+0) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN__SIZE_1 4 +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN_DISABLE (0x00000000) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN_ENABLE (0x00000001) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN0 0:0 +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN0_DISABLE (0x00000000) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN0_ENABLE (0x00000001) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN1 1:1 +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN1_DISABLE (0x00000000) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN1_ENABLE (0x00000001) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN2 2:2 +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN2_DISABLE (0x00000000) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN2_ENABLE (0x00000001) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN3 3:3 +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN3_DISABLE (0x00000000) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN3_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS (0x00000218) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+0):((i)+0) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS (0x0000021C) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVC37D_GET_RG_SCAN_LINE(b) (0x00000220 + (b)*0x00000004) +#define NVC37D_GET_RG_SCAN_LINE_LINE 15:0 +#define NVC37D_GET_RG_SCAN_LINE_VBLANK 16:16 +#define NVC37D_GET_RG_SCAN_LINE_VBLANK_FALSE (0x00000000) +#define NVC37D_GET_RG_SCAN_LINE_VBLANK_TRUE (0x00000001) +#define NVC37D_SET_GET_BLANKING_CTRL(b) (0x00000240 + (b)*0x00000004) +#define NVC37D_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NVC37D_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NVC37D_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NVC37D_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NVC37D_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NVC37D_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) + +#define NVC37D_PIOR_SET_CONTROL(a) (0x00000280 + (a)*0x00000020) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK 7:0 +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVC37D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NVC37D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NVC37D_PIOR_SET_CONTROL_PROTOCOL_EXT_SDI_SD_ENC (0x00000001) +#define NVC37D_PIOR_SET_CONTROL_PROTOCOL_EXT_SDI_HD_ENC (0x00000002) +#define NVC37D_PIOR_SET_CONTROL_PROTOCOL_DIST_RENDER_OUT (0x00000004) +#define NVC37D_PIOR_SET_CONTROL_PROTOCOL_DIST_RENDER_IN (0x00000005) +#define NVC37D_PIOR_SET_CONTROL_PROTOCOL_DIST_RENDER_INOUT (0x00000006) +#define NVC37D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 16:16 +#define NVC37D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC37D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC37D_PIOR_SET_CUSTOM_REASON(a) (0x00000284 + (a)*0x00000020) +#define NVC37D_PIOR_SET_CUSTOM_REASON_CODE 31:0 +#define NVC37D_PIOR_SET_SW_SPARE_A(a) (0x00000288 + (a)*0x00000020) +#define NVC37D_PIOR_SET_SW_SPARE_A_CODE 31:0 +#define NVC37D_PIOR_SET_SW_SPARE_B(a) (0x0000028C + (a)*0x00000020) +#define NVC37D_PIOR_SET_SW_SPARE_B_CODE 31:0 + +#define NVC37D_SOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK 7:0 +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DSI (0x0000000A) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NVC37D_SOR_SET_CONTROL_DE_SYNC_POLARITY 16:16 +#define NVC37D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC37D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NVC37D_SOR_SET_CUSTOM_REASON(a) (0x00000304 + (a)*0x00000020) +#define NVC37D_SOR_SET_CUSTOM_REASON_CODE 31:0 +#define NVC37D_SOR_SET_SW_SPARE_A(a) (0x00000308 + (a)*0x00000020) +#define NVC37D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NVC37D_SOR_SET_SW_SPARE_B(a) (0x0000030C + (a)*0x00000020) +#define NVC37D_SOR_SET_SW_SPARE_B_CODE 31:0 + +#define NVC37D_WINDOW_SET_CONTROL(a) (0x00001000 + (a)*0x00000080) +#define NVC37D_WINDOW_SET_CONTROL_OWNER 3:0 +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD(i) (0x00000000 +(i)) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD__SIZE_1 8 +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD0 (0x00000000) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD1 (0x00000001) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD2 (0x00000002) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD3 (0x00000003) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD4 (0x00000004) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD5 (0x00000005) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD6 (0x00000006) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD7 (0x00000007) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_NONE (0x0000000F) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0x00000080) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a) (0x00001008 + (a)*0x00000080) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR(a) (0x0000100C + (a)*0x00000080) +#define NVC37D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVC37D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a) (0x00001010 + (a)*0x00000080) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_MAX_PIXELS_FETCHED_PER_LINE 14:0 +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT 17:16 +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT_USAGE_NONE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT_USAGE_257 (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT_USAGE_1025 (0x00000002) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS 22:20 +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED 24:24 +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) + +#define NVC37D_HEAD_SET_PROCAMP(a) (0x00002000 + (a)*0x00000400) +#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003) +#define NVC37D_HEAD_SET_PROCAMP_CHROMA_LPF 3:3 +#define NVC37D_HEAD_SET_PROCAMP_CHROMA_LPF_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_PROCAMP_CHROMA_LPF_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_PROCAMP_SAT_COS 15:4 +#define NVC37D_HEAD_SET_PROCAMP_SAT_SINE 27:16 +#define NVC37D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 28:28 +#define NVC37D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NVC37D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NVC37D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 29:29 +#define NVC37D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL 31:30 +#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL_AUTO (0x00000000) +#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL_VIDEO (0x00000001) +#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL_GRAPHICS (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00002004 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 2:2 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 3:3 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 7:4 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000004) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000005) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000006) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000007) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000008) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 24:24 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 23:12 +#define NVC37D_HEAD_SET_CONTROL(a) (0x00002008 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTROL_STRUCTURE 1:0 +#define NVC37D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE 2:2 +#define NVC37D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_NORMAL (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 11:10 +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 8:4 +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 15:12 +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 23:22 +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 20:16 +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN 28:24 +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000004) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000005) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000006) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000007) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000008) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000009) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000B) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000C) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000D) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000E) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000F) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x00000010) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NVC37D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NVC37D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x0000200C + (a)*0x00000400) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC37D_HEAD_SET_PIXEL_REORDER_CONTROL(a) (0x00002010 + (a)*0x00000400) +#define NVC37D_HEAD_SET_PIXEL_REORDER_CONTROL_BANK_WIDTH 13:0 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00002014 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVC37D_HEAD_SET_DITHER_CONTROL(a) (0x00002018 + (a)*0x00000400) +#define NVC37D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NVC37D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS 5:4 +#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_6_BITS (0x00000000) +#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_8_BITS (0x00000001) +#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_10_BITS (0x00000002) +#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_12_BITS (0x00000003) +#define NVC37D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE 2:2 +#define NVC37D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE 10:8 +#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NVC37D_HEAD_SET_DITHER_CONTROL_PHASE 13:12 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x0000201C + (a)*0x00000400) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 0:0 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING 4:4 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 9:8 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NVC37D_HEAD_SET_DISPLAY_ID(a,b) (0x00002020 + (a)*0x00000400 + (b)*0x00000004) +#define NVC37D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00002028 + (a)*0x00000400) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC37D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR(a) (0x0000202C + (a)*0x00000400) +#define NVC37D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVC37D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS(a) (0x00002030 + (a)*0x00000400) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR 2:0 +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_NONE (0x00000000) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W32_H32 (0x00000001) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W64_H64 (0x00000002) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W128_H128 (0x00000003) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W256_H256 (0x00000004) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT 5:4 +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED 8:8 +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVC37D_HEAD_SET_STALL_LOCK(a) (0x00002034 + (a)*0x00000400) +#define NVC37D_HEAD_SET_STALL_LOCK_ENABLE 0:0 +#define NVC37D_HEAD_SET_STALL_LOCK_ENABLE_FALSE (0x00000000) +#define NVC37D_HEAD_SET_STALL_LOCK_ENABLE_TRUE (0x00000001) +#define NVC37D_HEAD_SET_STALL_LOCK_MODE 2:2 +#define NVC37D_HEAD_SET_STALL_LOCK_MODE_CONTINUOUS (0x00000000) +#define NVC37D_HEAD_SET_STALL_LOCK_MODE_ONE_SHOT (0x00000001) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN 8:4 +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC37D_HEAD_SET_STALL_LOCK_UNSTALL_MODE 12:12 +#define NVC37D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_CRASH_LOCK (0x00000000) +#define NVC37D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_LINE_LOCK (0x00000001) +#define NVC37D_HEAD_SET_STALL_LOCK_TEPOLARITY 14:14 +#define NVC37D_HEAD_SET_STALL_LOCK_TEPOLARITY_POSITIVE_TRUE (0x00000000) +#define NVC37D_HEAD_SET_STALL_LOCK_TEPOLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC37D_HEAD_SET_LOCK_CHAIN(a) (0x00002044 + (a)*0x00000400) +#define NVC37D_HEAD_SET_LOCK_CHAIN_POSITION 3:0 +#define NVC37D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x00002048 + (a)*0x00000400) +#define NVC37D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NVC37D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NVC37D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x0000204C + (a)*0x00000400) +#define NVC37D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NVC37D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NVC37D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x00002058 + (a)*0x00000400) +#define NVC37D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NVC37D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NVC37D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x0000205C + (a)*0x00000400) +#define NVC37D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NVC37D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NVC37D_HEAD_SET_DESKTOP_COLOR(a) (0x00002060 + (a)*0x00000400) +#define NVC37D_HEAD_SET_DESKTOP_COLOR_ALPHA 7:0 +#define NVC37D_HEAD_SET_DESKTOP_COLOR_RED 15:8 +#define NVC37D_HEAD_SET_DESKTOP_COLOR_GREEN 23:16 +#define NVC37D_HEAD_SET_DESKTOP_COLOR_BLUE 31:24 +#define NVC37D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000400) +#define NVC37D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NVC37D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NVC37D_HEAD_SET_RASTER_SYNC_END(a) (0x00002068 + (a)*0x00000400) +#define NVC37D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NVC37D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NVC37D_HEAD_SET_RASTER_BLANK_END(a) (0x0000206C + (a)*0x00000400) +#define NVC37D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NVC37D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NVC37D_HEAD_SET_RASTER_BLANK_START(a) (0x00002070 + (a)*0x00000400) +#define NVC37D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NVC37D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NVC37D_HEAD_SET_OVERSCAN_COLOR(a) (0x00002078 + (a)*0x00000400) +#define NVC37D_HEAD_SET_OVERSCAN_COLOR_RED_CR 9:0 +#define NVC37D_HEAD_SET_OVERSCAN_COLOR_GREEN_Y 19:10 +#define NVC37D_HEAD_SET_OVERSCAN_COLOR_BLUE_CB 29:20 +#define NVC37D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR(a) (0x0000207C + (a)*0x00000400) +#define NVC37D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_RED_CR 9:0 +#define NVC37D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_GREEN_Y 19:10 +#define NVC37D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_BLUE_CB 29:20 +#define NVC37D_HEAD_SET_HDMI_CTRL(a) (0x00002080 + (a)*0x00000400) +#define NVC37D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NVC37D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NVC37D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NVC37D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NVC37D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NVC37D_HEAD_SET_CONTEXT_DMA_CURSOR(a,b) (0x00002088 + (a)*0x00000400 + (b)*0x00000004) +#define NVC37D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0 +#define NVC37D_HEAD_SET_OFFSET_CURSOR(a,b) (0x00002090 + (a)*0x00000400 + (b)*0x00000004) +#define NVC37D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0 +#define NVC37D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x00002098 + (a)*0x00000400) +#define NVC37D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 0:0 +#define NVC37D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NVC37D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_CURSOR(a) (0x0000209C + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_FORMAT 7:0 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE 9:8 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 19:12 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 27:20 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA 29:28 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_NONE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_SRGB (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_YUV8_10 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_YUV12 (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION(a) (0x000020A0 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_K1 7:0 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT 11:8 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT 15:12 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_ZERO (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE 16:16 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_BLEND (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_XOR (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT(a) (0x000020A4 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE 1:0 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_257 (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_1025 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE 5:4 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_UNITY (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_XRBIAS (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_XVYCC (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE 9:8 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE_INDEX (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE_INTERPOLATE (0x00000001) +#define NVC37D_HEAD_SET_OFFSET_OUTPUT_LUT(a) (0x000020A8 + (a)*0x00000400) +#define NVC37D_HEAD_SET_OFFSET_OUTPUT_LUT_ORIGIN 31:0 +#define NVC37D_HEAD_SET_CONTEXT_DMA_OUTPUT_LUT(a) (0x000020AC + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTEXT_DMA_OUTPUT_LUT_HANDLE 31:0 +#define NVC37D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00002180 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NVC37D_HEAD_SET_CRC_CONTROL(a) (0x00002184 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 4:0 +#define NVC37D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 8:8 +#define NVC37D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NVC37D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC 19:12 +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_NONE (0x00000000) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SF (0x00000030) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR__SIZE_1 8 +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR0 (0x00000050) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR1 (0x00000051) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR2 (0x00000052) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR3 (0x00000053) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR4 (0x00000054) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR5 (0x00000055) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR6 (0x00000056) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR7 (0x00000057) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR(i) (0x00000060 +(i)) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR__SIZE_1 4 +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR0 (0x00000060) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR1 (0x00000061) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR2 (0x00000062) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR3 (0x00000063) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC 27:20 +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_NONE (0x00000000) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SF (0x00000030) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR__SIZE_1 8 +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR0 (0x00000050) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR1 (0x00000051) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR2 (0x00000052) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR3 (0x00000053) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR4 (0x00000054) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR5 (0x00000055) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR6 (0x00000056) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR7 (0x00000057) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR(i) (0x00000060 +(i)) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR__SIZE_1 4 +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR0 (0x00000060) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR1 (0x00000061) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR2 (0x00000062) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR3 (0x00000063) +#define NVC37D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 9:9 +#define NVC37D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_PRESENT_CONTROL(a) (0x0000218C + (a)*0x00000400) +#define NVC37D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 0:0 +#define NVC37D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NVC37D_HEAD_SET_SW_SPARE_A(a) (0x00002194 + (a)*0x00000400) +#define NVC37D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NVC37D_HEAD_SET_SW_SPARE_B(a) (0x00002198 + (a)*0x00000400) +#define NVC37D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NVC37D_HEAD_SET_SW_SPARE_C(a) (0x0000219C + (a)*0x00000400) +#define NVC37D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NVC37D_HEAD_SET_SW_SPARE_D(a) (0x000021A0 + (a)*0x00000400) +#define NVC37D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NVC37D_HEAD_SET_DISPLAY_RATE(a) (0x000021A8 + (a)*0x00000400) +#define NVC37D_HEAD_SET_DISPLAY_RATE_RUN_MODE 0:0 +#define NVC37D_HEAD_SET_DISPLAY_RATE_RUN_MODE_CONTINUOUS (0x00000000) +#define NVC37D_HEAD_SET_DISPLAY_RATE_RUN_MODE_ONE_SHOT (0x00000001) +#define NVC37D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_INTERVAL 25:4 +#define NVC37D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH 2:2 +#define NVC37D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_MIN_FRAME_IDLE(a) (0x00002218 + (a)*0x00000400) +#define NVC37D_HEAD_SET_MIN_FRAME_IDLE_LEADING_RASTER_LINES 14:0 +#define NVC37D_HEAD_SET_MIN_FRAME_IDLE_TRAILING_RASTER_LINES 30:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC37d_h diff --git a/userspace/sdks/nv570/inc/class/clc37dcrcnotif.h b/userspace/sdks/nv570/inc/class/clc37dcrcnotif.h new file mode 100644 index 0000000..bf0e9a2 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc37dcrcnotif.h @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __clc37dcrcnotif_h__ +#define __clc37dcrcnotif_h__ +/* This file is autogenerated. Do not edit */ + +#define NVC37D_NOTIFIER_CRC_STATUS_0 0x00000000 +#define NVC37D_NOTIFIER_CRC_STATUS_0_DONE 0:0 +#define NVC37D_NOTIFIER_CRC_STATUS_0_DONE_FALSE 0x00000000 +#define NVC37D_NOTIFIER_CRC_STATUS_0_DONE_TRUE 0x00000001 +#define NVC37D_NOTIFIER_CRC_STATUS_0_COMPOSITOR_OVERFLOW 3:3 +#define NVC37D_NOTIFIER_CRC_STATUS_0_COMPOSITOR_OVERFLOW_FALSE 0x00000000 +#define NVC37D_NOTIFIER_CRC_STATUS_0_COMPOSITOR_OVERFLOW_TRUE 0x00000001 +#define NVC37D_NOTIFIER_CRC_STATUS_0_RG_OVERFLOW 4:4 +#define NVC37D_NOTIFIER_CRC_STATUS_0_RG_OVERFLOW_FALSE 0x00000000 +#define NVC37D_NOTIFIER_CRC_STATUS_0_RG_OVERFLOW_TRUE 0x00000001 +#define NVC37D_NOTIFIER_CRC_STATUS_0_PRIMARY_OUTPUT_OVERFLOW 5:5 +#define NVC37D_NOTIFIER_CRC_STATUS_0_PRIMARY_OUTPUT_OVERFLOW_FALSE 0x00000000 +#define NVC37D_NOTIFIER_CRC_STATUS_0_PRIMARY_OUTPUT_OVERFLOW_TRUE 0x00000001 +#define NVC37D_NOTIFIER_CRC_STATUS_0_COUNT 27:16 +#define NVC37D_NOTIFIER_CRC_CRC_ENTRY0_11 0x0000000B +#define NVC37D_NOTIFIER_CRC_CRC_ENTRY0_11_COMPOSITOR_CRC 31:0 +#define NVC37D_NOTIFIER_CRC_CRC_ENTRY0_12 0x0000000C +#define NVC37D_NOTIFIER_CRC_CRC_ENTRY0_12_RG_CRC 31:0 +#define NVC37D_NOTIFIER_CRC_CRC_ENTRY0_13 0x0000000D +#define NVC37D_NOTIFIER_CRC_CRC_ENTRY0_13_PRIMARY_OUTPUT_CRC 31:0 +#define NVC37D_NOTIFIER_CRC_CRC_ENTRY1_21 0x00000015 + +#endif // __clc37dcrcnotif_h__ diff --git a/userspace/sdks/nv570/inc/class/clc37dswspare.h b/userspace/sdks/nv570/inc/class/clc37dswspare.h new file mode 100644 index 0000000..44b21a8 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc37dswspare.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc37d_sw_spare_h_ +#define _clc37d_sw_spare_h_ + +/* This file is *not* auto-generated. */ + +#define NVC37D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF 1:0 +#define NVC37D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF_NO_PREF (0x00000000) +#define NVC37D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF_QSYNC (0x00000001) + +#define NVC37D_HEAD_SET_SW_SPARE_A_DISABLE_MID_FRAME_AND_DWCF_WATERMARK 2:2 +#define NVC37D_HEAD_SET_SW_SPARE_A_DISABLE_MID_FRAME_AND_DWCF_WATERMARK_FALSE (0x00000000) +#define NVC37D_HEAD_SET_SW_SPARE_A_DISABLE_MID_FRAME_AND_DWCF_WATERMARK_TRUE (0x00000001) + +#endif // _clc37d_sw_spare_h_ diff --git a/userspace/sdks/nv570/inc/class/clc37e.h b/userspace/sdks/nv570/inc/class/clc37e.h new file mode 100644 index 0000000..f46929a --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc37e.h @@ -0,0 +1,498 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _clC37e_h_ +#define _clC37e_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC37E_WINDOW_CHANNEL_DMA (0x0000C37E) + +// dma opcode instructions +#define NVC37E_DMA +#define NVC37E_DMA_OPCODE 31:29 +#define NVC37E_DMA_OPCODE_METHOD 0x00000000 +#define NVC37E_DMA_OPCODE_JUMP 0x00000001 +#define NVC37E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC37E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC37E_DMA_METHOD_COUNT 27:18 +#define NVC37E_DMA_METHOD_OFFSET 13:2 +#define NVC37E_DMA_DATA 31:0 +#define NVC37E_DMA_DATA_NOP 0x00000000 +#define NVC37E_DMA_JUMP_OFFSET 11:2 +#define NVC37E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVC37E_PUT (0x00000000) +#define NVC37E_PUT_PTR 9:0 +#define NVC37E_GET (0x00000004) +#define NVC37E_GET_PTR 9:0 +#define NVC37E_UPDATE (0x00000200) +#define NVC37E_UPDATE_RELEASE_ELV 0:0 +#define NVC37E_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC37E_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC37E_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM 12:12 +#define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE (0x00000000) +#define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE (0x00000001) +#define NVC37E_GET_LINE (0x00000208) +#define NVC37E_GET_LINE_LINE 15:0 +#define NVC37E_SET_SEMAPHORE_CONTROL (0x0000020C) +#define NVC37E_SET_SEMAPHORE_CONTROL_OFFSET 7:0 +#define NVC37E_SET_SEMAPHORE_ACQUIRE (0x00000210) +#define NVC37E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NVC37E_SET_SEMAPHORE_RELEASE (0x00000214) +#define NVC37E_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NVC37E_SET_CONTEXT_DMA_SEMAPHORE (0x00000218) +#define NVC37E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NVC37E_SET_CONTEXT_DMA_NOTIFIER (0x0000021C) +#define NVC37E_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NVC37E_SET_NOTIFIER_CONTROL (0x00000220) +#define NVC37E_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC37E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC37E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC37E_SET_NOTIFIER_CONTROL_OFFSET 11:4 +#define NVC37E_SET_SIZE (0x00000224) +#define NVC37E_SET_SIZE_WIDTH 15:0 +#define NVC37E_SET_SIZE_HEIGHT 31:16 +#define NVC37E_SET_STORAGE (0x00000228) +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC37E_SET_STORAGE_MEMORY_LAYOUT 4:4 +#define NVC37E_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC37E_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC37E_SET_PARAMS (0x0000022C) +#define NVC37E_SET_PARAMS_FORMAT 7:0 +#define NVC37E_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NVC37E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F) +#define NVC37E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NVC37E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC37E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E) +#define NVC37E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC37E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6) +#define NVC37E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NVC37E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9) +#define NVC37E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NVC37E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NVC37E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NVC37E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024) +#define NVC37E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NVC37E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NVC37E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NVC37E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028) +#define NVC37E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029) +#define NVC37E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035) +#define NVC37E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036) +#define NVC37E_SET_PARAMS_FORMAT_Y8___U8V8_N422R (0x00000037) +#define NVC37E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038) +#define NVC37E_SET_PARAMS_FORMAT_Y8___U8___V8_N444 (0x0000003A) +#define NVC37E_SET_PARAMS_FORMAT_Y8___U8___V8_N420 (0x0000003B) +#define NVC37E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055) +#define NVC37E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056) +#define NVC37E_SET_PARAMS_FORMAT_Y10___U10V10_N422R (0x00000057) +#define NVC37E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058) +#define NVC37E_SET_PARAMS_FORMAT_Y10___U10___V10_N444 (0x0000005A) +#define NVC37E_SET_PARAMS_FORMAT_Y10___U10___V10_N420 (0x0000005B) +#define NVC37E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075) +#define NVC37E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076) +#define NVC37E_SET_PARAMS_FORMAT_Y12___U12V12_N422R (0x00000077) +#define NVC37E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078) +#define NVC37E_SET_PARAMS_FORMAT_Y12___U12___V12_N444 (0x0000007A) +#define NVC37E_SET_PARAMS_FORMAT_Y12___U12___V12_N420 (0x0000007B) +#define NVC37E_SET_PARAMS_COLOR_SPACE 9:8 +#define NVC37E_SET_PARAMS_COLOR_SPACE_RGB (0x00000000) +#define NVC37E_SET_PARAMS_COLOR_SPACE_YUV_601 (0x00000001) +#define NVC37E_SET_PARAMS_COLOR_SPACE_YUV_709 (0x00000002) +#define NVC37E_SET_PARAMS_COLOR_SPACE_YUV_2020 (0x00000003) +#define NVC37E_SET_PARAMS_INPUT_RANGE 13:12 +#define NVC37E_SET_PARAMS_INPUT_RANGE_BYPASS (0x00000000) +#define NVC37E_SET_PARAMS_INPUT_RANGE_LIMITED (0x00000001) +#define NVC37E_SET_PARAMS_INPUT_RANGE_FULL (0x00000002) +#define NVC37E_SET_PARAMS_UNDERREPLICATE 16:16 +#define NVC37E_SET_PARAMS_UNDERREPLICATE_DISABLE (0x00000000) +#define NVC37E_SET_PARAMS_UNDERREPLICATE_ENABLE (0x00000001) +#define NVC37E_SET_PARAMS_DE_GAMMA 21:20 +#define NVC37E_SET_PARAMS_DE_GAMMA_NONE (0x00000000) +#define NVC37E_SET_PARAMS_DE_GAMMA_SRGB (0x00000001) +#define NVC37E_SET_PARAMS_DE_GAMMA_YUV8_10 (0x00000002) +#define NVC37E_SET_PARAMS_DE_GAMMA_YUV12 (0x00000003) +#define NVC37E_SET_PARAMS_CSC 17:17 +#define NVC37E_SET_PARAMS_CSC_DISABLE (0x00000000) +#define NVC37E_SET_PARAMS_CSC_ENABLE (0x00000001) +#define NVC37E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18 +#define NVC37E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000) +#define NVC37E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001) +#define NVC37E_SET_PARAMS_SWAP_UV 19:19 +#define NVC37E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000) +#define NVC37E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001) +#define NVC37E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004) +#define NVC37E_SET_PLANAR_STORAGE_PITCH 12:0 +#define NVC37E_SET_CONTEXT_DMA_ISO(b) (0x00000240 + (b)*0x00000004) +#define NVC37E_SET_CONTEXT_DMA_ISO_HANDLE 31:0 +#define NVC37E_SET_OFFSET(b) (0x00000260 + (b)*0x00000004) +#define NVC37E_SET_OFFSET_ORIGIN 31:0 +#define NVC37E_SET_PROCESSING (0x00000280) +#define NVC37E_SET_PROCESSING_USE_GAIN_OFFSETS 0:0 +#define NVC37E_SET_PROCESSING_USE_GAIN_OFFSETS_DISABLE (0x00000000) +#define NVC37E_SET_PROCESSING_USE_GAIN_OFFSETS_ENABLE (0x00000001) +#define NVC37E_SET_CONVERSION_RED (0x00000284) +#define NVC37E_SET_CONVERSION_RED_GAIN 15:0 +#define NVC37E_SET_CONVERSION_RED_OFFSET 31:16 +#define NVC37E_SET_CONVERSION_GREEN (0x00000288) +#define NVC37E_SET_CONVERSION_GREEN_GAIN 15:0 +#define NVC37E_SET_CONVERSION_GREEN_OFFSET 31:16 +#define NVC37E_SET_CONVERSION_BLUE (0x0000028C) +#define NVC37E_SET_CONVERSION_BLUE_GAIN 15:0 +#define NVC37E_SET_CONVERSION_BLUE_OFFSET 31:16 +#define NVC37E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004) +#define NVC37E_SET_POINT_IN_X 15:0 +#define NVC37E_SET_POINT_IN_Y 31:16 +#define NVC37E_SET_SIZE_IN (0x00000298) +#define NVC37E_SET_SIZE_IN_WIDTH 14:0 +#define NVC37E_SET_SIZE_IN_HEIGHT 30:16 +#define NVC37E_SET_SIZE_OUT (0x000002A4) +#define NVC37E_SET_SIZE_OUT_WIDTH 14:0 +#define NVC37E_SET_SIZE_OUT_HEIGHT 30:16 +#define NVC37E_SET_CONTROL_INPUT_SCALER (0x000002A8) +#define NVC37E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVC37E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVC37E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVC37E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVC37E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVC37E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVC37E_SET_INPUT_SCALER_COEFF_VALUE (0x000002AC) +#define NVC37E_SET_INPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVC37E_SET_INPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVC37E_SET_CONTROL_INPUT_LUT (0x000002B0) +#define NVC37E_SET_CONTROL_INPUT_LUT_SIZE 1:0 +#define NVC37E_SET_CONTROL_INPUT_LUT_SIZE_SIZE_257 (0x00000000) +#define NVC37E_SET_CONTROL_INPUT_LUT_SIZE_SIZE_1025 (0x00000002) +#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE 5:4 +#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE_UNITY (0x00000000) +#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE_XRBIAS (0x00000001) +#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE_XVYCC (0x00000002) +#define NVC37E_SET_CONTROL_INPUT_LUT_OUTPUT_MODE 9:8 +#define NVC37E_SET_CONTROL_INPUT_LUT_OUTPUT_MODE_INDEX (0x00000000) +#define NVC37E_SET_CONTROL_INPUT_LUT_OUTPUT_MODE_INTERPOLATE (0x00000001) +#define NVC37E_SET_OFFSET_INPUT_LUT (0x000002B4) +#define NVC37E_SET_OFFSET_INPUT_LUT_ORIGIN 31:0 +#define NVC37E_SET_CONTEXT_DMA_INPUT_LUT (0x000002B8) +#define NVC37E_SET_CONTEXT_DMA_INPUT_LUT_HANDLE 31:0 +#define NVC37E_SET_CSC_RED2RED (0x000002BC) +#define NVC37E_SET_CSC_RED2RED_COEFF 18:0 +#define NVC37E_SET_CSC_GREEN2RED (0x000002C0) +#define NVC37E_SET_CSC_GREEN2RED_COEFF 18:0 +#define NVC37E_SET_CSC_BLUE2RED (0x000002C4) +#define NVC37E_SET_CSC_BLUE2RED_COEFF 18:0 +#define NVC37E_SET_CSC_CONSTANT2RED (0x000002C8) +#define NVC37E_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NVC37E_SET_CSC_RED2GREEN (0x000002CC) +#define NVC37E_SET_CSC_RED2GREEN_COEFF 18:0 +#define NVC37E_SET_CSC_GREEN2GREEN (0x000002D0) +#define NVC37E_SET_CSC_GREEN2GREEN_COEFF 18:0 +#define NVC37E_SET_CSC_BLUE2GREEN (0x000002D4) +#define NVC37E_SET_CSC_BLUE2GREEN_COEFF 18:0 +#define NVC37E_SET_CSC_CONSTANT2GREEN (0x000002D8) +#define NVC37E_SET_CSC_CONSTANT2GREEN_COEFF 18:0 +#define NVC37E_SET_CSC_RED2BLUE (0x000002DC) +#define NVC37E_SET_CSC_RED2BLUE_COEFF 18:0 +#define NVC37E_SET_CSC_GREEN2BLUE (0x000002E0) +#define NVC37E_SET_CSC_GREEN2BLUE_COEFF 18:0 +#define NVC37E_SET_CSC_BLUE2BLUE (0x000002E4) +#define NVC37E_SET_CSC_BLUE2BLUE_COEFF 18:0 +#define NVC37E_SET_CSC_CONSTANT2BLUE (0x000002E8) +#define NVC37E_SET_CSC_CONSTANT2BLUE_COEFF 18:0 +#define NVC37E_SET_COMPOSITION_CONTROL (0x000002EC) +#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0 +#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000) +#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001) +#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002) +#define NVC37E_SET_COMPOSITION_CONTROL_DEPTH 11:4 +#define NVC37E_SET_COMPOSITION_CONSTANT_ALPHA (0x000002F0) +#define NVC37E_SET_COMPOSITION_CONSTANT_ALPHA_K1 7:0 +#define NVC37E_SET_COMPOSITION_CONSTANT_ALPHA_K2 15:8 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT (0x000002F4) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC37E_SET_KEY_ALPHA (0x000002F8) +#define NVC37E_SET_KEY_ALPHA_MIN 15:0 +#define NVC37E_SET_KEY_ALPHA_MAX 31:16 +#define NVC37E_SET_KEY_RED_CR (0x000002FC) +#define NVC37E_SET_KEY_RED_CR_MIN 15:0 +#define NVC37E_SET_KEY_RED_CR_MAX 31:16 +#define NVC37E_SET_KEY_GREEN_Y (0x00000300) +#define NVC37E_SET_KEY_GREEN_Y_MIN 15:0 +#define NVC37E_SET_KEY_GREEN_Y_MAX 31:16 +#define NVC37E_SET_KEY_BLUE_CB (0x00000304) +#define NVC37E_SET_KEY_BLUE_CB_MIN 15:0 +#define NVC37E_SET_KEY_BLUE_CB_MAX 31:16 +#define NVC37E_SET_PRESENT_CONTROL (0x00000308) +#define NVC37E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NVC37E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4 +#define NVC37E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NVC37E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NVC37E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8 +#define NVC37E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000) +#define NVC37E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001) +#define NVC37E_SET_PRESENT_CONTROL_STEREO_MODE 13:12 +#define NVC37E_SET_PRESENT_CONTROL_STEREO_MODE_MONO (0x00000000) +#define NVC37E_SET_PRESENT_CONTROL_STEREO_MODE_PAIR_FLIP (0x00000001) +#define NVC37E_SET_PRESENT_CONTROL_STEREO_MODE_AT_ANY_FRAME (0x00000002) +#define NVC37E_SET_TIMESTAMP_ORIGIN_LO (0x00000340) +#define NVC37E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NVC37E_SET_TIMESTAMP_ORIGIN_HI (0x00000344) +#define NVC37E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NVC37E_SET_UPDATE_TIMESTAMP_LO (0x00000348) +#define NVC37E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NVC37E_SET_UPDATE_TIMESTAMP_HI (0x0000034C) +#define NVC37E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NVC37E_SET_INTERLOCK_FLAGS (0x00000370) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 0:0 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+1):((i)+1) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 1:1 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 2:2 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 3:3 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 4:4 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 5:5 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 6:6 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 7:7 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 8:8 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS (0x00000374) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC37e_h diff --git a/userspace/sdks/nv570/inc/class/clc397.h b/userspace/sdks/nv570/inc/class/clc397.h new file mode 100644 index 0000000..2122c75 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc397.h @@ -0,0 +1,4219 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_volta_a_h_ +#define _cl_volta_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl volta_a */ + +#include "nvtypes.h" + +#define VOLTA_A 0xC397 + +#define NVC397_SET_OBJECT 0x0000 +#define NVC397_SET_OBJECT_CLASS_ID 15:0 +#define NVC397_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC397_NO_OPERATION 0x0100 +#define NVC397_NO_OPERATION_V 31:0 + +#define NVC397_SET_NOTIFY_A 0x0104 +#define NVC397_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC397_SET_NOTIFY_B 0x0108 +#define NVC397_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC397_NOTIFY 0x010c +#define NVC397_NOTIFY_TYPE 31:0 +#define NVC397_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC397_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC397_WAIT_FOR_IDLE 0x0110 +#define NVC397_WAIT_FOR_IDLE_V 31:0 + +#define NVC397_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC397_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC397_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC397_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC397_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC397_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC397_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC397_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC397_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC397_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC397_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC397_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC397_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC397_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC397_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC397_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC397_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC397_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC397_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC397_SEND_GO_IDLE 0x013c +#define NVC397_SEND_GO_IDLE_V 31:0 + +#define NVC397_PM_TRIGGER 0x0140 +#define NVC397_PM_TRIGGER_V 31:0 + +#define NVC397_PM_TRIGGER_WFI 0x0144 +#define NVC397_PM_TRIGGER_WFI_V 31:0 + +#define NVC397_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC397_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC397_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC397_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC397_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC397_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC397_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC397_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC397_LINE_LENGTH_IN 0x0180 +#define NVC397_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC397_LINE_COUNT 0x0184 +#define NVC397_LINE_COUNT_VALUE 31:0 + +#define NVC397_OFFSET_OUT_UPPER 0x0188 +#define NVC397_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC397_OFFSET_OUT 0x018c +#define NVC397_OFFSET_OUT_VALUE 31:0 + +#define NVC397_PITCH_OUT 0x0190 +#define NVC397_PITCH_OUT_VALUE 31:0 + +#define NVC397_SET_DST_BLOCK_SIZE 0x0194 +#define NVC397_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC397_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC397_SET_DST_WIDTH 0x0198 +#define NVC397_SET_DST_WIDTH_V 31:0 + +#define NVC397_SET_DST_HEIGHT 0x019c +#define NVC397_SET_DST_HEIGHT_V 31:0 + +#define NVC397_SET_DST_DEPTH 0x01a0 +#define NVC397_SET_DST_DEPTH_V 31:0 + +#define NVC397_SET_DST_LAYER 0x01a4 +#define NVC397_SET_DST_LAYER_V 31:0 + +#define NVC397_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC397_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC397_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC397_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC397_LAUNCH_DMA 0x01b0 +#define NVC397_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC397_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC397_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC397_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC397_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC397_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC397_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC397_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC397_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC397_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC397_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC397_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC397_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC397_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC397_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC397_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC397_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC397_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC397_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC397_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC397_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC397_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC397_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC397_LOAD_INLINE_DATA 0x01b4 +#define NVC397_LOAD_INLINE_DATA_V 31:0 + +#define NVC397_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC397_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC397_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC397_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC397_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC397_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC397_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC397_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC397_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC397_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC397_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC397_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC397_RUN_DS_NOW 0x0200 +#define NVC397_RUN_DS_NOW_V 31:0 + +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC397_SET_GS_MODE 0x0208 +#define NVC397_SET_GS_MODE_TYPE 0:0 +#define NVC397_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVC397_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVC397_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC397_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC397_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC397_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC397_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC397_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_GS_DM_FIFO 0x0214 +#define NVC397_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC397_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC397_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC397_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC397_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC397_INVALIDATE_SHADER_CACHES 0x021c +#define NVC397_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC397_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC397_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC397_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC397_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC397_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC397_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC397_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC397_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC397_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC397_SET_INSTANCE_COUNT 0x0220 +#define NVC397_SET_INSTANCE_COUNT_V 31:0 + +#define NVC397_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVC397_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVC397_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC397_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVC397_SET_MME_VERSION 0x0234 +#define NVC397_SET_MME_VERSION_MAJOR 7:0 + +#define NVC397_INCREMENT_SYNC_POINT 0x02c8 +#define NVC397_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC397_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC397_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC397_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC397_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC397_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC397_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC397_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC397_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVC397_DECOMPRESS_SURFACE 0x02e0 +#define NVC397_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC397_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC397_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC397_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC397_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC397_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC397_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC397_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC397_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC397_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC397_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC397_SET_ZCULL_SUBREGION 0x02e8 +#define NVC397_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC397_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC397_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC397_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC397_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC397_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC397_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC397_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC397_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC397_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC397_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC397_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC397_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC397_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC397_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC397_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC397_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC397_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC397_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC397_DRAW_ZERO_INDEX 0x0304 +#define NVC397_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC397_SET_L1_CONFIGURATION 0x0308 +#define NVC397_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC397_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC397_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC397_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC397_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC397_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC397_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC397_SET_SPA_VERSION 0x0310 +#define NVC397_SET_SPA_VERSION_MINOR 7:0 +#define NVC397_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC397_SET_SNAP_GRID_LINE 0x0318 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC397_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC397_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC397_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC397_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC397_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC397_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC397_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC397_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC397_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC397_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC397_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC397_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC397_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC397_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC397_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC397_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC397_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC397_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC397_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC397_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC397_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC397_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC397_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC397_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC397_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC397_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC397_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC397_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC397_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC397_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC397_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC397_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC397_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC397_RESERVED_TG07 0x033c +#define NVC397_RESERVED_TG07_V 0:0 + +#define NVC397_RESERVED_TG08 0x0340 +#define NVC397_RESERVED_TG08_V 0:0 + +#define NVC397_RESERVED_TG09 0x0344 +#define NVC397_RESERVED_TG09_V 0:0 + +#define NVC397_RESERVED_TG10 0x0348 +#define NVC397_RESERVED_TG10_V 0:0 + +#define NVC397_RESERVED_TG11 0x034c +#define NVC397_RESERVED_TG11_V 0:0 + +#define NVC397_RESERVED_TG12 0x0350 +#define NVC397_RESERVED_TG12_V 0:0 + +#define NVC397_RESERVED_TG13 0x0354 +#define NVC397_RESERVED_TG13_V 0:0 + +#define NVC397_RESERVED_TG14 0x0358 +#define NVC397_RESERVED_TG14_V 0:0 + +#define NVC397_RESERVED_TG15 0x035c +#define NVC397_RESERVED_TG15_V 0:0 + +#define NVC397_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC397_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC397_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC397_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC397_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC397_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC397_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC397_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC397_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC397_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC397_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC397_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC397_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC397_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC397_SET_RASTER_ENABLE 0x037c +#define NVC397_SET_RASTER_ENABLE_V 0:0 +#define NVC397_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC397_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC397_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC397_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC397_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC397_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC397_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC397_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC397_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC397_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC397_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVC397_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVC397_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVC397_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVC397_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVC397_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVC397_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVC397_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVC397_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC397_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC397_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC397_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC397_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC397_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC397_SET_RASTER_INPUT 0x0740 +#define NVC397_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC397_SET_STREAM_OUTPUT 0x0744 +#define NVC397_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC397_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC397_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC397_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC397_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC397_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC397_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC397_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC397_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC397_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC397_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC397_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC397_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC397_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC397_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC397_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC397_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC397_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC397_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC397_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC397_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC397_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC397_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC397_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC397_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC397_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVC397_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC397_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC397_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC397_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC397_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC397_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC397_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC397_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC397_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC397_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC397_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC397_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC397_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC397_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC397_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC397_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC397_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC397_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC397_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC397_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC397_SET_ZCULL_STORAGE_B 0x07ec +#define NVC397_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC397_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC397_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC397_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC397_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC397_SET_ZT_READ_ONLY 0x07f8 +#define NVC397_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC397_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC397_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC397_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC397_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC397_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC397_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC397_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC397_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC397_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC397_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC397_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC397_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC397_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC397_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC397_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC397_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC397_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC397_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC397_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC397_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC397_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC397_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC397_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC397_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC397_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC397_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC397_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC397_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC397_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC397_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC397_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC397_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC397_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC397_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC397_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC397_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC397_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC397_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC397_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC397_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC397_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC397_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC397_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC397_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC397_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC397_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC397_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC397_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC397_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC397_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC397_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC397_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC397_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC397_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC397_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC397_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC397_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC397_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC397_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC397_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC397_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC397_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC397_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC397_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC397_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC397_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC397_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC397_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC397_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC397_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC397_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC397_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC397_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC397_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC397_SET_STATISTICS_COUNTER 0x0d68 +#define NVC397_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC397_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC397_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC397_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC397_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC397_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC397_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC397_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC397_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC397_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC397_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC397_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC397_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC397_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC397_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC397_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC397_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVC397_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC397_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC397_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC397_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC397_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC397_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC397_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC397_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC397_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC397_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC397_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC397_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC397_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC397_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC397_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC397_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC397_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC397_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC397_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC397_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC397_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC397_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC397_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC397_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC397_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC397_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC397_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC397_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC397_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC397_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC397_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC397_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC397_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC397_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC397_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC397_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC397_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC397_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC397_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC397_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC397_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC397_SET_POLY_SMOOTH 0x0db4 +#define NVC397_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC397_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC397_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC397_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC397_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC397_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC397_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC397_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC397_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC397_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_PATCH 0x0dcc +#define NVC397_SET_PATCH_SIZE 7:0 + +#define NVC397_SET_ITERATED_BLEND 0x0dd0 +#define NVC397_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC397_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC397_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC397_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC397_SET_ZCULL_CRITERION 0x0dd8 +#define NVC397_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC397_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC397_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC397_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC397_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC397_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC397_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC397_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC397_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC397_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC397_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC397_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC397_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC397_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC397_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC397_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC397_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC397_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC397_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC397_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC397_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC397_SET_SCISSOR_ENABLE_V 0:0 +#define NVC397_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC397_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC397_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC397_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC397_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC397_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC397_SET_VPC_PERF_KNOB 0x0f14 +#define NVC397_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC397_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC397_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC397_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC397_PM_LOCAL_TRIGGER 0x0f18 +#define NVC397_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC397_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC397_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC397_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC397_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC397_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC397_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC397_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC397_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC397_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC397_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC397_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC397_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC397_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC397_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC397_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC397_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC397_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC397_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC397_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC397_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC397_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC397_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC397_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC397_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC397_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC397_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC397_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC397_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC397_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC397_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC397_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC397_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC397_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC397_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC397_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC397_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC397_SET_SAMPLE_MASK 0x0fa4 +#define NVC397_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC397_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC397_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC397_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC397_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC397_SET_CT_MRT_ENABLE 0x0fac +#define NVC397_SET_CT_MRT_ENABLE_V 0:0 +#define NVC397_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC397_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC397_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC397_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC397_SET_TIR 0x0fb4 +#define NVC397_SET_TIR_MODE 1:0 +#define NVC397_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC397_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC397_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC397_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC397_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC397_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC397_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC397_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC397_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC397_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC397_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC397_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC397_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC397_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC397_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC397_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC397_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC397_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC397_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC397_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_TIR_MODULATION 0x0fd4 +#define NVC397_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC397_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC397_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC397_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC397_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC397_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC397_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC397_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC397_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC397_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC397_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC397_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC397_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC397_SET_ZT_A 0x0fe0 +#define NVC397_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_ZT_B 0x0fe4 +#define NVC397_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_ZT_FORMAT 0x0fe8 +#define NVC397_SET_ZT_FORMAT_V 4:0 +#define NVC397_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC397_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC397_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC397_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC397_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC397_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC397_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC397_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC397_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC397_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC397_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC397_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC397_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC397_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC397_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC397_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC397_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC397_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC397_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC397_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC397_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC397_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC397_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC397_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC397_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC397_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC397_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC397_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC397_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC397_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC397_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC397_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC397_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC397_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC397_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC397_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC397_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC397_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC397_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC397_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC397_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC397_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC397_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC397_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC397_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC397_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD02 0x102c +#define NVC397_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC397_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC397_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC397_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC397_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC397_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC397_SET_SPARE_NOOP01 0x1044 +#define NVC397_SET_SPARE_NOOP01_V 31:0 + +#define NVC397_SET_SPARE_NOOP02 0x1048 +#define NVC397_SET_SPARE_NOOP02_V 31:0 + +#define NVC397_SET_SPARE_NOOP03 0x104c +#define NVC397_SET_SPARE_NOOP03_V 31:0 + +#define NVC397_SET_SPARE_NOOP04 0x1050 +#define NVC397_SET_SPARE_NOOP04_V 31:0 + +#define NVC397_SET_SPARE_NOOP05 0x1054 +#define NVC397_SET_SPARE_NOOP05_V 31:0 + +#define NVC397_SET_SPARE_NOOP06 0x1058 +#define NVC397_SET_SPARE_NOOP06_V 31:0 + +#define NVC397_SET_SPARE_NOOP07 0x105c +#define NVC397_SET_SPARE_NOOP07_V 31:0 + +#define NVC397_SET_SPARE_NOOP08 0x1060 +#define NVC397_SET_SPARE_NOOP08_V 31:0 + +#define NVC397_SET_SPARE_NOOP09 0x1064 +#define NVC397_SET_SPARE_NOOP09_V 31:0 + +#define NVC397_SET_SPARE_NOOP10 0x1068 +#define NVC397_SET_SPARE_NOOP10_V 31:0 + +#define NVC397_SET_SPARE_NOOP11 0x106c +#define NVC397_SET_SPARE_NOOP11_V 31:0 + +#define NVC397_SET_SPARE_NOOP12 0x1070 +#define NVC397_SET_SPARE_NOOP12_V 31:0 + +#define NVC397_SET_SPARE_NOOP13 0x1074 +#define NVC397_SET_SPARE_NOOP13_V 31:0 + +#define NVC397_SET_SPARE_NOOP14 0x1078 +#define NVC397_SET_SPARE_NOOP14_V 31:0 + +#define NVC397_SET_SPARE_NOOP15 0x107c +#define NVC397_SET_SPARE_NOOP15_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC397_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC397_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC397_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC397_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC397_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC397_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC397_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC397_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC397_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC397_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC397_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC397_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC397_UNBIND_ALL 0x10f4 +#define NVC397_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC397_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC397_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC397_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC397_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC397_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC397_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC397_NO_OPERATION_DATA_HI 0x110c +#define NVC397_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC397_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC397_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC397_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC397_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC397_PM_TRIGGER_END 0x1114 +#define NVC397_PM_TRIGGER_END_V 31:0 + +#define NVC397_SET_VERTEX_ID_BASE 0x1118 +#define NVC397_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC397_SET_STENCIL_COMPRESSION 0x111c +#define NVC397_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC397_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC397_SET_TIR_CONTROL 0x1130 +#define NVC397_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC397_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC397_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC397_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC397_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC397_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC397_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC397_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC397_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 + +#define NVC397_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC397_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC397_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC397_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC397_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC397_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC397_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC397_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC397_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC397_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC397_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC397_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC397_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC397_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC397_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC397_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC397_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC397_FLUSH_PENDING_WRITES 0x1144 +#define NVC397_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC397_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC397_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC397_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC397_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC397_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC397_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC397_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC397_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC397_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC397_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC397_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC397_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC397_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC397_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC397_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC397_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC397_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC397_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC397_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC397_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC397_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC397_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_SCREEN_STATE_MASK 0x1204 +#define NVC397_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC397_SET_ZT_SPARSE 0x1208 +#define NVC397_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC397_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC397_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC397_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC397_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC397_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_SET_CT_SELECT 0x121c +#define NVC397_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC397_SET_CT_SELECT_TARGET0 6:4 +#define NVC397_SET_CT_SELECT_TARGET1 9:7 +#define NVC397_SET_CT_SELECT_TARGET2 12:10 +#define NVC397_SET_CT_SELECT_TARGET3 15:13 +#define NVC397_SET_CT_SELECT_TARGET4 18:16 +#define NVC397_SET_CT_SELECT_TARGET5 21:19 +#define NVC397_SET_CT_SELECT_TARGET6 24:22 +#define NVC397_SET_CT_SELECT_TARGET7 27:25 + +#define NVC397_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC397_SET_ZT_SIZE_A 0x1228 +#define NVC397_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC397_SET_ZT_SIZE_B 0x122c +#define NVC397_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC397_SET_ZT_SIZE_C 0x1230 +#define NVC397_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC397_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC397_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC397_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC397_SET_SAMPLER_BINDING 0x1234 +#define NVC397_SET_SAMPLER_BINDING_V 0:0 +#define NVC397_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC397_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC397_DRAW_AUTO 0x123c +#define NVC397_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC397_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC397_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC397_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC397_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC397_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC397_SET_BACK_END_COPY_A 0x1264 +#define NVC397_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC397_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC397_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC397_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC397_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BACK_END_COPY_B 0x1268 +#define NVC397_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC397_SET_BACK_END_COPY_C 0x126c +#define NVC397_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC397_SET_BACK_END_COPY_D 0x1270 +#define NVC397_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC397_SET_BACK_END_COPY_E 0x1274 +#define NVC397_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC397_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC397_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVC397_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC397_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC397_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC397_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC397_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC397_CLEAR_ZCULL_REGION 0x12c8 +#define NVC397_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC397_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC397_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC397_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC397_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC397_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC397_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC397_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC397_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC397_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC397_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC397_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC397_SET_DEPTH_TEST 0x12cc +#define NVC397_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC397_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC397_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_FILL_MODE 0x12d0 +#define NVC397_SET_FILL_MODE_V 31:0 +#define NVC397_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC397_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC397_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC397_SET_SHADE_MODE 0x12d4 +#define NVC397_SET_SHADE_MODE_V 31:0 +#define NVC397_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC397_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC397_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC397_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC397_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC397_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC397_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC397_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC397_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC397_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC397_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC397_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_DEPTH_WRITE 0x12e8 +#define NVC397_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC397_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_ALPHA_TEST 0x12ec +#define NVC397_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC397_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC397_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC397_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC397_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC397_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC397_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC397_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC397_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC397_D3D_SET_CULL_MODE 0x1308 +#define NVC397_D3D_SET_CULL_MODE_V 31:0 +#define NVC397_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC397_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC397_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC397_SET_DEPTH_FUNC 0x130c +#define NVC397_SET_DEPTH_FUNC_V 31:0 +#define NVC397_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC397_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC397_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC397_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC397_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC397_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC397_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC397_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC397_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC397_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC397_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC397_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC397_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC397_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC397_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC397_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC397_SET_ALPHA_REF 0x1310 +#define NVC397_SET_ALPHA_REF_V 31:0 + +#define NVC397_SET_ALPHA_FUNC 0x1314 +#define NVC397_SET_ALPHA_FUNC_V 31:0 +#define NVC397_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC397_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC397_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC397_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC397_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC397_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC397_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC397_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC397_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC397_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC397_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC397_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC397_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC397_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC397_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC397_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC397_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC397_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC397_SET_BLEND_CONST_RED 0x131c +#define NVC397_SET_BLEND_CONST_RED_V 31:0 + +#define NVC397_SET_BLEND_CONST_GREEN 0x1320 +#define NVC397_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC397_SET_BLEND_CONST_BLUE 0x1324 +#define NVC397_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC397_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC397_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC397_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC397_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC397_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC397_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC397_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC397_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC397_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC397_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BLEND_COLOR_OP 0x1340 +#define NVC397_SET_BLEND_COLOR_OP_V 31:0 +#define NVC397_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC397_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC397_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC397_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC397_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC397_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC397_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC397_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC397_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC397_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_BLEND_ALPHA_OP 0x134c +#define NVC397_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC397_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC397_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC397_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC397_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC397_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC397_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC397_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC397_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC397_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC397_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC397_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC397_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC397_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC397_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC397_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BLEND(i) (0x1360+(i)*4) +#define NVC397_SET_BLEND_ENABLE 0:0 +#define NVC397_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_STENCIL_TEST 0x1380 +#define NVC397_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC397_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_STENCIL_OP_FAIL 0x1384 +#define NVC397_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC397_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC397_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC397_SET_STENCIL_OP_ZPASS 0x138c +#define NVC397_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC397_SET_STENCIL_FUNC 0x1390 +#define NVC397_SET_STENCIL_FUNC_V 31:0 +#define NVC397_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC397_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC397_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC397_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC397_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC397_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC397_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC397_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC397_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC397_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC397_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC397_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC397_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC397_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC397_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC397_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC397_SET_STENCIL_FUNC_REF 0x1394 +#define NVC397_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC397_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC397_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC397_SET_STENCIL_MASK 0x139c +#define NVC397_SET_STENCIL_MASK_V 7:0 + +#define NVC397_SET_DRAW_AUTO_START 0x13a4 +#define NVC397_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC397_SET_PS_SATURATE 0x13a8 +#define NVC397_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC397_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC397_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC397_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC397_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC397_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC397_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC397_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC397_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC397_SET_WINDOW_ORIGIN 0x13ac +#define NVC397_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC397_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC397_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC397_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC397_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC397_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC397_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC397_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC397_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC397_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC397_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC397_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC397_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC397_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC397_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC397_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC397_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC397_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC397_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC397_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC397_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC397_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC397_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC397_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC397_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC397_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC397_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC397_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC397_STORE_ZCULL 0x1464 +#define NVC397_STORE_ZCULL_V 0:0 + +#define NVC397_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC397_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC397_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC397_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC397_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC397_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC397_LOAD_ZCULL 0x1500 +#define NVC397_LOAD_ZCULL_V 0:0 + +#define NVC397_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC397_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC397_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC397_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC397_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC397_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC397_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC397_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC397_SET_USER_CLIP_ENABLE 0x1510 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC397_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC397_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC397_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_POINT_SIZE 0x1518 +#define NVC397_SET_POINT_SIZE_V 31:0 + +#define NVC397_SET_ZCULL_STATS 0x151c +#define NVC397_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC397_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_POINT_SPRITE 0x1520 +#define NVC397_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC397_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC397_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC397_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC397_CLEAR_REPORT_VALUE 0x1530 +#define NVC397_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC397_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC397_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC397_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC397_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC397_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC397_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVC397_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC397_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC397_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_ZT_SELECT 0x1538 +#define NVC397_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC397_SET_RENDER_ENABLE_A 0x1550 +#define NVC397_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_RENDER_ENABLE_B 0x1554 +#define NVC397_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_RENDER_ENABLE_C 0x1558 +#define NVC397_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC397_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC397_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC397_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC397_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC397_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC397_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC397_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC397_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC397_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC397_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC397_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC397_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC397_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC397_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC397_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC397_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_TEX_HEADER_POOL_C 0x157c +#define NVC397_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC397_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC397_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC397_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC397_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC397_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC397_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC397_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC397_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC397_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC397_SET_SRGB_WRITE 0x15b8 +#define NVC397_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC397_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_DEPTH_BIAS 0x15bc +#define NVC397_SET_DEPTH_BIAS_V 31:0 + +#define NVC397_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC397_SET_RT_LAYER 0x15cc +#define NVC397_SET_RT_LAYER_V 15:0 +#define NVC397_SET_RT_LAYER_CONTROL 16:16 +#define NVC397_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC397_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC397_SET_ANTI_ALIAS 0x15d0 +#define NVC397_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC397_SET_EDGE_FLAG 0x15e4 +#define NVC397_SET_EDGE_FLAG_V 0:0 +#define NVC397_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC397_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC397_DRAW_INLINE_INDEX 0x15e8 +#define NVC397_DRAW_INLINE_INDEX_V 31:0 + +#define NVC397_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC397_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC397_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC397_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC397_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC397_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC397_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC397_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC397_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC397_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC397_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC397_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC397_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC397_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC397_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC397_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC397_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC397_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC397_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC397_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC397_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC397_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC397_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC397_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC397_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC397_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC397_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC397_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC397_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC397_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC397_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC397_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC397_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC397_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC397_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC397_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC397_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC397_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC397_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC397_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC397_END 0x1614 +#define NVC397_END_V 0:0 + +#define NVC397_BEGIN 0x1618 +#define NVC397_BEGIN_OP 15:0 +#define NVC397_BEGIN_OP_POINTS 0x00000000 +#define NVC397_BEGIN_OP_LINES 0x00000001 +#define NVC397_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC397_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC397_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC397_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC397_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC397_BEGIN_OP_QUADS 0x00000007 +#define NVC397_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC397_BEGIN_OP_POLYGON 0x00000009 +#define NVC397_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC397_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC397_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_BEGIN_OP_PATCH 0x0000000E +#define NVC397_BEGIN_PRIMITIVE_ID 24:24 +#define NVC397_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC397_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC397_BEGIN_INSTANCE_ID 27:26 +#define NVC397_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC397_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC397_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC397_BEGIN_SPLIT_MODE 30:29 +#define NVC397_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC397_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC397_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC397_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC397_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVC397_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC397_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_VERTEX_ID_COPY 0x161c +#define NVC397_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC397_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC397_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC397_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC397_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC397_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC397_LOAD_PRIMITIVE_ID 0x1624 +#define NVC397_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC397_SET_SHADER_BASED_CULL 0x162c +#define NVC397_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC397_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC397_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC397_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_CLASS_VERSION 0x1638 +#define NVC397_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC397_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC397_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC397_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC397_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC397_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC397_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC397_SET_DA_OUTPUT 0x164c +#define NVC397_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC397_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC397_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC397_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC397_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_POINT_CENTER_MODE 0x165c +#define NVC397_SET_POINT_CENTER_MODE_V 31:0 +#define NVC397_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC397_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC397_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC397_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC397_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC397_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC397_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC397_SET_LINE_STIPPLE 0x166c +#define NVC397_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC397_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC397_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC397_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC397_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC397_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC397_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC397_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC397_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC397_SET_PROVOKING_VERTEX 0x1684 +#define NVC397_SET_PROVOKING_VERTEX_V 0:0 +#define NVC397_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC397_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC397_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC397_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC397_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_POLYGON_STIPPLE 0x168c +#define NVC397_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC397_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_SHADER_CONTROL 0x1690 +#define NVC397_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC397_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC397_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC397_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC397_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC397_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC397_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC397_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC397_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC397_CHECK_CLASS_VERSION 0x16a0 +#define NVC397_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC397_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC397_SET_SPH_VERSION 0x16a4 +#define NVC397_SET_SPH_VERSION_CURRENT 15:0 +#define NVC397_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC397_CHECK_SPH_VERSION 0x16a8 +#define NVC397_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC397_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC397_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC397_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC397_SET_AAM_VERSION 0x1790 +#define NVC397_SET_AAM_VERSION_CURRENT 15:0 +#define NVC397_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC397_CHECK_AAM_VERSION 0x1794 +#define NVC397_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC397_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC397_SET_ZT_LAYER 0x179c +#define NVC397_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC397_SET_INDEX_BUFFER_A 0x17c8 +#define NVC397_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC397_SET_INDEX_BUFFER_B 0x17cc +#define NVC397_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC397_SET_INDEX_BUFFER_C 0x17d0 +#define NVC397_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC397_SET_INDEX_BUFFER_D 0x17d4 +#define NVC397_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC397_SET_INDEX_BUFFER_E 0x17d8 +#define NVC397_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC397_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC397_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC397_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC397_SET_INDEX_BUFFER_F 0x17dc +#define NVC397_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC397_DRAW_INDEX_BUFFER 0x17e0 +#define NVC397_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC397_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC397_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC397_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC397_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC397_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC397_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC397_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC397_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC397_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC397_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC397_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC397_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC397_OGL_SET_CULL 0x1918 +#define NVC397_OGL_SET_CULL_ENABLE 0:0 +#define NVC397_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC397_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC397_OGL_SET_FRONT_FACE 0x191c +#define NVC397_OGL_SET_FRONT_FACE_V 31:0 +#define NVC397_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC397_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC397_OGL_SET_CULL_FACE 0x1920 +#define NVC397_OGL_SET_CULL_FACE_V 31:0 +#define NVC397_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC397_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC397_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC397_SET_VIEWPORT_PIXEL 0x1924 +#define NVC397_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC397_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC397_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC397_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC397_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC397_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC397_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE 17:16 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_USE_FIELD_MIN_Z_ZERO_MAX_Z_ONE 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MIN_Z_MAX_Z 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_ZERO_ONE 0x00000002 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MINUS_INF_PLUS_INF 0x00000003 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC397_SET_USER_CLIP_OP 0x1940 +#define NVC397_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC397_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC397_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC397_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC397_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC397_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC397_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC397_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC397_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC397_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC397_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC397_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC397_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC397_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC397_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC397_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC397_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC397_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC397_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC397_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC397_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC397_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC397_INVALIDATE_ZCULL 0x1958 +#define NVC397_INVALIDATE_ZCULL_V 31:0 +#define NVC397_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC397_SET_ZCULL 0x1968 +#define NVC397_SET_ZCULL_Z_ENABLE 0:0 +#define NVC397_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC397_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_ZCULL_BOUNDS 0x196c +#define NVC397_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC397_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC397_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC397_ZCULL_SYNC 0x1978 +#define NVC397_ZCULL_SYNC_V 31:0 + +#define NVC397_SET_CLIP_ID_TEST 0x197c +#define NVC397_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC397_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC397_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC397_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC397_SET_CLIP_ID 0x1984 +#define NVC397_SET_CLIP_ID_V 31:0 + +#define NVC397_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC397_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC397_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC397_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC397_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC397_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC397_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC397_SET_LOGIC_OP 0x19c4 +#define NVC397_SET_LOGIC_OP_ENABLE 0:0 +#define NVC397_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC397_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC397_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC397_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC397_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC397_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC397_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC397_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC397_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC397_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC397_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC397_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC397_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC397_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC397_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC397_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC397_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC397_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC397_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC397_SET_Z_COMPRESSION 0x19cc +#define NVC397_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC397_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC397_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC397_CLEAR_SURFACE 0x19d0 +#define NVC397_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC397_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC397_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC397_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC397_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC397_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC397_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC397_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC397_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC397_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC397_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC397_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC397_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC397_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC397_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC397_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC397_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC397_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC397_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC397_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC397_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC397_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC397_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC397_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC397_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC397_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC397_PIPE_NOP 0x1a2c +#define NVC397_PIPE_NOP_V 31:0 + +#define NVC397_SET_SPARE00 0x1a30 +#define NVC397_SET_SPARE00_V 31:0 + +#define NVC397_SET_SPARE01 0x1a34 +#define NVC397_SET_SPARE01_V 31:0 + +#define NVC397_SET_SPARE02 0x1a38 +#define NVC397_SET_SPARE02_V 31:0 + +#define NVC397_SET_SPARE03 0x1a3c +#define NVC397_SET_SPARE03_V 31:0 + +#define NVC397_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC397_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC397_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC397_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC397_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC397_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC397_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC397_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC397_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC397_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC397_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC397_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC397_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC397_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC397_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC397_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC397_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC397_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC397_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC397_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC397_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC397_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC397_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC397_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC397_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC397_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC397_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC397_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC397_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC397_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC397_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC397_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC397_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC397_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVC397_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVC397_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVC397_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVC397_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVC397_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVC397_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVC397_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVC397_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC397_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC397_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC397_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC397_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC397_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC397_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC397_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC397_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC397_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC397_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC397_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC397_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC397_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC397_SET_PIPELINE_REGISTER_COUNT_V 8:0 + +#define NVC397_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC397_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC397_SET_PIPELINE_PROGRAM_ADDRESS_A(j) (0x2014+(j)*64) +#define NVC397_SET_PIPELINE_PROGRAM_ADDRESS_A_UPPER 7:0 + +#define NVC397_SET_PIPELINE_PROGRAM_ADDRESS_B(j) (0x2018+(j)*64) +#define NVC397_SET_PIPELINE_PROGRAM_ADDRESS_B_LOWER 31:0 + +#define NVC397_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVC397_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVC397_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC397_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC397_SET_FALCON00 0x2300 +#define NVC397_SET_FALCON00_V 31:0 + +#define NVC397_SET_FALCON01 0x2304 +#define NVC397_SET_FALCON01_V 31:0 + +#define NVC397_SET_FALCON02 0x2308 +#define NVC397_SET_FALCON02_V 31:0 + +#define NVC397_SET_FALCON03 0x230c +#define NVC397_SET_FALCON03_V 31:0 + +#define NVC397_SET_FALCON04 0x2310 +#define NVC397_SET_FALCON04_V 31:0 + +#define NVC397_SET_FALCON05 0x2314 +#define NVC397_SET_FALCON05_V 31:0 + +#define NVC397_SET_FALCON06 0x2318 +#define NVC397_SET_FALCON06_V 31:0 + +#define NVC397_SET_FALCON07 0x231c +#define NVC397_SET_FALCON07_V 31:0 + +#define NVC397_SET_FALCON08 0x2320 +#define NVC397_SET_FALCON08_V 31:0 + +#define NVC397_SET_FALCON09 0x2324 +#define NVC397_SET_FALCON09_V 31:0 + +#define NVC397_SET_FALCON10 0x2328 +#define NVC397_SET_FALCON10_V 31:0 + +#define NVC397_SET_FALCON11 0x232c +#define NVC397_SET_FALCON11_V 31:0 + +#define NVC397_SET_FALCON12 0x2330 +#define NVC397_SET_FALCON12_V 31:0 + +#define NVC397_SET_FALCON13 0x2334 +#define NVC397_SET_FALCON13_V 31:0 + +#define NVC397_SET_FALCON14 0x2338 +#define NVC397_SET_FALCON14_V 31:0 + +#define NVC397_SET_FALCON15 0x233c +#define NVC397_SET_FALCON15_V 31:0 + +#define NVC397_SET_FALCON16 0x2340 +#define NVC397_SET_FALCON16_V 31:0 + +#define NVC397_SET_FALCON17 0x2344 +#define NVC397_SET_FALCON17_V 31:0 + +#define NVC397_SET_FALCON18 0x2348 +#define NVC397_SET_FALCON18_V 31:0 + +#define NVC397_SET_FALCON19 0x234c +#define NVC397_SET_FALCON19_V 31:0 + +#define NVC397_SET_FALCON20 0x2350 +#define NVC397_SET_FALCON20_V 31:0 + +#define NVC397_SET_FALCON21 0x2354 +#define NVC397_SET_FALCON21_V 31:0 + +#define NVC397_SET_FALCON22 0x2358 +#define NVC397_SET_FALCON22_V 31:0 + +#define NVC397_SET_FALCON23 0x235c +#define NVC397_SET_FALCON23_V 31:0 + +#define NVC397_SET_FALCON24 0x2360 +#define NVC397_SET_FALCON24_V 31:0 + +#define NVC397_SET_FALCON25 0x2364 +#define NVC397_SET_FALCON25_V 31:0 + +#define NVC397_SET_FALCON26 0x2368 +#define NVC397_SET_FALCON26_V 31:0 + +#define NVC397_SET_FALCON27 0x236c +#define NVC397_SET_FALCON27_V 31:0 + +#define NVC397_SET_FALCON28 0x2370 +#define NVC397_SET_FALCON28_V 31:0 + +#define NVC397_SET_FALCON29 0x2374 +#define NVC397_SET_FALCON29_V 31:0 + +#define NVC397_SET_FALCON30 0x2378 +#define NVC397_SET_FALCON30_V 31:0 + +#define NVC397_SET_FALCON31 0x237c +#define NVC397_SET_FALCON31_V 31:0 + +#define NVC397_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC397_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC397_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC397_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC397_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC397_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC397_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC397_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC397_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC397_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC397_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC397_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC397_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC397_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC397_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC397_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC397_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC397_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC397_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC397_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC397_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC397_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC397_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC397_SET_TRAP_HANDLER_A 0x25f8 +#define NVC397_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC397_SET_TRAP_HANDLER_B 0x25fc +#define NVC397_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC397_SET_COLOR_CLAMP 0x2600 +#define NVC397_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC397_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC397_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BINDLESS_TEXTURE 0x2608 +#define NVC397_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVC397_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC397_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC397_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC397_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC397_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC397_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC397_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC397_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC397_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC397_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC397_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC397_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC397_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC397_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC397_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC397_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC397_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC397_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC397_CALL_MME_MACRO_V 31:0 + +#define NVC397_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC397_CALL_MME_DATA_V 31:0 + +#endif /* _cl_volta_a_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc3b0.h b/userspace/sdks/nv570/inc/class/clc3b0.h new file mode 100644 index 0000000..5ccaedd --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc3b0.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _clc3b0_h_ +#define _clc3b0_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC3B0_VIDEO_DECODER (0x0000C3B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc3b0_h + diff --git a/userspace/sdks/nv570/inc/class/clc3b5.h b/userspace/sdks/nv570/inc/class/clc3b5.h new file mode 100644 index 0000000..74ee1b7 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc3b5.h @@ -0,0 +1,278 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clc3b5_h_ +#define _clc3b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define VOLTA_DMA_COPY_A (0x0000C3B5) + +#define NVC3B5_NOP (0x00000100) +#define NVC3B5_NOP_PARAMETER 31:0 +#define NVC3B5_PM_TRIGGER (0x00000140) +#define NVC3B5_PM_TRIGGER_V 31:0 +#define NVC3B5_SET_SEMAPHORE_A (0x00000240) +#define NVC3B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC3B5_SET_SEMAPHORE_B (0x00000244) +#define NVC3B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC3B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC3B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC3B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC3B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC3B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC3B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC3B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC3B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC3B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC3B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC3B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC3B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC3B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC3B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC3B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC3B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC3B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC3B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC3B5_SET_SRC_PHYS_MODE_BASIC_KIND 5:2 +#define NVC3B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC3B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC3B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC3B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC3B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC3B5_SET_DST_PHYS_MODE_BASIC_KIND 5:2 +#define NVC3B5_LAUNCH_DMA (0x00000300) +#define NVC3B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC3B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC3B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC3B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC3B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC3B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC3B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC3B5_LAUNCH_DMA_FLUSH_TYPE 25:25 +#define NVC3B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000) +#define NVC3B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC3B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC3B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC3B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC3B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC3B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC3B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC3B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC3B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC3B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC3B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC3B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC3B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC3B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC3B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC3B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC3B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC3B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC3B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC3B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC3B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC3B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC3B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC3B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC3B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC3B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC3B5_LAUNCH_DMA_SRC_BYPASS_L2 20:20 +#define NVC3B5_LAUNCH_DMA_SRC_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC3B5_LAUNCH_DMA_SRC_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC3B5_LAUNCH_DMA_DST_BYPASS_L2 21:21 +#define NVC3B5_LAUNCH_DMA_DST_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC3B5_LAUNCH_DMA_DST_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC3B5_LAUNCH_DMA_VPRMODE 23:22 +#define NVC3B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVC3B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC3B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC3B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 +#define NVC3B5_OFFSET_IN_UPPER (0x00000400) +#define NVC3B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC3B5_OFFSET_IN_LOWER (0x00000404) +#define NVC3B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC3B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC3B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC3B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC3B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC3B5_PITCH_IN (0x00000410) +#define NVC3B5_PITCH_IN_VALUE 31:0 +#define NVC3B5_PITCH_OUT (0x00000414) +#define NVC3B5_PITCH_OUT_VALUE 31:0 +#define NVC3B5_LINE_LENGTH_IN (0x00000418) +#define NVC3B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC3B5_LINE_COUNT (0x0000041C) +#define NVC3B5_LINE_COUNT_VALUE 31:0 +#define NVC3B5_SET_REMAP_CONST_A (0x00000700) +#define NVC3B5_SET_REMAP_CONST_A_V 31:0 +#define NVC3B5_SET_REMAP_CONST_B (0x00000704) +#define NVC3B5_SET_REMAP_CONST_B_V 31:0 +#define NVC3B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC3B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC3B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC3B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC3B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC3B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC3B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC3B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC3B5_SET_DST_WIDTH (0x00000710) +#define NVC3B5_SET_DST_WIDTH_V 31:0 +#define NVC3B5_SET_DST_HEIGHT (0x00000714) +#define NVC3B5_SET_DST_HEIGHT_V 31:0 +#define NVC3B5_SET_DST_DEPTH (0x00000718) +#define NVC3B5_SET_DST_DEPTH_V 31:0 +#define NVC3B5_SET_DST_LAYER (0x0000071C) +#define NVC3B5_SET_DST_LAYER_V 31:0 +#define NVC3B5_SET_DST_ORIGIN (0x00000720) +#define NVC3B5_SET_DST_ORIGIN_X 15:0 +#define NVC3B5_SET_DST_ORIGIN_Y 31:16 +#define NVC3B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC3B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC3B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC3B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC3B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC3B5_SET_SRC_WIDTH (0x0000072C) +#define NVC3B5_SET_SRC_WIDTH_V 31:0 +#define NVC3B5_SET_SRC_HEIGHT (0x00000730) +#define NVC3B5_SET_SRC_HEIGHT_V 31:0 +#define NVC3B5_SET_SRC_DEPTH (0x00000734) +#define NVC3B5_SET_SRC_DEPTH_V 31:0 +#define NVC3B5_SET_SRC_LAYER (0x00000738) +#define NVC3B5_SET_SRC_LAYER_V 31:0 +#define NVC3B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC3B5_SET_SRC_ORIGIN_X 15:0 +#define NVC3B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC3B5_SRC_ORIGIN_X (0x00000744) +#define NVC3B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC3B5_SRC_ORIGIN_Y (0x00000748) +#define NVC3B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC3B5_DST_ORIGIN_X (0x0000074C) +#define NVC3B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC3B5_DST_ORIGIN_Y (0x00000750) +#define NVC3B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC3B5_PM_TRIGGER_END (0x00001114) +#define NVC3B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc3b5_h + diff --git a/userspace/sdks/nv570/inc/class/clc3b5sw.h b/userspace/sdks/nv570/inc/class/clc3b5sw.h new file mode 100644 index 0000000..518883c --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc3b5sw.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc3b5sw.finn +// + + + +// +// Using VERSION_0 will cause the API to interpret +// engineType as a CE engine instance. This allows +// for backward compatibility with 85B5sw and 90B5sw. +// +#define NVC3B5_ALLOCATION_PARAMETERS_VERSION_0 0 + +// +// Using VERSION_1 will cause the API to interpret +// engineType as an NV2080_ENGINE_TYPE ordinal. +// +#define NVC3B5_ALLOCATION_PARAMETERS_VERSION_1 1 + +#define NVC3B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc3b5U) + +typedef struct NVC3B5_ALLOCATION_PARAMETERS { + NvU32 version; + NvU32 engineType; +} NVC3B5_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clc3b7.h b/userspace/sdks/nv570/inc/class/clc3b7.h new file mode 100644 index 0000000..0a313b8 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc3b7.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clc3b7_h +#define clc3b7_h + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC3B7_VIDEO_ENCODER (0x0000C3B7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc3b7_h + diff --git a/userspace/sdks/nv570/inc/class/clc3c0.h b/userspace/sdks/nv570/inc/class/clc3c0.h new file mode 100644 index 0000000..76b4566 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc3c0.h @@ -0,0 +1,703 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_volta_compute_a_h_ +#define _cl_volta_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl volta_compute_a */ + +#include "nvtypes.h" + +#define VOLTA_COMPUTE_A 0xC3C0 + +#define NVC3C0_SET_OBJECT 0x0000 +#define NVC3C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC3C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC3C0_NO_OPERATION 0x0100 +#define NVC3C0_NO_OPERATION_V 31:0 + +#define NVC3C0_SET_NOTIFY_A 0x0104 +#define NVC3C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC3C0_SET_NOTIFY_B 0x0108 +#define NVC3C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC3C0_NOTIFY 0x010c +#define NVC3C0_NOTIFY_TYPE 31:0 +#define NVC3C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC3C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC3C0_WAIT_FOR_IDLE 0x0110 +#define NVC3C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC3C0_SEND_GO_IDLE 0x013c +#define NVC3C0_SEND_GO_IDLE_V 31:0 + +#define NVC3C0_PM_TRIGGER 0x0140 +#define NVC3C0_PM_TRIGGER_V 31:0 + +#define NVC3C0_PM_TRIGGER_WFI 0x0144 +#define NVC3C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC3C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC3C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC3C0_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC3C0_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC3C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC3C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC3C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC3C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC3C0_LINE_LENGTH_IN 0x0180 +#define NVC3C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC3C0_LINE_COUNT 0x0184 +#define NVC3C0_LINE_COUNT_VALUE 31:0 + +#define NVC3C0_OFFSET_OUT_UPPER 0x0188 +#define NVC3C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC3C0_OFFSET_OUT 0x018c +#define NVC3C0_OFFSET_OUT_VALUE 31:0 + +#define NVC3C0_PITCH_OUT 0x0190 +#define NVC3C0_PITCH_OUT_VALUE 31:0 + +#define NVC3C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC3C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC3C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC3C0_SET_DST_WIDTH 0x0198 +#define NVC3C0_SET_DST_WIDTH_V 31:0 + +#define NVC3C0_SET_DST_HEIGHT 0x019c +#define NVC3C0_SET_DST_HEIGHT_V 31:0 + +#define NVC3C0_SET_DST_DEPTH 0x01a0 +#define NVC3C0_SET_DST_DEPTH_V 31:0 + +#define NVC3C0_SET_DST_LAYER 0x01a4 +#define NVC3C0_SET_DST_LAYER_V 31:0 + +#define NVC3C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC3C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC3C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC3C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC3C0_LAUNCH_DMA 0x01b0 +#define NVC3C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC3C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC3C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC3C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC3C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC3C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC3C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC3C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC3C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC3C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC3C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC3C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC3C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC3C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC3C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC3C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC3C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC3C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC3C0_LOAD_INLINE_DATA 0x01b4 +#define NVC3C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC3C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC3C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC3C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC3C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC3C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC3C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC3C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC3C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC3C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC3C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC3C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC3C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC3C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC3C0_PERFMON_TRANSFER 0x0210 +#define NVC3C0_PERFMON_TRANSFER_V 31:0 + +#define NVC3C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC3C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC3C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC3C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC3C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC3C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC3C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC3C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC3C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC3C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC3C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC3C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC3C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC3C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC3C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC3C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC3C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC3C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC3C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC3C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC3C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC3C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC3C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC3C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC3C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC3C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC3C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC3C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC3C0_SET_SCG_CONTROL 0x0270 +#define NVC3C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 +#define NVC3C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 +#define NVC3C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 +#define NVC3C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 +#define NVC3C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 + +#define NVC3C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC3C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC3C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC3C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC3C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC3C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC3C0_SET_QMD_VERSION 0x0288 +#define NVC3C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC3C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC3C0_CHECK_QMD_VERSION 0x0290 +#define NVC3C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC3C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC3C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC3C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC3C0_SCG_HYSTERESIS_CONTROL 0x02a8 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 + +#define NVC3C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC3C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC3C0_SEND_PCAS_A 0x02b4 +#define NVC3C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC3C0_SEND_PCAS_B 0x02b8 +#define NVC3C0_SEND_PCAS_B_FROM 23:0 +#define NVC3C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC3C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC3C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC3C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC3C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC3C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC3C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC3C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC3C0_SET_SKED_CACHE_CONTROL 0x02cc +#define NVC3C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID 0:0 +#define NVC3C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE 0x00000000 +#define NVC3C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE 0x00000001 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC3C0_SET_SPA_VERSION 0x0310 +#define NVC3C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC3C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC3C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC3C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC3C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC3C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC3C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC3C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC3C0_SET_FALCON00 0x0500 +#define NVC3C0_SET_FALCON00_V 31:0 + +#define NVC3C0_SET_FALCON01 0x0504 +#define NVC3C0_SET_FALCON01_V 31:0 + +#define NVC3C0_SET_FALCON02 0x0508 +#define NVC3C0_SET_FALCON02_V 31:0 + +#define NVC3C0_SET_FALCON03 0x050c +#define NVC3C0_SET_FALCON03_V 31:0 + +#define NVC3C0_SET_FALCON04 0x0510 +#define NVC3C0_SET_FALCON04_V 31:0 + +#define NVC3C0_SET_FALCON05 0x0514 +#define NVC3C0_SET_FALCON05_V 31:0 + +#define NVC3C0_SET_FALCON06 0x0518 +#define NVC3C0_SET_FALCON06_V 31:0 + +#define NVC3C0_SET_FALCON07 0x051c +#define NVC3C0_SET_FALCON07_V 31:0 + +#define NVC3C0_SET_FALCON08 0x0520 +#define NVC3C0_SET_FALCON08_V 31:0 + +#define NVC3C0_SET_FALCON09 0x0524 +#define NVC3C0_SET_FALCON09_V 31:0 + +#define NVC3C0_SET_FALCON10 0x0528 +#define NVC3C0_SET_FALCON10_V 31:0 + +#define NVC3C0_SET_FALCON11 0x052c +#define NVC3C0_SET_FALCON11_V 31:0 + +#define NVC3C0_SET_FALCON12 0x0530 +#define NVC3C0_SET_FALCON12_V 31:0 + +#define NVC3C0_SET_FALCON13 0x0534 +#define NVC3C0_SET_FALCON13_V 31:0 + +#define NVC3C0_SET_FALCON14 0x0538 +#define NVC3C0_SET_FALCON14_V 31:0 + +#define NVC3C0_SET_FALCON15 0x053c +#define NVC3C0_SET_FALCON15_V 31:0 + +#define NVC3C0_SET_FALCON16 0x0540 +#define NVC3C0_SET_FALCON16_V 31:0 + +#define NVC3C0_SET_FALCON17 0x0544 +#define NVC3C0_SET_FALCON17_V 31:0 + +#define NVC3C0_SET_FALCON18 0x0548 +#define NVC3C0_SET_FALCON18_V 31:0 + +#define NVC3C0_SET_FALCON19 0x054c +#define NVC3C0_SET_FALCON19_V 31:0 + +#define NVC3C0_SET_FALCON20 0x0550 +#define NVC3C0_SET_FALCON20_V 31:0 + +#define NVC3C0_SET_FALCON21 0x0554 +#define NVC3C0_SET_FALCON21_V 31:0 + +#define NVC3C0_SET_FALCON22 0x0558 +#define NVC3C0_SET_FALCON22_V 31:0 + +#define NVC3C0_SET_FALCON23 0x055c +#define NVC3C0_SET_FALCON23_V 31:0 + +#define NVC3C0_SET_FALCON24 0x0560 +#define NVC3C0_SET_FALCON24_V 31:0 + +#define NVC3C0_SET_FALCON25 0x0564 +#define NVC3C0_SET_FALCON25_V 31:0 + +#define NVC3C0_SET_FALCON26 0x0568 +#define NVC3C0_SET_FALCON26_V 31:0 + +#define NVC3C0_SET_FALCON27 0x056c +#define NVC3C0_SET_FALCON27_V 31:0 + +#define NVC3C0_SET_FALCON28 0x0570 +#define NVC3C0_SET_FALCON28_V 31:0 + +#define NVC3C0_SET_FALCON29 0x0574 +#define NVC3C0_SET_FALCON29_V 31:0 + +#define NVC3C0_SET_FALCON30 0x0578 +#define NVC3C0_SET_FALCON30_V 31:0 + +#define NVC3C0_SET_FALCON31 0x057c +#define NVC3C0_SET_FALCON31_V 31:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC3C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC3C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC3C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC3C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC3C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC3C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC3C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC3C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC3C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC3C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC3C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC3C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC3C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC3C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC3C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC3C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC3C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC3C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC3C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC3C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC3C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC3C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC3C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC3C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC3C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC3C0_PIPE_NOP 0x1a2c +#define NVC3C0_PIPE_NOP_V 31:0 + +#define NVC3C0_SET_SPARE00 0x1a30 +#define NVC3C0_SET_SPARE00_V 31:0 + +#define NVC3C0_SET_SPARE01 0x1a34 +#define NVC3C0_SET_SPARE01_V 31:0 + +#define NVC3C0_SET_SPARE02 0x1a38 +#define NVC3C0_SET_SPARE02_V 31:0 + +#define NVC3C0_SET_SPARE03 0x1a3c +#define NVC3C0_SET_SPARE03_V 31:0 + +#define NVC3C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC3C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC3C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC3C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC3C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC3C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC3C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC3C0_SET_TRAP_HANDLER_A 0x25f8 +#define NVC3C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC3C0_SET_TRAP_HANDLER_B 0x25fc +#define NVC3C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC3C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC3C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC3C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC3C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC3C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC3C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC3C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC3C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC3C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC3C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC3C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC3C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_volta_compute_a_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc461.h b/userspace/sdks/nv570/inc/class/clc461.h new file mode 100644 index 0000000..0c0378f --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc461.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc461_h_ +#define _clc461_h_ + +#define TURING_USERMODE_A (0xc461) + +#endif // _clc461_h_ diff --git a/userspace/sdks/nv570/inc/class/clc46f.h b/userspace/sdks/nv570/inc/class/clc46f.h new file mode 100644 index 0000000..fb1c594 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc46f.h @@ -0,0 +1,365 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc46f_h_ +#define _clc46f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class TURING_CHANNEL_GPFIFO */ +/* + * Documentation for TURING_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + * Note there is no .mfs file for this class. + */ +#define TURING_CHANNEL_GPFIFO_A (0x0000C46F) + +#define NVC46F_TYPEDEF TURING_CHANNELChannelGPFifoA + +/* dma flow control data structure */ +typedef volatile struct Nvc46fControl_struct { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} Nvc46fControl, TuringAControlGPFifo; + +/* fields and values */ +#define NVC46F_NUMBER_OF_SUBCHANNELS (8) +#define NVC46F_SET_OBJECT (0x00000000) +#define NVC46F_SET_OBJECT_NVCLASS 15:0 +#define NVC46F_SET_OBJECT_ENGINE 20:16 +#define NVC46F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVC46F_ILLEGAL (0x00000004) +#define NVC46F_ILLEGAL_HANDLE 31:0 +#define NVC46F_NOP (0x00000008) +#define NVC46F_NOP_HANDLE 31:0 +#define NVC46F_SEMAPHOREA (0x00000010) +#define NVC46F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVC46F_SEMAPHOREB (0x00000014) +#define NVC46F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVC46F_SEMAPHOREC (0x00000018) +#define NVC46F_SEMAPHOREC_PAYLOAD 31:0 +#define NVC46F_SEMAPHORED (0x0000001C) +#define NVC46F_SEMAPHORED_OPERATION 4:0 +#define NVC46F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVC46F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVC46F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVC46F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVC46F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 +#define NVC46F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVC46F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVC46F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVC46F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVC46F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVC46F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVC46F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVC46F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVC46F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVC46F_SEMAPHORED_REDUCTION 30:27 +#define NVC46F_SEMAPHORED_REDUCTION_MIN 0x00000000 +#define NVC46F_SEMAPHORED_REDUCTION_MAX 0x00000001 +#define NVC46F_SEMAPHORED_REDUCTION_XOR 0x00000002 +#define NVC46F_SEMAPHORED_REDUCTION_AND 0x00000003 +#define NVC46F_SEMAPHORED_REDUCTION_OR 0x00000004 +#define NVC46F_SEMAPHORED_REDUCTION_ADD 0x00000005 +#define NVC46F_SEMAPHORED_REDUCTION_INC 0x00000006 +#define NVC46F_SEMAPHORED_REDUCTION_DEC 0x00000007 +#define NVC46F_SEMAPHORED_FORMAT 31:31 +#define NVC46F_SEMAPHORED_FORMAT_SIGNED 0x00000000 +#define NVC46F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 +#define NVC46F_NON_STALL_INTERRUPT (0x00000020) +#define NVC46F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVC46F_FB_FLUSH (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR +#define NVC46F_FB_FLUSH_HANDLE 31:0 +// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for +// specifying the page address for a targeted TLB invalidate and the uTLB for +// a targeted REPLAY_CANCEL for UVM. +// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly +// rearranged fields. +#define NVC46F_MEM_OP_A (0x00000028) +#define NVC46F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC46F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type +#define NVC46F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC46F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID 6:0 // only relevant for REPLAY_CANCEL_VA_GLOBAL +#define NVC46F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11 +#define NVC46F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001 +#define NVC46F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000 +#define NVC46F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12 +#define NVC46F_MEM_OP_B (0x0000002c) +#define NVC46F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0 +#define NVC46F_MEM_OP_C (0x00000030) +#define NVC46F_MEM_OP_C_MEMBAR_TYPE 2:0 +#define NVC46F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000 +#define NVC46F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE 9:7 //only relevant for REPLAY_CANCEL_VA_GLOBAL +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ 0 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE 1 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG 2 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD 3 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK 4 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL 5 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC 6 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL 7 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE +#define NVC46F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG 19:0 +// MEM_OP_D MUST be preceded by MEM_OPs A-C. +#define NVC46F_MEM_OP_D (0x00000034) +#define NVC46F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE +#define NVC46F_MEM_OP_D_OPERATION 31:27 +#define NVC46F_MEM_OP_D_OPERATION_MEMBAR 0x00000005 +#define NVC46F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVC46F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a +#define NVC46F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NVC46F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +// CLEAN_LINES is an alias for Tegra/GPU IP usage +#define NVC46F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e +#define NVC46F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVC46F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVC46F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015 +#define NVC46F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR 0x00000016 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE 1:0 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC 0x00000000 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC 0x00000001 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL 0x00000002 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED 0x00000003 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE 2:2 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC 0x00000000 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC 0x00000001 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK 6:3 +#define NVC46F_SET_REFERENCE (0x00000050) +#define NVC46F_SET_REFERENCE_COUNT 31:0 +#define NVC46F_SEM_ADDR_LO (0x0000005c) +#define NVC46F_SEM_ADDR_LO_OFFSET 31:2 +#define NVC46F_SEM_ADDR_HI (0x00000060) +#define NVC46F_SEM_ADDR_HI_OFFSET 7:0 +#define NVC46F_SEM_PAYLOAD_LO (0x00000064) +#define NVC46F_SEM_PAYLOAD_LO_PAYLOAD 31:0 +#define NVC46F_SEM_PAYLOAD_HI (0x00000068) +#define NVC46F_SEM_PAYLOAD_HI_PAYLOAD 31:0 +#define NVC46F_SEM_EXECUTE (0x0000006c) +#define NVC46F_SEM_EXECUTE_OPERATION 2:0 +#define NVC46F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000 +#define NVC46F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001 +#define NVC46F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ 0x00000002 +#define NVC46F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003 +#define NVC46F_SEM_EXECUTE_OPERATION_ACQ_AND 0x00000004 +#define NVC46F_SEM_EXECUTE_OPERATION_ACQ_NOR 0x00000005 +#define NVC46F_SEM_EXECUTE_OPERATION_REDUCTION 0x00000006 +#define NVC46F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12 +#define NVC46F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS 0x00000000 +#define NVC46F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001 +#define NVC46F_SEM_EXECUTE_RELEASE_WFI 20:20 +#define NVC46F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000 +#define NVC46F_SEM_EXECUTE_RELEASE_WFI_EN 0x00000001 +#define NVC46F_SEM_EXECUTE_PAYLOAD_SIZE 24:24 +#define NVC46F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000 +#define NVC46F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT 0x00000001 +#define NVC46F_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25 +#define NVC46F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000 +#define NVC46F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001 +#define NVC46F_SEM_EXECUTE_REDUCTION 30:27 +#define NVC46F_SEM_EXECUTE_REDUCTION_IMIN 0x00000000 +#define NVC46F_SEM_EXECUTE_REDUCTION_IMAX 0x00000001 +#define NVC46F_SEM_EXECUTE_REDUCTION_IXOR 0x00000002 +#define NVC46F_SEM_EXECUTE_REDUCTION_IAND 0x00000003 +#define NVC46F_SEM_EXECUTE_REDUCTION_IOR 0x00000004 +#define NVC46F_SEM_EXECUTE_REDUCTION_IADD 0x00000005 +#define NVC46F_SEM_EXECUTE_REDUCTION_INC 0x00000006 +#define NVC46F_SEM_EXECUTE_REDUCTION_DEC 0x00000007 +#define NVC46F_SEM_EXECUTE_REDUCTION_FORMAT 31:31 +#define NVC46F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000000 +#define NVC46F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000001 +#define NVC46F_WFI (0x00000078) +#define NVC46F_WFI_SCOPE 0:0 +#define NVC46F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000 +#define NVC46F_WFI_SCOPE_CURRENT_VEID 0x00000000 +#define NVC46F_WFI_SCOPE_ALL 0x00000001 +#define NVC46F_CRC_CHECK (0x0000007c) +#define NVC46F_CRC_CHECK_VALUE 31:0 +#define NVC46F_YIELD (0x00000080) +#define NVC46F_YIELD_OP 1:0 +#define NVC46F_YIELD_OP_NOP 0x00000000 +#define NVC46F_YIELD_OP_RUNLIST_TIMESLICE 0x00000002 +#define NVC46F_YIELD_OP_TSG 0x00000003 +#define NVC46F_CLEAR_FAULTED (0x00000084) +// Note: RM provides the HANDLE as an opaque value; the internal detail fields +// are intentionally not exposed to the driver through these defines. +#define NVC46F_CLEAR_FAULTED_HANDLE 30:0 +#define NVC46F_CLEAR_FAULTED_TYPE 31:31 +#define NVC46F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED 0x00000000 +#define NVC46F_CLEAR_FAULTED_TYPE_ENG_FAULTED 0x00000001 + + +/* GPFIFO entry format */ +#define NVC46F_GP_ENTRY__SIZE 8 +#define NVC46F_GP_ENTRY0_FETCH 0:0 +#define NVC46F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVC46F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVC46F_GP_ENTRY0_GET 31:2 +#define NVC46F_GP_ENTRY0_OPERAND 31:0 +#define NVC46F_GP_ENTRY1_GET_HI 7:0 +#define NVC46F_GP_ENTRY1_LEVEL 9:9 +#define NVC46F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVC46F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVC46F_GP_ENTRY1_LENGTH 30:10 +#define NVC46F_GP_ENTRY1_SYNC 31:31 +#define NVC46F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVC46F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVC46F_GP_ENTRY1_OPCODE 7:0 +#define NVC46F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVC46F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVC46F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVC46F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVC46F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVC46F_DMA_METHOD_ADDRESS 11:0 +#define NVC46F_DMA_SUBDEVICE_MASK 15:4 +#define NVC46F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVC46F_DMA_TERT_OP 17:16 +#define NVC46F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVC46F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVC46F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVC46F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVC46F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVC46F_DMA_METHOD_COUNT_OLD 28:18 +#define NVC46F_DMA_METHOD_COUNT 28:16 +#define NVC46F_DMA_IMMD_DATA 28:16 +#define NVC46F_DMA_SEC_OP 31:29 +#define NVC46F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVC46F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVC46F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVC46F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVC46F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVC46F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVC46F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVC46F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVC46F_DMA_INCR_ADDRESS 11:0 +#define NVC46F_DMA_INCR_SUBCHANNEL 15:13 +#define NVC46F_DMA_INCR_COUNT 28:16 +#define NVC46F_DMA_INCR_OPCODE 31:29 +#define NVC46F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVC46F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVC46F_DMA_NONINCR_ADDRESS 11:0 +#define NVC46F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVC46F_DMA_NONINCR_COUNT 28:16 +#define NVC46F_DMA_NONINCR_OPCODE 31:29 +#define NVC46F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVC46F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVC46F_DMA_ONEINCR_ADDRESS 11:0 +#define NVC46F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVC46F_DMA_ONEINCR_COUNT 28:16 +#define NVC46F_DMA_ONEINCR_OPCODE 31:29 +#define NVC46F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVC46F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVC46F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVC46F_DMA_IMMD_ADDRESS 11:0 +#define NVC46F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVC46F_DMA_IMMD_DATA 28:16 +#define NVC46F_DMA_IMMD_OPCODE 31:29 +#define NVC46F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVC46F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVC46F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC46F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVC46F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVC46F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC46F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVC46F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC46F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVC46F_DMA_ENDSEG_OPCODE 31:29 +#define NVC46F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVC46F_DMA_ADDRESS 12:2 +#define NVC46F_DMA_SUBCH 15:13 +#define NVC46F_DMA_OPCODE3 17:16 +#define NVC46F_DMA_OPCODE3_NONE (0x00000000) +#define NVC46F_DMA_COUNT 28:18 +#define NVC46F_DMA_OPCODE 31:29 +#define NVC46F_DMA_OPCODE_METHOD (0x00000000) +#define NVC46F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVC46F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc46f_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc46fsw.h b/userspace/sdks/nv570/inc/class/clc46fsw.h new file mode 100644 index 0000000..7438195 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc46fsw.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* This file is *not* auto-generated. */ + +#ifndef _clc46f_sw_h_ +#define _clc46f_sw_h_ + +#define NVC46F_NOTIFIERS_RC (0) +#define NVC46F_NOTIFIERS_REFCNT (1) +#define NVC46F_NOTIFIERS_NONSTALL (2) +#define NVC46F_NOTIFIERS_EVENTBUFFER (3) +#define NVC46F_NOTIFIERS_IDLECHANNEL (4) +#define NVC46F_NOTIFIERS_ENDCTX (5) +#define NVC46F_NOTIFIERS_SW (6) +#define NVC46F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVC46F_NOTIFIERS_REPLAYABLE_FAULT (8) +#define NVC46F_NOTIFIERS_MAXCOUNT (9) + +/* NvNotification[] fields and values */ +#define NVC46F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVC46F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _clc46f_sw_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc4b0.h b/userspace/sdks/nv570/inc/class/clc4b0.h new file mode 100644 index 0000000..4b7d335 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc4b0.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clc4b0_h_ +#define clc4b0_h_ + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC4B0_VIDEO_DECODER (0x0000C4B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc4b0_h + diff --git a/userspace/sdks/nv570/inc/class/clc4b7.h b/userspace/sdks/nv570/inc/class/clc4b7.h new file mode 100644 index 0000000..27f3983 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc4b7.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clc4b7_h_ +#define clc4b7_h_ + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC4B7_VIDEO_ENCODER (0x0000C4B7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc4b7_h + diff --git a/userspace/sdks/nv570/inc/class/clc4c0.h b/userspace/sdks/nv570/inc/class/clc4c0.h new file mode 100644 index 0000000..f96026c --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc4c0.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_volta_compute_b_h_ +#define _cl_volta_compute_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl volta_compute_b */ + +#include "nvtypes.h" + +#define VOLTA_COMPUTE_B 0xC4C0 + +#endif /* _cl_volta_compute_b_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc4d1.h b/userspace/sdks/nv570/inc/class/clc4d1.h new file mode 100644 index 0000000..196b034 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc4d1.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "nvtypes.h" + +#ifndef _clc4d1_h_ +#define _clc4d1_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC4D1_VIDEO_NVJPG (0x0000C4D1) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc4d1_h + diff --git a/userspace/sdks/nv570/inc/class/clc561.h b/userspace/sdks/nv570/inc/class/clc561.h new file mode 100644 index 0000000..83a9339 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc561.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc561_h_ +#define _clc561_h_ + +#define AMPERE_USERMODE_A (0xc561) + +#endif // _clc561_h_ diff --git a/userspace/sdks/nv570/inc/class/clc56f.h b/userspace/sdks/nv570/inc/class/clc56f.h new file mode 100644 index 0000000..bc8b675 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc56f.h @@ -0,0 +1,367 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc56f_h_ +#define _clc56f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class AMPERE_CHANNEL_GPFIFO */ +/* + * Documentation for AMPERE_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + * Note there is no .mfs file for this class. + */ +#define AMPERE_CHANNEL_GPFIFO_A (0x0000C56F) + +#define NVC56F_TYPEDEF AMPERE_CHANNELChannelGPFifoA + +/* dma flow control data structure */ +typedef volatile struct Nvc56fControl_struct { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} Nvc56fControl, AmpereAControlGPFifo; + +/* fields and values */ +#define NVC56F_NUMBER_OF_SUBCHANNELS (8) +#define NVC56F_SET_OBJECT (0x00000000) +#define NVC56F_SET_OBJECT_NVCLASS 15:0 +#define NVC56F_SET_OBJECT_ENGINE 20:16 +#define NVC56F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVC56F_ILLEGAL (0x00000004) +#define NVC56F_ILLEGAL_HANDLE 31:0 +#define NVC56F_NOP (0x00000008) +#define NVC56F_NOP_HANDLE 31:0 +#define NVC56F_SEMAPHOREA (0x00000010) +#define NVC56F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVC56F_SEMAPHOREB (0x00000014) +#define NVC56F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVC56F_SEMAPHOREC (0x00000018) +#define NVC56F_SEMAPHOREC_PAYLOAD 31:0 +#define NVC56F_SEMAPHORED (0x0000001C) +#define NVC56F_SEMAPHORED_OPERATION 4:0 +#define NVC56F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVC56F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVC56F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVC56F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVC56F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 +#define NVC56F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVC56F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVC56F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVC56F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVC56F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVC56F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVC56F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVC56F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVC56F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVC56F_SEMAPHORED_REDUCTION 30:27 +#define NVC56F_SEMAPHORED_REDUCTION_MIN 0x00000000 +#define NVC56F_SEMAPHORED_REDUCTION_MAX 0x00000001 +#define NVC56F_SEMAPHORED_REDUCTION_XOR 0x00000002 +#define NVC56F_SEMAPHORED_REDUCTION_AND 0x00000003 +#define NVC56F_SEMAPHORED_REDUCTION_OR 0x00000004 +#define NVC56F_SEMAPHORED_REDUCTION_ADD 0x00000005 +#define NVC56F_SEMAPHORED_REDUCTION_INC 0x00000006 +#define NVC56F_SEMAPHORED_REDUCTION_DEC 0x00000007 +#define NVC56F_SEMAPHORED_FORMAT 31:31 +#define NVC56F_SEMAPHORED_FORMAT_SIGNED 0x00000000 +#define NVC56F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 +#define NVC56F_NON_STALL_INTERRUPT (0x00000020) +#define NVC56F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVC56F_FB_FLUSH (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR +#define NVC56F_FB_FLUSH_HANDLE 31:0 +// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for +// specifying the page address for a targeted TLB invalidate and the uTLB for +// a targeted REPLAY_CANCEL for UVM. +// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly +// rearranged fields. +#define NVC56F_MEM_OP_A (0x00000028) +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE 7:6 // only relevant for invalidates with NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE for invalidating link TLB only, or non-link TLB only or all TLBs +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS 0 +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS 1 +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS 2 +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD 3 +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID 6:0 // only relevant for REPLAY_CANCEL_VA_GLOBAL +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11 +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001 +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000 +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12 +#define NVC56F_MEM_OP_B (0x0000002c) +#define NVC56F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0 +#define NVC56F_MEM_OP_C (0x00000030) +#define NVC56F_MEM_OP_C_MEMBAR_TYPE 2:0 +#define NVC56F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000 +#define NVC56F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE 9:7 //only relevant for REPLAY_CANCEL_VA_GLOBAL +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ 0 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE 1 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG 2 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD 3 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK 4 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL 5 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC 6 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL 7 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE +#define NVC56F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG 19:0 +// MEM_OP_D MUST be preceded by MEM_OPs A-C. +#define NVC56F_MEM_OP_D (0x00000034) +#define NVC56F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE +#define NVC56F_MEM_OP_D_OPERATION 31:27 +#define NVC56F_MEM_OP_D_OPERATION_MEMBAR 0x00000005 +#define NVC56F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVC56F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a +#define NVC56F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NVC56F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +// CLEAN_LINES is an alias for Tegra/GPU IP usage +#define NVC56F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e +#define NVC56F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVC56F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVC56F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015 +#define NVC56F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR 0x00000016 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE 1:0 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC 0x00000000 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC 0x00000001 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL 0x00000002 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED 0x00000003 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE 2:2 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC 0x00000000 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC 0x00000001 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK 6:3 +#define NVC56F_SET_REFERENCE (0x00000050) +#define NVC56F_SET_REFERENCE_COUNT 31:0 +#define NVC56F_SEM_ADDR_LO (0x0000005c) +#define NVC56F_SEM_ADDR_LO_OFFSET 31:2 +#define NVC56F_SEM_ADDR_HI (0x00000060) +#define NVC56F_SEM_ADDR_HI_OFFSET 7:0 +#define NVC56F_SEM_PAYLOAD_LO (0x00000064) +#define NVC56F_SEM_PAYLOAD_LO_PAYLOAD 31:0 +#define NVC56F_SEM_PAYLOAD_HI (0x00000068) +#define NVC56F_SEM_PAYLOAD_HI_PAYLOAD 31:0 +#define NVC56F_SEM_EXECUTE (0x0000006c) +#define NVC56F_SEM_EXECUTE_OPERATION 2:0 +#define NVC56F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000 +#define NVC56F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001 +#define NVC56F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ 0x00000002 +#define NVC56F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003 +#define NVC56F_SEM_EXECUTE_OPERATION_ACQ_AND 0x00000004 +#define NVC56F_SEM_EXECUTE_OPERATION_ACQ_NOR 0x00000005 +#define NVC56F_SEM_EXECUTE_OPERATION_REDUCTION 0x00000006 +#define NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12 +#define NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS 0x00000000 +#define NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001 +#define NVC56F_SEM_EXECUTE_RELEASE_WFI 20:20 +#define NVC56F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000 +#define NVC56F_SEM_EXECUTE_RELEASE_WFI_EN 0x00000001 +#define NVC56F_SEM_EXECUTE_PAYLOAD_SIZE 24:24 +#define NVC56F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000 +#define NVC56F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT 0x00000001 +#define NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25 +#define NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000 +#define NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001 +#define NVC56F_SEM_EXECUTE_REDUCTION 30:27 +#define NVC56F_SEM_EXECUTE_REDUCTION_IMIN 0x00000000 +#define NVC56F_SEM_EXECUTE_REDUCTION_IMAX 0x00000001 +#define NVC56F_SEM_EXECUTE_REDUCTION_IXOR 0x00000002 +#define NVC56F_SEM_EXECUTE_REDUCTION_IAND 0x00000003 +#define NVC56F_SEM_EXECUTE_REDUCTION_IOR 0x00000004 +#define NVC56F_SEM_EXECUTE_REDUCTION_IADD 0x00000005 +#define NVC56F_SEM_EXECUTE_REDUCTION_INC 0x00000006 +#define NVC56F_SEM_EXECUTE_REDUCTION_DEC 0x00000007 +#define NVC56F_SEM_EXECUTE_REDUCTION_FORMAT 31:31 +#define NVC56F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000000 +#define NVC56F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000001 +#define NVC56F_WFI (0x00000078) +#define NVC56F_WFI_SCOPE 0:0 +#define NVC56F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000 +#define NVC56F_WFI_SCOPE_CURRENT_VEID 0x00000000 +#define NVC56F_WFI_SCOPE_ALL 0x00000001 +#define NVC56F_YIELD (0x00000080) +#define NVC56F_YIELD_OP 1:0 +#define NVC56F_YIELD_OP_NOP 0x00000000 +#define NVC56F_YIELD_OP_TSG 0x00000003 +#define NVC56F_CLEAR_FAULTED (0x00000084) +// Note: RM provides the HANDLE as an opaque value; the internal detail fields +// are intentionally not exposed to the driver through these defines. +#define NVC56F_CLEAR_FAULTED_HANDLE 30:0 +#define NVC56F_CLEAR_FAULTED_TYPE 31:31 +#define NVC56F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED 0x00000000 +#define NVC56F_CLEAR_FAULTED_TYPE_ENG_FAULTED 0x00000001 + + +/* GPFIFO entry format */ +#define NVC56F_GP_ENTRY__SIZE 8 +#define NVC56F_GP_ENTRY0_FETCH 0:0 +#define NVC56F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVC56F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVC56F_GP_ENTRY0_GET 31:2 +#define NVC56F_GP_ENTRY0_OPERAND 31:0 +#define NVC56F_GP_ENTRY1_GET_HI 7:0 +#define NVC56F_GP_ENTRY1_LEVEL 9:9 +#define NVC56F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVC56F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVC56F_GP_ENTRY1_LENGTH 30:10 +#define NVC56F_GP_ENTRY1_SYNC 31:31 +#define NVC56F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVC56F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVC56F_GP_ENTRY1_OPCODE 7:0 +#define NVC56F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVC56F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVC56F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVC56F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVC56F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVC56F_DMA_METHOD_ADDRESS 11:0 +#define NVC56F_DMA_SUBDEVICE_MASK 15:4 +#define NVC56F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVC56F_DMA_TERT_OP 17:16 +#define NVC56F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVC56F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVC56F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVC56F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVC56F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVC56F_DMA_METHOD_COUNT_OLD 28:18 +#define NVC56F_DMA_METHOD_COUNT 28:16 +#define NVC56F_DMA_IMMD_DATA 28:16 +#define NVC56F_DMA_SEC_OP 31:29 +#define NVC56F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVC56F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVC56F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVC56F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVC56F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVC56F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVC56F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVC56F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVC56F_DMA_INCR_ADDRESS 11:0 +#define NVC56F_DMA_INCR_SUBCHANNEL 15:13 +#define NVC56F_DMA_INCR_COUNT 28:16 +#define NVC56F_DMA_INCR_OPCODE 31:29 +#define NVC56F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVC56F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVC56F_DMA_NONINCR_ADDRESS 11:0 +#define NVC56F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVC56F_DMA_NONINCR_COUNT 28:16 +#define NVC56F_DMA_NONINCR_OPCODE 31:29 +#define NVC56F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVC56F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVC56F_DMA_ONEINCR_ADDRESS 11:0 +#define NVC56F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVC56F_DMA_ONEINCR_COUNT 28:16 +#define NVC56F_DMA_ONEINCR_OPCODE 31:29 +#define NVC56F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVC56F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVC56F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVC56F_DMA_IMMD_ADDRESS 11:0 +#define NVC56F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVC56F_DMA_IMMD_DATA 28:16 +#define NVC56F_DMA_IMMD_OPCODE 31:29 +#define NVC56F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVC56F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVC56F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC56F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVC56F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVC56F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC56F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVC56F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC56F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVC56F_DMA_ENDSEG_OPCODE 31:29 +#define NVC56F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVC56F_DMA_ADDRESS 12:2 +#define NVC56F_DMA_SUBCH 15:13 +#define NVC56F_DMA_OPCODE3 17:16 +#define NVC56F_DMA_OPCODE3_NONE (0x00000000) +#define NVC56F_DMA_COUNT 28:18 +#define NVC56F_DMA_OPCODE 31:29 +#define NVC56F_DMA_OPCODE_METHOD (0x00000000) +#define NVC56F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVC56F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc56f_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc56fsw.h b/userspace/sdks/nv570/inc/class/clc56fsw.h new file mode 100644 index 0000000..13496be --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc56fsw.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* This file is *not* auto-generated. */ + +#ifndef _clc56f_sw_h_ +#define _clc56f_sw_h_ + +#define NVC56F_NOTIFIERS_RC (0) +#define NVC56F_NOTIFIERS_REFCNT (1) +#define NVC56F_NOTIFIERS_NONSTALL (2) +#define NVC56F_NOTIFIERS_EVENTBUFFER (3) +#define NVC56F_NOTIFIERS_IDLECHANNEL (4) +#define NVC56F_NOTIFIERS_ENDCTX (5) +#define NVC56F_NOTIFIERS_SW (6) +#define NVC56F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVC56F_NOTIFIERS_REPLAYABLE_FAULT (8) +#define NVC56F_NOTIFIERS_MAXCOUNT (9) + +/* NvNotification[] fields and values */ +#define NVC56F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVC56F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _clc56f_sw_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc570.h b/userspace/sdks/nv570/inc/class/clc570.h new file mode 100644 index 0000000..461736b --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc570.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc570.finn +// + +#define NVC570_DISPLAY (0xc570U) /* finn: Evaluated from "NVC570_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NVC570_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc570U) + +typedef struct NVC570_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NVC570_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clc572.h b/userspace/sdks/nv570/inc/class/clc572.h new file mode 100644 index 0000000..79dd9b3 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc572.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc572_h_ +#define _clc572_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define PHYSICAL_CHANNEL_GPFIFO (0x0000C572) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc572_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc573.h b/userspace/sdks/nv570/inc/class/clc573.h new file mode 100644 index 0000000..5cd57a8 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc573.h @@ -0,0 +1,606 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc573_h_ +#define _clc573_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC573_DISP_CAPABILITIES 0xC573 + +typedef volatile struct _clc573_tag0 { + NvU32 dispCapabilities[0x400]; +} _NvC573DispCapabilities,NvC573DispCapabilities_Map ; + + +#define NVC573_SYS_CAP 0x0 /* RW-4R */ +#define NVC573_SYS_CAP_HEAD0_EXISTS 0:0 /* RWIVF */ +#define NVC573_SYS_CAP_HEAD0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_HEAD1_EXISTS 1:1 /* RWIVF */ +#define NVC573_SYS_CAP_HEAD1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_HEAD2_EXISTS 2:2 /* RWIVF */ +#define NVC573_SYS_CAP_HEAD2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_HEAD3_EXISTS 3:3 /* RWIVF */ +#define NVC573_SYS_CAP_HEAD3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_HEAD4_EXISTS 4:4 /* RWIVF */ +#define NVC573_SYS_CAP_HEAD4_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_HEAD5_EXISTS 5:5 /* RWIVF */ +#define NVC573_SYS_CAP_HEAD5_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_HEAD6_EXISTS 6:6 /* RWIVF */ +#define NVC573_SYS_CAP_HEAD6_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_HEAD7_EXISTS 7:7 /* RWIVF */ +#define NVC573_SYS_CAP_HEAD7_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVC573_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */ +#define NVC573_SYS_CAP_HEAD_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR0_EXISTS 8:8 /* RWIVF */ +#define NVC573_SYS_CAP_SOR0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR1_EXISTS 9:9 /* RWIVF */ +#define NVC573_SYS_CAP_SOR1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR2_EXISTS 10:10 /* RWIVF */ +#define NVC573_SYS_CAP_SOR2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR3_EXISTS 11:11 /* RWIVF */ +#define NVC573_SYS_CAP_SOR3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR4_EXISTS 12:12 /* RWIVF */ +#define NVC573_SYS_CAP_SOR4_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR5_EXISTS 13:13 /* RWIVF */ +#define NVC573_SYS_CAP_SOR5_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR6_EXISTS 14:14 /* RWIVF */ +#define NVC573_SYS_CAP_SOR6_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR7_EXISTS 15:15 /* RWIVF */ +#define NVC573_SYS_CAP_SOR7_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* RWIVF */ +#define NVC573_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */ +#define NVC573_SYS_CAP_SOR_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB 0x4 /* RW-4R */ +#define NVC573_SYS_CAPB_WINDOW0_EXISTS 0:0 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW1_EXISTS 1:1 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW2_EXISTS 2:2 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW3_EXISTS 3:3 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW4_EXISTS 4:4 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW4_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW5_EXISTS 5:5 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW5_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW6_EXISTS 6:6 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW6_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW7_EXISTS 7:7 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW7_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW8_EXISTS 8:8 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW8_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW8_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW8_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW9_EXISTS 9:9 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW9_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW9_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW9_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW10_EXISTS 10:10 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW10_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW10_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW10_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW11_EXISTS 11:11 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW11_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW11_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW11_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW12_EXISTS 12:12 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW12_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW12_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW12_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW13_EXISTS 13:13 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW13_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW13_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW13_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW14_EXISTS 14:14 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW14_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW14_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW14_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW15_EXISTS 15:15 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW15_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW15_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW15_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW16_EXISTS 16:16 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW16_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW16_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW16_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW17_EXISTS 17:17 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW17_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW17_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW17_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW18_EXISTS 18:18 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW18_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW18_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW18_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW19_EXISTS 19:19 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW19_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW19_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW19_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW20_EXISTS 20:20 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW20_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW20_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW20_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW21_EXISTS 21:21 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW21_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW21_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW21_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW22_EXISTS 22:22 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW22_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW22_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW22_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW23_EXISTS 23:23 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW23_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW23_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW23_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW24_EXISTS 24:24 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW24_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW24_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW24_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW25_EXISTS 25:25 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW25_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW25_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW25_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW26_EXISTS 26:26 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW26_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW26_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW26_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW27_EXISTS 27:27 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW27_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW27_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW27_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW28_EXISTS 28:28 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW28_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW28_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW28_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW29_EXISTS 29:29 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW29_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW29_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW29_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW30_EXISTS 30:30 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW30_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW30_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW30_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW31_EXISTS 31:31 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW31_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW31_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW31_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW_EXISTS__SIZE_1 32 /* */ +#define NVC573_SYS_CAPB_WINDOW_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA 0x10 /* RW-4R */ +#define NVC573_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES 15:0 /* RWIUF */ +#define NVC573_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH 17:16 /* RWIVF */ +#define NVC573_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B 0x00000000 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B 0x00000002 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B 0x00000003 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_PLANAR 19:19 /* RWIVF */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_PLANAR_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_PLANAR_FALSE 0x00000000 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_PLANAR_TRUE 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_VGA 20:20 /* RWIVF */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_VGA_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE 0x00000000 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION 21:21 /* RWIVF */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_FALSE 0x00000000 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_TRUE 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MSCG 22:22 /* RWIVF */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MSCG_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MSCG_FALSE 0x00000000 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MSCG_TRUE 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH 23:23 /* RWIVF */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_FALSE 0x00000000 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_TRUE 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT 26:26 /* RWIVF */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION 31:30 /* RWIVF */ +#define NVC573_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B 0x00000000 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B 0x00000002 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B 0x00000003 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA(i) (0x680+(i)*32) /* RW-4A */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA__SIZE_1 8 /* */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_FULL_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_UNIT_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT 16:16 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT 17:17 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT 18:18 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OLPF_PRESENT 19:19 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OLPF_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OLPF_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OLPF_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT 20:20 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT 21:21 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT 22:22 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB(i) (0x684+(i)*32) /* RW-4A */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB__SIZE_1 8 /* */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_VGA 0:0 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_VGA_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_VGA_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_VGA_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGSZ 9:6 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGSZ_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGNR 12:10 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGNR_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT 15:15 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC(i) (0x688+(i)*32) /* RW-4A */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC__SIZE_1 8 /* */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC0_PRECISION 4:0 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC0_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC1_PRECISION 12:8 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC1_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP 13:13 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_SF_PRECISION 20:16 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_SF_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_CI_PRECISION 24:21 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_CI_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB 25:25 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPD(i) (0x68c+(i)*32) /* RW-4A */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPD__SIZE_1 8 /* */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE(i) (0x690+(i)*32) /* RW-4A */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE__SIZE_1 8 /* */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_RATEBUFSIZE 3:0 /* RWIUF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_RATEBUFSIZE_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_LINEBUFSIZE 13:8 /* RWIUF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_LINEBUFSIZE_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422 16:16 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420 17:17 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP(i) (0x144+(i)*8) /* RW-4A */ +#define NVC573_SOR_CAP__SIZE_1 8 /* */ +#define NVC573_SOR_CAP_SINGLE_LVDS_18 0:0 /* RWIVF */ +#define NVC573_SOR_CAP_SINGLE_LVDS_18_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_SINGLE_LVDS_24 1:1 /* RWIVF */ +#define NVC573_SOR_CAP_SINGLE_LVDS_24_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_DUAL_LVDS_18 2:2 /* RWIVF */ +#define NVC573_SOR_CAP_DUAL_LVDS_18_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_DUAL_LVDS_24 3:3 /* RWIVF */ +#define NVC573_SOR_CAP_DUAL_LVDS_24_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_SINGLE_TMDS_A 8:8 /* RWIVF */ +#define NVC573_SOR_CAP_SINGLE_TMDS_A_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_SINGLE_TMDS_B 9:9 /* RWIVF */ +#define NVC573_SOR_CAP_SINGLE_TMDS_B_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_DUAL_TMDS 11:11 /* RWIVF */ +#define NVC573_SOR_CAP_DUAL_TMDS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* RWIVF */ +#define NVC573_SOR_CAP_DISPLAY_OVER_PCIE_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_SDI 16:16 /* RWIVF */ +#define NVC573_SOR_CAP_SDI_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_SDI_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_SDI_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_DP_A 24:24 /* RWIVF */ +#define NVC573_SOR_CAP_DP_A_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_DP_A_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_DP_A_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_DP_B 25:25 /* RWIVF */ +#define NVC573_SOR_CAP_DP_B_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_DP_B_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_DP_B_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_DP_INTERLACE 26:26 /* RWIVF */ +#define NVC573_SOR_CAP_DP_INTERLACE_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_DP_8_LANES 27:27 /* RWIVF */ +#define NVC573_SOR_CAP_DP_8_LANES_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA(i) (0x780+(i)*32) /* RW-4A */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA__SIZE_1 32 /* */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH 13:10 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT 16:16 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT 17:17 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT 18:18 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT 19:19 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT 20:20 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT 21:21 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT 22:22 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT 23:23 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT 24:24 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB(i) (0x784+(i)*32) /* RW-4A */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB__SIZE_1 32 /* */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION 4:0 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ 9:6 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR 12:10 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT 15:15 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC(i) (0x788+(i)*32) /* RW-4A */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC__SIZE_1 32 /* */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION 4:0 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGSZ 9:6 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGSZ_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGNR 12:10 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGNR_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT 15:15 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION 20:16 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP 21:21 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD(i) (0x78c+(i)*32) /* RW-4A */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD__SIZE_1 32 /* */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ 3:0 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR 6:4 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD 8:8 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT 9:9 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION 16:12 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION 20:17 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB 21:21 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA 22:22 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE(i) (0x790+(i)*32) /* RW-4A */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE__SIZE_1 32 /* */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION 4:0 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGSZ 9:6 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGSZ_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGNR 12:10 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGNR_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT 15:15 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION 20:16 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP 21:21 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPF(i) (0x794+(i)*32) /* RW-4A */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPF__SIZE_1 32 /* */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CLK_CAP(i) (0x608+(i)*4) /* RW-4A */ +#define NVC573_SOR_CLK_CAP__SIZE_1 8 /* */ +#define NVC573_SOR_CLK_CAP_DP_MAX 7:0 /* RWIUF */ +#define NVC573_SOR_CLK_CAP_DP_MAX_INIT 0x00000051 /* RWI-V */ +#define NVC573_SOR_CLK_CAP_TMDS_MAX 23:16 /* RWIUF */ +#define NVC573_SOR_CLK_CAP_TMDS_MAX_INIT 0x0000003C /* RWI-V */ +#define NVC573_SOR_CLK_CAP_LVDS_MAX 31:24 /* RWIUF */ +#define NVC573_SOR_CLK_CAP_LVDS_MAX_INIT 0x00000000 /* RWI-V */ + +#ifdef __cplusplus +}; +#endif /* extern C */ +#endif //_clc573_h_ diff --git a/userspace/sdks/nv570/inc/class/clc574.h b/userspace/sdks/nv570/inc/class/clc574.h new file mode 100644 index 0000000..077a57f --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc574.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc574.finn +// + +#define UVM_CHANNEL_RETAINER (0xc574U) /* finn: Evaluated from "NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_MESSAGE_ID" */ + +#define NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_MESSAGE_ID (0xc574U) + +typedef struct NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS { + NvHandle hClient; + NvHandle hChannel; +} NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS; + diff --git a/userspace/sdks/nv570/inc/class/clc57a.h b/userspace/sdks/nv570/inc/class/clc57a.h new file mode 100644 index 0000000..2dcc60b --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc57a.h @@ -0,0 +1,213 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc57a__h_ +#define _clc57a__h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC57A_CURSOR_IMM_CHANNEL_PIO (0x0000C57A) + +typedef volatile struct _clc57a_tag0 { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x7D]; + NvV32 Update; // 0x00000200 - 0x00000203 + NvV32 SetInterlockFlags; // 0x00000204 - 0x00000207 + NvV32 SetCursorHotSpotPointOut[2]; // 0x00000208 - 0x0000020F + NvV32 SetWindowInterlockFlags; // 0x00000210 - 0x00000213 + NvV32 Reserved02[0x37B]; +} NVC57ADispCursorImmControlPio; + +#define NVC57A_FREE (0x00000008) +#define NVC57A_FREE_COUNT 5:0 +#define NVC57A_UPDATE (0x00000200) +#define NVC57A_UPDATE_RELEASE_ELV 0:0 +#define NVC57A_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC57A_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC57A_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC57A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC57A_SET_INTERLOCK_FLAGS (0x00000204) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC57A_SET_CURSOR_HOT_SPOT_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVC57A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0 +#define NVC57A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS (0x00000210) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc57a_h + diff --git a/userspace/sdks/nv570/inc/class/clc57b.h b/userspace/sdks/nv570/inc/class/clc57b.h new file mode 100644 index 0000000..f44d9a2 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc57b.h @@ -0,0 +1,67 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clC57b_h_ +#define _clC57b_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC57B_WINDOW_IMM_CHANNEL_DMA (0x0000C57B) + +// dma opcode instructions +#define NVC57B_DMA +#define NVC57B_DMA_OPCODE 31:29 +#define NVC57B_DMA_OPCODE_METHOD 0x00000000 +#define NVC57B_DMA_OPCODE_JUMP 0x00000001 +#define NVC57B_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC57B_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC57B_DMA_METHOD_COUNT 27:18 +#define NVC57B_DMA_METHOD_OFFSET 13:2 +#define NVC57B_DMA_DATA 31:0 +#define NVC57B_DMA_DATA_NOP 0x00000000 +#define NVC57B_DMA_JUMP_OFFSET 11:2 +#define NVC57B_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVC57B_PUT (0x00000000) +#define NVC57B_PUT_PTR 9:0 +#define NVC57B_GET (0x00000004) +#define NVC57B_GET_PTR 9:0 +#define NVC57B_UPDATE (0x00000200) +#define NVC57B_UPDATE_RELEASE_ELV 0:0 +#define NVC57B_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC57B_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC57B_UPDATE_INTERLOCK_WITH_WINDOW 1:1 +#define NVC57B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC57B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC57B_SET_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVC57B_SET_POINT_OUT_X 15:0 +#define NVC57B_SET_POINT_OUT_Y 31:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC57b_h diff --git a/userspace/sdks/nv570/inc/class/clc57d.h b/userspace/sdks/nv570/inc/class/clc57d.h new file mode 100644 index 0000000..4f415d0 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc57d.h @@ -0,0 +1,1277 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clC57d_h_ +#define _clC57d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC57D_CORE_CHANNEL_DMA (0x0000C57D) + +#define NV_DISP_NOTIFIER 0x00000000 +#define NV_DISP_NOTIFIER_SIZEOF 0x00000010 +#define NV_DISP_NOTIFIER__0 0x00000000 +#define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFIER__0_FIELD 8:8 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE 9:9 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001 +#define NV_DISP_NOTIFIER__0_R1 15:10 +#define NV_DISP_NOTIFIER__0_R2 23:16 +#define NV_DISP_NOTIFIER__0_R3 29:24 +#define NV_DISP_NOTIFIER__0_STATUS 31:30 +#define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002 +#define NV_DISP_NOTIFIER__1 0x00000001 +#define NV_DISP_NOTIFIER__1_R4 31:0 +#define NV_DISP_NOTIFIER__2 0x00000002 +#define NV_DISP_NOTIFIER__2_TIMESTAMP_LO 31:0 +#define NV_DISP_NOTIFIER__3 0x00000003 +#define NV_DISP_NOTIFIER__3_TIMESTAMP_HI 31:0 + + +// dma opcode instructions +#define NVC57D_DMA +#define NVC57D_DMA_OPCODE 31:29 +#define NVC57D_DMA_OPCODE_METHOD 0x00000000 +#define NVC57D_DMA_OPCODE_JUMP 0x00000001 +#define NVC57D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC57D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC57D_DMA_METHOD_COUNT 27:18 +#define NVC57D_DMA_METHOD_OFFSET 13:2 +#define NVC57D_DMA_DATA 31:0 +#define NVC57D_DMA_DATA_NOP 0x00000000 +#define NVC57D_DMA_JUMP_OFFSET 11:2 +#define NVC57D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// if cap SUPPORT_FLEXIBLE_WIN_MAPPING is FALSE, this define can be used to obtain which head a window is mapped to +#define NVC37D_WINDOW_MAPPED_TO_HEAD(w) ((w)>>1) +#define NVC37D_GET_VALID_WINDOWMASK_FOR_HEAD(h) ((1<<((h)*2)) | (1<<((h)*2+1))) + +// class methods +#define NVC57D_PUT (0x00000000) +#define NVC57D_PUT_PTR 9:0 +#define NVC57D_GET (0x00000004) +#define NVC57D_GET_PTR 9:0 +#define NVC57D_UPDATE (0x00000200) +#define NVC57D_UPDATE_SPECIAL_HANDLING 21:20 +#define NVC57D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NVC57D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NVC57D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NVC57D_UPDATE_SPECIAL_HANDLING_REASON 19:12 +#define NVC57D_UPDATE_INHIBIT_INTERRUPTS 24:24 +#define NVC57D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NVC57D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NVC57D_UPDATE_RELEASE_ELV 0:0 +#define NVC57D_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC57D_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC57D_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC57D_SET_CONTEXT_DMA_NOTIFIER (0x00000208) +#define NVC57D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NVC57D_SET_NOTIFIER_CONTROL (0x0000020C) +#define NVC57D_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC57D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC57D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC57D_SET_NOTIFIER_CONTROL_OFFSET 11:4 +#define NVC57D_SET_NOTIFIER_CONTROL_NOTIFY 12:12 +#define NVC57D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NVC57D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NVC57D_SET_CONTROL (0x00000210) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN(i) ((i)+0):((i)+0) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN__SIZE_1 4 +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN_DISABLE (0x00000000) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN_ENABLE (0x00000001) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN0 0:0 +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN0_DISABLE (0x00000000) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN0_ENABLE (0x00000001) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN1 1:1 +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN1_DISABLE (0x00000000) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN1_ENABLE (0x00000001) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN2 2:2 +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN2_DISABLE (0x00000000) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN2_ENABLE (0x00000001) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN3 3:3 +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN3_DISABLE (0x00000000) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN3_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS (0x00000218) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+0):((i)+0) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS (0x0000021C) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVC57D_GET_RG_SCAN_LINE(b) (0x00000220 + (b)*0x00000004) +#define NVC57D_GET_RG_SCAN_LINE_LINE 15:0 +#define NVC57D_GET_RG_SCAN_LINE_VBLANK 16:16 +#define NVC57D_GET_RG_SCAN_LINE_VBLANK_FALSE (0x00000000) +#define NVC57D_GET_RG_SCAN_LINE_VBLANK_TRUE (0x00000001) +#define NVC57D_SET_GET_BLANKING_CTRL(b) (0x00000240 + (b)*0x00000004) +#define NVC57D_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NVC57D_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NVC57D_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NVC57D_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NVC57D_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NVC57D_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) + +#define NVC57D_SOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK 7:0 +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVC57D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NVC57D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NVC57D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NVC57D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NVC57D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NVC57D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NVC57D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NVC57D_SOR_SET_CONTROL_PROTOCOL_DSI (0x0000000A) +#define NVC57D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NVC57D_SOR_SET_CONTROL_DE_SYNC_POLARITY 16:16 +#define NVC57D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC57D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC57D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NVC57D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NVC57D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NVC57D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NVC57D_SOR_SET_CUSTOM_REASON(a) (0x00000304 + (a)*0x00000020) +#define NVC57D_SOR_SET_CUSTOM_REASON_CODE 31:0 +#define NVC57D_SOR_SET_SW_SPARE_A(a) (0x00000308 + (a)*0x00000020) +#define NVC57D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NVC57D_SOR_SET_SW_SPARE_B(a) (0x0000030C + (a)*0x00000020) +#define NVC57D_SOR_SET_SW_SPARE_B_CODE 31:0 + +#define NVC57D_WINDOW_SET_CONTROL(a) (0x00001000 + (a)*0x00000080) +#define NVC57D_WINDOW_SET_CONTROL_OWNER 3:0 +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD(i) (0x00000000 +(i)) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD__SIZE_1 8 +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD0 (0x00000000) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD1 (0x00000001) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD2 (0x00000002) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD3 (0x00000003) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD4 (0x00000004) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD5 (0x00000005) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD6 (0x00000006) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD7 (0x00000007) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_NONE (0x0000000F) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0x00000080) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a) (0x00001008 + (a)*0x00000080) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR(a) (0x0000100C + (a)*0x00000080) +#define NVC57D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVC57D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a) (0x00001010 + (a)*0x00000080) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_MAX_PIXELS_FETCHED_PER_LINE 14:0 +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED 16:16 +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED 28:28 +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS 22:20 +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED 24:24 +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) + +#define NVC57D_HEAD_SET_PROCAMP(a) (0x00002000 + (a)*0x00000400) +#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003) +#define NVC57D_HEAD_SET_PROCAMP_CHROMA_LPF 3:3 +#define NVC57D_HEAD_SET_PROCAMP_CHROMA_LPF_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_PROCAMP_CHROMA_LPF_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 28:28 +#define NVC57D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NVC57D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00002004 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 2:2 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 3:3 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 7:4 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000004) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000005) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000006) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000007) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000008) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 24:24 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 23:12 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN 31:26 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN0 (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN1 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN2 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN3 (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN4 (0x00000004) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN5 (0x00000005) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN6 (0x00000006) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN7 (0x00000007) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN8 (0x00000008) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN9 (0x00000009) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN10 (0x0000000A) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN11 (0x0000000B) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN12 (0x0000000C) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN13 (0x0000000D) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN14 (0x0000000E) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN15 (0x0000000F) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN16 (0x00000010) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN17 (0x00000011) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN18 (0x00000012) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN19 (0x00000013) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN20 (0x00000014) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN21 (0x00000015) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN22 (0x00000016) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN23 (0x00000017) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN24 (0x00000018) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN25 (0x00000019) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN26 (0x0000001A) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN27 (0x0000001B) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN28 (0x0000001C) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN29 (0x0000001D) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN30 (0x0000001E) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN31 (0x0000001F) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_NONE (0x0000003F) +#define NVC57D_HEAD_SET_CONTROL(a) (0x00002008 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CONTROL_STRUCTURE 1:0 +#define NVC57D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE 2:2 +#define NVC57D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_NORMAL (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 11:10 +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 8:4 +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 15:12 +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 23:22 +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 20:16 +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN 28:24 +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000004) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000005) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000006) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000007) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000008) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000009) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000B) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000C) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000D) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000E) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000F) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x00000010) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NVC57D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NVC57D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x0000200C + (a)*0x00000400) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC57D_HEAD_SET_PIXEL_REORDER_CONTROL(a) (0x00002010 + (a)*0x00000400) +#define NVC57D_HEAD_SET_PIXEL_REORDER_CONTROL_BANK_WIDTH 13:0 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00002014 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVC57D_HEAD_SET_DITHER_CONTROL(a) (0x00002018 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NVC57D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_DITHER_CONTROL_BITS 5:4 +#define NVC57D_HEAD_SET_DITHER_CONTROL_BITS_TO_6_BITS (0x00000000) +#define NVC57D_HEAD_SET_DITHER_CONTROL_BITS_TO_8_BITS (0x00000001) +#define NVC57D_HEAD_SET_DITHER_CONTROL_BITS_TO_10_BITS (0x00000002) +#define NVC57D_HEAD_SET_DITHER_CONTROL_BITS_TO_12_BITS (0x00000003) +#define NVC57D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE 2:2 +#define NVC57D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_DITHER_CONTROL_MODE 10:8 +#define NVC57D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NVC57D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NVC57D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NVC57D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NVC57D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NVC57D_HEAD_SET_DITHER_CONTROL_MODE_ROUND (0x00000005) +#define NVC57D_HEAD_SET_DITHER_CONTROL_PHASE 13:12 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x0000201C + (a)*0x00000400) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 0:0 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING 4:4 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 9:8 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NVC57D_HEAD_SET_DISPLAY_ID(a,b) (0x00002020 + (a)*0x00000400 + (b)*0x00000004) +#define NVC57D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00002028 + (a)*0x00000400) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC57D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR(a) (0x0000202C + (a)*0x00000400) +#define NVC57D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVC57D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS(a) (0x00002030 + (a)*0x00000400) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR 2:0 +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_NONE (0x00000000) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W32_H32 (0x00000001) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W64_H64 (0x00000002) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W128_H128 (0x00000003) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W256_H256 (0x00000004) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED 4:4 +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_FALSE (0x00000000) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_TRUE (0x00000001) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS 14:12 +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED 8:8 +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVC57D_HEAD_SET_STALL_LOCK(a) (0x00002034 + (a)*0x00000400) +#define NVC57D_HEAD_SET_STALL_LOCK_ENABLE 0:0 +#define NVC57D_HEAD_SET_STALL_LOCK_ENABLE_FALSE (0x00000000) +#define NVC57D_HEAD_SET_STALL_LOCK_ENABLE_TRUE (0x00000001) +#define NVC57D_HEAD_SET_STALL_LOCK_MODE 2:2 +#define NVC57D_HEAD_SET_STALL_LOCK_MODE_CONTINUOUS (0x00000000) +#define NVC57D_HEAD_SET_STALL_LOCK_MODE_ONE_SHOT (0x00000001) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN 8:4 +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC57D_HEAD_SET_STALL_LOCK_UNSTALL_MODE 12:12 +#define NVC57D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_CRASH_LOCK (0x00000000) +#define NVC57D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_LINE_LOCK (0x00000001) +#define NVC57D_HEAD_SET_STALL_LOCK_TEPOLARITY 14:14 +#define NVC57D_HEAD_SET_STALL_LOCK_TEPOLARITY_POSITIVE_TRUE (0x00000000) +#define NVC57D_HEAD_SET_STALL_LOCK_TEPOLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC57D_HEAD_SET_LOCK_CHAIN(a) (0x00002044 + (a)*0x00000400) +#define NVC57D_HEAD_SET_LOCK_CHAIN_POSITION 3:0 +#define NVC57D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x00002048 + (a)*0x00000400) +#define NVC57D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NVC57D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NVC57D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x0000204C + (a)*0x00000400) +#define NVC57D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NVC57D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NVC57D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x00002058 + (a)*0x00000400) +#define NVC57D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NVC57D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NVC57D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x0000205C + (a)*0x00000400) +#define NVC57D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NVC57D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NVC57D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000400) +#define NVC57D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NVC57D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NVC57D_HEAD_SET_RASTER_SYNC_END(a) (0x00002068 + (a)*0x00000400) +#define NVC57D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NVC57D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NVC57D_HEAD_SET_RASTER_BLANK_END(a) (0x0000206C + (a)*0x00000400) +#define NVC57D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NVC57D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NVC57D_HEAD_SET_RASTER_BLANK_START(a) (0x00002070 + (a)*0x00000400) +#define NVC57D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NVC57D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NVC57D_HEAD_SET_OVERSCAN_COLOR(a) (0x00002078 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OVERSCAN_COLOR_RED_CR 9:0 +#define NVC57D_HEAD_SET_OVERSCAN_COLOR_GREEN_Y 19:10 +#define NVC57D_HEAD_SET_OVERSCAN_COLOR_BLUE_CB 29:20 +#define NVC57D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR(a) (0x0000207C + (a)*0x00000400) +#define NVC57D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_RED_CR 9:0 +#define NVC57D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_GREEN_Y 19:10 +#define NVC57D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_BLUE_CB 29:20 +#define NVC57D_HEAD_SET_HDMI_CTRL(a) (0x00002080 + (a)*0x00000400) +#define NVC57D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NVC57D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NVC57D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NVC57D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NVC57D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NVC57D_HEAD_SET_CONTEXT_DMA_CURSOR(a,b) (0x00002088 + (a)*0x00000400 + (b)*0x00000004) +#define NVC57D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0 +#define NVC57D_HEAD_SET_OFFSET_CURSOR(a,b) (0x00002090 + (a)*0x00000400 + (b)*0x00000004) +#define NVC57D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0 +#define NVC57D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x00002098 + (a)*0x00000400) +#define NVC57D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 0:0 +#define NVC57D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NVC57D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_CURSOR(a) (0x0000209C + (a)*0x00000400) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_FORMAT 7:0 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_SIZE 9:8 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 19:12 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 27:20 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION(a) (0x000020A0 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_K1 7:0 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT 11:8 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT 15:12 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_ZERO (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE 16:16 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_BLEND (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_XOR (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS 20:20 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00002180 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NVC57D_HEAD_SET_CRC_CONTROL(a) (0x00002184 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 5:0 +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_0 (0x00000000) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_1 (0x00000001) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_2 (0x00000002) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_3 (0x00000003) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_4 (0x00000004) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_5 (0x00000005) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_6 (0x00000006) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_7 (0x00000007) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_8 (0x00000008) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_9 (0x00000009) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_10 (0x0000000A) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_11 (0x0000000B) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_12 (0x0000000C) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_13 (0x0000000D) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_14 (0x0000000E) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_15 (0x0000000F) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_16 (0x00000010) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_17 (0x00000011) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_18 (0x00000012) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_19 (0x00000013) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_20 (0x00000014) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_21 (0x00000015) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_22 (0x00000016) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_23 (0x00000017) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_24 (0x00000018) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_25 (0x00000019) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_26 (0x0000001A) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_27 (0x0000001B) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_28 (0x0000001C) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_29 (0x0000001D) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_30 (0x0000001E) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_31 (0x0000001F) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000020) +#define NVC57D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 8:8 +#define NVC57D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NVC57D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC 19:12 +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_NONE (0x00000000) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SF (0x00000030) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR__SIZE_1 8 +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR0 (0x00000050) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR1 (0x00000051) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR2 (0x00000052) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR3 (0x00000053) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR4 (0x00000054) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR5 (0x00000055) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR6 (0x00000056) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR7 (0x00000057) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC 27:20 +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_NONE (0x00000000) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SF (0x00000030) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR__SIZE_1 8 +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR0 (0x00000050) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR1 (0x00000051) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR2 (0x00000052) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR3 (0x00000053) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR4 (0x00000054) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR5 (0x00000055) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR6 (0x00000056) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR7 (0x00000057) +#define NVC57D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 9:9 +#define NVC57D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_PRESENT_CONTROL(a) (0x0000218C + (a)*0x00000400) +#define NVC57D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 0:0 +#define NVC57D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NVC57D_HEAD_SET_SW_SPARE_A(a) (0x00002194 + (a)*0x00000400) +#define NVC57D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NVC57D_HEAD_SET_SW_SPARE_B(a) (0x00002198 + (a)*0x00000400) +#define NVC57D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NVC57D_HEAD_SET_SW_SPARE_C(a) (0x0000219C + (a)*0x00000400) +#define NVC57D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NVC57D_HEAD_SET_SW_SPARE_D(a) (0x000021A0 + (a)*0x00000400) +#define NVC57D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NVC57D_HEAD_SET_DISPLAY_RATE(a) (0x000021A8 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DISPLAY_RATE_RUN_MODE 0:0 +#define NVC57D_HEAD_SET_DISPLAY_RATE_RUN_MODE_CONTINUOUS (0x00000000) +#define NVC57D_HEAD_SET_DISPLAY_RATE_RUN_MODE_ONE_SHOT (0x00000001) +#define NVC57D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_INTERVAL 25:4 +#define NVC57D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH 2:2 +#define NVC57D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE(a) (0x00002214 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVC57D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVC57D_HEAD_SET_MIN_FRAME_IDLE(a) (0x00002218 + (a)*0x00000400) +#define NVC57D_HEAD_SET_MIN_FRAME_IDLE_LEADING_RASTER_LINES 14:0 +#define NVC57D_HEAD_SET_MIN_FRAME_IDLE_TRAILING_RASTER_LINES 30:16 +#define NVC57D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED(a) (0x00002220 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED_ALPHA 7:0 +#define NVC57D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED_RED 31:16 +#define NVC57D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE(a) (0x00002224 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE_GREEN 15:0 +#define NVC57D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE_BLUE 31:16 +#define NVC57D_HEAD_SET_CURSOR_COLOR_NORM_SCALE(a) (0x00002228 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CURSOR_COLOR_NORM_SCALE_VALUE 15:0 +#define NVC57D_HEAD_SET_XOR_BLEND_FACTOR(a) (0x0000222C + (a)*0x00000400) +#define NVC57D_HEAD_SET_XOR_BLEND_FACTOR_LOG2PEAK_LUMINANCE 3:0 +#define NVC57D_HEAD_SET_XOR_BLEND_FACTOR_S1 16:4 +#define NVC57D_HEAD_SET_XOR_BLEND_FACTOR_S2 30:18 +#define NVC57D_HEAD_SET_CLAMP_RANGE_GREEN(a) (0x00002238 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CLAMP_RANGE_GREEN_LOW 11:0 +#define NVC57D_HEAD_SET_CLAMP_RANGE_GREEN_HIGH 27:16 +#define NVC57D_HEAD_SET_CLAMP_RANGE_RED_BLUE(a) (0x0000223C + (a)*0x00000400) +#define NVC57D_HEAD_SET_CLAMP_RANGE_RED_BLUE_LOW 11:0 +#define NVC57D_HEAD_SET_CLAMP_RANGE_RED_BLUE_HIGH 27:16 +#define NVC57D_HEAD_SET_OCSC0CONTROL(a) (0x00002240 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0CONTROL_ENABLE 0:0 +#define NVC57D_HEAD_SET_OCSC0CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_OCSC0CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C00(a) (0x00002244 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C00_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C01(a) (0x00002248 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C01_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C02(a) (0x0000224C + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C02_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C03(a) (0x00002250 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C03_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C10(a) (0x00002254 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C10_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C11(a) (0x00002258 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C11_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C12(a) (0x0000225C + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C12_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C13(a) (0x00002260 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C13_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C20(a) (0x00002264 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C20_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C21(a) (0x00002268 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C21_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C22(a) (0x0000226C + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C22_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C23(a) (0x00002270 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C23_VALUE 20:0 +#define NVC57D_HEAD_SET_OLUT_CONTROL(a) (0x00002280 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OLUT_CONTROL_INTERPOLATE 0:0 +#define NVC57D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_OLUT_CONTROL_MIRROR 1:1 +#define NVC57D_HEAD_SET_OLUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_OLUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_OLUT_CONTROL_MODE 3:2 +#define NVC57D_HEAD_SET_OLUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVC57D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVC57D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVC57D_HEAD_SET_OLUT_CONTROL_SIZE 18:8 +#define NVC57D_HEAD_SET_OLUT_FP_NORM_SCALE(a) (0x00002284 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OLUT_FP_NORM_SCALE_VALUE 31:0 +#define NVC57D_HEAD_SET_CONTEXT_DMA_OLUT(a) (0x00002288 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CONTEXT_DMA_OLUT_HANDLE 31:0 +#define NVC57D_HEAD_SET_OFFSET_OLUT(a) (0x0000228C + (a)*0x00000400) +#define NVC57D_HEAD_SET_OFFSET_OLUT_ORIGIN 31:0 +#define NVC57D_HEAD_SET_OCSC1CONTROL(a) (0x0000229C + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1CONTROL_ENABLE 0:0 +#define NVC57D_HEAD_SET_OCSC1CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_OCSC1CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C00(a) (0x000022A0 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C00_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C01(a) (0x000022A4 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C01_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C02(a) (0x000022A8 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C02_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C03(a) (0x000022AC + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C03_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C10(a) (0x000022B0 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C10_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C11(a) (0x000022B4 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C11_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C12(a) (0x000022B8 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C12_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C13(a) (0x000022BC + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C13_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C20(a) (0x000022C0 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C20_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C21(a) (0x000022C4 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C21_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C22(a) (0x000022C8 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C22_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C23(a) (0x000022CC + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C23_VALUE 20:0 +#define NVC57D_HEAD_SET_TILE_POSITION(a) (0x000022D0 + (a)*0x00000400) +#define NVC57D_HEAD_SET_TILE_POSITION_X 2:0 +#define NVC57D_HEAD_SET_TILE_POSITION_Y 6:4 +#define NVC57D_HEAD_SET_DSC_CONTROL(a) (0x000022D4 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_CONTROL_ENABLE 0:0 +#define NVC57D_HEAD_SET_DSC_CONTROL_ENABLE_FALSE (0x00000000) +#define NVC57D_HEAD_SET_DSC_CONTROL_ENABLE_TRUE (0x00000001) +#define NVC57D_HEAD_SET_DSC_CONTROL_MODE 2:1 +#define NVC57D_HEAD_SET_DSC_CONTROL_MODE_SINGLE (0x00000000) +#define NVC57D_HEAD_SET_DSC_CONTROL_MODE_DUAL (0x00000001) +#define NVC57D_HEAD_SET_DSC_CONTROL_MODE_QUAD (0x00000002) +#define NVC57D_HEAD_SET_DSC_CONTROL_MODE_DROP (0x00000003) +#define NVC57D_HEAD_SET_DSC_CONTROL_AUTO_RESET 3:3 +#define NVC57D_HEAD_SET_DSC_CONTROL_AUTO_RESET_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_DSC_CONTROL_AUTO_RESET_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION 4:4 +#define NVC57D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET 5:5 +#define NVC57D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET_FALSE (0x00000000) +#define NVC57D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET_TRUE (0x00000001) +#define NVC57D_HEAD_SET_DSC_CONTROL_FLATNESS_DET_THRESH 15:6 +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL(a) (0x000022D8 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_ENABLE 0:0 +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_ENABLE_FALSE (0x00000000) +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_ENABLE_TRUE (0x00000001) +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_LOCATION 1:1 +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_VSYNC (0x00000000) +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_VBLANK (0x00000001) +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_SIZE 9:2 +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY 10:10 +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY_ONCE (0x00000001) +#define NVC57D_HEAD_SET_DSC_PPS_HEAD(a) (0x000022DC + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_HEAD_BYTE0 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_HEAD_BYTE1 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_HEAD_BYTE2 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_HEAD_BYTE3 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA0(a) (0x000022E0 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA0_DSC_VERSION_MINOR 3:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA0_DSC_VERSION_MAJOR 7:4 +#define NVC57D_HEAD_SET_DSC_PPS_DATA0_PPS_IDENTIFIER 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA0_RESERVED 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA0_LINEBUF_DEPTH 27:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA0_BITS_PER_COMPONENT 31:28 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1(a) (0x000022E4 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_BITS_PER_PIXEL_HIGH 1:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_VBR_ENABLE 2:2 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_SIMPLE422 3:3 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_CONVERT_RGB 4:4 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_BLOCK_PRED_ENABLE 5:5 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_RESERVED 7:6 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_BITS_PER_PIXEL_LOW 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_PIC_HEIGHT_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_PIC_HEIGHT_LOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA2(a) (0x000022E8 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA2_PIC_WIDTH_HIGH 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA2_PIC_WIDTH_LOW 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA2_SLICE_HEIGHT_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA2_SLICE_HEIGHT_LOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA3(a) (0x000022EC + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA3_SLICE_WIDTH_HIGH 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA3_SLICE_WIDTH_LOW 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA3_CHUNK_SIZE_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA3_CHUNK_SIZE_LOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA4(a) (0x000022F0 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA4_INITIAL_XMIT_DELAY_HIGH 1:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA4_RESERVED 7:2 +#define NVC57D_HEAD_SET_DSC_PPS_DATA4_INITIAL_XMIT_DELAY_LOW 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA4_INITIAL_DEC_DELAY_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA4_INITIAL_DEC_DELAY_LOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA5(a) (0x000022F4 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA5_RESERVED0 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA5_INITIAL_SCALE_VALUE 13:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA5_RESERVED1 15:14 +#define NVC57D_HEAD_SET_DSC_PPS_DATA5_SCALE_INCREMENT_INTERVAL_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA5_SCALE_INCREMENT_INTERVAL_LOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA6(a) (0x000022F8 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA6_SCALE_DECREMENT_INTERVAL_HIGH 3:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA6_RESERVED0 7:4 +#define NVC57D_HEAD_SET_DSC_PPS_DATA6_SCALE_DECREMENT_INTERVAL_LOW 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA6_RESERVED1 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA6_FIRST_LINE_BPG_OFFSET 28:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA6_RESERVED2 31:29 +#define NVC57D_HEAD_SET_DSC_PPS_DATA7(a) (0x000022FC + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA7_NFL_BPG_OFFSET_HIGH 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA7_NFL_BPG_OFFSET_LOW 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA7_SLICE_BPG_OFFSET_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA7_SLICE_BPG_OFFSET_LOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA8(a) (0x00002300 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA8_INITIAL_OFFSET_HIGH 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA8_INITIAL_OFFSET_LOW 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA8_FINAL_OFFSET_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA8_FINAL_OFFSET_LOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA9(a) (0x00002304 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA9_FLATNESS_MIN_QP 4:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA9_RESERVED0 7:5 +#define NVC57D_HEAD_SET_DSC_PPS_DATA9_FLATNESS_MAX_QP 12:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA9_RESERVED1 15:13 +#define NVC57D_HEAD_SET_DSC_PPS_DATA9_RC_MODEL_SIZE_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA9_RC_MODEL_SIZE_LOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA10(a) (0x00002308 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA10_RC_EDGE_FACTOR 3:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA10_RESERVED0 7:4 +#define NVC57D_HEAD_SET_DSC_PPS_DATA10_RC_QUANT_INCR_LIMIT0 12:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA10_RESERVED1 15:13 +#define NVC57D_HEAD_SET_DSC_PPS_DATA10_RC_QUANT_INCR_LIMIT1 20:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA10_RESERVED2 23:21 +#define NVC57D_HEAD_SET_DSC_PPS_DATA10_RC_TGT_OFFSET_LO 27:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA10_RC_TGT_OFFSET_HI 31:28 +#define NVC57D_HEAD_SET_DSC_PPS_DATA11(a) (0x0000230C + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH0 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH1 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH2 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH3 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA12(a) (0x00002310 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH4 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH5 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH6 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH7 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA13(a) (0x00002314 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH8 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH9 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH10 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH11 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA14(a) (0x00002318 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA14_RC_BUF_THRESH12 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA14_RC_BUF_THRESH13 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MAX_QP_HIGH0 18:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MIN_QP0 23:19 +#define NVC57D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_BPG_OFFSET0 29:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MAX_QP_LOW0 31:30 +#define NVC57D_HEAD_SET_DSC_PPS_DATA15(a) (0x0000231C + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_HIGH1 2:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MIN_QP1 7:3 +#define NVC57D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_BPG_OFFSET1 13:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_LOW1 15:14 +#define NVC57D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_HIGH2 18:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MIN_QP2 23:19 +#define NVC57D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_BPG_OFFSET2 29:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_LOW2 31:30 +#define NVC57D_HEAD_SET_DSC_PPS_DATA16(a) (0x00002320 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_HIGH3 2:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MIN_QP3 7:3 +#define NVC57D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_BPG_OFFSET3 13:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_LOW3 15:14 +#define NVC57D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_HIGH4 18:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MIN_QP4 23:19 +#define NVC57D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_BPG_OFFSET4 29:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_LOW4 31:30 +#define NVC57D_HEAD_SET_DSC_PPS_DATA17(a) (0x00002324 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_HIGH5 2:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MIN_QP5 7:3 +#define NVC57D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_BPG_OFFSET5 13:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_LOW5 15:14 +#define NVC57D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_HIGH6 18:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MIN_QP6 23:19 +#define NVC57D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_BPG_OFFSET6 29:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_LOW6 31:30 +#define NVC57D_HEAD_SET_DSC_PPS_DATA18(a) (0x00002328 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_HIGH7 2:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MIN_QP7 7:3 +#define NVC57D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_BPG_OFFSET7 13:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_LOW7 15:14 +#define NVC57D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_HIGH8 18:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MIN_QP8 23:19 +#define NVC57D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_BPG_OFFSET8 29:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_LOW8 31:30 +#define NVC57D_HEAD_SET_DSC_PPS_DATA19(a) (0x0000232C + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_HIGH9 2:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MIN_QP9 7:3 +#define NVC57D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_BPG_OFFSET9 13:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_LOW9 15:14 +#define NVC57D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_HIGH10 18:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MIN_QP10 23:19 +#define NVC57D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_BPG_OFFSET10 29:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_LOW10 31:30 +#define NVC57D_HEAD_SET_DSC_PPS_DATA20(a) (0x00002330 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_HIGH11 2:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MIN_QP11 7:3 +#define NVC57D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_BPG_OFFSET11 13:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_LOW11 15:14 +#define NVC57D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_HIGH12 18:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MIN_QP12 23:19 +#define NVC57D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_BPG_OFFSET12 29:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_LOW12 31:30 +#define NVC57D_HEAD_SET_DSC_PPS_DATA21(a) (0x00002334 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_HIGH13 2:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MIN_QP13 7:3 +#define NVC57D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_BPG_OFFSET13 13:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_LOW13 15:14 +#define NVC57D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_HIGH14 18:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MIN_QP14 23:19 +#define NVC57D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_BPG_OFFSET14 29:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_LOW14 31:30 +#define NVC57D_HEAD_SET_DSC_PPS_DATA22(a) (0x00002338 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA22_NATIVE422 0:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA22_NATIVE420 1:1 +#define NVC57D_HEAD_SET_DSC_PPS_DATA22_RESERVED0 7:2 +#define NVC57D_HEAD_SET_DSC_PPS_DATA22_SECOND_LINE_BPG_OFFSET 12:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA22_RESERVED1 15:13 +#define NVC57D_HEAD_SET_DSC_PPS_DATA22_NSL_BPG_OFFSET_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA22_NSL_BPG_OFFSETLOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA23(a) (0x0000233C + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA23_SECOND_LINE_OFFSET_ADJ_HIGH 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA23_SECOND_LINE_OFFSET_ADJ_LOW 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA23_RESERVED 31:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA24(a) (0x00002340 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA24_RESERVED 31:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA25(a) (0x00002344 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA25_RESERVED 31:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA26(a) (0x00002348 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA26_RESERVED 31:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA27(a) (0x0000234C + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA27_RESERVED 31:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA28(a) (0x00002350 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA28_RESERVED 31:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA29(a) (0x00002354 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA29_RESERVED 31:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA30(a) (0x00002358 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA30_RESERVED 31:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA31(a) (0x0000235C + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA31_RESERVED 31:0 +#define NVC57D_HEAD_SET_RG_MERGE(a) (0x00002360 + (a)*0x00000400) +#define NVC57D_HEAD_SET_RG_MERGE_MODE 1:0 +#define NVC57D_HEAD_SET_RG_MERGE_MODE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_RG_MERGE_MODE_SETUP (0x00000001) +#define NVC57D_HEAD_SET_RG_MERGE_MODE_MASTER (0x00000002) +#define NVC57D_HEAD_SET_RG_MERGE_MODE_SLAVE (0x00000003) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC57d_h diff --git a/userspace/sdks/nv570/inc/class/clc57e.h b/userspace/sdks/nv570/inc/class/clc57e.h new file mode 100644 index 0000000..d613410 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc57e.h @@ -0,0 +1,657 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clC57e_h_ +#define _clC57e_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC57E_WINDOW_CHANNEL_DMA (0x0000C57E) + +// dma opcode instructions +#define NVC57E_DMA +#define NVC57E_DMA_OPCODE 31:29 +#define NVC57E_DMA_OPCODE_METHOD 0x00000000 +#define NVC57E_DMA_OPCODE_JUMP 0x00000001 +#define NVC57E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC57E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC57E_DMA_METHOD_COUNT 27:18 +#define NVC57E_DMA_METHOD_OFFSET 13:2 +#define NVC57E_DMA_DATA 31:0 +#define NVC57E_DMA_DATA_NOP 0x00000000 +#define NVC57E_DMA_JUMP_OFFSET 11:2 +#define NVC57E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVC57E_PUT (0x00000000) +#define NVC57E_PUT_PTR 9:0 +#define NVC57E_GET (0x00000004) +#define NVC57E_GET_PTR 9:0 +#define NVC57E_UPDATE (0x00000200) +#define NVC57E_UPDATE_RELEASE_ELV 0:0 +#define NVC57E_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC57E_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC57E_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC57E_UPDATE_INTERLOCK_WITH_WIN_IMM 12:12 +#define NVC57E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE (0x00000000) +#define NVC57E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE (0x00000001) +#define NVC57E_GET_LINE (0x00000208) +#define NVC57E_GET_LINE_LINE 15:0 +#define NVC57E_SET_SEMAPHORE_CONTROL (0x0000020C) +#define NVC57E_SET_SEMAPHORE_CONTROL_OFFSET 7:0 +#define NVC57E_SET_SEMAPHORE_ACQUIRE (0x00000210) +#define NVC57E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NVC57E_SET_SEMAPHORE_RELEASE (0x00000214) +#define NVC57E_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NVC57E_SET_CONTEXT_DMA_SEMAPHORE (0x00000218) +#define NVC57E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NVC57E_SET_CONTEXT_DMA_NOTIFIER (0x0000021C) +#define NVC57E_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NVC57E_SET_NOTIFIER_CONTROL (0x00000220) +#define NVC57E_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC57E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC57E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC57E_SET_NOTIFIER_CONTROL_OFFSET 11:4 +#define NVC57E_SET_SIZE (0x00000224) +#define NVC57E_SET_SIZE_WIDTH 15:0 +#define NVC57E_SET_SIZE_HEIGHT 31:16 +#define NVC57E_SET_STORAGE (0x00000228) +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC57E_SET_STORAGE_MEMORY_LAYOUT 4:4 +#define NVC57E_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC57E_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC57E_SET_PARAMS (0x0000022C) +#define NVC57E_SET_PARAMS_FORMAT 7:0 +#define NVC57E_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NVC57E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F) +#define NVC57E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NVC57E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC57E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E) +#define NVC57E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC57E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6) +#define NVC57E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NVC57E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9) +#define NVC57E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NVC57E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NVC57E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NVC57E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024) +#define NVC57E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NVC57E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NVC57E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NVC57E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028) +#define NVC57E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029) +#define NVC57E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035) +#define NVC57E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036) +#define NVC57E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038) +#define NVC57E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055) +#define NVC57E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056) +#define NVC57E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058) +#define NVC57E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075) +#define NVC57E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076) +#define NVC57E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078) +#define NVC57E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18 +#define NVC57E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000) +#define NVC57E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001) +#define NVC57E_SET_PARAMS_SWAP_UV 19:19 +#define NVC57E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000) +#define NVC57E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001) +#define NVC57E_SET_PARAMS_FMT_ROUNDING_MODE 22:22 +#define NVC57E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_TO_NEAREST (0x00000000) +#define NVC57E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_DOWN (0x00000001) +#define NVC57E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004) +#define NVC57E_SET_PLANAR_STORAGE_PITCH 12:0 +#define NVC57E_SET_CONTEXT_DMA_ISO(b) (0x00000240 + (b)*0x00000004) +#define NVC57E_SET_CONTEXT_DMA_ISO_HANDLE 31:0 +#define NVC57E_SET_OFFSET(b) (0x00000260 + (b)*0x00000004) +#define NVC57E_SET_OFFSET_ORIGIN 31:0 +#define NVC57E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004) +#define NVC57E_SET_POINT_IN_X 15:0 +#define NVC57E_SET_POINT_IN_Y 31:16 +#define NVC57E_SET_SIZE_IN (0x00000298) +#define NVC57E_SET_SIZE_IN_WIDTH 15:0 +#define NVC57E_SET_SIZE_IN_HEIGHT 31:16 +#define NVC57E_SET_SIZE_OUT (0x000002A4) +#define NVC57E_SET_SIZE_OUT_WIDTH 15:0 +#define NVC57E_SET_SIZE_OUT_HEIGHT 31:16 +#define NVC57E_SET_CONTROL_INPUT_SCALER (0x000002A8) +#define NVC57E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVC57E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVC57E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVC57E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVC57E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVC57E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVC57E_SET_INPUT_SCALER_COEFF_VALUE (0x000002AC) +#define NVC57E_SET_INPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVC57E_SET_INPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVC57E_SET_COMPOSITION_CONTROL (0x000002EC) +#define NVC57E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0 +#define NVC57E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000) +#define NVC57E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001) +#define NVC57E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002) +#define NVC57E_SET_COMPOSITION_CONTROL_DEPTH 11:4 +#define NVC57E_SET_COMPOSITION_CONTROL_BYPASS 16:16 +#define NVC57E_SET_COMPOSITION_CONTROL_BYPASS_DISABLE (0x00000000) +#define NVC57E_SET_COMPOSITION_CONTROL_BYPASS_ENABLE (0x00000001) +#define NVC57E_SET_COMPOSITION_CONSTANT_ALPHA (0x000002F0) +#define NVC57E_SET_COMPOSITION_CONSTANT_ALPHA_K1 7:0 +#define NVC57E_SET_COMPOSITION_CONSTANT_ALPHA_K2 15:8 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT (0x000002F4) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC57E_SET_KEY_ALPHA (0x000002F8) +#define NVC57E_SET_KEY_ALPHA_MIN 15:0 +#define NVC57E_SET_KEY_ALPHA_MAX 31:16 +#define NVC57E_SET_KEY_RED_CR (0x000002FC) +#define NVC57E_SET_KEY_RED_CR_MIN 15:0 +#define NVC57E_SET_KEY_RED_CR_MAX 31:16 +#define NVC57E_SET_KEY_GREEN_Y (0x00000300) +#define NVC57E_SET_KEY_GREEN_Y_MIN 15:0 +#define NVC57E_SET_KEY_GREEN_Y_MAX 31:16 +#define NVC57E_SET_KEY_BLUE_CB (0x00000304) +#define NVC57E_SET_KEY_BLUE_CB_MIN 15:0 +#define NVC57E_SET_KEY_BLUE_CB_MAX 31:16 +#define NVC57E_SET_PRESENT_CONTROL (0x00000308) +#define NVC57E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NVC57E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4 +#define NVC57E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NVC57E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NVC57E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8 +#define NVC57E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000) +#define NVC57E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001) +#define NVC57E_SET_PRESENT_CONTROL_STEREO_MODE 13:12 +#define NVC57E_SET_PRESENT_CONTROL_STEREO_MODE_MONO (0x00000000) +#define NVC57E_SET_PRESENT_CONTROL_STEREO_MODE_PAIR_FLIP (0x00000001) +#define NVC57E_SET_PRESENT_CONTROL_STEREO_MODE_AT_ANY_FRAME (0x00000002) +#define NVC57E_SET_TIMESTAMP_ORIGIN_LO (0x00000340) +#define NVC57E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NVC57E_SET_TIMESTAMP_ORIGIN_HI (0x00000344) +#define NVC57E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NVC57E_SET_UPDATE_TIMESTAMP_LO (0x00000348) +#define NVC57E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NVC57E_SET_UPDATE_TIMESTAMP_HI (0x0000034C) +#define NVC57E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NVC57E_SET_INTERLOCK_FLAGS (0x00000370) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 0:0 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+1):((i)+1) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 1:1 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 2:2 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 3:3 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 4:4 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 5:5 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 6:6 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 7:7 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 8:8 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS (0x00000374) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVC57E_SET_EXT_PACKET_CONTROL (0x00000398) +#define NVC57E_SET_EXT_PACKET_CONTROL_ENABLE 0:0 +#define NVC57E_SET_EXT_PACKET_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57E_SET_EXT_PACKET_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57E_SET_EXT_PACKET_CONTROL_LOCATION 4:4 +#define NVC57E_SET_EXT_PACKET_CONTROL_LOCATION_VSYNC (0x00000000) +#define NVC57E_SET_EXT_PACKET_CONTROL_LOCATION_VBLANK (0x00000001) +#define NVC57E_SET_EXT_PACKET_CONTROL_FREQUENCY 8:8 +#define NVC57E_SET_EXT_PACKET_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVC57E_SET_EXT_PACKET_CONTROL_FREQUENCY_ONCE (0x00000001) +#define NVC57E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE 12:12 +#define NVC57E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_DISABLE (0x00000000) +#define NVC57E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_ENABLE (0x00000001) +#define NVC57E_SET_EXT_PACKET_CONTROL_SIZE 27:16 +#define NVC57E_SET_EXT_PACKET_DATA (0x0000039C) +#define NVC57E_SET_EXT_PACKET_DATA_DB0 7:0 +#define NVC57E_SET_EXT_PACKET_DATA_DB1 15:8 +#define NVC57E_SET_EXT_PACKET_DATA_DB2 23:16 +#define NVC57E_SET_EXT_PACKET_DATA_DB3 31:24 +#define NVC57E_SET_FMT_COEFFICIENT_C00 (0x00000400) +#define NVC57E_SET_FMT_COEFFICIENT_C00_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C01 (0x00000404) +#define NVC57E_SET_FMT_COEFFICIENT_C01_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C02 (0x00000408) +#define NVC57E_SET_FMT_COEFFICIENT_C02_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C03 (0x0000040C) +#define NVC57E_SET_FMT_COEFFICIENT_C03_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C10 (0x00000410) +#define NVC57E_SET_FMT_COEFFICIENT_C10_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C11 (0x00000414) +#define NVC57E_SET_FMT_COEFFICIENT_C11_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C12 (0x00000418) +#define NVC57E_SET_FMT_COEFFICIENT_C12_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C13 (0x0000041C) +#define NVC57E_SET_FMT_COEFFICIENT_C13_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C20 (0x00000420) +#define NVC57E_SET_FMT_COEFFICIENT_C20_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C21 (0x00000424) +#define NVC57E_SET_FMT_COEFFICIENT_C21_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C22 (0x00000428) +#define NVC57E_SET_FMT_COEFFICIENT_C22_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C23 (0x0000042C) +#define NVC57E_SET_FMT_COEFFICIENT_C23_VALUE 20:0 +#define NVC57E_SET_ILUT_CONTROL (0x00000440) +#define NVC57E_SET_ILUT_CONTROL_INTERPOLATE 0:0 +#define NVC57E_SET_ILUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC57E_SET_ILUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC57E_SET_ILUT_CONTROL_MIRROR 1:1 +#define NVC57E_SET_ILUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC57E_SET_ILUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC57E_SET_ILUT_CONTROL_MODE 3:2 +#define NVC57E_SET_ILUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVC57E_SET_ILUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVC57E_SET_ILUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVC57E_SET_ILUT_CONTROL_SIZE 18:8 +#define NVC57E_SET_CONTEXT_DMA_ILUT (0x00000444) +#define NVC57E_SET_CONTEXT_DMA_ILUT_HANDLE 31:0 +#define NVC57E_SET_OFFSET_ILUT (0x00000448) +#define NVC57E_SET_OFFSET_ILUT_ORIGIN 31:0 +#define NVC57E_SET_CSC00CONTROL (0x0000045C) +#define NVC57E_SET_CSC00CONTROL_ENABLE 0:0 +#define NVC57E_SET_CSC00CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57E_SET_CSC00CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57E_SET_CSC00COEFFICIENT_C00 (0x00000460) +#define NVC57E_SET_CSC00COEFFICIENT_C00_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C01 (0x00000464) +#define NVC57E_SET_CSC00COEFFICIENT_C01_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C02 (0x00000468) +#define NVC57E_SET_CSC00COEFFICIENT_C02_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C03 (0x0000046C) +#define NVC57E_SET_CSC00COEFFICIENT_C03_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C10 (0x00000470) +#define NVC57E_SET_CSC00COEFFICIENT_C10_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C11 (0x00000474) +#define NVC57E_SET_CSC00COEFFICIENT_C11_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C12 (0x00000478) +#define NVC57E_SET_CSC00COEFFICIENT_C12_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C13 (0x0000047C) +#define NVC57E_SET_CSC00COEFFICIENT_C13_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C20 (0x00000480) +#define NVC57E_SET_CSC00COEFFICIENT_C20_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C21 (0x00000484) +#define NVC57E_SET_CSC00COEFFICIENT_C21_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C22 (0x00000488) +#define NVC57E_SET_CSC00COEFFICIENT_C22_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C23 (0x0000048C) +#define NVC57E_SET_CSC00COEFFICIENT_C23_VALUE 20:0 +#define NVC57E_SET_CSC0LUT_CONTROL (0x000004A0) +#define NVC57E_SET_CSC0LUT_CONTROL_INTERPOLATE 0:0 +#define NVC57E_SET_CSC0LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC57E_SET_CSC0LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC57E_SET_CSC0LUT_CONTROL_MIRROR 1:1 +#define NVC57E_SET_CSC0LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC57E_SET_CSC0LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC57E_SET_CSC0LUT_CONTROL_ENABLE 4:4 +#define NVC57E_SET_CSC0LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57E_SET_CSC0LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57E_SET_CSC0LUT_SEGMENT_SIZE (0x000004A4) +#define NVC57E_SET_CSC0LUT_SEGMENT_SIZE_IDX 5:0 +#define NVC57E_SET_CSC0LUT_SEGMENT_SIZE_VALUE 18:16 +#define NVC57E_SET_CSC0LUT_ENTRY (0x000004A8) +#define NVC57E_SET_CSC0LUT_ENTRY_IDX 10:0 +#define NVC57E_SET_CSC0LUT_ENTRY_VALUE 31:16 +#define NVC57E_SET_CSC01CONTROL (0x000004BC) +#define NVC57E_SET_CSC01CONTROL_ENABLE 0:0 +#define NVC57E_SET_CSC01CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57E_SET_CSC01CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57E_SET_CSC01COEFFICIENT_C00 (0x000004C0) +#define NVC57E_SET_CSC01COEFFICIENT_C00_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C01 (0x000004C4) +#define NVC57E_SET_CSC01COEFFICIENT_C01_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C02 (0x000004C8) +#define NVC57E_SET_CSC01COEFFICIENT_C02_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C03 (0x000004CC) +#define NVC57E_SET_CSC01COEFFICIENT_C03_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C10 (0x000004D0) +#define NVC57E_SET_CSC01COEFFICIENT_C10_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C11 (0x000004D4) +#define NVC57E_SET_CSC01COEFFICIENT_C11_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C12 (0x000004D8) +#define NVC57E_SET_CSC01COEFFICIENT_C12_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C13 (0x000004DC) +#define NVC57E_SET_CSC01COEFFICIENT_C13_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C20 (0x000004E0) +#define NVC57E_SET_CSC01COEFFICIENT_C20_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C21 (0x000004E4) +#define NVC57E_SET_CSC01COEFFICIENT_C21_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C22 (0x000004E8) +#define NVC57E_SET_CSC01COEFFICIENT_C22_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C23 (0x000004EC) +#define NVC57E_SET_CSC01COEFFICIENT_C23_VALUE 20:0 +#define NVC57E_SET_TMO_CONTROL (0x00000500) +#define NVC57E_SET_TMO_CONTROL_INTERPOLATE 0:0 +#define NVC57E_SET_TMO_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC57E_SET_TMO_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC57E_SET_TMO_CONTROL_SAT_MODE 3:2 +#define NVC57E_SET_TMO_CONTROL_SIZE 18:8 +#define NVC57E_SET_TMO_LOW_INTENSITY_ZONE (0x00000508) +#define NVC57E_SET_TMO_LOW_INTENSITY_ZONE_END 29:16 +#define NVC57E_SET_TMO_LOW_INTENSITY_VALUE (0x0000050C) +#define NVC57E_SET_TMO_LOW_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVC57E_SET_TMO_LOW_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVC57E_SET_TMO_LOW_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVC57E_SET_TMO_MEDIUM_INTENSITY_ZONE (0x00000510) +#define NVC57E_SET_TMO_MEDIUM_INTENSITY_ZONE_START 13:0 +#define NVC57E_SET_TMO_MEDIUM_INTENSITY_ZONE_END 29:16 +#define NVC57E_SET_TMO_MEDIUM_INTENSITY_VALUE (0x00000514) +#define NVC57E_SET_TMO_MEDIUM_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVC57E_SET_TMO_MEDIUM_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVC57E_SET_TMO_MEDIUM_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVC57E_SET_TMO_HIGH_INTENSITY_ZONE (0x00000518) +#define NVC57E_SET_TMO_HIGH_INTENSITY_ZONE_START 13:0 +#define NVC57E_SET_TMO_HIGH_INTENSITY_VALUE (0x0000051C) +#define NVC57E_SET_TMO_HIGH_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVC57E_SET_TMO_HIGH_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVC57E_SET_TMO_HIGH_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVC57E_SET_CONTEXT_DMA_TMO_LUT (0x00000528) +#define NVC57E_SET_CONTEXT_DMA_TMO_LUT_HANDLE 31:0 +#define NVC57E_SET_OFFSET_TMO_LUT (0x0000052C) +#define NVC57E_SET_OFFSET_TMO_LUT_ORIGIN 31:0 +#define NVC57E_SET_CSC10CONTROL (0x0000053C) +#define NVC57E_SET_CSC10CONTROL_ENABLE 0:0 +#define NVC57E_SET_CSC10CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57E_SET_CSC10CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57E_SET_CSC10COEFFICIENT_C00 (0x00000540) +#define NVC57E_SET_CSC10COEFFICIENT_C00_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C01 (0x00000544) +#define NVC57E_SET_CSC10COEFFICIENT_C01_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C02 (0x00000548) +#define NVC57E_SET_CSC10COEFFICIENT_C02_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C03 (0x0000054C) +#define NVC57E_SET_CSC10COEFFICIENT_C03_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C10 (0x00000550) +#define NVC57E_SET_CSC10COEFFICIENT_C10_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C11 (0x00000554) +#define NVC57E_SET_CSC10COEFFICIENT_C11_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C12 (0x00000558) +#define NVC57E_SET_CSC10COEFFICIENT_C12_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C13 (0x0000055C) +#define NVC57E_SET_CSC10COEFFICIENT_C13_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C20 (0x00000560) +#define NVC57E_SET_CSC10COEFFICIENT_C20_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C21 (0x00000564) +#define NVC57E_SET_CSC10COEFFICIENT_C21_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C22 (0x00000568) +#define NVC57E_SET_CSC10COEFFICIENT_C22_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C23 (0x0000056C) +#define NVC57E_SET_CSC10COEFFICIENT_C23_VALUE 20:0 +#define NVC57E_SET_CSC1LUT_CONTROL (0x00000580) +#define NVC57E_SET_CSC1LUT_CONTROL_INTERPOLATE 0:0 +#define NVC57E_SET_CSC1LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC57E_SET_CSC1LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC57E_SET_CSC1LUT_CONTROL_MIRROR 1:1 +#define NVC57E_SET_CSC1LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC57E_SET_CSC1LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC57E_SET_CSC1LUT_CONTROL_ENABLE 4:4 +#define NVC57E_SET_CSC1LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57E_SET_CSC1LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57E_SET_CSC1LUT_SEGMENT_SIZE (0x00000584) +#define NVC57E_SET_CSC1LUT_SEGMENT_SIZE_IDX 5:0 +#define NVC57E_SET_CSC1LUT_SEGMENT_SIZE_VALUE 18:16 +#define NVC57E_SET_CSC1LUT_ENTRY (0x00000588) +#define NVC57E_SET_CSC1LUT_ENTRY_IDX 10:0 +#define NVC57E_SET_CSC1LUT_ENTRY_VALUE 31:16 +#define NVC57E_SET_CSC11CONTROL (0x0000059C) +#define NVC57E_SET_CSC11CONTROL_ENABLE 0:0 +#define NVC57E_SET_CSC11CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57E_SET_CSC11CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57E_SET_CSC11COEFFICIENT_C00 (0x000005A0) +#define NVC57E_SET_CSC11COEFFICIENT_C00_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C01 (0x000005A4) +#define NVC57E_SET_CSC11COEFFICIENT_C01_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C02 (0x000005A8) +#define NVC57E_SET_CSC11COEFFICIENT_C02_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C03 (0x000005AC) +#define NVC57E_SET_CSC11COEFFICIENT_C03_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C10 (0x000005B0) +#define NVC57E_SET_CSC11COEFFICIENT_C10_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C11 (0x000005B4) +#define NVC57E_SET_CSC11COEFFICIENT_C11_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C12 (0x000005B8) +#define NVC57E_SET_CSC11COEFFICIENT_C12_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C13 (0x000005BC) +#define NVC57E_SET_CSC11COEFFICIENT_C13_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C20 (0x000005C0) +#define NVC57E_SET_CSC11COEFFICIENT_C20_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C21 (0x000005C4) +#define NVC57E_SET_CSC11COEFFICIENT_C21_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C22 (0x000005C8) +#define NVC57E_SET_CSC11COEFFICIENT_C22_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C23 (0x000005CC) +#define NVC57E_SET_CSC11COEFFICIENT_C23_VALUE 20:0 +#define NVC57E_SET_CLAMP_RANGE (0x000005D0) +#define NVC57E_SET_CLAMP_RANGE_LOW 15:0 +#define NVC57E_SET_CLAMP_RANGE_HIGH 31:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC57e_h diff --git a/userspace/sdks/nv570/inc/class/clc57esw.h b/userspace/sdks/nv570/inc/class/clc57esw.h new file mode 100644 index 0000000..8c106b4 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc57esw.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2009-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc57e_sw_h_ +#define _clc57e_sw_h_ + +/* This file is *not* auto-generated. */ + +#define NVC57E_WINDOWS_NOTIFY_RM (0x0000058C) +#define NVC57E_WINDOWS_NOTIFY_RM_VSYNC_STATE_CHANGE 0:0 +#define NVC57E_WINDOWS_NOTIFY_RM_VSYNC_STATE_CHANGE_FALSE (0x00000000) +#define NVC57E_WINDOWS_NOTIFY_RM_VSYNC_STATE_CHANGE_TRUE (0x00000001) +#define NVC57E_WINDOWS_NOTIFY_RM_VSYNC_STATE 1:1 +#define NVC57E_WINDOWS_NOTIFY_RM_VSYNC_STATE_OFF (0x00000000) +#define NVC57E_WINDOWS_NOTIFY_RM_VSYNC_STATE_ON (0x00000001) +#define NVC57E_WINDOWS_NOTIFY_RM_ASSOCIATED_HEAD 7:4 + +#define SwSetMClkSwitch Reserved05[1] + +#define NVC57E_SW_SET_MCLK_SWITCH (0x000002B4) +#define NVC57E_SW_SET_MCLK_SWITCH_ENABLE 0:0 +#define NVC57E_SW_SET_MCLK_SWITCH_ENABLE_FALSE (0x00000000) +#define NVC57E_SW_SET_MCLK_SWITCH_ENABLE_TRUE (0x00000001) + +#endif // _clc57e_sw_h_ + diff --git a/userspace/sdks/nv570/inc/class/clc58b.h b/userspace/sdks/nv570/inc/class/clc58b.h new file mode 100644 index 0000000..4972f04 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc58b.h @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc58b.finn +// + +#define TURING_VMMU_A (0xc58bU) /* finn: Evaluated from "TURING_VMMU_A_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* + * @brief NvAlloc parameters for TuringVmmuA class + * + * This class represents mapping between guest physical and system physical. + * Will also be used to represent VF specific state for a given guest. + * + * gfid [in] + * GFID of VF + */ + +#define TURING_VMMU_A_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc58bU) + +typedef struct TURING_VMMU_A_ALLOCATION_PARAMETERS { + NvHandle hHostVgpuDevice; +} TURING_VMMU_A_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clc597.h b/userspace/sdks/nv570/inc/class/clc597.h new file mode 100644 index 0000000..711dae1 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc597.h @@ -0,0 +1,4352 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_turing_a_h_ +#define _cl_turing_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl turing_a */ + +#include "nvtypes.h" + +#define TURING_A 0xC597 + +#define NVC597_SET_OBJECT 0x0000 +#define NVC597_SET_OBJECT_CLASS_ID 15:0 +#define NVC597_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC597_NO_OPERATION 0x0100 +#define NVC597_NO_OPERATION_V 31:0 + +#define NVC597_SET_NOTIFY_A 0x0104 +#define NVC597_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC597_SET_NOTIFY_B 0x0108 +#define NVC597_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC597_NOTIFY 0x010c +#define NVC597_NOTIFY_TYPE 31:0 +#define NVC597_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC597_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC597_WAIT_FOR_IDLE 0x0110 +#define NVC597_WAIT_FOR_IDLE_V 31:0 + +#define NVC597_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC597_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC597_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC597_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC597_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC597_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC597_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC597_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC597_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC597_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC597_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC597_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC597_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC597_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC597_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC597_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC597_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC597_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC597_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC597_SEND_GO_IDLE 0x013c +#define NVC597_SEND_GO_IDLE_V 31:0 + +#define NVC597_PM_TRIGGER 0x0140 +#define NVC597_PM_TRIGGER_V 31:0 + +#define NVC597_PM_TRIGGER_WFI 0x0144 +#define NVC597_PM_TRIGGER_WFI_V 31:0 + +#define NVC597_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC597_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC597_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC597_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC597_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC597_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC597_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC597_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC597_LINE_LENGTH_IN 0x0180 +#define NVC597_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC597_LINE_COUNT 0x0184 +#define NVC597_LINE_COUNT_VALUE 31:0 + +#define NVC597_OFFSET_OUT_UPPER 0x0188 +#define NVC597_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC597_OFFSET_OUT 0x018c +#define NVC597_OFFSET_OUT_VALUE 31:0 + +#define NVC597_PITCH_OUT 0x0190 +#define NVC597_PITCH_OUT_VALUE 31:0 + +#define NVC597_SET_DST_BLOCK_SIZE 0x0194 +#define NVC597_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC597_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC597_SET_DST_WIDTH 0x0198 +#define NVC597_SET_DST_WIDTH_V 31:0 + +#define NVC597_SET_DST_HEIGHT 0x019c +#define NVC597_SET_DST_HEIGHT_V 31:0 + +#define NVC597_SET_DST_DEPTH 0x01a0 +#define NVC597_SET_DST_DEPTH_V 31:0 + +#define NVC597_SET_DST_LAYER 0x01a4 +#define NVC597_SET_DST_LAYER_V 31:0 + +#define NVC597_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC597_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC597_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC597_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC597_LAUNCH_DMA 0x01b0 +#define NVC597_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC597_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC597_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC597_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC597_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC597_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC597_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC597_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC597_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC597_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC597_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC597_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC597_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC597_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC597_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC597_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC597_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC597_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC597_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC597_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC597_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC597_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC597_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC597_LOAD_INLINE_DATA 0x01b4 +#define NVC597_LOAD_INLINE_DATA_V 31:0 + +#define NVC597_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC597_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC597_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC597_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC597_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC597_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC597_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC597_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC597_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC597_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC597_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC597_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC597_RUN_DS_NOW 0x0200 +#define NVC597_RUN_DS_NOW_V 31:0 + +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC597_SET_GS_MODE 0x0208 +#define NVC597_SET_GS_MODE_TYPE 0:0 +#define NVC597_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVC597_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVC597_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC597_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC597_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC597_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC597_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC597_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_GS_DM_FIFO 0x0214 +#define NVC597_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC597_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC597_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC597_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC597_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC597_INVALIDATE_SHADER_CACHES 0x021c +#define NVC597_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC597_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC597_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC597_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC597_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC597_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC597_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC597_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC597_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC597_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC597_SET_INSTANCE_COUNT 0x0220 +#define NVC597_SET_INSTANCE_COUNT_V 31:0 + +#define NVC597_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVC597_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVC597_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC597_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVC597_SET_MME_VERSION 0x0234 +#define NVC597_SET_MME_VERSION_MAJOR 7:0 + +#define NVC597_SET_INDEX_BUFFER_SIZE_A 0x0238 +#define NVC597_SET_INDEX_BUFFER_SIZE_A_UPPER 7:0 + +#define NVC597_SET_INDEX_BUFFER_SIZE_B 0x023c +#define NVC597_SET_INDEX_BUFFER_SIZE_B_LOWER 31:0 + +#define NVC597_SET_ROOT_TABLE_VISIBILITY(i) (0x0240+(i)*4) +#define NVC597_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP0_ENABLE 1:0 +#define NVC597_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP1_ENABLE 5:4 +#define NVC597_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP2_ENABLE 9:8 +#define NVC597_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP3_ENABLE 13:12 +#define NVC597_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP4_ENABLE 17:16 + +#define NVC597_SET_DRAW_CONTROL_A 0x0260 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY 3:0 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_POINTS 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_LINES 0x00000001 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_QUADS 0x00000007 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_PATCH 0x0000000E +#define NVC597_SET_DRAW_CONTROL_A_PRIMITIVE_ID 4:4 +#define NVC597_SET_DRAW_CONTROL_A_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ID 6:5 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ID_FIRST 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC597_SET_DRAW_CONTROL_A_SPLIT_MODE 8:7 +#define NVC597_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC597_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC597_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE 9:9 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 +#define NVC597_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX 10:10 +#define NVC597_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_FALSE 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_TRUE 0x00000001 +#define NVC597_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX 11:11 +#define NVC597_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_FALSE 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_TRUE 0x00000001 + +#define NVC597_SET_DRAW_CONTROL_B 0x0264 +#define NVC597_SET_DRAW_CONTROL_B_INSTANCE_COUNT 31:0 + +#define NVC597_DRAW_INDEX_BUFFER_BEGIN_END_A 0x0268 +#define NVC597_DRAW_INDEX_BUFFER_BEGIN_END_A_FIRST 31:0 + +#define NVC597_DRAW_INDEX_BUFFER_BEGIN_END_B 0x026c +#define NVC597_DRAW_INDEX_BUFFER_BEGIN_END_B_COUNT 31:0 + +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_A 0x0270 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_A_START 31:0 + +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_B 0x0274 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_B_COUNT 31:0 + +#define NVC597_INVALIDATE_RASTER_CACHE_NO_WFI 0x027c +#define NVC597_INVALIDATE_RASTER_CACHE_NO_WFI_V 0:0 + +#define NVC597_SET_COLOR_RENDER_TO_ZETA_SURFACE 0x02b8 +#define NVC597_SET_COLOR_RENDER_TO_ZETA_SURFACE_V 0:0 +#define NVC597_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_FALSE 0x00000000 +#define NVC597_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_TRUE 0x00000001 + +#define NVC597_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION 0x02bc +#define NVC597_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V 0:0 +#define NVC597_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_FALSE 0x00000000 +#define NVC597_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_TRUE 0x00000001 + +#define NVC597_INCREMENT_SYNC_POINT 0x02c8 +#define NVC597_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC597_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC597_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC597_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC597_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC597_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC597_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC597_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC597_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC597_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC597_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVC597_DECOMPRESS_SURFACE 0x02e0 +#define NVC597_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC597_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC597_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC597_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC597_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC597_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC597_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC597_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC597_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC597_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC597_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC597_SET_ZCULL_SUBREGION 0x02e8 +#define NVC597_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC597_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC597_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC597_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC597_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC597_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC597_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC597_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC597_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC597_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC597_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC597_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC597_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC597_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC597_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC597_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC597_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC597_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC597_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC597_DRAW_ZERO_INDEX 0x0304 +#define NVC597_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC597_SET_L1_CONFIGURATION 0x0308 +#define NVC597_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC597_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC597_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC597_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC597_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC597_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC597_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC597_SET_SPA_VERSION 0x0310 +#define NVC597_SET_SPA_VERSION_MINOR 7:0 +#define NVC597_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC597_SET_TIMESLICE_BATCH_LIMIT 0x0314 +#define NVC597_SET_TIMESLICE_BATCH_LIMIT_BATCH_LIMIT 15:0 + +#define NVC597_SET_SNAP_GRID_LINE 0x0318 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC597_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC597_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC597_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC597_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC597_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC597_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC597_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC597_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC597_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC597_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC597_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC597_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC597_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC597_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC597_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC597_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC597_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC597_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC597_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC597_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC597_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC597_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC597_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC597_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC597_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC597_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC597_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC597_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC597_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC597_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC597_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC597_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC597_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC597_RESERVED_TG07 0x033c +#define NVC597_RESERVED_TG07_V 0:0 + +#define NVC597_RESERVED_TG08 0x0340 +#define NVC597_RESERVED_TG08_V 0:0 + +#define NVC597_RESERVED_TG09 0x0344 +#define NVC597_RESERVED_TG09_V 0:0 + +#define NVC597_RESERVED_TG10 0x0348 +#define NVC597_RESERVED_TG10_V 0:0 + +#define NVC597_RESERVED_TG11 0x034c +#define NVC597_RESERVED_TG11_V 0:0 + +#define NVC597_RESERVED_TG12 0x0350 +#define NVC597_RESERVED_TG12_V 0:0 + +#define NVC597_RESERVED_TG13 0x0354 +#define NVC597_RESERVED_TG13_V 0:0 + +#define NVC597_RESERVED_TG14 0x0358 +#define NVC597_RESERVED_TG14_V 0:0 + +#define NVC597_RESERVED_TG15 0x035c +#define NVC597_RESERVED_TG15_V 0:0 + +#define NVC597_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC597_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC597_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC597_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC597_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC597_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC597_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC597_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC597_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC597_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC597_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC597_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC597_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC597_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC597_SET_RASTER_ENABLE 0x037c +#define NVC597_SET_RASTER_ENABLE_V 0:0 +#define NVC597_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC597_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC597_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC597_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC597_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC597_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC597_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC597_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC597_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC597_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC597_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVC597_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVC597_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVC597_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVC597_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVC597_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVC597_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVC597_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVC597_SET_ROOT_TABLE_SELECTOR 0x0504 +#define NVC597_SET_ROOT_TABLE_SELECTOR_ROOT_TABLE 2:0 +#define NVC597_SET_ROOT_TABLE_SELECTOR_OFFSET 15:8 + +#define NVC597_LOAD_ROOT_TABLE 0x0508 +#define NVC597_LOAD_ROOT_TABLE_V 31:0 + +#define NVC597_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVC597_SET_MME_MEM_ADDRESS_A_UPPER 7:0 + +#define NVC597_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVC597_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVC597_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVC597_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVC597_MME_DMA_READ 0x055c +#define NVC597_MME_DMA_READ_LENGTH 31:0 + +#define NVC597_MME_DMA_READ_FIFOED 0x0560 +#define NVC597_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVC597_MME_DMA_WRITE 0x0564 +#define NVC597_MME_DMA_WRITE_LENGTH 31:0 + +#define NVC597_MME_DMA_REDUCTION 0x0568 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVC597_MME_DMA_SYSMEMBAR 0x056c +#define NVC597_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVC597_MME_DMA_SYNC 0x0570 +#define NVC597_MME_DMA_SYNC_VALUE 31:0 + +#define NVC597_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NVC597_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NVC597_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NVC597_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NVC597_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NVC597_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NVC597_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NVC597_SET_VERTEX_STREAM_SIZE_A(j) (0x0600+(j)*8) +#define NVC597_SET_VERTEX_STREAM_SIZE_A_UPPER 7:0 + +#define NVC597_SET_VERTEX_STREAM_SIZE_B(j) (0x0604+(j)*8) +#define NVC597_SET_VERTEX_STREAM_SIZE_B_LOWER 31:0 + +#define NVC597_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC597_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC597_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC597_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC597_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC597_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC597_SET_RASTER_INPUT 0x0740 +#define NVC597_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC597_SET_STREAM_OUTPUT 0x0744 +#define NVC597_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC597_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC597_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC597_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC597_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC597_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC597_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC597_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC597_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC597_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC597_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC597_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC597_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC597_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC597_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC597_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC597_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC597_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC597_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC597_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC597_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC597_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC597_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC597_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC597_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC597_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVC597_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC597_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC597_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC597_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC597_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC597_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC597_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC597_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC597_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC597_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC597_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC597_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC597_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC597_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC597_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC597_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC597_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC597_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC597_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC597_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC597_SET_ZCULL_STORAGE_B 0x07ec +#define NVC597_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC597_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC597_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC597_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC597_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC597_SET_ZT_READ_ONLY 0x07f8 +#define NVC597_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC597_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC597_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC597_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC597_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC597_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC597_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC597_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC597_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC597_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC597_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC597_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC597_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC597_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC597_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC597_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC597_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC597_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC597_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC597_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC597_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC597_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC597_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC597_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC597_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC597_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC597_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC597_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC597_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC597_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC597_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC597_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC597_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC597_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC597_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC597_SET_COLOR_TARGET_RESERVED_A(j) (0x0824+(j)*64) +#define NVC597_SET_COLOR_TARGET_RESERVED_A_V 0:0 + +#define NVC597_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC597_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC597_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC597_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC597_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC597_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC597_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC597_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC597_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC597_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC597_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC597_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC597_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC597_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC597_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC597_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC597_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC597_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC597_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC597_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC597_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC597_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC597_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC597_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC597_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC597_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC597_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC597_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC597_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC597_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC597_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC597_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC597_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC597_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC597_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC597_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC597_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC597_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC597_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC597_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC597_SET_STATISTICS_COUNTER 0x0d68 +#define NVC597_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC597_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC597_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC597_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC597_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC597_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC597_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC597_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC597_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC597_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC597_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC597_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC597_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC597_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC597_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC597_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC597_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVC597_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC597_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC597_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC597_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC597_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC597_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC597_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC597_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC597_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC597_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC597_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC597_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC597_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC597_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC597_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC597_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC597_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC597_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC597_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC597_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC597_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC597_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC597_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC597_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC597_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC597_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC597_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC597_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC597_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC597_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC597_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC597_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC597_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC597_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC597_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC597_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC597_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC597_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC597_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC597_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC597_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC597_SET_POLY_SMOOTH 0x0db4 +#define NVC597_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC597_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC597_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC597_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC597_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC597_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC597_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC597_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC597_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC597_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_PATCH 0x0dcc +#define NVC597_SET_PATCH_SIZE 7:0 + +#define NVC597_SET_ITERATED_BLEND 0x0dd0 +#define NVC597_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC597_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC597_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC597_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC597_SET_ZCULL_CRITERION 0x0dd8 +#define NVC597_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC597_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC597_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC597_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC597_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC597_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC597_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC597_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC597_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC597_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC597_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC597_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC597_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC597_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC597_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC597_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC597_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC597_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC597_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC597_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC597_SET_SCISSOR_ENABLE_V 0:0 +#define NVC597_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC597_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC597_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC597_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC597_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC597_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC597_SET_VPC_PERF_KNOB 0x0f14 +#define NVC597_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC597_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC597_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC597_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC597_PM_LOCAL_TRIGGER 0x0f18 +#define NVC597_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC597_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC597_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC597_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC597_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC597_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC597_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC597_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC597_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC597_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC597_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC597_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC597_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC597_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC597_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC597_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC597_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC597_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC597_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC597_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC597_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC597_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC597_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC597_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC597_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC597_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC597_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC597_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC597_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC597_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC597_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC597_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC597_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC597_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC597_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC597_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC597_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC597_SET_SAMPLE_MASK 0x0fa4 +#define NVC597_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC597_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC597_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC597_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC597_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC597_SET_CT_MRT_ENABLE 0x0fac +#define NVC597_SET_CT_MRT_ENABLE_V 0:0 +#define NVC597_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC597_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC597_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC597_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC597_SET_TIR 0x0fb4 +#define NVC597_SET_TIR_MODE 1:0 +#define NVC597_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC597_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC597_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC597_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC597_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC597_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC597_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC597_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC597_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC597_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC597_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC597_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC597_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC597_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC597_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC597_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC597_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC597_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC597_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC597_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_TIR_MODULATION 0x0fd4 +#define NVC597_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC597_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC597_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC597_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC597_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC597_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC597_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC597_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC597_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC597_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC597_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC597_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC597_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC597_SET_ZT_A 0x0fe0 +#define NVC597_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_ZT_B 0x0fe4 +#define NVC597_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_ZT_FORMAT 0x0fe8 +#define NVC597_SET_ZT_FORMAT_V 4:0 +#define NVC597_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC597_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC597_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC597_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC597_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC597_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC597_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC597_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC597_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC597_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC597_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC597_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC597_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC597_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC597_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC597_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC597_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC597_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC597_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC597_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC597_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC597_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC597_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC597_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC597_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC597_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC597_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC597_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC597_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC597_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC597_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC597_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC597_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC597_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC597_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC597_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC597_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC597_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC597_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC597_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC597_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC597_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC597_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC597_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC597_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC597_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD02 0x102c +#define NVC597_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC597_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC597_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC597_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC597_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC597_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC597_SET_SPARE_NOOP01 0x1044 +#define NVC597_SET_SPARE_NOOP01_V 31:0 + +#define NVC597_SET_SPARE_NOOP02 0x1048 +#define NVC597_SET_SPARE_NOOP02_V 31:0 + +#define NVC597_SET_SPARE_NOOP03 0x104c +#define NVC597_SET_SPARE_NOOP03_V 31:0 + +#define NVC597_SET_SPARE_NOOP04 0x1050 +#define NVC597_SET_SPARE_NOOP04_V 31:0 + +#define NVC597_SET_SPARE_NOOP05 0x1054 +#define NVC597_SET_SPARE_NOOP05_V 31:0 + +#define NVC597_SET_SPARE_NOOP06 0x1058 +#define NVC597_SET_SPARE_NOOP06_V 31:0 + +#define NVC597_SET_SPARE_NOOP07 0x105c +#define NVC597_SET_SPARE_NOOP07_V 31:0 + +#define NVC597_SET_SPARE_NOOP08 0x1060 +#define NVC597_SET_SPARE_NOOP08_V 31:0 + +#define NVC597_SET_SPARE_NOOP09 0x1064 +#define NVC597_SET_SPARE_NOOP09_V 31:0 + +#define NVC597_SET_SPARE_NOOP10 0x1068 +#define NVC597_SET_SPARE_NOOP10_V 31:0 + +#define NVC597_SET_SPARE_NOOP11 0x106c +#define NVC597_SET_SPARE_NOOP11_V 31:0 + +#define NVC597_SET_SPARE_NOOP12 0x1070 +#define NVC597_SET_SPARE_NOOP12_V 31:0 + +#define NVC597_SET_SPARE_NOOP13 0x1074 +#define NVC597_SET_SPARE_NOOP13_V 31:0 + +#define NVC597_SET_SPARE_NOOP14 0x1078 +#define NVC597_SET_SPARE_NOOP14_V 31:0 + +#define NVC597_SET_SPARE_NOOP15 0x107c +#define NVC597_SET_SPARE_NOOP15_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC597_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC597_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC597_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC597_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC597_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC597_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC597_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC597_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC597_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC597_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC597_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC597_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC597_UNBIND_ALL 0x10f4 +#define NVC597_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC597_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC597_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC597_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC597_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC597_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC597_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC597_NO_OPERATION_DATA_HI 0x110c +#define NVC597_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC597_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC597_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC597_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC597_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC597_PM_TRIGGER_END 0x1114 +#define NVC597_PM_TRIGGER_END_V 31:0 + +#define NVC597_SET_VERTEX_ID_BASE 0x1118 +#define NVC597_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC597_SET_STENCIL_COMPRESSION 0x111c +#define NVC597_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC597_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC597_SET_TIR_CONTROL 0x1130 +#define NVC597_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC597_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC597_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC597_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC597_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC597_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC597_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC597_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC597_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 + +#define NVC597_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC597_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC597_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC597_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC597_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC597_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC597_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC597_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC597_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC597_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC597_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC597_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC597_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC597_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC597_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC597_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC597_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC597_FLUSH_PENDING_WRITES 0x1144 +#define NVC597_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC597_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC597_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC597_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC597_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC597_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC597_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC597_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC597_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC597_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC597_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC597_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC597_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC597_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC597_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC597_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC597_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC597_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC597_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC597_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC597_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC597_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC597_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_SCREEN_STATE_MASK 0x1204 +#define NVC597_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC597_SET_ZT_SPARSE 0x1208 +#define NVC597_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC597_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC597_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC597_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_SET_CT_SELECT 0x121c +#define NVC597_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC597_SET_CT_SELECT_TARGET0 6:4 +#define NVC597_SET_CT_SELECT_TARGET1 9:7 +#define NVC597_SET_CT_SELECT_TARGET2 12:10 +#define NVC597_SET_CT_SELECT_TARGET3 15:13 +#define NVC597_SET_CT_SELECT_TARGET4 18:16 +#define NVC597_SET_CT_SELECT_TARGET5 21:19 +#define NVC597_SET_CT_SELECT_TARGET6 24:22 +#define NVC597_SET_CT_SELECT_TARGET7 27:25 + +#define NVC597_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC597_SET_ZT_SIZE_A 0x1228 +#define NVC597_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC597_SET_ZT_SIZE_B 0x122c +#define NVC597_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC597_SET_ZT_SIZE_C 0x1230 +#define NVC597_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC597_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC597_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC597_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC597_SET_SAMPLER_BINDING 0x1234 +#define NVC597_SET_SAMPLER_BINDING_V 0:0 +#define NVC597_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC597_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC597_DRAW_AUTO 0x123c +#define NVC597_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC597_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC597_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC597_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC597_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC597_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC597_SET_BACK_END_COPY_A 0x1264 +#define NVC597_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC597_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC597_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC597_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC597_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BACK_END_COPY_B 0x1268 +#define NVC597_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC597_SET_BACK_END_COPY_C 0x126c +#define NVC597_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC597_SET_BACK_END_COPY_D 0x1270 +#define NVC597_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC597_SET_BACK_END_COPY_E 0x1274 +#define NVC597_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC597_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC597_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVC597_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC597_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC597_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC597_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC597_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC597_CLEAR_ZCULL_REGION 0x12c8 +#define NVC597_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC597_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC597_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC597_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC597_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC597_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC597_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC597_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC597_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC597_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC597_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC597_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC597_SET_DEPTH_TEST 0x12cc +#define NVC597_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC597_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_FILL_MODE 0x12d0 +#define NVC597_SET_FILL_MODE_V 31:0 +#define NVC597_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC597_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC597_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC597_SET_SHADE_MODE 0x12d4 +#define NVC597_SET_SHADE_MODE_V 31:0 +#define NVC597_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC597_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC597_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC597_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC597_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC597_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC597_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC597_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC597_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC597_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC597_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC597_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_DEPTH_WRITE 0x12e8 +#define NVC597_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC597_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_ALPHA_TEST 0x12ec +#define NVC597_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC597_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC597_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC597_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC597_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC597_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC597_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC597_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC597_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC597_D3D_SET_CULL_MODE 0x1308 +#define NVC597_D3D_SET_CULL_MODE_V 31:0 +#define NVC597_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC597_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC597_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC597_SET_DEPTH_FUNC 0x130c +#define NVC597_SET_DEPTH_FUNC_V 31:0 +#define NVC597_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC597_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC597_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC597_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC597_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC597_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC597_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC597_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC597_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC597_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC597_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC597_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC597_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC597_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC597_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC597_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC597_SET_ALPHA_REF 0x1310 +#define NVC597_SET_ALPHA_REF_V 31:0 + +#define NVC597_SET_ALPHA_FUNC 0x1314 +#define NVC597_SET_ALPHA_FUNC_V 31:0 +#define NVC597_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC597_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC597_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC597_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC597_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC597_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC597_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC597_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC597_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC597_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC597_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC597_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC597_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC597_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC597_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC597_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC597_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC597_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC597_SET_BLEND_CONST_RED 0x131c +#define NVC597_SET_BLEND_CONST_RED_V 31:0 + +#define NVC597_SET_BLEND_CONST_GREEN 0x1320 +#define NVC597_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC597_SET_BLEND_CONST_BLUE 0x1324 +#define NVC597_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC597_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC597_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC597_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC597_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC597_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC597_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC597_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC597_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC597_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC597_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BLEND_COLOR_OP 0x1340 +#define NVC597_SET_BLEND_COLOR_OP_V 31:0 +#define NVC597_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC597_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC597_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC597_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC597_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC597_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC597_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC597_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC597_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC597_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_BLEND_ALPHA_OP 0x134c +#define NVC597_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC597_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC597_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC597_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC597_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC597_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC597_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC597_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC597_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC597_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC597_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC597_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC597_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC597_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC597_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC597_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BLEND(i) (0x1360+(i)*4) +#define NVC597_SET_BLEND_ENABLE 0:0 +#define NVC597_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_STENCIL_TEST 0x1380 +#define NVC597_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC597_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_STENCIL_OP_FAIL 0x1384 +#define NVC597_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC597_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC597_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC597_SET_STENCIL_OP_ZPASS 0x138c +#define NVC597_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC597_SET_STENCIL_FUNC 0x1390 +#define NVC597_SET_STENCIL_FUNC_V 31:0 +#define NVC597_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC597_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC597_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC597_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC597_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC597_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC597_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC597_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC597_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC597_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC597_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC597_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC597_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC597_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC597_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC597_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC597_SET_STENCIL_FUNC_REF 0x1394 +#define NVC597_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC597_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC597_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC597_SET_STENCIL_MASK 0x139c +#define NVC597_SET_STENCIL_MASK_V 7:0 + +#define NVC597_SET_DRAW_AUTO_START 0x13a4 +#define NVC597_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC597_SET_PS_SATURATE 0x13a8 +#define NVC597_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC597_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC597_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC597_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC597_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC597_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC597_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC597_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC597_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC597_SET_WINDOW_ORIGIN 0x13ac +#define NVC597_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC597_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC597_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC597_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC597_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC597_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC597_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC597_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC597_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC597_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC597_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC597_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC597_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC597_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC597_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC597_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC597_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC597_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC597_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC597_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC597_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC597_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC597_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC597_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC597_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC597_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC597_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC597_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC597_STORE_ZCULL 0x1464 +#define NVC597_STORE_ZCULL_V 0:0 + +#define NVC597_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC597_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC597_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC597_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC597_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC597_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC597_LOAD_ZCULL 0x1500 +#define NVC597_LOAD_ZCULL_V 0:0 + +#define NVC597_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC597_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC597_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC597_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC597_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC597_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC597_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC597_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC597_SET_USER_CLIP_ENABLE 0x1510 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC597_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC597_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC597_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_POINT_SIZE 0x1518 +#define NVC597_SET_POINT_SIZE_V 31:0 + +#define NVC597_SET_ZCULL_STATS 0x151c +#define NVC597_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC597_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_POINT_SPRITE 0x1520 +#define NVC597_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC597_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC597_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC597_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC597_CLEAR_REPORT_VALUE 0x1530 +#define NVC597_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC597_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC597_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC597_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC597_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC597_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC597_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVC597_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC597_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC597_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_ZT_SELECT 0x1538 +#define NVC597_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC597_SET_RENDER_ENABLE_A 0x1550 +#define NVC597_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_RENDER_ENABLE_B 0x1554 +#define NVC597_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_RENDER_ENABLE_C 0x1558 +#define NVC597_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC597_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC597_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC597_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC597_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC597_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC597_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC597_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC597_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC597_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC597_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC597_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC597_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC597_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC597_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC597_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC597_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_TEX_HEADER_POOL_C 0x157c +#define NVC597_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC597_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC597_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC597_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC597_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC597_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC597_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC597_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC597_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC597_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC597_SET_SRGB_WRITE 0x15b8 +#define NVC597_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC597_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_DEPTH_BIAS 0x15bc +#define NVC597_SET_DEPTH_BIAS_V 31:0 + +#define NVC597_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC597_SET_RT_LAYER 0x15cc +#define NVC597_SET_RT_LAYER_V 15:0 +#define NVC597_SET_RT_LAYER_CONTROL 16:16 +#define NVC597_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC597_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC597_SET_ANTI_ALIAS 0x15d0 +#define NVC597_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC597_SET_EDGE_FLAG 0x15e4 +#define NVC597_SET_EDGE_FLAG_V 0:0 +#define NVC597_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC597_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC597_DRAW_INLINE_INDEX 0x15e8 +#define NVC597_DRAW_INLINE_INDEX_V 31:0 + +#define NVC597_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC597_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC597_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC597_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC597_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC597_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC597_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC597_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC597_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC597_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC597_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC597_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC597_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC597_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC597_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC597_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC597_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC597_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC597_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC597_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC597_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC597_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC597_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC597_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC597_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC597_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC597_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC597_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC597_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC597_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC597_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC597_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC597_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC597_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC597_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC597_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC597_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC597_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC597_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC597_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC597_END 0x1614 +#define NVC597_END_V 0:0 + +#define NVC597_BEGIN 0x1618 +#define NVC597_BEGIN_OP 15:0 +#define NVC597_BEGIN_OP_POINTS 0x00000000 +#define NVC597_BEGIN_OP_LINES 0x00000001 +#define NVC597_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC597_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC597_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC597_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC597_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC597_BEGIN_OP_QUADS 0x00000007 +#define NVC597_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC597_BEGIN_OP_POLYGON 0x00000009 +#define NVC597_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC597_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC597_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_BEGIN_OP_PATCH 0x0000000E +#define NVC597_BEGIN_PRIMITIVE_ID 24:24 +#define NVC597_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC597_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC597_BEGIN_INSTANCE_ID 27:26 +#define NVC597_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC597_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC597_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC597_BEGIN_SPLIT_MODE 30:29 +#define NVC597_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC597_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC597_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC597_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC597_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVC597_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC597_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_VERTEX_ID_COPY 0x161c +#define NVC597_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC597_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC597_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC597_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC597_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC597_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC597_LOAD_PRIMITIVE_ID 0x1624 +#define NVC597_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC597_SET_SHADER_BASED_CULL 0x162c +#define NVC597_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC597_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC597_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC597_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_CLASS_VERSION 0x1638 +#define NVC597_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC597_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC597_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC597_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC597_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC597_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC597_SET_DA_OUTPUT 0x164c +#define NVC597_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC597_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC597_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC597_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC597_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_POINT_CENTER_MODE 0x165c +#define NVC597_SET_POINT_CENTER_MODE_V 31:0 +#define NVC597_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC597_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC597_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC597_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC597_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC597_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC597_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC597_SET_LINE_STIPPLE 0x166c +#define NVC597_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC597_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC597_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC597_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC597_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC597_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC597_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC597_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC597_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC597_SET_PROVOKING_VERTEX 0x1684 +#define NVC597_SET_PROVOKING_VERTEX_V 0:0 +#define NVC597_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC597_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC597_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC597_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC597_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_POLYGON_STIPPLE 0x168c +#define NVC597_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC597_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_SHADER_CONTROL 0x1690 +#define NVC597_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC597_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC597_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC597_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC597_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC597_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC597_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC597_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC597_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC597_CHECK_CLASS_VERSION 0x16a0 +#define NVC597_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC597_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC597_SET_SPH_VERSION 0x16a4 +#define NVC597_SET_SPH_VERSION_CURRENT 15:0 +#define NVC597_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC597_CHECK_SPH_VERSION 0x16a8 +#define NVC597_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC597_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC597_SET_SCG_GRAPHICS_PRIORITY 0x16bc +#define NVC597_SET_SCG_GRAPHICS_PRIORITY_PRIORITY 5:0 + +#define NVC597_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS(i) (0x16c0+(i)*4) +#define NVC597_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC597_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC597_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC597_SET_AAM_VERSION 0x1790 +#define NVC597_SET_AAM_VERSION_CURRENT 15:0 +#define NVC597_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC597_CHECK_AAM_VERSION 0x1794 +#define NVC597_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC597_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC597_SET_ZT_LAYER 0x179c +#define NVC597_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC597_SET_INDEX_BUFFER_A 0x17c8 +#define NVC597_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC597_SET_INDEX_BUFFER_B 0x17cc +#define NVC597_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC597_SET_INDEX_BUFFER_E 0x17d8 +#define NVC597_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC597_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC597_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC597_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC597_SET_INDEX_BUFFER_F 0x17dc +#define NVC597_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC597_DRAW_INDEX_BUFFER 0x17e0 +#define NVC597_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC597_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC597_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC597_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC597_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC597_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC597_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC597_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC597_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC597_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC597_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC597_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC597_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC597_OGL_SET_CULL 0x1918 +#define NVC597_OGL_SET_CULL_ENABLE 0:0 +#define NVC597_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC597_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC597_OGL_SET_FRONT_FACE 0x191c +#define NVC597_OGL_SET_FRONT_FACE_V 31:0 +#define NVC597_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC597_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC597_OGL_SET_CULL_FACE 0x1920 +#define NVC597_OGL_SET_CULL_FACE_V 31:0 +#define NVC597_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC597_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC597_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC597_SET_VIEWPORT_PIXEL 0x1924 +#define NVC597_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC597_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC597_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC597_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC597_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC597_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC597_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE 17:16 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_USE_FIELD_MIN_Z_ZERO_MAX_Z_ONE 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MIN_Z_MAX_Z 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_ZERO_ONE 0x00000002 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MINUS_INF_PLUS_INF 0x00000003 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC597_SET_USER_CLIP_OP 0x1940 +#define NVC597_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC597_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC597_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC597_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC597_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC597_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC597_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC597_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC597_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC597_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC597_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC597_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC597_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC597_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC597_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC597_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC597_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC597_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC597_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC597_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC597_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC597_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC597_INVALIDATE_ZCULL 0x1958 +#define NVC597_INVALIDATE_ZCULL_V 31:0 +#define NVC597_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC597_SET_ZCULL 0x1968 +#define NVC597_SET_ZCULL_Z_ENABLE 0:0 +#define NVC597_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC597_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_ZCULL_BOUNDS 0x196c +#define NVC597_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC597_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC597_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC597_ZCULL_SYNC 0x1978 +#define NVC597_ZCULL_SYNC_V 31:0 + +#define NVC597_SET_CLIP_ID_TEST 0x197c +#define NVC597_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC597_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC597_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC597_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC597_SET_CLIP_ID 0x1984 +#define NVC597_SET_CLIP_ID_V 31:0 + +#define NVC597_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC597_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC597_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC597_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC597_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC597_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC597_SET_LOGIC_OP 0x19c4 +#define NVC597_SET_LOGIC_OP_ENABLE 0:0 +#define NVC597_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC597_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC597_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC597_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC597_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC597_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC597_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC597_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC597_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC597_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC597_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC597_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC597_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC597_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC597_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC597_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC597_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC597_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC597_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC597_SET_Z_COMPRESSION 0x19cc +#define NVC597_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC597_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC597_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC597_CLEAR_SURFACE 0x19d0 +#define NVC597_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC597_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC597_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC597_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC597_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC597_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC597_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC597_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC597_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC597_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC597_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC597_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC597_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC597_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC597_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC597_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC597_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC597_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC597_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC597_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC597_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC597_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC597_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC597_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC597_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC597_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC597_PIPE_NOP 0x1a2c +#define NVC597_PIPE_NOP_V 31:0 + +#define NVC597_SET_SPARE00 0x1a30 +#define NVC597_SET_SPARE00_V 31:0 + +#define NVC597_SET_SPARE01 0x1a34 +#define NVC597_SET_SPARE01_V 31:0 + +#define NVC597_SET_SPARE02 0x1a38 +#define NVC597_SET_SPARE02_V 31:0 + +#define NVC597_SET_SPARE03 0x1a3c +#define NVC597_SET_SPARE03_V 31:0 + +#define NVC597_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC597_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC597_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC597_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC597_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC597_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC597_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC597_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC597_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC597_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC597_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC597_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC597_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC597_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC597_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC597_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC597_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC597_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC597_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC597_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC597_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC597_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC597_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC597_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC597_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC597_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC597_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC597_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC597_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC597_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC597_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC597_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC597_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC597_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC597_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC597_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC597_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC597_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC597_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC597_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC597_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC597_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC597_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC597_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC597_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC597_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC597_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC597_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC597_SET_PIPELINE_REGISTER_COUNT_V 8:0 + +#define NVC597_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC597_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC597_SET_PIPELINE_PROGRAM_ADDRESS_A(j) (0x2014+(j)*64) +#define NVC597_SET_PIPELINE_PROGRAM_ADDRESS_A_UPPER 7:0 + +#define NVC597_SET_PIPELINE_PROGRAM_ADDRESS_B(j) (0x2018+(j)*64) +#define NVC597_SET_PIPELINE_PROGRAM_ADDRESS_B_LOWER 31:0 + +#define NVC597_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVC597_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVC597_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC597_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC597_SET_FALCON00 0x2300 +#define NVC597_SET_FALCON00_V 31:0 + +#define NVC597_SET_FALCON01 0x2304 +#define NVC597_SET_FALCON01_V 31:0 + +#define NVC597_SET_FALCON02 0x2308 +#define NVC597_SET_FALCON02_V 31:0 + +#define NVC597_SET_FALCON03 0x230c +#define NVC597_SET_FALCON03_V 31:0 + +#define NVC597_SET_FALCON04 0x2310 +#define NVC597_SET_FALCON04_V 31:0 + +#define NVC597_SET_FALCON05 0x2314 +#define NVC597_SET_FALCON05_V 31:0 + +#define NVC597_SET_FALCON06 0x2318 +#define NVC597_SET_FALCON06_V 31:0 + +#define NVC597_SET_FALCON07 0x231c +#define NVC597_SET_FALCON07_V 31:0 + +#define NVC597_SET_FALCON08 0x2320 +#define NVC597_SET_FALCON08_V 31:0 + +#define NVC597_SET_FALCON09 0x2324 +#define NVC597_SET_FALCON09_V 31:0 + +#define NVC597_SET_FALCON10 0x2328 +#define NVC597_SET_FALCON10_V 31:0 + +#define NVC597_SET_FALCON11 0x232c +#define NVC597_SET_FALCON11_V 31:0 + +#define NVC597_SET_FALCON12 0x2330 +#define NVC597_SET_FALCON12_V 31:0 + +#define NVC597_SET_FALCON13 0x2334 +#define NVC597_SET_FALCON13_V 31:0 + +#define NVC597_SET_FALCON14 0x2338 +#define NVC597_SET_FALCON14_V 31:0 + +#define NVC597_SET_FALCON15 0x233c +#define NVC597_SET_FALCON15_V 31:0 + +#define NVC597_SET_FALCON16 0x2340 +#define NVC597_SET_FALCON16_V 31:0 + +#define NVC597_SET_FALCON17 0x2344 +#define NVC597_SET_FALCON17_V 31:0 + +#define NVC597_SET_FALCON18 0x2348 +#define NVC597_SET_FALCON18_V 31:0 + +#define NVC597_SET_FALCON19 0x234c +#define NVC597_SET_FALCON19_V 31:0 + +#define NVC597_SET_FALCON20 0x2350 +#define NVC597_SET_FALCON20_V 31:0 + +#define NVC597_SET_FALCON21 0x2354 +#define NVC597_SET_FALCON21_V 31:0 + +#define NVC597_SET_FALCON22 0x2358 +#define NVC597_SET_FALCON22_V 31:0 + +#define NVC597_SET_FALCON23 0x235c +#define NVC597_SET_FALCON23_V 31:0 + +#define NVC597_SET_FALCON24 0x2360 +#define NVC597_SET_FALCON24_V 31:0 + +#define NVC597_SET_FALCON25 0x2364 +#define NVC597_SET_FALCON25_V 31:0 + +#define NVC597_SET_FALCON26 0x2368 +#define NVC597_SET_FALCON26_V 31:0 + +#define NVC597_SET_FALCON27 0x236c +#define NVC597_SET_FALCON27_V 31:0 + +#define NVC597_SET_FALCON28 0x2370 +#define NVC597_SET_FALCON28_V 31:0 + +#define NVC597_SET_FALCON29 0x2374 +#define NVC597_SET_FALCON29_V 31:0 + +#define NVC597_SET_FALCON30 0x2378 +#define NVC597_SET_FALCON30_V 31:0 + +#define NVC597_SET_FALCON31 0x237c +#define NVC597_SET_FALCON31_V 31:0 + +#define NVC597_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC597_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC597_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC597_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC597_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC597_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC597_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC597_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC597_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC597_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC597_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC597_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC597_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC597_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC597_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC597_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC597_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC597_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC597_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC597_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC597_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC597_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC597_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC597_SET_TRAP_HANDLER_A 0x25f8 +#define NVC597_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC597_SET_TRAP_HANDLER_B 0x25fc +#define NVC597_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC597_SET_COLOR_CLAMP 0x2600 +#define NVC597_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC597_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC597_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BINDLESS_TEXTURE 0x2608 +#define NVC597_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVC597_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC597_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC597_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC597_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC597_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC597_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC597_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC597_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC597_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC597_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC597_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC597_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC597_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC597_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC597_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC597_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC597_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC597_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC597_CALL_MME_MACRO_V 31:0 + +#define NVC597_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC597_CALL_MME_DATA_V 31:0 + +#endif /* _cl_turing_a_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc597tex.h b/userspace/sdks/nv570/inc/class/clc597tex.h new file mode 100644 index 0000000..4767ff9 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc597tex.h @@ -0,0 +1,1454 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2010 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLC597TEX_H__ +#define __CLC597TEX_H__ + +/* +** Texture Header State Blocklinear + */ + +#define NVC597_TEXHEAD_BL_COMPONENTS MW(6:0) +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_R32 0x0000000f +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_R16 0x0000001b +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_R8 0x0000001d +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_R1 0x0000001f +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_EAC 0x00000019 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_Z16 0x0000003a +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVC597_TEXHEAD_BL_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVC597_TEXHEAD_BL_R_DATA_TYPE MW(9:7) +#define NVC597_TEXHEAD_BL_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC597_TEXHEAD_BL_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC597_TEXHEAD_BL_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC597_TEXHEAD_BL_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC597_TEXHEAD_BL_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC597_TEXHEAD_BL_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC597_TEXHEAD_BL_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_TEXHEAD_BL_G_DATA_TYPE MW(12:10) +#define NVC597_TEXHEAD_BL_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC597_TEXHEAD_BL_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC597_TEXHEAD_BL_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC597_TEXHEAD_BL_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC597_TEXHEAD_BL_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC597_TEXHEAD_BL_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC597_TEXHEAD_BL_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_TEXHEAD_BL_B_DATA_TYPE MW(15:13) +#define NVC597_TEXHEAD_BL_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC597_TEXHEAD_BL_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC597_TEXHEAD_BL_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC597_TEXHEAD_BL_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC597_TEXHEAD_BL_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC597_TEXHEAD_BL_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC597_TEXHEAD_BL_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_TEXHEAD_BL_A_DATA_TYPE MW(18:16) +#define NVC597_TEXHEAD_BL_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC597_TEXHEAD_BL_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC597_TEXHEAD_BL_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC597_TEXHEAD_BL_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC597_TEXHEAD_BL_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC597_TEXHEAD_BL_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC597_TEXHEAD_BL_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_TEXHEAD_BL_X_SOURCE MW(21:19) +#define NVC597_TEXHEAD_BL_X_SOURCE_IN_ZERO 0x00000000 +#define NVC597_TEXHEAD_BL_X_SOURCE_IN_R 0x00000002 +#define NVC597_TEXHEAD_BL_X_SOURCE_IN_G 0x00000003 +#define NVC597_TEXHEAD_BL_X_SOURCE_IN_B 0x00000004 +#define NVC597_TEXHEAD_BL_X_SOURCE_IN_A 0x00000005 +#define NVC597_TEXHEAD_BL_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVC597_TEXHEAD_BL_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC597_TEXHEAD_BL_Y_SOURCE MW(24:22) +#define NVC597_TEXHEAD_BL_Y_SOURCE_IN_ZERO 0x00000000 +#define NVC597_TEXHEAD_BL_Y_SOURCE_IN_R 0x00000002 +#define NVC597_TEXHEAD_BL_Y_SOURCE_IN_G 0x00000003 +#define NVC597_TEXHEAD_BL_Y_SOURCE_IN_B 0x00000004 +#define NVC597_TEXHEAD_BL_Y_SOURCE_IN_A 0x00000005 +#define NVC597_TEXHEAD_BL_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVC597_TEXHEAD_BL_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC597_TEXHEAD_BL_Z_SOURCE MW(27:25) +#define NVC597_TEXHEAD_BL_Z_SOURCE_IN_ZERO 0x00000000 +#define NVC597_TEXHEAD_BL_Z_SOURCE_IN_R 0x00000002 +#define NVC597_TEXHEAD_BL_Z_SOURCE_IN_G 0x00000003 +#define NVC597_TEXHEAD_BL_Z_SOURCE_IN_B 0x00000004 +#define NVC597_TEXHEAD_BL_Z_SOURCE_IN_A 0x00000005 +#define NVC597_TEXHEAD_BL_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVC597_TEXHEAD_BL_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC597_TEXHEAD_BL_W_SOURCE MW(30:28) +#define NVC597_TEXHEAD_BL_W_SOURCE_IN_ZERO 0x00000000 +#define NVC597_TEXHEAD_BL_W_SOURCE_IN_R 0x00000002 +#define NVC597_TEXHEAD_BL_W_SOURCE_IN_G 0x00000003 +#define NVC597_TEXHEAD_BL_W_SOURCE_IN_B 0x00000004 +#define NVC597_TEXHEAD_BL_W_SOURCE_IN_A 0x00000005 +#define NVC597_TEXHEAD_BL_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVC597_TEXHEAD_BL_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC597_TEXHEAD_BL_PACK_COMPONENTS MW(31:31) +#define NVC597_TEXHEAD_BL_RESERVED1Y MW(36:32) +#define NVC597_TEXHEAD_BL_GOB_DEPTH_OFFSET MW(38:37) +#define NVC597_TEXHEAD_BL_RESERVED1X MW(40:39) +#define NVC597_TEXHEAD_BL_ADDRESS_BITS31TO9 MW(63:41) +#define NVC597_TEXHEAD_BL_ADDRESS_BITS48TO32 MW(80:64) +#define NVC597_TEXHEAD_BL_RESERVED_ADDRESS MW(84:81) +#define NVC597_TEXHEAD_BL_HEADER_VERSION MW(87:85) +#define NVC597_TEXHEAD_BL_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVC597_TEXHEAD_BL_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVC597_TEXHEAD_BL_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVC597_TEXHEAD_BL_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVC597_TEXHEAD_BL_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVC597_TEXHEAD_BL_RESERVED_HEADER_VERSION MW(88:88) +#define NVC597_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVC597_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVC597_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVC597_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVC597_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVC597_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVC597_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVC597_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVC597_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVC597_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVC597_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVC597_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVC597_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVC597_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVC597_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVC597_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVC597_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVC597_TEXHEAD_BL_RESERVED2A MW(95:93) +#define NVC597_TEXHEAD_BL_GOBS_PER_BLOCK_WIDTH MW(98:96) +#define NVC597_TEXHEAD_BL_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC597_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT MW(101:99) +#define NVC597_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC597_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC597_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC597_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC597_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC597_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC597_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH MW(104:102) +#define NVC597_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC597_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC597_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC597_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC597_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC597_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC597_TEXHEAD_BL_RESERVED3Y MW(105:105) +#define NVC597_TEXHEAD_BL_TILE_WIDTH_IN_GOBS MW(108:106) +#define NVC597_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVC597_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVC597_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVC597_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVC597_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVC597_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVC597_TEXHEAD_BL_GOB3D MW(109:109) +#define NVC597_TEXHEAD_BL_RESERVED3Z MW(111:110) +#define NVC597_TEXHEAD_BL_LOD_ANISO_QUALITY2 MW(112:112) +#define NVC597_TEXHEAD_BL_LOD_ANISO_QUALITY MW(113:113) +#define NVC597_TEXHEAD_BL_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC597_TEXHEAD_BL_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC597_TEXHEAD_BL_LOD_ISO_QUALITY MW(114:114) +#define NVC597_TEXHEAD_BL_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC597_TEXHEAD_BL_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC597_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVC597_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC597_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC597_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC597_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC597_TEXHEAD_BL_ANISO_SPREAD_SCALE MW(121:117) +#define NVC597_TEXHEAD_BL_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVC597_TEXHEAD_BL_DEPTH_TEXTURE MW(123:123) +#define NVC597_TEXHEAD_BL_MAX_MIP_LEVEL MW(127:124) +#define NVC597_TEXHEAD_BL_WIDTH_MINUS_ONE MW(144:128) +#define NVC597_TEXHEAD_BL_DEPTH_MINUS_ONE_BIT14 MW(145:145) +#define NVC597_TEXHEAD_BL_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVC597_TEXHEAD_BL_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVC597_TEXHEAD_BL_S_R_G_B_CONVERSION MW(150:150) +#define NVC597_TEXHEAD_BL_TEXTURE_TYPE MW(154:151) +#define NVC597_TEXHEAD_BL_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVC597_TEXHEAD_BL_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVC597_TEXHEAD_BL_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVC597_TEXHEAD_BL_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVC597_TEXHEAD_BL_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVC597_TEXHEAD_BL_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVC597_TEXHEAD_BL_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVC597_TEXHEAD_BL_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVC597_TEXHEAD_BL_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVC597_TEXHEAD_BL_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVC597_TEXHEAD_BL_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVC597_TEXHEAD_BL_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVC597_TEXHEAD_BL_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVC597_TEXHEAD_BL_SECTOR_PROMOTION MW(156:155) +#define NVC597_TEXHEAD_BL_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVC597_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVC597_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVC597_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVC597_TEXHEAD_BL_BORDER_SIZE MW(159:157) +#define NVC597_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVC597_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVC597_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVC597_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVC597_TEXHEAD_BL_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVC597_TEXHEAD_BL_HEIGHT_MINUS_ONE MW(175:160) +#define NVC597_TEXHEAD_BL_DEPTH_MINUS_ONE MW(189:176) +#define NVC597_TEXHEAD_BL_RESERVED5A MW(190:190) +#define NVC597_TEXHEAD_BL_NORMALIZED_COORDS MW(191:191) +#define NVC597_TEXHEAD_BL_RESERVED6Y MW(192:192) +#define NVC597_TEXHEAD_BL_TRILIN_OPT MW(197:193) +#define NVC597_TEXHEAD_BL_MIP_LOD_BIAS MW(210:198) +#define NVC597_TEXHEAD_BL_ANISO_BIAS MW(214:211) +#define NVC597_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVC597_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC597_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC597_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC597_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC597_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVC597_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC597_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC597_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC597_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC597_TEXHEAD_BL_MAX_ANISOTROPY MW(221:219) +#define NVC597_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVC597_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVC597_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVC597_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVC597_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVC597_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVC597_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVC597_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVC597_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVC597_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC597_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC597_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC597_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC597_TEXHEAD_BL_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVC597_TEXHEAD_BL_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVC597_TEXHEAD_BL_MULTI_SAMPLE_COUNT MW(235:232) +#define NVC597_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVC597_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVC597_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVC597_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVC597_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVC597_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVC597_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVC597_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVC597_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVC597_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVC597_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVC597_TEXHEAD_BL_MIN_LOD_CLAMP MW(247:236) +#define NVC597_TEXHEAD_BL_RESERVED7Y MW(255:248) + + +/* +** Texture Header State Blocklinear Color Key + */ + +#define NVC597_TEXHEAD_BLCK_COMPONENTS MW(6:0) +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVC597_TEXHEAD_BLCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVC597_TEXHEAD_BLCK_R_DATA_TYPE MW(9:7) +#define NVC597_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC597_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC597_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC597_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC597_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC597_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC597_TEXHEAD_BLCK_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_TEXHEAD_BLCK_G_DATA_TYPE MW(12:10) +#define NVC597_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC597_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC597_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC597_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC597_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC597_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC597_TEXHEAD_BLCK_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_TEXHEAD_BLCK_B_DATA_TYPE MW(15:13) +#define NVC597_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC597_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC597_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC597_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC597_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC597_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC597_TEXHEAD_BLCK_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_TEXHEAD_BLCK_A_DATA_TYPE MW(18:16) +#define NVC597_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC597_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC597_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC597_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC597_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC597_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC597_TEXHEAD_BLCK_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_TEXHEAD_BLCK_X_SOURCE MW(21:19) +#define NVC597_TEXHEAD_BLCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVC597_TEXHEAD_BLCK_X_SOURCE_IN_R 0x00000002 +#define NVC597_TEXHEAD_BLCK_X_SOURCE_IN_G 0x00000003 +#define NVC597_TEXHEAD_BLCK_X_SOURCE_IN_B 0x00000004 +#define NVC597_TEXHEAD_BLCK_X_SOURCE_IN_A 0x00000005 +#define NVC597_TEXHEAD_BLCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVC597_TEXHEAD_BLCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC597_TEXHEAD_BLCK_Y_SOURCE MW(24:22) +#define NVC597_TEXHEAD_BLCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVC597_TEXHEAD_BLCK_Y_SOURCE_IN_R 0x00000002 +#define NVC597_TEXHEAD_BLCK_Y_SOURCE_IN_G 0x00000003 +#define NVC597_TEXHEAD_BLCK_Y_SOURCE_IN_B 0x00000004 +#define NVC597_TEXHEAD_BLCK_Y_SOURCE_IN_A 0x00000005 +#define NVC597_TEXHEAD_BLCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVC597_TEXHEAD_BLCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC597_TEXHEAD_BLCK_Z_SOURCE MW(27:25) +#define NVC597_TEXHEAD_BLCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVC597_TEXHEAD_BLCK_Z_SOURCE_IN_R 0x00000002 +#define NVC597_TEXHEAD_BLCK_Z_SOURCE_IN_G 0x00000003 +#define NVC597_TEXHEAD_BLCK_Z_SOURCE_IN_B 0x00000004 +#define NVC597_TEXHEAD_BLCK_Z_SOURCE_IN_A 0x00000005 +#define NVC597_TEXHEAD_BLCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVC597_TEXHEAD_BLCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC597_TEXHEAD_BLCK_W_SOURCE MW(30:28) +#define NVC597_TEXHEAD_BLCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVC597_TEXHEAD_BLCK_W_SOURCE_IN_R 0x00000002 +#define NVC597_TEXHEAD_BLCK_W_SOURCE_IN_G 0x00000003 +#define NVC597_TEXHEAD_BLCK_W_SOURCE_IN_B 0x00000004 +#define NVC597_TEXHEAD_BLCK_W_SOURCE_IN_A 0x00000005 +#define NVC597_TEXHEAD_BLCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVC597_TEXHEAD_BLCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC597_TEXHEAD_BLCK_PACK_COMPONENTS MW(31:31) +#define NVC597_TEXHEAD_BLCK_RESERVED1Y MW(36:32) +#define NVC597_TEXHEAD_BLCK_GOB_DEPTH_OFFSET MW(38:37) +#define NVC597_TEXHEAD_BLCK_RESERVED1X MW(40:39) +#define NVC597_TEXHEAD_BLCK_ADDRESS_BITS31TO9 MW(63:41) +#define NVC597_TEXHEAD_BLCK_ADDRESS_BITS48TO32 MW(80:64) +#define NVC597_TEXHEAD_BLCK_RESERVED_ADDRESS MW(84:81) +#define NVC597_TEXHEAD_BLCK_HEADER_VERSION MW(87:85) +#define NVC597_TEXHEAD_BLCK_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVC597_TEXHEAD_BLCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVC597_TEXHEAD_BLCK_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVC597_TEXHEAD_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVC597_TEXHEAD_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVC597_TEXHEAD_BLCK_RESERVED_HEADER_VERSION MW(88:88) +#define NVC597_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVC597_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVC597_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVC597_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVC597_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVC597_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVC597_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVC597_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVC597_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVC597_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVC597_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVC597_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVC597_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVC597_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVC597_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVC597_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVC597_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVC597_TEXHEAD_BLCK_RESERVED2A MW(95:93) +#define NVC597_TEXHEAD_BLCK_GOBS_PER_BLOCK_WIDTH MW(98:96) +#define NVC597_TEXHEAD_BLCK_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC597_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT MW(101:99) +#define NVC597_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC597_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC597_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC597_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC597_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC597_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC597_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH MW(104:102) +#define NVC597_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC597_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC597_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC597_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC597_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC597_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC597_TEXHEAD_BLCK_RESERVED3Y MW(105:105) +#define NVC597_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS MW(108:106) +#define NVC597_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVC597_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVC597_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVC597_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVC597_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVC597_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVC597_TEXHEAD_BLCK_GOB3D MW(109:109) +#define NVC597_TEXHEAD_BLCK_RESERVED3Z MW(111:110) +#define NVC597_TEXHEAD_BLCK_LOD_ANISO_QUALITY2 MW(112:112) +#define NVC597_TEXHEAD_BLCK_LOD_ANISO_QUALITY MW(113:113) +#define NVC597_TEXHEAD_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC597_TEXHEAD_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC597_TEXHEAD_BLCK_LOD_ISO_QUALITY MW(114:114) +#define NVC597_TEXHEAD_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC597_TEXHEAD_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC597_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVC597_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC597_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC597_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC597_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC597_TEXHEAD_BLCK_ANISO_SPREAD_SCALE MW(121:117) +#define NVC597_TEXHEAD_BLCK_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVC597_TEXHEAD_BLCK_DEPTH_TEXTURE MW(123:123) +#define NVC597_TEXHEAD_BLCK_MAX_MIP_LEVEL MW(127:124) +#define NVC597_TEXHEAD_BLCK_WIDTH_MINUS_ONE MW(144:128) +#define NVC597_TEXHEAD_BLCK_DEPTH_MINUS_ONE_BIT14 MW(145:145) +#define NVC597_TEXHEAD_BLCK_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVC597_TEXHEAD_BLCK_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVC597_TEXHEAD_BLCK_S_R_G_B_CONVERSION MW(150:150) +#define NVC597_TEXHEAD_BLCK_TEXTURE_TYPE MW(154:151) +#define NVC597_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVC597_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVC597_TEXHEAD_BLCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVC597_TEXHEAD_BLCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVC597_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVC597_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVC597_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVC597_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVC597_TEXHEAD_BLCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVC597_TEXHEAD_BLCK_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVC597_TEXHEAD_BLCK_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVC597_TEXHEAD_BLCK_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVC597_TEXHEAD_BLCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVC597_TEXHEAD_BLCK_SECTOR_PROMOTION MW(156:155) +#define NVC597_TEXHEAD_BLCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVC597_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVC597_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVC597_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVC597_TEXHEAD_BLCK_BORDER_SIZE MW(159:157) +#define NVC597_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVC597_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVC597_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVC597_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVC597_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVC597_TEXHEAD_BLCK_HEIGHT_MINUS_ONE MW(175:160) +#define NVC597_TEXHEAD_BLCK_DEPTH_MINUS_ONE MW(189:176) +#define NVC597_TEXHEAD_BLCK_RESERVED5A MW(190:190) +#define NVC597_TEXHEAD_BLCK_NORMALIZED_COORDS MW(191:191) +#define NVC597_TEXHEAD_BLCK_COLOR_KEY_OP MW(192:192) +#define NVC597_TEXHEAD_BLCK_TRILIN_OPT MW(197:193) +#define NVC597_TEXHEAD_BLCK_MIP_LOD_BIAS MW(210:198) +#define NVC597_TEXHEAD_BLCK_ANISO_BIAS MW(214:211) +#define NVC597_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVC597_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC597_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC597_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC597_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC597_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVC597_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC597_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC597_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC597_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC597_TEXHEAD_BLCK_MAX_ANISOTROPY MW(221:219) +#define NVC597_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVC597_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVC597_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVC597_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVC597_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVC597_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVC597_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVC597_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVC597_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVC597_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC597_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC597_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC597_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC597_TEXHEAD_BLCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Header State One-D Buffer + */ + +#define NVC597_TEXHEAD_1D_COMPONENTS MW(6:0) +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_R32 0x0000000f +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_R16 0x0000001b +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_R8 0x0000001d +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_R1 0x0000001f +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_EAC 0x00000019 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_Z16 0x0000003a +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVC597_TEXHEAD_1D_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVC597_TEXHEAD_1D_R_DATA_TYPE MW(9:7) +#define NVC597_TEXHEAD_1D_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC597_TEXHEAD_1D_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC597_TEXHEAD_1D_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC597_TEXHEAD_1D_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC597_TEXHEAD_1D_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC597_TEXHEAD_1D_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC597_TEXHEAD_1D_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_TEXHEAD_1D_G_DATA_TYPE MW(12:10) +#define NVC597_TEXHEAD_1D_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC597_TEXHEAD_1D_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC597_TEXHEAD_1D_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC597_TEXHEAD_1D_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC597_TEXHEAD_1D_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC597_TEXHEAD_1D_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC597_TEXHEAD_1D_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_TEXHEAD_1D_B_DATA_TYPE MW(15:13) +#define NVC597_TEXHEAD_1D_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC597_TEXHEAD_1D_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC597_TEXHEAD_1D_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC597_TEXHEAD_1D_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC597_TEXHEAD_1D_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC597_TEXHEAD_1D_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC597_TEXHEAD_1D_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_TEXHEAD_1D_A_DATA_TYPE MW(18:16) +#define NVC597_TEXHEAD_1D_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC597_TEXHEAD_1D_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC597_TEXHEAD_1D_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC597_TEXHEAD_1D_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC597_TEXHEAD_1D_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC597_TEXHEAD_1D_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC597_TEXHEAD_1D_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_TEXHEAD_1D_X_SOURCE MW(21:19) +#define NVC597_TEXHEAD_1D_X_SOURCE_IN_ZERO 0x00000000 +#define NVC597_TEXHEAD_1D_X_SOURCE_IN_R 0x00000002 +#define NVC597_TEXHEAD_1D_X_SOURCE_IN_G 0x00000003 +#define NVC597_TEXHEAD_1D_X_SOURCE_IN_B 0x00000004 +#define NVC597_TEXHEAD_1D_X_SOURCE_IN_A 0x00000005 +#define NVC597_TEXHEAD_1D_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVC597_TEXHEAD_1D_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC597_TEXHEAD_1D_Y_SOURCE MW(24:22) +#define NVC597_TEXHEAD_1D_Y_SOURCE_IN_ZERO 0x00000000 +#define NVC597_TEXHEAD_1D_Y_SOURCE_IN_R 0x00000002 +#define NVC597_TEXHEAD_1D_Y_SOURCE_IN_G 0x00000003 +#define NVC597_TEXHEAD_1D_Y_SOURCE_IN_B 0x00000004 +#define NVC597_TEXHEAD_1D_Y_SOURCE_IN_A 0x00000005 +#define NVC597_TEXHEAD_1D_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVC597_TEXHEAD_1D_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC597_TEXHEAD_1D_Z_SOURCE MW(27:25) +#define NVC597_TEXHEAD_1D_Z_SOURCE_IN_ZERO 0x00000000 +#define NVC597_TEXHEAD_1D_Z_SOURCE_IN_R 0x00000002 +#define NVC597_TEXHEAD_1D_Z_SOURCE_IN_G 0x00000003 +#define NVC597_TEXHEAD_1D_Z_SOURCE_IN_B 0x00000004 +#define NVC597_TEXHEAD_1D_Z_SOURCE_IN_A 0x00000005 +#define NVC597_TEXHEAD_1D_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVC597_TEXHEAD_1D_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC597_TEXHEAD_1D_W_SOURCE MW(30:28) +#define NVC597_TEXHEAD_1D_W_SOURCE_IN_ZERO 0x00000000 +#define NVC597_TEXHEAD_1D_W_SOURCE_IN_R 0x00000002 +#define NVC597_TEXHEAD_1D_W_SOURCE_IN_G 0x00000003 +#define NVC597_TEXHEAD_1D_W_SOURCE_IN_B 0x00000004 +#define NVC597_TEXHEAD_1D_W_SOURCE_IN_A 0x00000005 +#define NVC597_TEXHEAD_1D_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVC597_TEXHEAD_1D_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC597_TEXHEAD_1D_PACK_COMPONENTS MW(31:31) +#define NVC597_TEXHEAD_1D_ADDRESS_BITS31TO0 MW(63:32) +#define NVC597_TEXHEAD_1D_ADDRESS_BITS48TO32 MW(80:64) +#define NVC597_TEXHEAD_1D_RESERVED_ADDRESS MW(84:81) +#define NVC597_TEXHEAD_1D_HEADER_VERSION MW(87:85) +#define NVC597_TEXHEAD_1D_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVC597_TEXHEAD_1D_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVC597_TEXHEAD_1D_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVC597_TEXHEAD_1D_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVC597_TEXHEAD_1D_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVC597_TEXHEAD_1D_RESERVED_HEADER_VERSION MW(88:88) +#define NVC597_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVC597_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVC597_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVC597_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVC597_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVC597_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVC597_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVC597_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVC597_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVC597_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVC597_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVC597_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVC597_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVC597_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVC597_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVC597_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVC597_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVC597_TEXHEAD_1D_RESERVED2A MW(95:93) +#define NVC597_TEXHEAD_1D_WIDTH_MINUS_ONE_BITS31TO16 MW(111:96) +#define NVC597_TEXHEAD_1D_RESERVED3X MW(127:112) +#define NVC597_TEXHEAD_1D_WIDTH_MINUS_ONE_BITS15TO0 MW(143:128) +#define NVC597_TEXHEAD_1D_RESERVED4X MW(149:144) +#define NVC597_TEXHEAD_1D_S_R_G_B_CONVERSION MW(150:150) +#define NVC597_TEXHEAD_1D_TEXTURE_TYPE MW(154:151) +#define NVC597_TEXHEAD_1D_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVC597_TEXHEAD_1D_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVC597_TEXHEAD_1D_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVC597_TEXHEAD_1D_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVC597_TEXHEAD_1D_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVC597_TEXHEAD_1D_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVC597_TEXHEAD_1D_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVC597_TEXHEAD_1D_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVC597_TEXHEAD_1D_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVC597_TEXHEAD_1D_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVC597_TEXHEAD_1D_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVC597_TEXHEAD_1D_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVC597_TEXHEAD_1D_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVC597_TEXHEAD_1D_SECTOR_PROMOTION MW(156:155) +#define NVC597_TEXHEAD_1D_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVC597_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVC597_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVC597_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVC597_TEXHEAD_1D_RESERVED4Y MW(159:157) +#define NVC597_TEXHEAD_1D_RESERVED5X MW(189:160) +#define NVC597_TEXHEAD_1D_RESERVED5A MW(190:190) +#define NVC597_TEXHEAD_1D_RESERVED5Y MW(191:191) +#define NVC597_TEXHEAD_1D_RESERVED6X MW(223:192) +#define NVC597_TEXHEAD_1D_RESERVED7X MW(255:224) + + +/* +** Texture Header State Pitch + */ + +#define NVC597_TEXHEAD_PITCH_COMPONENTS MW(6:0) +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_R32 0x0000000f +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_R16 0x0000001b +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_R8 0x0000001d +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_R1 0x0000001f +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_EAC 0x00000019 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_Z16 0x0000003a +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVC597_TEXHEAD_PITCH_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVC597_TEXHEAD_PITCH_R_DATA_TYPE MW(9:7) +#define NVC597_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC597_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC597_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC597_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC597_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC597_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC597_TEXHEAD_PITCH_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_TEXHEAD_PITCH_G_DATA_TYPE MW(12:10) +#define NVC597_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC597_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC597_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC597_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC597_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC597_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC597_TEXHEAD_PITCH_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_TEXHEAD_PITCH_B_DATA_TYPE MW(15:13) +#define NVC597_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC597_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC597_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC597_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC597_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC597_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC597_TEXHEAD_PITCH_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_TEXHEAD_PITCH_A_DATA_TYPE MW(18:16) +#define NVC597_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC597_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC597_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC597_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC597_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC597_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC597_TEXHEAD_PITCH_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_TEXHEAD_PITCH_X_SOURCE MW(21:19) +#define NVC597_TEXHEAD_PITCH_X_SOURCE_IN_ZERO 0x00000000 +#define NVC597_TEXHEAD_PITCH_X_SOURCE_IN_R 0x00000002 +#define NVC597_TEXHEAD_PITCH_X_SOURCE_IN_G 0x00000003 +#define NVC597_TEXHEAD_PITCH_X_SOURCE_IN_B 0x00000004 +#define NVC597_TEXHEAD_PITCH_X_SOURCE_IN_A 0x00000005 +#define NVC597_TEXHEAD_PITCH_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVC597_TEXHEAD_PITCH_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC597_TEXHEAD_PITCH_Y_SOURCE MW(24:22) +#define NVC597_TEXHEAD_PITCH_Y_SOURCE_IN_ZERO 0x00000000 +#define NVC597_TEXHEAD_PITCH_Y_SOURCE_IN_R 0x00000002 +#define NVC597_TEXHEAD_PITCH_Y_SOURCE_IN_G 0x00000003 +#define NVC597_TEXHEAD_PITCH_Y_SOURCE_IN_B 0x00000004 +#define NVC597_TEXHEAD_PITCH_Y_SOURCE_IN_A 0x00000005 +#define NVC597_TEXHEAD_PITCH_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVC597_TEXHEAD_PITCH_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC597_TEXHEAD_PITCH_Z_SOURCE MW(27:25) +#define NVC597_TEXHEAD_PITCH_Z_SOURCE_IN_ZERO 0x00000000 +#define NVC597_TEXHEAD_PITCH_Z_SOURCE_IN_R 0x00000002 +#define NVC597_TEXHEAD_PITCH_Z_SOURCE_IN_G 0x00000003 +#define NVC597_TEXHEAD_PITCH_Z_SOURCE_IN_B 0x00000004 +#define NVC597_TEXHEAD_PITCH_Z_SOURCE_IN_A 0x00000005 +#define NVC597_TEXHEAD_PITCH_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVC597_TEXHEAD_PITCH_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC597_TEXHEAD_PITCH_W_SOURCE MW(30:28) +#define NVC597_TEXHEAD_PITCH_W_SOURCE_IN_ZERO 0x00000000 +#define NVC597_TEXHEAD_PITCH_W_SOURCE_IN_R 0x00000002 +#define NVC597_TEXHEAD_PITCH_W_SOURCE_IN_G 0x00000003 +#define NVC597_TEXHEAD_PITCH_W_SOURCE_IN_B 0x00000004 +#define NVC597_TEXHEAD_PITCH_W_SOURCE_IN_A 0x00000005 +#define NVC597_TEXHEAD_PITCH_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVC597_TEXHEAD_PITCH_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC597_TEXHEAD_PITCH_PACK_COMPONENTS MW(31:31) +#define NVC597_TEXHEAD_PITCH_RESERVED1A MW(36:32) +#define NVC597_TEXHEAD_PITCH_ADDRESS_BITS31TO5 MW(63:37) +#define NVC597_TEXHEAD_PITCH_ADDRESS_BITS48TO32 MW(80:64) +#define NVC597_TEXHEAD_PITCH_RESERVED_ADDRESS MW(84:81) +#define NVC597_TEXHEAD_PITCH_HEADER_VERSION MW(87:85) +#define NVC597_TEXHEAD_PITCH_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVC597_TEXHEAD_PITCH_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVC597_TEXHEAD_PITCH_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVC597_TEXHEAD_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVC597_TEXHEAD_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVC597_TEXHEAD_PITCH_RESERVED_HEADER_VERSION MW(88:88) +#define NVC597_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVC597_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVC597_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVC597_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVC597_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVC597_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVC597_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVC597_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVC597_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVC597_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVC597_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVC597_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVC597_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVC597_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVC597_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVC597_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVC597_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVC597_TEXHEAD_PITCH_RESERVED2A MW(95:93) +#define NVC597_TEXHEAD_PITCH_PITCH_BITS20TO5 MW(111:96) +#define NVC597_TEXHEAD_PITCH_LOD_ANISO_QUALITY2 MW(112:112) +#define NVC597_TEXHEAD_PITCH_LOD_ANISO_QUALITY MW(113:113) +#define NVC597_TEXHEAD_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC597_TEXHEAD_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC597_TEXHEAD_PITCH_LOD_ISO_QUALITY MW(114:114) +#define NVC597_TEXHEAD_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC597_TEXHEAD_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC597_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVC597_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC597_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC597_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC597_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC597_TEXHEAD_PITCH_ANISO_SPREAD_SCALE MW(121:117) +#define NVC597_TEXHEAD_PITCH_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVC597_TEXHEAD_PITCH_DEPTH_TEXTURE MW(123:123) +#define NVC597_TEXHEAD_PITCH_MAX_MIP_LEVEL MW(127:124) +#define NVC597_TEXHEAD_PITCH_WIDTH_MINUS_ONE MW(144:128) +#define NVC597_TEXHEAD_PITCH_PITCH_BIT21 MW(145:145) +#define NVC597_TEXHEAD_PITCH_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVC597_TEXHEAD_PITCH_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVC597_TEXHEAD_PITCH_S_R_G_B_CONVERSION MW(150:150) +#define NVC597_TEXHEAD_PITCH_TEXTURE_TYPE MW(154:151) +#define NVC597_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVC597_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVC597_TEXHEAD_PITCH_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVC597_TEXHEAD_PITCH_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVC597_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVC597_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVC597_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVC597_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVC597_TEXHEAD_PITCH_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVC597_TEXHEAD_PITCH_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVC597_TEXHEAD_PITCH_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVC597_TEXHEAD_PITCH_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVC597_TEXHEAD_PITCH_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVC597_TEXHEAD_PITCH_SECTOR_PROMOTION MW(156:155) +#define NVC597_TEXHEAD_PITCH_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVC597_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVC597_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVC597_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVC597_TEXHEAD_PITCH_BORDER_SIZE MW(159:157) +#define NVC597_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVC597_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVC597_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVC597_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVC597_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVC597_TEXHEAD_PITCH_HEIGHT_MINUS_ONE MW(175:160) +#define NVC597_TEXHEAD_PITCH_DEPTH_MINUS_ONE MW(189:176) +#define NVC597_TEXHEAD_PITCH_RESERVED5A MW(190:190) +#define NVC597_TEXHEAD_PITCH_NORMALIZED_COORDS MW(191:191) +#define NVC597_TEXHEAD_PITCH_RESERVED6Y MW(192:192) +#define NVC597_TEXHEAD_PITCH_TRILIN_OPT MW(197:193) +#define NVC597_TEXHEAD_PITCH_MIP_LOD_BIAS MW(210:198) +#define NVC597_TEXHEAD_PITCH_ANISO_BIAS MW(214:211) +#define NVC597_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVC597_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC597_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC597_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC597_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC597_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVC597_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC597_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC597_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC597_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC597_TEXHEAD_PITCH_MAX_ANISOTROPY MW(221:219) +#define NVC597_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVC597_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVC597_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVC597_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVC597_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVC597_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVC597_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVC597_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVC597_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVC597_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC597_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC597_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC597_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC597_TEXHEAD_PITCH_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVC597_TEXHEAD_PITCH_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVC597_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT MW(235:232) +#define NVC597_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVC597_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVC597_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVC597_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVC597_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVC597_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVC597_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVC597_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVC597_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVC597_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVC597_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVC597_TEXHEAD_PITCH_MIN_LOD_CLAMP MW(247:236) +#define NVC597_TEXHEAD_PITCH_RESERVED7Y MW(255:248) + + +/* +** Texture Header State Pitch Color Key + */ + +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS MW(6:0) +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVC597_TEXHEAD_PITCHCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVC597_TEXHEAD_PITCHCK_R_DATA_TYPE MW(9:7) +#define NVC597_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC597_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC597_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC597_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC597_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC597_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC597_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_TEXHEAD_PITCHCK_G_DATA_TYPE MW(12:10) +#define NVC597_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC597_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC597_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC597_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC597_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC597_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC597_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_TEXHEAD_PITCHCK_B_DATA_TYPE MW(15:13) +#define NVC597_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC597_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC597_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC597_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC597_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC597_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC597_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_TEXHEAD_PITCHCK_A_DATA_TYPE MW(18:16) +#define NVC597_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC597_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC597_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC597_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC597_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC597_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC597_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_TEXHEAD_PITCHCK_X_SOURCE MW(21:19) +#define NVC597_TEXHEAD_PITCHCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVC597_TEXHEAD_PITCHCK_X_SOURCE_IN_R 0x00000002 +#define NVC597_TEXHEAD_PITCHCK_X_SOURCE_IN_G 0x00000003 +#define NVC597_TEXHEAD_PITCHCK_X_SOURCE_IN_B 0x00000004 +#define NVC597_TEXHEAD_PITCHCK_X_SOURCE_IN_A 0x00000005 +#define NVC597_TEXHEAD_PITCHCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVC597_TEXHEAD_PITCHCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC597_TEXHEAD_PITCHCK_Y_SOURCE MW(24:22) +#define NVC597_TEXHEAD_PITCHCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVC597_TEXHEAD_PITCHCK_Y_SOURCE_IN_R 0x00000002 +#define NVC597_TEXHEAD_PITCHCK_Y_SOURCE_IN_G 0x00000003 +#define NVC597_TEXHEAD_PITCHCK_Y_SOURCE_IN_B 0x00000004 +#define NVC597_TEXHEAD_PITCHCK_Y_SOURCE_IN_A 0x00000005 +#define NVC597_TEXHEAD_PITCHCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVC597_TEXHEAD_PITCHCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC597_TEXHEAD_PITCHCK_Z_SOURCE MW(27:25) +#define NVC597_TEXHEAD_PITCHCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVC597_TEXHEAD_PITCHCK_Z_SOURCE_IN_R 0x00000002 +#define NVC597_TEXHEAD_PITCHCK_Z_SOURCE_IN_G 0x00000003 +#define NVC597_TEXHEAD_PITCHCK_Z_SOURCE_IN_B 0x00000004 +#define NVC597_TEXHEAD_PITCHCK_Z_SOURCE_IN_A 0x00000005 +#define NVC597_TEXHEAD_PITCHCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVC597_TEXHEAD_PITCHCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC597_TEXHEAD_PITCHCK_W_SOURCE MW(30:28) +#define NVC597_TEXHEAD_PITCHCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVC597_TEXHEAD_PITCHCK_W_SOURCE_IN_R 0x00000002 +#define NVC597_TEXHEAD_PITCHCK_W_SOURCE_IN_G 0x00000003 +#define NVC597_TEXHEAD_PITCHCK_W_SOURCE_IN_B 0x00000004 +#define NVC597_TEXHEAD_PITCHCK_W_SOURCE_IN_A 0x00000005 +#define NVC597_TEXHEAD_PITCHCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVC597_TEXHEAD_PITCHCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC597_TEXHEAD_PITCHCK_PACK_COMPONENTS MW(31:31) +#define NVC597_TEXHEAD_PITCHCK_RESERVED1A MW(36:32) +#define NVC597_TEXHEAD_PITCHCK_ADDRESS_BITS31TO5 MW(63:37) +#define NVC597_TEXHEAD_PITCHCK_ADDRESS_BITS48TO32 MW(80:64) +#define NVC597_TEXHEAD_PITCHCK_RESERVED_ADDRESS MW(84:81) +#define NVC597_TEXHEAD_PITCHCK_HEADER_VERSION MW(87:85) +#define NVC597_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVC597_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVC597_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVC597_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVC597_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVC597_TEXHEAD_PITCHCK_RESERVED_HEADER_VERSION MW(88:88) +#define NVC597_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVC597_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVC597_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVC597_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVC597_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVC597_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVC597_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVC597_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVC597_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVC597_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVC597_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVC597_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVC597_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVC597_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVC597_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVC597_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVC597_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVC597_TEXHEAD_PITCHCK_RESERVED2A MW(95:93) +#define NVC597_TEXHEAD_PITCHCK_PITCH_BITS20TO5 MW(111:96) +#define NVC597_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY2 MW(112:112) +#define NVC597_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY MW(113:113) +#define NVC597_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC597_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC597_TEXHEAD_PITCHCK_LOD_ISO_QUALITY MW(114:114) +#define NVC597_TEXHEAD_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC597_TEXHEAD_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC597_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVC597_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC597_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC597_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC597_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC597_TEXHEAD_PITCHCK_ANISO_SPREAD_SCALE MW(121:117) +#define NVC597_TEXHEAD_PITCHCK_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVC597_TEXHEAD_PITCHCK_DEPTH_TEXTURE MW(123:123) +#define NVC597_TEXHEAD_PITCHCK_MAX_MIP_LEVEL MW(127:124) +#define NVC597_TEXHEAD_PITCHCK_WIDTH_MINUS_ONE MW(144:128) +#define NVC597_TEXHEAD_PITCHCK_PITCH_BIT21 MW(145:145) +#define NVC597_TEXHEAD_PITCHCK_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVC597_TEXHEAD_PITCHCK_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVC597_TEXHEAD_PITCHCK_S_R_G_B_CONVERSION MW(150:150) +#define NVC597_TEXHEAD_PITCHCK_TEXTURE_TYPE MW(154:151) +#define NVC597_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVC597_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVC597_TEXHEAD_PITCHCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVC597_TEXHEAD_PITCHCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVC597_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVC597_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVC597_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVC597_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVC597_TEXHEAD_PITCHCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVC597_TEXHEAD_PITCHCK_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVC597_TEXHEAD_PITCHCK_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVC597_TEXHEAD_PITCHCK_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVC597_TEXHEAD_PITCHCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVC597_TEXHEAD_PITCHCK_SECTOR_PROMOTION MW(156:155) +#define NVC597_TEXHEAD_PITCHCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVC597_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVC597_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVC597_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVC597_TEXHEAD_PITCHCK_BORDER_SIZE MW(159:157) +#define NVC597_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVC597_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVC597_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVC597_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVC597_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVC597_TEXHEAD_PITCHCK_HEIGHT_MINUS_ONE MW(175:160) +#define NVC597_TEXHEAD_PITCHCK_DEPTH_MINUS_ONE MW(189:176) +#define NVC597_TEXHEAD_PITCHCK_RESERVED5A MW(190:190) +#define NVC597_TEXHEAD_PITCHCK_NORMALIZED_COORDS MW(191:191) +#define NVC597_TEXHEAD_PITCHCK_COLOR_KEY_OP MW(192:192) +#define NVC597_TEXHEAD_PITCHCK_TRILIN_OPT MW(197:193) +#define NVC597_TEXHEAD_PITCHCK_MIP_LOD_BIAS MW(210:198) +#define NVC597_TEXHEAD_PITCHCK_ANISO_BIAS MW(214:211) +#define NVC597_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVC597_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC597_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC597_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC597_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC597_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVC597_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC597_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC597_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC597_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC597_TEXHEAD_PITCHCK_MAX_ANISOTROPY MW(221:219) +#define NVC597_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVC597_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVC597_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVC597_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVC597_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVC597_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVC597_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVC597_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVC597_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVC597_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC597_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC597_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC597_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC597_TEXHEAD_PITCHCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Sampler State + */ + +#define NVC597_TEXSAMP0_ADDRESS_U 2:0 +#define NVC597_TEXSAMP0_ADDRESS_U_WRAP 0x00000000 +#define NVC597_TEXSAMP0_ADDRESS_U_MIRROR 0x00000001 +#define NVC597_TEXSAMP0_ADDRESS_U_CLAMP_TO_EDGE 0x00000002 +#define NVC597_TEXSAMP0_ADDRESS_U_BORDER 0x00000003 +#define NVC597_TEXSAMP0_ADDRESS_U_CLAMP_OGL 0x00000004 +#define NVC597_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVC597_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_BORDER 0x00000006 +#define NVC597_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVC597_TEXSAMP0_ADDRESS_V 5:3 +#define NVC597_TEXSAMP0_ADDRESS_V_WRAP 0x00000000 +#define NVC597_TEXSAMP0_ADDRESS_V_MIRROR 0x00000001 +#define NVC597_TEXSAMP0_ADDRESS_V_CLAMP_TO_EDGE 0x00000002 +#define NVC597_TEXSAMP0_ADDRESS_V_BORDER 0x00000003 +#define NVC597_TEXSAMP0_ADDRESS_V_CLAMP_OGL 0x00000004 +#define NVC597_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVC597_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_BORDER 0x00000006 +#define NVC597_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVC597_TEXSAMP0_ADDRESS_P 8:6 +#define NVC597_TEXSAMP0_ADDRESS_P_WRAP 0x00000000 +#define NVC597_TEXSAMP0_ADDRESS_P_MIRROR 0x00000001 +#define NVC597_TEXSAMP0_ADDRESS_P_CLAMP_TO_EDGE 0x00000002 +#define NVC597_TEXSAMP0_ADDRESS_P_BORDER 0x00000003 +#define NVC597_TEXSAMP0_ADDRESS_P_CLAMP_OGL 0x00000004 +#define NVC597_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVC597_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_BORDER 0x00000006 +#define NVC597_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVC597_TEXSAMP0_DEPTH_COMPARE 9:9 +#define NVC597_TEXSAMP0_DEPTH_COMPARE_FUNC 12:10 +#define NVC597_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_NEVER 0x00000000 +#define NVC597_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_LESS 0x00000001 +#define NVC597_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_EQUAL 0x00000002 +#define NVC597_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_LEQUAL 0x00000003 +#define NVC597_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_GREATER 0x00000004 +#define NVC597_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_NOTEQUAL 0x00000005 +#define NVC597_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_GEQUAL 0x00000006 +#define NVC597_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_ALWAYS 0x00000007 +#define NVC597_TEXSAMP0_S_R_G_B_CONVERSION 13:13 +#define NVC597_TEXSAMP0_RESERVED0A 16:14 +#define NVC597_TEXSAMP0_RESERVED0B 19:17 +#define NVC597_TEXSAMP0_MAX_ANISOTROPY 22:20 +#define NVC597_TEXSAMP0_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVC597_TEXSAMP0_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVC597_TEXSAMP0_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVC597_TEXSAMP0_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVC597_TEXSAMP0_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVC597_TEXSAMP0_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVC597_TEXSAMP0_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVC597_TEXSAMP0_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVC597_TEXSAMP0_FORCED_INVALID 31:31 +#define NVC597_TEXSAMP1_MAG_FILTER 2:0 +#define NVC597_TEXSAMP1_MAG_FILTER_MAG_POINT 0x00000001 +#define NVC597_TEXSAMP1_MAG_FILTER_MAG_LINEAR 0x00000002 +#define NVC597_TEXSAMP1_MAG_FILTER_VCAA_4_TAP 0x00000003 +#define NVC597_TEXSAMP1_MAG_FILTER_VCAA_8_TAP 0x00000004 +#define NVC597_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP 3:3 +#define NVC597_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP_INTEGER_AND_FRACTION 0x00000000 +#define NVC597_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP_INTEGER_ONLY 0x00000001 +#define NVC597_TEXSAMP1_MIN_FILTER 5:4 +#define NVC597_TEXSAMP1_MIN_FILTER_MIN_POINT 0x00000001 +#define NVC597_TEXSAMP1_MIN_FILTER_MIN_LINEAR 0x00000002 +#define NVC597_TEXSAMP1_MIN_FILTER_MIN_ANISO 0x00000003 +#define NVC597_TEXSAMP1_MIP_FILTER 7:6 +#define NVC597_TEXSAMP1_MIP_FILTER_MIP_NONE 0x00000001 +#define NVC597_TEXSAMP1_MIP_FILTER_MIP_POINT 0x00000002 +#define NVC597_TEXSAMP1_MIP_FILTER_MIP_LINEAR 0x00000003 +#define NVC597_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING 9:8 +#define NVC597_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_USE_WRAP 0x00000000 +#define NVC597_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_OVERRIDE_WRAP 0x00000001 +#define NVC597_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_AUTO_SPAN_SEAM 0x00000002 +#define NVC597_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_AUTO_CROSS_SEAM 0x00000003 +#define NVC597_TEXSAMP1_REDUCTION_FILTER 11:10 +#define NVC597_TEXSAMP1_REDUCTION_FILTER_RED_NONE 0x00000000 +#define NVC597_TEXSAMP1_REDUCTION_FILTER_RED_MINIMUM 0x00000001 +#define NVC597_TEXSAMP1_REDUCTION_FILTER_RED_MAXIMUM 0x00000002 +#define NVC597_TEXSAMP1_MIP_LOD_BIAS 24:12 +#define NVC597_TEXSAMP1_FLOAT_COORD_NORMALIZATION 25:25 +#define NVC597_TEXSAMP1_FLOAT_COORD_NORMALIZATION_USE_HEADER_SETTING 0x00000000 +#define NVC597_TEXSAMP1_FLOAT_COORD_NORMALIZATION_FORCE_UNNORMALIZED_COORDS 0x00000001 +#define NVC597_TEXSAMP1_TRILIN_OPT 30:26 +#define NVC597_TEXSAMP2_MIN_LOD_CLAMP 11:0 +#define NVC597_TEXSAMP2_MAX_LOD_CLAMP 23:12 +#define NVC597_TEXSAMP2_S_R_G_B_BORDER_COLOR_R 31:24 +#define NVC597_TEXSAMP3_RESERVED12 11:0 +#define NVC597_TEXSAMP3_S_R_G_B_BORDER_COLOR_G 19:12 +#define NVC597_TEXSAMP3_S_R_G_B_BORDER_COLOR_B 27:20 +#define NVC597_TEXSAMP4_BORDER_COLOR_R 31:0 +#define NVC597_TEXSAMP5_BORDER_COLOR_G 31:0 +#define NVC597_TEXSAMP6_BORDER_COLOR_B 31:0 +#define NVC597_TEXSAMP7_BORDER_COLOR_A 31:0 + + + +#endif // #ifndef __CLC597TEX_H__ diff --git a/userspace/sdks/nv570/inc/class/clc5b5.h b/userspace/sdks/nv570/inc/class/clc5b5.h new file mode 100644 index 0000000..cc3633e --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc5b5.h @@ -0,0 +1,282 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clc5b5_h_ +#define _clc5b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define TURING_DMA_COPY_A (0x0000C5B5) + +#define NVC5B5_NOP (0x00000100) +#define NVC5B5_NOP_PARAMETER 31:0 +#define NVC5B5_PM_TRIGGER (0x00000140) +#define NVC5B5_PM_TRIGGER_V 31:0 +#define NVC5B5_SET_SEMAPHORE_A (0x00000240) +#define NVC5B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC5B5_SET_SEMAPHORE_B (0x00000244) +#define NVC5B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC5B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC5B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC5B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC5B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC5B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC5B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC5B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC5B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC5B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC5B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC5B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC5B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC5B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC5B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC5B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC5B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC5B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC5B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC5B5_SET_SRC_PHYS_MODE_BASIC_KIND 5:2 +#define NVC5B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC5B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC5B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC5B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC5B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC5B5_SET_DST_PHYS_MODE_BASIC_KIND 5:2 +#define NVC5B5_LAUNCH_DMA (0x00000300) +#define NVC5B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC5B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC5B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC5B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC5B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC5B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC5B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC5B5_LAUNCH_DMA_FLUSH_TYPE 25:25 +#define NVC5B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000) +#define NVC5B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE (0x00000003) +#define NVC5B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC5B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC5B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC5B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC5B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC5B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC5B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC5B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC5B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC5B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC5B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC5B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC5B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC5B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC5B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC5B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC5B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC5B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC5B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC5B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC5B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC5B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC5B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC5B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC5B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC5B5_LAUNCH_DMA_SRC_BYPASS_L2 20:20 +#define NVC5B5_LAUNCH_DMA_SRC_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC5B5_LAUNCH_DMA_SRC_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC5B5_LAUNCH_DMA_DST_BYPASS_L2 21:21 +#define NVC5B5_LAUNCH_DMA_DST_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC5B5_LAUNCH_DMA_DST_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC5B5_LAUNCH_DMA_VPRMODE 23:22 +#define NVC5B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVC5B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC5B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC5B5_LAUNCH_DMA_DISABLE_PLC 26:26 +#define NVC5B5_LAUNCH_DMA_DISABLE_PLC_FALSE (0x00000000) +#define NVC5B5_LAUNCH_DMA_DISABLE_PLC_TRUE (0x00000001) +#define NVC5B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 +#define NVC5B5_OFFSET_IN_UPPER (0x00000400) +#define NVC5B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC5B5_OFFSET_IN_LOWER (0x00000404) +#define NVC5B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC5B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC5B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC5B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC5B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC5B5_PITCH_IN (0x00000410) +#define NVC5B5_PITCH_IN_VALUE 31:0 +#define NVC5B5_PITCH_OUT (0x00000414) +#define NVC5B5_PITCH_OUT_VALUE 31:0 +#define NVC5B5_LINE_LENGTH_IN (0x00000418) +#define NVC5B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC5B5_LINE_COUNT (0x0000041C) +#define NVC5B5_LINE_COUNT_VALUE 31:0 +#define NVC5B5_SET_REMAP_CONST_A (0x00000700) +#define NVC5B5_SET_REMAP_CONST_A_V 31:0 +#define NVC5B5_SET_REMAP_CONST_B (0x00000704) +#define NVC5B5_SET_REMAP_CONST_B_V 31:0 +#define NVC5B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC5B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC5B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC5B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC5B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC5B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC5B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC5B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC5B5_SET_DST_WIDTH (0x00000710) +#define NVC5B5_SET_DST_WIDTH_V 31:0 +#define NVC5B5_SET_DST_HEIGHT (0x00000714) +#define NVC5B5_SET_DST_HEIGHT_V 31:0 +#define NVC5B5_SET_DST_DEPTH (0x00000718) +#define NVC5B5_SET_DST_DEPTH_V 31:0 +#define NVC5B5_SET_DST_LAYER (0x0000071C) +#define NVC5B5_SET_DST_LAYER_V 31:0 +#define NVC5B5_SET_DST_ORIGIN (0x00000720) +#define NVC5B5_SET_DST_ORIGIN_X 15:0 +#define NVC5B5_SET_DST_ORIGIN_Y 31:16 +#define NVC5B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC5B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC5B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC5B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC5B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC5B5_SET_SRC_WIDTH (0x0000072C) +#define NVC5B5_SET_SRC_WIDTH_V 31:0 +#define NVC5B5_SET_SRC_HEIGHT (0x00000730) +#define NVC5B5_SET_SRC_HEIGHT_V 31:0 +#define NVC5B5_SET_SRC_DEPTH (0x00000734) +#define NVC5B5_SET_SRC_DEPTH_V 31:0 +#define NVC5B5_SET_SRC_LAYER (0x00000738) +#define NVC5B5_SET_SRC_LAYER_V 31:0 +#define NVC5B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC5B5_SET_SRC_ORIGIN_X 15:0 +#define NVC5B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC5B5_SRC_ORIGIN_X (0x00000744) +#define NVC5B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC5B5_SRC_ORIGIN_Y (0x00000748) +#define NVC5B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC5B5_DST_ORIGIN_X (0x0000074C) +#define NVC5B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC5B5_DST_ORIGIN_Y (0x00000750) +#define NVC5B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC5B5_PM_TRIGGER_END (0x00001114) +#define NVC5B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc5b5_h + diff --git a/userspace/sdks/nv570/inc/class/clc5b5sw.h b/userspace/sdks/nv570/inc/class/clc5b5sw.h new file mode 100644 index 0000000..12b3cc0 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc5b5sw.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc5b5sw.finn +// + + + +// +// Using VERSION_0 will cause the API to interpret +// engineType as a CE engine instance. This allows +// for backward compatibility with 85B5sw and 90B5sw. +// +#define NVC5B5_ALLOCATION_PARAMETERS_VERSION_0 0 + +// +// Using VERSION_1 will cause the API to interpret +// engineType as an NV2080_ENGINE_TYPE ordinal. +// +#define NVC5B5_ALLOCATION_PARAMETERS_VERSION_1 1 + +#define NVC5B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc5b5U) + +typedef struct NVC5B5_ALLOCATION_PARAMETERS { + NvU32 version; + NvU32 engineType; +} NVC5B5_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clc5c0.h b/userspace/sdks/nv570/inc/class/clc5c0.h new file mode 100644 index 0000000..51e0837 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc5c0.h @@ -0,0 +1,732 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_turing_compute_a_h_ +#define _cl_turing_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl turing_compute_a */ + +#include "nvtypes.h" + +#define TURING_COMPUTE_A 0xC5C0 + +#define NVC5C0_SET_OBJECT 0x0000 +#define NVC5C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC5C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC5C0_NO_OPERATION 0x0100 +#define NVC5C0_NO_OPERATION_V 31:0 + +#define NVC5C0_SET_NOTIFY_A 0x0104 +#define NVC5C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC5C0_SET_NOTIFY_B 0x0108 +#define NVC5C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_NOTIFY 0x010c +#define NVC5C0_NOTIFY_TYPE 31:0 +#define NVC5C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC5C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC5C0_WAIT_FOR_IDLE 0x0110 +#define NVC5C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC5C0_SEND_GO_IDLE 0x013c +#define NVC5C0_SEND_GO_IDLE_V 31:0 + +#define NVC5C0_PM_TRIGGER 0x0140 +#define NVC5C0_PM_TRIGGER_V 31:0 + +#define NVC5C0_PM_TRIGGER_WFI 0x0144 +#define NVC5C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC5C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC5C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC5C0_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC5C0_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC5C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC5C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC5C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC5C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC5C0_LINE_LENGTH_IN 0x0180 +#define NVC5C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC5C0_LINE_COUNT 0x0184 +#define NVC5C0_LINE_COUNT_VALUE 31:0 + +#define NVC5C0_OFFSET_OUT_UPPER 0x0188 +#define NVC5C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC5C0_OFFSET_OUT 0x018c +#define NVC5C0_OFFSET_OUT_VALUE 31:0 + +#define NVC5C0_PITCH_OUT 0x0190 +#define NVC5C0_PITCH_OUT_VALUE 31:0 + +#define NVC5C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC5C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC5C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC5C0_SET_DST_WIDTH 0x0198 +#define NVC5C0_SET_DST_WIDTH_V 31:0 + +#define NVC5C0_SET_DST_HEIGHT 0x019c +#define NVC5C0_SET_DST_HEIGHT_V 31:0 + +#define NVC5C0_SET_DST_DEPTH 0x01a0 +#define NVC5C0_SET_DST_DEPTH_V 31:0 + +#define NVC5C0_SET_DST_LAYER 0x01a4 +#define NVC5C0_SET_DST_LAYER_V 31:0 + +#define NVC5C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC5C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC5C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC5C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC5C0_LAUNCH_DMA 0x01b0 +#define NVC5C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC5C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC5C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC5C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC5C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC5C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC5C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC5C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC5C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC5C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC5C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC5C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC5C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC5C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC5C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC5C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC5C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC5C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC5C0_LOAD_INLINE_DATA 0x01b4 +#define NVC5C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC5C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC5C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC5C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC5C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC5C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC5C0_SET_SM_SCG_CONTROL 0x01e8 +#define NVC5C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS 0:0 +#define NVC5C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE 0x00000000 +#define NVC5C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE 0x00000001 + +#define NVC5C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC5C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC5C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC5C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC5C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC5C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC5C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC5C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC5C0_PERFMON_TRANSFER 0x0210 +#define NVC5C0_PERFMON_TRANSFER_V 31:0 + +#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_A 0x0214 +#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_A_ADDRESS_UPPER 7:0 + +#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_B 0x0218 +#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC5C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC5C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC5C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC5C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC5C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC5C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC5C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC5C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC5C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC5C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC5C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC5C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC5C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC5C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC5C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC5C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC5C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC5C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC5C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC5C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC5C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC5C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC5C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC5C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC5C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC5C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC5C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC5C0_SET_SCG_CONTROL 0x0270 +#define NVC5C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 +#define NVC5C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 +#define NVC5C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 +#define NVC5C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 +#define NVC5C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 + +#define NVC5C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC5C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC5C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC5C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC5C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC5C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC5C0_SET_QMD_VERSION 0x0288 +#define NVC5C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC5C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC5C0_CHECK_QMD_VERSION 0x0290 +#define NVC5C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC5C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC5C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC5C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL 0x029c +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_CONSTANT_BUFFER_MASK 7:0 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE 8:8 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE 12:12 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE 16:16 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE 20:20 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE 24:24 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_TRUE 0x00000001 + +#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC5C0_SCG_HYSTERESIS_CONTROL 0x02a8 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 + +#define NVC5C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC5C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC5C0_SEND_PCAS_A 0x02b4 +#define NVC5C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC5C0_SEND_PCAS_B 0x02b8 +#define NVC5C0_SEND_PCAS_B_FROM 23:0 +#define NVC5C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC5C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC5C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC5C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC5C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC5C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC5C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC5C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC5C0_SET_SKED_CACHE_CONTROL 0x02cc +#define NVC5C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID 0:0 +#define NVC5C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE 0x00000000 +#define NVC5C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE 0x00000001 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC5C0_SET_SPA_VERSION 0x0310 +#define NVC5C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC5C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC5C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC5C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC5C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC5C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC5C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC5C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC5C0_SET_FALCON00 0x0500 +#define NVC5C0_SET_FALCON00_V 31:0 + +#define NVC5C0_SET_FALCON01 0x0504 +#define NVC5C0_SET_FALCON01_V 31:0 + +#define NVC5C0_SET_FALCON02 0x0508 +#define NVC5C0_SET_FALCON02_V 31:0 + +#define NVC5C0_SET_FALCON03 0x050c +#define NVC5C0_SET_FALCON03_V 31:0 + +#define NVC5C0_SET_FALCON04 0x0510 +#define NVC5C0_SET_FALCON04_V 31:0 + +#define NVC5C0_SET_FALCON05 0x0514 +#define NVC5C0_SET_FALCON05_V 31:0 + +#define NVC5C0_SET_FALCON06 0x0518 +#define NVC5C0_SET_FALCON06_V 31:0 + +#define NVC5C0_SET_FALCON07 0x051c +#define NVC5C0_SET_FALCON07_V 31:0 + +#define NVC5C0_SET_FALCON08 0x0520 +#define NVC5C0_SET_FALCON08_V 31:0 + +#define NVC5C0_SET_FALCON09 0x0524 +#define NVC5C0_SET_FALCON09_V 31:0 + +#define NVC5C0_SET_FALCON10 0x0528 +#define NVC5C0_SET_FALCON10_V 31:0 + +#define NVC5C0_SET_FALCON11 0x052c +#define NVC5C0_SET_FALCON11_V 31:0 + +#define NVC5C0_SET_FALCON12 0x0530 +#define NVC5C0_SET_FALCON12_V 31:0 + +#define NVC5C0_SET_FALCON13 0x0534 +#define NVC5C0_SET_FALCON13_V 31:0 + +#define NVC5C0_SET_FALCON14 0x0538 +#define NVC5C0_SET_FALCON14_V 31:0 + +#define NVC5C0_SET_FALCON15 0x053c +#define NVC5C0_SET_FALCON15_V 31:0 + +#define NVC5C0_SET_FALCON16 0x0540 +#define NVC5C0_SET_FALCON16_V 31:0 + +#define NVC5C0_SET_FALCON17 0x0544 +#define NVC5C0_SET_FALCON17_V 31:0 + +#define NVC5C0_SET_FALCON18 0x0548 +#define NVC5C0_SET_FALCON18_V 31:0 + +#define NVC5C0_SET_FALCON19 0x054c +#define NVC5C0_SET_FALCON19_V 31:0 + +#define NVC5C0_SET_FALCON20 0x0550 +#define NVC5C0_SET_FALCON20_V 31:0 + +#define NVC5C0_SET_FALCON21 0x0554 +#define NVC5C0_SET_FALCON21_V 31:0 + +#define NVC5C0_SET_FALCON22 0x0558 +#define NVC5C0_SET_FALCON22_V 31:0 + +#define NVC5C0_SET_FALCON23 0x055c +#define NVC5C0_SET_FALCON23_V 31:0 + +#define NVC5C0_SET_FALCON24 0x0560 +#define NVC5C0_SET_FALCON24_V 31:0 + +#define NVC5C0_SET_FALCON25 0x0564 +#define NVC5C0_SET_FALCON25_V 31:0 + +#define NVC5C0_SET_FALCON26 0x0568 +#define NVC5C0_SET_FALCON26_V 31:0 + +#define NVC5C0_SET_FALCON27 0x056c +#define NVC5C0_SET_FALCON27_V 31:0 + +#define NVC5C0_SET_FALCON28 0x0570 +#define NVC5C0_SET_FALCON28_V 31:0 + +#define NVC5C0_SET_FALCON29 0x0574 +#define NVC5C0_SET_FALCON29_V 31:0 + +#define NVC5C0_SET_FALCON30 0x0578 +#define NVC5C0_SET_FALCON30_V 31:0 + +#define NVC5C0_SET_FALCON31 0x057c +#define NVC5C0_SET_FALCON31_V 31:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC5C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC5C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC5C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC5C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS(i) (0x0da0+(i)*4) +#define NVC5C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC5C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC5C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC5C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC5C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC5C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC5C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC5C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC5C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC5C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC5C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC5C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC5C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC5C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC5C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC5C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC5C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC5C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC5C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC5C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC5C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC5C0_PIPE_NOP 0x1a2c +#define NVC5C0_PIPE_NOP_V 31:0 + +#define NVC5C0_SET_SPARE00 0x1a30 +#define NVC5C0_SET_SPARE00_V 31:0 + +#define NVC5C0_SET_SPARE01 0x1a34 +#define NVC5C0_SET_SPARE01_V 31:0 + +#define NVC5C0_SET_SPARE02 0x1a38 +#define NVC5C0_SET_SPARE02_V 31:0 + +#define NVC5C0_SET_SPARE03 0x1a3c +#define NVC5C0_SET_SPARE03_V 31:0 + +#define NVC5C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC5C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC5C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC5C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC5C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC5C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC5C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC5C0_SET_TRAP_HANDLER_A 0x25f8 +#define NVC5C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC5C0_SET_TRAP_HANDLER_B 0x25fc +#define NVC5C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC5C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC5C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC5C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC5C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC5C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC5C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC5C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC5C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC5C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC5C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC5C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_turing_compute_a_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc637.h b/userspace/sdks/nv570/inc/class/clc637.h new file mode 100644 index 0000000..2f8ec0c --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc637.h @@ -0,0 +1,62 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc637.finn +// + +#define AMPERE_SMC_PARTITION_REF (0xc637U) /* finn: Evaluated from "NVC637_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +// +// This swizzId can be used by root clients like tools for device level +// profiling +// +#define NVC637_DEVICE_PROFILING_SWIZZID (0xFFFFFFFE) + +// +// TODO: Deprecate NVC637_DEVICE_LEVEL_SWIZZID once all the clients are moved to +// NVC637_DEVICE_PROFILING_SWIZZID +// +#define NVC637_DEVICE_LEVEL_SWIZZID NVC637_DEVICE_PROFILING_SWIZZID + +/* NvRmAlloc parameters */ +#define NVC637_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc637U) + +typedef struct NVC637_ALLOCATION_PARAMETERS { + // + // capDescriptor is a file descriptor for unix RM clients, but a void + // pointer for windows RM clients. + // + // capDescriptor is transparent to RM clients i.e. RM's user-mode shim + // populates this field on behalf of clients. + // + NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8); + + NvU32 swizzId; +} NVC637_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clc638.h b/userspace/sdks/nv570/inc/class/clc638.h new file mode 100644 index 0000000..fc038b3 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc638.h @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc638.finn +// + +#define AMPERE_SMC_EXEC_PARTITION_REF (0xc638U) /* finn: Evaluated from "NVC638_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* NvRmAlloc parameters */ +#define NVC638_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc638U) + +typedef struct NVC638_ALLOCATION_PARAMETERS { + // + // capDescriptor is a file descriptor for unix RM clients, but a void + // pointer for windows RM clients. + // + // capDescriptor is transparent to RM clients i.e. RM's user-mode shim + // populates this field on behalf of clients. + // + NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8); + + NvU32 execPartitionId; +} NVC638_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clc639.h b/userspace/sdks/nv570/inc/class/clc639.h new file mode 100644 index 0000000..538ede0 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc639.h @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc639.finn +// + +#define AMPERE_SMC_CONFIG_SESSION (0xc639U) /* finn: Evaluated from "NVC639_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* NvRmAlloc parameters */ +#define NVC639_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc639U) + +typedef struct NVC639_ALLOCATION_PARAMETERS { + // + // capDescriptor is a file descriptor for unix RM clients, but a void + // pointer for windows RM clients. + // + // capDescriptor is transparent to RM clients i.e. RM's user-mode shim + // populates this field on behalf of clients. + // + NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8); +} NVC639_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clc640.h b/userspace/sdks/nv570/inc/class/clc640.h new file mode 100644 index 0000000..885a501 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc640.h @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc640.finn +// + +#define AMPERE_SMC_MONITOR_SESSION (0xc640U) /* finn: Evaluated from "NVC640_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* NvRmAlloc parameters */ +#define NVC640_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc640U) + +typedef struct NVC640_ALLOCATION_PARAMETERS { + // + // capDescriptor is a file descriptor for unix RM clients, but a void + // pointer for windows RM clients. + // + // capDescriptor is transparent to RM clients i.e. RM's user-mode shim + // populates this field on behalf of clients. + // + NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8); +} NVC640_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clc661.h b/userspace/sdks/nv570/inc/class/clc661.h new file mode 100644 index 0000000..d9f8a48 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc661.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clc661_h__ +#define __gh100_clc661_h__ +#define HOPPER_USERMODE_A (0xc661) +#endif // __gh100_clc661_h__ diff --git a/userspace/sdks/nv570/inc/class/clc670.h b/userspace/sdks/nv570/inc/class/clc670.h new file mode 100644 index 0000000..4828651 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc670.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc670.finn +// + +#define NVC670_DISPLAY (0xc670U) /* finn: Evaluated from "NVC670_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NVC670_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc670U) + +typedef struct NVC670_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numDsis; // Number of DSIs in this chip/display +} NVC670_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clc671.h b/userspace/sdks/nv570/inc/class/clc671.h new file mode 100644 index 0000000..0255c8b --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc671.h @@ -0,0 +1,124 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc671_h_ +#define _clc671_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC671_DISP_SF_USER (0x000C671) + +typedef volatile struct _clc671_tag0 { + NvU32 dispSfUserOffset[0x400]; +} _NvC671DispSfUser, NvC671DispSfUserMap; + +#define NVC671_SF_HDMI_INFO_IDX_GENERIC_INFOFRAME 0x00000001 /* */ +#define NVC671_SF_HDMI_INFO_IDX_VSI 0x00000004 /* */ +#define NVC671_SF_HDMI_INFO_CTRL(i,j) (0x000E0000-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVC671_SF_HDMI_INFO_CTRL__SIZE_1 4 /* */ +#define NVC671_SF_HDMI_INFO_CTRL__SIZE_2 5 /* */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x000E0000-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 8 /* */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER 4:4 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_DIS 0x00000000 /* RWI-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_EN 0x00000001 /* RW--V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE 8:8 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_EN 0x00000001 /* RW--V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW 9:9 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_STATUS(i) (0x000E0004-0x000E0000+(i)*1024) /* R--4A */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1 8 /* */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_STATUS_SENT 0:0 /* R-IVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT 0x00000000 /* R-I-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x000E0008-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 8 /* */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x000E000C-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 8 /* */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x000E0010-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 8 /* */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x000E0014-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 8 /* */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x000E0018-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 8 /* */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW(i) (0x000E001C-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW__SIZE_1 8 /* */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _clc671_h_ diff --git a/userspace/sdks/nv570/inc/class/clc673.h b/userspace/sdks/nv570/inc/class/clc673.h new file mode 100644 index 0000000..b5942aa --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc673.h @@ -0,0 +1,505 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc673_h_ +#define _clc673_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC673_DISP_CAPABILITIES 0xC673 + +typedef volatile struct _clc673_tag0 { + NvU32 dispCapabilities[0x400]; +} _NvC673DispCapabilities,NvC673DispCapabilities_Map ; + + +#define NVC673_SYS_CAP 0x0 /* RW-4R */ +#define NVC673_SYS_CAP_HEAD0_EXISTS 0:0 /* RWIVF */ +#define NVC673_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_HEAD1_EXISTS 1:1 /* RWIVF */ +#define NVC673_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_HEAD2_EXISTS 2:2 /* RWIVF */ +#define NVC673_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_HEAD3_EXISTS 3:3 /* RWIVF */ +#define NVC673_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_HEAD4_EXISTS 4:4 /* RWIVF */ +#define NVC673_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_HEAD5_EXISTS 5:5 /* RWIVF */ +#define NVC673_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_HEAD6_EXISTS 6:6 /* RWIVF */ +#define NVC673_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_HEAD7_EXISTS 7:7 /* RWIVF */ +#define NVC673_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVC673_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */ +#define NVC673_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR0_EXISTS 8:8 /* RWIVF */ +#define NVC673_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR1_EXISTS 9:9 /* RWIVF */ +#define NVC673_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR2_EXISTS 10:10 /* RWIVF */ +#define NVC673_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR3_EXISTS 11:11 /* RWIVF */ +#define NVC673_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR4_EXISTS 12:12 /* RWIVF */ +#define NVC673_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR5_EXISTS 13:13 /* RWIVF */ +#define NVC673_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR6_EXISTS 14:14 /* RWIVF */ +#define NVC673_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR7_EXISTS 15:15 /* RWIVF */ +#define NVC673_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* RWIVF */ +#define NVC673_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */ +#define NVC673_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_DSI0_EXISTS 20:20 /* RWIVF */ +#define NVC673_SYS_CAP_DSI0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_DSI0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_DSI1_EXISTS 21:21 /* RWIVF */ +#define NVC673_SYS_CAP_DSI1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_DSI1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_DSI2_EXISTS 22:22 /* RWIVF */ +#define NVC673_SYS_CAP_DSI2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_DSI2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_DSI3_EXISTS 23:23 /* RWIVF */ +#define NVC673_SYS_CAP_DSI3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_DSI3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_DSI_EXISTS(i) (20+(i)):(20+(i)) /* RWIVF */ +#define NVC673_SYS_CAP_DSI_EXISTS__SIZE_1 4 /* */ +#define NVC673_SYS_CAP_DSI_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_DSI_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB 0x4 /* RW-4R */ +#define NVC673_SYS_CAPB_WINDOW0_EXISTS 0:0 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW1_EXISTS 1:1 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW2_EXISTS 2:2 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW3_EXISTS 3:3 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW4_EXISTS 4:4 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW5_EXISTS 5:5 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW6_EXISTS 6:6 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW7_EXISTS 7:7 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW8_EXISTS 8:8 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW8_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW8_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW9_EXISTS 9:9 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW9_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW9_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW10_EXISTS 10:10 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW10_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW10_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW11_EXISTS 11:11 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW11_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW11_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW12_EXISTS 12:12 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW12_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW12_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW13_EXISTS 13:13 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW13_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW13_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW14_EXISTS 14:14 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW14_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW14_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW15_EXISTS 15:15 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW15_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW15_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW16_EXISTS 16:16 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW16_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW16_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW17_EXISTS 17:17 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW17_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW17_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW18_EXISTS 18:18 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW18_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW18_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW19_EXISTS 19:19 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW19_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW19_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW20_EXISTS 20:20 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW20_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW20_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW21_EXISTS 21:21 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW21_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW21_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW22_EXISTS 22:22 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW22_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW22_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW23_EXISTS 23:23 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW23_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW23_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW24_EXISTS 24:24 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW24_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW24_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW25_EXISTS 25:25 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW25_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW25_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW26_EXISTS 26:26 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW26_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW26_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW27_EXISTS 27:27 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW27_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW27_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW28_EXISTS 28:28 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW28_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW28_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW29_EXISTS 29:29 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW29_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW29_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW30_EXISTS 30:30 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW30_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW30_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW31_EXISTS 31:31 /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW31_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW31_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVC673_SYS_CAPB_WINDOW_EXISTS__SIZE_1 32 /* */ +#define NVC673_SYS_CAPB_WINDOW_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAPB_WINDOW_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA 0x10 /* RW-4R */ +#define NVC673_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES 15:0 /* RWIUF */ +#define NVC673_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH 17:16 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B 0x00000002 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B 0x00000003 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_ROTATION 18:18 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_ROTATION_FALSE 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_ROTATION_TRUE 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_PLANAR 19:19 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_PLANAR_FALSE 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_PLANAR_TRUE 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_VGA 20:20 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION 21:21 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_FALSE 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_TRUE 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MSCG 22:22 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MSCG_FALSE 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MSCG_TRUE 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH 23:23 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_FALSE 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_TRUE 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT 26:26 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION 31:30 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B 0x00000002 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B 0x00000003 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC 0x18 /* RW-4R */ +#define NVC673_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE 1:0 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_32B 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_64B 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_128B 0x00000002 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_256B 0x00000003 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED 6:4 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_NONE 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_TWO 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_FOUR 0x00000002 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_EIGHT 0x00000003 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_SIXTEEN 0x00000004 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR 11:11 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_FALSE 0x00000000 /* RWI-V */ +#define NVC673_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_TRUE 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP 12:12 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_FALSE 0x00000000 /* RWI-V */ +#define NVC673_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA(i) (0x680+(i)*32) /* RW-4A */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA__SIZE_1 8 /* */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT 16:16 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT 17:17 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT 18:18 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT 19:19 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT 20:20 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT 21:21 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT 22:22 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT 23:23 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT 24:24 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB(i) (0x684+(i)*32) /* RW-4A */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB__SIZE_1 8 /* */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_VGA 0:0 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_VGA_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_VGA_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGSZ 9:6 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGNR 12:10 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT 15:15 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC(i) (0x688+(i)*32) /* RW-4A */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC__SIZE_1 8 /* */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_OCSC0_PRECISION 4:0 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_OCSC1_PRECISION 12:8 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP 13:13 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_SF_PRECISION 20:16 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_CI_PRECISION 24:21 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB 25:25 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPD(i) (0x68c+(i)*32) /* RW-4A */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPD__SIZE_1 8 /* */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE(i) (0x690+(i)*32) /* RW-4A */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE__SIZE_1 8 /* */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE_DSC_RATEBUFSIZE 3:0 /* RWIUF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE_DSC_LINEBUFSIZE 13:8 /* RWIUF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422 16:16 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420 17:17 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPF(i) (0x694+(i)*32) /* RW-4A */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPF__SIZE_1 8 /* */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPF_VFILTER_MAX_PIXELS 15:0 /* RWIVF */ +#define NVC673_SOR_CAP(i) (0x144+(i)*8) /* RW-4A */ +#define NVC673_SOR_CAP__SIZE_1 8 /* */ +#define NVC673_SOR_CAP_SINGLE_LVDS_18 0:0 /* RWIVF */ +#define NVC673_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_SINGLE_LVDS_24 1:1 /* RWIVF */ +#define NVC673_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_DUAL_LVDS_18 2:2 /* RWIVF */ +#define NVC673_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_DUAL_LVDS_24 3:3 /* RWIVF */ +#define NVC673_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_SINGLE_TMDS_A 8:8 /* RWIVF */ +#define NVC673_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_SINGLE_TMDS_B 9:9 /* RWIVF */ +#define NVC673_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_DUAL_TMDS 11:11 /* RWIVF */ +#define NVC673_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* RWIVF */ +#define NVC673_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_SDI 16:16 /* RWIVF */ +#define NVC673_SOR_CAP_SDI_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_SDI_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_DP_A 24:24 /* RWIVF */ +#define NVC673_SOR_CAP_DP_A_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_DP_A_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_DP_B 25:25 /* RWIVF */ +#define NVC673_SOR_CAP_DP_B_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_DP_B_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_DP_INTERLACE 26:26 /* RWIVF */ +#define NVC673_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_DP_8_LANES 27:27 /* RWIVF */ +#define NVC673_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_HDMI_FRL 28:28 /* RWIVF */ +#define NVC673_SOR_CAP_HDMI_FRL_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_HDMI_FRL_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA(i) (0x780+(i)*32) /* RW-4A */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA__SIZE_1 32 /* */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH 13:10 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT 16:16 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT 17:17 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT 18:18 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT 19:19 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT 20:20 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT 21:21 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT 22:22 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT 23:23 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT 24:24 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB(i) (0x784+(i)*32) /* RW-4A */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB__SIZE_1 32 /* */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION 4:0 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ 9:6 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR 12:10 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT 15:15 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC(i) (0x788+(i)*32) /* RW-4A */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC__SIZE_1 32 /* */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION 4:0 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGSZ 9:6 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGNR 12:10 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT 15:15 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION 20:16 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP 21:21 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD(i) (0x78c+(i)*32) /* RW-4A */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD__SIZE_1 32 /* */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ 3:0 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR 6:4 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD 8:8 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT 9:9 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION 16:12 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION 20:17 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB 21:21 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA 22:22 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE(i) (0x790+(i)*32) /* RW-4A */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE__SIZE_1 32 /* */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION 4:0 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGSZ 9:6 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGNR 12:10 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT 15:15 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION 20:16 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP 21:21 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPF(i) (0x794+(i)*32) /* RW-4A */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPF__SIZE_1 32 /* */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */ +#define NVC673_SOR_CLK_CAP(i) (0x608+(i)*4) /* RW-4A */ +#define NVC673_SOR_CLK_CAP__SIZE_1 8 /* */ +#define NVC673_SOR_CLK_CAP_DP_MAX 7:0 /* RWIUF */ +#define NVC673_SOR_CLK_CAP_TMDS_MAX 23:16 /* RWIUF */ +#define NVC673_SOR_CLK_CAP_LVDS_MAX 31:24 /* RWIUF */ + +#ifdef __cplusplus +}; +#endif /* extern C */ +#endif //_clc673_h_ diff --git a/userspace/sdks/nv570/inc/class/clc67a.h b/userspace/sdks/nv570/inc/class/clc67a.h new file mode 100644 index 0000000..4496969 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc67a.h @@ -0,0 +1,213 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc67a__h_ +#define _clc67a__h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC67A_CURSOR_IMM_CHANNEL_PIO (0x0000C67A) + +typedef volatile struct _clc67a_tag0 { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x7D]; + NvV32 Update; // 0x00000200 - 0x00000203 + NvV32 SetInterlockFlags; // 0x00000204 - 0x00000207 + NvV32 SetCursorHotSpotPointOut[2]; // 0x00000208 - 0x0000020F + NvV32 SetWindowInterlockFlags; // 0x00000210 - 0x00000213 + NvV32 Reserved02[0x37B]; +} NVC67ADispCursorImmControlPio; + +#define NVC67A_FREE (0x00000008) +#define NVC67A_FREE_COUNT 5:0 +#define NVC67A_UPDATE (0x00000200) +#define NVC67A_UPDATE_RELEASE_ELV 0:0 +#define NVC67A_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC67A_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC67A_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC67A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC67A_SET_INTERLOCK_FLAGS (0x00000204) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC67A_SET_CURSOR_HOT_SPOT_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVC67A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0 +#define NVC67A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS (0x00000210) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc67a_h + diff --git a/userspace/sdks/nv570/inc/class/clc67b.h b/userspace/sdks/nv570/inc/class/clc67b.h new file mode 100644 index 0000000..5d73866 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc67b.h @@ -0,0 +1,67 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clC67b_h_ +#define _clC67b_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC67B_WINDOW_IMM_CHANNEL_DMA (0x0000C67B) + +// dma opcode instructions +#define NVC67B_DMA +#define NVC67B_DMA_OPCODE 31:29 +#define NVC67B_DMA_OPCODE_METHOD 0x00000000 +#define NVC67B_DMA_OPCODE_JUMP 0x00000001 +#define NVC67B_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC67B_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC67B_DMA_METHOD_COUNT 27:18 +#define NVC67B_DMA_METHOD_OFFSET 13:2 +#define NVC67B_DMA_DATA 31:0 +#define NVC67B_DMA_DATA_NOP 0x00000000 +#define NVC67B_DMA_JUMP_OFFSET 11:2 +#define NVC67B_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVC67B_PUT (0x00000000) +#define NVC67B_PUT_PTR 9:0 +#define NVC67B_GET (0x00000004) +#define NVC67B_GET_PTR 9:0 +#define NVC67B_UPDATE (0x00000200) +#define NVC67B_UPDATE_RELEASE_ELV 0:0 +#define NVC67B_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC67B_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC67B_UPDATE_INTERLOCK_WITH_WINDOW 1:1 +#define NVC67B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC67B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC67B_SET_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVC67B_SET_POINT_OUT_X 15:0 +#define NVC67B_SET_POINT_OUT_Y 31:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC67b_h diff --git a/userspace/sdks/nv570/inc/class/clc67d.h b/userspace/sdks/nv570/inc/class/clc67d.h new file mode 100644 index 0000000..6b09ded --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc67d.h @@ -0,0 +1,1337 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clC67d_h_ +#define _clC67d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC67D_CORE_CHANNEL_DMA (0x0000C67D) + +#define NV_DISP_NOTIFIER 0x00000000 +#define NV_DISP_NOTIFIER_SIZEOF 0x00000010 +#define NV_DISP_NOTIFIER__0 0x00000000 +#define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFIER__0_FIELD 8:8 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE 9:9 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001 +#define NV_DISP_NOTIFIER__0_R1 15:10 +#define NV_DISP_NOTIFIER__0_R2 23:16 +#define NV_DISP_NOTIFIER__0_R3 29:24 +#define NV_DISP_NOTIFIER__0_STATUS 31:30 +#define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002 +#define NV_DISP_NOTIFIER__1 0x00000001 +#define NV_DISP_NOTIFIER__1_R4 31:0 +#define NV_DISP_NOTIFIER__2 0x00000002 +#define NV_DISP_NOTIFIER__2_TIMESTAMP_LO 31:0 +#define NV_DISP_NOTIFIER__3 0x00000003 +#define NV_DISP_NOTIFIER__3_TIMESTAMP_HI 31:0 + + +// dma opcode instructions +#define NVC67D_DMA +#define NVC67D_DMA_OPCODE 31:29 +#define NVC67D_DMA_OPCODE_METHOD 0x00000000 +#define NVC67D_DMA_OPCODE_JUMP 0x00000001 +#define NVC67D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC67D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC67D_DMA_METHOD_COUNT 27:18 +#define NVC67D_DMA_METHOD_OFFSET 13:2 +#define NVC67D_DMA_DATA 31:0 +#define NVC67D_DMA_DATA_NOP 0x00000000 +#define NVC67D_DMA_JUMP_OFFSET 11:2 +#define NVC67D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// if cap SUPPORT_FLEXIBLE_WIN_MAPPING is FALSE, this define can be used to obtain which head a window is mapped to +#define NVC37D_WINDOW_MAPPED_TO_HEAD(w) ((w)>>1) +#define NVC37D_GET_VALID_WINDOWMASK_FOR_HEAD(h) ((1<<((h)*2)) | (1<<((h)*2+1))) + +// class methods +#define NVC67D_PUT (0x00000000) +#define NVC67D_PUT_PTR 9:0 +#define NVC67D_GET (0x00000004) +#define NVC67D_GET_PTR 9:0 +#define NVC67D_UPDATE (0x00000200) +#define NVC67D_UPDATE_SPECIAL_HANDLING 21:20 +#define NVC67D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NVC67D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NVC67D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NVC67D_UPDATE_SPECIAL_HANDLING_REASON 19:12 +#define NVC67D_UPDATE_INHIBIT_INTERRUPTS 24:24 +#define NVC67D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NVC67D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NVC67D_UPDATE_RELEASE_ELV 0:0 +#define NVC67D_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC67D_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC67D_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC67D_SET_CONTEXT_DMA_NOTIFIER (0x00000208) +#define NVC67D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NVC67D_SET_NOTIFIER_CONTROL (0x0000020C) +#define NVC67D_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC67D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC67D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC67D_SET_NOTIFIER_CONTROL_OFFSET 11:4 +#define NVC67D_SET_NOTIFIER_CONTROL_NOTIFY 12:12 +#define NVC67D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NVC67D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NVC67D_SET_CONTROL (0x00000210) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN(i) ((i)+0):((i)+0) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN__SIZE_1 4 +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN_DISABLE (0x00000000) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN_ENABLE (0x00000001) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN0 0:0 +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN0_DISABLE (0x00000000) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN0_ENABLE (0x00000001) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN1 1:1 +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN1_DISABLE (0x00000000) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN1_ENABLE (0x00000001) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN2 2:2 +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN2_DISABLE (0x00000000) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN2_ENABLE (0x00000001) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN3 3:3 +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN3_DISABLE (0x00000000) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN3_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS (0x00000218) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+0):((i)+0) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS (0x0000021C) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVC67D_GET_RG_SCAN_LINE(b) (0x00000220 + (b)*0x00000004) +#define NVC67D_GET_RG_SCAN_LINE_LINE 15:0 +#define NVC67D_GET_RG_SCAN_LINE_VBLANK 16:16 +#define NVC67D_GET_RG_SCAN_LINE_VBLANK_FALSE (0x00000000) +#define NVC67D_GET_RG_SCAN_LINE_VBLANK_TRUE (0x00000001) +#define NVC67D_SET_GET_BLANKING_CTRL(b) (0x00000240 + (b)*0x00000004) +#define NVC67D_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NVC67D_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NVC67D_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NVC67D_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NVC67D_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NVC67D_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) + +#define NVC67D_SOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK 7:0 +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVC67D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NVC67D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NVC67D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NVC67D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NVC67D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NVC67D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NVC67D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NVC67D_SOR_SET_CONTROL_PROTOCOL_HDMI_FRL (0x0000000C) +#define NVC67D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NVC67D_SOR_SET_CONTROL_DE_SYNC_POLARITY 16:16 +#define NVC67D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC67D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC67D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NVC67D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NVC67D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NVC67D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NVC67D_SOR_SET_CUSTOM_REASON(a) (0x00000304 + (a)*0x00000020) +#define NVC67D_SOR_SET_CUSTOM_REASON_CODE 31:0 +#define NVC67D_SOR_SET_SW_SPARE_A(a) (0x00000308 + (a)*0x00000020) +#define NVC67D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NVC67D_SOR_SET_SW_SPARE_B(a) (0x0000030C + (a)*0x00000020) +#define NVC67D_SOR_SET_SW_SPARE_B_CODE 31:0 + +#define NVC67D_DSI_SET_CONTROL(a) (0x00000500 + (a)*0x00000020) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK 7:0 +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVC67D_DSI_SET_CUSTOM_REASON(a) (0x00000504 + (a)*0x00000020) +#define NVC67D_DSI_SET_CUSTOM_REASON_CODE 31:0 +#define NVC67D_DSI_SET_SW_SPARE_A(a) (0x00000508 + (a)*0x00000020) +#define NVC67D_DSI_SET_SW_SPARE_A_CODE 31:0 +#define NVC67D_DSI_SET_SW_SPARE_B(a) (0x0000050C + (a)*0x00000020) +#define NVC67D_DSI_SET_SW_SPARE_B_CODE 31:0 + +#define NVC67D_WINDOW_SET_CONTROL(a) (0x00001000 + (a)*0x00000080) +#define NVC67D_WINDOW_SET_CONTROL_OWNER 3:0 +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD(i) (0x00000000 +(i)) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD__SIZE_1 8 +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD0 (0x00000000) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD1 (0x00000001) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD2 (0x00000002) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD3 (0x00000003) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD4 (0x00000004) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD5 (0x00000005) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD6 (0x00000006) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD7 (0x00000007) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_NONE (0x0000000F) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0x00000080) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a) (0x00001008 + (a)*0x00000080) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR(a) (0x0000100C + (a)*0x00000080) +#define NVC67D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVC67D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a) (0x00001010 + (a)*0x00000080) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_MAX_PIXELS_FETCHED_PER_LINE 14:0 +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED 16:16 +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED 28:28 +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS 22:20 +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED 24:24 +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED 30:30 +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED_TRUE (0x00000001) + +#define NVC67D_HEAD_SET_PROCAMP(a) (0x00002000 + (a)*0x00000400) +#define NVC67D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NVC67D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NVC67D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NVC67D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NVC67D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003) +#define NVC67D_HEAD_SET_PROCAMP_CHROMA_LPF 3:3 +#define NVC67D_HEAD_SET_PROCAMP_CHROMA_LPF_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_PROCAMP_CHROMA_LPF_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_PROCAMP_CHROMA_DOWN_V 4:4 +#define NVC67D_HEAD_SET_PROCAMP_CHROMA_DOWN_V_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_PROCAMP_CHROMA_DOWN_V_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 28:28 +#define NVC67D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NVC67D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00002004 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 2:2 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 3:3 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 7:4 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000003) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000004) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000005) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000006) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000007) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000008) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_444 (0x00000009) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444NP (0x0000000A) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 24:24 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 23:12 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN 31:26 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN0 (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN1 (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN2 (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN3 (0x00000003) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN4 (0x00000004) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN5 (0x00000005) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN6 (0x00000006) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN7 (0x00000007) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN8 (0x00000008) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN9 (0x00000009) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN10 (0x0000000A) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN11 (0x0000000B) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN12 (0x0000000C) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN13 (0x0000000D) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN14 (0x0000000E) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN15 (0x0000000F) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN16 (0x00000010) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN17 (0x00000011) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN18 (0x00000012) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN19 (0x00000013) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN20 (0x00000014) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN21 (0x00000015) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN22 (0x00000016) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN23 (0x00000017) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN24 (0x00000018) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN25 (0x00000019) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN26 (0x0000001A) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN27 (0x0000001B) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN28 (0x0000001C) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN29 (0x0000001D) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN30 (0x0000001E) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN31 (0x0000001F) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_NONE (0x0000003F) +#define NVC67D_HEAD_SET_CONTROL(a) (0x00002008 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CONTROL_STRUCTURE 1:0 +#define NVC67D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE 2:2 +#define NVC67D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_NORMAL (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_YUV420PACKER 3:3 +#define NVC67D_HEAD_SET_CONTROL_YUV420PACKER_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_YUV420PACKER_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 11:10 +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 8:4 +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 15:12 +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 23:22 +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 20:16 +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN 28:24 +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000003) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000004) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000005) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000006) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000007) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000008) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000009) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000B) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000C) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000D) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000E) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000F) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x00000010) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NVC67D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NVC67D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x0000200C + (a)*0x00000400) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC67D_HEAD_SET_PIXEL_REORDER_CONTROL(a) (0x00002010 + (a)*0x00000400) +#define NVC67D_HEAD_SET_PIXEL_REORDER_CONTROL_BANK_WIDTH 13:0 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00002014 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVC67D_HEAD_SET_DITHER_CONTROL(a) (0x00002018 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NVC67D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_DITHER_CONTROL_BITS 5:4 +#define NVC67D_HEAD_SET_DITHER_CONTROL_BITS_TO_6_BITS (0x00000000) +#define NVC67D_HEAD_SET_DITHER_CONTROL_BITS_TO_8_BITS (0x00000001) +#define NVC67D_HEAD_SET_DITHER_CONTROL_BITS_TO_10_BITS (0x00000002) +#define NVC67D_HEAD_SET_DITHER_CONTROL_BITS_TO_12_BITS (0x00000003) +#define NVC67D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE 2:2 +#define NVC67D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_DITHER_CONTROL_MODE 10:8 +#define NVC67D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NVC67D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NVC67D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NVC67D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NVC67D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NVC67D_HEAD_SET_DITHER_CONTROL_MODE_ROUND (0x00000005) +#define NVC67D_HEAD_SET_DITHER_CONTROL_PHASE 13:12 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x0000201C + (a)*0x00000400) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 0:0 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING 4:4 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 9:8 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NVC67D_HEAD_SET_DISPLAY_ID(a,b) (0x00002020 + (a)*0x00000400 + (b)*0x00000004) +#define NVC67D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00002028 + (a)*0x00000400) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC67D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR(a) (0x0000202C + (a)*0x00000400) +#define NVC67D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVC67D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS(a) (0x00002030 + (a)*0x00000400) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR 2:0 +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_NONE (0x00000000) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W32_H32 (0x00000001) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W64_H64 (0x00000002) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W128_H128 (0x00000003) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W256_H256 (0x00000004) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED 4:4 +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_FALSE (0x00000000) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_TRUE (0x00000001) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS 14:12 +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED 8:8 +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED 16:16 +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED_FALSE (0x00000000) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED_TRUE (0x00000001) +#define NVC67D_HEAD_SET_STALL_LOCK(a) (0x00002034 + (a)*0x00000400) +#define NVC67D_HEAD_SET_STALL_LOCK_ENABLE 0:0 +#define NVC67D_HEAD_SET_STALL_LOCK_ENABLE_FALSE (0x00000000) +#define NVC67D_HEAD_SET_STALL_LOCK_ENABLE_TRUE (0x00000001) +#define NVC67D_HEAD_SET_STALL_LOCK_MODE 2:2 +#define NVC67D_HEAD_SET_STALL_LOCK_MODE_CONTINUOUS (0x00000000) +#define NVC67D_HEAD_SET_STALL_LOCK_MODE_ONE_SHOT (0x00000001) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN 8:4 +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC67D_HEAD_SET_STALL_LOCK_UNSTALL_MODE 12:12 +#define NVC67D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_CRASH_LOCK (0x00000000) +#define NVC67D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_LINE_LOCK (0x00000001) +#define NVC67D_HEAD_SET_STALL_LOCK_TEPOLARITY 14:14 +#define NVC67D_HEAD_SET_STALL_LOCK_TEPOLARITY_POSITIVE_TRUE (0x00000000) +#define NVC67D_HEAD_SET_STALL_LOCK_TEPOLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC67D_HEAD_SET_STALL_LOCK_UNSTALL_SYNC_ADVANCE 25:16 +#define NVC67D_HEAD_SET_LOCK_CHAIN(a) (0x00002044 + (a)*0x00000400) +#define NVC67D_HEAD_SET_LOCK_CHAIN_POSITION 3:0 +#define NVC67D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x00002048 + (a)*0x00000400) +#define NVC67D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NVC67D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NVC67D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x0000204C + (a)*0x00000400) +#define NVC67D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NVC67D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NVC67D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x00002058 + (a)*0x00000400) +#define NVC67D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NVC67D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NVC67D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x0000205C + (a)*0x00000400) +#define NVC67D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NVC67D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NVC67D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000400) +#define NVC67D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NVC67D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NVC67D_HEAD_SET_RASTER_SYNC_END(a) (0x00002068 + (a)*0x00000400) +#define NVC67D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NVC67D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NVC67D_HEAD_SET_RASTER_BLANK_END(a) (0x0000206C + (a)*0x00000400) +#define NVC67D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NVC67D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NVC67D_HEAD_SET_RASTER_BLANK_START(a) (0x00002070 + (a)*0x00000400) +#define NVC67D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NVC67D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NVC67D_HEAD_SET_OVERSCAN_COLOR(a) (0x00002078 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OVERSCAN_COLOR_RED_CR 9:0 +#define NVC67D_HEAD_SET_OVERSCAN_COLOR_GREEN_Y 19:10 +#define NVC67D_HEAD_SET_OVERSCAN_COLOR_BLUE_CB 29:20 +#define NVC67D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR(a) (0x0000207C + (a)*0x00000400) +#define NVC67D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_RED_CR 9:0 +#define NVC67D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_GREEN_Y 19:10 +#define NVC67D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_BLUE_CB 29:20 +#define NVC67D_HEAD_SET_HDMI_CTRL(a) (0x00002080 + (a)*0x00000400) +#define NVC67D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NVC67D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NVC67D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NVC67D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NVC67D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NVC67D_HEAD_SET_CONTEXT_DMA_CURSOR(a,b) (0x00002088 + (a)*0x00000400 + (b)*0x00000004) +#define NVC67D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0 +#define NVC67D_HEAD_SET_OFFSET_CURSOR(a,b) (0x00002090 + (a)*0x00000400 + (b)*0x00000004) +#define NVC67D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0 +#define NVC67D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x00002098 + (a)*0x00000400) +#define NVC67D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 0:0 +#define NVC67D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NVC67D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_CURSOR(a) (0x0000209C + (a)*0x00000400) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_FORMAT 7:0 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_SIZE 9:8 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 19:12 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 27:20 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION(a) (0x000020A0 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_K1 7:0 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT 11:8 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT 15:12 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_ZERO (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE 16:16 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_BLEND (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_XOR (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS 20:20 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00002180 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NVC67D_HEAD_SET_CRC_CONTROL(a) (0x00002184 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 5:0 +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_0 (0x00000000) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_1 (0x00000001) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_2 (0x00000002) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_3 (0x00000003) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_4 (0x00000004) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_5 (0x00000005) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_6 (0x00000006) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_7 (0x00000007) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_8 (0x00000008) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_9 (0x00000009) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_10 (0x0000000A) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_11 (0x0000000B) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_12 (0x0000000C) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_13 (0x0000000D) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_14 (0x0000000E) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_15 (0x0000000F) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_16 (0x00000010) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_17 (0x00000011) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_18 (0x00000012) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_19 (0x00000013) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_20 (0x00000014) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_21 (0x00000015) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_22 (0x00000016) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_23 (0x00000017) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_24 (0x00000018) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_25 (0x00000019) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_26 (0x0000001A) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_27 (0x0000001B) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_28 (0x0000001C) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_29 (0x0000001D) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_30 (0x0000001E) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_31 (0x0000001F) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000020) +#define NVC67D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 8:8 +#define NVC67D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NVC67D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC 19:12 +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_NONE (0x00000000) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SF (0x00000030) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR__SIZE_1 8 +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR0 (0x00000050) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR1 (0x00000051) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR2 (0x00000052) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR3 (0x00000053) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR4 (0x00000054) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR5 (0x00000055) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR6 (0x00000056) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR7 (0x00000057) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC 27:20 +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_NONE (0x00000000) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SF (0x00000030) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR__SIZE_1 8 +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR0 (0x00000050) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR1 (0x00000051) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR2 (0x00000052) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR3 (0x00000053) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR4 (0x00000054) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR5 (0x00000055) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR6 (0x00000056) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR7 (0x00000057) +#define NVC67D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 9:9 +#define NVC67D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_PRESENT_CONTROL(a) (0x0000218C + (a)*0x00000400) +#define NVC67D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 0:0 +#define NVC67D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NVC67D_HEAD_SET_SW_SPARE_A(a) (0x00002194 + (a)*0x00000400) +#define NVC67D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NVC67D_HEAD_SET_SW_SPARE_B(a) (0x00002198 + (a)*0x00000400) +#define NVC67D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NVC67D_HEAD_SET_SW_SPARE_C(a) (0x0000219C + (a)*0x00000400) +#define NVC67D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NVC67D_HEAD_SET_SW_SPARE_D(a) (0x000021A0 + (a)*0x00000400) +#define NVC67D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NVC67D_HEAD_SET_DISPLAY_RATE(a) (0x000021A8 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DISPLAY_RATE_RUN_MODE 0:0 +#define NVC67D_HEAD_SET_DISPLAY_RATE_RUN_MODE_CONTINUOUS (0x00000000) +#define NVC67D_HEAD_SET_DISPLAY_RATE_RUN_MODE_ONE_SHOT (0x00000001) +#define NVC67D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_INTERVAL 25:4 +#define NVC67D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH 2:2 +#define NVC67D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_CONTEXT_DMA_RG_REL_SEMAPHORE(a,b) (0x000021AC + (a)*0x00000400 + (b)*0x00000004) +#define NVC67D_HEAD_SET_CONTEXT_DMA_RG_REL_SEMAPHORE_HANDLE 31:0 +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL(a,b) (0x000021CC + (a)*0x00000400 + (b)*0x00000004) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_OFFSET 7:0 +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE 14:14 +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE_WRITE (0x00000000) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE 10:10 +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE_ONE_TIME (0x00000000) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE_CONTINUOUS (0x00000001) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RASTER_LINE 30:16 +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_VALUE(a,b) (0x000021EC + (a)*0x00000400 + (b)*0x00000004) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_VALUE 31:0 +#define NVC67D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE(a) (0x00002214 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVC67D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVC67D_HEAD_SET_MIN_FRAME_IDLE(a) (0x00002218 + (a)*0x00000400) +#define NVC67D_HEAD_SET_MIN_FRAME_IDLE_LEADING_RASTER_LINES 14:0 +#define NVC67D_HEAD_SET_MIN_FRAME_IDLE_TRAILING_RASTER_LINES 30:16 +#define NVC67D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED(a) (0x00002220 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED_ALPHA 7:0 +#define NVC67D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED_RED 31:16 +#define NVC67D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE(a) (0x00002224 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE_GREEN 15:0 +#define NVC67D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE_BLUE 31:16 +#define NVC67D_HEAD_SET_CURSOR_COLOR_NORM_SCALE(a) (0x00002228 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CURSOR_COLOR_NORM_SCALE_VALUE 15:0 +#define NVC67D_HEAD_SET_XOR_BLEND_FACTOR(a) (0x0000222C + (a)*0x00000400) +#define NVC67D_HEAD_SET_XOR_BLEND_FACTOR_LOG2PEAK_LUMINANCE 3:0 +#define NVC67D_HEAD_SET_XOR_BLEND_FACTOR_S1 16:4 +#define NVC67D_HEAD_SET_XOR_BLEND_FACTOR_S2 30:18 +#define NVC67D_HEAD_SET_CLAMP_RANGE_GREEN(a) (0x00002238 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CLAMP_RANGE_GREEN_LOW 11:0 +#define NVC67D_HEAD_SET_CLAMP_RANGE_GREEN_HIGH 27:16 +#define NVC67D_HEAD_SET_CLAMP_RANGE_RED_BLUE(a) (0x0000223C + (a)*0x00000400) +#define NVC67D_HEAD_SET_CLAMP_RANGE_RED_BLUE_LOW 11:0 +#define NVC67D_HEAD_SET_CLAMP_RANGE_RED_BLUE_HIGH 27:16 +#define NVC67D_HEAD_SET_OCSC0CONTROL(a) (0x00002240 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0CONTROL_ENABLE 0:0 +#define NVC67D_HEAD_SET_OCSC0CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_OCSC0CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C00(a) (0x00002244 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C00_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C01(a) (0x00002248 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C01_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C02(a) (0x0000224C + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C02_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C03(a) (0x00002250 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C03_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C10(a) (0x00002254 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C10_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C11(a) (0x00002258 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C11_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C12(a) (0x0000225C + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C12_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C13(a) (0x00002260 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C13_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C20(a) (0x00002264 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C20_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C21(a) (0x00002268 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C21_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C22(a) (0x0000226C + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C22_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C23(a) (0x00002270 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C23_VALUE 20:0 +#define NVC67D_HEAD_SET_OLUT_CONTROL(a) (0x00002280 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OLUT_CONTROL_INTERPOLATE 0:0 +#define NVC67D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_OLUT_CONTROL_MIRROR 1:1 +#define NVC67D_HEAD_SET_OLUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_OLUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_OLUT_CONTROL_MODE 3:2 +#define NVC67D_HEAD_SET_OLUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVC67D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVC67D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVC67D_HEAD_SET_OLUT_CONTROL_SIZE 18:8 +#define NVC67D_HEAD_SET_OLUT_FP_NORM_SCALE(a) (0x00002284 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OLUT_FP_NORM_SCALE_VALUE 31:0 +#define NVC67D_HEAD_SET_CONTEXT_DMA_OLUT(a) (0x00002288 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CONTEXT_DMA_OLUT_HANDLE 31:0 +#define NVC67D_HEAD_SET_OFFSET_OLUT(a) (0x0000228C + (a)*0x00000400) +#define NVC67D_HEAD_SET_OFFSET_OLUT_ORIGIN 31:0 +#define NVC67D_HEAD_SET_OCSC1CONTROL(a) (0x0000229C + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1CONTROL_ENABLE 0:0 +#define NVC67D_HEAD_SET_OCSC1CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_OCSC1CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C00(a) (0x000022A0 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C00_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C01(a) (0x000022A4 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C01_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C02(a) (0x000022A8 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C02_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C03(a) (0x000022AC + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C03_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C10(a) (0x000022B0 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C10_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C11(a) (0x000022B4 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C11_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C12(a) (0x000022B8 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C12_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C13(a) (0x000022BC + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C13_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C20(a) (0x000022C0 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C20_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C21(a) (0x000022C4 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C21_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C22(a) (0x000022C8 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C22_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C23(a) (0x000022CC + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C23_VALUE 20:0 +#define NVC67D_HEAD_SET_TILE_POSITION(a) (0x000022D0 + (a)*0x00000400) +#define NVC67D_HEAD_SET_TILE_POSITION_X 2:0 +#define NVC67D_HEAD_SET_TILE_POSITION_Y 6:4 +#define NVC67D_HEAD_SET_DSC_CONTROL(a) (0x000022D4 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_CONTROL_ENABLE 0:0 +#define NVC67D_HEAD_SET_DSC_CONTROL_ENABLE_FALSE (0x00000000) +#define NVC67D_HEAD_SET_DSC_CONTROL_ENABLE_TRUE (0x00000001) +#define NVC67D_HEAD_SET_DSC_CONTROL_MODE 2:1 +#define NVC67D_HEAD_SET_DSC_CONTROL_MODE_SINGLE (0x00000000) +#define NVC67D_HEAD_SET_DSC_CONTROL_MODE_DUAL (0x00000001) +#define NVC67D_HEAD_SET_DSC_CONTROL_MODE_QUAD (0x00000002) +#define NVC67D_HEAD_SET_DSC_CONTROL_AUTO_RESET 3:3 +#define NVC67D_HEAD_SET_DSC_CONTROL_AUTO_RESET_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_DSC_CONTROL_AUTO_RESET_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION 4:4 +#define NVC67D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET 5:5 +#define NVC67D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET_FALSE (0x00000000) +#define NVC67D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET_TRUE (0x00000001) +#define NVC67D_HEAD_SET_DSC_CONTROL_FLATNESS_DET_THRESH 15:6 +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL(a) (0x000022D8 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_ENABLE 0:0 +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_ENABLE_FALSE (0x00000000) +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_ENABLE_TRUE (0x00000001) +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_LOCATION 1:1 +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_VSYNC (0x00000000) +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_VBLANK (0x00000001) +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_SIZE 9:2 +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY 10:10 +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY_ONCE (0x00000001) +#define NVC67D_HEAD_SET_DSC_PPS_HEAD(a) (0x000022DC + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_HEAD_BYTE0 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_HEAD_BYTE1 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_HEAD_BYTE2 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_HEAD_BYTE3 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA0(a) (0x000022E0 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA0_DSC_VERSION_MINOR 3:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA0_DSC_VERSION_MAJOR 7:4 +#define NVC67D_HEAD_SET_DSC_PPS_DATA0_PPS_IDENTIFIER 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA0_RESERVED 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA0_LINEBUF_DEPTH 27:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA0_BITS_PER_COMPONENT 31:28 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1(a) (0x000022E4 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_BITS_PER_PIXEL_HIGH 1:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_VBR_ENABLE 2:2 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_SIMPLE422 3:3 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_CONVERT_RGB 4:4 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_BLOCK_PRED_ENABLE 5:5 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_RESERVED 7:6 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_BITS_PER_PIXEL_LOW 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_PIC_HEIGHT_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_PIC_HEIGHT_LOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA2(a) (0x000022E8 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA2_PIC_WIDTH_HIGH 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA2_PIC_WIDTH_LOW 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA2_SLICE_HEIGHT_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA2_SLICE_HEIGHT_LOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA3(a) (0x000022EC + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA3_SLICE_WIDTH_HIGH 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA3_SLICE_WIDTH_LOW 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA3_CHUNK_SIZE_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA3_CHUNK_SIZE_LOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA4(a) (0x000022F0 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA4_INITIAL_XMIT_DELAY_HIGH 1:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA4_RESERVED 7:2 +#define NVC67D_HEAD_SET_DSC_PPS_DATA4_INITIAL_XMIT_DELAY_LOW 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA4_INITIAL_DEC_DELAY_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA4_INITIAL_DEC_DELAY_LOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA5(a) (0x000022F4 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA5_RESERVED0 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA5_INITIAL_SCALE_VALUE 13:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA5_RESERVED1 15:14 +#define NVC67D_HEAD_SET_DSC_PPS_DATA5_SCALE_INCREMENT_INTERVAL_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA5_SCALE_INCREMENT_INTERVAL_LOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA6(a) (0x000022F8 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA6_SCALE_DECREMENT_INTERVAL_HIGH 3:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA6_RESERVED0 7:4 +#define NVC67D_HEAD_SET_DSC_PPS_DATA6_SCALE_DECREMENT_INTERVAL_LOW 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA6_RESERVED1 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA6_FIRST_LINE_BPG_OFFSET 28:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA6_RESERVED2 31:29 +#define NVC67D_HEAD_SET_DSC_PPS_DATA7(a) (0x000022FC + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA7_NFL_BPG_OFFSET_HIGH 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA7_NFL_BPG_OFFSET_LOW 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA7_SLICE_BPG_OFFSET_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA7_SLICE_BPG_OFFSET_LOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA8(a) (0x00002300 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA8_INITIAL_OFFSET_HIGH 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA8_INITIAL_OFFSET_LOW 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA8_FINAL_OFFSET_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA8_FINAL_OFFSET_LOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA9(a) (0x00002304 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA9_FLATNESS_MIN_QP 4:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA9_RESERVED0 7:5 +#define NVC67D_HEAD_SET_DSC_PPS_DATA9_FLATNESS_MAX_QP 12:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA9_RESERVED1 15:13 +#define NVC67D_HEAD_SET_DSC_PPS_DATA9_RC_MODEL_SIZE_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA9_RC_MODEL_SIZE_LOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA10(a) (0x00002308 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA10_RC_EDGE_FACTOR 3:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA10_RESERVED0 7:4 +#define NVC67D_HEAD_SET_DSC_PPS_DATA10_RC_QUANT_INCR_LIMIT0 12:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA10_RESERVED1 15:13 +#define NVC67D_HEAD_SET_DSC_PPS_DATA10_RC_QUANT_INCR_LIMIT1 20:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA10_RESERVED2 23:21 +#define NVC67D_HEAD_SET_DSC_PPS_DATA10_RC_TGT_OFFSET_LO 27:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA10_RC_TGT_OFFSET_HI 31:28 +#define NVC67D_HEAD_SET_DSC_PPS_DATA11(a) (0x0000230C + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH0 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH1 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH2 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH3 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA12(a) (0x00002310 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH4 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH5 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH6 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH7 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA13(a) (0x00002314 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH8 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH9 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH10 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH11 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA14(a) (0x00002318 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA14_RC_BUF_THRESH12 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA14_RC_BUF_THRESH13 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MAX_QP_HIGH0 18:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MIN_QP0 23:19 +#define NVC67D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_BPG_OFFSET0 29:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MAX_QP_LOW0 31:30 +#define NVC67D_HEAD_SET_DSC_PPS_DATA15(a) (0x0000231C + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_HIGH1 2:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MIN_QP1 7:3 +#define NVC67D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_BPG_OFFSET1 13:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_LOW1 15:14 +#define NVC67D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_HIGH2 18:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MIN_QP2 23:19 +#define NVC67D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_BPG_OFFSET2 29:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_LOW2 31:30 +#define NVC67D_HEAD_SET_DSC_PPS_DATA16(a) (0x00002320 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_HIGH3 2:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MIN_QP3 7:3 +#define NVC67D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_BPG_OFFSET3 13:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_LOW3 15:14 +#define NVC67D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_HIGH4 18:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MIN_QP4 23:19 +#define NVC67D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_BPG_OFFSET4 29:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_LOW4 31:30 +#define NVC67D_HEAD_SET_DSC_PPS_DATA17(a) (0x00002324 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_HIGH5 2:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MIN_QP5 7:3 +#define NVC67D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_BPG_OFFSET5 13:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_LOW5 15:14 +#define NVC67D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_HIGH6 18:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MIN_QP6 23:19 +#define NVC67D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_BPG_OFFSET6 29:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_LOW6 31:30 +#define NVC67D_HEAD_SET_DSC_PPS_DATA18(a) (0x00002328 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_HIGH7 2:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MIN_QP7 7:3 +#define NVC67D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_BPG_OFFSET7 13:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_LOW7 15:14 +#define NVC67D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_HIGH8 18:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MIN_QP8 23:19 +#define NVC67D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_BPG_OFFSET8 29:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_LOW8 31:30 +#define NVC67D_HEAD_SET_DSC_PPS_DATA19(a) (0x0000232C + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_HIGH9 2:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MIN_QP9 7:3 +#define NVC67D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_BPG_OFFSET9 13:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_LOW9 15:14 +#define NVC67D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_HIGH10 18:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MIN_QP10 23:19 +#define NVC67D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_BPG_OFFSET10 29:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_LOW10 31:30 +#define NVC67D_HEAD_SET_DSC_PPS_DATA20(a) (0x00002330 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_HIGH11 2:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MIN_QP11 7:3 +#define NVC67D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_BPG_OFFSET11 13:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_LOW11 15:14 +#define NVC67D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_HIGH12 18:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MIN_QP12 23:19 +#define NVC67D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_BPG_OFFSET12 29:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_LOW12 31:30 +#define NVC67D_HEAD_SET_DSC_PPS_DATA21(a) (0x00002334 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_HIGH13 2:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MIN_QP13 7:3 +#define NVC67D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_BPG_OFFSET13 13:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_LOW13 15:14 +#define NVC67D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_HIGH14 18:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MIN_QP14 23:19 +#define NVC67D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_BPG_OFFSET14 29:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_LOW14 31:30 +#define NVC67D_HEAD_SET_DSC_PPS_DATA22(a) (0x00002338 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA22_NATIVE422 0:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA22_NATIVE420 1:1 +#define NVC67D_HEAD_SET_DSC_PPS_DATA22_RESERVED0 7:2 +#define NVC67D_HEAD_SET_DSC_PPS_DATA22_SECOND_LINE_BPG_OFFSET 12:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA22_RESERVED1 15:13 +#define NVC67D_HEAD_SET_DSC_PPS_DATA22_NSL_BPG_OFFSET_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA22_NSL_BPG_OFFSETLOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA23(a) (0x0000233C + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA23_SECOND_LINE_OFFSET_ADJ_HIGH 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA23_SECOND_LINE_OFFSET_ADJ_LOW 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA23_RESERVED 31:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA24(a) (0x00002340 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA24_RESERVED 31:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA25(a) (0x00002344 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA25_RESERVED 31:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA26(a) (0x00002348 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA26_RESERVED 31:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA27(a) (0x0000234C + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA27_RESERVED 31:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA28(a) (0x00002350 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA28_RESERVED 31:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA29(a) (0x00002354 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA29_RESERVED 31:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA30(a) (0x00002358 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA30_RESERVED 31:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA31(a) (0x0000235C + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA31_RESERVED 31:0 +#define NVC67D_HEAD_SET_RG_MERGE(a) (0x00002360 + (a)*0x00000400) +#define NVC67D_HEAD_SET_RG_MERGE_MODE 1:0 +#define NVC67D_HEAD_SET_RG_MERGE_MODE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_RG_MERGE_MODE_SETUP (0x00000001) +#define NVC67D_HEAD_SET_RG_MERGE_MODE_MASTER (0x00000002) +#define NVC67D_HEAD_SET_RG_MERGE_MODE_SLAVE (0x00000003) +#define NVC67D_HEAD_SET_RASTER_HBLANK_DELAY(a) (0x00002364 + (a)*0x00000400) +#define NVC67D_HEAD_SET_RASTER_HBLANK_DELAY_BLANK_START 15:0 +#define NVC67D_HEAD_SET_RASTER_HBLANK_DELAY_BLANK_END 31:16 +#define NVC67D_HEAD_SET_HDMI_DSC_HCACTIVE(a) (0x00002368 + (a)*0x00000400) +#define NVC67D_HEAD_SET_HDMI_DSC_HCACTIVE_BYTES 15:0 +#define NVC67D_HEAD_SET_HDMI_DSC_HCACTIVE_TRI_BYTES 31:16 +#define NVC67D_HEAD_SET_HDMI_DSC_HCBLANK(a) (0x0000236C + (a)*0x00000400) +#define NVC67D_HEAD_SET_HDMI_DSC_HCBLANK_WIDTH 15:0 +#define NVC67D_HEAD_SW_RESERVED(a,b) (0x00002370 + (a)*0x00000400 + (b)*0x00000004) +#define NVC67D_HEAD_SW_RESERVED_VALUE 31:0 +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_HI(a,b) (0x00002380 + (a)*0x00000400 + (b)*0x00000004) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_HI_VALUE 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC67d_h diff --git a/userspace/sdks/nv570/inc/class/clc67e.h b/userspace/sdks/nv570/inc/class/clc67e.h new file mode 100644 index 0000000..871e8cd --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc67e.h @@ -0,0 +1,698 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clC67e_h_ +#define _clC67e_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC67E_WINDOW_CHANNEL_DMA (0x0000C67E) + +// dma opcode instructions +#define NVC67E_DMA +#define NVC67E_DMA_OPCODE 31:29 +#define NVC67E_DMA_OPCODE_METHOD 0x00000000 +#define NVC67E_DMA_OPCODE_JUMP 0x00000001 +#define NVC67E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC67E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC67E_DMA_METHOD_COUNT 27:18 +#define NVC67E_DMA_METHOD_OFFSET 13:2 +#define NVC67E_DMA_DATA 31:0 +#define NVC67E_DMA_DATA_NOP 0x00000000 +#define NVC67E_DMA_JUMP_OFFSET 11:2 +#define NVC67E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVC67E_PUT (0x00000000) +#define NVC67E_PUT_PTR 9:0 +#define NVC67E_GET (0x00000004) +#define NVC67E_GET_PTR 9:0 +#define NVC67E_UPDATE (0x00000200) +#define NVC67E_UPDATE_RELEASE_ELV 0:0 +#define NVC67E_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC67E_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC67E_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC67E_UPDATE_INTERLOCK_WITH_WIN_IMM 12:12 +#define NVC67E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE (0x00000000) +#define NVC67E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE (0x00000001) +#define NVC67E_SET_SEMAPHORE_ACQUIRE_HI (0x00000204) +#define NVC67E_SET_SEMAPHORE_ACQUIRE_HI_VALUE 31:0 +#define NVC67E_GET_LINE (0x00000208) +#define NVC67E_GET_LINE_LINE 15:0 +#define NVC67E_SET_SEMAPHORE_CONTROL (0x0000020C) +#define NVC67E_SET_SEMAPHORE_CONTROL_OFFSET 7:0 +#define NVC67E_SET_SEMAPHORE_CONTROL_SKIP_ACQ 11:11 +#define NVC67E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_FALSE (0x00000000) +#define NVC67E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_TRUE (0x00000001) +#define NVC67E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVC67E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVC67E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVC67E_SET_SEMAPHORE_CONTROL_ACQ_MODE 13:12 +#define NVC67E_SET_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000) +#define NVC67E_SET_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001) +#define NVC67E_SET_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002) +#define NVC67E_SET_SEMAPHORE_CONTROL_REL_MODE 14:14 +#define NVC67E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE (0x00000000) +#define NVC67E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC67E_SET_SEMAPHORE_ACQUIRE (0x00000210) +#define NVC67E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NVC67E_SET_SEMAPHORE_RELEASE (0x00000214) +#define NVC67E_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NVC67E_SET_CONTEXT_DMA_SEMAPHORE (0x00000218) +#define NVC67E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NVC67E_SET_CONTEXT_DMA_NOTIFIER (0x0000021C) +#define NVC67E_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NVC67E_SET_NOTIFIER_CONTROL (0x00000220) +#define NVC67E_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC67E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC67E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC67E_SET_NOTIFIER_CONTROL_OFFSET 11:4 +#define NVC67E_SET_SIZE (0x00000224) +#define NVC67E_SET_SIZE_WIDTH 15:0 +#define NVC67E_SET_SIZE_HEIGHT 31:16 +#define NVC67E_SET_STORAGE (0x00000228) +#define NVC67E_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NVC67E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NVC67E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NVC67E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC67E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC67E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC67E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC67E_SET_PARAMS (0x0000022C) +#define NVC67E_SET_PARAMS_FORMAT 7:0 +#define NVC67E_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NVC67E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F) +#define NVC67E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NVC67E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC67E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E) +#define NVC67E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC67E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6) +#define NVC67E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NVC67E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9) +#define NVC67E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NVC67E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NVC67E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NVC67E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NVC67E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NVC67E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028) +#define NVC67E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029) +#define NVC67E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035) +#define NVC67E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036) +#define NVC67E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038) +#define NVC67E_SET_PARAMS_FORMAT_Y8___U8___V8_N444 (0x0000003A) +#define NVC67E_SET_PARAMS_FORMAT_Y8___U8___V8_N420 (0x0000003B) +#define NVC67E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055) +#define NVC67E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056) +#define NVC67E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058) +#define NVC67E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075) +#define NVC67E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076) +#define NVC67E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078) +#define NVC67E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18 +#define NVC67E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000) +#define NVC67E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001) +#define NVC67E_SET_PARAMS_SWAP_UV 19:19 +#define NVC67E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000) +#define NVC67E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001) +#define NVC67E_SET_PARAMS_FMT_ROUNDING_MODE 22:22 +#define NVC67E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_TO_NEAREST (0x00000000) +#define NVC67E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_DOWN (0x00000001) +#define NVC67E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004) +#define NVC67E_SET_PLANAR_STORAGE_PITCH 12:0 +#define NVC67E_SET_SEMAPHORE_RELEASE_HI (0x0000023C) +#define NVC67E_SET_SEMAPHORE_RELEASE_HI_VALUE 31:0 +#define NVC67E_SET_CONTEXT_DMA_ISO(b) (0x00000240 + (b)*0x00000004) +#define NVC67E_SET_CONTEXT_DMA_ISO_HANDLE 31:0 +#define NVC67E_SET_OFFSET(b) (0x00000260 + (b)*0x00000004) +#define NVC67E_SET_OFFSET_ORIGIN 31:0 +#define NVC67E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004) +#define NVC67E_SET_POINT_IN_X 15:0 +#define NVC67E_SET_POINT_IN_Y 31:16 +#define NVC67E_SET_SIZE_IN (0x00000298) +#define NVC67E_SET_SIZE_IN_WIDTH 15:0 +#define NVC67E_SET_SIZE_IN_HEIGHT 31:16 +#define NVC67E_SET_SIZE_OUT (0x000002A4) +#define NVC67E_SET_SIZE_OUT_WIDTH 15:0 +#define NVC67E_SET_SIZE_OUT_HEIGHT 31:16 +#define NVC67E_SET_CONTROL_INPUT_SCALER (0x000002A8) +#define NVC67E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVC67E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVC67E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVC67E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVC67E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVC67E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVC67E_SET_INPUT_SCALER_COEFF_VALUE (0x000002AC) +#define NVC67E_SET_INPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVC67E_SET_INPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVC67E_SET_COMPOSITION_CONTROL (0x000002EC) +#define NVC67E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0 +#define NVC67E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000) +#define NVC67E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001) +#define NVC67E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002) +#define NVC67E_SET_COMPOSITION_CONTROL_DEPTH 11:4 +#define NVC67E_SET_COMPOSITION_CONTROL_BYPASS 16:16 +#define NVC67E_SET_COMPOSITION_CONTROL_BYPASS_DISABLE (0x00000000) +#define NVC67E_SET_COMPOSITION_CONTROL_BYPASS_ENABLE (0x00000001) +#define NVC67E_SET_COMPOSITION_CONSTANT_ALPHA (0x000002F0) +#define NVC67E_SET_COMPOSITION_CONSTANT_ALPHA_K1 7:0 +#define NVC67E_SET_COMPOSITION_CONSTANT_ALPHA_K2 15:8 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT (0x000002F4) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC67E_SET_KEY_ALPHA (0x000002F8) +#define NVC67E_SET_KEY_ALPHA_MIN 15:0 +#define NVC67E_SET_KEY_ALPHA_MAX 31:16 +#define NVC67E_SET_KEY_RED_CR (0x000002FC) +#define NVC67E_SET_KEY_RED_CR_MIN 15:0 +#define NVC67E_SET_KEY_RED_CR_MAX 31:16 +#define NVC67E_SET_KEY_GREEN_Y (0x00000300) +#define NVC67E_SET_KEY_GREEN_Y_MIN 15:0 +#define NVC67E_SET_KEY_GREEN_Y_MAX 31:16 +#define NVC67E_SET_KEY_BLUE_CB (0x00000304) +#define NVC67E_SET_KEY_BLUE_CB_MIN 15:0 +#define NVC67E_SET_KEY_BLUE_CB_MAX 31:16 +#define NVC67E_SET_PRESENT_CONTROL (0x00000308) +#define NVC67E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NVC67E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4 +#define NVC67E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NVC67E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NVC67E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8 +#define NVC67E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000) +#define NVC67E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001) +#define NVC67E_SET_PRESENT_CONTROL_STEREO_MODE 13:12 +#define NVC67E_SET_PRESENT_CONTROL_STEREO_MODE_MONO (0x00000000) +#define NVC67E_SET_PRESENT_CONTROL_STEREO_MODE_PAIR_FLIP (0x00000001) +#define NVC67E_SET_PRESENT_CONTROL_STEREO_MODE_AT_ANY_FRAME (0x00000002) +#define NVC67E_SET_ACQ_SEMAPHORE_VALUE_HI (0x0000030C) +#define NVC67E_SET_ACQ_SEMAPHORE_VALUE_HI_VALUE 31:0 +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL (0x00000330) +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL_OFFSET 7:0 +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE 13:12 +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000) +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001) +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002) +#define NVC67E_SET_ACQ_SEMAPHORE_VALUE (0x00000334) +#define NVC67E_SET_ACQ_SEMAPHORE_VALUE_VALUE 31:0 +#define NVC67E_SET_CONTEXT_DMA_ACQ_SEMAPHORE (0x00000338) +#define NVC67E_SET_CONTEXT_DMA_ACQ_SEMAPHORE_HANDLE 31:0 +#define NVC67E_SET_SCAN_DIRECTION (0x0000033C) +#define NVC67E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION 0:0 +#define NVC67E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_LEFT (0x00000000) +#define NVC67E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_RIGHT (0x00000001) +#define NVC67E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION 1:1 +#define NVC67E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_TOP (0x00000000) +#define NVC67E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_BOTTOM (0x00000001) +#define NVC67E_SET_SCAN_DIRECTION_COLUMN_ORDER 2:2 +#define NVC67E_SET_SCAN_DIRECTION_COLUMN_ORDER_FALSE (0x00000000) +#define NVC67E_SET_SCAN_DIRECTION_COLUMN_ORDER_TRUE (0x00000001) +#define NVC67E_SET_TIMESTAMP_ORIGIN_LO (0x00000340) +#define NVC67E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NVC67E_SET_TIMESTAMP_ORIGIN_HI (0x00000344) +#define NVC67E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NVC67E_SET_UPDATE_TIMESTAMP_LO (0x00000348) +#define NVC67E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NVC67E_SET_UPDATE_TIMESTAMP_HI (0x0000034C) +#define NVC67E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NVC67E_SET_INTERLOCK_FLAGS (0x00000370) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 0:0 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+1):((i)+1) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 1:1 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 2:2 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 3:3 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 4:4 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 5:5 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 6:6 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 7:7 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 8:8 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS (0x00000374) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVC67E_SET_EXT_PACKET_CONTROL (0x00000398) +#define NVC67E_SET_EXT_PACKET_CONTROL_ENABLE 0:0 +#define NVC67E_SET_EXT_PACKET_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67E_SET_EXT_PACKET_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67E_SET_EXT_PACKET_CONTROL_LOCATION 4:4 +#define NVC67E_SET_EXT_PACKET_CONTROL_LOCATION_VSYNC (0x00000000) +#define NVC67E_SET_EXT_PACKET_CONTROL_LOCATION_VBLANK (0x00000001) +#define NVC67E_SET_EXT_PACKET_CONTROL_FREQUENCY 8:8 +#define NVC67E_SET_EXT_PACKET_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVC67E_SET_EXT_PACKET_CONTROL_FREQUENCY_ONCE (0x00000001) +#define NVC67E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE 12:12 +#define NVC67E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_DISABLE (0x00000000) +#define NVC67E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_ENABLE (0x00000001) +#define NVC67E_SET_EXT_PACKET_CONTROL_SIZE 27:16 +#define NVC67E_SET_EXT_PACKET_DATA (0x0000039C) +#define NVC67E_SET_EXT_PACKET_DATA_DB0 7:0 +#define NVC67E_SET_EXT_PACKET_DATA_DB1 15:8 +#define NVC67E_SET_EXT_PACKET_DATA_DB2 23:16 +#define NVC67E_SET_EXT_PACKET_DATA_DB3 31:24 +#define NVC67E_SET_FMT_COEFFICIENT_C00 (0x00000400) +#define NVC67E_SET_FMT_COEFFICIENT_C00_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C01 (0x00000404) +#define NVC67E_SET_FMT_COEFFICIENT_C01_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C02 (0x00000408) +#define NVC67E_SET_FMT_COEFFICIENT_C02_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C03 (0x0000040C) +#define NVC67E_SET_FMT_COEFFICIENT_C03_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C10 (0x00000410) +#define NVC67E_SET_FMT_COEFFICIENT_C10_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C11 (0x00000414) +#define NVC67E_SET_FMT_COEFFICIENT_C11_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C12 (0x00000418) +#define NVC67E_SET_FMT_COEFFICIENT_C12_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C13 (0x0000041C) +#define NVC67E_SET_FMT_COEFFICIENT_C13_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C20 (0x00000420) +#define NVC67E_SET_FMT_COEFFICIENT_C20_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C21 (0x00000424) +#define NVC67E_SET_FMT_COEFFICIENT_C21_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C22 (0x00000428) +#define NVC67E_SET_FMT_COEFFICIENT_C22_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C23 (0x0000042C) +#define NVC67E_SET_FMT_COEFFICIENT_C23_VALUE 20:0 +#define NVC67E_SET_ILUT_CONTROL (0x00000440) +#define NVC67E_SET_ILUT_CONTROL_INTERPOLATE 0:0 +#define NVC67E_SET_ILUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC67E_SET_ILUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC67E_SET_ILUT_CONTROL_MIRROR 1:1 +#define NVC67E_SET_ILUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC67E_SET_ILUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC67E_SET_ILUT_CONTROL_MODE 3:2 +#define NVC67E_SET_ILUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVC67E_SET_ILUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVC67E_SET_ILUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVC67E_SET_ILUT_CONTROL_SIZE 18:8 +#define NVC67E_SET_CONTEXT_DMA_ILUT (0x00000444) +#define NVC67E_SET_CONTEXT_DMA_ILUT_HANDLE 31:0 +#define NVC67E_SET_OFFSET_ILUT (0x00000448) +#define NVC67E_SET_OFFSET_ILUT_ORIGIN 31:0 +#define NVC67E_SET_CSC00CONTROL (0x0000045C) +#define NVC67E_SET_CSC00CONTROL_ENABLE 0:0 +#define NVC67E_SET_CSC00CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67E_SET_CSC00CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67E_SET_CSC00COEFFICIENT_C00 (0x00000460) +#define NVC67E_SET_CSC00COEFFICIENT_C00_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C01 (0x00000464) +#define NVC67E_SET_CSC00COEFFICIENT_C01_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C02 (0x00000468) +#define NVC67E_SET_CSC00COEFFICIENT_C02_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C03 (0x0000046C) +#define NVC67E_SET_CSC00COEFFICIENT_C03_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C10 (0x00000470) +#define NVC67E_SET_CSC00COEFFICIENT_C10_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C11 (0x00000474) +#define NVC67E_SET_CSC00COEFFICIENT_C11_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C12 (0x00000478) +#define NVC67E_SET_CSC00COEFFICIENT_C12_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C13 (0x0000047C) +#define NVC67E_SET_CSC00COEFFICIENT_C13_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C20 (0x00000480) +#define NVC67E_SET_CSC00COEFFICIENT_C20_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C21 (0x00000484) +#define NVC67E_SET_CSC00COEFFICIENT_C21_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C22 (0x00000488) +#define NVC67E_SET_CSC00COEFFICIENT_C22_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C23 (0x0000048C) +#define NVC67E_SET_CSC00COEFFICIENT_C23_VALUE 20:0 +#define NVC67E_SET_CSC0LUT_CONTROL (0x000004A0) +#define NVC67E_SET_CSC0LUT_CONTROL_INTERPOLATE 0:0 +#define NVC67E_SET_CSC0LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC67E_SET_CSC0LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC67E_SET_CSC0LUT_CONTROL_MIRROR 1:1 +#define NVC67E_SET_CSC0LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC67E_SET_CSC0LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC67E_SET_CSC0LUT_CONTROL_ENABLE 4:4 +#define NVC67E_SET_CSC0LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67E_SET_CSC0LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67E_SET_CSC0LUT_SEGMENT_SIZE (0x000004A4) +#define NVC67E_SET_CSC0LUT_SEGMENT_SIZE_IDX 5:0 +#define NVC67E_SET_CSC0LUT_SEGMENT_SIZE_VALUE 18:16 +#define NVC67E_SET_CSC0LUT_ENTRY (0x000004A8) +#define NVC67E_SET_CSC0LUT_ENTRY_IDX 10:0 +#define NVC67E_SET_CSC0LUT_ENTRY_VALUE 31:16 +#define NVC67E_SET_CSC01CONTROL (0x000004BC) +#define NVC67E_SET_CSC01CONTROL_ENABLE 0:0 +#define NVC67E_SET_CSC01CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67E_SET_CSC01CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67E_SET_CSC01COEFFICIENT_C00 (0x000004C0) +#define NVC67E_SET_CSC01COEFFICIENT_C00_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C01 (0x000004C4) +#define NVC67E_SET_CSC01COEFFICIENT_C01_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C02 (0x000004C8) +#define NVC67E_SET_CSC01COEFFICIENT_C02_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C03 (0x000004CC) +#define NVC67E_SET_CSC01COEFFICIENT_C03_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C10 (0x000004D0) +#define NVC67E_SET_CSC01COEFFICIENT_C10_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C11 (0x000004D4) +#define NVC67E_SET_CSC01COEFFICIENT_C11_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C12 (0x000004D8) +#define NVC67E_SET_CSC01COEFFICIENT_C12_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C13 (0x000004DC) +#define NVC67E_SET_CSC01COEFFICIENT_C13_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C20 (0x000004E0) +#define NVC67E_SET_CSC01COEFFICIENT_C20_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C21 (0x000004E4) +#define NVC67E_SET_CSC01COEFFICIENT_C21_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C22 (0x000004E8) +#define NVC67E_SET_CSC01COEFFICIENT_C22_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C23 (0x000004EC) +#define NVC67E_SET_CSC01COEFFICIENT_C23_VALUE 20:0 +#define NVC67E_SET_TMO_CONTROL (0x00000500) +#define NVC67E_SET_TMO_CONTROL_INTERPOLATE 0:0 +#define NVC67E_SET_TMO_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC67E_SET_TMO_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC67E_SET_TMO_CONTROL_SAT_MODE 3:2 +#define NVC67E_SET_TMO_CONTROL_SIZE 18:8 +#define NVC67E_SET_TMO_LOW_INTENSITY_ZONE (0x00000508) +#define NVC67E_SET_TMO_LOW_INTENSITY_ZONE_END 29:16 +#define NVC67E_SET_TMO_LOW_INTENSITY_VALUE (0x0000050C) +#define NVC67E_SET_TMO_LOW_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVC67E_SET_TMO_LOW_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVC67E_SET_TMO_LOW_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVC67E_SET_TMO_MEDIUM_INTENSITY_ZONE (0x00000510) +#define NVC67E_SET_TMO_MEDIUM_INTENSITY_ZONE_START 13:0 +#define NVC67E_SET_TMO_MEDIUM_INTENSITY_ZONE_END 29:16 +#define NVC67E_SET_TMO_MEDIUM_INTENSITY_VALUE (0x00000514) +#define NVC67E_SET_TMO_MEDIUM_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVC67E_SET_TMO_MEDIUM_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVC67E_SET_TMO_MEDIUM_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVC67E_SET_TMO_HIGH_INTENSITY_ZONE (0x00000518) +#define NVC67E_SET_TMO_HIGH_INTENSITY_ZONE_START 13:0 +#define NVC67E_SET_TMO_HIGH_INTENSITY_VALUE (0x0000051C) +#define NVC67E_SET_TMO_HIGH_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVC67E_SET_TMO_HIGH_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVC67E_SET_TMO_HIGH_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVC67E_SET_CONTEXT_DMA_TMO_LUT (0x00000528) +#define NVC67E_SET_CONTEXT_DMA_TMO_LUT_HANDLE 31:0 +#define NVC67E_SET_OFFSET_TMO_LUT (0x0000052C) +#define NVC67E_SET_OFFSET_TMO_LUT_ORIGIN 31:0 +#define NVC67E_SET_CSC10CONTROL (0x0000053C) +#define NVC67E_SET_CSC10CONTROL_ENABLE 0:0 +#define NVC67E_SET_CSC10CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67E_SET_CSC10CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67E_SET_CSC10COEFFICIENT_C00 (0x00000540) +#define NVC67E_SET_CSC10COEFFICIENT_C00_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C01 (0x00000544) +#define NVC67E_SET_CSC10COEFFICIENT_C01_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C02 (0x00000548) +#define NVC67E_SET_CSC10COEFFICIENT_C02_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C03 (0x0000054C) +#define NVC67E_SET_CSC10COEFFICIENT_C03_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C10 (0x00000550) +#define NVC67E_SET_CSC10COEFFICIENT_C10_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C11 (0x00000554) +#define NVC67E_SET_CSC10COEFFICIENT_C11_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C12 (0x00000558) +#define NVC67E_SET_CSC10COEFFICIENT_C12_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C13 (0x0000055C) +#define NVC67E_SET_CSC10COEFFICIENT_C13_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C20 (0x00000560) +#define NVC67E_SET_CSC10COEFFICIENT_C20_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C21 (0x00000564) +#define NVC67E_SET_CSC10COEFFICIENT_C21_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C22 (0x00000568) +#define NVC67E_SET_CSC10COEFFICIENT_C22_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C23 (0x0000056C) +#define NVC67E_SET_CSC10COEFFICIENT_C23_VALUE 20:0 +#define NVC67E_SET_CSC1LUT_CONTROL (0x00000580) +#define NVC67E_SET_CSC1LUT_CONTROL_INTERPOLATE 0:0 +#define NVC67E_SET_CSC1LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC67E_SET_CSC1LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC67E_SET_CSC1LUT_CONTROL_MIRROR 1:1 +#define NVC67E_SET_CSC1LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC67E_SET_CSC1LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC67E_SET_CSC1LUT_CONTROL_ENABLE 4:4 +#define NVC67E_SET_CSC1LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67E_SET_CSC1LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67E_SET_CSC1LUT_SEGMENT_SIZE (0x00000584) +#define NVC67E_SET_CSC1LUT_SEGMENT_SIZE_IDX 5:0 +#define NVC67E_SET_CSC1LUT_SEGMENT_SIZE_VALUE 18:16 +#define NVC67E_SET_CSC1LUT_ENTRY (0x00000588) +#define NVC67E_SET_CSC1LUT_ENTRY_IDX 10:0 +#define NVC67E_SET_CSC1LUT_ENTRY_VALUE 31:16 +#define NVC67E_SET_CSC11CONTROL (0x0000059C) +#define NVC67E_SET_CSC11CONTROL_ENABLE 0:0 +#define NVC67E_SET_CSC11CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67E_SET_CSC11CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67E_SET_CSC11COEFFICIENT_C00 (0x000005A0) +#define NVC67E_SET_CSC11COEFFICIENT_C00_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C01 (0x000005A4) +#define NVC67E_SET_CSC11COEFFICIENT_C01_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C02 (0x000005A8) +#define NVC67E_SET_CSC11COEFFICIENT_C02_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C03 (0x000005AC) +#define NVC67E_SET_CSC11COEFFICIENT_C03_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C10 (0x000005B0) +#define NVC67E_SET_CSC11COEFFICIENT_C10_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C11 (0x000005B4) +#define NVC67E_SET_CSC11COEFFICIENT_C11_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C12 (0x000005B8) +#define NVC67E_SET_CSC11COEFFICIENT_C12_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C13 (0x000005BC) +#define NVC67E_SET_CSC11COEFFICIENT_C13_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C20 (0x000005C0) +#define NVC67E_SET_CSC11COEFFICIENT_C20_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C21 (0x000005C4) +#define NVC67E_SET_CSC11COEFFICIENT_C21_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C22 (0x000005C8) +#define NVC67E_SET_CSC11COEFFICIENT_C22_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C23 (0x000005CC) +#define NVC67E_SET_CSC11COEFFICIENT_C23_VALUE 20:0 +#define NVC67E_SET_CLAMP_RANGE (0x000005D0) +#define NVC67E_SET_CLAMP_RANGE_LOW 15:0 +#define NVC67E_SET_CLAMP_RANGE_HIGH 31:16 +#define NVC67E_SW_RESERVED(b) (0x000005D4 + (b)*0x00000004) +#define NVC67E_SW_RESERVED_VALUE 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC67e_h diff --git a/userspace/sdks/nv570/inc/class/clc697.h b/userspace/sdks/nv570/inc/class/clc697.h new file mode 100644 index 0000000..a8b447e --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc697.h @@ -0,0 +1,4352 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_ampere_a_h_ +#define _cl_ampere_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl ampere_a */ + +#include "nvtypes.h" + +#define AMPERE_A 0xC697 + +#define NVC697_SET_OBJECT 0x0000 +#define NVC697_SET_OBJECT_CLASS_ID 15:0 +#define NVC697_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC697_NO_OPERATION 0x0100 +#define NVC697_NO_OPERATION_V 31:0 + +#define NVC697_SET_NOTIFY_A 0x0104 +#define NVC697_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC697_SET_NOTIFY_B 0x0108 +#define NVC697_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC697_NOTIFY 0x010c +#define NVC697_NOTIFY_TYPE 31:0 +#define NVC697_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC697_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC697_WAIT_FOR_IDLE 0x0110 +#define NVC697_WAIT_FOR_IDLE_V 31:0 + +#define NVC697_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC697_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC697_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC697_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC697_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC697_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC697_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC697_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC697_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC697_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC697_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC697_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC697_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC697_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC697_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC697_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC697_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC697_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC697_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC697_SEND_GO_IDLE 0x013c +#define NVC697_SEND_GO_IDLE_V 31:0 + +#define NVC697_PM_TRIGGER 0x0140 +#define NVC697_PM_TRIGGER_V 31:0 + +#define NVC697_PM_TRIGGER_WFI 0x0144 +#define NVC697_PM_TRIGGER_WFI_V 31:0 + +#define NVC697_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC697_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC697_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC697_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC697_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC697_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC697_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC697_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC697_LINE_LENGTH_IN 0x0180 +#define NVC697_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC697_LINE_COUNT 0x0184 +#define NVC697_LINE_COUNT_VALUE 31:0 + +#define NVC697_OFFSET_OUT_UPPER 0x0188 +#define NVC697_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC697_OFFSET_OUT 0x018c +#define NVC697_OFFSET_OUT_VALUE 31:0 + +#define NVC697_PITCH_OUT 0x0190 +#define NVC697_PITCH_OUT_VALUE 31:0 + +#define NVC697_SET_DST_BLOCK_SIZE 0x0194 +#define NVC697_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC697_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC697_SET_DST_WIDTH 0x0198 +#define NVC697_SET_DST_WIDTH_V 31:0 + +#define NVC697_SET_DST_HEIGHT 0x019c +#define NVC697_SET_DST_HEIGHT_V 31:0 + +#define NVC697_SET_DST_DEPTH 0x01a0 +#define NVC697_SET_DST_DEPTH_V 31:0 + +#define NVC697_SET_DST_LAYER 0x01a4 +#define NVC697_SET_DST_LAYER_V 31:0 + +#define NVC697_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC697_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC697_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC697_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC697_LAUNCH_DMA 0x01b0 +#define NVC697_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC697_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC697_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC697_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC697_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC697_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC697_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC697_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC697_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC697_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC697_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC697_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC697_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC697_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC697_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC697_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC697_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC697_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC697_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC697_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC697_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC697_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC697_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC697_LOAD_INLINE_DATA 0x01b4 +#define NVC697_LOAD_INLINE_DATA_V 31:0 + +#define NVC697_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC697_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC697_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC697_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC697_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC697_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC697_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC697_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC697_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC697_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC697_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC697_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC697_RUN_DS_NOW 0x0200 +#define NVC697_RUN_DS_NOW_V 31:0 + +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC697_SET_GS_MODE 0x0208 +#define NVC697_SET_GS_MODE_TYPE 0:0 +#define NVC697_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVC697_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVC697_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC697_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC697_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC697_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC697_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC697_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_GS_DM_FIFO 0x0214 +#define NVC697_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC697_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC697_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC697_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC697_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC697_INVALIDATE_SHADER_CACHES 0x021c +#define NVC697_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC697_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC697_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC697_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC697_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC697_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC697_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC697_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC697_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC697_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC697_SET_INSTANCE_COUNT 0x0220 +#define NVC697_SET_INSTANCE_COUNT_V 31:0 + +#define NVC697_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVC697_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVC697_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC697_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVC697_SET_MME_VERSION 0x0234 +#define NVC697_SET_MME_VERSION_MAJOR 7:0 + +#define NVC697_SET_INDEX_BUFFER_SIZE_A 0x0238 +#define NVC697_SET_INDEX_BUFFER_SIZE_A_UPPER 7:0 + +#define NVC697_SET_INDEX_BUFFER_SIZE_B 0x023c +#define NVC697_SET_INDEX_BUFFER_SIZE_B_LOWER 31:0 + +#define NVC697_SET_ROOT_TABLE_VISIBILITY(i) (0x0240+(i)*4) +#define NVC697_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP0_ENABLE 1:0 +#define NVC697_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP1_ENABLE 5:4 +#define NVC697_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP2_ENABLE 9:8 +#define NVC697_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP3_ENABLE 13:12 +#define NVC697_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP4_ENABLE 17:16 + +#define NVC697_SET_DRAW_CONTROL_A 0x0260 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY 3:0 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_POINTS 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_LINES 0x00000001 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_QUADS 0x00000007 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_PATCH 0x0000000E +#define NVC697_SET_DRAW_CONTROL_A_PRIMITIVE_ID 4:4 +#define NVC697_SET_DRAW_CONTROL_A_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ID 6:5 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ID_FIRST 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC697_SET_DRAW_CONTROL_A_SPLIT_MODE 8:7 +#define NVC697_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC697_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC697_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE 9:9 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 +#define NVC697_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX 10:10 +#define NVC697_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_FALSE 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_TRUE 0x00000001 +#define NVC697_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX 11:11 +#define NVC697_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_FALSE 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_TRUE 0x00000001 + +#define NVC697_SET_DRAW_CONTROL_B 0x0264 +#define NVC697_SET_DRAW_CONTROL_B_INSTANCE_COUNT 31:0 + +#define NVC697_DRAW_INDEX_BUFFER_BEGIN_END_A 0x0268 +#define NVC697_DRAW_INDEX_BUFFER_BEGIN_END_A_FIRST 31:0 + +#define NVC697_DRAW_INDEX_BUFFER_BEGIN_END_B 0x026c +#define NVC697_DRAW_INDEX_BUFFER_BEGIN_END_B_COUNT 31:0 + +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_A 0x0270 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_A_START 31:0 + +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_B 0x0274 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_B_COUNT 31:0 + +#define NVC697_INVALIDATE_RASTER_CACHE_NO_WFI 0x027c +#define NVC697_INVALIDATE_RASTER_CACHE_NO_WFI_V 0:0 + +#define NVC697_SET_COLOR_RENDER_TO_ZETA_SURFACE 0x02b8 +#define NVC697_SET_COLOR_RENDER_TO_ZETA_SURFACE_V 0:0 +#define NVC697_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_FALSE 0x00000000 +#define NVC697_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_TRUE 0x00000001 + +#define NVC697_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION 0x02bc +#define NVC697_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V 0:0 +#define NVC697_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_FALSE 0x00000000 +#define NVC697_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_TRUE 0x00000001 + +#define NVC697_INCREMENT_SYNC_POINT 0x02c8 +#define NVC697_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC697_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC697_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC697_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC697_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC697_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC697_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC697_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC697_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC697_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC697_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVC697_DECOMPRESS_SURFACE 0x02e0 +#define NVC697_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC697_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC697_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC697_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC697_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC697_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC697_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC697_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC697_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC697_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC697_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC697_SET_ZCULL_SUBREGION 0x02e8 +#define NVC697_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC697_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC697_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC697_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC697_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC697_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC697_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC697_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC697_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC697_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC697_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC697_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC697_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC697_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC697_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC697_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC697_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC697_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC697_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC697_DRAW_ZERO_INDEX 0x0304 +#define NVC697_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC697_SET_L1_CONFIGURATION 0x0308 +#define NVC697_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC697_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC697_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC697_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC697_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC697_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC697_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC697_SET_SPA_VERSION 0x0310 +#define NVC697_SET_SPA_VERSION_MINOR 7:0 +#define NVC697_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC697_SET_TIMESLICE_BATCH_LIMIT 0x0314 +#define NVC697_SET_TIMESLICE_BATCH_LIMIT_BATCH_LIMIT 15:0 + +#define NVC697_SET_SNAP_GRID_LINE 0x0318 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC697_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC697_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC697_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC697_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC697_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC697_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC697_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC697_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC697_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC697_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC697_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC697_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC697_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC697_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC697_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC697_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC697_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC697_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC697_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC697_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC697_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC697_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC697_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC697_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC697_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC697_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC697_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC697_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC697_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC697_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC697_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC697_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC697_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC697_RESERVED_TG07 0x033c +#define NVC697_RESERVED_TG07_V 0:0 + +#define NVC697_RESERVED_TG08 0x0340 +#define NVC697_RESERVED_TG08_V 0:0 + +#define NVC697_RESERVED_TG09 0x0344 +#define NVC697_RESERVED_TG09_V 0:0 + +#define NVC697_RESERVED_TG10 0x0348 +#define NVC697_RESERVED_TG10_V 0:0 + +#define NVC697_RESERVED_TG11 0x034c +#define NVC697_RESERVED_TG11_V 0:0 + +#define NVC697_RESERVED_TG12 0x0350 +#define NVC697_RESERVED_TG12_V 0:0 + +#define NVC697_RESERVED_TG13 0x0354 +#define NVC697_RESERVED_TG13_V 0:0 + +#define NVC697_RESERVED_TG14 0x0358 +#define NVC697_RESERVED_TG14_V 0:0 + +#define NVC697_RESERVED_TG15 0x035c +#define NVC697_RESERVED_TG15_V 0:0 + +#define NVC697_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC697_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC697_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC697_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC697_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC697_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC697_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC697_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC697_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC697_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC697_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC697_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC697_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC697_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC697_SET_RASTER_ENABLE 0x037c +#define NVC697_SET_RASTER_ENABLE_V 0:0 +#define NVC697_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC697_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC697_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC697_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC697_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC697_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC697_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC697_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC697_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC697_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC697_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVC697_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVC697_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVC697_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVC697_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVC697_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVC697_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVC697_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVC697_SET_ROOT_TABLE_SELECTOR 0x0504 +#define NVC697_SET_ROOT_TABLE_SELECTOR_ROOT_TABLE 2:0 +#define NVC697_SET_ROOT_TABLE_SELECTOR_OFFSET 15:8 + +#define NVC697_LOAD_ROOT_TABLE 0x0508 +#define NVC697_LOAD_ROOT_TABLE_V 31:0 + +#define NVC697_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVC697_SET_MME_MEM_ADDRESS_A_UPPER 7:0 + +#define NVC697_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVC697_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVC697_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVC697_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVC697_MME_DMA_READ 0x055c +#define NVC697_MME_DMA_READ_LENGTH 31:0 + +#define NVC697_MME_DMA_READ_FIFOED 0x0560 +#define NVC697_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVC697_MME_DMA_WRITE 0x0564 +#define NVC697_MME_DMA_WRITE_LENGTH 31:0 + +#define NVC697_MME_DMA_REDUCTION 0x0568 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVC697_MME_DMA_SYSMEMBAR 0x056c +#define NVC697_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVC697_MME_DMA_SYNC 0x0570 +#define NVC697_MME_DMA_SYNC_VALUE 31:0 + +#define NVC697_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NVC697_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NVC697_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NVC697_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NVC697_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NVC697_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NVC697_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NVC697_SET_VERTEX_STREAM_SIZE_A(j) (0x0600+(j)*8) +#define NVC697_SET_VERTEX_STREAM_SIZE_A_UPPER 7:0 + +#define NVC697_SET_VERTEX_STREAM_SIZE_B(j) (0x0604+(j)*8) +#define NVC697_SET_VERTEX_STREAM_SIZE_B_LOWER 31:0 + +#define NVC697_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC697_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC697_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC697_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC697_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC697_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC697_SET_RASTER_INPUT 0x0740 +#define NVC697_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC697_SET_STREAM_OUTPUT 0x0744 +#define NVC697_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC697_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC697_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC697_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC697_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC697_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC697_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC697_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC697_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC697_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC697_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC697_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC697_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC697_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC697_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC697_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC697_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC697_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC697_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC697_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC697_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC697_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC697_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC697_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC697_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC697_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVC697_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC697_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC697_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC697_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC697_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC697_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC697_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC697_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC697_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC697_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC697_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC697_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC697_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC697_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC697_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC697_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC697_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC697_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC697_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC697_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC697_SET_ZCULL_STORAGE_B 0x07ec +#define NVC697_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC697_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC697_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC697_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC697_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC697_SET_ZT_READ_ONLY 0x07f8 +#define NVC697_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC697_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC697_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC697_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC697_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC697_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC697_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC697_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC697_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC697_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC697_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC697_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC697_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC697_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC697_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC697_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC697_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC697_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC697_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC697_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC697_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC697_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC697_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC697_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC697_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC697_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC697_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC697_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC697_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC697_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC697_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC697_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC697_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC697_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC697_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC697_SET_COLOR_TARGET_RESERVED_A(j) (0x0824+(j)*64) +#define NVC697_SET_COLOR_TARGET_RESERVED_A_V 0:0 + +#define NVC697_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC697_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC697_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC697_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC697_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC697_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC697_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC697_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC697_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC697_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC697_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC697_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC697_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC697_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC697_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC697_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC697_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC697_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC697_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC697_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC697_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC697_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC697_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC697_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC697_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC697_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC697_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC697_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC697_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC697_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC697_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC697_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC697_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC697_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC697_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC697_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC697_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC697_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC697_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC697_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC697_SET_STATISTICS_COUNTER 0x0d68 +#define NVC697_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC697_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC697_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC697_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC697_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC697_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC697_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC697_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC697_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC697_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC697_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC697_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC697_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC697_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC697_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC697_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC697_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVC697_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC697_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC697_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC697_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC697_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC697_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC697_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC697_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC697_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC697_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC697_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC697_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC697_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC697_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC697_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC697_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC697_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC697_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC697_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC697_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC697_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC697_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC697_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC697_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC697_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC697_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC697_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC697_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC697_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC697_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC697_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC697_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC697_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC697_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC697_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC697_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC697_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC697_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC697_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC697_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC697_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC697_SET_POLY_SMOOTH 0x0db4 +#define NVC697_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC697_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC697_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC697_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC697_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC697_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC697_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC697_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC697_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC697_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_PATCH 0x0dcc +#define NVC697_SET_PATCH_SIZE 7:0 + +#define NVC697_SET_ITERATED_BLEND 0x0dd0 +#define NVC697_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC697_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC697_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC697_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC697_SET_ZCULL_CRITERION 0x0dd8 +#define NVC697_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC697_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC697_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC697_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC697_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC697_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC697_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC697_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC697_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC697_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC697_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC697_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC697_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC697_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC697_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC697_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC697_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC697_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC697_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC697_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC697_SET_SCISSOR_ENABLE_V 0:0 +#define NVC697_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC697_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC697_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC697_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC697_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC697_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC697_SET_VPC_PERF_KNOB 0x0f14 +#define NVC697_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC697_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC697_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC697_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC697_PM_LOCAL_TRIGGER 0x0f18 +#define NVC697_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC697_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC697_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC697_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC697_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC697_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC697_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC697_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC697_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC697_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC697_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC697_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC697_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC697_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC697_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC697_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC697_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC697_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC697_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC697_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC697_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC697_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC697_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC697_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC697_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC697_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC697_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC697_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC697_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC697_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC697_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC697_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC697_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC697_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC697_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC697_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC697_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC697_SET_SAMPLE_MASK 0x0fa4 +#define NVC697_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC697_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC697_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC697_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC697_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC697_SET_CT_MRT_ENABLE 0x0fac +#define NVC697_SET_CT_MRT_ENABLE_V 0:0 +#define NVC697_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC697_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC697_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC697_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC697_SET_TIR 0x0fb4 +#define NVC697_SET_TIR_MODE 1:0 +#define NVC697_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC697_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC697_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC697_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC697_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC697_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC697_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC697_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC697_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC697_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC697_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC697_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC697_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC697_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC697_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC697_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC697_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC697_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC697_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC697_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_TIR_MODULATION 0x0fd4 +#define NVC697_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC697_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC697_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC697_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC697_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC697_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC697_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC697_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC697_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC697_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC697_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC697_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC697_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC697_SET_ZT_A 0x0fe0 +#define NVC697_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_ZT_B 0x0fe4 +#define NVC697_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_ZT_FORMAT 0x0fe8 +#define NVC697_SET_ZT_FORMAT_V 4:0 +#define NVC697_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC697_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC697_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC697_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC697_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC697_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC697_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC697_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC697_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC697_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC697_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC697_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC697_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC697_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC697_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC697_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC697_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC697_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC697_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC697_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC697_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC697_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC697_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC697_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC697_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC697_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC697_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC697_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC697_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC697_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC697_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC697_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC697_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC697_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC697_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC697_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC697_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC697_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC697_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC697_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC697_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC697_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC697_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC697_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC697_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC697_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD02 0x102c +#define NVC697_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC697_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC697_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC697_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC697_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC697_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC697_SET_SPARE_NOOP01 0x1044 +#define NVC697_SET_SPARE_NOOP01_V 31:0 + +#define NVC697_SET_SPARE_NOOP02 0x1048 +#define NVC697_SET_SPARE_NOOP02_V 31:0 + +#define NVC697_SET_SPARE_NOOP03 0x104c +#define NVC697_SET_SPARE_NOOP03_V 31:0 + +#define NVC697_SET_SPARE_NOOP04 0x1050 +#define NVC697_SET_SPARE_NOOP04_V 31:0 + +#define NVC697_SET_SPARE_NOOP05 0x1054 +#define NVC697_SET_SPARE_NOOP05_V 31:0 + +#define NVC697_SET_SPARE_NOOP06 0x1058 +#define NVC697_SET_SPARE_NOOP06_V 31:0 + +#define NVC697_SET_SPARE_NOOP07 0x105c +#define NVC697_SET_SPARE_NOOP07_V 31:0 + +#define NVC697_SET_SPARE_NOOP08 0x1060 +#define NVC697_SET_SPARE_NOOP08_V 31:0 + +#define NVC697_SET_SPARE_NOOP09 0x1064 +#define NVC697_SET_SPARE_NOOP09_V 31:0 + +#define NVC697_SET_SPARE_NOOP10 0x1068 +#define NVC697_SET_SPARE_NOOP10_V 31:0 + +#define NVC697_SET_SPARE_NOOP11 0x106c +#define NVC697_SET_SPARE_NOOP11_V 31:0 + +#define NVC697_SET_SPARE_NOOP12 0x1070 +#define NVC697_SET_SPARE_NOOP12_V 31:0 + +#define NVC697_SET_SPARE_NOOP13 0x1074 +#define NVC697_SET_SPARE_NOOP13_V 31:0 + +#define NVC697_SET_SPARE_NOOP14 0x1078 +#define NVC697_SET_SPARE_NOOP14_V 31:0 + +#define NVC697_SET_SPARE_NOOP15 0x107c +#define NVC697_SET_SPARE_NOOP15_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC697_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC697_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC697_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC697_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC697_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC697_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC697_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC697_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC697_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC697_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC697_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC697_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC697_UNBIND_ALL 0x10f4 +#define NVC697_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC697_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC697_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC697_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC697_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC697_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC697_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC697_NO_OPERATION_DATA_HI 0x110c +#define NVC697_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC697_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC697_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC697_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC697_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC697_PM_TRIGGER_END 0x1114 +#define NVC697_PM_TRIGGER_END_V 31:0 + +#define NVC697_SET_VERTEX_ID_BASE 0x1118 +#define NVC697_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC697_SET_STENCIL_COMPRESSION 0x111c +#define NVC697_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC697_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC697_SET_TIR_CONTROL 0x1130 +#define NVC697_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC697_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC697_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC697_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC697_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC697_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC697_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC697_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC697_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 + +#define NVC697_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC697_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC697_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC697_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC697_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC697_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC697_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC697_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC697_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC697_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC697_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC697_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC697_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC697_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC697_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC697_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC697_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC697_FLUSH_PENDING_WRITES 0x1144 +#define NVC697_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC697_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC697_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC697_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC697_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC697_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC697_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC697_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC697_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC697_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC697_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC697_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC697_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC697_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC697_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC697_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC697_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC697_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC697_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC697_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC697_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC697_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC697_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_SCREEN_STATE_MASK 0x1204 +#define NVC697_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC697_SET_ZT_SPARSE 0x1208 +#define NVC697_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC697_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC697_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC697_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_SET_CT_SELECT 0x121c +#define NVC697_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC697_SET_CT_SELECT_TARGET0 6:4 +#define NVC697_SET_CT_SELECT_TARGET1 9:7 +#define NVC697_SET_CT_SELECT_TARGET2 12:10 +#define NVC697_SET_CT_SELECT_TARGET3 15:13 +#define NVC697_SET_CT_SELECT_TARGET4 18:16 +#define NVC697_SET_CT_SELECT_TARGET5 21:19 +#define NVC697_SET_CT_SELECT_TARGET6 24:22 +#define NVC697_SET_CT_SELECT_TARGET7 27:25 + +#define NVC697_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC697_SET_ZT_SIZE_A 0x1228 +#define NVC697_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC697_SET_ZT_SIZE_B 0x122c +#define NVC697_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC697_SET_ZT_SIZE_C 0x1230 +#define NVC697_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC697_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC697_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC697_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC697_SET_SAMPLER_BINDING 0x1234 +#define NVC697_SET_SAMPLER_BINDING_V 0:0 +#define NVC697_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC697_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC697_DRAW_AUTO 0x123c +#define NVC697_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC697_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC697_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC697_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC697_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC697_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC697_SET_BACK_END_COPY_A 0x1264 +#define NVC697_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC697_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC697_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC697_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC697_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BACK_END_COPY_B 0x1268 +#define NVC697_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC697_SET_BACK_END_COPY_C 0x126c +#define NVC697_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC697_SET_BACK_END_COPY_D 0x1270 +#define NVC697_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC697_SET_BACK_END_COPY_E 0x1274 +#define NVC697_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC697_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC697_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVC697_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC697_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC697_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC697_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC697_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC697_CLEAR_ZCULL_REGION 0x12c8 +#define NVC697_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC697_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC697_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC697_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC697_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC697_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC697_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC697_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC697_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC697_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC697_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC697_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC697_SET_DEPTH_TEST 0x12cc +#define NVC697_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC697_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_FILL_MODE 0x12d0 +#define NVC697_SET_FILL_MODE_V 31:0 +#define NVC697_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC697_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC697_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC697_SET_SHADE_MODE 0x12d4 +#define NVC697_SET_SHADE_MODE_V 31:0 +#define NVC697_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC697_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC697_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC697_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC697_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC697_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC697_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC697_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC697_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC697_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC697_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC697_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_DEPTH_WRITE 0x12e8 +#define NVC697_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC697_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_ALPHA_TEST 0x12ec +#define NVC697_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC697_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC697_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC697_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC697_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC697_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC697_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC697_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC697_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC697_D3D_SET_CULL_MODE 0x1308 +#define NVC697_D3D_SET_CULL_MODE_V 31:0 +#define NVC697_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC697_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC697_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC697_SET_DEPTH_FUNC 0x130c +#define NVC697_SET_DEPTH_FUNC_V 31:0 +#define NVC697_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC697_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC697_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC697_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC697_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC697_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC697_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC697_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC697_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC697_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC697_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC697_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC697_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC697_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC697_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC697_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC697_SET_ALPHA_REF 0x1310 +#define NVC697_SET_ALPHA_REF_V 31:0 + +#define NVC697_SET_ALPHA_FUNC 0x1314 +#define NVC697_SET_ALPHA_FUNC_V 31:0 +#define NVC697_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC697_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC697_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC697_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC697_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC697_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC697_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC697_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC697_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC697_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC697_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC697_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC697_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC697_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC697_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC697_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC697_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC697_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC697_SET_BLEND_CONST_RED 0x131c +#define NVC697_SET_BLEND_CONST_RED_V 31:0 + +#define NVC697_SET_BLEND_CONST_GREEN 0x1320 +#define NVC697_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC697_SET_BLEND_CONST_BLUE 0x1324 +#define NVC697_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC697_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC697_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC697_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC697_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC697_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC697_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC697_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC697_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC697_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC697_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BLEND_COLOR_OP 0x1340 +#define NVC697_SET_BLEND_COLOR_OP_V 31:0 +#define NVC697_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC697_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC697_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC697_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC697_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC697_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC697_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC697_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC697_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC697_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_BLEND_ALPHA_OP 0x134c +#define NVC697_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC697_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC697_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC697_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC697_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC697_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC697_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC697_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC697_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC697_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC697_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC697_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC697_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC697_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC697_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC697_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BLEND(i) (0x1360+(i)*4) +#define NVC697_SET_BLEND_ENABLE 0:0 +#define NVC697_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_STENCIL_TEST 0x1380 +#define NVC697_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC697_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_STENCIL_OP_FAIL 0x1384 +#define NVC697_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC697_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC697_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC697_SET_STENCIL_OP_ZPASS 0x138c +#define NVC697_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC697_SET_STENCIL_FUNC 0x1390 +#define NVC697_SET_STENCIL_FUNC_V 31:0 +#define NVC697_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC697_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC697_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC697_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC697_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC697_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC697_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC697_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC697_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC697_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC697_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC697_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC697_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC697_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC697_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC697_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC697_SET_STENCIL_FUNC_REF 0x1394 +#define NVC697_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC697_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC697_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC697_SET_STENCIL_MASK 0x139c +#define NVC697_SET_STENCIL_MASK_V 7:0 + +#define NVC697_SET_DRAW_AUTO_START 0x13a4 +#define NVC697_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC697_SET_PS_SATURATE 0x13a8 +#define NVC697_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC697_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC697_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC697_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC697_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC697_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC697_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC697_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC697_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC697_SET_WINDOW_ORIGIN 0x13ac +#define NVC697_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC697_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC697_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC697_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC697_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC697_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC697_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC697_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC697_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC697_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC697_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC697_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC697_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC697_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC697_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC697_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC697_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC697_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC697_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC697_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC697_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC697_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC697_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC697_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC697_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC697_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC697_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC697_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC697_STORE_ZCULL 0x1464 +#define NVC697_STORE_ZCULL_V 0:0 + +#define NVC697_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC697_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC697_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC697_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC697_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC697_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC697_LOAD_ZCULL 0x1500 +#define NVC697_LOAD_ZCULL_V 0:0 + +#define NVC697_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC697_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC697_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC697_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC697_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC697_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC697_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC697_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC697_SET_USER_CLIP_ENABLE 0x1510 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC697_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC697_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC697_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_POINT_SIZE 0x1518 +#define NVC697_SET_POINT_SIZE_V 31:0 + +#define NVC697_SET_ZCULL_STATS 0x151c +#define NVC697_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC697_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_POINT_SPRITE 0x1520 +#define NVC697_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC697_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC697_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC697_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC697_CLEAR_REPORT_VALUE 0x1530 +#define NVC697_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC697_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC697_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC697_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC697_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC697_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC697_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVC697_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC697_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC697_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_ZT_SELECT 0x1538 +#define NVC697_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC697_SET_RENDER_ENABLE_A 0x1550 +#define NVC697_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_RENDER_ENABLE_B 0x1554 +#define NVC697_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_RENDER_ENABLE_C 0x1558 +#define NVC697_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC697_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC697_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC697_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC697_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC697_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC697_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC697_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC697_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC697_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC697_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC697_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC697_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC697_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC697_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC697_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC697_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_TEX_HEADER_POOL_C 0x157c +#define NVC697_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC697_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC697_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC697_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC697_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC697_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC697_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC697_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC697_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC697_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC697_SET_SRGB_WRITE 0x15b8 +#define NVC697_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC697_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_DEPTH_BIAS 0x15bc +#define NVC697_SET_DEPTH_BIAS_V 31:0 + +#define NVC697_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC697_SET_RT_LAYER 0x15cc +#define NVC697_SET_RT_LAYER_V 15:0 +#define NVC697_SET_RT_LAYER_CONTROL 16:16 +#define NVC697_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC697_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC697_SET_ANTI_ALIAS 0x15d0 +#define NVC697_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC697_SET_EDGE_FLAG 0x15e4 +#define NVC697_SET_EDGE_FLAG_V 0:0 +#define NVC697_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC697_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC697_DRAW_INLINE_INDEX 0x15e8 +#define NVC697_DRAW_INLINE_INDEX_V 31:0 + +#define NVC697_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC697_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC697_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC697_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC697_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC697_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC697_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC697_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC697_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC697_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC697_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC697_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC697_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC697_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC697_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC697_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC697_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC697_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC697_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC697_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC697_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC697_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC697_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC697_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC697_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC697_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC697_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC697_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC697_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC697_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC697_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC697_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC697_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC697_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC697_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC697_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC697_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC697_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC697_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC697_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC697_END 0x1614 +#define NVC697_END_V 0:0 + +#define NVC697_BEGIN 0x1618 +#define NVC697_BEGIN_OP 15:0 +#define NVC697_BEGIN_OP_POINTS 0x00000000 +#define NVC697_BEGIN_OP_LINES 0x00000001 +#define NVC697_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC697_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC697_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC697_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC697_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC697_BEGIN_OP_QUADS 0x00000007 +#define NVC697_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC697_BEGIN_OP_POLYGON 0x00000009 +#define NVC697_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC697_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC697_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_BEGIN_OP_PATCH 0x0000000E +#define NVC697_BEGIN_PRIMITIVE_ID 24:24 +#define NVC697_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC697_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC697_BEGIN_INSTANCE_ID 27:26 +#define NVC697_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC697_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC697_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC697_BEGIN_SPLIT_MODE 30:29 +#define NVC697_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC697_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC697_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC697_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC697_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVC697_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC697_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_VERTEX_ID_COPY 0x161c +#define NVC697_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC697_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC697_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC697_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC697_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC697_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC697_LOAD_PRIMITIVE_ID 0x1624 +#define NVC697_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC697_SET_SHADER_BASED_CULL 0x162c +#define NVC697_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC697_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC697_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC697_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_CLASS_VERSION 0x1638 +#define NVC697_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC697_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC697_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC697_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC697_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC697_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC697_SET_DA_OUTPUT 0x164c +#define NVC697_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC697_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC697_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC697_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC697_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_POINT_CENTER_MODE 0x165c +#define NVC697_SET_POINT_CENTER_MODE_V 31:0 +#define NVC697_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC697_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC697_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC697_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC697_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC697_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC697_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC697_SET_LINE_STIPPLE 0x166c +#define NVC697_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC697_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC697_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC697_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC697_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC697_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC697_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC697_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC697_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC697_SET_PROVOKING_VERTEX 0x1684 +#define NVC697_SET_PROVOKING_VERTEX_V 0:0 +#define NVC697_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC697_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC697_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC697_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC697_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_POLYGON_STIPPLE 0x168c +#define NVC697_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC697_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_SHADER_CONTROL 0x1690 +#define NVC697_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC697_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC697_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC697_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC697_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC697_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC697_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC697_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC697_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC697_CHECK_CLASS_VERSION 0x16a0 +#define NVC697_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC697_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC697_SET_SPH_VERSION 0x16a4 +#define NVC697_SET_SPH_VERSION_CURRENT 15:0 +#define NVC697_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC697_CHECK_SPH_VERSION 0x16a8 +#define NVC697_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC697_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC697_SET_SCG_GRAPHICS_PRIORITY 0x16bc +#define NVC697_SET_SCG_GRAPHICS_PRIORITY_PRIORITY 5:0 + +#define NVC697_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS(i) (0x16c0+(i)*4) +#define NVC697_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC697_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC697_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC697_SET_AAM_VERSION 0x1790 +#define NVC697_SET_AAM_VERSION_CURRENT 15:0 +#define NVC697_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC697_CHECK_AAM_VERSION 0x1794 +#define NVC697_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC697_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC697_SET_ZT_LAYER 0x179c +#define NVC697_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC697_SET_INDEX_BUFFER_A 0x17c8 +#define NVC697_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC697_SET_INDEX_BUFFER_B 0x17cc +#define NVC697_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC697_SET_INDEX_BUFFER_E 0x17d8 +#define NVC697_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC697_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC697_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC697_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC697_SET_INDEX_BUFFER_F 0x17dc +#define NVC697_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC697_DRAW_INDEX_BUFFER 0x17e0 +#define NVC697_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC697_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC697_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC697_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC697_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC697_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC697_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC697_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC697_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC697_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC697_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC697_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC697_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC697_OGL_SET_CULL 0x1918 +#define NVC697_OGL_SET_CULL_ENABLE 0:0 +#define NVC697_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC697_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC697_OGL_SET_FRONT_FACE 0x191c +#define NVC697_OGL_SET_FRONT_FACE_V 31:0 +#define NVC697_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC697_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC697_OGL_SET_CULL_FACE 0x1920 +#define NVC697_OGL_SET_CULL_FACE_V 31:0 +#define NVC697_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC697_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC697_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC697_SET_VIEWPORT_PIXEL 0x1924 +#define NVC697_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC697_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC697_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC697_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC697_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC697_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC697_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE 17:16 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_USE_FIELD_MIN_Z_ZERO_MAX_Z_ONE 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MIN_Z_MAX_Z 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_ZERO_ONE 0x00000002 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MINUS_INF_PLUS_INF 0x00000003 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC697_SET_USER_CLIP_OP 0x1940 +#define NVC697_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC697_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC697_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC697_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC697_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC697_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC697_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC697_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC697_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC697_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC697_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC697_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC697_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC697_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC697_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC697_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC697_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC697_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC697_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC697_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC697_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC697_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC697_INVALIDATE_ZCULL 0x1958 +#define NVC697_INVALIDATE_ZCULL_V 31:0 +#define NVC697_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC697_SET_ZCULL 0x1968 +#define NVC697_SET_ZCULL_Z_ENABLE 0:0 +#define NVC697_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC697_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_ZCULL_BOUNDS 0x196c +#define NVC697_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC697_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC697_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC697_ZCULL_SYNC 0x1978 +#define NVC697_ZCULL_SYNC_V 31:0 + +#define NVC697_SET_CLIP_ID_TEST 0x197c +#define NVC697_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC697_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC697_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC697_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC697_SET_CLIP_ID 0x1984 +#define NVC697_SET_CLIP_ID_V 31:0 + +#define NVC697_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC697_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC697_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC697_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC697_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC697_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC697_SET_LOGIC_OP 0x19c4 +#define NVC697_SET_LOGIC_OP_ENABLE 0:0 +#define NVC697_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC697_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC697_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC697_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC697_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC697_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC697_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC697_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC697_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC697_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC697_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC697_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC697_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC697_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC697_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC697_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC697_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC697_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC697_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC697_SET_Z_COMPRESSION 0x19cc +#define NVC697_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC697_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC697_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC697_CLEAR_SURFACE 0x19d0 +#define NVC697_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC697_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC697_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC697_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC697_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC697_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC697_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC697_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC697_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC697_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC697_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC697_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC697_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC697_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC697_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC697_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC697_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC697_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC697_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC697_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC697_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC697_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC697_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC697_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC697_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC697_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC697_PIPE_NOP 0x1a2c +#define NVC697_PIPE_NOP_V 31:0 + +#define NVC697_SET_SPARE00 0x1a30 +#define NVC697_SET_SPARE00_V 31:0 + +#define NVC697_SET_SPARE01 0x1a34 +#define NVC697_SET_SPARE01_V 31:0 + +#define NVC697_SET_SPARE02 0x1a38 +#define NVC697_SET_SPARE02_V 31:0 + +#define NVC697_SET_SPARE03 0x1a3c +#define NVC697_SET_SPARE03_V 31:0 + +#define NVC697_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC697_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC697_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC697_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC697_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC697_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC697_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC697_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC697_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC697_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC697_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC697_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC697_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC697_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC697_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC697_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC697_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC697_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC697_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC697_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC697_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC697_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC697_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC697_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC697_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC697_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC697_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC697_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC697_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC697_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC697_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC697_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC697_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC697_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC697_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC697_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC697_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC697_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC697_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC697_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC697_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC697_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC697_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC697_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC697_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC697_SET_PIPELINE_RESERVED_B(j) (0x2004+(j)*64) +#define NVC697_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVC697_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC697_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC697_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC697_SET_PIPELINE_REGISTER_COUNT_V 8:0 + +#define NVC697_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC697_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC697_SET_PIPELINE_PROGRAM_ADDRESS_A(j) (0x2014+(j)*64) +#define NVC697_SET_PIPELINE_PROGRAM_ADDRESS_A_UPPER 7:0 + +#define NVC697_SET_PIPELINE_PROGRAM_ADDRESS_B(j) (0x2018+(j)*64) +#define NVC697_SET_PIPELINE_PROGRAM_ADDRESS_B_LOWER 31:0 + +#define NVC697_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVC697_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVC697_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC697_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC697_SET_FALCON00 0x2300 +#define NVC697_SET_FALCON00_V 31:0 + +#define NVC697_SET_FALCON01 0x2304 +#define NVC697_SET_FALCON01_V 31:0 + +#define NVC697_SET_FALCON02 0x2308 +#define NVC697_SET_FALCON02_V 31:0 + +#define NVC697_SET_FALCON03 0x230c +#define NVC697_SET_FALCON03_V 31:0 + +#define NVC697_SET_FALCON04 0x2310 +#define NVC697_SET_FALCON04_V 31:0 + +#define NVC697_SET_FALCON05 0x2314 +#define NVC697_SET_FALCON05_V 31:0 + +#define NVC697_SET_FALCON06 0x2318 +#define NVC697_SET_FALCON06_V 31:0 + +#define NVC697_SET_FALCON07 0x231c +#define NVC697_SET_FALCON07_V 31:0 + +#define NVC697_SET_FALCON08 0x2320 +#define NVC697_SET_FALCON08_V 31:0 + +#define NVC697_SET_FALCON09 0x2324 +#define NVC697_SET_FALCON09_V 31:0 + +#define NVC697_SET_FALCON10 0x2328 +#define NVC697_SET_FALCON10_V 31:0 + +#define NVC697_SET_FALCON11 0x232c +#define NVC697_SET_FALCON11_V 31:0 + +#define NVC697_SET_FALCON12 0x2330 +#define NVC697_SET_FALCON12_V 31:0 + +#define NVC697_SET_FALCON13 0x2334 +#define NVC697_SET_FALCON13_V 31:0 + +#define NVC697_SET_FALCON14 0x2338 +#define NVC697_SET_FALCON14_V 31:0 + +#define NVC697_SET_FALCON15 0x233c +#define NVC697_SET_FALCON15_V 31:0 + +#define NVC697_SET_FALCON16 0x2340 +#define NVC697_SET_FALCON16_V 31:0 + +#define NVC697_SET_FALCON17 0x2344 +#define NVC697_SET_FALCON17_V 31:0 + +#define NVC697_SET_FALCON18 0x2348 +#define NVC697_SET_FALCON18_V 31:0 + +#define NVC697_SET_FALCON19 0x234c +#define NVC697_SET_FALCON19_V 31:0 + +#define NVC697_SET_FALCON20 0x2350 +#define NVC697_SET_FALCON20_V 31:0 + +#define NVC697_SET_FALCON21 0x2354 +#define NVC697_SET_FALCON21_V 31:0 + +#define NVC697_SET_FALCON22 0x2358 +#define NVC697_SET_FALCON22_V 31:0 + +#define NVC697_SET_FALCON23 0x235c +#define NVC697_SET_FALCON23_V 31:0 + +#define NVC697_SET_FALCON24 0x2360 +#define NVC697_SET_FALCON24_V 31:0 + +#define NVC697_SET_FALCON25 0x2364 +#define NVC697_SET_FALCON25_V 31:0 + +#define NVC697_SET_FALCON26 0x2368 +#define NVC697_SET_FALCON26_V 31:0 + +#define NVC697_SET_FALCON27 0x236c +#define NVC697_SET_FALCON27_V 31:0 + +#define NVC697_SET_FALCON28 0x2370 +#define NVC697_SET_FALCON28_V 31:0 + +#define NVC697_SET_FALCON29 0x2374 +#define NVC697_SET_FALCON29_V 31:0 + +#define NVC697_SET_FALCON30 0x2378 +#define NVC697_SET_FALCON30_V 31:0 + +#define NVC697_SET_FALCON31 0x237c +#define NVC697_SET_FALCON31_V 31:0 + +#define NVC697_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC697_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC697_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC697_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC697_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC697_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC697_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC697_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC697_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC697_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC697_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC697_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC697_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC697_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC697_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC697_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC697_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC697_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC697_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC697_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC697_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC697_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC697_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC697_SET_TRAP_HANDLER_A 0x25f8 +#define NVC697_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC697_SET_TRAP_HANDLER_B 0x25fc +#define NVC697_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC697_SET_COLOR_CLAMP 0x2600 +#define NVC697_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC697_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC697_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC697_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC697_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC697_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC697_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC697_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC697_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC697_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC697_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC697_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC697_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC697_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC697_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC697_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC697_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC697_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC697_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC697_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC697_CALL_MME_MACRO_V 31:0 + +#define NVC697_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC697_CALL_MME_DATA_V 31:0 + +#endif /* _cl_ampere_a_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc6b0.h b/userspace/sdks/nv570/inc/class/clc6b0.h new file mode 100644 index 0000000..d36f053 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc6b0.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clc6b0_h_ +#define clc6b0_h_ + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC6B0_VIDEO_DECODER (0x0000C6B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc6b0_h + diff --git a/userspace/sdks/nv570/inc/class/clc6b5.h b/userspace/sdks/nv570/inc/class/clc6b5.h new file mode 100644 index 0000000..873ca74 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc6b5.h @@ -0,0 +1,282 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clc6b5_h_ +#define _clc6b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define AMPERE_DMA_COPY_A (0x0000C6B5) + +#define NVC6B5_NOP (0x00000100) +#define NVC6B5_NOP_PARAMETER 31:0 +#define NVC6B5_PM_TRIGGER (0x00000140) +#define NVC6B5_PM_TRIGGER_V 31:0 +#define NVC6B5_SET_SEMAPHORE_A (0x00000240) +#define NVC6B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC6B5_SET_SEMAPHORE_B (0x00000244) +#define NVC6B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC6B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC6B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC6B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC6B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC6B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC6B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC6B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC6B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC6B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC6B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC6B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC6B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC6B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC6B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC6B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC6B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC6B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC6B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC6B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVC6B5_SET_SRC_PHYS_MODE_BASIC_KIND 5:2 +#define NVC6B5_SET_SRC_PHYS_MODE_PEER_ID 8:6 +#define NVC6B5_SET_SRC_PHYS_MODE_FLA 9:9 +#define NVC6B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC6B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC6B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC6B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC6B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC6B5_SET_DST_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVC6B5_SET_DST_PHYS_MODE_BASIC_KIND 5:2 +#define NVC6B5_SET_DST_PHYS_MODE_PEER_ID 8:6 +#define NVC6B5_SET_DST_PHYS_MODE_FLA 9:9 +#define NVC6B5_LAUNCH_DMA (0x00000300) +#define NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC6B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC6B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC6B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC6B5_LAUNCH_DMA_FLUSH_TYPE 25:25 +#define NVC6B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000) +#define NVC6B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE (0x00000003) +#define NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC6B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC6B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC6B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC6B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC6B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC6B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC6B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC6B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC6B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC6B5_LAUNCH_DMA_VPRMODE 23:22 +#define NVC6B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVC6B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC6B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC6B5_LAUNCH_DMA_DISABLE_PLC 26:26 +#define NVC6B5_LAUNCH_DMA_DISABLE_PLC_FALSE (0x00000000) +#define NVC6B5_LAUNCH_DMA_DISABLE_PLC_TRUE (0x00000001) +#define NVC6B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 +#define NVC6B5_OFFSET_IN_UPPER (0x00000400) +#define NVC6B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC6B5_OFFSET_IN_LOWER (0x00000404) +#define NVC6B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC6B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC6B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC6B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC6B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC6B5_PITCH_IN (0x00000410) +#define NVC6B5_PITCH_IN_VALUE 31:0 +#define NVC6B5_PITCH_OUT (0x00000414) +#define NVC6B5_PITCH_OUT_VALUE 31:0 +#define NVC6B5_LINE_LENGTH_IN (0x00000418) +#define NVC6B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC6B5_LINE_COUNT (0x0000041C) +#define NVC6B5_LINE_COUNT_VALUE 31:0 +#define NVC6B5_SET_REMAP_CONST_A (0x00000700) +#define NVC6B5_SET_REMAP_CONST_A_V 31:0 +#define NVC6B5_SET_REMAP_CONST_B (0x00000704) +#define NVC6B5_SET_REMAP_CONST_B_V 31:0 +#define NVC6B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC6B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC6B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC6B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC6B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC6B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC6B5_SET_DST_WIDTH (0x00000710) +#define NVC6B5_SET_DST_WIDTH_V 31:0 +#define NVC6B5_SET_DST_HEIGHT (0x00000714) +#define NVC6B5_SET_DST_HEIGHT_V 31:0 +#define NVC6B5_SET_DST_DEPTH (0x00000718) +#define NVC6B5_SET_DST_DEPTH_V 31:0 +#define NVC6B5_SET_DST_LAYER (0x0000071C) +#define NVC6B5_SET_DST_LAYER_V 31:0 +#define NVC6B5_SET_DST_ORIGIN (0x00000720) +#define NVC6B5_SET_DST_ORIGIN_X 15:0 +#define NVC6B5_SET_DST_ORIGIN_Y 31:16 +#define NVC6B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC6B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC6B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC6B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC6B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC6B5_SET_SRC_WIDTH (0x0000072C) +#define NVC6B5_SET_SRC_WIDTH_V 31:0 +#define NVC6B5_SET_SRC_HEIGHT (0x00000730) +#define NVC6B5_SET_SRC_HEIGHT_V 31:0 +#define NVC6B5_SET_SRC_DEPTH (0x00000734) +#define NVC6B5_SET_SRC_DEPTH_V 31:0 +#define NVC6B5_SET_SRC_LAYER (0x00000738) +#define NVC6B5_SET_SRC_LAYER_V 31:0 +#define NVC6B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC6B5_SET_SRC_ORIGIN_X 15:0 +#define NVC6B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC6B5_SRC_ORIGIN_X (0x00000744) +#define NVC6B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC6B5_SRC_ORIGIN_Y (0x00000748) +#define NVC6B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC6B5_DST_ORIGIN_X (0x0000074C) +#define NVC6B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC6B5_DST_ORIGIN_Y (0x00000750) +#define NVC6B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC6B5_PM_TRIGGER_END (0x00001114) +#define NVC6B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc6b5_h + diff --git a/userspace/sdks/nv570/inc/class/clc6b5sw.h b/userspace/sdks/nv570/inc/class/clc6b5sw.h new file mode 100644 index 0000000..2b41bdf --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc6b5sw.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc6b5sw.finn +// + + + +// +// Using VERSION_0 will cause the API to interpret +// engineType as a CE engine instance. This allows +// for backward compatibility with 85B5sw and 90B5sw. +// +#define NVC6B5_ALLOCATION_PARAMETERS_VERSION_0 0 + +// +// Using VERSION_1 will cause the API to interpret +// engineType as an NV2080_ENGINE_TYPE ordinal. +// +#define NVC6B5_ALLOCATION_PARAMETERS_VERSION_1 1 + +#define NVC6B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc6b5U) + +typedef struct NVC6B5_ALLOCATION_PARAMETERS { + NvU32 version; + NvU32 engineType; +} NVC6B5_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clc6c0.h b/userspace/sdks/nv570/inc/class/clc6c0.h new file mode 100644 index 0000000..48aa385 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc6c0.h @@ -0,0 +1,697 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_ampere_compute_a_h_ +#define _cl_ampere_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl ampere_compute_a */ + +#include "nvtypes.h" + +#define AMPERE_COMPUTE_A 0xC6C0 + +#define NVC6C0_SET_OBJECT 0x0000 +#define NVC6C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC6C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC6C0_NO_OPERATION 0x0100 +#define NVC6C0_NO_OPERATION_V 31:0 + +#define NVC6C0_SET_NOTIFY_A 0x0104 +#define NVC6C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC6C0_SET_NOTIFY_B 0x0108 +#define NVC6C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC6C0_NOTIFY 0x010c +#define NVC6C0_NOTIFY_TYPE 31:0 +#define NVC6C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC6C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC6C0_WAIT_FOR_IDLE 0x0110 +#define NVC6C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC6C0_SEND_GO_IDLE 0x013c +#define NVC6C0_SEND_GO_IDLE_V 31:0 + +#define NVC6C0_PM_TRIGGER 0x0140 +#define NVC6C0_PM_TRIGGER_V 31:0 + +#define NVC6C0_PM_TRIGGER_WFI 0x0144 +#define NVC6C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC6C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC6C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC6C0_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC6C0_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC6C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC6C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC6C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC6C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC6C0_LINE_LENGTH_IN 0x0180 +#define NVC6C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC6C0_LINE_COUNT 0x0184 +#define NVC6C0_LINE_COUNT_VALUE 31:0 + +#define NVC6C0_OFFSET_OUT_UPPER 0x0188 +#define NVC6C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC6C0_OFFSET_OUT 0x018c +#define NVC6C0_OFFSET_OUT_VALUE 31:0 + +#define NVC6C0_PITCH_OUT 0x0190 +#define NVC6C0_PITCH_OUT_VALUE 31:0 + +#define NVC6C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC6C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC6C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC6C0_SET_DST_WIDTH 0x0198 +#define NVC6C0_SET_DST_WIDTH_V 31:0 + +#define NVC6C0_SET_DST_HEIGHT 0x019c +#define NVC6C0_SET_DST_HEIGHT_V 31:0 + +#define NVC6C0_SET_DST_DEPTH 0x01a0 +#define NVC6C0_SET_DST_DEPTH_V 31:0 + +#define NVC6C0_SET_DST_LAYER 0x01a4 +#define NVC6C0_SET_DST_LAYER_V 31:0 + +#define NVC6C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC6C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC6C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC6C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC6C0_LAUNCH_DMA 0x01b0 +#define NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC6C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC6C0_LOAD_INLINE_DATA 0x01b4 +#define NVC6C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC6C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC6C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC6C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC6C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC6C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC6C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC6C0_SET_SM_SCG_CONTROL 0x01e8 +#define NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS 0:0 +#define NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE 0x00000000 +#define NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE 0x00000001 + +#define NVC6C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC6C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC6C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC6C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC6C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC6C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC6C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC6C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC6C0_PERFMON_TRANSFER 0x0210 +#define NVC6C0_PERFMON_TRANSFER_V 31:0 + +#define NVC6C0_SET_QMD_VIRTUALIZATION_BASE_A 0x0214 +#define NVC6C0_SET_QMD_VIRTUALIZATION_BASE_A_ADDRESS_UPPER 7:0 + +#define NVC6C0_SET_QMD_VIRTUALIZATION_BASE_B 0x0218 +#define NVC6C0_SET_QMD_VIRTUALIZATION_BASE_B_ADDRESS_LOWER 31:0 + +#define NVC6C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC6C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC6C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC6C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC6C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC6C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC6C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC6C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC6C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC6C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC6C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC6C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC6C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC6C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC6C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC6C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC6C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC6C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC6C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC6C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC6C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC6C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC6C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC6C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC6C0_SET_SCG_CONTROL 0x0270 +#define NVC6C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 +#define NVC6C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 +#define NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 +#define NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 +#define NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 + +#define NVC6C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC6C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC6C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC6C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC6C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC6C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC6C0_SET_QMD_VERSION 0x0288 +#define NVC6C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC6C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC6C0_CHECK_QMD_VERSION 0x0290 +#define NVC6C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC6C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC6C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC6C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL 0x029c +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_CONSTANT_BUFFER_MASK 7:0 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE 8:8 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE 12:12 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE 16:16 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE 20:20 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE 24:24 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_TRUE 0x00000001 + +#define NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC6C0_SCG_HYSTERESIS_CONTROL 0x02a8 +#define NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 +#define NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 +#define NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 +#define NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 + +#define NVC6C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC6C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC6C0_SEND_PCAS_A 0x02b4 +#define NVC6C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC6C0_SEND_PCAS_B 0x02b8 +#define NVC6C0_SEND_PCAS_B_FROM 23:0 +#define NVC6C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC6C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC6C0_SEND_SIGNALING_PCAS2_B 0x02c0 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION 3:0 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_NOP 0x00000000 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE 0x00000001 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_SCHEDULE 0x00000002 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_COPY_SCHEDULE 0x00000003 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_PUT 0x00000006 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_DECREMENT_DEPENDENCE 0x00000007 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH 0x00000008 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH_SCHEDULE 0x00000009 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_SCHEDULE 0x0000000A +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_FORCE_REQUIRE_SCHEDULING 0x0000000B + +#define NVC6C0_SET_SKED_CACHE_CONTROL 0x02cc +#define NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID 0:0 +#define NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE 0x00000000 +#define NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE 0x00000001 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC6C0_SET_SPA_VERSION 0x0310 +#define NVC6C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC6C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC6C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC6C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC6C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC6C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC6C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC6C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC6C0_SET_FALCON00 0x0500 +#define NVC6C0_SET_FALCON00_V 31:0 + +#define NVC6C0_SET_FALCON01 0x0504 +#define NVC6C0_SET_FALCON01_V 31:0 + +#define NVC6C0_SET_FALCON02 0x0508 +#define NVC6C0_SET_FALCON02_V 31:0 + +#define NVC6C0_SET_FALCON03 0x050c +#define NVC6C0_SET_FALCON03_V 31:0 + +#define NVC6C0_SET_FALCON04 0x0510 +#define NVC6C0_SET_FALCON04_V 31:0 + +#define NVC6C0_SET_FALCON05 0x0514 +#define NVC6C0_SET_FALCON05_V 31:0 + +#define NVC6C0_SET_FALCON06 0x0518 +#define NVC6C0_SET_FALCON06_V 31:0 + +#define NVC6C0_SET_FALCON07 0x051c +#define NVC6C0_SET_FALCON07_V 31:0 + +#define NVC6C0_SET_FALCON08 0x0520 +#define NVC6C0_SET_FALCON08_V 31:0 + +#define NVC6C0_SET_FALCON09 0x0524 +#define NVC6C0_SET_FALCON09_V 31:0 + +#define NVC6C0_SET_FALCON10 0x0528 +#define NVC6C0_SET_FALCON10_V 31:0 + +#define NVC6C0_SET_FALCON11 0x052c +#define NVC6C0_SET_FALCON11_V 31:0 + +#define NVC6C0_SET_FALCON12 0x0530 +#define NVC6C0_SET_FALCON12_V 31:0 + +#define NVC6C0_SET_FALCON13 0x0534 +#define NVC6C0_SET_FALCON13_V 31:0 + +#define NVC6C0_SET_FALCON14 0x0538 +#define NVC6C0_SET_FALCON14_V 31:0 + +#define NVC6C0_SET_FALCON15 0x053c +#define NVC6C0_SET_FALCON15_V 31:0 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC6C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC6C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS(i) (0x0da0+(i)*4) +#define NVC6C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC6C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC6C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC6C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC6C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC6C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC6C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC6C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC6C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC6C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC6C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC6C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC6C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC6C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC6C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC6C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC6C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC6C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC6C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC6C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC6C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC6C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC6C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC6C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC6C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC6C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC6C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC6C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC6C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC6C0_PIPE_NOP 0x1a2c +#define NVC6C0_PIPE_NOP_V 31:0 + +#define NVC6C0_SET_SPARE00 0x1a30 +#define NVC6C0_SET_SPARE00_V 31:0 + +#define NVC6C0_SET_SPARE01 0x1a34 +#define NVC6C0_SET_SPARE01_V 31:0 + +#define NVC6C0_SET_SPARE02 0x1a38 +#define NVC6C0_SET_SPARE02_V 31:0 + +#define NVC6C0_SET_SPARE03 0x1a3c +#define NVC6C0_SET_SPARE03_V 31:0 + +#define NVC6C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC6C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC6C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC6C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC6C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC6C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC6C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC6C0_SET_TRAP_HANDLER_A 0x25f8 +#define NVC6C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC6C0_SET_TRAP_HANDLER_B 0x25fc +#define NVC6C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC6C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC6C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC6C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC6C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC6C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC6C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC6C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC6C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC6C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC6C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC6C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC6C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_ampere_compute_a_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc6fa.h b/userspace/sdks/nv570/inc/class/clc6fa.h new file mode 100644 index 0000000..92d06ea --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc6fa.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc6fa_h_ +#define _clc6fa_h_ + +#define NVC6FA_VIDEO_OFA (0x0000C6FA) + +#endif // _clc6fa_h_ diff --git a/userspace/sdks/nv570/inc/class/clc761.h b/userspace/sdks/nv570/inc/class/clc761.h new file mode 100644 index 0000000..38ff555 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc761.h @@ -0,0 +1,30 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc761_h_ +#define _clc761_h_ + +#define BLACKWELL_USERMODE_A (0xc761) + +#endif /* _clc761_h_ */ + diff --git a/userspace/sdks/nv570/inc/class/clc763.h b/userspace/sdks/nv570/inc/class/clc763.h new file mode 100644 index 0000000..eb70baa --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc763.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc763_h_ +#define _clc763_h_ + +#define MMU_VIDMEM_ACCESS_BIT_BUFFER (0xc763) + +#endif /* _clc763_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc770.h b/userspace/sdks/nv570/inc/class/clc770.h new file mode 100644 index 0000000..87580e5 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc770.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc770.finn +// + +#define NVC770_DISPLAY (0xc770U) /* finn: Evaluated from "NVC770_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + + + diff --git a/userspace/sdks/nv570/inc/class/clc771.h b/userspace/sdks/nv570/inc/class/clc771.h new file mode 100644 index 0000000..9d484a7 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc771.h @@ -0,0 +1,257 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc771_h_ +#define _clc771_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC771_DISP_SF_USER (0x000C771) + +typedef volatile struct _clc771_tag0 { + NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x000D0FFF:0x000D0000 */ +} _NvC771DispSfUser, NvC771DispSfUserMap; + +#define NVC771_SF_HDMI_INFO_IDX_GENERIC_INFOFRAME 0x00000001 /* */ +#define NVC771_SF_HDMI_INFO_IDX_VSI 0x00000004 /* */ +#define NVC771_SF_HDMI_INFO_CTRL(i,j) (0x000E0000-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVC771_SF_HDMI_INFO_CTRL__SIZE_1 4 /* */ +#define NVC771_SF_HDMI_INFO_CTRL__SIZE_2 5 /* */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x000E0000-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 8 /* */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER 4:4 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_DIS 0x00000000 /* RWI-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_EN 0x00000001 /* RW--V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE 8:8 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_EN 0x00000001 /* RW--V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW 9:9 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_STATUS(i) (0x000E0004-0x000E0000+(i)*1024) /* R--4A */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1 8 /* */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_STATUS_SENT 0:0 /* R-IVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT 0x00000000 /* R-I-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x000E0008-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 8 /* */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x000E000C-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 8 /* */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x000E0010-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 8 /* */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x000E0014-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 8 /* */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x000E0018-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 8 /* */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW(i) (0x000E001C-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW__SIZE_1 8 /* */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_CTRL(i,j) (0x000E0200-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_CTRL__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_CTRL__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_CTRL_ENABLE 0:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_SINGLE 4:4 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_CTRL_SINGLE_NO 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_SINGLE_YES 0x00000001 /* RW--V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_LOC 9:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_CTRL_LOC_VBLANK 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_LOC_VSYNC 0x00000001 /* RW--V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_LOC_LOADV 0x00000002 /* RW--V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_NEW 12:12 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_CTRL_NEW_INIT 0x00000000 /* R-I-V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_NEW_DONE 0x00000000 /* R---V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_NEW_PENDING 0x00000001 /* R---V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_NEW_TRIGGER 0x00000001 /* -W--T */ +#define NVC771_SF_SHARED_GENERIC_CTRL_STATUS 13:13 /* R-IVF */ +#define NVC771_SF_SHARED_GENERIC_CTRL_STATUS_DONE 0x00000001 /* R---V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_STATUS_WAIT 0x00000000 /* R---V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_STATUS_INIT 0x00000000 /* R-I-V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_CHECKSUM_HW 16:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_CTRL_CHECKSUM_HW_NO 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_CHECKSUM_HW_YES 0x00000001 /* RW--V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_BUSY 20:20 /* R-IVF */ +#define NVC771_SF_SHARED_GENERIC_CTRL_BUSY_NO 0x00000000 /* R-I-V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_BUSY_YES 0x00000001 /* R---V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_VSC_SDP_UPDATE_RFB_OVERRIDE 28:28 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_CTRL_VSC_SDP_UPDATE_RFB_OVERRIDE_DISABLE 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_VSC_SDP_UPDATE_RFB_OVERRIDE_ENABLE 0x00000001 /* RW--V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_VSC_SDP_SU_COORDINATES_VALID_OVERRIDE 31:31 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_CTRL_VSC_SDP_SU_COORDINATES_VALID_OVERRIDE_DISABLE 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_VSC_SDP_SU_COORDINATES_VALID_OVERRIDE_ENABLE 0x00000001 /* RW--V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER(i,j) (0x000E0204-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB3 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB3_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0(i,j) (0x000E0208-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB0 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB0_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB1 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB1_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB2 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB2_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB3 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB3_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1(i,j) (0x000E020C-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB4 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB4_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB5 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB5_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB6 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB6_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB7 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB7_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2(i,j) (0x000E0210-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB8 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB8_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB9 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB9_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB10 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB10_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB11 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB11_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3(i,j) (0x000E0214-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB12 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB12_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB13 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB13_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB14 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB14_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB15 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB15_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4(i,j) (0x000E0218-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB16 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB16_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB17 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB17_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB18 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB18_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB19 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB19_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5(i,j) (0x000E021C-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB20 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB20_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB21 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB21_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB22 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB22_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB23 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB23_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6(i,j) (0x000E0220-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB24 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB24_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB25 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB25_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB26 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB26_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB27 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB27_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7(i,j) (0x000E0224-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB28 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB28_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB29 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB29_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB30 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB30_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB31 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB31_INIT 0x00000000 /* RWI-V */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _clc771_h_ diff --git a/userspace/sdks/nv570/inc/class/clc773.h b/userspace/sdks/nv570/inc/class/clc773.h new file mode 100644 index 0000000..eb20db3 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc773.h @@ -0,0 +1,667 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc773_h_ +#define _clc773_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC773_DISP_CAPABILITIES 0xC773 + +typedef volatile struct _clc773_tag0 { + NvU32 dispCapabilities[0x400]; +} _NvC773DispCapabilities,NvC773DispCapabilities_Map ; + + +#define NVC773_SYS_CAP 0x0 /* RW-4R */ +#define NVC773_SYS_CAP_HEAD0_EXISTS 0:0 /* RWIVF */ +#define NVC773_SYS_CAP_HEAD0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAP_HEAD1_EXISTS 1:1 /* RWIVF */ +#define NVC773_SYS_CAP_HEAD1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAP_HEAD2_EXISTS 2:2 /* RWIVF */ +#define NVC773_SYS_CAP_HEAD2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAP_HEAD3_EXISTS 3:3 /* RWIVF */ +#define NVC773_SYS_CAP_HEAD3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAP_HEAD4_EXISTS 4:4 /* RWIVF */ +#define NVC773_SYS_CAP_HEAD4_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAP_HEAD5_EXISTS 5:5 /* RWIVF */ +#define NVC773_SYS_CAP_HEAD5_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAP_HEAD6_EXISTS 6:6 /* RWIVF */ +#define NVC773_SYS_CAP_HEAD6_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAP_HEAD7_EXISTS 7:7 /* RWIVF */ +#define NVC773_SYS_CAP_HEAD7_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVC773_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */ +#define NVC773_SYS_CAP_HEAD_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAP_SOR0_EXISTS 8:8 /* RWIVF */ +#define NVC773_SYS_CAP_SOR0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAP_SOR1_EXISTS 9:9 /* RWIVF */ +#define NVC773_SYS_CAP_SOR1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAP_SOR2_EXISTS 10:10 /* RWIVF */ +#define NVC773_SYS_CAP_SOR2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAP_SOR3_EXISTS 11:11 /* RWIVF */ +#define NVC773_SYS_CAP_SOR3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAP_SOR4_EXISTS 12:12 /* RWIVF */ +#define NVC773_SYS_CAP_SOR4_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAP_SOR5_EXISTS 13:13 /* RWIVF */ +#define NVC773_SYS_CAP_SOR5_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAP_SOR6_EXISTS 14:14 /* RWIVF */ +#define NVC773_SYS_CAP_SOR6_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAP_SOR7_EXISTS 15:15 /* RWIVF */ +#define NVC773_SYS_CAP_SOR7_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* RWIVF */ +#define NVC773_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */ +#define NVC773_SYS_CAP_SOR_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAP_DSI0_EXISTS 20:20 /* RWIVF */ +#define NVC773_SYS_CAP_DSI0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAP_DSI0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAP_DSI0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAP_DSI1_EXISTS 21:21 /* RWIVF */ +#define NVC773_SYS_CAP_DSI1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAP_DSI1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAP_DSI1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAP_DSI2_EXISTS 22:22 /* RWIVF */ +#define NVC773_SYS_CAP_DSI2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAP_DSI2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAP_DSI2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAP_DSI3_EXISTS 23:23 /* RWIVF */ +#define NVC773_SYS_CAP_DSI3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAP_DSI3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAP_DSI3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAP_DSI_EXISTS(i) (20+(i)):(20+(i)) /* RWIVF */ +#define NVC773_SYS_CAP_DSI_EXISTS__SIZE_1 4 /* */ +#define NVC773_SYS_CAP_DSI_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAP_DSI_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAP_DSI_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB 0x4 /* RW-4R */ +#define NVC773_SYS_CAPB_WINDOW0_EXISTS 0:0 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW1_EXISTS 1:1 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW2_EXISTS 2:2 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW3_EXISTS 3:3 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW4_EXISTS 4:4 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW4_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW5_EXISTS 5:5 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW5_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW6_EXISTS 6:6 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW6_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW7_EXISTS 7:7 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW7_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW8_EXISTS 8:8 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW8_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW8_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW8_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW9_EXISTS 9:9 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW9_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW9_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW9_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW10_EXISTS 10:10 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW10_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW10_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW10_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW11_EXISTS 11:11 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW11_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW11_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW11_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW12_EXISTS 12:12 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW12_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW12_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW12_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW13_EXISTS 13:13 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW13_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW13_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW13_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW14_EXISTS 14:14 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW14_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW14_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW14_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW15_EXISTS 15:15 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW15_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW15_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW15_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW16_EXISTS 16:16 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW16_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW16_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW16_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW17_EXISTS 17:17 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW17_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW17_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW17_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW18_EXISTS 18:18 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW18_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW18_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW18_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW19_EXISTS 19:19 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW19_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW19_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW19_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW20_EXISTS 20:20 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW20_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW20_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW20_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW21_EXISTS 21:21 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW21_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW21_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW21_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW22_EXISTS 22:22 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW22_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW22_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW22_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW23_EXISTS 23:23 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW23_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW23_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW23_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW24_EXISTS 24:24 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW24_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW24_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW24_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW25_EXISTS 25:25 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW25_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW25_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW25_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW26_EXISTS 26:26 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW26_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW26_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW26_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW27_EXISTS 27:27 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW27_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW27_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW27_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW28_EXISTS 28:28 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW28_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW28_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW28_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW29_EXISTS 29:29 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW29_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW29_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW29_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW30_EXISTS 30:30 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW30_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW30_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW30_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW31_EXISTS 31:31 /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW31_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW31_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW31_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVC773_SYS_CAPB_WINDOW_EXISTS__SIZE_1 32 /* */ +#define NVC773_SYS_CAPB_WINDOW_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SYS_CAPB_WINDOW_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC773_SYS_CAPB_WINDOW_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPA 0x10 /* RW-4R */ +#define NVC773_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES 15:0 /* RWIUF */ +#define NVC773_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES_INIT 0x00000000 /* RWI-V */ +#define NVC773_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH 17:16 /* RWIVF */ +#define NVC773_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NVC773_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B 0x00000000 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B 0x00000001 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B 0x00000002 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B 0x00000003 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_ROTATION 18:18 /* RWIVF */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_ROTATION_INIT 0x00000000 /* RWI-V */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_ROTATION_FALSE 0x00000000 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_ROTATION_TRUE 0x00000001 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_PLANAR 19:19 /* RWIVF */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_PLANAR_INIT 0x00000000 /* RWI-V */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_PLANAR_FALSE 0x00000000 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_PLANAR_TRUE 0x00000001 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_VGA 20:20 /* RWIVF */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_VGA_INIT 0x00000000 /* RWI-V */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE 0x00000000 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE 0x00000001 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION 21:21 /* RWIVF */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_INIT 0x00000000 /* RWI-V */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_FALSE 0x00000000 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_TRUE 0x00000001 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_MSCG 22:22 /* RWIVF */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_MSCG_INIT 0x00000000 /* RWI-V */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_MSCG_FALSE 0x00000000 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_MSCG_TRUE 0x00000001 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH 23:23 /* RWIVF */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_INIT 0x00000000 /* RWI-V */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_FALSE 0x00000000 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_TRUE 0x00000001 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT 26:26 /* RWIVF */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_INIT 0x00000000 /* RWI-V */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_FALSE 0x00000000 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_TRUE 0x00000001 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION 31:30 /* RWIVF */ +#define NVC773_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_INIT 0x00000000 /* RWI-V */ +#define NVC773_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B 0x00000000 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B 0x00000001 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B 0x00000002 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B 0x00000003 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPC 0x18 /* RW-4R */ +#define NVC773_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE 1:0 /* RWIVF */ +#define NVC773_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_INIT 0x00000000 /* RWI-V */ +#define NVC773_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_32B 0x00000000 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_64B 0x00000001 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_128B 0x00000002 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_256B 0x00000003 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED 6:4 /* RWIVF */ +#define NVC773_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_INIT 0x00000000 /* RWI-V */ +#define NVC773_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_NONE 0x00000000 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_TWO 0x00000001 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_FOUR 0x00000002 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_EIGHT 0x00000003 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_SIXTEEN 0x00000004 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR 11:11 /* RWIVF */ +#define NVC773_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_FALSE 0x00000000 /* RWI-V */ +#define NVC773_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_TRUE 0x00000001 /* RW--V */ +#define NVC773_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP 12:12 /* RWIVF */ +#define NVC773_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_FALSE 0x00000000 /* RWI-V */ +#define NVC773_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_TRUE 0x00000001 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA(i) (0x680+(i)*32) /* RW-4A */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA__SIZE_1 8 /* */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_FULL_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_UNIT_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT 16:16 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT 17:17 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT 18:18 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT 19:19 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT 20:20 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT 21:21 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT 22:22 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT 23:23 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT 24:24 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPB(i) (0x684+(i)*32) /* RW-4A */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPB__SIZE_1 8 /* */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPB_VGA 0:0 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPB_VGA_TRUE 0x00000001 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPB_VGA_FALSE 0x00000000 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPB_VGA_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGSZ 9:6 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGSZ_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGNR 12:10 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGNR_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT 15:15 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC(i) (0x688+(i)*32) /* RW-4A */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC__SIZE_1 8 /* */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_OCSC0_PRECISION 4:0 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_OCSC0_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_OCSC1_PRECISION 12:8 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_OCSC1_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP 13:13 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_SF_PRECISION 20:16 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_SF_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_CI_PRECISION 24:21 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_CI_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB 25:25 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPD(i) (0x68c+(i)*32) /* RW-4A */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPD__SIZE_1 8 /* */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPE(i) (0x690+(i)*32) /* RW-4A */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPE__SIZE_1 8 /* */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPE_DSC_RATEBUFSIZE 3:0 /* RWIUF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPE_DSC_RATEBUFSIZE_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPE_DSC_LINEBUFSIZE 13:8 /* RWIUF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPE_DSC_LINEBUFSIZE_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422 16:16 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_TRUE 0x00000001 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_FALSE 0x00000000 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420 17:17 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_TRUE 0x00000001 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_FALSE 0x00000000 /* RW--V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_INIT 0x00000000 /* RWI-V */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPF(i) (0x694+(i)*32) /* RW-4A */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPF__SIZE_1 8 /* */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPF_VFILTER_MAX_PIXELS 15:0 /* RWIVF */ +#define NVC773_POSTCOMP_HEAD_HDR_CAPF_VFILTER_MAX_PIXELS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SOR_CAP(i) (0x144+(i)*8) /* RW-4A */ +#define NVC773_SOR_CAP__SIZE_1 8 /* */ +#define NVC773_SOR_CAP_SINGLE_LVDS_18 0:0 /* RWIVF */ +#define NVC773_SOR_CAP_SINGLE_LVDS_18_INIT 0x00000000 /* RWI-V */ +#define NVC773_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVC773_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVC773_SOR_CAP_SINGLE_LVDS_24 1:1 /* RWIVF */ +#define NVC773_SOR_CAP_SINGLE_LVDS_24_INIT 0x00000000 /* RWI-V */ +#define NVC773_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVC773_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVC773_SOR_CAP_DUAL_LVDS_18 2:2 /* RWIVF */ +#define NVC773_SOR_CAP_DUAL_LVDS_18_INIT 0x00000000 /* RWI-V */ +#define NVC773_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVC773_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVC773_SOR_CAP_DUAL_LVDS_24 3:3 /* RWIVF */ +#define NVC773_SOR_CAP_DUAL_LVDS_24_INIT 0x00000000 /* RWI-V */ +#define NVC773_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVC773_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVC773_SOR_CAP_SINGLE_TMDS_A 8:8 /* RWIVF */ +#define NVC773_SOR_CAP_SINGLE_TMDS_A_INIT 0x00000000 /* RWI-V */ +#define NVC773_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* RW--V */ +#define NVC773_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* RW--V */ +#define NVC773_SOR_CAP_SINGLE_TMDS_B 9:9 /* RWIVF */ +#define NVC773_SOR_CAP_SINGLE_TMDS_B_INIT 0x00000000 /* RWI-V */ +#define NVC773_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* RW--V */ +#define NVC773_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* RW--V */ +#define NVC773_SOR_CAP_DUAL_TMDS 11:11 /* RWIVF */ +#define NVC773_SOR_CAP_DUAL_TMDS_INIT 0x00000000 /* RWI-V */ +#define NVC773_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* RW--V */ +#define NVC773_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* RW--V */ +#define NVC773_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* RWIVF */ +#define NVC773_SOR_CAP_DISPLAY_OVER_PCIE_INIT 0x00000000 /* RWI-V */ +#define NVC773_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* RW--V */ +#define NVC773_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* RW--V */ +#define NVC773_SOR_CAP_SDI 16:16 /* RWIVF */ +#define NVC773_SOR_CAP_SDI_INIT 0x00000000 /* RWI-V */ +#define NVC773_SOR_CAP_SDI_FALSE 0x00000000 /* RW--V */ +#define NVC773_SOR_CAP_SDI_TRUE 0x00000001 /* RW--V */ +#define NVC773_SOR_CAP_DP_A 24:24 /* RWIVF */ +#define NVC773_SOR_CAP_DP_A_INIT 0x00000000 /* RWI-V */ +#define NVC773_SOR_CAP_DP_A_FALSE 0x00000000 /* RW--V */ +#define NVC773_SOR_CAP_DP_A_TRUE 0x00000001 /* RW--V */ +#define NVC773_SOR_CAP_DP_B 25:25 /* RWIVF */ +#define NVC773_SOR_CAP_DP_B_INIT 0x00000000 /* RWI-V */ +#define NVC773_SOR_CAP_DP_B_FALSE 0x00000000 /* RW--V */ +#define NVC773_SOR_CAP_DP_B_TRUE 0x00000001 /* RW--V */ +#define NVC773_SOR_CAP_DP_INTERLACE 26:26 /* RWIVF */ +#define NVC773_SOR_CAP_DP_INTERLACE_INIT 0x00000000 /* RWI-V */ +#define NVC773_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* RW--V */ +#define NVC773_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* RW--V */ +#define NVC773_SOR_CAP_DP_8_LANES 27:27 /* RWIVF */ +#define NVC773_SOR_CAP_DP_8_LANES_INIT 0x00000000 /* RWI-V */ +#define NVC773_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* RW--V */ +#define NVC773_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* RW--V */ +#define NVC773_SOR_CAP_HDMI_FRL 28:28 /* RWIVF */ +#define NVC773_SOR_CAP_HDMI_FRL_INIT 0x00000000 /* RWI-V */ +#define NVC773_SOR_CAP_HDMI_FRL_FALSE 0x00000000 /* RW--V */ +#define NVC773_SOR_CAP_HDMI_FRL_TRUE 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA(i) (0x780+(i)*32) /* RW-4A */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA__SIZE_1 32 /* */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH 13:10 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT 16:16 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT 17:17 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT 18:18 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT 19:19 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT 20:20 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT 21:21 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT 22:22 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT 23:23 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT 24:24 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB(i) (0x784+(i)*32) /* RW-4A */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB__SIZE_1 32 /* */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION 4:0 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ 9:6 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR 12:10 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT 15:15 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC(i) (0x788+(i)*32) /* RW-4A */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC__SIZE_1 32 /* */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION 4:0 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGSZ 9:6 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGSZ_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGNR 12:10 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGNR_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT 15:15 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION 20:16 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP 21:21 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD(i) (0x78c+(i)*32) /* RW-4A */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD__SIZE_1 32 /* */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ 3:0 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR 6:4 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD 8:8 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT 9:9 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION 16:12 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION 20:17 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB 21:21 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA 22:22 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_TRUE 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_FALSE 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE(i) (0x790+(i)*32) /* RW-4A */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE__SIZE_1 32 /* */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION 4:0 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGSZ 9:6 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGSZ_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGNR 12:10 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGNR_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT 15:15 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION 20:16 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP 21:21 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPF(i) (0x794+(i)*32) /* RW-4A */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPF__SIZE_1 32 /* */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP_INIT 0x00000000 /* RWI-V */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */ +#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP_INIT 0x00000000 /* RWI-V */ +#define NVC773_SOR_CLK_CAP(i) (0x608+(i)*4) /* RW-4A */ +#define NVC773_SOR_CLK_CAP__SIZE_1 8 /* */ +#define NVC773_SOR_CLK_CAP_DP_MAX 7:0 /* RWIUF */ +#define NVC773_SOR_CLK_CAP_DP_MAX_INIT 0x00000051 /* RWI-V */ +#define NVC773_SOR_CLK_CAP_TMDS_MAX 23:16 /* RWIUF */ +#define NVC773_SOR_CLK_CAP_TMDS_MAX_INIT 0x0000003C /* RWI-V */ +#define NVC773_SOR_CLK_CAP_LVDS_MAX 31:24 /* RWIUF */ +#define NVC773_SOR_CLK_CAP_LVDS_MAX_INIT 0x00000000 /* RWI-V */ + +#ifdef __cplusplus +}; +#endif /* extern C */ +#endif //_clc773_h_ diff --git a/userspace/sdks/nv570/inc/class/clc77d.h b/userspace/sdks/nv570/inc/class/clc77d.h new file mode 100644 index 0000000..50bc709 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc77d.h @@ -0,0 +1,1372 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clC77d_h_ +#define _clC77d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC77D_CORE_CHANNEL_DMA (0x0000C77D) + +#define NV_DISP_NOTIFIER 0x00000000 +#define NV_DISP_NOTIFIER_SIZEOF 0x00000010 +#define NV_DISP_NOTIFIER__0 0x00000000 +#define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFIER__0_FIELD 8:8 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE 9:9 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001 +#define NV_DISP_NOTIFIER__0_R1 15:10 +#define NV_DISP_NOTIFIER__0_R2 23:16 +#define NV_DISP_NOTIFIER__0_R3 29:24 +#define NV_DISP_NOTIFIER__0_STATUS 31:30 +#define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002 +#define NV_DISP_NOTIFIER__1 0x00000001 +#define NV_DISP_NOTIFIER__1_R4 31:0 +#define NV_DISP_NOTIFIER__2 0x00000002 +#define NV_DISP_NOTIFIER__2_TIMESTAMP_LO 31:0 +#define NV_DISP_NOTIFIER__3 0x00000003 +#define NV_DISP_NOTIFIER__3_TIMESTAMP_HI 31:0 + + +// dma opcode instructions +#define NVC77D_DMA +#define NVC77D_DMA_OPCODE 31:29 +#define NVC77D_DMA_OPCODE_METHOD 0x00000000 +#define NVC77D_DMA_OPCODE_JUMP 0x00000001 +#define NVC77D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC77D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC77D_DMA_METHOD_COUNT 27:18 +#define NVC77D_DMA_METHOD_OFFSET 13:2 +#define NVC77D_DMA_DATA 31:0 +#define NVC77D_DMA_DATA_NOP 0x00000000 +#define NVC77D_DMA_JUMP_OFFSET 11:2 +#define NVC77D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// if cap SUPPORT_FLEXIBLE_WIN_MAPPING is FALSE, this define can be used to obtain which head a window is mapped to +#define NVC37D_WINDOW_MAPPED_TO_HEAD(w) ((w)>>1) +#define NVC37D_GET_VALID_WINDOWMASK_FOR_HEAD(h) ((1<<((h)*2)) | (1<<((h)*2+1))) + +// class methods +#define NVC77D_PUT (0x00000000) +#define NVC77D_PUT_PTR 9:0 +#define NVC77D_GET (0x00000004) +#define NVC77D_GET_PTR 9:0 +#define NVC77D_UPDATE (0x00000200) +#define NVC77D_UPDATE_SPECIAL_HANDLING 21:20 +#define NVC77D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NVC77D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NVC77D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NVC77D_UPDATE_SPECIAL_HANDLING_REASON 19:12 +#define NVC77D_UPDATE_INHIBIT_INTERRUPTS 24:24 +#define NVC77D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NVC77D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NVC77D_UPDATE_RELEASE_ELV 0:0 +#define NVC77D_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC77D_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC77D_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC77D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC77D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC77D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC77D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC77D_SET_CONTEXT_DMA_NOTIFIER (0x00000208) +#define NVC77D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NVC77D_SET_NOTIFIER_CONTROL (0x0000020C) +#define NVC77D_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC77D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC77D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC77D_SET_NOTIFIER_CONTROL_OFFSET 11:4 +#define NVC77D_SET_NOTIFIER_CONTROL_NOTIFY 12:12 +#define NVC77D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NVC77D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NVC77D_SET_CONTROL (0x00000210) +#define NVC77D_SET_CONTROL_FLIP_LOCK_PIN(i) ((i)+0):((i)+0) +#define NVC77D_SET_CONTROL_FLIP_LOCK_PIN__SIZE_1 4 +#define NVC77D_SET_CONTROL_FLIP_LOCK_PIN_DISABLE (0x00000000) +#define NVC77D_SET_CONTROL_FLIP_LOCK_PIN_ENABLE (0x00000001) +#define NVC77D_SET_CONTROL_FLIP_LOCK_PIN0 0:0 +#define NVC77D_SET_CONTROL_FLIP_LOCK_PIN0_DISABLE (0x00000000) +#define NVC77D_SET_CONTROL_FLIP_LOCK_PIN0_ENABLE (0x00000001) +#define NVC77D_SET_CONTROL_FLIP_LOCK_PIN1 1:1 +#define NVC77D_SET_CONTROL_FLIP_LOCK_PIN1_DISABLE (0x00000000) +#define NVC77D_SET_CONTROL_FLIP_LOCK_PIN1_ENABLE (0x00000001) +#define NVC77D_SET_CONTROL_FLIP_LOCK_PIN2 2:2 +#define NVC77D_SET_CONTROL_FLIP_LOCK_PIN2_DISABLE (0x00000000) +#define NVC77D_SET_CONTROL_FLIP_LOCK_PIN2_ENABLE (0x00000001) +#define NVC77D_SET_CONTROL_FLIP_LOCK_PIN3 3:3 +#define NVC77D_SET_CONTROL_FLIP_LOCK_PIN3_DISABLE (0x00000000) +#define NVC77D_SET_CONTROL_FLIP_LOCK_PIN3_ENABLE (0x00000001) +#define NVC77D_SET_INTERLOCK_FLAGS (0x00000218) +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+0):((i)+0) +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC77D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS (0x0000021C) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC77D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVC77D_GET_RG_SCAN_LINE(b) (0x00000220 + (b)*0x00000004) +#define NVC77D_GET_RG_SCAN_LINE_LINE 15:0 +#define NVC77D_GET_RG_SCAN_LINE_VBLANK 16:16 +#define NVC77D_GET_RG_SCAN_LINE_VBLANK_FALSE (0x00000000) +#define NVC77D_GET_RG_SCAN_LINE_VBLANK_TRUE (0x00000001) +#define NVC77D_SET_GET_BLANKING_CTRL(b) (0x00000240 + (b)*0x00000004) +#define NVC77D_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NVC77D_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NVC77D_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NVC77D_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NVC77D_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NVC77D_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) + +#define NVC77D_SOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NVC77D_SOR_SET_CONTROL_OWNER_MASK 7:0 +#define NVC77D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVC77D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVC77D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVC77D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVC77D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVC77D_SOR_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVC77D_SOR_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVC77D_SOR_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVC77D_SOR_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVC77D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NVC77D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NVC77D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NVC77D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NVC77D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NVC77D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NVC77D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NVC77D_SOR_SET_CONTROL_PROTOCOL_HDMI_FRL (0x0000000C) +#define NVC77D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NVC77D_SOR_SET_CONTROL_DE_SYNC_POLARITY 16:16 +#define NVC77D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC77D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC77D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NVC77D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NVC77D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NVC77D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NVC77D_SOR_SET_CUSTOM_REASON(a) (0x00000304 + (a)*0x00000020) +#define NVC77D_SOR_SET_CUSTOM_REASON_CODE 31:0 +#define NVC77D_SOR_SET_SW_SPARE_A(a) (0x00000308 + (a)*0x00000020) +#define NVC77D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NVC77D_SOR_SET_SW_SPARE_B(a) (0x0000030C + (a)*0x00000020) +#define NVC77D_SOR_SET_SW_SPARE_B_CODE 31:0 + +#define NVC77D_DSI_SET_CONTROL(a) (0x00000500 + (a)*0x00000020) +#define NVC77D_DSI_SET_CONTROL_OWNER_MASK 7:0 +#define NVC77D_DSI_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVC77D_DSI_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVC77D_DSI_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVC77D_DSI_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVC77D_DSI_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVC77D_DSI_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVC77D_DSI_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVC77D_DSI_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVC77D_DSI_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVC77D_DSI_SET_CUSTOM_REASON(a) (0x00000504 + (a)*0x00000020) +#define NVC77D_DSI_SET_CUSTOM_REASON_CODE 31:0 +#define NVC77D_DSI_SET_SW_SPARE_A(a) (0x00000508 + (a)*0x00000020) +#define NVC77D_DSI_SET_SW_SPARE_A_CODE 31:0 +#define NVC77D_DSI_SET_SW_SPARE_B(a) (0x0000050C + (a)*0x00000020) +#define NVC77D_DSI_SET_SW_SPARE_B_CODE 31:0 + +#define NVC77D_WINDOW_SET_CONTROL(a) (0x00001000 + (a)*0x00000080) +#define NVC77D_WINDOW_SET_CONTROL_OWNER 3:0 +#define NVC77D_WINDOW_SET_CONTROL_OWNER_HEAD(i) (0x00000000 +(i)) +#define NVC77D_WINDOW_SET_CONTROL_OWNER_HEAD__SIZE_1 8 +#define NVC77D_WINDOW_SET_CONTROL_OWNER_HEAD0 (0x00000000) +#define NVC77D_WINDOW_SET_CONTROL_OWNER_HEAD1 (0x00000001) +#define NVC77D_WINDOW_SET_CONTROL_OWNER_HEAD2 (0x00000002) +#define NVC77D_WINDOW_SET_CONTROL_OWNER_HEAD3 (0x00000003) +#define NVC77D_WINDOW_SET_CONTROL_OWNER_HEAD4 (0x00000004) +#define NVC77D_WINDOW_SET_CONTROL_OWNER_HEAD5 (0x00000005) +#define NVC77D_WINDOW_SET_CONTROL_OWNER_HEAD6 (0x00000006) +#define NVC77D_WINDOW_SET_CONTROL_OWNER_HEAD7 (0x00000007) +#define NVC77D_WINDOW_SET_CONTROL_OWNER_NONE (0x0000000F) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0x00000080) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a) (0x00001008 + (a)*0x00000080) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR(a) (0x0000100C + (a)*0x00000080) +#define NVC77D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVC77D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVC77D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a) (0x00001010 + (a)*0x00000080) +#define NVC77D_WINDOW_SET_WINDOW_USAGE_BOUNDS_MAX_PIXELS_FETCHED_PER_LINE 14:0 +#define NVC77D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED 16:16 +#define NVC77D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED 28:28 +#define NVC77D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS 22:20 +#define NVC77D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVC77D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED 24:24 +#define NVC77D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVC77D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED 30:30 +#define NVC77D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED_FALSE (0x00000000) +#define NVC77D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED_TRUE (0x00000001) + +#define NVC77D_HEAD_SET_PROCAMP(a) (0x00002000 + (a)*0x00000400) +#define NVC77D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NVC77D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NVC77D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NVC77D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NVC77D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003) +#define NVC77D_HEAD_SET_PROCAMP_CHROMA_LPF 3:3 +#define NVC77D_HEAD_SET_PROCAMP_CHROMA_LPF_DISABLE (0x00000000) +#define NVC77D_HEAD_SET_PROCAMP_CHROMA_LPF_ENABLE (0x00000001) +#define NVC77D_HEAD_SET_PROCAMP_CHROMA_DOWN_V 4:4 +#define NVC77D_HEAD_SET_PROCAMP_CHROMA_DOWN_V_DISABLE (0x00000000) +#define NVC77D_HEAD_SET_PROCAMP_CHROMA_DOWN_V_ENABLE (0x00000001) +#define NVC77D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 28:28 +#define NVC77D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NVC77D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00002004 + (a)*0x00000400) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 2:2 +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 3:3 +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 7:4 +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000000) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000001) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000002) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000003) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000004) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000005) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000006) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000007) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000008) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_444 (0x00000009) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444NP (0x0000000A) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 24:24 +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 23:12 +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN 31:26 +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN0 (0x00000000) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN1 (0x00000001) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN2 (0x00000002) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN3 (0x00000003) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN4 (0x00000004) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN5 (0x00000005) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN6 (0x00000006) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN7 (0x00000007) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN8 (0x00000008) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN9 (0x00000009) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN10 (0x0000000A) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN11 (0x0000000B) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN12 (0x0000000C) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN13 (0x0000000D) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN14 (0x0000000E) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN15 (0x0000000F) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN16 (0x00000010) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN17 (0x00000011) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN18 (0x00000012) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN19 (0x00000013) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN20 (0x00000014) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN21 (0x00000015) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN22 (0x00000016) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN23 (0x00000017) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN24 (0x00000018) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN25 (0x00000019) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN26 (0x0000001A) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN27 (0x0000001B) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN28 (0x0000001C) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN29 (0x0000001D) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN30 (0x0000001E) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN31 (0x0000001F) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_NONE (0x0000003F) +#define NVC77D_HEAD_SET_CONTROL(a) (0x00002008 + (a)*0x00000400) +#define NVC77D_HEAD_SET_CONTROL_STRUCTURE 1:0 +#define NVC77D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NVC77D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE 2:2 +#define NVC77D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_NORMAL (0x00000000) +#define NVC77D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000001) +#define NVC77D_HEAD_SET_CONTROL_YUV420PACKER 3:3 +#define NVC77D_HEAD_SET_CONTROL_YUV420PACKER_DISABLE (0x00000000) +#define NVC77D_HEAD_SET_CONTROL_YUV420PACKER_ENABLE (0x00000001) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 11:10 +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 8:4 +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 15:12 +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 23:22 +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 20:16 +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC77D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN 28:24 +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000001) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000002) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000003) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000004) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000005) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000006) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000007) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000008) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000009) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000B) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000C) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000D) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000E) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000F) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x00000010) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC77D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NVC77D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVC77D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVC77D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NVC77D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVC77D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVC77D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x0000200C + (a)*0x00000400) +#define NVC77D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NVC77D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NVC77D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC77D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC77D_HEAD_SET_PIXEL_REORDER_CONTROL(a) (0x00002010 + (a)*0x00000400) +#define NVC77D_HEAD_SET_PIXEL_REORDER_CONTROL_BANK_WIDTH 13:0 +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00002014 + (a)*0x00000400) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVC77D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVC77D_HEAD_SET_DITHER_CONTROL(a) (0x00002018 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NVC77D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC77D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC77D_HEAD_SET_DITHER_CONTROL_BITS 5:4 +#define NVC77D_HEAD_SET_DITHER_CONTROL_BITS_TO_6_BITS (0x00000000) +#define NVC77D_HEAD_SET_DITHER_CONTROL_BITS_TO_8_BITS (0x00000001) +#define NVC77D_HEAD_SET_DITHER_CONTROL_BITS_TO_10_BITS (0x00000002) +#define NVC77D_HEAD_SET_DITHER_CONTROL_BITS_TO_12_BITS (0x00000003) +#define NVC77D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE 2:2 +#define NVC77D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_DISABLE (0x00000000) +#define NVC77D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_ENABLE (0x00000001) +#define NVC77D_HEAD_SET_DITHER_CONTROL_MODE 10:8 +#define NVC77D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NVC77D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NVC77D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NVC77D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NVC77D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NVC77D_HEAD_SET_DITHER_CONTROL_MODE_ROUND (0x00000005) +#define NVC77D_HEAD_SET_DITHER_CONTROL_PHASE 13:12 +#define NVC77D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x0000201C + (a)*0x00000400) +#define NVC77D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 0:0 +#define NVC77D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NVC77D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NVC77D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING 4:4 +#define NVC77D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_DISABLE (0x00000000) +#define NVC77D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_ENABLE (0x00000001) +#define NVC77D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 9:8 +#define NVC77D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NVC77D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NVC77D_HEAD_SET_DISPLAY_ID(a,b) (0x00002020 + (a)*0x00000400 + (b)*0x00000004) +#define NVC77D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NVC77D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00002028 + (a)*0x00000400) +#define NVC77D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NVC77D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NVC77D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC77D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC77D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR(a) (0x0000202C + (a)*0x00000400) +#define NVC77D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVC77D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVC77D_HEAD_SET_HEAD_USAGE_BOUNDS(a) (0x00002030 + (a)*0x00000400) +#define NVC77D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR 2:0 +#define NVC77D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_NONE (0x00000000) +#define NVC77D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W32_H32 (0x00000001) +#define NVC77D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W64_H64 (0x00000002) +#define NVC77D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W128_H128 (0x00000003) +#define NVC77D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W256_H256 (0x00000004) +#define NVC77D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED 4:4 +#define NVC77D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_FALSE (0x00000000) +#define NVC77D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_TRUE (0x00000001) +#define NVC77D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS 14:12 +#define NVC77D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVC77D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVC77D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED 8:8 +#define NVC77D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC77D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVC77D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED 16:16 +#define NVC77D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED_FALSE (0x00000000) +#define NVC77D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED_TRUE (0x00000001) +#define NVC77D_HEAD_SET_HEAD_USAGE_BOUNDS_ELV_START 31:17 +#define NVC77D_HEAD_SET_STALL_LOCK(a) (0x00002034 + (a)*0x00000400) +#define NVC77D_HEAD_SET_STALL_LOCK_ENABLE 0:0 +#define NVC77D_HEAD_SET_STALL_LOCK_ENABLE_FALSE (0x00000000) +#define NVC77D_HEAD_SET_STALL_LOCK_ENABLE_TRUE (0x00000001) +#define NVC77D_HEAD_SET_STALL_LOCK_MODE 2:2 +#define NVC77D_HEAD_SET_STALL_LOCK_MODE_CONTINUOUS (0x00000000) +#define NVC77D_HEAD_SET_STALL_LOCK_MODE_ONE_SHOT (0x00000001) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN 8:4 +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC77D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC77D_HEAD_SET_STALL_LOCK_UNSTALL_MODE 12:12 +#define NVC77D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_CRASH_LOCK (0x00000000) +#define NVC77D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_LINE_LOCK (0x00000001) +#define NVC77D_HEAD_SET_STALL_LOCK_TEPOLARITY 14:14 +#define NVC77D_HEAD_SET_STALL_LOCK_TEPOLARITY_POSITIVE_TRUE (0x00000000) +#define NVC77D_HEAD_SET_STALL_LOCK_TEPOLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC77D_HEAD_SET_STALL_LOCK_UNSTALL_SYNC_ADVANCE 25:16 +#define NVC77D_HEAD_SET_LOCK_CHAIN(a) (0x00002044 + (a)*0x00000400) +#define NVC77D_HEAD_SET_LOCK_CHAIN_POSITION 3:0 +#define NVC77D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x00002048 + (a)*0x00000400) +#define NVC77D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NVC77D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NVC77D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x0000204C + (a)*0x00000400) +#define NVC77D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NVC77D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NVC77D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x00002058 + (a)*0x00000400) +#define NVC77D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NVC77D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NVC77D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x0000205C + (a)*0x00000400) +#define NVC77D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NVC77D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NVC77D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000400) +#define NVC77D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NVC77D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NVC77D_HEAD_SET_RASTER_SYNC_END(a) (0x00002068 + (a)*0x00000400) +#define NVC77D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NVC77D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NVC77D_HEAD_SET_RASTER_BLANK_END(a) (0x0000206C + (a)*0x00000400) +#define NVC77D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NVC77D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NVC77D_HEAD_SET_RASTER_BLANK_START(a) (0x00002070 + (a)*0x00000400) +#define NVC77D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NVC77D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NVC77D_HEAD_SET_OVERSCAN_COLOR(a) (0x00002078 + (a)*0x00000400) +#define NVC77D_HEAD_SET_OVERSCAN_COLOR_RED_CR 9:0 +#define NVC77D_HEAD_SET_OVERSCAN_COLOR_GREEN_Y 19:10 +#define NVC77D_HEAD_SET_OVERSCAN_COLOR_BLUE_CB 29:20 +#define NVC77D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR(a) (0x0000207C + (a)*0x00000400) +#define NVC77D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_RED_CR 9:0 +#define NVC77D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_GREEN_Y 19:10 +#define NVC77D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_BLUE_CB 29:20 +#define NVC77D_HEAD_SET_HDMI_CTRL(a) (0x00002080 + (a)*0x00000400) +#define NVC77D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NVC77D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NVC77D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NVC77D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NVC77D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NVC77D_HEAD_SET_CONTEXT_DMA_CURSOR(a,b) (0x00002088 + (a)*0x00000400 + (b)*0x00000004) +#define NVC77D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0 +#define NVC77D_HEAD_SET_OFFSET_CURSOR(a,b) (0x00002090 + (a)*0x00000400 + (b)*0x00000004) +#define NVC77D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0 +#define NVC77D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x00002098 + (a)*0x00000400) +#define NVC77D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 0:0 +#define NVC77D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NVC77D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NVC77D_HEAD_SET_CONTROL_CURSOR(a) (0x0000209C + (a)*0x00000400) +#define NVC77D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NVC77D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NVC77D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NVC77D_HEAD_SET_CONTROL_CURSOR_FORMAT 7:0 +#define NVC77D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC77D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC77D_HEAD_SET_CONTROL_CURSOR_SIZE 9:8 +#define NVC77D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NVC77D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NVC77D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NVC77D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NVC77D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 19:12 +#define NVC77D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 27:20 +#define NVC77D_HEAD_SET_CONTROL_CURSOR_COMPOSITION(a) (0x000020A0 + (a)*0x00000400) +#define NVC77D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_K1 7:0 +#define NVC77D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT 11:8 +#define NVC77D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC77D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC77D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT 15:12 +#define NVC77D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_ZERO (0x00000000) +#define NVC77D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC77D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC77D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE 16:16 +#define NVC77D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_BLEND (0x00000000) +#define NVC77D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_XOR (0x00000001) +#define NVC77D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS 20:20 +#define NVC77D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_DISABLE (0x00000000) +#define NVC77D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_ENABLE (0x00000001) +#define NVC77D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00002180 + (a)*0x00000400) +#define NVC77D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NVC77D_HEAD_SET_CRC_CONTROL(a) (0x00002184 + (a)*0x00000400) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 5:0 +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_0 (0x00000000) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_1 (0x00000001) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_2 (0x00000002) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_3 (0x00000003) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_4 (0x00000004) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_5 (0x00000005) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_6 (0x00000006) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_7 (0x00000007) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_8 (0x00000008) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_9 (0x00000009) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_10 (0x0000000A) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_11 (0x0000000B) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_12 (0x0000000C) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_13 (0x0000000D) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_14 (0x0000000E) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_15 (0x0000000F) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_16 (0x00000010) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_17 (0x00000011) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_18 (0x00000012) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_19 (0x00000013) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_20 (0x00000014) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_21 (0x00000015) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_22 (0x00000016) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_23 (0x00000017) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_24 (0x00000018) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_25 (0x00000019) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_26 (0x0000001A) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_27 (0x0000001B) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_28 (0x0000001C) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_29 (0x0000001D) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_30 (0x0000001E) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_31 (0x0000001F) +#define NVC77D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000020) +#define NVC77D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 8:8 +#define NVC77D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NVC77D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NVC77D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC 19:12 +#define NVC77D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_NONE (0x00000000) +#define NVC77D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SF (0x00000030) +#define NVC77D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC77D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR__SIZE_1 8 +#define NVC77D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR0 (0x00000050) +#define NVC77D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR1 (0x00000051) +#define NVC77D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR2 (0x00000052) +#define NVC77D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR3 (0x00000053) +#define NVC77D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR4 (0x00000054) +#define NVC77D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR5 (0x00000055) +#define NVC77D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR6 (0x00000056) +#define NVC77D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR7 (0x00000057) +#define NVC77D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC 27:20 +#define NVC77D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_NONE (0x00000000) +#define NVC77D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SF (0x00000030) +#define NVC77D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC77D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR__SIZE_1 8 +#define NVC77D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR0 (0x00000050) +#define NVC77D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR1 (0x00000051) +#define NVC77D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR2 (0x00000052) +#define NVC77D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR3 (0x00000053) +#define NVC77D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR4 (0x00000054) +#define NVC77D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR5 (0x00000055) +#define NVC77D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR6 (0x00000056) +#define NVC77D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR7 (0x00000057) +#define NVC77D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 9:9 +#define NVC77D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NVC77D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NVC77D_HEAD_SET_PRESENT_CONTROL(a) (0x0000218C + (a)*0x00000400) +#define NVC77D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 0:0 +#define NVC77D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NVC77D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NVC77D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NVC77D_HEAD_SET_SW_SPARE_A(a) (0x00002194 + (a)*0x00000400) +#define NVC77D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NVC77D_HEAD_SET_SW_SPARE_B(a) (0x00002198 + (a)*0x00000400) +#define NVC77D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NVC77D_HEAD_SET_SW_SPARE_C(a) (0x0000219C + (a)*0x00000400) +#define NVC77D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NVC77D_HEAD_SET_SW_SPARE_D(a) (0x000021A0 + (a)*0x00000400) +#define NVC77D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NVC77D_HEAD_SET_DISPLAY_RATE(a) (0x000021A8 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DISPLAY_RATE_RUN_MODE 0:0 +#define NVC77D_HEAD_SET_DISPLAY_RATE_RUN_MODE_CONTINUOUS (0x00000000) +#define NVC77D_HEAD_SET_DISPLAY_RATE_RUN_MODE_ONE_SHOT (0x00000001) +#define NVC77D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_INTERVAL 25:4 +#define NVC77D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH 2:2 +#define NVC77D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_DISABLE (0x00000000) +#define NVC77D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_ENABLE (0x00000001) +#define NVC77D_HEAD_SET_CONTEXT_DMA_RG_REL_SEMAPHORE(a,b) (0x000021AC + (a)*0x00000400 + (b)*0x00000004) +#define NVC77D_HEAD_SET_CONTEXT_DMA_RG_REL_SEMAPHORE_HANDLE 31:0 +#define NVC77D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL(a,b) (0x000021CC + (a)*0x00000400 + (b)*0x00000004) +#define NVC77D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_OFFSET 7:0 +#define NVC77D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVC77D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVC77D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVC77D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE 14:14 +#define NVC77D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE_WRITE (0x00000000) +#define NVC77D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC77D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE 10:10 +#define NVC77D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE_ONE_TIME (0x00000000) +#define NVC77D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE_CONTINUOUS (0x00000001) +#define NVC77D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RASTER_LINE 30:16 +#define NVC77D_HEAD_SET_RG_REL_SEMAPHORE_VALUE(a,b) (0x000021EC + (a)*0x00000400 + (b)*0x00000004) +#define NVC77D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_VALUE 31:0 +#define NVC77D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE(a) (0x00002214 + (a)*0x00000400) +#define NVC77D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVC77D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVC77D_HEAD_SET_MIN_FRAME_IDLE(a) (0x00002218 + (a)*0x00000400) +#define NVC77D_HEAD_SET_MIN_FRAME_IDLE_LEADING_RASTER_LINES 14:0 +#define NVC77D_HEAD_SET_MIN_FRAME_IDLE_TRAILING_RASTER_LINES 30:16 +#define NVC77D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED(a) (0x00002220 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED_ALPHA 7:0 +#define NVC77D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED_RED 31:16 +#define NVC77D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE(a) (0x00002224 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE_GREEN 15:0 +#define NVC77D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE_BLUE 31:16 +#define NVC77D_HEAD_SET_CURSOR_COLOR_NORM_SCALE(a) (0x00002228 + (a)*0x00000400) +#define NVC77D_HEAD_SET_CURSOR_COLOR_NORM_SCALE_VALUE 15:0 +#define NVC77D_HEAD_SET_XOR_BLEND_FACTOR(a) (0x0000222C + (a)*0x00000400) +#define NVC77D_HEAD_SET_XOR_BLEND_FACTOR_LOG2PEAK_LUMINANCE 3:0 +#define NVC77D_HEAD_SET_XOR_BLEND_FACTOR_S1 16:4 +#define NVC77D_HEAD_SET_XOR_BLEND_FACTOR_S2 30:18 +#define NVC77D_HEAD_SET_CLAMP_RANGE_GREEN(a) (0x00002238 + (a)*0x00000400) +#define NVC77D_HEAD_SET_CLAMP_RANGE_GREEN_LOW 11:0 +#define NVC77D_HEAD_SET_CLAMP_RANGE_GREEN_HIGH 27:16 +#define NVC77D_HEAD_SET_CLAMP_RANGE_RED_BLUE(a) (0x0000223C + (a)*0x00000400) +#define NVC77D_HEAD_SET_CLAMP_RANGE_RED_BLUE_LOW 11:0 +#define NVC77D_HEAD_SET_CLAMP_RANGE_RED_BLUE_HIGH 27:16 +#define NVC77D_HEAD_SET_OCSC0CONTROL(a) (0x00002240 + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC0CONTROL_ENABLE 0:0 +#define NVC77D_HEAD_SET_OCSC0CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC77D_HEAD_SET_OCSC0CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC77D_HEAD_SET_OCSC0COEFFICIENT_C00(a) (0x00002244 + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC0COEFFICIENT_C00_VALUE 20:0 +#define NVC77D_HEAD_SET_OCSC0COEFFICIENT_C01(a) (0x00002248 + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC0COEFFICIENT_C01_VALUE 20:0 +#define NVC77D_HEAD_SET_OCSC0COEFFICIENT_C02(a) (0x0000224C + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC0COEFFICIENT_C02_VALUE 20:0 +#define NVC77D_HEAD_SET_OCSC0COEFFICIENT_C03(a) (0x00002250 + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC0COEFFICIENT_C03_VALUE 20:0 +#define NVC77D_HEAD_SET_OCSC0COEFFICIENT_C10(a) (0x00002254 + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC0COEFFICIENT_C10_VALUE 20:0 +#define NVC77D_HEAD_SET_OCSC0COEFFICIENT_C11(a) (0x00002258 + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC0COEFFICIENT_C11_VALUE 20:0 +#define NVC77D_HEAD_SET_OCSC0COEFFICIENT_C12(a) (0x0000225C + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC0COEFFICIENT_C12_VALUE 20:0 +#define NVC77D_HEAD_SET_OCSC0COEFFICIENT_C13(a) (0x00002260 + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC0COEFFICIENT_C13_VALUE 20:0 +#define NVC77D_HEAD_SET_OCSC0COEFFICIENT_C20(a) (0x00002264 + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC0COEFFICIENT_C20_VALUE 20:0 +#define NVC77D_HEAD_SET_OCSC0COEFFICIENT_C21(a) (0x00002268 + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC0COEFFICIENT_C21_VALUE 20:0 +#define NVC77D_HEAD_SET_OCSC0COEFFICIENT_C22(a) (0x0000226C + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC0COEFFICIENT_C22_VALUE 20:0 +#define NVC77D_HEAD_SET_OCSC0COEFFICIENT_C23(a) (0x00002270 + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC0COEFFICIENT_C23_VALUE 20:0 +#define NVC77D_HEAD_SET_OLUT_CONTROL(a) (0x00002280 + (a)*0x00000400) +#define NVC77D_HEAD_SET_OLUT_CONTROL_INTERPOLATE 0:0 +#define NVC77D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC77D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC77D_HEAD_SET_OLUT_CONTROL_MIRROR 1:1 +#define NVC77D_HEAD_SET_OLUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC77D_HEAD_SET_OLUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC77D_HEAD_SET_OLUT_CONTROL_MODE 3:2 +#define NVC77D_HEAD_SET_OLUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVC77D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVC77D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVC77D_HEAD_SET_OLUT_CONTROL_SIZE 18:8 +#define NVC77D_HEAD_SET_OLUT_FP_NORM_SCALE(a) (0x00002284 + (a)*0x00000400) +#define NVC77D_HEAD_SET_OLUT_FP_NORM_SCALE_VALUE 31:0 +#define NVC77D_HEAD_SET_CONTEXT_DMA_OLUT(a) (0x00002288 + (a)*0x00000400) +#define NVC77D_HEAD_SET_CONTEXT_DMA_OLUT_HANDLE 31:0 +#define NVC77D_HEAD_SET_OFFSET_OLUT(a) (0x0000228C + (a)*0x00000400) +#define NVC77D_HEAD_SET_OFFSET_OLUT_ORIGIN 31:0 +#define NVC77D_HEAD_SET_OCSC1CONTROL(a) (0x0000229C + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC1CONTROL_ENABLE 0:0 +#define NVC77D_HEAD_SET_OCSC1CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC77D_HEAD_SET_OCSC1CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC77D_HEAD_SET_OCSC1COEFFICIENT_C00(a) (0x000022A0 + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC1COEFFICIENT_C00_VALUE 20:0 +#define NVC77D_HEAD_SET_OCSC1COEFFICIENT_C01(a) (0x000022A4 + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC1COEFFICIENT_C01_VALUE 20:0 +#define NVC77D_HEAD_SET_OCSC1COEFFICIENT_C02(a) (0x000022A8 + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC1COEFFICIENT_C02_VALUE 20:0 +#define NVC77D_HEAD_SET_OCSC1COEFFICIENT_C03(a) (0x000022AC + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC1COEFFICIENT_C03_VALUE 20:0 +#define NVC77D_HEAD_SET_OCSC1COEFFICIENT_C10(a) (0x000022B0 + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC1COEFFICIENT_C10_VALUE 20:0 +#define NVC77D_HEAD_SET_OCSC1COEFFICIENT_C11(a) (0x000022B4 + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC1COEFFICIENT_C11_VALUE 20:0 +#define NVC77D_HEAD_SET_OCSC1COEFFICIENT_C12(a) (0x000022B8 + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC1COEFFICIENT_C12_VALUE 20:0 +#define NVC77D_HEAD_SET_OCSC1COEFFICIENT_C13(a) (0x000022BC + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC1COEFFICIENT_C13_VALUE 20:0 +#define NVC77D_HEAD_SET_OCSC1COEFFICIENT_C20(a) (0x000022C0 + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC1COEFFICIENT_C20_VALUE 20:0 +#define NVC77D_HEAD_SET_OCSC1COEFFICIENT_C21(a) (0x000022C4 + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC1COEFFICIENT_C21_VALUE 20:0 +#define NVC77D_HEAD_SET_OCSC1COEFFICIENT_C22(a) (0x000022C8 + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC1COEFFICIENT_C22_VALUE 20:0 +#define NVC77D_HEAD_SET_OCSC1COEFFICIENT_C23(a) (0x000022CC + (a)*0x00000400) +#define NVC77D_HEAD_SET_OCSC1COEFFICIENT_C23_VALUE 20:0 +#define NVC77D_HEAD_SET_TILE_POSITION(a) (0x000022D0 + (a)*0x00000400) +#define NVC77D_HEAD_SET_TILE_POSITION_X 2:0 +#define NVC77D_HEAD_SET_TILE_POSITION_Y 6:4 +#define NVC77D_HEAD_SET_DSC_CONTROL(a) (0x000022D4 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_CONTROL_ENABLE 0:0 +#define NVC77D_HEAD_SET_DSC_CONTROL_ENABLE_FALSE (0x00000000) +#define NVC77D_HEAD_SET_DSC_CONTROL_ENABLE_TRUE (0x00000001) +#define NVC77D_HEAD_SET_DSC_CONTROL_MODE 2:1 +#define NVC77D_HEAD_SET_DSC_CONTROL_MODE_SINGLE (0x00000000) +#define NVC77D_HEAD_SET_DSC_CONTROL_MODE_DUAL (0x00000001) +#define NVC77D_HEAD_SET_DSC_CONTROL_MODE_QUAD (0x00000002) +#define NVC77D_HEAD_SET_DSC_CONTROL_AUTO_RESET 3:3 +#define NVC77D_HEAD_SET_DSC_CONTROL_AUTO_RESET_DISABLE (0x00000000) +#define NVC77D_HEAD_SET_DSC_CONTROL_AUTO_RESET_ENABLE (0x00000001) +#define NVC77D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION 4:4 +#define NVC77D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION_DISABLE (0x00000000) +#define NVC77D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION_ENABLE (0x00000001) +#define NVC77D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET 5:5 +#define NVC77D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET_FALSE (0x00000000) +#define NVC77D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET_TRUE (0x00000001) +#define NVC77D_HEAD_SET_DSC_CONTROL_FLATNESS_DET_THRESH 15:6 +#define NVC77D_HEAD_SET_DSC_PPS_CONTROL(a) (0x000022D8 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_CONTROL_ENABLE 0:0 +#define NVC77D_HEAD_SET_DSC_PPS_CONTROL_ENABLE_FALSE (0x00000000) +#define NVC77D_HEAD_SET_DSC_PPS_CONTROL_ENABLE_TRUE (0x00000001) +#define NVC77D_HEAD_SET_DSC_PPS_CONTROL_LOCATION 1:1 +#define NVC77D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_VSYNC (0x00000000) +#define NVC77D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_VBLANK (0x00000001) +#define NVC77D_HEAD_SET_DSC_PPS_CONTROL_SIZE 9:2 +#define NVC77D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY 10:10 +#define NVC77D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVC77D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY_ONCE (0x00000001) +#define NVC77D_HEAD_SET_DSC_PPS_HEAD(a) (0x000022DC + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_HEAD_BYTE0 7:0 +#define NVC77D_HEAD_SET_DSC_PPS_HEAD_BYTE1 15:8 +#define NVC77D_HEAD_SET_DSC_PPS_HEAD_BYTE2 23:16 +#define NVC77D_HEAD_SET_DSC_PPS_HEAD_BYTE3 31:24 +#define NVC77D_HEAD_SET_DSC_PPS_DATA0(a) (0x000022E0 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA0_DSC_VERSION_MINOR 3:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA0_DSC_VERSION_MAJOR 7:4 +#define NVC77D_HEAD_SET_DSC_PPS_DATA0_PPS_IDENTIFIER 15:8 +#define NVC77D_HEAD_SET_DSC_PPS_DATA0_RESERVED 23:16 +#define NVC77D_HEAD_SET_DSC_PPS_DATA0_LINEBUF_DEPTH 27:24 +#define NVC77D_HEAD_SET_DSC_PPS_DATA0_BITS_PER_COMPONENT 31:28 +#define NVC77D_HEAD_SET_DSC_PPS_DATA1(a) (0x000022E4 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA1_BITS_PER_PIXEL_HIGH 1:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA1_VBR_ENABLE 2:2 +#define NVC77D_HEAD_SET_DSC_PPS_DATA1_SIMPLE422 3:3 +#define NVC77D_HEAD_SET_DSC_PPS_DATA1_CONVERT_RGB 4:4 +#define NVC77D_HEAD_SET_DSC_PPS_DATA1_BLOCK_PRED_ENABLE 5:5 +#define NVC77D_HEAD_SET_DSC_PPS_DATA1_RESERVED 7:6 +#define NVC77D_HEAD_SET_DSC_PPS_DATA1_BITS_PER_PIXEL_LOW 15:8 +#define NVC77D_HEAD_SET_DSC_PPS_DATA1_PIC_HEIGHT_HIGH 23:16 +#define NVC77D_HEAD_SET_DSC_PPS_DATA1_PIC_HEIGHT_LOW 31:24 +#define NVC77D_HEAD_SET_DSC_PPS_DATA2(a) (0x000022E8 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA2_PIC_WIDTH_HIGH 7:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA2_PIC_WIDTH_LOW 15:8 +#define NVC77D_HEAD_SET_DSC_PPS_DATA2_SLICE_HEIGHT_HIGH 23:16 +#define NVC77D_HEAD_SET_DSC_PPS_DATA2_SLICE_HEIGHT_LOW 31:24 +#define NVC77D_HEAD_SET_DSC_PPS_DATA3(a) (0x000022EC + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA3_SLICE_WIDTH_HIGH 7:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA3_SLICE_WIDTH_LOW 15:8 +#define NVC77D_HEAD_SET_DSC_PPS_DATA3_CHUNK_SIZE_HIGH 23:16 +#define NVC77D_HEAD_SET_DSC_PPS_DATA3_CHUNK_SIZE_LOW 31:24 +#define NVC77D_HEAD_SET_DSC_PPS_DATA4(a) (0x000022F0 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA4_INITIAL_XMIT_DELAY_HIGH 1:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA4_RESERVED 7:2 +#define NVC77D_HEAD_SET_DSC_PPS_DATA4_INITIAL_XMIT_DELAY_LOW 15:8 +#define NVC77D_HEAD_SET_DSC_PPS_DATA4_INITIAL_DEC_DELAY_HIGH 23:16 +#define NVC77D_HEAD_SET_DSC_PPS_DATA4_INITIAL_DEC_DELAY_LOW 31:24 +#define NVC77D_HEAD_SET_DSC_PPS_DATA5(a) (0x000022F4 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA5_RESERVED0 7:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA5_INITIAL_SCALE_VALUE 13:8 +#define NVC77D_HEAD_SET_DSC_PPS_DATA5_RESERVED1 15:14 +#define NVC77D_HEAD_SET_DSC_PPS_DATA5_SCALE_INCREMENT_INTERVAL_HIGH 23:16 +#define NVC77D_HEAD_SET_DSC_PPS_DATA5_SCALE_INCREMENT_INTERVAL_LOW 31:24 +#define NVC77D_HEAD_SET_DSC_PPS_DATA6(a) (0x000022F8 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA6_SCALE_DECREMENT_INTERVAL_HIGH 3:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA6_RESERVED0 7:4 +#define NVC77D_HEAD_SET_DSC_PPS_DATA6_SCALE_DECREMENT_INTERVAL_LOW 15:8 +#define NVC77D_HEAD_SET_DSC_PPS_DATA6_RESERVED1 23:16 +#define NVC77D_HEAD_SET_DSC_PPS_DATA6_FIRST_LINE_BPG_OFFSET 28:24 +#define NVC77D_HEAD_SET_DSC_PPS_DATA6_RESERVED2 31:29 +#define NVC77D_HEAD_SET_DSC_PPS_DATA7(a) (0x000022FC + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA7_NFL_BPG_OFFSET_HIGH 7:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA7_NFL_BPG_OFFSET_LOW 15:8 +#define NVC77D_HEAD_SET_DSC_PPS_DATA7_SLICE_BPG_OFFSET_HIGH 23:16 +#define NVC77D_HEAD_SET_DSC_PPS_DATA7_SLICE_BPG_OFFSET_LOW 31:24 +#define NVC77D_HEAD_SET_DSC_PPS_DATA8(a) (0x00002300 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA8_INITIAL_OFFSET_HIGH 7:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA8_INITIAL_OFFSET_LOW 15:8 +#define NVC77D_HEAD_SET_DSC_PPS_DATA8_FINAL_OFFSET_HIGH 23:16 +#define NVC77D_HEAD_SET_DSC_PPS_DATA8_FINAL_OFFSET_LOW 31:24 +#define NVC77D_HEAD_SET_DSC_PPS_DATA9(a) (0x00002304 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA9_FLATNESS_MIN_QP 4:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA9_RESERVED0 7:5 +#define NVC77D_HEAD_SET_DSC_PPS_DATA9_FLATNESS_MAX_QP 12:8 +#define NVC77D_HEAD_SET_DSC_PPS_DATA9_RESERVED1 15:13 +#define NVC77D_HEAD_SET_DSC_PPS_DATA9_RC_MODEL_SIZE_HIGH 23:16 +#define NVC77D_HEAD_SET_DSC_PPS_DATA9_RC_MODEL_SIZE_LOW 31:24 +#define NVC77D_HEAD_SET_DSC_PPS_DATA10(a) (0x00002308 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA10_RC_EDGE_FACTOR 3:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA10_RESERVED0 7:4 +#define NVC77D_HEAD_SET_DSC_PPS_DATA10_RC_QUANT_INCR_LIMIT0 12:8 +#define NVC77D_HEAD_SET_DSC_PPS_DATA10_RESERVED1 15:13 +#define NVC77D_HEAD_SET_DSC_PPS_DATA10_RC_QUANT_INCR_LIMIT1 20:16 +#define NVC77D_HEAD_SET_DSC_PPS_DATA10_RESERVED2 23:21 +#define NVC77D_HEAD_SET_DSC_PPS_DATA10_RC_TGT_OFFSET_LO 27:24 +#define NVC77D_HEAD_SET_DSC_PPS_DATA10_RC_TGT_OFFSET_HI 31:28 +#define NVC77D_HEAD_SET_DSC_PPS_DATA11(a) (0x0000230C + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH0 7:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH1 15:8 +#define NVC77D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH2 23:16 +#define NVC77D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH3 31:24 +#define NVC77D_HEAD_SET_DSC_PPS_DATA12(a) (0x00002310 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH4 7:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH5 15:8 +#define NVC77D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH6 23:16 +#define NVC77D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH7 31:24 +#define NVC77D_HEAD_SET_DSC_PPS_DATA13(a) (0x00002314 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH8 7:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH9 15:8 +#define NVC77D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH10 23:16 +#define NVC77D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH11 31:24 +#define NVC77D_HEAD_SET_DSC_PPS_DATA14(a) (0x00002318 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA14_RC_BUF_THRESH12 7:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA14_RC_BUF_THRESH13 15:8 +#define NVC77D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MAX_QP_HIGH0 18:16 +#define NVC77D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MIN_QP0 23:19 +#define NVC77D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_BPG_OFFSET0 29:24 +#define NVC77D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MAX_QP_LOW0 31:30 +#define NVC77D_HEAD_SET_DSC_PPS_DATA15(a) (0x0000231C + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_HIGH1 2:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MIN_QP1 7:3 +#define NVC77D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_BPG_OFFSET1 13:8 +#define NVC77D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_LOW1 15:14 +#define NVC77D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_HIGH2 18:16 +#define NVC77D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MIN_QP2 23:19 +#define NVC77D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_BPG_OFFSET2 29:24 +#define NVC77D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_LOW2 31:30 +#define NVC77D_HEAD_SET_DSC_PPS_DATA16(a) (0x00002320 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_HIGH3 2:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MIN_QP3 7:3 +#define NVC77D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_BPG_OFFSET3 13:8 +#define NVC77D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_LOW3 15:14 +#define NVC77D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_HIGH4 18:16 +#define NVC77D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MIN_QP4 23:19 +#define NVC77D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_BPG_OFFSET4 29:24 +#define NVC77D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_LOW4 31:30 +#define NVC77D_HEAD_SET_DSC_PPS_DATA17(a) (0x00002324 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_HIGH5 2:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MIN_QP5 7:3 +#define NVC77D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_BPG_OFFSET5 13:8 +#define NVC77D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_LOW5 15:14 +#define NVC77D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_HIGH6 18:16 +#define NVC77D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MIN_QP6 23:19 +#define NVC77D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_BPG_OFFSET6 29:24 +#define NVC77D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_LOW6 31:30 +#define NVC77D_HEAD_SET_DSC_PPS_DATA18(a) (0x00002328 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_HIGH7 2:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MIN_QP7 7:3 +#define NVC77D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_BPG_OFFSET7 13:8 +#define NVC77D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_LOW7 15:14 +#define NVC77D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_HIGH8 18:16 +#define NVC77D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MIN_QP8 23:19 +#define NVC77D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_BPG_OFFSET8 29:24 +#define NVC77D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_LOW8 31:30 +#define NVC77D_HEAD_SET_DSC_PPS_DATA19(a) (0x0000232C + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_HIGH9 2:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MIN_QP9 7:3 +#define NVC77D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_BPG_OFFSET9 13:8 +#define NVC77D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_LOW9 15:14 +#define NVC77D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_HIGH10 18:16 +#define NVC77D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MIN_QP10 23:19 +#define NVC77D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_BPG_OFFSET10 29:24 +#define NVC77D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_LOW10 31:30 +#define NVC77D_HEAD_SET_DSC_PPS_DATA20(a) (0x00002330 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_HIGH11 2:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MIN_QP11 7:3 +#define NVC77D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_BPG_OFFSET11 13:8 +#define NVC77D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_LOW11 15:14 +#define NVC77D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_HIGH12 18:16 +#define NVC77D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MIN_QP12 23:19 +#define NVC77D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_BPG_OFFSET12 29:24 +#define NVC77D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_LOW12 31:30 +#define NVC77D_HEAD_SET_DSC_PPS_DATA21(a) (0x00002334 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_HIGH13 2:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MIN_QP13 7:3 +#define NVC77D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_BPG_OFFSET13 13:8 +#define NVC77D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_LOW13 15:14 +#define NVC77D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_HIGH14 18:16 +#define NVC77D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MIN_QP14 23:19 +#define NVC77D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_BPG_OFFSET14 29:24 +#define NVC77D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_LOW14 31:30 +#define NVC77D_HEAD_SET_DSC_PPS_DATA22(a) (0x00002338 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA22_NATIVE422 0:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA22_NATIVE420 1:1 +#define NVC77D_HEAD_SET_DSC_PPS_DATA22_RESERVED0 7:2 +#define NVC77D_HEAD_SET_DSC_PPS_DATA22_SECOND_LINE_BPG_OFFSET 12:8 +#define NVC77D_HEAD_SET_DSC_PPS_DATA22_RESERVED1 15:13 +#define NVC77D_HEAD_SET_DSC_PPS_DATA22_NSL_BPG_OFFSET_HIGH 23:16 +#define NVC77D_HEAD_SET_DSC_PPS_DATA22_NSL_BPG_OFFSETLOW 31:24 +#define NVC77D_HEAD_SET_DSC_PPS_DATA23(a) (0x0000233C + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA23_SECOND_LINE_OFFSET_ADJ_HIGH 7:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA23_SECOND_LINE_OFFSET_ADJ_LOW 15:8 +#define NVC77D_HEAD_SET_DSC_PPS_DATA23_RESERVED 31:16 +#define NVC77D_HEAD_SET_DSC_PPS_DATA24(a) (0x00002340 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA24_RESERVED 31:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA25(a) (0x00002344 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA25_RESERVED 31:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA26(a) (0x00002348 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA26_RESERVED 31:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA27(a) (0x0000234C + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA27_RESERVED 31:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA28(a) (0x00002350 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA28_RESERVED 31:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA29(a) (0x00002354 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA29_RESERVED 31:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA30(a) (0x00002358 + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA30_RESERVED 31:0 +#define NVC77D_HEAD_SET_DSC_PPS_DATA31(a) (0x0000235C + (a)*0x00000400) +#define NVC77D_HEAD_SET_DSC_PPS_DATA31_RESERVED 31:0 +#define NVC77D_HEAD_SET_RG_MERGE(a) (0x00002360 + (a)*0x00000400) +#define NVC77D_HEAD_SET_RG_MERGE_MODE 1:0 +#define NVC77D_HEAD_SET_RG_MERGE_MODE_DISABLE (0x00000000) +#define NVC77D_HEAD_SET_RG_MERGE_MODE_SETUP (0x00000001) +#define NVC77D_HEAD_SET_RG_MERGE_MODE_MASTER (0x00000002) +#define NVC77D_HEAD_SET_RG_MERGE_MODE_SLAVE (0x00000003) +#define NVC77D_HEAD_SET_RASTER_HBLANK_DELAY(a) (0x00002364 + (a)*0x00000400) +#define NVC77D_HEAD_SET_RASTER_HBLANK_DELAY_BLANK_START 15:0 +#define NVC77D_HEAD_SET_RASTER_HBLANK_DELAY_BLANK_END 31:16 +#define NVC77D_HEAD_SET_HDMI_DSC_HCACTIVE(a) (0x00002368 + (a)*0x00000400) +#define NVC77D_HEAD_SET_HDMI_DSC_HCACTIVE_BYTES 15:0 +#define NVC77D_HEAD_SET_HDMI_DSC_HCACTIVE_TRI_BYTES 31:16 +#define NVC77D_HEAD_SET_HDMI_DSC_HCBLANK(a) (0x0000236C + (a)*0x00000400) +#define NVC77D_HEAD_SET_HDMI_DSC_HCBLANK_WIDTH 15:0 +#define NVC77D_HEAD_SW_RESERVED(a,b) (0x00002370 + (a)*0x00000400 + (b)*0x00000004) +#define NVC77D_HEAD_SW_RESERVED_VALUE 31:0 +#define NVC77D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_HI(a,b) (0x00002380 + (a)*0x00000400 + (b)*0x00000004) +#define NVC77D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_HI_VALUE 31:0 +#define NVC77D_HEAD_SET_INFOFRAME_CTRL(a) (0x000023A4 + (a)*0x00000400) +#define NVC77D_HEAD_SET_INFOFRAME_CTRL_MODE 1:0 +#define NVC77D_HEAD_SET_INFOFRAME_CTRL_MODE_DISABLE (0x00000000) +#define NVC77D_HEAD_SET_INFOFRAME_CTRL_MODE_GENERIC (0x00000001) +#define NVC77D_HEAD_SET_INFOFRAME_CTRL_MODE_EMP_OTHERS (0x00000002) +#define NVC77D_HEAD_SET_INFOFRAME_CTRL_FREQUENCY 12:12 +#define NVC77D_HEAD_SET_INFOFRAME_CTRL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVC77D_HEAD_SET_INFOFRAME_CTRL_FREQUENCY_ONCE (0x00000001) +#define NVC77D_HEAD_SET_INFOFRAME_CTRL_LOCATION 5:4 +#define NVC77D_HEAD_SET_INFOFRAME_CTRL_LOCATION_VSYNC (0x00000000) +#define NVC77D_HEAD_SET_INFOFRAME_CTRL_LOCATION_VBLANK (0x00000001) +#define NVC77D_HEAD_SET_INFOFRAME_CTRL_MTD_STATE_CTRL 14:14 +#define NVC77D_HEAD_SET_INFOFRAME_CTRL_MTD_STATE_CTRL_ACTIVE (0x00000000) +#define NVC77D_HEAD_SET_INFOFRAME_CTRL_MTD_STATE_CTRL_ARM (0x00000001) +#define NVC77D_HEAD_SET_INFOFRAME_HEADER(a) (0x000023A8 + (a)*0x00000400) +#define NVC77D_HEAD_SET_INFOFRAME_HEADER_HB0 7:0 +#define NVC77D_HEAD_SET_INFOFRAME_HEADER_HB1 15:8 +#define NVC77D_HEAD_SET_INFOFRAME_HEADER_HB2 23:16 +#define NVC77D_HEAD_SET_INFOFRAME_HEADER_HB3 31:24 +#define NVC77D_HEAD_SET_INFOFRAME_DATA0(a) (0x000023AC + (a)*0x00000400) +#define NVC77D_HEAD_SET_INFOFRAME_DATA0_DB0 7:0 +#define NVC77D_HEAD_SET_INFOFRAME_DATA0_DB1 15:8 +#define NVC77D_HEAD_SET_INFOFRAME_DATA0_DB2 23:16 +#define NVC77D_HEAD_SET_INFOFRAME_DATA0_DB3 31:24 +#define NVC77D_HEAD_SET_INFOFRAME_DATA1(a) (0x000023B0 + (a)*0x00000400) +#define NVC77D_HEAD_SET_INFOFRAME_DATA1_DB4 7:0 +#define NVC77D_HEAD_SET_INFOFRAME_DATA1_DB5 15:8 +#define NVC77D_HEAD_SET_INFOFRAME_DATA1_DB6 23:16 +#define NVC77D_HEAD_SET_INFOFRAME_DATA1_DB7 31:24 +#define NVC77D_HEAD_SET_INFOFRAME_DATA2(a) (0x000023B4 + (a)*0x00000400) +#define NVC77D_HEAD_SET_INFOFRAME_DATA2_DB8 7:0 +#define NVC77D_HEAD_SET_INFOFRAME_DATA2_DB9 15:8 +#define NVC77D_HEAD_SET_INFOFRAME_DATA2_DB10 23:16 +#define NVC77D_HEAD_SET_INFOFRAME_DATA2_DB11 31:24 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC77d_h diff --git a/userspace/sdks/nv570/inc/class/clc77f.h b/userspace/sdks/nv570/inc/class/clc77f.h new file mode 100644 index 0000000..3651a58 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc77f.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clC77F_h_ +#define _clC77F_h_ + +// +// This class provides functional support of Display ANYChannel, Display Contextdmas bound to +// ANYChannel can be used on any other display window channels. +// +#define NVC77F_ANY_CHANNEL_DMA (0x0000C77F) + +#endif // _clC77F_h_ + diff --git a/userspace/sdks/nv570/inc/class/clc797.h b/userspace/sdks/nv570/inc/class/clc797.h new file mode 100644 index 0000000..dc4b600 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc797.h @@ -0,0 +1,4481 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_ampere_b_h_ +#define _cl_ampere_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl ampere_b */ + +#include "nvtypes.h" + +#define AMPERE_B 0xC797 + +#define NVC797_SET_OBJECT 0x0000 +#define NVC797_SET_OBJECT_CLASS_ID 15:0 +#define NVC797_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC797_NO_OPERATION 0x0100 +#define NVC797_NO_OPERATION_V 31:0 + +#define NVC797_SET_NOTIFY_A 0x0104 +#define NVC797_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC797_SET_NOTIFY_B 0x0108 +#define NVC797_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC797_NOTIFY 0x010c +#define NVC797_NOTIFY_TYPE 31:0 +#define NVC797_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC797_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC797_WAIT_FOR_IDLE 0x0110 +#define NVC797_WAIT_FOR_IDLE_V 31:0 + +#define NVC797_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC797_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC797_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC797_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC797_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC797_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC797_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC797_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC797_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC797_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC797_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC797_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC797_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC797_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC797_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC797_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC797_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC797_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC797_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC797_SEND_GO_IDLE 0x013c +#define NVC797_SEND_GO_IDLE_V 31:0 + +#define NVC797_PM_TRIGGER 0x0140 +#define NVC797_PM_TRIGGER_V 31:0 + +#define NVC797_PM_TRIGGER_WFI 0x0144 +#define NVC797_PM_TRIGGER_WFI_V 31:0 + +#define NVC797_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC797_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC797_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC797_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC797_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC797_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC797_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC797_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER 0x0158 +#define NVC797_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER_PAYLOAD_LOWER 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER 0x015c +#define NVC797_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD_UPPER 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_ADDRESS_LOWER 0x0160 +#define NVC797_SET_REPORT_SEMAPHORE_ADDRESS_LOWER_LOWER 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_ADDRESS_UPPER 0x0164 +#define NVC797_SET_REPORT_SEMAPHORE_ADDRESS_UPPER_UPPER 7:0 + +#define NVC797_REPORT_SEMAPHORE_EXECUTE 0x0168 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_OPERATION 1:0 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_OPERATION_RELEASE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_OPERATION_ACQUIRE 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_OPERATION_REPORT_ONLY 0x00000002 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_OPERATION_TRAP 0x00000003 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION 5:2 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC797_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE 6:6 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT 11:7 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_NONE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_SCG_CLOCKS 0x00000008 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS0 0x0000000A +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS1 0x0000000C +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS2 0x0000000E +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS3 0x00000010 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_TIMESTAMP 0x00000014 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE 14:13 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_SUB_REPORT 17:15 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE 19:19 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE 18:18 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE 20:20 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP 23:21 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_INC 0x00000003 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_AND 0x00000005 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_OR 0x00000006 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT 25:24 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64 27:27 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_FALSE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_TRUE 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE 29:28 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_NONE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 + +#define NVC797_LINE_LENGTH_IN 0x0180 +#define NVC797_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC797_LINE_COUNT 0x0184 +#define NVC797_LINE_COUNT_VALUE 31:0 + +#define NVC797_OFFSET_OUT_UPPER 0x0188 +#define NVC797_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC797_OFFSET_OUT 0x018c +#define NVC797_OFFSET_OUT_VALUE 31:0 + +#define NVC797_PITCH_OUT 0x0190 +#define NVC797_PITCH_OUT_VALUE 31:0 + +#define NVC797_SET_DST_BLOCK_SIZE 0x0194 +#define NVC797_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC797_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC797_SET_DST_WIDTH 0x0198 +#define NVC797_SET_DST_WIDTH_V 31:0 + +#define NVC797_SET_DST_HEIGHT 0x019c +#define NVC797_SET_DST_HEIGHT_V 31:0 + +#define NVC797_SET_DST_DEPTH 0x01a0 +#define NVC797_SET_DST_DEPTH_V 31:0 + +#define NVC797_SET_DST_LAYER 0x01a4 +#define NVC797_SET_DST_LAYER_V 31:0 + +#define NVC797_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC797_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC797_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC797_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC797_LAUNCH_DMA 0x01b0 +#define NVC797_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC797_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC797_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC797_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC797_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC797_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC797_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC797_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC797_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC797_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC797_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC797_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC797_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC797_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC797_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC797_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC797_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC797_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC797_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC797_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC797_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC797_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC797_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC797_LOAD_INLINE_DATA 0x01b4 +#define NVC797_LOAD_INLINE_DATA_V 31:0 + +#define NVC797_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC797_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC797_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC797_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC797_SET_MME_SWITCH_STATE 0x01ec +#define NVC797_SET_MME_SWITCH_STATE_VALID 0:0 +#define NVC797_SET_MME_SWITCH_STATE_VALID_FALSE 0x00000000 +#define NVC797_SET_MME_SWITCH_STATE_VALID_TRUE 0x00000001 +#define NVC797_SET_MME_SWITCH_STATE_SAVE_MACRO 11:4 +#define NVC797_SET_MME_SWITCH_STATE_RESTORE_MACRO 19:12 + +#define NVC797_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC797_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC797_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC797_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC797_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC797_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC797_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC797_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC797_RUN_DS_NOW 0x0200 +#define NVC797_RUN_DS_NOW_V 31:0 + +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC797_SET_GS_MODE 0x0208 +#define NVC797_SET_GS_MODE_TYPE 0:0 +#define NVC797_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVC797_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVC797_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC797_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC797_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC797_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC797_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC797_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_GS_DM_FIFO 0x0214 +#define NVC797_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC797_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC797_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC797_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC797_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC797_INVALIDATE_SHADER_CACHES 0x021c +#define NVC797_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC797_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC797_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC797_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC797_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC797_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC797_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC797_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC797_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC797_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC797_SET_INSTANCE_COUNT 0x0220 +#define NVC797_SET_INSTANCE_COUNT_V 31:0 + +#define NVC797_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVC797_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVC797_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC797_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVC797_SET_MME_VERSION 0x0234 +#define NVC797_SET_MME_VERSION_MAJOR 7:0 + +#define NVC797_SET_INDEX_BUFFER_SIZE_A 0x0238 +#define NVC797_SET_INDEX_BUFFER_SIZE_A_UPPER 7:0 + +#define NVC797_SET_INDEX_BUFFER_SIZE_B 0x023c +#define NVC797_SET_INDEX_BUFFER_SIZE_B_LOWER 31:0 + +#define NVC797_SET_ROOT_TABLE_VISIBILITY(i) (0x0240+(i)*4) +#define NVC797_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP0_ENABLE 1:0 +#define NVC797_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP1_ENABLE 5:4 +#define NVC797_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP2_ENABLE 9:8 +#define NVC797_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP3_ENABLE 13:12 +#define NVC797_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP4_ENABLE 17:16 + +#define NVC797_SET_DRAW_CONTROL_A 0x0260 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY 3:0 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_POINTS 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_LINES 0x00000001 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_QUADS 0x00000007 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_PATCH 0x0000000E +#define NVC797_SET_DRAW_CONTROL_A_PRIMITIVE_ID 4:4 +#define NVC797_SET_DRAW_CONTROL_A_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ID 6:5 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ID_FIRST 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC797_SET_DRAW_CONTROL_A_SPLIT_MODE 8:7 +#define NVC797_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC797_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC797_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE 9:9 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 +#define NVC797_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX 10:10 +#define NVC797_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_FALSE 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_TRUE 0x00000001 +#define NVC797_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX 11:11 +#define NVC797_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_FALSE 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_TRUE 0x00000001 + +#define NVC797_SET_DRAW_CONTROL_B 0x0264 +#define NVC797_SET_DRAW_CONTROL_B_INSTANCE_COUNT 31:0 + +#define NVC797_DRAW_INDEX_BUFFER_BEGIN_END_A 0x0268 +#define NVC797_DRAW_INDEX_BUFFER_BEGIN_END_A_FIRST 31:0 + +#define NVC797_DRAW_INDEX_BUFFER_BEGIN_END_B 0x026c +#define NVC797_DRAW_INDEX_BUFFER_BEGIN_END_B_COUNT 31:0 + +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_A 0x0270 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_A_START 31:0 + +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_B 0x0274 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_B_COUNT 31:0 + +#define NVC797_INVALIDATE_RASTER_CACHE_NO_WFI 0x027c +#define NVC797_INVALIDATE_RASTER_CACHE_NO_WFI_V 0:0 + +#define NVC797_SET_COLOR_RENDER_TO_ZETA_SURFACE 0x02b8 +#define NVC797_SET_COLOR_RENDER_TO_ZETA_SURFACE_V 0:0 +#define NVC797_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_FALSE 0x00000000 +#define NVC797_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_TRUE 0x00000001 + +#define NVC797_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION 0x02bc +#define NVC797_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V 0:0 +#define NVC797_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_FALSE 0x00000000 +#define NVC797_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_TRUE 0x00000001 + +#define NVC797_INCREMENT_SYNC_POINT 0x02c8 +#define NVC797_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC797_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC797_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC797_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC797_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC797_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC797_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC797_SET_ROOT_TABLE_PREFETCH 0x02d0 +#define NVC797_SET_ROOT_TABLE_PREFETCH_STAGE_ENABLES 5:0 + +#define NVC797_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC797_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC797_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC797_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVC797_DECOMPRESS_SURFACE 0x02e0 +#define NVC797_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC797_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC797_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC797_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC797_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC797_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC797_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC797_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC797_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC797_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC797_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC797_SET_ZCULL_SUBREGION 0x02e8 +#define NVC797_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC797_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC797_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC797_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC797_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC797_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC797_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC797_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC797_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC797_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC797_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC797_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC797_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC797_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC797_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC797_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC797_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC797_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC797_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC797_DRAW_ZERO_INDEX 0x0304 +#define NVC797_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC797_SET_L1_CONFIGURATION 0x0308 +#define NVC797_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC797_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC797_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC797_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC797_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC797_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC797_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC797_SET_SPA_VERSION 0x0310 +#define NVC797_SET_SPA_VERSION_MINOR 7:0 +#define NVC797_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC797_SET_TIMESLICE_BATCH_LIMIT 0x0314 +#define NVC797_SET_TIMESLICE_BATCH_LIMIT_BATCH_LIMIT 15:0 + +#define NVC797_SET_SNAP_GRID_LINE 0x0318 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC797_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC797_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC797_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC797_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC797_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC797_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC797_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC797_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC797_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC797_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC797_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC797_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC797_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC797_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC797_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC797_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC797_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC797_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC797_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC797_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC797_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC797_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC797_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC797_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC797_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC797_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC797_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC797_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC797_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC797_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC797_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC797_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC797_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC797_RESERVED_TG07 0x033c +#define NVC797_RESERVED_TG07_V 0:0 + +#define NVC797_RESERVED_TG08 0x0340 +#define NVC797_RESERVED_TG08_V 0:0 + +#define NVC797_RESERVED_TG09 0x0344 +#define NVC797_RESERVED_TG09_V 0:0 + +#define NVC797_RESERVED_TG10 0x0348 +#define NVC797_RESERVED_TG10_V 0:0 + +#define NVC797_RESERVED_TG11 0x034c +#define NVC797_RESERVED_TG11_V 0:0 + +#define NVC797_RESERVED_TG12 0x0350 +#define NVC797_RESERVED_TG12_V 0:0 + +#define NVC797_RESERVED_TG13 0x0354 +#define NVC797_RESERVED_TG13_V 0:0 + +#define NVC797_RESERVED_TG14 0x0358 +#define NVC797_RESERVED_TG14_V 0:0 + +#define NVC797_RESERVED_TG15 0x035c +#define NVC797_RESERVED_TG15_V 0:0 + +#define NVC797_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC797_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC797_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC797_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC797_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC797_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC797_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC797_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC797_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC797_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC797_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC797_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC797_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC797_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC797_SET_RASTER_ENABLE 0x037c +#define NVC797_SET_RASTER_ENABLE_V 0:0 +#define NVC797_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC797_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC797_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC797_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC797_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC797_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC797_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC797_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC797_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC797_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC797_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVC797_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVC797_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVC797_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVC797_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVC797_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVC797_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVC797_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVC797_SET_Z_ROP_SLICE_MAP 0x0500 +#define NVC797_SET_Z_ROP_SLICE_MAP_VIRTUAL_ADDRESS_MASK 31:0 + +#define NVC797_SET_ROOT_TABLE_SELECTOR 0x0504 +#define NVC797_SET_ROOT_TABLE_SELECTOR_ROOT_TABLE 2:0 +#define NVC797_SET_ROOT_TABLE_SELECTOR_OFFSET 15:8 + +#define NVC797_LOAD_ROOT_TABLE 0x0508 +#define NVC797_LOAD_ROOT_TABLE_V 31:0 + +#define NVC797_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVC797_SET_MME_MEM_ADDRESS_A_UPPER 16:0 + +#define NVC797_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVC797_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVC797_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVC797_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVC797_MME_DMA_READ 0x055c +#define NVC797_MME_DMA_READ_LENGTH 31:0 + +#define NVC797_MME_DMA_READ_FIFOED 0x0560 +#define NVC797_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVC797_MME_DMA_WRITE 0x0564 +#define NVC797_MME_DMA_WRITE_LENGTH 31:0 + +#define NVC797_MME_DMA_REDUCTION 0x0568 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVC797_MME_DMA_SYSMEMBAR 0x056c +#define NVC797_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVC797_MME_DMA_SYNC 0x0570 +#define NVC797_MME_DMA_SYNC_VALUE 31:0 + +#define NVC797_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NVC797_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NVC797_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NVC797_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NVC797_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NVC797_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NVC797_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NVC797_SET_VERTEX_STREAM_SIZE_A(j) (0x0600+(j)*8) +#define NVC797_SET_VERTEX_STREAM_SIZE_A_UPPER 7:0 + +#define NVC797_SET_VERTEX_STREAM_SIZE_B(j) (0x0604+(j)*8) +#define NVC797_SET_VERTEX_STREAM_SIZE_B_LOWER 31:0 + +#define NVC797_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC797_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC797_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC797_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC797_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC797_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC797_SET_RASTER_INPUT 0x0740 +#define NVC797_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC797_SET_STREAM_OUTPUT 0x0744 +#define NVC797_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC797_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC797_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC797_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC797_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC797_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC797_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC797_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC797_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC797_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC797_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC797_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC797_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC797_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC797_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC797_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC797_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC797_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC797_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC797_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC797_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC797_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC797_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC797_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC797_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC797_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVC797_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC797_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC797_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC797_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC797_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC797_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC797_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC797_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC797_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC797_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC797_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC797_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC797_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC797_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC797_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC797_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC797_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC797_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC797_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC797_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC797_SET_ZCULL_STORAGE_B 0x07ec +#define NVC797_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC797_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC797_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC797_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC797_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC797_SET_ZT_READ_ONLY 0x07f8 +#define NVC797_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC797_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC797_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC797_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC797_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC797_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC797_THROTTLE_SM 0x07fc +#define NVC797_THROTTLE_SM_MULTIPLY_ADD 0:0 +#define NVC797_THROTTLE_SM_MULTIPLY_ADD_FALSE 0x00000000 +#define NVC797_THROTTLE_SM_MULTIPLY_ADD_TRUE 0x00000001 + +#define NVC797_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC797_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC797_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC797_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC797_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC797_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC797_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC797_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC797_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC797_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC797_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC797_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC797_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC797_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC797_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC797_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC797_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC797_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC797_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC797_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC797_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC797_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC797_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC797_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC797_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC797_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC797_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC797_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC797_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC797_SET_COLOR_TARGET_C_ROP_SLICE_MAP(j) (0x0824+(j)*64) +#define NVC797_SET_COLOR_TARGET_C_ROP_SLICE_MAP_VIRTUAL_ADDRESS_MASK 31:0 + +#define NVC797_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC797_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC797_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC797_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC797_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC797_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC797_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC797_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC797_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC797_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC797_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC797_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC797_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC797_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC797_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC797_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC797_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC797_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC797_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC797_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC797_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC797_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC797_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC797_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC797_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC797_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC797_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC797_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC797_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC797_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC797_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC797_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC797_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC797_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC797_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC797_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC797_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC797_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC797_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC797_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC797_SET_STATISTICS_COUNTER 0x0d68 +#define NVC797_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC797_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC797_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC797_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC797_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC797_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC797_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC797_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC797_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC797_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC797_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC797_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC797_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC797_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC797_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC797_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC797_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVC797_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC797_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC797_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC797_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC797_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC797_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC797_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC797_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC797_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC797_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC797_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC797_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC797_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC797_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC797_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC797_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC797_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC797_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC797_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC797_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC797_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC797_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC797_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC797_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC797_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC797_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC797_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC797_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC797_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC797_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC797_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC797_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC797_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC797_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC797_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC797_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC797_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC797_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC797_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC797_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC797_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC797_SET_POLY_SMOOTH 0x0db4 +#define NVC797_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC797_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC797_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC797_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC797_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC797_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC797_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC797_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC797_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC797_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_PATCH 0x0dcc +#define NVC797_SET_PATCH_SIZE 7:0 + +#define NVC797_SET_ITERATED_BLEND 0x0dd0 +#define NVC797_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC797_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC797_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC797_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC797_SET_ZCULL_CRITERION 0x0dd8 +#define NVC797_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC797_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC797_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC797_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC797_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC797_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC797_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC797_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC797_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC797_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC797_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 +#define NVC797_PIXEL_SHADER_BARRIER_BARRIER_LOCATION 1:1 +#define NVC797_PIXEL_SHADER_BARRIER_BARRIER_LOCATION_BLOCK_BEFORE_PS 0x00000000 +#define NVC797_PIXEL_SHADER_BARRIER_BARRIER_LOCATION_BLOCK_BEFORE_PS_AND_ZTEST 0x00000001 + +#define NVC797_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC797_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC797_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC797_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC797_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC797_MME_DMA_WRITE_METHOD_BARRIER 0x0dec +#define NVC797_MME_DMA_WRITE_METHOD_BARRIER_V 0:0 + +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC797_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC797_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC797_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC797_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC797_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC797_SET_SCISSOR_ENABLE_V 0:0 +#define NVC797_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC797_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC797_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC797_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC797_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC797_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC797_SET_VPC_PERF_KNOB 0x0f14 +#define NVC797_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC797_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC797_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC797_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC797_PM_LOCAL_TRIGGER 0x0f18 +#define NVC797_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC797_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC797_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC797_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC797_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC797_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC797_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC797_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC797_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC797_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC797_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC797_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC797_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC797_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC797_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC797_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC797_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC797_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC797_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC797_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC797_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC797_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC797_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC797_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC797_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC797_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC797_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC797_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC797_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC797_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC797_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC797_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC797_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC797_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC797_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC797_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC797_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC797_SET_SAMPLE_MASK 0x0fa4 +#define NVC797_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC797_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC797_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC797_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC797_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC797_SET_CT_MRT_ENABLE 0x0fac +#define NVC797_SET_CT_MRT_ENABLE_V 0:0 +#define NVC797_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC797_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC797_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC797_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC797_SET_TIR 0x0fb4 +#define NVC797_SET_TIR_MODE 1:0 +#define NVC797_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC797_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC797_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC797_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC797_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC797_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC797_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC797_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC797_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC797_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC797_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC797_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC797_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC797_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC797_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC797_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC797_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC797_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC797_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC797_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_TIR_MODULATION 0x0fd4 +#define NVC797_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC797_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC797_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC797_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC797_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC797_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC797_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC797_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC797_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC797_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC797_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC797_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC797_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC797_SET_ZT_A 0x0fe0 +#define NVC797_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_ZT_B 0x0fe4 +#define NVC797_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_ZT_FORMAT 0x0fe8 +#define NVC797_SET_ZT_FORMAT_V 4:0 +#define NVC797_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC797_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC797_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC797_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC797_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC797_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC797_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC797_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC797_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC797_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC797_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC797_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC797_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC797_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC797_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC797_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC797_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC797_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC797_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC797_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC797_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC797_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC797_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC797_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC797_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC797_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC797_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC797_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC797_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC797_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC797_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC797_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC797_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC797_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC797_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC797_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC797_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC797_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC797_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC797_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC797_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC797_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC797_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC797_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC797_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC797_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD02 0x102c +#define NVC797_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC797_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC797_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC797_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC797_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC797_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC797_SET_SPARE_NOOP01 0x1044 +#define NVC797_SET_SPARE_NOOP01_V 31:0 + +#define NVC797_SET_SPARE_NOOP02 0x1048 +#define NVC797_SET_SPARE_NOOP02_V 31:0 + +#define NVC797_SET_SPARE_NOOP03 0x104c +#define NVC797_SET_SPARE_NOOP03_V 31:0 + +#define NVC797_SET_SPARE_NOOP04 0x1050 +#define NVC797_SET_SPARE_NOOP04_V 31:0 + +#define NVC797_SET_SPARE_NOOP05 0x1054 +#define NVC797_SET_SPARE_NOOP05_V 31:0 + +#define NVC797_SET_SPARE_NOOP06 0x1058 +#define NVC797_SET_SPARE_NOOP06_V 31:0 + +#define NVC797_SET_SPARE_NOOP07 0x105c +#define NVC797_SET_SPARE_NOOP07_V 31:0 + +#define NVC797_SET_SPARE_NOOP08 0x1060 +#define NVC797_SET_SPARE_NOOP08_V 31:0 + +#define NVC797_SET_SPARE_NOOP09 0x1064 +#define NVC797_SET_SPARE_NOOP09_V 31:0 + +#define NVC797_SET_SPARE_NOOP10 0x1068 +#define NVC797_SET_SPARE_NOOP10_V 31:0 + +#define NVC797_SET_SPARE_NOOP11 0x106c +#define NVC797_SET_SPARE_NOOP11_V 31:0 + +#define NVC797_SET_SPARE_NOOP12 0x1070 +#define NVC797_SET_SPARE_NOOP12_V 31:0 + +#define NVC797_SET_SPARE_NOOP13 0x1074 +#define NVC797_SET_SPARE_NOOP13_V 31:0 + +#define NVC797_SET_SPARE_NOOP14 0x1078 +#define NVC797_SET_SPARE_NOOP14_V 31:0 + +#define NVC797_SET_SPARE_NOOP15 0x107c +#define NVC797_SET_SPARE_NOOP15_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC797_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC797_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC797_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC797_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC797_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC797_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC797_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC797_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC797_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC797_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC797_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC797_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC797_UNBIND_ALL 0x10f4 +#define NVC797_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC797_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC797_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC797_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC797_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC797_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC797_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC797_NO_OPERATION_DATA_HI 0x110c +#define NVC797_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC797_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC797_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC797_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC797_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC797_PM_TRIGGER_END 0x1114 +#define NVC797_PM_TRIGGER_END_V 31:0 + +#define NVC797_SET_VERTEX_ID_BASE 0x1118 +#define NVC797_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC797_SET_STENCIL_COMPRESSION 0x111c +#define NVC797_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC797_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC797_SET_TIR_CONTROL 0x1130 +#define NVC797_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC797_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC797_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC797_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC797_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC797_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC797_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC797_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC797_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 +#define NVC797_SET_TIR_CONTROL_REDUCTION_MODE 2:2 +#define NVC797_SET_TIR_CONTROL_REDUCTION_MODE_AFFINITY_MAP 0x00000000 +#define NVC797_SET_TIR_CONTROL_REDUCTION_MODE_TRUNCATION 0x00000001 + +#define NVC797_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC797_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC797_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC797_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC797_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC797_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC797_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC797_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC797_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC797_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC797_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC797_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC797_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC797_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC797_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC797_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC797_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC797_FLUSH_PENDING_WRITES 0x1144 +#define NVC797_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC797_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC797_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC797_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC797_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC797_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC797_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC797_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC797_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC797_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC797_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC797_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC797_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC797_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC797_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC797_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC797_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC797_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC797_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC797_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC797_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC797_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC797_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_SCREEN_STATE_MASK 0x1204 +#define NVC797_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC797_SET_ZT_SPARSE 0x1208 +#define NVC797_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC797_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC797_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC797_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_SET_CT_SELECT 0x121c +#define NVC797_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC797_SET_CT_SELECT_TARGET0 6:4 +#define NVC797_SET_CT_SELECT_TARGET1 9:7 +#define NVC797_SET_CT_SELECT_TARGET2 12:10 +#define NVC797_SET_CT_SELECT_TARGET3 15:13 +#define NVC797_SET_CT_SELECT_TARGET4 18:16 +#define NVC797_SET_CT_SELECT_TARGET5 21:19 +#define NVC797_SET_CT_SELECT_TARGET6 24:22 +#define NVC797_SET_CT_SELECT_TARGET7 27:25 + +#define NVC797_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC797_SET_ZT_SIZE_A 0x1228 +#define NVC797_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC797_SET_ZT_SIZE_B 0x122c +#define NVC797_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC797_SET_ZT_SIZE_C 0x1230 +#define NVC797_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC797_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC797_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC797_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC797_SET_SAMPLER_BINDING 0x1234 +#define NVC797_SET_SAMPLER_BINDING_V 0:0 +#define NVC797_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC797_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC797_DRAW_AUTO 0x123c +#define NVC797_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC797_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC797_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC797_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC797_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC797_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC797_SET_BACK_END_COPY_A 0x1264 +#define NVC797_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC797_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC797_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC797_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC797_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BACK_END_COPY_B 0x1268 +#define NVC797_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC797_SET_BACK_END_COPY_C 0x126c +#define NVC797_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC797_SET_BACK_END_COPY_D 0x1270 +#define NVC797_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC797_SET_BACK_END_COPY_E 0x1274 +#define NVC797_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC797_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC797_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVC797_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC797_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC797_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC797_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC797_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC797_CLEAR_ZCULL_REGION 0x12c8 +#define NVC797_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC797_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC797_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC797_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC797_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC797_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC797_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC797_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC797_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC797_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC797_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC797_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC797_SET_DEPTH_TEST 0x12cc +#define NVC797_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC797_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_FILL_MODE 0x12d0 +#define NVC797_SET_FILL_MODE_V 31:0 +#define NVC797_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC797_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC797_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC797_SET_SHADE_MODE 0x12d4 +#define NVC797_SET_SHADE_MODE_V 31:0 +#define NVC797_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC797_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC797_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC797_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC797_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC797_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC797_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC797_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC797_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC797_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC797_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC797_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_DEPTH_WRITE 0x12e8 +#define NVC797_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC797_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_ALPHA_TEST 0x12ec +#define NVC797_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC797_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC797_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC797_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC797_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC797_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC797_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC797_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC797_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC797_D3D_SET_CULL_MODE 0x1308 +#define NVC797_D3D_SET_CULL_MODE_V 31:0 +#define NVC797_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC797_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC797_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC797_SET_DEPTH_FUNC 0x130c +#define NVC797_SET_DEPTH_FUNC_V 31:0 +#define NVC797_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC797_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC797_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC797_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC797_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC797_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC797_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC797_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC797_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC797_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC797_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC797_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC797_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC797_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC797_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC797_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC797_SET_ALPHA_REF 0x1310 +#define NVC797_SET_ALPHA_REF_V 31:0 + +#define NVC797_SET_ALPHA_FUNC 0x1314 +#define NVC797_SET_ALPHA_FUNC_V 31:0 +#define NVC797_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC797_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC797_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC797_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC797_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC797_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC797_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC797_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC797_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC797_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC797_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC797_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC797_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC797_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC797_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC797_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC797_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC797_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC797_SET_BLEND_CONST_RED 0x131c +#define NVC797_SET_BLEND_CONST_RED_V 31:0 + +#define NVC797_SET_BLEND_CONST_GREEN 0x1320 +#define NVC797_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC797_SET_BLEND_CONST_BLUE 0x1324 +#define NVC797_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC797_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC797_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC797_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC797_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC797_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC797_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC797_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC797_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC797_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC797_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BLEND_COLOR_OP 0x1340 +#define NVC797_SET_BLEND_COLOR_OP_V 31:0 +#define NVC797_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC797_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC797_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC797_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC797_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC797_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC797_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC797_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC797_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC797_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_BLEND_ALPHA_OP 0x134c +#define NVC797_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC797_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC797_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC797_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC797_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC797_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC797_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC797_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC797_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC797_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC797_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC797_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC797_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC797_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC797_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC797_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BLEND(i) (0x1360+(i)*4) +#define NVC797_SET_BLEND_ENABLE 0:0 +#define NVC797_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_STENCIL_TEST 0x1380 +#define NVC797_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC797_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_STENCIL_OP_FAIL 0x1384 +#define NVC797_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC797_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC797_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC797_SET_STENCIL_OP_ZPASS 0x138c +#define NVC797_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC797_SET_STENCIL_FUNC 0x1390 +#define NVC797_SET_STENCIL_FUNC_V 31:0 +#define NVC797_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC797_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC797_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC797_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC797_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC797_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC797_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC797_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC797_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC797_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC797_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC797_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC797_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC797_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC797_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC797_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC797_SET_STENCIL_FUNC_REF 0x1394 +#define NVC797_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC797_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC797_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC797_SET_STENCIL_MASK 0x139c +#define NVC797_SET_STENCIL_MASK_V 7:0 + +#define NVC797_SET_DRAW_AUTO_START 0x13a4 +#define NVC797_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC797_SET_PS_SATURATE 0x13a8 +#define NVC797_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC797_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC797_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC797_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC797_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC797_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC797_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC797_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC797_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC797_SET_WINDOW_ORIGIN 0x13ac +#define NVC797_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC797_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC797_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC797_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC797_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC797_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC797_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC797_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC797_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC797_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC797_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC797_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC797_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC797_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC797_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC797_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC797_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC797_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC797_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC797_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC797_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC797_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC797_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC797_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC797_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC797_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC797_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC797_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC797_STORE_ZCULL 0x1464 +#define NVC797_STORE_ZCULL_V 0:0 + +#define NVC797_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC797_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC797_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC797_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC797_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC797_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC797_LOAD_ZCULL 0x1500 +#define NVC797_LOAD_ZCULL_V 0:0 + +#define NVC797_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC797_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC797_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC797_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC797_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC797_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC797_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC797_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC797_SET_USER_CLIP_ENABLE 0x1510 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC797_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC797_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC797_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_POINT_SIZE 0x1518 +#define NVC797_SET_POINT_SIZE_V 31:0 + +#define NVC797_SET_ZCULL_STATS 0x151c +#define NVC797_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC797_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_POINT_SPRITE 0x1520 +#define NVC797_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC797_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC797_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC797_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC797_CLEAR_REPORT_VALUE 0x1530 +#define NVC797_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC797_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC797_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC797_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC797_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC797_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC797_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVC797_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC797_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC797_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_ZT_SELECT 0x1538 +#define NVC797_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC797_SET_RENDER_ENABLE_A 0x1550 +#define NVC797_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_RENDER_ENABLE_B 0x1554 +#define NVC797_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_RENDER_ENABLE_C 0x1558 +#define NVC797_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC797_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC797_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC797_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC797_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC797_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC797_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC797_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC797_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC797_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC797_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC797_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC797_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC797_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC797_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC797_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC797_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_TEX_HEADER_POOL_C 0x157c +#define NVC797_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC797_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC797_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC797_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC797_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC797_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC797_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC797_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC797_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC797_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC797_SET_SRGB_WRITE 0x15b8 +#define NVC797_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC797_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_DEPTH_BIAS 0x15bc +#define NVC797_SET_DEPTH_BIAS_V 31:0 + +#define NVC797_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC797_SET_RT_LAYER 0x15cc +#define NVC797_SET_RT_LAYER_V 15:0 +#define NVC797_SET_RT_LAYER_CONTROL 16:16 +#define NVC797_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC797_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC797_SET_ANTI_ALIAS 0x15d0 +#define NVC797_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC797_SET_EDGE_FLAG 0x15e4 +#define NVC797_SET_EDGE_FLAG_V 0:0 +#define NVC797_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC797_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC797_DRAW_INLINE_INDEX 0x15e8 +#define NVC797_DRAW_INLINE_INDEX_V 31:0 + +#define NVC797_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC797_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC797_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC797_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC797_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC797_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC797_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC797_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC797_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC797_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC797_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC797_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC797_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC797_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC797_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC797_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC797_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC797_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC797_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC797_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC797_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC797_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC797_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC797_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC797_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC797_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC797_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC797_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC797_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC797_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC797_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC797_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC797_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC797_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC797_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC797_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC797_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC797_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC797_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC797_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC797_END 0x1614 +#define NVC797_END_V 0:0 + +#define NVC797_BEGIN 0x1618 +#define NVC797_BEGIN_OP 15:0 +#define NVC797_BEGIN_OP_POINTS 0x00000000 +#define NVC797_BEGIN_OP_LINES 0x00000001 +#define NVC797_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC797_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC797_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC797_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC797_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC797_BEGIN_OP_QUADS 0x00000007 +#define NVC797_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC797_BEGIN_OP_POLYGON 0x00000009 +#define NVC797_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC797_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC797_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_BEGIN_OP_PATCH 0x0000000E +#define NVC797_BEGIN_PRIMITIVE_ID 24:24 +#define NVC797_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC797_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC797_BEGIN_INSTANCE_ID 27:26 +#define NVC797_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC797_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC797_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC797_BEGIN_SPLIT_MODE 30:29 +#define NVC797_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC797_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC797_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC797_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC797_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVC797_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC797_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_VERTEX_ID_COPY 0x161c +#define NVC797_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC797_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC797_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC797_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC797_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC797_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC797_LOAD_PRIMITIVE_ID 0x1624 +#define NVC797_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC797_SET_SHADER_BASED_CULL 0x162c +#define NVC797_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC797_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC797_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC797_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_CLASS_VERSION 0x1638 +#define NVC797_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC797_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC797_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC797_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC797_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC797_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC797_SET_DA_OUTPUT 0x164c +#define NVC797_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC797_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC797_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC797_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC797_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_POINT_CENTER_MODE 0x165c +#define NVC797_SET_POINT_CENTER_MODE_V 31:0 +#define NVC797_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC797_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC797_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC797_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC797_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC797_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC797_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC797_SET_LINE_STIPPLE 0x166c +#define NVC797_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC797_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC797_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC797_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC797_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC797_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC797_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC797_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC797_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC797_SET_PROVOKING_VERTEX 0x1684 +#define NVC797_SET_PROVOKING_VERTEX_V 0:0 +#define NVC797_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC797_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC797_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC797_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC797_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_POLYGON_STIPPLE 0x168c +#define NVC797_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC797_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_SHADER_CONTROL 0x1690 +#define NVC797_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC797_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC797_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC797_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC797_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC797_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC797_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC797_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC797_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC797_CHECK_CLASS_VERSION 0x16a0 +#define NVC797_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC797_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC797_SET_SPH_VERSION 0x16a4 +#define NVC797_SET_SPH_VERSION_CURRENT 15:0 +#define NVC797_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC797_CHECK_SPH_VERSION 0x16a8 +#define NVC797_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC797_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC797_SET_SCG_GRAPHICS_PRIORITY 0x16bc +#define NVC797_SET_SCG_GRAPHICS_PRIORITY_PRIORITY 5:0 + +#define NVC797_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS(i) (0x16c0+(i)*4) +#define NVC797_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC797_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC797_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC797_SET_AAM_VERSION 0x1790 +#define NVC797_SET_AAM_VERSION_CURRENT 15:0 +#define NVC797_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC797_CHECK_AAM_VERSION 0x1794 +#define NVC797_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC797_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC797_SET_ZT_LAYER 0x179c +#define NVC797_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC797_SET_INDEX_BUFFER_A 0x17c8 +#define NVC797_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC797_SET_INDEX_BUFFER_B 0x17cc +#define NVC797_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC797_SET_INDEX_BUFFER_E 0x17d8 +#define NVC797_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC797_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC797_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC797_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC797_SET_INDEX_BUFFER_F 0x17dc +#define NVC797_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC797_DRAW_INDEX_BUFFER 0x17e0 +#define NVC797_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC797_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC797_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC797_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC797_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC797_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC797_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC797_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC797_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC797_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC797_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC797_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC797_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC797_OGL_SET_CULL 0x1918 +#define NVC797_OGL_SET_CULL_ENABLE 0:0 +#define NVC797_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC797_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC797_OGL_SET_FRONT_FACE 0x191c +#define NVC797_OGL_SET_FRONT_FACE_V 31:0 +#define NVC797_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC797_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC797_OGL_SET_CULL_FACE 0x1920 +#define NVC797_OGL_SET_CULL_FACE_V 31:0 +#define NVC797_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC797_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC797_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC797_SET_VIEWPORT_PIXEL 0x1924 +#define NVC797_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC797_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC797_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC797_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC797_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC797_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC797_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE 17:16 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_USE_FIELD_MIN_Z_ZERO_MAX_Z_ONE 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MIN_Z_MAX_Z 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_ZERO_ONE 0x00000002 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MINUS_INF_PLUS_INF 0x00000003 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC797_SET_USER_CLIP_OP 0x1940 +#define NVC797_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC797_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC797_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC797_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC797_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC797_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC797_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC797_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC797_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC797_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC797_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC797_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC797_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC797_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC797_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC797_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC797_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC797_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC797_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC797_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC797_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC797_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC797_INVALIDATE_ZCULL 0x1958 +#define NVC797_INVALIDATE_ZCULL_V 31:0 +#define NVC797_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC797_SET_ZCULL 0x1968 +#define NVC797_SET_ZCULL_Z_ENABLE 0:0 +#define NVC797_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC797_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_ZCULL_BOUNDS 0x196c +#define NVC797_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC797_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC797_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC797_ZCULL_SYNC 0x1978 +#define NVC797_ZCULL_SYNC_V 31:0 + +#define NVC797_SET_CLIP_ID_TEST 0x197c +#define NVC797_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC797_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC797_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC797_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC797_SET_CLIP_ID 0x1984 +#define NVC797_SET_CLIP_ID_V 31:0 + +#define NVC797_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC797_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC797_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC797_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC797_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC797_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC797_SET_LOGIC_OP 0x19c4 +#define NVC797_SET_LOGIC_OP_ENABLE 0:0 +#define NVC797_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC797_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC797_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC797_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC797_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC797_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC797_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC797_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC797_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC797_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC797_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC797_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC797_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC797_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC797_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC797_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC797_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC797_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC797_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC797_SET_Z_COMPRESSION 0x19cc +#define NVC797_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC797_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC797_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC797_CLEAR_SURFACE 0x19d0 +#define NVC797_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC797_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC797_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC797_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC797_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC797_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC797_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC797_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC797_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC797_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC797_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC797_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC797_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC797_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC797_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC797_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC797_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC797_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC797_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC797_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC797_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC797_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC797_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC797_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC797_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC797_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC797_PIPE_NOP 0x1a2c +#define NVC797_PIPE_NOP_V 31:0 + +#define NVC797_SET_SPARE00 0x1a30 +#define NVC797_SET_SPARE00_V 31:0 + +#define NVC797_SET_SPARE01 0x1a34 +#define NVC797_SET_SPARE01_V 31:0 + +#define NVC797_SET_SPARE02 0x1a38 +#define NVC797_SET_SPARE02_V 31:0 + +#define NVC797_SET_SPARE03 0x1a3c +#define NVC797_SET_SPARE03_V 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC797_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC797_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC797_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC797_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC797_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC797_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC797_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC797_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC797_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC797_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC797_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC797_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_TIMESTAMP 0x00000014 +#define NVC797_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC797_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC797_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC797_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC797_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC797_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC797_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC797_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC797_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC797_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC797_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC797_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC797_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC797_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC797_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC797_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC797_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC797_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC797_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC797_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC797_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC797_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC797_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC797_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC797_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC797_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC797_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC797_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC797_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC797_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC797_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC797_SET_PIPELINE_RESERVED_B(j) (0x2004+(j)*64) +#define NVC797_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVC797_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC797_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC797_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC797_SET_PIPELINE_REGISTER_COUNT_V 8:0 + +#define NVC797_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC797_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC797_SET_PIPELINE_PROGRAM_ADDRESS_A(j) (0x2014+(j)*64) +#define NVC797_SET_PIPELINE_PROGRAM_ADDRESS_A_UPPER 7:0 + +#define NVC797_SET_PIPELINE_PROGRAM_ADDRESS_B(j) (0x2018+(j)*64) +#define NVC797_SET_PIPELINE_PROGRAM_ADDRESS_B_LOWER 31:0 + +#define NVC797_SET_PIPELINE_PROGRAM_PREFETCH(j) (0x201c+(j)*64) +#define NVC797_SET_PIPELINE_PROGRAM_PREFETCH_SIZE_IN_BLOCKS 6:0 + +#define NVC797_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC797_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC797_SET_FALCON00 0x2300 +#define NVC797_SET_FALCON00_V 31:0 + +#define NVC797_SET_FALCON01 0x2304 +#define NVC797_SET_FALCON01_V 31:0 + +#define NVC797_SET_FALCON02 0x2308 +#define NVC797_SET_FALCON02_V 31:0 + +#define NVC797_SET_FALCON03 0x230c +#define NVC797_SET_FALCON03_V 31:0 + +#define NVC797_SET_FALCON04 0x2310 +#define NVC797_SET_FALCON04_V 31:0 + +#define NVC797_SET_FALCON05 0x2314 +#define NVC797_SET_FALCON05_V 31:0 + +#define NVC797_SET_FALCON06 0x2318 +#define NVC797_SET_FALCON06_V 31:0 + +#define NVC797_SET_FALCON07 0x231c +#define NVC797_SET_FALCON07_V 31:0 + +#define NVC797_SET_FALCON08 0x2320 +#define NVC797_SET_FALCON08_V 31:0 + +#define NVC797_SET_FALCON09 0x2324 +#define NVC797_SET_FALCON09_V 31:0 + +#define NVC797_SET_FALCON10 0x2328 +#define NVC797_SET_FALCON10_V 31:0 + +#define NVC797_SET_FALCON11 0x232c +#define NVC797_SET_FALCON11_V 31:0 + +#define NVC797_SET_FALCON12 0x2330 +#define NVC797_SET_FALCON12_V 31:0 + +#define NVC797_SET_FALCON13 0x2334 +#define NVC797_SET_FALCON13_V 31:0 + +#define NVC797_SET_FALCON14 0x2338 +#define NVC797_SET_FALCON14_V 31:0 + +#define NVC797_SET_FALCON15 0x233c +#define NVC797_SET_FALCON15_V 31:0 + +#define NVC797_SET_FALCON16 0x2340 +#define NVC797_SET_FALCON16_V 31:0 + +#define NVC797_SET_FALCON17 0x2344 +#define NVC797_SET_FALCON17_V 31:0 + +#define NVC797_SET_FALCON18 0x2348 +#define NVC797_SET_FALCON18_V 31:0 + +#define NVC797_SET_FALCON19 0x234c +#define NVC797_SET_FALCON19_V 31:0 + +#define NVC797_SET_FALCON20 0x2350 +#define NVC797_SET_FALCON20_V 31:0 + +#define NVC797_SET_FALCON21 0x2354 +#define NVC797_SET_FALCON21_V 31:0 + +#define NVC797_SET_FALCON22 0x2358 +#define NVC797_SET_FALCON22_V 31:0 + +#define NVC797_SET_FALCON23 0x235c +#define NVC797_SET_FALCON23_V 31:0 + +#define NVC797_SET_FALCON24 0x2360 +#define NVC797_SET_FALCON24_V 31:0 + +#define NVC797_SET_FALCON25 0x2364 +#define NVC797_SET_FALCON25_V 31:0 + +#define NVC797_SET_FALCON26 0x2368 +#define NVC797_SET_FALCON26_V 31:0 + +#define NVC797_SET_FALCON27 0x236c +#define NVC797_SET_FALCON27_V 31:0 + +#define NVC797_SET_FALCON28 0x2370 +#define NVC797_SET_FALCON28_V 31:0 + +#define NVC797_SET_FALCON29 0x2374 +#define NVC797_SET_FALCON29_V 31:0 + +#define NVC797_SET_FALCON30 0x2378 +#define NVC797_SET_FALCON30_V 31:0 + +#define NVC797_SET_FALCON31 0x237c +#define NVC797_SET_FALCON31_V 31:0 + +#define NVC797_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC797_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC797_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC797_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC797_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC797_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC797_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC797_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC797_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC797_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC797_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC797_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC797_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC797_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC797_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC797_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC797_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC797_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC797_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC797_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC797_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC797_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC797_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC797_SET_TRAP_HANDLER_A 0x25f8 +#define NVC797_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC797_SET_TRAP_HANDLER_B 0x25fc +#define NVC797_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC797_SET_COLOR_CLAMP 0x2600 +#define NVC797_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC797_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC797_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC797_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC797_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC797_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC797_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC797_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC797_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC797_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC797_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC797_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC797_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC797_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC797_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC797_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC797_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC797_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC797_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC797_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC797_CALL_MME_MACRO_V 31:0 + +#define NVC797_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC797_CALL_MME_DATA_V 31:0 + +#endif /* _cl_ampere_b_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc7b0.h b/userspace/sdks/nv570/inc/class/clc7b0.h new file mode 100644 index 0000000..8c98771 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc7b0.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clc7b0_h_ +#define clc7b0_h_ + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC7B0_VIDEO_DECODER (0x0000C7B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc7b0_h + diff --git a/userspace/sdks/nv570/inc/class/clc7b5.h b/userspace/sdks/nv570/inc/class/clc7b5.h new file mode 100644 index 0000000..df331e8 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc7b5.h @@ -0,0 +1,304 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clc7b5_h_ +#define _clc7b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define AMPERE_DMA_COPY_B (0x0000C7B5) + +#define NVC7B5_NOP (0x00000100) +#define NVC7B5_NOP_PARAMETER 31:0 +#define NVC7B5_PM_TRIGGER (0x00000140) +#define NVC7B5_PM_TRIGGER_V 31:0 +#define NVC7B5_SET_MONITORED_FENCE_TYPE (0x0000021C) +#define NVC7B5_SET_MONITORED_FENCE_TYPE_TYPE 0:0 +#define NVC7B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE (0x00000000) +#define NVC7B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE_EXT (0x00000001) +#define NVC7B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER (0x00000220) +#define NVC7B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER_UPPER 16:0 +#define NVC7B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER (0x00000224) +#define NVC7B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER_LOWER 31:0 +#define NVC7B5_SET_SEMAPHORE_A (0x00000240) +#define NVC7B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC7B5_SET_SEMAPHORE_B (0x00000244) +#define NVC7B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC7B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC7B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC7B5_SET_SEMAPHORE_PAYLOAD_UPPER (0x0000024C) +#define NVC7B5_SET_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD 31:0 +#define NVC7B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC7B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC7B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC7B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC7B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC7B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC7B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC7B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC7B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC7B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC7B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC7B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC7B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC7B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC7B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC7B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC7B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVC7B5_SET_SRC_PHYS_MODE_BASIC_KIND 5:2 +#define NVC7B5_SET_SRC_PHYS_MODE_PEER_ID 8:6 +#define NVC7B5_SET_SRC_PHYS_MODE_FLA 9:9 +#define NVC7B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC7B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC7B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC7B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC7B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC7B5_SET_DST_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVC7B5_SET_DST_PHYS_MODE_BASIC_KIND 5:2 +#define NVC7B5_SET_DST_PHYS_MODE_PEER_ID 8:6 +#define NVC7B5_SET_DST_PHYS_MODE_FLA 9:9 +#define NVC7B5_LAUNCH_DMA (0x00000300) +#define NVC7B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC7B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC7B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC7B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC7B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC7B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC7B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC7B5_LAUNCH_DMA_FLUSH_TYPE 25:25 +#define NVC7B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000) +#define NVC7B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_NO_TIMESTAMP (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_WITH_TIMESTAMP (0x00000002) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE (0x00000003) +#define NVC7B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC7B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC7B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC7B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC7B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC7B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC7B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC7B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC7B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC7B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC7B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC7B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC7B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC7B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC7B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC7B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC7B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC7B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC7B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC7B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC7B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC7B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC7B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC7B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC7B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDA (0x00000008) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDB (0x00000009) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN (0x0000000B) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX (0x0000000C) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDC (0x0000000D) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDD (0x0000000E) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDE (0x0000000F) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC7B5_LAUNCH_DMA_VPRMODE 23:22 +#define NVC7B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVC7B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC7B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC7B5_LAUNCH_DMA_DISABLE_PLC 26:26 +#define NVC7B5_LAUNCH_DMA_DISABLE_PLC_FALSE (0x00000000) +#define NVC7B5_LAUNCH_DMA_DISABLE_PLC_TRUE (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE 27:27 +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_ONE_WORD (0x00000000) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_TWO_WORD (0x00000001) +#define NVC7B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 +#define NVC7B5_OFFSET_IN_UPPER (0x00000400) +#define NVC7B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC7B5_OFFSET_IN_LOWER (0x00000404) +#define NVC7B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC7B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC7B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC7B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC7B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC7B5_PITCH_IN (0x00000410) +#define NVC7B5_PITCH_IN_VALUE 31:0 +#define NVC7B5_PITCH_OUT (0x00000414) +#define NVC7B5_PITCH_OUT_VALUE 31:0 +#define NVC7B5_LINE_LENGTH_IN (0x00000418) +#define NVC7B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC7B5_LINE_COUNT (0x0000041C) +#define NVC7B5_LINE_COUNT_VALUE 31:0 +#define NVC7B5_SET_REMAP_CONST_A (0x00000700) +#define NVC7B5_SET_REMAP_CONST_A_V 31:0 +#define NVC7B5_SET_REMAP_CONST_B (0x00000704) +#define NVC7B5_SET_REMAP_CONST_B_V 31:0 +#define NVC7B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC7B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC7B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC7B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC7B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC7B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC7B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC7B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC7B5_SET_DST_WIDTH (0x00000710) +#define NVC7B5_SET_DST_WIDTH_V 31:0 +#define NVC7B5_SET_DST_HEIGHT (0x00000714) +#define NVC7B5_SET_DST_HEIGHT_V 31:0 +#define NVC7B5_SET_DST_DEPTH (0x00000718) +#define NVC7B5_SET_DST_DEPTH_V 31:0 +#define NVC7B5_SET_DST_LAYER (0x0000071C) +#define NVC7B5_SET_DST_LAYER_V 31:0 +#define NVC7B5_SET_DST_ORIGIN (0x00000720) +#define NVC7B5_SET_DST_ORIGIN_X 15:0 +#define NVC7B5_SET_DST_ORIGIN_Y 31:16 +#define NVC7B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC7B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC7B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC7B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC7B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC7B5_SET_SRC_WIDTH (0x0000072C) +#define NVC7B5_SET_SRC_WIDTH_V 31:0 +#define NVC7B5_SET_SRC_HEIGHT (0x00000730) +#define NVC7B5_SET_SRC_HEIGHT_V 31:0 +#define NVC7B5_SET_SRC_DEPTH (0x00000734) +#define NVC7B5_SET_SRC_DEPTH_V 31:0 +#define NVC7B5_SET_SRC_LAYER (0x00000738) +#define NVC7B5_SET_SRC_LAYER_V 31:0 +#define NVC7B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC7B5_SET_SRC_ORIGIN_X 15:0 +#define NVC7B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC7B5_SRC_ORIGIN_X (0x00000744) +#define NVC7B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC7B5_SRC_ORIGIN_Y (0x00000748) +#define NVC7B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC7B5_DST_ORIGIN_X (0x0000074C) +#define NVC7B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC7B5_DST_ORIGIN_Y (0x00000750) +#define NVC7B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC7B5_PM_TRIGGER_END (0x00001114) +#define NVC7B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc7b5_h + diff --git a/userspace/sdks/nv570/inc/class/clc7b7.h b/userspace/sdks/nv570/inc/class/clc7b7.h new file mode 100644 index 0000000..909195b --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc7b7.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef clc7b7_h_ +#define clc7b7_h_ + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC7B7_VIDEO_ENCODER (0x0000C7B7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc7b7_h + diff --git a/userspace/sdks/nv570/inc/class/clc7c0.h b/userspace/sdks/nv570/inc/class/clc7c0.h new file mode 100644 index 0000000..6eb2889 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc7c0.h @@ -0,0 +1,848 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_ampere_compute_b_h_ +#define _cl_ampere_compute_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl ampere_compute_b */ + +#include "nvtypes.h" + +#define AMPERE_COMPUTE_B 0xC7C0 + +#define NVC7C0_SET_OBJECT 0x0000 +#define NVC7C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC7C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC7C0_NO_OPERATION 0x0100 +#define NVC7C0_NO_OPERATION_V 31:0 + +#define NVC7C0_SET_NOTIFY_A 0x0104 +#define NVC7C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC7C0_SET_NOTIFY_B 0x0108 +#define NVC7C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC7C0_NOTIFY 0x010c +#define NVC7C0_NOTIFY_TYPE 31:0 +#define NVC7C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC7C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC7C0_WAIT_FOR_IDLE 0x0110 +#define NVC7C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC7C0_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC7C0_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC7C0_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC7C0_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC7C0_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC7C0_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC7C0_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC7C0_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC7C0_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC7C0_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC7C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC7C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC7C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC7C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC7C0_SEND_GO_IDLE 0x013c +#define NVC7C0_SEND_GO_IDLE_V 31:0 + +#define NVC7C0_PM_TRIGGER 0x0140 +#define NVC7C0_PM_TRIGGER_V 31:0 + +#define NVC7C0_PM_TRIGGER_WFI 0x0144 +#define NVC7C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC7C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC7C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC7C0_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC7C0_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC7C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC7C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC7C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC7C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER 0x0158 +#define NVC7C0_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER_PAYLOAD_LOWER 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER 0x015c +#define NVC7C0_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD_UPPER 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_ADDRESS_LOWER 0x0160 +#define NVC7C0_SET_REPORT_SEMAPHORE_ADDRESS_LOWER_LOWER 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_ADDRESS_UPPER 0x0164 +#define NVC7C0_SET_REPORT_SEMAPHORE_ADDRESS_UPPER_UPPER 7:0 + +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE 0x0168 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_OPERATION 1:0 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_OPERATION_RELEASE 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_OPERATION_ACQUIRE 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_OPERATION_REPORT_ONLY 0x00000002 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_OPERATION_TRAP 0x00000003 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE 2:2 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE 4:3 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE 5:5 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE 6:6 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP 9:7 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_INC 0x00000003 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_AND 0x00000005 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_OR 0x00000006 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT 11:10 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64 12:12 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_FALSE 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_TRUE 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE 14:13 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_NONE 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 + +#define NVC7C0_LINE_LENGTH_IN 0x0180 +#define NVC7C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC7C0_LINE_COUNT 0x0184 +#define NVC7C0_LINE_COUNT_VALUE 31:0 + +#define NVC7C0_OFFSET_OUT_UPPER 0x0188 +#define NVC7C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC7C0_OFFSET_OUT 0x018c +#define NVC7C0_OFFSET_OUT_VALUE 31:0 + +#define NVC7C0_PITCH_OUT 0x0190 +#define NVC7C0_PITCH_OUT_VALUE 31:0 + +#define NVC7C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC7C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC7C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC7C0_SET_DST_WIDTH 0x0198 +#define NVC7C0_SET_DST_WIDTH_V 31:0 + +#define NVC7C0_SET_DST_HEIGHT 0x019c +#define NVC7C0_SET_DST_HEIGHT_V 31:0 + +#define NVC7C0_SET_DST_DEPTH 0x01a0 +#define NVC7C0_SET_DST_DEPTH_V 31:0 + +#define NVC7C0_SET_DST_LAYER 0x01a4 +#define NVC7C0_SET_DST_LAYER_V 31:0 + +#define NVC7C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC7C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC7C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC7C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC7C0_LAUNCH_DMA 0x01b0 +#define NVC7C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC7C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC7C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC7C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC7C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC7C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC7C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC7C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC7C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC7C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC7C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC7C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC7C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC7C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC7C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC7C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC7C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC7C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC7C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC7C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC7C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC7C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC7C0_LOAD_INLINE_DATA 0x01b4 +#define NVC7C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC7C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC7C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC7C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC7C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC7C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC7C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC7C0_SET_SM_SCG_CONTROL 0x01e8 +#define NVC7C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS 0:0 +#define NVC7C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE 0x00000000 +#define NVC7C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE 0x00000001 + +#define NVC7C0_SET_MME_SWITCH_STATE 0x01ec +#define NVC7C0_SET_MME_SWITCH_STATE_VALID 0:0 +#define NVC7C0_SET_MME_SWITCH_STATE_VALID_FALSE 0x00000000 +#define NVC7C0_SET_MME_SWITCH_STATE_VALID_TRUE 0x00000001 +#define NVC7C0_SET_MME_SWITCH_STATE_SAVE_MACRO 11:4 +#define NVC7C0_SET_MME_SWITCH_STATE_RESTORE_MACRO 19:12 + +#define NVC7C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC7C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC7C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC7C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC7C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC7C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC7C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC7C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC7C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC7C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC7C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC7C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC7C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC7C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC7C0_PERFMON_TRANSFER 0x0210 +#define NVC7C0_PERFMON_TRANSFER_V 31:0 + +#define NVC7C0_SET_QMD_VIRTUALIZATION_BASE_A 0x0214 +#define NVC7C0_SET_QMD_VIRTUALIZATION_BASE_A_ADDRESS_UPPER 7:0 + +#define NVC7C0_SET_QMD_VIRTUALIZATION_BASE_B 0x0218 +#define NVC7C0_SET_QMD_VIRTUALIZATION_BASE_B_ADDRESS_LOWER 31:0 + +#define NVC7C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC7C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC7C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC7C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC7C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC7C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC7C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC7C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC7C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC7C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC7C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC7C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC7C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC7C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC7C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC7C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC7C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC7C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC7C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC7C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC7C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC7C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC7C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC7C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC7C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC7C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC7C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC7C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC7C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC7C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC7C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC7C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC7C0_SET_SCG_CONTROL 0x0270 +#define NVC7C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 +#define NVC7C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 +#define NVC7C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 +#define NVC7C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 +#define NVC7C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 + +#define NVC7C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC7C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC7C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC7C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC7C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC7C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC7C0_SET_QMD_VERSION 0x0288 +#define NVC7C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC7C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC7C0_CHECK_QMD_VERSION 0x0290 +#define NVC7C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC7C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC7C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC7C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL 0x029c +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_CONSTANT_BUFFER_MASK 7:0 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE 8:8 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE 12:12 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_DEPENDENT_ENABLE 9:9 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_DEPENDENT_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_DEPENDENT_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE 16:16 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE 20:20 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_DEPENDENT_ENABLE 10:10 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_DEPENDENT_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_DEPENDENT_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE 24:24 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_TRUE 0x00000001 + +#define NVC7C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC7C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC7C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC7C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC7C0_SCG_HYSTERESIS_CONTROL 0x02a8 +#define NVC7C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 +#define NVC7C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC7C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 +#define NVC7C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 +#define NVC7C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC7C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 + +#define NVC7C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC7C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC7C0_SEND_PCAS_A 0x02b4 +#define NVC7C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC7C0_SEND_PCAS_B 0x02b8 +#define NVC7C0_SEND_PCAS_B_FROM 23:0 +#define NVC7C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC7C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC7C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC7C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC7C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC7C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC7C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC7C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC7C0_SEND_SIGNALING_PCAS2_B 0x02c0 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION 3:0 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_NOP 0x00000000 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE 0x00000001 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_SCHEDULE 0x00000002 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_COPY_SCHEDULE 0x00000003 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_PUT 0x00000006 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_DECREMENT_DEPENDENCE 0x00000007 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH 0x00000008 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH_SCHEDULE 0x00000009 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_SCHEDULE 0x0000000A +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_FORCE_REQUIRE_SCHEDULING 0x0000000B +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_DEPENDENCE 0x0000000C +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_CWD_REF_COUNTER 0x0000000D +#define NVC7C0_SEND_SIGNALING_PCAS2_B_SELECT 13:8 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_OFFSET_MINUS_ONE 23:14 + +#define NVC7C0_SET_SKED_CACHE_CONTROL 0x02cc +#define NVC7C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID 0:0 +#define NVC7C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE 0x00000000 +#define NVC7C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE 0x00000001 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC7C0_SET_SPA_VERSION 0x0310 +#define NVC7C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC7C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC7C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC7C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC7C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC7C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC7C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC7C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC7C0_SET_FALCON00 0x0500 +#define NVC7C0_SET_FALCON00_V 31:0 + +#define NVC7C0_SET_FALCON01 0x0504 +#define NVC7C0_SET_FALCON01_V 31:0 + +#define NVC7C0_SET_FALCON02 0x0508 +#define NVC7C0_SET_FALCON02_V 31:0 + +#define NVC7C0_SET_FALCON03 0x050c +#define NVC7C0_SET_FALCON03_V 31:0 + +#define NVC7C0_SET_FALCON04 0x0510 +#define NVC7C0_SET_FALCON04_V 31:0 + +#define NVC7C0_SET_FALCON05 0x0514 +#define NVC7C0_SET_FALCON05_V 31:0 + +#define NVC7C0_SET_FALCON06 0x0518 +#define NVC7C0_SET_FALCON06_V 31:0 + +#define NVC7C0_SET_FALCON07 0x051c +#define NVC7C0_SET_FALCON07_V 31:0 + +#define NVC7C0_SET_FALCON08 0x0520 +#define NVC7C0_SET_FALCON08_V 31:0 + +#define NVC7C0_SET_FALCON09 0x0524 +#define NVC7C0_SET_FALCON09_V 31:0 + +#define NVC7C0_SET_FALCON10 0x0528 +#define NVC7C0_SET_FALCON10_V 31:0 + +#define NVC7C0_SET_FALCON11 0x052c +#define NVC7C0_SET_FALCON11_V 31:0 + +#define NVC7C0_SET_FALCON12 0x0530 +#define NVC7C0_SET_FALCON12_V 31:0 + +#define NVC7C0_SET_FALCON13 0x0534 +#define NVC7C0_SET_FALCON13_V 31:0 + +#define NVC7C0_SET_FALCON14 0x0538 +#define NVC7C0_SET_FALCON14_V 31:0 + +#define NVC7C0_SET_FALCON15 0x053c +#define NVC7C0_SET_FALCON15_V 31:0 + +#define NVC7C0_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVC7C0_SET_MME_MEM_ADDRESS_A_UPPER 16:0 + +#define NVC7C0_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVC7C0_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVC7C0_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVC7C0_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVC7C0_MME_DMA_READ 0x055c +#define NVC7C0_MME_DMA_READ_LENGTH 31:0 + +#define NVC7C0_MME_DMA_READ_FIFOED 0x0560 +#define NVC7C0_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVC7C0_MME_DMA_WRITE 0x0564 +#define NVC7C0_MME_DMA_WRITE_LENGTH 31:0 + +#define NVC7C0_MME_DMA_REDUCTION 0x0568 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVC7C0_MME_DMA_SYSMEMBAR 0x056c +#define NVC7C0_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVC7C0_MME_DMA_SYNC 0x0570 +#define NVC7C0_MME_DMA_SYNC_VALUE 31:0 + +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC7C0_THROTTLE_SM 0x07fc +#define NVC7C0_THROTTLE_SM_MULTIPLY_ADD 0:0 +#define NVC7C0_THROTTLE_SM_MULTIPLY_ADD_FALSE 0x00000000 +#define NVC7C0_THROTTLE_SM_MULTIPLY_ADD_TRUE 0x00000001 + +#define NVC7C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC7C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC7C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC7C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS(i) (0x0da0+(i)*4) +#define NVC7C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC7C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC7C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC7C0_MME_DMA_WRITE_METHOD_BARRIER 0x0dec +#define NVC7C0_MME_DMA_WRITE_METHOD_BARRIER_V 0:0 + +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC7C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC7C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC7C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC7C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC7C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC7C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC7C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC7C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC7C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC7C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC7C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC7C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC7C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC7C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC7C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC7C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC7C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC7C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC7C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC7C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC7C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC7C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC7C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC7C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC7C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC7C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC7C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC7C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC7C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC7C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC7C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC7C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC7C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC7C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC7C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC7C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC7C0_PIPE_NOP 0x1a2c +#define NVC7C0_PIPE_NOP_V 31:0 + +#define NVC7C0_SET_SPARE00 0x1a30 +#define NVC7C0_SET_SPARE00_V 31:0 + +#define NVC7C0_SET_SPARE01 0x1a34 +#define NVC7C0_SET_SPARE01_V 31:0 + +#define NVC7C0_SET_SPARE02 0x1a38 +#define NVC7C0_SET_SPARE02_V 31:0 + +#define NVC7C0_SET_SPARE03 0x1a3c +#define NVC7C0_SET_SPARE03_V 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC7C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC7C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC7C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC7C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC7C0_SET_TRAP_HANDLER_A 0x25f8 +#define NVC7C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC7C0_SET_TRAP_HANDLER_B 0x25fc +#define NVC7C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC7C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC7C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC7C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC7C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC7C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC7C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC7C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC7C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC7C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC7C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC7C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC7C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC7C0_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC7C0_CALL_MME_MACRO_V 31:0 + +#define NVC7C0_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC7C0_CALL_MME_DATA_V 31:0 + +#endif /* _cl_ampere_compute_b_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc7fa.h b/userspace/sdks/nv570/inc/class/clc7fa.h new file mode 100644 index 0000000..50892c5 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc7fa.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "nvtypes.h" + +#ifndef _clc7fa_h_ +#define _clc7fa_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC7FA_VIDEO_OFA (0x0000C7FA) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc7fa_h + diff --git a/userspace/sdks/nv570/inc/class/clc863.h b/userspace/sdks/nv570/inc/class/clc863.h new file mode 100644 index 0000000..1240562 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc863.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef CLC863_H +#define CLC863_H + +#define HOPPER_MMU_VIDMEM_ACCESS_BIT_BUFFER (0xc863) + +#define NVC863_SIZE 1024 + +#endif diff --git a/userspace/sdks/nv570/inc/class/clc86f.h b/userspace/sdks/nv570/inc/class/clc86f.h new file mode 100644 index 0000000..1548cd2 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc86f.h @@ -0,0 +1,191 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clc86f_h__ +#define __gh100_clc86f_h__ + +#define HOPPER_CHANNEL_GPFIFO_A (0x0000C86F) + +typedef volatile struct Nvc86fControl_struct { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} Nvc86fControl, HopperAControlGPFifo; + +#define NVC86F_SET_OBJECT (0x00000000) +// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for +// specifying the page address for a targeted TLB invalidate and the uTLB for +// a targeted REPLAY_CANCEL for UVM. +// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly +// rearranged fields. +#define NVC86F_MEM_OP_A (0x00000028) +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE 7:6 // only relevant for invalidates with NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE for invalidating link TLB only, or non-link TLB only or all TLBs +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS 0 +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS 1 +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS 2 +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD 3 +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID 8:0 // only relevant for REPLAY_CANCEL_VA_GLOBAL +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11 +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001 +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000 +#define NVC86F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12 +#define NVC86F_MEM_OP_B (0x0000002c) +#define NVC86F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0 +#define NVC86F_MEM_OP_C (0x00000030) +#define NVC86F_MEM_OP_C_MEMBAR_TYPE 2:0 +#define NVC86F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000 +#define NVC86F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE 9:7 //only relevant for REPLAY_CANCEL_VA_GLOBAL +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ 0 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE 1 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG 2 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD 3 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK 4 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL 5 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC 6 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL 7 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE +#define NVC86F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG 19:0 +// MEM_OP_D MUST be preceded by MEM_OPs A-C. +#define NVC86F_MEM_OP_D (0x00000034) +#define NVC86F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE +#define NVC86F_MEM_OP_D_OPERATION 31:27 +#define NVC86F_MEM_OP_D_OPERATION_MEMBAR 0x00000005 +#define NVC86F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVC86F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a +#define NVC86F_MEM_OP_D_OPERATION_MMU_OPERATION 0x0000000b +#define NVC86F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NVC86F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +// CLEAN_LINES is an alias for Tegra/GPU IP usage +#define NVC86F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e +#define NVC86F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVC86F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVC86F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015 +#define NVC86F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR 0x00000016 +#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE 1:0 +#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC 0x00000000 +#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC 0x00000001 +#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL 0x00000002 +#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED 0x00000003 +#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE 2:2 +#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC 0x00000000 +#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC 0x00000001 +#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK 6:3 +#define NVC86F_MEM_OP_D_MMU_OPERATION_TYPE 23:20 +#define NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_RESERVED 0x00000000 +#define NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_VIDMEM_ACCESS_BIT_DUMP 0x00000001 +#define NVC86F_SEM_ADDR_LO (0x0000005c) +#define NVC86F_SEM_ADDR_LO_OFFSET 31:2 +#define NVC86F_SEM_ADDR_HI (0x00000060) +#define NVC86F_SEM_ADDR_HI_OFFSET 24:0 +#define NVC86F_SEM_PAYLOAD_LO (0x00000064) +#define NVC86F_SEM_PAYLOAD_HI (0x00000068) +#define NVC86F_SEM_EXECUTE (0x0000006c) +#define NVC86F_SEM_EXECUTE_OPERATION 2:0 +#define NVC86F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000 +#define NVC86F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001 +#define NVC86F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003 +#define NVC86F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12 +#define NVC86F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001 +#define NVC86F_SEM_EXECUTE_RELEASE_WFI 20:20 +#define NVC86F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000 +#define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE 24:24 +#define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000 +#define NVC86F_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25 +#define NVC86F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000 +#define NVC86F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001 +#define NVC86F_WFI (0x00000078) +#define NVC86F_WFI_SCOPE 0:0 +#define NVC86F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000 +#define NVC86F_WFI_SCOPE_CURRENT_VEID 0x00000000 +#define NVC86F_WFI_SCOPE_ALL 0x00000001 + +/* GPFIFO entry format */ +#define NVC86F_GP_ENTRY__SIZE 8 +#define NVC86F_GP_ENTRY0_FETCH 0:0 +#define NVC86F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVC86F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVC86F_GP_ENTRY0_GET 31:2 +#define NVC86F_GP_ENTRY0_OPERAND 31:0 +#define NVC86F_GP_ENTRY0_PB_EXTENDED_BASE_OPERAND 24:8 +#define NVC86F_GP_ENTRY1_GET_HI 7:0 +#define NVC86F_GP_ENTRY1_LEVEL 9:9 +#define NVC86F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVC86F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVC86F_GP_ENTRY1_LENGTH 30:10 +#define NVC86F_GP_ENTRY1_SYNC 31:31 +#define NVC86F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVC86F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVC86F_GP_ENTRY1_OPCODE 7:0 +#define NVC86F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVC86F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVC86F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVC86F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 +#define NVC86F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE 0x00000004 + +#endif // __gh100_clc86f_h__ diff --git a/userspace/sdks/nv570/inc/class/clc86fsw.h b/userspace/sdks/nv570/inc/class/clc86fsw.h new file mode 100644 index 0000000..6020315 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc86fsw.h @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* This file is *not* auto-generated. */ + +#ifndef _clc86f_sw_h_ +#define _clc86f_sw_h_ + +#define NVC86F_NOTIFIERS_RC (0) +#define NVC86F_NOTIFIERS_REFCNT (1) +#define NVC86F_NOTIFIERS_NONSTALL (2) +#define NVC86F_NOTIFIERS_EVENTBUFFER (3) +#define NVC86F_NOTIFIERS_IDLECHANNEL (4) +#define NVC86F_NOTIFIERS_ENDCTX (5) +#define NVC86F_NOTIFIERS_SW (6) +#define NVC86F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVC86F_NOTIFIERS_REPLAYABLE_FAULT (8) +#define NVC86F_NOTIFIERS_KEY_ROTATION (9) +#define NVC86F_NOTIFIERS_MAXCOUNT (10) + +/* NvNotification[] fields and values */ +#define NVC86F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVC86F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _clc56f_sw_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc870.h b/userspace/sdks/nv570/inc/class/clc870.h new file mode 100644 index 0000000..d2d35f1 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc870.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc870.finn +// + +#define NVC870_DISPLAY (0xc870U) /* finn: Evaluated from "NVC870_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NVC870_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc870U) + +typedef struct NVC870_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numDsis; // Number of DSIs in this chip/display +} NVC870_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clc871.h b/userspace/sdks/nv570/inc/class/clc871.h new file mode 100644 index 0000000..a8d348b --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc871.h @@ -0,0 +1,380 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc871_h_ +#define _clc871_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC871_DISP_SF_USER (0x000C871) + +typedef volatile struct _clc871_tag0 { + NvU32 dispSfUserOffset[0x400]; +} _NvC871DispSfUser, NvC871DispSfUserMap; + +#define NVC871_SF_HDMI_INFO_IDX_AVI_INFOFRAME 0x00000000 /* */ +#define NVC871_SF_HDMI_INFO_IDX_GCP 0x00000001 /* */ +#define NVC871_SF_HDMI_INFO_IDX_ACR 0x00000002 /* */ +#define NVC871_SF_HDMI_INFO_CTRL(i,j) (0x000E0000-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVC871_SF_HDMI_INFO_CTRL__SIZE_1 8 /* */ +#define NVC871_SF_HDMI_INFO_CTRL__SIZE_2 3 /* */ +#define NVC871_SF_HDMI_INFO_CTRL_ENABLE 0:0 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NVC871_SF_HDMI_INFO_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NVC871_SF_HDMI_INFO_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NVC871_SF_HDMI_INFO_CTRL_OTHER 4:4 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_CTRL_OTHER_DIS 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_CTRL_OTHER_EN 0x00000001 /* RW--V */ +#define NVC871_SF_HDMI_INFO_CTRL_SINGLE 8:8 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_CTRL_SINGLE_EN 0x00000001 /* RW--V */ +#define NVC871_SF_HDMI_INFO_CTRL_CHKSUM_HW 9:9 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */ +#define NVC871_SF_HDMI_INFO_CTRL_CHKSUM_HW_EN 0x00000001 /* RW--V */ +#define NVC871_SF_HDMI_INFO_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */ +#define NVC871_SF_HDMI_INFO_CTRL_CHKSUM_HW_DIS 0x00000000 /* RW--V */ +#define NVC871_SF_HDMI_INFO_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_CTRL_HBLANK 12:12 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_CTRL_HBLANK_DIS 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_CTRL_HBLANK_EN 0x00000001 /* RW--V */ +#define NVC871_SF_HDMI_INFO_CTRL_VIDEO_FMT 16:16 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_CTRL_VIDEO_FMT_SW_CONTROLLED 0x00000000 /* RW--V */ +#define NVC871_SF_HDMI_INFO_CTRL_VIDEO_FMT_HW_CONTROLLED 0x00000001 /* RW--V */ +#define NVC871_SF_HDMI_INFO_CTRL_VIDEO_FMT_INIT 0x00000001 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_STATUS(i,j) (0x000E0004-0x000E0000+(i)*1024+(j)*64) /* R--4A */ +#define NVC871_SF_HDMI_INFO_STATUS__SIZE_1 8 /* */ +#define NVC871_SF_HDMI_INFO_STATUS__SIZE_2 3 /* */ +#define NVC871_SF_HDMI_INFO_STATUS_SENT 0:0 /* R--VF */ +#define NVC871_SF_HDMI_INFO_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NVC871_SF_HDMI_INFO_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NVC871_SF_HDMI_INFO_HEADER(i,j) (0x000E0008-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVC871_SF_HDMI_INFO_HEADER__SIZE_1 8 /* */ +#define NVC871_SF_HDMI_INFO_HEADER__SIZE_2 3 /* */ +#define NVC871_SF_HDMI_INFO_HEADER_HB0 7:0 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_HEADER_HB1 15:8 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_HEADER_HB2 23:16 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK0_LOW(i,j) (0x000E000C-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVC871_SF_HDMI_INFO_SUBPACK0_LOW__SIZE_1 8 /* */ +#define NVC871_SF_HDMI_INFO_SUBPACK0_LOW__SIZE_2 3 /* */ +#define NVC871_SF_HDMI_INFO_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK0_HIGH(i,j) (0x000E0010-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVC871_SF_HDMI_INFO_SUBPACK0_HIGH__SIZE_1 8 /* */ +#define NVC871_SF_HDMI_INFO_SUBPACK0_HIGH__SIZE_2 3 /* */ +#define NVC871_SF_HDMI_INFO_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK1_LOW(i,j) (0x000E0014-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVC871_SF_HDMI_INFO_SUBPACK1_LOW__SIZE_1 8 /* */ +#define NVC871_SF_HDMI_INFO_SUBPACK1_LOW__SIZE_2 3 /* */ +#define NVC871_SF_HDMI_INFO_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK1_HIGH(i,j) (0x000E0018-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVC871_SF_HDMI_INFO_SUBPACK1_HIGH__SIZE_1 8 /* */ +#define NVC871_SF_HDMI_INFO_SUBPACK1_HIGH__SIZE_2 3 /* */ +#define NVC871_SF_HDMI_INFO_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK2_LOW(i,j) (0x000E001C-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVC871_SF_HDMI_INFO_SUBPACK2_LOW__SIZE_1 8 /* */ +#define NVC871_SF_HDMI_INFO_SUBPACK2_LOW__SIZE_2 3 /* */ +#define NVC871_SF_HDMI_INFO_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK2_HIGH(i,j) (0x000E0020-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVC871_SF_HDMI_INFO_SUBPACK2_HIGH__SIZE_1 8 /* */ +#define NVC871_SF_HDMI_INFO_SUBPACK2_HIGH__SIZE_2 3 /* */ +#define NVC871_SF_HDMI_INFO_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK3_LOW(i,j) (0x000E0024-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVC871_SF_HDMI_INFO_SUBPACK3_LOW__SIZE_1 8 /* */ +#define NVC871_SF_HDMI_INFO_SUBPACK3_LOW__SIZE_2 3 /* */ +#define NVC871_SF_HDMI_INFO_SUBPACK3_LOW_PB21 7:0 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK3_LOW_PB22 15:8 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK3_LOW_PB23 23:16 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK3_LOW_PB24 31:24 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK3_HIGH(i,j) (0x000E0028-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVC871_SF_HDMI_INFO_SUBPACK3_HIGH__SIZE_1 8 /* */ +#define NVC871_SF_HDMI_INFO_SUBPACK3_HIGH__SIZE_2 3 /* */ +#define NVC871_SF_HDMI_INFO_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_INFO_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */ +#define NVC871_SF_HDMI_INFO_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x000E0000-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 8 /* */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER 4:4 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_DIS 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_EN 0x00000001 /* RW--V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE 8:8 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_EN 0x00000001 /* RW--V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW 9:9 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_STATUS(i) (0x000E0004-0x000E0000+(i)*1024) /* R--4A */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1 8 /* */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_STATUS_SENT 0:0 /* R-IVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT 0x00000000 /* R-I-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x000E0008-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 8 /* */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x000E000C-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 8 /* */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x000E0010-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 8 /* */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x000E0014-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 8 /* */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x000E0018-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 8 /* */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW(i) (0x000E001C-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW__SIZE_1 8 /* */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_GCP_CTRL(i) (0x000E0040-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC871_SF_HDMI_GCP_CTRL__SIZE_1 8 /* */ +#define NVC871_SF_HDMI_GCP_CTRL_ENABLE 0:0 /* RWIVF */ +#define NVC871_SF_HDMI_GCP_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_GCP_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NVC871_SF_HDMI_GCP_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NVC871_SF_HDMI_GCP_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NVC871_SF_HDMI_GCP_CTRL_OTHER 4:4 /* RWIVF */ +#define NVC871_SF_HDMI_GCP_CTRL_OTHER_DIS 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_GCP_CTRL_OTHER_EN 0x00000001 /* RW--V */ +#define NVC871_SF_HDMI_GCP_CTRL_SINGLE 8:8 /* RWIVF */ +#define NVC871_SF_HDMI_GCP_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_GCP_CTRL_SINGLE_EN 0x00000001 /* RW--V */ +#define NVC871_SF_HDMI_GCP_STATUS(i) (0x000E0044-0x000E0000+(i)*1024) /* R--4A */ +#define NVC871_SF_HDMI_GCP_STATUS__SIZE_1 8 /* */ +#define NVC871_SF_HDMI_GCP_STATUS_SENT 0:0 /* R-IVF */ +#define NVC871_SF_HDMI_GCP_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_SENT_INIT 0x00000000 /* R-I-V */ +#define NVC871_SF_HDMI_GCP_STATUS_ACTIVE_START_PP 6:4 /* R--VF */ +#define NVC871_SF_HDMI_GCP_STATUS_ACTIVE_START_PP_0 0x00000004 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_ACTIVE_START_PP_1 0x00000001 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_ACTIVE_START_PP_2 0x00000002 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_ACTIVE_START_PP_3 0x00000003 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_ACTIVE_END_PP 10:8 /* R--VF */ +#define NVC871_SF_HDMI_GCP_STATUS_ACTIVE_END_PP_0 0x00000004 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_ACTIVE_END_PP_1 0x00000001 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_ACTIVE_END_PP_2 0x00000002 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_ACTIVE_END_PP_3 0x00000003 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_VSYNC_START_PP 14:12 /* R--VF */ +#define NVC871_SF_HDMI_GCP_STATUS_VSYNC_START_PP_0 0x00000004 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_VSYNC_START_PP_1 0x00000001 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_VSYNC_START_PP_2 0x00000002 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_VSYNC_START_PP_3 0x00000003 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_VSYNC_END_PP 18:16 /* R--VF */ +#define NVC871_SF_HDMI_GCP_STATUS_VSYNC_END_PP_0 0x00000004 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_VSYNC_END_PP_1 0x00000001 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_VSYNC_END_PP_2 0x00000002 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_VSYNC_END_PP_3 0x00000003 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_HSYNC_START_PP 22:20 /* R--VF */ +#define NVC871_SF_HDMI_GCP_STATUS_HSYNC_START_PP_0 0x00000004 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_HSYNC_START_PP_1 0x00000001 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_HSYNC_START_PP_2 0x00000002 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_HSYNC_START_PP_3 0x00000003 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_HSYNC_END_PP 26:24 /* R--VF */ +#define NVC871_SF_HDMI_GCP_STATUS_HSYNC_END_PP_0 0x00000004 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_HSYNC_END_PP_1 0x00000001 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_HSYNC_END_PP_2 0x00000002 /* R---V */ +#define NVC871_SF_HDMI_GCP_STATUS_HSYNC_END_PP_3 0x00000003 /* R---V */ +#define NVC871_SF_HDMI_GCP_SUBPACK(i) (0x000E004C-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC871_SF_HDMI_GCP_SUBPACK__SIZE_1 8 /* */ +#define NVC871_SF_HDMI_GCP_SUBPACK_SB0 7:0 /* RWIVF */ +#define NVC871_SF_HDMI_GCP_SUBPACK_SB0_INIT 0x00000001 /* RWI-V */ +#define NVC871_SF_HDMI_GCP_SUBPACK_SB0_SET_AVMUTE 0x00000001 /* RW--V */ +#define NVC871_SF_HDMI_GCP_SUBPACK_SB0_CLR_AVMUTE 0x00000010 /* RW--V */ +#define NVC871_SF_HDMI_GCP_SUBPACK_SB1 15:8 /* RWIVF */ +#define NVC871_SF_HDMI_GCP_SUBPACK_SB1_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_GCP_SUBPACK_SB2 23:16 /* RWIVF */ +#define NVC871_SF_HDMI_GCP_SUBPACK_SB2_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_HDMI_GCP_SUBPACK_SB1_CTRL 24:24 /* RWIVF */ +#define NVC871_SF_HDMI_GCP_SUBPACK_SB1_CTRL_INIT 0x00000001 /* RWI-V */ +#define NVC871_SF_HDMI_GCP_SUBPACK_SB1_CTRL_SW 0x00000000 /* RW--V */ +#define NVC871_SF_HDMI_GCP_SUBPACK_SB1_CTRL_HW 0x00000001 /* RW--V */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL(i,j) (0x000E0130-0x000E0000+(i)*1024+(j)*8) /* RW-4A */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL__SIZE_1 8 /* */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL__SIZE_2 10 /* */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE 3:1 /* RWIVF */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_ALWAYS 0x00000000 /* RWI-V */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_ONCE 0x00000001 /* RW--V */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_ALWAYS 0x00000002 /* RW--V */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_ONCE 0x00000003 /* RW--V */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_TRIGGER 0x00000004 /* RW--V */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL_LOC 5:4 /* RWIVF */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL_LOC_VBLANK 0x00000000 /* RWI-V */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL_LOC_VSYNC 0x00000001 /* RW--V */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL_LOC_LINE 0x00000002 /* RW--V */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL_LOC_LOADV 0x00000003 /* RW--V */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL_OFFSET 10:6 /* RWIVF */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL_SIZE 18:14 /* RWIVF */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL_SIZE_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL_BUSY 22:22 /* R-IVF */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL_BUSY_NO 0x00000000 /* R-I-V */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL_BUSY_YES 0x00000001 /* R---V */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL_SENT 23:23 /* R-IVF */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL_SENT_NO 0x00000000 /* R-I-V */ +#define NVC871_SF_GENERIC_INFOFRAME_CTRL_SENT_YES 0x00000001 /* R---V */ +#define NVC871_SF_GENERIC_INFOFRAME_CONFIG(i,j) (0x000E0134-0x000E0000+(i)*1024+(j)*8) /* RW-4A */ +#define NVC871_SF_GENERIC_INFOFRAME_CONFIG__SIZE_1 8 /* */ +#define NVC871_SF_GENERIC_INFOFRAME_CONFIG__SIZE_2 10 /* */ +#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_FID 7:0 /* RWIVF */ +#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_FID_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID 23:8 /* RWIVF */ +#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED 24:24 /* RWIVF */ +#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED_NO 0x00000000 /* RWI-V */ +#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED_YES 0x00000001 /* RW--V */ +#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_CRC_OVERRIDE 28:28 /* RWIVF */ +#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_CRC_OVERRIDE_NO 0x00000000 /* RWI-V */ +#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_CRC_OVERRIDE_YES 0x00000001 /* RW--V */ +#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM 29:29 /* RWIVF */ +#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM_NO 0x00000000 /* RWI-V */ +#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM_YES 0x00000001 /* RW--V */ +#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_NEW 30:30 /* RWIVF */ +#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_NEW_INIT 0x00000000 /* R-I-V */ +#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_NEW_DONE 0x00000000 /* R---V */ +#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_NEW_PENDING 0x00000001 /* R---V */ +#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_NEW_TRIGGER 0x00000001 /* -W--T */ +#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL 31:31 /* RWIVF */ +#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL_ACT 0x00000000 /* RWI-V */ +#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL_ARM 0x00000001 /* RW--V */ +#define NVC871_SF_GENERIC_INFOFRAME_DATA_CTRL(i) (0x000E03F0-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC871_SF_GENERIC_INFOFRAME_DATA_CTRL__SIZE_1 8 /* */ +#define NVC871_SF_GENERIC_INFOFRAME_DATA_CTRL_OFFSET 4:0 /* RWIVF */ +#define NVC871_SF_GENERIC_INFOFRAME_DATA_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_GENERIC_INFOFRAME_DATA(i) (0x000E03F4-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC871_SF_GENERIC_INFOFRAME_DATA__SIZE_1 8 /* */ +#define NVC871_SF_GENERIC_INFOFRAME_DATA_BYTE0 7:0 /* RWIVF */ +#define NVC871_SF_GENERIC_INFOFRAME_DATA_BYTE0_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_GENERIC_INFOFRAME_DATA_BYTE1 15:8 /* RWIVF */ +#define NVC871_SF_GENERIC_INFOFRAME_DATA_BYTE1_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_GENERIC_INFOFRAME_DATA_BYTE2 23:16 /* RWIVF */ +#define NVC871_SF_GENERIC_INFOFRAME_DATA_BYTE2_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_GENERIC_INFOFRAME_DATA_BYTE3 31:24 /* RWIVF */ +#define NVC871_SF_GENERIC_INFOFRAME_DATA_BYTE3_INIT 0x00000000 /* RWI-V */ +#define NVC871_SF_GENERIC_INFOFRAME_MISC_CTRL(i) (0x000E03F8-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC871_SF_GENERIC_INFOFRAME_MISC_CTRL__SIZE_1 8 /* */ +#define NVC871_SF_GENERIC_INFOFRAME_MISC_CTRL_WIN_CHN_SEL 0:0 /* RWIVF */ +#define NVC871_SF_GENERIC_INFOFRAME_MISC_CTRL_WIN_CHN_SEL_PRIVATE 0x00000000 /* RWI-V */ +#define NVC871_SF_GENERIC_INFOFRAME_MISC_CTRL_WIN_CHN_SEL_PUBLIC 0x00000001 /* RW--V */ +#define NVC871_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY 1:1 /* RWIVF */ +#define NVC871_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY_HIGH 0x00000000 /* RW--V */ +#define NVC871_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY_LOW 0x00000001 /* RWI-V */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _clc871_h_ diff --git a/userspace/sdks/nv570/inc/class/clc873.h b/userspace/sdks/nv570/inc/class/clc873.h new file mode 100644 index 0000000..2d32b6d --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc873.h @@ -0,0 +1,399 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc873_h_ +#define _clc873_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC873_DISP_CAPABILITIES 0xC873 + +typedef volatile struct _clc873_tag0 { + NvU32 dispCapabilities[0x400]; +} _NvC873DispCapabilities,NvC873DispCapabilities_Map ; + + +#define NVC873_SYS_CAP 0x0 /* RW-4R */ +#define NVC873_SYS_CAP_HEAD0_EXISTS 0:0 /* RWIVF */ +#define NVC873_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC873_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC873_SYS_CAP_HEAD1_EXISTS 1:1 /* RWIVF */ +#define NVC873_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC873_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC873_SYS_CAP_HEAD2_EXISTS 2:2 /* RWIVF */ +#define NVC873_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC873_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC873_SYS_CAP_HEAD3_EXISTS 3:3 /* RWIVF */ +#define NVC873_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC873_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC873_SYS_CAP_HEAD4_EXISTS 4:4 /* RWIVF */ +#define NVC873_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC873_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC873_SYS_CAP_HEAD5_EXISTS 5:5 /* RWIVF */ +#define NVC873_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC873_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC873_SYS_CAP_HEAD6_EXISTS 6:6 /* RWIVF */ +#define NVC873_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC873_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC873_SYS_CAP_HEAD7_EXISTS 7:7 /* RWIVF */ +#define NVC873_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC873_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC873_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVC873_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */ +#define NVC873_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC873_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC873_SYS_CAP_SOR0_EXISTS 8:8 /* RWIVF */ +#define NVC873_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC873_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC873_SYS_CAP_SOR1_EXISTS 9:9 /* RWIVF */ +#define NVC873_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC873_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC873_SYS_CAP_SOR2_EXISTS 10:10 /* RWIVF */ +#define NVC873_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC873_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC873_SYS_CAP_SOR3_EXISTS 11:11 /* RWIVF */ +#define NVC873_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC873_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC873_SYS_CAP_SOR4_EXISTS 12:12 /* RWIVF */ +#define NVC873_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC873_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC873_SYS_CAP_SOR5_EXISTS 13:13 /* RWIVF */ +#define NVC873_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC873_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC873_SYS_CAP_SOR6_EXISTS 14:14 /* RWIVF */ +#define NVC873_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC873_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC873_SYS_CAP_SOR7_EXISTS 15:15 /* RWIVF */ +#define NVC873_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC873_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC873_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* RWIVF */ +#define NVC873_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */ +#define NVC873_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC873_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC873_SYS_CAP_DSI0_EXISTS 20:20 /* RWIVF */ +#define NVC873_SYS_CAP_DSI0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC873_SYS_CAP_DSI0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC873_SYS_CAP_DSI1_EXISTS 21:21 /* RWIVF */ +#define NVC873_SYS_CAP_DSI1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC873_SYS_CAP_DSI1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC873_SYS_CAP_DSI2_EXISTS 22:22 /* RWIVF */ +#define NVC873_SYS_CAP_DSI2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC873_SYS_CAP_DSI2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC873_SYS_CAP_DSI3_EXISTS 23:23 /* RWIVF */ +#define NVC873_SYS_CAP_DSI3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC873_SYS_CAP_DSI3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC873_SYS_CAP_DSI_EXISTS(i) (20+(i)):(20+(i)) /* RWIVF */ +#define NVC873_SYS_CAP_DSI_EXISTS__SIZE_1 4 /* */ +#define NVC873_SYS_CAP_DSI_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC873_SYS_CAP_DSI_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPA 0x10 /* RW-4R */ +#define NVC873_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES 15:0 /* RWIUF */ +#define NVC873_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH 17:16 /* RWIVF */ +#define NVC873_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B 0x00000000 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B 0x00000001 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B 0x00000002 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B 0x00000003 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPA_SUPPORT_ROTATION 18:18 /* RWIVF */ +#define NVC873_IHUB_COMMON_CAPA_SUPPORT_ROTATION_FALSE 0x00000000 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPA_SUPPORT_ROTATION_TRUE 0x00000001 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPA_SUPPORT_PLANAR 19:19 /* RWIVF */ +#define NVC873_IHUB_COMMON_CAPA_SUPPORT_PLANAR_FALSE 0x00000000 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPA_SUPPORT_PLANAR_TRUE 0x00000001 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPA_SUPPORT_VGA 20:20 /* RWIVF */ +#define NVC873_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE 0x00000000 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE 0x00000001 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION 21:21 /* RWIVF */ +#define NVC873_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_FALSE 0x00000000 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_TRUE 0x00000001 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPA_SUPPORT_MSCG 22:22 /* RWIVF */ +#define NVC873_IHUB_COMMON_CAPA_SUPPORT_MSCG_FALSE 0x00000000 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPA_SUPPORT_MSCG_TRUE 0x00000001 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH 23:23 /* RWIVF */ +#define NVC873_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_FALSE 0x00000000 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_TRUE 0x00000001 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT 26:26 /* RWIVF */ +#define NVC873_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_FALSE 0x00000000 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_TRUE 0x00000001 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION 31:30 /* RWIVF */ +#define NVC873_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B 0x00000000 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B 0x00000001 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B 0x00000002 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B 0x00000003 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPC 0x18 /* RW-4R */ +#define NVC873_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE 1:0 /* RWIVF */ +#define NVC873_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_32B 0x00000000 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_64B 0x00000001 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_128B 0x00000002 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_256B 0x00000003 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED 6:4 /* RWIVF */ +#define NVC873_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_NONE 0x00000000 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_TWO 0x00000001 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_FOUR 0x00000002 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_EIGHT 0x00000003 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_SIXTEEN 0x00000004 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR 11:11 /* RWIVF */ +#define NVC873_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_FALSE 0x00000000 /* RWI-V */ +#define NVC873_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_TRUE 0x00000001 /* RW--V */ +#define NVC873_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP 12:12 /* RWIVF */ +#define NVC873_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_FALSE 0x00000000 /* RWI-V */ +#define NVC873_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_TRUE 0x00000001 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA(i) (0x680+(i)*32) /* RW-4A */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA__SIZE_1 8 /* */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT 16:16 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT 17:17 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT 18:18 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT 19:19 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT 20:20 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT 21:21 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT 22:22 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT 23:23 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT 24:24 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPB(i) (0x684+(i)*32) /* RW-4A */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPB__SIZE_1 8 /* */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPB_VGA 0:0 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPB_VGA_TRUE 0x00000001 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPB_VGA_FALSE 0x00000000 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGSZ 9:6 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGNR 12:10 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT 15:15 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPC(i) (0x688+(i)*32) /* RW-4A */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPC__SIZE_1 8 /* */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPC_OCSC0_PRECISION 4:0 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPC_OCSC1_PRECISION 12:8 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP 13:13 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPC_SCLR_SF_PRECISION 20:16 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPC_SCLR_CI_PRECISION 24:21 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB 25:25 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPD(i) (0x68c+(i)*32) /* RW-4A */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPD__SIZE_1 8 /* */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPE(i) (0x690+(i)*32) /* RW-4A */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPE__SIZE_1 8 /* */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPE_DSC_RATEBUFSIZE 3:0 /* RWIUF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPE_DSC_LINEBUFSIZE 13:8 /* RWIUF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422 16:16 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_TRUE 0x00000001 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_FALSE 0x00000000 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420 17:17 /* RWIVF */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_TRUE 0x00000001 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_FALSE 0x00000000 /* RW--V */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPF(i) (0x694+(i)*32) /* RW-4A */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPF__SIZE_1 8 /* */ +#define NVC873_POSTCOMP_HEAD_HDR_CAPF_VFILTER_MAX_PIXELS 15:0 /* RWIVF */ +#define NVC873_SOR_CAP(i) (0x144+(i)*8) /* RW-4A */ +#define NVC873_SOR_CAP__SIZE_1 8 /* */ +#define NVC873_SOR_CAP_SINGLE_LVDS_18 0:0 /* RWIVF */ +#define NVC873_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVC873_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVC873_SOR_CAP_SINGLE_LVDS_24 1:1 /* RWIVF */ +#define NVC873_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVC873_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVC873_SOR_CAP_DUAL_LVDS_18 2:2 /* RWIVF */ +#define NVC873_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVC873_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVC873_SOR_CAP_DUAL_LVDS_24 3:3 /* RWIVF */ +#define NVC873_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVC873_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVC873_SOR_CAP_SINGLE_TMDS_A 8:8 /* RWIVF */ +#define NVC873_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* RW--V */ +#define NVC873_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* RW--V */ +#define NVC873_SOR_CAP_SINGLE_TMDS_B 9:9 /* RWIVF */ +#define NVC873_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* RW--V */ +#define NVC873_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* RW--V */ +#define NVC873_SOR_CAP_DUAL_TMDS 11:11 /* RWIVF */ +#define NVC873_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* RW--V */ +#define NVC873_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* RW--V */ +#define NVC873_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* RWIVF */ +#define NVC873_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* RW--V */ +#define NVC873_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* RW--V */ +#define NVC873_SOR_CAP_SDI 16:16 /* RWIVF */ +#define NVC873_SOR_CAP_SDI_FALSE 0x00000000 /* RW--V */ +#define NVC873_SOR_CAP_SDI_TRUE 0x00000001 /* RW--V */ +#define NVC873_SOR_CAP_DP_A 24:24 /* RWIVF */ +#define NVC873_SOR_CAP_DP_A_FALSE 0x00000000 /* RW--V */ +#define NVC873_SOR_CAP_DP_A_TRUE 0x00000001 /* RW--V */ +#define NVC873_SOR_CAP_DP_B 25:25 /* RWIVF */ +#define NVC873_SOR_CAP_DP_B_FALSE 0x00000000 /* RW--V */ +#define NVC873_SOR_CAP_DP_B_TRUE 0x00000001 /* RW--V */ +#define NVC873_SOR_CAP_DP_INTERLACE 26:26 /* RWIVF */ +#define NVC873_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* RW--V */ +#define NVC873_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* RW--V */ +#define NVC873_SOR_CAP_DP_8_LANES 27:27 /* RWIVF */ +#define NVC873_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* RW--V */ +#define NVC873_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* RW--V */ +#define NVC873_SOR_CAP_HDMI_FRL 28:28 /* RWIVF */ +#define NVC873_SOR_CAP_HDMI_FRL_FALSE 0x00000000 /* RW--V */ +#define NVC873_SOR_CAP_HDMI_FRL_TRUE 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA(i) (0x780+(i)*32) /* RW-4A */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA__SIZE_1 32 /* */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH 13:10 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT 16:16 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT 17:17 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT 18:18 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT 19:19 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT 20:20 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT 21:21 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT 22:22 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT 23:23 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT 24:24 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPB(i) (0x784+(i)*32) /* RW-4A */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPB__SIZE_1 32 /* */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION 4:0 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ 9:6 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR 12:10 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT 15:15 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC(i) (0x788+(i)*32) /* RW-4A */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC__SIZE_1 32 /* */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION 4:0 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGSZ 9:6 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGNR 12:10 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT 15:15 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION 20:16 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP 21:21 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD(i) (0x78c+(i)*32) /* RW-4A */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD__SIZE_1 32 /* */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ 3:0 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR 6:4 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD 8:8 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT 9:9 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION 16:12 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION 20:17 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB 21:21 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA 22:22 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_TRUE 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_FALSE 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE(i) (0x790+(i)*32) /* RW-4A */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE__SIZE_1 32 /* */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION 4:0 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGSZ 9:6 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGNR 12:10 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT 15:15 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION 20:16 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP 21:21 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPF(i) (0x794+(i)*32) /* RW-4A */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPF__SIZE_1 32 /* */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */ +#define NVC873_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */ + +#ifdef __cplusplus +}; +#endif /* extern C */ +#endif //_clc873_h_ diff --git a/userspace/sdks/nv570/inc/class/clc87a.h b/userspace/sdks/nv570/inc/class/clc87a.h new file mode 100644 index 0000000..cadb2ae --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc87a.h @@ -0,0 +1,180 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc87a__h_ +#define _clc87a__h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC87A_CURSOR_IMM_CHANNEL_PIO (0x0000C87A) + +typedef volatile struct _clc87a_tag0 { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x7D]; + NvV32 Update; // 0x00000200 - 0x00000203 + NvV32 SetInterlockFlags; // 0x00000204 - 0x00000207 + NvV32 SetCursorHotSpotPointOut[2]; // 0x00000208 - 0x0000020F + NvV32 SetWindowInterlockFlags; // 0x00000210 - 0x00000213 + NvV32 Reserved02[0x37B]; +} NVC87ADispCursorImmControlPio; + +#define NVC87A_FREE (0x00000008) +#define NVC87A_FREE_COUNT 5:0 +#define NVC87A_UPDATE (0x00000200) +#define NVC87A_SET_INTERLOCK_FLAGS (0x00000204) +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC87A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC87A_SET_CURSOR_HOT_SPOT_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVC87A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0 +#define NVC87A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS (0x00000210) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC87A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc87a_h + diff --git a/userspace/sdks/nv570/inc/class/clc87b.h b/userspace/sdks/nv570/inc/class/clc87b.h new file mode 100644 index 0000000..608e7e9 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc87b.h @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clC87b_h_ +#define _clC87b_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC87B_WINDOW_IMM_CHANNEL_DMA (0x0000C87B) + +// dma opcode instructions +#define NVC87B_DMA +#define NVC87B_DMA_OPCODE 31:29 +#define NVC87B_DMA_OPCODE_METHOD 0x00000000 +#define NVC87B_DMA_OPCODE_JUMP 0x00000001 +#define NVC87B_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC87B_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC87B_DMA_METHOD_COUNT 27:18 +#define NVC87B_DMA_METHOD_OFFSET 13:2 +#define NVC87B_DMA_DATA 31:0 +#define NVC87B_DMA_DATA_NOP 0x00000000 +#define NVC87B_DMA_JUMP_OFFSET 11:2 +#define NVC87B_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVC87B_PUT (0x00000000) +#define NVC87B_PUT_PTR 9:0 +#define NVC87B_GET (0x00000004) +#define NVC87B_GET_PTR 9:0 +#define NVC87B_UPDATE (0x00000200) +#define NVC87B_UPDATE_INTERLOCK_WITH_WINDOW 1:1 +#define NVC87B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC87B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC87B_SET_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVC87B_SET_POINT_OUT_X 15:0 +#define NVC87B_SET_POINT_OUT_Y 31:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC87b_h diff --git a/userspace/sdks/nv570/inc/class/clc87d.h b/userspace/sdks/nv570/inc/class/clc87d.h new file mode 100644 index 0000000..1472a94 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc87d.h @@ -0,0 +1,1341 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clC87d_h_ +#define _clC87d_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC87D_CORE_CHANNEL_DMA (0x0000C87D) + +#define NV_DISP_NOTIFIER 0x00000000 +#define NV_DISP_NOTIFIER_SIZEOF 0x00000010 +#define NV_DISP_NOTIFIER__0 0x00000000 +#define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFIER__0_FIELD 8:8 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE 9:9 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001 +#define NV_DISP_NOTIFIER__0_R1 15:10 +#define NV_DISP_NOTIFIER__0_R2 23:16 +#define NV_DISP_NOTIFIER__0_R3 29:24 +#define NV_DISP_NOTIFIER__0_STATUS 31:30 +#define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002 +#define NV_DISP_NOTIFIER__1 0x00000001 +#define NV_DISP_NOTIFIER__1_R4 31:0 +#define NV_DISP_NOTIFIER__2 0x00000002 +#define NV_DISP_NOTIFIER__2_TIMESTAMP_LO 31:0 +#define NV_DISP_NOTIFIER__3 0x00000003 +#define NV_DISP_NOTIFIER__3_TIMESTAMP_HI 31:0 + + +// dma opcode instructions +#define NVC87D_DMA +#define NVC87D_DMA_OPCODE 31:29 +#define NVC87D_DMA_OPCODE_METHOD 0x00000000 +#define NVC87D_DMA_OPCODE_JUMP 0x00000001 +#define NVC87D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC87D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC87D_DMA_METHOD_COUNT 27:18 +#define NVC87D_DMA_METHOD_OFFSET 13:2 +#define NVC87D_DMA_DATA 31:0 +#define NVC87D_DMA_DATA_NOP 0x00000000 +#define NVC87D_DMA_JUMP_OFFSET 11:2 +#define NVC87D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// if cap SUPPORT_FLEXIBLE_WIN_MAPPING is FALSE, this define can be used to obtain which head a window is mapped to +#define NVC37D_WINDOW_MAPPED_TO_HEAD(w) ((w)>>1) +#define NVC37D_GET_VALID_WINDOWMASK_FOR_HEAD(h) ((1<<((h)*2)) | (1<<((h)*2+1))) + +// class methods +#define NVC87D_PUT (0x00000000) +#define NVC87D_PUT_PTR 9:0 +#define NVC87D_GET (0x00000004) +#define NVC87D_GET_PTR 9:0 +#define NVC87D_UPDATE (0x00000200) +#define NVC87D_UPDATE_SPECIAL_HANDLING 21:20 +#define NVC87D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NVC87D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NVC87D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NVC87D_UPDATE_SPECIAL_HANDLING_REASON 19:12 +#define NVC87D_UPDATE_INHIBIT_INTERRUPTS 24:24 +#define NVC87D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NVC87D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NVC87D_UPDATE_RELEASE_ELV 0:0 +#define NVC87D_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC87D_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC87D_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC87D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC87D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC87D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC87D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC87D_SET_CONTEXT_DMA_NOTIFIER (0x00000208) +#define NVC87D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NVC87D_SET_NOTIFIER_CONTROL (0x0000020C) +#define NVC87D_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC87D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC87D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC87D_SET_NOTIFIER_CONTROL_OFFSET 11:4 +#define NVC87D_SET_NOTIFIER_CONTROL_NOTIFY 12:12 +#define NVC87D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NVC87D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NVC87D_SET_CONTROL (0x00000210) +#define NVC87D_SET_CONTROL_FLIP_LOCK_PIN(i) ((i)+0):((i)+0) +#define NVC87D_SET_CONTROL_FLIP_LOCK_PIN__SIZE_1 4 +#define NVC87D_SET_CONTROL_FLIP_LOCK_PIN_DISABLE (0x00000000) +#define NVC87D_SET_CONTROL_FLIP_LOCK_PIN_ENABLE (0x00000001) +#define NVC87D_SET_CONTROL_FLIP_LOCK_PIN0 0:0 +#define NVC87D_SET_CONTROL_FLIP_LOCK_PIN0_DISABLE (0x00000000) +#define NVC87D_SET_CONTROL_FLIP_LOCK_PIN0_ENABLE (0x00000001) +#define NVC87D_SET_CONTROL_FLIP_LOCK_PIN1 1:1 +#define NVC87D_SET_CONTROL_FLIP_LOCK_PIN1_DISABLE (0x00000000) +#define NVC87D_SET_CONTROL_FLIP_LOCK_PIN1_ENABLE (0x00000001) +#define NVC87D_SET_CONTROL_FLIP_LOCK_PIN2 2:2 +#define NVC87D_SET_CONTROL_FLIP_LOCK_PIN2_DISABLE (0x00000000) +#define NVC87D_SET_CONTROL_FLIP_LOCK_PIN2_ENABLE (0x00000001) +#define NVC87D_SET_CONTROL_FLIP_LOCK_PIN3 3:3 +#define NVC87D_SET_CONTROL_FLIP_LOCK_PIN3_DISABLE (0x00000000) +#define NVC87D_SET_CONTROL_FLIP_LOCK_PIN3_ENABLE (0x00000001) +#define NVC87D_SET_INTERLOCK_FLAGS (0x00000218) +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+0):((i)+0) +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC87D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS (0x0000021C) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC87D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVC87D_GET_RG_SCAN_LINE(b) (0x00000220 + (b)*0x00000004) +#define NVC87D_GET_RG_SCAN_LINE_LINE 15:0 +#define NVC87D_GET_RG_SCAN_LINE_VBLANK 16:16 +#define NVC87D_GET_RG_SCAN_LINE_VBLANK_FALSE (0x00000000) +#define NVC87D_GET_RG_SCAN_LINE_VBLANK_TRUE (0x00000001) +#define NVC87D_SET_GET_BLANKING_CTRL(b) (0x00000240 + (b)*0x00000004) +#define NVC87D_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NVC87D_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NVC87D_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NVC87D_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NVC87D_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NVC87D_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) + +#define NVC87D_SOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NVC87D_SOR_SET_CONTROL_OWNER_MASK 7:0 +#define NVC87D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVC87D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVC87D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVC87D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVC87D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVC87D_SOR_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVC87D_SOR_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVC87D_SOR_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVC87D_SOR_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVC87D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NVC87D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NVC87D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NVC87D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NVC87D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NVC87D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NVC87D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NVC87D_SOR_SET_CONTROL_PROTOCOL_HDMI_FRL (0x0000000C) +#define NVC87D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NVC87D_SOR_SET_CONTROL_DE_SYNC_POLARITY 16:16 +#define NVC87D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC87D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC87D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NVC87D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NVC87D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NVC87D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NVC87D_SOR_SET_CUSTOM_REASON(a) (0x00000304 + (a)*0x00000020) +#define NVC87D_SOR_SET_CUSTOM_REASON_CODE 31:0 +#define NVC87D_SOR_SET_SW_SPARE_A(a) (0x00000308 + (a)*0x00000020) +#define NVC87D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NVC87D_SOR_SET_SW_SPARE_B(a) (0x0000030C + (a)*0x00000020) +#define NVC87D_SOR_SET_SW_SPARE_B_CODE 31:0 + +#define NVC87D_DSI_SET_CONTROL(a) (0x00000500 + (a)*0x00000020) +#define NVC87D_DSI_SET_CONTROL_OWNER_MASK 7:0 +#define NVC87D_DSI_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVC87D_DSI_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVC87D_DSI_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVC87D_DSI_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVC87D_DSI_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVC87D_DSI_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVC87D_DSI_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVC87D_DSI_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVC87D_DSI_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVC87D_DSI_SET_CUSTOM_REASON(a) (0x00000504 + (a)*0x00000020) +#define NVC87D_DSI_SET_CUSTOM_REASON_CODE 31:0 +#define NVC87D_DSI_SET_SW_SPARE_A(a) (0x00000508 + (a)*0x00000020) +#define NVC87D_DSI_SET_SW_SPARE_A_CODE 31:0 +#define NVC87D_DSI_SET_SW_SPARE_B(a) (0x0000050C + (a)*0x00000020) +#define NVC87D_DSI_SET_SW_SPARE_B_CODE 31:0 + +#define NVC87D_WINDOW_SET_CONTROL(a) (0x00001000 + (a)*0x00000080) +#define NVC87D_WINDOW_SET_CONTROL_OWNER 3:0 +#define NVC87D_WINDOW_SET_CONTROL_OWNER_HEAD(i) (0x00000000 +(i)) +#define NVC87D_WINDOW_SET_CONTROL_OWNER_HEAD__SIZE_1 8 +#define NVC87D_WINDOW_SET_CONTROL_OWNER_HEAD0 (0x00000000) +#define NVC87D_WINDOW_SET_CONTROL_OWNER_HEAD1 (0x00000001) +#define NVC87D_WINDOW_SET_CONTROL_OWNER_HEAD2 (0x00000002) +#define NVC87D_WINDOW_SET_CONTROL_OWNER_HEAD3 (0x00000003) +#define NVC87D_WINDOW_SET_CONTROL_OWNER_HEAD4 (0x00000004) +#define NVC87D_WINDOW_SET_CONTROL_OWNER_HEAD5 (0x00000005) +#define NVC87D_WINDOW_SET_CONTROL_OWNER_HEAD6 (0x00000006) +#define NVC87D_WINDOW_SET_CONTROL_OWNER_HEAD7 (0x00000007) +#define NVC87D_WINDOW_SET_CONTROL_OWNER_NONE (0x0000000F) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0x00000080) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a) (0x00001008 + (a)*0x00000080) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR(a) (0x0000100C + (a)*0x00000080) +#define NVC87D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVC87D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVC87D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a) (0x00001010 + (a)*0x00000080) +#define NVC87D_WINDOW_SET_WINDOW_USAGE_BOUNDS_MAX_PIXELS_FETCHED_PER_LINE 14:0 +#define NVC87D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED 16:16 +#define NVC87D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED 28:28 +#define NVC87D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS 22:20 +#define NVC87D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVC87D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED 24:24 +#define NVC87D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVC87D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED 30:30 +#define NVC87D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED_FALSE (0x00000000) +#define NVC87D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED_TRUE (0x00000001) + +#define NVC87D_HEAD_SET_PROCAMP(a) (0x00002000 + (a)*0x00000400) +#define NVC87D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NVC87D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NVC87D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NVC87D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NVC87D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003) +#define NVC87D_HEAD_SET_PROCAMP_CHROMA_LPF 3:3 +#define NVC87D_HEAD_SET_PROCAMP_CHROMA_LPF_DISABLE (0x00000000) +#define NVC87D_HEAD_SET_PROCAMP_CHROMA_LPF_ENABLE (0x00000001) +#define NVC87D_HEAD_SET_PROCAMP_CHROMA_DOWN_V 4:4 +#define NVC87D_HEAD_SET_PROCAMP_CHROMA_DOWN_V_DISABLE (0x00000000) +#define NVC87D_HEAD_SET_PROCAMP_CHROMA_DOWN_V_ENABLE (0x00000001) +#define NVC87D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 28:28 +#define NVC87D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NVC87D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00002004 + (a)*0x00000400) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 2:2 +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 3:3 +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 7:4 +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000000) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000001) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000002) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000003) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000004) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000005) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000006) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000007) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000008) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_444 (0x00000009) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444NP (0x0000000A) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 24:24 +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 23:12 +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN 31:26 +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN0 (0x00000000) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN1 (0x00000001) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN2 (0x00000002) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN3 (0x00000003) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN4 (0x00000004) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN5 (0x00000005) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN6 (0x00000006) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN7 (0x00000007) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN8 (0x00000008) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN9 (0x00000009) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN10 (0x0000000A) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN11 (0x0000000B) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN12 (0x0000000C) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN13 (0x0000000D) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN14 (0x0000000E) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN15 (0x0000000F) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN16 (0x00000010) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN17 (0x00000011) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN18 (0x00000012) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN19 (0x00000013) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN20 (0x00000014) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN21 (0x00000015) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN22 (0x00000016) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN23 (0x00000017) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN24 (0x00000018) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN25 (0x00000019) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN26 (0x0000001A) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN27 (0x0000001B) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN28 (0x0000001C) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN29 (0x0000001D) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN30 (0x0000001E) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN31 (0x0000001F) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_NONE (0x0000003F) +#define NVC87D_HEAD_SET_CONTROL(a) (0x00002008 + (a)*0x00000400) +#define NVC87D_HEAD_SET_CONTROL_STRUCTURE 1:0 +#define NVC87D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NVC87D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE 2:2 +#define NVC87D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_NORMAL (0x00000000) +#define NVC87D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000001) +#define NVC87D_HEAD_SET_CONTROL_YUV420PACKER 3:3 +#define NVC87D_HEAD_SET_CONTROL_YUV420PACKER_DISABLE (0x00000000) +#define NVC87D_HEAD_SET_CONTROL_YUV420PACKER_ENABLE (0x00000001) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 11:10 +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 8:4 +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 15:12 +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 23:22 +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 20:16 +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC87D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN 28:24 +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000001) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000002) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000003) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000004) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000005) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000006) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000007) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000008) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000009) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000B) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000C) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000D) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000E) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000F) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x00000010) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC87D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NVC87D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVC87D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVC87D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NVC87D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVC87D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVC87D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x0000200C + (a)*0x00000400) +#define NVC87D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NVC87D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NVC87D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC87D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC87D_HEAD_SET_PIXEL_REORDER_CONTROL(a) (0x00002010 + (a)*0x00000400) +#define NVC87D_HEAD_SET_PIXEL_REORDER_CONTROL_BANK_WIDTH 13:0 +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00002014 + (a)*0x00000400) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVC87D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVC87D_HEAD_SET_DITHER_CONTROL(a) (0x00002018 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NVC87D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC87D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC87D_HEAD_SET_DITHER_CONTROL_BITS 5:4 +#define NVC87D_HEAD_SET_DITHER_CONTROL_BITS_TO_6_BITS (0x00000000) +#define NVC87D_HEAD_SET_DITHER_CONTROL_BITS_TO_8_BITS (0x00000001) +#define NVC87D_HEAD_SET_DITHER_CONTROL_BITS_TO_10_BITS (0x00000002) +#define NVC87D_HEAD_SET_DITHER_CONTROL_BITS_TO_12_BITS (0x00000003) +#define NVC87D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE 2:2 +#define NVC87D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_DISABLE (0x00000000) +#define NVC87D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_ENABLE (0x00000001) +#define NVC87D_HEAD_SET_DITHER_CONTROL_MODE 10:8 +#define NVC87D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NVC87D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NVC87D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NVC87D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NVC87D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NVC87D_HEAD_SET_DITHER_CONTROL_MODE_ROUND (0x00000005) +#define NVC87D_HEAD_SET_DITHER_CONTROL_PHASE 13:12 +#define NVC87D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x0000201C + (a)*0x00000400) +#define NVC87D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 0:0 +#define NVC87D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NVC87D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NVC87D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING 4:4 +#define NVC87D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_DISABLE (0x00000000) +#define NVC87D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_ENABLE (0x00000001) +#define NVC87D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 9:8 +#define NVC87D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NVC87D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NVC87D_HEAD_SET_DISPLAY_ID(a,b) (0x00002020 + (a)*0x00000400 + (b)*0x00000004) +#define NVC87D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NVC87D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00002028 + (a)*0x00000400) +#define NVC87D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NVC87D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NVC87D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC87D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC87D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR(a) (0x0000202C + (a)*0x00000400) +#define NVC87D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVC87D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVC87D_HEAD_SET_HEAD_USAGE_BOUNDS(a) (0x00002030 + (a)*0x00000400) +#define NVC87D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR 2:0 +#define NVC87D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_NONE (0x00000000) +#define NVC87D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W32_H32 (0x00000001) +#define NVC87D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W64_H64 (0x00000002) +#define NVC87D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W128_H128 (0x00000003) +#define NVC87D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W256_H256 (0x00000004) +#define NVC87D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED 4:4 +#define NVC87D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_FALSE (0x00000000) +#define NVC87D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_TRUE (0x00000001) +#define NVC87D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS 14:12 +#define NVC87D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVC87D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVC87D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED 8:8 +#define NVC87D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC87D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVC87D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED 16:16 +#define NVC87D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED_FALSE (0x00000000) +#define NVC87D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED_TRUE (0x00000001) +#define NVC87D_HEAD_SET_STALL_LOCK(a) (0x00002034 + (a)*0x00000400) +#define NVC87D_HEAD_SET_STALL_LOCK_ENABLE 0:0 +#define NVC87D_HEAD_SET_STALL_LOCK_ENABLE_FALSE (0x00000000) +#define NVC87D_HEAD_SET_STALL_LOCK_ENABLE_TRUE (0x00000001) +#define NVC87D_HEAD_SET_STALL_LOCK_MODE 2:2 +#define NVC87D_HEAD_SET_STALL_LOCK_MODE_CONTINUOUS (0x00000000) +#define NVC87D_HEAD_SET_STALL_LOCK_MODE_ONE_SHOT (0x00000001) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN 8:4 +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC87D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC87D_HEAD_SET_STALL_LOCK_UNSTALL_MODE 12:12 +#define NVC87D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_CRASH_LOCK (0x00000000) +#define NVC87D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_LINE_LOCK (0x00000001) +#define NVC87D_HEAD_SET_STALL_LOCK_TEPOLARITY 14:14 +#define NVC87D_HEAD_SET_STALL_LOCK_TEPOLARITY_POSITIVE_TRUE (0x00000000) +#define NVC87D_HEAD_SET_STALL_LOCK_TEPOLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC87D_HEAD_SET_STALL_LOCK_UNSTALL_SYNC_ADVANCE 25:16 +#define NVC87D_HEAD_SET_LOCK_CHAIN(a) (0x00002044 + (a)*0x00000400) +#define NVC87D_HEAD_SET_LOCK_CHAIN_POSITION 3:0 +#define NVC87D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x00002048 + (a)*0x00000400) +#define NVC87D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NVC87D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NVC87D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x0000204C + (a)*0x00000400) +#define NVC87D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NVC87D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NVC87D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x00002058 + (a)*0x00000400) +#define NVC87D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NVC87D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NVC87D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x0000205C + (a)*0x00000400) +#define NVC87D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NVC87D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NVC87D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000400) +#define NVC87D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NVC87D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NVC87D_HEAD_SET_RASTER_SYNC_END(a) (0x00002068 + (a)*0x00000400) +#define NVC87D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NVC87D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NVC87D_HEAD_SET_RASTER_BLANK_END(a) (0x0000206C + (a)*0x00000400) +#define NVC87D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NVC87D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NVC87D_HEAD_SET_RASTER_BLANK_START(a) (0x00002070 + (a)*0x00000400) +#define NVC87D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NVC87D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NVC87D_HEAD_SET_OVERSCAN_COLOR(a) (0x00002078 + (a)*0x00000400) +#define NVC87D_HEAD_SET_OVERSCAN_COLOR_RED_CR 9:0 +#define NVC87D_HEAD_SET_OVERSCAN_COLOR_GREEN_Y 19:10 +#define NVC87D_HEAD_SET_OVERSCAN_COLOR_BLUE_CB 29:20 +#define NVC87D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR(a) (0x0000207C + (a)*0x00000400) +#define NVC87D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_RED_CR 9:0 +#define NVC87D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_GREEN_Y 19:10 +#define NVC87D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_BLUE_CB 29:20 +#define NVC87D_HEAD_SET_HDMI_CTRL(a) (0x00002080 + (a)*0x00000400) +#define NVC87D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NVC87D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NVC87D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NVC87D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NVC87D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NVC87D_HEAD_SET_CONTEXT_DMA_CURSOR(a,b) (0x00002088 + (a)*0x00000400 + (b)*0x00000004) +#define NVC87D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0 +#define NVC87D_HEAD_SET_OFFSET_CURSOR(a,b) (0x00002090 + (a)*0x00000400 + (b)*0x00000004) +#define NVC87D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0 +#define NVC87D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x00002098 + (a)*0x00000400) +#define NVC87D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 0:0 +#define NVC87D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NVC87D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NVC87D_HEAD_SET_CONTROL_CURSOR(a) (0x0000209C + (a)*0x00000400) +#define NVC87D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NVC87D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NVC87D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NVC87D_HEAD_SET_CONTROL_CURSOR_FORMAT 7:0 +#define NVC87D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC87D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC87D_HEAD_SET_CONTROL_CURSOR_SIZE 9:8 +#define NVC87D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NVC87D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NVC87D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NVC87D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NVC87D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 19:12 +#define NVC87D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 27:20 +#define NVC87D_HEAD_SET_CONTROL_CURSOR_COMPOSITION(a) (0x000020A0 + (a)*0x00000400) +#define NVC87D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_K1 7:0 +#define NVC87D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT 11:8 +#define NVC87D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC87D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC87D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT 15:12 +#define NVC87D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_ZERO (0x00000000) +#define NVC87D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC87D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC87D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE 16:16 +#define NVC87D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_BLEND (0x00000000) +#define NVC87D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_XOR (0x00000001) +#define NVC87D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS 20:20 +#define NVC87D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_DISABLE (0x00000000) +#define NVC87D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_ENABLE (0x00000001) +#define NVC87D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00002180 + (a)*0x00000400) +#define NVC87D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NVC87D_HEAD_SET_CRC_CONTROL(a) (0x00002184 + (a)*0x00000400) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 5:0 +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_0 (0x00000000) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_1 (0x00000001) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_2 (0x00000002) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_3 (0x00000003) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_4 (0x00000004) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_5 (0x00000005) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_6 (0x00000006) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_7 (0x00000007) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_8 (0x00000008) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_9 (0x00000009) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_10 (0x0000000A) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_11 (0x0000000B) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_12 (0x0000000C) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_13 (0x0000000D) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_14 (0x0000000E) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_15 (0x0000000F) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_16 (0x00000010) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_17 (0x00000011) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_18 (0x00000012) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_19 (0x00000013) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_20 (0x00000014) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_21 (0x00000015) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_22 (0x00000016) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_23 (0x00000017) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_24 (0x00000018) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_25 (0x00000019) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_26 (0x0000001A) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_27 (0x0000001B) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_28 (0x0000001C) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_29 (0x0000001D) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_30 (0x0000001E) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_31 (0x0000001F) +#define NVC87D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000020) +#define NVC87D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 8:8 +#define NVC87D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NVC87D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NVC87D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC 19:12 +#define NVC87D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_NONE (0x00000000) +#define NVC87D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SF (0x00000030) +#define NVC87D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC87D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR__SIZE_1 8 +#define NVC87D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR0 (0x00000050) +#define NVC87D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR1 (0x00000051) +#define NVC87D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR2 (0x00000052) +#define NVC87D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR3 (0x00000053) +#define NVC87D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR4 (0x00000054) +#define NVC87D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR5 (0x00000055) +#define NVC87D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR6 (0x00000056) +#define NVC87D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR7 (0x00000057) +#define NVC87D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC 27:20 +#define NVC87D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_NONE (0x00000000) +#define NVC87D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SF (0x00000030) +#define NVC87D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC87D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR__SIZE_1 8 +#define NVC87D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR0 (0x00000050) +#define NVC87D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR1 (0x00000051) +#define NVC87D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR2 (0x00000052) +#define NVC87D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR3 (0x00000053) +#define NVC87D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR4 (0x00000054) +#define NVC87D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR5 (0x00000055) +#define NVC87D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR6 (0x00000056) +#define NVC87D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR7 (0x00000057) +#define NVC87D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 9:9 +#define NVC87D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NVC87D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NVC87D_HEAD_SET_PRESENT_CONTROL(a) (0x0000218C + (a)*0x00000400) +#define NVC87D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 0:0 +#define NVC87D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NVC87D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NVC87D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NVC87D_HEAD_SET_SW_SPARE_A(a) (0x00002194 + (a)*0x00000400) +#define NVC87D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NVC87D_HEAD_SET_SW_SPARE_B(a) (0x00002198 + (a)*0x00000400) +#define NVC87D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NVC87D_HEAD_SET_SW_SPARE_C(a) (0x0000219C + (a)*0x00000400) +#define NVC87D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NVC87D_HEAD_SET_SW_SPARE_D(a) (0x000021A0 + (a)*0x00000400) +#define NVC87D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NVC87D_HEAD_SET_DISPLAY_RATE(a) (0x000021A8 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DISPLAY_RATE_RUN_MODE 0:0 +#define NVC87D_HEAD_SET_DISPLAY_RATE_RUN_MODE_CONTINUOUS (0x00000000) +#define NVC87D_HEAD_SET_DISPLAY_RATE_RUN_MODE_ONE_SHOT (0x00000001) +#define NVC87D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_INTERVAL 25:4 +#define NVC87D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH 2:2 +#define NVC87D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_DISABLE (0x00000000) +#define NVC87D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_ENABLE (0x00000001) +#define NVC87D_HEAD_SET_CONTEXT_DMA_RG_REL_SEMAPHORE(a,b) (0x000021AC + (a)*0x00000400 + (b)*0x00000004) +#define NVC87D_HEAD_SET_CONTEXT_DMA_RG_REL_SEMAPHORE_HANDLE 31:0 +#define NVC87D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL(a,b) (0x000021CC + (a)*0x00000400 + (b)*0x00000004) +#define NVC87D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_OFFSET 7:0 +#define NVC87D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVC87D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVC87D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVC87D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE 14:14 +#define NVC87D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE_WRITE (0x00000000) +#define NVC87D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC87D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE 10:10 +#define NVC87D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE_ONE_TIME (0x00000000) +#define NVC87D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE_CONTINUOUS (0x00000001) +#define NVC87D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RASTER_LINE 30:16 +#define NVC87D_HEAD_SET_RG_REL_SEMAPHORE_VALUE(a,b) (0x000021EC + (a)*0x00000400 + (b)*0x00000004) +#define NVC87D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_VALUE 31:0 +#define NVC87D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE(a) (0x00002214 + (a)*0x00000400) +#define NVC87D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVC87D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVC87D_HEAD_SET_MIN_FRAME_IDLE(a) (0x00002218 + (a)*0x00000400) +#define NVC87D_HEAD_SET_MIN_FRAME_IDLE_LEADING_RASTER_LINES 14:0 +#define NVC87D_HEAD_SET_MIN_FRAME_IDLE_TRAILING_RASTER_LINES 30:16 +#define NVC87D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED(a) (0x00002220 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED_ALPHA 7:0 +#define NVC87D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED_RED 31:16 +#define NVC87D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE(a) (0x00002224 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE_GREEN 15:0 +#define NVC87D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE_BLUE 31:16 +#define NVC87D_HEAD_SET_CURSOR_COLOR_NORM_SCALE(a) (0x00002228 + (a)*0x00000400) +#define NVC87D_HEAD_SET_CURSOR_COLOR_NORM_SCALE_VALUE 15:0 +#define NVC87D_HEAD_SET_XOR_BLEND_FACTOR(a) (0x0000222C + (a)*0x00000400) +#define NVC87D_HEAD_SET_XOR_BLEND_FACTOR_LOG2PEAK_LUMINANCE 3:0 +#define NVC87D_HEAD_SET_XOR_BLEND_FACTOR_S1 16:4 +#define NVC87D_HEAD_SET_XOR_BLEND_FACTOR_S2 30:18 +#define NVC87D_HEAD_SET_CLAMP_RANGE_GREEN(a) (0x00002238 + (a)*0x00000400) +#define NVC87D_HEAD_SET_CLAMP_RANGE_GREEN_LOW 11:0 +#define NVC87D_HEAD_SET_CLAMP_RANGE_GREEN_HIGH 27:16 +#define NVC87D_HEAD_SET_CLAMP_RANGE_RED_BLUE(a) (0x0000223C + (a)*0x00000400) +#define NVC87D_HEAD_SET_CLAMP_RANGE_RED_BLUE_LOW 11:0 +#define NVC87D_HEAD_SET_CLAMP_RANGE_RED_BLUE_HIGH 27:16 +#define NVC87D_HEAD_SET_OCSC0CONTROL(a) (0x00002240 + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC0CONTROL_ENABLE 0:0 +#define NVC87D_HEAD_SET_OCSC0CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC87D_HEAD_SET_OCSC0CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC87D_HEAD_SET_OCSC0COEFFICIENT_C00(a) (0x00002244 + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC0COEFFICIENT_C00_VALUE 20:0 +#define NVC87D_HEAD_SET_OCSC0COEFFICIENT_C01(a) (0x00002248 + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC0COEFFICIENT_C01_VALUE 20:0 +#define NVC87D_HEAD_SET_OCSC0COEFFICIENT_C02(a) (0x0000224C + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC0COEFFICIENT_C02_VALUE 20:0 +#define NVC87D_HEAD_SET_OCSC0COEFFICIENT_C03(a) (0x00002250 + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC0COEFFICIENT_C03_VALUE 20:0 +#define NVC87D_HEAD_SET_OCSC0COEFFICIENT_C10(a) (0x00002254 + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC0COEFFICIENT_C10_VALUE 20:0 +#define NVC87D_HEAD_SET_OCSC0COEFFICIENT_C11(a) (0x00002258 + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC0COEFFICIENT_C11_VALUE 20:0 +#define NVC87D_HEAD_SET_OCSC0COEFFICIENT_C12(a) (0x0000225C + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC0COEFFICIENT_C12_VALUE 20:0 +#define NVC87D_HEAD_SET_OCSC0COEFFICIENT_C13(a) (0x00002260 + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC0COEFFICIENT_C13_VALUE 20:0 +#define NVC87D_HEAD_SET_OCSC0COEFFICIENT_C20(a) (0x00002264 + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC0COEFFICIENT_C20_VALUE 20:0 +#define NVC87D_HEAD_SET_OCSC0COEFFICIENT_C21(a) (0x00002268 + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC0COEFFICIENT_C21_VALUE 20:0 +#define NVC87D_HEAD_SET_OCSC0COEFFICIENT_C22(a) (0x0000226C + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC0COEFFICIENT_C22_VALUE 20:0 +#define NVC87D_HEAD_SET_OCSC0COEFFICIENT_C23(a) (0x00002270 + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC0COEFFICIENT_C23_VALUE 20:0 +#define NVC87D_HEAD_SET_OLUT_CONTROL(a) (0x00002280 + (a)*0x00000400) +#define NVC87D_HEAD_SET_OLUT_CONTROL_INTERPOLATE 0:0 +#define NVC87D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC87D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC87D_HEAD_SET_OLUT_CONTROL_MIRROR 1:1 +#define NVC87D_HEAD_SET_OLUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC87D_HEAD_SET_OLUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC87D_HEAD_SET_OLUT_CONTROL_MODE 3:2 +#define NVC87D_HEAD_SET_OLUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVC87D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVC87D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVC87D_HEAD_SET_OLUT_CONTROL_SIZE 18:8 +#define NVC87D_HEAD_SET_OLUT_FP_NORM_SCALE(a) (0x00002284 + (a)*0x00000400) +#define NVC87D_HEAD_SET_OLUT_FP_NORM_SCALE_VALUE 31:0 +#define NVC87D_HEAD_SET_CONTEXT_DMA_OLUT(a) (0x00002288 + (a)*0x00000400) +#define NVC87D_HEAD_SET_CONTEXT_DMA_OLUT_HANDLE 31:0 +#define NVC87D_HEAD_SET_OFFSET_OLUT(a) (0x0000228C + (a)*0x00000400) +#define NVC87D_HEAD_SET_OFFSET_OLUT_ORIGIN 31:0 +#define NVC87D_HEAD_SET_OCSC1CONTROL(a) (0x0000229C + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC1CONTROL_ENABLE 0:0 +#define NVC87D_HEAD_SET_OCSC1CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC87D_HEAD_SET_OCSC1CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC87D_HEAD_SET_OCSC1COEFFICIENT_C00(a) (0x000022A0 + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC1COEFFICIENT_C00_VALUE 20:0 +#define NVC87D_HEAD_SET_OCSC1COEFFICIENT_C01(a) (0x000022A4 + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC1COEFFICIENT_C01_VALUE 20:0 +#define NVC87D_HEAD_SET_OCSC1COEFFICIENT_C02(a) (0x000022A8 + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC1COEFFICIENT_C02_VALUE 20:0 +#define NVC87D_HEAD_SET_OCSC1COEFFICIENT_C03(a) (0x000022AC + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC1COEFFICIENT_C03_VALUE 20:0 +#define NVC87D_HEAD_SET_OCSC1COEFFICIENT_C10(a) (0x000022B0 + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC1COEFFICIENT_C10_VALUE 20:0 +#define NVC87D_HEAD_SET_OCSC1COEFFICIENT_C11(a) (0x000022B4 + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC1COEFFICIENT_C11_VALUE 20:0 +#define NVC87D_HEAD_SET_OCSC1COEFFICIENT_C12(a) (0x000022B8 + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC1COEFFICIENT_C12_VALUE 20:0 +#define NVC87D_HEAD_SET_OCSC1COEFFICIENT_C13(a) (0x000022BC + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC1COEFFICIENT_C13_VALUE 20:0 +#define NVC87D_HEAD_SET_OCSC1COEFFICIENT_C20(a) (0x000022C0 + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC1COEFFICIENT_C20_VALUE 20:0 +#define NVC87D_HEAD_SET_OCSC1COEFFICIENT_C21(a) (0x000022C4 + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC1COEFFICIENT_C21_VALUE 20:0 +#define NVC87D_HEAD_SET_OCSC1COEFFICIENT_C22(a) (0x000022C8 + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC1COEFFICIENT_C22_VALUE 20:0 +#define NVC87D_HEAD_SET_OCSC1COEFFICIENT_C23(a) (0x000022CC + (a)*0x00000400) +#define NVC87D_HEAD_SET_OCSC1COEFFICIENT_C23_VALUE 20:0 +#define NVC87D_HEAD_SET_TILE_POSITION(a) (0x000022D0 + (a)*0x00000400) +#define NVC87D_HEAD_SET_TILE_POSITION_X 2:0 +#define NVC87D_HEAD_SET_TILE_POSITION_Y 6:4 +#define NVC87D_HEAD_SET_DSC_CONTROL(a) (0x000022D4 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_CONTROL_ENABLE 0:0 +#define NVC87D_HEAD_SET_DSC_CONTROL_ENABLE_FALSE (0x00000000) +#define NVC87D_HEAD_SET_DSC_CONTROL_ENABLE_TRUE (0x00000001) +#define NVC87D_HEAD_SET_DSC_CONTROL_MODE 2:1 +#define NVC87D_HEAD_SET_DSC_CONTROL_MODE_SINGLE (0x00000000) +#define NVC87D_HEAD_SET_DSC_CONTROL_MODE_DUAL (0x00000001) +#define NVC87D_HEAD_SET_DSC_CONTROL_MODE_QUAD (0x00000002) +#define NVC87D_HEAD_SET_DSC_CONTROL_AUTO_RESET 3:3 +#define NVC87D_HEAD_SET_DSC_CONTROL_AUTO_RESET_DISABLE (0x00000000) +#define NVC87D_HEAD_SET_DSC_CONTROL_AUTO_RESET_ENABLE (0x00000001) +#define NVC87D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION 4:4 +#define NVC87D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION_DISABLE (0x00000000) +#define NVC87D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION_ENABLE (0x00000001) +#define NVC87D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET 5:5 +#define NVC87D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET_FALSE (0x00000000) +#define NVC87D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET_TRUE (0x00000001) +#define NVC87D_HEAD_SET_DSC_CONTROL_FLATNESS_DET_THRESH 15:6 +#define NVC87D_HEAD_SET_DSC_PPS_CONTROL(a) (0x000022D8 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_CONTROL_ENABLE 0:0 +#define NVC87D_HEAD_SET_DSC_PPS_CONTROL_ENABLE_FALSE (0x00000000) +#define NVC87D_HEAD_SET_DSC_PPS_CONTROL_ENABLE_TRUE (0x00000001) +#define NVC87D_HEAD_SET_DSC_PPS_CONTROL_LOCATION 1:1 +#define NVC87D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_VSYNC (0x00000000) +#define NVC87D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_VBLANK (0x00000001) +#define NVC87D_HEAD_SET_DSC_PPS_CONTROL_SIZE 9:2 +#define NVC87D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY 10:10 +#define NVC87D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVC87D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY_ONCE (0x00000001) +#define NVC87D_HEAD_SET_DSC_PPS_HEAD(a) (0x000022DC + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_HEAD_BYTE0 7:0 +#define NVC87D_HEAD_SET_DSC_PPS_HEAD_BYTE1 15:8 +#define NVC87D_HEAD_SET_DSC_PPS_HEAD_BYTE2 23:16 +#define NVC87D_HEAD_SET_DSC_PPS_HEAD_BYTE3 31:24 +#define NVC87D_HEAD_SET_DSC_PPS_DATA0(a) (0x000022E0 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA0_DSC_VERSION_MINOR 3:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA0_DSC_VERSION_MAJOR 7:4 +#define NVC87D_HEAD_SET_DSC_PPS_DATA0_PPS_IDENTIFIER 15:8 +#define NVC87D_HEAD_SET_DSC_PPS_DATA0_RESERVED 23:16 +#define NVC87D_HEAD_SET_DSC_PPS_DATA0_LINEBUF_DEPTH 27:24 +#define NVC87D_HEAD_SET_DSC_PPS_DATA0_BITS_PER_COMPONENT 31:28 +#define NVC87D_HEAD_SET_DSC_PPS_DATA1(a) (0x000022E4 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA1_BITS_PER_PIXEL_HIGH 1:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA1_VBR_ENABLE 2:2 +#define NVC87D_HEAD_SET_DSC_PPS_DATA1_SIMPLE422 3:3 +#define NVC87D_HEAD_SET_DSC_PPS_DATA1_CONVERT_RGB 4:4 +#define NVC87D_HEAD_SET_DSC_PPS_DATA1_BLOCK_PRED_ENABLE 5:5 +#define NVC87D_HEAD_SET_DSC_PPS_DATA1_RESERVED 7:6 +#define NVC87D_HEAD_SET_DSC_PPS_DATA1_BITS_PER_PIXEL_LOW 15:8 +#define NVC87D_HEAD_SET_DSC_PPS_DATA1_PIC_HEIGHT_HIGH 23:16 +#define NVC87D_HEAD_SET_DSC_PPS_DATA1_PIC_HEIGHT_LOW 31:24 +#define NVC87D_HEAD_SET_DSC_PPS_DATA2(a) (0x000022E8 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA2_PIC_WIDTH_HIGH 7:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA2_PIC_WIDTH_LOW 15:8 +#define NVC87D_HEAD_SET_DSC_PPS_DATA2_SLICE_HEIGHT_HIGH 23:16 +#define NVC87D_HEAD_SET_DSC_PPS_DATA2_SLICE_HEIGHT_LOW 31:24 +#define NVC87D_HEAD_SET_DSC_PPS_DATA3(a) (0x000022EC + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA3_SLICE_WIDTH_HIGH 7:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA3_SLICE_WIDTH_LOW 15:8 +#define NVC87D_HEAD_SET_DSC_PPS_DATA3_CHUNK_SIZE_HIGH 23:16 +#define NVC87D_HEAD_SET_DSC_PPS_DATA3_CHUNK_SIZE_LOW 31:24 +#define NVC87D_HEAD_SET_DSC_PPS_DATA4(a) (0x000022F0 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA4_INITIAL_XMIT_DELAY_HIGH 1:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA4_RESERVED 7:2 +#define NVC87D_HEAD_SET_DSC_PPS_DATA4_INITIAL_XMIT_DELAY_LOW 15:8 +#define NVC87D_HEAD_SET_DSC_PPS_DATA4_INITIAL_DEC_DELAY_HIGH 23:16 +#define NVC87D_HEAD_SET_DSC_PPS_DATA4_INITIAL_DEC_DELAY_LOW 31:24 +#define NVC87D_HEAD_SET_DSC_PPS_DATA5(a) (0x000022F4 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA5_RESERVED0 7:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA5_INITIAL_SCALE_VALUE 13:8 +#define NVC87D_HEAD_SET_DSC_PPS_DATA5_RESERVED1 15:14 +#define NVC87D_HEAD_SET_DSC_PPS_DATA5_SCALE_INCREMENT_INTERVAL_HIGH 23:16 +#define NVC87D_HEAD_SET_DSC_PPS_DATA5_SCALE_INCREMENT_INTERVAL_LOW 31:24 +#define NVC87D_HEAD_SET_DSC_PPS_DATA6(a) (0x000022F8 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA6_SCALE_DECREMENT_INTERVAL_HIGH 3:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA6_RESERVED0 7:4 +#define NVC87D_HEAD_SET_DSC_PPS_DATA6_SCALE_DECREMENT_INTERVAL_LOW 15:8 +#define NVC87D_HEAD_SET_DSC_PPS_DATA6_RESERVED1 23:16 +#define NVC87D_HEAD_SET_DSC_PPS_DATA6_FIRST_LINE_BPG_OFFSET 28:24 +#define NVC87D_HEAD_SET_DSC_PPS_DATA6_RESERVED2 31:29 +#define NVC87D_HEAD_SET_DSC_PPS_DATA7(a) (0x000022FC + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA7_NFL_BPG_OFFSET_HIGH 7:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA7_NFL_BPG_OFFSET_LOW 15:8 +#define NVC87D_HEAD_SET_DSC_PPS_DATA7_SLICE_BPG_OFFSET_HIGH 23:16 +#define NVC87D_HEAD_SET_DSC_PPS_DATA7_SLICE_BPG_OFFSET_LOW 31:24 +#define NVC87D_HEAD_SET_DSC_PPS_DATA8(a) (0x00002300 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA8_INITIAL_OFFSET_HIGH 7:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA8_INITIAL_OFFSET_LOW 15:8 +#define NVC87D_HEAD_SET_DSC_PPS_DATA8_FINAL_OFFSET_HIGH 23:16 +#define NVC87D_HEAD_SET_DSC_PPS_DATA8_FINAL_OFFSET_LOW 31:24 +#define NVC87D_HEAD_SET_DSC_PPS_DATA9(a) (0x00002304 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA9_FLATNESS_MIN_QP 4:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA9_RESERVED0 7:5 +#define NVC87D_HEAD_SET_DSC_PPS_DATA9_FLATNESS_MAX_QP 12:8 +#define NVC87D_HEAD_SET_DSC_PPS_DATA9_RESERVED1 15:13 +#define NVC87D_HEAD_SET_DSC_PPS_DATA9_RC_MODEL_SIZE_HIGH 23:16 +#define NVC87D_HEAD_SET_DSC_PPS_DATA9_RC_MODEL_SIZE_LOW 31:24 +#define NVC87D_HEAD_SET_DSC_PPS_DATA10(a) (0x00002308 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA10_RC_EDGE_FACTOR 3:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA10_RESERVED0 7:4 +#define NVC87D_HEAD_SET_DSC_PPS_DATA10_RC_QUANT_INCR_LIMIT0 12:8 +#define NVC87D_HEAD_SET_DSC_PPS_DATA10_RESERVED1 15:13 +#define NVC87D_HEAD_SET_DSC_PPS_DATA10_RC_QUANT_INCR_LIMIT1 20:16 +#define NVC87D_HEAD_SET_DSC_PPS_DATA10_RESERVED2 23:21 +#define NVC87D_HEAD_SET_DSC_PPS_DATA10_RC_TGT_OFFSET_LO 27:24 +#define NVC87D_HEAD_SET_DSC_PPS_DATA10_RC_TGT_OFFSET_HI 31:28 +#define NVC87D_HEAD_SET_DSC_PPS_DATA11(a) (0x0000230C + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH0 7:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH1 15:8 +#define NVC87D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH2 23:16 +#define NVC87D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH3 31:24 +#define NVC87D_HEAD_SET_DSC_PPS_DATA12(a) (0x00002310 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH4 7:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH5 15:8 +#define NVC87D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH6 23:16 +#define NVC87D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH7 31:24 +#define NVC87D_HEAD_SET_DSC_PPS_DATA13(a) (0x00002314 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH8 7:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH9 15:8 +#define NVC87D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH10 23:16 +#define NVC87D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH11 31:24 +#define NVC87D_HEAD_SET_DSC_PPS_DATA14(a) (0x00002318 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA14_RC_BUF_THRESH12 7:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA14_RC_BUF_THRESH13 15:8 +#define NVC87D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MAX_QP_HIGH0 18:16 +#define NVC87D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MIN_QP0 23:19 +#define NVC87D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_BPG_OFFSET0 29:24 +#define NVC87D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MAX_QP_LOW0 31:30 +#define NVC87D_HEAD_SET_DSC_PPS_DATA15(a) (0x0000231C + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_HIGH1 2:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MIN_QP1 7:3 +#define NVC87D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_BPG_OFFSET1 13:8 +#define NVC87D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_LOW1 15:14 +#define NVC87D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_HIGH2 18:16 +#define NVC87D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MIN_QP2 23:19 +#define NVC87D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_BPG_OFFSET2 29:24 +#define NVC87D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_LOW2 31:30 +#define NVC87D_HEAD_SET_DSC_PPS_DATA16(a) (0x00002320 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_HIGH3 2:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MIN_QP3 7:3 +#define NVC87D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_BPG_OFFSET3 13:8 +#define NVC87D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_LOW3 15:14 +#define NVC87D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_HIGH4 18:16 +#define NVC87D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MIN_QP4 23:19 +#define NVC87D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_BPG_OFFSET4 29:24 +#define NVC87D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_LOW4 31:30 +#define NVC87D_HEAD_SET_DSC_PPS_DATA17(a) (0x00002324 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_HIGH5 2:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MIN_QP5 7:3 +#define NVC87D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_BPG_OFFSET5 13:8 +#define NVC87D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_LOW5 15:14 +#define NVC87D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_HIGH6 18:16 +#define NVC87D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MIN_QP6 23:19 +#define NVC87D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_BPG_OFFSET6 29:24 +#define NVC87D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_LOW6 31:30 +#define NVC87D_HEAD_SET_DSC_PPS_DATA18(a) (0x00002328 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_HIGH7 2:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MIN_QP7 7:3 +#define NVC87D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_BPG_OFFSET7 13:8 +#define NVC87D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_LOW7 15:14 +#define NVC87D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_HIGH8 18:16 +#define NVC87D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MIN_QP8 23:19 +#define NVC87D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_BPG_OFFSET8 29:24 +#define NVC87D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_LOW8 31:30 +#define NVC87D_HEAD_SET_DSC_PPS_DATA19(a) (0x0000232C + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_HIGH9 2:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MIN_QP9 7:3 +#define NVC87D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_BPG_OFFSET9 13:8 +#define NVC87D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_LOW9 15:14 +#define NVC87D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_HIGH10 18:16 +#define NVC87D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MIN_QP10 23:19 +#define NVC87D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_BPG_OFFSET10 29:24 +#define NVC87D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_LOW10 31:30 +#define NVC87D_HEAD_SET_DSC_PPS_DATA20(a) (0x00002330 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_HIGH11 2:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MIN_QP11 7:3 +#define NVC87D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_BPG_OFFSET11 13:8 +#define NVC87D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_LOW11 15:14 +#define NVC87D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_HIGH12 18:16 +#define NVC87D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MIN_QP12 23:19 +#define NVC87D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_BPG_OFFSET12 29:24 +#define NVC87D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_LOW12 31:30 +#define NVC87D_HEAD_SET_DSC_PPS_DATA21(a) (0x00002334 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_HIGH13 2:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MIN_QP13 7:3 +#define NVC87D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_BPG_OFFSET13 13:8 +#define NVC87D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_LOW13 15:14 +#define NVC87D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_HIGH14 18:16 +#define NVC87D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MIN_QP14 23:19 +#define NVC87D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_BPG_OFFSET14 29:24 +#define NVC87D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_LOW14 31:30 +#define NVC87D_HEAD_SET_DSC_PPS_DATA22(a) (0x00002338 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA22_NATIVE422 0:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA22_NATIVE420 1:1 +#define NVC87D_HEAD_SET_DSC_PPS_DATA22_RESERVED0 7:2 +#define NVC87D_HEAD_SET_DSC_PPS_DATA22_SECOND_LINE_BPG_OFFSET 12:8 +#define NVC87D_HEAD_SET_DSC_PPS_DATA22_RESERVED1 15:13 +#define NVC87D_HEAD_SET_DSC_PPS_DATA22_NSL_BPG_OFFSET_HIGH 23:16 +#define NVC87D_HEAD_SET_DSC_PPS_DATA22_NSL_BPG_OFFSETLOW 31:24 +#define NVC87D_HEAD_SET_DSC_PPS_DATA23(a) (0x0000233C + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA23_SECOND_LINE_OFFSET_ADJ_HIGH 7:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA23_SECOND_LINE_OFFSET_ADJ_LOW 15:8 +#define NVC87D_HEAD_SET_DSC_PPS_DATA23_RESERVED 31:16 +#define NVC87D_HEAD_SET_DSC_PPS_DATA24(a) (0x00002340 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA24_RESERVED 31:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA25(a) (0x00002344 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA25_RESERVED 31:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA26(a) (0x00002348 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA26_RESERVED 31:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA27(a) (0x0000234C + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA27_RESERVED 31:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA28(a) (0x00002350 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA28_RESERVED 31:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA29(a) (0x00002354 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA29_RESERVED 31:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA30(a) (0x00002358 + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA30_RESERVED 31:0 +#define NVC87D_HEAD_SET_DSC_PPS_DATA31(a) (0x0000235C + (a)*0x00000400) +#define NVC87D_HEAD_SET_DSC_PPS_DATA31_RESERVED 31:0 +#define NVC87D_HEAD_SET_RG_MERGE(a) (0x00002360 + (a)*0x00000400) +#define NVC87D_HEAD_SET_RG_MERGE_MODE 1:0 +#define NVC87D_HEAD_SET_RG_MERGE_MODE_DISABLE (0x00000000) +#define NVC87D_HEAD_SET_RG_MERGE_MODE_SETUP (0x00000001) +#define NVC87D_HEAD_SET_RG_MERGE_MODE_MASTER (0x00000002) +#define NVC87D_HEAD_SET_RG_MERGE_MODE_SLAVE (0x00000003) +#define NVC87D_HEAD_SET_RASTER_HBLANK_DELAY(a) (0x00002364 + (a)*0x00000400) +#define NVC87D_HEAD_SET_RASTER_HBLANK_DELAY_BLANK_START 15:0 +#define NVC87D_HEAD_SET_RASTER_HBLANK_DELAY_BLANK_END 31:16 +#define NVC87D_HEAD_SET_HDMI_DSC_HCACTIVE(a) (0x00002368 + (a)*0x00000400) +#define NVC87D_HEAD_SET_HDMI_DSC_HCACTIVE_BYTES 15:0 +#define NVC87D_HEAD_SET_HDMI_DSC_HCACTIVE_TRI_BYTES 31:16 +#define NVC87D_HEAD_SET_HDMI_DSC_HCBLANK(a) (0x0000236C + (a)*0x00000400) +#define NVC87D_HEAD_SET_HDMI_DSC_HCBLANK_WIDTH 15:0 +#define NVC87D_HEAD_SW_RESERVED(a,b) (0x00002370 + (a)*0x00000400 + (b)*0x00000004) +#define NVC87D_HEAD_SW_RESERVED_VALUE 31:0 +#define NVC87D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_HI(a,b) (0x00002380 + (a)*0x00000400 + (b)*0x00000004) +#define NVC87D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_HI_VALUE 31:0 +#define NVC87D_HEAD_SET_HEAD_INFOFRAME(a) (0x000023A0 + (a)*0x00000400) +#define NVC87D_HEAD_SET_HEAD_INFOFRAME_FID 7:0 +#define NVC87D_HEAD_SET_HEAD_INFOFRAME_EN 16:16 +#define NVC87D_HEAD_SET_HEAD_INFOFRAME_EN_DISABLE (0x00000000) +#define NVC87D_HEAD_SET_HEAD_INFOFRAME_EN_ENABLE (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC87d_h diff --git a/userspace/sdks/nv570/inc/class/clc87e.h b/userspace/sdks/nv570/inc/class/clc87e.h new file mode 100644 index 0000000..61c58f1 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc87e.h @@ -0,0 +1,697 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clC87e_h_ +#define _clC87e_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC87E_WINDOW_CHANNEL_DMA (0x0000C87E) + +// dma opcode instructions +#define NVC87E_DMA +#define NVC87E_DMA_OPCODE 31:29 +#define NVC87E_DMA_OPCODE_METHOD 0x00000000 +#define NVC87E_DMA_OPCODE_JUMP 0x00000001 +#define NVC87E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC87E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC87E_DMA_METHOD_COUNT 27:18 +#define NVC87E_DMA_METHOD_OFFSET 13:2 +#define NVC87E_DMA_DATA 31:0 +#define NVC87E_DMA_DATA_NOP 0x00000000 +#define NVC87E_DMA_JUMP_OFFSET 11:2 +#define NVC87E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVC87E_PUT (0x00000000) +#define NVC87E_PUT_PTR 9:0 +#define NVC87E_GET (0x00000004) +#define NVC87E_GET_PTR 9:0 +#define NVC87E_UPDATE (0x00000200) +#define NVC87E_UPDATE_RELEASE_ELV 0:0 +#define NVC87E_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC87E_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC87E_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC87E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC87E_UPDATE_INTERLOCK_WITH_WIN_IMM 12:12 +#define NVC87E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE (0x00000000) +#define NVC87E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE (0x00000001) +#define NVC87E_SET_SEMAPHORE_ACQUIRE_HI (0x00000204) +#define NVC87E_SET_SEMAPHORE_ACQUIRE_HI_VALUE 31:0 +#define NVC87E_GET_LINE (0x00000208) +#define NVC87E_GET_LINE_LINE 15:0 +#define NVC87E_SET_SEMAPHORE_CONTROL (0x0000020C) +#define NVC87E_SET_SEMAPHORE_CONTROL_OFFSET 7:0 +#define NVC87E_SET_SEMAPHORE_CONTROL_SKIP_ACQ 11:11 +#define NVC87E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_FALSE (0x00000000) +#define NVC87E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_TRUE (0x00000001) +#define NVC87E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVC87E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVC87E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVC87E_SET_SEMAPHORE_CONTROL_ACQ_MODE 13:12 +#define NVC87E_SET_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000) +#define NVC87E_SET_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001) +#define NVC87E_SET_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002) +#define NVC87E_SET_SEMAPHORE_CONTROL_REL_MODE 14:14 +#define NVC87E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE (0x00000000) +#define NVC87E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC87E_SET_SEMAPHORE_ACQUIRE (0x00000210) +#define NVC87E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NVC87E_SET_SEMAPHORE_RELEASE (0x00000214) +#define NVC87E_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NVC87E_SET_CONTEXT_DMA_SEMAPHORE (0x00000218) +#define NVC87E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NVC87E_SET_CONTEXT_DMA_NOTIFIER (0x0000021C) +#define NVC87E_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NVC87E_SET_NOTIFIER_CONTROL (0x00000220) +#define NVC87E_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC87E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC87E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC87E_SET_NOTIFIER_CONTROL_OFFSET 11:4 +#define NVC87E_SET_SIZE (0x00000224) +#define NVC87E_SET_SIZE_WIDTH 15:0 +#define NVC87E_SET_SIZE_HEIGHT 31:16 +#define NVC87E_SET_STORAGE (0x00000228) +#define NVC87E_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NVC87E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NVC87E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NVC87E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC87E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC87E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC87E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC87E_SET_PARAMS (0x0000022C) +#define NVC87E_SET_PARAMS_FORMAT 7:0 +#define NVC87E_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NVC87E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F) +#define NVC87E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NVC87E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC87E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E) +#define NVC87E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC87E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6) +#define NVC87E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NVC87E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9) +#define NVC87E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NVC87E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NVC87E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NVC87E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NVC87E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NVC87E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028) +#define NVC87E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029) +#define NVC87E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035) +#define NVC87E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036) +#define NVC87E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038) +#define NVC87E_SET_PARAMS_FORMAT_Y8___U8___V8_N444 (0x0000003A) +#define NVC87E_SET_PARAMS_FORMAT_Y8___U8___V8_N420 (0x0000003B) +#define NVC87E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055) +#define NVC87E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056) +#define NVC87E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058) +#define NVC87E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075) +#define NVC87E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076) +#define NVC87E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078) +#define NVC87E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18 +#define NVC87E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000) +#define NVC87E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001) +#define NVC87E_SET_PARAMS_SWAP_UV 19:19 +#define NVC87E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000) +#define NVC87E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001) +#define NVC87E_SET_PARAMS_FMT_ROUNDING_MODE 22:22 +#define NVC87E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_TO_NEAREST (0x00000000) +#define NVC87E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_DOWN (0x00000001) +#define NVC87E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004) +#define NVC87E_SET_PLANAR_STORAGE_PITCH 12:0 +#define NVC87E_SET_SEMAPHORE_RELEASE_HI (0x0000023C) +#define NVC87E_SET_SEMAPHORE_RELEASE_HI_VALUE 31:0 +#define NVC87E_SET_CONTEXT_DMA_ISO(b) (0x00000240 + (b)*0x00000004) +#define NVC87E_SET_CONTEXT_DMA_ISO_HANDLE 31:0 +#define NVC87E_SET_OFFSET(b) (0x00000260 + (b)*0x00000004) +#define NVC87E_SET_OFFSET_ORIGIN 31:0 +#define NVC87E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004) +#define NVC87E_SET_POINT_IN_X 15:0 +#define NVC87E_SET_POINT_IN_Y 31:16 +#define NVC87E_SET_SIZE_IN (0x00000298) +#define NVC87E_SET_SIZE_IN_WIDTH 15:0 +#define NVC87E_SET_SIZE_IN_HEIGHT 31:16 +#define NVC87E_SET_SIZE_OUT (0x000002A4) +#define NVC87E_SET_SIZE_OUT_WIDTH 15:0 +#define NVC87E_SET_SIZE_OUT_HEIGHT 31:16 +#define NVC87E_SET_CONTROL_INPUT_SCALER (0x000002A8) +#define NVC87E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVC87E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVC87E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVC87E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVC87E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVC87E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVC87E_SET_INPUT_SCALER_COEFF_VALUE (0x000002AC) +#define NVC87E_SET_INPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVC87E_SET_INPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVC87E_SET_COMPOSITION_CONTROL (0x000002EC) +#define NVC87E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0 +#define NVC87E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000) +#define NVC87E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001) +#define NVC87E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002) +#define NVC87E_SET_COMPOSITION_CONTROL_DEPTH 11:4 +#define NVC87E_SET_COMPOSITION_CONTROL_BYPASS 16:16 +#define NVC87E_SET_COMPOSITION_CONTROL_BYPASS_DISABLE (0x00000000) +#define NVC87E_SET_COMPOSITION_CONTROL_BYPASS_ENABLE (0x00000001) +#define NVC87E_SET_COMPOSITION_CONSTANT_ALPHA (0x000002F0) +#define NVC87E_SET_COMPOSITION_CONSTANT_ALPHA_K1 7:0 +#define NVC87E_SET_COMPOSITION_CONSTANT_ALPHA_K2 15:8 +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT (0x000002F4) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0 +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4 +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8 +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12 +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16 +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20 +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24 +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28 +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC87E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC87E_SET_KEY_ALPHA (0x000002F8) +#define NVC87E_SET_KEY_ALPHA_MIN 15:0 +#define NVC87E_SET_KEY_ALPHA_MAX 31:16 +#define NVC87E_SET_KEY_RED_CR (0x000002FC) +#define NVC87E_SET_KEY_RED_CR_MIN 15:0 +#define NVC87E_SET_KEY_RED_CR_MAX 31:16 +#define NVC87E_SET_KEY_GREEN_Y (0x00000300) +#define NVC87E_SET_KEY_GREEN_Y_MIN 15:0 +#define NVC87E_SET_KEY_GREEN_Y_MAX 31:16 +#define NVC87E_SET_KEY_BLUE_CB (0x00000304) +#define NVC87E_SET_KEY_BLUE_CB_MIN 15:0 +#define NVC87E_SET_KEY_BLUE_CB_MAX 31:16 +#define NVC87E_SET_PRESENT_CONTROL (0x00000308) +#define NVC87E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NVC87E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4 +#define NVC87E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NVC87E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NVC87E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8 +#define NVC87E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000) +#define NVC87E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001) +#define NVC87E_SET_PRESENT_CONTROL_STEREO_MODE 13:12 +#define NVC87E_SET_PRESENT_CONTROL_STEREO_MODE_MONO (0x00000000) +#define NVC87E_SET_PRESENT_CONTROL_STEREO_MODE_PAIR_FLIP (0x00000001) +#define NVC87E_SET_PRESENT_CONTROL_STEREO_MODE_AT_ANY_FRAME (0x00000002) +#define NVC87E_SET_ACQ_SEMAPHORE_VALUE_HI (0x0000030C) +#define NVC87E_SET_ACQ_SEMAPHORE_VALUE_HI_VALUE 31:0 +#define NVC87E_SET_ACQ_SEMAPHORE_CONTROL (0x00000330) +#define NVC87E_SET_ACQ_SEMAPHORE_CONTROL_OFFSET 7:0 +#define NVC87E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVC87E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVC87E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVC87E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE 13:12 +#define NVC87E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000) +#define NVC87E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001) +#define NVC87E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002) +#define NVC87E_SET_ACQ_SEMAPHORE_VALUE (0x00000334) +#define NVC87E_SET_ACQ_SEMAPHORE_VALUE_VALUE 31:0 +#define NVC87E_SET_CONTEXT_DMA_ACQ_SEMAPHORE (0x00000338) +#define NVC87E_SET_CONTEXT_DMA_ACQ_SEMAPHORE_HANDLE 31:0 +#define NVC87E_SET_SCAN_DIRECTION (0x0000033C) +#define NVC87E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION 0:0 +#define NVC87E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_LEFT (0x00000000) +#define NVC87E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_RIGHT (0x00000001) +#define NVC87E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION 1:1 +#define NVC87E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_TOP (0x00000000) +#define NVC87E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_BOTTOM (0x00000001) +#define NVC87E_SET_SCAN_DIRECTION_COLUMN_ORDER 2:2 +#define NVC87E_SET_SCAN_DIRECTION_COLUMN_ORDER_FALSE (0x00000000) +#define NVC87E_SET_SCAN_DIRECTION_COLUMN_ORDER_TRUE (0x00000001) +#define NVC87E_SET_TIMESTAMP_ORIGIN_LO (0x00000340) +#define NVC87E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NVC87E_SET_TIMESTAMP_ORIGIN_HI (0x00000344) +#define NVC87E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NVC87E_SET_UPDATE_TIMESTAMP_LO (0x00000348) +#define NVC87E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NVC87E_SET_UPDATE_TIMESTAMP_HI (0x0000034C) +#define NVC87E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NVC87E_SET_INTERLOCK_FLAGS (0x00000370) +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 0:0 +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+1):((i)+1) +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 1:1 +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 2:2 +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 3:3 +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 4:4 +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 5:5 +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 6:6 +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 7:7 +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 8:8 +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC87E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS (0x00000374) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC87E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVC87E_SET_EXT_PACKET_CONTROL (0x00000398) +#define NVC87E_SET_EXT_PACKET_CONTROL_ENABLE 0:0 +#define NVC87E_SET_EXT_PACKET_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC87E_SET_EXT_PACKET_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC87E_SET_EXT_PACKET_CONTROL_LOCATION 4:4 +#define NVC87E_SET_EXT_PACKET_CONTROL_LOCATION_VSYNC (0x00000000) +#define NVC87E_SET_EXT_PACKET_CONTROL_LOCATION_VBLANK (0x00000001) +#define NVC87E_SET_EXT_PACKET_CONTROL_FREQUENCY 8:8 +#define NVC87E_SET_EXT_PACKET_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVC87E_SET_EXT_PACKET_CONTROL_FREQUENCY_ONCE (0x00000001) +#define NVC87E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE 12:12 +#define NVC87E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_DISABLE (0x00000000) +#define NVC87E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_ENABLE (0x00000001) +#define NVC87E_SET_EXT_PACKET_CONTROL_SIZE 27:16 +#define NVC87E_SET_EXT_PACKET_DATA (0x0000039C) +#define NVC87E_SET_EXT_PACKET_DATA_DB0 7:0 +#define NVC87E_SET_EXT_PACKET_DATA_DB1 15:8 +#define NVC87E_SET_EXT_PACKET_DATA_DB2 23:16 +#define NVC87E_SET_EXT_PACKET_DATA_DB3 31:24 +#define NVC87E_SET_FMT_COEFFICIENT_C00 (0x00000400) +#define NVC87E_SET_FMT_COEFFICIENT_C00_VALUE 20:0 +#define NVC87E_SET_FMT_COEFFICIENT_C01 (0x00000404) +#define NVC87E_SET_FMT_COEFFICIENT_C01_VALUE 20:0 +#define NVC87E_SET_FMT_COEFFICIENT_C02 (0x00000408) +#define NVC87E_SET_FMT_COEFFICIENT_C02_VALUE 20:0 +#define NVC87E_SET_FMT_COEFFICIENT_C03 (0x0000040C) +#define NVC87E_SET_FMT_COEFFICIENT_C03_VALUE 20:0 +#define NVC87E_SET_FMT_COEFFICIENT_C10 (0x00000410) +#define NVC87E_SET_FMT_COEFFICIENT_C10_VALUE 20:0 +#define NVC87E_SET_FMT_COEFFICIENT_C11 (0x00000414) +#define NVC87E_SET_FMT_COEFFICIENT_C11_VALUE 20:0 +#define NVC87E_SET_FMT_COEFFICIENT_C12 (0x00000418) +#define NVC87E_SET_FMT_COEFFICIENT_C12_VALUE 20:0 +#define NVC87E_SET_FMT_COEFFICIENT_C13 (0x0000041C) +#define NVC87E_SET_FMT_COEFFICIENT_C13_VALUE 20:0 +#define NVC87E_SET_FMT_COEFFICIENT_C20 (0x00000420) +#define NVC87E_SET_FMT_COEFFICIENT_C20_VALUE 20:0 +#define NVC87E_SET_FMT_COEFFICIENT_C21 (0x00000424) +#define NVC87E_SET_FMT_COEFFICIENT_C21_VALUE 20:0 +#define NVC87E_SET_FMT_COEFFICIENT_C22 (0x00000428) +#define NVC87E_SET_FMT_COEFFICIENT_C22_VALUE 20:0 +#define NVC87E_SET_FMT_COEFFICIENT_C23 (0x0000042C) +#define NVC87E_SET_FMT_COEFFICIENT_C23_VALUE 20:0 +#define NVC87E_SET_ILUT_CONTROL (0x00000440) +#define NVC87E_SET_ILUT_CONTROL_INTERPOLATE 0:0 +#define NVC87E_SET_ILUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC87E_SET_ILUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC87E_SET_ILUT_CONTROL_MIRROR 1:1 +#define NVC87E_SET_ILUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC87E_SET_ILUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC87E_SET_ILUT_CONTROL_MODE 3:2 +#define NVC87E_SET_ILUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVC87E_SET_ILUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVC87E_SET_ILUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVC87E_SET_ILUT_CONTROL_SIZE 18:8 +#define NVC87E_SET_CONTEXT_DMA_ILUT (0x00000444) +#define NVC87E_SET_CONTEXT_DMA_ILUT_HANDLE 31:0 +#define NVC87E_SET_OFFSET_ILUT (0x00000448) +#define NVC87E_SET_OFFSET_ILUT_ORIGIN 31:0 +#define NVC87E_SET_CSC00CONTROL (0x0000045C) +#define NVC87E_SET_CSC00CONTROL_ENABLE 0:0 +#define NVC87E_SET_CSC00CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC87E_SET_CSC00CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC87E_SET_CSC00COEFFICIENT_C00 (0x00000460) +#define NVC87E_SET_CSC00COEFFICIENT_C00_VALUE 20:0 +#define NVC87E_SET_CSC00COEFFICIENT_C01 (0x00000464) +#define NVC87E_SET_CSC00COEFFICIENT_C01_VALUE 20:0 +#define NVC87E_SET_CSC00COEFFICIENT_C02 (0x00000468) +#define NVC87E_SET_CSC00COEFFICIENT_C02_VALUE 20:0 +#define NVC87E_SET_CSC00COEFFICIENT_C03 (0x0000046C) +#define NVC87E_SET_CSC00COEFFICIENT_C03_VALUE 20:0 +#define NVC87E_SET_CSC00COEFFICIENT_C10 (0x00000470) +#define NVC87E_SET_CSC00COEFFICIENT_C10_VALUE 20:0 +#define NVC87E_SET_CSC00COEFFICIENT_C11 (0x00000474) +#define NVC87E_SET_CSC00COEFFICIENT_C11_VALUE 20:0 +#define NVC87E_SET_CSC00COEFFICIENT_C12 (0x00000478) +#define NVC87E_SET_CSC00COEFFICIENT_C12_VALUE 20:0 +#define NVC87E_SET_CSC00COEFFICIENT_C13 (0x0000047C) +#define NVC87E_SET_CSC00COEFFICIENT_C13_VALUE 20:0 +#define NVC87E_SET_CSC00COEFFICIENT_C20 (0x00000480) +#define NVC87E_SET_CSC00COEFFICIENT_C20_VALUE 20:0 +#define NVC87E_SET_CSC00COEFFICIENT_C21 (0x00000484) +#define NVC87E_SET_CSC00COEFFICIENT_C21_VALUE 20:0 +#define NVC87E_SET_CSC00COEFFICIENT_C22 (0x00000488) +#define NVC87E_SET_CSC00COEFFICIENT_C22_VALUE 20:0 +#define NVC87E_SET_CSC00COEFFICIENT_C23 (0x0000048C) +#define NVC87E_SET_CSC00COEFFICIENT_C23_VALUE 20:0 +#define NVC87E_SET_CSC0LUT_CONTROL (0x000004A0) +#define NVC87E_SET_CSC0LUT_CONTROL_INTERPOLATE 0:0 +#define NVC87E_SET_CSC0LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC87E_SET_CSC0LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC87E_SET_CSC0LUT_CONTROL_MIRROR 1:1 +#define NVC87E_SET_CSC0LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC87E_SET_CSC0LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC87E_SET_CSC0LUT_CONTROL_ENABLE 4:4 +#define NVC87E_SET_CSC0LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC87E_SET_CSC0LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC87E_SET_CSC0LUT_SEGMENT_SIZE (0x000004A4) +#define NVC87E_SET_CSC0LUT_SEGMENT_SIZE_IDX 5:0 +#define NVC87E_SET_CSC0LUT_SEGMENT_SIZE_VALUE 18:16 +#define NVC87E_SET_CSC0LUT_ENTRY (0x000004A8) +#define NVC87E_SET_CSC0LUT_ENTRY_IDX 10:0 +#define NVC87E_SET_CSC0LUT_ENTRY_VALUE 31:16 +#define NVC87E_SET_CSC01CONTROL (0x000004BC) +#define NVC87E_SET_CSC01CONTROL_ENABLE 0:0 +#define NVC87E_SET_CSC01CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC87E_SET_CSC01CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC87E_SET_CSC01COEFFICIENT_C00 (0x000004C0) +#define NVC87E_SET_CSC01COEFFICIENT_C00_VALUE 20:0 +#define NVC87E_SET_CSC01COEFFICIENT_C01 (0x000004C4) +#define NVC87E_SET_CSC01COEFFICIENT_C01_VALUE 20:0 +#define NVC87E_SET_CSC01COEFFICIENT_C02 (0x000004C8) +#define NVC87E_SET_CSC01COEFFICIENT_C02_VALUE 20:0 +#define NVC87E_SET_CSC01COEFFICIENT_C03 (0x000004CC) +#define NVC87E_SET_CSC01COEFFICIENT_C03_VALUE 20:0 +#define NVC87E_SET_CSC01COEFFICIENT_C10 (0x000004D0) +#define NVC87E_SET_CSC01COEFFICIENT_C10_VALUE 20:0 +#define NVC87E_SET_CSC01COEFFICIENT_C11 (0x000004D4) +#define NVC87E_SET_CSC01COEFFICIENT_C11_VALUE 20:0 +#define NVC87E_SET_CSC01COEFFICIENT_C12 (0x000004D8) +#define NVC87E_SET_CSC01COEFFICIENT_C12_VALUE 20:0 +#define NVC87E_SET_CSC01COEFFICIENT_C13 (0x000004DC) +#define NVC87E_SET_CSC01COEFFICIENT_C13_VALUE 20:0 +#define NVC87E_SET_CSC01COEFFICIENT_C20 (0x000004E0) +#define NVC87E_SET_CSC01COEFFICIENT_C20_VALUE 20:0 +#define NVC87E_SET_CSC01COEFFICIENT_C21 (0x000004E4) +#define NVC87E_SET_CSC01COEFFICIENT_C21_VALUE 20:0 +#define NVC87E_SET_CSC01COEFFICIENT_C22 (0x000004E8) +#define NVC87E_SET_CSC01COEFFICIENT_C22_VALUE 20:0 +#define NVC87E_SET_CSC01COEFFICIENT_C23 (0x000004EC) +#define NVC87E_SET_CSC01COEFFICIENT_C23_VALUE 20:0 +#define NVC87E_SET_TMO_CONTROL (0x00000500) +#define NVC87E_SET_TMO_CONTROL_INTERPOLATE 0:0 +#define NVC87E_SET_TMO_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC87E_SET_TMO_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC87E_SET_TMO_CONTROL_SAT_MODE 3:2 +#define NVC87E_SET_TMO_CONTROL_SIZE 18:8 +#define NVC87E_SET_TMO_LOW_INTENSITY_ZONE (0x00000508) +#define NVC87E_SET_TMO_LOW_INTENSITY_ZONE_END 29:16 +#define NVC87E_SET_TMO_LOW_INTENSITY_VALUE (0x0000050C) +#define NVC87E_SET_TMO_LOW_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVC87E_SET_TMO_LOW_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVC87E_SET_TMO_LOW_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVC87E_SET_TMO_MEDIUM_INTENSITY_ZONE (0x00000510) +#define NVC87E_SET_TMO_MEDIUM_INTENSITY_ZONE_START 13:0 +#define NVC87E_SET_TMO_MEDIUM_INTENSITY_ZONE_END 29:16 +#define NVC87E_SET_TMO_MEDIUM_INTENSITY_VALUE (0x00000514) +#define NVC87E_SET_TMO_MEDIUM_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVC87E_SET_TMO_MEDIUM_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVC87E_SET_TMO_MEDIUM_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVC87E_SET_TMO_HIGH_INTENSITY_ZONE (0x00000518) +#define NVC87E_SET_TMO_HIGH_INTENSITY_ZONE_START 13:0 +#define NVC87E_SET_TMO_HIGH_INTENSITY_VALUE (0x0000051C) +#define NVC87E_SET_TMO_HIGH_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVC87E_SET_TMO_HIGH_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVC87E_SET_TMO_HIGH_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVC87E_SET_CONTEXT_DMA_TMO_LUT (0x00000528) +#define NVC87E_SET_CONTEXT_DMA_TMO_LUT_HANDLE 31:0 +#define NVC87E_SET_OFFSET_TMO_LUT (0x0000052C) +#define NVC87E_SET_OFFSET_TMO_LUT_ORIGIN 31:0 +#define NVC87E_SET_CSC10CONTROL (0x0000053C) +#define NVC87E_SET_CSC10CONTROL_ENABLE 0:0 +#define NVC87E_SET_CSC10CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC87E_SET_CSC10CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC87E_SET_CSC10COEFFICIENT_C00 (0x00000540) +#define NVC87E_SET_CSC10COEFFICIENT_C00_VALUE 20:0 +#define NVC87E_SET_CSC10COEFFICIENT_C01 (0x00000544) +#define NVC87E_SET_CSC10COEFFICIENT_C01_VALUE 20:0 +#define NVC87E_SET_CSC10COEFFICIENT_C02 (0x00000548) +#define NVC87E_SET_CSC10COEFFICIENT_C02_VALUE 20:0 +#define NVC87E_SET_CSC10COEFFICIENT_C03 (0x0000054C) +#define NVC87E_SET_CSC10COEFFICIENT_C03_VALUE 20:0 +#define NVC87E_SET_CSC10COEFFICIENT_C10 (0x00000550) +#define NVC87E_SET_CSC10COEFFICIENT_C10_VALUE 20:0 +#define NVC87E_SET_CSC10COEFFICIENT_C11 (0x00000554) +#define NVC87E_SET_CSC10COEFFICIENT_C11_VALUE 20:0 +#define NVC87E_SET_CSC10COEFFICIENT_C12 (0x00000558) +#define NVC87E_SET_CSC10COEFFICIENT_C12_VALUE 20:0 +#define NVC87E_SET_CSC10COEFFICIENT_C13 (0x0000055C) +#define NVC87E_SET_CSC10COEFFICIENT_C13_VALUE 20:0 +#define NVC87E_SET_CSC10COEFFICIENT_C20 (0x00000560) +#define NVC87E_SET_CSC10COEFFICIENT_C20_VALUE 20:0 +#define NVC87E_SET_CSC10COEFFICIENT_C21 (0x00000564) +#define NVC87E_SET_CSC10COEFFICIENT_C21_VALUE 20:0 +#define NVC87E_SET_CSC10COEFFICIENT_C22 (0x00000568) +#define NVC87E_SET_CSC10COEFFICIENT_C22_VALUE 20:0 +#define NVC87E_SET_CSC10COEFFICIENT_C23 (0x0000056C) +#define NVC87E_SET_CSC10COEFFICIENT_C23_VALUE 20:0 +#define NVC87E_SET_CSC1LUT_CONTROL (0x00000580) +#define NVC87E_SET_CSC1LUT_CONTROL_INTERPOLATE 0:0 +#define NVC87E_SET_CSC1LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC87E_SET_CSC1LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC87E_SET_CSC1LUT_CONTROL_MIRROR 1:1 +#define NVC87E_SET_CSC1LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC87E_SET_CSC1LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC87E_SET_CSC1LUT_CONTROL_ENABLE 4:4 +#define NVC87E_SET_CSC1LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC87E_SET_CSC1LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC87E_SET_CSC1LUT_SEGMENT_SIZE (0x00000584) +#define NVC87E_SET_CSC1LUT_SEGMENT_SIZE_IDX 5:0 +#define NVC87E_SET_CSC1LUT_SEGMENT_SIZE_VALUE 18:16 +#define NVC87E_SET_CSC1LUT_ENTRY (0x00000588) +#define NVC87E_SET_CSC1LUT_ENTRY_IDX 10:0 +#define NVC87E_SET_CSC1LUT_ENTRY_VALUE 31:16 +#define NVC87E_SET_CSC11CONTROL (0x0000059C) +#define NVC87E_SET_CSC11CONTROL_ENABLE 0:0 +#define NVC87E_SET_CSC11CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC87E_SET_CSC11CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC87E_SET_CSC11COEFFICIENT_C00 (0x000005A0) +#define NVC87E_SET_CSC11COEFFICIENT_C00_VALUE 20:0 +#define NVC87E_SET_CSC11COEFFICIENT_C01 (0x000005A4) +#define NVC87E_SET_CSC11COEFFICIENT_C01_VALUE 20:0 +#define NVC87E_SET_CSC11COEFFICIENT_C02 (0x000005A8) +#define NVC87E_SET_CSC11COEFFICIENT_C02_VALUE 20:0 +#define NVC87E_SET_CSC11COEFFICIENT_C03 (0x000005AC) +#define NVC87E_SET_CSC11COEFFICIENT_C03_VALUE 20:0 +#define NVC87E_SET_CSC11COEFFICIENT_C10 (0x000005B0) +#define NVC87E_SET_CSC11COEFFICIENT_C10_VALUE 20:0 +#define NVC87E_SET_CSC11COEFFICIENT_C11 (0x000005B4) +#define NVC87E_SET_CSC11COEFFICIENT_C11_VALUE 20:0 +#define NVC87E_SET_CSC11COEFFICIENT_C12 (0x000005B8) +#define NVC87E_SET_CSC11COEFFICIENT_C12_VALUE 20:0 +#define NVC87E_SET_CSC11COEFFICIENT_C13 (0x000005BC) +#define NVC87E_SET_CSC11COEFFICIENT_C13_VALUE 20:0 +#define NVC87E_SET_CSC11COEFFICIENT_C20 (0x000005C0) +#define NVC87E_SET_CSC11COEFFICIENT_C20_VALUE 20:0 +#define NVC87E_SET_CSC11COEFFICIENT_C21 (0x000005C4) +#define NVC87E_SET_CSC11COEFFICIENT_C21_VALUE 20:0 +#define NVC87E_SET_CSC11COEFFICIENT_C22 (0x000005C8) +#define NVC87E_SET_CSC11COEFFICIENT_C22_VALUE 20:0 +#define NVC87E_SET_CSC11COEFFICIENT_C23 (0x000005CC) +#define NVC87E_SET_CSC11COEFFICIENT_C23_VALUE 20:0 +#define NVC87E_SET_CLAMP_RANGE (0x000005D0) +#define NVC87E_SET_CLAMP_RANGE_LOW 15:0 +#define NVC87E_SET_CLAMP_RANGE_HIGH 31:16 +#define NVC87E_SW_RESERVED(b) (0x000005D4 + (b)*0x00000004) +#define NVC87E_SW_RESERVED_VALUE 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC87e_h diff --git a/userspace/sdks/nv570/inc/class/clc8b5.h b/userspace/sdks/nv570/inc/class/clc8b5.h new file mode 100644 index 0000000..2676dc5 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc8b5.h @@ -0,0 +1,137 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clc8b5_h__ +#define __gh100_clc8b5_h__ + +#define HOPPER_DMA_COPY_A (0x0000C8B5) +#define NVC8B5_SET_SEMAPHORE_A (0x00000240) +#define NVC8B5_SET_SEMAPHORE_A_UPPER 24:0 +#define NVC8B5_SET_SEMAPHORE_B (0x00000244) +#define NVC8B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC8B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC8B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC8B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVC8B5_SET_SRC_PHYS_MODE_PEER_ID 8:6 +#define NVC8B5_SET_SRC_PHYS_MODE_FLA 9:9 +#define NVC8B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC8B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC8B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC8B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC8B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC8B5_SET_DST_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVC8B5_LAUNCH_DMA (0x00000300) +#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_FLUSH_TYPE 25:25 +#define NVC8B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000) +#define NVC8B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_NO_TIMESTAMP (0x00000001) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_WITH_TIMESTAMP (0x00000002) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC8B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC8B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC8B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC8B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC8B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC8B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC8B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC8B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC8B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_COPY_TYPE 21:20 +#define NVC8B5_LAUNCH_DMA_COPY_TYPE_PROT2PROT (0x00000000) +#define NVC8B5_LAUNCH_DMA_COPY_TYPE_DEFAULT (0x00000000) +#define NVC8B5_LAUNCH_DMA_COPY_TYPE_SECURE (0x00000001) +#define NVC8B5_LAUNCH_DMA_COPY_TYPE_NONPROT2NONPROT (0x00000002) +#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE 23:23 +#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_FALSE (0x00000000) +#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_DISABLE_PLC 26:26 +#define NVC8B5_LAUNCH_DMA_DISABLE_PLC_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE 27:27 +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_ONE_WORD (0x00000000) +#define NVC8B5_OFFSET_IN_UPPER (0x00000400) +#define NVC8B5_OFFSET_IN_UPPER_UPPER 24:0 +#define NVC8B5_OFFSET_IN_LOWER (0x00000404) +#define NVC8B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC8B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC8B5_OFFSET_OUT_UPPER_UPPER 24:0 +#define NVC8B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC8B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC8B5_LINE_LENGTH_IN (0x00000418) +#define NVC8B5_SET_SECURE_COPY_MODE (0x00000500) +#define NVC8B5_SET_SECURE_COPY_MODE_MODE 0:0 +#define NVC8B5_SET_SECURE_COPY_MODE_MODE_ENCRYPT (0x00000000) +#define NVC8B5_SET_SECURE_COPY_MODE_MODE_DECRYPT (0x00000001) +#define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER (0x00000514) +#define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER_UPPER 24:0 +#define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER (0x00000518) +#define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER_LOWER 31:0 +#define NVC8B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER (0x00000530) +#define NVC8B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER_UPPER 24:0 +#define NVC8B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER (0x00000534) +#define NVC8B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER_LOWER 31:0 +#define NVC8B5_SET_ENCRYPT_IV_ADDR_UPPER (0x00000538) +#define NVC8B5_SET_ENCRYPT_IV_ADDR_UPPER_UPPER 24:0 +#define NVC8B5_SET_ENCRYPT_IV_ADDR_LOWER (0x0000053C) +#define NVC8B5_SET_ENCRYPT_IV_ADDR_LOWER_LOWER 31:0 +#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS (0x000006FC) +#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE 0:0 +#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_FALSE (0x00000000) +#define NVC8B5_SET_REMAP_CONST_A (0x00000700) +#define NVC8B5_SET_REMAP_CONST_B (0x00000704) +#define NVC8B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#endif // __gh100_clc8b5_h__ diff --git a/userspace/sdks/nv570/inc/class/clc96f.h b/userspace/sdks/nv570/inc/class/clc96f.h new file mode 100644 index 0000000..14b8a5d --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc96f.h @@ -0,0 +1,113 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gb100_clc96f_h__ +#define __gb100_clc96f_h__ + +#define BLACKWELL_CHANNEL_GPFIFO_A (0x0000C96F) + +typedef volatile struct Nvc96fControl_struct { + NvU32 Ignored00[0x23]; /* 0000-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored01[0x5c]; +} Nvc96fControl, BlackwellAControlGPFifo; + +#define NVC96F_SET_OBJECT (0x00000000) +#define NVC96F_MEM_OP_A (0x00000028) +#define NVC96F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type +#define NVC96F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE 7:6 // only relevant for invalidates with NVC96F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE for invalidating link TLB only, or non-link TLB only or all TLBs +#define NVC96F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS 2 +#define NVC96F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11 +#define NVC96F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001 +#define NVC96F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000 +#define NVC96F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12 +#define NVC96F_MEM_OP_B (0x0000002c) +#define NVC96F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0 +#define NVC96F_MEM_OP_C (0x00000030) +#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0 +#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED +#define NVC96F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1 +#define NVC96F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVC96F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVC96F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE +#define NVC96F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000 +#define NVC96F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE +#define NVC96F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000 +#define NVC96F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001 +#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below +#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table +#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001 +#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006 +#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE +#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 +#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE + +#define NVC96F_MEM_OP_D (0x00000034) +#define NVC96F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE +#define NVC96F_MEM_OP_D_OPERATION 31:27 +#define NVC96F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVC96F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a +#define NVC96F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVC96F_MEM_OP_D_OPERATION_L2_SYSMEM_NCOH_INVALIDATE 0x00000011 + +#define NVC96F_SEM_ADDR_LO (0x0000005c) +#define NVC96F_SEM_ADDR_LO_OFFSET 31:2 +#define NVC96F_SEM_ADDR_HI (0x00000060) +#define NVC96F_SEM_ADDR_HI_OFFSET 24:0 +#define NVC96F_SEM_PAYLOAD_LO (0x00000064) +#define NVC96F_SEM_PAYLOAD_HI (0x00000068) +#define NVC96F_SEM_EXECUTE (0x0000006c) +#define NVC96F_SEM_EXECUTE_OPERATION 2:0 +#define NVC96F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000 +#define NVC96F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001 +#define NVC96F_SEM_EXECUTE_RELEASE_WFI 20:20 +#define NVC96F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000 +#define NVC96F_SEM_EXECUTE_PAYLOAD_SIZE 24:24 +#define NVC96F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000 + +/* GPFIFO entry format */ +#define NVC96F_GP_ENTRY__SIZE 8 +#define NVC96F_GP_ENTRY0_FETCH 0:0 +#define NVC96F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVC96F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVC96F_GP_ENTRY0_GET 31:2 +#define NVC96F_GP_ENTRY0_OPERAND 31:0 +#define NVC96F_GP_ENTRY0_PB_EXTENDED_BASE_OPERAND 24:8 +#define NVC96F_GP_ENTRY1_GET_HI 7:0 +#define NVC96F_GP_ENTRY1_LEVEL 9:9 +#define NVC96F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVC96F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVC96F_GP_ENTRY1_LENGTH 30:10 +#define NVC96F_GP_ENTRY1_SYNC 31:31 +#define NVC96F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVC96F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVC96F_GP_ENTRY1_OPCODE 7:0 +#define NVC96F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVC96F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVC96F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVC96F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 +#define NVC96F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE 0x00000004 + +#endif // __gb100_clc96f_h__ diff --git a/userspace/sdks/nv570/inc/class/clc96fsw.h b/userspace/sdks/nv570/inc/class/clc96fsw.h new file mode 100644 index 0000000..d34715a --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc96fsw.h @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* This file is *not* auto-generated. */ + +#ifndef _clc96f_sw_h_ +#define _clc96f_sw_h_ + +#define NVC96F_NOTIFIERS_RC (0) +#define NVC96F_NOTIFIERS_REFCNT (1) +#define NVC96F_NOTIFIERS_NONSTALL (2) +#define NVC96F_NOTIFIERS_EVENTBUFFER (3) +#define NVC96F_NOTIFIERS_IDLECHANNEL (4) +#define NVC96F_NOTIFIERS_ENDCTX (5) +#define NVC96F_NOTIFIERS_SW (6) +#define NVC96F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVC96F_NOTIFIERS_REPLAYABLE_FAULT (8) +#define NVC96F_NOTIFIERS_KEY_ROTATION (9) +#define NVC96F_NOTIFIERS_MAXCOUNT (10) + +/* NvNotification[] fields and values */ +#define NVC96F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVC96F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _clc96f_sw_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc970.h b/userspace/sdks/nv570/inc/class/clc970.h new file mode 100644 index 0000000..769cd74 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc970.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc970.finn +// + +#define NVC970_DISPLAY (0xc970U) /* finn: Evaluated from "NVC970_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NVC970_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc970U) + +typedef struct NVC970_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numDsis; // Number of DSIs in this chip/display +} NVC970_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clc971.h b/userspace/sdks/nv570/inc/class/clc971.h new file mode 100644 index 0000000..7cdb433 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc971.h @@ -0,0 +1,329 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc971_h_ +#define _clc971_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC971_DISP_SF_USER (0x000C971) + +typedef volatile struct { + NvU32 dispSfUserOffset[0x400]; +} _NvC971DispSfUser, NvC971DispSfUserMap; + +#define NVC971_SF_HDMI_INFO_IDX_AVI_INFOFRAME 0x00000000 /* */ +#define NVC971_SF_HDMI_INFO_IDX_GCP 0x00000001 /* */ +#define NVC971_SF_HDMI_INFO_IDX_ACR 0x00000002 /* */ +#define NVC971_SF_HDMI_INFO_CTRL(i,j) (0x000E0000-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVC971_SF_HDMI_INFO_CTRL__SIZE_1 8 /* */ +#define NVC971_SF_HDMI_INFO_CTRL__SIZE_2 3 /* */ +#define NVC971_SF_HDMI_INFO_CTRL_ENABLE 0:0 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NVC971_SF_HDMI_INFO_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NVC971_SF_HDMI_INFO_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NVC971_SF_HDMI_INFO_CTRL_CHKSUM_HW 9:9 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */ +#define NVC971_SF_HDMI_INFO_CTRL_CHKSUM_HW_EN 0x00000001 /* RW--V */ +#define NVC971_SF_HDMI_INFO_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */ +#define NVC971_SF_HDMI_INFO_CTRL_CHKSUM_HW_DIS 0x00000000 /* RW--V */ +#define NVC971_SF_HDMI_INFO_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_CTRL_HBLANK 12:12 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_CTRL_HBLANK_DIS 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_CTRL_HBLANK_EN 0x00000001 /* RW--V */ +#define NVC971_SF_HDMI_INFO_CTRL_VIDEO_FMT 16:16 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_CTRL_VIDEO_FMT_SW_CONTROLLED 0x00000000 /* RW--V */ +#define NVC971_SF_HDMI_INFO_CTRL_VIDEO_FMT_HW_CONTROLLED 0x00000001 /* RW--V */ +#define NVC971_SF_HDMI_INFO_CTRL_VIDEO_FMT_INIT 0x00000001 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_STATUS(i,j) (0x000E0004-0x000E0000+(i)*1024+(j)*64) /* R--4A */ +#define NVC971_SF_HDMI_INFO_STATUS__SIZE_1 8 /* */ +#define NVC971_SF_HDMI_INFO_STATUS__SIZE_2 3 /* */ +#define NVC971_SF_HDMI_INFO_STATUS_SENT 0:0 /* R--VF */ +#define NVC971_SF_HDMI_INFO_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NVC971_SF_HDMI_INFO_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NVC971_SF_HDMI_INFO_HEADER(i,j) (0x000E0008-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVC971_SF_HDMI_INFO_HEADER__SIZE_1 8 /* */ +#define NVC971_SF_HDMI_INFO_HEADER__SIZE_2 3 /* */ +#define NVC971_SF_HDMI_INFO_HEADER_HB0 7:0 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_HEADER_HB1 15:8 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_HEADER_HB2 23:16 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK0_LOW(i,j) (0x000E000C-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVC971_SF_HDMI_INFO_SUBPACK0_LOW__SIZE_1 8 /* */ +#define NVC971_SF_HDMI_INFO_SUBPACK0_LOW__SIZE_2 3 /* */ +#define NVC971_SF_HDMI_INFO_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK0_HIGH(i,j) (0x000E0010-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVC971_SF_HDMI_INFO_SUBPACK0_HIGH__SIZE_1 8 /* */ +#define NVC971_SF_HDMI_INFO_SUBPACK0_HIGH__SIZE_2 3 /* */ +#define NVC971_SF_HDMI_INFO_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK1_LOW(i,j) (0x000E0014-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVC971_SF_HDMI_INFO_SUBPACK1_LOW__SIZE_1 8 /* */ +#define NVC971_SF_HDMI_INFO_SUBPACK1_LOW__SIZE_2 3 /* */ +#define NVC971_SF_HDMI_INFO_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK1_HIGH(i,j) (0x000E0018-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVC971_SF_HDMI_INFO_SUBPACK1_HIGH__SIZE_1 8 /* */ +#define NVC971_SF_HDMI_INFO_SUBPACK1_HIGH__SIZE_2 3 /* */ +#define NVC971_SF_HDMI_INFO_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK2_LOW(i,j) (0x000E001C-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVC971_SF_HDMI_INFO_SUBPACK2_LOW__SIZE_1 8 /* */ +#define NVC971_SF_HDMI_INFO_SUBPACK2_LOW__SIZE_2 3 /* */ +#define NVC971_SF_HDMI_INFO_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK2_HIGH(i,j) (0x000E0020-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVC971_SF_HDMI_INFO_SUBPACK2_HIGH__SIZE_1 8 /* */ +#define NVC971_SF_HDMI_INFO_SUBPACK2_HIGH__SIZE_2 3 /* */ +#define NVC971_SF_HDMI_INFO_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK3_LOW(i,j) (0x000E0024-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVC971_SF_HDMI_INFO_SUBPACK3_LOW__SIZE_1 8 /* */ +#define NVC971_SF_HDMI_INFO_SUBPACK3_LOW__SIZE_2 3 /* */ +#define NVC971_SF_HDMI_INFO_SUBPACK3_LOW_PB21 7:0 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK3_LOW_PB22 15:8 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK3_LOW_PB23 23:16 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK3_LOW_PB24 31:24 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK3_HIGH(i,j) (0x000E0028-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVC971_SF_HDMI_INFO_SUBPACK3_HIGH__SIZE_1 8 /* */ +#define NVC971_SF_HDMI_INFO_SUBPACK3_HIGH__SIZE_2 3 /* */ +#define NVC971_SF_HDMI_INFO_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_INFO_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */ +#define NVC971_SF_HDMI_INFO_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x000E0000-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 8 /* */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW 9:9 /* RWIVF */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_STATUS(i) (0x000E0004-0x000E0000+(i)*1024) /* R--4A */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1 8 /* */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_STATUS_SENT 0:0 /* R-IVF */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT 0x00000000 /* R-I-V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x000E0008-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 8 /* */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x000E000C-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 8 /* */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x000E0010-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 8 /* */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x000E0014-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 8 /* */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x000E0018-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 8 /* */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW(i) (0x000E001C-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW__SIZE_1 8 /* */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NVC971_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_GCP_CTRL(i) (0x000E0040-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC971_SF_HDMI_GCP_CTRL__SIZE_1 8 /* */ +#define NVC971_SF_HDMI_GCP_CTRL_ENABLE 0:0 /* RWIVF */ +#define NVC971_SF_HDMI_GCP_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_GCP_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NVC971_SF_HDMI_GCP_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NVC971_SF_HDMI_GCP_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NVC971_SF_HDMI_GCP_STATUS(i) (0x000E0044-0x000E0000+(i)*1024) /* R--4A */ +#define NVC971_SF_HDMI_GCP_STATUS__SIZE_1 8 /* */ +#define NVC971_SF_HDMI_GCP_STATUS_SENT 0:0 /* R-IVF */ +#define NVC971_SF_HDMI_GCP_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NVC971_SF_HDMI_GCP_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NVC971_SF_HDMI_GCP_STATUS_SENT_INIT 0x00000000 /* R-I-V */ +#define NVC971_SF_HDMI_GCP_SUBPACK(i) (0x000E004C-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC971_SF_HDMI_GCP_SUBPACK__SIZE_1 8 /* */ +#define NVC971_SF_HDMI_GCP_SUBPACK_SB0 7:0 /* RWIVF */ +#define NVC971_SF_HDMI_GCP_SUBPACK_SB0_INIT 0x00000001 /* RWI-V */ +#define NVC971_SF_HDMI_GCP_SUBPACK_SB0_SET_AVMUTE 0x00000001 /* RW--V */ +#define NVC971_SF_HDMI_GCP_SUBPACK_SB0_CLR_AVMUTE 0x00000010 /* RW--V */ +#define NVC971_SF_HDMI_GCP_SUBPACK_SB1 15:8 /* RWIVF */ +#define NVC971_SF_HDMI_GCP_SUBPACK_SB1_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_GCP_SUBPACK_SB2 23:16 /* RWIVF */ +#define NVC971_SF_HDMI_GCP_SUBPACK_SB2_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_HDMI_GCP_SUBPACK_SB1_CTRL 24:24 /* RWIVF */ +#define NVC971_SF_HDMI_GCP_SUBPACK_SB1_CTRL_INIT 0x00000001 /* RWI-V */ +#define NVC971_SF_HDMI_GCP_SUBPACK_SB1_CTRL_SW 0x00000000 /* RW--V */ +#define NVC971_SF_HDMI_GCP_SUBPACK_SB1_CTRL_HW 0x00000001 /* RW--V */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL(i,j) (0x000E0130-0x000E0000+(i)*1024+(j)*8) /* RW-4A */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL__SIZE_1 8 /* */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL__SIZE_2 10 /* */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE 3:1 /* RWIVF */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_ALWAYS 0x00000000 /* RWI-V */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_ONCE 0x00000001 /* RW--V */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_ALWAYS 0x00000002 /* RW--V */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_ONCE 0x00000003 /* RW--V */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_TRIGGER 0x00000004 /* RW--V */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL_LOC 5:4 /* RWIVF */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL_LOC_VBLANK 0x00000000 /* RWI-V */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL_LOC_VSYNC 0x00000001 /* RW--V */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL_LOC_LINE 0x00000002 /* RW--V */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL_OFFSET 10:6 /* RWIVF */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL_SIZE 18:14 /* RWIVF */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL_SIZE_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL_BUSY 22:22 /* R-IVF */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL_BUSY_NO 0x00000000 /* R-I-V */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL_BUSY_YES 0x00000001 /* R---V */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL_SENT 23:23 /* RWIVF */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL_SENT_NO 0x00000000 /* R-I-V */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL_SENT_YES 0x00000001 /* R---V */ +#define NVC971_SF_GENERIC_INFOFRAME_CTRL_SENT_CLEAR 0x00000001 /* -W--C */ +#define NVC971_SF_GENERIC_INFOFRAME_CONFIG(i,j) (0x000E0134-0x000E0000+(i)*1024+(j)*8) /* RW-4A */ +#define NVC971_SF_GENERIC_INFOFRAME_CONFIG__SIZE_1 8 /* */ +#define NVC971_SF_GENERIC_INFOFRAME_CONFIG__SIZE_2 10 /* */ +#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_FID 7:0 /* RWIVF */ +#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_FID_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID 23:8 /* RWIVF */ +#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED 24:24 /* RWIVF */ +#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED_NO 0x00000000 /* RWI-V */ +#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED_YES 0x00000001 /* RW--V */ +#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN 25:25 /* RWIVF */ +#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN_NO 0x00000000 /* RWI-V */ +#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN_YES 0x00000001 /* RW--V */ +#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM 29:29 /* RWIVF */ +#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM_NO 0x00000000 /* RWI-V */ +#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM_YES 0x00000001 /* RW--V */ +#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_NEW 30:30 /* RWIVF */ +#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_NEW_INIT 0x00000000 /* R-I-V */ +#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_NEW_DONE 0x00000000 /* R---V */ +#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_NEW_PENDING 0x00000001 /* R---T */ +#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_NEW_TRIGGER 0x00000001 /* -W--T */ +#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL 31:31 /* RWIVF */ +#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL_ACT 0x00000000 /* RWI-V */ +#define NVC971_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL_ARM 0x00000001 /* RW--V */ +#define NVC971_SF_GENERIC_INFOFRAME_DATA_CTRL(i) (0x000E03F0-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC971_SF_GENERIC_INFOFRAME_DATA_CTRL__SIZE_1 8 /* */ +#define NVC971_SF_GENERIC_INFOFRAME_DATA_CTRL_OFFSET 4:0 /* RWIVF */ +#define NVC971_SF_GENERIC_INFOFRAME_DATA_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_GENERIC_INFOFRAME_DATA(i) (0x000E03F4-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC971_SF_GENERIC_INFOFRAME_DATA__SIZE_1 8 /* */ +#define NVC971_SF_GENERIC_INFOFRAME_DATA_BYTE0 7:0 /* RWIVF */ +#define NVC971_SF_GENERIC_INFOFRAME_DATA_BYTE0_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_GENERIC_INFOFRAME_DATA_BYTE1 15:8 /* RWIVF */ +#define NVC971_SF_GENERIC_INFOFRAME_DATA_BYTE1_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_GENERIC_INFOFRAME_DATA_BYTE2 23:16 /* RWIVF */ +#define NVC971_SF_GENERIC_INFOFRAME_DATA_BYTE2_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_GENERIC_INFOFRAME_DATA_BYTE3 31:24 /* RWIVF */ +#define NVC971_SF_GENERIC_INFOFRAME_DATA_BYTE3_INIT 0x00000000 /* RWI-V */ +#define NVC971_SF_GENERIC_INFOFRAME_MISC_CTRL(i) (0x000E03F8-0x000E0000+(i)*1024) /* RW-4A */ +#define NVC971_SF_GENERIC_INFOFRAME_MISC_CTRL__SIZE_1 8 /* */ +#define NVC971_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY 1:1 /* RWIVF */ +#define NVC971_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY_HIGH 0x00000000 /* RW--V */ +#define NVC971_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY_LOW 0x00000001 /* RWI-V */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _clc971_h_ diff --git a/userspace/sdks/nv570/inc/class/clc973.h b/userspace/sdks/nv570/inc/class/clc973.h new file mode 100644 index 0000000..f770493 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc973.h @@ -0,0 +1,379 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc973_h_ +#define _clc973_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC973_DISP_CAPABILITIES 0xC973 + +#define NVC973_SYS_CAP 0x0 /* RW-4R */ +#define NVC973_SYS_CAP_HEAD0_EXISTS 0:0 /* RWIVF */ +#define NVC973_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC973_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC973_SYS_CAP_HEAD1_EXISTS 1:1 /* RWIVF */ +#define NVC973_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC973_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC973_SYS_CAP_HEAD2_EXISTS 2:2 /* RWIVF */ +#define NVC973_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC973_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC973_SYS_CAP_HEAD3_EXISTS 3:3 /* RWIVF */ +#define NVC973_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC973_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC973_SYS_CAP_HEAD4_EXISTS 4:4 /* RWIVF */ +#define NVC973_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC973_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC973_SYS_CAP_HEAD5_EXISTS 5:5 /* RWIVF */ +#define NVC973_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC973_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC973_SYS_CAP_HEAD6_EXISTS 6:6 /* RWIVF */ +#define NVC973_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC973_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC973_SYS_CAP_HEAD7_EXISTS 7:7 /* RWIVF */ +#define NVC973_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC973_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC973_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVC973_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */ +#define NVC973_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC973_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC973_SYS_CAP_SOR0_EXISTS 8:8 /* RWIVF */ +#define NVC973_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC973_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC973_SYS_CAP_SOR1_EXISTS 9:9 /* RWIVF */ +#define NVC973_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC973_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC973_SYS_CAP_SOR2_EXISTS 10:10 /* RWIVF */ +#define NVC973_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC973_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC973_SYS_CAP_SOR3_EXISTS 11:11 /* RWIVF */ +#define NVC973_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC973_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC973_SYS_CAP_SOR4_EXISTS 12:12 /* RWIVF */ +#define NVC973_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC973_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC973_SYS_CAP_SOR5_EXISTS 13:13 /* RWIVF */ +#define NVC973_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC973_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC973_SYS_CAP_SOR6_EXISTS 14:14 /* RWIVF */ +#define NVC973_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC973_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC973_SYS_CAP_SOR7_EXISTS 15:15 /* RWIVF */ +#define NVC973_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC973_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC973_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* RWIVF */ +#define NVC973_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */ +#define NVC973_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC973_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC973_SYS_CAP_DSI0_EXISTS 20:20 /* RWIVF */ +#define NVC973_SYS_CAP_DSI0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC973_SYS_CAP_DSI0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC973_SYS_CAP_DSI1_EXISTS 21:21 /* RWIVF */ +#define NVC973_SYS_CAP_DSI1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC973_SYS_CAP_DSI1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC973_SYS_CAP_DSI2_EXISTS 22:22 /* RWIVF */ +#define NVC973_SYS_CAP_DSI2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC973_SYS_CAP_DSI2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC973_SYS_CAP_DSI3_EXISTS 23:23 /* RWIVF */ +#define NVC973_SYS_CAP_DSI3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC973_SYS_CAP_DSI3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC973_SYS_CAP_DSI_EXISTS(i) (20+(i)):(20+(i)) /* RWIVF */ +#define NVC973_SYS_CAP_DSI_EXISTS__SIZE_1 4 /* */ +#define NVC973_SYS_CAP_DSI_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC973_SYS_CAP_DSI_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPA 0x10 /* RW-4R */ +#define NVC973_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES 15:0 /* RWIUF */ +#define NVC973_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH 17:16 /* RWIVF */ +#define NVC973_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B 0x00000000 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B 0x00000001 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B 0x00000002 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B 0x00000003 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPA_SUPPORT_ROTATION 18:18 /* RWIVF */ +#define NVC973_IHUB_COMMON_CAPA_SUPPORT_ROTATION_FALSE 0x00000000 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPA_SUPPORT_ROTATION_TRUE 0x00000001 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPA_SUPPORT_PLANAR 19:19 /* RWIVF */ +#define NVC973_IHUB_COMMON_CAPA_SUPPORT_PLANAR_FALSE 0x00000000 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPA_SUPPORT_PLANAR_TRUE 0x00000001 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPA_SUPPORT_VGA 20:20 /* RWIVF */ +#define NVC973_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE 0x00000000 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE 0x00000001 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION 21:21 /* RWIVF */ +#define NVC973_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_FALSE 0x00000000 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_TRUE 0x00000001 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPA_SUPPORT_MSCG 22:22 /* RWIVF */ +#define NVC973_IHUB_COMMON_CAPA_SUPPORT_MSCG_FALSE 0x00000000 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPA_SUPPORT_MSCG_TRUE 0x00000001 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH 23:23 /* RWIVF */ +#define NVC973_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_FALSE 0x00000000 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_TRUE 0x00000001 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT 26:26 /* RWIVF */ +#define NVC973_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_FALSE 0x00000000 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_TRUE 0x00000001 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION 31:30 /* RWIVF */ +#define NVC973_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B 0x00000000 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B 0x00000001 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B 0x00000002 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B 0x00000003 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPC 0x18 /* RW-4R */ +#define NVC973_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE 1:0 /* RWIVF */ +#define NVC973_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_32B 0x00000000 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_64B 0x00000001 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_128B 0x00000002 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_256B 0x00000003 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED 6:4 /* RWIVF */ +#define NVC973_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_NONE 0x00000000 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_TWO 0x00000001 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_FOUR 0x00000002 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_EIGHT 0x00000003 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_SIXTEEN 0x00000004 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR 11:11 /* RWIVF */ +#define NVC973_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_FALSE 0x00000000 /* RWI-V */ +#define NVC973_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_TRUE 0x00000001 /* RW--V */ +#define NVC973_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP 12:12 /* RWIVF */ +#define NVC973_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_FALSE 0x00000000 /* RWI-V */ +#define NVC973_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_TRUE 0x00000001 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPA(i) (0x680+(i)*32) /* RW-4A */ +#define NVC973_POSTCOMP_HDR_CAPA__SIZE_1 8 /* */ +#define NVC973_POSTCOMP_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPA_OCSC0_PRESENT 16:16 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPA_OCSC0_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPA_OCSC0_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPA_OCSC1_PRESENT 17:17 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPA_OCSC1_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPA_OCSC1_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPA_SCLR_PRESENT 18:18 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPA_HCLPF_PRESENT 19:19 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPA_HCLPF_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPA_HCLPF_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPA_DTH_PRESENT 20:20 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPA_DTH_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPA_DTH_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPA_OSCAN_PRESENT 21:21 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPA_OSCAN_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPA_OSCAN_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPA_DSC_PRESENT 22:22 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPA_DSC_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPA_DSC_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPA_VFILTER_PRESENT 23:23 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPA_VFILTER_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPA_VFILTER_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPB(i) (0x684+(i)*32) /* RW-4A */ +#define NVC973_POSTCOMP_HDR_CAPB__SIZE_1 8 /* */ +#define NVC973_POSTCOMP_HDR_CAPB_VGA 0:0 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPB_VGA_TRUE 0x00000001 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPB_VGA_FALSE 0x00000000 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPB_OLUT_SZ 12:1 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPB_OLUT_LOGNR 15:13 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD 17:17 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPB_OLUT_DIRECT 18:18 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPB_OLUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPB_OLUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPC(i) (0x688+(i)*32) /* RW-4A */ +#define NVC973_POSTCOMP_HDR_CAPC__SIZE_1 8 /* */ +#define NVC973_POSTCOMP_HDR_CAPC_OCSC0_PRECISION 4:0 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPC_OCSC1_PRECISION 12:8 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP 13:13 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPC_SCLR_SF_PRECISION 20:16 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPC_SCLR_CI_PRECISION 24:21 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB 25:25 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPD(i) (0x68c+(i)*32) /* RW-4A */ +#define NVC973_POSTCOMP_HDR_CAPD__SIZE_1 8 /* */ +#define NVC973_POSTCOMP_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPE(i) (0x690+(i)*32) /* RW-4A */ +#define NVC973_POSTCOMP_HDR_CAPE__SIZE_1 8 /* */ +#define NVC973_POSTCOMP_HDR_CAPE_DSC_NATIVE422 16:16 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPE_DSC_NATIVE422_TRUE 0x00000001 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPE_DSC_NATIVE422_FALSE 0x00000000 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPE_DSC_NATIVE420 17:17 /* RWIVF */ +#define NVC973_POSTCOMP_HDR_CAPE_DSC_NATIVE420_TRUE 0x00000001 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPE_DSC_NATIVE420_FALSE 0x00000000 /* RW--V */ +#define NVC973_POSTCOMP_HDR_CAPF(i) (0x694+(i)*32) /* RW-4A */ +#define NVC973_POSTCOMP_HDR_CAPF__SIZE_1 8 /* */ +#define NVC973_POSTCOMP_HDR_CAPF_VFILTER_MAX_PIXELS 15:0 /* RWIVF */ +#define NVC973_SOR_CAP(i) (0x144+(i)*8) /* RW-4A */ +#define NVC973_SOR_CAP__SIZE_1 8 /* */ +#define NVC973_SOR_CAP_SINGLE_LVDS_18 0:0 /* RWIVF */ +#define NVC973_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVC973_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVC973_SOR_CAP_SINGLE_LVDS_24 1:1 /* RWIVF */ +#define NVC973_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVC973_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVC973_SOR_CAP_DUAL_LVDS_18 2:2 /* RWIVF */ +#define NVC973_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVC973_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVC973_SOR_CAP_DUAL_LVDS_24 3:3 /* RWIVF */ +#define NVC973_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVC973_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVC973_SOR_CAP_SINGLE_TMDS_A 8:8 /* RWIVF */ +#define NVC973_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* RW--V */ +#define NVC973_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* RW--V */ +#define NVC973_SOR_CAP_SINGLE_TMDS_B 9:9 /* RWIVF */ +#define NVC973_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* RW--V */ +#define NVC973_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* RW--V */ +#define NVC973_SOR_CAP_DUAL_TMDS 11:11 /* RWIVF */ +#define NVC973_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* RW--V */ +#define NVC973_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* RW--V */ +#define NVC973_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* RWIVF */ +#define NVC973_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* RW--V */ +#define NVC973_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* RW--V */ +#define NVC973_SOR_CAP_SDI 16:16 /* RWIVF */ +#define NVC973_SOR_CAP_SDI_FALSE 0x00000000 /* RW--V */ +#define NVC973_SOR_CAP_SDI_TRUE 0x00000001 /* RW--V */ +#define NVC973_SOR_CAP_DP_A 24:24 /* RWIVF */ +#define NVC973_SOR_CAP_DP_A_FALSE 0x00000000 /* RW--V */ +#define NVC973_SOR_CAP_DP_A_TRUE 0x00000001 /* RW--V */ +#define NVC973_SOR_CAP_DP_B 25:25 /* RWIVF */ +#define NVC973_SOR_CAP_DP_B_FALSE 0x00000000 /* RW--V */ +#define NVC973_SOR_CAP_DP_B_TRUE 0x00000001 /* RW--V */ +#define NVC973_SOR_CAP_DP_INTERLACE 26:26 /* RWIVF */ +#define NVC973_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* RW--V */ +#define NVC973_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* RW--V */ +#define NVC973_SOR_CAP_DP_8_LANES 27:27 /* RWIVF */ +#define NVC973_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* RW--V */ +#define NVC973_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* RW--V */ +#define NVC973_SOR_CAP_HDMI_FRL 28:28 /* RWIVF */ +#define NVC973_SOR_CAP_HDMI_FRL_FALSE 0x00000000 /* RW--V */ +#define NVC973_SOR_CAP_HDMI_FRL_TRUE 0x00000001 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA(i) (0x780+(i)*32) /* RW-4A */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA__SIZE_1 32 /* */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH 13:10 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT 16:16 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT 17:17 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT 18:18 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT 19:19 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT 20:20 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT 21:21 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT 22:22 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT 23:23 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT 24:24 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPB(i) (0x784+(i)*32) /* RW-4A */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPB__SIZE_1 32 /* */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION 4:0 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ 9:6 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR 12:10 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT 15:15 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC(i) (0x788+(i)*32) /* RW-4A */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC__SIZE_1 32 /* */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION 4:0 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT 15:15 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION 20:16 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP 21:21 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD(i) (0x78c+(i)*32) /* RW-4A */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD__SIZE_1 32 /* */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ 3:0 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR 6:4 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD 8:8 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT 9:9 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION 16:12 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION 20:17 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB 21:21 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA 22:22 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_TRUE 0x00000001 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_FALSE 0x00000000 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE(i) (0x790+(i)*32) /* RW-4A */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE__SIZE_1 32 /* */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION 4:0 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT 15:15 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION 20:16 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP 21:21 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPF(i) (0x794+(i)*32) /* RW-4A */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPF__SIZE_1 32 /* */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */ +#define NVC973_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */ + +#ifdef __cplusplus +}; +#endif /* extern C */ +#endif //_clc973_h_ diff --git a/userspace/sdks/nv570/inc/class/clc97a.h b/userspace/sdks/nv570/inc/class/clc97a.h new file mode 100644 index 0000000..fd26c95 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc97a.h @@ -0,0 +1,168 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc97a__h_ +#define _clc97a__h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC97A_CURSOR_IMM_CHANNEL_PIO (0x0000C97A) + +#define NVC97A_FREE (0x00000008) +#define NVC97A_FREE_COUNT 5:0 +#define NVC97A_UPDATE (0x00000200) +#define NVC97A_SET_INTERLOCK_FLAGS (0x00000204) +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC97A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC97A_SET_CURSOR_HOT_SPOT_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVC97A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0 +#define NVC97A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS (0x00000210) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC97A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc97a_h diff --git a/userspace/sdks/nv570/inc/class/clc97b.h b/userspace/sdks/nv570/inc/class/clc97b.h new file mode 100644 index 0000000..40c1e10 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc97b.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc97b_h_ +#define _clc97b_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC97B_WINDOW_IMM_CHANNEL_DMA (0x0000C97B) + +// dma opcode instructions +#define NVC97B_DMA +#define NVC97B_DMA_OPCODE 31:29 +#define NVC97B_DMA_OPCODE_METHOD 0x00000000 +#define NVC97B_DMA_OPCODE_JUMP 0x00000001 +#define NVC97B_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC97B_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC97B_DMA_METHOD_COUNT 27:18 +#define NVC97B_DMA_METHOD_OFFSET 15:2 +#define NVC97B_DMA_DATA 31:0 +#define NVC97B_DMA_DATA_NOP 0x00000000 +#define NVC97B_DMA_JUMP_OFFSET 15:2 +#define NVC97B_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVC97B_PUT (0x00000000) +#define NVC97B_PUT_PTR 9:0 +#define NVC97B_GET (0x00000004) +#define NVC97B_GET_PTR 9:0 +#define NVC97B_UPDATE (0x00000200) +#define NVC97B_UPDATE_INTERLOCK_WITH_WINDOW 1:1 +#define NVC97B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC97B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC97B_SET_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVC97B_SET_POINT_OUT_X 15:0 +#define NVC97B_SET_POINT_OUT_Y 31:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc97b_h diff --git a/userspace/sdks/nv570/inc/class/clc97d.h b/userspace/sdks/nv570/inc/class/clc97d.h new file mode 100644 index 0000000..69254b4 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc97d.h @@ -0,0 +1,1377 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc97d_h_ +#define _clc97d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC97D_CORE_CHANNEL_DMA (0x0000C97D) + +#define NV_DISP_NOTIFIER 0x00000000 +#define NV_DISP_NOTIFIER_SIZEOF 0x00000010 +#define NV_DISP_NOTIFIER__0 0x00000000 +#define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFIER__0_FIELD 8:8 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE 9:9 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001 +#define NV_DISP_NOTIFIER__0_R1 15:10 +#define NV_DISP_NOTIFIER__0_R2 23:16 +#define NV_DISP_NOTIFIER__0_R3 29:24 +#define NV_DISP_NOTIFIER__0_STATUS 31:30 +#define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002 +#define NV_DISP_NOTIFIER__1 0x00000001 +#define NV_DISP_NOTIFIER__1_R4 31:0 +#define NV_DISP_NOTIFIER__2 0x00000002 +#define NV_DISP_NOTIFIER__2_TIMESTAMP_LO 31:0 +#define NV_DISP_NOTIFIER__3 0x00000003 +#define NV_DISP_NOTIFIER__3_TIMESTAMP_HI 31:0 + + +// dma opcode instructions +#define NVC97D_DMA +#define NVC97D_DMA_OPCODE 31:29 +#define NVC97D_DMA_OPCODE_METHOD 0x00000000 +#define NVC97D_DMA_OPCODE_JUMP 0x00000001 +#define NVC97D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC97D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC97D_DMA_METHOD_COUNT 27:18 +#define NVC97D_DMA_METHOD_OFFSET 15:2 +#define NVC97D_DMA_DATA 31:0 +#define NVC97D_DMA_DATA_NOP 0x00000000 +#define NVC97D_DMA_JUMP_OFFSET 15:2 +#define NVC97D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// if cap SUPPORT_FLEXIBLE_WIN_MAPPING is FALSE, this define can be used to obtain which head a window is mapped to +#define NVC37D_WINDOW_MAPPED_TO_HEAD(w) ((w)>>1) +#define NVC37D_GET_VALID_WINDOWMASK_FOR_HEAD(h) ((1<<((h)*2)) | (1<<((h)*2+1))) + + +// class methods +#define NVC97D_PUT (0x00000000) +#define NVC97D_PUT_PTR 9:0 +#define NVC97D_GET (0x00000004) +#define NVC97D_GET_PTR 9:0 +#define NVC97D_UPDATE (0x00000200) +#define NVC97D_UPDATE_SPECIAL_HANDLING 21:20 +#define NVC97D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NVC97D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NVC97D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NVC97D_UPDATE_SPECIAL_HANDLING_REASON 19:12 +#define NVC97D_UPDATE_INHIBIT_INTERRUPTS 24:24 +#define NVC97D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NVC97D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NVC97D_UPDATE_RELEASE_ELV 0:0 +#define NVC97D_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC97D_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC97D_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC97D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC97D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC97D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC97D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC97D_SET_NOTIFIER_CONTROL (0x0000020C) +#define NVC97D_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC97D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC97D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC97D_SET_NOTIFIER_CONTROL_NOTIFY 12:12 +#define NVC97D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NVC97D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NVC97D_SET_CONTROL (0x00000210) +#define NVC97D_SET_CONTROL_FLIP_LOCK_PIN(i) ((i)+0):((i)+0) +#define NVC97D_SET_CONTROL_FLIP_LOCK_PIN__SIZE_1 4 +#define NVC97D_SET_CONTROL_FLIP_LOCK_PIN_DISABLE (0x00000000) +#define NVC97D_SET_CONTROL_FLIP_LOCK_PIN_ENABLE (0x00000001) +#define NVC97D_SET_CONTROL_FLIP_LOCK_PIN0 0:0 +#define NVC97D_SET_CONTROL_FLIP_LOCK_PIN0_DISABLE (0x00000000) +#define NVC97D_SET_CONTROL_FLIP_LOCK_PIN0_ENABLE (0x00000001) +#define NVC97D_SET_CONTROL_FLIP_LOCK_PIN1 1:1 +#define NVC97D_SET_CONTROL_FLIP_LOCK_PIN1_DISABLE (0x00000000) +#define NVC97D_SET_CONTROL_FLIP_LOCK_PIN1_ENABLE (0x00000001) +#define NVC97D_SET_CONTROL_FLIP_LOCK_PIN2 2:2 +#define NVC97D_SET_CONTROL_FLIP_LOCK_PIN2_DISABLE (0x00000000) +#define NVC97D_SET_CONTROL_FLIP_LOCK_PIN2_ENABLE (0x00000001) +#define NVC97D_SET_CONTROL_FLIP_LOCK_PIN3 3:3 +#define NVC97D_SET_CONTROL_FLIP_LOCK_PIN3_DISABLE (0x00000000) +#define NVC97D_SET_CONTROL_FLIP_LOCK_PIN3_ENABLE (0x00000001) +#define NVC97D_SET_INTERLOCK_FLAGS (0x00000218) +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+0):((i)+0) +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC97D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS (0x0000021C) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC97D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVC97D_GET_RG_SCAN_LINE(b) (0x00000220 + (b)*0x00000004) +#define NVC97D_GET_RG_SCAN_LINE_LINE 15:0 +#define NVC97D_GET_RG_SCAN_LINE_VBLANK 16:16 +#define NVC97D_GET_RG_SCAN_LINE_VBLANK_FALSE (0x00000000) +#define NVC97D_GET_RG_SCAN_LINE_VBLANK_TRUE (0x00000001) +#define NVC97D_SET_GET_BLANKING_CTRL(b) (0x00000240 + (b)*0x00000004) +#define NVC97D_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NVC97D_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NVC97D_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NVC97D_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NVC97D_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NVC97D_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) +#define NVC97D_SET_SURFACE_ADDRESS_HI_NOTIFIER (0x00000260) +#define NVC97D_SET_SURFACE_ADDRESS_HI_NOTIFIER_ADDRESS_HI 31:0 +#define NVC97D_SET_SURFACE_ADDRESS_LO_NOTIFIER (0x00000264) +#define NVC97D_SET_SURFACE_ADDRESS_LO_NOTIFIER_ADDRESS_LO 31:4 +#define NVC97D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET 3:2 +#define NVC97D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_IOVA (0x00000000) +#define NVC97D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_NVM (0x00000001) +#define NVC97D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI (0x00000002) +#define NVC97D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVC97D_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE 0:0 +#define NVC97D_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_DISABLE (0x00000000) +#define NVC97D_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_ENABLE (0x00000001) + +#define NVC97D_SOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NVC97D_SOR_SET_CONTROL_OWNER_MASK 7:0 +#define NVC97D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVC97D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVC97D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVC97D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVC97D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVC97D_SOR_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVC97D_SOR_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVC97D_SOR_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVC97D_SOR_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVC97D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NVC97D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NVC97D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NVC97D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NVC97D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NVC97D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NVC97D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NVC97D_SOR_SET_CONTROL_PROTOCOL_HDMI_FRL (0x0000000C) +#define NVC97D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NVC97D_SOR_SET_CONTROL_DE_SYNC_POLARITY 16:16 +#define NVC97D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC97D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC97D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NVC97D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NVC97D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NVC97D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NVC97D_SOR_SET_CUSTOM_REASON(a) (0x00000304 + (a)*0x00000020) +#define NVC97D_SOR_SET_CUSTOM_REASON_CODE 31:0 +#define NVC97D_SOR_SET_SW_SPARE_A(a) (0x00000308 + (a)*0x00000020) +#define NVC97D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NVC97D_SOR_SET_SW_SPARE_B(a) (0x0000030C + (a)*0x00000020) +#define NVC97D_SOR_SET_SW_SPARE_B_CODE 31:0 + +#define NVC97D_DSI_SET_CONTROL(a) (0x00000500 + (a)*0x00000020) +#define NVC97D_DSI_SET_CONTROL_OWNER_MASK 7:0 +#define NVC97D_DSI_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVC97D_DSI_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVC97D_DSI_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVC97D_DSI_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVC97D_DSI_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVC97D_DSI_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVC97D_DSI_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVC97D_DSI_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVC97D_DSI_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVC97D_DSI_SET_CUSTOM_REASON(a) (0x00000504 + (a)*0x00000020) +#define NVC97D_DSI_SET_CUSTOM_REASON_CODE 31:0 +#define NVC97D_DSI_SET_SW_SPARE_A(a) (0x00000508 + (a)*0x00000020) +#define NVC97D_DSI_SET_SW_SPARE_A_CODE 31:0 +#define NVC97D_DSI_SET_SW_SPARE_B(a) (0x0000050C + (a)*0x00000020) +#define NVC97D_DSI_SET_SW_SPARE_B_CODE 31:0 + +#define NVC97D_WINDOW_SET_CONTROL(a) (0x00001000 + (a)*0x00000080) +#define NVC97D_WINDOW_SET_CONTROL_OWNER 3:0 +#define NVC97D_WINDOW_SET_CONTROL_OWNER_HEAD(i) (0x00000000 +(i)) +#define NVC97D_WINDOW_SET_CONTROL_OWNER_HEAD__SIZE_1 8 +#define NVC97D_WINDOW_SET_CONTROL_OWNER_HEAD0 (0x00000000) +#define NVC97D_WINDOW_SET_CONTROL_OWNER_HEAD1 (0x00000001) +#define NVC97D_WINDOW_SET_CONTROL_OWNER_HEAD2 (0x00000002) +#define NVC97D_WINDOW_SET_CONTROL_OWNER_HEAD3 (0x00000003) +#define NVC97D_WINDOW_SET_CONTROL_OWNER_HEAD4 (0x00000004) +#define NVC97D_WINDOW_SET_CONTROL_OWNER_HEAD5 (0x00000005) +#define NVC97D_WINDOW_SET_CONTROL_OWNER_HEAD6 (0x00000006) +#define NVC97D_WINDOW_SET_CONTROL_OWNER_HEAD7 (0x00000007) +#define NVC97D_WINDOW_SET_CONTROL_OWNER_NONE (0x0000000F) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0x00000080) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a) (0x00001008 + (a)*0x00000080) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR(a) (0x0000100C + (a)*0x00000080) +#define NVC97D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVC97D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVC97D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a) (0x00001010 + (a)*0x00000080) +#define NVC97D_WINDOW_SET_WINDOW_USAGE_BOUNDS_MAX_PIXELS_FETCHED_PER_LINE 14:0 +#define NVC97D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED 16:16 +#define NVC97D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED 28:28 +#define NVC97D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS 22:20 +#define NVC97D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVC97D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED 24:24 +#define NVC97D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVC97D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED 30:30 +#define NVC97D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED_FALSE (0x00000000) +#define NVC97D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED_TRUE (0x00000001) + +#define NVC97D_HEAD_SET_PROCAMP(a) (0x00002000 + (a)*0x00000800) +#define NVC97D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NVC97D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NVC97D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NVC97D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NVC97D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003) +#define NVC97D_HEAD_SET_PROCAMP_CHROMA_LPF 3:3 +#define NVC97D_HEAD_SET_PROCAMP_CHROMA_LPF_DISABLE (0x00000000) +#define NVC97D_HEAD_SET_PROCAMP_CHROMA_LPF_ENABLE (0x00000001) +#define NVC97D_HEAD_SET_PROCAMP_CHROMA_DOWN_V 4:4 +#define NVC97D_HEAD_SET_PROCAMP_CHROMA_DOWN_V_DISABLE (0x00000000) +#define NVC97D_HEAD_SET_PROCAMP_CHROMA_DOWN_V_ENABLE (0x00000001) +#define NVC97D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 28:28 +#define NVC97D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NVC97D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00002004 + (a)*0x00000800) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 2:2 +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 3:3 +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 7:4 +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000000) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000001) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000002) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000003) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000004) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000005) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000006) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000007) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000008) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_444 (0x00000009) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444NP (0x0000000A) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 24:24 +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 23:12 +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN 31:26 +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN0 (0x00000000) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN1 (0x00000001) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN2 (0x00000002) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN3 (0x00000003) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN4 (0x00000004) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN5 (0x00000005) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN6 (0x00000006) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN7 (0x00000007) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN8 (0x00000008) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN9 (0x00000009) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN10 (0x0000000A) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN11 (0x0000000B) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN12 (0x0000000C) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN13 (0x0000000D) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN14 (0x0000000E) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN15 (0x0000000F) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN16 (0x00000010) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN17 (0x00000011) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN18 (0x00000012) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN19 (0x00000013) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN20 (0x00000014) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN21 (0x00000015) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN22 (0x00000016) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN23 (0x00000017) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN24 (0x00000018) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN25 (0x00000019) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN26 (0x0000001A) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN27 (0x0000001B) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN28 (0x0000001C) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN29 (0x0000001D) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN30 (0x0000001E) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN31 (0x0000001F) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_NONE (0x0000003F) +#define NVC97D_HEAD_SET_CONTROL(a) (0x00002008 + (a)*0x00000800) +#define NVC97D_HEAD_SET_CONTROL_STRUCTURE 1:0 +#define NVC97D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NVC97D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE 2:2 +#define NVC97D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_NORMAL (0x00000000) +#define NVC97D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000001) +#define NVC97D_HEAD_SET_CONTROL_YUV420PACKER 3:3 +#define NVC97D_HEAD_SET_CONTROL_YUV420PACKER_DISABLE (0x00000000) +#define NVC97D_HEAD_SET_CONTROL_YUV420PACKER_ENABLE (0x00000001) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 11:10 +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 8:4 +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 15:12 +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 23:22 +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 20:16 +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC97D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN 28:24 +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000001) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000002) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000003) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000004) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000005) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000006) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000007) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000008) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000009) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000B) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000C) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000D) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000E) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000F) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x00000010) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC97D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NVC97D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVC97D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVC97D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NVC97D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVC97D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVC97D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x0000200C + (a)*0x00000800) +#define NVC97D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NVC97D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NVC97D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC97D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00002014 + (a)*0x00000800) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVC97D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVC97D_HEAD_SET_DITHER_CONTROL(a) (0x00002018 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NVC97D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC97D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC97D_HEAD_SET_DITHER_CONTROL_BITS 5:4 +#define NVC97D_HEAD_SET_DITHER_CONTROL_BITS_TO_6_BITS (0x00000000) +#define NVC97D_HEAD_SET_DITHER_CONTROL_BITS_TO_8_BITS (0x00000001) +#define NVC97D_HEAD_SET_DITHER_CONTROL_BITS_TO_10_BITS (0x00000002) +#define NVC97D_HEAD_SET_DITHER_CONTROL_BITS_TO_12_BITS (0x00000003) +#define NVC97D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE 2:2 +#define NVC97D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_DISABLE (0x00000000) +#define NVC97D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_ENABLE (0x00000001) +#define NVC97D_HEAD_SET_DITHER_CONTROL_MODE 10:8 +#define NVC97D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NVC97D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NVC97D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NVC97D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NVC97D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NVC97D_HEAD_SET_DITHER_CONTROL_MODE_ROUND (0x00000005) +#define NVC97D_HEAD_SET_DITHER_CONTROL_PHASE 13:12 +#define NVC97D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x0000201C + (a)*0x00000800) +#define NVC97D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 0:0 +#define NVC97D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NVC97D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NVC97D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING 4:4 +#define NVC97D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_DISABLE (0x00000000) +#define NVC97D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_ENABLE (0x00000001) +#define NVC97D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 9:8 +#define NVC97D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NVC97D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NVC97D_HEAD_SET_DISPLAY_ID(a,b) (0x00002020 + (a)*0x00000800 + (b)*0x00000004) +#define NVC97D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NVC97D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00002028 + (a)*0x00000800) +#define NVC97D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NVC97D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NVC97D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC97D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC97D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR(a) (0x0000202C + (a)*0x00000800) +#define NVC97D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVC97D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVC97D_HEAD_SET_HEAD_USAGE_BOUNDS(a) (0x00002030 + (a)*0x00000800) +#define NVC97D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR 2:0 +#define NVC97D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_NONE (0x00000000) +#define NVC97D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W32_H32 (0x00000001) +#define NVC97D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W64_H64 (0x00000002) +#define NVC97D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W128_H128 (0x00000003) +#define NVC97D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W256_H256 (0x00000004) +#define NVC97D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED 4:4 +#define NVC97D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_FALSE (0x00000000) +#define NVC97D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_TRUE (0x00000001) +#define NVC97D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS 14:12 +#define NVC97D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVC97D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVC97D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED 8:8 +#define NVC97D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC97D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVC97D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED 16:16 +#define NVC97D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED_FALSE (0x00000000) +#define NVC97D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED_TRUE (0x00000001) +#define NVC97D_HEAD_SET_STALL_LOCK(a) (0x00002034 + (a)*0x00000800) +#define NVC97D_HEAD_SET_STALL_LOCK_ENABLE 0:0 +#define NVC97D_HEAD_SET_STALL_LOCK_ENABLE_FALSE (0x00000000) +#define NVC97D_HEAD_SET_STALL_LOCK_ENABLE_TRUE (0x00000001) +#define NVC97D_HEAD_SET_STALL_LOCK_MODE 2:2 +#define NVC97D_HEAD_SET_STALL_LOCK_MODE_CONTINUOUS (0x00000000) +#define NVC97D_HEAD_SET_STALL_LOCK_MODE_ONE_SHOT (0x00000001) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN 8:4 +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC97D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC97D_HEAD_SET_STALL_LOCK_UNSTALL_MODE 12:12 +#define NVC97D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_CRASH_LOCK (0x00000000) +#define NVC97D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_LINE_LOCK (0x00000001) +#define NVC97D_HEAD_SET_STALL_LOCK_TEPOLARITY 14:14 +#define NVC97D_HEAD_SET_STALL_LOCK_TEPOLARITY_POSITIVE_TRUE (0x00000000) +#define NVC97D_HEAD_SET_STALL_LOCK_TEPOLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC97D_HEAD_SET_STALL_LOCK_UNSTALL_SYNC_ADVANCE 25:16 +#define NVC97D_HEAD_SET_LOCK_CHAIN(a) (0x00002044 + (a)*0x00000800) +#define NVC97D_HEAD_SET_LOCK_CHAIN_POSITION 3:0 +#define NVC97D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x00002048 + (a)*0x00000800) +#define NVC97D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NVC97D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NVC97D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x0000204C + (a)*0x00000800) +#define NVC97D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NVC97D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NVC97D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x00002058 + (a)*0x00000800) +#define NVC97D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NVC97D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NVC97D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x0000205C + (a)*0x00000800) +#define NVC97D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NVC97D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NVC97D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000800) +#define NVC97D_HEAD_SET_RASTER_SIZE_WIDTH 15:0 +#define NVC97D_HEAD_SET_RASTER_SIZE_HEIGHT 31:16 +#define NVC97D_HEAD_SET_RASTER_SYNC_END(a) (0x00002068 + (a)*0x00000800) +#define NVC97D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NVC97D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NVC97D_HEAD_SET_RASTER_BLANK_END(a) (0x0000206C + (a)*0x00000800) +#define NVC97D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NVC97D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NVC97D_HEAD_SET_RASTER_BLANK_START(a) (0x00002070 + (a)*0x00000800) +#define NVC97D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NVC97D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NVC97D_HEAD_SET_OVERSCAN_COLOR(a) (0x00002078 + (a)*0x00000800) +#define NVC97D_HEAD_SET_OVERSCAN_COLOR_RED_CR 9:0 +#define NVC97D_HEAD_SET_OVERSCAN_COLOR_GREEN_Y 19:10 +#define NVC97D_HEAD_SET_OVERSCAN_COLOR_BLUE_CB 29:20 +#define NVC97D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR(a) (0x0000207C + (a)*0x00000800) +#define NVC97D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_RED_CR 9:0 +#define NVC97D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_GREEN_Y 19:10 +#define NVC97D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_BLUE_CB 29:20 +#define NVC97D_HEAD_SET_HDMI_CTRL(a) (0x00002080 + (a)*0x00000800) +#define NVC97D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NVC97D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NVC97D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NVC97D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NVC97D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NVC97D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x00002098 + (a)*0x00000800) +#define NVC97D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 0:0 +#define NVC97D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NVC97D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NVC97D_HEAD_SET_CONTROL_CURSOR(a) (0x0000209C + (a)*0x00000800) +#define NVC97D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NVC97D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NVC97D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NVC97D_HEAD_SET_CONTROL_CURSOR_FORMAT 7:0 +#define NVC97D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC97D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC97D_HEAD_SET_CONTROL_CURSOR_SIZE 9:8 +#define NVC97D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NVC97D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NVC97D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NVC97D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NVC97D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 19:12 +#define NVC97D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 27:20 +#define NVC97D_HEAD_SET_CONTROL_CURSOR_COMPOSITION(a) (0x000020A0 + (a)*0x00000800) +#define NVC97D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_K1 7:0 +#define NVC97D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT 11:8 +#define NVC97D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC97D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC97D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT 15:12 +#define NVC97D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_ZERO (0x00000000) +#define NVC97D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC97D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC97D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE 16:16 +#define NVC97D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_BLEND (0x00000000) +#define NVC97D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_XOR (0x00000001) +#define NVC97D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS 20:20 +#define NVC97D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_DISABLE (0x00000000) +#define NVC97D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_ENABLE (0x00000001) +#define NVC97D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI(a) (0x000020C0 + (a)*0x00000800) +#define NVC97D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_HERTZ 3:0 +#define NVC97D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_MAX(a) (0x000020C4 + (a)*0x00000800) +#define NVC97D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_MAX_HERTZ 3:0 +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_HI_RG_REL_SEMAPHORE(a,b) (0x00002110 + (a)*0x00000800 + (b)*0x00000004) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_HI_RG_REL_SEMAPHORE_ADDRESS_HI 31:0 +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE(a,b) (0x00002130 + (a)*0x00000800 + (b)*0x00000004) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_ADDRESS_LO 31:4 +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_TARGET 3:2 +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_TARGET_IOVA (0x00000000) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_TARGET_PHYSICAL_NVM (0x00000001) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_TARGET_PHYSICAL_PCI (0x00000002) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_ENABLE 0:0 +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_ENABLE_DISABLE (0x00000000) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_ENABLE_ENABLE (0x00000001) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_HI_CRC(a) (0x00002150 + (a)*0x00000800) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_HI_CRC_ADDRESS_HI 31:0 +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_CRC(a) (0x00002154 + (a)*0x00000800) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_ADDRESS_LO 31:4 +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET 3:2 +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET_IOVA (0x00000000) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET_PHYSICAL_NVM (0x00000001) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET_PHYSICAL_PCI (0x00000002) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_ENABLE 0:0 +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_ENABLE_DISABLE (0x00000000) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_ENABLE_ENABLE (0x00000001) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_HI_OLUT(a) (0x00002158 + (a)*0x00000800) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_HI_OLUT_ADDRESS_HI 31:0 +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT(a) (0x0000215C + (a)*0x00000800) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_ADDRESS_LO 31:4 +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET 3:2 +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET_IOVA (0x00000000) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET_PHYSICAL_NVM (0x00000001) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET_PHYSICAL_PCI (0x00000002) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_ENABLE 0:0 +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_ENABLE_DISABLE (0x00000000) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_ENABLE_ENABLE (0x00000001) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_HI_CURSOR(a,b) (0x00002170 + (a)*0x00000800 + (b)*0x00000004) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_HI_CURSOR_ADDRESS_HI 31:0 +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR(a,b) (0x00002178 + (a)*0x00000800 + (b)*0x00000004) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_ADDRESS_LO 31:4 +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET 3:2 +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET_IOVA (0x00000000) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET_PHYSICAL_NVM (0x00000001) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET_PHYSICAL_PCI (0x00000002) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_KIND 1:1 +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_KIND_PITCH (0x00000000) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_KIND_BLOCKLINEAR (0x00000001) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_ENABLE 0:0 +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_ENABLE_DISABLE (0x00000000) +#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_ENABLE_ENABLE (0x00000001) +#define NVC97D_HEAD_SET_CRC_CONTROL(a) (0x00002184 + (a)*0x00000800) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 5:0 +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_0 (0x00000000) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_1 (0x00000001) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_2 (0x00000002) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_3 (0x00000003) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_4 (0x00000004) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_5 (0x00000005) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_6 (0x00000006) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_7 (0x00000007) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_8 (0x00000008) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_9 (0x00000009) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_10 (0x0000000A) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_11 (0x0000000B) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_12 (0x0000000C) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_13 (0x0000000D) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_14 (0x0000000E) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_15 (0x0000000F) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_16 (0x00000010) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_17 (0x00000011) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_18 (0x00000012) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_19 (0x00000013) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_20 (0x00000014) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_21 (0x00000015) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_22 (0x00000016) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_23 (0x00000017) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_24 (0x00000018) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_25 (0x00000019) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_26 (0x0000001A) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_27 (0x0000001B) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_28 (0x0000001C) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_29 (0x0000001D) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_30 (0x0000001E) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_31 (0x0000001F) +#define NVC97D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000020) +#define NVC97D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 8:8 +#define NVC97D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NVC97D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NVC97D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC 19:12 +#define NVC97D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_NONE (0x00000000) +#define NVC97D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SF (0x00000030) +#define NVC97D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC97D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR__SIZE_1 8 +#define NVC97D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR0 (0x00000050) +#define NVC97D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR1 (0x00000051) +#define NVC97D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR2 (0x00000052) +#define NVC97D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR3 (0x00000053) +#define NVC97D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR4 (0x00000054) +#define NVC97D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR5 (0x00000055) +#define NVC97D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR6 (0x00000056) +#define NVC97D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR7 (0x00000057) +#define NVC97D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC 27:20 +#define NVC97D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_NONE (0x00000000) +#define NVC97D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SF (0x00000030) +#define NVC97D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC97D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR__SIZE_1 8 +#define NVC97D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR0 (0x00000050) +#define NVC97D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR1 (0x00000051) +#define NVC97D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR2 (0x00000052) +#define NVC97D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR3 (0x00000053) +#define NVC97D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR4 (0x00000054) +#define NVC97D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR5 (0x00000055) +#define NVC97D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR6 (0x00000056) +#define NVC97D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR7 (0x00000057) +#define NVC97D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 9:9 +#define NVC97D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NVC97D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NVC97D_HEAD_SET_PRESENT_CONTROL(a) (0x0000218C + (a)*0x00000800) +#define NVC97D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 0:0 +#define NVC97D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NVC97D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NVC97D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NVC97D_HEAD_SET_SW_SPARE_A(a) (0x00002194 + (a)*0x00000800) +#define NVC97D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NVC97D_HEAD_SET_SW_SPARE_B(a) (0x00002198 + (a)*0x00000800) +#define NVC97D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NVC97D_HEAD_SET_SW_SPARE_C(a) (0x0000219C + (a)*0x00000800) +#define NVC97D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NVC97D_HEAD_SET_SW_SPARE_D(a) (0x000021A0 + (a)*0x00000800) +#define NVC97D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NVC97D_HEAD_SET_DISPLAY_RATE(a) (0x000021A8 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DISPLAY_RATE_RUN_MODE 1:0 +#define NVC97D_HEAD_SET_DISPLAY_RATE_RUN_MODE_CONTINUOUS (0x00000000) +#define NVC97D_HEAD_SET_DISPLAY_RATE_RUN_MODE_ONE_SHOT (0x00000001) +#define NVC97D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_INTERVAL 25:4 +#define NVC97D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH 2:2 +#define NVC97D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_DISABLE (0x00000000) +#define NVC97D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_ENABLE (0x00000001) +#define NVC97D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL(a,b) (0x000021CC + (a)*0x00000800 + (b)*0x00000004) +#define NVC97D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVC97D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVC97D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVC97D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE 14:14 +#define NVC97D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE_WRITE (0x00000000) +#define NVC97D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC97D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE 10:10 +#define NVC97D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE_ONE_TIME (0x00000000) +#define NVC97D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE_CONTINUOUS (0x00000001) +#define NVC97D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RASTER_LINE 31:16 +#define NVC97D_HEAD_SET_RG_REL_SEMAPHORE_VALUE(a,b) (0x000021EC + (a)*0x00000800 + (b)*0x00000004) +#define NVC97D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_VALUE 31:0 +#define NVC97D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE(a) (0x00002214 + (a)*0x00000800) +#define NVC97D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVC97D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVC97D_HEAD_SET_MIN_FRAME_IDLE(a) (0x00002218 + (a)*0x00000800) +#define NVC97D_HEAD_SET_MIN_FRAME_IDLE_LEADING_RASTER_LINES 14:0 +#define NVC97D_HEAD_SET_MIN_FRAME_IDLE_TRAILING_RASTER_LINES 30:16 +#define NVC97D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED(a) (0x00002220 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED_ALPHA 7:0 +#define NVC97D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED_RED 31:16 +#define NVC97D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE(a) (0x00002224 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE_GREEN 15:0 +#define NVC97D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE_BLUE 31:16 +#define NVC97D_HEAD_SET_CURSOR_COLOR_NORM_SCALE(a) (0x00002228 + (a)*0x00000800) +#define NVC97D_HEAD_SET_CURSOR_COLOR_NORM_SCALE_VALUE 15:0 +#define NVC97D_HEAD_SET_XOR_BLEND_FACTOR(a) (0x0000222C + (a)*0x00000800) +#define NVC97D_HEAD_SET_XOR_BLEND_FACTOR_LOG2PEAK_LUMINANCE 3:0 +#define NVC97D_HEAD_SET_XOR_BLEND_FACTOR_S1 16:4 +#define NVC97D_HEAD_SET_XOR_BLEND_FACTOR_S2 30:18 +#define NVC97D_HEAD_SET_CLAMP_RANGE_GREEN(a) (0x00002238 + (a)*0x00000800) +#define NVC97D_HEAD_SET_CLAMP_RANGE_GREEN_LOW 11:0 +#define NVC97D_HEAD_SET_CLAMP_RANGE_GREEN_HIGH 27:16 +#define NVC97D_HEAD_SET_CLAMP_RANGE_RED_BLUE(a) (0x0000223C + (a)*0x00000800) +#define NVC97D_HEAD_SET_CLAMP_RANGE_RED_BLUE_LOW 11:0 +#define NVC97D_HEAD_SET_CLAMP_RANGE_RED_BLUE_HIGH 27:16 +#define NVC97D_HEAD_SET_OCSC0CONTROL(a) (0x00002240 + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC0CONTROL_ENABLE 0:0 +#define NVC97D_HEAD_SET_OCSC0CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC97D_HEAD_SET_OCSC0CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC97D_HEAD_SET_OCSC0COEFFICIENT_C00(a) (0x00002244 + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC0COEFFICIENT_C00_VALUE 20:0 +#define NVC97D_HEAD_SET_OCSC0COEFFICIENT_C01(a) (0x00002248 + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC0COEFFICIENT_C01_VALUE 20:0 +#define NVC97D_HEAD_SET_OCSC0COEFFICIENT_C02(a) (0x0000224C + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC0COEFFICIENT_C02_VALUE 20:0 +#define NVC97D_HEAD_SET_OCSC0COEFFICIENT_C03(a) (0x00002250 + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC0COEFFICIENT_C03_VALUE 20:0 +#define NVC97D_HEAD_SET_OCSC0COEFFICIENT_C10(a) (0x00002254 + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC0COEFFICIENT_C10_VALUE 20:0 +#define NVC97D_HEAD_SET_OCSC0COEFFICIENT_C11(a) (0x00002258 + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC0COEFFICIENT_C11_VALUE 20:0 +#define NVC97D_HEAD_SET_OCSC0COEFFICIENT_C12(a) (0x0000225C + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC0COEFFICIENT_C12_VALUE 20:0 +#define NVC97D_HEAD_SET_OCSC0COEFFICIENT_C13(a) (0x00002260 + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC0COEFFICIENT_C13_VALUE 20:0 +#define NVC97D_HEAD_SET_OCSC0COEFFICIENT_C20(a) (0x00002264 + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC0COEFFICIENT_C20_VALUE 20:0 +#define NVC97D_HEAD_SET_OCSC0COEFFICIENT_C21(a) (0x00002268 + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC0COEFFICIENT_C21_VALUE 20:0 +#define NVC97D_HEAD_SET_OCSC0COEFFICIENT_C22(a) (0x0000226C + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC0COEFFICIENT_C22_VALUE 20:0 +#define NVC97D_HEAD_SET_OCSC0COEFFICIENT_C23(a) (0x00002270 + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC0COEFFICIENT_C23_VALUE 20:0 +#define NVC97D_HEAD_SET_OLUT_CONTROL(a) (0x00002280 + (a)*0x00000800) +#define NVC97D_HEAD_SET_OLUT_CONTROL_INTERPOLATE 0:0 +#define NVC97D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC97D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC97D_HEAD_SET_OLUT_CONTROL_MIRROR 1:1 +#define NVC97D_HEAD_SET_OLUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC97D_HEAD_SET_OLUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC97D_HEAD_SET_OLUT_CONTROL_MODE 3:2 +#define NVC97D_HEAD_SET_OLUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVC97D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVC97D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVC97D_HEAD_SET_OLUT_CONTROL_SIZE 18:8 +#define NVC97D_HEAD_SET_OLUT_FP_NORM_SCALE(a) (0x00002284 + (a)*0x00000800) +#define NVC97D_HEAD_SET_OLUT_FP_NORM_SCALE_VALUE 31:0 +#define NVC97D_HEAD_SET_OCSC1CONTROL(a) (0x0000229C + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC1CONTROL_ENABLE 0:0 +#define NVC97D_HEAD_SET_OCSC1CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC97D_HEAD_SET_OCSC1CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC97D_HEAD_SET_OCSC1COEFFICIENT_C00(a) (0x000022A0 + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC1COEFFICIENT_C00_VALUE 20:0 +#define NVC97D_HEAD_SET_OCSC1COEFFICIENT_C01(a) (0x000022A4 + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC1COEFFICIENT_C01_VALUE 20:0 +#define NVC97D_HEAD_SET_OCSC1COEFFICIENT_C02(a) (0x000022A8 + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC1COEFFICIENT_C02_VALUE 20:0 +#define NVC97D_HEAD_SET_OCSC1COEFFICIENT_C03(a) (0x000022AC + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC1COEFFICIENT_C03_VALUE 20:0 +#define NVC97D_HEAD_SET_OCSC1COEFFICIENT_C10(a) (0x000022B0 + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC1COEFFICIENT_C10_VALUE 20:0 +#define NVC97D_HEAD_SET_OCSC1COEFFICIENT_C11(a) (0x000022B4 + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC1COEFFICIENT_C11_VALUE 20:0 +#define NVC97D_HEAD_SET_OCSC1COEFFICIENT_C12(a) (0x000022B8 + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC1COEFFICIENT_C12_VALUE 20:0 +#define NVC97D_HEAD_SET_OCSC1COEFFICIENT_C13(a) (0x000022BC + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC1COEFFICIENT_C13_VALUE 20:0 +#define NVC97D_HEAD_SET_OCSC1COEFFICIENT_C20(a) (0x000022C0 + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC1COEFFICIENT_C20_VALUE 20:0 +#define NVC97D_HEAD_SET_OCSC1COEFFICIENT_C21(a) (0x000022C4 + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC1COEFFICIENT_C21_VALUE 20:0 +#define NVC97D_HEAD_SET_OCSC1COEFFICIENT_C22(a) (0x000022C8 + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC1COEFFICIENT_C22_VALUE 20:0 +#define NVC97D_HEAD_SET_OCSC1COEFFICIENT_C23(a) (0x000022CC + (a)*0x00000800) +#define NVC97D_HEAD_SET_OCSC1COEFFICIENT_C23_VALUE 20:0 +#define NVC97D_HEAD_SET_HEAD_POSITION(a) (0x000022D0 + (a)*0x00000800) +#define NVC97D_HEAD_SET_HEAD_POSITION_X 2:0 +#define NVC97D_HEAD_SET_HEAD_POSITION_Y 6:4 +#define NVC97D_HEAD_SET_DSC_CONTROL(a) (0x000022D4 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_CONTROL_ENABLE 0:0 +#define NVC97D_HEAD_SET_DSC_CONTROL_ENABLE_FALSE (0x00000000) +#define NVC97D_HEAD_SET_DSC_CONTROL_ENABLE_TRUE (0x00000001) +#define NVC97D_HEAD_SET_DSC_CONTROL_AUTO_RESET 3:3 +#define NVC97D_HEAD_SET_DSC_CONTROL_AUTO_RESET_DISABLE (0x00000000) +#define NVC97D_HEAD_SET_DSC_CONTROL_AUTO_RESET_ENABLE (0x00000001) +#define NVC97D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION 4:4 +#define NVC97D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION_DISABLE (0x00000000) +#define NVC97D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION_ENABLE (0x00000001) +#define NVC97D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET 5:5 +#define NVC97D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET_FALSE (0x00000000) +#define NVC97D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET_TRUE (0x00000001) +#define NVC97D_HEAD_SET_DSC_CONTROL_FLATNESS_DET_THRESH 15:6 +#define NVC97D_HEAD_SET_DSC_PPS_CONTROL(a) (0x000022D8 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_CONTROL_ENABLE 0:0 +#define NVC97D_HEAD_SET_DSC_PPS_CONTROL_ENABLE_FALSE (0x00000000) +#define NVC97D_HEAD_SET_DSC_PPS_CONTROL_ENABLE_TRUE (0x00000001) +#define NVC97D_HEAD_SET_DSC_PPS_CONTROL_LOCATION 2:1 +#define NVC97D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_VBLANK (0x00000000) +#define NVC97D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_VSYNC (0x00000001) +#define NVC97D_HEAD_SET_DSC_PPS_CONTROL_SIZE 10:3 +#define NVC97D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY 11:11 +#define NVC97D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVC97D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY_ONCE (0x00000001) +#define NVC97D_HEAD_SET_DSC_PPS_HEAD(a) (0x000022DC + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_HEAD_BYTE0 7:0 +#define NVC97D_HEAD_SET_DSC_PPS_HEAD_BYTE1 15:8 +#define NVC97D_HEAD_SET_DSC_PPS_HEAD_BYTE2 23:16 +#define NVC97D_HEAD_SET_DSC_PPS_HEAD_BYTE3 31:24 +#define NVC97D_HEAD_SET_DSC_PPS_DATA0(a) (0x000022E0 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA0_DSC_VERSION_MINOR 3:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA0_DSC_VERSION_MAJOR 7:4 +#define NVC97D_HEAD_SET_DSC_PPS_DATA0_PPS_IDENTIFIER 15:8 +#define NVC97D_HEAD_SET_DSC_PPS_DATA0_RESERVED 23:16 +#define NVC97D_HEAD_SET_DSC_PPS_DATA0_LINEBUF_DEPTH 27:24 +#define NVC97D_HEAD_SET_DSC_PPS_DATA0_BITS_PER_COMPONENT 31:28 +#define NVC97D_HEAD_SET_DSC_PPS_DATA1(a) (0x000022E4 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA1_BITS_PER_PIXEL_HIGH 1:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA1_VBR_ENABLE 2:2 +#define NVC97D_HEAD_SET_DSC_PPS_DATA1_SIMPLE422 3:3 +#define NVC97D_HEAD_SET_DSC_PPS_DATA1_CONVERT_RGB 4:4 +#define NVC97D_HEAD_SET_DSC_PPS_DATA1_BLOCK_PRED_ENABLE 5:5 +#define NVC97D_HEAD_SET_DSC_PPS_DATA1_RESERVED 7:6 +#define NVC97D_HEAD_SET_DSC_PPS_DATA1_BITS_PER_PIXEL_LOW 15:8 +#define NVC97D_HEAD_SET_DSC_PPS_DATA1_PIC_HEIGHT_HIGH 23:16 +#define NVC97D_HEAD_SET_DSC_PPS_DATA1_PIC_HEIGHT_LOW 31:24 +#define NVC97D_HEAD_SET_DSC_PPS_DATA2(a) (0x000022E8 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA2_PIC_WIDTH_HIGH 7:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA2_PIC_WIDTH_LOW 15:8 +#define NVC97D_HEAD_SET_DSC_PPS_DATA2_SLICE_HEIGHT_HIGH 23:16 +#define NVC97D_HEAD_SET_DSC_PPS_DATA2_SLICE_HEIGHT_LOW 31:24 +#define NVC97D_HEAD_SET_DSC_PPS_DATA3(a) (0x000022EC + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA3_SLICE_WIDTH_HIGH 7:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA3_SLICE_WIDTH_LOW 15:8 +#define NVC97D_HEAD_SET_DSC_PPS_DATA3_CHUNK_SIZE_HIGH 23:16 +#define NVC97D_HEAD_SET_DSC_PPS_DATA3_CHUNK_SIZE_LOW 31:24 +#define NVC97D_HEAD_SET_DSC_PPS_DATA4(a) (0x000022F0 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA4_INITIAL_XMIT_DELAY_HIGH 1:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA4_RESERVED 7:2 +#define NVC97D_HEAD_SET_DSC_PPS_DATA4_INITIAL_XMIT_DELAY_LOW 15:8 +#define NVC97D_HEAD_SET_DSC_PPS_DATA4_INITIAL_DEC_DELAY_HIGH 23:16 +#define NVC97D_HEAD_SET_DSC_PPS_DATA4_INITIAL_DEC_DELAY_LOW 31:24 +#define NVC97D_HEAD_SET_DSC_PPS_DATA5(a) (0x000022F4 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA5_RESERVED0 7:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA5_INITIAL_SCALE_VALUE 13:8 +#define NVC97D_HEAD_SET_DSC_PPS_DATA5_RESERVED1 15:14 +#define NVC97D_HEAD_SET_DSC_PPS_DATA5_SCALE_INCREMENT_INTERVAL_HIGH 23:16 +#define NVC97D_HEAD_SET_DSC_PPS_DATA5_SCALE_INCREMENT_INTERVAL_LOW 31:24 +#define NVC97D_HEAD_SET_DSC_PPS_DATA6(a) (0x000022F8 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA6_SCALE_DECREMENT_INTERVAL_HIGH 3:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA6_RESERVED0 7:4 +#define NVC97D_HEAD_SET_DSC_PPS_DATA6_SCALE_DECREMENT_INTERVAL_LOW 15:8 +#define NVC97D_HEAD_SET_DSC_PPS_DATA6_RESERVED1 23:16 +#define NVC97D_HEAD_SET_DSC_PPS_DATA6_FIRST_LINE_BPG_OFFSET 28:24 +#define NVC97D_HEAD_SET_DSC_PPS_DATA6_RESERVED2 31:29 +#define NVC97D_HEAD_SET_DSC_PPS_DATA7(a) (0x000022FC + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA7_NFL_BPG_OFFSET_HIGH 7:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA7_NFL_BPG_OFFSET_LOW 15:8 +#define NVC97D_HEAD_SET_DSC_PPS_DATA7_SLICE_BPG_OFFSET_HIGH 23:16 +#define NVC97D_HEAD_SET_DSC_PPS_DATA7_SLICE_BPG_OFFSET_LOW 31:24 +#define NVC97D_HEAD_SET_DSC_PPS_DATA8(a) (0x00002300 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA8_INITIAL_OFFSET_HIGH 7:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA8_INITIAL_OFFSET_LOW 15:8 +#define NVC97D_HEAD_SET_DSC_PPS_DATA8_FINAL_OFFSET_HIGH 23:16 +#define NVC97D_HEAD_SET_DSC_PPS_DATA8_FINAL_OFFSET_LOW 31:24 +#define NVC97D_HEAD_SET_DSC_PPS_DATA9(a) (0x00002304 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA9_FLATNESS_MIN_QP 4:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA9_RESERVED0 7:5 +#define NVC97D_HEAD_SET_DSC_PPS_DATA9_FLATNESS_MAX_QP 12:8 +#define NVC97D_HEAD_SET_DSC_PPS_DATA9_RESERVED1 15:13 +#define NVC97D_HEAD_SET_DSC_PPS_DATA9_RC_MODEL_SIZE_HIGH 23:16 +#define NVC97D_HEAD_SET_DSC_PPS_DATA9_RC_MODEL_SIZE_LOW 31:24 +#define NVC97D_HEAD_SET_DSC_PPS_DATA10(a) (0x00002308 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA10_RC_EDGE_FACTOR 3:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA10_RESERVED0 7:4 +#define NVC97D_HEAD_SET_DSC_PPS_DATA10_RC_QUANT_INCR_LIMIT0 12:8 +#define NVC97D_HEAD_SET_DSC_PPS_DATA10_RESERVED1 15:13 +#define NVC97D_HEAD_SET_DSC_PPS_DATA10_RC_QUANT_INCR_LIMIT1 20:16 +#define NVC97D_HEAD_SET_DSC_PPS_DATA10_RESERVED2 23:21 +#define NVC97D_HEAD_SET_DSC_PPS_DATA10_RC_TGT_OFFSET_LO 27:24 +#define NVC97D_HEAD_SET_DSC_PPS_DATA10_RC_TGT_OFFSET_HI 31:28 +#define NVC97D_HEAD_SET_DSC_PPS_DATA11(a) (0x0000230C + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH0 7:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH1 15:8 +#define NVC97D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH2 23:16 +#define NVC97D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH3 31:24 +#define NVC97D_HEAD_SET_DSC_PPS_DATA12(a) (0x00002310 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH4 7:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH5 15:8 +#define NVC97D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH6 23:16 +#define NVC97D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH7 31:24 +#define NVC97D_HEAD_SET_DSC_PPS_DATA13(a) (0x00002314 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH8 7:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH9 15:8 +#define NVC97D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH10 23:16 +#define NVC97D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH11 31:24 +#define NVC97D_HEAD_SET_DSC_PPS_DATA14(a) (0x00002318 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA14_RC_BUF_THRESH12 7:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA14_RC_BUF_THRESH13 15:8 +#define NVC97D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MAX_QP_HIGH0 18:16 +#define NVC97D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MIN_QP0 23:19 +#define NVC97D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_BPG_OFFSET0 29:24 +#define NVC97D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MAX_QP_LOW0 31:30 +#define NVC97D_HEAD_SET_DSC_PPS_DATA15(a) (0x0000231C + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_HIGH1 2:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MIN_QP1 7:3 +#define NVC97D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_BPG_OFFSET1 13:8 +#define NVC97D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_LOW1 15:14 +#define NVC97D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_HIGH2 18:16 +#define NVC97D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MIN_QP2 23:19 +#define NVC97D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_BPG_OFFSET2 29:24 +#define NVC97D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_LOW2 31:30 +#define NVC97D_HEAD_SET_DSC_PPS_DATA16(a) (0x00002320 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_HIGH3 2:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MIN_QP3 7:3 +#define NVC97D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_BPG_OFFSET3 13:8 +#define NVC97D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_LOW3 15:14 +#define NVC97D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_HIGH4 18:16 +#define NVC97D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MIN_QP4 23:19 +#define NVC97D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_BPG_OFFSET4 29:24 +#define NVC97D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_LOW4 31:30 +#define NVC97D_HEAD_SET_DSC_PPS_DATA17(a) (0x00002324 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_HIGH5 2:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MIN_QP5 7:3 +#define NVC97D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_BPG_OFFSET5 13:8 +#define NVC97D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_LOW5 15:14 +#define NVC97D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_HIGH6 18:16 +#define NVC97D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MIN_QP6 23:19 +#define NVC97D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_BPG_OFFSET6 29:24 +#define NVC97D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_LOW6 31:30 +#define NVC97D_HEAD_SET_DSC_PPS_DATA18(a) (0x00002328 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_HIGH7 2:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MIN_QP7 7:3 +#define NVC97D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_BPG_OFFSET7 13:8 +#define NVC97D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_LOW7 15:14 +#define NVC97D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_HIGH8 18:16 +#define NVC97D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MIN_QP8 23:19 +#define NVC97D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_BPG_OFFSET8 29:24 +#define NVC97D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_LOW8 31:30 +#define NVC97D_HEAD_SET_DSC_PPS_DATA19(a) (0x0000232C + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_HIGH9 2:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MIN_QP9 7:3 +#define NVC97D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_BPG_OFFSET9 13:8 +#define NVC97D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_LOW9 15:14 +#define NVC97D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_HIGH10 18:16 +#define NVC97D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MIN_QP10 23:19 +#define NVC97D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_BPG_OFFSET10 29:24 +#define NVC97D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_LOW10 31:30 +#define NVC97D_HEAD_SET_DSC_PPS_DATA20(a) (0x00002330 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_HIGH11 2:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MIN_QP11 7:3 +#define NVC97D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_BPG_OFFSET11 13:8 +#define NVC97D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_LOW11 15:14 +#define NVC97D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_HIGH12 18:16 +#define NVC97D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MIN_QP12 23:19 +#define NVC97D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_BPG_OFFSET12 29:24 +#define NVC97D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_LOW12 31:30 +#define NVC97D_HEAD_SET_DSC_PPS_DATA21(a) (0x00002334 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_HIGH13 2:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MIN_QP13 7:3 +#define NVC97D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_BPG_OFFSET13 13:8 +#define NVC97D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_LOW13 15:14 +#define NVC97D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_HIGH14 18:16 +#define NVC97D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MIN_QP14 23:19 +#define NVC97D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_BPG_OFFSET14 29:24 +#define NVC97D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_LOW14 31:30 +#define NVC97D_HEAD_SET_DSC_PPS_DATA22(a) (0x00002338 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA22_NATIVE422 0:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA22_NATIVE420 1:1 +#define NVC97D_HEAD_SET_DSC_PPS_DATA22_RESERVED0 7:2 +#define NVC97D_HEAD_SET_DSC_PPS_DATA22_SECOND_LINE_BPG_OFFSET 12:8 +#define NVC97D_HEAD_SET_DSC_PPS_DATA22_RESERVED1 15:13 +#define NVC97D_HEAD_SET_DSC_PPS_DATA22_NSL_BPG_OFFSET_HIGH 23:16 +#define NVC97D_HEAD_SET_DSC_PPS_DATA22_NSL_BPG_OFFSETLOW 31:24 +#define NVC97D_HEAD_SET_DSC_PPS_DATA23(a) (0x0000233C + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA23_SECOND_LINE_OFFSET_ADJ_HIGH 7:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA23_SECOND_LINE_OFFSET_ADJ_LOW 15:8 +#define NVC97D_HEAD_SET_DSC_PPS_DATA23_RESERVED 31:16 +#define NVC97D_HEAD_SET_DSC_PPS_DATA24(a) (0x00002340 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA24_RESERVED 31:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA25(a) (0x00002344 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA25_RESERVED 31:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA26(a) (0x00002348 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA26_RESERVED 31:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA27(a) (0x0000234C + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA27_RESERVED 31:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA28(a) (0x00002350 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA28_RESERVED 31:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA29(a) (0x00002354 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA29_RESERVED 31:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA30(a) (0x00002358 + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA30_RESERVED 31:0 +#define NVC97D_HEAD_SET_DSC_PPS_DATA31(a) (0x0000235C + (a)*0x00000800) +#define NVC97D_HEAD_SET_DSC_PPS_DATA31_RESERVED 31:0 +#define NVC97D_HEAD_SET_RASTER_HBLANK_DELAY(a) (0x00002364 + (a)*0x00000800) +#define NVC97D_HEAD_SET_RASTER_HBLANK_DELAY_BLANK_START 15:0 +#define NVC97D_HEAD_SET_RASTER_HBLANK_DELAY_BLANK_END 31:16 +#define NVC97D_HEAD_SET_HDMI_DSC_HCACTIVE(a) (0x00002368 + (a)*0x00000800) +#define NVC97D_HEAD_SET_HDMI_DSC_HCACTIVE_BYTES 15:0 +#define NVC97D_HEAD_SET_HDMI_DSC_HCACTIVE_TRI_BYTES 31:16 +#define NVC97D_HEAD_SET_HDMI_DSC_HCBLANK(a) (0x0000236C + (a)*0x00000800) +#define NVC97D_HEAD_SET_HDMI_DSC_HCBLANK_WIDTH 15:0 +#define NVC97D_HEAD_SW_RESERVED(a,b) (0x00002370 + (a)*0x00000800 + (b)*0x00000004) +#define NVC97D_HEAD_SW_RESERVED_VALUE 31:0 +#define NVC97D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_HI(a,b) (0x00002380 + (a)*0x00000800 + (b)*0x00000004) +#define NVC97D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_HI_VALUE 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc97d_h diff --git a/userspace/sdks/nv570/inc/class/clc97dswspare.h b/userspace/sdks/nv570/inc/class/clc97dswspare.h new file mode 100644 index 0000000..918da10 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc97dswspare.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2023-2025, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc97d_sw_spare_h_ +#define _clc97d_sw_spare_h_ + +/* This file is *not* auto-generated. */ + +// +// Quadro Sync is a mechanism used to synchronize scanout and flips between +// GPUs in different systems (e.g., to drive large video walls, such as in a +// planetarium). Special FPGA boards (e.g., P2060 or P2061) are added to the +// system to provide the reference frame lock signal. The VPLL_REF field below +// is set to "QSYNC" on the head which is selected to be driven by the external +// reference signal. As with any HEAD_SET_SW_SPARE method, changing the value +// of a field will trigger a supervisor interrupt sequence. +// +#define NVC97D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF 1:0 +#define NVC97D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF_NO_PREF (0x00000000) +#define NVC97D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF_QSYNC (0x00000001) + +// +// DRR (Dynamic Refresh Rate) is a power saving feature that lowers the refresh +// rate when a high flip rate is not required. A modeset is required in order +// to change the target refresh rate for DRR purposes. Such a modeset +// (indicated by the DRR_MODESET bit) does not change any IMP-relevant +// parameters except back porch (and vertical total), so IMP can optimize such +// modesets by, for example, skipping disablement of mclk switch. +// +// If any head has the DRR_MODESET bit set, no other head that is changing is +// allowed to execute a non-DRR transition as part of the same modeset. +// +#define NVC97D_HEAD_SET_SW_RESERVED_DRR_MODESET 31:31 +#define NVC97D_HEAD_SET_SW_RESERVED_DRR_MODESET_FALSE (0x00000000) +#define NVC97D_HEAD_SET_SW_RESERVED_DRR_MODESET_TRUE (0x00000001) + +#endif // _clc97d_sw_spare_h_ diff --git a/userspace/sdks/nv570/inc/class/clc97e.h b/userspace/sdks/nv570/inc/class/clc97e.h new file mode 100644 index 0000000..78aa9d7 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc97e.h @@ -0,0 +1,751 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc97e_h_ +#define _clc97e_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC97E_WINDOW_CHANNEL_DMA (0x0000C97E) + +// dma opcode instructions +#define NVC97E_DMA +#define NVC97E_DMA_OPCODE 31:29 +#define NVC97E_DMA_OPCODE_METHOD 0x00000000 +#define NVC97E_DMA_OPCODE_JUMP 0x00000001 +#define NVC97E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC97E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC97E_DMA_METHOD_COUNT 27:18 +#define NVC97E_DMA_METHOD_OFFSET 15:2 +#define NVC97E_DMA_DATA 31:0 +#define NVC97E_DMA_DATA_NOP 0x00000000 +#define NVC97E_DMA_JUMP_OFFSET 15:2 +#define NVC97E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVC97E_PUT (0x00000000) +#define NVC97E_PUT_PTR 9:0 +#define NVC97E_GET (0x00000004) +#define NVC97E_GET_PTR 9:0 +#define NVC97E_UPDATE (0x00000200) +#define NVC97E_UPDATE_RELEASE_ELV 0:0 +#define NVC97E_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC97E_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC97E_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC97E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC97E_UPDATE_INTERLOCK_WITH_WIN_IMM 12:12 +#define NVC97E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE (0x00000000) +#define NVC97E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE (0x00000001) +#define NVC97E_SET_SEMAPHORE_ACQUIRE_HI (0x00000204) +#define NVC97E_SET_SEMAPHORE_ACQUIRE_HI_VALUE 31:0 +#define NVC97E_GET_LINE (0x00000208) +#define NVC97E_GET_LINE_LINE 15:0 +#define NVC97E_SET_SEMAPHORE_CONTROL (0x0000020C) +#define NVC97E_SET_SEMAPHORE_CONTROL_SKIP_ACQ 11:11 +#define NVC97E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_FALSE (0x00000000) +#define NVC97E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_TRUE (0x00000001) +#define NVC97E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVC97E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVC97E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVC97E_SET_SEMAPHORE_CONTROL_ACQ_MODE 13:12 +#define NVC97E_SET_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000) +#define NVC97E_SET_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001) +#define NVC97E_SET_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002) +#define NVC97E_SET_SEMAPHORE_CONTROL_REL_MODE 14:14 +#define NVC97E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE (0x00000000) +#define NVC97E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC97E_SET_SEMAPHORE_ACQUIRE (0x00000210) +#define NVC97E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NVC97E_SET_SEMAPHORE_RELEASE (0x00000214) +#define NVC97E_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NVC97E_SET_NOTIFIER_CONTROL (0x00000220) +#define NVC97E_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC97E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC97E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC97E_SET_SIZE (0x00000224) +#define NVC97E_SET_SIZE_WIDTH 15:0 +#define NVC97E_SET_SIZE_HEIGHT 31:16 +#define NVC97E_SET_STORAGE (0x00000228) +#define NVC97E_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NVC97E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NVC97E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NVC97E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC97E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC97E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC97E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC97E_SET_PARAMS (0x0000022C) +#define NVC97E_SET_PARAMS_FORMAT 7:0 +#define NVC97E_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NVC97E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F) +#define NVC97E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NVC97E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC97E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E) +#define NVC97E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC97E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6) +#define NVC97E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NVC97E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9) +#define NVC97E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NVC97E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NVC97E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NVC97E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NVC97E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NVC97E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028) +#define NVC97E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029) +#define NVC97E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035) +#define NVC97E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036) +#define NVC97E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038) +#define NVC97E_SET_PARAMS_FORMAT_Y8___U8___V8_N444 (0x0000003A) +#define NVC97E_SET_PARAMS_FORMAT_Y8___U8___V8_N420 (0x0000003B) +#define NVC97E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055) +#define NVC97E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056) +#define NVC97E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058) +#define NVC97E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075) +#define NVC97E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076) +#define NVC97E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078) +#define NVC97E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18 +#define NVC97E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000) +#define NVC97E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001) +#define NVC97E_SET_PARAMS_SWAP_UV 19:19 +#define NVC97E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000) +#define NVC97E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001) +#define NVC97E_SET_PARAMS_FMT_ROUNDING_MODE 22:22 +#define NVC97E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_TO_NEAREST (0x00000000) +#define NVC97E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_DOWN (0x00000001) +#define NVC97E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004) +#define NVC97E_SET_PLANAR_STORAGE_PITCH 12:0 +#define NVC97E_SET_SEMAPHORE_RELEASE_HI (0x0000023C) +#define NVC97E_SET_SEMAPHORE_RELEASE_HI_VALUE 31:0 +#define NVC97E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004) +#define NVC97E_SET_POINT_IN_X 15:0 +#define NVC97E_SET_POINT_IN_Y 31:16 +#define NVC97E_SET_SIZE_IN (0x00000298) +#define NVC97E_SET_SIZE_IN_WIDTH 15:0 +#define NVC97E_SET_SIZE_IN_HEIGHT 31:16 +#define NVC97E_SET_SIZE_OUT (0x000002A4) +#define NVC97E_SET_SIZE_OUT_WIDTH 15:0 +#define NVC97E_SET_SIZE_OUT_HEIGHT 31:16 +#define NVC97E_SET_CONTROL_INPUT_SCALER (0x000002A8) +#define NVC97E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVC97E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVC97E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVC97E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVC97E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVC97E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVC97E_SET_INPUT_SCALER_COEFF_VALUE (0x000002AC) +#define NVC97E_SET_INPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVC97E_SET_INPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVC97E_SET_COMPOSITION_CONTROL (0x000002EC) +#define NVC97E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0 +#define NVC97E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000) +#define NVC97E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001) +#define NVC97E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002) +#define NVC97E_SET_COMPOSITION_CONTROL_DEPTH 11:4 +#define NVC97E_SET_COMPOSITION_CONTROL_BYPASS 16:16 +#define NVC97E_SET_COMPOSITION_CONTROL_BYPASS_DISABLE (0x00000000) +#define NVC97E_SET_COMPOSITION_CONTROL_BYPASS_ENABLE (0x00000001) +#define NVC97E_SET_COMPOSITION_CONSTANT_ALPHA (0x000002F0) +#define NVC97E_SET_COMPOSITION_CONSTANT_ALPHA_K1 7:0 +#define NVC97E_SET_COMPOSITION_CONSTANT_ALPHA_K2 15:8 +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT (0x000002F4) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0 +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4 +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8 +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12 +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16 +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20 +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24 +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28 +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC97E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC97E_SET_KEY_ALPHA (0x000002F8) +#define NVC97E_SET_KEY_ALPHA_MIN 15:0 +#define NVC97E_SET_KEY_ALPHA_MAX 31:16 +#define NVC97E_SET_KEY_RED_CR (0x000002FC) +#define NVC97E_SET_KEY_RED_CR_MIN 15:0 +#define NVC97E_SET_KEY_RED_CR_MAX 31:16 +#define NVC97E_SET_KEY_GREEN_Y (0x00000300) +#define NVC97E_SET_KEY_GREEN_Y_MIN 15:0 +#define NVC97E_SET_KEY_GREEN_Y_MAX 31:16 +#define NVC97E_SET_KEY_BLUE_CB (0x00000304) +#define NVC97E_SET_KEY_BLUE_CB_MIN 15:0 +#define NVC97E_SET_KEY_BLUE_CB_MAX 31:16 +#define NVC97E_SET_PRESENT_CONTROL (0x00000308) +#define NVC97E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NVC97E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4 +#define NVC97E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NVC97E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NVC97E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8 +#define NVC97E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000) +#define NVC97E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001) +#define NVC97E_SET_PRESENT_CONTROL_STEREO_MODE 13:12 +#define NVC97E_SET_PRESENT_CONTROL_STEREO_MODE_MONO (0x00000000) +#define NVC97E_SET_PRESENT_CONTROL_STEREO_MODE_PAIR_FLIP (0x00000001) +#define NVC97E_SET_PRESENT_CONTROL_STEREO_MODE_AT_ANY_FRAME (0x00000002) +#define NVC97E_SET_ACQ_SEMAPHORE_VALUE_HI (0x0000030C) +#define NVC97E_SET_ACQ_SEMAPHORE_VALUE_HI_VALUE 31:0 +#define NVC97E_SET_ACQ_SEMAPHORE_CONTROL (0x00000330) +#define NVC97E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVC97E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVC97E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVC97E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE 13:12 +#define NVC97E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000) +#define NVC97E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001) +#define NVC97E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002) +#define NVC97E_SET_ACQ_SEMAPHORE_VALUE (0x00000334) +#define NVC97E_SET_ACQ_SEMAPHORE_VALUE_VALUE 31:0 +#define NVC97E_SET_SCAN_DIRECTION (0x0000033C) +#define NVC97E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION 0:0 +#define NVC97E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_LEFT (0x00000000) +#define NVC97E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_RIGHT (0x00000001) +#define NVC97E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION 1:1 +#define NVC97E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_TOP (0x00000000) +#define NVC97E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_BOTTOM (0x00000001) +#define NVC97E_SET_SCAN_DIRECTION_COLUMN_ORDER 2:2 +#define NVC97E_SET_SCAN_DIRECTION_COLUMN_ORDER_FALSE (0x00000000) +#define NVC97E_SET_SCAN_DIRECTION_COLUMN_ORDER_TRUE (0x00000001) +#define NVC97E_SET_TIMESTAMP_ORIGIN_LO (0x00000340) +#define NVC97E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NVC97E_SET_TIMESTAMP_ORIGIN_HI (0x00000344) +#define NVC97E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NVC97E_SET_UPDATE_TIMESTAMP_LO (0x00000348) +#define NVC97E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NVC97E_SET_UPDATE_TIMESTAMP_HI (0x0000034C) +#define NVC97E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NVC97E_SET_INTERLOCK_FLAGS (0x00000370) +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 0:0 +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+1):((i)+1) +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 1:1 +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 2:2 +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 3:3 +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 4:4 +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 5:5 +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 6:6 +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 7:7 +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 8:8 +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC97E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS (0x00000374) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC97E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVC97E_SET_EXT_PACKET_CONTROL (0x00000398) +#define NVC97E_SET_EXT_PACKET_CONTROL_ENABLE 0:0 +#define NVC97E_SET_EXT_PACKET_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC97E_SET_EXT_PACKET_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC97E_SET_EXT_PACKET_CONTROL_LOCATION 4:4 +#define NVC97E_SET_EXT_PACKET_CONTROL_LOCATION_VSYNC (0x00000000) +#define NVC97E_SET_EXT_PACKET_CONTROL_LOCATION_VBLANK (0x00000001) +#define NVC97E_SET_EXT_PACKET_CONTROL_FREQUENCY 8:8 +#define NVC97E_SET_EXT_PACKET_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVC97E_SET_EXT_PACKET_CONTROL_FREQUENCY_ONCE (0x00000001) +#define NVC97E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE 12:12 +#define NVC97E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_DISABLE (0x00000000) +#define NVC97E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_ENABLE (0x00000001) +#define NVC97E_SET_EXT_PACKET_CONTROL_SIZE 27:16 +#define NVC97E_SET_EXT_PACKET_DATA (0x0000039C) +#define NVC97E_SET_EXT_PACKET_DATA_DB0 7:0 +#define NVC97E_SET_EXT_PACKET_DATA_DB1 15:8 +#define NVC97E_SET_EXT_PACKET_DATA_DB2 23:16 +#define NVC97E_SET_EXT_PACKET_DATA_DB3 31:24 +#define NVC97E_SET_FMT_COEFFICIENT_C00 (0x00000400) +#define NVC97E_SET_FMT_COEFFICIENT_C00_VALUE 20:0 +#define NVC97E_SET_FMT_COEFFICIENT_C01 (0x00000404) +#define NVC97E_SET_FMT_COEFFICIENT_C01_VALUE 20:0 +#define NVC97E_SET_FMT_COEFFICIENT_C02 (0x00000408) +#define NVC97E_SET_FMT_COEFFICIENT_C02_VALUE 20:0 +#define NVC97E_SET_FMT_COEFFICIENT_C03 (0x0000040C) +#define NVC97E_SET_FMT_COEFFICIENT_C03_VALUE 20:0 +#define NVC97E_SET_FMT_COEFFICIENT_C10 (0x00000410) +#define NVC97E_SET_FMT_COEFFICIENT_C10_VALUE 20:0 +#define NVC97E_SET_FMT_COEFFICIENT_C11 (0x00000414) +#define NVC97E_SET_FMT_COEFFICIENT_C11_VALUE 20:0 +#define NVC97E_SET_FMT_COEFFICIENT_C12 (0x00000418) +#define NVC97E_SET_FMT_COEFFICIENT_C12_VALUE 20:0 +#define NVC97E_SET_FMT_COEFFICIENT_C13 (0x0000041C) +#define NVC97E_SET_FMT_COEFFICIENT_C13_VALUE 20:0 +#define NVC97E_SET_FMT_COEFFICIENT_C20 (0x00000420) +#define NVC97E_SET_FMT_COEFFICIENT_C20_VALUE 20:0 +#define NVC97E_SET_FMT_COEFFICIENT_C21 (0x00000424) +#define NVC97E_SET_FMT_COEFFICIENT_C21_VALUE 20:0 +#define NVC97E_SET_FMT_COEFFICIENT_C22 (0x00000428) +#define NVC97E_SET_FMT_COEFFICIENT_C22_VALUE 20:0 +#define NVC97E_SET_FMT_COEFFICIENT_C23 (0x0000042C) +#define NVC97E_SET_FMT_COEFFICIENT_C23_VALUE 20:0 +#define NVC97E_SET_ILUT_CONTROL (0x00000440) +#define NVC97E_SET_ILUT_CONTROL_INTERPOLATE 0:0 +#define NVC97E_SET_ILUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC97E_SET_ILUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC97E_SET_ILUT_CONTROL_MIRROR 1:1 +#define NVC97E_SET_ILUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC97E_SET_ILUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC97E_SET_ILUT_CONTROL_MODE 3:2 +#define NVC97E_SET_ILUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVC97E_SET_ILUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVC97E_SET_ILUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVC97E_SET_ILUT_CONTROL_SIZE 18:8 +#define NVC97E_SET_CSC00CONTROL (0x0000045C) +#define NVC97E_SET_CSC00CONTROL_ENABLE 0:0 +#define NVC97E_SET_CSC00CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC97E_SET_CSC00CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC97E_SET_CSC00COEFFICIENT_C00 (0x00000460) +#define NVC97E_SET_CSC00COEFFICIENT_C00_VALUE 20:0 +#define NVC97E_SET_CSC00COEFFICIENT_C01 (0x00000464) +#define NVC97E_SET_CSC00COEFFICIENT_C01_VALUE 20:0 +#define NVC97E_SET_CSC00COEFFICIENT_C02 (0x00000468) +#define NVC97E_SET_CSC00COEFFICIENT_C02_VALUE 20:0 +#define NVC97E_SET_CSC00COEFFICIENT_C03 (0x0000046C) +#define NVC97E_SET_CSC00COEFFICIENT_C03_VALUE 20:0 +#define NVC97E_SET_CSC00COEFFICIENT_C10 (0x00000470) +#define NVC97E_SET_CSC00COEFFICIENT_C10_VALUE 20:0 +#define NVC97E_SET_CSC00COEFFICIENT_C11 (0x00000474) +#define NVC97E_SET_CSC00COEFFICIENT_C11_VALUE 20:0 +#define NVC97E_SET_CSC00COEFFICIENT_C12 (0x00000478) +#define NVC97E_SET_CSC00COEFFICIENT_C12_VALUE 20:0 +#define NVC97E_SET_CSC00COEFFICIENT_C13 (0x0000047C) +#define NVC97E_SET_CSC00COEFFICIENT_C13_VALUE 20:0 +#define NVC97E_SET_CSC00COEFFICIENT_C20 (0x00000480) +#define NVC97E_SET_CSC00COEFFICIENT_C20_VALUE 20:0 +#define NVC97E_SET_CSC00COEFFICIENT_C21 (0x00000484) +#define NVC97E_SET_CSC00COEFFICIENT_C21_VALUE 20:0 +#define NVC97E_SET_CSC00COEFFICIENT_C22 (0x00000488) +#define NVC97E_SET_CSC00COEFFICIENT_C22_VALUE 20:0 +#define NVC97E_SET_CSC00COEFFICIENT_C23 (0x0000048C) +#define NVC97E_SET_CSC00COEFFICIENT_C23_VALUE 20:0 +#define NVC97E_SET_CSC0LUT_CONTROL (0x000004A0) +#define NVC97E_SET_CSC0LUT_CONTROL_INTERPOLATE 0:0 +#define NVC97E_SET_CSC0LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC97E_SET_CSC0LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC97E_SET_CSC0LUT_CONTROL_MIRROR 1:1 +#define NVC97E_SET_CSC0LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC97E_SET_CSC0LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC97E_SET_CSC0LUT_CONTROL_ENABLE 4:4 +#define NVC97E_SET_CSC0LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC97E_SET_CSC0LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC97E_SET_CSC01CONTROL (0x000004BC) +#define NVC97E_SET_CSC01CONTROL_ENABLE 0:0 +#define NVC97E_SET_CSC01CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC97E_SET_CSC01CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC97E_SET_CSC01COEFFICIENT_C00 (0x000004C0) +#define NVC97E_SET_CSC01COEFFICIENT_C00_VALUE 20:0 +#define NVC97E_SET_CSC01COEFFICIENT_C01 (0x000004C4) +#define NVC97E_SET_CSC01COEFFICIENT_C01_VALUE 20:0 +#define NVC97E_SET_CSC01COEFFICIENT_C02 (0x000004C8) +#define NVC97E_SET_CSC01COEFFICIENT_C02_VALUE 20:0 +#define NVC97E_SET_CSC01COEFFICIENT_C03 (0x000004CC) +#define NVC97E_SET_CSC01COEFFICIENT_C03_VALUE 20:0 +#define NVC97E_SET_CSC01COEFFICIENT_C10 (0x000004D0) +#define NVC97E_SET_CSC01COEFFICIENT_C10_VALUE 20:0 +#define NVC97E_SET_CSC01COEFFICIENT_C11 (0x000004D4) +#define NVC97E_SET_CSC01COEFFICIENT_C11_VALUE 20:0 +#define NVC97E_SET_CSC01COEFFICIENT_C12 (0x000004D8) +#define NVC97E_SET_CSC01COEFFICIENT_C12_VALUE 20:0 +#define NVC97E_SET_CSC01COEFFICIENT_C13 (0x000004DC) +#define NVC97E_SET_CSC01COEFFICIENT_C13_VALUE 20:0 +#define NVC97E_SET_CSC01COEFFICIENT_C20 (0x000004E0) +#define NVC97E_SET_CSC01COEFFICIENT_C20_VALUE 20:0 +#define NVC97E_SET_CSC01COEFFICIENT_C21 (0x000004E4) +#define NVC97E_SET_CSC01COEFFICIENT_C21_VALUE 20:0 +#define NVC97E_SET_CSC01COEFFICIENT_C22 (0x000004E8) +#define NVC97E_SET_CSC01COEFFICIENT_C22_VALUE 20:0 +#define NVC97E_SET_CSC01COEFFICIENT_C23 (0x000004EC) +#define NVC97E_SET_CSC01COEFFICIENT_C23_VALUE 20:0 +#define NVC97E_SET_TMO_CONTROL (0x00000500) +#define NVC97E_SET_TMO_CONTROL_INTERPOLATE 0:0 +#define NVC97E_SET_TMO_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC97E_SET_TMO_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC97E_SET_TMO_CONTROL_SAT_MODE 3:2 +#define NVC97E_SET_TMO_CONTROL_SIZE 18:8 +#define NVC97E_SET_TMO_LOW_INTENSITY_ZONE (0x00000508) +#define NVC97E_SET_TMO_LOW_INTENSITY_ZONE_END 29:16 +#define NVC97E_SET_TMO_LOW_INTENSITY_VALUE (0x0000050C) +#define NVC97E_SET_TMO_LOW_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVC97E_SET_TMO_LOW_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVC97E_SET_TMO_LOW_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVC97E_SET_TMO_MEDIUM_INTENSITY_ZONE (0x00000510) +#define NVC97E_SET_TMO_MEDIUM_INTENSITY_ZONE_START 13:0 +#define NVC97E_SET_TMO_MEDIUM_INTENSITY_ZONE_END 29:16 +#define NVC97E_SET_TMO_MEDIUM_INTENSITY_VALUE (0x00000514) +#define NVC97E_SET_TMO_MEDIUM_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVC97E_SET_TMO_MEDIUM_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVC97E_SET_TMO_MEDIUM_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVC97E_SET_TMO_HIGH_INTENSITY_ZONE (0x00000518) +#define NVC97E_SET_TMO_HIGH_INTENSITY_ZONE_START 13:0 +#define NVC97E_SET_TMO_HIGH_INTENSITY_VALUE (0x0000051C) +#define NVC97E_SET_TMO_HIGH_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVC97E_SET_TMO_HIGH_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVC97E_SET_TMO_HIGH_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVC97E_SET_CSC10CONTROL (0x0000053C) +#define NVC97E_SET_CSC10CONTROL_ENABLE 0:0 +#define NVC97E_SET_CSC10CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC97E_SET_CSC10CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC97E_SET_CSC10COEFFICIENT_C00 (0x00000540) +#define NVC97E_SET_CSC10COEFFICIENT_C00_VALUE 20:0 +#define NVC97E_SET_CSC10COEFFICIENT_C01 (0x00000544) +#define NVC97E_SET_CSC10COEFFICIENT_C01_VALUE 20:0 +#define NVC97E_SET_CSC10COEFFICIENT_C02 (0x00000548) +#define NVC97E_SET_CSC10COEFFICIENT_C02_VALUE 20:0 +#define NVC97E_SET_CSC10COEFFICIENT_C03 (0x0000054C) +#define NVC97E_SET_CSC10COEFFICIENT_C03_VALUE 20:0 +#define NVC97E_SET_CSC10COEFFICIENT_C10 (0x00000550) +#define NVC97E_SET_CSC10COEFFICIENT_C10_VALUE 20:0 +#define NVC97E_SET_CSC10COEFFICIENT_C11 (0x00000554) +#define NVC97E_SET_CSC10COEFFICIENT_C11_VALUE 20:0 +#define NVC97E_SET_CSC10COEFFICIENT_C12 (0x00000558) +#define NVC97E_SET_CSC10COEFFICIENT_C12_VALUE 20:0 +#define NVC97E_SET_CSC10COEFFICIENT_C13 (0x0000055C) +#define NVC97E_SET_CSC10COEFFICIENT_C13_VALUE 20:0 +#define NVC97E_SET_CSC10COEFFICIENT_C20 (0x00000560) +#define NVC97E_SET_CSC10COEFFICIENT_C20_VALUE 20:0 +#define NVC97E_SET_CSC10COEFFICIENT_C21 (0x00000564) +#define NVC97E_SET_CSC10COEFFICIENT_C21_VALUE 20:0 +#define NVC97E_SET_CSC10COEFFICIENT_C22 (0x00000568) +#define NVC97E_SET_CSC10COEFFICIENT_C22_VALUE 20:0 +#define NVC97E_SET_CSC10COEFFICIENT_C23 (0x0000056C) +#define NVC97E_SET_CSC10COEFFICIENT_C23_VALUE 20:0 +#define NVC97E_SET_CSC1LUT_CONTROL (0x00000580) +#define NVC97E_SET_CSC1LUT_CONTROL_INTERPOLATE 0:0 +#define NVC97E_SET_CSC1LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC97E_SET_CSC1LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC97E_SET_CSC1LUT_CONTROL_MIRROR 1:1 +#define NVC97E_SET_CSC1LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC97E_SET_CSC1LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC97E_SET_CSC1LUT_CONTROL_ENABLE 4:4 +#define NVC97E_SET_CSC1LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC97E_SET_CSC1LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC97E_SET_CSC11CONTROL (0x0000059C) +#define NVC97E_SET_CSC11CONTROL_ENABLE 0:0 +#define NVC97E_SET_CSC11CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC97E_SET_CSC11CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC97E_SET_CSC11COEFFICIENT_C00 (0x000005A0) +#define NVC97E_SET_CSC11COEFFICIENT_C00_VALUE 20:0 +#define NVC97E_SET_CSC11COEFFICIENT_C01 (0x000005A4) +#define NVC97E_SET_CSC11COEFFICIENT_C01_VALUE 20:0 +#define NVC97E_SET_CSC11COEFFICIENT_C02 (0x000005A8) +#define NVC97E_SET_CSC11COEFFICIENT_C02_VALUE 20:0 +#define NVC97E_SET_CSC11COEFFICIENT_C03 (0x000005AC) +#define NVC97E_SET_CSC11COEFFICIENT_C03_VALUE 20:0 +#define NVC97E_SET_CSC11COEFFICIENT_C10 (0x000005B0) +#define NVC97E_SET_CSC11COEFFICIENT_C10_VALUE 20:0 +#define NVC97E_SET_CSC11COEFFICIENT_C11 (0x000005B4) +#define NVC97E_SET_CSC11COEFFICIENT_C11_VALUE 20:0 +#define NVC97E_SET_CSC11COEFFICIENT_C12 (0x000005B8) +#define NVC97E_SET_CSC11COEFFICIENT_C12_VALUE 20:0 +#define NVC97E_SET_CSC11COEFFICIENT_C13 (0x000005BC) +#define NVC97E_SET_CSC11COEFFICIENT_C13_VALUE 20:0 +#define NVC97E_SET_CSC11COEFFICIENT_C20 (0x000005C0) +#define NVC97E_SET_CSC11COEFFICIENT_C20_VALUE 20:0 +#define NVC97E_SET_CSC11COEFFICIENT_C21 (0x000005C4) +#define NVC97E_SET_CSC11COEFFICIENT_C21_VALUE 20:0 +#define NVC97E_SET_CSC11COEFFICIENT_C22 (0x000005C8) +#define NVC97E_SET_CSC11COEFFICIENT_C22_VALUE 20:0 +#define NVC97E_SET_CSC11COEFFICIENT_C23 (0x000005CC) +#define NVC97E_SET_CSC11COEFFICIENT_C23_VALUE 20:0 +#define NVC97E_SET_CLAMP_RANGE (0x000005D0) +#define NVC97E_SET_CLAMP_RANGE_LOW 15:0 +#define NVC97E_SET_CLAMP_RANGE_HIGH 31:16 +#define NVC97E_SW_RESERVED(b) (0x000005D4 + (b)*0x00000004) +#define NVC97E_SW_RESERVED_VALUE 31:0 +#define NVC97E_SET_SURFACE_ADDRESS_HI_SEMAPHORE (0x00000640) +#define NVC97E_SET_SURFACE_ADDRESS_HI_SEMAPHORE_ADDRESS_HI 31:0 +#define NVC97E_SET_SURFACE_ADDRESS_LO_SEMAPHORE (0x00000644) +#define NVC97E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ADDRESS_LO 31:4 +#define NVC97E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET 3:2 +#define NVC97E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_IOVA (0x00000000) +#define NVC97E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_NVM (0x00000001) +#define NVC97E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_PCI (0x00000002) +#define NVC97E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVC97E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE 0:0 +#define NVC97E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE_DISABLE (0x00000000) +#define NVC97E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE_ENABLE (0x00000001) +#define NVC97E_SET_SURFACE_ADDRESS_HI_ACQ_SEMAPHORE (0x00000648) +#define NVC97E_SET_SURFACE_ADDRESS_HI_ACQ_SEMAPHORE_ADDRESS_HI 31:0 +#define NVC97E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE (0x0000064C) +#define NVC97E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ADDRESS_LO 31:4 +#define NVC97E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET 3:2 +#define NVC97E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_IOVA (0x00000000) +#define NVC97E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_NVM (0x00000001) +#define NVC97E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_PCI (0x00000002) +#define NVC97E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVC97E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE 0:0 +#define NVC97E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE_DISABLE (0x00000000) +#define NVC97E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE_ENABLE (0x00000001) +#define NVC97E_SET_SURFACE_ADDRESS_HI_NOTIFIER (0x00000650) +#define NVC97E_SET_SURFACE_ADDRESS_HI_NOTIFIER_ADDRESS_HI 31:0 +#define NVC97E_SET_SURFACE_ADDRESS_LO_NOTIFIER (0x00000654) +#define NVC97E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ADDRESS_LO 31:4 +#define NVC97E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET 3:2 +#define NVC97E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_IOVA (0x00000000) +#define NVC97E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_NVM (0x00000001) +#define NVC97E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI (0x00000002) +#define NVC97E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVC97E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE 0:0 +#define NVC97E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_DISABLE (0x00000000) +#define NVC97E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_ENABLE (0x00000001) +#define NVC97E_SET_SURFACE_ADDRESS_HI_ISO(b) (0x00000658 + (b)*0x00000004) +#define NVC97E_SET_SURFACE_ADDRESS_HI_ISO_ADDRESS_HI 31:0 +#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO(b) (0x00000670 + (b)*0x00000004) +#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO_ADDRESS_LO 31:4 +#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO_TARGET 3:2 +#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_IOVA (0x00000000) +#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_NVM (0x00000001) +#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_PCI (0x00000002) +#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO_KIND 1:1 +#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO_KIND_PITCH (0x00000000) +#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO_KIND_BLOCKLINEAR (0x00000001) +#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE 0:0 +#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE_DISABLE (0x00000000) +#define NVC97E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE_ENABLE (0x00000001) +#define NVC97E_SET_SURFACE_ADDRESS_HI_ILUT (0x00000688) +#define NVC97E_SET_SURFACE_ADDRESS_HI_ILUT_ADDRESS_HI 31:0 +#define NVC97E_SET_SURFACE_ADDRESS_LO_ILUT (0x0000068C) +#define NVC97E_SET_SURFACE_ADDRESS_LO_ILUT_ADDRESS_LO 31:4 +#define NVC97E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET 3:2 +#define NVC97E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_IOVA (0x00000000) +#define NVC97E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_NVM (0x00000001) +#define NVC97E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_PCI (0x00000002) +#define NVC97E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVC97E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE 0:0 +#define NVC97E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE_DISABLE (0x00000000) +#define NVC97E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE_ENABLE (0x00000001) +#define NVC97E_SET_SURFACE_ADDRESS_HI_TMO_LUT (0x00000690) +#define NVC97E_SET_SURFACE_ADDRESS_HI_TMO_LUT_ADDRESS_HI 31:0 +#define NVC97E_SET_SURFACE_ADDRESS_LO_TMO_LUT (0x00000694) +#define NVC97E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ADDRESS_LO 31:4 +#define NVC97E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET 3:2 +#define NVC97E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_IOVA (0x00000000) +#define NVC97E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_NVM (0x00000001) +#define NVC97E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_PCI (0x00000002) +#define NVC97E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVC97E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE 0:0 +#define NVC97E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE_DISABLE (0x00000000) +#define NVC97E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE_ENABLE (0x00000001) +#define NVC97E_SET_TELLTALE_CRC_REGION(b) (0x00000698 + (b)*0x00000004) +#define NVC97E_SET_TELLTALE_CRC_REGION_INDEX0 7:0 +#define NVC97E_SET_TELLTALE_CRC_REGION_INDEX1 15:8 +#define NVC97E_SET_TELLTALE_CRC_REGION_INDEX2 23:16 +#define NVC97E_SET_TELLTALE_CRC_REGION_INDEX3 31:24 +#define NVC97E_SET_TELLTALE_GOLDEN_CRC_LOWER(b) (0x000006A8 + (b)*0x00000004) +#define NVC97E_SET_TELLTALE_GOLDEN_CRC_LOWER_CRC 31:0 +#define NVC97E_SET_TELLTALE_GOLDEN_CRC_UPPER(b) (0x000006E8 + (b)*0x00000004) +#define NVC97E_SET_TELLTALE_GOLDEN_CRC_UPPER_CRC 31:0 +#define NVC97E_SET_TELLTALE_CRC_CONTROL (0x00000728) +#define NVC97E_SET_TELLTALE_CRC_CONTROL_REGION_ENABLE 15:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc97e_h diff --git a/userspace/sdks/nv570/inc/class/clc997.h b/userspace/sdks/nv570/inc/class/clc997.h new file mode 100644 index 0000000..81607be --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc997.h @@ -0,0 +1,4481 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_ada_a_h_ +#define _cl_ada_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl ada_a */ + +#include "nvtypes.h" + +#define ADA_A 0xC997 + +#define NVC997_SET_OBJECT 0x0000 +#define NVC997_SET_OBJECT_CLASS_ID 15:0 +#define NVC997_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC997_NO_OPERATION 0x0100 +#define NVC997_NO_OPERATION_V 31:0 + +#define NVC997_SET_NOTIFY_A 0x0104 +#define NVC997_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC997_SET_NOTIFY_B 0x0108 +#define NVC997_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC997_NOTIFY 0x010c +#define NVC997_NOTIFY_TYPE 31:0 +#define NVC997_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC997_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC997_WAIT_FOR_IDLE 0x0110 +#define NVC997_WAIT_FOR_IDLE_V 31:0 + +#define NVC997_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC997_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC997_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC997_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC997_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC997_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC997_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC997_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC997_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC997_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC997_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC997_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC997_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC997_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC997_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC997_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC997_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC997_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC997_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC997_SEND_GO_IDLE 0x013c +#define NVC997_SEND_GO_IDLE_V 31:0 + +#define NVC997_PM_TRIGGER 0x0140 +#define NVC997_PM_TRIGGER_V 31:0 + +#define NVC997_PM_TRIGGER_WFI 0x0144 +#define NVC997_PM_TRIGGER_WFI_V 31:0 + +#define NVC997_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC997_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC997_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC997_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC997_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC997_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC997_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC997_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER 0x0158 +#define NVC997_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER_PAYLOAD_LOWER 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER 0x015c +#define NVC997_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD_UPPER 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_ADDRESS_LOWER 0x0160 +#define NVC997_SET_REPORT_SEMAPHORE_ADDRESS_LOWER_LOWER 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_ADDRESS_UPPER 0x0164 +#define NVC997_SET_REPORT_SEMAPHORE_ADDRESS_UPPER_UPPER 7:0 + +#define NVC997_REPORT_SEMAPHORE_EXECUTE 0x0168 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_OPERATION 1:0 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_OPERATION_RELEASE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_OPERATION_ACQUIRE 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_OPERATION_REPORT_ONLY 0x00000002 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_OPERATION_TRAP 0x00000003 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION 5:2 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC997_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE 6:6 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT 11:7 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_NONE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_SCG_CLOCKS 0x00000008 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS0 0x0000000A +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS1 0x0000000C +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS2 0x0000000E +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS3 0x00000010 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_TIMESTAMP 0x00000014 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE 14:13 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_SUB_REPORT 17:15 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE 19:19 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE 18:18 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE 20:20 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP 23:21 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_INC 0x00000003 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_AND 0x00000005 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_OR 0x00000006 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT 25:24 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64 27:27 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_FALSE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_TRUE 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE 29:28 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_NONE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 + +#define NVC997_LINE_LENGTH_IN 0x0180 +#define NVC997_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC997_LINE_COUNT 0x0184 +#define NVC997_LINE_COUNT_VALUE 31:0 + +#define NVC997_OFFSET_OUT_UPPER 0x0188 +#define NVC997_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC997_OFFSET_OUT 0x018c +#define NVC997_OFFSET_OUT_VALUE 31:0 + +#define NVC997_PITCH_OUT 0x0190 +#define NVC997_PITCH_OUT_VALUE 31:0 + +#define NVC997_SET_DST_BLOCK_SIZE 0x0194 +#define NVC997_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC997_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC997_SET_DST_WIDTH 0x0198 +#define NVC997_SET_DST_WIDTH_V 31:0 + +#define NVC997_SET_DST_HEIGHT 0x019c +#define NVC997_SET_DST_HEIGHT_V 31:0 + +#define NVC997_SET_DST_DEPTH 0x01a0 +#define NVC997_SET_DST_DEPTH_V 31:0 + +#define NVC997_SET_DST_LAYER 0x01a4 +#define NVC997_SET_DST_LAYER_V 31:0 + +#define NVC997_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC997_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC997_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC997_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC997_LAUNCH_DMA 0x01b0 +#define NVC997_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC997_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC997_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC997_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC997_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC997_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC997_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC997_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC997_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC997_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC997_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC997_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC997_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC997_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC997_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC997_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC997_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC997_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC997_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC997_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC997_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC997_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC997_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC997_LOAD_INLINE_DATA 0x01b4 +#define NVC997_LOAD_INLINE_DATA_V 31:0 + +#define NVC997_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC997_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC997_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC997_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC997_SET_MME_SWITCH_STATE 0x01ec +#define NVC997_SET_MME_SWITCH_STATE_VALID 0:0 +#define NVC997_SET_MME_SWITCH_STATE_VALID_FALSE 0x00000000 +#define NVC997_SET_MME_SWITCH_STATE_VALID_TRUE 0x00000001 +#define NVC997_SET_MME_SWITCH_STATE_SAVE_MACRO 11:4 +#define NVC997_SET_MME_SWITCH_STATE_RESTORE_MACRO 19:12 + +#define NVC997_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC997_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC997_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC997_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC997_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC997_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC997_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC997_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC997_RUN_DS_NOW 0x0200 +#define NVC997_RUN_DS_NOW_V 31:0 + +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC997_SET_GS_MODE 0x0208 +#define NVC997_SET_GS_MODE_TYPE 0:0 +#define NVC997_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVC997_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVC997_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC997_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC997_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC997_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC997_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC997_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_GS_DM_FIFO 0x0214 +#define NVC997_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC997_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC997_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC997_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC997_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC997_INVALIDATE_SHADER_CACHES 0x021c +#define NVC997_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC997_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC997_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC997_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC997_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC997_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC997_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC997_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC997_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC997_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC997_SET_INSTANCE_COUNT 0x0220 +#define NVC997_SET_INSTANCE_COUNT_V 31:0 + +#define NVC997_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVC997_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVC997_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC997_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVC997_SET_MME_VERSION 0x0234 +#define NVC997_SET_MME_VERSION_MAJOR 7:0 + +#define NVC997_SET_INDEX_BUFFER_SIZE_A 0x0238 +#define NVC997_SET_INDEX_BUFFER_SIZE_A_UPPER 7:0 + +#define NVC997_SET_INDEX_BUFFER_SIZE_B 0x023c +#define NVC997_SET_INDEX_BUFFER_SIZE_B_LOWER 31:0 + +#define NVC997_SET_ROOT_TABLE_VISIBILITY(i) (0x0240+(i)*4) +#define NVC997_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP0_ENABLE 1:0 +#define NVC997_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP1_ENABLE 5:4 +#define NVC997_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP2_ENABLE 9:8 +#define NVC997_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP3_ENABLE 13:12 +#define NVC997_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP4_ENABLE 17:16 + +#define NVC997_SET_DRAW_CONTROL_A 0x0260 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY 3:0 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_POINTS 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_LINES 0x00000001 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_QUADS 0x00000007 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_PATCH 0x0000000E +#define NVC997_SET_DRAW_CONTROL_A_PRIMITIVE_ID 4:4 +#define NVC997_SET_DRAW_CONTROL_A_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ID 6:5 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ID_FIRST 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC997_SET_DRAW_CONTROL_A_SPLIT_MODE 8:7 +#define NVC997_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC997_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC997_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE 9:9 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 +#define NVC997_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX 10:10 +#define NVC997_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_FALSE 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_TRUE 0x00000001 +#define NVC997_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX 11:11 +#define NVC997_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_FALSE 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_TRUE 0x00000001 + +#define NVC997_SET_DRAW_CONTROL_B 0x0264 +#define NVC997_SET_DRAW_CONTROL_B_INSTANCE_COUNT 31:0 + +#define NVC997_DRAW_INDEX_BUFFER_BEGIN_END_A 0x0268 +#define NVC997_DRAW_INDEX_BUFFER_BEGIN_END_A_FIRST 31:0 + +#define NVC997_DRAW_INDEX_BUFFER_BEGIN_END_B 0x026c +#define NVC997_DRAW_INDEX_BUFFER_BEGIN_END_B_COUNT 31:0 + +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_A 0x0270 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_A_START 31:0 + +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_B 0x0274 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_B_COUNT 31:0 + +#define NVC997_INVALIDATE_RASTER_CACHE_NO_WFI 0x027c +#define NVC997_INVALIDATE_RASTER_CACHE_NO_WFI_V 0:0 + +#define NVC997_SET_COLOR_RENDER_TO_ZETA_SURFACE 0x02b8 +#define NVC997_SET_COLOR_RENDER_TO_ZETA_SURFACE_V 0:0 +#define NVC997_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_FALSE 0x00000000 +#define NVC997_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_TRUE 0x00000001 + +#define NVC997_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION 0x02bc +#define NVC997_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V 0:0 +#define NVC997_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_FALSE 0x00000000 +#define NVC997_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_TRUE 0x00000001 + +#define NVC997_INCREMENT_SYNC_POINT 0x02c8 +#define NVC997_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC997_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC997_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC997_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC997_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC997_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC997_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC997_SET_ROOT_TABLE_PREFETCH 0x02d0 +#define NVC997_SET_ROOT_TABLE_PREFETCH_STAGE_ENABLES 5:0 + +#define NVC997_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC997_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC997_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC997_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVC997_DECOMPRESS_SURFACE 0x02e0 +#define NVC997_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC997_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC997_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC997_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC997_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC997_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC997_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC997_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC997_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC997_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC997_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC997_SET_ZCULL_SUBREGION 0x02e8 +#define NVC997_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC997_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC997_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC997_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC997_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC997_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC997_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC997_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC997_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC997_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC997_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC997_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC997_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC997_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC997_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC997_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC997_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC997_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC997_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC997_DRAW_ZERO_INDEX 0x0304 +#define NVC997_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC997_SET_L1_CONFIGURATION 0x0308 +#define NVC997_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC997_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC997_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC997_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC997_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC997_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC997_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC997_SET_SPA_VERSION 0x0310 +#define NVC997_SET_SPA_VERSION_MINOR 7:0 +#define NVC997_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC997_SET_TIMESLICE_BATCH_LIMIT 0x0314 +#define NVC997_SET_TIMESLICE_BATCH_LIMIT_BATCH_LIMIT 15:0 + +#define NVC997_SET_SNAP_GRID_LINE 0x0318 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC997_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC997_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC997_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC997_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC997_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC997_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC997_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC997_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC997_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC997_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC997_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC997_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC997_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC997_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC997_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC997_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC997_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC997_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC997_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC997_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC997_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC997_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC997_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC997_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC997_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC997_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC997_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC997_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC997_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC997_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC997_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC997_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC997_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC997_RESERVED_TG07 0x033c +#define NVC997_RESERVED_TG07_V 0:0 + +#define NVC997_RESERVED_TG08 0x0340 +#define NVC997_RESERVED_TG08_V 0:0 + +#define NVC997_RESERVED_TG09 0x0344 +#define NVC997_RESERVED_TG09_V 0:0 + +#define NVC997_RESERVED_TG10 0x0348 +#define NVC997_RESERVED_TG10_V 0:0 + +#define NVC997_RESERVED_TG11 0x034c +#define NVC997_RESERVED_TG11_V 0:0 + +#define NVC997_RESERVED_TG12 0x0350 +#define NVC997_RESERVED_TG12_V 0:0 + +#define NVC997_RESERVED_TG13 0x0354 +#define NVC997_RESERVED_TG13_V 0:0 + +#define NVC997_RESERVED_TG14 0x0358 +#define NVC997_RESERVED_TG14_V 0:0 + +#define NVC997_RESERVED_TG15 0x035c +#define NVC997_RESERVED_TG15_V 0:0 + +#define NVC997_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC997_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC997_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC997_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC997_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC997_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC997_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC997_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC997_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC997_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC997_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC997_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC997_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC997_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC997_SET_RASTER_ENABLE 0x037c +#define NVC997_SET_RASTER_ENABLE_V 0:0 +#define NVC997_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC997_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC997_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC997_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC997_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC997_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC997_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC997_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC997_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC997_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC997_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVC997_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVC997_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVC997_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVC997_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVC997_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVC997_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVC997_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVC997_SET_Z_ROP_SLICE_MAP 0x0500 +#define NVC997_SET_Z_ROP_SLICE_MAP_VIRTUAL_ADDRESS_MASK 31:0 + +#define NVC997_SET_ROOT_TABLE_SELECTOR 0x0504 +#define NVC997_SET_ROOT_TABLE_SELECTOR_ROOT_TABLE 2:0 +#define NVC997_SET_ROOT_TABLE_SELECTOR_OFFSET 15:8 + +#define NVC997_LOAD_ROOT_TABLE 0x0508 +#define NVC997_LOAD_ROOT_TABLE_V 31:0 + +#define NVC997_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVC997_SET_MME_MEM_ADDRESS_A_UPPER 16:0 + +#define NVC997_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVC997_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVC997_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVC997_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVC997_MME_DMA_READ 0x055c +#define NVC997_MME_DMA_READ_LENGTH 31:0 + +#define NVC997_MME_DMA_READ_FIFOED 0x0560 +#define NVC997_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVC997_MME_DMA_WRITE 0x0564 +#define NVC997_MME_DMA_WRITE_LENGTH 31:0 + +#define NVC997_MME_DMA_REDUCTION 0x0568 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVC997_MME_DMA_SYSMEMBAR 0x056c +#define NVC997_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVC997_MME_DMA_SYNC 0x0570 +#define NVC997_MME_DMA_SYNC_VALUE 31:0 + +#define NVC997_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NVC997_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NVC997_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NVC997_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NVC997_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NVC997_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NVC997_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NVC997_SET_VERTEX_STREAM_SIZE_A(j) (0x0600+(j)*8) +#define NVC997_SET_VERTEX_STREAM_SIZE_A_UPPER 7:0 + +#define NVC997_SET_VERTEX_STREAM_SIZE_B(j) (0x0604+(j)*8) +#define NVC997_SET_VERTEX_STREAM_SIZE_B_LOWER 31:0 + +#define NVC997_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC997_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC997_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC997_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC997_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC997_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC997_SET_RASTER_INPUT 0x0740 +#define NVC997_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC997_SET_STREAM_OUTPUT 0x0744 +#define NVC997_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC997_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC997_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC997_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC997_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC997_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC997_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC997_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC997_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC997_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC997_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC997_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC997_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC997_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC997_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC997_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC997_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC997_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC997_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC997_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC997_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC997_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC997_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC997_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC997_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC997_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVC997_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC997_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC997_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC997_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC997_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC997_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC997_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC997_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC997_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC997_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC997_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC997_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC997_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC997_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC997_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC997_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC997_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC997_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC997_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC997_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC997_SET_ZCULL_STORAGE_B 0x07ec +#define NVC997_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC997_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC997_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC997_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC997_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC997_SET_ZT_READ_ONLY 0x07f8 +#define NVC997_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC997_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC997_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC997_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC997_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC997_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC997_THROTTLE_SM 0x07fc +#define NVC997_THROTTLE_SM_MULTIPLY_ADD 0:0 +#define NVC997_THROTTLE_SM_MULTIPLY_ADD_FALSE 0x00000000 +#define NVC997_THROTTLE_SM_MULTIPLY_ADD_TRUE 0x00000001 + +#define NVC997_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC997_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC997_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC997_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC997_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC997_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC997_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC997_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC997_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC997_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC997_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC997_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC997_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC997_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC997_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC997_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC997_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC997_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC997_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC997_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC997_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC997_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC997_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC997_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC997_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC997_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC997_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC997_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC997_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC997_SET_COLOR_TARGET_C_ROP_SLICE_MAP(j) (0x0824+(j)*64) +#define NVC997_SET_COLOR_TARGET_C_ROP_SLICE_MAP_VIRTUAL_ADDRESS_MASK 31:0 + +#define NVC997_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC997_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC997_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC997_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC997_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC997_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC997_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC997_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC997_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC997_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC997_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC997_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC997_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC997_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC997_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC997_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC997_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC997_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC997_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC997_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC997_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC997_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC997_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC997_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC997_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC997_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC997_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC997_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC997_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC997_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC997_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC997_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC997_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC997_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC997_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC997_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC997_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC997_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC997_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC997_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC997_SET_STATISTICS_COUNTER 0x0d68 +#define NVC997_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC997_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC997_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC997_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC997_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC997_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC997_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC997_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC997_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC997_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC997_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC997_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC997_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC997_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC997_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC997_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC997_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVC997_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC997_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC997_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC997_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC997_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC997_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC997_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC997_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC997_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC997_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC997_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC997_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC997_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC997_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC997_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC997_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC997_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC997_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC997_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC997_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC997_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC997_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC997_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC997_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC997_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC997_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC997_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC997_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC997_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC997_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC997_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC997_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC997_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC997_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC997_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC997_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC997_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC997_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC997_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC997_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC997_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC997_SET_POLY_SMOOTH 0x0db4 +#define NVC997_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC997_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC997_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC997_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC997_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC997_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC997_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC997_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC997_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC997_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_PATCH 0x0dcc +#define NVC997_SET_PATCH_SIZE 7:0 + +#define NVC997_SET_ITERATED_BLEND 0x0dd0 +#define NVC997_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC997_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC997_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC997_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC997_SET_ZCULL_CRITERION 0x0dd8 +#define NVC997_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC997_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC997_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC997_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC997_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC997_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC997_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC997_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC997_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC997_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC997_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 +#define NVC997_PIXEL_SHADER_BARRIER_BARRIER_LOCATION 1:1 +#define NVC997_PIXEL_SHADER_BARRIER_BARRIER_LOCATION_BLOCK_BEFORE_PS 0x00000000 +#define NVC997_PIXEL_SHADER_BARRIER_BARRIER_LOCATION_BLOCK_BEFORE_PS_AND_ZTEST 0x00000001 + +#define NVC997_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC997_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC997_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC997_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC997_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC997_MME_DMA_WRITE_METHOD_BARRIER 0x0dec +#define NVC997_MME_DMA_WRITE_METHOD_BARRIER_V 0:0 + +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC997_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC997_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC997_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC997_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC997_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC997_SET_SCISSOR_ENABLE_V 0:0 +#define NVC997_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC997_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC997_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC997_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC997_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC997_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC997_SET_VPC_PERF_KNOB 0x0f14 +#define NVC997_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC997_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC997_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC997_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC997_PM_LOCAL_TRIGGER 0x0f18 +#define NVC997_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC997_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC997_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC997_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC997_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC997_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC997_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC997_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC997_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC997_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC997_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC997_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC997_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC997_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC997_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC997_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC997_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC997_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC997_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC997_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC997_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC997_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC997_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC997_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC997_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC997_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC997_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC997_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC997_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC997_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC997_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC997_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC997_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC997_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC997_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC997_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC997_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC997_SET_SAMPLE_MASK 0x0fa4 +#define NVC997_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC997_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC997_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC997_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC997_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC997_SET_CT_MRT_ENABLE 0x0fac +#define NVC997_SET_CT_MRT_ENABLE_V 0:0 +#define NVC997_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC997_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC997_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC997_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC997_SET_TIR 0x0fb4 +#define NVC997_SET_TIR_MODE 1:0 +#define NVC997_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC997_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC997_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC997_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC997_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC997_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC997_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC997_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC997_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC997_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC997_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC997_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC997_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC997_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC997_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC997_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC997_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC997_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC997_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC997_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_TIR_MODULATION 0x0fd4 +#define NVC997_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC997_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC997_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC997_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC997_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC997_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC997_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC997_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC997_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC997_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC997_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC997_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC997_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC997_SET_ZT_A 0x0fe0 +#define NVC997_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_ZT_B 0x0fe4 +#define NVC997_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_ZT_FORMAT 0x0fe8 +#define NVC997_SET_ZT_FORMAT_V 4:0 +#define NVC997_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC997_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC997_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC997_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC997_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC997_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC997_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC997_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC997_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC997_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC997_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC997_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC997_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC997_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC997_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC997_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC997_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC997_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC997_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC997_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC997_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC997_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC997_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC997_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC997_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC997_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC997_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC997_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC997_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC997_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC997_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC997_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC997_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC997_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC997_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC997_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC997_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC997_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC997_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC997_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC997_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC997_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC997_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC997_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC997_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC997_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD02 0x102c +#define NVC997_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC997_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC997_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC997_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC997_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC997_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC997_SET_SPARE_NOOP01 0x1044 +#define NVC997_SET_SPARE_NOOP01_V 31:0 + +#define NVC997_SET_SPARE_NOOP02 0x1048 +#define NVC997_SET_SPARE_NOOP02_V 31:0 + +#define NVC997_SET_SPARE_NOOP03 0x104c +#define NVC997_SET_SPARE_NOOP03_V 31:0 + +#define NVC997_SET_SPARE_NOOP04 0x1050 +#define NVC997_SET_SPARE_NOOP04_V 31:0 + +#define NVC997_SET_SPARE_NOOP05 0x1054 +#define NVC997_SET_SPARE_NOOP05_V 31:0 + +#define NVC997_SET_SPARE_NOOP06 0x1058 +#define NVC997_SET_SPARE_NOOP06_V 31:0 + +#define NVC997_SET_SPARE_NOOP07 0x105c +#define NVC997_SET_SPARE_NOOP07_V 31:0 + +#define NVC997_SET_SPARE_NOOP08 0x1060 +#define NVC997_SET_SPARE_NOOP08_V 31:0 + +#define NVC997_SET_SPARE_NOOP09 0x1064 +#define NVC997_SET_SPARE_NOOP09_V 31:0 + +#define NVC997_SET_SPARE_NOOP10 0x1068 +#define NVC997_SET_SPARE_NOOP10_V 31:0 + +#define NVC997_SET_SPARE_NOOP11 0x106c +#define NVC997_SET_SPARE_NOOP11_V 31:0 + +#define NVC997_SET_SPARE_NOOP12 0x1070 +#define NVC997_SET_SPARE_NOOP12_V 31:0 + +#define NVC997_SET_SPARE_NOOP13 0x1074 +#define NVC997_SET_SPARE_NOOP13_V 31:0 + +#define NVC997_SET_SPARE_NOOP14 0x1078 +#define NVC997_SET_SPARE_NOOP14_V 31:0 + +#define NVC997_SET_SPARE_NOOP15 0x107c +#define NVC997_SET_SPARE_NOOP15_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC997_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC997_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC997_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC997_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC997_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC997_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC997_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC997_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC997_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC997_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC997_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC997_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC997_UNBIND_ALL 0x10f4 +#define NVC997_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC997_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC997_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC997_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC997_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC997_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC997_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC997_NO_OPERATION_DATA_HI 0x110c +#define NVC997_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC997_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC997_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC997_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC997_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC997_PM_TRIGGER_END 0x1114 +#define NVC997_PM_TRIGGER_END_V 31:0 + +#define NVC997_SET_VERTEX_ID_BASE 0x1118 +#define NVC997_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC997_SET_STENCIL_COMPRESSION 0x111c +#define NVC997_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC997_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC997_SET_TIR_CONTROL 0x1130 +#define NVC997_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC997_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC997_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC997_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC997_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC997_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC997_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC997_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC997_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 +#define NVC997_SET_TIR_CONTROL_REDUCTION_MODE 2:2 +#define NVC997_SET_TIR_CONTROL_REDUCTION_MODE_AFFINITY_MAP 0x00000000 +#define NVC997_SET_TIR_CONTROL_REDUCTION_MODE_TRUNCATION 0x00000001 + +#define NVC997_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC997_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC997_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC997_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC997_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC997_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC997_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC997_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC997_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC997_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC997_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC997_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC997_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC997_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC997_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC997_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC997_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC997_FLUSH_PENDING_WRITES 0x1144 +#define NVC997_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC997_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC997_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC997_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC997_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC997_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC997_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC997_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC997_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC997_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC997_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC997_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC997_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC997_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC997_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC997_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC997_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC997_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC997_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC997_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC997_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC997_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC997_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_SCREEN_STATE_MASK 0x1204 +#define NVC997_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC997_SET_ZT_SPARSE 0x1208 +#define NVC997_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC997_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC997_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC997_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_SET_CT_SELECT 0x121c +#define NVC997_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC997_SET_CT_SELECT_TARGET0 6:4 +#define NVC997_SET_CT_SELECT_TARGET1 9:7 +#define NVC997_SET_CT_SELECT_TARGET2 12:10 +#define NVC997_SET_CT_SELECT_TARGET3 15:13 +#define NVC997_SET_CT_SELECT_TARGET4 18:16 +#define NVC997_SET_CT_SELECT_TARGET5 21:19 +#define NVC997_SET_CT_SELECT_TARGET6 24:22 +#define NVC997_SET_CT_SELECT_TARGET7 27:25 + +#define NVC997_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC997_SET_ZT_SIZE_A 0x1228 +#define NVC997_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC997_SET_ZT_SIZE_B 0x122c +#define NVC997_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC997_SET_ZT_SIZE_C 0x1230 +#define NVC997_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC997_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC997_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC997_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC997_SET_SAMPLER_BINDING 0x1234 +#define NVC997_SET_SAMPLER_BINDING_V 0:0 +#define NVC997_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC997_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC997_DRAW_AUTO 0x123c +#define NVC997_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC997_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC997_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC997_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC997_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC997_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC997_SET_BACK_END_COPY_A 0x1264 +#define NVC997_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC997_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC997_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC997_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC997_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BACK_END_COPY_B 0x1268 +#define NVC997_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC997_SET_BACK_END_COPY_C 0x126c +#define NVC997_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC997_SET_BACK_END_COPY_D 0x1270 +#define NVC997_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC997_SET_BACK_END_COPY_E 0x1274 +#define NVC997_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC997_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC997_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVC997_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC997_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC997_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC997_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC997_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC997_CLEAR_ZCULL_REGION 0x12c8 +#define NVC997_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC997_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC997_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC997_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC997_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC997_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC997_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC997_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC997_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC997_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC997_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC997_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC997_SET_DEPTH_TEST 0x12cc +#define NVC997_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC997_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_FILL_MODE 0x12d0 +#define NVC997_SET_FILL_MODE_V 31:0 +#define NVC997_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC997_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC997_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC997_SET_SHADE_MODE 0x12d4 +#define NVC997_SET_SHADE_MODE_V 31:0 +#define NVC997_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC997_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC997_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC997_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC997_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC997_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC997_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC997_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC997_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC997_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC997_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC997_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_DEPTH_WRITE 0x12e8 +#define NVC997_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC997_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_ALPHA_TEST 0x12ec +#define NVC997_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC997_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC997_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC997_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC997_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC997_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC997_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC997_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC997_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC997_D3D_SET_CULL_MODE 0x1308 +#define NVC997_D3D_SET_CULL_MODE_V 31:0 +#define NVC997_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC997_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC997_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC997_SET_DEPTH_FUNC 0x130c +#define NVC997_SET_DEPTH_FUNC_V 31:0 +#define NVC997_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC997_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC997_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC997_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC997_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC997_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC997_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC997_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC997_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC997_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC997_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC997_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC997_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC997_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC997_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC997_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC997_SET_ALPHA_REF 0x1310 +#define NVC997_SET_ALPHA_REF_V 31:0 + +#define NVC997_SET_ALPHA_FUNC 0x1314 +#define NVC997_SET_ALPHA_FUNC_V 31:0 +#define NVC997_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC997_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC997_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC997_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC997_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC997_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC997_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC997_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC997_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC997_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC997_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC997_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC997_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC997_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC997_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC997_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC997_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC997_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC997_SET_BLEND_CONST_RED 0x131c +#define NVC997_SET_BLEND_CONST_RED_V 31:0 + +#define NVC997_SET_BLEND_CONST_GREEN 0x1320 +#define NVC997_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC997_SET_BLEND_CONST_BLUE 0x1324 +#define NVC997_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC997_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC997_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC997_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC997_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC997_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC997_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC997_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC997_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC997_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC997_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BLEND_COLOR_OP 0x1340 +#define NVC997_SET_BLEND_COLOR_OP_V 31:0 +#define NVC997_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC997_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC997_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC997_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC997_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC997_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC997_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC997_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC997_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC997_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_BLEND_ALPHA_OP 0x134c +#define NVC997_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC997_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC997_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC997_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC997_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC997_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC997_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC997_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC997_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC997_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC997_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC997_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC997_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC997_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC997_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC997_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BLEND(i) (0x1360+(i)*4) +#define NVC997_SET_BLEND_ENABLE 0:0 +#define NVC997_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_STENCIL_TEST 0x1380 +#define NVC997_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC997_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_STENCIL_OP_FAIL 0x1384 +#define NVC997_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC997_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC997_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC997_SET_STENCIL_OP_ZPASS 0x138c +#define NVC997_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC997_SET_STENCIL_FUNC 0x1390 +#define NVC997_SET_STENCIL_FUNC_V 31:0 +#define NVC997_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC997_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC997_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC997_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC997_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC997_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC997_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC997_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC997_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC997_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC997_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC997_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC997_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC997_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC997_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC997_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC997_SET_STENCIL_FUNC_REF 0x1394 +#define NVC997_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC997_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC997_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC997_SET_STENCIL_MASK 0x139c +#define NVC997_SET_STENCIL_MASK_V 7:0 + +#define NVC997_SET_DRAW_AUTO_START 0x13a4 +#define NVC997_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC997_SET_PS_SATURATE 0x13a8 +#define NVC997_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC997_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC997_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC997_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC997_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC997_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC997_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC997_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC997_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC997_SET_WINDOW_ORIGIN 0x13ac +#define NVC997_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC997_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC997_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC997_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC997_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC997_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC997_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC997_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC997_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC997_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC997_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC997_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC997_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC997_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC997_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC997_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC997_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC997_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC997_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC997_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC997_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC997_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC997_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC997_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC997_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC997_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC997_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC997_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC997_STORE_ZCULL 0x1464 +#define NVC997_STORE_ZCULL_V 0:0 + +#define NVC997_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC997_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC997_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC997_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC997_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC997_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC997_LOAD_ZCULL 0x1500 +#define NVC997_LOAD_ZCULL_V 0:0 + +#define NVC997_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC997_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC997_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC997_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC997_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC997_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC997_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC997_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC997_SET_USER_CLIP_ENABLE 0x1510 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC997_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC997_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC997_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_POINT_SIZE 0x1518 +#define NVC997_SET_POINT_SIZE_V 31:0 + +#define NVC997_SET_ZCULL_STATS 0x151c +#define NVC997_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC997_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_POINT_SPRITE 0x1520 +#define NVC997_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC997_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC997_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC997_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC997_CLEAR_REPORT_VALUE 0x1530 +#define NVC997_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC997_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC997_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC997_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC997_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC997_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC997_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVC997_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC997_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC997_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_ZT_SELECT 0x1538 +#define NVC997_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC997_SET_RENDER_ENABLE_A 0x1550 +#define NVC997_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_RENDER_ENABLE_B 0x1554 +#define NVC997_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_RENDER_ENABLE_C 0x1558 +#define NVC997_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC997_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC997_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC997_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC997_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC997_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC997_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC997_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC997_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC997_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC997_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC997_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC997_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC997_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC997_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC997_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC997_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_TEX_HEADER_POOL_C 0x157c +#define NVC997_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC997_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC997_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC997_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC997_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC997_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC997_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC997_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC997_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC997_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC997_SET_SRGB_WRITE 0x15b8 +#define NVC997_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC997_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_DEPTH_BIAS 0x15bc +#define NVC997_SET_DEPTH_BIAS_V 31:0 + +#define NVC997_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC997_SET_RT_LAYER 0x15cc +#define NVC997_SET_RT_LAYER_V 15:0 +#define NVC997_SET_RT_LAYER_CONTROL 16:16 +#define NVC997_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC997_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC997_SET_ANTI_ALIAS 0x15d0 +#define NVC997_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC997_SET_EDGE_FLAG 0x15e4 +#define NVC997_SET_EDGE_FLAG_V 0:0 +#define NVC997_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC997_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC997_DRAW_INLINE_INDEX 0x15e8 +#define NVC997_DRAW_INLINE_INDEX_V 31:0 + +#define NVC997_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC997_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC997_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC997_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC997_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC997_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC997_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC997_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC997_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC997_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC997_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC997_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC997_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC997_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC997_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC997_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC997_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC997_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC997_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC997_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC997_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC997_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC997_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC997_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC997_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC997_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC997_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC997_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC997_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC997_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC997_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC997_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC997_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC997_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC997_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC997_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC997_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC997_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC997_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC997_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC997_END 0x1614 +#define NVC997_END_V 0:0 + +#define NVC997_BEGIN 0x1618 +#define NVC997_BEGIN_OP 15:0 +#define NVC997_BEGIN_OP_POINTS 0x00000000 +#define NVC997_BEGIN_OP_LINES 0x00000001 +#define NVC997_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC997_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC997_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC997_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC997_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC997_BEGIN_OP_QUADS 0x00000007 +#define NVC997_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC997_BEGIN_OP_POLYGON 0x00000009 +#define NVC997_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC997_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC997_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_BEGIN_OP_PATCH 0x0000000E +#define NVC997_BEGIN_PRIMITIVE_ID 24:24 +#define NVC997_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC997_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC997_BEGIN_INSTANCE_ID 27:26 +#define NVC997_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC997_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC997_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC997_BEGIN_SPLIT_MODE 30:29 +#define NVC997_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC997_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC997_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC997_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC997_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVC997_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC997_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_VERTEX_ID_COPY 0x161c +#define NVC997_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC997_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC997_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC997_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC997_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC997_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC997_LOAD_PRIMITIVE_ID 0x1624 +#define NVC997_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC997_SET_SHADER_BASED_CULL 0x162c +#define NVC997_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC997_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC997_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC997_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_CLASS_VERSION 0x1638 +#define NVC997_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC997_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC997_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC997_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC997_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC997_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC997_SET_DA_OUTPUT 0x164c +#define NVC997_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC997_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC997_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC997_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC997_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_POINT_CENTER_MODE 0x165c +#define NVC997_SET_POINT_CENTER_MODE_V 31:0 +#define NVC997_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC997_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC997_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC997_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC997_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC997_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC997_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC997_SET_LINE_STIPPLE 0x166c +#define NVC997_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC997_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC997_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC997_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC997_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC997_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC997_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC997_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC997_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC997_SET_PROVOKING_VERTEX 0x1684 +#define NVC997_SET_PROVOKING_VERTEX_V 0:0 +#define NVC997_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC997_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC997_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC997_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC997_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_POLYGON_STIPPLE 0x168c +#define NVC997_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC997_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_SHADER_CONTROL 0x1690 +#define NVC997_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC997_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC997_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC997_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC997_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC997_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC997_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC997_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC997_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC997_CHECK_CLASS_VERSION 0x16a0 +#define NVC997_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC997_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC997_SET_SPH_VERSION 0x16a4 +#define NVC997_SET_SPH_VERSION_CURRENT 15:0 +#define NVC997_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC997_CHECK_SPH_VERSION 0x16a8 +#define NVC997_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC997_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC997_SET_SCG_GRAPHICS_PRIORITY 0x16bc +#define NVC997_SET_SCG_GRAPHICS_PRIORITY_PRIORITY 5:0 + +#define NVC997_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS(i) (0x16c0+(i)*4) +#define NVC997_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC997_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC997_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC997_SET_AAM_VERSION 0x1790 +#define NVC997_SET_AAM_VERSION_CURRENT 15:0 +#define NVC997_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC997_CHECK_AAM_VERSION 0x1794 +#define NVC997_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC997_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC997_SET_ZT_LAYER 0x179c +#define NVC997_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC997_SET_INDEX_BUFFER_A 0x17c8 +#define NVC997_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC997_SET_INDEX_BUFFER_B 0x17cc +#define NVC997_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC997_SET_INDEX_BUFFER_E 0x17d8 +#define NVC997_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC997_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC997_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC997_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC997_SET_INDEX_BUFFER_F 0x17dc +#define NVC997_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC997_DRAW_INDEX_BUFFER 0x17e0 +#define NVC997_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC997_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC997_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC997_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC997_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC997_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC997_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC997_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC997_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC997_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC997_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC997_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC997_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC997_OGL_SET_CULL 0x1918 +#define NVC997_OGL_SET_CULL_ENABLE 0:0 +#define NVC997_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC997_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC997_OGL_SET_FRONT_FACE 0x191c +#define NVC997_OGL_SET_FRONT_FACE_V 31:0 +#define NVC997_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC997_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC997_OGL_SET_CULL_FACE 0x1920 +#define NVC997_OGL_SET_CULL_FACE_V 31:0 +#define NVC997_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC997_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC997_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC997_SET_VIEWPORT_PIXEL 0x1924 +#define NVC997_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC997_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC997_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC997_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC997_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC997_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC997_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE 17:16 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_USE_FIELD_MIN_Z_ZERO_MAX_Z_ONE 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MIN_Z_MAX_Z 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_ZERO_ONE 0x00000002 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MINUS_INF_PLUS_INF 0x00000003 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC997_SET_USER_CLIP_OP 0x1940 +#define NVC997_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC997_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC997_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC997_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC997_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC997_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC997_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC997_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC997_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC997_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC997_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC997_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC997_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC997_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC997_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC997_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC997_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC997_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC997_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC997_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC997_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC997_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC997_INVALIDATE_ZCULL 0x1958 +#define NVC997_INVALIDATE_ZCULL_V 31:0 +#define NVC997_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC997_SET_ZCULL 0x1968 +#define NVC997_SET_ZCULL_Z_ENABLE 0:0 +#define NVC997_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC997_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_ZCULL_BOUNDS 0x196c +#define NVC997_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC997_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC997_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC997_ZCULL_SYNC 0x1978 +#define NVC997_ZCULL_SYNC_V 31:0 + +#define NVC997_SET_CLIP_ID_TEST 0x197c +#define NVC997_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC997_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC997_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC997_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC997_SET_CLIP_ID 0x1984 +#define NVC997_SET_CLIP_ID_V 31:0 + +#define NVC997_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC997_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC997_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC997_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC997_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC997_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC997_SET_LOGIC_OP 0x19c4 +#define NVC997_SET_LOGIC_OP_ENABLE 0:0 +#define NVC997_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC997_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC997_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC997_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC997_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC997_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC997_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC997_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC997_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC997_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC997_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC997_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC997_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC997_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC997_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC997_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC997_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC997_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC997_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC997_SET_Z_COMPRESSION 0x19cc +#define NVC997_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC997_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC997_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC997_CLEAR_SURFACE 0x19d0 +#define NVC997_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC997_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC997_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC997_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC997_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC997_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC997_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC997_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC997_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC997_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC997_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC997_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC997_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC997_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC997_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC997_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC997_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC997_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC997_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC997_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC997_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC997_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC997_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC997_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC997_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC997_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC997_PIPE_NOP 0x1a2c +#define NVC997_PIPE_NOP_V 31:0 + +#define NVC997_SET_SPARE00 0x1a30 +#define NVC997_SET_SPARE00_V 31:0 + +#define NVC997_SET_SPARE01 0x1a34 +#define NVC997_SET_SPARE01_V 31:0 + +#define NVC997_SET_SPARE02 0x1a38 +#define NVC997_SET_SPARE02_V 31:0 + +#define NVC997_SET_SPARE03 0x1a3c +#define NVC997_SET_SPARE03_V 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC997_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC997_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC997_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC997_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC997_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC997_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC997_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC997_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC997_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC997_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC997_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC997_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_TIMESTAMP 0x00000014 +#define NVC997_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC997_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC997_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC997_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC997_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC997_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC997_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC997_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC997_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC997_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC997_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC997_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC997_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC997_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC997_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC997_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC997_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC997_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC997_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC997_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC997_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC997_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC997_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC997_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC997_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC997_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC997_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC997_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC997_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC997_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC997_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC997_SET_PIPELINE_RESERVED_B(j) (0x2004+(j)*64) +#define NVC997_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVC997_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC997_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC997_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC997_SET_PIPELINE_REGISTER_COUNT_V 8:0 + +#define NVC997_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC997_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC997_SET_PIPELINE_PROGRAM_ADDRESS_A(j) (0x2014+(j)*64) +#define NVC997_SET_PIPELINE_PROGRAM_ADDRESS_A_UPPER 7:0 + +#define NVC997_SET_PIPELINE_PROGRAM_ADDRESS_B(j) (0x2018+(j)*64) +#define NVC997_SET_PIPELINE_PROGRAM_ADDRESS_B_LOWER 31:0 + +#define NVC997_SET_PIPELINE_PROGRAM_PREFETCH(j) (0x201c+(j)*64) +#define NVC997_SET_PIPELINE_PROGRAM_PREFETCH_SIZE_IN_BLOCKS 6:0 + +#define NVC997_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC997_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC997_SET_FALCON00 0x2300 +#define NVC997_SET_FALCON00_V 31:0 + +#define NVC997_SET_FALCON01 0x2304 +#define NVC997_SET_FALCON01_V 31:0 + +#define NVC997_SET_FALCON02 0x2308 +#define NVC997_SET_FALCON02_V 31:0 + +#define NVC997_SET_FALCON03 0x230c +#define NVC997_SET_FALCON03_V 31:0 + +#define NVC997_SET_FALCON04 0x2310 +#define NVC997_SET_FALCON04_V 31:0 + +#define NVC997_SET_FALCON05 0x2314 +#define NVC997_SET_FALCON05_V 31:0 + +#define NVC997_SET_FALCON06 0x2318 +#define NVC997_SET_FALCON06_V 31:0 + +#define NVC997_SET_FALCON07 0x231c +#define NVC997_SET_FALCON07_V 31:0 + +#define NVC997_SET_FALCON08 0x2320 +#define NVC997_SET_FALCON08_V 31:0 + +#define NVC997_SET_FALCON09 0x2324 +#define NVC997_SET_FALCON09_V 31:0 + +#define NVC997_SET_FALCON10 0x2328 +#define NVC997_SET_FALCON10_V 31:0 + +#define NVC997_SET_FALCON11 0x232c +#define NVC997_SET_FALCON11_V 31:0 + +#define NVC997_SET_FALCON12 0x2330 +#define NVC997_SET_FALCON12_V 31:0 + +#define NVC997_SET_FALCON13 0x2334 +#define NVC997_SET_FALCON13_V 31:0 + +#define NVC997_SET_FALCON14 0x2338 +#define NVC997_SET_FALCON14_V 31:0 + +#define NVC997_SET_FALCON15 0x233c +#define NVC997_SET_FALCON15_V 31:0 + +#define NVC997_SET_FALCON16 0x2340 +#define NVC997_SET_FALCON16_V 31:0 + +#define NVC997_SET_FALCON17 0x2344 +#define NVC997_SET_FALCON17_V 31:0 + +#define NVC997_SET_FALCON18 0x2348 +#define NVC997_SET_FALCON18_V 31:0 + +#define NVC997_SET_FALCON19 0x234c +#define NVC997_SET_FALCON19_V 31:0 + +#define NVC997_SET_FALCON20 0x2350 +#define NVC997_SET_FALCON20_V 31:0 + +#define NVC997_SET_FALCON21 0x2354 +#define NVC997_SET_FALCON21_V 31:0 + +#define NVC997_SET_FALCON22 0x2358 +#define NVC997_SET_FALCON22_V 31:0 + +#define NVC997_SET_FALCON23 0x235c +#define NVC997_SET_FALCON23_V 31:0 + +#define NVC997_SET_FALCON24 0x2360 +#define NVC997_SET_FALCON24_V 31:0 + +#define NVC997_SET_FALCON25 0x2364 +#define NVC997_SET_FALCON25_V 31:0 + +#define NVC997_SET_FALCON26 0x2368 +#define NVC997_SET_FALCON26_V 31:0 + +#define NVC997_SET_FALCON27 0x236c +#define NVC997_SET_FALCON27_V 31:0 + +#define NVC997_SET_FALCON28 0x2370 +#define NVC997_SET_FALCON28_V 31:0 + +#define NVC997_SET_FALCON29 0x2374 +#define NVC997_SET_FALCON29_V 31:0 + +#define NVC997_SET_FALCON30 0x2378 +#define NVC997_SET_FALCON30_V 31:0 + +#define NVC997_SET_FALCON31 0x237c +#define NVC997_SET_FALCON31_V 31:0 + +#define NVC997_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC997_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC997_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC997_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC997_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC997_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC997_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC997_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC997_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC997_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC997_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC997_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC997_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC997_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC997_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC997_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC997_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC997_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC997_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC997_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC997_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC997_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC997_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC997_SET_TRAP_HANDLER_A 0x25f8 +#define NVC997_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC997_SET_TRAP_HANDLER_B 0x25fc +#define NVC997_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC997_SET_COLOR_CLAMP 0x2600 +#define NVC997_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC997_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC997_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC997_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC997_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC997_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC997_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC997_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC997_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC997_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC997_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC997_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC997_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC997_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC997_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC997_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC997_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC997_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC997_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC997_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC997_CALL_MME_MACRO_V 31:0 + +#define NVC997_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC997_CALL_MME_DATA_V 31:0 + +#endif /* _cl_ada_a_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clc9b0.h b/userspace/sdks/nv570/inc/class/clc9b0.h new file mode 100644 index 0000000..604fe53 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc9b0.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc9b0_h_ +#define _clc9b0_h_ + +#define NVC9B0_VIDEO_DECODER (0x0000C9B0) + +#endif diff --git a/userspace/sdks/nv570/inc/class/clc9b5.h b/userspace/sdks/nv570/inc/class/clc9b5.h new file mode 100644 index 0000000..d9871f8 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc9b5.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gb100_clc9b5_h__ +#define __gb100_clc9b5_h__ + +#define BLACKWELL_DMA_COPY_A (0x0000C9B5) + +#endif // __gb100_clc9b5_h__ diff --git a/userspace/sdks/nv570/inc/class/clc9b7.h b/userspace/sdks/nv570/inc/class/clc9b7.h new file mode 100644 index 0000000..6a0caef --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc9b7.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc9b7_h_ +#define _clc9b7_h_ + +#define NVC9B7_VIDEO_ENCODER (0x0000C9B7) + +#endif diff --git a/userspace/sdks/nv570/inc/class/clc9c0.h b/userspace/sdks/nv570/inc/class/clc9c0.h new file mode 100644 index 0000000..35da97f --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc9c0.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc9c0_h_ +#define _clc9c0_h_ + +#define ADA_COMPUTE_A 0xC9C0 + +#endif diff --git a/userspace/sdks/nv570/inc/class/clc9d1.h b/userspace/sdks/nv570/inc/class/clc9d1.h new file mode 100644 index 0000000..6849f96 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc9d1.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _clc9d1_h_ +#define _clc9d1_h_ + +#define NVC9D1_VIDEO_NVJPG (0x0000C9D1) + +#endif // _clc9d1_h diff --git a/userspace/sdks/nv570/inc/class/clc9fa.h b/userspace/sdks/nv570/inc/class/clc9fa.h new file mode 100644 index 0000000..6b4a20a --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clc9fa.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _clc9fa_h_ +#define _clc9fa_h_ + +#define NVC9FA_VIDEO_OFA (0x0000C9FA) + +#endif // _clc9fa_h + diff --git a/userspace/sdks/nv570/inc/class/clca6f.h b/userspace/sdks/nv570/inc/class/clca6f.h new file mode 100644 index 0000000..a41c22e --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clca6f.h @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gb202_clca6f_h__ +#define __gb202_clca6f_h__ + +typedef volatile struct Nvca6fControl_struct { + NvU32 Ignored00[0x23]; /* 0000-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored01[0x5c]; +} Nvca6fControl, BlackwellBControlGPFifo; + +#define BLACKWELL_CHANNEL_GPFIFO_B (0x0000CA6F) + +#define NVCA6F_SET_OBJECT (0x00000000) +#define NVCA6F_SEM_ADDR_LO (0x0000005c) +#define NVCA6F_SEM_ADDR_LO_OFFSET 31:2 +#define NVCA6F_SEM_ADDR_HI (0x00000060) +#define NVCA6F_SEM_ADDR_HI_OFFSET 24:0 +#define NVCA6F_SEM_PAYLOAD_LO (0x00000064) +#define NVCA6F_SEM_PAYLOAD_HI (0x00000068) +#define NVCA6F_SEM_EXECUTE (0x0000006c) +#define NVCA6F_SEM_EXECUTE_OPERATION 2:0 +#define NVCA6F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000 +#define NVCA6F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001 +#define NVCA6F_SEM_EXECUTE_RELEASE_WFI 20:20 +#define NVCA6F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000 +#define NVCA6F_SEM_EXECUTE_PAYLOAD_SIZE 24:24 +#define NVCA6F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000 + +/* GPFIFO entry format */ +#define NVCA6F_GP_ENTRY__SIZE 8 +#define NVCA6F_GP_ENTRY0_FETCH 0:0 +#define NVCA6F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVCA6F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVCA6F_GP_ENTRY0_GET 31:2 +#define NVCA6F_GP_ENTRY0_OPERAND 31:0 +#define NVCA6F_GP_ENTRY0_PB_EXTENDED_BASE_OPERAND 24:8 +#define NVCA6F_GP_ENTRY1_GET_HI 7:0 +#define NVCA6F_GP_ENTRY1_LEVEL 9:9 +#define NVCA6F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVCA6F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVCA6F_GP_ENTRY1_LENGTH 30:10 +#define NVCA6F_GP_ENTRY1_SYNC 31:31 +#define NVCA6F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVCA6F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVCA6F_GP_ENTRY1_OPCODE 7:0 +#define NVCA6F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVCA6F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVCA6F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVCA6F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 +#define NVCA6F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE 0x00000004 + +#endif // __gb202_clca6f_h__ diff --git a/userspace/sdks/nv570/inc/class/clca6fsw.h b/userspace/sdks/nv570/inc/class/clca6fsw.h new file mode 100644 index 0000000..469f54a --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clca6fsw.h @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + /* This file is *not* auto-generated. */ + +#ifndef _clca6f_sw_h_ +#define _clca6f_sw_h_ + +#define NVCA6F_NOTIFIERS_RC (0) +#define NVCA6F_NOTIFIERS_REFCNT (1) +#define NVCA6F_NOTIFIERS_NONSTALL (2) +#define NVCA6F_NOTIFIERS_EVENTBUFFER (3) +#define NVCA6F_NOTIFIERS_IDLECHANNEL (4) +#define NVCA6F_NOTIFIERS_ENDCTX (5) +#define NVCA6F_NOTIFIERS_SW (6) +#define NVCA6F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVCA6F_NOTIFIERS_REPLAYABLE_FAULT (8) +#define NVCA6F_NOTIFIERS_KEY_ROTATION (9) +#define NVCA6F_NOTIFIERS_MAXCOUNT (10) + +/* NvNotification[] fields and values */ +#define NVCA6F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVCA6F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _clca6f_sw_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clca70.h b/userspace/sdks/nv570/inc/class/clca70.h new file mode 100644 index 0000000..647051d --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clca70.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clca70.finn +// + +#define NVCA70_DISPLAY (0xca70U) /* finn: Evaluated from "NVCA70_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NVCA70_ALLOCATION_PARAMETERS_MESSAGE_ID (0xca70U) + +typedef struct NVCA70_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numDsis; // Number of DSIs in this chip/display +} NVCA70_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clca71.h b/userspace/sdks/nv570/inc/class/clca71.h new file mode 100644 index 0000000..80668b1 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clca71.h @@ -0,0 +1,186 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clca71_h_ +#define _clca71_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVCA71_DISP_SF_USER (0x000CA71) + +typedef volatile struct _clca71_tag0 { + NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x000D0FFF:0x000D0000 */ +} _NvCA71DispSfUser, NvCA71DispSfUserMap; + +#define NVCA71_SF_HDMI_INFO_CTRL(i,j) (0x000E0000-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVCA71_SF_HDMI_INFO_CTRL__SIZE_1 8 /* */ +#define NVCA71_SF_HDMI_INFO_CTRL__SIZE_2 3 /* */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x000E0000-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 8 /* */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW 9:9 /* RWIVF */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_STATUS(i) (0x000E0004-0x000E0000+(i)*1024) /* R--4A */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1 8 /* */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT 0:0 /* R-IVF */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT 0x00000000 /* R-I-V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x000E0008-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 8 /* */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x000E000C-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 8 /* */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x000E0010-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 8 /* */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x000E0014-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 8 /* */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x000E0018-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 8 /* */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW(i) (0x000E001C-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW__SIZE_1 8 /* */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL(i,j) (0x000E0130-0x000E0000+(i)*1024+(j)*8) /* RW-4A */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL__SIZE_1 8 /* */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL__SIZE_2 10 /* */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE 3:1 /* RWIVF */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_ALWAYS 0x00000000 /* RWI-V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_ONCE 0x00000001 /* RW--V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_ALWAYS 0x00000002 /* RW--V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_ONCE 0x00000003 /* RW--V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_TRIGGER 0x00000004 /* RW--V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_LOC 5:4 /* RWIVF */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_LOC_VBLANK 0x00000000 /* RWI-V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_LOC_VSYNC 0x00000001 /* RW--V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_LOC_LINE 0x00000002 /* RW--V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_OFFSET 10:6 /* RWIVF */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_SIZE 18:14 /* RWIVF */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_SIZE_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_BUSY 22:22 /* R-IVF */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_BUSY_NO 0x00000000 /* R-I-V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_BUSY_YES 0x00000001 /* R---V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_SENT 23:23 /* RWIVF */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_SENT_NO 0x00000000 /* R-I-V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_SENT_YES 0x00000001 /* R---V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_SENT_CLEAR 0x00000001 /* -W--C */ +#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG(i,j) (0x000E0134-0x000E0000+(i)*1024+(j)*8) /* RW-4A */ +#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG__SIZE_1 8 /* */ +#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG__SIZE_2 10 /* */ +#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_FID 7:0 /* RWIVF */ +#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_FID_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID 23:8 /* RWIVF */ +#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED 24:24 /* RWIVF */ +#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED_NO 0x00000000 /* RWI-V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED_YES 0x00000001 /* RW--V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN 25:25 /* RWIVF */ +#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN_NO 0x00000000 /* RWI-V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN_YES 0x00000001 /* RW--V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM 29:29 /* RWIVF */ +#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM_NO 0x00000000 /* RWI-V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM_YES 0x00000001 /* RW--V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_NEW 30:30 /* RWIVF */ +#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_NEW_INIT 0x00000000 /* R-I-V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_NEW_DONE 0x00000000 /* R---V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_NEW_PENDING 0x00000001 /* R---T */ +#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_NEW_TRIGGER 0x00000001 /* -W--T */ +#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL 31:31 /* RWIVF */ +#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL_ACT 0x00000000 /* RWI-V */ +#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL_ARM 0x00000001 /* RW--V */ +#define NVCA71_SF_GENERIC_INFOFRAME_DATA_CTRL(i) (0x000E03F0-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCA71_SF_GENERIC_INFOFRAME_DATA_CTRL__SIZE_1 8 /* */ +#define NVCA71_SF_GENERIC_INFOFRAME_DATA_CTRL_OFFSET 4:0 /* RWIVF */ +#define NVCA71_SF_GENERIC_INFOFRAME_DATA_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_GENERIC_INFOFRAME_DATA(i) (0x000E03F4-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCA71_SF_GENERIC_INFOFRAME_DATA__SIZE_1 8 /* */ +#define NVCA71_SF_GENERIC_INFOFRAME_DATA_BYTE0 7:0 /* RWIVF */ +#define NVCA71_SF_GENERIC_INFOFRAME_DATA_BYTE0_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_GENERIC_INFOFRAME_DATA_BYTE1 15:8 /* RWIVF */ +#define NVCA71_SF_GENERIC_INFOFRAME_DATA_BYTE1_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_GENERIC_INFOFRAME_DATA_BYTE2 23:16 /* RWIVF */ +#define NVCA71_SF_GENERIC_INFOFRAME_DATA_BYTE2_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_GENERIC_INFOFRAME_DATA_BYTE3 31:24 /* RWIVF */ +#define NVCA71_SF_GENERIC_INFOFRAME_DATA_BYTE3_INIT 0x00000000 /* RWI-V */ +#define NVCA71_SF_GENERIC_INFOFRAME_MISC_CTRL(i) (0x000E03F8-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCA71_SF_GENERIC_INFOFRAME_MISC_CTRL__SIZE_1 8 /* */ +#define NVCA71_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY 1:1 /* RWIVF */ +#define NVCA71_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY_HIGH 0x00000000 /* RW--V */ +#define NVCA71_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY_LOW 0x00000001 /* RWI-V */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _clca71_h_ diff --git a/userspace/sdks/nv570/inc/class/clca73.h b/userspace/sdks/nv570/inc/class/clca73.h new file mode 100644 index 0000000..d30e957 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clca73.h @@ -0,0 +1,915 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clca73_h_ +#define _clca73_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVCA73_DISP_CAPABILITIES 0xCA73 + +typedef volatile struct _clca73_tag0 { + NvU32 dispCapabilities[0x400]; +} _NvCA73DispCapabilities,NvCA73DispCapabilities_Map ; + + +#define NVCA73_SYS_CAP 0x0 /* RW-4R */ +#define NVCA73_SYS_CAP_HEAD0_EXISTS 0:0 /* RWIVF */ +#define NVCA73_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAP_HEAD1_EXISTS 1:1 /* RWIVF */ +#define NVCA73_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAP_HEAD2_EXISTS 2:2 /* RWIVF */ +#define NVCA73_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAP_HEAD3_EXISTS 3:3 /* RWIVF */ +#define NVCA73_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAP_HEAD4_EXISTS 4:4 /* RWIVF */ +#define NVCA73_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAP_HEAD5_EXISTS 5:5 /* RWIVF */ +#define NVCA73_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAP_HEAD6_EXISTS 6:6 /* RWIVF */ +#define NVCA73_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAP_HEAD7_EXISTS 7:7 /* RWIVF */ +#define NVCA73_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVCA73_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */ +#define NVCA73_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAP_SOR0_EXISTS 8:8 /* RWIVF */ +#define NVCA73_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAP_SOR1_EXISTS 9:9 /* RWIVF */ +#define NVCA73_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAP_SOR2_EXISTS 10:10 /* RWIVF */ +#define NVCA73_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAP_SOR3_EXISTS 11:11 /* RWIVF */ +#define NVCA73_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAP_SOR4_EXISTS 12:12 /* RWIVF */ +#define NVCA73_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAP_SOR5_EXISTS 13:13 /* RWIVF */ +#define NVCA73_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAP_SOR6_EXISTS 14:14 /* RWIVF */ +#define NVCA73_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAP_SOR7_EXISTS 15:15 /* RWIVF */ +#define NVCA73_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* RWIVF */ +#define NVCA73_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */ +#define NVCA73_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAP_RISCV0_EXISTS 16:16 /* RWIVF */ +#define NVCA73_SYS_CAP_RISCV0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAP_RISCV0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAP_DSI0_EXISTS 20:20 /* RWIVF */ +#define NVCA73_SYS_CAP_DSI0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAP_DSI0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAP_DSI1_EXISTS 21:21 /* RWIVF */ +#define NVCA73_SYS_CAP_DSI1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAP_DSI1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAP_DSI2_EXISTS 22:22 /* RWIVF */ +#define NVCA73_SYS_CAP_DSI2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAP_DSI2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAP_DSI3_EXISTS 23:23 /* RWIVF */ +#define NVCA73_SYS_CAP_DSI3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAP_DSI3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAP_DSI_EXISTS(i) (20+(i)):(20+(i)) /* RWIVF */ +#define NVCA73_SYS_CAP_DSI_EXISTS__SIZE_1 4 /* */ +#define NVCA73_SYS_CAP_DSI_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAP_DSI_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB 0x4 /* RW-4R */ +#define NVCA73_SYS_CAPB_WINDOW0_EXISTS 0:0 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW1_EXISTS 1:1 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW2_EXISTS 2:2 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW3_EXISTS 3:3 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW4_EXISTS 4:4 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW5_EXISTS 5:5 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW6_EXISTS 6:6 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW7_EXISTS 7:7 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW8_EXISTS 8:8 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW8_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW8_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW9_EXISTS 9:9 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW9_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW9_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW10_EXISTS 10:10 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW10_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW10_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW11_EXISTS 11:11 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW11_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW11_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW12_EXISTS 12:12 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW12_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW12_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW13_EXISTS 13:13 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW13_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW13_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW14_EXISTS 14:14 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW14_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW14_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW15_EXISTS 15:15 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW15_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW15_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW16_EXISTS 16:16 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW16_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW16_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW17_EXISTS 17:17 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW17_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW17_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW18_EXISTS 18:18 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW18_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW18_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW19_EXISTS 19:19 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW19_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW19_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW20_EXISTS 20:20 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW20_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW20_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW21_EXISTS 21:21 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW21_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW21_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW22_EXISTS 22:22 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW22_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW22_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW23_EXISTS 23:23 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW23_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW23_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW24_EXISTS 24:24 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW24_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW24_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW25_EXISTS 25:25 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW25_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW25_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW26_EXISTS 26:26 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW26_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW26_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW27_EXISTS 27:27 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW27_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW27_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW28_EXISTS 28:28 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW28_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW28_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW29_EXISTS 29:29 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW29_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW29_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW30_EXISTS 30:30 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW30_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW30_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW31_EXISTS 31:31 /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW31_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW31_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVCA73_SYS_CAPB_WINDOW_EXISTS__SIZE_1 32 /* */ +#define NVCA73_SYS_CAPB_WINDOW_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPB_WINDOW_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPC 0x20 /* RW-4R */ +#define NVCA73_SYS_CAPC_TILE0_EXISTS 0:0 /* RWIVF */ +#define NVCA73_SYS_CAPC_TILE0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE1_EXISTS 1:1 /* RWIVF */ +#define NVCA73_SYS_CAPC_TILE1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE2_EXISTS 2:2 /* RWIVF */ +#define NVCA73_SYS_CAPC_TILE2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE3_EXISTS 3:3 /* RWIVF */ +#define NVCA73_SYS_CAPC_TILE3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE4_EXISTS 4:4 /* RWIVF */ +#define NVCA73_SYS_CAPC_TILE4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE5_EXISTS 5:5 /* RWIVF */ +#define NVCA73_SYS_CAPC_TILE5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE6_EXISTS 6:6 /* RWIVF */ +#define NVCA73_SYS_CAPC_TILE6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE7_EXISTS 7:7 /* RWIVF */ +#define NVCA73_SYS_CAPC_TILE7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVCA73_SYS_CAPC_TILE_EXISTS__SIZE_1 8 /* */ +#define NVCA73_SYS_CAPC_TILE_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE0_SUPPORT_MULTI_TILE 8:8 /* RWIVF */ +#define NVCA73_SYS_CAPC_TILE0_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE0_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE1_SUPPORT_MULTI_TILE 9:9 /* RWIVF */ +#define NVCA73_SYS_CAPC_TILE1_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE1_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE2_SUPPORT_MULTI_TILE 10:10 /* RWIVF */ +#define NVCA73_SYS_CAPC_TILE2_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE2_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE3_SUPPORT_MULTI_TILE 11:11 /* RWIVF */ +#define NVCA73_SYS_CAPC_TILE3_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE3_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE4_SUPPORT_MULTI_TILE 12:12 /* RWIVF */ +#define NVCA73_SYS_CAPC_TILE4_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE4_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE5_SUPPORT_MULTI_TILE 13:13 /* RWIVF */ +#define NVCA73_SYS_CAPC_TILE5_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE5_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE6_SUPPORT_MULTI_TILE 14:14 /* RWIVF */ +#define NVCA73_SYS_CAPC_TILE6_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE6_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE7_SUPPORT_MULTI_TILE 15:15 /* RWIVF */ +#define NVCA73_SYS_CAPC_TILE7_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE7_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE(i) (8+(i)):(8+(i)) /* RWIVF */ +#define NVCA73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE__SIZE_1 8 /* */ +#define NVCA73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPC_MERGER_TILE_BUFFER_SIZE 31:16 /* RWIUF */ +#define NVCA73_SYS_CAPD 0x2c /* RW-4R */ +#define NVCA73_SYS_CAPD_NUM_TELLTALE_REGIONS 4:0 /* RWIUF */ +#define NVCA73_SYS_CAPD_NUM_FROZEN_FRAME_REGIONS 12:8 /* RWIUF */ +#define NVCA73_SYS_CAPD_NUM_ROI 20:16 /* RWIUF */ +#define NVCA73_SYS_CAPD_AE_SDP_EXISTS 30:30 /* RWIVF */ +#define NVCA73_SYS_CAPD_AE_SDP_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPD_AE_SDP_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPD_AMSS_EXISTS 31:31 /* RWIVF */ +#define NVCA73_SYS_CAPD_AMSS_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPD_AMSS_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE 0x34 /* RW-4R */ +#define NVCA73_SYS_CAPE_VIRWIN0_EXISTS 0:0 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN1_EXISTS 1:1 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN2_EXISTS 2:2 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN3_EXISTS 3:3 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN4_EXISTS 4:4 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN5_EXISTS 5:5 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN6_EXISTS 6:6 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN7_EXISTS 7:7 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN8_EXISTS 8:8 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN8_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN8_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN9_EXISTS 9:9 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN9_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN9_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN10_EXISTS 10:10 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN10_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN10_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN11_EXISTS 11:11 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN11_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN11_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN12_EXISTS 12:12 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN12_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN12_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN13_EXISTS 13:13 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN13_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN13_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN14_EXISTS 14:14 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN14_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN14_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN15_EXISTS 15:15 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN15_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN15_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN16_EXISTS 16:16 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN16_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN16_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN17_EXISTS 17:17 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN17_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN17_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN18_EXISTS 18:18 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN18_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN18_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN19_EXISTS 19:19 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN19_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN19_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN20_EXISTS 20:20 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN20_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN20_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN21_EXISTS 21:21 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN21_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN21_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN22_EXISTS 22:22 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN22_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN22_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN23_EXISTS 23:23 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN23_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN23_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN24_EXISTS 24:24 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN24_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN24_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN25_EXISTS 25:25 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN25_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN25_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN26_EXISTS 26:26 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN26_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN26_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN27_EXISTS 27:27 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN27_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN27_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN28_EXISTS 28:28 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN28_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN28_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN29_EXISTS 29:29 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN29_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN29_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN30_EXISTS 30:30 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN30_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN30_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN31_EXISTS 31:31 /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN31_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN31_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVCA73_SYS_CAPE_VIRWIN_EXISTS__SIZE_1 32 /* */ +#define NVCA73_SYS_CAPE_VIRWIN_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_SYS_CAPE_VIRWIN_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_MISC_CAPA_NUM_VMS 17:13 /* RWIUF */ +#define NVCA73_LINK_CAP 0x30 /* RW-4R */ +#define NVCA73_LINK_CAP_PHYCTRL0_EXISTS 0:0 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL1_EXISTS 1:1 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL2_EXISTS 2:2 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL3_EXISTS 3:3 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL4_EXISTS 4:4 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL5_EXISTS 5:5 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL6_EXISTS 6:6 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL7_EXISTS 7:7 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL8_EXISTS 8:8 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL8_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL8_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL9_EXISTS 9:9 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL9_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL9_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL10_EXISTS 10:10 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL10_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL10_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL11_EXISTS 11:11 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL11_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL11_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL12_EXISTS 12:12 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL12_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL12_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL13_EXISTS 13:13 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL13_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL13_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL14_EXISTS 14:14 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL14_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL14_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL15_EXISTS 15:15 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL15_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL15_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL16_EXISTS 16:16 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL16_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL16_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL17_EXISTS 17:17 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL17_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL17_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL18_EXISTS 18:18 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL18_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL18_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL19_EXISTS 19:19 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL19_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL19_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL20_EXISTS 20:20 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL20_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL20_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL21_EXISTS 21:21 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL21_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL21_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL22_EXISTS 22:22 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL22_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL22_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL23_EXISTS 23:23 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL23_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL23_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL24_EXISTS 24:24 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL24_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL24_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL25_EXISTS 25:25 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL25_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL25_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL26_EXISTS 26:26 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL26_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL26_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL27_EXISTS 27:27 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL27_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL27_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL28_EXISTS 28:28 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL28_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL28_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL29_EXISTS 29:29 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL29_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL29_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL30_EXISTS 30:30 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL30_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL30_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL31_EXISTS 31:31 /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL31_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL31_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVCA73_LINK_CAP_PHYCTRL_EXISTS__SIZE_1 32 /* */ +#define NVCA73_LINK_CAP_PHYCTRL_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCA73_LINK_CAP_PHYCTRL_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPA 0x10 /* RW-4R */ +#define NVCA73_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES 15:0 /* RWIUF */ +#define NVCA73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH 17:16 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B 0x00000002 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B 0x00000003 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_ROTATION 18:18 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_ROTATION_FALSE 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_ROTATION_TRUE 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_PLANAR 19:19 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_PLANAR_FALSE 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_PLANAR_TRUE 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_VGA 20:20 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION 21:21 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_FALSE 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_TRUE 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_MSCG 22:22 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_MSCG_FALSE 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_MSCG_TRUE 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH 23:23 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_FALSE 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_TRUE 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_MSCG_LPS 26:26 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_MSCG_LPS_FALSE 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_MSCG_LPS_TRUE 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION 31:30 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B 0x00000002 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B 0x00000003 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPC 0x18 /* RW-4R */ +#define NVCA73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE 1:0 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_32B 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_64B 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_128B 0x00000002 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_256B 0x00000003 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED 6:4 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_NONE 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_TWO 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_FOUR 0x00000002 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_EIGHT 0x00000003 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_SIXTEEN 0x00000004 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR 11:11 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_FALSE 0x00000000 /* RWI-V */ +#define NVCA73_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_TRUE 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP 12:12 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_FALSE 0x00000000 /* RWI-V */ +#define NVCA73_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_TRUE 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPC_SUPPORT_MEMPOOL_YUV_COMPRESSION 13:13 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPC_SUPPORT_MEMPOOL_YUV_COMPRESSION_FALSE 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPC_SUPPORT_MEMPOOL_YUV_COMPRESSION_TRUE 0x00000001 /* RWI-V */ +#define NVCA73_IHUB_COMMON_CAPE 0x24 /* RW-4R */ +#define NVCA73_IHUB_COMMON_CAPE_PHYWIN_BUFFER_SIZE 15:0 /* RWIUF */ +#define NVCA73_IHUB_COMMON_CAPF 0x28 /* RW-4R */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN0_SUPPORT_MULTI_TILE 0:0 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN0_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN0_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN1_SUPPORT_MULTI_TILE 1:1 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN1_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN1_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN2_SUPPORT_MULTI_TILE 2:2 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN2_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN2_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN3_SUPPORT_MULTI_TILE 3:3 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN3_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN3_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN4_SUPPORT_MULTI_TILE 4:4 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN4_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN4_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN5_SUPPORT_MULTI_TILE 5:5 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN5_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN5_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN6_SUPPORT_MULTI_TILE 6:6 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN6_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN6_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN7_SUPPORT_MULTI_TILE 7:7 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN7_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN7_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN8_SUPPORT_MULTI_TILE 8:8 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN8_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN8_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN9_SUPPORT_MULTI_TILE 9:9 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN9_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN9_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN10_SUPPORT_MULTI_TILE 10:10 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN10_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN10_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN11_SUPPORT_MULTI_TILE 11:11 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN11_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN11_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN12_SUPPORT_MULTI_TILE 12:12 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN12_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN12_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN13_SUPPORT_MULTI_TILE 13:13 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN13_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN13_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN14_SUPPORT_MULTI_TILE 14:14 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN14_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN14_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN15_SUPPORT_MULTI_TILE 15:15 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN15_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN15_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN16_SUPPORT_MULTI_TILE 16:16 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN16_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN16_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN17_SUPPORT_MULTI_TILE 17:17 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN17_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN17_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN18_SUPPORT_MULTI_TILE 18:18 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN18_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN18_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN19_SUPPORT_MULTI_TILE 19:19 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN19_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN19_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN20_SUPPORT_MULTI_TILE 20:20 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN20_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN20_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN21_SUPPORT_MULTI_TILE 21:21 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN21_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN21_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN22_SUPPORT_MULTI_TILE 22:22 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN22_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN22_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN23_SUPPORT_MULTI_TILE 23:23 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN23_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN23_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN24_SUPPORT_MULTI_TILE 24:24 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN24_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN24_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN25_SUPPORT_MULTI_TILE 25:25 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN25_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN25_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN26_SUPPORT_MULTI_TILE 26:26 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN26_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN26_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN27_SUPPORT_MULTI_TILE 27:27 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN27_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN27_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN28_SUPPORT_MULTI_TILE 28:28 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN28_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN28_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN29_SUPPORT_MULTI_TILE 29:29 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN29_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN29_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN30_SUPPORT_MULTI_TILE 30:30 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN30_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN30_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN31_SUPPORT_MULTI_TILE 31:31 /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN31_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN31_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE__SIZE_1 32 /* */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCA73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPA(i) (0x680+(i)*32) /* RW-4A */ +#define NVCA73_POSTCOMP_HDR_CAPA__SIZE_1 8 /* */ +#define NVCA73_POSTCOMP_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPA_OCSC0_PRESENT 16:16 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPA_OCSC0_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPA_OCSC0_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPA_OCSC1_PRESENT 17:17 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPA_OCSC1_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPA_OCSC1_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPA_SCLR_PRESENT 18:18 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPA_HCLPF_PRESENT 19:19 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPA_HCLPF_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPA_HCLPF_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPA_DTH_PRESENT 20:20 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPA_DTH_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPA_DTH_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPA_OSCAN_PRESENT 21:21 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPA_OSCAN_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPA_OSCAN_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPA_DSC_PRESENT 22:22 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPA_DSC_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPA_DSC_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPA_VFILTER_PRESENT 23:23 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPA_VFILTER_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPA_VFILTER_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPA_LTM_PRESENT 25:25 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPA_LTM_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPA_LTM_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPB(i) (0x684+(i)*32) /* RW-4A */ +#define NVCA73_POSTCOMP_HDR_CAPB__SIZE_1 8 /* */ +#define NVCA73_POSTCOMP_HDR_CAPB_VGA 0:0 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPB_VGA_TRUE 0x00000001 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPB_VGA_FALSE 0x00000000 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPB_OLUT_SZ 12:1 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPB_OLUT_LOGNR 15:13 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD 17:17 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPB_OLUT_DIRECT 18:18 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPB_OLUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPB_OLUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPC(i) (0x688+(i)*32) /* RW-4A */ +#define NVCA73_POSTCOMP_HDR_CAPC__SIZE_1 8 /* */ +#define NVCA73_POSTCOMP_HDR_CAPC_OCSC0_PRECISION 4:0 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPC_OCSC1_PRECISION 12:8 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP 13:13 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPC_SCLR_SF_PRECISION 20:16 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPC_SCLR_CI_PRECISION 24:21 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB 25:25 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPD(i) (0x68c+(i)*32) /* RW-4A */ +#define NVCA73_POSTCOMP_HDR_CAPD__SIZE_1 8 /* */ +#define NVCA73_POSTCOMP_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPE(i) (0x690+(i)*32) /* RW-4A */ +#define NVCA73_POSTCOMP_HDR_CAPE__SIZE_1 8 /* */ +#define NVCA73_POSTCOMP_HDR_CAPE_DSC_MAXLINEWIDTH 15:0 /* RWIUF */ +#define NVCA73_POSTCOMP_HDR_CAPE_DSC_NATIVE422 16:16 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPE_DSC_NATIVE422_TRUE 0x00000001 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPE_DSC_NATIVE422_FALSE 0x00000000 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPE_DSC_NATIVE420 17:17 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPE_DSC_NATIVE420_TRUE 0x00000001 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPE_DSC_NATIVE420_FALSE 0x00000000 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_PRESENT 18:18 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE 21:19 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_9x9x9 0x00000000 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_17x17x17 0x00000001 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_25x25x25 0x00000002 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_33x33x33 0x00000003 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_4 0x00000004 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_5 0x00000005 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_6 0x00000006 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_7 0x00000007 /* RW--V */ +#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_NUM_CURVES 23:22 /* RWIUF */ +#define NVCA73_POSTCOMP_HDR_CAPF(i) (0x694+(i)*32) /* RW-4A */ +#define NVCA73_POSTCOMP_HDR_CAPF__SIZE_1 8 /* */ +#define NVCA73_POSTCOMP_HDR_CAPF_VFILTER_MAX_PIXELS 15:0 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPF_LTM_MAX_PIXELS 31:16 /* RWIVF */ +#define NVCA73_POSTCOMP_HDR_CAPG(i) (0x698+(i)*32) /* RW-4A */ +#define NVCA73_POSTCOMP_HDR_CAPG__SIZE_1 8 /* */ +#define NVCA73_POSTCOMP_HDR_CAPG_CMI_SZ 11:0 /* RWIUF */ +#define NVCA73_POSTCOMP_HDR_CAPG_CMI_LOGNR 14:12 /* RWIUF */ +#define NVCA73_POSTCOMP_HDR_CAPG_CMO_SZ 26:15 /* RWIUF */ +#define NVCA73_POSTCOMP_HDR_CAPG_CMO_LOGNR 29:27 /* RWIUF */ +#define NVCA73_SOR_CAP(i) (0x144+(i)*8) /* RW-4A */ +#define NVCA73_SOR_CAP__SIZE_1 8 /* */ +#define NVCA73_SOR_CAP_SINGLE_LVDS_18 0:0 /* RWIVF */ +#define NVCA73_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVCA73_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVCA73_SOR_CAP_SINGLE_LVDS_24 1:1 /* RWIVF */ +#define NVCA73_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVCA73_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVCA73_SOR_CAP_DUAL_LVDS_18 2:2 /* RWIVF */ +#define NVCA73_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVCA73_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVCA73_SOR_CAP_DUAL_LVDS_24 3:3 /* RWIVF */ +#define NVCA73_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVCA73_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVCA73_SOR_CAP_DP_DUAL_MODE 4:4 /* RWIVF */ +#define NVCA73_SOR_CAP_DP_DUAL_MODE_FALSE 0x00000000 /* RW--V */ +#define NVCA73_SOR_CAP_DP_DUAL_MODE_TRUE 0x00000001 /* RW--V */ +#define NVCA73_SOR_CAP_SINGLE_TMDS_A 8:8 /* RWIVF */ +#define NVCA73_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* RW--V */ +#define NVCA73_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* RW--V */ +#define NVCA73_SOR_CAP_SINGLE_TMDS_B 9:9 /* RWIVF */ +#define NVCA73_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* RW--V */ +#define NVCA73_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* RW--V */ +#define NVCA73_SOR_CAP_DUAL_TMDS 11:11 /* RWIVF */ +#define NVCA73_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* RW--V */ +#define NVCA73_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* RW--V */ +#define NVCA73_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* RWIVF */ +#define NVCA73_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* RW--V */ +#define NVCA73_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* RW--V */ +#define NVCA73_SOR_CAP_DP_TUNNELING_OVER_USB4 15:15 /* RWIVF */ +#define NVCA73_SOR_CAP_DP_TUNNELING_OVER_USB4_FALSE 0x00000000 /* RW--V */ +#define NVCA73_SOR_CAP_DP_TUNNELING_OVER_USB4_TRUE 0x00000001 /* RW--V */ +#define NVCA73_SOR_CAP_SDI 16:16 /* RWIVF */ +#define NVCA73_SOR_CAP_SDI_FALSE 0x00000000 /* RW--V */ +#define NVCA73_SOR_CAP_SDI_TRUE 0x00000001 /* RW--V */ +#define NVCA73_SOR_CAP_DP_DUAL_MST 23:23 /* RWIVF */ +#define NVCA73_SOR_CAP_DP_DUAL_MST_FALSE 0x00000000 /* RW--V */ +#define NVCA73_SOR_CAP_DP_DUAL_MST_TRUE 0x00000001 /* RW--V */ +#define NVCA73_SOR_CAP_DP_A 24:24 /* RWIVF */ +#define NVCA73_SOR_CAP_DP_A_FALSE 0x00000000 /* RW--V */ +#define NVCA73_SOR_CAP_DP_A_TRUE 0x00000001 /* RW--V */ +#define NVCA73_SOR_CAP_DP_B 25:25 /* RWIVF */ +#define NVCA73_SOR_CAP_DP_B_FALSE 0x00000000 /* RW--V */ +#define NVCA73_SOR_CAP_DP_B_TRUE 0x00000001 /* RW--V */ +#define NVCA73_SOR_CAP_DP_INTERLACE 26:26 /* RWIVF */ +#define NVCA73_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* RW--V */ +#define NVCA73_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* RW--V */ +#define NVCA73_SOR_CAP_DP_8_LANES 27:27 /* RWIVF */ +#define NVCA73_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* RW--V */ +#define NVCA73_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* RW--V */ +#define NVCA73_SOR_CAP_HDMI_FRL 28:28 /* RWIVF */ +#define NVCA73_SOR_CAP_HDMI_FRL_FALSE 0x00000000 /* RW--V */ +#define NVCA73_SOR_CAP_HDMI_FRL_TRUE 0x00000001 /* RW--V */ +#define NVCA73_SOR_CAP_HDMI_FRL_YUV422 29:29 /* RWIVF */ +#define NVCA73_SOR_CAP_HDMI_FRL_YUV422_FALSE 0x00000000 /* RW--V */ +#define NVCA73_SOR_CAP_HDMI_FRL_YUV422_TRUE 0x00000001 /* RW--V */ +#define NVCA73_SOR_CAP_DP_128B132B 30:30 /* RWIVF */ +#define NVCA73_SOR_CAP_DP_128B132B_FALSE 0x00000000 /* RW--V */ +#define NVCA73_SOR_CAP_DP_128B132B_TRUE 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA(i) (0x780+(i)*32) /* RW-4A */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA__SIZE_1 32 /* */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH 13:10 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT 16:16 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT 17:17 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT 18:18 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT 19:19 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT 20:20 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT 21:21 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT 22:22 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT 23:23 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT 24:24 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPB(i) (0x784+(i)*32) /* RW-4A */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPB__SIZE_1 32 /* */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION 4:0 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ 9:6 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR 12:10 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD 14:14 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT 15:15 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC(i) (0x788+(i)*32) /* RW-4A */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC__SIZE_1 32 /* */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION 4:0 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_FVLUT 13:13 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_FVLUT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_FVLUT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT 15:15 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION 20:16 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP 21:21 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD(i) (0x78c+(i)*32) /* RW-4A */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD__SIZE_1 32 /* */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ 3:0 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR 6:4 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD 8:8 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT 9:9 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION 16:12 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION 20:17 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB 21:21 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA 22:22 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_TRUE 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_FALSE 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE(i) (0x790+(i)*32) /* RW-4A */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE__SIZE_1 32 /* */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION 4:0 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_FVLUT 13:13 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_FVLUT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_FVLUT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT 15:15 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION 20:16 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP 21:21 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPF(i) (0x794+(i)*32) /* RW-4A */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPF__SIZE_1 32 /* */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */ +#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */ +#define NVCA73_SOR_CLK_CAP(i) (0x608+(i)*4) /* RW-4A */ +#define NVCA73_SOR_CLK_CAP__SIZE_1 8 /* */ +#define NVCA73_SOR_CLK_CAP_DP_MAX 7:0 /* RWIUF */ +#define NVCA73_SOR_CLK_CAP_TMDS_MAX 23:16 /* RWIUF */ +#define NVCA73_SOR_CLK_CAP_LVDS_MAX 31:24 /* RWIUF */ + +#ifdef __cplusplus +}; +#endif /* extern C */ +#endif //_clca73_h_ diff --git a/userspace/sdks/nv570/inc/class/clca7a.h b/userspace/sdks/nv570/inc/class/clca7a.h new file mode 100644 index 0000000..8049aec --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clca7a.h @@ -0,0 +1,216 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clca7a__h_ +#define _clca7a__h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVCA7A_CURSOR_IMM_CHANNEL_PIO (0x0000CA7A) + +typedef volatile struct _clca7a_tag0 { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x7D]; + NvV32 Update; // 0x00000200 - 0x00000203 + NvV32 SetInterlockFlags; // 0x00000204 - 0x00000207 + NvV32 SetCursorHotSpotPointOut[2]; // 0x00000208 - 0x0000020F + NvV32 SetWindowInterlockFlags; // 0x00000210 - 0x00000213 + NvV32 Reserved02[0x3F7B]; +} NVCA7ADispCursorImmControlPio; + +#define NVCA7A_FREE (0x00000008) +#define NVCA7A_FREE_COUNT 5:0 +#define NVCA7A_UPDATE (0x00000200) +#define NVCA7A_UPDATE_RELEASE_ELV 0:0 +#define NVCA7A_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVCA7A_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVCA7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVCA7A_UPDATE_FORCE_FULLSCREEN 12:12 +#define NVCA7A_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000) +#define NVCA7A_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001) +#define NVCA7A_SET_INTERLOCK_FLAGS (0x00000204) +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVCA7A_SET_CURSOR_HOT_SPOT_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVCA7A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0 +#define NVCA7A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS (0x00000210) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clca7a_h + diff --git a/userspace/sdks/nv570/inc/class/clca7b.h b/userspace/sdks/nv570/inc/class/clca7b.h new file mode 100644 index 0000000..44f4017 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clca7b.h @@ -0,0 +1,70 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clca7b_h_ +#define _clca7b_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVCA7B_WINDOW_IMM_CHANNEL_DMA (0x0000CA7B) + +// dma opcode instructions +#define NVCA7B_DMA +#define NVCA7B_DMA_OPCODE 31:29 +#define NVCA7B_DMA_OPCODE_METHOD 0x00000000 +#define NVCA7B_DMA_OPCODE_JUMP 0x00000001 +#define NVCA7B_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVCA7B_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVCA7B_DMA_METHOD_COUNT 27:18 +#define NVCA7B_DMA_METHOD_OFFSET 15:2 +#define NVCA7B_DMA_DATA 31:0 +#define NVCA7B_DMA_DATA_NOP 0x00000000 +#define NVCA7B_DMA_JUMP_OFFSET 15:2 +#define NVCA7B_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVCA7B_PUT (0x00000000) +#define NVCA7B_PUT_PTR 13:0 +#define NVCA7B_GET (0x00000004) +#define NVCA7B_GET_PTR 13:0 +#define NVCA7B_UPDATE (0x00000200) +#define NVCA7B_UPDATE_RELEASE_ELV 0:0 +#define NVCA7B_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVCA7B_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVCA7B_UPDATE_INTERLOCK_WITH_WINDOW 1:1 +#define NVCA7B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVCA7B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVCA7B_UPDATE_FORCE_FULLSCREEN 4:4 +#define NVCA7B_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000) +#define NVCA7B_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001) +#define NVCA7B_SET_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVCA7B_SET_POINT_OUT_X 15:0 +#define NVCA7B_SET_POINT_OUT_Y 31:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clca7b_h diff --git a/userspace/sdks/nv570/inc/class/clca7d.h b/userspace/sdks/nv570/inc/class/clca7d.h new file mode 100644 index 0000000..b890f4c --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clca7d.h @@ -0,0 +1,2007 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clca7d_h_ +#define _clca7d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVCA7D_CORE_CHANNEL_DMA (0x0000CA7D) + +#define NV_DISP_NOTIFIER 0x00000000 +#define NV_DISP_NOTIFIER_SIZEOF 0x00000010 +#define NV_DISP_NOTIFIER__0 0x00000000 +#define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFIER__0_FIELD 8:8 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE 9:9 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001 +#define NV_DISP_NOTIFIER__0_R1 15:10 +#define NV_DISP_NOTIFIER__0_R2 23:16 +#define NV_DISP_NOTIFIER__0_R3 29:24 +#define NV_DISP_NOTIFIER__0_STATUS 31:30 +#define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002 +#define NV_DISP_NOTIFIER__1 0x00000001 +#define NV_DISP_NOTIFIER__1_R4 31:0 +#define NV_DISP_NOTIFIER__2 0x00000002 +#define NV_DISP_NOTIFIER__2_TIMESTAMP_LO 31:0 +#define NV_DISP_NOTIFIER__3 0x00000003 +#define NV_DISP_NOTIFIER__3_TIMESTAMP_HI 31:0 + + +// dma opcode instructions +#define NVCA7D_DMA +#define NVCA7D_DMA_OPCODE 31:29 +#define NVCA7D_DMA_OPCODE_METHOD 0x00000000 +#define NVCA7D_DMA_OPCODE_JUMP 0x00000001 +#define NVCA7D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVCA7D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVCA7D_DMA_METHOD_COUNT 27:18 +#define NVCA7D_DMA_METHOD_OFFSET 15:2 +#define NVCA7D_DMA_DATA 31:0 +#define NVCA7D_DMA_DATA_NOP 0x00000000 +#define NVCA7D_DMA_JUMP_OFFSET 15:2 +#define NVCA7D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// if cap SUPPORT_FLEXIBLE_WIN_MAPPING is FALSE, this define can be used to obtain which head a window is mapped to +#define NVC37D_WINDOW_MAPPED_TO_HEAD(w) ((w)>>1) +#define NVC37D_GET_VALID_WINDOWMASK_FOR_HEAD(h) ((1<<((h)*2)) | (1<<((h)*2+1))) + +// class methods +#define NVCA7D_PUT (0x00000000) +#define NVCA7D_PUT_PTR 13:0 +#define NVCA7D_GET (0x00000004) +#define NVCA7D_GET_PTR 13:0 +#define NVCA7D_UPDATE (0x00000200) +#define NVCA7D_UPDATE_SPECIAL_HANDLING 21:20 +#define NVCA7D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NVCA7D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NVCA7D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NVCA7D_UPDATE_SPECIAL_HANDLING_REASON 19:12 +#define NVCA7D_UPDATE_INHIBIT_INTERRUPTS 24:24 +#define NVCA7D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NVCA7D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NVCA7D_UPDATE_RELEASE_ELV 0:0 +#define NVCA7D_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVCA7D_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVCA7D_UPDATE_FORCE_FULLSCREEN 28:28 +#define NVCA7D_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000) +#define NVCA7D_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001) +#define NVCA7D_SET_NOTIFIER_CONTROL (0x0000020C) +#define NVCA7D_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVCA7D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVCA7D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVCA7D_SET_NOTIFIER_CONTROL_NOTIFY 12:12 +#define NVCA7D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NVCA7D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NVCA7D_SET_CONTROL (0x00000210) +#define NVCA7D_SET_CONTROL_FLIP_LOCK_PIN(i) ((i)+0):((i)+0) +#define NVCA7D_SET_CONTROL_FLIP_LOCK_PIN__SIZE_1 4 +#define NVCA7D_SET_CONTROL_FLIP_LOCK_PIN_DISABLE (0x00000000) +#define NVCA7D_SET_CONTROL_FLIP_LOCK_PIN_ENABLE (0x00000001) +#define NVCA7D_SET_CONTROL_FLIP_LOCK_PIN0 0:0 +#define NVCA7D_SET_CONTROL_FLIP_LOCK_PIN0_DISABLE (0x00000000) +#define NVCA7D_SET_CONTROL_FLIP_LOCK_PIN0_ENABLE (0x00000001) +#define NVCA7D_SET_CONTROL_FLIP_LOCK_PIN1 1:1 +#define NVCA7D_SET_CONTROL_FLIP_LOCK_PIN1_DISABLE (0x00000000) +#define NVCA7D_SET_CONTROL_FLIP_LOCK_PIN1_ENABLE (0x00000001) +#define NVCA7D_SET_CONTROL_FLIP_LOCK_PIN2 2:2 +#define NVCA7D_SET_CONTROL_FLIP_LOCK_PIN2_DISABLE (0x00000000) +#define NVCA7D_SET_CONTROL_FLIP_LOCK_PIN2_ENABLE (0x00000001) +#define NVCA7D_SET_CONTROL_FLIP_LOCK_PIN3 3:3 +#define NVCA7D_SET_CONTROL_FLIP_LOCK_PIN3_DISABLE (0x00000000) +#define NVCA7D_SET_CONTROL_FLIP_LOCK_PIN3_ENABLE (0x00000001) +#define NVCA7D_SET_INTERLOCK_FLAGS (0x00000218) +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+0):((i)+0) +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS (0x0000021C) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVCA7D_GET_RG_SCAN_LINE(b) (0x00000220 + (b)*0x00000004) +#define NVCA7D_GET_RG_SCAN_LINE_LINE 15:0 +#define NVCA7D_GET_RG_SCAN_LINE_VBLANK 16:16 +#define NVCA7D_GET_RG_SCAN_LINE_VBLANK_FALSE (0x00000000) +#define NVCA7D_GET_RG_SCAN_LINE_VBLANK_TRUE (0x00000001) +#define NVCA7D_SET_GET_BLANKING_CTRL(b) (0x00000240 + (b)*0x00000004) +#define NVCA7D_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NVCA7D_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NVCA7D_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NVCA7D_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NVCA7D_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NVCA7D_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) +#define NVCA7D_SET_SURFACE_ADDRESS_HI_NOTIFIER (0x00000260) +#define NVCA7D_SET_SURFACE_ADDRESS_HI_NOTIFIER_ADDRESS_HI 31:0 +#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER (0x00000264) +#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_ADDRESS_LO 31:4 +#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET 3:2 +#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_IOVA (0x00000000) +#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE 0:0 +#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_DISABLE (0x00000000) +#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_ENABLE (0x00000001) + +#define NVCA7D_SOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK 7:0 +#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVCA7D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NVCA7D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NVCA7D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NVCA7D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NVCA7D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NVCA7D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NVCA7D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NVCA7D_SOR_SET_CONTROL_PROTOCOL_HDMI_FRL (0x0000000C) +#define NVCA7D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NVCA7D_SOR_SET_CONTROL_DE_SYNC_POLARITY 16:16 +#define NVCA7D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVCA7D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVCA7D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NVCA7D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NVCA7D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NVCA7D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NVCA7D_SOR_SET_CUSTOM_REASON(a) (0x00000304 + (a)*0x00000020) +#define NVCA7D_SOR_SET_CUSTOM_REASON_CODE 31:0 +#define NVCA7D_SOR_SET_SW_SPARE_A(a) (0x00000308 + (a)*0x00000020) +#define NVCA7D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NVCA7D_SOR_SET_SW_SPARE_B(a) (0x0000030C + (a)*0x00000020) +#define NVCA7D_SOR_SET_SW_SPARE_B_CODE 31:0 + +#define NVCA7D_DSI_SET_CONTROL(a) (0x00000500 + (a)*0x00000020) +#define NVCA7D_DSI_SET_CONTROL_OWNER_MASK 7:0 +#define NVCA7D_DSI_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVCA7D_DSI_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVCA7D_DSI_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVCA7D_DSI_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVCA7D_DSI_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVCA7D_DSI_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVCA7D_DSI_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVCA7D_DSI_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVCA7D_DSI_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVCA7D_DSI_SET_CUSTOM_REASON(a) (0x00000504 + (a)*0x00000020) +#define NVCA7D_DSI_SET_CUSTOM_REASON_CODE 31:0 +#define NVCA7D_DSI_SET_SW_SPARE_A(a) (0x00000508 + (a)*0x00000020) +#define NVCA7D_DSI_SET_SW_SPARE_A_CODE 31:0 +#define NVCA7D_DSI_SET_SW_SPARE_B(a) (0x0000050C + (a)*0x00000020) +#define NVCA7D_DSI_SET_SW_SPARE_B_CODE 31:0 + +#define NVCA7D_WINDOW_SET_CONTROL(a) (0x00001000 + (a)*0x00000080) +#define NVCA7D_WINDOW_SET_CONTROL_OWNER 3:0 +#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD(i) (0x00000000 +(i)) +#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD__SIZE_1 8 +#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD0 (0x00000000) +#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD1 (0x00000001) +#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD2 (0x00000002) +#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD3 (0x00000003) +#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD4 (0x00000004) +#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD5 (0x00000005) +#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD6 (0x00000006) +#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD7 (0x00000007) +#define NVCA7D_WINDOW_SET_CONTROL_OWNER_NONE (0x0000000F) +#define NVCA7D_WINDOW_SET_CONTROL_HIDE 8:8 +#define NVCA7D_WINDOW_SET_CONTROL_HIDE_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_CONTROL_HIDE_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_CONTROL_DISABLE_PHYSICAL_FLIPS 9:9 +#define NVCA7D_WINDOW_SET_CONTROL_DISABLE_PHYSICAL_FLIPS_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_CONTROL_DISABLE_PHYSICAL_FLIPS_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_CONTROL_ALLOW_SUPERFRAME 10:10 +#define NVCA7D_WINDOW_SET_CONTROL_ALLOW_SUPERFRAME_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_CONTROL_ALLOW_SUPERFRAME_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0x00000080) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a) (0x00001008 + (a)*0x00000080) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR(a) (0x0000100C + (a)*0x00000080) +#define NVCA7D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVCA7D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a) (0x00001010 + (a)*0x00000080) +#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_MAX_PIXELS_FETCHED_PER_LINE 14:0 +#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED 16:16 +#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED 28:28 +#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS 22:20 +#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED 24:24 +#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED 30:30 +#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_LAYOUT 26:25 +#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_LAYOUT_PITCH_BLOCKLINEAR (0x00000000) +#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_LAYOUT_PITCH (0x00000001) +#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_LAYOUT_BLOCKLINEAR (0x00000002) +#define NVCA7D_WINDOW_SET_PHYSICAL(a) (0x00001014 + (a)*0x00000080) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW 31:0 +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_NONE (0x00000000) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW0 (0x00000001) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW1 (0x00000002) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW2 (0x00000004) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW3 (0x00000008) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW4 (0x00000010) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW5 (0x00000020) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW6 (0x00000040) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW7 (0x00000080) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW8 (0x00000100) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW9 (0x00000200) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW10 (0x00000400) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW11 (0x00000800) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW12 (0x00001000) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW13 (0x00002000) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW14 (0x00004000) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW15 (0x00008000) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW16 (0x00010000) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW17 (0x00020000) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW18 (0x00040000) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW19 (0x00080000) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW20 (0x00100000) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW21 (0x00200000) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW22 (0x00400000) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW23 (0x00800000) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW24 (0x01000000) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW25 (0x02000000) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW26 (0x04000000) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW27 (0x08000000) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW28 (0x10000000) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW29 (0x20000000) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW30 (0x40000000) +#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW31 (0x80000000) +#define NVCA7D_WINDOW_SET_GUEST_OVERRIDES(a) (0x00001024 + (a)*0x00000080) +#define NVCA7D_WINDOW_SET_GUEST_OVERRIDES_SET_SIZE_OUT 0:0 +#define NVCA7D_WINDOW_SET_GUEST_OVERRIDES_SET_SIZE_OUT_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_GUEST_OVERRIDES_SET_SIZE_OUT_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_CONTROL 1:1 +#define NVCA7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_CONTROL_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_CONTROL_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_CONSTANT_ALPHA 2:2 +#define NVCA7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_CONSTANT_ALPHA_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_CONSTANT_ALPHA_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_FACTOR_SELECT 3:3 +#define NVCA7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_FACTOR_SELECT_FALSE (0x00000000) +#define NVCA7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_FACTOR_SELECT_TRUE (0x00000001) +#define NVCA7D_WINDOW_SET_GUEST_SIZE_OUT(a) (0x00001028 + (a)*0x00000080) +#define NVCA7D_WINDOW_SET_GUEST_SIZE_OUT_WIDTH 15:0 +#define NVCA7D_WINDOW_SET_GUEST_SIZE_OUT_HEIGHT 31:16 +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL(a) (0x0000102C + (a)*0x00000080) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0 +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL_DEPTH 11:4 +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL_BYPASS 16:16 +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL_BYPASS_DISABLE (0x00000000) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL_BYPASS_ENABLE (0x00000001) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_CONSTANT_ALPHA(a) (0x00001030 + (a)*0x00000080) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_CONSTANT_ALPHA_K1 7:0 +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_CONSTANT_ALPHA_K2 15:8 +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT(a) (0x00001034 + (a)*0x00000080) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0 +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4 +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8 +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12 +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16 +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20 +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24 +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28 +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVCA7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) + +#define NVCA7D_HEAD_SET_PROCAMP(a) (0x00002000 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NVCA7D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NVCA7D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NVCA7D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NVCA7D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003) +#define NVCA7D_HEAD_SET_PROCAMP_CHROMA_LPF 3:3 +#define NVCA7D_HEAD_SET_PROCAMP_CHROMA_LPF_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_PROCAMP_CHROMA_LPF_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_PROCAMP_CHROMA_DOWN_V 4:4 +#define NVCA7D_HEAD_SET_PROCAMP_CHROMA_DOWN_V_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_PROCAMP_CHROMA_DOWN_V_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 28:28 +#define NVCA7D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NVCA7D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00002004 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 2:2 +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 3:3 +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 7:4 +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000000) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000001) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000002) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000003) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000004) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000005) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000006) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000007) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000008) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_444 (0x00000009) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444NP (0x0000000A) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 24:24 +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 23:12 +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN 31:26 +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN0 (0x00000000) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN1 (0x00000001) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN2 (0x00000002) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN3 (0x00000003) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN4 (0x00000004) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN5 (0x00000005) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN6 (0x00000006) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN7 (0x00000007) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN8 (0x00000008) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN9 (0x00000009) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN10 (0x0000000A) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN11 (0x0000000B) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN12 (0x0000000C) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN13 (0x0000000D) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN14 (0x0000000E) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN15 (0x0000000F) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN16 (0x00000010) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN17 (0x00000011) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN18 (0x00000012) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN19 (0x00000013) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN20 (0x00000014) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN21 (0x00000015) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN22 (0x00000016) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN23 (0x00000017) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN24 (0x00000018) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN25 (0x00000019) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN26 (0x0000001A) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN27 (0x0000001B) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN28 (0x0000001C) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN29 (0x0000001D) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN30 (0x0000001E) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN31 (0x0000001F) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_NONE (0x0000003F) +#define NVCA7D_HEAD_SET_CONTROL(a) (0x00002008 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_CONTROL_STRUCTURE 1:0 +#define NVCA7D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NVCA7D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE 2:2 +#define NVCA7D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_NORMAL (0x00000000) +#define NVCA7D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000001) +#define NVCA7D_HEAD_SET_CONTROL_YUV420PACKER 3:3 +#define NVCA7D_HEAD_SET_CONTROL_YUV420PACKER_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_CONTROL_YUV420PACKER_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_MODE 11:10 +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_MODE_NO_LOCK (0x00000000) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN 8:4 +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCKOUT_WINDOW 15:12 +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_MODE 23:22 +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_MODE_NO_LOCK (0x00000000) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN 20:16 +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN 28:24 +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_NONE (0x00000000) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000001) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000002) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000003) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000004) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000005) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000006) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000007) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000008) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000009) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x0000000A) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000B) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000C) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000D) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000E) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000F) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x00000010) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVCA7D_HEAD_SET_CONTROL_SINK_STEREO_LOCK_MODE 30:30 +#define NVCA7D_HEAD_SET_CONTROL_SINK_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_CONTROL_SINK_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_STEREO_LOCK_MODE 31:31 +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_CONTROL_SOURCE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x0000200C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00002014 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVCA7D_HEAD_SET_DITHER_CONTROL(a) (0x00002018 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NVCA7D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_DITHER_CONTROL_BITS 5:4 +#define NVCA7D_HEAD_SET_DITHER_CONTROL_BITS_TO_6_BITS (0x00000000) +#define NVCA7D_HEAD_SET_DITHER_CONTROL_BITS_TO_8_BITS (0x00000001) +#define NVCA7D_HEAD_SET_DITHER_CONTROL_BITS_TO_10_BITS (0x00000002) +#define NVCA7D_HEAD_SET_DITHER_CONTROL_BITS_TO_12_BITS (0x00000003) +#define NVCA7D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE 2:2 +#define NVCA7D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_DITHER_CONTROL_MODE 10:8 +#define NVCA7D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NVCA7D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NVCA7D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NVCA7D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NVCA7D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NVCA7D_HEAD_SET_DITHER_CONTROL_MODE_ROUND (0x00000005) +#define NVCA7D_HEAD_SET_DITHER_CONTROL_PHASE 13:12 +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x0000201C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 0:0 +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING 4:4 +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 9:8 +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NVCA7D_HEAD_SET_DISPLAY_ID(a,b) (0x00002020 + (a)*0x00000800 + (b)*0x00000004) +#define NVCA7D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00002028 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NVCA7D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR(a) (0x0000202C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVCA7D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS(a) (0x00002030 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR 2:0 +#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_NONE (0x00000000) +#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W32_H32 (0x00000001) +#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W64_H64 (0x00000002) +#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W128_H128 (0x00000003) +#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W256_H256 (0x00000004) +#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED 4:4 +#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_FALSE (0x00000000) +#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_TRUE (0x00000001) +#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_LTM_ALLOWED 5:5 +#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_LTM_ALLOWED_FALSE (0x00000000) +#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_LTM_ALLOWED_TRUE (0x00000001) +#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS 14:12 +#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED 8:8 +#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED 16:16 +#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED_FALSE (0x00000000) +#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED_TRUE (0x00000001) +#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_ELV_START 31:17 +#define NVCA7D_HEAD_SET_STALL_LOCK(a) (0x00002034 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_STALL_LOCK_ENABLE 0:0 +#define NVCA7D_HEAD_SET_STALL_LOCK_ENABLE_FALSE (0x00000000) +#define NVCA7D_HEAD_SET_STALL_LOCK_ENABLE_TRUE (0x00000001) +#define NVCA7D_HEAD_SET_STALL_LOCK_MODE 2:2 +#define NVCA7D_HEAD_SET_STALL_LOCK_MODE_CONTINUOUS (0x00000000) +#define NVCA7D_HEAD_SET_STALL_LOCK_MODE_ONE_SHOT (0x00000001) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN 8:4 +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVCA7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVCA7D_HEAD_SET_STALL_LOCK_UNSTALL_MODE 12:12 +#define NVCA7D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_CRASH_LOCK (0x00000000) +#define NVCA7D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_LINE_LOCK (0x00000001) +#define NVCA7D_HEAD_SET_STALL_LOCK_TEPOLARITY 14:14 +#define NVCA7D_HEAD_SET_STALL_LOCK_TEPOLARITY_POSITIVE_TRUE (0x00000000) +#define NVCA7D_HEAD_SET_STALL_LOCK_TEPOLARITY_NEGATIVE_TRUE (0x00000001) +#define NVCA7D_HEAD_SET_STALL_LOCK_UNSTALL_SYNC_ADVANCE 25:16 +#define NVCA7D_HEAD_SET_LOCK_CHAIN(a) (0x00002044 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_LOCK_CHAIN_POSITION 3:0 +#define NVCA7D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x00002048 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NVCA7D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NVCA7D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x0000204C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NVCA7D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NVCA7D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x00002058 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NVCA7D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NVCA7D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x0000205C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NVCA7D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NVCA7D_HEAD_SET_TILE_MASK(a) (0x00002060 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_TILE_MASK_TILE 7:0 +#define NVCA7D_HEAD_SET_TILE_MASK_TILE_NONE (0x00000000) +#define NVCA7D_HEAD_SET_TILE_MASK_TILE_TILE0 (0x00000001) +#define NVCA7D_HEAD_SET_TILE_MASK_TILE_TILE1 (0x00000002) +#define NVCA7D_HEAD_SET_TILE_MASK_TILE_TILE2 (0x00000004) +#define NVCA7D_HEAD_SET_TILE_MASK_TILE_TILE3 (0x00000008) +#define NVCA7D_HEAD_SET_TILE_MASK_TILE_TILE4 (0x00000010) +#define NVCA7D_HEAD_SET_TILE_MASK_TILE_TILE5 (0x00000020) +#define NVCA7D_HEAD_SET_TILE_MASK_TILE_TILE6 (0x00000040) +#define NVCA7D_HEAD_SET_TILE_MASK_TILE_TILE7 (0x00000080) +#define NVCA7D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_RASTER_SIZE_WIDTH 15:0 +#define NVCA7D_HEAD_SET_RASTER_SIZE_HEIGHT 31:16 +#define NVCA7D_HEAD_SET_RASTER_SYNC_END(a) (0x00002068 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NVCA7D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NVCA7D_HEAD_SET_RASTER_BLANK_END(a) (0x0000206C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NVCA7D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NVCA7D_HEAD_SET_RASTER_BLANK_START(a) (0x00002070 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NVCA7D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NVCA7D_HEAD_SET_OVERSCAN_COLOR(a) (0x00002078 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OVERSCAN_COLOR_RED_CR 9:0 +#define NVCA7D_HEAD_SET_OVERSCAN_COLOR_GREEN_Y 19:10 +#define NVCA7D_HEAD_SET_OVERSCAN_COLOR_BLUE_CB 29:20 +#define NVCA7D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR(a) (0x0000207C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_RED_CR 9:0 +#define NVCA7D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_GREEN_Y 19:10 +#define NVCA7D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_BLUE_CB 29:20 +#define NVCA7D_HEAD_SET_HDMI_CTRL(a) (0x00002080 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NVCA7D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NVCA7D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NVCA7D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NVCA7D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NVCA7D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x00002098 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 0:0 +#define NVCA7D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NVCA7D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NVCA7D_HEAD_SET_CONTROL_CURSOR(a) (0x0000209C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_FORMAT 7:0 +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x000000E9) +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x000000CF) +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_SIZE 9:8 +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 19:12 +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 27:20 +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION(a) (0x000020A0 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_K1 7:0 +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT 11:8 +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1_TIMES_SRC (0x00000005) +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT 15:12 +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_ZERO (0x00000000) +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE 16:16 +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_BLEND (0x00000000) +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_XOR (0x00000001) +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS 20:20 +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_CMI_LUT_CONTROL(a) (0x000020A4 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_CMI_LUT_CONTROL_ENABLE 0:0 +#define NVCA7D_HEAD_SET_CMI_LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_CMI_LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_CMI_LUT_CONTROL_INTERPOLATE 1:1 +#define NVCA7D_HEAD_SET_CMI_LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_CMI_LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_CMI_LUT_CONTROL_MIRROR 2:2 +#define NVCA7D_HEAD_SET_CMI_LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_CMI_LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_CMI_FP_NORM_SCALE(a) (0x000020A8 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_CMI_FP_NORM_SCALE_FPNORM 31:0 +#define NVCA7D_HEAD_SET_CMO_LUT_CONTROL(a) (0x000020AC + (a)*0x00000800) +#define NVCA7D_HEAD_SET_CMO_LUT_CONTROL_ENABLE 0:0 +#define NVCA7D_HEAD_SET_CMO_LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_CMO_LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_CMO_LUT_CONTROL_INTERPOLATE 1:1 +#define NVCA7D_HEAD_SET_CMO_LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_CMO_LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_CMO_LUT_CONTROL_MIRROR 2:2 +#define NVCA7D_HEAD_SET_CMO_LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_CMO_LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_CM3D0CONTROL(a) (0x000020B8 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_CM3D0CONTROL_MODE 0:0 +#define NVCA7D_HEAD_SET_CM3D0CONTROL_MODE_GAMUT_MAPPING (0x00000000) +#define NVCA7D_HEAD_SET_CM3D0CONTROL_MODE_PANEL_CORR (0x00000001) +#define NVCA7D_HEAD_SET_CM3D0CONTROL_ROUND 1:1 +#define NVCA7D_HEAD_SET_CM3D0CONTROL_ROUND_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_CM3D0CONTROL_ROUND_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_CM3D0CONTROL_LAST_ENTRY_ADD1 2:2 +#define NVCA7D_HEAD_SET_CM3D0CONTROL_LAST_ENTRY_ADD1_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_CM3D0CONTROL_LAST_ENTRY_ADD1_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_CM3D0CONTROL_SIZE 3:3 +#define NVCA7D_HEAD_SET_CM3D0CONTROL_SIZE_SIZE_9X9X9 (0x00000000) +#define NVCA7D_HEAD_SET_CM3D0CONTROL_SIZE_SIZE_17X17X17 (0x00000001) +#define NVCA7D_HEAD_SET_CM3D0CONTROL_RANGE_SCALE 8:6 +#define NVCA7D_HEAD_SET_CM3D0CONTROL_CONTENT_OFFSET 22:9 +#define NVCA7D_HEAD_SET_CM3D1CONTROL(a) (0x000020BC + (a)*0x00000800) +#define NVCA7D_HEAD_SET_CM3D1CONTROL_MODE 0:0 +#define NVCA7D_HEAD_SET_CM3D1CONTROL_MODE_GAMUT_MAPPING (0x00000000) +#define NVCA7D_HEAD_SET_CM3D1CONTROL_MODE_PANEL_CORR (0x00000001) +#define NVCA7D_HEAD_SET_CM3D1CONTROL_ROUND 1:1 +#define NVCA7D_HEAD_SET_CM3D1CONTROL_ROUND_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_CM3D1CONTROL_ROUND_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_CM3D1CONTROL_LAST_ENTRY_ADD1 2:2 +#define NVCA7D_HEAD_SET_CM3D1CONTROL_LAST_ENTRY_ADD1_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_CM3D1CONTROL_LAST_ENTRY_ADD1_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_CM3D1CONTROL_SIZE 3:3 +#define NVCA7D_HEAD_SET_CM3D1CONTROL_SIZE_SIZE_9X9X9 (0x00000000) +#define NVCA7D_HEAD_SET_CM3D1CONTROL_SIZE_SIZE_17X17X17 (0x00000001) +#define NVCA7D_HEAD_SET_CM3D1CONTROL_RANGE_SCALE 8:6 +#define NVCA7D_HEAD_SET_CM3D1CONTROL_CONTENT_OFFSET 22:9 +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI(a) (0x000020C0 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_HERTZ 3:0 +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_MAX(a) (0x000020C4 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_MAX_HERTZ 3:0 +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE(a,b) (0x000020C8 + (a)*0x00000800 + (b)*0x00000004) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW 15:10 +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN0 (0x00000000) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN1 (0x00000001) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN2 (0x00000002) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN3 (0x00000003) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN4 (0x00000004) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN5 (0x00000005) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN6 (0x00000006) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN7 (0x00000007) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN8 (0x00000008) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN9 (0x00000009) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN10 (0x0000000A) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN11 (0x0000000B) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN12 (0x0000000C) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN13 (0x0000000D) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN14 (0x0000000E) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN15 (0x0000000F) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN16 (0x00000010) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN17 (0x00000011) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN18 (0x00000012) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN19 (0x00000013) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN20 (0x00000014) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN21 (0x00000015) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN22 (0x00000016) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN23 (0x00000017) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN24 (0x00000018) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN25 (0x00000019) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN26 (0x0000001A) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN27 (0x0000001B) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN28 (0x0000001C) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN29 (0x0000001D) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN30 (0x0000001E) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN31 (0x0000001F) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_NONE (0x0000003F) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_INDEX 1:1 +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_ENABLE 0:0 +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_ENABLE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_ENABLE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_LOCATION_OVERRIDE 2:2 +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_LOCATION_OVERRIDE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_LOCATION_OVERRIDE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_LOCATION 9:8 +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_LOCATION_VBLANK (0x00000000) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_LOCATION_VSYNC (0x00000001) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_LOCATION_LINE (0x00000002) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_LINE_ID 30:16 +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_LINE_ID_REVERSED 31:31 +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_LINE_ID_REVERSED_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_LINE_ID_REVERSED_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_HB0OVERRIDE 4:4 +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_HB0OVERRIDE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_HB0OVERRIDE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_HB1OVERRIDE 5:5 +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_HB1OVERRIDE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_HB1OVERRIDE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_HB2OVERRIDE 6:6 +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_HB2OVERRIDE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_HB2OVERRIDE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_HB3OVERRIDE 7:7 +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_HB3OVERRIDE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_INFOFRAME_OVERRIDE_HB3OVERRIDE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_INFOFRAME_HEADER_OVERRIDE(a,b) (0x000020D0 + (a)*0x00000800 + (b)*0x00000004) +#define NVCA7D_HEAD_SET_INFOFRAME_HEADER_OVERRIDE_HB0 7:0 +#define NVCA7D_HEAD_SET_INFOFRAME_HEADER_OVERRIDE_HB1 15:8 +#define NVCA7D_HEAD_SET_INFOFRAME_HEADER_OVERRIDE_HB2 23:16 +#define NVCA7D_HEAD_SET_INFOFRAME_HEADER_OVERRIDE_HB3 31:24 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_RG_REL_SEMAPHORE(a,b) (0x00002110 + (a)*0x00000800 + (b)*0x00000004) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_RG_REL_SEMAPHORE_ADDRESS_HI 31:0 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE(a,b) (0x00002130 + (a)*0x00000800 + (b)*0x00000004) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_ADDRESS_LO 31:4 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_TARGET 3:2 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_TARGET_IOVA (0x00000000) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_ENABLE 0:0 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_ENABLE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_ENABLE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_CRC(a) (0x00002150 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_CRC_ADDRESS_HI 31:0 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC(a) (0x00002154 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_ADDRESS_LO 31:4 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET 3:2 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET_IOVA (0x00000000) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_ENABLE 0:0 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_ENABLE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_ENABLE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_OLUT(a) (0x00002158 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_OLUT_ADDRESS_HI 31:0 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT(a) (0x0000215C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_ADDRESS_LO 31:4 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET 3:2 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET_IOVA (0x00000000) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_ENABLE 0:0 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_ENABLE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_ENABLE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_CM3D0(a) (0x00002160 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_CM3D0_ADDRESS_HI 31:0 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0(a) (0x00002164 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_ADDRESS_LO 31:4 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_TARGET 3:2 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_TARGET_IOVA (0x00000000) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_ENABLE 0:0 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_ENABLE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_ENABLE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_CM3D1(a) (0x00002168 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_CM3D1_ADDRESS_HI 31:0 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1(a) (0x0000216C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_ADDRESS_LO 31:4 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_TARGET 3:2 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_TARGET_IOVA (0x00000000) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_ENABLE 0:0 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_ENABLE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_ENABLE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_CURSOR(a,b) (0x00002170 + (a)*0x00000800 + (b)*0x00000004) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_CURSOR_ADDRESS_HI 31:0 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR(a,b) (0x00002178 + (a)*0x00000800 + (b)*0x00000004) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_ADDRESS_LO 31:4 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET 3:2 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET_IOVA (0x00000000) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_KIND 1:1 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_KIND_PITCH (0x00000000) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_KIND_BLOCKLINEAR (0x00000001) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_ENABLE 0:0 +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_ENABLE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_ENABLE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_CRC_CONTROL(a) (0x00002184 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 5:0 +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_0 (0x00000000) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_1 (0x00000001) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_2 (0x00000002) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_3 (0x00000003) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_4 (0x00000004) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_5 (0x00000005) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_6 (0x00000006) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_7 (0x00000007) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_8 (0x00000008) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_9 (0x00000009) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_10 (0x0000000A) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_11 (0x0000000B) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_12 (0x0000000C) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_13 (0x0000000D) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_14 (0x0000000E) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_15 (0x0000000F) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_16 (0x00000010) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_17 (0x00000011) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_18 (0x00000012) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_19 (0x00000013) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_20 (0x00000014) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_21 (0x00000015) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_22 (0x00000016) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_23 (0x00000017) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_24 (0x00000018) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_25 (0x00000019) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_26 (0x0000001A) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_27 (0x0000001B) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_28 (0x0000001C) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_29 (0x0000001D) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_30 (0x0000001E) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_31 (0x0000001F) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000020) +#define NVCA7D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 8:8 +#define NVCA7D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NVCA7D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC 19:12 +#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_NONE (0x00000000) +#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SF (0x00000030) +#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR__SIZE_1 8 +#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR0 (0x00000050) +#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR1 (0x00000051) +#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR2 (0x00000052) +#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR3 (0x00000053) +#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR4 (0x00000054) +#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR5 (0x00000055) +#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR6 (0x00000056) +#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR7 (0x00000057) +#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC 27:20 +#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_NONE (0x00000000) +#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SF (0x00000030) +#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR__SIZE_1 8 +#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR0 (0x00000050) +#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR1 (0x00000051) +#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR2 (0x00000052) +#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR3 (0x00000053) +#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR4 (0x00000054) +#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR5 (0x00000055) +#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR6 (0x00000056) +#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR7 (0x00000057) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 9:9 +#define NVCA7D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_PRESENT_CONTROL(a) (0x0000218C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 0:0 +#define NVCA7D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NVCA7D_HEAD_SET_SW_SPARE_A(a) (0x00002194 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NVCA7D_HEAD_SET_SW_SPARE_B(a) (0x00002198 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NVCA7D_HEAD_SET_SW_SPARE_C(a) (0x0000219C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NVCA7D_HEAD_SET_SW_SPARE_D(a) (0x000021A0 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NVCA7D_HEAD_SET_DISPLAY_RATE(a) (0x000021A8 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DISPLAY_RATE_RUN_MODE 1:0 +#define NVCA7D_HEAD_SET_DISPLAY_RATE_RUN_MODE_CONTINUOUS (0x00000000) +#define NVCA7D_HEAD_SET_DISPLAY_RATE_RUN_MODE_ONE_SHOT (0x00000001) +#define NVCA7D_HEAD_SET_DISPLAY_RATE_RUN_MODE_ONE_SHOT_SELF_REFRESH (0x00000002) +#define NVCA7D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_INTERVAL 25:4 +#define NVCA7D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH 2:2 +#define NVCA7D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL(a,b) (0x000021CC + (a)*0x00000800 + (b)*0x00000004) +#define NVCA7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVCA7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVCA7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVCA7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE 14:14 +#define NVCA7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE_WRITE (0x00000000) +#define NVCA7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE_WRITE_AWAKEN (0x00000001) +#define NVCA7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE 10:10 +#define NVCA7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE_ONE_TIME (0x00000000) +#define NVCA7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE_CONTINUOUS (0x00000001) +#define NVCA7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RASTER_LINE 31:16 +#define NVCA7D_HEAD_SET_RG_REL_SEMAPHORE_VALUE(a,b) (0x000021EC + (a)*0x00000800 + (b)*0x00000004) +#define NVCA7D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_VALUE 31:0 +#define NVCA7D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE(a) (0x00002214 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVCA7D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVCA7D_HEAD_SET_MIN_FRAME_IDLE(a) (0x00002218 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_MIN_FRAME_IDLE_LEADING_RASTER_LINES 14:0 +#define NVCA7D_HEAD_SET_MIN_FRAME_IDLE_TRAILING_RASTER_LINES 30:16 +#define NVCA7D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED(a) (0x00002220 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED_ALPHA 7:0 +#define NVCA7D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED_RED 31:16 +#define NVCA7D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE(a) (0x00002224 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE_GREEN 15:0 +#define NVCA7D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE_BLUE 31:16 +#define NVCA7D_HEAD_SET_CURSOR_COLOR_NORM_SCALE(a) (0x00002228 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_CURSOR_COLOR_NORM_SCALE_VALUE 15:0 +#define NVCA7D_HEAD_SET_XOR_BLEND_FACTOR(a) (0x0000222C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_XOR_BLEND_FACTOR_LOG2PEAK_LUMINANCE 3:0 +#define NVCA7D_HEAD_SET_XOR_BLEND_FACTOR_S1 16:4 +#define NVCA7D_HEAD_SET_XOR_BLEND_FACTOR_S2 30:18 +#define NVCA7D_HEAD_SET_CLAMP_RANGE_GREEN(a) (0x00002238 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_CLAMP_RANGE_GREEN_LOW 11:0 +#define NVCA7D_HEAD_SET_CLAMP_RANGE_GREEN_HIGH 27:16 +#define NVCA7D_HEAD_SET_CLAMP_RANGE_RED_BLUE(a) (0x0000223C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_CLAMP_RANGE_RED_BLUE_LOW 11:0 +#define NVCA7D_HEAD_SET_CLAMP_RANGE_RED_BLUE_HIGH 27:16 +#define NVCA7D_HEAD_SET_OCSC0CONTROL(a) (0x00002240 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC0CONTROL_ENABLE 0:0 +#define NVCA7D_HEAD_SET_OCSC0CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_OCSC0CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_OCSC0COEFFICIENT_C00(a) (0x00002244 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC0COEFFICIENT_C00_VALUE 20:0 +#define NVCA7D_HEAD_SET_OCSC0COEFFICIENT_C01(a) (0x00002248 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC0COEFFICIENT_C01_VALUE 20:0 +#define NVCA7D_HEAD_SET_OCSC0COEFFICIENT_C02(a) (0x0000224C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC0COEFFICIENT_C02_VALUE 20:0 +#define NVCA7D_HEAD_SET_OCSC0COEFFICIENT_C03(a) (0x00002250 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC0COEFFICIENT_C03_VALUE 20:0 +#define NVCA7D_HEAD_SET_OCSC0COEFFICIENT_C10(a) (0x00002254 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC0COEFFICIENT_C10_VALUE 20:0 +#define NVCA7D_HEAD_SET_OCSC0COEFFICIENT_C11(a) (0x00002258 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC0COEFFICIENT_C11_VALUE 20:0 +#define NVCA7D_HEAD_SET_OCSC0COEFFICIENT_C12(a) (0x0000225C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC0COEFFICIENT_C12_VALUE 20:0 +#define NVCA7D_HEAD_SET_OCSC0COEFFICIENT_C13(a) (0x00002260 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC0COEFFICIENT_C13_VALUE 20:0 +#define NVCA7D_HEAD_SET_OCSC0COEFFICIENT_C20(a) (0x00002264 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC0COEFFICIENT_C20_VALUE 20:0 +#define NVCA7D_HEAD_SET_OCSC0COEFFICIENT_C21(a) (0x00002268 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC0COEFFICIENT_C21_VALUE 20:0 +#define NVCA7D_HEAD_SET_OCSC0COEFFICIENT_C22(a) (0x0000226C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC0COEFFICIENT_C22_VALUE 20:0 +#define NVCA7D_HEAD_SET_OCSC0COEFFICIENT_C23(a) (0x00002270 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC0COEFFICIENT_C23_VALUE 20:0 +#define NVCA7D_HEAD_SET_OLUT_CONTROL(a) (0x00002280 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OLUT_CONTROL_INTERPOLATE 0:0 +#define NVCA7D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_OLUT_CONTROL_MIRROR 1:1 +#define NVCA7D_HEAD_SET_OLUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_OLUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_OLUT_CONTROL_MODE 3:2 +#define NVCA7D_HEAD_SET_OLUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVCA7D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVCA7D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVCA7D_HEAD_SET_OLUT_CONTROL_SIZE 18:8 +#define NVCA7D_HEAD_SET_OLUT_CONTROL_DIRECT_ROUND 4:4 +#define NVCA7D_HEAD_SET_OLUT_CONTROL_DIRECT_ROUND_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_OLUT_CONTROL_DIRECT_ROUND_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_OLUT_CONTROL_LEVEL 25:20 +#define NVCA7D_HEAD_SET_OLUT_CONTROL_SEGMENT_SIZE_BITS 5:5 +#define NVCA7D_HEAD_SET_OLUT_CONTROL_SEGMENT_SIZE_BITS_SIZE_3BITS (0x00000000) +#define NVCA7D_HEAD_SET_OLUT_CONTROL_SEGMENT_SIZE_BITS_SIZE_4BITS (0x00000001) +#define NVCA7D_HEAD_SET_OLUT_FP_NORM_SCALE(a) (0x00002284 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OLUT_FP_NORM_SCALE_VALUE 31:0 +#define NVCA7D_HEAD_SET_OCSC1CONTROL(a) (0x0000229C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC1CONTROL_ENABLE 0:0 +#define NVCA7D_HEAD_SET_OCSC1CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_OCSC1CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_OCSC1COEFFICIENT_C00(a) (0x000022A0 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC1COEFFICIENT_C00_VALUE 20:0 +#define NVCA7D_HEAD_SET_OCSC1COEFFICIENT_C01(a) (0x000022A4 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC1COEFFICIENT_C01_VALUE 20:0 +#define NVCA7D_HEAD_SET_OCSC1COEFFICIENT_C02(a) (0x000022A8 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC1COEFFICIENT_C02_VALUE 20:0 +#define NVCA7D_HEAD_SET_OCSC1COEFFICIENT_C03(a) (0x000022AC + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC1COEFFICIENT_C03_VALUE 20:0 +#define NVCA7D_HEAD_SET_OCSC1COEFFICIENT_C10(a) (0x000022B0 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC1COEFFICIENT_C10_VALUE 20:0 +#define NVCA7D_HEAD_SET_OCSC1COEFFICIENT_C11(a) (0x000022B4 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC1COEFFICIENT_C11_VALUE 20:0 +#define NVCA7D_HEAD_SET_OCSC1COEFFICIENT_C12(a) (0x000022B8 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC1COEFFICIENT_C12_VALUE 20:0 +#define NVCA7D_HEAD_SET_OCSC1COEFFICIENT_C13(a) (0x000022BC + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC1COEFFICIENT_C13_VALUE 20:0 +#define NVCA7D_HEAD_SET_OCSC1COEFFICIENT_C20(a) (0x000022C0 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC1COEFFICIENT_C20_VALUE 20:0 +#define NVCA7D_HEAD_SET_OCSC1COEFFICIENT_C21(a) (0x000022C4 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC1COEFFICIENT_C21_VALUE 20:0 +#define NVCA7D_HEAD_SET_OCSC1COEFFICIENT_C22(a) (0x000022C8 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC1COEFFICIENT_C22_VALUE 20:0 +#define NVCA7D_HEAD_SET_OCSC1COEFFICIENT_C23(a) (0x000022CC + (a)*0x00000800) +#define NVCA7D_HEAD_SET_OCSC1COEFFICIENT_C23_VALUE 20:0 +#define NVCA7D_HEAD_SET_HEAD_POSITION(a) (0x000022D0 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_HEAD_POSITION_X 2:0 +#define NVCA7D_HEAD_SET_HEAD_POSITION_Y 6:4 +#define NVCA7D_HEAD_SET_DSC_CONTROL(a) (0x000022D4 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_CONTROL_ENABLE 0:0 +#define NVCA7D_HEAD_SET_DSC_CONTROL_ENABLE_FALSE (0x00000000) +#define NVCA7D_HEAD_SET_DSC_CONTROL_ENABLE_TRUE (0x00000001) +#define NVCA7D_HEAD_SET_DSC_CONTROL_AUTO_RESET 3:3 +#define NVCA7D_HEAD_SET_DSC_CONTROL_AUTO_RESET_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_DSC_CONTROL_AUTO_RESET_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION 4:4 +#define NVCA7D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET 5:5 +#define NVCA7D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET_FALSE (0x00000000) +#define NVCA7D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET_TRUE (0x00000001) +#define NVCA7D_HEAD_SET_DSC_CONTROL_FLATNESS_DET_THRESH 15:6 +#define NVCA7D_HEAD_SET_DSC_PPS_CONTROL(a) (0x000022D8 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_CONTROL_ENABLE 0:0 +#define NVCA7D_HEAD_SET_DSC_PPS_CONTROL_ENABLE_FALSE (0x00000000) +#define NVCA7D_HEAD_SET_DSC_PPS_CONTROL_ENABLE_TRUE (0x00000001) +#define NVCA7D_HEAD_SET_DSC_PPS_CONTROL_LOCATION 2:1 +#define NVCA7D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_VBLANK (0x00000000) +#define NVCA7D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_VSYNC (0x00000001) +#define NVCA7D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_LINE (0x00000002) +#define NVCA7D_HEAD_SET_DSC_PPS_CONTROL_SIZE 10:3 +#define NVCA7D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY 11:11 +#define NVCA7D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVCA7D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY_ONCE (0x00000001) +#define NVCA7D_HEAD_SET_DSC_PPS_CONTROL_LINE_ID 26:12 +#define NVCA7D_HEAD_SET_DSC_PPS_CONTROL_LINE_ID_REVERSED 27:27 +#define NVCA7D_HEAD_SET_DSC_PPS_CONTROL_LINE_ID_REVERSED_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_DSC_PPS_CONTROL_LINE_ID_REVERSED_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_DSC_PPS_HEAD(a) (0x000022DC + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_HEAD_BYTE0 7:0 +#define NVCA7D_HEAD_SET_DSC_PPS_HEAD_BYTE1 15:8 +#define NVCA7D_HEAD_SET_DSC_PPS_HEAD_BYTE2 23:16 +#define NVCA7D_HEAD_SET_DSC_PPS_HEAD_BYTE3 31:24 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA0(a) (0x000022E0 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA0_DSC_VERSION_MINOR 3:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA0_DSC_VERSION_MAJOR 7:4 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA0_PPS_IDENTIFIER 15:8 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA0_RESERVED 23:16 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA0_LINEBUF_DEPTH 27:24 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA0_BITS_PER_COMPONENT 31:28 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA1(a) (0x000022E4 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA1_BITS_PER_PIXEL_HIGH 1:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA1_VBR_ENABLE 2:2 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA1_SIMPLE422 3:3 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA1_CONVERT_RGB 4:4 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA1_BLOCK_PRED_ENABLE 5:5 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA1_RESERVED 7:6 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA1_BITS_PER_PIXEL_LOW 15:8 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA1_PIC_HEIGHT_HIGH 23:16 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA1_PIC_HEIGHT_LOW 31:24 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA2(a) (0x000022E8 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA2_PIC_WIDTH_HIGH 7:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA2_PIC_WIDTH_LOW 15:8 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA2_SLICE_HEIGHT_HIGH 23:16 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA2_SLICE_HEIGHT_LOW 31:24 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA3(a) (0x000022EC + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA3_SLICE_WIDTH_HIGH 7:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA3_SLICE_WIDTH_LOW 15:8 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA3_CHUNK_SIZE_HIGH 23:16 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA3_CHUNK_SIZE_LOW 31:24 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA4(a) (0x000022F0 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA4_INITIAL_XMIT_DELAY_HIGH 1:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA4_RESERVED 7:2 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA4_INITIAL_XMIT_DELAY_LOW 15:8 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA4_INITIAL_DEC_DELAY_HIGH 23:16 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA4_INITIAL_DEC_DELAY_LOW 31:24 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA5(a) (0x000022F4 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA5_RESERVED0 7:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA5_INITIAL_SCALE_VALUE 13:8 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA5_RESERVED1 15:14 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA5_SCALE_INCREMENT_INTERVAL_HIGH 23:16 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA5_SCALE_INCREMENT_INTERVAL_LOW 31:24 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA6(a) (0x000022F8 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA6_SCALE_DECREMENT_INTERVAL_HIGH 3:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA6_RESERVED0 7:4 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA6_SCALE_DECREMENT_INTERVAL_LOW 15:8 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA6_RESERVED1 23:16 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA6_FIRST_LINE_BPG_OFFSET 28:24 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA6_RESERVED2 31:29 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA7(a) (0x000022FC + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA7_NFL_BPG_OFFSET_HIGH 7:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA7_NFL_BPG_OFFSET_LOW 15:8 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA7_SLICE_BPG_OFFSET_HIGH 23:16 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA7_SLICE_BPG_OFFSET_LOW 31:24 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA8(a) (0x00002300 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA8_INITIAL_OFFSET_HIGH 7:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA8_INITIAL_OFFSET_LOW 15:8 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA8_FINAL_OFFSET_HIGH 23:16 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA8_FINAL_OFFSET_LOW 31:24 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA9(a) (0x00002304 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA9_FLATNESS_MIN_QP 4:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA9_RESERVED0 7:5 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA9_FLATNESS_MAX_QP 12:8 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA9_RESERVED1 15:13 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA9_RC_MODEL_SIZE_HIGH 23:16 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA9_RC_MODEL_SIZE_LOW 31:24 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA10(a) (0x00002308 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA10_RC_EDGE_FACTOR 3:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA10_RESERVED0 7:4 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA10_RC_QUANT_INCR_LIMIT0 12:8 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA10_RESERVED1 15:13 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA10_RC_QUANT_INCR_LIMIT1 20:16 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA10_RESERVED2 23:21 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA10_RC_TGT_OFFSET_LO 27:24 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA10_RC_TGT_OFFSET_HI 31:28 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA11(a) (0x0000230C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH0 7:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH1 15:8 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH2 23:16 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH3 31:24 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA12(a) (0x00002310 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH4 7:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH5 15:8 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH6 23:16 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH7 31:24 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA13(a) (0x00002314 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH8 7:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH9 15:8 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH10 23:16 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH11 31:24 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA14(a) (0x00002318 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA14_RC_BUF_THRESH12 7:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA14_RC_BUF_THRESH13 15:8 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MAX_QP_HIGH0 18:16 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MIN_QP0 23:19 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_BPG_OFFSET0 29:24 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MAX_QP_LOW0 31:30 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA15(a) (0x0000231C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_HIGH1 2:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MIN_QP1 7:3 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_BPG_OFFSET1 13:8 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_LOW1 15:14 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_HIGH2 18:16 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MIN_QP2 23:19 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_BPG_OFFSET2 29:24 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_LOW2 31:30 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA16(a) (0x00002320 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_HIGH3 2:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MIN_QP3 7:3 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_BPG_OFFSET3 13:8 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_LOW3 15:14 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_HIGH4 18:16 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MIN_QP4 23:19 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_BPG_OFFSET4 29:24 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_LOW4 31:30 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA17(a) (0x00002324 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_HIGH5 2:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MIN_QP5 7:3 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_BPG_OFFSET5 13:8 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_LOW5 15:14 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_HIGH6 18:16 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MIN_QP6 23:19 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_BPG_OFFSET6 29:24 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_LOW6 31:30 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA18(a) (0x00002328 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_HIGH7 2:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MIN_QP7 7:3 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_BPG_OFFSET7 13:8 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_LOW7 15:14 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_HIGH8 18:16 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MIN_QP8 23:19 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_BPG_OFFSET8 29:24 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_LOW8 31:30 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA19(a) (0x0000232C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_HIGH9 2:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MIN_QP9 7:3 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_BPG_OFFSET9 13:8 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_LOW9 15:14 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_HIGH10 18:16 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MIN_QP10 23:19 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_BPG_OFFSET10 29:24 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_LOW10 31:30 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA20(a) (0x00002330 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_HIGH11 2:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MIN_QP11 7:3 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_BPG_OFFSET11 13:8 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_LOW11 15:14 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_HIGH12 18:16 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MIN_QP12 23:19 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_BPG_OFFSET12 29:24 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_LOW12 31:30 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA21(a) (0x00002334 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_HIGH13 2:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MIN_QP13 7:3 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_BPG_OFFSET13 13:8 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_LOW13 15:14 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_HIGH14 18:16 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MIN_QP14 23:19 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_BPG_OFFSET14 29:24 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_LOW14 31:30 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA22(a) (0x00002338 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA22_NATIVE422 0:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA22_NATIVE420 1:1 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA22_RESERVED0 7:2 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA22_SECOND_LINE_BPG_OFFSET 12:8 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA22_RESERVED1 15:13 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA22_NSL_BPG_OFFSET_HIGH 23:16 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA22_NSL_BPG_OFFSETLOW 31:24 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA23(a) (0x0000233C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA23_SECOND_LINE_OFFSET_ADJ_HIGH 7:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA23_SECOND_LINE_OFFSET_ADJ_LOW 15:8 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA23_RESERVED 31:16 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA24(a) (0x00002340 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA24_RESERVED 31:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA25(a) (0x00002344 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA25_RESERVED 31:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA26(a) (0x00002348 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA26_RESERVED 31:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA27(a) (0x0000234C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA27_RESERVED 31:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA28(a) (0x00002350 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA28_RESERVED 31:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA29(a) (0x00002354 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA29_RESERVED 31:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA30(a) (0x00002358 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA30_RESERVED 31:0 +#define NVCA7D_HEAD_SET_DSC_PPS_DATA31(a) (0x0000235C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DSC_PPS_DATA31_RESERVED 31:0 +#define NVCA7D_HEAD_SET_RASTER_HBLANK_DELAY(a) (0x00002364 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_RASTER_HBLANK_DELAY_BLANK_START 15:0 +#define NVCA7D_HEAD_SET_RASTER_HBLANK_DELAY_BLANK_END 31:16 +#define NVCA7D_HEAD_SET_HDMI_DSC_HCACTIVE(a) (0x00002368 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_HDMI_DSC_HCACTIVE_BYTES 15:0 +#define NVCA7D_HEAD_SET_HDMI_DSC_HCACTIVE_TRI_BYTES 31:16 +#define NVCA7D_HEAD_SET_HDMI_DSC_HCBLANK(a) (0x0000236C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_HDMI_DSC_HCBLANK_WIDTH 15:0 +#define NVCA7D_HEAD_SW_RESERVED(a,b) (0x00002370 + (a)*0x00000800 + (b)*0x00000004) +#define NVCA7D_HEAD_SW_RESERVED_VALUE 31:0 +#define NVCA7D_HEAD_SET_DP_CTRL(a) (0x0000237C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DP_CTRL_EFFECTIVE_BITS_PER_PIXEL_ADJ 9:0 +#define NVCA7D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_HI(a,b) (0x00002380 + (a)*0x00000800 + (b)*0x00000004) +#define NVCA7D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_HI_VALUE 31:0 +#define NVCA7D_HEAD_SET_HEAD_INFOFRAME(a) (0x000023A0 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_HEAD_INFOFRAME_FID 7:0 +#define NVCA7D_HEAD_SET_HEAD_INFOFRAME_EN 16:16 +#define NVCA7D_HEAD_SET_HEAD_INFOFRAME_EN_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_HEAD_INFOFRAME_EN_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_INFOFRAME_CTRL(a) (0x000023A4 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_INFOFRAME_CTRL_MODE 1:0 +#define NVCA7D_HEAD_SET_INFOFRAME_CTRL_MODE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_INFOFRAME_CTRL_MODE_EMP_VTEM_QMS (0x00000001) +#define NVCA7D_HEAD_SET_INFOFRAME_CTRL_MODE_EMP_OTHERS (0x00000002) +#define NVCA7D_HEAD_SET_INFOFRAME_CTRL_FREQUENCY 12:12 +#define NVCA7D_HEAD_SET_INFOFRAME_CTRL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVCA7D_HEAD_SET_INFOFRAME_CTRL_FREQUENCY_ONCE (0x00000001) +#define NVCA7D_HEAD_SET_INFOFRAME_CTRL_LOCATION 5:4 +#define NVCA7D_HEAD_SET_INFOFRAME_CTRL_LOCATION_VBLANK (0x00000000) +#define NVCA7D_HEAD_SET_INFOFRAME_CTRL_LOCATION_VSYNC (0x00000001) +#define NVCA7D_HEAD_SET_INFOFRAME_CTRL_LOCATION_LINE (0x00000002) +#define NVCA7D_HEAD_SET_INFOFRAME_CTRL_LINE_ID 30:16 +#define NVCA7D_HEAD_SET_INFOFRAME_CTRL_LINE_ID_REVERSED 31:31 +#define NVCA7D_HEAD_SET_INFOFRAME_CTRL_LINE_ID_REVERSED_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_INFOFRAME_CTRL_LINE_ID_REVERSED_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_INFOFRAME_CTRL_MTD_STATE_CTRL 14:14 +#define NVCA7D_HEAD_SET_INFOFRAME_CTRL_MTD_STATE_CTRL_ACTIVE (0x00000000) +#define NVCA7D_HEAD_SET_INFOFRAME_CTRL_MTD_STATE_CTRL_ARM (0x00000001) +#define NVCA7D_HEAD_SET_INFOFRAME_HEADER(a) (0x000023A8 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_INFOFRAME_HEADER_HB0 7:0 +#define NVCA7D_HEAD_SET_INFOFRAME_HEADER_HB1 15:8 +#define NVCA7D_HEAD_SET_INFOFRAME_HEADER_HB2 23:16 +#define NVCA7D_HEAD_SET_INFOFRAME_HEADER_HB3 31:24 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA0(a) (0x000023AC + (a)*0x00000800) +#define NVCA7D_HEAD_SET_INFOFRAME_DATA0_DB0 7:0 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA0_DB1 15:8 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA0_DB2 23:16 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA0_DB3 31:24 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA1(a) (0x000023B0 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_INFOFRAME_DATA1_DB4 7:0 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA1_DB5 15:8 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA1_DB6 23:16 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA1_DB7 31:24 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA2(a) (0x000023B4 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_INFOFRAME_DATA2_DB8 7:0 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA2_DB9 15:8 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA2_DB10 23:16 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA2_DB11 31:24 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA3(a) (0x000023B8 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_INFOFRAME_DATA3_DB12 7:0 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA3_DB13 15:8 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA3_DB14 23:16 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA3_DB15 31:24 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA4(a) (0x000023BC + (a)*0x00000800) +#define NVCA7D_HEAD_SET_INFOFRAME_DATA4_DB16 7:0 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA4_DB17 15:8 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA4_DB18 23:16 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA4_DB19 31:24 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA5(a) (0x000023C0 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_INFOFRAME_DATA5_DB20 7:0 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA5_DB21 15:8 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA5_DB22 23:16 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA5_DB23 31:24 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA6(a) (0x000023C4 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_INFOFRAME_DATA6_DB24 7:0 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA6_DB25 15:8 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA6_DB26 23:16 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA6_DB27 31:24 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA7(a) (0x000023C8 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_INFOFRAME_DATA7_DB28 7:0 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA7_DB29 15:8 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA7_DB30 23:16 +#define NVCA7D_HEAD_SET_INFOFRAME_DATA7_DB31 31:24 +#define NVCA7D_HEAD_SET_RASTER_SIZE_FRACTION(a) (0x000023CC + (a)*0x00000800) +#define NVCA7D_HEAD_SET_RASTER_SIZE_FRACTION_HEIGHT 15:0 +#define NVCA7D_HEAD_SET_LTM_CONTROL(a) (0x000023D0 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_LTM_CONTROL_ENABLE 0:0 +#define NVCA7D_HEAD_SET_LTM_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_LTM_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_LTM_CONTROL_MODE 1:1 +#define NVCA7D_HEAD_SET_LTM_CONTROL_MODE_TMO (0x00000000) +#define NVCA7D_HEAD_SET_LTM_CONTROL_MODE_LTM (0x00000001) +#define NVCA7D_HEAD_SET_LTM_CONTROL_TONE_SELECT 2:2 +#define NVCA7D_HEAD_SET_LTM_CONTROL_TONE_SELECT_INTENSITY (0x00000000) +#define NVCA7D_HEAD_SET_LTM_CONTROL_TONE_SELECT_CDB (0x00000001) +#define NVCA7D_HEAD_SET_LTM_CONTROL_SKIN_TONE_ENABLE 3:3 +#define NVCA7D_HEAD_SET_LTM_CONTROL_SKIN_TONE_ENABLE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_LTM_CONTROL_SKIN_TONE_ENABLE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_LTM_CONTROL_LUT_INTERPOLATE 4:4 +#define NVCA7D_HEAD_SET_LTM_CONTROL_LUT_INTERPOLATE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_LTM_CONTROL_LUT_INTERPOLATE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT8 5:5 +#define NVCA7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT8_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT8_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT10 6:6 +#define NVCA7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT10_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT10_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT_ROUND 7:7 +#define NVCA7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT_ROUND_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT_ROUND_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_LTM_CONTROL_HIST_SOURCE 9:8 +#define NVCA7D_HEAD_SET_LTM_CONTROL_HIST_SOURCE_MAX_RGB (0x00000000) +#define NVCA7D_HEAD_SET_LTM_CONTROL_HIST_SOURCE_LIN_I (0x00000001) +#define NVCA7D_HEAD_SET_LTM_CONTROL_HIST_SOURCE_PQI (0x00000002) +#define NVCA7D_HEAD_SET_LTM_CONTROL_HIST_SOURCE_CDB (0x00000003) +#define NVCA7D_HEAD_SET_LTM_CONTROL_HIST_RANGE 11:10 +#define NVCA7D_HEAD_SET_LTM_CONTROL_HIST_RANGE_RANGE_10000 (0x00000000) +#define NVCA7D_HEAD_SET_LTM_CONTROL_HIST_RANGE_RANGE_5000 (0x00000001) +#define NVCA7D_HEAD_SET_LTM_CONTROL_HIST_RANGE_RANGE_2500 (0x00000002) +#define NVCA7D_HEAD_SET_LTM_CONTROL_HIST_RANGE_RANGE_1250 (0x00000003) +#define NVCA7D_HEAD_SET_LTM_CONTROL_HIST_END_LINE 31:16 +#define NVCA7D_HEAD_SET_RGB2ITP_COEFF_C00(a) (0x000023D4 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_RGB2ITP_COEFF_C00_VALUE 20:0 +#define NVCA7D_HEAD_SET_RGB2ITP_COEFF_C01(a) (0x000023D8 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_RGB2ITP_COEFF_C01_VALUE 20:0 +#define NVCA7D_HEAD_SET_RGB2ITP_COEFF_C02(a) (0x000023DC + (a)*0x00000800) +#define NVCA7D_HEAD_SET_RGB2ITP_COEFF_C02_VALUE 20:0 +#define NVCA7D_HEAD_SET_RGB2ITP_COEFF_C03(a) (0x000023E0 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_RGB2ITP_COEFF_C03_VALUE 20:0 +#define NVCA7D_HEAD_SET_RGB2ITP_COEFF_C10(a) (0x000023E4 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_RGB2ITP_COEFF_C10_VALUE 20:0 +#define NVCA7D_HEAD_SET_RGB2ITP_COEFF_C11(a) (0x000023E8 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_RGB2ITP_COEFF_C11_VALUE 20:0 +#define NVCA7D_HEAD_SET_RGB2ITP_COEFF_C12(a) (0x000023EC + (a)*0x00000800) +#define NVCA7D_HEAD_SET_RGB2ITP_COEFF_C12_VALUE 20:0 +#define NVCA7D_HEAD_SET_RGB2ITP_COEFF_C13(a) (0x000023F0 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_RGB2ITP_COEFF_C13_VALUE 20:0 +#define NVCA7D_HEAD_SET_RGB2ITP_COEFF_C20(a) (0x000023F4 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_RGB2ITP_COEFF_C20_VALUE 20:0 +#define NVCA7D_HEAD_SET_RGB2ITP_COEFF_C21(a) (0x000023F8 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_RGB2ITP_COEFF_C21_VALUE 20:0 +#define NVCA7D_HEAD_SET_RGB2ITP_COEFF_C22(a) (0x000023FC + (a)*0x00000800) +#define NVCA7D_HEAD_SET_RGB2ITP_COEFF_C22_VALUE 20:0 +#define NVCA7D_HEAD_SET_RGB2ITP_COEFF_C23(a) (0x00002400 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_RGB2ITP_COEFF_C23_VALUE 20:0 +#define NVCA7D_HEAD_SET_ITP2RGB_COEFF_C00(a) (0x00002404 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_ITP2RGB_COEFF_C00_VALUE 20:0 +#define NVCA7D_HEAD_SET_ITP2RGB_COEFF_C01(a) (0x00002408 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_ITP2RGB_COEFF_C01_VALUE 20:0 +#define NVCA7D_HEAD_SET_ITP2RGB_COEFF_C02(a) (0x0000240C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_ITP2RGB_COEFF_C02_VALUE 20:0 +#define NVCA7D_HEAD_SET_ITP2RGB_COEFF_C03(a) (0x00002410 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_ITP2RGB_COEFF_C03_VALUE 20:0 +#define NVCA7D_HEAD_SET_ITP2RGB_COEFF_C10(a) (0x00002414 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_ITP2RGB_COEFF_C10_VALUE 20:0 +#define NVCA7D_HEAD_SET_ITP2RGB_COEFF_C11(a) (0x00002418 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_ITP2RGB_COEFF_C11_VALUE 20:0 +#define NVCA7D_HEAD_SET_ITP2RGB_COEFF_C12(a) (0x0000241C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_ITP2RGB_COEFF_C12_VALUE 20:0 +#define NVCA7D_HEAD_SET_ITP2RGB_COEFF_C13(a) (0x00002420 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_ITP2RGB_COEFF_C13_VALUE 20:0 +#define NVCA7D_HEAD_SET_ITP2RGB_COEFF_C20(a) (0x00002424 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_ITP2RGB_COEFF_C20_VALUE 20:0 +#define NVCA7D_HEAD_SET_ITP2RGB_COEFF_C21(a) (0x00002428 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_ITP2RGB_COEFF_C21_VALUE 20:0 +#define NVCA7D_HEAD_SET_ITP2RGB_COEFF_C22(a) (0x0000242C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_ITP2RGB_COEFF_C22_VALUE 20:0 +#define NVCA7D_HEAD_SET_ITP2RGB_COEFF_C23(a) (0x00002430 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_ITP2RGB_COEFF_C23_VALUE 20:0 +#define NVCA7D_HEAD_SET_LTM_MAX_SELECTIVE_UPDATE(a) (0x00002434 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_LTM_MAX_SELECTIVE_UPDATE_SIZE 31:0 +#define NVCA7D_HEAD_SET_SELF_REFRESH_OVERRIDE(a) (0x00002438 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_SELF_REFRESH_OVERRIDE_FRAME_RELEASE 0:0 +#define NVCA7D_HEAD_SET_SELF_REFRESH_OVERRIDE_FRAME_RELEASE_AUTOMATIC (0x00000000) +#define NVCA7D_HEAD_SET_SELF_REFRESH_OVERRIDE_FRAME_RELEASE_MANUAL (0x00000001) +#define NVCA7D_HEAD_SET_SELECTIVE_UPDATE(a) (0x0000243C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_SELECTIVE_UPDATE_ENABLE 0:0 +#define NVCA7D_HEAD_SET_SELECTIVE_UPDATE_ENABLE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_SELECTIVE_UPDATE_ENABLE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_SELECTIVE_UPDATE_EARLY_REGION 1:1 +#define NVCA7D_HEAD_SET_SELECTIVE_UPDATE_EARLY_REGION_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_SELECTIVE_UPDATE_EARLY_REGION_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_CURSOR_DIRTY(a) (0x00002440 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_CURSOR_DIRTY_STATE 0:0 +#define NVCA7D_HEAD_SET_CURSOR_DIRTY_STATE_FALSE (0x00000000) +#define NVCA7D_HEAD_SET_CURSOR_DIRTY_STATE_TRUE (0x00000001) +#define NVCA7D_HEAD_SET_DPM_CONTROL(a) (0x00002444 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_DPM_CONTROL_ENABLE 0:0 +#define NVCA7D_HEAD_SET_DPM_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_DPM_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_DPM_CONTROL_ALPM 1:1 +#define NVCA7D_HEAD_SET_DPM_CONTROL_ALPM_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_DPM_CONTROL_ALPM_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_DPM_CONTROL_ALPM_TYPE 2:2 +#define NVCA7D_HEAD_SET_DPM_CONTROL_ALPM_TYPE_AUX_LESS (0x00000000) +#define NVCA7D_HEAD_SET_DPM_CONTROL_AS_SDP 3:3 +#define NVCA7D_HEAD_SET_DPM_CONTROL_AS_SDP_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_DPM_CONTROL_AS_SDP_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL(a) (0x00002448 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_ENABLE 0:0 +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_ENABLE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_ENABLE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_SELF_REFRESH 1:1 +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_SELF_REFRESH_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_SELF_REFRESH_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_MODE 3:2 +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_MODE_PSR1 (0x00000000) +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_MODE_PANEL_REPLAY (0x00000002) +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_CRC 4:4 +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_CRC_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_CRC_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_LOCATION 7:6 +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_LOCATION_VBLANK (0x00000000) +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_LOCATION_VSYNC (0x00000001) +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_LOCATION_LINE (0x00000002) +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_LINE_ID 22:8 +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_CAPTURE_INDICATOR 23:23 +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_CAPTURE_INDICATOR_SAME (0x00000000) +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_CAPTURE_INDICATOR_EARLY (0x00000001) +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_IDLE_SDP 24:24 +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_IDLE_SDP_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_IDLE_SDP_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_OVERRIDE_SU_VSC 25:25 +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_OVERRIDE_SU_VSC_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_VSC_SDP_CTRL_OVERRIDE_SU_VSC_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_VSC_SDP_HEADER(a) (0x0000244C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_VSC_SDP_HEADER_HEADER_BYTE 31:0 +#define NVCA7D_HEAD_SET_VSC_SDP_DATA0(a) (0x00002450 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_VSC_SDP_DATA0_DATA_BYTE 31:0 +#define NVCA7D_HEAD_SET_VSC_SDP_DATA1(a) (0x00002454 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_VSC_SDP_DATA1_DATA_BYTE 31:0 +#define NVCA7D_HEAD_SET_VSC_SDP_DATA2(a) (0x00002458 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_VSC_SDP_DATA2_DATA_BYTE 31:0 +#define NVCA7D_HEAD_SET_VSC_SDP_DATA3(a) (0x0000245C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_VSC_SDP_DATA3_DATA_BYTE 31:0 +#define NVCA7D_HEAD_SET_VSC_SDP_DATA4(a) (0x00002460 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_VSC_SDP_DATA4_DATA_BYTE 31:0 +#define NVCA7D_HEAD_SET_VSC_SDP_DATA5(a) (0x00002464 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_VSC_SDP_DATA5_DATA_BYTE 31:0 +#define NVCA7D_HEAD_SET_VSC_SDP_DATA6(a) (0x00002468 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_VSC_SDP_DATA6_DATA_BYTE 31:0 +#define NVCA7D_HEAD_SET_VSC_SDP_DATA7(a) (0x0000246C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_VSC_SDP_DATA7_DATA_BYTE 31:0 +#define NVCA7D_HEAD_SET_RGB2ITP_CONTROL(a) (0x00002470 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_INPUT_MATRIX 0:0 +#define NVCA7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_INPUT_MATRIX_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_INPUT_MATRIX_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_FVLUT 1:1 +#define NVCA7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_FVLUT_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_FVLUT_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_INTERPOLATE 4:4 +#define NVCA7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_INTERPOLATE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_INTERPOLATE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_MIRROR 5:5 +#define NVCA7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_MIRROR_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_MIRROR_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_CURVE 7:6 +#define NVCA7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_CURVE_CSCLUT_PQ (0x00000000) +#define NVCA7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_CURVE_CSCLUT_HLG (0x00000001) +#define NVCA7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_CURVE_CSCLUT_DIRECT (0x00000002) +#define NVCA7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_OUTPUT_MATRIX 2:2 +#define NVCA7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_OUTPUT_MATRIX_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_OUTPUT_MATRIX_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_RGB2ITP_LUT_FP_NORM_SCALE(a) (0x00002474 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_RGB2ITP_LUT_FP_NORM_SCALE_VALUE 31:0 +#define NVCA7D_HEAD_SET_ITP2RGB_CONTROL(a) (0x00002478 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_INPUT_MATRIX 0:0 +#define NVCA7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_INPUT_MATRIX_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_INPUT_MATRIX_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_FVLUT 1:1 +#define NVCA7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_FVLUT_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_FVLUT_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_INTERPOLATE 4:4 +#define NVCA7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_INTERPOLATE_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_INTERPOLATE_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_MIRROR 5:5 +#define NVCA7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_MIRROR_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_MIRROR_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_CURVE 7:6 +#define NVCA7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_CURVE_CSCLUT_PQ (0x00000000) +#define NVCA7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_CURVE_CSCLUT_HLG (0x00000001) +#define NVCA7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_CURVE_CSCLUT_DIRECT (0x00000002) +#define NVCA7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_OUTPUT_MATRIX 2:2 +#define NVCA7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_OUTPUT_MATRIX_DISABLE (0x00000000) +#define NVCA7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_OUTPUT_MATRIX_ENABLE (0x00000001) +#define NVCA7D_HEAD_SET_ITP2RGB_LUT_FP_SCALE(a) (0x0000247C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_ITP2RGB_LUT_FP_SCALE_VALUE 15:0 +#define NVCA7D_HEAD_SET_BLANK_OUTPUT_COLOR(a) (0x00002484 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_BLANK_OUTPUT_COLOR_RED_CR 9:0 +#define NVCA7D_HEAD_SET_BLANK_OUTPUT_COLOR_GREEN_Y 19:10 +#define NVCA7D_HEAD_SET_BLANK_OUTPUT_COLOR_BLUE_CB 29:20 +#define NVCA7D_HEAD_SET_SELECTIVE_UPDATE_GRANULARITY(a) (0x0000249C + (a)*0x00000800) +#define NVCA7D_HEAD_SET_SELECTIVE_UPDATE_GRANULARITY_X 15:0 +#define NVCA7D_HEAD_SET_SELECTIVE_UPDATE_GRANULARITY_Y 31:16 +#define NVCA7D_HEAD_SET_LTM_HIST_COEFF_C00(a) (0x000024A0 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_LTM_HIST_COEFF_C00_VALUE 20:0 +#define NVCA7D_HEAD_SET_LTM_HIST_COEFF_C01(a) (0x000024A4 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_LTM_HIST_COEFF_C01_VALUE 20:0 +#define NVCA7D_HEAD_SET_LTM_HIST_COEFF_C02(a) (0x000024A8 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_LTM_HIST_COEFF_C02_VALUE 20:0 +#define NVCA7D_HEAD_SET_LTM_HIST_COEFF_C03(a) (0x000024AC + (a)*0x00000800) +#define NVCA7D_HEAD_SET_LTM_HIST_COEFF_C03_VALUE 20:0 +#define NVCA7D_HEAD_SET_LTM_HIST_COEFF_C10(a) (0x000024B0 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_LTM_HIST_COEFF_C10_VALUE 20:0 +#define NVCA7D_HEAD_SET_LTM_HIST_COEFF_C11(a) (0x000024B4 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_LTM_HIST_COEFF_C11_VALUE 20:0 +#define NVCA7D_HEAD_SET_LTM_HIST_COEFF_C12(a) (0x000024B8 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_LTM_HIST_COEFF_C12_VALUE 20:0 +#define NVCA7D_HEAD_SET_LTM_HIST_COEFF_C13(a) (0x000024BC + (a)*0x00000800) +#define NVCA7D_HEAD_SET_LTM_HIST_COEFF_C13_VALUE 20:0 +#define NVCA7D_HEAD_SET_LTM_HIST_COEFF_C20(a) (0x000024C0 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_LTM_HIST_COEFF_C20_VALUE 20:0 +#define NVCA7D_HEAD_SET_LTM_HIST_COEFF_C21(a) (0x000024C4 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_LTM_HIST_COEFF_C21_VALUE 20:0 +#define NVCA7D_HEAD_SET_LTM_HIST_COEFF_C22(a) (0x000024C8 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_LTM_HIST_COEFF_C22_VALUE 20:0 +#define NVCA7D_HEAD_SET_LTM_HIST_COEFF_C23(a) (0x000024CC + (a)*0x00000800) +#define NVCA7D_HEAD_SET_LTM_HIST_COEFF_C23_VALUE 20:0 + +#define NVCA7D_TILE_SET_TILE_SIZE(a) (0x00006000 + (a)*0x00000200) +#define NVCA7D_TILE_SET_TILE_SIZE_START 14:0 +#define NVCA7D_TILE_SET_TILE_SIZE_WIDTH 30:16 +#define NVCA7D_TILE_SET_CMI_LUT_SEGMENT_SIZE(a) (0x00006074 + (a)*0x00000200) +#define NVCA7D_TILE_SET_CMI_LUT_SEGMENT_SIZE_IDX 5:0 +#define NVCA7D_TILE_SET_CMI_LUT_SEGMENT_SIZE_VALUE 8:6 +#define NVCA7D_TILE_SET_CMI_LUT_ENTRY(a) (0x00006078 + (a)*0x00000200) +#define NVCA7D_TILE_SET_CMI_LUT_ENTRY_IDX 10:0 +#define NVCA7D_TILE_SET_CMI_LUT_ENTRY_VALUE 24:11 +#define NVCA7D_TILE_SET_CMI_LUT_ENTRY_LAST 25:25 +#define NVCA7D_TILE_SET_CMI_LUT_ENTRY_LAST_FALSE (0x00000000) +#define NVCA7D_TILE_SET_CMI_LUT_ENTRY_LAST_TRUE (0x00000001) +#define NVCA7D_TILE_SET_CMO_LUT_SEGMENT_SIZE(a) (0x0000607C + (a)*0x00000200) +#define NVCA7D_TILE_SET_CMO_LUT_SEGMENT_SIZE_IDX 5:0 +#define NVCA7D_TILE_SET_CMO_LUT_SEGMENT_SIZE_VALUE 8:6 +#define NVCA7D_TILE_SET_CMO_LUT_ENTRY(a) (0x00006080 + (a)*0x00000200) +#define NVCA7D_TILE_SET_CMO_LUT_ENTRY_IDX 10:0 +#define NVCA7D_TILE_SET_CMO_LUT_ENTRY_VALUE 26:11 +#define NVCA7D_TILE_SET_CMO_LUT_ENTRY_LAST 27:27 +#define NVCA7D_TILE_SET_CMO_LUT_ENTRY_LAST_FALSE (0x00000000) +#define NVCA7D_TILE_SET_CMO_LUT_ENTRY_LAST_TRUE (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clca7d_h diff --git a/userspace/sdks/nv570/inc/class/clca7e.h b/userspace/sdks/nv570/inc/class/clca7e.h new file mode 100644 index 0000000..bd672e3 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clca7e.h @@ -0,0 +1,906 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clca7e_h_ +#define _clca7e_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVCA7E_WINDOW_CHANNEL_DMA (0x0000CA7E) + +// dma opcode instructions +#define NVCA7E_DMA +#define NVCA7E_DMA_OPCODE 31:29 +#define NVCA7E_DMA_OPCODE_METHOD 0x00000000 +#define NVCA7E_DMA_OPCODE_JUMP 0x00000001 +#define NVCA7E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVCA7E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVCA7E_DMA_METHOD_COUNT 27:18 +#define NVCA7E_DMA_METHOD_OFFSET 15:2 +#define NVCA7E_DMA_DATA 31:0 +#define NVCA7E_DMA_DATA_NOP 0x00000000 +#define NVCA7E_DMA_JUMP_OFFSET 15:2 +#define NVCA7E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVCA7E_PUT (0x00000000) +#define NVCA7E_PUT_PTR 13:0 +#define NVCA7E_GET (0x00000004) +#define NVCA7E_GET_PTR 13:0 +#define NVCA7E_UPDATE (0x00000200) +#define NVCA7E_UPDATE_RELEASE_ELV 0:0 +#define NVCA7E_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVCA7E_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVCA7E_UPDATE_INTERLOCK_WITH_WIN_IMM 12:12 +#define NVCA7E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE (0x00000000) +#define NVCA7E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE (0x00000001) +#define NVCA7E_UPDATE_FORCE_FULLSCREEN 16:16 +#define NVCA7E_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000) +#define NVCA7E_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001) +#define NVCA7E_SET_SEMAPHORE_ACQUIRE_HI (0x00000204) +#define NVCA7E_SET_SEMAPHORE_ACQUIRE_HI_VALUE 31:0 +#define NVCA7E_GET_LINE (0x00000208) +#define NVCA7E_GET_LINE_LINE 15:0 +#define NVCA7E_SET_SEMAPHORE_CONTROL (0x0000020C) +#define NVCA7E_SET_SEMAPHORE_CONTROL_SKIP_ACQ 11:11 +#define NVCA7E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_FALSE (0x00000000) +#define NVCA7E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_TRUE (0x00000001) +#define NVCA7E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVCA7E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVCA7E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVCA7E_SET_SEMAPHORE_CONTROL_ACQ_MODE 13:12 +#define NVCA7E_SET_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000) +#define NVCA7E_SET_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001) +#define NVCA7E_SET_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002) +#define NVCA7E_SET_SEMAPHORE_CONTROL_REL_MODE 14:14 +#define NVCA7E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE (0x00000000) +#define NVCA7E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE_AWAKEN (0x00000001) +#define NVCA7E_SET_SEMAPHORE_ACQUIRE (0x00000210) +#define NVCA7E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NVCA7E_SET_SEMAPHORE_RELEASE (0x00000214) +#define NVCA7E_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NVCA7E_SET_NOTIFIER_CONTROL (0x00000220) +#define NVCA7E_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVCA7E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVCA7E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVCA7E_SET_SIZE (0x00000224) +#define NVCA7E_SET_SIZE_WIDTH 15:0 +#define NVCA7E_SET_SIZE_HEIGHT 31:16 +#define NVCA7E_SET_STORAGE (0x00000228) +#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVCA7E_SET_PARAMS (0x0000022C) +#define NVCA7E_SET_PARAMS_FORMAT 7:0 +#define NVCA7E_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NVCA7E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F) +#define NVCA7E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NVCA7E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NVCA7E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E) +#define NVCA7E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NVCA7E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6) +#define NVCA7E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NVCA7E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9) +#define NVCA7E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NVCA7E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NVCA7E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NVCA7E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NVCA7E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NVCA7E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028) +#define NVCA7E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029) +#define NVCA7E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035) +#define NVCA7E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036) +#define NVCA7E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038) +#define NVCA7E_SET_PARAMS_FORMAT_Y8___U8___V8_N444 (0x0000003A) +#define NVCA7E_SET_PARAMS_FORMAT_Y8___U8___V8_N420 (0x0000003B) +#define NVCA7E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055) +#define NVCA7E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056) +#define NVCA7E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058) +#define NVCA7E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075) +#define NVCA7E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076) +#define NVCA7E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078) +#define NVCA7E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18 +#define NVCA7E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000) +#define NVCA7E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001) +#define NVCA7E_SET_PARAMS_SWAP_UV 19:19 +#define NVCA7E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000) +#define NVCA7E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001) +#define NVCA7E_SET_PARAMS_FMT_ROUNDING_MODE 22:22 +#define NVCA7E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_TO_NEAREST (0x00000000) +#define NVCA7E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_DOWN (0x00000001) +#define NVCA7E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004) +#define NVCA7E_SET_PLANAR_STORAGE_PITCH 12:0 +#define NVCA7E_SET_SEMAPHORE_RELEASE_HI (0x0000023C) +#define NVCA7E_SET_SEMAPHORE_RELEASE_HI_VALUE 31:0 +#define NVCA7E_SET_SURFACE_ADDRESS_HI_BEGUN_SEMAPHORE_ARRAY (0x00000240) +#define NVCA7E_SET_SURFACE_ADDRESS_HI_BEGUN_SEMAPHORE_ARRAY_ADDRESS_HI 31:0 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY (0x00000244) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ADDRESS_LO 31:4 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET 3:2 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_IOVA (0x00000000) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ENABLE 0:0 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ENABLE_DISABLE (0x00000000) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ENABLE_ENABLE (0x00000001) +#define NVCA7E_SET_SURFACE_ADDRESS_HI_FINISH_SEMAPHORE_ARRAY (0x00000248) +#define NVCA7E_SET_SURFACE_ADDRESS_HI_FINISH_SEMAPHORE_ARRAY_ADDRESS_HI 31:0 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY (0x0000024C) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ADDRESS_LO 31:4 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET 3:2 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_IOVA (0x00000000) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ENABLE 0:0 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ENABLE_DISABLE (0x00000000) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ENABLE_ENABLE (0x00000001) +#define NVCA7E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004) +#define NVCA7E_SET_POINT_IN_X 15:0 +#define NVCA7E_SET_POINT_IN_Y 31:16 +#define NVCA7E_SET_SIZE_IN (0x00000298) +#define NVCA7E_SET_SIZE_IN_WIDTH 15:0 +#define NVCA7E_SET_SIZE_IN_HEIGHT 31:16 +#define NVCA7E_SET_SIZE_OUT (0x000002A4) +#define NVCA7E_SET_SIZE_OUT_WIDTH 15:0 +#define NVCA7E_SET_SIZE_OUT_HEIGHT 31:16 +#define NVCA7E_SET_CONTROL_INPUT_SCALER (0x000002A8) +#define NVCA7E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVCA7E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVCA7E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVCA7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVCA7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVCA7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVCA7E_SET_CONTROL_INPUT_SCALER_VERTICAL_FORCE_ENABLE 8:8 +#define NVCA7E_SET_CONTROL_INPUT_SCALER_VERTICAL_FORCE_ENABLE_DISABLE (0x00000000) +#define NVCA7E_SET_CONTROL_INPUT_SCALER_VERTICAL_FORCE_ENABLE_ENABLE (0x00000001) +#define NVCA7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_FORCE_ENABLE 9:9 +#define NVCA7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_FORCE_ENABLE_DISABLE (0x00000000) +#define NVCA7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_FORCE_ENABLE_ENABLE (0x00000001) +#define NVCA7E_SET_INPUT_SCALER_COEFF_VALUE (0x000002AC) +#define NVCA7E_SET_INPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVCA7E_SET_INPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVCA7E_SET_COMPOSITION_CONTROL (0x000002EC) +#define NVCA7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0 +#define NVCA7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000) +#define NVCA7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001) +#define NVCA7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002) +#define NVCA7E_SET_COMPOSITION_CONTROL_DEPTH 11:4 +#define NVCA7E_SET_COMPOSITION_CONTROL_BYPASS 16:16 +#define NVCA7E_SET_COMPOSITION_CONTROL_BYPASS_DISABLE (0x00000000) +#define NVCA7E_SET_COMPOSITION_CONTROL_BYPASS_ENABLE (0x00000001) +#define NVCA7E_SET_COMPOSITION_CONSTANT_ALPHA (0x000002F0) +#define NVCA7E_SET_COMPOSITION_CONSTANT_ALPHA_K1 7:0 +#define NVCA7E_SET_COMPOSITION_CONSTANT_ALPHA_K2 15:8 +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT (0x000002F4) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0 +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4 +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8 +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12 +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16 +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20 +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24 +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28 +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVCA7E_SET_KEY_ALPHA (0x000002F8) +#define NVCA7E_SET_KEY_ALPHA_MIN 15:0 +#define NVCA7E_SET_KEY_ALPHA_MAX 31:16 +#define NVCA7E_SET_KEY_RED_CR (0x000002FC) +#define NVCA7E_SET_KEY_RED_CR_MIN 15:0 +#define NVCA7E_SET_KEY_RED_CR_MAX 31:16 +#define NVCA7E_SET_KEY_GREEN_Y (0x00000300) +#define NVCA7E_SET_KEY_GREEN_Y_MIN 15:0 +#define NVCA7E_SET_KEY_GREEN_Y_MAX 31:16 +#define NVCA7E_SET_KEY_BLUE_CB (0x00000304) +#define NVCA7E_SET_KEY_BLUE_CB_MIN 15:0 +#define NVCA7E_SET_KEY_BLUE_CB_MAX 31:16 +#define NVCA7E_SET_PRESENT_CONTROL (0x00000308) +#define NVCA7E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NVCA7E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4 +#define NVCA7E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NVCA7E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NVCA7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8 +#define NVCA7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000) +#define NVCA7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001) +#define NVCA7E_SET_PRESENT_CONTROL_STEREO_MODE 13:12 +#define NVCA7E_SET_PRESENT_CONTROL_STEREO_MODE_MONO (0x00000000) +#define NVCA7E_SET_PRESENT_CONTROL_STEREO_MODE_PAIR_FLIP (0x00000001) +#define NVCA7E_SET_PRESENT_CONTROL_STEREO_MODE_AT_ANY_FRAME (0x00000002) +#define NVCA7E_SET_ACQ_SEMAPHORE_VALUE_HI (0x0000030C) +#define NVCA7E_SET_ACQ_SEMAPHORE_VALUE_HI_VALUE 31:0 +#define NVCA7E_SET_ACQ_SEMAPHORE_CONTROL (0x00000330) +#define NVCA7E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVCA7E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVCA7E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVCA7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE 13:12 +#define NVCA7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000) +#define NVCA7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001) +#define NVCA7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002) +#define NVCA7E_SET_ACQ_SEMAPHORE_VALUE (0x00000334) +#define NVCA7E_SET_ACQ_SEMAPHORE_VALUE_VALUE 31:0 +#define NVCA7E_SET_SCAN_DIRECTION (0x0000033C) +#define NVCA7E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION 0:0 +#define NVCA7E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_LEFT (0x00000000) +#define NVCA7E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_RIGHT (0x00000001) +#define NVCA7E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION 1:1 +#define NVCA7E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_TOP (0x00000000) +#define NVCA7E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_BOTTOM (0x00000001) +#define NVCA7E_SET_SCAN_DIRECTION_COLUMN_ORDER 2:2 +#define NVCA7E_SET_SCAN_DIRECTION_COLUMN_ORDER_FALSE (0x00000000) +#define NVCA7E_SET_SCAN_DIRECTION_COLUMN_ORDER_TRUE (0x00000001) +#define NVCA7E_SET_TIMESTAMP_ORIGIN_LO (0x00000340) +#define NVCA7E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NVCA7E_SET_TIMESTAMP_ORIGIN_HI (0x00000344) +#define NVCA7E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NVCA7E_SET_UPDATE_TIMESTAMP_LO (0x00000348) +#define NVCA7E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NVCA7E_SET_UPDATE_TIMESTAMP_HI (0x0000034C) +#define NVCA7E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NVCA7E_SET_INTERLOCK_FLAGS (0x00000370) +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 0:0 +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+1):((i)+1) +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 1:1 +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 2:2 +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 3:3 +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 4:4 +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 5:5 +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 6:6 +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 7:7 +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 8:8 +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS (0x00000374) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVCA7E_SET_CHROMA_VER (0x00000378) +#define NVCA7E_SET_CHROMA_VER_POSITION 1:0 +#define NVCA7E_SET_CHROMA_VER_POSITION_TOP (0x00000000) +#define NVCA7E_SET_CHROMA_VER_POSITION_CENTER (0x00000001) +#define NVCA7E_SET_CHROMA_VER_POSITION_BOTTOM (0x00000002) +#define NVCA7E_SET_CHROMA_VER_USE_SWPOSITION 2:2 +#define NVCA7E_SET_CHROMA_VER_USE_SWPOSITION_FALSE (0x00000000) +#define NVCA7E_SET_CHROMA_VER_USE_SWPOSITION_TRUE (0x00000001) +#define NVCA7E_SET_CHROMA_VER_WEIGHT_ODD 4:3 +#define NVCA7E_SET_CHROMA_VER_WEIGHT_ODD_WT_0 (0x00000000) +#define NVCA7E_SET_CHROMA_VER_WEIGHT_ODD_WT_QUARTER (0x00000001) +#define NVCA7E_SET_CHROMA_VER_WEIGHT_ODD_WT_HALF (0x00000002) +#define NVCA7E_SET_CHROMA_VER_WEIGHT_ODD_WT_THREE_QUARTER (0x00000003) +#define NVCA7E_SET_CHROMA_VER_WEIGHT_EVEN 6:5 +#define NVCA7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_0 (0x00000000) +#define NVCA7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_QUARTER (0x00000001) +#define NVCA7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_HALF (0x00000002) +#define NVCA7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_THREE_QUARTER (0x00000003) +#define NVCA7E_SET_CHROMA_VER_USE_SWWEIGHTS 7:7 +#define NVCA7E_SET_CHROMA_VER_USE_SWWEIGHTS_FALSE (0x00000000) +#define NVCA7E_SET_CHROMA_VER_USE_SWWEIGHTS_TRUE (0x00000001) +#define NVCA7E_SET_CHROMA_HOR (0x0000037C) +#define NVCA7E_SET_CHROMA_HOR_REPLACE_ODD 0:0 +#define NVCA7E_SET_CHROMA_HOR_REPLACE_ODD_DISABLE (0x00000000) +#define NVCA7E_SET_CHROMA_HOR_REPLACE_ODD_ENABLE (0x00000001) +#define NVCA7E_SET_CHROMA_HOR_REPLACE_EVEN 1:1 +#define NVCA7E_SET_CHROMA_HOR_REPLACE_EVEN_DISABLE (0x00000000) +#define NVCA7E_SET_CHROMA_HOR_REPLACE_EVEN_ENABLE (0x00000001) +#define NVCA7E_SET_CHROMA_HOR_WEIGHT_ODD 3:2 +#define NVCA7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_0 (0x00000000) +#define NVCA7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_QUARTER (0x00000001) +#define NVCA7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_HALF (0x00000002) +#define NVCA7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_THREE_QUARTER (0x00000003) +#define NVCA7E_SET_CHROMA_HOR_WEIGHT_EVEN 5:4 +#define NVCA7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_0 (0x00000000) +#define NVCA7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_QUARTER (0x00000001) +#define NVCA7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_HALF (0x00000002) +#define NVCA7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_THREE_QUARTER (0x00000003) +#define NVCA7E_SET_CHROMA_HOR_USE_SWWEIGHTS 6:6 +#define NVCA7E_SET_CHROMA_HOR_USE_SWWEIGHTS_FALSE (0x00000000) +#define NVCA7E_SET_CHROMA_HOR_USE_SWWEIGHTS_TRUE (0x00000001) +#define NVCA7E_SET_EXT_PACKET_CONTROL (0x00000398) +#define NVCA7E_SET_EXT_PACKET_CONTROL_ENABLE 0:0 +#define NVCA7E_SET_EXT_PACKET_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCA7E_SET_EXT_PACKET_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCA7E_SET_EXT_PACKET_CONTROL_LOCATION 4:4 +#define NVCA7E_SET_EXT_PACKET_CONTROL_LOCATION_VSYNC (0x00000000) +#define NVCA7E_SET_EXT_PACKET_CONTROL_LOCATION_VBLANK (0x00000001) +#define NVCA7E_SET_EXT_PACKET_CONTROL_FREQUENCY 8:8 +#define NVCA7E_SET_EXT_PACKET_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVCA7E_SET_EXT_PACKET_CONTROL_FREQUENCY_ONCE (0x00000001) +#define NVCA7E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE 12:12 +#define NVCA7E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_DISABLE (0x00000000) +#define NVCA7E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_ENABLE (0x00000001) +#define NVCA7E_SET_EXT_PACKET_CONTROL_SIZE 27:16 +#define NVCA7E_SET_EXT_PACKET_DATA (0x0000039C) +#define NVCA7E_SET_EXT_PACKET_DATA_DB0 7:0 +#define NVCA7E_SET_EXT_PACKET_DATA_DB1 15:8 +#define NVCA7E_SET_EXT_PACKET_DATA_DB2 23:16 +#define NVCA7E_SET_EXT_PACKET_DATA_DB3 31:24 +#define NVCA7E_SET_WIN_INFOFRAME (0x000003A0) +#define NVCA7E_SET_WIN_INFOFRAME_FID 7:0 +#define NVCA7E_SET_WIN_INFOFRAME_EN 16:16 +#define NVCA7E_SET_WIN_INFOFRAME_EN_DISABLE (0x00000000) +#define NVCA7E_SET_WIN_INFOFRAME_EN_ENABLE (0x00000001) +#define NVCA7E_SET_FMT_COEFFICIENT_C00 (0x00000400) +#define NVCA7E_SET_FMT_COEFFICIENT_C00_VALUE 20:0 +#define NVCA7E_SET_FMT_COEFFICIENT_C01 (0x00000404) +#define NVCA7E_SET_FMT_COEFFICIENT_C01_VALUE 20:0 +#define NVCA7E_SET_FMT_COEFFICIENT_C02 (0x00000408) +#define NVCA7E_SET_FMT_COEFFICIENT_C02_VALUE 20:0 +#define NVCA7E_SET_FMT_COEFFICIENT_C03 (0x0000040C) +#define NVCA7E_SET_FMT_COEFFICIENT_C03_VALUE 20:0 +#define NVCA7E_SET_FMT_COEFFICIENT_C10 (0x00000410) +#define NVCA7E_SET_FMT_COEFFICIENT_C10_VALUE 20:0 +#define NVCA7E_SET_FMT_COEFFICIENT_C11 (0x00000414) +#define NVCA7E_SET_FMT_COEFFICIENT_C11_VALUE 20:0 +#define NVCA7E_SET_FMT_COEFFICIENT_C12 (0x00000418) +#define NVCA7E_SET_FMT_COEFFICIENT_C12_VALUE 20:0 +#define NVCA7E_SET_FMT_COEFFICIENT_C13 (0x0000041C) +#define NVCA7E_SET_FMT_COEFFICIENT_C13_VALUE 20:0 +#define NVCA7E_SET_FMT_COEFFICIENT_C20 (0x00000420) +#define NVCA7E_SET_FMT_COEFFICIENT_C20_VALUE 20:0 +#define NVCA7E_SET_FMT_COEFFICIENT_C21 (0x00000424) +#define NVCA7E_SET_FMT_COEFFICIENT_C21_VALUE 20:0 +#define NVCA7E_SET_FMT_COEFFICIENT_C22 (0x00000428) +#define NVCA7E_SET_FMT_COEFFICIENT_C22_VALUE 20:0 +#define NVCA7E_SET_FMT_COEFFICIENT_C23 (0x0000042C) +#define NVCA7E_SET_FMT_COEFFICIENT_C23_VALUE 20:0 +#define NVCA7E_SET_ILUT_CONTROL (0x00000440) +#define NVCA7E_SET_ILUT_CONTROL_INTERPOLATE 0:0 +#define NVCA7E_SET_ILUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVCA7E_SET_ILUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVCA7E_SET_ILUT_CONTROL_MIRROR 1:1 +#define NVCA7E_SET_ILUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVCA7E_SET_ILUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVCA7E_SET_ILUT_CONTROL_MODE 3:2 +#define NVCA7E_SET_ILUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVCA7E_SET_ILUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVCA7E_SET_ILUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVCA7E_SET_ILUT_CONTROL_SIZE 18:8 +#define NVCA7E_SET_CSC00CONTROL (0x0000045C) +#define NVCA7E_SET_CSC00CONTROL_ENABLE 0:0 +#define NVCA7E_SET_CSC00CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCA7E_SET_CSC00CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCA7E_SET_CSC00COEFFICIENT_C00 (0x00000460) +#define NVCA7E_SET_CSC00COEFFICIENT_C00_VALUE 20:0 +#define NVCA7E_SET_CSC00COEFFICIENT_C01 (0x00000464) +#define NVCA7E_SET_CSC00COEFFICIENT_C01_VALUE 20:0 +#define NVCA7E_SET_CSC00COEFFICIENT_C02 (0x00000468) +#define NVCA7E_SET_CSC00COEFFICIENT_C02_VALUE 20:0 +#define NVCA7E_SET_CSC00COEFFICIENT_C03 (0x0000046C) +#define NVCA7E_SET_CSC00COEFFICIENT_C03_VALUE 20:0 +#define NVCA7E_SET_CSC00COEFFICIENT_C10 (0x00000470) +#define NVCA7E_SET_CSC00COEFFICIENT_C10_VALUE 20:0 +#define NVCA7E_SET_CSC00COEFFICIENT_C11 (0x00000474) +#define NVCA7E_SET_CSC00COEFFICIENT_C11_VALUE 20:0 +#define NVCA7E_SET_CSC00COEFFICIENT_C12 (0x00000478) +#define NVCA7E_SET_CSC00COEFFICIENT_C12_VALUE 20:0 +#define NVCA7E_SET_CSC00COEFFICIENT_C13 (0x0000047C) +#define NVCA7E_SET_CSC00COEFFICIENT_C13_VALUE 20:0 +#define NVCA7E_SET_CSC00COEFFICIENT_C20 (0x00000480) +#define NVCA7E_SET_CSC00COEFFICIENT_C20_VALUE 20:0 +#define NVCA7E_SET_CSC00COEFFICIENT_C21 (0x00000484) +#define NVCA7E_SET_CSC00COEFFICIENT_C21_VALUE 20:0 +#define NVCA7E_SET_CSC00COEFFICIENT_C22 (0x00000488) +#define NVCA7E_SET_CSC00COEFFICIENT_C22_VALUE 20:0 +#define NVCA7E_SET_CSC00COEFFICIENT_C23 (0x0000048C) +#define NVCA7E_SET_CSC00COEFFICIENT_C23_VALUE 20:0 +#define NVCA7E_SET_CSC0LUT_FP_NORM_SCALE (0x00000490) +#define NVCA7E_SET_CSC0LUT_FP_NORM_SCALE_VALUE 31:0 +#define NVCA7E_SET_CSC0LUT_CONTROL (0x000004A0) +#define NVCA7E_SET_CSC0LUT_CONTROL_INTERPOLATE 0:0 +#define NVCA7E_SET_CSC0LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVCA7E_SET_CSC0LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVCA7E_SET_CSC0LUT_CONTROL_MIRROR 1:1 +#define NVCA7E_SET_CSC0LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVCA7E_SET_CSC0LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVCA7E_SET_CSC0LUT_CONTROL_ENABLE 4:4 +#define NVCA7E_SET_CSC0LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCA7E_SET_CSC0LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCA7E_SET_CSC0LUT_CONTROL_CURVE 6:5 +#define NVCA7E_SET_CSC0LUT_CONTROL_CURVE_CSCLUT_PQ (0x00000000) +#define NVCA7E_SET_CSC0LUT_CONTROL_CURVE_CSCLUT_HLG (0x00000001) +#define NVCA7E_SET_CSC0LUT_CONTROL_CURVE_CSCLUT_DIRECT (0x00000002) +#define NVCA7E_SET_CSC01CONTROL (0x000004BC) +#define NVCA7E_SET_CSC01CONTROL_ENABLE 0:0 +#define NVCA7E_SET_CSC01CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCA7E_SET_CSC01CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCA7E_SET_CSC01COEFFICIENT_C00 (0x000004C0) +#define NVCA7E_SET_CSC01COEFFICIENT_C00_VALUE 20:0 +#define NVCA7E_SET_CSC01COEFFICIENT_C01 (0x000004C4) +#define NVCA7E_SET_CSC01COEFFICIENT_C01_VALUE 20:0 +#define NVCA7E_SET_CSC01COEFFICIENT_C02 (0x000004C8) +#define NVCA7E_SET_CSC01COEFFICIENT_C02_VALUE 20:0 +#define NVCA7E_SET_CSC01COEFFICIENT_C03 (0x000004CC) +#define NVCA7E_SET_CSC01COEFFICIENT_C03_VALUE 20:0 +#define NVCA7E_SET_CSC01COEFFICIENT_C10 (0x000004D0) +#define NVCA7E_SET_CSC01COEFFICIENT_C10_VALUE 20:0 +#define NVCA7E_SET_CSC01COEFFICIENT_C11 (0x000004D4) +#define NVCA7E_SET_CSC01COEFFICIENT_C11_VALUE 20:0 +#define NVCA7E_SET_CSC01COEFFICIENT_C12 (0x000004D8) +#define NVCA7E_SET_CSC01COEFFICIENT_C12_VALUE 20:0 +#define NVCA7E_SET_CSC01COEFFICIENT_C13 (0x000004DC) +#define NVCA7E_SET_CSC01COEFFICIENT_C13_VALUE 20:0 +#define NVCA7E_SET_CSC01COEFFICIENT_C20 (0x000004E0) +#define NVCA7E_SET_CSC01COEFFICIENT_C20_VALUE 20:0 +#define NVCA7E_SET_CSC01COEFFICIENT_C21 (0x000004E4) +#define NVCA7E_SET_CSC01COEFFICIENT_C21_VALUE 20:0 +#define NVCA7E_SET_CSC01COEFFICIENT_C22 (0x000004E8) +#define NVCA7E_SET_CSC01COEFFICIENT_C22_VALUE 20:0 +#define NVCA7E_SET_CSC01COEFFICIENT_C23 (0x000004EC) +#define NVCA7E_SET_CSC01COEFFICIENT_C23_VALUE 20:0 +#define NVCA7E_SET_TMO_CONTROL (0x00000500) +#define NVCA7E_SET_TMO_CONTROL_INTERPOLATE 0:0 +#define NVCA7E_SET_TMO_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVCA7E_SET_TMO_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVCA7E_SET_TMO_CONTROL_SAT_MODE 3:2 +#define NVCA7E_SET_TMO_CONTROL_SIZE 18:8 +#define NVCA7E_SET_TMO_LOW_INTENSITY_ZONE (0x00000508) +#define NVCA7E_SET_TMO_LOW_INTENSITY_ZONE_END 29:16 +#define NVCA7E_SET_TMO_LOW_INTENSITY_VALUE (0x0000050C) +#define NVCA7E_SET_TMO_LOW_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVCA7E_SET_TMO_LOW_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVCA7E_SET_TMO_LOW_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVCA7E_SET_TMO_MEDIUM_INTENSITY_ZONE (0x00000510) +#define NVCA7E_SET_TMO_MEDIUM_INTENSITY_ZONE_START 13:0 +#define NVCA7E_SET_TMO_MEDIUM_INTENSITY_ZONE_END 29:16 +#define NVCA7E_SET_TMO_MEDIUM_INTENSITY_VALUE (0x00000514) +#define NVCA7E_SET_TMO_MEDIUM_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVCA7E_SET_TMO_MEDIUM_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVCA7E_SET_TMO_MEDIUM_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVCA7E_SET_TMO_HIGH_INTENSITY_ZONE (0x00000518) +#define NVCA7E_SET_TMO_HIGH_INTENSITY_ZONE_START 13:0 +#define NVCA7E_SET_TMO_HIGH_INTENSITY_VALUE (0x0000051C) +#define NVCA7E_SET_TMO_HIGH_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVCA7E_SET_TMO_HIGH_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVCA7E_SET_TMO_HIGH_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVCA7E_SET_CSC10CONTROL (0x0000053C) +#define NVCA7E_SET_CSC10CONTROL_ENABLE 0:0 +#define NVCA7E_SET_CSC10CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCA7E_SET_CSC10CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCA7E_SET_CSC10COEFFICIENT_C00 (0x00000540) +#define NVCA7E_SET_CSC10COEFFICIENT_C00_VALUE 20:0 +#define NVCA7E_SET_CSC10COEFFICIENT_C01 (0x00000544) +#define NVCA7E_SET_CSC10COEFFICIENT_C01_VALUE 20:0 +#define NVCA7E_SET_CSC10COEFFICIENT_C02 (0x00000548) +#define NVCA7E_SET_CSC10COEFFICIENT_C02_VALUE 20:0 +#define NVCA7E_SET_CSC10COEFFICIENT_C03 (0x0000054C) +#define NVCA7E_SET_CSC10COEFFICIENT_C03_VALUE 20:0 +#define NVCA7E_SET_CSC10COEFFICIENT_C10 (0x00000550) +#define NVCA7E_SET_CSC10COEFFICIENT_C10_VALUE 20:0 +#define NVCA7E_SET_CSC10COEFFICIENT_C11 (0x00000554) +#define NVCA7E_SET_CSC10COEFFICIENT_C11_VALUE 20:0 +#define NVCA7E_SET_CSC10COEFFICIENT_C12 (0x00000558) +#define NVCA7E_SET_CSC10COEFFICIENT_C12_VALUE 20:0 +#define NVCA7E_SET_CSC10COEFFICIENT_C13 (0x0000055C) +#define NVCA7E_SET_CSC10COEFFICIENT_C13_VALUE 20:0 +#define NVCA7E_SET_CSC10COEFFICIENT_C20 (0x00000560) +#define NVCA7E_SET_CSC10COEFFICIENT_C20_VALUE 20:0 +#define NVCA7E_SET_CSC10COEFFICIENT_C21 (0x00000564) +#define NVCA7E_SET_CSC10COEFFICIENT_C21_VALUE 20:0 +#define NVCA7E_SET_CSC10COEFFICIENT_C22 (0x00000568) +#define NVCA7E_SET_CSC10COEFFICIENT_C22_VALUE 20:0 +#define NVCA7E_SET_CSC10COEFFICIENT_C23 (0x0000056C) +#define NVCA7E_SET_CSC10COEFFICIENT_C23_VALUE 20:0 +#define NVCA7E_SET_CSC1LUT_FP_SCALE (0x00000570) +#define NVCA7E_SET_CSC1LUT_FP_SCALE_VALUE 15:0 +#define NVCA7E_SET_CSC1LUT_CONTROL (0x00000580) +#define NVCA7E_SET_CSC1LUT_CONTROL_INTERPOLATE 0:0 +#define NVCA7E_SET_CSC1LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVCA7E_SET_CSC1LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVCA7E_SET_CSC1LUT_CONTROL_MIRROR 1:1 +#define NVCA7E_SET_CSC1LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVCA7E_SET_CSC1LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVCA7E_SET_CSC1LUT_CONTROL_ENABLE 4:4 +#define NVCA7E_SET_CSC1LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCA7E_SET_CSC1LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCA7E_SET_CSC1LUT_CONTROL_CURVE 6:5 +#define NVCA7E_SET_CSC1LUT_CONTROL_CURVE_CSCLUT_PQ (0x00000000) +#define NVCA7E_SET_CSC1LUT_CONTROL_CURVE_CSCLUT_HLG (0x00000001) +#define NVCA7E_SET_CSC1LUT_CONTROL_CURVE_CSCLUT_DIRECT (0x00000002) +#define NVCA7E_SET_CSC11CONTROL (0x0000059C) +#define NVCA7E_SET_CSC11CONTROL_ENABLE 0:0 +#define NVCA7E_SET_CSC11CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCA7E_SET_CSC11CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCA7E_SET_CSC11CONTROL_LEVEL 7:2 +#define NVCA7E_SET_CSC11COEFFICIENT_C00 (0x000005A0) +#define NVCA7E_SET_CSC11COEFFICIENT_C00_VALUE 20:0 +#define NVCA7E_SET_CSC11COEFFICIENT_C01 (0x000005A4) +#define NVCA7E_SET_CSC11COEFFICIENT_C01_VALUE 20:0 +#define NVCA7E_SET_CSC11COEFFICIENT_C02 (0x000005A8) +#define NVCA7E_SET_CSC11COEFFICIENT_C02_VALUE 20:0 +#define NVCA7E_SET_CSC11COEFFICIENT_C03 (0x000005AC) +#define NVCA7E_SET_CSC11COEFFICIENT_C03_VALUE 20:0 +#define NVCA7E_SET_CSC11COEFFICIENT_C10 (0x000005B0) +#define NVCA7E_SET_CSC11COEFFICIENT_C10_VALUE 20:0 +#define NVCA7E_SET_CSC11COEFFICIENT_C11 (0x000005B4) +#define NVCA7E_SET_CSC11COEFFICIENT_C11_VALUE 20:0 +#define NVCA7E_SET_CSC11COEFFICIENT_C12 (0x000005B8) +#define NVCA7E_SET_CSC11COEFFICIENT_C12_VALUE 20:0 +#define NVCA7E_SET_CSC11COEFFICIENT_C13 (0x000005BC) +#define NVCA7E_SET_CSC11COEFFICIENT_C13_VALUE 20:0 +#define NVCA7E_SET_CSC11COEFFICIENT_C20 (0x000005C0) +#define NVCA7E_SET_CSC11COEFFICIENT_C20_VALUE 20:0 +#define NVCA7E_SET_CSC11COEFFICIENT_C21 (0x000005C4) +#define NVCA7E_SET_CSC11COEFFICIENT_C21_VALUE 20:0 +#define NVCA7E_SET_CSC11COEFFICIENT_C22 (0x000005C8) +#define NVCA7E_SET_CSC11COEFFICIENT_C22_VALUE 20:0 +#define NVCA7E_SET_CSC11COEFFICIENT_C23 (0x000005CC) +#define NVCA7E_SET_CSC11COEFFICIENT_C23_VALUE 20:0 +#define NVCA7E_SET_CLAMP_RANGE (0x000005D0) +#define NVCA7E_SET_CLAMP_RANGE_LOW 15:0 +#define NVCA7E_SET_CLAMP_RANGE_HIGH 31:16 +#define NVCA7E_SW_RESERVED(b) (0x000005D4 + (b)*0x00000004) +#define NVCA7E_SW_RESERVED_VALUE 31:0 +#define NVCA7E_SET_DIRTY_RECT_SIZE (0x000005E4) +#define NVCA7E_SET_DIRTY_RECT_SIZE_WIDTH 15:0 +#define NVCA7E_SET_DIRTY_RECT_SIZE_HEIGHT 31:16 +#define NVCA7E_SET_DIRTY_RECT_POSITION (0x000005E8) +#define NVCA7E_SET_DIRTY_RECT_POSITION_X 15:0 +#define NVCA7E_SET_DIRTY_RECT_POSITION_Y 31:16 +#define NVCA7E_SET_SUPERFRAME (0x000005EC) +#define NVCA7E_SET_SUPERFRAME_ENABLE 0:0 +#define NVCA7E_SET_SUPERFRAME_ENABLE_DISABLE (0x00000000) +#define NVCA7E_SET_SUPERFRAME_ENABLE_ENABLE (0x00000001) +#define NVCA7E_SET_SUPERFRAME_MODE 2:1 +#define NVCA7E_SET_SUPERFRAME_MODE_FIXED (0x00000000) +#define NVCA7E_SET_SUPERFRAME_MODE_DYNAMIC (0x00000001) +#define NVCA7E_SET_SUPERFRAME_MODE_SW (0x00000003) +#define NVCA7E_SET_SUPERFRAME_RATIO_IN 15:8 +#define NVCA7E_SET_SUPERFRAME_RATIO_OUT 23:16 +#define NVCA7E_SET_SUPERFRAME_START_COUNT 31:24 +#define NVCA7E_SET_INFOFRAME_CTRL(b) (0x000005F0 + (b)*0x00000004) +#define NVCA7E_SET_INFOFRAME_CTRL_ENABLE 0:0 +#define NVCA7E_SET_INFOFRAME_CTRL_ENABLE_DISABLE (0x00000000) +#define NVCA7E_SET_INFOFRAME_CTRL_ENABLE_ENABLE (0x00000001) +#define NVCA7E_SET_INFOFRAME_CTRL_LOCATION 5:4 +#define NVCA7E_SET_INFOFRAME_CTRL_LOCATION_VBLANK (0x00000000) +#define NVCA7E_SET_INFOFRAME_CTRL_LOCATION_VSYNC (0x00000001) +#define NVCA7E_SET_INFOFRAME_CTRL_LOCATION_LINE (0x00000002) +#define NVCA7E_SET_INFOFRAME_CTRL_LINE_ID 30:16 +#define NVCA7E_SET_INFOFRAME_CTRL_LINE_ID_REVERSED 31:31 +#define NVCA7E_SET_INFOFRAME_CTRL_LINE_ID_REVERSED_DISABLE (0x00000000) +#define NVCA7E_SET_INFOFRAME_CTRL_LINE_ID_REVERSED_ENABLE (0x00000001) +#define NVCA7E_SET_INFOFRAME_HEADER(b) (0x000005F8 + (b)*0x00000004) +#define NVCA7E_SET_INFOFRAME_HEADER_HB0 7:0 +#define NVCA7E_SET_INFOFRAME_HEADER_HB1 15:8 +#define NVCA7E_SET_INFOFRAME_HEADER_HB2 23:16 +#define NVCA7E_SET_INFOFRAME_HEADER_HB3 31:24 +#define NVCA7E_SET_INFOFRAME_DATA0(b) (0x00000600 + (b)*0x00000004) +#define NVCA7E_SET_INFOFRAME_DATA0_DB0 7:0 +#define NVCA7E_SET_INFOFRAME_DATA0_DB1 15:8 +#define NVCA7E_SET_INFOFRAME_DATA0_DB2 23:16 +#define NVCA7E_SET_INFOFRAME_DATA0_DB3 31:24 +#define NVCA7E_SET_INFOFRAME_DATA1(b) (0x00000608 + (b)*0x00000004) +#define NVCA7E_SET_INFOFRAME_DATA1_DB4 7:0 +#define NVCA7E_SET_INFOFRAME_DATA1_DB5 15:8 +#define NVCA7E_SET_INFOFRAME_DATA1_DB6 23:16 +#define NVCA7E_SET_INFOFRAME_DATA1_DB7 31:24 +#define NVCA7E_SET_INFOFRAME_DATA2(b) (0x00000610 + (b)*0x00000004) +#define NVCA7E_SET_INFOFRAME_DATA2_DB8 7:0 +#define NVCA7E_SET_INFOFRAME_DATA2_DB9 15:8 +#define NVCA7E_SET_INFOFRAME_DATA2_DB10 23:16 +#define NVCA7E_SET_INFOFRAME_DATA2_DB11 31:24 +#define NVCA7E_SET_INFOFRAME_DATA3(b) (0x00000618 + (b)*0x00000004) +#define NVCA7E_SET_INFOFRAME_DATA3_DB12 7:0 +#define NVCA7E_SET_INFOFRAME_DATA3_DB13 15:8 +#define NVCA7E_SET_INFOFRAME_DATA3_DB14 23:16 +#define NVCA7E_SET_INFOFRAME_DATA3_DB15 31:24 +#define NVCA7E_SET_INFOFRAME_DATA4(b) (0x00000620 + (b)*0x00000004) +#define NVCA7E_SET_INFOFRAME_DATA4_DB16 7:0 +#define NVCA7E_SET_INFOFRAME_DATA4_DB17 15:8 +#define NVCA7E_SET_INFOFRAME_DATA4_DB18 23:16 +#define NVCA7E_SET_INFOFRAME_DATA4_DB19 31:24 +#define NVCA7E_SET_INFOFRAME_DATA5(b) (0x00000628 + (b)*0x00000004) +#define NVCA7E_SET_INFOFRAME_DATA5_DB20 7:0 +#define NVCA7E_SET_INFOFRAME_DATA5_DB21 15:8 +#define NVCA7E_SET_INFOFRAME_DATA5_DB22 23:16 +#define NVCA7E_SET_INFOFRAME_DATA5_DB23 31:24 +#define NVCA7E_SET_INFOFRAME_DATA6(b) (0x00000630 + (b)*0x00000004) +#define NVCA7E_SET_INFOFRAME_DATA6_DB24 7:0 +#define NVCA7E_SET_INFOFRAME_DATA6_DB25 15:8 +#define NVCA7E_SET_INFOFRAME_DATA6_DB26 23:16 +#define NVCA7E_SET_INFOFRAME_DATA6_DB27 31:24 +#define NVCA7E_SET_INFOFRAME_DATA7(b) (0x00000638 + (b)*0x00000004) +#define NVCA7E_SET_INFOFRAME_DATA7_DB28 7:0 +#define NVCA7E_SET_INFOFRAME_DATA7_DB29 15:8 +#define NVCA7E_SET_INFOFRAME_DATA7_DB30 23:16 +#define NVCA7E_SET_INFOFRAME_DATA7_DB31 31:24 +#define NVCA7E_SET_SURFACE_ADDRESS_HI_SEMAPHORE (0x00000640) +#define NVCA7E_SET_SURFACE_ADDRESS_HI_SEMAPHORE_ADDRESS_HI 31:0 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE (0x00000644) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ADDRESS_LO 31:4 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET 3:2 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_IOVA (0x00000000) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE 0:0 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE_DISABLE (0x00000000) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE_ENABLE (0x00000001) +#define NVCA7E_SET_SURFACE_ADDRESS_HI_ACQ_SEMAPHORE (0x00000648) +#define NVCA7E_SET_SURFACE_ADDRESS_HI_ACQ_SEMAPHORE_ADDRESS_HI 31:0 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE (0x0000064C) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ADDRESS_LO 31:4 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET 3:2 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_IOVA (0x00000000) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE 0:0 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE_DISABLE (0x00000000) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE_ENABLE (0x00000001) +#define NVCA7E_SET_SURFACE_ADDRESS_HI_NOTIFIER (0x00000650) +#define NVCA7E_SET_SURFACE_ADDRESS_HI_NOTIFIER_ADDRESS_HI 31:0 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER (0x00000654) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ADDRESS_LO 31:4 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET 3:2 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_IOVA (0x00000000) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE 0:0 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_DISABLE (0x00000000) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_ENABLE (0x00000001) +#define NVCA7E_SET_SURFACE_ADDRESS_HI_ISO(b) (0x00000658 + (b)*0x00000004) +#define NVCA7E_SET_SURFACE_ADDRESS_HI_ISO_ADDRESS_HI 31:0 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO(b) (0x00000670 + (b)*0x00000004) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_ADDRESS_LO 31:4 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET 3:2 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_IOVA (0x00000000) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_KIND 1:1 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_KIND_PITCH (0x00000000) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_KIND_BLOCKLINEAR (0x00000001) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE 0:0 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE_DISABLE (0x00000000) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE_ENABLE (0x00000001) +#define NVCA7E_SET_SURFACE_ADDRESS_HI_ILUT (0x00000688) +#define NVCA7E_SET_SURFACE_ADDRESS_HI_ILUT_ADDRESS_HI 31:0 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT (0x0000068C) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_ADDRESS_LO 31:4 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET 3:2 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_IOVA (0x00000000) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE 0:0 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE_DISABLE (0x00000000) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE_ENABLE (0x00000001) +#define NVCA7E_SET_SURFACE_ADDRESS_HI_TMO_LUT (0x00000690) +#define NVCA7E_SET_SURFACE_ADDRESS_HI_TMO_LUT_ADDRESS_HI 31:0 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_TMO_LUT (0x00000694) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ADDRESS_LO 31:4 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET 3:2 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_IOVA (0x00000000) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE 0:0 +#define NVCA7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE_DISABLE (0x00000000) +#define NVCA7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE_ENABLE (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clca7e_h diff --git a/userspace/sdks/nv570/inc/class/clcab5.h b/userspace/sdks/nv570/inc/class/clcab5.h new file mode 100644 index 0000000..bd23835 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcab5.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clcab5_h_ +#define _clcab5_h_ + +#define BLACKWELL_DMA_COPY_B (0x0000CAB5) + +#define NVCAB5_LAUNCH_DMA (0x00000300) +#define NVCAB5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVCAB5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVCAB5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVCAB5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVCAB5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PREFETCH (0x00000003) + +#define NVCAB5_REQ_ATTR (0x00000754) +#define NVCAB5_REQ_ATTR_PREFETCH_L2_CLASS 1:0 +#define NVCAB5_REQ_ATTR_PREFETCH_L2_CLASS_EVICT_FIRST (0x00000000) +#define NVCAB5_REQ_ATTR_PREFETCH_L2_CLASS_EVICT_NORMAL (0x00000001) +#define NVCAB5_REQ_ATTR_PREFETCH_L2_CLASS_EVICT_LAST (0x00000002) +#define NVCAB5_REQ_ATTR_PREFETCH_L2_CLASS_EVICT_DEMOTE (0x00000003) + +#endif /* _clcab5_h_ */ + diff --git a/userspace/sdks/nv570/inc/class/clcb33.h b/userspace/sdks/nv570/inc/class/clcb33.h new file mode 100644 index 0000000..c0e1934 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcb33.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clcb33.finn +// + +#define NV_CONFIDENTIAL_COMPUTE (0xcb33U) /* finn: Evaluated from "NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS_MESSAGE_ID" */ + +#define NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS_MESSAGE_ID (0xcb33U) + +typedef struct NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS { + NvHandle hClient; +} NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS; + diff --git a/userspace/sdks/nv570/inc/class/clcb70.h b/userspace/sdks/nv570/inc/class/clcb70.h new file mode 100644 index 0000000..86a14ea --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcb70.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clcb70.finn +// + +#define NVCB70_DISPLAY (0xcb70U) /* finn: Evaluated from "NVCB70_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NVCB70_ALLOCATION_PARAMETERS_MESSAGE_ID (0xcb70U) + +typedef struct NVCB70_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numDsis; // Number of DSIs in this chip/display +} NVCB70_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clcb71.h b/userspace/sdks/nv570/inc/class/clcb71.h new file mode 100644 index 0000000..bdeda14 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcb71.h @@ -0,0 +1,186 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clcb71_h_ +#define _clcb71_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVCB71_DISP_SF_USER (0x000CB71) + +typedef volatile struct _clcb71_tag0 { + NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x000D0FFF:0x000D0000 */ +} _NvCB71DispSfUser, NvCB71DispSfUserMap; + +#define NVCB71_SF_HDMI_INFO_CTRL(i,j) (0x000E0000-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVCB71_SF_HDMI_INFO_CTRL__SIZE_1 8 /* */ +#define NVCB71_SF_HDMI_INFO_CTRL__SIZE_2 3 /* */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x000E0000-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 8 /* */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW 9:9 /* RWIVF */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_STATUS(i) (0x000E0004-0x000E0000+(i)*1024) /* R--4A */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1 8 /* */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT 0:0 /* R-IVF */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT 0x00000000 /* R-I-V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x000E0008-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 8 /* */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x000E000C-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 8 /* */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x000E0010-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 8 /* */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x000E0014-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 8 /* */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x000E0018-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 8 /* */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW(i) (0x000E001C-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW__SIZE_1 8 /* */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL(i,j) (0x000E0130-0x000E0000+(i)*1024+(j)*8) /* RW-4A */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL__SIZE_1 8 /* */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL__SIZE_2 10 /* */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE 3:1 /* RWIVF */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_ALWAYS 0x00000000 /* RWI-V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_ONCE 0x00000001 /* RW--V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_ALWAYS 0x00000002 /* RW--V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_ONCE 0x00000003 /* RW--V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_TRIGGER 0x00000004 /* RW--V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_LOC 5:4 /* RWIVF */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_LOC_VBLANK 0x00000000 /* RWI-V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_LOC_VSYNC 0x00000001 /* RW--V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_LOC_LINE 0x00000002 /* RW--V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_OFFSET 10:6 /* RWIVF */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_SIZE 18:14 /* RWIVF */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_SIZE_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_BUSY 22:22 /* R-IVF */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_BUSY_NO 0x00000000 /* R-I-V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_BUSY_YES 0x00000001 /* R---V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_SENT 23:23 /* RWIVF */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_SENT_NO 0x00000000 /* R-I-V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_SENT_YES 0x00000001 /* R---V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_SENT_CLEAR 0x00000001 /* -W--C */ +#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG(i,j) (0x000E0134-0x000E0000+(i)*1024+(j)*8) /* RW-4A */ +#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG__SIZE_1 8 /* */ +#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG__SIZE_2 10 /* */ +#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_FID 7:0 /* RWIVF */ +#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_FID_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID 23:8 /* RWIVF */ +#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED 24:24 /* RWIVF */ +#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED_NO 0x00000000 /* RWI-V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED_YES 0x00000001 /* RW--V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN 25:25 /* RWIVF */ +#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN_NO 0x00000000 /* RWI-V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN_YES 0x00000001 /* RW--V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM 29:29 /* RWIVF */ +#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM_NO 0x00000000 /* RWI-V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM_YES 0x00000001 /* RW--V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_NEW 30:30 /* RWIVF */ +#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_NEW_INIT 0x00000000 /* R-I-V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_NEW_DONE 0x00000000 /* R---V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_NEW_PENDING 0x00000001 /* R---T */ +#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_NEW_TRIGGER 0x00000001 /* -W--T */ +#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL 31:31 /* RWIVF */ +#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL_ACT 0x00000000 /* RWI-V */ +#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL_ARM 0x00000001 /* RW--V */ +#define NVCB71_SF_GENERIC_INFOFRAME_DATA_CTRL(i) (0x000E03F0-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCB71_SF_GENERIC_INFOFRAME_DATA_CTRL__SIZE_1 8 /* */ +#define NVCB71_SF_GENERIC_INFOFRAME_DATA_CTRL_OFFSET 4:0 /* RWIVF */ +#define NVCB71_SF_GENERIC_INFOFRAME_DATA_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_GENERIC_INFOFRAME_DATA(i) (0x000E03F4-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCB71_SF_GENERIC_INFOFRAME_DATA__SIZE_1 8 /* */ +#define NVCB71_SF_GENERIC_INFOFRAME_DATA_BYTE0 7:0 /* RWIVF */ +#define NVCB71_SF_GENERIC_INFOFRAME_DATA_BYTE0_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_GENERIC_INFOFRAME_DATA_BYTE1 15:8 /* RWIVF */ +#define NVCB71_SF_GENERIC_INFOFRAME_DATA_BYTE1_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_GENERIC_INFOFRAME_DATA_BYTE2 23:16 /* RWIVF */ +#define NVCB71_SF_GENERIC_INFOFRAME_DATA_BYTE2_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_GENERIC_INFOFRAME_DATA_BYTE3 31:24 /* RWIVF */ +#define NVCB71_SF_GENERIC_INFOFRAME_DATA_BYTE3_INIT 0x00000000 /* RWI-V */ +#define NVCB71_SF_GENERIC_INFOFRAME_MISC_CTRL(i) (0x000E03F8-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCB71_SF_GENERIC_INFOFRAME_MISC_CTRL__SIZE_1 8 /* */ +#define NVCB71_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY 1:1 /* RWIVF */ +#define NVCB71_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY_HIGH 0x00000000 /* RW--V */ +#define NVCB71_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY_LOW 0x00000001 /* RWI-V */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _clcb71_h_ diff --git a/userspace/sdks/nv570/inc/class/clcb73.h b/userspace/sdks/nv570/inc/class/clcb73.h new file mode 100644 index 0000000..f15d092 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcb73.h @@ -0,0 +1,915 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clcb73_h_ +#define _clcb73_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVCB73_DISP_CAPABILITIES 0xCB73 + +typedef volatile struct _clcb73_tag0 { + NvU32 dispCapabilities[0x400]; +} _NvCB73DispCapabilities,NvCB73DispCapabilities_Map ; + + +#define NVCB73_SYS_CAP 0x0 /* RW-4R */ +#define NVCB73_SYS_CAP_HEAD0_EXISTS 0:0 /* RWIVF */ +#define NVCB73_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAP_HEAD1_EXISTS 1:1 /* RWIVF */ +#define NVCB73_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAP_HEAD2_EXISTS 2:2 /* RWIVF */ +#define NVCB73_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAP_HEAD3_EXISTS 3:3 /* RWIVF */ +#define NVCB73_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAP_HEAD4_EXISTS 4:4 /* RWIVF */ +#define NVCB73_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAP_HEAD5_EXISTS 5:5 /* RWIVF */ +#define NVCB73_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAP_HEAD6_EXISTS 6:6 /* RWIVF */ +#define NVCB73_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAP_HEAD7_EXISTS 7:7 /* RWIVF */ +#define NVCB73_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVCB73_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */ +#define NVCB73_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAP_SOR0_EXISTS 8:8 /* RWIVF */ +#define NVCB73_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAP_SOR1_EXISTS 9:9 /* RWIVF */ +#define NVCB73_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAP_SOR2_EXISTS 10:10 /* RWIVF */ +#define NVCB73_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAP_SOR3_EXISTS 11:11 /* RWIVF */ +#define NVCB73_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAP_SOR4_EXISTS 12:12 /* RWIVF */ +#define NVCB73_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAP_SOR5_EXISTS 13:13 /* RWIVF */ +#define NVCB73_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAP_SOR6_EXISTS 14:14 /* RWIVF */ +#define NVCB73_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAP_SOR7_EXISTS 15:15 /* RWIVF */ +#define NVCB73_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* RWIVF */ +#define NVCB73_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */ +#define NVCB73_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAP_RISCV0_EXISTS 16:16 /* RWIVF */ +#define NVCB73_SYS_CAP_RISCV0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAP_RISCV0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAP_DSI0_EXISTS 20:20 /* RWIVF */ +#define NVCB73_SYS_CAP_DSI0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAP_DSI0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAP_DSI1_EXISTS 21:21 /* RWIVF */ +#define NVCB73_SYS_CAP_DSI1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAP_DSI1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAP_DSI2_EXISTS 22:22 /* RWIVF */ +#define NVCB73_SYS_CAP_DSI2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAP_DSI2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAP_DSI3_EXISTS 23:23 /* RWIVF */ +#define NVCB73_SYS_CAP_DSI3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAP_DSI3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAP_DSI_EXISTS(i) (20+(i)):(20+(i)) /* RWIVF */ +#define NVCB73_SYS_CAP_DSI_EXISTS__SIZE_1 4 /* */ +#define NVCB73_SYS_CAP_DSI_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAP_DSI_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB 0x4 /* RW-4R */ +#define NVCB73_SYS_CAPB_WINDOW0_EXISTS 0:0 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW1_EXISTS 1:1 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW2_EXISTS 2:2 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW3_EXISTS 3:3 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW4_EXISTS 4:4 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW5_EXISTS 5:5 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW6_EXISTS 6:6 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW7_EXISTS 7:7 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW8_EXISTS 8:8 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW8_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW8_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW9_EXISTS 9:9 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW9_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW9_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW10_EXISTS 10:10 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW10_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW10_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW11_EXISTS 11:11 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW11_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW11_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW12_EXISTS 12:12 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW12_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW12_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW13_EXISTS 13:13 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW13_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW13_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW14_EXISTS 14:14 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW14_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW14_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW15_EXISTS 15:15 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW15_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW15_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW16_EXISTS 16:16 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW16_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW16_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW17_EXISTS 17:17 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW17_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW17_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW18_EXISTS 18:18 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW18_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW18_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW19_EXISTS 19:19 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW19_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW19_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW20_EXISTS 20:20 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW20_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW20_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW21_EXISTS 21:21 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW21_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW21_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW22_EXISTS 22:22 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW22_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW22_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW23_EXISTS 23:23 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW23_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW23_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW24_EXISTS 24:24 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW24_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW24_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW25_EXISTS 25:25 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW25_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW25_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW26_EXISTS 26:26 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW26_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW26_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW27_EXISTS 27:27 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW27_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW27_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW28_EXISTS 28:28 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW28_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW28_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW29_EXISTS 29:29 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW29_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW29_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW30_EXISTS 30:30 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW30_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW30_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW31_EXISTS 31:31 /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW31_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW31_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVCB73_SYS_CAPB_WINDOW_EXISTS__SIZE_1 32 /* */ +#define NVCB73_SYS_CAPB_WINDOW_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPB_WINDOW_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPC 0x20 /* RW-4R */ +#define NVCB73_SYS_CAPC_TILE0_EXISTS 0:0 /* RWIVF */ +#define NVCB73_SYS_CAPC_TILE0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE1_EXISTS 1:1 /* RWIVF */ +#define NVCB73_SYS_CAPC_TILE1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE2_EXISTS 2:2 /* RWIVF */ +#define NVCB73_SYS_CAPC_TILE2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE3_EXISTS 3:3 /* RWIVF */ +#define NVCB73_SYS_CAPC_TILE3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE4_EXISTS 4:4 /* RWIVF */ +#define NVCB73_SYS_CAPC_TILE4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE5_EXISTS 5:5 /* RWIVF */ +#define NVCB73_SYS_CAPC_TILE5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE6_EXISTS 6:6 /* RWIVF */ +#define NVCB73_SYS_CAPC_TILE6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE7_EXISTS 7:7 /* RWIVF */ +#define NVCB73_SYS_CAPC_TILE7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVCB73_SYS_CAPC_TILE_EXISTS__SIZE_1 8 /* */ +#define NVCB73_SYS_CAPC_TILE_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE0_SUPPORT_MULTI_TILE 8:8 /* RWIVF */ +#define NVCB73_SYS_CAPC_TILE0_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE0_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE1_SUPPORT_MULTI_TILE 9:9 /* RWIVF */ +#define NVCB73_SYS_CAPC_TILE1_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE1_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE2_SUPPORT_MULTI_TILE 10:10 /* RWIVF */ +#define NVCB73_SYS_CAPC_TILE2_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE2_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE3_SUPPORT_MULTI_TILE 11:11 /* RWIVF */ +#define NVCB73_SYS_CAPC_TILE3_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE3_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE4_SUPPORT_MULTI_TILE 12:12 /* RWIVF */ +#define NVCB73_SYS_CAPC_TILE4_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE4_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE5_SUPPORT_MULTI_TILE 13:13 /* RWIVF */ +#define NVCB73_SYS_CAPC_TILE5_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE5_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE6_SUPPORT_MULTI_TILE 14:14 /* RWIVF */ +#define NVCB73_SYS_CAPC_TILE6_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE6_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE7_SUPPORT_MULTI_TILE 15:15 /* RWIVF */ +#define NVCB73_SYS_CAPC_TILE7_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE7_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE(i) (8+(i)):(8+(i)) /* RWIVF */ +#define NVCB73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE__SIZE_1 8 /* */ +#define NVCB73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPC_MERGER_TILE_BUFFER_SIZE 31:16 /* RWIUF */ +#define NVCB73_SYS_CAPD 0x2c /* RW-4R */ +#define NVCB73_SYS_CAPD_NUM_TELLTALE_REGIONS 4:0 /* RWIUF */ +#define NVCB73_SYS_CAPD_NUM_FROZEN_FRAME_REGIONS 12:8 /* RWIUF */ +#define NVCB73_SYS_CAPD_NUM_ROI 20:16 /* RWIUF */ +#define NVCB73_SYS_CAPD_AE_SDP_EXISTS 30:30 /* RWIVF */ +#define NVCB73_SYS_CAPD_AE_SDP_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPD_AE_SDP_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPD_AMSS_EXISTS 31:31 /* RWIVF */ +#define NVCB73_SYS_CAPD_AMSS_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPD_AMSS_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE 0x34 /* RW-4R */ +#define NVCB73_SYS_CAPE_VIRWIN0_EXISTS 0:0 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN1_EXISTS 1:1 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN2_EXISTS 2:2 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN3_EXISTS 3:3 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN4_EXISTS 4:4 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN5_EXISTS 5:5 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN6_EXISTS 6:6 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN7_EXISTS 7:7 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN8_EXISTS 8:8 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN8_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN8_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN9_EXISTS 9:9 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN9_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN9_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN10_EXISTS 10:10 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN10_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN10_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN11_EXISTS 11:11 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN11_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN11_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN12_EXISTS 12:12 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN12_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN12_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN13_EXISTS 13:13 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN13_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN13_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN14_EXISTS 14:14 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN14_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN14_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN15_EXISTS 15:15 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN15_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN15_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN16_EXISTS 16:16 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN16_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN16_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN17_EXISTS 17:17 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN17_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN17_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN18_EXISTS 18:18 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN18_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN18_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN19_EXISTS 19:19 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN19_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN19_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN20_EXISTS 20:20 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN20_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN20_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN21_EXISTS 21:21 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN21_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN21_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN22_EXISTS 22:22 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN22_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN22_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN23_EXISTS 23:23 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN23_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN23_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN24_EXISTS 24:24 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN24_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN24_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN25_EXISTS 25:25 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN25_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN25_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN26_EXISTS 26:26 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN26_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN26_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN27_EXISTS 27:27 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN27_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN27_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN28_EXISTS 28:28 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN28_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN28_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN29_EXISTS 29:29 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN29_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN29_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN30_EXISTS 30:30 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN30_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN30_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN31_EXISTS 31:31 /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN31_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN31_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVCB73_SYS_CAPE_VIRWIN_EXISTS__SIZE_1 32 /* */ +#define NVCB73_SYS_CAPE_VIRWIN_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_SYS_CAPE_VIRWIN_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_MISC_CAPA_NUM_VMS 17:13 /* RWIUF */ +#define NVCB73_LINK_CAP 0x30 /* RW-4R */ +#define NVCB73_LINK_CAP_PHYCTRL0_EXISTS 0:0 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL1_EXISTS 1:1 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL2_EXISTS 2:2 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL3_EXISTS 3:3 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL4_EXISTS 4:4 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL5_EXISTS 5:5 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL6_EXISTS 6:6 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL7_EXISTS 7:7 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL8_EXISTS 8:8 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL8_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL8_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL9_EXISTS 9:9 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL9_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL9_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL10_EXISTS 10:10 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL10_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL10_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL11_EXISTS 11:11 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL11_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL11_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL12_EXISTS 12:12 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL12_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL12_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL13_EXISTS 13:13 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL13_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL13_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL14_EXISTS 14:14 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL14_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL14_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL15_EXISTS 15:15 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL15_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL15_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL16_EXISTS 16:16 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL16_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL16_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL17_EXISTS 17:17 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL17_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL17_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL18_EXISTS 18:18 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL18_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL18_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL19_EXISTS 19:19 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL19_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL19_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL20_EXISTS 20:20 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL20_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL20_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL21_EXISTS 21:21 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL21_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL21_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL22_EXISTS 22:22 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL22_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL22_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL23_EXISTS 23:23 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL23_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL23_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL24_EXISTS 24:24 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL24_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL24_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL25_EXISTS 25:25 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL25_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL25_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL26_EXISTS 26:26 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL26_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL26_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL27_EXISTS 27:27 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL27_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL27_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL28_EXISTS 28:28 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL28_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL28_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL29_EXISTS 29:29 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL29_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL29_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL30_EXISTS 30:30 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL30_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL30_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL31_EXISTS 31:31 /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL31_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL31_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVCB73_LINK_CAP_PHYCTRL_EXISTS__SIZE_1 32 /* */ +#define NVCB73_LINK_CAP_PHYCTRL_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCB73_LINK_CAP_PHYCTRL_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPA 0x10 /* RW-4R */ +#define NVCB73_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES 15:0 /* RWIUF */ +#define NVCB73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH 17:16 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B 0x00000002 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B 0x00000003 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_ROTATION 18:18 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_ROTATION_FALSE 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_ROTATION_TRUE 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_PLANAR 19:19 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_PLANAR_FALSE 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_PLANAR_TRUE 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_VGA 20:20 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION 21:21 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_FALSE 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_TRUE 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MSCG 22:22 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MSCG_FALSE 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MSCG_TRUE 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH 23:23 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_FALSE 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_TRUE 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MSCG_LPS 26:26 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MSCG_LPS_FALSE 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MSCG_LPS_TRUE 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION 31:30 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B 0x00000002 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B 0x00000003 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPC 0x18 /* RW-4R */ +#define NVCB73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE 1:0 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_32B 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_64B 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_128B 0x00000002 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_256B 0x00000003 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED 6:4 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_NONE 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_TWO 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_FOUR 0x00000002 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_EIGHT 0x00000003 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_SIXTEEN 0x00000004 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR 11:11 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_FALSE 0x00000000 /* RWI-V */ +#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_TRUE 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP 12:12 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_FALSE 0x00000000 /* RWI-V */ +#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_TRUE 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_MEMPOOL_YUV_COMPRESSION 13:13 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_MEMPOOL_YUV_COMPRESSION_FALSE 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_MEMPOOL_YUV_COMPRESSION_TRUE 0x00000001 /* RWI-V */ +#define NVCB73_IHUB_COMMON_CAPE 0x24 /* RW-4R */ +#define NVCB73_IHUB_COMMON_CAPE_PHYWIN_BUFFER_SIZE 15:0 /* RWIUF */ +#define NVCB73_IHUB_COMMON_CAPF 0x28 /* RW-4R */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN0_SUPPORT_MULTI_TILE 0:0 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN0_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN0_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN1_SUPPORT_MULTI_TILE 1:1 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN1_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN1_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN2_SUPPORT_MULTI_TILE 2:2 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN2_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN2_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN3_SUPPORT_MULTI_TILE 3:3 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN3_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN3_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN4_SUPPORT_MULTI_TILE 4:4 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN4_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN4_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN5_SUPPORT_MULTI_TILE 5:5 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN5_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN5_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN6_SUPPORT_MULTI_TILE 6:6 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN6_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN6_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN7_SUPPORT_MULTI_TILE 7:7 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN7_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN7_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN8_SUPPORT_MULTI_TILE 8:8 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN8_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN8_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN9_SUPPORT_MULTI_TILE 9:9 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN9_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN9_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN10_SUPPORT_MULTI_TILE 10:10 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN10_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN10_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN11_SUPPORT_MULTI_TILE 11:11 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN11_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN11_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN12_SUPPORT_MULTI_TILE 12:12 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN12_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN12_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN13_SUPPORT_MULTI_TILE 13:13 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN13_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN13_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN14_SUPPORT_MULTI_TILE 14:14 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN14_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN14_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN15_SUPPORT_MULTI_TILE 15:15 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN15_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN15_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN16_SUPPORT_MULTI_TILE 16:16 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN16_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN16_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN17_SUPPORT_MULTI_TILE 17:17 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN17_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN17_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN18_SUPPORT_MULTI_TILE 18:18 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN18_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN18_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN19_SUPPORT_MULTI_TILE 19:19 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN19_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN19_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN20_SUPPORT_MULTI_TILE 20:20 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN20_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN20_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN21_SUPPORT_MULTI_TILE 21:21 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN21_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN21_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN22_SUPPORT_MULTI_TILE 22:22 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN22_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN22_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN23_SUPPORT_MULTI_TILE 23:23 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN23_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN23_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN24_SUPPORT_MULTI_TILE 24:24 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN24_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN24_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN25_SUPPORT_MULTI_TILE 25:25 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN25_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN25_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN26_SUPPORT_MULTI_TILE 26:26 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN26_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN26_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN27_SUPPORT_MULTI_TILE 27:27 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN27_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN27_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN28_SUPPORT_MULTI_TILE 28:28 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN28_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN28_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN29_SUPPORT_MULTI_TILE 29:29 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN29_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN29_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN30_SUPPORT_MULTI_TILE 30:30 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN30_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN30_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN31_SUPPORT_MULTI_TILE 31:31 /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN31_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN31_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE__SIZE_1 32 /* */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCB73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPA(i) (0x680+(i)*32) /* RW-4A */ +#define NVCB73_POSTCOMP_HDR_CAPA__SIZE_1 8 /* */ +#define NVCB73_POSTCOMP_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPA_OCSC0_PRESENT 16:16 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPA_OCSC0_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPA_OCSC0_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPA_OCSC1_PRESENT 17:17 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPA_OCSC1_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPA_OCSC1_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPA_SCLR_PRESENT 18:18 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPA_HCLPF_PRESENT 19:19 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPA_HCLPF_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPA_HCLPF_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPA_DTH_PRESENT 20:20 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPA_DTH_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPA_DTH_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPA_OSCAN_PRESENT 21:21 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPA_OSCAN_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPA_OSCAN_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPA_DSC_PRESENT 22:22 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPA_DSC_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPA_DSC_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPA_VFILTER_PRESENT 23:23 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPA_VFILTER_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPA_VFILTER_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPA_LTM_PRESENT 25:25 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPA_LTM_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPA_LTM_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPB(i) (0x684+(i)*32) /* RW-4A */ +#define NVCB73_POSTCOMP_HDR_CAPB__SIZE_1 8 /* */ +#define NVCB73_POSTCOMP_HDR_CAPB_VGA 0:0 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPB_VGA_TRUE 0x00000001 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPB_VGA_FALSE 0x00000000 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPB_OLUT_SZ 12:1 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPB_OLUT_LOGNR 15:13 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD 17:17 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPB_OLUT_DIRECT 18:18 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPB_OLUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPB_OLUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPC(i) (0x688+(i)*32) /* RW-4A */ +#define NVCB73_POSTCOMP_HDR_CAPC__SIZE_1 8 /* */ +#define NVCB73_POSTCOMP_HDR_CAPC_OCSC0_PRECISION 4:0 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPC_OCSC1_PRECISION 12:8 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP 13:13 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_SF_PRECISION 20:16 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_CI_PRECISION 24:21 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB 25:25 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPD(i) (0x68c+(i)*32) /* RW-4A */ +#define NVCB73_POSTCOMP_HDR_CAPD__SIZE_1 8 /* */ +#define NVCB73_POSTCOMP_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPE(i) (0x690+(i)*32) /* RW-4A */ +#define NVCB73_POSTCOMP_HDR_CAPE__SIZE_1 8 /* */ +#define NVCB73_POSTCOMP_HDR_CAPE_DSC_MAXLINEWIDTH 15:0 /* RWIUF */ +#define NVCB73_POSTCOMP_HDR_CAPE_DSC_NATIVE422 16:16 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPE_DSC_NATIVE422_TRUE 0x00000001 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPE_DSC_NATIVE422_FALSE 0x00000000 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPE_DSC_NATIVE420 17:17 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPE_DSC_NATIVE420_TRUE 0x00000001 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPE_DSC_NATIVE420_FALSE 0x00000000 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_PRESENT 18:18 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE 21:19 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_9x9x9 0x00000000 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_17x17x17 0x00000001 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_25x25x25 0x00000002 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_33x33x33 0x00000003 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_4 0x00000004 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_5 0x00000005 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_6 0x00000006 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_7 0x00000007 /* RW--V */ +#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_NUM_CURVES 23:22 /* RWIUF */ +#define NVCB73_POSTCOMP_HDR_CAPF(i) (0x694+(i)*32) /* RW-4A */ +#define NVCB73_POSTCOMP_HDR_CAPF__SIZE_1 8 /* */ +#define NVCB73_POSTCOMP_HDR_CAPF_VFILTER_MAX_PIXELS 15:0 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPF_LTM_MAX_PIXELS 31:16 /* RWIVF */ +#define NVCB73_POSTCOMP_HDR_CAPG(i) (0x698+(i)*32) /* RW-4A */ +#define NVCB73_POSTCOMP_HDR_CAPG__SIZE_1 8 /* */ +#define NVCB73_POSTCOMP_HDR_CAPG_CMI_SZ 11:0 /* RWIUF */ +#define NVCB73_POSTCOMP_HDR_CAPG_CMI_LOGNR 14:12 /* RWIUF */ +#define NVCB73_POSTCOMP_HDR_CAPG_CMO_SZ 26:15 /* RWIUF */ +#define NVCB73_POSTCOMP_HDR_CAPG_CMO_LOGNR 29:27 /* RWIUF */ +#define NVCB73_SOR_CAP(i) (0x144+(i)*8) /* RW-4A */ +#define NVCB73_SOR_CAP__SIZE_1 8 /* */ +#define NVCB73_SOR_CAP_SINGLE_LVDS_18 0:0 /* RWIVF */ +#define NVCB73_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVCB73_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVCB73_SOR_CAP_SINGLE_LVDS_24 1:1 /* RWIVF */ +#define NVCB73_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVCB73_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVCB73_SOR_CAP_DUAL_LVDS_18 2:2 /* RWIVF */ +#define NVCB73_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVCB73_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVCB73_SOR_CAP_DUAL_LVDS_24 3:3 /* RWIVF */ +#define NVCB73_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVCB73_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVCB73_SOR_CAP_DP_DUAL_MODE 4:4 /* RWIVF */ +#define NVCB73_SOR_CAP_DP_DUAL_MODE_FALSE 0x00000000 /* RW--V */ +#define NVCB73_SOR_CAP_DP_DUAL_MODE_TRUE 0x00000001 /* RW--V */ +#define NVCB73_SOR_CAP_SINGLE_TMDS_A 8:8 /* RWIVF */ +#define NVCB73_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* RW--V */ +#define NVCB73_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* RW--V */ +#define NVCB73_SOR_CAP_SINGLE_TMDS_B 9:9 /* RWIVF */ +#define NVCB73_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* RW--V */ +#define NVCB73_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* RW--V */ +#define NVCB73_SOR_CAP_DUAL_TMDS 11:11 /* RWIVF */ +#define NVCB73_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* RW--V */ +#define NVCB73_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* RW--V */ +#define NVCB73_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* RWIVF */ +#define NVCB73_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* RW--V */ +#define NVCB73_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* RW--V */ +#define NVCB73_SOR_CAP_DP_TUNNELING_OVER_USB4 15:15 /* RWIVF */ +#define NVCB73_SOR_CAP_DP_TUNNELING_OVER_USB4_FALSE 0x00000000 /* RW--V */ +#define NVCB73_SOR_CAP_DP_TUNNELING_OVER_USB4_TRUE 0x00000001 /* RW--V */ +#define NVCB73_SOR_CAP_SDI 16:16 /* RWIVF */ +#define NVCB73_SOR_CAP_SDI_FALSE 0x00000000 /* RW--V */ +#define NVCB73_SOR_CAP_SDI_TRUE 0x00000001 /* RW--V */ +#define NVCB73_SOR_CAP_DP_DUAL_MST 23:23 /* RWIVF */ +#define NVCB73_SOR_CAP_DP_DUAL_MST_FALSE 0x00000000 /* RW--V */ +#define NVCB73_SOR_CAP_DP_DUAL_MST_TRUE 0x00000001 /* RW--V */ +#define NVCB73_SOR_CAP_DP_A 24:24 /* RWIVF */ +#define NVCB73_SOR_CAP_DP_A_FALSE 0x00000000 /* RW--V */ +#define NVCB73_SOR_CAP_DP_A_TRUE 0x00000001 /* RW--V */ +#define NVCB73_SOR_CAP_DP_B 25:25 /* RWIVF */ +#define NVCB73_SOR_CAP_DP_B_FALSE 0x00000000 /* RW--V */ +#define NVCB73_SOR_CAP_DP_B_TRUE 0x00000001 /* RW--V */ +#define NVCB73_SOR_CAP_DP_INTERLACE 26:26 /* RWIVF */ +#define NVCB73_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* RW--V */ +#define NVCB73_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* RW--V */ +#define NVCB73_SOR_CAP_DP_8_LANES 27:27 /* RWIVF */ +#define NVCB73_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* RW--V */ +#define NVCB73_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* RW--V */ +#define NVCB73_SOR_CAP_HDMI_FRL 28:28 /* RWIVF */ +#define NVCB73_SOR_CAP_HDMI_FRL_FALSE 0x00000000 /* RW--V */ +#define NVCB73_SOR_CAP_HDMI_FRL_TRUE 0x00000001 /* RW--V */ +#define NVCB73_SOR_CAP_HDMI_FRL_YUV422 29:29 /* RWIVF */ +#define NVCB73_SOR_CAP_HDMI_FRL_YUV422_FALSE 0x00000000 /* RW--V */ +#define NVCB73_SOR_CAP_HDMI_FRL_YUV422_TRUE 0x00000001 /* RW--V */ +#define NVCB73_SOR_CAP_DP_128B132B 30:30 /* RWIVF */ +#define NVCB73_SOR_CAP_DP_128B132B_FALSE 0x00000000 /* RW--V */ +#define NVCB73_SOR_CAP_DP_128B132B_TRUE 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA(i) (0x780+(i)*32) /* RW-4A */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA__SIZE_1 32 /* */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH 13:10 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT 16:16 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT 17:17 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT 18:18 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT 19:19 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT 20:20 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT 21:21 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT 22:22 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT 23:23 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT 24:24 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB(i) (0x784+(i)*32) /* RW-4A */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB__SIZE_1 32 /* */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION 4:0 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ 9:6 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR 12:10 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD 14:14 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT 15:15 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC(i) (0x788+(i)*32) /* RW-4A */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC__SIZE_1 32 /* */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION 4:0 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_FVLUT 13:13 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_FVLUT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_FVLUT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT 15:15 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION 20:16 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP 21:21 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD(i) (0x78c+(i)*32) /* RW-4A */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD__SIZE_1 32 /* */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ 3:0 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR 6:4 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD 8:8 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT 9:9 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION 16:12 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION 20:17 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB 21:21 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA 22:22 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_TRUE 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_FALSE 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE(i) (0x790+(i)*32) /* RW-4A */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE__SIZE_1 32 /* */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION 4:0 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_FVLUT 13:13 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_FVLUT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_FVLUT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT 15:15 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION 20:16 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP 21:21 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPF(i) (0x794+(i)*32) /* RW-4A */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPF__SIZE_1 32 /* */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */ +#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */ +#define NVCB73_SOR_CLK_CAP(i) (0x608+(i)*4) /* RW-4A */ +#define NVCB73_SOR_CLK_CAP__SIZE_1 8 /* */ +#define NVCB73_SOR_CLK_CAP_DP_MAX 7:0 /* RWIUF */ +#define NVCB73_SOR_CLK_CAP_TMDS_MAX 23:16 /* RWIUF */ +#define NVCB73_SOR_CLK_CAP_LVDS_MAX 31:24 /* RWIUF */ + +#ifdef __cplusplus +}; +#endif /* extern C */ +#endif //_clcb73_h_ diff --git a/userspace/sdks/nv570/inc/class/clcb7a.h b/userspace/sdks/nv570/inc/class/clcb7a.h new file mode 100644 index 0000000..49ff6af --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcb7a.h @@ -0,0 +1,216 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clcb7a__h_ +#define _clcb7a__h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVCB7A_CURSOR_IMM_CHANNEL_PIO (0x0000CB7A) + +typedef volatile struct _clcb7a_tag0 { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x7D]; + NvV32 Update; // 0x00000200 - 0x00000203 + NvV32 SetInterlockFlags; // 0x00000204 - 0x00000207 + NvV32 SetCursorHotSpotPointOut[2]; // 0x00000208 - 0x0000020F + NvV32 SetWindowInterlockFlags; // 0x00000210 - 0x00000213 + NvV32 Reserved02[0x3F7B]; +} NVCB7ADispCursorImmControlPio; + +#define NVCB7A_FREE (0x00000008) +#define NVCB7A_FREE_COUNT 5:0 +#define NVCB7A_UPDATE (0x00000200) +#define NVCB7A_UPDATE_RELEASE_ELV 0:0 +#define NVCB7A_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVCB7A_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVCB7A_UPDATE_FORCE_FULLSCREEN 12:12 +#define NVCB7A_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000) +#define NVCB7A_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001) +#define NVCB7A_SET_INTERLOCK_FLAGS (0x00000204) +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVCB7A_SET_CURSOR_HOT_SPOT_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVCB7A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0 +#define NVCB7A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS (0x00000210) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clcb7a_h + diff --git a/userspace/sdks/nv570/inc/class/clcb7b.h b/userspace/sdks/nv570/inc/class/clcb7b.h new file mode 100644 index 0000000..5e33f0a --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcb7b.h @@ -0,0 +1,70 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clcb7b_h_ +#define _clcb7b_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVCB7B_WINDOW_IMM_CHANNEL_DMA (0x0000CB7B) + +// dma opcode instructions +#define NVCB7B_DMA +#define NVCB7B_DMA_OPCODE 31:29 +#define NVCB7B_DMA_OPCODE_METHOD 0x00000000 +#define NVCB7B_DMA_OPCODE_JUMP 0x00000001 +#define NVCB7B_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVCB7B_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVCB7B_DMA_METHOD_COUNT 27:18 +#define NVCB7B_DMA_METHOD_OFFSET 15:2 +#define NVCB7B_DMA_DATA 31:0 +#define NVCB7B_DMA_DATA_NOP 0x00000000 +#define NVCB7B_DMA_JUMP_OFFSET 15:2 +#define NVCB7B_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVCB7B_PUT (0x00000000) +#define NVCB7B_PUT_PTR 13:0 +#define NVCB7B_GET (0x00000004) +#define NVCB7B_GET_PTR 13:0 +#define NVCB7B_UPDATE (0x00000200) +#define NVCB7B_UPDATE_RELEASE_ELV 0:0 +#define NVCB7B_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVCB7B_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVCB7B_UPDATE_INTERLOCK_WITH_WINDOW 1:1 +#define NVCB7B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVCB7B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVCB7B_UPDATE_FORCE_FULLSCREEN 4:4 +#define NVCB7B_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000) +#define NVCB7B_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001) +#define NVCB7B_SET_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVCB7B_SET_POINT_OUT_X 15:0 +#define NVCB7B_SET_POINT_OUT_Y 31:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clcb7b_h diff --git a/userspace/sdks/nv570/inc/class/clcb7d.h b/userspace/sdks/nv570/inc/class/clcb7d.h new file mode 100644 index 0000000..aea7dab --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcb7d.h @@ -0,0 +1,2007 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clcb7d_h_ +#define _clcb7d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVCB7D_CORE_CHANNEL_DMA (0x0000CB7D) + +#define NV_DISP_NOTIFIER 0x00000000 +#define NV_DISP_NOTIFIER_SIZEOF 0x00000010 +#define NV_DISP_NOTIFIER__0 0x00000000 +#define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFIER__0_FIELD 8:8 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE 9:9 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001 +#define NV_DISP_NOTIFIER__0_R1 15:10 +#define NV_DISP_NOTIFIER__0_R2 23:16 +#define NV_DISP_NOTIFIER__0_R3 29:24 +#define NV_DISP_NOTIFIER__0_STATUS 31:30 +#define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002 +#define NV_DISP_NOTIFIER__1 0x00000001 +#define NV_DISP_NOTIFIER__1_R4 31:0 +#define NV_DISP_NOTIFIER__2 0x00000002 +#define NV_DISP_NOTIFIER__2_TIMESTAMP_LO 31:0 +#define NV_DISP_NOTIFIER__3 0x00000003 +#define NV_DISP_NOTIFIER__3_TIMESTAMP_HI 31:0 + + +// dma opcode instructions +#define NVCB7D_DMA +#define NVCB7D_DMA_OPCODE 31:29 +#define NVCB7D_DMA_OPCODE_METHOD 0x00000000 +#define NVCB7D_DMA_OPCODE_JUMP 0x00000001 +#define NVCB7D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVCB7D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVCB7D_DMA_METHOD_COUNT 27:18 +#define NVCB7D_DMA_METHOD_OFFSET 15:2 +#define NVCB7D_DMA_DATA 31:0 +#define NVCB7D_DMA_DATA_NOP 0x00000000 +#define NVCB7D_DMA_JUMP_OFFSET 15:2 +#define NVCB7D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// if cap SUPPORT_FLEXIBLE_WIN_MAPPING is FALSE, this define can be used to obtain which head a window is mapped to +#define NVC37D_WINDOW_MAPPED_TO_HEAD(w) ((w)>>1) +#define NVC37D_GET_VALID_WINDOWMASK_FOR_HEAD(h) ((1<<((h)*2)) | (1<<((h)*2+1))) + +// class methods +#define NVCB7D_PUT (0x00000000) +#define NVCB7D_PUT_PTR 13:0 +#define NVCB7D_GET (0x00000004) +#define NVCB7D_GET_PTR 13:0 +#define NVCB7D_UPDATE (0x00000200) +#define NVCB7D_UPDATE_SPECIAL_HANDLING 21:20 +#define NVCB7D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NVCB7D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NVCB7D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NVCB7D_UPDATE_SPECIAL_HANDLING_REASON 19:12 +#define NVCB7D_UPDATE_INHIBIT_INTERRUPTS 24:24 +#define NVCB7D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NVCB7D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NVCB7D_UPDATE_RELEASE_ELV 0:0 +#define NVCB7D_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVCB7D_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVCB7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVCB7D_UPDATE_FORCE_FULLSCREEN 28:28 +#define NVCB7D_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000) +#define NVCB7D_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001) +#define NVCB7D_SET_NOTIFIER_CONTROL (0x0000020C) +#define NVCB7D_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVCB7D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVCB7D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVCB7D_SET_NOTIFIER_CONTROL_NOTIFY 12:12 +#define NVCB7D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NVCB7D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NVCB7D_SET_CONTROL (0x00000210) +#define NVCB7D_SET_CONTROL_FLIP_LOCK_PIN(i) ((i)+0):((i)+0) +#define NVCB7D_SET_CONTROL_FLIP_LOCK_PIN__SIZE_1 4 +#define NVCB7D_SET_CONTROL_FLIP_LOCK_PIN_DISABLE (0x00000000) +#define NVCB7D_SET_CONTROL_FLIP_LOCK_PIN_ENABLE (0x00000001) +#define NVCB7D_SET_CONTROL_FLIP_LOCK_PIN0 0:0 +#define NVCB7D_SET_CONTROL_FLIP_LOCK_PIN0_DISABLE (0x00000000) +#define NVCB7D_SET_CONTROL_FLIP_LOCK_PIN0_ENABLE (0x00000001) +#define NVCB7D_SET_CONTROL_FLIP_LOCK_PIN1 1:1 +#define NVCB7D_SET_CONTROL_FLIP_LOCK_PIN1_DISABLE (0x00000000) +#define NVCB7D_SET_CONTROL_FLIP_LOCK_PIN1_ENABLE (0x00000001) +#define NVCB7D_SET_CONTROL_FLIP_LOCK_PIN2 2:2 +#define NVCB7D_SET_CONTROL_FLIP_LOCK_PIN2_DISABLE (0x00000000) +#define NVCB7D_SET_CONTROL_FLIP_LOCK_PIN2_ENABLE (0x00000001) +#define NVCB7D_SET_CONTROL_FLIP_LOCK_PIN3 3:3 +#define NVCB7D_SET_CONTROL_FLIP_LOCK_PIN3_DISABLE (0x00000000) +#define NVCB7D_SET_CONTROL_FLIP_LOCK_PIN3_ENABLE (0x00000001) +#define NVCB7D_SET_INTERLOCK_FLAGS (0x00000218) +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+0):((i)+0) +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVCB7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS (0x0000021C) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVCB7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVCB7D_GET_RG_SCAN_LINE(b) (0x00000220 + (b)*0x00000004) +#define NVCB7D_GET_RG_SCAN_LINE_LINE 15:0 +#define NVCB7D_GET_RG_SCAN_LINE_VBLANK 16:16 +#define NVCB7D_GET_RG_SCAN_LINE_VBLANK_FALSE (0x00000000) +#define NVCB7D_GET_RG_SCAN_LINE_VBLANK_TRUE (0x00000001) +#define NVCB7D_SET_GET_BLANKING_CTRL(b) (0x00000240 + (b)*0x00000004) +#define NVCB7D_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NVCB7D_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NVCB7D_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NVCB7D_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NVCB7D_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NVCB7D_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) +#define NVCB7D_SET_SURFACE_ADDRESS_HI_NOTIFIER (0x00000260) +#define NVCB7D_SET_SURFACE_ADDRESS_HI_NOTIFIER_ADDRESS_HI 31:0 +#define NVCB7D_SET_SURFACE_ADDRESS_LO_NOTIFIER (0x00000264) +#define NVCB7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_ADDRESS_LO 31:4 +#define NVCB7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET 3:2 +#define NVCB7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_IOVA (0x00000000) +#define NVCB7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCB7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCB7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCB7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE 0:0 +#define NVCB7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_DISABLE (0x00000000) +#define NVCB7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_ENABLE (0x00000001) + +#define NVCB7D_SOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NVCB7D_SOR_SET_CONTROL_OWNER_MASK 7:0 +#define NVCB7D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVCB7D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVCB7D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVCB7D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVCB7D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVCB7D_SOR_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVCB7D_SOR_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVCB7D_SOR_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVCB7D_SOR_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVCB7D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NVCB7D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NVCB7D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NVCB7D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NVCB7D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NVCB7D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NVCB7D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NVCB7D_SOR_SET_CONTROL_PROTOCOL_HDMI_FRL (0x0000000C) +#define NVCB7D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NVCB7D_SOR_SET_CONTROL_DE_SYNC_POLARITY 16:16 +#define NVCB7D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVCB7D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVCB7D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NVCB7D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NVCB7D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NVCB7D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NVCB7D_SOR_SET_CUSTOM_REASON(a) (0x00000304 + (a)*0x00000020) +#define NVCB7D_SOR_SET_CUSTOM_REASON_CODE 31:0 +#define NVCB7D_SOR_SET_SW_SPARE_A(a) (0x00000308 + (a)*0x00000020) +#define NVCB7D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NVCB7D_SOR_SET_SW_SPARE_B(a) (0x0000030C + (a)*0x00000020) +#define NVCB7D_SOR_SET_SW_SPARE_B_CODE 31:0 + +#define NVCB7D_DSI_SET_CONTROL(a) (0x00000500 + (a)*0x00000020) +#define NVCB7D_DSI_SET_CONTROL_OWNER_MASK 7:0 +#define NVCB7D_DSI_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVCB7D_DSI_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVCB7D_DSI_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVCB7D_DSI_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVCB7D_DSI_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVCB7D_DSI_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVCB7D_DSI_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVCB7D_DSI_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVCB7D_DSI_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVCB7D_DSI_SET_CUSTOM_REASON(a) (0x00000504 + (a)*0x00000020) +#define NVCB7D_DSI_SET_CUSTOM_REASON_CODE 31:0 +#define NVCB7D_DSI_SET_SW_SPARE_A(a) (0x00000508 + (a)*0x00000020) +#define NVCB7D_DSI_SET_SW_SPARE_A_CODE 31:0 +#define NVCB7D_DSI_SET_SW_SPARE_B(a) (0x0000050C + (a)*0x00000020) +#define NVCB7D_DSI_SET_SW_SPARE_B_CODE 31:0 + +#define NVCB7D_WINDOW_SET_CONTROL(a) (0x00001000 + (a)*0x00000080) +#define NVCB7D_WINDOW_SET_CONTROL_OWNER 3:0 +#define NVCB7D_WINDOW_SET_CONTROL_OWNER_HEAD(i) (0x00000000 +(i)) +#define NVCB7D_WINDOW_SET_CONTROL_OWNER_HEAD__SIZE_1 8 +#define NVCB7D_WINDOW_SET_CONTROL_OWNER_HEAD0 (0x00000000) +#define NVCB7D_WINDOW_SET_CONTROL_OWNER_HEAD1 (0x00000001) +#define NVCB7D_WINDOW_SET_CONTROL_OWNER_HEAD2 (0x00000002) +#define NVCB7D_WINDOW_SET_CONTROL_OWNER_HEAD3 (0x00000003) +#define NVCB7D_WINDOW_SET_CONTROL_OWNER_HEAD4 (0x00000004) +#define NVCB7D_WINDOW_SET_CONTROL_OWNER_HEAD5 (0x00000005) +#define NVCB7D_WINDOW_SET_CONTROL_OWNER_HEAD6 (0x00000006) +#define NVCB7D_WINDOW_SET_CONTROL_OWNER_HEAD7 (0x00000007) +#define NVCB7D_WINDOW_SET_CONTROL_OWNER_NONE (0x0000000F) +#define NVCB7D_WINDOW_SET_CONTROL_HIDE 8:8 +#define NVCB7D_WINDOW_SET_CONTROL_HIDE_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_CONTROL_HIDE_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_CONTROL_DISABLE_PHYSICAL_FLIPS 9:9 +#define NVCB7D_WINDOW_SET_CONTROL_DISABLE_PHYSICAL_FLIPS_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_CONTROL_DISABLE_PHYSICAL_FLIPS_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_CONTROL_ALLOW_SUPERFRAME 10:10 +#define NVCB7D_WINDOW_SET_CONTROL_ALLOW_SUPERFRAME_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_CONTROL_ALLOW_SUPERFRAME_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0x00000080) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a) (0x00001008 + (a)*0x00000080) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR(a) (0x0000100C + (a)*0x00000080) +#define NVCB7D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVCB7D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVCB7D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a) (0x00001010 + (a)*0x00000080) +#define NVCB7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_MAX_PIXELS_FETCHED_PER_LINE 14:0 +#define NVCB7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED 16:16 +#define NVCB7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED 28:28 +#define NVCB7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS 22:20 +#define NVCB7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVCB7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED 24:24 +#define NVCB7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED 30:30 +#define NVCB7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_LAYOUT 26:25 +#define NVCB7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_LAYOUT_PITCH_BLOCKLINEAR (0x00000000) +#define NVCB7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_LAYOUT_PITCH (0x00000001) +#define NVCB7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_LAYOUT_BLOCKLINEAR (0x00000002) +#define NVCB7D_WINDOW_SET_PHYSICAL(a) (0x00001014 + (a)*0x00000080) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW 31:0 +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_NONE (0x00000000) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW0 (0x00000001) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW1 (0x00000002) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW2 (0x00000004) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW3 (0x00000008) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW4 (0x00000010) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW5 (0x00000020) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW6 (0x00000040) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW7 (0x00000080) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW8 (0x00000100) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW9 (0x00000200) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW10 (0x00000400) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW11 (0x00000800) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW12 (0x00001000) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW13 (0x00002000) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW14 (0x00004000) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW15 (0x00008000) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW16 (0x00010000) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW17 (0x00020000) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW18 (0x00040000) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW19 (0x00080000) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW20 (0x00100000) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW21 (0x00200000) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW22 (0x00400000) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW23 (0x00800000) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW24 (0x01000000) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW25 (0x02000000) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW26 (0x04000000) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW27 (0x08000000) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW28 (0x10000000) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW29 (0x20000000) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW30 (0x40000000) +#define NVCB7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW31 (0x80000000) +#define NVCB7D_WINDOW_SET_GUEST_OVERRIDES(a) (0x00001024 + (a)*0x00000080) +#define NVCB7D_WINDOW_SET_GUEST_OVERRIDES_SET_SIZE_OUT 0:0 +#define NVCB7D_WINDOW_SET_GUEST_OVERRIDES_SET_SIZE_OUT_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_GUEST_OVERRIDES_SET_SIZE_OUT_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_CONTROL 1:1 +#define NVCB7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_CONTROL_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_CONTROL_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_CONSTANT_ALPHA 2:2 +#define NVCB7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_CONSTANT_ALPHA_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_CONSTANT_ALPHA_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_FACTOR_SELECT 3:3 +#define NVCB7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_FACTOR_SELECT_FALSE (0x00000000) +#define NVCB7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_FACTOR_SELECT_TRUE (0x00000001) +#define NVCB7D_WINDOW_SET_GUEST_SIZE_OUT(a) (0x00001028 + (a)*0x00000080) +#define NVCB7D_WINDOW_SET_GUEST_SIZE_OUT_WIDTH 15:0 +#define NVCB7D_WINDOW_SET_GUEST_SIZE_OUT_HEIGHT 31:16 +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL(a) (0x0000102C + (a)*0x00000080) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0 +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL_DEPTH 11:4 +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL_BYPASS 16:16 +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL_BYPASS_DISABLE (0x00000000) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL_BYPASS_ENABLE (0x00000001) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_CONSTANT_ALPHA(a) (0x00001030 + (a)*0x00000080) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_CONSTANT_ALPHA_K1 7:0 +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_CONSTANT_ALPHA_K2 15:8 +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT(a) (0x00001034 + (a)*0x00000080) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0 +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4 +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8 +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12 +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16 +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20 +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24 +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28 +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVCB7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) + +#define NVCB7D_HEAD_SET_PROCAMP(a) (0x00002000 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NVCB7D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NVCB7D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NVCB7D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NVCB7D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003) +#define NVCB7D_HEAD_SET_PROCAMP_CHROMA_LPF 3:3 +#define NVCB7D_HEAD_SET_PROCAMP_CHROMA_LPF_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_PROCAMP_CHROMA_LPF_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_PROCAMP_CHROMA_DOWN_V 4:4 +#define NVCB7D_HEAD_SET_PROCAMP_CHROMA_DOWN_V_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_PROCAMP_CHROMA_DOWN_V_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 28:28 +#define NVCB7D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NVCB7D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00002004 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 2:2 +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 3:3 +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 7:4 +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000000) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000001) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000002) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000003) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000004) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000005) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000006) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000007) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000008) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_444 (0x00000009) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444NP (0x0000000A) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 24:24 +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 23:12 +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN 31:26 +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN0 (0x00000000) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN1 (0x00000001) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN2 (0x00000002) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN3 (0x00000003) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN4 (0x00000004) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN5 (0x00000005) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN6 (0x00000006) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN7 (0x00000007) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN8 (0x00000008) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN9 (0x00000009) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN10 (0x0000000A) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN11 (0x0000000B) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN12 (0x0000000C) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN13 (0x0000000D) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN14 (0x0000000E) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN15 (0x0000000F) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN16 (0x00000010) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN17 (0x00000011) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN18 (0x00000012) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN19 (0x00000013) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN20 (0x00000014) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN21 (0x00000015) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN22 (0x00000016) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN23 (0x00000017) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN24 (0x00000018) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN25 (0x00000019) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN26 (0x0000001A) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN27 (0x0000001B) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN28 (0x0000001C) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN29 (0x0000001D) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN30 (0x0000001E) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN31 (0x0000001F) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_NONE (0x0000003F) +#define NVCB7D_HEAD_SET_CONTROL(a) (0x00002008 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_CONTROL_STRUCTURE 1:0 +#define NVCB7D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NVCB7D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE 2:2 +#define NVCB7D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_NORMAL (0x00000000) +#define NVCB7D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000001) +#define NVCB7D_HEAD_SET_CONTROL_YUV420PACKER 3:3 +#define NVCB7D_HEAD_SET_CONTROL_YUV420PACKER_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_CONTROL_YUV420PACKER_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_MODE 11:10 +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_MODE_NO_LOCK (0x00000000) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN 8:4 +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVCB7D_HEAD_SET_CONTROL_SINK_LOCKOUT_WINDOW 15:12 +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_MODE 23:22 +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_MODE_NO_LOCK (0x00000000) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN 20:16 +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN 28:24 +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_NONE (0x00000000) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000001) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000002) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000003) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000004) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000005) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000006) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000007) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000008) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000009) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x0000000A) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000B) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000C) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000D) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000E) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000F) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x00000010) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVCB7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVCB7D_HEAD_SET_CONTROL_SINK_STEREO_LOCK_MODE 30:30 +#define NVCB7D_HEAD_SET_CONTROL_SINK_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_CONTROL_SINK_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_STEREO_LOCK_MODE 31:31 +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_CONTROL_SOURCE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x0000200C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NVCB7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NVCB7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NVCB7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00002014 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVCB7D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVCB7D_HEAD_SET_DITHER_CONTROL(a) (0x00002018 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NVCB7D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_DITHER_CONTROL_BITS 5:4 +#define NVCB7D_HEAD_SET_DITHER_CONTROL_BITS_TO_6_BITS (0x00000000) +#define NVCB7D_HEAD_SET_DITHER_CONTROL_BITS_TO_8_BITS (0x00000001) +#define NVCB7D_HEAD_SET_DITHER_CONTROL_BITS_TO_10_BITS (0x00000002) +#define NVCB7D_HEAD_SET_DITHER_CONTROL_BITS_TO_12_BITS (0x00000003) +#define NVCB7D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE 2:2 +#define NVCB7D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_DITHER_CONTROL_MODE 10:8 +#define NVCB7D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NVCB7D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NVCB7D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NVCB7D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NVCB7D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NVCB7D_HEAD_SET_DITHER_CONTROL_MODE_ROUND (0x00000005) +#define NVCB7D_HEAD_SET_DITHER_CONTROL_PHASE 13:12 +#define NVCB7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x0000201C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 0:0 +#define NVCB7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NVCB7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NVCB7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING 4:4 +#define NVCB7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 9:8 +#define NVCB7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NVCB7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NVCB7D_HEAD_SET_DISPLAY_ID(a,b) (0x00002020 + (a)*0x00000800 + (b)*0x00000004) +#define NVCB7D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NVCB7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00002028 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NVCB7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NVCB7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NVCB7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NVCB7D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR(a) (0x0000202C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVCB7D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVCB7D_HEAD_SET_HEAD_USAGE_BOUNDS(a) (0x00002030 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR 2:0 +#define NVCB7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_NONE (0x00000000) +#define NVCB7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W32_H32 (0x00000001) +#define NVCB7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W64_H64 (0x00000002) +#define NVCB7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W128_H128 (0x00000003) +#define NVCB7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W256_H256 (0x00000004) +#define NVCB7D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED 4:4 +#define NVCB7D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_FALSE (0x00000000) +#define NVCB7D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_TRUE (0x00000001) +#define NVCB7D_HEAD_SET_HEAD_USAGE_BOUNDS_LTM_ALLOWED 5:5 +#define NVCB7D_HEAD_SET_HEAD_USAGE_BOUNDS_LTM_ALLOWED_FALSE (0x00000000) +#define NVCB7D_HEAD_SET_HEAD_USAGE_BOUNDS_LTM_ALLOWED_TRUE (0x00000001) +#define NVCB7D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS 14:12 +#define NVCB7D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVCB7D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVCB7D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED 8:8 +#define NVCB7D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVCB7D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVCB7D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED 16:16 +#define NVCB7D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED_FALSE (0x00000000) +#define NVCB7D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED_TRUE (0x00000001) +#define NVCB7D_HEAD_SET_HEAD_USAGE_BOUNDS_ELV_START 31:17 +#define NVCB7D_HEAD_SET_STALL_LOCK(a) (0x00002034 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_STALL_LOCK_ENABLE 0:0 +#define NVCB7D_HEAD_SET_STALL_LOCK_ENABLE_FALSE (0x00000000) +#define NVCB7D_HEAD_SET_STALL_LOCK_ENABLE_TRUE (0x00000001) +#define NVCB7D_HEAD_SET_STALL_LOCK_MODE 2:2 +#define NVCB7D_HEAD_SET_STALL_LOCK_MODE_CONTINUOUS (0x00000000) +#define NVCB7D_HEAD_SET_STALL_LOCK_MODE_ONE_SHOT (0x00000001) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN 8:4 +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVCB7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVCB7D_HEAD_SET_STALL_LOCK_UNSTALL_MODE 12:12 +#define NVCB7D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_CRASH_LOCK (0x00000000) +#define NVCB7D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_LINE_LOCK (0x00000001) +#define NVCB7D_HEAD_SET_STALL_LOCK_TEPOLARITY 14:14 +#define NVCB7D_HEAD_SET_STALL_LOCK_TEPOLARITY_POSITIVE_TRUE (0x00000000) +#define NVCB7D_HEAD_SET_STALL_LOCK_TEPOLARITY_NEGATIVE_TRUE (0x00000001) +#define NVCB7D_HEAD_SET_STALL_LOCK_UNSTALL_SYNC_ADVANCE 25:16 +#define NVCB7D_HEAD_SET_LOCK_CHAIN(a) (0x00002044 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_LOCK_CHAIN_POSITION 3:0 +#define NVCB7D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x00002048 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NVCB7D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NVCB7D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x0000204C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NVCB7D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NVCB7D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x00002058 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NVCB7D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NVCB7D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x0000205C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NVCB7D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NVCB7D_HEAD_SET_TILE_MASK(a) (0x00002060 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_TILE_MASK_TILE 7:0 +#define NVCB7D_HEAD_SET_TILE_MASK_TILE_NONE (0x00000000) +#define NVCB7D_HEAD_SET_TILE_MASK_TILE_TILE0 (0x00000001) +#define NVCB7D_HEAD_SET_TILE_MASK_TILE_TILE1 (0x00000002) +#define NVCB7D_HEAD_SET_TILE_MASK_TILE_TILE2 (0x00000004) +#define NVCB7D_HEAD_SET_TILE_MASK_TILE_TILE3 (0x00000008) +#define NVCB7D_HEAD_SET_TILE_MASK_TILE_TILE4 (0x00000010) +#define NVCB7D_HEAD_SET_TILE_MASK_TILE_TILE5 (0x00000020) +#define NVCB7D_HEAD_SET_TILE_MASK_TILE_TILE6 (0x00000040) +#define NVCB7D_HEAD_SET_TILE_MASK_TILE_TILE7 (0x00000080) +#define NVCB7D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_RASTER_SIZE_WIDTH 15:0 +#define NVCB7D_HEAD_SET_RASTER_SIZE_HEIGHT 31:16 +#define NVCB7D_HEAD_SET_RASTER_SYNC_END(a) (0x00002068 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NVCB7D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NVCB7D_HEAD_SET_RASTER_BLANK_END(a) (0x0000206C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NVCB7D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NVCB7D_HEAD_SET_RASTER_BLANK_START(a) (0x00002070 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NVCB7D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NVCB7D_HEAD_SET_OVERSCAN_COLOR(a) (0x00002078 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OVERSCAN_COLOR_RED_CR 9:0 +#define NVCB7D_HEAD_SET_OVERSCAN_COLOR_GREEN_Y 19:10 +#define NVCB7D_HEAD_SET_OVERSCAN_COLOR_BLUE_CB 29:20 +#define NVCB7D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR(a) (0x0000207C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_RED_CR 9:0 +#define NVCB7D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_GREEN_Y 19:10 +#define NVCB7D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_BLUE_CB 29:20 +#define NVCB7D_HEAD_SET_HDMI_CTRL(a) (0x00002080 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NVCB7D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NVCB7D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NVCB7D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NVCB7D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NVCB7D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x00002098 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 0:0 +#define NVCB7D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NVCB7D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NVCB7D_HEAD_SET_CONTROL_CURSOR(a) (0x0000209C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_FORMAT 7:0 +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x000000E9) +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x000000CF) +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_SIZE 9:8 +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 19:12 +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 27:20 +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION(a) (0x000020A0 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_K1 7:0 +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT 11:8 +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1_TIMES_SRC (0x00000005) +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT 15:12 +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_ZERO (0x00000000) +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE 16:16 +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_BLEND (0x00000000) +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_XOR (0x00000001) +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS 20:20 +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_CMI_LUT_CONTROL(a) (0x000020A4 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_CMI_LUT_CONTROL_ENABLE 0:0 +#define NVCB7D_HEAD_SET_CMI_LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_CMI_LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_CMI_LUT_CONTROL_INTERPOLATE 1:1 +#define NVCB7D_HEAD_SET_CMI_LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_CMI_LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_CMI_LUT_CONTROL_MIRROR 2:2 +#define NVCB7D_HEAD_SET_CMI_LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_CMI_LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_CMI_FP_NORM_SCALE(a) (0x000020A8 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_CMI_FP_NORM_SCALE_FPNORM 31:0 +#define NVCB7D_HEAD_SET_CMO_LUT_CONTROL(a) (0x000020AC + (a)*0x00000800) +#define NVCB7D_HEAD_SET_CMO_LUT_CONTROL_ENABLE 0:0 +#define NVCB7D_HEAD_SET_CMO_LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_CMO_LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_CMO_LUT_CONTROL_INTERPOLATE 1:1 +#define NVCB7D_HEAD_SET_CMO_LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_CMO_LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_CMO_LUT_CONTROL_MIRROR 2:2 +#define NVCB7D_HEAD_SET_CMO_LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_CMO_LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_CM3D0CONTROL(a) (0x000020B8 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_CM3D0CONTROL_MODE 0:0 +#define NVCB7D_HEAD_SET_CM3D0CONTROL_MODE_GAMUT_MAPPING (0x00000000) +#define NVCB7D_HEAD_SET_CM3D0CONTROL_MODE_PANEL_CORR (0x00000001) +#define NVCB7D_HEAD_SET_CM3D0CONTROL_ROUND 1:1 +#define NVCB7D_HEAD_SET_CM3D0CONTROL_ROUND_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_CM3D0CONTROL_ROUND_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_CM3D0CONTROL_LAST_ENTRY_ADD1 2:2 +#define NVCB7D_HEAD_SET_CM3D0CONTROL_LAST_ENTRY_ADD1_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_CM3D0CONTROL_LAST_ENTRY_ADD1_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_CM3D0CONTROL_SIZE 3:3 +#define NVCB7D_HEAD_SET_CM3D0CONTROL_SIZE_SIZE_9X9X9 (0x00000000) +#define NVCB7D_HEAD_SET_CM3D0CONTROL_SIZE_SIZE_17X17X17 (0x00000001) +#define NVCB7D_HEAD_SET_CM3D0CONTROL_RANGE_SCALE 8:6 +#define NVCB7D_HEAD_SET_CM3D0CONTROL_CONTENT_OFFSET 22:9 +#define NVCB7D_HEAD_SET_CM3D1CONTROL(a) (0x000020BC + (a)*0x00000800) +#define NVCB7D_HEAD_SET_CM3D1CONTROL_MODE 0:0 +#define NVCB7D_HEAD_SET_CM3D1CONTROL_MODE_GAMUT_MAPPING (0x00000000) +#define NVCB7D_HEAD_SET_CM3D1CONTROL_MODE_PANEL_CORR (0x00000001) +#define NVCB7D_HEAD_SET_CM3D1CONTROL_ROUND 1:1 +#define NVCB7D_HEAD_SET_CM3D1CONTROL_ROUND_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_CM3D1CONTROL_ROUND_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_CM3D1CONTROL_LAST_ENTRY_ADD1 2:2 +#define NVCB7D_HEAD_SET_CM3D1CONTROL_LAST_ENTRY_ADD1_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_CM3D1CONTROL_LAST_ENTRY_ADD1_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_CM3D1CONTROL_SIZE 3:3 +#define NVCB7D_HEAD_SET_CM3D1CONTROL_SIZE_SIZE_9X9X9 (0x00000000) +#define NVCB7D_HEAD_SET_CM3D1CONTROL_SIZE_SIZE_17X17X17 (0x00000001) +#define NVCB7D_HEAD_SET_CM3D1CONTROL_RANGE_SCALE 8:6 +#define NVCB7D_HEAD_SET_CM3D1CONTROL_CONTENT_OFFSET 22:9 +#define NVCB7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI(a) (0x000020C0 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_HERTZ 3:0 +#define NVCB7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_MAX(a) (0x000020C4 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_MAX_HERTZ 3:0 +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE(a,b) (0x000020C8 + (a)*0x00000800 + (b)*0x00000004) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW 15:10 +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN0 (0x00000000) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN1 (0x00000001) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN2 (0x00000002) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN3 (0x00000003) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN4 (0x00000004) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN5 (0x00000005) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN6 (0x00000006) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN7 (0x00000007) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN8 (0x00000008) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN9 (0x00000009) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN10 (0x0000000A) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN11 (0x0000000B) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN12 (0x0000000C) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN13 (0x0000000D) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN14 (0x0000000E) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN15 (0x0000000F) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN16 (0x00000010) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN17 (0x00000011) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN18 (0x00000012) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN19 (0x00000013) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN20 (0x00000014) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN21 (0x00000015) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN22 (0x00000016) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN23 (0x00000017) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN24 (0x00000018) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN25 (0x00000019) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN26 (0x0000001A) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN27 (0x0000001B) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN28 (0x0000001C) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN29 (0x0000001D) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN30 (0x0000001E) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN31 (0x0000001F) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_NONE (0x0000003F) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_INDEX 1:1 +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_ENABLE 0:0 +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_ENABLE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_ENABLE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_LOCATION_OVERRIDE 2:2 +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_LOCATION_OVERRIDE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_LOCATION_OVERRIDE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_LOCATION 9:8 +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_LOCATION_VBLANK (0x00000000) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_LOCATION_VSYNC (0x00000001) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_LOCATION_LINE (0x00000002) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_LINE_ID 30:16 +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_LINE_ID_REVERSED 31:31 +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_LINE_ID_REVERSED_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_LINE_ID_REVERSED_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_HB0OVERRIDE 4:4 +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_HB0OVERRIDE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_HB0OVERRIDE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_HB1OVERRIDE 5:5 +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_HB1OVERRIDE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_HB1OVERRIDE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_HB2OVERRIDE 6:6 +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_HB2OVERRIDE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_HB2OVERRIDE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_HB3OVERRIDE 7:7 +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_HB3OVERRIDE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_INFOFRAME_OVERRIDE_HB3OVERRIDE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_INFOFRAME_HEADER_OVERRIDE(a,b) (0x000020D0 + (a)*0x00000800 + (b)*0x00000004) +#define NVCB7D_HEAD_SET_INFOFRAME_HEADER_OVERRIDE_HB0 7:0 +#define NVCB7D_HEAD_SET_INFOFRAME_HEADER_OVERRIDE_HB1 15:8 +#define NVCB7D_HEAD_SET_INFOFRAME_HEADER_OVERRIDE_HB2 23:16 +#define NVCB7D_HEAD_SET_INFOFRAME_HEADER_OVERRIDE_HB3 31:24 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_HI_RG_REL_SEMAPHORE(a,b) (0x00002110 + (a)*0x00000800 + (b)*0x00000004) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_HI_RG_REL_SEMAPHORE_ADDRESS_HI 31:0 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE(a,b) (0x00002130 + (a)*0x00000800 + (b)*0x00000004) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_ADDRESS_LO 31:4 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_TARGET 3:2 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_TARGET_IOVA (0x00000000) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_ENABLE 0:0 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_ENABLE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_ENABLE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_HI_CRC(a) (0x00002150 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_HI_CRC_ADDRESS_HI 31:0 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC(a) (0x00002154 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_ADDRESS_LO 31:4 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET 3:2 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET_IOVA (0x00000000) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_ENABLE 0:0 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_ENABLE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_ENABLE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_HI_OLUT(a) (0x00002158 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_HI_OLUT_ADDRESS_HI 31:0 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT(a) (0x0000215C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_ADDRESS_LO 31:4 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET 3:2 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET_IOVA (0x00000000) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_ENABLE 0:0 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_ENABLE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_ENABLE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_HI_CM3D0(a) (0x00002160 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_HI_CM3D0_ADDRESS_HI 31:0 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0(a) (0x00002164 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_ADDRESS_LO 31:4 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_TARGET 3:2 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_TARGET_IOVA (0x00000000) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_ENABLE 0:0 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_ENABLE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_ENABLE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_HI_CM3D1(a) (0x00002168 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_HI_CM3D1_ADDRESS_HI 31:0 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1(a) (0x0000216C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_ADDRESS_LO 31:4 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_TARGET 3:2 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_TARGET_IOVA (0x00000000) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_ENABLE 0:0 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_ENABLE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_ENABLE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_HI_CURSOR(a,b) (0x00002170 + (a)*0x00000800 + (b)*0x00000004) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_HI_CURSOR_ADDRESS_HI 31:0 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR(a,b) (0x00002178 + (a)*0x00000800 + (b)*0x00000004) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_ADDRESS_LO 31:4 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET 3:2 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET_IOVA (0x00000000) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_KIND 1:1 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_KIND_PITCH (0x00000000) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_KIND_BLOCKLINEAR (0x00000001) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_ENABLE 0:0 +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_ENABLE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_ENABLE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_CRC_CONTROL(a) (0x00002184 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 5:0 +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_0 (0x00000000) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_1 (0x00000001) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_2 (0x00000002) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_3 (0x00000003) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_4 (0x00000004) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_5 (0x00000005) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_6 (0x00000006) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_7 (0x00000007) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_8 (0x00000008) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_9 (0x00000009) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_10 (0x0000000A) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_11 (0x0000000B) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_12 (0x0000000C) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_13 (0x0000000D) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_14 (0x0000000E) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_15 (0x0000000F) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_16 (0x00000010) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_17 (0x00000011) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_18 (0x00000012) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_19 (0x00000013) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_20 (0x00000014) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_21 (0x00000015) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_22 (0x00000016) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_23 (0x00000017) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_24 (0x00000018) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_25 (0x00000019) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_26 (0x0000001A) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_27 (0x0000001B) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_28 (0x0000001C) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_29 (0x0000001D) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_30 (0x0000001E) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_31 (0x0000001F) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000020) +#define NVCB7D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 8:8 +#define NVCB7D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NVCB7D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NVCB7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC 19:12 +#define NVCB7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_NONE (0x00000000) +#define NVCB7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SF (0x00000030) +#define NVCB7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVCB7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR__SIZE_1 8 +#define NVCB7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR0 (0x00000050) +#define NVCB7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR1 (0x00000051) +#define NVCB7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR2 (0x00000052) +#define NVCB7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR3 (0x00000053) +#define NVCB7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR4 (0x00000054) +#define NVCB7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR5 (0x00000055) +#define NVCB7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR6 (0x00000056) +#define NVCB7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR7 (0x00000057) +#define NVCB7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC 27:20 +#define NVCB7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_NONE (0x00000000) +#define NVCB7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SF (0x00000030) +#define NVCB7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVCB7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR__SIZE_1 8 +#define NVCB7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR0 (0x00000050) +#define NVCB7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR1 (0x00000051) +#define NVCB7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR2 (0x00000052) +#define NVCB7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR3 (0x00000053) +#define NVCB7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR4 (0x00000054) +#define NVCB7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR5 (0x00000055) +#define NVCB7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR6 (0x00000056) +#define NVCB7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR7 (0x00000057) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 9:9 +#define NVCB7D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_PRESENT_CONTROL(a) (0x0000218C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 0:0 +#define NVCB7D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NVCB7D_HEAD_SET_SW_SPARE_A(a) (0x00002194 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NVCB7D_HEAD_SET_SW_SPARE_B(a) (0x00002198 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NVCB7D_HEAD_SET_SW_SPARE_C(a) (0x0000219C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NVCB7D_HEAD_SET_SW_SPARE_D(a) (0x000021A0 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NVCB7D_HEAD_SET_DISPLAY_RATE(a) (0x000021A8 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DISPLAY_RATE_RUN_MODE 1:0 +#define NVCB7D_HEAD_SET_DISPLAY_RATE_RUN_MODE_CONTINUOUS (0x00000000) +#define NVCB7D_HEAD_SET_DISPLAY_RATE_RUN_MODE_ONE_SHOT (0x00000001) +#define NVCB7D_HEAD_SET_DISPLAY_RATE_RUN_MODE_ONE_SHOT_SELF_REFRESH (0x00000002) +#define NVCB7D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_INTERVAL 25:4 +#define NVCB7D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH 2:2 +#define NVCB7D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL(a,b) (0x000021CC + (a)*0x00000800 + (b)*0x00000004) +#define NVCB7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVCB7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVCB7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVCB7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE 14:14 +#define NVCB7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE_WRITE (0x00000000) +#define NVCB7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE_WRITE_AWAKEN (0x00000001) +#define NVCB7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE 10:10 +#define NVCB7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE_ONE_TIME (0x00000000) +#define NVCB7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE_CONTINUOUS (0x00000001) +#define NVCB7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RASTER_LINE 31:16 +#define NVCB7D_HEAD_SET_RG_REL_SEMAPHORE_VALUE(a,b) (0x000021EC + (a)*0x00000800 + (b)*0x00000004) +#define NVCB7D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_VALUE 31:0 +#define NVCB7D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE(a) (0x00002214 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVCB7D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVCB7D_HEAD_SET_MIN_FRAME_IDLE(a) (0x00002218 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_MIN_FRAME_IDLE_LEADING_RASTER_LINES 14:0 +#define NVCB7D_HEAD_SET_MIN_FRAME_IDLE_TRAILING_RASTER_LINES 30:16 +#define NVCB7D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED(a) (0x00002220 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED_ALPHA 7:0 +#define NVCB7D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED_RED 31:16 +#define NVCB7D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE(a) (0x00002224 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE_GREEN 15:0 +#define NVCB7D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE_BLUE 31:16 +#define NVCB7D_HEAD_SET_CURSOR_COLOR_NORM_SCALE(a) (0x00002228 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_CURSOR_COLOR_NORM_SCALE_VALUE 15:0 +#define NVCB7D_HEAD_SET_XOR_BLEND_FACTOR(a) (0x0000222C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_XOR_BLEND_FACTOR_LOG2PEAK_LUMINANCE 3:0 +#define NVCB7D_HEAD_SET_XOR_BLEND_FACTOR_S1 16:4 +#define NVCB7D_HEAD_SET_XOR_BLEND_FACTOR_S2 30:18 +#define NVCB7D_HEAD_SET_CLAMP_RANGE_GREEN(a) (0x00002238 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_CLAMP_RANGE_GREEN_LOW 11:0 +#define NVCB7D_HEAD_SET_CLAMP_RANGE_GREEN_HIGH 27:16 +#define NVCB7D_HEAD_SET_CLAMP_RANGE_RED_BLUE(a) (0x0000223C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_CLAMP_RANGE_RED_BLUE_LOW 11:0 +#define NVCB7D_HEAD_SET_CLAMP_RANGE_RED_BLUE_HIGH 27:16 +#define NVCB7D_HEAD_SET_OCSC0CONTROL(a) (0x00002240 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC0CONTROL_ENABLE 0:0 +#define NVCB7D_HEAD_SET_OCSC0CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_OCSC0CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_OCSC0COEFFICIENT_C00(a) (0x00002244 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC0COEFFICIENT_C00_VALUE 20:0 +#define NVCB7D_HEAD_SET_OCSC0COEFFICIENT_C01(a) (0x00002248 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC0COEFFICIENT_C01_VALUE 20:0 +#define NVCB7D_HEAD_SET_OCSC0COEFFICIENT_C02(a) (0x0000224C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC0COEFFICIENT_C02_VALUE 20:0 +#define NVCB7D_HEAD_SET_OCSC0COEFFICIENT_C03(a) (0x00002250 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC0COEFFICIENT_C03_VALUE 20:0 +#define NVCB7D_HEAD_SET_OCSC0COEFFICIENT_C10(a) (0x00002254 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC0COEFFICIENT_C10_VALUE 20:0 +#define NVCB7D_HEAD_SET_OCSC0COEFFICIENT_C11(a) (0x00002258 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC0COEFFICIENT_C11_VALUE 20:0 +#define NVCB7D_HEAD_SET_OCSC0COEFFICIENT_C12(a) (0x0000225C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC0COEFFICIENT_C12_VALUE 20:0 +#define NVCB7D_HEAD_SET_OCSC0COEFFICIENT_C13(a) (0x00002260 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC0COEFFICIENT_C13_VALUE 20:0 +#define NVCB7D_HEAD_SET_OCSC0COEFFICIENT_C20(a) (0x00002264 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC0COEFFICIENT_C20_VALUE 20:0 +#define NVCB7D_HEAD_SET_OCSC0COEFFICIENT_C21(a) (0x00002268 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC0COEFFICIENT_C21_VALUE 20:0 +#define NVCB7D_HEAD_SET_OCSC0COEFFICIENT_C22(a) (0x0000226C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC0COEFFICIENT_C22_VALUE 20:0 +#define NVCB7D_HEAD_SET_OCSC0COEFFICIENT_C23(a) (0x00002270 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC0COEFFICIENT_C23_VALUE 20:0 +#define NVCB7D_HEAD_SET_OLUT_CONTROL(a) (0x00002280 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OLUT_CONTROL_INTERPOLATE 0:0 +#define NVCB7D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_OLUT_CONTROL_MIRROR 1:1 +#define NVCB7D_HEAD_SET_OLUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_OLUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_OLUT_CONTROL_MODE 3:2 +#define NVCB7D_HEAD_SET_OLUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVCB7D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVCB7D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVCB7D_HEAD_SET_OLUT_CONTROL_SIZE 18:8 +#define NVCB7D_HEAD_SET_OLUT_CONTROL_DIRECT_ROUND 4:4 +#define NVCB7D_HEAD_SET_OLUT_CONTROL_DIRECT_ROUND_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_OLUT_CONTROL_DIRECT_ROUND_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_OLUT_CONTROL_LEVEL 25:20 +#define NVCB7D_HEAD_SET_OLUT_CONTROL_SEGMENT_SIZE_BITS 5:5 +#define NVCB7D_HEAD_SET_OLUT_CONTROL_SEGMENT_SIZE_BITS_SIZE_3BITS (0x00000000) +#define NVCB7D_HEAD_SET_OLUT_CONTROL_SEGMENT_SIZE_BITS_SIZE_4BITS (0x00000001) +#define NVCB7D_HEAD_SET_OLUT_FP_NORM_SCALE(a) (0x00002284 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OLUT_FP_NORM_SCALE_VALUE 31:0 +#define NVCB7D_HEAD_SET_OCSC1CONTROL(a) (0x0000229C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC1CONTROL_ENABLE 0:0 +#define NVCB7D_HEAD_SET_OCSC1CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_OCSC1CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_OCSC1COEFFICIENT_C00(a) (0x000022A0 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC1COEFFICIENT_C00_VALUE 20:0 +#define NVCB7D_HEAD_SET_OCSC1COEFFICIENT_C01(a) (0x000022A4 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC1COEFFICIENT_C01_VALUE 20:0 +#define NVCB7D_HEAD_SET_OCSC1COEFFICIENT_C02(a) (0x000022A8 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC1COEFFICIENT_C02_VALUE 20:0 +#define NVCB7D_HEAD_SET_OCSC1COEFFICIENT_C03(a) (0x000022AC + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC1COEFFICIENT_C03_VALUE 20:0 +#define NVCB7D_HEAD_SET_OCSC1COEFFICIENT_C10(a) (0x000022B0 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC1COEFFICIENT_C10_VALUE 20:0 +#define NVCB7D_HEAD_SET_OCSC1COEFFICIENT_C11(a) (0x000022B4 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC1COEFFICIENT_C11_VALUE 20:0 +#define NVCB7D_HEAD_SET_OCSC1COEFFICIENT_C12(a) (0x000022B8 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC1COEFFICIENT_C12_VALUE 20:0 +#define NVCB7D_HEAD_SET_OCSC1COEFFICIENT_C13(a) (0x000022BC + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC1COEFFICIENT_C13_VALUE 20:0 +#define NVCB7D_HEAD_SET_OCSC1COEFFICIENT_C20(a) (0x000022C0 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC1COEFFICIENT_C20_VALUE 20:0 +#define NVCB7D_HEAD_SET_OCSC1COEFFICIENT_C21(a) (0x000022C4 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC1COEFFICIENT_C21_VALUE 20:0 +#define NVCB7D_HEAD_SET_OCSC1COEFFICIENT_C22(a) (0x000022C8 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC1COEFFICIENT_C22_VALUE 20:0 +#define NVCB7D_HEAD_SET_OCSC1COEFFICIENT_C23(a) (0x000022CC + (a)*0x00000800) +#define NVCB7D_HEAD_SET_OCSC1COEFFICIENT_C23_VALUE 20:0 +#define NVCB7D_HEAD_SET_HEAD_POSITION(a) (0x000022D0 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_HEAD_POSITION_X 2:0 +#define NVCB7D_HEAD_SET_HEAD_POSITION_Y 6:4 +#define NVCB7D_HEAD_SET_DSC_CONTROL(a) (0x000022D4 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_CONTROL_ENABLE 0:0 +#define NVCB7D_HEAD_SET_DSC_CONTROL_ENABLE_FALSE (0x00000000) +#define NVCB7D_HEAD_SET_DSC_CONTROL_ENABLE_TRUE (0x00000001) +#define NVCB7D_HEAD_SET_DSC_CONTROL_AUTO_RESET 3:3 +#define NVCB7D_HEAD_SET_DSC_CONTROL_AUTO_RESET_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_DSC_CONTROL_AUTO_RESET_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION 4:4 +#define NVCB7D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET 5:5 +#define NVCB7D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET_FALSE (0x00000000) +#define NVCB7D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET_TRUE (0x00000001) +#define NVCB7D_HEAD_SET_DSC_CONTROL_FLATNESS_DET_THRESH 15:6 +#define NVCB7D_HEAD_SET_DSC_PPS_CONTROL(a) (0x000022D8 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_CONTROL_ENABLE 0:0 +#define NVCB7D_HEAD_SET_DSC_PPS_CONTROL_ENABLE_FALSE (0x00000000) +#define NVCB7D_HEAD_SET_DSC_PPS_CONTROL_ENABLE_TRUE (0x00000001) +#define NVCB7D_HEAD_SET_DSC_PPS_CONTROL_LOCATION 2:1 +#define NVCB7D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_VBLANK (0x00000000) +#define NVCB7D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_VSYNC (0x00000001) +#define NVCB7D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_LINE (0x00000002) +#define NVCB7D_HEAD_SET_DSC_PPS_CONTROL_SIZE 10:3 +#define NVCB7D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY 11:11 +#define NVCB7D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVCB7D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY_ONCE (0x00000001) +#define NVCB7D_HEAD_SET_DSC_PPS_CONTROL_LINE_ID 26:12 +#define NVCB7D_HEAD_SET_DSC_PPS_CONTROL_LINE_ID_REVERSED 27:27 +#define NVCB7D_HEAD_SET_DSC_PPS_CONTROL_LINE_ID_REVERSED_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_DSC_PPS_CONTROL_LINE_ID_REVERSED_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_DSC_PPS_HEAD(a) (0x000022DC + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_HEAD_BYTE0 7:0 +#define NVCB7D_HEAD_SET_DSC_PPS_HEAD_BYTE1 15:8 +#define NVCB7D_HEAD_SET_DSC_PPS_HEAD_BYTE2 23:16 +#define NVCB7D_HEAD_SET_DSC_PPS_HEAD_BYTE3 31:24 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA0(a) (0x000022E0 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA0_DSC_VERSION_MINOR 3:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA0_DSC_VERSION_MAJOR 7:4 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA0_PPS_IDENTIFIER 15:8 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA0_RESERVED 23:16 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA0_LINEBUF_DEPTH 27:24 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA0_BITS_PER_COMPONENT 31:28 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA1(a) (0x000022E4 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA1_BITS_PER_PIXEL_HIGH 1:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA1_VBR_ENABLE 2:2 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA1_SIMPLE422 3:3 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA1_CONVERT_RGB 4:4 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA1_BLOCK_PRED_ENABLE 5:5 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA1_RESERVED 7:6 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA1_BITS_PER_PIXEL_LOW 15:8 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA1_PIC_HEIGHT_HIGH 23:16 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA1_PIC_HEIGHT_LOW 31:24 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA2(a) (0x000022E8 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA2_PIC_WIDTH_HIGH 7:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA2_PIC_WIDTH_LOW 15:8 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA2_SLICE_HEIGHT_HIGH 23:16 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA2_SLICE_HEIGHT_LOW 31:24 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA3(a) (0x000022EC + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA3_SLICE_WIDTH_HIGH 7:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA3_SLICE_WIDTH_LOW 15:8 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA3_CHUNK_SIZE_HIGH 23:16 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA3_CHUNK_SIZE_LOW 31:24 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA4(a) (0x000022F0 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA4_INITIAL_XMIT_DELAY_HIGH 1:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA4_RESERVED 7:2 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA4_INITIAL_XMIT_DELAY_LOW 15:8 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA4_INITIAL_DEC_DELAY_HIGH 23:16 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA4_INITIAL_DEC_DELAY_LOW 31:24 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA5(a) (0x000022F4 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA5_RESERVED0 7:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA5_INITIAL_SCALE_VALUE 13:8 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA5_RESERVED1 15:14 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA5_SCALE_INCREMENT_INTERVAL_HIGH 23:16 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA5_SCALE_INCREMENT_INTERVAL_LOW 31:24 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA6(a) (0x000022F8 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA6_SCALE_DECREMENT_INTERVAL_HIGH 3:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA6_RESERVED0 7:4 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA6_SCALE_DECREMENT_INTERVAL_LOW 15:8 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA6_RESERVED1 23:16 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA6_FIRST_LINE_BPG_OFFSET 28:24 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA6_RESERVED2 31:29 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA7(a) (0x000022FC + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA7_NFL_BPG_OFFSET_HIGH 7:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA7_NFL_BPG_OFFSET_LOW 15:8 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA7_SLICE_BPG_OFFSET_HIGH 23:16 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA7_SLICE_BPG_OFFSET_LOW 31:24 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA8(a) (0x00002300 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA8_INITIAL_OFFSET_HIGH 7:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA8_INITIAL_OFFSET_LOW 15:8 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA8_FINAL_OFFSET_HIGH 23:16 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA8_FINAL_OFFSET_LOW 31:24 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA9(a) (0x00002304 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA9_FLATNESS_MIN_QP 4:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA9_RESERVED0 7:5 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA9_FLATNESS_MAX_QP 12:8 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA9_RESERVED1 15:13 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA9_RC_MODEL_SIZE_HIGH 23:16 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA9_RC_MODEL_SIZE_LOW 31:24 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA10(a) (0x00002308 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA10_RC_EDGE_FACTOR 3:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA10_RESERVED0 7:4 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA10_RC_QUANT_INCR_LIMIT0 12:8 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA10_RESERVED1 15:13 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA10_RC_QUANT_INCR_LIMIT1 20:16 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA10_RESERVED2 23:21 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA10_RC_TGT_OFFSET_LO 27:24 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA10_RC_TGT_OFFSET_HI 31:28 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA11(a) (0x0000230C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH0 7:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH1 15:8 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH2 23:16 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH3 31:24 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA12(a) (0x00002310 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH4 7:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH5 15:8 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH6 23:16 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH7 31:24 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA13(a) (0x00002314 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH8 7:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH9 15:8 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH10 23:16 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH11 31:24 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA14(a) (0x00002318 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA14_RC_BUF_THRESH12 7:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA14_RC_BUF_THRESH13 15:8 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MAX_QP_HIGH0 18:16 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MIN_QP0 23:19 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_BPG_OFFSET0 29:24 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MAX_QP_LOW0 31:30 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA15(a) (0x0000231C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_HIGH1 2:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MIN_QP1 7:3 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_BPG_OFFSET1 13:8 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_LOW1 15:14 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_HIGH2 18:16 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MIN_QP2 23:19 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_BPG_OFFSET2 29:24 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_LOW2 31:30 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA16(a) (0x00002320 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_HIGH3 2:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MIN_QP3 7:3 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_BPG_OFFSET3 13:8 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_LOW3 15:14 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_HIGH4 18:16 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MIN_QP4 23:19 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_BPG_OFFSET4 29:24 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_LOW4 31:30 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA17(a) (0x00002324 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_HIGH5 2:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MIN_QP5 7:3 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_BPG_OFFSET5 13:8 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_LOW5 15:14 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_HIGH6 18:16 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MIN_QP6 23:19 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_BPG_OFFSET6 29:24 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_LOW6 31:30 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA18(a) (0x00002328 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_HIGH7 2:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MIN_QP7 7:3 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_BPG_OFFSET7 13:8 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_LOW7 15:14 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_HIGH8 18:16 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MIN_QP8 23:19 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_BPG_OFFSET8 29:24 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_LOW8 31:30 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA19(a) (0x0000232C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_HIGH9 2:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MIN_QP9 7:3 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_BPG_OFFSET9 13:8 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_LOW9 15:14 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_HIGH10 18:16 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MIN_QP10 23:19 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_BPG_OFFSET10 29:24 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_LOW10 31:30 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA20(a) (0x00002330 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_HIGH11 2:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MIN_QP11 7:3 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_BPG_OFFSET11 13:8 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_LOW11 15:14 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_HIGH12 18:16 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MIN_QP12 23:19 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_BPG_OFFSET12 29:24 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_LOW12 31:30 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA21(a) (0x00002334 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_HIGH13 2:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MIN_QP13 7:3 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_BPG_OFFSET13 13:8 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_LOW13 15:14 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_HIGH14 18:16 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MIN_QP14 23:19 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_BPG_OFFSET14 29:24 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_LOW14 31:30 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA22(a) (0x00002338 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA22_NATIVE422 0:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA22_NATIVE420 1:1 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA22_RESERVED0 7:2 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA22_SECOND_LINE_BPG_OFFSET 12:8 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA22_RESERVED1 15:13 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA22_NSL_BPG_OFFSET_HIGH 23:16 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA22_NSL_BPG_OFFSETLOW 31:24 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA23(a) (0x0000233C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA23_SECOND_LINE_OFFSET_ADJ_HIGH 7:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA23_SECOND_LINE_OFFSET_ADJ_LOW 15:8 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA23_RESERVED 31:16 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA24(a) (0x00002340 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA24_RESERVED 31:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA25(a) (0x00002344 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA25_RESERVED 31:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA26(a) (0x00002348 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA26_RESERVED 31:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA27(a) (0x0000234C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA27_RESERVED 31:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA28(a) (0x00002350 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA28_RESERVED 31:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA29(a) (0x00002354 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA29_RESERVED 31:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA30(a) (0x00002358 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA30_RESERVED 31:0 +#define NVCB7D_HEAD_SET_DSC_PPS_DATA31(a) (0x0000235C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DSC_PPS_DATA31_RESERVED 31:0 +#define NVCB7D_HEAD_SET_RASTER_HBLANK_DELAY(a) (0x00002364 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_RASTER_HBLANK_DELAY_BLANK_START 15:0 +#define NVCB7D_HEAD_SET_RASTER_HBLANK_DELAY_BLANK_END 31:16 +#define NVCB7D_HEAD_SET_HDMI_DSC_HCACTIVE(a) (0x00002368 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_HDMI_DSC_HCACTIVE_BYTES 15:0 +#define NVCB7D_HEAD_SET_HDMI_DSC_HCACTIVE_TRI_BYTES 31:16 +#define NVCB7D_HEAD_SET_HDMI_DSC_HCBLANK(a) (0x0000236C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_HDMI_DSC_HCBLANK_WIDTH 15:0 +#define NVCB7D_HEAD_SW_RESERVED(a,b) (0x00002370 + (a)*0x00000800 + (b)*0x00000004) +#define NVCB7D_HEAD_SW_RESERVED_VALUE 31:0 +#define NVCB7D_HEAD_SET_DP_CTRL(a) (0x0000237C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DP_CTRL_EFFECTIVE_BITS_PER_PIXEL_ADJ 9:0 +#define NVCB7D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_HI(a,b) (0x00002380 + (a)*0x00000800 + (b)*0x00000004) +#define NVCB7D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_HI_VALUE 31:0 +#define NVCB7D_HEAD_SET_HEAD_INFOFRAME(a) (0x000023A0 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_HEAD_INFOFRAME_FID 7:0 +#define NVCB7D_HEAD_SET_HEAD_INFOFRAME_EN 16:16 +#define NVCB7D_HEAD_SET_HEAD_INFOFRAME_EN_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_HEAD_INFOFRAME_EN_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_INFOFRAME_CTRL(a) (0x000023A4 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_INFOFRAME_CTRL_MODE 1:0 +#define NVCB7D_HEAD_SET_INFOFRAME_CTRL_MODE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_INFOFRAME_CTRL_MODE_EMP_VTEM_QMS (0x00000001) +#define NVCB7D_HEAD_SET_INFOFRAME_CTRL_MODE_EMP_OTHERS (0x00000002) +#define NVCB7D_HEAD_SET_INFOFRAME_CTRL_FREQUENCY 12:12 +#define NVCB7D_HEAD_SET_INFOFRAME_CTRL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVCB7D_HEAD_SET_INFOFRAME_CTRL_FREQUENCY_ONCE (0x00000001) +#define NVCB7D_HEAD_SET_INFOFRAME_CTRL_LOCATION 5:4 +#define NVCB7D_HEAD_SET_INFOFRAME_CTRL_LOCATION_VBLANK (0x00000000) +#define NVCB7D_HEAD_SET_INFOFRAME_CTRL_LOCATION_VSYNC (0x00000001) +#define NVCB7D_HEAD_SET_INFOFRAME_CTRL_LOCATION_LINE (0x00000002) +#define NVCB7D_HEAD_SET_INFOFRAME_CTRL_LINE_ID 30:16 +#define NVCB7D_HEAD_SET_INFOFRAME_CTRL_LINE_ID_REVERSED 31:31 +#define NVCB7D_HEAD_SET_INFOFRAME_CTRL_LINE_ID_REVERSED_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_INFOFRAME_CTRL_LINE_ID_REVERSED_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_INFOFRAME_CTRL_MTD_STATE_CTRL 14:14 +#define NVCB7D_HEAD_SET_INFOFRAME_CTRL_MTD_STATE_CTRL_ACTIVE (0x00000000) +#define NVCB7D_HEAD_SET_INFOFRAME_CTRL_MTD_STATE_CTRL_ARM (0x00000001) +#define NVCB7D_HEAD_SET_INFOFRAME_HEADER(a) (0x000023A8 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_INFOFRAME_HEADER_HB0 7:0 +#define NVCB7D_HEAD_SET_INFOFRAME_HEADER_HB1 15:8 +#define NVCB7D_HEAD_SET_INFOFRAME_HEADER_HB2 23:16 +#define NVCB7D_HEAD_SET_INFOFRAME_HEADER_HB3 31:24 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA0(a) (0x000023AC + (a)*0x00000800) +#define NVCB7D_HEAD_SET_INFOFRAME_DATA0_DB0 7:0 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA0_DB1 15:8 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA0_DB2 23:16 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA0_DB3 31:24 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA1(a) (0x000023B0 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_INFOFRAME_DATA1_DB4 7:0 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA1_DB5 15:8 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA1_DB6 23:16 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA1_DB7 31:24 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA2(a) (0x000023B4 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_INFOFRAME_DATA2_DB8 7:0 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA2_DB9 15:8 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA2_DB10 23:16 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA2_DB11 31:24 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA3(a) (0x000023B8 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_INFOFRAME_DATA3_DB12 7:0 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA3_DB13 15:8 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA3_DB14 23:16 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA3_DB15 31:24 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA4(a) (0x000023BC + (a)*0x00000800) +#define NVCB7D_HEAD_SET_INFOFRAME_DATA4_DB16 7:0 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA4_DB17 15:8 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA4_DB18 23:16 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA4_DB19 31:24 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA5(a) (0x000023C0 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_INFOFRAME_DATA5_DB20 7:0 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA5_DB21 15:8 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA5_DB22 23:16 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA5_DB23 31:24 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA6(a) (0x000023C4 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_INFOFRAME_DATA6_DB24 7:0 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA6_DB25 15:8 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA6_DB26 23:16 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA6_DB27 31:24 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA7(a) (0x000023C8 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_INFOFRAME_DATA7_DB28 7:0 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA7_DB29 15:8 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA7_DB30 23:16 +#define NVCB7D_HEAD_SET_INFOFRAME_DATA7_DB31 31:24 +#define NVCB7D_HEAD_SET_RASTER_SIZE_FRACTION(a) (0x000023CC + (a)*0x00000800) +#define NVCB7D_HEAD_SET_RASTER_SIZE_FRACTION_HEIGHT 15:0 +#define NVCB7D_HEAD_SET_LTM_CONTROL(a) (0x000023D0 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_LTM_CONTROL_ENABLE 0:0 +#define NVCB7D_HEAD_SET_LTM_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_LTM_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_LTM_CONTROL_MODE 1:1 +#define NVCB7D_HEAD_SET_LTM_CONTROL_MODE_TMO (0x00000000) +#define NVCB7D_HEAD_SET_LTM_CONTROL_MODE_LTM (0x00000001) +#define NVCB7D_HEAD_SET_LTM_CONTROL_TONE_SELECT 2:2 +#define NVCB7D_HEAD_SET_LTM_CONTROL_TONE_SELECT_INTENSITY (0x00000000) +#define NVCB7D_HEAD_SET_LTM_CONTROL_TONE_SELECT_CDB (0x00000001) +#define NVCB7D_HEAD_SET_LTM_CONTROL_SKIN_TONE_ENABLE 3:3 +#define NVCB7D_HEAD_SET_LTM_CONTROL_SKIN_TONE_ENABLE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_LTM_CONTROL_SKIN_TONE_ENABLE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_LTM_CONTROL_LUT_INTERPOLATE 4:4 +#define NVCB7D_HEAD_SET_LTM_CONTROL_LUT_INTERPOLATE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_LTM_CONTROL_LUT_INTERPOLATE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT8 5:5 +#define NVCB7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT8_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT8_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT10 6:6 +#define NVCB7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT10_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT10_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT_ROUND 7:7 +#define NVCB7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT_ROUND_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT_ROUND_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_LTM_CONTROL_HIST_SOURCE 9:8 +#define NVCB7D_HEAD_SET_LTM_CONTROL_HIST_SOURCE_MAX_RGB (0x00000000) +#define NVCB7D_HEAD_SET_LTM_CONTROL_HIST_SOURCE_LIN_I (0x00000001) +#define NVCB7D_HEAD_SET_LTM_CONTROL_HIST_SOURCE_PQI (0x00000002) +#define NVCB7D_HEAD_SET_LTM_CONTROL_HIST_SOURCE_CDB (0x00000003) +#define NVCB7D_HEAD_SET_LTM_CONTROL_HIST_RANGE 11:10 +#define NVCB7D_HEAD_SET_LTM_CONTROL_HIST_RANGE_RANGE_10000 (0x00000000) +#define NVCB7D_HEAD_SET_LTM_CONTROL_HIST_RANGE_RANGE_5000 (0x00000001) +#define NVCB7D_HEAD_SET_LTM_CONTROL_HIST_RANGE_RANGE_2500 (0x00000002) +#define NVCB7D_HEAD_SET_LTM_CONTROL_HIST_RANGE_RANGE_1250 (0x00000003) +#define NVCB7D_HEAD_SET_LTM_CONTROL_HIST_END_LINE 31:16 +#define NVCB7D_HEAD_SET_RGB2ITP_COEFF_C00(a) (0x000023D4 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_RGB2ITP_COEFF_C00_VALUE 20:0 +#define NVCB7D_HEAD_SET_RGB2ITP_COEFF_C01(a) (0x000023D8 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_RGB2ITP_COEFF_C01_VALUE 20:0 +#define NVCB7D_HEAD_SET_RGB2ITP_COEFF_C02(a) (0x000023DC + (a)*0x00000800) +#define NVCB7D_HEAD_SET_RGB2ITP_COEFF_C02_VALUE 20:0 +#define NVCB7D_HEAD_SET_RGB2ITP_COEFF_C03(a) (0x000023E0 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_RGB2ITP_COEFF_C03_VALUE 20:0 +#define NVCB7D_HEAD_SET_RGB2ITP_COEFF_C10(a) (0x000023E4 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_RGB2ITP_COEFF_C10_VALUE 20:0 +#define NVCB7D_HEAD_SET_RGB2ITP_COEFF_C11(a) (0x000023E8 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_RGB2ITP_COEFF_C11_VALUE 20:0 +#define NVCB7D_HEAD_SET_RGB2ITP_COEFF_C12(a) (0x000023EC + (a)*0x00000800) +#define NVCB7D_HEAD_SET_RGB2ITP_COEFF_C12_VALUE 20:0 +#define NVCB7D_HEAD_SET_RGB2ITP_COEFF_C13(a) (0x000023F0 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_RGB2ITP_COEFF_C13_VALUE 20:0 +#define NVCB7D_HEAD_SET_RGB2ITP_COEFF_C20(a) (0x000023F4 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_RGB2ITP_COEFF_C20_VALUE 20:0 +#define NVCB7D_HEAD_SET_RGB2ITP_COEFF_C21(a) (0x000023F8 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_RGB2ITP_COEFF_C21_VALUE 20:0 +#define NVCB7D_HEAD_SET_RGB2ITP_COEFF_C22(a) (0x000023FC + (a)*0x00000800) +#define NVCB7D_HEAD_SET_RGB2ITP_COEFF_C22_VALUE 20:0 +#define NVCB7D_HEAD_SET_RGB2ITP_COEFF_C23(a) (0x00002400 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_RGB2ITP_COEFF_C23_VALUE 20:0 +#define NVCB7D_HEAD_SET_ITP2RGB_COEFF_C00(a) (0x00002404 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_ITP2RGB_COEFF_C00_VALUE 20:0 +#define NVCB7D_HEAD_SET_ITP2RGB_COEFF_C01(a) (0x00002408 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_ITP2RGB_COEFF_C01_VALUE 20:0 +#define NVCB7D_HEAD_SET_ITP2RGB_COEFF_C02(a) (0x0000240C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_ITP2RGB_COEFF_C02_VALUE 20:0 +#define NVCB7D_HEAD_SET_ITP2RGB_COEFF_C03(a) (0x00002410 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_ITP2RGB_COEFF_C03_VALUE 20:0 +#define NVCB7D_HEAD_SET_ITP2RGB_COEFF_C10(a) (0x00002414 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_ITP2RGB_COEFF_C10_VALUE 20:0 +#define NVCB7D_HEAD_SET_ITP2RGB_COEFF_C11(a) (0x00002418 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_ITP2RGB_COEFF_C11_VALUE 20:0 +#define NVCB7D_HEAD_SET_ITP2RGB_COEFF_C12(a) (0x0000241C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_ITP2RGB_COEFF_C12_VALUE 20:0 +#define NVCB7D_HEAD_SET_ITP2RGB_COEFF_C13(a) (0x00002420 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_ITP2RGB_COEFF_C13_VALUE 20:0 +#define NVCB7D_HEAD_SET_ITP2RGB_COEFF_C20(a) (0x00002424 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_ITP2RGB_COEFF_C20_VALUE 20:0 +#define NVCB7D_HEAD_SET_ITP2RGB_COEFF_C21(a) (0x00002428 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_ITP2RGB_COEFF_C21_VALUE 20:0 +#define NVCB7D_HEAD_SET_ITP2RGB_COEFF_C22(a) (0x0000242C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_ITP2RGB_COEFF_C22_VALUE 20:0 +#define NVCB7D_HEAD_SET_ITP2RGB_COEFF_C23(a) (0x00002430 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_ITP2RGB_COEFF_C23_VALUE 20:0 +#define NVCB7D_HEAD_SET_LTM_MAX_SELECTIVE_UPDATE(a) (0x00002434 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_LTM_MAX_SELECTIVE_UPDATE_SIZE 31:0 +#define NVCB7D_HEAD_SET_SELF_REFRESH_OVERRIDE(a) (0x00002438 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_SELF_REFRESH_OVERRIDE_FRAME_RELEASE 0:0 +#define NVCB7D_HEAD_SET_SELF_REFRESH_OVERRIDE_FRAME_RELEASE_AUTOMATIC (0x00000000) +#define NVCB7D_HEAD_SET_SELF_REFRESH_OVERRIDE_FRAME_RELEASE_MANUAL (0x00000001) +#define NVCB7D_HEAD_SET_SELECTIVE_UPDATE(a) (0x0000243C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_SELECTIVE_UPDATE_ENABLE 0:0 +#define NVCB7D_HEAD_SET_SELECTIVE_UPDATE_ENABLE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_SELECTIVE_UPDATE_ENABLE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_SELECTIVE_UPDATE_EARLY_REGION 1:1 +#define NVCB7D_HEAD_SET_SELECTIVE_UPDATE_EARLY_REGION_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_SELECTIVE_UPDATE_EARLY_REGION_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_CURSOR_DIRTY(a) (0x00002440 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_CURSOR_DIRTY_STATE 0:0 +#define NVCB7D_HEAD_SET_CURSOR_DIRTY_STATE_FALSE (0x00000000) +#define NVCB7D_HEAD_SET_CURSOR_DIRTY_STATE_TRUE (0x00000001) +#define NVCB7D_HEAD_SET_DPM_CONTROL(a) (0x00002444 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_DPM_CONTROL_ENABLE 0:0 +#define NVCB7D_HEAD_SET_DPM_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_DPM_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_DPM_CONTROL_ALPM 1:1 +#define NVCB7D_HEAD_SET_DPM_CONTROL_ALPM_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_DPM_CONTROL_ALPM_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_DPM_CONTROL_ALPM_TYPE 2:2 +#define NVCB7D_HEAD_SET_DPM_CONTROL_ALPM_TYPE_AUX_LESS (0x00000000) +#define NVCB7D_HEAD_SET_DPM_CONTROL_AS_SDP 3:3 +#define NVCB7D_HEAD_SET_DPM_CONTROL_AS_SDP_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_DPM_CONTROL_AS_SDP_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL(a) (0x00002448 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_ENABLE 0:0 +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_ENABLE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_ENABLE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_SELF_REFRESH 1:1 +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_SELF_REFRESH_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_SELF_REFRESH_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_MODE 3:2 +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_MODE_PSR1 (0x00000000) +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_MODE_PANEL_REPLAY (0x00000002) +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_CRC 4:4 +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_CRC_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_CRC_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_LOCATION 7:6 +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_LOCATION_VBLANK (0x00000000) +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_LOCATION_VSYNC (0x00000001) +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_LOCATION_LINE (0x00000002) +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_LINE_ID 22:8 +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_CAPTURE_INDICATOR 23:23 +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_CAPTURE_INDICATOR_SAME (0x00000000) +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_CAPTURE_INDICATOR_EARLY (0x00000001) +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_IDLE_SDP 24:24 +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_IDLE_SDP_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_IDLE_SDP_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_OVERRIDE_SU_VSC 25:25 +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_OVERRIDE_SU_VSC_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_VSC_SDP_CTRL_OVERRIDE_SU_VSC_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_VSC_SDP_HEADER(a) (0x0000244C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_VSC_SDP_HEADER_HEADER_BYTE 31:0 +#define NVCB7D_HEAD_SET_VSC_SDP_DATA0(a) (0x00002450 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_VSC_SDP_DATA0_DATA_BYTE 31:0 +#define NVCB7D_HEAD_SET_VSC_SDP_DATA1(a) (0x00002454 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_VSC_SDP_DATA1_DATA_BYTE 31:0 +#define NVCB7D_HEAD_SET_VSC_SDP_DATA2(a) (0x00002458 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_VSC_SDP_DATA2_DATA_BYTE 31:0 +#define NVCB7D_HEAD_SET_VSC_SDP_DATA3(a) (0x0000245C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_VSC_SDP_DATA3_DATA_BYTE 31:0 +#define NVCB7D_HEAD_SET_VSC_SDP_DATA4(a) (0x00002460 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_VSC_SDP_DATA4_DATA_BYTE 31:0 +#define NVCB7D_HEAD_SET_VSC_SDP_DATA5(a) (0x00002464 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_VSC_SDP_DATA5_DATA_BYTE 31:0 +#define NVCB7D_HEAD_SET_VSC_SDP_DATA6(a) (0x00002468 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_VSC_SDP_DATA6_DATA_BYTE 31:0 +#define NVCB7D_HEAD_SET_VSC_SDP_DATA7(a) (0x0000246C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_VSC_SDP_DATA7_DATA_BYTE 31:0 +#define NVCB7D_HEAD_SET_RGB2ITP_CONTROL(a) (0x00002470 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_INPUT_MATRIX 0:0 +#define NVCB7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_INPUT_MATRIX_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_INPUT_MATRIX_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_FVLUT 1:1 +#define NVCB7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_FVLUT_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_FVLUT_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_INTERPOLATE 4:4 +#define NVCB7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_INTERPOLATE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_INTERPOLATE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_MIRROR 5:5 +#define NVCB7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_MIRROR_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_MIRROR_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_CURVE 7:6 +#define NVCB7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_CURVE_CSCLUT_PQ (0x00000000) +#define NVCB7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_CURVE_CSCLUT_HLG (0x00000001) +#define NVCB7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_CURVE_CSCLUT_DIRECT (0x00000002) +#define NVCB7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_OUTPUT_MATRIX 2:2 +#define NVCB7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_OUTPUT_MATRIX_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_OUTPUT_MATRIX_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_RGB2ITP_LUT_FP_NORM_SCALE(a) (0x00002474 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_RGB2ITP_LUT_FP_NORM_SCALE_VALUE 31:0 +#define NVCB7D_HEAD_SET_ITP2RGB_CONTROL(a) (0x00002478 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_INPUT_MATRIX 0:0 +#define NVCB7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_INPUT_MATRIX_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_INPUT_MATRIX_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_FVLUT 1:1 +#define NVCB7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_FVLUT_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_FVLUT_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_INTERPOLATE 4:4 +#define NVCB7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_INTERPOLATE_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_INTERPOLATE_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_MIRROR 5:5 +#define NVCB7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_MIRROR_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_MIRROR_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_CURVE 7:6 +#define NVCB7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_CURVE_CSCLUT_PQ (0x00000000) +#define NVCB7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_CURVE_CSCLUT_HLG (0x00000001) +#define NVCB7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_CURVE_CSCLUT_DIRECT (0x00000002) +#define NVCB7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_OUTPUT_MATRIX 2:2 +#define NVCB7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_OUTPUT_MATRIX_DISABLE (0x00000000) +#define NVCB7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_OUTPUT_MATRIX_ENABLE (0x00000001) +#define NVCB7D_HEAD_SET_ITP2RGB_LUT_FP_SCALE(a) (0x0000247C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_ITP2RGB_LUT_FP_SCALE_VALUE 15:0 +#define NVCB7D_HEAD_SET_BLANK_OUTPUT_COLOR(a) (0x00002484 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_BLANK_OUTPUT_COLOR_RED_CR 9:0 +#define NVCB7D_HEAD_SET_BLANK_OUTPUT_COLOR_GREEN_Y 19:10 +#define NVCB7D_HEAD_SET_BLANK_OUTPUT_COLOR_BLUE_CB 29:20 +#define NVCB7D_HEAD_SET_SELECTIVE_UPDATE_GRANULARITY(a) (0x0000249C + (a)*0x00000800) +#define NVCB7D_HEAD_SET_SELECTIVE_UPDATE_GRANULARITY_X 15:0 +#define NVCB7D_HEAD_SET_SELECTIVE_UPDATE_GRANULARITY_Y 31:16 +#define NVCB7D_HEAD_SET_LTM_HIST_COEFF_C00(a) (0x000024A0 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_LTM_HIST_COEFF_C00_VALUE 20:0 +#define NVCB7D_HEAD_SET_LTM_HIST_COEFF_C01(a) (0x000024A4 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_LTM_HIST_COEFF_C01_VALUE 20:0 +#define NVCB7D_HEAD_SET_LTM_HIST_COEFF_C02(a) (0x000024A8 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_LTM_HIST_COEFF_C02_VALUE 20:0 +#define NVCB7D_HEAD_SET_LTM_HIST_COEFF_C03(a) (0x000024AC + (a)*0x00000800) +#define NVCB7D_HEAD_SET_LTM_HIST_COEFF_C03_VALUE 20:0 +#define NVCB7D_HEAD_SET_LTM_HIST_COEFF_C10(a) (0x000024B0 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_LTM_HIST_COEFF_C10_VALUE 20:0 +#define NVCB7D_HEAD_SET_LTM_HIST_COEFF_C11(a) (0x000024B4 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_LTM_HIST_COEFF_C11_VALUE 20:0 +#define NVCB7D_HEAD_SET_LTM_HIST_COEFF_C12(a) (0x000024B8 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_LTM_HIST_COEFF_C12_VALUE 20:0 +#define NVCB7D_HEAD_SET_LTM_HIST_COEFF_C13(a) (0x000024BC + (a)*0x00000800) +#define NVCB7D_HEAD_SET_LTM_HIST_COEFF_C13_VALUE 20:0 +#define NVCB7D_HEAD_SET_LTM_HIST_COEFF_C20(a) (0x000024C0 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_LTM_HIST_COEFF_C20_VALUE 20:0 +#define NVCB7D_HEAD_SET_LTM_HIST_COEFF_C21(a) (0x000024C4 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_LTM_HIST_COEFF_C21_VALUE 20:0 +#define NVCB7D_HEAD_SET_LTM_HIST_COEFF_C22(a) (0x000024C8 + (a)*0x00000800) +#define NVCB7D_HEAD_SET_LTM_HIST_COEFF_C22_VALUE 20:0 +#define NVCB7D_HEAD_SET_LTM_HIST_COEFF_C23(a) (0x000024CC + (a)*0x00000800) +#define NVCB7D_HEAD_SET_LTM_HIST_COEFF_C23_VALUE 20:0 + +#define NVCB7D_TILE_SET_TILE_SIZE(a) (0x00006000 + (a)*0x00000200) +#define NVCB7D_TILE_SET_TILE_SIZE_START 14:0 +#define NVCB7D_TILE_SET_TILE_SIZE_WIDTH 30:16 +#define NVCB7D_TILE_SET_CMI_LUT_SEGMENT_SIZE(a) (0x00006074 + (a)*0x00000200) +#define NVCB7D_TILE_SET_CMI_LUT_SEGMENT_SIZE_IDX 5:0 +#define NVCB7D_TILE_SET_CMI_LUT_SEGMENT_SIZE_VALUE 8:6 +#define NVCB7D_TILE_SET_CMI_LUT_ENTRY(a) (0x00006078 + (a)*0x00000200) +#define NVCB7D_TILE_SET_CMI_LUT_ENTRY_IDX 10:0 +#define NVCB7D_TILE_SET_CMI_LUT_ENTRY_VALUE 24:11 +#define NVCB7D_TILE_SET_CMI_LUT_ENTRY_LAST 25:25 +#define NVCB7D_TILE_SET_CMI_LUT_ENTRY_LAST_FALSE (0x00000000) +#define NVCB7D_TILE_SET_CMI_LUT_ENTRY_LAST_TRUE (0x00000001) +#define NVCB7D_TILE_SET_CMO_LUT_SEGMENT_SIZE(a) (0x0000607C + (a)*0x00000200) +#define NVCB7D_TILE_SET_CMO_LUT_SEGMENT_SIZE_IDX 5:0 +#define NVCB7D_TILE_SET_CMO_LUT_SEGMENT_SIZE_VALUE 8:6 +#define NVCB7D_TILE_SET_CMO_LUT_ENTRY(a) (0x00006080 + (a)*0x00000200) +#define NVCB7D_TILE_SET_CMO_LUT_ENTRY_IDX 10:0 +#define NVCB7D_TILE_SET_CMO_LUT_ENTRY_VALUE 26:11 +#define NVCB7D_TILE_SET_CMO_LUT_ENTRY_LAST 27:27 +#define NVCB7D_TILE_SET_CMO_LUT_ENTRY_LAST_FALSE (0x00000000) +#define NVCB7D_TILE_SET_CMO_LUT_ENTRY_LAST_TRUE (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clcb7d_h diff --git a/userspace/sdks/nv570/inc/class/clcb7e.h b/userspace/sdks/nv570/inc/class/clcb7e.h new file mode 100644 index 0000000..de38e2e --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcb7e.h @@ -0,0 +1,906 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clcb7e_h_ +#define _clcb7e_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVCB7E_WINDOW_CHANNEL_DMA (0x0000CB7E) + +// dma opcode instructions +#define NVCB7E_DMA +#define NVCB7E_DMA_OPCODE 31:29 +#define NVCB7E_DMA_OPCODE_METHOD 0x00000000 +#define NVCB7E_DMA_OPCODE_JUMP 0x00000001 +#define NVCB7E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVCB7E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVCB7E_DMA_METHOD_COUNT 27:18 +#define NVCB7E_DMA_METHOD_OFFSET 15:2 +#define NVCB7E_DMA_DATA 31:0 +#define NVCB7E_DMA_DATA_NOP 0x00000000 +#define NVCB7E_DMA_JUMP_OFFSET 15:2 +#define NVCB7E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVCB7E_PUT (0x00000000) +#define NVCB7E_PUT_PTR 13:0 +#define NVCB7E_GET (0x00000004) +#define NVCB7E_GET_PTR 13:0 +#define NVCB7E_UPDATE (0x00000200) +#define NVCB7E_UPDATE_RELEASE_ELV 0:0 +#define NVCB7E_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVCB7E_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVCB7E_UPDATE_INTERLOCK_WITH_WIN_IMM 12:12 +#define NVCB7E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE (0x00000000) +#define NVCB7E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE (0x00000001) +#define NVCB7E_UPDATE_FORCE_FULLSCREEN 16:16 +#define NVCB7E_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000) +#define NVCB7E_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001) +#define NVCB7E_SET_SEMAPHORE_ACQUIRE_HI (0x00000204) +#define NVCB7E_SET_SEMAPHORE_ACQUIRE_HI_VALUE 31:0 +#define NVCB7E_GET_LINE (0x00000208) +#define NVCB7E_GET_LINE_LINE 15:0 +#define NVCB7E_SET_SEMAPHORE_CONTROL (0x0000020C) +#define NVCB7E_SET_SEMAPHORE_CONTROL_SKIP_ACQ 11:11 +#define NVCB7E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_FALSE (0x00000000) +#define NVCB7E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_TRUE (0x00000001) +#define NVCB7E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVCB7E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVCB7E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVCB7E_SET_SEMAPHORE_CONTROL_ACQ_MODE 13:12 +#define NVCB7E_SET_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000) +#define NVCB7E_SET_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001) +#define NVCB7E_SET_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002) +#define NVCB7E_SET_SEMAPHORE_CONTROL_REL_MODE 14:14 +#define NVCB7E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE (0x00000000) +#define NVCB7E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE_AWAKEN (0x00000001) +#define NVCB7E_SET_SEMAPHORE_ACQUIRE (0x00000210) +#define NVCB7E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NVCB7E_SET_SEMAPHORE_RELEASE (0x00000214) +#define NVCB7E_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NVCB7E_SET_NOTIFIER_CONTROL (0x00000220) +#define NVCB7E_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVCB7E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVCB7E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVCB7E_SET_SIZE (0x00000224) +#define NVCB7E_SET_SIZE_WIDTH 15:0 +#define NVCB7E_SET_SIZE_HEIGHT 31:16 +#define NVCB7E_SET_STORAGE (0x00000228) +#define NVCB7E_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NVCB7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NVCB7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NVCB7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NVCB7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVCB7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVCB7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVCB7E_SET_PARAMS (0x0000022C) +#define NVCB7E_SET_PARAMS_FORMAT 7:0 +#define NVCB7E_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NVCB7E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F) +#define NVCB7E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NVCB7E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NVCB7E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E) +#define NVCB7E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NVCB7E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6) +#define NVCB7E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NVCB7E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9) +#define NVCB7E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NVCB7E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NVCB7E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NVCB7E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NVCB7E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NVCB7E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028) +#define NVCB7E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029) +#define NVCB7E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035) +#define NVCB7E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036) +#define NVCB7E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038) +#define NVCB7E_SET_PARAMS_FORMAT_Y8___U8___V8_N444 (0x0000003A) +#define NVCB7E_SET_PARAMS_FORMAT_Y8___U8___V8_N420 (0x0000003B) +#define NVCB7E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055) +#define NVCB7E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056) +#define NVCB7E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058) +#define NVCB7E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075) +#define NVCB7E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076) +#define NVCB7E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078) +#define NVCB7E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18 +#define NVCB7E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000) +#define NVCB7E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001) +#define NVCB7E_SET_PARAMS_SWAP_UV 19:19 +#define NVCB7E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000) +#define NVCB7E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001) +#define NVCB7E_SET_PARAMS_FMT_ROUNDING_MODE 22:22 +#define NVCB7E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_TO_NEAREST (0x00000000) +#define NVCB7E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_DOWN (0x00000001) +#define NVCB7E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004) +#define NVCB7E_SET_PLANAR_STORAGE_PITCH 12:0 +#define NVCB7E_SET_SEMAPHORE_RELEASE_HI (0x0000023C) +#define NVCB7E_SET_SEMAPHORE_RELEASE_HI_VALUE 31:0 +#define NVCB7E_SET_SURFACE_ADDRESS_HI_BEGUN_SEMAPHORE_ARRAY (0x00000240) +#define NVCB7E_SET_SURFACE_ADDRESS_HI_BEGUN_SEMAPHORE_ARRAY_ADDRESS_HI 31:0 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY (0x00000244) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ADDRESS_LO 31:4 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET 3:2 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_IOVA (0x00000000) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ENABLE 0:0 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ENABLE_DISABLE (0x00000000) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ENABLE_ENABLE (0x00000001) +#define NVCB7E_SET_SURFACE_ADDRESS_HI_FINISH_SEMAPHORE_ARRAY (0x00000248) +#define NVCB7E_SET_SURFACE_ADDRESS_HI_FINISH_SEMAPHORE_ARRAY_ADDRESS_HI 31:0 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY (0x0000024C) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ADDRESS_LO 31:4 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET 3:2 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_IOVA (0x00000000) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ENABLE 0:0 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ENABLE_DISABLE (0x00000000) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ENABLE_ENABLE (0x00000001) +#define NVCB7E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004) +#define NVCB7E_SET_POINT_IN_X 15:0 +#define NVCB7E_SET_POINT_IN_Y 31:16 +#define NVCB7E_SET_SIZE_IN (0x00000298) +#define NVCB7E_SET_SIZE_IN_WIDTH 15:0 +#define NVCB7E_SET_SIZE_IN_HEIGHT 31:16 +#define NVCB7E_SET_SIZE_OUT (0x000002A4) +#define NVCB7E_SET_SIZE_OUT_WIDTH 15:0 +#define NVCB7E_SET_SIZE_OUT_HEIGHT 31:16 +#define NVCB7E_SET_CONTROL_INPUT_SCALER (0x000002A8) +#define NVCB7E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVCB7E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVCB7E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVCB7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVCB7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVCB7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVCB7E_SET_CONTROL_INPUT_SCALER_VERTICAL_FORCE_ENABLE 8:8 +#define NVCB7E_SET_CONTROL_INPUT_SCALER_VERTICAL_FORCE_ENABLE_DISABLE (0x00000000) +#define NVCB7E_SET_CONTROL_INPUT_SCALER_VERTICAL_FORCE_ENABLE_ENABLE (0x00000001) +#define NVCB7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_FORCE_ENABLE 9:9 +#define NVCB7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_FORCE_ENABLE_DISABLE (0x00000000) +#define NVCB7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_FORCE_ENABLE_ENABLE (0x00000001) +#define NVCB7E_SET_INPUT_SCALER_COEFF_VALUE (0x000002AC) +#define NVCB7E_SET_INPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVCB7E_SET_INPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVCB7E_SET_COMPOSITION_CONTROL (0x000002EC) +#define NVCB7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0 +#define NVCB7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000) +#define NVCB7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001) +#define NVCB7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002) +#define NVCB7E_SET_COMPOSITION_CONTROL_DEPTH 11:4 +#define NVCB7E_SET_COMPOSITION_CONTROL_BYPASS 16:16 +#define NVCB7E_SET_COMPOSITION_CONTROL_BYPASS_DISABLE (0x00000000) +#define NVCB7E_SET_COMPOSITION_CONTROL_BYPASS_ENABLE (0x00000001) +#define NVCB7E_SET_COMPOSITION_CONSTANT_ALPHA (0x000002F0) +#define NVCB7E_SET_COMPOSITION_CONSTANT_ALPHA_K1 7:0 +#define NVCB7E_SET_COMPOSITION_CONSTANT_ALPHA_K2 15:8 +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT (0x000002F4) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0 +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4 +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8 +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12 +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16 +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20 +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24 +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28 +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVCB7E_SET_KEY_ALPHA (0x000002F8) +#define NVCB7E_SET_KEY_ALPHA_MIN 15:0 +#define NVCB7E_SET_KEY_ALPHA_MAX 31:16 +#define NVCB7E_SET_KEY_RED_CR (0x000002FC) +#define NVCB7E_SET_KEY_RED_CR_MIN 15:0 +#define NVCB7E_SET_KEY_RED_CR_MAX 31:16 +#define NVCB7E_SET_KEY_GREEN_Y (0x00000300) +#define NVCB7E_SET_KEY_GREEN_Y_MIN 15:0 +#define NVCB7E_SET_KEY_GREEN_Y_MAX 31:16 +#define NVCB7E_SET_KEY_BLUE_CB (0x00000304) +#define NVCB7E_SET_KEY_BLUE_CB_MIN 15:0 +#define NVCB7E_SET_KEY_BLUE_CB_MAX 31:16 +#define NVCB7E_SET_PRESENT_CONTROL (0x00000308) +#define NVCB7E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NVCB7E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4 +#define NVCB7E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NVCB7E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NVCB7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8 +#define NVCB7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000) +#define NVCB7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001) +#define NVCB7E_SET_PRESENT_CONTROL_STEREO_MODE 13:12 +#define NVCB7E_SET_PRESENT_CONTROL_STEREO_MODE_MONO (0x00000000) +#define NVCB7E_SET_PRESENT_CONTROL_STEREO_MODE_PAIR_FLIP (0x00000001) +#define NVCB7E_SET_PRESENT_CONTROL_STEREO_MODE_AT_ANY_FRAME (0x00000002) +#define NVCB7E_SET_ACQ_SEMAPHORE_VALUE_HI (0x0000030C) +#define NVCB7E_SET_ACQ_SEMAPHORE_VALUE_HI_VALUE 31:0 +#define NVCB7E_SET_ACQ_SEMAPHORE_CONTROL (0x00000330) +#define NVCB7E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVCB7E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVCB7E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVCB7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE 13:12 +#define NVCB7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000) +#define NVCB7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001) +#define NVCB7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002) +#define NVCB7E_SET_ACQ_SEMAPHORE_VALUE (0x00000334) +#define NVCB7E_SET_ACQ_SEMAPHORE_VALUE_VALUE 31:0 +#define NVCB7E_SET_SCAN_DIRECTION (0x0000033C) +#define NVCB7E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION 0:0 +#define NVCB7E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_LEFT (0x00000000) +#define NVCB7E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_RIGHT (0x00000001) +#define NVCB7E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION 1:1 +#define NVCB7E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_TOP (0x00000000) +#define NVCB7E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_BOTTOM (0x00000001) +#define NVCB7E_SET_SCAN_DIRECTION_COLUMN_ORDER 2:2 +#define NVCB7E_SET_SCAN_DIRECTION_COLUMN_ORDER_FALSE (0x00000000) +#define NVCB7E_SET_SCAN_DIRECTION_COLUMN_ORDER_TRUE (0x00000001) +#define NVCB7E_SET_TIMESTAMP_ORIGIN_LO (0x00000340) +#define NVCB7E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NVCB7E_SET_TIMESTAMP_ORIGIN_HI (0x00000344) +#define NVCB7E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NVCB7E_SET_UPDATE_TIMESTAMP_LO (0x00000348) +#define NVCB7E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NVCB7E_SET_UPDATE_TIMESTAMP_HI (0x0000034C) +#define NVCB7E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NVCB7E_SET_INTERLOCK_FLAGS (0x00000370) +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 0:0 +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+1):((i)+1) +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 1:1 +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 2:2 +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 3:3 +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 4:4 +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 5:5 +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 6:6 +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 7:7 +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 8:8 +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS (0x00000374) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVCB7E_SET_CHROMA_VER (0x00000378) +#define NVCB7E_SET_CHROMA_VER_POSITION 1:0 +#define NVCB7E_SET_CHROMA_VER_POSITION_TOP (0x00000000) +#define NVCB7E_SET_CHROMA_VER_POSITION_CENTER (0x00000001) +#define NVCB7E_SET_CHROMA_VER_POSITION_BOTTOM (0x00000002) +#define NVCB7E_SET_CHROMA_VER_USE_SWPOSITION 2:2 +#define NVCB7E_SET_CHROMA_VER_USE_SWPOSITION_FALSE (0x00000000) +#define NVCB7E_SET_CHROMA_VER_USE_SWPOSITION_TRUE (0x00000001) +#define NVCB7E_SET_CHROMA_VER_WEIGHT_ODD 4:3 +#define NVCB7E_SET_CHROMA_VER_WEIGHT_ODD_WT_0 (0x00000000) +#define NVCB7E_SET_CHROMA_VER_WEIGHT_ODD_WT_QUARTER (0x00000001) +#define NVCB7E_SET_CHROMA_VER_WEIGHT_ODD_WT_HALF (0x00000002) +#define NVCB7E_SET_CHROMA_VER_WEIGHT_ODD_WT_THREE_QUARTER (0x00000003) +#define NVCB7E_SET_CHROMA_VER_WEIGHT_EVEN 6:5 +#define NVCB7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_0 (0x00000000) +#define NVCB7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_QUARTER (0x00000001) +#define NVCB7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_HALF (0x00000002) +#define NVCB7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_THREE_QUARTER (0x00000003) +#define NVCB7E_SET_CHROMA_VER_USE_SWWEIGHTS 7:7 +#define NVCB7E_SET_CHROMA_VER_USE_SWWEIGHTS_FALSE (0x00000000) +#define NVCB7E_SET_CHROMA_VER_USE_SWWEIGHTS_TRUE (0x00000001) +#define NVCB7E_SET_CHROMA_HOR (0x0000037C) +#define NVCB7E_SET_CHROMA_HOR_REPLACE_ODD 0:0 +#define NVCB7E_SET_CHROMA_HOR_REPLACE_ODD_DISABLE (0x00000000) +#define NVCB7E_SET_CHROMA_HOR_REPLACE_ODD_ENABLE (0x00000001) +#define NVCB7E_SET_CHROMA_HOR_REPLACE_EVEN 1:1 +#define NVCB7E_SET_CHROMA_HOR_REPLACE_EVEN_DISABLE (0x00000000) +#define NVCB7E_SET_CHROMA_HOR_REPLACE_EVEN_ENABLE (0x00000001) +#define NVCB7E_SET_CHROMA_HOR_WEIGHT_ODD 3:2 +#define NVCB7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_0 (0x00000000) +#define NVCB7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_QUARTER (0x00000001) +#define NVCB7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_HALF (0x00000002) +#define NVCB7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_THREE_QUARTER (0x00000003) +#define NVCB7E_SET_CHROMA_HOR_WEIGHT_EVEN 5:4 +#define NVCB7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_0 (0x00000000) +#define NVCB7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_QUARTER (0x00000001) +#define NVCB7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_HALF (0x00000002) +#define NVCB7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_THREE_QUARTER (0x00000003) +#define NVCB7E_SET_CHROMA_HOR_USE_SWWEIGHTS 6:6 +#define NVCB7E_SET_CHROMA_HOR_USE_SWWEIGHTS_FALSE (0x00000000) +#define NVCB7E_SET_CHROMA_HOR_USE_SWWEIGHTS_TRUE (0x00000001) +#define NVCB7E_SET_EXT_PACKET_CONTROL (0x00000398) +#define NVCB7E_SET_EXT_PACKET_CONTROL_ENABLE 0:0 +#define NVCB7E_SET_EXT_PACKET_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCB7E_SET_EXT_PACKET_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCB7E_SET_EXT_PACKET_CONTROL_LOCATION 4:4 +#define NVCB7E_SET_EXT_PACKET_CONTROL_LOCATION_VSYNC (0x00000000) +#define NVCB7E_SET_EXT_PACKET_CONTROL_LOCATION_VBLANK (0x00000001) +#define NVCB7E_SET_EXT_PACKET_CONTROL_FREQUENCY 8:8 +#define NVCB7E_SET_EXT_PACKET_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVCB7E_SET_EXT_PACKET_CONTROL_FREQUENCY_ONCE (0x00000001) +#define NVCB7E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE 12:12 +#define NVCB7E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_DISABLE (0x00000000) +#define NVCB7E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_ENABLE (0x00000001) +#define NVCB7E_SET_EXT_PACKET_CONTROL_SIZE 27:16 +#define NVCB7E_SET_EXT_PACKET_DATA (0x0000039C) +#define NVCB7E_SET_EXT_PACKET_DATA_DB0 7:0 +#define NVCB7E_SET_EXT_PACKET_DATA_DB1 15:8 +#define NVCB7E_SET_EXT_PACKET_DATA_DB2 23:16 +#define NVCB7E_SET_EXT_PACKET_DATA_DB3 31:24 +#define NVCB7E_SET_WIN_INFOFRAME (0x000003A0) +#define NVCB7E_SET_WIN_INFOFRAME_FID 7:0 +#define NVCB7E_SET_WIN_INFOFRAME_EN 16:16 +#define NVCB7E_SET_WIN_INFOFRAME_EN_DISABLE (0x00000000) +#define NVCB7E_SET_WIN_INFOFRAME_EN_ENABLE (0x00000001) +#define NVCB7E_SET_FMT_COEFFICIENT_C00 (0x00000400) +#define NVCB7E_SET_FMT_COEFFICIENT_C00_VALUE 20:0 +#define NVCB7E_SET_FMT_COEFFICIENT_C01 (0x00000404) +#define NVCB7E_SET_FMT_COEFFICIENT_C01_VALUE 20:0 +#define NVCB7E_SET_FMT_COEFFICIENT_C02 (0x00000408) +#define NVCB7E_SET_FMT_COEFFICIENT_C02_VALUE 20:0 +#define NVCB7E_SET_FMT_COEFFICIENT_C03 (0x0000040C) +#define NVCB7E_SET_FMT_COEFFICIENT_C03_VALUE 20:0 +#define NVCB7E_SET_FMT_COEFFICIENT_C10 (0x00000410) +#define NVCB7E_SET_FMT_COEFFICIENT_C10_VALUE 20:0 +#define NVCB7E_SET_FMT_COEFFICIENT_C11 (0x00000414) +#define NVCB7E_SET_FMT_COEFFICIENT_C11_VALUE 20:0 +#define NVCB7E_SET_FMT_COEFFICIENT_C12 (0x00000418) +#define NVCB7E_SET_FMT_COEFFICIENT_C12_VALUE 20:0 +#define NVCB7E_SET_FMT_COEFFICIENT_C13 (0x0000041C) +#define NVCB7E_SET_FMT_COEFFICIENT_C13_VALUE 20:0 +#define NVCB7E_SET_FMT_COEFFICIENT_C20 (0x00000420) +#define NVCB7E_SET_FMT_COEFFICIENT_C20_VALUE 20:0 +#define NVCB7E_SET_FMT_COEFFICIENT_C21 (0x00000424) +#define NVCB7E_SET_FMT_COEFFICIENT_C21_VALUE 20:0 +#define NVCB7E_SET_FMT_COEFFICIENT_C22 (0x00000428) +#define NVCB7E_SET_FMT_COEFFICIENT_C22_VALUE 20:0 +#define NVCB7E_SET_FMT_COEFFICIENT_C23 (0x0000042C) +#define NVCB7E_SET_FMT_COEFFICIENT_C23_VALUE 20:0 +#define NVCB7E_SET_ILUT_CONTROL (0x00000440) +#define NVCB7E_SET_ILUT_CONTROL_INTERPOLATE 0:0 +#define NVCB7E_SET_ILUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVCB7E_SET_ILUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVCB7E_SET_ILUT_CONTROL_MIRROR 1:1 +#define NVCB7E_SET_ILUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVCB7E_SET_ILUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVCB7E_SET_ILUT_CONTROL_MODE 3:2 +#define NVCB7E_SET_ILUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVCB7E_SET_ILUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVCB7E_SET_ILUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVCB7E_SET_ILUT_CONTROL_SIZE 18:8 +#define NVCB7E_SET_CSC00CONTROL (0x0000045C) +#define NVCB7E_SET_CSC00CONTROL_ENABLE 0:0 +#define NVCB7E_SET_CSC00CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCB7E_SET_CSC00CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCB7E_SET_CSC00COEFFICIENT_C00 (0x00000460) +#define NVCB7E_SET_CSC00COEFFICIENT_C00_VALUE 20:0 +#define NVCB7E_SET_CSC00COEFFICIENT_C01 (0x00000464) +#define NVCB7E_SET_CSC00COEFFICIENT_C01_VALUE 20:0 +#define NVCB7E_SET_CSC00COEFFICIENT_C02 (0x00000468) +#define NVCB7E_SET_CSC00COEFFICIENT_C02_VALUE 20:0 +#define NVCB7E_SET_CSC00COEFFICIENT_C03 (0x0000046C) +#define NVCB7E_SET_CSC00COEFFICIENT_C03_VALUE 20:0 +#define NVCB7E_SET_CSC00COEFFICIENT_C10 (0x00000470) +#define NVCB7E_SET_CSC00COEFFICIENT_C10_VALUE 20:0 +#define NVCB7E_SET_CSC00COEFFICIENT_C11 (0x00000474) +#define NVCB7E_SET_CSC00COEFFICIENT_C11_VALUE 20:0 +#define NVCB7E_SET_CSC00COEFFICIENT_C12 (0x00000478) +#define NVCB7E_SET_CSC00COEFFICIENT_C12_VALUE 20:0 +#define NVCB7E_SET_CSC00COEFFICIENT_C13 (0x0000047C) +#define NVCB7E_SET_CSC00COEFFICIENT_C13_VALUE 20:0 +#define NVCB7E_SET_CSC00COEFFICIENT_C20 (0x00000480) +#define NVCB7E_SET_CSC00COEFFICIENT_C20_VALUE 20:0 +#define NVCB7E_SET_CSC00COEFFICIENT_C21 (0x00000484) +#define NVCB7E_SET_CSC00COEFFICIENT_C21_VALUE 20:0 +#define NVCB7E_SET_CSC00COEFFICIENT_C22 (0x00000488) +#define NVCB7E_SET_CSC00COEFFICIENT_C22_VALUE 20:0 +#define NVCB7E_SET_CSC00COEFFICIENT_C23 (0x0000048C) +#define NVCB7E_SET_CSC00COEFFICIENT_C23_VALUE 20:0 +#define NVCB7E_SET_CSC0LUT_FP_NORM_SCALE (0x00000490) +#define NVCB7E_SET_CSC0LUT_FP_NORM_SCALE_VALUE 31:0 +#define NVCB7E_SET_CSC0LUT_CONTROL (0x000004A0) +#define NVCB7E_SET_CSC0LUT_CONTROL_INTERPOLATE 0:0 +#define NVCB7E_SET_CSC0LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVCB7E_SET_CSC0LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVCB7E_SET_CSC0LUT_CONTROL_MIRROR 1:1 +#define NVCB7E_SET_CSC0LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVCB7E_SET_CSC0LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVCB7E_SET_CSC0LUT_CONTROL_ENABLE 4:4 +#define NVCB7E_SET_CSC0LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCB7E_SET_CSC0LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCB7E_SET_CSC0LUT_CONTROL_CURVE 6:5 +#define NVCB7E_SET_CSC0LUT_CONTROL_CURVE_CSCLUT_PQ (0x00000000) +#define NVCB7E_SET_CSC0LUT_CONTROL_CURVE_CSCLUT_HLG (0x00000001) +#define NVCB7E_SET_CSC0LUT_CONTROL_CURVE_CSCLUT_DIRECT (0x00000002) +#define NVCB7E_SET_CSC01CONTROL (0x000004BC) +#define NVCB7E_SET_CSC01CONTROL_ENABLE 0:0 +#define NVCB7E_SET_CSC01CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCB7E_SET_CSC01CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCB7E_SET_CSC01COEFFICIENT_C00 (0x000004C0) +#define NVCB7E_SET_CSC01COEFFICIENT_C00_VALUE 20:0 +#define NVCB7E_SET_CSC01COEFFICIENT_C01 (0x000004C4) +#define NVCB7E_SET_CSC01COEFFICIENT_C01_VALUE 20:0 +#define NVCB7E_SET_CSC01COEFFICIENT_C02 (0x000004C8) +#define NVCB7E_SET_CSC01COEFFICIENT_C02_VALUE 20:0 +#define NVCB7E_SET_CSC01COEFFICIENT_C03 (0x000004CC) +#define NVCB7E_SET_CSC01COEFFICIENT_C03_VALUE 20:0 +#define NVCB7E_SET_CSC01COEFFICIENT_C10 (0x000004D0) +#define NVCB7E_SET_CSC01COEFFICIENT_C10_VALUE 20:0 +#define NVCB7E_SET_CSC01COEFFICIENT_C11 (0x000004D4) +#define NVCB7E_SET_CSC01COEFFICIENT_C11_VALUE 20:0 +#define NVCB7E_SET_CSC01COEFFICIENT_C12 (0x000004D8) +#define NVCB7E_SET_CSC01COEFFICIENT_C12_VALUE 20:0 +#define NVCB7E_SET_CSC01COEFFICIENT_C13 (0x000004DC) +#define NVCB7E_SET_CSC01COEFFICIENT_C13_VALUE 20:0 +#define NVCB7E_SET_CSC01COEFFICIENT_C20 (0x000004E0) +#define NVCB7E_SET_CSC01COEFFICIENT_C20_VALUE 20:0 +#define NVCB7E_SET_CSC01COEFFICIENT_C21 (0x000004E4) +#define NVCB7E_SET_CSC01COEFFICIENT_C21_VALUE 20:0 +#define NVCB7E_SET_CSC01COEFFICIENT_C22 (0x000004E8) +#define NVCB7E_SET_CSC01COEFFICIENT_C22_VALUE 20:0 +#define NVCB7E_SET_CSC01COEFFICIENT_C23 (0x000004EC) +#define NVCB7E_SET_CSC01COEFFICIENT_C23_VALUE 20:0 +#define NVCB7E_SET_TMO_CONTROL (0x00000500) +#define NVCB7E_SET_TMO_CONTROL_INTERPOLATE 0:0 +#define NVCB7E_SET_TMO_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVCB7E_SET_TMO_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVCB7E_SET_TMO_CONTROL_SAT_MODE 3:2 +#define NVCB7E_SET_TMO_CONTROL_SIZE 18:8 +#define NVCB7E_SET_TMO_LOW_INTENSITY_ZONE (0x00000508) +#define NVCB7E_SET_TMO_LOW_INTENSITY_ZONE_END 29:16 +#define NVCB7E_SET_TMO_LOW_INTENSITY_VALUE (0x0000050C) +#define NVCB7E_SET_TMO_LOW_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVCB7E_SET_TMO_LOW_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVCB7E_SET_TMO_LOW_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVCB7E_SET_TMO_MEDIUM_INTENSITY_ZONE (0x00000510) +#define NVCB7E_SET_TMO_MEDIUM_INTENSITY_ZONE_START 13:0 +#define NVCB7E_SET_TMO_MEDIUM_INTENSITY_ZONE_END 29:16 +#define NVCB7E_SET_TMO_MEDIUM_INTENSITY_VALUE (0x00000514) +#define NVCB7E_SET_TMO_MEDIUM_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVCB7E_SET_TMO_MEDIUM_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVCB7E_SET_TMO_MEDIUM_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVCB7E_SET_TMO_HIGH_INTENSITY_ZONE (0x00000518) +#define NVCB7E_SET_TMO_HIGH_INTENSITY_ZONE_START 13:0 +#define NVCB7E_SET_TMO_HIGH_INTENSITY_VALUE (0x0000051C) +#define NVCB7E_SET_TMO_HIGH_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVCB7E_SET_TMO_HIGH_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVCB7E_SET_TMO_HIGH_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVCB7E_SET_CSC10CONTROL (0x0000053C) +#define NVCB7E_SET_CSC10CONTROL_ENABLE 0:0 +#define NVCB7E_SET_CSC10CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCB7E_SET_CSC10CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCB7E_SET_CSC10COEFFICIENT_C00 (0x00000540) +#define NVCB7E_SET_CSC10COEFFICIENT_C00_VALUE 20:0 +#define NVCB7E_SET_CSC10COEFFICIENT_C01 (0x00000544) +#define NVCB7E_SET_CSC10COEFFICIENT_C01_VALUE 20:0 +#define NVCB7E_SET_CSC10COEFFICIENT_C02 (0x00000548) +#define NVCB7E_SET_CSC10COEFFICIENT_C02_VALUE 20:0 +#define NVCB7E_SET_CSC10COEFFICIENT_C03 (0x0000054C) +#define NVCB7E_SET_CSC10COEFFICIENT_C03_VALUE 20:0 +#define NVCB7E_SET_CSC10COEFFICIENT_C10 (0x00000550) +#define NVCB7E_SET_CSC10COEFFICIENT_C10_VALUE 20:0 +#define NVCB7E_SET_CSC10COEFFICIENT_C11 (0x00000554) +#define NVCB7E_SET_CSC10COEFFICIENT_C11_VALUE 20:0 +#define NVCB7E_SET_CSC10COEFFICIENT_C12 (0x00000558) +#define NVCB7E_SET_CSC10COEFFICIENT_C12_VALUE 20:0 +#define NVCB7E_SET_CSC10COEFFICIENT_C13 (0x0000055C) +#define NVCB7E_SET_CSC10COEFFICIENT_C13_VALUE 20:0 +#define NVCB7E_SET_CSC10COEFFICIENT_C20 (0x00000560) +#define NVCB7E_SET_CSC10COEFFICIENT_C20_VALUE 20:0 +#define NVCB7E_SET_CSC10COEFFICIENT_C21 (0x00000564) +#define NVCB7E_SET_CSC10COEFFICIENT_C21_VALUE 20:0 +#define NVCB7E_SET_CSC10COEFFICIENT_C22 (0x00000568) +#define NVCB7E_SET_CSC10COEFFICIENT_C22_VALUE 20:0 +#define NVCB7E_SET_CSC10COEFFICIENT_C23 (0x0000056C) +#define NVCB7E_SET_CSC10COEFFICIENT_C23_VALUE 20:0 +#define NVCB7E_SET_CSC1LUT_FP_SCALE (0x00000570) +#define NVCB7E_SET_CSC1LUT_FP_SCALE_VALUE 15:0 +#define NVCB7E_SET_CSC1LUT_CONTROL (0x00000580) +#define NVCB7E_SET_CSC1LUT_CONTROL_INTERPOLATE 0:0 +#define NVCB7E_SET_CSC1LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVCB7E_SET_CSC1LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVCB7E_SET_CSC1LUT_CONTROL_MIRROR 1:1 +#define NVCB7E_SET_CSC1LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVCB7E_SET_CSC1LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVCB7E_SET_CSC1LUT_CONTROL_ENABLE 4:4 +#define NVCB7E_SET_CSC1LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCB7E_SET_CSC1LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCB7E_SET_CSC1LUT_CONTROL_CURVE 6:5 +#define NVCB7E_SET_CSC1LUT_CONTROL_CURVE_CSCLUT_PQ (0x00000000) +#define NVCB7E_SET_CSC1LUT_CONTROL_CURVE_CSCLUT_HLG (0x00000001) +#define NVCB7E_SET_CSC1LUT_CONTROL_CURVE_CSCLUT_DIRECT (0x00000002) +#define NVCB7E_SET_CSC11CONTROL (0x0000059C) +#define NVCB7E_SET_CSC11CONTROL_ENABLE 0:0 +#define NVCB7E_SET_CSC11CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCB7E_SET_CSC11CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCB7E_SET_CSC11CONTROL_LEVEL 7:2 +#define NVCB7E_SET_CSC11COEFFICIENT_C00 (0x000005A0) +#define NVCB7E_SET_CSC11COEFFICIENT_C00_VALUE 20:0 +#define NVCB7E_SET_CSC11COEFFICIENT_C01 (0x000005A4) +#define NVCB7E_SET_CSC11COEFFICIENT_C01_VALUE 20:0 +#define NVCB7E_SET_CSC11COEFFICIENT_C02 (0x000005A8) +#define NVCB7E_SET_CSC11COEFFICIENT_C02_VALUE 20:0 +#define NVCB7E_SET_CSC11COEFFICIENT_C03 (0x000005AC) +#define NVCB7E_SET_CSC11COEFFICIENT_C03_VALUE 20:0 +#define NVCB7E_SET_CSC11COEFFICIENT_C10 (0x000005B0) +#define NVCB7E_SET_CSC11COEFFICIENT_C10_VALUE 20:0 +#define NVCB7E_SET_CSC11COEFFICIENT_C11 (0x000005B4) +#define NVCB7E_SET_CSC11COEFFICIENT_C11_VALUE 20:0 +#define NVCB7E_SET_CSC11COEFFICIENT_C12 (0x000005B8) +#define NVCB7E_SET_CSC11COEFFICIENT_C12_VALUE 20:0 +#define NVCB7E_SET_CSC11COEFFICIENT_C13 (0x000005BC) +#define NVCB7E_SET_CSC11COEFFICIENT_C13_VALUE 20:0 +#define NVCB7E_SET_CSC11COEFFICIENT_C20 (0x000005C0) +#define NVCB7E_SET_CSC11COEFFICIENT_C20_VALUE 20:0 +#define NVCB7E_SET_CSC11COEFFICIENT_C21 (0x000005C4) +#define NVCB7E_SET_CSC11COEFFICIENT_C21_VALUE 20:0 +#define NVCB7E_SET_CSC11COEFFICIENT_C22 (0x000005C8) +#define NVCB7E_SET_CSC11COEFFICIENT_C22_VALUE 20:0 +#define NVCB7E_SET_CSC11COEFFICIENT_C23 (0x000005CC) +#define NVCB7E_SET_CSC11COEFFICIENT_C23_VALUE 20:0 +#define NVCB7E_SET_CLAMP_RANGE (0x000005D0) +#define NVCB7E_SET_CLAMP_RANGE_LOW 15:0 +#define NVCB7E_SET_CLAMP_RANGE_HIGH 31:16 +#define NVCB7E_SW_RESERVED(b) (0x000005D4 + (b)*0x00000004) +#define NVCB7E_SW_RESERVED_VALUE 31:0 +#define NVCB7E_SET_DIRTY_RECT_SIZE (0x000005E4) +#define NVCB7E_SET_DIRTY_RECT_SIZE_WIDTH 15:0 +#define NVCB7E_SET_DIRTY_RECT_SIZE_HEIGHT 31:16 +#define NVCB7E_SET_DIRTY_RECT_POSITION (0x000005E8) +#define NVCB7E_SET_DIRTY_RECT_POSITION_X 15:0 +#define NVCB7E_SET_DIRTY_RECT_POSITION_Y 31:16 +#define NVCB7E_SET_SUPERFRAME (0x000005EC) +#define NVCB7E_SET_SUPERFRAME_ENABLE 0:0 +#define NVCB7E_SET_SUPERFRAME_ENABLE_DISABLE (0x00000000) +#define NVCB7E_SET_SUPERFRAME_ENABLE_ENABLE (0x00000001) +#define NVCB7E_SET_SUPERFRAME_MODE 2:1 +#define NVCB7E_SET_SUPERFRAME_MODE_FIXED (0x00000000) +#define NVCB7E_SET_SUPERFRAME_MODE_DYNAMIC (0x00000001) +#define NVCB7E_SET_SUPERFRAME_MODE_SW (0x00000003) +#define NVCB7E_SET_SUPERFRAME_RATIO_IN 15:8 +#define NVCB7E_SET_SUPERFRAME_RATIO_OUT 23:16 +#define NVCB7E_SET_SUPERFRAME_START_COUNT 31:24 +#define NVCB7E_SET_INFOFRAME_CTRL(b) (0x000005F0 + (b)*0x00000004) +#define NVCB7E_SET_INFOFRAME_CTRL_ENABLE 0:0 +#define NVCB7E_SET_INFOFRAME_CTRL_ENABLE_DISABLE (0x00000000) +#define NVCB7E_SET_INFOFRAME_CTRL_ENABLE_ENABLE (0x00000001) +#define NVCB7E_SET_INFOFRAME_CTRL_LOCATION 5:4 +#define NVCB7E_SET_INFOFRAME_CTRL_LOCATION_VBLANK (0x00000000) +#define NVCB7E_SET_INFOFRAME_CTRL_LOCATION_VSYNC (0x00000001) +#define NVCB7E_SET_INFOFRAME_CTRL_LOCATION_LINE (0x00000002) +#define NVCB7E_SET_INFOFRAME_CTRL_LINE_ID 30:16 +#define NVCB7E_SET_INFOFRAME_CTRL_LINE_ID_REVERSED 31:31 +#define NVCB7E_SET_INFOFRAME_CTRL_LINE_ID_REVERSED_DISABLE (0x00000000) +#define NVCB7E_SET_INFOFRAME_CTRL_LINE_ID_REVERSED_ENABLE (0x00000001) +#define NVCB7E_SET_INFOFRAME_HEADER(b) (0x000005F8 + (b)*0x00000004) +#define NVCB7E_SET_INFOFRAME_HEADER_HB0 7:0 +#define NVCB7E_SET_INFOFRAME_HEADER_HB1 15:8 +#define NVCB7E_SET_INFOFRAME_HEADER_HB2 23:16 +#define NVCB7E_SET_INFOFRAME_HEADER_HB3 31:24 +#define NVCB7E_SET_INFOFRAME_DATA0(b) (0x00000600 + (b)*0x00000004) +#define NVCB7E_SET_INFOFRAME_DATA0_DB0 7:0 +#define NVCB7E_SET_INFOFRAME_DATA0_DB1 15:8 +#define NVCB7E_SET_INFOFRAME_DATA0_DB2 23:16 +#define NVCB7E_SET_INFOFRAME_DATA0_DB3 31:24 +#define NVCB7E_SET_INFOFRAME_DATA1(b) (0x00000608 + (b)*0x00000004) +#define NVCB7E_SET_INFOFRAME_DATA1_DB4 7:0 +#define NVCB7E_SET_INFOFRAME_DATA1_DB5 15:8 +#define NVCB7E_SET_INFOFRAME_DATA1_DB6 23:16 +#define NVCB7E_SET_INFOFRAME_DATA1_DB7 31:24 +#define NVCB7E_SET_INFOFRAME_DATA2(b) (0x00000610 + (b)*0x00000004) +#define NVCB7E_SET_INFOFRAME_DATA2_DB8 7:0 +#define NVCB7E_SET_INFOFRAME_DATA2_DB9 15:8 +#define NVCB7E_SET_INFOFRAME_DATA2_DB10 23:16 +#define NVCB7E_SET_INFOFRAME_DATA2_DB11 31:24 +#define NVCB7E_SET_INFOFRAME_DATA3(b) (0x00000618 + (b)*0x00000004) +#define NVCB7E_SET_INFOFRAME_DATA3_DB12 7:0 +#define NVCB7E_SET_INFOFRAME_DATA3_DB13 15:8 +#define NVCB7E_SET_INFOFRAME_DATA3_DB14 23:16 +#define NVCB7E_SET_INFOFRAME_DATA3_DB15 31:24 +#define NVCB7E_SET_INFOFRAME_DATA4(b) (0x00000620 + (b)*0x00000004) +#define NVCB7E_SET_INFOFRAME_DATA4_DB16 7:0 +#define NVCB7E_SET_INFOFRAME_DATA4_DB17 15:8 +#define NVCB7E_SET_INFOFRAME_DATA4_DB18 23:16 +#define NVCB7E_SET_INFOFRAME_DATA4_DB19 31:24 +#define NVCB7E_SET_INFOFRAME_DATA5(b) (0x00000628 + (b)*0x00000004) +#define NVCB7E_SET_INFOFRAME_DATA5_DB20 7:0 +#define NVCB7E_SET_INFOFRAME_DATA5_DB21 15:8 +#define NVCB7E_SET_INFOFRAME_DATA5_DB22 23:16 +#define NVCB7E_SET_INFOFRAME_DATA5_DB23 31:24 +#define NVCB7E_SET_INFOFRAME_DATA6(b) (0x00000630 + (b)*0x00000004) +#define NVCB7E_SET_INFOFRAME_DATA6_DB24 7:0 +#define NVCB7E_SET_INFOFRAME_DATA6_DB25 15:8 +#define NVCB7E_SET_INFOFRAME_DATA6_DB26 23:16 +#define NVCB7E_SET_INFOFRAME_DATA6_DB27 31:24 +#define NVCB7E_SET_INFOFRAME_DATA7(b) (0x00000638 + (b)*0x00000004) +#define NVCB7E_SET_INFOFRAME_DATA7_DB28 7:0 +#define NVCB7E_SET_INFOFRAME_DATA7_DB29 15:8 +#define NVCB7E_SET_INFOFRAME_DATA7_DB30 23:16 +#define NVCB7E_SET_INFOFRAME_DATA7_DB31 31:24 +#define NVCB7E_SET_SURFACE_ADDRESS_HI_SEMAPHORE (0x00000640) +#define NVCB7E_SET_SURFACE_ADDRESS_HI_SEMAPHORE_ADDRESS_HI 31:0 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE (0x00000644) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ADDRESS_LO 31:4 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET 3:2 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_IOVA (0x00000000) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE 0:0 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE_DISABLE (0x00000000) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE_ENABLE (0x00000001) +#define NVCB7E_SET_SURFACE_ADDRESS_HI_ACQ_SEMAPHORE (0x00000648) +#define NVCB7E_SET_SURFACE_ADDRESS_HI_ACQ_SEMAPHORE_ADDRESS_HI 31:0 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE (0x0000064C) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ADDRESS_LO 31:4 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET 3:2 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_IOVA (0x00000000) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE 0:0 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE_DISABLE (0x00000000) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE_ENABLE (0x00000001) +#define NVCB7E_SET_SURFACE_ADDRESS_HI_NOTIFIER (0x00000650) +#define NVCB7E_SET_SURFACE_ADDRESS_HI_NOTIFIER_ADDRESS_HI 31:0 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER (0x00000654) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ADDRESS_LO 31:4 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET 3:2 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_IOVA (0x00000000) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE 0:0 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_DISABLE (0x00000000) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_ENABLE (0x00000001) +#define NVCB7E_SET_SURFACE_ADDRESS_HI_ISO(b) (0x00000658 + (b)*0x00000004) +#define NVCB7E_SET_SURFACE_ADDRESS_HI_ISO_ADDRESS_HI 31:0 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO(b) (0x00000670 + (b)*0x00000004) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_ADDRESS_LO 31:4 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET 3:2 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_IOVA (0x00000000) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_KIND 1:1 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_KIND_PITCH (0x00000000) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_KIND_BLOCKLINEAR (0x00000001) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE 0:0 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE_DISABLE (0x00000000) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE_ENABLE (0x00000001) +#define NVCB7E_SET_SURFACE_ADDRESS_HI_ILUT (0x00000688) +#define NVCB7E_SET_SURFACE_ADDRESS_HI_ILUT_ADDRESS_HI 31:0 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT (0x0000068C) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_ADDRESS_LO 31:4 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET 3:2 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_IOVA (0x00000000) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE 0:0 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE_DISABLE (0x00000000) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE_ENABLE (0x00000001) +#define NVCB7E_SET_SURFACE_ADDRESS_HI_TMO_LUT (0x00000690) +#define NVCB7E_SET_SURFACE_ADDRESS_HI_TMO_LUT_ADDRESS_HI 31:0 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT (0x00000694) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ADDRESS_LO 31:4 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET 3:2 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_IOVA (0x00000000) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE 0:0 +#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE_DISABLE (0x00000000) +#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE_ENABLE (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clcb7e_h diff --git a/userspace/sdks/nv570/inc/class/clcb97.h b/userspace/sdks/nv570/inc/class/clcb97.h new file mode 100644 index 0000000..7528a2d --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcb97.h @@ -0,0 +1,4480 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_hopper_a_h_ +#define _cl_hopper_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl hopper_a */ + +#include "nvtypes.h" + +#define HOPPER_A 0xCB97 + +#define NVCB97_SET_OBJECT 0x0000 +#define NVCB97_SET_OBJECT_CLASS_ID 15:0 +#define NVCB97_SET_OBJECT_ENGINE_ID 20:16 + +#define NVCB97_NO_OPERATION 0x0100 +#define NVCB97_NO_OPERATION_V 31:0 + +#define NVCB97_SET_NOTIFY_A 0x0104 +#define NVCB97_SET_NOTIFY_A_ADDRESS_UPPER 24:0 + +#define NVCB97_SET_NOTIFY_B 0x0108 +#define NVCB97_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVCB97_NOTIFY 0x010c +#define NVCB97_NOTIFY_TYPE 31:0 +#define NVCB97_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVCB97_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVCB97_WAIT_FOR_IDLE 0x0110 +#define NVCB97_WAIT_FOR_IDLE_V 31:0 + +#define NVCB97_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVCB97_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVCB97_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVCB97_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVCB97_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVCB97_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVCB97_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVCB97_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVCB97_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVCB97_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVCB97_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVCB97_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVCB97_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVCB97_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVCB97_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVCB97_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVCB97_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVCB97_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVCB97_SEND_GO_IDLE 0x013c +#define NVCB97_SEND_GO_IDLE_V 31:0 + +#define NVCB97_PM_TRIGGER 0x0140 +#define NVCB97_PM_TRIGGER_V 31:0 + +#define NVCB97_PM_TRIGGER_WFI 0x0144 +#define NVCB97_PM_TRIGGER_WFI_V 31:0 + +#define NVCB97_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVCB97_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVCB97_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVCB97_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVCB97_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVCB97_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVCB97_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVCB97_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER 0x0158 +#define NVCB97_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER_PAYLOAD_LOWER 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER 0x015c +#define NVCB97_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD_UPPER 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_ADDRESS_LOWER 0x0160 +#define NVCB97_SET_REPORT_SEMAPHORE_ADDRESS_LOWER_LOWER 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_ADDRESS_UPPER 0x0164 +#define NVCB97_SET_REPORT_SEMAPHORE_ADDRESS_UPPER_UPPER 24:0 + +#define NVCB97_REPORT_SEMAPHORE_EXECUTE 0x0168 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_OPERATION 1:0 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_OPERATION_RELEASE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_OPERATION_ACQUIRE 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_OPERATION_REPORT_ONLY 0x00000002 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_OPERATION_TRAP 0x00000003 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION 5:2 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_NONE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_VPC 0x00000004 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_ALL 0x0000000F +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE 6:6 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT 11:7 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_NONE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_VS_INVOCATIONS 0x00000005 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_TI_INVOCATIONS 0x0000001B +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_TS_INVOCATIONS 0x0000001D +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_GS_INVOCATIONS 0x00000007 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_SCG_CLOCKS 0x00000008 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS0 0x0000000A +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS1 0x0000000C +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS2 0x0000000E +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS3 0x00000010 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_PS_INVOCATIONS 0x00000013 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_TIMESTAMP 0x00000014 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE 14:13 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_SUB_REPORT 17:15 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE 19:19 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_FALSE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_TRUE 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE 18:18 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE_FALSE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE_TRUE 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE 20:20 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP 23:21 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_ADD 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MIN 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MAX 0x00000002 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_INC 0x00000003 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_DEC 0x00000004 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_AND 0x00000005 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_OR 0x00000006 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_XOR 0x00000007 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT 25:24 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64 27:27 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_FALSE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_TRUE 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE 29:28 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_NONE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 + +#define NVCB97_LINE_LENGTH_IN 0x0180 +#define NVCB97_LINE_LENGTH_IN_VALUE 31:0 + +#define NVCB97_LINE_COUNT 0x0184 +#define NVCB97_LINE_COUNT_VALUE 31:0 + +#define NVCB97_OFFSET_OUT_UPPER 0x0188 +#define NVCB97_OFFSET_OUT_UPPER_VALUE 24:0 + +#define NVCB97_OFFSET_OUT 0x018c +#define NVCB97_OFFSET_OUT_VALUE 31:0 + +#define NVCB97_PITCH_OUT 0x0190 +#define NVCB97_PITCH_OUT_VALUE 31:0 + +#define NVCB97_SET_DST_BLOCK_SIZE 0x0194 +#define NVCB97_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVCB97_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVCB97_SET_DST_WIDTH 0x0198 +#define NVCB97_SET_DST_WIDTH_V 31:0 + +#define NVCB97_SET_DST_HEIGHT 0x019c +#define NVCB97_SET_DST_HEIGHT_V 31:0 + +#define NVCB97_SET_DST_DEPTH 0x01a0 +#define NVCB97_SET_DST_DEPTH_V 31:0 + +#define NVCB97_SET_DST_LAYER 0x01a4 +#define NVCB97_SET_DST_LAYER_V 31:0 + +#define NVCB97_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVCB97_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVCB97_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVCB97_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVCB97_LAUNCH_DMA 0x01b0 +#define NVCB97_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVCB97_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVCB97_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVCB97_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVCB97_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVCB97_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVCB97_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVCB97_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVCB97_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVCB97_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVCB97_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVCB97_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVCB97_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVCB97_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVCB97_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVCB97_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVCB97_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVCB97_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVCB97_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVCB97_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVCB97_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVCB97_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVCB97_LOAD_INLINE_DATA 0x01b4 +#define NVCB97_LOAD_INLINE_DATA_V 31:0 + +#define NVCB97_SET_I2M_SEMAPHORE_A 0x01dc +#define NVCB97_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 24:0 + +#define NVCB97_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVCB97_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVCB97_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVCB97_SET_MME_SWITCH_STATE 0x01ec +#define NVCB97_SET_MME_SWITCH_STATE_VALID 0:0 +#define NVCB97_SET_MME_SWITCH_STATE_VALID_FALSE 0x00000000 +#define NVCB97_SET_MME_SWITCH_STATE_VALID_TRUE 0x00000001 +#define NVCB97_SET_MME_SWITCH_STATE_SAVE_MACRO 11:4 +#define NVCB97_SET_MME_SWITCH_STATE_RESTORE_MACRO 19:12 + +#define NVCB97_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVCB97_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVCB97_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVCB97_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVCB97_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVCB97_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVCB97_SET_I2M_SPARE_NOOP03 0x01fc +#define NVCB97_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVCB97_RUN_DS_NOW 0x0200 +#define NVCB97_RUN_DS_NOW_V 31:0 + +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVCB97_SET_GS_MODE 0x0208 +#define NVCB97_SET_GS_MODE_TYPE 0:0 +#define NVCB97_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVCB97_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVCB97_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVCB97_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVCB97_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVCB97_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVCB97_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_GS_DM_FIFO 0x0214 +#define NVCB97_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVCB97_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVCB97_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVCB97_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVCB97_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVCB97_INVALIDATE_SHADER_CACHES 0x021c +#define NVCB97_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVCB97_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVCB97_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVCB97_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVCB97_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVCB97_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVCB97_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVCB97_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVCB97_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVCB97_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVCB97_SET_INSTANCE_COUNT 0x0220 +#define NVCB97_SET_INSTANCE_COUNT_V 31:0 + +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_GO_IDLE_TIMEOUT 0x022c +#define NVCB97_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVCB97_SET_MME_VERSION 0x0234 +#define NVCB97_SET_MME_VERSION_MAJOR 7:0 + +#define NVCB97_SET_INDEX_BUFFER_SIZE_A 0x0238 +#define NVCB97_SET_INDEX_BUFFER_SIZE_A_UPPER 7:0 + +#define NVCB97_SET_INDEX_BUFFER_SIZE_B 0x023c +#define NVCB97_SET_INDEX_BUFFER_SIZE_B_LOWER 31:0 + +#define NVCB97_SET_ROOT_TABLE_VISIBILITY(i) (0x0240+(i)*4) +#define NVCB97_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP0_ENABLE 1:0 +#define NVCB97_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP1_ENABLE 5:4 +#define NVCB97_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP2_ENABLE 9:8 +#define NVCB97_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP3_ENABLE 13:12 +#define NVCB97_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP4_ENABLE 17:16 + +#define NVCB97_SET_DRAW_CONTROL_A 0x0260 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY 3:0 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_LINES 0x00000001 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_PATCH 0x0000000E +#define NVCB97_SET_DRAW_CONTROL_A_PRIMITIVE_ID 4:4 +#define NVCB97_SET_DRAW_CONTROL_A_PRIMITIVE_ID_FIRST 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ID 6:5 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ID_FIRST 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVCB97_SET_DRAW_CONTROL_A_SPLIT_MODE 8:7 +#define NVCB97_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVCB97_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVCB97_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE 9:9 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX 10:10 +#define NVCB97_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_FALSE 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_TRUE 0x00000001 +#define NVCB97_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX 11:11 +#define NVCB97_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_FALSE 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_TRUE 0x00000001 + +#define NVCB97_SET_DRAW_CONTROL_B 0x0264 +#define NVCB97_SET_DRAW_CONTROL_B_INSTANCE_COUNT 31:0 + +#define NVCB97_DRAW_INDEX_BUFFER_BEGIN_END_A 0x0268 +#define NVCB97_DRAW_INDEX_BUFFER_BEGIN_END_A_FIRST 31:0 + +#define NVCB97_DRAW_INDEX_BUFFER_BEGIN_END_B 0x026c +#define NVCB97_DRAW_INDEX_BUFFER_BEGIN_END_B_COUNT 31:0 + +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_A 0x0270 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_A_START 31:0 + +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_B 0x0274 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_B_COUNT 31:0 + +#define NVCB97_INVALIDATE_RASTER_CACHE_NO_WFI 0x027c +#define NVCB97_INVALIDATE_RASTER_CACHE_NO_WFI_V 0:0 + +#define NVCB97_SET_COLOR_RENDER_TO_ZETA_SURFACE 0x02b8 +#define NVCB97_SET_COLOR_RENDER_TO_ZETA_SURFACE_V 0:0 +#define NVCB97_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_FALSE 0x00000000 +#define NVCB97_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_TRUE 0x00000001 + +#define NVCB97_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION 0x02bc +#define NVCB97_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V 0:0 +#define NVCB97_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_TRUE 0x00000001 + +#define NVCB97_INCREMENT_SYNC_POINT 0x02c8 +#define NVCB97_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVCB97_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVCB97_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVCB97_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVCB97_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVCB97_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVCB97_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVCB97_SET_ROOT_TABLE_PREFETCH 0x02d0 +#define NVCB97_SET_ROOT_TABLE_PREFETCH_STAGE_ENABLES 5:0 + +#define NVCB97_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVCB97_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVCB97_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVCB97_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVCB97_DECOMPRESS_SURFACE 0x02e0 +#define NVCB97_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVCB97_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVCB97_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVCB97_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVCB97_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVCB97_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVCB97_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVCB97_SET_ZCULL_SUBREGION 0x02e8 +#define NVCB97_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVCB97_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVCB97_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVCB97_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVCB97_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVCB97_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVCB97_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVCB97_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVCB97_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVCB97_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVCB97_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVCB97_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVCB97_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVCB97_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVCB97_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVCB97_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVCB97_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVCB97_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVCB97_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVCB97_DRAW_ZERO_INDEX 0x0304 +#define NVCB97_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVCB97_SET_L1_CONFIGURATION 0x0308 +#define NVCB97_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVCB97_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVCB97_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVCB97_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVCB97_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVCB97_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVCB97_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVCB97_SET_SPA_VERSION 0x0310 +#define NVCB97_SET_SPA_VERSION_MINOR 7:0 +#define NVCB97_SET_SPA_VERSION_MAJOR 15:8 + +#define NVCB97_SET_TIMESLICE_BATCH_LIMIT 0x0314 +#define NVCB97_SET_TIMESLICE_BATCH_LIMIT_BATCH_LIMIT 15:0 + +#define NVCB97_SET_SNAP_GRID_LINE 0x0318 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVCB97_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVCB97_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVCB97_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVCB97_SET_SNAP_GRID_NON_LINE 0x031c +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVCB97_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVCB97_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVCB97_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVCB97_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVCB97_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVCB97_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVCB97_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVCB97_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVCB97_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVCB97_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVCB97_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVCB97_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVCB97_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVCB97_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVCB97_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVCB97_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVCB97_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVCB97_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVCB97_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVCB97_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVCB97_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVCB97_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVCB97_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVCB97_SET_TESSELLATION_LOD_V1 0x0330 +#define NVCB97_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVCB97_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVCB97_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVCB97_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVCB97_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVCB97_RESERVED_TG07 0x033c +#define NVCB97_RESERVED_TG07_V 0:0 + +#define NVCB97_RESERVED_TG08 0x0340 +#define NVCB97_RESERVED_TG08_V 0:0 + +#define NVCB97_RESERVED_TG09 0x0344 +#define NVCB97_RESERVED_TG09_V 0:0 + +#define NVCB97_RESERVED_TG10 0x0348 +#define NVCB97_RESERVED_TG10_V 0:0 + +#define NVCB97_RESERVED_TG11 0x034c +#define NVCB97_RESERVED_TG11_V 0:0 + +#define NVCB97_RESERVED_TG12 0x0350 +#define NVCB97_RESERVED_TG12_V 0:0 + +#define NVCB97_RESERVED_TG13 0x0354 +#define NVCB97_RESERVED_TG13_V 0:0 + +#define NVCB97_RESERVED_TG14 0x0358 +#define NVCB97_RESERVED_TG14_V 0:0 + +#define NVCB97_RESERVED_TG15 0x035c +#define NVCB97_RESERVED_TG15_V 0:0 + +#define NVCB97_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVCB97_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVCB97_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVCB97_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVCB97_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVCB97_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVCB97_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVCB97_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVCB97_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVCB97_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVCB97_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVCB97_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVCB97_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVCB97_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVCB97_SET_RASTER_ENABLE 0x037c +#define NVCB97_SET_RASTER_ENABLE_V 0:0 +#define NVCB97_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVCB97_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVCB97_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVCB97_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVCB97_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVCB97_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVCB97_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVCB97_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVCB97_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVCB97_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVCB97_SET_Z_ROP_SLICE_MAP 0x0500 +#define NVCB97_SET_Z_ROP_SLICE_MAP_VIRTUAL_ADDRESS_MASK 31:0 + +#define NVCB97_SET_ROOT_TABLE_SELECTOR 0x0504 +#define NVCB97_SET_ROOT_TABLE_SELECTOR_ROOT_TABLE 2:0 +#define NVCB97_SET_ROOT_TABLE_SELECTOR_OFFSET 15:8 + +#define NVCB97_LOAD_ROOT_TABLE 0x0508 +#define NVCB97_LOAD_ROOT_TABLE_V 31:0 + +#define NVCB97_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVCB97_SET_MME_MEM_ADDRESS_A_UPPER 24:0 + +#define NVCB97_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVCB97_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVCB97_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVCB97_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVCB97_MME_DMA_READ 0x055c +#define NVCB97_MME_DMA_READ_LENGTH 31:0 + +#define NVCB97_MME_DMA_READ_FIFOED 0x0560 +#define NVCB97_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVCB97_MME_DMA_WRITE 0x0564 +#define NVCB97_MME_DMA_WRITE_LENGTH 31:0 + +#define NVCB97_MME_DMA_REDUCTION 0x0568 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVCB97_MME_DMA_SYSMEMBAR 0x056c +#define NVCB97_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVCB97_MME_DMA_SYNC 0x0570 +#define NVCB97_MME_DMA_SYNC_VALUE 31:0 + +#define NVCB97_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NVCB97_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NVCB97_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NVCB97_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NVCB97_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NVCB97_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NVCB97_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NVCB97_SET_VERTEX_STREAM_SIZE_A(j) (0x0600+(j)*8) +#define NVCB97_SET_VERTEX_STREAM_SIZE_A_UPPER 7:0 + +#define NVCB97_SET_VERTEX_STREAM_SIZE_B(j) (0x0604+(j)*8) +#define NVCB97_SET_VERTEX_STREAM_SIZE_B_LOWER 31:0 + +#define NVCB97_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVCB97_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVCB97_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVCB97_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVCB97_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVCB97_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVCB97_SET_RASTER_INPUT 0x0740 +#define NVCB97_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVCB97_SET_STREAM_OUTPUT 0x0744 +#define NVCB97_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVCB97_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVCB97_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVCB97_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVCB97_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVCB97_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVCB97_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVCB97_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVCB97_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVCB97_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVCB97_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVCB97_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVCB97_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 6:0 + +#define NVCB97_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVCB97_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVCB97_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVCB97_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVCB97_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVCB97_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVCB97_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVCB97_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVCB97_SET_TEXTURE_HEADER_VERSION 0x07ac +#define NVCB97_SET_TEXTURE_HEADER_VERSION_MAJOR 7:0 + +#define NVCB97_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVCB97_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVCB97_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVCB97_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVCB97_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVCB97_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVCB97_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVCB97_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVCB97_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVCB97_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVCB97_SET_CULL_BEFORE_FETCH 0x07dc +#define NVCB97_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVCB97_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVCB97_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVCB97_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVCB97_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVCB97_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVCB97_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVCB97_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVCB97_SET_ZCULL_STORAGE_A 0x07e8 +#define NVCB97_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_ZCULL_STORAGE_B 0x07ec +#define NVCB97_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_ZCULL_STORAGE_C 0x07f0 +#define NVCB97_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_ZCULL_STORAGE_D 0x07f4 +#define NVCB97_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_ZT_READ_ONLY 0x07f8 +#define NVCB97_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVCB97_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVCB97_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVCB97_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVCB97_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVCB97_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVCB97_THROTTLE_SM 0x07fc +#define NVCB97_THROTTLE_SM_MULTIPLY_ADD 0:0 +#define NVCB97_THROTTLE_SM_MULTIPLY_ADD_FALSE 0x00000000 +#define NVCB97_THROTTLE_SM_MULTIPLY_ADD_TRUE 0x00000001 + +#define NVCB97_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVCB97_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVCB97_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVCB97_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVCB97_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVCB97_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVCB97_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVCB97_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVCB97_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVCB97_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVCB97_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVCB97_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVCB97_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVCB97_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVCB97_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVCB97_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVCB97_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVCB97_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVCB97_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVCB97_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVCB97_SET_COLOR_TARGET_C_ROP_SLICE_MAP(j) (0x0824+(j)*64) +#define NVCB97_SET_COLOR_TARGET_C_ROP_SLICE_MAP_VIRTUAL_ADDRESS_MASK 31:0 + +#define NVCB97_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVCB97_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVCB97_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVCB97_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVCB97_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVCB97_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVCB97_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVCB97_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVCB97_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVCB97_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVCB97_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVCB97_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVCB97_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVCB97_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVCB97_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVCB97_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVCB97_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVCB97_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVCB97_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVCB97_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVCB97_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVCB97_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVCB97_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVCB97_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVCB97_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVCB97_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVCB97_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVCB97_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVCB97_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVCB97_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVCB97_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVCB97_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVCB97_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVCB97_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVCB97_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVCB97_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVCB97_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVCB97_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVCB97_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVCB97_SET_STATISTICS_COUNTER 0x0d68 +#define NVCB97_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVCB97_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVCB97_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVCB97_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVCB97_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVCB97_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVCB97_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVCB97_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVCB97_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVCB97_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVCB97_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVCB97_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVCB97_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVCB97_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVCB97_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVCB97_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVCB97_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVCB97_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVCB97_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVCB97_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVCB97_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVCB97_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVCB97_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVCB97_SET_VERTEX_ARRAY_START 0x0d74 +#define NVCB97_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVCB97_DRAW_VERTEX_ARRAY 0x0d78 +#define NVCB97_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVCB97_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVCB97_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVCB97_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVCB97_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVCB97_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVCB97_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVCB97_SET_Z_CLEAR_VALUE 0x0d90 +#define NVCB97_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVCB97_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVCB97_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVCB97_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVCB97_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVCB97_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVCB97_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVCB97_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVCB97_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVCB97_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVCB97_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVCB97_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVCB97_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVCB97_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVCB97_SET_FRONT_POLYGON_MODE 0x0dac +#define NVCB97_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVCB97_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVCB97_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVCB97_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVCB97_SET_BACK_POLYGON_MODE 0x0db0 +#define NVCB97_SET_BACK_POLYGON_MODE_V 31:0 +#define NVCB97_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVCB97_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVCB97_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVCB97_SET_POLY_SMOOTH 0x0db4 +#define NVCB97_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVCB97_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVCB97_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVCB97_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVCB97_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVCB97_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVCB97_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVCB97_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVCB97_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_PATCH 0x0dcc +#define NVCB97_SET_PATCH_SIZE 7:0 + +#define NVCB97_SET_ITERATED_BLEND 0x0dd0 +#define NVCB97_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVCB97_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVCB97_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVCB97_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVCB97_SET_ZCULL_CRITERION 0x0dd8 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVCB97_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVCB97_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVCB97_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_CRITERION_SREF 23:16 +#define NVCB97_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVCB97_PIXEL_SHADER_BARRIER 0x0de0 +#define NVCB97_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVCB97_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVCB97_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 +#define NVCB97_PIXEL_SHADER_BARRIER_BARRIER_LOCATION 1:1 +#define NVCB97_PIXEL_SHADER_BARRIER_BARRIER_LOCATION_BLOCK_BEFORE_PS 0x00000000 +#define NVCB97_PIXEL_SHADER_BARRIER_BARRIER_LOCATION_BLOCK_BEFORE_PS_AND_ZTEST 0x00000001 + +#define NVCB97_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVCB97_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVCB97_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVCB97_MME_DMA_WRITE_METHOD_BARRIER 0x0dec +#define NVCB97_MME_DMA_WRITE_METHOD_BARRIER_V 0:0 + +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVCB97_SET_WINDOW_OFFSET_X 0x0df8 +#define NVCB97_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVCB97_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVCB97_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVCB97_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVCB97_SET_SCISSOR_ENABLE_V 0:0 +#define NVCB97_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVCB97_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVCB97_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVCB97_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVCB97_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVCB97_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVCB97_SET_VPC_PERF_KNOB 0x0f14 +#define NVCB97_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVCB97_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVCB97_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVCB97_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVCB97_PM_LOCAL_TRIGGER 0x0f18 +#define NVCB97_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVCB97_SET_POST_Z_PS_IMASK 0x0f1c +#define NVCB97_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVCB97_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVCB97_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVCB97_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVCB97_SET_BACK_STENCIL_MASK 0x0f58 +#define NVCB97_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVCB97_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVCB97_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVCB97_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVCB97_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVCB97_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVCB97_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVCB97_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVCB97_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVCB97_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVCB97_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVCB97_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVCB97_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVCB97_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVCB97_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVCB97_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVCB97_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVCB97_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVCB97_SET_SAMPLE_MASK 0x0fa4 +#define NVCB97_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVCB97_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVCB97_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVCB97_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVCB97_SET_CT_MRT_ENABLE 0x0fac +#define NVCB97_SET_CT_MRT_ENABLE_V 0:0 +#define NVCB97_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVCB97_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVCB97_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVCB97_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVCB97_SET_TIR 0x0fb4 +#define NVCB97_SET_TIR_MODE 1:0 +#define NVCB97_SET_TIR_MODE_DISABLED 0x00000000 +#define NVCB97_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVCB97_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVCB97_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVCB97_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVCB97_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVCB97_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVCB97_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVCB97_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVCB97_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVCB97_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVCB97_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVCB97_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVCB97_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVCB97_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVCB97_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVCB97_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVCB97_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVCB97_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVCB97_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_TIR_MODULATION 0x0fd4 +#define NVCB97_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVCB97_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVCB97_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVCB97_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVCB97_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVCB97_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVCB97_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVCB97_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVCB97_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVCB97_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVCB97_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVCB97_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVCB97_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVCB97_SET_ZT_A 0x0fe0 +#define NVCB97_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_ZT_B 0x0fe4 +#define NVCB97_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_ZT_FORMAT 0x0fe8 +#define NVCB97_SET_ZT_FORMAT_V 4:0 +#define NVCB97_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVCB97_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVCB97_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVCB97_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVCB97_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVCB97_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVCB97_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 + +#define NVCB97_SET_ZT_BLOCK_SIZE 0x0fec +#define NVCB97_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVCB97_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVCB97_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVCB97_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVCB97_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVCB97_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVCB97_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVCB97_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVCB97_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVCB97_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVCB97_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVCB97_SET_VIEWPORT_MULTICAST 0x1004 +#define NVCB97_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVCB97_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVCB97_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVCB97_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVCB97_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVCB97_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVCB97_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVCB97_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVCB97_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVCB97_SET_RESERVED_SW_METHOD00 0x1014 +#define NVCB97_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVCB97_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVCB97_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVCB97_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVCB97_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVCB97_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVCB97_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVCB97_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVCB97_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVCB97_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_RESERVED_SW_METHOD01 0x1028 +#define NVCB97_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD02 0x102c +#define NVCB97_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVCB97_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVCB97_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVCB97_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVCB97_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVCB97_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVCB97_SET_SPARE_NOOP01 0x1044 +#define NVCB97_SET_SPARE_NOOP01_V 31:0 + +#define NVCB97_SET_SPARE_NOOP02 0x1048 +#define NVCB97_SET_SPARE_NOOP02_V 31:0 + +#define NVCB97_SET_SPARE_NOOP03 0x104c +#define NVCB97_SET_SPARE_NOOP03_V 31:0 + +#define NVCB97_SET_SPARE_NOOP04 0x1050 +#define NVCB97_SET_SPARE_NOOP04_V 31:0 + +#define NVCB97_SET_SPARE_NOOP05 0x1054 +#define NVCB97_SET_SPARE_NOOP05_V 31:0 + +#define NVCB97_SET_SPARE_NOOP06 0x1058 +#define NVCB97_SET_SPARE_NOOP06_V 31:0 + +#define NVCB97_SET_SPARE_NOOP07 0x105c +#define NVCB97_SET_SPARE_NOOP07_V 31:0 + +#define NVCB97_SET_SPARE_NOOP08 0x1060 +#define NVCB97_SET_SPARE_NOOP08_V 31:0 + +#define NVCB97_SET_SPARE_NOOP09 0x1064 +#define NVCB97_SET_SPARE_NOOP09_V 31:0 + +#define NVCB97_SET_SPARE_NOOP10 0x1068 +#define NVCB97_SET_SPARE_NOOP10_V 31:0 + +#define NVCB97_SET_SPARE_NOOP11 0x106c +#define NVCB97_SET_SPARE_NOOP11_V 31:0 + +#define NVCB97_SET_SPARE_NOOP12 0x1070 +#define NVCB97_SET_SPARE_NOOP12_V 31:0 + +#define NVCB97_SET_SPARE_NOOP13 0x1074 +#define NVCB97_SET_SPARE_NOOP13_V 31:0 + +#define NVCB97_SET_SPARE_NOOP14 0x1078 +#define NVCB97_SET_SPARE_NOOP14_V 31:0 + +#define NVCB97_SET_SPARE_NOOP15 0x107c +#define NVCB97_SET_SPARE_NOOP15_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVCB97_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVCB97_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVCB97_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD06 0x10bc +#define NVCB97_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVCB97_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVCB97_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVCB97_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVCB97_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVCB97_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVCB97_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVCB97_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD13 0x10dc +#define NVCB97_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVCB97_UNBIND_ALL 0x10f4 +#define NVCB97_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVCB97_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVCB97_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVCB97_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVCB97_SET_RESERVED_SW_METHOD14 0x1100 +#define NVCB97_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD15 0x1104 +#define NVCB97_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVCB97_NO_OPERATION_DATA_HI 0x110c +#define NVCB97_NO_OPERATION_DATA_HI_V 31:0 + +#define NVCB97_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVCB97_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVCB97_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVCB97_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVCB97_PM_TRIGGER_END 0x1114 +#define NVCB97_PM_TRIGGER_END_V 31:0 + +#define NVCB97_SET_VERTEX_ID_BASE 0x1118 +#define NVCB97_SET_VERTEX_ID_BASE_V 31:0 + +#define NVCB97_SET_STENCIL_COMPRESSION 0x111c +#define NVCB97_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVCB97_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVCB97_SET_TIR_CONTROL 0x1130 +#define NVCB97_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVCB97_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVCB97_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVCB97_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVCB97_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVCB97_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVCB97_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVCB97_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVCB97_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 +#define NVCB97_SET_TIR_CONTROL_REDUCTION_MODE 2:2 +#define NVCB97_SET_TIR_CONTROL_REDUCTION_MODE_AFFINITY_MAP 0x00000000 +#define NVCB97_SET_TIR_CONTROL_REDUCTION_MODE_TRUNCATION 0x00000001 + +#define NVCB97_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVCB97_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVCB97_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVCB97_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVCB97_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVCB97_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVCB97_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVCB97_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVCB97_SET_FILL_VIA_TRIANGLE 0x113c +#define NVCB97_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVCB97_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVCB97_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVCB97_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVCB97_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVCB97_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVCB97_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVCB97_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVCB97_FLUSH_PENDING_WRITES 0x1144 +#define NVCB97_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVCB97_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVCB97_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVCB97_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVCB97_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVCB97_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVCB97_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVCB97_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVCB97_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVCB97_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVCB97_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVCB97_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVCB97_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVCB97_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVCB97_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVCB97_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVCB97_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVCB97_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVCB97_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_SCREEN_STATE_MASK 0x1204 +#define NVCB97_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVCB97_SET_ZT_SPARSE 0x1208 +#define NVCB97_SET_ZT_SPARSE_ENABLE 0:0 +#define NVCB97_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVCB97_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVCB97_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_SET_CT_SELECT 0x121c +#define NVCB97_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVCB97_SET_CT_SELECT_TARGET0 6:4 +#define NVCB97_SET_CT_SELECT_TARGET1 9:7 +#define NVCB97_SET_CT_SELECT_TARGET2 12:10 +#define NVCB97_SET_CT_SELECT_TARGET3 15:13 +#define NVCB97_SET_CT_SELECT_TARGET4 18:16 +#define NVCB97_SET_CT_SELECT_TARGET5 21:19 +#define NVCB97_SET_CT_SELECT_TARGET6 24:22 +#define NVCB97_SET_CT_SELECT_TARGET7 27:25 + +#define NVCB97_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVCB97_SET_ZT_SIZE_A 0x1228 +#define NVCB97_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVCB97_SET_ZT_SIZE_B 0x122c +#define NVCB97_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVCB97_SET_ZT_SIZE_C 0x1230 +#define NVCB97_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVCB97_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVCB97_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVCB97_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVCB97_SET_SAMPLER_BINDING 0x1234 +#define NVCB97_SET_SAMPLER_BINDING_V 0:0 +#define NVCB97_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVCB97_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVCB97_DRAW_AUTO 0x123c +#define NVCB97_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVCB97_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVCB97_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVCB97_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVCB97_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVCB97_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVCB97_SET_BACK_END_COPY_A 0x1264 +#define NVCB97_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVCB97_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVCB97_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVCB97_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BACK_END_COPY_B 0x1268 +#define NVCB97_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_BACK_END_COPY_C 0x126c +#define NVCB97_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_BACK_END_COPY_D 0x1270 +#define NVCB97_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_BACK_END_COPY_E 0x1274 +#define NVCB97_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVCB97_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVCB97_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVCB97_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVCB97_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVCB97_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVCB97_CLEAR_ZCULL_REGION 0x12c8 +#define NVCB97_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVCB97_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVCB97_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVCB97_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVCB97_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVCB97_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVCB97_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVCB97_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVCB97_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVCB97_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVCB97_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVCB97_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVCB97_SET_DEPTH_TEST 0x12cc +#define NVCB97_SET_DEPTH_TEST_ENABLE 0:0 +#define NVCB97_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_FILL_MODE 0x12d0 +#define NVCB97_SET_FILL_MODE_V 31:0 +#define NVCB97_SET_FILL_MODE_V_POINT 0x00000001 +#define NVCB97_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVCB97_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVCB97_SET_SHADE_MODE 0x12d4 +#define NVCB97_SET_SHADE_MODE_V 31:0 +#define NVCB97_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVCB97_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVCB97_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVCB97_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVCB97_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVCB97_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVCB97_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVCB97_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVCB97_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVCB97_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVCB97_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVCB97_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_DEPTH_WRITE 0x12e8 +#define NVCB97_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVCB97_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_ALPHA_TEST 0x12ec +#define NVCB97_SET_ALPHA_TEST_ENABLE 0:0 +#define NVCB97_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVCB97_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVCB97_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVCB97_DRAW_INLINE_INDEX4X8 0x1304 +#define NVCB97_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVCB97_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVCB97_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVCB97_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVCB97_D3D_SET_CULL_MODE 0x1308 +#define NVCB97_D3D_SET_CULL_MODE_V 31:0 +#define NVCB97_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVCB97_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVCB97_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVCB97_SET_DEPTH_FUNC 0x130c +#define NVCB97_SET_DEPTH_FUNC_V 31:0 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVCB97_SET_ALPHA_REF 0x1310 +#define NVCB97_SET_ALPHA_REF_V 31:0 + +#define NVCB97_SET_ALPHA_FUNC 0x1314 +#define NVCB97_SET_ALPHA_FUNC_V 31:0 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVCB97_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVCB97_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVCB97_SET_BLEND_CONST_RED 0x131c +#define NVCB97_SET_BLEND_CONST_RED_V 31:0 + +#define NVCB97_SET_BLEND_CONST_GREEN 0x1320 +#define NVCB97_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVCB97_SET_BLEND_CONST_BLUE 0x1324 +#define NVCB97_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVCB97_SET_BLEND_CONST_ALPHA 0x1328 +#define NVCB97_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVCB97_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVCB97_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVCB97_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVCB97_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BLEND_COLOR_OP 0x1340 +#define NVCB97_SET_BLEND_COLOR_OP_V 31:0 +#define NVCB97_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVCB97_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVCB97_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVCB97_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVCB97_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVCB97_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVCB97_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVCB97_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVCB97_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVCB97_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_BLEND_ALPHA_OP 0x134c +#define NVCB97_SET_BLEND_ALPHA_OP_V 31:0 +#define NVCB97_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVCB97_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVCB97_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVCB97_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVCB97_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVCB97_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVCB97_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVCB97_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVCB97_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVCB97_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVCB97_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVCB97_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_SINGLE_ROP_CONTROL 0x135c +#define NVCB97_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVCB97_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BLEND(i) (0x1360+(i)*4) +#define NVCB97_SET_BLEND_ENABLE 0:0 +#define NVCB97_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_STENCIL_TEST 0x1380 +#define NVCB97_SET_STENCIL_TEST_ENABLE 0:0 +#define NVCB97_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_STENCIL_OP_FAIL 0x1384 +#define NVCB97_SET_STENCIL_OP_FAIL_V 31:0 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVCB97_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVCB97_SET_STENCIL_OP_ZPASS 0x138c +#define NVCB97_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVCB97_SET_STENCIL_FUNC 0x1390 +#define NVCB97_SET_STENCIL_FUNC_V 31:0 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVCB97_SET_STENCIL_FUNC_REF 0x1394 +#define NVCB97_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVCB97_SET_STENCIL_FUNC_MASK 0x1398 +#define NVCB97_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVCB97_SET_STENCIL_MASK 0x139c +#define NVCB97_SET_STENCIL_MASK_V 7:0 + +#define NVCB97_SET_DRAW_AUTO_START 0x13a4 +#define NVCB97_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVCB97_SET_PS_SATURATE 0x13a8 +#define NVCB97_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVCB97_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVCB97_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVCB97_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVCB97_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVCB97_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVCB97_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVCB97_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVCB97_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVCB97_SET_WINDOW_ORIGIN 0x13ac +#define NVCB97_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVCB97_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVCB97_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVCB97_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVCB97_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVCB97_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVCB97_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVCB97_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVCB97_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVCB97_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVCB97_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVCB97_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVCB97_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVCB97_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVCB97_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVCB97_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVCB97_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVCB97_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVCB97_SET_PS_WARP_WATERMARKS 0x1450 +#define NVCB97_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVCB97_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVCB97_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVCB97_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVCB97_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVCB97_STORE_ZCULL 0x1464 +#define NVCB97_STORE_ZCULL_V 0:0 + +#define NVCB97_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVCB97_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVCB97_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVCB97_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVCB97_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVCB97_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVCB97_LOAD_ZCULL 0x1500 +#define NVCB97_LOAD_ZCULL_V 0:0 + +#define NVCB97_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVCB97_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVCB97_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVCB97_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVCB97_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVCB97_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVCB97_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVCB97_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVCB97_SET_USER_CLIP_ENABLE 0x1510 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVCB97_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVCB97_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVCB97_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_POINT_SIZE 0x1518 +#define NVCB97_SET_POINT_SIZE_V 31:0 + +#define NVCB97_SET_ZCULL_STATS 0x151c +#define NVCB97_SET_ZCULL_STATS_ENABLE 0:0 +#define NVCB97_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_POINT_SPRITE 0x1520 +#define NVCB97_SET_POINT_SPRITE_ENABLE 0:0 +#define NVCB97_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_SHADER_EXCEPTIONS 0x1528 +#define NVCB97_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVCB97_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVCB97_CLEAR_REPORT_VALUE 0x1530 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVCB97_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVCB97_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVCB97_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_ZT_SELECT 0x1538 +#define NVCB97_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVCB97_SET_RENDER_ENABLE_A 0x1550 +#define NVCB97_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_RENDER_ENABLE_B 0x1554 +#define NVCB97_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_RENDER_ENABLE_C 0x1558 +#define NVCB97_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVCB97_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVCB97_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVCB97_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVCB97_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVCB97_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVCB97_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVCB97_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVCB97_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVCB97_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVCB97_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVCB97_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVCB97_SET_ANTI_ALIASED_LINE 0x1570 +#define NVCB97_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVCB97_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_TEX_HEADER_POOL_A 0x1574 +#define NVCB97_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_TEX_HEADER_POOL_B 0x1578 +#define NVCB97_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_TEX_HEADER_POOL_C 0x157c +#define NVCB97_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVCB97_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVCB97_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVCB97_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVCB97_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVCB97_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVCB97_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVCB97_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVCB97_SET_SRGB_WRITE 0x15b8 +#define NVCB97_SET_SRGB_WRITE_ENABLE 0:0 +#define NVCB97_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_DEPTH_BIAS 0x15bc +#define NVCB97_SET_DEPTH_BIAS_V 31:0 + +#define NVCB97_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVCB97_SET_RT_LAYER 0x15cc +#define NVCB97_SET_RT_LAYER_V 15:0 +#define NVCB97_SET_RT_LAYER_CONTROL 16:16 +#define NVCB97_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVCB97_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVCB97_SET_ANTI_ALIAS 0x15d0 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVCB97_SET_EDGE_FLAG 0x15e4 +#define NVCB97_SET_EDGE_FLAG_V 0:0 +#define NVCB97_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVCB97_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVCB97_DRAW_INLINE_INDEX 0x15e8 +#define NVCB97_DRAW_INLINE_INDEX_V 31:0 + +#define NVCB97_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVCB97_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVCB97_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVCB97_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVCB97_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVCB97_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVCB97_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVCB97_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVCB97_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVCB97_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVCB97_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVCB97_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVCB97_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVCB97_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVCB97_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVCB97_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVCB97_SET_POINT_SPRITE_SELECT 0x1604 +#define NVCB97_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVCB97_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVCB97_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVCB97_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVCB97_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVCB97_END 0x1614 +#define NVCB97_END_V 0:0 + +#define NVCB97_BEGIN 0x1618 +#define NVCB97_BEGIN_OP 15:0 +#define NVCB97_BEGIN_OP_POINTS 0x00000000 +#define NVCB97_BEGIN_OP_LINES 0x00000001 +#define NVCB97_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVCB97_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVCB97_BEGIN_OP_TRIANGLES 0x00000004 +#define NVCB97_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVCB97_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVCB97_BEGIN_OP_QUADS 0x00000007 +#define NVCB97_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVCB97_BEGIN_OP_POLYGON 0x00000009 +#define NVCB97_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVCB97_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_BEGIN_OP_PATCH 0x0000000E +#define NVCB97_BEGIN_PRIMITIVE_ID 24:24 +#define NVCB97_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVCB97_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVCB97_BEGIN_INSTANCE_ID 27:26 +#define NVCB97_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVCB97_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVCB97_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVCB97_BEGIN_SPLIT_MODE 30:29 +#define NVCB97_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVCB97_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVCB97_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVCB97_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVCB97_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVCB97_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVCB97_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_VERTEX_ID_COPY 0x161c +#define NVCB97_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVCB97_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVCB97_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVCB97_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVCB97_LOAD_PRIMITIVE_ID 0x1624 +#define NVCB97_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVCB97_SET_SHADER_BASED_CULL 0x162c +#define NVCB97_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVCB97_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVCB97_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_CLASS_VERSION 0x1638 +#define NVCB97_SET_CLASS_VERSION_CURRENT 15:0 +#define NVCB97_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCB97_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVCB97_SET_DA_OUTPUT 0x164c +#define NVCB97_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVCB97_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVCB97_SET_ANTI_ALIASED_POINT 0x1658 +#define NVCB97_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVCB97_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_POINT_CENTER_MODE 0x165c +#define NVCB97_SET_POINT_CENTER_MODE_V 31:0 +#define NVCB97_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVCB97_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVCB97_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVCB97_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVCB97_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVCB97_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVCB97_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVCB97_SET_LINE_STIPPLE 0x166c +#define NVCB97_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVCB97_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVCB97_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVCB97_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVCB97_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVCB97_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVCB97_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVCB97_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVCB97_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVCB97_SET_PROVOKING_VERTEX 0x1684 +#define NVCB97_SET_PROVOKING_VERTEX_V 0:0 +#define NVCB97_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVCB97_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVCB97_SET_TWO_SIDED_LIGHT 0x1688 +#define NVCB97_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVCB97_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_POLYGON_STIPPLE 0x168c +#define NVCB97_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVCB97_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_SHADER_CONTROL 0x1690 +#define NVCB97_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVCB97_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVCB97_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVCB97_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVCB97_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVCB97_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVCB97_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVCB97_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVCB97_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVCB97_CHECK_CLASS_VERSION 0x16a0 +#define NVCB97_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVCB97_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCB97_SET_SPH_VERSION 0x16a4 +#define NVCB97_SET_SPH_VERSION_CURRENT 15:0 +#define NVCB97_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCB97_CHECK_SPH_VERSION 0x16a8 +#define NVCB97_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVCB97_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVCB97_SET_SCG_GRAPHICS_PRIORITY 0x16bc +#define NVCB97_SET_SCG_GRAPHICS_PRIORITY_PRIORITY 5:0 + +#define NVCB97_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS(i) (0x16c0+(i)*4) +#define NVCB97_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS_V 31:0 + +#define NVCB97_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVCB97_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVCB97_SET_AAM_VERSION 0x1790 +#define NVCB97_SET_AAM_VERSION_CURRENT 15:0 +#define NVCB97_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCB97_CHECK_AAM_VERSION 0x1794 +#define NVCB97_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVCB97_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCB97_SET_ZT_LAYER 0x179c +#define NVCB97_SET_ZT_LAYER_OFFSET 15:0 + +#define NVCB97_SET_INDEX_BUFFER_A 0x17c8 +#define NVCB97_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_INDEX_BUFFER_B 0x17cc +#define NVCB97_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_INDEX_BUFFER_E 0x17d8 +#define NVCB97_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVCB97_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVCB97_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVCB97_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVCB97_SET_INDEX_BUFFER_F 0x17dc +#define NVCB97_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVCB97_DRAW_INDEX_BUFFER 0x17e0 +#define NVCB97_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVCB97_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVCB97_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVCB97_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVCB97_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVCB97_OGL_SET_CULL 0x1918 +#define NVCB97_OGL_SET_CULL_ENABLE 0:0 +#define NVCB97_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVCB97_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVCB97_OGL_SET_FRONT_FACE 0x191c +#define NVCB97_OGL_SET_FRONT_FACE_V 31:0 +#define NVCB97_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVCB97_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVCB97_OGL_SET_CULL_FACE 0x1920 +#define NVCB97_OGL_SET_CULL_FACE_V 31:0 +#define NVCB97_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVCB97_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVCB97_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVCB97_SET_VIEWPORT_PIXEL 0x1924 +#define NVCB97_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVCB97_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVCB97_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVCB97_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVCB97_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVCB97_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE 17:16 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_USE_FIELD_MIN_Z_ZERO_MAX_Z_ONE 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MIN_Z_MAX_Z 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_ZERO_ONE 0x00000002 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MINUS_INF_PLUS_INF 0x00000003 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVCB97_SET_USER_CLIP_OP 0x1940 +#define NVCB97_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVCB97_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVCB97_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVCB97_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVCB97_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVCB97_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVCB97_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVCB97_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVCB97_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVCB97_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVCB97_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVCB97_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVCB97_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVCB97_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVCB97_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVCB97_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVCB97_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVCB97_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVCB97_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVCB97_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVCB97_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVCB97_INVALIDATE_ZCULL 0x1958 +#define NVCB97_INVALIDATE_ZCULL_V 31:0 +#define NVCB97_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVCB97_SET_ZCULL 0x1968 +#define NVCB97_SET_ZCULL_Z_ENABLE 0:0 +#define NVCB97_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVCB97_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_ZCULL_BOUNDS 0x196c +#define NVCB97_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVCB97_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVCB97_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVCB97_ZCULL_SYNC 0x1978 +#define NVCB97_ZCULL_SYNC_V 31:0 + +#define NVCB97_SET_CLIP_ID_TEST 0x197c +#define NVCB97_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVCB97_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVCB97_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVCB97_SET_CLIP_ID 0x1984 +#define NVCB97_SET_CLIP_ID_V 31:0 + +#define NVCB97_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVCB97_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVCB97_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVCB97_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVCB97_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVCB97_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVCB97_SET_LOGIC_OP 0x19c4 +#define NVCB97_SET_LOGIC_OP_ENABLE 0:0 +#define NVCB97_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_LOGIC_OP_FUNC 0x19c8 +#define NVCB97_SET_LOGIC_OP_FUNC_V 31:0 +#define NVCB97_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVCB97_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVCB97_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVCB97_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVCB97_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVCB97_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVCB97_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVCB97_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVCB97_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVCB97_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVCB97_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVCB97_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVCB97_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVCB97_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVCB97_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVCB97_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVCB97_SET_Z_COMPRESSION 0x19cc +#define NVCB97_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVCB97_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVCB97_CLEAR_SURFACE 0x19d0 +#define NVCB97_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVCB97_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVCB97_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVCB97_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVCB97_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVCB97_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVCB97_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVCB97_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVCB97_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVCB97_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVCB97_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVCB97_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVCB97_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVCB97_SET_CT_WRITE_R_ENABLE 0:0 +#define NVCB97_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_CT_WRITE_G_ENABLE 4:4 +#define NVCB97_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_CT_WRITE_B_ENABLE 8:8 +#define NVCB97_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_CT_WRITE_A_ENABLE 12:12 +#define NVCB97_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVCB97_PIPE_NOP 0x1a2c +#define NVCB97_PIPE_NOP_V 31:0 + +#define NVCB97_SET_SPARE00 0x1a30 +#define NVCB97_SET_SPARE00_V 31:0 + +#define NVCB97_SET_SPARE01 0x1a34 +#define NVCB97_SET_SPARE01_V 31:0 + +#define NVCB97_SET_SPARE02 0x1a38 +#define NVCB97_SET_SPARE02_V 31:0 + +#define NVCB97_SET_SPARE03 0x1a3c +#define NVCB97_SET_SPARE03_V 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVCB97_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 24:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVCB97_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVCB97_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVCB97_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVCB97_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVCB97_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVCB97_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVCB97_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVCB97_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVCB97_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVCB97_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVCB97_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_TIMESTAMP 0x00000014 +#define NVCB97_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVCB97_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVCB97_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVCB97_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVCB97_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVCB97_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVCB97_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVCB97_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVCB97_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVCB97_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVCB97_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVCB97_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVCB97_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVCB97_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVCB97_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVCB97_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVCB97_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVCB97_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVCB97_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVCB97_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVCB97_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVCB97_SET_PIPELINE_RESERVED_B(j) (0x2004+(j)*64) +#define NVCB97_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVCB97_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVCB97_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVCB97_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVCB97_SET_PIPELINE_REGISTER_COUNT_V 8:0 + +#define NVCB97_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVCB97_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVCB97_SET_PIPELINE_PROGRAM_ADDRESS_A(j) (0x2014+(j)*64) +#define NVCB97_SET_PIPELINE_PROGRAM_ADDRESS_A_UPPER 7:0 + +#define NVCB97_SET_PIPELINE_PROGRAM_ADDRESS_B(j) (0x2018+(j)*64) +#define NVCB97_SET_PIPELINE_PROGRAM_ADDRESS_B_LOWER 31:0 + +#define NVCB97_SET_PIPELINE_PROGRAM_PREFETCH(j) (0x201c+(j)*64) +#define NVCB97_SET_PIPELINE_PROGRAM_PREFETCH_SIZE_IN_BLOCKS 6:0 + +#define NVCB97_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVCB97_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVCB97_SET_FALCON00 0x2300 +#define NVCB97_SET_FALCON00_V 31:0 + +#define NVCB97_SET_FALCON01 0x2304 +#define NVCB97_SET_FALCON01_V 31:0 + +#define NVCB97_SET_FALCON02 0x2308 +#define NVCB97_SET_FALCON02_V 31:0 + +#define NVCB97_SET_FALCON03 0x230c +#define NVCB97_SET_FALCON03_V 31:0 + +#define NVCB97_SET_FALCON04 0x2310 +#define NVCB97_SET_FALCON04_V 31:0 + +#define NVCB97_SET_FALCON05 0x2314 +#define NVCB97_SET_FALCON05_V 31:0 + +#define NVCB97_SET_FALCON06 0x2318 +#define NVCB97_SET_FALCON06_V 31:0 + +#define NVCB97_SET_FALCON07 0x231c +#define NVCB97_SET_FALCON07_V 31:0 + +#define NVCB97_SET_FALCON08 0x2320 +#define NVCB97_SET_FALCON08_V 31:0 + +#define NVCB97_SET_FALCON09 0x2324 +#define NVCB97_SET_FALCON09_V 31:0 + +#define NVCB97_SET_FALCON10 0x2328 +#define NVCB97_SET_FALCON10_V 31:0 + +#define NVCB97_SET_FALCON11 0x232c +#define NVCB97_SET_FALCON11_V 31:0 + +#define NVCB97_SET_FALCON12 0x2330 +#define NVCB97_SET_FALCON12_V 31:0 + +#define NVCB97_SET_FALCON13 0x2334 +#define NVCB97_SET_FALCON13_V 31:0 + +#define NVCB97_SET_FALCON14 0x2338 +#define NVCB97_SET_FALCON14_V 31:0 + +#define NVCB97_SET_FALCON15 0x233c +#define NVCB97_SET_FALCON15_V 31:0 + +#define NVCB97_SET_FALCON16 0x2340 +#define NVCB97_SET_FALCON16_V 31:0 + +#define NVCB97_SET_FALCON17 0x2344 +#define NVCB97_SET_FALCON17_V 31:0 + +#define NVCB97_SET_FALCON18 0x2348 +#define NVCB97_SET_FALCON18_V 31:0 + +#define NVCB97_SET_FALCON19 0x234c +#define NVCB97_SET_FALCON19_V 31:0 + +#define NVCB97_SET_FALCON20 0x2350 +#define NVCB97_SET_FALCON20_V 31:0 + +#define NVCB97_SET_FALCON21 0x2354 +#define NVCB97_SET_FALCON21_V 31:0 + +#define NVCB97_SET_FALCON22 0x2358 +#define NVCB97_SET_FALCON22_V 31:0 + +#define NVCB97_SET_FALCON23 0x235c +#define NVCB97_SET_FALCON23_V 31:0 + +#define NVCB97_SET_FALCON24 0x2360 +#define NVCB97_SET_FALCON24_V 31:0 + +#define NVCB97_SET_FALCON25 0x2364 +#define NVCB97_SET_FALCON25_V 31:0 + +#define NVCB97_SET_FALCON26 0x2368 +#define NVCB97_SET_FALCON26_V 31:0 + +#define NVCB97_SET_FALCON27 0x236c +#define NVCB97_SET_FALCON27_V 31:0 + +#define NVCB97_SET_FALCON28 0x2370 +#define NVCB97_SET_FALCON28_V 31:0 + +#define NVCB97_SET_FALCON29 0x2374 +#define NVCB97_SET_FALCON29_V 31:0 + +#define NVCB97_SET_FALCON30 0x2378 +#define NVCB97_SET_FALCON30_V 31:0 + +#define NVCB97_SET_FALCON31 0x237c +#define NVCB97_SET_FALCON31_V 31:0 + +#define NVCB97_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVCB97_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVCB97_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVCB97_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVCB97_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVCB97_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVCB97_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVCB97_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVCB97_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVCB97_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVCB97_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVCB97_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVCB97_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVCB97_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVCB97_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVCB97_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVCB97_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVCB97_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVCB97_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVCB97_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVCB97_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVCB97_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVCB97_SET_TRAP_HANDLER_A 0x25f8 +#define NVCB97_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVCB97_SET_TRAP_HANDLER_B 0x25fc +#define NVCB97_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_COLOR_CLAMP 0x2600 +#define NVCB97_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVCB97_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVCB97_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVCB97_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVCB97_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVCB97_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVCB97_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVCB97_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVCB97_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVCB97_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVCB97_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVCB97_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVCB97_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVCB97_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVCB97_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVCB97_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVCB97_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVCB97_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVCB97_CALL_MME_MACRO_V 31:0 + +#define NVCB97_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVCB97_CALL_MME_DATA_V 31:0 + +#endif /* _cl_hopper_a_h_ */ diff --git a/userspace/sdks/nv570/inc/class/clcb97tex.h b/userspace/sdks/nv570/inc/class/clcb97tex.h new file mode 100644 index 0000000..f9871b7 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcb97tex.h @@ -0,0 +1,2437 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLCB97TEX_H__ +#define __CLCB97TEX_H__ + +/* +** Texture Header State Blocklinear + */ + +#define NVCB97_TEXHEAD_BL_COMPONENTS MW(6:0) +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE MW(9:7) +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE MW(12:10) +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE MW(15:13) +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE MW(18:16) +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_X_SOURCE MW(21:19) +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_Y_SOURCE MW(24:22) +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_Z_SOURCE MW(27:25) +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_W_SOURCE MW(30:28) +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_PACK_COMPONENTS MW(31:31) +#define NVCB97_TEXHEAD_BL_RESERVED1Y MW(36:32) +#define NVCB97_TEXHEAD_BL_GOB_DEPTH_OFFSET MW(38:37) +#define NVCB97_TEXHEAD_BL_RESERVED1X MW(40:39) +#define NVCB97_TEXHEAD_BL_ADDRESS_BITS31TO9 MW(63:41) +#define NVCB97_TEXHEAD_BL_ADDRESS_BITS48TO32 MW(80:64) +#define NVCB97_TEXHEAD_BL_RESERVED_ADDRESS MW(84:81) +#define NVCB97_TEXHEAD_BL_HEADER_VERSION MW(87:85) +#define NVCB97_TEXHEAD_BL_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVCB97_TEXHEAD_BL_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVCB97_TEXHEAD_BL_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVCB97_TEXHEAD_BL_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVCB97_TEXHEAD_BL_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVCB97_TEXHEAD_BL_RESERVED_HEADER_VERSION MW(88:88) +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVCB97_TEXHEAD_BL_RESERVED2A MW(95:93) +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_WIDTH MW(98:96) +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT MW(101:99) +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH MW(104:102) +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_BL_RESERVED3Y MW(105:105) +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS MW(108:106) +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_BL_GOB3D MW(109:109) +#define NVCB97_TEXHEAD_BL_RESERVED3Z MW(111:110) +#define NVCB97_TEXHEAD_BL_LOD_ANISO_QUALITY2 MW(112:112) +#define NVCB97_TEXHEAD_BL_LOD_ANISO_QUALITY MW(113:113) +#define NVCB97_TEXHEAD_BL_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_BL_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_BL_LOD_ISO_QUALITY MW(114:114) +#define NVCB97_TEXHEAD_BL_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_BL_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_BL_ANISO_SPREAD_SCALE MW(121:117) +#define NVCB97_TEXHEAD_BL_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVCB97_TEXHEAD_BL_DEPTH_TEXTURE MW(123:123) +#define NVCB97_TEXHEAD_BL_MAX_MIP_LEVEL MW(127:124) +#define NVCB97_TEXHEAD_BL_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_BL_DEPTH_MINUS_ONE_BIT14 MW(145:145) +#define NVCB97_TEXHEAD_BL_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVCB97_TEXHEAD_BL_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVCB97_TEXHEAD_BL_S_R_G_B_CONVERSION MW(150:150) +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE MW(154:151) +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_BL_SECTOR_PROMOTION MW(156:155) +#define NVCB97_TEXHEAD_BL_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_BL_BORDER_SIZE MW(159:157) +#define NVCB97_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVCB97_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVCB97_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVCB97_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVCB97_TEXHEAD_BL_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVCB97_TEXHEAD_BL_HEIGHT_MINUS_ONE MW(175:160) +#define NVCB97_TEXHEAD_BL_DEPTH_MINUS_ONE MW(189:176) +#define NVCB97_TEXHEAD_BL_RESERVED5A MW(190:190) +#define NVCB97_TEXHEAD_BL_NORMALIZED_COORDS MW(191:191) +#define NVCB97_TEXHEAD_BL_RESERVED6Y MW(192:192) +#define NVCB97_TEXHEAD_BL_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_BL_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_BL_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_BL_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVCB97_TEXHEAD_BL_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT MW(235:232) +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVCB97_TEXHEAD_BL_MIN_LOD_CLAMP MW(247:236) +#define NVCB97_TEXHEAD_BL_RESERVED7Y MW(255:248) + + +/* +** Texture Header State Blocklinear Color Key + */ + +#define NVCB97_TEXHEAD_BLCK_COMPONENTS MW(6:0) +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE MW(9:7) +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE MW(12:10) +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE MW(15:13) +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE MW(18:16) +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE MW(21:19) +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE MW(24:22) +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE MW(27:25) +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE MW(30:28) +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_PACK_COMPONENTS MW(31:31) +#define NVCB97_TEXHEAD_BLCK_RESERVED1Y MW(36:32) +#define NVCB97_TEXHEAD_BLCK_GOB_DEPTH_OFFSET MW(38:37) +#define NVCB97_TEXHEAD_BLCK_RESERVED1X MW(40:39) +#define NVCB97_TEXHEAD_BLCK_ADDRESS_BITS31TO9 MW(63:41) +#define NVCB97_TEXHEAD_BLCK_ADDRESS_BITS48TO32 MW(80:64) +#define NVCB97_TEXHEAD_BLCK_RESERVED_ADDRESS MW(84:81) +#define NVCB97_TEXHEAD_BLCK_HEADER_VERSION MW(87:85) +#define NVCB97_TEXHEAD_BLCK_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVCB97_TEXHEAD_BLCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVCB97_TEXHEAD_BLCK_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVCB97_TEXHEAD_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVCB97_TEXHEAD_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVCB97_TEXHEAD_BLCK_RESERVED_HEADER_VERSION MW(88:88) +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVCB97_TEXHEAD_BLCK_RESERVED2A MW(95:93) +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_WIDTH MW(98:96) +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT MW(101:99) +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH MW(104:102) +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_BLCK_RESERVED3Y MW(105:105) +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS MW(108:106) +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_BLCK_GOB3D MW(109:109) +#define NVCB97_TEXHEAD_BLCK_RESERVED3Z MW(111:110) +#define NVCB97_TEXHEAD_BLCK_LOD_ANISO_QUALITY2 MW(112:112) +#define NVCB97_TEXHEAD_BLCK_LOD_ANISO_QUALITY MW(113:113) +#define NVCB97_TEXHEAD_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_BLCK_LOD_ISO_QUALITY MW(114:114) +#define NVCB97_TEXHEAD_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_ANISO_SPREAD_SCALE MW(121:117) +#define NVCB97_TEXHEAD_BLCK_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVCB97_TEXHEAD_BLCK_DEPTH_TEXTURE MW(123:123) +#define NVCB97_TEXHEAD_BLCK_MAX_MIP_LEVEL MW(127:124) +#define NVCB97_TEXHEAD_BLCK_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_BLCK_DEPTH_MINUS_ONE_BIT14 MW(145:145) +#define NVCB97_TEXHEAD_BLCK_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVCB97_TEXHEAD_BLCK_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVCB97_TEXHEAD_BLCK_S_R_G_B_CONVERSION MW(150:150) +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE MW(154:151) +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_BLCK_SECTOR_PROMOTION MW(156:155) +#define NVCB97_TEXHEAD_BLCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_BLCK_BORDER_SIZE MW(159:157) +#define NVCB97_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVCB97_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVCB97_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVCB97_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVCB97_TEXHEAD_BLCK_HEIGHT_MINUS_ONE MW(175:160) +#define NVCB97_TEXHEAD_BLCK_DEPTH_MINUS_ONE MW(189:176) +#define NVCB97_TEXHEAD_BLCK_RESERVED5A MW(190:190) +#define NVCB97_TEXHEAD_BLCK_NORMALIZED_COORDS MW(191:191) +#define NVCB97_TEXHEAD_BLCK_COLOR_KEY_OP MW(192:192) +#define NVCB97_TEXHEAD_BLCK_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_BLCK_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_BLCK_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Header State One-D Buffer + */ + +#define NVCB97_TEXHEAD_1D_COMPONENTS MW(6:0) +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE MW(9:7) +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE MW(12:10) +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE MW(15:13) +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE MW(18:16) +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_X_SOURCE MW(21:19) +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_Y_SOURCE MW(24:22) +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_Z_SOURCE MW(27:25) +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_W_SOURCE MW(30:28) +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_PACK_COMPONENTS MW(31:31) +#define NVCB97_TEXHEAD_1D_ADDRESS_BITS31TO0 MW(63:32) +#define NVCB97_TEXHEAD_1D_ADDRESS_BITS48TO32 MW(80:64) +#define NVCB97_TEXHEAD_1D_RESERVED_ADDRESS MW(84:81) +#define NVCB97_TEXHEAD_1D_HEADER_VERSION MW(87:85) +#define NVCB97_TEXHEAD_1D_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVCB97_TEXHEAD_1D_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVCB97_TEXHEAD_1D_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVCB97_TEXHEAD_1D_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVCB97_TEXHEAD_1D_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVCB97_TEXHEAD_1D_RESERVED_HEADER_VERSION MW(88:88) +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVCB97_TEXHEAD_1D_RESERVED2A MW(95:93) +#define NVCB97_TEXHEAD_1D_WIDTH_MINUS_ONE_BITS31TO16 MW(111:96) +#define NVCB97_TEXHEAD_1D_RESERVED3X MW(127:112) +#define NVCB97_TEXHEAD_1D_WIDTH_MINUS_ONE_BITS15TO0 MW(143:128) +#define NVCB97_TEXHEAD_1D_RESERVED4X MW(149:144) +#define NVCB97_TEXHEAD_1D_S_R_G_B_CONVERSION MW(150:150) +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE MW(154:151) +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_1D_SECTOR_PROMOTION MW(156:155) +#define NVCB97_TEXHEAD_1D_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_1D_RESERVED4Y MW(159:157) +#define NVCB97_TEXHEAD_1D_RESERVED5X MW(189:160) +#define NVCB97_TEXHEAD_1D_RESERVED5A MW(190:190) +#define NVCB97_TEXHEAD_1D_RESERVED5Y MW(191:191) +#define NVCB97_TEXHEAD_1D_RESERVED6X MW(223:192) +#define NVCB97_TEXHEAD_1D_RESERVED7X MW(255:224) + + +/* +** Texture Header State Pitch + */ + +#define NVCB97_TEXHEAD_PITCH_COMPONENTS MW(6:0) +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE MW(9:7) +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE MW(12:10) +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE MW(15:13) +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE MW(18:16) +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE MW(21:19) +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE MW(24:22) +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE MW(27:25) +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE MW(30:28) +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_PACK_COMPONENTS MW(31:31) +#define NVCB97_TEXHEAD_PITCH_RESERVED1A MW(36:32) +#define NVCB97_TEXHEAD_PITCH_ADDRESS_BITS31TO5 MW(63:37) +#define NVCB97_TEXHEAD_PITCH_ADDRESS_BITS48TO32 MW(80:64) +#define NVCB97_TEXHEAD_PITCH_RESERVED_ADDRESS MW(84:81) +#define NVCB97_TEXHEAD_PITCH_HEADER_VERSION MW(87:85) +#define NVCB97_TEXHEAD_PITCH_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVCB97_TEXHEAD_PITCH_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVCB97_TEXHEAD_PITCH_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVCB97_TEXHEAD_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVCB97_TEXHEAD_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVCB97_TEXHEAD_PITCH_RESERVED_HEADER_VERSION MW(88:88) +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVCB97_TEXHEAD_PITCH_RESERVED2A MW(95:93) +#define NVCB97_TEXHEAD_PITCH_PITCH_BITS20TO5 MW(111:96) +#define NVCB97_TEXHEAD_PITCH_LOD_ANISO_QUALITY2 MW(112:112) +#define NVCB97_TEXHEAD_PITCH_LOD_ANISO_QUALITY MW(113:113) +#define NVCB97_TEXHEAD_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_PITCH_LOD_ISO_QUALITY MW(114:114) +#define NVCB97_TEXHEAD_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_ANISO_SPREAD_SCALE MW(121:117) +#define NVCB97_TEXHEAD_PITCH_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVCB97_TEXHEAD_PITCH_DEPTH_TEXTURE MW(123:123) +#define NVCB97_TEXHEAD_PITCH_MAX_MIP_LEVEL MW(127:124) +#define NVCB97_TEXHEAD_PITCH_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_PITCH_PITCH_BIT21 MW(145:145) +#define NVCB97_TEXHEAD_PITCH_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVCB97_TEXHEAD_PITCH_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVCB97_TEXHEAD_PITCH_S_R_G_B_CONVERSION MW(150:150) +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE MW(154:151) +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_PITCH_SECTOR_PROMOTION MW(156:155) +#define NVCB97_TEXHEAD_PITCH_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_PITCH_BORDER_SIZE MW(159:157) +#define NVCB97_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVCB97_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVCB97_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVCB97_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVCB97_TEXHEAD_PITCH_HEIGHT_MINUS_ONE MW(175:160) +#define NVCB97_TEXHEAD_PITCH_DEPTH_MINUS_ONE MW(189:176) +#define NVCB97_TEXHEAD_PITCH_RESERVED5A MW(190:190) +#define NVCB97_TEXHEAD_PITCH_NORMALIZED_COORDS MW(191:191) +#define NVCB97_TEXHEAD_PITCH_RESERVED6Y MW(192:192) +#define NVCB97_TEXHEAD_PITCH_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_PITCH_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_PITCH_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVCB97_TEXHEAD_PITCH_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT MW(235:232) +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVCB97_TEXHEAD_PITCH_MIN_LOD_CLAMP MW(247:236) +#define NVCB97_TEXHEAD_PITCH_RESERVED7Y MW(255:248) + + +/* +** Texture Header State Pitch Color Key + */ + +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS MW(6:0) +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE MW(9:7) +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE MW(12:10) +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE MW(15:13) +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE MW(18:16) +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE MW(21:19) +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE MW(24:22) +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE MW(27:25) +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE MW(30:28) +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_PACK_COMPONENTS MW(31:31) +#define NVCB97_TEXHEAD_PITCHCK_RESERVED1A MW(36:32) +#define NVCB97_TEXHEAD_PITCHCK_ADDRESS_BITS31TO5 MW(63:37) +#define NVCB97_TEXHEAD_PITCHCK_ADDRESS_BITS48TO32 MW(80:64) +#define NVCB97_TEXHEAD_PITCHCK_RESERVED_ADDRESS MW(84:81) +#define NVCB97_TEXHEAD_PITCHCK_HEADER_VERSION MW(87:85) +#define NVCB97_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_RESERVED_HEADER_VERSION MW(88:88) +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVCB97_TEXHEAD_PITCHCK_RESERVED2A MW(95:93) +#define NVCB97_TEXHEAD_PITCHCK_PITCH_BITS20TO5 MW(111:96) +#define NVCB97_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY2 MW(112:112) +#define NVCB97_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY MW(113:113) +#define NVCB97_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_LOD_ISO_QUALITY MW(114:114) +#define NVCB97_TEXHEAD_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_SPREAD_SCALE MW(121:117) +#define NVCB97_TEXHEAD_PITCHCK_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVCB97_TEXHEAD_PITCHCK_DEPTH_TEXTURE MW(123:123) +#define NVCB97_TEXHEAD_PITCHCK_MAX_MIP_LEVEL MW(127:124) +#define NVCB97_TEXHEAD_PITCHCK_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_PITCHCK_PITCH_BIT21 MW(145:145) +#define NVCB97_TEXHEAD_PITCHCK_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVCB97_TEXHEAD_PITCHCK_S_R_G_B_CONVERSION MW(150:150) +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE MW(154:151) +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_PITCHCK_SECTOR_PROMOTION MW(156:155) +#define NVCB97_TEXHEAD_PITCHCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_BORDER_SIZE MW(159:157) +#define NVCB97_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_HEIGHT_MINUS_ONE MW(175:160) +#define NVCB97_TEXHEAD_PITCHCK_DEPTH_MINUS_ONE MW(189:176) +#define NVCB97_TEXHEAD_PITCHCK_RESERVED5A MW(190:190) +#define NVCB97_TEXHEAD_PITCHCK_NORMALIZED_COORDS MW(191:191) +#define NVCB97_TEXHEAD_PITCHCK_COLOR_KEY_OP MW(192:192) +#define NVCB97_TEXHEAD_PITCHCK_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_PITCHCK_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Header V2 Blocklinear + */ + +#define NVCB97_TEXHEAD_V2_BL_RESERVED0A MW(3:0) +#define NVCB97_TEXHEAD_V2_BL_GOB_DEPTH_OFFSET MW(8:4) +#define NVCB97_TEXHEAD_V2_BL_ADDRESS_BITS31TO9 MW(31:9) +#define NVCB97_TEXHEAD_V2_BL_ADDRESS_BITS56TO32 MW(56:32) +#define NVCB97_TEXHEAD_V2_BL_RESERVED1A MW(63:57) +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_WIDTH MW(66:64) +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT MW(69:67) +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH MW(72:70) +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_RESERVED3Y MW(73:73) +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS MW(76:74) +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_GOB3D MW(77:77) +#define NVCB97_TEXHEAD_V2_BL_RESERVED2Z MW(79:78) +#define NVCB97_TEXHEAD_V2_BL_LOD_ANISO_QUALITY2 MW(80:80) +#define NVCB97_TEXHEAD_V2_BL_LOD_ANISO_QUALITY MW(81:81) +#define NVCB97_TEXHEAD_V2_BL_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_LOD_ISO_QUALITY MW(82:82) +#define NVCB97_TEXHEAD_V2_BL_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_MODIFIER MW(84:83) +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_ANISO_SPREAD_SCALE MW(89:85) +#define NVCB97_TEXHEAD_V2_BL_USE_HEADER_OPT_CONTROL MW(90:90) +#define NVCB97_TEXHEAD_V2_BL_DEPTH_TEXTURE MW(91:91) +#define NVCB97_TEXHEAD_V2_BL_MAX_MIP_LEVEL MW(95:92) +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE MW(98:96) +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE MW(101:99) +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE MW(104:102) +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE MW(107:105) +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE MW(111:108) +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_UNORM 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_SNORM 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_FLOAT 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_SGNRGB 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_SGNA 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_DSDT 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_UINT 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_SINT 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_ZS 0x00000008 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_SZ 0x00000009 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_ZFS 0x0000000a +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS MW(118:112) +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_V2_BL_PACK_COMPONENTS MW(119:119) +#define NVCB97_TEXHEAD_V2_BL_RESERVED3A MW(123:120) +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION MW(127:124) +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION_SELECT_PITCH_COLOR_KEY_V2 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION_SELECT_PITCH_V2 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION_SELECT_BLOCKLINEAR_V2 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY_V2 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION_SELECT_ONE_D_RAW_TYPED 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION_SELECT_ONE_D_STRUCT_BUF 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_V2_BL_NORMALIZED_COORDS MW(145:145) +#define NVCB97_TEXHEAD_V2_BL_ANISO_SPREAD_MAX_LOG2 MW(148:146) +#define NVCB97_TEXHEAD_V2_BL_S_R_G_B_CONVERSION MW(149:149) +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE MW(153:150) +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_V2_BL_SECTOR_PROMOTION MW(155:154) +#define NVCB97_TEXHEAD_V2_BL_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_BORDER_SOURCE MW(156:156) +#define NVCB97_TEXHEAD_V2_BL_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_RESERVED4A MW(159:157) +#define NVCB97_TEXHEAD_V2_BL_HEIGHT_MINUS_ONE MW(176:160) +#define NVCB97_TEXHEAD_V2_BL_DEPTH_MINUS_ONE MW(191:177) +#define NVCB97_TEXHEAD_V2_BL_RESERVED6Y MW(192:192) +#define NVCB97_TEXHEAD_V2_BL_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_V2_BL_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_V2_BL_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVCB97_TEXHEAD_V2_BL_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT MW(235:232) +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVCB97_TEXHEAD_V2_BL_MIN_LOD_CLAMP MW(247:236) +#define NVCB97_TEXHEAD_V2_BL_RESERVED7Y MW(255:248) + + +/* +** Texture Header V2 Blocklinear Color Key + */ + +#define NVCB97_TEXHEAD_V2_BLCK_RESERVED0A MW(3:0) +#define NVCB97_TEXHEAD_V2_BLCK_GOB_DEPTH_OFFSET MW(8:4) +#define NVCB97_TEXHEAD_V2_BLCK_ADDRESS_BITS31TO9 MW(31:9) +#define NVCB97_TEXHEAD_V2_BLCK_ADDRESS_BITS56TO32 MW(56:32) +#define NVCB97_TEXHEAD_V2_BLCK_RESERVED1A MW(63:57) +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_WIDTH MW(66:64) +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT MW(69:67) +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH MW(72:70) +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_RESERVED3Y MW(73:73) +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS MW(76:74) +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_GOB3D MW(77:77) +#define NVCB97_TEXHEAD_V2_BLCK_RESERVED2Z MW(79:78) +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ANISO_QUALITY2 MW(80:80) +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ANISO_QUALITY MW(81:81) +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ISO_QUALITY MW(82:82) +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_MODIFIER MW(84:83) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_SPREAD_SCALE MW(89:85) +#define NVCB97_TEXHEAD_V2_BLCK_USE_HEADER_OPT_CONTROL MW(90:90) +#define NVCB97_TEXHEAD_V2_BLCK_DEPTH_TEXTURE MW(91:91) +#define NVCB97_TEXHEAD_V2_BLCK_MAX_MIP_LEVEL MW(95:92) +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE MW(98:96) +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE MW(101:99) +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE MW(104:102) +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE MW(107:105) +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE MW(111:108) +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_UNORM 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_SNORM 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_FLOAT 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_SGNRGB 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_SGNA 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_DSDT 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_UINT 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_SINT 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_ZS 0x00000008 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_SZ 0x00000009 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_ZFS 0x0000000a +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS MW(118:112) +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_V2_BLCK_PACK_COMPONENTS MW(119:119) +#define NVCB97_TEXHEAD_V2_BLCK_RESERVED3A MW(123:120) +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION MW(127:124) +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY_V2 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION_SELECT_PITCH_V2 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR_V2 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY_V2 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION_SELECT_ONE_D_RAW_TYPED 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION_SELECT_ONE_D_STRUCT_BUF 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_V2_BLCK_NORMALIZED_COORDS MW(145:145) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_SPREAD_MAX_LOG2 MW(148:146) +#define NVCB97_TEXHEAD_V2_BLCK_S_R_G_B_CONVERSION MW(149:149) +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE MW(153:150) +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_V2_BLCK_SECTOR_PROMOTION MW(155:154) +#define NVCB97_TEXHEAD_V2_BLCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_BORDER_SOURCE MW(156:156) +#define NVCB97_TEXHEAD_V2_BLCK_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_RESERVED4A MW(159:157) +#define NVCB97_TEXHEAD_V2_BLCK_HEIGHT_MINUS_ONE MW(176:160) +#define NVCB97_TEXHEAD_V2_BLCK_DEPTH_MINUS_ONE MW(191:177) +#define NVCB97_TEXHEAD_V2_BLCK_COLOR_KEY_OP MW(192:192) +#define NVCB97_TEXHEAD_V2_BLCK_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_V2_BLCK_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Header V2 One-D Raw Typed + */ + +#define NVCB97_TEXHEAD_V2_1DRT_ADDRESS_BITS31TO0 MW(31:0) +#define NVCB97_TEXHEAD_V2_1DRT_ADDRESS_BITS63TO32 MW(63:32) +#define NVCB97_TEXHEAD_V2_1DRT_WIDTH_MINUS_ONE MW(95:64) +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE MW(98:96) +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE MW(101:99) +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE MW(104:102) +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE MW(107:105) +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE MW(111:108) +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_UNORM 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_SNORM 0x00000001 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_FLOAT 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_SGNRGB 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_SGNA 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_DSDT 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_UINT 0x00000006 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_SINT 0x00000007 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_ZS 0x00000008 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_SZ 0x00000009 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_ZFS 0x0000000a +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS MW(117:112) +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_INVALID 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_G8R24 0x0000000d +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_G24R8 0x0000000e +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R32 0x0000000f +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_G8R8 0x00000018 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R16 0x0000001b +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R8 0x0000001d +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_G4R4 0x0000001e +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_X8B8G8R8_SRGB 0x00000031 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_A8B8G8R8_SRGB 0x00000032 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_G8R8_SRGB 0x00000033 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R8_SRGB 0x00000034 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZESV2_CS_BITFIELD_SIZE 0x0000003f +#define NVCB97_TEXHEAD_V2_1DRT_SECTOR_PROMOTION MW(119:118) +#define NVCB97_TEXHEAD_V2_1DRT_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_V2_1DRT_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_RESERVED3A MW(123:120) +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION MW(127:124) +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION_SELECT_PITCH_COLOR_KEY_V2 0x00000001 +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION_SELECT_PITCH_V2 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION_SELECT_BLOCKLINEAR_V2 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY_V2 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION_SELECT_ONE_D_RAW_TYPED 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION_SELECT_ONE_D_STRUCT_BUF 0x00000006 +#define NVCB97_TEXHEAD_V2_1DRT_RESERVED4X MW(156:128) +#define NVCB97_TEXHEAD_V2_1DRT_RESERVED4A MW(159:157) +#define NVCB97_TEXHEAD_V2_1DRT_RESERVED5X MW(191:160) +#define NVCB97_TEXHEAD_V2_1DRT_RESERVED6X MW(223:192) +#define NVCB97_TEXHEAD_V2_1DRT_RESERVED7X MW(255:224) + + +/* +** Texture Header V2 One-D Structured Buffer + */ + +#define NVCB97_TEXHEAD_V2_1DSB_ADDRESS_BITS31TO0 MW(31:0) +#define NVCB97_TEXHEAD_V2_1DSB_ADDRESS_BITS63TO32 MW(63:32) +#define NVCB97_TEXHEAD_V2_1DSB_WIDTH_MINUS_ONE MW(95:64) +#define NVCB97_TEXHEAD_V2_1DSB_STRIDE MW(107:96) +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE MW(111:108) +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_UNORM 0x00000000 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_SNORM 0x00000001 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_FLOAT 0x00000002 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_SGNRGB 0x00000003 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_SGNA 0x00000004 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_DSDT 0x00000005 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_UINT 0x00000006 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_SINT 0x00000007 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_ZS 0x00000008 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_SZ 0x00000009 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_ZFS 0x0000000a +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS MW(117:112) +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_INVALID 0x00000000 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_G8R24 0x0000000d +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_G24R8 0x0000000e +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R32 0x0000000f +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_G8R8 0x00000018 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R16 0x0000001b +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R8 0x0000001d +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_G4R4 0x0000001e +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_X8B8G8R8_SRGB 0x00000031 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_A8B8G8R8_SRGB 0x00000032 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_G8R8_SRGB 0x00000033 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R8_SRGB 0x00000034 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZESV2_CS_BITFIELD_SIZE 0x0000003f +#define NVCB97_TEXHEAD_V2_1DSB_SECTOR_PROMOTION MW(119:118) +#define NVCB97_TEXHEAD_V2_1DSB_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_V2_1DSB_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_V2_1DSB_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_V2_1DSB_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_V2_1DSB_RESERVED3A MW(123:120) +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION MW(127:124) +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION_SELECT_PITCH_COLOR_KEY_V2 0x00000001 +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION_SELECT_PITCH_V2 0x00000002 +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION_SELECT_BLOCKLINEAR_V2 0x00000003 +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY_V2 0x00000004 +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION_SELECT_ONE_D_RAW_TYPED 0x00000005 +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION_SELECT_ONE_D_STRUCT_BUF 0x00000006 +#define NVCB97_TEXHEAD_V2_1DSB_RESERVED4X MW(156:128) +#define NVCB97_TEXHEAD_V2_1DSB_RESERVED4A MW(159:157) +#define NVCB97_TEXHEAD_V2_1DSB_RESERVED5X MW(191:160) +#define NVCB97_TEXHEAD_V2_1DSB_RESERVED6X MW(223:192) +#define NVCB97_TEXHEAD_V2_1DSB_RESERVED7X MW(255:224) + + +/* +** Texture Header V2 Pitch + */ + +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED0A MW(3:0) +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED0X MW(4:4) +#define NVCB97_TEXHEAD_V2_PITCH_ADDRESS_BITS31TO5 MW(31:5) +#define NVCB97_TEXHEAD_V2_PITCH_ADDRESS_BITS56TO32 MW(56:32) +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED1A MW(63:57) +#define NVCB97_TEXHEAD_V2_PITCH_PITCH_BITS21TO5 MW(80:64) +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ANISO_QUALITY2 MW(81:81) +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ANISO_QUALITY MW(82:82) +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ISO_QUALITY MW(83:83) +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_MODIFIER MW(85:84) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_SPREAD_SCALE MW(90:86) +#define NVCB97_TEXHEAD_V2_PITCH_DEPTH_TEXTURE MW(91:91) +#define NVCB97_TEXHEAD_V2_PITCH_MAX_MIP_LEVEL MW(95:92) +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE MW(98:96) +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE MW(101:99) +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE MW(104:102) +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE MW(107:105) +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE MW(111:108) +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_UNORM 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_SNORM 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_FLOAT 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_SGNRGB 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_SGNA 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_DSDT 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_UINT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_SINT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_ZS 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_SZ 0x00000009 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_ZFS 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS MW(118:112) +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_V2_PITCH_PACK_COMPONENTS MW(119:119) +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED3A MW(123:120) +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION MW(127:124) +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION_SELECT_PITCH_COLOR_KEY_V2 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION_SELECT_PITCH_V2 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR_V2 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY_V2 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION_SELECT_ONE_D_RAW_TYPED 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION_SELECT_ONE_D_STRUCT_BUF 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_V2_PITCH_NORMALIZED_COORDS MW(145:145) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_SPREAD_MAX_LOG2 MW(148:146) +#define NVCB97_TEXHEAD_V2_PITCH_S_R_G_B_CONVERSION MW(149:149) +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE MW(153:150) +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_V2_PITCH_SECTOR_PROMOTION MW(155:154) +#define NVCB97_TEXHEAD_V2_PITCH_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_BORDER_SOURCE MW(156:156) +#define NVCB97_TEXHEAD_V2_PITCH_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED4A MW(159:157) +#define NVCB97_TEXHEAD_V2_PITCH_HEIGHT_MINUS_ONE MW(176:160) +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED5Y MW(191:177) +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED6Y MW(192:192) +#define NVCB97_TEXHEAD_V2_PITCH_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_V2_PITCH_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVCB97_TEXHEAD_V2_PITCH_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT MW(235:232) +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVCB97_TEXHEAD_V2_PITCH_MIN_LOD_CLAMP MW(247:236) +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED7Y MW(255:248) + + +/* +** Texture Header V2 Pitch Color Key + */ + +#define NVCB97_TEXHEAD_V2_PITCHCK_RESERVED0A MW(3:0) +#define NVCB97_TEXHEAD_V2_PITCHCK_RESERVED0X MW(4:4) +#define NVCB97_TEXHEAD_V2_PITCHCK_ADDRESS_BITS31TO5 MW(31:5) +#define NVCB97_TEXHEAD_V2_PITCHCK_ADDRESS_BITS56TO32 MW(56:32) +#define NVCB97_TEXHEAD_V2_PITCHCK_RESERVED1A MW(63:57) +#define NVCB97_TEXHEAD_V2_PITCHCK_PITCH_BITS21TO5 MW(80:64) +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ANISO_QUALITY2 MW(81:81) +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ANISO_QUALITY MW(82:82) +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ISO_QUALITY MW(83:83) +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER MW(85:84) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_SPREAD_SCALE MW(90:86) +#define NVCB97_TEXHEAD_V2_PITCHCK_DEPTH_TEXTURE MW(91:91) +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_MIP_LEVEL MW(95:92) +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE MW(98:96) +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE MW(101:99) +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE MW(104:102) +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE MW(107:105) +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE MW(111:108) +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_UNORM 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_SNORM 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_FLOAT 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_SGNRGB 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_SGNA 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_DSDT 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_UINT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_SINT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_ZS 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_SZ 0x00000009 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_ZFS 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS MW(118:112) +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_V2_PITCHCK_PACK_COMPONENTS MW(119:119) +#define NVCB97_TEXHEAD_V2_PITCHCK_RESERVED3A MW(123:120) +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION MW(127:124) +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY_V2 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION_SELECT_PITCH_V2 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR_V2 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY_V2 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION_SELECT_ONE_D_RAW_TYPED 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION_SELECT_ONE_D_STRUCT_BUF 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_V2_PITCHCK_NORMALIZED_COORDS MW(145:145) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_SPREAD_MAX_LOG2 MW(148:146) +#define NVCB97_TEXHEAD_V2_PITCHCK_S_R_G_B_CONVERSION MW(149:149) +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE MW(153:150) +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_V2_PITCHCK_SECTOR_PROMOTION MW(155:154) +#define NVCB97_TEXHEAD_V2_PITCHCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_BORDER_SOURCE MW(156:156) +#define NVCB97_TEXHEAD_V2_PITCHCK_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_RESERVED4A MW(159:157) +#define NVCB97_TEXHEAD_V2_PITCHCK_HEIGHT_MINUS_ONE MW(176:160) +#define NVCB97_TEXHEAD_V2_PITCHCK_RESERVED5Y MW(191:177) +#define NVCB97_TEXHEAD_V2_PITCHCK_COLOR_KEY_OP MW(192:192) +#define NVCB97_TEXHEAD_V2_PITCHCK_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_V2_PITCHCK_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Sampler State + */ + +#define NVCB97_TEXSAMP0_ADDRESS_U 2:0 +#define NVCB97_TEXSAMP0_ADDRESS_U_WRAP 0x00000000 +#define NVCB97_TEXSAMP0_ADDRESS_U_MIRROR 0x00000001 +#define NVCB97_TEXSAMP0_ADDRESS_U_CLAMP_TO_EDGE 0x00000002 +#define NVCB97_TEXSAMP0_ADDRESS_U_BORDER 0x00000003 +#define NVCB97_TEXSAMP0_ADDRESS_U_CLAMP_OGL 0x00000004 +#define NVCB97_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVCB97_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_BORDER 0x00000006 +#define NVCB97_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVCB97_TEXSAMP0_ADDRESS_V 5:3 +#define NVCB97_TEXSAMP0_ADDRESS_V_WRAP 0x00000000 +#define NVCB97_TEXSAMP0_ADDRESS_V_MIRROR 0x00000001 +#define NVCB97_TEXSAMP0_ADDRESS_V_CLAMP_TO_EDGE 0x00000002 +#define NVCB97_TEXSAMP0_ADDRESS_V_BORDER 0x00000003 +#define NVCB97_TEXSAMP0_ADDRESS_V_CLAMP_OGL 0x00000004 +#define NVCB97_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVCB97_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_BORDER 0x00000006 +#define NVCB97_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVCB97_TEXSAMP0_ADDRESS_P 8:6 +#define NVCB97_TEXSAMP0_ADDRESS_P_WRAP 0x00000000 +#define NVCB97_TEXSAMP0_ADDRESS_P_MIRROR 0x00000001 +#define NVCB97_TEXSAMP0_ADDRESS_P_CLAMP_TO_EDGE 0x00000002 +#define NVCB97_TEXSAMP0_ADDRESS_P_BORDER 0x00000003 +#define NVCB97_TEXSAMP0_ADDRESS_P_CLAMP_OGL 0x00000004 +#define NVCB97_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVCB97_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_BORDER 0x00000006 +#define NVCB97_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE 9:9 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC 12:10 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_NEVER 0x00000000 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_LESS 0x00000001 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_EQUAL 0x00000002 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_LEQUAL 0x00000003 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_GREATER 0x00000004 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_NOTEQUAL 0x00000005 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_GEQUAL 0x00000006 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_ALWAYS 0x00000007 +#define NVCB97_TEXSAMP0_S_R_G_B_CONVERSION 13:13 +#define NVCB97_TEXSAMP0_RESERVED0A 16:14 +#define NVCB97_TEXSAMP0_RESERVED0B 19:17 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY 22:20 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXSAMP0_FORCED_INVALID 31:31 +#define NVCB97_TEXSAMP1_MAG_FILTER 2:0 +#define NVCB97_TEXSAMP1_MAG_FILTER_MAG_POINT 0x00000001 +#define NVCB97_TEXSAMP1_MAG_FILTER_MAG_LINEAR 0x00000002 +#define NVCB97_TEXSAMP1_MAG_FILTER_VCAA_4_TAP 0x00000003 +#define NVCB97_TEXSAMP1_MAG_FILTER_VCAA_8_TAP 0x00000004 +#define NVCB97_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP 3:3 +#define NVCB97_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP_INTEGER_AND_FRACTION 0x00000000 +#define NVCB97_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP_INTEGER_ONLY 0x00000001 +#define NVCB97_TEXSAMP1_MIN_FILTER 5:4 +#define NVCB97_TEXSAMP1_MIN_FILTER_MIN_POINT 0x00000001 +#define NVCB97_TEXSAMP1_MIN_FILTER_MIN_LINEAR 0x00000002 +#define NVCB97_TEXSAMP1_MIN_FILTER_MIN_ANISO 0x00000003 +#define NVCB97_TEXSAMP1_MIP_FILTER 7:6 +#define NVCB97_TEXSAMP1_MIP_FILTER_MIP_NONE 0x00000001 +#define NVCB97_TEXSAMP1_MIP_FILTER_MIP_POINT 0x00000002 +#define NVCB97_TEXSAMP1_MIP_FILTER_MIP_LINEAR 0x00000003 +#define NVCB97_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING 9:8 +#define NVCB97_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_USE_WRAP 0x00000000 +#define NVCB97_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_OVERRIDE_WRAP 0x00000001 +#define NVCB97_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_AUTO_SPAN_SEAM 0x00000002 +#define NVCB97_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_AUTO_CROSS_SEAM 0x00000003 +#define NVCB97_TEXSAMP1_REDUCTION_FILTER 11:10 +#define NVCB97_TEXSAMP1_REDUCTION_FILTER_RED_NONE 0x00000000 +#define NVCB97_TEXSAMP1_REDUCTION_FILTER_RED_MINIMUM 0x00000001 +#define NVCB97_TEXSAMP1_REDUCTION_FILTER_RED_MAXIMUM 0x00000002 +#define NVCB97_TEXSAMP1_MIP_LOD_BIAS 24:12 +#define NVCB97_TEXSAMP1_FLOAT_COORD_NORMALIZATION 25:25 +#define NVCB97_TEXSAMP1_FLOAT_COORD_NORMALIZATION_USE_HEADER_SETTING 0x00000000 +#define NVCB97_TEXSAMP1_FLOAT_COORD_NORMALIZATION_FORCE_UNNORMALIZED_COORDS 0x00000001 +#define NVCB97_TEXSAMP1_TRILIN_OPT 30:26 +#define NVCB97_TEXSAMP2_MIN_LOD_CLAMP 11:0 +#define NVCB97_TEXSAMP2_MAX_LOD_CLAMP 23:12 +#define NVCB97_TEXSAMP2_S_R_G_B_BORDER_COLOR_R 31:24 +#define NVCB97_TEXSAMP3_RESERVED12 11:0 +#define NVCB97_TEXSAMP3_S_R_G_B_BORDER_COLOR_G 19:12 +#define NVCB97_TEXSAMP3_S_R_G_B_BORDER_COLOR_B 27:20 +#define NVCB97_TEXSAMP4_BORDER_COLOR_R 31:0 +#define NVCB97_TEXSAMP5_BORDER_COLOR_G 31:0 +#define NVCB97_TEXSAMP6_BORDER_COLOR_B 31:0 +#define NVCB97_TEXSAMP7_BORDER_COLOR_A 31:0 + + + +#endif // #ifndef __CLCB97TEX_H__ diff --git a/userspace/sdks/nv570/inc/class/clcba2.h b/userspace/sdks/nv570/inc/class/clcba2.h new file mode 100644 index 0000000..1917abf --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcba2.h @@ -0,0 +1,159 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _clcba2_h_ +#define _clcba2_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define HOPPER_SEC2_WORK_LAUNCH_A (0x0000CBA2) + +typedef volatile struct _clcba2_tag0 { + NvV32 Reserved00[0x100]; + NvV32 DecryptCopySrcAddrHi; // 0x00000400 - 0x00000403 + NvV32 DecryptCopySrcAddrLo; // 0x00000404 - 0x00000407 + NvV32 DecryptCopyDstAddrHi; // 0x00000408 - 0x0000040B + NvV32 DecryptCopyDstAddrLo; // 0x0000040c - 0x0000040F + NvU32 DecryptCopySize; // 0x00000410 - 0x00000413 + NvU32 DecryptCopyAuthTagAddrHi; // 0x00000414 - 0x00000417 + NvU32 DecryptCopyAuthTagAddrLo; // 0x00000418 - 0x0000041B + NvV32 DigestAddrHi; // 0x0000041C - 0x0000041F + NvV32 DigestAddrLo; // 0x00000420 - 0x00000423 + NvV32 Reserved01[0x7]; + NvV32 SemaphoreA; // 0x00000440 - 0x00000443 + NvV32 SemaphoreB; // 0x00000444 - 0x00000447 + NvV32 SemaphoreSetPayloadLower; // 0x00000448 - 0x0000044B + NvV32 SemaphoreSetPayloadUppper; // 0x0000044C - 0x0000044F + NvV32 SemaphoreD; // 0x00000450 - 0x00000453 + NvU32 Reserved02[0x7]; + NvV32 Execute; // 0x00000470 - 0x00000473 + NvV32 Reserved03[0x23]; +} NVCBA2_HOPPER_SEC2_WORK_LAUNCH_AControlPio; + +#define NVCBA2_DECRYPT_COPY_SRC_ADDR_HI (0x00000400) +#define NVCBA2_DECRYPT_COPY_SRC_ADDR_HI_DATA 24:0 +#define NVCBA2_DECRYPT_COPY_SRC_ADDR_LO (0x00000404) +#define NVCBA2_DECRYPT_COPY_SRC_ADDR_LO_DATA 31:4 +#define NVCBA2_DECRYPT_COPY_DST_ADDR_HI (0x00000408) +#define NVCBA2_DECRYPT_COPY_DST_ADDR_HI_DATA 24:0 +#define NVCBA2_DECRYPT_COPY_DST_ADDR_LO (0x0000040c) +#define NVCBA2_DECRYPT_COPY_DST_ADDR_LO_DATA 31:4 +#define NVCBA2_DECRYPT_COPY_SIZE (0x00000410) +#define NVCBA2_DECRYPT_COPY_SIZE_DATA 31:2 +#define NVCBA2_DECRYPT_COPY_AUTH_TAG_ADDR_HI (0x00000414) +#define NVCBA2_DECRYPT_COPY_AUTH_TAG_ADDR_HI_DATA 24:0 +#define NVCBA2_DECRYPT_COPY_AUTH_TAG_ADDR_LO (0x00000418) +#define NVCBA2_DECRYPT_COPY_AUTH_TAG_ADDR_LO_DATA 31:4 +#define NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_HI (0x0000041C) +#define NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_HI_DATA 24:0 +#define NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_LO (0x00000420) +#define NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_LO_DATA 31:4 +#define NVCBA2_SEMAPHORE_A (0x00000440) +#define NVCBA2_SEMAPHORE_A_UPPER 24:0 +#define NVCBA2_SEMAPHORE_B (0x00000444) +#define NVCBA2_SEMAPHORE_B_LOWER 31:2 +#define NVCBA2_SET_SEMAPHORE_PAYLOAD_LOWER (0x00000448) +#define NVCBA2_SET_SEMAPHORE_PAYLOAD_LOWER_DATA 31:0 +#define NVCBA2_SET_SEMAPHORE_PAYLOAD_UPPER (0x0000044C) +#define NVCBA2_SET_SEMAPHORE_PAYLOAD_UPPER_DATA 31:0 +#define NVCBA2_SEMAPHORE_D (0x00000450) +#define NVCBA2_SEMAPHORE_D_NOTIFY_INTR 0:0 +#define NVCBA2_SEMAPHORE_D_NOTIFY_INTR_DISABLE (0x00000000) +#define NVCBA2_SEMAPHORE_D_NOTIFY_INTR_ENABLE (0x00000001) +#define NVCBA2_SEMAPHORE_D_PAYLOAD_SIZE 1:1 +#define NVCBA2_SEMAPHORE_D_PAYLOAD_SIZE_32_BIT (0x00000000) +#define NVCBA2_SEMAPHORE_D_PAYLOAD_SIZE_64_BIT (0x00000001) +#define NVCBA2_SEMAPHORE_D_TIMESTAMP 2:2 +#define NVCBA2_SEMAPHORE_D_TIMESTAMP_DISABLE (0x00000000) +#define NVCBA2_SEMAPHORE_D_TIMESTAMP_ENABLE (0x00000001) +#define NVCBA2_SEMAPHORE_D_FLUSH_DISABLE 3:3 +#define NVCBA2_SEMAPHORE_D_FLUSH_DISABLE_FALSE (0x00000000) +#define NVCBA2_SEMAPHORE_D_FLUSH_DISABLE_TRUE (0x00000001) +#define NVCBA2_EXECUTE (0x00000470) +#define NVCBA2_EXECUTE_NOTIFY 0:0 +#define NVCBA2_EXECUTE_NOTIFY_DISABLE (0x00000000) +#define NVCBA2_EXECUTE_NOTIFY_ENABLE (0x00000001) +#define NVCBA2_EXECUTE_NOTIFY_ON 1:1 +#define NVCBA2_EXECUTE_NOTIFY_ON_END (0x00000000) +#define NVCBA2_EXECUTE_NOTIFY_ON_BEGIN (0x00000001) +#define NVCBA2_EXECUTE_FLUSH_DISABLE 2:2 +#define NVCBA2_EXECUTE_FLUSH_DISABLE_FALSE (0x00000000) +#define NVCBA2_EXECUTE_FLUSH_DISABLE_TRUE (0x00000001) +#define NVCBA2_EXECUTE_NOTIFY_INTR 3:3 +#define NVCBA2_EXECUTE_NOTIFY_INTR_DISABLE (0x00000000) +#define NVCBA2_EXECUTE_NOTIFY_INTR_ENABLE (0x00000001) +#define NVCBA2_EXECUTE_PAYLOAD_SIZE 4:4 +#define NVCBA2_EXECUTE_PAYLOAD_SIZE_32_BIT (0x00000000) +#define NVCBA2_EXECUTE_PAYLOAD_SIZE_64_BIT (0x00000001) +#define NVCBA2_EXECUTE_TIMESTAMP 5:5 +#define NVCBA2_EXECUTE_TIMESTAMP_DISABLE (0x00000000) +#define NVCBA2_EXECUTE_TIMESTAMP_ENABLE (0x00000001) +#define NVCBA2_EXECUTE_PHYSICAL_SCRUBBER 6:6 +#define NVCBA2_EXECUTE_PHYSICAL_SCRUBBER_DISABLE (0x00000000) +#define NVCBA2_EXECUTE_PHYSICAL_SCRUBBER_ENABLE (0x00000001) + +// Class definitions +#define NVCBA2_DECRYPT_COPY_SIZE_MAX_BYTES (2*1024*1024) +#define NVCBA2_DECRYPT_SCRUB_SIZE_MAX_BYTES (1024*1024*1024) + +// Errors +#define NVCBA2_ERROR_NONE (0x00000000) +#define NVCBA2_ERROR_DECRYPT_COPY_SRC_ADDR_MISALIGNED_POINTER (0x00000001) +#define NVCBA2_ERROR_DECRYPT_COPY_DEST_ADDR_MISALIGNED_POINTER (0x00000002) +#define NVCBA2_ERROR_DECRYPT_COPY_AUTH_TAG_ADDR_MISALIGNED_POINTER (0x00000003) +#define NVCBA2_ERROR_DECRYPT_COPY_DMA_NACK (0x00000004) +#define NVCBA2_ERROR_DECRYPT_COPY_AUTH_TAG_MISMATCH (0x00000005) +#define NVCBA2_ERROR_METHOD_STREAM_AUTH_TAG_ADDR_MISALIGNED_POINTER (0x00000006) +#define NVCBA2_ERROR_METHOD_STREAM_AUTH_TAG_ADDR_DMA_NACK (0x00000007) +#define NVCBA2_ERROR_METHOD_STREAM_AUTH_TAG_CHECK_FAILURE (0x00000008) +#define NVCBA2_ERROR_MISALIGNED_SIZE (0x00000009) +#define NVCBA2_ERROR_MISSING_METHODS (0x0000000A) +#define NVCBA2_ERROR_SEMAPHORE_RELEASE_DMA_NACK (0x0000000B) +#define NVCBA2_ERROR_DECRYPT_SIZE_MAX_EXCEEDED (0x0000000C) +#define NVCBA2_ERROR_OS_APPLICATION (0x0000000D) +#define NVCBA2_ERROR_INVALID_CTXSW_REQUEST (0x0000000E) +#define NVCBA2_ERROR_BUFFER_OVERFLOW (0x0000000F) +#define NVCBA2_ERROR_IV_OVERFLOW (0x00000010) +#define NVCBA2_ERROR_INTERNAL_SETUP_FAILURE (0x00000011) +#define NVCBA2_ERROR_DECRYPT_COPY_INTERNAL_DMA_FAILURE (0x00000012) +#define NVCBA2_ERROR_METHOD_STREAM_AUTH_TAG_ADDR_INTERNAL_DMA_FAILURE (0x00000013) +#define NVCBA2_ERROR_METHOD_STREAM_AUTH_TAG_HMAC_CALC_FAILURE (0x00000014) +#define NVCBA2_ERROR_NONCE_OVERFLOW (0x00000015) +#define NVCBA2_ERROR_AES_GCM_DECRYPTION_FAILURE (0x00000016) +#define NVCBA2_ERROR_SEMAPHORE_RELEASE_INTERNAL_DMA_FAILURE (0x00000017) +#define NVCBA2_ERROR_KEY_DERIVATION_FAILURE (0x00000018) +#define NVCBA2_ERROR_SCRUBBER_FAILURE (0x00000019) +#define NVCBA2_ERROR_SCRUBBER_INVALD_ADDRESS (0x0000001a) +#define NVCBA2_ERROR_SCRUBBER_INSUFFICIENT_PERMISSIONS (0x0000001b) +#define NVCBA2_ERROR_SCRUBBER_MUTEX_ACQUIRE_FAILURE (0x0000001c) +#define NVCBA2_ERROR_SCRUB_SIZE_MAX_EXCEEDED (0x0000001d) +#define NVCBA2_ERROR_SIZE_ZERO (0x0000001e) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clcba2_h diff --git a/userspace/sdks/nv570/inc/class/clcbc0.h b/userspace/sdks/nv570/inc/class/clcbc0.h new file mode 100644 index 0000000..bed5e94 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcbc0.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clcbc0_h__ +#define __gh100_clcbc0_h__ +#define HOPPER_COMPUTE_A 0xCBC0 +#endif // __gh100_clcbc0_h__ diff --git a/userspace/sdks/nv570/inc/class/clcbca.h b/userspace/sdks/nv570/inc/class/clcbca.h new file mode 100644 index 0000000..4570cc9 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcbca.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _CLCBCA_H_ +#define _CLCBCA_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV_COUNTER_COLLECTION_UNIT (0x0000CBCA) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _CLCBCA_H_ diff --git a/userspace/sdks/nv570/inc/class/clcc70.h b/userspace/sdks/nv570/inc/class/clcc70.h new file mode 100644 index 0000000..79aeafc --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcc70.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2024, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clcc70.finn +// + +#define NVCC70_DISPLAY (0xcc70U) /* finn: Evaluated from "NVCC70_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NVCC70_ALLOCATION_PARAMETERS_MESSAGE_ID (0xcc70U) + +typedef struct NVCC70_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numDsis; // Number of DSIs in this chip/display +} NVCC70_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clcc71.h b/userspace/sdks/nv570/inc/class/clcc71.h new file mode 100644 index 0000000..0520145 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcc71.h @@ -0,0 +1,186 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clcc71_h_ +#define _clcc71_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVCC71_DISP_SF_USER (0x000CC71) + +typedef volatile struct _clcc71_tag0 { + NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x000D0FFF:0x000D0000 */ +} _NvCC71DispSfUser, NvCC71DispSfUserMap; + +#define NVCC71_SF_HDMI_INFO_CTRL(i,j) (0x000E0000-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVCC71_SF_HDMI_INFO_CTRL__SIZE_1 8 /* */ +#define NVCC71_SF_HDMI_INFO_CTRL__SIZE_2 3 /* */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x000E0000-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 8 /* */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW 9:9 /* RWIVF */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_STATUS(i) (0x000E0004-0x000E0000+(i)*1024) /* R--4A */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1 8 /* */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT 0:0 /* R-IVF */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT 0x00000000 /* R-I-V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x000E0008-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 8 /* */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x000E000C-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 8 /* */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x000E0010-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 8 /* */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x000E0014-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 8 /* */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x000E0018-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 8 /* */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW(i) (0x000E001C-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW__SIZE_1 8 /* */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NVCC71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL(i,j) (0x000E0130-0x000E0000+(i)*1024+(j)*8) /* RW-4A */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL__SIZE_1 8 /* */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL__SIZE_2 10 /* */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE 3:1 /* RWIVF */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_ALWAYS 0x00000000 /* RWI-V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_ONCE 0x00000001 /* RW--V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_ALWAYS 0x00000002 /* RW--V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_ONCE 0x00000003 /* RW--V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_TRIGGER 0x00000004 /* RW--V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_LOC 5:4 /* RWIVF */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_LOC_VBLANK 0x00000000 /* RWI-V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_LOC_VSYNC 0x00000001 /* RW--V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_LOC_LINE 0x00000002 /* RW--V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_OFFSET 10:6 /* RWIVF */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_SIZE 18:14 /* RWIVF */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_SIZE_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_BUSY 22:22 /* R-IVF */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_BUSY_NO 0x00000000 /* R-I-V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_BUSY_YES 0x00000001 /* R---V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_SENT 23:23 /* RWIVF */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_SENT_NO 0x00000000 /* R-I-V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_SENT_YES 0x00000001 /* R---V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CTRL_SENT_CLEAR 0x00000001 /* -W--C */ +#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG(i,j) (0x000E0134-0x000E0000+(i)*1024+(j)*8) /* RW-4A */ +#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG__SIZE_1 8 /* */ +#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG__SIZE_2 10 /* */ +#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_FID 7:0 /* RWIVF */ +#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_FID_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID 23:8 /* RWIVF */ +#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED 24:24 /* RWIVF */ +#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED_NO 0x00000000 /* RWI-V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED_YES 0x00000001 /* RW--V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN 25:25 /* RWIVF */ +#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN_NO 0x00000000 /* RWI-V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN_YES 0x00000001 /* RW--V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM 29:29 /* RWIVF */ +#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM_NO 0x00000000 /* RWI-V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM_YES 0x00000001 /* RW--V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_NEW 30:30 /* RWIVF */ +#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_NEW_INIT 0x00000000 /* R-I-V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_NEW_DONE 0x00000000 /* R---V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_NEW_PENDING 0x00000001 /* R---T */ +#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_NEW_TRIGGER 0x00000001 /* -W--T */ +#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL 31:31 /* RWIVF */ +#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL_ACT 0x00000000 /* RWI-V */ +#define NVCC71_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL_ARM 0x00000001 /* RW--V */ +#define NVCC71_SF_GENERIC_INFOFRAME_DATA_CTRL(i) (0x000E03F0-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCC71_SF_GENERIC_INFOFRAME_DATA_CTRL__SIZE_1 8 /* */ +#define NVCC71_SF_GENERIC_INFOFRAME_DATA_CTRL_OFFSET 4:0 /* RWIVF */ +#define NVCC71_SF_GENERIC_INFOFRAME_DATA_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_GENERIC_INFOFRAME_DATA(i) (0x000E03F4-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCC71_SF_GENERIC_INFOFRAME_DATA__SIZE_1 8 /* */ +#define NVCC71_SF_GENERIC_INFOFRAME_DATA_BYTE0 7:0 /* RWIVF */ +#define NVCC71_SF_GENERIC_INFOFRAME_DATA_BYTE0_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_GENERIC_INFOFRAME_DATA_BYTE1 15:8 /* RWIVF */ +#define NVCC71_SF_GENERIC_INFOFRAME_DATA_BYTE1_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_GENERIC_INFOFRAME_DATA_BYTE2 23:16 /* RWIVF */ +#define NVCC71_SF_GENERIC_INFOFRAME_DATA_BYTE2_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_GENERIC_INFOFRAME_DATA_BYTE3 31:24 /* RWIVF */ +#define NVCC71_SF_GENERIC_INFOFRAME_DATA_BYTE3_INIT 0x00000000 /* RWI-V */ +#define NVCC71_SF_GENERIC_INFOFRAME_MISC_CTRL(i) (0x000E03F8-0x000E0000+(i)*1024) /* RW-4A */ +#define NVCC71_SF_GENERIC_INFOFRAME_MISC_CTRL__SIZE_1 8 /* */ +#define NVCC71_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY 1:1 /* RWIVF */ +#define NVCC71_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY_HIGH 0x00000000 /* RW--V */ +#define NVCC71_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY_LOW 0x00000001 /* RWI-V */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _clcc71_h_ diff --git a/userspace/sdks/nv570/inc/class/clcc73.h b/userspace/sdks/nv570/inc/class/clcc73.h new file mode 100644 index 0000000..306ae29 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcc73.h @@ -0,0 +1,915 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clcc73_h_ +#define _clcc73_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVCC73_DISP_CAPABILITIES 0xCC73 + +typedef volatile struct _clcc73_tag0 { + NvU32 dispCapabilities[0x400]; +} _NvCC73DispCapabilities,NvCC73DispCapabilities_Map ; + + +#define NVCC73_SYS_CAP 0x0 /* RW-4R */ +#define NVCC73_SYS_CAP_HEAD0_EXISTS 0:0 /* RWIVF */ +#define NVCC73_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAP_HEAD1_EXISTS 1:1 /* RWIVF */ +#define NVCC73_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAP_HEAD2_EXISTS 2:2 /* RWIVF */ +#define NVCC73_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAP_HEAD3_EXISTS 3:3 /* RWIVF */ +#define NVCC73_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAP_HEAD4_EXISTS 4:4 /* RWIVF */ +#define NVCC73_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAP_HEAD5_EXISTS 5:5 /* RWIVF */ +#define NVCC73_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAP_HEAD6_EXISTS 6:6 /* RWIVF */ +#define NVCC73_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAP_HEAD7_EXISTS 7:7 /* RWIVF */ +#define NVCC73_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVCC73_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */ +#define NVCC73_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAP_SOR0_EXISTS 8:8 /* RWIVF */ +#define NVCC73_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAP_SOR1_EXISTS 9:9 /* RWIVF */ +#define NVCC73_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAP_SOR2_EXISTS 10:10 /* RWIVF */ +#define NVCC73_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAP_SOR3_EXISTS 11:11 /* RWIVF */ +#define NVCC73_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAP_SOR4_EXISTS 12:12 /* RWIVF */ +#define NVCC73_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAP_SOR5_EXISTS 13:13 /* RWIVF */ +#define NVCC73_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAP_SOR6_EXISTS 14:14 /* RWIVF */ +#define NVCC73_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAP_SOR7_EXISTS 15:15 /* RWIVF */ +#define NVCC73_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* RWIVF */ +#define NVCC73_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */ +#define NVCC73_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAP_RISCV0_EXISTS 16:16 /* RWIVF */ +#define NVCC73_SYS_CAP_RISCV0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAP_RISCV0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAP_DSI0_EXISTS 20:20 /* RWIVF */ +#define NVCC73_SYS_CAP_DSI0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAP_DSI0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAP_DSI1_EXISTS 21:21 /* RWIVF */ +#define NVCC73_SYS_CAP_DSI1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAP_DSI1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAP_DSI2_EXISTS 22:22 /* RWIVF */ +#define NVCC73_SYS_CAP_DSI2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAP_DSI2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAP_DSI3_EXISTS 23:23 /* RWIVF */ +#define NVCC73_SYS_CAP_DSI3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAP_DSI3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAP_DSI_EXISTS(i) (20+(i)):(20+(i)) /* RWIVF */ +#define NVCC73_SYS_CAP_DSI_EXISTS__SIZE_1 4 /* */ +#define NVCC73_SYS_CAP_DSI_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAP_DSI_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB 0x4 /* RW-4R */ +#define NVCC73_SYS_CAPB_WINDOW0_EXISTS 0:0 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW1_EXISTS 1:1 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW2_EXISTS 2:2 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW3_EXISTS 3:3 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW4_EXISTS 4:4 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW5_EXISTS 5:5 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW6_EXISTS 6:6 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW7_EXISTS 7:7 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW8_EXISTS 8:8 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW8_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW8_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW9_EXISTS 9:9 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW9_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW9_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW10_EXISTS 10:10 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW10_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW10_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW11_EXISTS 11:11 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW11_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW11_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW12_EXISTS 12:12 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW12_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW12_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW13_EXISTS 13:13 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW13_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW13_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW14_EXISTS 14:14 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW14_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW14_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW15_EXISTS 15:15 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW15_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW15_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW16_EXISTS 16:16 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW16_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW16_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW17_EXISTS 17:17 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW17_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW17_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW18_EXISTS 18:18 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW18_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW18_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW19_EXISTS 19:19 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW19_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW19_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW20_EXISTS 20:20 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW20_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW20_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW21_EXISTS 21:21 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW21_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW21_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW22_EXISTS 22:22 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW22_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW22_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW23_EXISTS 23:23 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW23_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW23_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW24_EXISTS 24:24 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW24_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW24_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW25_EXISTS 25:25 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW25_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW25_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW26_EXISTS 26:26 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW26_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW26_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW27_EXISTS 27:27 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW27_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW27_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW28_EXISTS 28:28 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW28_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW28_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW29_EXISTS 29:29 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW29_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW29_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW30_EXISTS 30:30 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW30_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW30_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW31_EXISTS 31:31 /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW31_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW31_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVCC73_SYS_CAPB_WINDOW_EXISTS__SIZE_1 32 /* */ +#define NVCC73_SYS_CAPB_WINDOW_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPB_WINDOW_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPC 0x20 /* RW-4R */ +#define NVCC73_SYS_CAPC_TILE0_EXISTS 0:0 /* RWIVF */ +#define NVCC73_SYS_CAPC_TILE0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE1_EXISTS 1:1 /* RWIVF */ +#define NVCC73_SYS_CAPC_TILE1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE2_EXISTS 2:2 /* RWIVF */ +#define NVCC73_SYS_CAPC_TILE2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE3_EXISTS 3:3 /* RWIVF */ +#define NVCC73_SYS_CAPC_TILE3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE4_EXISTS 4:4 /* RWIVF */ +#define NVCC73_SYS_CAPC_TILE4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE5_EXISTS 5:5 /* RWIVF */ +#define NVCC73_SYS_CAPC_TILE5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE6_EXISTS 6:6 /* RWIVF */ +#define NVCC73_SYS_CAPC_TILE6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE7_EXISTS 7:7 /* RWIVF */ +#define NVCC73_SYS_CAPC_TILE7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVCC73_SYS_CAPC_TILE_EXISTS__SIZE_1 8 /* */ +#define NVCC73_SYS_CAPC_TILE_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE0_SUPPORT_MULTI_TILE 8:8 /* RWIVF */ +#define NVCC73_SYS_CAPC_TILE0_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE0_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE1_SUPPORT_MULTI_TILE 9:9 /* RWIVF */ +#define NVCC73_SYS_CAPC_TILE1_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE1_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE2_SUPPORT_MULTI_TILE 10:10 /* RWIVF */ +#define NVCC73_SYS_CAPC_TILE2_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE2_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE3_SUPPORT_MULTI_TILE 11:11 /* RWIVF */ +#define NVCC73_SYS_CAPC_TILE3_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE3_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE4_SUPPORT_MULTI_TILE 12:12 /* RWIVF */ +#define NVCC73_SYS_CAPC_TILE4_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE4_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE5_SUPPORT_MULTI_TILE 13:13 /* RWIVF */ +#define NVCC73_SYS_CAPC_TILE5_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE5_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE6_SUPPORT_MULTI_TILE 14:14 /* RWIVF */ +#define NVCC73_SYS_CAPC_TILE6_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE6_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE7_SUPPORT_MULTI_TILE 15:15 /* RWIVF */ +#define NVCC73_SYS_CAPC_TILE7_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE7_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE(i) (8+(i)):(8+(i)) /* RWIVF */ +#define NVCC73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE__SIZE_1 8 /* */ +#define NVCC73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPC_MERGER_TILE_BUFFER_SIZE 31:16 /* RWIUF */ +#define NVCC73_SYS_CAPD 0x2c /* RW-4R */ +#define NVCC73_SYS_CAPD_NUM_TELLTALE_REGIONS 4:0 /* RWIUF */ +#define NVCC73_SYS_CAPD_NUM_FROZEN_FRAME_REGIONS 12:8 /* RWIUF */ +#define NVCC73_SYS_CAPD_NUM_ROI 20:16 /* RWIUF */ +#define NVCC73_SYS_CAPD_AE_SDP_EXISTS 30:30 /* RWIVF */ +#define NVCC73_SYS_CAPD_AE_SDP_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPD_AE_SDP_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPD_AMSS_EXISTS 31:31 /* RWIVF */ +#define NVCC73_SYS_CAPD_AMSS_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPD_AMSS_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE 0x34 /* RW-4R */ +#define NVCC73_SYS_CAPE_VIRWIN0_EXISTS 0:0 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN1_EXISTS 1:1 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN2_EXISTS 2:2 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN3_EXISTS 3:3 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN4_EXISTS 4:4 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN5_EXISTS 5:5 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN6_EXISTS 6:6 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN7_EXISTS 7:7 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN8_EXISTS 8:8 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN8_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN8_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN9_EXISTS 9:9 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN9_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN9_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN10_EXISTS 10:10 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN10_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN10_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN11_EXISTS 11:11 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN11_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN11_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN12_EXISTS 12:12 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN12_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN12_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN13_EXISTS 13:13 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN13_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN13_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN14_EXISTS 14:14 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN14_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN14_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN15_EXISTS 15:15 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN15_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN15_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN16_EXISTS 16:16 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN16_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN16_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN17_EXISTS 17:17 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN17_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN17_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN18_EXISTS 18:18 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN18_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN18_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN19_EXISTS 19:19 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN19_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN19_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN20_EXISTS 20:20 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN20_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN20_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN21_EXISTS 21:21 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN21_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN21_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN22_EXISTS 22:22 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN22_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN22_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN23_EXISTS 23:23 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN23_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN23_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN24_EXISTS 24:24 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN24_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN24_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN25_EXISTS 25:25 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN25_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN25_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN26_EXISTS 26:26 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN26_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN26_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN27_EXISTS 27:27 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN27_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN27_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN28_EXISTS 28:28 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN28_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN28_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN29_EXISTS 29:29 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN29_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN29_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN30_EXISTS 30:30 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN30_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN30_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN31_EXISTS 31:31 /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN31_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN31_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVCC73_SYS_CAPE_VIRWIN_EXISTS__SIZE_1 32 /* */ +#define NVCC73_SYS_CAPE_VIRWIN_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_SYS_CAPE_VIRWIN_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_MISC_CAPA_NUM_VMS 17:13 /* RWIUF */ +#define NVCC73_LINK_CAP 0x30 /* RW-4R */ +#define NVCC73_LINK_CAP_PHYCTRL0_EXISTS 0:0 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL1_EXISTS 1:1 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL2_EXISTS 2:2 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL3_EXISTS 3:3 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL4_EXISTS 4:4 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL5_EXISTS 5:5 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL6_EXISTS 6:6 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL7_EXISTS 7:7 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL8_EXISTS 8:8 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL8_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL8_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL9_EXISTS 9:9 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL9_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL9_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL10_EXISTS 10:10 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL10_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL10_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL11_EXISTS 11:11 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL11_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL11_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL12_EXISTS 12:12 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL12_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL12_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL13_EXISTS 13:13 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL13_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL13_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL14_EXISTS 14:14 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL14_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL14_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL15_EXISTS 15:15 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL15_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL15_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL16_EXISTS 16:16 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL16_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL16_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL17_EXISTS 17:17 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL17_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL17_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL18_EXISTS 18:18 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL18_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL18_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL19_EXISTS 19:19 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL19_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL19_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL20_EXISTS 20:20 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL20_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL20_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL21_EXISTS 21:21 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL21_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL21_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL22_EXISTS 22:22 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL22_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL22_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL23_EXISTS 23:23 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL23_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL23_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL24_EXISTS 24:24 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL24_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL24_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL25_EXISTS 25:25 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL25_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL25_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL26_EXISTS 26:26 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL26_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL26_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL27_EXISTS 27:27 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL27_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL27_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL28_EXISTS 28:28 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL28_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL28_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL29_EXISTS 29:29 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL29_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL29_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL30_EXISTS 30:30 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL30_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL30_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL31_EXISTS 31:31 /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL31_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL31_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVCC73_LINK_CAP_PHYCTRL_EXISTS__SIZE_1 32 /* */ +#define NVCC73_LINK_CAP_PHYCTRL_EXISTS_NO 0x00000000 /* RW--V */ +#define NVCC73_LINK_CAP_PHYCTRL_EXISTS_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPA 0x10 /* RW-4R */ +#define NVCC73_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES 15:0 /* RWIUF */ +#define NVCC73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH 17:16 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B 0x00000002 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B 0x00000003 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_ROTATION 18:18 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_ROTATION_FALSE 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_ROTATION_TRUE 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_PLANAR 19:19 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_PLANAR_FALSE 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_PLANAR_TRUE 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_VGA 20:20 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION 21:21 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_FALSE 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_TRUE 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_MSCG 22:22 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_MSCG_FALSE 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_MSCG_TRUE 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH 23:23 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_FALSE 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_TRUE 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_MSCG_LPS 26:26 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_MSCG_LPS_FALSE 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPA_SUPPORT_MSCG_LPS_TRUE 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION 31:30 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B 0x00000002 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B 0x00000003 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPC 0x18 /* RW-4R */ +#define NVCC73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE 1:0 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_32B 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_64B 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_128B 0x00000002 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_256B 0x00000003 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED 6:4 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_NONE 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_TWO 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_FOUR 0x00000002 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_EIGHT 0x00000003 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_SIXTEEN 0x00000004 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR 11:11 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_FALSE 0x00000000 /* RWI-V */ +#define NVCC73_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_TRUE 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP 12:12 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_FALSE 0x00000000 /* RWI-V */ +#define NVCC73_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_TRUE 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPC_SUPPORT_MEMPOOL_YUV_COMPRESSION 13:13 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPC_SUPPORT_MEMPOOL_YUV_COMPRESSION_FALSE 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPC_SUPPORT_MEMPOOL_YUV_COMPRESSION_TRUE 0x00000001 /* RWI-V */ +#define NVCC73_IHUB_COMMON_CAPE 0x24 /* RW-4R */ +#define NVCC73_IHUB_COMMON_CAPE_PHYWIN_BUFFER_SIZE 15:0 /* RWIUF */ +#define NVCC73_IHUB_COMMON_CAPF 0x28 /* RW-4R */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN0_SUPPORT_MULTI_TILE 0:0 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN0_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN0_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN1_SUPPORT_MULTI_TILE 1:1 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN1_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN1_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN2_SUPPORT_MULTI_TILE 2:2 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN2_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN2_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN3_SUPPORT_MULTI_TILE 3:3 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN3_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN3_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN4_SUPPORT_MULTI_TILE 4:4 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN4_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN4_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN5_SUPPORT_MULTI_TILE 5:5 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN5_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN5_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN6_SUPPORT_MULTI_TILE 6:6 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN6_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN6_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN7_SUPPORT_MULTI_TILE 7:7 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN7_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN7_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN8_SUPPORT_MULTI_TILE 8:8 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN8_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN8_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN9_SUPPORT_MULTI_TILE 9:9 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN9_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN9_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN10_SUPPORT_MULTI_TILE 10:10 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN10_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN10_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN11_SUPPORT_MULTI_TILE 11:11 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN11_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN11_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN12_SUPPORT_MULTI_TILE 12:12 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN12_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN12_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN13_SUPPORT_MULTI_TILE 13:13 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN13_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN13_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN14_SUPPORT_MULTI_TILE 14:14 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN14_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN14_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN15_SUPPORT_MULTI_TILE 15:15 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN15_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN15_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN16_SUPPORT_MULTI_TILE 16:16 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN16_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN16_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN17_SUPPORT_MULTI_TILE 17:17 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN17_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN17_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN18_SUPPORT_MULTI_TILE 18:18 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN18_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN18_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN19_SUPPORT_MULTI_TILE 19:19 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN19_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN19_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN20_SUPPORT_MULTI_TILE 20:20 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN20_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN20_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN21_SUPPORT_MULTI_TILE 21:21 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN21_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN21_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN22_SUPPORT_MULTI_TILE 22:22 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN22_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN22_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN23_SUPPORT_MULTI_TILE 23:23 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN23_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN23_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN24_SUPPORT_MULTI_TILE 24:24 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN24_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN24_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN25_SUPPORT_MULTI_TILE 25:25 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN25_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN25_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN26_SUPPORT_MULTI_TILE 26:26 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN26_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN26_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN27_SUPPORT_MULTI_TILE 27:27 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN27_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN27_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN28_SUPPORT_MULTI_TILE 28:28 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN28_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN28_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN29_SUPPORT_MULTI_TILE 29:29 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN29_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN29_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN30_SUPPORT_MULTI_TILE 30:30 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN30_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN30_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN31_SUPPORT_MULTI_TILE 31:31 /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN31_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN31_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE__SIZE_1 32 /* */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */ +#define NVCC73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPA(i) (0x680+(i)*32) /* RW-4A */ +#define NVCC73_POSTCOMP_HDR_CAPA__SIZE_1 8 /* */ +#define NVCC73_POSTCOMP_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPA_OCSC0_PRESENT 16:16 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPA_OCSC0_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPA_OCSC0_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPA_OCSC1_PRESENT 17:17 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPA_OCSC1_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPA_OCSC1_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPA_SCLR_PRESENT 18:18 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPA_HCLPF_PRESENT 19:19 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPA_HCLPF_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPA_HCLPF_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPA_DTH_PRESENT 20:20 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPA_DTH_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPA_DTH_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPA_OSCAN_PRESENT 21:21 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPA_OSCAN_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPA_OSCAN_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPA_DSC_PRESENT 22:22 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPA_DSC_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPA_DSC_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPA_VFILTER_PRESENT 23:23 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPA_VFILTER_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPA_VFILTER_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPA_LTM_PRESENT 25:25 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPA_LTM_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPA_LTM_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPB(i) (0x684+(i)*32) /* RW-4A */ +#define NVCC73_POSTCOMP_HDR_CAPB__SIZE_1 8 /* */ +#define NVCC73_POSTCOMP_HDR_CAPB_VGA 0:0 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPB_VGA_TRUE 0x00000001 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPB_VGA_FALSE 0x00000000 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPB_OLUT_SZ 12:1 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPB_OLUT_LOGNR 15:13 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD 17:17 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPB_OLUT_DIRECT 18:18 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPB_OLUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPB_OLUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPC(i) (0x688+(i)*32) /* RW-4A */ +#define NVCC73_POSTCOMP_HDR_CAPC__SIZE_1 8 /* */ +#define NVCC73_POSTCOMP_HDR_CAPC_OCSC0_PRECISION 4:0 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPC_OCSC1_PRECISION 12:8 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP 13:13 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPC_SCLR_SF_PRECISION 20:16 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPC_SCLR_CI_PRECISION 24:21 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB 25:25 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPD(i) (0x68c+(i)*32) /* RW-4A */ +#define NVCC73_POSTCOMP_HDR_CAPD__SIZE_1 8 /* */ +#define NVCC73_POSTCOMP_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPE(i) (0x690+(i)*32) /* RW-4A */ +#define NVCC73_POSTCOMP_HDR_CAPE__SIZE_1 8 /* */ +#define NVCC73_POSTCOMP_HDR_CAPE_DSC_MAXLINEWIDTH 15:0 /* RWIUF */ +#define NVCC73_POSTCOMP_HDR_CAPE_DSC_NATIVE422 16:16 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPE_DSC_NATIVE422_TRUE 0x00000001 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPE_DSC_NATIVE422_FALSE 0x00000000 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPE_DSC_NATIVE420 17:17 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPE_DSC_NATIVE420_TRUE 0x00000001 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPE_DSC_NATIVE420_FALSE 0x00000000 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_PRESENT 18:18 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE 21:19 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_9x9x9 0x00000000 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_17x17x17 0x00000001 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_25x25x25 0x00000002 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_33x33x33 0x00000003 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_4 0x00000004 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_5 0x00000005 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_6 0x00000006 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_7 0x00000007 /* RW--V */ +#define NVCC73_POSTCOMP_HDR_CAPE_3DLUT_NUM_CURVES 23:22 /* RWIUF */ +#define NVCC73_POSTCOMP_HDR_CAPF(i) (0x694+(i)*32) /* RW-4A */ +#define NVCC73_POSTCOMP_HDR_CAPF__SIZE_1 8 /* */ +#define NVCC73_POSTCOMP_HDR_CAPF_VFILTER_MAX_PIXELS 15:0 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPF_LTM_MAX_PIXELS 31:16 /* RWIVF */ +#define NVCC73_POSTCOMP_HDR_CAPG(i) (0x698+(i)*32) /* RW-4A */ +#define NVCC73_POSTCOMP_HDR_CAPG__SIZE_1 8 /* */ +#define NVCC73_POSTCOMP_HDR_CAPG_CMI_SZ 11:0 /* RWIUF */ +#define NVCC73_POSTCOMP_HDR_CAPG_CMI_LOGNR 14:12 /* RWIUF */ +#define NVCC73_POSTCOMP_HDR_CAPG_CMO_SZ 26:15 /* RWIUF */ +#define NVCC73_POSTCOMP_HDR_CAPG_CMO_LOGNR 29:27 /* RWIUF */ +#define NVCC73_SOR_CAP(i) (0x144+(i)*8) /* RW-4A */ +#define NVCC73_SOR_CAP__SIZE_1 8 /* */ +#define NVCC73_SOR_CAP_SINGLE_LVDS_18 0:0 /* RWIVF */ +#define NVCC73_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVCC73_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVCC73_SOR_CAP_SINGLE_LVDS_24 1:1 /* RWIVF */ +#define NVCC73_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVCC73_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVCC73_SOR_CAP_DUAL_LVDS_18 2:2 /* RWIVF */ +#define NVCC73_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVCC73_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVCC73_SOR_CAP_DUAL_LVDS_24 3:3 /* RWIVF */ +#define NVCC73_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVCC73_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVCC73_SOR_CAP_DP_DUAL_MODE 4:4 /* RWIVF */ +#define NVCC73_SOR_CAP_DP_DUAL_MODE_FALSE 0x00000000 /* RW--V */ +#define NVCC73_SOR_CAP_DP_DUAL_MODE_TRUE 0x00000001 /* RW--V */ +#define NVCC73_SOR_CAP_SINGLE_TMDS_A 8:8 /* RWIVF */ +#define NVCC73_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* RW--V */ +#define NVCC73_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* RW--V */ +#define NVCC73_SOR_CAP_SINGLE_TMDS_B 9:9 /* RWIVF */ +#define NVCC73_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* RW--V */ +#define NVCC73_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* RW--V */ +#define NVCC73_SOR_CAP_DUAL_TMDS 11:11 /* RWIVF */ +#define NVCC73_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* RW--V */ +#define NVCC73_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* RW--V */ +#define NVCC73_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* RWIVF */ +#define NVCC73_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* RW--V */ +#define NVCC73_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* RW--V */ +#define NVCC73_SOR_CAP_DP_TUNNELING_OVER_USB4 15:15 /* RWIVF */ +#define NVCC73_SOR_CAP_DP_TUNNELING_OVER_USB4_FALSE 0x00000000 /* RW--V */ +#define NVCC73_SOR_CAP_DP_TUNNELING_OVER_USB4_TRUE 0x00000001 /* RW--V */ +#define NVCC73_SOR_CAP_SDI 16:16 /* RWIVF */ +#define NVCC73_SOR_CAP_SDI_FALSE 0x00000000 /* RW--V */ +#define NVCC73_SOR_CAP_SDI_TRUE 0x00000001 /* RW--V */ +#define NVCC73_SOR_CAP_DP_DUAL_MST 23:23 /* RWIVF */ +#define NVCC73_SOR_CAP_DP_DUAL_MST_FALSE 0x00000000 /* RW--V */ +#define NVCC73_SOR_CAP_DP_DUAL_MST_TRUE 0x00000001 /* RW--V */ +#define NVCC73_SOR_CAP_DP_A 24:24 /* RWIVF */ +#define NVCC73_SOR_CAP_DP_A_FALSE 0x00000000 /* RW--V */ +#define NVCC73_SOR_CAP_DP_A_TRUE 0x00000001 /* RW--V */ +#define NVCC73_SOR_CAP_DP_B 25:25 /* RWIVF */ +#define NVCC73_SOR_CAP_DP_B_FALSE 0x00000000 /* RW--V */ +#define NVCC73_SOR_CAP_DP_B_TRUE 0x00000001 /* RW--V */ +#define NVCC73_SOR_CAP_DP_INTERLACE 26:26 /* RWIVF */ +#define NVCC73_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* RW--V */ +#define NVCC73_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* RW--V */ +#define NVCC73_SOR_CAP_DP_8_LANES 27:27 /* RWIVF */ +#define NVCC73_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* RW--V */ +#define NVCC73_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* RW--V */ +#define NVCC73_SOR_CAP_HDMI_FRL 28:28 /* RWIVF */ +#define NVCC73_SOR_CAP_HDMI_FRL_FALSE 0x00000000 /* RW--V */ +#define NVCC73_SOR_CAP_HDMI_FRL_TRUE 0x00000001 /* RW--V */ +#define NVCC73_SOR_CAP_HDMI_FRL_YUV422 29:29 /* RWIVF */ +#define NVCC73_SOR_CAP_HDMI_FRL_YUV422_FALSE 0x00000000 /* RW--V */ +#define NVCC73_SOR_CAP_HDMI_FRL_YUV422_TRUE 0x00000001 /* RW--V */ +#define NVCC73_SOR_CAP_DP_128B132B 30:30 /* RWIVF */ +#define NVCC73_SOR_CAP_DP_128B132B_FALSE 0x00000000 /* RW--V */ +#define NVCC73_SOR_CAP_DP_128B132B_TRUE 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA(i) (0x780+(i)*32) /* RW-4A */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA__SIZE_1 32 /* */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH 13:10 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT 16:16 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT 17:17 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT 18:18 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT 19:19 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT 20:20 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT 21:21 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT 22:22 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT 23:23 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT 24:24 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPB(i) (0x784+(i)*32) /* RW-4A */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPB__SIZE_1 32 /* */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION 4:0 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ 9:6 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR 12:10 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD 14:14 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT 15:15 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC(i) (0x788+(i)*32) /* RW-4A */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC__SIZE_1 32 /* */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION 4:0 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_FVLUT 13:13 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_FVLUT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_FVLUT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT 15:15 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION 20:16 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP 21:21 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD(i) (0x78c+(i)*32) /* RW-4A */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD__SIZE_1 32 /* */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ 3:0 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR 6:4 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD 8:8 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT 9:9 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION 16:12 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION 20:17 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB 21:21 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA 22:22 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_TRUE 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_FALSE 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE(i) (0x790+(i)*32) /* RW-4A */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE__SIZE_1 32 /* */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION 4:0 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_FVLUT 13:13 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_FVLUT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_FVLUT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT 15:15 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION 20:16 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP 21:21 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPF(i) (0x794+(i)*32) /* RW-4A */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPF__SIZE_1 32 /* */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */ +#define NVCC73_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */ +#define NVCC73_SOR_CLK_CAP(i) (0x608+(i)*4) /* RW-4A */ +#define NVCC73_SOR_CLK_CAP__SIZE_1 8 /* */ +#define NVCC73_SOR_CLK_CAP_DP_MAX 7:0 /* RWIUF */ +#define NVCC73_SOR_CLK_CAP_TMDS_MAX 23:16 /* RWIUF */ +#define NVCC73_SOR_CLK_CAP_LVDS_MAX 31:24 /* RWIUF */ + +#ifdef __cplusplus +}; +#endif /* extern C */ +#endif //_clcc73_h_ diff --git a/userspace/sdks/nv570/inc/class/clcc7a.h b/userspace/sdks/nv570/inc/class/clcc7a.h new file mode 100644 index 0000000..1596460 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcc7a.h @@ -0,0 +1,216 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clcc7a__h_ +#define _clcc7a__h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVCC7A_CURSOR_IMM_CHANNEL_PIO (0x0000CC7A) + +typedef volatile struct _clcc7a_tag0 { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x7D]; + NvV32 Update; // 0x00000200 - 0x00000203 + NvV32 SetInterlockFlags; // 0x00000204 - 0x00000207 + NvV32 SetCursorHotSpotPointOut[2]; // 0x00000208 - 0x0000020F + NvV32 SetWindowInterlockFlags; // 0x00000210 - 0x00000213 + NvV32 Reserved02[0x3F7B]; +} NVCC7ADispCursorImmControlPio; + +#define NVCC7A_FREE (0x00000008) +#define NVCC7A_FREE_COUNT 5:0 +#define NVCC7A_UPDATE (0x00000200) +#define NVCC7A_UPDATE_RELEASE_ELV 0:0 +#define NVCC7A_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVCC7A_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVCC7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVCC7A_UPDATE_FORCE_FULLSCREEN 12:12 +#define NVCC7A_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000) +#define NVCC7A_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001) +#define NVCC7A_SET_INTERLOCK_FLAGS (0x00000204) +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVCC7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVCC7A_SET_CURSOR_HOT_SPOT_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVCC7A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0 +#define NVCC7A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS (0x00000210) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVCC7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clcc7a_h + \ No newline at end of file diff --git a/userspace/sdks/nv570/inc/class/clcc7b.h b/userspace/sdks/nv570/inc/class/clcc7b.h new file mode 100644 index 0000000..a97a324 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcc7b.h @@ -0,0 +1,70 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clcc7b_h_ +#define _clcc7b_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVCC7B_WINDOW_IMM_CHANNEL_DMA (0x0000CC7B) + +// dma opcode instructions +#define NVCC7B_DMA +#define NVCC7B_DMA_OPCODE 31:29 +#define NVCC7B_DMA_OPCODE_METHOD 0x00000000 +#define NVCC7B_DMA_OPCODE_JUMP 0x00000001 +#define NVCC7B_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVCC7B_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVCC7B_DMA_METHOD_COUNT 27:18 +#define NVCC7B_DMA_METHOD_OFFSET 15:2 +#define NVCC7B_DMA_DATA 31:0 +#define NVCC7B_DMA_DATA_NOP 0x00000000 +#define NVCC7B_DMA_JUMP_OFFSET 15:2 +#define NVCC7B_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVCC7B_PUT (0x00000000) +#define NVCC7B_PUT_PTR 13:0 +#define NVCC7B_GET (0x00000004) +#define NVCC7B_GET_PTR 13:0 +#define NVCC7B_UPDATE (0x00000200) +#define NVCC7B_UPDATE_RELEASE_ELV 0:0 +#define NVCC7B_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVCC7B_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVCC7B_UPDATE_INTERLOCK_WITH_WINDOW 1:1 +#define NVCC7B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVCC7B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVCC7B_UPDATE_FORCE_FULLSCREEN 4:4 +#define NVCC7B_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000) +#define NVCC7B_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001) +#define NVCC7B_SET_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVCC7B_SET_POINT_OUT_X 15:0 +#define NVCC7B_SET_POINT_OUT_Y 31:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clcc7b_h diff --git a/userspace/sdks/nv570/inc/class/clcc7d.h b/userspace/sdks/nv570/inc/class/clcc7d.h new file mode 100644 index 0000000..948ca11 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcc7d.h @@ -0,0 +1,2007 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clcc7d_h_ +#define _clcc7d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVCC7D_CORE_CHANNEL_DMA (0x0000CC7D) + +#define NV_DISP_NOTIFIER 0x00000000 +#define NV_DISP_NOTIFIER_SIZEOF 0x00000010 +#define NV_DISP_NOTIFIER__0 0x00000000 +#define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFIER__0_FIELD 8:8 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE 9:9 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001 +#define NV_DISP_NOTIFIER__0_R1 15:10 +#define NV_DISP_NOTIFIER__0_R2 23:16 +#define NV_DISP_NOTIFIER__0_R3 29:24 +#define NV_DISP_NOTIFIER__0_STATUS 31:30 +#define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002 +#define NV_DISP_NOTIFIER__1 0x00000001 +#define NV_DISP_NOTIFIER__1_R4 31:0 +#define NV_DISP_NOTIFIER__2 0x00000002 +#define NV_DISP_NOTIFIER__2_TIMESTAMP_LO 31:0 +#define NV_DISP_NOTIFIER__3 0x00000003 +#define NV_DISP_NOTIFIER__3_TIMESTAMP_HI 31:0 + + +// dma opcode instructions +#define NVCC7D_DMA +#define NVCC7D_DMA_OPCODE 31:29 +#define NVCC7D_DMA_OPCODE_METHOD 0x00000000 +#define NVCC7D_DMA_OPCODE_JUMP 0x00000001 +#define NVCC7D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVCC7D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVCC7D_DMA_METHOD_COUNT 27:18 +#define NVCC7D_DMA_METHOD_OFFSET 15:2 +#define NVCC7D_DMA_DATA 31:0 +#define NVCC7D_DMA_DATA_NOP 0x00000000 +#define NVCC7D_DMA_JUMP_OFFSET 15:2 +#define NVCC7D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// if cap SUPPORT_FLEXIBLE_WIN_MAPPING is FALSE, this define can be used to obtain which head a window is mapped to +#define NVC37D_WINDOW_MAPPED_TO_HEAD(w) ((w)>>1) +#define NVC37D_GET_VALID_WINDOWMASK_FOR_HEAD(h) ((1<<((h)*2)) | (1<<((h)*2+1))) + +// class methods +#define NVCC7D_PUT (0x00000000) +#define NVCC7D_PUT_PTR 13:0 +#define NVCC7D_GET (0x00000004) +#define NVCC7D_GET_PTR 13:0 +#define NVCC7D_UPDATE (0x00000200) +#define NVCC7D_UPDATE_SPECIAL_HANDLING 21:20 +#define NVCC7D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NVCC7D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NVCC7D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NVCC7D_UPDATE_SPECIAL_HANDLING_REASON 19:12 +#define NVCC7D_UPDATE_INHIBIT_INTERRUPTS 24:24 +#define NVCC7D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NVCC7D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NVCC7D_UPDATE_RELEASE_ELV 0:0 +#define NVCC7D_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVCC7D_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVCC7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVCC7D_UPDATE_FORCE_FULLSCREEN 28:28 +#define NVCC7D_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000) +#define NVCC7D_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001) +#define NVCC7D_SET_NOTIFIER_CONTROL (0x0000020C) +#define NVCC7D_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVCC7D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVCC7D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVCC7D_SET_NOTIFIER_CONTROL_NOTIFY 12:12 +#define NVCC7D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NVCC7D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NVCC7D_SET_CONTROL (0x00000210) +#define NVCC7D_SET_CONTROL_FLIP_LOCK_PIN(i) ((i)+0):((i)+0) +#define NVCC7D_SET_CONTROL_FLIP_LOCK_PIN__SIZE_1 4 +#define NVCC7D_SET_CONTROL_FLIP_LOCK_PIN_DISABLE (0x00000000) +#define NVCC7D_SET_CONTROL_FLIP_LOCK_PIN_ENABLE (0x00000001) +#define NVCC7D_SET_CONTROL_FLIP_LOCK_PIN0 0:0 +#define NVCC7D_SET_CONTROL_FLIP_LOCK_PIN0_DISABLE (0x00000000) +#define NVCC7D_SET_CONTROL_FLIP_LOCK_PIN0_ENABLE (0x00000001) +#define NVCC7D_SET_CONTROL_FLIP_LOCK_PIN1 1:1 +#define NVCC7D_SET_CONTROL_FLIP_LOCK_PIN1_DISABLE (0x00000000) +#define NVCC7D_SET_CONTROL_FLIP_LOCK_PIN1_ENABLE (0x00000001) +#define NVCC7D_SET_CONTROL_FLIP_LOCK_PIN2 2:2 +#define NVCC7D_SET_CONTROL_FLIP_LOCK_PIN2_DISABLE (0x00000000) +#define NVCC7D_SET_CONTROL_FLIP_LOCK_PIN2_ENABLE (0x00000001) +#define NVCC7D_SET_CONTROL_FLIP_LOCK_PIN3 3:3 +#define NVCC7D_SET_CONTROL_FLIP_LOCK_PIN3_DISABLE (0x00000000) +#define NVCC7D_SET_CONTROL_FLIP_LOCK_PIN3_ENABLE (0x00000001) +#define NVCC7D_SET_INTERLOCK_FLAGS (0x00000218) +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+0):((i)+0) +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVCC7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS (0x0000021C) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVCC7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVCC7D_GET_RG_SCAN_LINE(b) (0x00000220 + (b)*0x00000004) +#define NVCC7D_GET_RG_SCAN_LINE_LINE 15:0 +#define NVCC7D_GET_RG_SCAN_LINE_VBLANK 16:16 +#define NVCC7D_GET_RG_SCAN_LINE_VBLANK_FALSE (0x00000000) +#define NVCC7D_GET_RG_SCAN_LINE_VBLANK_TRUE (0x00000001) +#define NVCC7D_SET_GET_BLANKING_CTRL(b) (0x00000240 + (b)*0x00000004) +#define NVCC7D_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NVCC7D_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NVCC7D_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NVCC7D_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NVCC7D_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NVCC7D_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) +#define NVCC7D_SET_SURFACE_ADDRESS_HI_NOTIFIER (0x00000260) +#define NVCC7D_SET_SURFACE_ADDRESS_HI_NOTIFIER_ADDRESS_HI 31:0 +#define NVCC7D_SET_SURFACE_ADDRESS_LO_NOTIFIER (0x00000264) +#define NVCC7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_ADDRESS_LO 31:4 +#define NVCC7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET 3:2 +#define NVCC7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_IOVA (0x00000000) +#define NVCC7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCC7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCC7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCC7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE 0:0 +#define NVCC7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_DISABLE (0x00000000) +#define NVCC7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_ENABLE (0x00000001) + +#define NVCC7D_SOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NVCC7D_SOR_SET_CONTROL_OWNER_MASK 7:0 +#define NVCC7D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVCC7D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVCC7D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVCC7D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVCC7D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVCC7D_SOR_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVCC7D_SOR_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVCC7D_SOR_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVCC7D_SOR_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVCC7D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NVCC7D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NVCC7D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NVCC7D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NVCC7D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NVCC7D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NVCC7D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NVCC7D_SOR_SET_CONTROL_PROTOCOL_HDMI_FRL (0x0000000C) +#define NVCC7D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NVCC7D_SOR_SET_CONTROL_DE_SYNC_POLARITY 16:16 +#define NVCC7D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVCC7D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVCC7D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NVCC7D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NVCC7D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NVCC7D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NVCC7D_SOR_SET_CUSTOM_REASON(a) (0x00000304 + (a)*0x00000020) +#define NVCC7D_SOR_SET_CUSTOM_REASON_CODE 31:0 +#define NVCC7D_SOR_SET_SW_SPARE_A(a) (0x00000308 + (a)*0x00000020) +#define NVCC7D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NVCC7D_SOR_SET_SW_SPARE_B(a) (0x0000030C + (a)*0x00000020) +#define NVCC7D_SOR_SET_SW_SPARE_B_CODE 31:0 + +#define NVCC7D_DSI_SET_CONTROL(a) (0x00000500 + (a)*0x00000020) +#define NVCC7D_DSI_SET_CONTROL_OWNER_MASK 7:0 +#define NVCC7D_DSI_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVCC7D_DSI_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVCC7D_DSI_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVCC7D_DSI_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVCC7D_DSI_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVCC7D_DSI_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVCC7D_DSI_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVCC7D_DSI_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVCC7D_DSI_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVCC7D_DSI_SET_CUSTOM_REASON(a) (0x00000504 + (a)*0x00000020) +#define NVCC7D_DSI_SET_CUSTOM_REASON_CODE 31:0 +#define NVCC7D_DSI_SET_SW_SPARE_A(a) (0x00000508 + (a)*0x00000020) +#define NVCC7D_DSI_SET_SW_SPARE_A_CODE 31:0 +#define NVCC7D_DSI_SET_SW_SPARE_B(a) (0x0000050C + (a)*0x00000020) +#define NVCC7D_DSI_SET_SW_SPARE_B_CODE 31:0 + +#define NVCC7D_WINDOW_SET_CONTROL(a) (0x00001000 + (a)*0x00000080) +#define NVCC7D_WINDOW_SET_CONTROL_OWNER 3:0 +#define NVCC7D_WINDOW_SET_CONTROL_OWNER_HEAD(i) (0x00000000 +(i)) +#define NVCC7D_WINDOW_SET_CONTROL_OWNER_HEAD__SIZE_1 8 +#define NVCC7D_WINDOW_SET_CONTROL_OWNER_HEAD0 (0x00000000) +#define NVCC7D_WINDOW_SET_CONTROL_OWNER_HEAD1 (0x00000001) +#define NVCC7D_WINDOW_SET_CONTROL_OWNER_HEAD2 (0x00000002) +#define NVCC7D_WINDOW_SET_CONTROL_OWNER_HEAD3 (0x00000003) +#define NVCC7D_WINDOW_SET_CONTROL_OWNER_HEAD4 (0x00000004) +#define NVCC7D_WINDOW_SET_CONTROL_OWNER_HEAD5 (0x00000005) +#define NVCC7D_WINDOW_SET_CONTROL_OWNER_HEAD6 (0x00000006) +#define NVCC7D_WINDOW_SET_CONTROL_OWNER_HEAD7 (0x00000007) +#define NVCC7D_WINDOW_SET_CONTROL_OWNER_NONE (0x0000000F) +#define NVCC7D_WINDOW_SET_CONTROL_HIDE 8:8 +#define NVCC7D_WINDOW_SET_CONTROL_HIDE_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_CONTROL_HIDE_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_CONTROL_DISABLE_PHYSICAL_FLIPS 9:9 +#define NVCC7D_WINDOW_SET_CONTROL_DISABLE_PHYSICAL_FLIPS_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_CONTROL_DISABLE_PHYSICAL_FLIPS_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_CONTROL_ALLOW_SUPERFRAME 10:10 +#define NVCC7D_WINDOW_SET_CONTROL_ALLOW_SUPERFRAME_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_CONTROL_ALLOW_SUPERFRAME_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0x00000080) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a) (0x00001008 + (a)*0x00000080) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR(a) (0x0000100C + (a)*0x00000080) +#define NVCC7D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVCC7D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVCC7D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a) (0x00001010 + (a)*0x00000080) +#define NVCC7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_MAX_PIXELS_FETCHED_PER_LINE 14:0 +#define NVCC7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED 16:16 +#define NVCC7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED 28:28 +#define NVCC7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS 22:20 +#define NVCC7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVCC7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED 24:24 +#define NVCC7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED 30:30 +#define NVCC7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_LAYOUT 26:25 +#define NVCC7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_LAYOUT_PITCH_BLOCKLINEAR (0x00000000) +#define NVCC7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_LAYOUT_PITCH (0x00000001) +#define NVCC7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_LAYOUT_BLOCKLINEAR (0x00000002) +#define NVCC7D_WINDOW_SET_PHYSICAL(a) (0x00001014 + (a)*0x00000080) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW 31:0 +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_NONE (0x00000000) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW0 (0x00000001) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW1 (0x00000002) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW2 (0x00000004) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW3 (0x00000008) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW4 (0x00000010) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW5 (0x00000020) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW6 (0x00000040) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW7 (0x00000080) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW8 (0x00000100) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW9 (0x00000200) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW10 (0x00000400) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW11 (0x00000800) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW12 (0x00001000) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW13 (0x00002000) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW14 (0x00004000) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW15 (0x00008000) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW16 (0x00010000) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW17 (0x00020000) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW18 (0x00040000) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW19 (0x00080000) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW20 (0x00100000) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW21 (0x00200000) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW22 (0x00400000) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW23 (0x00800000) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW24 (0x01000000) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW25 (0x02000000) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW26 (0x04000000) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW27 (0x08000000) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW28 (0x10000000) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW29 (0x20000000) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW30 (0x40000000) +#define NVCC7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW31 (0x80000000) +#define NVCC7D_WINDOW_SET_GUEST_OVERRIDES(a) (0x00001024 + (a)*0x00000080) +#define NVCC7D_WINDOW_SET_GUEST_OVERRIDES_SET_SIZE_OUT 0:0 +#define NVCC7D_WINDOW_SET_GUEST_OVERRIDES_SET_SIZE_OUT_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_GUEST_OVERRIDES_SET_SIZE_OUT_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_CONTROL 1:1 +#define NVCC7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_CONTROL_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_CONTROL_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_CONSTANT_ALPHA 2:2 +#define NVCC7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_CONSTANT_ALPHA_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_CONSTANT_ALPHA_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_FACTOR_SELECT 3:3 +#define NVCC7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_FACTOR_SELECT_FALSE (0x00000000) +#define NVCC7D_WINDOW_SET_GUEST_OVERRIDES_SET_COMPOSITION_FACTOR_SELECT_TRUE (0x00000001) +#define NVCC7D_WINDOW_SET_GUEST_SIZE_OUT(a) (0x00001028 + (a)*0x00000080) +#define NVCC7D_WINDOW_SET_GUEST_SIZE_OUT_WIDTH 15:0 +#define NVCC7D_WINDOW_SET_GUEST_SIZE_OUT_HEIGHT 31:16 +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL(a) (0x0000102C + (a)*0x00000080) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0 +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL_DEPTH 11:4 +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL_BYPASS 16:16 +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL_BYPASS_DISABLE (0x00000000) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_CONTROL_BYPASS_ENABLE (0x00000001) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_CONSTANT_ALPHA(a) (0x00001030 + (a)*0x00000080) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_CONSTANT_ALPHA_K1 7:0 +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_CONSTANT_ALPHA_K2 15:8 +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT(a) (0x00001034 + (a)*0x00000080) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0 +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4 +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8 +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12 +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16 +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20 +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24 +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28 +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVCC7D_WINDOW_SET_GUEST_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) + +#define NVCC7D_HEAD_SET_PROCAMP(a) (0x00002000 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NVCC7D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NVCC7D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NVCC7D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NVCC7D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003) +#define NVCC7D_HEAD_SET_PROCAMP_CHROMA_LPF 3:3 +#define NVCC7D_HEAD_SET_PROCAMP_CHROMA_LPF_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_PROCAMP_CHROMA_LPF_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_PROCAMP_CHROMA_DOWN_V 4:4 +#define NVCC7D_HEAD_SET_PROCAMP_CHROMA_DOWN_V_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_PROCAMP_CHROMA_DOWN_V_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 28:28 +#define NVCC7D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NVCC7D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00002004 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 2:2 +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 3:3 +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 7:4 +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000000) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000001) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000002) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000003) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000004) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000005) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000006) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000007) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000008) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_444 (0x00000009) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444NP (0x0000000A) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 24:24 +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 23:12 +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN 31:26 +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN0 (0x00000000) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN1 (0x00000001) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN2 (0x00000002) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN3 (0x00000003) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN4 (0x00000004) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN5 (0x00000005) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN6 (0x00000006) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN7 (0x00000007) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN8 (0x00000008) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN9 (0x00000009) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN10 (0x0000000A) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN11 (0x0000000B) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN12 (0x0000000C) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN13 (0x0000000D) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN14 (0x0000000E) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN15 (0x0000000F) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN16 (0x00000010) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN17 (0x00000011) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN18 (0x00000012) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN19 (0x00000013) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN20 (0x00000014) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN21 (0x00000015) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN22 (0x00000016) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN23 (0x00000017) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN24 (0x00000018) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN25 (0x00000019) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN26 (0x0000001A) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN27 (0x0000001B) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN28 (0x0000001C) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN29 (0x0000001D) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN30 (0x0000001E) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN31 (0x0000001F) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_NONE (0x0000003F) +#define NVCC7D_HEAD_SET_CONTROL(a) (0x00002008 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_CONTROL_STRUCTURE 1:0 +#define NVCC7D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NVCC7D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE 2:2 +#define NVCC7D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_NORMAL (0x00000000) +#define NVCC7D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000001) +#define NVCC7D_HEAD_SET_CONTROL_YUV420PACKER 3:3 +#define NVCC7D_HEAD_SET_CONTROL_YUV420PACKER_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_CONTROL_YUV420PACKER_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_MODE 11:10 +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_MODE_NO_LOCK (0x00000000) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN 8:4 +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVCC7D_HEAD_SET_CONTROL_SINK_LOCKOUT_WINDOW 15:12 +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_MODE 23:22 +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_MODE_NO_LOCK (0x00000000) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN 20:16 +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN 28:24 +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_NONE (0x00000000) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000001) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000002) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000003) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000004) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000005) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000006) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000007) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000008) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000009) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x0000000A) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000B) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000C) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000D) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000E) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000F) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x00000010) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVCC7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVCC7D_HEAD_SET_CONTROL_SINK_STEREO_LOCK_MODE 30:30 +#define NVCC7D_HEAD_SET_CONTROL_SINK_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_CONTROL_SINK_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_STEREO_LOCK_MODE 31:31 +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_CONTROL_SOURCE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x0000200C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NVCC7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NVCC7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NVCC7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00002014 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVCC7D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVCC7D_HEAD_SET_DITHER_CONTROL(a) (0x00002018 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NVCC7D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_DITHER_CONTROL_BITS 5:4 +#define NVCC7D_HEAD_SET_DITHER_CONTROL_BITS_TO_6_BITS (0x00000000) +#define NVCC7D_HEAD_SET_DITHER_CONTROL_BITS_TO_8_BITS (0x00000001) +#define NVCC7D_HEAD_SET_DITHER_CONTROL_BITS_TO_10_BITS (0x00000002) +#define NVCC7D_HEAD_SET_DITHER_CONTROL_BITS_TO_12_BITS (0x00000003) +#define NVCC7D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE 2:2 +#define NVCC7D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_DITHER_CONTROL_MODE 10:8 +#define NVCC7D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NVCC7D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NVCC7D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NVCC7D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NVCC7D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NVCC7D_HEAD_SET_DITHER_CONTROL_MODE_ROUND (0x00000005) +#define NVCC7D_HEAD_SET_DITHER_CONTROL_PHASE 13:12 +#define NVCC7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x0000201C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 0:0 +#define NVCC7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NVCC7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NVCC7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING 4:4 +#define NVCC7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 9:8 +#define NVCC7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NVCC7D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NVCC7D_HEAD_SET_DISPLAY_ID(a,b) (0x00002020 + (a)*0x00000800 + (b)*0x00000004) +#define NVCC7D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NVCC7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00002028 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NVCC7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NVCC7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NVCC7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NVCC7D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR(a) (0x0000202C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVCC7D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVCC7D_HEAD_SET_HEAD_USAGE_BOUNDS(a) (0x00002030 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR 2:0 +#define NVCC7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_NONE (0x00000000) +#define NVCC7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W32_H32 (0x00000001) +#define NVCC7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W64_H64 (0x00000002) +#define NVCC7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W128_H128 (0x00000003) +#define NVCC7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W256_H256 (0x00000004) +#define NVCC7D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED 4:4 +#define NVCC7D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_FALSE (0x00000000) +#define NVCC7D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_TRUE (0x00000001) +#define NVCC7D_HEAD_SET_HEAD_USAGE_BOUNDS_LTM_ALLOWED 5:5 +#define NVCC7D_HEAD_SET_HEAD_USAGE_BOUNDS_LTM_ALLOWED_FALSE (0x00000000) +#define NVCC7D_HEAD_SET_HEAD_USAGE_BOUNDS_LTM_ALLOWED_TRUE (0x00000001) +#define NVCC7D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS 14:12 +#define NVCC7D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVCC7D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVCC7D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED 8:8 +#define NVCC7D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVCC7D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVCC7D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED 16:16 +#define NVCC7D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED_FALSE (0x00000000) +#define NVCC7D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED_TRUE (0x00000001) +#define NVCC7D_HEAD_SET_HEAD_USAGE_BOUNDS_ELV_START 31:17 +#define NVCC7D_HEAD_SET_STALL_LOCK(a) (0x00002034 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_STALL_LOCK_ENABLE 0:0 +#define NVCC7D_HEAD_SET_STALL_LOCK_ENABLE_FALSE (0x00000000) +#define NVCC7D_HEAD_SET_STALL_LOCK_ENABLE_TRUE (0x00000001) +#define NVCC7D_HEAD_SET_STALL_LOCK_MODE 2:2 +#define NVCC7D_HEAD_SET_STALL_LOCK_MODE_CONTINUOUS (0x00000000) +#define NVCC7D_HEAD_SET_STALL_LOCK_MODE_ONE_SHOT (0x00000001) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN 8:4 +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVCC7D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVCC7D_HEAD_SET_STALL_LOCK_UNSTALL_MODE 12:12 +#define NVCC7D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_CRASH_LOCK (0x00000000) +#define NVCC7D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_LINE_LOCK (0x00000001) +#define NVCC7D_HEAD_SET_STALL_LOCK_TEPOLARITY 14:14 +#define NVCC7D_HEAD_SET_STALL_LOCK_TEPOLARITY_POSITIVE_TRUE (0x00000000) +#define NVCC7D_HEAD_SET_STALL_LOCK_TEPOLARITY_NEGATIVE_TRUE (0x00000001) +#define NVCC7D_HEAD_SET_STALL_LOCK_UNSTALL_SYNC_ADVANCE 25:16 +#define NVCC7D_HEAD_SET_LOCK_CHAIN(a) (0x00002044 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_LOCK_CHAIN_POSITION 3:0 +#define NVCC7D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x00002048 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NVCC7D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NVCC7D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x0000204C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NVCC7D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NVCC7D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x00002058 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NVCC7D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NVCC7D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x0000205C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NVCC7D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NVCC7D_HEAD_SET_TILE_MASK(a) (0x00002060 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_TILE_MASK_TILE 7:0 +#define NVCC7D_HEAD_SET_TILE_MASK_TILE_NONE (0x00000000) +#define NVCC7D_HEAD_SET_TILE_MASK_TILE_TILE0 (0x00000001) +#define NVCC7D_HEAD_SET_TILE_MASK_TILE_TILE1 (0x00000002) +#define NVCC7D_HEAD_SET_TILE_MASK_TILE_TILE2 (0x00000004) +#define NVCC7D_HEAD_SET_TILE_MASK_TILE_TILE3 (0x00000008) +#define NVCC7D_HEAD_SET_TILE_MASK_TILE_TILE4 (0x00000010) +#define NVCC7D_HEAD_SET_TILE_MASK_TILE_TILE5 (0x00000020) +#define NVCC7D_HEAD_SET_TILE_MASK_TILE_TILE6 (0x00000040) +#define NVCC7D_HEAD_SET_TILE_MASK_TILE_TILE7 (0x00000080) +#define NVCC7D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_RASTER_SIZE_WIDTH 15:0 +#define NVCC7D_HEAD_SET_RASTER_SIZE_HEIGHT 31:16 +#define NVCC7D_HEAD_SET_RASTER_SYNC_END(a) (0x00002068 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NVCC7D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NVCC7D_HEAD_SET_RASTER_BLANK_END(a) (0x0000206C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NVCC7D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NVCC7D_HEAD_SET_RASTER_BLANK_START(a) (0x00002070 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NVCC7D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NVCC7D_HEAD_SET_OVERSCAN_COLOR(a) (0x00002078 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OVERSCAN_COLOR_RED_CR 9:0 +#define NVCC7D_HEAD_SET_OVERSCAN_COLOR_GREEN_Y 19:10 +#define NVCC7D_HEAD_SET_OVERSCAN_COLOR_BLUE_CB 29:20 +#define NVCC7D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR(a) (0x0000207C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_RED_CR 9:0 +#define NVCC7D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_GREEN_Y 19:10 +#define NVCC7D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_BLUE_CB 29:20 +#define NVCC7D_HEAD_SET_HDMI_CTRL(a) (0x00002080 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NVCC7D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NVCC7D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NVCC7D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NVCC7D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NVCC7D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x00002098 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 0:0 +#define NVCC7D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NVCC7D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NVCC7D_HEAD_SET_CONTROL_CURSOR(a) (0x0000209C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_FORMAT 7:0 +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x000000E9) +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x000000CF) +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_SIZE 9:8 +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 19:12 +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 27:20 +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION(a) (0x000020A0 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_K1 7:0 +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT 11:8 +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1_TIMES_SRC (0x00000005) +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT 15:12 +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_ZERO (0x00000000) +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE 16:16 +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_BLEND (0x00000000) +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_XOR (0x00000001) +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS 20:20 +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_CMI_LUT_CONTROL(a) (0x000020A4 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_CMI_LUT_CONTROL_ENABLE 0:0 +#define NVCC7D_HEAD_SET_CMI_LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_CMI_LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_CMI_LUT_CONTROL_INTERPOLATE 1:1 +#define NVCC7D_HEAD_SET_CMI_LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_CMI_LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_CMI_LUT_CONTROL_MIRROR 2:2 +#define NVCC7D_HEAD_SET_CMI_LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_CMI_LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_CMI_FP_NORM_SCALE(a) (0x000020A8 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_CMI_FP_NORM_SCALE_FPNORM 31:0 +#define NVCC7D_HEAD_SET_CMO_LUT_CONTROL(a) (0x000020AC + (a)*0x00000800) +#define NVCC7D_HEAD_SET_CMO_LUT_CONTROL_ENABLE 0:0 +#define NVCC7D_HEAD_SET_CMO_LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_CMO_LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_CMO_LUT_CONTROL_INTERPOLATE 1:1 +#define NVCC7D_HEAD_SET_CMO_LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_CMO_LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_CMO_LUT_CONTROL_MIRROR 2:2 +#define NVCC7D_HEAD_SET_CMO_LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_CMO_LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_CM3D0CONTROL(a) (0x000020B8 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_CM3D0CONTROL_MODE 0:0 +#define NVCC7D_HEAD_SET_CM3D0CONTROL_MODE_GAMUT_MAPPING (0x00000000) +#define NVCC7D_HEAD_SET_CM3D0CONTROL_MODE_PANEL_CORR (0x00000001) +#define NVCC7D_HEAD_SET_CM3D0CONTROL_ROUND 1:1 +#define NVCC7D_HEAD_SET_CM3D0CONTROL_ROUND_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_CM3D0CONTROL_ROUND_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_CM3D0CONTROL_LAST_ENTRY_ADD1 2:2 +#define NVCC7D_HEAD_SET_CM3D0CONTROL_LAST_ENTRY_ADD1_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_CM3D0CONTROL_LAST_ENTRY_ADD1_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_CM3D0CONTROL_SIZE 3:3 +#define NVCC7D_HEAD_SET_CM3D0CONTROL_SIZE_SIZE_9X9X9 (0x00000000) +#define NVCC7D_HEAD_SET_CM3D0CONTROL_SIZE_SIZE_17X17X17 (0x00000001) +#define NVCC7D_HEAD_SET_CM3D0CONTROL_RANGE_SCALE 8:6 +#define NVCC7D_HEAD_SET_CM3D0CONTROL_CONTENT_OFFSET 22:9 +#define NVCC7D_HEAD_SET_CM3D1CONTROL(a) (0x000020BC + (a)*0x00000800) +#define NVCC7D_HEAD_SET_CM3D1CONTROL_MODE 0:0 +#define NVCC7D_HEAD_SET_CM3D1CONTROL_MODE_GAMUT_MAPPING (0x00000000) +#define NVCC7D_HEAD_SET_CM3D1CONTROL_MODE_PANEL_CORR (0x00000001) +#define NVCC7D_HEAD_SET_CM3D1CONTROL_ROUND 1:1 +#define NVCC7D_HEAD_SET_CM3D1CONTROL_ROUND_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_CM3D1CONTROL_ROUND_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_CM3D1CONTROL_LAST_ENTRY_ADD1 2:2 +#define NVCC7D_HEAD_SET_CM3D1CONTROL_LAST_ENTRY_ADD1_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_CM3D1CONTROL_LAST_ENTRY_ADD1_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_CM3D1CONTROL_SIZE 3:3 +#define NVCC7D_HEAD_SET_CM3D1CONTROL_SIZE_SIZE_9X9X9 (0x00000000) +#define NVCC7D_HEAD_SET_CM3D1CONTROL_SIZE_SIZE_17X17X17 (0x00000001) +#define NVCC7D_HEAD_SET_CM3D1CONTROL_RANGE_SCALE 8:6 +#define NVCC7D_HEAD_SET_CM3D1CONTROL_CONTENT_OFFSET 22:9 +#define NVCC7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI(a) (0x000020C0 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_HERTZ 3:0 +#define NVCC7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_MAX(a) (0x000020C4 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_MAX_HERTZ 3:0 +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE(a,b) (0x000020C8 + (a)*0x00000800 + (b)*0x00000004) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW 15:10 +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN0 (0x00000000) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN1 (0x00000001) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN2 (0x00000002) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN3 (0x00000003) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN4 (0x00000004) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN5 (0x00000005) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN6 (0x00000006) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN7 (0x00000007) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN8 (0x00000008) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN9 (0x00000009) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN10 (0x0000000A) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN11 (0x0000000B) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN12 (0x0000000C) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN13 (0x0000000D) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN14 (0x0000000E) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN15 (0x0000000F) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN16 (0x00000010) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN17 (0x00000011) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN18 (0x00000012) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN19 (0x00000013) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN20 (0x00000014) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN21 (0x00000015) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN22 (0x00000016) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN23 (0x00000017) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN24 (0x00000018) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN25 (0x00000019) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN26 (0x0000001A) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN27 (0x0000001B) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN28 (0x0000001C) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN29 (0x0000001D) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN30 (0x0000001E) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_WIN31 (0x0000001F) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_WINDOW_NONE (0x0000003F) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_INDEX 1:1 +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_ENABLE 0:0 +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_ENABLE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_ENABLE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_LOCATION_OVERRIDE 2:2 +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_LOCATION_OVERRIDE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_LOCATION_OVERRIDE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_LOCATION 9:8 +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_LOCATION_VBLANK (0x00000000) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_LOCATION_VSYNC (0x00000001) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_LOCATION_LINE (0x00000002) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_LINE_ID 30:16 +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_LINE_ID_REVERSED 31:31 +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_LINE_ID_REVERSED_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_LINE_ID_REVERSED_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_HB0OVERRIDE 4:4 +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_HB0OVERRIDE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_HB0OVERRIDE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_HB1OVERRIDE 5:5 +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_HB1OVERRIDE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_HB1OVERRIDE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_HB2OVERRIDE 6:6 +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_HB2OVERRIDE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_HB2OVERRIDE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_HB3OVERRIDE 7:7 +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_HB3OVERRIDE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_INFOFRAME_OVERRIDE_HB3OVERRIDE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_INFOFRAME_HEADER_OVERRIDE(a,b) (0x000020D0 + (a)*0x00000800 + (b)*0x00000004) +#define NVCC7D_HEAD_SET_INFOFRAME_HEADER_OVERRIDE_HB0 7:0 +#define NVCC7D_HEAD_SET_INFOFRAME_HEADER_OVERRIDE_HB1 15:8 +#define NVCC7D_HEAD_SET_INFOFRAME_HEADER_OVERRIDE_HB2 23:16 +#define NVCC7D_HEAD_SET_INFOFRAME_HEADER_OVERRIDE_HB3 31:24 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_HI_RG_REL_SEMAPHORE(a,b) (0x00002110 + (a)*0x00000800 + (b)*0x00000004) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_HI_RG_REL_SEMAPHORE_ADDRESS_HI 31:0 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE(a,b) (0x00002130 + (a)*0x00000800 + (b)*0x00000004) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_ADDRESS_LO 31:4 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_TARGET 3:2 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_TARGET_IOVA (0x00000000) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_ENABLE 0:0 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_ENABLE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE_ENABLE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_HI_CRC(a) (0x00002150 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_HI_CRC_ADDRESS_HI 31:0 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC(a) (0x00002154 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_ADDRESS_LO 31:4 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET 3:2 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET_IOVA (0x00000000) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_ENABLE 0:0 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_ENABLE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_ENABLE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_HI_OLUT(a) (0x00002158 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_HI_OLUT_ADDRESS_HI 31:0 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT(a) (0x0000215C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_ADDRESS_LO 31:4 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET 3:2 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET_IOVA (0x00000000) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_ENABLE 0:0 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_ENABLE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_ENABLE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_HI_CM3D0(a) (0x00002160 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_HI_CM3D0_ADDRESS_HI 31:0 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0(a) (0x00002164 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_ADDRESS_LO 31:4 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_TARGET 3:2 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_TARGET_IOVA (0x00000000) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_ENABLE 0:0 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_ENABLE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D0_ENABLE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_HI_CM3D1(a) (0x00002168 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_HI_CM3D1_ADDRESS_HI 31:0 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1(a) (0x0000216C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_ADDRESS_LO 31:4 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_TARGET 3:2 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_TARGET_IOVA (0x00000000) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_ENABLE 0:0 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_ENABLE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CM3D1_ENABLE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_HI_CURSOR(a,b) (0x00002170 + (a)*0x00000800 + (b)*0x00000004) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_HI_CURSOR_ADDRESS_HI 31:0 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR(a,b) (0x00002178 + (a)*0x00000800 + (b)*0x00000004) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_ADDRESS_LO 31:4 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET 3:2 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET_IOVA (0x00000000) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_KIND 1:1 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_KIND_PITCH (0x00000000) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_KIND_BLOCKLINEAR (0x00000001) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_ENABLE 0:0 +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_ENABLE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_ENABLE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_CRC_CONTROL(a) (0x00002184 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 5:0 +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_0 (0x00000000) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_1 (0x00000001) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_2 (0x00000002) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_3 (0x00000003) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_4 (0x00000004) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_5 (0x00000005) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_6 (0x00000006) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_7 (0x00000007) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_8 (0x00000008) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_9 (0x00000009) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_10 (0x0000000A) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_11 (0x0000000B) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_12 (0x0000000C) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_13 (0x0000000D) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_14 (0x0000000E) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_15 (0x0000000F) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_16 (0x00000010) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_17 (0x00000011) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_18 (0x00000012) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_19 (0x00000013) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_20 (0x00000014) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_21 (0x00000015) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_22 (0x00000016) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_23 (0x00000017) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_24 (0x00000018) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_25 (0x00000019) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_26 (0x0000001A) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_27 (0x0000001B) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_28 (0x0000001C) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_29 (0x0000001D) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_30 (0x0000001E) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_31 (0x0000001F) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000020) +#define NVCC7D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 8:8 +#define NVCC7D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NVCC7D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NVCC7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC 19:12 +#define NVCC7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_NONE (0x00000000) +#define NVCC7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SF (0x00000030) +#define NVCC7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVCC7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR__SIZE_1 8 +#define NVCC7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR0 (0x00000050) +#define NVCC7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR1 (0x00000051) +#define NVCC7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR2 (0x00000052) +#define NVCC7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR3 (0x00000053) +#define NVCC7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR4 (0x00000054) +#define NVCC7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR5 (0x00000055) +#define NVCC7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR6 (0x00000056) +#define NVCC7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR7 (0x00000057) +#define NVCC7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC 27:20 +#define NVCC7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_NONE (0x00000000) +#define NVCC7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SF (0x00000030) +#define NVCC7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVCC7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR__SIZE_1 8 +#define NVCC7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR0 (0x00000050) +#define NVCC7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR1 (0x00000051) +#define NVCC7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR2 (0x00000052) +#define NVCC7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR3 (0x00000053) +#define NVCC7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR4 (0x00000054) +#define NVCC7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR5 (0x00000055) +#define NVCC7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR6 (0x00000056) +#define NVCC7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR7 (0x00000057) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 9:9 +#define NVCC7D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_PRESENT_CONTROL(a) (0x0000218C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 0:0 +#define NVCC7D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NVCC7D_HEAD_SET_SW_SPARE_A(a) (0x00002194 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NVCC7D_HEAD_SET_SW_SPARE_B(a) (0x00002198 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NVCC7D_HEAD_SET_SW_SPARE_C(a) (0x0000219C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NVCC7D_HEAD_SET_SW_SPARE_D(a) (0x000021A0 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NVCC7D_HEAD_SET_DISPLAY_RATE(a) (0x000021A8 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DISPLAY_RATE_RUN_MODE 1:0 +#define NVCC7D_HEAD_SET_DISPLAY_RATE_RUN_MODE_CONTINUOUS (0x00000000) +#define NVCC7D_HEAD_SET_DISPLAY_RATE_RUN_MODE_ONE_SHOT (0x00000001) +#define NVCC7D_HEAD_SET_DISPLAY_RATE_RUN_MODE_ONE_SHOT_SELF_REFRESH (0x00000002) +#define NVCC7D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_INTERVAL 25:4 +#define NVCC7D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH 2:2 +#define NVCC7D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL(a,b) (0x000021CC + (a)*0x00000800 + (b)*0x00000004) +#define NVCC7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVCC7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVCC7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVCC7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE 14:14 +#define NVCC7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE_WRITE (0x00000000) +#define NVCC7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE_WRITE_AWAKEN (0x00000001) +#define NVCC7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE 10:10 +#define NVCC7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE_ONE_TIME (0x00000000) +#define NVCC7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE_CONTINUOUS (0x00000001) +#define NVCC7D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RASTER_LINE 31:16 +#define NVCC7D_HEAD_SET_RG_REL_SEMAPHORE_VALUE(a,b) (0x000021EC + (a)*0x00000800 + (b)*0x00000004) +#define NVCC7D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_VALUE 31:0 +#define NVCC7D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE(a) (0x00002214 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVCC7D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVCC7D_HEAD_SET_MIN_FRAME_IDLE(a) (0x00002218 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_MIN_FRAME_IDLE_LEADING_RASTER_LINES 14:0 +#define NVCC7D_HEAD_SET_MIN_FRAME_IDLE_TRAILING_RASTER_LINES 30:16 +#define NVCC7D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED(a) (0x00002220 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED_ALPHA 7:0 +#define NVCC7D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED_RED 31:16 +#define NVCC7D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE(a) (0x00002224 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE_GREEN 15:0 +#define NVCC7D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE_BLUE 31:16 +#define NVCC7D_HEAD_SET_CURSOR_COLOR_NORM_SCALE(a) (0x00002228 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_CURSOR_COLOR_NORM_SCALE_VALUE 15:0 +#define NVCC7D_HEAD_SET_XOR_BLEND_FACTOR(a) (0x0000222C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_XOR_BLEND_FACTOR_LOG2PEAK_LUMINANCE 3:0 +#define NVCC7D_HEAD_SET_XOR_BLEND_FACTOR_S1 16:4 +#define NVCC7D_HEAD_SET_XOR_BLEND_FACTOR_S2 30:18 +#define NVCC7D_HEAD_SET_CLAMP_RANGE_GREEN(a) (0x00002238 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_CLAMP_RANGE_GREEN_LOW 11:0 +#define NVCC7D_HEAD_SET_CLAMP_RANGE_GREEN_HIGH 27:16 +#define NVCC7D_HEAD_SET_CLAMP_RANGE_RED_BLUE(a) (0x0000223C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_CLAMP_RANGE_RED_BLUE_LOW 11:0 +#define NVCC7D_HEAD_SET_CLAMP_RANGE_RED_BLUE_HIGH 27:16 +#define NVCC7D_HEAD_SET_OCSC0CONTROL(a) (0x00002240 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC0CONTROL_ENABLE 0:0 +#define NVCC7D_HEAD_SET_OCSC0CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_OCSC0CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_OCSC0COEFFICIENT_C00(a) (0x00002244 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC0COEFFICIENT_C00_VALUE 20:0 +#define NVCC7D_HEAD_SET_OCSC0COEFFICIENT_C01(a) (0x00002248 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC0COEFFICIENT_C01_VALUE 20:0 +#define NVCC7D_HEAD_SET_OCSC0COEFFICIENT_C02(a) (0x0000224C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC0COEFFICIENT_C02_VALUE 20:0 +#define NVCC7D_HEAD_SET_OCSC0COEFFICIENT_C03(a) (0x00002250 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC0COEFFICIENT_C03_VALUE 20:0 +#define NVCC7D_HEAD_SET_OCSC0COEFFICIENT_C10(a) (0x00002254 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC0COEFFICIENT_C10_VALUE 20:0 +#define NVCC7D_HEAD_SET_OCSC0COEFFICIENT_C11(a) (0x00002258 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC0COEFFICIENT_C11_VALUE 20:0 +#define NVCC7D_HEAD_SET_OCSC0COEFFICIENT_C12(a) (0x0000225C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC0COEFFICIENT_C12_VALUE 20:0 +#define NVCC7D_HEAD_SET_OCSC0COEFFICIENT_C13(a) (0x00002260 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC0COEFFICIENT_C13_VALUE 20:0 +#define NVCC7D_HEAD_SET_OCSC0COEFFICIENT_C20(a) (0x00002264 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC0COEFFICIENT_C20_VALUE 20:0 +#define NVCC7D_HEAD_SET_OCSC0COEFFICIENT_C21(a) (0x00002268 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC0COEFFICIENT_C21_VALUE 20:0 +#define NVCC7D_HEAD_SET_OCSC0COEFFICIENT_C22(a) (0x0000226C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC0COEFFICIENT_C22_VALUE 20:0 +#define NVCC7D_HEAD_SET_OCSC0COEFFICIENT_C23(a) (0x00002270 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC0COEFFICIENT_C23_VALUE 20:0 +#define NVCC7D_HEAD_SET_OLUT_CONTROL(a) (0x00002280 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OLUT_CONTROL_INTERPOLATE 0:0 +#define NVCC7D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_OLUT_CONTROL_MIRROR 1:1 +#define NVCC7D_HEAD_SET_OLUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_OLUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_OLUT_CONTROL_MODE 3:2 +#define NVCC7D_HEAD_SET_OLUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVCC7D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVCC7D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVCC7D_HEAD_SET_OLUT_CONTROL_SIZE 18:8 +#define NVCC7D_HEAD_SET_OLUT_CONTROL_DIRECT_ROUND 4:4 +#define NVCC7D_HEAD_SET_OLUT_CONTROL_DIRECT_ROUND_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_OLUT_CONTROL_DIRECT_ROUND_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_OLUT_CONTROL_LEVEL 25:20 +#define NVCC7D_HEAD_SET_OLUT_CONTROL_SEGMENT_SIZE_BITS 5:5 +#define NVCC7D_HEAD_SET_OLUT_CONTROL_SEGMENT_SIZE_BITS_SIZE_3BITS (0x00000000) +#define NVCC7D_HEAD_SET_OLUT_CONTROL_SEGMENT_SIZE_BITS_SIZE_4BITS (0x00000001) +#define NVCC7D_HEAD_SET_OLUT_FP_NORM_SCALE(a) (0x00002284 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OLUT_FP_NORM_SCALE_VALUE 31:0 +#define NVCC7D_HEAD_SET_OCSC1CONTROL(a) (0x0000229C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC1CONTROL_ENABLE 0:0 +#define NVCC7D_HEAD_SET_OCSC1CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_OCSC1CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_OCSC1COEFFICIENT_C00(a) (0x000022A0 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC1COEFFICIENT_C00_VALUE 20:0 +#define NVCC7D_HEAD_SET_OCSC1COEFFICIENT_C01(a) (0x000022A4 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC1COEFFICIENT_C01_VALUE 20:0 +#define NVCC7D_HEAD_SET_OCSC1COEFFICIENT_C02(a) (0x000022A8 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC1COEFFICIENT_C02_VALUE 20:0 +#define NVCC7D_HEAD_SET_OCSC1COEFFICIENT_C03(a) (0x000022AC + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC1COEFFICIENT_C03_VALUE 20:0 +#define NVCC7D_HEAD_SET_OCSC1COEFFICIENT_C10(a) (0x000022B0 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC1COEFFICIENT_C10_VALUE 20:0 +#define NVCC7D_HEAD_SET_OCSC1COEFFICIENT_C11(a) (0x000022B4 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC1COEFFICIENT_C11_VALUE 20:0 +#define NVCC7D_HEAD_SET_OCSC1COEFFICIENT_C12(a) (0x000022B8 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC1COEFFICIENT_C12_VALUE 20:0 +#define NVCC7D_HEAD_SET_OCSC1COEFFICIENT_C13(a) (0x000022BC + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC1COEFFICIENT_C13_VALUE 20:0 +#define NVCC7D_HEAD_SET_OCSC1COEFFICIENT_C20(a) (0x000022C0 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC1COEFFICIENT_C20_VALUE 20:0 +#define NVCC7D_HEAD_SET_OCSC1COEFFICIENT_C21(a) (0x000022C4 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC1COEFFICIENT_C21_VALUE 20:0 +#define NVCC7D_HEAD_SET_OCSC1COEFFICIENT_C22(a) (0x000022C8 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC1COEFFICIENT_C22_VALUE 20:0 +#define NVCC7D_HEAD_SET_OCSC1COEFFICIENT_C23(a) (0x000022CC + (a)*0x00000800) +#define NVCC7D_HEAD_SET_OCSC1COEFFICIENT_C23_VALUE 20:0 +#define NVCC7D_HEAD_SET_HEAD_POSITION(a) (0x000022D0 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_HEAD_POSITION_X 2:0 +#define NVCC7D_HEAD_SET_HEAD_POSITION_Y 6:4 +#define NVCC7D_HEAD_SET_DSC_CONTROL(a) (0x000022D4 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_CONTROL_ENABLE 0:0 +#define NVCC7D_HEAD_SET_DSC_CONTROL_ENABLE_FALSE (0x00000000) +#define NVCC7D_HEAD_SET_DSC_CONTROL_ENABLE_TRUE (0x00000001) +#define NVCC7D_HEAD_SET_DSC_CONTROL_AUTO_RESET 3:3 +#define NVCC7D_HEAD_SET_DSC_CONTROL_AUTO_RESET_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_DSC_CONTROL_AUTO_RESET_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION 4:4 +#define NVCC7D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET 5:5 +#define NVCC7D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET_FALSE (0x00000000) +#define NVCC7D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET_TRUE (0x00000001) +#define NVCC7D_HEAD_SET_DSC_CONTROL_FLATNESS_DET_THRESH 15:6 +#define NVCC7D_HEAD_SET_DSC_PPS_CONTROL(a) (0x000022D8 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_CONTROL_ENABLE 0:0 +#define NVCC7D_HEAD_SET_DSC_PPS_CONTROL_ENABLE_FALSE (0x00000000) +#define NVCC7D_HEAD_SET_DSC_PPS_CONTROL_ENABLE_TRUE (0x00000001) +#define NVCC7D_HEAD_SET_DSC_PPS_CONTROL_LOCATION 2:1 +#define NVCC7D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_VBLANK (0x00000000) +#define NVCC7D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_VSYNC (0x00000001) +#define NVCC7D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_LINE (0x00000002) +#define NVCC7D_HEAD_SET_DSC_PPS_CONTROL_SIZE 10:3 +#define NVCC7D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY 11:11 +#define NVCC7D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVCC7D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY_ONCE (0x00000001) +#define NVCC7D_HEAD_SET_DSC_PPS_CONTROL_LINE_ID 26:12 +#define NVCC7D_HEAD_SET_DSC_PPS_CONTROL_LINE_ID_REVERSED 27:27 +#define NVCC7D_HEAD_SET_DSC_PPS_CONTROL_LINE_ID_REVERSED_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_DSC_PPS_CONTROL_LINE_ID_REVERSED_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_DSC_PPS_HEAD(a) (0x000022DC + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_HEAD_BYTE0 7:0 +#define NVCC7D_HEAD_SET_DSC_PPS_HEAD_BYTE1 15:8 +#define NVCC7D_HEAD_SET_DSC_PPS_HEAD_BYTE2 23:16 +#define NVCC7D_HEAD_SET_DSC_PPS_HEAD_BYTE3 31:24 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA0(a) (0x000022E0 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA0_DSC_VERSION_MINOR 3:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA0_DSC_VERSION_MAJOR 7:4 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA0_PPS_IDENTIFIER 15:8 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA0_RESERVED 23:16 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA0_LINEBUF_DEPTH 27:24 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA0_BITS_PER_COMPONENT 31:28 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA1(a) (0x000022E4 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA1_BITS_PER_PIXEL_HIGH 1:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA1_VBR_ENABLE 2:2 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA1_SIMPLE422 3:3 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA1_CONVERT_RGB 4:4 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA1_BLOCK_PRED_ENABLE 5:5 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA1_RESERVED 7:6 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA1_BITS_PER_PIXEL_LOW 15:8 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA1_PIC_HEIGHT_HIGH 23:16 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA1_PIC_HEIGHT_LOW 31:24 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA2(a) (0x000022E8 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA2_PIC_WIDTH_HIGH 7:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA2_PIC_WIDTH_LOW 15:8 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA2_SLICE_HEIGHT_HIGH 23:16 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA2_SLICE_HEIGHT_LOW 31:24 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA3(a) (0x000022EC + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA3_SLICE_WIDTH_HIGH 7:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA3_SLICE_WIDTH_LOW 15:8 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA3_CHUNK_SIZE_HIGH 23:16 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA3_CHUNK_SIZE_LOW 31:24 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA4(a) (0x000022F0 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA4_INITIAL_XMIT_DELAY_HIGH 1:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA4_RESERVED 7:2 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA4_INITIAL_XMIT_DELAY_LOW 15:8 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA4_INITIAL_DEC_DELAY_HIGH 23:16 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA4_INITIAL_DEC_DELAY_LOW 31:24 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA5(a) (0x000022F4 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA5_RESERVED0 7:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA5_INITIAL_SCALE_VALUE 13:8 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA5_RESERVED1 15:14 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA5_SCALE_INCREMENT_INTERVAL_HIGH 23:16 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA5_SCALE_INCREMENT_INTERVAL_LOW 31:24 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA6(a) (0x000022F8 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA6_SCALE_DECREMENT_INTERVAL_HIGH 3:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA6_RESERVED0 7:4 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA6_SCALE_DECREMENT_INTERVAL_LOW 15:8 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA6_RESERVED1 23:16 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA6_FIRST_LINE_BPG_OFFSET 28:24 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA6_RESERVED2 31:29 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA7(a) (0x000022FC + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA7_NFL_BPG_OFFSET_HIGH 7:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA7_NFL_BPG_OFFSET_LOW 15:8 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA7_SLICE_BPG_OFFSET_HIGH 23:16 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA7_SLICE_BPG_OFFSET_LOW 31:24 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA8(a) (0x00002300 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA8_INITIAL_OFFSET_HIGH 7:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA8_INITIAL_OFFSET_LOW 15:8 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA8_FINAL_OFFSET_HIGH 23:16 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA8_FINAL_OFFSET_LOW 31:24 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA9(a) (0x00002304 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA9_FLATNESS_MIN_QP 4:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA9_RESERVED0 7:5 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA9_FLATNESS_MAX_QP 12:8 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA9_RESERVED1 15:13 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA9_RC_MODEL_SIZE_HIGH 23:16 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA9_RC_MODEL_SIZE_LOW 31:24 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA10(a) (0x00002308 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA10_RC_EDGE_FACTOR 3:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA10_RESERVED0 7:4 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA10_RC_QUANT_INCR_LIMIT0 12:8 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA10_RESERVED1 15:13 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA10_RC_QUANT_INCR_LIMIT1 20:16 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA10_RESERVED2 23:21 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA10_RC_TGT_OFFSET_LO 27:24 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA10_RC_TGT_OFFSET_HI 31:28 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA11(a) (0x0000230C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH0 7:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH1 15:8 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH2 23:16 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH3 31:24 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA12(a) (0x00002310 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH4 7:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH5 15:8 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH6 23:16 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH7 31:24 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA13(a) (0x00002314 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH8 7:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH9 15:8 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH10 23:16 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH11 31:24 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA14(a) (0x00002318 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA14_RC_BUF_THRESH12 7:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA14_RC_BUF_THRESH13 15:8 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MAX_QP_HIGH0 18:16 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MIN_QP0 23:19 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_BPG_OFFSET0 29:24 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MAX_QP_LOW0 31:30 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA15(a) (0x0000231C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_HIGH1 2:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MIN_QP1 7:3 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_BPG_OFFSET1 13:8 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_LOW1 15:14 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_HIGH2 18:16 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MIN_QP2 23:19 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_BPG_OFFSET2 29:24 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_LOW2 31:30 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA16(a) (0x00002320 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_HIGH3 2:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MIN_QP3 7:3 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_BPG_OFFSET3 13:8 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_LOW3 15:14 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_HIGH4 18:16 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MIN_QP4 23:19 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_BPG_OFFSET4 29:24 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_LOW4 31:30 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA17(a) (0x00002324 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_HIGH5 2:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MIN_QP5 7:3 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_BPG_OFFSET5 13:8 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_LOW5 15:14 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_HIGH6 18:16 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MIN_QP6 23:19 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_BPG_OFFSET6 29:24 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_LOW6 31:30 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA18(a) (0x00002328 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_HIGH7 2:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MIN_QP7 7:3 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_BPG_OFFSET7 13:8 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_LOW7 15:14 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_HIGH8 18:16 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MIN_QP8 23:19 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_BPG_OFFSET8 29:24 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_LOW8 31:30 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA19(a) (0x0000232C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_HIGH9 2:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MIN_QP9 7:3 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_BPG_OFFSET9 13:8 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_LOW9 15:14 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_HIGH10 18:16 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MIN_QP10 23:19 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_BPG_OFFSET10 29:24 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_LOW10 31:30 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA20(a) (0x00002330 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_HIGH11 2:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MIN_QP11 7:3 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_BPG_OFFSET11 13:8 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_LOW11 15:14 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_HIGH12 18:16 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MIN_QP12 23:19 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_BPG_OFFSET12 29:24 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_LOW12 31:30 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA21(a) (0x00002334 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_HIGH13 2:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MIN_QP13 7:3 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_BPG_OFFSET13 13:8 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_LOW13 15:14 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_HIGH14 18:16 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MIN_QP14 23:19 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_BPG_OFFSET14 29:24 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_LOW14 31:30 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA22(a) (0x00002338 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA22_NATIVE422 0:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA22_NATIVE420 1:1 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA22_RESERVED0 7:2 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA22_SECOND_LINE_BPG_OFFSET 12:8 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA22_RESERVED1 15:13 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA22_NSL_BPG_OFFSET_HIGH 23:16 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA22_NSL_BPG_OFFSETLOW 31:24 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA23(a) (0x0000233C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA23_SECOND_LINE_OFFSET_ADJ_HIGH 7:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA23_SECOND_LINE_OFFSET_ADJ_LOW 15:8 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA23_RESERVED 31:16 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA24(a) (0x00002340 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA24_RESERVED 31:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA25(a) (0x00002344 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA25_RESERVED 31:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA26(a) (0x00002348 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA26_RESERVED 31:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA27(a) (0x0000234C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA27_RESERVED 31:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA28(a) (0x00002350 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA28_RESERVED 31:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA29(a) (0x00002354 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA29_RESERVED 31:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA30(a) (0x00002358 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA30_RESERVED 31:0 +#define NVCC7D_HEAD_SET_DSC_PPS_DATA31(a) (0x0000235C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DSC_PPS_DATA31_RESERVED 31:0 +#define NVCC7D_HEAD_SET_RASTER_HBLANK_DELAY(a) (0x00002364 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_RASTER_HBLANK_DELAY_BLANK_START 15:0 +#define NVCC7D_HEAD_SET_RASTER_HBLANK_DELAY_BLANK_END 31:16 +#define NVCC7D_HEAD_SET_HDMI_DSC_HCACTIVE(a) (0x00002368 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_HDMI_DSC_HCACTIVE_BYTES 15:0 +#define NVCC7D_HEAD_SET_HDMI_DSC_HCACTIVE_TRI_BYTES 31:16 +#define NVCC7D_HEAD_SET_HDMI_DSC_HCBLANK(a) (0x0000236C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_HDMI_DSC_HCBLANK_WIDTH 15:0 +#define NVCC7D_HEAD_SW_RESERVED(a,b) (0x00002370 + (a)*0x00000800 + (b)*0x00000004) +#define NVCC7D_HEAD_SW_RESERVED_VALUE 31:0 +#define NVCC7D_HEAD_SET_DP_CTRL(a) (0x0000237C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DP_CTRL_EFFECTIVE_BITS_PER_PIXEL_ADJ 9:0 +#define NVCC7D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_HI(a,b) (0x00002380 + (a)*0x00000800 + (b)*0x00000004) +#define NVCC7D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_HI_VALUE 31:0 +#define NVCC7D_HEAD_SET_HEAD_INFOFRAME(a) (0x000023A0 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_HEAD_INFOFRAME_FID 7:0 +#define NVCC7D_HEAD_SET_HEAD_INFOFRAME_EN 16:16 +#define NVCC7D_HEAD_SET_HEAD_INFOFRAME_EN_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_HEAD_INFOFRAME_EN_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_INFOFRAME_CTRL(a) (0x000023A4 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_INFOFRAME_CTRL_MODE 1:0 +#define NVCC7D_HEAD_SET_INFOFRAME_CTRL_MODE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_INFOFRAME_CTRL_MODE_EMP_VTEM_QMS (0x00000001) +#define NVCC7D_HEAD_SET_INFOFRAME_CTRL_MODE_EMP_OTHERS (0x00000002) +#define NVCC7D_HEAD_SET_INFOFRAME_CTRL_FREQUENCY 12:12 +#define NVCC7D_HEAD_SET_INFOFRAME_CTRL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVCC7D_HEAD_SET_INFOFRAME_CTRL_FREQUENCY_ONCE (0x00000001) +#define NVCC7D_HEAD_SET_INFOFRAME_CTRL_LOCATION 5:4 +#define NVCC7D_HEAD_SET_INFOFRAME_CTRL_LOCATION_VBLANK (0x00000000) +#define NVCC7D_HEAD_SET_INFOFRAME_CTRL_LOCATION_VSYNC (0x00000001) +#define NVCC7D_HEAD_SET_INFOFRAME_CTRL_LOCATION_LINE (0x00000002) +#define NVCC7D_HEAD_SET_INFOFRAME_CTRL_LINE_ID 30:16 +#define NVCC7D_HEAD_SET_INFOFRAME_CTRL_LINE_ID_REVERSED 31:31 +#define NVCC7D_HEAD_SET_INFOFRAME_CTRL_LINE_ID_REVERSED_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_INFOFRAME_CTRL_LINE_ID_REVERSED_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_INFOFRAME_CTRL_MTD_STATE_CTRL 14:14 +#define NVCC7D_HEAD_SET_INFOFRAME_CTRL_MTD_STATE_CTRL_ACTIVE (0x00000000) +#define NVCC7D_HEAD_SET_INFOFRAME_CTRL_MTD_STATE_CTRL_ARM (0x00000001) +#define NVCC7D_HEAD_SET_INFOFRAME_HEADER(a) (0x000023A8 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_INFOFRAME_HEADER_HB0 7:0 +#define NVCC7D_HEAD_SET_INFOFRAME_HEADER_HB1 15:8 +#define NVCC7D_HEAD_SET_INFOFRAME_HEADER_HB2 23:16 +#define NVCC7D_HEAD_SET_INFOFRAME_HEADER_HB3 31:24 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA0(a) (0x000023AC + (a)*0x00000800) +#define NVCC7D_HEAD_SET_INFOFRAME_DATA0_DB0 7:0 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA0_DB1 15:8 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA0_DB2 23:16 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA0_DB3 31:24 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA1(a) (0x000023B0 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_INFOFRAME_DATA1_DB4 7:0 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA1_DB5 15:8 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA1_DB6 23:16 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA1_DB7 31:24 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA2(a) (0x000023B4 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_INFOFRAME_DATA2_DB8 7:0 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA2_DB9 15:8 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA2_DB10 23:16 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA2_DB11 31:24 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA3(a) (0x000023B8 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_INFOFRAME_DATA3_DB12 7:0 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA3_DB13 15:8 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA3_DB14 23:16 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA3_DB15 31:24 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA4(a) (0x000023BC + (a)*0x00000800) +#define NVCC7D_HEAD_SET_INFOFRAME_DATA4_DB16 7:0 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA4_DB17 15:8 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA4_DB18 23:16 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA4_DB19 31:24 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA5(a) (0x000023C0 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_INFOFRAME_DATA5_DB20 7:0 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA5_DB21 15:8 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA5_DB22 23:16 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA5_DB23 31:24 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA6(a) (0x000023C4 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_INFOFRAME_DATA6_DB24 7:0 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA6_DB25 15:8 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA6_DB26 23:16 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA6_DB27 31:24 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA7(a) (0x000023C8 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_INFOFRAME_DATA7_DB28 7:0 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA7_DB29 15:8 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA7_DB30 23:16 +#define NVCC7D_HEAD_SET_INFOFRAME_DATA7_DB31 31:24 +#define NVCC7D_HEAD_SET_RASTER_SIZE_FRACTION(a) (0x000023CC + (a)*0x00000800) +#define NVCC7D_HEAD_SET_RASTER_SIZE_FRACTION_HEIGHT 15:0 +#define NVCC7D_HEAD_SET_LTM_CONTROL(a) (0x000023D0 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_LTM_CONTROL_ENABLE 0:0 +#define NVCC7D_HEAD_SET_LTM_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_LTM_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_LTM_CONTROL_MODE 1:1 +#define NVCC7D_HEAD_SET_LTM_CONTROL_MODE_TMO (0x00000000) +#define NVCC7D_HEAD_SET_LTM_CONTROL_MODE_LTM (0x00000001) +#define NVCC7D_HEAD_SET_LTM_CONTROL_TONE_SELECT 2:2 +#define NVCC7D_HEAD_SET_LTM_CONTROL_TONE_SELECT_INTENSITY (0x00000000) +#define NVCC7D_HEAD_SET_LTM_CONTROL_TONE_SELECT_CDB (0x00000001) +#define NVCC7D_HEAD_SET_LTM_CONTROL_SKIN_TONE_ENABLE 3:3 +#define NVCC7D_HEAD_SET_LTM_CONTROL_SKIN_TONE_ENABLE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_LTM_CONTROL_SKIN_TONE_ENABLE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_LTM_CONTROL_LUT_INTERPOLATE 4:4 +#define NVCC7D_HEAD_SET_LTM_CONTROL_LUT_INTERPOLATE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_LTM_CONTROL_LUT_INTERPOLATE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT8 5:5 +#define NVCC7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT8_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT8_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT10 6:6 +#define NVCC7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT10_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT10_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT_ROUND 7:7 +#define NVCC7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT_ROUND_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_LTM_CONTROL_LUT_DIRECT_ROUND_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_LTM_CONTROL_HIST_SOURCE 9:8 +#define NVCC7D_HEAD_SET_LTM_CONTROL_HIST_SOURCE_MAX_RGB (0x00000000) +#define NVCC7D_HEAD_SET_LTM_CONTROL_HIST_SOURCE_LIN_I (0x00000001) +#define NVCC7D_HEAD_SET_LTM_CONTROL_HIST_SOURCE_PQI (0x00000002) +#define NVCC7D_HEAD_SET_LTM_CONTROL_HIST_SOURCE_CDB (0x00000003) +#define NVCC7D_HEAD_SET_LTM_CONTROL_HIST_RANGE 11:10 +#define NVCC7D_HEAD_SET_LTM_CONTROL_HIST_RANGE_RANGE_10000 (0x00000000) +#define NVCC7D_HEAD_SET_LTM_CONTROL_HIST_RANGE_RANGE_5000 (0x00000001) +#define NVCC7D_HEAD_SET_LTM_CONTROL_HIST_RANGE_RANGE_2500 (0x00000002) +#define NVCC7D_HEAD_SET_LTM_CONTROL_HIST_RANGE_RANGE_1250 (0x00000003) +#define NVCC7D_HEAD_SET_LTM_CONTROL_HIST_END_LINE 31:16 +#define NVCC7D_HEAD_SET_RGB2ITP_COEFF_C00(a) (0x000023D4 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_RGB2ITP_COEFF_C00_VALUE 20:0 +#define NVCC7D_HEAD_SET_RGB2ITP_COEFF_C01(a) (0x000023D8 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_RGB2ITP_COEFF_C01_VALUE 20:0 +#define NVCC7D_HEAD_SET_RGB2ITP_COEFF_C02(a) (0x000023DC + (a)*0x00000800) +#define NVCC7D_HEAD_SET_RGB2ITP_COEFF_C02_VALUE 20:0 +#define NVCC7D_HEAD_SET_RGB2ITP_COEFF_C03(a) (0x000023E0 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_RGB2ITP_COEFF_C03_VALUE 20:0 +#define NVCC7D_HEAD_SET_RGB2ITP_COEFF_C10(a) (0x000023E4 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_RGB2ITP_COEFF_C10_VALUE 20:0 +#define NVCC7D_HEAD_SET_RGB2ITP_COEFF_C11(a) (0x000023E8 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_RGB2ITP_COEFF_C11_VALUE 20:0 +#define NVCC7D_HEAD_SET_RGB2ITP_COEFF_C12(a) (0x000023EC + (a)*0x00000800) +#define NVCC7D_HEAD_SET_RGB2ITP_COEFF_C12_VALUE 20:0 +#define NVCC7D_HEAD_SET_RGB2ITP_COEFF_C13(a) (0x000023F0 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_RGB2ITP_COEFF_C13_VALUE 20:0 +#define NVCC7D_HEAD_SET_RGB2ITP_COEFF_C20(a) (0x000023F4 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_RGB2ITP_COEFF_C20_VALUE 20:0 +#define NVCC7D_HEAD_SET_RGB2ITP_COEFF_C21(a) (0x000023F8 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_RGB2ITP_COEFF_C21_VALUE 20:0 +#define NVCC7D_HEAD_SET_RGB2ITP_COEFF_C22(a) (0x000023FC + (a)*0x00000800) +#define NVCC7D_HEAD_SET_RGB2ITP_COEFF_C22_VALUE 20:0 +#define NVCC7D_HEAD_SET_RGB2ITP_COEFF_C23(a) (0x00002400 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_RGB2ITP_COEFF_C23_VALUE 20:0 +#define NVCC7D_HEAD_SET_ITP2RGB_COEFF_C00(a) (0x00002404 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_ITP2RGB_COEFF_C00_VALUE 20:0 +#define NVCC7D_HEAD_SET_ITP2RGB_COEFF_C01(a) (0x00002408 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_ITP2RGB_COEFF_C01_VALUE 20:0 +#define NVCC7D_HEAD_SET_ITP2RGB_COEFF_C02(a) (0x0000240C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_ITP2RGB_COEFF_C02_VALUE 20:0 +#define NVCC7D_HEAD_SET_ITP2RGB_COEFF_C03(a) (0x00002410 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_ITP2RGB_COEFF_C03_VALUE 20:0 +#define NVCC7D_HEAD_SET_ITP2RGB_COEFF_C10(a) (0x00002414 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_ITP2RGB_COEFF_C10_VALUE 20:0 +#define NVCC7D_HEAD_SET_ITP2RGB_COEFF_C11(a) (0x00002418 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_ITP2RGB_COEFF_C11_VALUE 20:0 +#define NVCC7D_HEAD_SET_ITP2RGB_COEFF_C12(a) (0x0000241C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_ITP2RGB_COEFF_C12_VALUE 20:0 +#define NVCC7D_HEAD_SET_ITP2RGB_COEFF_C13(a) (0x00002420 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_ITP2RGB_COEFF_C13_VALUE 20:0 +#define NVCC7D_HEAD_SET_ITP2RGB_COEFF_C20(a) (0x00002424 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_ITP2RGB_COEFF_C20_VALUE 20:0 +#define NVCC7D_HEAD_SET_ITP2RGB_COEFF_C21(a) (0x00002428 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_ITP2RGB_COEFF_C21_VALUE 20:0 +#define NVCC7D_HEAD_SET_ITP2RGB_COEFF_C22(a) (0x0000242C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_ITP2RGB_COEFF_C22_VALUE 20:0 +#define NVCC7D_HEAD_SET_ITP2RGB_COEFF_C23(a) (0x00002430 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_ITP2RGB_COEFF_C23_VALUE 20:0 +#define NVCC7D_HEAD_SET_LTM_MAX_SELECTIVE_UPDATE(a) (0x00002434 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_LTM_MAX_SELECTIVE_UPDATE_SIZE 31:0 +#define NVCC7D_HEAD_SET_SELF_REFRESH_OVERRIDE(a) (0x00002438 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_SELF_REFRESH_OVERRIDE_FRAME_RELEASE 0:0 +#define NVCC7D_HEAD_SET_SELF_REFRESH_OVERRIDE_FRAME_RELEASE_AUTOMATIC (0x00000000) +#define NVCC7D_HEAD_SET_SELF_REFRESH_OVERRIDE_FRAME_RELEASE_MANUAL (0x00000001) +#define NVCC7D_HEAD_SET_SELECTIVE_UPDATE(a) (0x0000243C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_SELECTIVE_UPDATE_ENABLE 0:0 +#define NVCC7D_HEAD_SET_SELECTIVE_UPDATE_ENABLE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_SELECTIVE_UPDATE_ENABLE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_SELECTIVE_UPDATE_EARLY_REGION 1:1 +#define NVCC7D_HEAD_SET_SELECTIVE_UPDATE_EARLY_REGION_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_SELECTIVE_UPDATE_EARLY_REGION_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_CURSOR_DIRTY(a) (0x00002440 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_CURSOR_DIRTY_STATE 0:0 +#define NVCC7D_HEAD_SET_CURSOR_DIRTY_STATE_FALSE (0x00000000) +#define NVCC7D_HEAD_SET_CURSOR_DIRTY_STATE_TRUE (0x00000001) +#define NVCC7D_HEAD_SET_DPM_CONTROL(a) (0x00002444 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_DPM_CONTROL_ENABLE 0:0 +#define NVCC7D_HEAD_SET_DPM_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_DPM_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_DPM_CONTROL_ALPM 1:1 +#define NVCC7D_HEAD_SET_DPM_CONTROL_ALPM_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_DPM_CONTROL_ALPM_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_DPM_CONTROL_ALPM_TYPE 2:2 +#define NVCC7D_HEAD_SET_DPM_CONTROL_ALPM_TYPE_AUX_LESS (0x00000000) +#define NVCC7D_HEAD_SET_DPM_CONTROL_AS_SDP 3:3 +#define NVCC7D_HEAD_SET_DPM_CONTROL_AS_SDP_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_DPM_CONTROL_AS_SDP_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL(a) (0x00002448 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_ENABLE 0:0 +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_ENABLE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_ENABLE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_SELF_REFRESH 1:1 +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_SELF_REFRESH_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_SELF_REFRESH_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_MODE 3:2 +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_MODE_PSR1 (0x00000000) +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_MODE_PANEL_REPLAY (0x00000002) +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_CRC 4:4 +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_CRC_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_CRC_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_LOCATION 7:6 +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_LOCATION_VBLANK (0x00000000) +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_LOCATION_VSYNC (0x00000001) +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_LOCATION_LINE (0x00000002) +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_LINE_ID 22:8 +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_CAPTURE_INDICATOR 23:23 +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_CAPTURE_INDICATOR_SAME (0x00000000) +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_CAPTURE_INDICATOR_EARLY (0x00000001) +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_IDLE_SDP 24:24 +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_IDLE_SDP_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_IDLE_SDP_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_OVERRIDE_SU_VSC 25:25 +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_OVERRIDE_SU_VSC_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_VSC_SDP_CTRL_OVERRIDE_SU_VSC_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_VSC_SDP_HEADER(a) (0x0000244C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_VSC_SDP_HEADER_HEADER_BYTE 31:0 +#define NVCC7D_HEAD_SET_VSC_SDP_DATA0(a) (0x00002450 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_VSC_SDP_DATA0_DATA_BYTE 31:0 +#define NVCC7D_HEAD_SET_VSC_SDP_DATA1(a) (0x00002454 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_VSC_SDP_DATA1_DATA_BYTE 31:0 +#define NVCC7D_HEAD_SET_VSC_SDP_DATA2(a) (0x00002458 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_VSC_SDP_DATA2_DATA_BYTE 31:0 +#define NVCC7D_HEAD_SET_VSC_SDP_DATA3(a) (0x0000245C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_VSC_SDP_DATA3_DATA_BYTE 31:0 +#define NVCC7D_HEAD_SET_VSC_SDP_DATA4(a) (0x00002460 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_VSC_SDP_DATA4_DATA_BYTE 31:0 +#define NVCC7D_HEAD_SET_VSC_SDP_DATA5(a) (0x00002464 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_VSC_SDP_DATA5_DATA_BYTE 31:0 +#define NVCC7D_HEAD_SET_VSC_SDP_DATA6(a) (0x00002468 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_VSC_SDP_DATA6_DATA_BYTE 31:0 +#define NVCC7D_HEAD_SET_VSC_SDP_DATA7(a) (0x0000246C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_VSC_SDP_DATA7_DATA_BYTE 31:0 +#define NVCC7D_HEAD_SET_RGB2ITP_CONTROL(a) (0x00002470 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_INPUT_MATRIX 0:0 +#define NVCC7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_INPUT_MATRIX_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_INPUT_MATRIX_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_FVLUT 1:1 +#define NVCC7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_FVLUT_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_FVLUT_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_INTERPOLATE 4:4 +#define NVCC7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_INTERPOLATE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_INTERPOLATE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_MIRROR 5:5 +#define NVCC7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_MIRROR_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_MIRROR_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_CURVE 7:6 +#define NVCC7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_CURVE_CSCLUT_PQ (0x00000000) +#define NVCC7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_CURVE_CSCLUT_HLG (0x00000001) +#define NVCC7D_HEAD_SET_RGB2ITP_CONTROL_FVLUT_CURVE_CSCLUT_DIRECT (0x00000002) +#define NVCC7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_OUTPUT_MATRIX 2:2 +#define NVCC7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_OUTPUT_MATRIX_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_RGB2ITP_CONTROL_ENABLE_OUTPUT_MATRIX_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_RGB2ITP_LUT_FP_NORM_SCALE(a) (0x00002474 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_RGB2ITP_LUT_FP_NORM_SCALE_VALUE 31:0 +#define NVCC7D_HEAD_SET_ITP2RGB_CONTROL(a) (0x00002478 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_INPUT_MATRIX 0:0 +#define NVCC7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_INPUT_MATRIX_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_INPUT_MATRIX_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_FVLUT 1:1 +#define NVCC7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_FVLUT_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_FVLUT_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_INTERPOLATE 4:4 +#define NVCC7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_INTERPOLATE_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_INTERPOLATE_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_MIRROR 5:5 +#define NVCC7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_MIRROR_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_MIRROR_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_CURVE 7:6 +#define NVCC7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_CURVE_CSCLUT_PQ (0x00000000) +#define NVCC7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_CURVE_CSCLUT_HLG (0x00000001) +#define NVCC7D_HEAD_SET_ITP2RGB_CONTROL_FVLUT_CURVE_CSCLUT_DIRECT (0x00000002) +#define NVCC7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_OUTPUT_MATRIX 2:2 +#define NVCC7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_OUTPUT_MATRIX_DISABLE (0x00000000) +#define NVCC7D_HEAD_SET_ITP2RGB_CONTROL_ENABLE_OUTPUT_MATRIX_ENABLE (0x00000001) +#define NVCC7D_HEAD_SET_ITP2RGB_LUT_FP_SCALE(a) (0x0000247C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_ITP2RGB_LUT_FP_SCALE_VALUE 15:0 +#define NVCC7D_HEAD_SET_BLANK_OUTPUT_COLOR(a) (0x00002484 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_BLANK_OUTPUT_COLOR_RED_CR 9:0 +#define NVCC7D_HEAD_SET_BLANK_OUTPUT_COLOR_GREEN_Y 19:10 +#define NVCC7D_HEAD_SET_BLANK_OUTPUT_COLOR_BLUE_CB 29:20 +#define NVCC7D_HEAD_SET_SELECTIVE_UPDATE_GRANULARITY(a) (0x0000249C + (a)*0x00000800) +#define NVCC7D_HEAD_SET_SELECTIVE_UPDATE_GRANULARITY_X 15:0 +#define NVCC7D_HEAD_SET_SELECTIVE_UPDATE_GRANULARITY_Y 31:16 +#define NVCC7D_HEAD_SET_LTM_HIST_COEFF_C00(a) (0x000024A0 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_LTM_HIST_COEFF_C00_VALUE 20:0 +#define NVCC7D_HEAD_SET_LTM_HIST_COEFF_C01(a) (0x000024A4 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_LTM_HIST_COEFF_C01_VALUE 20:0 +#define NVCC7D_HEAD_SET_LTM_HIST_COEFF_C02(a) (0x000024A8 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_LTM_HIST_COEFF_C02_VALUE 20:0 +#define NVCC7D_HEAD_SET_LTM_HIST_COEFF_C03(a) (0x000024AC + (a)*0x00000800) +#define NVCC7D_HEAD_SET_LTM_HIST_COEFF_C03_VALUE 20:0 +#define NVCC7D_HEAD_SET_LTM_HIST_COEFF_C10(a) (0x000024B0 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_LTM_HIST_COEFF_C10_VALUE 20:0 +#define NVCC7D_HEAD_SET_LTM_HIST_COEFF_C11(a) (0x000024B4 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_LTM_HIST_COEFF_C11_VALUE 20:0 +#define NVCC7D_HEAD_SET_LTM_HIST_COEFF_C12(a) (0x000024B8 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_LTM_HIST_COEFF_C12_VALUE 20:0 +#define NVCC7D_HEAD_SET_LTM_HIST_COEFF_C13(a) (0x000024BC + (a)*0x00000800) +#define NVCC7D_HEAD_SET_LTM_HIST_COEFF_C13_VALUE 20:0 +#define NVCC7D_HEAD_SET_LTM_HIST_COEFF_C20(a) (0x000024C0 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_LTM_HIST_COEFF_C20_VALUE 20:0 +#define NVCC7D_HEAD_SET_LTM_HIST_COEFF_C21(a) (0x000024C4 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_LTM_HIST_COEFF_C21_VALUE 20:0 +#define NVCC7D_HEAD_SET_LTM_HIST_COEFF_C22(a) (0x000024C8 + (a)*0x00000800) +#define NVCC7D_HEAD_SET_LTM_HIST_COEFF_C22_VALUE 20:0 +#define NVCC7D_HEAD_SET_LTM_HIST_COEFF_C23(a) (0x000024CC + (a)*0x00000800) +#define NVCC7D_HEAD_SET_LTM_HIST_COEFF_C23_VALUE 20:0 + +#define NVCC7D_TILE_SET_TILE_SIZE(a) (0x00006000 + (a)*0x00000200) +#define NVCC7D_TILE_SET_TILE_SIZE_START 14:0 +#define NVCC7D_TILE_SET_TILE_SIZE_WIDTH 30:16 +#define NVCC7D_TILE_SET_CMI_LUT_SEGMENT_SIZE(a) (0x00006074 + (a)*0x00000200) +#define NVCC7D_TILE_SET_CMI_LUT_SEGMENT_SIZE_IDX 5:0 +#define NVCC7D_TILE_SET_CMI_LUT_SEGMENT_SIZE_VALUE 8:6 +#define NVCC7D_TILE_SET_CMI_LUT_ENTRY(a) (0x00006078 + (a)*0x00000200) +#define NVCC7D_TILE_SET_CMI_LUT_ENTRY_IDX 10:0 +#define NVCC7D_TILE_SET_CMI_LUT_ENTRY_VALUE 24:11 +#define NVCC7D_TILE_SET_CMI_LUT_ENTRY_LAST 25:25 +#define NVCC7D_TILE_SET_CMI_LUT_ENTRY_LAST_FALSE (0x00000000) +#define NVCC7D_TILE_SET_CMI_LUT_ENTRY_LAST_TRUE (0x00000001) +#define NVCC7D_TILE_SET_CMO_LUT_SEGMENT_SIZE(a) (0x0000607C + (a)*0x00000200) +#define NVCC7D_TILE_SET_CMO_LUT_SEGMENT_SIZE_IDX 5:0 +#define NVCC7D_TILE_SET_CMO_LUT_SEGMENT_SIZE_VALUE 8:6 +#define NVCC7D_TILE_SET_CMO_LUT_ENTRY(a) (0x00006080 + (a)*0x00000200) +#define NVCC7D_TILE_SET_CMO_LUT_ENTRY_IDX 10:0 +#define NVCC7D_TILE_SET_CMO_LUT_ENTRY_VALUE 26:11 +#define NVCC7D_TILE_SET_CMO_LUT_ENTRY_LAST 27:27 +#define NVCC7D_TILE_SET_CMO_LUT_ENTRY_LAST_FALSE (0x00000000) +#define NVCC7D_TILE_SET_CMO_LUT_ENTRY_LAST_TRUE (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clcc7d_h diff --git a/userspace/sdks/nv570/inc/class/clcc7e.h b/userspace/sdks/nv570/inc/class/clcc7e.h new file mode 100644 index 0000000..4475183 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcc7e.h @@ -0,0 +1,917 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clcc7e_h_ +#define _clcc7e_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVCC7E_WINDOW_CHANNEL_DMA (0x0000CC7E) + +// dma opcode instructions +#define NVCC7E_DMA +#define NVCC7E_DMA_OPCODE 31:29 +#define NVCC7E_DMA_OPCODE_METHOD 0x00000000 +#define NVCC7E_DMA_OPCODE_JUMP 0x00000001 +#define NVCC7E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVCC7E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVCC7E_DMA_METHOD_COUNT 27:18 +#define NVCC7E_DMA_METHOD_OFFSET 15:2 +#define NVCC7E_DMA_DATA 31:0 +#define NVCC7E_DMA_DATA_NOP 0x00000000 +#define NVCC7E_DMA_JUMP_OFFSET 15:2 +#define NVCC7E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVCC7E_PUT (0x00000000) +#define NVCC7E_PUT_PTR 13:0 +#define NVCC7E_GET (0x00000004) +#define NVCC7E_GET_PTR 13:0 +#define NVCC7E_UPDATE (0x00000200) +#define NVCC7E_UPDATE_RELEASE_ELV 0:0 +#define NVCC7E_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVCC7E_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVCC7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVCC7E_UPDATE_INTERLOCK_WITH_WIN_IMM 12:12 +#define NVCC7E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE (0x00000000) +#define NVCC7E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE (0x00000001) +#define NVCC7E_UPDATE_FORCE_FULLSCREEN 16:16 +#define NVCC7E_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000) +#define NVCC7E_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001) +#define NVCC7E_SET_SEMAPHORE_ACQUIRE_HI (0x00000204) +#define NVCC7E_SET_SEMAPHORE_ACQUIRE_HI_VALUE 31:0 +#define NVCC7E_GET_LINE (0x00000208) +#define NVCC7E_GET_LINE_LINE 15:0 +#define NVCC7E_SET_SEMAPHORE_CONTROL (0x0000020C) +#define NVCC7E_SET_SEMAPHORE_CONTROL_SKIP_ACQ 11:11 +#define NVCC7E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_FALSE (0x00000000) +#define NVCC7E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_TRUE (0x00000001) +#define NVCC7E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVCC7E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVCC7E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVCC7E_SET_SEMAPHORE_CONTROL_ACQ_MODE 13:12 +#define NVCC7E_SET_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000) +#define NVCC7E_SET_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001) +#define NVCC7E_SET_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002) +#define NVCC7E_SET_SEMAPHORE_CONTROL_REL_MODE 14:14 +#define NVCC7E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE (0x00000000) +#define NVCC7E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE_AWAKEN (0x00000001) +#define NVCC7E_SET_SEMAPHORE_ACQUIRE (0x00000210) +#define NVCC7E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NVCC7E_SET_SEMAPHORE_RELEASE (0x00000214) +#define NVCC7E_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NVCC7E_SET_NOTIFIER_CONTROL (0x00000220) +#define NVCC7E_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVCC7E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVCC7E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVCC7E_SET_SIZE (0x00000224) +#define NVCC7E_SET_SIZE_WIDTH 15:0 +#define NVCC7E_SET_SIZE_HEIGHT 31:16 +#define NVCC7E_SET_STORAGE (0x00000228) +#define NVCC7E_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NVCC7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NVCC7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NVCC7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NVCC7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVCC7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVCC7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVCC7E_SET_PARAMS (0x0000022C) +#define NVCC7E_SET_PARAMS_FORMAT 7:0 +#define NVCC7E_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NVCC7E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F) +#define NVCC7E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NVCC7E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NVCC7E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E) +#define NVCC7E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NVCC7E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6) +#define NVCC7E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NVCC7E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9) +#define NVCC7E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NVCC7E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NVCC7E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NVCC7E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NVCC7E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NVCC7E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028) +#define NVCC7E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029) +#define NVCC7E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035) +#define NVCC7E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036) +#define NVCC7E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038) +#define NVCC7E_SET_PARAMS_FORMAT_Y8___U8___V8_N444 (0x0000003A) +#define NVCC7E_SET_PARAMS_FORMAT_Y8___U8___V8_N420 (0x0000003B) +#define NVCC7E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055) +#define NVCC7E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056) +#define NVCC7E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058) +#define NVCC7E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075) +#define NVCC7E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076) +#define NVCC7E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078) +#define NVCC7E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18 +#define NVCC7E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000) +#define NVCC7E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001) +#define NVCC7E_SET_PARAMS_SWAP_UV 19:19 +#define NVCC7E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000) +#define NVCC7E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001) +#define NVCC7E_SET_PARAMS_FMT_ROUNDING_MODE 22:22 +#define NVCC7E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_TO_NEAREST (0x00000000) +#define NVCC7E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_DOWN (0x00000001) +#define NVCC7E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004) +#define NVCC7E_SET_PLANAR_STORAGE_PITCH 12:0 +#define NVCC7E_SET_SEMAPHORE_RELEASE_HI (0x0000023C) +#define NVCC7E_SET_SEMAPHORE_RELEASE_HI_VALUE 31:0 +#define NVCC7E_SET_SURFACE_ADDRESS_HI_BEGUN_SEMAPHORE_ARRAY (0x00000240) +#define NVCC7E_SET_SURFACE_ADDRESS_HI_BEGUN_SEMAPHORE_ARRAY_ADDRESS_HI 31:0 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY (0x00000244) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ADDRESS_LO 31:4 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET 3:2 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_IOVA (0x00000000) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ENABLE 0:0 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ENABLE_DISABLE (0x00000000) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ENABLE_ENABLE (0x00000001) +#define NVCC7E_SET_SURFACE_ADDRESS_HI_FINISH_SEMAPHORE_ARRAY (0x00000248) +#define NVCC7E_SET_SURFACE_ADDRESS_HI_FINISH_SEMAPHORE_ARRAY_ADDRESS_HI 31:0 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY (0x0000024C) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ADDRESS_LO 31:4 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET 3:2 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_IOVA (0x00000000) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ENABLE 0:0 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ENABLE_DISABLE (0x00000000) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ENABLE_ENABLE (0x00000001) +#define NVCC7E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004) +#define NVCC7E_SET_POINT_IN_X 15:0 +#define NVCC7E_SET_POINT_IN_Y 31:16 +#define NVCC7E_SET_SIZE_IN (0x00000298) +#define NVCC7E_SET_SIZE_IN_WIDTH 15:0 +#define NVCC7E_SET_SIZE_IN_HEIGHT 31:16 +#define NVCC7E_SET_SIZE_OUT (0x000002A4) +#define NVCC7E_SET_SIZE_OUT_WIDTH 15:0 +#define NVCC7E_SET_SIZE_OUT_HEIGHT 31:16 +#define NVCC7E_SET_CONTROL_INPUT_SCALER (0x000002A8) +#define NVCC7E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVCC7E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVCC7E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVCC7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVCC7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVCC7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVCC7E_SET_CONTROL_INPUT_SCALER_VERTICAL_FORCE_ENABLE 8:8 +#define NVCC7E_SET_CONTROL_INPUT_SCALER_VERTICAL_FORCE_ENABLE_DISABLE (0x00000000) +#define NVCC7E_SET_CONTROL_INPUT_SCALER_VERTICAL_FORCE_ENABLE_ENABLE (0x00000001) +#define NVCC7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_FORCE_ENABLE 9:9 +#define NVCC7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_FORCE_ENABLE_DISABLE (0x00000000) +#define NVCC7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_FORCE_ENABLE_ENABLE (0x00000001) +#define NVCC7E_SET_INPUT_SCALER_COEFF_VALUE (0x000002AC) +#define NVCC7E_SET_INPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVCC7E_SET_INPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVCC7E_SET_COMPOSITION_CONTROL (0x000002EC) +#define NVCC7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0 +#define NVCC7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000) +#define NVCC7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001) +#define NVCC7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002) +#define NVCC7E_SET_COMPOSITION_CONTROL_DEPTH 11:4 +#define NVCC7E_SET_COMPOSITION_CONTROL_BYPASS 16:16 +#define NVCC7E_SET_COMPOSITION_CONTROL_BYPASS_DISABLE (0x00000000) +#define NVCC7E_SET_COMPOSITION_CONTROL_BYPASS_ENABLE (0x00000001) +#define NVCC7E_SET_COMPOSITION_CONSTANT_ALPHA (0x000002F0) +#define NVCC7E_SET_COMPOSITION_CONSTANT_ALPHA_K1 7:0 +#define NVCC7E_SET_COMPOSITION_CONSTANT_ALPHA_K2 15:8 +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT (0x000002F4) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0 +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4 +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8 +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12 +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16 +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20 +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24 +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28 +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVCC7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVCC7E_SET_KEY_ALPHA (0x000002F8) +#define NVCC7E_SET_KEY_ALPHA_MIN 15:0 +#define NVCC7E_SET_KEY_ALPHA_MAX 31:16 +#define NVCC7E_SET_KEY_RED_CR (0x000002FC) +#define NVCC7E_SET_KEY_RED_CR_MIN 15:0 +#define NVCC7E_SET_KEY_RED_CR_MAX 31:16 +#define NVCC7E_SET_KEY_GREEN_Y (0x00000300) +#define NVCC7E_SET_KEY_GREEN_Y_MIN 15:0 +#define NVCC7E_SET_KEY_GREEN_Y_MAX 31:16 +#define NVCC7E_SET_KEY_BLUE_CB (0x00000304) +#define NVCC7E_SET_KEY_BLUE_CB_MIN 15:0 +#define NVCC7E_SET_KEY_BLUE_CB_MAX 31:16 +#define NVCC7E_SET_PRESENT_CONTROL (0x00000308) +#define NVCC7E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NVCC7E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4 +#define NVCC7E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NVCC7E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NVCC7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8 +#define NVCC7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000) +#define NVCC7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001) +#define NVCC7E_SET_PRESENT_CONTROL_STEREO_MODE 13:12 +#define NVCC7E_SET_PRESENT_CONTROL_STEREO_MODE_MONO (0x00000000) +#define NVCC7E_SET_PRESENT_CONTROL_STEREO_MODE_PAIR_FLIP (0x00000001) +#define NVCC7E_SET_PRESENT_CONTROL_STEREO_MODE_AT_ANY_FRAME (0x00000002) +#define NVCC7E_SET_ACQ_SEMAPHORE_VALUE_HI (0x0000030C) +#define NVCC7E_SET_ACQ_SEMAPHORE_VALUE_HI_VALUE 31:0 +#define NVCC7E_SET_ACQ_SEMAPHORE_CONTROL (0x00000330) +#define NVCC7E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVCC7E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVCC7E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVCC7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE 13:12 +#define NVCC7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000) +#define NVCC7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001) +#define NVCC7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002) +#define NVCC7E_SET_ACQ_SEMAPHORE_VALUE (0x00000334) +#define NVCC7E_SET_ACQ_SEMAPHORE_VALUE_VALUE 31:0 +#define NVCC7E_SET_SCAN_DIRECTION (0x0000033C) +#define NVCC7E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION 0:0 +#define NVCC7E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_LEFT (0x00000000) +#define NVCC7E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_RIGHT (0x00000001) +#define NVCC7E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION 1:1 +#define NVCC7E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_TOP (0x00000000) +#define NVCC7E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_BOTTOM (0x00000001) +#define NVCC7E_SET_SCAN_DIRECTION_COLUMN_ORDER 2:2 +#define NVCC7E_SET_SCAN_DIRECTION_COLUMN_ORDER_FALSE (0x00000000) +#define NVCC7E_SET_SCAN_DIRECTION_COLUMN_ORDER_TRUE (0x00000001) +#define NVCC7E_SET_TIMESTAMP_ORIGIN_LO (0x00000340) +#define NVCC7E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NVCC7E_SET_TIMESTAMP_ORIGIN_HI (0x00000344) +#define NVCC7E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NVCC7E_SET_UPDATE_TIMESTAMP_LO (0x00000348) +#define NVCC7E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NVCC7E_SET_UPDATE_TIMESTAMP_HI (0x0000034C) +#define NVCC7E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NVCC7E_SET_INTERLOCK_FLAGS (0x00000370) +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 0:0 +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+1):((i)+1) +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 1:1 +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 2:2 +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 3:3 +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 4:4 +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 5:5 +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 6:6 +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 7:7 +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 8:8 +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVCC7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS (0x00000374) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVCC7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVCC7E_SET_CHROMA_VER (0x00000378) +#define NVCC7E_SET_CHROMA_VER_POSITION 1:0 +#define NVCC7E_SET_CHROMA_VER_POSITION_TOP (0x00000000) +#define NVCC7E_SET_CHROMA_VER_POSITION_CENTER (0x00000001) +#define NVCC7E_SET_CHROMA_VER_POSITION_BOTTOM (0x00000002) +#define NVCC7E_SET_CHROMA_VER_USE_SWPOSITION 2:2 +#define NVCC7E_SET_CHROMA_VER_USE_SWPOSITION_FALSE (0x00000000) +#define NVCC7E_SET_CHROMA_VER_USE_SWPOSITION_TRUE (0x00000001) +#define NVCC7E_SET_CHROMA_VER_WEIGHT_ODD 4:3 +#define NVCC7E_SET_CHROMA_VER_WEIGHT_ODD_WT_0 (0x00000000) +#define NVCC7E_SET_CHROMA_VER_WEIGHT_ODD_WT_QUARTER (0x00000001) +#define NVCC7E_SET_CHROMA_VER_WEIGHT_ODD_WT_HALF (0x00000002) +#define NVCC7E_SET_CHROMA_VER_WEIGHT_ODD_WT_THREE_QUARTER (0x00000003) +#define NVCC7E_SET_CHROMA_VER_WEIGHT_EVEN 6:5 +#define NVCC7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_0 (0x00000000) +#define NVCC7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_QUARTER (0x00000001) +#define NVCC7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_HALF (0x00000002) +#define NVCC7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_THREE_QUARTER (0x00000003) +#define NVCC7E_SET_CHROMA_VER_USE_SWWEIGHTS 7:7 +#define NVCC7E_SET_CHROMA_VER_USE_SWWEIGHTS_FALSE (0x00000000) +#define NVCC7E_SET_CHROMA_VER_USE_SWWEIGHTS_TRUE (0x00000001) +#define NVCC7E_SET_CHROMA_HOR (0x0000037C) +#define NVCC7E_SET_CHROMA_HOR_REPLACE_ODD 0:0 +#define NVCC7E_SET_CHROMA_HOR_REPLACE_ODD_DISABLE (0x00000000) +#define NVCC7E_SET_CHROMA_HOR_REPLACE_ODD_ENABLE (0x00000001) +#define NVCC7E_SET_CHROMA_HOR_REPLACE_EVEN 1:1 +#define NVCC7E_SET_CHROMA_HOR_REPLACE_EVEN_DISABLE (0x00000000) +#define NVCC7E_SET_CHROMA_HOR_REPLACE_EVEN_ENABLE (0x00000001) +#define NVCC7E_SET_CHROMA_HOR_WEIGHT_ODD 3:2 +#define NVCC7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_0 (0x00000000) +#define NVCC7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_QUARTER (0x00000001) +#define NVCC7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_HALF (0x00000002) +#define NVCC7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_THREE_QUARTER (0x00000003) +#define NVCC7E_SET_CHROMA_HOR_WEIGHT_EVEN 5:4 +#define NVCC7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_0 (0x00000000) +#define NVCC7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_QUARTER (0x00000001) +#define NVCC7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_HALF (0x00000002) +#define NVCC7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_THREE_QUARTER (0x00000003) +#define NVCC7E_SET_CHROMA_HOR_USE_SWWEIGHTS 6:6 +#define NVCC7E_SET_CHROMA_HOR_USE_SWWEIGHTS_FALSE (0x00000000) +#define NVCC7E_SET_CHROMA_HOR_USE_SWWEIGHTS_TRUE (0x00000001) +#define NVCC7E_SET_EXT_PACKET_CONTROL (0x00000398) +#define NVCC7E_SET_EXT_PACKET_CONTROL_ENABLE 0:0 +#define NVCC7E_SET_EXT_PACKET_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCC7E_SET_EXT_PACKET_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCC7E_SET_EXT_PACKET_CONTROL_LOCATION 4:4 +#define NVCC7E_SET_EXT_PACKET_CONTROL_LOCATION_VSYNC (0x00000000) +#define NVCC7E_SET_EXT_PACKET_CONTROL_LOCATION_VBLANK (0x00000001) +#define NVCC7E_SET_EXT_PACKET_CONTROL_FREQUENCY 8:8 +#define NVCC7E_SET_EXT_PACKET_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVCC7E_SET_EXT_PACKET_CONTROL_FREQUENCY_ONCE (0x00000001) +#define NVCC7E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE 12:12 +#define NVCC7E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_DISABLE (0x00000000) +#define NVCC7E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_ENABLE (0x00000001) +#define NVCC7E_SET_EXT_PACKET_CONTROL_SIZE 27:16 +#define NVCC7E_SET_EXT_PACKET_DATA (0x0000039C) +#define NVCC7E_SET_EXT_PACKET_DATA_DB0 7:0 +#define NVCC7E_SET_EXT_PACKET_DATA_DB1 15:8 +#define NVCC7E_SET_EXT_PACKET_DATA_DB2 23:16 +#define NVCC7E_SET_EXT_PACKET_DATA_DB3 31:24 +#define NVCC7E_SET_WIN_INFOFRAME (0x000003A0) +#define NVCC7E_SET_WIN_INFOFRAME_FID 7:0 +#define NVCC7E_SET_WIN_INFOFRAME_EN 16:16 +#define NVCC7E_SET_WIN_INFOFRAME_EN_DISABLE (0x00000000) +#define NVCC7E_SET_WIN_INFOFRAME_EN_ENABLE (0x00000001) +#define NVCC7E_SET_FMT_COEFFICIENT_C00 (0x00000400) +#define NVCC7E_SET_FMT_COEFFICIENT_C00_VALUE 20:0 +#define NVCC7E_SET_FMT_COEFFICIENT_C01 (0x00000404) +#define NVCC7E_SET_FMT_COEFFICIENT_C01_VALUE 20:0 +#define NVCC7E_SET_FMT_COEFFICIENT_C02 (0x00000408) +#define NVCC7E_SET_FMT_COEFFICIENT_C02_VALUE 20:0 +#define NVCC7E_SET_FMT_COEFFICIENT_C03 (0x0000040C) +#define NVCC7E_SET_FMT_COEFFICIENT_C03_VALUE 20:0 +#define NVCC7E_SET_FMT_COEFFICIENT_C10 (0x00000410) +#define NVCC7E_SET_FMT_COEFFICIENT_C10_VALUE 20:0 +#define NVCC7E_SET_FMT_COEFFICIENT_C11 (0x00000414) +#define NVCC7E_SET_FMT_COEFFICIENT_C11_VALUE 20:0 +#define NVCC7E_SET_FMT_COEFFICIENT_C12 (0x00000418) +#define NVCC7E_SET_FMT_COEFFICIENT_C12_VALUE 20:0 +#define NVCC7E_SET_FMT_COEFFICIENT_C13 (0x0000041C) +#define NVCC7E_SET_FMT_COEFFICIENT_C13_VALUE 20:0 +#define NVCC7E_SET_FMT_COEFFICIENT_C20 (0x00000420) +#define NVCC7E_SET_FMT_COEFFICIENT_C20_VALUE 20:0 +#define NVCC7E_SET_FMT_COEFFICIENT_C21 (0x00000424) +#define NVCC7E_SET_FMT_COEFFICIENT_C21_VALUE 20:0 +#define NVCC7E_SET_FMT_COEFFICIENT_C22 (0x00000428) +#define NVCC7E_SET_FMT_COEFFICIENT_C22_VALUE 20:0 +#define NVCC7E_SET_FMT_COEFFICIENT_C23 (0x0000042C) +#define NVCC7E_SET_FMT_COEFFICIENT_C23_VALUE 20:0 +#define NVCC7E_SET_ILUT_CONTROL (0x00000440) +#define NVCC7E_SET_ILUT_CONTROL_INTERPOLATE 0:0 +#define NVCC7E_SET_ILUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVCC7E_SET_ILUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVCC7E_SET_ILUT_CONTROL_MIRROR 1:1 +#define NVCC7E_SET_ILUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVCC7E_SET_ILUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVCC7E_SET_ILUT_CONTROL_MODE 3:2 +#define NVCC7E_SET_ILUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVCC7E_SET_ILUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVCC7E_SET_ILUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVCC7E_SET_ILUT_CONTROL_SIZE 18:8 +#define NVCC7E_SET_CSC00CONTROL (0x0000045C) +#define NVCC7E_SET_CSC00CONTROL_ENABLE 0:0 +#define NVCC7E_SET_CSC00CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCC7E_SET_CSC00CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCC7E_SET_CSC00COEFFICIENT_C00 (0x00000460) +#define NVCC7E_SET_CSC00COEFFICIENT_C00_VALUE 20:0 +#define NVCC7E_SET_CSC00COEFFICIENT_C01 (0x00000464) +#define NVCC7E_SET_CSC00COEFFICIENT_C01_VALUE 20:0 +#define NVCC7E_SET_CSC00COEFFICIENT_C02 (0x00000468) +#define NVCC7E_SET_CSC00COEFFICIENT_C02_VALUE 20:0 +#define NVCC7E_SET_CSC00COEFFICIENT_C03 (0x0000046C) +#define NVCC7E_SET_CSC00COEFFICIENT_C03_VALUE 20:0 +#define NVCC7E_SET_CSC00COEFFICIENT_C10 (0x00000470) +#define NVCC7E_SET_CSC00COEFFICIENT_C10_VALUE 20:0 +#define NVCC7E_SET_CSC00COEFFICIENT_C11 (0x00000474) +#define NVCC7E_SET_CSC00COEFFICIENT_C11_VALUE 20:0 +#define NVCC7E_SET_CSC00COEFFICIENT_C12 (0x00000478) +#define NVCC7E_SET_CSC00COEFFICIENT_C12_VALUE 20:0 +#define NVCC7E_SET_CSC00COEFFICIENT_C13 (0x0000047C) +#define NVCC7E_SET_CSC00COEFFICIENT_C13_VALUE 20:0 +#define NVCC7E_SET_CSC00COEFFICIENT_C20 (0x00000480) +#define NVCC7E_SET_CSC00COEFFICIENT_C20_VALUE 20:0 +#define NVCC7E_SET_CSC00COEFFICIENT_C21 (0x00000484) +#define NVCC7E_SET_CSC00COEFFICIENT_C21_VALUE 20:0 +#define NVCC7E_SET_CSC00COEFFICIENT_C22 (0x00000488) +#define NVCC7E_SET_CSC00COEFFICIENT_C22_VALUE 20:0 +#define NVCC7E_SET_CSC00COEFFICIENT_C23 (0x0000048C) +#define NVCC7E_SET_CSC00COEFFICIENT_C23_VALUE 20:0 +#define NVCC7E_SET_CSC0LUT_FP_NORM_SCALE (0x00000490) +#define NVCC7E_SET_CSC0LUT_FP_NORM_SCALE_VALUE 31:0 +#define NVCC7E_SET_CSC0LUT_CONTROL (0x000004A0) +#define NVCC7E_SET_CSC0LUT_CONTROL_INTERPOLATE 0:0 +#define NVCC7E_SET_CSC0LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVCC7E_SET_CSC0LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVCC7E_SET_CSC0LUT_CONTROL_MIRROR 1:1 +#define NVCC7E_SET_CSC0LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVCC7E_SET_CSC0LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVCC7E_SET_CSC0LUT_CONTROL_ENABLE 4:4 +#define NVCC7E_SET_CSC0LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCC7E_SET_CSC0LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCC7E_SET_CSC0LUT_CONTROL_CURVE 6:5 +#define NVCC7E_SET_CSC0LUT_CONTROL_CURVE_CSCLUT_PQ (0x00000000) +#define NVCC7E_SET_CSC0LUT_CONTROL_CURVE_CSCLUT_HLG (0x00000001) +#define NVCC7E_SET_CSC0LUT_CONTROL_CURVE_CSCLUT_DIRECT (0x00000002) +#define NVCC7E_SET_CSC01CONTROL (0x000004BC) +#define NVCC7E_SET_CSC01CONTROL_ENABLE 0:0 +#define NVCC7E_SET_CSC01CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCC7E_SET_CSC01CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCC7E_SET_CSC01COEFFICIENT_C00 (0x000004C0) +#define NVCC7E_SET_CSC01COEFFICIENT_C00_VALUE 20:0 +#define NVCC7E_SET_CSC01COEFFICIENT_C01 (0x000004C4) +#define NVCC7E_SET_CSC01COEFFICIENT_C01_VALUE 20:0 +#define NVCC7E_SET_CSC01COEFFICIENT_C02 (0x000004C8) +#define NVCC7E_SET_CSC01COEFFICIENT_C02_VALUE 20:0 +#define NVCC7E_SET_CSC01COEFFICIENT_C03 (0x000004CC) +#define NVCC7E_SET_CSC01COEFFICIENT_C03_VALUE 20:0 +#define NVCC7E_SET_CSC01COEFFICIENT_C10 (0x000004D0) +#define NVCC7E_SET_CSC01COEFFICIENT_C10_VALUE 20:0 +#define NVCC7E_SET_CSC01COEFFICIENT_C11 (0x000004D4) +#define NVCC7E_SET_CSC01COEFFICIENT_C11_VALUE 20:0 +#define NVCC7E_SET_CSC01COEFFICIENT_C12 (0x000004D8) +#define NVCC7E_SET_CSC01COEFFICIENT_C12_VALUE 20:0 +#define NVCC7E_SET_CSC01COEFFICIENT_C13 (0x000004DC) +#define NVCC7E_SET_CSC01COEFFICIENT_C13_VALUE 20:0 +#define NVCC7E_SET_CSC01COEFFICIENT_C20 (0x000004E0) +#define NVCC7E_SET_CSC01COEFFICIENT_C20_VALUE 20:0 +#define NVCC7E_SET_CSC01COEFFICIENT_C21 (0x000004E4) +#define NVCC7E_SET_CSC01COEFFICIENT_C21_VALUE 20:0 +#define NVCC7E_SET_CSC01COEFFICIENT_C22 (0x000004E8) +#define NVCC7E_SET_CSC01COEFFICIENT_C22_VALUE 20:0 +#define NVCC7E_SET_CSC01COEFFICIENT_C23 (0x000004EC) +#define NVCC7E_SET_CSC01COEFFICIENT_C23_VALUE 20:0 +#define NVCC7E_SET_TMO_CONTROL (0x00000500) +#define NVCC7E_SET_TMO_CONTROL_INTERPOLATE 0:0 +#define NVCC7E_SET_TMO_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVCC7E_SET_TMO_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVCC7E_SET_TMO_CONTROL_SAT_MODE 3:2 +#define NVCC7E_SET_TMO_CONTROL_SIZE 18:8 +#define NVCC7E_SET_TMO_LOW_INTENSITY_ZONE (0x00000508) +#define NVCC7E_SET_TMO_LOW_INTENSITY_ZONE_END 29:16 +#define NVCC7E_SET_TMO_LOW_INTENSITY_VALUE (0x0000050C) +#define NVCC7E_SET_TMO_LOW_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVCC7E_SET_TMO_LOW_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVCC7E_SET_TMO_LOW_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVCC7E_SET_TMO_MEDIUM_INTENSITY_ZONE (0x00000510) +#define NVCC7E_SET_TMO_MEDIUM_INTENSITY_ZONE_START 13:0 +#define NVCC7E_SET_TMO_MEDIUM_INTENSITY_ZONE_END 29:16 +#define NVCC7E_SET_TMO_MEDIUM_INTENSITY_VALUE (0x00000514) +#define NVCC7E_SET_TMO_MEDIUM_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVCC7E_SET_TMO_MEDIUM_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVCC7E_SET_TMO_MEDIUM_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVCC7E_SET_TMO_HIGH_INTENSITY_ZONE (0x00000518) +#define NVCC7E_SET_TMO_HIGH_INTENSITY_ZONE_START 13:0 +#define NVCC7E_SET_TMO_HIGH_INTENSITY_VALUE (0x0000051C) +#define NVCC7E_SET_TMO_HIGH_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVCC7E_SET_TMO_HIGH_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVCC7E_SET_TMO_HIGH_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVCC7E_SET_CSC10CONTROL (0x0000053C) +#define NVCC7E_SET_CSC10CONTROL_ENABLE 0:0 +#define NVCC7E_SET_CSC10CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCC7E_SET_CSC10CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCC7E_SET_CSC10COEFFICIENT_C00 (0x00000540) +#define NVCC7E_SET_CSC10COEFFICIENT_C00_VALUE 20:0 +#define NVCC7E_SET_CSC10COEFFICIENT_C01 (0x00000544) +#define NVCC7E_SET_CSC10COEFFICIENT_C01_VALUE 20:0 +#define NVCC7E_SET_CSC10COEFFICIENT_C02 (0x00000548) +#define NVCC7E_SET_CSC10COEFFICIENT_C02_VALUE 20:0 +#define NVCC7E_SET_CSC10COEFFICIENT_C03 (0x0000054C) +#define NVCC7E_SET_CSC10COEFFICIENT_C03_VALUE 20:0 +#define NVCC7E_SET_CSC10COEFFICIENT_C10 (0x00000550) +#define NVCC7E_SET_CSC10COEFFICIENT_C10_VALUE 20:0 +#define NVCC7E_SET_CSC10COEFFICIENT_C11 (0x00000554) +#define NVCC7E_SET_CSC10COEFFICIENT_C11_VALUE 20:0 +#define NVCC7E_SET_CSC10COEFFICIENT_C12 (0x00000558) +#define NVCC7E_SET_CSC10COEFFICIENT_C12_VALUE 20:0 +#define NVCC7E_SET_CSC10COEFFICIENT_C13 (0x0000055C) +#define NVCC7E_SET_CSC10COEFFICIENT_C13_VALUE 20:0 +#define NVCC7E_SET_CSC10COEFFICIENT_C20 (0x00000560) +#define NVCC7E_SET_CSC10COEFFICIENT_C20_VALUE 20:0 +#define NVCC7E_SET_CSC10COEFFICIENT_C21 (0x00000564) +#define NVCC7E_SET_CSC10COEFFICIENT_C21_VALUE 20:0 +#define NVCC7E_SET_CSC10COEFFICIENT_C22 (0x00000568) +#define NVCC7E_SET_CSC10COEFFICIENT_C22_VALUE 20:0 +#define NVCC7E_SET_CSC10COEFFICIENT_C23 (0x0000056C) +#define NVCC7E_SET_CSC10COEFFICIENT_C23_VALUE 20:0 +#define NVCC7E_SET_CSC1LUT_FP_SCALE (0x00000570) +#define NVCC7E_SET_CSC1LUT_FP_SCALE_VALUE 15:0 +#define NVCC7E_SET_CSC1LUT_CONTROL (0x00000580) +#define NVCC7E_SET_CSC1LUT_CONTROL_INTERPOLATE 0:0 +#define NVCC7E_SET_CSC1LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVCC7E_SET_CSC1LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVCC7E_SET_CSC1LUT_CONTROL_MIRROR 1:1 +#define NVCC7E_SET_CSC1LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVCC7E_SET_CSC1LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVCC7E_SET_CSC1LUT_CONTROL_ENABLE 4:4 +#define NVCC7E_SET_CSC1LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCC7E_SET_CSC1LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCC7E_SET_CSC1LUT_CONTROL_CURVE 6:5 +#define NVCC7E_SET_CSC1LUT_CONTROL_CURVE_CSCLUT_PQ (0x00000000) +#define NVCC7E_SET_CSC1LUT_CONTROL_CURVE_CSCLUT_HLG (0x00000001) +#define NVCC7E_SET_CSC1LUT_CONTROL_CURVE_CSCLUT_DIRECT (0x00000002) +#define NVCC7E_SET_CSC11CONTROL (0x0000059C) +#define NVCC7E_SET_CSC11CONTROL_ENABLE 0:0 +#define NVCC7E_SET_CSC11CONTROL_ENABLE_DISABLE (0x00000000) +#define NVCC7E_SET_CSC11CONTROL_ENABLE_ENABLE (0x00000001) +#define NVCC7E_SET_CSC11CONTROL_LEVEL 7:2 +#define NVCC7E_SET_CSC11COEFFICIENT_C00 (0x000005A0) +#define NVCC7E_SET_CSC11COEFFICIENT_C00_VALUE 20:0 +#define NVCC7E_SET_CSC11COEFFICIENT_C01 (0x000005A4) +#define NVCC7E_SET_CSC11COEFFICIENT_C01_VALUE 20:0 +#define NVCC7E_SET_CSC11COEFFICIENT_C02 (0x000005A8) +#define NVCC7E_SET_CSC11COEFFICIENT_C02_VALUE 20:0 +#define NVCC7E_SET_CSC11COEFFICIENT_C03 (0x000005AC) +#define NVCC7E_SET_CSC11COEFFICIENT_C03_VALUE 20:0 +#define NVCC7E_SET_CSC11COEFFICIENT_C10 (0x000005B0) +#define NVCC7E_SET_CSC11COEFFICIENT_C10_VALUE 20:0 +#define NVCC7E_SET_CSC11COEFFICIENT_C11 (0x000005B4) +#define NVCC7E_SET_CSC11COEFFICIENT_C11_VALUE 20:0 +#define NVCC7E_SET_CSC11COEFFICIENT_C12 (0x000005B8) +#define NVCC7E_SET_CSC11COEFFICIENT_C12_VALUE 20:0 +#define NVCC7E_SET_CSC11COEFFICIENT_C13 (0x000005BC) +#define NVCC7E_SET_CSC11COEFFICIENT_C13_VALUE 20:0 +#define NVCC7E_SET_CSC11COEFFICIENT_C20 (0x000005C0) +#define NVCC7E_SET_CSC11COEFFICIENT_C20_VALUE 20:0 +#define NVCC7E_SET_CSC11COEFFICIENT_C21 (0x000005C4) +#define NVCC7E_SET_CSC11COEFFICIENT_C21_VALUE 20:0 +#define NVCC7E_SET_CSC11COEFFICIENT_C22 (0x000005C8) +#define NVCC7E_SET_CSC11COEFFICIENT_C22_VALUE 20:0 +#define NVCC7E_SET_CSC11COEFFICIENT_C23 (0x000005CC) +#define NVCC7E_SET_CSC11COEFFICIENT_C23_VALUE 20:0 +#define NVCC7E_SET_CLAMP_RANGE (0x000005D0) +#define NVCC7E_SET_CLAMP_RANGE_LOW 15:0 +#define NVCC7E_SET_CLAMP_RANGE_HIGH 31:16 +#define NVCC7E_SW_RESERVED(b) (0x000005D4 + (b)*0x00000004) +#define NVCC7E_SW_RESERVED_VALUE 31:0 +#define NVCC7E_SET_DIRTY_RECT_SIZE (0x000005E4) +#define NVCC7E_SET_DIRTY_RECT_SIZE_WIDTH 15:0 +#define NVCC7E_SET_DIRTY_RECT_SIZE_HEIGHT 31:16 +#define NVCC7E_SET_DIRTY_RECT_POSITION (0x000005E8) +#define NVCC7E_SET_DIRTY_RECT_POSITION_X 15:0 +#define NVCC7E_SET_DIRTY_RECT_POSITION_Y 31:16 +#define NVCC7E_SET_SUPERFRAME (0x000005EC) +#define NVCC7E_SET_SUPERFRAME_ENABLE 0:0 +#define NVCC7E_SET_SUPERFRAME_ENABLE_DISABLE (0x00000000) +#define NVCC7E_SET_SUPERFRAME_ENABLE_ENABLE (0x00000001) +#define NVCC7E_SET_SUPERFRAME_MODE 2:1 +#define NVCC7E_SET_SUPERFRAME_MODE_FIXED (0x00000000) +#define NVCC7E_SET_SUPERFRAME_MODE_DYNAMIC (0x00000001) +#define NVCC7E_SET_SUPERFRAME_MODE_SW (0x00000003) +#define NVCC7E_SET_SUPERFRAME_RATIO_IN 15:8 +#define NVCC7E_SET_SUPERFRAME_RATIO_OUT 23:16 +#define NVCC7E_SET_SUPERFRAME_START_COUNT 31:24 +#define NVCC7E_SET_INFOFRAME_CTRL(b) (0x000005F0 + (b)*0x00000004) +#define NVCC7E_SET_INFOFRAME_CTRL_ENABLE 0:0 +#define NVCC7E_SET_INFOFRAME_CTRL_ENABLE_DISABLE (0x00000000) +#define NVCC7E_SET_INFOFRAME_CTRL_ENABLE_ENABLE (0x00000001) +#define NVCC7E_SET_INFOFRAME_CTRL_LOCATION 5:4 +#define NVCC7E_SET_INFOFRAME_CTRL_LOCATION_VBLANK (0x00000000) +#define NVCC7E_SET_INFOFRAME_CTRL_LOCATION_VSYNC (0x00000001) +#define NVCC7E_SET_INFOFRAME_CTRL_LOCATION_LINE (0x00000002) +#define NVCC7E_SET_INFOFRAME_CTRL_LINE_ID 30:16 +#define NVCC7E_SET_INFOFRAME_CTRL_LINE_ID_REVERSED 31:31 +#define NVCC7E_SET_INFOFRAME_CTRL_LINE_ID_REVERSED_DISABLE (0x00000000) +#define NVCC7E_SET_INFOFRAME_CTRL_LINE_ID_REVERSED_ENABLE (0x00000001) +#define NVCC7E_SET_INFOFRAME_HEADER(b) (0x000005F8 + (b)*0x00000004) +#define NVCC7E_SET_INFOFRAME_HEADER_HB0 7:0 +#define NVCC7E_SET_INFOFRAME_HEADER_HB1 15:8 +#define NVCC7E_SET_INFOFRAME_HEADER_HB2 23:16 +#define NVCC7E_SET_INFOFRAME_HEADER_HB3 31:24 +#define NVCC7E_SET_INFOFRAME_DATA0(b) (0x00000600 + (b)*0x00000004) +#define NVCC7E_SET_INFOFRAME_DATA0_DB0 7:0 +#define NVCC7E_SET_INFOFRAME_DATA0_DB1 15:8 +#define NVCC7E_SET_INFOFRAME_DATA0_DB2 23:16 +#define NVCC7E_SET_INFOFRAME_DATA0_DB3 31:24 +#define NVCC7E_SET_INFOFRAME_DATA1(b) (0x00000608 + (b)*0x00000004) +#define NVCC7E_SET_INFOFRAME_DATA1_DB4 7:0 +#define NVCC7E_SET_INFOFRAME_DATA1_DB5 15:8 +#define NVCC7E_SET_INFOFRAME_DATA1_DB6 23:16 +#define NVCC7E_SET_INFOFRAME_DATA1_DB7 31:24 +#define NVCC7E_SET_INFOFRAME_DATA2(b) (0x00000610 + (b)*0x00000004) +#define NVCC7E_SET_INFOFRAME_DATA2_DB8 7:0 +#define NVCC7E_SET_INFOFRAME_DATA2_DB9 15:8 +#define NVCC7E_SET_INFOFRAME_DATA2_DB10 23:16 +#define NVCC7E_SET_INFOFRAME_DATA2_DB11 31:24 +#define NVCC7E_SET_INFOFRAME_DATA3(b) (0x00000618 + (b)*0x00000004) +#define NVCC7E_SET_INFOFRAME_DATA3_DB12 7:0 +#define NVCC7E_SET_INFOFRAME_DATA3_DB13 15:8 +#define NVCC7E_SET_INFOFRAME_DATA3_DB14 23:16 +#define NVCC7E_SET_INFOFRAME_DATA3_DB15 31:24 +#define NVCC7E_SET_INFOFRAME_DATA4(b) (0x00000620 + (b)*0x00000004) +#define NVCC7E_SET_INFOFRAME_DATA4_DB16 7:0 +#define NVCC7E_SET_INFOFRAME_DATA4_DB17 15:8 +#define NVCC7E_SET_INFOFRAME_DATA4_DB18 23:16 +#define NVCC7E_SET_INFOFRAME_DATA4_DB19 31:24 +#define NVCC7E_SET_INFOFRAME_DATA5(b) (0x00000628 + (b)*0x00000004) +#define NVCC7E_SET_INFOFRAME_DATA5_DB20 7:0 +#define NVCC7E_SET_INFOFRAME_DATA5_DB21 15:8 +#define NVCC7E_SET_INFOFRAME_DATA5_DB22 23:16 +#define NVCC7E_SET_INFOFRAME_DATA5_DB23 31:24 +#define NVCC7E_SET_INFOFRAME_DATA6(b) (0x00000630 + (b)*0x00000004) +#define NVCC7E_SET_INFOFRAME_DATA6_DB24 7:0 +#define NVCC7E_SET_INFOFRAME_DATA6_DB25 15:8 +#define NVCC7E_SET_INFOFRAME_DATA6_DB26 23:16 +#define NVCC7E_SET_INFOFRAME_DATA6_DB27 31:24 +#define NVCC7E_SET_INFOFRAME_DATA7(b) (0x00000638 + (b)*0x00000004) +#define NVCC7E_SET_INFOFRAME_DATA7_DB28 7:0 +#define NVCC7E_SET_INFOFRAME_DATA7_DB29 15:8 +#define NVCC7E_SET_INFOFRAME_DATA7_DB30 23:16 +#define NVCC7E_SET_INFOFRAME_DATA7_DB31 31:24 +#define NVCC7E_SET_SURFACE_ADDRESS_HI_SEMAPHORE (0x00000640) +#define NVCC7E_SET_SURFACE_ADDRESS_HI_SEMAPHORE_ADDRESS_HI 31:0 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE (0x00000644) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ADDRESS_LO 31:4 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET 3:2 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_IOVA (0x00000000) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE 0:0 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE_DISABLE (0x00000000) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE_ENABLE (0x00000001) +#define NVCC7E_SET_SURFACE_ADDRESS_HI_ACQ_SEMAPHORE (0x00000648) +#define NVCC7E_SET_SURFACE_ADDRESS_HI_ACQ_SEMAPHORE_ADDRESS_HI 31:0 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE (0x0000064C) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ADDRESS_LO 31:4 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET 3:2 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_IOVA (0x00000000) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE 0:0 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE_DISABLE (0x00000000) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE_ENABLE (0x00000001) +#define NVCC7E_SET_SURFACE_ADDRESS_HI_NOTIFIER (0x00000650) +#define NVCC7E_SET_SURFACE_ADDRESS_HI_NOTIFIER_ADDRESS_HI 31:0 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_NOTIFIER (0x00000654) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ADDRESS_LO 31:4 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET 3:2 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_IOVA (0x00000000) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE 0:0 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_DISABLE (0x00000000) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_ENABLE (0x00000001) +#define NVCC7E_SET_SURFACE_ADDRESS_HI_ISO(b) (0x00000658 + (b)*0x00000004) +#define NVCC7E_SET_SURFACE_ADDRESS_HI_ISO_ADDRESS_HI 31:0 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO(b) (0x00000670 + (b)*0x00000004) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO_ADDRESS_LO 31:4 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET 3:2 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_IOVA (0x00000000) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO_KIND 1:1 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO_KIND_PITCH (0x00000000) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO_KIND_BLOCKLINEAR (0x00000001) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE 0:0 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE_DISABLE (0x00000000) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE_ENABLE (0x00000001) +#define NVCC7E_SET_SURFACE_ADDRESS_HI_ILUT (0x00000688) +#define NVCC7E_SET_SURFACE_ADDRESS_HI_ILUT_ADDRESS_HI 31:0 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ILUT (0x0000068C) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ILUT_ADDRESS_LO 31:4 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET 3:2 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_IOVA (0x00000000) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE 0:0 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE_DISABLE (0x00000000) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE_ENABLE (0x00000001) +#define NVCC7E_SET_SURFACE_ADDRESS_HI_TMO_LUT (0x00000690) +#define NVCC7E_SET_SURFACE_ADDRESS_HI_TMO_LUT_ADDRESS_HI 31:0 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_TMO_LUT (0x00000694) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ADDRESS_LO 31:4 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET 3:2 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_IOVA (0x00000000) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_NVM (0x00000001) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_PCI (0x00000002) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE 0:0 +#define NVCC7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE_DISABLE (0x00000000) +#define NVCC7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE_ENABLE (0x00000001) +#define NVCC7E_SET_TELLTALE_CRC_REGION(b) (0x00000698 + (b)*0x00000004) +#define NVCC7E_SET_TELLTALE_CRC_REGION_INDEX0 7:0 +#define NVCC7E_SET_TELLTALE_CRC_REGION_INDEX1 15:8 +#define NVCC7E_SET_TELLTALE_CRC_REGION_INDEX2 23:16 +#define NVCC7E_SET_TELLTALE_CRC_REGION_INDEX3 31:24 +#define NVCC7E_SET_TELLTALE_GOLDEN_CRC_LOWER(b) (0x000006A8 + (b)*0x00000004) +#define NVCC7E_SET_TELLTALE_GOLDEN_CRC_LOWER_CRC 31:0 +#define NVCC7E_SET_TELLTALE_GOLDEN_CRC_UPPER(b) (0x000006E8 + (b)*0x00000004) +#define NVCC7E_SET_TELLTALE_GOLDEN_CRC_UPPER_CRC 31:0 +#define NVCC7E_SET_TELLTALE_CRC_CONTROL (0x00000728) +#define NVCC7E_SET_TELLTALE_CRC_CONTROL_REGION_ENABLE 15:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clcc7e_h diff --git a/userspace/sdks/nv570/inc/class/clcd40.h b/userspace/sdks/nv570/inc/class/clcd40.h new file mode 100644 index 0000000..c301740 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcd40.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gb100_clcd40_h__ +#define __gb100_clcd40_h__ + +#define BLACKWELL_INLINE_TO_MEMORY_A 0xCD40 + +#endif // __gb100_clcd40_h__ diff --git a/userspace/sdks/nv570/inc/class/clcd97.h b/userspace/sdks/nv570/inc/class/clcd97.h new file mode 100644 index 0000000..89bf0d8 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcd97.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gb100_clcd97_h__ +#define __gb100_clcd97_h__ + +#define BLACKWELL_A 0xCD97 + +#endif // __gb100_clcd97_h__ diff --git a/userspace/sdks/nv570/inc/class/clcdb0.h b/userspace/sdks/nv570/inc/class/clcdb0.h new file mode 100644 index 0000000..8150cf6 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcdb0.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gb100_clcdb0_h__ +#define __gb100_clcdb0_h__ + +#define NVCDB0_VIDEO_DECODER (0x0000CDB0) + +#endif // __gb100_clcdb0_h__ diff --git a/userspace/sdks/nv570/inc/class/clcdc0.h b/userspace/sdks/nv570/inc/class/clcdc0.h new file mode 100644 index 0000000..dca1a2d --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcdc0.h @@ -0,0 +1,777 @@ +/******************************************************************************* + Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef HWFE_BLACKWELL_COMPUTE_A_SW_H +#define HWFE_BLACKWELL_COMPUTE_A_SW_H + +#include "nvtypes.h" + +#define BLACKWELL_COMPUTE_A 0xCDC0 + +#define NVCDC0_SET_OBJECT 0x0000 +#define NVCDC0_SET_OBJECT_CLASS_ID 15:0 +#define NVCDC0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVCDC0_NO_OPERATION 0x0100 +#define NVCDC0_NO_OPERATION_V 31:0 + +#define NVCDC0_SET_NOTIFY_A 0x0104 +#define NVCDC0_SET_NOTIFY_A_ADDRESS_UPPER 24:0 + +#define NVCDC0_SET_NOTIFY_B 0x0108 +#define NVCDC0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVCDC0_NOTIFY 0x010c +#define NVCDC0_NOTIFY_TYPE 31:0 +#define NVCDC0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVCDC0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVCDC0_WAIT_FOR_IDLE 0x0110 +#define NVCDC0_WAIT_FOR_IDLE_V 31:0 + +#define NVCDC0_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVCDC0_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVCDC0_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVCDC0_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVCDC0_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVCDC0_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVCDC0_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVCDC0_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVCDC0_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVCDC0_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVCDC0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVCDC0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVCDC0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVCDC0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVCDC0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVCDC0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVCDC0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVCDC0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVCDC0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVCDC0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVCDC0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVCDC0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVCDC0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVCDC0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVCDC0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVCDC0_SEND_GO_IDLE 0x013c +#define NVCDC0_SEND_GO_IDLE_V 31:0 + +#define NVCDC0_PM_TRIGGER 0x0140 +#define NVCDC0_PM_TRIGGER_V 31:0 + +#define NVCDC0_PM_TRIGGER_WFI 0x0144 +#define NVCDC0_PM_TRIGGER_WFI_V 31:0 + +#define NVCDC0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVCDC0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVCDC0_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVCDC0_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVCDC0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVCDC0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVCDC0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVCDC0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVCDC0_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER 0x0158 +#define NVCDC0_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER_PAYLOAD_LOWER 31:0 + +#define NVCDC0_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER 0x015c +#define NVCDC0_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD_UPPER 31:0 + +#define NVCDC0_SET_REPORT_SEMAPHORE_ADDRESS_LOWER 0x0160 +#define NVCDC0_SET_REPORT_SEMAPHORE_ADDRESS_LOWER_LOWER 31:0 + +#define NVCDC0_SET_REPORT_SEMAPHORE_ADDRESS_UPPER 0x0164 +#define NVCDC0_SET_REPORT_SEMAPHORE_ADDRESS_UPPER_UPPER 24:0 + +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE 0x0168 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_OPERATION 1:0 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_OPERATION_RELEASE 0x00000000 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_OPERATION_ACQUIRE 0x00000001 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_OPERATION_REPORT_ONLY 0x00000002 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_OPERATION_TRAP 0x00000003 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE 2:2 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE 4:3 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE 5:5 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_FALSE 0x00000000 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_TRUE 0x00000001 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE 6:6 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP 9:7 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_ADD 0x00000000 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MIN 0x00000001 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MAX 0x00000002 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_INC 0x00000003 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_DEC 0x00000004 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_AND 0x00000005 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_OR 0x00000006 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_XOR 0x00000007 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT 11:10 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64 12:12 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_FALSE 0x00000000 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_TRUE 0x00000001 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE 14:13 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_NONE 0x00000000 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 +#define NVCDC0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 + +#define NVCDC0_LINE_LENGTH_IN 0x0180 +#define NVCDC0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVCDC0_LINE_COUNT 0x0184 +#define NVCDC0_LINE_COUNT_VALUE 31:0 + +#define NVCDC0_OFFSET_OUT_UPPER 0x0188 +#define NVCDC0_OFFSET_OUT_UPPER_VALUE 24:0 + +#define NVCDC0_OFFSET_OUT 0x018c +#define NVCDC0_OFFSET_OUT_VALUE 31:0 + +#define NVCDC0_PITCH_OUT 0x0190 +#define NVCDC0_PITCH_OUT_VALUE 31:0 + +#define NVCDC0_LAUNCH_DMA 0x01b0 +#define NVCDC0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVCDC0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVCDC0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVCDC0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVCDC0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVCDC0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVCDC0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVCDC0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVCDC0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVCDC0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVCDC0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVCDC0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVCDC0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVCDC0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVCDC0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVCDC0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVCDC0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVCDC0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVCDC0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVCDC0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVCDC0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVCDC0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVCDC0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVCDC0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVCDC0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVCDC0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVCDC0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVCDC0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVCDC0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVCDC0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVCDC0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVCDC0_LOAD_INLINE_DATA 0x01b4 +#define NVCDC0_LOAD_INLINE_DATA_V 31:0 + +#define NVCDC0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVCDC0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 24:0 + +#define NVCDC0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVCDC0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVCDC0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVCDC0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVCDC0_SET_SM_SCG_CONTROL 0x01e8 +#define NVCDC0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS 0:0 +#define NVCDC0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE 0x00000000 +#define NVCDC0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE 0x00000001 + +#define NVCDC0_SET_MME_SWITCH_STATE 0x01ec +#define NVCDC0_SET_MME_SWITCH_STATE_VALID 0:0 +#define NVCDC0_SET_MME_SWITCH_STATE_VALID_FALSE 0x00000000 +#define NVCDC0_SET_MME_SWITCH_STATE_VALID_TRUE 0x00000001 +#define NVCDC0_SET_MME_SWITCH_STATE_SAVE_MACRO 11:4 +#define NVCDC0_SET_MME_SWITCH_STATE_RESTORE_MACRO 19:12 + +#define NVCDC0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVCDC0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVCDC0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVCDC0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVCDC0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVCDC0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVCDC0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVCDC0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVCDC0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVCDC0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVCDC0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVCDC0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVCDC0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVCDC0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVCDC0_PERFMON_TRANSFER 0x0210 +#define NVCDC0_PERFMON_TRANSFER_V 31:0 + +#define NVCDC0_INVALIDATE_SHADER_CACHES 0x021c +#define NVCDC0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVCDC0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVCDC0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVCDC0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVCDC0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVCDC0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVCDC0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVCDC0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVCDC0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVCDC0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVCDC0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVCDC0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVCDC0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVCDC0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVCDC0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVCDC0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVCDC0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVCDC0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVCDC0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVCDC0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVCDC0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVCDC0_SET_RESERVED_SW_METHOD03 0x022c +#define NVCDC0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVCDC0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVCDC0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVCDC0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVCDC0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVCDC0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVCDC0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVCDC0_SET_RESERVED_SW_METHOD07 0x023c +#define NVCDC0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVCDC0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVCDC0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVCDC0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVCDC0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVCDC0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVCDC0_SET_CWD_REF_COUNTER 0x0248 +#define NVCDC0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVCDC0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVCDC0_SET_RESERVED_SW_METHOD08 0x024c +#define NVCDC0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVCDC0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVCDC0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVCDC0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVCDC0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVCDC0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVCDC0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVCDC0_SET_RESERVED_SW_METHOD12 0x025c +#define NVCDC0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVCDC0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVCDC0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVCDC0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVCDC0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVCDC0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVCDC0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVCDC0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVCDC0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVCDC0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCDC0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVCDC0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVCDC0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCDC0_SET_QMD_VERSION 0x0288 +#define NVCDC0_SET_QMD_VERSION_CURRENT 15:0 +#define NVCDC0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCDC0_INVALIDATE_SKED_CACHES 0x0298 +#define NVCDC0_INVALIDATE_SKED_CACHES_FORCE_IGNORE_VEID 0:0 +#define NVCDC0_INVALIDATE_SKED_CACHES_FORCE_IGNORE_VEID_FALSE 0x00000000 +#define NVCDC0_INVALIDATE_SKED_CACHES_FORCE_IGNORE_VEID_TRUE 0x00000001 + +#define NVCDC0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVCDC0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVCDC0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVCDC0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVCDC0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVCDC0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVCDC0_SEND_PCAS_A 0x02b4 +#define NVCDC0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVCDC0_SEND_PCAS_B 0x02b8 +#define NVCDC0_SEND_PCAS_B_FROM 23:0 +#define NVCDC0_SEND_PCAS_B_DELTA 31:24 + +#define NVCDC0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVCDC0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVCDC0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVCDC0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVCDC0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVCDC0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVCDC0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVCDC0_SEND_SIGNALING_PCAS2_B 0x02c0 +#define NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION 3:0 +#define NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_NOP 0x00000000 +#define NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE 0x00000001 +#define NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_SCHEDULE 0x00000002 +#define NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_COPY_SCHEDULE 0x00000003 +#define NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_PUT 0x00000006 +#define NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_DECREMENT_DEPENDENCE 0x00000007 +#define NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH 0x00000008 +#define NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH_SCHEDULE 0x00000009 +#define NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_SCHEDULE 0x0000000A +#define NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_FORCE_REQUIRE_SCHEDULING 0x0000000B +#define NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_DEPENDENCE 0x0000000C +#define NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_CWD_REF_COUNTER 0x0000000D +#define NVCDC0_SEND_SIGNALING_PCAS2_B_SELECT 13:8 +#define NVCDC0_SEND_SIGNALING_PCAS2_B_OFFSET_MINUS_ONE 23:14 + +#define NVCDC0_SET_SKED_CACHE_CONTROL 0x02cc +#define NVCDC0_SET_SKED_CACHE_CONTROL_IGNORE_VEID 0:0 +#define NVCDC0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE 0x00000000 +#define NVCDC0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE 0x00000001 + +#define NVCDC0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVCDC0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVCDC0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVCDC0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVCDC0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVCDC0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 +#define NVCDC0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_PLURAL_TPC_GPC_COUNT 23:16 +#define NVCDC0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SINGLETON_TPC_GPC_COUNT 31:24 + +#define NVCDC0_SET_SPA_VERSION 0x0310 +#define NVCDC0_SET_SPA_VERSION_MINOR 7:0 +#define NVCDC0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVCDC0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVCDC0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 8:0 +#define NVCDC0_SET_INLINE_QMD_ADDRESS_A_INLINE_SIZE 30:30 +#define NVCDC0_SET_INLINE_QMD_ADDRESS_A_INLINE_SIZE_INLINE_256 0x00000000 +#define NVCDC0_SET_INLINE_QMD_ADDRESS_A_INLINE_SIZE_INLINE_384 0x00000001 + +#define NVCDC0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVCDC0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVCDC0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVCDC0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVCDC0_SET_FALCON00 0x0500 +#define NVCDC0_SET_FALCON00_V 31:0 + +#define NVCDC0_SET_FALCON01 0x0504 +#define NVCDC0_SET_FALCON01_V 31:0 + +#define NVCDC0_SET_FALCON02 0x0508 +#define NVCDC0_SET_FALCON02_V 31:0 + +#define NVCDC0_SET_FALCON03 0x050c +#define NVCDC0_SET_FALCON03_V 31:0 + +#define NVCDC0_SET_FALCON04 0x0510 +#define NVCDC0_SET_FALCON04_V 31:0 + +#define NVCDC0_SET_FALCON05 0x0514 +#define NVCDC0_SET_FALCON05_V 31:0 + +#define NVCDC0_SET_FALCON06 0x0518 +#define NVCDC0_SET_FALCON06_V 31:0 + +#define NVCDC0_SET_FALCON07 0x051c +#define NVCDC0_SET_FALCON07_V 31:0 + +#define NVCDC0_SET_FALCON08 0x0520 +#define NVCDC0_SET_FALCON08_V 31:0 + +#define NVCDC0_SET_FALCON09 0x0524 +#define NVCDC0_SET_FALCON09_V 31:0 + +#define NVCDC0_SET_FALCON10 0x0528 +#define NVCDC0_SET_FALCON10_V 31:0 + +#define NVCDC0_SET_FALCON11 0x052c +#define NVCDC0_SET_FALCON11_V 31:0 + +#define NVCDC0_SET_FALCON12 0x0530 +#define NVCDC0_SET_FALCON12_V 31:0 + +#define NVCDC0_SET_FALCON13 0x0534 +#define NVCDC0_SET_FALCON13_V 31:0 + +#define NVCDC0_SET_FALCON14 0x0538 +#define NVCDC0_SET_FALCON14_V 31:0 + +#define NVCDC0_SET_FALCON15 0x053c +#define NVCDC0_SET_FALCON15_V 31:0 + +#define NVCDC0_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVCDC0_SET_MME_MEM_ADDRESS_A_UPPER 24:0 + +#define NVCDC0_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVCDC0_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVCDC0_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVCDC0_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVCDC0_MME_DMA_READ 0x055c +#define NVCDC0_MME_DMA_READ_LENGTH 31:0 + +#define NVCDC0_MME_DMA_READ_FIFOED 0x0560 +#define NVCDC0_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVCDC0_MME_DMA_WRITE 0x0564 +#define NVCDC0_MME_DMA_WRITE_LENGTH 31:0 + +#define NVCDC0_MME_DMA_REDUCTION 0x0568 +#define NVCDC0_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVCDC0_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVCDC0_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVCDC0_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVCDC0_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVCDC0_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVCDC0_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVCDC0_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVCDC0_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVCDC0_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVCDC0_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVCDC0_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVCDC0_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVCDC0_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVCDC0_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVCDC0_MME_DMA_SYSMEMBAR 0x056c +#define NVCDC0_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVCDC0_MME_DMA_SYNC 0x0570 +#define NVCDC0_MME_DMA_SYNC_VALUE 31:0 + +#define NVCDC0_EVENT_START_TRIGGER 0x074c +#define NVCDC0_EVENT_START_TRIGGER_V 31:0 + +#define NVCDC0_EVENT_STOP_TRIGGER 0x075c +#define NVCDC0_EVENT_STOP_TRIGGER_V 31:0 + +#define NVCDC0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVCDC0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 24:0 + +#define NVCDC0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVCDC0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVCDC0_SET_TEXTURE_HEADER_VERSION 0x07ac +#define NVCDC0_SET_TEXTURE_HEADER_VERSION_MAJOR 7:0 + +#define NVCDC0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVCDC0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVCDC0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVCDC0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVCDC0_SET_MONITORED_FENCE_SIGNAL_ADDRESS_BASE_A 0x07b8 +#define NVCDC0_SET_MONITORED_FENCE_SIGNAL_ADDRESS_BASE_A_LOWER 31:0 + +#define NVCDC0_SET_MONITORED_FENCE_SIGNAL_ADDRESS_BASE_B 0x07bc +#define NVCDC0_SET_MONITORED_FENCE_SIGNAL_ADDRESS_BASE_B_UPPER 24:0 + +#define NVCDC0_THROTTLE_SM 0x07fc +#define NVCDC0_THROTTLE_SM_MULTIPLY_ADD 0:0 +#define NVCDC0_THROTTLE_SM_MULTIPLY_ADD_FALSE 0x00000000 +#define NVCDC0_THROTTLE_SM_MULTIPLY_ADD_TRUE 0x00000001 + +#define NVCDC0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVCDC0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVCDC0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVCDC0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVCDC0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS(i) (0x0da0+(i)*4) +#define NVCDC0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS_V 31:0 + +#define NVCDC0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVCDC0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVCDC0_MME_DMA_WRITE_METHOD_BARRIER 0x0dec +#define NVCDC0_MME_DMA_WRITE_METHOD_BARRIER_V 0:0 + +#define NVCDC0_EVENT_STOP_TRIGGER_WFI 0x0ffc +#define NVCDC0_EVENT_STOP_TRIGGER_WFI_V 31:0 + +#define NVCDC0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVCDC0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVCDC0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVCDC0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVCDC0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVCDC0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVCDC0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVCDC0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVCDC0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVCDC0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVCDC0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVCDC0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVCDC0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVCDC0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVCDC0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVCDC0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVCDC0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVCDC0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVCDC0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVCDC0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVCDC0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVCDC0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVCDC0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVCDC0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVCDC0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVCDC0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVCDC0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVCDC0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVCDC0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVCDC0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVCDC0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVCDC0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVCDC0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVCDC0_SET_RENDER_ENABLE_A 0x1550 +#define NVCDC0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVCDC0_SET_RENDER_ENABLE_B 0x1554 +#define NVCDC0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVCDC0_SET_RENDER_ENABLE_C 0x1558 +#define NVCDC0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVCDC0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVCDC0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVCDC0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVCDC0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVCDC0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVCDC0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVCDC0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 24:0 + +#define NVCDC0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVCDC0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVCDC0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVCDC0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 31:0 + +#define NVCDC0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVCDC0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 24:0 + +#define NVCDC0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVCDC0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVCDC0_SET_TEX_HEADER_POOL_C 0x157c +#define NVCDC0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 31:0 + +#define NVCDC0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVCDC0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVCDC0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVCDC0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVCDC0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVCDC0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVCDC0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVCDC0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVCDC0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVCDC0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVCDC0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVCDC0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVCDC0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVCDC0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVCDC0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVCDC0_PIPE_NOP 0x1a2c +#define NVCDC0_PIPE_NOP_V 31:0 + +#define NVCDC0_SET_SPARE00 0x1a30 +#define NVCDC0_SET_SPARE00_V 31:0 + +#define NVCDC0_SET_SPARE01 0x1a34 +#define NVCDC0_SET_SPARE01_V 31:0 + +#define NVCDC0_SET_SPARE02 0x1a38 +#define NVCDC0_SET_SPARE02_V 31:0 + +#define NVCDC0_SET_SPARE03 0x1a3c +#define NVCDC0_SET_SPARE03_V 31:0 + +#define NVCDC0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVCDC0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 24:0 + +#define NVCDC0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVCDC0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVCDC0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVCDC0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVCDC0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVCDC0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVCDC0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVCDC0_SET_TRAP_HANDLER_A 0x25f8 +#define NVCDC0_SET_TRAP_HANDLER_A_ADDRESS_UPPER 24:0 + +#define NVCDC0_SET_TRAP_HANDLER_B 0x25fc +#define NVCDC0_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVCDC0_SET_BINDLESS_TEXTURE 0x2608 +#define NVCDC0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVCDC0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVCDC0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVCDC0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVCDC0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVCDC0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVCDC0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVCDC0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVCDC0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVCDC0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVCDC0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVCDC0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVCDC0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVCDC0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVCDC0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVCDC0_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVCDC0_CALL_MME_MACRO_V 31:0 + +#define NVCDC0_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVCDC0_CALL_MME_DATA_V 31:0 + +#endif /* HWFE_BLACKWELL_COMPUTE_A_SW_H */ diff --git a/userspace/sdks/nv570/inc/class/clcdcd.h b/userspace/sdks/nv570/inc/class/clcdcd.h new file mode 100644 index 0000000..63bc42b --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcdcd.h @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clcdcd.finn +// + +#define TRACE_DEVICE_EVENT (0xcdcdU) /* finn: Evaluated from "NVCDCD_ALLOC_PARAMETERS_MESSAGE_ID" */ + +#define NVCDCD_ALLOC_PARAMETERS_MESSAGE_ID (0xcdcdU) + +typedef struct NVCDCD_ALLOC_PARAMETERS { + // + // capDescriptor is a file descriptor for unix RM clients, but a void + // pointer for windows RM clients. + // + // capDescriptor is transparent to RM clients i.e. RM's user-mode shim + // populates this field on behalf of clients. + // + NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8); +} NVCDCD_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv570/inc/class/clcdd1.h b/userspace/sdks/nv570/inc/class/clcdd1.h new file mode 100644 index 0000000..62d99a4 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcdd1.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gb100_clcdd1_h__ +#define __gb100_clcdd1_h__ + +#define NVCDD1_VIDEO_NVJPG (0x0000CDD1) + +#endif // __gb100_clcdd1_h__ diff --git a/userspace/sdks/nv570/inc/class/clcdfa.h b/userspace/sdks/nv570/inc/class/clcdfa.h new file mode 100644 index 0000000..c4bb4e1 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcdfa.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gb100_clcdfa_h__ +#define __gb100_clcdfa_h__ + +#define NVCDFA_VIDEO_OFA (0x0000CDFA) + +#endif // __gb100_clcdfa_h__ diff --git a/userspace/sdks/nv570/inc/class/clce97.h b/userspace/sdks/nv570/inc/class/clce97.h new file mode 100644 index 0000000..bf302f9 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clce97.h @@ -0,0 +1,30 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clce97_h_ +#define _clce97_h_ + +#define BLACKWELL_B 0xCE97 + +#endif /* _clce97_h_ */ + diff --git a/userspace/sdks/nv570/inc/class/clceb0.h b/userspace/sdks/nv570/inc/class/clceb0.h new file mode 100644 index 0000000..715e81a --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clceb0.h @@ -0,0 +1,30 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef clceb0_h_ +#define clceb0_h_ + +#define NVCEB0_VIDEO_DECODER (0x0000CEB0) + +#endif // clceb0_h + diff --git a/userspace/sdks/nv570/inc/class/clceb7.h b/userspace/sdks/nv570/inc/class/clceb7.h new file mode 100644 index 0000000..df7a3bd --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clceb7.h @@ -0,0 +1,30 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef clceb7_h_ +#define clceb7_h_ + +#define NVCEB7_VIDEO_ENCODER (0x0000CEB7) + +#endif // clceb7_h + diff --git a/userspace/sdks/nv570/inc/class/clcec0.h b/userspace/sdks/nv570/inc/class/clcec0.h new file mode 100644 index 0000000..f73e705 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcec0.h @@ -0,0 +1,30 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clcec0_h_ +#define _clcec0_h_ + +#define BLACKWELL_COMPUTE_B 0xCEC0 + +#endif /* _clcec0_h_ */ + diff --git a/userspace/sdks/nv570/inc/class/clced0.h b/userspace/sdks/nv570/inc/class/clced0.h new file mode 100644 index 0000000..9f1192a --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clced0.h @@ -0,0 +1,30 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clced0_h_ +#define _clced0_h_ + +#define NVCED0_VIDEO_NVJPG (0x0000CED0) + +#endif // _clced0_h + diff --git a/userspace/sdks/nv570/inc/class/clcefa.h b/userspace/sdks/nv570/inc/class/clcefa.h new file mode 100644 index 0000000..6157f96 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcefa.h @@ -0,0 +1,30 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clcefa_h_ +#define _clcefa_h_ + +#define NVCEFA_VIDEO_OFA (0x0000CEFA) + +#endif // _clcefa_h + diff --git a/userspace/sdks/nv570/inc/class/clcfb0.h b/userspace/sdks/nv570/inc/class/clcfb0.h new file mode 100644 index 0000000..c3485ac --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcfb0.h @@ -0,0 +1,30 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clcfb0_h_ +#define _clcfb0_h_ + +#define NVCFB0_VIDEO_DECODER (0x0000CFB0) + +#endif /* _clcfb0_h_ */ + diff --git a/userspace/sdks/nv570/inc/class/clcfb7.h b/userspace/sdks/nv570/inc/class/clcfb7.h new file mode 100644 index 0000000..36aa79c --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcfb7.h @@ -0,0 +1,30 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clcfb7_h_ +#define _clcfb7_h_ + +#define NVCFB7_VIDEO_ENCODER (0x0000CFB7) + +#endif /* _clcfb7_h_ */ + diff --git a/userspace/sdks/nv570/inc/class/clcfd1.h b/userspace/sdks/nv570/inc/class/clcfd1.h new file mode 100644 index 0000000..6339df0 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcfd1.h @@ -0,0 +1,30 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clcfd1_h_ +#define _clcfd1_h_ + +#define NVCFD1_VIDEO_NVJPG (0x0000CFD1) + +#endif /* _clcfd1_h_ */ + diff --git a/userspace/sdks/nv570/inc/class/clcffa.h b/userspace/sdks/nv570/inc/class/clcffa.h new file mode 100644 index 0000000..e54be2d --- /dev/null +++ b/userspace/sdks/nv570/inc/class/clcffa.h @@ -0,0 +1,30 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clcffa_h_ +#define _clcffa_h_ + +#define NVCFFA_VIDEO_OFA (0x0000CFFAU) + +#endif /* _clcffa_h_ */ + diff --git a/userspace/sdks/nv570/inc/class/cld0b7.h b/userspace/sdks/nv570/inc/class/cld0b7.h new file mode 100644 index 0000000..d7c044d --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cld0b7.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef cld0b7_h +#define cld0b7_h + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVD0B7_VIDEO_ENCODER (0x0000D0B7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // cld0b7_h + diff --git a/userspace/sdks/nv570/inc/class/cld1b0.h b/userspace/sdks/nv570/inc/class/cld1b0.h new file mode 100644 index 0000000..006d0a7 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cld1b0.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef cld1b0_h_ +#define cld1b0_h_ + +#define NVD1B0_VIDEO_DECODER (0x0000D1B0) + +#endif // cld1b0_h diff --git a/userspace/sdks/nv570/inc/class/cld1b7.h b/userspace/sdks/nv570/inc/class/cld1b7.h new file mode 100644 index 0000000..e76867f --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cld1b7.h @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef cld1b7_h_ +#define cld1b7_h_ +#define NVD1B7_VIDEO_ENCODER (0x0000D1B7) +#endif // cld1b7_ diff --git a/userspace/sdks/nv570/inc/class/cld1fa.h b/userspace/sdks/nv570/inc/class/cld1fa.h new file mode 100644 index 0000000..d0f244e --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cld1fa.h @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef cld1fa_h_ +#define cld1fa_h_ +#define NVD1FA_VIDEO_OFA (0x0000D1FA) +#endif // cld1fa_h diff --git a/userspace/sdks/nv570/inc/class/cld2b0.h b/userspace/sdks/nv570/inc/class/cld2b0.h new file mode 100644 index 0000000..a5dd839 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cld2b0.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef cld2b0_h_ +#define cld2b0_h_ + +#define NVD2B0_VIDEO_DECODER (0x0000D2B0) + +#endif // cld2b0_h diff --git a/userspace/sdks/nv570/inc/class/cld2d1.h b/userspace/sdks/nv570/inc/class/cld2d1.h new file mode 100644 index 0000000..fd231fa --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cld2d1.h @@ -0,0 +1,30 @@ + +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef cld2d1_h_ +#define cld2d1_h_ + +#define NVD2D1_VIDEO_NVJPG (0x0000D2D1) + +#endif // cld2d1_h diff --git a/userspace/sdks/nv570/inc/class/cld2fa.h b/userspace/sdks/nv570/inc/class/cld2fa.h new file mode 100644 index 0000000..5b7fd55 --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cld2fa.h @@ -0,0 +1,28 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef cld2fa_h_ +#define cld2fa_h_ + +#define NVD2FA_VIDEO_OFA (0x0000D2FA) + +#endif // cld2fa_h diff --git a/userspace/sdks/nv570/inc/class/cld5b7.h b/userspace/sdks/nv570/inc/class/cld5b7.h new file mode 100644 index 0000000..171c7dd --- /dev/null +++ b/userspace/sdks/nv570/inc/class/cld5b7.h @@ -0,0 +1,30 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cld5b7_h_ +#define _cld5b7_h_ + +#define NVD5B7_VIDEO_ENCODER (0x0000D5B7) + +#endif /* _cld5b7_h_ */ + diff --git a/userspace/sdks/nv570/inc/cpuopsys.h b/userspace/sdks/nv570/inc/cpuopsys.h new file mode 100644 index 0000000..eab5359 --- /dev/null +++ b/userspace/sdks/nv570/inc/cpuopsys.h @@ -0,0 +1,421 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! \brief + * Define compile time symbols for CPU type and operating system type. + * This file should only contain preprocessor commands so that + * there are no dependencies on other files. + * + * cpuopsys.h + * + * Copyright (c) 2001-2025, Nvidia Corporation. All rights reserved. + */ + +/*! + * Uniform names are defined for compile time options to distinguish + * CPU types and Operating systems. + * Distinctions between CPU and OpSys should be orthogonal. + * + * These uniform names have initially been defined by keying off the + * makefile/build names defined for builds in the OpenGL group. + * Getting the uniform names defined for other builds may require + * different qualifications. + * + * The file is placed here to allow for the possibility of all driver + * components using the same naming convention for conditional compilation. + */ + +#ifndef CPUOPSYS_H +#define CPUOPSYS_H + +/*****************************************************************************/ +/* Define all OS/CPU-Chip related symbols */ + +/* ***** WINDOWS variations */ +#if defined(_WIN32) || defined(_WIN16) +# define NV_WINDOWS + +# if defined(_WIN32_WINNT) +# define NV_WINDOWS_NT +# elif defined(_WIN32_WCE) +# define NV_WINDOWS_CE +# else +# define NV_WINDOWS_9X +# endif +#endif /* _WIN32 || defined(_WIN16) */ + +/* ***** Unix variations */ +#if defined(__linux__) && !defined(NV_LINUX) && !defined(NV_VMWARE) +# define NV_LINUX +#endif /* defined(__linux__) */ + +#if defined(__VMWARE__) && !defined(NV_VMWARE) +# define NV_VMWARE +#endif /* defined(__VMWARE__) */ + +/* SunOS + gcc */ +#if defined(__sun__) && defined(__svr4__) && !defined(NV_SUNOS) +# define NV_SUNOS +#endif /* defined(__sun__) && defined(__svr4__) */ + +/* SunOS + Sun Compiler (named SunPro, Studio or Forte) */ +#if defined(__SUNPRO_C) || defined(__SUNPRO_CC) +# define NV_SUNPRO_C +# define NV_SUNOS +#endif /* defined(_SUNPRO_C) || defined(__SUNPRO_CC) */ + +#if defined(__FreeBSD__) && !defined(NV_BSD) +# define NV_BSD +#endif /* defined(__FreeBSD__) */ + +/* XXXar don't define NV_UNIX on MacOSX or vxworks or QNX */ +#if (defined(__unix__) || defined(__unix) || defined(__INTEGRITY) ) && !defined(nvmacosx) && !defined(vxworks) && !defined(NV_UNIX) && !defined(__QNX__) && !defined(__QNXNTO__)/* XXX until removed from Makefiles */ +# define NV_UNIX +#endif /* defined(__unix__) */ + +#if (defined(__QNX__) || defined(__QNXNTO__)) && !defined(NV_QNX) +# define NV_QNX +#endif + +#if (defined(__ANDROID__) || defined(ANDROID)) && !defined(NV_ANDROID) +# define NV_ANDROID +#endif + +#if defined(DceCore) && !defined(NV_DCECORE) +# define NV_DCECORE +#endif + +/* ***** Apple variations */ +#if defined(macintosh) || defined(__APPLE__) +# define NV_MACINTOSH +# if defined(__MACH__) +# define NV_MACINTOSH_OSX +# else +# define NV_MACINTOSH_OS9 +# endif +# if defined(__LP64__) +# define NV_MACINTOSH_64 +# endif +#endif /* defined(macintosh) */ + +/* ***** VxWorks */ +/* Tornado 2.21 is gcc 2.96 and #defines __vxworks. */ +/* Tornado 2.02 is gcc 2.7.2 and doesn't define any OS symbol, so we rely on */ +/* the build system #defining vxworks. */ +#if defined(__vxworks) || defined(vxworks) +# define NV_VXWORKS +#endif + +/* ***** Integrity OS */ +#if defined(__INTEGRITY) +# if !defined(NV_INTEGRITY) +# define NV_INTEGRITY +# endif +#endif + +/* ***** Processor type variations */ + +#if ((defined(_M_IX86) || defined(__i386__) || defined(__i386)) && !defined(NVCPU_X86)) /* XXX until removed from Makefiles */ +/* _M_IX86 for windows, __i386__ for Linux (or any x86 using gcc) */ +/* __i386 for Studio compiler on Solaris x86 */ +# define NVCPU_X86 /* any IA32 machine (not x86-64) */ +# define NVCPU_MIN_PAGE_SHIFT 12 +#endif + +#if defined(NV_LINUX) && defined(__ia64__) +# define NVCPU_IA64_LINUX /* any IA64 for Linux opsys */ +#endif +#if defined(NVCPU_IA64_WINDOWS) || defined(NVCPU_IA64_LINUX) || defined(IA64) +# define NVCPU_IA64 /* any IA64 for any opsys */ +#endif + +#if (defined(NV_MACINTOSH) && !(defined(__i386__) || defined(__x86_64__))) || defined(__PPC__) || defined(__ppc) +# if defined(__powerpc64__) && defined(__LITTLE_ENDIAN__) +# ifndef NVCPU_PPC64LE +# define NVCPU_PPC64LE /* PPC 64-bit little endian */ +# endif +# else +# ifndef NVCPU_PPC +# define NVCPU_PPC /* any non-PPC64LE PowerPC architecture */ +# endif +# ifndef NV_BIG_ENDIAN +# define NV_BIG_ENDIAN +# endif +# endif +# define NVCPU_FAMILY_PPC +#endif + +#if defined(__x86_64) || defined(AMD64) || defined(_M_AMD64) +# define NVCPU_X86_64 /* any x86-64 for any opsys */ +#endif + +#if defined(NVCPU_X86) || defined(NVCPU_X86_64) +# define NVCPU_FAMILY_X86 +#endif + +#if defined(__riscv) && (__riscv_xlen==64) +# define NVCPU_RISCV64 +# if defined(__nvriscv) +# define NVCPU_NVRISCV64 +# endif +#endif + +#if defined(__arm__) || defined(_M_ARM) +/* + * 32-bit instruction set on, e.g., ARMv7 or AArch32 execution state + * on ARMv8 + */ +# define NVCPU_ARM +# define NVCPU_MIN_PAGE_SHIFT 12 +#endif + +#if defined(__aarch64__) || defined(__ARM64__) || defined(_M_ARM64) +# define NVCPU_AARCH64 /* 64-bit A64 instruction set on ARMv8 */ +# define NVCPU_MIN_PAGE_SHIFT 12 +#endif + +#if defined(NVCPU_ARM) || defined(NVCPU_AARCH64) +# define NVCPU_FAMILY_ARM +#endif + +#if defined(__SH4__) +# ifndef NVCPU_SH4 +# define NVCPU_SH4 /* Renesas (formerly Hitachi) SH4 */ +# endif +# if defined NV_WINDOWS_CE +# define NVCPU_MIN_PAGE_SHIFT 12 +# endif +#endif + +/* For Xtensa processors */ +#if defined(__XTENSA__) +# define NVCPU_XTENSA +# if defined(__XTENSA_EB__) +# define NV_BIG_ENDIAN +# endif +#endif + + +/* + * Other flavors of CPU type should be determined at run-time. + * For example, an x86 architecture with/without SSE. + * If it can compile, then there's no need for a compile time option. + * For some current GCC limitations, these may be fixed by using the Intel + * compiler for certain files in a Linux build. + */ + +/* The minimum page size can be determined from the minimum page shift */ +#if defined(NVCPU_MIN_PAGE_SHIFT) +#define NVCPU_MIN_PAGE_SIZE (1 << NVCPU_MIN_PAGE_SHIFT) +#endif + +#if defined(NVCPU_IA64) || defined(NVCPU_X86_64) || \ + defined(NV_MACINTOSH_64) || defined(NVCPU_AARCH64) || \ + defined(NVCPU_PPC64LE) || defined(NVCPU_RISCV64) +# define NV_64_BITS /* all architectures where pointers are 64 bits */ +#else +/* we assume 32 bits. I don't see a need for NV_16_BITS. */ +#endif + +/* For verification-only features not intended to be included in normal drivers */ +#if defined(ENABLE_VERIF_FEATURES) +#define NV_VERIF_FEATURES +#endif + +/* + * New, safer family of #define's -- these ones use 0 vs. 1 rather than + * defined/!defined. This is advantageous because if you make a typo, + * say misspelled ENDIAN: + * + * #if NVCPU_IS_BIG_ENDAIN + * + * ...some compilers can give you a warning telling you that you screwed up. + * The compiler can also give you a warning if you forget to #include + * "cpuopsys.h" in your code before the point where you try to use these + * conditionals. + * + * Also, the names have been prefixed in more cases with "CPU" or "OS" for + * increased clarity. You can tell the names apart from the old ones because + * they all use "_IS_" in the name. + * + * Finally, these can be used in "if" statements and not just in #if's. For + * example: + * + * if (NVCPU_IS_BIG_ENDIAN) x = Swap32(x); + * + * Maybe some day in the far-off future these can replace the old #define's. + */ + +#define NV_IS_MODS 0 + +#define NVOS_IS_WINDOWS 0 +#if defined(NV_WINDOWS_CE) +#define NVOS_IS_WINDOWS_CE 1 +#else +#define NVOS_IS_WINDOWS_CE 0 +#endif +#if defined(NV_LINUX) +#define NVOS_IS_LINUX 1 +#else +#define NVOS_IS_LINUX 0 +#endif +#if defined(NV_UNIX) +#define NVOS_IS_UNIX 1 +#else +#define NVOS_IS_UNIX 0 +#endif +#if defined(NV_BSD) +#define NVOS_IS_FREEBSD 1 +#else +#define NVOS_IS_FREEBSD 0 +#endif +#if defined(NV_SUNOS) +#define NVOS_IS_SOLARIS 1 +#else +#define NVOS_IS_SOLARIS 0 +#endif +#define NVOS_IS_VMWARE 0 +#if defined(NV_QNX) +#define NVOS_IS_QNX 1 +#else +#define NVOS_IS_QNX 0 +#endif +#if defined(NV_ANDROID) +#define NVOS_IS_ANDROID 1 +#else +#define NVOS_IS_ANDROID 0 +#endif +#if defined(NV_MACINTOSH) +#define NVOS_IS_MACINTOSH 1 +#else +#define NVOS_IS_MACINTOSH 0 +#endif +#if defined(NV_VXWORKS) +#define NVOS_IS_VXWORKS 1 +#else +#define NVOS_IS_VXWORKS 0 +#endif +#if defined(NV_LIBOS) +#define NVOS_IS_LIBOS 1 +#else +#define NVOS_IS_LIBOS 0 +#endif +#if defined(NV_INTEGRITY) +#define NVOS_IS_INTEGRITY 1 +#else +#define NVOS_IS_INTEGRITY 0 +#endif + +#if defined(NVCPU_X86) +#define NVCPU_IS_X86 1 +#else +#define NVCPU_IS_X86 0 +#endif +#if defined(NVCPU_RISCV64) +#define NVCPU_IS_RISCV64 1 +#else +#define NVCPU_IS_RISCV64 0 +#endif +#if defined(NVCPU_NVRISCV64) +#define NVCPU_IS_NVRISCV64 1 +#else +#define NVCPU_IS_NVRISCV64 0 +#endif +#if defined(NVCPU_IA64) +#define NVCPU_IS_IA64 1 +#else +#define NVCPU_IS_IA64 0 +#endif +#if defined(NVCPU_X86_64) +#define NVCPU_IS_X86_64 1 +#else +#define NVCPU_IS_X86_64 0 +#endif +#if defined(NVCPU_FAMILY_X86) +#define NVCPU_IS_FAMILY_X86 1 +#else +#define NVCPU_IS_FAMILY_X86 0 +#endif +#if defined(NVCPU_PPC) +#define NVCPU_IS_PPC 1 +#else +#define NVCPU_IS_PPC 0 +#endif +#if defined(NVCPU_PPC64LE) +#define NVCPU_IS_PPC64LE 1 +#else +#define NVCPU_IS_PPC64LE 0 +#endif +#if defined(NVCPU_FAMILY_PPC) +#define NVCPU_IS_FAMILY_PPC 1 +#else +#define NVCPU_IS_FAMILY_PPC 0 +#endif +#if defined(NVCPU_ARM) +#define NVCPU_IS_ARM 1 +#else +#define NVCPU_IS_ARM 0 +#endif +#if defined(NVCPU_AARCH64) +#define NVCPU_IS_AARCH64 1 +#else +#define NVCPU_IS_AARCH64 0 +#endif +#if defined(NVCPU_FAMILY_ARM) +#define NVCPU_IS_FAMILY_ARM 1 +#else +#define NVCPU_IS_FAMILY_ARM 0 +#endif +#if defined(NVCPU_SH4) +#define NVCPU_IS_SH4 1 +#else +#define NVCPU_IS_SH4 0 +#endif +#if defined(NVCPU_XTENSA) +#define NVCPU_IS_XTENSA 1 +#else +#define NVCPU_IS_XTENSA 0 +#endif +#if defined(NV_BIG_ENDIAN) +#define NVCPU_IS_BIG_ENDIAN 1 +#else +#define NVCPU_IS_BIG_ENDIAN 0 +#endif +#if defined(NV_64_BITS) +#define NVCPU_IS_64_BITS 1 +#else +#define NVCPU_IS_64_BITS 0 +#endif +#if defined(NVCPU_FAMILY_ARM) +#define NVCPU_IS_PCIE_CACHE_COHERENT 0 +#else +#define NVCPU_IS_PCIE_CACHE_COHERENT 1 +#endif +#if defined(NV_DCECORE) +#define NVOS_IS_DCECORE 1 +#else +#define NVOS_IS_DCECORE 0 +#endif +/*****************************************************************************/ + +#endif /* CPUOPSYS_H */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000base.h b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000base.h new file mode 100644 index 0000000..6f49405 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000base.h @@ -0,0 +1,68 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000base.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV01_ROOT (client) control commands and parameters */ + +#define NV0000_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0000,NV0000_CTRL_##cat,idx) + +/* Client command categories (6bits) */ +#define NV0000_CTRL_RESERVED (0x00) +#define NV0000_CTRL_SYSTEM (0x01) +#define NV0000_CTRL_GPU (0x02) +#define NV0000_CTRL_GSYNC (0x03) +#define NV0000_CTRL_DIAG (0x04) +#define NV0000_CTRL_EVENT (0x05) +#define NV0000_CTRL_NVD (0x06) +#define NV0000_CTRL_SWINSTR (0x07) +#define NV0000_CTRL_PROC (0x09) +#define NV0000_CTRL_SYNC_GPU_BOOST (0x0A) +#define NV0000_CTRL_GPUACCT (0x0B) +#define NV0000_CTRL_VGPU (0x0C) +#define NV0000_CTRL_CLIENT (0x0D) + +// per-OS categories start at highest category and work backwards +#define NV0000_CTRL_OS_WINDOWS (0x3F) +#define NV0000_CTRL_OS_MACOS (0x3E) +#define NV0000_CTRL_OS_UNIX (0x3D) + + +/* + * NV0000_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0000_CTRL_CMD_NULL (0x0) /* finn: Evaluated from "(FINN_NV01_ROOT_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrl0000_base_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000client.h b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000client.h new file mode 100644 index 0000000..163d26a --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000client.h @@ -0,0 +1,208 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000client.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +#include "class/cl0000.h" +#include "rs_access.h" + +/* + * NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE + * + * This command may be used to query memory address space type associated with an object + * + * Parameters: + * hObject[IN] + * handle of the object to look up + * addrSpaceType[OUT] + * addrSpaceType with associated memory descriptor + * + * Possible status values are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_OBJECT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE (0xd01) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS { + NvHandle hObject; /* [in] - Handle of object to look up */ + NvU32 mapFlags; /* [in] - Flags that will be used when mapping the object */ + NvU32 addrSpaceType; /* [out] - Memory Address Space Type */ +} NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS; + +#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_INVALID 0x00000000 +#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_SYSMEM 0x00000001 +#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM 0x00000002 +#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_REGMEM 0x00000003 +#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC 0x00000004 +#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC_MC 0x00000005 + +/* + * NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO + * + * This command may be used to query information on a handle + */ +#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO (0xd02) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS { + NvHandle hObject; /* [in] - Handle of object to look up */ + NvU32 index; /* [in] - Type of lookup */ + + union { + NvHandle hResult; /* [out] - Result of lookup when result is a handle type */ + NV_DECLARE_ALIGNED(NvU64 iResult, 8); /* [out] - Result of lookup when result is a integer */ + } data; +} NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS; + +#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_INVALID 0x00000000 +#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_PARENT 0x00000001 +#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_CLASSID 0x00000002 + +/* + * NV0000_CTRL_CMD_CLIENT_GET_ACCESS_RIGHTS + * + * This command may be used to get this client's access rights for an object + * The object to which access rights are checked does not have to be owned by + * the client calling the command, it is owned by the hClient parameter + */ +#define NV0000_CTRL_CMD_CLIENT_GET_ACCESS_RIGHTS (0xd03) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS { + NvHandle hObject; /* [in] - Handle of object to look up */ + NvHandle hClient; /* [in] - Handle of client which owns hObject */ + RS_ACCESS_MASK maskResult; /* [out] - Result of lookup */ +} NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS; + +/* + * NV0000_CTRL_CMD_CLIENT_SET_INHERITED_SHARE_POLICY + * + * DEPRECATED: Calls NV0000_CTRL_CMD_CLIENT_SHARE_OBJECT with hObject=hClient + * + * This command will modify a client's inherited share policy list + * The policy is applied in the same way that NvRmShare applies policies, + * except to the client's inherited policy list instead of an object's policy list + */ +#define NV0000_CTRL_CMD_CLIENT_SET_INHERITED_SHARE_POLICY (0xd04) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS { + RS_SHARE_POLICY sharePolicy; /* [in] - Share Policy to apply */ +} NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS; + +/* + * NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE + * + * This command may be used to get a handle of a child of a given type + */ +#define NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE (0xd05) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS { + NvHandle hParent; /* [in] - Handle of parent object */ + NvU32 classId; /* [in] - Class ID of the child object */ + NvHandle hObject; /* [out] - Handle of the child object (0 if not found) */ +} NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS; + +/* + * NV0000_CTRL_CMD_CLIENT_SHARE_OBJECT + * + * This command is meant to imitate the NvRmShare API. + * Applies a share policy to an object, which should be owned by the caller's client. + * The policy is applied in the same way that NvRmShare applies policies. + * + * This ctrl command is only meant to be used in older branches. For releases after R450, + * use NvRmShare directly instead. + */ +#define NV0000_CTRL_CMD_CLIENT_SHARE_OBJECT (0xd06) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS { + NvHandle hObject; /* [in] - Handle of object to share */ + RS_SHARE_POLICY sharePolicy; /* [in] - Share Policy to apply */ +} NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS; + +/* + * NV0000_CTRL_CMD_CLIENT_OBJECTS_ARE_DUPLICATES + * + * This command returns true if the objects are duplicates. + * + * Currently supported only for memory objects. + */ +#define NV0000_CTRL_CMD_CLIENT_OBJECTS_ARE_DUPLICATES (0xd07) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS { + NvHandle hObject1; /* [in] - Handle of object to be checked */ + NvHandle hObject2; /* [in] - Handle of object to be checked */ + NvBool bDuplicates; /* [out] - Returns true if duplicates */ +} NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS; + +/* + * NV0000_CTRL_CMD_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL: + * + * Subscribes to the first accessible or provided channel. + * Subscription is valid throughout the lifetime of a client. + * + * devDescriptor [OPAQUE IN] + * devDescriptor is an IMEX file descriptor for UNIX RM clients, but a void + * pointer for windows RM clients. It is transparent to RM clients i.e. RM's + * user-mode shim populates this field on behalf of clients. + * + * channel [IN/OUT] + * Channel number to which the client is subscribed + * If -1 is passed, RM picks the first accessible channel. + */ +#define NV0000_CTRL_CMD_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL (0xd08) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS { + NV_DECLARE_ALIGNED(NvU64 devDescriptor, 8); + NvU32 channel; +} NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS; + + + +/* _ctrl0000client_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000diag.h b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000diag.h new file mode 100644 index 0000000..45f421e --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000diag.h @@ -0,0 +1,324 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000diag.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +/* NV01_ROOT (client) system control commands and parameters */ + +/* + * NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_STATE + * + * This command returns the current lock meter logging state. + * + * state + * This parameter returns the current lock meter logging state. + * NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_DISABLED + * This value indicates lock metering is disabled. + * NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_ENABLED + * This value indicates lock metering is enabled. + * count + * This parameter returns the total number of lock metering entries + * (NV0000_CTRL_DIAG_LOCK_METER_ENTRY) available. This value will + * not exceed NV0000_CTRL_DIAG_LOCK_METER_MAX_ENTRIES. When lock metering + * is enabled this parameter will return zero. + * missedCount + * This parameter returns the number of lock metering entries that had + * to be discarded due to a full lock metering table. This value will + * not exceed NV0000_CTRL_DIAG_LOCK_METER_MAX_TABLE_ENTRIES. When lock + * metering is enabled this parameter will return zero. + * bCircularBuffer + * This parameter returns type of buffer. + * TRUE + * Buffer is circular + * FALSE + * Buffer is sequential + * + * Possible status values returned are: + * NV_OK + */ +#define NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_STATE (0x480) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS_MESSAGE_ID (0x80U) + +typedef struct NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS { + NvU32 state; + NvU32 count; + NvU32 missedCount; + NvBool bCircularBuffer; +} NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS; + +/* valid lock metering state values */ +#define NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_DISABLED (0x00000000) +#define NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_ENABLED (0x00000001) + +/* maximum possible number of lock metering entries stored internally */ +#define NV0000_CTRL_DIAG_LOCK_METER_MAX_TABLE_ENTRIES (0x20000) + +/* + * NV0000_CTRL_CMD_DIAG_SET_LOCK_METER_STATE + * + * This command sets the current lock meter logging state. + * + * state + * This parameter specifies the new state of the lock metering mechanism. + * Legal state values are: + * NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_DISABLE + * This value disables lock metering. + * NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_ENABLE + * This value enables lock metering. + * NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_RESET + * This value resets, or clears, all lock metering state. Lock + * metering must be disabled prior to attempting a reset. + * bCircularBuffer + * This parameter specifies type of buffer. + * Possible values are: + * TRUE + * For circular buffer. + * FALSE + * For sequential buffer. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV0000_CTRL_CMD_DIAG_SET_LOCK_METER_STATE (0x481) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS { + NvU32 state; + NvBool bCircularBuffer; +} NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS; + +/* valid lock metering state values */ +#define NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_DISABLE (0x00000000) +#define NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_ENABLE (0x00000001) +#define NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_RESET (0x00000002) + +/* + * NV0000_CTRL_DIAG_LOCK_METER_ENTRY + * + * This structure represents a single lock meter entry. + * + * counter + * This field contains the number of nanonseconds elapsed since the + * the last system boot when the lock meter entry was generated. + * freq + * This field contains the CPU performance counter frequency in units + * of ticks per second. + * line + * This field contains the relevant line number. + * filename + * This field contains the relevant file name. + * tag + * This field contains a tag uniquely identifying the user of the metered + * lock operations. + * cpuNum + * This field contains the CPU number from which the metered operation + * was initiated. + * irql + * This field contains the IRQL at which the metered operation was + * initiated. + * data0 + * data1 + * data2 + * These fields contain tag-specific data. + */ +#define NV0000_CTRL_DIAG_LOCK_METER_ENTRY_FILENAME_LENGTH (0xc) + +typedef struct NV0000_CTRL_DIAG_LOCK_METER_ENTRY { + NV_DECLARE_ALIGNED(NvU64 counter, 8); + + NvU32 line; + NvU8 filename[NV0000_CTRL_DIAG_LOCK_METER_ENTRY_FILENAME_LENGTH]; + + NvU16 tag; + NvU8 cpuNum; + NvU8 irql; + + NV_DECLARE_ALIGNED(NvU64 threadId, 8); + + NvU32 data0; + NvU32 data1; + NvU32 data2; +} NV0000_CTRL_DIAG_LOCK_METER_ENTRY; + +/* valid lock meter entry tag values */ +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA (0x00000001) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_FORCED (0x00000002) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_COND (0x00000003) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_SEMA (0x00000004) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_API (0x00000010) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_API (0x00000011) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_GPUS (0x00000020) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_GPUS (0x00000021) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_DATA (0x00000100) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RMCTRL (0x00001000) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GETEX (0x00002002) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SETEX (0x00002003) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_VIDHEAP (0x00003000) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM (0x00003001) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM (0x00003002) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM_DMA (0x00003003) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM_DMA (0x00003004) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC (0x00004000) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_MEM (0x00004001) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_DUP_OBJECT (0x00004010) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CLIENT (0x00005000) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DEVICE (0x00005001) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE (0x00005002) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE_DIAG (0x00005003) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP (0x00005004) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP_CMN (0x00005005) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL (0x00005006) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_MPEG (0x00005007) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_DISP (0x00005008) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_MEMORY (0x00005009) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_FBMEM (0x0000500A) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_OBJECT (0x0000500B) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_EVENT (0x0000500C) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_IDLE_CHANNELS (0x00006000) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_BIND_CTXDMA (0x00007000) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_CTXDMA (0x00007001) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ISR (0x0000F000) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_DPC (0x0000F00F) + +/* + * NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_ENTRIES + * + * This command returns lock metering data in a fixed-sized array of entries. + * Each request will return up NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_MAX_ENTRIES + * entries. + * + * It is up to the caller to repeat these requests to retrieve the total number + * of entries reported by NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_STATE. + * + * entryCount + * This parameter returns the total number of valid entries returned + * in the entries array. This value will not exceed + * NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_MAX but may be less. + * A value of zero indicates there are no more valid entries. + * entries + * This parameter contains the storage into which lock metering entry + * data is returned. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_ENTRIES (0x485) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS_MESSAGE_ID" */ + +/* total number of entries returned */ +#define NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_MAX (0x40) + +#define NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS_MESSAGE_ID (0x85U) + +typedef struct NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS { + NvU32 entryCount; + NV_DECLARE_ALIGNED(NV0000_CTRL_DIAG_LOCK_METER_ENTRY entries[NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_MAX], 8); +} NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS; + +/* + * NV0000_CTRL_CMD_DIAG_PROFILE_RPC + * + * This command returns the RPC runtime information, and + * will only return valid when it is running inside VGX mode. + * + * rpcProfileCmd: + * RPC profiler command issued by rpc profiler utility + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_DIAG_PROFILE_RPC (0x488) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS_MESSAGE_ID" */ + +typedef struct RPC_METER_ENTRY { + NV_DECLARE_ALIGNED(NvU64 startTimeInNs, 8); + NV_DECLARE_ALIGNED(NvU64 endTimeInNs, 8); + NV_DECLARE_ALIGNED(NvU64 rpcDataTag, 8); + NV_DECLARE_ALIGNED(NvU64 rpcExtraData, 8); +} RPC_METER_ENTRY; + +#define NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS_MESSAGE_ID (0x88U) + +typedef struct NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS { + NvU32 rpcProfileCmd; +} NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS; + +#define NV0000_CTRL_PROFILE_RPC_CMD_DISABLE (0x00000000) +#define NV0000_CTRL_PROFILE_RPC_CMD_ENABLE (0x00000001) +#define NV0000_CTRL_PROFILE_RPC_CMD_RESET (0x00000002) + +/* + * NV0000_CTRL_CMD_DIAG_DUMP_RPC + * + * This command returns the RPC runtime information, which + * will be logged by NV0000_CTRL_CMD_DIAG_PROFILE_RPC command + * when running inside VGX mode. + * + * When issuing this command, the RPC profiler has to be disabled. + * + * firstEntryOffset: + * [IN] offset for first entry. + * + * outputEntryCout: + * [OUT] number of entries returned in rpcProfilerBuffer. + * + * remainingEntryCount: + * [OUT] number of entries remaining. + * + * elapsedTimeInNs: + * [OUT] runtime for the RPC profiler tool. + * + * rpcProfilerBuffer: + * [OUT] buffer to store the RPC entries + */ + +#define NV0000_CTRL_CMD_DIAG_DUMP_RPC (0x489) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_DUMP_RPC_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_DIAG_RPC_MAX_ENTRIES (100) + +#define NV0000_CTRL_DIAG_DUMP_RPC_PARAMS_MESSAGE_ID (0x89U) + +typedef struct NV0000_CTRL_DIAG_DUMP_RPC_PARAMS { + NvU32 firstEntryOffset; + NvU32 outputEntryCount; + NvU32 remainingEntryCount; + NV_DECLARE_ALIGNED(NvU64 elapsedTimeInNs, 8); + NV_DECLARE_ALIGNED(RPC_METER_ENTRY rpcProfilerBuffer[NV0000_CTRL_DIAG_RPC_MAX_ENTRIES], 8); +} NV0000_CTRL_DIAG_DUMP_RPC_PARAMS; + +/* _ctrl0000diag_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000event.h b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000event.h new file mode 100644 index 0000000..ded1265 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000event.h @@ -0,0 +1,145 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000event.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +#include "class/cl0000.h" + +#define NV0000_NOTIFIERS_DISPLAY_CHANGE (0) +#define NV0000_NOTIFIERS_VGPU_UNBIND_EVENT (1) +#define NV0000_NOTIFIERS_VGPU_BIND_EVENT (2) +#define NV0000_NOTIFIERS_GPU_BIND_UNBIND_EVENT (3) +#define NV0000_NOTIFIERS_MAXCOUNT (4) + +/* + * NV0000_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * This command sets event notification for the system events. + * + * event + * This parameter specifies the type of event to which the specified + * action is to be applied. The valid event values can be found in + * cl0000.h. + * + * action + * This parameter specifies the desired event notification action. + * Valid notification actions include: + * NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE + * This action disables event notification for the specified + * event. + * NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE + * This action enables single-shot event notification for the + * specified event. + * NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT + * This action enables repeated event notification for the + * specified event. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_CLIENT + * + */ + +#define NV0000_CTRL_CMD_EVENT_SET_NOTIFICATION (0x501) /* finn: Evaluated from "(FINN_NV01_ROOT_EVENT_INTERFACE_ID << 8) | NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS { + NvU32 event; + NvU32 action; +} NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001) +#define NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002) + +typedef struct NV0000_CTRL_SYSTEM_EVENT_DATA_DISPLAY_CHANGE { + NvU32 deviceMask; +} NV0000_CTRL_SYSTEM_EVENT_DATA_DISPLAY_CHANGE; + +typedef struct NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_UNBIND { + NvU32 gpuId; +} NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_UNBIND; + +typedef struct NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_BIND { + NvU32 gpuId; +} NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_BIND; + +typedef struct NV0000_CTRL_SYSTEM_EVENT_DATA_GPU_BIND_UNBIND { + NvU32 gpuId; + NvBool bBind; +} NV0000_CTRL_SYSTEM_EVENT_DATA_GPU_BIND_UNBIND; + +/* + * NV0000_CTRL_CMD_GET_SYSTEM_EVENT_DATA + * + * This command reads the client's event data queue info FIFO order. + * See the description of NV01_EVENT for details on registering events. + * + * event + * Output only as selective event data query is not supported yet. + * Event type. + * Valid event type values can be found in this header file. + * + * data + * Data associated with the event. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND when system event queue is empty + * + */ + +#define NV0000_CTRL_CMD_GET_SYSTEM_EVENT_DATA (0x502) /* finn: Evaluated from "(FINN_NV01_ROOT_EVENT_INTERFACE_ID << 8) | NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS { + NvU32 event; + + union { + NV0000_CTRL_SYSTEM_EVENT_DATA_DISPLAY_CHANGE display; + NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_UNBIND vgpuUnbind; + NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_BIND vgpuBind; + NV0000_CTRL_SYSTEM_EVENT_DATA_GPU_BIND_UNBIND gpuBindUnbind; + } data; +} NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS; + +/* _ctrl0000event_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000gpu.h b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000gpu.h new file mode 100644 index 0000000..6cbc76f --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000gpu.h @@ -0,0 +1,1122 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000gpu.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl2080/ctrl2080nvlink_common.h" +#include "nvlimits.h" + +/* NV01_ROOT (client) GPU control commands and parameters */ + +typedef NV2080_CTRL_NVLINK_LINK_MASK NV0000_CTRL_NVLINK_LINK_MASK; + +/* + * NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS + * + * This command returns a table of attached gpuId values. + * The table is NV0000_CTRL_GPU_MAX_ATTACHED_GPUS entries in size. + * + * gpuIds[] + * This parameter returns the table of attached GPU IDs. + * The GPU ID is an opaque platform-dependent value that can be used + * with the NV0000_CTRL_CMD_GPU_GET_ID_INFO command to retrieve + * additional information about the GPU. The valid entries in gpuIds[] + * are contiguous, with a value of NV0000_CTRL_GPU_INVALID_ID indicating + * the invalid entries. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS (0x201U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_MAX_ATTACHED_GPUS 32U +#define NV0000_CTRL_GPU_INVALID_ID (0xffffffffU) + +#define NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS { + NvU32 gpuIds[NV0000_CTRL_GPU_MAX_ATTACHED_GPUS]; +} NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS; + +/* + * Deprecated. Please use NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 instead. + */ +#define NV0000_CTRL_CMD_GPU_GET_ID_INFO (0x202U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_MAX_SZNAME 128U + +#define NV0000_CTRL_NO_NUMA_NODE (-1) + +#define NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_GPU_GET_ID_INFO_PARAMS { + NvU32 gpuId; + NvU32 gpuFlags; + NvU32 deviceInstance; + NvU32 subDeviceInstance; + NV_DECLARE_ALIGNED(NvP64 szName, 8); + NvU32 sliStatus; + NvU32 boardId; + NvU32 gpuInstance; + NvS32 numaId; +} NV0000_CTRL_GPU_GET_ID_INFO_PARAMS; + +#define NV0000_CTRL_SLI_STATUS_OK (0x00000000U) +#define NV0000_CTRL_SLI_STATUS_OS_NOT_SUPPORTED (0x00000002U) +#define NV0000_CTRL_SLI_STATUS_GPU_NOT_SUPPORTED (0x00000040U) +#define NV0000_CTRL_SLI_STATUS_INVALID_GPU_COUNT (0x00000001U) + +/* + * NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 + * This command returns GPU instance information for the specified GPU. + * + * [in] gpuId + * This parameter should specify a valid GPU ID value. If there + * is no GPU present with the specified ID, a status of + * NV_ERR_INVALID_ARGUMENT is returned. + * [out] gpuFlags + * This parameter returns various flags values for the specified GPU. + * Valid flag values include: + * NV0000_CTRL_GPU_ID_INFO_IN_USE + * When true this flag indicates there are client references + * to the GPU in the form of device class instantiations (see + * NV01_DEVICE or NV03_DEVICE descriptions for details). + * NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE + * When true this flag indicates the GPU is linked into an + * active SLI device. + * NV0000_CTRL_GPU_ID_INFO_MOBILE + * When true this flag indicates the GPU is a mobile GPU. + * NV0000_CTRL_GPU_ID_BOOT_MASTER + * When true this flag indicates the GPU is the boot master GPU. + * NV0000_CTRL_GPU_ID_INFO_SOC + * When true this flag indicates the GPU is part of a + * System-on-Chip (SOC). + * NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED + * When ATS is enabled on the system. + * NV0000_CTRL_GPU_ID_INFO_SOC_TYPE + * This field indicates the GPU type for SOC-based GPUs. Legal values + * for this field include: + * NV0000_CTRL_GPU_ID_INFO_SOC_TYPE_NONE + * This value indicates the GPU is not an SOC GPU. + * NV0000_CTRL_GPU_ID_INFO_SOC_TYPE_DISPLAY + * This value indicates the GPU is an SOC display GPU. + * NV0000_CTRL_GPU_ID_INFO_SOC_TYPE_IGPU + * This value indicates the GPU is an iGPU. + * NV0000_CTRL_GPU_ID_INFO_SOC_TYPE_DISPLAY_AND_IGPU + * This value indicates the GPU is both an iGPU and an SOC + * display GPU. + * [out] deviceInstance + * This parameter returns the broadcast device instance number associated + * with the specified GPU. This value can be used to instantiate + * a broadcast reference to the GPU using the NV01_DEVICE classes. + * [out] subDeviceInstance + * This parameter returns the unicast subdevice instance number + * associated with the specified GPU. This value can be used to + * instantiate a unicast reference to the GPU using the NV20_SUBDEVICE + * classes. + * [out] sliStatus + * This parameters returns the SLI status for the specified GPU. + * Legal values for this member are described by NV0000_CTRL_SLI_STATUS. + * [out] boardId + * This parameter returns the board ID value with which the + * specified GPU is associated. Multiple GPUs can share the + * same board ID in multi-GPU configurations. + * [out] gpuInstance + * This parameter returns the GPU instance number for the specified GPU. + * GPU instance numbers are assigned in bus-probe order beginning with + * zero and are limited to one less the number of GPUs in the system. + * [out] numaId + * This parameter returns the ID of NUMA node for the specified GPU or + * the subscribed MIG partition when MIG is enabled. + * In case there is no NUMA node, NV0000_CTRL_NO_NUMA_NODE is returned. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + + + +#define NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 (0x205U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS { + NvU32 gpuId; + NvU32 gpuFlags; + NvU32 deviceInstance; + NvU32 subDeviceInstance; + NvU32 sliStatus; + NvU32 boardId; + NvU32 gpuInstance; + NvS32 numaId; +} NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS; + + +/* valid flags values */ +#define NV0000_CTRL_GPU_ID_INFO_IN_USE 0:0 +#define NV0000_CTRL_GPU_ID_INFO_IN_USE_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_IN_USE_TRUE (0x00000001U) +#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE 1:1 +#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_TRUE (0x00000001U) +#define NV0000_CTRL_GPU_ID_INFO_MOBILE 2:2 +#define NV0000_CTRL_GPU_ID_INFO_MOBILE_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_MOBILE_TRUE (0x00000001U) +#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER 3:3 +#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_TRUE (0x00000001U) + + +#define NV0000_CTRL_GPU_ID_INFO_SOC 5:5 +#define NV0000_CTRL_GPU_ID_INFO_SOC_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_SOC_TRUE (0x00000001U) +#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED 6:6 +#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE (0x00000001U) +#define NV0000_CTRL_GPU_ID_INFO_SOC_TYPE 8:7 +#define NV0000_CTRL_GPU_ID_INFO_SOC_TYPE_NONE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_SOC_TYPE_DISPLAY (0x00000001U) +#define NV0000_CTRL_GPU_ID_INFO_SOC_TYPE_IGPU (0x00000002U) +#define NV0000_CTRL_GPU_ID_INFO_SOC_TYPE_DISPLAY_AND_IGPU (0x00000003U) + +/* + * NV0000_CTRL_CMD_GPU_GET_INIT_STATUS + * + * This command returns the initialization status for the specified GPU, and + * will return NV_ERR_INVALID_STATE if called prior to GPU + * initialization. + * + * gpuId + * This parameter should specify a valid GPU ID value. If there + * is no GPU present with the specified ID, a status of + * NV_ERR_INVALID_ARGUMENT is returned. + * status + * This parameter returns the status code identifying the initialization + * state of the GPU. If this parameter has the value NV_OK, + * then no errors were detected during GPU initialization. Otherwise, this + * parameter specifies the top-level error that was detected during GPU + * initialization. Note that a value of NV_OK only means that + * no errors were detected during the actual GPU initialization, and other + * errors may have occurred that prevent the GPU from being attached or + * accessible via the NV01_DEVICE or NV20_SUBDEVICE classes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV0000_CTRL_CMD_GPU_GET_INIT_STATUS (0x203U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS { + NvU32 gpuId; + NvU32 status; +} NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS + * + * This command returns a mask of valid device IDs. These device IDs + * can be used to instantiate the NV01_DEVICE_0 class (see NV01_DEVICE_0 + * for more information). + * + * deviceIds + * This parameter returns the mask of valid device IDs. Each enabled bit + * in the mask corresponds to a valid device instance. Valid device + * instances can be used to initialize the NV0080_ALLOC_PARAMETERS + * structure when using NvRmAlloc to instantiate device handles. The + * number of device IDs will not exceed NV_MAX_DEVICES in number. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS (0x204U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS { + NvU32 deviceIds; +} NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS; + + + +/* + * NV0000_CTRL_CMD_GPU_GET_PROBED_IDS + * + * This command returns a table of probed gpuId values. + * The table is NV0000_CTRL_GPU_MAX_PROBED_GPUS entries in size. + * + * gpuIds[] + * This parameter returns the table of probed GPU IDs. + * The GPU ID is an opaque platform-dependent value that can + * be used with the NV0000_CTRL_CMD_GPU_ATTACH_IDS and + * NV0000_CTRL_CMD_GPU_DETACH_ID commands to attach and detach + * the GPU. + * The valid entries in gpuIds[] are contiguous, with a value + * of NV0000_CTRL_GPU_INVALID_ID indicating the invalid entries. + * excludedGpuIds[] + * This parameter returns the table of excluded GPU IDs. + * An excluded GPU ID is an opaque platform-dependent value that + * can be used with NV0000_CTRL_CMD_GPU_GET_PCI_INFO and + * NV0000_CTRL_CMD_GPU_GET_UUID_INFO. + * The valid entries in excludedGpuIds[] are contiguous, with a value + * of NV0000_CTRL_GPU_INVALID_ID indicating the invalid entries. + * gpuFlags[] + * This parameter returns flags for each valid entry in the gpuIds[] + * table. Note that excluded GPUs do not have a gpuFlags[] entry. + * Valid flag values include: + * NV0000_CTRL_GPU_PROBED_ID_INFO_FLAGS_SOC_DISPLAY + * When TRUE this flag indicates the GPU supports SOC Display + * functionality. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0000_CTRL_CMD_GPU_GET_PROBED_IDS (0x214U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_MAX_PROBED_GPUS NV_MAX_DEVICES + +#define NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS { + NvU32 gpuIds[NV0000_CTRL_GPU_MAX_PROBED_GPUS]; + NvU32 excludedGpuIds[NV0000_CTRL_GPU_MAX_PROBED_GPUS]; + NvU32 gpuFlags[NV0000_CTRL_GPU_MAX_PROBED_GPUS]; +} NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS; + +/* valid flags values */ +#define NV0000_CTRL_GPU_PROBED_ID_FLAGS_SOC_DISPLAY 0:0 +#define NV0000_CTRL_GPU_PROBED_ID_FLAGS_SOC_DISPLAY_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_PROBED_ID_FLAGS_SOC_DISPLAY_TRUE (0x00000001U) + +/* + * NV0000_CTRL_CMD_GPU_GET_PCI_INFO + * + * This command takes a gpuId and returns PCI bus information about + * the device. If the OS does not support returning PCI bus + * information, this call will return NV_ERR_NOT_SUPPORTED + * + * gpuId + * This parameter should specify a valid GPU ID value. If there + * is no GPU present with the specified ID, a status of + * NV_ERR_INVALID_ARGUMENT is returned. + * + * domain + * This parameter returns the PCI domain of the GPU. + * + * bus + * This parameter returns the PCI bus of the GPU. + * + * slot + * This parameter returns the PCI slot of the GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_GPU_GET_PCI_INFO (0x21bU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID (0x1BU) + +typedef struct NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS { + NvU32 gpuId; + NvU32 domain; + NvU16 bus; + NvU16 slot; +} NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_ATTACH_IDS + * + * This command attaches the GPUs with the gpuIds matching those in + * the table provided by the client. + * The table is NV0000_CTRL_GPU_MAX_PROBED_GPUS entries in size. + * + * gpuIds[] + * This parameter holds the table of gpuIds to attach. At least + * one gpuId must be specified; clients may use the special + * gpuId value NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS to indicate + * that all probed GPUs are to be attached. + * The entries in gpuIds[] must be contiguous, with a value of + * NV0000_CTRL_GPU_INVALID_ID to indicate the first invalid + * entry. + * If one or more of the gpuId values do not specify a GPU found + * in the system, the NV_ERR_INVALID_ARGUMENT error + * status is returned. + * + * failedId + * If NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS is specified and + * a GPU cannot be attached, the NV0000_CTRL_CMD_GPU_ATTACH_IDS + * command returns an error code and saves the failing GPU's + * gpuId in this field. + * + * If a table of gpuIds is provided, these gpuIds will be validated + * against the RM's table of probed gpuIds and attached in turn, + * if valid; if NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS is used, all + * probed gpuIds will be attached, in the order the associated GPUs + * were probed in by the RM. + * + * If a gpuId fails to attach, this gpuId is stored in the failedId + * field. Any GPUs attached by the command prior the failure are + * detached. + * + * If multiple clients use NV0000_CTRL_CMD_GPU_ATTACH_IDS to attach + * a gpuId, the RM ensures that the gpuId won't be detached until + * all clients have issued a call to NV0000_CTRL_CMD_GPU_DETACH_IDS + * to detach the gpuId (or have terminated). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OPERATING_SYSTEM + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_IRQ_EDGE_TRIGGERED + * NV_ERR_IRQ_NOT_FIRING + */ +#define NV0000_CTRL_CMD_GPU_ATTACH_IDS (0x215U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS (0x0000ffffU) + +#define NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV0000_CTRL_GPU_ATTACH_IDS_PARAMS { + NvU32 gpuIds[NV0000_CTRL_GPU_MAX_PROBED_GPUS]; + NvU32 failedId; +} NV0000_CTRL_GPU_ATTACH_IDS_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_DETACH_IDS + * + * This command detaches the GPUs with the gpuIds matching those in + * the table provided by the client. + * The table is NV0000_CTRL_GPU_MAX_ATTACHED_GPUS entries in size. + * + * gpuIds[] + * This parameter holds the table of gpuIds to detach. At least + * one gpuId must be specified; clients may use the special + * gpuId NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS to indicate that + * all attached GPUs are to be detached. + * The entries in gpuIds[] must be contiguous, with a value of + * NV0000_CTRL_GPU_INVALID_ID to indicate the first invalid + * entry. + * If one or more of the gpuId values do not specify a GPU found + * in the system, the NV_ERR_INVALID_ARGUMENT error + * status is returned. + * + * If a table of gpuIds is provided, these gpuIds will be validated + * against the RM's list of attached gpuIds; each valid gpuId is + * detached immediately if it's no longer in use (i.e. if there are + * no client references to the associated GPU in the form of + * device class instantiations (see the NV01_DEVICE or NV03_DEVICE + * descriptions for details)) and if no other client still requires + * the associated GPU to be attached. + * + * If a given gpuId can't be detached immediately, it will instead + * be detached when the last client reference is freed or when + * the last client that issued NV0000_CTRL_CMD_GPU_ATTACH_IDS for + * this gpuId either issues NV0000_CTRL_CMD_GPU_DETACH_IDS or exits + * without detaching the gpuId explicitly. + * + * Clients may use the NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS command + * to obtain a table of the attached gpuIds. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OPERATING_SYSTEM + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_GPU_DETACH_IDS (0x216U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS (0x0000ffffU) + +#define NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV0000_CTRL_GPU_DETACH_IDS_PARAMS { + NvU32 gpuIds[NV0000_CTRL_GPU_MAX_ATTACHED_GPUS]; +} NV0000_CTRL_GPU_DETACH_IDS_PARAMS; + + + +/* + * NV0000_CTRL_CMD_GPU_GET_VIDEO_LINKS + * + * This command returns information about video bridge connections + * detected between GPUs in the system, organized as a table + * with one row per attached GPU and none, one or more peer GPUs + * listed in the columns of each row, if connected to the row head + * GPU via a video bridge. + * + * gpuId + * For each row, this field holds the GPU ID of the GPU + * whose connections are listed in the row. + * + * connectedGpuIds + * For each row, this table holds the GPU IDs of the + * GPUs connected to the GPU identified via the 'gpuId' + * field. + * + * links + * This table holds information about the video bridges + * connected between GPUs in the system. Each row + * represents connections to a single GPU. + * + * Please note: the table only reports video links between already + * attached GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_GPU_GET_VIDEO_LINKS (0x219U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_MAX_VIDEO_LINKS 8U + +typedef struct NV0000_CTRL_GPU_VIDEO_LINKS { + NvU32 gpuId; + NvU32 connectedGpuIds[NV0000_CTRL_GPU_MAX_VIDEO_LINKS]; +} NV0000_CTRL_GPU_VIDEO_LINKS; + +#define NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS { + NV0000_CTRL_GPU_VIDEO_LINKS links[NV0000_CTRL_GPU_MAX_ATTACHED_GPUS]; +} NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS; + + + +/* + * NV0000_CTRL_CMD_GPU_GET_UUID_INFO + * + * This command returns requested information pertaining to the GPU + * specified by the GPU UUID passed in. + * + * Generally only GPUs that have been attached are visible to this call. Therefore + * queries on unattached GPUs will fail with NV_ERR_OBJECT_NOT_FOUND. However, + * a query for a SHA1 UUID may succeed for an unattached GPU in cases where the GID + * is cached, such as an excluded GPU. + * + * gpuGuid (INPUT) + * The GPU UUID of the gpu whose parameters are to be returned. Refer to + * NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information. + * + * flags (INPUT) + * The _FORMAT* flags designate ascii string format or a binary format. + * + * The _TYPE* flags designate either SHA-1-based (32-hex-character) or + * SHA-256-based (64-hex-character). + * + * gpuId (OUTPUT) + * The GPU ID of the GPU identified by gpuGuid. Refer to + * NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information. + * + * deviceInstance (OUTPUT) + * The device instance of the GPU identified by gpuGuid. Refer to + * NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information. + * + * subdeviceInstance (OUTPUT) + * The subdevice instance of the GPU identified by gpuGuid. Refer to + * NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * + */ +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO (0x274U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID" */ + +/* maximum possible number of bytes of GID information */ +#define NV0000_GPU_MAX_GID_LENGTH (0x00000100U) + +#define NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID (0x74U) + +typedef struct NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS { + NvU8 gpuUuid[NV0000_GPU_MAX_GID_LENGTH]; + NvU32 flags; + NvU32 gpuId; + NvU32 deviceInstance; + NvU32 subdeviceInstance; +} NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS; + +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT 1:0 +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_ASCII (0x00000000U) +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_BINARY (0x00000002U) + +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE 2:2 +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA1 (0x00000000U) +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA256 (0x00000001U) + +/* + * NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID + * + * This command returns the GPU UUID for the provided GPU ID. + * Note that only GPUs that have been attached are visible to this call. + * Therefore queries on unattached GPUs will fail + * with NV_ERR_OBJECT_NOT_FOUND. + * + * gpuId (INPUT) + * The GPU ID whose parameters are to be returned. Refer to + * NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information. + * + * flags (INPUT) + * + * NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII + * This value is used to request the GPU UUID in ASCII format. + * NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY + * This value is used to request the GPU UUID in binary format. + * + * NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1 + * This value is used to request that the GPU UUID value + * be SHA1-based (32-hex-character). + * NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256 + * This value is used to request that the GPU UUID value + * be SHA256-based (64-hex-character). + * + * gpuUuid[NV0000_GPU_MAX_GID_LENGTH] (OUTPUT) + * The GPU UUID of the GPU identified by GPU ID. Refer to + * NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information. + * + * uuidStrLen (OUTPUT) + * The length of the UUID returned which is related to the format that + * was requested using flags. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_OPERATING_SYSTEM + */ +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID (0x275U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID (0x75U) + +typedef struct NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS { + NvU32 gpuId; + NvU32 flags; + NvU8 gpuUuid[NV0000_GPU_MAX_GID_LENGTH]; + NvU32 uuidStrLen; +} NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS; + +/* valid format values */ +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT 1:0 +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII (0x00000000U) +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY (0x00000002U) + +/*valid type values*/ +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE 2:2 +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1 (0x00000000U) +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256 (0x00000001U) + + + +/* + * NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE + * + * This command is used to enter or exit the so called "drain" state. + * When this state is enabled, the existing clients continue executing + * as usual, however no new client connections are allowed. + * This is done in order to "drain" the system of the running clients + * in preparation to selectively powering down the GPU. + * No GPU can enter a bleed state if that GPU is in an SLI group. + * In that case, NV_ERR_IN_USE is returned. + * Requires administrator privileges. + * + * It is expected, that the "drain" state will be eventually deprecated + * and replaced with another mechanism to quiesce a GPU (Bug 1718113). + * + * gpuId (INPUT) + * This parameter should specify a valid GPU ID value. If there + * is no GPU present with the specified ID, a status of + * NV_ERR_INVALID_ARGUMENT is returned. + * newState (INPUT) + * This input parameter is used to enter or exit the "drain" + * software state of the GPU specified by the gpuId parameter. + * Possible values are: + * NV0000_CTRL_GPU_DRAIN_STATE_ENABLED + * NV0000_CTRL_GPU_DRAIN_STATE_DISABLED + * flags (INPUT) + * NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE + * if set, upon reaching quiescence, a request will be made to + * the OS to "forget" the PCI device associated with the + * GPU specified by the gpuId parameter, in case such a request + * is supported by the OS. Otherwise, NV_ERR_NOT_SUPPORTED + * will be returned. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_IN_USE + */ + +#define NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE (0x278U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID" */ + +/* Possible values of newState */ +#define NV0000_CTRL_GPU_DRAIN_STATE_DISABLED (0x00000000U) +#define NV0000_CTRL_GPU_DRAIN_STATE_ENABLED (0x00000001U) + +/* Defined bits for the "flags" argument */ +#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE (0x00000001U) +#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE (0x00000002U) + +#define NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID (0x78U) + +typedef struct NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS { + NvU32 gpuId; + NvU32 newState; + NvU32 flags; +} NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE + * + * gpuId (INPUT) + * This parameter should specify a valid GPU ID value. If there + * is no GPU present with the specified ID, a status of + * NVOS_STATUS_ERROR_INVALID_ARGUMENT is returned. + * drainState (OUTPUT) + * This parameter returns a value indicating if the "drain" + * state is currently enabled or not for the specified GPU. See the + * description of NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE. + * Possible values are: + * NV0000_CTRL_GPU_DRAIN_STATE_ENABLED + * NV0000_CTRL_GPU_DRAIN_STATE_DISABLED + * flags (OUTPUT) + * NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE + * if set, upon reaching quiesence, the GPU device will be + * removed automatically from the kernel space, similar + * to what writing "1" to the sysfs "remove" node does. + * NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE + * after removing the GPU, also disable the parent bridge's + * PCIe link. This flag can only be set in conjunction with + * NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE, and then + * only when the GPU is already idle (not attached). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE (0x279U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID (0x79U) + +typedef struct NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS { + NvU32 gpuId; + NvU32 drainState; + NvU32 flags; +} NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_DISCOVER + * + * This request asks the OS to scan the PCI tree or a sub-tree for GPUs, + * that are not yet known to the OS, and to make them available for use. + * If all of domain:bus:slot.function are zeros, the entire tree is scanned, + * otherwise the parameters identify the bridge device, that roots the + * subtree to be scanned. + * Requires administrator privileges. + * + * domain (INPUT) + * PCI domain of the bridge + * bus (INPUT) + * PCI bus of the bridge + * slot (INPUT) + * PCI slot of the bridge + * function (INPUT) + * PCI function of the bridge + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_DEVICE + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_OPERATING_SYSTEM + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_GPU_DISCOVER (0x27aU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | 0x7A" */ + +typedef struct NV0000_CTRL_GPU_DISCOVER_PARAMS { + NvU32 domain; + NvU8 bus; + NvU8 slot; + NvU8 function; +} NV0000_CTRL_GPU_DISCOVER_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE + * + * This command is used to get the content of the MemOp (CUDA Memory Operation) + * enablement mask, which can be overridden by using the MemOpOverride RegKey. + * + * The enableMask member must be treated as a bitmask, where each bit controls + * the enablement of a feature. + * + * So far, the only feature which is defined controls to whole MemOp APIs. + * + * Possible status values returned are: + * NV_OK + * + */ +#define NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE (0x27bU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID (0x7BU) + +typedef struct NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS { + NvU32 enableMask; +} NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS; + +#define NV0000_CTRL_GPU_FLAGS_MEMOP_ENABLE (0x00000001U) + +/* + * NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT + * + * This privileged command is used to disable initialization for the NVLinks + * provided in the mask. + * + * The mask must be applied before the GPU is attached. DISABLE_NVLINK_INIT + * is an NOP for non-NVLink GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_DEVICE + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_INVALID_STATE + * NV_ERR_IN_USE + * + */ +#define NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT (0x281U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS { + NvU32 gpuId; + NvU32 mask; // This field will be deprecated in the future, please use links + NV_DECLARE_ALIGNED(NV0000_CTRL_NVLINK_LINK_MASK links, 8); + NvBool bSkipHwNvlinkDisable; +} NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS; + + +#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA 0x00000175U +#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN 6U +#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT 5U + +/* + * NV0000_CTRL_CMD_IDLE_CHANNELS + */ +#define NV0000_CTRL_CMD_IDLE_CHANNELS (0x283U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID (0x83U) + +typedef struct NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS { + NvHandle hDevice; + NvHandle hChannel; + NvV32 numChannels; + /* C form: NvP64 phClients NV_ALIGN_BYTES(8); */ + NV_DECLARE_ALIGNED(NvP64 phClients, 8); + /* C form: NvP64 phDevices NV_ALIGN_BYTES(8); */ + NV_DECLARE_ALIGNED(NvP64 phDevices, 8); + /* C form: NvP64 phChannels NV_ALIGN_BYTES(8); */ + NV_DECLARE_ALIGNED(NvP64 phChannels, 8); + NvV32 flags; + NvV32 timeout; +} NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS; + +#define NV0000_CTRL_GPU_IMAGE_TYPE_GSP (0x00000001U) +#define NV0000_CTRL_GPU_IMAGE_TYPE_GSP_LOG (0x00000002U) +#define NV0000_CTRL_GPU_IMAGE_TYPE_BINDATA_IMAGE (0x00000003U) +/* + * NV0000_CTRL_CMD_PUSH_UCODE_IMAGE + * + * This command is used to push the GSP ucode into RM. + * This function is used only on VMware + * + * Possible status values returned are: + * NV_OK The sent data is stored successfully + * NV_ERR_INVALID_ARGUMENT if the arguments are not proper + * NV_ERR_NO_MEMORY if memory allocation failed + * NV_ERR_NOT_SUPPORTED if function is invoked on non-GSP setup or any + * setup other than VMware host + * + */ +#define NV0000_CTRL_CMD_PUSH_UCODE_IMAGE (0x285) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS_MESSAGE_ID (0x85U) + +typedef struct NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS { + NvU8 image; + NV_DECLARE_ALIGNED(NvU64 totalSize, 8); + NV_DECLARE_ALIGNED(NvP64 pData, 8); +} NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_SET_NVLINK_BW_MODE + * + * This command is used to set NVLINK bandwidth for power saving + * + * The setting must be applied before the GPU is attached. + * NVLINK_BW_MODE is an NOP for non-NVLink GPUs. + * + * [in] mode + * Possible Legacy values that can be set in bits 2:0: + * NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_FULL + * NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_OFF + * NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_MIN + * NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_HALF + * NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_3QUARTER + * bits 3:15 can be used to specify link count + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_DEVICE + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_INVALID_STATE + * NV_ERR_IN_USE + */ + +#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SETTING_LEGACY 2:0 +#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SETTING_LINK_COUNT 7:3 + +#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_FULL (0x00U) +#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_OFF (0x01U) +#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_MIN (0x02U) +#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_HALF (0x03U) +#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_3QUARTER (0x04U) +#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_LINK_COUNT (0x05U) + +#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_UNSET (0x00U) +#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_PER_NODE (0x01U) +#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_PER_GPU (0x02U) + + +#define NV0000_CTRL_CMD_GPU_SET_NVLINK_BW_MODE (0x286U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID (0x86U) + +typedef struct NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS { + NvU16 mode; +} NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_GET_NVLINK_BW_MODE + * + * This command is used to get NVLINK bandwidth for power saving + * + * NVLINK_BW_MODE is an NOP for non-NVLink GPUs. + * + * [out] mode + * BW mode currently set for the GPUs on the system. + * Possible values are: + * NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_FULL + * NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_OFF + * NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_MIN + * NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_HALF + * NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_3QUARTER + * [out] bwModeScope + * Scope of the bw mode setting on the system. + * Possible values are: + * NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_UNSET + * NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_PER_NODE + * NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_PER_GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_DEVICE + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_INVALID_STATE + * NV_ERR_IN_USE + */ + +#define NV0000_CTRL_CMD_GPU_GET_NVLINK_BW_MODE (0x287U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID (0x87U) + +typedef struct NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS { + NvU8 mode; + NvU8 bwModeScope; +} NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS; + +/* + * NV0000_CTRL_GPU_ACTIVE_DEVICE + * + * This structure describes a single MIG or plain device in the system + * available for use. + * + * gpuId + * ID of an attached GPU. + * gpuInstanceId + * MIG gpu instance id of an instance existing on this GPU. + * NV0000_CTRL_GPU_INVALID_ID if the GPU is not in MIG mode. + * computeInstanceId + * MIG compute instance id of an instance existing on this GPU. + * NV0000_CTRL_GPU_INVALID_ID if the GPU is not in MIG mode. + * + */ +typedef struct NV0000_CTRL_GPU_ACTIVE_DEVICE { + NvU32 gpuId; + NvU32 gpuInstanceId; + NvU32 computeInstanceId; +} NV0000_CTRL_GPU_ACTIVE_DEVICE; + +/* + * NV0000_CTRL_CMD_GPU_GET_ACTIVE_DEVICE_IDS + * + * This command returns a list of valid GPUs treating uniformly MIG devices + * and GPUs not in MIG mode. + * + * [out] devices + * List of devices aviable for use. + * [out] numDevices + * Number of valid entries in gpus + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0000_CTRL_CMD_GPU_GET_ACTIVE_DEVICE_IDS (0x288U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_MAX_ACTIVE_DEVICES 256U + +#define NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS_MESSAGE_ID (0x88U) + +typedef struct NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS { + NvU32 numDevices; + NV0000_CTRL_GPU_ACTIVE_DEVICE devices[NV0000_CTRL_GPU_MAX_ACTIVE_DEVICES]; +} NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID + * + * This command attaches the GPU with the given gpuId, similar to + * NV0000_CTRL_CMD_GPU_ATTACH_IDS. However, this command instructs the RM + * to perform the attach in the background. + * + * After calling this command, clients are expected to call + * NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID before performing any operation that + * depends on the GPU being attached. + * + * If the gpuId fails to attach, either this command or the subsequent + * NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID command may fail. + * + * If clients from multiple processes use this command or the + * NV0000_CTRL_CMD_GPU_ATTACH_IDS command to attach a gpuId, the RM ensures + * that the gpuId won't be detached until all processes have issued a call to + * NV0000_CTRL_CMD_GPU_DETACH_IDS to detach the gpuId (or have terminated). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OPERATING_SYSTEM + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID (0x289U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS_MESSAGE_ID (0x89U) + +typedef struct NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS { + NvU32 gpuId; +} NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID + * + * This command waits for and returns the status of a background attach + * operation started by NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID. + * + * Clients are expected to call this command after calling + * NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID before performing any operation that + * depends on the GPU being attached. + * + * If the gpuId fails to attach, either this command or the previous + * NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID command may fail. + * + * Calling this command for a gpuId that is already attached (for example, + * after a successful NV0000_CTRL_CMD_GPU_ATTACH_IDS) is a no-op. + * + * Calling this command for a gpuId that is neither attached nor has a + * background attach operation will result in NV_ERR_INVALID_ARGUMENT. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OPERATING_SYSTEM + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_IRQ_EDGE_TRIGGERED + * NV_ERR_IRQ_NOT_FIRING + */ +#define NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID (0x290U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS_MESSAGE_ID (0x90U) + +typedef struct NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS { + NvU32 gpuId; +} NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_PCI_READ_WRITE + * + * This control is supported only on MODS. + * + */ + +#define NV0000_CTRL_CMD_GPU_PCI_READ_WRITE_DATA_SIZE_08 0 +#define NV0000_CTRL_CMD_GPU_PCI_READ_WRITE_DATA_SIZE_16 1 +#define NV0000_CTRL_CMD_GPU_PCI_READ_WRITE_DATA_SIZE_32 2 + +#define NV0000_CTRL_CMD_GPU_PCI_READ_WRITE (0x291U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_PCI_READ_WRITE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_PCI_READ_WRITE_PARAMS_MESSAGE_ID (0x91U) + +typedef struct NV0000_CTRL_GPU_PCI_READ_WRITE_PARAMS { + NvBool bWrite; + NvU16 pciDomain; + NvU8 pciBus; + NvU8 pciDevice; + NvU8 pciFunction; + NvU8 pciOffset; + NvU32 dataSize; + NvU32 data; +} NV0000_CTRL_GPU_PCI_READ_WRITE_PARAMS; + +/* _ctrl0000gpu_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000gpuacct.h b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000gpuacct.h new file mode 100644 index 0000000..4e01862 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000gpuacct.h @@ -0,0 +1,319 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000gpuacct.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +/* + * NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE + * + * This command is used to enable or disable the per process GPU accounting. + * This is part of GPU's software state and will persist if persistent + * software state is enabled. Refer to the description of + * NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE for more information. + * + * gpuId + * This parameter should specify a valid GPU ID value. Refer to the + * description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more + * information. If there is no GPU present with the specified ID, + * a status of NV_ERR_INVALID_ARGUMENT is returned. + * pid + * This input parameter specifies the process id of the process for which + * the accounting state needs to be set. + * In case of VGX host, this parameter specifies VGPU plugin(VM) pid. This + * parameter is set only when this RM control is called from VGPU plugin, + * otherwise it is zero meaning set/reset the accounting state for the + * specified GPU. + * newState + * This input parameter is used to enable or disable the GPU accounting. + * Possible values are: + * NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED + * NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE (0xb01) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID" */ + +/* Possible values of persistentSwState */ +#define NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED (0x00000000) +#define NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED (0x00000001) + +#define NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS { + NvU32 gpuId; + NvU32 pid; + NvU32 newState; +} NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS; + +/* + * NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_STATE + * + * This command is used to get the current state of GPU accounting. + * + * gpuId + * This parameter should specify a valid GPU ID value. Refer to the + * description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more + * information. If there is no GPU present with the specified ID, + * a status of NV_ERR_INVALID_ARGUMENT is returned. + * pid + * This input parameter specifies the process id of the process of which the + * accounting state needs to be queried. + * In case of VGX host, this parameter specifies VGPU plugin(VM) pid. This + * parameter is set only when this RM control is called from VGPU plugin, + * otherwise it is zero meaning the accounting state needs to be queried for + * the specified GPU. + * state + * This parameter returns a value indicating if per process GPU accounting + * is currently enabled or not for the specified GPU. See the + * description of NV0000_CTRL_CMD_GPU_SET_ACCOUNTING_STATE. + * Possible values are: + * NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED + * NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_STATE (0xb02) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS { + NvU32 gpuId; + NvU32 pid; + NvU32 state; +} NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS; + +/* + * NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS + * + * This command returns GPU accounting data for the process. + * + * gpuId + * This parameter should specify a valid GPU ID value. Refer to the + * description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more + * information. If there is no GPU present with the specified ID, + * a status of NV_ERR_INVALID_ARGUMENT is returned. + * pid + * This parameter specifies the PID of the process for which information is + * to be queried. + * In case of VGX host, this parameter specifies VGPU plugin(VM) pid inside + * which the subPid is running. This parameter is set to VGPU plugin pid + * when this RM control is called from VGPU plugin. + * subPid + * In case of VGX host, this parameter specifies the PID of the process for + * which information is to be queried. In other cases, it is zero. + * gpuUtil + * This parameter returns the average GR utilization during the process's + * lifetime. + * fbUtil + * This parameter returns the average FB bandwidth utilization during the + * process's lifetime. + * maxFbUsage + * This parameter returns the maximum FB allocated (in bytes) by the process. + * startTime + * This parameter returns the time stamp value in micro seconds at the time + * process started utilizing GPU. + * stopTime + * This parameter returns the time stamp value in micro seconds at the time + * process stopped utilizing GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_GPUACCT_GET_PROC_ACCOUNTING_INFO (0xb03) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS { + NvU32 gpuId; + NvU32 pid; + NvU32 subPid; + NvU32 gpuUtil; + NvU32 fbUtil; + NV_DECLARE_ALIGNED(NvU64 maxFbUsage, 8); + NV_DECLARE_ALIGNED(NvU64 startTime, 8); + NV_DECLARE_ALIGNED(NvU64 endTime, 8); +} NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS; + +/* + * NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_PIDS + * + * This command is used to get the PIDS of processes with accounting + * information in the driver. + * + * gpuId + * This parameter should specify a valid GPU ID value. Refer to the + * description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more + * information. If there is no GPU present with the specified ID, + * a status of NV_ERR_INVALID_ARGUMENT is returned. + * pid + * This input parameter specifies the process id of the process of which the + * information needs to be queried. + * In case of VGX host, this parameter specifies VGPU plugin(VM) pid. This + * parameter is set only when this RM control is called from VGPU plugin, + * otherwise it is zero meaning get the pid list of the all the processes + * running on the specified GPU. + * pidTbl + * This parameter returns the table of all PIDs for which driver has + * accounting info. + * pidCount + * This parameter returns the number of entries in the PID table. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_PIDS (0xb04) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_MESSAGE_ID" */ + +/* max size of pidTable */ +#define NV0000_GPUACCT_PID_MAX_COUNT 4000 + +#define NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS { + NvU32 gpuId; + NvU32 pid; + NvU32 pidTbl[NV0000_GPUACCT_PID_MAX_COUNT]; + NvU32 pidCount; +} NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS; + +/* + * NV0000_CTRL_CMD_GPUACCT_CLEAR_ACCOUNTING_DATA + * + * This command is used to clear previously collected GPU accounting data. This + * will have no affect on data for the running processes, accounting data for + * these processes will not be cleared and will still be logged for these + * processes. In order to clear ALL accounting data, accounting needs to be + * disabled using NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE before executing + * this command. + * + * gpuId + * This parameter should specify a valid GPU ID value. Refer to the + * description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more + * information. If there is no GPU present with the specified ID, + * a status of NV_ERR_INVALID_ARGUMENT is returned. + * pid + * This input parameter specifies the process id of the process for which + * the accounting data needs to be cleared. + * In case of VGX host, this parameter specifies VGPU plugin(VM) pid for + * which the accounting data needs to be cleared. This parameter is set only + * when this RM control is called from VGPU plugin, otherwise it is zero + * meaning clear the accounting data of processes running on baremetal + * system. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ + +#define NV0000_CTRL_CMD_GPUACCT_CLEAR_ACCOUNTING_DATA (0xb05) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS { + NvU32 gpuId; + NvU32 pid; +} NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS; + +/* + * NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_V2_PARAMS + * + * This command returns GPU accounting data (V2) for the process. + * + * gpuId + * This parameter should specify a valid GPU ID value. Refer to the + * description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more + * information. If there is no GPU present with the specified ID, + * a status of NV_ERR_INVALID_ARGUMENT is returned. + * pid + * This parameter specifies the PID of the process for which information is + * to be queried. + * In case of VGX host, this parameter specifies VGPU plugin(VM) pid inside + * which the subPid is running. This parameter is set to VGPU plugin pid + * when this RM control is called from VGPU plugin. + * subPid + * In case of VGX host, this parameter specifies the PID of the process for + * which information is to be queried. In other cases, it is zero. + * gpuUtil + * This parameter returns the average GR utilization during the process's + * lifetime. + * fbUtil + * This parameter returns the average FB bandwidth utilization during the + * process's lifetime. + * sampleCount + * This parameter returns the samples count during the process's lifetime. + * maxFbUsage + * This parameter returns the maximum FB allocated (in bytes) by the process. + * startTime + * This parameter returns the time stamp value in micro seconds at the time + * process started utilizing GPU. + * stopTime + * This parameter returns the time stamp value in micro seconds at the time + * process stopped utilizing GPU. + * sumGpuUtil + * This parameter returns the sum of GR utilization during the process's + * lifetime. + * sumFbUtil + * This parameter returns the sum of FB bandwidth utilization during the + * process's lifetime. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_GPUACCT_GET_PROC_ACCOUNTING_INFO_V2 (0xb06) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_V2_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_V2_PARAMS { + NvU32 gpuId; + NvU32 pid; + NvU32 subPid; + NvU32 gpuUtil; + NvU32 fbUtil; + NvU32 sampleCount; + NV_DECLARE_ALIGNED(NvU64 maxFbUsage, 8); + NV_DECLARE_ALIGNED(NvU64 startTime, 8); + NV_DECLARE_ALIGNED(NvU64 endTime, 8); + NV_DECLARE_ALIGNED(NvU64 sumGpuUtil, 8); + NV_DECLARE_ALIGNED(NvU64 sumFbUtil, 8); +} NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_V2_PARAMS; + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000gsync.h b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000gsync.h new file mode 100644 index 0000000..fae2cf9 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000gsync.h @@ -0,0 +1,101 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000gsync.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +#include "class/cl30f1.h" +/* NV01_ROOT (client) system controller control commands and parameters */ + +/* + * NV0000_CTRL_CMD_GSYNC_GET_ATTACHED_IDS + * + * This command returns a table of attached gsyncId values. + * The table is NV0000_CTRL_GSYNC_MAX_ATTACHED_GSYNCS entries in size. + * + * gsyncIds[] + * This parameter returns the table of attached gsync IDs. + * The gsync ID is an opaque platform-dependent value that + * can be used with the NV0000_CTRL_CMD_GSYNC_GET_ID_INFO command to + * retrieve additional information about the gsync device. + * The valid entries in gsyncIds[] are contiguous, with a value + * of NV0000_CTRL_GSYNC_INVALID_ID indicating the invalid entries. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV0000_CTRL_CMD_GSYNC_GET_ATTACHED_IDS (0x301) /* finn: Evaluated from "(FINN_NV01_ROOT_GSYNC_INTERFACE_ID << 8) | NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS { + NvU32 gsyncIds[NV30F1_MAX_GSYNCS]; +} NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS; + +/* this value marks entries in gsyncIds[] as invalid */ +#define NV0000_CTRL_GSYNC_INVALID_ID (0xffffffff) + +/* + * NV0000_CTRL_CMD_GSYNC_GET_ID_INFO + * + * This command returns gsync instance information for the + * specified gsync device. + * + * gsyncId + * This parameter should specify a valid gsync ID value. + * If there is no gsync present with the specified ID, a + * status of NV_ERR_INVALID_ARGUMENT is returned. + * gsyncFlags + * This parameter returns the current state of the gsync device. + * gsyncInstance + * This parameter returns the instance number associated with the + * specified gsync. This value can be used to instantiate + * a reference to the gsync using one of the NV30_GSYNC + * classes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_GSYNC_GET_ID_INFO (0x302) /* finn: Evaluated from "(FINN_NV01_ROOT_GSYNC_INTERFACE_ID << 8) | NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS { + NvU32 gsyncId; + NvU32 gsyncFlags; + NvU32 gsyncInstance; +} NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS; + +/* _ctrl0000gsync_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000nvd.h b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000nvd.h new file mode 100644 index 0000000..92a2ba5 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000nvd.h @@ -0,0 +1,637 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000nvd.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +/* NV01_ROOT (client) nvd control commands and parameters */ + +/* + * NV0080_CTRL_NVD_DUMP_COMPONENT + * + * The following dump components are used to describe legal ranges in + * commands below: + * + * NV0080_CTRL_CMD_NVD_DUMP_COMPONENT_SYS + * This is the system dump component. + * NV0080_CTRL_CMD_NVD_DUMP_COMPONENT_NVLOG + * This is the nvlog dump component. + * NV0080_CTRL_CMD_NVD_DUMP_COMPONENT_RESERVED + * This component is reserved. + * + * See nvdump.h for more information on dump component values. + */ +#define NV0000_CTRL_NVD_DUMP_COMPONENT_SYS (0x400) +#define NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG (0x800) +#define NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED (0xB00) + +/* + * NV0000_CTRL_CMD_NVD_GET_DUMP_SIZE + * + * This command gets the expected dump size of a particular system + * dump component. Note that events that occur between this command + * and a later NV0000_CTRL_CMD_NVD_GET_DUMP command could alter the size of + * the buffer required. + * + * component + * This parameter specifies the system dump component for which the + * dump size is desired. Legal values for this parameter must + * be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_SYS and + * less than NV0000_CTRL_NVD_GET_DUMP_COMPONENT_NVLOG. + * size + * This parameter returns the expected size in bytes. The maximum + * value of this call is NV0000_CTRL_NVD_MAX_DUMP_SIZE. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT if components are invalid. + */ + +#define NV0000_CTRL_CMD_NVD_GET_DUMP_SIZE (0x601) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS { + NvU32 component; + NvU32 size; +} NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS; + +/* Max size that a GET_DUMP_SIZE_PARAMS call can return */ +#define NV0000_CTRL_NVD_MAX_DUMP_SIZE (1000000) + +/* + * NV0000_CTRL_CMD_NVD_GET_DUMP + * + * This command gets a dump of a particular system dump component. If triggers + * is non-zero, the command waits for the trigger to occur before it returns. + * + * pBuffer + * This parameter points to the buffer for the data. + * component + * This parameter specifies the system dump component for which the + * dump is to be retrieved. Legal values for this parameter must + * be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_SYS and + * less than NV0000_CTRL_NVD_GET_DUMP_COMPONENT_NVLOG. + * size + * On entry, this parameter specifies the maximum length for + * the returned data. On exit, it specifies the number of bytes + * returned. + * + * Possible status values returned are: + * NV_OK + * NVOS_ERROR_INVALID_ARGUMENT if components are invalid. + * NVOS_ERROR_INVALID_ADDRESS if pBuffer is invalid + * NVOS_ERROR_INVALID_???? if the buffer was too small + */ +#define NV0000_CTRL_CMD_NVD_GET_DUMP (0x602) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_NVD_GET_DUMP_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pBuffer, 8); + NvU32 component; + NvU32 size; +} NV0000_CTRL_NVD_GET_DUMP_PARAMS; + +/* + * NV0000_CTRL_CMD_NVD_GET_TIMESTAMP + * + * This command returns the current value of the timestamp used + * by the RM in NvDebug dumps. It is provided to keep the RM and NvDebug + * clients on the same time base. + * + * cpuClkId + * See also NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO + * This parameter specifies the source of the CPU clock. Legal values for + * this parameter include: + * NV0000_NVD_CPU_TIME_CLK_ID_DEFAULT and NV0000_NVD_CPU_TIME_CLK_ID_OSTIME + * This clock id will provide real time in microseconds since 00:00:00 UTC on January 1, 1970. + * It is calculated as follows: + * (seconds * 1000000) + uSeconds + * NV0000_NVD_CPU_TIME_CLK_ID_PLATFORM_API + * This clock id will provide time stamp that is constant-rate, high + * precision using platform API that is also available in the user mode. + * NV0000_NVD_CPU_TIME_CLK_ID_TSC + * This clock id will provide time stamp using CPU's time stamp counter. + * + * timestamp + * Retrieved timestamp + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_NVD_CPU_TIME_CLK_ID_DEFAULT (0x00000000) +#define NV0000_NVD_CPU_TIME_CLK_ID_OSTIME (0x00000001) +#define NV0000_NVD_CPU_TIME_CLK_ID_TSC (0x00000002) +#define NV0000_NVD_CPU_TIME_CLK_ID_PLATFORM_API (0x00000003) + +#define NV0000_CTRL_CMD_NVD_GET_TIMESTAMP (0x603) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS { + NV_DECLARE_ALIGNED(NvU64 timestamp, 8); + NvU8 cpuClkId; +} NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS; + +/* + * NV0000_CTRL_CMD_NVD_GET_NVLOG_INFO + * + * This command gets the current state of the NvLog buffer system. + * + * component (in) + * This parameter specifies the system dump component for which the + * NvLog info is desired. Legal values for this parameter must + * be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG and + * less than NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED. + * version (out) + * This parameter returns the version of the Nvlog subsystem. + * runtimeSizes (out) + * This parameter returns the array of sizes for all supported printf + * specifiers. This information is necessary to know how many bytes + * to decode when given a certain specifier (such as %d). + * The following describes the contents of each array entry: + * NV0000_CTRL_NVD_RUNTIME_SIZE_UNUSED + * This array entry has special meaning and is unused in the + * runtimeSizes array. + * NV0000_CTRL_NVD_RUNTIME_SIZE_INT + * This array entry returns the size of integer types for use in + * interpreting the %d, %u, %x, %X, %i, %o specifiers. + * NV0000_CTRL_NVD_RUNTIME_SIZE_LONG_LONG + * This array entry returns the size of long long integer types for + * using in interpreting the %lld, %llu, %llx, %llX, %lli, %llo + * specifiers. + * NV0000_CTRL_NVD_RUNTIME_SIZE_STRING + * This array entry returns zero as strings are not allowed. + * NV0000_CTRL_NVD_RUNTIME_SIZE_PTR + * This array entry returns the size of the pointer type for use + * in interpreting the %p specifier. + * NV0000_CTRL_NVD_RUNTIME_SIZE_CHAR + * This array entry returns the size of the char type for use in + * intpreting the %c specifier. + * NV0000_CTRL_NVD_RUNTIME_SIZE_FLOAT + * This array entry returns the size of the float types for use in + * in interpreting the %f, %g, %e, %F, %G, %E specifiers. + * All remaining entries are reserved and return 0. + * printFlags (out) + * This parameter returns the flags of the NvLog system. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_BUFFER_FLAGS + * See NV0000_CTRL_CMD_NVD_GET_NVLOG_BUF_INFO for more details. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_BUFFER_SIZE + * This field returns the buffer size in KBytes. A value of zero + * is returned when logging is disabled. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP + * This field returns the format of the timestamp. Legal values + * for this parameter include: + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP_NONE + * This value indicates no timestamp. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP_32BIT + * This value indicates a 32-bit timestamp. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP_64BIT + * This value indicates a 64-bit timestamp. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP_32BIT_DIFF + * This value indicates a 32-bit differential timestamp. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_RESERVED + * This field is reserved. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_RUNTIME_LEVEL + * This field returns the lowest debug level for which logging + * is enabled by default. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_INIT + * This field indicates if logging for the specified component has + * been initialized. Legal values for this parameter include: + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_INIT_NO + * This value indicates NvLog is uninitialized. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_INIT_YES + * This value indicates NvLog has been initialized. + * signature (out) + * This parameter is the signature of the database + * required to decode these logs, autogenerated at buildtime. + * bufferTags (out) + * This parameter identifies the buffer tag used during allocation + * or a value of '0' if buffer is unallocated for each possible + * buffer. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT if components are invalid. + */ +#define NV0000_CTRL_CMD_NVD_GET_NVLOG_INFO (0x604) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS_MESSAGE_ID" */ + +/* maximum size of the runtimeSizes array */ +#define NV0000_CTRL_NVD_MAX_RUNTIME_SIZES (16) + +/* size of signature parameter */ +#define NV0000_CTRL_NVD_SIGNATURE_SIZE (4) + +/* Maximum number of buffers */ +#define NV0000_CTRL_NVD_MAX_BUFFERS (3840) + +#define NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS { + NvU32 component; + NvU32 version; + NvU8 runtimeSizes[NV0000_CTRL_NVD_MAX_RUNTIME_SIZES]; + NvU32 printFlags; + NvU32 signature[NV0000_CTRL_NVD_SIGNATURE_SIZE]; + NvU32 bufferTags[NV0000_CTRL_NVD_MAX_BUFFERS]; +} NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS; + +/* runtimeSize array indices */ +#define NV0000_CTRL_NVD_RUNTIME_SIZE_UNUSED (0) +#define NV0000_CTRL_NVD_RUNTIME_SIZE_INT (1) +#define NV0000_CTRL_NVD_RUNTIME_SIZE_LONG_LONG (2) +#define NV0000_CTRL_NVD_RUNTIME_SIZE_STRING (3) +#define NV0000_CTRL_NVD_RUNTIME_SIZE_PTR (4) +#define NV0000_CTRL_NVD_RUNTIME_SIZE_CHAR (5) +#define NV0000_CTRL_NVD_RUNTIME_SIZE_FLOAT (6) + +/* printFlags fields and values */ +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_INFO 7:0 +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE 23:8 +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DISABLE (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DEFAULT (0x00000004) +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_RUNTIME_LEVEL 28:25 +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP 30:29 +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_NONE (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32 (0x00000001) +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_64 (0x00000002) +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32_DIFF (0x00000003) +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED 31:31 +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_NO (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_YES (0x00000001) + +/* + * NV0000_CTRL_CMD_NVD_GET_NVLOG_BUFFER_INFO + * + * This command gets the current state of a specific buffer in the NvLog + * buffer system. + * + * component (in) + * This parameter specifies the system dump component for which the + * NvLog info is desired. Legal values for this parameter must + * be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG and + * less than NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED. + * buffer (in/out) + * This parameter specifies the buffer number from which to retrieve the + * buffer information. Valid values are 0 to (NV0000_CTRL_NVD_MAX_BUFFERS - 1). + * If the buffer is specified using the 'tag' parameter, the buffer + * number is returned through this one. + * tag (in/out) + * If this parameter is non-zero, it will be used to specify the buffer, + * instead of 'buffer' parameter. It returns the tag of the specified buffer + * size (out) + * This parameter returns the size of the specified buffer. + * flags (in/out) + * On input, this parameter sets the following behavior: + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE + * This flag controls if the nvlog system should pause output + * to this buffer. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_YES + * The buffer should be paused until another command + * unpauses this buffer. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_NO + * The buffer should not be paused. + * On output, this parameter returns the flags of a specified buffer: + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED + * This flag indicates if logging to the specified buffer is + * disabled or not. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE + * This flag indicates the buffer logging type: + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_RING + * This type value indicates logging to the buffer wraps. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_NOWRAP + * This type value indicates logging to the buffer does not wrap. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE + * This flag indicates if the buffer size is expandable. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_NO + * The buffer is not expandable. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_YES + * The buffer is expandable. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NON_PAGED + * This flag indicates if the buffer occupies non-paged or pageable + * memory. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NON_PAGED_NO + * The buffer is in pageable memory. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NON_PAGES_YES + * The buffer is in non-paged memory. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING + * This flag indicates the locking mode for the specified buffer. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_NONE + * This locking value indicates that no locking is performed. This + * locking mode is typically used for inherently single-threaded + * buffers. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_STATE + * This locking value indicates that the buffer is locked only + * during state changes and that memory copying is unlocked. This + * mode should not be used tiny buffers that overflow every write + * or two. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_FULL + * This locking value indicates the buffer is locked for the full + * duration of the write. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA + * This flag indicates if the buffer is stored in OCA dumps. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_NO + * The buffer is not included in OCA dumps. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_YES + * The buffer is included in OCA dumps. + * pos (out) + * This parameter is the current position of the tracker/cursor in the + * buffer. + * overflow (out) + * This parameter is the number of times the buffer has overflowed. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT if components are invalid. + */ + +#define NV0000_CTRL_CMD_NVD_GET_NVLOG_BUFFER_INFO (0x605) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS { + NvU32 component; + NvU32 buffer; + NvU32 tag; + NvU32 size; + NvU32 flags; + NvU32 pos; + NvU32 overflow; +} NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS; + +/* flags fields and values */ +/* input */ +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE 0:0 +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_NO (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_YES (0x00000001) + +/* output */ +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED 0:0 +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_NO (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_YES (0x00000001) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE 1:1 +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_RING (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_NOWRAP (0x00000001) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE 2:2 +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_NO (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_YES (0x00000001) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED 3:3 +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_NO (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_YES (0x00000001) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING 5:4 +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_NONE (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_STATE (0x00000001) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_FULL (0x00000002) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA 6:6 +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_NO (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_YES (0x00000001) + +/* + * NV0000_CTRL_CMD_NVD_GET_NVLOG + * + * This command retrieves the specified dump block from the specified + * NvLog buffer. To retrieve the entire buffer, the caller should start + * with blockNum set to 0 and continue issuing calls with an incremented + * blockNum until the returned size value is less than + * NV0000_CTRL_NVD_NVLOG_MAX_BLOCK_SIZE. + * + * component (in) + * This parameter specifies the system dump component for which the NvLog + * dump operation is to be directed. Legal values for this parameter + * must be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG + * and less than NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED. + * buffer (in) + * This parameter specifies the NvLog buffer to dump. + * blockNum (in) + * This parameter specifies the block number for which data is to be + * dumped. + * size (in/out) + * On entry, this parameter specifies the maximum length in bytes for + * the returned data (should be set to NV0000_CTRL_NVLOG_MAX_BLOCK_SIZE). + * On exit, it specifies the number of bytes returned. + * data (out) + * This parameter returns the data for the specified block. The size + * patameter values indicates the number of valid bytes returned. + * + * Possible status values returned are: + * NV_OK + * NVOS_ERROR_INVALID_ARGUMENT if components are invalid. + */ +#define NV0000_CTRL_CMD_NVD_GET_NVLOG (0x606) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_NVLOG_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_NVLOG_MAX_BLOCK_SIZE (4000) + +#define NV0000_CTRL_NVD_GET_NVLOG_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV0000_CTRL_NVD_GET_NVLOG_PARAMS { + NvU32 component; + NvU32 buffer; + NvU32 blockNum; + NvU32 size; + NvU8 data[NV0000_CTRL_NVLOG_MAX_BLOCK_SIZE]; +} NV0000_CTRL_NVD_GET_NVLOG_PARAMS; + +/* + * NV0000_CTRL_CMD_NVD_GET_RCERR_RPT + * + * This command returns block of registers that were recorded at the time + * of an RC error for the current process. + * + * reqIdx: + * [IN] the index of the report being requested. + * index rolls over to 0. + * if the requested index is not in the circular buffer, then no data is + * transferred & either NV_ERR_INVALID_INDEX (indicating the specified + * index is not in the table) is returned. + * + * rptIdx: + * [OUT] the index of the report being returned. + * if the requested index is not in the circular buffer, then the value is + * undefined, no data istransferred & NV_ERR_INVALID_INDEX is returned. + * if the the specified index is present, but does not meet the requested + * criteria (refer to the owner & processId fields). the rptIdx will be + * set to a value that does not match the reqIdx, and no data will be + * transferred. NV_ERR_INSUFFICIENT_PERMISSIONS is still returned. + * + * gpuTag: + * [OUT] id of the GPU whose data was collected. + * + * rptTimeInNs: + * [OUT] the timestamp for when the report was created. + * + * startIdx: + * [OUT] the index of the oldest start record for the first report that + * matches the specified criteria (refer to the owner & processId + * fields). If no records match the specified criteria, this value is + * undefined, the failure code NV_ERR_MISSING_TABLE_ENTRY will + * be returned, and no data will be transferred. + * + * endIdx: + * [OUT] the index of the newest end record for the most recent report that + * matches the specified criteria (refer to the owner & processId + * fields). If no records match the specified criteria, this value is + * undefined, the failure code NV_ERR_MISSING_TABLE_ENTRY will + * be returned, and no data will be transferred. + * + * rptType: + * [OUT] indicator of what data is in the report. + * + * flags + * [OUT] a set odf flags indicating attributes of the record + * NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_FIRST -- indicates this is the first record of a report. + * NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_LAST -- indicates this is the last record of the report. + * NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_RANGE_VALID -- indicates this is the response contains a valid +* index range. + * Note, this may be set when an error is returned indicating a valid range was found, but event of + * the requested index was not. + * NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_DATA_VALID -- indicates this is the response contains valid data. + * + * rptCount: + * [OUT] number of entries returned in report. + * + * owner: + * [IN] Entries are only returned if they have the same owner as the specified owner or the specified + * owner Id is NV0000_CTRL_CMD_NVD_RPT_ANY_OWNER_ID. + * if the requested index is not owned by the specified owner, the rptIdx + * will be set to a value that does not match the reqIdx, and no data will + * be transferred. NV_ERR_INSUFFICIENT_PERMISSIONS is returned. + * + * processId: + * [IN] Deprecated + * report: + * [OUT] array of rptCount enum/value pair entries containing the data from the report. + * entries beyond rptCount are undefined. + * + * + * Possible status values returned are: + * NV_OK -- we found & transferred the requested record. + * NV_ERR_MISSING_TABLE_ENTRY -- we don't find any records that meet the criteria. + * NV_ERR_INVALID_INDEX -- the requested index was not found in the buffer. + * NV_ERR_INSUFFICIENT_PERMISSIONS -- the requested record was found, but it did not meet the criteria. + * NV_ERR_BUSY_RETRY -- We could not access the circular buffer. + * + */ + +#define NV0000_CTRL_CMD_NVD_GET_RCERR_RPT (0x607) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_MAX_ENTRIES 200 + +// report types +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_TEST 0 +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GRSTATUS 1 +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GPCSTATUS 2 +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_MMU_FAULT_STATUS 3 +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_RC_ERROR 4 + +// pseudo register enums attribute content +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_EMPTY 0x00000000 +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_OVERFLOWED 0x00000001 // number of missed entries. +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_MAX_PSEDO_REG 0x0000000f + + + +// Flags Definitions +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_FIRST 0x00000001 // indicates this is the first record of a report. +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_LAST 0x00000002 // indicates this is the last record of the report. +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_RANGE_VALID 0x00000004 // indicates this is the response contains a valid range +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_DATA_VALID 0x00000008 // indicates this is the response contains valid data + + +// Attribute Definitions +#define TPC_REG_ATTR(gpcId, tpcId) ((gpcId << 8) | (tpcId)) +#define ROP_REG_ATTR(gpcId, ropId) ((gpcId << 8) | (ropId)) +#define SM_REG_ATTR(gpcId, tpcId, smId) ((((gpcId) << 16) | ((tpcId) << 8)) | (smId)) + +// Process Id Pseudo values +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_PROCESS_ID 0x00000000 // get report for any process ID + +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_OWNER_ID 0xFFFFFFFF // get report for any owner ID + + +typedef struct NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY { + NvU32 tag; + NvU32 value; + NvU32 attribute; +} NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY; + +#define NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS { + NvU16 reqIdx; + NvU16 rptIdx; + NvU32 GPUTag; + NvU32 rptTime; // time in seconds since 1/1/1970 + NvU16 startIdx; + NvU16 endIdx; + NvU16 rptType; + NvU32 flags; + NvU16 rptCount; + NvU32 owner; // indicating whose reports to get + NvU32 processId; // deprecated field + + NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY report[NV0000_CTRL_CMD_NVD_RCERR_RPT_MAX_ENTRIES]; +} NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS; + +/* + * NV0000_CTRL_CMD_NVD_GET_DPC_ISR_TS + * + * This command returns the time stamp information that are collected from + * the execution of various DPCs/ISRs. This time stamp information is for + * debugging purposes only and would help with analyzing regressions and + * latencies for DPC/ISR execution times. + * + * tsBufferSize + * This field specifies the size of the buffer that the caller allocates. + * tsBuffer + * THis field specifies a pointer in the callers address space to the + * buffer into which the timestamp info on DPC/ISR is to be returned. + * This buffer must at least be as big as tsBufferSize. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV0000_CTRL_CMD_NVD_GET_DPC_ISR_TS (0x608) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS { + NvU32 tsBufferSize; + NV_DECLARE_ALIGNED(NvP64 pTSBuffer, 8); +} NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS; + +/* _ctrl0000nvd_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000proc.h b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000proc.h new file mode 100644 index 0000000..70ff0eb --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000proc.h @@ -0,0 +1,98 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000proc.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" +#include "nvlimits.h" + +/* + * NV0000_CTRL_CMD_SET_SUB_PROCESS_ID + * + * Save the sub process ID and sub process name in client database + * subProcID + * Sub process ID + * subProcessName + * Sub process name + * + * In vGPU environment, sub process means the guest user/kernel process running + * within a single VM. It also refers to any sub process (or sub-sub process) + * within a parent process. + * + * Please refer to the wiki for more details about sub process concept: Resource_Server + * + * Possible return values are: + * NV_OK + */ +#define NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS { + NvU32 subProcessID; + char subProcessName[NV_PROC_NAME_MAX_LENGTH]; +} NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS; + +/* + * NV0000_CTRL_CMD_DISABLE_SUB_PROCESS_USERD_ISOLATION + * + * Disable sub process USERD isolation. + * bIsSubProcIsolated + * NV_TRUE to disable sub process USERD isolation + * + * USERD allocated by different domains should not be put into the same physical page. + * This provides the basic security isolation because a physical page is the unit of + * granularity at which OS can provide isolation between processes. + * + * GUEST_USER: USERD allocated by guest user process + * GUEST_KERNEL: USERD allocated by guest kernel process + * GUEST_INSECURE: USERD allocated by guest/kernel process, + * INSECURE means there is no isolation between guest user and guest kernel + * HOST_USER: USERD allocated by host user process + * HOST_KERNEL: USERD allocated by host kernel process + * + * When sub process USERD isolation is disabled, we won't distinguish USERD allocated by guest + * user and guest kernel. They all belong to the GUEST_INSECURE domain. + * + * Please refer to wiki for more details: RM_USERD_Isolation + * + * Possible return values are: + * NV_OK + */ +#define NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS { + NvBool bIsSubProcessDisabled; +} NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS; + +#define NV0000_CTRL_CMD_SET_SUB_PROCESS_ID (0x901) /* finn: Evaluated from "(FINN_NV01_ROOT_PROC_INTERFACE_ID << 8) | NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_DISABLE_SUB_PROCESS_USERD_ISOLATION (0x902) /* finn: Evaluated from "(FINN_NV01_ROOT_PROC_INTERFACE_ID << 8) | NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS_MESSAGE_ID" */ + +/* _ctrl0000proc_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h new file mode 100644 index 0000000..1ca299f --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h @@ -0,0 +1,112 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000syncgpuboost.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +#include "nvtypes.h" +#include "nvlimits.h" + +/* --------------------------- Macros ----------------------------------------*/ +// There are at least 2 GPUs in a sync group. Hence max is half of max devices. +#define NV0000_SYNC_GPU_BOOST_MAX_GROUPS (0x10) /* finn: Evaluated from "((NV_MAX_DEVICES) >> 1)" */ +#define NV0000_SYNC_GPU_BOOST_INVALID_GROUP_ID 0xFFFFFFFF + +/*-------------------------Command Prototypes---------------------------------*/ + +/*! + * Query whether SYNC GPU BOOST MANAGER is enabled or disabled. + */ +#define NV0000_CTRL_CMD_SYNC_GPU_BOOST_INFO (0xa01) /* finn: Evaluated from "(FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID << 8) | NV0000_SYNC_GPU_BOOST_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_SYNC_GPU_BOOST_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_SYNC_GPU_BOOST_INFO_PARAMS { + // [out] Specifies if Sync Gpu Boost Manager is enabled or not. + NvBool bEnabled; +} NV0000_SYNC_GPU_BOOST_INFO_PARAMS; + +/*! + * Creates a Synchronized GPU-Boost Group (SGBG) + */ +#define NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_CREATE (0xa02) /* finn: Evaluated from "(FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID << 8) | NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS_MESSAGE_ID" */ + +/*! + * Describes a Synchronized GPU-Boost Group configuration + */ +typedef struct NV0000_SYNC_GPU_BOOST_GROUP_CONFIG { + // [in] Number of elements in @ref gpuIds + NvU32 gpuCount; + + // [in] IDs of GPUs to be put in the Sync Boost Group + NvU32 gpuIds[NV_MAX_DEVICES]; + + // [out] Unique ID of the SGBG, if created + NvU32 boostGroupId; + + // [in] If this group represents bridgeless SLI + NvBool bBridgeless; +} NV0000_SYNC_GPU_BOOST_GROUP_CONFIG; + +#define NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS { + NV0000_SYNC_GPU_BOOST_GROUP_CONFIG boostConfig; +} NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS; + +/*! + * Destroys a previously created Synchronized GPU-Boost Group(SGBG) + */ +#define NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_DESTROY (0xa03) /* finn: Evaluated from "(FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID << 8) | NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS_MESSAGE_ID" */ + +#define NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS { + // [[in] Unique ID of the SGBG to be destroyed + NvU32 boostGroupId; +} NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS; + +/*! + * Get configuration information for all Synchronized Boost Groups in the system. + */ +#define NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_INFO (0xa04) /* finn: Evaluated from "(FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID << 8) | NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS { + // [out] Number of groups retrieved. @ref NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS::boostGroups + NvU32 groupCount; + + // [out] @ref NV0000_SYNC_GPU_BOOST_GROUP_CONFIG + NV0000_SYNC_GPU_BOOST_GROUP_CONFIG pBoostGroups[NV0000_SYNC_GPU_BOOST_MAX_GROUPS]; +} NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS; + +/* _ctrl0000syncgpuboost_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000system.h b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000system.h new file mode 100644 index 0000000..8376c57 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000system.h @@ -0,0 +1,3239 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000system.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl0000/ctrl0000base.h" + +/* NV01_ROOT (client) system control commands and parameters */ + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_FEATURES + * + * This command returns a mask of supported features for the SYSTEM category + * of the 0000 class. + * + * Valid features include: + * + * NV0000_CTRL_GET_FEATURES_SLI + * When this bit is set, SLI is supported. + * NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT + * When this bit is set, EFI has initialized core channel + * NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED + * When this bit is set, RM test only code is supported. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_FEATURES (0x1f0U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID (0xF0U) + +typedef struct NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS { + NvU32 featuresMask; +} NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS; + + + +/* Valid feature values */ +#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI 0:0 +#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE (0x00000001U) + +#define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING 3:3 +#define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_TRUE (0x00000001U) + +#define NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED 4:4 +#define NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED_TRUE (0x00000001U) +/* + * NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION + * + * This command returns the current driver information. + * The first time this is called the size of strings is + * set with the greater of NV_BUILD_BRANCH_VERSION and + * NV_DISPLAY_DRIVER_TITLE. The client then allocates memory + * of size sizeOfStrings for pVersionBuffer and pTitleBuffer + * and calls the command again to receive driver info. + * + * sizeOfStrings + * This field returns the size in bytes of the pVersionBuffer and + * pTitleBuffer strings. + * pDriverVersionBuffer + * This field returns the version (NV_VERSION_STRING). + * pVersionBuffer + * This field returns the version (NV_BUILD_BRANCH_VERSION). + * pTitleBuffer + * This field returns the title (NV_DISPLAY_DRIVER_TITLE). + * changelistNumber + * This field returns the changelist value (NV_BUILD_CHANGELIST_NUM). + * officialChangelistNumber + * This field returns the last official changelist value + * (NV_LAST_OFFICIAL_CHANGELIST_NUM). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION (0x101U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS { + NvU32 sizeOfStrings; + NV_DECLARE_ALIGNED(NvP64 pDriverVersionBuffer, 8); + NV_DECLARE_ALIGNED(NvP64 pVersionBuffer, 8); + NV_DECLARE_ALIGNED(NvP64 pTitleBuffer, 8); + NvU32 changelistNumber; + NvU32 officialChangelistNumber; +} NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS; + +typedef enum NV0000_CTRL_SYSTEM_SH_SOC_TYPE { + NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NA = 0, + NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NV_GRACE = 1, + +} NV0000_CTRL_SYSTEM_SH_SOC_TYPE; + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO + * + * This command returns system CPU information. + * + * type + * This field returns the processor type. + * Legal processor types include: + * Intel processors: + * P55 : P55C - MMX + * P6 : PPro + * P2 : PentiumII + * P2XC : Xeon & Celeron + * CELA : Celeron-A + * P3 : Pentium-III + * P3_INTL2 : Pentium-III w/integrated L2 (fullspeed, on die, 256K) + * P4 : Pentium 4 + * CORE2 : Core2 Duo Conroe + * AMD processors + * K62 : K6-2 w/ 3DNow + * IDT/Centaur processors + * C6 : WinChip C6 + * C62 : WinChip 2 w/ 3DNow + * Cyrix processors + * GX : MediaGX + * M1 : 6x86 + * M2 : M2 + * MGX : MediaGX w/ MMX + * Transmeta processors + * TM_CRUSOE : Transmeta Crusoe(tm) + * PowerPC processors + * PPC603 : PowerPC 603 + * PPC604 : PowerPC 604 + * PPC750 : PowerPC 750 + * + * capabilities + * This field returns the capabilities of the processor. + * Legal processor capabilities include: + * MMX : supports MMX + * SSE : supports SSE + * 3DNOW : supports 3DNow + * SSE2 : supports SSE2 + * SFENCE : supports SFENCE + * WRITE_COMBINING : supports write-combining + * ALTIVEC : supports ALTIVEC + * PUT_NEEDS_IO : requires OUT inst w/PUT updates + * NEEDS_WC_WORKAROUND : requires workaround for P4 write-combining bug + * 3DNOW_EXT : supports 3DNow Extensions + * MMX_EXT : supports MMX Extensions + * CMOV : supports CMOV + * CLFLUSH : supports CLFLUSH + * SSE3 : supports SSE3 + * NEEDS_WAR_124888 : requires write to GPU while spinning on + * : GPU value + * HT : support hyper-threading + * clock + * This field returns the processor speed in MHz. + * L1DataCacheSize + * This field returns the level 1 data (or unified) cache size + * in kilobytes. + * L2DataCacheSize + * This field returns the level 2 data (or unified) cache size + * in kilobytes. + * dataCacheLineSize + * This field returns the bytes per line in the level 1 data cache. + * numLogicalCpus + * This field returns the number of logical processors. On Intel x86 + * systems that support it, this value will incorporate the current state + * of HyperThreading. + * numPhysicalCpus + * This field returns the number of physical processors. + * name + * This field returns the CPU name in ASCII string format. + * family + * Vendor defined Family and Extended Family combined + * model + * Vendor defined Model and Extended Model combined + * stepping + * Silicon stepping + * bCCEnabled + * Confidentail compute enabled/disabled state + * selfHostedSocType + * SoC type NV0000_CTRL_SYSTEM_SH_SOC_TYPE* in case of self hosted systems + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO (0x102U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS { + NvU32 type; /* processor type */ + NvU32 capabilities; /* processor caps */ + NvU32 clock; /* processor speed (MHz) */ + NvU32 L1DataCacheSize; /* L1 dcache size (KB) */ + NvU32 L2DataCacheSize; /* L2 dcache size (KB) */ + NvU32 dataCacheLineSize; /* L1 dcache bytes/line */ + NvU32 numLogicalCpus; /* logial processor cnt */ + NvU32 numPhysicalCpus; /* physical processor cnt*/ + NvU8 name[52]; /* embedded cpu name */ + NvU32 family; /* Vendor defined Family and Extended Family combined */ + NvU32 model; /* Vendor defined Model and Extended Model combined */ + NvU8 stepping; /* Silicon stepping */ + NvU32 coresOnDie; /* cpu cores per die */ + NvBool bCCEnabled; /* CC enabled on cpu */ + NV0000_CTRL_SYSTEM_SH_SOC_TYPE selfHostedSocType; /* SoC type in case of self hosted systems */ +} NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS; + +// Macros for CPU family information +#define NV0000_CTRL_SYSTEM_CPU_FAMILY 3:0 +#define NV0000_CTRL_SYSTEM_CPU_EXTENDED_FAMILY 11:4 + +// Macros for CPU model information +#define NV0000_CTRL_SYSTEM_CPU_MODEL 3:0 +#define NV0000_CTRL_SYSTEM_CPU_EXTENDED_MODEL 7:4 + +// Macros for AMD CPU information +#define NV0000_CTRL_SYSTEM_CPU_ID_AMD_FAMILY 0xF +#define NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_FAMILY 0xA +#define NV0000_CTRL_SYSTEM_CPU_ID_AMD_MODEL 0x0 +#define NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_MODEL 0x4 + +// Macros for Intel CPU information +#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_FAMILY 0x6 +#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_FAMILY 0x0 +#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_S_MODEL 0x7 +#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_P_MODEL 0xA +#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_MODEL 0x9 + +/* processor type values */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_UNKNOWN (0x00000000U) +/* Intel types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P5 (0x00000001U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P55 (0x00000002U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P6 (0x00000003U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P2 (0x00000004U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P2XC (0x00000005U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_CELA (0x00000006U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P3 (0x00000007U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P3_INTL2 (0x00000008U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P4 (0x00000009U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2 (0x00000010U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_CELN_M16H (0x00000011U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2_EXTRM (0x00000012U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_ATOM (0x00000013U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_XEON_SPR (0x00000014U) +/* AMD types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K5 (0x00000030U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K6 (0x00000031U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K62 (0x00000032U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K63 (0x00000033U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K7 (0x00000034U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K8 (0x00000035U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K10 (0x00000036U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K11 (0x00000037U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_RYZEN (0x00000038U) +/* IDT/Centaur types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_C6 (0x00000060U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_C62 (0x00000061U) +/* Cyrix types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_GX (0x00000070U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_M1 (0x00000071U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_M2 (0x00000072U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_MGX (0x00000073U) +/* Transmeta types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_TM_CRUSOE (0x00000080U) +/* IBM types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC603 (0x00000090U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC604 (0x00000091U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC750 (0x00000092U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_POWERN (0x00000093U) +/* Unknown ARM architecture CPU type */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_UNKNOWN (0xA0000000U) +/* ARM Ltd types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A9 (0xA0000009U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A15 (0xA000000FU) +/* NVIDIA types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_1_0 (0xA0001000U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_2_0 (0xA0002000U) + +/* Generic types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC (0xA00FF000U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC (0xA00FF001U) + +/* processor capabilities */ +#define NV0000_CTRL_SYSTEM_CPU_CAP_MMX (0x00000001U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE (0x00000002U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW (0x00000004U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 (0x00000008U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE (0x00000010U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING (0x00000020U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC (0x00000040U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_PUT_NEEDS_IO (0x00000080U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WC_WORKAROUND (0x00000100U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT (0x00000200U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT (0x00000400U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_CMOV (0x00000800U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH (0x00001000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_190854 (0x00002000U) /* deprecated */ +#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 (0x00004000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_124888 (0x00008000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE (0x00010000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 (0x00020000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 (0x00040000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_AVX (0x00080000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_ERMS (0x00100000U) + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO + * + * This command returns system chipset information. + * + * vendorId + * This parameter returns the vendor identification for the chipset. + * A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the chipset + * cannot be identified. + * deviceId + * This parameter returns the device identification for the chipset. + * A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the chipset + * cannot be identified. + * subSysVendorId + * This parameter returns the subsystem vendor identification for the + * chipset. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the + * chipset cannot be identified. + * subSysDeviceId + * This parameter returns the subsystem device identification for the + * chipset. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the + * chipset cannot be identified. + * HBvendorId + * This parameter returns the vendor identification for the chipset's + * host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates + * the chipset's host bridge cannot be identified. + * HBdeviceId + * This parameter returns the device identification for the chipset's + * host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates + * the chipset's host bridge cannot be identified. + * HBsubSysVendorId + * This parameter returns the subsystem vendor identification for the + * chipset's host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID + * indicates the chipset's host bridge cannot be identified. + * HBsubSysDeviceId + * This parameter returns the subsystem device identification for the + * chipset's host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID + * indicates the chipset's host bridge cannot be identified. + * sliBondId + * This parameter returns the SLI bond identification for the chipset. + * vendorNameString + * This parameter returns the vendor name string. + * chipsetNameString + * This parameter returns the vendor name string. + * sliBondNameString + * This parameter returns the SLI bond name string. + * flag + * This parameter specifies NV0000_CTRL_SYSTEM_CHIPSET_FLAG_XXX flags: + * _HAS_RESIZABLE_BAR_ISSUE_YES: Chipset where the use of resizable BAR1 + * should be disabled - bug 3440153 + * _BAR1_UNALIGNED_ACCESS_YES: unaligned acccess in BAR1 is allowed. + * chipsetId + * This parameter returns the chipset identification. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO (0x104U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID" */ + +/* maximum name string length */ +#define NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH (0x0000020U) + +/* invalid id */ +#define NV0000_SYSTEM_CHIPSET_INVALID_ID (0xffffU) + +#define NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS { + NvU16 vendorId; + NvU16 deviceId; + NvU16 subSysVendorId; + NvU16 subSysDeviceId; + NvU16 HBvendorId; + NvU16 HBdeviceId; + NvU16 HBsubSysVendorId; + NvU16 HBsubSysDeviceId; + NvU32 sliBondId; + NvU8 vendorNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; + NvU8 subSysVendorNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; + NvU8 chipsetNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; + NvU8 sliBondNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; + NvU32 flags; + NvU32 chipsetId; +} NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS; + +#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE 0:0 +#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_NO (0x00000000U) +#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_YES (0x00000001U) + +#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_BAR1_UNALIGNED_ACCESS 1:1 +#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_BAR1_UNALIGNED_ACCESS_NO (0x00000000U) +#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_BAR1_UNALIGNED_ACCESS_YES (0x00000001U) + + + +/* + * NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT + * + * This command returns whether the VRR cookie is present in the SBIOS. + * + * bIsPresent (out) + * This parameter contains whether the VRR cookie is present in the SBIOS. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT (0x107U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS { + NvBool bIsPresent; +} NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES + * + * This command is used to retrieve the measured times spent holding and waiting for + * the main RM locks (API and GPU). + * + * waitApiLock + * Total time spent by RM API's waiting to acquire the API lock + * + * holdRoApiLock + * Total time spent by RM API's holding the API lock in RO mode. + * + * holdRwApiLock + * Total time spent by RM API's holding the API lock in RW mode. + * + * waitGpuLock + * Total time spent by RM API's waiting to acquire one or more GPU locks. + * + * holdGpuLock + * Total time spent by RM API's holding one or more GPU locks. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES (0x109U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS { + NV_DECLARE_ALIGNED(NvU64 waitApiLock, 8); + NV_DECLARE_ALIGNED(NvU64 holdRoApiLock, 8); + NV_DECLARE_ALIGNED(NvU64 holdRwApiLock, 8); + NV_DECLARE_ALIGNED(NvU64 waitGpuLock, 8); + NV_DECLARE_ALIGNED(NvU64 holdGpuLock, 8); +} NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST + * + * This command is used to retrieve the set of system-level classes + * supported by the platform. + * + * numClasses + * This parameter returns the number of valid entries in the returned + * classes[] list. This parameter will not exceed + * Nv0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE. + * classes + * This parameter returns the list of supported classes + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST (0x108U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID" */ + +/* maximum number of classes returned in classes[] array */ +#define NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE (32U) + +#define NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS { + NvU32 numClasses; + NvU32 classes[NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE]; +} NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT + * + * This command is used to send triggered mobile related system events + * to the RM. + * + * eventType + * This parameter indicates the triggered event type. This parameter + * should specify a valid NV0000_CTRL_SYSTEM_EVENT_TYPE value. + * eventData + * This parameter specifies the type-dependent event data associated + * with EventType. This parameter should specify a valid + * NV0000_CTRL_SYSTEM_EVENT_DATA value. + * bEventDataForced + * This parameter specifies what we have to do, Whether trust current + * Lid/Dock state or not. This parameter should specify a valid + * NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED value. + + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * Sync this up (#defines) with one in nvapi.spec! + * (NV_ACPI_EVENT_TYPE & NV_ACPI_EVENT_DATA) + */ +#define NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT (0x110U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS { + NvU32 eventType; + NvU32 eventData; + NvBool bEventDataForced; +} NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS; + +/* valid eventType values */ +#define NV0000_CTRL_SYSTEM_EVENT_TYPE_LID_STATE (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_TYPE_POWER_SOURCE (0x00000001U) +#define NV0000_CTRL_SYSTEM_EVENT_TYPE_DOCK_STATE (0x00000002U) +#define NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_LID (0x00000003U) +#define NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_DOCK (0x00000004U) + +/* valid eventData values */ +#define NV0000_CTRL_SYSTEM_EVENT_DATA_LID_OPEN (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_LID_CLOSED (0x00000001U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_BATTERY (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_AC (0x00000001U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_UNDOCKED (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_DOCKED (0x00000001U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DSM (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DCS (0x00000001U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_NVIF (0x00000002U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_ACPI (0x00000003U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL (0x00000004U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_COUNT (0x5U) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL + 1)" */ +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DSM (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DCS (0x00000001U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_NVIF (0x00000002U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_ACPI (0x00000003U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL (0x00000004U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_COUNT (0x5U) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL + 1)" */ + +/* valid bEventDataForced values */ +#define NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_TRUE (0x00000001U) + +/* + * NV000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE + * + * This command is used to query the platform type. + * + * systemType + * This parameter returns the type of the system. + * Legal values for this parameter include: + * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP + * The system is a desktop platform. + * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC + * The system is a mobile (non-Toshiba) platform. + * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP + * The system is a mobile Toshiba platform. + * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC + * The system is a system-on-a-chip (SOC) platform. + * + + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE (0x111U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS { + NvU32 systemType; +} NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS; + +/* valid systemType values */ +#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP (0x000000U) +#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC (0x000001U) +#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_TOSHIBA (0x000002U) +#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC (0x000003U) + + + + +/* + * NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL + * + * This command controls the current RmMsg filters. + * + * It is only supported if RmMsg is enabled (e.g. debug builds). + * + * cmd + * GET - Gets the current RmMsg filter string. + * SET - Sets the current RmMsg filter string. + * + * count + * The length of the RmMsg filter string. + * + * data + * The RmMsg filter string. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL (0x121U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE 512U + +#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_GET (0x00000000U) +#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_SET (0x00000001U) + +#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID (0x21U) + +typedef struct NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS { + NvU32 cmd; + NvU32 count; + NvU8 data[NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE]; +} NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL + * + * This command is used to control GPS functionality. It allows control of + * GPU Performance Scaling (GPS), changing its operational parameters and read + * most GPS dynamic parameters. + * + * command + * This parameter specifies the command to execute. Invalid commands + * result in the return of an NV_ERR_INVALID_ARGUMENT status. + * locale + * This parameter indicates the specific locale to which the command + * 'command' is to be applied. + * Supported range of CPU/GPU {i = 0, ..., 255} + * data + * This parameter contains a command-specific data payload. It can + * be used to input data as well as output data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_COMMAND + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_DATA + * NV_ERR_INVALID_REQUEST + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL (0x122U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS { + NvU16 command; + NvU16 locale; + NvU32 data; +} NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS; + +/* + * Valid command values : + * + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT + * Is used to check if GPS was correctly initialized. + * Possible return (OUT) values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC + * Are used to stop/start GPS functionality and to get current status. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS + * Are used to control execution of GPS actions and to get current status. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC + * Are used to switch current GPS logic and to retrieve current logic. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF + * Will cause that all GPS actions will be NULL. + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY + * Fuzzy logic will determine GPS actions based on current ruleset. + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC + * Deterministic logic will define GPS actions based on current ruleset. + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE + * Are used to set/retrieve system control preference. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT + * Are used to set/retrieve GPU2CPU pstate limits. + * IN/OUT values are four bytes packed into a 32-bit data field. + * The CPU cap index for GPU pstate 0 is in the lowest byte, the CPU cap + * index for the GPU pstate 3 is in the highest byte, etc. One + * special value is to disable the override to the GPU2CPU map: + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE + * Is used to stop/start GPS PMU functionality. + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE + * Is used to get the current status of PMU GPS. + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER + * Are used to set/retrieve max power [mW] that system can provide. + * This is hardcoded GPS safety feature and logic/rules does not apply + * to this threshold. + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET + * Are used to set/retrieve current system cooling budget [mW]. + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD + * Are used to set/retrieve integration interval [sec]. + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT + * Are used to set/retrieve used ruleset [#]. Value is checked + * against MAX number of rules for currently used GPS logic. Also COUNT + * provides a way to find out how many rules exist for the current control + * system. + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST + * Is used to set/get a delay relative to now during which to allow unbound + * CPU performance. Units are seconds. + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE + * Is used to override/get the actual power supply mode (AC/Battery). + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO + * Is used to get the Ventura system information for VCT tool + * Returned 32bit value should be treated as bitmask and decoded in + * following way: + * Encoding details are defined in objgps.h refer to + * NV_GPS_SYS_SUPPORT_INFO and corresponding bit defines. + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTION + * Is used to get the supported sub-functions defined in SBIOS. Returned + * value is a bitmask where each bit corresponds to different function: + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE + * Are used to retrieve appropriate power measurements and their derivatives + * in [mW] for required locale. _BURDEN is defined only for _LOCALE_SYSTEM. + * _INTERMEDIATE is not defined for _LOCALE_SYSTEM, and takes an In value as + * index. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS + * Is used to retrieve parameters when adjusting raw sensor power reading. + * The values may come from SBIOS, VBIOS, registry or driver default. + * Possible IN value is the index of interested parameter. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE + * Are used to retrieve appropriate temperature measurements and their + * derivatives in [1/1000 Celsius]. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX + * Are used to retrieve CPU(x)/GPU(x) p-state or it's limits. + * Not applicable to _LOCALE_SYSTEM. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION + * Is used to retrieve last GPS action for given domain. + * Not applicable to _LOCALE_SYSTEM. + * Possible return (OUT) values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0 + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1 + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1 + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2 + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE + * Is used to set the power sensor simulator state. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE + * Is used to get the power simulator sensor simulator state. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA + * Is used to set power sensor simulator data + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA + * Is used to get power sensor simulator data + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK + * Is used to respond to the ACPI event triggered by SBIOS. RM will + * request value for budget and status, validate them, apply them + * and send ACK back to SBIOS. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT + * Is a test cmd that should notify SBIOS to send ACPI event requesting + * budget and status change. + */ +#define NV0000_CTRL_CMD_SYSTEM_GPS_INVALID (0xFFFFU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT (0x0000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC (0x0001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC (0x0002U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS (0x0003U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS (0x0004U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC (0x0005U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC (0x0006U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE (0x0007U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE (0x0008U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT (0x0009U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT (0x000AU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE (0x000BU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE (0x000CU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER (0x0100U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER (0x0101U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET (0x0102U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET (0x0103U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD (0x0104U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD (0x0105U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET (0x0106U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET (0x0107U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT (0x0108U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST (0x0109U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST (0x010AU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE (0x010BU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE (0x010CU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO (0x010DU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTIONS (0x010EU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER (0x0200U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA (0x0201U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE (0x0202U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG (0x0203U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL (0x0204U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN (0x0205U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE (0x0206U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS (0x0210U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP (0x0220U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA (0x0221U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE (0x0222U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE (0x0240U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP (0x0241U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN (0x0242U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX (0x0243U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION (0x0244U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_SLFM_PRESENT (0x0245U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE (0x0250U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE (0x0251U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA (0x0252U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA (0x0253U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK (0x0320U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT (0x0321U) + +/* valid LOCALE values */ +#define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_INVALID (0xFFFFU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_SYSTEM (0x0000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_CPU(i) (0x0100+((i)%0x100)) +#define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_GPU(i) (0x0200+((i)%0x100)) + +/* valid data values for enums */ +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID (0x80000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE (0xFFFFFFFFU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_ON (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS (0x00000004U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC (0x00000008U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC (0x00000010U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB (0x00000020U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS (0x00000040U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0 (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1 (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT (0x00000003U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1 (0x00000004U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2 (0x00000005U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM (0x00000006U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM (0x00000007U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_NO (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_YES (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_ON (0x00000001U) + +/* + * NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL + * + * This command allows execution of multiple GpsControl commands within one + * RmControl call. For practical reasons # of commands is limited to 16. + * This command shares defines with NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL. + * + * cmdCount + * Number of commands that should be executed. + * Less or equal to NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX. + * + * succeeded + * Number of commands that were succesully executed. + * Less or equal to NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX. + * Failing commands return NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID + * in their data field. + * + * cmdData + * Array of commands with following structure: + * command + * This parameter specifies the command to execute. + * Invalid commands result in the return of an + * NV_ERR_INVALID_ARGUMENT status. + * locale + * This parameter indicates the specific locale to which + * the command 'command' is to be applied. + * Supported range of CPU/GPU {i = 0, ..., 255} + * data + * This parameter contains a command-specific data payload. + * It is used both to input data as well as to output data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL (0x123U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX (16U) +#define NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID (0x23U) + +typedef struct NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS { + NvU32 cmdCount; + NvU32 succeeded; + + struct { + NvU16 command; + NvU16 locale; + NvU32 data; + } cmdData[NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX]; +} NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS; + + +/* + * Deprecated. Please use NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 instead. + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS (0x127U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID" */ + +/* + * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED must remain equal to the square of + * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS due to Check RM parsing issues. + * NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS is the maximum size of GPU groups + * allowed for batched P2P caps queries provided by the RM control + * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX. + */ +#define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS 32U +#define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED 1024U +#define NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS 8U +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER 0xffffffffU + +/* P2P capabilities status index values */ +#define NV0000_CTRL_P2P_CAPS_INDEX_READ 0U +#define NV0000_CTRL_P2P_CAPS_INDEX_WRITE 1U +#define NV0000_CTRL_P2P_CAPS_INDEX_NVLINK 2U +#define NV0000_CTRL_P2P_CAPS_INDEX_ATOMICS 3U +#define NV0000_CTRL_P2P_CAPS_INDEX_PROP 4U +#define NV0000_CTRL_P2P_CAPS_INDEX_LOOPBACK 5U +#define NV0000_CTRL_P2P_CAPS_INDEX_PCI 6U +#define NV0000_CTRL_P2P_CAPS_INDEX_C2C 7U +#define NV0000_CTRL_P2P_CAPS_INDEX_PCI_BAR1 8U + +#define NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE 9U + + +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID (0x27U) + +typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS { + NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; + NvU32 gpuCount; + NvU32 p2pCaps; + NvU32 p2pOptimalReadCEs; + NvU32 p2pOptimalWriteCEs; + NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; + NV_DECLARE_ALIGNED(NvP64 busPeerIds, 8); + NV_DECLARE_ALIGNED(NvP64 busEgmPeerIds, 8); +} NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS; + +/* valid p2pCaps values */ +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED 0:0 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED 1:1 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED 2:2 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED 3:3 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED 4:4 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED 5:5 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED 6:6 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED 7:7 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED 8:8 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED 9:9 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED 10:10 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_TRUE (0x00000001U) + + +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED 12:12 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED 13:13 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_TRUE (0x00000001U) + +/* P2P status codes */ +#define NV0000_P2P_CAPS_STATUS_OK (0x00U) +#define NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED (0x01U) +#define NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED (0x02U) +#define NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED (0x03U) +#define NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY (0x04U) +#define NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED (0x05U) + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 + * + * This command returns peer to peer capabilities present between GPUs. + * Valid requests must present a list of GPU Ids. + * + * [in] gpuIds + * This member contains the array of GPU IDs for which we query the P2P + * capabilities. Valid entries are contiguous, beginning with the first + * entry in the list. + * [in] gpuCount + * This member contains the number of GPU IDs stored in the gpuIds[] array. + * [out] p2pCaps + * This member returns the peer to peer capabilities discovered between the + * GPUs. Valid p2pCaps values include: + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED + * When this bit is set, peer to peer writes between subdevices owned + * by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED + * When this bit is set, peer to peer reads between subdevices owned + * by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED + * When this bit is set, peer to peer PROP between subdevices owned + * by this device are supported. This is enabled by default + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED + * When this bit is set, PCI is supported for all P2P between subdevices + * owned by this device. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED + * When this bit is set, NVLINK is supported for all P2P between subdevices + * owned by this device. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED + * When this bit is set, peer to peer atomics between subdevices owned + * by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED + * When this bit is set, peer to peer loopback is supported for subdevices + * owned by this device. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED + * When this bit is set, indirect peer to peer writes between subdevices + * owned by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED + * When this bit is set, indirect peer to peer reads between subdevices + * owned by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED + * When this bit is set, indirect peer to peer atomics between + * subdevices owned by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED + * When this bit is set, indirect NVLINK is supported for subdevices + * owned by this device. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED + * When this bit is set, C2C P2P is supported between the GPUs + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_BAR1_SUPPORTED + * When this bit is set, BAR1 P2P is supported between the GPUs + * mentioned in @ref gpuIds + * [out] p2pOptimalReadCEs + * For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink + * [out] p2pOptimalWriteCEs + * For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink + * [out] p2pCapsStatus + * This member returns status of all supported p2p capabilities. Valid + * status values include: + * NV0000_P2P_CAPS_STATUS_OK + * P2P capability is supported. + * NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED + * Chipset doesn't support p2p capability. + * NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED + * GPU doesn't support p2p capability. + * NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED + * IOH topology isn't supported. For e.g. root ports are on different + * IOH. + * NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY + * P2P Capability is disabled by a regkey. + * NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED + * P2P Capability is not supported. + * NV0000_P2P_CAPS_STATUS_NVLINK_SETUP_FAILED + * Indicates that NvLink P2P link setup failed. + * [out] busPeerIds + * Peer ID matrix. It is a one-dimentional array. + * busPeerIds[X * gpuCount + Y] maps from index X to index Y in + * the gpuIds[] table. For invalid or non-existent peer busPeerIds[] + * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. + * [out] busEgmPeerIds + * EGM Peer ID matrix. It is a one-dimentional array. + * busEgmPeerIds[X * gpuCount + Y] maps from index X to index Y in + * the gpuIds[] table. For invalid or non-existent peer busEgmPeerIds[] + * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ + + + +#define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 (0x12bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID (0x2BU) + +typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS { + NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; + NvU32 gpuCount; + NvU32 p2pCaps; + NvU32 p2pOptimalReadCEs; + NvU32 p2pOptimalWriteCEs; + NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; + NvU32 busPeerIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED]; + NvU32 busEgmPeerIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED]; +} NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX + * + * This command returns peer to peer capabilities present between all pairs of + * GPU IDs {(a, b) : a in gpuIdGrpA and b in gpuIdGrpB}. This can be used to + * collect all P2P capabilities in the system - see the SRT: + * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX_TEST + * for a demonstration. + * + * The call will query for all pairs between set A and set B, and returns + * results in both link directions. The results are two-dimensional arrays where + * the first dimension is the index within the set-A array of one GPU ID under + * consideration, and the second dimension is the index within the set-B array + * of the other GPU ID under consideration. + * + * That is, the result arrays are *ALWAYS* to be indexed first with the set-A + * index, then with the set-B index. The B-to-A direction of results are put in + * the b2aOptimal(Read|Write)CEs. This makes it unnecessary to call the query + * twice, since the usual use case requires both directions. + * + * If a set is being compared against itself (by setting grpBCount to 0), then + * the result matrices are symmetric - it doesn't matter which index is first. + * However, the choice of indices is effectively a choice of which ID is "B" and + * which is "A" for the "a2b" and "b2a" directional results. + * + * [in] grpACount + * This member contains the number of GPU IDs stored in the gpuIdGrpA[] + * array. Must be >= 0. + * [in] grpBCount + * This member contains the number of GPU IDs stored in the gpuIdGrpB[] + * array. Can be == 0 to specify a check of group A against itself. + * [in] gpuIdGrpA + * This member contains the array of GPU IDs in "group A", each of which + * will have its P2P capabilities returned with respect to each GPU ID in + * "group B". Valid entries are contiguous, beginning with the first entry + * in the list. + * [in] gpuIdGrpB + * This member contains the array of GPU IDs in "group B", each of which + * will have its P2P capabilities returned with respect to each GPU ID in + * "group A". Valid entries are contiguous, beginning with the first entry + * in the list. May be equal to gpuIdGrpA, but best performance requires + * that the caller specifies grpBCount = 0 in this case, and ignores this. + * [out] p2pCaps + * This member returns the peer to peer capabilities discovered between the + * pairs of input GPUs between the groups, indexed by [A_index][B_index]. + * Valid p2pCaps values include: + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED + * When this bit is set, peer to peer writes between subdevices owned + * by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED + * When this bit is set, peer to peer reads between subdevices owned + * by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED + * When this bit is set, peer to peer PROP between subdevices owned + * by this device are supported. This is enabled by default + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED + * When this bit is set, PCI is supported for all P2P between subdevices + * owned by this device. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED + * When this bit is set, NVLINK is supported for all P2P between subdevices + * owned by this device. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED + * When this bit is set, peer to peer atomics between subdevices owned + * by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED + * When this bit is set, peer to peer loopback is supported for subdevices + * owned by this device. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED + * When this bit is set, indirect peer to peer writes between subdevices + * owned by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED + * When this bit is set, indirect peer to peer reads between subdevices + * owned by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED + * When this bit is set, indirect peer to peer atomics between + * subdevices owned by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED + * When this bit is set, indirect NVLINK is supported for subdevices + * owned by this device. + * [out] a2bOptimalReadCes + * For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink + * in the A-to-B direction. + * [out] a2bOptimalWriteCes + * For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink + * in the A-to-B direction. + * [out] b2aOptimalReadCes + * For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink + * in the B-to-A direction. + * [out] b2aOptimalWriteCes + * For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink + * in the B-to-A direction. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ + + + +#define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX (0x13aU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID (0x3AU) + +typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS { + NvU32 grpACount; + NvU32 grpBCount; + NvU32 gpuIdGrpA[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; + NvU32 gpuIdGrpB[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; + NvU32 p2pCaps[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS][NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; + NvU32 a2bOptimalReadCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS][NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; + NvU32 a2bOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS][NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; + NvU32 b2aOptimalReadCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS][NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; + NvU32 b2aOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS][NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; +} NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GPS_CTRL + * + * This command is used to execute general GPS Functions, most dealing with + * calling SBIOS, or retrieving cached sensor and GPS state data. + * + * version + * This parameter specifies the version of the interface. Legal values + * for this parameter are 1. + * cmd + * This parameter specifies the GPS API to be invoked. + * Valid values for this parameter are: + * NV0000_CTRL_GPS_CMD_GET_THERM_LIMIT + * This command gets the temperature limit for thermal controller. When + * this command is specified the input parameter contains ???. + * NV0000_CTRL_GPS_CMD_SET_THERM_LIMIT + * This command set the temperature limit for thermal controller. When + * this command is specified the input parameter contains ???. + * input + * This parameter specifies the cmd-specific input value. + * result + * This parameter returns the cmd-specific output value. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_SYSTEM_GPS_CTRL (0x12aU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID (0x2AU) + +typedef struct NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS { + NvU32 cmd; + NvS32 input[2]; + NvS32 result[4]; +} NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS; + +/* valid version values */ +#define NV0000_CTRL_GPS_PSHARE_PARAMS_PSP_CURRENT_VERSION (0x00010000U) + +/* valid cmd values */ +#define NV0000_CTRL_GPS_CMD_TYPE_GET_THERM_LIMIT (0x00000002U) +#define NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000U) +#define NV0000_CTRL_GPS_RESULT_THERMAL_LIMIT (0x00000000U) +#define NV0000_CTRL_GPS_RESULT_MIN_LIMIT (0x00000001U) +#define NV0000_CTRL_GPS_RESULT_MAX_LIMIT (0x00000002U) +#define NV0000_CTRL_GPS_RESULT_LIMIT_SOURCE (0x00000003U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_THERM_LIMIT (0x00000003U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_THERMAL_LIMIT (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA (0x00000004U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DOWN_N_DELTA (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA (0x00000005U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DOWN_N_DELTA (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA (0x00000006U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_HOLD_DELTA (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA (0x00000007U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_HOLD_DELTA (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA (0x00000008U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_UP_DELTA (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA (0x00000009U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_UP_DELTA (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA (0x0000000AU) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_ENGAGE_DELTA (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA (0x0000000BU) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_ENGAGE_DELTA (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000CU) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000DU) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_STATUS (0x00000016U) +#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_STATUS (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_STATUS (0x00000017U) +#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_STATUS (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM (0x00000018U) +#define NV0000_CTRL_GPS_RESULT_CPU_SET_UTIL_AVG_NUM (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM (0x00000019U) +#define NV0000_CTRL_GPS_INPUT_CPU_GET_UTIL_AVG_NUM (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_PERF_SENSOR (0x0000001AU) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_NEXT_EXPECTED_POLL (0x00000001U) +#define NV0000_CTRL_GPS_RESULT_PERF_SENSOR_VALUE (0x00000000U) +#define NV0000_CTRL_GPS_RESULT_PERF_SENSOR_AVAILABLE (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_CALL_ACPI (0x0000001BU) +#define NV0000_CTRL_GPS_INPUT_ACPI_CMD (0x00000000U) +#define NV0000_CTRL_GPS_INPUT_ACPI_PARAM_IN (0x00000001U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_1 (0x00000000U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_2 (0x00000001U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_STATUS (0x00000000U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_VERSION (0x00000001U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_SZ (0x00000002U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_SZ (0x00000000U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_COUNT (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_IGPU_TURBO (0x0000001CU) +#define NV0000_CTRL_GPS_INPUT_SET_IGPU_TURBO (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERIOD (0x00000026U) +#define NV0000_CTRL_GPS_INPUT_TEMP_PERIOD (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERIOD (0x00000027U) +#define NV0000_CTRL_GPS_RESULT_TEMP_PERIOD (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_NUDGE_FACTOR (0x00000028U) +#define NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_UP (0x00000000U) +#define NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_DOWN (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_NUDGE_FACTOR (0x00000029U) +#define NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_UP (0x00000000U) +#define NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_DOWN (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES (0x0000002AU) +#define NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) +#define NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES (0x0000002BU) +#define NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) +#define NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERF_LIMITS (0x0000002CU) +#define NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_UPPER (0x00000000U) +#define NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_LOWER (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERF_LIMITS (0x0000002DU) +#define NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_UPPER (0x00000000U) +#define NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_LOWER (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_PM1_AVAILABLE (0x0000002EU) +#define NV0000_CTRL_GPS_INPUT_PM1_AVAILABLE (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_PM1_AVAILABLE (0x0000002FU) +#define NV0000_CTRL_GPS_OUTPUT_PM1_AVAILABLE (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS (0x00000044U) +#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) +#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS (0x00000045U) +#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT (0x00000046U) +#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ (0000000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT (0x00000047U) +#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ (0000000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM (0x00000048U) +#define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_INDEX (0000000000U) +#define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_AVAILABLE_MASK (0000000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM (0x00000049U) +#define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX (0000000000U) +#define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX_MAX (2U) + +#define NV0000_CTRL_GPS_PPM_INDEX 7:0 +#define NV0000_CTRL_GPS_PPM_INDEX_MAXPERF (0U) +#define NV0000_CTRL_GPS_PPM_INDEX_BALANCED (1U) +#define NV0000_CTRL_GPS_PPM_INDEX_QUIET (2U) +#define NV0000_CTRL_GPS_PPM_INDEX_INVALID (0xFFU) +#define NV0000_CTRL_GPS_PPM_MASK 15:8 +#define NV0000_CTRL_GPS_PPM_MASK_INVALID (0U) + +/* valid PS_STATUS result values */ +#define NV0000_CTRL_GPS_CMD_PS_STATUS_OFF (0U) +#define NV0000_CTRL_GPS_CMD_PS_STATUS_ON (1U) + + +#define GPS_MAX_COUNTERS_PER_BLOCK 32U +#define NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID (0x29U) + +typedef struct NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS { + NvU32 objHndl; + NvU32 blockId; + NvU32 nextExpectedSampleTimems; + NvU32 countersReq; + NvU32 countersReturned; + NvU32 counterBlock[GPS_MAX_COUNTERS_PER_BLOCK]; +} NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS; + +#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS (0x12cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS_MESSAGE_ID (0x2CU) + +typedef NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS; + +#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS (0x12eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID (0x2EU) + +typedef NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI + * + * This command allows users to call GPS ACPI commands for testing purposes. + * + * cmd + * This parameter specifies the GPS ACPI command to execute. + * + * input + * This parameter specified the cmd-dependent input value. + * + * resultSz + * This parameter returns the size (in bytes) of the valid data + * returned in the result parameter. + * + * result + * This parameter returns the results of the specified cmd. + * The maximum size (in bytes) of this returned data will + * not exceed GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE + * + * GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE + * The size of buffer (result) in unit of NvU32. + * The smallest value is sizeof(PSS_ENTRY)*ACPI_PSS_ENTRY_MAX. + * Since the prior one is 24 bytes, and the later one is 48, + * this value cannot be smaller than 288. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT, + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_PERMISSIONS + * + */ +#define GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U +#define NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID (0x2DU) + +typedef struct NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS { + NvU32 cmd; + NvU32 input; + NvU32 resultSz; + NvU32 result[GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE]; +} NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS; + +#define NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI (0x12dU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID" */ + +/* + * NV0000_CTRL_SYSTEM_PARAM_* + * + * The following is a list of system-level parameters (often sensors) that the + * driver can be made aware of. They are primarily intended to be used by system + * power-balancing algorithms that require system-wide visibility in order to + * function. The names and values used here are established and specified in + * several different NVIDIA documents that are made externally available. Thus, + * updates to this list must be made with great caution. The only permissible + * change is to append new parameters. Reordering is strictly prohibited. + * + * Brief Parameter Summary: + * TGPU - GPU temperature (NvTemp) + * PDTS - CPU package temperature (NvTemp) + * SFAN - System fan speed (% of maximum fan speed) + * SKNT - Skin temperature (NvTemp) + * CPUE - CPU energy counter (NvU32) + * TMP1 - Additional temperature sensor 1 (NvTemp) + * TMP2 - Additional temperature sensor 2 (NvTemp) + * CTGP - Mode 2 power limit offset (NvU32) + * PPMD - Power mode data (NvU32) + */ +#define NV0000_CTRL_SYSTEM_PARAM_TGPU (0x00000000U) +#define NV0000_CTRL_SYSTEM_PARAM_PDTS (0x00000001U) +#define NV0000_CTRL_SYSTEM_PARAM_SFAN (0x00000002U) +#define NV0000_CTRL_SYSTEM_PARAM_SKNT (0x00000003U) +#define NV0000_CTRL_SYSTEM_PARAM_CPUE (0x00000004U) +#define NV0000_CTRL_SYSTEM_PARAM_TMP1 (0x00000005U) +#define NV0000_CTRL_SYSTEM_PARAM_TMP2 (0x00000006U) +#define NV0000_CTRL_SYSTEM_PARAM_CTGP (0x00000007U) +#define NV0000_CTRL_SYSTEM_PARAM_PPMD (0x00000008U) +#define NV0000_CTRL_SYSTEM_PARAM_COUNT (0x00000009U) + +/* + * NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD + * + * This command is used to execute general ACPI methods. + * + * method + * This parameter identifies the MXM ACPI API to be invoked. + * Valid values for this parameter are: + * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS + * This value specifies that the DSM NVOP subfunction OPTIMUSCAPS + * API is to be invoked. + * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG + * This value specifies that the DSM NVOP subfunction OPTIMUSFLAG + * API is to be invoked. This API will set a Flag in sbios to Indicate + * that HD Audio Controller is disable/Enabled from GPU Config space. + * This flag will be used by sbios to restore Audio state after resuming + * from s3/s4. + * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS + * This value specifies that the DSM JT subfunction FUNC_CAPS is to + * to be invoked to get the SBIOS capabilities + * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY + * This value specifies that the DSM JT subfunction FUNC_PLATPOLICY is + * to be invoked to set and get the various platform policies for JT. + * Refer to the JT spec in more detail on various policies. + * inData + * This parameter specifies the method-specific input buffer. Data is + * passed to the specified API using this buffer. + * inDataSize + * This parameter specifies the size of the inData buffer in bytes. + * outStatus + * This parameter returns the status code from the associated ACPI call. + * outData + * This parameter specifies the method-specific output buffer. Data + * is returned by the specified API using this buffer. + * outDataSize + * This parameter specifies the size of the outData buffer in bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD (0x130U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID (0x30U) + +typedef struct NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS { + NvU32 method; + NV_DECLARE_ALIGNED(NvP64 inData, 8); + NvU16 inDataSize; + NvU32 outStatus; + NV_DECLARE_ALIGNED(NvP64 outData, 8); + NvU16 outDataSize; +} NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS; + +/* valid method parameter values */ +#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS (0x00000000U) +#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG (0x00000001U) +#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS (0x00000002U) +#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY (0x00000003U) +/* + * NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS + * + * This command can be used to instruct the RM to enable/disable specific module + * of ETW events. + * + * moduleMask + * This parameter specifies the module of events we would like to + * enable/disable. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS (0x131U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID (0x31U) + +typedef struct NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS { + NvU32 moduleMask; +} NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS; + +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ALL (0x00000001U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NOFREQ (0x00000002U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_FLUSH (0x00000004U) + +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PERF (0x00000010U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ELPG (0x00000020U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVDPS (0x00000040U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_POWER (0x00000080U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_DISP (0x00000100U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RMAPI (0x00000200U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_INTR (0x00000400U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_LOCK (0x00000800U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RCJOURNAL (0x00001000U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GENERIC (0x00002000U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_THERM (0x00004000U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GPS (0x00008000U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PCIE (0x00010000U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVTELEMETRY (0x00020000U) + +/* + * NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA + * + * This command is used to read FRL data based on need. + * + * nextSampleNumber + * This parameter returns the counter of next sample which is being filled. + * samples + * This parameter returns the frame time, render time, target time, client ID + * with one reserve bit for future use. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA (0x12fU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE 64U + +typedef struct NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE { + NvU16 frameTime; + NvU16 renderTime; + NvU16 targetTime; + NvU8 sleepTime; + NvU8 sampleNumber; +} NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE; + +#define NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID (0x2FU) + +typedef struct NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS { + NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE samples[NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE]; + NvU8 nextSampleNumber; +} NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA + * + * This command is used to write FRM data based on need. + * + * frameTime + * This parameter contains the frame time of current frame. + * renderTime + * This parameter contains the render time of current frame. + * targetTime + * This parameter contains the target time of current frame. + * sleepTime + * This parameter contains the sleep duration inserted by FRL for the latest frame. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA (0x132U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID (0x32U) + +typedef struct NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS { + NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE sampleData; +} NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO + * + * This command returns the current host driver, host OS and + * plugin information. It is only valid when VGX is setup. + * szHostDriverVersionBuffer + * This field returns the host driver version (NV_VERSION_STRING). + * szHostVersionBuffer + * This field returns the host driver version (NV_BUILD_BRANCH_VERSION). + * szHostTitleBuffer + * This field returns the host driver title (NV_DISPLAY_DRIVER_TITLE). + * szPluginTitleBuffer + * This field returns the plugin build title (NV_DISPLAY_DRIVER_TITLE). + * szHostUnameBuffer + * This field returns the call of 'uname' on the host OS. + * iHostChangelistNumber + * This field returns the changelist value of the host driver (NV_BUILD_CHANGELIST_NUM). + * iPluginChangelistNumber + * This field returns the changelist value of the plugin (NV_BUILD_CHANGELIST_NUM). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE 256U +#define NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO (0x133U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID (0x33U) + +typedef struct NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS { + char szHostDriverVersionBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; + char szHostVersionBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; + char szHostTitleBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; + char szPluginTitleBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; + char szHostUnameBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; + NvU32 iHostChangelistNumber; + NvU32 iPluginChangelistNumber; +} NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS + * + * This command returns the power status of the GPUs in the system, successfully attached or not because of + * insufficient power. It is supported on Kepler and up only. + * gpuCount + * This field returns the count into the following arrays. + * busNumber + * This field returns the busNumber of a GPU. + * gpuExternalPowerStatus + * This field returns the corresponding external power status: + * NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED + * NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS (0x134U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID (0x34U) + +typedef struct NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS { + NvU8 gpuCount; + NvU8 gpuBus[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; + NvU8 gpuExternalPowerStatus[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; +} NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS; + +/* Valid gpuExternalPowerStatus values */ +#define NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED 0U +#define NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED 1U + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS + * + * This command returns the caller's API access privileges using + * this client handle. + * + * privStatus + * This parameter returns a mask of possible access privileges: + * NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_PRIV_USER_FLAG + * The caller is running with elevated privileges + * NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_ROOT_HANDLE_FLAG + * Client is of NV01_ROOT class. + * NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG + * Client has PRIV bit set. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ + + +#define NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS (0x135U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID (0x35U) + +typedef struct NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS { + NvU8 privStatusFlags; +} NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS; + + +/* Valid privStatus values */ +#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_USER_FLAG (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_KERNEL_HANDLE_FLAG (0x00000002U) +#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG (0x00000004U) + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS + * + * The fabric manager (FM) notifies RM that fabric (system) is ready for peer to + * peer (P2P) use or still initializing the fabric. This command allows clients + * to query fabric status to allow P2P operations. + * + * Note, on systems where FM isn't used, RM just returns _SKIP. + * + * fabricStatus + * This parameter returns current fabric status: + * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP + * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED + * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS + * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_INVALID_PARAM_STRUCT + */ + +typedef enum NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS { + NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP = 1, + NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED = 2, + NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS = 3, + NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED = 4, +} NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS; + +#define NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS (0x136U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID (0x36U) + +typedef struct NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS { + NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS fabricStatus; +} NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS; + +/* + * NV0000_CTRL_VGPU_GET_VGPU_VERSION_INFO + * + * This command is used to query the range of VGX version supported. + * + * host_min_supported_version + * The minimum vGPU version supported by host driver + * host_max_supported_version + * The maximum vGPU version supported by host driver + * user_min_supported_version + * The minimum vGPU version set by user for vGPU support + * user_max_supported_version + * The maximum vGPU version set by user for vGPU support + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + */ +#define NV0000_CTRL_VGPU_GET_VGPU_VERSION (0x137U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID" */ + +/* + * NV0000_CTRL_VGPU_GET_VGPU_VERSION + */ +#define NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID (0x37U) + +typedef struct NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS { + NvU32 host_min_supported_version; + NvU32 host_max_supported_version; + NvU32 user_min_supported_version; + NvU32 user_max_supported_version; +} NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS; + +/* + * NV0000_CTRL_VGPU_SET_VGPU_VERSION + * + * This command is used to query whether pGPU is live migration capable or not. + * + * min_version + * The minimum vGPU version to be supported being set + * max_version + * The maximum vGPU version to be supported being set + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + */ +#define NV0000_CTRL_VGPU_SET_VGPU_VERSION (0x138U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID" */ + +/* + * NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS + */ +#define NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID (0x38U) + +typedef struct NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS { + NvU32 min_version; + NvU32 max_version; +} NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS; + +/* + * NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID + * + * This command is used to get a unique identifier for the instance of RM. + * The returned value will only change when the driver is reloaded. A previous + * value will never be reused on a given machine. + * + * rm_instance_id; + * The instance ID of the current RM instance + * + * Possible status values returned are: + * NV_OK + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_RM_INSTANCE_ID (0x139U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID" */ + +/* + * NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS + */ +#define NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID (0x39U) + +typedef struct NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS { + NV_DECLARE_ALIGNED(NvU64 rm_instance_id, 8); +} NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO + * + * This API is used to get the TPP(total processing power) and + * the rated TGP(total GPU power) from SBIOS. + * + * NVPCF is an acronym for Nvidia Platform Controllers and Framework + * which implements platform level policies. NVPCF is implemented in + * a kernel driver on windows. It is implemented in a user mode app + * called nvidia-powerd on Linux. + * + * Valid subFunc ids for NVPCF 1x include : + * NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED + * NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS + * + * Valid subFunc ids for NVPCF 2x include : + * NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED + * NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS + * NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CONFIG_TABLES + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO (0x13bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID" */ +#define NVPCF_CTRL_SYSPWRLIMIT_TYPE_BASE 1U +#define NV0000_CTRL_SYSTEM_POWER_INFO_INDEX_MAX_SIZE 32U + +#define NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT_MESSAGE_ID (0x48U) + +typedef struct NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT { + + /* Battery state of charge threshold (percent 0-100) */ + NvU8 batteryStateOfChargePercent; + + /* Long Timescale Battery current limit (milliamps) */ + NvU32 batteryCurrentLimitmA; + + /* Rest of system reserved power (milliwatts) */ + NvU32 restOfSytemReservedPowermW; + + /* Min CPU TDP (milliwatts) */ + NvU32 minCpuTdpmW; + + /* Max CPU TDP (milliwatts) */ + NvU32 maxCpuTdpmW; + + /* Short Timescale Battery current limit (milliamps) */ + NvU32 shortTimescaleBatteryCurrentLimitmA; +} NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT; + +/*! + * States for the Battery CPU TDP Control ability. + * _CPU_TDP_CONTROL_TYPE_DC_ONLY :==> Legacy setting for DC only CPU TDP Control + * _CPU_TDP_CONTROL_TYPE_DC_AC :==> AC and DC both support CPU TDP Control + */ +typedef enum QBOOST_CPU_TDP_CONTROL_TYPE { + QBOOST_CPU_TDP_CONTROL_TYPE_DC_ONLY = 0, + QBOOST_CPU_TDP_CONTROL_TYPE_DC_AC = 1, +} QBOOST_CPU_TDP_CONTROL_TYPE; + +#define NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID (0x3BU) + +typedef struct NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS { + /*Buffer to get all the supported functions*/ + NvU32 supportedFuncs; + + /* GPU ID */ + NvU32 gpuId; + + /* Total processing power including CPU and GPU */ + NvU32 tpp; + + /* Rated total GPU Power */ + NvU32 ratedTgp; + + /* NVPCF subfunction id */ + NvU32 subFunc; + + /* Configurable TGP offset, in mW */ + NvS32 ctgpOffsetmW; + + /* TPP, as offset in mW */ + NvS32 targetTppOffsetmW; + + /* Maximum allowed output, as offset in mW */ + NvS32 maxOutputOffsetmW; + + /* Minimum allowed output, as offset in mW */ + NvS32 minOutputOffsetmW; + + /* Configurable TGP offset, on battery, in milli-Watts. */ + NvS32 ctgpBattOffsetmW; + + /* Target total processing power on battery, offset, in milli-Watts. */ + NvS32 targetTppBattOffsetmW; + + /* + * Maximum allowed output on battery, offset, in milli-Watts. + */ + NvS32 maxOutputBattOffsetmW; + + /* + * Minimum allowed output on battery, offset, in milli-Watts. + */ + NvS32 minOutputBattOffsetmW; + + /* + * If value specified is larger than the statically assigned ROS reserve in + * the system power limits table, this will take affect. + * + * A value of zero naturally works as a clear as it will be lesser than the + * statically assigned value. + */ + NvU32 dcRosReserveOverridemW; + + /* + * This is the active arbitrated long timescale limit provided by Qboost and + * honored by JPAC/JPPC + */ + NvU32 dcTspLongTimescaleLimitmA; + + /* + * The long timescale limit override. + */ + NvU32 dcTspLongTimescaleLimitOverridemA; + + /* + * This is the active arbitrated short timescale limit provided by Qboost and + * honored by RM/PMU + */ + NvU32 dcTspShortTimescaleLimitmA; + + /* + * This is the value provided by the SBIOS to update the short timescale + * DC-TSP power policy managed by the PMU + */ + NvU32 dcTspShortTimescaleLimitOverridemA; + + /* Dynamic Boost AC support */ + NvBool bEnableForAC; + + /* Dynamic Boost DC support */ + NvBool bEnableForDC; + + /* The System Controller Table Version */ + NvU8 version; + + /* Base sampling period */ + NvU16 samplingPeriodmS; + + /* Sampling Multiplier */ + NvU16 samplingMulti; + + /* Fitler function type */ + NvU8 filterType; + + union { + + /* weight */ + NvU8 weight; + + /* windowSize */ + NvU8 windowSize; + } filterParam; + + /* Reserved */ + NvU16 filterReserved; + + /* Controller Type Dynamic Boost Controller */ + NvBool bIsBoostController; + + /* Increase power limit ratio */ + NvU16 incRatio; + + /* Decrease power limit ratio */ + NvU16 decRatio; + + /* Dynamic Boost Controller DC Support */ + NvBool bSupportBatt; + + /* CPU type(Intel/AMD) */ + NvU8 cpuType; + + /* GPU type(Nvidia) */ + NvU8 gpuType; + + /* System Power Table info index */ + NvU32 sysPwrIndex; + + /* System Power Table get table limits */ + NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT sysPwrGetInfo[NV0000_CTRL_SYSTEM_POWER_INFO_INDEX_MAX_SIZE]; + + /* + * Does this version of the system power limits table support TSP -> table + * version 2.0 and later should set this to true + */ + NvBool bIsTspSupported; + + /* + * Stores the System Power Limits (Battery State of Charge aka BSOC) table version implemented by the SBIOS + * + */ + NvU8 sysPwrLimitsTableVersion; + + /* SYSPWRLIMIT class types */ + NvU32 type; + + /* CPU TDP Limit to be set (milliwatts) */ + NvU32 cpuTdpmw; + + /* CPU TDP Control Support */ + QBOOST_CPU_TDP_CONTROL_TYPE cpuTdpControlType; +} NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS; + +/* Define the filter types */ +#define CONTROLLER_FILTER_TYPE_EMWA 0U +#define CONTROLLER_FILTER_TYPE_MOVING_MAX 1U + +/* Valid NVPCF subfunction case */ +#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED_CASE 0U +#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_CASE 1U +#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE 2U +#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_CASE 3U + +/* NVPCF subfunction to get the static data tables */ +#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CASE 4U + +/* NVPCF subfunction to get the system power limits table */ +#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DC_SYSTEM_POWER_LIMITS_CASE 5U + +/* NVPCF subfunction to change the CPU's TDP limit */ +#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_CPU_TDP_LIMIT_CONTROL_CASE 6U + +/* Valid NVPCF subfunction ids */ +#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED (0x00000000) +#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS (0x00000002) + +/* + * Defines for get supported sub functions bit fields + */ +#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED 0:0 +#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_YES 1 +#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_NO 0 +#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_DC_SYSTEM_POWER_LIMITS_IS_SUPPORTED 8:8 +#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_DC_SYSTEM_POWER_LIMITS_IS_SUPPORTED_YES 1 +#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_DC_SYSTEM_POWER_LIMITS_IS_SUPPORTED_NO 0 +#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_CPU_TDP_LIMIT_CONTROL_IS_SUPPORTED 9:9 +#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_CPU_TDP_LIMIT_CONTROL_IS_SUPPORTED_YES 1 +#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_CPU_TDP_LIMIT_CONTROL_IS_SUPPORTED_NO 0 + + +/*! + * Config DSM 2x version specific defines + */ +#define NVPCF0100_CTRL_CONFIG_DSM_2X_VERSION (0x00000200) +#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED (0x00000000) +#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CONFIG_TABLES (0x00000001) +#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS (0x00000002) +#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DC_SYSTEM_POWER_LIMITS_TABLE (0x00000008) +#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_CPU_TDP_LIMIT_CONTROL (0x00000009) + +/*! + * Defines the max buffer size for config + */ +#define NVPCF0100_CTRL_CONFIG_2X_BUFF_SIZE_MAX (255) + +/* + * NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT + * + * This API is used to sync the external fabric management status with + * GSP-RM + * + * bExternalFabricMgmt + * Whether fabric is externally managed + * + * Possible status values returned are: + * NV_OK + */ +#define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT (0x13cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID (0x3CU) + +typedef struct NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS { + NvBool bExternalFabricMgmt; +} NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS; + +/* + * NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO + * + * This API is used to get information about the RM client + * database. + * + * clientCount [OUT] + * This field indicates the number of clients currently allocated. + * + * resourceCount [OUT] + * This field indicates the number of resources currently allocated + * across all clients. + * + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_CLIENT_DATABASE_INFO (0x13dU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID (0x3DU) + +typedef struct NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS { + NvU32 clientCount; + NV_DECLARE_ALIGNED(NvU64 resourceCount, 8); +} NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 + * + * This command returns the current driver information in + * statically sized character arrays. + * + * driverVersionBuffer + * This field returns the version (NV_VERSION_STRING). + * versionBuffer + * This field returns the version (NV_BUILD_BRANCH_VERSION). + * driverBranch + * This field returns the branch (NV_BUILD_BRANCH). + * titleBuffer + * This field returns the title (NV_DISPLAY_DRIVER_TITLE). + * changelistNumber + * This field returns the changelist value (NV_BUILD_CHANGELIST_NUM). + * officialChangelistNumber + * This field returns the last official changelist value + * (NV_LAST_OFFICIAL_CHANGELIST_NUM). + * + * Possible status values returned are: + * NV_OK + */ + +#define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE 256U +#define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 (0x13eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID (0x3EU) + +typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS { + char driverVersionBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; + char versionBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; + char driverBranch[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; + char titleBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; + NvU32 changelistNumber; + NvU32 officialChangelistNumber; +} NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL + * + * This API is used to get/set RMCTRL cache mode + * + * cmd [IN] + * GET - Gets RMCTRL cache mode + * SET - Sets RMCTRL cache mode + * + * mode [IN/OUT] + * On GET, this field is the output of current RMCTRL cache mode + * On SET, this field indicates the mode to set RMCTRL cache to + * Valid values for this parameter are: + * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE + * No get/set action to cache. + * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE + * Try to get from cache at the beginning of the control. + * Set cache after control finished if the control has not been cached. + * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY + * Do not get from cache. Set cache when control call finished. + * When setting the cache, verify the value in the cache is the same + * with the current control value if the control is already cached. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL (0x13fU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID (0x3FU) + +typedef struct NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS { + NvU32 cmd; + NvU32 mode; +} NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS; + +#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_GET (0x00000000U) +#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_SET (0x00000001U) + +#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE (0x00000000U) +#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE (0x00000001U) +#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY (0x00000002U) + +/* + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL + * + * This command is used to control PFM_REQ_HNDLR functionality. It allows control of + * GPU Performance Scaling (PFM_REQ_HNDLR), changing its operational parameters and read + * most PFM_REQ_HNDLR dynamic parameters. + * + * command + * This parameter specifies the command to execute. Invalid commands + * result in the return of an NV_ERR_INVALID_ARGUMENT status. + * locale + * This parameter indicates the specific locale to which the command + * 'command' is to be applied. +* Supported range of CPU/GPU {i = 0, ..., 255} + * data + * This parameter contains a command-specific data payload. It can + * be used to input data as well as output data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_COMMAND + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_DATA + * NV_ERR_INVALID_REQUEST + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL (0x140U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID (0x40U) + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS { + NvU16 command; + NvU16 locale; + NvU32 data; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS; + +/* + * Valid command values : + * + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT + * Is used to check if PFM_REQ_HNDLR was correctly initialized. + * Possible return (OUT) values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC + * Are used to stop/start PFM_REQ_HNDLR functionality and to get current status. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS + * Are used to control execution of PFM_REQ_HNDLR actions and to get current status. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC + * Are used to switch current PFM_REQ_HNDLR logic and to retrieve current logic. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF + * Will cause that all PFM_REQ_HNDLR actions will be NULL. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY + * Fuzzy logic will determine PFM_REQ_HNDLR actions based on current ruleset. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC + * Deterministic logic will define PFM_REQ_HNDLR actions based on current ruleset. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE + * Are used to set/retrieve system control preference. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT + * Are used to set/retrieve GPU2CPU pstate limits. + * IN/OUT values are four bytes packed into a 32-bit data field. + * The CPU cap index for GPU pstate 0 is in the lowest byte, the CPU cap + * index for the GPU pstate 3 is in the highest byte, etc. One + * special value is to disable the override to the GPU2CPU map: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE + * Is used to stop/start PFM_REQ_HNDLR PMU functionality. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE + * Is used to get the current status of PMU PFM_REQ_HNDLR. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER + * Are used to set/retrieve max power [mW] that system can provide. + * This is hardcoded PFM_REQ_HNDLR safety feature and logic/rules does not apply + * to this threshold. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET + * Are used to set/retrieve current system cooling budget [mW]. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD + * Are used to set/retrieve integration interval [sec]. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT + * Are used to set/retrieve used ruleset [#]. Value is checked + * against MAX number of rules for currently used PFM_REQ_HNDLR logic. Also COUNT + * provides a way to find out how many rules exist for the current control + * system. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST + * Is used to set/get a delay relative to now during which to allow unbound + * CPU performance. Units are seconds. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE + * Is used to override/get the actual power supply mode (AC/Battery). + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO + * Is used to get the Ventura system information for VCT tool + * Returned 32bit value should be treated as bitmask and decoded in + * following way: + * Encoding details are defined in objPFM_REQ_HNDLR.h refer to + * NV_PFM_REQ_HNDLR_SYS_SUPPORT_INFO and corresponding bit defines. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTION + * Is used to get the supported sub-functions defined in SBIOS. Returned + * value is a bitmask where each bit corresponds to different function: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE + * Are used to retrieve appropriate power measurements and their derivatives + * in [mW] for required locale. _BURDEN is defined only for _LOCALE_SYSTEM. + * _INTERMEDIATE is not defined for _LOCALE_SYSTEM, and takes an In value as + * index. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS + * Is used to retrieve parameters when adjusting raw sensor power reading. + * The values may come from SBIOS, VBIOS, registry or driver default. + * Possible IN value is the index of interested parameter. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE + * Are used to retrieve appropriate temperature measurements and their + * derivatives in [1/1000 Celsius]. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX + * Are used to retrieve CPU(x)/GPU(x) p-state or it's limits. + * Not applicable to _LOCALE_SYSTEM. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION + * Is used to retrieve last PFM_REQ_HNDLR action for given domain. + * Not applicable to _LOCALE_SYSTEM. + * Possible return (OUT) values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0 + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1 + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1 + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2 + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE + * Is used to set the power sensor simulator state. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE + * Is used to get the power simulator sensor simulator state. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA + * Is used to set power sensor simulator data + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA + * Is used to get power sensor simulator data + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK + * Is used to respond to the ACPI event triggered by SBIOS. RM will + * request value for budget and status, validate them, apply them + * and send ACK back to SBIOS. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT + * Is a test cmd that should notify SBIOS to send ACPI event requesting + * budget and status change. + */ +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_INVALID (0xFFFFU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT (0x0000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC (0x0001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC (0x0002U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS (0x0003U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS (0x0004U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC (0x0005U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC (0x0006U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE (0x0007U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE (0x0008U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT (0x0009U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT (0x000AU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE (0x000BU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE (0x000CU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER (0x0100U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER (0x0101U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET (0x0102U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET (0x0103U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD (0x0104U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD (0x0105U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET (0x0106U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET (0x0107U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT (0x0108U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST (0x0109U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST (0x010AU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE (0x010BU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE (0x010CU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO (0x010DU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTIONS (0x010EU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER (0x0200U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA (0x0201U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE (0x0202U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG (0x0203U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL (0x0204U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN (0x0205U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE (0x0206U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS (0x0210U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP (0x0220U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA (0x0221U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE (0x0222U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE (0x0240U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP (0x0241U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN (0x0242U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX (0x0243U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION (0x0244U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_SLFM_PRESENT (0x0245U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE (0x0250U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE (0x0251U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA (0x0252U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA (0x0253U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK (0x0320U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT (0x0321U) + +/* valid LOCALE values */ +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_INVALID (0xFFFFU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_SYSTEM (0x0000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_CPU(i) (0x0100+((i)%0x100)) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_GPU(i) (0x0200+((i)%0x100)) + +/* valid data values for enums */ +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID (0x80000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE (0xFFFFFFFFU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_ON (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS (0x00000004U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC (0x00000008U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC (0x00000010U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB (0x00000020U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS (0x00000040U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0 (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1 (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT (0x00000003U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1 (0x00000004U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2 (0x00000005U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM (0x00000006U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM (0x00000007U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_NO (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_YES (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_ON (0x00000001U) + +/* + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL + * + * This command allows execution of multiple PFM_REQ_HNDLRControl commands within one + * RmControl call. For practical reasons # of commands is limited to 16. + * This command shares defines with NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL. + * + * cmdCount + * Number of commands that should be executed. + * Less or equal to NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX. + * + * succeeded + * Number of commands that were succesully executed. + * Less or equal to NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX. + * Failing commands return NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID + * in their data field. + * + * cmdData + * Array of commands with following structure: + * command + * This parameter specifies the command to execute. + * Invalid commands result in the return of an + * NV_ERR_INVALID_ARGUMENT status. + * locale + * This parameter indicates the specific locale to which + * the command 'command' is to be applied. + * Supported range of CPU/GPU {i = 0, ..., 255} + * data + * This parameter contains a command-specific data payload. + * It is used both to input data as well as to output data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL (0x141U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX (16U) +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID (0x41U) + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS { + NvU32 cmdCount; + NvU32 succeeded; + + struct { + NvU16 command; + NvU16 locale; + NvU32 data; + } cmdData[NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX]; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL + * + * This command is used to execute general PFM_REQ_HNDLR Functions, most dealing with + * calling SBIOS, or retrieving cached sensor and PFM_REQ_HNDLR state data. + * + * version + * This parameter specifies the version of the interface. Legal values + * for this parameter are 1. + * cmd + * This parameter specifies the PFM_REQ_HNDLR API to be invoked. + * Valid values for this parameter are: + * NV0000_CTRL_PFM_REQ_HNDLR_CMD_GET_THERM_LIMIT + * This command gets the temperature limit for thermal controller. When + * this command is specified the input parameter contains ???. + * NV0000_CTRL_PFM_REQ_HNDLR_CMD_SET_THERM_LIMIT + * This command set the temperature limit for thermal controller. When + * this command is specified the input parameter contains ???. + * input + * This parameter specifies the cmd-specific input value. + * result + * This parameter returns the cmd-specific output value. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL (0x142U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID (0x42U) + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS { + NvU32 cmd; + NvS32 input[2]; + NvS32 result[4]; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS; + +/* valid version values */ +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_PSP_CURRENT_VERSION (0x00010000U) + +/* valid cmd values */ +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_THERM_LIMIT (0x00000002U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_THERMAL_LIMIT (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MIN_LIMIT (0x00000001U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MAX_LIMIT (0x00000002U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE (0x00000003U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_THERM_LIMIT (0x00000003U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_THERMAL_LIMIT (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA (0x00000004U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DOWN_N_DELTA (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA (0x00000005U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DOWN_N_DELTA (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA (0x00000006U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_HOLD_DELTA (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA (0x00000007U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_HOLD_DELTA (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA (0x00000008U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_UP_DELTA (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA (0x00000009U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_UP_DELTA (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA (0x0000000AU) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_ENGAGE_DELTA (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA (0x0000000BU) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_ENGAGE_DELTA (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000CU) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000DU) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_STATUS (0x00000016U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_STATUS (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_STATUS (0x00000017U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_STATUS (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM (0x00000018U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_CPU_SET_UTIL_AVG_NUM (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM (0x00000019U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_CPU_GET_UTIL_AVG_NUM (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PERF_SENSOR (0x0000001AU) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_NEXT_EXPECTED_POLL (0x00000001U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_VALUE (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_AVAILABLE (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_CALL_ACPI (0x0000001BU) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_CMD (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_PARAM_IN (0x00000001U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_1 (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_2 (0x00000001U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_STATUS (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_VERSION (0x00000001U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_SZ (0x00000002U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_SZ (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_COUNT (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_IGPU_TURBO (0x0000001CU) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SET_IGPU_TURBO (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERIOD (0x00000026U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERIOD (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERIOD (0x00000027U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERIOD (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_NUDGE_FACTOR (0x00000028U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_UP (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_DOWN (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_NUDGE_FACTOR (0x00000029U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_UP (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_DOWN (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES (0x0000002AU) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES (0x0000002BU) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERF_LIMITS (0x0000002CU) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_UPPER (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_LOWER (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERF_LIMITS (0x0000002DU) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_UPPER (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_LOWER (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PM1_AVAILABLE (0x0000002EU) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_PM1_AVAILABLE (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PM1_AVAILABLE (0x0000002FU) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_PM1_AVAILABLE (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS (0x00000044U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS (0x00000045U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT (0x00000046U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ (0000000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT (0x00000047U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ (0000000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM (0x00000048U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_INDEX (0000000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_AVAILABLE_MASK (0000000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM (0x00000049U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX (0000000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX_MAX (2U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX 7:0 +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_MAXPERF (0U) +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_BALANCED (1U) +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_QUIET (2U) +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID (0xFFU) +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK 15:8 +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK_INVALID (0U) + +/* valid PS_STATUS result values */ +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_OFF (0U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_ON (1U) + +#define PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK 32U +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS { + NvU32 objHndl; + NvU32 blockId; + NvU32 nextExpectedSampleTimems; + NvU32 countersReq; + NvU32 countersReturned; + NvU32 counterBlock[PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK]; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS; + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS (0x146U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS_MESSAGE_ID (0x46U) + +typedef NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS; + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS (0x147U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID (0x47U) + +typedef NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI + * + * This command allows users to call PFM_REQ_HNDLR ACPI commands for testing purposes. + * + * cmd + * This parameter specifies the PFM_REQ_HNDLR ACPI command to execute. + * + * input + * This parameter specified the cmd-dependent input value. + * + * resultSz + * This parameter returns the size (in bytes) of the valid data + * returned in the result parameter. + * + * result + * This parameter returns the results of the specified cmd. + * The maximum size (in bytes) of this returned data will + * not exceed PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE + * + * PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE + * The size of buffer (result) in unit of NvU32. + * The smallest value is sizeof(PSS_ENTRY)*ACPI_PSS_ENTRY_MAX. + * Since the prior one is 24 bytes, and the later one is 48, + * this value cannot be smaller than 288. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT, + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_PERMISSIONS + * + */ +#define PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID (0x43U) + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS { + NvU32 cmd; + NvU32 input; + NvU32 resultSz; + NvU32 result[PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE]; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS; + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI (0x143U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PFM_REQ_HNDLR (0x00008000U) + +/* + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA + * + * This command is used to read FRL data based on need. + * + * nextSampleNumber + * This parameter returns the counter of next sample which is being filled. + * samples + * This parameter returns the frame time, render time, target time, client ID + * with one reserve bit for future use. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA (0x144U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE 64U + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE { + NvU16 frameTime; + NvU16 renderTime; + NvU16 targetTime; + NvU8 sleepTime; + NvU8 sampleNumber; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE; + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID (0x44U) + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS { + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE samples[NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE]; + NvU8 nextSampleNumber; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA + * + * This command is used to write FRM data based on need. + * + * frameTime + * This parameter contains the frame time of current frame. + * renderTime + * This parameter contains the render time of current frame. + * targetTime + * This parameter contains the target time of current frame. + * sleepTime + * This parameter contains the sleep duration inserted by FRL for the latest frame. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA (0x145U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID (0x45U) + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS { + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE sampleData; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_READ_CPER + * + * This command is used to pull CPER logs from RM. + * + * cperTypeMask [IN] + * Types of records to access. Bitmask of READ_CPER_ACCESS_TYPE values. + * uuid [IN] + * UUID of target to pull records for. Set to 0 to pull records for all UUIDs. + * cperCursor [IN/OUT] + * Opaque handle used to sequentially pull CPER records + * buffer [OUT] + * Buffer to be filled in. + * bufferSize [IN/OUT] + * Size of buffer. Returning 0 to user indicates no buffer was found. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_SYSTEM_READ_CPER (0x149U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_READ_CPER_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_READ_CPER_ACCESS_TYPE_GPU (1U) + +#define READ_CPER_BUFFER_SIZE 1024U + +#define NV0000_CTRL_SYSTEM_READ_CPER_PARAMS_MESSAGE_ID (0x49U) + +typedef struct NV0000_CTRL_SYSTEM_READ_CPER_PARAMS { + NV_DECLARE_ALIGNED(NvU64 cperTypeMask, 8); + NvU8 uuid[16]; + NvU32 cperCursor; + NvU8 buffer[READ_CPER_BUFFER_SIZE]; + NvU32 bufferSize; +} NV0000_CTRL_SYSTEM_READ_CPER_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_SOC_SET_PERF_LIMITS + * + * This command sets lower and/or upper bounds for a display clock (dispclk or + * hubclk), or for the memory perf level. When this API is called, the system + * will immediately attempt to switch the clock or perf level to a value that + * meets the specified condition(s). + * + * For both clock and perf level, if no lower limit is desired, the "min" input + * should be set to zero. For a clock, if no upper limit is desired, the "max" + * input should be set to NV_U32_MAX. For a perf level, an upper limit is not + * currently supported, and the "max" input must be set to NV_U32_MAX. + * + * Any perf limit set through this API will remain in effect until it is updated + * or cancelled by a subsequent call to this API. A perf limit may be + * cancelled by setting the "min" value to NV_U32_MIN (0) and the "max" value + * (for clocks) to NV_U32_MAX. Only one perf limit may be in effect for a + * given clientUsageId and resource at any given time. + * + * At any given time, multiple perf limits (with different clientUsageIds) may + * be in effect for a given clock or perf level, and that clock or perf level + * will be set to a value that meets the requirements of all active perf + * limits. If there is a conflict between perf limits, the conflict will be + * resolved by the perf limit(s) with the higher priority. + * + * For example, suppose the API is called with the following parameters: + * clientUsageId = NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_ID_MODS + * bwResource = NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_BW_RESOURCE_DISPCLK + * minLevelOrFreqKHz = 800000 + * maxLevelOrFreqKHz = 800000 + * This will set dispclk to 800 MHz (or possibly a slightly higher frequency, + * if the clock dividers do not allow 800 MHz to be set exactly). + * + * Then suppose this call is made: + * clientUsageId = NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_ID_ISMODEPOSSIBLE + * bwResource = NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_BW_RESOURCE_DISPCLK + * minLevelOrFreqKHz = 1000000 + * maxLevelOrFreqKHz = 0xFFFFFFFF + * After this call, dispclk will remain set to 800 MHz, because, although the + * min frequency was requested to be at least 1 GHz, this would conflict with + * the "maxLevelOrFreqKHz = 800000" value set in the previous call, which is + * still in effect. The previous call takes priority because + * NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_ID_MODS has higher priority than + * NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_ID_ISMODEPOSSIBLE. + * + * Then suppose this call is made: + * clientUsageId = NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_ID_MODS + * bwResource = NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_BW_RESOURCE_DISPCLK + * minLevelOrFreqKHz = 0 + * maxLevelOrFreqKHz = 0xFFFFFFFF + * This removes the NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_ID_MODS perf + * limit. At this point, dispclk will be set to 1 GHz, in accordance with the + * NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_ID_ISMODEPOSSIBLE perf limit, + * which is still in effect. (The remaining perf limit allows the clock to be + * higher than 1 GHz, but in practice, the clock will generally be set to the + * lowest frequency that meets the perf limit requirement, to save power. For + * perf level, perf monitors (which do not use the perf limit mechanism) may + * force a higher value in order to meet performance needs.) + * + * This API takes an array of perf limit structures, so multiple perf limits + * may be set within the same call. + * + * This API is primarily intended for use on SOC products, where display is + * separate from the GPU. On dGPU products, this API may not be supported; + * instead, NV2080_CTRL_CMD_PERF_LIMITS_SET_STATUS_V2 may be used to set perf + * limits. + * + * numLimits (in) + * This is the number of perf limits with lower and/or upper limits to + * apply. + * + * bWaitForCompletion (in) + * It is possible that a perf change or clock change may take some time to + * execute. If this flag is set, the API will wait for all of the changes + * to complete before returning. (However, it will not wait for completion + * of any operation that is blocked by a higher priority perf limit.) + * + * clientUsageId (in) + * This is a NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_ID_xxx value indicating + * who the client is, and/or the purpose of the perf limit. It is used to + * establish priority between conflicting perf limits. + * + * bwResource (in) + * This is a NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_BW_RESOURCE_xxx value + * indicating which clock, or memory perf level, is to have limits applied. + * + * minLevelOrFreqKHz (in) + * maxLevelOrFreqKHz (in) + * If bwResource is + * NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_BW_RESOURCE_PERF_LEVEL, then + * minLevelOrFreqKHz specifies the zero-based index of the minimum perf + * level to allow. maxLevelOrFreqKHz should be set to NV_U32_MAX. + * + * If bwResource specifies a clock + * (NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_BW_RESOURCE_DISPCLK or + * NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_BW_RESOURCE_HUBCLK), then + * minLevelOrFreqKHz and maxLevelOrFreqKHz specify the lower and upper + * limits (respectively) for the specified clock's frequency. + */ +#define NV0000_CTRL_CMD_SYSTEM_SOC_SET_PERF_LIMITS (0x150U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMITS_PARAMS_MESSAGE_ID" */ + +/* valid clientUsageId values */ +#define NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_ID_TEST_PERF_LEVELS (0U) +#define NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_ID_ISMODEPOSSIBLE (1U) +#define NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_ID_MCLK_SWITCH (2U) +#define NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_ID_MODS (3U) + +/* valid bwResource values */ +#define NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_BW_RESOURCE_PERF_LEVEL (0U) +#define NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_BW_RESOURCE_DISPCLK (1U) +#define NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_BW_RESOURCE_HUBCLK (2U) + +/* Define a structure for a single perf limit */ +typedef struct NV0000_CTRL_SYSTEM_SOC_PERF_LIMIT { + NvU32 minLevelOrFreqKHz; + NvU32 maxLevelOrFreqKHz; + NvU8 clientUsageId; + NvU8 bwResource; +} NV0000_CTRL_SYSTEM_SOC_PERF_LIMIT; + +/* Maximum number of limits that can be set in a single call */ +#define NV0000_CTRL_SYSTEM_SOC_PERF_MAX_LIMITS (16U) + +#define NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMITS_PARAMS_MESSAGE_ID (0x150U) + +typedef struct NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMITS_PARAMS { + NvU32 numLimits; + NV0000_CTRL_SYSTEM_SOC_PERF_LIMIT limits[NV0000_CTRL_SYSTEM_SOC_PERF_MAX_LIMITS]; + NvBool bWaitForCompletion; +} NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMITS_PARAMS; + +/* _ctrl0000system_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000unix.h b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000unix.h new file mode 100644 index 0000000..7400a69 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000unix.h @@ -0,0 +1,468 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000unix.finn +// + +#include "ctrl0000gpu.h" +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +/* NV01_ROOT (client) Linux control commands and parameters */ + +/* + * NV0000_CTRL_CMD_OS_UNIX_FLUSH_USER_CACHE + * + * This command may be used to force a cache flush for a range of virtual addresses in + * memory. Can be used for either user or kernel addresses. + * + * offset, length + * These parameters specify the offset within the memory block + * and the number of bytes to flush/invalidate + * cacheOps + * This parameter flags whether to flush, invalidate or do both. + * Possible values are: + * NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH + * NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_INVALIDATE + * NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH_INVALIDATE + * hDevice + * This parameter is the handle to the device + * hObject + * This parameter is the handle to the memory structure being operated on. + * internalOnly + * Intended for internal use unless client is running in MODS UNIX environment, + * in which case this parameter specify the virtual address of the memory block + * to flush. + * + * Possible status values are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_COMMAND + * NV_ERR_INVALID_LIMIT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_OS_UNIX_FLUSH_USER_CACHE (0x3d02) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 length, 8); + NvU32 cacheOps; + NvHandle hDevice; + NvHandle hObject; + NV_DECLARE_ALIGNED(NvU64 internalOnly, 8); +} NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS; + +#define NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH (0x00000001) +#define NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_INVALIDATE (0x00000002) +#define NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH_INVALIDATE (0x00000003) + + +/* + * NV0000_CTRL_CMD_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR + * + * This command is used to get the control file descriptor. + * + * Possible status values returned are: + * NV_OK + * + */ +#define NV0000_CTRL_CMD_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR (0x3d04) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | 0x4" */ + +typedef struct NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS { + NvS32 fd; +} NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS; + +typedef enum NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE { + NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_NONE = 0, + NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM = 1, +} NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE; + +typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECT { + NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE type; + + union { + struct { + NvHandle hDevice; + NvHandle hParent; + NvHandle hObject; + } rmObject; + } data; +} NV0000_CTRL_OS_UNIX_EXPORT_OBJECT; + +/* + * NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD + * + * This command may be used to export NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE + * object to file descriptor. + * + * Note that the 'fd' parameter is an input parameter at the kernel level, but + * an output parameter for usermode RMAPI clients -- the RMAPI library will + * open a new FD automatically if a usermode RMAPI client exports an object. + * + * Kernel-mode RM clients can export an object to an FD in two steps: + * 1. User client calls this RMControl with the flag 'EMPTY_FD_TRUE' to create + * an empty FD to receive the object, then passes that FD to the kernel-mode + * RM client. + * 2. Kernel-mode RM client fills in the rest of the + * NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS as usual and calls RM to + * associate its desired RM object with the empty FD from its usermode + * client. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_PARAMETER + */ +#define NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD (0x3d05) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS { + NV0000_CTRL_OS_UNIX_EXPORT_OBJECT object; /* IN */ + NvS32 fd; /* IN/OUT */ + NvU32 flags; /* IN */ +} NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS; + +/* + * If EMPTY_FD is TRUE, the 'fd' will be created but no object will be + * associated with it. The hDevice parameter is still required, to determine + * the correct device node on which to create the file descriptor. + * (An empty FD can then be passed to a kernel-mode driver to associate it with + * an actual object.) + */ +#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD 0:0 +#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_FALSE (0x00000000) +#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_TRUE (0x00000001) + +/* + * NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD + * + * This command may be used to import back + * NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE object from file descriptor. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_PARAMETER + */ +#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD (0x3d06) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS { + NvS32 fd; /* IN */ + NV0000_CTRL_OS_UNIX_EXPORT_OBJECT object; /* IN */ +} NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS; + +/* + * NV0000_CTRL_CMD_OS_GET_GPU_INFO + * + * This command will query the OS specific info for the specified GPU. + * + * gpuId + * This parameter should specify a valid GPU ID value. If there + * is no GPU present with the specified ID, a status of + * NV_ERR_INVALID_ARGUMENT is returned. + * minorNum + * This parameter returns minor number of device node. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_OS_GET_GPU_INFO (0x3d07) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | 0x7" */ + +typedef struct NV0000_CTRL_OS_GET_GPU_INFO_PARAMS { + NvU32 gpuId; /* IN */ + NvU32 minorNum; /* OUT */ +} NV0000_CTRL_OS_GET_GPU_INFO_PARAMS; + +/* + * NV0000_CTRL_CMD_OS_UNIX_GET_EXPORT_OBJECT_INFO + * + * This command will query the deviceInstance for the specified FD + * which is referencing an exported object. + * + * fd + * File descriptor parameter is referencing an exported object on a Unix system. + * + * deviceInstatnce + * This parameter returns a deviceInstance on which the object is located. + * + * NV_MAX_DEVICES is returned if the object is parented by a client instead + * of a device. + * + * gpuInstanceId + * For objects parented by device this parameter returns MIG GPU instance + * id the device is subscribed to or NV_U32_MAX if no subscription was made. + * + * maxObjects + * This parameter returns the maximum number of object handles that may be + * contained in the file descriptor. + * + * metadata + * This parameter returns the user metadata passed into the + * _EXPORT_OBJECTS_TO_FD control call. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OBJECT_NOT_FOUND + */ + +#define NV0000_CTRL_CMD_OS_UNIX_GET_EXPORT_OBJECT_INFO (0x3d08) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE 64 + +#define NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS { + NvS32 fd; /* IN */ + NvU32 deviceInstance; /* OUT */ + NvU32 gpuInstanceId; /* OUT */ + NvU16 maxObjects; /* OUT */ + NvU8 metadata[NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE]; /* OUT */ +} NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS; + +/* + * NV0000_CTRL_CMD_OS_UNIX_REFRESH_RMAPI_DEVICE_LIST + * + * This command will re-fetch probed GPUs information and update RMAPI library's + * internal detected GPU context information accordingly. Without this, GPUs + * attached to RM after RMAPI client initialization will not be accessible and + * all RMAPI library calls will fail on them. + * Currently this is used by NVSwitch Fabric Manager in conjunction with NVSwitch + * Shared Virtualization feature where GPUs are hot-plugged to OS/RM (by Hypervisor) + * and Fabric Manager is signaled externally by the Hypervisor to initialize those GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_OPERATING_SYSTEM + */ + +#define NV0000_CTRL_CMD_OS_UNIX_REFRESH_RMAPI_DEVICE_LIST (0x3d09) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | 0x9" */ + +/* + * This control call has been deprecated. It will be deleted soon. + * Use NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD (singular) or + * NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD (plural) instead. + */ +#define NV0000_CTRL_CMD_OS_UNIX_CREATE_EXPORT_OBJECT_FD (0x3d0a) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_BUFFER_SIZE NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE + +#define NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS { + NvHandle hDevice; /* IN */ + NvU16 maxObjects; /* IN */ + NvU8 metadata[NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_BUFFER_SIZE]; /* IN */ + NvS32 fd; /* IN/OUT */ +} NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS; + +/* + * NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD + * + * Exports RM handles to an fd that was provided, also creates an FD if + * requested. + * + * The objects in the 'handles' array are exported into the fd + * as the range [index, index + numObjects). + * + * If index + numObjects is greater than the maxObjects value used + * to create the file descriptor, NV_ERR_INVALID_PARAMETER is returned. + * + * If 'numObjects and 'index' overlap with a prior call, the newer call's RM object + * handles will overwrite the previously exported handles from the previous call. + * This overlapping behavior can also be used to unexport a handle by setting + * the appropriate object in 'objects' to 0. + * + * fd + * A file descriptor. If -1, a new FD will be created. + * + * hDevice + * The owning device of the objects to be exported (must be the same for + * all objects). + * + * maxObjects + * The total number of objects that the client wishes to export to the FD. + * This parameter will be honored only when the FD is getting created. + * + * metadata + * A buffer for clients to write some metadata to and pass to the importing + * client. This parameter will be honored only when the FD is getting + * created. + * + * objects + * Array of RM object handles to export to the fd. + * + * numObjects + * The number of handles the user wishes to export in this call. + * + * index + * The index into the export fd at which to start exporting the handles in + * 'objects' (for use in iterative calls). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OUT_OF_RANGE + * NV_ERR_NOT_SUPPORTED + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_OBJECT_HANDLE + */ +#define NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD (0x3d0b) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_MAX_OBJECTS 512 + +#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS { + NvS32 fd; /* IN/OUT */ + NvHandle hDevice; /* IN */ + NvU16 maxObjects; /* IN */ + NvU8 metadata[NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE]; /* IN */ + NvHandle objects[NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_MAX_OBJECTS]; /* IN */ + NvU16 numObjects; /* IN */ + NvU16 index; /* IN */ +} NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS; + +/* + * NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECTS_FROM_FD + * + * This command can be used to import back RM handles + * that were exported to an fd using the + * NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD control call. + * + * If index + numObjects is greater than the maxObjects value used + * to create the file descriptor, NV_ERR_INVALID_PARAMETER is returned + * and no objects are imported. + * + * For each valid handle in the 'objects' array parameter at index 'i', + * the corresponding object handle at index ('i' + 'index') contained by + * the fd will be imported. If the object at index ('i' + 'index') has + * not been exported into the fd, no object will be imported. + * + * If any of handles contained in the 'objects' array parameter are invalid + * and the corresponding export object handle is valid, + * NV_ERR_INVALID_PARAMETER will be returned and no handles will be imported. + * + * fd + * The export fd on which to import handles out of. + * + * hParent + * The parent RM handle of which all of the exported objects will + * be duped under. + * + * objects + * An array of RM handles. The exported objects will be duped under + * these handles during the import process. + * + * objectTypes + * An array of RM handle types. The type _NONE will be returned if + * the object was not imported. Other possible object types are + * mentioned below. + * + * numObjects + * The number of valid object handles in the 'objects' array. This should + * be set to the number of objects that the client wishes to import. + * + * index + * The index into the fd in which to start importing from. For + * use in iterative calls. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OUT_OF_RANGE + * NV_ERR_NOT_SUPPORTED + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_PARAMETER + */ +#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECTS_FROM_FD (0x3d0c) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID" */ + +// +// TODO Bump this back up to 512 after the FLA revamp is complete +// +#define NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS 128 + +#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_NONE 0 +#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_VIDMEM 1 +#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_SYSMEM 2 +#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC 3 +#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC_MC 4 + +#define NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS { + NvS32 fd; /* IN */ + NvHandle hParent; /* IN */ + NvHandle objects[NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS]; /* IN */ + NvU8 objectTypes[NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS]; /* OUT */ + NvU16 numObjects; /* IN */ + NvU16 index; /* IN */ +} NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS; + +#define NV0000_CTRL_OS_UNIX_MEMACCT_SET_LIMITS_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV0000_CTRL_OS_UNIX_MEMACCT_SET_LIMITS_PARAMS { + NvS32 cgroupFd; + NvU32 gpuId; + NV_DECLARE_ALIGNED(NvU64 softLimit, 8); + NV_DECLARE_ALIGNED(NvU64 hardLimit, 8); +} NV0000_CTRL_OS_UNIX_MEMACCT_SET_LIMITS_PARAMS; + +#define NV0000_CTRL_OS_UNIX_CMD_MEMACCT_SET_LIMITS (0x3d0d) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_MEMACCT_SET_LIMITS_PARAMS_MESSAGE_ID" */ + +typedef struct NV0000_CTRL_OS_UNIX_MEMACCT_LIMITS { + NvU32 gpuId; + NV_DECLARE_ALIGNED(NvU64 soft, 8); + NV_DECLARE_ALIGNED(NvU64 hard, 8); + NV_DECLARE_ALIGNED(NvU64 current, 8); +} NV0000_CTRL_OS_UNIX_MEMACCT_LIMITS; + +#define NV0000_CTRL_OS_UNIX_MEMACCT_GET_LIMITS_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV0000_CTRL_OS_UNIX_MEMACCT_GET_LIMITS_PARAMS { + NvS32 cgroupFd; + NvU32 count; + NV_DECLARE_ALIGNED(NV0000_CTRL_OS_UNIX_MEMACCT_LIMITS limits[NV0000_CTRL_GPU_MAX_ATTACHED_GPUS], 8); +} NV0000_CTRL_OS_UNIX_MEMACCT_GET_LIMITS_PARAMS; + +#define NV0000_CTRL_OS_UNIX_CMD_MEMACCT_GET_LIMITS (0x3d0e) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_MEMACCT_GET_LIMITS_PARAMS_MESSAGE_ID" */ + +/* _ctrl0000unix_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000vgpu.h b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000vgpu.h new file mode 100644 index 0000000..412559c --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0000/ctrl0000vgpu.h @@ -0,0 +1,224 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000vgpu.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrla081.h" +#include "class/cl0000.h" +#include "nv_vgpu_types.h" + +/* DRF macros for OBJGPU::gpuId */ +#define NV0000_BUSDEVICE_DOMAIN 31:16 +#define NV0000_BUSDEVICE_BUS 15:8 +#define NV0000_BUSDEVICE_DEVICE 7:0 + +#define GPU_32_BIT_ID_DECODE_DOMAIN(gpuId) (NvU16)DRF_VAL(0000, _BUSDEVICE, _DOMAIN, gpuId); +#define GPU_32_BIT_ID_DECODE_BUS(gpuId) (NvU8) DRF_VAL(0000, _BUSDEVICE, _BUS, gpuId); +#define GPU_32_BIT_ID_DECODE_DEVICE(gpuId) (NvU8) DRF_VAL(0000, _BUSDEVICE, _DEVICE, gpuId); + +/* + * NV0000_CTRL_CMD_VGPU_CREATE_DEVICE + * + * This command informs RM to create a vGPU device on KVM. + * + * vgpuName [IN] + * This parameter provides the MDEV UUID or VF BDF depending on whether MDEV + * or vfio-pci-core framework is used. + * + * gpuPciId [IN] + * This parameter provides gpuId of GPU on which vgpu device is created. + * + * gpuPciBdf + * This parameter specifies the BDF of the VF. (Same as PF for non-sriov) + * + * vgpuTypeId [IN] + * This parameter specifies the vGPU type ID for the device to be created. + * + * vgpuId [OUT] + * This parameter returns the vgpu id allocated by RM for the device + * + * gpuInstanceId [OUT] + * This parameter returns the swizzId allocated by RM for the device. + * + * placementId [OUT] + * This parameter returns the placementId allocated by RM for the device. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_EVENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_CLIENT + * + */ + +#define NV0000_CTRL_CMD_VGPU_CREATE_DEVICE (0xc02) /* finn: Evaluated from "(FINN_NV01_ROOT_VGPU_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS { + NvU8 vgpuName[VM_UUID_SIZE]; + NvU32 gpuPciId; + NvU32 gpuPciBdf; + NvU32 vgpuTypeId; + NvU16 vgpuId; + NvU32 gpuInstanceId; + NvU32 placementId; +} NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS; + +/* + * NV0000_CTRL_CMD_VGPU_GET_INSTANCES + * + * This command queries RM for available instances for a particular vGPU type ID + * on KVM. + * + * gpuPciId [IN] + * This parameter specifies gpuId of GPU on which vGPU instances are being + * queried. + * + * gpuPciBdf [IN] + * This parameter specifies the BDF of the VF. (Same as PF for non-sriov) + * + * numVgpuTypes [IN] + * This parameter specifies the count of vgpuTypeIds supplied and the + * count of availableInstances values to be returned. + * + * vgpuTypeIds [IN] + * This parameter specifies a total of numVgpuTypes vGPU type IDs for which + * the available instances are to be queried. + * + * availableInstances [OUT] + * This parameter returns a total of numVgpuTypes available instances for + * the respective vGPU type IDs supplied in vgpuTypeIds input parameter. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_EVENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_CLIENT + * NV_ERR_INVALID_STATE + * + */ + +#define NV0000_CTRL_CMD_VGPU_GET_INSTANCES (0xc03) /* finn: Evaluated from "(FINN_NV01_ROOT_VGPU_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS { + NvU32 gpuPciId; + NvU32 gpuPciBdf; + NvU32 numVgpuTypes; + NvU32 vgpuTypeIds[NVA081_MAX_VGPU_TYPES_PER_PGPU]; + NvU32 availableInstances[NVA081_MAX_VGPU_TYPES_PER_PGPU]; +} NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS; + +/* + * NV0000_CTRL_CMD_VGPU_DELETE_DEVICE + * + * This command informs RM to delete a vGPU device on KVM. + * + * vgpuName [IN] + * This parameter provides the MDEV UUID or VF BDF depending on whether MDEV + * or vfio-pci-core framework is used. + * + * vgpuId [IN] + * This parameter provides the vgpu id allocated by RM for the device to be + * deleted. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_EVENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_CLIENT + * + */ + +#define NV0000_CTRL_CMD_VGPU_DELETE_DEVICE (0xc04) /* finn: Evaluated from "(FINN_NV01_ROOT_VGPU_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS { + NvU8 vgpuName[VM_UUID_SIZE]; + NvU16 vgpuId; +} NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS; + +/* + * NV0000_CTRL_CMD_VGPU_VFIO_NOTIFY_RM_STATUS + * + * This command informs RM the status of vgpu-vfio GPU operations such as probe and unregister. + * + * returnStatus [IN] + * This parameter provides the status of vgpu-vfio GPU operation. + * + * gpuPciId [IN] + * This parameter provides the gpu id of the GPU + */ + +#define NV0000_CTRL_CMD_VGPU_VFIO_NOTIFY_RM_STATUS (0xc05) /* finn: Evaluated from "(FINN_NV01_ROOT_VGPU_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS { + NvU32 returnStatus; + NvU32 gpuId; +} NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_UPDATE_SYSFS_NODE + * + * This command will get/set the information of following sysfs node: + * gpuInstanceId + * placementId + * + * vgpuName [IN] + * This parameter provides the MDEV UUID or VF BDF depending on whether MDEV + * or vfio-pci-core framework is used. + * + * mode [IN] + * This parameter provides info about the type of operation this cmd will perform. + * + * sysfs_val [IN/OUT] + * This parameter will store the info of placementID/gpuInstanceId. + * + */ + +#define NV0000_CTRL_CMD_GPU_UPDATE_SYSFS_NODE (0x206U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS { + NvU8 vgpuName[VM_UUID_SIZE]; + NvU32 mode; + NvU32 sysfs_val; +} NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS; + +/* _ctrl0000vgpu_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0002.h b/userspace/sdks/nv570/inc/ctrl/ctrl0002.h new file mode 100644 index 0000000..44f5279 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0002.h @@ -0,0 +1,178 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0002.finn +// + +#include "ctrl/ctrlxxxx.h" +#define NV0002_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0002, NV0002_CTRL_##cat, idx) + +/* Client command categories (6bits) */ +#define NV0002_CTRL_RESERVED (0x00) +#define NV0002_CTRL_DMA (0x01) + + +/* + * NV0002_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ + +#define NV0002_CTRL_CMD_NULL (0x20000) /* finn: Evaluated from "(FINN_NV01_CONTEXT_DMA_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV0002_CTRL_CMD_UPDATE_CONTEXTDMA + * + * This command will update the parameters of the specified context dma. The + * context dma must be bound to a display channel. The update is limited + * to the display view of the context dma. Other use cases will continue to + * use the original allocation parameters. + * + * This is used on platforms where memory may be moved by the operating + * system after allocation. + * + * This control call supports the NVOS54_FLAGS_LOCK_BYPASS flag. + * + * baseAddress + * This parameter, if selected by flags, indicates the new baseAddress for + * the ctxdma + * limit + * This parameter, if selected by flags, indicates the new limit of the + * ctxdma. + * hCtxDma + * ContextDma handle on which to operate. Must match the handle given to the control + * call. + * hChannel + * Display channel handle. This field is ignored. + * hintHandle + * Hint value returned from HeapAllocHint which encodes information about + * the surface. This is used by chips without generic kind. Newer chips + * use the COMPR_INFO flag and the hintHandle must be zero. + * flags + * This parameter specifies flags which indicate which other parameters are + * valid. + * FLAGS_PAGESIZE updates the context DMA pagesize field, if not _DEFAULT + * FLAGS_USE_COMPR_INFO uses the surface format specified in the params, instead of hintHandle. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_NOT_SUPPORTED + */ +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA (0x20101) /* finn: Evaluated from "(FINN_NV01_CONTEXT_DMA_DMA_INTERFACE_ID << 8) | NV0002_CTRL_UPDATE_CONTEXTDMA_PARAMS_MESSAGE_ID" */ + +#define NV0002_CTRL_UPDATE_CONTEXTDMA_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0002_CTRL_UPDATE_CONTEXTDMA_PARAMS { + NV_DECLARE_ALIGNED(NvU64 baseAddress, 8); + NV_DECLARE_ALIGNED(NvU64 limit, 8); + NvHandle hSubDevice; + NvHandle hCtxDma; + NvHandle hChannel; + NvHandle hintHandle; + NvU32 flags; +} NV0002_CTRL_UPDATE_CONTEXTDMA_PARAMS; + +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_BASEADDRESS 0:0 +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_BASEADDRESS_INVALID (0x00000000) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_BASEADDRESS_VALID (0x00000001) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_LIMIT 1:1 +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_LIMIT_INVALID (0x00000000) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_LIMIT_VALID (0x00000001) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_HINT 2:2 +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_HINT_INVALID (0x00000000) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_HINT_VALID (0x00000001) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_PAGESIZE 4:3 +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_PAGESIZE_DEFAULT (0x00000000) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_PAGESIZE_4K (0x00000001) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_PAGESIZE_BIG (0x00000002) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_USE_COMPR_INFO 6:5 +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_USE_COMPR_INFO_NONE (0x00000000) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_USE_COMPR_INFO_FORMAT_PITCH (0x00000001) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_USE_COMPR_INFO_FORMAT_BLOCK_LINEAR (0x00000002) + +/* + * NV0002_CTRL_CMD_BIND_CONTEXTDMA + * + * Bind a context dma to a display channel. Binding is no longer required for + * Host channels, but does silently succeed. + * + * This control call supports the NVOS54_FLAGS_LOCK_BYPASS flag. + * + * This control replaces the obsolete RmBindContextDma() API. + * + * hChannel + * The channel for ctxdma bind + * + * Possible error codes include + * NV_OK + * NV_ERR_TOO_MANY_PRIMARIES hash table is full + * NV_ERR_NO_MEMORY instance memory is full + * NV_ERR_INVALID_OFFSET surface is not correctly aligned + * NV_ERR_STATE_IN_USE context dma was already bound given channel + */ +#define NV0002_CTRL_CMD_BIND_CONTEXTDMA (0x20102) /* finn: Evaluated from "(FINN_NV01_CONTEXT_DMA_DMA_INTERFACE_ID << 8) | NV0002_CTRL_BIND_CONTEXTDMA_PARAMS_MESSAGE_ID" */ + +#define NV0002_CTRL_BIND_CONTEXTDMA_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0002_CTRL_BIND_CONTEXTDMA_PARAMS { + NvHandle hChannel; +} NV0002_CTRL_BIND_CONTEXTDMA_PARAMS; + +/* + * NV0002_CTRL_CMD_UNBIND_CONTEXTDMA + * + * Unbind a context dma from a display channel. + * + * This control call supports the NVOS54_FLAGS_LOCK_BYPASS flag. + * + * hChannel + * The display channel to unbind from + * + * Possible error codes include + * NV_OK + * NV_ERR_INVALID_STATE channel was not bound + */ +#define NV0002_CTRL_CMD_UNBIND_CONTEXTDMA (0x20103) /* finn: Evaluated from "(FINN_NV01_CONTEXT_DMA_DMA_INTERFACE_ID << 8) | NV0002_CTRL_UNBIND_CONTEXTDMA_PARAMS_MESSAGE_ID" */ + +#define NV0002_CTRL_UNBIND_CONTEXTDMA_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0002_CTRL_UNBIND_CONTEXTDMA_PARAMS { + NvHandle hChannel; +} NV0002_CTRL_UNBIND_CONTEXTDMA_PARAMS; + +/* _ctrl0002.h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0004.h b/userspace/sdks/nv570/inc/ctrl/ctrl0004.h new file mode 100644 index 0000000..05bb88f --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0004.h @@ -0,0 +1,93 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0004.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV01_TIMER control commands and parameters */ + +#define NV0004_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0004, NV0004_CTRL_##cat, idx) + +/* NV01_TIMER command categories (8bits) */ +#define NV0004_CTRL_RESERVED (0x00) +#define NV0004_CTRL_TMR (0x01) + +/* + * NV0004_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0004_CTRL_CMD_NULL (0x40000) /* finn: Evaluated from "(FINN_NV01_TIMER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV0004_CTRL_CMD_TMR_SET_ALARM_NOTIFY + * + * This command can be used to set a PTIMER alarm to trigger at the + * specified time in the future on the subdevice associated with this + * NV01_TIMER object instance. + * + * hEvent + * This parameter specifies the handle of an NV01_EVENT object instance + * that is to be signaled when the alarm triggers. This NV01_EVENT + * object instance must have been allocated with this NV01_TIMER object + * instance as its parent. If this parameter is set to NV01_NULL_OBJECT + * then all NV01_EVENT object instances associated with this NV01_TIMER + * object instance are signaled. + * alarmTimeUsecs + * This parameter specifies the relative time in nanoseconds at which + * the alarm should trigger. Note that the accuracy between the alarm + * trigger and the subsequent notification to the caller can vary + * depending on system conditions. + * + * Possible status values returned include: + * NVOS_STATUS_SUCCES + * NVOS_STATUS_INVALID_PARAM_STRUCT + * NVOS_STATUS_INVALID_OBJECT_HANDLE + */ + +#define NV0004_CTRL_CMD_TMR_SET_ALARM_NOTIFY (0x40110) /* finn: Evaluated from "(FINN_NV01_TIMER_TMR_INTERFACE_ID << 8) | NV0004_CTRL_TMR_SET_ALARM_NOTIFY_PARAMS_MESSAGE_ID" */ + +#define NV0004_CTRL_TMR_SET_ALARM_NOTIFY_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV0004_CTRL_TMR_SET_ALARM_NOTIFY_PARAMS { + NvHandle hEvent; + NV_DECLARE_ALIGNED(NvU64 alarmTimeNsecs, 8); +} NV0004_CTRL_TMR_SET_ALARM_NOTIFY_PARAMS; + +/* _ctrl0004_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl000f.h b/userspace/sdks/nv570/inc/ctrl/ctrl000f.h new file mode 100644 index 0000000..3f70c7d --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl000f.h @@ -0,0 +1,85 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl000f.finn +// + +#include "ctrl/ctrlxxxx.h" + +#define NV000F_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x000f, NV000F_CTRL_##cat, idx) + +/* Client command categories (6bits) */ +#define NV000F_CTRL_RESERVED (0x00U) +#define NV000F_CTRL_FM (0x01U) +#define NV000F_CTRL_RESERVED2 (0x02U) + +/* + * NV000f_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV000F_CTRL_CMD_NULL (0xf0000U) /* finn: Evaluated from "(FINN_FABRIC_MANAGER_SESSION_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV000F_CTRL_CMD_SET_FM_STATE + * + * This command will notify RM that the fabric manager is initialized. + * + * RM would block P2P operations such as P2P capability reporting, NV50_P2P object + * allocation etc. until the notification received. + * + * Possible status values returned are: + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + * NV_OK + */ +#define NV000F_CTRL_CMD_SET_FM_STATE (0xf0101U) /* finn: Evaluated from "(FINN_FABRIC_MANAGER_SESSION_FM_INTERFACE_ID << 8) | 0x1" */ + +/* + * NV000F_CTRL_CMD_CLEAR_FM_STATE + * + * This command will notify RM that the fabric manager is uninitialized. + * + * RM would block P2P operations such as P2P capability reporting, NV50_P2P object + * allocation etc. as soon as the notification received. + * + * Possible status values returned are: + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + * NV_OK + */ +#define NV000F_CTRL_CMD_CLEAR_FM_STATE (0xf0102U) /* finn: Evaluated from "(FINN_FABRIC_MANAGER_SESSION_FM_INTERFACE_ID << 8) | 0x2" */ + +/* _ctrl000f.h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0020.h b/userspace/sdks/nv570/inc/ctrl/ctrl0020.h new file mode 100644 index 0000000..257db3a --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0020.h @@ -0,0 +1,80 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0020.finn +// + +#include "ctrl/ctrlxxxx.h" +#define NV0020_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0x0020, NV0020_CTRL_##cat, idx) + +/* NV0020_GPU_MANAGEMENT command categories (6bits) */ +#define NV0020_CTRL_RESERVED (0x00) +#define NV0020_CTRL_GPU_MGMT (0x01) + +/* + * NV0020_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0020_CTRL_CMD_NULL (0x200000) /* finn: Evaluated from "(FINN_NV0020_GPU_MANAGEMENT_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* Maximum possible number of bytes of GID information */ +#define NV0020_GPU_MAX_GID_LENGTH (0x00000100) + +/* + * NV0020_CTRL_CMD_GPU_MGMT_SET_SHUTDOWN_STATE + * + * This command modifies GPU zero power state for the desired GPU in the + * database. This state is set by a privileged client, after the GPU is + * completely unregistered from RM as well as PCI subsystem. On Linux, + * clients perform this operation through pci-sysfs. + * This control call requires admin privileges. + * + * uuid (INPUT) + * The UUID of the gpu. + * Supports binary format and SHA-1 type. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0020_CTRL_CMD_GPU_MGMT_SET_SHUTDOWN_STATE (0x200101) /* finn: Evaluated from "(FINN_NV0020_GPU_MANAGEMENT_GPU_MGMT_INTERFACE_ID << 8) | NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS { + NvU8 uuid[NV0020_GPU_MAX_GID_LENGTH]; +} NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS; + +/* _ctrl0020_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl003e.h b/userspace/sdks/nv570/inc/ctrl/ctrl003e.h new file mode 100644 index 0000000..8799e9e --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl003e.h @@ -0,0 +1,136 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl003e.finn +// + +#include "ctrl0041.h" +#include "ctrl/ctrlxxxx.h" +/* NV01_MEMORY_SYSTEM control commands and parameters */ + +#define NV003E_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x003E, NV003E_CTRL_##cat, idx) + +/* NV01_MEMORY_SYSTEM command categories (6bits) */ +#define NV003E_CTRL_RESERVED (0x00) +#define NV003E_CTRL_MEMORY (0x01) + +/* + * NV003E_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV003E_CTRL_CMD_NULL (0x3e0000) /* finn: Evaluated from "(FINN_NV01_MEMORY_SYSTEM_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV003E_CTRL_CMD_GET_SURFACE_PHYS_ATTR + * + * See NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR + * + */ +#define NV003E_CTRL_CMD_GET_SURFACE_PHYS_ATTR NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR + +typedef NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS NV003E_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS; + + +/* valid gpuCacheAttr return values */ +#define NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN (0x00000000) +#define NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED (0x00000001) +#define NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED (0x00000002) + +/* NV003E_CTRL_CMD_GET_SURFACE_NUM_PHYS_PAGES + * + * This command returns the number of physical pages associated with the + * memory object. + * + * This call is currently only implemented on Linux and assumes that linux + * kernel in which RM module will be loaded has same page size as defined + * in linux kernel source with which RM module was built. + * + * numPages + * This parameter returns total number of physical pages associated with + * the memory object. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV003E_CTRL_CMD_GET_SURFACE_NUM_PHYS_PAGES (0x3e0102) /* finn: Evaluated from "(FINN_NV01_MEMORY_SYSTEM_MEMORY_INTERFACE_ID << 8) | NV003E_CTRL_GET_SURFACE_NUM_PHYS_PAGES_PARAMS_MESSAGE_ID" */ + +#define NV003E_CTRL_GET_SURFACE_NUM_PHYS_PAGES_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV003E_CTRL_GET_SURFACE_NUM_PHYS_PAGES_PARAMS { + NvU32 numPages; +} NV003E_CTRL_GET_SURFACE_NUM_PHYS_PAGES_PARAMS; + + +/* NV003E_CTRL_CMD_GET_SURFACE_PHYS_PAGES + * + * This command returns physical pages associated with the memory object. + * + * This call is currently only implemented on Linux and assumes that linux + * kernel in which RM module will be loaded has same page size as defined + * in linux kernel source with which RM module was built. + * + * pPages + * This parameter returns physical pages associated with the memory object. + * + * numPages + * This parameter is both an input and an output. As an input parameter, + * it's value indicates maximum number of physical pages to be copied to + * pPages. As an output parameter, it's value indicates number of physical + * pages copied to pPages. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV003E_CTRL_CMD_GET_SURFACE_PHYS_PAGES (0x3e0103) /* finn: Evaluated from "(FINN_NV01_MEMORY_SYSTEM_MEMORY_INTERFACE_ID << 8) | NV003E_CTRL_GET_SURFACE_PHYS_PAGES_PARAMS_MESSAGE_ID" */ + +#define NV003E_CTRL_GET_SURFACE_PHYS_PAGES_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV003E_CTRL_GET_SURFACE_PHYS_PAGES_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pPages, 8); + NvU32 numPages; +} NV003E_CTRL_GET_SURFACE_PHYS_PAGES_PARAMS; + +/* _ctrl003e_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0041.h b/userspace/sdks/nv570/inc/ctrl/ctrl0041.h new file mode 100644 index 0000000..fd66f78 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0041.h @@ -0,0 +1,494 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0041.finn +// + +#include "nvos.h" +#include "ctrl/ctrlxxxx.h" +/* NV04_MEMORY control commands and parameters */ + +#define NV0041_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0041, NV0041_CTRL_##cat, idx) + +/* NV04_MEMORY command categories (6bits) */ +#define NV0041_CTRL_RESERVED (0x00) +#define NV0041_CTRL_MEMORY (0x01) + +/* + * NV0041_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0041_CTRL_CMD_NULL (0x410000) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR + * + * This command returns attributes associated with the memory object + * at the given offset. The architecture dependent return parameter + * comprFormat determines the meaningfulness (or not) of comprOffset. + * + * This call is only currently supported in the MODS environment. + * + * memOffset + * This parameter is both an input and an output. As input, this + * parameter holds an offset into the memory surface. The return + * value is the physical address of the surface at the given offset. + * memFormat + * This parameter returns the memory kind of the surface. + * comprOffset + * This parameter returns the compression offset of the surface. + * comprFormat + * This parameter returns the type of compression of the surface. + * memAperture + * The aperture of the surface is returned in this field. + * Legal return values for this parameter are + * NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_VIDMEM + * NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_SYSMEM + * gpuCacheAttr + * gpuCacheAttr returns the gpu cache attribute of the surface. + * Legal return values for this field are + * NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN + * NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED + * NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED + * gpuP2PCacheAttr + * gpuP2PCacheAttr returns the gpu peer-to-peer cache attribute of the surface. + * Legal return values for this field are + * NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN + * NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED + * NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED + * mmuContext + * mmuContext indicates the type of physical address to be returned (input parameter). + * Legal return values for this field are + * TEGRA_VASPACE_A -- return the device physical address for Tegra (non-GPU) engines. This is the system physical address itself. + * returns the system physical address. This may change to use a class value in future. + * FERMI_VASPACE_A -- return the device physical address for GPU engines. This can be a system physical address or a GPU SMMU virtual address. + * 0 -- return the device physical address for GPU engines. This can be a system physical address or a GPU SMMU virtual address. + * use of zero may be deprecated in future. + * contigSegmentSize + * If the underlying surface is physically contiguous, this parameter + * returns the size in bytes of the piece of memory starting from + * the offset specified in the memOffset parameter extending to the last + * byte of the surface. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_BAD_OBJECT_HANDLE + * NVOS_STATUS_BAD_OBJECT_PARENT + * NVOS_STATUS_NOT_SUPPORTED + * + */ +#define NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR (0x410103) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS { + NV_DECLARE_ALIGNED(NvU64 memOffset, 8); + NvU32 memFormat; + NvU32 comprOffset; + NvU32 comprFormat; + NvU32 memAperture; + NvU32 gpuCacheAttr; + NvU32 gpuP2PCacheAttr; + NvU32 mmuContext; + NV_DECLARE_ALIGNED(NvU64 contigSegmentSize, 8); +} NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS; + +/* valid memAperture return values */ +#define NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_VIDMEM (0x00000000) +#define NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_SYSMEM (0x00000001) + +/* valid gpuCacheAttr return values */ +#define NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN (0x00000000) +#define NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED (0x00000001) +#define NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED (0x00000002) + +/* + * NV0041_CTRL_CMD_GET_SURFACE_ZCULL_ID + * + * This command returns the Z-cull identifier for a surface. + * The value of ~0 is returned if there is none associated. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_BAD_OBJECT_HANDLE + * NVOS_STATUS_BAD_OBJECT_PARENT + * NVOS_STATUS_NOT_SUPPORTED + * + */ +#define NV0041_CTRL_CMD_GET_SURFACE_ZCULL_ID (0x410104) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS { + NvU32 zcullId; +} NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS; + + +// return values for 'tilingFormat' +// XXX - the names for these are misleading +#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_INVALID (0x00000000) +#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_FB (0x00000001) +#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_FB_1HIGH (0x00000002) +#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_FB_4HIGH (0x00000003) +#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_UMA_1HIGH (0x00000004) +#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_UMA_4HIGH (0x00000005) + +/* + * NV0041_CTRL_SURFACE_INFO + * + * This structure represents a single 32bit surface value. Clients + * request a particular surface value by specifying a unique surface + * information index. + * + * Legal surface information index values are: + * NV0041_CTRL_SURFACE_INFO_INDEX_ATTRS + * This index is used to request the set of hw attributes associated + * with the surface. Each distinct attribute is represented by a + * single bit flag in the returned value. + * Legal flags values for this index are: + * NV0041_CTRL_SURFACE_INFO_ATTRS_COMPR + * This surface has compression resources bound to it. + * NV0041_CTRL_SURFACE_INFO_ATTRS_ZCULL + * This surface has zcull resources bound to it. + * NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_SIZE_LO + * This index is used to request the low 32 bits of the physically allocated + * size (64 bit value) in units of bytes for the associated surface. + * NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_SIZE_HI + * This index is used to request the high 32 bits of the physically + * allocated size (64 bit value) in units of bytes for the associated + * surface. + * NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE + * This index is used to request the compression coverage (if any) + * in units of 64K for the associated surface. A value of zero indicates + * there are no compression resources associated with the surface. + * Legal return values range from zero to a maximum number of 64K units + * that is GPU implementation dependent. + * NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_SIZE + * This index is used to request the physically allocated size in units + * of 4K(NV0041_CTRL_SURFACE_INFO_PHYS_SIZE_SCALE_FACTOR) for the associated + * surface. This interface is obsoleted by + * NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_SIZE_{LO,HI}. + * NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_ATTR + * This index is used to request the surface attribute field. The returned + * field value can be decoded using the NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_* + * DRF-style macros provided below. + * NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE + * This index is used to request the surface address space type. + * Returned values are described by NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE. + */ +typedef NVXXXX_CTRL_XXX_INFO NV0041_CTRL_SURFACE_INFO; + +/* valid surface info index values */ +#define NV0041_CTRL_SURFACE_INFO_INDEX_ATTRS (0x00000001) +#define NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_SIZE_LO (0x00000002) +#define NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_SIZE_HI (0x00000003) +#define NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE (0x00000005) +#define NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_SIZE (0x00000007) +#define NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_ATTR (0x00000008) +#define NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE (0x00000009) + +/* + * This define indicates the scale factor of the reported physical size to the + * actual size in bytes. We use the scale factor to save space from the + * interface and account for large surfaces. To get the actual size, + * use `(NvU64)reported_size * NV0041_CTRL_SURFACE_INFO_PHYS_SIZE_SCALE_FACTOR`. + */ +#define NV0041_CTRL_SURFACE_INFO_PHYS_SIZE_SCALE_FACTOR (0x1000) + +/* valid surface info attr flags */ +#define NV0041_CTRL_SURFACE_INFO_ATTRS_COMPR (0x00000002) +#define NV0041_CTRL_SURFACE_INFO_ATTRS_ZCULL (0x00000004) + +/* Valid surface info page size */ +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE NVOS32_ATTR_PAGE_SIZE +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE_DEFAULT NVOS32_ATTR_PAGE_SIZE_DEFAULT +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE_4KB NVOS32_ATTR_PAGE_SIZE_4KB +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE_BIG NVOS32_ATTR_PAGE_SIZE_BIG +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE_HUGE NVOS32_ATTR_PAGE_SIZE_HUGE + +/* Valid surface info CPU coherency */ +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY NVOS32_ATTR_COHERENCY +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_UNCACHED NVOS32_ATTR_COHERENCY_UNCACHED +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_CACHED NVOS32_ATTR_COHERENCY_CACHED +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_COMBINE NVOS32_ATTR_COHERENCY_WRITE_COMBINE +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_THROUGH NVOS32_ATTR_COHERENCY_WRITE_THROUGH +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_PROTECT NVOS32_ATTR_COHERENCY_WRITE_PROTECT +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_BACK NVOS32_ATTR_COHERENCY_WRITE_BACK + +/* Valid surface info format */ +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_FORMAT NVOS32_ATTR_FORMAT +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_FORMAT_PITCH NVOS32_ATTR_FORMAT_PITCH +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_FORMAT_SWIZZLED NVOS32_ATTR_FORMAT_SWIZZLED +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_FORMAT_BLOCK_LINEAR NVOS32_ATTR_FORMAT_BLOCK_LINEAR + +/* + * NV0041_CTRL_CMD_GET_SURFACE_INFO + * + * This command returns surface information for the associated memory object. + * Requests to retrieve surface information use a list of one or more + * NV0041_CTRL_SURFACE_INFO structures. + * + * surfaceInfoListSize + * This field specifies the number of entries on the caller's + * surfaceInfoList. + * surfaceInfoList + * This field specifies a pointer in the caller's address space + * to the buffer into which the surface information is to be returned. + * This buffer must be at least as big as surfaceInfoListSize multiplied + * by the size of the NV0041_CTRL_SURFACE_INFO structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV0041_CTRL_CMD_GET_SURFACE_INFO (0x410110) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_GET_SURFACE_INFO_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV0041_CTRL_GET_SURFACE_INFO_PARAMS { + NvU32 surfaceInfoListSize; + NV_DECLARE_ALIGNED(NvP64 surfaceInfoList, 8); +} NV0041_CTRL_GET_SURFACE_INFO_PARAMS; + +/* + * NV0041_CTRL_CMD_GET_SURFACE_COMPRESSION_COVERAGE + * + * This command returns the percentage of surface compression tag coverage. + * The value of 0 is returned if there are no tags associated. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_BAD_OBJECT_HANDLE + * NVOS_STATUS_BAD_OBJECT_PARENT + * NVOS_STATUS_NOT_SUPPORTED + * + */ +#define NV0041_CTRL_CMD_GET_SURFACE_COMPRESSION_COVERAGE (0x410112) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS { + NvHandle hSubDevice; /* if non zero subDevice handle of local GPU */ + NvU32 lineMin; + NvU32 lineMax; + NvU32 format; +} NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS; + +/* + * NV0041_CTRL_CMD_GET_FBMEM_BUS_ADDR + * + * This command returns the BAR1 physical address of a + * Memory mapping made using NvRmMapMemory() + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INVALID_DATA + * NV_ERR_INVALID_CLIENT + * NV_ERR_INVALID_OBJECT_HANDLE + * + */ +#define NV0041_CTRL_CMD_GET_FBMEM_BUS_ADDR (0x410114) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_FBMEM_BUS_ADDR_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_GET_FBMEM_BUS_ADDR_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV0041_CTRL_GET_FBMEM_BUS_ADDR_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pLinearAddress, 8); /* [in] Linear address of CPU mapping */ + NV_DECLARE_ALIGNED(NvU64 busAddress, 8); /* [out] BAR1 address */ +} NV0041_CTRL_GET_FBMEM_BUS_ADDR_PARAMS; + +/* + * NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE + * + * This command flushes a cache on the GPU which all memory accesses go + * through. The types of flushes supported by this API may not be supported by + * all hardware. Attempting an unsupported flush type will result in an error. + * + * flags + * Contains flags to control various aspects of the flush. Valid values + * are defined in NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS*. Not all + * flags are valid for all GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NVOS_STATUS_INVALID_ARGUMENT + * NVOS_STATUS_INVALID_STATE + * + * See Also: + * NV0080_CTRL_CMD_DMA_FLUSH + * Performs flush operations in broadcast for the GPU cache and other hardware + * engines. Use this call if you want to flush all GPU caches in a + * broadcast device. + * NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE + * Flushes the entire GPU cache or a set of physical addresses (if the + * hardware supports it). Use this call if you want to flush a set of + * addresses or the entire GPU cache in unicast mode. + * + */ +#define NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE (0x410116) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS { + NvU32 flags; +} NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS; + +#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK 0:0 +#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_NO (0x00000000) +#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_YES (0x00000001) +#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_INVALIDATE 1:1 +#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_NO (0x00000000) +#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_YES (0x00000001) + +/* + * NV0041_CTRL_CMD_GET_EME_PAGE_SIZE + * + * This command may be used to get the memory page size + * + * Parameters: + * pageSize [OUT] + * pageSize with associated memory descriptor + * + * Possible status values are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_NOT_SUPPORTED + */ +#define NV0041_CTRL_CMD_GET_MEM_PAGE_SIZE (0x410118) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); /* [out] - page size */ +} NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS; + +/* + * NV0041_CTRL_CMD_UPDATE_SURFACE_COMPRESSION + * + * Acquire/release compression for surface + * + * Parameters: + * bRelease [IN] + * true = release compression; false = acquire compression + */ +#define NV0041_CTRL_CMD_UPDATE_SURFACE_COMPRESSION (0x410119) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_UPDATE_SURFACE_COMPRESSION_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_UPDATE_SURFACE_COMPRESSION_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV0041_CTRL_UPDATE_SURFACE_COMPRESSION_PARAMS { + NvBool bRelease; /* [in] - acquire/release setting */ +} NV0041_CTRL_UPDATE_SURFACE_COMPRESSION_PARAMS; + +#define NV0041_CTRL_CMD_PRINT_LABELS_PARAMS_MESSAGE_ID (0x50U) + +typedef struct NV0041_CTRL_CMD_PRINT_LABELS_PARAMS { + NvU32 tag; /* [in] */ +} NV0041_CTRL_CMD_PRINT_LABELS_PARAMS; +#define NV0041_CTRL_CMD_SET_LABEL_PARAMS_MESSAGE_ID (0x51U) + +typedef struct NV0041_CTRL_CMD_SET_LABEL_PARAMS { + NvU32 tag; /* [in] */ +} NV0041_CTRL_CMD_SET_LABEL_PARAMS; +#define NV0041_CTRL_CMD_SET_LABEL (0x410151) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_CMD_SET_LABEL_PARAMS_MESSAGE_ID" */ +#define NV0041_CTRL_CMD_GET_LABEL (0x410152) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_CMD_GET_LABEL_PARAMS_MESSAGE_ID" */ +#define NV0041_CTRL_CMD_GET_LABEL_PARAMS_MESSAGE_ID (0x52U) + +typedef struct NV0041_CTRL_CMD_GET_LABEL_PARAMS { + NvU32 tag; /* [in] */ +} NV0041_CTRL_CMD_GET_LABEL_PARAMS; + +/* + * NV0041_CTRL_CMD_SET_TAG + * + * This command sets memory allocation tag used for debugging. +* Every client has it's own memory allocation tag and tag is copying when object is duping. + * This control can be used for shared allocations to change it's tag. + */ +#define NV0041_CTRL_CMD_SET_TAG (0x410120) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_CMD_SET_TAG_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_CMD_SET_TAG_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV0041_CTRL_CMD_SET_TAG_PARAMS { + NvU32 tag; /* [in] */ +} NV0041_CTRL_CMD_SET_TAG_PARAMS; + +/* + * NV0041_CTRL_CMD_GET_TAG + * + * This command returns memory allocation tag used for debugging. + */ +#define NV0041_CTRL_CMD_GET_TAG (0x410121) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_CMD_GET_TAG_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_CMD_GET_TAG_PARAMS_MESSAGE_ID (0x21U) + +typedef struct NV0041_CTRL_CMD_GET_TAG_PARAMS { + NvU32 tag; /* [out] */ +} NV0041_CTRL_CMD_GET_TAG_PARAMS; + +/* + * NV0041_CTRL_CMD_MAP_MEMORY_FOR_GPU_ACCESS + * + * Map system memory into IOMMU VAS of a GPU described by hSubdevice + * Returns the address + * + */ +#define NV0041_CTRL_CMD_MAP_MEMORY_FOR_GPU_ACCESS (0x410122) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_MAP_MEMORY_FOR_GPU_ACCESS_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_MAP_MEMORY_FOR_GPU_ACCESS_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NV0041_CTRL_MAP_MEMORY_FOR_GPU_ACCESS_PARAMS { + NvHandle hSubdevice; + NV_DECLARE_ALIGNED(NvU64 address, 8); +} NV0041_CTRL_MAP_MEMORY_FOR_GPU_ACCESS_PARAMS; + + +/* + * NV0041_CTRL_CMD_UNMAP_MEMORY_FOR_GPU_ACCESS + * + * See NV0041_CTRL_CMD_MAP_MEMORY_FOR_GPU_ACCESS + * + */ +#define NV0041_CTRL_CMD_UNMAP_MEMORY_FOR_GPU_ACCESS (0x410153) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_UNMAP_MEMORY_FOR_GPU_ACCESS_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_UNMAP_MEMORY_FOR_GPU_ACCESS_PARAMS_MESSAGE_ID (0x53U) + +typedef struct NV0041_CTRL_UNMAP_MEMORY_FOR_GPU_ACCESS_PARAMS { + NvHandle hSubdevice; +} NV0041_CTRL_UNMAP_MEMORY_FOR_GPU_ACCESS_PARAMS; + +/* _ctrl0041_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0050.h b/userspace/sdks/nv570/inc/ctrl/ctrl0050.h new file mode 100644 index 0000000..6914231 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0050.h @@ -0,0 +1,208 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0050.finn +// + +#include "ctrl/ctrlxxxx.h" + +#define NV0050_CTRL_CMD(cat, idx) NVXXXX_CTRL_CMD(0x0050, NV0050_CTRL_##cat, idx) + +#define NV0050_CTRL_RESERVED (0x00U) +#define NV0050_CTRL_MEMORY (0x01U) + +#define NV0050_CTRL_CMD_NULL (0x5000U) /* finn: Evaluated from "(FINN_NV_CE_UTILS_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV0050_CTRL_CMD_MEMSET + * + * Memsets a memory allocation and releases a semaphore on completion. + * + * hMemory [IN] + * Memory handle of the memory descriptor that needs to be memset. + * This is only available for verification purposes. + * + * offset [IN] + * Offset into the memory descriptor. + * + * length [IN] + * Length of physical memory to be memset. + * Must be less than or equal to memory size. + * + * pattern [IN] + * The pattern to memset to + * + * flags [IN] + * Can be any of the NV0050_CTRL_MEMSET_FLAGS_* + * DEFAULT + * By default, the memcopy operation will be synchronous and using + * physical copies + * ASYNC + * This flag forces this memset to be asynchronous. + * VIRTUAL + * This flag forces the memset to use Virtual addresses which are + * identity mapped. To use this feature, users need to pass in the + * hVaspace with identity mapped addresses for the entire memory during + * construct. + * PIPELINED + * This flag allows the copy/memset operation to be pipelined with previous dma operations on the same channel + * It means that its reads/writes are allowed happen before writes of preceding operations are tlb-acked + * The flag can be useful when dealing with non-inersecting async operations, + * but it can result in races when 2 async CE operations target the same allocation, and the second operation uses the flag + * Race example: + * 1. async copy A -> B + * 2. pipelined copy B -> C + * Here copy 2 can read B before copy finishes writing it, which will result in C containing invalid data + * Technical details: + * By default, first _LAUNCH_DMA method of a CE operation is marked has _TRANSFER_TYPE_NON_PIPELINED, which the flag overrides + * Subsequent _LAUNCH_DMA methods belonging to the same operation use _TRANSFER_TYPE_PIPELINED, as each of these methods should + * target different addresses + * + * submittedWorkId [OUT] + * The work submission token users can poll on to wait for work + * completed by CE. Only valid in case of ASYNC mode. + */ + +#define NV0050_CTRL_MEMSET_FLAGS_DEFAULT 0 +#define NV0050_CTRL_MEMSET_FLAGS_ASYNC NVBIT(0) +#define NV0050_CTRL_MEMSET_FLAGS_VIRTUAL NVBIT(1) +#define NV0050_CTRL_MEMSET_FLAGS_PIPELINED NVBIT(2) + +#define NV0050_CTRL_CMD_MEMSET (0x500101U) /* finn: Evaluated from "(FINN_NV_CE_UTILS_UTILS_INTERFACE_ID << 8) | NV0050_CTRL_MEMSET_PARAMS_MESSAGE_ID" */ + +#define NV0050_CTRL_MEMSET_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0050_CTRL_MEMSET_PARAMS { + NvHandle hMemory; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 length, 8); + NvU32 pattern; + NV_DECLARE_ALIGNED(NvU64 flags, 8); + NV_DECLARE_ALIGNED(NvU64 submittedWorkId, 8); +} NV0050_CTRL_MEMSET_PARAMS; + +/* + * NV0050_CTRL_CMD_MEMCOPY + * + * Copies from a source memoryto ssdestination memory and releases a semaphore + * on completion + * + * hDstMemory [IN] + * Memory handle of the memory descriptor to which data will be copied. + * This is only available for verification purposes. + * + * hSrcMemory [IN] + * Memory handle of the memory descriptor from which data will be copied. + * This is only available for verification purposes. + * + * dstOfffset [IN] + * Offset into the destination memory descriptor. + * + * srcOffset [IN] + * Offset into the source memory descriptor. + * + * length [IN] + * Length of physical memory to be copied. + * Must be less than or equal to both destination and source memory size. + * + * flags [IN] + * Can be any of the NV0050_CTRL_MEMCOPY_FLAGS_* + * DEFAULT + * By default, the memcopy operation will be synchronous and using + * physical copies + * ASYNC + * This flag forces this memset to be asynchronous. + * VIRTUAL + * This flag forces the memset to use Virtual addresses which are + * identity mapped. To use this feature, users need to pass in the + * hVaspace with identity mapped addresses for the entire memory during + * construct. + * PIPELINED + * This flag allows the copy/memset operation to be pipelined with previous dma operations on the same channel + * It means that its reads/writes are allowed happen before writes of preceding operations are tlb-acked + * The flag can be useful when dealing with non-inersecting async operations, + * but it can result in races when 2 async CE operations target the same allocation, and the second operation uses the flag + * Race example: + * 1. async copy A -> B + * 2. pipelined copy B -> C + * Here copy 2 can read B before copy finishes writing it, which will result in C containing invalid data + * Technical details: + * By default, first _LAUNCH_DMA method of a CE operation is marked has _TRANSFER_TYPE_NON_PIPELINED, which the flag overrides + * Subsequent _LAUNCH_DMA methods belonging to the same operation use _TRANSFER_TYPE_PIPELINED, as each of these methods should + * target different addresses + * + * submittedWorkId [OUT] + * The work submission token users can poll on to wait for work + * completed by CE. Only valid in case of ASYNC mode. + */ + +#define NV0050_CTRL_MEMCOPY_FLAGS_DEFAULT 0 +#define NV0050_CTRL_MEMCOPY_FLAGS_ASYNC NVBIT(0) +#define NV0050_CTRL_MEMCOPY_FLAGS_VIRTUAL NVBIT(1) +#define NV0050_CTRL_MEMCOPY_FLAGS_PIPELINED NVBIT(2) + +#define NV0050_CTRL_CMD_MEMCOPY (0x500102U) /* finn: Evaluated from "(FINN_NV_CE_UTILS_UTILS_INTERFACE_ID << 8 | NV0050_CTRL_MEMCOPY_PARAMS_MESSAGE_ID)" */ + +#define NV0050_CTRL_MEMCOPY_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0050_CTRL_MEMCOPY_PARAMS { + NvHandle hDstMemory; + NvHandle hSrcMemory; + NV_DECLARE_ALIGNED(NvU64 dstOffset, 8); + NV_DECLARE_ALIGNED(NvU64 srcOffset, 8); + NV_DECLARE_ALIGNED(NvU64 length, 8); + NV_DECLARE_ALIGNED(NvU64 flags, 8); + NV_DECLARE_ALIGNED(NvU64 submittedWorkId, 8); +} NV0050_CTRL_MEMCOPY_PARAMS; + +/* + * NV0050_CTRL_CMD_CHECK_PROGRESS + * + * Check if a previously submitted work item has been completed by HW. + * + * submittedWorkId [IN] + * The work submission token users can poll on to wait for work + * completed by CE. + * + */ +#define NV0050_CTRL_CHECK_PROGRESS_RESULT_DEFAULT 0 +#define NV0050_CTRL_CHECK_PROGRESS_RESULT_FINISHED NVBIT(1) + +#define NV0050_CTRL_CMD_CHECK_PROGRESS (0x500103U) /* finn: Evaluated from "(FINN_NV_CE_UTILS_UTILS_INTERFACE_ID << 8 | NV0050_CTRL_CHECK_PROGRESS_PARAMS_MESSAGE_ID)" */ + +#define NV0050_CTRL_CHECK_PROGRESS_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0050_CTRL_CHECK_PROGRESS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 submittedWorkId, 8); + NvU32 result; +} NV0050_CTRL_CHECK_PROGRESS_PARAMS; + +/* _ctrl0050_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0073.h b/userspace/sdks/nv570/inc/ctrl/ctrl0073.h new file mode 100644 index 0000000..9987bae --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0073.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2015,2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073.finn +// + + + + +#include "ctrl/ctrlxxxx.h" +/* category-specific includes */ +#include "ctrl0073/ctrl0073system.h" +#include "ctrl0073/ctrl0073specific.h" +#include "ctrl0073/ctrl0073stereo.h" +#include "ctrl0073/ctrl0073event.h" +#include "ctrl0073/ctrl0073internal.h" +#include "ctrl0073/ctrl0073dfp.h" +#include "ctrl0073/ctrl0073dp.h" +#include "ctrl0073/ctrl0073svp.h" +#include "ctrl0073/ctrl0073dpu.h" +#include "ctrl0073/ctrl0073psr.h" +#include "ctrl0073/ctrl0073common.h" diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073base.h b/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073base.h new file mode 100644 index 0000000..1f687aa --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073base.h @@ -0,0 +1,61 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073base.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV04_DISPLAY_COMMON control commands and parameters */ + +#define NV0073_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0073, NV0073_CTRL_##cat, idx) + +/* NV04_DISPLAY_COMMON command categories (6bits) */ +#define NV0073_CTRL_RESERVED (0x00U) +#define NV0073_CTRL_SYSTEM (0x01U) +#define NV0073_CTRL_SPECIFIC (0x02U) +#define NV0073_CTRL_EVENT (0x03U) +#define NV0073_CTRL_INTERNAL (0x04U) +#define NV0073_CTRL_COMMON (0x05U) +#define NV0073_CTRL_DFP (0x11U) +#define NV0073_CTRL_DP (0x13U) +#define NV0073_CTRL_SVP (0x14U) +#define NV0073_CTRL_DPU (0x15U) +#define NV0073_CTRL_PSR (0x16U) +#define NV0073_CTRL_STEREO (0x17U) + +/* + * NV0073_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0073_CTRL_CMD_NULL (0x730000U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrl0073base_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073common.h b/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073common.h new file mode 100644 index 0000000..153cfb8 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073common.h @@ -0,0 +1,119 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073common.finn +// + + + +/* + * DSC caps - + * bDscSupported + * If GPU supports DSC or not + * + * encoderColorFormatMask + * Mask of all color formats for which DSC + * encoding is supported by GPU + * + * lineBufferSizeKB + * Size of line buffer. + * + * rateBufferSizeKB + * Size of rate buffer per slice. + * + * bitsPerPixelPrecision + * Bits per pixel precision for DSC e.g. 1/16, 1/8, 1/4, 1/2, 1bpp + * + * maxNumHztSlices + * Maximum number of horizontal slices supported by DSC encoder + * + * lineBufferBitDepth + * Bit depth used by the GPU to store the reconstructed pixels within + * the line buffer + */ +#define NV0073_CTRL_CMD_DSC_CAP_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0073_CTRL_CMD_DSC_CAP_PARAMS { + NvBool bDscSupported; + NvU32 encoderColorFormatMask; + NvU32 lineBufferSizeKB; + NvU32 rateBufferSizeKB; + NvU32 bitsPerPixelPrecision; + NvU32 maxNumHztSlices; + NvU32 lineBufferBitDepth; +} NV0073_CTRL_CMD_DSC_CAP_PARAMS; + +/* + * NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior + * cmd + * This parameter is an input to this command. + * Here are the current defined fields: + * NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER + * Set to specify what operation to run. + * NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER_UP + * Request to power up pad. + * NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER_DOWN + * Request to power down the pad. + * linkBw + * This parameter is used to pass in the link bandwidth required to run the + * power up sequence. Refer enum DM_FRL_LINK_RATE_GBPS for valid values. + * laneCount + * This parameter is used to pass the lanecount. + * sorIndex + * This parameter is used to pass the SOR index. + * padlinkIndex + * This parameter is used to pass the padlink index for primary link. + * Please refer enum DFPPADLINK for valid index values for Link A~F. + */ + +#define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD (0x730502U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_COMMON_INTERFACE_ID << 8) | NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_PARAMS { + NvU32 subDeviceInstance; + NvU32 cmd; + NvU32 linkBw; + NvU32 laneCount; + NvU32 sorIndex; + NvU32 padlinkIndex; +} NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_PARAMS; + +#define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER 0:0 +#define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER_UP (0x00000000U) +#define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER_DOWN (0x00000001U) + +/* _ctrl0073common_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073dfp.h b/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073dfp.h new file mode 100644 index 0000000..b8dce37 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073dfp.h @@ -0,0 +1,1884 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073dfp.finn +// + +#include "ctrl/ctrl0073/ctrl0073base.h" +#include "ctrl/ctrl0073/ctrl0073common.h" + +#include "nvcfg_sdk.h" + +/* NV04_DISPLAY_COMMON dfp-display-specific control commands and parameters */ + +/* + * NV0073_CTRL_CMD_DFP_GET_INFO + * + * This command can be used to determine the associated display type for + * the specified displayId. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must be a dfp display + * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * flags + * This parameter returns the information specific to this dfp. Here are + * the possible fields: + * NV0073_CTRL_DFP_FLAGS_SIGNAL + * This specifies the type of signal used for this dfp. + * NV0073_CTRL_DFP_FLAGS_LANES + * This specifies whether the board supports 1, 2, or 4 lanes + * for DISPLAYPORT signals. + * NV0073_CTRL_DFP_FLAGS_LIMIT + * Some GPUs were not qualified to run internal TMDS except at 60 HZ + * refresh rates. So, if LIMIT_60HZ_RR is set, then the client must + * make sure to only allow 60 HZ refresh rate modes to the OS/User. + * NV0073_CTRL_DFP_FLAGS_SLI_SCALER + * While running in SLI, if SLI_SCALER_DISABLE is set, the GPU cannot + * scale any resolutions. So, the output timing must match the + * memory footprint. + * NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE + * This specifies whether the DFP displayId is capable of + * transmitting HDMI. + * NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE + * This specifies whether the displayId is capable of sending a + * limited color range out from the board. + * NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE + * This specifies whether the displayId is capable of auto-configuring + * the color range. + * NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE + * This specifies whether the displayId is capable of sending the + * YCBCR422 color format out from the board. + * NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE + * This specifies whether the displayId is capable of sending + * YCBCR444 color format out from the board. + * NV0073_CTRL_DFP_FLAGS_TYPE_C_TO_DP_CONNECTOR + * This specifies whether the displayId is a DP connector routed to an USB-TYPE-C port. + * NV0073_CTRL_DFP_FLAGS_DP_LINK_BANDWIDTH + * This specifies max link rate supported by the displayId, if the DFP is + * display port. + * NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED + * This specifies whether the DFP displayId is allowed to transmit HDMI + * based on the VBIOS settings. + * NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT + * This specifies whether the DFP displayId is actually an embedded display + * port based on VBIOS connector information AND ASSR cap. + * NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT + * This specifies whether the DFP displayId must be trained to RBR mode + * (if it is using DP protocol) whenever possible. + * NV0073_CTRL_DFP_FLAGS_LINK + * This specifies whether the board supports single or dual links + * for TMDS, LVDS, and SDI signals. + * NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED + * This specifies if PostCursor2 is disabled in the VBIOS + * NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID + * This indicates whether this SOR uses DSI-A, DSI-B or both (ganged mode). + * NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE + * This indicates whether this DFP supports DDS (NV dynamic display mux). + * UHBRSupportedByDfp + * Bitmask to specify the UHBR link rates supported by this dfp. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_DFP_GET_INFO (0x731140U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_GET_INFO_PARAMS_MESSAGE_ID (0x40U) + +typedef struct NV0073_CTRL_DFP_GET_INFO_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 flags; + NvU32 UHBRSupportedByDfp; +} NV0073_CTRL_DFP_GET_INFO_PARAMS; + +/* valid display types */ +#define NV0073_CTRL_DFP_FLAGS_SIGNAL 2:0 +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_TMDS (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_LVDS (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_SDI (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DISPLAYPORT (0x00000003U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DSI (0x00000004U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_WRBK (0x00000005U) +#define NV0073_CTRL_DFP_FLAGS_LANE 5:3 +#define NV0073_CTRL_DFP_FLAGS_LANE_NONE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_LANE_SINGLE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_LANE_DUAL (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_LANE_QUAD (0x00000003U) +#define NV0073_CTRL_DFP_FLAGS_LANE_OCT (0x00000004U) +#define NV0073_CTRL_DFP_FLAGS_LIMIT 6:6 +#define NV0073_CTRL_DFP_FLAGS_LIMIT_DISABLE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_LIMIT_60HZ_RR (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER 7:7 +#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_NORMAL (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_DISABLE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE 8:8 +#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE 9:9 +#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE 10:10 +#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE 11:11 +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE 12:12 +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_TYPE_C_TO_DP_CONNECTOR 13:13 +#define NV0073_CTRL_DFP_FLAGS_TYPE_C_TO_DP_CONNECTOR_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_TYPE_C_TO_DP_CONNECTOR_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED 14:14 +#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT 15:15 +#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT 16:16 +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_NONE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_PREFER_RBR (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW 19:17 +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_1_62GBPS (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_2_70GBPS (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_5_40GBPS (0x00000003U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_8_10GBPS (0x00000004U) +#define NV0073_CTRL_DFP_FLAGS_LINK 21:20 +#define NV0073_CTRL_DFP_FLAGS_LINK_NONE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_LINK_SINGLE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_LINK_DUAL (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID 22:22 +#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID 24:23 +#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_NONE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_A (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_B (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_GANGED (0x00000003U) +#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED 25:25 +#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DP_PHY_REPEATER_COUNT 29:26 +#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE 30:30 +#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_TRUE (0x00000001U) + +#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_10_0GBPS 0:0 +#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_10_0GBPS_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_10_0GBPS_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_13_5GBPS 1:1 +#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_13_5GBPS_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_13_5GBPS_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_20_0GBPS 2:2 +#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_20_0GBPS_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_20_0GBPS_TRUE (0x00000001U) + + + +/* + * NV0073_CTRL_CMD_DFP_GET_DP2TMDS_DONGLE_INFO + * + * This command can be used to determine information about dongles attached + * to a displayport connection. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the dfp display which owns the + * panel power to adjust. The display ID must be a dfp display + * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * flags + * This parameter provide state information about the dongle attachments. + * NV0073_CTRL_DFP_GET_DP2TMDS_DONGLE_INFO_FLAGS_CAPABLE + * Specifies if the connection is capable of a dongle. This field + * returns false in all cases of signal types except for those capable + * of outputting TMDS. Even then the if a gpio is not defined, the + * the a statement of false will also be returned. + * NV0073_CTRL_DFP_GET_DP2TMDS_DONGLE_INFO_FLAGS_ATTACHED + * When attached, this value specifies that a dongle is detected and + * attached. The client should read the _TYPE field to determine + * if it is a dp2hdmi or dp2dvi dongle. + * NV0073_CTRL_DFP_GET_DP2TMDS_DONGLE_INFO_FLAGS_TYPE + * _DP2DVI: no response to i2cAddr 0x80 per DP interop guidelines. + * clients MUST avoid outputting HDMI even if capable. + * _DP2HDMI: dongle responds to i2cAddr 0x80 per DP interop guidelines. + * client is allowed to output HDMI when possible. + * _LFH_DVI: DMS59-DVI breakout dongle is in use. + * _LFH_VGA: DMS59-VGA breakout dongle is in use. + * NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE + * _1: Max TMDS Clock rate is 165 MHz for both DVI and HDMI. + * _2: Max TMDS Clock rate will be specified in the dongle + * address space at device address 0x80. + * DVI is up to 165 MHz + * HDMI is up to 300 MHz + * There are type 2 devices that support beyond 600 MHz + * though not defined in the spec. + * maxTmdsClkRateHz + * This defines the max TMDS clock rate for dual mode adaptor in Hz. + */ +#define NV0073_CTRL_CMD_DFP_GET_DISPLAYPORT_DONGLE_INFO (0x731142U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS_MESSAGE_ID (0x42U) + +typedef struct NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 flags; + NvU32 maxTmdsClkRateHz; +} NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS; + +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_CAPABLE 0:0 +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_ATTACHED 1:1 +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_ATTACHED_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_ATTACHED_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE 7:4 +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE_DP2DVI (0x00000000U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE_DP2HDMI (0x00000001U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE_LFH_DVI (0x00000002U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE_LFH_VGA (0x00000003U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE 8:8 +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE_1 (0x00000000U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE_2 (0x00000001U) + +/* + * NV0073_CTRL_CMD_DFP_SET_ELD_AUDIO_CAPS + * + * This command is used to inform hardware the receiver's audio capabilities + * using the new EDID Like Data (ELD) memory structure. The ELD memory + * structure is read by the audio driver by issuing the ELD Data command verb. + * This mechanism is used for passing sink device' audio EDID information + * from graphics software to audio software. ELD contents will contain a + * subset of the sink device's EDID information. + * The client should inform hardware at initial boot, a modeset, and whenever + * a hotplug event occurs. + * + * displayId + * This parameter indicates the digital display device's + * mask. This comes as input to this command. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * numELDSize + * This parameter specifies how many bytes of data RM should write to the + * ELD buffer. Section 7.3.3.36 of the ECN specifies that the ELD buffer + * size of zero based. HDAudio driver will then use this information to + * determine how many bytes of the ELD buffer the HDAudio should read. + * The maximum size of the buffer is 96 bytes. + * bufferELD + * This buffer contains data as defined in the ECR HDMI ELD memory structure. + * Refer to the ELD Memory Structure Specification for more details. + * The format should be: + * - Header block is fixed at 4 bytes + * The header block contains the ELD version and baseline ELD len as + * well as some reserved fields. + * - Baseline block for audio descriptors is 76 bytes + * (15 SAD; each SAD=3 bytes requiring 45 bytes with 31 bytes to spare) + * As well as some other bits used to denote the CEA version, + * the speaker allocation data, monitor name, connector type, and + * hdcp capabilities. + * - Vendor specific block of 16 bytes + * maxFreqSupported + * Supply the maximum frequency supported for the overall audio caps. + * This value should match CEA861-X defines for sample freq. + * ctrl: + * NV0073_CTRL_DFP_SET_ELD_AUDIO_CAPS_CTRL_PD: + * Specifies the presence detect of the receiver. On a hotplug + * or modeset client should set this bit to TRUE. + * NV0073_CTRL_DFP_SET_ELD_AUDIO_CAPS_CTRL_ELDV: + * Specifies whether the ELD buffer contents are valid. + * An intrinsic unsolicited response (UR) is generated whenever + * the ELDV bit changes in value and the PD=1. When _PD=1(hotplug), + * RM will set the ELDV bit after ELD buffer contents are written. + * If _ELDV bit is set to false such as during a unplug, then the + * contents of the ELD buffer will be cleared. + * deviceEntry: + * The deviceEntry number from which the SF should accept packets. + * _NONE if disabling audio. + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_DFP_SET_ELD_AUDIO_CAPS (0x731144U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER 96U + +#define NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS_MESSAGE_ID (0x44U) + +typedef struct NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 numELDSize; + NvU8 bufferELD[NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER]; + NvU32 maxFreqSupported; + NvU32 ctrl; + NvU32 deviceEntry; +} NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS; + +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0320KHZ (0x00000001U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0441KHZ (0x00000002U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0480KHZ (0x00000003U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0882KHZ (0x00000004U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0960KHZ (0x00000005U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_1764KHZ (0x00000006U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_1920KHZ (0x00000007U) + +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD 0:0 +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV 1:1 +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV_TRUE (0x00000001U) + +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_0 (0x00000000U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_1 (0x00000001U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_2 (0x00000002U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_3 (0x00000003U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_NONE (0x00000007U) + + + +/* + * NV0073_CTRL_CMD_DFP_GET_SPREAD_SPECTRUM_STATUS + * + * This command is used to get spread spectrum status for a display device. + * + * displayId + * Display ID for which the spread spectrum status is needed. + * checkRMSsState + * Default is to check in Vbios. This flag lets this control call to check in register. + * status + * Return status value. + */ + +#define NV0073_CTRL_CMD_DFP_GET_SPREAD_SPECTRUM (0x73114cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS_MESSAGE_ID (0x4CU) + +typedef struct NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS { + NvU32 displayId; + NvBool enabled; +} NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS; + +/* + * NV0073_CTRL_CMD_DFP_UPDATE_DYNAMIC_DFP_CACHE + * + * Update the Dynamic DFP with Bcaps read from remote display. + * Also updates hdcpFlags, gpu hdcp capable flags in DFP. + * If bResetDfp is true, all the flags are reset before making changes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_DFP_UPDATE_DYNAMIC_DFP_CACHE (0x73114eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS_MESSAGE_ID (0x4EU) + +typedef struct NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS { + NvU32 subDeviceInstance; + NvU32 headIndex; + NvU8 bcaps; + NvU8 bksv[5]; + NvU32 hdcpFlags; + NvBool bHdcpCapable; + NvBool bResetDfp; + NvU8 updateMask; +} NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS; + +#define NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_MASK_BCAPS 0x01U +#define NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_MASK_BKSV 0x02U +#define NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_MASK_FLAGS 0x03U + +/* + * NV0073_CTRL_CMD_DFP_SET_AUDIO_ENABLE + * + * This command sets the audio enable state of the DFP. When disabled, + * no audio stream packets or audio timestamp packets will be sent. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the dfp + * audio should be enabled or disabled. The display ID must be a dfp display. + * If the displayId is not a dfp, this call will return + * NV_ERR_INVALID_ARGUMENT. + * enable + * This parameter specifies whether to enable (NV_TRUE) or disable (NV_FALSE) + * audio to the display. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * + */ +#define NV0073_CTRL_CMD_DFP_SET_AUDIO_ENABLE (0x731150U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS_MESSAGE_ID (0x50U) + +typedef struct NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool enable; +} NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS; + + +/* + * NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG + * + * This variable specifies default/primary/secondary sor sublinks to be configured. + * These access modes are: + * + * NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_NONE + * Default link config + * NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_PRIMARY_SOR_LINK + * Primary sor sublink to be configured + * NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_SECONDARY_SOR_LINK + * Secondary sor sublink to be configured + */ +typedef NvU32 NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG; + +#define NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_NONE (0x0U) +#define NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_PRIMARY_SOR_LINK (0x1U) +#define NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_SECONDARY_SOR_LINK (0x2U) + +/* + * NV0073_CTRL_DFP_ASSIGN_SOR_INFO + * + * This structure describes info about assigned SOR + * + * displayMask + * The displayMask for the SOR corresponding to its HW routings + * sorType + * This parameter specifies the SOR type + * Here are the current defined fields: + * NV0073_CTRL_DFP_SOR_TYPE_NONE + * Unallocated SOR + * NV0073_CTRL_DFP_SOR_TYPE_2H1OR_PRIMARY + * Primary SOR for 2H1OR stream + * NV0073_CTRL_DFP_SOR_TYPE_2H1OR_SECONDARY + * Secondary SOR for 2H1OR stream + * NV0073_CTRL_DFP_SOR_TYPE_SINGLE + * Default Single SOR + * Note - sorType should only be referred to identify 2H1OR Primary and Secondary SOR + * + */ + +typedef struct NV0073_CTRL_DFP_ASSIGN_SOR_INFO { + NvU32 displayMask; + NvU32 sorType; +} NV0073_CTRL_DFP_ASSIGN_SOR_INFO; + +#define NV0073_CTRL_DFP_SOR_TYPE_NONE (0x00000000U) +#define NV0073_CTRL_DFP_SOR_TYPE_SINGLE (0x00000001U) +#define NV0073_CTRL_DFP_SOR_TYPE_2H1OR_PRIMARY (0x00000002U) +#define NV0073_CTRL_DFP_SOR_TYPE_2H1OR_SECONDARY (0x00000003U) + +/* + * NV0073_CTRL_CMD_DFP_ASSIGN_SOR + * + * This command is used by the clients to assign SOR to DFP for CROSS-BAR + * when the default SOR-DFP routing that comes from vbios is not considered. + * SOR shall be assigned to a DFP at the runtime. This call should be called + * before a modeset is done on any dfp display and also before LinkTraining for DP displays. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * DisplayId of the primary display for which SOR is to be assigned. However, if + * displayId is 0 then RM shall return the XBAR config it has stored in it's structures. + * sorExcludeMask + * sorMask of the SORs which should not be used for assignment. If this is 0, + * then SW is free to allocate any available SOR. + * slaveDisplayId + * displayId of the slave device in case of dualSST mode. This ctrl call will + * allocate SORs to both slave and the master if slaveDisplayId is set. + * forceSublinkConfig + * forces RM to configure primary or secondary sor sublink on the given diaplayId. + * If not set, then RM will do the default configurations. + * bIs2Head1Or + * Specifies that SOR allocation is required for 2 head 1 OR. This will allocate + * 2 SOR for same displayId - one Master and one Slave. Slave SOR would be disconnected + * from any padlink and get feedback clock from Master SOR's padlink. + * sorAssignList[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS] + * returns the displayMask for all SORs corresponding to their HW routings. + * sorAssignListWithTag[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS] + * returns the displayMask for all SORs corresponding to their HW routings along with + * SOR type to identify 2H1OR Primary and Secondary SORs. SOR type would be identified by + * NV0073_CTRL_DFP_SOR_TYPE. sorAssignList would look as below - + * sorAssignListWithTag[] = { DisplayMask, SOR Type + * {0x100, SECONDARY_SOR} + * {0x200, SINGLE_SOR} + * {0x100, PRIMARY_SOR} + * {0, NONE}} + * } + * Here, for display id = 0x100, SOR2 is Primary and SOR0 is Secondary. + * Note - sorAssignList parameter would be removed after Bug 200749158 is resolved + * reservedSorMask + * returns the sorMask reserved for the internal panels. + * flags + * Other detail settings. + * _AUDIO_OPTIMAL: Client requests trying to get audio SOR if possible. + * If there's no audio capable SOR and OD is HDMI/DP, + * RM will fail the control call. + * _AUDIO_DEFAULT: RM does not check audio-capability of SOR. + * + * _ACTIVE_SOR_NOT_AUDIO_CAPABLE_YES : RM returns Active SOR which is not Audio capable. + * _ACTIVE_SOR_NOT_AUDIO_CAPABLE_NO : RM is not returning 'Active non-audio capable SOR'. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + + +#define NV0073_CTRL_CMD_DFP_ASSIGN_SOR (0x731152U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS 4U + +#define NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS_MESSAGE_ID (0x52U) + +typedef struct NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU8 sorExcludeMask; + NvU32 slaveDisplayId; + NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG forceSublinkConfig; + NvBool bIs2Head1Or; + NvU32 sorAssignList[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS]; + NV0073_CTRL_DFP_ASSIGN_SOR_INFO sorAssignListWithTag[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS]; + NvU8 reservedSorMask; + NvU32 flags; +} NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS; + +#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO 0:0 +#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO_OPTIMAL (0x00000001U) +#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO_DEFAULT (0x00000000U) +#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE 1:1 +#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE_NO (0x00000000U) +#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE_YES (0x00000001U) + +/* +* NV0073_CTRL_CMD_DFP_GET_PADLINK_MASK +* +* This command will only be used by chipTB tests to get the padlinks corresponding +* to the given displayId. RM gets this information from vbios. This control call is +* only for verif purpose. +* +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. This parameter must specify a value between zero and the +* total number of subdevices within the parent device. This parameter +* should be set to zero for default behavior. +* displayId +* DisplayId of the display for which the client needs analog link Mask +* padlinkMask +* analogLinkMask for the given displayId. This value returned is 0xffffffff if +* the given displayId is invalid else RM returns the corresponding padlinkMask. +* NV_OK +* NV_ERR_INVALID_ARGUMENT +* NV_ERR_NOT_SUPPORTED +*/ + + +#define NV0073_CTRL_CMD_DFP_GET_PADLINK_MASK (0x731153U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS_MESSAGE_ID (0x53U) + +typedef struct NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 padlinkMask; +} NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS; + +/* + * NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE + * This enum defines the functions that are supported for which a + * corresponding GPIO pin number could be retrieved + * Values copied from objgpio.h GPIO_FUNC_TYPE_LCD_*. Please keep the + * values in sync between the 2 files + */ + +typedef enum NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE { + // GPIO types of LCD GPIO functions common to all internal panels + NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_BACKLIGHT = 268435456, + NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_POWER = 285212672, + NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_POWER_OK = 301989888, + NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_SELF_TEST = 318767104, + NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_LAMP_STATUS = 335544320, + NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_BRIGHTNESS = 352321536, +} NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE; + +/* + * NV0073_CTRL_CMD_DFP_GET_LCD_GPIO_PIN_NUM + * + * This command can be used to get the GPIO pin number that corresponds to one + * of the LCD functions + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the dfp display. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NVOS_STATUS_ERROR_INVALID_ARGUMENT. + * funcType + * The LDC function for which the GPIO pin number is needed + * lcdGpioPinNum + * The GPIO pin number that corresponds to the LCD function. + * +*/ +#define NV0073_CTRL_CMD_DFP_GET_LCD_GPIO_PIN_NUM (0x731154U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS_MESSAGE_ID (0x54U) + +typedef struct NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE funcType; + NvU32 lcdGpioPinNum; +} NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS; + + + +/* + * NV0073_CTRL_CMD_DFP_CONFIG_TWO_HEAD_ONE_OR + * + * This command is used for configuration of 2 head 1 OR. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * Display Id of the panel for which Two Head One OR is going to be used + * bEnable + * Enable/Disable 2 Head 1 OR + * masterSorIdx + * Master SOR Index which will send pixels to panel + * slaveSorIdx + * Slave SOR Index which will take feedback clock from Master SOR's + * padlink + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + * NVOS_STATUS_ERROR_INVALID_ARGUMENT + * NVOS_STATUS_ERROR_NOT_SUPPORTED + */ + + +#define NV0073_CTRL_CMD_DFP_CONFIG_TWO_HEAD_ONE_OR (0x731156U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS_MESSAGE_ID (0x56U) + +typedef struct NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bEnable; + NvU32 masterSorIdx; + NvU32 slaveSorIdx; +} NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS; + +/* + * NV0073_CTRL_CMD_DFP_DSC_CRC_CONTROL + * + * This command is used to enable/disable CRC on the GPU or query the registers + * related to it + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * headIndex + * index of the head + * cmd + * specifying if setup or querying is done + * bEnable + * enable or disable CRC on the GPU + * gpuCrc0 + * 0-indexed CRC register of the GPU + * gpuCrc1 + * 1-indexed CRC register of the GPU + * gpuCrc0 + * 2-indexed CRC register of the GPU + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + * NVOS_STATUS_ERROR_NOT_SUPPORTED + */ + + +#define NV0073_CTRL_CMD_DFP_DSC_CRC_CONTROL (0x731157U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS_MESSAGE_ID (0x57U) + +typedef struct NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS { + NvU32 subDeviceInstance; + NvU32 headIndex; + NvU32 cmd; + NvBool bEnable; + NvU16 gpuCrc0; + NvU16 gpuCrc1; + NvU16 gpuCrc2; +} NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS; + +#define NV0073_CTRL_DP_CRC_CONTROL_CMD 0:0 +#define NV0073_CTRL_DP_CRC_CONTROL_CMD_SETUP (0x00000000U) +#define NV0073_CTRL_DP_CRC_CONTROL_CMD_QUERY (0x00000001U) + +/* + * NV0073_CTRL_CMD_DFP_INIT_MUX_DATA + * + * This control call is used to configure the display MUX related data + * for the given display device. Clients to RM are expected to call this + * control call to initialize the data related to MUX before any MUX related + * operations such mux switch or PSR entry/ exit are performed. + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId (in) + * ID of the display device for which the mux state has to be initialized + * manfId (in) + * Specifies the manufacturer ID of panel obtained from the EDID. This + * parameter is expected to be non-zero only in case of internal panel. + * productId (in) + * Specifies the product ID of panel obtained from the EDID. This + * parameter is expected to be non-zero only in case of internal panel. + * tconId (out) + * RM provides an enumerated TCON specific value to help the client + * identify the panel TCON. Clients can refer to the enum from sdk/nvidia/inc/dds_tcon_db.h + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_DFP_INIT_MUX_DATA (0x731158U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS_MESSAGE_ID (0x58U) + +typedef struct NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU16 manfId; + NvU16 productId; + NvU16 tconId; +} NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS; + + + +/* + * NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX + * + * This command is used to switch the dynamic display mux between + * integrated GPU and discrete GPU. + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId (in) + * ID of the display device for which the display MUX has to be switched + * flags (in) + * Flags indicating the action to be performed. Here are the possible + * valid values- + * NV0073_CTRL_DFP_DISP_MUX_SWITCH_IGPU_TO_DGPU + * When set mux is switched from integrated to discrete GPU. + * NV0073_CTRL_DFP_DISP_MUX_SWITCH_DGPU_TO_IGPU + * When set mux is switched from discrete to integrated GPU. + * NV0073_CTRL_DFP_DISP_MUX_SWITCH_SKIP_SIDEBAND_ACCESS + * Set to true for PSR panels as we skip sideband access. + * auxSettleDelay (in) + * Time, in milliseconds, necessary for AUX channel to settle and become + * accessible after a mux switch. Set to zero to use the default delay. + * muxSwitchLatencyMs (out) + * mux switch latency stats in milli-seconds + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX (0x731160U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS_MESSAGE_ID (0x60U) + +typedef struct NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 flags; + NvU32 auxSettleDelay; + NvU32 muxSwitchLatencyMs; +} NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS; + +/* valid flags*/ +#define NV0073_CTRL_DFP_DISP_MUX_SWITCH 0:0 +#define NV0073_CTRL_DFP_DISP_MUX_SWITCH_IGPU_TO_DGPU 0x00000000 +#define NV0073_CTRL_DFP_DISP_MUX_SWITCH_DGPU_TO_IGPU 0x00000001 +#define NV0073_CTRL_DFP_DISP_MUX_SWITCH_SKIP_SIDEBAND_ACCESS 1:1 +#define NV0073_CTRL_DFP_DISP_MUX_SWITCH_SKIP_SIDEBAND_ACCESS_YES 0x00000001 +#define NV0073_CTRL_DFP_DISP_MUX_SWITCH_SKIP_SIDEBAND_ACCESS_NO 0x00000000 + +/* + * NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS + * + * This command is used to perform all the operations that need to be + * performed before a mux switch is started. + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId (in) + * ID of the display device for which the pre mux switch operations have + * to be performed. + * flags (in) + * Flags indicating the action to be performed. Here are the possible + * valid values - + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_IGPU_TO_DGPU + * Indicates a switch from i to d is initiated + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_DGPU_TO_IGPU + * Indicates a switch from d to i is initiated + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP_NO + * When set RM will execute the PSR enter sequence. By default RM will + * not skip SR enter sequence + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP_YES + * When set RM will skip the PSR enter sequence + * iGpuBrightness (in) + * iGPU brightness value (scale 0~100) before switching mux from I2D. + * This is used to match brightness after switching mux to dGPU + * preOpsLatencyMs (out) + * premux switch operations latency stats in milli-seconds. This includes - + * - disabling SOR sequencer and enable BL GPIO control + * - toggling LCD VDD, BL EN and PWM MUX GPIOs + * - PSR entry, if not skipped + * psrEntryLatencyMs (out) + * psr entry latency stats in milli-seconds + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS (0x731161U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS_MESSAGE_ID (0x61U) + +typedef struct NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 flags; + NvU32 iGpuBrightness; + NvU32 preOpsLatencyMs; + NvU32 psrEntryLatencyMs; +} NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS; + +/* valid flags*/ +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE 0:0 +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_IGPU_TO_DGPU 0x00000000U +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_DGPU_TO_IGPU 0x00000001U +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP 1:1 +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP_NO 0x00000000U +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP_YES 0x00000001U +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING 2:2 +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_KNOWN 0x00000000 +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_UNKNOWN 0x00000001 +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SKIP_BACKLIGHT_ENABLE 3:3 +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SKIP_BACKLIGHT_ENABLE_NO 0x00000000U +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SKIP_BACKLIGHT_ENABLE_YES 0x00000001U + +#define NV0073_CTRL_DISP_MUX_BACKLIGHT_BRIGHTNESS_MIN 0U +#define NV0073_CTRL_DISP_MUX_BACKLIGHT_BRIGHTNESS_MAX 100U + +/* + * NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS + * + * This command is used to perform all the operations that need to be + * performed after a successful mux switch is completed. + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId (in) + * ID of the display device for which the post mux switch operations have + * to be performed. + * flags (in) + * Flags indicating the action to be performed. Here are the possible + * valid values - + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_IGPU_TO_DGPU + * Indicates a switch from i to d is initiated + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_DGPU_TO_IGPU + * Indicates a switch from d to i is initiated + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP_NO + * When set RM will execute the PSR exit sequence. By default RM will + * not skip SR exit sequence + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP_YES + * When set RM will skip the PSR exit sequence + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_KNOWN + * Indicates mux switches where we know when igpu powers up + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_UNKNOWN + * Indicates mux switches where we don't know when igpu powers up + * postOpsLatencyMs (out) + * postmux switch operations latency stats in milli-seconds. This includes - + * - restoring SOR sequencer and BL GPIO control + * - toggling LCD VDD, BL EN and PWM MUX GPIOs + * - PSR exit, if not skipped + * psrExitLatencyMs (out) + * psr exit latency stats in milli-seconds + * psrExitTransitionToInactiveLatencyMs (out) + * psr exit latency stats in milli-seconds, from state 2 (SR active) to state 4 (transition to inactive) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_TIMEOUT in case of SR exit failure + */ + +#define NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS (0x731162U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS_MESSAGE_ID (0x62U) + +typedef struct NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 flags; + NvU32 postOpsLatencyMs; + NvU32 psrExitLatencyMs; + NvU32 psrExitTransitionToInactiveLatencyMs; +} NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS; + +/* valid flags*/ +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE 0:0 +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP 1:1 +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP_NO 0x00000000U +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP_YES 0x00000001U + +/* + * NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS + * + * This command is used to query the display mux status for the given + * display device + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId (in) + * ID of the display device for which the post mux switch operations have + * to be performed. + * muxStatus (out) + * status indicating the current state of the mux. + * valid values - + * NV0073_CTRL_DFP_DISP_MUX_STATE_INTEGRATED_GPU + * Indicates that the MUX is currently switched to integrated GPU. + * NV0073_CTRL_DFP_DISP_MUX_STATE_DISCRETE_GPU + * Indicates that the MUX is currently switched to discrete GPU. + * NV0073_CTRL_DFP_DISP_MUX_MODE_DISCRETE_ONLY + * Indicates that the MUX mode is set to discrete mode, where all displays + * are driven by discrete GPU. + * NV0073_CTRL_DFP_DISP_MUX_MODE_INTEGRATED_ONLY + * Indicates that the MUX mode is set to integrated mode, where all + * displays are driven by Integrated GPU. + * NV0073_CTRL_DFP_DISP_MUX_MODE_HYBRID + * Indicates that the MUX mode is set to hybrid, where internal panel is + * driven by integrated GPU, while external displays might be driven by + * discrete GPU. + * NV0073_CTRL_DFP_DISP_MUX_MODE_DYNAMIC + * Indicates that the MUX mode is dynamic. It is only in this mode, the + * display MUX can be toggled between discrete and hybrid dynamically. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS (0x731163U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS_MESSAGE_ID (0x63U) + +typedef struct NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 muxStatus; +} NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS; + +/* valid flags */ +#define NV0073_CTRL_DFP_DISP_MUX_STATE 1:0 +#define NV0073_CTRL_DFP_DISP_MUX_STATE_INVALID 0x00000000U +#define NV0073_CTRL_DFP_DISP_MUX_STATE_INTEGRATED_GPU 0x00000001U +#define NV0073_CTRL_DFP_DISP_MUX_STATE_DISCRETE_GPU 0x00000002U +#define NV0073_CTRL_DFP_DISP_MUX_MODE 4:2 +#define NV0073_CTRL_DFP_DISP_MUX_MODE_INVALID 0x00000000U +#define NV0073_CTRL_DFP_DISP_MUX_MODE_INTEGRATED_ONLY 0x00000001U +#define NV0073_CTRL_DFP_DISP_MUX_MODE_DISCRETE_ONLY 0x00000002U +#define NV0073_CTRL_DFP_DISP_MUX_MODE_HYBRID 0x00000003U +#define NV0073_CTRL_DFP_DISP_MUX_MODE_DYNAMIC 0x00000004U + + + +/* +* NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING +* +* This command can be used to get DSI mode timing parameters. +* +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. This parameter must specify a value between zero and the +* total number of subdevices within the parent device. This parameter +* should be set to zero for default behavior. +* displayId +* This parameter specifies the ID of the display on which the DSI +* info will be set. The display ID must be a DSI-capable display. +* hActive +* This parameter specifies the horizontal length of the active pixel +* data in the raster. +* vActive +* This parameter specifies the vertical lines of the active pixel +* data in the raster. +* hFrontPorch +* This parameter specifies the number of horizontal front porch +* blanking pixels in the raster. +* vFrontPorch +* This parameter specifies the numer of lines of the vertical front +* porch in the raster. +* hBackPorch +* This parameter specifies the number of horizontal back porch +* blanking pixels in the raster. +* vBackPorch +* This parameter specifies the numer of lines of the vertical back +* porch in the raster. +* hSyncWidth +* This parameter specifies the number of horizontal sync pixels in +* the raster. +* vSyncWidth +* This parameter specifies the numer of lines of the vertical sync +* in the raster. +* bpp +* This parameter specifies the depth (Bits per Pixel) of the output +* display stream. +* refresh +* This parameter specifies the refresh rate of the panel (in Hz). +* pclkHz +* This parameter specifies the pixel clock rate in Hz. +* numLanes +* Number of DSI data lanes. +* dscEnable +* Flag to indicate if DSC an be enabled, which in turn indicates if +* panel supports DSC. +* dscBpp +* DSC Bits per pixel +* dscNumSlices +* Number of slices for DSC. +* dscDuaDsc +* Flag to indicate if panel supports DSC streams from two DSI +* controllers. +* dscSliceHeight +* Height of DSC slices. +* dscBlockPrediction +* Flag to indicate if DSC Block Prediction needs to be enabled. +* dscDecoderVersionMajor +* Major version number of DSC decoder on Panel. +* dscDecoderVersionMinor +* Minor version number of DSC decoder on Panel. +* dscUseCustomPPS +* Flag to indicate if Panel uses custom PPS values which deviate from standard values. +* dscCustomPPSData +* 32 bytes of custom PPS data required by Panel. +* dscEncoderCaps +* Capabilities of DSC encoder in SoC. +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_ARGUMENT +* NV_ERR_NOT_SUPPORTED +*/ + +#define NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING (0x731166U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DFP_DSI_CUSTOM_PPS_DATA_COUNT 32U + +#define NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS_MESSAGE_ID (0x66U) + +typedef struct NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 hActive; + NvU32 vActive; + NvU32 hFrontPorch; + NvU32 vFrontPorch; + NvU32 hBackPorch; + NvU32 vBackPorch; + NvU32 hSyncWidth; + NvU32 vSyncWidth; + NvU32 bpp; + NvU32 refresh; + NvU32 pclkHz; + NvU32 numLanes; + NvU32 dscEnable; + NvU32 dscBpp; + NvU32 dscNumSlices; + NvU32 dscDualDsc; + NvU32 dscSliceHeight; + NvU32 dscBlockPrediction; + NvU32 dscDecoderVersionMajor; + NvU32 dscDecoderVersionMinor; + NvBool dscUseCustomPPS; + NvU32 dscCustomPPSData[NV0073_CTRL_CMD_DFP_DSI_CUSTOM_PPS_DATA_COUNT]; + NV0073_CTRL_CMD_DSC_CAP_PARAMS dscEncoderCaps; +} NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS; + + + +/* + * NV0073_CTRL_CMD_DFP_GET_FIXED_MODE_TIMING + * + * This control call is used to retrieve the display mode timing info that's + * specified for a given DFP from an offline configuration blob (e.g., Device Tree). + * This display timing info is intended to replace the timings exposed in a + * sink's EDID. + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId (in) + * ID of the display device for which the timings should be retrieved. + * stream (in) + * For MST connectors with static topologies (e.g., DP serializers), + * this parameter further identifies the video stream for which the + * timings should be retrieved. + * valid (out) + * Indicates whether a valid display timing was found for this DFP. + * hActive (out) + * Horizontal active width in pixels + * hFrontPorch (out) + * Horizontal front porch + * hSyncWidth (out) + * Horizontal sync width + * hBackPorch (out) + * Horizontal back porch + * vActive (out) + * Vertical active height in lines + * vFrontPorch (out) + * Vertical front porch + * vSyncWidth (out) + * Vertical sync width + * vBackPorch (out) + * Vertical back porch + * pclkKHz (out) + * Pixel clock frequency in KHz + * rrx1k (out) + * Refresh rate in units of 0.001Hz +* x (out) +* x offset inside superframe at which this view starts + * y (out) +* y offset inside superframe at which this view starts + * width (out) +* Horizontal active width in pixels for this view +* height (out) +* Vertical active height in lines for this view + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_DFP_GET_FIXED_MODE_TIMING (0x731172) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8 | NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS_MESSAGE_ID)" */ + +#define NV0073_CTRL_DFP_FIXED_MODE_TIMING_MAX_SUPERFRAME_VIEWS 4U + +#define NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS_MESSAGE_ID (0x72U) + +typedef struct NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU8 stream; + + NvBool valid; + + NvU16 hActive; + NvU16 hFrontPorch; + NvU16 hSyncWidth; + NvU16 hBackPorch; + + NvU16 vActive; + NvU16 vFrontPorch; + NvU16 vSyncWidth; + NvU16 vBackPorch; + + NvU32 pclkKHz; + NvU32 rrx1k; + + struct { + NvU8 numViews; + struct { + NvU16 x; + NvU16 y; + NvU16 width; + NvU16 height; + } view[NV0073_CTRL_DFP_FIXED_MODE_TIMING_MAX_SUPERFRAME_VIEWS]; + } superframeInfo; +} NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS; + + + +/* + * NV0073_CTRL_DFP_ENTER_DISPLAY_POWER_GATING_DIAGNOSTIC_DATA + * + * This structure describes diagnostic information about display power + * gating entry sequence + * + * totalRmEntryLatencyUs + * Duration in microseconds that RM took to service 'Enter + * Display Power Gating' command. This includes time for all + * steps that RM performs as part of display power gating entry + * sequence including the below parameters. + * hwOkToGateLatencyUs + * Duration in microseconds that HW took to assert ok_to_gate. + * Only valid when displayId is not equal to 0xFFFFFFFF + * carApiLatencyUs + * Duration in microseconds that CAR (Clock and Reset) block took to + * service 'Enter Display Power Gating' command + * + */ + +typedef struct NV0073_CTRL_DFP_ENTER_DISPLAY_POWER_GATING_DIAGNOSTIC_DATA { + NvU32 totalRmEntryLatencyUs; + NvU32 hwOkToGateLatencyUs; + NvU32 carEntryApiLatencyUs; +} NV0073_CTRL_DFP_ENTER_DISPLAY_POWER_GATING_DIAGNOSTIC_DATA; + +/* + * NV0073_CTRL_CMD_DFP_ENTER_DISPLAY_POWER_GATING + * + * This command can be used to enter display power gating with an option to + * save-restore settings for the specified displayId. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the state + * needs to be saved-restored during exit of Display Power Gating. + * The display ID must be a dfp display as determined with the + * NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. If more than one + * displayId bit is set or the displayId is not a dfp, this call will + * return NV_ERR_INVALID_ARGUMENT. For the case where no save-restore + * is needed, displayId should be set to 0xFFFFFFFF. + * flags + * This parameter specifies special request from client for RM(for future use) + * diagnosticData + * This parameter provides diagnostic information about display power + * gating entry sequence + * + * Possible status values returned are: + * NV_OK - If Display Power Gating Entry was successful + * NV_ERR_GENERIC - If Display Power Gating Entry failed + * NV_ERR_INVALID_ARGUMENT - If incorrect parameters are sent + */ +#define NV0073_CTRL_CMD_DFP_ENTER_DISPLAY_POWER_GATING (0x731174U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_ENTER_DISPLAY_POWER_GATING_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DFP_ENTER_DISPLAY_POWER_GATING_PARAMS_MESSAGE_ID (0x74U) + +typedef struct NV0073_CTRL_CMD_DFP_ENTER_DISPLAY_POWER_GATING_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 flag; + NV0073_CTRL_DFP_ENTER_DISPLAY_POWER_GATING_DIAGNOSTIC_DATA diagnosticData; +} NV0073_CTRL_CMD_DFP_ENTER_DISPLAY_POWER_GATING_PARAMS; + +#define NV0073_CTRL_DFP_ENTER_DISPLAY_POWER_GATING_FLAGS_RESERVED 31:0 +#define NV0073_CTRL_DFP_ENTER_DISPLAY_POWER_GATING_FLAGS_RESERVED_INIT (0x00000000U) + +/* + * NV0073_CTRL_DFP_EXIT_DISPLAY_POWER_GATING_DIAGNOSTIC_DATA + * + * This structure describes diagnostic information about display power + * gating exit sequence + * + * totalRmExitLatencyUs + * Duration in microseconds that RM took to service 'Exit + * Display Power Gating' command. This includes time for all + * steps that RM performs as part of display power gating exit + * sequence including the below parameters. + * riscvBootupLatencyUs + * Duration in microseconds that LTM RISCV took to bootup. + * carExitApiLatencyUs + * Duration in microseconds that CAR (Clock and Reset) block took + * to service 'Exit Display Power Gating' command + * + */ +typedef struct NV0073_CTRL_DFP_EXIT_DISPLAY_POWER_GATING_DIAGNOSTIC_DATA { + NvU32 totalRmExitLatencyUs; + NvU32 riscvBootupLatencyUs; + NvU32 carExitApiLatencyUs; +} NV0073_CTRL_DFP_EXIT_DISPLAY_POWER_GATING_DIAGNOSTIC_DATA; + +/* + * NV0073_CTRL_CMD_DFP_EXIT_DISPLAY_POWER_GATING + * + * This command can be used to exit display power gating. If preceding + * NV0073_CTRL_CMD_DFP_ENTER_DISPLAY_POWER_GATING command requested for + * save-restore of settings for a particular displayId then this command + * will restore settings for that displayId. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * flags + * This parameter specifies special request from client for RM(for future use) + * diagnosticData + * This parameter provides diagnostic information about display power + * gating exit sequence + * + * Possible status values returned are: + * NV_OK - When Display Power Gating Exit was successful + * NV_ERR_GENERIC - When Display Power Gating Exit failed + * NV_ERR_INVALID_ARGUMENT - When incorrect parameters are sent + */ + +#define NV0073_CTRL_CMD_DFP_EXIT_DISPLAY_POWER_GATING (0x731175U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_EXIT_DISPLAY_POWER_GATING_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DFP_EXIT_DISPLAY_POWER_GATING_PARAMS_MESSAGE_ID (0x75U) + +typedef struct NV0073_CTRL_CMD_DFP_EXIT_DISPLAY_POWER_GATING_PARAMS { + NvU32 subDeviceInstance; + NvU32 flag; + NV0073_CTRL_DFP_EXIT_DISPLAY_POWER_GATING_DIAGNOSTIC_DATA diagnosticData; +} NV0073_CTRL_CMD_DFP_EXIT_DISPLAY_POWER_GATING_PARAMS; + +#define NV0073_CTRL_DFP_EXIT_DISPLAY_POWER_GATING_FLAGS_RESERVED 31:0 +#define NV0073_CTRL_DFP_EXIT_DISPLAY_POWER_GATING_FLAGS_RESERVED_INIT (0x00000000U) + +/* + * NV0073_CTRL_CMD_DFP_EDP_DRIVER_UNLOAD + * + * This command is called when we want to inform RM of driver + * unload. + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation + * should be directed. + * displayId (in) + * This parameter inputs the displayId of the active display. A value + * of zero indicates no display is active. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_DFP_EDP_DRIVER_UNLOAD (0x731176U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS_MESSAGE_ID (0x76U) + +typedef struct NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; +} NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_SET_REGION_RAM_RECTANGLES + * + * @brief + * This command can be used to program the Rectangle regions info into + * Region RAM. These Rectangle regions are then used as regions of interest + * for Tell Tale and Frozen Frame detection. + * + * Some NVDisplay hardware has an internal RAM to support TellTale(TT) + * and Frozen Frame(FF) features. Each entry in this RAM is simply defined + * as a rectangle (x/y position, width and height). RM will load the region + * RAM with rectangle entries using PDISP registers. + * + * Several new Core/Window methods have been added. These methods can be + * programmed to specify which rectangle resources would be enabled and inform + * hw to start using for TT/FF checking. There are also methods that can be used + * to configure the manner of checking (e.g., for frozen frame detection, how + * many regions need to be frozen for how many frames before it's considered as + * a fault). As part of these methods, need to specify the index of the region + * RAM entry (rectangle) that needs to be checked. This ID is already specified + * for each rectangle as part of the info that was programmed by RM to Region RAM. + * + * The rectangles loaded onto Region RAM are not specifically tied to the current + * mode, and do not have to be coupled with only one single mode. Based on the + * current raster size, it is expected that the RM clients would choose the + * Rectangles that are within the raster size. Once TT/FF checking is enabled, + * Display HW continuously checks and will raise an interrupt event if detects an + * error case. If a rectangle resource is chosen that "doesn't fit" the current + * raster size, overlaps with another rectangle resource, etc, then HW will + * generate an exception for these invalid states. + * + * @params + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * numRectangles + * This parameter specifies the number of rectangles whose region info + * has been passed as part of this control call + * rectanglesInfo::rectangleID + * This parameter provides the ID of the rectangle which will be used + * to identify the rectangle during methods programming for TellTale + * or Frozen Frame detection. + * rectanglesInfo::xCoordinate + * This parameter specifies the x-coordinate of the top left corner of + * the rectangle in the viewport. + * rectanglesInfo::yCoordinate + * This parameter specifies the y-coordinate of the top left corner of + * the rectangle in the viewport. + * rectanglesInfo::width + * This parameter specifies the width of the rectangle. + * rectanglesInfo::height + * This parameter specifies the height of the rectangle. + * + * Possible status values returned are: + * NV_OK - Upon successfully programming Rectangles info to Region RAM + * NV_ERR_INVALID_ARGUMENT - When incorrect values are passed in arguments + */ +#define NV0073_CTRL_CMD_SYSTEM_SET_REGION_RAM_RECTANGLES (0x731177U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_SET_REGION_RAM_RECTANGLES_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_MAX_REGION_RAM_RECTANGLES 16U + +#define NV0073_CTRL_CMD_SYSTEM_SET_REGION_RAM_RECTANGLES_PARAMS_MESSAGE_ID (0x77U) + +typedef struct NV0073_CTRL_CMD_SYSTEM_SET_REGION_RAM_RECTANGLES_PARAMS { + NvU32 subDeviceInstance; + NvU8 numRectangles; + + struct { + NvU8 rectangleID; + NvU16 xCoordinate; + NvU16 yCoordinate; + NvU16 width; + NvU16 height; + } rectanglesInfo[NV0073_CTRL_CMD_SYSTEM_MAX_REGION_RAM_RECTANGLES]; +} NV0073_CTRL_CMD_SYSTEM_SET_REGION_RAM_RECTANGLES_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_CONFIGURE_SAFETY_INTERRUPTS + * + * This command can be used to set the interrupt handling mechanism (One-time + * or Continuous) of TellTale and FrozenFrame/Overlap events. Also, this command + * can be used to Enable/Disable the safety interrupts. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * tellTaleEvents + * The 'mode' variable holds the interrupt configuration values for + * TellTale events. Clients can specify whether the interrupt needs to + * be Disabled or Enabled Continuously or Enabled Only Once using the + * NV0073_CTRL_CMD_SYSTEM_SAFETY_INTERRUPT_MODE_* macros. ENABLE_ONLY_ONCE + * helps avoid interrupt storm by disabling the interrupt after the first + * event since Safety Interrupts are generated per frame. + * The 'specified' field should be used to specify if the 'mode' value at + * that index should be programmed as part of the control call handling + * function. This helps if Clients don't want to update the TellTale + * interrupt configuration of a particular tile in this instance of the + * control call invocation. If it is set to NV_TRUE, the 'mode' value + * will be programmed. If NV_FALSE, 'mode' value will not be programmed. + * frozenFrameEvents + * The 'mode' variable holds the interrupt configuration values for + * FrozenFrame events. Clients can specify whether the interrupt needs to + * be Disabled or Enabled Continuously or Enabled Only Once using the + * NV0073_CTRL_CMD_SYSTEM_SAFETY_INTERRUPT_MODE_* macros. ENABLE_ONLY_ONCE + * helps avoid interrupt storm by disabling the interrupt after the first + * event since Safety Interrupts are generated per frame. + * The 'specified' field should be used to specify if the 'mode' value at + * that index should be programmed as part of the control call handling + * function. This helps if Clients don't want to update the Frozen Frame + * interrupt configuration of a particular head in this instance of the + * control call invocation. If it is set to NV_TRUE, the 'mode' value + * will be programmed. If NV_FALSE, 'mode' value will not be programmed. + * overlapEvents + * The 'mode' variable holds the interrupt configuration values for + * Overlap events. Clients can specify whether the interrupt needs to + * be Disabled or Enabled Continuously or Enabled Only Once using the + * NV0073_CTRL_CMD_SYSTEM_SAFETY_INTERRUPT_MODE_* macros. ENABLE_ONLY_ONCE + * helps avoid interrupt storm by disabling the interrupt after the first + * event since Safety Interrupts are generated per frame. + * The 'specified' field should be used to specify if the 'mode' value at + * that index should be programmed as part of the control call handling + * function. This helps if Clients don't want to update the Overlap + * interrupt configuration of a particular tile in this instance of the + * control call invocation. If it is set to NV_TRUE, the 'mode' value + * will be programmed. If NV_FALSE, 'mode' value will not be programmed. + */ +/* + * NOTE: Though we have created tellTaleEvents, frozenFrameEvents and overlapEvents structs as + * arrays holding interrupt 'mode' for each Head/Tile, RM currently does not support + * configuring these interrupts per Head/Tile. This support is planned to be added in RM + * sometime later, but having the structures per Head/Tile helps in future-proofing the + * control call interface. + * Expectation from the clients is to set the same 'mode' value at all the indexes (for + * all Heads/Tiles). This specified 'mode' value will be globally applied for all + Heads/Tiles for now. + */ +#define NV0073_CTRL_CMD_SYSTEM_CONFIGURE_SAFETY_INTERRUPTS (0x731178U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_CONFIGURE_SAFETY_INTERRUPTS_PARAMS_MESSAGE_ID" */ + +/* + * Interrupt configuration values for Safety events + */ +#define NV0073_CTRL_CMD_SYSTEM_SAFETY_INTERRUPT_MODE_DISABLE 0U +#define NV0073_CTRL_CMD_SYSTEM_SAFETY_INTERRUPT_MODE_ENABLE_CONTINUOUS 1U +#define NV0073_CTRL_CMD_SYSTEM_SAFETY_INTERRUPT_MODE_ENABLE_ONLY_ONCE 2U +#define NV0073_CTRL_CMD_SYSTEM_SAFETY_INTERRUPT_MODE_RESERVED 3U + +/* + * Head and Tile count used to specify Safety interrupt configuration for each head/tile. + */ +#define NV0073_CTRL_CMD_SYSTEM_MAX_SAFETY_HEAD_COUNT 8U +#define NV0073_CTRL_CMD_SYSTEM_MAX_SAFETY_TILE_COUNT 8U + +#define NV0073_CTRL_CMD_SYSTEM_CONFIGURE_SAFETY_INTERRUPTS_PARAMS_MESSAGE_ID (0x78U) + +typedef struct NV0073_CTRL_CMD_SYSTEM_CONFIGURE_SAFETY_INTERRUPTS_PARAMS { + NvU32 subDeviceInstance; + + struct { + NvU8 mode; + NvBool specified; + } tellTaleEvents[NV0073_CTRL_CMD_SYSTEM_MAX_SAFETY_TILE_COUNT]; + + struct { + NvU8 mode; + NvBool specified; + } frozenFrameEvents[NV0073_CTRL_CMD_SYSTEM_MAX_SAFETY_HEAD_COUNT]; + + struct { + NvU8 mode; + NvBool specified; + } overlapEvents[NV0073_CTRL_CMD_SYSTEM_MAX_SAFETY_TILE_COUNT]; +} NV0073_CTRL_CMD_SYSTEM_CONFIGURE_SAFETY_INTERRUPTS_PARAMS; + +/* + * NV0073_CTRL_CMD_DFP_GET_DISP_PHY_INFO + * + * Return a high-level DISP PHY description that is independent of raw register + * encodings. Tools or firmware can use the information to reason about link + * routing and data-rate policy, etc. + * + * Parameters + * subDeviceInstance (in) + * Sub-device instance within NV04_DISPLAY_COMMON. + * + * edpClkSrc (out) enum NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC + * edpPllFreq (out) enum NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_SEL + * + * padLink[4] (out) One entry per DP Pad-Link (DP0...DP3): + * sorSel enum NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL + * mode enum NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE + * cableOrient enum NV0073_CTRL_DFP_DISP_PHY_CABLE_ORIENT + * modeStatusDone NvBool (Alt-mode exit / entry finished) + * safeMode enum NV0073_CTRL_DFP_DISP_PHY_TYPEC_SAFE_MODE + * + * tpllForceVal enum NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_VAL + * tpllForceEn NvBool (DA_XTP_LN_TPLL_SEL[16]) + * pllPwrSeqEn NvBool (DP_PHY_DIG_PLL_CTL_0[0]) + * pllPwrSeqState enum NV0073_CTRL_DFP_DISP_PHY_PLL_PWR_STATE + * bitRateSel enum NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_SEL + * pdCableIdA NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_A_INFO + * structured view of TOP_TYPEC_IPMUX_PD_CABLE_ID_A + * (DP-rate capability, pin sets, UHBR13.5 support, + * active component type, DP-AM version, ...) + * + * pdCableIdB NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_B_INFO + * structured view of TOP_TYPEC_IPMUX_PD_CABLE_ID_B + * (VCONN source indication) + * + * Status values + * NV_OK + * NV_ERR_INVALID_ARGUMENT invalid subDeviceInstance + * NV_ERR_NOT_SUPPORTED device doesn't have a display + */ + +#define NV0073_CTRL_DFP_DISP_DP_PADLINK_COUNT 4U + +// eDP clock source selection (EDP_PHY_DIG_MISC[3:0]) +typedef enum NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC { + NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC_NONE = 0, + NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC_SOR0 = 1, + NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC_SOR1 = 2, + NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC_SOR2 = 4, + NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC_SOR3 = 8, +} NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC; + +// eDP PLL frequency selector (EDP_PHY_DIG_BIT_RATE[3:0]) +typedef enum NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_SEL { + NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_1_62GHZ = 1, + NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_2_16GHZ = 2, + NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_2_43GHZ = 3, + NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_2_70GHZ = 4, + NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_3_24GHZ = 5, + NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_4_32GHZ = 6, + NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_5_40GHZ = 7, + NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_6_75GHZ = 8, + NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_8_10GHZ = 9, +} NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_SEL; + +// DP bit-rate selector (DP_PHY_DIG_BIT_RATE[2:0]) +typedef enum NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_SEL { + NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_1_62GHZ = 0, + NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_2_70GHZ = 1, + NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_5_40GHZ = 2, + NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_8_10GHZ = 3, + NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_10_00GHZ = 4, + NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_13_50GHZ = 5, + NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_20_00GHZ = 6, +} NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_SEL; + +// DP_PHY_DIG_MISC[3:0] +typedef enum NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL { + NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL_NONE = 0, + NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL_SOR0 = 1, + NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL_SOR1 = 2, + NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL_SOR2 = 3, + NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL_SOR3 = 4, +} NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL; + +// Type-C mux operating mode (TOP_TYPEC_IPMUX_CTRL[1:0]) +typedef enum NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE { + NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE_USB4_2T2R = 0, + NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE_USB3_2T2R = 1, + NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE_DP_4T = 2, + NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE_DP_2T_USB3_1T1R = 3, +} NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE; + +// Cable orientation (TOP_TYPEC_IPMUX_CTRL[2]) +typedef enum NV0073_CTRL_DFP_DISP_PHY_CABLE_ORIENT { + NV0073_CTRL_DFP_DISP_PHY_ORIENT_UNFLIPPED = 0, + NV0073_CTRL_DFP_DISP_PHY_ORIENT_FLIPPED = 1, +} NV0073_CTRL_DFP_DISP_PHY_CABLE_ORIENT; + +// Safe-mode control (TOP_TYPEC_IPMUX_CTRL[3]) +typedef enum NV0073_CTRL_DFP_DISP_PHY_TYPEC_SAFE_MODE { + NV0073_CTRL_DFP_DISP_PHY_TYPEC_SAFE_MODE_ENABLED = 0, // IP-MUX held in Safe-Mode + NV0073_CTRL_DFP_DISP_PHY_TYPEC_SAFE_MODE_ALT = 1, // Safe-Mode disabled so Alt-Mode allowed +} NV0073_CTRL_DFP_DISP_PHY_TYPEC_SAFE_MODE; + +// TPLL force-value codes (DA_XTP_LN_TPLL_SEL[15:8]) +typedef enum NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_VAL { + NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_RBR_UHBR13_5 = 57, // RBR / UHBR13.5 + NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_HBR_HBR2 = 89, // HBR / HBR2 + NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_HBR3 = 121, // HBR3 + NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_UHBR10_UHBR20 = 26, // UHBR10 / UHBR20 +} NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_VAL; + +// PLL power-sequence state (DP_PHY_DIG_PLL_CTL_0[2:1]) +typedef enum NV0073_CTRL_DFP_DISP_PHY_PLL_PWR_STATE { + NV0073_CTRL_DFP_DISP_PHY_PLL_STATE_PD = 0, + NV0073_CTRL_DFP_DISP_PHY_PLL_STATE_BIAS_ON = 1, + NV0073_CTRL_DFP_DISP_PHY_PLL_STATE_PLL_ON = 2, + NV0073_CTRL_DFP_DISP_PHY_PLL_STATE_LANE_ON = 3, +} NV0073_CTRL_DFP_DISP_PHY_PLL_PWR_STATE; + +// Supported DisplayPort data-rate capability (bits 5:2) +typedef enum NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT { + NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_NONE = 0, + NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UPTO_HBR3 = 1, + NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UHBR10_0 = 2, + NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UPTO_UHBR10_0 = 3, + NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UHBR20_0 = 4, + NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UPTO_HBR3_UHBR20_0 = 5, + NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UHBR10_0_UHBR20_0 = 6, + NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UPTO_UHBR20_0 = 7, +} NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT; + +// SRC / SINK pin-sets advertised by the cable (bits 15:8 / 23:16) +typedef enum NV0073_CTRL_DFP_DISP_PHY_PD_CBL_PIN_CAP { + NV0073_CTRL_DFP_DISP_PHY_PD_CBL_PIN_CD = 12, + NV0073_CTRL_DFP_DISP_PHY_PD_CBL_PIN_E = 16, +} NV0073_CTRL_DFP_DISP_PHY_PD_CBL_PIN_CAP; + +// UHBR13.5 support is Boolean, using NvBool + +// Active-component type (bits 29:28) +typedef enum NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_COMP { + NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_PASSIVE = 0, + NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_RETIMER = 1, + NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_REDRIVER = 2, + NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_OPTICAL = 3, +} NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_COMP; + +// DP Alt-Mode version supported by the cable (bits 31:30) +typedef enum NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DPAM_VERS { + NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DPAM_VERS_UPTO_2_0 = 0, + NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DPAM_VERS_2_1_OR_LATER = 1, +} NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DPAM_VERS; + +// VCONN source indication (Cable-ID-B bit 0) +typedef enum NV0073_CTRL_DFP_DISP_PHY_PD_CBL_VCONN_SRC { + NV0073_CTRL_DFP_DISP_PHY_PD_CBL_VCONN_SRC_DPTX = 0, + NV0073_CTRL_DFP_DISP_PHY_PD_CBL_VCONN_SRC_DPRX = 1, +} NV0073_CTRL_DFP_DISP_PHY_PD_CBL_VCONN_SRC; + +// DP mode indicating which type of DP connection is active +typedef enum NV0073_CTRL_DFP_DISP_PHY_DP_MODE { + NV0073_CTRL_DFP_DISP_PHY_DP_MODE_FSDP = 0, // Full Size DP + NV0073_CTRL_DFP_DISP_PHY_DP_MODE_ALT_MODE = 1, // DP Alt Mode + NV0073_CTRL_DFP_DISP_PHY_DP_MODE_TUNNELING = 2, // DP Tunneling +} NV0073_CTRL_DFP_DISP_PHY_DP_MODE; + +typedef struct NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_A_INFO { + NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT dpProt; + NV0073_CTRL_DFP_DISP_PHY_PD_CBL_PIN_CAP srcPinSet; + NV0073_CTRL_DFP_DISP_PHY_PD_CBL_PIN_CAP sinkPinSet; + NvBool bUhbr13_5; // bit 26 + NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_COMP activeComp; // bits 29:28 + NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DPAM_VERS dpamVers; // bits 31:30 +} NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_A_INFO; + +typedef struct NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_B_INFO { + NV0073_CTRL_DFP_DISP_PHY_PD_CBL_VCONN_SRC vconnSrc; // bit 0 +} NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_B_INFO; + +// DIA (Display Input Adapter) info for DP tunneling +typedef struct NV0073_CTRL_DFP_DISP_PHY_DIA_INFO { + NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL sorSel; // Which SOR for this DIA + NvBool bHpdActive; // HPD on the DIA (DP Tunneling Enabled) + NvBool bSorDpTunnelingEnabled; // SOR assigned to DIA (from sorSel) enabled for Tunneling + NvU32 sorClkMeasuredKHz; // Measured SOR clock rate in KHz (only valid for tunneling) + NvU32 sorClkProgrammedKHz; // Programmed SOR clock rate in KHz (only valid for tunneling) + NvBool bDownspreadEnabled; // 0.5% downspread enabled (DPCD 003h bit 0 && 107h bit 4) +} NV0073_CTRL_DFP_DISP_PHY_DIA_INFO; + +typedef struct NV0073_CTRL_DFP_DISP_PHY_PADLINK_INFO { + // Type-C mux status + NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE mode; // USB4_2T2R, etc + NV0073_CTRL_DFP_DISP_PHY_CABLE_ORIENT cableOrient; + NvBool bModeStatusDone; // Type-C IP-MUX has finished its "mode-change" power-down / power-up sequence when entering or exiting an alternate mode + NV0073_CTRL_DFP_DISP_PHY_TYPEC_SAFE_MODE safeMode; + + // Data-rate / PLL settings + NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_VAL tpllForceVal; + NvBool bTpllForceEn; // 0 = let hardware pick the appropriate TPLL settings automatically, 1 = force the TPLL to use tpllForceVal. + NvBool bPllPwrSeqEn; // 0 = normal automatic power-sequencer operation, 1 = override; the PHY obeys the explicit power state given in pllPwrSeqState. + NV0073_CTRL_DFP_DISP_PHY_PLL_PWR_STATE pllPwrSeqState; + NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_SEL bitRateSel; + + // USB-PD cable identification + NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_A_INFO pdCableIdA; + NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_B_INFO pdCableIdB; + + // HPD and DP mode info + NvBool bHpdActive; // HPD status: active (high) or inactive (low) + NV0073_CTRL_DFP_DISP_PHY_DP_MODE dpMode; // DP mode: FSDP, Alt Mode, or Tunneling + NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL sorSel; // SOR connected to padlink (for Alt Mode and FSDP) + NV0073_CTRL_DFP_DISP_PHY_DIA_INFO diaInfo[2]; + + // SOR clock rate info + NvU32 sorClkMeasuredKHz; // Measured SOR clock rate in KHz (from NV_PDISP_SOR_CLK_METER) + NvU32 sorClkProgrammedKHz; // Programmed SOR clock rate in KHz (from DPCD 00100h) + NvBool bDownspreadEnabled; // 0.5% downspread enabled (DPCD 003h bit 0 && 107h bit 4) +} NV0073_CTRL_DFP_DISP_PHY_PADLINK_INFO; + +#define NV0073_CTRL_CMD_DFP_GET_DISP_PHY_INFO (0x731180U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_DISP_PHY_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_GET_DISP_PHY_INFO_PARAMS_MESSAGE_ID (0x80U) + +typedef struct NV0073_CTRL_DFP_GET_DISP_PHY_INFO_PARAMS { + NvU32 subDeviceInstance; + + // eDP-wide settings + NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC edpClkSrc; + NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_SEL edpPllFreq; + + // Per-Pad-Link (DP0...DP3) information + NV0073_CTRL_DFP_DISP_PHY_PADLINK_INFO padLink[NV0073_CTRL_DFP_DISP_DP_PADLINK_COUNT]; +} NV0073_CTRL_DFP_GET_DISP_PHY_INFO_PARAMS; + +/* _ctrl0073dfp_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073dp.h b/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073dp.h new file mode 100644 index 0000000..ff4d340 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073dp.h @@ -0,0 +1,3731 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073dp.finn +// + +#include "ctrl/ctrl0073/ctrl0073base.h" +#include "ctrl/ctrl0073/ctrl0073common.h" + +#include "nvcfg_sdk.h" + +/* NV04_DISPLAY_COMMON dfp-display-specific control commands and parameters */ + +/* + * NV0073_CTRL_CMD_DP_AUXCH_CTRL + * + * This command can be used to perform an aux channel transaction to the + * displayPort receiver. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must a dfp display. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * bAddrOnly + * If set to NV_TRUE, this parameter prompts an address-only + * i2c-over-AUX transaction to be issued, if supported. Else the + * call fails with NVOS_STATUS_ERR_NOT_SUPPORTED. The size parameter is + * expected to be 0 for address-only transactions. + * cmd + * This parameter is an input to this command. The cmd parameter follows + * Section 2.4 AUX channel syntax in the DisplayPort spec. + * Here are the current defined fields: + * NV0073_CTRL_DP_AUXCH_CMD_TYPE + * This specifies the request command transaction + * NV0073_CTRL_DP_AUXCH_CMD_TYPE_I2C + * Set this value to indicate a I2C transaction. + * NV0073_CTRL_DP_AUXCH_CMD_TYPE_AUX + * Set this value to indicate a DisplayPort transaction. + * NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT + * This field is dependent on NV0073_CTRL_DP_AUXCH_CMD_TYPE. + * It is only valid if NV0073_CTRL_DP_AUXCH_CMD_TYPE_I2C + * is specified above and indicates a middle of transaction. + * In the case of AUX, this field should be set to zero. The valid + * values are: + * NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT_FALSE + * The I2C transaction is not in the middle of a transaction. + * NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT_TRUE + * The I2C transaction is in the middle of a transaction. + * NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE + * The request type specifies if we are doing a read/write or write + * status request: + * NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_READ + * An I2C or AUX channel read is requested. + * NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_WRITE + * An I2C or AUX channel write is requested. + * NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_WRITE_STATUS + * An I2C write status request desired. This value should + * not be set in the case of an AUX CH request and only applies + * to I2C write transaction command. + * addr + * This parameter is an input to this command. The addr parameter follows + * Section 2.4 in DisplayPort spec and the client should refer to the valid + * address in DisplayPort spec. Only the first 20 bits are valid. + * data[] + * In the case of a read transaction, this parameter returns the data from + * transaction request. In the case of a write transaction, the client + * should write to this buffer for the data to send. The max # of bytes + * allowed is NV0073_CTRL_DP_AUXCH_MAX_DATA_SIZE. + * size + * Specifies how many data bytes to read/write depending on the transaction type. + * The input size value should be indexed from 0. That means if you want to read + * 1 byte -> size = 0, 2 bytes -> size = 1, 3 bytes -> size = 2, up to 16 bytes + * where size = 15. On return, this parameter returns total number of data bytes + * successfully read/written from/to the transaction (indexed from 1). That is, + * if you successfully requested 1 byte, you would send down size = 0. On return, + * you should expect size = 1 if all 1 byte were successfully read. (Note that + * it is valid for a display to reply with fewer than the requested number of + * bytes; in that case, it is up to the client to make a new request for the + * remaining bytes.) + * replyType + * This parameter is an output to this command. It returns the auxChannel + * status after the end of the aux Ch transaction. The valid values are + * based on the DisplayPort spec: + * NV0073_CTRL_DP_AUXCH_REPLYTYPE_ACK + * In the case of a write, + * AUX: write transaction completed and all data bytes written. + * I2C: return size bytes has been written to i2c slave. + * In the case of a read, return of ACK indicates ready to reply + * another read request. + * NV0073_CTRL_DP_AUXCH_REPLYTYPE_NACK + * In the case of a write, first return size bytes have been written. + * In the case of a read, implies that does not have requested data + * for the read request transaction. + * NV0073_CTRL_DP_AUXCH_REPLYTYPE_DEFER + * Not ready for the write/read request and client should retry later. + * NV0073_CTRL_DP_DISPLAYPORT_AUXCH_REPLYTYPE_I2CNACK + * Applies to I2C transactions only. For I2C write transaction: + * has written the first return size bytes to I2C slave before getting + * NACK. For a read I2C transaction, the I2C slave has NACKED the I2C + * address. + * NV0073_CTRL_DP_AUXCH_REPLYTYPE_I2CDEFER + * Applicable to I2C transactions. For I2C write and read + * transactions, I2C slave has yet to ACK or NACK the I2C transaction. + * NV0073_CTRL_DP_AUXCH_REPLYTYPE_TIMEOUT + * The receiver did not respond within the timeout period defined in + * the DisplayPort 1.1a specification. + * retryTimeMs + * This parameter is an output to this command. In case of + * NVOS_STATUS_ERROR_RETRY return status, this parameter returns the time + * duration in milli-seconds after which client should retry this command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_ERROR_RETRY + */ +#define NV0073_CTRL_CMD_DP_AUXCH_CTRL (0x731341U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_AUXCH_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_AUXCH_MAX_DATA_SIZE 16U +#define NV0073_CTRL_DP_AUXCH_CTRL_PARAMS_MESSAGE_ID (0x41U) + +typedef struct NV0073_CTRL_DP_AUXCH_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bAddrOnly; + NvU32 cmd; + NvU32 addr; + NvU8 data[NV0073_CTRL_DP_AUXCH_MAX_DATA_SIZE]; + NvU32 size; + NvU32 replyType; + NvU32 retryTimeMs; +} NV0073_CTRL_DP_AUXCH_CTRL_PARAMS; + +#define NV0073_CTRL_DP_AUXCH_CMD_TYPE 3:3 +#define NV0073_CTRL_DP_AUXCH_CMD_TYPE_I2C (0x00000000U) +#define NV0073_CTRL_DP_AUXCH_CMD_TYPE_AUX (0x00000001U) +#define NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT 2:2 +#define NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT_FALSE (0x00000000U) +#define NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT_TRUE (0x00000001U) +#define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE 1:0 +#define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_WRITE (0x00000000U) +#define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_READ (0x00000001U) +#define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_WRITE_STATUS (0x00000002U) + +#define NV0073_CTRL_DP_AUXCH_ADDR 20:0 + +#define NV0073_CTRL_DP_AUXCH_REPLYTYPE 3:0 +#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_ACK (0x00000000U) +#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_NACK (0x00000001U) +#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_DEFER (0x00000002U) +#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_TIMEOUT (0x00000003U) +#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_I2CNACK (0x00000004U) +#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_I2CDEFER (0x00000008U) + +//This is not the register field, this is software failure case when we +//have invalid argument +#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_INVALID_ARGUMENT (0xffffffffU) + + + +/* + * NV0073_CTRL_CMD_DP_CTRL + * + * This command is used to set various displayPort configurations for + * the specified displayId such a lane count and link bandwidth. It + * is assumed that link training has already occurred. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must a dfp display. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * cmd + * This parameter is an input to this command. + * Here are the current defined fields: + * NV0073_CTRL_DP_CMD_SET_LANE_COUNT + * Set to specify the number of displayPort lanes to configure. + * NV0073_CTRL_DP_CMD_SET_LANE_COUNT_FALSE + * No request to set the displayport lane count. + * NV0073_CTRL_DP_CMD_SET_LANE_COUNT_TRUE + * Set this value to indicate displayport lane count change. + * NV0073_CTRL_DP_CMD_SET_LINK_BANDWIDTH + * Set to specify a request to change the link bandwidth. + * NV0073_CTRL_DP_CMD_SET_LINK_BANDWIDTH_FALSE + * No request to set the displayport link bandwidth. + * NV0073_CTRL_DP_CMD_SET_LINK_BANDWIDTH_TRUE + * Set this value to indicate displayport link bandwidth change. + * NV0073_CTRL_DP_CMD_SET_LINK_BANDWIDTH + * Set to specify a request to change the link bandwidth. + * NV0073_CTRL_DP_CMD_SET_LINK_BANDWIDTH_FALSE + * No request to set the displayport link bandwidth. + * NV0073_CTRL_DP_CMD_SET_LINK_BANDWIDTH_TRUE + * Set this value to indicate displayport link bandwidth change. + * NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD + * Set to disable downspread during link training. + * NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD_FALSE + * Downspread will be enabled. + * NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD_TRUE + * Downspread will be disabled (e.g. for compliance testing). + * NV0073_CTRL_DP_CMD_SET_FORMAT_MODE + * This field specifies the DP stream mode. + * NV0073_CTRL_DP_CMD_SET_FORMAT_MODE_SINGLE_STREAM + * This value indicates that single stream mode is specified. + * NV0073_CTRL_DP_CMD_SET_FORMAT_MODE_MULTI_STREAM + * This value indicates that multi stream mode is specified. + * NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING + * Set to do Fast link training (avoid AUX transactions for link + * training). We need to restore all the previous trained link settings + * (e.g. the drive current/preemphasis settings) before doing FLT. + * During FLT, we send training pattern 1 followed by training pattern 2 + * each for a period of 500us. + * NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING_NO + * Not a fast link training scenario. + * NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING_YES + * Do fast link training. + * NV0073_CTRL_DP_CMD_NO_LINK_TRAINING + * Set to do No link training. We need to restore all the previous + * trained link settings (e.g. the drive current/preemphasis settings) + * before doing NLT, but we don't need to do the Clock Recovery and + * Channel Equalization. (Please refer to NVIDIA PANEL SELFREFRESH + * CONTROLLER SPECIFICATION 3.1.6 for detail flow) + * NV0073_CTRL_DP_CMD_NO_LINK_TRAINING_NO + * Not a no link training scenario. + * NV0073_CTRL_DP_CMD_NO_LINK_TRAINING_YES + * Do no link training. + * NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING + * Specifies whether RM should use the DP Downspread setting specified by + * NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD command regardless of what the Display + * is capable of. This is used along with the Fake link training option so that + * we can configure the GPU to enable/disable spread when a real display is + * not connected. + * NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING_FORCE + * RM Always use the DP Downspread setting specified. + * NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING_DEFAULT + * RM will enable Downspread only if the display supports it. (default) + * NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING + * Specifies whether RM should skip HW training of the link. + * If this is the case then RM only updates its SW state without actually + * touching any HW registers. Clients should use this ONLY if it has determined - + * a. link is trained and not lost + * b. desired link config is same as current trained link config + * c. link is not in D3 (should be in D0) + * NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING_NO + * RM doesn't skip HW LT as the current Link Config is not the same as the + * requested Link Config. + * NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING_YES + * RM skips HW LT and only updates its SW state as client has determined that + * the current state of the link and the requested Link Config is the same. + * NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG + * Set if the client does not want link training to happen. + * This should ONLY be used for HW verification. + * NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG_FALSE + * This is normal production behaviour which shall perform + * link training or follow the normal procedure for lane count + * reduction. + * NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG_TRUE + * Set this value to not perform link config steps, this should + * only be turned on for HW verif testing. If _LINK_BANDWIDTH + * or _LANE_COUNT is set, RM will only write to the TX DP registers + * and perform no link training. + * NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED + * This field specifies if source grants Post Link training Adjustment request or not. + * NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED_NO + * Source does not grant Post Link training Adjustment request + * NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED_YES + * Source grants Post Link training Adjustment request + * Source wants to link train LT Tunable Repeaters + * NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING + * This field specifies if fake link training is to be done. This will + * program enough of the hardware to avoid any hardware hangs and + * depending upon option chosen by the client, OR will be enabled for + * transmisssion. + * NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_NO + * No Fake LT will be performed + * NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_DONOT_TOGGLE_TRANSMISSION + * SOR will be not powered up during Fake LT + * NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_TOGGLE_TRANSMISSION_ON + * SOR will be powered up during Fake LT + * NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER + * This field specifies if source wants to link train LT Tunable Repeaters or not. + * NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER_NO + * Source does not want to link train LT Tunable Repeaters + * NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER_YES + * NV0073_CTRL_DP_CMD_BANDWIDTH_TEST + * Set if the client wants to reset the link after the link + * training is done. As a part of uncommtting a DP display. + * NV0073_CTRL_DP_CMD_BANDWIDTH_TEST_NO + * This is for normal operation, if DD decided not to reset the link. + * NV0073_CTRL_DP_CMD_BANDWIDTH_TEST_YES + * This is to reset the link, if DD decided to uncommit the display because + * the link is no more required to be enabled, as in a DP compliance test. + * NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE + * Set if the client does not want link training to happen. + * This should ONLY be used for HW verification if necessary. + * NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_FALSE + * This is normal production behaviour which shall perform + * pre link training checks such as if both rx and tx are capable + * of the requested config for lane and link bw. + * NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_TRUE + * Set this value to bypass link config check, this should + * only be turned on for HW verif testing. If _LINK_BANDWIDTH + * or _LANE_COUNT is set, RM will not check TX and DX caps. + * NV0073_CTRL_DP_CMD_FALLBACK_CONFIG + * Set if requested config by client fails and if link if being + * trained for the fallback config. + * NV0073_CTRL_DP_CMD_FALLBACK_CONFIG_FALSE + * This is the normal case when the link is being trained for a requested config. + * NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_TRUE + * Set this value in case the link configuration for requested config fails + * and the link is being trained for a fallback config. + * NV0073_CTRL_DP_CMD_ENABLE_FEC + * Specifies whether RM should set NV_DPCD14_FEC_CONFIGURATION_FEC_READY + * before link training if client has determined that FEC is required(for DSC). + * If required to be enabled RM sets FEC enable bit in panel, start link training. + * Enabling/disabling FEC on GPU side is not done during Link training + * and RM Ctrl call NV0073_CTRL_CMD_DP_CONFIGURE_FEC has to be called + * explicitly to enable/disable FEC after LT(including PostLT LQA). + * If enabled, FEC would be disabled while powering down the link. + * Client has to make sure to account for 3% overhead of transmitting + * FEC symbols while calculating DP bandwidth. + * NV0073_CTRL_DP_CMD_ENABLE_FEC_FALSE + * This is the normal case when FEC is not required + * NV0073_CTRL_DP_CMD_ENABLE_FEC_TRUE + * Set this value in case FEC needs to be enabled + * data + * This parameter is an input and output to this command. + * Here are the current defined fields: + * NV0073_CTRL_DP_DATA_SET_LANE_COUNT + * This field specifies the desired setting for lane count. A client + * may choose any lane count as long as it does not exceed the + * capability of DisplayPort receiver as indicated in the + * receiver capability field. The valid values for this field are: + * NV0073_CTRL_DP_DATA_SET_LANE_COUNT_0 + * For zero-lane configurations, link training is shut down. + * NV0073_CTRL_DP_DATA_SET_LANE_COUNT_1 + * For one-lane configurations, lane0 is used. + * NV0073_CTRL_DP_DATA_SET_LANE_COUNT_2 + * For two-lane configurations, lane0 and lane1 is used. + * NV0073_CTRL_DP_DATA_SET_LANE_COUNT_4 + * For four-lane configurations, all lanes are used. + * NV0073_CTRL_DP_DATA_SET_LANE_COUNT_8 + * For devices that supports 8-lane DP. + * On return, the lane count setting is returned which may be + * different from the requested input setting. + * NV0073_CTRL_DP_DATA_SET_LINK_BW + * This field specifies the desired setting for link bandwidth. There + * are only four supported main link bandwidth settings. The + * valid values for this field are: + * NV0073_CTRL_DP_DATA_SET_LINK_BW_1_62GBPS + * NV0073_CTRL_DP_DATA_SET_LINK_BW_2_70GBPS + * NV0073_CTRL_DP_DATA_SET_LINK_BW_5_40GBPS + * NV0073_CTRL_DP_DATA_SET_LINK_BW_8_10GBPS + * On return, the link bandwidth setting is returned which may be + * different from the requested input setting. + * NV0073_CTRL_DP_DATA_TARGET + * This field specifies which physical repeater or sink to be trained. + * Client should make sure + * 1. Physical repeater should be targeted in order, start from the one closest to GPU. + * 2. All physical repeater is properly trained before targets sink. + * The valid values for this field are: + * NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_X + * 'X' denotes physical repeater index. It's a 1-based index to + * reserve 0 for _SINK. + * 'X' can't be more than 8. + * NV0073_CTRL_DP_DATA_TARGET_SINK + * err + * This parameter specifies provides info regarding the outcome + * of this calling control call. If zero, no errors were found. + * Otherwise, this parameter will specify the error detected. + * The valid parameter is broken down as follows: + * NV0073_CTRL_DP_ERR_SET_LANE_COUNT + * If set to _ERR, set lane count failed. + * NV0073_CTRL_DP_ERR_SET_LINK_BANDWIDTH + * If set to _ERR, set link bandwidth failed. + * NV0073_CTRL_DP_ERR_DISABLE_DOWNSPREAD + * If set to _ERR, disable downspread failed. + * NV0073_CTRL_DP_ERR_INVALID_PARAMETER + * If set to _ERR, at least one of the calling functions + * failed due to an invalid parameter. + * NV0073_CTRL_DP_ERR_SET_LINK_TRAINING + * If set to _ERR, link training failed. + * NV0073_CTRL_DP_ERR_TRAIN_PHY_REPEATER + * If set to _ERR, the operation to Link Train repeater is failed. + * NV0073_CTRL_DP_ERR_ENABLE_FEC + * If set to _ERR, the operation to enable FEC is failed. + * NV0073_CTRL_DP_ERR_LINK_STATUS + * If set to _DISCONNECTED, link training failed and link is disconnected / unplugged. + * + * retryTimeMs + * This parameter is an output to this command. In case of + * NVOS_STATUS_ERROR_RETRY return status, this parameter returns the time + * duration in milli-seconds after which client should retry this command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_ERROR_RETRY + */ + +#define NV0073_CTRL_CMD_DP_CTRL (0x731343U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_CTRL_PARAMS_MESSAGE_ID (0x43U) + +typedef struct NV0073_CTRL_DP_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 cmd; + NvU32 data; + NvU32 err; + NvU32 retryTimeMs; + NvU32 eightLaneDpcdBaseAddr; +} NV0073_CTRL_DP_CTRL_PARAMS; + +#define NV0073_CTRL_DP_CMD_SET_LANE_COUNT 0:0 +#define NV0073_CTRL_DP_CMD_SET_LANE_COUNT_FALSE (0x00000000U) +#define NV0073_CTRL_DP_CMD_SET_LANE_COUNT_TRUE (0x00000001U) +#define NV0073_CTRL_DP_CMD_SET_LINK_BW 1:1 +#define NV0073_CTRL_DP_CMD_SET_LINK_BW_FALSE (0x00000000U) +#define NV0073_CTRL_DP_CMD_SET_LINK_BW_TRUE (0x00000001U) +#define NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD 2:2 +#define NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD_FALSE (0x00000000U) +#define NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD_TRUE (0x00000001U) +#define NV0073_CTRL_DP_CMD_UNUSED 3:3 +#define NV0073_CTRL_DP_CMD_SET_FORMAT_MODE 4:4 +#define NV0073_CTRL_DP_CMD_SET_FORMAT_MODE_SINGLE_STREAM (0x00000000U) +#define NV0073_CTRL_DP_CMD_SET_FORMAT_MODE_MULTI_STREAM (0x00000001U) +#define NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING 5:5 +#define NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING_NO (0x00000000U) +#define NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING_YES (0x00000001U) +#define NV0073_CTRL_DP_CMD_NO_LINK_TRAINING 6:6 +#define NV0073_CTRL_DP_CMD_NO_LINK_TRAINING_NO (0x00000000U) +#define NV0073_CTRL_DP_CMD_NO_LINK_TRAINING_YES (0x00000001U) +#define NV0073_CTRL_DP_CMD_SET_ENHANCED_FRAMING 7:7 +#define NV0073_CTRL_DP_CMD_SET_ENHANCED_FRAMING_FALSE (0x00000000U) +#define NV0073_CTRL_DP_CMD_SET_ENHANCED_FRAMING_TRUE (0x00000001U) +#define NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING 8:8 +#define NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING_DEFAULT (0x00000000U) +#define NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING_FORCE (0x00000001U) +#define NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING 9:9 +#define NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING_NO (0x00000000U) +#define NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING_YES (0x00000001U) +#define NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED 10:10 +#define NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED_NO (0x00000000U) +#define NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED_YES (0x00000001U) +#define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING 12:11 +#define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_NO (0x00000000U) +#define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_DONOT_TOGGLE_TRANSMISSION (0x00000001U) +#define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_TOGGLE_TRANSMISSION_ON (0x00000002U) +#define NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER 13:13 +#define NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER_NO (0x00000000U) +#define NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER_YES (0x00000001U) +#define NV0073_CTRL_DP_CMD_FALLBACK_CONFIG 14:14 +#define NV0073_CTRL_DP_CMD_FALLBACK_CONFIG_FALSE (0x00000000U) +#define NV0073_CTRL_DP_CMD_FALLBACK_CONFIG_TRUE (0x00000001U) +#define NV0073_CTRL_DP_CMD_ENABLE_FEC 15:15 +#define NV0073_CTRL_DP_CMD_ENABLE_FEC_FALSE (0x00000000U) +#define NV0073_CTRL_DP_CMD_ENABLE_FEC_TRUE (0x00000001U) + +#define NV0073_CTRL_DP_CMD_BANDWIDTH_TEST 29:29 +#define NV0073_CTRL_DP_CMD_BANDWIDTH_TEST_NO (0x00000000U) +#define NV0073_CTRL_DP_CMD_BANDWIDTH_TEST_YES (0x00000001U) +#define NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE 30:30 +#define NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG 31:31 +#define NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG_FALSE (0x00000000U) +#define NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG_TRUE (0x00000001U) + +#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT 4:0 +#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_0 (0x00000000U) +#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_1 (0x00000001U) +#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_2 (0x00000002U) +#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_4 (0x00000004U) +#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_8 (0x00000008U) +#define NV0073_CTRL_DP_DATA_SET_LINK_BW 15:8 +#define NV0073_CTRL_DP_DATA_SET_LINK_BW_1_62GBPS (0x00000006U) +#define NV0073_CTRL_DP_DATA_SET_LINK_BW_2_16GBPS (0x00000008U) +#define NV0073_CTRL_DP_DATA_SET_LINK_BW_2_43GBPS (0x00000009U) +#define NV0073_CTRL_DP_DATA_SET_LINK_BW_2_70GBPS (0x0000000AU) +#define NV0073_CTRL_DP_DATA_SET_LINK_BW_3_24GBPS (0x0000000CU) +#define NV0073_CTRL_DP_DATA_SET_LINK_BW_4_32GBPS (0x00000010U) +#define NV0073_CTRL_DP_DATA_SET_LINK_BW_5_40GBPS (0x00000014U) +#define NV0073_CTRL_DP_DATA_SET_LINK_BW_8_10GBPS (0x0000001EU) +#define NV0073_CTRL_DP_DATA_SET_ENHANCED_FRAMING 18:18 +#define NV0073_CTRL_DP_DATA_SET_ENHANCED_FRAMING_NO (0x00000000U) +#define NV0073_CTRL_DP_DATA_SET_ENHANCED_FRAMING_YES (0x00000001U) +#define NV0073_CTRL_DP_DATA_TARGET 22:19 +#define NV0073_CTRL_DP_DATA_TARGET_SINK (0x00000000U) +#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_0 (0x00000001U) +#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_1 (0x00000002U) +#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_2 (0x00000003U) +#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_3 (0x00000004U) +#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_4 (0x00000005U) +#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_5 (0x00000006U) +#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_6 (0x00000007U) +#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_7 (0x00000008U) + +#define NV0073_CTRL_DP_ERR_SET_LANE_COUNT 0:0 +#define NV0073_CTRL_DP_ERR_SET_LANE_COUNT_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_SET_LANE_COUNT_ERR (0x00000001U) +#define NV0073_CTRL_DP_ERR_SET_LINK_BW 1:1 +#define NV0073_CTRL_DP_ERR_SET_LINK_BW_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_SET_LINK_BW_ERR (0x00000001U) +#define NV0073_CTRL_DP_ERR_DISABLE_DOWNSPREAD 2:2 +#define NV0073_CTRL_DP_ERR_DISABLE_DOWNSPREAD_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_DISABLE_DOWNSPREAD_ERR (0x00000001U) +#define NV0073_CTRL_DP_ERR_UNUSED 3:3 +#define NV0073_CTRL_DP_ERR_CLOCK_RECOVERY 4:4 +#define NV0073_CTRL_DP_ERR_CLOCK_RECOVERY_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_CLOCK_RECOVERY_ERR (0x00000001U) +#define NV0073_CTRL_DP_ERR_CHANNEL_EQUALIZATION 5:5 +#define NV0073_CTRL_DP_ERR_CHANNEL_EQUALIZATION_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_CHANNEL_EQUALIZATION_ERR (0x00000001U) +#define NV0073_CTRL_DP_ERR_TRAIN_PHY_REPEATER 6:6 +#define NV0073_CTRL_DP_ERR_TRAIN_PHY_REPEATER_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_TRAIN_PHY_REPEATER_ERR (0x00000001U) +#define NV0073_CTRL_DP_ERR_ENABLE_FEC 7:7 +#define NV0073_CTRL_DP_ERR_ENABLE_FEC_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_ENABLE_FEC_ERR (0x00000001U) +#define NV0073_CTRL_DP_ERR_CR_DONE_LANE 11:8 +#define NV0073_CTRL_DP_ERR_CR_DONE_LANE_0_LANE (0x00000000U) +#define NV0073_CTRL_DP_ERR_CR_DONE_LANE_1_LANE (0x00000001U) +#define NV0073_CTRL_DP_ERR_CR_DONE_LANE_2_LANE (0x00000002U) +#define NV0073_CTRL_DP_ERR_CR_DONE_LANE_4_LANE (0x00000004U) +#define NV0073_CTRL_DP_ERR_CR_DONE_LANE_8_LANE (0x00000008U) +#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE 15:12 +#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE_0_LANE (0x00000000U) +#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE_1_LANE (0x00000001U) +#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE_2_LANE (0x00000002U) +#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE_4_LANE (0x00000004U) +#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE_8_LANE (0x00000008U) +#define NV0073_CTRL_DP_ERR_LINK_STATUS 29:29 +#define NV0073_CTRL_DP_ERR_LINK_STATUS_CONNECTED (0x00000000U) +#define NV0073_CTRL_DP_ERR_LINK_STATUS_DISCONNECTED (0x00000001U) +#define NV0073_CTRL_DP_ERR_INVALID_PARAMETER 30:30 +#define NV0073_CTRL_DP_ERR_INVALID_PARAMETER_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_INVALID_PARAMETER_ERR (0x00000001U) +#define NV0073_CTRL_DP_ERR_LINK_TRAINING 31:31 +#define NV0073_CTRL_DP_ERR_LINK_TRAINING_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_LINK_TRAINING_ERR (0x00000001U) + +/* + * NV0073_CTRL_DP_LANE_DATA_PARAMS + * + * This structure provides lane characteristics. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must a dfp display. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * numLanes + * Indicates number of lanes for which the data is valid + * data + * This parameter is an input to this command. + * Here are the current defined fields: + * NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS + * This field specifies the preemphasis level set in the lane. + * The valid values for this field are: + * NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_NONE + * No-preemphais for this lane. + * NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL1 + * Preemphasis set to 3.5 dB. + * NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL2 + * Preemphasis set to 6.0 dB. + * NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL3 + * Preemphasis set to 9.5 dB. + * NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT + * This field specifies the drive current set in the lane. + * The valid values for this field are: + * NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL0 + * Drive current level is set to 8 mA + * NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL1 + * Drive current level is set to 12 mA + * NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL2 + * Drive current level is set to 16 mA + * NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL3 + * Drive current level is set to 24 mA + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_MAX_LANES 8U + +typedef struct NV0073_CTRL_DP_LANE_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 numLanes; + NvU32 data[NV0073_CTRL_MAX_LANES]; +} NV0073_CTRL_DP_LANE_DATA_PARAMS; + +#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS 1:0 +#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_NONE (0x00000000U) +#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL1 (0x00000001U) +#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL2 (0x00000002U) +#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL3 (0x00000003U) +#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT 3:2 +#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL0 (0x00000000U) +#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL1 (0x00000001U) +#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL2 (0x00000002U) +#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL3 (0x00000003U) + +/* + * NV0073_CTRL_CMD_GET_DP_LANE_DATA + * + * This command is used to get the current pre-emphasis and drive current + * level values for the specified number of lanes. + * + * The command takes a NV0073_CTRL_DP_LANE_DATA_PARAMS structure as the + * argument with the appropriate subDeviceInstance and displayId filled. + * The arguments of this structure and the format of preemphasis and drive- + * current levels are described above. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * NOTE: This control call is only for testing purposes and + * should not be used in normal DP operations. Preemphais + * and drive current level will be set during Link training + * in normal DP operations + * + */ + +#define NV0073_CTRL_CMD_DP_GET_LANE_DATA (0x731345U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_LANE_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_GET_LANE_DATA_PARAMS_MESSAGE_ID (0x45U) + +typedef NV0073_CTRL_DP_LANE_DATA_PARAMS NV0073_CTRL_DP_GET_LANE_DATA_PARAMS; + + +/* + * NV0073_CTRL_CMD_SET_DP_LANE_DATA + * + * This command is used to set the pre-emphasis and drive current + * level values for the specified number of lanes. + * + * The command takes a NV0073_CTRL_DP_LANE_DATA_PARAMS structure as the + * argument with the appropriate subDeviceInstance, displayId, number of + * lanes, preemphasis and drive current values filled in. + * The arguments of this structure and the format of preemphasis and drive- + * current levels are described above. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * NOTE: This control call is only for testing purposes and + * should not be used in normal DP operations. Preemphais + * and drivecurrent will be set during Link training in + * normal DP operations + * + */ + +#define NV0073_CTRL_CMD_DP_SET_LANE_DATA (0x731346U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_LANE_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_SET_LANE_DATA_PARAMS_MESSAGE_ID (0x46U) + +typedef NV0073_CTRL_DP_LANE_DATA_PARAMS NV0073_CTRL_DP_SET_LANE_DATA_PARAMS; + +#define NV0073_CTRL_CSTM_BUFFER_SIZE 9U + +/* + * NV0073_CTRL_DP_CSTM + * + * This structure specifies - + * A) 80 bit DP CSTM Test Pattern data for DP1.x (HBR2 + 8b/10b channel coding) + * The fields of this structure are to be specified as follows: + * field_31_0 takes bits 31:0 + * field_63_32 takes bits 63:32 + * field_95_64 takes bits 79:64 + * B) 264 bit DP CSTM Test Pattern data for DP2.x (128b/132b channel coding) + * The fields of this structure are to be specified as follows: + * field_31_0 contains bits 31:0 + * field_63_32 contains bits 63:32 + * field_95_64 contains bits 95:64 + * field_127_96 contains bits 127:96 + * field_159_128 contains bits 159:128 + * field_191_160 contains bits 191:160 + * field_223_192 contains bits 223:192 + * field_255_224 contains bits 255:224 + * field_263_256 contains bits 263:256 + */ +typedef struct NV0073_CTRL_DP_CSTM { + NvU32 field_31_0; + NvU32 field_63_32; + NvU32 field_95_64; + NvU32 field_127_96; + NvU32 field_159_128; + NvU32 field_191_160; + NvU32 field_223_192; + NvU32 field_255_224; + NvU32 field_263_256; +} NV0073_CTRL_DP_CSTM; + +#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_CSTM2 15:0 +#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_CSTM8 7:0 + +/* + * NV0073_CTRL_DP_TESTPATTERN + * + * This structure specifies the possible test patterns available in display port, + * and parameters for Square pattern. + * + */ + +typedef struct NV0073_CTRL_DP_TESTPATTERN { + NvU32 testPattern; +} NV0073_CTRL_DP_TESTPATTERN; +#define NV0073_CTRL_DP_TESTPATTERN_DATA 4:0 +#define NV0073_CTRL_DP_TESTPATTERN_DATA_NONE (0x00000000U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_D10_2 (0x00000001U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_SERMP (0x00000002U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_7 (0x00000003U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_CSTM (0x00000004U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_HBR2COMPLIANCE (0x00000005U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_CP2520PAT3 (0x00000006U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_TRAINING1 (0x00000007U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_TRAINING2 (0x00000008U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_TRAINING3 (0x00000009U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_TRAINING4 (0x0000000AU) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_CP2520PAT1 (0x0000000BU) + +#define NV0073_CTRL_DP_TESTPATTERN_DATA_128B132B_TPS1 (0x0000000CU) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_128B132B_TPS2 (0x0000000DU) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_9 (0x0000000EU) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_11 (0x0000000FU) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_15 (0x00000010U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_23 (0x00000011U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_31 (0x00000012U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_SQNUM (0x00000013U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_CSTM_264 (0x00000014U) +/* + * The following three flags specify the parameters for SQ Pattern tests. + * Only valid when testPattern is NV0073_CTRL_DP_TESTPATTERN_DATA_SQNUM + */ +#define NV0073_CTRL_DP_TESTPATTERN_SQ_PATTERN_PRESHOOT 8:8 +#define NV0073_CTRL_DP_TESTPATTERN_SQ_PATTERN_PRESHOOT_DISABLED (0x00000000U) +#define NV0073_CTRL_DP_TESTPATTERN_SQ_PATTERN_PRESHOOT_ENABLED (0x00000001U) +#define NV0073_CTRL_DP_TESTPATTERN_SQ_PATTERN_DE_EMPHASIS 9:9 +#define NV0073_CTRL_DP_TESTPATTERN_SQ_PATTERN_DE_EMPHASIS_DISABLED (0x00000000U) +#define NV0073_CTRL_DP_TESTPATTERN_SQ_PATTERN_DE_EMPHASIS_ENABLED (0x00000001U) +#define NV0073_CTRL_DP_TESTPATTERN_SQ_PATTERN_NUM 23:16 + + + +/* + * NV0073_CTRL_CMD_DP_SET_TESTPATTERN + * + * This command forces the main link to output the selected test patterns + * supported in DP specs. + * + * The command takes a NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS structure as the + * argument with the appropriate subDeviceInstance, displayId and test pattern + * to be set as inputs. + * The arguments of this structure and the format of test patterns are + * described above. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must a dfp display. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * testPattern + * This parameter is of type NV0073_CTRL_DP_TESTPATTERN and specifies + * the testpattern to set on displayport. The format of this structure + * is described above. + * laneMask + * This parameter specifies the bit mask of DP lanes on which test + * pattern is to be applied. + * cstm + * This parameter specifies the all the bits for CSTM test pattern. + * bIsHBR2 + * This Boolean parameter is set to TRUE if HBR2 compliance test is + * being performed. + * bSkipLaneDataOverride + * skip override of pre-emp and drive current + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * NOTE: This control call is only for testing purposes and + * should not be used in normal DP operations. Preemphais + * and drivecurrent will be set during Link training in + * normal DP operations + * + */ + +#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_MESSAGE_ID (0x47U) + +typedef struct NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NV0073_CTRL_DP_TESTPATTERN testPattern; + NvU8 laneMask; + NV0073_CTRL_DP_CSTM cstm; + NvBool bIsHBR2; + NvBool bSkipLaneDataOverride; +} NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS; + +#define NV0073_CTRL_CMD_DP_SET_TESTPATTERN (0x731347U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_MESSAGE_ID" */ + +/* + * NV0073_CTRL_CMD_GET_DP_TESTPATTERN + * + * This command returns the current test pattern set on the main link of + * Display Port. + * + * The command takes a NV0073_CTRL_DP_GET_TESTPATTERN_PARAMS structure as the + * argument with the appropriate subDeviceInstance, displayId as inputs and + * returns the current test pattern in testPattern field of the structure. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must a dfp display. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * testPattern + * This parameter is of type NV0073_CTRL_DP_TESTPATTERN and specifies the + * testpattern set on displayport. The format of this structure is + * described above. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * NOTE: This control call is only for testing purposes and + * should not be used in normal DP operations. + * + */ + +#define NV0073_CTRL_DP_GET_TESTPATTERN_PARAMS_MESSAGE_ID (0x48U) + +typedef struct NV0073_CTRL_DP_GET_TESTPATTERN_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NV0073_CTRL_DP_TESTPATTERN testPattern; + NV0073_CTRL_DP_CSTM cstm; +} NV0073_CTRL_DP_GET_TESTPATTERN_PARAMS; + +#define NV0073_CTRL_CMD_DP_GET_TESTPATTERN (0x731348U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_TESTPATTERN_PARAMS_MESSAGE_ID" */ + +/* + * NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA + * + * This structure specifies the Pre-emphasis/Drive Current/Postcursor2/TxPu information + * for a display port device. These are the the current values that RM is + * using to map the levels for Pre-emphasis and Drive Current for Link + * Training. + * preEmphasis + * This field specifies the preemphasis values. + * driveCurrent + * This field specifies the driveCurrent values. + * postcursor2 + * This field specifies the postcursor2 values. + * TxPu + * This field specifies the pull-up current source drive values. + */ +#define NV0073_CTRL_MAX_DRIVECURRENT_LEVELS 4U +#define NV0073_CTRL_MAX_PREEMPHASIS_LEVELS 4U +#define NV0073_CTRL_MAX_POSTCURSOR2_LEVELS 4U + +typedef struct NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_1 { + NvU32 preEmphasis; + NvU32 driveCurrent; + NvU32 postCursor2; + NvU32 TxPu; +} NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_1; + +/* + * NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA + * + * This command is used to override the Pre-emphasis/Drive Current/PostCursor2/TxPu + * data in the RM. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the digital display for which the + * data should be returned. The display ID must a digital display. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * dpData + * This parameter is of type NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA + * and specifies the Pre-emphasis/Drive Current/Postcursor2/TxPu information + * for a display port device. + * The command takes a NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS + * structure as the argument with the appropriate subDeviceInstance, displayId, + * and dpData. The fields of this structure are described above. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS_MESSAGE_ID (0x51U) + +typedef struct NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_1 dpData[NV0073_CTRL_MAX_POSTCURSOR2_LEVELS][NV0073_CTRL_MAX_DRIVECURRENT_LEVELS][NV0073_CTRL_MAX_PREEMPHASIS_LEVELS]; +} NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS; + +#define NV0073_CTRL_CMD_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA (0x731351U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS_MESSAGE_ID" */ + +/* + * NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA + * + * This command is used to get the Pre-emphasis/Drive Current/PostCursor2/TxPu data. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the digital display for which the + * data should be returned. The display ID must a digital display. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * The command takes a NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS + * structure as the argument with the appropriate subDeviceInstance, displayId, + * and dpData. The fields of this structure are described above. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS_MESSAGE_ID (0x52U) + +typedef struct NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_1 dpData[NV0073_CTRL_MAX_POSTCURSOR2_LEVELS][NV0073_CTRL_MAX_DRIVECURRENT_LEVELS][NV0073_CTRL_MAX_PREEMPHASIS_LEVELS]; +} NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS; + +#define NV0073_CTRL_CMD_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA (0x731352U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS_MESSAGE_ID" */ + + + +/* + * NV0073_CTRL_CMD_DP_MAIN_LINK_CTRL + * + * This command is used to set various Main Link configurations for + * the specified displayId such as powering up/down Main Link. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the DP display which owns + * the Main Link to be adjusted. The display ID must a DP display + * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * ctrl + * Here are the current defined fields: + * NV0073_CTRL_DP_MAIN_LINK_CTRL_POWER_STATE_POWERDOWN + * This value will power down Main Link. + * NV0073_CTRL_DP_MAIN_LINK_CTRL_POWER_STATE_POWERUP + * This value will power up Main Link. + * +*/ +#define NV0073_CTRL_CMD_DP_MAIN_LINK_CTRL (0x731356U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_MAIN_LINK_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_MAIN_LINK_CTRL_PARAMS_MESSAGE_ID (0x56U) + +typedef struct NV0073_CTRL_DP_MAIN_LINK_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 ctrl; +} NV0073_CTRL_DP_MAIN_LINK_CTRL_PARAMS; + +#define NV0073_CTRL_DP_MAIN_LINK_CTRL_POWER_STATE 0:0 +#define NV0073_CTRL_DP_MAIN_LINK_CTRL_POWER_STATE_POWERDOWN (0x00000000U) +#define NV0073_CTRL_DP_MAIN_LINK_CTRL_POWER_STATE_POWERUP (0x00000001U) + +/* + * NV0073_CTRL_CMD_DP_SET_AUDIO_MUTESTREAM + * + * This command sets the current audio mute state on the main link of Display Port + * + * The command takes a NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS structure as the + * argument with the appropriate subDeviceInstance, displayId as inputs and whether to enable + * or disable mute in the parameter - mute. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the audio stream + * state should be returned. The display ID must a DP display. + * If the display ID is invalid or if it is not a DP display, + * this call will return NV_ERR_INVALID_ARGUMENT. + * mute + * This parameter is an input to this command. + * Here are the current defined values: + * NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_DISABLE + * Audio mute will be disabled. + * NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_ENABLE + * Audio mute will be enabled. + * NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_AUTO + * Audio mute will be automatically controlled by hardware. + * + * Note: Any other value for mute in NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS is not allowed and + * the API will return an error. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * + */ +#define NV0073_CTRL_CMD_DP_SET_AUDIO_MUTESTREAM (0x731359U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID (0x59U) + +typedef struct NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 mute; +} NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS; + +#define NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_DISABLE (0x00000000U) +#define NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_ENABLE (0x00000001U) +#define NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_AUTO (0x00000002U) + +/* + * NV0073_CTRL_CMD_DP_ASSR_CTRL + * + * This command is used to control and query DisplayPort ASSR + * settings for the specified displayId. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the DP display which owns + * the Main Link to be adjusted. The display ID must a DP display + * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * cmd + * This input parameter specifies the command to execute. Legal + * values for this parameter include: + * NV0073_CTRL_DP_ASSR_CMD_QUERY_STATE + * This field can be used to query ASSR state. When used the ASSR + * state value is returned in the data parameter. + * NV0073_CTRL_DP_ASSR_CMD_DISABLE + * This field can be used to control the ASSR disable state. + * NV0073_CTRL_DP_ASSR_CMD_FORCE_STATE + * This field can be used to control ASSR State without looking at + * whether the display supports it. Used in conjunction with + * Fake link training. Note that this updates the state on the + * source side only. The sink is assumed to be configured for ASSR + * by the client (DD). + * data + * This parameter specifies the data associated with the cmd + * parameter. + * NV0073_CTRL_DP_ASSR_DATA_STATE_ENABLED + * This field indicates the state of ASSR when queried using cmd + * parameter. When used to control the State, it indicates whether + * ASSR should be enabled or disabled. + * NV0073_CTRL_DP_ASSR_DATA_STATE_ENABLED_NO + * When queried this flag indicates that ASSR is not enabled on the sink. + * When used as the data for CMD_FORCE_STATE, it requests ASSR to + * to be disabled on the source side. + * NV0073_CTRL_DP_ASSR_DATA_STATE_ENABLED_YES + * When queried this flag indicates that ASSR is not enabled on the sink. + * When used as the data for CMD_FORCE_STATE, it requests ASSR to + * to be enabled on the source side. + * err + * This output parameter specifies any errors associated with the cmd + * parameter. + * NV0073_CTRL_DP_ASSR_ERR_CAP + * This field indicates the error pertaining to ASSR capability of + * the sink device. + * NV0073_CTRL_DP_ASSR_ERR_CAP_NOERR + * This flag indicates there is no error. + * NV0073_CTRL_DP_ASSR_ERR_CAP_ERR + * This flag indicates that the sink is not ASSR capable. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_CMD_DP_ASSR_CTRL (0x73135aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_ASSR_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_ASSR_CTRL_PARAMS_MESSAGE_ID (0x5AU) + +typedef struct NV0073_CTRL_DP_ASSR_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 cmd; + NvU32 data; + NvU32 err; +} NV0073_CTRL_DP_ASSR_CTRL_PARAMS; + +#define NV0073_CTRL_DP_ASSR_CMD 31:0 +#define NV0073_CTRL_DP_ASSR_CMD_QUERY_STATE (0x00000001U) +#define NV0073_CTRL_DP_ASSR_CMD_DISABLE (0x00000002U) +#define NV0073_CTRL_DP_ASSR_CMD_FORCE_STATE (0x00000003U) +#define NV0073_CTRL_DP_ASSR_CMD_ENABLE (0x00000004U) +#define NV0073_CTRL_DP_ASSR_DATA_STATE_ENABLED 0:0 +#define NV0073_CTRL_DP_ASSR_DATA_STATE_ENABLED_NO (0x00000000U) +#define NV0073_CTRL_DP_ASSR_DATA_STATE_ENABLED_YES (0x00000001U) +#define NV0073_CTRL_DP_ASSR_ERR_CAP 0:0 +#define NV0073_CTRL_DP_ASSR_ERR_CAP_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ASSR_ERR_CAP_ERR (0x00000001U) + +/* + * NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID + * + * This command is used to assign a displayId from the free pool + * to a specific AUX Address in a DP 1.2 topology. The topology + * is uniquely identified by the DisplayId of the DP connector. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This is the DisplayId of the DP connector to which the topology + * is rooted. + * preferredDisplayId + * Client can sent a preferredDisplayID which RM can use during allocation + * if available. If this Id is a part of allDisplayMask in RM then we return + * a free available Id to the client. However, if this is set to + * NV0073_CTRL_CMD_DP_INVALID_PREFERRED_DISPLAY_ID then we return allDisplayMask value. + * useBFM + * Set to true if DP-BFM is used during emulation/RTL Sim. + * + * [out] displayIdAssigned + * This is the out field that will receive the new displayId. If the + * function fails this is guaranteed to be 0. + * [out] allDisplayMask + * This is allDisplayMask RM variable which is returned only when + * preferredDisplayId is set to NV0073_CTRL_CMD_DP_INVALID_PREFERRED_DISPLAY_ID + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID (0x73135bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS_MESSAGE_ID" */ + +/* + * There cannot be more than 128 devices in a topology (also by DP 1.2 specification) + * NOTE: Temporarily lowered to pass XAPI RM tests. Should be reevaluated! + */ +#define NV0073_CTRL_CMD_DP_MAX_TOPOLOGY_NODES 120U +#define NV0073_CTRL_CMD_DP_INVALID_PREFERRED_DISPLAY_ID 0xffffffffU + +#define NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS_MESSAGE_ID (0x5BU) + +typedef struct NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 preferredDisplayId; + + NvBool force; + NvBool useBFM; + + NvU32 displayIdAssigned; + NvU32 allDisplayMask; +} NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID + * + * This command is used to return a multistream displayid to the unused pool. + * You must not call this function while either the ARM or ASSEMBLY state cache + * refers to this display-id. The head must not be attached. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This is the displayId to free. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + * + */ +#define NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID (0x73135cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS_MESSAGE_ID (0x5CU) + +typedef struct NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; +} NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_GET_LINK_CONFIG + * + * This command is used to query DisplayPort link config + * settings on the transmitter side. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the DP display which owns + * the Main Link to be queried. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * laneCount + * Number of lanes the DP transmitter hardware is set up to drive. + * linkBW + * The BW of each lane that the DP transmitter hardware is set up to drive. + * The values returned will be according to the DP specifications. + * dp2LinkBW + * Current BW of each lane that the DP transmitter hardware is set up to drive is UHBR. + * The values returned will be using 10M convention. + * + * Note: + * linkBW and dp2LinkBw are mutual exclusive. Only one of the value will be non-zero. + * + */ +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG (0x731360U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS_MESSAGE_ID (0x60U) + +typedef struct NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 laneCount; + NvU32 linkBW; + NvU32 dp2LinkBW; + NvBool bFECEnabled; +} NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS; + +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT 3:0 +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_0 (0x00000000U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_1 (0x00000001U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_2 (0x00000002U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_4 (0x00000004U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW 3:0 +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_1_62GBPS (0x00000006U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_2_70GBPS (0x0000000aU) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_5_40GBPS (0x00000014U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_8_10GBPS (0x0000001EU) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_2_16GBPS (0x00000008U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_2_43GBPS (0x00000009U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_3_24GBPS (0x0000000CU) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_4_32GBPS (0x00000010U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_6_75GBPS (0x00000019U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW 15:0 +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_1_62GBPS (0x000000A2U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_2_70GBPS (0x0000010EU) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_5_40GBPS (0x0000021CU) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_8_10GBPS (0x0000032AU) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_2_16GBPS (0x000000D8U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_2_43GBPS (0x000000F3U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_3_24GBPS (0x00000114U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_4_32GBPS (0x000001B0U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_6_75GBPS (0x000002A3U) + +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_10_0GBPS (0x000003E8U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_13_5GBPS (0x00000546U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_20_0GBPS (0x000007D0U) + + +/* + * NV0073_CTRL_CMD_DP_GET_EDP_DATA + * + * This command is used to query Embedded DisplayPort information. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the eDP display which owns + * the Main Link to be queried. + * If more than one displayId bit is set or the displayId is not a eDP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * data + * This output parameter specifies the data associated with the eDP display. + * It is only valid if this function returns NV_OK. + * NV0073_CTRL_CMD_DP_GET_EDP_DATA_PANEL_POWER + * This field indicates the state of the eDP panel power. + * NV0073_CTRL_CMD_DP_GET_EDP_DATA_PANEL_POWER_OFF + * This eDP panel is powered off. + * NV0073_CTRL_CMD_DP_GET_EDP_DATA_PANEL_POWER_ON + * This eDP panel is powered on. + * NV0073_CTRL_CMD_DP_GET_EDP_DATA_DPCD_POWER_OFF + * This field tells the client if DPCD power off command + * should be used for the current eDP panel. + * NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_OFF_ENABLE + * This eDP panel can use DPCD to power off the panel. + * NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_OFF_DISABLE + * This eDP panel cannot use DPCD to power off the panel. + * NV0073_CTRL_DP_GET_EDP_DATA_DPCD_SET_POWER + * This field tells the client current eDP panel DPCD SET_POWER (0x600) status + * NV0073_CTRL_DP_GET_EDP_DATA_DPCD_SET_POWER_D0 + * This eDP panel is current up and in full power mode. + * NV0073_CTRL_DP_GET_EDP_DATA_DPCD_SET_POWER_D3 + * This eDP panel is current standby. + */ +#define NV0073_CTRL_CMD_DP_GET_EDP_DATA (0x731361U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_EDP_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_GET_EDP_DATA_PARAMS_MESSAGE_ID (0x61U) + +typedef struct NV0073_CTRL_DP_GET_EDP_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 data; +} NV0073_CTRL_DP_GET_EDP_DATA_PARAMS; + +#define NV0073_CTRL_DP_GET_EDP_DATA_PANEL_POWER 0:0 +#define NV0073_CTRL_DP_GET_EDP_DATA_PANEL_POWER_OFF (0x00000000U) +#define NV0073_CTRL_DP_GET_EDP_DATA_PANEL_POWER_ON (0x00000001U) +#define NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_OFF 1:1 +#define NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_OFF_ENABLE (0x00000000U) +#define NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_OFF_DISABLE (0x00000001U) +#define NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_STATE 2:2 +#define NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_STATE_D0 (0x00000000U) +#define NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_STATE_D3 (0x00000001U) +/* + * NV0073_CTRL_CMD_DP_CONFIG_STREAM + * + * This command sets various multi/single stream related params for + * for a given head. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * Head + * Specifies the head index for the stream. + * sorIndex + * Specifies the SOR index for the stream. + * dpLink + * Specifies the DP link: either 0 or 1 (A , B) + * bEnableOverride + * Specifies whether we're manually configuring this stream. + * If not set, none of the remaining settings have any effect. + * bMST + * Specifies whether in Multistream or Singlestream mode. + * MST/SST + * Structures for passing in either Multistream or Singlestream params + * slotStart + * Specifies the start value of the timeslot + * slotEnd + * Specifies the end value of the timeslot + * PBN + * Specifies the PBN for the timeslot. + * minHBlank + * Specifies the min HBlank + * minVBlank + * Specifies the min VBlank + * sendACT -- deprecated. A new control call has been added. + * Specifies whether ACT has to be sent or not. + * tuSize + * Specifies TU size value + * watermark + * Specifies stream watermark. + * bEnableTwoHeadOneOr + * Whether two head one OR is enabled. If this is set then RM will + * replicate SF settings of Master head on Slave head. Head index + * passed should be of Master Head. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC: when this command has already been called + * + */ +#define NV0073_CTRL_CMD_DP_CONFIG_STREAM (0x731362U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS_MESSAGE_ID (0x62U) + +typedef struct NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvU32 sorIndex; + NvU32 dpLink; + + NvBool bEnableOverride; + NvBool bMST; + NvU32 singleHeadMultistreamMode; + NvU32 hBlankSym; + NvU32 vBlankSym; + NvU32 colorFormat; + NvBool bEnableTwoHeadOneOr; + + struct { + NvU32 slotStart; + NvU32 slotEnd; + NvU32 PBN; + NvU32 Timeslice; + NvBool sendACT; // deprecated -Use NV0073_CTRL_CMD_DP_SEND_ACT + NvU32 singleHeadMSTPipeline; + NvBool bEnableAudioOverRightPanel; + } MST; + + struct { + NvBool bEnhancedFraming; + NvU32 tuSize; + NvU32 waterMark; + NvBool bEnableAudioOverRightPanel; + } SST; +} NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_SET_RATE_GOV + * + * This command enables rate governing for a MST. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * Head + * Specifies the head index for the stream. + * sorIndex + * Specifies the SOR index for the stream. + * flags + * Specifies Rate Governing, trigger type and wait on trigger and operation type. + * + * _FLAGS_OPERATION: whether this control call should program or check for status of previous operation. + * + * _FLAGS_STATUS: Out only. Caller should check the status for _FLAGS_OPERATION_CHECK_STATUS through + * this bit. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC: when this command has already been called + * + */ +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV (0x731363U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_RATE_GOV_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_PARAMS_MESSAGE_ID (0x63U) + +typedef struct NV0073_CTRL_CMD_DP_SET_RATE_GOV_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvU32 sorIndex; + NvU32 flags; +} NV0073_CTRL_CMD_DP_SET_RATE_GOV_PARAMS; + +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_ENABLE_RG 0:0 +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_ENABLE_RG_OFF (0x00000000U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_ENABLE_RG_ON (0x00000001U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_TRIGGER_MODE 1:1 +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_TRIGGER_MODE_LOADV (0x00000000U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_TRIGGER_MODE_IMMEDIATE (0x00000001U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_WAIT_TRIGGER 2:2 +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_WAIT_TRIGGER_OFF (0x00000000U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_WAIT_TRIGGER_ON (0x00000001U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_OPERATION 3:3 +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_OPERATION_PROGRAM (0x00000000U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_OPERATION_CHECK_STATUS (0x00000001U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_STATUS 31:31 +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_STATUS_FAIL (0x00000000U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_STATUS_PASS (0x00000001U) + +/* + * NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT + * + * This call is used by the displayport library. Once + * all of the platforms have ported, this call will be + * deprecated and made the default behavior. + * + * Disables automatic watermark programming + * Disables automatic DP IRQ handling (CP IRQ) + * Disables automatic retry on defers + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT (0x731365U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS_MESSAGE_ID (0x65U) + +typedef struct NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS { + NvU32 subDeviceInstance; +} NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_SET_ECF + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * sorIndex + * This parameter specifies the Index of sor for which ecf + * should be updated. + * ecf + * This parameter has the ECF bit mask. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_CMD_DP_SET_ECF (0x731366U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_ECF_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SET_ECF_PARAMS_MESSAGE_ID (0x66U) + +typedef struct NV0073_CTRL_CMD_DP_SET_ECF_PARAMS { + NvU32 subDeviceInstance; + NvU32 sorIndex; + NV_DECLARE_ALIGNED(NvU64 ecf, 8); + NvBool bForceClearEcf; + NvBool bAddStreamBack; +} NV0073_CTRL_CMD_DP_SET_ECF_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_SEND_ACT + * + * This command sends ACT. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * displayId + * Specifies the root port displayId for which the trigger has to be done. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC: when this command has already been called + * + */ +#define NV0073_CTRL_CMD_DP_SEND_ACT (0x731367U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS_MESSAGE_ID (0x67U) + +typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; +} NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS; + + + +/* + * NV0073_CTRL_CMD_DP_GET_CAPS + * + * This command returns the following info + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * sorIndex + * Specifies the SOR index. + * dpVersionsSupported + * Specified the DP versions supported by the GPU + * UHBRSupportedByGpu + * Bitmask to specify the UHBR link rates supported by the GPU. + * bIsMultistreamSupported + * Returns NV_TRUE if MST is supported by the GPU else NV_FALSE + * bIsSCEnabled + * Returns NV_TRUE if Stream cloning is supported by the GPU else NV_FALSE + * maxLinkRate + * Returns Maximum allowed orclk for DP mode of SOR + * 1 signifies 5.40(HBR2), 2 signifies 2.70(HBR), 3 signifies 1.62(RBR) + * bHasIncreasedWatermarkLimits + * Returns NV_TRUE if the GPU uses higher watermark limits, else NV_FALSE + * bIsPC2Disabled + * Returns NV_TRUE if VBIOS flag to disable PostCursor2 is set, else NV_FALSE + * bFECSupported + * Returns NV_TRUE if GPU supports FEC, else NV_FALSE + * bIsTrainPhyRepeater + * Returns NV_TRUE if LTTPR Link Training feature is set + * bOverrideLinkBw + * Returns NV_TRUE if DFP limits defined in DCB have to be honored, else NV_FALSE + * bUseRgFlushSequence + * Returns NV_TRUE if GPU uses the new RG flush design + * bSupportDPDownSpread + * Returns NV_TRUE if GPU support downspread. + * bAvoidHBR3 + * Returns NV_TRUE if we need to avoid HBR3 as much as possible + * bPollingEnabledForDpMstDetection + * Returns NV_TRUE for N1X. + * - The Post-based approach introduced a delay in processing LAM and EDID events + * - This never introduced any delay. There is some delay from an unknown source which needs to be debugged + * bIsDpTunnelingHwBugWarEnabled + * Returns NV_TRUE if USB4 DP tunneling HW bug WAR is enabled for the chip. + * + * DSC caps + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ + +#define NV0073_CTRL_CMD_DP_GET_CAPS (0x731369U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID (0x69U) + +typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS { + NvU32 subDeviceInstance; + NvU32 sorIndex; + NvU32 maxLinkRate; + NvU32 dpVersionsSupported; + NvU32 UHBRSupportedByGpu; + NvBool bIsMultistreamSupported; + NvBool bIsSCEnabled; + NvBool bHasIncreasedWatermarkLimits; + NvBool bIsPC2Disabled; + NvBool isSingleHeadMSTSupported; + NvBool bFECSupported; + NvBool bIsTrainPhyRepeater; + NvBool bOverrideLinkBw; + NvBool bUseRgFlushSequence; + NvBool bSupportDPDownSpread; + NvBool bAvoidHBR3; + NvBool bPollingEnabledForDpMstDetection; + NvBool bIsDpTunnelingHwBugWarEnabled; + NV0073_CTRL_CMD_DSC_CAP_PARAMS DSC; +} NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS; + +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2 0:0 +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2_NO (0x00000000U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2_YES (0x00000001U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4 1:1 +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_NO (0x00000000U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_YES (0x00000001U) + +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP2_0 2:2 +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP2_0_NO (0x00000000U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP2_0_YES (0x00000001U) + + +#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE 2:0 +#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_NONE (0x00000000U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_1_62 (0x00000001U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_2_70 (0x00000002U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_5_40 (0x00000003U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_8_10 (0x00000004U) + +#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR10_0 0:0 +#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR10_0_NO (0x00000000U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR10_0_YES (0x00000001U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR13_5 1:1 +#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR13_5_NO (0x00000000U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR13_5_YES (0x00000001U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR20_0 2:2 +#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR20_0_NO (0x00000000U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR20_0_YES (0x00000001U) + + +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_RGB (0x00000001U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_444 (0x00000002U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_422 (0x00000004U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_420 (0x00000008U) + +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_16 (0x00000001U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_8 (0x00000002U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_4 (0x00000003U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_2 (0x00000004U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1 (0x00000005U) + +#define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES (0x73136aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_MSA_PROPERTIES_SYNC_POLARITY_LOW (0U) +#define NV0073_CTRL_CMD_DP_MSA_PROPERTIES_SYNC_POLARITY_HIGH (1U) + +typedef struct NV0073_CTRL_DP_MSA_PROPERTIES_MASK { + NvU8 miscMask[2]; + NvBool bRasterTotalHorizontal; + NvBool bRasterTotalVertical; + NvBool bActiveStartHorizontal; + NvBool bActiveStartVertical; + NvBool bSurfaceTotalHorizontal; + NvBool bSurfaceTotalVertical; + NvBool bSyncWidthHorizontal; + NvBool bSyncPolarityHorizontal; + NvBool bSyncHeightVertical; + NvBool bSyncPolarityVertical; + NvBool bReservedEnable[3]; +} NV0073_CTRL_DP_MSA_PROPERTIES_MASK; + +typedef struct NV0073_CTRL_DP_MSA_PROPERTIES_VALUES { + NvU8 misc[2]; + NvU16 rasterTotalHorizontal; + NvU16 rasterTotalVertical; + NvU16 activeStartHorizontal; + NvU16 activeStartVertical; + NvU16 surfaceTotalHorizontal; + NvU16 surfaceTotalVertical; + NvU16 syncWidthHorizontal; + NvU16 syncPolarityHorizontal; + NvU16 syncHeightVertical; + NvU16 syncPolarityVertical; + NvU8 reserved[3]; +} NV0073_CTRL_DP_MSA_PROPERTIES_VALUES; + +#define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS_MESSAGE_ID (0x6AU) + +typedef struct NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bEnableMSA; + NvBool bStereoPhaseInverse; + NvBool bCacheMsaOverrideForNextModeset; + NV0073_CTRL_DP_MSA_PROPERTIES_MASK featureMask; + NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureValues; + NV_DECLARE_ALIGNED(struct NV0073_CTRL_DP_MSA_PROPERTIES_VALUES *pFeatureDebugValues, 8); +} NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT + * + * This command can be used to invoke a fake interrupt for the operation of DP1.2 branch device + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * interruptType + * This parameter specifies the type of fake interrupt to be invoked. Possible values are: + * 0 => IRQ + * 1 => HPDPlug + * 2 => HPDUnPlug + * displayId + * should be for DP only + * + */ + +#define NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT (0x73136bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_PARAMS_MESSAGE_ID (0x6BU) + +typedef struct NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 interruptType; +} NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_PARAMS; + +#define NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_IRQ (0x00000000U) +#define NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_PLUG (0x00000001U) +#define NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_UNPLUG (0x00000002U) + +/* + * NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG + * + * This command sets the MS displayId lit up by driver for further use of VBIOS + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * should be for DP only + * activeDevAddr + * Active MS panel address + * sorIndex + * SOR Index + * dpLink + * DP Sub Link Index + * hopCount + * Maximum hopcounts in MS address + * dpMsDevAddrState + * DP Multistream Device Address State. The values can be + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_TIMEOUT + * + */ +#define NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG (0x73136cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG_PARAMS_MESSAGE_ID (0x6CU) + +typedef struct NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 activeDevAddr; + NvU32 sorIndex; + NvU32 dpLink; + NvU32 hopCount; + NvU32 dpMsDevAddrState; +} NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG_PARAMS; + + + +/* +* NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT +* +* This command configures a new bit, NV_PDISP_SF_DP_LINKCTL_TRIGGER_SELECT +* to indicate which pipeline will handle the +* time slots allocation in single head MST mode +* +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. This parameter must specify a value between zero and the +* total number of subdevices within the parent device. This parameter +* should be set to zero for default behavior +* Head +* Specifies the head index for the stream +* sorIndex +* Specifies the SOR index for the stream +* streamIndex +* Stream Identifier +* +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_ARGUMENT +* NV_ERR_GENERIC: when this command has already been called +* +*/ +#define NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT (0x73136fU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT_PARAMS_MESSAGE_ID (0x6FU) + +typedef struct NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvU32 sorIndex; + NvU32 singleHeadMSTPipeline; +} NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT_PARAMS; + +/* +* NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM +* +* This call is used by the displayport library.& clients of RM +* Its main function is to configure single Head Multi stream mode + * this call configures internal RM datastructures to support required mode. +* +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. This parameter must specify a value between zero and the +* total number of subdevices within the parent device. This parameter +* should be set to zero for default behavior. +* +* displayIDs +* This parameter specifies array of DP displayIds to be configured which are driven out from a single head. +* +* numStreams +* This parameter specifies number of streams driven from a single head +* ex: for 2SST & 2MST its value is 2. +* +* mode +* This parameter specifies single head multi stream mode to be configured. +* +* bSetConfigure +* This parameter configures single head multistream mode +* if TRUE it sets SST or MST based on 'mode' parameter and updates internal driver data structures with the given information. +* if FALSE clears the configuration of single head multi stream mode. +* +* vbiosPrimaryDispIdIndex +* This parameter specifies vbios master displayID index in displayIDs input array. +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_ARGUMENT +* NV_ERR_NOT_SUPPORTED +* +*/ +#define NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM (0x73136eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SINGLE_HEAD_MAX_STREAMS (0x00000002U) +#define NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM_PARAMS_MESSAGE_ID (0x6EU) + +typedef struct NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayIDs[NV0073_CTRL_CMD_DP_SINGLE_HEAD_MAX_STREAMS]; + NvU32 numStreams; + NvU32 mode; + NvBool bSetConfig; + NvU8 vbiosPrimaryDispIdIndex; +} NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM_PARAMS; + +#define NV0073_CTRL_CMD_DP_SINGLE_HEAD_MULTI_STREAM_NONE (0x00000000U) +#define NV0073_CTRL_CMD_DP_SINGLE_HEAD_MULTI_STREAM_MODE_SST (0x00000001U) +#define NV0073_CTRL_CMD_DP_SINGLE_HEAD_MULTI_STREAM_MODE_MST (0x00000002U) + +/* +* NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL +* +* This command configures a new bit, NV_PDISP_SF_DP_LINKCTL_TRIGGER_ALL +* to indicate which if all the pipelines to take affect on ACT (sorFlushUpdates) +* in single head MST mode +* +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. This parameter must specify a value between zero and the +* total number of subdevices within the parent device. This parameter +* should be set to zero for default behavior +* Head +* Specifies the head index for the stream +* sorIndex +* Specifies the SOR index for the stream +* streamIndex +* Stream Identifier +* +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_ARGUMENT +* NV_ERR_GENERIC: when this command has already been called +* +*/ +#define NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL (0x731370U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL_PARAMS_MESSAGE_ID (0x70U) + +typedef struct NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvBool enable; +} NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL_PARAMS; + +/* NV0073_CTRL_CMD_SPECIFIC_RETRIEVE_DP_RING_BUFFER + * + * These commands retrieves buffer from RM for + * DP Library to dump logs + * + * + * Possible status values returned include: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_DP_RETRIEVE_DP_RING_BUFFER (0x731371U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_RETRIEVE_DP_RING_BUFFER_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_RETRIEVE_DP_RING_BUFFER_PARAMS_MESSAGE_ID (0x71U) + +typedef struct NV0073_CTRL_CMD_DP_RETRIEVE_DP_RING_BUFFER_PARAMS { + NV_DECLARE_ALIGNED(NvU8 *pDpRingBuffer, 8); + NvU8 ringBufferType; + NvU32 numRecords; +} NV0073_CTRL_CMD_DP_RETRIEVE_DP_RING_BUFFER_PARAMS; + + + +/* +* NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA +* +* This command collects the DP AUX log from the RM aux buffer and +* sends it to the application. +* +* dpAuxBufferReadSize +* Specifies the number of logs to be read from the +* AUX buffer in RM +* dpNumMessagesRead +* Specifies the number of logs read from the AUX buffer +* dpAuxBuffer +* The local buffer to copy the specified number of logs +* from RM to user application +* +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_ARGUMENT +* NV_ERR_GENERIC: when this command has already been called +* +* +*DPAUXPACKET - This structure holds the log information +* auxPacket - carries the hex dump of the message transaction +* auxEvents - Contains the information as in what request and reply type where +* auxRequestTimeStamp - Request timestamp +* auxMessageReqSize - Request Message size +* auxMessageReplySize - Reply message size(how much information was actually send by receiver) +* auxOutPort - DP port number +* auxPortAddress - Address to which data was requested to be read or written +* auxReplyTimeStamp - Reply timestamp +* auxCount - Serial number to keep track of transactions +*/ + +/*Maximum dp messages size is 16 as per the protocol*/ +#define DP_MAX_MSG_SIZE 16U +#define MAX_LOGS_PER_POLL 50U + +/* Various kinds of DP Aux transactions */ +#define NV_DP_AUXLOGGER_REQUEST_TYPE 3:0 +#define NV_DP_AUXLOGGER_REQUEST_TYPE_NULL 0x00000000U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_I2CWR 0x00000001U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_I2CREQWSTAT 0x00000002U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_MOTWR 0x00000003U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_MOTREQWSTAT 0x00000004U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_AUXWR 0x00000005U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_I2CRD 0x00000006U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_MOTRD 0x00000007U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_AUXRD 0x00000008U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_UNKNOWN 0x00000009U + +#define NV_DP_AUXLOGGER_REPLY_TYPE 7:4 +#define NV_DP_AUXLOGGER_REPLY_TYPE_NULL 0x00000000U +#define NV_DP_AUXLOGGER_REPLY_TYPE_SB_ACK 0x00000001U +#define NV_DP_AUXLOGGER_REPLY_TYPE_RETRY 0x00000002U +#define NV_DP_AUXLOGGER_REPLY_TYPE_TIMEOUT 0x00000003U +#define NV_DP_AUXLOGGER_REPLY_TYPE_DEFER 0x00000004U +#define NV_DP_AUXLOGGER_REPLY_TYPE_DEFER_TO 0x00000005U +#define NV_DP_AUXLOGGER_REPLY_TYPE_ACK 0x00000006U +#define NV_DP_AUXLOGGER_REPLY_TYPE_ERROR 0x00000007U +#define NV_DP_AUXLOGGER_REPLY_TYPE_UNKNOWN 0x00000008U + +#define NV_DP_AUXLOGGER_EVENT_TYPE 9:8 +#define NV_DP_AUXLOGGER_EVENT_TYPE_AUX 0x00000000U +#define NV_DP_AUXLOGGER_EVENT_TYPE_HOT_PLUG 0x00000001U +#define NV_DP_AUXLOGGER_EVENT_TYPE_HOT_UNPLUG 0x00000002U +#define NV_DP_AUXLOGGER_EVENT_TYPE_IRQ 0x00000003U + +#define NV_DP_AUXLOGGER_AUXCTL_CMD 15:12 +#define NV_DP_AUXLOGGER_AUXCTL_CMD_INIT 0x00000000U +#define NV_DP_AUXLOGGER_AUXCTL_CMD_I2CWR 0x00000000U +#define NV_DP_AUXLOGGER_AUXCTL_CMD_I2CRD 0x00000001U +#define NV_DP_AUXLOGGER_AUXCTL_CMD_I2CREQWSTAT 0x00000002U +#define NV_DP_AUXLOGGER_AUXCTL_CMD_MOTWR 0x00000004U +#define NV_DP_AUXLOGGER_AUXCTL_CMD_MOTRD 0x00000005U +#define NV_DP_AUXLOGGER_AUXCTL_CMD_MOTREQWSTAT 0x00000006U +#define NV_DP_AUXLOGGER_AUXCTL_CMD_AUXWR 0x00000008U +#define NV_DP_AUXLOGGER_AUXCTL_CMD_AUXRD 0x00000009U + + +typedef struct DPAUXPACKET { + NvU32 auxEvents; + NvU32 auxRequestTimeStamp; + NvU32 auxMessageReqSize; + NvU32 auxMessageReplySize; + NvU32 auxOutPort; + NvU32 auxPortAddress; + NvU32 auxReplyTimeStamp; + NvU32 auxCount; + NvU8 auxPacket[DP_MAX_MSG_SIZE]; +} DPAUXPACKET; +typedef struct DPAUXPACKET *PDPAUXPACKET; + +#define NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA (0x731373U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA_PARAMS_MESSAGE_ID (0x73U) + +typedef struct NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA_PARAMS { + //In + NvU32 subDeviceInstance; + NvU32 dpAuxBufferReadSize; + + //Out + NvU32 dpNumMessagesRead; + DPAUXPACKET dpAuxBuffer[MAX_LOGS_PER_POLL]; +} NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA_PARAMS; + + + + +/* NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES + * + * This setup link rate table for target display to enable indexed link rate + * and export valid link rates back to client. Client may pass empty table to + * reset previous setting. + * + * subDeviceInstance + * client will give a subdevice to get right pGpu/pDisp for it + * displayId + * DisplayId of the display for which the client targets + * linkRateTbl + * Link rates in 200KHz as native granularity from eDP 1.4 + * linkBwTbl + * Link rates valid for client to apply to + * linkBwCount + * Total valid link rates + * + * Possible status values returned include: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES (0x731377U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES 8U + +#define NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS_MESSAGE_ID (0x77U) + +typedef struct NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS { + // In + NvU32 subDeviceInstance; + NvU32 displayId; + NvU16 linkRateTbl[NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES]; + + // Out + NvU16 linkBwTbl[NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES]; + NvU8 linkBwCount; +} NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS; + + +/* + * NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES + * + * This command is used to not depend on supervisor interrupts for setting the + * stereo msa params. We will not cache the values and can toggle stereo using + * this ctrl call on demand. Note that this control call will only change stereo + * settings and will leave other settings as is. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * should be for DP only + * bEnableMSA + * To enable or disable MSA + * bStereoPhaseInverse + * To enable or disable Stereo Phase Inverse value + * featureMask + * Enable/Disable mask of individual MSA property. + * featureValues + * MSA property value to write + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_TIMEOUT + * + */ +#define NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES (0x731378U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES_PARAMS_MESSAGE_ID (0x78U) + +typedef struct NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bEnableMSA; + NvBool bStereoPhaseInverse; + NV0073_CTRL_DP_MSA_PROPERTIES_MASK featureMask; + NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureValues; +} NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES_PARAMS; + + + +/* + * NV0073_CTRL_CMD_DP_CONFIGURE_FEC + * + * This command is used to enable/disable FEC on DP Mainlink. + * FEC is a prerequisite to DSC. This should be called only + * after LT completes (including PostLT LQA) while enabling. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * displayId + * Can only be 1 and must be DP. + * + * bEnableFec + * To enable or disable FEC + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV0073_CTRL_CMD_DP_CONFIGURE_FEC (0x73137aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIGURE_FEC_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_CONFIGURE_FEC_PARAMS_MESSAGE_ID (0x7AU) + +typedef struct NV0073_CTRL_CMD_DP_CONFIGURE_FEC_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bEnableFec; +} NV0073_CTRL_CMD_DP_CONFIGURE_FEC_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior + * cmd + * This parameter is an input to this command. + * Here are the current defined fields: + * NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_CMD_POWER + * Set to specify what operation to run. + * NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_CMD_POWER_UP + * Request to power up pad. + * NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_CMD_POWER_DOWN + * Request to power down the pad. + * linkBw + * This parameter is used to pass in the link bandwidth required to run the + * power up sequence. Refer enum DP_LINK_BANDWIDTH for valid values. + * laneCount + * This parameter is used to pass the lanecount. + * sorIndex + * This parameter is used to pass the SOR index. + * sublinkIndex + * This parameter is used to pass the sublink index. Please refer + * enum DFPLINKINDEX for valid values + * priPadLinkIndex + * This parameter is used to pass the padlink index for primary link. + * Please refer enum DFPPADLINK for valid index values for Link A~F. + * secPadLinkIndex + * This parameter is used to pass the padlink index for secondary link. + * For Single SST pass in NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PADLINK_INDEX_INVALID + * bEnableSpread + * This parameter is boolean value used to indicate if spread is to be enabled or disabled. + */ + +#define NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD (0x73137bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PARAMS_MESSAGE_ID (0x7BU) + +typedef struct NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PARAMS { + NvU32 subDeviceInstance; + NvU32 cmd; + NvU32 linkBw; + NvU32 laneCount; + NvU32 sorIndex; + NvU32 sublinkIndex; // sublink A/B + NvU32 priPadLinkIndex; // padlink A/B/C/D/E/F + NvU32 secPadLinkIndex; // padlink A/B/C/D/E/F for secondary link in DualSST case. + NvBool bEnableSpread; +} NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PARAMS; + +#define NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_CMD_POWER 0:0 +#define NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_CMD_POWER_UP (0x00000000U) +#define NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_CMD_POWER_DOWN (0x00000001U) + +#define NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PADLINK_INDEX_INVALID (0x000000FFU) + +/* + * NV0073_CTRL_CMD_DP_AUXCH_CTRL + * + * This command can be used to perform the I2C Bulk transfer over + * DP Aux channel. This is the display port specific implementation + * for sending bulk data over the DpAux channel, by splitting up the + * data into pieces and retrying for pieces that aren't ACK'd. + * + * subDeviceInstance [IN] + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId [IN] + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must a dfp display. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * addr [IN] + * This parameter is an input to this command. The addr parameter follows + * Section 2.4 in DisplayPort spec and the client should refer to the valid + * address in DisplayPort spec. Only the first 20 bits are valid. + * bWrite [IN] + * This parameter specifies whether the command is a I2C write (NV_TRUE) or + * a I2C read (NV_FALSE). + * data [IN/OUT] + * In the case of a read transaction, this parameter returns the data from + * transaction request. In the case of a write transaction, the client + * should write to this buffer for the data to send. + * size [IN/OUT] + * Specifies how many data bytes to read/write depending on the + * transaction type. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_DP_AUXCH_I2C_TRANSFER_CTRL (0x73137cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_MAX_DATA_SIZE 256U + +#define NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_CTRL_PARAMS_MESSAGE_ID (0x7CU) + +typedef struct NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 addr; + NvBool bWrite; + NvU8 data[NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_MAX_DATA_SIZE]; + NvU32 size; +} NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_CTRL_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_ENABLE_VRR + * + * The command is used to enable VRR. + * + * subDeviceInstance [IN] + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior + * displayId [IN] + * This parameter is an input to this command, specifies the ID of the display + * for client targeted to. + * The display ID must a DP display. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * cmd [IN] + * This parameter is an input to this command. + * + * _STAGE: specifies the stage id to execute in the VRR enablement sequence. + * _MONITOR_ENABLE_BEGIN: Send command to the monitor to start monitor + * enablement procedure. + * _MONITOR_ENABLE_CHALLENGE: Send challenge to the monitor + * _MONITOR_ENABLE_CHECK: Read digest from the monitor, and verify + * if the result is valid. + * _DRIVER_ENABLE_BEGIN: Send command to the monitor to start driver + * enablement procedure. + * _DRIVER_ENABLE_CHALLENGE: Read challenge from the monitor and write back + * corresponding digest. + * _DRIVER_ENABLE_CHECK: Check if monitor enablement worked. + * _RESET_MONITOR: Set the FW state m/c to a known state. + * _INIT_PUBLIC_INFO: Send command to the monitor to prepare public info. + * _GET_PUBLIC_INFO: Read public info from the monitor. + * _STATUS_CHECK: Check if monitor is ready for next command. + * result [OUT] + * This is an output parameter to reflect the result of the operation. + */ +#define NV0073_CTRL_CMD_DP_ENABLE_VRR (0x73137dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS_MESSAGE_ID (0x7DU) + +typedef struct NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 cmd; + NvU32 result; +} NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS; + +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE 3:0 +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_MONITOR_ENABLE_BEGIN (0x00000000U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_MONITOR_ENABLE_CHALLENGE (0x00000001U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_MONITOR_ENABLE_CHECK (0x00000002U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_DRIVER_ENABLE_BEGIN (0x00000003U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_DRIVER_ENABLE_CHALLENGE (0x00000004U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_DRIVER_ENABLE_CHECK (0x00000005U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_RESET_MONITOR (0x00000006U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_INIT_PUBLIC_INFO (0x00000007U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_GET_PUBLIC_INFO (0x00000008U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_STATUS_CHECK (0x00000009U) + +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_OK (0x00000000U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_PENDING (0x80000001U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_READ_ERROR (0x80000002U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_WRITE_ERROR (0x80000003U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_DEVICE_ERROR (0x80000004U) + +/* + * NV0073_CTRL_CMD_DP_GET_GENERIC_INFOFRAME + * + * This command is used to capture the display output packets for DP protocol. + * Common supported packets are Dynamic Range and mastering infoframe SDP for HDR, + * VSC SDP for colorimetry and pixel encoding info. + * + * displayID (in) + * This parameter specifies the displayID for the display resource to configure. + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the NV04_DISPLAY_COMMON + * parent device to which the operation should be directed. + * infoframeIndex (in) + * HW provides support to program 2 generic infoframes per frame for DP. + * This parameter indicates which infoframe packet is to be captured. + * Possible flags are as follows: + * NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_CAPTURE_MODE + * This flag indicates the INFOFRAME that needs to be read. + * Set to _INFOFRAME0 if RM should read GENERIC_INFOFRAME + * Set to _INFOFRAME1 if RM should read GENERIC_INFOFRAME1 + * packet (out) + * pPacket points to the memory for reading the infoframe packet. + * bTransmitControl (out) + * This gives the transmit mode of infoframes. + * If set, means infoframe will be sent as soon as possible and then on + * every frame during vblank. + * If cleared, means the infoframe will be sent once as soon as possible. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_DP_GET_GENERIC_INFOFRAME (0x73137eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_GENERIC_INFOFRAME_MAX_PACKET_SIZE 36U + +#define NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_PARAMS_MESSAGE_ID (0x7EU) + +typedef struct NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 infoframeIndex; + NvU8 packet[NV0073_CTRL_DP_GENERIC_INFOFRAME_MAX_PACKET_SIZE]; + NvBool bTransmitControl; +} NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_PARAMS; + + +#define NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_CAPTURE_MODE 0:0 +#define NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_CAPTURE_MODE_INFOFRAME0 (0x0000000U) +#define NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_CAPTURE_MODE_INFOFRAME1 (0x0000001U) + + +/* + * NV0073_CTRL_CMD_DP_GET_MSA_ATTRIBUTES + * + * This command is used to capture the various data attributes sent in the MSA for DP protocol. + * Refer table 2-94 'MSA Data Fields' in DP1.4a spec document for MSA data field description. + * + * displayID (in) + * This parameter specifies the displayID for the display resource to configure. + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the NV04_DISPLAY_COMMON + * parent device to which the operation should be directed. + * mvid, nvid (out) + * Video timestamp used by DP sink for regenerating pixel clock. + * misc0, misc1 (out) + * Miscellaneous MSA attributes. + * hTotal, vTotal (out) + * Htotal measured in pixel count and vtotal measured in line count. + * hActiveStart, vActiveStart (out) + * Active start measured from start of leading edge of the sync pulse. + * hActiveWidth, vActiveWidth (out) + * Active video width and height. + * hSyncWidth, vSyncWidth (out) + * Width of sync pulse. + * hSyncPolarity, vSyncPolarity (out) + * Polarity of sync pulse. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_DP_GET_MSA_ATTRIBUTES (0x73137fU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_MSA_ATTRIBUTES_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_MSA_MAX_DATA_SIZE 7U + +#define NV0073_CTRL_DP_GET_MSA_ATTRIBUTES_PARAMS_MESSAGE_ID (0x7FU) + +typedef struct NV0073_CTRL_DP_GET_MSA_ATTRIBUTES_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 mvid; + NvU32 nvid; + NvU8 misc0; + NvU8 misc1; + NvU16 hTotal; + NvU16 vTotal; + NvU16 hActiveStart; + NvU16 vActiveStart; + NvU16 hActiveWidth; + NvU16 vActiveWidth; + NvU16 hSyncWidth; + NvU16 vSyncWidth; + NvBool hSyncPolarity; + NvBool vSyncPolarity; +} NV0073_CTRL_DP_GET_MSA_ATTRIBUTES_PARAMS; + +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_MVID 23:0 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_NVID 23:0 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_MISC0 7:0 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_MISC1 15:8 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_HTOTAL 15:0 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_VTOTAL 31:16 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_HACTIVE_START 15:0 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_VACTIVE_START 31:16 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_HACTIVE_WIDTH 15:0 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_VACTIVE_WIDTH 31:16 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_HSYNC_WIDTH 14:0 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_HSYNC_POLARITY 15:15 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_VSYNC_WIDTH 30:16 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_VSYNC_POLARITY 31:31 + +/* + * NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL + * + * This command is used to query OD capability and status as well as + * control OD functionality of eDP LCD panels. + * + * subDeviceInstance [in] + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId [in] + * This parameter specifies the ID of the DP display which owns + * the Main Link to be adjusted. The display ID must a DP display + * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * cmd [in] + * This parameter is an input to this command. The cmd parameter tells + * whether we have to get the value of a specific field or set the + * value in case of a writeable field. + * control [in] + * This parameter is input by the user. It is used by the user to decide the control + * value to be written to change the Sink OD mode. The command to write is + * the NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET command. + * bOdCapable [out] + * This parameter reflects the OD capability of the Sink which can be + * fetched by using the NV0073_CTRL_CMD_DP_AUXCH_OD_CAPABLE_QUERY command. + * bOdControlCapable [out] + * This parameter reflects the OD control capability of the Sink which can be + * fetched by using the NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_CAPABLE_QUERY command. + * bOdStatus [out] + * This parameter reflects the Sink OD status which can be + * fetched by using the NV0073_CTRL_CMD_DP_AUXCH_OD_STATUS_QUERY command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL (0x731380U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS_MESSAGE_ID (0x80U) + +typedef struct NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU8 control; + NvU8 cmd; + NvBool bOdCapable; + NvBool bOdControlCapable; + NvBool bOdStatus; +} NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS; + +/* valid commands */ +#define NV0073_CTRL_CMD_DP_AUXCHQUERY_OD_CAPABLE 0x00000000 +#define NV0073_CTRL_CMD_DP_AUXCHQUERY_OD_CTL_CAPABLE 0x00000001 +#define NV0073_CTRL_CMD_DP_AUXCHQUERY_OD_STATUS 0x00000002 +#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET 0x00000003 + +/* valid state values */ +#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET_AUTONOMOUS 0x00000000 +#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET_DISABLE_OD 0x00000002 +#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET_ENABLE_OD 0x00000003 + +/* + * NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES + * + * This command returns the following info + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * should be for DP only + * bEnableMSA + * To enable or disable MSA + * bStereoPhaseInverse + * To enable or disable Stereo Phase Inverse value + * bCacheMsaOverrideForNextModeset + * Cache the values and don't apply them until next modeset + * featureMask + * Enable/Disable mask of individual MSA property + * featureValues + * MSA property value to write + * bDebugValues + * To inform whether actual MSA values need to be returned + * pFeatureDebugValues + * It will actual MSA property value being written on HW. + * If its NULL then no error but return nothing + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_TIMEOUT + * + */ +#define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2 (0x731381U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bEnableMSA; + NvBool bStereoPhaseInverse; + NvBool bCacheMsaOverrideForNextModeset; + NV0073_CTRL_DP_MSA_PROPERTIES_MASK featureMask; + NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureValues; + NvBool bDebugValues; + NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureDebugValues; +} NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS; + +/* + * NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL + * + * This command is used to trigger link training on DP2.x device with 128b132b channel encoding. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * displayId + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must a dfp display. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * + * cmd + * This parameter is an input to this command. + * Here are the current defined fields: + * 1.Ask RM to enter specific stage + * NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING + * NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET + * _PRE_LT : Request RM to get ready for 128b/132b Link Training. + * _CHNL_EQ : Request RM to start Channel Equalization phase. + * _CDS : Request RM to start Clock Data Switch phase. + * _POST_LT : Request RM to clean up/sync up once 128b/132b LT is done. + * + * _SET_* only valid if _SETTING_TRUE + * + * 2.Ask RM to check the completion of specific stage + * NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLLING + * NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_CHNL_EQ_DONE + * _CHNL_EQ_INTERLANE_ALIGN + * _CDS + * _POLL_* only valid if _POLLING_TRUE + * + * _SETTING_TRUE and _POLLING_TRUE are mutual exclusive. + * RM will return NV_ERR_INVALID_ARGUMENT if both bit are set. + * + * 3.Downspread configuration + * NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD + * Specifies whether RM should be forced to enable or disable the DP + * Downspread setting. This can be used along with the Fake link + * training option so that we can configure the GPU to enable/disable + * spread when a real display is not connected. + * + * NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD_NO (default behavior) + * RM will enable Downspread when the display supports it. + * NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD_YES + * RM will enable/disable Downspread according to _SET_DOWNSPREAD field. + * + * NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD + * Specifies if RM should enable or disable downspread. + * Only valid when _FORCED_DOWNSPREAD is set to _YES + * + * NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD_ENABLE + * RM will enable Downspread even if the display does not support it. + * NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD_DISABLE + * RM will not enable Downspread even if the display does support it. + * + * 4.NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING + * This field specifies if fake link training is to be done. This will + * program enough of the hardware to avoid any hardware hangs and + * depending upon option chosen by the client, OR will be enabled for + * transmisssion. + * + * NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_NO + * No Fake LT will be performed + * NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_DONOT_TOGGLE_TRANSMISSION + * SOR will be not powered up during Fake LT + * NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_TOGGLE_TRANSMISSION_ON + * SOR will be powered up during Fake LT + * + * 5.NV0073_CTRL_DP2X_CMD_FALLBACK_CONFIG + * + * 6.NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING + * Specifies whether RM should skip HW training of the link. + * If this is the case then RM only updates its SW state without actually + * touching any HW registers. Clients should use this ONLY if it has determined - + * a. link is trained and not lost + * b. desired link config is same as current trained link config + * c. link is not in D3 (should be in D0) + * + * NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING_NO + * RM doesn't skip HW LT as the current Link Config is not the same as the + * requested Link Config. + * NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING_YES + * RM skips HW LT and only updates its SW state as client has determined that + * the current state of the link and the requested Link Config is the same. + * + * data + * This parameter is an input and output to this command. + * Here are the current defined fields: + * NV0073_CTRL_DP2X_DATA_LANE_COUNT + * Valid values: 0, 1, 2, 4 + * NV0073_CTRL_DP2X_DATA_LINK_BW + * Valid values: all standard link rates defined in DP2.x and ILRs defined in eDP spec. + * + * NV0073_CTRL_DP2X_DATA_RESET_LINK_REASON + * Only valid when NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING and + * NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET_PRE_LT are both set. + * Valid value: + * NV0073_CTRL_DP2X_DATA_RESET_REASON_START_LT: + * RM clears 0x102. + * NV0073_CTRL_DP2X_DATA_RESET_REASON_FALLBACK: + * RM clears 0x102 then clears 0x103-0x106. + * NV0073_CTRL_DP2X_DATA_RESET_REASON_CHANNEL_CODING: + * RM puts DPRX to D3 then clears 0x103-0x106. + * + * pollingInfo + * This parameter is an output to this command. + * Here are the current defined fields: + * + * NV0073_CTRL_DP2X_POLLING_INFO_TRAINING_AUX_RD_INTERVAL + * For Channel equalization, the polling interval is defined in DPCD 0x2216. + * RM report to DPLib when _SET_STAGE is set to _CHNL_EQ. + * Polling interval for Channel Equalization is defined as + * (128b132b_DP_TRAINING_AUX_RD_INTERVAL value + 1) * 128b132b_DP_TRAINING_AUX_RD_INTERVAL_UNIT. + * The maximum is 256 ms. + * (For CDS stage, the polling interval is fixed at 3ms.) + * + * NV0073_CTRL_DP2X_POLLING_INFO_TRAINING_AUX_RD_INTERVAL_UNIT + * Unit mapping for polling interval is + * 0 = 2ms + * 1 = 1ms + * + * NV0073_CTRL_DP2X_POLLING_INFO_TRAINING_AUX_RD_INTERVAL_UNIT_2MS + * NV0073_CTRL_DP2X_POLLING_INFO_TRAINING_AUX_RD_INTERVAL_UNIT_1MS + * + * NV0073_CTRL_DP2X_POLLING_INFO_RESULT + * _DONE: if the specified stage is done. + * _PENDING: if the specified stage is still pending. + * + * err + * This parameter provides info regarding the outcome of this calling control call. + * If zero, no errors were found. + * Otherwise, this parameter will specify the error detected. + * The valid parameter is broken down as follows: + * NV0073_CTRL_DP2X_ERR_CHANNEL_EQ_DONE + * If set to _ERR, link training failed at channel equalization phase. + * NV0073_CTRL_DP2X_ERR_CDS_DONE + * If set to _ERR, link training failed at CDS phase. + * NV0073_CTRL_DP2X_ERR_TIMEOUT + * If set to _ERR, link training failed because of timeout. + * NV0073_CTRL_DP2X_ERR_LT_FAILED + * If set to _ERR, link training failed. + * NV0073_CTRL_DP2X_ERR_INVALID_PARAMETER + * If set to _ERR, link configuration or displayID is invalid. + * NV0073_CTRL_DP2X_ERR_SET_LANE_COUNT + * If set to _ERR, link training failed when setting lane count. + * NV0073_CTRL_DP2X_ERR_SET_LINK_BW + * If set to _ERR, link training failed when setting link rate. + * NV0073_CTRL_DP2X_ERR_ENABLE_FEC + * If set to _ERR, link training failed when enabling FEC. + * NV0073_CTRL_DP2X_ERR_CONFIG_LTTPR + * If set to _ERR, link training failed when setting LTTPR. + * NV0073_CTRL_DP2X_ERR_PRE_LT + * If set to _ERR, link training failed before link training start. + * NV0073_CTRL_DP2X_ERR_LINK_STATUS + * If set to _DISCONNECTED, link training failed and link is disconnected / unplugged. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_ERROR + */ + +#define NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL (0x731383U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS_MESSAGE_ID (0x83U) + +typedef struct NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 cmd; + NvU32 data; + NvU32 pollingInfo; + NvU32 err; +} NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS; + +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING 0:0 +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING_FALSE (0x00000000U) +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING_TRUE (0x00000001U) +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET 3:1 +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET_RESET_LINK (0x00000000U) +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET_PRE_LT (0x00000001U) +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET_CHNL_EQ (0x00000002U) +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET_CDS (0x00000003U) +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET_POST_LT (0x00000004U) +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLLING 8:8 +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLLING_FALSE (0x00000000U) +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLLING_TRUE (0x00000001U) +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL 10:9 +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_RESET_LINK (0x00000000U) +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_CHNL_EQ_DONE (0x00000001U) +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_CHNL_EQ_INTERLANE_ALIGN (0x00000002U) +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_CDS (0x00000003U) + +// Flags for link training. +#define NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD 16:16 +#define NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD_NO (0x00000000U) +#define NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD_YES (0x00000001U) +#define NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD 17:17 +#define NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD_DISABLE (0x00000000U) +#define NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD_ENABLE (0x00000001U) +#define NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING 18:18 +#define NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING_NO (0x00000000U) +#define NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING_YES (0x00000001U) +#define NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING 20:19 +#define NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_NO (0x00000000U) +#define NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_DONOT_TOGGLE_TRANSMISSION (0x00000001U) +#define NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_TOGGLE_TRANSMISSION_ON (0x00000002U) +#define NV0073_CTRL_DP2X_CMD_FALLBACK_CONFIG 21:21 +#define NV0073_CTRL_DP2X_CMD_FALLBACK_CONFIG_FALSE (0x00000000U) +#define NV0073_CTRL_DP2X_CMD_FALLBACK_CONFIG_TRUE (0x00000001U) + +// Basic Data for Link training: Lane count and bandwidth. +#define NV0073_CTRL_DP2X_DATA_LANE_COUNT 3:0 +#define NV0073_CTRL_DP2X_DATA_LANE_COUNT_0 (0x00000000U) +#define NV0073_CTRL_DP2X_DATA_LANE_COUNT_1 (0x00000001U) +#define NV0073_CTRL_DP2X_DATA_LANE_COUNT_2 (0x00000002U) +#define NV0073_CTRL_DP2X_DATA_LANE_COUNT_4 (0x00000004U) +#define NV0073_CTRL_DP2X_DATA_LINK_BW 7:4 +#define NV0073_CTRL_DP2X_DATA_LINK_BW_1_62GBPS (0x00000001U) +#define NV0073_CTRL_DP2X_DATA_LINK_BW_2_16GBPS (0x00000002U) +#define NV0073_CTRL_DP2X_DATA_LINK_BW_2_43GBPS (0x00000003U) +#define NV0073_CTRL_DP2X_DATA_LINK_BW_2_70GBPS (0x00000004U) +#define NV0073_CTRL_DP2X_DATA_LINK_BW_3_24GBPS (0x00000005U) +#define NV0073_CTRL_DP2X_DATA_LINK_BW_4_32GBPS (0x00000006U) +#define NV0073_CTRL_DP2X_DATA_LINK_BW_5_40GBPS (0x00000007U) +#define NV0073_CTRL_DP2X_DATA_LINK_BW_6_75GBPS (0x00000008U) +#define NV0073_CTRL_DP2X_DATA_LINK_BW_8_10GBPS (0x00000009U) +#define NV0073_CTRL_DP2X_DATA_LINK_BW_UHBR10_0 (0x0000000AU) +#define NV0073_CTRL_DP2X_DATA_LINK_BW_UHBR13_5 (0x0000000BU) +#define NV0073_CTRL_DP2X_DATA_LINK_BW_UHBR20_0 (0x0000000CU) + + +// Flag for SET_RESET_LINK +#define NV0073_CTRL_DP2X_DATA_RESET_REASON 9:8 +#define NV0073_CTRL_DP2X_DATA_RESET_REASON_START_LT (0x00000000U) +#define NV0073_CTRL_DP2X_DATA_RESET_REASON_FALLBACK (0x00000001U) +#define NV0073_CTRL_DP2X_DATA_RESET_REASON_CHANNEL_CODING (0x00000002U) + +#define NV0073_CTRL_DP2X_ERR_CHANNEL_EQ 0:0 +#define NV0073_CTRL_DP2X_ERR_CHANNEL_EQ_DONE (0x00000000U) +#define NV0073_CTRL_DP2X_ERR_CHANNEL_EQ_FAILED (0x00000001U) +#define NV0073_CTRL_DP2X_ERR_CDS 1:1 +#define NV0073_CTRL_DP2X_ERR_CDS_DONE (0x00000000U) +#define NV0073_CTRL_DP2X_ERR_CDS_FAILED (0x00000001U) +#define NV0073_CTRL_DP2X_ERR_TIMEOUT 2:2 +#define NV0073_CTRL_DP2X_ERR_TIMEOUT_NO (0x00000000U) +#define NV0073_CTRL_DP2X_ERR_TIMEOUT_YES (0x00000001U) +#define NV0073_CTRL_DP2X_ERR_LT_FAILED 3:3 +#define NV0073_CTRL_DP2X_ERR_LT_FAILED_NO (0x00000000U) +#define NV0073_CTRL_DP2X_ERR_LT_FAILED_YES (0x00000001U) +#define NV0073_CTRL_DP2X_ERR_INVALID_PARAMETER 4:4 +#define NV0073_CTRL_DP2X_ERR_INVALID_PARAMETER_NOERR (0x00000000U) +#define NV0073_CTRL_DP2X_ERR_INVALID_PARAMETER_ERR (0x00000001U) +#define NV0073_CTRL_DP2X_ERR_SET_LANE_COUNT 5:5 +#define NV0073_CTRL_DP2X_ERR_SET_LANE_COUNT_NOERR (0x00000000U) +#define NV0073_CTRL_DP2X_ERR_SET_LANE_COUNT_ERR (0x00000001U) +#define NV0073_CTRL_DP2X_ERR_SET_LINK_BW 6:6 +#define NV0073_CTRL_DP2X_ERR_SET_LINK_BW_NOERR (0x00000000U) +#define NV0073_CTRL_DP2X_ERR_SET_LINK_BW_ERR (0x00000001U) +#define NV0073_CTRL_DP2X_ERR_ENABLE_FEC 7:7 +#define NV0073_CTRL_DP2X_ERR_ENABLE_FEC_NOERR (0x00000000U) +#define NV0073_CTRL_DP2X_ERR_ENABLE_FEC_ERR (0x00000001U) +#define NV0073_CTRL_DP2X_ERR_CONFIG_LTTPR 8:8 +#define NV0073_CTRL_DP2X_ERR_CONFIG_LTTPR_NOERR (0x00000000U) +#define NV0073_CTRL_DP2X_ERR_CONFIG_LTTPR_ERR (0x00000001U) +#define NV0073_CTRL_DP2X_ERR_PRE_LT 9:9 +#define NV0073_CTRL_DP2X_ERR_PRE_LT_NOERR (0x00000000U) +#define NV0073_CTRL_DP2X_ERR_PRE_LT_ERR (0x00000001U) +#define NV0073_CTRL_DP2X_ERR_POST_LT 10:10 +#define NV0073_CTRL_DP2X_ERR_POST_LT_NOERR (0x00000000U) +#define NV0073_CTRL_DP2X_ERR_POST_LT_ERR (0x00000001U) +#define NV0073_CTRL_DP2X_ERR_RESET_LINK 11:11 +#define NV0073_CTRL_DP2X_ERR_RESET_LINK_NOERR (0x00000000U) +#define NV0073_CTRL_DP2X_ERR_RESET_LINK_ERR (0x00000001U) +#define NV0073_CTRL_DP2X_ERR_LINK_STATUS 12:12 +#define NV0073_CTRL_DP2X_ERR_LINK_STATUS_CONNECTED (0x00000000U) +#define NV0073_CTRL_DP2X_ERR_LINK_STATUS_DISCONNECTED (0x00000001U) + +#define NV0073_CTRL_DP2X_POLLING_INFO_TRAINING_AUX_RD_INTERVAL 6:0 +#define NV0073_CTRL_DP2X_POLLING_INFO_TRAINING_AUX_RD_INTERVAL_UNIT 7:7 +#define NV0073_CTRL_DP2X_POLLING_INFO_TRAINING_AUX_RD_INTERVAL_UNIT_2MS (0x00000000U) +#define NV0073_CTRL_DP2X_POLLING_INFO_TRAINING_AUX_RD_INTERVAL_UNIT_1MS (0x00000001U) +#define NV0073_CTRL_DP2X_POLLING_INFO_RESULT 31:31 +#define NV0073_CTRL_DP2X_POLLING_INFO_RESULT_PENDING (0x00000001U) +#define NV0073_CTRL_DP2X_POLLING_INFO_RESULT_DONE (0x00000000U) + +/* + * NV0073_CTRL_DP2X_LANE_DATA_PARAMS + * + * This structure provides DP2.x lane characteristics. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must a dfp display. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * numLanes + * Indicates number of lanes for which the data is valid. + * For SET it's an input. For GET it's an output. + * + * data + * This parameter can be an input or output based on the usage. + * For SET it's an input. For GET it's an output. + * + * Here are the current defined fields: + * NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL + * Possible Values: + * NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_0 + * ... + * NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_15 + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_DP2X_LANE_DATA_BUFFER_SIZE (0x20U) /* finn: Evaluated from "(4 * NV0073_CTRL_MAX_LANES)" */ + +typedef struct NV0073_CTRL_DP2X_LANE_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 numLanes; + NvU32 data[NV0073_CTRL_MAX_LANES]; +} NV0073_CTRL_DP2X_LANE_DATA_PARAMS; + +#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL 3:0 +#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_0 (0x00000000U) +#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_1 (0x00000001U) +#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_2 (0x00000002U) +#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_3 (0x00000003U) +#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_4 (0x00000004U) +#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_5 (0x00000005U) +#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_6 (0x00000006U) +#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_7 (0x00000007U) +#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_8 (0x00000008U) +#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_9 (0x00000009U) +#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_10 (0x0000000AU) +#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_11 (0x0000000BU) +#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_12 (0x0000000CU) +#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_13 (0x0000000DU) +#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_14 (0x0000000EU) +#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_15 (0x0000000FU) + +/* + * NV0073_CTRL_CMD_GET_DP2X_LANE_DATA + * + * This command is used to get the current TxFFE pre-defined level values for + * the current actively trained number of lanes. + * + * The command takes a NV0073_CTRL_DP2X_LANE_DATA_PARAMS structure as the + * argument with the appropriate subDeviceInstance and displayId filled. + * The arguments of this structure and the format of TxFFE Levels are described above. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * NOTE: This control call is only for testing purposes and should not be used + * in normal DP operations. TxFFE level for each lane will be set during + * Link training in normal DP operations + * + */ + +#define NV0073_CTRL_CMD_DP2X_GET_LANE_DATA (0x731384U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP2X_GET_LANE_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP2X_GET_LANE_DATA_PARAMS_MESSAGE_ID (0x84U) + +typedef NV0073_CTRL_DP2X_LANE_DATA_PARAMS NV0073_CTRL_DP2X_GET_LANE_DATA_PARAMS; + +/* + * NV0073_CTRL_CMD_SET_DP2X_LANE_DATA + * + * This command is used to set the TxFFE pre-defined level for the specified number of lanes. + * + * The command takes a NV0073_CTRL_DP2X_LANE_DATA_PARAMS structure as the + * argument with the appropriate subDeviceInstance, displayId, number of + * lanes, TxFFE levels for each lanes filled in. + * The arguments of this structure and the format of TxFFE Levels are described above. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * NOTE: This control call is only for testing purposes and should not be used + * in normal DP operations. TxFFE level for each lane will be set during + * Link training in normal DP operations + * + */ + +#define NV0073_CTRL_CMD_DP2X_SET_LANE_DATA (0x731385U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP2X_SET_LANE_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP2X_SET_LANE_DATA_PARAMS_MESSAGE_ID (0x85U) + +typedef NV0073_CTRL_DP2X_LANE_DATA_PARAMS NV0073_CTRL_DP2X_SET_LANE_DATA_PARAMS; + + + +/* + * NV0073_CTRL_CMD_DP_AUXCH_VBL_CTRL + * + * This command is used to query VBL capability and status as well as + * control enable/disable of VBL feature of eDP LCD panels. + * + * subDeviceInstance [in] + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId [in] + * This parameter specifies the ID of the DP display which owns + * the Main Link to be adjusted. The display ID must a DP display + * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * cmd [in] + * This parameter is an input to this command. The cmd parameter tells + * whether we have to get the value of a specific field or set the + * value in case of a writeable field. + * control [in] + * This parameter is input by the user. It is used by the user to decide the control + * value to be written to the VBL control field. The command to write is + * the NV0073_CTRL_CMD_DP_AUXCH_VBL_CTL_SET command. + * bVblControlCapable [out] + * This parameter reflects the VBL control capability of the Sink which can be + * fetched by using the NV0073_CTRL_CMD_DP_AUXCH_VBL_CTL_CAPABLE_QUERY command. + * bVblStatus [out] + * This parameter reflects the Sink VBL status which can be + * fetched by using the NV0073_CTRL_CMD_DP_AUXCH_VBL_STATUS_QUERY command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_DP_AUXCH_VBL_CTRL (0x731386U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_AUXCH_VBL_CTRL_PARAMS_MESSAGE_ID" */ + +/* valid commands */ +#define NV0073_CTRL_CMD_DP_AUXCH_QUERY_VBL_CTL_CAPABLE 0x00000000 +#define NV0073_CTRL_CMD_DP_AUXCH_QUERY_VBL_STATUS 0x00000001 +#define NV0073_CTRL_CMD_DP_AUXCH_SET_VBL_CTL 0x00000002 + +/* valid state values */ +#define NV0073_CTRL_CMD_DP_AUXCH_SET_VBL_CTL_DISABLE 0x00000001 +#define NV0073_CTRL_CMD_DP_AUXCH_SET_VBL_CTL_AUTONOMOUS 0x00000000 + +#define NV0073_CTRL_CMD_DP_AUXCH_VBL_CTRL_PARAMS_MESSAGE_ID (0x86U) + +typedef struct NV0073_CTRL_CMD_DP_AUXCH_VBL_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU8 cmd; + NvU8 control; + NvBool bVblControlCapable; + NvBool bVblStatus; +} NV0073_CTRL_CMD_DP_AUXCH_VBL_CTRL_PARAMS; + +/* + * NV0073_CTRL_DP_LEVEL_INFO_TABLE_ENTRY + * + * This structure specifies the Pre-emphasis/Drive Current/preshoot/TxPu + * information for a DP device. These are the the current values that RM is + * using to map the levels for Pre-emphasis and Drive Current for Link Training. + * preEmphasis + * This field specifies the preemphasis values. + * driveCurrent + * This field specifies the driveCurrent values. + * preshoot + * This field specifies the preshoot values. + * TxPu + * This field specifies the pull-up current source drive values. + */ +#define NV0073_CTRL_DP2X_MAX_TXFFE_LEVELS 16 +typedef struct NV0073_CTRL_DP_LEVEL_INFO_TABLE_ENTRY { + NvU32 preEmphasis; + NvU32 driveCurrent; + NvU32 preShoot; + NvU32 txPu; +} NV0073_CTRL_DP_LEVEL_INFO_TABLE_ENTRY; + +/* + * NV0073_CTRL_DP_SET_LEVEL_INFO_TABLE_DATA + * + * This command is used to override the Pre-emphasis/Drive Current/preshoot/TxPu + * data table in RM. This data is dependent on the target link rate. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the digital display for which the + * data should be returned. The display ID must a digital display. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * linkRate + * The target link rate that the lane drive parameters will be used with, + * using 10M convention. Refer to NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW + * constants. + * This control call only supports DP1.x link rates. For DP2.X UHBR link rates, + * use NV0073_CTRL_DP2X_SET_LEVEL_INFO_TABLE_DATA + * dpData + * This parameter is of type NV0073_CTRL_DP_LEVEL_INFO_TABLE_DATA + * and specifies the Pre-emphasis/Drive Current/Preshoot/TxPu information + * for a DP device. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_DP_SET_LEVEL_INFO_TABLE_DATA_PARAMS_MESSAGE_ID (0x87U) + +typedef struct NV0073_CTRL_DP_SET_LEVEL_INFO_TABLE_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 padlinkIndex; + NvU32 linkRate; + NV0073_CTRL_DP_LEVEL_INFO_TABLE_ENTRY dpData[NV0073_CTRL_MAX_DRIVECURRENT_LEVELS][NV0073_CTRL_MAX_PREEMPHASIS_LEVELS]; +} NV0073_CTRL_DP_SET_LEVEL_INFO_TABLE_DATA_PARAMS; + +#define NV0073_CTRL_CMD_DP_SET_LEVEL_INFO_TABLE_DATA (0x731387U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_LEVEL_INFO_TABLE_DATA_PARAMS_MESSAGE_ID" */ + +/* + * NV0073_CTRL_DP_GET_LEVEL_INFO_TABLE_DATA + * + * This command is used to fetch the Pre-emphasis/Drive Current/preshoot/TxPu + * data table in RM. This data is dependent on the target link rate. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the digital display for which the + * data should be returned. The display ID must a digital display. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * linkRate + * The target link rate that the lane drive parameters will be used with, + * using 10M convention. Refer to NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW + * constants. + * This control call only supports DP1.x link rates. For DP2.X UHBR link rates, + * use NV0073_CTRL_DP2X_GET_LEVEL_INFO_TABLE_DATA + * dpData + * This parameter is of type NV0073_CTRL_DP_LEVEL_INFO_TABLE_DATA + * and specifies the Pre-emphasis/Drive Current/Preshoot/TxPu information + * for a DP device. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_DP_GET_LEVEL_INFO_TABLE_DATA_PARAMS_MESSAGE_ID (0x88U) + +typedef struct NV0073_CTRL_DP_GET_LEVEL_INFO_TABLE_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 padlinkIndex; + NvU32 linkRate; + NV0073_CTRL_DP_LEVEL_INFO_TABLE_ENTRY dpData[NV0073_CTRL_MAX_DRIVECURRENT_LEVELS][NV0073_CTRL_MAX_PREEMPHASIS_LEVELS]; +} NV0073_CTRL_DP_GET_LEVEL_INFO_TABLE_DATA_PARAMS; + +#define NV0073_CTRL_CMD_DP_GET_LEVEL_INFO_TABLE_DATA (0x731388U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_LEVEL_INFO_TABLE_DATA_PARAMS_MESSAGE_ID" */ + +/* + * NV0073_CTRL_DP2X_SET_LEVEL_INFO_TABLE_DATA + * + * This command is used to override the Pre-emphasis/Drive Current/preshoot/TxPu + * data table in RM. This data is dependent on the target link rate. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the digital display for which the + * data should be returned. The display ID must a digital display. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * linkRate + * The target link rate that the lane drive parameters will be used with, + * using 10M convention. Refer to NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW + * constants. + * This control call only supports UHBR link rates. For DP1.x legacy link rates, + * use NV0073_CTRL_DP_SET_LEVEL_INFO_TABLE_DATA + * dpData + * This parameter is of type NV0073_CTRL_DP_LEVEL_INFO_TABLE_DATA + * and specifies the Pre-emphasis/Drive Current/Preshoot/TxPu information + * for a DP device. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_DP2X_SET_LEVEL_INFO_TABLE_DATA_PARAMS_MESSAGE_ID (0x89U) + +typedef struct NV0073_CTRL_DP2X_SET_LEVEL_INFO_TABLE_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 padlinkIndex; + NvU32 linkRate; + NV0073_CTRL_DP_LEVEL_INFO_TABLE_ENTRY dpData[NV0073_CTRL_DP2X_MAX_TXFFE_LEVELS]; +} NV0073_CTRL_DP2X_SET_LEVEL_INFO_TABLE_DATA_PARAMS; + +#define NV0073_CTRL_CMD_DP2X_SET_LEVEL_INFO_TABLE_DATA (0x731389U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP2X_SET_LEVEL_INFO_TABLE_DATA_PARAMS_MESSAGE_ID" */ + +/* + * NV0073_CTRL_DP2X_GET_LEVEL_INFO_TABLE_DATA + * + * This command is used to fetch the Pre-emphasis/Drive Current/preshoot/TxPu + * data table in RM. This data is dependent on the target link rate. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the digital display for which the + * data should be returned. The display ID must a digital display. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * linkRate + * The target link rate that the lane drive parameters will be used with, + * using 10M convention. Refer to NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW + * constants. + * This control call only supports UHBR link rates. For DP1.x legacy link rates, + * use NV0073_CTRL_DP_SET_LEVEL_INFO_TABLE_DATA + * dpData + * This parameter is of type NV0073_CTRL_DP_LEVEL_INFO_TABLE_DATA + * and specifies the Pre-emphasis/Drive Current/Preshoot/TxPu information + * for a DP device. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_DP2X_GET_LEVEL_INFO_TABLE_DATA_PARAMS_MESSAGE_ID (0x8AU) + +typedef struct NV0073_CTRL_DP2X_GET_LEVEL_INFO_TABLE_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 padlinkIndex; + NvU32 linkRate; + NV0073_CTRL_DP_LEVEL_INFO_TABLE_ENTRY dpData[NV0073_CTRL_DP2X_MAX_TXFFE_LEVELS]; +} NV0073_CTRL_DP2X_GET_LEVEL_INFO_TABLE_DATA_PARAMS; + +#define NV0073_CTRL_CMD_DP2X_GET_LEVEL_INFO_TABLE_DATA (0x73138aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP2X_GET_LEVEL_INFO_TABLE_DATA_PARAMS_MESSAGE_ID" */ + +/* + * NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR + * + * This command is used to apply the WAR based on EDID. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the digital display for which the + * data should be returned. The display ID must a digital display. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * bEnable + * This parameter will be used by RM to set the PDB property. Later that PDB + * property will be used for applying the WAR + * head + * This parameter specify for which head RM need to apply the WAR + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR_PARAMS_MESSAGE_ID (0x8BU) + +typedef struct NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 bEnable; + NvU32 head; +} NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR_PARAMS; + +#define NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR (0x73138bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR_PARAMS_MESSAGE_ID" */ + + + +/* + * NV0073_CTRL_CMD_CALCULATE_DP_IMP + * + * This command is used to query if a certain mode is supported by the DP IMP + * calculation. The command is required for NVD5 and later GPUs. + * + * subDeviceInstance [in] + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId [in] + * This parameter specifies the ID of the DP display which owns + * the Main Link to be adjusted. The display ID must a DP display + * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * linkConfig [in] + * This parameter specifies the link configuration used to validate the mode. + * linkRate10M: + * The link rate that will be used to validate the IMP. Using 10M convention. + * Refer to NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW constants. + * laneCount: + * The lane count that will be used to validate the IMP. + * bEnhancedFraming: + * Specify if enhanced framing is enabled. + * bDp2xChannelCoding: + * Specify if it's using 8b/10b or 128b/132b channel coding. + * bMultiStreamTopology: + * Specify if it's on Multiple stream topology (the device direct connected is a branch). + * bFECEnabled: + * Specify if FEC is enabled. + * modesetInfo [in] + * This parameter specifies the target display mode to be validated. + * rasterWidth: + * The total width of the mode. + * rasterHeight: + * The total height of the mode. + * surfaceWidth: + * The active width of the mode. + * surfaceHeight: + * The active height of the mode. + * rasterBlankStartX / rasterBlankEndX: + * The pixel location of horizontal blank starts and ends. + * depth: + * Color depth represents the number of bits used to indicate the color of a single pixel. + * The value will be different when DSC is enabled. + * twoChannelAudioHz/eightChannelAudioHz: + * The audio sample rate for different channels used. + * pixelFrequencyKHz: + * The pixel clock used by the mode. + * colorFormat: + * RGB/YCbCr444/YCbCr422/YCbCr420. + * bDSCEnabled: + * Specify if DSC is enabled. + * watermark [out] + * This parameter reflects the results of the calculation/verification. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_CALCULATE_DP_IMP (0x73138cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS_MESSAGE_ID" */ + +typedef struct NV0073_CTRL_DP_IMP_LINK_CONFIGURATION { + NvU32 linkRate10M; + NvU32 laneCount; + NvBool bEnhancedFraming; + NvBool bDp2xChannelCoding; + NvBool bMultiStreamTopology; + NvBool bFECEnabled; + NvBool bDisableEffBppSST8b10b; +} NV0073_CTRL_DP_IMP_LINK_CONFIGURATION; + +typedef struct NV0073_CTRL_DP_IMP_DSC_PARAMETERS { + NvU32 sliceCount; + NvU32 sliceWidth; + NvU32 sliceHeight; + NvU32 dscVersionMajor; + NvU32 dscVersionMinor; +} NV0073_CTRL_DP_IMP_DSC_PARAMETERS; + +typedef struct NV0073_CTRL_DP_IMP_MODESET_DATA { + NvU32 rasterWidth; + NvU32 rasterHeight; + NvU32 surfaceWidth; + NvU32 surfaceHeight; + NvU32 rasterBlankStartX; + NvU32 rasterBlankEndX; + NvU32 depth; + NvU32 twoChannelAudioHz; + NvU32 eightChannelAudioHz; + NvU32 pixelFrequencyKHz; + NvU32 bitsPerComponent; + NvU32 colorFormat; + NvBool bDSCEnabled; +} NV0073_CTRL_DP_IMP_MODESET_DATA; + +typedef struct NV0073_CTRL_DP_IMP_WATERMARK { + NvU32 waterMark; + NvU32 tuSize; + NvU32 minHBlank; + NvU32 hBlankSym; + NvU32 vBlankSym; + NvU32 effectiveBpp; + NvBool bIsModePossible; +} NV0073_CTRL_DP_IMP_WATERMARK; + +#define NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS_MESSAGE_ID (0x8CU) + +typedef struct NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 headIndex; + NV0073_CTRL_DP_IMP_LINK_CONFIGURATION linkConfig; + NV0073_CTRL_DP_IMP_MODESET_DATA modesetInfo; + NV0073_CTRL_DP_IMP_DSC_PARAMETERS dscInfo; + NV0073_CTRL_DP_IMP_WATERMARK watermark; +} NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_GET_CABLEID_INFO_FROM_MACRO + * + * This command is used to read cable ID Information from USB-C Cable for + * DP configuration purposes. + * + * subDeviceInstance [in] + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * displayId [in] + * This parameter specifies the ID of the DP display which owns + * the Main Link to be adjusted. The display ID must a DP display + * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_PARAMETER. + * + * cableIDInfo [out] + * This parameter reflects the result of the cable ID read from the cable + * + * Possible status values returned are: + * NV_ERR_INVALID_PARAMETER + * NV_ERR_NOT_SUPPORTED + * NV_OK + */ + +#define NV0073_CTRL_CMD_DP_GET_CABLEID_INFO_FROM_MACRO (0x73138dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_USBC_CABLEID_INFO_PARAMS_MESSAGE_ID" */ + +typedef enum NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE { + NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_UNKNOWN = 0, + NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_PASSIVE = 1, + NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_ACTIVE_RETIMER = 2, + NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_ACTIVE_LIN_REDRIVER = 3, + NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_OPTICAL = 4, +} NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE; + +typedef struct NV0073_CTRL_DP_USBC_CABLEID_INFO { + NvBool uhbr10_0_capable; + NvBool uhbr13_5_capable; + NvBool uhbr20_0_capable; + NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE type; + NvBool vconn_source; +} NV0073_CTRL_DP_USBC_CABLEID_INFO; + +#define NV0073_CTRL_DP_USBC_CABLEID_INFO_PARAMS_MESSAGE_ID (0x8DU) + +typedef struct NV0073_CTRL_DP_USBC_CABLEID_INFO_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NV0073_CTRL_DP_USBC_CABLEID_INFO cableIDInfo; +} NV0073_CTRL_DP_USBC_CABLEID_INFO_PARAMS; + +/* + * NV0073_CTRL_CMD_STUFF_DUMMY_SYMBOL_WAR + * + * Some sink devices require extra padding between SDPs. This is programmed for GB20x+ GPUs. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the control + * is being issued. The display ID must be valid. + * head + * This parameter specifies the head index for the operation. + * bEnable + * Boolean to enable or disable the WAR. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_STUFF_DUMMY_SYMBOL_WAR_PARAMS_MESSAGE_ID (0x8EU) + +typedef struct NV0073_CTRL_STUFF_DUMMY_SYMBOL_WAR_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 head; + NvBool bEnable; +} NV0073_CTRL_STUFF_DUMMY_SYMBOL_WAR_PARAMS; + +#define NV0073_CTRL_CMD_STUFF_DUMMY_SYMBOL_WAR (0x73138eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_STUFF_DUMMY_SYMBOL_WAR_PARAMS_MESSAGE_ID" */ + +/* + * NV0073_CTRL_CMD_DP_NOTIFY_LT + * + * This is called to inform RM when LT starts / ends. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the control + * is being issued. The display ID must be valid. + * bLTInProgress + * Boolean to indicate if link training is in progress. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_DP_NOTIFY_LT_PARAMS_MESSAGE_ID (0x8FU) + +typedef struct NV0073_CTRL_DP_NOTIFY_LT_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bLTInProgress; +} NV0073_CTRL_DP_NOTIFY_LT_PARAMS; + +#define NV0073_CTRL_CMD_DP_NOTIFY_LT (0x73138fU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_NOTIFY_LT_PARAMS_MESSAGE_ID" */ + +/* + * NV0073_CTRL_CMD_GET_USB_DPIN_ADAPTER_INFO + * + * Get USB4 DP_IN Adapter number from RM + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the control + * is being issued. The display ID must be valid. + * driverId + * This parameter uniquely identifies the host router in the system. + * dpInAdapterNumber + * DP_IN adapter number that belongs to the displayId + * topologyId + * Unique number to identify the USB4 router topology + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_DP_USB_TOPOLOGY_ID_LENGTH 5 + +typedef struct NV0073_CTRL_DP_USB4_INFO { + NvU8 driverId; + NvU8 dpInAdapterNumber; + NvU8 topologyId[NV0073_CTRL_DP_USB_TOPOLOGY_ID_LENGTH]; +} NV0073_CTRL_DP_USB4_INFO; + +#define NV0073_CTRL_CMD_GET_USB_DPIN_ADAPTER_INFO_PARAMS_MESSAGE_ID (0x90U) + +typedef struct NV0073_CTRL_CMD_GET_USB_DPIN_ADAPTER_INFO_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NV0073_CTRL_DP_USB4_INFO usb4Info; +} NV0073_CTRL_CMD_GET_USB_DPIN_ADAPTER_INFO_PARAMS; + +#define NV0073_CTRL_CMD_GET_USB_DPIN_ADAPTER_INFO (0x731390U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_GET_USB_DPIN_ADAPTER_INFO_PARAMS_MESSAGE_ID" */ + +/* _ctrl0073dp_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073dpu.h b/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073dpu.h new file mode 100644 index 0000000..04aeead --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073dpu.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073dpu.finn +// + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073event.h b/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073event.h new file mode 100644 index 0000000..b02eda5 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073event.h @@ -0,0 +1,112 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073event.finn +// + +#include "ctrl/ctrl0073/ctrl0073base.h" + +/* +* tilemask +* Tiles assocaited with calc tiemout head. +* frameActive +* New frame has started on this Head. +* histoReady +* Asserts when histogram data from all the "enabled" LTMs belonging to this head +* is ready. +* startFrameReady +* When histo_ready interrupt +* is received and HDMA is programmed and then RISCV asserts STARTFRAME_READY. +*/ +typedef struct NV0073_LTM_HEAD_STATUS_PARAMS { + NvU8 tileMask; + NvBool frameActive; + NvBool histoReady; + NvBool startFrameReady; +} NV0073_LTM_HEAD_STATUS_PARAMS; + +/* NV04_DISPLAY_COMMON event-related control commands and parameters */ + +/* + * NV0073_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * This command sets event notification state for the associated display + * object. This command requires that an instance of NV01_EVENT has been + * previously bound to the associated display object. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * hEvent + * This parameter specifies the handle of the NV01_EVENT instance + * to be bound to the given subDeviceInstance. + * event + * This parameter specifies the type of event to which the specified + * action is to be applied. This parameter must specify a valid + * NV0073_NOTIFIERS value (see cl0073.h for more details) and should + * not exceed one less NV0073_NOTIFIERS_MAXCOUNT. + * action + * This parameter specifies the desired event notification action. + * Valid notification actions include: + * NV0073_CTRL_SET_EVENT_NOTIFICATION_DISABLE + * This action disables event notification for the specified + * event for the associated subdevice object. + * NV0073_CTRL_SET_EVENT_NOTIFICATION_SINGLE + * This action enables single-shot event notification for the + * specified event for the associated subdevice object. + * NV0073_CTRL_SET_EVENT_NOTIFICATION_REPEAT + * This action enables repeated event notification for the specified + * event for the associated system controller object. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV0073_CTRL_CMD_EVENT_SET_NOTIFICATION (0x730301U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_EVENT_INTERFACE_ID << 8) | NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS { + NvU32 subDeviceInstance; + NvHandle hEvent; + NvU32 event; + NvU32 action; +} NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000U) +#define NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001U) +#define NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002U) + +/* _ctrl0073event_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073internal.h b/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073internal.h new file mode 100644 index 0000000..6ce5ad7 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073internal.h @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073internal.finn +// + +#include "ctrl/ctrl0073/ctrl0073base.h" +#include "ctrl/ctrl0073/ctrl0073system.h" +#include "ctrl/ctrl0073/ctrl0073dfp.h" + +#define NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE (0x730401U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_PARAMS_MESSAGE_ID (0x1U) + +typedef NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS NV0073_CTRL_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_PARAMS; + +#define NV0073_CTRL_CMD_INTERNAL_DFP_SWITCH_DISP_MUX (0x730460U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_INTERNAL_DFP_SWITCH_DISP_MUX_PARAMS_MESSAGE_ID (0x3U) + +typedef NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS NV0073_CTRL_CMD_INTERNAL_DFP_SWITCH_DISP_MUX_PARAMS; + +#define NV0073_CTRL_CMD_INTERNAL_DFP_GET_DISP_MUX_STATUS (0x730404U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_INTERNAL_DFP_GET_DISP_MUX_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_INTERNAL_DFP_GET_DISP_MUX_STATUS_PARAMS_MESSAGE_ID (0x4U) + +typedef NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS NV0073_CTRL_CMD_INTERNAL_DFP_GET_DISP_MUX_STATUS_PARAMS; + +/* ctrl0073internal_h */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073psr.h b/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073psr.h new file mode 100644 index 0000000..f971074 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073psr.h @@ -0,0 +1,70 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073psr.finn +// + +#include "ctrl/ctrl0073/ctrl0073base.h" + +/* NV04_DISPLAY_COMMON psr-display-specific control commands and parameters */ + +/* + * NV0073_CTRL_CMD_PSR_GET_SR_PANEL_INFO + * + * displayId + * Display ID on which this information is being requested. + * frameLockPin + * Returns the frame lock pin of the panel. + * i2cAddress + * Returns the i2c address on which the SR panel is attached. + * NOTE: applies only to LVDS panels, otherwise this field + * should be ignored. + * bSelfRefreshEnabled + * Returns whether SR is enabled in RM. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_PSR_GET_SR_PANEL_INFO (0x731602U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_PSR_INTERFACE_ID << 8) | NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS { + NvU32 displayId; + NvU32 frameLockPin; + NvU8 i2cAddress; + NvBool bSelfRefreshEnabled; +} NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS; + + + +/* _ctrl0073psr_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073specific.h b/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073specific.h new file mode 100644 index 0000000..12420b9 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073specific.h @@ -0,0 +1,3184 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073specific.finn +// + +#include "ctrl/ctrl0073/ctrl0073base.h" + +#include "ctrl/ctrlxxxx.h" +/* NV04_DISPLAY_COMMON display-specific control commands and parameters */ + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_TYPE + * + * This command can be used to determine the associated display type for + * the specified displayId. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the display + * type is to be returned. Only one display may be indicated in this + * parameter. + * displayType + * This parameter returns the display type associated with the specified + * displayId parameter. Valid displayType values are: + * NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_CRT + * NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_DFP + * NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_TV + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_TYPE (0x730240U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_TYPE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_GET_TYPE_PARAMS_MESSAGE_ID (0x40U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_TYPE_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 displayType; +} NV0073_CTRL_SPECIFIC_GET_TYPE_PARAMS; + +/* valid display types */ +#define NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_UNKNOWN (0x00000000U) +#define NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_CRT (0x00000001U) +#define NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_DFP (0x00000002U) +#define NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_TV (0x00000003U) + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_EDID_V2 + * + * This command can be used to request the EDID for the specified displayId. + * + * [in] subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the total + * number of subdevices within the parent device. This parameter should + * be set to zero for default behavior. + * [in] displayId + * This parameter specifies the display to read the EDID. The display ID + * must specify a display with a positive connect state as determined + * with the NV0073_CTRL_CMD_SYSTEM_GET_CONNECT_STATE command. Only one + * display may be indicated in this parameter. If a more than one + * display Id is used, the RM will return NV_ERR_INVALID_ARGUMENT. + * [out] bufferSize + * This parameter returns the number of bytes copied into edidBuffer after + * performing the requested EDID operations. + * [out] edidBuffer + * The array of EDIDs that RM will fill after the requested operations. If + * the size of the array is not large enough to hold the number of bytes to + * be copied, NV_ERR_INVALID_ARGUMENT will be returned. + * [in] flags + * This parameter defines the specific operations that will be performed + * in reading the EDID. + * Here are the current defined fields: + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_COPY_CACHE + * A client uses this field to indicate whether to return the cached + * copy of the EDID or to use DDC to read the EDID from the display. + * Possible values are: + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_COPY_CACHE_NO + * The RM will use DDC to grab the EDID. + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_COPY_CACHE_YES + * The RM will copy the last EDID found into the clients + * buffer. No DDC will be performed. + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_READ_MODE + * A client uses this field to indicate whether to read from + * the HW and return the EDID w/o any patching + * Possible values are: + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_READ_MODE_COOKED + * Use the _COPY_CACHE policy + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_READ_MODE_RAW + * Perform the read and return an unadulterated EDID. + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE + * A client uses this field to indicate whether to read EDID + * from SBIOS using ACPI sub function for display dynamic switching + * feature. This flag should only be set on internal display with + * dynamic switching feature enabled. + * Possible values are: + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE_ACPI + * RM reads the EDID from SBIOS and returns the raw EDID provided + * by SBIOS. + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE_DEFAULT + * EDID is read based on rest of the 'flags' that are passed to + * this function. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_EDID_V2 (0x730245U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_GET_EDID_MAX_EDID_BYTES 2048U + +#define NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS_MESSAGE_ID (0x45U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 bufferSize; + NvU32 flags; + NvU8 edidBuffer[NV0073_CTRL_SPECIFIC_GET_EDID_MAX_EDID_BYTES]; +} NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS; + +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_COPY_CACHE 0:0 +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_COPY_CACHE_NO 0x00000000U +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_COPY_CACHE_YES 0x00000001U + +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_READ_MODE 1:1 +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_READ_MODE_COOKED 0x00000000U +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_READ_MODE_RAW 0x00000001U + +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE 3:2 +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE_DEFAULT 0x00000000U +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE_ACPI 0x00000001U + +/* + * NV0073_CTRL_CMD_SPECIFIC_SET_EDID_V2 + * + * This command can be used to set or remove a complete EDID for the + * specified displayId. Once the EDID is set, any requests + * to read the EDID or use DDC detection will always use a cached copy of + * the EDID. That is, the EDID becomes static until disabled by calling + * this same function with edidBuffer. Note, that DDC based + * detection will always pass for any displayId that has set an EDID. Also, + * this path will not store any value across reboots. If an EDID needs to + * remain set after a reboot, RM clients must call this function again. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the total + * number of subdevices within the parent device. This parameter should + * be set to zero for default behavior. + * displayId + * This parameter specifies the display to store or the EDID. Only one + * display may be indicated in this parameter. If more than one displayId + * is used, the RM will return NV_ERR_INVALID_ARGUMENT. + * If the displayId does not use DDC and hence would not have an EDID, + * then the RM could also return NV_ERR_INVALID_ARGUMENT. + * bufferSize + * This parameter specifies the size of the EDID buffer pointed to by + * pEdidBuffer. If the EDID write contains more bytes than bufferSize, + * the RM will extend the bufferSize of the EDID inside the RM to match. + * Note a bufferSize of 0 would mean no bytes will be copied, but set the + * current cached EDID as static. + * edidBuffer + * This parameter specifies the EDID buffer that the RM will copy into + * the RM buffer. If the EDID buffer is empty, the RM will remove any + * previous set EDID and allow further detection and EDID reads to use DDC. + * The RM will not check to see if the EDID is valid here or not. + * The client should validate the EDID if needed before calling this function. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + */ + +#define NV0073_CTRL_CMD_SPECIFIC_SET_EDID_V2 (0x730246U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_EDID_V2_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_EDID_V2_PARAMS_MESSAGE_ID (0x46U) + +typedef struct NV0073_CTRL_SPECIFIC_SET_EDID_V2_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 bufferSize; + NvU8 edidBuffer[NV0073_CTRL_SPECIFIC_GET_EDID_MAX_EDID_BYTES]; +} NV0073_CTRL_SPECIFIC_SET_EDID_V2_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE + * + * This Control Cmd is for providing the Faking device(s) support from RM. + * This command serves as the entry point for all interaction of RM with + * user mode component of the any internal [test] tool. The Faking framework + * in RM will be activated only after the usermode app sends in a proper ENABLE + * cmd first. Any attempt to issue other cmds while the faking code has not + * been enabled will result in RM err _INVALID_DATA. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the total + * number of subdevices within the parent device. This parameter should + * be set to zero for default behavior. + * cmd + * This field will carry the command to be executed by the framework. + * This includes Enabling/Disabling the test framework and faking devices + * like CRT/DVI/TV. + * data + * This field is to carry the data required for executing the cmd. + * Except for Enable and Disable, the other faking device commands will + * require the device mask of the device to be faked/removed. + * tvType + * This field specifies a specific TV type while faking a TV. + * Possible values are: + * NV0073_FAKE_DEVICE_TV_NONE + * NV0073_FAKE_DEVICE_TV_SVIDEO + * NV0073_FAKE_DEVICE_TV_COMPOSITE + * NV0073_FAKE_DEVICE_TV_COMPONENT + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_DATA + * + */ + +#define NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE (0x730243U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE_PARAMS_MESSAGE_ID" */ + +/* valid fake device TV connector types */ +#define NV0073_FAKE_DEVICE_TV_NONE (0U) +#define NV0073_FAKE_DEVICE_TV_SVIDEO (1U) +#define NV0073_FAKE_DEVICE_TV_COMPOSITE (2U) +#define NV0073_FAKE_DEVICE_TV_COMPONENT (3U) + +#define NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE_PARAMS_MESSAGE_ID (0x43U) + +typedef struct NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE_PARAMS { + NvU32 subDeviceInstance; + NvU32 cmd; + NvU32 data; + NvU32 tvType; +} NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE_PARAMS; + +/* Faking Support commands */ +/* some random value to enable/disable test code */ +#define NV0073_FAKE_DEVICE_SUPPORT_ENABLE 0x11faU +#define NV0073_FAKE_DEVICE_SUPPORT_DISABLE 0x99ceU +#define NV0073_FAKE_DEVICE_SUPPORT_ATTACH_DEVICES 0x100U +#define NV0073_FAKE_DEVICE_SUPPORT_REMOVE_DEVICES 0x101U + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID + * + * This command returns the I2C portID for the specified display device. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the display for which information is to be + * returned. Only one display may be indicated in this parameter. + * If more than one displayId is used a failing status of + * NV_ERR_INVALID_ARGUMENT will be returned. + * commPortId + * This parameter returns the I2C communication port ID of the + * display device indicated by the displayId parameter. + * ddcPortId + * This parameter returns the I2C DDC port ID of the display device + * indicated by the displayId parameter. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID (0x730211U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 commPortId; + NvU32 ddcPortId; +} NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS; + +#define NV0073_CTRL_SPECIFIC_I2C_PORT_NONE (0x0U) + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_CONNECTOR_DATA + * + * This command can be used to get display connector data. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the display for which information is to be + * returned. Only one display may be indicated in this parameter. + * If more than one displayId is used a failing status of + * NV_ERR_INVALID_ARGUMENT will be returned. + * DDCPartners + * This parameter specifies an NV0073_DISPLAY_MASK value describing + * the set of displays that share the same DDC line as displayId. This + * parameter will always be returned even if we also return the + * NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_FLAGS_PRESENT_NO flag. + * flags + * This parameter specifies optional flags to be used while retrieving + * the connector data for a given displayId. + * Legal values for this parameter include: + * NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_FLAGS_PRESENT + * This flag describes whether the connector data is present + * inside the firmware. + * count + * This parameter returns the number of connectors associated with + * the displayId argument. This value indicates the number of +* valid entries returned in the data parameter. + * data + * This parameter returns an array of structures containing the connector + * data associated with each connector for the given displayId argument. + * The count field specifies how many entries in this array are returned. + * Each entry in the array contains the following members: + * index + * This value is the index associated with the given connector. If + * two displayIds share the same index, then they share the same + * connector. + * type + * This value defines the type of connector associated with the + * displayId argument. + * location + * This value provides a possible means to determine the relative + * location of the connector in association to other connectors. + * For desktop boards, a value of zero defines the south most + * connector (the connector closest to the bus slot into which + * the board is inserted). + * platform + * This value defines the type of system with which to associate the + * location of each connector. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + */ + +#define NV0073_CTRL_CMD_SPECIFIC_GET_CONNECTOR_DATA (0x730250U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS_MESSAGE_ID" */ + +/* maximum number of connectors */ +#define NV0073_CTRL_MAX_CONNECTORS 4U + +#define NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS_MESSAGE_ID (0x50U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 flags; + NvU32 DDCPartners; + NvU32 count; + struct { + NvU32 index; + NvU32 type; + NvU32 location; + } data[NV0073_CTRL_MAX_CONNECTORS]; + NvU32 platform; +} NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS; + +/* defines for the flags field */ +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_FLAGS_PRESENT 0:0 +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_FLAGS_PRESENT_NO 0x00000000U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_FLAGS_PRESENT_YES 0x00000001U + +/* defines for the data[].type field */ +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_VGA_15_PIN 0x00000000U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_TV_COMPOSITE 0x00000010U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_TV_SVIDEO 0x00000011U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_TV_HDTV_COMPONENT 0x00000013U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_TV_SCART 0x00000014U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_TV_COMPOSITE_SCART_OVER_EIAJ4120_BLUE 0x00000016U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_TV_HDTV_EIAJ4120 0x00000017U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_PC_POD_HDTV_YPRPB 0x00000018U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_PC_POD_SVIDEO 0x00000019U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_PC_POD_COMPOSITE 0x0000001AU +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DVI_I_TV_SVIDEO 0x00000020U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DVI_I_TV_COMPOSITE 0x00000021U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DVI_I 0x00000030U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DVI_D 0x00000031U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_ADC 0x00000032U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_LFH_DVI_I_1 0x00000038U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_LFH_DVI_I_2 0x00000039U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_SPWG 0x00000040U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_OEM 0x00000041U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DP_EXT 0x00000046U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DP_INT 0x00000047U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DP_MINI_EXT 0x00000048U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DP_SERIALIZER 0x00000049U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_HDMI_A 0x00000061U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_HDMI_C_MINI 0x00000063U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_LFH_DP_1 0x00000064U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_LFH_DP_2 0x00000065U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_VIRTUAL_WFD 0x00000070U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_USB_C 0x00000071U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DSI 0x00000072U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_STEREO_3PIN_DIN 0x00000073U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_USB_C_UHBR 0x00000074U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_UNKNOWN 0xFFFFFFFFU + +/* defines for the platform field */ +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_DEFAULT_ADD_IN_CARD 0x00000000U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_TWO_PLATE_ADD_IN_CARD 0x00000001U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_CONFIGURABLE 0x00000002U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_DESKTOP_FULL_DP 0x00000007U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_MOBILE_ADD_IN_CARD 0x00000008U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_MXM 0x00000009U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_MOBILE_BACK 0x00000010U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_MOBILE_BACK_LEFT 0x00000011U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_MOBILE_BACK_DOCK 0x00000018U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_CRUSH_DEFAULT 0x00000020U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_UNKNOWN 0xFFFFFFFFU + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_HDCP_REPEATER_INFO + * + * This command is used to get HDCP repeater information. From the + * repeater device this call returns KsvList,BStatus and VPrime. If the + * device is implemented internally, the client call supply a Cksv and Cn + * And in turn following parameters are returned: MPrime, Dksv which are used + * for upstream authentication. In addition to this the flag bAuthRequired + * shall be set to indicate that upstream authentication is required along with + * comparing the KsvList with SRM. On the other hand, if the device is an + * external implementation MPrime and Dksv values shall be ignored and the flag + * bAuthRequired will not be set indicating upstream authentication not + * required and just the comparison of KsvList with upstream SRM is required. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter indicates the digital display device's + * displayId. This comes as input to this command. + * bRepeaterPending + * The repeater pending flag as the output to this command. + * The flag returned indicating whether repeater is ready or not + * TRUE if repeater is not ready and FALSE otherwise. + * Cn + * This parameter is the input value Cn a 64 bit random number + * to be provided to this command. Cn value is Upstream protocol's + * exchange random number.This value must be written by software + * before the KSV is written if the transmitter device follows the HDCP + * upstream protocol. If the transmitter supports a proprietary method of + * authenticating the repeater device, Cn can be ignored. + * Cksv + * This parameter is the input value Cksv (a unique identifier) of 40 bit + * size to be provided to this command. This input value shall contain 20 + * ones and 20 zeros in accordance with the HDCP specification. This value + * must be written by software before the KSV is written if the transmitter + * device follows the HDCP upstream protocol. If the transmitter supports + * a proprietary method of authenticating the repeater device, Cksv can be + * ignored. + * actualKsvSize + * The actual KSV list size(in bytes) returned back as output while reading + * KSV list. + * ksvList + * In case downstream device is repeater then this will give the list of + * KSV's of all downstream devices attached to the repeater. It differs + * from actualKsvSize because this allocates maximum allowed size. + * If downstream device is receiver then this array will contain all zeros. + * BStatus + * The BSTATUS value as output by this command.This value's bit fields + * contains information returned by repeater device such as total number of + * downstream devices attached to the repeater excluding HDCP repeater, + * value for the depth indicating number of connection levels through + * connection topology, this value also gives information about maximum + * cascaded and devices exceeded (127). + * VPrime + * The VPRIME value returned as output by this command from the repeater + * device. This value should be used to compare the verification value + * during the HDCP upstream protocol using SHA1 in accordance with the + * upstream protocol. This value can be ignored if bAuthRequired is not + * set indicating the verification is done by the transmitter device. + * bAuthrequired + * The authentication flag as the output to this command. + * The Flag returned indicating whether authentication is required or not + * TRUE if authentication required and FALSE otherwise. + * MPrime + * The MPRIME value returned as output by this command. + * MPrime shall be decrypted by the client and used in the SHA-1 + * computation of V during upstream authentication. This value can be + * ignored if bAuthRequired is not set indicating the verification is + * done by the transmitter device. + * Dksv + * This parameter is the output value DKSV of 40 bit size. + * As per the HDCP specification this value should contain 20 ones and + * 20 zeros.This value can be ignored if bAuthRequired is not set + * indicating the verification is done by the transmitter device. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_REP_KSV_SIZE (5U) +#define NV0073_CTRL_DKSV_SIZE (5U) +#define NV0073_CTRL_MPRIME_SIZE (0x2U) /* finn: Evaluated from "(8 / 4)" */ +#define NV0073_CTRL_CN_SIZE (0x2U) /* finn: Evaluated from "(8 / 4)" */ +#define NV0073_CTRL_CKSV_SIZE (5U) +#define NV0073_CTRL_VPRIME_SIZE (0x5U) /* finn: Evaluated from "(20 / 4)" */ + +#define NV0073_CTRL_MAX_HDCP_REPEATER_COUNT (0x27bU) /* finn: Evaluated from "(NV0073_CTRL_REP_KSV_SIZE * 127)" */ + +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDCP_REPEATER_INFO (0x730260U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_HDCP_REPEATER_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_GET_HDCP_REPEATER_INFO_PARAMS_MESSAGE_ID (0x60U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_HDCP_REPEATER_INFO_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU8 bRepeaterPending; + NvU32 Cn[NV0073_CTRL_CN_SIZE]; + NvU8 Cksv[NV0073_CTRL_CKSV_SIZE]; + NvU32 actualKsvSize; + NvU8 ksvList[NV0073_CTRL_MAX_HDCP_REPEATER_COUNT]; + NvU16 BStatus; + NvU32 VPrime[NV0073_CTRL_VPRIME_SIZE]; + NvU8 bAuthrequired; + NvU32 MPrime[NV0073_CTRL_MPRIME_SIZE]; + NvU8 Dksv[NV0073_CTRL_DKSV_SIZE]; +} NV0073_CTRL_SPECIFIC_GET_HDCP_REPEATER_INFO_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_ENABLE + * + * This command is used to signal the resource manager that the upcoming mode + * shall be hdmi vs dvi. This is required since the resource manager + * does not read the display edid. The resource manager shall enable hdmi + * components such as turning on the audio engine for instance. This should + * be called prior to every modeset in which the displayId is capable of hdmi. + * displayId + * This parameter specifies the displayId of HDMI resource to configure. + * This comes as input to this command. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which operation should be directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * enable + * This field specifies the legal values: + * NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_TRUE + * NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_FALSE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_ENABLE (0x730273U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS_MESSAGE_ID (0x73U) + +typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS { + NvU8 subDeviceInstance; + NvU32 displayId; + NvU8 enable; +} NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS; + +#define NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_FALSE (0x00000000U) +#define NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_TRUE (0x00000001U) + +/* + * NV0073_CTRL_CMD_SPECIFIC_CTRL_HDMI + * + * This command can be used to enable HDMI communication on the associated GPU. + * This should be called prior to every modeset in which the displayId is capable of HDMI. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which operation should be directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * displayId + * This parameter specifies the displayId of HDMI resource to configure. + * This comes as input to this command. + * enable + * This field specifies the legal values: + * NV0073_CTRL_SPECIFIC_CTRL_HDMI_DISABLE + * NV0073_CTRL_SPECIFIC_CTRL_HDMI_ENABLE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_CTRL_HDMI (0x730274U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_CTRL_HDMI_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_CTRL_HDMI_PARAMS_MESSAGE_ID (0x74U) + +typedef struct NV0073_CTRL_SPECIFIC_CTRL_HDMI_PARAMS { + NvU8 subDeviceInstance; + NvU32 displayId; + NvBool bEnable; +} NV0073_CTRL_SPECIFIC_CTRL_HDMI_PARAMS; + +#define NV0073_CTRL_SPECIFIC_CTRL_HDMI_DISABLE (0x00000000U) +#define NV0073_CTRL_SPECIFIC_CTRL_HDMI_ENABLE (0x00000001U) + +/* + * NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM + * + * This command is used to signal the resource manager that the audio stream + * is to be mute off or on. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which operation should be directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * displayId + * This parameter specifies the displayId of HDMI resource to configure. + * This comes as input to this command. + * mute + * This field specifies the legal values: + * NV0073_CTRL_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_TRUE + * NV0073_CTRL_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_FALSE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM (0x730275U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID (0x75U) + +typedef struct NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS { + NvU8 subDeviceInstance; + NvU32 displayId; + NvU8 mute; +} NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS; + +#define NV0073_CTRL_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_FALSE (0x00000000U) +#define NV0073_CTRL_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_TRUE (0x00000001U) + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_HDCP_STATE + * + * This command is used to obtain that state of hdcp for the specified attach + * point (that being the displayId). + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the display for which information is to be + * returned. Only one display may be indicated in this parameter. + * If more than one displayId is used a failing status of + * NV_ERR_INVALID_ARGUMENT will be returned. + * flags + * This parameter specifies the state of the attach point resource. + * Here are the current defined fields: + * NV0073_CTRL_SPECIFIC_HDCP_STATE_ENCRYPTING + * This comes as an output to this command. The attach point + * is currently encrypting hdcp content over the attach point + * link. This state of this field is determined by + * NV0073_CTRL_SPECIFIC_HDCP_STATE_ENCRYPTING_CACHED. The + * default is to return cached hdcp state. + * NV0073_CTRL_SPECIFIC_HDCP_STATE_ENCRYPTING_CACHED + * This comes as an input to this command. If set to 1, the return + * value in NV0073_CTRL_SPECIFIC_HDCP_STATE_ENCRYPTING is based + * on the Status Word. If the uncached hdcp state fails, + * such as the case for external hdcp designs that do not support + * Upstream Status register, then if the flag + * NV0073_CTRL_SPECIFIC_HDCP_STATE_ENCRYPTING_CACHED is set, RM + * will unclear it and return the cached value instead. + * NV0073_CTRL_SPECIFIC_HDCP_STATE_AP_CAPABLE + * This comes as an output to this command. + * This bit indicates that the attach point resource is capable + * of hdcp encryption. + * NV0073_CTRL_SPECIFIC_HDCP_STATE_AP_DUAL_LINK_CAPABLE + * This comes as an output to this command. + * This bit indicates that the attach point resource is capable + * of hdcp encryption in a dual-link configuration. + * NV0073_CTRL_SPECIFIC_HDCP_STATE_AP_DISALLOWED + * This bit indicates that the attach point resource should not + * have HDCP available even if capable. + * NV0073_CTRL_SPECIFIC_HDCP_STATE_RECEIVER_CAPABLE + * This comes as an output to this command. + * This bit indicates that the receiver attached to this attach point + * resource is capable of hdcp encryption. + * NV0073_CTRL_SPECIFIC_HDCP_STATE_REPEATER_CAPABLE + * This comes as an output to this command. + * This bit indicates that the receiver attached to this attach point + * resource is capable of hdcp repeater operation. + * NV0073_CTRL_SPECIFIC_HDCP_STATE_FP_INTERNAL + * This comes as output to this command. + * This bit indicates that the associated display is an HDCP-capable + * internal panel. + * NV0073_CTRL_SPECIFIC_HDCP_STATE_HDCP22_RECEIVER_CAPABLE + * This comes as output to this command. + * This bit indicates that the receiver attached to this attach point + * resource is capable of hdcp22 encryption. + * NV0073_CTRL_SPECIFIC_HDCP_STATE_HDCP22_REPEATER_CAPABLE + * This comes as output to this command. + * This bit indicates that the receiver attached to this attach point + * resource is capable of hdcp22 repeater operation. + * NV0073_CTRL_SPECIFIC_HDCP_STATE_HDCP22_ENCRYPTING + * This comes as an output to this command. The attach point + * is currently encrypting hdcp22 content over the attach point + * link. This state of this field is determined by + * NV0073_CTRL_SPECIFIC_HDCP_STATE_ENCRYPTING_CACHED, return hdcp22 uncached + * status by default. + * NV0073_CTRL_SPECIFIC_HDCP_STATE_HDCP22_TYPE1 + * This comes as an output to this command. The attach point + * is currently encrypting hdcp22 content with stream Type 1 over the + * link. This state of this field is determined by + * NV0073_CTRL_SPECIFIC_HDCP_STATE_ENCRYPTING_CACHED, return hdcp22 uncached + * status of stream type by default. + * NV0073_CTRL_SPECIFIC_HDCP_STATE_AUTHENTICATED + * This comes an output to this command. + * This bit indicates if the receiver attached to this attach point + * completes authenticaion with source or not. To non DP-MST receiver, the state + * should be identical to NV0073_CTRL_SPECIFIC_HDCP_STATE_HDCP22_ENCRYPTING, while + * DP MST needs to assign ECF after authenticated. + * NV0073_CTRL_SPECIFIC_HDCP_STATE_AP_HDCP22_CAPABLE + * This comes as an output to this command. + * This bit indicates that the attach point resource is capable + * of hdcp2.2 encryption. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDCP_STATE (0x730280U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_HDCP_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_GET_HDCP_STATE_PARAMS_MESSAGE_ID (0x80U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_HDCP_STATE_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 flags; +} NV0073_CTRL_SPECIFIC_GET_HDCP_STATE_PARAMS; + +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_ENCRYPTING 0:0 +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_ENCRYPTING_NO (0x00000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_ENCRYPTING_YES (0x00000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_ENCRYPTING_CACHED 1:1 +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_ENCRYPTING_CACHED_TRUE (0x00000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_ENCRYPTING_CACHED_FALSE (0x00000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_HDCP22_ENCRYPTION_INPROGRESS 2:2 +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_HDCP22_ENCRYPTION_INPROGRESS_YES (0x00000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_HDCP22_ENCRYPTION_INPROGRESS_NO (0x00000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_AP_CAPABLE 4:4 +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_AP_CAPABLE_NO (0x00000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_AP_CAPABLE_YES (0x00000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_AP_DUAL_LINK_CAPABLE 5:5 +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_AP_DUAL_LINK_CAPABLE_NO (0x00000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_AP_DUAL_LINK_CAPABLE_YES (0x00000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_AP_DISALLOWED 6:6 +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_AP_DISALLOWED_NO (0x00000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_AP_DISALLOWED_YES (0x00000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_RECEIVER_CAPABLE 8:8 +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_RECEIVER_CAPABLE_NO (0x00000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_RECEIVER_CAPABLE_YES (0x00000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_REPEATER_CAPABLE 9:9 +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_REPEATER_CAPABLE_NO (0x00000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_REPEATER_CAPABLE_YES (0x00000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_FP_INTERNAL 10:10 +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_FP_INTERNAL_FALSE (0x00000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_FP_INTERNAL_TRUE (0x00000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_HDCP22_RECEIVER_CAPABLE 11:11 +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_HDCP22_RECEIVER_CAPABLE_NO (0x00000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_HDCP22_RECEIVER_CAPABLE_YES (0x00000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_HDCP22_REPEATER_CAPABLE 12:12 +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_HDCP22_REPEATER_CAPABLE_NO (0x00000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_HDCP22_REPEATER_CAPABLE_YES (0x00000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_HDCP22_ENCRYPTING 13:13 +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_HDCP22_ENCRYPTING_NO (0x00000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_HDCP22_ENCRYPTING_YES (0x00000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_HDCP22_TYPE1 14:14 +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_HDCP22_TYPE1_NO (0x00000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_HDCP22_TYPE1_YES (0x00000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_AUTHENTICATED 15:15 +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_AUTHENTICATED_NO (0x00000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_AUTHENTICATED_YES (0x00000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_AP_HDCP22_CAPABLE 16:16 +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_AP_HDCP22_CAPABLE_NO (0x00000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_STATE_AP_HDCP22_CAPABLE_YES (0x00000001U) + +/* + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_INFO + * + * This structure describes stStatus information. + * + * displayId + * This parameter returns the displayId associated with the + * attach point index. + * S + * Each element contains the attach-point S. This value's bit + * field contains information pertaining to STATUS of each attach point. + * The stStatus parameter is broken down as follows: + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_S_ENCRYPTING + * This field specifies that the attach-point is transmitting and + * has output encryption enabled. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_S_REPEATER + * This field specifies that the attach-point is transmitting to a + * repeater device. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_S_USER_ACCESSIBLE + * This field specifies that the attach-point is transmitting on a + * user-accessible external digital port. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_S_EXTERNALLY_UNPROTECTED + * This field specifies that the attach-point is transmitting + * externally and is unprotected. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_S_ATTACH_PORT_INDEX + * This field specifies the port/attach-point index. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_NUM_PORTS + * This field specifies the number of connectable attach-ports. + * The default is 8. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_S_INTERNAL_PANEL + * This field specifies a compliant internal/non-user accessible + * port panel without hdcp encryption. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_S_WIDE_SCOPE + * This field specifies _CS is not enough to determine the presence + * of non-compliant outputs (this field is always 1). + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_S_CS_CAPABLE + * This field specifies that connection-state is supported. + * This field is always 1. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_S_READZ_CAPABLE + * This field specifies that readZ is supported. + * This field is always 0. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_S_DUAL_LINK_EVEN + * This field specifies the even half of a dual-link (0x74). + * This field *NOT* yet supported. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_S_DUAL_LINK_ODD + * This field specifies the odd half of a dual-link (0x76) + * This field *NOT* yet supported. + */ +typedef struct NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_INFO { + NvU32 displayId; + NV_DECLARE_ALIGNED(NvU64 S, 8); +} NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_INFO; + +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_S_ENCRYPTING 0:0 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_S_REPEATER 1:1 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_S_USER_ACCESSIBLE 2:2 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_S_EXTERNALLY_UNPROTECTED 3:3 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_S_ATTACH_PORT_INDEX 7:4 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_S_NUM_PORTS 11:8 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_S_INTERNAL_PANEL 12:12 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_S_WIDE_SCOPE 13:13 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_S_CS_CAPABLE 14:14 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_S_READZ_CAPABLE 15:15 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_S_RESERVED0 39:16 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_S_DUAL_LINK_EVEN 40:40 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_S_DUAL_LINK_ODD 41:41 + + +/* + * NV0073_CTRL_CMD_SPECIFIC_HDCP_CTRL + * + * This command is used to do HDCP controls on the specified attach + * point (that being the displayId). + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the display for which information is to be + * returned. Only one display may be indicated in this parameter. + * If more than one displayId is used a failing status of + * NV_ERR_INVALID_ARGUMENT will be returned. + * err + * This parameter specifies provides info regarding the outcome + * of this calling control call. If zero, no errors were found. + * Otherwise, this parameter will specify the error detected. + * The valid parameter is broken down as follows: + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_ERR_UNSUCCESSFUL + * If set to _YES, this indicates at least one of the calling + * functions failed. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_ERR_PENDING + * If set to _YES, this indicates at renogiation is not complete and + * that the client should check status later. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_ERR_BAD_TOKEN_TYPE + * If set to _YES, the session ID or KSV was rejected. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_ERR_LINK_FAILED + * If set to _YES, renogiation could not complete. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_ERR_INVALID_PARAMETER + * If set to _YES, one or more of the calling parameters was invalid. + * cmd + * This parameter specifies a bitmask of the legal defined fields. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_NULL + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_RENEGOTIATE + * This command forces the specified displayId to renegotiate the + * hdcp link. The client should supply as an input, + * cN and cKsv. On return, bStatus, stStatus and cS is returned. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_DISABLE_AUTHENTICATION + * This command forces the specified displayId to off authentication the + * hdcp link. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_READ_LINK_STATUS + * This command reads the status of the cipher returning a signed + * S (ie: kP) and cS for the requested displayId, as well as + * the relevant parameters necessary for the client to verify + * the information provided. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_VALIDATE_LINK + * This command returns the parameters necessary to validiate the + * links for the displayId. The client should supply as input + * cN and cKsv. On return, bStatus, cS, stStatus, aN, numBksvs, + * bKsvList, vP, mP, and dKsv are returned. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_QUERY_HEAD_CONFIG + * This command enumerates ports attached to a head. + * On input, Cn and cKsv should be provided and on return + * bSTatus, status, and connection state is returned. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_ABORT_AUTHENTICATION + * This command causes the specified AP to abort authentication + * protocol after KSV list is read, or during next time it's + * renegotiated. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_GET_ALL_FLAGS + * This command provides all possible valid device data. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_GET_SPECIFIED_FLAGS + * This command provides data specified by flags field set by the + * client. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_FORWARD_PENDING_KSVLIST_READY + * This command provides client to tell there's pending Hdcp1X KsvList + * Ready notification at BStatus read. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_READ_LINK_STATUS_NO_DISPLAY + * This command reads the status of the cipher returning a signed + * S (ie: kP) and cS and the relevant parameters necessary for the client to + * verify upstream. + * flags + * This parameter specifies a bitmask of the legal defined fields and the + * reason AbortAuthentication. + * The client shall set the desired fields and on return if valid, + * the resource manager will set which flags are actually valid. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_BCAPS_PRESENT + * IN: Request hdcp receiver bcaps register state. + * OUT: Bcaps parameter contains valid receiver bcaps register data. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_BSTATUS_PRESENT + * IN: Request hdcp receiver bstatus register state. + * OUT: BStatus parameter contains valid receiver bstatus register data + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_BKSV_PRESENT + * IN: Request hdcp receiver key selection vector: BKSV + * Driver will read BKSV from receiver and update RM states if + * the cmd is _GET_SPECIFIED_FLAGS and _KP_PRESENT is unset. + * Otherwise, driver returns cached BKSV. + * OUT: Bksv parameter contains valid receiver bksv data. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_BKSV_LIST_PRESENT + * IN: Request list of downstream BKSV from repeater + * OUT: BksvList parameter contains valid data. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_DKSV_PRESENT + * IN: Request hdcp transmitter key selection vector: DKSV + * OUT: Dksv parameter contains valid receiver DKSV data. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_AN_PRESENT + * IN: Request hdcp parameter An + * OUT: An parameter contains valid data + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_AKSV_PRESENT + * IN: Request hdcp transmitter downstream key selection vector: AKSV + * OUT: Aksv parameter contains valid receiver Aksv data. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_VP_PRESENT + * IN: Request VPrime data + * OUT: VPrime parameter contains valid data + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_MP_PRESENT + * IN: Request MPrime data used for repeater authentication + * OUT: MPrime parameter contains valid data + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_KP_PRESENT + * IN: Request SPrime data + * OUT: SPrime parameter contains valid data + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_IMPLICIT_HEAD + * IN: The head to use if no legal head could be located. + * Use NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_IMPLICIT_HEAD_NONE + * if no implicit head should be used. + * OUT: n/a + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_FORCE_REAUTH + * IN: Request to execute authentication protocol even encryption + * enabled. + * OUT: n/a + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_RXIDMSG_PENDING + * IN: Request to execute repeater authentication protocol with pending + * ID List message information. + * OUT: n/a + * Reason of AbortAuthentication. + * When pass in by client, it indicates the reason why client issue an + * Abort. When return by RM, it indicates the reason of last successful + * Abort. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_ABORT_NONE + * Default value + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_ABORT_UNTRUST + * Abort due to Kp mismatch + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_ABORT_UNRELBL + * Abort due to repeated link failure + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_ABORT_KSV_LEN + * Abort due to KSV length + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_ABORT_KSV_SIG + * Abort due to KSV signature + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_ABORT_SRM_SIG + * Abort due to SRM signature + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_ABORT_SRM_REV + * Abort due to SRM revocation + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_ABORT_NORDY + * Abort due to repeater not ready + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_ABORT_KSVTOP + * Abort due to KSV topology error + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_ABORT_BADBKSV + * Abort due to invalid Bksv + * linkCount + * This parameter specifies how many links are valid. This is important + * when determining AKSV, BKSV, AN, etc... and is an output to this + * command. + * apIndex + * Each element of this parameter specifies the hardware attach-point index + * for the requested displayId. The 2nd element is only valid in the case + * where the resource output is capable of dual-link determined when the + * linkCount is greater than 1. + * cN + * This parameter is the input value Cn a 64 bit random number + * to be provided to this command. Cn value is Upstream protocol's + * exchange random number.This value must be written by software + * before the KSV is written if the transmitter device follows the HDCP + * upstream protocol. + * cKsv + * This parameter is the input value Cksv (a unique identifier) of 40 bit + * size to be provided to this command. This input value shall contain 20 + * ones and 20 zeros in accordance with the HDCP specification. This value + * must be written by software before the KSV is written if the transmitter + * device follows the HDCP upstream protocol. + * aN + * Each element of this buffer specifies the output value aN, + * a 64 bit random number used during hdcp authentication and validating + * the upstream link in which case only the first 40 bits are used. + * The 2nd element is only valid in the case where the resource output is + * capable of dual-link determined when the linkCount is greater than 1. + * aKsv + * Each element of this buffer specifies output value aKsv of 40 bit size. + * As per the HDCP specification this value should contain 20 ones and + * 20 zeros. + * The 2nd element is only valid in the case where the resource output is + * capable of dual-link determined when the linkCount is greater than 1. + * bStatus + * Each element contains the attach-point bStatus data returned by the + * repeater/receiver device (if valid). The bStatus value is an output + * by this command. For HDCP on DP, bInfo is the one we should look at. + * bInfo is defined exactly the same with bStatus on DVI. Hal is taking + * care of the difference here. + * This bStatus info is broken down as follows: + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_BSTATUS_DEVICE_COUNT + * Specifies the total number of receivers excluding repeater. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_BSTATUS_MAX_DEVICES_EXCEEDED + * Specifies a topology error in which greater than 127 devices are + * detected in the overall hdcp configuration. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_BSTATUS_REPEATER_DEPTH + * Specifies the repeater depth. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_BSTATUS_MAX_CASCADE_EXCEEDED + * Specifies a topology error in which greater than 7 levels are + * detected in the overall hdcp configuration. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDMI_MODE + * Specifies that the hdcp receiver is in HDMI mode. + * bCaps + * The BCAPS value is an output by this command. This value's bit fields + * contains information returned by receiver device. Bcaps can be used + * to determine if receiver is a repeater and when the ksvlist and vprime + * data is ready. + * The BCAPS is defined different in the spec of HDCP on DP. It's been + * split to BCAPS and BSTATUS. Here we'll end a flag to indicate + * the client if it's a DP. + * The bCaps parameter is broken down as follows based on HDCP spec 1.1: + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_BCAPS_FAST_REAUTHENTICATION + * This field when set to 1, specifies the receiver is capable of + * receiving(unencrypted) video signal during session + * re-authentication. All HDMI capable receivers shall be capable of + * performing the fast authentication even if this bit is not set. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_BCAPS_EESS_1_1 + * This field when set to 1, specifies this HDCP receiver supports + * Enhanced Encryption Status Signaling (EESS), Advance cipher, and + * Enhanced Link Verification options. For the HDMI protocol, EESS + * capability is assumed regardless of this bit setting. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_BCAPS_READY_KSV_FIFO + * This field when set to 1, specifies this HDCP repeater has built + * the list of attached KSVs and computed the verification value V'. + * This value is always zero during the computation of V'. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_BCAPS_FAST + * This field when set to 1, specifies this device supports 400khz + * transfers. When zero, 100 khz is the maximum transfer rate + * supported. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_BCAPS_REPEATER + * This field when set to 1, specifies the HDCP receiver supports + * downstream connections as permitted by Digital Content + * Protection LLC licence. This bit does not change while the HDCP + * receiver is active. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_BCAPS_HDMI_RESERVED + * This field is reserved and HDCP receivers not capable of + * support HDMI must clear this bit to 0. + * stStatus + * This parameter specifies the attach point stStatus. See + * the description of NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_INFO for + * details on stStatus information. + * cS + * This parameter provides the connection-state for the status of + * all port/attach-points on this head. + * The connection-state is broken down as follows: + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_CS_ATTACH_POINTS + * This field specifies the transmitting attach-points. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_CS_NON_HDCP + * This field specifies the transmitting attach-points. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_CS_HEAD_INDEX + * This field specifies the index of the head. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_CS_RFUPLANES + * This field specifies the RFUPLANES. + * This field *NOT* yet supported. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_CS_NUM_ACTIVE_HEADS + * This field specifies the number of heads - 1. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_CS_ATTACH_PLANES + * This field specifies attach planes. + * This field *NOT* yet supported. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_CS_ENCRYPTING + * This field is supported on chips with Display IP 0501 and later. + * NV0073_CTRL_SPECIFIC_HDCP_CTRL_CS_SPAN_MODE + * This field specifies dual-display span mode. + * This field *NOT* yet supported. + * bKsvList + * In case downstream device is repeater then this will give the list of + * KSV's of all downstream devices attached to the repeater. It differs + * from actualKsvSize because this allocates maximum allowed size. + * If downstream device is receiver then this array will contain all zeros. + * numBksvs + * Total number of Bksv from all downstream devices in the bKsvList. + * This info can also be obtained via bStatus. + * vP + * The VPRIME value returned as output by this command from the repeater + * device. This value should be used to compare the verification value + * during the HDCP upstream protocol using SHA1 in accordance with the + * upstream protocol. This value can be ignored if bAuthRequired is not + * set indicating the verification is done by the transmitter device. + * kP + * The KP value is returned as an output by this command. This + * parameter is the signature computed by hardware and the client + * should compute the signature to compare this value. + * The 2nd element is only valid in the case where the resource output is + * capable of dual-link determined when the linkCount is greater than 1. + * mP + * The MPRIME value returned as output by this command. + * MPrime shall be decrypted by the client and used in the SHA-1 + * computation of V during upstream authentication. This value can be + * ignored if bAuthRequired is not set indicating the verification is + * done by the transmitter device. + * dKsv + * Each element of this buffer is the output value DKSV of 40 bit size. + * As per the HDCP specification this value should contain 20 ones and + * 20 zeros. + * The 2nd element is only valid in the case where the resource output is + * capable of dual-link determined when the linkCount is greater than 1. + * streamIndex + * Each content stream is assigned an index value bye upstream client. + * HDMI: The index must be 0. + * DP SST: The index must be 0. + * DP MST: Assigned stream index. + * streamType + * Each content stream is assigned a type value by the upstream content + * control function. + * 0x00: Type 0 content stream. May be transimtted by the HDCP repeater to + * all HDCP devices. + * 0x01: Type 1 content stream. Must not be transmitted by the HDCP + * repeater to HDCP 1.x-compliant devices and HDCP 2.0-compliant + * repeaters. + * 0x02-0xFF: reserved for futures use only. + * bEnforceType0Hdcp1xDS + * If this bit is set, DPU enforces Type0 if it finds Hdcp1x monitor downstream + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SPECIFIC_HDCP_CTRL (0x730282U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_HDCP_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_HDCP_LINK_COUNT (0x0000002U) +#define NV0073_CTRL_HDCP_VPRIME_SIZE (0x0000014U) +#define NV0073_CTRL_HDCP_MAX_DEVICE_COUNT (0x00000FFU) +#define NV0073_CTRL_HDCP_KSV_SIZE (0x0000005U) +#define NV0073_CTRL_HDCP_MAX_NUM_APS (0x0000010U) + +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_PARAMS_MESSAGE_ID (0x82U) + +typedef struct NV0073_CTRL_SPECIFIC_HDCP_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + + NvU32 err; + + NvU32 cmd; + NvU32 flags; + NvU8 linkCount; + + NV_DECLARE_ALIGNED(NvU64 cN, 8); + NV_DECLARE_ALIGNED(NvU64 cKsv, 8); + + NvU32 apIndex[NV0073_CTRL_HDCP_LINK_COUNT]; + + NV_DECLARE_ALIGNED(NvU64 aN[NV0073_CTRL_HDCP_LINK_COUNT], 8); + NV_DECLARE_ALIGNED(NvU64 aKsv[NV0073_CTRL_HDCP_LINK_COUNT], 8); + + NvU32 bStatus[NV0073_CTRL_HDCP_MAX_NUM_APS]; + NvU32 bCaps[NV0073_CTRL_HDCP_MAX_NUM_APS]; + + NV_DECLARE_ALIGNED(NV0073_CTRL_SPECIFIC_HDCP_CTRL_STATUS_INFO stStatus[NV0073_CTRL_HDCP_MAX_NUM_APS], 8); + + NV_DECLARE_ALIGNED(NvU64 cS, 8); + + NV_DECLARE_ALIGNED(NvU64 bKsv[NV0073_CTRL_HDCP_LINK_COUNT], 8); + NV_DECLARE_ALIGNED(NvU64 bKsvList[NV0073_CTRL_HDCP_MAX_DEVICE_COUNT], 8); + NvU32 numBksvs; + + NvU8 vP[NV0073_CTRL_HDCP_VPRIME_SIZE]; + NV_DECLARE_ALIGNED(NvU64 kP[NV0073_CTRL_HDCP_LINK_COUNT], 8); + + NV_DECLARE_ALIGNED(NvU64 mP, 8); + NV_DECLARE_ALIGNED(NvU64 dKsv[NV0073_CTRL_HDCP_LINK_COUNT], 8); + + NvU32 streamIndex; + NvU8 streamType; + NvBool bEnforceType0Hdcp1xDS; + + NvBool bPendingKsvListReady; + + NvBool isHdcpCapable; + NvBool isHdcpAuthOn; + NvBool isHdcpRp; + NvBool isHdcp2X; + NvBool bMaxCascadeExceeded; + NvBool bMaxDeviceExceeded; + NvBool bHdcp1DevDownstream; + NvBool bHdcp2LegacyDevDownstream; + NvU8 cascadeDepth; +} NV0073_CTRL_SPECIFIC_HDCP_CTRL_PARAMS; + +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_ERR_UNSUCCESSFUL 0:0 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_ERR_UNSUCCESSFUL_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_ERR_UNSUCCESSFUL_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_ERR_PENDING 1:1 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_ERR_PENDING_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_ERR_PENDING_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_ERR_BAD_TOKEN_TYPE 2:2 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_ERR_BAD_TOKEN_TYPE_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_ERR_BAD_TOKEN_TYPE_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_ERR_LINK_FAILED 3:3 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_ERR_LINK_FAILED_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_ERR_LINK_FAILED_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_ERR_INVALID_PARAMETER 4:4 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_ERR_INVALID_PARAMETER_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_ERR_INVALID_PARAMETER_YES (0x0000001U) + +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD 31:0 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_NULL (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_READ_LINK_STATUS (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_VALIDATE_LINK (0x0000002U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_QUERY_HEAD_CONFIG (0x0000003U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_RENEGOTIATE (0x0000004U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_GET_ALL_FLAGS (0x0000005U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_GET_SPECIFIED_FLAGS (0x0000006U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_ABORT_AUTHENTICATION (0x0000007U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_DISABLE_AUTHENTICATION (0x0000008U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_SET_TYPE (0x0000009U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_FORWARD_KSVLIST_READY (0x000000AU) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_READ_LINK_STATUS_NO_DISPLAY (0x000000BU) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_READ_TOPOLOGY (0x000000CU) + +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_BCAPS_PRESENT 0:0 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_BCAPS_PRESENT_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_BCAPS_PRESENT_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_BSTATUS_PRESENT 1:1 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_BSTATUS_PRESENT_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_BSTATUS_PRESENT_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_BKSV_PRESENT 2:2 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_BKSV_PRESENT_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_BKSV_PRESENT_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_BKSV_S_PRESENT 3:3 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_BKSV_S_PRESENT_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_BKSV_S_PRESENT_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_BKSV_LIST_PRESENT 4:4 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_BKSV_LIST_PRESENT_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_BKSV_LIST_PRESENT_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_AN_PRESENT 5:5 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_AN_PRESENT_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_AN_PRESENT_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_AN_S_PRESENT 6:6 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_AN_S_PRESENT_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_AN_S_PRESENT_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_AKSV_PRESENT 7:7 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_AKSV_PRESENT_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_AKSV_PRESENT_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_AKSV_S_PRESENT 8:8 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_AKSV_S_PRESENT_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_AKSV_S_PRESENT_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_DKSV_PRESENT 9:9 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_DKSV_PRESENT_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_DKSV_PRESENT_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_DKSV_S_PRESENT 10:10 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_DKSV_S_PRESENT_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_DKSV_S_PRESENT_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_MP_PRESENT 11:11 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_MP_PRESENT_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_MP_PRESENT_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_VP_PRESENT 12:12 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_VP_PRESENT_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_VP_PRESENT_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_CN_PRESENT 13:13 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_CN_PRESENT_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_CN_PRESENT_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_CKSV_PRESENT 14:14 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_CKSV_PRESENT_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_CKSV_PRESENT_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_KP_PRESENT 15:15 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_KP_PRESENT_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_KP_PRESENT_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_KP_S_PRESENT 16:16 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_KP_S_PRESENT_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_KP_S_PRESENT_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_STATUS_PRESENT 17:17 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_STATUS_PRESENT_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_STATUS_PRESENT_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_CS_PRESENT 18:18 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_CS_PRESENT_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_CS_PRESENT_YES (0x0000001U) + +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_ABORT 22:19 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_ABORT_NONE (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_ABORT_UNTRUST (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_ABORT_UNRELBL (0x0000002U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_ABORT_KSV_LEN (0x0000003U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_ABORT_KSV_SIG (0x0000004U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_ABORT_SRM_SIG (0x0000005U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_ABORT_SRM_REV (0x0000006U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_ABORT_NORDY (0x0000007U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_ABORT_KSVTOP (0x0000008U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_ABORT_BADBKSV (0x0000009U) + +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_IMPLICIT_HEAD 25:23 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_IMPLICIT_HEAD_NONE (0x0000007U) + +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_TYPE_CHANGED 26:26 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_TYPE_CHANGED_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_TYPE_CHANGED_YES (0x0000001U) + +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_FORCE_REAUTH 27:27 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_FORCE_REAUTH_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_FORCE_REAUTH_YES (0x0000001U) + +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_RXIDMSG_PENDING 28:28 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_RXIDMSG_PENDING_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_RXIDMSG_PENDING_YES (0x0000001U) + +/* BCaps definition of HDCP over TMDS */ +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_BCAPS_FAST_REAUTHENTICATION 0:0 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_BCAPS_EESS_1_1 1:1 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_BCAPS_FAST 4:4 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_BCAPS_READY_KSV_FIFO 5:5 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_BCAPS_REPEATER 6:6 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_BCAPS_HDMI_RESERVED 7:7 +/* BCaps definition of HDCP over DP */ +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_BCAPS_DP_HDCP_CAPABLE 0:0 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_BCAPS_DP_REPEATER 1:1 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_BCAPS_DP_READY_KSV_FIFO 2:2 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_BCAPS_DP_R0_AVAILABLE 3:3 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_BCAPS_DP_LINK_INTEGRITY_FAILURE 4:4 + +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_BSTATUS_DEVICE_COUNT 6:0 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_BSTATUS_MAX_DEVICES_EXCEEDED 7:7 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_BSTATUS_REPEATER_DEPTH 10:8 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_BSTATUS_MAX_CASCADE_EXCEEDED 11:11 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDMI_MODE 12:12 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_RESERVED_0 31:13 + +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CS_ATTACH_POINTS 15:0 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CS_NON_HDCP 16:16 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CS_HEAD_INDEX 20:17 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CS_RFUPLANES 28:21 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CS_NUM_ACTIVE_HEADS 30:29 +// Bit 39-29 are implementation dependent connection state information +// for HDCP22 from gm206 (v02_06) onwards Bit-30 says HDCP22 encryption status. +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CS_HDCP22_ENCRYPTION 30:30 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CS_HDCP22_ENCRYPTION_YES 0x00000001U +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CS_HDCP22_ENCRYPTION_NO 0x00000000U +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CS_HDCP22_TYPE1 31:31 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CS_HDCP22_TYPE1_YES 0x00000001U +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CS_HDCP22_TYPE1_NO 0x00000000U +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CS_RESERVED_0 39:32 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CS_ATTACH_PLANES 47:40 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CS_ENCRYPTING 48:48 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CS_SPAN_MODE 49:49 + +/* This HDCP_MODE definition applies to both DP and TMDS */ +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_BCAPS_HDCP_MODE 15:15 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_BCAPS_HDCP_MODE_TMDS (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_BCAPS_HDCP_MODE_DP (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_BCAPS_HDCP_VERSION 23:16 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_BCAPS_HDCP_VERSION_1X (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_BCAPS_HDCP_VERSION_22 (0x0000022U) + +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_BCAPS_REPEATER 0:0 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_BCAPS_REPEATER_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_BCAPS_REPEATER_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_BCAPS_HDCP_CAPABLE 1:1 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_BCAPS_HDCP_CAPABLE_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_BCAPS_HDCP_CAPABLE_YES (0x0000001U) + +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_BSTATUS_DP_READY 0:0 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_BSTATUS_DP_HPRIME_AVAILABLE 1:1 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_BSTATUS_DP_PAIRING_AVAILABLE 2:2 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_BSTATUS_DP_REAUTH_REQ 3:3 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_BSTATUS_DP_LINK_INTEGRITY_FAILURE 4:4 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_BSTATUS_HDCP1_REPEATER_DOWNSTREAM 5:5 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_BSTATUS_HDCP2_0_REPEATER_DOWNSTREAM 6:6 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_BSTATUS_MAX_CASCADE_EXCEEDED 7:7 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_BSTATUS_MAX_DEVS_EXCEEDED 8:8 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_BSTATUS_DEVICE_COUNT 13:9 +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_BSTATUS_REPEATER_DEPTH 16:14 + +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_TYPE_0 (0x00U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_TYPE_1 (0x01U) + +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_ENFORCE_TYPE0_HDCP1XDS_NO (0x00U) +#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_ENFORCE_TYPE0_HDCP1XDS_YES (0x01U) + + + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_HDCP_DIAGNOSTICS + * + * This command is used to obtain diagnostic info, useful when hdcp + * fails for the specified attach point (that being the displayId). + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the display for which information is to be + * returned. Only one display may be indicated in this parameter. + * If more than one displayId is used a failing status of + * NV_ERR_INVALID_ARGUMENT will be returned. + * flags + * This parameter specifies the diagnostics obtained from the attach point + * resource. Here are the current defined fields: + * NV0073_CTRL_SPECIFIC_HDCP_STATE_ROM_ERROR + * The hdcp hardware detected an error with the rom. Possible + * causes are that a rom is not present or if present, the hardware + * is not able to access the rom. + * NV0073_CTRL_SPECIFIC_HDCP_DIAGNOSTICS_BOND_NOT_ENABLED + * The hdcp fuse register has not been set. + * NV0073_CTRL_SPECIFIC_HDCP_STATE_AKSV_INVALID + * If the AKSV (key selection vector) of the hardware does not return + * 20 1s and 0s, this bit will be set. This is an indication that + * the ROM is not programmed correctly and may need to be corrected + * by replacing the external hdcp cryptorom. + * NV0073_CTRL_SPECIFIC_HDCP_STATE_BKSV_INVALID + * If the BKSV (key selection vector) of the display receiver hardware + * does not return 20 1s and 0s, this bit will be set. + * NV0073_CTRL_SPECIFIC_HDCP_STATE_DKSV_INVALID + * If the DKSV (key selection vector) of the upstream hdcp hardware + * does not return 20 1s and 0s, this bit will be set. + * NV0073_CTRL_SPECIFIC_HDCP_STATE_DUAL_LINK_INUSE + * This bit is set if the attach point is currently outputting dual-link + * NV0073_CTRL_SPECIFIC_HDCP_STATE_DOWNSTREAM_CHECKSUM_FAILED + * This bit is set if hardware reports that its checksum BIST of its + * downstream HDCP keys failed. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDCP_DIAGNOSTICS (0x730281U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_HDCP_DIAGNOSTICS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_GET_HDCP_DIAGNOSTICS_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_HDCP_DIAGNOSTICS_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 flags; +} NV0073_CTRL_SPECIFIC_GET_HDCP_DIAGNOSTICS_PARAMS; + +#define NV0073_CTRL_SPECIFIC_HDCP_DIAGNOSTICS_ROM_ERROR 0:0 +#define NV0073_CTRL_SPECIFIC_HDCP_DIAGNOSTICS_BOND_NOT_ENABLED 1:1 +#define NV0073_CTRL_SPECIFIC_HDCP_DIAGNOSTICS_AKSV_INVALID 2:2 +#define NV0073_CTRL_SPECIFIC_HDCP_DIAGNOSTICS_BKSV_INVALID 3:3 +#define NV0073_CTRL_SPECIFIC_HDCP_DIAGNOSTICS_DKSV_INVALID 4:4 +#define NV0073_CTRL_SPECIFIC_HDCP_DIAGNOSTICS_DUAL_LINK_INUSE 5:5 +#define NV0073_CTRL_SPECIFIC_HDCP_DIAGNOSTICS_DOWNSTREAM_CHECKSUM_FAILED 6:6 + +/* + * NV0073_CTRL_SPECIFIC_ACPI_ID_MAPPING + * + * This structure defines the mapping between the ACPI ID and the corresponding + * display ID of a display device + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * acpiId + * The ACPI ID of the display device + * displayId + * The corresponding display ID + * dodIndex + * The corresponding DOD index + */ +typedef struct NV0073_CTRL_SPECIFIC_ACPI_ID_MAPPING { + NvU32 subDeviceInstance; + NvU32 acpiId; + NvU32 displayId; + NvU32 dodIndex; +} NV0073_CTRL_SPECIFIC_ACPI_ID_MAPPING; + +/* + * NV0073_CTRL_CMD_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT + * + * This call will return the Display Port Attachment value + * per displayID as defined by Nvidia that is directly + * associated with the ACPI 3.0 _DOD entry's Display Port + * Attachment field. This should help clients map the + * _DOD ACPI ID to each displayID. Note, that some systems + * do not have a standard in place for this field. On those + * systems, the RM will return NV_ERR_NOT_SUPPORTED. + * + * Note that this "Display Port" attachment field has nothing + * to do with DisplayPort/DP. It's an unfortunate name inside + * the ACPI 3.0 spec that coincides with the name of DisplayPort. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_NOT_SUPPORTED + * +*/ + +#define NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS_MESSAGE_ID (0x85U) + +typedef struct NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 dispPortAttachment; +} NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS; + + +#define NV0073_CTRL_CMD_SPECIFIC_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT (0x730285U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS_MESSAGE_ID" */ + +// defines for dispPortAttachment +#define NV0073_DISPLAY_PORT_ATTACHMENT_ANALOG (0x00000000U) +#define NV0073_DISPLAY_PORT_ATTACHMENT_LVDS (0x00000001U) +#define NV0073_DISPLAY_PORT_ATTACHMENT_DP_A (0x00000002U) +#define NV0073_DISPLAY_PORT_ATTACHMENT_DP_B (0x00000003U) +#define NV0073_DISPLAY_PORT_ATTACHMENT_DP_C (0x00000004U) +#define NV0073_DISPLAY_PORT_ATTACHMENT_DP_D (0x00000005U) +#define NV0073_DISPLAY_PORT_ATTACHMENT_UNKNOWN (0xFFFFFFFFU) + +/* + * NV0073_CTRL_CMD_SPECIFIC_SET_ACPI_ID_MAPPING + * + * This call will update the RM data structure which holds the + * ACPI ID to display ID mapping of the display devices + * + * The input parameter is an array of structures of type + * NV0073_CTRL_SPECIFIC_ACPI_ID_MAPPING + * + * If some of the array elements remain unused, the acpiId field of the + * structure must be set to 0x0000 + * + * The size of the array is given by + * NV0073_CTRL_SPECIFIC_MAX_ACPI_DEVICES (defined below) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * +*/ +#define NV0073_CTRL_CMD_SPECIFIC_SET_ACPI_ID_MAPPING (0x730284U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_MAX_ACPI_DEVICES 16U + +#define NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS_MESSAGE_ID (0x84U) + +typedef struct NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS { + NV0073_CTRL_SPECIFIC_ACPI_ID_MAPPING mapTable[NV0073_CTRL_SPECIFIC_MAX_ACPI_DEVICES]; +} NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_ALL_HEAD_MASK + * + * This call will return all head mask. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * headMask + * headMask is the mask of all heads that are usable. For example, if + * head 0 and head 2 are present, headMask would be NVBIT(0)|NVBIT(2). This + * parameter returns to the client. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_ALL_HEAD_MASK (0x730287U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS_MESSAGE_ID (0x87U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS { + NvU32 subDeviceInstance; + NvU32 headMask; +} NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_SET_OD_PACKET + * + * This command is used to program the display output packets. + * Currently it supports DP and HDMI. + * Common supported packets are AVI infoframes, Audio Infoframes, Gamma + * Metadata, Vendor Specific infoframes and General Control Packets (GCP). + * + GCP AVMute Enable should be performed before the start of the modeset. + * + GCP AVMute Disable should be performed after the end of the modeset. + * GCP AVMute should contain HDR + 7 bytes. + * + AVI infoframes should occur after the modeset but before a GCP AVMute + * Disable. AVI infoframe should contain HDR + 14 bytes + * + Audio infoframes should occur after the modeset but before a GCP AVMute + * Enable. + * Audio infoframe should contain HDR + 11 bytes. + * + Gamma Metadata packets should contain HDR + 28 bytes. + * + Vendor Specific packets are variable length. + * By HDMI 1.4 June 5 2009 spec, payload can be 5 bytes, 6 bytes, 7 bytes or + * 16 bytes, depending on the packets spec. + * Unused data bytes should be zero-ed out. + * + * displayID + * This parameter specifies the displayID for the display resource to + * configure. + * This comes as input to this command. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * transmitControl + * This parameter controls how the packet is to be sent by setting the + * control bits. + * Possible flags are as follows: + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE + * Set to _ENABLE to start sending the packet at next frame, set to + * _DISABLE to stop sending. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME + * Set to _ENABLE to send the packet at other frame, set to _DISABLE to + * send at every frame. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME + * Set to _ENABLE to send once next frame, set to _DISABLE to send at + * every frame. + * Note: A setting to set both _OTHER_FRAME and _SINGLE_FRAME is invalid + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK + * Set to _ENABLE to send the packet once on next HBLANK, set to + * _DISABLE to send on VBLANK. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE + * Set to _ENABLE to send the info frame packet as soon as possible. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT + * Set to _SW_CONTROLLED to set HDMI_Video_Format field and 3D_Structure field + * from NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB4 and PB5, if it is set to _HW_CONTROLLED + * then HW will get them based on the state of the setHdmiCtrl method. + * Btw this applies only for stereo ovverides. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY + * Set to TRUE to send Vendor specific info frame used for 3D stereo LR sync. + * Set PACKET_TYPE=pktType_VendorSpecInfoFrame along with this flag. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING + * Set to TRUE to send Vendor specific info frame used for Self Refresh panels + * Set PACKET_TYPE=pktType_VendorSpecInfoFrame along with this flag. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE + * HW provides support to program 2 generic infoframes per frame for DP with GP10X+. + * This flag indicates the INFOFRAME that needs to be programmed. + * Set to _INFOFRAME0 if RM should program GENERIC_INFOFRAME + * Set to _INFOFRAME1 if RM should program GENERIC_INFOFRAME1 + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE + * This option is reserved for backward compatibility with + * NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_PACKET and + * NV0073_CTRL_CMD_DP_SET_PACKET. + * It is temporal and will be deprecated soon. + * packetSize + * packet size of packets in pPacket to send, including header and payload. + * targetHead + * Specifies the target head number for which SDP needs to be updated. + * bUsePsrHeadforSdp + * Indicates use targetHead field for setting SDP or infoframe packet instead + * of deriving the active head from displayID. + * pPacket + * pPacket points to the packets to send. + * For HDMI 1.1, the maximum allowed bytes is 31. + * The packet array includes the 3 bytes of header + data depending on + * the type of packet. For an infoframe, the header bytes refer to type, + * version and length respectively. This comes as input to this command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_SET_OD_PACKET (0x730288U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SET_OD_MAX_PACKET_SIZE 36U + +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS_MESSAGE_ID (0x88U) + +typedef struct NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 transmitControl; + NvU32 packetSize; + NvU32 targetHead; + NvBool bUsePsrHeadforSdp; + NvU8 aPacket[NV0073_CTRL_SET_OD_MAX_PACKET_SIZE]; +} NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS; + +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE 0:0 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME 1:1 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME_DISABLE (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME_ENABLE (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME 2:2 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME_DISABLE (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME_ENABLE (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK 3:3 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK_DISABLE (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK_ENABLE (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE 4:4 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE_DISABLE (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE_ENABLE (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT 5:5 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT_SW_CONTROLLED (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT_HW_CONTROLLED (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY 6:6 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY_FALSE (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY_TRUE (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING 7:7 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_FALSE (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_TRUE (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE 9:8 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE_INFOFRAME0 (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE_INFOFRAME1 (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE 31:31 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_YES (0x0000001U) + + +/* + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_PARAMS + * + * This command is used to enable/disable sending of display output packets. + * Currently it supports HDMI only. + * Unused data bytes should be zero-ed out. + * + * displayID + * This parameter specifies the displayID for the display output resource to + * configure. + * This comes as input to this command. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * type + * The client shall specify the type of display output packet. For HDMI, set + * this according to HDMI specification 1.4. + * This comes as input to this command. + * transmitControl + * This parameter controls how the packet is to be sent by setting the control + * bits. + * Possible flags are as follows: + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ENABLE + * Set to _ENABLE to start sending the packet at next frame, set to + * _DISABLE to stop sending. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_OTHER_FRAME + * Set to _ENABLE to send the packet at other frame, set to _DISABLE to + * send at every frame. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SINGLE_FRAME + * Set to _ENABLE to send once next frame, set to _DISABLE to send at + * every frame. + * Note: A setting to set both _OTHER_FRAME and _SINGLE_FRAME is invalid + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ON_HBLANK + * Set to _ENABLE to send the packet once on next HBLANK, set to _DISABLE + * to send on VBLANK. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_VIDEO_FMT + * Set to _SW_CONTROLLED to set HDMI_Video_Format field and 3D_Structure field + * from NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB4 and PB5, if it is set to _HW_CONTROLLED + * then HW will get them based on the state of the setHdmiCtrl method. + * Btw this applies only for stereo ovverides. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_STEREO_POLARITY + * Set to TRUE to enable Vendor specific info frame used for 3D stereo LR sync + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING + * Set to TRUE to enable Vendor specific info frame used for Self Refresh panels + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE + * This option is reserved for backward compatibility with + * NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_PACKET and + * NV0073_CTRL_CMD_DP_SET_PACKET. + * It is temporal and will be deprecated soon. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_SET_OD_PACKET_CTRL (0x730289U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_PARAMS_MESSAGE_ID (0x89U) + +typedef struct NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 type; + NvU32 transmitControl; +} NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_PARAMS; + +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ENABLE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ENABLE_NO NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE_NO +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ENABLE_YES NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE_YES +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_OTHER_FRAME NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_OTHER_FRAME_DISABLE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME_DISABLE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_OTHER_FRAME_ENABLE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME_ENABLE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SINGLE_FRAME NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SINGLE_FRAME_DISABLE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME_DISABLE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SINGLE_FRAME_ENABLE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME_ENABLE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ON_HBLANK NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ON_HBLANK_DISABLE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK_DISABLE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ON_HBLANK_ENABLE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK_ENABLE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_VIDEO_FMT NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_VIDEO_FMT_SW_CONTROLLED NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT_SW_CONTROLLED +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_VIDEO_FMT_HW_CONTROLLED NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT_HW_CONTROLLED +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_STEREO_POLARITY NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_STEREO_POLARITY_FALSE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY_FALSE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_STEREO_POLARITY_TRUE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY_TRUE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_TRUE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_FALSE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_FALSE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_TRUE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_NO NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_NO +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_YES NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_YES + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_PCLK_LIMIT + * + * This command returns the maximum supported pixel clock rate that is + * supported by the specified display device. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the display for which information is to be + * returned. Only one display may be indicated in this parameter. + * If more than one displayId is used a failing status of + * NV_ERR_INVALID_ARGUMENT will be returned. + * pclkLimit + * This parameter returns the min of orPclkLimit and vbPclkLimit in KHz. + * It may be used for SLI configs that use a video bridge. For non-SLI + * configs and bridgeless SLI configs, the client should use orPclkLimit instead. + * orPclkLimit + * This parameter returns the maximum pixel clock frequency of OR in KHz. + * vbPclkLimit + * This parameter returns the maximum pixel clock frequency of the + * video bridge (SLI) in KHz (or zero if there is no video bridge). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_PCLK_LIMIT (0x73028aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_PCLK_LIMIT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_GET_PCLK_LIMIT_PARAMS_MESSAGE_ID (0x8AU) + +typedef struct NV0073_CTRL_SPECIFIC_GET_PCLK_LIMIT_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 pclkLimit; + NvU32 orPclkLimit; + NvU32 vbPclkLimit; +} NV0073_CTRL_SPECIFIC_GET_PCLK_LIMIT_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_OR_GET_INFO + * + * This command returns output resource information for the specified display + * device. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the display for which information is to be + * returned. Only one display may be indicated in this parameter. + * If more than one displayId is used a failing status of + * NV_ERR_INVALID_ARGUMENT will be returned. + * type + * This parameter returns the output resource type. Legal values for + * this parameter include: + * NV0073_CTRL_SPECIFIC_OR_TYPE_DAC + * The output resource is a DAC. + * NV0073_CTRL_SPECIFIC_OR_TYPE_SOR + * The output resource is a serial output resource. + * NV0073_CTRL_SPECIFIC_OR_TYPE_DSI + * The output resource is a Display Serial Interface output resource. + * NV0073_CTRL_SPECIFIC_OR_TYPE_PIOR + * The output resource is a parallel input output resource. + * index + * This parameter returns the type-specific index of the output + * resource associated with the specified displayId. + * protocol + * This parameter returns the type-specific protocol used by the + * output resource. Legal values for this parameter include: + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_DAC_RGB_CRT + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_LVDS_CUSTOM + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_A + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_B + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DUAL_TMDS + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_A + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_B + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_PIOR_EXT_TMDS_ENC + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_DSI + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_UNKNOWN + * ditherType + * This parameter returns the dither type for the output resource. + * Legal values for this parameter include: + * NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_6_BITS + * NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_8_BITS + * NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_10_BITS + * NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_OFF + * ditherAlgo + * This parameter returns the dithering algorithm used by the output + * resource. Legal values for this parameter include: + * NV0073_CTRL_SPECIFIC_OR_DITHER_ALOGO_DYNAMIC_ERR_ACC + * NV0073_CTRL_SPECIFIC_OR_DITHER_ALOGO_STATIC_ERR_ACC + * NV0073_CTRL_SPECIFIC_OR_DITHER_ALOGO_DYNAMIC_2X2 + * NV0073_CTRL_SPECIFIC_OR_DITHER_ALOGO_STATIC_2X2 + * NV0073_CTRL_SPECIFIC_OR_DITHER_ALOGO_TEMPORAL + * NV0073_CTRL_SPECIFIC_OR_DITHER_ALOGO_UNKNOWN + * location + * This parameter returns the physical location of the output resource. + * Legal values for this parameter include: + * NV0073_CTRL_SPECIFIC_OR_LOCATION_CHIP + * NV0073_CTRL_SPECIFIC_OR_LOCATION_BOARD + * rootPortId + * This parameter specifies the Root-Port ID for the given display. + * dcbIndex + * This parameter returns the DCB index of the display device. + * vbiosAddress + * This parameter is the VBIOS IP address which will have valid value + * only if displayId is allocated by VBIOS. + * bIsLitByVbios + * This parameter specifies that whether displayID allocation was + * requested by VBIOS or not. + * bIsDispDynamic + * Returns NV_TRUE if DisplayID is allocated Dynamically else NV_FALSE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_OR_GET_INFO (0x73028bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS_MESSAGE_ID (0x8BU) + +typedef struct NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 index; + NvU32 type; + NvU32 protocol; + NvU32 ditherType; + NvU32 ditherAlgo; + NvU32 location; + NvU32 rootPortId; + NvU32 dcbIndex; + NV_DECLARE_ALIGNED(NvU64 vbiosAddress, 8); + NvBool bIsLitByVbios; + NvBool bIsDispDynamic; +} NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS; + +/* valid type values */ +#define NV0073_CTRL_SPECIFIC_OR_TYPE_NONE (0x00000000U) +#define NV0073_CTRL_SPECIFIC_OR_TYPE_DAC (0x00000001U) +#define NV0073_CTRL_SPECIFIC_OR_TYPE_SOR (0x00000002U) +#define NV0073_CTRL_SPECIFIC_OR_TYPE_PIOR (0x00000003U) + + +#define NV0073_CTRL_SPECIFIC_OR_TYPE_DSI (0x00000005U) + +/* valid DAC protocol values */ +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_DAC_RGB_CRT (0x00000000U) + + + +/* valid SOR protocol values */ +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_LVDS_CUSTOM (0x00000000U) +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_A (0x00000001U) +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_B (0x00000002U) +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DUAL_TMDS (0x00000005U) +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_A (0x00000008U) +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_B (0x00000009U) +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DSI (0x00000010U) + +/* valid DSI protocol values */ +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_DSI (0x00000011U) + +/* valid PIOR protocol values */ +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_PIOR_EXT_TMDS_ENC (0x00000000U) + +/* valid UNKNOWN protocol value */ +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_UNKNOWN (0xFFFFFFFFU) + +/* valid ditherType values */ +#define NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_6_BITS (0x00000000U) +#define NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_8_BITS (0x00000001U) +#define NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_10_BITS (0x00000002U) +#define NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_OFF (0x00000003U) + +/* valid ditherAlgo values */ +#define NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_DYNAMIC_ERR_ACC (0x00000000U) +#define NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_STATIC_ERR_ACC (0x00000001U) +#define NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_DYNAMIC_2X2 (0x00000002U) +#define NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_STATIC_2X2 (0x00000003U) +#define NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_TEMPORAL (0x00000004U) +#define NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_UNKNOWN (0xFFFFFFFFU) + +/* valid location values */ +#define NV0073_CTRL_SPECIFIC_OR_LOCATION_CHIP (0x00000000U) +#define NV0073_CTRL_SPECIFIC_OR_LOCATION_BOARD (0x00000001U) + +/* + * NV0073_CTRL_CMD_SPECIFIC_HDCP_KSVLIST_VALIDATE + * + * This Command initiate the KSV validation for the specific device + * if it is a repeater. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * displayId + * This parameter specifies the ID of the root port device for which KsvList is to be validated + * bUseCachedKsvList + * The parameter specifies RM to use cachedKsvList in case BCAPS's READY bit not set to read + * ksvList. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_NOT_READY + */ +#define NV0073_CTRL_CMD_SPECIFIC_HDCP_KSVLIST_VALIDATE (0x73028dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_HDCP_KSVLIST_VALIDATE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_HDCP_KSVLIST_VALIDATE_PARAMS_MESSAGE_ID (0x8DU) + +typedef struct NV0073_CTRL_SPECIFIC_HDCP_KSVLIST_VALIDATE_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bUseCachedKsvList; +} NV0073_CTRL_SPECIFIC_HDCP_KSVLIST_VALIDATE_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_HDCP_UPDATE + * + * This Command updates the display to the proper HDCP state based on + * whether it has been newly connected or disconnected. This is called + * during a hotplug event. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * displayId + * This parameter specifies the ID of the root port device to update + * bIsConnected + * This parameter specifies whether the device has been connected (NV_TRUE) + * or disconnected (NV_FALSE). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_SPECIFIC_HDCP_UPDATE (0x73028eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_HDCP_UPDATE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_HDCP_UPDATE_PARAMS_MESSAGE_ID (0x8EU) + +typedef struct NV0073_CTRL_SPECIFIC_HDCP_UPDATE_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bIsConnected; +} NV0073_CTRL_SPECIFIC_HDCP_UPDATE_PARAMS; + + + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS + * NV0073_CTRL_CMD_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS + * + * These commands retrieve and set the user backlight brightness for + * the specified display. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId + * Display for which brightness is to be retrieved or set. + * brightness + * The backlight brightness in the range [0,100], inclusive. This + * is an input for SET_BACKLIGHT_BRIGHTNESS, and an output for + * GET_BACKLIGHT_BRIGHTNESS. + * brightnessType + * This can take in one of the three parameters: + * NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_TYPE_PERCENT100(for percentage brightness with value calibrated to 100 scale), + * NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_TYPE_PERCENT1000(for percentage brightness with uncalibrated values), + * NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_TYPE_NITS(used when panel supports Nits based) + * based on the brightness control method to be used. + * + * Possible status values returned include: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS (0x730291U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_BACKLIGHT_BRIGHTNESS_MIN_VALUE 0U +#define NV0073_CTRL_BACKLIGHT_BRIGHTNESS_MAX_VALUE 100U + +typedef struct NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 brightness; + NvBool bUncalibrated; + NvU8 brightnessType; +} NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS; +#define NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_TYPE_PERCENT100 1 +#define NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_TYPE_PERCENT1000 2 +#define NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_TYPE_NITS 3 + +#define NV0073_CTRL_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID (0x91U) + +typedef NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS NV0073_CTRL_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS_PARAMS; + +#define NV0073_CTRL_CMD_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS (0x730292U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID (0x92U) + +typedef NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS NV0073_CTRL_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS + * + * This command is used to inform RM about the scrambling, clock mode, FRL and + * DSC caps of the HDMI sink device. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed.. + * displayID + * This parameter specifies the displayID for the display output resource to + * configure. + * caps + * This parameter specifies the sink caps. + * GT_340MHZ_CLOCK_SUPPORTED refers to whether sink supports TMDS clock (sorClk) rate greater than 340 MHz + * LTE_340MHZ_SCRAMBLING_SUPPORTED refers to whether scrambling is supported for clock rate at or below 340 MHz + * SCDC_SUPPORTED refers to whether SCDC access is supported on sink + * MAX_FRL_RATE_SUPPORTED refers to the maximum HDMI 2.1 FRL rate supported + * DSC_12_SUPPORTED refers to whether VESA DSC v1.2a is supported + * DSC_12_MAX_FRL_RATE_SUPPORTED refers to the maximum HDMI 2.1 FRL rate supported when VESA DSC v1.2a is supported + * + * + * Possible status values returned include: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS (0x730293U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS_MESSAGE_ID (0x93U) + +typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 caps; +} NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS; + +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_GT_340MHZ_CLOCK_SUPPORTED 0:0 +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_GT_340MHZ_CLOCK_SUPPORTED_FALSE (0x00000000U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_GT_340MHZ_CLOCK_SUPPORTED_TRUE (0x00000001U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_LTE_340MHZ_SCRAMBLING_SUPPORTED 1:1 +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_LTE_340MHZ_SCRAMBLING_SUPPORTED_FALSE (0x00000000U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_LTE_340MHZ_SCRAMBLING_SUPPORTED_TRUE (0x00000001U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_SCDC_SUPPORTED 2:2 +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_SCDC_SUPPORTED_FALSE (0x00000000U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_SCDC_SUPPORTED_TRUE (0x00000001U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED 5:3 +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_NONE (0x00000000U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_3LANES_3G (0x00000001U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_3LANES_6G (0x00000002U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_6G (0x00000003U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_8G (0x00000004U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_10G (0x00000005U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_12G (0x00000006U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_12_SUPPORTED 6:6 +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_12_SUPPORTED_FALSE (0x00000000U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_12_SUPPORTED_TRUE (0x00000001U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED 9:7 +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_NONE (0x00000000U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_3LANES_3G (0x00000001U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_3LANES_6G (0x00000002U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_6G (0x00000003U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_8G (0x00000004U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_10G (0x00000005U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_12G (0x00000006U) + + + +/* + * NV0073_CTRL_CMD_SPECIFIC_SET_MONITOR_POWER + * + * This command sets monitor power on/off. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId + * This parameter specifies the displayID for the display output resource to + * configure. + * powerState + * This parameter should be one of the valid + * NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_* values. + * headIdx + * The head id on which power operation needs to be done. + * bForceMonitorState + * Monitor power state that client wants to force in RM. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_SET_MONITOR_POWER (0x730295U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS_MESSAGE_ID (0x95U) + +typedef struct NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 powerState; + NvU32 headIdx; + NvBool bForceMonitorState; +} NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS; + +#define NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_OFF (0x00000000U) +#define NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_ON (0x00000001U) + + + +/* +* NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_CONFIG +* +* This command is used to perform HDMI FRL link training and enable FRL mode for +* the specified displayId. The link configuration will be returned after link +* training success. +* +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. +* displayID +* This parameter specifies the displayID for the display output resource to +* configure. +* data +* This parameter is an input and output to this command. +* Here are the current defined fields: +* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE +* This field specifies the desired setting for lane count. A client may +* choose any lane count as long as it does not exceed the capability of +* HDMI FRL sink as indicated in the sink capability field. +* The valid values for this field are: +* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_NONE +* For 0 lane configuration, link training is shut down (disable FRL). +* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_3G +* For FRL 3-lane configuration and 3 Gbps bandwidth per lane. +* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_6G +* For FRL 3-lane configuration and 6 Gbps bandwidth per lane. +* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_6G +* For FRL 4-lane configuration and 6 Gbps bandwidth per lane. +* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_8G +* For FRL 4-lane configuration and 8 Gbps bandwidth per lane. +* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_10G +* For FRL 4-lane configuration and 10 Gbps bandwidth per lane. +* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_12G +* For FRL 4-lane configuration and 12 Gbps bandwidth per lane. +* On return, the link bandwidth setting is returned which may be +* different from the requested input setting. +* bFakeLt +* This flag as input to this command. +* It indicates the FRL link training is a fake link training or not. +* TRUE if the FRL link training is fake and no real sink device attached. +* bLtSkipped +* The flag returned indicating whether link training is skipped or not. +* TRUE if link training is skipped due to the link config is not changed. +* bLinkAssessmentOnly +* The flag as input to this command. It indicates that the client is doing +* link training only for the link assessment, no FRL video transmission is +* intended. +* +* Possible status values returned include: +* NV_OK - +* Affter finishing link tranning, NV_OK status will be returned along with +* the updated link congiration. In case of link training failure, FRL_RATE_NONE +* will be returned with NV_OK. +* NV_ERR_NOT_SUPPORTED - +* If the GPU/sink is not capable for HDMI FRL, NV_ERR_NOT_SUPPORTED status +* will be returned. +* NV_ERR_INVALID_ARGUMENT +* If any argument is valid for this control call, NV_ERR_INVALID_ARGUMENT +* status will be returned. +*/ +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_CONFIG (0x73029aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS_MESSAGE_ID (0x9AU) + +typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 data; + NvBool bFakeLt; + NvBool bDoNotSkipLt; + NvBool bLtSkipped; + NvBool bLinkAssessmentOnly; +} NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS; + +#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE 2:0 +#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_NONE (0x00000000U) +#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_3G (0x00000001U) +#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_6G (0x00000002U) +#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_6G (0x00000003U) +#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_8G (0x00000004U) +#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_10G (0x00000005U) +#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_12G (0x00000006U) + +/* +* NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE +* +* This command is used to enable flush mode on given HDMI displayId in +* preparation for FRL link training. The flush mode can be enabled only if HDMI +* display is active and driven by FRL protocol. If display is not active then +* this control command does nothing. +* +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. +* displayID +* This parameter specifies the displayID for the display output resource to +* configure. +* bEnable +* This parameter is an inputto this command. +* +* Possible status values returned include: +* NV_OK +* NV_ERR_INVALID_ARGUMENT +* If any argument is invalid for this control call, NV_ERR_INVALID_ARGUMENT +* status will be returned. +*/ +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE (0x73029bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE_PARAMS_MESSAGE_ID (0x9BU) + +typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bEnable; +} NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE_PARAMS; + + + +#define NV0073_CTRL_SPECIFIC_MAX_CRC_REGIONS 9U + +#define NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS_PARAMS_MESSAGE_ID (0xA0U) + +typedef struct NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 regionCrcs[NV0073_CTRL_SPECIFIC_MAX_CRC_REGIONS]; + NvU16 reqRegionCrcMask; +} NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS + * + * This command is used to capture the active viewport region CRCs + * + * [in]subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * [in]displayId + * This parameter specifies the displayId of panel, for which region CRC to be captured +.* + * [out]regionCrcs + * This field holds the region CRC values to be returned after successful completion of the control command. + * + * [in]reqRegionCrcMask + * This parameter specifies BIT mask value of requested CRC regions. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS (0x7302a0U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS_PARAMS_MESSAGE_ID" */ + +/* +* NV0073_CTRL_CMD_SPECIFIC_APPLY_EDID_OVERRIDE_V2 +* +* Apply EDID override on specific OD. +* +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. +* displayId (in) +* ID of panel on which the operation is to be performed. +* bufferSize (in) +* Size of the EDID buffer. +* edidBuffer (in/out) +* The buffer which stores the EDID before and after override. +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_PARAMETER +*/ +#define NV0073_CTRL_CMD_SPECIFIC_APPLY_EDID_OVERRIDE_V2 (0x7302a1U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_APPLY_EDID_OVERRIDE_V2_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_APPLY_EDID_OVERRIDE_V2_PARAMS_MESSAGE_ID (0xA1U) + +typedef struct NV0073_CTRL_SPECIFIC_APPLY_EDID_OVERRIDE_V2_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 bufferSize; + NvU8 edidBuffer[NV0073_CTRL_SPECIFIC_GET_EDID_MAX_EDID_BYTES]; +} NV0073_CTRL_SPECIFIC_APPLY_EDID_OVERRIDE_V2_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS + * + * This command is used to get the HDMI FRL caps of GPU side. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * caps + * This parameter specifies the GPU caps. + * MAX_FRL_RATE_SUPPORTED refers to the maximum HDMI 2.1 FRL link rate supported + * + * + * Possible status values returned include: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS (0x7302a2U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_HDMI_GPU_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_GET_HDMI_GPU_CAPS_PARAMS_MESSAGE_ID (0xA2U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_HDMI_GPU_CAPS_PARAMS { + NvU32 subDeviceInstance; + NvU32 caps; +} NV0073_CTRL_SPECIFIC_GET_HDMI_GPU_CAPS_PARAMS; + +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED 2:0 +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_NONE (0x00000000U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_3LANES_3G (0x00000001U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_3LANES_6G (0x00000002U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_4LANES_6G (0x00000003U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_4LANES_8G (0x00000004U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_4LANES_10G (0x00000005U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_4LANES_12G (0x00000006U) + + + +/* + * NV0073_CTRL_CMD_SPECIFIC_DISPLAY_CHANGE + * + * Notifies the system that a display change is about to begin/end. + * Also performs the necessary synchronizations for the same. + * + * The command takes a NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS structure as an + * argument with appropriate subDeviceInstance. + * + * [in]subDeviceInstance + * The sub-device instance + * [in]newDevices + * Bitmask of devices that are planned on being enabled with the + * pending device change. + * [in]properties + * Bitmask of display attributes for new configuration (none used at the moment). + * [in]enable + * Parameter to decide between display change start and end. Can take values + * NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_START or NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_END. + * Possible return values: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + */ + +#define NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS_MESSAGE_ID (0xA4U) + +typedef struct NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS { + + NvU32 subDeviceInstance; + NvU32 newDevices; + NvU32 properties; + NvU32 enable; +} NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS; + +#define NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_END (0x00000000U) +#define NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_START (0x00000001U) + +#define NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PROPERTIES_SPANNING (0x00000001U) + +#define NV0073_CTRL_CMD_SPECIFIC_DISPLAY_CHANGE (0x7302a4U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS_MESSAGE_ID" */ + + + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA + * + * This command is used to get the HDMI sink status/caps via Status and Control + * Data Channel (SCDC). + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId + * This parameter specifies the displayId of HDMI sink. + * offset + * This parameter specifies the SCDC offset which the read operation + * should be used. + * data + * This field specifies the return data from sink for reading the specified + * SCDC offset. + * + * + * Possible status values returned include: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA (0x7302a6U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_HDMI_SCDC_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_GET_HDMI_SCDC_DATA_PARAMS_MESSAGE_ID (0xA6U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_HDMI_SCDC_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU8 offset; + NvU8 data; +} NV0073_CTRL_SPECIFIC_GET_HDMI_SCDC_DATA_PARAMS; + +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET 7:0 +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_NONE (0x00000000U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_SINK_VERSION (0x00000001U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_SOURCE_VERSION (0x00000002U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_UPDATE_FLAGS_0 (0x00000010U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_TMDS_CONFIGURATION (0x00000020U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_SCRAMBLER_STATUS (0x00000021U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CONFIGURATION_0 (0x00000030U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CONFIGURATION_1 (0x00000031U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_SOURCE_TEST_CONFIGURATION (0x00000035U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_STATUS_FLAGS_0 (0x00000040U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_STATUS_FLAGS_1 (0x00000041U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_STATUS_FLAGS_2 (0x00000042U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_0 (0x00000050U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_1 (0x00000051U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_2 (0x00000052U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_3 (0x00000053U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_4 (0x00000054U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_5 (0x00000055U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_6 (0x00000056U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_7 (0x00000057U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_8 (0x00000058U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_RSED_0 (0x00000059U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_RSED_1 (0x0000005AU) + +/* + * NV0073_CTRL_CMD_SPECIFIC_IS_DIRECTMODE_DISPLAY + * + * This command is used to query whether the specified monitor should be used + * with directmode. + * + * [in]manufacturerID + * This parameter specifies the 16-bit EDID Manufacturer ID. + * [in]productID + * This parameter specifies the 16-bit EDID Product ID. + * [out]bIsDirectmode; + * This indicates whether the monitor should be used with directmode. + * Possible return values: + * NV_OK + */ + +#define NV0073_CTRL_CMD_SPECIFIC_IS_DIRECTMODE_DISPLAY (0x7302a7U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_IS_DIRECTMODE_DISPLAY_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_IS_DIRECTMODE_DISPLAY_PARAMS_MESSAGE_ID (0xA7U) + +typedef struct NV0073_CTRL_SPECIFIC_IS_DIRECTMODE_DISPLAY_PARAMS { + NvU16 manufacturerID; + NvU16 productID; + NvBool bIsDirectmode; +} NV0073_CTRL_SPECIFIC_IS_DIRECTMODE_DISPLAY_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION + * + * This command is used to get the HDMI FRL capacity computation result. + * + * [in] cmd + * This parameter specifies the command for the HDMI FRL capacity computation. + * [in] input + * This parameter specifies the input data for the HDMI FRL capacity + * computation. + * [out] result + * This indicates the computation result of HDMI FRL capacity computation. + * [in/out] preCalc + * This indicates the pre-caculation result of HDMI FRL capacity computation. + * [in/out] dsc + * This indicates the DSC parameters of HDMI FRL capacity computation. + * Possible return values: + * NV_OK + */ + +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION (0x7302a8U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS_MESSAGE_ID" */ + +typedef struct NV0073_CTRL_FRL_CAPACITY_COMPUTATION_PARAMS { + NvU32 numLanes; + NvU32 frlBitRateGbps; + NvU32 pclk10KHz; + NvU32 hTotal; + NvU32 hActive; + NvU32 bpc; + NvU32 pixelPacking; + NvU32 audioType; + NvU32 numAudioChannels; + NvU32 audioFreqKHz; + + struct { + NvU32 bppTargetx16; + NvU32 hSlices; + NvU32 sliceWidth; + NvU32 dscTotalChunkKBytes; + } compressionInfo; +} NV0073_CTRL_FRL_CAPACITY_COMPUTATION_PARAMS; + +typedef struct NV0073_CTRL_FRL_CAPACITY_COMPUTATION_RESULT { + NvU32 frlRate; + NvU32 bppTargetx16; + NvBool engageCompression; + NvBool isAudioSupported; + NvBool dataFlowDisparityReqMet; + NvBool dataFlowMeteringReqMet; + NvBool isVideoTransportSupported; + NvU32 triBytesBorrowed; + NvU32 hcActiveBytes; + NvU32 hcActiveTriBytes; + NvU32 hcBlankTriBytes; + NvU32 tBlankToTTotalX1k; +} NV0073_CTRL_FRL_CAPACITY_COMPUTATION_RESULT; + +typedef struct NV0073_CTRL_FRL_PRE_CALC_CONFIG { + NvU32 vic; + NvU32 packing; + NvU32 bpc; + NvU32 frlRate; + NvU32 bppX16; + NvBool bHasPreCalcFRLData; +} NV0073_CTRL_FRL_PRE_CALC_CONFIG; + +typedef struct NV0073_CTRL_IS_FRL_DSC_POSSIBLE_PARAMS { + NvU32 maxSliceCount; + NvU32 maxSliceWidth; + NvBool bIsDSCPossible; +} NV0073_CTRL_IS_FRL_DSC_POSSIBLE_PARAMS; + +#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS_MESSAGE_ID (0xA8U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS { + NvU8 cmd; + NV0073_CTRL_FRL_CAPACITY_COMPUTATION_PARAMS input; + NV0073_CTRL_FRL_CAPACITY_COMPUTATION_RESULT result; + NV0073_CTRL_FRL_PRE_CALC_CONFIG preCalc; + NV0073_CTRL_IS_FRL_DSC_POSSIBLE_PARAMS dsc; +} NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS; + +#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_NULL (0x00000000U) +#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_UNCOMPRESSED_VIDEO (0x00000001U) +#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_COMPRESSED_VIDEO (0x00000002U) +#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_HAS_PRECAL_FRL_DATA (0x00000003U) +#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_GET_PRECAL_UNCOMPRESSED_FRL_CONFIG (0x00000004U) +#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_GET_PRECAL_COMPRESSED_FRL_CONFIG (0x00000005U) +#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_IS_FRL_DSC_POSSIBLE (0x00000006U) + +/* + * NV0073_CTRL_CMD_SPECIFIC_SET_SHARED_GENERIC_PACKET + * + * This command is used to program the display output packets. + * This generic packets can be used for both HDMI and DP. + * HW has added 6 new generic packets for each head because some usecases have + * requirement to send infoframe in particular location (vsync, vblank, loadV). + * + * Note: 1. Client first needs to reserve or acquire a free infoframe index + * using NV0073_CTRL_CMD_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET. + * 2. Client needs to update the SDP index for head through control call + * NV0073_CTRL_CMD_SPECIFIC_SET_SHARED_GENERIC_PACKET + * 3. Client needs to Release the infoframe index using control call + * NV0073_CTRL_CMD_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET + * + * [in]subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * [in]transmitControl + * This parameter controls how the packet is to be sent by setting the + * control bits. + * Possible flags are as follows: + * NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_ENABLE + * Setting this field to _YES will enable this generic infoframe, + * Setting this field to _NO will disable this generic infoframe. + * NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_SINGLE + * Set to _YES will cause new infoframe to be transmitted exactly once. + * Set to _NO will cause new infoframe to be transmitted every frame. + * NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_LOC + * SDP can be sent in 3 different locations: + * VBLANK - new infoframe will be sent at Vblank. + * VSYNC - new infoframe will be sent at Vsync. + * LOADV - new infoframe will be triggered by LOADV, and sent at Vsync + * NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_UPDATE_RFB_OVERRIDE + * _ENABLE: override DB1 bit1 with existence of loadv (for Panel Self Refresh) + * _DISABLE: do not override shared generic infoframe subpacker DB1 bit1. + * NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_SU_COORDINATES_VALID_OVERRIDE + * _ENABLE: override DB1 bit3 with existence of loadv (for Panel Replay) + * _DISABLE: do not override shared generic infoframe subpacker DB1 bit3. + * [in]packetSize + * size of packets in Packet array to send, including header and payload. + * [in]infoframeIndex + * Specifies the target head number for which SDP needs to be updated. + * [in]infoframeIndex + * Specifies the index of infoframe. + * [in]packet + * pPacket points to the packets to send. + * For HDMI 1.1, the maximum allowed bytes is 31. + * The packet array includes the 3 bytes of header + data depending on + * the type of packet. For an infoframe, the header bytes refer to type, + * version and length respectively. This comes as input to this command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SPECIFIC_SET_SHARED_GENERIC_PACKET (0x7302a9) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_SHARED_GENERIC_PACKET_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_SHARED_GENERIC_PACKET_PARAMS_MESSAGE_ID (0xA9U) + +typedef struct NV0073_CTRL_SPECIFIC_SET_SHARED_GENERIC_PACKET_PARAMS { + NvU32 subDeviceInstance; + NvU32 transmitControl; + NvU32 packetSize; + NvU32 targetHeadIndex; + NvU32 infoframeIndex; + NvU8 packet[NV0073_CTRL_SET_OD_MAX_PACKET_SIZE]; +} NV0073_CTRL_SPECIFIC_SET_SHARED_GENERIC_PACKET_PARAMS; + +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_ENABLE 0:0 +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_ENABLE_NO (0x0000000) +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_ENABLE_YES (0x0000001) + +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_SINGLE 1:1 +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_SINGLE_NO (0x0000000) +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_SINGLE_YES (0x0000001) + +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_LOC 5:2 +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_LOC_VBLANK (0x0000000) +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_LOC_VSYNC (0x0000001) +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_LOC_LOADV (0x0000002) + +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_STATE_OVERRIDE 6:6 +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_STATE_OVERRIDE_DISABLE (0x0000000) +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_STATE_OVERRIDE_ENABLE (0x0000001) + +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_UPDATE_RFB_OVERRIDE 7:7 +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_UPDATE_RFB_OVERRIDE_DISABLE (0x0000000) +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_UPDATE_RFB_OVERRIDE_ENABLE (0x0000001) + +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_SU_COORDINATES_VALID_OVERRIDE 8:8 +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_SU_COORDINATES_VALID_OVERRIDE_DISABLE (0x0000000) +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_SU_COORDINATES_VALID_OVERRIDE_ENABLE (0x0000001) + +/* + * NV0073_CTRL_CMD_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET + * + * This command is used to reserve the infoframe for head and RM would assign + * free infoframe index and return the index of infoframe. Later client needs + * to call control call NV0073_CTRL_CMD_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET + * to release the index. + * + * [in]subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * [in]targetHeadIndex + * target Head for which SDP needs to be sent + * [out]infoframeIndex + * return Infoframe Index for head. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFIENT_RESOURCES + */ + +#define NV0073_CTRL_CMD_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET (0x7302aa) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET_PARAMS_MESSAGE_ID (0xAAU) + +typedef struct NV0073_CTRL_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET_PARAMS { + NvU32 subDeviceInstance; + NvU32 targetHeadIndex; + NvU32 infoframeIndex; +} NV0073_CTRL_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET + * + * This command is used to release the infoframe index which was acquired by + * client. + * + * [in]subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * [in]targetHeadIndex + * Specifies the target head number for which SDP needs to be updated. + * [in]infoframeIndex + * Infoframe index for the target head + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET (0x7302ab) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET_PARAMS_MESSAGE_ID (0xABU) + +typedef struct NV0073_CTRL_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET_PARAMS { + NvU32 subDeviceInstance; + NvU32 targetHeadIndex; + NvU32 infoframeIndex; +} NV0073_CTRL_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_DISP_I2C_READ_WRITE + * + * This command is used to do I2C R/W to slave on display i2c instance. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * i2cPort + * This parameter specifies the I2C CCB port ID. + * i2cSlaveAddress + * This parameter specifies the I2C slave address. + * readWriteFlag + * This parameter specifies whether its read/write operation. + * readWriteLen + * This parameter specifies the length of the read/write buffer + * readBuffer + * This parameter reads the data from slave address and copies to this + * buffer + * writeBuffer + * This parameter specifies this buffer data that would be written to + * slave address + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SPECIFIC_DISP_I2C_READ_WRITE (0x7302acU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_BUF_LEN 128U + +#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS_MESSAGE_ID (0xACU) + +typedef struct NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS { + NvU32 subDeviceInstance; + NvU32 i2cPort; + NvU32 i2cSlaveAddress; + NvU32 readWriteFlag; + NvU32 readWriteLen; + NvU8 readBuffer[NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_BUF_LEN]; + NvU8 writeBuffer[NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_BUF_LEN]; +} NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS; + +#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_MODE (0x00000001) +#define NV0073_CTRL_SPECIFIC_DISP_I2C_WRITE_MODE (0x00000000) + +/* + * NV0073_CTRL_CMD_GET_VALID_HEAD_WINDOW_ASSIGNMENT + * + * This command returns the valid window head assignment mask + * + * windowHeadMask [out] + * This out parameter is an array which holds the head mask for + * each window. The Nth element in the array would be a bitmask + * of which heads can possibly drive window N. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT (0x7302ad) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_MAX_WINDOWS 32U +#define NV0073_CTRL_SPECIFIC_FLEXIBLE_HEAD_WINDOW_ASSIGNMENT (0xFFU) + +#define NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS_MESSAGE_ID (0xADU) + +typedef struct NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS { + NvU32 subDeviceInstance; + NvU8 windowHeadMask[NV0073_CTRL_SPECIFIC_MAX_WINDOWS]; +} NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY + * + * This command is used to query whether the specified monitor should default + * to adaptive sync. + * + * [in]manufacturerID + * This parameter specifies the 16-bit EDID Manufacturer ID. + * [in]productID + * This parameter specifies the 16-bit EDID Product ID. + * [out]bDefaultAdaptivesync; + * This indicates whether the monitor should default to adaptive sync. + * Possible return values: + * NV_OK + */ + +#define NV0073_CTRL_CMD_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY (0x7302aeU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS_MESSAGE_ID (0xAEU) + +typedef struct NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS { + NvU16 manufacturerID; + NvU16 productID; + NvBool bDefaultAdaptivesync; +} NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_DISPLAY_BRIGHTNESS_LTM + * NV0073_CTRL_CMD_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM + * These commands retrieve and set the brightness level and Local Tone Mapping (LTM) settings for + * the specified display. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * + * displayId + * Display for which brightness/LTM settings is to be retrieved or set. + * + * brightnessMilliNits + * the display brightness in the millinits units in the [0,10000000] range, inclusive. + * + * transitionTimeMs + * the transition time for display brightness to transition from current brightness level to the brightnessMilliNits + * + * bUncalibrated + * if true the parameter indicates brightnessMilliNits has to be interpreted as brightness % value, in 0.001% units + * + * bAdaptiveBrightness + * if true the brightnessMilliNits is set by the OS in the response to the ambient light sensor (ALS) input (if present on the system) + * + * bBoostRange + * if true the brightnessMilliNits value is set by the OS in the response to the ambient light sensor (ALS) input (if present on the system) + * Indicating very bright ambient light environment + * + * ambientIlluminance + * if bAdaptiveBrightness = true, ambientIlluminance represents an ambient illuminance value reported by the ALS sensor, in 0.001 Lux units + * + * ambientChromaticityX + * if bAdaptiveBrightness = true, ambientChromaticityX represents X chromaticity value reported by ALS sensor, in 0.001 units of [0,1] range + * + * ambientChromaticityY + * if bAdaptiveBrightness = true, ambientChromaticityY represents Y chromaticity value reported by ALS sensor, in 0.001 units of [0,1] range + * + * bLtmEnable + * if set to true, enable LTM functionality in GPU display HW. Set to true by default. + * + * bEnhanceContrast + * if bLtmEnable = true, and if set to true, enhance local contrast via LTM regardless of any other contrast enhancement driver policies. Set to false by default. + * + * contrastGain + * if bLtmEnable = true, this is used to how gain we need to apply on the contrast. + * + * detailGain + * if bLtmEnable = true, how much details needs to be boosted is indicated by this parameter. + * + * bContentAdaptiveBrightness + * if bLtmEnable = true, and if set to true, modify display backlight level and adjust pixel values dynamically on per-frame basis to perform content adaptive brightness control to reduce display power. Set to false by default. + * + * bDynamicHdrTonemapping + * if bLtmEnable = true, and if set to true, and output is HDR, enable dynamic per frame HDR tonemapping. Set to false by default. + * + * maxDisplayLuminance + * maximum display luminance + * + * maxOutputLuminance + * maximum output luminance considering the protocol limit (SDR/HDR) and maximum display luminance. + * + * luminanceSscalingFactor + * HDR tone mapping luminance scaling factor + * + * Possible status values returned include: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +typedef struct NV0073_CTRL_SPECIFIC_DISPLAY_BRIGHTNESS_LTM_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 brightnessMilliNits; + NvU32 transitionTimeMs; + NvBool bUncalibrated; + NvBool bAdaptiveBrightness; + NvBool bBoostRange; + NvU32 ambientIlluminance; + NvU32 ambientChromaticityX; + NvU32 ambientChromaticityY; + NvBool bEnhanceContrast; + NvU16 contrastGain; + NvU16 detailGain; + NvBool bContentAdaptiveBrightness; + NvBool bDynamicHdrTonemapping; + NvU32 maxDisplayLuminance; + NvU32 maxOutputLuminance; + NvU32 luminanceScalingFactor; +} NV0073_CTRL_SPECIFIC_DISPLAY_BRIGHTNESS_LTM_PARAMS; + +#define NV0073_CTRL_SPECIFIC_GET_DISPLAY_BRIGHTNESS_LTM_PARAMS_MESSAGE_ID (0xAFU) + +typedef NV0073_CTRL_SPECIFIC_DISPLAY_BRIGHTNESS_LTM_PARAMS NV0073_CTRL_SPECIFIC_GET_DISPLAY_BRIGHTNESS_LTM_PARAMS; + +#define NV0073_CTRL_CMD_SPECIFIC_GET_DISPLAY_BRIGHTNESS_LTM (0x7302afU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_DISPLAY_BRIGHTNESS_LTM_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM_PARAMS_MESSAGE_ID (0xB0U) + +typedef NV0073_CTRL_SPECIFIC_DISPLAY_BRIGHTNESS_LTM_PARAMS NV0073_CTRL_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM_PARAMS; + +#define NV0073_CTRL_CMD_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM (0x7302b0U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM_PARAMS_MESSAGE_ID" */ + +/* +* NV0073_CTRL_CMD_GET_REGISTER_OFFSET_FOR_ULMB_TIMESTAMP +* +* The command returns the offset of the disp registers for sending timestamp +* directly to RISCV, so that clients may map them directly and write to this +* register which will trigger interrupt in RISCV. +* +* Possible status values returned are: +* NV_OK +* NV_ERR_NOT_SUPPORTED +*/ + +#define NV0073_CTRL_CMD_GET_REGISTER_OFFSET_FOR_ULMB_TIMESTAMP (0x7302b1U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_GET_REGISTER_OFFSET_FOR_ULMB_TIMESTAMP_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_GET_REGISTER_OFFSET_FOR_ULMB_TIMESTAMP_PARAMS_MESSAGE_ID (0xB1U) + +typedef struct NV0073_CTRL_GET_REGISTER_OFFSET_FOR_ULMB_TIMESTAMP_PARAMS { + NvU32 subDeviceInstance; + NvU32 dispRegisterBase; +} NV0073_CTRL_GET_REGISTER_OFFSET_FOR_ULMB_TIMESTAMP_PARAMS; +/* _ctrl0073specific_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073stereo.h b/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073stereo.h new file mode 100644 index 0000000..7029743 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073stereo.h @@ -0,0 +1,201 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073stereo.finn +// + +#include "ctrl/ctrl0073/ctrl0073base.h" + + + +/* + * NV0073_CTRL_CMD_STEREO_DONGLE_SUPPORTED + * + * This command returns the support status of the NV stereo emitter + * (also known as the stereo dongle). It reports if the stereo dongle + * is present in terms of the USB interface initialized in Resman. + * This provides a RmControl interface to the STEREO_DONGLE_SUPPORTED + * command in stereoDongleControl. + * + * Parameters: + * [IN] subDeviceInstance - This parameter specifies the subdevice instance + * within the NV04_DISPLAY_COMMON parent device to which the operation + * should be directed. This parameter must specify a value between + * zero and the total number of subdevices within the parent device. + * This parameter should be set to zero for default behavior. + * [IN] head - head to be passed to stereoDongleControl + * [IN] bI2cEmitter - I2C driven DT embedded emitter + * [IN] bForcedSupported - GPIO23 driven emitter + * [OUT] support - the control word returned by stereoDongleControl + * + * Possible status values returned are: + * NV_ERR_NOT_SUPPORTED - stereo is not initialized on the GPU + */ +#define NV0073_CTRL_CMD_STEREO_DONGLE_SUPPORTED (0x731702U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID << 8) | NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvBool bI2cEmitter; + NvBool bForcedSupported; + NvU32 support; +} NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS; + +/* + * NV0073_CTRL_CMD_STEREO_DONGLE_SET_TIMINGS + * + * Sets new video mode timings + * E.g. from display driver on mode set + * + * Parameters: + * [IN] subDeviceInstance - This parameter specifies the subdevice instance + * within the NV04_DISPLAY_COMMON parent device to which the operation + * should be directed. This parameter must specify a value between + * zero and the total number of subdevices within the parent device. + * This parameter should be set to zero for default behavior. + * [IN] head - head to be passed to stereoDongleControl + * [IN] timings - new timings to be set + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED - stereo is not initialized on the GPU + */ +#define NV0073_CTRL_CMD_STEREO_DONGLE_SET_TIMINGS (0x731703U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID << 8) | NV0073_CTRL_STEREO_DONGLE_SET_TIMINGS_PARAMS_MESSAGE_ID" */ + +typedef struct NV0073_CTRL_STEREO_VIDEO_MODE_TIMINGS { + NvU32 PixelClock; + NvU16 TotalWidth; + NvU16 VisibleImageWidth; + NvU16 HorizontalBlankStart; + NvU16 HorizontalBlankWidth; + NvU16 HorizontalSyncStart; + NvU16 HorizontalSyncWidth; + NvU16 TotalHeight; + NvU16 VisibleImageHeight; + NvU16 VerticalBlankStart; + NvU16 VerticalBlankHeight; + NvU16 VerticalSyncStart; + NvU16 VerticalSyncHeight; + NvU16 InterlacedMode; + NvU16 DoubleScanMode; + + NvU16 MonitorVendorId; + NvU16 MonitorProductId; +} NV0073_CTRL_STEREO_VIDEO_MODE_TIMINGS; + +#define NV0073_CTRL_STEREO_DONGLE_SET_TIMINGS_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0073_CTRL_STEREO_DONGLE_SET_TIMINGS_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NV0073_CTRL_STEREO_VIDEO_MODE_TIMINGS timings; +} NV0073_CTRL_STEREO_DONGLE_SET_TIMINGS_PARAMS; + +/* + * NV0073_CTRL_CMD_STEREO_DONGLE_ACTIVATE + * + * stereoDongleActivate wrapper / NV_STEREO_DONGLE_ACTIVATE_DATA_ACTIVE_YES + * Updates sbios of 3D stereo state active + * + * Parameters: + * [IN] subDeviceInstance - This parameter specifies the subdevice instance + * within the NV04_DISPLAY_COMMON parent device to which the operation + * should be directed. This parameter must specify a value between + * zero and the total number of subdevices within the parent device. + * This parameter should be set to zero for default behavior. + * [IN] head - head to be passed to stereoDongleActivate + * [IN] bSDA - enable stereo on DDC SDA + * [IN] bWorkStation - is workstation stereo? + * [IN] bDLP - is checkerboard DLP Stereo? + * [IN] IRPower - IR power value + * [IN] flywheel - FlyWheel value + * [IN] bRegIgnore - use reg? + * [IN] bI2cEmitter - Sets NV_STEREO_DONGLE_ACTVATE_DATA_I2C_EMITTER_YES and pStereo->bAegisDT + * [IN] bForcedSupported - Sets NV_STEREO_DONGLE_FORCED_SUPPORTED_YES and pStereo->GPIOControlledDongle + * [IN] bInfoFrame - Aegis DT with DP InfoFrame + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT - if (head > OBJ_MAX_HEADS) + * NV_ERR_NOT_SUPPORTED - stereo is not initialized on the GPU + */ +#define NV0073_CTRL_CMD_STEREO_DONGLE_ACTIVATE (0x731704U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID << 8) | NV0073_CTRL_STEREO_DONGLE_ACTIVATE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_STEREO_DONGLE_ACTIVATE_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0073_CTRL_STEREO_DONGLE_ACTIVATE_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvBool bSDA; + NvBool bWorkStation; + NvBool bDLP; + NvU8 IRPower; + NvU8 flywheel; + NvBool bRegIgnore; + NvBool bI2cEmitter; + NvBool bForcedSupported; + NvBool bInfoFrame; +} NV0073_CTRL_STEREO_DONGLE_ACTIVATE_PARAMS; + +/* + * NV0073_CTRL_CMD_STEREO_DONGLE_DEACTIVATE + * + * stereoDongleActivate wrapper / NV_STEREO_DONGLE_ACTIVATE_DATA_ACTIVE_NO + * + * If active count<=0 then no 3D app is running which indicates + * that we have really deactivated the stereo, updates sbios of 3D stereo state NOT ACTIVE. + * + * Parameters: + * [IN] subDeviceInstance - This parameter specifies the subdevice instance + * within the NV04_DISPLAY_COMMON parent device to which the operation + * should be directed. This parameter must specify a value between + * zero and the total number of subdevices within the parent device. + * This parameter should be set to zero for default behavior. + * [IN] head - head to be passed to stereoDongleActivate + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT - if (head > OBJ_MAX_HEADS) + * NV_ERR_NOT_SUPPORTED - stereo is not initialized on the GPU + */ +#define NV0073_CTRL_CMD_STEREO_DONGLE_DEACTIVATE (0x731705U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID << 8) | NV0073_CTRL_STEREO_DONGLE_DEACTIVATE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_STEREO_DONGLE_DEACTIVATE_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0073_CTRL_STEREO_DONGLE_DEACTIVATE_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; +} NV0073_CTRL_STEREO_DONGLE_DEACTIVATE_PARAMS; + + + +/* _ctrl0073stereo_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073svp.h b/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073svp.h new file mode 100644 index 0000000..d4375a0 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073svp.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073svp.finn +// + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073system.h b/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073system.h new file mode 100644 index 0000000..04a75db --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0073/ctrl0073system.h @@ -0,0 +1,2697 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073system.finn +// + +#include "nvlimits.h" +#include "ctrl/ctrl0073/ctrl0073base.h" + +/* NV04_DISPLAY_COMMON system-level control commands and parameters */ + +/* extract cap bit setting from tbl */ +#define NV0073_CTRL_SYSTEM_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* Caps format is byte_index:bit_mask. + * Important: keep the number of bytes needed for these fields in sync with + * NV0073_CTRL_SYSTEM_CAPS_TBL_SIZE + */ +#define NV0073_CTRL_SYSTEM_CAPS_AA_FOS_GAMMA_COMP_SUPPORTED 0:0x01 +#define NV0073_CTRL_SYSTEM_CAPS_TV_LOWRES_BUG_85919 0:0x02 +#define NV0073_CTRL_SYSTEM_CAPS_DFP_GPU_SCALING_BUG_154102 0:0x04 +#define NV0073_CTRL_SYSTEM_CAPS_SLI_INTERLACED_MODE_BUG_235218 0:0x08 // Deprecated +#define NV0073_CTRL_SYSTEM_CAPS_STEREO_DIN_AVAILABLE 0:0x10 +#define NV0073_CTRL_SYSTEM_CAPS_OFFSET_PCLK_DFP_FOR_EMI_BUG_443891 0:0x20 +#define NV0073_CTRL_SYSTEM_CAPS_GET_DMI_SCANLINE_SUPPORTED 0:0x40 +/* + * Indicates support for HDCP Key Selection Vector (KSV) list and System + * Renewability Message (SRM) validation +*/ +#define NV0073_CTRL_SYSTEM_CAPS_KSV_SRM_VALIDATION_SUPPORTED 0:0x80 + +#define NV0073_CTRL_SYSTEM_CAPS_SINGLE_HEAD_MST_SUPPORTED 1:0x01 +#define NV0073_CTRL_SYSTEM_CAPS_SINGLE_HEAD_DUAL_SST_SUPPORTED 1:0x02 +#define NV0073_CTRL_SYSTEM_CAPS_HDMI_2_0_SUPPORTED 1:0x04 +#define NV0073_CTRL_SYSTEM_CAPS_CROSS_BAR_SUPPORTED 1:0x08 +#define NV0073_CTRL_SYSTEM_CAPS_RASTER_LOCK_NEEDS_MIO_POWER 1:0x10 +/* + * Indicates that modesets where no heads are increasing resource requirements, + * or no heads are decreasing resource requirements, can be done glitchlessly. + */ +#define NV0073_CTRL_SYSTEM_CAPS_GLITCHLESS_MODESET_SUPPORTED 1:0x20 +/* Indicates the SW ACR is enabled for HDMI 2.1 due to Bug 3275257. */ +#define NV0073_CTRL_SYSTEM_CAPS_HDMI21_SW_ACR_BUG_3275257 1:0x40 + +/* Size in bytes of display caps table. Keep in sync with # of fields above. */ +#define NV0073_CTRL_SYSTEM_CAPS_TBL_SIZE 2U + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_CAPS_V2 + * + * This command returns the set of display capabilities for the parent device + * in the form of an array of unsigned bytes. Display capabilities + * include supported features and required workarounds for the display + * engine(s) within the device, each represented by a byte offset into the + * table and a bit position within that byte. The set of display capabilities + * will be normalized across all GPUs within the device (a feature capability + * will be set only if it's supported on all GPUs while a required workaround + * capability will be set if any of the GPUs require it). + * + * [out] capsTbl + * The display caps bits will be transferred by the RM into this array of + * unsigned bytes. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_CAPS_V2 (0x730101U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x01U) + +typedef struct NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS { + NvU8 capsTbl[NV0073_CTRL_SYSTEM_CAPS_TBL_SIZE]; +} NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_NUM_HEADS + * + * This commands returns the number of heads supported by the specified + * subdevice and available for use by displays. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * flags + * This parameter specifies optional flags to be used to while retrieving + * the number of heads. + * Possible valid flags are: + * NV0073_CTRL_SYSTEM_GET_NUM_HEADS_CLIENT + * This flag is used to request the number of heads that are + * currently in use by an NV client using a user display class + * instance (see NV15_VIDEO_LUT_CURSOR_DAC for an examle). If this + * flag is disabled then the total number of heads supported is + * returned. + * numHeads + * This parameter returns the number of usable heads for the specified + * subdevice. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_NUM_HEADS (0x730102U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS_MESSAGE_ID (0x02U) + +typedef struct NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS { + NvU32 subDeviceInstance; + NvU32 flags; + NvU32 numHeads; +} NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS; + +/* valid get num heads flags */ +#define NV0073_CTRL_SYSTEM_GET_NUM_HEADS_FLAGS_CLIENT 0:0 +#define NV0073_CTRL_SYSTEM_GET_NUM_HEADS_FLAGS_CLIENT_DISABLE (0x00000000U) +#define NV0073_CTRL_SYSTEM_GET_NUM_HEADS_FLAGS_CLIENT_ENABLE (0x00000001U) + + + + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_SCANLINE + * + * This command returns the current RG scanline of the specified head on the + * specified subdevice. To get the DMI scanline on supported chips, use + * NV0073_CTRL_CMD_SYSTEM_GET_DMI_SCANLINE + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * head + * This parameter specifies the head for which the active display + * should be retrieved. This value must be between zero and the + * maximum number of heads supported by the subdevice. + * currentScanline + * This parameter returns the current RG scanline value for the specified + * head. If the head does not have a valid mode enabled then a scanline + * value of 0xffffffff is returned. + * bStereoEyeSupported (out) + * This parameter specifies whether stereoEye reporting is supported (this + * is hw dependent). Note that this value doesn't actually reflect whether + * given head is really in stereo mode. + * stereoEye (out) + * If supported (ie bStereoEyeSupported is TRUE), this parameter returns + * either NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS_RIGHT_EYE or + * NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS_LEFT_EYE, reflecting the + * stereo eye that is currently scanned out. Although this value typically + * changes at the beginning of vblank, the exact guarantee isn't more + * accurate than "somewhere in vblank". + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_SCANLINE (0x730104U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_GET_SCANLINE_RIGHT_EYE 0x00000000U +#define NV0073_CTRL_CMD_SYSTEM_GET_SCANLINE_LEFT_EYE 0x00000001U + +#define NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS_MESSAGE_ID (0x04U) + +typedef struct NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvU32 currentScanline; + NvBool bStereoEyeSupported; + NvU32 stereoEye; +} NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_VBLANK_COUNTER + * + * This command returns the current VBlank counter of the specified head on the + * specified subdevice. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * head + * This parameter specifies the head for which the vblank counter + * should be retrieved. This value must be between zero and the + * maximum number of heads supported by the subdevice. + * lowLatencyHint + * RM maintains several different vblank counts. When this parameter is + * NV_TRUE, the command may return the low latency count. + * verticalBlankCounter + * This parameter returns the vblank counter value for the specified + * head. If the display mode is not valid or vblank not active then + * the verticalBlankCounter value is undefined. + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_VBLANK_COUNTER (0x730105U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS_MESSAGE_ID (0x05U) + +typedef struct NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvBool lowLatencyHint; + NvU32 verticalBlankCounter; +} NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_VBLANK_ENABLE + * + * This command returns the current VBlank enable status for the specified + * head. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * head + * This parameter specifies the head for which the vblank status + * should be retrieved. This value must be between zero and the + * maximum number of heads supported by the subdevice. + * bEnabled + * This parameter returns the vblank enable status for the specified head. + * A value of NV_FALSE indicates that vblank interrupts are not currently + * enabled while a value of NV_TRUE indicates that vblank are currently + * enabled. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_VBLANK_ENABLE (0x730106U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS_MESSAGE_ID (0x06U) + +typedef struct NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvBool bEnabled; +} NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED + * + * This command returns the set of supported display IDs for the specified + * subdevice in the form of a 32bit display mask. State from internal + * display connectivity tables is used to determine the set of possible + * display connections for the GPU. The presence of a display in the + * display mask only indicates the display is supported. The connectivity + * status of the display should be determined using the + * NV0073_CTRL_CMD_SYSTEM_GET_CONNECT_STATE command. The displayMask + * value returned by NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED is static + * and will remain consistent across boots of the system. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayMask + * This parameter returns a NV0073_DISPLAY_MASK value describing the set + * of displays supported by the subdevice. An enabled bit in displayMask + * indicates the support of a display device with that displayId. + * displayMaskDDC + * This parameter returns a NV0073_DISPLAY_MASK value, indicating the + * subset of displayMask that supports DDC. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED (0x730107U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS_MESSAGE_ID (0x07U) + +typedef struct NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayMask; + NvU32 displayMaskDDC; +} NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_CONNECT_STATE + * + * This command can be used to check the presence of a mask of display + * devices on the specified subdevice. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * flags + * This parameter specifies optional flags to be used while retrieving + * the connection state information. + * Here are the current defined fields: + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD + * A client uses this field to indicate what method it wishes the + * system to use when determining the presence of attached displays. + * Possible values are: + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD_DEFAULT + * The system decides what method to use. + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD_CACHED + * Return the last full detection state for the display mask. + * safety.) + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD_ECONODDC + * Ping the DDC address of the given display mask to check for + * a connected device. This is a lightweight method to check + * for a present device. + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_DDC + * A client uses this field to indicate whether to allow DDC during + * this detection or to not use it. + * Possible values are: + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_DDC_DEFAULT + * The system will use DDC as needed for each display. + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_DDC_DISABLE + * The system will not use DDC for any display. If DDC is + * disabled, this detection state will not be cached. + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_LOAD + * A client uses this field to indicate whether to detect loads + * during this detection or to not use it. + * Possible values are: + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_LOAD_DEFAULT + * The system will use load detection as needed for each display. + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_LOAD_DISABLE + * The system will not use load detection for any display. If + * load detection is disabled, this detection state will not + * be cached. + * displayMask + * This parameter specifies an NV0073_DISPLAY_MASK value describing + * the set of displays for which connectivity status is to be checked. + * If a display is present then the corresponding bit in the display + * mask is left enabled. If the display is not present then the + * corresponding bit in the display mask is disabled. Upon return this + * parameter contains the subset of displays in the mask that are + * connected. + * + * If displayMask includes bit(s) that correspond to a TV encoder, the + * result will be simply 'yes' or 'no' without any indication of which + * connector(s) are actually attached. For fine-grained TV attachment + * detection, please see NV0073_CTRL_CMD_TV_GET_ATTACHMENT_STATUS. + * retryTimeMs + * This parameter is an output to this command. In case of + * NVOS_STATUS_ERROR_RETRY return status, this parameter returns the time + * duration in milli-seconds after which client should retry this command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_ERROR_RETRY + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_CONNECT_STATE (0x730108U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS_MESSAGE_ID (0x08U) + +typedef struct NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS { + NvU32 subDeviceInstance; + NvU32 flags; + NvU32 displayMask; + NvU32 retryTimeMs; +} NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS; + +/* valid get connect state flags */ +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD 1:0 +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD_DEFAULT (0x00000000U) +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD_CACHED (0x00000001U) +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD_ECONODDC (0x00000002U) +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_DDC 4:4 +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_DDC_DEFAULT (0x00000000U) +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_DDC_DISABLE (0x00000001U) +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_LOAD 5:5 +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_LOAD_DEFAULT (0x00000000U) +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_LOAD_DISABLE (0x00000001U) +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_VBLANK 6:6 +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_VBLANK_DEFAULT (0x00000000U) +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_VBLANK_SAFE (0x00000001U) + + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_CONFIG + * + * This command can be used to retrieve dynamic hotplug state information that + * are currently recorded by the RM. This information can be used by the client + * to determine which displays to detect after a hotplug event occurs. Or if + * the client knows that this device generates a hot plug/unplug signal on all + * connectors, then this can be used to cull displays from detection. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * flags + * This parameter specifies optional flags to be used while retrieving + * or changing the hotplug configuration. + * No flags are currently defined. + * hotplugEventMask + * For _GET_HOTPLUG_CONFIG, this returns which connectors the client + * has asked for notifications for, when a hotplug event is detected. + * Events can only be provided for connectors whose displayID is set + * by the system in the hotplugInterruptible field. + * hotplugPollable + * For _GET_HOTPLUG_CONFIG, this returns which connectors are pollable + * in some non-destructive fashion. + * hotplugInterruptible + * For _GET_HOTPLUG_CONFIG, this returns which connectors are capable + * of generating interrupts. + * + * This display mask specifies an NV0073_DISPLAY_MASK value describing + * the set of displays that have seen a hotplug or hotunplug event + * sometime after the last valid EDID read. If the device never has + * a valid EDID read, then it will always be listed here. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + + +#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_CONFIG (0x730109U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS_MESSAGE_ID (0x09U) + +typedef struct NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS { + NvU32 subDeviceInstance; + NvU32 flags; + NvU32 hotplugEventMask; + NvU32 hotplugPollable; + NvU32 hotplugInterruptible; + NvU32 hotplugAlwaysAttached; +} NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_STATE + * + * This command can be used to retrieve dynamic hotplug state information that + * are currently recorded by the RM. This information can be used by the client + * to determine which displays to detect after a hotplug event occurs. Or if + * the client knows that this device generates a hot plug/unplug signal on all + * connectors, then this can be used to cull displays from detection. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * flags + * This parameter specifies optional flags to be used while retrieving + * the hotplug state information. + * Here are the current defined fields: + * NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID + * A client uses this field to determine the lid state. + * Possible values are: + * NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID_OPEN + * The lid is open. + * NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID_CLOSED + * The lid is closed. The client should remove devices as + * reported inside the + * NV0073_CTRL_SYSTEM_GET_CONNECT_POLICY_PARAMS.lidClosedMask. + * hotplugAfterEdidMask + * This display mask specifies an NV0073_DISPLAY_MASK value describing + * the set of displays that have seen a hotplug or hotunplug event + * sometime after the last valid EDID read. If the device never has + * a valid EDID read, then it will always be listed here. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + + +#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_STATE (0x73010aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS_MESSAGE_ID (0x0AU) + +typedef struct NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS { + NvU32 subDeviceInstance; + NvU32 flags; + NvU32 hotplugAfterEdidMask; +} NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS; + +/* valid get hoplug state flags */ +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID 0:0 +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID_OPEN (0x00000000U) +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID_CLOSED (0x00000001U) + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_HEAD_ROUTING_MAP + * + * This command can be used to retrieve the suggested head routing map + * for the specified display mask. A head routing map describes the + * suggested crtc (or head) assignments for each display in the specified + * mask. + * + * Up to MAX_DISPLAYS displays may be specified in the display mask. Displays + * are numbered from zero beginning with the lowest bit position set in the + * mask. The corresponding head assignment for each of specified displays can + * then be found in the respective per-device field in the routing map. + * + * If a particular display cannot be successfully assigned a position in the + * head routing map then it is removed from the display mask. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayMask + * This parameter specifies the NV0073_DISPLAY_MASK value for which + * the head routing map is desired. Each enabled bit indicates + * a display device to include in the routing map. Enabled bits + * must represent supported displays as indicated by the + * NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED command. If a particular + * display cannot be included in the routing map then it's corresponding + * bit in the displayMask will be disabled. A return value of 0 in + * displayMask indicates that a head routing map could not be constructed + * with the given display devices. + * oldDisplayMask + * This optional parameter specifies a prior display mask to be + * used when generating the head routing map to be returned in + * headRoutingMap. Displays set in oldDisplayMask are retained + * if possible in the new routing map. + * oldHeadRoutingMap + * This optional parameter specifies a prior head routing map to be + * used when generating the new routing map to be returned in + * headRoutingMap. Head assignments in oldHeadRoutingMap are + * retained if possible in the new routing map. + * headRoutingMap + * This parameter returns the new head routing map. This parameter + * is organized into eight distinct fields, each containing the head + * assignment for the corresponding display in display mask. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_HEAD_ROUTING_MAP (0x73010bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_HEAD_ROUTING_MAP_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_HEAD_ROUTING_MAP_PARAMS_MESSAGE_ID (0x0BU) + +typedef struct NV0073_CTRL_SYSTEM_GET_HEAD_ROUTING_MAP_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayMask; + NvU32 oldDisplayMask; + NvU32 oldHeadRoutingMap; + NvU32 headRoutingMap; +} NV0073_CTRL_SYSTEM_GET_HEAD_ROUTING_MAP_PARAMS; + +/* maximum number of allowed displays in a routing map */ +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_MAX_DISPLAYS (8U) + +/* per-display head assignments in a routing map */ +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY0 3:0 +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY1 7:4 +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY2 11:8 +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY3 15:12 +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY4 19:16 +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY5 23:20 +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY6 27:24 +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY7 31:28 + + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_ACTIVE + * + * This command returns the active display ID for the specified head + * on the specified subdevice. The active display may be established + * at system boot by low-level software and can then be later modified + * by an NV client using a user display class instance (see + * NV15_VIDEO_LUT_CURSOR_DAC). + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * head + * This parameter specifies the head for which the active display + * should be retrieved. This value must be between zero and the + * maximum number of heads supported by the subdevice. + * flags + * This parameter specifies optional flags to be used to while retrieving + * the active display information. + * Possible valid flags are: + * NV0073_CTRL_SYSTEM_GET_ACTIVE_FLAGS_CLIENT + * This flag is used to limit the search for the active display to + * that established by an NV client. If this flag is not specified, + * then any active display is returned (setup at system boot by + * low-level software or later by an NV client). + * displayId + * This parameter returns the displayId of the active display. A value + * of zero indicates no display is active. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_ACTIVE (0x73010cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS_MESSAGE_ID (0x0CU) + +typedef struct NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvU32 flags; + NvU32 displayId; +} NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS; + +/* valid get active flags */ +#define NV0073_CTRL_SYSTEM_GET_ACTIVE_FLAGS_CLIENT 0:0 +#define NV0073_CTRL_SYSTEM_GET_ACTIVE_FLAGS_CLIENT_DISABLE (0x00000000U) +#define NV0073_CTRL_SYSTEM_GET_ACTIVE_FLAGS_CLIENT_ENABLE (0x00000001U) + + + +/* + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP + * + * This structure defines the mapping between the RM's displayId and the + * defined ACPI IDs for each display. + * displayId + * This parameter is a handle to a single display output path from the + * GPU pins to the display connector. Each display ID is defined by one bit. + * A zero in this parameter indicates a skip entry. + * acpiId + * This parameter defines the corresponding ACPI ID of the displayId. + * flags + * This parameter specifies optional flags that describe the association + * between the display ID and the ACPI ID. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN + * This field describes where the ACPI was found. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_RM + * The ACPI ID was generated by RM code. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_DOD + * The ACPI ID was found via the ACPI _DOD call. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_CLIENT + * The ACPI ID was generated by RM Client and sent to RM. Note this + * must be set on a NV0073_CTRL_CMD_SYSTEM_SET_ACPI_ID_MAP call. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_UNDOCKED + * This flag explains that the ACPI ID is only valid when the system + * is undocked. If this flag is not set, the ACPI ID is valid always. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_DOCKED + * This flag explains that the ACPI ID is only valid when the system + * is docked. If this flag is not set, the ACPI ID is valid always. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_BIOS_DETECT + * This flag is set only if the _DOD returns that the device can be + * detected by the system BIOS. This flag is copied directly from + * the ACPI spec. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_NON_VGA_OUTPUT + * This flag is set only if the _DOD returns that the device is + * a non-VGA device whose power is related to the VGA device. + * i.e. TV tuner, DVD decoder, Video capture. This flag is copied + * directly from the ACPI spec. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_MULTIHEAD_ID + * This value is set only if the _DOD returns it. The number + * indicates the head output of a multi-head device. This has no + * relation to the term, Head, currently used in the RM today. + * This is strictly a copy of the value directly from the ACPI spec. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_SCHEME + * This flag is set only if the _DOD returns that the acpiID follows + * the ACPI 3.0 spec. This flag is copied directly from + * the ACPI spec. + * + */ + +typedef struct NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS { + NvU32 displayId; + NvU32 acpiId; + NvU32 flags; +} NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS; + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN 1:0 +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_RM 0x00000000U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_DOD 0x00000001U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_CLIENT 0x00000002U + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_UNDOCKED 2:2 +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_UNDOCKED_FALSE 0x00000000U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_UNDOCKED_TRUE 0x00000001U + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_DOCKED 3:3 +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_DOCKED_FALSE 0x00000000U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_DOCKED_TRUE 0x00000001U + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_BIOS_DETECT 16:16 +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_BIOS_DETECT_FALSE 0x00000000U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_BIOS_DETECT_TRUE 0x00000001U + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_NON_VGA_OUTPUT 17:17 +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_NON_VGA_OUTPUT_FALSE 0x00000000U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_NON_VGA_OUTPUT_TRUE 0x00000001U + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_MULTIHEAD_ID 20:18 + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_SCHEME 31:31 +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_SCHEME_VENDOR 0x00000000U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_SCHEME_30 0x00000001U + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS (16U) + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_ACPI_ID_MAP + * + * This command retrieves the mapping between the RM's displayId and the + * defined ACPI IDs for each display. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and + * the total number of subdevices within the parent device. It should + * be set to zero for default behavior. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS + * An array of display ID to ACPI ids with flags for each description. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * Only returned if subdeviceInstance was not valid. + */ + +#define NV0073_CTRL_CMD_SYSTEM_GET_ACPI_ID_MAP (0x730115U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS_MESSAGE_ID" */ + + +#define NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS { + NvU32 subDeviceInstance; + NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS acpiIdMap[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS]; +} NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_INTERNAL_DISPLAYS + * + * This command returns the set of internal (safe) display IDs for the specified + * subdevice in the form of a 32bit display mask. Safe means the displays do + * not require copy protection as they are on the motherboard. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * internalDisplaysMask + * This parameter returns a NV0073_DISPLAY_MASK value describing the set + * of displays that are internal (safe) and which do not require copy + * protection schemes. + * availableInternalDisplaysMask + * This parameter returns a NV0073_DISPLAY_MASK value describing the set + * of displays that are internal and available for use. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_INTERNAL_DISPLAYS (0x730116U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS { + NvU32 subDeviceInstance; + NvU32 internalDisplaysMask; + NvU32 availableInternalDisplaysMask; +} NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED + * + * This command is used to notify RM that all subdevices are ready for ACPI + * calls. The caller must make sure that the OS is ready to handle the ACPI + * calls for each ACPI ID. So, this call must be done after the OS has + * initialized all the display ACPI IDs to this subdevice. + * Besides, the ACPI spec provides a function for the display drivers to read + * the EDID directly from the SBIOS for each display's ACPI ID. This function + * is used to override the EDID found from a I2C or DPAux based transaction. + * This command will also attempt to call the ACPI _DDC function to read the + * EDID from the SBIOS for all displayIDs. If an EDID is found from this call, + * the RM will store that new EDID in the EDID buffer of that OD. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_NOT_SUPPORTED + * + */ + +#define NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS_MESSAGE_ID (0x17U) + +typedef struct NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS { + NvU32 subDeviceInstance; +} NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS; + +#define NV0073_CTRL_CMD_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED (0x730117U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS_MESSAGE_ID" */ + +/* + * To support RMCTRLs for BOARDOBJGRP_E255, we were required to increase the + * XAPI limit to 16K. It was observed that XP does NOT allow the static array + * size greater then 10K and this was causing the DVS failure. So we are using + * the OLD XAPI value i.e. 4K for NV0073_CTRL_SYSTEM_SRM_BUFFER_MAX while + * internally we are using the new updated XAPI value i.e. 16K. + */ +#define XAPI_ENVELOPE_MAX_PAYLOAD_SIZE_OLD 4096U + +/* + * NV0073_CTRL_SYSTEM_SRM_CHUNK + * + * Several control commands require an SRM, which may be larger than the + * available buffer. Therefore, this structure is used to transfer the needed + * data. + * + * startByte + * Index of the byte in the SRM buffer at which the current chunk of data + * starts. If this value is 0, it indicates the start of a new SRM. A + * value other than 0 indicates additional data for an SRM. + * numBytes + * Size in bytes of the current chunk of data. + * totalBytes + * Size in bytes of the entire SRM. + * srmBuffer + * Buffer containing the current chunk of SRM data. + */ +/* Set max SRM size to the XAPI max, minus some space for other fields */ +#define NV0073_CTRL_SYSTEM_SRM_BUFFER_MAX (0xe00U) /* finn: Evaluated from "(XAPI_ENVELOPE_MAX_PAYLOAD_SIZE_OLD - 512)" */ + +typedef struct NV0073_CTRL_SYSTEM_SRM_CHUNK { + NvU32 startByte; + NvU32 numBytes; + NvU32 totalBytes; + + /* C form: NvU8 srmBuffer[NV0073_CTRL_SYSTEM_SRM_BUFFER_MAX]; */ + NvU8 srmBuffer[NV0073_CTRL_SYSTEM_SRM_BUFFER_MAX]; +} NV0073_CTRL_SYSTEM_SRM_CHUNK; + +/* + * NV0073_CTRL_CMD_SYSTEM_VALIDATE_SRM + * + * Instructs the RM to validate the SRM for use by HDCP revocation. The SRM + * may be larger than the buffer provided by the API. In that case, the SRM is + * sent in chunks no larger than NV0073_CTRL_SYSTEM_SRM_BUFFER_MAX bytes. + * + * Upon completion of the validation, which is an asynchronous operation, the + * client will receive a event. Alternatively, the client + * may poll for completion of SRM validation via + * NV0073_CTRL_CMD_SYSTEM_GET_SRM_STATUS. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * srm + * A chunk of the SRM. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_NOT_READY + * NV_ERR_INVALID_ARGUMENT + * NV_WARN_MORE_PROCESSING_REQUIRED + * NV_ERR_INSUFFICIENT_RESOURCES + */ +#define NV0073_CTRL_CMD_SYSTEM_VALIDATE_SRM (0x730118U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_VALIDATE_SRM_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_VALIDATE_SRM_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV0073_CTRL_SYSTEM_VALIDATE_SRM_PARAMS { + NvU32 subDeviceInstance; + NV0073_CTRL_SYSTEM_SRM_CHUNK srm; +} NV0073_CTRL_SYSTEM_VALIDATE_SRM_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_SRM_STATUS + * + * Retrieves the status of the request to validate the SRM. If a request to + * validate an SRM is still pending, NV_ERR_NOT_READY will be + * returned and the status will not be updated. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * status + * Result of the last SRM validation request. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_NOT_READY + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_SRM_STATUS (0x730119U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_SRM_STATUS_PARAMS_MESSAGE_ID" */ + +typedef enum NV0073_CTRL_SYSTEM_SRM_STATUS { + NV0073_CTRL_SYSTEM_SRM_STATUS_OK = 0, // Validation succeeded + NV0073_CTRL_SYSTEM_SRM_STATUS_FAIL = 1, // Validation request failed + NV0073_CTRL_SYSTEM_SRM_STATUS_BAD_FORMAT = 2, // Bad SRM format + NV0073_CTRL_SYSTEM_SRM_STATUS_INVALID = 3, // Bad SRM signature +} NV0073_CTRL_SYSTEM_SRM_STATUS; + +#define NV0073_CTRL_SYSTEM_GET_SRM_STATUS_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV0073_CTRL_SYSTEM_GET_SRM_STATUS_PARAMS { + NvU32 subDeviceInstance; + NvU32 status; +} NV0073_CTRL_SYSTEM_GET_SRM_STATUS_PARAMS; + + + +/* + * NV0073_CTRL_CMD_SYSTEM_HDCP_REVOCATION_CHECK + * + * Performs the HDCP revocation process. Given the supplied SRM, all attached + * devices will be checked to see if they are on the revocation list or not. + * + * srm + * The SRM to do the revocation check against. For SRMs larger than + * NV0073_CTRL_SYSTEM_SRM_BUFFER_MAX, the caller will need to break up the + * SRM into chunks and make multiple calls. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_NOT_READY + * NV_ERR_INVALID_ARGUMENT + * NV_WARN_MORE_PROCESSING_REQUIRED + * NV_ERR_INSUFFICIENT_RESOURCES + */ +#define NV0073_CTRL_CMD_SYSTEM_HDCP_REVOCATION_CHECK (0x73011bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_HDCP_REVOCATE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_HDCP_REVOCATE_PARAMS_MESSAGE_ID (0x1BU) + +typedef struct NV0073_CTRL_SYSTEM_HDCP_REVOCATE_PARAMS { + NV0073_CTRL_SYSTEM_SRM_CHUNK srm; +} NV0073_CTRL_SYSTEM_HDCP_REVOCATE_PARAMS; + +/* + * NV0073_CTRL_CMD_UPDATE_SRM + * + * Updates the SRM used by RM for HDCP revocation checks. The SRM must have + * been previously validated as authentic. + * + * srm + * The SRM data. For SRMs larger than NV0073_CTRL_SYSTEM_SRM_BUFFER_MAX, + * the caller will need to break up the SRM into chunks and make multiple + * calls. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_NOT_READY + * NV_ERR_INVALID_ARGUMENT + * NV_WARN_MORE_PROCESSING_REQUIRED + * NV_ERR_INSUFFICIENT_RESOURCES + */ +#define NV0073_CTRL_CMD_SYSTEM_UPDATE_SRM (0x73011cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_UPDATE_SRM_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_UPDATE_SRM_PARAMS_MESSAGE_ID (0x1CU) + +typedef struct NV0073_CTRL_SYSTEM_UPDATE_SRM_PARAMS { + NV0073_CTRL_SYSTEM_SRM_CHUNK srm; +} NV0073_CTRL_SYSTEM_UPDATE_SRM_PARAMS; + +/* + * NV0073_CTRL_SYSTEM_CONNECTOR_INFO + * + * This structure describes a single connector table entry. + * + * type + * This field specifies the connector type. + * displayMask + * This field specifies the the displayMask to which the connector belongs. + * location + * This field specifies the placement of the connector on the platform. + * hotplug + * This field specifies hotplug capabilities (if any) for the connector. + */ +typedef struct NV0073_CTRL_SYSTEM_CONNECTOR_INFO { + NvU32 type; + NvU32 displayMask; + NvU32 location; + NvU32 hotplug; +} NV0073_CTRL_SYSTEM_CONNECTOR_INFO; + +/* valid type values */ +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_VGA_15_PIN (0x00000000U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_A (0x00000001U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_POD_VGA_15_PIN (0x00000002U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_COMPOSITE (0x00000010U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_SVIDEO (0x00000011U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_SVIDEO_BO_COMPOSITE (0x00000012U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_COMPONENT (0x00000013U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_SCART (0x00000014U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_SCART_EIAJ4120 (0x00000014U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_EIAJ4120 (0x00000017U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_PC_POD_HDTV_YPRPB (0x00000018U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_PC_POD_SVIDEO (0x00000019U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_PC_POD_COMPOSITE (0x0000001AU) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_I_TV_SVIDEO (0x00000020U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_I_TV_COMPOSITE (0x00000021U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_I_TV_SV_BO_COMPOSITE (0x00000022U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_I (0x00000030U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_D (0x00000031U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_ADC (0x00000032U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LFH_DVI_I_1 (0x00000038U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LFH_DVI_I_2 (0x00000039U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LFH_SVIDEO (0x0000003AU) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_BNC (0x0000003CU) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LVDS_SPWG (0x00000040U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LVDS_OEM (0x00000041U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LVDS_SPWG_DET (0x00000042U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LVDS_OEM_DET (0x00000043U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TVDS_OEM_ATT (0x00000045U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_VGA_15_PIN_UNDOCKED (0x00000050U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_VGA_15_PIN_DOCKED (0x00000051U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_I_UNDOCKED (0x00000052U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_I_DOCKED (0x00000053U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_D_UNDOCKED (0x00000052U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_D_DOCKED (0x00000053U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DP_EXT (0x00000056U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DP_INT (0x00000057U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DP_EXT_UNDOCKED (0x00000058U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DP_EXT_DOCKED (0x00000059U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_3PIN_DIN_STEREO (0x00000060U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_HDMI_A (0x00000061U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_AUDIO_SPDIF (0x00000062U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_HDMI_C_MINI (0x00000063U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LFH_DP_1 (0x00000064U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LFH_DP_2 (0x00000065U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_VIRTUAL_WFD (0x00000070U) + +/* valid hotplug values */ +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_HOTPLUG_A_SUPPORTED (0x00000001U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_HOTPLUG_B_SUPPORTED (0x00000002U) + +/* + * Nv0073_CTRL_CMD_SYSTEM_GET_CONNECTOR_TABLE + * + * This command can be used to retrieve display connector information. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * version + * This parameter returns the version of the connector table. + * platform + * This parameter returns the type of platform of the associated subdevice. + * connectorTableEntries + * This parameter returns the number of valid entries in the connector + * table. + * connectorTable + * This parameter returns the connector information in the form of an + * array of NV0073_CTRL_SYSTEM_CONNECTOR_INFO structures. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_CONNECTOR_TABLE (0x73011dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS_MESSAGE_ID" */ + +/* maximum number of connector table entries */ +#define NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_MAX_ENTRIES (16U) + +#define NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS_MESSAGE_ID (0x1DU) + +typedef struct NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS { + NvU32 subDeviceInstance; + NvU32 version; + NvU32 platform; + NvU32 connectorTableEntries; + /* + * C form: + * NV0073_CTRL_SYSTEM_CONNECTOR_INFO connectorTable[NV0073_CTRL_SYSTEM_CONNECTOR_TABLE_MAX_ENTRIES]; + */ + NV0073_CTRL_SYSTEM_CONNECTOR_INFO connectorTable[NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_MAX_ENTRIES]; +} NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS; + +/* valid version values */ +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_VERSION_30 (0x00000030U) + +/* valid platform values */ +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_DEFAULT_ADD_IN_CARD (0x00000000U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_TWO_PLATE_ADD_IN_CARD (0x00000001U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_MOBILE_ADD_IN_CARD (0x00000008U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_MXM_MODULE (0x00000009U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_MOBILE_BACK (0x00000010U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_MOBILE_BACK_LEFT (0x00000011U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_MOBILE_BACK_DOCK (0x00000018U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_CRUSH_DEFAULT (0x00000020U) + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_BOOT_DISPLAYS + * + * This command returns a mask of boot display IDs. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * bootDisplayMask + * This parameter returns the mask of boot display IDs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_BOOT_DISPLAYS (0x73011eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS_MESSAGE_ID (0x1EU) + +typedef struct NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS { + NvU32 subDeviceInstance; + NvU32 bootDisplayMask; +} NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD + * + * This command is used to execute general MXM ACPI methods. + * + * method + * This parameter identifies the MXM ACPI API to be invoked. + * Valid values for this parameter are: + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMI + * This value specifies that the MXMI API is to invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMS + * This value specifies that the MXMS API is to invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX + * This value specifies that the MXMX API is to invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUON + * This value specifies that the Hybrid GPU ON API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUOFF + * This value specifies that the Hybrid GPU OFF API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUSTA + * This value specifies that the Hybrid GPU STA API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS + * This value specifies that the Hybrid GPU MXDS API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX + * This value specifies that the Hybrid GPU MXMX API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS + * This value specifies that the Hybrid GPU DOS API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_ROM + * This value specifies that the Hybrid GPU ROM API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOD + * This value specifies that the Hybrid GPU DOD API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_SUPPORT + * This value specifies that the Hybrid GPU DSM subfunction SUPPORT + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HYBRIDCAPS + * This value specifies that the Hybrid GPU DSM subfunction SUPPORT + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POLICYSELECT + * This value specifies that the Hybrid GPU DSM subfunction POLICYSELECT + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POWERCONTROL + * This value specifies that the Hybrid GPU DSM subfunction POWERCONTROL + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_PLATPOLICY + * This value specifies that the Hybrid GPU DSM subfunction PLATPOLICY + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_DISPLAYSTATUS + * This value specifies that the Hybrid GPU DSM subfunction DISPLAYSTATUS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MDTL + * This value specifies that the Hybrid GPU DSM subfunction MDTL + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBLIST + * This value specifies that the Hybrid GPU DSM subfunction HCSMBLIST + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBADDR + * This value specifies that the Hybrid GPU DSM subfunction HCSMBADDR + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCREADBYTE + * This value specifies that the Hybrid GPU DSM subfunction HCREADBYTE + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSENDBYTE + * This value specifies that the Hybrid GPU DSM subfunction HCSENDBYTES + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETSTATUS + * This value specifies that the Hybrid GPU DSM subfunction HCGETSTATUS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCTRIGDDC + * This value specifies that the Hybrid GPU DSM subfunction HCTRIGDDC + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETDDC + * This value specifies that the Hybrid GPU DSM subfunction HCGETDDC + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DCS + * This value specifies that the Hybrid GPU DCS API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXSS + * This value specifies that the DSM MXM subfunction MXSS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMI + * This value specifies that the DSM MXM subfunction MXMI + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMS + * This value specifies that the DSM MXM subfunction MXMS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXPP + * This value specifies that the DSM MXM subfunction MXPP + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXDP + * This value specifies that the DSM MXM subfunction MXDP + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MDTL + * This value specifies that the DSM MXM subfunction MDTL + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXCB + * This value specifies that the DSM MXM subfunction MXCB + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_REMAPFUNC + * This value specifies the DSM generic remapping should return function + * and subfunction when this API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_HYBRIDCAPS + * This value specifies that the generic DSM subfunction HYBRIDCAPS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_POLICYSELECT + * This value specifies that the generic DSM subfunction POLICYSELECT + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_PLATPOLICY + * This value specifies that the generic DSM subfunction PLATPOLICY + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_DISPLAYSTATUS + * This value specifies that the generic DSM subfunction DISPLAYSTATUS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_MDTL + * This value specifies that the generic DSM subfunction MDTL + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETOBJBYTYPE + * This value specifies that the generic DSM subfunction GETOBJBYTYPE + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETALLOBJS + * This value specifies that the generic DSM subfunction GETALLOBJS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETEVENTLIST + * This value specifies that the generic DSM subfunction GETEVENTLIST + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETBACKLIGHT + * This value specifies that the generic DSM subfunction GETBACKLIGHT + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_TESTSUBFUNCENABLED + * This value specifies the testIfDsmSubFunctionEnabled test should + * be done for the func/subfunction when this API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_GETSUPPORTEDFUNC + * This value specifies the list of supported generic dsm functions + * should be returned. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS + * This value specifies that the DSM NVOP subfunction OPTIMUSCAPS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG + * This value specifies that the DSM NVOP subfunction OPTIMUSFLAG + * API is to be invoked. This API will set a Flag in sbios to Indicate + * that HD Audio Controller is disable/Enabled from GPU Config space. + * This flag will be used by sbios to restore Audio state after resuming + * from s3/s4. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_WMMX_NVOP_GPUON + * This value specifies that the WMMX (WMI-ACPI) GPON methods has to be invoked + * this call should happen below DPC level from any client. + * inData + * This parameter specifies the method-specific input buffer. Data is + * passed to the specified API using this buffer. For display related + * APIs the associated display mask can be found at a byte offset within + * the inData buffer using the following method-specific values: + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX_DISP_MASK_OFFSET + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS_DISP_MASK_OFFSET + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX_DISP_MASK_OFFSET + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS_DISP_MASK_OFFSET + * inDataSize + * This parameter specifies the size of the inData buffer in bytes. + * outStatus + * This parameter returns the status code from the associated ACPI call. + * outData + * This parameter specifies the method-specific output buffer. Data + * is returned by the specified API using this buffer. + * outDataSize + * This parameter specifies the size of the outData buffer in bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD (0x730120U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS { + NvU32 method; + NV_DECLARE_ALIGNED(NvP64 inData, 8); + NvU16 inDataSize; + NvU32 outStatus; + NV_DECLARE_ALIGNED(NvP64 outData, 8); + NvU16 outDataSize; +} NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS; + + +/* valid method parameter values */ +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX (0x00000002U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX_DISP_MASK_OFFSET (0x00000001U) + +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUON (0x00000003U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUOFF (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUSTA (0x00000005U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS (0x00000006U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX (0x00000007U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS (0x00000008U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_ROM (0x00000009U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOD (0x0000000aU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_SUPPORT (0x0000000bU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HYBRIDCAPS (0x0000000cU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POLICYSELECT (0x0000000dU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POWERCONTROL (0x0000000eU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_PLATPOLICY (0x0000000fU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_DISPLAYSTATUS (0x00000010U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MDTL (0x00000011U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBLIST (0x00000012U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBADDR (0x00000013U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCREADBYTE (0x00000014U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSENDBYTE (0x00000015U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETSTATUS (0x00000016U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCTRIGDDC (0x00000017U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETDDC (0x00000018U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DCS (0x00000019U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXSS (0x0000001aU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMI (0x0000001bU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMS (0x0000001cU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXPP (0x0000001dU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXDP (0x0000001eU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MDTL (0x0000001fU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXCB (0x00000020U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_GETEVENTLIST (0x00000021U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETMEMTABLE (0x00000022U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETMEMCFG (0x00000023U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETOBJBYTYPE (0x00000024U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETALLOBJS (0x00000025U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_REMAPFUNC (0x00000026U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_DISPLAYSTATUS (0x0000002aU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_MDTL (0x0000002bU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETOBJBYTYPE (0x0000002cU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETALLOBJS (0x0000002dU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETEVENTLIST (0x0000002eU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETBACKLIGHT (0x0000002fU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_TESTSUBFUNCENABLED (0x00000030U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_GETSUPPORTEDFUNC (0x00000031U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS (0x00000032U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_WMMX_NVOP_GPUON (0x00000033U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG (0x00000034U) + + +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETCALLBACKS (0x00000036U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_SUPPORTFUNCS (0x00000037U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_PLATCAPS (0x00000038U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_PLATPOLICY (0x00000039U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_MSTL (0x0000003aU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVGPS_FUNC_SUPPORT (0x0000003bU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDS (0x0000003cU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDM (0x0000003dU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXID (0x0000003eU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_LRST (0x0000003fU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DDC_EDID (0x00000040U) + +/* valid input buffer offset values */ +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDS_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDM_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXID_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_LRST_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DDC_EDID_DISP_MASK_OFFSET (0x00000004U) + + + +/* +* NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS +* +* This command is used to update information about VRR capable monitors +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed.This parameter must specify a value between zero and the +* total number of subdevices within the parent device.This parameter +* should be set to zero for default behavior. +* +* displayId +* DisplayId of the panel for which client wants to add or remove from VRR +* capable monitor list +* +* bAddition +* When set to NV_TRUE, signifies that the vrr monitor is to be added. +* When set to NV_FALSE, signifies that the vrr monitor is to be removed. +* +*/ +#define NV0073_CTRL_CMD_SYSTEM_VRR_DISPLAY_INFO (0x73012cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS_MESSAGE_ID (0x2CU) + +typedef struct NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bAddition; +} NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_UNPLUG_STATE + * + * This command can be used to retrieve hotplug and unplug state + * information that are currently recorded by the RM. This information is + * used by the client to determine which displays to detect after a + * hotplug event occurs. Or if the client knows that this device generates + * a hot plug/unplug signal on all connectors, then this can be used to call + * displays from detection. The displayIds on which hotplug/unplug has + * happened will be reported only ONCE to the client. That is if the call + * is done multiple times for the same event update, then for consequent + * calls the display mask will be reported as 0. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * flags + * This parameter specifies optional flags to be used while retrieving + * the hotplug state information. + * Here are the current defined fields: + * NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID + * A client uses this field to determine the lid state. + * Possible values are: + * NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID_OPEN + * The lid is open. + * NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID_CLOSED + * The lid is closed. The client should remove devices a + * reported inside the + * NV0073_CTRL_SYSTEM_GET_CONNECT_POLICY_PARAMS.lidClosedMask. + * hotPlugMask + * This display mask specifies an NV0073_DISPLAY_MASK value describing + * the set of displays that have seen a hotplug. + * hotUnplugMask + * This display mask specifies an NV0073_DISPLAY_MASK value describing + * the set of displays that have seen a hot unplug + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_UNPLUG_STATE (0x73012dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS_MESSAGE_ID (0x2DU) + +typedef struct NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS { + NvU32 subDeviceInstance; + NvU32 flags; + NvU32 hotPlugMask; + NvU32 hotUnplugMask; +} NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS; + +/* valid get hoplug state flags */ +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_FLAGS_LID 0:0 +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_FLAGS_LID_OPEN (0x00000000U) +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_FLAGS_LID_CLOSED (0x00000001U) + +/* + * NV0073_CTRL_CMD_SYSTEM_CLEAR_ELV_BLOCK + * + * This command instructs the RM to explicitly clear any + * ELV block. Clients should call this before attempting core-channel + * updates when in VRR one-shot mode. ELV block mode will be + * properly restored to its appropriate setting based on the stall-lock + * in Supervisor3 after the core channel update + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * displayId + * The public ID of the Output Display which is to be used for VRR. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ + +#define NV0073_CTRL_CMD_SYSTEM_CLEAR_ELV_BLOCK (0x73012eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS_MESSAGE_ID (0x2EU) + +typedef struct NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; +} NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR + * + * This command arms the display modeset supervisor to operate in + * a lightweight mode. By calling this, the client is implicitly + * promising not to make any changes in the next modeset that require + * the full supervisor. After SV3, the LWSV will disarm and any subsequent + * modesets will revert to full supervisors. This must be called separately + * for every display that will be part of the modeset. + * It is recommended that the client explicitly disarm the lightweight + * supervisor after every modeset as null modesets will not trigger the + * supervisor interrupts and the RM will not be able to disarm automatically + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * displayId + * The public ID of the Output Display which is to be used for VRR. + * + * bArmLWSV + * If this is set to NV_TRUE, the RM will arm the lightweight supervisor + * for the next modeset. + * If this is set to NV_FALSE, the RM will disarm the lightweight supervisor + * + * bVrrState + * VRR state to be changed. + * + * vActive + * GPU-SRC vertical active value + * + * vfp + * GPU-SRC vertical front porch + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ + +#define NV0073_CTRL_CMD_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR (0x73012fU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR_PARAMS_MESSAGE_ID (0x2FU) + +typedef struct NV0073_CTRL_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bArmLWSV; + NvBool bVrrState; + NvU32 vActive; + NvU32 vfp; +} NV0073_CTRL_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR_PARAMS; + + + +/* +* NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS +* +* This command is used to configure pstate switch parameters on VRR monitors +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed.This parameter must specify a value between zero and the +* total number of subdevices within the parent device.This parameter +* should be set to zero for default behavior. +* +* displayId +* DisplayId of the monitor being vrr configured +* +* bVrrState +* When set to NV_TRUE, signifies that the vrr is about to become active. +* When set to NV_FALSE, signifies that the vrr is about to become suspended. +* +* bVrrDirty +* When set to NV_TRUE, indicates that vrr configuration has been changed +* When set to NV_FALSE, this will indicate transitions from One shot mode to +* Continuous mode and vice versa +* +* bVrrEnabled +* When set to NV_TRUE, indicates that vrr has been enabled, i.e. vBp extended by 2 lines +* +* maxVblankExtension +* When VRR is enabled, this is the maximum amount of lines that the vblank can be extended. +* Only updated when bVrrDirty = true +* +* internalVRRHeadVblankStretch +* When VRR is enabled, this is the maximum amount of lines that the vblank can be extended. +* On NVSR and DD panels . Only updated when bVrrDirty = true +* +* minVblankExtension +* When VRR is enabled, this is the minimum amount of lines that should be present in the Vblank. The purpose is to cap the maximum refresh (currently only for HDMI 2.1 VRR compliance) +*/ +#define NV0073_CTRL_CMD_SYSTEM_CONFIG_VRR_PSTATE_SWITCH (0x730134U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS_MESSAGE_ID (0x34U) + +typedef struct NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bVrrState; + NvBool bVrrDirty; + NvBool bVrrEnabled; + NvU32 maxVblankExtension; + NvU32 internalVRRHeadVblankStretch; + NvU32 minVblankExtension; +} NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS; + + + +/* + * NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX + * + * This command is used to query the display mask of all displays + * that support dynamic display MUX. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayMask (out) + * Mask of all displays that support dynamic display MUX + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX (0x73013dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS_MESSAGE_ID (0x3DU) + +typedef struct NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS { + NvU32 subDeviceInstance; + NvU32 muxDisplayMask; +} NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS; + + + +/* + * NV0073_CTRL_CMD_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH + * + * This command allocates a specified amount of ISO memory bandwidth for + * display. If the requested amount of bandwidth cannot be allocated (either + * because it exceeds the total bandwidth available to the system, or because + * too much bandwidth is already allocated to other clients), the call will + * fail and NV_ERR_INSUFFICIENT_RESOURCES will be returned. + * + * If bandwidth has already been allocated via a prior call, and a new + * allocation is requested, the new allocation will replace the old one. (If + * the new allocation fails, the old allocation remains in effect.) + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * averageBandwidthKBPS + * This parameter specifies the amount of ISO memory bandwidth requested. + * floorBandwidthKBPS + * This parameter specifies the minimum required (i.e., floor) dramclk + * frequency, multiplied by the width of the pipe over which the display + * data will travel. (It is understood that the bandwidth calculated by + * multiplying the clock frequency by the pipe width will not be + * realistically achievable, due to overhead in the memory subsystem. The + * API will not actually use the bandwidth value, except to reverse the + * calculation to get the required dramclk frequency.) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INSUFFICIENT_RESOURCES + * NV_ERR_NOT_SUPPORTED + * NV_ERR_GENERIC + */ + +/* + * NV0073_CTRL_CMD_SYSTEM_INTERNAL_ALLOCATE_DISPLAY_BANDWIDTH + * + * This command is identical to + * NV0073_CTRL_CMD_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH, except that it routes to + * Physical RM, and is for internal RM use. Clients are advised to use + * NV0073_CTRL_CMD_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH instead. + */ + +#define NV0073_CTRL_CMD_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH (0x730143U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_MESSAGE_ID" */ +#define NV0073_CTRL_CMD_SYSTEM_INTERNAL_ALLOCATE_DISPLAY_BANDWIDTH (0x730157U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_INTERNAL_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_MESSAGE_ID" */ + +typedef struct NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_TYPE { + NvU32 subDeviceInstance; + NvU32 averageBandwidthKBPS; + NvU32 floorBandwidthKBPS; +} NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_TYPE; + +#define NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_MESSAGE_ID (0x43U) + +typedef NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_TYPE NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS; +#define NV0073_CTRL_SYSTEM_INTERNAL_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_MESSAGE_ID (0x57U) + +typedef NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_TYPE NV0073_CTRL_SYSTEM_INTERNAL_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS; + +/* + * NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS + * + * This structure represents the hotplug event config control parameters. + * + * subDeviceInstance + * This parameter should specify the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * + * deviceMapFilter + * This parameter returns (in GET) or should specify (in SET) a device map + * indicating device(s) to sense. + * + * hotPluginSense + * This parameter returns (in GET) or should specify (in SET) a device map + * indicating device(s) plugged in that caused the most recent hotplug + * event. + * + * hotUnplugSense + * This parameter returns (in GET) or should specify (in SET) a device map + * indicating device(s) un plugged that caused the most recent hotplug + * event. + */ + +typedef struct NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS { + NvU32 subDeviceInstance; + NvU32 deviceMapFilter; + NvU32 hotPluginSense; + NvU32 hotUnplugSense; +} NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_EVENT_CONFIG + * + * This command fetches the hotplug event configuration. + * + * See @ref NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS for documentation on + * the parameters. + */ + +#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_EVENT_CONFIG (0x730144U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_HOTPLUG_EVENT_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_EVENT_CONFIG_PARAMS_MESSAGE_ID (0x44U) + +typedef NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS NV0073_CTRL_SYSTEM_GET_HOTPLUG_EVENT_CONFIG_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_SET_HOTPLUG_EVENT_CONFIG + * + * This command sets the hotplug event configuration. + * + * See @ref NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS for documentation on + * the parameters. + */ + +#define NV0073_CTRL_CMD_SYSTEM_SET_HOTPLUG_EVENT_CONFIG (0x730145U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_SET_HOTPLUG_EVENT_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_SET_HOTPLUG_EVENT_CONFIG_PARAMS_MESSAGE_ID (0x45U) + +typedef NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS NV0073_CTRL_SYSTEM_SET_HOTPLUG_EVENT_CONFIG_PARAMS; + + + +/* +* NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS +* +* This command is used to read Core channel, Cursor channel, Window channel, and Head register values and encode these values with ProtoDmp. +* +* subDeviceInstance (in) +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. +* headMask (in) +* Head mask representing which register values should be encoded +* windowMask (in) +* Window channel mask whose register values should be encoded +* bRecordCoreChannel (in) +* Indicates whether or not to encode core channel register values +* bRecordCursorChannel (in) +* Indicates whether or not to encode cursor channel register values +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_ARGUMENT +* NV_ERR_NOT_SUPPORTED +*/ +#define NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS (0x73014aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS_MESSAGE_ID (0x4AU) + +typedef struct NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS { + NvU32 subDeviceInstance; + NvU32 headMask; + NvU32 windowMask; + NvBool bRecordCoreChannel; + NvBool bRecordCursorChannel; +} NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT + * + * This command is used to query the display mux status for the given + * display device + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT (0x73014bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS_MESSAGE_ID (0x4BU) + +typedef struct NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS { + NvU32 subDeviceInstance; + NvBool bIsSidebandI2cSupported; +} NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT + * + * This command is used to query if SIDEBAND SR can be used with the + * given display device. If PSR API is supported on the system, + * then sideband SR support is set to false. + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation + * should be directed. + * displayId (in) + * This parameter inputs the displayId of the active display. A value + * of zero indicates no display is active. + * bIsSidebandSrSupported + * If it is true, it means that sideband is supported and not PSR API. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT (0x73014cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS_MESSAGE_ID (0x4CU) + +typedef struct NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bIsSidebandSrSupported; +} NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS; + +/* + * Maps the memory allocated in Kernel RM into Physical RM using the + * memory descriptor information provided. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +typedef struct NV0073_CTRL_SHARED_MEMDESC_INFO { + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NV_DECLARE_ALIGNED(NvU64 alignment, 8); + NvU32 addressSpace; + NvU32 cpuCacheAttrib; +} NV0073_CTRL_SHARED_MEMDESC_INFO; + +#define NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA (0x730151U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS_MESSAGE_ID (0x51U) + +typedef struct NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS { + NV_DECLARE_ALIGNED(NV0073_CTRL_SHARED_MEMDESC_INFO memDescInfo, 8); + NvU32 subDeviceInstance; + NvBool bMap; +} NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO + * + * Fetches the LoadV Counter information from corresponding registers. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * head + * headId of the panel for which we are going to read loadv info + * Possible status values returned are: + * counterValue + * Counts number of frames that have been procesed or synchronized with display + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO (0x730154U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO_PARAMS_MESSAGE_ID (0x54U) + +typedef struct NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvU32 counterValue; +} NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO_PARAMS; + +/*! + * @brief Defines Display Low Power feature IDs + * + * Following defines specifies unique IDs to identify Display Power saving feature. + */ +#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_INVALID 0x0000 +#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_ALPM 0x0001 +#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_SWITCH_HUBCLK 0x0002 +#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_SWITCH_RISCV0CLK 0x0003 +#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_SWITCH_DISPCLK 0x0004 +#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_SWITCH_POSTRG_CLKS 0x0005 +#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_GATING_HUBCLK 0x0006 +#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_GATING_DISPCLK 0x0007 +#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_GATING_POSTRG_CLKS 0x0008 +#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_MSCG 0x0009 +#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_GEN_STATS 0x0010 + +// Parameter/characteristics of Display ALPM +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_ALPM_INVALID 0x0000 +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_ALPM_SUPPORTED 0x0001 +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_ALPM_ENABLED 0x0002 +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_ALPM_TYPE_AUX_LESS 0x0003 +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_ALPM_ENGAGE_TIME 0x0004 +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_ALPM_ENTRY_COUNT 0x0005 +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_ALPM_EXIT_COUNT 0x0006 + +/*! + * @brief Parameter/characteristics of hubclk, dispclk, riscv0clk and Post-RG clock Switching + * + * Following are the Parameter/characteristics for of hubclk, dispclk, riscv0clk and + * Post-RG clock Switching + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_SWITCH_INVALID (0x0000) + +/*! + * Property specifies if Clock Switching is supported + * or not. This property is applicable for hubclk, dispclk, riscv0clk and Post-RG clk. + * (This property allows Get operation) + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_SWITCH_SUPPORT (0x0001) + + /*! + * Property specifies if Clock Switching is enabled or not. + * This property is applicable for hubclk, dispclk, riscv0clk and Post-RG clk. + * (This property allows Get and Set operation) + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_SWITCH_ENABLED (0x0002) + + /*! + * Property specifies the time(us) for which the specified clock was in Safe mode. + * This property is applicable for hubclk, dispclk, riscv0clk and Post-RG clk + * (This property allows Get operation) + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_SWITCH_SAFE_TIME_US (0x0003) + + /*! + * Property specifies the time(us) for which the specified clock was in Alternate mode. + * This property is only applicable to riscv0clk. + * (This property allows Get operation) + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_SWITCH_ALTERNATE_TIME_US (0x0004) + + /*! + * Property specifies if the specified clock is forced to Function mode or not. + * This property is applicable for hubclk, dispclk, riscv0clk and Post-RG clk. + * (This property allows Get and Set operation) + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_SWITCH_FORCE_FUNCTION (0x0005) + + /*! + * Property specifies if there was an error when the specified clock is being switched + * to safe mode but switch didn't happen in programmed time. + * This property is applicable for hubclk, dispclk, riscv0clk and Post-RG clk. + * (This property allows Get operation) + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_SWITCH_SAFE_ERROR (0x0006) + + /*! + * Property specifies if there was an error when the specified clock is being switched + * to function mode but switch didn't happen in programmed time. + * This property is applicable for hubclk, dispclk, riscv0clk and Post-RG clk. + * (This property allows Get operation) + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_SWITCH_UNSAFE_ERROR (0x0007) + + /*! + * Property specifies if there was an error when Riscv0clk clock is being switched + * to alternate mode but switch didn't happen in programmed time. + * This property is only applicable to riscv0clk. + * (This property allows Get operation) + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_SWITCH_ALTER_ERROR (0x0008) + + /*! + * Property specifies if there was an error when the Riscv0clk clock is being switched to + * function mode but switch didn't happen in programmed time. + * This property is only applicable to riscv0clk. + * (This property allows Get operation) + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_SWITCH_UNALTER_ERROR (0x0009) + + /*! + * Property specifies current state of the specified clock + * i.e. Safe or Function or Alternate + * (This property allows Get operation) + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_SWITCH_STATUS (0x0010) + +/*! + * @brief Parameter/characteristics of hubclk, dispclk and Post-RG clock Gating + * + * Following are the Parameter/characteristics for of hubclk, dispclk and Post-RG + * Clock Gating + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_GATING_INVALID (0x0000) + +/*! + * Property specifies if Clock Gating is supported + * or not. This property is applicable for hubclk, dispclk and Post-RG clk. + * (This property allows Get operation) + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_GATING_SUPPORT (0x0001) +/*! + * Property specifies if Clock Gating is enabled or not. + * This property is applicable for hubclk, dispclk and Post-RG clk. + * (This property allows Get and Set operation) + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_GATING_ENABLED (0x0002) + +/*! + * Property specifies the time(us) for which the specified clock was gated. + * This property is applicable for hubclk, dispclk and Post-RG clk + * (This property allows Get operation) + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_GATING_GATE_TIME_US (0x0003) + + /*! + * Property specifies current state of the specified clock + * i.e. Gated ot not Gated + * (This property allows Get operation) + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_GATING_STATUS (0x0004) + +/*! + * @brief Parameter/characteristics of MSCG + * + * Following are the Parameter/characteristics for MSCG + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_INVALID (0x0000) + +/*! + * Property specifies if DPS1 is supported + * (This property allows Get operation) + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS1_SUPPORT (0x0001) + +/*! + * Property specifies if DPS2 is supported + * (This property allows Get operation) + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS2_SUPPORT (0x0002) + +/*! + * Property specifies if MSCG is enabled + * (This property allows Get/SET operation) + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_ENABLED (0x0003) + +/*! + * Property specifies the time(in US) for which DPS1 was enabled + * in ACTIVE region + * (This property allows Get operation) + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS1_ACTIVE_TIME_US (0x0004) + +/*! + * Property specifies the time(in US) for which DPS1 was enabled + * in VBLANK region + * (This property allows Get operation) + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS1_VBLANK_TIME_US (0x0005) + +/*! + * Property specifies the time(in US) for which DPS2 was enabled + * in ACTIVE region + * (This property allows Get operation) + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS2_ACTIVE_TIME_US (0x0006) + +/*! + * Property specifies the time(in US) for which DPS2 was enabled + * in VBLANK region + * (This property allows Get operation) + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS2_VBLANK_TIME_US (0x0007) + +/*! + * @brief Parameter/characteristics of General Display Stats + * + * Following are the Parameter/characteristics for General Display Stats + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_GEN_STATS_INVALID (0x0000) + +/*! + * Property specifies the frame counter for display. + * (This property allows Get operation) + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_GEN_STATS_FRAME_COUNTER (0x0001) + +/*! + * Property specifies the LOADV counter for display. + * (This property allows Get operation) + */ +#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_GEN_STATS_LOADV_COUNTER (0x0002) + +/*! + * @brief Structure to identify display low power feature + * + * Structure to get/set feature Id, It has two fields + * FeatureID[In] : Feature Identifier + * SubFeatureID[In] : If Any Subfeature associated to Feature + * + * In general, Power saving feature is identify by featureId and SubFeature. + * Add enum in this structure in case some specific power feature needs + * additional fields. "Union" should follow XAPI standards. + */ +typedef struct NV0073_CTRL_DISP_LPWR_FEATURE { + NvU16 featureId; + NvU16 subfeatureId; +} NV0073_CTRL_DISP_LPWR_FEATURE; + +/*! + * @brief Parameter structure + * + * Structure to get/set parameter/characteristic. Each parameter has 3 field + * 1) ID [In] : Parameter Identifier + * 2) Flag [In/Out] : Flags + * 3) Value [In/Out] : Value of parameter + * + * Add enum in this structure in case we need to additional fields for some + * special parameters. + */ +typedef struct NV0073_CTRL_DISP_LPWR_PARAMETER { + NvU16 paramId; + NvU16 flag; + NvU32 val; +} NV0073_CTRL_DISP_LPWR_PARAMETER; + +/*! + * @brief Flags for PARAMETER + * + * SUCCEED: + * - Get/Set param call is succeed or not. + * - Get Param call for given parameter succeed means RMCtrl retrieved valid + * value for this parameter. + * - Set Param call for given parameter succeed means RMCtrl set value of this + * parameter. + * + * BLOCKING: + * - Defines whether RM Ctrl call is blocking/non-blocking for given parameter. + */ + +#define NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_FLAG_SUCCEED 0:0 +#define NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_FLAG_SUCCEED_NO 0x0 +#define NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_FLAG_SUCCEED_YES 0x1 + +/*! + * @brief Defines all information required to get/set the parameter for given + * display low power feature. + */ +typedef struct NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER { + NV0073_CTRL_DISP_LPWR_FEATURE feature; + NV0073_CTRL_DISP_LPWR_PARAMETER param; +} NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER; + +// Max size of FEATURE_PARAMETER structure for RMCtrl NV0073_CTRL_DISP_LPWR_GET/SET +#define NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_LIST_MAX_SIZE 64 + +/* + * NV0073_CTRL_CMD_DISP_LPWR_FEATURE_PARAMETER_GET + * + * This command retrieves parameters/characteristics of power features. It can + * query NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_LIST_MAX_SIZE number of parameters + * in one call. Command provides facility of collecting information on multiple + * power saving features in one call. + * + * Commands returns SUCCESS only when it successfully retrieves value all + * parameter in the list. + * + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * + * displayId + * DisplayId of the panel for which we are going to low power features data + * Possible status values returned are: + * + * listSize + * Number of valid entries in list. + * + * list + * List of parameters. Refer NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER to get + * details about each entry in the list. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_DISP_LPWR_FEATURE_PARAMETER_GET (0x730155) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_GET_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_GET_PARAMS_MESSAGE_ID (0x55U) + +typedef struct NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_GET_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 listSize; + NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER list[NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_LIST_MAX_SIZE]; +} NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_GET_PARAMS; + +/* + * NV0073_CTRL_CMD_DISP_LPWR_FEATURE_PARAMETER_SET + * + * This command sets parameters/characteristics of power features. It can + * set NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_LIST_MAX_SIZE number of parameters + * in one call. Command provides facility of setting parameters for multiple + * power saving features in one call. + * + * Commands returns SUCCESS only when it successfully sets value of all + * parameter in the list. + * + * listSize + * Number of valid entries in list. + * + * list + * List of parameters. Refer NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER to get + * details about each entry in the list. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_DISP_LPWR_FEATURE_PARAMETER_SET (0x730156) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_SET_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_SET_PARAMS_MESSAGE_ID (0x56U) + +typedef struct NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_SET_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 listSize; + NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER list[NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_LIST_MAX_SIZE]; +} NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_SET_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR + * + * This command is used to Notify RM about DRR feature. RM uses this + * notification to account MSCG WARs for Turing and Ampere HW bugs. + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation + * should be directed. + * presentDurationUs (in) + * This parameter inputs the presentDurationUs of the active display. + * bEnableDrr + * If it is true, it means that DRR is enabled from DD side. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR (0x730159U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS_MESSAGE_ID (0x59U) + +typedef struct NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS { + NvU32 subDeviceInstance; + NvU32 presentDurationUs; + NvBool bEnableDrr; +} NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_SET_DISPLAY_PERF_LIMIT + * + * Note: This API is obsolete, replaced by + * NV0000_CTRL_CMD_SYSTEM_SOC_SET_PERF_LIMITS. + * + * This command sets lower and/or upper bounds for a display clock (dispclk or + * hubclk), or for the memory perf level. When this API is called, the system + * will immediately attempt to switch the clock or perf level to a value that + * meets the specified condition(s). + * + * If no lower limit is desired, the "min" input should be set to zero. + * + * If no upper limit is desired for a clock, the "max" input should be set to + * NV_U32_MAX. + * + * This API does not allow an upper limit to be specified for perf level. + * + * Any perf limit set through this API will remain in effect until it updated + * or cancelled by a subsequent call to this API. A perf limit may be + * cancelled by setting the "min" value to NV_U32_MIN (0) and the "max" value + * (for clocks) to NV_U32_MAX. Only one perf limit may be in effect for a + * given clientUsageId and type at any given time. + * + * At any given time, multiple perf limits (with different clientUsageIds) may + * be in effect for a given clock or perf level, and that clock or perf level + * will be set to a value that meets the requirements of all active perf + * limits. If there is a conflict between perf limits, the conflict will be + * resolved by the perf limit(s) with the higher priority. + * + * For example, suppose the API is called with the following parameters: + * clientUsageId = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS + * type = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_DISPCLK + * data.clock.minFrequencyKHz = 800000 + * data.clock.maxFrequencyKHz = 800000 + * This will set dispclk to 800 MHz (or possibly a slightly higher frequency, + * if the clock dividers do not allow 800 MHz to be set exactly). + * + * Then suppose this call is made: + * clientUsageId = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_ISMODEPOSSIBLE + * type = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_DISPCLK + * data.clock.minFrequencyKHz = 1000000 + * data.clock.maxFrequencyKHz = 0xFFFFFFFF + * After this call, dispclk will remain set to 800 MHz, because, although the + * min frequency was requested to be at least 1 GHz, this would conflict with + * the "maxFrequencyKHz = 800000" value set in the previous call, which is + * still in effect. The previous call takes priority because + * NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS has higher priority than + * NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_ISMODEPOSSIBLE. + * + * Then suppose this call is made: + * clientUsageId = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS + * type = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_DISPCLK + * data.clock.minFrequencyKHz = 0 + * data.clock.maxFrequencyKHz = 0xFFFFFFFF + * This removes the NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS perf + * limit. At this point, dispclk will be set to 1 GHz, in accordance with the + * NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_ISMODEPOSSIBLE perf limit, + * which is still in effect. (The remaining perf limit allows the clock to be + * higher than 1 GHz, but in practice, the clock will generally be set to the + * lowest frequency that meets the perf limit requirement, to save power. For + * perf level, perf monitors (which do not use the perf limit mechanism) may + * force a higher value in order to meet performance needs.) + * + * This API takes an array of perf limit structures, so multiple perf limits + * maybe set within the same call. + * + * This API is primarily intended for use on SOC products, where display is + * separate from the GPU. On dGPU products, this API may not be supported; + * instead, NV2080_CTRL_CMD_PERF_LIMITS_SET_STATUS_V2 may be used to set perf + * limits. + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * numLimits (in) + * This is the number of perf limits with lower and/or upper limits to + * apply. + * + * bWaitForCompletion (in) + * It is possible that a perf change or clock change may take some time to + * execute. If this flag is set, the API will wait for all of the changes + * to complete before returning. (However, it will not wait for completion + * of any operation that is blocked by a higher priority perf limit.) + * + * clientUsageId (in) + * This is a NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_xxx value + * indicating who the client is, and/or the purpose of the perf limit. It + * is used to establish priority between conflicting perf limits. + * + * whatIsToBeLimited (in) + * This is a NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_xxx value + * indicating which clock, or memory perf level, is to have limits applied. + * + * minLevelOrFreqKHz (in) + * maxLevelOrFreqKHz (in) + * If type is + * NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_PERF_LEVEL, then + * minLevelOrFreqKHz specifies the zero-based index of the minimum perf + * level to allow. maxLevelOrFreqKHz is not used. + * + * If type specifies a clock + * (NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_DISPCLK or + * NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_HUBCLK), then + * minLevelOrFreqKHz and maxLevelOrFreqKHz specify the lower and upper + * limits (respectively) for the specified clock's frequency. + */ +#define NV0073_CTRL_CMD_SYSTEM_SET_DISPLAY_PERF_LIMIT (0x73015aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_PARAMS_MESSAGE_ID" */ + +/* valid clientUsageId values */ +#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_ISMODEPOSSIBLE (0U) +#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MCLK_SWITCH (1U) +#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS (2U) +#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_TEST_PERF_LEVELS (3U) + +/* valid type values */ +#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_LIMITING_PERF_LEVEL (0U) +#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_LIMITING_DISPCLK (1U) +#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_LIMITING_HUBCLK (2U) + +/* Define a structure for a single perf limit */ +typedef struct NV0073_CTRL_SYSTEM_DISPLAY_PERF_LIMIT { + NvU8 clientUsageId; + NvU8 whatIsToBeLimited; + NvU32 minLevelOrFreqKHz; + NvU32 maxLevelOrFreqKHz; +} NV0073_CTRL_SYSTEM_DISPLAY_PERF_LIMIT; + +#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_PARAMS_MESSAGE_ID (0x5AU) + +typedef struct NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_PARAMS { + NvU32 subDeviceInstance; + NvU32 numLimits; + NvBool bWaitForCompletion; + NV_DECLARE_ALIGNED(NvP64 limits, 8); +} NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_CRASH_LOCK_COUNTER_INFO + * + * Fetches the Crash Lock Counter information from corresponding register. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * head + * HeadId of the panel for which we are going to read crash lock counter info + * Possible status values returned are: + * counterValueV + * Counts number of vertical crashlock events that have occured with this display + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SYSTEM_GET_CRASH_LOCK_COUNTER_INFO (0x730160U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_GET_CRASH_LOCK_COUNTER_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_GET_CRASH_LOCK_COUNTER_INFO_PARAMS_MESSAGE_ID (0x60U) + +typedef struct NV0073_CTRL_CMD_SYSTEM_GET_CRASH_LOCK_COUNTER_INFO_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvU32 counterValueV; +} NV0073_CTRL_CMD_SYSTEM_GET_CRASH_LOCK_COUNTER_INFO_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GSYNC_SET_EXACT_REFRESH_RATE + * + * DD sends this command to RM to control the exact refresh rate for framelock. + * RM will adjust the pixel clock to this precise value during the next modeset + * if framelock is enabled. + * The refresh rate is given in the form of (refreshRateNumerator / refreshRateDenominator) * Hz + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId + * This specifies a display to configure + * refreshRateNumerator + * This specifies the numerator of the refresh rate fraction + * refreshRateDenominator + * This specifies the denominator of the refresh rate fraction + * hTotal + * This specifies the hTotal of the display + * vTotal + * This specifies the vTotal of the display + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAMETER + */ + +#define NV0073_CTRL_CMD_SYSTEM_GSYNC_SET_EXACT_REFRESH_RATE (0x7301a4U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GSYNC_SET_EXACT_REFRESH_RATE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_MAX_GSYNC_DISPLAYS 32 + +#define NV0073_CTRL_SYSTEM_GSYNC_SET_EXACT_REFRESH_RATE_PARAMS_MESSAGE_ID (0xA4U) + +typedef struct NV0073_CTRL_SYSTEM_GSYNC_SET_EXACT_REFRESH_RATE_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NV_DECLARE_ALIGNED(NvU64 refreshRateNumerator, 8); + NV_DECLARE_ALIGNED(NvU64 refreshRateDenominator, 8); + NvU32 hTotal; + NvU32 vTotal; +} NV0073_CTRL_SYSTEM_GSYNC_SET_EXACT_REFRESH_RATE_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GSYNC_GET_EXACT_PIXEL_CLOCK + * + * Diagnostic query to get the exact pixel clock from RM + * The pixel clock rate is given in the form of (refreshRateNumerator / refreshRateDenominator) * Hz + * + * displayId + * This specifies a display to query + * pixelClockNumerator + * This specifies the numerator of the pixel clock fraction + * pixelClockDenominator + * This specifies the denominator of the pixel clock fraction + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAMETER + * NV_ERR_NOT_SUPPORTED + * NV_ERR_NOT_READY + * NV_ERR_INVALID_STATE + */ +#define NV0073_CTRL_CMD_SYSTEM_GSYNC_GET_EXACT_PIXEL_CLOCK (0x7301a6U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GSYNC_GET_EXACT_PIXEL_CLOCK_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GSYNC_GET_EXACT_PIXEL_CLOCK_PARAMS_MESSAGE_ID (0xA6U) + +typedef struct NV0073_CTRL_SYSTEM_GSYNC_GET_EXACT_PIXEL_CLOCK_PARAMS { + NvU32 displayId; + NV_DECLARE_ALIGNED(NvU64 pixelClockNumerator, 8); + NV_DECLARE_ALIGNED(NvU64 pixelClockDenominator, 8); +} NV0073_CTRL_SYSTEM_GSYNC_GET_EXACT_PIXEL_CLOCK_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_RASTER_FRAME_LINE_PIXEL + * + * Diagnostic query to get the raster position that is currently being output on a display + * + * displayCount + * This specifies how many displays are included + * displayId + * This specifies a display to query + * timestampBeginning + * This is returned by RM to specify the kernel timestamp when reading the values was started + * in units of nanoseconds + * timestampEnd + * This is returned by RM to specify the kernel timestamp when reading the values was finished + * in units of nanoseconds + * frame + * This is returned by RM to give the current frame counter + * line + * This is returned by RM to give the current line number + * pixel + * This is returned by RM to give the current column in the line + * stereoPhase + * This is returned by RM to give the stereo phase + * (NV0073_CTRL_CMD_SYSTEM_GET_DMI_SCANLINE_LEFT_EYE or NV0073_CTRL_CMD_SYSTEM_GET_DMI_SCANLINE_RIGHT_EYE) + * timestampFrequency + * This is returned by RM to specify how many times the kernel timestamp changes per second + * (according to the OS) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_SYSTEM_GET_RASTER_FRAME_LINE_PIXEL (0x7301a5U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_RASTER_FRAME_LINE_PIXEL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_RASTER_FRAME_LINE_PIXEL_PARAMS_MESSAGE_ID (0xA5U) + +typedef struct NV0073_CTRL_SYSTEM_GET_RASTER_FRAME_LINE_PIXEL_PARAMS { + NvU32 displayCount; + struct { + NvU32 displayId; + NV_DECLARE_ALIGNED(NvU64 timestampBeginning, 8); + NV_DECLARE_ALIGNED(NvU64 timestampEnd, 8); + NvU32 frame; + NvU32 line; + NvU32 pixel; + NvU8 stereoPhase; + } displays[NV_MAX_HEADS]; + NV_DECLARE_ALIGNED(NvU64 timestampFrequency, 8); +} NV0073_CTRL_SYSTEM_GET_RASTER_FRAME_LINE_PIXEL_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_QUERY_UEFI_DISPLAY_BANDWIDTH + * + * Queries the UEFI allocated ISO BW and Floor BW for Display. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * isoBandwidthKBPS + * ISO BW set by UEFI to initialize display + * floorBandwidthKBPS + * Floor BW set by UEFI to initialize display + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_GENERIC + */ + +#define NV0073_CTRL_CMD_SYSTEM_QUERY_UEFI_DISPLAY_BANDWIDTH (0x730161U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_QUERY_UEFI_DISPLAY_BANDWIDTH_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_QUERY_UEFI_DISPLAY_BANDWIDTH_PARAMS_MESSAGE_ID (0x61U) + +typedef struct NV0073_CTRL_SYSTEM_QUERY_UEFI_DISPLAY_BANDWIDTH_PARAMS { + NvU32 subDeviceInstance; + NvU32 isoBandwidthKBPS; + NvU32 floorBandwidthKBPS; +} NV0073_CTRL_SYSTEM_QUERY_UEFI_DISPLAY_BANDWIDTH_PARAMS; + +/* _ctrl0073system_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0076.h b/userspace/sdks/nv570/inc/ctrl/ctrl0076.h new file mode 100644 index 0000000..0387fc9 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0076.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0076.finn +// + + + +/* + * NV0076_CTRL_NOTIFY_CONSOLE_DISABLED + * + * This command signals to the resource manager that the operating system's + * legacy framebuffer console was disabled and that the underlying BAR mapping + * can be freed. + */ +#define NV0076_CTRL_CMD_NOTIFY_CONSOLE_DISABLED (0x760101) /* finn: Evaluated from "(FINN_NV01_FRAMEBUFFER_CONSOLE_INTERFACE_ID << 8) | 1" */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0080.h b/userspace/sdks/nv570/inc/ctrl/ctrl0080.h new file mode 100644 index 0000000..4221326 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0080.h @@ -0,0 +1,49 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080.finn +// + + + + +#include "ctrl0080/ctrl0080bif.h" +#include "ctrl0080/ctrl0080gpu.h" +#include "ctrl0080/ctrl0080dma.h" +#include "ctrl0080/ctrl0080gr.h" +#include "ctrl0080/ctrl0080cipher.h" +#include "ctrl0080/ctrl0080fb.h" +#include "ctrl0080/ctrl0080fifo.h" +#include "ctrl0080/ctrl0080host.h" + + +#include "ctrl0080/ctrl0080perf.h" +#include "ctrl0080/ctrl0080nvenc.h" +#include "ctrl0080/ctrl0080nvdec.h" +#include "ctrl0080/ctrl0080nvjpg.h" +#include "ctrl0080/ctrl0080unix.h" +#include "ctrl0080/ctrl0080internal.h" diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080base.h b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080base.h new file mode 100644 index 0000000..9780602 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080base.h @@ -0,0 +1,73 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080base.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV01_DEVICE_XX/NV03_DEVICE control commands and parameters */ + +#define NV0080_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0080, NV0080_CTRL_##cat, idx) + +/* GPU device command categories (6bits) */ +#define NV0080_CTRL_RESERVED (0x00) +#define NV0080_CTRL_BIF (0x01) +#define NV0080_CTRL_GPU (0x02) +#define NV0080_CTRL_CLK (0x10) +#define NV0080_CTRL_GR (0x11) +#define NV0080_CTRL_CIPHER (0x12) +#define NV0080_CTRL_FB (0x13) +#define NV0080_CTRL_HOST (0x14) +#define NV0080_CTRL_VIDEO (0x15) +#define NV0080_CTRL_FIFO (0x17) +#define NV0080_CTRL_DMA (0x18) +#define NV0080_CTRL_PERF (0x19) +#define NV0080_CTRL_PERF_LEGACY_NON_PRIVILEGED (0x99) /* finn: Evaluated from "(NV0080_CTRL_PERF | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV0080_CTRL_NVENC (0x1B) +#define NV0080_CTRL_NVDEC (0x1C) +#define NV0080_CTRL_RC (0x1D) +#define NV0080_CTRL_OS_UNIX (0x1E) +#define NV0080_CTRL_NVJPG (0x1F) +#define NV0080_CTRL_INTERNAL (0x20) +#define NV0080_CTRL_NVLINK (0x21) + +/* + * NV0080_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0080_CTRL_CMD_NULL (0x800000) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrl0080base_h_ */ + +/* extract device cap setting from specified category-specific caps table */ +#define NV0080_CTRL_GET_CAP(cat,tbl,c) \ + NV0080_CTRL_##cat##_GET_CAP(tbl, NV0080_CTRL_##cat##_CAPS_##c) diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080bif.h b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080bif.h new file mode 100644 index 0000000..c3d1831 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080bif.h @@ -0,0 +1,125 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080bif.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" +#include "nvcfg_sdk.h" + +/* + * NV0080_CTRL_CMD_BIF_RESET + * + * This command initiates the specified reset type on the GPU. + * + * flags + * Specifies various arguments to the reset operation. + * + * Supported fields include: + * + * NV0080_CTRL_BIF_RESET_FLAGS_TYPE + * When set to _SW_RESET, a SW (fullchip) reset is performed. When set + * to _SBR, a secondary-bus reset is performed. When set to + * _FUNDAMENTAL, a fundamental reset is performed. + * + * NOTE: _FUNDAMENTAL is not supported for Blackwell and later chips. + * Use BOOT_DEVICE_FUSE or BOOT_DEVICE reset type instead. + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0080_CTRL_CMD_BIF_RESET (0x800102) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_RESET_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_BIF_RESET_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_BIF_RESET_PARAMS { + NvU32 flags; +} NV0080_CTRL_BIF_RESET_PARAMS; + + +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE 4:0 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SW_RESET 0x1 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SBR 0x2 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_FUNDAMENTAL 0x3 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE_FUSE 0x4 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE 0x5 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_PEX 0x6 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_OOBHUB_TRIGGER 0x7 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BASE 0x8 + +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_CXL_RESET 0x9 + + + +/* + * NV0080_CTRL_BIF_ASPM_CYA_UPDATE + * + * bL0sEnable + * bL1Enable + * ASPM CYA update by client + * + * Possible status values returned are: + * NV_OK + */ + +#define NV0080_CTRL_CMD_BIF_ASPM_CYA_UPDATE (0x800105) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS { + NvBool bL0sEnable; + NvBool bL1Enable; +} NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS; + +/* + * NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK + * + * pciePowerControlMask + * pciePowerControlIdentifiedKeyOrder + * pciePowerControlIdentifiedKeyLocation + * ASPM and RTD3 enable/disable information + * + * Possible status values returned are: + * NV_OK + */ + +#define NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK (0x800106) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS { + NvU32 pciePowerControlMask; + NvU32 pciePowerControlIdentifiedKeyOrder; + NvU32 pciePowerControlIdentifiedKeyLocation; +} NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS; + +/* _ctrl0080bif_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080cipher.h b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080cipher.h new file mode 100644 index 0000000..9b63db0 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080cipher.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080cipher.finn +// + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080dma.h b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080dma.h new file mode 100644 index 0000000..d53e06c --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080dma.h @@ -0,0 +1,860 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080dma.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE dma control commands and parameters */ + +/* + * NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK + * + * This parameter returns the parameters specific to a PTE as follows: + * pageSize + * GET: This parameter returns the page size of the PTE information + * being returned. If 0, then this pteBlock[] array entry is + * invalid or not used. (pteBlock[0] is always used.) + * SET: This parameter specifies the page size of the PTE information + * to be set. If 0, then this pteBlock[] array entry is invalid + * or not used. (pteBlock[0] is always used.) + * pteEntrySize + * GET: This parameter returns the size of the PTE in bytes for this GPU. + * SET: N/A + * comptagLine + * GET: This parameter returns the comptagline field of the corresponding PTE. + * SET: This parameter sets the comptagline field of the corresponding PTE. + * Incorrect values may lead to dire consequences. + * kind + * GET: This parameter returns the kind field of the corresponding PTE. + * SET: This parameter sets the kind field of the corresponding PTE. + * Incorrect values may lead to undesirable consequences. + * pteFlags + * This parameter returns various fields from the PTE, these are: + * FLAGS_VALID: + * GET: This flag returns the valid bit of the PTE. + * SET: This flag sets the valid bit of the PTE. + * FLAGS_ENCRYPTED: + * GET: This flag returns the encrypted bit of the PTE. Not all GPUs + * support encryption. If not supported, this flag will be set to + * NOT_SUPPORTED. + * SET: This flag sets the encrypted bit of the PTE. + * FLAGS_APERTURE: + * GET: This flag returns the aperture field of the PTE. See + * NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_FLAGS_APERTURE_* for values. + * SET: This flag sets the aperture field of the PTE. See + * NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_FLAGS_APERTURE_* for values. + * FLAGS_COMPTAGS: + * GET: This flag returns the comptags field of the PTE. (Not used on Fermi) + * SET: N/A + * FLAGS_GPU_CACHED: + * GET: This flag returns the GPU cacheable bit of the PTE. GPU caching of + * sysmem was added in iGT21a and Fermi. If not supported, this flag + * will be set to NOT_SUPPORTED. + * SET: N/A for specific chips, e.g., GF100 + * FLAGS_SHADER_ACCESS: + * GET: This flag returns the shader access control of the PTE. This feature + * was introduced in Kepler. If not supported, this flag will be set to + * NOT_SUPPORTED. + * SET: N/A + */ + +typedef struct NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK { + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); + NV_DECLARE_ALIGNED(NvU64 pteEntrySize, 8); + NvU32 comptagLine; + NvU32 kind; + NvU32 pteFlags; +} NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK; + +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID 0:0 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_TRUE (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED 2:1 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_TRUE (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_NOT_SUPPORTED (0x00000002U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE 6:3 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_VIDEO_MEMORY (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_PEER_MEMORY (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_COHERENT_MEMORY (0x00000002U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_NON_COHERENT_MEMORY (0x00000003U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS 10:7 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_NONE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_1 (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_2 (0x00000002U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_4 (0x00000004U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED 12:11 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_TRUE (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_NOT_SUPPORTED (0x00000002U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS 14:13 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_WRITE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_ONLY (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_WRITE_ONLY (0x00000002U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_NOT_SUPPORTED (0x00000003U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY 15:15 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_TRUE (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC 16:16 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_DISABLE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_ENABLE (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING 17:17 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_DISABLE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_ENABLE (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED 18:18 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_TRUE (0x00000001U) + +/* + * NV0080_CTRL_DMA_GET_PTE_INFO + * + * This command queries PTE information for the specified GPU virtual address. + * + * gpuAddr + * This parameter specifies the GPU virtual address for which PTE + * information is to be returned. + * skipVASpaceInit + * This parameter specifies(true/false) whether the VA Space + * initialization should be skipped in this ctrl call. + * pteBlocks + * This parameter returns the page size-specific attributes of a PTE. + * Please see NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK. + * hVASpace + * handle for the allocated VA space that this control call should operate + * on. If it's 0, it assumes to use the implicit allocated VA space. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + * NV_ERR_GENERIC + */ + +#define NV0080_CTRL_CMD_DMA_GET_PTE_INFO (0x801801U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS 5U + +#define NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 gpuAddr, 8); + NvU32 subDeviceId; + NvU8 skipVASpaceInit; + NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK pteBlocks[NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS], 8); + NvHandle hVASpace; +} NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS; + +/* + * NV0080_CTRL_DMA_SET_PTE_INFO + * + * This command sets PTE information for the specified GPU virtual address. + * Usage of parameter and field definitions is identical to that of + * NV0080_CTRL_DMA_GET_PTE_INFO, with the following exception: + * + * - pteFlags field NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS is ignored, + * as this setting is specified via the kind specification. + * - pteEntrySize is ignored, as this setting is read-only in the GET case. + * - hVASpace + * handle for the allocated VA space that this control call should operate + * on. If it's 0, it assumes to use the implicit allocated VA space. + * + */ + +#define NV0080_CTRL_CMD_DMA_SET_PTE_INFO (0x80180aU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS 5U + +#define NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 gpuAddr, 8); + NvU32 subDeviceId; + NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK pteBlocks[NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS], 8); + NvHandle hVASpace; +} NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS; + + +#define NV0080_CTRL_CMD_DMA_FILL_PTE_MEM (0x801802U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS { + NvU32 pageCount; + struct { + NvHandle hClient; + NvHandle hDevice; + NvHandle hMemory; + NvU32 subDeviceId; + } hwResource; + struct { + NvU32 fbKind; + NvU32 sysKind; + NvU32 compTagStartOffset; + } comprInfo; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 gpuAddr, 8); + NV_DECLARE_ALIGNED(NvP64 pageArray, 8); + NV_DECLARE_ALIGNED(NvP64 pteMem, 8); + NvU32 pteMemPfn; + NvU32 pageSize; + NvU32 startPageIndex; + NV_DECLARE_ALIGNED(NvU64 flags, 8); + NvHandle hSrcVASpace; + NvHandle hTgtVASpace; + NvU32 peerId; +} NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS; + + + +/* + * NV0080_CTRL_DMA_FLUSH + * + * This command flushes the specified target unit + * + * targetUnit + * The unit to flush, either L2 cache or compression tag cache. + * This field is a logical OR of the individual fields such as + * L2 cache or compression tag cache. Also L2 invalidation for + * either SYSMEM/PEERMEM is triggered. But this invalidation is + * for FERMI. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + * + * See Also: + * NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE + * Flushes the entire GPU cache or a set of physical addresses (if the + * hardware supports it). Use this call if you want to flush a set of + * addresses or the entire GPU cache in unicast mode. + * NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE + * Flushes memory associated with a single allocation if the hardware + * supports it. Use this call if you want to flush a single allocation and + * you have a memory object describing the physical memory. + */ +#define NV0080_CTRL_CMD_DMA_FLUSH (0x801805U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_FLUSH_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_FLUSH_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0080_CTRL_DMA_FLUSH_PARAMS { + NvU32 targetUnit; +} NV0080_CTRL_DMA_FLUSH_PARAMS; + +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2 0:0 +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_DISABLE (0x00000000U) +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_ENABLE (0x00000001U) +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG 1:1 +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_DISABLE (0x00000000U) +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_ENABLE (0x00000001U) +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB 2:2 +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_DISABLE (0x00000000U) +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_ENABLE (0x00000001U) + +// This is exclusively for Fermi +// The selection of non-zero valued bit-fields avoids the routing +// into the above cases and vice-versa +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE 4:3 +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_SYSMEM (0x00000001U) +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_PEERMEM (0x00000002U) + + +/** + * NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS + * + * This command returns information about the VA caps on the GPU + * + * vaBitCount + * Returns number of bits in a virtual address + * pdeCoverageBitCount + * Returns number of VA bits covered in each PDE. One PDE covers + * 2^pdeCoverageBitCount bytes. + * + * bigPageSize + * Size of the big page + * compressionPageSize + * Size of region each compression tag covers + * dualPageTableSupported + * TRUE if one page table can map with both 4KB and big pages + * + * numPageTableFormats + * Returns the number of different page table sizes supported by the RM + * pageTableBigFormat + * pageTable4KFormat[] + * Returns size in bytes and number of VA bits covered by each page table + * format. Up to MAX_NUM_PAGE_TABLE_FORMATS can be returned. The most + * compact format will be pageTableSize[0] and the least compact format + * will be last. + * hVASpace + * handle for the allocated VA space that this control call should operate + * on. If it's 0, it assumes to use the implicit allocated VA space. + * vaRangeLo + * Indicates the start of usable VA range. + * + * hugePageSize + * Size of the huge page if supported, 0 otherwise. + * + * vaSpaceId + * Virtual Address Space id assigned by RM. + * Only relevant on AMODEL. + * + * pageSize512MB + * Size of the 512MB page if supported, 0 otherwise. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS (0x801806U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_MESSAGE_ID" */ + +typedef struct NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT { + NvU32 pageTableSize; + NvU32 pageTableCoverage; +} NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT; + +#define NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS (16U) +#define NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS { + NvU32 vaBitCount; + NvU32 pdeCoverageBitCount; + NvU32 num4KPageTableFormats; + NvU32 bigPageSize; + NvU32 compressionPageSize; + NvU32 dualPageTableSupported; + NvU32 idealVRAMPageSize; + NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT pageTableBigFormat; + NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT pageTable4KFormat[NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS]; + NvHandle hVASpace; + NV_DECLARE_ALIGNED(NvU64 vaRangeLo, 8); + NvU32 vaSpaceId; + NV_DECLARE_ALIGNED(NvU64 supportedPageSizeMask, 8); +} NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS; + +/* + * Adding a version define to allow clients to access valid + * parameters based on version. + */ +#define NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS_WITH_VA_RANGE_LO 0x1U + +/* + * NV0080_CTRL_DMA_GET_PDE_INFO + * + * This command queries PDE information for the specified GPU virtual address. + * + * gpuAddr + * This parameter specifies the GPU virtual address for which PDE + * information is to be returned. + * pdeVirtAddr + * This parameter returns the GPU virtual address of the PDE. + * pdeEntrySize + * This parameter returns the size of the PDE in bytes for this GPU. + * pdeAddrSpace + * This parameter returns the GPU address space of the PDE. + * pdeSize + * This parameter returns the fractional size of the page table(s) as + * actually set in the PDE, FULL, 1/2, 1/4 or 1/8. (This amount may + * differ from that derived from pdeVASpaceSize.) Intended for VERIF only. + * pteBlocks + * This parameter returns the page size-specific parameters as follows: + * ptePhysAddr + * This parameter returns the GPU physical address of the page table. + * pteCacheAttrib + * This parameter returns the caching attribute of the + * GPU physical address of the page table. + * pteEntrySize + * This parameter returns the size of the PTE in bytes for this GPU. + * pageSize + * This parameter returns the page size of the page table. + * If pageSize == 0, then this PTE block is not valid. + * pteAddrSpace + * This parameter returns the GPU address space of the page table. + * pdeVASpaceSize + * This parameter returns the size of the VA space addressable by + * the page table if fully used (i.e., if all PTEs marked VALID). + * pdbAddr + * This parameter returns the PDB address for the PDE. + * hVASpace + * handle for the allocated VA space that this control call should operate + * on. If it's 0, it assumes to use the implicit allocated VA space. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV0080_CTRL_CMD_DMA_GET_PDE_INFO (0x801809U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_MESSAGE_ID" */ + +typedef struct NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK { + NV_DECLARE_ALIGNED(NvU64 ptePhysAddr, 8); + NvU32 pteCacheAttrib; + NvU32 pteEntrySize; + NvU32 pageSize; + NvU32 pteAddrSpace; + NvU32 pdeVASpaceSize; + NvU32 pdeFlags; +} NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK; + +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_VIDEO_MEMORY (0x00000000U) +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY (0x00000001U) +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY (0x00000002U) + +#define NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS 5U + +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 gpuAddr, 8); + NV_DECLARE_ALIGNED(NvU64 pdeVirtAddr, 8); + NvU32 pdeEntrySize; + NvU32 pdeAddrSpace; + NvU32 pdeSize; + NvU32 subDeviceId; + NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK pteBlocks[NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS], 8); + NV_DECLARE_ALIGNED(NvU64 pdbAddr, 8); + NvHandle hVASpace; +} NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS; + +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_VIDEO_MEMORY (0x00000000U) +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY (0x00000001U) +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY (0x00000002U) +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_FULL 1U +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_HALF 2U +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_QUARTER 3U +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_EIGHTH 4U + +/* + * NV0080_CTRL_CMD_DMA_INVALIDATE_TLB + * + * This command invalidates the GPU TLB. This is intended to be used + * for RM clients that manage their own TLB consistency when updating + * page tables on their own, or with DEFER_TLB_INVALIDATION options + * to other RM APIs. + * + * hVASpace + * This parameter specifies the VASpace object whose MMU TLB entries + * needs to be invalidated, if the flag is set to NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_FALSE. + * Specifying a GMMU VASpace object handle will invalidate the GMMU TLB for the particular VASpace. + * Specifying a SMMU VASpace object handle will flush the entire SMMU TLB & PTC. + * + * flags + * This parameter can be used to specify any flags needed + * for the invlalidation request. + * NV0080_CTRL_DMA_INVALIDATE_TLB_ALL + * When set to TRUE this flag requests a global invalidate. + * When set to FALSE this flag requests a chip-specfic + * optimization to invalidate only the address space bound + * to the associated hDevice. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_TIMEOUT_RETRY + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0080_CTRL_CMD_DMA_INVALIDATE_TLB (0x80180cU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS { + NvHandle hVASpace; + NvU32 flags; +} NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS; + +#define NV0080_CTRL_DMA_INVALIDATE_TLB_ALL 0:0 +#define NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_TRUE (0x00000001U) + +/** + * NV0080_CTRL_CMD_DMA_GET_CAPS + * + * This command returns the set of DMA capabilities for the device + * in the form of an array of unsigned bytes. DMA capabilities + * include supported features and required workarounds for address + * translation system within the device, each represented by a byte + * offset into the table and a bit position within that byte. + * + * capsTblSize + * This parameter specifies the size in bytes of the caps table. + * This value should be set to NV0080_CTRL_DMA_CAPS_TBL_SIZE. + * + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the framebuffer caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + * + * 32BIT_POINTER_ENFORCED + * If this property is TRUE NVOS32 and NVOS46 calls with + * 32BIT_POINTER_DISABLED will return addresses above 4GB. + * + * SHADER_ACCESS_SUPPORTED + * If this property is set, the MMU in the system supports the independent + * access bits for the shader. This is accessed with the following fields: + * NVOS46_FLAGS_SHADER_ACCESS + * NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_FLAGS_SHADER_ACCESS + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_DMA_GET_CAPS (0x80180dU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_GET_CAPS_PARAMS_MESSAGE_ID" */ +/* size in bytes of fb caps table */ +#define NV0080_CTRL_DMA_CAPS_TBL_SIZE 8U +#define NV0080_CTRL_DMA_GET_CAPS_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV0080_CTRL_DMA_GET_CAPS_PARAMS { + NvU32 capsTblSize; + NvU8 capsTbl[NV0080_CTRL_DMA_CAPS_TBL_SIZE]; +} NV0080_CTRL_DMA_GET_CAPS_PARAMS; + +/* extract cap bit setting from tbl */ +#define NV0080_CTRL_DMA_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* caps format is byte_index:bit_mask */ +#define NV0080_CTRL_DMA_CAPS_32BIT_POINTER_ENFORCED 0:0x01 +#define NV0080_CTRL_DMA_CAPS_SHADER_ACCESS_SUPPORTED 0:0x04 +#define NV0080_CTRL_DMA_CAPS_SPARSE_VIRTUAL_SUPPORTED 0:0x08 +#define NV0080_CTRL_DMA_CAPS_MULTIPLE_VA_SPACES_SUPPORTED 0:0x10 + +/* + * NV0080_CTRL_DMA_SET_VA_SPACE_SIZE + * + * Change the size of an existing VA space. + * NOTE: Currently this only supports growing the size, not shrinking. + * + * 1. Allocate new page directory able to map extended range. + * 2. Copy existing PDEs from old directory to new directory. + * 3. Initialize new PDEs to invalid. + * 4. Update instmem to point to new page directory. + * 5. Free old page directory. + * + * vaSpaceSize + * On input, the requested size of the VA space in bytes. + * On output, the actual resulting VA space size. + * + * The actual size will be greater than or equal to the requested size, + * unless NV0080_CTRL_DMA_GROW_VA_SPACE_SIZE_MAX is requested, which + * requests the maximum available. + * + * NOTE: Specific size requests (e.g. other than SIZE_MAX) must account + * for the VA hole at the beginning of the range which is used to + * distinguish NULL pointers. This region is not counted as part + * of the vaSpaceSize since it is not allocatable. + * + * hVASpace + * handle for the allocated VA space that this control call should operate + * on. If it's 0, it assumes to use the implicit allocated VA space + * associated with the client/device pair. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_RESOURCES + */ +#define NV0080_CTRL_CMD_DMA_SET_VA_SPACE_SIZE (0x80180eU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 vaSpaceSize, 8); + NvHandle hVASpace; +} NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS; + +#define NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_MAX (0xFFFFFFFFFFFFFFFFULL) + +/* + * NV0080_CTRL_DMA_UPDATE_PDE_2 + * + * This command updates a single PDE for the given (hClient, hDevice) + * with specific attributes. + * This command is only available on Windows and MODS platforms. + * This command can be called by kernel clients only. + * + * The VA range the PDE maps must be contained by a VA allocation marked with + * NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED. + * However if the MODS-only FORCE_OVERRIDE flag is set this restriction is relaxed. + * + * RM does not track the PDE's attributes in SW - this control simply stuffs + * the PDE in memory after translating and checking the parameters. + * + * Parameters are checked for relative consistency (e.g. valid domains), + * but it is the client's responsibility to provide correct page table + * addresses, e.g. global consistency is not checked. + * + * It is also the client's responsibility to flush/invalidate the MMU + * when appropriate, either by setting the _FLUSH_PDE_CACHE flag for this + * call or by flushing through other APIs. + * This control does not flush automatically to allow batches of calls + * to be made before a single flush. + * + * ptParams + * Page-size-specific parameters, as follows: + * + * physAddr + * Base address of physically contiguous memory of page table. + * Must be aligned sufficiently for the PDE address field. + * numEntries + * Deprecated and ignored. + * Use FLAGS_PDE_SIZE that applies to the tables for all page sizes. + * aperture + * Address space the base address applies to. + * Can be left as INVALID to ignore this page table size. + * + * pdeIndex + * The PDE index this update applies to. + * flags + * See NV0080_CTRL_DMA_UPDATE_PDE_FLAGS_*. + * hVASpace + * handle for the allocated VA space that this control call should operate + * on. If it's 0, it assumes to use the implicit allocated VA space + * associated with the client/device pair. + * pPdeBuffer [out] + * Kernel pointer to 64 bit unsigned integer representing a Page Dir Entry + * that needs to be updated. It should point to memory as wide as the Page Dir + * Entry. + * + * If NULL, Page Dir Entry updates will go to the internally managed Page Dir. + * If not NULL, the updates will be written to this buffer. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_NOT_SUPPORTED + */ +#define NV0080_CTRL_CMD_DMA_UPDATE_PDE_2 (0x80180fU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_MESSAGE_ID" */ + +typedef struct NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 physAddr, 8); + NvU32 numEntries; // deprecated + NvU32 aperture; +} NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS; + +#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_INVALID (0x00000000U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_VIDEO_MEMORY (0x00000001U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_COHERENT_MEMORY (0x00000002U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_NON_COHERENT_MEMORY (0x00000003U) + +#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_SMALL 0U +#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_BIG 1U +#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE 2U + +#define NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS { + NvU32 pdeIndex; + NvU32 flags; + NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS ptParams[NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE], 8); + NvHandle hVASpace; + NV_DECLARE_ALIGNED(NvP64 pPdeBuffer, 8); // NV_MMU_VER2_DUAL_PDE__SIZE + NvU32 subDeviceId; // ID+1, 0 for BC +} NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS; + +/*! + * If set a PDE cache flush (MMU invalidate) will be performed. + */ +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE 0:0 +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_TRUE (0x00000001U) + +/*! + * For verification purposes (MODS-only) this flag may be set to modify any PDE + * in the VA space (RM managed or externally managed). + * It is up to caller to restore any changes properly (or to expect faults). + */ +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE 1:1 +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_TRUE (0x00000001U) + +/*! + * Directly controls the PDE_SIZE field (size of the page tables pointed to by this PDE). + */ +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE 3:2 +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_FULL (0x00000000U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_HALF (0x00000001U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_QUARTER (0x00000002U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_EIGHTH (0x00000003U) + +/*! + * Used to specify if the allocation is sparse. Applicable only in case of + * VA Space managed by OS, as in WDDM2.0 + */ +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE 4:4 +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_TRUE (0x00000001U) + +/* + * NV0080_CTRL_DMA_SET_DEFAULT_VASPACE + * This is a special control call provided for KMD to use. + * It will associate an allocated Address Space Object as the + * default address space of the device. + * + * This is added so that the USER can move to using address space objects when they + * want to specify the size of the big page size they want to use but still want + * to use the rest of the relevant RM apis without specifying the hVASpace. + * + * This call will succeed only if there is already no VASPACE associated with the + * device. This means the user will have to call this before he has made any allocations + * on this device/address space. + * + * The hVASpace that is passed in to be associated shoould belong to the parent device that + * this call is made for. This call will fail if we try to associate a VASpace belonging to + * some other client/device. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + * + */ +#define NV0080_CTRL_DMA_SET_DEFAULT_VASPACE (0x801812U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS { + NvHandle hVASpace; +} NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS; + +/*! + * NV0080_CTRL_DMA_SET_PAGE_DIRECTORY + * + * Move an existing VA space to an externally-managed top-level page directory. + * The VA space must have been created in SHARED_MANAGEMENT mode. + * For lifecycle details, see NV_VASPACE_ALLOCATION_PARAMETERS documentation in nvos.h. + * + * RM will propagate the update to all channels using the VA space. + * + * NOTE: All channels using this VA space are expected to be idle and unscheduled prior + * to and during this control call - it is responsibility of caller to ensure this. + * + * physAddress + * Physical address of the new page directory within the aperture specified by flags. + * numEntries + * Number of entries in the new page directory. + * The backing phyical memory must be at least this size (multiplied by entry size). + * flags + * APERTURE + * Specifies which physical aperture the page directory resides. + * PRESERVE_PDES + * Deprecated - RM will always copy the RM-managed PDEs from the old page directory + * to the new page directory. + * ALL_CHANNELS + * If true, RM will update the instance blocks for all channels using + * the VAS and ignore the chId parameter. + * EXTEND_VASPACE + * If true, RM will use the client VA for client VA requests in VASPACE_SHARED_MANAGEMENT mode + * If false, RM will use the internal VA for client VA requests. + * IGNORE_CHANNEL_BUSY + * If true, RM will ignore the channel busy status during set page + * directory operation. + * hVASpace + * handle for the allocated VA space that this control call should operate + * on. If it's 0, it assumes to use the implicit allocated VA space + * associated with the client/device pair. + * chId + * ID of the Channel to be updated. + * pasid + * PASID (Process Address Space IDentifier) of the process corresponding to + * the VA space. Ignored unless the VA space has ATS enabled. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_LIMIT + * NV_ERR_GENERIC + */ +#define NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY (0x801813U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS { + NV_DECLARE_ALIGNED(NvU64 physAddress, 8); + NvU32 numEntries; + NvU32 flags; + NvHandle hVASpace; + NvU32 chId; + NvU32 subDeviceId; // ID+1, 0 for BC + NvU32 pasid; +} NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS; + +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE 1:0 +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_VIDMEM (0x00000000U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_COH (0x00000001U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_NONCOH (0x00000002U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES 2:2 +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_TRUE (0x00000001U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS 3:3 +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_TRUE (0x00000001U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY 4:4 +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_TRUE (0x00000001U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE 5:5 +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_TRUE (0x00000001U) + +/*! + * NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY + * + * Restore an existing VA space to an RM-managed top-level page directory. + * The VA space must have been created in SHARED_MANAGEMENT mode and + * previously relocated to an externally-managed page directory with + * NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY (these two API are symmetric operations). + * For lifecycle details, see NV_VASPACE_ALLOCATION_PARAMETERS documentation in nvos.h. + * + * RM will propagate the update to all channels using the VA space. + * + * NOTE: All channels using this VA space are expected to be idle and unscheduled prior + * to and during this control call - it is responsibility of caller to ensure this. + * + * hVASpace + * handle for the allocated VA space that this control call should operate + * on. If it's 0, it assumes to use the implicit allocated VA space + * associated with the client/device pair. + */ +#define NV0080_CTRL_CMD_DMA_UNSET_PAGE_DIRECTORY (0x801814U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS { + NvHandle hVASpace; + NvU32 subDeviceId; // ID+1, 0 for BC +} NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS; + + + +/* _ctrl0080dma_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080fb.h b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080fb.h new file mode 100644 index 0000000..7f57092 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080fb.h @@ -0,0 +1,265 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080fb.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE fb control commands and parameters */ + +/** + * NV0080_CTRL_CMD_FB_GET_CAPS + * + * This command returns the set of framebuffer capabilities for the device + * in the form of an array of unsigned bytes. Framebuffer capabilities + * include supported features and required workarounds for the framebuffer + * engine(s) within the device, each represented by a byte offset into the + * table and a bit position within that byte. + * + * capsTblSize + * This parameter specifies the size in bytes of the caps table. + * This value should be set to NV0080_CTRL_FB_CAPS_TBL_SIZE. + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the framebuffer caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_POINTER + */ +#define NV0080_CTRL_CMD_FB_GET_CAPS (0x801301) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FB_GET_CAPS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0080_CTRL_FB_GET_CAPS_PARAMS { + NvU32 capsTblSize; + NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); +} NV0080_CTRL_FB_GET_CAPS_PARAMS; + +/* extract cap bit setting from tbl */ +#define NV0080_CTRL_FB_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* caps format is byte_index:bit_mask */ +#define NV0080_CTRL_FB_CAPS_SUPPORT_RENDER_TO_SYSMEM 0:0x01 +#define NV0080_CTRL_FB_CAPS_BLOCKLINEAR 0:0x02 +#define NV0080_CTRL_FB_CAPS_SUPPORT_SCANOUT_FROM_SYSMEM 0:0x04 +#define NV0080_CTRL_FB_CAPS_SUPPORT_CACHED_SYSMEM 0:0x08 +#define NV0080_CTRL_FB_CAPS_SUPPORT_C24_COMPRESSION 0:0x10 // Deprecated +#define NV0080_CTRL_FB_CAPS_SUPPORT_SYSMEM_COMPRESSION 0:0x20 +#define NV0080_CTRL_FB_CAPS_NISO_CFG0_BUG_534680 0:0x40 // Deprecated +#define NV0080_CTRL_FB_CAPS_ISO_FETCH_ALIGN_BUG_561630 0:0x80 // Deprecated + +#define NV0080_CTRL_FB_CAPS_BLOCKLINEAR_GOBS_512 1:0x01 +#define NV0080_CTRL_FB_CAPS_L2_TAG_BUG_632241 1:0x02 +#define NV0080_CTRL_FB_CAPS_SINGLE_FB_UNIT 1:0x04 // Deprecated +#define NV0080_CTRL_FB_CAPS_CE_RMW_DISABLE_BUG_897745 1:0x08 // Deprecated +#define NV0080_CTRL_FB_CAPS_OS_OWNS_HEAP_NEED_ECC_SCRUB 1:0x10 +#define NV0080_CTRL_FB_CAPS_ASYNC_CE_L2_BYPASS_SET 1:0x20 // Deprecated +#define NV0080_CTRL_FB_CAPS_DISABLE_TILED_CACHING_INVALIDATES_WITH_ECC_BUG_1521641 1:0x40 +#define NV0080_CTRL_FB_CAPS_GENERIC_PAGE_KIND 1:0x80 + +#define NV0080_CTRL_FB_CAPS_DISABLE_MSCG_WITH_VR_BUG_1681803 2:0x01 +#define NV0080_CTRL_FB_CAPS_VIDMEM_ALLOCS_ARE_CLEARED 2:0x02 +#define NV0080_CTRL_FB_CAPS_DISABLE_PLC_GLOBALLY 2:0x04 +#define NV0080_CTRL_FB_CAPS_PLC_BUG_3046774 2:0x08 +#define NV0080_CTRL_FB_CAPS_PARTIAL_UNMAP 2:0x10 + + +/* size in bytes of fb caps table */ +#define NV0080_CTRL_FB_CAPS_TBL_SIZE 3 + + + +/*! + * NV0080_CTRL_CMD_FB_COMPBIT_STORE_GET_INFO + * + * This command returns compbit backing store-related information. + * + * size + * [out] Size of compbit store, in bytes + * address + * [out] Address of compbit store + * addressSpace + * [out] Address space of compbit store (corresponds to type NV_ADDRESS_SPACE in nvrm.h) + * maxCompbitLine + * [out] Maximum compbitline possible, determined based on size + * comptagsPerCacheLine + * [out] Number of compression tags per compression cache line, across all + * L2 slices. + * cacheLineSize + * [out] Size of compression cache line, across all L2 slices. (bytes) + * cacheLineSizePerSlice + * [out] Size of the compression cache line per slice (bytes) + * cacheLineFetchAlignment + * [out] Alignment used while fetching the compression cacheline range in FB. + * If start offset of compcacheline in FB is S and end offset is E, then + * the range to fetch to ensure entire compcacheline data is extracted is: + * (align_down(S) , align_up(E)) + * This is needed in GM20X+ because of interleaving of data in Linear FB space. + * Example - In GM204 every other 1K FB chunk of data is offset by 16K. + * backingStoreBase + * [out] Address of start of Backing Store in linear FB Physical Addr space. + * This is the actual offset in FB which HW starts using as the Backing Store and + * in general will be different from the start of the region that driver allocates + * as the backing store. This address is expected to be 2K aligned. + * gobsPerComptagPerSlice + * [out] (Only on Pascal) Number of GOBS(512 bytes of surface PA) that correspond to one 64KB comptgaline, per slice. + * One GOB stores 1 byte of compression bits. + * 0 value means this field is not applicable for the current architecture. + * backingStoreCbcBase + * [out] 2KB aligned base address of CBC (post divide address) + * comptaglineAllocationPolicy + * [out] Policy used to allocate comptagline from CBC for the device + * privRegionStartOffset + * [out] Starting offset for any priv region allocated by clients. only used by MODS + * Possible status values returned are: + * NV_OK + */ +#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO (0x801306) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 Size, 8); + NV_DECLARE_ALIGNED(NvU64 Address, 8); + NvU32 AddressSpace; + NvU32 MaxCompbitLine; + NvU32 comptagsPerCacheLine; + NvU32 cacheLineSize; + NvU32 cacheLineSizePerSlice; + NvU32 cacheLineFetchAlignment; + NV_DECLARE_ALIGNED(NvU64 backingStoreBase, 8); + NvU32 gobsPerComptagPerSlice; + NvU32 backingStoreCbcBase; + NvU32 comptaglineAllocationPolicy; + NV_DECLARE_ALIGNED(NvU64 privRegionStartOffset, 8); + NvU32 cbcCoveragePerSlice; + NV_DECLARE_ALIGNED(NvU64 cbcRegionSize, 8); +} NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS; + +#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_UNKNOWN 0 // ADDR_UNKNOWN +#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_SYSMEM 1 // ADDR_SYSMEM +#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_FBMEM 2 // ADDR_FBMEM + +// Policy used to allocate comptaglines +/** + * Legacy mode allocates a comptagline for 64kb page. This mode will always allocate + * contiguous comptaglines from a ctag heap. + */ +#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_LEGACY 0 +/** + * 1TO1 mode allocates a comptagline for 64kb page. This mode will calculate + * comptagline offset based on physical address. This mode will allocate + * contiguous comptaglines if the surface is contiguous and non-contiguous + * comptaglines for non-contiguous surfaces. + */ +#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO1 1 +/** + * 1TO4_Heap mode allocates a comptagline for 256kb page granularity. This mode + * will allocate comptagline from a heap. This mode will align the surface allocations + * to 256kb before allocating comptaglines. The comptaglines allocated will always be + * contiguous here. + * TODO: For GA10x, this mode will support < 256kb surface allocations, by sharing + * a comptagline with at most 3 different 64Kb allocations. This will result in + * miixed-contiguity config where comptaglines will be allocated contiguously as well + * as non-contiguous when shared with other allocations. + */ +#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO4 2 +/** + * Rawmode will transfer allocation of comptaglines to HW, where HW manages + * comptaglines based on physical offset. The comptaglines are cleared when SW + * issues physical/virtual scrub to the surface before reuse. + */ +#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_RAWMODE 3 + +/** + * NV0080_CTRL_CMD_FB_GET_CAPS_V2 + * + * This command returns the same set of framebuffer capabilities for the + * device as @ref NV0080_CTRL_CMD_FB_GET_CAPS. The difference is in the structure + * NV0080_CTRL_FB_GET_CAPS_V2_PARAMS, which contains a statically sized array, + * rather than a caps table pointer and a caps table size in + * NV0080_CTRL_FB_GET_CAPS_PARAMS. + * + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the framebuffer caps bits will be written by the RM. + * The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_POINTER + */ +#define NV0080_CTRL_CMD_FB_GET_CAPS_V2 (0x801307) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FB_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV0080_CTRL_FB_GET_CAPS_V2_PARAMS { + NvU8 capsTbl[NV0080_CTRL_FB_CAPS_TBL_SIZE]; +} NV0080_CTRL_FB_GET_CAPS_V2_PARAMS; + +/** + * NV0080_CTRL_CMD_FB_SET_DEFAULT_VIDMEM_PHYSICALITY + * + * When clients allocate video memory specifying _DEFAULT (0) for + * NVOS32_ATTR_PHYSICALITY, RM will usually allocate contiguous memory. + * Clients can change that behavior with this command so that _DEFAULT maps to + * another value. + * + * The expectation is that clients currently implicitly rely on the default, + * but can be incrementally updated to explicitly specify _CONTIGUOUS where + * necessary and change the default for their allocations to _NONCONTIGUOUS or + * _ALLOW_NONCONTIGUOUS. + * + * In the future RM may be updated to globally default to _NONCONTIGUOUS or + * _ALLOW_NONCONTIGUOUS, and at that point this can be removed. + */ +#define NV0080_CTRL_CMD_FB_SET_DEFAULT_VIDMEM_PHYSICALITY (0x801308) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS { + NvU32 value; +} NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS; + +typedef enum NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY { + NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_DEFAULT = 0, + NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_NONCONTIGUOUS = 1, + NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_CONTIGUOUS = 2, + NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_ALLOW_NONCONTIGUOUS = 3, +} NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY; + + +/* _ctrl0080fb_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080fifo.h b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080fifo.h new file mode 100644 index 0000000..819104d --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080fifo.h @@ -0,0 +1,403 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080fifo.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE fifo control commands and parameters */ + +/** + * NV0080_CTRL_FIFO_GET_CAPS + * + * This command returns the set of FIFO engine capabilities for the device + * in the form of an array of unsigned bytes. FIFO capabilities + * include supported features and required workarounds for the FIFO + * engine(s) within the device, each represented by a byte offset into the + * table and a bit position within that byte. + * + * capsTblSize + * This parameter specifies the size in bytes of the caps table. + * This value should be set to NV0080_CTRL_FIFO_CAPS_TBL_SIZE. + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the framebuffer caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_FIFO_GET_CAPS (0x801701) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_GET_CAPS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0080_CTRL_FIFO_GET_CAPS_PARAMS { + NvU32 capsTblSize; + NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); +} NV0080_CTRL_FIFO_GET_CAPS_PARAMS; + +/* extract cap bit setting from tbl */ +#define NV0080_CTRL_FIFO_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* caps format is byte_index:bit_mask */ +#define NV0080_CTRL_FIFO_CAPS_SUPPORT_SCHED_EVENT 0:0x01 +#define NV0080_CTRL_FIFO_CAPS_SUPPORT_PCI_PB 0:0x02 +#define NV0080_CTRL_FIFO_CAPS_SUPPORT_VID_PB 0:0x04 +#define NV0080_CTRL_FIFO_CAPS_USERD_IN_SYSMEM 0:0x40 +/* do not use pipelined PTE BLITs to update PTEs: call the RM */ +#define NV0080_CTRL_FIFO_CAPS_NO_PIPELINED_PTE_BLIT 0:0x80 +#define NV0080_CTRL_FIFO_CAPS_GPU_MAP_CHANNEL 1:0x01 +#define NV0080_CTRL_FIFO_CAPS_BUFFEREDMODE_SCHEDULING 1:0x02 // Deprecated +#define NV0080_CTRL_FIFO_CAPS_WFI_BUG_898467 1:0x08 // Deprecated +#define NV0080_CTRL_FIFO_CAPS_HAS_HOST_LB_OVERFLOW_BUG_1667921 1:0x10 +/* + * To indicate Volta subcontext support with multiple VA spaces in a TSG. + * We are not using "subcontext" tag for the property, since we also use + * subcontext to represent pre-VOlta SCG feature, which only allows a single + * VA space in a TSG. + */ +#define NV0080_CTRL_FIFO_CAPS_MULTI_VAS_PER_CHANGRP 1:0x20 + + +#define NV0080_CTRL_FIFO_CAPS_SUPPORT_WDDM_INTERLEAVING 1:0x40 +#define NV0080_CTRL_FIFO_CAPS_IS_GRCE_VALID_REQUIRED 1:0x80 + +/* size in bytes of fifo caps table */ +#define NV0080_CTRL_FIFO_CAPS_TBL_SIZE 2 + +/* + * NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES + * + * This command is used to provide the caller with the alignment and size + * of the context save region for an engine + * + * engineId + * This parameter is an input parameter specifying the engineId for which + * the alignment/size is requested. + * alignment + * This parameter is an output parameter which will be filled in with the + * minimum alignment requirement. + * size + * This parameter is an output parameter which will be filled in with the + * minimum size of the context save region for the engine. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES (0x801707) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID 4:0 +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS (0x00000000) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VLD (0x00000001) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VIDEO (0x00000002) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_MPEG (0x00000003) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_CAPTURE (0x00000004) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_DISPLAY (0x00000005) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_ENCRYPTION (0x00000006) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_POSTPROCESS (0x00000007) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ZCULL (0x00000008) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PM (0x00000009) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COMPUTE_PREEMPT (0x0000000a) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PREEMPT (0x0000000b) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SPILL (0x0000000c) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL (0x0000000d) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BETACB (0x0000000e) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV (0x0000000f) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PATCH (0x00000010) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BUNDLE_CB (0x00000011) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL_GLOBAL (0x00000012) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ATTRIBUTE_CB (0x00000013) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV_CB_GLOBAL (0x00000014) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_POOL (0x00000015) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_CTRL_BLK (0x00000016) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_FECS_EVENT (0x00000017) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PRIV_ACCESS_MAP (0x00000018) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SETUP (0x00000019) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT (0x0000001a) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS { + NvU32 engineId; + NvU32 alignment; + NvU32 size; +} NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS; + +/* + * NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST + * + * Takes a list of hChannels as input and returns the + * corresponding Channel IDs that they corresponding to + * on hw. + * + * numChannels + * Size of input hChannellist + * pChannelHandleList + * List of input channel handles + * pChannelList + * List of Channel ID's corresponding to the + * each entry in the hChannelList. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST (0x80170d) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS { + NvU32 numChannels; + NV_DECLARE_ALIGNED(NvP64 pChannelHandleList, 8); + NV_DECLARE_ALIGNED(NvP64 pChannelList, 8); +} NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS; + + +/* + * NV0080_CTRL_CMD_FIFO_GET_LATENCY_BUFFER_SIZE + * + * This control call is used to return the number of gp methods(gpsize) and push buffer methods(pbsize) + * allocated to each engine. + * + *engineID + * The engine ID which is an input + * + *gpEntries + * number of gp entries + * + *pbEntries + * number of pb entries (in units of 32B rows) + * + */ + + +#define NV0080_CTRL_CMD_FIFO_GET_LATENCY_BUFFER_SIZE (0x80170e) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS { + NvU32 engineID; + NvU32 gpEntries; + NvU32 pbEntries; +} NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS; + +#define NV0080_CTRL_FIFO_GET_CHANNELLIST_INVALID_CHANNEL (0xffffffff) + +/* + * NV0080_CTRL_CMD_FIFO_SET_CHANNEL_PROPERTIES + * + * This command allows internal properties of the channel + * to be modified even when the channel is active. Most of these properties + * are not meant to be modified during normal runs hence have been + * kept separate from channel alloc params. It is the + * responsibility of the underlying hal routine to make + * sure the channel properties are changed while the channel + * is *NOT* in a transient state. + * + * hChannel + * The handle to the channel. + * + * property + * The channel property to be modified. + * NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_xxx provides the entire list + * of properties. + * + * value + * The new value for the property. + * + * When property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_INVALIDATE_PDB_TARGET + * value is ignored + * desc: Override the channel's page directory pointer table with an + * erroneous aperture value. (TODO: make test calls NV_VERIF_FEATURES + * only)(VERIF ONLY) + * + * property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT + * value = engineID of engine that will have its context pointer reset. + * engineID defines can be found in cl2080.h + * (e.g., NV2080_ENGINE_TYPE_GRAPHICS) + * desc: Override the channel's engine context pointer with a non existent + * buffer forcing it to fault. (VERIF ONLY) + * + * property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT_NOPREEMPT + * value = engineID of engine that will have its context pointer reset. + * engineID defines can be found in cl2080.h + * (e.g., NV2080_ENGINE_TYPE_GRAPHICS) + * desc: Override the channel's engine context pointer with a non existent + * buffer forcing it to fault. However the channel will not be preempted + * before having its channel state modified.(VERIF ONLY) + * + * property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_NOOP + * value is ignored + * desc: does not change any channel state exercises a full channel preempt/ + * unbind/bind op. (VERIF ONLY) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_CHANNEL + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0080_CTRL_CMD_FIFO_SET_CHANNEL_PROPERTIES (0x80170f) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS { + NvHandle hChannel; + NvU32 property; + NV_DECLARE_ALIGNED(NvU64 value, 8); +} NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS; + +#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_INVALIDATE_PDB_TARGET (0x00000004) +#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT (0x00000005) +#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_NOOP (0x00000007) +#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT_NOPREEMPT (0x00000008) + + + +/* + * NV0080_CTRL_CMD_FIFO_STOP_RUNLIST + * + * Stops all processing on the runlist for the given engine. This is only + * valid in per-engine round-robin scheduling mode. + * + * engineID + * This parameter specifies the engine to be stopped. Engine defines + * can be found in cl2080.h. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV0080_CTRL_CMD_FIFO_STOP_RUNLIST (0x801711) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS { + NvU32 engineID; +} NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS; + +/* + * NV0080_CTRL_CMD_FIFO_START_RUNLIST + * + * Restarts a runlist previously stopped with NV0080_CTRL_CMD_FIFO_STOP_RUNLIST. + * This is only valid for per-engine round-robin mode. + * + * engineID + * This parameter specifies the engine to be started. Engine defines + * can be found in cl2080.h. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV0080_CTRL_CMD_FIFO_START_RUNLIST (0x801712) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV0080_CTRL_FIFO_START_RUNLIST_PARAMS { + NvU32 engineID; +} NV0080_CTRL_FIFO_START_RUNLIST_PARAMS; + +/** + * NV0080_CTRL_FIFO_GET_CAPS_V2 + * + * This command returns the same set of FIFO engine capabilities for the device + * as @ref NV0080_CTRL_FIFO_GET_CAPS. The difference is in the structure + * NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS, which contains a statically sized array, + * rather than a caps table pointer and a caps table size in + * NV0080_CTRL_FIFO_GET_CAPS_PARAMS. + * + * capsTbl + * This parameter is an array of the client's caps table buffer. + * The framebuffer caps bits will be written by the RM. + * The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_FIFO_GET_CAPS_V2 (0x801713) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS { + NvU8 capsTbl[NV0080_CTRL_FIFO_CAPS_TBL_SIZE]; +} NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS; + +/** + * NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS + * + * @brief This command idles (deschedules and waits for pending work to complete) channels + * belonging to a particular device. + * + * numChannels + * Number of channels to idle + * + * hChannels + * Array of channel handles to idle + * + * flags + * NVOS30_FLAGS that control aspects of how the channel is idled + * + * timeout + * GPU timeout in microseconds, for each CHID Manager's idling operation + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_TIMEOUT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_LOCK_STATE + */ +#define NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS (0x801714) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS_MESSAGE_ID" */ +#define NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS_MAX_CHANNELS 4096 + +#define NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS { + NvU32 numChannels; + NvHandle hChannels[NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS_MAX_CHANNELS]; + NvU32 flags; + NvU32 timeout; +} NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS; + +/* _ctrl0080fifo_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080gpu.h b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080gpu.h new file mode 100644 index 0000000..9ab821b --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080gpu.h @@ -0,0 +1,656 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080gpu.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" +#include "nvlimits.h" + + +/* NV01_DEVICE_XX/NV03_DEVICE gpu control commands and parameters */ + +/* + * NV0080_CTRL_CMD_GPU_GET_CLASSLIST + * + * This command returns supported class information for the specified device. + * If the device is comprised of more than one GPU, the class list represents + * the set of supported classes common to all GPUs within the device. + * + * It has two modes: + * + * If the classList pointer is NULL, then this command returns the number + * of classes supported by the device in the numClasses field. The value + * should then be used by the client to allocate a classList buffer + * large enough to hold one 32bit value per numClasses entry. + * + * If the classList pointer is non-NULL, then this command returns the + * set of supported class numbers in the specified buffer. + * + * numClasses + * If classList is NULL, then this parameter will return the + * number of classes supported by the device. If classList is non-NULL, + * then this parameter indicates the number of entries in classList. + * classList + * This parameter specifies a pointer to the client's buffer into + * which the supported class numbers should be returned. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV0080_CTRL_CMD_GPU_GET_CLASSLIST (0x800201) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS { + NvU32 numClasses; + NV_DECLARE_ALIGNED(NvP64 classList, 8); +} NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS; + +/** + * NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES + * + * This command returns the number of subdevices for the device. + * + * numSubDevices + * This parameter returns the number of subdevices within the device. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES (0x800280) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS_MESSAGE_ID (0x80U) + +typedef struct NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS { + NvU32 numSubDevices; +} NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS; + +/* + * NV0080_CTRL_CMD_GPU_GET_VIDLINK_ORDER + * + * This command returns the video link order of each subdevice id inside the + * device. This call can only be made after SLI is enabled. This call is + * intended for 3D clients to use to determine the vidlink order of the + * devices. The Display Output Parent will always be the first subdevice + * mask listed in the array. Note that this command should not be used in + * case of bridgeless SLI. The order of the subdevices returned by this + * command will not be correct in case of bridgeless SLI. + * + * ConnectionCount + * Each HW can provide 1 or 2 links between all GPUs in a device. This + * number tells how many links are available between GPUs. This data + * also represents the number of concurrent SLI heads that can run at + * the same time over this one device. + * + * Order + * This array returns the order of subdevices that are used through + * the vidlink for display output. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0080_CTRL_CMD_GPU_GET_VIDLINK_ORDER (0x800281) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS { + NvU32 ConnectionCount; + NvU32 Order[NV_MAX_SUBDEVICES]; +} NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS; + +/* + * NV0080_CTRL_CMD_GPU_SET_DISPLAY_OWNER + * + * This command sets display ownership within the device to the specified + * subdevice instance. The actual transfer of display ownership will take + * place at the next modeset. + * + * subDeviceInstance + * This member specifies the subdevice instance of the new display + * owner. The subdevice instance must be in the legal range + * indicated by the NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0080_CTRL_CMD_GPU_SET_DISPLAY_OWNER (0x800282) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS_MESSAGE_ID (0x82U) + +typedef struct NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS { + NvU32 subDeviceInstance; +} NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS; + +/* + * NV0080_CTRL_CMD_GPU_GET_DISPLAY_OWNER + * + * This command returns the subdevice instance of the current display owner + * within the device. + * + * subDeviceInstance + * This member returns the subdevice instance of the current display + * owner. The subdevice instance will be in the legal range + * indicated by the NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0080_CTRL_CMD_GPU_GET_DISPLAY_OWNER (0x800283) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS_MESSAGE_ID (0x83U) + +typedef struct NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS { + NvU32 subDeviceInstance; +} NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS; + +/* + * NV0080_CTRL_CMD_GPU_SET_VIDLINK + * + * This command enables or disables the VIDLINK of all subdevices in the + * current SLI configuration. + * + * enable + * Enables or disables the vidlink + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV0080_CTRL_CMD_GPU_SET_VIDLINK (0x800285) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_VIDLINK_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_SET_VIDLINK_PARAMS_MESSAGE_ID (0x85U) + +typedef struct NV0080_CTRL_GPU_SET_VIDLINK_PARAMS { + NvU32 enable; +} NV0080_CTRL_GPU_SET_VIDLINK_PARAMS; + +#define NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_FALSE (0x00000000) +#define NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_TRUE (0x00000001) + +/* commands */ +#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_GET_STATUS 0 +#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERDOWN 1 +#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERUP 2 + +/* status */ +#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWER_ON 0 +#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_DOWN 1 +#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_GATED 2 +#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_UP 3 + +/* + * NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE + * + * This command is used to enable or disable the persistence of a GPU's + * software state when no clients exist. With persistent software state enabled + * the GPU's software state is not torn down when the last client exits, but is + * retained until either the kernel module unloads or persistent software state + * is disabled. + * + * newState + * This input parameter is used to enable or disable the persistence of the + * software state of all subdevices within the device. + * Possible values are: + * NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED + * NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE (0x800287) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID" */ + +/* Possible values of persistentSwState */ +#define NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED (0x00000000) +#define NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED (0x00000001) + +#define NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID (0x87U) + +typedef struct NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS { + NvU32 newState; +} NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS; + +/* + * NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE + * + * swStatePersistence + * This parameter returns a value indicating if persistent software + * state is currently enabled or not for the specified GPU. See the + * description of NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE. + * Possible values are: + * NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED + * NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE (0x800288) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID (0x88U) + +typedef struct NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS { + NvU32 swStatePersistence; +} NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS; + +/** + * NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE + * + * This command returns a value indicating virtualization mode in + * which the GPU is running. + * + * virtualizationMode + * This parameter returns the virtualization mode of the device. + * Possible values are: + * NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE + * This value indicates that there is no virtualization mode associated with the + * device (i.e. it's a baremetal GPU). + * NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS + * This value indicates that the device is associated with the NMOS. + * NV0080_CTRL_GPU_VIRTUALIZATION_MODE_VGX + * This value indicates that the device is associated with VGX(guest GPU). + * NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST + * NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VGPU + * This value indicates that the device is associated with vGPU(host GPU). + * NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VSGA + * This value indicates that the device is associated with vSGA(host GPU). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE (0x800289) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE (0x00000000) +#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS (0x00000001) +#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_VGX (0x00000002) +#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST (0x00000003) +#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VGPU NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST +#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VSGA (0x00000004) + +#define NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS_MESSAGE_ID (0x89U) + +typedef struct NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS { + NvU32 virtualizationMode; + NvBool isGridBuild; +} NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS; + +/* + * NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE + * + * This command returns the setting information for sparse texture compute + * mode optimization on the associated GPU. This setting indicates how the + * large page size should be selected by the RM for the GPU. + * + * defaultSetting + * This field specifies what the OS default setting is for the associated + * GPU. See NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE for a list + * of possible values. + * currentSetting + * This field specifies which optimization mode was applied when the + * driver was loaded. See + * NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE for a list of + * possible values. + * pendingSetting + * This field specifies which optimization mode will be applied on the + * next driver reload. See + * NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE for a list of + * possible values. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE (0x80028c) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID (0x8CU) + +typedef struct NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS { + NvU32 defaultSetting; + NvU32 currentSetting; + NvU32 pendingSetting; +} NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS; + +/* + * NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE + * + * This command sets the pending setting for sparse texture compute mode. This + * setting indicates how the large page size should be selected by the RM for + * the GPU on the next driver reload. + * + * setting + * This field specifies which use case the RM should optimize the large + * page size for on the next driver reload. Possible values for this + * field are: + * NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_DEFAULT + * This value indicates that the RM should use the default setting for + * the GPU's large page size. The default setting is reported by + * NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE. + * NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_COMPUTE + * This value indicates that the RM should select the GPU's large page + * size to optimize for compute use cases. + * NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_SPARSE_TEXTURE + * This value indicates that the RM should select the GPU's large page + * size to optimize for sparse texture use cases. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +#define NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE (0x80028d) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID (0x8DU) + +typedef struct NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS { + NvU32 setting; +} NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS; + +/* Possible sparse texture compute mode setting values */ +#define NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_DEFAULT 0 +#define NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_COMPUTE 1 +#define NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_SPARSE_TEXTURE 2 + +/* + * NV0080_CTRL_CMD_GPU_GET_VGX_CAPS + * + * This command gets the VGX capability of the GPU depending on the status of + * the VGX hardware fuse. + * + * isVgx + * This field is set to NV_TRUE is VGX fuse is enabled for the GPU otherwise + * it is set to NV_FALSE. + * + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + * NVOS_STATUS_ERROR_NOT_SUPPORTED + */ +#define NV0080_CTRL_CMD_GPU_GET_VGX_CAPS (0x80028e) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS_MESSAGE_ID (0x8EU) + +typedef struct NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS { + NvBool isVgx; +} NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS; + + + +/* + * NV0080_CTRL_CMD_GPU_GET_SRIOV_CAPS + * + * This command is used to query GPU SRIOV capabilities + * totalVFs + * Total number of virtual functions supported. + * + * firstVfOffset + * Offset of the first VF. + * + * vfFeatureMask + * Bitmask of features managed by the guest + * + * FirstVFBar0Address + * Address of BAR0 region of first VF. + * + * FirstVFBar1Address + * Address of BAR1 region of first VF. + * + * FirstVFBar2Address + * Address of BAR2 region of first VF. + * + * bar0Size + * Size of BAR0 region on VF. + * + * bar1Size + * Size of BAR1 region on VF. + * + * bar2Size + * Size of BAR2 region on VF. + * + * b64bitBar0 + * If the VF BAR0 is 64-bit addressable. + * + * b64bitBar1 + * If the VF BAR1 is 64-bit addressable. + * + * b64bitBar2 + * If the VF BAR2 is 64-bit addressable. + * + * bSriovEnabled + * Flag for SR-IOV enabled or not. + * + * bSriovHeavyEnabled + * Flag for whether SR-IOV is enabled in standard or heavy mode. + * + * bEmulateVFBar0TlbInvalidationRegister + * Flag for whether VF's TLB Invalidate Register region needs emulation. + * + * bClientRmAllocatedCtxBuffer + * Flag for whether engine ctx buffer is managed by client RM. + * + * bNonPowerOf2ChannelCountSupported + * Flag for whether non power of 2 VF channels are supported. + * + * bVfResizableBAR1Supported + * Flag for whether Resizable VF BAR1 capability is supported. + * +* Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV0080_CTRL_CMD_GPU_GET_SRIOV_CAPS (0x800291) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_MESSAGE_ID (0x91U) + +typedef struct NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS { + NvU32 totalVFs; + NvU32 firstVfOffset; + NvU32 vfFeatureMask; + NV_DECLARE_ALIGNED(NvU64 FirstVFBar0Address, 8); + NV_DECLARE_ALIGNED(NvU64 FirstVFBar1Address, 8); + NV_DECLARE_ALIGNED(NvU64 FirstVFBar2Address, 8); + NV_DECLARE_ALIGNED(NvU64 bar0Size, 8); + NV_DECLARE_ALIGNED(NvU64 bar1Size, 8); + NV_DECLARE_ALIGNED(NvU64 bar2Size, 8); + NvBool b64bitBar0; + NvBool b64bitBar1; + NvBool b64bitBar2; + NvBool bSriovEnabled; + NvBool bSriovHeavyEnabled; + NvBool bEmulateVFBar0TlbInvalidationRegister; + NvBool bClientRmAllocatedCtxBuffer; + NvBool bNonPowerOf2ChannelCountSupported; + NvBool bVfResizableBAR1Supported; +} NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS; + + +// Update this macro if new HW exceeds GPU Classlist MAX_SIZE +#define NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE 200 + +#define NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 (0x800292) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID (0x92U) + +typedef struct NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS { + NvU32 numClasses; // __OUT__ + NvU32 classList[NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE]; // __OUT__ +} NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS; + +/* + * NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE + * + * Find a subdevice handle allocated under this device + */ +#define NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE (0x800293) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM_MESSAGE_ID (0x93U) + +typedef struct NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM { + NvU32 subDeviceInst; // [in] + NvHandle hSubDevice; // [out] +} NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM; + +/* + * NV0080_CTRL_CMD_GPU_GET_BRAND_CAPS + * + * This command gets branding information for the device. + * + * brands + * Mask containing branding information. A bit in this + * mask is set if the GPU has particular branding. + * + * Possible status values returned are: + * NV_OK + */ + +#define NV0080_CTRL_GPU_GET_BRAND_CAPS_QUADRO NVBIT(0) +#define NV0080_CTRL_GPU_GET_BRAND_CAPS_NVS NVBIT(1) +#define NV0080_CTRL_GPU_GET_BRAND_CAPS_TITAN NVBIT(2) + +#define NV0080_CTRL_CMD_GPU_GET_BRAND_CAPS (0x800294) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS_MESSAGE_ID (0x94U) + +typedef struct NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS { + NvU32 brands; +} NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS; + +/* + * These are the per-VF BAR1 sizes that we support in MB. + */ +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M (1 << 6) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128M (1 << 7) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256M (1 << 8) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_512M (1 << 9) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_1G (1 << 10) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_2G (1 << 11) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_4G (1 << 12) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_8G (1 << 13) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_16G (1 << 14) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_32G (1 << 15) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64G (1 << 16) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G (1 << 17) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256G (1 << 18) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MIN NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MAX NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256G + +#define NV0080_CTRL_GPU_VGPU_NUM_VFS_INVALID 0x0 + +/* + * NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE + * + * @brief Resize BAR1 per-VF on the given GPU + * vfBar1SizeMB[in] Requested VF BAR1 size in MB + * numVfs[out] Number of VFs that can be created + * given the requested BAR1 size + */ +#define NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE (0x800296) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS_MESSAGE_ID (0x96U) + +typedef struct NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS { + NvU32 vfBar1SizeMB; + NvU32 numVfs; +} NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS; + +/* + * NV0080_CTRL_CMD_GPU_SET_VGPU_HETEROGENEOUS_MODE + * + * This command set a value indicating vGPU heterogeneous mode. + * vGPU heterogeneous mode on a GPU can only be set when the command + * is running in a vGPU host device. + * + * gpuInstanceId + * GPU Instance ID or Swizz ID + * + * bHeterogeneousMode + * This parameter set the vGPU heterogeneous mode of the device. + * Possible values are: + * NV_TRUE + * This value indicates that the device will be associated with vGPU heterogeneous mode. + * NV_FALSE + * This value indicates that the device will be removed from vGPU heterogeneous mode. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_IN_USE + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0080_CTRL_CMD_GPU_SET_VGPU_HETEROGENEOUS_MODE (0x800297) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID (0x97U) + +typedef struct NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS { + NvBool bHeterogeneousMode; + NvU32 gpuInstanceId; +} NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS; + +/** + * NV0080_CTRL_CMD_GPU_GET_VGPU_HETEROGENEOUS_MODE + * + * This command returns a value indicating vGPU heterogeneous mode of + * the GPU. + * + * gpuInstanceId + * GPU Instance ID or Swizz ID + * + * bHeterogeneousMode + * This parameter returns the vGPU heterogeneous mode of the device. + * Possible values are: + * NV_TRUE + * This value indicates that the device is associated with vGPU heterogeneous mode. + * NV_FALSE + * This value indicates that the device is not in vGPU heterogeneous mode. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_GPU_GET_VGPU_HETEROGENEOUS_MODE (0x800298) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID (0x98U) + +typedef struct NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS { + NvBool bHeterogeneousMode; + NvU32 gpuInstanceId; +} NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS; + +/* _ctrl0080gpu_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080gr.h b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080gr.h new file mode 100644 index 0000000..e8cc815 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080gr.h @@ -0,0 +1,299 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080gr.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" +#include "nvcfg_sdk.h" + +typedef struct NV0080_CTRL_GR_ROUTE_INFO { + NvU32 flags; + NV_DECLARE_ALIGNED(NvU64 route, 8); +} NV0080_CTRL_GR_ROUTE_INFO; + +/* NV01_DEVICE_XX/NV03_DEVICE gr engine control commands and parameters */ + +/** + * NV0080_CTRL_CMD_GR_GET_CAPS + * + * This command returns the set of graphics capabilities for the device + * in the form of an array of unsigned bytes. Graphics capabilities + * include supported features and required workarounds for the graphics + * engine(s) within the device, each represented by a byte offset into the + * table and a bit position within that byte. + * + * capsTblSize + * This parameter specifies the size in bytes of the caps table. + * This value should be set to NV0080_CTRL_GR_CAPS_TBL_SIZE. + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the graphics caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + */ +#define NV0080_CTRL_CMD_GR_GET_CAPS (0x801102) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GR_GET_CAPS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_GR_GET_CAPS_PARAMS { + NvU32 capsTblSize; + NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); +} NV0080_CTRL_GR_GET_CAPS_PARAMS; + +/* extract cap bit setting from tbl */ +#define NV0080_CTRL_GR_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + + + +/* + * Size in bytes of gr caps table. This value should be one greater + * than the largest byte_index value above. + */ +#define NV0080_CTRL_GR_CAPS_TBL_SIZE 23 + + + +/* + * NV0080_CTRL_CMD_GR_INFO + * + * This structure represents a single 32bit graphics engine value. Clients + * request a particular graphics engine value by specifying a unique bus + * information index. + * + * Legal graphics information index values are: + * NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS + * This index is used to request the number of clip IDs supported by + * the device. + * NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 + * This index is used to request the minimum number of attributes that + * need to be enabled to avoid bug 261894. A return value of 0 + * indicates that there is no minimum and the bug is not present on this + * system. + */ +typedef NVXXXX_CTRL_XXX_INFO NV0080_CTRL_GR_INFO; + +/* valid graphics info index values */ +#define NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS (0x00000000) +#define NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 (0x00000001) +#define NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK (0x00000002) +#define NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT (0x00000003) +#define NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT (0x00000004) +#define NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE (0x00000005) +#define NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT (0x00000006) +#define NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT (0x00000007) +#define NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR (0x00000008) +#define NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT (0x00000009) +#define NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT (0x0000000A) +#define NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT (0x0000000B) +#define NV0080_CTRL_GR_INFO_INDEX_SM_VERSION (0x0000000C) +#define NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM (0x0000000D) +#define NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP (0x0000000E) +#define NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES (0x0000000F) +#define NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES (0x00000010) +#define NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY (0x00000011) +#define NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY (0x00000012) +#define NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM (0x00000013) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS (0x00000014) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS (0x00000015) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS (0x00000016) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC (0x00000017) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS (0x00000018) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS (0x00000019) +#define NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED (0x0000001A) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS (0x0000001B) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC (0x0000001C) +#define NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT (0x0000001D) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES (0x0000001E) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS (0x0000001F) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC (0x00000020) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS (0x00000021) +#define NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT (0x00000022) +#define NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT (0x00000023) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS (0x00000024) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS (0x00000025) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES (0x00000026) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC (0x00000027) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP (0x00000028) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC (0x00000029) +#define NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC (0x0000002A) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP (0x0000002B) +#define NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT (0x0000002C) +#define NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT (0x0000002D) +#define NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT (0x0000002E) + + +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC (0x00000032) + +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES (0x00000033) + + +#define NV0080_CTRL_GR_INFO_INDEX_RESERVED (0x00000033) +#define NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES (0x00000034) +#define NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES (0x00000035) +#define NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS (0x00000036) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG (0x00000037) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET (0x00000038) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET (0x00000039) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_CPC_PER_GPC (0x0000003A) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_HSHUB_NVLINK_MASK (0x0000003B) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_HSHUB_C2C_MASK (0x0000003C) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_HSHUB_PCIE_MASK (0x0000003D) + + +#define NV0080_CTRL_GR_INFO_INDEX_RESERVED1 (0x0000003E) + +/* When adding a new INDEX, please update MAX_SIZE accordingly + * NOTE: 0080 functionality is merged with 2080 functionality, so this max size + * reflects that. + */ +#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x0000003E) +#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x3f) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */ + +/* + * NV0080_CTRL_CMD_GR_GET_INFO + * + * This command returns graphics engine information for the associate GPU. + * Request to retrieve graphics information use a list of one or more + * NV0080_CTRL_GR_INFO structures. + * + * grInfoListSize + * This field specifies the number of entries on the caller's + * grInfoList. + * grInfoList + * This field specifies a pointer in the caller's address space + * to the buffer into which the bus information is to be returned. + * This buffer must be at least as big as grInfoListSize multiplied + * by the size of the NV0080_CTRL_GR_INFO structure. + */ +#define NV0080_CTRL_CMD_GR_GET_INFO (0x801104) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0080_CTRL_GR_GET_INFO_PARAMS { + NvU32 grInfoListSize; + NV_DECLARE_ALIGNED(NvP64 grInfoList, 8); +} NV0080_CTRL_GR_GET_INFO_PARAMS; + +/* + * NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE + * This command gets the current partition mode of a TSG context. + * + * NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE + * This command sets the partition mode of a TSG context. + * + * NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS + * This structure defines the parameters used for TPC partitioning mode SET/GET commands + * + * hChannelGroup [IN] + * RM Handle to the TSG + * + * mode [IN/OUT] + * Partitioning mode enum value + * For the SET cmd, this is an input parameter + * For the GET cmd, this is an output parameter + * + * bEnableAllTpcs [IN] + * Flag to enable all TPCs by default + * + * grRouteInfo[IN] + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + */ +#define NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE (0x801107) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x801108) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID" */ + +/* Enum for listing TPC partitioning modes */ +typedef enum NV0080_CTRL_GR_TPC_PARTITION_MODE { + NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE = 0, + NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC = 1, + NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC = 2, +} NV0080_CTRL_GR_TPC_PARTITION_MODE; + +typedef struct NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS { + NvHandle hChannelGroup; // [in] + NV0080_CTRL_GR_TPC_PARTITION_MODE mode; // [in/out] + NvBool bEnableAllTpcs; // [in/out] + NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); // [in] +} NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS; + +#define NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID (0x7U) + +typedef NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS; + +#define NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID (0x8U) + +typedef NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS; + +/** + * NV0080_CTRL_CMD_GR_GET_CAPS_V2 + * + * This command returns the same set of graphics capabilities for the device + * as @ref NV0080_CTRL_CMD_GR_GET_CAPS. The difference is in the structure + * NV0080_CTRL_GR_GET_INFO_V2_PARAMS, which contains a statically sized array, + * rather than a caps table pointer and a caps table size in + * NV0080_CTRL_GR_GET_INFO_PARAMS. Additionally, + * NV0080_CTRL_GR_GET_INFO_V2_PARAMS contains a parameter for specifying routing + * information, used for MIG. + * + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the graphics caps bits will be written by the RM. + * The caps table is an array of unsigned bytes. + * + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + * bCapsPopulated + * This parameter indicates that the capsTbl has been partially populated by + * previous calls to NV0080_CTRL_CMD_GR_GET_CAPS_V2 on other subdevices. + */ +#define NV0080_CTRL_CMD_GR_GET_CAPS_V2 (0x801109) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV0080_CTRL_GR_GET_CAPS_V2_PARAMS { + NvU8 capsTbl[NV0080_CTRL_GR_CAPS_TBL_SIZE]; + NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvBool bCapsPopulated; +} NV0080_CTRL_GR_GET_CAPS_V2_PARAMS; + +#define NV0080_CTRL_CMD_GR_GET_INFO_V2 (0x801110) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV0080_CTRL_GR_GET_INFO_V2_PARAMS { + NvU32 grInfoListSize; + NV0080_CTRL_GR_INFO grInfoList[NV0080_CTRL_GR_INFO_MAX_SIZE]; + NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV0080_CTRL_GR_GET_INFO_V2_PARAMS; + +/* _ctrl0080gr_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080host.h b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080host.h new file mode 100644 index 0000000..312d6d7 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080host.h @@ -0,0 +1,87 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080host.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE host control commands and parameters */ + +/* + * NV0080_CTRL_CMD_HOST_GET_CAPS + * + * This command returns the set of host capabilities for the device + * in the form of an array of unsigned bytes. Host capabilities + * include supported features and required workarounds for the host-related + * engine(s) within the device, each represented by a byte offset into + * the table and a bit position within that byte. + * + * capsTblSize + * This parameter specifies the size in bytes of the caps table. + * This value should be set to NV0080_CTRL_HOST_CAPS_TBL_SIZE. + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the host caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_POINTER + */ +#define NV0080_CTRL_CMD_HOST_GET_CAPS (0x801401) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_HOST_INTERFACE_ID << 8) | NV0080_CTRL_HOST_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_HOST_GET_CAPS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0080_CTRL_HOST_GET_CAPS_PARAMS { + NvU32 capsTblSize; + NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); +} NV0080_CTRL_HOST_GET_CAPS_PARAMS; + +/* extract cap bit setting from tbl */ +#define NV0080_CTRL_HOST_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* caps format is byte_index:bit_mask */ +#define NV0080_CTRL_HOST_CAPS_CPU_WRITE_WAR_BUG_420495 2:0x20 +#define NV0080_CTRL_HOST_CAPS_EXPLICIT_CACHE_FLUSH_REQD 2:0x40 + +/* size in bytes of host caps table */ +#define NV0080_CTRL_HOST_CAPS_TBL_SIZE 3 + +#define NV0080_CTRL_CMD_HOST_GET_CAPS_V2 (0x801402) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_HOST_INTERFACE_ID << 8) | NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS { + NvU8 capsTbl[NV0080_CTRL_HOST_CAPS_TBL_SIZE]; +} NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS; + +/* _ctrl0080host_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080internal.h b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080internal.h new file mode 100644 index 0000000..caa8d90 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080internal.h @@ -0,0 +1,148 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080internal.finn +// + +#include "ctrl0080gr.h" +#include "ctrl0080fifo.h" +#include "ctrl/ctrl0080/ctrl0080base.h" +#include "ctrl/ctrl0080/ctrl0080perf.h" + + + + +/*! + * @ref NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE + */ +#define NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE (0x802002) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID" */ + + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS { + NV_DECLARE_ALIGNED(NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS params, 8); +} NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS; + + +/*! + * @ref NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE + */ +#define NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE (0x802003) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID" */ + + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS { + NV_DECLARE_ALIGNED(NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS params, 8); +} NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS; + + +/*! + * @ref NV0080_CTRL_CMD_PERF_CUDA_LIMIT_SET_CONTROL + */ +#define NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_SET_CONTROL (0x802009) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS_MESSAGE_ID" */ + + +/*! + * This command disables cuda limit activation at teardown of the client. + */ +#define NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE (0x802004) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x4" */ + +/*! + * @ref NV0080_CTRL_CMD_PERF_SLI_GPU_BOOST_SYNC_SET_CONTROL + */ +#define NV0080_CTRL_CMD_INTERNAL_PERF_SLI_GPU_BOOST_SYNC_SET_CONTROL (0x802007) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID" */ + + + +/* + * NV0080_CTRL_CMD_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS + * + * This command will RC and disable channels permanently for the given clients. + * + * numClients + * Number of clients + * clientHandles + * List of client handles + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ + +#define NV0080_CTRL_CMD_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS (0x802008) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS_MESSAGE_ID" */ + +#define NV_FIFO_PERMANENTLY_DISABLE_CHANNELS_MAX_CLIENTS 200U + +#define NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS_MESSAGE_ID (0x08U) + +typedef struct NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS { + NvU32 numClients; + NvHandle clientHandles[NV_FIFO_PERMANENTLY_DISABLE_CHANNELS_MAX_CLIENTS]; +} NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS; + +/*! + * NV0080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED + * + * Tell Physical RM whether any ZBC-kind surfaces are allocated. + * If PF and all VFs report false, ZBC table can be flushed by Physical RM. + * + * bZbcReferenced [IN] + * NV_TRUE -> ZBC-kind (and no _SKIP_ZBCREFCOUNT flag) are allocated in Kernel RM + * + */ +#define NV0080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED (0x80200a) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID (0x0AU) + +typedef struct NV0080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS { + NvBool bZbcSurfacesExist; +} NV0080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS; + + + +#define NV0080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x45U) + +typedef struct NV0080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS { + NvBool bTeardown; +} NV0080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS; + +#define NV0080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR (0x802046) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID" */ +#define NV0080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x46U) + +typedef NV0080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS NV0080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS; + +/* ctrl0080internal_h */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080nvdec.h b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080nvdec.h new file mode 100644 index 0000000..5f4b277 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080nvdec.h @@ -0,0 +1,117 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080nvdec.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE bit stream processor control commands and parameters */ + +/* + * NV0080_CTRL_CMD_NVDEC_GET_CAPS + * + * This command returns the set of NVDEC capabilities for the device + * in the form of an array of unsigned bytes. NVDEC capabilities + * include supported features and required workarounds for the decoder + * within the device, each represented by a byte offset into the + * table and a bit position within that byte. + * + * capsTblSize + * This parameter specifies the size in bytes of the caps table. + * This value should be set to NV0080_CTRL_NVDEC_CAPS_TBL_SIZE. + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the NVDEC caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + * instanceId + * This parameter specifies the instance Id of NVDEC for which + * cap bits are requested. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0080_CTRL_CMD_NVDEC_GET_CAPS (0x801c01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_NVDEC_INTERFACE_ID << 8) | NV0080_CTRL_NVDEC_GET_CAPS_PARAMS_MESSAGE_ID" */ +#define NV0080_CTRL_CMD_BSP_GET_CAPS NV0080_CTRL_CMD_NVDEC_GET_CAPS + +#define NV0080_CTRL_NVDEC_GET_CAPS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0080_CTRL_NVDEC_GET_CAPS_PARAMS { + NvU32 capsTblSize; + NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); + NvU32 instanceId; +} NV0080_CTRL_NVDEC_GET_CAPS_PARAMS; +#define NV0080_CTRL_BSP_GET_CAPS_PARAMS NV0080_CTRL_NVDEC_GET_CAPS_PARAMS + + + +/* + * Size in bytes of nvdec caps table. This value should be one greater + * than the largest byte_index value above. + */ +#define NV0080_CTRL_NVDEC_CAPS_TBL_SIZE 8 +#define NV0080_CTRL_BSP_CAPS_TBL_SIZE NV0080_CTRL_NVDEC_CAPS_TBL_SIZE + +/* + * NV0080_CTRL_CMD_NVDEC_GET_CAPS_V2 + * + * This command returns the set of NVDEC capabilities for the device + * in the form of an array of unsigned bytes. NVDEC capabilities + * include supported features and required workarounds for the decoder + * within the device, each represented by a byte offset into the + * table and a bit position within that byte. + * (The V2 version flattens the capsTbl array pointer). + * + * capsTbl + * This parameter is an array of unsigned bytes where the NVDEC caps bits + * will be transferred by the RM. + * instanceId + * This parameter specifies the instance Id of NVDEC for which + * cap bits are requested. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0080_CTRL_CMD_NVDEC_GET_CAPS_V2 (0x801c02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_NVDEC_INTERFACE_ID << 8) | NV0080_CTRL_NVDEC_GET_CAPS_PARAMS_V2_MESSAGE_ID" */ +#define NV0080_CTRL_CMD_BSP_GET_CAPS_V2 NV0080_CTRL_CMD_NVDEC_GET_CAPS_V2 + +#define NV0080_CTRL_NVDEC_GET_CAPS_PARAMS_V2_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_NVDEC_GET_CAPS_PARAMS_V2 { + NvU8 capsTbl[NV0080_CTRL_NVDEC_CAPS_TBL_SIZE]; + NvU32 instanceId; +} NV0080_CTRL_NVDEC_GET_CAPS_PARAMS_V2; + +/* _ctrl0080nvdec_h_ */ +#define NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2 NV0080_CTRL_NVDEC_GET_CAPS_PARAMS_V2 diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080nvenc.h b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080nvenc.h new file mode 100644 index 0000000..cafb281 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080nvenc.h @@ -0,0 +1,96 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080nvenc.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE NVENC control commands and parameters */ + +/* + * NV0080_CTRL_CMD_NVENC_GET_CAPS + * + * This command returns the set of NVENC capabilities for the device + * in the form of an array of unsigned bytes. NVENC capabilities + * include supported features and required workarounds for the NVENC-related + * engine(s) within the device, each represented by a byte offset into + * the table and a bit position within that byte. + * + * capsTblSize + * This parameter specifies the size in bytes of the caps table. + * This value should be set to NV0080_CTRL_NVENC_CAPS_TBL_SIZE. + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the NVENC caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_NVENC_GET_CAPS (0x801b01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_NVENC_INTERFACE_ID << 8) | NV0080_CTRL_NVENC_GET_CAPS_PARAMS_MESSAGE_ID" */ +#define NV0080_CTRL_CMD_MSENC_GET_CAPS NV0080_CTRL_CMD_NVENC_GET_CAPS + +#define NV0080_CTRL_NVENC_GET_CAPS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0080_CTRL_NVENC_GET_CAPS_PARAMS { + NvU32 capsTblSize; + NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); +} NV0080_CTRL_NVENC_GET_CAPS_PARAMS; +#define NV0080_CTRL_MSENC_GET_CAPS_PARAMS NV0080_CTRL_NVENC_GET_CAPS_PARAMS + + + +/* size in bytes of NVENC caps table */ +#define NV0080_CTRL_NVENC_CAPS_TBL_SIZE 6 +#define NV0080_CTRL_MSENC_CAPS_TBL_SIZE NV0080_CTRL_NVENC_CAPS_TBL_SIZE + +/* + * NV0080_CTRL_CMD_NVENC_GET_CAPS_V2 + * + * This command is a version of NV0080_CTRL_CMD_NVENC_GET_CAPS with caps passed inline in capsTbl. + * + * For consistency with other video caps controls, it adds `instanceId` parameter. Currently it is + * ignored. + */ +#define NV0080_CTRL_CMD_NVENC_GET_CAPS_V2 (0x801b02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_NVENC_INTERFACE_ID << 8) | NV0080_CTRL_NVENC_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ +#define NV0080_CTRL_CMD_MSENC_GET_CAPS_V2 NV0080_CTRL_CMD_NVENC_GET_CAPS_V2 + +#define NV0080_CTRL_NVENC_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_NVENC_GET_CAPS_V2_PARAMS { + NvU8 capsTbl[NV0080_CTRL_NVENC_CAPS_TBL_SIZE]; + NvU32 instanceId; // ignored +} NV0080_CTRL_NVENC_GET_CAPS_V2_PARAMS; + + +/* _ctrl0080nvenc_h_ */ +#define NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS NV0080_CTRL_NVENC_GET_CAPS_V2_PARAMS diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080nvjpg.h b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080nvjpg.h new file mode 100644 index 0000000..dd3c662 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080nvjpg.h @@ -0,0 +1,75 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080nvjpg.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE NVJPG control commands and parameters */ + + + +/* + * Size in bytes of NVJPG caps table. This value should be one greater + * than the largest byte_index value above. + */ +#define NV0080_CTRL_NVJPG_CAPS_TBL_SIZE 9 + +/* + * NV0080_CTRL_CMD_NVJPG_GET_CAPS_V2 + * + * This command returns the set of NVJPG capabilities for the device + * in the form of an array of unsigned bytes. NVJPG capabilities + * include supported features of the NVJPG engine(s) within the device, + * each represented by a byte offset into the table and a bit position within + * that byte. + * + * [out] capsTbl + * This caps table array is where the NVJPG caps bits will be transferred + * by the RM. The caps table is an array of unsigned bytes. + * instanceId + * This parameter specifies the instance Id of NVDEC for which + * cap bits are requested. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_NVJPG_GET_CAPS_V2 (0x801f02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_NVJPG_INTERFACE_ID << 8) | NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS { + NvU8 capsTbl[NV0080_CTRL_NVJPG_CAPS_TBL_SIZE]; + NvU32 instanceId; +} NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS; + +/* _ctrl0080NVJPG_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080perf.h b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080perf.h new file mode 100644 index 0000000..1768aa7 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080perf.h @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080perf.finn +// + +#define NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS { + NvBool bActivate; +} NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS; + +#define NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS { + NvBool bCudaLimit; +} NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS; + + +/* + * This command sets the control information pertaining to Cuda limit. + * + * bCudaLimit + * When set to TRUE, clocks will be limited based on Cuda. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_STATE + */ +#define NV0080_CTRL_CMD_PERF_CUDA_LIMIT_SET_CONTROL (0x801909) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_PERF_INTERFACE_ID << 8) | NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS_MESSAGE_ID" */ + + + +/* _ctrl0080perf_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080unix.h b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080unix.h new file mode 100644 index 0000000..cceb42f --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0080/ctrl0080unix.h @@ -0,0 +1,95 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080unix.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE UNIX-specific control commands and parameters */ + +/* + * NV0080_CTRL_CMD_OS_UNIX_VT_SWITCH + * + * This command notifies RM to save or restore the current console state. It is + * intended to be called just before the display driver starts using the display + * engine, and after it has finished using it. + * + * cmd + * Indicates which operation should be performed. + * + * SAVE_VT_STATE + * Records the current state of the console, to be restored later. + * RESTORE_VT_STATE + * Restores the previously-saved console state. + * + * fbInfo + * Returns information about the system's framebuffer console, if one + * exists. If no console is present, all fields will be zero. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_OS_UNIX_VT_SWITCH (0x801e01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS { + NvU32 cmd; /* in */ +} NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS; + +/* Called when the display driver needs RM to save the console data, + * which will be used in RM based console restore */ +#define NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_SAVE_VT_STATE (0x00000001) + +/* Called when the display driver needs RM to restore the console */ +#define NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_RESTORE_VT_STATE (0x00000002) + +/* Called when the display driver has restored the console -- RM doesn't + * need to do anything further, but needs to be informed to avoid turning the + * GPU off and thus destroying the console state. */ +#define NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_CONSOLE_RESTORED (0x00000003) + +#define NV0080_CTRL_CMD_OS_UNIX_VT_GET_FB_INFO (0x801e02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS { + NvU32 subDeviceInstance; /* out */ + + NvU16 width; /* out */ + NvU16 height; /* out */ + NvU16 depth; /* out */ + NvU16 pitch; /* out */ + NV_DECLARE_ALIGNED(NvU64 baseAddress, 8); /* out */ + NV_DECLARE_ALIGNED(NvU64 size, 8); /* out */ +} NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS; + +/* _ctrl0080unix_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0090.h b/userspace/sdks/nv570/inc/ctrl/ctrl0090.h new file mode 100644 index 0000000..95b8902 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0090.h @@ -0,0 +1,154 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0090.finn +// + + + +// NV0080_CTRL_GR_TPC_PARTITION_MODE +#include "ctrl/ctrl0080/ctrl0080gr.h" + +/*! + * This file defines control call interfaces for the KernelGraphicsContext + * objects Each channel running within a TSG contains a HW context represented + * by the above object(s). GR permits multiple channels to share a single + * context, and these APIs operate upon that context and may be issued from any + * TSG, channel, or context handle. + */ + +/* + * NV0090_CTRL_CMD_NULL + * + * @brief This command does nothing. + * + * @return NV_OK + */ +#define NV0090_CTRL_CMD_NULL (0x900100) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x0" */ + +/*! + * NV0090_CTRL_CMD_SET_TPC_PARTITION_MODE + * NV0090_CTRL_CMD_GET_TPC_PARTITION_MODE + * + * @brief sets or gets the TPC partition mode for this context + * + * @param[in/out] mode Partitioning mode enum value + * @param[in/out] bEnableAllTpcs Flag to enable all TPCs by default + * + * @return NV_OK on success + * NV_ERR_OBJECT_NOT_FOUND if issued on non-GR ctx + */ +typedef struct NV0090_CTRL_TPC_PARTITION_MODE_PARAMS { + NV0080_CTRL_GR_TPC_PARTITION_MODE mode; + NvBool bEnableAllTpcs; +} NV0090_CTRL_TPC_PARTITION_MODE_PARAMS; + +#define NV0090_CTRL_CMD_SET_TPC_PARTITION_MODE (0x900101) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x1" */ +#define NV0090_CTRL_CMD_INTERNAL_SET_TPC_PARTITION_MODE (0x900102) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x2" */ +#define NV0090_CTRL_CMD_GET_TPC_PARTITION_MODE (0x900103) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x3" */ +#define NV0090_CTRL_CMD_INTERNAL_GET_TPC_PARTITION_MODE (0x900104) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x4" */ + +/** + * NV0090_CTRL_GET_MMU_DEBUG_MODE + * + * @brief retrieve the current MMU debug mode for the grctx according to the HW + * + * @param[out] bMode current MMU debug mode + */ +typedef struct NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS { + NvBool bMode; +} NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS; + +#define NV0090_CTRL_CMD_GET_MMU_DEBUG_MODE (0x900105) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x5" */ +#define NV0090_CTRL_CMD_INTERNAL_GET_MMU_DEBUG_MODE (0x900106) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x6" */ + +/** + * NV0090_CTRL_PROGRAM_VIDEMEM_PROMOTE + * + * @brief This control call is used to set the promotion policies to vidmem through + * per-TSG config + * + * If the request is for less bytes than the current PROMOTE setting, then + * the request is promoted. For example if the request size is for 32B and + * 64B promotion is turned on for that unit, then the request to FB will be + * for all the bytes to the 64B aligned address. + * + * @param[in] l1 + * An input parameter which represents VIDMEM_L1_PROMOTE[17:16]. + * @param[in] t1 + * An input parameter which represents VIDMEM_T1_PROMOTE[19:18]. + * + * @return NV_OK on success, or + * NV_ERR_INVALID_ARGUMENT or + * NV_ERR_INVALID_STATE + */ +typedef enum NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE { + NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_NONE = 0, + NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_64B = 1, + NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_128B = 2, +} NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE; + +typedef struct NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD { + NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE size; +} NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD; + +#define NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS { + NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD l1; + NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD t1; +} NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS; + +#define NV0090_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE (0x900107) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x7" */ +#define NV0090_CTRL_CMD_INTERNAL_PROGRAM_VIDMEM_PROMOTE (0x900108) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x8" */ + +/* + * NV0090_CTRL_SET_LG_SECTOR_PROMOTION + * + * This command toggles the type of LG sector promotion used by writing to NV_PTPC_PRI_SM_L1TAG_CTRL_SECTOR_PROMOTE_GLOBAL and NV_PTPC_PRI_SM_L1TAG_CTRL2_SECTOR_PROMOTE_GLOBAL_EXT + * + * promoType[IN] + * This parameter specifies what kind of sector promotion to perform + * + */ +typedef enum NV0090_CTRL_SET_LG_SECTOR_PROMOTION_TYPE { + NV0090_CTRL_SET_LG_SECTOR_PROMOTION_NONE = 0, + NV0090_CTRL_SET_LG_SECTOR_PROMOTION_64B = 1, + NV0090_CTRL_SET_LG_SECTOR_PROMOTION_128B = 2, +} NV0090_CTRL_SET_LG_SECTOR_PROMOTION_TYPE; + +#define NV0090_CTRL_SET_LG_SECTOR_PROMOTION_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV0090_CTRL_SET_LG_SECTOR_PROMOTION_PARAMS { + NV0090_CTRL_SET_LG_SECTOR_PROMOTION_TYPE promoType; +} NV0090_CTRL_SET_LG_SECTOR_PROMOTION_PARAMS; + +#define NV0090_CTRL_CMD_SET_LG_SECTOR_PROMOTION (0x90010bU) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0xB" */ +#define NV0090_CTRL_CMD_INTERNAL_SET_LG_SECTOR_PROMOTION (0x90010cU) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0xC" */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl00da.h b/userspace/sdks/nv570/inc/ctrl/ctrl00da.h new file mode 100644 index 0000000..d404f06 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl00da.h @@ -0,0 +1,258 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl00da.finn +// + + + +/* NV_SEMAPHORE_SURFACE control commands and parameters */ + +#define NV_SEMAPHORE_SURFACE_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x00DA, NV00DA_CTRL_##cat, idx) + +/* +* NV_SEMAPHORE_SURFACE_CTRL_CMD_REF_MEMORY +* Duplicate the memory object(s) bound to the semaphore surface into the RM +* client of the caller. +* +* The handle values are generated and returned by resource manager if the +* client specified a handle value of zero. +* +* If the semaphore surface has a valid max submitted value memory object, but +* the GPU + system do not require separate max submitted value and semaphore +* value surfaces, the handles provided by the client must be equal, and the +* handles returned by resource manager will also be equal. In such cases, the +* client must recognize that both handles correspond to a single reference to +* a single object, and hence the handle must be freed only once by the client. +* +* If the GPU does not require a max submitted value memory object, the handle +* value must be set to zero and the returned handle will always be zero as +* well. +* +* RETURNS: +* NVOS_STATUS_SUCCESS if the memory object(s) were successfully duplicated +* into the calling client. +* NVOS_STATUS_ERROR_INVALID_PARAMETER if any of the rules regarding the +* max submitted value handle value were violated. +* An error code forwarded from NvRmDupObject for any other failures. +*/ +#define NV_SEMAPHORE_SURFACE_CTRL_CMD_REF_MEMORY (0xda0001) /* finn: Evaluated from "(FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID << 8) | NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS_MESSAGE_ID" */ + +#define NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS_MESSAGE_ID (0x01U) + +typedef struct NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS { + NvHandle hSemaphoreMem; + NvHandle hMaxSubmittedMem; +} NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS; + +/* +* Currently no known usages that require more than two indices per channel: +* +* 1) The channel's associated backend engine's TRAP interrupt. +* 2) The frontend/GPFIFO's non-stall interrupt. +* +* The remaining slots are for futureproofing purposes only. +*/ +#define NV_SEMAPHORE_SURFACE_CTRL_CMD_BIND_CHANNEL_MAX_INDICES 8 + +/* +* NV_SEMAPHORE_SURFACE_CTRL_CMD_BIND_CHANNEL +* Associates a channel with the semaphore surface. All channels which will +* wait on or signal semaphores in a semaphore surface should first register +* with it to ensure proper event delivery and error handling. +* +* numNotifyIndices is the number of valid entries in notifyIndices. +* +* notifyIndices is an array of notifier indices corresponding to the engines +* the caller may use to signal a semaphore in the semaphore surface. See +* cl2080_notifiers.h for a list of notifier indices. For example, this would +* indicate a channel using the GR0(graphics/compute) and FIFO TRAP method +* (GPFIFO) notifiers to signal semaphores. +* +* params.hChannel = myChannelHandle; +* params.numNotifyIndices = 2; +* params.notifyIndex[0] = NV2080_NOTIFIERS_GR0; +* params.notifyIndex[1] = NV2080_NOTIFIERS_FIFO_EVENT_MTHD; +* +* If the specified channel will only be used to wait for semaphores, set +* numNotifyIndices to 0. +* +* RETURNS: +* NVOS_STATUS_SUCCESS if the channel and notification indices were +* successfully bound. +* NVOS_STATUS_ERROR_INVALID_OBJECT_HANDLE if hChannel does not refer an object +* in the client. +* NVOS_STATUS_ERROR_INVALID_OBJECT_ERROR if hChannel does not refer to a valid +* channel object. +* NVOS_STATUS_ERROR_INVALID_PARAMETER if numNotifyIndices is greater than +* NV_SEMAPHORE_SURFACE_CTRL_CMD_BIND_CHANNEL_MAX_INDICES. +* NVOS_STATUS_ERROR_NOT_SUPPORTED if the notifyIndex is not a valid +* notification index. +* NVOS_STATUS_ERROR_INVALID_STATE if an internal inconsistency is found in the +* binding tracking logic. +* NV_ERR_NO_MEMORY if memory could not be allocated for internal tracking +* structures. +*/ +#define NV_SEMAPHORE_SURFACE_CTRL_CMD_BIND_CHANNEL (0xda0002) /* finn: Evaluated from "(FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID << 8) | NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS_MESSAGE_ID (0x02U) + +typedef struct NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS { + NvHandle hChannel; + NvU32 numNotifyIndices; + NvU32 notifyIndices[NV_SEMAPHORE_SURFACE_CTRL_CMD_BIND_CHANNEL_MAX_INDICES]; +} NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS; + +/* +* NV_SEMAPHORE_SURFACE_CTRL_CMD_UNBIND_CHANNEL +* Dissociate a channel and a semaphore surface. Before freeing a channel +* object, it should be dissociated from all semaphore surfaces to which it has +* been bound. +* +* hChannel is a valid channel object handle which has previously been bound +* to the semaphore surface. +* +* numNotifyIndices is the number of valid entries in the notifyIndices array. +* the hChannel handle. +* +* notifyIndices is the array of notifier indices that was bound to the +* semaphore surface with the hChannel handle. + +* RETURNS: +* NVOS_STATUS_SUCCESS if the channel and notification indices were +* successfully unbound. +* NVOS_STATUS_ERROR_INVALID_OBJECT_HANDLE if hChannel does not refer an object +* in the client. +* NVOS_STATUS_ERROR_INVALID_OBJECT_ERROR if hChannel does not refer to a valid +* channel object. +* NVOS_STATUS_ERROR_INVALID_PARAMETER if numNotifyIndices is greater than +* NV_SEMAPHORE_SURFACE_CTRL_CMD_BIND_CHANNEL_MAX_INDICES. +* NVOS_STATUS_ERROR_INVALID_STATE if no binding associated with the specified +* channel and notification indices is found. +*/ +#define NV_SEMAPHORE_SURFACE_CTRL_CMD_UNBIND_CHANNEL (0xda0006) /* finn: Evaluated from "(FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID << 8) | NV_SEMAPHORE_SURFACE_CTRL_UNBIND_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NV_SEMAPHORE_SURFACE_CTRL_UNBIND_CHANNEL_PARAMS_MESSAGE_ID (0x06U) + +typedef struct NV_SEMAPHORE_SURFACE_CTRL_UNBIND_CHANNEL_PARAMS { + NvHandle hChannel; + NvU32 numNotifyIndices; + NvU32 notifyIndices[NV_SEMAPHORE_SURFACE_CTRL_CMD_BIND_CHANNEL_MAX_INDICES]; +} NV_SEMAPHORE_SURFACE_CTRL_UNBIND_CHANNEL_PARAMS; + +/* +* NV_SEMAPHORE_SURFACE_CTRL_CMD_REGISTER_WAITER +* Ask RM to signal the specified OS event and/or set the semaphore to a new +* value when the value at the specified index is >= a desired value. +* +* index - Specifies the semaphore slot within the surface to which the the wait +* applies. +* waitValue - The value to wait for. +* newValue - Specifies a value to set the semaphore to automatically when the +* specified semaphore slot reaches waitValue. "0" means the semaphore +* value is not altered by this waiter. +* notificationHandle - The OS event (kernel callback or userspace event +* handle) to notify when the value is reached, or 0 if no notification +* is required. +* +* The waiter must specify at least one action. +* +* RETURNS: +* NVOS_STATUS_SUCCESS if the waitValue has not been reached and a waiter was +* successfully registered +* NVOS_STATUS_SUCCESS if the waitValue has been reached, newValue was applied, +* and notificationHandle was 0 (No notification was requested). +* NVOS_STATUS_ERROR_ALREADY_SIGNALLED if the waitValue has been reached and +* newValue was applied if it was not 0, but no notification was registered +* or generated on notificationHandle. Other notifications generated as a +* side effect of newValue being applied, if any, were generated. +* NVOS_STATUS_ERROR_STATE_IN_USE if newValue is not 0 and the specified index +* already has an auto-update value registered. No waiter is registered. +* NVOS_STATUS_ERROR_STATE_IN_USE if the specified notification handle is +* already registered as a waiter for the specified wait_value at the +* specified index. +* already has an auto-update value registered. No waiter is registered. +* NVOS_STATUS_ERROR_* miscelaneous internal errors. No waiter is registered. +*/ +#define NV_SEMAPHORE_SURFACE_CTRL_CMD_REGISTER_WAITER (0xda0003) /* finn: Evaluated from "(FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID << 8) | NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS_MESSAGE_ID" */ + +#define NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS_MESSAGE_ID (0x03U) + +typedef struct NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS { + NV_DECLARE_ALIGNED(NvU64 index, 8); + NV_DECLARE_ALIGNED(NvU64 waitValue, 8); + NV_DECLARE_ALIGNED(NvU64 newValue, 8); + NV_DECLARE_ALIGNED(NvU64 notificationHandle, 8); +} NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS; + +/* +* NV_SEMAPHORE_SURFACE_CTRL_CMD_SET_VALUE +* Modify a semaphore surface semaphore value, awakening any CPU waiters in +* the process. newValue must be >= the current value at the specified index. +*/ +#define NV_SEMAPHORE_SURFACE_CTRL_CMD_SET_VALUE (0xda0004) /* finn: Evaluated from "(FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID << 8) | NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS_MESSAGE_ID" */ + +#define NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS_MESSAGE_ID (0x04U) + +typedef struct NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 index, 8); + NV_DECLARE_ALIGNED(NvU64 newValue, 8); +} NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS; + +/* +* NV_SEMAPHORE_SURFACE_CTRL_CMD_UNREGISTER_WAITER +* Remove a previously registered notification handle from an index + value +* tuple's list of waiters. +* +* index - Specifies the semaphore slot within the surface on which the waiter +* was previously registered. +* waitValue - The value the wait was registered for. +* notificationHandle - The OS event (kernel callback or userspace event +* handle) registered as a waiter. +* +* RETURNS: +* NVOS_STATUS_SUCCESS the waiter was successfully removed from the list of +* pending waiters. +* NVOS_STATUS_ERROR_* miscelaneous internal errors, or the waiter was not +* found in the list of pending waiters. The waiter may have already been +* called, or may be in a list of imminent notifications the RM is +* processing. +*/ +#define NV_SEMAPHORE_SURFACE_CTRL_CMD_UNREGISTER_WAITER (0xda0005) /* finn: Evaluated from "(FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID << 8) | NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS_MESSAGE_ID" */ + +#define NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS_MESSAGE_ID (0x05U) + +typedef struct NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS { + NV_DECLARE_ALIGNED(NvU64 index, 8); + NV_DECLARE_ALIGNED(NvU64 waitValue, 8); + NV_DECLARE_ALIGNED(NvU64 notificationHandle, 8); +} NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS; + +/* _ctrl00da_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl00de.h b/userspace/sdks/nv570/inc/ctrl/ctrl00de.h new file mode 100644 index 0000000..0194451 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl00de.h @@ -0,0 +1,98 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl00de.finn +// + +#include "ctrl/ctrlxxxx.h" + +#define NV00DE_CTRL_CMD(cat, idx) NVXXXX_CTRL_CMD(0x00de, NV00DE_CTRL_##cat, idx) + +/* RM_USER_SHARED_DATA control commands and parameters */ + +/* + * NV00DE_CTRL_CMD_REQUEST_DATA_POLL + * + * @brief Request some polled data elements to be updated + * Equivalent to requesting polling using NV00DE_ALLOC_PARAMETERS->polledDataMask + * See cl00de.h for mask bits + * + * @param[in] polledDataMask Bitmask of data to be updated + * + * @return NV_OK on success + * @return NV_ERR_ otherwise + */ +#define NV00DE_CTRL_CMD_REQUEST_DATA_POLL (0xde0001U) /* finn: Evaluated from "(FINN_RM_USER_SHARED_DATA_INTERFACE_ID << 8) | NV00DE_CTRL_REQUEST_DATA_POLL_PARAMS_MESSAGE_ID" */ + +#define NV00DE_CTRL_REQUEST_DATA_POLL_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV00DE_CTRL_REQUEST_DATA_POLL_PARAMS { + NV_DECLARE_ALIGNED(NvU64 polledDataMask, 8); +} NV00DE_CTRL_REQUEST_DATA_POLL_PARAMS; + +#define NV00DE_RUSD_POLLING_INTERVAL_MIN 100 + +/* + * NV00DE_CTRL_CMD_REQUEST_POLL_INTERVAL + * + * @brief Privileged control to set RUSD polling interval. + * Valid interval is between NV00DE_RUSD_POLLING_INTERVAL_MIN and + * the default value (decided by SKU and can be overriden by regkey). + * A 0 polling interval is a special value that resets the interval for + * this RUSD instance to the default value. + * Polling interval less than NV00DE_RUSD_POLLING_INTERVAL_MIN is + * invalid. Polling interval greater than the default value is considered + * a reset to default value as well. The reason is that a polling interval + * request from client is considered satisfied as long as RUSD polls more + * frequently than the request. The clients do not need to know the + * default or actual frequency that RUSD is running. Hence, we don't + * return an error when client requests a polling frequency higher than + * the default value. + * + * RUSD will poll at the minimum of all requested polling intervals that + * are valid. + * + * The polling interval can change when: + * 1. A client requests a polling interval + * 2. A client is freed + * + * @param[in] pollingIntervalMs + * + * @return NV_OK on success + * NV_ERR_ otherwise + */ +#define NV00DE_CTRL_CMD_REQUEST_POLL_INTERVAL (0xde0002U) /* finn: Evaluated from "(FINN_RM_USER_SHARED_DATA_INTERFACE_ID << 8) | NV00DE_CTRL_REQUEST_POLL_INTERVAL_PARAM_MESSAGE_ID" */ + +#define NV00DE_CTRL_REQUEST_POLL_INTERVAL_PARAM_MESSAGE_ID (0x2U) + +typedef struct NV00DE_CTRL_REQUEST_POLL_INTERVAL_PARAM { + NvU32 pollingIntervalMs; +} NV00DE_CTRL_REQUEST_POLL_INTERVAL_PARAM; + +/* _ctrl00de.h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl00e0.h b/userspace/sdks/nv570/inc/ctrl/ctrl00e0.h new file mode 100644 index 0000000..1f34700 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl00e0.h @@ -0,0 +1,158 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl00e0.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "class/cl00e0.h" + +#define NV00E0_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x00E0, NV00E0_CTRL_##cat, idx) + +/* NV00E0 command categories (6bits) */ +#define NV00E0_CTRL_RESERVED (0x00U) +#define NV00E0_CTRL_MEMORY_EXPORT (0x01U) + +/* + * NV00E0_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV00E0_CTRL_CMD_NULL (0xe00000U) /* finn: Evaluated from "(FINN_NV_MEMORY_EXPORT_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV00E0_CTRL_CMD_EXPORT_MEM + * + * Attaches memory handles to the export object. + * + * index [IN] + * Index into the export object at which to start attaching the provided + * memory handles. + * + * hParent [IN] + * Parent of memory handles to be attached (client or device or subdevice) + * If device or subdevice is used as parent, the related GPU is ref-counted + * by populating devDescriptor on behalf of the caller. + * + * handles [IN] + * Memory handles to be attached. + * + * numHandles [IN] + * Number of memory handles to be attached. + * + * devDescriptor [OPAQUE] + * devDescriptor is a file descriptor for unix RM clients, but a void + * pointer for windows RM clients. It is transparent to RM clients i.e. RM's + * user-mode shim populates this field on behalf of clients. + * + * Notes: + * - Imported fabric memory handles not supported. + * - No MIG support. + * - If 'numHandles' and 'index' overlap with a prior call, the newer call's + * RM handles will overwrite the attached handles from the previous call. + * This overlapping behavior can also be used to detach a handle by setting + * the appropriate object in 'handles' to 0. + */ +#define NV00E0_CTRL_CMD_EXPORT_MEM (0xe00101) /* finn: Evaluated from "(FINN_NV_MEMORY_EXPORT_INTERFACE_ID << 8) | NV00E0_CTRL_EXPORT_MEM_PARAMS_MESSAGE_ID" */ + +#define NV00E0_MAX_EXPORT_HANDLES 256 + +#define NV00E0_CTRL_EXPORT_MEM_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV00E0_CTRL_EXPORT_MEM_PARAMS { + NvU16 index; + NvHandle hParent; + NvHandle handles[NV00E0_MAX_EXPORT_HANDLES]; + NvU16 numHandles; + NV_DECLARE_ALIGNED(NvU64 devDescriptor, 8); +} NV00E0_CTRL_EXPORT_MEM_PARAMS; + +/* + * NV00E0_CTRL_CMD_IMPORT_MEM + * + * Imports attached objects into the caller's RM client. + * + * index [IN] + * Index into the export object from which start importing. + * + * numHandles [IN] + * Number of memory handles to be imported. + * + * handles [IN] + * Handles to be used for importing. + * + * memInfos [OUT] + * Information of the imported objects + */ +#define NV00E0_CTRL_CMD_IMPORT_MEM (0xe00102) /* finn: Evaluated from "(FINN_NV_MEMORY_EXPORT_INTERFACE_ID << 8) | NV00E0_CTRL_IMPORT_MEM_PARAMS_MESSAGE_ID" */ + +#define NV00E0_MAX_IMPORT_HANDLES 128 + +#define NV00E0_ADDR_SPACE_TYPE_SYSMEM 0x1 +#define NV00E0_ADDR_SPACE_TYPE_VIDMEM 0x2 +#define NV00E0_ADDR_SPACE_TYPE_FABRIC 0x3 +#define NV00E0_ADDR_SPACE_TYPE_FABRIC_MC 0x4 + +typedef struct NV_IMPORT_MEM_INFO { + NvHandle hParent; + NvU8 addrSpace; +} NV_IMPORT_MEM_INFO; + +#define NV00E0_CTRL_IMPORT_MEM_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV00E0_CTRL_IMPORT_MEM_PARAMS { + NvU16 index; + NvU16 numHandles; + NvHandle handles[NV00E0_MAX_IMPORT_HANDLES]; + NV_IMPORT_MEM_INFO memInfos[NV00E0_MAX_IMPORT_HANDLES]; +} NV00E0_CTRL_IMPORT_MEM_PARAMS; + +/* +* NV00E0_CTRL_CMD_GET_INFO +* +* Returns object information +* +* info [OUT] +* Same as NV00E0_ALLOCATION_PARAMETERS, see cl00e0.h for details. +*/ +#define NV00E0_CTRL_CMD_GET_INFO (0xe00103) /* finn: Evaluated from "(FINN_NV_MEMORY_EXPORT_INTERFACE_ID << 8) | NV00E0_CTRL_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV00E0_CTRL_GET_INFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV00E0_CTRL_GET_INFO_PARAMS { + NV00E0_ALLOCATION_PARAMETERS info; +} NV00E0_CTRL_GET_INFO_PARAMS; + +/* _ctrl00e0_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl00f1.h b/userspace/sdks/nv570/inc/ctrl/ctrl00f1.h new file mode 100644 index 0000000..06019a4 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl00f1.h @@ -0,0 +1,245 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl00f1.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "class/cl00e0.h" + +/* + * NV00F1_CTRL_CMD_GET_FABRIC_EVENTS + * + * Queries the fabric object for events. + * + * eventArray [OUT] + * An array of import lifetime events. + * + * numEvents [OUT] + * The number of valid events in eventArray. + * + * bMoreEvents [OUT] + * Whether there are any remaining events to be queried. + * + * Possible status values returned are: + * NV_ERR_NOT_SUPPORTED + * NV_OK + */ +#define NV00F1_CTRL_CMD_GET_FABRIC_EVENTS (0xf10001U) /* finn: Evaluated from "(FINN_IMEX_SESSION_INTERFACE_ID << 8) | NV00F1_CTRL_GET_FABRIC_EVENTS_PARAMS_MESSAGE_ID" */ + +/* Event types */ +#define NV00F1_CTRL_FABRIC_EVENT_TYPE_MEM_IMPORT 0U +#define NV00F1_CTRL_FABRIC_EVENT_TYPE_MEM_UNIMPORT 1U +#define NV00F1_CTRL_FABRIC_EVENT_TYPE_REMOTE_GPU_ATTACH 2U +#define NV00F1_CTRL_FABRIC_EVENT_TYPE_CLIQUE_ID_CHANGE 3U + +/* + * id + * Import ID. An import request can be uniquely identified using, + * . + * + * index + * Index of the export object to which the memory object is attached. + * + * exportNodeId + * ID of the exporter node where memory will be imported. + * + * exportUuid + * Universally unique identifier of the export object. This is extracted + * from a fabric packet. + * + + */ +typedef struct NV00F1_CTRL_FABRIC_MEM_IMPORT_EVENT_DATA { + NV_DECLARE_ALIGNED(NvU64 id, 8); + NvU16 index; + NvU16 exportNodeId; + NvU8 exportUuid[NV_MEM_EXPORT_UUID_LEN]; +} NV00F1_CTRL_FABRIC_MEM_IMPORT_EVENT_DATA; + +/* + * importEventId + * ID of the corresponding import event. + * + * exportNodeId + * ID of the exporter node where memory will be unimported. + */ +typedef struct NV00F1_CTRL_FABRIC_MEM_UNIMPORT_EVENT_DATA { + NV_DECLARE_ALIGNED(NvU64 importEventId, 8); + NvU16 exportNodeId; +} NV00F1_CTRL_FABRIC_MEM_UNIMPORT_EVENT_DATA; + +/* + * gpuFabricProbeHandle + * Fabric probe handle of the remote GPU + * + * key + * Key is used by the GFM in the MCFLA team response as an ID to allow the + * RM to correlate it with the MCFLA team request. + * + * bwModeEpoch + * Currently active bwModeEpoch of the remote GPU being attached. + * + * pageSize + * Client selected page size of the remote GPU being attached. + * + * cliqueId + * Clique ID of the remote GPU being attached. + * + * index + * Index of the export object to which the memory object is attached. + * + * exportNodeId + * ID of the exporter node where memory will be imported. + * + * bwMode + * Currently active bwMode of the remote GPU being attached + * + * exportUuid + * Universally unique identifier of the export object. This is extracted + * from a fabric packet. + */ +typedef struct NV00F1_CTRL_ATTACH_REMOTE_GPU_EVENT_DATA { + NV_DECLARE_ALIGNED(NvU64 gpuFabricProbeHandle, 8); + NV_DECLARE_ALIGNED(NvU64 key, 8); + NV_DECLARE_ALIGNED(NvU64 bwModeEpoch, 8); + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); + NvU32 cliqueId; + NvU16 index; + NvU16 exportNodeId; + NvU16 bwMode; + NvU8 exportUuid[NV_MEM_EXPORT_UUID_LEN]; +} NV00F1_CTRL_ATTACH_REMOTE_GPU_EVENT_DATA; + +/* + * gpuId + * GPU ID of the GPU whose cliqueID has changed. + * + * cliqueId + * Clique ID of the GPU. + */ +typedef struct NV00F1_CTRL_CLIQUE_ID_CHANGE_GPU_EVENT_DATA { + NvU32 gpuId; + NvU32 cliqueId; +} NV00F1_CTRL_CLIQUE_ID_CHANGE_GPU_EVENT_DATA; + +/* + * type + * Event type, one of NV00F1_CTRL_FABRIC_EVENT_TYPE_*. + * + * id + * A monotonically increasing event ID. + * + * imexChannel + * imex channel subscribed by the caller. + * + * data + * Event data + */ +typedef struct NV00F1_CTRL_FABRIC_EVENT { + NvU8 type; + NV_DECLARE_ALIGNED(NvU64 id, 8); + NvU32 imexChannel; + + union { + NV_DECLARE_ALIGNED(NV00F1_CTRL_FABRIC_MEM_IMPORT_EVENT_DATA import, 8); + NV_DECLARE_ALIGNED(NV00F1_CTRL_FABRIC_MEM_UNIMPORT_EVENT_DATA unimport, 8); + NV_DECLARE_ALIGNED(NV00F1_CTRL_ATTACH_REMOTE_GPU_EVENT_DATA attach, 8); + NV00F1_CTRL_CLIQUE_ID_CHANGE_GPU_EVENT_DATA cliqueIdChange; + } data; +} NV00F1_CTRL_FABRIC_EVENT; + +#define NV00F1_CTRL_GET_FABRIC_EVENTS_ARRAY_SIZE 128U + +#define NV00F1_CTRL_GET_FABRIC_EVENTS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV00F1_CTRL_GET_FABRIC_EVENTS_PARAMS { + NV_DECLARE_ALIGNED(NV00F1_CTRL_FABRIC_EVENT eventArray[NV00F1_CTRL_GET_FABRIC_EVENTS_ARRAY_SIZE], 8); + NvU32 numEvents; + NvBool bMoreEvents; +} NV00F1_CTRL_GET_FABRIC_EVENTS_PARAMS; + +/* + * NV00F1_CTRL_CMD_FINISH_MEM_UNIMPORT + * + * Notifies the unimport sequence is finished. + * + * tokenArray [IN] + * An array of tokens that finished the unimport sequence. + * + * numTokens [IN] + * The number of valid tokens in the tokenArray. + * + * Possible status values returned are: + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + * NV_OK + */ +#define NV00F1_CTRL_CMD_FINISH_MEM_UNIMPORT (0xf10002U) /* finn: Evaluated from "(FINN_IMEX_SESSION_INTERFACE_ID << 8) | NV00F1_CTRL_FINISH_MEM_UNIMPORT_PARAMS_MESSAGE_ID" */ + +/* + * unimportEventId + * ID of the unimport event. + */ +typedef struct NV00F1_CTRL_FABRIC_UNIMPORT_TOKEN { + NV_DECLARE_ALIGNED(NvU64 unimportEventId, 8); +} NV00F1_CTRL_FABRIC_UNIMPORT_TOKEN; + +#define NV00F1_CTRL_FINISH_MEM_UNIMPORT_ARRAY_SIZE 256U + +#define NV00F1_CTRL_FINISH_MEM_UNIMPORT_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV00F1_CTRL_FINISH_MEM_UNIMPORT_PARAMS { + NV_DECLARE_ALIGNED(NV00F1_CTRL_FABRIC_UNIMPORT_TOKEN tokenArray[NV00F1_CTRL_FINISH_MEM_UNIMPORT_ARRAY_SIZE], 8); + NvU32 numTokens; +} NV00F1_CTRL_FINISH_MEM_UNIMPORT_PARAMS; + +/* + * NV00F1_CTRL_CMD_DISABLE_IMPORTERS + * + * Disables clients which imported memory from the given nodeId. Channel + * recovery (disablement) sequence is also invoked to halt fabric traffic + * from these clients. + * + * nodeId [IN] + * An array of tokens that finished the unimport sequence. + * + * Possible status values returned are: + * NV_ERR_NOT_SUPPORTED + * NV_OK + */ +#define NV00F1_CTRL_CMD_DISABLE_IMPORTERS (0xf10003U) /* finn: Evaluated from "(FINN_IMEX_SESSION_INTERFACE_ID << 8) | NV00F1_CTRL_DISABLE_IMPORTERS_PARAMS_MESSAGE_ID" */ + +#define NV00F1_CTRL_DISABLE_IMPORTERS_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV00F1_CTRL_DISABLE_IMPORTERS_PARAMS { + NvU16 nodeId; +} NV00F1_CTRL_DISABLE_IMPORTERS_PARAMS; + +/* _ctrl00f1.h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl00f8.h b/userspace/sdks/nv570/inc/ctrl/ctrl00f8.h new file mode 100644 index 0000000..36f80ab --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl00f8.h @@ -0,0 +1,331 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl00f8.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "ctrl90f1.h" +#include "mmu_fmt_types.h" + +#define NV00F8_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x00f8, NV00F8_CTRL_##cat, idx) + +/* NV00F8 command categories (6bits) */ +#define NV00F8_CTRL_RESERVED (0x00U) +#define NV00F8_CTRL_FABRIC (0x01U) + +/* + * NV00F8_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV00F8_CTRL_CMD_NULL (0xf80000U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV00F8_CTRL_CMD_GET_INFO + * + * Queries memory allocation attributes. + * + * size [OUT] + * Size of the allocation. + * + * pageSize [OUT] + * Page size of the allocation. + * + * allocFlags [OUT] + * Flags passed during the allocation. + * + * physAttrs [OUT] + * Physical attributes associated with memory allocation. + * For flexible mappings, it is not possible to retrieve this information, + * behavior is undefined (returns all zeros). + */ +#define NV00F8_CTRL_CMD_GET_INFO (0xf80101U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_GET_INFO_PARAMS_MESSAGE_ID" */ + +/* + * addressSpace + * Same as NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE. + * + * compressionCoverage + * Same as NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE. + */ +typedef struct NV_PHYSICAL_MEMORY_ATTRS { + NvU32 addressSpace; + NvU32 compressionCoverage; +} NV_PHYSICAL_MEMORY_ATTRS; + +#define NV00F8_CTRL_GET_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV00F8_CTRL_GET_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 size, 8); + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); + NvU32 allocFlags; + NV_PHYSICAL_MEMORY_ATTRS physAttrs; +} NV00F8_CTRL_GET_INFO_PARAMS; + +/* + * NV00F8_CTRL_CMD_DESCRIBE + * + * Queries the physical attributes of the fabric memory allocation. + * + * offset [IN] + * Offset into memory allocation to query physical addresses for. + * + * totalPfns [OUT] + * Number of PFNs in memory allocation. + * + * pfnArray [OUT] + * Array of PFNs in memory allocation (2MB page size shifted). + * + * numPfns [OUT] + * Number of valid entries in pfnArray. + * + * attrs [OUT] + * Attributes associated with memory allocation. + * + * physAttrs [OUT] + * Physical attributes associated with memory allocation. + * For flexible mappings, it is not possible to retrieve this information, + * behavior is undefined (returns all zeros). + * + * memFlags [OUT] + * Flags associated with memory allocation. + * + * Note: This control call is only available for privileged clients. + */ + +#define NV00F8_CTRL_CMD_DESCRIBE (0xf80102) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_DESCRIBE_PARAMS_MESSAGE_ID" */ + +#define NV00F8_CTRL_DESCRIBE_PFN_ARRAY_SIZE 512 + +/* + * kind + * Kind of memory allocation. + * + * pageSize + * Page size of memory allocation. + * + * size + * Size of memory allocation + * + * cliqueId + * Clique ID of the owner GPU + * + * bwModeEpoch + * Currently active bwModeEpoch of of the owner GPU + * + * bwMode + * Currently active bwMode of the owner GPU + */ +typedef struct NV_FABRIC_MEMORY_ATTRS { + NvU32 kind; + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 cliqueId; + NV_DECLARE_ALIGNED(NvU64 bwModeEpoch, 8); + NvU16 bwMode; +} NV_FABRIC_MEMORY_ATTRS; + +#define NV00F8_CTRL_DESCRIBE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV00F8_CTRL_DESCRIBE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 totalPfns, 8); + NvU32 pfnArray[NV00F8_CTRL_DESCRIBE_PFN_ARRAY_SIZE]; + NvU32 numPfns; + NV_DECLARE_ALIGNED(NV_FABRIC_MEMORY_ATTRS attrs, 8); + NV_PHYSICAL_MEMORY_ATTRS physAttrs; + NvU32 memFlags; +} NV00F8_CTRL_DESCRIBE_PARAMS; + +/* + * hMemory + * Physical memory handle to be attached. + * + * offset + * Offset into the fabric object. + * Must be physical memory pagesize aligned (at least). + * + * mapOffSet + * Offset into the physical memory descriptor. + * Must be physical memory pagesize aligned. + * + * mapLength + * Length of physical memory handle to be mapped. + * Must be physical memory pagesize aligned and less than or equal to + * fabric alloc size. + */ +typedef struct NV00F8_CTRL_ATTACH_MEM_INFO { + NvHandle hMemory; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 mapOffset, 8); + NV_DECLARE_ALIGNED(NvU64 mapLength, 8); +} NV00F8_CTRL_ATTACH_MEM_INFO; + +/* + * NV00F8_CTRL_CMD_ATTACH_MEM + * + * Attaches physical memory info to the fabric object. + * + * memInfos [IN] + * Memory infos to be attached. + * + * numMemInfos [IN] + * Number of memory infos to be attached. + * + * flags [IN] + * For future use only. Must be zero for now. + * + * numAttached [OUT] + * Successful attach count (returns a valid value on error too) + * + * Restrictions: + * a. Physical memory with 2MB pagesize is allowed + * b. vidmem and sysmem with fixed node ID can be attached. + * sysmem with fixed node ID is supported only if EGM is enabled. + * c. Supported only for flexible fabric objects. + */ +#define NV00F8_CTRL_CMD_ATTACH_MEM (0xf80103) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_ATTACH_MEM_PARAMS_MESSAGE_ID" */ + +#define NV00F8_MAX_ATTACHABLE_MEM_INFOS 64 + +#define NV00F8_CTRL_ATTACH_MEM_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV00F8_CTRL_ATTACH_MEM_PARAMS { + NV_DECLARE_ALIGNED(NV00F8_CTRL_ATTACH_MEM_INFO memInfos[NV00F8_MAX_ATTACHABLE_MEM_INFOS], 8); + NvU16 numMemInfos; + NvU32 flags; + NvU16 numAttached; +} NV00F8_CTRL_ATTACH_MEM_PARAMS; + +/* + * NV00F8_CTRL_CMD_DETACH_MEM + * + * Detaches physical memory handle from the fabric object. + * + * offsets [IN] + * Offsets at which memory was attached. + * + * numOffsets [IN] + * Number of offsets to be detached. + * + * flags [IN] + * For future use only. Must be zero for now. + * + * numDetached [OUT] + * Successful detach count (returns a valid value on error too) + */ +#define NV00F8_CTRL_CMD_DETACH_MEM (0xf80104) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_DETACH_MEM_PARAMS_MESSAGE_ID" */ + +#define NV00F8_MAX_DETACHABLE_OFFSETS 64 + +#define NV00F8_CTRL_DETACH_MEM_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV00F8_CTRL_DETACH_MEM_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offsets[NV00F8_MAX_DETACHABLE_OFFSETS], 8); + NvU16 numOffsets; + NvU32 flags; + NvU16 numDetached; +} NV00F8_CTRL_DETACH_MEM_PARAMS; + +/* + * NV00F8_CTRL_CMD_GET_NUM_ATTACHED_MEM + * + * Returns number of attached physical memory info to the fabric object in + * a given offset range. + * + * offsetStart [IN] + * Offsets at which memory was attached. + * + * offsetEnd [IN] + * Offsets at which memory was attached. + * + * numMemInfos [OUT] + * Number of memory infos. + */ +#define NV00F8_CTRL_CMD_GET_NUM_ATTACHED_MEM (0xf80105) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS_MESSAGE_ID" */ + +#define NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offsetStart, 8); + NV_DECLARE_ALIGNED(NvU64 offsetEnd, 8); + NvU16 numMemInfos; +} NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS; + +/* + * NV00F8_CTRL_CMD_GET_PAGE_LEVEL_INFO + * + * Queries page table information for a specific memory fabric address. This + * call is only supported for Verif platforms. This will return the same info + * as NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS. + * + * offset [IN] + * Memory fabric Offset from the base address for which page table + * information is queried. This offset should be aligned to physical page + * size. + * + * numLevels [OUT] + * Number of levels populated. + * + * levels [OUT] + * Per-level information. + * + * pFmt + * Same as NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS. + * + * levelFmt + * Same as NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS. + * + * sublevelFmt + * Same as NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS. + * + * aperture + * Same as NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS. + * + * size + * Same as NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS. + */ +#define NV00F8_CTRL_CMD_GET_PAGE_LEVEL_INFO (0xf80107U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NvU32 numLevels; + NV_DECLARE_ALIGNED(NV_CTRL_VASPACE_PAGE_LEVEL levels[GMMU_FMT_MAX_LEVELS], 8); +} NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS; + +/* _ctrl00f8_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl00f9.h b/userspace/sdks/nv570/inc/ctrl/ctrl00f9.h new file mode 100644 index 0000000..a51caa5 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl00f9.h @@ -0,0 +1,87 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-22 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl00f9.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl00f8.h" + +#define NV00F9_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x00f9, NV00F9_CTRL_##cat, idx) + +/* NV00F9 command categories (6bits) */ +#define NV00F9_CTRL_RESERVED (0x00U) +#define NV00F9_CTRL_IMPORT (0x01U) + +/* + * NV00F9_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV00F9_CTRL_CMD_NULL (0xf90000U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_IMPORT_V2_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV00F9_CTRL_CMD_GET_INFO + * + * Queries memory allocation attributes. + * + * size [OUT] + * Size of the allocation. + * + * pageSize [OUT] + * Page size of the allocation + * + * memFlags [OUT] + * Flags associated with memory allocation. + * + * physAttrs [OUT] + * Physical attributes associated with memory allocation. + * For flexible mappings, it is not possible to retrieve this information, + * behavior is undefined (returns all zeros). + */ +#define NV00F9_CTRL_CMD_GET_INFO (0xf90101U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_IMPORT_V2_IMPORT_INTERFACE_ID << 8) | NV00F9_CTRL_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV00F9_CTRL_GET_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV00F9_CTRL_GET_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 size, 8); + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); + NvU32 memFlags; + NV_PHYSICAL_MEMORY_ATTRS physAttrs; +} NV00F9_CTRL_GET_INFO_PARAMS; + +/* _ctrl00f9_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl00fb.h b/userspace/sdks/nv570/inc/ctrl/ctrl00fb.h new file mode 100644 index 0000000..d995ffc --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl00fb.h @@ -0,0 +1,114 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-22 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl00fb.finn +// + +#include "nvtypes.h" +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl00f8.h" + +#define NV00FB_CTRL_CMD(cat, idx) \ + NVXXXX_CTRL_CMD(0x00fb, NV00FB_CTRL_##cat, idx) + +/* NV00FB command categories (6bits) */ +#define NV00FB_CTRL_RESERVED (0x00U) +#define NV00FB_CTRL_IMPORT_REF (0x01U) + +/* + * NV00FB_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV00FB_CTRL_CMD_NULL (0xfb0000U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_IMPORTED_REF_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV00FB_CTRL_CMD_VALIDATE + * + * Populate the imported memory, making it ready to map locally. + * + * attrs [IN] + * Attributes associated with memory allocation. + * + * physAttrs [IN] + * Physical attributes associated with memory allocation. + * For flexible mappings, it is not possible to retrieve this information, + * behavior is undefined (returns all zeros). + * + * offset [IN] + * Offset into memory allocation to query physical addresses for. + * + * totalPfns [IN] + * Number of PFNs in memory allocation. + * + * pfnArray [IN] + * Array of PFNs in memory allocation (2MB page size shifted). + * + * numPfns [IN] + * Number of valid entries in pfnArray. + * + * memFlags [IN] + * Flags associated with memory allocation. + * + * flags [IN] + * Flags to notify RM about errors during import. + * + * bDone [out] + * Whether the RM is expecting additional calls to _VALIDATE. + */ +#define NV00FB_CTRL_CMD_VALIDATE (0xfb0101U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_IMPORTED_REF_IMPORT_REF_INTERFACE_ID << 8) | NV00FB_CTRL_VALIDATE_PARAMS_MESSAGE_ID" */ + +#define NV00FB_CTRL_VALIDATE_PFN_ARRAY_SIZE 512U + +#define NV00FB_CTRL_FLAGS_NONE 0U +#define NV00FB_CTRL_FLAGS_IMPORT_FAILED 1U + +#define NV00FB_CTRL_VALIDATE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV00FB_CTRL_VALIDATE_PARAMS { + NV_DECLARE_ALIGNED(NV_FABRIC_MEMORY_ATTRS attrs, 8); + NV_PHYSICAL_MEMORY_ATTRS physAttrs; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 totalPfns, 8); + NvU32 pfnArray[NV00FB_CTRL_VALIDATE_PFN_ARRAY_SIZE]; + NvU32 numPfns; + NvU32 memFlags; + NvU32 flags; + NvBool bDone; +} NV00FB_CTRL_VALIDATE_PARAMS; + +/* _ctrl00fb_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl00fd.h b/userspace/sdks/nv570/inc/ctrl/ctrl00fd.h new file mode 100644 index 0000000..75985e7 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl00fd.h @@ -0,0 +1,280 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl00fd.finn +// + +#include "ctrl/ctrlxxxx.h" + +#define NV00FD_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x00fd, NV00FD_CTRL_##cat, idx) + +/* NV00FD command categories (6bits) */ +#define NV00FD_CTRL_RESERVED (0x00) +#define NV00FD_CTRL_MULTICAST_FABRIC (0x01) + +/* + * NV00FD_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV00FD_CTRL_CMD_NULL (0xfd0000) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV00FD_CTRL_CMD_GET_INFO + * + * Queries multicast memory fabric allocation attributes. + * + * alignment [OUT] + * Alignment for the allocation. + * + * allocSize [OUT] + * Size of the allocation. + * + * pageSize [OUT] + * Page size of the allocation. + * + * numMaxGpus [OUT] + * Maximum number of attachable GPUs + * + * numAttachedGpus [OUT] + * Number of GPUs currently attached + * + */ +#define NV00FD_CTRL_CMD_GET_INFO (0xfd0101) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV00FD_CTRL_GET_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV00FD_CTRL_GET_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 alignment, 8); + NV_DECLARE_ALIGNED(NvU64 allocSize, 8); + NvU32 pageSize; + NvU32 numMaxGpus; + NvU32 numAttachedGpus; +} NV00FD_CTRL_GET_INFO_PARAMS; + +/* + * NV00FD_CTRL_CMD_ATTACH_MEM + * + * Attaches the physical memory handle and in turn the memory + * owner of the physical memory to the Multicast FLA object. + * + * hSubdevice [IN] + * Subdevice handle of the owner GPU + * + * hMemory [IN] + * Physical memory handle to be attached. + * + * offset [IN] + * Offset into the MCFLA object. Must be at least physical pagesize aligned. + * + * mapOffSet [IN] + * Offset into the physical memory descriptor. + * Must be physical memory pagesize aligned. + * + * mapLength [IN] + * Length of physical memory handle to be mapped. + * Must be physical memory pagesize aligned and less than or equal to + * MCFLA alloc size + * + * flags [IN] + * For future use only. Must be zero for now. + * + * subPageOffset [IN] + * For future use only. Must be zero for now. + */ + +/* + * subPageOffset + * Offset within the physical memory pagesize. + * Pre-GR100 must be zero. + * GR100+ must be 256B aligned and any mapping using a non-zero + * value cannot extend into the last 2MB of the FLA allocation. + */ + + + +/* + * Restrictions: + * a. Memory belonging to only NVSwitch P2P supported GPUs + * which can do multicast can be attached + * b. Physical memory with 2MB or 512MB pagesize is allowed + * c. Both vidmem and sysmem (EGM) physical memory handles are supported + */ +#define NV00FD_CTRL_CMD_ATTACH_MEM (0xfd0102) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_ATTACH_MEM_PARAMS_MESSAGE_ID" */ + +#define NV00FD_CTRL_ATTACH_MEM_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV00FD_CTRL_ATTACH_MEM_PARAMS { + NvHandle hSubdevice; + NvHandle hMemory; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 mapOffset, 8); + NV_DECLARE_ALIGNED(NvU64 mapLength, 8); + NvU32 flags; + NvU32 subPageOffset; +} NV00FD_CTRL_ATTACH_MEM_PARAMS; + +/* + * NV00FD_CTRL_CMD_REGISTER_EVENT + * + * Allows clients to optionally register for events after the Multicast + * FLA object is duped under another client. + * + * pOsEvent [IN] + * OS event handle created with NvRmAllocOsEvent(). + * + */ +#define NV00FD_CTRL_CMD_REGISTER_EVENT (0xfd0103) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_REGISTER_EVENT_PARAMS_MESSAGE_ID" */ + +#define NV00FD_CTRL_REGISTER_EVENT_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV00FD_CTRL_REGISTER_EVENT_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pOsEvent, 8); +} NV00FD_CTRL_REGISTER_EVENT_PARAMS; + +/* + * NV00FD_CTRL_CMD_ATTACH_GPU + * + * Attaches GPU to the Multicast FLA object. This step must be done before + * attaching memory to the Multicast FLA object. + * + * hSubdevice [IN] + * Subdevice handle of the owner GPU + * + * flags [IN] + * For future use only. Must be zero for now. + * + * devDescriptor [IN] + * devDescriptor is a file descriptor for unix RM clients, but a void + * pointer for windows RM clients. It is transparent to RM clients i.e. RM's + * user-mode shim populates this field on behalf of clients. + */ +#define NV00FD_CTRL_CMD_ATTACH_GPU (0xfd0104) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_ATTACH_GPU_PARAMS_MESSAGE_ID" */ + +#define NV00FD_CTRL_ATTACH_GPU_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV00FD_CTRL_ATTACH_GPU_PARAMS { + NvHandle hSubdevice; + NvU32 flags; + NV_DECLARE_ALIGNED(NvU64 devDescriptor, 8); +} NV00FD_CTRL_ATTACH_GPU_PARAMS; + +/* + * NV00FD_CTRL_CMD_DETACH_MEM + * + * Detaches the physical memory handle for a given GPU. + * + * hSubdevice [IN] + * Subdevice handle of the GPU for which memory to be detached. + * + * offset [IN] + * Offset into the MCFLA object at which memory to be detached. Same as + * NV00FD_CTRL_CMD_ATTACH_MEM. + * + * flags [IN] + * For future use only. Must be zero for now. + */ +#define NV00FD_CTRL_CMD_DETACH_MEM (0xfd0105) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_DETACH_MEM_PARAMS_MESSAGE_ID" */ + +#define NV00FD_CTRL_DETACH_MEM_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV00FD_CTRL_DETACH_MEM_PARAMS { + NvHandle hSubdevice; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NvU32 flags; +} NV00FD_CTRL_DETACH_MEM_PARAMS; + +/* + * NV00FD_CTRL_CMD_ATTACH_REMOTE_GPU + * + * Attaches a remote GPU to the Multicast FLA object. This control call is + * restricted to the privileged clients like IMEX daemon. + * + * gpuFabricProbeHandle [IN] + * Fabric probe handle of the remote GPU + * + * key [IN] + * Key is used by the GFM in the MCFLA team response as an ID to allow the + * RM to correlate it with the MCFLA team request. + * + * bwModeEpoch [IN] + * Currently active bwModeEpoch of the remote GPU being attached. + * + * pageSize [IN] + * The page size requested by the remote client. Must match prime configuration. + * + * cliqueId [IN] + * Clique ID of the remote GPU being attached. + * + * nodeId [IN] + * nodeID from which the remote GPU is being attached. + * + * bwMode [IN] + * Currently active bwMode of the remote GPU being attached. + */ +#define NV00FD_CTRL_CMD_ATTACH_REMOTE_GPU (0xfd0106) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_ATTACH_REMOTE_GPU_PARAMS_MESSAGE_ID" */ + +#define NV00FD_CTRL_ATTACH_REMOTE_GPU_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV00FD_CTRL_ATTACH_REMOTE_GPU_PARAMS { + NV_DECLARE_ALIGNED(NvU64 gpuFabricProbeHandle, 8); + NV_DECLARE_ALIGNED(NvU64 key, 8); + NV_DECLARE_ALIGNED(NvU64 bwModeEpoch, 8); + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); + NvU32 cliqueId; + NvU16 nodeId; + NvU16 bwMode; +} NV00FD_CTRL_ATTACH_REMOTE_GPU_PARAMS; + +/* + * NV00FD_CTRL_CMD_SET_FAILURE + * + * Marks the MCLFA object allocation with a failure. This control call is + * restricted to the privileged client like IMEX daemon. + * + * status [IN] + * Failure status, shouldn't be NV_OK. + */ +#define NV00FD_CTRL_CMD_SET_FAILURE (0xfd0107) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_SET_FAILURE_PARAMS_MESSAGE_ID" */ + +#define NV00FD_CTRL_SET_FAILURE_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV00FD_CTRL_SET_FAILURE_PARAMS { + NV_STATUS status; +} NV00FD_CTRL_SET_FAILURE_PARAMS; + + + +/* _ctrl00fd_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl00fe.h b/userspace/sdks/nv570/inc/ctrl/ctrl00fe.h new file mode 100644 index 0000000..a5cf2b6 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl00fe.h @@ -0,0 +1,107 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl00fe.finn +// + +typedef enum NV00FE_CTRL_OPERATION_TYPE { + NV00FE_CTRL_OPERATION_TYPE_NOP = 0, // operation is ignored, used internally + NV00FE_CTRL_OPERATION_TYPE_MAP = 1, + NV00FE_CTRL_OPERATION_TYPE_UNMAP = 2, + NV00FE_CTRL_OPERATION_TYPE_SEMAPHORE_WAIT = 3, + NV00FE_CTRL_OPERATION_TYPE_SEMAPHORE_SIGNAL = 4, +} NV00FE_CTRL_OPERATION_TYPE; + +typedef struct NV00FE_CTRL_OPERATION_MAP { + NvHandle hVirtualMemory; + NV_DECLARE_ALIGNED(NvU64 virtualOffset, 8); + NvHandle hPhysicalMemory; + NV_DECLARE_ALIGNED(NvU64 physicalOffset, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 dmaFlags; // NVOS46_FLAGS + NvU32 kindOverride; +} NV00FE_CTRL_OPERATION_MAP; + +typedef struct NV00FE_CTRL_OPERATION_UNMAP { + NvHandle hVirtualMemory; + NV_DECLARE_ALIGNED(NvU64 virtualOffset, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 dmaFlags; // NVOS47_FLAGS +} NV00FE_CTRL_OPERATION_UNMAP; + +typedef struct NV00FE_CTRL_OPERATION_SEMAPHORE { + NvU32 index; + NV_DECLARE_ALIGNED(NvU64 value, 8); +} NV00FE_CTRL_OPERATION_SEMAPHORE; + +typedef struct NV00FE_CTRL_OPERATION { + NV00FE_CTRL_OPERATION_TYPE type; + + union { + NV_DECLARE_ALIGNED(NV00FE_CTRL_OPERATION_MAP map, 8); + NV_DECLARE_ALIGNED(NV00FE_CTRL_OPERATION_UNMAP unmap, 8); + NV_DECLARE_ALIGNED(NV00FE_CTRL_OPERATION_SEMAPHORE semaphore, 8); + } data; +} NV00FE_CTRL_OPERATION; + +/* + * NV00FE_CTRL_CMD_SUBMIT_OPERATIONS + * + * Execute a list of mapping/semaphore operations + * Page size is determined by the virtual allocation + * Offsets/sizes must respect the page size + * + */ +#define NV00FE_CTRL_CMD_SUBMIT_OPERATIONS (0xfe0101U) /* finn: Evaluated from "(FINN_NV_MEMORY_MAPPER_INTERFACE_ID << 8) | NV00FE_CTRL_SUBMIT_OPERATIONS_PARAMS_MESSAGE_ID" */ + +#define NV00FE_MAX_OPERATIONS_COUNT (0x00001000U) + +#define NV00FE_CTRL_SUBMIT_OPERATIONS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV00FE_CTRL_SUBMIT_OPERATIONS_PARAMS { + NvU32 operationsCount; + NV_DECLARE_ALIGNED(NV00FE_CTRL_OPERATION pOperations[NV00FE_MAX_OPERATIONS_COUNT], 8); + NvU32 operationsProcessedCount; +} NV00FE_CTRL_SUBMIT_OPERATIONS_PARAMS; + +/* + * NV00FE_CTRL_CMD_RESIZE_QUEUE + * + * Resize the MemoryMapper command queue + * All pending commands remain in queue + * + */ +#define NV00FE_CTRL_CMD_RESIZE_QUEUE (0xfe0102U) /* finn: Evaluated from "(FINN_NV_MEMORY_MAPPER_INTERFACE_ID << 8) | NV00FE_CTRL_RESIZE_QUEUE_PARAMS_MESSAGE_ID" */ + +#define NV00FE_CTRL_RESIZE_QUEUE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV00FE_CTRL_RESIZE_QUEUE_PARAMS { + NvU32 maxQueueSize; +} NV00FE_CTRL_RESIZE_QUEUE_PARAMS; + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl0100.h b/userspace/sdks/nv570/inc/ctrl/ctrl0100.h new file mode 100644 index 0000000..35c42ac --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl0100.h @@ -0,0 +1,263 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0100.finn +// + +#include "ctrl/ctrlxxxx.h" + +#define NV0100_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0100, NV0100_CTRL_##cat, idx) + +/* Client command categories (6bits) */ +#define NV0100_CTRL_RESERVED (0x00U) +#define NV0100_CTRL_LOCK_STRESS (0x01U) + +/* + * NV0100_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0100_CTRL_CMD_NULL (0x1000000U) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV0100_CTRL_CMD_RESET_LOCK_STRESS_STATE + * + * This command resets RM's lock stress counters to 0, allowing for a new lock stress + * run to start. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0100_CTRL_CMD_RESET_LOCK_STRESS_STATE (0x1000101U) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID << 8) | 0x1" */ + +/* + * Bit fields to indicate to the caller whether an action was performed on a counter + * Setting any of these fields to 1 means to increment/decrement the respective counter. + * Setting any of these fields to 0 means to ignore the respective counter. + */ +#define NV0100_CTRL_GLOBAL_RMAPI_LOCK_STRESS_COUNTER_ACTION 0:0 +#define NV0100_CTRL_GPU_LOCK_STRESS_COUNTER_ACTION 1:1 +#define NV0100_CTRL_CLIENT_LOCK_STRESS_COUNTER_ACTION 2:2 +#define NV0100_CTRL_INTERNAL_CLIENT_LOCK_STRESS_COUNTER_ACTION 3:3 +#define NV0100_CTRL_ALL_LOCK_STRESS_COUNTER_ACTION 3:0 + +/* + * Bit fields to indicate to the caller what type of action was performed on a counter + * Setting any of these fields to 1 means to increment the respective counter. + * Setting any of these fields to 0 means to decrement the respective counter. + */ +#define NV0100_CTRL_GLOBAL_RMAPI_LOCK_STRESS_COUNTER_INCREMENT 4:4 +#define NV0100_CTRL_GPU_LOCK_STRESS_COUNTER_INCREMENT 5:5 +#define NV0100_CTRL_CLIENT_LOCK_STRESS_COUNTER_INCREMENT 6:6 +#define NV0100_CTRL_INTERNAL_CLIENT_LOCK_STRESS_COUNTER_INCREMENT 7:7 +#define NV0100_CTRL_ALL_LOCK_STRESS_COUNTER_INCREMENT 7:4 + +typedef struct NV0100_CTRL_LOCK_STRESS_OUTPUT { + NvU8 action; +} NV0100_CTRL_LOCK_STRESS_OUTPUT; + +/* + * NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_ALL_RM_LOCKS + * + * This command does a random increment/decrement on global counters in RM and reports + * the operation performed back to the caller. This is done with all RM locks held. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_ALL_RM_LOCKS (0x1000102U) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID << 8) | NV0100_CTRL_PERFORM_LOCK_STRESS_ALL_RM_LOCKS_PARAMS_MESSAGE_ID" */ + +#define NV0100_CTRL_PERFORM_LOCK_STRESS_ALL_RM_LOCKS_PARAMS_MESSAGE_ID (0x2U) + +typedef NV0100_CTRL_LOCK_STRESS_OUTPUT NV0100_CTRL_PERFORM_LOCK_STRESS_ALL_RM_LOCKS_PARAMS; + +/* + * NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_NO_GPUS_LOCK + * + * This command does a random increment/decrement on global counters in RM and reports + * the operation performed back to the caller. This is done with all RM locks held except + * for the GPU locks. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_NO_GPUS_LOCK (0x1000103U) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID << 8) | NV0100_CTRL_PERFORM_LOCK_STRESS_NO_GPUS_LOCK_PARAMS_MESSAGE_ID" */ + +#define NV0100_CTRL_PERFORM_LOCK_STRESS_NO_GPUS_LOCK_PARAMS_MESSAGE_ID (0x3U) + +typedef NV0100_CTRL_LOCK_STRESS_OUTPUT NV0100_CTRL_PERFORM_LOCK_STRESS_NO_GPUS_LOCK_PARAMS; + +/* + * NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_API_LOCK_READ_MODE + * + * This command does a random increment/decrement on global counters in RM and reports + * the operation performed back to the caller. This is done with the API lock held in + * read mode and GPU locks held. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_API_LOCK_READ_MODE (0x1000104U) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID << 8) | NV0100_CTRL_PERFORM_LOCK_STRESS_API_LOCK_READ_MODE_PARAMS_MESSAGE_ID" */ + +#define NV0100_CTRL_PERFORM_LOCK_STRESS_API_LOCK_READ_MODE_PARAMS_MESSAGE_ID (0x4U) + +typedef NV0100_CTRL_LOCK_STRESS_OUTPUT NV0100_CTRL_PERFORM_LOCK_STRESS_API_LOCK_READ_MODE_PARAMS; + +/* + * NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_NO_GPUS_LOCK_API_LOCK_READ_MODE + * + * This command does a random increment/decrement on global counters in RM and reports + * the operation performed back to the caller. This is done with the API lock held in + * read mode. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_NO_GPUS_LOCK_API_LOCK_READ_MODE (0x1000105U) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID << 8) | NV0100_CTRL_PERFORM_LOCK_STRESS_NO_GPUS_LOCK_API_LOCK_READ_MODE_PARAMS_MESSAGE_ID" */ + +#define NV0100_CTRL_PERFORM_LOCK_STRESS_NO_GPUS_LOCK_API_LOCK_READ_MODE_PARAMS_MESSAGE_ID (0x5U) + +typedef NV0100_CTRL_LOCK_STRESS_OUTPUT NV0100_CTRL_PERFORM_LOCK_STRESS_NO_GPUS_LOCK_API_LOCK_READ_MODE_PARAMS; + +/* + * NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_INTERNAL_ALL_RM_LOCKS + * + * This command does a random increment/decrement on global counters in RM and reports + * the operation performed back to the caller. This is done with all RM locks held in the + * internal RM API path. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_INTERNAL_ALL_RM_LOCKS (0x1000106U) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID << 8) | NV0100_CTRL_PERFORM_LOCK_STRESS_INTERNAL_ALL_RM_LOCKS_PARAMS_MESSAGE_ID" */ + +#define NV0100_CTRL_PERFORM_LOCK_STRESS_INTERNAL_ALL_RM_LOCKS_PARAMS_MESSAGE_ID (0x6U) + +typedef NV0100_CTRL_LOCK_STRESS_OUTPUT NV0100_CTRL_PERFORM_LOCK_STRESS_INTERNAL_ALL_RM_LOCKS_PARAMS; + +/* + * NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_INTERNAL_NO_GPUS_LOCK + * + * This command does a random increment/decrement on global counters in RM and reports + * the operation performed back to the caller. This is done with all RM locks held except + * for the GPU locks in the internal RM API path. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_INTERNAL_NO_GPUS_LOCK (0x1000107U) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID << 8) | NV0100_CTRL_PERFORM_LOCK_STRESS_INTERNAL_NO_GPUS_LOCK_PARAMS_MESSAGE_ID" */ + +#define NV0100_CTRL_PERFORM_LOCK_STRESS_INTERNAL_NO_GPUS_LOCK_PARAMS_MESSAGE_ID (0x7U) + +typedef NV0100_CTRL_LOCK_STRESS_OUTPUT NV0100_CTRL_PERFORM_LOCK_STRESS_INTERNAL_NO_GPUS_LOCK_PARAMS; + +/* + * NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_INTERNAL_API_LOCK_READ_MODE + * + * This command does a random increment/decrement on global counters in RM and reports + * the operation performed back to the caller. This is done with the API lock taken in + * read mode and GPU locks held in the internal RM API path. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_INTERNAL_API_LOCK_READ_MODE (0x1000108U) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID << 8) | NV0100_CTRL_PERFORM_LOCK_STRESS_INTERNAL_API_LOCK_READ_MODE_PARAMS_MESSAGE_ID" */ + +#define NV0100_CTRL_PERFORM_LOCK_STRESS_INTERNAL_API_LOCK_READ_MODE_PARAMS_MESSAGE_ID (0x8U) + +typedef NV0100_CTRL_LOCK_STRESS_OUTPUT NV0100_CTRL_PERFORM_LOCK_STRESS_INTERNAL_API_LOCK_READ_MODE_PARAMS; + +/* + * NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_INTERNAL_NO_GPUS_LOCK_API_LOCK_READ_MODE + * + * This command does a random increment/decrement on global counters in RM and reports + * the operation performed back to the caller. This is done with the API lock held in read + * mode in the internal RM API path. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_INTERNAL_NO_GPUS_LOCK_API_LOCK_READ_MODE (0x1000109U) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID << 8) | NV0100_CTRL_PERFORM_LOCK_STRESS_INTERNAL_NO_GPUS_LOCK_API_LOCK_READ_MODE_PARAMS_MESSAGE_ID" */ + +#define NV0100_CTRL_PERFORM_LOCK_STRESS_INTERNAL_NO_GPUS_LOCK_API_LOCK_READ_MODE_PARAMS_MESSAGE_ID (0x9U) + +typedef NV0100_CTRL_LOCK_STRESS_OUTPUT NV0100_CTRL_PERFORM_LOCK_STRESS_INTERNAL_NO_GPUS_LOCK_API_LOCK_READ_MODE_PARAMS; + +/* + * NV0100_CTRL_CMD_GET_LOCK_STRESS_COUNTERS + * + * This command gets the value of the global lock stress counters in RM at the end of + * the lock stress test. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0100_CTRL_CMD_GET_LOCK_STRESS_COUNTERS (0x100010aU) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID << 8) | NV0100_CTRL_GET_LOCK_STRESS_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV0100_CTRL_GET_LOCK_STRESS_COUNTERS_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV0100_CTRL_GET_LOCK_STRESS_COUNTERS_PARAMS { + NvS32 globalLockStressCounter; + NvS32 gpuLockStressCounter; + NvS32 clientLockStressCounter; + NvS32 internalClientLockStressCounter; +} NV0100_CTRL_GET_LOCK_STRESS_COUNTERS_PARAMS; + +/* + * NV0100_CTRL_CMD_RECURSIVE_GPU_LOCK_TEST* + * + * @brief Testing the recursive GPU lock acquisition + * + * bLeaf [IN] Indicate that this is a leaf node to check the held lock only, + * insted of running a full test. This parameter is used internally + * to test locking for recursive RMCTRLs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_TEST_ONLY_CODE_NOT_ENABLED + * NV_ERR_INVALID_LOCK_STATE + */ + +#define NV0100_CTRL_CMD_RECURSIVE_GPU_LOCK_TEST_PARAM_MESSAGE_ID (0xBU) + +typedef struct NV0100_CTRL_CMD_RECURSIVE_GPU_LOCK_TEST_PARAM { + NvBool bLeaf; +} NV0100_CTRL_CMD_RECURSIVE_GPU_LOCK_TEST_PARAM; + +#define NV0100_CTRL_CMD_RECURSIVE_GPU_LOCK_TEST_NO_LOCK (0x100010bU) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID << 8) | NV0100_CTRL_CMD_RECURSIVE_GPU_LOCK_TEST_PARAM_MESSAGE_ID" */ +#define NV0100_CTRL_CMD_RECURSIVE_GPU_LOCK_TEST_ALL_LOCK (0x100010cU) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID << 8) | (NV0100_CTRL_CMD_RECURSIVE_GPU_LOCK_TEST_PARAM_MESSAGE_ID + 1)" */ +#define NV0100_CTRL_CMD_RECURSIVE_GPU_LOCK_TEST_DEVICE_LOCK (0x100010dU) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID << 8) | (NV0100_CTRL_CMD_RECURSIVE_GPU_LOCK_TEST_PARAM_MESSAGE_ID + 2)" */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080.h new file mode 100644 index 0000000..91ab9a0 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080.h @@ -0,0 +1,91 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080.finn +// + + + + +#include "ctrl/ctrlxxxx.h" +#include "ctrl2080/ctrl2080gpu.h" +#include "ctrl2080/ctrl2080fuse.h" +#include "ctrl2080/ctrl2080event.h" +#include "ctrl2080/ctrl2080tmr.h" +#include "ctrl2080/ctrl2080bios.h" +#include "ctrl2080/ctrl2080mc.h" +#include "ctrl2080/ctrl2080fifo.h" +#include "ctrl2080/ctrl2080fb.h" + + + +#include "ctrl2080/ctrl2080spdm.h" +#include "ctrl2080/ctrl2080gr.h" +#include "ctrl2080/ctrl2080bus.h" +#include "ctrl2080/ctrl2080thermal.h" +#include "ctrl2080/ctrl2080fan.h" +#include "ctrl2080/ctrl2080i2c.h" +#include "ctrl2080/ctrl2080internal.h" +#include "ctrl2080/ctrl2080spi.h" +#include "ctrl2080/ctrl2080gpio.h" +#include "ctrl2080/ctrl2080clk.h" +#include "ctrl2080/ctrl2080perf.h" +#include "ctrl2080/ctrl2080perf_cf.h" + + +#include "ctrl2080/ctrl2080rc.h" +#include "ctrl2080/ctrl2080dma.h" +#include "ctrl2080/ctrl2080dmabuf.h" +#include "ctrl2080/ctrl2080nvd.h" +#include "ctrl2080/ctrl2080boardobj.h" +#include "ctrl2080/ctrl2080pmgr.h" +#include "ctrl2080/ctrl2080power.h" +#include "ctrl2080/ctrl2080lpwr.h" +#include "ctrl2080/ctrl2080acr.h" +#include "ctrl2080/ctrl2080ce.h" +#include "ctrl2080/ctrl2080nvlink.h" +#include "ctrl2080/ctrl2080flcn.h" +#include "ctrl2080/ctrl2080volt.h" +#include "ctrl2080/ctrl2080ecc.h" +#include "ctrl2080/ctrl2080cipher.h" +#include "ctrl2080/ctrl2080fla.h" +#include "ctrl2080/ctrl2080gsp.h" +#include "ctrl2080/ctrl2080pmu.h" + + +#include "ctrl2080/ctrl2080grmgr.h" + + +#include "ctrl2080/ctrl2080vgpumgrinternal.h" +#include "ctrl2080/ctrl2080hshub.h" +/* include appropriate os-specific command header */ + + +#include "ctrl2080/ctrl2080unix.h" +#include "ctrl2080/ctrl2080bif.h" + + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080acr.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080acr.h new file mode 100644 index 0000000..d67b0f2 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080acr.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080acr.finn +// + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080base.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080base.h new file mode 100644 index 0000000..be142a2 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080base.h @@ -0,0 +1,119 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080base.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV20_SUBDEVICE_XX control commands and parameters */ + +#define NV2080_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x2080, NV2080_CTRL_##cat, idx) + +/* Subdevice command categories (6bits) */ +#define NV2080_CTRL_RESERVED (0x00) +#define NV2080_CTRL_GPU (0x01) +#define NV2080_CTRL_GPU_LEGACY_NON_PRIVILEGED (0x81) /* finn: Evaluated from "(NV2080_CTRL_GPU | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_FUSE (0x02) +#define NV2080_CTRL_FUSE_LEGACY_NON_PRIVILEGED (0x82) /* finn: Evaluated from "(NV2080_CTRL_FUSE | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_EVENT (0x03) +#define NV2080_CTRL_TIMER (0x04) +#define NV2080_CTRL_THERMAL (0x05) +#define NV2080_CTRL_THERMAL_LEGACY_PRIVILEGED (0xc5) /* finn: Evaluated from "(NV2080_CTRL_THERMAL | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */ +#define NV2080_CTRL_THERMAL_LEGACY_NON_PRIVILEGED (0x85) /* finn: Evaluated from "(NV2080_CTRL_THERMAL | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_I2C (0x06) +#define NV2080_CTRL_EXTI2C (0x07) +#define NV2080_CTRL_BIOS (0x08) +#define NV2080_CTRL_CIPHER (0x09) +#define NV2080_CTRL_INTERNAL (0x0A) +#define NV2080_CTRL_CLK_LEGACY_PRIVILEGED (0xd0) /* finn: Evaluated from "(NV2080_CTRL_CLK | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */ +#define NV2080_CTRL_CLK_LEGACY_NON_PRIVILEGED (0x90) /* finn: Evaluated from "(NV2080_CTRL_CLK | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_CLK (0x10) +#define NV2080_CTRL_FIFO (0x11) +#define NV2080_CTRL_GR (0x12) +#define NV2080_CTRL_FB (0x13) +#define NV2080_CTRL_NOISE (0x15) +#define NV2080_CTRL_MC (0x17) +#define NV2080_CTRL_BUS (0x18) +#define NV2080_CTRL_PERF_LEGACY_PRIVILEGED (0xe0) /* finn: Evaluated from "(NV2080_CTRL_PERF | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */ +#define NV2080_CTRL_PERF_LEGACY_NON_PRIVILEGED (0xa0) /* finn: Evaluated from "(NV2080_CTRL_PERF | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_PERF (0x20) +#define NV2080_CTRL_NVIF (0x21) +#define NV2080_CTRL_RC (0x22) +#define NV2080_CTRL_GPIO (0x23) +#define NV2080_CTRL_GPIO_LEGACY_NON_PRIVILEGED (0xa3) /* finn: Evaluated from "(NV2080_CTRL_GPIO | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_NVD (0x24) +#define NV2080_CTRL_DMA (0x25) +#define NV2080_CTRL_PMGR (0x26) +#define NV2080_CTRL_PMGR_LEGACY_PRIVILEGED (0xe6) /* finn: Evaluated from "(NV2080_CTRL_PMGR | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */ +#define NV2080_CTRL_PMGR_LEGACY_NON_PRIVILEGED (0xa6) /* finn: Evaluated from "(NV2080_CTRL_PMGR | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_POWER (0x27) +#define NV2080_CTRL_POWER_LEGACY_NON_PRIVILEGED (0xa7) /* finn: Evaluated from "(NV2080_CTRL_POWER | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_LPWR (0x28) +#define NV2080_CTRL_LPWR_LEGACY_NON_PRIVILEGED (0xa8) /* finn: Evaluated from "(NV2080_CTRL_LPWR | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_LPWR_LEGACY_PRIVILEGED (0xe8) /* finn: Evaluated from "(NV2080_CTRL_LPWR | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */ +#define NV2080_CTRL_ACR (0x29) +#define NV2080_CTRL_CE (0x2A) +#define NV2080_CTRL_SPI (0x2B) +#define NV2080_CTRL_NVLINK (0x30) +#define NV2080_CTRL_FLCN (0x31) +#define NV2080_CTRL_VOLT (0x32) +#define NV2080_CTRL_VOLT_LEGACY_PRIVILEGED (0xf2) /* finn: Evaluated from "(NV2080_CTRL_VOLT | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */ +#define NV2080_CTRL_VOLT_LEGACY_NON_PRIVILEGED (0xb2) /* finn: Evaluated from "(NV2080_CTRL_VOLT | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_RIST (0x33) +#define NV2080_CTRL_RIST_LEGACY_PRIVILEGED (0xf3) /* finn: Evaluated from "(NV2080_CTRL_RIST | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */ +#define NV2080_CTRL_RIST_LEGACY_NON_PRIVILEGED (0xb3) /* finn: Evaluated from "(NV2080_CTRL_RIST | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_ECC (0x34) +#define NV2080_CTRL_ECC_NON_PRIVILEGED (0xb4) /* finn: Evaluated from "(NV2080_CTRL_ECC | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_FLA (0x35) +#define NV2080_CTRL_GSP (0x36) +#define NV2080_CTRL_NNE (0x37) +#define NV2080_CTRL_NNE_LEGACY_NON_PRIVILEGED (0xb7) /* finn: Evaluated from "(NV2080_CTRL_NNE | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_GRMGR (0x38) +#define NV2080_CTRL_UCODE_FUZZER (0x39) +#define NV2080_CTRL_DMABUF (0x3A) +#define NV2080_CTRL_BIF (0x3B) + + + +// per-OS categories start at highest category and work backwards +#define NV2080_CTRL_OS_WINDOWS (0x3F) +#define NV2080_CTRL_OS_MACOS (0x3E) +#define NV2080_CTRL_OS_UNIX (0x3D) + + +/* + * NV2080_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_NULL (0x20800000) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrl2080base_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080bif.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080bif.h new file mode 100644 index 0000000..e1344e2 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080bif.h @@ -0,0 +1,85 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023-25 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080bif.finn +// + +#include "nvcfg_sdk.h" +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX bif control commands and parameters + * This control command is intended for handling APIs that GET/SET information + * related to PCIe. + */ + +typedef enum NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG { + NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_INVALID = 0, + NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_DEVICE_CTRL_STATUS = 1, + NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_LINK_CTRL_STATUS = 2, + NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_DEVICE_CTRL_STATUS_2 = 3, + NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_LINK_CAP = 4, + NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_L1_PM_SUBSTATES_CTRL1 = 5, + NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_CHECK_FAILED_STATUS = 6, + NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_MISROUTED_TLP_STATUS = 7, + NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_PCRC_CHECK_FAILED_STATUS = 8, + NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_CHECK_FAILED_MASK = 9, + NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_MISROUTED_TLP_MASK = 10, + NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_PCRC_CHECK_FAILED_MASK = 11, + NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_CHECK_FAILED_SEVERITY = 12, + NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_MISROUTED_TLP_SEVERITY = 13, + NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_PCRC_CHECK_FAILED_SEVERITY = 14, + NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_TLP_ENCRYPTION_STATUS = 15, + NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_TYPE_LINK_STREAM_ENABLED = 16, + NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_TYPE_SELECTIVE_STREAM_ENABLED = 17, + NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_TYPE_FLOW_THROUGH_STREAM_ENABLED = 18, +} NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG; + +#define NV2080_CTRL_CMD_BIF_DATA_PARAMS_MAX 32 + +#define NV2080_CTRL_CMD_BIF_GET_DATA (0x20803b01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIF_INTERFACE_ID << 8) | NV2080_CTRL_BIF_GET_DATA_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BIF_GET_DATA_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_BIF_GET_DATA_PARAMS { + NvU32 featureId; + NvU32 paramId[NV2080_CTRL_CMD_BIF_DATA_PARAMS_MAX]; + NvU32 paramVal[NV2080_CTRL_CMD_BIF_DATA_PARAMS_MAX]; + NvU32 flags; + NvU32 paramSize; +} NV2080_CTRL_BIF_GET_DATA_PARAMS; + +typedef enum NV2080_CTRL_BIF_FEATURE_ID { + NV2080_CTRL_BIF_FEATURE_ID_INVALID = 0, + NV2080_CTRL_BIF_FEATURE_ID_CONFIG_REG = 1, + +} NV2080_CTRL_BIF_FEATURE_ID; + + + +/* _ctrl2080bif_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080bios.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080bios.h new file mode 100644 index 0000000..203c94a --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080bios.h @@ -0,0 +1,484 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080bios.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX bios-related control commands and parameters */ + + + +typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_BIOS_INFO; + +/* Maximum number of bios infos that can be queried at once */ +#define NV2080_CTRL_BIOS_INFO_MAX_SIZE (0x0000000F) + +#define NV2080_CTRL_BIOS_INFO_INDEX_REVISION (0x00000000) +#define NV2080_CTRL_BIOS_INFO_INDEX_OEM_REVISION (0x00000001) + + + +/* + * NV2080_CTRL_CMD_BIOS_GET_INFO + * + * This command returns bios information for the associated GPU. + * Requests to retrieve bios information use a list of one or more + * NV2080_CTRL_BIOS_INFO structures. + * + * biosInfoListSize + * This field specifies the number of entries on the caller's + * biosInfoList. + * biosInfoList + * This field specifies a pointer in the caller's address space + * to the buffer into which the bios information is to be returned. + * This buffer must be at least as big as biosInfoListSize multiplied + * by the size of the NV2080_CTRL_BIOS_INFO structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV2080_CTRL_CMD_BIOS_GET_INFO (0x20800802) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | 0x2" */ + +typedef struct NV2080_CTRL_BIOS_GET_INFO_PARAMS { + NvU32 biosInfoListSize; + NV_DECLARE_ALIGNED(NvP64 biosInfoList, 8); +} NV2080_CTRL_BIOS_GET_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_BIOS_GET_INFO_V2 + * + * This command returns bios information for the associated GPU. + * Requests to retrieve bios information use a list of one or more + * NV2080_CTRL_BIOS_INFO structures. + * + * biosInfoListSize + * This field specifies the number of entries on the caller's + * biosInfoList. + * biosInfoList + * Bios information to be returned. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV2080_CTRL_CMD_BIOS_GET_INFO_V2 (0x20800810) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS { + NvU32 biosInfoListSize; + NV2080_CTRL_BIOS_INFO biosInfoList[NV2080_CTRL_BIOS_INFO_MAX_SIZE]; +} NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS; + +/* + * NV2080_CTRL_BIOS_NBSI + * + * NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH + * This is the maximum length of a given registry string input (in characters). + * + * NV2080_CTRL_BIOS_NBSI_STRING_TYPE_ASCII + * This is a value indicating the format of a registry string is ascii. + * NV2080_CTRL_BIOS_NBSI_STRING_TYPE_UNICODE + * This is a value indicating the format of a registry string is unicode. + * NV2080_CTRL_BIOS_NBSI_STRING_TYPE_HASH + * This is a value indicating a registry string is actually a pre-hashed value. + * + * NV2080_CTRL_BIOS_NBSI_REG_STRING + * This is a structure used to store a registry string object. + * The members are as follows: + * + * size + * This is the size (in bytes) of the data contained in the string. If this + * is greater than the maximum registry string length, an error will be + * returned. + * type + * This is the type of data contained in the registry string. It can be either + * ascii, unicode or a pre-hashed value. + * value + * This is the value of the string. Depending on the type, a different object + * will be used to access the data. + */ +#define NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH (0x00000100) + +#define NV2080_CTRL_BIOS_NBSI_STRING_TYPE_ASCII (0x00000000) +#define NV2080_CTRL_BIOS_NBSI_STRING_TYPE_UNICODE (0x00000001) +#define NV2080_CTRL_BIOS_NBSI_STRING_TYPE_HASH (0x00000002) + +#define NV2080_CTRL_BIOS_NBSI_MODULE_ROOT (0x00000000) +#define NV2080_CTRL_BIOS_NBSI_MODULE_RM (0x00000001) +#define NV2080_CTRL_BIOS_NBSI_MODULE_DISPLAYDRIVER (0x00000002) +#define NV2080_CTRL_BIOS_NBSI_MODULE_VIDEO (0x00000003) +#define NV2080_CTRL_BIOS_NBSI_MODULE_CPL (0x00000004) +#define NV2080_CTRL_BIOS_NBSI_MODULE_D3D (0x00000005) +#define NV2080_CTRL_BIOS_NBSI_MODULE_OGL (0x00000006) +#define NV2080_CTRL_BIOS_NBSI_MODULE_PMU (0x00000007) +#define NV2080_CTRL_BIOS_NBSI_MODULE_MODE (0x00000008) +// this should equal the last NBSI_MODULE plus 1. +#define NV2080_CTRL_BIOS_NBSI_NUM_MODULES (0x00000009) + +// +// Never use this value! It's needed for DD/Video modules, but does not correspond +// to a valid NBSI hive! +// +#define NV2080_CTRL_BIOS_NBSI_MODULE_UNKNOWN (0x80000000) + +typedef struct NV2080_CTRL_BIOS_NBSI_REG_STRING { + NvU32 size; + NvU32 type; + + union { + NvU8 ascii[NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH]; + NvU16 unicode[NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH]; + NvU16 hash; + } value; +} NV2080_CTRL_BIOS_NBSI_REG_STRING; + + +/* + * NV2080_CTRL_CMD_BIOS_GET_NBSI + * + * module + * This field specifies the given module per the MODULE_TYPES enum. + * path + * This field specifies the full path and registry node name for a + * given NBSI object. This is a maximum of 255 unicode characters, + * but may be provided as ascii or a pre-formed hash per the type + * member. The size (in bytes) of the given string/hash should be + * provided in the size member. + * + * NOTE: In the case of an incomplete path such as HKR, one may pass + * in simply the root node. E.g.: + * 1.) Normal case: HKLM\Path\Subpath + * 2.) Unknown case: HKR + * It is expected that all unknown/incomplete paths will be determined + * prior to NBSI programming! There is otherwise NO WAY to match + * the hash given by an incomplete path to that stored in NBSI! + * + * valueName + * This field specifies the registry name for a given NBSI object. + * This is a maximum of 255 unicode characters, but may be provided + * in ascii or a pre-formed hash per the type member. The size (in bytes) + * of the given string/hash should be provided in the size member. + * retBuf + * This field provides a pointer to a buffer into which the value + * retrieved from NBSI may be returned + * retSize + * This field is an input/output. It specifies the maximum size of the + * return buffer as an input, and the size of the returned data as an + * output. + * errorCode + * This field is a return value. It gives an error code representing + * failure to return a value (as opposed to failure of the call). + * This obeys the following: + * + * NV2080_CTRL_BIOS_GET_NBSI_SUCCESS + * The call has returned complete and valid data. + * NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE + * The call returned complete and valid data which is expected to override + * any stored registry settings. + * NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE + * The call returned data, but the size of the return buffer was + * insufficient to contain it. The value returned in retSize represents + * the total size necessary (in bytes) to contain the data. + * if the size was non-0, the buffer is filled with the object contents up + * to that size. Can be used with retBufOffset to use multiple calls to get + * tables of very large size. + * NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND + * The call did not find a valid NBSI object for this key. This indicates + * NBSI has no opinion and, more importantly, any data returned is identical + * to data passed in. + * + * Possible return values are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_BIOS_GET_NBSI_SUCCESS (0x00000000) +#define NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE (0x00000001) +#define NV2080_CTRL_BIOS_GET_NBSI_BAD_HASH (0xFFFFFFFA) +#define NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS (0xFFFFFFFB) +#define NV2080_CTRL_BIOS_GET_NBSI_BAD_TABLE (0xFFFFFFFC) +#define NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE (0xFFFFFFFD) +#define NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE (0xFFFFFFFE) +#define NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND (0xFFFFFFFF) + +#define NV2080_CTRL_CMD_BIOS_GET_NBSI (0x20800803) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_NBSI_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BIOS_GET_NBSI_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_BIOS_GET_NBSI_PARAMS { + NvU32 module; + NV2080_CTRL_BIOS_NBSI_REG_STRING path; + NV2080_CTRL_BIOS_NBSI_REG_STRING valueName; + NV_DECLARE_ALIGNED(NvP64 retBuf, 8); + NvU32 retSize; + NvU32 errorCode; +} NV2080_CTRL_BIOS_GET_NBSI_PARAMS; + +#define NV2080_CTRL_CMD_BIOS_GET_NBSI_V2 (0x2080080e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_BIOS_GET_NBSI_MAX_RET_SIZE (0x100) + +#define NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS { + NvU32 module; + NV2080_CTRL_BIOS_NBSI_REG_STRING path; + NV2080_CTRL_BIOS_NBSI_REG_STRING valueName; + NvU8 retBuf[NV2080_BIOS_GET_NBSI_MAX_RET_SIZE]; + NvU32 retSize; + NvU32 errorCode; +} NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS; + +/* + * NV2080_CTRL_CMD_BIOS_GET_NBSI_OBJ + * + * globType + * This field specifies the glob type wanted + * 0xffff: APItest... returns NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS + * globIndex + * Index for globType desired + * 0 = best fit + * 1..255 = actual index + * globSource + * Index to nbsi directory sources used when getting entire directory + * 0 = registry + * 1 = VBIOS + * 2 = SBIOS + * 3 = ACPI + * retBufOffset + * When making multiple calls to get the object (if retSize is too small) + * offset into real object (0=start of object) + * retBuf + * This field provides a pointer to a buffer into which the object + * retrieved from NBSI may be returned + * retSize + * This field is an input/output. It specifies the maximum size of the + * return buffer as an input, and the size of the returned data as an + * output. + * totalObjSize + * This field is an output, where the total size of the object being + * retrieved is returned. + * errorCode + * This field is a return value. It gives an error code representing + * failure to return a value (as opposed to failure of the call). + * This obeys the following: + * + * NV2080_CTRL_BIOS_GET_NBSI_SUCCESS + * The call has returned complete and valid data. + * NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE + * The call returned complete and valid data which is expected to override + * any stored registry settings. + * NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE + * The call returned data, but the size of the return buffer was + * insufficient to contain it. The value returned in retSize represents + * the total size necessary (in bytes) to contain the data. + * NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND + * The call did not find a valid NBSI object for this key. This indicates + * NBSI has no opinion and, more importantly, any data returned is identical + * to data passed in. + * + * Possible return values are: + * NV2080_CTRL_BIOS_GET_NBSI_SUCCESS + * NV2080_CTRL_BIOS_GET_NBSI_APITEST_NODIRACCESS + * NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS + * NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE + * NV2080_CTRL_BIOS_GET_NBSI_BAD_TABLE + * NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE + * NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND + */ +#define NV2080_CTRL_CMD_BIOS_GET_NBSI_OBJ (0x20800806) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS { + NvU16 globType; + NvU8 globIndex; + NvU16 globSource; + NvU32 retBufOffset; + NV_DECLARE_ALIGNED(NvP64 retBuf, 8); + NvU32 retSize; + NvU32 totalObjSize; + NvU32 errorCode; +} NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS; + +#define GLOB_TYPE_GET_NBSI_DIR 0xfffe +#define GLOB_TYPE_APITEST 0xffff +#define GLOB_TYPE_GET_NBSI_ACPI_RAW 0xfffd + + + +/* + * NV2080_CTRL_CMD_BIOS_GET_SKU_INFO + * + * This command returns information about the current board SKU. + * NV_ERR_INVALID_OWNER will be returned if the call + * isn't made with the OS as the administrator. + * + * chipSKU + * This field returns the sku for the current chip. + * chipSKUMod + * This field returns the SKU modifier. + * skuConfigVersion + * Version number for the SKU configuration detailing pstate, thermal, VF curve and so on. + * project + * This field returns the Project (Board) number. + * projectSKU + * This field returns the Project (Board) SKU number. + * CDP + * This field returns the Collaborative Design Project Number. + * projectSKUMod + * This field returns the Project (Board) SKU Modifier. + * businessCycle + * This field returns the business cycle the board is associated with. + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OWNER + */ +#define NV2080_CTRL_CMD_BIOS_GET_SKU_INFO (0x20800808) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS { + NvU32 BoardID; + char chipSKU[9]; + char chipSKUMod[5]; + NvU32 skuConfigVersion; + char project[5]; + char projectSKU[5]; + char CDP[6]; + char projectSKUMod[2]; + NvU32 businessCycle; +} NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_BIOS_GET_POST_TIME + + * This command is used to get the GPU POST time (in milliseconds). + * If the associated GPU is the master GPU this value will be recorded + * by the VBIOS and retrieved from the KDA buffer. If the associated + * GPU is a secondaryGPU then this value will reflect the devinit + * processing time. + * + * vbiosPostTime + * This parameter returns the vbios post time in msec. + * + * Possible return status values are + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV2080_CTRL_CMD_BIOS_GET_POST_TIME (0x20800809) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS { + NV_DECLARE_ALIGNED(NvU64 vbiosPostTime, 8); +} NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS; + + + +/* + * NV2080_CTRL_CMD_BIOS_GET_UEFI_SUPPORT + * + * This function is used to give out the UEFI version, UEFI image presence and + * Graphics Firmware Mode i.e. whether system is running in UEFI or not. + * + * version + * This parameter returns the UEFI version. + * + * flags + * This parameter indicates UEFI image presence and Graphics Firmware mode. + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE + * This field returns UEFI presence value. Legal values for this + * field include: + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_NO + * This value indicates that UEFI image is not present. + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_YES + * This value indicates that UEFI image is present. + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_PLACEHOLDER + * This value indicates that there is a dummy UEFI placeholder, + * which can later be updated with a valid UEFI image. + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_HIDDEN + * This value indicates that UEFI image is hidden. + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING + * This field indicates the UEFI running value. Legal values for + * this parameter include: + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_FALSE + * This value indicates that UEFI is not running. + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE + * This value indicates that UEFI is running. + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT + * This field indicates the EFI running value. Legal values for + * this parameter include: + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_FALSE + * This value indicates that display is in vbios mode. + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_TRUE + * This value indicates that display is in EFI mode. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_READY + * NV_ERR_INVALID_STATE + */ + +#define NV2080_CTRL_CMD_BIOS_GET_UEFI_SUPPORT (0x2080080b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS { + NvU32 version; + NvU32 flags; +} NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS; + +/* Legal values for flags parameter */ +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE 1:0 +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_NO (0x00000000) +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_YES (0x00000001) +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_PLACEHOLDER (0x00000002) +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_HIDDEN (0x00000003) +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING 2:2 +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_FALSE (0x00000000) +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE (0x00000001) +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT 3:3 +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_FALSE (0x00000000) +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_TRUE (0x00000001) + + + +/* _ctrl2080bios_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080boardobj.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080boardobj.h new file mode 100644 index 0000000..43912a6 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080boardobj.h @@ -0,0 +1,1280 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080boardobj.finn +// + + + +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h" + +/*! + * @brief NV20_SUBDEVICE_XX BOARDOBJ-related control commands and parameters. + * + * Base structures in RMCTRL equivalent to BOARDOBJ/BOARDOBJGRP in RM. NV2080 + * structs in this file carry info w.r.t BOARDOBJ/BOARDOBJGRP. + */ + +/*! + * @brief Type for representing an index of a BOARDOBJ within a + * BOARDOBJGRP. This type can also represent the number of elements + * within a BOARDOBJGRP or the number of bits in a BOARDOBJGRPMASK. + */ +typedef NvU16 NvBoardObjIdx; + +/*! + * @brief Type for representing an index into a mask element within a + * BOARDOBJGRPMASK to a @ref NV2080_CTRL_BOARDOBJGRP_MASK_PRIMITIVE. + */ +typedef NvU16 NvBoardObjMaskIdx; + +/*! + * @brief Primitive type which a BOARDOBJGRPMASK is composed of. + * + * For example, a 32 bit mask will have one of these elements and a 256 bit + * mask will have eight. + */ +typedef NvU32 NV2080_CTRL_BOARDOBJGRP_MASK_PRIMITIVE; + +/*! + * @brief Min value a single BOARDOBJGRPMASK element can hold. + * + * @note Must be kept in sync with @ref + * NV2080_CTRL_BOARDOBJGRP_MASK_PRIMITIVE. + */ +#define NV2080_CTRL_BOARDOBJGRP_MASK_ELEMENT_MIN NV_U32_MIN + +/*! + * @brief Max value a single BOARDOBJGRPMASK element can hold. + * + * @note Must be kept in sync with @ref + * NV2080_CTRL_BOARDOBJGRP_MASK_PRIMITIVE. + */ +#define NV2080_CTRL_BOARDOBJGRP_MASK_ELEMENT_MAX NV_U32_MAX + +/*! + * @brief Number of bits in a the NV2080_CTRL_BOARDOBJGRP_MASK_PRIMITIVE type. + * + * This exists to eliminate the assumption that 32-bits is the width of + * NV2080_CTRL_BOARDOBJGRP_MASK primitive element. + * + * @note Left shift by 3 (multiply by 8) converts the sizeof in bytes to the + * number of bits in our primitive/essential mask type. + */ +#define NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE 32 + +/*! + * @brief Value for an invalid Board Object index. + * + * This value should only be used directly for input to and output + * from BOARDOBJ and BOARDOBJGRP code. + * + * @note This define should not be referenced directly in any + * implementing object code. Instead, each object should define it's + * own IDX_INVALID macro and alias it to whatever size fits their + * specific index storage type. + * For example, many objects still store indexes as NvU8 (because the + * GRPs are either _E32 or _E255) while others store as NvBoardObjIdx + * (currently aliased to NvU16), so they should alias to a correct + * type. + */ +#define NV2080_CTRL_BOARDOBJ_IDX_INVALID NV_U16_MAX + +/*! + * @brief Value for an invalid Board Object index. + * + * This value encodes an invalid/unsupported BOARDOBJ index for an + * 8-bit value. This should be used within by any legacy appcode + * implementing BOARDOBJGRP which stores/encodes indexes as 8-bit + * values. + * + * All new groups should use @ref NV2080_CTRL_BOARDOBJ_IDX_INVALID. + * + * @note This define should not be referenced directly in any + * implementing object code. Instead, each object should define it's + * own IDX_INVALID macro and alias it to whatever size fits their + * specific index storage type. + * For example, many objects still store indexes as NvU8 (because the + * GRPs are either _E32 or _E255) while others store as NvU16 (for + * GRPs larger than _E255), so they should alias to a correct type. + */ +#define NV2080_CTRL_BOARDOBJ_IDX_INVALID_8BIT NV_U8_MAX + +/*! + * @brief Computes the array index of a NV2080_CTRL_BOARDOBJGRP_MASK element + * storing requested bit. + * + * @note Designed to be used in conjunction with @ref + * NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET. + * + * @param[in] _bit Index of a bit within a bit mask. + * + * @return Array index of mask element containing @ref _bit. + */ +#define NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(_bit) \ + ((_bit) / NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE) + +/*! + * @brief Computes bit-position within NV2080_CTRL_BOARDOBJGRP_MASK element + * corresponding to requested bit. + * + * @note Designed to be used in conjunction with @ref + * NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX. + * + * @param[in] _bit Index of a bit within a bit mask. + * + * @return Offset (in bits) within a mask element for @ref _bit. + */ +#define NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(_bit) \ + ((_bit) % NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE) + +/*! + * @brief Computes the size of an array of NV2080_CTRL_BOARDOBJGRP_MASK + * elements that can store all mask's bits. + * + * @param[in] _bits Size of the mask in bits. + * + * @return Number of array elements needed to store @ref _bits number of bits. + */ +#define NV2080_CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits) \ + (NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX((_bits) - 1U) + 1U) + + +/*! + * @brief Number of elements that are in the NV2080_CTRL_BOARDOBJGRP_MASK base + * class. + * + * @note "START_SIZE" is used here to represent the size of the mask that + * derived classes must build up from. See @ref + * NV2080_CTRL_BOARDOBJGRP_MASK_E32, @ref + * NV2080_CTRL_BOARDOBJGRP_MASK_E255, @ref + * NV2080_CTRL_BOARDOBJGRP_MASK_E512, @ref + * NV2080_CTRL_BOARDOBJGRP_MASK_E1024, @ref + * NV2080_CTRL_BOARDOBJGRP_MASK_E2048, @ref + * NV2080_CTRL_BOARDOBJGRP_MASK_E8192. + */ +#define NV2080_CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE 1U + +/*! + * @brief Macro used to determine the number of NV2080_CTRL_BOARDOBJGRP_MASK + * elements required to extend the base number of elements in a mask, + * @ref NV2080_CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE. + * + * @note Used in order to avoid dynamic memory allocation and related + * code/data waste as well as two levels of indirection while accessing + * the data bits stored in an array of @ref + * NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE sized words. The + * NV2080_CTRL_BOARDOBJGRP_MASK super-class array's size should be + * zero and actual data should be completely stored in child's array. + * Since most compilers reject structures with zero-sized arrays first + * element word was moved to the super-class and remaining array + * elements to child class. + * + * @param[in] _bits Total number of bits to be represented in the + * NV2080_CTRL_BOARDOBJGRP_MASK extending mask class. + * + * @return Number of additional mask elements that must be allocated in order + * to extend the NV2080_CTRL_BOARDOBJGRP_MASK base class. + */ +#define NV2080_CTRL_BOARDOBJGRP_MASK_ARRAY_EXTENSION_SIZE(_bits) \ + (NV2080_CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits) - \ + (NV2080_CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE)) + +/*! + * @deprecated DO NOT USE! Use a sub-class specific + * NV2080_CTRL_BOARDOBJGRP_MASK_E*_BIT_GET variant + */ +#define NV2080_CTRL_BOARDOBJGRP_MASK_BIT_GET__DEPRECATED_DO_NOT_USE(_pMask, _bitIdx) \ + (((_pMask)->pData[NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(_bitIdx)]\ + & NVBIT_TYPE(NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(_bitIdx), \ + NV2080_CTRL_BOARDOBJGRP_MASK_PRIMITIVE)) != 0U) + +/*! + * @deprecated DO NOT USE!: Use a sub-class specific + * @ref NV2080_CTRL_BOARDOBJGRP_MASK_E*_FOR_EACH_INDEX_TYPED + * variant + */ +#define NV2080_CTRL_BOARDOBJGRP_MASK_FOR_EACH_INDEX__DEPRECATED_DO_NOT_USE(_maxObjects,_index,_pMask) \ +{ \ + for ((_index) = 0; (_index) < (_maxObjects); (_index)++) \ + { \ + if(!NV2080_CTRL_BOARDOBJGRP_MASK_BIT_GET__DEPRECATED_DO_NOT_USE((_pMask), (_index))) \ + { \ + continue; \ + } +#define NV2080_CTRL_BOARDOBJGRP_MASK_FOR_EACH_INDEX_END \ + } \ +} + +/*! + * @deprecated DO NOT USE! Use type-safe + * @ref NV2080_CTRL_BOARDOBJGRP_MASK_E32_FOR_EACH_INDEX + * instead + */ +#define NV2080_CTRL_BOARDOBJGRP_MASK_E32_FOR_EACH_INDEX__DEPRECATED(_index,_pMask) \ + NV2080_CTRL_BOARDOBJGRP_MASK_FOR_EACH_INDEX__DEPRECATED_DO_NOT_USE( \ + NV2080_CTRL_BOARDOBJGRP_E32_MAX_OBJECTS,_index,_pMask) + +/*! + * @deprecated DO NOT USE! Use type-safe + * @ref NV2080_CTRL_BOARDOBJGRP_MASK_E255_FOR_EACH_INDEX + * instead + */ +#define NV2080_CTRL_BOARDOBJGRP_MASK_E255_FOR_EACH_INDEX__DEPRECATED(_index,_pMask) \ + NV2080_CTRL_BOARDOBJGRP_MASK_FOR_EACH_INDEX__DEPRECATED_DO_NOT_USE( \ + NV2080_CTRL_BOARDOBJGRP_E255_MAX_OBJECTS,_index,_pMask) + +/*! + * @brief Board Object Group Mask base class. + * + * Used to unify access to all NV2080_CTRL_BOARDOBJGRP_MASK_E** child classes. + */ +typedef struct NV2080_CTRL_BOARDOBJGRP_MASK { + /*! + * @brief Start with a single element array which is enough to represent + * NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE bits. + * + * @note Must be the last member of this structure. + */ + // FINN PORT: The below field is a bit vector! + // In FINN, bit vectors are arrays of bools and each bool becomes 1 bit when used in an array + // FINN generates an array of NvU32's on the back end for these bit vectors + NvU32 pData[1] /* 32 bits */; +} NV2080_CTRL_BOARDOBJGRP_MASK; +typedef struct NV2080_CTRL_BOARDOBJGRP_MASK *PNV2080_CTRL_BOARDOBJGRP_MASK; + +/*! + * @brief NV2080_CTRL_BOARDOBJGRP_MASK child class capable of storing 32 bits + * indexed between 0..31. + */ +typedef struct NV2080_CTRL_BOARDOBJGRP_MASK_E32 { + /*! + * @brief NV2080_CTRL_BOARDOBJGRP_MASK super-class. Must be the first + * member of the structure. + */ + NV2080_CTRL_BOARDOBJGRP_MASK super; +} NV2080_CTRL_BOARDOBJGRP_MASK_E32; +typedef struct NV2080_CTRL_BOARDOBJGRP_MASK_E32 *PNV2080_CTRL_BOARDOBJGRP_MASK_E32; + +/*! + * @brief NV2080_CTRL_BOARDOBJGRP_MASK child class capable of storing 255 bits + * indexed between 0..254. + */ +typedef struct NV2080_CTRL_BOARDOBJGRP_MASK_E255 { + /*! + * @brief NV2080_CTRL_BOARDOBJGRP_MASK super-class. Must be the first + * member of the structure. + */ + NV2080_CTRL_BOARDOBJGRP_MASK super; + + /*! + * @brief Continuation of the array of + * NV2080_CTRL_BOARDOBJGRP_MASK_PRIMITIVE elements representing the + * bit-mask. + * + * @note Must be the second member of the structure. + */ + + // FINN PORT: The below field is a bit vector! + // In FINN, bit vectors are arrays of bools and each bool becomes 1 bit when used in an array + // FINN generates an array of NvU32's on the back end for these bit vectors + NvU32 pDataE255[7] /* 223 bits */; +} NV2080_CTRL_BOARDOBJGRP_MASK_E255; +typedef struct NV2080_CTRL_BOARDOBJGRP_MASK_E255 *PNV2080_CTRL_BOARDOBJGRP_MASK_E255; + +/*! + * @brief NV2080_CTRL_BOARDOBJGRP_MASK child class capable of storing 512 bits + * indexed between 0..511. + */ +typedef struct NV2080_CTRL_BOARDOBJGRP_MASK_E512 { + /*! + * @brief NV2080_CTRL_BOARDOBJGRP_MASK super-class. Must be the first + * member of the structure. + */ + NV2080_CTRL_BOARDOBJGRP_MASK super; + + /*! + * @brief Continuation of the array of + * NV2080_CTRL_BOARDOBJGRP_MASK_PRIMITIVE elements representing the + * bit-mask. + * + * @note Must be the second member of the structure. + */ + + // FINN PORT: The below field is a bit vector! + // In FINN, bit vectors are arrays of bools and each bool becomes 1 bit when used in an array + // FINN generates an array of NvU32's on the back end for these bit vectors + NvU32 pDataE512[15] /* 480 bits */; +} NV2080_CTRL_BOARDOBJGRP_MASK_E512; +typedef struct NV2080_CTRL_BOARDOBJGRP_MASK_E512 *PNV2080_CTRL_BOARDOBJGRP_MASK_E512; + +/*! + * @brief NV2080_CTRL_BOARDOBJGRP_MASK child class capable of storing 1024 bits + * indexed between 0..1023. + */ +typedef struct NV2080_CTRL_BOARDOBJGRP_MASK_E1024 { + /*! + * @brief NV2080_CTRL_BOARDOBJGRP_MASK super-class. Must be the first + * member of the structure. + */ + NV2080_CTRL_BOARDOBJGRP_MASK super; + + /*! + * @brief Continuation of the array of + * NV2080_CTRL_BOARDOBJGRP_MASK_PRIMITIVE elements representing the + * bit-mask. + * + * @note Must be the second member of the structure. + */ + + // FINN PORT: The below field is a bit vector! + // In FINN, bit vectors are arrays of bools and each bool becomes 1 bit when used in an array + // FINN generates an array of NvU32's on the back end for these bit vectors + NvU32 pDataE1024[31] /* 992 bits */; +} NV2080_CTRL_BOARDOBJGRP_MASK_E1024; +typedef struct NV2080_CTRL_BOARDOBJGRP_MASK_E1024 *PNV2080_CTRL_BOARDOBJGRP_MASK_E1024; + +/*! + * @brief NV2080_CTRL_BOARDOBJGRP_MASK child class capable of storing 2048 bits + * indexed between 0..2047. + */ +typedef struct NV2080_CTRL_BOARDOBJGRP_MASK_E2048 { + /*! + * @brief NV2080_CTRL_BOARDOBJGRP_MASK super-class. Must be the first + * member of the structure. + */ + NV2080_CTRL_BOARDOBJGRP_MASK super; + + /*! + * @brief Continuation of the array of + * NV2080_CTRL_BOARDOBJGRP_MASK_PRIMITIVE elements representing the + * bit-mask. + * + * @note Must be the second member of the structure. + */ + + // FINN PORT: The below field is a bit vector! + // In FINN, bit vectors are arrays of bools and each bool becomes 1 bit when used in an array + // FINN generates an array of NvU32's on the back end for these bit vectors + NvU32 pDataE2048[63] /* 2016 bits */; +} NV2080_CTRL_BOARDOBJGRP_MASK_E2048; +typedef struct NV2080_CTRL_BOARDOBJGRP_MASK_E2048 *PNV2080_CTRL_BOARDOBJGRP_MASK_E2048; + +/*! + * @brief NV2080_CTRL_BOARDOBJGRP_MASK child class capable of storing 8192 bits + * indexed between 0..8191. + */ +typedef struct NV2080_CTRL_BOARDOBJGRP_MASK_E8192 { + /*! + * @brief NV2080_CTRL_BOARDOBJGRP_MASK super-class. Must be the first + * member of the structure. + */ + NV2080_CTRL_BOARDOBJGRP_MASK super; + + /*! + * @brief Continuation of the array of + * NV2080_CTRL_BOARDOBJGRP_MASK_PRIMITIVE elements representing the + * bit-mask. + * + * @note Must be the second member of the structure. + */ + + // FINN PORT: The below field is a bit vector! + // In FINN, bit vectors are arrays of bools and each bool becomes 1 bit when used in an array + // FINN generates an array of NvU32's on the back end for these bit vectors + NvU32 pDataE8192[255] /* 8160 bits */; +} NV2080_CTRL_BOARDOBJGRP_MASK_E8192; +typedef struct NV2080_CTRL_BOARDOBJGRP_MASK_E8192 *PNV2080_CTRL_BOARDOBJGRP_MASK_E8192; + +/*! + * @brief Macro to provide the BOARDOBJ type for a given (UNIT, CLASS, TYPE) + * combination. + * + * @details For arguments (FOO, BAR, BAZ), this macro will return + * NV2080_CTRL_FOO_BAR_TYPE_BAZ + * + * @param[in] _unit The unit. + * @param[in] _class The class. + * @param[in] _type The type. + * + * @return BOARDOBJ object type identifier. + */ +#define NV2080_CTRL_BOARDOBJ_TYPE(_unit, _class, _type) \ + NV2080_CTRL_##_unit##_##_class##_TYPE_##_type + + + +/*! + * @brief Base structure which describes a BOARDOBJ CLIENT_INFO in RMCTRL. + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO { + /*! + * @brief BOARDOBJ type. + * + * This should be a unique value within the class that the BOARDOBJ belongs. + */ + NvU8 type; +} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO; + +/*! + * @brief Base structure which describes a BOARDOBJ CLIENT_STATUS in RMCTRL. + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS { + /*! + * @brief BOARDOBJ type. + * + * This should be a unique value within the class that the BOARDOBJ belongs. + */ + NvU8 type; +} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS; + +/*! + * @brief Base structure which describes a BOARDOBJ CLIENT_CONTROL in RMCTRL. + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL { + /*! + * @brief BOARDOBJ type. + * + * This should be a unique value within the class that the BOARDOBJ belongs. + */ + NvU8 type; +} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL; + +/*! + * @brief Base structure which describes a BOARDOBJ CLIENT_READINGS in RMCTRL. + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS { + /*! + * @brief BOARDOBJ type. + * + * This should be a unique value within the class that the BOARDOBJ belongs. + */ + NvU8 type; +} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS; + +/*! + * @brief Base structure which describes a CLIENT_INFO BOARDOBJ_INTERFACE in RMCTRL. + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_INTERFACE { + /*! + * @brief Reserved for future use cases. + */ + NvU8 rsvd; +} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_INTERFACE; + +/*! + * @brief Base structure which describes a CLIENT_STATUS BOARDOBJ_INTERFACE in RMCTRL. + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_INTERFACE { + /*! + * @brief Reserved for future use cases. + */ + NvU8 rsvd; +} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_INTERFACE; + +/*! + * @brief Base structure which describes a CLIENT_CONTROL BOARDOBJ_INTERFACE in RMCTRL. + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_INTERFACE { + /*! + * @brief Reserved for future use cases. + */ + NvU8 rsvd; +} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_INTERFACE; + +/*! + * @brief Base structure which describes a CLIENT_READINGS BOARDOBJ_INTERFACE in RMCTRL. + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_INTERFACE { + /*! + * @brief Reserved for future use cases. + */ + NvU8 rsvd; +} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_INTERFACE; + +/*! + * @brief Structure representing CLIENT_INFO for a BOARDOBJ_IFACE_MODEL interface + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL { + /*! + * Super class CLIENT_INFO + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_INTERFACE super; +} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL; + +/*! + * @brief Structure representing CLIENT_INFO for a BOARDOBJ_IFACE_MODEL_20 + * interface + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL_20 { + /*! + * Super class CLIENT_INFO + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL super; +} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL_20; + +/*! + * @brief Structure representing CLIENT_INFO for a + * BOARDOBJ_IFACE_MODEL_PMU_INIT_1X interface + * + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL_PMU_INIT_1X { + /*! + * Super class CLIENT_INFO + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL_20 super; +} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL_PMU_INIT_1X; + +/*! + * @brief Structure representing CLIENT_STATUS for a BOARDOBJ_IFACE_MODEL interface + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL { + /*! + * Super class CLIENT_STATUS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_INTERFACE super; +} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL; + +/*! + * @brief Structure representing CLIENT_STATUS for a BOARDOBJ_IFACE_MODEL_20 + * interface + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL_20 { + /*! + * Super class CLIENT_STATUS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL super; +} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL_20; + +/*! + * @brief Structure representing CLIENT_STATUS for a + * BOARDOBJ_IFACE_MODEL_PMU_INIT_1X interface + * + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL_PMU_INIT_1X { + /*! + * Super class CLIENT_STATUS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL_20 super; +} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL_PMU_INIT_1X; + +/*! + * @brief Structure representing CLIENT_CONTROL for a BOARDOBJ_IFACE_MODEL interface + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL { + /*! + * Super class CLIENT_CONTROL + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_INTERFACE super; +} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL; + +/*! + * @brief Structure representing CLIENT_CONTROL for a BOARDOBJ_IFACE_MODEL_20 + * interface + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL_20 { + /*! + * Super class CLIENT_CONTROL + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL super; +} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL_20; + +/*! + * @brief Structure representing CLIENT_CONTROL for a + * BOARDOBJ_IFACE_MODEL_PMU_INIT_1X interface + * + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL_PMU_INIT_1X { + /*! + * Super class CLIENT_CONTROL + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL_20 super; +} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL_PMU_INIT_1X; + +/*! + * @brief Structure representing CLIENT_READINGS for a BOARDOBJ_IFACE_MODEL interface + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL { + /*! + * Super class CLIENT_READINGS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_INTERFACE super; +} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL; + +/*! + * @brief Structure representing CLIENT_READINGS for a BOARDOBJ_IFACE_MODEL_20 + * interface + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL_20 { + /*! + * Super class CLIENT_READINGS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL super; +} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL_20; + +/*! + * @brief Structure representing CLIENT_READINGS for a + * BOARDOBJ_IFACE_MODEL_PMU_INIT_1X interface + * + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL_PMU_INIT_1X { + /*! + * Super class CLIENT_READINGS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL_20 super; +} NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL_PMU_INIT_1X; + +/*! + * CLIENT_INFO data for @ref BOARDOBJGRP base class + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO { + /*! + * @brief Concrete class type of this BOARDOBJGRP + */ + NvU8 classType; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO; + +/*! + * CLIENT_INFO SUPER_ALIAS version for @ref BOARDOBJGRP base class + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_SUPER_ALIAS { + /*! + * Base class CLIENT_INFO + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO super; + + NV2080_CTRL_BOARDOBJGRP_MASK objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_SUPER_ALIAS; + +/*! + * CLIENT_STATUS data for @ref BOARDOBJGRP base class + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS { + /*! + * @brief Concrete class type of this BOARDOBJGRP + */ + NvU8 classType; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS; + +/*! + * CLIENT_STATUS SUPER_ALIAS version for @ref BOARDOBJGRP base class + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_SUPER_ALIAS { + /*! + * Base class CLIENT_STATUS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS super; + + NV2080_CTRL_BOARDOBJGRP_MASK objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_SUPER_ALIAS; + +/*! + * CLIENT_CONTROL data for @ref BOARDOBJGRP base class + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL { + /*! + * @brief Concrete class type of this BOARDOBJGRP + */ + NvU8 classType; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL; + +/*! + * CLIENT_CONTROL SUPER_ALIAS version for @ref BOARDOBJGRP base class + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_SUPER_ALIAS { + /*! + * Base class CLIENT_CONTROL + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL super; + + NV2080_CTRL_BOARDOBJGRP_MASK objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_SUPER_ALIAS; + +/*! + * CLIENT_READINGS data for @ref BOARDOBJGRP base class + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS { + /*! + * @brief Concrete class type of this BOARDOBJGRP + */ + NvU8 classType; + + /*! + * Whether the CLIENT_READINGS have been initialized. + * This should be set to false on any initial call into the API + */ + NvBool bInitialized; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS; + +/*! + * CLIENT_READINGS SUPER_ALIAS version for @ref BOARDOBJGRP base class + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_SUPER_ALIAS { + /*! + * Base class CLIENT_READINGS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS super; + + NV2080_CTRL_BOARDOBJGRP_MASK objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_SUPER_ALIAS; + +/*! + * CLIENT_INFO for @ref BOARDOBJGRP_E32 + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E32 { + /*! + * Base class CLIENT_INFO + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO super; + + /*! + * Mask of valid @ref BOARDOBJ objects within the payload + */ + NV2080_CTRL_BOARDOBJGRP_MASK_E32 objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E32; + +/*! + * CLIENT_STATUS for @ref BOARDOBJGRP_E32 + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E32 { + /*! + * Base class CLIENT_STATUS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS super; + + /*! + * Mask of valid @ref BOARDOBJ objects within the payload + */ + NV2080_CTRL_BOARDOBJGRP_MASK_E32 objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E32; + +/*! + * CLIENT_CONTROL for @ref BOARDOBJGRP_E32 + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E32 { + /*! + * Base class CLIENT_CONTROL + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL super; + + /*! + * Mask of valid @ref BOARDOBJ objects within the payload + */ + NV2080_CTRL_BOARDOBJGRP_MASK_E32 objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E32; + +/*! + * CLIENT_READINGS for @ref BOARDOBJGRP_E32 + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E32 { + /*! + * Base class CLIENT_READINGS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS super; + + /*! + * Mask of valid @ref BOARDOBJ objects within the payload + */ + NV2080_CTRL_BOARDOBJGRP_MASK_E32 objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E32; + +/*! + * CLIENT_INFO for @ref BOARDOBJGRP_E255 + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E255 { + /*! + * Base class CLIENT_INFO + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO super; + + /*! + * Mask of valid @ref BOARDOBJ objects within the payload + */ + NV2080_CTRL_BOARDOBJGRP_MASK_E255 objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E255; + +/*! + * CLIENT_STATUS for @ref BOARDOBJGRP_E255 + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E255 { + /*! + * Base class CLIENT_STATUS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS super; + + /*! + * Mask of valid @ref BOARDOBJ objects within the payload + */ + NV2080_CTRL_BOARDOBJGRP_MASK_E255 objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E255; + +/*! + * CLIENT_CONTROL for @ref BOARDOBJGRP_E255 + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E255 { + /*! + * Base class CLIENT_CONTROL + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL super; + + /*! + * Mask of valid @ref BOARDOBJ objects within the payload + */ + NV2080_CTRL_BOARDOBJGRP_MASK_E255 objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E255; + +/*! + * CLIENT_READINGS for @ref BOARDOBJGRP_E255 + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E255 { + /*! + * Base class CLIENT_READINGS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS super; + + /*! + * Mask of valid @ref BOARDOBJ objects within the payload + */ + NV2080_CTRL_BOARDOBJGRP_MASK_E255 objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E255; + +/*! + * CLIENT_INFO for @ref BOARDOBJGRP_E512 + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E512 { + /*! + * Base class CLIENT_INFO + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO super; + + /*! + * Mask of valid @ref BOARDOBJ objects within the payload + */ + NV2080_CTRL_BOARDOBJGRP_MASK_E512 objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E512; + +/*! + * CLIENT_STATUS for @ref BOARDOBJGRP_E512 + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E512 { + /*! + * Base class CLIENT_STATUS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS super; + + /*! + * Mask of valid @ref BOARDOBJ objects within the payload + */ + NV2080_CTRL_BOARDOBJGRP_MASK_E512 objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E512; + +/*! + * CLIENT_CONTROL for @ref BOARDOBJGRP_E512 + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E512 { + /*! + * Base class CLIENT_CONTROL + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL super; + + /*! + * Mask of valid @ref BOARDOBJ objects within the payload + */ + NV2080_CTRL_BOARDOBJGRP_MASK_E512 objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E512; + +/*! + * CLIENT_READINGS for @ref BOARDOBJGRP_E512 + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E512 { + /*! + * Base class CLIENT_READINGS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS super; + + /*! + * Mask of valid @ref BOARDOBJ objects within the payload + */ + NV2080_CTRL_BOARDOBJGRP_MASK_E512 objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E512; + +/*! + * CLIENT_INFO for @ref BOARDOBJGRP_E1024 + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E1024 { + /*! + * Base class CLIENT_INFO + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO super; + + /*! + * Mask of valid @ref BOARDOBJ objects within the payload + */ + NV2080_CTRL_BOARDOBJGRP_MASK_E1024 objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E1024; + +/*! + * CLIENT_STATUS for @ref BOARDOBJGRP_E1024 + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E1024 { + /*! + * Base class CLIENT_STATUS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS super; + + /*! + * Mask of valid @ref BOARDOBJ objects within the payload + */ + NV2080_CTRL_BOARDOBJGRP_MASK_E1024 objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E1024; + +/*! + * CLIENT_CONTROL for @ref BOARDOBJGRP_E1024 + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E1024 { + /*! + * Base class CLIENT_CONTROL + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL super; + + /*! + * Mask of valid @ref BOARDOBJ objects within the payload + */ + NV2080_CTRL_BOARDOBJGRP_MASK_E1024 objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E1024; + +/*! + * CLIENT_READINGS for @ref BOARDOBJGRP_E1024 + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E1024 { + /*! + * Base class CLIENT_READINGS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS super; + + /*! + * Mask of valid @ref BOARDOBJ objects within the payload + */ + NV2080_CTRL_BOARDOBJGRP_MASK_E1024 objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E1024; + +/*! + * CLIENT_INFO for @ref BOARDOBJGRP_E2048 + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E2048 { + /*! + * Base class CLIENT_INFO + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO super; + + /*! + * Mask of valid @ref BOARDOBJ objects within the payload + */ + NV2080_CTRL_BOARDOBJGRP_MASK_E2048 objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E2048; + +/*! + * CLIENT_STATUS for @ref BOARDOBJGRP_E2048 + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E2048 { + /*! + * Base class CLIENT_STATUS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS super; + + /*! + * Mask of valid @ref BOARDOBJ objects within the payload + */ + NV2080_CTRL_BOARDOBJGRP_MASK_E2048 objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E2048; + +/*! + * CLIENT_CONTROL for @ref BOARDOBJGRP_E2048 + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E2048 { + /*! + * Base class CLIENT_CONTROL + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL super; + + /*! + * Mask of valid @ref BOARDOBJ objects within the payload + */ + NV2080_CTRL_BOARDOBJGRP_MASK_E2048 objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E2048; + +/*! + * CLIENT_READINGS for @ref BOARDOBJGRP_E2048 + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E2048 { + /*! + * Base class CLIENT_READINGS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS super; + + /*! + * Mask of valid @ref BOARDOBJ objects within the payload + */ + NV2080_CTRL_BOARDOBJGRP_MASK_E2048 objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E2048; + + +/*! + * CLIENT_INFO for @ref BOARDOBJGRP_E8192 + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E8192 { + /*! + * Base class CLIENT_INFO + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO super; + + /*! + * Mask of valid @ref BOARDOBJ objects within the payload + */ + NV2080_CTRL_BOARDOBJGRP_MASK_E8192 objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E8192; + +/*! + * CLIENT_STATUS for @ref BOARDOBJGRP_E8192 + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E8192 { + /*! + * Base class CLIENT_STATUS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS super; + + /*! + * Mask of valid @ref BOARDOBJ objects within the payload + */ + NV2080_CTRL_BOARDOBJGRP_MASK_E8192 objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E8192; + +/*! + * CLIENT_CONTROL for @ref BOARDOBJGRP_E8192 + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E8192 { + /*! + * Base class CLIENT_CONTROL + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL super; + + /*! + * Mask of valid @ref BOARDOBJ objects within the payload + */ + NV2080_CTRL_BOARDOBJGRP_MASK_E8192 objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E8192; + +/*! + * CLIENT_READINGS for @ref BOARDOBJGRP_E8192 + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E8192 { + /*! + * Base class CLIENT_READINGS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS super; + + /*! + * Mask of valid @ref BOARDOBJ objects within the payload + */ + NV2080_CTRL_BOARDOBJGRP_MASK_E8192 objMask; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E8192; + + +/*! + * @brief Structure representing CLIENT_INFO for a BOARDOBJGRP_INTERFACE in RMCTRL. + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_INTERFACE { + /*! + * @brief Reserved for future use cases. + */ + NvU8 rsvd; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_INTERFACE; + +/*! + * @brief Structure representing CLIENT_INFO for a BOARDOBJGRP_IFACE_MODEL interface + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL { + /*! + * Super class CLIENT_INFO + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_INTERFACE super; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL; + +/*! + * @brief Structure representing CLIENT_INFO for a BOARDOBJGRP_IFACE_MODEL_20 + * interface + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL_20 { + /*! + * Super class CLIENT_INFO + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL super; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL_20; + +/*! + * @brief Structure representing CLIENT_INFO for a + * BOARDOBJGRP_IFACE_MODEL_PMU_INIT_1X interface + * + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL_PMU_INIT_1X { + /*! + * Super class CLIENT_INFO + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL_20 super; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL_PMU_INIT_1X; + +/*! + * @brief Structure representing CLIENT_STATUS for a BOARDOBJGRP_INTERFACE in RMCTRL. + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_INTERFACE { + /*! + * @brief Reserved for future use cases. + */ + NvU8 rsvd; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_INTERFACE; + +/*! + * @brief Structure representing CLIENT_STATUS for a BOARDOBJGRP_IFACE_MODEL interface + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL { + /*! + * Super class CLIENT_STATUS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_INTERFACE super; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL; + +/*! + * @brief Structure representing CLIENT_STATUS for a BOARDOBJGRP_IFACE_MODEL_20 + * interface + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL_20 { + /*! + * Super class CLIENT_STATUS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL super; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL_20; + +/*! + * @brief Structure representing CLIENT_STATUS for a + * BOARDOBJGRP_IFACE_MODEL_PMU_INIT_1X interface + * + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL_PMU_INIT_1X { + /*! + * Super class CLIENT_STATUS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL_20 super; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL_PMU_INIT_1X; + +/*! + * @brief Structure representing CLIENT_CONTROL for a BOARDOBJGRP_INTERFACE in RMCTRL. + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_INTERFACE { + /*! + * @brief Reserved for future use cases. + */ + NvU8 rsvd; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_INTERFACE; + +/*! + * @brief Structure representing CLIENT_CONTROL for a BOARDOBJGRP_IFACE_MODEL interface + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL { + /*! + * Super class CLIENT_CONTROL + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_INTERFACE super; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL; + +/*! + * @brief Structure representing CLIENT_CONTROL for a BOARDOBJGRP_IFACE_MODEL_20 + * interface + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL_20 { + /*! + * Super class CLIENT_CONTROL + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL super; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL_20; + +/*! + * @brief Structure representing CLIENT_CONTROL for a + * BOARDOBJGRP_IFACE_MODEL_PMU_INIT_1X interface + * + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL_PMU_INIT_1X { + /*! + * Super class CLIENT_CONTROL + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL_20 super; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL_PMU_INIT_1X; + +/*! + * @brief Structure representing CLIENT_READINGS for a BOARDOBJGRP_INTERFACE in RMCTRL. + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_INTERFACE { + /*! + * @brief Reserved for future use cases. + */ + NvU8 rsvd; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_INTERFACE; + +/*! + * @brief Structure representing CLIENT_READINGS for a BOARDOBJGRP_IFACE_MODEL interface + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL { + /*! + * Super class CLIENT_READINGS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_INTERFACE super; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL; + +/*! + * @brief Structure representing CLIENT_READINGS for a BOARDOBJGRP_IFACE_MODEL_20 + * interface + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL_20 { + /*! + * Super class CLIENT_READINGS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL super; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL_20; + +/*! + * @brief Structure representing CLIENT_READINGS for a + * BOARDOBJGRP_IFACE_MODEL_PMU_INIT_1X interface + * + */ +typedef struct NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL_PMU_INIT_1X { + /*! + * Super class CLIENT_READINGS + */ + NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL_20 super; +} NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL_PMU_INIT_1X; diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h new file mode 100644 index 0000000..5a11107 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080boardobjgrpclasses.finn +// + + + +#include "nvtypes.h" + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080bus.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080bus.h new file mode 100644 index 0000000..5d0b593 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080bus.h @@ -0,0 +1,1696 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080bus.finn +// + +#include "nvcfg_sdk.h" +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX bus control commands and parameters */ + +/** + * NV2080_CTRL_CMD_BUS_GET_PCI_INFO + * + * This command returns PCI bus identifier information for the specified GPU. + * + * pciDeviceId + * This parameter specifies the internal PCI device and vendor + * identifiers for the GPU. + * pciSubSystemId + * This parameter specifies the internal PCI subsystem identifier for + * the GPU. + * pciRevisionId + * This parameter specifies the internal PCI device-specific revision + * identifier for the GPU. + * pciExtDeviceId + * This parameter specifies the external PCI device identifier for + * the GPU. It contains only the 16-bit device identifier. This + * value is identical to the device identifier portion of + * pciDeviceId since non-transparent bridges are no longer supported. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_BUS_GET_PCI_INFO (0x20801801) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS { + NvU32 pciDeviceId; + NvU32 pciSubSystemId; + NvU32 pciRevisionId; + NvU32 pciExtDeviceId; +} NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS; + +/* + * NV2080_CTRL_BUS_INFO + * + * This structure represents a single 32bit bus engine value. Clients + * request a particular bus engine value by specifying a unique bus + * information index. + * + * Legal bus information index values are: + * NV2080_CTRL_BUS_INFO_INDEX_TYPE + * This index is used to request the bus type of the GPU. + * Legal return values for this index are: + * NV2080_CTRL_BUS_INFO_TYPE_PCI + * NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS + * NV2080_CTRL_BUS_INFO_TYPE_FPCI + * NV2080_CTRL_BUS_INFO_INDEX_INTLINE + * This index is used to request the interrupt line (or irq) assignment + * for the GPU. The return value is system-dependent. + * NV2080_CTRL_BUS_INFO_INDEX_CAPS + * This index is used to request the bus engine capabilities for the GPU. + * The return value is specified as a mask of capabilities. + * Legal return values for this index are: + * NV2080_CTRL_BUS_INFO_CAPS_NEED_IO_FLUSH + * NV2080_CTRL_BUS_INFO_CAPS_CHIP_INTEGRATED + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CAPS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CAPS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CAPS + * These indices are used to request PCI Express link-specific + * capabilities values. A value of zero is returned for non-PCIE GPUs. + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CTRL_STATUS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CTRL_STATUS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CTRL_STATUS + * These indices are used to request PCI Express link-specific + * control status values. A value of zero is returned for non-PCIE GPUs. + * NV2080_CTRL_BUS_INFO_INDEX_COHERENT_DMA_FLAGS + * This index is used to request coherent dma transfer flags. + * Valid coherent dma transfer flags include: + * NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA + * NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART + * NV2080_CTRL_BUS_INFO_INDEX_NONCOHERENT_DMA_FLAGS + * This index is used to request noncoherent dma transfer flags. + * Valid noncoherent dma transfer flags include: + * NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA + * NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART + * NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE + * NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE + * This index is used to request the size of the GPU GART in MBytes. + * NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_FLAGS + * This index is used to request GPU GART flags. + * Valid gart flags include: + * NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH + * This flag indicates that GPU GART clients need to do an explicit + * flush via an appropriate SetContextDma method. + * NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED + * This flag indicates that the GART address range includes both + * system and video memory. + * NV2080_CTRL_BUS_INFO_INDEX_BUS_NUMBER + * This index is used to request the PCI-based bus number of the GPU. + * Support for this index is platform-dependent. + * NV2080_CTRL_BUS_INFO_INDEX_DEVICE_NUMBER + * This index is used to request the PCI-based device number of the GPU. + * Support for this index is platform-dependent. + * NV2080_CTRL_BUS_INFO_INDEX_DOMAIN_NUMBER + * This index is used to request the PCI-based domain number of the GPU. + * Support for this index is platform-dependent. + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_ERRORS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_ERRORS + * These indices are used to request PCI Express error status. + * The current status is cleared as part of these requests. + * Valid PCI Express error status values include: + * NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR + * NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_NON_FATAL_ERROR + * NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_FATAL_ERROR + * NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_UNSUPP_REQUEST + * NV2080_CTRL_BUS_INFO_INDEX_INTERFACE_TYPE + * This index is used to request the bus interface type of the GPU. + * Legal return values for this index are: + * NV2080_CTRL_BUS_INFO_TYPE_PCI + * NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS + * NV2080_CTRL_BUS_INFO_TYPE_FPCI + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_INFO // DEPRECATED + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN_INFO // REPLACES "GEN2" variant + * This index is used to retrieve PCI Express Gen configuration support + * This index is used to retrieve PCI Express Gen2 configuration support + * for the GPU. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN1 + * The GPU is PCI Express Gen1 capable. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN2 + * The GPU is PCI Express Gen2 capable. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN3 + * The GPU is PCI Express Gen3 capable. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN4 + * The GPU is PCI Express Gen4 capable. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN5 + * The GPU is PCI Express Gen5 capable. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN1 + * The GPU is configured in PCI Express Gen1 mode. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN2 + * The GPU is configured in PCI Express Gen2 mode. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN3 + * The GPU is configured in PCI Express Gen3 mode. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN4 + * The GPU is configured in PCI Express Gen4 mode. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN5 + * The GPU is configured in PCI Express Gen5 mode. + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_AER + * This index retrieves PCI Express Advanced Error Reporting (AER) errors + * for the GPU. + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CAPS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CAPS + * This index retrieves the PCI Express link capabilities for the + * board. For example, a Quadro FX4700X2 has two GPUs and PCIe + * switch. With this board, this index returns the link + * capabilities of the PCIe switch. In a single GPU board, this + * index returns the link capabilities of the GPU. A value of + * zero is returned for non-PCIE GPUs. + * UPSTREAM_LINK_CAPS is kept for backwards compatibility. + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CTRL_STATUS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CTRL_STATUS + * This index retrieves the PCI Express link status for the board. + * For example, a Quadro FX4700X2 has two GPUs and PCIe switch. + * With this board, this index returns the link capabilities of + * the PCIe switch. In a single GPU board, this index returns the + * link status of the GPU. A value of zero is returned for + * non-PCIE GPUs. + * UPSTREAM_LINK_CTRL_STATUS is kept for backwards compatibility. + * NV2080_CTRL_BUS_INFO_INDEX_ASLM_STATUS + * This index is used to request the PCI Express ASLM settings. + * This index is only valid when NV2080_CTRL_BUS_INFO_TYPE indicates PCIE. + * A value of zero is returned for non-PCI Express bus type. + * _ASLM_STATUS_PCIE is always _PRESENT if PCI Express bus type. + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_WIDTH_SWITCH_ERROR_COUNT + * This index is used to get the ASLM switching error count. + * A value of zero will be returned if no errors occurs while + * ASLM switching + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_SWITCH_ERROR_COUNT + * This index is used to get the Gen1<-->Gen2 switching error count + * A value of zero will be returned in case speed change from Gen1 to + * Gen2 is clean or if chipset is not gen2 capable or if gen1<-->gen2 + * switching is disabled. + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_CYA_ASPM + * This index is used to get the ASPM CYA L0s\L1 enable\disable status. + * Legal return value is specified as a mask of valid and data field + * possible return values are: + * NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_NO + * NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_YES + * NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_DISABLED + * NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S + * NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L1 + * NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S_L1 + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS + * These indices are used to request detailed PCI Express error counters. + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS_CLEAR + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS_CLEAR + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED_CLEAR + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS_CLEAR + * These indices are used to clear detailed PCI Express error counters. + * NV2080_CTRL_BUS_INFO_INDEX_GPU_INTERFACE_TYPE + * This index is used to request the internal interface type of the GPU. + * Legal return values for this index are: + * NV2080_CTRL_BUS_INFO_TYPE_PCI + * NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS + * NV2080_CTRL_BUS_INFO_TYPE_FPCI + * NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE + * This index queries the type of sysmem connection to CPU + * NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE + * NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK + * NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C + * + */ + +typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_BUS_INFO; + +/* valid bus info index values */ + +/** + * This index is used to request the bus type of the GPU. + * Legal return values for this index are: + * NV2080_CTRL_BUS_INFO_TYPE_PCI + * NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS + * NV2080_CTRL_BUS_INFO_TYPE_FPCI + */ +#define NV2080_CTRL_BUS_INFO_INDEX_TYPE (0x00000000) +#define NV2080_CTRL_BUS_INFO_INDEX_INTLINE (0x00000001) +#define NV2080_CTRL_BUS_INFO_INDEX_CAPS (0x00000002) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CAPS (0x00000003) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CAPS (0x00000004) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CAPS (0x00000005) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CAPS (0x00000006) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CTRL_STATUS (0x00000007) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CTRL_STATUS (0x00000008) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CTRL_STATUS (0x00000009) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CTRL_STATUS (0x0000000A) +/** + * This index is used to request coherent dma transfer flags. + * Valid coherent dma transfer flags include: + * NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA + * NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART + */ +#define NV2080_CTRL_BUS_INFO_INDEX_COHERENT_DMA_FLAGS (0x0000000B) +/** + * This index is used to request noncoherent dma transfer flags. + * Valid noncoherent dma transfer flags include: + * NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA + * NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART + * NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE + */ +#define NV2080_CTRL_BUS_INFO_INDEX_NONCOHERENT_DMA_FLAGS (0x0000000C) +/** + * This index is used to request the size of the GPU GART in MBytes. + */ +#define NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE (0x0000000D) +/** + * This index is used to request GPU GART flags. + * Valid gart flags include: + * NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH + * This flag indicates that GPU GART clients need to do an explicit + * flush via an appropriate SetContextDma method. + * NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED + * This flag indicates that the GART address range includes both + * system and video memory. + */ +#define NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_FLAGS (0x0000000E) +#define NV2080_CTRL_BUS_INFO_INDEX_BUS_NUMBER (0x0000000F) +#define NV2080_CTRL_BUS_INFO_INDEX_DEVICE_NUMBER (0x00000010) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_ERRORS (0x00000011) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_ERRORS (0x00000012) +#define NV2080_CTRL_BUS_INFO_INDEX_INTERFACE_TYPE (0x00000013) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_INFO (0x00000014) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_AER (0x00000015) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CAPS (0x00000016) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CTRL_STATUS (0x00000017) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_ASLM_STATUS (0x00000018) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_WIDTH_SWITCH_ERROR_COUNT (0x00000019) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_SPEED_SWITCH_ERROR_COUNT (0x0000001A) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_CYA_ASPM (0x0000001B) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS (0x0000001C) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS (0x0000001D) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED (0x0000001E) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS (0x0000001F) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS_CLEAR (0x00000020) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS_CLEAR (0x00000021) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED_CLEAR (0x00000022) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS_CLEAR (0x00000023) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS (0x00000024) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS (0x00000025) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS (0x00000026) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS (0x00000027) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS_CLEAR (0x00000028) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS_CLEAR (0x00000029) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS_CLEAR (0x0000002A) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS_CLEAR (0x0000002B) +#define NV2080_CTRL_BUS_INFO_INDEX_DOMAIN_NUMBER (0x0000002C) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN_INFO (0x0000002D) +#define NV2080_CTRL_BUS_INFO_INDEX_GPU_INTERFACE_TYPE (0x0000002E) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_GEN_INFO (0x0000002F) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_GEN_INFO (0x00000030) +#define NV2080_CTRL_BUS_INFO_INDEX_MSI_INFO (0x00000031) +/** + * This index is used to request the top 32 bits of the size of the GPU + * GART in MBytes. + */ +#define NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE_HI (0x00000032) +#define NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE (0x00000033) +#define NV2080_CTRL_BUS_INFO_INDEX_MAX NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE +#define NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE (0x00000034) + +/* valid bus info type return values */ +#define NV2080_CTRL_BUS_INFO_TYPE_PCI (0x00000001) +#define NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS (0x00000003) +#define NV2080_CTRL_BUS_INFO_TYPE_FPCI (0x00000004) +#define NV2080_CTRL_BUS_INFO_TYPE_AXI (0x00000008) + +/* valid bus capability flags */ +#define NV2080_CTRL_BUS_INFO_CAPS_NEED_IO_FLUSH (0x00000001) +#define NV2080_CTRL_BUS_INFO_CAPS_CHIP_INTEGRATED (0x00000002) + +/* + * Format of PCIE link caps return values + * Note that Link Capabilities register format is followed only for bits 11:0 + */ +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED 3:0 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_2500MBPS (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_5000MBPS (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_8000MBPS (0x00000003) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_16000MBPS (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_32000MBPS (0x00000005) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_64000MBPS (0x00000006) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_WIDTH 9:4 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM 11:10 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_NONE (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S_L1 (0x00000003) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN 15:12 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN1 (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN2 (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN3 (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN4 (0x00000003) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN5 (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN6 (0x00000005) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL 19:16 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN1 (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN2 (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN3 (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN4 (0x00000003) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN5 (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN6 (0x00000005) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN 23:20 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN1 (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN2 (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN3 (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN4 (0x00000003) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN5 (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN6 (0x00000005) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES 24:24 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_ENABLED (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_DISABLED (0x00000001) + +/* format of PCIE control status return values */ +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM 1:0 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_DISABLED (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L1 (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S_L1 (0x00000003) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED 19:16 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_2500MBPS (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_5000MBPS (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_8000MBPS (0x00000003) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_16000MBPS (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_32000MBPS (0x00000005) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_64000MBPS (0x00000006) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH 25:20 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_UNDEFINED (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X1 (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X2 (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X4 (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X8 (0x00000008) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X12 (0x0000000C) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X16 (0x00000010) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X32 (0x00000020) + +/* coherent dma transfer flags */ +#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA 0:0 +#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_FALSE (0x00000000) +#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_TRUE (0x00000001) +#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART 2:2 +#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_FALSE (0x00000000) +#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_TRUE (0x00000001) + +/* noncoherent dma transfer flags */ +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA 0:0 +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_FALSE (0x00000000) +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_TRUE (0x00000001) +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART 2:2 +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_FALSE (0x00000000) +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_TRUE (0x00000001) +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE 3:3 +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_FALSE (0x00000000) +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_TRUE (0x00000001) + +/* GPU GART flags */ +#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH 0:0 +#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_FALSE (0x00000000) +#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_TRUE (0x00000001) +#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED 1:1 +#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_FALSE (0x00000000) +#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_TRUE (0x00000001) + +/* format of PCIE errors return values */ +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_NON_FATAL_ERROR (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_FATAL_ERROR (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_UNSUPP_REQUEST (0x00000008) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_ENTERED_RECOVERY (0x00000010) + +/* PCIE Gen2 capability and current level */ +#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP 0:0 +#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_FALSE (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_TRUE (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL 1:1 +#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN1 (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN2 (0x00000001) + +/* format of PCIE AER return values */ +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_TRAINING_ERR (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_DLINK_PROTO_ERR (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_POISONED_TLP (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_FC_PROTO_ERR (0x00000008) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_TIMEOUT (0x00000010) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_ABORT (0x00000020) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNEXP_CPL (0x00000040) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_RCVR_OVERFLOW (0x00000080) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_MALFORMED_TLP (0x00000100) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_ECRC_ERROR (0x00000200) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNSUPPORTED_REQ (0x00000400) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RCV_ERR (0x00010000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_TLP (0x00020000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_DLLP (0x00040000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_ROLLOVER (0x00080000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_TIMEOUT (0x00100000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_ADVISORY_NONFATAL (0x00200000) + +/* format of PCIE ASLM status return value */ +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE 0:0 +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_ERROR (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_PRESENT (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED 1:1 +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE 2:2 +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED 3:3 +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04 4:4 +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_MISSING (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_PRESENT (0x00000001) + +/* format of GPU CYA CAPS return value */ +#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID 0:0 +#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM 2:1 +#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_DISABLED (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L1 (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S_L1 (0x00000003) + +/* format of MSI INFO return value */ +#define NV2080_CTRL_BUS_INFO_MSI_STATUS 0:0 +#define NV2080_CTRL_BUS_INFO_MSI_STATUS_DISABLED (0x00000000) +#define NV2080_CTRL_BUS_INFO_MSI_STATUS_ENABLED (0x00000001) + +/*format of L1PM Substates capabilities information */ +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED 0:0 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED 1:1 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED 2:2 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED 3:3 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED 4:4 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_RESERVED 7:5 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PORT_RESTORE_TIME 15:8 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_T_POWER_ON_SCALE 17:16 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_T_POWER_ON_VALUE 23:19 + +/*format of L1 PM Substates Control 1 Register */ +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED 0:0 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED 1:1 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED 2:2 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED 3:3 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_COMMON_MODE_RESTORE_TIME 15:8 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_LTR_L1_2_THRESHOLD_VALUE 25:16 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_LTR_L1_2_THRESHOLD_SCALE 31:29 + +/*format of L1 PM Substates Control 2 Register */ +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL2_T_POWER_ON_SCALE 1:0 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL2_T_POWER_ON_VALUE 7:3 + +/* valid sysmem connection type values */ +#define NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE (0x00000000) +#define NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK (0x00000001) +#define NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C (0x00000002) + +/** + * NV2080_CTRL_CMD_BUS_GET_INFO + * + * This command returns bus engine information for the associated GPU. + * Requests to retrieve bus information use a list of one or more + * NV2080_CTRL_BUS_INFO structures. + * + * busInfoListSize + * This field specifies the number of entries on the caller's + * busInfoList. + * busInfoList + * This field specifies a pointer in the caller's address space + * to the buffer into which the bus information is to be returned. + * This buffer must be at least as big as busInfoListSize multiplied + * by the size of the NV2080_CTRL_BUS_INFO structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV2080_CTRL_CMD_BUS_GET_INFO (0x20801802) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_GET_INFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_BUS_GET_INFO_PARAMS { + NvU32 busInfoListSize; + NV_DECLARE_ALIGNED(NvP64 busInfoList, 8); +} NV2080_CTRL_BUS_GET_INFO_PARAMS; + +#define NV2080_CTRL_CMD_BUS_GET_INFO_V2 (0x20801823) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_MESSAGE_ID (0x23U) + +typedef struct NV2080_CTRL_BUS_GET_INFO_V2_PARAMS { + NvU32 busInfoListSize; + NV2080_CTRL_BUS_INFO busInfoList[NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE]; +} NV2080_CTRL_BUS_GET_INFO_V2_PARAMS; + +/* + * NV2080_CTRL_BUS_PCI_BAR_INFO + * + * This structure describes PCI bus BAR information. + * + * flags + * This field contains any flags for the associated BAR. + * barSize + * This field contains the size in megabytes of the associated BAR. + * DEPRECATED, please use barSizeBytes. + * barSizeBytes + * This field contains the size in bytes of the associated BAR. + * barOffset + * This field contains the PCI bus offset in bytes of the associated BAR. + */ +typedef struct NV2080_CTRL_BUS_PCI_BAR_INFO { + NvU32 flags; + NvU32 barSize; + NV_DECLARE_ALIGNED(NvU64 barSizeBytes, 8); + NV_DECLARE_ALIGNED(NvU64 barOffset, 8); +} NV2080_CTRL_BUS_PCI_BAR_INFO; + +/* + * NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO + * + * This command returns PCI bus BAR information. + * + * barCount + * This field returns the number of BARs for the associated subdevice. + * Legal values for this parameter will be between one to + * NV2080_CTRL_BUS_MAX_BARS. + * barInfo + * This field returns per-BAR information in the form of an array of + * NV2080_CTRL_BUS_PCI_BAR_INFO structures. Information for as many as + * NV2080_CTRL_BUS_MAX_PCI_BARS will be returned. Any unused entries will + * be initialized to zero. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO (0x20801803) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS_MESSAGE_ID" */ + +/* maximum number of BARs per subdevice */ +#define NV2080_CTRL_BUS_MAX_PCI_BARS (8) + +#define NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS { + NvU32 pciBarCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_BUS_PCI_BAR_INFO pciBarInfo[NV2080_CTRL_BUS_MAX_PCI_BARS], 8); +} NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_SET_PCIE_LINK_WIDTH + * + * This command sets PCI-E link width to the specified new value. + * + * pcieLinkWidth + * This field specifies the new PCI-E link width. + * + * failingReason + * This field specifies the reason why the change of link width fails. + * It is valid only when this routine returns NV_ERR_GENERIC. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_GENERIC + */ +#define NV2080_CTRL_CMD_BUS_SET_PCIE_LINK_WIDTH (0x20801804) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS { + NvU32 pcieLinkWidth; + NvU32 failingReason; +} NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS; + +#define NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PSTATE (0x00000001) +#define NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PCIE_CFG_ACCESS (0x00000002) +#define NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_TRAINING (0x00000004) + +/* + * NV2080_CTRL_CMD_BUS_SET_PCIE_SPEED + * + * This command Initiates a change in PCIE Bus Speed + * + * busSpeed + * This field is the target speed to train to. + * Legal values for this parameter are: + * NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS + * NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS + * NV2080_CTRL_BUS_SET_PCIE_SPEED_8000MBPS + * NV2080_CTRL_BUS_SET_PCIE_SPEED_16000MBPS + * NV2080_CTRL_BUS_SET_PCIE_SPEED_32000MBPS + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_BUS_SET_PCIE_SPEED (0x20801805) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS { + NvU32 busSpeed; +} NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS; + +#define NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS (0x00000001) +#define NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS (0x00000002) +#define NV2080_CTRL_BUS_SET_PCIE_SPEED_8000MBPS (0x00000003) +#define NV2080_CTRL_BUS_SET_PCIE_SPEED_16000MBPS (0x00000004) +#define NV2080_CTRL_BUS_SET_PCIE_SPEED_32000MBPS (0x00000005) +#define NV2080_CTRL_BUS_SET_PCIE_SPEED_64000MBPS (0x00000006) + + +/* + * NV2080_CTRL_CMD_BUS_MAP_BAR2 + * + * This command sets up BAR2 page tables for passed-in memory handle. + * This command MUST be executed before NV2080_CTRL_CMD_BUS_UNMAP_BAR2 + * or NV2080_CTRL_CMD_BUS_VERIFY_BAR2. Not supported on SLI. + * + * hMemory + * This field is a handle to physical memory. + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV2080_CTRL_CMD_BUS_MAP_BAR2 (0x20801809) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_MAP_BAR2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_MAP_BAR2_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_BUS_MAP_BAR2_PARAMS { + NvHandle hMemory; +} NV2080_CTRL_BUS_MAP_BAR2_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_UNMAP_BAR2 + * + * This command unmaps any pending BAR2 page tables created with + * NV2080_CTRL_CMD_BUS_MAP_BAR2 command. The handle passed in must + * match the handle used to map the page tables. Not supported on SLI. + * + * hMemory + * This field is a handle to physical memory. + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV2080_CTRL_CMD_BUS_UNMAP_BAR2 (0x2080180a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS { + NvHandle hMemory; +} NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_VERIFY_BAR2 + * + * This command tests BAR2 against BAR0 if there are BAR2 page tables + * set up with NV2080_CTRL_CMD_BUS_MAP_BAR2 command. The handle passed + * in must match the handle used to map the page tables. Not supported on SLI. + * + * hMemory + * This field is a handle to physical memory. + * offset + * Base offset of the surface where the test will make its first dword write. + * size + * Test will write '(size/4)*4' bytes starting at surface offset `offset'. + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV2080_CTRL_CMD_BUS_VERIFY_BAR2 (0x2080180b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS { + NvHandle hMemory; + NvU32 offset; + NvU32 size; +} NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_SERVICE_GPU_MULTIFUNC_STATE + * This command would reports the current Audio device power state or Sets new power state. + * + * command + * This parametrer specifies the target GPU multifunction state. + * NV2080_CTRL_BUS_ENABLE_GPU_MULTIFUNC_STATE Enables the multi function state + * NV2080_CTRL_BUS_DISABLE_GPU_MULTIFUNC_STATE Disables the multi function state. + * NV2080_CTRL_BUS_GET_GPU_MULTIFUNC_STATE Get the Current device power state. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + */ + +#define NV2080_CTRL_CMD_BUS_SERVICE_GPU_MULTIFUNC_STATE (0x20801812) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS { + NvU8 command; + NvU32 deviceState; +} NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS; + +#define NV2080_CTRL_BUS_ENABLE_GPU_MULTIFUNC_STATE (0x00000000) +#define NV2080_CTRL_BUS_DISABLE_GPU_MULTIFUNC_STATE (0x00000001) +#define NV2080_CTRL_BUS_GET_GPU_MULTIFUNC_STATE (0x00000002) + +/* + * NV2080_CTRL_CMD_BUS_GET_PEX_COUNTERS + * This command gets the counts for different counter types. + * + * pexCounterMask + * This parameter specifies the input mask for desired counter types. + * + * pexTotalCorrectableErrors + * This parameter gives the total correctable errors which includes + * NV_XVE_ERROR_COUNTER1 plus LCRC Errors, 8B10B Errors, NAKS and Failed L0s + * + * pexCorrectableErrors + * This parameter only includes NV_XVE_ERROR_COUNTER1 value. + * + * pexTotalNonFatalErrors + * This parameter returns total Non-Fatal Errors which may or may not + * include Correctable Errors. + * + * pexTotalFatalErrors + * This parameter returns Total Fatal Errors + * + * pexTotalUnsupportedReqs + * This parameter returns Total Unsupported Requests + * + * pexErrors + * This array contains the error counts for each error type as requested from + * the pexCounterMask. The array indexes correspond to the mask bits one-to-one. + */ + +#define NV2080_CTRL_CMD_BUS_GET_PEX_COUNTERS (0x20801813) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PEX_MAX_COUNTER_TYPES 31 +#define NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS { + NvU32 pexCounterMask; + NvU32 pexTotalCorrectableErrors; + NvU16 pexCorrectableErrors; + NvU8 pexTotalNonFatalErrors; + NvU8 pexTotalFatalErrors; + NvU8 pexTotalUnsupportedReqs; + NvU16 pexCounters[NV2080_CTRL_PEX_MAX_COUNTER_TYPES]; +} NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS; + +/* + * Note that MAX_COUNTER_TYPES will need to be updated each time + * a new counter type gets added to the list below. The value + * depends on the bits set for the last valid define. Look + * at pexCounters[] comments above for details. + * + */ +#define NV2080_CTRL_BUS_PEX_COUNTER_TYPE 0x00000000 +#define NV2080_CTRL_BUS_PEX_COUNTER_RECEIVER_ERRORS 0x00000001 +#define NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_COUNT 0x00000002 +#define NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_ROLLOVER_COUNT 0x00000004 +#define NV2080_CTRL_BUS_PEX_COUNTER_BAD_DLLP_COUNT 0x00000008 +#define NV2080_CTRL_BUS_PEX_COUNTER_BAD_TLP_COUNT 0x00000010 +#define NV2080_CTRL_BUS_PEX_COUNTER_8B10B_ERRORS_COUNT 0x00000020 +#define NV2080_CTRL_BUS_PEX_COUNTER_SYNC_HEADER_ERRORS_COUNT 0x00000040 +#define NV2080_CTRL_BUS_PEX_COUNTER_LCRC_ERRORS_COUNT 0x00000080 +#define NV2080_CTRL_BUS_PEX_COUNTER_FAILED_L0S_EXITS_COUNT 0x00000100 +#define NV2080_CTRL_BUS_PEX_COUNTER_NAKS_SENT_COUNT 0x00000200 +#define NV2080_CTRL_BUS_PEX_COUNTER_NAKS_RCVD_COUNT 0x00000400 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_ERRORS 0x00000800 +#define NV2080_CTRL_BUS_PEX_COUNTER_L1_TO_RECOVERY_COUNT 0x00001000 +#define NV2080_CTRL_BUS_PEX_COUNTER_L0_TO_RECOVERY_COUNT 0x00002000 +#define NV2080_CTRL_BUS_PEX_COUNTER_RECOVERY_COUNT 0x00004000 +#define NV2080_CTRL_BUS_PEX_COUNTER_CHIPSET_XMIT_L0S_ENTRY_COUNT 0x00008000 +#define NV2080_CTRL_BUS_PEX_COUNTER_GPU_XMIT_L0S_ENTRY_COUNT 0x00010000 +#define NV2080_CTRL_BUS_PEX_COUNTER_L1_ENTRY_COUNT 0x00020000 +#define NV2080_CTRL_BUS_PEX_COUNTER_L1P_ENTRY_COUNT 0x00040000 +#define NV2080_CTRL_BUS_PEX_COUNTER_DEEP_L1_ENTRY_COUNT 0x00080000 +#define NV2080_CTRL_BUS_PEX_COUNTER_ASLM_COUNT 0x00100000 +#define NV2080_CTRL_BUS_PEX_COUNTER_TOTAL_CORR_ERROR_COUNT 0x00200000 +#define NV2080_CTRL_BUS_PEX_COUNTER_CORR_ERROR_COUNT 0x00400000 +#define NV2080_CTRL_BUS_PEX_COUNTER_NON_FATAL_ERROR_COUNT 0x00800000 +#define NV2080_CTRL_BUS_PEX_COUNTER_FATAL_ERROR_COUNT 0x01000000 +#define NV2080_CTRL_BUS_PEX_COUNTER_UNSUPP_REQ_COUNT 0x02000000 +#define NV2080_CTRL_BUS_PEX_COUNTER_L1_1_ENTRY_COUNT 0x04000000 +#define NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ENTRY_COUNT 0x08000000 +#define NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ABORT_COUNT 0x10000000 +#define NV2080_CTRL_BUS_PEX_COUNTER_L1SS_TO_DEEP_L1_TIMEOUT_COUNT 0x20000000 +#define NV2080_CTRL_BUS_PEX_COUNTER_L1_SHORT_DURATION_COUNT 0x40000000 + +/* + * NV2080_CTRL_CMD_BUS_CLEAR_PEX_COUNTER_COUNTERS + * This command gets the counts for different counter types. + * + * pexCounterMask + * This parameter specifies the input mask for desired counters to be + * cleared. Note that all counters cannot be cleared. + */ + +#define NV2080_CTRL_CMD_BUS_CLEAR_PEX_COUNTERS (0x20801814) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS { + NvU32 pexCounterMask; +} NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_FREEZE_PEX_COUNTERS + * This command gets the counts for different counter types. + * + * pexCounterMask + * This parameter specifies the input mask for desired counters to be + * freezed. Note that all counters cannot be frozen. + * + * bFreezeRmCounter + * This parameter decides whether API will freeze it or unfreeze it. + * NV_TRUE for freeze and NV_FALSE for unfreeze. + */ + +#define NV2080_CTRL_CMD_BUS_FREEZE_PEX_COUNTERS (0x20801815) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS { + NvU32 pexCounterMask; + NvBool bFreezeRmCounter; +} NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS + * This command gets the per Lane Counters and the type of errors. + * + * pexLaneErrorStatus + * This mask specifies the type of error detected on any of the Lanes. + * + * pexLaneCounter + * This array gives the counters per Lane. Each index corresponds to Lane + * index + 1 + */ + +#define NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS (0x20801816) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PEX_MAX_LANES 16 +#define NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS { + NvU16 pexLaneErrorStatus; + NvU8 pexLaneCounter[NV2080_CTRL_PEX_MAX_LANES]; +} NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS; + +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_TYPE 0x00000000 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_CODING_ERR 0x00000001 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_ORDER_ERR 0x00000002 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_OS_DATA_SEQ_ERR 0x00000004 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_TSX_DATA_SEQ_ERR 0x00000008 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_SKPOS_LFSR_ERR 0x00000010 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_RX_CLK_FIFO_OVERFLOW 0x00000020 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_ELASTIC_FIFO_OVERFLOW 0x00000040 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LINK_NUM_ERR 0x00000080 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LANE_NUM_ERR 0x00000100 + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY (0x20801817) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID (0x17U) + +typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS { + NvBool bPexLtrRegkeyOverride; + NvBool bPexRootPortLtrSupported; + NvBool bPexGpuLtrSupported; + NvU16 pexLtrSnoopLatencyValue; + NvU8 pexLtrSnoopLatencyScale; + NvU16 pexLtrNoSnoopLatencyValue; + NvU8 pexLtrNoSnoopLatencyScale; +} NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS; + +#define NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY (0x20801818) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS { + NvU16 pexLtrSnoopLatencyValue; + NvU8 pexLtrSnoopLatencyScale; + NvU16 pexLtrNoSnoopLatencyValue; + NvU8 pexLtrNoSnoopLatencyScale; +} NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_GET_PEX_UTIL_COUNTERS + * This command gets the counts for different counter types. + * + * pexCounterMask + * This parameter specifies the input mask for desired counter types. + * + */ +#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_BYTES 0x00000001 +#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_BYTES 0x00000002 +#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0 0x00000004 +#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0 0x00000008 +#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0S 0x00000010 +#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0S 0x00000020 +#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_NON_L0_L0S 0x00000040 +#define NV2080_CTRL_PEX_UTIL_MAX_COUNTER_TYPES 7 + +#define NV2080_CTRL_CMD_BUS_GET_PEX_UTIL_COUNTERS (0x20801819) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS { + NvU32 pexCounterMask; + NvU32 pexCounters[NV2080_CTRL_PEX_UTIL_MAX_COUNTER_TYPES]; +} NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_CLEAR_PEX_UTIL_COUNTER_COUNTERS + * This command gets the counts for different counter types. + * + * pexCounterMask + * This parameter specifies the input mask for desired counters to be + * cleared. Note that all counters cannot be cleared. + * + * NOTE: EX_UTIL_COUNTER_UPSTREAM & NV2080_CTRL_BUS_PEX_UTIL_COUNTER_DOWNSTREAM + * belongs to PMU. The ctrl function will not reset nor disable/enable them. + */ +#define NV2080_CTRL_CMD_BUS_CLEAR_PEX_UTIL_COUNTERS (0x20801820) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS { + NvU32 pexCounterMask; +} NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS; + +#define NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS (0x20801824) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS_MESSAGE_ID (0x24U) + +typedef struct NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS { + NvBool bEnable; +} NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_GET_NVLINK_PEER_ID_MASK + * + * This command returns cached(SW only) NVLINK peer id mask. Currently, this control + * call is only needed inside a SR-IOV enabled guest where page table management is + * being done by the guest. Guest needs this mask to derive the peer id corresponding + * to the peer GPU. This peer id will then be programmed inside the PTEs by guest RM. + * + * nvlinkPeerIdMask[OUT] + * - The peer id mask is returned in this array. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_BUS_GET_NVLINK_PEER_ID_MASK (0x20801825) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_MAX_NUM_GPUS 32 + +#define NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_MESSAGE_ID (0x25U) + +typedef struct NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS { + NvU32 nvlinkPeerIdMask[NV2080_CTRL_BUS_MAX_NUM_GPUS]; +} NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS + * This command takes parameters eomMode, eomNblks and eomNerrs from the client + * and then sends it out to PMU. + */ +#define NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS (0x20801826) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS_MESSAGE_ID (0x26U) + +typedef struct NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS { + NvU8 eomMode; + NvU8 eomNblks; + NvU8 eomNerrs; +} NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE + * This command takes parameters UPHY register's address and lane from the client + * and then sends it out to PMU. + */ +#define NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE (0x20801827) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS_MESSAGE_ID (0x27U) + +typedef struct NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS { + NvU32 regAddress; + NvU32 laneSelectMask; + NvU16 regValue; +} NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_GET_EOM_STATUS + * + */ +#define NV2080_CTRL_CMD_BUS_GET_EOM_STATUS (0x20801828) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_MAX_NUM_LANES 32 + +#define NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS_MESSAGE_ID (0x28U) + +typedef struct NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS { + NvU8 eomMode; + NvU8 eomNblks; + NvU8 eomNerrs; + NvU8 eomBerEyeSel; + NvU8 eomPamEyeSel; + NvU32 laneMask; + NvU16 eomStatus[NV2080_CTRL_BUS_MAX_NUM_LANES]; +} NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS + * + * This command returns the PCIe requester atomics operation capabilities + * of the GPU with regards to the aspect of support the client is asking for. + * + * + * capType [IN] + * The aspect of the atomics support the client is querying atomics capability for. + * Supported types are defined under NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_*. + * + * dbdf [IN] - + * Argument used to identify the PCIe peer endpoint. Used only for the _CAPTYPE_P2P. + * Encoded as: domain (31:16), bus (15:8), device (7:3), function (2:0) + * + * atomicsCaps[OUT] + * Mask of supported PCIe requester atomic operations in the form of + * NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_* + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS (0x20801829) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID (0x29U) + +typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS { + NvU32 capType; + NvU32 dbdf; + NvU32 atomicsCaps; +} NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS; + +/* + * Defined methods to expose atomics capability. + * + * NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_SYSMEM + * Exposes the state of atomics support between GPU and Sysmem. + * NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_GPU + * Exposes the state of the GPU atomics support without taking into account PCIe topology. + * NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_P2P + * Exposes the state of atomics support between the source (this GPU) + * and peer GPU identified by the dbdf argument. + */ +#define NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_SYSMEM 0x0 +#define NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_GPU 0x1 +#define NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_P2P 0x2 + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32 0:0 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64 1:1 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32 2:2 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64 3:3 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32 4:4 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64 5:5 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128 6:6 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_NO (0x00000000) + +/* + * NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS + * + * This command returns the supported GPU atomic operations + * that map to the capable PCIe atomic operations from GPU to + * coherent SYSMEM. + * + * capType [IN] + * The aspect of the atomics support the client is querying atomics capability for. + * Supported types are defined under NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_*. + * + * dbdf [IN] - + * Argument used to identify the PCIe peer endpoint. Used only for the _CAPTYPE_P2P. + * Encoded as: domain (31:16), bus (15:8), device (7:3), function (2:0) + * + * atomicOp[OUT] + * Array of NV2080_CTRL_BUS_PCIE_GPU_ATOMICS that contains the atomic operation + * supported status and its attributes. The array can be + * indexed using one of NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_* + * + */ +#define NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS (0x2080182a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IADD 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMIN 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMAX 2 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_INC 3 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_DEC 4 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IAND 5 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IOR 6 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IXOR 7 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_EXCH 8 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_CAS 9 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FADD 10 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMIN 11 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMAX 12 + +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT 13 + +/* + * NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO + * + * Describes the support state and related attributes of a single GPU atomic op. + * + * bSupported + * Is the GPU atomic operation natively supported by the PCIe + * + * attributes + * Provides the attributes mask of the GPU atomic operation when supported + * in the form of + * NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_* + */ +typedef struct NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO { + NvBool bSupported; + NvU32 attributes; +} NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO; + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID (0x2AU) + +typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS { + NvU32 capType; + NvU32 dbdf; + NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO atomicOp[NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT]; +} NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS; + +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR 0:0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR 1:1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION 2:2 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32 3:3 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64 4:4 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128 5:5 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED 6:6 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED 7:7 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_NO 0 + +/* + * NV2080_CTRL_CMD_BUS_GET_C2C_INFO + * + * This command returns the C2C links information. + * + * bIsLinkUp[OUT] + * NV_TRUE if the C2C links are present and the links are up. + * The below remaining fields are valid only if return value is + * NV_OK and bIsLinkUp is NV_TRUE. + * bLinkInHS[OUT] + * NV_TRUE if the C2C links are in high speed mode. + * nrLinks[OUT] + * Total number of C2C links that are up. + * maxNrLinks[OUT] + * Maximum number of C2C links that are supported. + * linkMask[OUT] + * Bitmask of the C2C links present and up. + * perLinkBwMBps[OUT] + * Theoretical per link bandwidth in MBps. + * perLinkLaneWidth[OUT] + * Lane width per link. + * remoteType[OUT] + * Type of the device connected to the remote end of the C2C link. + * Valid values are : + * NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU - connected to a CPU + * NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU - connected to another GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * + * Please also review the information below for additional information on + * select fields: + * + * remoteType[OUT] + * NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU - connected to a CPU + * in either self-hosted mode or externally-hostedmode. + */ + +#define NV2080_CTRL_CMD_BUS_GET_C2C_INFO (0x2080182b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_GET_C2C_INFO_MAX_C2C_INSTANCES 2 +#define NV2080_CTRL_CMD_BUS_GET_C2C_INFO_MAX_C2C_LINKS_PER_INSTANCE 7 +#define NV2080_CTRL_CMD_BUS_GET_C2C_INFO_MAX_C2C_LINKS (0xe) /* finn: Evaluated from "NV2080_CTRL_CMD_BUS_GET_C2C_INFO_MAX_C2C_INSTANCES * NV2080_CTRL_CMD_BUS_GET_C2C_INFO_MAX_C2C_LINKS_PER_INSTANCE" */ + +#define NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID (0x2BU) + +typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS { + NvBool bIsLinkUp; + NvBool bLinkInHS; + + NvBool bEncryptionEnabled; + + + NvU32 nrLinks; + NvU32 maxNrLinks; + NvU32 linkMask; + NvU32 perLinkBwMBps; + NvU32 perLinkLaneWidth; + NvU32 remoteType; +} NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS; + +#define NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU 1 +#define NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU 2 + + + +/* + * NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS + * + * This command disables the GPU system memory access after quiescing the GPU, + * or re-enables sysmem access. + * + * bDisable + * If NV_TRUE the GPU is quiesced and system memory access is disabled . + * If NV_FALSE the GPU system memory access is re-enabled and the GPU is resumed. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS (0x2080182c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS_MESSAGE_ID (0x2CU) + +typedef struct NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS { + NvBool bDisable; +} NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO + * + * This command returns the C2C error info for a C2C links. + * + * errCnts[OUT] + * Array of structure that contains the error counts for + * number of times one of C2C fatal error interrupt has happened. + * The array size should be NV2080_CTRL_CMD_BUS_GET_C2C_INFO_MAX_C2C_LINKS. + * + * nrCrcErrIntr[OUT] + * Number of times CRC error interrupt triggered. + * nrReplayErrIntr[OUT] + * Number of times REPLAY error interrupt triggered. + * nrReplayB2bErrIntr[OUT] + * Number of times REPLAY_B2B error interrupt triggered. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO (0x2080182d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID (0x2DU) + +typedef struct NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS { + struct { + NvU32 nrCrcErrIntr; + NvU32 nrReplayErrIntr; + NvU32 nrReplayB2bErrIntr; + } errCnts[NV2080_CTRL_CMD_BUS_GET_C2C_INFO_MAX_C2C_LINKS]; +} NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING + * + * This command sets P2P mapping. + * + * connectionType[IN] + * Connection type, one of NV2080_CTRL_CMD_BUS_SET_P2P_MAPPINGS_CONNECTION + * peerId[IN] + * peerId of remote GPU from local GPU on which call is made. + * bSpaAccessOnly[IN] + * SPA access only. SPA addressing mode is supported when we support ATS. + * bUseUuid [in] + * Option only available for Guest RPCs and is not avaliable for external clients. + * Set to NV_TRUE to use remoteGpuUuid in lieu of remoteGpuId to identify target GPU. + * remoteGpuId[IN] + * GPU ID of remote GPU. + * remoteGpuUuid [in] + * Alternative to gpuId; used to identify target GPU for which caps are being queried. + * Option only available for Guest RPCs. + * If bUseUuid == NV_TRUE, gpuUuid is used in lieu of gpuId to identify target GPU. + * If bUseUuid == NV_FALSE, gpuUuid is ignored and gpuId is used by default. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING (0x2080182e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_INVALID 0 +#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_NVLINK 1 +#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE 2 +#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE_BAR1 3 +#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_C2C 4 + +#define NV2080_SET_P2P_MAPPING_UUID_LEN 16U + +#define NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_MESSAGE_ID (0x2EU) + +typedef struct NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS { + NvU32 connectionType; + NvU32 peerId; + NvBool bEgmPeer; + NvBool bSpaAccessOnly; + NvBool bUseUuid; + NvU32 remoteGpuId; + NvU8 remoteGpuUuid[NV2080_SET_P2P_MAPPING_UUID_LEN]; +} NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING + * + * This command unsets P2P mapping. + * + * connectionType[IN] + * Connection type, one of NV2080_CTRL_CMD_BUS_SET_P2P_MAPPINGS_CONNECTION + * peerId[IN] + * peerId of remote GPU from local GPU on which call is mad. + * bUseUuid [in] + * Option only available for Guest RPCs and is not avaliable for external clients. + * Set to NV_TRUE to use remoteGpuUuid in lieu of remoteGpuId to identify target GPU. + * remoteGpuId[IN] + * GPU ID of remote GPU. + * remoteGpuUuid [in] + * Alternative to gpuId; used to identify target GPU for which caps are being queried. + * Option only available for Guest RPCs. + * If bUseUuid == NV_TRUE, gpuUuid is used in lieu of gpuId to identify target GPU. + * If bUseUuid == NV_FALSE, gpuUuid is ignored and gpuId is used by default. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING (0x2080182f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_MESSAGE_ID (0x2FU) + +typedef struct NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS { + NvU32 connectionType; + NvU32 peerId; + NvBool bUseUuid; + NvU32 remoteGpuId; + NvU8 remoteGpuUuid[NV2080_SET_P2P_MAPPING_UUID_LEN]; +} NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS + * + * This command returns the PCIe completer atomics operation capabilities + * of the GPU. + * + * atomicsCaps[OUT] + * Mask of supported PCIe completer atomic operations in the form of + * NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_* + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS (0x20801830) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS_MESSAGE_ID (0x30U) + +typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS { + NvU32 atomicsCaps; +} NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS; + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32 0:0 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64 1:1 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32 2:2 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64 3:3 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32 4:4 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64 5:5 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128 6:6 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_NO (0x00000000) + +/* + * NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS + * + * This command returns C2C low power statistics. + * Units for residency and latency are in microsceconds. + * c2cStateSupportMask[OUT] + Support Mask of supplrted C2C State. CL0 will always be supported (FULL_POWER) + * cl3EntryCount[OUT] + * Count of the number of times CL3 state has been entered. + * cl3ResidentTimeUs[OUT] + * Total/Average resident time in CL3 state. + * cl3AvgEntryLatencyUs[OUT] + * Average entry latency for CL3 state. + * cl3AvgExitLatencyUs[OUT] + * Average exit latency for CL3 state. + * cl3PstateSupportMask[OUT] + Pstate Support Mask for CL3 state + * cl3IdleThresholdUs[OUT] + * Get idle threshold for CL3 state. + * cl4EntryCount[OUT] + * Count of the number of times CL4 state has been entered. + * cl4ResidentTimeUs[OUT] + * Total/Average resident time in CL4 state. + * cl4AvgEntryLatencyUs[OUT] + * Average entry latency for CL4 state. + * cl4AvgExitLatencyUs[OUT] + * Average exit latency for CL4 state. + * cl4PstateSupportMask[OUT] + Pstate Support Mask for CL4 state + * cl4IdleThresholdUs[OUT] + * Get idle threshold for CL4 state. + * localPowerState[OUT] + * Power state of the local end of the C2C link. + * Valid values are : + * NV2080_CTRL_CMD_BUS_GET_C2C_STATE_FULL_POWER - Full power state + * NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL3 - Low power state + * NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL4 - Low power state + * remotePowerState[OUT] + * Power state of the remote end of the C2C link. + * Valid values are : + * NV2080_CTRL_CMD_BUS_GET_C2C_STATE_FULL_POWER - Full power state + * NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL3 - Low power state + * NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL4 - Low power state + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * + * Please also review the information below for additional information on + * select fields: + * + * cl3EntryCount/cl4EntryCount[OUT] + * These may not represent current exact count, as low power transitions could have + * occured after reading the counter register. + */ + +#define NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS (0x20801831) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS_MESSAGE_ID (0x31U) + +typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS { + NvU32 c2cStateSupportMask; + NvBool bCl3Support; + NvU32 cl3EntryCount; + NvU32 cl3ExitCount; + NvU32 cl3ResidentTimeUs; + NvU32 cl3AvgEntryLatencyUs; + NvU32 cl3AvgExitLatencyUs; + NvU32 cl3PstateSupportMask; + NvU32 cl3DisallowReasonMask; + NvBool bCl4Support; + NvU32 cl4EntryCount; + NvU32 cl4ExitCount; + NvU32 cl4ResidentTimeUs; + NvU32 cl4AvgEntryLatencyUs; + NvU32 cl4AvgExitLatencyUs; + NvU32 cl4PstateSupportMask; + NvU32 cl4DisallowReasonMask; + NvU32 c2cLpwrStateAllowedMask; + NvU32 localPowerState; + NvU32 remotePowerState; + NvU32 cl3IdleThresholdUs; + NvU32 cl4IdleThresholdUs; +} NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS; + +#define NV2080_CTRL_CMD_BUS_GET_C2C_STATE_FULL_POWER 0x0 +#define NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL3 0x1 +#define NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL4 0x2 + +/* + * NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE + * + * This command sets the allow vote for C2C Lpwr States. + * c2cLpwrStateId[IN] + * C2C LowPower State Id : NV2080_CTRL_LPWR_C2C_STATE_ID_CLx + * bAllowed[in] + * State Allowed/disallowed flag + */ +#define NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE (0x20801832) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS_MESSAGE_ID (0x32U) + +typedef struct NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS { + NvU32 c2cLpwrStateId; + NvBool bAllowed; +} NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS; + + +/* + * NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_IDLE_THRESHOLD + * + * This command sets the idle threshold for C2C Lpwr States. + * c2cLpwrStateId[IN] + * C2C LowPower State Id : NV2080_CTRL_LPWR_C2C_STATE_ID_CLx + * idleThresholdUs[in] + * The Idle Threshold for the C2C Ctrl in Micro Seconds + */ +#define NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_IDLE_THRESHOLD (0x20801836) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_IDLE_THRESHOLD_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_IDLE_THRESHOLD_PARAMS_MESSAGE_ID (0x36U) + +typedef struct NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_IDLE_THRESHOLD_PARAMS { + NvU32 c2cLpwrStateId; + NvU32 idleThresholdUs; +} NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_IDLE_THRESHOLD_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_GET_C2C_PACKET_COUNTERS + * + * This command gets packet counter values for all C2C links. This + * is intended for testing and debug only. These values cannot be used to + * measure bandwidth. + * packetCounters[OUT] + * An array of C2C packet counters + * + */ +#define NV2080_CTRL_CMD_BUS_GET_C2C_PACKET_COUNTERS (0x20801837) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_C2C_PACKET_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_GET_C2C_PACKET_COUNTERS_PARAMS_MESSAGE_ID (0x37U) + +typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_PACKET_COUNTERS_PARAMS { + NvU32 packetCounters[NV2080_CTRL_CMD_BUS_GET_C2C_INFO_MAX_C2C_LINKS]; +} NV2080_CTRL_CMD_BUS_GET_C2C_PACKET_COUNTERS_PARAMS; + + + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080ce.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080ce.h new file mode 100644 index 0000000..d6b353e --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080ce.h @@ -0,0 +1,577 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080ce.finn +// + + + +#include "nvcfg_sdk.h" + + +/* NV20_SUBDEVICE_XX ce control commands and parameters */ + +/* + * NV2080_CTRL_CMD_CE_GET_CAPS + * + * This command returns the set of CE capabilities for the device + * in the form of an array of unsigned bytes. + * + * ceEngineType + * This parameter specifies the copy engine type + * capsTblSize + * This parameter specifies the size in bytes of the caps table per CE. + * This value should be set to NV2080_CTRL_CE_CAPS_TBL_SIZE. + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the CE caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_CE_GET_CAPS (0x20802a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CAPS_PARAMS_MESSAGE_ID" */ + +/* + * Size in bytes of CE caps table. This value should be one greater + * than the largest byte_index value below. + */ +#define NV2080_CTRL_CE_CAPS_TBL_SIZE 2 + +#define NV2080_CTRL_CE_GET_CAPS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_CE_GET_CAPS_PARAMS { + NvU32 ceEngineType; + NvU32 capsTblSize; + NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); +} NV2080_CTRL_CE_GET_CAPS_PARAMS; + +#define NV2080_CTRL_CMD_CE_GET_CAPS_V2 (0x20802a03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS { + NvU32 ceEngineType; + NvU8 capsTbl[NV2080_CTRL_CE_CAPS_TBL_SIZE]; +} NV2080_CTRL_CE_GET_CAPS_V2_PARAMS; + +/* extract cap bit setting from tbl */ +#define NV2080_CTRL_CE_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* caps format is byte_index:bit_mask */ +#define NV2080_CTRL_CE_CAPS_CE_GRCE 0:0x01 +#define NV2080_CTRL_CE_CAPS_CE_SHARED 0:0x02 +#define NV2080_CTRL_CE_CAPS_CE_SYSMEM_READ 0:0x04 +#define NV2080_CTRL_CE_CAPS_CE_SYSMEM_WRITE 0:0x08 +#define NV2080_CTRL_CE_CAPS_CE_NVLINK_P2P 0:0x10 +#define NV2080_CTRL_CE_CAPS_CE_SYSMEM 0:0x20 +#define NV2080_CTRL_CE_CAPS_CE_P2P 0:0x40 +#define NV2080_CTRL_CE_CAPS_CE_BL_SIZE_GT_64K_SUPPORTED 0:0x80 +#define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_NONPIPELINED_BL 1:0x01 +#define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL 1:0x02 +#define NV2080_CTRL_CE_CAPS_CE_CC_SECURE 1:0x04 +#define NV2080_CTRL_CE_CAPS_CE_DECOMP_SUPPORTED 1:0x08 +#define NV2080_CTRL_CE_CAPS_CE_CC_WORK_SUBMIT 1:0x10 +#define NV2080_CTRL_CE_CAPS_CE_SCRUB 1:0x40 + +/* + * NV2080_CTRL_CE_CAPS_CE_GRCE + * Set if the CE is synchronous with GR + * + * NV2080_CTRL_CE_CAPS_CE_SHARED + * Set if the CE shares physical CEs with any other CE + * + * NV2080_CTRL_CE_CAPS_CE_SYSMEM_READ + * Set if the CE can give enhanced performance for SYSMEM reads over other CEs + * + * NV2080_CTRL_CE_CAPS_CE_SYSMEM_WRITE + * Set if the CE can give enhanced performance for SYSMEM writes over other CEs + * + * NV2080_CTRL_CE_CAPS_CE_NVLINK_P2P + * Set if the CE can be used for P2P transactions using NVLINK + * Once a CE is exposed for P2P over NVLINK, it will remain available for the life of RM + * PCE2LCE mapping may change based on the number of GPUs registered in RM however + * + * NV2080_CTRL_CE_CAPS_CE_SYSMEM + * Set if the CE can be used for SYSMEM transactions + * + * NV2080_CTRL_CE_CAPS_CE_P2P + * Set if the CE can be used for P2P transactions + * + * NV2080_CTRL_CE_CAPS_CE_BL_SIZE_GT_64K_SUPPORTED + * Set if the CE supports BL copy size greater than 64K + * + * NV2080_CTRL_CE_CAPS_CE_SUPPORTS_NONPIPELINED_BL + * Set if the CE supports non-pipelined Block linear + * + * NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL + * Set if the CE supports pipelined Block Linear + * + * NV2080_CTRL_CE_CAPS_CE_CC_SECURE + * Set if the CE is capable of encryption/decryption + * + * NV2080_CTRL_CE_CAPS_CE_DECOMP_SUPPORTED + * Set if the CE is capable of handling decompression workloads; + * async copies will not be supported on the same CE + * + * NV2080_CTRL_CE_CAPS_CE_CC_WORK_SUBMIT + * Set if the CE can be used for work launch/completion in CC mode + * + * NV2080_CTRL_CE_CAPS_CE_SCRUB + * Set if the CE can be used for fast scrubbing + */ + +/* + * NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK + * + * This command returns the mapping of PCE's for the given LCE. + * The pceMask is local to the CE shim that ceEngineType belongs to. + * + * ceEngineType + * This parameter specifies the copy engine type + * pceMask + * This parameter specifies a mask of PCEs that correspond + * to the LCE specified in ceEngineType + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK (0x20802a02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS { + NvU32 ceEngineType; + NvU32 pceMask; +} NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS; + +/* + * NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG + * + * This command sets the PCE2LCE configuration + * + * pceLceConfig[NV2080_CTRL_MAX_PCES] + * This parameter specifies the PCE-LCE mapping requested + * grceLceConfig[NV2080_CTRL_MAX_GRCES] + * This parameter specifies which LCE is the GRCE sharing with + * 0xF -> Does not share with any LCE + * 0-MAX_LCE -> Shares with the given LCE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG (0x20802a04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MAX_PCES 64 +#define NV2080_CTRL_MAX_GRCES 4 + +#define NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS { + NvU32 ceEngineType; + NvU32 pceLceMap[NV2080_CTRL_MAX_PCES]; + NvU32 grceSharedLceMap[NV2080_CTRL_MAX_GRCES]; +} NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS; + +/* + * NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS + * + * This command updates the PCE-LCE mappings + * + * pceLceMap [IN] + * This parameter contains the array of PCE to LCE mappings. + * The array is indexed by the PCE index, and contains the + * LCE index that the PCE is assigned to. A unused PCE is + * tagged with NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE. + * + * grceConfig [IN] + * This parameter contains the array of GRCE configs. + * 0xF -> GRCE does not share with any LCE + * 0-MAX_LCE -> GRCE shares with the given LCE + * + * exposeCeMask [IN] + * This parameter specifies the mask of LCEs to export to the + * clients after the update. + * + * bUpdateNvlinkPceLce [IN] + * Whether PCE-LCE mappings need to be updated for nvlink topology. + * If this is NV_FALSE, RM would ignore the above values. However, + * PCE-LCE mappings will still be updated if there were any regkey + * overrides. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS (0x20802a05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS { + NvU32 pceLceMap[NV2080_CTRL_MAX_PCES]; + NvU32 grceConfig[NV2080_CTRL_MAX_GRCES]; + NvU32 exposeCeMask; + NvBool bUpdateNvlinkPceLce; +} NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS; + +#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE 0xf + +/* + * NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB + * + * This function triggers an update of the exported CE classes. CEs with + * no physical resources will not be exported. A record of these + * will be return in in the stubbedCeMask. + * + * An example if NV2080_ENGINE_TYPE_COPY4 is stubbed (1<<4) will be + * set in stubbedCeMask. + * + * This function operates on all CE shims. + */ +#define NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB (0x20802a06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS { + NvU32 stubbedCeMask; +} NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS; + +/* + * NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS + * + * Query _CE_GRCE, _CE_SHARED, _CE_SUPPORTS_PIPELINED_BL, _CE_SUPPORTS_NONPIPELINED_BL bits of CE + * capabilities. + * + */ + +#define NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS (0x20802a07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS_MESSAGE_ID (0x7U) + +typedef NV2080_CTRL_CE_GET_CAPS_V2_PARAMS NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS; + +#define NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS { + NvU32 size; +} NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS; + +#define NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE (0x20802a08) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASKS + * + * Get HSHUB and FBHUB PCE masks. + * + * [out] hshubPceMasks + * PCE mask for each HSHUB + * [out] fbhubPceMask + * FBHUB PCE mask + */ + +#define NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK (0x20802a09) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_MAX_HSHUBS 32 + +#define NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS { + NvU32 hshubPceMasks[NV2080_CTRL_CE_MAX_HSHUBS]; + NvU32 fbhubPceMask; +} NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS; + +/* + * NV2080_CTRL_CMD_CE_GET_ALL_CAPS + * + * Query caps of all CEs. + * + * [out] capsTbl + * Array of CE caps in the order of CEs. The caps bits interpretation is the same as in + * NV2080_CTRL_CMD_CE_GET_CAPS. + * [out] present + * Bit mask indicating which CEs are usable by the client and have their caps indicated in capsTbl. + * If a CE is not marked present, its caps bits should be ignored. + * If client is subscribed to a MIG instance, only the CEs present in the instance are tagged as such. + */ + +#define NV2080_CTRL_CMD_CE_GET_ALL_CAPS (0x20802a0a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MAX_CES 64 + +#define NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID (0xaU) + +typedef struct NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS { + NvU8 capsTbl[NV2080_CTRL_MAX_CES][NV2080_CTRL_CE_CAPS_TBL_SIZE]; + NV_DECLARE_ALIGNED(NvU64 present, 8); +} NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS; + +#define NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS (0x20802a0b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID (0xbU) + +typedef NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS; + +/* + * NV2080_CTRL_CMD_CE_GET_LCE_SHIM_INFO + * + * This command queries LCE shim information of a specified CE. + * The information includes the shim instance the CE belongs to. + * And the local LCE within the shim. + * + * [in] ceEngineType + * This parameter specifies the copy engine type, NV2080 define + * [out] shimInstance + * The shim instance the ceEngineType belongs to. + * [out] shimLocalLceIdx + * The local LCE index within the shim + * + */ + +#define NV2080_CTRL_CMD_CE_GET_LCE_SHIM_INFO (0x20802a0c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS_MESSAGE_ID (0xcU) + +typedef struct NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS { + NvU32 ceEngineType; + NvU32 shimInstance; + NvU32 shimLocalLceIdx; +} NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS; + +/* + * This command is identical to NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS + * but supports more than one CE shim. + * + * This command updates the PCE-LCE mappings for one CE shim. On + * GPUs with multiple CE shims, this interface must be called for + * each shim. + * + * shimInstance [IN] + * Specify which CE shim instance to operate on. + */ + +#define NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS_V2 (0x20802a0d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS_MESSAGE_ID (0xdU) + +typedef struct NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS { + NvU32 pceLceMap[NV2080_CTRL_MAX_PCES]; + NvU32 grceConfig[NV2080_CTRL_MAX_GRCES]; + NvU32 exposeCeMask; + NvBool bUpdateNvlinkPceLce; + NvU32 shimInstance; +} NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS; + +/* + * This command is identical to NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK_PARAMS + * but supports more than one CE shim. + * + * This command gets HSHUB/CEHUB and FBHUB PCE Mask. On + * GPUs with multiple CE shims, this interface must be called for + * each shim. + * + * [in] shimInstance + * Specify which CE shim instance to operate on. + */ + +#define NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK_V2 (0x20802a0e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS_MESSAGE_ID (0xeU) + +typedef struct NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS { + NvU32 connectingHubPceMasks[NV2080_CTRL_CE_MAX_HSHUBS]; + NvU32 fbhubPceMask; + NvU32 shimInstance; +} NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS; + +typedef enum NV2080_CTRL_CE_LCE_TYPE { + NV2080_CTRL_CE_LCE_TYPE_PCIE = 1, + NV2080_CTRL_CE_LCE_TYPE_DECOMP = 2, + NV2080_CTRL_CE_LCE_TYPE_SCRUB = 3, + NV2080_CTRL_CE_LCE_TYPE_NVLINK_PEER = 4, + NV2080_CTRL_CE_LCE_TYPE_C2C = 5, + NV2080_CTRL_CE_LCE_TYPE_PCIE_RD = 6, + NV2080_CTRL_CE_LCE_TYPE_PCIE_WR = 7, + NV2080_CTRL_CE_LCE_TYPE_C2C_H2D = 8, + NV2080_CTRL_CE_LCE_TYPE_C2C_D2H = 9, + NV2080_CTRL_CE_LCE_TYPE_CC_WORK_SUBMIT = 10, +} NV2080_CTRL_CE_LCE_TYPE; + +typedef enum NV2080_CTRL_CE_SHIM_PREFERENCE { + NV2080_CTRL_CE_SHIM_PREFERENCE_SAME_SHIM = 1, + NV2080_CTRL_CE_SHIM_PREFERENCE_DIFFERENT_SHIM = 2, +} NV2080_CTRL_CE_SHIM_PREFERENCE; + +/* + * NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE + * + * This command queries the PCE config required for the specified LCE type. + * + * [in] lceType + * LCE type. Should be one of NV2080_CTRL_CE_LCE_TYPE_* values. + * [in] metadataForLceType + * Metadata for LCE type. + * [out] numPces + * Number of PCEs supported per LCE + * [out] numLces + * Maximum number of LCEs supported by the chip for the specified LCE type. + * [out] supportedPceMask + * The mask of the PCEs that support the specified LCE type. + * [out] supportedLceMask + * The mask of the LCEs that support the specified LCE type. + * [out] pcePerHshub + * Numbers of PCEs from any given HSHUB that can be assigned to this LCE type. + * [out] multipleLceShimPreference + * Shim selection preference in case there are multiple LCEs + * + * @return NV_OK + */ + +#define NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE (0x20802a0f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS_MESSAGE_ID (0xfU) + +typedef struct NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS { + NV2080_CTRL_CE_LCE_TYPE lceType; + NvU32 metadataForLceType; + NvU32 numPces; + NvU32 numLces; + NvU32 supportedPceMask; + NvU32 supportedLceMask; + NvU32 pcePerHshub; + NV2080_CTRL_CE_SHIM_PREFERENCE multipleLceShimPreference; +} NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS; + +/* + * NV2080_CTRL_CMD_CE_GET_DECOMP_LCE_MASK + * + * This command gets the mask of LCEs that are enabled for decomp workloads. + * On GPUs with multiple CE shims, this interface must be called for + * each shim. + * + * [in] shimInstance + * Specify which CE shim instance to operate on. + * [out] decompLceMask + * Returns a 64-bit mask of which LCEs in given shim are marked as decomp CEs + */ + +#define NV2080_CTRL_CMD_CE_GET_DECOMP_LCE_MASK (0x20802a11) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS { + NV_DECLARE_ALIGNED(NvU64 decompLceMask, 8); + NvU32 shimInstance; +} NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS; + +/* + * NV2080_CTRL_CMD_CE_IS_DECOMP_LCE_ENABLED + * + * This command returns whether a given global LCE index is enabled for decomp workloads. + * It has to be given a global LCE index (cannot support shim local LCE ID) + * + * [in] lceIndex + * [out] bDecompEnabled + * Returns NV_TRUE if LCE is enabled for decompression, else returns NV_FALSE + */ + +#define NV2080_CTRL_CMD_CE_IS_DECOMP_LCE_ENABLED (0x20802a12) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS { + NvU32 lceIndex; + NvBool bDecompEnabled; +} NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_MIG_GPU_INSTANCE + * + * This command queries the PCE config required for the specified MIG GPU Instance. + * Mappings will prioritize utilizing 1 LCE each for sysmem read and write if available + * and ensure maximum number of PCEs are allocated for those LCEs to allow maximum bandwidth. + * + * [in] lceMask + * Mask of LCEs which are being requested + * [in] numLCEs + * Number of LCEs available for this GPU Instance + * [out] pceAvailableMask + * Mask of PCEs which are available for this specific LCE mask given + * [out] numLcesToMap + * Number of LCEs to map based on total num LCEs given + * [out] lceAvailableMask + * Mask of LCEs which should be mapped for this GPU Instance based on num LCEs given + * [out] numMinPcesPerLce + * Number of PCEs to be mapped for each LCE + */ + +#define NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_MIG_GPU_INSTANCE (0x20802a13) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_MIG_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_MIG_GPU_INSTANCE_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_MIG_GPU_INSTANCE_PARAMS { + NvU32 lceMask; + NvU32 numLces; + NvU32 pceAvailableMask; + NvU32 numLcesToMap; + NvU32 lceAvailableMask; + NvU32 numMinPcesPerLce; +} NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_MIG_GPU_INSTANCE_PARAMS; + +/* + * NV2080_CTRL_CE_UPDATE_PCE_LCE_MIG_MAPPINGS + * + * Apply CE Mappings for MIG GPU Instance + * + * [in] pceLceMap + * Array of mappings indexed by PCE + * [in] lceAvailableMask + * Mask of LCEs available to this MIG GPU Instance + */ + +#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MIG_MAPPINGS (0x20802a14) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_PCE_LCE_MIG_MAPPINGS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MIG_MAPPINGS_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV2080_CTRL_CE_UPDATE_PCE_LCE_MIG_MAPPINGS_PARAMS { + NvU32 pceLceMap[NV2080_CTRL_MAX_PCES]; + NvU32 lceAvailableMask; + NvU32 shimInstance; +} NV2080_CTRL_CE_UPDATE_PCE_LCE_MIG_MAPPINGS_PARAMS; + +/* _ctrl2080ce_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080cipher.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080cipher.h new file mode 100644 index 0000000..b46acf7 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080cipher.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080cipher.finn +// + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080clk.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080clk.h new file mode 100644 index 0000000..deecc8e --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080clk.h @@ -0,0 +1,128 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080clk.finn +// + +#include "nvfixedtypes.h" +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "ctrl/ctrl2080/ctrl2080boardobj.h" +#include "ctrl/ctrl2080/ctrl2080gpumon.h" +#include "ctrl/ctrl2080/ctrl2080clkavfs.h" +#include "ctrl/ctrl2080/ctrl2080volt.h" +#include "ctrl/ctrl2080/ctrl2080pmumon.h" + +#define NV2080_CTRL_CLK_DOMAIN_TEGRA_UNDEFINED (0x00000000U) +#define NV2080_CTRL_CLK_DOMAIN_TEGRA_GPCCLK (0x00000001U) +#define NV2080_CTRL_CLK_DOMAIN_TEGRA_NVDCLK (0x00000002U) + + + +/*! + * NV2080_CTRL_CMD_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES + * + * Control call to query the samples within the PWR_CHANNELS PMUMON queue. + */ +#define NV2080_CTRL_CMD_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES (0x20801037) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CLK_INTERFACE_ID << 8) | NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES_PARAMS_MESSAGE_ID" */ + +/*! + * @brief With sample period being potentially as fast every 20ms, this gives + * us 5 seconds worth of data. + */ +#define NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE_COUNT (250U) + +/*! + * Temporary until an INFO control call is stubbed out that exposes the supported + * feature set of the sampling. + */ +#define NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE_INVALID (NV_U32_MAX) + +/*! + * A single sample of the power channels at a particular point in time. + */ +typedef struct NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE { + /*! + * Ptimer timestamp of when this data was collected. + */ + NV_DECLARE_ALIGNED(NV2080_CTRL_PMUMON_SAMPLE super, 8); + + /*! + * Point sampled programmed GPCCLK frequency in KHz. + * + * NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE_INVALID if not supported. + */ + NvU32 gpcClkFreqKHz; + + /*! + * Point sampled programmed DRAMCLK frequency in KHz. + * + * NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE_INVALID if not supported. + */ + NvU32 dramClkFreqKHz; + + /*! + * Point sampled programmed NVDCLK frequency in KHz. + * + * NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE_INVALID if not supported. + */ + NvU32 nvdClkFreqKHz; + + /*! + * Point sampled programmed active GPCCLK frequency in KHz. + * + * NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE_INVALID if not supported. + */ + NvU32 activeGpcClkFreqKHz; +} NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE; +typedef struct NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE *PNV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE; + +/*! + * Input/Output parameters for @ref NV2080_CTRL_CMD_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES + */ +#define NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES_PARAMS_MESSAGE_ID (0x37U) + +typedef struct NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES_PARAMS { + /*! + * [in/out] Meta-data for the samples[] below. Will be modified by the + * control call on caller's behalf and should be passed back in + * un-modified for subsequent calls. + */ + NV2080_CTRL_PMUMON_GET_SAMPLES_SUPER super; + + /*! + * [out] Between the last call and current call, samples[0...super.numSamples-1] + * have been published to the pmumon queue. Samples are copied into + * this buffer in chronological order. Indexes within this buffer do + * not represent indexes of samples in the actual PMUMON queue. + */ + NV_DECLARE_ALIGNED(NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE samples[NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE_COUNT], 8); +} NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES_PARAMS; +typedef struct NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES_PARAMS *PNV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES_PARAMS; + +/* _ctrl2080clk_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080clkavfs.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080clkavfs.h new file mode 100644 index 0000000..2d339fa --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080clkavfs.h @@ -0,0 +1,36 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080clkavfs.finn +// + + + +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "ctrl/ctrl2080/ctrl2080boardobj.h" +#include "ctrl/ctrl2080/ctrl2080volt.h" + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080dma.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080dma.h new file mode 100644 index 0000000..4a380d1 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080dma.h @@ -0,0 +1,180 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080dma.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX dma control commands and parameters */ + +/* + * NV2080_CTRL_CMD_DMA_INVALIDATE_TLB + * + * This command invalidates the GPU TLB. This is intended to be used + * by RM clients that manage their own TLB consistency when updating + * page tables on their own, or with DEFER_TLB_INVALIDATION options + * to other RM APIs. + * + * hVASpace + * This parameter specifies the VASpace object whose MMU TLB entries needs to be invalidated. + * Specifying a GMMU VASpace object handle will invalidate the GMMU TLB for the particular VASpace. + * Specifying a SMMU VASpace object handle will flush the entire SMMU TLB & PTC. + * + * This call can be used with the NV50_DEFERRED_API_CLASS (class 0x5080). + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_TIMEOUT_RETRY + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_DMA_INVALIDATE_TLB (0x20802502) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMA_INTERFACE_ID << 8) | NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS { + NvHandle hClient; // Deprecated. Kept here for compactibility with chips_GB9-2-1-1 + NvHandle hDevice; // Deprecated. Kept here for compactibility with chips_GB9-2-1-1 + NvU32 engine; // Deprecated. Kept here for compactibility with chips_GB9-2-1-1 + NvHandle hVASpace; +} NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS; + +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS 0:0 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO 1:1 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY 2:2 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE 3:3 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB 4:4 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV 5:5 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG 6:6 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD 7:7 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION 8:8 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON 9:9 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS 10:10 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR 11:11 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_TRUE (0x00000001) + +/* + * NV2080_CTRL_DMA_INFO + * + * This structure represents a single 32bit dma engine value. Clients + * request a particular DMA engine value by specifying a unique dma + * information index. + * + * Legal dma information index values are: + * NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE + * This index can be used to request the system address size in bits. + */ +typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_DMA_INFO; + +/* valid dma info index values */ +#define NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE (0x000000000) + +/* set INDEX_MAX to greatest possible index value */ +#define NV2080_CTRL_DMA_INFO_INDEX_MAX NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE + +/* + * NV2080_CTRL_CMD_DMA_GET_INFO + * + * This command returns dma engine information for the associated GPU. + * Requests to retrieve dma information use an array of one or more + * NV2080_CTRL_DMA_INFO structures. + * + * dmaInfoTblSize + * This field specifies the number of valid entries in the dmaInfoList + * array. This value cannot exceed NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES. + * dmaInfoTbl + * This parameter contains the client's dma info table into + * which the dma info values will be transferred by the RM. + * The dma info table is an array of NV2080_CTRL_DMA_INFO structures. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_DMA_GET_INFO (0x20802503) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMA_INTERFACE_ID << 8) | NV2080_CTRL_DMA_GET_INFO_PARAMS_MESSAGE_ID" */ + +/* maximum number of NV2080_CTRL_DMA_INFO entries per request */ +#define NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES (256) + +#define NV2080_CTRL_DMA_GET_INFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_DMA_GET_INFO_PARAMS { + NvU32 dmaInfoTblSize; + /* + * C form: + * NV2080_CTRL_DMA_INFO dmaInfoTbl[NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES]; + */ + NV2080_CTRL_DMA_INFO dmaInfoTbl[NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES]; +} NV2080_CTRL_DMA_GET_INFO_PARAMS; + +typedef struct NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO { + /*! + * 64KB aligned address of source 64KB tile for comptag reswizzle. + */ + NvU32 srcAddr; + + /*! + * 64KB aligned address of destination 64KB tile for comptag reswizzle. + */ + NvU32 dstAddr; + + /*! + * Comptag index assigned to the 64K sized tile relative to + * the compcacheline. Absolute comptag index would be: + * startComptagIndex + relComptagIndex. + */ + NvU16 relComptagIndex; +} NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO; + +// _ctrl2080dma_h_ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080dmabuf.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080dmabuf.h new file mode 100644 index 0000000..34fa680 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080dmabuf.h @@ -0,0 +1,127 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080dmabuf.finn +// + + + +/* + * NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD + * + * Exports RM vidmem and sysmem handles to a dma-buf fd. + * + * The objects in the 'handles' array are exported to the fd as range: + * [index, index + numObjects). + * + * A dma-buf fd is created the first time this control call is called. + * The fd is an input parameter for subsequent calls to attach additional handles + * over NV2080_CTRL_DMABUF_MAX_HANDLES. + * + * fd + * A dma-buf file descriptor. If -1, a new FD will be created. + * + * totalObjects + * The total number of objects that the client wishes to export to the FD. + * This parameter will be honored only when the FD is getting created. + * + * numObjects + * The number of handles the user wishes to export in this call. + * + * index + * The index into the export fd at which to start exporting the handles in + * 'handles'. This index cannot overlap a previously used index. + * + * totalSize + * The total size of memory being exported in bytes, needed to create the dma-buf. + * This size includes the memory that will be exported in future export calls + * for this dma-buf. + * + * mappingType + * The type of mapping that must be used for this dma-buf. + * See NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_* for all possible values. + * + * With type DEFAULT, the driver shall decide the type based on platform coherency: + * C2C for coherent + * PCIe BAR1 for non-coherent + * Type FORCE_PCIE field is a workaround for platforms with Grace (PCIe Gen4/Gen5 RPs) paired with + * Gen6 parts like Blackwell GPUs and CX8 NICs, requiring a separate Gen6 PCIe link to maximize RDMA + * bandwidth. This type allows dma-buf to be mapped over this Gen6 PCIe link. + * + * This call shall return NV_ERR_NOT_SUPPORTED if FORCE_PCIE type is used on non-Grace platforms. + * + * bAllowMmap + * mmap support is allowed or not for the specific dmabuf based fd. User can control it. + * That way user can enable mmap for testing/specific use cases and not for any all handles. + * + * handles + * An array of {handle, offset, size} that describes the dma-buf. + * The offsets and sizes must be OS page-size aligned. + * + * Limitations: + * 1. This call supports vidmem and sysmem objects. + * 2. All memory handles should belong to the same GPU or the same GPU MIG instance. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_NO_MEMORY + * NV_ERR_OPERATING_SYSTEM + * NV_ERR_IN_USE + * NV_ERR_INVALID_OBJECT + * NV_ERR_INVALID_OBJECT_PARENT + */ +#define NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD (0x20803a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMABUF_INTERFACE_ID << 8) | NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_DMABUF_MAX_HANDLES 128 + +#define NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT (0x00000000U) +#define NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE (0x00000001U) + +typedef struct NV2080_CTRL_DMABUF_MEM_HANDLE_INFO { + NvHandle hMemory; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); +} NV2080_CTRL_DMABUF_MEM_HANDLE_INFO; + +#define NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS { + NvS32 fd; + NvU32 totalObjects; + NvU32 numObjects; + NvU32 index; + NV_DECLARE_ALIGNED(NvU64 totalSize, 8); + NvU8 mappingType; + NvBool bAllowMmap; + NV_DECLARE_ALIGNED(NV2080_CTRL_DMABUF_MEM_HANDLE_INFO handles[NV2080_CTRL_DMABUF_MAX_HANDLES], 8); +} NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS; + +// _ctrl2080dmabuf_h_ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080ecc.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080ecc.h new file mode 100644 index 0000000..85b3599 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080ecc.h @@ -0,0 +1,256 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080ecc.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + + + +#define NV2080_CTRL_CMD_ECC_GET_CLIENT_EXPOSED_COUNTERS (0x20803400U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS + * + * sramParityUncorrectedUnique [out] + * sramSecDedUncorrectedUnique [out] + * sramCorrectedUnique [out] + * dramUncorrectedTotal [out] + * dramCorrectedTotal [out] + * Aggregate error counts for SRAM and DRAM. + * + * lastClearedTimestamp [out] + * unix-epoch based timestamp. These fields indicate when the error counters + * were last cleared by the user. + * + * sramBucketL2 [out] + * sramBucketSM [out] + * sramBucketPcie [out] + * sramBucketFirmware [out] + * sramBucketOther [out] + * Aggregate unique uncorrctable error counts for SRAM buckets. + * + * sramErrorThresholdExceeded [out] + * Boolean flag which is set if SRAM error threshold was exceeded + */ + +#define NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID (0x0U) + +typedef struct NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 sramParityUncorrectedUnique, 8); + NV_DECLARE_ALIGNED(NvU64 sramSecDedUncorrectedUnique, 8); + NV_DECLARE_ALIGNED(NvU64 sramCorrectedUnique, 8); + NV_DECLARE_ALIGNED(NvU64 dramUncorrectedTotal, 8); + NV_DECLARE_ALIGNED(NvU64 dramCorrectedTotal, 8); + + NvU32 lastClearedTimestamp; + + NV_DECLARE_ALIGNED(NvU64 sramBucketL2, 8); + NV_DECLARE_ALIGNED(NvU64 sramBucketSM, 8); + NV_DECLARE_ALIGNED(NvU64 sramBucketPcie, 8); + NV_DECLARE_ALIGNED(NvU64 sramBucketFirmware, 8); + NV_DECLARE_ALIGNED(NvU64 sramBucketOther, 8); + + NvBool sramErrorThresholdExceeded; +} NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS; + +/* + * NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS + * + * Reports count of volatile errors + * + * sramCorUni [out]: + * Unique correctable SRAM error count + * sramUncParityUni [out]: + * Unique uncorrectable SRAM parity error count + * sramUncSecDedUni [out]: + * Unique uncorrectable SRAM SEC-DED error count + * dramCorTot [out]: + * Total correctable DRAM error count + * dramUncTot [out]: + * total uncorrectable DRAM error count + */ +#define NV2080_CTRL_CMD_ECC_GET_VOLATILE_COUNTS (0x20803401U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 sramCorUni, 8); + NV_DECLARE_ALIGNED(NvU64 sramUncParityUni, 8); + NV_DECLARE_ALIGNED(NvU64 sramUncSecDedUni, 8); + NV_DECLARE_ALIGNED(NvU64 dramCorTot, 8); + NV_DECLARE_ALIGNED(NvU64 dramUncTot, 8); +} NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS; + +typedef struct eccLocation { + NvU32 location; + NvU32 sublocation; + NvU32 extlocation; +} eccLocation; + +/* + * NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_ENTRY + * + * unit + * The unit the error occurred in + * location + * The location info for the error + * address + * The address of the error + * bIsParity + * True if error is parity error, false if error is SEC-DED error + * count + * The number of uncorrectable unique error counts that occurred + */ + +typedef struct NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_ENTRY { + NvU32 unit; + eccLocation location; + NvU32 address; + NvBool bIsParity; + NvU32 count; +} NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_ENTRY; + +/* + * NV2080_CTRL_CMD_ECC_GET_SRAM_UNIQUE_UNCORR_COUNTS + * + * This command is used to query the ECC inforom object and determine the number + * of unique uncorrectable error counts that occurred at an address. + * + * entryCount + * The number of entries + * + * entries + * The array of NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_ENTRY + */ + +#define NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_MAX_COUNT 600 + +#define NV2080_CTRL_CMD_ECC_GET_SRAM_UNIQUE_UNCORR_COUNTS (0x20803402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_SRAM_UNIQUE_UNCORR_COUNTS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_ECC_GET_SRAM_UNIQUE_UNCORR_COUNTS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_ECC_GET_SRAM_UNIQUE_UNCORR_COUNTS_PARAMS { + NvU32 entryCount; + NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_ENTRY entries[NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_MAX_COUNT]; +} NV2080_CTRL_ECC_GET_SRAM_UNIQUE_UNCORR_COUNTS_PARAMS; + +#define NV2080_CTRL_ECC_ERROR_TYPE_CORRECTED 0 +#define NV2080_CTRL_ECC_ERROR_TYPE_UNCORRECTED 1 + + + +/* + * NV2080_CTRL_CMD_ECC_INJECT_ERROR + * + * This command is used to inject ECC errors. + * + * unit + * The ECC unit + * + * errorType + * The type of error to be injected + * + * location + * The location within the ECC unit to be injected + * + * flags + * Specific injection flags + * + * address + * Specific injection address for DRAM + */ +#define NV2080_CTRL_CMD_ECC_INJECT_ERROR (0x20803403) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_ECC_INJECT_ERROR_PARAMS { + NvU32 unit; + NvU8 errorType; + eccLocation location; + NvU32 flags; + NV_DECLARE_ALIGNED(NvU64 address, 8); +} NV2080_CTRL_ECC_INJECT_ERROR_PARAMS; + +/* + * NV2080_CTRL_CMD_ECC_GET_REPAIR_STATUS + * + * This command is used to query the status of TPC/Channel repair + * + * bTpcRepairPending + * Boolean indicating if TPC repair is pending + * bChannelRepairPending + * Boolean indicating if Channel repair is pending + */ + +#define NV2080_CTRL_CMD_ECC_GET_REPAIR_STATUS (0x20803404) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_REPAIR_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_ECC_GET_REPAIR_STATUS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_ECC_GET_REPAIR_STATUS_PARAMS { + NvBool bTpcRepairPending; + NvBool bChannelRepairPending; +} NV2080_CTRL_ECC_GET_REPAIR_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_ECC_INJECTION_SUPPORTED + * + * Determines if error injection is supported for a given HW unit + * + * unit [in]: + * The ECC protected unit for which ECC injection support is being checked + * + * bCorrectableSupported [out]: + * Boolean value that shows if correcatable errors can be injected + * + * bUncorrectableSupported [out]: + * Boolean value that shows if uncorrecatable errors can be injected +*/ + +#define NV2080_CTRL_CMD_ECC_INJECTION_SUPPORTED (0x20803405) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV2080_CTRL_ECC_INJECTION_SUPPORTED_PARAMS { + NvU32 unit; + eccLocation location; + NvBool bCorrectableSupported; + NvBool bUncorrectableSupported; +} NV2080_CTRL_ECC_INJECTION_SUPPORTED_PARAMS; + +#define NV2080_CTRL_CMD_ECC_GET_UNREPAIRABLE_MEMORY_FLAG (0x20803406) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_UNREPAIRABLE_MEMORY_FLAG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_ECC_GET_UNREPAIRABLE_MEMORY_FLAG_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_ECC_GET_UNREPAIRABLE_MEMORY_FLAG_PARAMS { + NvBool bUnrepairableMemory; +} NV2080_CTRL_ECC_GET_UNREPAIRABLE_MEMORY_FLAG_PARAMS; + +/* _ctrl2080ecc_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080event.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080event.h new file mode 100644 index 0000000..a496ce2 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080event.h @@ -0,0 +1,396 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080event.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +#include "nv_vgpu_types.h" +/* NV20_SUBDEVICE_XX event-related control commands and parameters */ + +/* + * NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * This command sets event notification state for the associated subdevice. + * This command requires that an instance of NV01_EVENT has been previously + * bound to the associated subdevice object. + * + * event + * This parameter specifies the type of event to which the specified + * action is to be applied. This parameter must specify a valid + * NV2080_NOTIFIERS value (see cl2080.h for more details) and should + * not exceed one less NV2080_NOTIFIERS_MAXCOUNT. + * action + * This parameter specifies the desired event notification action. + * Valid notification actions include: + * NV2080_CTRL_SET_EVENT_NOTIFICATION_DISABLE + * This action disables event notification for the specified + * event for the associated subdevice object. + * NV2080_CTRL_SET_EVENT_NOTIFICATION_SINGLE + * This action enables single-shot event notification for the + * specified event for the associated subdevice object. + * NV2080_CTRL_SET_EVENT_NOTIFICATION_REPEAT + * This action enables repeated event notification for the specified + * event for the associated system controller object. + * bNotifyState + * This boolean is used to indicate the current state of the notifier + * at the time of event registration. This is optional and its semantics + * needs to be agreed upon by the notifier and client using the notifier + * info32 + * This is used to send 32-bit initial state info with the notifier at + * time of event registration + * info16 + * This is used to send 16-bit initial state info with the notifier at + * time of event registration + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION (0x20800301) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS { + NvU32 event; + NvU32 action; + NvBool bNotifyState; + NvU32 info32; + NvU16 info16; +} NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001) +#define NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002) + +/* XUSB/PPC D-state defines */ +#define NV2080_EVENT_DSTATE_XUSB_D0 (0x00000000) +#define NV2080_EVENT_DSTATE_XUSB_D3 (0x00000003) +#define NV2080_EVENT_DSTATE_XUSB_INVALID (0xFFFFFFFF) +#define NV2080_EVENT_DSTATE_PPC_D0 (0x00000000) +#define NV2080_EVENT_DSTATE_PPC_D3 (0x00000003) +#define NV2080_EVENT_DSTATE_PPC_INVALID (0xFFFFFFFF) + +// HDACODEC Decice DState, D3_COLD is only for verbose mapping, it cannot be logged +typedef enum NV2080_EVENT_HDACODEC_DSTATE { + NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D0 = 0, + NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D1 = 1, + NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D2 = 2, + NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_HOT = 3, + NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_COLD = 4, + NV2080_EVENT_HDACODEC_DEVICE_DSTATE_DSTATE_MAX = 5, +} NV2080_EVENT_HDACODEC_DSTATE; + +/* + * NV2080_CTRL_CMD_EVENT_SET_TRIGGER + * + * This command triggers a software event for the associated subdevice. + * This command accepts no parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_EVENT_SET_TRIGGER (0x20800302) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | 0x2" */ + +/* + * NV2080_CTRL_CMD_EVENT_SET_NOTIFIER_MEMORY + * + * hMemory + * This parameter specifies the handle of the memory object + * that identifies the memory address translation for this + * subdevice instance's notification(s). The beginning of the + * translation points to an array of notification data structures. + * The size of the translation must be at least large enough to hold the + * maximum number of notification data structures identified by + * the NV2080_MAX_NOTIFIERS value. + * Legal argument values must be instances of the following classes: + * NV01_NULL + * NV04_MEMORY + * When hMemory specifies the NV01_NULL_OBJECT value then any existing + * memory translation connection is cleared. There must not be any + * pending notifications when this command is issued. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES (0x20800303) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS { + NvHandle hMemory; +} NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS; + +#define NV2080_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED 0 +#define NV2080_EVENT_MEMORY_NOTIFIES_STATUS_PENDING 1 +#define NV2080_EVENT_MEMORY_NOTIFIES_STATUS_ERROR 2 + +/* + * NV2080_CTRL_CMD_EVENT_SET_SEMAPHORE_MEMORY + * + * hSemMemory + * This parameter specifies the handle of the memory object that + * identifies the semaphore memory associated with this subdevice + * event notification. Once this is set RM will generate an event + * only when there is a change in the semaphore value. It is + * expected that the semaphore memory value will be updated by + * the GPU indicating that there is an event pending. This + * command is used by VGX plugin to determine which virtual + * machine has generated a particular event. + * + * semOffset + * This parameter indicates the memory offset of the semaphore. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_EVENT_SET_SEMAPHORE_MEMORY (0x20800304) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS { + NvHandle hSemMemory; + NvU32 semOffset; +} NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS; + +/* + * NV2080_CTRL_CMD_EVENT_SET_GUEST_MSI + * + * hSemMemory + * This parameter specifies the handle of the memory object that + * identifies the semaphore memory associated with this subdevice + * event notification. Once this is set RM will generate an event + * only when there is a change in the semaphore value. It is + * expected that the semaphore memory value will be updated by + * the GPU indicating that there is an event pending. This + * command is used by VGX plugin to determine which virtual + * machine has generated a particular event. + * + * guestMSIAddr + * This parameter indicates the guest allocated MSI address. + * + * guestMSIData + * This parameter indicates the MSI data set by the guest OS. + * + * vgpuUuid + * This parameter specifies the uuid of vGPU assigned to VM. + * + * domainId + * This parameter specifies the unique guest virtual machine identifier + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_EVENT_SET_GUEST_MSI (0x20800305) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS { + NV_DECLARE_ALIGNED(NvU64 guestMSIAddr, 8); + NvU32 guestMSIData; + NvHandle hSemMemory; + NvBool isReset; + NvU8 vgpuUuid[VM_UUID_SIZE]; + NV_DECLARE_ALIGNED(NvU64 domainId, 8); +} NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS; + + +/* + * NV2080_CTRL_CMD_EVENT_SET_SEMA_MEM_VALIDATION + * + * hSemMemory + * This parameter specifies the handle of the memory object that + * identifies the semaphore memory associated with this subdevice + * event notification. Once this is set RM will generate an event + * only when there is a change in the semaphore value. It is + * expected that the semaphore memory value will be updated by + * the GPU indicating that there is an event pending. This + * command is used by VGX plugin to determine which virtual + * machine has generated a particular event. + * + * isSemaMemValidationEnabled + * This parameter used to enable/disable change in sema value check + * while generating an event. + * + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + * NVOS_STATUS_ERROR_INVALID_OBJECT_HANDLE + * NVOS_STATUS_ERROR_INVALID_ARGUMENT + */ + + +#define NV2080_CTRL_CMD_EVENT_SET_SEMA_MEM_VALIDATION (0x20800306) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS { + NvHandle hSemMemory; + NvBool isSemaMemValidationEnabled; +} NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS; + + +/* + * NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO + * + * This command triggers a FIFO event for the associated subdevice. + * + * hEvent + * Handle of the event that should be notified. If zero, all + * non-stall interrupt events for this subdevice will be notified. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO (0x20800308) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS { + NvHandle hEvent; +} NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS; + +/* + * NV2080_CTRL_CMD_EVENT_VIDEO_BIND_EVTBUF_FOR_UID + * + * This command is used to create a video bind-point to an event buffer that + * is filtered by UID. + * + * hEventBuffer[IN] + * The event buffer to bind to + * + * recordSize[IN] + * The size of the FECS record in bytes + * + * levelOfDetail[IN] + * One of NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_: + * FULL: Report all CtxSw events + * SIMPLE: Report engine start and engine end events only + * CUSTOM: Report events in the eventFilter field + * NOTE: RM may override the level-of-detail depending on the caller + * + * eventFilter[IN] + * Bitmask of events to report if levelOfDetail is CUSTOM + * + * bAllUsers[IN] + * Only report video data for the current user if false, for all users if true + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_EVENT_VIDEO_BIND_EVTBUF (0x20800309) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD { + NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_FULL = 0, + NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_SIMPLE = 1, + NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_CUSTOM = 2, +} NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD; + +#define NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS { + NvHandle hEventBuffer; + NvU32 recordSize; + NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD levelOfDetail; + NvU32 eventFilter; + NvBool bAllUsers; +} NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS; + + +/* + * NV2080_CTRL_CMD_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_FOR_UID + * + * This command is used to create a RATS tracing bindpoint to eventbuffer. + * + * hEventBuffer[IN] + * The event buffer to bind to + * + * tracepointMask[IN] + * Bitmask for selecting tracepoints + * + * gspLoggingBufferSize[IN] + * User defined size of GSP owned event logging buffer + * + * gspLoggingBufferWatermark[IN] + * User defined watermark that triggers RPC to kernel of traces + * HINT: set higher for more frequent trace updates + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_EVENT_RATS_GSP_TRACE_BIND_EVTBUF (0x2080030a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS { + NvHandle hEventBuffer; + NV_DECLARE_ALIGNED(NvU64 tracepointMask, 8); + NvU32 gspLoggingBufferSize; + NvU32 gspLoggingBufferWatermark; +} NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS; + + /* + * NV2080_CTRL_CMD_EVENT_NOCAT_BIND_EVTBUF + * + * This command is used to create a NOCAT bind-point to an event buffer. + * + * hEventBuffer[IN] + * The event buffer to bind to + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_EVENT_NOCAT_BIND_EVTBUF (0x2080030b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_NOCAT_BIND_EVTBUF_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_EVENT_NOCAT_BIND_EVTBUF_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV2080_CTRL_EVENT_NOCAT_BIND_EVTBUF_PARAMS { + NvHandle hEventBuffer; +} NV2080_CTRL_EVENT_NOCAT_BIND_EVTBUF_PARAMS; + + + +/* _ctrl2080event_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fan.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fan.h new file mode 100644 index 0000000..1221171 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fan.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080fan.finn +// + + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fb.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fb.h new file mode 100644 index 0000000..06653bd --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fb.h @@ -0,0 +1,3093 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080fb.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX fb control commands and parameters */ + +#include "nvlimits.h" +#include "nvcfg_sdk.h" + +/* + * NV2080_CTRL_FB_INFO + * + * This structure represents a single 32bit fb engine value. Clients + * request a particular fb engine value by specifying a unique fb + * information index. + * + * Legal fb information index values are: + * NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT + * This index is used to request the number of tiled regions supported + * by the associated subdevice. The return value is GPU + * implementation-dependent. A return value of 0 indicates the GPU + * does not support tiling. + * NV2080_CTRL_FB_INFO_INDEX_COMPRESSION_SIZE + * This index is used to request the amount of compression (in bytes) + * supported by the associated subdevice. The return value is GPU + * implementation-dependent. A return value of 0 indicates the GPU + * does not support compression. + * Nv2080_CTRL_FB_INFO_INDEX_DRAM_PAGE_STRIDE + * This index is used to request the DRAM page stride (in bytes) + * supported by the associated subdevice. The return value is GPU + * implementation-dependent. + * NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_FREE_COUNT + * This index is used to request the number of free tiled regions on + * the associated subdevice. The return value represents the current + * number of free tiled regions at the time the command is processed and + * is not guaranteed to remain unchanged. A return value of 0 indicates + * that there are no available tiled regions on the associated subdevice. + * NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT + * This index is used to request the number of frame buffer partitions + * on the associated subdevice. Starting with Fermi there are now two units + * with the name framebuffer partitions. On those chips this index returns + * the number of FBPAs. For number of FBPs use + * NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE + * This index is used to request the amount of framebuffer memory in + * kilobytes physically present on the associated subdevice. This + * value will never exceed the value reported by + * NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE. + * This an SMC aware attribute, so the per-partition framebuffer memory + * size will be returned when the client has a partition subscription. + * NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE + * This index is used to request the total amount of video memory in + * kilobytes for use with the associated subdevice. This value will + * reflect both framebuffer memory as well as any system memory dedicated + * for use with the subdevice. + * This an SMC aware attribute, so the per-partition video memory size + * will be returned when the client has a partition subscription. + * NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE + * This index is used to request the amount of total RAM in kilobytes + * available for user allocations. This value reflects the total ram + * size less the amount of memory reserved for internal use. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_HEAP_START + * This index is used to request the offset for start of heap in + * kilobytes. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE + * This index is used to request the available amount of video memory in + * kilobytes for use with the associated subdevice or the SMC partition. + * This an SMC aware attribute, thus necessary partition subscription is + * required to query per partition information, if the device is partitioned. + * Alternatively, the SMC/MIG monitor capability can be acquired to query + * aggregate available memory across all the valid partitions. + * NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE + * This index reflects the amount of heap memory in kilobytes that + * is accessible by the CPU. On subdevices with video memory sizes that + * exceed the amount that can be bus mappable this value will be less + * than that reported by NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_BUS_WIDTH + * This index is used to request the FB bus bandwidth on the associated + * subdevice. + * NV2080_CTRL_FB_INFO_INDEX_RAM_CFG + * This index is used to request the implementation-dependent RAM + * configuration value of the associated subdevice. + * NV2080_CTRL_FB_INFO_INDEX_RAM_TYPE + * This index is used to request the type of RAM used for the framebuffer + * on the associated subdevice. Legal RAM types include: + * NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN + * NV2080_CTRL_FB_INFO_RAM_TYPE_SDRAM + * NV2080_CTRL_FB_INFO_RAM_TYPE_DDR1 + * NV2080_CTRL_FB_INFO_RAM_TYPE_DDR2 + * NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR2 + * NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR3 + * NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR4 + * NV2080_CTRL_FB_INFO_RAM_TYPE_DDR3 + * NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5 + * NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5X + * NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6 + * NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6X + * NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR2 + * NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR4 + * NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5 + * NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT + * This index is used to request the number of FB banks on the associated + * subdevice. + * NV2080_CTRL_FB_INFO_INDEX_OVERLAY_OFFSET_ADJUSTMENT + * This index is used to request the offset relative to the start of the + * overlay surface(s), in bytes, at which scanout should happen if the + * primary and the overlay surfaces are all aligned on large page + * boundaries. + * NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_SPACE_SIZE_KB + * This index is used to request the size of the GPU's virtual address + * space in kilobytes. + * NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_HEAP_SIZE_KB + * This index is used to request the size of the GPU's virtual address + * space heap (minus RM-reserved space) in kilobytes. + * NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_MAPPBLE_SIZE_KB + * This index is used to request the size of the GPU's BAR1 mappable + * virtual address space in kilobytes. + * NV2080_CTRL_FB_INFO_INDEX_EFFECTIVE_BW + * This index is deprecated, and returns zero value. + * NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK + * NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_0 + * NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_1 + * NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_2 + * NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_3 + * This index is used to request the mask of currently active partitions. + * Each active partition has an ID that's equivalent to the corresponding + * bit position in the mask. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * This value is moving from 32bits to 64bits, so PARTITION_MASK + * (though kept for backwards compatibility on older chips), on newer chips + * will be replaced by: + * PARTITION_MASK_0 for the lower 32bits + * PARTITION_MASK_1 for the next 32bits + * PARTITION_MASK_2 for the next 32bits + * PARTITION_MASK_3 for the upper 32bits + * Note that PARTITION_MASK and PARTITION_MASK_0 are handled the same, and + * use the same enum value. + * NV2080_CTRL_FB_INFO_INDEX_LTC_MASK + * NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_0 + * NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_1 + * NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_2 + * NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_3 + * NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_4 + * NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_5 + * NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_6 + * NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_7 + * This index is used to request the mask of currently active LTCs. + * Each active LTC has an ID that's equivalent to the corresponding + * bit position in the mask. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * This value is moving from 32bits to 64bits, so LTC_MASK + * (though kept for backwards compatibility on older chips), on newer chips + * will be replaced by: + * LTC_MASK_0 for the lower 32bits + * LTC_MASK_1 for the next 32bits + * LTC_MASK_2 for the next 32bits + * LTC_MASK_3 for the next 32bits + * LTC_MASK_4 for the next 32bits + * LTC_MASK_5 for the next 32bits + * LTC_MASK_6 for the next 32bits + * LTC_MASK_7 for the upper 32bits + * Note that LTC_MASK and LTC_MASK_0 are handled the same, and + * use the same enum value. + * NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE + * This index is used to request the amount of total RAM in kilobytes + * reserved for internal RM allocations on Vista. This will need to + * be subtracted from the total heap size to get the amount available to + * KMD. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_RAM_LOCATION + * This index is used to distinguish between different memory + * configurations. + * NV2080_CTRL_FB_INFO_INDEX_FB_IS_BROKEN + * This index is used to check if the FB is functional + * NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT + * This index is used to get the number of FBPs on the subdevice. This + * field is not to be confused with + * NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT (returns number of FBPAs). + * Starting with Fermi the term partition is an ambiguous term, both FBP + * and FBPA mean FB partitions. The FBPA is the low level DRAM controller, + * while a FBP is the aggregation of one or more FBPAs, L2, ROP, and some + * other units. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_L2CACHE_SIZE + * This index is used to get the size of the L2 cache in Bytes. + * A value of zero indicates that the L2 cache isn't supported on the + * associated subdevice. + * NV2080_CTRL_FB_INFO_INDEX_MEMORYINFO_VENDOR_ID + * This index is used to get the memory vendor ID information from + * the Memory Information Table in the VBIOS. Legal memory Vendor ID + * values include: + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_UNKNOWN + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_RESERVED + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_SAMSUNG + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_QIMONDA + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ELPIDA + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ETRON + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_NANYA + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_HYNIX + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MOSEL + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_WINBOND + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ESMT + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MICRON + * NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE + * This index is used to request the amount of unused bar1 space. The + * data returned is a value in KB. It is not guaranteed to be entirely + * accurate since it is a snapshot at a particular time and can + * change quickly. + * NV2080_CTRL_FB_INFO_INDEX_BAR1_MAX_CONTIGUOUS_AVAIL_SIZE + * This index is used to request the amount of largest unused contiguous + * block in bar1 space. The data returned is a value in KB. It is not + * guaranteed to be entirely accurate since it is a snapshot at a particular + * time and can change quickly. + * NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE + * This index is used to request the amount of usable framebuffer memory in + * kilobytes physically present on the associated subdevice. This + * value will never exceed the value reported by + * NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_LTC_COUNT + * Returns the active LTC count across all active FBPs. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_LTS_COUNT + * Returns the active LTS count across all active LTCs. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_PSEUDO_CHANNEL_MODE + * This is used to identify if pseudo-channel mode is enabled for HBM + * NV2080_CTRL_FB_INFO_INDEX_SMOOTHDISP_RSVD_BAR1_SIZE + * This is used by WDDM-KMD to determine whether and how much RM reserved BAR1 for smooth transition + * NV2080_CTRL_FB_INFO_INDEX_HEAP_OFFLINE_SIZE + * Returns the total size of the all dynamically offlined pages in KiB + * NV2080_CTRL_FB_INFO_INDEX_1TO1_COMPTAG_ENABLED + * Returns true if 1to1 comptag is enabled + * NV2080_CTRL_FB_INFO_INDEX_SUSPEND_RESUME_RSVD_SIZE + * Returns the total size of the memory(FB) that will saved/restored during save/restore cycle + * NV2080_CTRL_FB_INFO_INDEX_ALLOW_PAGE_RETIREMENT + * Returns true if page retirement is allowed + * NV2080_CTRL_FB_INFO_POISON_FUSE_ENABLED + * Returns true if poison fuse is enabled + * NV2080_CTRL_FB_INFO_FBPA_ECC_ENABLED + * Returns true if ECC is enabled for FBPA + * NV2080_CTRL_FB_INFO_DYNAMIC_PAGE_OFFLINING_ENABLED + * Returns true if dynamic page blacklisting is enabled + * NV2080_CTRL_FB_INFO_INDEX_FORCED_BAR1_64KB_MAPPING_ENABLED + * Returns true if 64KB mapping on BAR1 is force-enabled + * NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_SIZE + * Returns the P2P mailbox size to be allocated by the client. + * Returns 0 if the P2P mailbox is allocated by RM. + * NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_ALIGNMENT_SIZE + * Returns the P2P mailbox alignment requirement. + * Returns 0 if the P2P mailbox is allocated by RM. + * NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_BAR1_MAX_OFFSET_64KB + * Returns the P2P mailbox max offset requirement. + * Returns 0 if the P2P mailbox is allocated by RM. + * NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB + * Returns total protected memory when memory protection is enabled + * Returns 0 when memory protection is not enabled. + * NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB + * Returns protected memory available for allocation when memory + * protection is enabled. + * Returns 0 when memory protection is not enabled. + * NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE + * Returns the ECC status size (corresponds to subpartitions or channels + * depending on architecture/memory type). + * NV2080_CTRL_FB_INFO_INDEX_IS_ZERO_FB + * Returns true if FB is not present on this chip + * NV2080_CTRL_FB_INFO_INDEX_ACCESS_COUNTER_BUFFER_COUNT + * Returns the count of access counter buffers supported by GPU + */ +typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FB_INFO; + +/* valid fb info index values */ +#define NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT (0x00000000U) // Deprecated +#define NV2080_CTRL_FB_INFO_INDEX_COMPRESSION_SIZE (0x00000001U) +#define NV2080_CTRL_FB_INFO_INDEX_DRAM_PAGE_STRIDE (0x00000002U) +#define NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_FREE_COUNT (0x00000003U) +#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT (0x00000004U) +#define NV2080_CTRL_FB_INFO_INDEX_BAR1_SIZE (0x00000005U) +#define NV2080_CTRL_FB_INFO_INDEX_BANK_SWIZZLE_ALIGNMENT (0x00000006U) +#define NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE (0x00000007U) +#define NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE (0x00000008U) +#define NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE (0x00000009U) +#define NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE (0x0000000AU) +#define NV2080_CTRL_FB_INFO_INDEX_BUS_WIDTH (0x0000000BU) +#define NV2080_CTRL_FB_INFO_INDEX_RAM_CFG (0x0000000CU) +#define NV2080_CTRL_FB_INFO_INDEX_RAM_TYPE (0x0000000DU) +#define NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT (0x0000000EU) +#define NV2080_CTRL_FB_INFO_INDEX_OVERLAY_OFFSET_ADJUSTMENT (0x0000000FU) // Deprecated (index reused to return 0) +#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_SPACE_SIZE_KB (0x0000000FU) // Deprecated (index reused to return 0) +#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_HEAP_SIZE_KB (0x0000000FU) // Deprecated (index reused to return 0) +#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_MAPPBLE_SIZE_KB (0x0000000FU) // Deprecated (index reused to return 0) +#define NV2080_CTRL_FB_INFO_INDEX_EFFECTIVE_BW (0x0000000FU) // Deprecated (index reused to return 0) +#define NV2080_CTRL_FB_INFO_INDEX_FB_TAX_SIZE_KB (0x00000010U) +#define NV2080_CTRL_FB_INFO_INDEX_HEAP_BASE_KB (0x00000011U) +#define NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_SIZE_KB (0x00000012U) +#define NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_BASE_KB (0x00000013U) +#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK (0x00000014U) +#define NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE (0x00000015U) +#define NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE (0x00000016U) +#define NV2080_CTRL_FB_INFO_INDEX_RAM_LOCATION (0x00000017U) +#define NV2080_CTRL_FB_INFO_INDEX_FB_IS_BROKEN (0x00000018U) +#define NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT (0x00000019U) +#define NV2080_CTRL_FB_INFO_INDEX_FBP_MASK (0x0000001AU) +#define NV2080_CTRL_FB_INFO_INDEX_L2CACHE_SIZE (0x0000001BU) +#define NV2080_CTRL_FB_INFO_INDEX_MEMORYINFO_VENDOR_ID (0x0000001CU) +#define NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE (0x0000001DU) +#define NV2080_CTRL_FB_INFO_INDEX_HEAP_START (0x0000001EU) +#define NV2080_CTRL_FB_INFO_INDEX_BAR1_MAX_CONTIGUOUS_AVAIL_SIZE (0x0000001FU) +#define NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE (0x00000020U) +#define NV2080_CTRL_FB_INFO_INDEX_TRAINIG_2T (0x00000021U) +#define NV2080_CTRL_FB_INFO_INDEX_LTC_COUNT (0x00000022U) +#define NV2080_CTRL_FB_INFO_INDEX_LTS_COUNT (0x00000023U) +#define NV2080_CTRL_FB_INFO_INDEX_L2CACHE_ONLY_MODE (0x00000024U) +#define NV2080_CTRL_FB_INFO_INDEX_PSEUDO_CHANNEL_MODE (0x00000025U) +#define NV2080_CTRL_FB_INFO_INDEX_SMOOTHDISP_RSVD_BAR1_SIZE (0x00000026U) +#define NV2080_CTRL_FB_INFO_INDEX_HEAP_OFFLINE_SIZE (0x00000027U) +#define NV2080_CTRL_FB_INFO_INDEX_1TO1_COMPTAG_ENABLED (0x00000028U) +#define NV2080_CTRL_FB_INFO_INDEX_SUSPEND_RESUME_RSVD_SIZE (0x00000029U) +#define NV2080_CTRL_FB_INFO_INDEX_ALLOW_PAGE_RETIREMENT (0x0000002AU) +#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK (0x0000002BU) +#define NV2080_CTRL_FB_INFO_POISON_FUSE_ENABLED (0x0000002CU) +#define NV2080_CTRL_FB_INFO_FBPA_ECC_ENABLED (0x0000002DU) +#define NV2080_CTRL_FB_INFO_DYNAMIC_PAGE_OFFLINING_ENABLED (0x0000002EU) +#define NV2080_CTRL_FB_INFO_INDEX_FORCED_BAR1_64KB_MAPPING_ENABLED (0x0000002FU) +#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_SIZE (0x00000030U) +#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_ALIGNMENT (0x00000031U) +#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_BAR1_MAX_OFFSET_64KB (0x00000032U) +#define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB (0x00000033U) +#define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB (0x00000034U) +#define NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE (0x00000035U) +#define NV2080_CTRL_FB_INFO_INDEX_IS_ZERO_FB (0x00000036U) +#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_0 (NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK) +#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_1 (0x00000037U) +#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_0 (NV2080_CTRL_FB_INFO_INDEX_LTC_MASK) +#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_1 (0x00000038U) +#define NV2080_CTRL_FB_INFO_INDEX_ACCESS_COUNTER_BUFFER_COUNT (0x00000039U) +#define NV2080_CTRL_FB_INFO_INDEX_COHERENCE_INFO (0x0000003AU) +#define NV2080_CTRL_FB_INFO_INDEX_NUMA_NODE_ID (0x0000003BU) +#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_2 (0x0000003CU) +#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_3 (0x0000003DU) +#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_2 (0x0000003EU) +#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_3 (0x0000003FU) +#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_4 (0x00000040U) +#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_5 (0x00000041U) +#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_6 (0x00000042U) +#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_7 (0x00000043U) + +#define NV2080_CTRL_FB_INFO_INDEX_MAX NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_7 + +/* Intentionally picking a value much bigger than NV2080_CTRL_FB_INFO_INDEX_MAX to prevent VGPU plumbing updates */ +#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE (0x00000080U) + +/* valid fb RAM type values */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN (0x00000000U) +#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDRAM (0x00000001U) +#define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR1 (0x00000002U) /* SDDR and GDDR (aka DDR1 and GDDR1) */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2 (0x00000003U) /* SDDR2 Used on NV43 and later */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR2 NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2 /* Deprecated alias */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR2 (0x00000004U) /* GDDR2 Used on NV30 and some NV36 */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR3 (0x00000005U) /* GDDR3 Used on NV40 and later */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR4 (0x00000006U) /* GDDR4 Used on G80 and later (deprecated) */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3 (0x00000007U) /* SDDR3 Used on G9x and later */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR3 NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3 /* Deprecated alias */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5 (0x00000008U) /* GDDR5 Used on GT21x and later */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR2 (0x00000009U) /* LPDDR (Low Power SDDR) used on T2x and later. */ + + +#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR4 (0x0000000CU) /* SDDR4 Used on Maxwell and later */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR4 (0x0000000DU) /* LPDDR (Low Power SDDR) used on T21x and later.*/ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM1 (0x0000000EU) /* HBM1 (High Bandwidth Memory) used on GP100 */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM2 (0x0000000FU) /* HBM2 (High Bandwidth Memory-pseudo channel) */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5X (0x00000010U) /* GDDR5X Used on GP10x */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6 (0x00000011U) /* GDDR6 Used on TU10x */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6X (0x00000012U) /* GDDR6X Used on GA10x */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5 (0x00000013U) /* LPDDR (Low Power SDDR) used on T23x and later.*/ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM3 (0x00000014U) /* HBM3 (High Bandwidth Memory) v3 */ + +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR7 (0x00000015U) /* GDDR7 */ + + +/* + * Guarding the macro which reveal the use of HBM4. + */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM4 (0x00000016U) /* HBM4 (High Bandwidth Memory) v4 */ + + + +/* valid RAM LOCATION types */ +#define NV2080_CTRL_FB_INFO_RAM_LOCATION_GPU_DEDICATED (0x00000000U) +#define NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_SHARED (0x00000001U) +#define NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_DEDICATED (0x00000002U) + +/* valid Memory Vendor ID values */ +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_SAMSUNG (0x00000001U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_QIMONDA (0x00000002U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ELPIDA (0x00000003U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ETRON (0x00000004U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_NANYA (0x00000005U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_HYNIX (0x00000006U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MOSEL (0x00000007U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_WINBOND (0x00000008U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ESMT (0x00000009U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MICRON (0x0000000FU) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_UNKNOWN (0xFFFFFFFFU) + +#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_UNSUPPORTED (0x00000000U) +#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_DISABLED (0x00000001U) +#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_ENABLED (0x00000002U) + +#define NV2080_CTRL_FB_INFO_INDEX_COHERENCE_INFO_NON_FULLY_COHERENT (0x00000000U) +#define NV2080_CTRL_FB_INFO_INDEX_COHERENCE_INFO_FULLY_COHERENT (0x00000001U) + +/** + * NV2080_CTRL_CMD_FB_GET_INFO + * + * This command returns fb engine information for the associated GPU. + * Requests to retrieve fb information use a list of one or more + * NV2080_CTRL_FB_INFO structures. + * + * fbInfoListSize + * This field specifies the number of entries on the caller's + * fbInfoList. + * fbInfoList + * This field specifies a pointer in the caller's address space + * to the buffer into which the fb information is to be returned. + * This buffer must be at least as big as fbInfoListSize multiplied + * by the size of the NV2080_CTRL_FB_INFO structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV2080_CTRL_CMD_FB_GET_INFO (0x20801301U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_FB_GET_INFO_PARAMS { + NvU32 fbInfoListSize; + NV_DECLARE_ALIGNED(NvP64 fbInfoList, 8); +} NV2080_CTRL_FB_GET_INFO_PARAMS; + +#define NV2080_CTRL_CMD_FB_GET_INFO_V2 (0x20801303U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_INFO_V2_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_FB_GET_INFO_V2_PARAMS { + NvU32 fbInfoListSize; + NV2080_CTRL_FB_INFO fbInfoList[NV2080_CTRL_FB_INFO_MAX_LIST_SIZE]; +} NV2080_CTRL_FB_GET_INFO_V2_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_GET_BAR1_OFFSET + * + * This command returns the GPU virtual address of a bar1 + * allocation, given the CPU virtual address. + * + * cpuVirtAddress + * This field specifies the associated CPU virtual address of the + * memory allocation. + * gpuVirtAddress + * The GPU virtual address associated with the allocation + * is returned in this field. + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_GET_BAR1_OFFSET (0x20801310U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS { + NV_DECLARE_ALIGNED(NvP64 cpuVirtAddress, 8); + NV_DECLARE_ALIGNED(NvU64 gpuVirtAddress, 8); +} NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS; + +/* + * NV2080_CTRL_FB_CMD_GET_CALIBRATION_LOCK_FAILED + * + * This command returns the failure counts for calibration. + * + * uFlags + * Just one for now -- ehether to reset the counts. + * driveStrengthRiseCount + * This parameter specifies the failure count for drive strength rising. + * driveStrengthFallCount + * This parameter specifies the failure count for drive strength falling. + * driveStrengthTermCount + * This parameter specifies the failure count for drive strength + * termination. + * slewStrengthRiseCount + * This parameter specifies the failure count for slew strength rising. + * slewStrengthFallCount + * This parameter specifies the failure count for slew strength falling. + * slewStrengthTermCount + * This parameter specifies the failure count for slew strength + * termination. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INVALID_PARAM_STRUCT + * NVOS_STATUS_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_GET_CALIBRATION_LOCK_FAILED (0x2080130cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS { + NvU32 flags; + NvU32 driveStrengthRiseCount; + NvU32 driveStrengthFallCount; + NvU32 driveStrengthTermCount; + NvU32 slewStrengthRiseCount; + NvU32 slewStrengthFallCount; +} NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS; + +/* valid flags parameter values */ +#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE (0x00000000U) +#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET (0x00000001U) + +/* + * NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL + * + * If supported by hardware and the OS, this command implements a streamlined version of + * NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE which can be called at high IRQL and Bypass the + * RM Lock. + * + * Requires the following NVOS54_PARAMETERS to be set for raised IRQ / Lock Bypass operation: + * NVOS54_FLAGS_IRQL_RAISED + * NVOS54_FLAGS_LOCK_BYPASS + * + * flags + * Contains flags to control various aspects of the flush. Valid values + * are defined in NV2080_CTRL_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS*. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + * + * See Also: + * NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE + * This is the more generalized version which is not intended to be called at raised IRQ level + * NV0080_CTRL_CMD_DMA_FLUSH + * Performs flush operations in broadcast for the GPU cache and other hardware + * engines. Use this call if you want to flush all GPU caches in a + * broadcast device. + * NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE + * Flushes memory associated with a single allocation if the hardware + * supports it. Use this call if you want to flush a single allocation and + * you have a memory object describing the physical memory. + */ +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL (0x2080130dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS { + NvU32 flags; +} NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS; + +/* valid fields and values for flags */ +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK 0:0 +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_NO (0x00000000U) +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_YES (0x00000001U) +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE 1:1 +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_NO (0x00000000U) +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_YES (0x00000001U) +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH 2:2 +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_NO (0x00000000U) +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_YES (0x00000001U) + +/* + * NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE + * + * This command flushes a cache on the GPU which all memory accesses go + * through. The types of flushes supported by this API may not be supported by + * all hardware. Attempting an unsupported flush type will result in an error. + * + * addressArray + * An array of physical addresses in the aperture defined by + * NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE. Each entry points to a + * contiguous block of memory of size memBlockSizeBytes. The addresses are + * aligned down to addressAlign before coalescing adjacent addresses and + * sending flushes to hardware. + * addressAlign + * Used to align-down addresses held in addressArray. A value of 0 will be + * forced to 1 to avoid a divide by zero. Value is treated as minimum + * alignment and any hardware alignment requirements above this value will + * be honored. + * addressArraySize + * The number of entries in addressArray. + * memBlockSizeBytes + * The size in bytes of each memory block pointed to by addressArray. + * flags + * Contains flags to control various aspects of the flush. Valid values + * are defined in NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS*. Not all flags are + * valid for all defined FLUSH_MODEs or all GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + * + * See Also: + * NV0080_CTRL_CMD_DMA_FLUSH + * Performs flush operations in broadcast for the GPU cache and other hardware + * engines. Use this call if you want to flush all GPU caches in a + * broadcast device. + * NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE + * Flushes memory associated with a single allocation if the hardware + * supports it. Use this call if you want to flush a single allocation and + * you have a memory object describing the physical memory. + */ +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE (0x2080130eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES 500U + +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 addressArray[NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES], 8); + NvU32 addressArraySize; + NvU32 addressAlign; + NV_DECLARE_ALIGNED(NvU64 memBlockSizeBytes, 8); + NvU32 flags; +} NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS; + +/* valid fields and values for flags */ +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE 1:0 +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_VIDEO_MEMORY (0x00000000U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_SYSTEM_MEMORY (0x00000001U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_PEER_MEMORY (0x00000002U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK 2:2 +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_NO (0x00000000U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_YES (0x00000001U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE 3:3 +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_NO (0x00000000U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_YES (0x00000001U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE 4:4 +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_ADDRESS_ARRAY (0x00000000U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_FULL_CACHE (0x00000001U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH 5:5 +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_NO (0x00000000U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_YES (0x00000001U) + +/* + * NV2080_CTRL_CMD_FB_IS_KIND + * + * This command is used to perform various operations like 'IS_KIND_VALID', + * 'IS_KIND_COMPRESSIBLE'on the kind passed by the caller. The operation to be + * performed should be passed in the 'operation' parameter of + * NV2080_CTRL_FB_IS_KIND_PARAMS, the kind on which the operation is to be + * performed should be passed in the 'kind' parameter. The result of the + * operation (true/false) will be returned in the 'result' parameter. + * + * operation + * Specifies what operation is to be performed on the kind passed by the + * caller. The supported operations are + * NV2080_CTRL_FB_IS_KIND_OPERATION_SUPPORTED + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure is + * supported for this GPU. Returns nonzero value in 'result' parameter + * if the input kind is supported, else returns zero in the result. + * NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure is + * compressible. Returns nonzero value in 'result' parameter if the + * input kind is compressible, else returns zero in the result. + * NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_1 + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure supports + * 1 bit compression. Returns nonzero value in 'result' parameter if + * kind supports 1 bit compression, else returns zero in the result. + * NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_2 + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure supports + * 2 bit compression. Returns nonzero value in 'result' parameter if + * kind supports 1 bit compression, else returns zero in the result. + * NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_4 + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure supports + * 4 bit compression. Returns nonzero value in 'result' parameter if + * kind supports 4 bit compression, else returns zero in the result. + * NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure + * supports ZBC. Returns nonzero value in 'result' parameter if the + * input kind supports ZBC, else returns zero in the result. + * NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_1 + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure + * supports 1 bit ZBC. Returns nonzero value in 'result' parameter if + * the input kind supports 1 bit ZBC, else returns zero in the result. + * NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_2 + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure + * supports 2 bit ZBC. Returns nonzero value in 'result' parameter if + * the input kind supports 2 bit ZBC, else returns zero in the result. + * NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_4 + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure + * supports 4 bit ZBC. Returns nonzero value in 'result' parameter if + * the input kind supports 4 bit ZBC, else returns zero in the result. + * kind + * Specifies the kind on which the operation is to be carried out. The + * legal range of values for the kind parameter is different on different + * GPUs. For e.g. on Fermi, valid range is 0x00 to 0xfe. Still, some values + * inside this legal range can be invalid i.e. not defined. + * So its always better to first check if a particular kind is supported on + * the current GPU with 'NV2080_CTRL_FB_IS_KIND_SUPPORTED' operation. + * result + * Upon return, this parameter will hold the result (true/false) of the + * operation performed on the kind. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_IS_KIND (0x20801313U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV2080_CTRL_FB_IS_KIND_PARAMS { + NvU32 operation; + NvU32 kind; + NvBool result; +} NV2080_CTRL_FB_IS_KIND_PARAMS; + +/* valid values for operation */ +#define NV2080_CTRL_FB_IS_KIND_OPERATION_SUPPORTED (0x00000000U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE (0x00000001U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_1 (0x00000002U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_2 (0x00000003U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_4 (0x00000004U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC (0x00000005U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_1 (0x00000006U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_2 (0x00000007U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_4 (0x00000008U) + +/** + * NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO + * + * This command returns the state of a cache which all GPU memory accesess go + * through. + * + * powerState + * Returns the power state of the cache. Possible values are defined in + * NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE. + * + * writeMode + * Returns the write mode of the cache. Possible values are defined in + * NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE. + * + * bypassMode + * Returns the bypass mode of the L2 cache. Possible values are defined in + * NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE. + * + * rcmState + * Returns the RCM state of the cache. Possible values are defined in + * NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO (0x20801315U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS { + NvU32 powerState; + NvU32 writeMode; + NvU32 bypassMode; + NvU32 rcmState; +} NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS; + +/* valid values for powerState */ +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_ENABLED (0x00000000U) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_DISABLED (0x00000001U) +/* valid values for writeMode */ +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITETHROUGH (0x00000000U) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITEBACK (0x00000001U) +/* valid values for bypassMode */ +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_DISABLED (0x00000000U) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_ENABLED (0x00000001U) +/* valid values for rcmState */ +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_FULL (0x00000000U) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_TRANSITIONING (0x00000001U) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_REDUCED (0x00000002U) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_ZERO_CACHE (0x00000003U) + +/* + * NV2080_CTRL_FB_CMD_GET_FB_REGION_INFO + * + * This command returns the FB memory region characteristics. + * + * numFBRegions + * Number of valid regions returned in fbRegion[] + * fbRegion[].base + * Base address of region. The first valid address in the range + * [base..limit]. + * fbRegion[].limit + * Last/end address of region. The last valid address in the range + * [base..limit]. + * (limit - base + 1) = size of the region + * fbRegion[].reserved + * Amount of memory that RM speculatively needs within the region. A + * client doing its own memory management should leave at least this much + * memory available for RM use. This particularly applies to a driver + * model like LDDM. + * fbRegion[].performance + * Relative performance of this region compared to other regions. + * The definition is vague, and only connotes relative bandwidth or + * performance. The higher the value, the higher the performance. + * fbRegion[].supportCompressed + * TRUE if compressed surfaces/kinds are supported + * FALSE if compressed surfaces/kinds are not allowed to be allocated in + * this region + * fbRegion[].supportISO + * TRUE if ISO surfaces/kinds are supported (Display, cursor, video) + * FALSE if ISO surfaces/kinds are not allowed to be allocated in this + * region + * fbRegion[].bProtected + * TRUE if this region is a protected memory region. If true only + * allocations marked as protected (NVOS32_ALLOC_FLAGS_PROTECTED) can be + * allocated in this region. + * fbRegion[].blackList[] - DEPRECATED: Use supportISO + * TRUE for each NVOS32_TYPE_IMAGE* that is NOT allowed in this region. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO (0x20801320U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES 18U + +// add tags as needed for regions through either memmgrInitFbRegions or memmgrInsertFbRegion +typedef enum NV2080_FB_REGION_TAG { + NV2080_FB_REGION_TAG_NONE = 0, // default tag + NV2080_FB_REGION_TAG_GSP_CARVEOUT = 1, // GSP carveout region, usually at highest address + NV2080_FB_REGION_TAG_CPU_RM_RESERVED = 2, // first reserved region for structures in CPU RM + NV2080_FB_REGION_TAG_CPU_RM_RESERVED_HEAP = 3, // second reserved region for structures in CPU RM + NV2080_FB_REGION_TAG_GSP_RM_RESERVED = 4, // first reserved region for structures in GSP RM + NV2080_FB_REGION_TAG_GSP_RM_RESERVED_HEAP = 5, // second reserved region for structures in GSP RM +} NV2080_FB_REGION_TAG; + +typedef struct NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO { + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 limit, 8); + NV_DECLARE_ALIGNED(NvU64 reserved, 8); + NvU32 performance; + NvBool supportCompressed; + NvBool supportISO; + NvBool bProtected; + NvBool blackList[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES]; + NV2080_FB_REGION_TAG regionTag; +} NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO; + +#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES 16U + +#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS { + NvU32 numFBRegions; + NV_DECLARE_ALIGNED(NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO fbRegion[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES], 8); +} NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_OFFLINE_PAGES + * + * This command adds video memory page addresses to the list of offlined + * addresses so that they're not allocated to any client. The newly offlined + * addresses take effect after a reboot. + * + * offlined + * This input parameter is an array of NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO + * structures, containing the video memory physical page numbers that + * are to be blacklisted. This array can hold a maximum of NV2080_CTRL_FB_ + * BLACKLIST_PAGES_MAX_PAGES address pairs. Valid entries are adjacent. + * pageSize + * This input parameter contains the size of the page that is to be + * blacklisted. + * validEntries + * This input parameter specifies the number of valid entries in the + * offlined array. + * numPagesAdded + * This output parameter specifies how many of the validEntries were + * actually offlined. If numPagesAdded < validEntries, it + * means that only addresses from offlined[0] to offlined[numPagesAdded - 1] + * were added to the list of offlined addresses. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_OFFLINE_PAGES (0x20801321U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES (0x00000040U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_INVALID_ADDRESS (0xffffffffffffffffULL) +#define NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_4K (0x00000000U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_64K (0x00000001U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_128K (0x00000002U) + +/* + * NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO + * + * pageAddressWithEccOn + * Address of the memory page retired when ECC is enabled on the board. + * pageAddressWithEccOff + * Address of the memory page retired when ECC is disabled on the board. + * rbcAddress + * Row/Bank/Column Address of the faulty memory which caused the page to + * be retired + * source + * The reason for the page to be retired + * status + * Non-exceptional reasons for a page retirement failure + * NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_OK + * No error + * NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_PENDING_RETIREMENT + * The given address is already pending retirement or has + * been retired during the current driver run. The page + * will be offlined during the next driver run. + * NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_BLACKLISTING_FAILED + * The given page was retired on a previous driver run, + * so it should not be accessible unless offlining failed. + * Failing to offline a page is strongly indicative of a + * driver offlining bug. + * NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_TABLE_FULL + * The PBL is full and no more pages can be retired + * NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_INTERNAL_ERROR + * Internal driver error + * + */ + + + +typedef struct NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO { + NV_DECLARE_ALIGNED(NvU64 pageAddressWithEccOn, 8); + NV_DECLARE_ALIGNED(NvU64 pageAddressWithEccOff, 8); + NvU32 rbcAddress; + NvU32 source; + NvU32 status; + NvU32 timestamp; +} NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO; + +/* valid values for source */ +#define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE (0x00000002U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE (0x00000004U) + + + +/* valid values for status */ +#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_OK (0x00000000U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_PENDING_RETIREMENT (0x00000001U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_BLACKLISTING_FAILED (0x00000002U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_TABLE_FULL (0x00000003U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_INTERNAL_ERROR (0x00000004U) + +/* deprecated */ +#define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_MULTIPLE_SBE NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE +#define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DBE NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE + + +#define NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS_MESSAGE_ID (0x21U) + +typedef struct NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO offlined[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES], 8); + NvU32 pageSize; + NvU32 validEntries; + NvU32 numPagesAdded; +} NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_GET_OFFLINED_PAGES + * + * This command returns the list of video memory page addresses in the + * Inforom's blacklist. + * + * offlined + * This output parameter is an array of NV2080_CTRL_FB_BLACKLIST_ADDRESS_ + * INFO structures, containing the video memory physical page numbers that + * are blacklisted. This array can hold a maximum of NV2080_CTRL_FB_ + * BLACKLIST_PAGES_MAX_PAGES address pairs. Valid entries are adjacent. + * The array also contains the Row/Bank/Column Address and source. + * validEntries + * This output parameter specifies the number of valid entries in the + * offlined array. + * bRetirementPending (DEPRECATED, use retirementPending instead) + * This output parameter returns if any pages on the list are pending + * retirement. + * retirementPending + * Communicates to the caller whether retirement updates are pending and the + * reason for the updates. Possible fields are: + * NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_*: + * NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE: + * Indicates whether pages are pending retirement due to SBE. + * NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE: + * Indicates whether pages are pending retirement due to DBE. Driver + * reload needed to retire bad memory pages and allow compute app runs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + + + +#define NV2080_CTRL_CMD_FB_GET_OFFLINED_PAGES (0x20801322U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE 0:0 +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_FALSE 0U +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_TRUE 1U +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE 1:1 +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_FALSE 0U +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_TRUE 1U + + + +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO offlined[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES], 8); + NvU32 validEntries; + NvBool bRetirementPending; + NvU8 retirementPending; +} NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_QUERY_ACR_REGION + * + * This control command is used to query the secured region allocated + * + * queryType + * NV2080_CTRL_CMD_FB_ACR_QUERY_GET_REGION_STATUS: Provides the alloc + * status and ACR region ID. + * NV2080_CTRL_CMD_FB_QUERY_MAP_REGION : Maps the region on BAR1 + * it returns the "pCpuAddr" and pPriv to user. + * NV2080_CTRL_CMD_FB_QUERY_UNMAP_REGION: Unmaps the mapped region. + * it takes the pPriv as input + * + * clientReq : struct ACR_REQUEST_PARAMS + * It is used to find the allocated ACR region for that client + * clientId : ACR Client ID + * reqReadMask : read mask of ACR region + * reqWriteMask : Write mask of ACR region + * regionSize : ACR region Size + * + * clientReqStatus : struct ACR_STATUS_PARAMS + * This struct is stores the output of requested ACR region. + * allocStatus : Allocated Status of ACR region + * regionId : ACR region ID + * physicalAddress : Physical address on FB + * + * + * NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE + * NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_NONE : Control command executed successfully + * NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_INVALID_CLIENT_REQUEST : Please check the parameter + * for ACR client request + * NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_FAILED_TO_MAP_ON_BAR1 : RM Fails to map ACR region + * on BAR1 + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED +*/ +#define NV2080_CTRL_CMD_FB_QUERY_ACR_REGION (0x20801325U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS_MESSAGE_ID" */ + +// +// We can create an ACR region by using RMCreateAcrRegion[1|2] regkey or mods -acr[1|2]_size +// Client ID for such region is 2 in RM. +// +#define NV2080_CTRL_CMD_FB_ACR_CLIENT_ID 2U + +typedef enum NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE { + NV2080_CTRL_CMD_FB_ACR_QUERY_GET_CLIENT_REGION_STATUS = 0, + NV2080_CTRL_CMD_FB_ACR_QUERY_GET_REGION_PROPERTY = 1, + NV2080_CTRL_CMD_FB_ACR_QUERY_GET_FALCON_STATUS = 2, +} NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE; + +typedef enum NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE { + NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_NONE = 0, + NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_INVALID_CLIENT_REQUEST = 1, +} NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE; + +typedef struct ACR_REQUEST_PARAMS { + NvU32 clientId; + NvU32 reqReadMask; + NvU32 reqWriteMask; + NvU32 regionSize; +} ACR_REQUEST_PARAMS; + +typedef struct ACR_REGION_ID_PROP { + NvU32 regionId; + NvU32 readMask; + NvU32 writeMask; + NvU32 regionSize; + NvU32 clientMask; + NV_DECLARE_ALIGNED(NvU64 physicalAddress, 8); +} ACR_REGION_ID_PROP; + +typedef struct ACR_STATUS_PARAMS { + NvU32 allocStatus; + NvU32 regionId; + NV_DECLARE_ALIGNED(NvU64 physicalAddress, 8); +} ACR_STATUS_PARAMS; + +typedef struct ACR_REGION_HANDLE { + NvHandle hClient; + NvHandle hParent; + NvHandle hMemory; + NvU32 hClass; + NvHandle hDevice; +} ACR_REGION_HANDLE; + +typedef struct ACR_FALCON_LS_STATUS { + NvU16 falconId; + NvBool bIsInLs; +} ACR_FALCON_LS_STATUS; + +#define NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS_MESSAGE_ID (0x25U) + +typedef struct NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS { + NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE queryType; + NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE errorCode; + NV_DECLARE_ALIGNED(ACR_REGION_ID_PROP acrRegionIdProp, 8); + ACR_REQUEST_PARAMS clientReq; + NV_DECLARE_ALIGNED(ACR_STATUS_PARAMS clientReqStatus, 8); + ACR_REGION_HANDLE handle; + ACR_FALCON_LS_STATUS falconStatus; +} NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_CLEAR_OFFLINED_PAGES + * + * This command clears offlined video memory page addresses from the Inforom. + * + * sourceMask + * This is a bit mask of NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE. Pages + * offlined from the specified sources will be cleared/removed from the + * Inforom PBL object denylist. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_CLEAR_OFFLINED_PAGES (0x20801326U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS_MESSAGE_ID (0x26U) + +typedef struct NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS { + NvU32 sourceMask; +} NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO + * + * Gets pointer to then object of class CompBitCopy, which is used for swizzling + * compression bits in the compression backing store. The caller is expected to + * have the appropriate headers for class CompBitCopy. Also retrieves values of some + * parameters needed to call the compbit swizzling method. + * + * @params[out] void *pCompBitCopyObj + * Opaque pointer to object of class CompBitCopy + * @params[out] void *pSwizzleParams + * Opaque pointer to values needed to call the compbit + * swizzle method. + * + * Possible status values returned are: + * NV_OK NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO (0x20801327U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS_MESSAGE_ID (0x27U) + +typedef struct NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pCompBitCopyObj, 8); + NV_DECLARE_ALIGNED(NvP64 pSwizzleParams, 8); +} NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_GET_LTC_INFO_FOR_FBP + * + * Gets the count and mask of LTCs for a given FBP. + * + * fbpIndex + * The physical index of the FBP to get LTC info for. + * ltcMask + * The mask of active LTCs for the given FBP. + * ltcCount + * The count of active LTCs for the given FBP. + * ltsMask + * The mask of active LTSs for the given FBP + * ltsCount + * The count of active LTSs for the given FBP + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_GET_LTC_INFO_FOR_FBP (0x20801328U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_MESSAGE_ID (0x28U) + +typedef struct NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS { + NvU8 fbpIndex; + NvU32 ltcMask; + NvU32 ltcCount; + NvU32 ltsMask; + NvU32 ltsCount; +} NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS; + + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT < Deprecated > + * + * "set the context" for following CompBitCopy member functions. + * These are the CompBitCopy member variables that remain connstant + * over multiple CompBitCopy member function calls, yet stay the same + * throughout a single surface eviction. + * + * @params[in] UINT64 backingStorePA; + * Physical Address of the Backing Store + * @params[in] UINT08 *backingStoreVA; + * Virtual Address of the Backing Store + * @params[in] UINT64 backingStoreChunkPA; + * Physical Address of the "Chunk Buffer" + * @params[in] UINT08 *backingStoreChunkVA; + * Virtual Address of the "Chunk Buffer" + * @params[in] UINT32 backingStoreChunkSize; + * Size of the "Chunk Buffer" + * @params[in] UINT08 *cacheWriteBitMap; + * Pointer to the bitmap which parts of the + * "Chunk" was updated. + * @params[in] bool backingStoreChunkOverfetch; + * Overfetch factor. + * @params[in] UINT32 PageSizeSrc; + * Page size of Source Surface. + * @params[in] UINT32 PageSizeDest; + * page size of Destination Surface. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT (0x20801329U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x29" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS { + NvU32 CBCBaseAddress; + NV_DECLARE_ALIGNED(NvU64 backingStorePA, 8); + NV_DECLARE_ALIGNED(NvU8 *backingStoreVA, 8); + NV_DECLARE_ALIGNED(NvU64 backingStoreChunkPA, 8); + NV_DECLARE_ALIGNED(NvU8 *backingStoreChunkVA, 8); + NvU32 backingStoreChunkSize; + NV_DECLARE_ALIGNED(NvU8 *cacheWriteBitMap, 8); + NvBool backingStoreChunkOverfetch; + NvU32 PageSizeSrc; + NvU32 PageSizeDest; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS < Deprecated > + * + * Retrieves the Compression and Fast Clear bits for the surface+offset given. + * + * @params[out] NvU32 *fcbits; + * Fast Clear Bits returned + * @params[out] NvU32 *compbits; + * Compression Bits returned + * @params[in] NvU64 dataPhysicalStart; + * Start Address of Data + * @params[in] NvU64 surfaceOffset; + * Offset in the surface + * @params[in] NvU32 comptagLine; + * Compression Tag Number + * @params[in] NvBool upper64KBCompbitSel; + * Selects Upper or Lower 64K + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTEDD + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS (0x2080132aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2A" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS { + NV_DECLARE_ALIGNED(NvU32 *fcbits, 8); + NV_DECLARE_ALIGNED(NvU32 *compbits, 8); + NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8); + NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8); + NvU32 comptagLine; + NvBool upper64KBCompbitSel; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS < Deprecated > + * + * Sets the Compression and Fast Clear bits for the surface+offset given. + * + * @params[in] NvU32 fcbits; + * Fast Clear Bits to write. + * @params[in] NvU32 compbits; + * Compression Bits to write + * @params[in] NvBool writeFc; + * Indicates if Fast Clear Bits should be written + * @params[in] NvU64 dataPhysicalStart; + * Start Address of Data + * @params[in] NvU64 surfaceOffset; + * Offset in the surface + * @params[in] NvU32 comptagLine; + * Compression Tag Number + * @params[in] NvBool upper64KBCompbitSel; + * Selects Upper or Lower 64K + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS (0x2080132bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2B" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS { + NvU32 fcbits; + NvU32 compbits; + NvBool writeFc; + NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8); + NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8); + NvU32 comptagLine; + NvBool upper64KBCompbitSel; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB < Deprecated > + * + * Read 64KB chunk of CompBits + * + * @params[in] NvU64 SrcDataPhysicalStart; + * Start Address of Data + * @params[in] NvU32 SrcComptagLine; + * Compression Tag Number + * @params[in] NvU32 page64KB; + * Which 64K block to read from. + * @params[out] NvU32 *compbitBuffer; + * Buffer for CompBits read, + * @params[in] NvBool upper64KBCompbitSel; + * Selects Upper or Lower 64K + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB (0x2080132cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2C" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS { + NV_DECLARE_ALIGNED(NvU64 SrcDataPhysicalStart, 8); + NvU32 SrcComptagLine; + NvU32 page64KB; + NV_DECLARE_ALIGNED(NvU32 *compbitBuffer, 8); + NvBool upper64KBCompbitSel; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB < Deprecated > + * + * Write 64K chunk of COmpBits. + * + * @params[in] NvU64 SrcDataPhysicalStart; + * Start Address of Data + * @params[in] NvU32 SrcComptagLine; + * Compression Tag Number + * @params[in] NvU32 page64KB; + * Which 64K block to read from. + * @params[in] NvU32 *compbitBuffer; + * Buffer for CompBits to write. + * @params[in] NvBool upper64KBCompbitSel + * Selects Upper or Lower 64K + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB (0x2080132dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2D" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS { + NV_DECLARE_ALIGNED(NvU64 DstDataPhysicalStart, 8); + NvU32 DstComptagLine; + NvU32 page64KB; + NV_DECLARE_ALIGNED(NvU32 *compbitBuffer, 8); + NvBool upper64KBCompbitSel; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1 < Deprecated > + * + * Used by MODS (and possibly other clients) to have compbit code write + * write directly to BAR1, rather than a intermediate buffer. + * + * @params[in] NvBool bForceBar1; + * Enables or disables direct writes to BAR1. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1 (0x20801335U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x35" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS { + NvBool bForceBar1; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_GET_AMAP_CONF + * + * Fills in fields of a structure of class ConfParamsV1, which is used for + * swizzling compression bits in the compression backing store. + * The caller is expected to have the appropriate headers for class ConfParamsV1. + * + * @params[in|out] void *pAmapConfParms + * Opaque pointer to structure of values for ConfParamsV1 + * @params[in|out] void *pCbcSwizzleParms + * Opaque pointer to structure of values for CbcSwizzleParamsV1 + * + * Possible status values returned are: + * NV_OK NV_ERR_NOT_SUPPORTED + * + * pCbcSwizzleParams will be filled in with certain parameters from + * @CbcSwizzleParamsV1. However, the caller is responsible for making sure + * all parameters are filled in before using it. + */ +#define NV2080_CTRL_CMD_FB_GET_AMAP_CONF (0x20801336U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS_MESSAGE_ID (0x36U) + +typedef struct NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pAmapConfParams, 8); + NV_DECLARE_ALIGNED(NvP64 pCbcSwizzleParams, 8); +} NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_CBC_OP + * + * Provides a way for clients to request a CBC Operation + * + * @params[in] CTRL_CMD_FB_CBC_OP fbCBCOp + * CBC Operation requested. + * Valid Values: + * CTRL_CMD_FB_CBC_OP_CLEAN + * CTRL_CMD_FB_CBC_OP_INVALIDATE + * + * Possible status values returned are: + * NV_OK NV_ERR_NOT_SUPPORTED NV_ERR_INVALID_ARGUMENT NV_ERR_TIMEOUT + */ +#define NV2080_CTRL_CMD_FB_CBC_OP (0x20801337U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_CBC_OP_PARAMS_MESSAGE_ID" */ + +/*! + * Permitted CBC Operations + */ +typedef enum CTRL_CMD_FB_CBC_OP { + CTRL_CMD_FB_CBC_OP_CLEAN = 0, + CTRL_CMD_FB_CBC_OP_INVALIDATE = 1, +} CTRL_CMD_FB_CBC_OP; + +#define NV2080_CTRL_CMD_FB_CBC_OP_PARAMS_MESSAGE_ID (0x37U) + +typedef struct NV2080_CTRL_CMD_FB_CBC_OP_PARAMS { + CTRL_CMD_FB_CBC_OP fbCBCOp; +} NV2080_CTRL_CMD_FB_CBC_OP_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_GET_CTAGS_FOR_CBC_EVICTION + * + * The call will fetch the compression tags reserved for CBC eviction. + * + * Each comptag will correspond to a unique compression cacheline. The usage of + * these comptags is to evict the CBC by making accesses to a dummy compressed page, + * thereby evicting each CBC line. + * + * @param [in][out] NvU32 pCompTags + * Array of reserved compression tags of size @ref NV2080_MAX_CTAGS_FOR_CBC_EVICTION + * @param [out] numCompTags + * Number of entries returned in @ref pCompTags + * + * @returns + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_OUT_OF_RANGE + * NV_ERR_INVALID_PARAMETER + */ +#define NV2080_CTRL_CMD_FB_GET_CTAGS_FOR_CBC_EVICTION (0x20801338U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS_MESSAGE_ID" */ + +/*! + * Max size of @ref NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS::pCompTags + * Arbitrary, but sufficiently large number. Should be checked against CBC size. + */ +#define NV2080_MAX_CTAGS_FOR_CBC_EVICTION 0x7FU + + +#define NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS_MESSAGE_ID (0x38U) + +typedef struct NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS { + NvU32 pCompTags[NV2080_MAX_CTAGS_FOR_CBC_EVICTION]; + NvU32 numCompTags; +} NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE + * + * This Call will allocate compression tag + * + * @params[in] NvU32 attr + * Stores the information: + * 1. NVOS32_ATTR_COMPR_REQUIRED or not + * 2. NVOS32_ATTR_PAGE_SIZE + * @params[in] NvU32 attr2 + * Determine whether to allocate + * an entire cache line or allocate by size + * @params[in] NvU32 size + * Specify the size of allocation, in pages not bytes + * @params[in] NvU32 ctagOffset + * Determine the offset usage of the allocation + * @params[out] NvU32 hwResId + * Stores the result of the allocation + * @params[out] NvU32 RetcompTagLineMin + * The resulting min Ctag Number from the allocation + * @params[out] NvU32 RetcompTagLineMax + * The resulting max Ctag Number from the allocation + * @returns + * NV_OK + * NV_ERR_INSUFFICIENT_RESOURCES + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ + +#define NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE (0x20801339U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS_MESSAGE_ID (0x39U) + +typedef struct NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS { + NvU32 attr; + NvU32 attr2; + NvU32 size; + NvU32 ctagOffset; + NvU32 hwResId; + NvU32 retCompTagLineMin; + NvU32 retCompTagLineMax; +} NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_FREE_TILE + * + * This control call is used to release tile back to the free pool + * + * @params[in] NvU32 hwResId + * Stores the information of a previous allocation + * @returns + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ + +#define NV2080_CTRL_CMD_FB_FREE_TILE (0x2080133aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS_MESSAGE_ID (0x3AU) + +typedef struct NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS { + NvU32 hwResId; +} NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS; + + +/* + * NV2080_CTRL_CMD_FB_SETUP_VPR_REGION + * + * This control command is used to request vpr region setup + * + * requestType + * NV2080_CTRL_CMD_FB_SET_VPR: Request to setup VPR + * + * requestParams : struct VPR_REQUEST_PARAMS + * It contains the VPR region request details like, + * startAddr : FB offset from which we need to setup VPR + * size : required size of the region + * + * statusParams : struct VPR_STATUS_PARAMS + * This struct stores the output of requested VPR region + * status : Whether the request was successful + * + * NV2080_CTRL_CMD_FB_VPR_ERROR_CODE : + * NV2080_CTRL_CMD_FB_VPR_ERROR_GENERIC : Some unknown error occurred + * NV2080_CTRL_CMD_FB_VPR_ERROR_INVALID_CLIENT_REQUEST : Request was invalid + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_SETUP_VPR_REGION (0x2080133bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE { + NV2080_CTRL_CMD_FB_SET_VPR = 0, +} NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE; + +typedef enum NV2080_CTRL_CMD_FB_VPR_ERROR_CODE { + NV2080_CTRL_CMD_FB_VPR_ERROR_GENERIC = 0, + NV2080_CTRL_CMD_FB_VPR_ERROR_INVALID_CLIENT_REQUEST = 1, +} NV2080_CTRL_CMD_FB_VPR_ERROR_CODE; + +typedef struct VPR_REQUEST_PARAMS { + NvU32 startAddr; + NvU32 size; +} VPR_REQUEST_PARAMS; + +typedef struct VPR_STATUS_PARAMS { + NvU32 status; +} VPR_STATUS_PARAMS; + +#define NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS_MESSAGE_ID (0x3BU) + +typedef struct NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS { + NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE requestType; + VPR_REQUEST_PARAMS requestParams; + VPR_STATUS_PARAMS statusParams; +} NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS; +typedef struct NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS *PNV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_GET_CLI_MANAGED_OFFLINED_PAGES + * + * This command returns the list of offlined video memory page addresses in the + * region managed by Client + * + * offlinedPages + * This output parameter is an array of video memory physical page numbers that + * are offlined. This array can hold a maximum of NV2080_CTRL_FB_ + * OFFLINED_PAGES_MAX_PAGES addresses. + * pageSize + * This output parameter contains the size of the page that is offlined. + * validEntries + * This output parameter specifies the number of valid entries in the + * offlined array. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_FB_GET_CLI_MANAGED_OFFLINED_PAGES (0x2080133cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS_MESSAGE_ID (0x3CU) + +typedef struct NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS { + NvU32 offlinedPages[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES]; // A 32B can hold enough. + NvU32 pageSize; + NvU32 validEntries; +} NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO + * + * This command returns parameters required to initialize compbit copy object + * used by address mapping library + * + * defaultPageSize + * Page size used by @ref CompBitCopy methods + * comptagsPerCacheLine + * Number of compression tags in a single compression cache line. + * unpackedComptagLinesPerCacheLine; + * From hw (not adjusted for CompBits code) Number of compression tags + * in a single compression cache line. + * compCacheLineSizePerLTC; + * Size of compression cache line per L2 slice. Size in Bytes. + * unpackedCompCacheLineSizePerLTC; + * From hw (not adjusted for CompBits code) size of compression + * cache line per L2 slice. Size in Bytes + * slicesPerLTC; + * Number of L2 slices per L2 cache. + * numActiveLTCs; + * Number of active L2 caches. (Not floorswept) + * familyName; + * Family name for the GPU. + * chipName; + * Chip name for the GPU. + * bitsPerRAMEntry; + * Bits per RAM entry. (Need better doc) + * ramBankWidth; + * Width of RAM bank. (Need better doc) + * bitsPerComptagLine; + * Number of bits per compression tag line. + * ramEntriesPerCompCacheLine; + * Number of RAM entries spanned by 1 compression cache line. + * comptagLineSize; + * Size of compression tag line, in Bytes. + * + * Possible status values returned are: + * NV_OK + */ + +#define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO (0x2080133dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS_MESSAGE_ID (0x3DU) + +typedef struct NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS { + NvU32 defaultPageSize; + NvU32 comptagsPerCacheLine; + NvU32 unpackedComptagLinesPerCacheLine; + NvU32 compCacheLineSizePerLTC; + NvU32 unpackedCompCacheLineSizePerLTC; + NvU32 slicesPerLTC; + NvU32 numActiveLTCs; + NvU32 familyName; + NvU32 chipName; + NvU32 bitsPerRAMEntry; + NvU32 ramBankWidth; + NvU32 bitsPerComptagLine; + NvU32 ramEntriesPerCompCacheLine; + NvU32 comptagLineSize; +} NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_SET_RRD + * + * Sets the row-to-row delay on the GPU's FB + * + * Possible status values returned are: + * NV_OK + * Any error code + */ +#define NV2080_CTRL_CMD_FB_SET_RRD (0x2080133eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_RRD_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_SET_RRD_RESET_VALUE (~((NvU32)0)) +#define NV2080_CTRL_FB_SET_RRD_PARAMS_MESSAGE_ID (0x3EU) + +typedef struct NV2080_CTRL_FB_SET_RRD_PARAMS { + NvU32 rrd; +} NV2080_CTRL_FB_SET_RRD_PARAMS; + +/* + * NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS + * + * This is not a control call of it's own, but there are common definitions for + * the two NV2080_CTRL_CMD_FB_SET_READ/WRITE_LIMIT control calls. + */ +typedef struct NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS { + NvU8 limit; +} NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS; +#define NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE (0xffU) + +/* + * NV2080_CTRL_CMD_FB_SET_READ_LIMIT + * + * Sets the READ_LIMIT to be used in the NV_PFB_FBPA_DIR_ARB_CFG0 register + * + * limit + * The limit value to use + * + * Possible status values returned are: + * NV_OK + * Any error code + */ +#define NV2080_CTRL_CMD_FB_SET_READ_LIMIT (0x2080133fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_SET_READ_LIMIT_RESET_VALUE NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE +#define NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS_MESSAGE_ID (0x3FU) + +typedef NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_SET_WRITE_LIMIT + * + * Sets the WRITE_LIMIT to be used in the NV_PFB_FBPA_DIR_ARB_CFG0 register + * + * limit + * The limit value to us + * + * Possible status values returned are: + * NV_OK + * Any error code + */ +#define NV2080_CTRL_CMD_FB_SET_WRITE_LIMIT (0x20801340U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_SET_WRITE_LIMIT_RESET_VALUE NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE +#define NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS_MESSAGE_ID (0x40U) + +typedef NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_PATCH_PBR_FOR_MINING + * + * Patches some VBIOS values related to PBR to better suit mining applications + * + * bEnable + * Set the mining-specific values or reset to the original values + * + * Possible status values returned are: + * NV_OK + * Any error code + */ +#define NV2080_CTRL_CMD_FB_PATCH_PBR_FOR_MINING (0x20801341U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS_MESSAGE_ID (0x41U) + +typedef struct NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS { + NvBool bEnable; +} NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT + * + * Get memory alignment. Replacement for NVOS32_FUNCTION_GET_MEM_ALIGNMENT + */ +#define NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT (0x20801342U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID (0x42U) + +typedef struct NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS { + NvU32 alignType; // Input + NvU32 alignAttr; + NvU32 alignInputFlags; + NvU32 alignHead; + NV_DECLARE_ALIGNED(NvU64 alignSize, 8); + NvU32 alignHeight; + NvU32 alignWidth; + NvU32 alignPitch; + NvU32 alignPad; + NvU32 alignMask; + NvU32 alignKind; + NvU32 alignAdjust; // Output -- If non-zero the amount we need to adjust the offset + NvU32 alignAttr2; +} NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_GET_CBC_BASEADDR + * + * Get the CBC Base physical address + * This control call is required by error containment tests + * NV2080_CTRL_CMD_FB_GET_AMAP_CONF can also return CBC base address + * but it requires kernel privilege, and it not callalble from SRT test + * + * @params[out] NvU64 cbcBaseAddr + * Base physical address for CBC data. + * + * Possible status values returned are: + * NV_OK NV_ERR_NOT_SUPPORTED + * + */ +#define NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR (0x20801343U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS_MESSAGE_ID (0x43U) + +typedef struct NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS { + NvU32 cbcBaseAddress; + NvU32 compCacheLineSize; + NV_DECLARE_ALIGNED(NvU64 backingStoreStartPA, 8); + NV_DECLARE_ALIGNED(NvU64 backingStoreAllocPA, 8); + NvU32 backingStoreChunkOverfetch; +} NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS; + +#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING 0:0 +#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE 0U +#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE 1U +#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_ACTIVE 1:1 +#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_ACTIVE_FALSE 0U +#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_ACTIVE_TRUE 1U + + + +typedef struct NV2080_CTRL_FB_ROW_REMAP_ENTRY { + NvU32 remapRegVal; + NvU32 timestamp; + NvU8 fbpa; + NvU8 sublocation; + NvU8 source; + NvU8 flags; +} NV2080_CTRL_FB_ROW_REMAP_ENTRY; + +/* valid values for source */ + + +#define NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_SBE_FIELD (0x00000002U) +#define NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_DBE_FIELD (0x00000003U) + +#define NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS (0x00000200U) + +/* + * NV2080_CTRL_CMD_FB_GET_REMAPPED_ROWS + * + * This command returns the list of remapped rows stored in the Inforom. + * + * entryCount + * This output parameter specifies the number of remapped rows + * flags + * This output parameter contains info on whether or not there are pending + * remappings and whether or not a remapping failed + * entries + * This output parameter is an array of NV2080_CTRL_FB_REMAP_ENTRY + * containing inforomation on the remapping that occurred. This array can + * hold a maximum of NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_POINTER + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_GET_REMAPPED_ROWS (0x20801344U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING \ + NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING +#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_FALSE NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE +#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_TRUE NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE +#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE 1:1 +#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_FALSE 0U +#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_TRUE 1U + +#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS_MESSAGE_ID (0x44U) + +typedef struct NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS { + NvU32 entryCount; + NvU8 flags; + NV2080_CTRL_FB_ROW_REMAP_ENTRY entries[NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS]; +} NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS; + +// Max size of the queryParams in Bytes, so that the NV2080_CTRL_FB_FS_INFO_QUERY struct is still 32B +#define NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE 24U + +/*! + * Structure holding the out params for NV2080_CTRL_FB_FS_INFO_INVALID_QUERY. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS { + // Unused param, will ensure the size of NV2080_CTRL_FB_FS_INFO_QUERY struct to be 32B + NvU8 data[NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE]; +} NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_FBP_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS { + /*! + * [in]: swizzId + * PartitionID associated with a created smc partition. Currently used only for a + * device monitoring client to get the physical values of the FB. The client needs to pass + * 'NV2080_CTRL_GPU_PARTITION_ID_INVALID' explicitly if it wants RM to ignore the swizzId. + * RM will consider this request similar to a legacy case. + * The client's subscription is used only as a capability check and not as an input swizzId. + */ + NvU32 swizzId; + /*! + * [out]: physical/local fbp mask. + */ + NV_DECLARE_ALIGNED(NvU64 fbpEnMask, 8); +} NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_LTC_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS { + /*! + * [in]: physical/local FB partition index. + */ + NvU32 fbpIndex; + /*! + * [out]: physical/local ltc mask. + */ + NvU32 ltcEnMask; +} NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_LTS_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS { + /*! + * [in]: physical/local FB partition index. + */ + NvU32 fbpIndex; + /*! + * [out]: physical/local lts mask. + * Note that lts bits are flattened out for all ltc with in a fbp. + */ + NvU32 ltsEnMask; +} NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_FBPA_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS { + /*! + * [in]: physical/local FB partition index. + */ + NvU32 fbpIndex; + /*! + * [out]: physical/local FBPA mask. + */ + NvU32 fbpaEnMask; +} NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS { + /*! + * [in]: physical/local FB partition index. + */ + NvU32 fbpIndex; + /*! + * [out]: physical/local FBPA-SubPartition mask. + */ + NvU32 fbpaSubpEnMask; +} NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP + */ +typedef struct NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS { + /*! + * [in]: physical/local FB partition index. + */ + NvU32 fbpIndex; + /*! + * [out]: Logical/local FBP index + */ + NvU32 fbpLogicalIndex; +} NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_ROP_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS { + /*! + * [in]: physical/local FB partition index. + */ + NvU32 fbpIndex; + /*! + * [out]: physical/local ROP mask. + */ + NvU32 ropEnMask; +} NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_SYS_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_SYS_MASK_PARAMS { + /*! + * [in]: swizzId + * PartitionID associated with a created smc partition. Currently used only for a + * device monitoring client to get the physical values of the sys. The client needs to pass + * 'NV2080_CTRL_GPU_PARTITION_ID_INVALID' explicitly if it wants RM to ignore the swizzId. + * RM will consider this request similar to a legacy case. + */ + NvU32 swizzId; + /*! + * [out]: physical/local sys mask. + */ + NV_DECLARE_ALIGNED(NvU64 sysEnMask, 8); +} NV2080_CTRL_FB_FS_INFO_SYS_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS { + /*! + * [in]: Physical FB partition index. + */ + NvU32 fbpIndex; + /*! + * [in]: swizzId + * PartitionID associated with a created smc partition. + */ + NvU32 swizzId; + /*! + * [out]: physical ltc mask. + */ + NvU32 ltcEnMask; +} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS { + /*! + * [in]: Physical FB partition index. + */ + NvU32 fbpIndex; + /*! + * [in]: swizzId + * PartitionID associated with a created smc partition. + */ + NvU32 swizzId; + /*! + * [out]: physical lts mask. + */ + NvU32 ltsEnMask; +} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS { + /*! + * [in]: Physical FB partition index. + */ + NvU32 fbpIndex; + /*! + * [in]: swizzId + * PartitionID associated with a created smc partition. + */ + NvU32 swizzId; + /*! + * [out]: physical fbpa mask. + */ + NvU32 fbpaEnMask; +} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS { + /*! + * [in]: Physical FB partition index. + */ + NvU32 fbpIndex; + /*! + * [in]: swizzId + * PartitionID associated with a created smc partition. + */ + NvU32 swizzId; + /*! + * [out]: physical rop mask. + */ + NvU32 ropEnMask; +} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS { + /*! + * [in]: Physical FB partition index. + */ + NvU32 fbpIndex; + /*! + * [in]: swizzId + * PartitionID associated with a created smc partition. Currently used only for a + * device monitoring client to get the physical values of the FB. The client needs to pass + * 'NV2080_CTRL_GPU_PARTITION_ID_INVALID' explicitly if it wants RM to ignore the swizzId. + * RM will consider this request similar to a legacy case. + * The client's subscription is used only as a capability check and not as an input swizzId. + */ + NvU32 swizzId; + /*! + * [out]: physical FBPA_SubPartition mask associated with requested partition. + */ + NV_DECLARE_ALIGNED(NvU64 fbpaSubpEnMask, 8); +} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK. + */ +typedef struct NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS { + /*! + * [in]: physical/local sys Id. + */ + NvU32 sysIdx; + /*! + * [out]: physical/local sysltc mask. + */ + NvU32 sysl2LtcEnMask; +} NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK. + */ +typedef struct NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS { + /*! + * [IN]: physical/local SYS index. + */ + NvU32 sysIdx; + /*! + * [OUT]: physical/local lts mask. + * Note: this lts mask should be flattened out within a sys chiplet + */ + NV_DECLARE_ALIGNED(NvU64 sysl2LtsEnMask, 8); +} NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PAC_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS { + /*! + * [in]: physical/local FB partition index. + */ + NvU32 fbpIndex; + /*! + * [out]: physical/local PAC mask. + */ + NvU32 pacEnMask; +} NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS { + /*! + * [in]: physical/local FB partition index. + */ + NvU32 fbpIndex; + /*! + * [out]: logical/local ltc mask. + */ + NV_DECLARE_ALIGNED(NvU64 logicalLtcEnMask, 8); +} NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS { + /*! + * [in]: Physical FB partition index. + */ + NvU32 fbpIndex; + /*! + * [in]: swizzId + * PartitionID associated with a created smc partition. + */ + NvU32 swizzId; + /*! + * [out]: logical ltc mask. + */ + NV_DECLARE_ALIGNED(NvU64 logicalLtcEnMask, 8); +} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS; + +// Possible values for queryType +#define NV2080_CTRL_FB_FS_INFO_INVALID_QUERY 0x0U +#define NV2080_CTRL_FB_FS_INFO_FBP_MASK 0x1U +#define NV2080_CTRL_FB_FS_INFO_LTC_MASK 0x2U +#define NV2080_CTRL_FB_FS_INFO_LTS_MASK 0x3U +#define NV2080_CTRL_FB_FS_INFO_FBPA_MASK 0x4U +#define NV2080_CTRL_FB_FS_INFO_ROP_MASK 0x5U +#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK 0x6U +#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK 0x7U +#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK 0x8U +#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK 0x9U +#define NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK 0xAU +#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK 0xBU +#define NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP 0xCU +#define NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK 0xDU +#define NV2080_CTRL_FB_FS_INFO_PAC_MASK 0xEU +#define NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK 0xFU +#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK 0x10U +#define NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK 0x11U +#define NV2080_CTRL_FB_FS_INFO_SYS_MASK 0x12U + +typedef struct NV2080_CTRL_FB_FS_INFO_QUERY { + NvU16 queryType; + NvU8 reserved[2]; + NvU32 status; + union { + NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS inv; + NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS fbp, 8); + NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS ltc; + NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS lts; + NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS fbpa; + NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS rop; + NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS dmLtc; + NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS dmLts; + NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS dmFbpa; + NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS dmRop; + NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS dmFbpaSubp, 8); + NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS fbpaSubp; + NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS fbpLogicalMap; + NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS sysl2Ltc; + NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS pac; + NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS logicalLtc, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS dmLogicalLtc, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS sysl2Lts, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_SYS_MASK_PARAMS sys, 8); + } queryParams; +} NV2080_CTRL_FB_FS_INFO_QUERY; + +// Max number of queries that can be batched in a single call to NV2080_CTRL_CMD_FB_GET_FS_INFO +#define NV2080_CTRL_FB_FS_INFO_MAX_QUERIES 120U + +#define NV2080_CTRL_FB_GET_FS_INFO_PARAMS_MESSAGE_ID (0x46U) + +typedef struct NV2080_CTRL_FB_GET_FS_INFO_PARAMS { + NvU16 numQueries; + NvU8 reserved[6]; + NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_QUERY queries[NV2080_CTRL_FB_FS_INFO_MAX_QUERIES], 8); +} NV2080_CTRL_FB_GET_FS_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_GET_FS_INFO + * + * This control call returns the fb engine information for a partition/GPU. + * Supports an interface so that the caller can issue multiple queries by batching them + * in a single call. Returns the first error it encounters. + * + * numQueries[IN] + * - Specifies the number of valid queries. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_GET_FS_INFO (0x20801346U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_FS_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_HISTOGRAM_IDX_NO_REMAPPED_ROWS (0x0U) +#define NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAPPED_ROW (0x1U) +#define NV2080_CTRL_FB_HISTOGRAM_IDX_MIXED_REMAPPED_REMAINING_ROWS (0x2U) +#define NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAINING_ROW (0x3U) +#define NV2080_CTRL_FB_HISTOGRAM_IDX_MAX_REMAPPED_ROWS (0x4U) + +#define NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS_MESSAGE_ID (0x47U) + +typedef struct NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS { + NvU32 histogram[5]; +} NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM + * + * This control call returns stats on the number of banks that have a certain + * number of rows remapped in the bank. Specifically the number of banks that + * have 0, 1, 2 through (max-2), max-1 and max number of rows remapped in the + * bank. Values will be returned in an array. + * + * Index values are: + * + * NV2080_CTRL_FB_HISTOGRAM_IDX_NO_REMAPPED_ROWS + * Number of banks with zero rows remapped + NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAPPED_ROW + * Number of banks with one row remapped + NV2080_CTRL_FB_HISTOGRAM_IDX_MIXED_REMAPPED_REMAINING_ROWS + * Number of banks with 2 through (max-2) rows remapped + NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAINING_ROW + * Number of banks with (max-1) rows remapped + NV2080_CTRL_FB_HISTOGRAM_IDX_MAX_REMAPPED_ROWS + * Number of banks with max rows remapped + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM (0x20801347U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_FB_GET_DYNAMICALLY_BLACKLISTED_PAGES + * + * This command returns the list of dynamically blacklisted video memory page addresses + * after last driver load. + * + * blackList + * This output parameter is an array of NV2080_CTRL_FB_DYNAMIC_BLACKLIST_ADDRESS_INFO + * This array can hold a maximum of NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES. + * validEntries + * This output parameter specifies the number of valid entries in the + * blackList array. + * baseIndex + * With the limit of up to 512 blacklisted pages, the size of this array + * exceeds the rpc buffer limit. This control call will collect the data + * in multiple passes. This parameter indicates the start index of the + * data to be passed back to the caller + * This cannot be greater than NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES + * bMore + * This parameter indicates whether there are more valid elements to be + * fetched. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_FB_GET_DYNAMIC_OFFLINED_PAGES (0x20801348U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */ + +/* Maximum pages that can be dynamically blacklisted */ +#define NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES 512U + +/* + * Maximum entries that can be sent in a single pass of + * NV2080_CTRL_CMD_FB_GET_DYNAMIC_OFFLINED_PAGES + */ +#define NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES 64U + +/** + * NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO + * pageNumber + * This output parameter specifies the dynamically blacklisted page number. + * source + * The reason for the page to be retired. Valid values for + * this parameter include: + * NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_INVALID + * Invalid source. + * NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE + * Page retired by dynamic page retirement due to a double bit + * error seen. + */ +typedef struct NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO { + NV_DECLARE_ALIGNED(NvU64 pageNumber, 8); + NvU8 source; +} NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO; + +#define NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_MESSAGE_ID (0x48U) + +typedef struct NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO offlined[NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES], 8); + NvU32 validEntries; + NvU32 baseIndex; + NvBool bMore; +} NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS; + +/* valid values for source */ + +#define NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_INVALID (0x00000000U) +#define NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_DPR_DBE (0x00000001U) + +/* + * NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO + * + * This control command is used by clients to query information pertaining to client allocations. + * + * + * @params [IN/OUT] NvU64 allocCount: + * Client specifies the allocation count that it received using the + * previous NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO control call. + * RM will get the total number of allocations known by RM and fill + * allocCount with it. + * + * @params [IN] NvP64 pAllocInfo: + * Pointer to the buffer allocated by client of size NV2080_CTRL_CMD_FB_ALLOCATION_INFO * + * allocCount. RM returns the info pertaining to each of the contiguous client + * allocation chunks in pAllocInfo. The format of the allocation information is given by + * NV2080_CTRL_CMD_FB_ALLOCATION_INFO. The client has to sort the returned information if + * it wants to retain the legacy behavior of SORTED BY OFFSET. Information is only returned + * if and only if allocCount[IN]>=allocCount[OUT] and clientCount[IN]>=clientCount[OUT]. + * + * @params [IN/OUT] NvP64 clientCount: + * Client specifies the client count that it received using the + * previous NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO control call. + * RM will get the total number of clients that have allocations with RM + * and fill clientCount with it. + * + * @params [IN] NvP64 pClientInfo: + * Pointer to the buffer allocated by client of size NV2080_CTRL_CMD_FB_CLIENT_INFO * + * clientCount. RM returns the info pertaining to each of the clients that have allocations + * known about by RM in pClientInfo. The format of the allocation information is given by + * NV2080_CTRL_CMD_FB_CLIENT_INFO. Information is only returned if and only if + * allocCount[IN]>=allocCount[OUT] and clientCount[IN]>=clientCount[OUT]. + * + * @returns Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_POINTER + * NV_ERR_NO_MEMORY + * + * @Usage: All privileged RM clients for debugging only. Initially, call this with allocCount = + * clientCount = 0 to get client count, and then call again with allocated memory and sizes. + * Client can repeat with the new count-sized allocations until a maximum try count is + * reached or client is out of memory. + */ + +#define NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO (0x20801349U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS_MESSAGE_ID" */ + +/* + * These work with the FLD_SET_REF_NUM and FLD_TEST_REF macros and describe the 'flags' member + * of the NV2080_CTRL_CMD_FB_ALLOCATION_INFO struct. + */ + +// Address space of the allocation +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE 4:0 +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_SYSMEM 0U +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_VIDMEM 1U + +// Whether the allocation is shared +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED 5:5 +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_FALSE 0U +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_TRUE 1U + +// Whether this client owns this allocation +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER 6:6 +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_FALSE 0U +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_TRUE 1U + +typedef struct NV2080_CTRL_CMD_FB_ALLOCATION_INFO { + NvU32 client; /* [OUT] Identifies the client that made or shares the allocation (index into pClientInfo)*/ + NvU32 flags; /* [OUT] Flags associated with the allocation (see previous defines) */ + NV_DECLARE_ALIGNED(NvU64 beginAddr, 8); /* [OUT] Starting physical address of the chunk */ + NV_DECLARE_ALIGNED(NvU64 size, 8); /* [OUT] Size of the allocated contiguous chunk in bytes */ +} NV2080_CTRL_CMD_FB_ALLOCATION_INFO; + +typedef struct NV2080_CTRL_CMD_FB_CLIENT_INFO { + NvHandle handle; /* [OUT] Handle of the client that made or shares the allocation */ + NvU32 pid; /* [OUT] PID of the client that made or shares the allocation */ + + /* For the definition of the subprocessID and subprocessName params, see NV0000_CTRL_CMD_SET_SUB_PROCESS_ID */ + NvU32 subProcessID; /* [OUT] Subprocess ID of the client that made or shares the allocation */ + char subProcessName[NV_PROC_NAME_MAX_LENGTH]; /* [OUT] Subprocess Name of the client that made or shares the allocation */ +} NV2080_CTRL_CMD_FB_CLIENT_INFO; + +#define NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS_MESSAGE_ID (0x49U) + +typedef struct NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 allocCount, 8); + NV_DECLARE_ALIGNED(NvP64 pAllocInfo, 8); + NV_DECLARE_ALIGNED(NvU64 clientCount, 8); + NV_DECLARE_ALIGNED(NvP64 pClientInfo, 8); +} NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS + * + * This control command is used by clients to update the NUMA status. + * + * @params [IN] NvBool bOnline: + * + * @returns Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * + */ +#define NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS (0x20801350U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS_MESSAGE_ID (0x50U) + +typedef struct NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS { + NvBool bOnline; +} NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_GET_NUMA_INFO + * + * This control command is used by clients to get per-subdevice or + * subscribed MIG partition(when MIG is enabled) NUMA memory information as + * assigned by the system. + * + * numaNodeId[OUT] + * - Specifies the NUMA node ID. + * + * numaMemAddr[OUT] + * - Specifies the NUMA memory address. + * + * numaMemSize[OUT] + * - Specifies the NUMA memory size. + * + * numaOfflineAddressesCount[IN/OUT] + * - If non-zero, then it specifies the maximum number of entries in + * numaOfflineAddresses[] for which the information is required. + * It will be updated with the actual number of entries present in + * the numaOfflineAddresses[]. + * + * numaOfflineAddresses[OUT] + * - If numaOfflineAddressesCount is non-zero, it contains the addresses + * of offline pages in the NUMA region. + * + * @returns Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_GET_NUMA_INFO (0x20801351U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_NUMA_INFO_MAX_OFFLINE_ADDRESSES 64U + +#define NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS_MESSAGE_ID (0x51U) + +typedef struct NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS { + NvS32 numaNodeId; + NV_DECLARE_ALIGNED(NvU64 numaMemAddr, 8); + NV_DECLARE_ALIGNED(NvU64 numaMemSize, 8); + NvU32 numaOfflineAddressesCount; + NV_DECLARE_ALIGNED(NvU64 numaOfflineAddresses[NV2080_CTRL_FB_NUMA_INFO_MAX_OFFLINE_ADDRESSES], 8); +} NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT + * + * This control command is used by clients to get NV_SEMAPHORE_SURFACE layout/caps before allocation. + * A semaphore surface can be viewed as an array of independent semaphore entries. + * + * maxSubmittedSemaphoreValueOffset[OUT] + * - An offset of the max submitted value, relative to the semaphore surface entry start, if used. + * Used to emulate 64-bit semaphore values on chips where 64-bit semaphores are not supported. + * + * monitoredFenceThresholdOffset[OUT] + * - An offset of the monitored fence memory, relative to the semaphore surface entry start, if supported. + * + * size[OUT] + * - A size of a single semaphore surface entry. + * + * caps[OUT] + * - A mask of NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_* values. + */ +#define NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT (0x20801352U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_MONITORED_FENCE_SUPPORTED (0x00000001U) +#define NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_64BIT_SEMAPHORES_SUPPORTED (0x00000002U) + +#define NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS_MESSAGE_ID (0x52U) + +typedef struct NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS { + NV_DECLARE_ALIGNED(NvU64 maxSubmittedSemaphoreValueOffset, 8); + NV_DECLARE_ALIGNED(NvU64 monitoredFenceThresholdOffset, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 caps; +} NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS; + +/* + * NV2080_CTRL_CMD_GMMU_COMMIT_TLB_INVALIDATE + * + * This control command is used by clients to commit TLB invalidates + * + * gfid[OUT] + * - Specifices GPU function ID. + * + * invalidateAll[OUT] + * - Specifies whether to invalidate all using boolean + * + * @returns Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV2080_CTRL_CMD_GMMU_COMMIT_TLB_INVALIDATE (0x20801353U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS_MESSAGE_ID (0x53U) + +typedef struct NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS { + NvU32 gfid; + NvBool invalidateAll; +} NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS; + +// NV_FB_ALLOC_RM_INTERNAL_OWNER__MAX - NV_FB_ALLOC_RM_INTERNAL_OWNER__MIN // +#define NV2080_CTRL_CMD_FB_STATS_MAX_OWNER 201U + +typedef struct NV2080_CTRL_CMD_FB_STATS_OWNER_INFO { + //! Total allocated size for this owner + NV_DECLARE_ALIGNED(NvU64 allocSize, 8); + + //! Total memory blocks belonging this owner + NvU32 numBlocks; + + //! Total reserved size for this owner + NV_DECLARE_ALIGNED(NvU64 rsvdSize, 8); +} NV2080_CTRL_CMD_FB_STATS_OWNER_INFO; + +#define NV2080_CTRL_CMD_RM_FB_STATS_ENTRY_MESSAGE_ID (0x2AU) + +typedef struct NV2080_CTRL_CMD_RM_FB_STATS_ENTRY { + //! RM reserved heap memory + NV_DECLARE_ALIGNED(NvU64 reservedHeap, 8); + + //! Free RM heap memory (reserved but not allocated) + NV_DECLARE_ALIGNED(NvU64 reservedHeapFree, 8); + + //! RM reserved memory + NV_DECLARE_ALIGNED(NvU64 reserved, 8); + + //! owner info table + NV_DECLARE_ALIGNED(NV2080_CTRL_CMD_FB_STATS_OWNER_INFO fbBlockInfo[NV2080_CTRL_CMD_FB_STATS_MAX_OWNER], 8); +} NV2080_CTRL_CMD_RM_FB_STATS_ENTRY; + + +/* + * NV2080_CTRL_CMD_FB_STATS_GET + * + * Get the FB allocations info from CPU-RM and GSP-RM. + */ +#define NV2080_CTRL_CMD_FB_STATS_GET (0x2080132f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_STATS_GET_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_STATS_GET_PARAMS_MESSAGE_ID (0x2FU) + +typedef struct NV2080_CTRL_CMD_FB_STATS_GET_PARAMS { + //! Total physical memory available (accounts row-remapping) + NV_DECLARE_ALIGNED(NvU64 total, 8); + + //! Total usable memory for OS/KMD + NV_DECLARE_ALIGNED(NvU64 os, 8); + + //! GSP carveout size + NV_DECLARE_ALIGNED(NvU64 gspCarveout, 8); + + //! misc reserved region size (console, vGPU-specific, CBC, etc.) + NV_DECLARE_ALIGNED(NvU64 miscReserved, 8); + + //! CPU-RM sizes info + NV_DECLARE_ALIGNED(NV2080_CTRL_CMD_RM_FB_STATS_ENTRY cpuFbInfo, 8); + + //! GSP-RM sizes info + NV_DECLARE_ALIGNED(NV2080_CTRL_CMD_RM_FB_STATS_ENTRY gspFbInfo, 8); +} NV2080_CTRL_CMD_FB_STATS_GET_PARAMS; + +/* + * NV2080_CTRL_CMD_GSP_FB_STATS_GET + * + * Get the FB allocations info from GSP-RM. + */ +#define NV2080_CTRL_CMD_GSP_FB_STATS_GET (0x2080132a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_RM_FB_STATS_ENTRY_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_FB_GET_STATIC_BAR1_INFO + * + * This command returns the GPU static BAR1 Info + * This is for general P2P DMA. NV50_P2P is for GPU P2P. + * + * @params [OUT] NvBool bStaticBar1Enabled: + * This field indicates the static BAR1 mode is enabled. All the following fields are valid + * only if static BAR1 mode is enabled. + * @params [OUT] NvU64 staticBar1StartOffset: + * Static BAR1 may start at nonzero BAR1 address. + * This field indicates the start offset of the static BAR1. + * @params [OUT] NvU64 staticBar1Size: + * This field indicates the size of the static BAR1. + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_GET_STATIC_BAR1_INFO (0x20801354U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS_MESSAGE_ID (0x54U) + +typedef struct NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS { + NvBool bStaticBar1Enabled; + NvBool bStaticBar1WriteCombined; + NV_DECLARE_ALIGNED(NvU64 staticBar1StartOffset, 8); + NV_DECLARE_ALIGNED(NvU64 staticBar1Size, 8); +} NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION + * + * This command returns the current DRAM encryption configuration + * setting for a GPU given its subdevice handle. The value returned + * is the current DRAM encryption setting for the GPU stored in non-volatile + * memory on the board. + * + * currentConfiguration + * The current DRAM encryption configuration setting. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION (0x20801355U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_DISABLED (0x00000000U) +#define NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_ENABLED (0x00000001U) + +#define NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS_MESSAGE_ID (0x55U) + +typedef struct NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS { + NvU32 currentConfiguration; +} NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_SET_DRAM_ENCRYPTION_CONFIGURATION + * + * This command changes the DRAM encryption configuration setting for + * a GPU given its subdevice handle. The value specified is stored + * in non-volatile memory on the board and will take effect with the + * next GPU reset. + * + * newConfiguration + * The new configuration setting to take effect with + * the next GPU reset. + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_SET_DRAM_ENCRYPTION_CONFIGURATION (0x20801356U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_DISABLE (0x00000000U) +#define NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_ENABLE (0x00000001U) + +#define NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS_MESSAGE_ID (0x56U) + +typedef struct NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS { + NvU32 newConfiguration; +} NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT + * + * This command returns whether or not DRAM encryption config object is supported via the InfoROM. + * + * isSupported [OUT] + * This parameter returns whether the DRAM Encryption inforom object is present in the inforom. + * The various values of isSupported is: + * 1. NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_DISABLED + * 2. NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_ENABLED + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT (0x20801357U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_DISABLED (0x00000000U) +#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_ENABLED (0x00000001U) + +#define NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID (0x57U) + +typedef struct NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS { + NvU32 isSupported; +} NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS + * + * This command returns the current DRAM encryption status. + * + * currentStatus + * The current DRAM encryption status. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS (0x20801358U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_DISABLED (0x00000000U) +#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_ENABLED (0x00000001U) + +#define NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID (0x58U) + +typedef struct NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS { + NvU32 currentStatus; +} NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_GET_MEMORY_BOOT_TRAINING_FLAGS + * + * This command returns the memory boot training flags from VBIOS table. + * + * flagCollectSchmooData + * flagWrTrHybridVrefEn + * flagWrTrHybridNonVrefEn + * flagRdTrHybridVrefEn + * flagRdTrHybridNonVrefEn + * skipBootTraining + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_GET_MEMORY_BOOT_TRAINING_FLAGS (0x20801359U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS_MESSAGE_ID (0x59U) + +typedef struct NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS { + NvBool flagCollectSchmooData; + NvBool flagWrTrHybridVrefEn; + NvBool flagWrTrHybridNonVrefEn; + NvBool flagRdTrHybridVrefEn; + NvBool flagRdTrHybridNonVrefEn; + NvBool skipBootTraining; +} NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS; + +/* + * NV2080_CTRL_FB_CMD_GET_CARVEOUT_REGION_INFO + * + * This command returns the carveout memory region characteristics. + * + * numCarveoutRegions + * Number of valid regions returned in carveoutRegion[]. + * carveoutRegion[].base + * Base address of carveout memory region. + * carveoutRegion[].size + * size of carveout memory region. + * carveoutType + * carveout type for carveout memory region. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_GET_CARVEOUT_REGION_INFO (0x20801360U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE { + NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE_DISPLAY_FRM = 0, + NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE_DISPLAY_FRM_RESERVED = 1, + NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE_UEFI = 2, +} NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE; + +typedef struct NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO { + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE carveoutType; +} NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO; + +#define NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_MAX_ENTRIES 8U + +#define NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS_MESSAGE_ID (0x60U) + +typedef struct NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS { + NvU32 numCarveoutRegions; + NV_DECLARE_ALIGNED(NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO carveoutRegion[NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_MAX_ENTRIES], 8); +} NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS; + +/* valid values for source */ + + +#define NV2080_CTRL_FB_REMAPPED_BANK_SOURCE_FIELD (0x00000002U) + +#define NV2080_CTRL_FB_REMAPPED_BANKS_MAX_BANKS (0x00000200U) + +typedef struct NV2080_CTRL_FB_BANK_REMAP_HISTOGRAM { + NvU32 maxGroupCount; + NvU32 noSpareGroupCount; +} NV2080_CTRL_FB_BANK_REMAP_HISTOGRAM; + +/* + * NV2080_CTRL_CMD_FB_GET_REMAPPED_BANKS + * + * This command returns the list of remapped banks stored in the Inforom. + * + * entryCount + * This output parameter specifies the number of remapped banks + * flags + * This output parameter contains info on whether or not there are pending + * remappings and whether or not a remapping failed + * histogram + * This output parameter contains the group histogram of bank remapper. + * entries + * This output parameter is an array of NV2080_CTRL_FB_BANK_REMAP_ENTRY + * containing inforomation on the remapping that occurred. This array can + * hold a maximum of NV2080_CTRL_FB_REMAPPED_BANKS_MAX_BANKS + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_POINTER + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_GET_REMAPPED_BANKS (0x20801361U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_REMAPPED_BANKS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_REMAPPED_BANKS_FLAGS_PENDING 0:0 +#define NV2080_CTRL_FB_GET_REMAPPED_BANKS_FLAGS_PENDING_FALSE 0U +#define NV2080_CTRL_FB_GET_REMAPPED_BANKS_FLAGS_PENDING_TRUE 1U + +typedef struct NV2080_CTRL_FB_BANK_REMAP_ENTRY { + NvU32 remapRegVal; + NvU32 timestamp; + NvU8 fbpa; + NvU8 channel; + NvU8 pseudoChannel; + NvU8 group; + NvU8 source; + NvU8 flags; +} NV2080_CTRL_FB_BANK_REMAP_ENTRY; + +#define NV2080_CTRL_FB_GET_REMAPPED_BANKS_PARAMS_MESSAGE_ID (0x61U) + +typedef struct NV2080_CTRL_FB_GET_REMAPPED_BANKS_PARAMS { + NvU32 entryCount; + NvU8 flags; + NV2080_CTRL_FB_BANK_REMAP_HISTOGRAM histogram; + NV2080_CTRL_FB_BANK_REMAP_ENTRY entries[NV2080_CTRL_FB_REMAPPED_BANKS_MAX_BANKS]; +} NV2080_CTRL_FB_GET_REMAPPED_BANKS_PARAMS; + +/* + * NV2080_CTRL_CMD_GET_UGPU_MEMORY_INFO + * + * @brief Returns free nonlocalized memory available as well as localizable memory available per uGPU. + * + * @param[out] totalMemory Total memory available for nonlocalized allocations. + * Identical to NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE when PMA is enabled. + * @param[out] freeMemory Free memory available for nonlocalized allocations. + * Identical to NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE when PMA is enabled. + * @param[out] ugpuTotalMemory Array of total memory sizes available for localized allocations per uGPU. + * Analogous to NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE, but relects memory available to each uGPU. + * @param[out] ugpuFreeMemory Array of free memory sizes available for localized allocations per uGPU. + * Analogous to NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE, but relects memory available to each uGPU. + * + * @return NV_OK, NV_ERR_NOT_SUPPORTED if localization is not supported. + */ +#define NV2080_CTRL_CMD_FB_GET_UGPU_MEMORY_INFO (0x20801362U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_UGPU_MEMORY_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_UGPU_MEMORY_INFO_MAX_UGPUS 2U + +#define NV2080_CTRL_FB_GET_UGPU_MEMORY_INFO_PARAMS_MESSAGE_ID (0x62U) + +typedef struct NV2080_CTRL_FB_GET_UGPU_MEMORY_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 totalMemory, 8); + NV_DECLARE_ALIGNED(NvU64 freeMemory, 8); + NV_DECLARE_ALIGNED(NvU64 ugpuTotalMemory[NV2080_CTRL_FB_GET_UGPU_MEMORY_INFO_MAX_UGPUS], 8); + NV_DECLARE_ALIGNED(NvU64 ugpuFreeMemory[NV2080_CTRL_FB_GET_UGPU_MEMORY_INFO_MAX_UGPUS], 8); +} NV2080_CTRL_FB_GET_UGPU_MEMORY_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_GET_CPU_COHERENT_RANGE + * + * This command returns the CPU-coherent FB range. + * Only applicable on self-hosted platforms. + * + * coherentCpuFbBase + * FB offset of the start of the CPU-coherent range + * coherentCpuFbEnd + * FB offset of the end (exclusive) of the CPU-coherent range + */ +#define NV2080_CTRL_CMD_FB_GET_CPU_COHERENT_RANGE (0x20801363U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CPU_COHERENT_RANGE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_CPU_COHERENT_RANGE_PARAMS_MESSAGE_ID (0x63U) + +typedef struct NV2080_CTRL_FB_GET_CPU_COHERENT_RANGE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 coherentCpuFbBase, 8); + NV_DECLARE_ALIGNED(NvU64 coherentCpuFbEnd, 8); +} NV2080_CTRL_FB_GET_CPU_COHERENT_RANGE_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_GET_WPR_REGION_INFO + * + * This command returns information about WPR regions. + * + * wpr1Start + * FB offset of the start of WPR1 + * wpr1End + * FB offset of the end (exclusive) of WPR1 + * wpr2Start + * FB offset of the start of WPR1 + * wpr2End + * FB offset of the end (exclusive) of WPR1 + * fbRegionOfWpr2Start + * FB offset of the start of the FB region (as tracked by RM) that contains WPR2 + */ +#define NV2080_CTRL_CMD_FB_GET_WPR_REGION_INFO (0x20801364U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_WPR_REGION_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_WPR_REGION_INFO_PARAMS_MESSAGE_ID (0x64U) + +typedef struct NV2080_CTRL_FB_GET_WPR_REGION_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 wpr1Start, 8); + NV_DECLARE_ALIGNED(NvU64 wpr1End, 8); + NV_DECLARE_ALIGNED(NvU64 wpr2Start, 8); + NV_DECLARE_ALIGNED(NvU64 wpr2End, 8); + NV_DECLARE_ALIGNED(NvU64 fbRegionOfWpr2Start, 8); +} NV2080_CTRL_FB_GET_WPR_REGION_INFO_PARAMS; + +/* _ctrl2080fb_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fifo.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fifo.h new file mode 100644 index 0000000..e0d6c0a --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fifo.h @@ -0,0 +1,1140 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080fifo.finn +// + +#include "nvcfg_sdk.h" +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* + * NV2080_CTRL_CMD_SET_GPFIFO + * + * This command set the GPFIFO offset and number of entries for a channel + * after it has been allocated. The channel must be idle and not pending, + * otherwise ERROR_IN_USE will be returned. + * + * hChannel + * The handle to the channel. + * base + * The base of the GPFIFO in the channel ctxdma. + * numEntries + * The number of entries in the GPFIFO. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_CHANNEL + * NV_ERR_STATE_IN_USE + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV2080_CTRL_CMD_SET_GPFIFO (0x20801102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_SET_GPFIFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_SET_GPFIFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_CMD_SET_GPFIFO_PARAMS { + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 base, 8); + NvU32 numEntries; +} NV2080_CTRL_CMD_SET_GPFIFO_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_GET_PHYSICAL_CHANNEL_COUNT + * + * This command returns the maximum number of physical channels available for + * allocation on the current GPU. This may be less than or equal to the total + * number of channels supported by the current hardware. + * + * physChannelCount + * This output parameter contains the maximum physical channel count. + * + * physChannelCountInUse + * This output parameter contains the number of physical channels in use + * + * Possible return status values returned are + * NV_OK + * + */ +#define NV2080_CTRL_CMD_FIFO_GET_PHYSICAL_CHANNEL_COUNT (0x20801108) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS { + NvU32 physChannelCount; + NvU32 physChannelCountInUse; +} NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS; + +/* + * NV2080_CTRL_FIFO_INFO + * + * This structure represents a single 32bit fifo engine value. Clients + * request a particular FIFO engine value by specifying a unique fifo + * information index. + * + * Legal fifo information index values are: + * NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL + * This index can be used to request the amount of instance space + * in kilobytes reserved by the fifo engine. + * NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS + * This index can be used to query the maximum number of channel groups + * that can be allocated on the GPU. + * NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP + * This index can be used to query the maximum number of channels that can + * be allocated in a single channel group. + * NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP + * This index can be used to query the maximum number of subcontext that can + * be allocated in a single channel group. + * NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET + * This index can be used to query the starting offset of the RM + * pre-allocated USERD range in BAR1. This index query is honored only + * on Legacy-vGPU host RM. + * NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE + * This index can be used to query the default timeslice value + * (microseconds) used for a channel or channel group. + * NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE + * This index can be used to query the number of channel groups that are + * already allocated on the GPU. + * NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED + * This index can be used to check if per runlist channel ram is supported, and + * to query the supported number of channels per runlist. + * NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE + * This index can be used to get max channel groups supported per engine/runlist. + * NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE + * This index can be used too get channel groups currently in use per engine/runlist. + * NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT + * This index can be used to query the maximum "lower" subcontext index + * allocated under NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC_PREFER_LOWER. + * Note: Includes subcontext ID 0, which will be allocated last in ASYNC allocation mode. + * + */ +typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FIFO_INFO; + +/* valid fifo info index values */ +#define NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL (0x000000000) +#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS (0x000000001) +#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP (0x000000002) +#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP (0x000000003) +#define NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET (0x000000004) +#define NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE (0x000000005) +#define NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE (0x000000006) +#define NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED (0x000000007) +#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE (0x000000008) +#define NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE (0x000000009) +#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT (0x00000000a) + + +/* set INDEX_MAX to greatest possible index value */ +#define NV2080_CTRL_FIFO_INFO_INDEX_MAX NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT + +#define NV2080_CTRL_FIFO_GET_INFO_USERD_OFFSET_SHIFT (12) + +/* + * NV2080_CTRL_CMD_FIFO_GET_INFO + * + * This command returns fifo engine information for the associated GPU. + * Requests to retrieve fifo information use an array of one or more + * NV2080_CTRL_FIFO_INFO structures. + * + * fifoInfoTblSize + * This field specifies the number of valid entries in the fifoInfoList + * array. This value cannot exceed NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES. + * fifoInfoTbl + * This parameter contains the client's fifo info table into + * which the fifo info values will be transferred by the RM. + * The fifo info table is an array of NV2080_CTRL_FIFO_INFO structures. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FIFO_GET_INFO (0x20801109) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_INFO_PARAMS_MESSAGE_ID" */ + +/* maximum number of NV2080_CTRL_FIFO_INFO entries per request */ +#define NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES (256) + +#define NV2080_CTRL_FIFO_GET_INFO_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_FIFO_GET_INFO_PARAMS { + NvU32 fifoInfoTblSize; + /* + * C form: + * NV2080_CTRL_FIFO_INFO fifoInfoTbl[NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES]; + */ + NV2080_CTRL_FIFO_INFO fifoInfoTbl[NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES]; + NvU32 engineType; +} NV2080_CTRL_FIFO_GET_INFO_PARAMS; + + + +/* + * NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL + * + * This command removes the specified channel from the associated GPU's runlist + * and then initiates RC recovery. If the channel is active it will first be preempted. + * hChannel + * The handle to the channel to be preempted. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_CHANNEL + */ +#define NV2080_CTRL_CMD_FIFO_CHANNEL_PREEMPTIVE_REMOVAL (0x2080110a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS { + NvHandle hChannel; +} NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS + * + * This command will disable or enable scheduling of channels described in the + * list provided. Whether or not the channels are also preempted off the GPU + * can be controlled by bOnlyDisableScheduling. By default channels are preempted + * off the GPU. + * + * bDisable + * This value determines whether to disable or + * enable the set of channels. + * numChannels + * The number of channels to be stopped. + * bOnlyDisableScheduling + * When false and bDisable=NV_TRUE,the call will ensure none of the listed + * channels are running in hardware and will not run until a call with + * bDisable=NV_FALSE is made. When true and bDisable=NV_TRUE, the control + * call will ensure that none of the listed channels can be scheduled on the + * GPU until a call with bDisable=NV_FALSE is made, but will not remove any + * of the listed channels from hardware if they are currently running. When + * bDisable=NV_FALSE this field is ignored. + * bRewindGpPut + * If a channel is being disabled and bRewindGpPut=NV_TRUE, the channel's RAMFC + * will be updated so that GP_PUT is reset to the value of GP_GET. + * hClientList + * An array of NvU32 listing the client handles + * hChannelList + * An array of NvU32 listing the channel handles + * to be stopped. + * pRunlistPreemptEvent + * KEVENT handle for Async HW runlist preemption (unused on preMaxwell) + * When NULL, will revert to synchronous preemption with spinloop + * + * Possible status values returned are: + * NV_OK + * NVOS_INVALID_STATE + */ + +#define NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS (0x2080110b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES (64) + +#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS { + NvBool bDisable; + NvU32 numChannels; + NvBool bOnlyDisableScheduling; + NvBool bRewindGpPut; + NV_DECLARE_ALIGNED(NvP64 pRunlistPreemptEvent, 8); + // C form: NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES] + NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES]; + // C form: NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES] + NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES]; +} NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS; + +#define NV2080_CTRL_FIFO_DISABLE_CHANNEL_FALSE (0x00000000) +#define NV2080_CTRL_FIFO_DISABLE_CHANNEL_TRUE (0x00000001) +#define NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_FALSE (0x00000000) +#define NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_TRUE (0x00000001) + +/* + * NV2080_CTRL_FIFO_MEM_INFO + * + * This structure describes the details of a block of memory. It consists + * of the following fields + * + * aperture + * One of the NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_* values + * base + * Physical base address of the memory + * size + * Size in bytes of the memory +*/ +typedef struct NV2080_CTRL_FIFO_MEM_INFO { + NvU32 aperture; + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); +} NV2080_CTRL_FIFO_MEM_INFO; + +/* + * NV2080_CTRL_FIFO_CHANNEL_MEM_INFO + * + * This structure describes the details of the instance memory, ramfc + * and method buffers a channel. It consists of the following fields + * + * inst + * Structure describing the details of instance memory + * ramfc + * Structure describing the details of ramfc + * methodBuf + * Array of structures describing the details of method buffers + * methodBufCount + * Number of method buffers(one per runqueue) + */ + +// max runqueues +#define NV2080_CTRL_FIFO_GET_CHANNEL_MEM_INFO_MAX_COUNT 0x2 + +typedef struct NV2080_CTRL_FIFO_CHANNEL_MEM_INFO { + NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_MEM_INFO inst, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_MEM_INFO ramfc, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_MEM_INFO methodBuf[NV2080_CTRL_FIFO_GET_CHANNEL_MEM_INFO_MAX_COUNT], 8); + NvU32 methodBufCount; +} NV2080_CTRL_FIFO_CHANNEL_MEM_INFO; + +/* + * NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM + * + * This command returns the memory aperture, physical base address and the + * size of each of the instance memory, cache1 and ramfc of a channel. + * + * hChannel + * The handle to the channel for which the memory information is desired. + * chMemInfo + * A NV2080_CTRL_FIFO_CHANNEL_MEM_INFO structure + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_CHANNEL +*/ + +#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO (0x2080110c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS { + NvHandle hChannel; + NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_CHANNEL_MEM_INFO chMemInfo, 8); +} NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS; + +#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_INVALID 0x00000000 +#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_VIDMEM 0x00000001 +#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_COH 0x00000002 +#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_NCOH 0x00000003 + +/* + * NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION + * + * This command determines the location (vidmem/sysmem) + * and attribute (cached/uncached/write combined) of memory where USERD is located. + * + * aperture + * One of the NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_* values. + * + * attribute + * One of the NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_* values. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_POINTER +*/ + +#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION (0x2080110d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS { + NvU32 aperture; + NvU32 attribute; +} NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS; + +// support for CPU coherent vidmem (VIDMEM_NVILINK_COH) is not yet available in RM + +#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_VIDMEM 0x00000000 +#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_SYSMEM 0x00000001 + +#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_CACHED 0x00000000 +#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_UNCACHED 0X00000001 +#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_WRITECOMBINED 0X00000002 + + +#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_UNKNOWN 0 +#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_OTHER 1 +#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_BEST_EFFORT 2 +#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_EQUAL_SHARE 3 +#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_FIXED_SHARE 4 + +// Count of the supported vGPU scheduler policies +#define NV2080_CTRL_CMD_SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT 3 + +#define NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DEFAULT 0 +#define NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DISABLE 1 +#define NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_ENABLE 2 + +/* + * NV2080_CTRL_CMD_FIFO_OBJSCHED_SW_GET_LOG + * + * This command returns the OBJSCHED_SW log enties. + * + * engineId + * This field specifies the NV2080_ENGINE_TYPE_* engine whose SW runlist log + * entries are to be fetched. + * + * count + * This field returns the count of log entries fetched. + * + * entry + * The array of SW runlist log entries. + * + * timestampNs + * Timestamp in ns when this SW runlist was preeempted. + * + * timeRunTotalNs + * Total time in ns this SW runlist has run as compared to others. + * + * timeRunNs + * Time in ns this SW runlist ran before preemption. + * + * swrlId + * SW runlist Id. + * + * schedPolicy + * This field returns the runlist scheduling policy. It specifies the + * NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy. + * + * arrEnabled + * This field returns if Adaptive round robin scheduler + * is enabled/disabled. + * + * arrAvgFactor + * This field returns the average factor to be used in compensating the timeslice + * for Adaptive scheduler mode. + * + * targetTimesliceNs + * This field returns the target timeslice duration in ns for each SW runlist + * as configured by the user or the default value otherwise. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT +*/ + +#define NV2080_CTRL_CMD_FIFO_OBJSCHED_SW_GET_LOG (0x2080110e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_OBJSCHED_SW_COUNT 32 +#define NV2080_CTRL_FIFO_OBJSCHED_SW_NCOUNTERS 8 +#define NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRIES 200 + +typedef struct NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRY { + NV_DECLARE_ALIGNED(NvU64 timestampNs, 8); + NV_DECLARE_ALIGNED(NvS64 timeRunTotalNs, 8); + NvU32 timeRunNs; + NvU32 swrlId; + NvU32 targetTimeSlice; + NV_DECLARE_ALIGNED(NvU64 cumulativePreemptionTime, 8); + NV_DECLARE_ALIGNED(NvU64 cumulativeIdleTime, 8); + NvU32 weight; + NV_DECLARE_ALIGNED(NvU64 counters[NV2080_CTRL_FIFO_OBJSCHED_SW_NCOUNTERS], 8); +} NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRY; + +#define NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS { + NvU32 engineId; + NvU32 count; + NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRY entry[NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRIES], 8); + NvU32 schedPolicy; + NvU32 arrEnabled; + NvU32 arrAvgFactor; + NvU32 targetTimesliceNs; +} NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS; + + + + +/* + * NV2080_CTRL_CMD_FIFO_CONFIG_CTXSW_TIMEOUT + * + * This command can be used to enable and set the engine + * context switch timeout + * + * timeout: Timeout in number of microsec PTIMER ticks + * 1 microsec PTIMER tick = 1024 PTIMER nanoseconds + * bEnable: TRUE/FALSE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT +*/ + +#define NV2080_CTRL_CMD_FIFO_CONFIG_CTXSW_TIMEOUT (0x20801110) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_CONFIG_CTXSW_TIMEOUT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_CONFIG_CTXSW_TIMEOUT_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV2080_CTRL_FIFO_CONFIG_CTXSW_TIMEOUT_PARAMS { + NvU32 timeout; + NvBool bEnable; +} NV2080_CTRL_FIFO_CONFIG_CTXSW_TIMEOUT_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE + * + * This command retrieves entries from the SW encoded GPU device info table + * from Host RM. + * + * Parameters: + * + * baseIndex [in] + * The starting index to read from the devinfo table. Must be a multiple of + * MAX_ENTRIES. + * + * entries [out] + * A buffer to store up to MAX_ENTRIES entries of the devinfo table. + * + * numEntries [out] + * Number of populated entries in the provided buffer. + * + * bMore [out] + * A boolean flag indicating whether more valid entries are available to be + * read. A value of NV_TRUE indicates that a further call to this control + * with baseIndex incremented by MAX_ENTRIES will yield further valid data. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE (0x20801112) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_DEVICES 256 +#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES 32 +#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES 16 +#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA 2 +#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN 16 + +/* + * NV2080_CTRL_FIFO_DEVICE_ENTRY + * + * This structure contains the engine, engine name and + * push buffers information of FIFO device entry. It consists of the following fields + * + * engineData + * Type of the engine + * pbdmaIds + * List of pbdma ids associated with engine + * pbdmaFaultIds + * List of pbdma fault ids associated with engine + * numPbdmas + * Number of pbdmas + * engineName + * Name of the engine + */ +typedef struct NV2080_CTRL_FIFO_DEVICE_ENTRY { + NvU32 engineData[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES]; + NvU32 pbdmaIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA]; + NvU32 pbdmaFaultIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA]; + NvU32 numPbdmas; + char engineName[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN]; +} NV2080_CTRL_FIFO_DEVICE_ENTRY; + +#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS { + NvU32 baseIndex; + NvU32 numEntries; + NvBool bMore; + // C form: NV2080_CTRL_FIFO_DEVICE_ENTRY entries[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES]; + NV2080_CTRL_FIFO_DEVICE_ENTRY entries[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES]; +} NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT + * + * This command clears the ENGINE or PBDMA FAULTED bit and reschedules the faulted channel + * by ringing channel's doorbell + * + * Parameters: + * + * engineType [in] + * The NV2080_ENGINE_TYPE of the engine to which the faulted + * channel is bound. This may be a logical id for guest RM in + * case of SMC. + * + * vChid [in] + * Virtual channel ID on which the fault occurred + * + * faultType [in] + * Whether fault was triggered by engine (_ENGINE_FAULTED) or PBDMA (_PBDMA_FAULTED) + * The value specified must be one of the NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_* values + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT (0x20801113) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_ENGINE 0x00000001 +#define NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_PBDMA 0x00000002 + +#define NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS { + NvU32 engineType; + NvU32 vChid; + NvU32 faultType; +} NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS; + + + +/* + * NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY + * + * Allows clients to set the global scheduling policy for all runlists + * associated to the given subdevice. + * + * Currently, this is only supported for HW runlists. + * + * Since this is a global setting, only privileged clients will be allowed to + * set it. Regular clients will get NV_ERR_INSUFFICIENT_PERMISSIONS error. + * + * Once a certain scheduling policy is set, that policy cannot be changed to a + * different one unless all clients which set it have either restored the policy + * (using the corresponding restore flag) or died. Clients trying to set a + * policy while a different one is locked by another client will get a + * NV_ERR_INVALID_STATE error. + * + * The same client can set a scheduling policy and later change to another one + * only when no other clients have set the same policy. Such sequence will be + * equivalent to restoring the policy in between. + * + * For instance, the following sequence: + * + * 1. Set policy A + * 2. Set policy B + * + * is equivalent to: + * + * 1. Set policy A + * 2. Restore policy + * 3. Set policy B + * + * Parameters: + * + * flags + * This field specifies the operational properties to be applied: + * + * - NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_FALSE + * Try to set the provided 'schedPolicy' scheduling policy. If the + * operation succeeds, other clients will be prevented from setting a + * different scheduling policy until all clients using it have either + * restored it or died. + * + * - NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_TRUE + * Let the scheduler know the client no longer requires the current + * scheduling policy. This may or may not actually change the + * scheduling policy, depending on how many other clients are also + * using the current policy. + * + * The 'schedPolicy' parameter is ignored when this flag is set. + * + * schedPolicy + * One of: + * + * - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_DEFAULT + * Set the default scheduling policy and prevent other clients from + * changing it. + * + * - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED + * This scheduling policy will make channels to be scheduled according + * to their interleave level. See NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL + * description for more details. + * - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM + * This scheduling policy will make channels to be scheduled according + * to their interleave level per WDDM policy. + * See NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL description for more details. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_INVALID_STATE + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY (0x20801115) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS_MESSAGE_ID" */ + +/* schedPolicy values */ +#define NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_DEFAULT 0x0 +#define NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED 0x1 +#define NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM 0x2 + +/* SET_SCHED_POLICY flags */ +#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE 0:0 +#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_FALSE (0x00000000) +#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_TRUE (0x00000001) + +#define NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS { + NvU32 flags; + NvU32 schedPolicy; +} NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_UPDATE_CHANNEL_INFO + * + * This command updates the channel info params for an existing channel + * + * Can be a deferred Api. The control call can be used for migrating a + * + * channel to a new userd and gpfifo + * + * Parameters: + * [in] hClient - Client handle + * [in] hChannel - Channel handle + * [in] hUserdMemory - UserD handle + * [in] gpFifoEntries - Number of Gpfifo Entries + * [in] gpFifoOffset - Gpfifo Virtual Offset + * [in] userdOffset - UserD offset + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FIFO_UPDATE_CHANNEL_INFO (0x20801116) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS { + NvHandle hClient; + NvHandle hChannel; + NvHandle hUserdMemory; + NvU32 gpFifoEntries; + NV_DECLARE_ALIGNED(NvU64 gpFifoOffset, 8); + NV_DECLARE_ALIGNED(NvU64 userdOffset, 8); +} NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS + * + * This command will disable or enable scheduling of all usermode channels. + * + * bDisable + * This value determines whether to disable or enable the usermode channels. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS (0x20801117) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS_MESSAGE_ID (0x17U) + +typedef struct NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS { + NvBool bDisable; +} NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB + * + * When a VF subcontext is marked as a zombie, host RM points its PDB to a dummy + * page allocated by guest RM in GPA space. This command provides the parameters + * of the guest RMs memory descriptor to be able to create a corresponding + * memory descriptor on the host RM. Host RM uses this to program the PDB of a + * zombie subcontext. + * + * Parameters: + * Input parameters to describe the memory descriptor + * [in] base + * [in] size + * [in] addressSpace + * [in] cacheAttrib + */ +#define NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB (0x20801118) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS { + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 addressSpace; + NvU32 cacheAttrib; +} NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_GET_ALLOCATED_CHANNELS + * + * Get's a bitmask of allocated channels. No guarantees are made about + * synchronization. A channel returned as allocated by this ctrl cmd might have + * already been destructed. + * + * Parameters: + * [in] runlistId + * [in,out] bitMask A 1 bit indicates that a channel with this index/id is + * allocated. This field is a multiple of 32 bits and each 32 + * bit group must be accessed as a platform 32 bit int to + * correctly map channel IDs. + * + */ +#define NV2080_CTRL_CMD_FIFO_GET_ALLOCATED_CHANNELS (0x20801119) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS_MESSAGE_ID" */ + +/* + * The maximum number than can be returned by + * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS + */ +#define NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS 4096 + +#define NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS { + NvU32 runlistId; + NvU32 bitMask[NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS / 32]; +} NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION + * + * This command will disable and preempt channels described in the + * list provided and mark them ready for key rotation. + * hClient <-> hChannel pairs should use the same index in the arrays. + * + * numChannels + * The number of valid entries in hChannelList array. + * hClientList + * An array of NvHandle listing the client handles + * hChannelList + * An array of NvHandle listing the channel handles + * to be stopped. + * bEnableAfterKeyRotation + * This determines if channel is enabled by RM after it completes key rotation. + * Possible status values returned are: + * NV_OK + * NVOS_INVALID_STATE + */ +#define NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION (0x2080111a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES (64) + +#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID (0x1AU) + +typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS { + NvU32 numChannels; + NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES]; + NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES]; + NvBool bEnableAfterKeyRotation; +} NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2 + * + * This command does the same thing as @ref NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION. + * The difference is that it doesn't take a list of clients and instead all channels belong + * to the client on which this control call is made. + * + * numChannels + * The number of valid entries in hChannelList array. + * hChannelList + * An array of NvHandle listing the channel handles + * to be stopped. + * bEnableAfterKeyRotation + * This determines if channel is enabled by RM after it completes key rotation. + * Possible status values returned are: + * NV_OK + * NVOS_INVALID_STATE + */ +#define NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2 (0x2080111b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS_MESSAGE_ID (0x1BU) + +typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS { + NvU32 numChannels; + NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES]; + NvBool bEnableAfterKeyRotation; +} NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_ROTATE_KEYS + * + * This command will disable and preempt channels described in the + * list provided and force key rotation on these channels. + * hClient <-> hChannel pairs should use the same index in the arrays. + * This control call is only for Blackwell and newer GPUs. + * + * numChannels + * The number of valid entries in hChannelList array. + * hClientList + * An array of NvHandle listing the client handles + * hChannelList + * An array of NvHandle listing the channel handles + * to be stopped. + * bEnableAfterKeyRotation + * This determines if channel is enabled by RM after it completes key rotation. + * Possible status values returned are: + * NV_OK + * NVOS_INVALID_STATE + */ +#define NV2080_CTRL_CMD_FIFO_ROTATE_KEYS (0x2080111c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_ROTATE_KEYS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FIFO_ROTATE_KEYS_PARAMS_MESSAGE_ID (0x1CU) + +typedef struct NV2080_CTRL_CMD_FIFO_ROTATE_KEYS_PARAMS { + NvU32 numChannels; + NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES]; + NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES]; + NvBool bEnableAfterKeyRotation; +} NV2080_CTRL_CMD_FIFO_ROTATE_KEYS_PARAMS; + + + +/* + * NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_STATE + * + * This command returns the vGPU schedular state. + * + * engineId + * This field specifies the NV2080_ENGINE_TYPE_* engine whose SW runlist log + * entries are to be fetched. + * + * schedPolicy + * This field returns the runlist scheduling policy. It specifies the + * NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy. + * + * arrEnabled + * This field returns if Adaptive round robin scheduler + * is enabled/disabled. + * + * targetTimesliceNs + * This field returns the target timeslice duration in ns for each SW runlist + * as configured by the user or the default value otherwise. + * + * arrAvgFactor + * This field returns the average factor to be used in compensating the timeslice + * for Adaptive scheduler mode. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_STATE (0x20801120) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS { + NvU32 engineId; + NvU32 schedPolicy; + NvU32 arrEnabled; + NvU32 targetTimesliceNs; + NvU32 arrAvgFactor; +} NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_OBJSCHED_SET_STATE + * + * This command set the vGPU schedular state. + * + * engineId + * This field specifies the NV2080_ENGINE_TYPE_* engine. + * + * schedPolicy + * This field sets the runlist scheduling policy. It specifies the + * NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy. + * + * enableArr + * This field sets the Adaptive round robin scheduler + * is enabled/disabled. + * + * timesliceTargetNs + * This field sets the time slice target time in ns. + * + * frequencyForARR + * This field sets the scheduling frequency for Adaptive round robin scheduler mode. + * + * avgFactorForARR + * This field sets the average factor to be used in compensating the timeslice + * for Adaptive scheduler mode. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_STATE + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV2080_CTRL_CMD_FIFO_OBJSCHED_SET_STATE (0x20801121) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS_MESSAGE_ID (0x21U) + +typedef struct NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS { + NvU32 engineId; + NvU32 schedPolicy; + NvU32 enableArr; + NvU32 timesliceTargetNs; + NvU32 frequencyForARR; + NvU32 avgFactorForARR; +} NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_CAPS + * + * This command returns the vGPU schedular capabilities. + * + * engineId [in] + * This field specifies the NV2080_ENGINE_TYPE_* engine whose SW runlist log + * entries are to be fetched. + * + * supportedSchedulers [out] + * This field returns the supported runlist scheduling policies on the device. + * It specifies the NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy. + * + * bIsArrModeSupported [out] + * This field returns if Adaptive scheduler mode is enabled/disabled. + * + * maxTimesliceNs [out] + * This field returns the maximum time slice value in ns. + * + * minTimesliceNs [out] + * This field returns the minimum time slice value in ns. + * + * maxFrequencyForARR [out] + * This field returns the maximum scheduling frequency for + * Adaptive round robin scheduler mode. + * + * minFrequencyForARR [out] + * This field returns the minimum scheduling frequency for + * Adaptive round robin scheduler mode. + * + * maxAvgFactorForARR [out] + * This field returns the maximum average factor in compensating + * the timeslice for Adaptive scheduler mode. + * + * minAvgFactorForARR [out] + * This field returns the minimum average factor in compensating + * the timeslice for Adaptive scheduler mode. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_CAPS (0x20801122) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS { + NvU32 engineId; + NvU32 supportedSchedulers[NV2080_CTRL_CMD_SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT]; + NvBool bIsArrModeSupported; + NvU32 maxTimesliceNs; + NvU32 minTimesliceNs; + NvU32 maxFrequencyForARR; + NvU32 minFrequencyForARR; + NvU32 maxAvgFactorForARR; + NvU32 minAvgFactorForARR; +} NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS; + +// Max channels per group is limited by NV_RAMRL_ENTRY_TSG_LENGTH_MAX for the arch. +#define NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG 128 + +/* + * NV2080_CTRL_CMD_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO + * hClient + * Input parameter + * This parameter specifies the client handle associated input channel/TSG + * hChannelOrTsg + * Input parameter. + * This parameter specifies the handle of input channel handle (or channel + * group) + * tsgId + * Output parameter. + * This field return the Unique of TSG object if user specified a channel group handle + * with hChannelOrTsg. + * numChannels + * Output parameter. + * This field return the number of channels under TSG if user specify a + * channel group handle or return 1 if user specify a channel handle. + * channelUniqueID + * Output parameter. + * This array field returns unique Channel ID for each channel. + * vasUniqueID + * Output parameter. + * This array field returns unique IDs of VA Space objects of channels under TSG or channel. + * veid + * Output parameter. + * This array field returns VEID for channels under TSG or channel. + */ +#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO (0x20801123) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS_MESSAGE_ID (0x23U) + +typedef struct NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS { + NvHandle hClient; + NvHandle hChannelOrTsg; + NvU32 tsgId; + NvU32 numChannels; + NvU32 channelUniqueID[NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG]; + NvU32 vasUniqueID[NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG]; + NvU32 veid[NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG]; +} NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_QUERY_CHANNEL_UNIQUE_ID + * This command is used query the CID (channel ID) in batch + * hClients + * Input parameter + * Array of Client handles + * hChannels + * Input parameter + * Array of Channel handles + * numChannels + * Indicates the number of input client, channel handle pairs. + * channelUniqueIDs + * Output parameter. + * This parameter returns an array of unique Channel IDs for each input pair. + * channel handles. + */ +#define NV2080_CTRL_CMD_FIFO_QUERY_CHANNEL_UNIQUE_ID (0x20801124) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS_MESSAGE_ID (0x24U) + +typedef struct NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS { + NvHandle hClients[NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG]; + NvHandle hChannels[NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG]; + NvU32 numChannels; + NvU32 channelUniqueIDs[NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG]; +} NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS; +/* _ctrl2080fifo_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fla.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fla.h new file mode 100644 index 0000000..1f0c86a --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fla.h @@ -0,0 +1,208 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080fla.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX FLA control commands and parameters */ + +/* + * NV2080_CTRL_CMD_FLA_RANGE + * + * This command is used to initialize/destroy FLA VAS for a GPU.This is intended + * to be used by RM clients that manages the FLA VASpace range. The mode of the + * command is decided based on the parameter passed by the client. + * + * base + * This parameter specifies the base of the FLA VAS that needs to be allocated + * for this GPU + * + * size + * This parameter specifies the size of the FLA VAS that needs to be allocated + * for this GPU + * + * mode + * This parameter specifies the functionality of the command. + * MODE_INITIALIZE + * Setting this mode, will initialize the FLA VASpace for the gpu with + * base and size passed as arguments. FLA VASpace will be owned by RM. + * if the client calls the command more than once before destroying + * the FLA VAS, then this command will verify the range exported before and + * return success if it matches. If FLA is not supported for the platform, + * will return NV_ERR_NOT_SUPPORTED. + * MODE_DESTROY (deprecated) + * This command is NOP. + * MODE_HOST_MANAGED_VAS_INITIALIZE + * This mode will initialize the FLA VASpace for the gpu with hVASpace + * handle in addition to base and size arguments. FLA VASpace will be initiated + * and owned by guest RM. Used only in virtualization platforms by internal clients. + * MODE_HOST_MANAGED_VAS_DESTROY + * This mode will destroy the FLA VAS associated with the device. It will destruct + * only the resources associated with host RM side. Used only in virtualization platforms + * by internal clients. + * + * hVASpace + * This paramete specifies the FLA VAspace that needs to be associated with + * device. This parameter takes effect only for internal client in virtualization + * platforms. For any other platform and external clients, this parameter has no effect. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_IN_USE + * NV_ERR_INVALID_OWNER + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_FLA_RANGE (0x20803501) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_RANGE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLA_RANGE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_FLA_RANGE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 mode; + NvHandle hVASpace; +} NV2080_CTRL_FLA_RANGE_PARAMS; + +#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_NONE 0x00000000 +#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_INITIALIZE NVBIT(0) +#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_DESTROY NVBIT(1) +#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_INITIALIZE NVBIT(2) +#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_DESTROY NVBIT(3) + + +/* + * NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK + * + * This command is used to (un)bind FLA Instance Memory Block(IMB) with MMU. + * This control call is created for vGPU platform, when a FLA VAS is created/destroyed + * by Guest RM. Guest RM doesn't have privilege to (un)bind the IMB with MMU, hence + * need to be RPC-ed to Host RM to (un)bind + * The mode of the command is decided based on the actionParam passed by the client. + * + * imbPhysAddr + * This parameter specifies the FLA Instance Memory Block PA to be programmed + * to MMU. IMB address should be 4k aligned. This parameter is needed only + * for ACTION_BIND. + * + * addrSpace + * This parameter specifies the address space of FLA Instance Memory Block. This + * parmater is needed only for ACTION_BIND. + * Available options are: + * NV2080_CTRL_FLA_ADDRSPACE_SYSMEM + * Clients need to use this address space if the IMB is located in sysmem + * NV2080_CTRL_FLA_ADDRSPACE_FBMEM + * Clients need to use this address space if the IMB is located in FB + * + * actionParam + * This parameter specifies the functionality of the command. + * NV2080_CTRL_FLA_ACTION_BIND + * Setting this type, will call busBindFla helper HAL + * NV2080_CTRL_FLA_ACTION_UNBIND + * Setting this type, will call busUnbindFla helper HAL + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +typedef enum NV2080_CTRL_FLA_ADDRSPACE { + NV2080_CTRL_FLA_ADDRSPACE_SYSMEM = 0, + NV2080_CTRL_FLA_ADDRSPACE_FBMEM = 1, +} NV2080_CTRL_FLA_ADDRSPACE; + +typedef enum NV2080_CTRL_FLA_ACTION { + NV2080_CTRL_FLA_ACTION_BIND = 0, + NV2080_CTRL_FLA_ACTION_UNBIND = 1, +} NV2080_CTRL_FLA_ACTION; + +#define NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK (0x20803502) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS { + NV_DECLARE_ALIGNED(NvU64 imbPhysAddr, 8); + NV2080_CTRL_FLA_ADDRSPACE addrSpace; + NV2080_CTRL_FLA_ACTION flaAction; +} NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS; + + +/* + * NV2080_CTRL_CMD_FLA_GET_RANGE + * + * This command is used to query the FLA base and size from plugin to return as static info to Guest RM. + * + * base + * This parameter returns the base address of FLA range registered to the subdevice. + * size + * This parameter returns the size of FLA range registered to the subdevice. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FLA_GET_RANGE (0x20803503) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_GET_RANGE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLA_GET_RANGE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_FLA_GET_RANGE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); +} NV2080_CTRL_FLA_GET_RANGE_PARAMS; + +/* + * NV2080_CTRL_CMD_FLA_GET_FABRIC_MEM_STATS + * + * This command returns the total size and the free size of the fabric vaspace. + * Note: This returns the information for the FABRIC_VASPACE_A class. + * + * totalSize[OUT] + * - Total fabric vaspace. + * + * freeSize [OUT] + * - Available fabric vaspace. + * + * Possible status values returned are: + * + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FLA_GET_FABRIC_MEM_STATS (0x20803504) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 totalSize, 8); + NV_DECLARE_ALIGNED(NvU64 freeSize, 8); +} NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS; + +// _ctrl2080fla_h_ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080flcn.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080flcn.h new file mode 100644 index 0000000..9dd4266 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080flcn.h @@ -0,0 +1,454 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080flcn.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + + + + +// +// XAPICHK/XAPI_TEST breaks on including "nvmisc.h". Workaround: don't include +// the header in that case and just redefine the macros we need. +// +#include "nvmisc.h" +/* + * Obsolete Falcon ID type. Use NV2080_ENGINE_TYPE_ instead + */ +#define FALCON_ID_PMU (NV2080_ENGINE_TYPE_PMU) +#define FALCON_ID_DPU (NV2080_ENGINE_TYPE_DPU) +#define FALCON_ID_SEC2 (NV2080_ENGINE_TYPE_SEC2) +#define FALCON_ID_FBFLCN (NV2080_ENGINE_TYPE_FBFLCN) + +/* + * NV2080_CTRL_CMD_FLCN_GET_DMEM_USAGE + * + * This command returns total heap size and free heap size of a falcon engine + * + * flcnID + * The falcon ID + * + * heapSize + * Total heap size in byte + * + * heapFree + * Total free heap size in byte + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT + */ +#define NV2080_CTRL_CMD_FLCN_GET_DMEM_USAGE (0x20803101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS { + NvU32 flcnID; + NvU32 heapSize; + NvU32 heapFree; +} NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS; + +/*! + * @defgroup NVOS_INST_EVT Instrumentation event types. + * @{ + */ + +//! Reserved for uStreamer internal use. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RSVD_DO_NOT_USE 0x00U + +//! RTOS CTXSW includes next taskID and number of ODP for previous task. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_END 0x01U + +//! Begin of a HW IRQ. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_BEGIN 0x02U + +//! End of a HW IRQ, before stack pinning etc is performed. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_END 0x03U + +//! RTOS Timer tick slip. (Only for # tick processed > 1). +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TIMER_TICK 0x04U + +//! Task start processing an event, includes taskId, eventType and unitId (optional). +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_BEGIN 0x05U + +//! Task finished processing an event, incldues taskId. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_END 0x06U + +//! Latency for inserting response into RM queue. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RM_QUEUE_LATENCY 0x07U + +//! Special / multi-purpose event, see field definition below. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_SPECIAL_EVENT 0x08U + +//! Unused, recycle +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_UNUSED_0 0x09U + +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_DMA_END 0x0AU + +//! Begin/end for arbitrary block of code. The payload contains a sub-ID for each location profiled. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_BEGIN 0x0BU +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_END 0x0CU + +//! Queueing time for the most recent event. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_LATENCY 0x0DU +/*!@}*/ + +#define NV2080_CTRL_FLCN_NVOS_INST_INVALID_TASK_ID 0xFFU + +/* + * NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH + * + * Get the egine arch i.e FALCON, RISCV etc given the NV2080_ENGINE_TYPE_*. + * + */ +#define NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH (0x20803118) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS { + //! The engine type, from NV2080_ENGINE_TYPE_* + NvU32 engine; + + //! The engine architecture - FALCON or RISC-V + NvU32 engineArch; +} NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS; + +/*! + * @defgroup Engine Arch types + * @{ + */ +#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_DEFAULT 0x0 +#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_FALCON 0x1 +#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV 0x2 +#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV_EB 0x3 +/*!@}*/ + + +/* ----------------------- uStreamer (INST v2) ------------------------------ */ +/*! + * @defgroup NV2080_CTRL_FLCN_USTREAMER_EVENT uStreamer event fields. + * + * This is a binary-packed representation of uStreamer events. There are + * three main types of entry: Head, Payload, and Tail. COMM here is used + * when a field is shared among multiple event types. + * + * @{ + */ +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_COMM_FLAG 31:31 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_COMM_HEAD 30:30 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_VARIABLE 29:29 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EXTEND 28:28 + +/*! + * Below DRF's need constants assigned to start and end so they can be represented in FINN properly + * This is because FINN v1 will not have the ability to represent DRF's and bit fields yet. + */ +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT (27) +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE (20) +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID \ + (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT) : \ + (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE) +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT (28) +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE (24) +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT \ + (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT) : \ + (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE) + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_LENGTH 19:8 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOAD 7:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT 23:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_HEAD_TIME 29:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_DATA_PAYLOAD 30:0 +/*!@}*/ + + +/*! + * @defgroup NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_BREAKDOWN + * + * These DRFs define breakdown of the compact payload for various event IDs. + * + * @{ + */ + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_TASK_ID 7:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON 10:8 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_YIELD 0x0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_INT0 0x1 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_TIMER_TICK 0x2 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_QUEUE_BLOCK 0x3 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_DMA_SUSPENDED 0x4 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_ODP_MISS_COUNT 23:11 + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TIMER_TICK_TIME_SLIP 23:0 + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_TASK_ID 7:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_UNIT_ID 15:8 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_EVENT_TYPE 23:16 + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_TASK_ID 7:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_CALLBACK_ID 15:8 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC 15:8 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC_BOBJ_CMD_BASE 0xF0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_CLASS_ID 23:16 + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_RM_QUEUE_LATENCY_SHIFT 10U + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_TASK_ID 7:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID 23:8 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_RESERVED 0x000000 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_CB_ENQUEUE_FAIL 0x000001 + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_LATENCY_SHIFT 6U + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID 11:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_INVALID 0x000 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_VF_SWITCH_TOTAL 0x001 + +/*!@}*/ + + +/*! + * @defgroup NV2080_CTRL_FLCN_USTREAMER_FEATURE + * + * This defines all the features currently supported by uStreamer. For a new + * usecase of uStreamer, a feature should be defined here describing the usecase. + * This value should be unique for each queue. + * + * @{ + */ +#define NV2080_CTRL_FLCN_USTREAMER_FEATURE_DEFAULT 0U +#define NV2080_CTRL_FLCN_USTREAMER_FEATURE__COUNT 1U +/*!@}*/ + +/*! + * @defgroup NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY + * + * This defines the DRF used for ustreamer queue policy + * + * @{ + */ + +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH 0:0 +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_DISABLED 0U +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_ENABLED 1U + +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH 1:1 +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_DISABLED 0U +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_ENABLED 1U + +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH 2:2 +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_DISABLED 0U +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_ENABLED 1U + +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_THRESHOLD 31:8 + +/*!@}*/ + +/*! + * The maximum number of compact event types, calculated from the number of bits + * in the event structure. + */ +#define NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES_COMPACT (0x20U) /* finn: Evaluated from "(1 << (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT - NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE + 1))" */ + +/*! + * The maximum number of event types, calculated from the number of bits in the + * event structure. + */ +#define NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES (0x120U) /* finn: Evaluated from "((1 << (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT - NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE + 1)) + NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES_COMPACT)" */ + +/*! + * The number of bytes required in the event mask to contain all event types. + */ +#define NV2080_CTRL_FLCN_USTREAMER_MASK_SIZE_BYTES (0x24U) /* finn: Evaluated from "((NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES + 7) / 8)" */ + +/*! + * uStreamer Event Filter type, stored as a bitmask. + */ +typedef struct NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER { + NvU8 mask[NV2080_CTRL_FLCN_USTREAMER_MASK_SIZE_BYTES]; +} NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER; + +/*! + * NV2080_CTRL_CMD_FLCN_USTREAMER_QUEUE_INFO + * Get queue info for mapping / unmapping + */ +#define NV2080_CTRL_CMD_FLCN_USTREAMER_QUEUE_INFO (0x20803120) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS { + //! The engine type, from NV2080_ENGINE_TYPE_* + NvU32 engine; + + //! + // The page size of the requested queue in bytes. + // + NvU32 pageSize; + + //! Offset of the queue buffer in FB. + NV_DECLARE_ALIGNED(NvUPtr offset, 8); + + //! + // The size of the user-mapped instrumentation buffer. Measured in bytes. + // + NvU32 size; + + //! + // The feature ID of the queue. + // + NvU8 queueFeatureId; +} NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET/SET + * + * Get/set the event bitmask for the default queue. + */ +#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET (0x20803122) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_SET (0x20803123) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS_MESSAGE_ID" */ + +typedef struct NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS { + //! The engine type, from NV2080_ENGINE_TYPE_* + NvU32 engine; + + /*! + * The bitmask of which event types to log. An event type corresponding to + * a bit with a zero will be ignored at the log site, which prevents it + * from filling up the resident buffer in the PMU. In general, set this to + * only log the event types you actually want to use. + * Refer to NVOS_BM_* in nvos_utility.h for usage. + */ + NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER eventFilter; + + //! The queueId of the queue whose eventFilter we want to interact with + NvU8 queueId; +} NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS; + +#define NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS_MESSAGE_ID (0x22U) + +typedef NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS; + +#define NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS_MESSAGE_ID (0x23U) + +typedef NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS; + +/* + * NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO + * + * This command provides the attributes of the falcon engine context buffer + * + * hUserClient [IN] + * This parameter specifies the client handle that owns this channel. + * hChannel [IN] + * This parameter specifies the channel or channel group (TSG) handle + * alignment + * Specifies the alignment requirement for each context buffer + * size + * Aligned size of context buffer + * bufferHandle + * Opaque pointer to memdesc. Used by kernel clients for tracking purpose only. + * pageCount + * allocation size in the form of pageCount + * physAddr + * Physical address of the buffer first page + * aperture + * allocation aperture. Could be SYSMEM, VIDMEM, UNKNOWN + * kind + * PTE kind of this allocation. + * pageSize + * Page size of the buffer. + * bIsContigous + * States if physical allocation for this buffer is contiguous. PageSize will + * have no meaning if this flag is set. + * bDeviceDescendant + * TRUE if the allocation is a constructed under a Device or Subdevice. + * uuid + * SHA1 UUID of the Device or Subdevice. Valid when bDeviceDescendant is TRUE. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO (0x20803124) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID (0x24U) + +typedef struct NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS { + NvHandle hUserClient; + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 alignment, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NV_DECLARE_ALIGNED(NvP64 bufferHandle, 8); + NV_DECLARE_ALIGNED(NvU64 pageCount, 8); + NV_DECLARE_ALIGNED(NvU64 physAddr, 8); + NvU32 aperture; + NvU32 kind; + NvU32 pageSize; + NvBool bIsContigous; + NvBool bDeviceDescendant; + NvU8 uuid[16]; +} NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS; + +// Aperture flags +#define NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_UNKNWON ADDR_UNKNOWN +#define NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_SYSMEM ADDR_SYSMEM +#define NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_FBMEM ADDR_FBMEM + +/* + * NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE + * + * This command provides the size of the falcon engine context buffer + * + * hChannel [IN] + * This parameter specifies the channel or channel group (TSG) handle + * totalBufferSize [OUT] + * This parameter returns the total context buffers size. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE (0x20803125) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x25U) + +typedef struct NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS { + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 totalBufferSize, 8); +} NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS; + + + +/* _ctrl2080flcn_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fuse.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fuse.h new file mode 100644 index 0000000..7ea0b05 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080fuse.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080fuse.finn +// + + + +/* _ctrl2080fuse_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gpio.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gpio.h new file mode 100644 index 0000000..fd0e349 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gpio.h @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080gpio.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + + + +#define NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_DIRECTION (0x20802300) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS_MESSAGE_ID (0x00U) + +typedef struct NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS { + NvU32 gpioPin; // in + NvBool bInput; // in +} NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_OUTPUT (0x20802301) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS_MESSAGE_ID (0x01U) + +typedef struct NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS { + NvU32 gpioPin; // in + NvU32 value; // in +} NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_GPIO_READ_INPUT (0x20802302) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS_MESSAGE_ID (0x02U) + +typedef struct NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS { + NvU32 gpioPin; // in + NvU32 value; // out +} NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION (0x20802303) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS_MESSAGE_ID (0x03U) + +typedef struct NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS { + NvU32 function; // in + NvU32 pin; // in +} NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS; + +/* _ctrl2080gpio_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gpu.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gpu.h new file mode 100644 index 0000000..bdc35e5 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gpu.h @@ -0,0 +1,5026 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080gpu.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "ctrl/ctrl2080/ctrl2080gr.h" +#include "ctrl/ctrl0000/ctrl0000system.h" +#include "nvcfg_sdk.h" +#include "nvstatus.h" + +#define NV_GRID_LICENSE_INFO_MAX_LENGTH (128) + +/* License info strings for vGPU products */ +#define NV_GRID_LICENSE_FEATURE_VPC_EDITION "GRID-Virtual-PC,2.0;Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0" +#define NV_GRID_LICENSE_FEATURE_VAPPS_EDITION "GRID-Virtual-Apps,3.0" +#define NV_GRID_LICENSE_FEATURE_VIRTUAL_WORKSTATION_EDITION "Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0" +#define NV_GRID_LICENSE_FEATURE_GAMING_EDITION "GRID-vGaming,8.0" +#define NV_GRID_LICENSE_FEATURE_COMPUTE_EDITION "NVIDIA-vComputeServer,9.0" + +#define NV_GRID_LICENSED_PRODUCT_VWS "NVIDIA RTX Virtual Workstation" +#define NV_GRID_LICENSED_PRODUCT_GAMING "NVIDIA Cloud Gaming" +#define NV_GRID_LICENSED_PRODUCT_VPC "NVIDIA Virtual PC" +#define NV_GRID_LICENSED_PRODUCT_VAPPS "NVIDIA Virtual Applications" +#define NV_GRID_LICENSED_PRODUCT_COMPUTE "NVIDIA Virtual Compute Server" +#define NV_GRID_LICENSED_PRODUCT_VGPU_FOR_COMPUTE "NVIDIA vGPU for Compute" + + + +/* NV20_SUBDEVICE_XX gpu control commands and parameters */ + + + +typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO; + +/* valid gpu info index values */ + +#define NV2080_CTRL_GPU_INFO_INDEX_INDEX 23:0 + + + +#define NV2080_CTRL_GPU_INFO_INDEX_ECID_LO32 (0x00000001U) +#define NV2080_CTRL_GPU_INFO_INDEX_ECID_HI32 (0x00000002U) +#define NV2080_CTRL_GPU_INFO_INDEX_MINOR_REVISION_EXT (0x00000004U) + + +#define NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV0 (0x00000012U) +#define NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV1 (0x00000013U) + + +#define NV2080_CTRL_GPU_INFO_INDEX_ECID_EXTENDED (0x0000001bU) +#define NV2080_CTRL_GPU_INFO_INDEX_SYSMEM_ACCESS (0x0000001fU) + + +#define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD (0x00000022U) + + +#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE (0x00000025U) +#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED (0x00000027U) +#define NV2080_CTRL_GPU_INFO_INDEX_NVSWITCH_PROXY_DETECTED (0x00000028U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT (0x00000029U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SMC_MODE (0x0000002aU) +#define NV2080_CTRL_GPU_INFO_INDEX_SPLIT_VAS_MGMT_SERVER_CLIENT_RM (0x0000002bU) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SM_VERSION (0x0000002cU) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY (0x0000002dU) + + +#define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM (0x0000002fU) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY (0x00000030U) +#define NV2080_CTRL_GPU_INFO_INDEX_NVENC_STATS_REPORTING_STATE (0x00000031U) + + +#define NV2080_CTRL_GPU_INFO_INDEX_DISPLAY_ENABLED (0x00000034U) +#define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED (0x00000035U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY (0x00000036U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY (0x00000037U) + + +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY (0x0000003aU) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY (0x0000003bU) +#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU (0x0000003cU) +#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY (0x0000003dU) + + +#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED (0x0000003fU) + + +#define NV2080_CTRL_GPU_INFO_INDEX_IS_LOCALIZATION_SUPPORTED (0x00000041U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_NON_PASID_ATS_CAPABILITY (0x00000042U) + +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_SYSMEM_CAPABILITY (0x00000043U) + + +#define NV2080_CTRL_GPU_INFO_INDEX_COHERENT_GPU_MEMORY_MODE (0x00000044U) + +#define NV2080_CTRL_GPU_INFO_INDEX_COMPR_BIT_BACKING_COPY_TYPE (0x00000045U) + +#define NV2080_CTRL_GPU_INFO_INDEX_CPU_COHERENT_CACHING_GPU_MEMORY_CAPABILITY (0x00000046U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_COHERENT_CACHING_CPU_MEMORY_CAPABILITY (0x00000047U) + +#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000048U) + +#define NV2080_CTRL_GPU_INFO_INDEX_TYPE 30:28 +#define NV2080_CTRL_GPU_INFO_INDEX_TYPE_SPECIFIC_ID 27:24 +#define NV2080_CTRL_GPU_INFO_INDEX_RESERVED 31:31 + +/* valid minor revision extended values */ +#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE (0x00000000U) +#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_P (0x00000001U) +#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_V (0x00000002U) +#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_PV (0x00000003U) + + + +/* valid system memory access capability values */ +#define NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_YES (0x00000001U) + + + +/* valid gemini board values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_YES (0x00000001U) + +/* valid surprise removal values */ +#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_YES (0x00000001U) + +/* valid poison fuse capability values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_YES (0x00000001U) + +/* valid nvswitch proxy detected values */ +#define NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_YES (0x00000001U) + +/* valid NVSR GPU support info values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_YES (0x00000001U) + +/* valid SMC mode values */ +#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_UNSUPPORTED (0x00000000U) +#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLED (0x00000001U) +#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLED (0x00000002U) +#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLE_PENDING (0x00000003U) +#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLE_PENDING (0x00000004U) + +/* valid split VAS mode values */ +#define NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_YES (0x00000001U) + +/* valid grid capability values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_YES (0x00000001U) + +/* valid per runlist channel ram capability values */ +#define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_DISABLED (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_ENABLED (0x00000001U) + +/* valid ATS capability values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_YES (0x00000001U) + +/* valid Nvenc Session Stats reporting state values */ +#define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_DISABLED (0x00000000U) +#define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED (0x00000001U) +#define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_NOT_SUPPORTED (0x00000002U) + +/* valid display enabled values */ +#define NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_YES (0x00000001U) + +/* valid mobile config enabled values */ +#define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_YES (0x00000001U) + + +/* valid profiling capability values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_DISABLED (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_ENABLED (0x00000001U) + +/* valid debugging capability values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_DISABLED (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_ENABLED (0x00000001U) + + + +/* valid local EGM supported values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_YES (0x00000001U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_PEERID 31:1 + +/* valid self hosted values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_YES (0x00000001U) + +/* valid CMP (Crypto Mining Processor) SKU values */ +#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_YES (0x00000001U) + + +/* valid dma-buf suport values */ +#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES (0x00000001U) + +/* valid resetless MIG device supported values */ +#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_YES (0x00000001U) + +/* valid localization supported values */ +#define NV2080_CTRL_GPU_INFO_INDEX_IS_LOCALIZATION_SUPPORTED_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_IS_LOCALIZATION_SUPPORTED_YES (0x00000001U) + +/* valid Non-PASID ATS capability values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_NON_PASID_ATS_CAPABILITY_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_NON_PASID_ATS_CAPABILITY_YES (0x00000001U) + +/* valid fla sysmem capability values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_SYSMEM_CAPABILITY_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_SYSMEM_CAPABILITY_YES (0x00000001U) + + + +/* valid coherent GPU memory mode capability values */ +#define NV2080_CTRL_GPU_INFO_INDEX_COHERENT_GPU_MEMORY_MODE_NONE (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_COHERENT_GPU_MEMORY_MODE_NUMA (0x00000001U) +#define NV2080_CTRL_GPU_INFO_INDEX_COHERENT_GPU_MEMORY_MODE_DRIVER (0x00000002U) + +/* valid compression bit backing copy type values */ +#define NV2080_CTRL_GPU_INFO_INDEX_COMP_BIT_BACKING_COPY_TYPE_PHYSICAL (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_COMP_BIT_BACKING_COPY_TYPE_VIRTUAL (0x00000001U) + +#define NV2080_CTRL_GPU_INFO_INDEX_CPU_COHERENT_CACHING_GPU_MEMORY_CAPABILITY_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_CPU_COHERENT_CACHING_GPU_MEMORY_CAPABILITY_YES (0x00000001U) + +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_COHERENT_CACHING_CPU_MEMORY_CAPABILITY_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_COHERENT_CACHING_CPU_MEMORY_CAPABILITY_YES (0x00000001U) + + +/* + * NV2080_CTRL_CMD_GPU_GET_INFO + * + * This command returns gpu information for the associated GPU. Requests + * to retrieve gpu information use a list of one or more NV2080_CTRL_GPU_INFO + * structures. + * + * gpuInfoListSize + * This field specifies the number of entries on the caller's + * gpuInfoList. + * gpuInfoList + * This field specifies a pointer in the caller's address space + * to the buffer into which the gpu information is to be returned. + * This buffer must be at least as big as gpuInfoListSize multiplied + * by the size of the NV2080_CTRL_GPU_INFO structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_OPERATING_SYSTEM + */ +#define NV2080_CTRL_CMD_GPU_GET_INFO (0x20800101U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_GPU_GET_INFO_PARAMS { + NvU32 gpuInfoListSize; + NV_DECLARE_ALIGNED(NvP64 gpuInfoList, 8); +} NV2080_CTRL_GPU_GET_INFO_PARAMS; + +#define NV2080_CTRL_CMD_GPU_GET_INFO_V2 (0x20800102U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_GPU_GET_INFO_V2_PARAMS { + NvU32 gpuInfoListSize; + NV2080_CTRL_GPU_INFO gpuInfoList[NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE]; +} NV2080_CTRL_GPU_GET_INFO_V2_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_NAME_STRING + * + * This command returns the name of the GPU in string form in ASCII format. + * + * gpuNameStringFlags + * Ignored, to be removed. Callers should not be setting it at all. + * gpuNameString + * This field contains the buffer into which the name string should be + * returned. The length of the returned string will be no more than + * NV2080_CTRL_GPU_MAX_NAME_STRING_LENGTH bytes in size. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV2080_CTRL_CMD_GPU_GET_NAME_STRING (0x20800110U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID" */ + +#define NV2080_GPU_MAX_NAME_STRING_LENGTH (0x0000040U) + +// This field is deprecated - 'gpuNameStringFlags' is now a simple scalar. +// Field maintained (and extended from 0:0) for compile-time compatibility. +#define NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE 31:0 + +/* valid gpu name string flags - deprecated, should not set anything */ +#define NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII (0x00000000U) + +#define NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS { + NvU32 gpuNameStringFlags; + struct { + NvU8 ascii[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + } gpuNameString; +} NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING + * + * This command returns the short name of the GPU in ASCII string form. + * + * gpuShortNameString + * This field contains the buffer into which the short name string should + * be returned. The length of the returned string will be no more than + * NV2080_MAX_NAME_STRING_LENGTH bytes in size. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING (0x20800111U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS { + NvU8 gpuShortNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH]; +} NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_SET_POWER + * + * This command sets the power state for the GPU as a whole, various engines, + * or clocks. + * + * target + * One of NV2080_CTRL_GPU_SET_POWER_TARGET_* + * + * newLevel + * One of NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_* + * NV2080_CTRL_GPU_SET_POWER_STATE_ENGINE_LEVEL_* + * NV2080_CTRL_GPU_SET_POWER_STATE_CLOCK_LEVEL_* + * depending on the target above. + * + * oldLevel + * Previous level as appropriate. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_GPU_SET_POWER (0x20800112U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV2080_CTRL_GPU_SET_POWER_PARAMS { + NvU32 target; + NvU32 newLevel; + NvU32 oldLevel; +} NV2080_CTRL_GPU_SET_POWER_PARAMS; + + + +#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_0 (0x00000000U) +#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_1 (0x00000001U) +#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_2 (0x00000002U) +#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3 (0x00000003U) +#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_4 (0x00000004U) +#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_7 (0x00000007U) + +/* + * NV2080_CTRL_CMD_GPU_GET_SDM + * + * This command returns the subdevice mask value for the associated subdevice. + * The subdevice mask value can be used with the SET_SUBDEVICE_MASK instruction + * provided by the NV36_CHANNEL_DMA and newer channel dma classes. + * + * subdeviceMask [out] + * This field return the subdevice mask value. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_GPU_GET_SDM (0x20800118U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV2080_CTRL_GPU_GET_SDM_PARAMS { + NvU32 subdeviceMask; +} NV2080_CTRL_GPU_GET_SDM_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_SET_SDM + * + * This command sets the subdevice instance and mask value for the associated subdevice. + * The subdevice mask value can be used with the SET_SUBDEVICE_MASK instruction + * provided by the NV36_CHANNEL_DMA and newer channel dma classes. + * It must be called before the GPU HW is initialized otherwise + * NV_ERR_INVALID_STATE is being returned. + * + * subdeviceMask [in] + * This field configures the subdevice mask value for the GPU/Subdevice + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_DATA + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_GPU_SET_SDM (0x20800120U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV2080_CTRL_GPU_SET_SDM_PARAMS { + NvU32 subdeviceMask; +} NV2080_CTRL_GPU_SET_SDM_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO + * + * This command returns the associated subdevices' simulation information. + * + * type + * This field returns the simulation type. + * One of NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_* + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO (0x20800119U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS { + NvU32 type; +} NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS; + +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_NONE (0x00000000U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_MODS_AMODEL (0x00000001U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_LIVE_AMODEL (0x00000002U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_FMODEL (0x00000003U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_RTL (0x00000004U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU (0x00000005U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU_LOW_POWER (0x00000006U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA (0x00000007U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_RTL (0x00000008U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_FMODEL (0x00000009U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_UNKNOWN (0xFFFFFFFFU) + +/* + * NV2080_CTRL_GPU_REG_OP + * + * This structure describes register operation information for use with + * the NV2080_CTRL_CMD_GPU_EXEC_REG_OPS command. The structure describes + * a single register operation. The operation can be a read or write and + * can involve either 32bits or 64bits of data. + * + * For 32bit read operations, the operation takes the following form: + * + * regValueLo = read(bar0 + regOffset) + * regValueHi = 0 + * + * For 64bit read operations, the operation takes the following form: + * + * regValueLo = read(bar0 + regOffset) + * regValueHi = read(bar0 + regOffset + 4) + * + * For 32bit write operations, the operation takes the following form: + * + * new = ((read(bar0 + regOffset) & ~regAndNMaskLo) | regValueLo) + * write(bar0 + regOffset, new) + * + * For 64bit write operations, the operation takes the following form: + * + * new_lo = ((read(bar0 + regOffset) & ~regAndNMaskLo) | regValueLo) + * new_hi = ((read(bar0 + regOffset + 4) & ~regAndNMaskHi) | regValueHi) + * write(bar0 + regOffset, new_lo) + * write(bar0 + regOffset + 4, new_hi) + * + * Details on the parameters follow: + * + * regOp + * This field specifies the operation to be applied to the register + * specified by the regOffset parameter. Valid values for this + * parameter are: + * NV2080_CTRL_GPU_REG_OP_READ_08 + * The register operation should be a 8bit global privileged register read. + * NV2080_CTRL_GPU_REG_OP_WRITE_08 + * The register operation should be a 8bit global privileged register write. + * NV2080_CTRL_GPU_REG_OP_READ_32 + * The register operation should be a 32bit register read. + * NV2080_CTRL_GPU_REG_OP_WRITE_32 + * The register operation should be a 32bit register write. + * NV2080_CTRL_GPU_REG_OP_READ_64 + * The register operation should be a 64bit register read. + * NV2080_CTRL_GPU_REG_OP_WRITE_64 + * The register operation should be a 64bit register write. + * regType + * This field specifies the type of the register specified by the + * regOffset parameter. Valid values for this parameter are: + * NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL + * The register is a global privileged register. Read operations + * return the current value from the associated global register. + * Write operations for registers of this type take effect immediately. + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX + * The register is a graphics context register. Read operations + * return the current value from the associated global register. + * Write operations are applied to all existing graphics engine + * contexts. Any newly created graphics engine contexts will also + * be modified. + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC + * This is a graphics context TPC register group. Write operations are + * applied to TPC group(s) specified by regGroupMask. + * This field is ignored for read operations. + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM + * This is a graphics context SM register group that is inside TPC + * group. Write operations are applied to SM group(s) specified by + * regGroupMask (TPC) and regSubGroupMask (SM). This field is ignored + * for read operations. + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP + * This is a graphics context CROP register group. Write operations + * are applied to registers specified by regGroupMask. This field is + * ignored for read operations. + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP + * This is a graphics context ZROP register group. Write operations + * are applied to registers specified by regGroupMask. This field is + * ignored for read operations. + * NV2080_CTRL_GPU_REG_OP_TYPE_FB + * This is a fb register group. Write operations are applied to + * registers specified by regGroupMask. This field is + * ignored for read operations. + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD + * This is a graphics context QUAD register group. Operations + * are applied to registers specified by regQuad value. + * regQuad + * This field specifies the quad to be accessed for register regOffsetwhen + * the regType specified is NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD. + * regGroupMask + * This field specifies which registers inside an array should be updated. + * This field is used when regType is one of below: + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP + * NV2080_CTRL_GPU_REG_OP_TYPE_FB + * When regGroupMask is used, the regOffset MUST be the first register in + * an array. + * regSubGroupMask + * This field specifies which registers inside a group should be updated. + * This field is used for updating SM registers when regType is: + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC + * When regSubGroupMask is used, regOffset MUST be the first register in an + * array AND also the first one in sub array. regGroupMask specifies + * TPC(X) and regSubGroupMask specifies SM_CTX_N(Y) + * regStatus + * This field returns the completion status for the associated register + * operation in the form of a bitmask. Possible status values for this + * field are: + * NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS + * This value indicates the operation completed successfully. + * NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OP + * This bit value indicates that the regOp value is not valid. + * NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_TYPE + * This bit value indicates that the regType value is not valid. + * NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OFFSET + * This bit value indicates that the regOffset value is invalid. + * The regOffset value must be within the legal BAR0 range for the + * associated GPU and must target a supported register with a + * supported operation. + * NV2080_CTRL_GPU_REG_OP_STATUS_UNSUPPORTED_OFFSET + * This bit value indicates that the operation to the register + * specified by the regOffset value is not supported for the + * associated GPU. + * NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_MASK + * This bit value indicates that the regTpcMask value is invalid. + * The regTpcMask must be a subset of TPCs that are enabled on the + * associated GPU. + * NV2080_CTRL_GPU_REG_OP_STATUS_NOACCESS + * The caller does not have access to the register at given offset + * regOffset + * This field specifies the register offset to access. The specified + * offset must be a valid BAR0 offset for the associated GPU. + * regValueLo + * This field contains the low 32bits of the register value. + * For read operations, this value returns the current value of the + * register specified by regOffset. For write operations, this field + * specifies the logical OR value applied to the current value + * contained in the register specified by regOffset. + * regValueHi + * This field contains the high 32bits of the register value. + * For read operations, this value returns the current value of the + * register specified by regOffset + 4. For write operations, this field + * specifies the logical OR value applied to the current value + * contained in the register specified by regOffset + 4. + * regAndNMaskLo + * This field contains the mask used to clear a desired field from + * the current value contained in the register specified by regOffsetLo. + * This field is negated and ANDed to this current register value. + * This field is only used for write operations. This field is ignored + * for read operations. + * regAndNMaskHi + * This field contains the mask used to clear a desired field from + * the current value contained in the register specified by regOffsetHi. + * This field is negated and ANDed to this current register value. + * This field is only used for write operations. This field is ignored + * for read operations. + */ +typedef struct NV2080_CTRL_GPU_REG_OP { + NvU8 regOp; + NvU8 regType; + NvU8 regStatus; + NvU8 regQuad; + NvU32 regGroupMask; + NvU32 regSubGroupMask; + NvU32 regOffset; + NvU32 regValueHi; + NvU32 regValueLo; + NvU32 regAndNMaskHi; + NvU32 regAndNMaskLo; +} NV2080_CTRL_GPU_REG_OP; + +/* valid regOp values */ +#define NV2080_CTRL_GPU_REG_OP_READ_32 (0x00000000U) +#define NV2080_CTRL_GPU_REG_OP_WRITE_32 (0x00000001U) +#define NV2080_CTRL_GPU_REG_OP_READ_64 (0x00000002U) +#define NV2080_CTRL_GPU_REG_OP_WRITE_64 (0x00000003U) +#define NV2080_CTRL_GPU_REG_OP_READ_08 (0x00000004U) +#define NV2080_CTRL_GPU_REG_OP_WRITE_08 (0x00000005U) + +/* valid regType values */ +#define NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL (0x00000000U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX (0x00000001U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC (0x00000002U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM (0x00000004U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP (0x00000008U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP (0x00000010U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_FB (0x00000020U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD (0x00000040U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_DEVICE (0x00000080U) + +/* valid regStatus values (note: NvU8 ie, 1 byte) */ +#define NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS (0x00U) +#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OP (0x01U) +#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_TYPE (0x02U) +#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OFFSET (0x04U) +#define NV2080_CTRL_GPU_REG_OP_STATUS_UNSUPPORTED_OP (0x08U) +#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_MASK (0x10U) +#define NV2080_CTRL_GPU_REG_OP_STATUS_NOACCESS (0x20U) + +/* + * NV2080_CTRL_CMD_GPU_EXEC_REG_OPS + * + * This command is used to submit a buffer containing one or more + * NV2080_CTRL_GPU_REG_OP structures for processing. Each entry in the + * buffer specifies a single read or write operation. Each entry is checked + * for validity in an initial pass over the buffer with the results for + * each operation stored in the corresponding regStatus field. Unless + * bNonTransactional flag is set to true, if any invalid entries are found + * during this initial pass then none of the operations are executed. Entries + * are processed in order within each regType with NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL + * entries processed first followed by NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX entries. + * + * hClientTarget + * This parameter specifies the handle of the client that owns the channel + * specified by hChannelTarget. If this parameter is set to 0 then the set + * of channel-specific register operations are applied to all current and + * future channels. + * hChannelTarget + * This parameter specifies the handle of the target channel (or channel + * group) object instance to which channel-specific register operations are + * to be directed. If hClientTarget is set to 0 then this parameter must + * also be set to 0. + * bNonTransactional + * This field specifies if command is non-transactional i.e. if set to + * true, all the valid operations will be executed. + * reserved00 + * This parameter is reserved for future use. It should be initialized to + * zero for correct operation. + * regOpCount + * This field specifies the number of entries on the caller's regOps + * list. + * regOps + * This field specifies a pointer in the caller's address space + * to the buffer from which the desired register information is to be + * retrieved. This buffer must be at least as big as regInfoCount + * multiplied by the size of the NV2080_CTRL_GPU_REG_OP structure. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. When SMC is enabled, this + * is a mandatory parameter. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS (0x20800122U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS { + NvHandle hClientTarget; + NvHandle hChannelTarget; + NvU32 bNonTransactional; + NvU32 reserved00[2]; + NvU32 regOpCount; + NV_DECLARE_ALIGNED(NvP64 regOps, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_ENGINES + * + * Returns a list of supported engine types along with the number of instances + * of each type. Querying with engineList NULL returns engineCount. + * + * engineCount + * This field specifies the number of entries on the caller's engineList + * field. + * engineList + * This field is a pointer to a buffer of NvU32 values representing the + * set of engines supported by the associated subdevice. Refer to cl2080.h + * for the complete set of supported engine types. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_GPU_GET_ENGINES (0x20800123U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID (0x23U) + +typedef struct NV2080_CTRL_GPU_GET_ENGINES_PARAMS { + NvU32 engineCount; + NV_DECLARE_ALIGNED(NvP64 engineList, 8); +} NV2080_CTRL_GPU_GET_ENGINES_PARAMS; + +#define NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 (0x20800170U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID" */ + +/* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */ +#define NV2080_GPU_MAX_ENGINES_LIST_SIZE 0x54U + +#define NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID (0x70U) + +typedef struct NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS { + NvU32 engineCount; + NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; +} NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST + * + * Returns a list of classes supported by a given engine type. + * + * engineType + * This field specifies the engine type being queried. + * NV2080_CTRL_ENGINE_TYPE_ALLENGINES will return classes + * supported by all engines. + * + * numClasses + * This field specifies the number of classes supported by + * engineType. + * + * classList + * This field is an array containing the list of supported + * classes. Is of type (NvU32*) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST (0x20800124U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID (0x24U) + +typedef struct NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS { + NvU32 engineType; + NvU32 numClasses; + NV_DECLARE_ALIGNED(NvP64 classList, 8); +} NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS; + + +/* + * NV2080_CTRL_CMD_GPU_GET_ENGINE_FAULT_INFO + * + * This command returns the fault properties of the specified engine type. + * + * engineType + * Input parameter. + * This field specifies the engine type being queried. + * Engine type is specified using the NV2080_ENGINE_TYPE_* defines in cl2080.h. + * The list of engines supported by a chip can be got using the + * NV2080_CTRL_CMD_GPU_GET_ENGINES ctrl call. + * + * mmuFaultId + * Output parameter. + * This field returns the MMU fault ID for the specified engine. + * If the engine supports subcontext, this field provides the base fault id. + * + * bSubcontextSupported + * Output parameter. + * Returns TRUE if subcontext faulting is supported by the engine. + * Engine that support subcontext use fault IDs in the range [mmuFaultId, mmuFaultId + maxSubCtx). + * "maxSubctx" can be found using the NV2080_CTRL_FIFO_INFO ctrl call with + * NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP as the index. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_GPU_GET_ENGINE_FAULT_INFO (0x20800125U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID (0x25U) + +typedef struct NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS { + NvU32 engineType; + NvU32 mmuFaultId; + NvBool bSubcontextSupported; +} NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS; + + + +/*! + * NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY + * Data block describing a virtual context buffer to be promoted + * + * gpuPhysAddr [IN] + * GPU Physical Address for the buffer + * gpuVirtAddr [IN] + * GPU Virtual Address for the buffer + * size[IN] + * Size of this virtual context buffer + * physAttr [IN] + * Physical memory attributes (aperture, cacheable) + * bufferId [IN] + * Virtual context buffer type, data type NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_* + * bInitialize [IN] + * Flag indicating that this virtual context buffer should be initialized prior to promotion. + * The client must clear (memset) the buffer to 0x0 prior to initialization. + * Following buffers need initialization: + * 1. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN + * 2. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH + * 3. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP + * 4. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP + * bNonmapped [IN] + * Flag indicating that the virtual address is not to be promoted with this + * call. It is illegal to set this flag and not set bInitialize. + */ +typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY { + NV_DECLARE_ALIGNED(NvU64 gpuPhysAddr, 8); + NV_DECLARE_ALIGNED(NvU64 gpuVirtAddr, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 physAttr; + NvU16 bufferId; + NvU8 bInitialize; + NvU8 bNonmapped; +} NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY; + +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN 0U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM 1U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH 2U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_BUFFER_BUNDLE_CB 3U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PAGEPOOL 4U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_ATTRIBUTE_CB 5U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_RTV_CB_GLOBAL 6U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_POOL 7U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_CTRL_BLK 8U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_FECS_EVENT 9U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP 10U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP 11U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GLOBAL_PRIV_ACCESS_MAP 12U + +#define NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES 16U + +/* + * NV2080_CTRL_CMD_GPU_PROMOTE_CTX + * + * This command is used to promote a Virtual Context + * + * engineType + * Engine Virtual Context is for + * hClient + * Client Handle for hVirtMemory + * ChID + * Hw Channel -- Actually hw index for channel (deprecated) + * hChanClient + * The client handle for hObject + * hObject + * Passed in object handle for either a single channel or a channel group + * hVirtMemory + * Virtual Address handle to map Virtual Context to + * virtAddress + * Virtual Address to map Virtual Context to + * size + * size of the Virtual Context + * entryCount + * Number of valid entries in the promotion entry list + * promoteEntry + * List of context buffer entries to issue promotions for. + * + * When not using promoteEntry, only hVirtMemory or (virtAddress, size) should be + * specified, the code cases based on hVirtMemory(NULL vs non-NULL) so + * if both are specified, hVirtMemory has precedence. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED - The Class does not support version info retrieval + * NV_ERR_INVALID_DEVICE - The Class/Device is not yet ready to provide this info. + * NV_ERR_INVALID_ARGUMENT - Bad/Unknown Class ID specified. + */ +#define NV2080_CTRL_CMD_GPU_PROMOTE_CTX (0x2080012bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID (0x2BU) + +typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS { + NvU32 engineType; + NvHandle hClient; + NvU32 ChID; + NvHandle hChanClient; + NvHandle hObject; + NvHandle hVirtMemory; + NV_DECLARE_ALIGNED(NvU64 virtAddress, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 entryCount; + // C form: NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY promoteEntry[NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES]; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY promoteEntry[NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES], 8); +} NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS; +typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS *PNV2080_CTRL_GPU_PROMOTE_CTX_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_EVICT_CTX + * + * This command is used to evict a Virtual Context + * + * engineType + * Engine Virtual Context is for + * hClient + * Client Handle + * ChID + * Hw Channel -- Actually hw index for channel (deprecated) + * hChanClient + * Client handle for hObject + * hObject + * Passed in object handle for either a single channel or a channel group + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED - The Class does not support version info retrieval + * NV_ERR_INVALID_DEVICE - The Class/Device is not yet ready to provide this info. + * NV_ERR_INVALID_ARGUMENT - Bad/Unknown Class ID specified. + */ +#define NV2080_CTRL_CMD_GPU_EVICT_CTX (0x2080012cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID (0x2CU) + +typedef struct NV2080_CTRL_GPU_EVICT_CTX_PARAMS { + NvU32 engineType; + NvHandle hClient; + NvU32 ChID; + NvHandle hChanClient; + NvHandle hObject; +} NV2080_CTRL_GPU_EVICT_CTX_PARAMS; +typedef struct NV2080_CTRL_GPU_EVICT_CTX_PARAMS *PNV2080_CTRL_GPU_EVICT_CTX_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_INITIALIZE_CTX + * + * This command is used to initialize a Virtual Context. The ctx buffer must be + * cleared (zerod) by the caller prior to invoking this method. + * + * engineType + * Engine Virtual Context is for + * hClient + * Client Handle for the hVirtMemory + * ChID + * Hw channel -- Actually channel index (deprecated) + * hChanClient + * The client handle for hObject + * hObject + * Passed in object handle for either a single channel or a channel group + * hVirtMemory + * Virtual Address where to map Virtual Context to + * physAddress + * Physical offset in FB to use as Virtual Context + * physAttr + * Physical memory attributes + * hDmaHandle + * Dma Handle when using discontiguous context buffers + * index + * Start offset in Virtual DMA Context + * size + * Size of the Virtual Context + * + * Only hVirtMemory or size should be specified, the code cases based on hVirtMemory + * (NULL vs non-NULL) so if both are specified, hVirtMemory has precedence. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED - The Class does not support version info retrieval + * NV_ERR_INVALID_DEVICE - The Class/Device is not yet ready to provide this info. + * NV_ERR_INVALID_ARGUMENT - Bad/Unknown Class ID specified. + */ +#define NV2080_CTRL_CMD_GPU_INITIALIZE_CTX (0x2080012dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID (0x2DU) + +typedef struct NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS { + NvU32 engineType; + NvHandle hClient; + NvU32 ChID; + NvHandle hChanClient; + NvHandle hObject; + NvHandle hVirtMemory; + NV_DECLARE_ALIGNED(NvU64 physAddress, 8); + NvU32 physAttr; + NvHandle hDmaHandle; + NvU32 index; + NV_DECLARE_ALIGNED(NvU64 size, 8); +} NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS; +typedef struct NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS *PNV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS; + +#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE 1:0 +#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_VIDMEM (0x00000000U) +#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_COH_SYS (0x00000001U) +#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_NCOH_SYS (0x00000002U) + +#define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE 2:2 +#define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_YES (0x00000000U) +#define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_NO (0x00000001U) + +/* + * NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX - Tells RM Whether this Ctx buffer needs to + * do a full initialization (Load the golden image). When a context is promoted on a different + * channel than it was originally inited, the client can use this flag to tell RM + * that this is an already inited Context. In such cases RM will update the internal state + * to update the context address and state variables. + */ + +#define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX 3:3 +#define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_NO (0x00000000U) +#define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_YES (0x00000001U) + +/* + * NV2080_CTRL_CMD_CPU_QUERY_ECC_INTR + * Queries the top level ECC PMC PRI register + * TODO remove these parameters, tracked in bug #1975721 + */ +#define NV2080_CTRL_CMD_GPU_QUERY_ECC_INTR (0x2080012eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x2E" */ + +typedef struct NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS { + NvU32 eccIntrStatus; +} NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS; + +/** + * NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS + * + * This command is used to query the ECC status of a GPU by a subdevice + * handle. Please see the NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS + * data structure description below for details on the data reported + * per hardware unit. + * + * units + * Array of structures used to describe per-unit state + * + * flags + * See interface flag definitions below. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + + + +#define NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS (0x2080012fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID" */ + + +#define NV2080_CTRL_GPU_ECC_UNIT_GSP (0x0000001DU) + + +#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x00000029U) + + + +// Deprecated do not use +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE 0:0 +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_FILTERED (0x00000000U) +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_RAW (0x00000001U) + +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_FALSE 0U +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_TRUE 1U +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_INDETERMINATE 2U + +/* + * NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS + * + * This structure represents the exception status of a class of per-unit + * exceptions + * + * count + * number of exceptions that have occurred since boot + */ +typedef struct NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS { + NV_DECLARE_ALIGNED(NvU64 count, 8); +} NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS; + +/* + * NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS + * + * This structure represents the per-unit ECC exception status + * + * enabled + * ECC enabled yes/no for this unit + * scrubComplete + * Scrub has completed yes/no. A scrub is performed for some units to ensure + * the checkbits are consistent with the protected data. + * supported + * Whether HW supports ECC in this unit for this GPU + * dbe + * Double bit error (DBE) status. The value returned reflects a counter + * that is monotonic, but can be reset by clients. + * dbeNonResettable (deprecated do not use) + * Double bit error (DBE) status, not client resettable. + * sbe + * Single bit error (SBE) status. The value returned reflects a counter + * that is monotonic, but can be reset by clients. + * sbeNonResettable (deprecated do not use) + * Single bit error (SBE) status, not client resettable. + * + */ +typedef struct NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS { + NvBool enabled; + NvBool scrubComplete; + NvBool supported; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS dbe, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS dbeNonResettable, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS sbe, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS sbeNonResettable, 8); +} NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS; + +/* + * NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS + * + * This structure returns ECC exception status and GPU Fatal Poison for all units + * + * units + * This structure represents ECC exception status for all Units. + * bFatalPoisonError + * Whether GPU Fatal poison error occurred in this GPU. This will be set for Ampere_and_later + * uncorrectableError + * Indicates whether any uncorrectable GR ECC errors have occurred. When + * SMC is enabled, uncorrectableError is only valid when the client is + * subscribed to a partition. Check QUERY_ECC_STATUS_UNC_ERR_* + * flags + * Flags passed by caller. Refer NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_* for details. + * grRouteInfo + * SMC partition information. This input is only valid when SMC is + * enabled on Ampere_and_later. + * + */ +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID (0x2FU) + +typedef struct NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS units[NV2080_CTRL_GPU_ECC_UNIT_COUNT], 8); + NvBool bFatalPoisonError; + NvU8 uncorrectableError; + NvU32 flags; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES + * + * This command sets the compute mode rules for the associated subdevice. The + * default mode is equivalent to NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE. This + * command is available to clients with administrator privileges only. An + * attempt to use this command by a client without administrator privileged + * results in the return of an NV_ERR_INSUFFICIENT_PERMISSIONS status. + * + * rules + * This parameter is used to specify the rules that govern the GPU with + * respect to NV50_COMPUTE objects. Legal values for this parameter include: + * + * NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE + * This mode indicate that no special restrictions apply to the + * allocation of NV50_COMPUTE objects. + * + * NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE + * This mode means that only one instance of NV50_COMPUTE will be + * allowed at a time. This restriction is enforced at each subsequent + * NV50_COMPUTE allocation attempt. Setting this mode will not affect + * any existing compute programs that may be running. For example, + * if this mode is set while three compute programs are running, then + * all of those programs will be allowed to continue running. However, + * until they all finish running, no new NV50_COMPUTE objects may be + * allocated. User-mode clients should treat this as restricting access + * to a NV50_COMPUTE object to a single thread within a process. + * + * NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED + * This mode means that that GPU is not ever allowed to instantiate an + * NV50_COMPUTE object, and thus cannot run any new compute programs. + * This restriction is enforced at each subsequent NV50_COMPUTE object + * allocation attempt. Setting this mode will not affect any existing + * compute programs that may be running. For example, if this mode is + * set while three compute programs are running, then all of those + * programs will be allowed to continue running. However, no new + * NV50_COMPUTE objects may be allocated. + * + * + * NV2080_CTRL_GPU_COMPUTE_MODE_EXCLUSIVE_COMPUTE_PROCESS + * This mode is identical to EXCLUSIVE_COMPUTE, where only one instance + * of NV50_COMPUTE will be allowed at a time. It is separate from + * EXCLUSIVE_COMPUTE to allow user-mode clients to differentiate + * exclusive access to a compute object from a single thread of a + * process from exclusive access to a compute object from all threads + * of a process. User-mode clients should not limit access to a + * NV50_COMPUTE object to a single thread when the GPU is set to + * EXCLUSIVE_COMPUTE_PROCESS. + * + * An invalid rules parameter value results in the return of an + * NV_ERR_INVALID_ARGUMENT status. + * + * flags + * Reserved. Caller should set this field to zero. + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT (if an invalid rule number is provided) + * NV_ERR_INSUFFICIENT_PERMISSIONS (if the user is not the Administrator or superuser) + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES (0x20800130U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID" */ + +/* valid rules parameter values */ +#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE (0x00000000U) +#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE (0x00000001U) +#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED (0x00000002U) +#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE_PROCESS (0x00000003U) + +#define NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID (0x30U) + +typedef struct NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS { + NvU32 rules; + NvU32 flags; +} NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES + * + * This command queries the compute mode rules for the associated subdevice. + * Please see the NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES command, above, for + * details as to what the rules mean. + * + * rules + * Specifies the rules that govern the GPU, with respect to NV50_COMPUTE + * objects. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES (0x20800131U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID (0x31U) + +typedef struct NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS { + NvU32 rules; +} NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION + * + * This command returns the current ECC configuration setting for + * a GPU given its subdevice handle. The value returned is + * the current ECC setting for the GPU stored in non-volatile + * memory on the board. + * + * currentConfiguration + * The current ECC configuration setting. + * + * defaultConfiguration + * The factory default ECC configuration setting. + * + * Please see the NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS command if + * you wish to determine if ECC is currently enabled. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION (0x20800133U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLED (0x00000000U) +#define NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLED (0x00000001U) + +#define NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID (0x33U) + +typedef struct NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS { + NvU32 currentConfiguration; + NvU32 defaultConfiguration; +} NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_SET_ECC_CONFIGURATION + * + * This command changes the ECC configuration setting for a GPU + * given its subdevice handle. The value specified is + * stored in non-volatile memory on the board and will take + * effect with the next GPU reset + * + * newConfiguration + * The new configuration setting to take effect with + * the next GPU reset. + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_SET_ECC_CONFIGURATION (0x20800134U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLE (0x00000000U) +#define NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLE (0x00000001U) + +#define NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID (0x34U) + +typedef struct NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS { + NvU32 newConfiguration; +} NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS + * + * This command resets volatile and/or persistent ECC error + * status information for a GPU given its subdevice + * handle. + * + * statuses + * The ECC error statuses (the current, volatile + * and/or the persistent error counter(s)) to + * be reset by the command. + * flags + * FORCE_PURGE + * Forcibly clean all the ECC InfoROM state if this flag is set + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS (0x20800136U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_ECC_ERROR_STATUS_NONE (0x00000000U) +#define NV2080_CTRL_GPU_ECC_ERROR_STATUS_VOLATILE (0x00000001U) +#define NV2080_CTRL_GPU_ECC_ERROR_STATUS_AGGREGATE (0x00000002U) + +#define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE 0:0 +#define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_FALSE 0U +#define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_TRUE 1U + +#define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID (0x36U) + +typedef struct NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS { + NvU32 statuses; + NvU8 flags; +} NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_FERMI_GPC_INFO + * + * This command returns a mask of enabled GPCs for the associated GPU. + * + * gpcMask + * This parameter returns a mask of enabled GPCs. Each GPC has an ID + * that's equivalent to the corresponding bit position in the mask. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_GPU_GET_FERMI_GPC_INFO (0x20800137U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID (0x37U) + +typedef struct NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS { + NvU32 gpcMask; +} NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_FERMI_TPC_INFO + * + * This command returns a mask of enabled TPCs for a specified GPC. + * + * gpcId + * This parameter specifies the GPC for which TPC information is + * to be retrieved. If the GPC with this ID is not enabled this command + * will return an tpcMask value of zero. + * + * tpcMask + * This parameter returns a mask of enabled TPCs for the specified GPC. + * Each TPC has an ID that's equivalent to the corresponding bit + * position in the mask. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_GPU_GET_FERMI_TPC_INFO (0x20800138U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID (0x38U) + +typedef struct NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS { + NvU32 gpcId; + NvU32 tpcMask; +} NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_FERMI_ZCULL_INFO + * + * This command returns a mask of enabled ZCULLs for a specified GPC. + * + * gpcId + * This parameter specifies the GPC for which ZCULL information is to be + * retrieved. If the GPC with this ID is not enabled this command will + * return an zcullMask value of zero. + * + * zcullMask + * This parameter returns a mask of enabled ZCULLs for the specified GPC. + * Each ZCULL has an ID that's equivalent to the corresponding bit + * position in the mask. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_PARAM_STRUCT + * + * Deprecated: Please use GR based control call + * NV2080_CTRL_CMD_GR_GET_ZCULL_MASK + * + */ +#define NV2080_CTRL_CMD_GPU_GET_FERMI_ZCULL_INFO (0x20800139U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID (0x39U) + +typedef struct NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS { + NvU32 gpcId; + NvU32 zcullMask; +} NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO + * + * If an InfoROM with a valid OEM Board Object is present, this + * command returns relevant information from the object to the + * caller. + * + * The following data are currently reported: + * + * buildDate + * The board's build date (8 digit BCD in format YYYYMMDD). + * + * marketingName + * The board's marketing name (24 ASCII letters e.g. "Quadro FX5800"). + * + * boardSerialNumber + * The board's serial number. + * + * memoryManufacturer + * The board's memory manufacturer ('S'amsung/'H'ynix/'I'nfineon). + * + * memoryDateCode + * The board's memory datecode (LSB justified ASCII field with 0x00 + * denoting empty space). + * + * productPartNumber + * The board's 900 product part number (LSB justified ASCII field with 0x00 + * denoting empty space e.g. "900-21228-0208-200"). + * + * boardRevision + * The board's revision (for e.g. A02, B01) + * + * boardType + * The board's type ('E'ngineering/'P'roduction) + * + * board699PartNumber + * The board's 699 product part number (LSB justified ASCII field with 0x00 + * denoting empty space e.g. "699-21228-0208-200"). + * + * board965PartNumber + * The board's 965 product part number (LSB justified ASCII field with 0x00 + * denoting empty space e.g. "965-21228-0208-200"). + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO (0x2080013fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_GPU_MAX_MARKETING_NAME_LENGTH (0x00000018U) +#define NV2080_GPU_MAX_SERIAL_NUMBER_LENGTH (0x00000010U) +#define NV2080_GPU_MAX_MEMORY_PART_ID_LENGTH (0x00000014U) +#define NV2080_GPU_MAX_MEMORY_DATE_CODE_LENGTH (0x00000006U) +#define NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH (0x00000014U) + +#define NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID (0x3FU) + +typedef struct NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS { + NvU32 buildDate; + NvU8 marketingName[NV2080_GPU_MAX_MARKETING_NAME_LENGTH]; + NvU8 serialNumber[NV2080_GPU_MAX_SERIAL_NUMBER_LENGTH]; + NvU8 memoryManufacturer; + NvU8 memoryPartID[NV2080_GPU_MAX_MEMORY_PART_ID_LENGTH]; + NvU8 memoryDateCode[NV2080_GPU_MAX_MEMORY_DATE_CODE_LENGTH]; + NvU8 productPartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH]; + NvU8 boardRevision[3]; + NvU8 boardType; + NvU8 board699PartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH]; + NvU8 board965PartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH]; +} NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GPU_GET_ID + * + * This command returns the gpuId of the associated object. + * + * gpuId + * This field return the gpuId. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_ID (0x20800142U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID (0x42U) + +typedef struct NV2080_CTRL_GPU_GET_ID_PARAMS { + NvU32 gpuId; +} NV2080_CTRL_GPU_GET_ID_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE + * + * This command is used to enable or disable GPU debug mode. While this mode + * is enabled, some client RM calls that can potentially timeout return + * NV_ERR_BUSY_RETRY, signalling the client to try again once GPU + * debug mode is disabled. + * + * mode + * This parameter specifies whether GPU debug mode is to be enabled or + * disabled. Possible values are: + * + * NV2080_CTRL_GPU_DEBUG_MODE_ENABLED + * NV2080_CTRL_GPU_DEBUG_MODE_DISABLED + * + * Possible return status values are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE (0x20800143U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID (0x43U) + +typedef struct NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS { + NvU32 mode; +} NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS; + +#define NV2080_CTRL_GPU_DEBUG_MODE_ENABLED (0x00000001U) +#define NV2080_CTRL_GPU_DEBUG_MODE_DISABLED (0x00000002U) + +/* + * NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE + * + * This command is used to query whether debug mode is enabled on the current + * GPU. Please see the description of NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE + * for more details on GPU debug mode. + * + * currentMode + * This parameter returns the state of GPU debug mode for the current GPU. + * Possible values are: + * + * NV2080_CTRL_GPU_DEBUG_MODE_ENABLED + * NV2080_CTRL_GPU_DEBUG_MODE_DISABLED + * + * Possible return status values are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE (0x20800144U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID (0x44U) + +typedef struct NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS { + NvU32 currentMode; +} NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST + * + * Returns a list of engines that can partner or coexist + * when using the target channel or partnership class. + * This list may include all engines (pre-Kepler), or as few + * as 1 engine (Kepler and beyond). + * + * engineType + * This field specifies the target engine type. + * See cl2080.h for a list of valid engines. + * + * partnershipClassId + * This field specifies the target channel + * or partnership class ID. + * An example of such a class is GF100_CHANNEL_GPFIFO. + * + * runqueue + * This field is an index which indicates the runqueue to + * return the list of supported engines for. This is the + * same field as what NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE + * specifies. This is only valid for TSG. + * + * numPartners; + * This field returns the number of + * valid entries in the partnersList array + * + * partnerList + * This field is an array containing the list of supported + * partner engines types, in no particular order, and + * may even be empty (numPartners = 0). + * See cl2080.h for a list of possible engines. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST (0x20800147U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID" */ + +/* this macro specifies the maximum number of partner entries */ +#define NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS (0x00000020U) + +#define NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID (0x47U) + +typedef struct NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS { + NvU32 engineType; + NvU32 partnershipClassId; + NvU32 runqueue; + NvU32 numPartners; + // C form: NvU32 partnerList[NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS]; + NvU32 partnerList[NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS]; +} NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GPU_GET_GID_INFO + * + * This command returns the GPU ID (GID) string for the associated + * GPU. This value can be useful for GPU identification and security + * system validation. + * + * The GPU ID is a SHA-1 based 16 byte ID, formatted as a 32 character + * hexadecimal string as "GPU-%08x-%04x-%04x-%04x-%012x" (the + * canonical format of a UUID) + * + * The GPU IDs are generated using the ECID, PMC_BOOT_0, and + * PMC_BOOT_42 of the GPU as the hash message. + * + * index + * Index is ignored for GPU UUID. If MODE_UGPU is set in flags, index specifies + * the which uGPU ID should be returned. + * + * flags (Input) The _FORMAT* flags designate ascii or binary format. Binary + * format returns the raw bytes of either the 16-byte SHA-1 ID or the + * 32-byte SHA-256 ID. + * + * The _TYPE* flags needs to specify the _SHA1 type. + * + * The _MODE* flags specify what type of GID to produce. + * + * length + * (Output) Actual GID length, in bytes. + * + * data[NV2080_BUS_MAX_GID_LENGTH] + * (Output) Result buffer: the GID itself, in a format that is determined by + * the "flags" field (described above). + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_PARAMETER + * NV_ERR_INVALID_INDEX + */ +#define NV2080_CTRL_CMD_GPU_GET_GID_INFO (0x2080014aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID" */ + +/* maximum possible number of bytes of GID information returned */ +#define NV2080_GPU_MAX_GID_LENGTH (0x000000100ULL) + +/* maximum possible number of bytes of GID information returned if given the BINARY and SHA1 flags */ +#define NV2080_GPU_MAX_SHA1_BINARY_GID_LENGTH (0x000000010ULL) + +#define NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID (0x4AU) + +typedef struct NV2080_CTRL_GPU_GET_GID_INFO_PARAMS { + NvU32 index; + NvU32 flags; + NvU32 length; + NvU8 data[NV2080_GPU_MAX_GID_LENGTH]; +} NV2080_CTRL_GPU_GET_GID_INFO_PARAMS; + +/* valid flags values */ +#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT 1:0 +#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_ASCII (0x00000000U) +#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_BINARY (0x00000002U) + +#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE 2:2 +#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE_SHA1 (0x00000000U) + +#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_MODE 5:3 +#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_MODE_GPU (0x00000000U) +#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_MODE_UGPU (0x00000001U) + +/* + * NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION + * + * This command can be used by clients to retrieve the version of an + * InfoROM object. + * + * objectType + * This parameter specifies the name of the InfoROM object whose version + * should be queried. + * + * version + * This parameter returns the version of the InfoROM object specified by + * the objectType parameter. + * + * subversion + * This parameter returns the subversion of the InfoROM object specified + * by the objectType parameter. + * + * Possible return status values: + * NV_OK + * NV_ERR_STATE_IN_USE + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION (0x2080014bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_INFOROM_OBJ_TYPE_LEN 3U + +#define NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID (0x4BU) + +typedef struct NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS { + char objectType[NV2080_CTRL_GPU_INFOROM_OBJ_TYPE_LEN]; + NvU8 version; + NvU8 subversion; +} NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS; + + +/* + * NV2080_CTRL_CMD_SET_GPU_OPTIMUS_INFO + * + * This command will specify that system is Optimus enabled. + * + * isOptimusEnabled + * Set NV_TRUE if system is Optimus enabled. + * + * Possible status return values are: + * NV_OK + */ +#define NV2080_CTRL_CMD_SET_GPU_OPTIMUS_INFO (0x2080014cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID (0x4CU) + +typedef struct NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS { + NvBool isOptimusEnabled; +} NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_IP_VERSION + * + * Will return the IP VERSION on the given engine for engines that support + * this capability. + * + * targetEngine + * This parameter specifies the target engine type to query for IP_VERSION. + * + * ipVersion + * This parameter returns the IP VERSION read from the unit's IP_VER + * register. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_GPU_GET_IP_VERSION (0x2080014dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID (0x4DU) + +typedef struct NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS { + NvU32 targetEngine; + NvU32 ipVersion; +} NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS; + +#define NV2080_CTRL_GPU_GET_IP_VERSION_DISPLAY (0x00000001U) +#define NV2080_CTRL_GPU_GET_IP_VERSION_HDACODEC (0x00000002U) +#define NV2080_CTRL_GPU_GET_IP_VERSION_PMGR (0x00000003U) +#define NV2080_CTRL_GPU_GET_IP_VERSION_PPWR_PMU (0x00000004U) +#define NV2080_CTRL_GPU_GET_IP_VERSION_DISP_FALCON (0x00000005U) + +/* + * NV2080_CTRL_CMD_GPU_ID_ILLUM_SUPPORT + * + * This command returns an indicator which reports if the specified Illumination control + * attribute is supported + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_GPU_ILLUM_ATTRIB_LOGO_BRIGHTNESS 0U +#define NV2080_CTRL_GPU_ILLUM_ATTRIB_SLI_BRIGHTNESS 1U +#define NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT (0x20800153U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID (0x53U) + +typedef struct NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS { + NvU32 attribute; + NvBool bSupported; +} NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_ID_ILLUM + * + * This command returns the current value of the specified Illumination control attribute. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_ILLUM (0x20800154U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ILLUM_PARAMS_MESSAGE_ID" */ + +typedef struct NV2080_CTRL_CMD_GPU_ILLUM_PARAMS { + NvU32 attribute; + NvU32 value; +} NV2080_CTRL_CMD_GPU_ILLUM_PARAMS; + +#define NV2080_CTRL_GPU_GET_ILLUM_PARAMS_MESSAGE_ID (0x54U) + +typedef NV2080_CTRL_CMD_GPU_ILLUM_PARAMS NV2080_CTRL_GPU_GET_ILLUM_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_SET_ID_ILLUM + * + * This command sets a new valuefor the specified Illumination control attribute. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_SET_ILLUM (0x20800155U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID (0x55U) + +typedef NV2080_CTRL_CMD_GPU_ILLUM_PARAMS NV2080_CTRL_GPU_SET_ILLUM_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION + * + * This command can be used by clients to retrieve the version of the entire + * InfoROM image. + * + * version + * This parameter returns the version of the InfoROM image as a NULL- + * terminated character string of the form "XXXX.XXXX.XX.XX" where each + * 'X' is an integer character. + * + * Possible status return values are: + * NVOS_STATUS_SUCCES + * NV_ERR_INSUFFICIENT_RESOURCES + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_DATA + */ +#define NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION (0x20800156U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_INFOROM_IMAGE_VERSION_LEN 16U + +#define NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID (0x56U) + +typedef struct NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS { + NvU8 version[NV2080_CTRL_GPU_INFOROM_IMAGE_VERSION_LEN]; +} NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT + * + * This command returns whether or not ECC is supported via the InfoROM. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT (0x20800157U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x57" */ + +/* + * NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION + * + * This structure contains information about a single physical bridge. + * + * fwVersion + * This field specifies Firmware Version of the bridge stored in + * bridge EEPROM. + * oemVersion + * This field specifies Oem Version of the firmware stored in + * bridge EEPROM. + * siliconRevision + * This field contains the silicon revision of the bridge hardware. + * It is set by the chip manufacturer. + * hwbcResourceType + * This field specifies the hardware broadcast resource type. + * Value denotes the kind of bridge - PLX or BR04 + * + */ + +typedef struct NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS { + NvU32 fwVersion; + NvU8 oemVersion; + NvU8 siliconRevision; + NvU8 hwbcResourceType; +} NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO + * + * This command returns physical bridge information in the system. + * Information consists of bridgeCount and a list of bridgeId's. + * The bridge Id's are used by NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION + * to get firmware version, oem version and silicon revision info. + * + * bridgeCount + * This field specifies the number of physical brides present + * in the system. + * hPhysicalBridges + * This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE. + * In this array, the bridge Id's are stored. + * bridgeList + * This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE. + * In this array, the bridge version details are stored. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO (0x2080015aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MAX_PHYSICAL_BRIDGE (100U) +#define NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID (0x5AU) + +typedef struct NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS { + NvU8 bridgeCount; + NvHandle hPhysicalBridges[NV2080_CTRL_MAX_PHYSICAL_BRIDGE]; + NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS bridgeList[NV2080_CTRL_MAX_PHYSICAL_BRIDGE]; +} NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS; + +/* + * NV2080_CTRL_GPU_BRIDGE_VERSION + * + * This structure contains information about a single physical bridge. + * + * bus + * This field specifies the bus id of the bridge. + * device + * This field specifies the device id of the bridge. + * func + * This field specifies the function id of the bridge. + * oemVersion + * This field specifies Oem Version of the firmware stored in + * bridge EEPROM. + * siliconRevision + * This field contains the silicon revision of the bridge hardware. + * It is set by the chip manufacturer. + * hwbcResourceType + * This field specifies the hardware broadcast resource type. + * Value denotes the kind of bridge - PLX or BR04 + * domain + * This field specifies the respective domain of the PCI device. + * fwVersion + * This field specifies Firmware Version of the bridge stored in + * bridge EEPROM. + * + * If (fwVersion, oemVersion, siliconRevision) == 0, it would mean that RM + * was unable to fetch the value from the bridge device. + * + */ + +typedef struct NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS { + NvU8 bus; + NvU8 device; + NvU8 func; + NvU8 oemVersion; + NvU8 siliconRevision; + NvU8 hwbcResourceType; + NvU32 domain; + NvU32 fwVersion; +} NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU + * + * This command returns information about all the upstream bridges of the GPU. + * Information consists of bridge firmware version and its bus topology. + * + * bridgeCount + * This field specifies the number of physical brides present + * in the system. + * physicalBridgeIds + * This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE. + * In this array, the bridge Ids are stored. + * bridgeList + * This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE. + * In this array, the bridge version details are stored. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU (0x2080015bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID (0x5BU) + +typedef struct NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS { + NvU8 bridgeCount; + NvU32 physicalBridgeIds[NV2080_CTRL_MAX_PHYSICAL_BRIDGE]; + NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS bridgeList[NV2080_CTRL_MAX_PHYSICAL_BRIDGE]; +} NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS + * + * This command is used to query the status of the HW scrubber. If a scrub is + * in progress then the range which is being scrubbed is also reported back. + * + * scrubberStatus + * Reports the status of the scrubber unit - running/idle. + * + * remainingtimeMs + * If scrubbing is going on, reports the remaining time in milliseconds + * required to finish the scrub. + * + * scrubStartAddr + * This parameter reports the start address of the ongoing scrub if scrub + * is going on, otherwise reports the start addr of the last finished scrub + * + * scrubEndAddr + * This parameter reports the end address of the ongoing scrub if scrub + * is going on, otherwise reports the end addr of the last finished scrub. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS (0x2080015fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID (0x5FU) + +typedef struct NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS { + NvU32 scrubberStatus; + NvU32 remainingTimeMs; + NV_DECLARE_ALIGNED(NvU64 scrubStartAddr, 8); + NV_DECLARE_ALIGNED(NvU64 scrubEndAddr, 8); +} NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS; + +/* valid values for scrubber status */ +#define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_RUNNING (0x00000000U) +#define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_IDLE (0x00000001U) + +/* + * NV2080_CTRL_CMD_GPU_GET_VPR_CAPS + * + * This command is used to query the VPR capability information for a + * GPU. If VPR is supported, the parameters are filled accordingly. + * The addresses returned are all physical addresses. + * + * minStartAddr + * Returns the minimum start address that can be possible for VPR. + * + * maxEndAddr + * Returns the maximum end address that can be possible for VPR. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_GPU_GET_VPR_CAPS (0x20800160U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID (0x60U) + +typedef struct NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 minStartAddr, 8); + NV_DECLARE_ALIGNED(NvU64 maxEndAddr, 8); +} NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GPU_HANDLE_GPU_SR + * + * Communicates to RM to handle GPU Surprise Removal + * Called from client when it receives SR IRP from OS + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + */ +#define NV2080_CTRL_CMD_GPU_HANDLE_GPU_SR (0x20800167U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x67" */ + + +/* + * NV2080_CTRL_CMD_GPU_GET_PES_INFO + * + * This command provides the PES count and mask of enabled PES for a + * specified GPC. It also returns the TPC to PES mapping information + * for a given GPU. + * + * gpcId[IN] + * This parameter specifies the GPC for which PES information is to be + * retrieved. If the GPC with this ID is not enabled this command will + * return an activePesMask of zero + * + * numPesInGpc[OUT] + * This parameter returns the number of PES in this GPC. + * + * activePesMask[OUT] + * This parameter returns a mask of enabled PESs for the specified GPC. + * Each PES has an ID that is equivalent to the corresponding bit position + * in the mask. + * + * maxTpcPerGpcCount[OUT] + * This parameter returns the max number of TPCs in a GPC. + * + * tpcToPesMap[OUT] + * This array stores the TPC to PES mappings. The value at tpcToPesMap[tpcIndex] + * is the index of the PES it belongs to. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_PES_INFO (0x20800168U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_GPU_GET_PES_INFO_MAX_TPC_PER_GPC_COUNT 10U + +#define NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID (0x68U) + +typedef struct NV2080_CTRL_GPU_GET_PES_INFO_PARAMS { + NvU32 gpcId; + NvU32 numPesInGpc; + NvU32 activePesMask; + NvU32 maxTpcPerGpcCount; + NvU32 tpcToPesMap[NV2080_CTRL_CMD_GPU_GET_PES_INFO_MAX_TPC_PER_GPC_COUNT]; +} NV2080_CTRL_GPU_GET_PES_INFO_PARAMS; + +/* NV2080_CTRL_CMD_GPU_GET_OEM_INFO + * + * If an InfoROM with a valid OEM Object is present, this + * command returns relevant information from the object to the + * caller. + * + * oemInfo + * This array stores information specifically for OEM use + * (e.g. "their own serial number", "lot codes", etc) + * "The byte definition is up to the OEM" + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_GPU_GET_OEM_INFO (0x20800169U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_GPU_MAX_OEM_INFO_LENGTH (0x000001F8U) + +#define NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID (0x69U) + +typedef struct NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS { + NvU8 oemInfo[NV2080_GPU_MAX_OEM_INFO_LENGTH]; +} NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_VPR_INFO + * + * This command is used to query the VPR information for a GPU. + * The following VPR related information can be queried by selecting the queryType: + * 1. The current VPR range. + * 2. The max VPR range ever possible on this GPU. + * + * queryType [in] + * This input parameter is used to select the type of information to query. + * Possible values for this parameter are: + * 1. NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS: Use this to query the + * max VPR range ever possible on this GPU. + * 2. NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE: Use this to query + * the current VPR range on this GPU. + * + * bVprEnabled [out] + * For query type "NV2080_CTRL_GPU_GET_VPR_INFO_CUR_RANGE", this parameter + * returns if VPR is currently enabled or not. + * + * vprStartAddress [out] + * For NV2080_CTRL_GPU_GET_VPR_INFO_CAPS, it returns minimum allowed VPR start address. + * For NV2080_CTRL_GPU_GET_VPR_INFO_RANGE, it returns current VPR start address. + * + * vprEndAddress [out] + * For NV2080_CTRL_GPU_GET_VPR_INFO_CAPS, it returns maximum allowed VPR end address. + * For NV2080_CTRL_GPU_GET_VPR_INFO_RANGE, it returns current VPR end address. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_VPR_INFO (0x2080016bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID" */ + + +typedef enum NV2080_CTRL_VPR_INFO_QUERY_TYPE { + NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS = 0, + NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE = 1, +} NV2080_CTRL_VPR_INFO_QUERY_TYPE; + +#define NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID (0x6BU) + +typedef struct NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS { + NV2080_CTRL_VPR_INFO_QUERY_TYPE queryType; + NvBool bIsVprEnabled; + NV_DECLARE_ALIGNED(NvU64 vprStartAddressInBytes, 8); + NV_DECLARE_ALIGNED(NvU64 vprEndAddressInBytes, 8); +} NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_ENCODER_CAPACITY + * + * This command is used to query the encoder capacity of the GPU. + * + * queryType [in] + * This input parameter is used to select the type of information to query. + * Possible values for this parameter are: + * 1. NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264: Use this to query the + * H.264 encoding capacity on this GPU. + * 2. NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC: Use this to query the + * H.265/HEVC encoding capacity on this GPU. + * 3. NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1: Use this to query the + * AV1 encoding capacity on this GPU. + * + * encoderCapacity [out] + * Encoder capacity value from 0 to 100. Value of 0x00 indicates encoder performance + * may be minimal for this GPU and software should fall back to CPU-based encode. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_GPU_GET_ENCODER_CAPACITY (0x2080016cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE { + NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264 = 0, + NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC = 1, + NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1 = 2, +} NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE; + +#define NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID (0x6CU) + +typedef struct NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS { + NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE queryType; + NvU32 encoderCapacity; +} NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS; + +/* + * NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS + * + * This command is used to retrieve the GPU's count of encoder sessions, + * trailing average FPS and encode latency over all active sessions. + * + * encoderSessionCount + * This field specifies count of all active encoder sessions on this GPU. + * + * averageEncodeFps + * This field specifies the average encode FPS for this GPU. + * + * averageEncodeLatency + * This field specifies the average encode latency in microseconds for this GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS (0x2080016dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID (0x6DU) + +typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS { + NvU32 encoderSessionCount; + NvU32 averageEncodeFps; + NvU32 averageEncodeLatency; +} NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS; + +#define NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES 0x200U // 512 entries. + +/* + * NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO + * + * This command returns NVENC software sessions information for the associate GPU. + * Request to retrieve session information use a list of one or more + * NV2080_CTRL_NVENC_SW_SESSION_INFO structures. + * + * sessionInfoTblEntry + * This field specifies the number of entries on the that are filled inside + * sessionInfoTbl. Max value of this field once returned from RM would be + * NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES, + * + * sessionInfoTbl + * This field specifies a pointer in the caller's address space + * to the buffer into which the NVENC session information is to be returned. + * When buffer is NULL, RM assume that client is querying sessions count value + * and return the current encoder session counts in sessionInfoTblEntry field. + * To get actual buffer data, client should allocate sessionInfoTbl of size + * NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES multiplied by the + * size of the NV2080_CTRL_NVENC_SW_SESSION_INFO structure. RM will fill the + * current session data in sessionInfoTbl buffer and then update the + * sessionInfoTblEntry to reflect current session count value. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NO_MEMORY + * NV_ERR_INVALID_LOCK_STATE + * NV_ERR_INVALID_ARGUMENT + */ + +typedef struct NV2080_CTRL_NVENC_SW_SESSION_INFO { + NvU32 processId; + NvU32 subProcessId; + NvU32 sessionId; + NvU32 codecType; + NvU32 hResolution; + NvU32 vResolution; + NvU32 averageEncodeFps; + NvU32 averageEncodeLatency; +} NV2080_CTRL_NVENC_SW_SESSION_INFO; + +#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS_MESSAGE_ID (0x6EU) + +typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS { + NvU32 sessionInfoTblEntry; + NV_DECLARE_ALIGNED(NvP64 sessionInfoTbl, 8); +} NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS; + +#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO (0x2080016eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR + * + * The command sets fabric base address which represents top N bits of a + * peer memory address. These N bits will be used to index NvSwitch routing + * tables to forward peer memory accesses to associated GPUs. + * + * The command is available to clients with administrator privileges only. + * An attempt to use this command by a client without administrator privileged + * results in the return of NV_ERR_INSUFFICIENT_PERMISSIONS status. + * + * The command allows to set fabricAddr once in a lifetime of a GPU. A GPU must + * be destroyed in order to re-assign a different fabricAddr. An attempt to + * re-assign address without destroying a GPU would result in the return of + * NV_ERR_STATE_IN_USE status. + * + * fabricBaseAddr[IN] + * - An address with at least 32GB alignment. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_NOT_SUPPORTED + * NV_ERR_STATE_IN_USE + */ + +#define NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID (0x6FU) + +typedef struct NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS { + NV_DECLARE_ALIGNED(NvU64 fabricBaseAddr, 8); +} NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS; + +#define NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR (0x2080016fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT + * + * The command will trigger the specified interrupt on the host from a guest. + * + * handle[IN] + * - An opaque handle that will be passed in along with the interrupt + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS_MESSAGE_ID (0x72U) + +typedef struct NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS { + NvU32 handle; +} NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS; + +#define NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT (0x20800172U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS + * + * This control call is to query the status of gpu function registers + * + * statusMask[IN] + * - Input mask of required status registers + * xusbData[OUT] + * - data from querying XUSB status register + * ppcData[OUT] + * - data from querying PPC status register + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + + + +#define NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS_MESSAGE_ID (0x73U) + +typedef struct NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS { + NvU32 statusMask; + NvU32 xusbData; + NvU32 ppcData; +} NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS; + +#define NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS (0x20800173U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_GPU_PARTITION_SPAN + * + * This struct represents the span of a memory partition, which represents the + * slices a given partition occupies (or may occupy) within a fixed range which + * is defined per-chip. A partition containing more resources will cover more + * GPU slices and therefore cover a larger span. + * + * lo + * - The starting unit of this span, inclusive + * + * hi + * - The ending unit of this span, inclusive + * + */ +typedef struct NV2080_CTRL_GPU_PARTITION_SPAN { + NV_DECLARE_ALIGNED(NvU64 lo, 8); + NV_DECLARE_ALIGNED(NvU64 hi, 8); +} NV2080_CTRL_GPU_PARTITION_SPAN; + +/* + * NV2080_CTRL_EXEC_PARTITION_SPAN + * + * This struct represents the span of a compute partition, which represents the + * slices a given partition occupies (or may occupy) within a fixed range which + * is defined memory partition. A partition containing more resources will cover + * more GPU instance slices and therefore cover a larger span. + * + * lo + * - The starting unit of this span, inclusive + * + * hi + * - The ending unit of this span, inclusive + * + */ +typedef struct NV2080_CTRL_EXEC_PARTITION_SPAN { + NV_DECLARE_ALIGNED(NvU64 lo, 8); + NV_DECLARE_ALIGNED(NvU64 hi, 8); +} NV2080_CTRL_EXEC_PARTITION_SPAN; + +#define NV_GI_UUID_LEN 16U + +/* + * NV2080_CTRL_GPU_SET_PARTITION_INFO + * + * This command partitions a GPU into different SMC-Memory partitions. + * The command will configure HW partition table to create work and memory + * isolation. + * + * The command is available to clients with administrator privileges only. + * An attempt to use this command by a client without administrator privileged + * results in the return of NV_ERR_INSUFFICIENT_PERMISSIONS status. + * + * The command allows partitioning an invalid partition only. An attempt to + * re-partition a valid partition will resule in NV_ERR_STATE_IN_USE. + * Repartitioning can be done only if a partition has been destroyed/invalidated + * before re-partitioning. + * + * swizzId[IN/OUT] + * - PartitionID associated with a newly created partition. Input in case + * of partition invalidation. + * + * uuid[OUT] + * - Uuid of a newly created partition. + * + * partitionFlag[IN] + * - Flags to determine if GPU is requested to be partitioned in FULL, + * HALF, QUARTER or ONE_EIGHTHED and whether the partition requires + * any additional resources. + * When flags include NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA + * partition will be created with at least one video decode, jpeg and + * optical flow engines. This flag is valid only for partitions with + * a single GPC. + * + * bValid[IN] + * - NV_TRUE if creating a partition. NV_FALSE if destroying a partition. + * + * placement[IN] + * - Optional placement span to allocate the partition into. Valid + * placements are returned from NV2080_CTRL_CMD_GPU_GET_PARTITION_CAPACITY. + * The partition flag NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN must + * be set for this parameter to be used. If the flag is set and the given + * placement is not valid, an error will be returned. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_NOT_SUPPORTED + * NV_ERR_STATE_IN_USE + */ +typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO { + NvU32 swizzId; + NvU8 uuid[NV_GI_UUID_LEN]; + NvU32 partitionFlag; + NvBool bValid; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN placement, 8); +} NV2080_CTRL_GPU_SET_PARTITION_INFO; + +#define PARTITIONID_INVALID NV2080_CTRL_GPU_PARTITION_ID_INVALID +#define NV2080_CTRL_GPU_PARTITION_ID_INVALID 0xFFFFFFFFU +#define NV2080_CTRL_GPU_MAX_PARTITIONS 0x00000008U +#define NV2080_CTRL_GPU_MAX_PARTITION_IDS 0x00000009U +#define NV2080_CTRL_GPU_MAX_SMC_IDS 0x00000008U +#define NV2080_CTRL_GPU_MAX_GPC_PER_SMC 0x00000040U +#define NV2080_CTRL_GPU_MAX_CE_PER_SMC 0x00000008U + +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE 1:0 +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL 0x00000000U +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF 0x00000001U +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER 0x00000002U +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH 0x00000003U +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE 4U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE 4:2 +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL 0x00000000U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF 0x00000001U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF 0x00000002U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER 0x00000003U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER 0x00000004U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH 0x00000005U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_06 0x00000006U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_07 0x00000007U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE 8U + + + +#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE 7:5 +#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_FULL 0x00000001U +#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_HALF 0x00000002U +#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_MINI_HALF 0x00000003U +#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_QUARTER 0x00000004U +#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_EIGHTH 0x00000005U +#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_RESERVED_INTERNAL_06 0x00000006U +#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_RESERVED_INTERNAL_07 0x00000007U + +#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_NONE 0x00000000U +#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE__SIZE 8U + + +#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 90U + +#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA 29:28 +#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA_DEFAULT 0U +#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA_DISABLE 1U +#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA_ENABLE 2U + + +#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA 30:30 +#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE 0U +#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE 1U +#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN 31:31 +#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE 0U +#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE 1U + +// TODO XXX Bug 2657907 Remove these once clients update +#define NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _FULL) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _FULL)) +#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _HALF) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _HALF)) +#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _HALF) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _MINI_HALF)) +#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _QUARTER) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _QUARTER)) +#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _QUARTER) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _MINI_QUARTER)) +#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _EIGHTH) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _EIGHTH)) + +#define NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID (0x74U) + +typedef struct NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS { + NvU32 partitionCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_SET_PARTITION_INFO partitionInfo[NV2080_CTRL_GPU_MAX_PARTITIONS], 8); +} NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS; + +#define NV2080_CTRL_CMD_GPU_SET_PARTITIONS (0x20800174U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_GPU_GET_PARTITION_INFO + * + * This command gets the partition information for requested partitions. + * If GPU is not partitioned, the control call will return NV_ERR_NOT_SUPPORTED. + * + * The command will can return global partition information as well as single + * partition information if global flag is not set. + * In bare-metal user-mode can request all partition info while in virtualization + * plugin should make an RPC with swizzId which is assigned to the requesting + * VM. + * + * swizzId[IN] + * - HW Partition ID associated with the requested partition. + * + * partitionFlag[OUT] + * - partitionFlag that was provided during partition creation. + * + * grEngCount[OUT] + * - Number of SMC engines/GR engines allocated in partition + * GrIDs in a partition will always start from 0 and end at grEngCount-1 + * + * veidCount[OUT] + * - VEID Count assigned to a partition. These will be divided across + * SMC engines once CONFIGURE_PARTITION call has been made. The current + * algorithm is to assign veidPerGpc * gpcCountPerSmc to a SMC engine. + * + * smCount[OUT] + * - SMs assigned to a partition. + * + * ceCount[OUT] + * - Copy Engines assigned to a partition. + * + * nvEncCount[OUT] + * - NvEnc Engines assigned to a partition. + * + * nvDecCount[OUT] + * - NvDec Engines assigned to a partition. + * + * nvJpgCount[OUT] + * - NvJpg Engines assigned to a partition. + * + * gpcCount[OUT] + * - Max GPCs assigned to a partition, including the GfxCapable ones. + * + * virtualGpcCount[OUT] + * - Virtualized GPC count assigned to partition + * + * gfxGpcCount[OUT] + * - Max GFX GPCs assigned to a partition. This is a subset of the GPCs incuded in gpcCount. + * + * gpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT] + * - GPC count associated with every valid SMC/Gr, including the GPCs capable of GFX + * + * virtualGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT] + * - Virtualized GPC count associated with every valid SMC/Gr, including the GPCs capable of GFX + * + * gfxGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT] + * - GFX GPC count associated with every valid SMC/Gr. This is a subset of the GPCs included in gfxGpcCount + * + * veidsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT] + * - VEID count associated with every valid SMC. VEIDs within this SMC + * will start from 0 and go till veidCount[SMC_ID] - 1. + * + * span[OUT] + * - The span covered by this partition + * + * bValid[OUT] + * - NV_TRUE if partition is valid else NV_FALSE. + * + * bPartitionError[OUT] + * - NV_TRUE if partition had poison error which requires drain and reset + * else NV_FALSE. + * + * validCTSIdMask[OUT] + * - Mask of CTS IDs usable by this partition, not reflecting current allocations + * + * validGfxCTSIdMask[OUT] + * - Mask of CTS IDs that contain Gfx capable Grs usable by this partition, not reflecting current allocations + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_NOT_SUPPORTED + */ +typedef struct NV2080_CTRL_GPU_GET_PARTITION_INFO { + NvU32 swizzId; + NvU32 partitionFlag; + NvU32 grEngCount; + NvU32 veidCount; + NvU32 smCount; + NvU32 ceCount; + NvU32 nvEncCount; + NvU32 nvDecCount; + NvU32 nvJpgCount; + NvU32 nvOfaCount; + NvU32 gpcCount; + NvU32 virtualGpcCount; + NvU32 gfxGpcCount; + NvU32 gpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NvU32 virtualGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NvU32 gfxGpcPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NvU32 veidsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NV_DECLARE_ALIGNED(NvU64 memSize, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN span, 8); + NvBool bValid; + NvBool bPartitionError; + NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8); + NV_DECLARE_ALIGNED(NvU64 validGfxCTSIdMask, 8); +} NV2080_CTRL_GPU_GET_PARTITION_INFO; + +/* + * NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS + * + * queryPartitionInfo[IN] + * - Max sized array of NV2080_CTRL_GPU_GET_PARTITION_INFO to get partition + * Info + * + * bGetAllPartitionInfo[In] + * - Flag to get all partitions info. Only root client will receive all + * partition's info. Non-Root clients should not use this flag + * + * validPartitionCount[Out] + * - Valid partition count which has been filled by RM as part of the call + * + */ +#define NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS_MESSAGE_ID (0x75U) + +typedef struct NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_GET_PARTITION_INFO queryPartitionInfo[NV2080_CTRL_GPU_MAX_PARTITIONS], 8); + NvU32 validPartitionCount; + NvBool bGetAllPartitionInfo; +} NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS; + +#define NV2080_CTRL_CMD_GPU_GET_PARTITIONS (0x20800175U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_GPU_CONFIGURE_PARTITION + * + * This command configures a partition by associating GPCs with SMC Engines + * available in that partition. Engines which are to have GPCs assigned to them + * shall not already have any GPCs assigned to them. It is not valid to both + * assign GPCs and remove GPCs as part of a single call to this function. + * + * swizzId[IN] + * - PartitionID for configuring partition. If partition has a valid + * context created, then configuration is not allowed. + * + * gpcCountPerSmcEng[IN] + * - Number of GPCs expected to be configured per SMC. Supported + * configurations are 0, 1, 2, 4 or 8. "0" means a particular SMC + * engine will be disabled with no GPC connected to it. + * + * updateSmcEngMask[IN] + * - Mask tracking valid entries of gpcCountPerSmcEng. A value of + * 0 in bit index i indicates that engine i will keep its current + * configuration. + * + * bUseAllGPCs[IN] + * - Flag specifying alternate configuration mode, indicating that in + * swizzid 0 only, all non-floorswept GPCs should be connected to the + * engine indicated by a raised bit in updateSmcEngMask. Only a single + * engine may be targeted by this operation. The gpcCountPerSmcEng + * parameter should not be used with this flag. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_INSUFFICIENT_RESOURCES + * NV_ERR_NOT_SUPPORTED + * NV_ERR_STATE_IN_USE + */ +#define NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION (0x20800176U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID (0x76U) + +typedef struct NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS { + NvU32 swizzId; + NvU32 gpcCountPerSmcEng[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NvU32 updateSmcEngMask; + NvBool bUseAllGPCs; +} NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS; + + +/* + * NV2080_CTRL_GPU_FAULT_PACKET + * + * This struct represents a GMMU fault packet. + * + */ +#define NV2080_CTRL_GPU_FAULT_PACKET_SIZE 32U +typedef struct NV2080_CTRL_GPU_FAULT_PACKET { + NvU8 data[NV2080_CTRL_GPU_FAULT_PACKET_SIZE]; +} NV2080_CTRL_GPU_FAULT_PACKET; + +/* + * NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT + * + * This command reports a nonreplayable fault packet to RM. + * It is only used by UVM. + * + * pFaultPacket[IN] + * - A fault packet that will be later cast to GMMU_FAULT_PACKET *. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_GPU_REPORT_NON_REPLAYABLE_FAULT (0x20800177U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID (0x77U) + +typedef struct NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS { + NV2080_CTRL_GPU_FAULT_PACKET faultPacket; +} NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU + * + * This command is similar to NV2080_CTRL_CMD_GPU_EXEC_REG_OPS, except it is used + * by the VGPU plugin client only. This command provides access to the subset of + * privileged registers. + * + * See confluence page "vGPU UMED Security" for details. + * + */ +#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU (0x20800178U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS_MESSAGE_ID (0x78U) + +typedef NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE + * + * This command returns the runlist pri base of the specified engine(s). + * + * engineList + * Input array. + * This array specifies the engines being queried for information. + * The list of engines supported by a chip can be fetched using the + * NV2080_CTRL_CMD_GPU_GET_ENGINES/GET_ENGINES_V2 ctrl call. + * + * runlistPriBase + * Output array. + * Returns the runlist pri base for the specified engines + * Else, will return _NULL when the input is a NV2080_ENGINE_TYPE_NULL + * and will return _ERROR when the control call fails due to an invalid argument + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE (0x20800179U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID (0x79U) + +typedef struct NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS { + NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; + NvU32 runlistPriBase[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; + NvU32 runlistId[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; +} NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS; + +#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_NULL (0xFFFFFFFFU) +#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_ERROR (0xFFFFFFFBU) +#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_INVALID (0xFFFFFFFFU) +#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_ERROR (0xFFFFFFFBU) + +/* + * NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID + * + * This command returns the host hardware defined engine ID of the specified engine(s). + * + * engineList + * Input array. + * This array specifies the engines being queried for information. + * The list of engines supported by a chip can be fetched using the + * NV2080_CTRL_CMD_GPU_GET_ENGINES/GET_ENGINES_V2 ctrl call. + * + * hwEngineID + * Output array. + * Returns the host hardware engine ID(s) for the specified engines + * Else, will return _NULL when the input is a NV2080_ENGINE_TYPE_NULL + * and will return _ERROR when the control call fails due to an invalid argument + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID (0x2080017aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID (0x7AU) + +typedef struct NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS { + NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; + NvU32 hwEngineID[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; +} NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS; + +#define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_NULL (0xFFFFFFFFU) +#define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_ERROR (0xFFFFFFFBU) + +/* + * NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS + * + * This command is used to retrieve the GPU's count of FBC sessions, + * average FBC calls and FBC latency over all active sessions. + * + * sessionCount + * This field specifies count of all active fbc sessions on this GPU. + * + * averageFPS + * This field specifies the average frames captured. + * + * averageLatency + * This field specifies the average FBC latency in microseconds. + * + * Possible status values returned are : + * NV_OK + * NV_ERR_INVALID_ARGUMENT +*/ +#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS (0x2080017bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID (0x7BU) + +typedef struct NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS { + NvU32 sessionCount; + NvU32 averageFPS; + NvU32 averageLatency; +} NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS; + +/* +* NV2080_CTRL_NVFBC_SW_SESSION_INFO +* +* processId[OUT] +* Process id of the process owning the NvFBC session. +* On VGX host, this will specify the vGPU plugin process id. +* subProcessId[OUT] +* Process id of the process owning the NvFBC session if the +* session is on VGX guest, else the value is zero. +* vgpuInstanceId[OUT] +* vGPU on which the process owning the NvFBC session +* is running if session is on VGX guest, else +* the value is zero. +* sessionId[OUT] +* Unique session id of the NvFBC session. +* sessionType[OUT] +* Type of NvFBC session. +* displayOrdinal[OUT] +* Display identifier associated with the NvFBC session. +* sessionFlags[OUT] +* One or more of NV2080_CTRL_NVFBC_SESSION_FLAG_xxx. +* hMaxResolution[OUT] +* Max horizontal resolution supported by the NvFBC session. +* vMaxResolution[OUT] +* Max vertical resolution supported by the NvFBC session. +* hResolution[OUT] +* Horizontal resolution requested by caller in grab call. +* vResolution[OUT] +* Vertical resolution requested by caller in grab call. +* averageFPS[OUT] +* Average no. of frames captured per second. +* averageLatency[OUT] +* Average frame capture latency in microseconds. +*/ + +#define NV2080_CTRL_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED 0x00000001U +#define NV2080_CTRL_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED 0x00000002U +#define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_NO_WAIT 0x00000004U +#define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_INFINITE 0x00000008U +#define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_TIMEOUT 0x00000010U + +typedef struct NV2080_CTRL_NVFBC_SW_SESSION_INFO { + NvU32 processId; + NvU32 subProcessId; + NvU32 vgpuInstanceId; + NvU32 sessionId; + NvU32 sessionType; + NvU32 displayOrdinal; + NvU32 sessionFlags; + NvU32 hMaxResolution; + NvU32 vMaxResolution; + NvU32 hResolution; + NvU32 vResolution; + NvU32 averageFPS; + NvU32 averageLatency; +} NV2080_CTRL_NVFBC_SW_SESSION_INFO; + +/* +* NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO +* +* This command returns NVFBC software sessions information for the associate GPU. +* +* sessionInfoCount +* This field specifies the number of entries that are filled inside +* sessionInfoTbl. Max value of this field once returned from RM would be +* NV2080_GPU_NVFBC_MAX_COUNT. +* +* sessionInfoTbl +* This field specifies the array in which the NVFBC session information is to +* be returned. RM will fill the current session data in sessionInfoTbl array +* and then update the sessionInfoCount to reflect current session count value. +* +* Possible status values returned are: +* NV_OK +* NV_ERR_NO_MEMORY +* NV_ERR_INVALID_LOCK_STATE +* NV_ERR_INVALID_ARGUMENT +*/ + +#define NV2080_GPU_NVFBC_MAX_SESSION_COUNT 256U + +#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID (0x7CU) + +typedef struct NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS { + NvU32 sessionInfoCount; + NV2080_CTRL_NVFBC_SW_SESSION_INFO sessionInfoTbl[NV2080_GPU_NVFBC_MAX_SESSION_COUNT]; +} NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS; + +#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO (0x2080017cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID" */ + + +/* + * NV2080_CTRL_CMD_GPU_GET_FIRST_ASYNC_CE_IDX + * + * This command returns the first async ce index + * + * CE Index + * Output parameter. + * Returns the first async ce index + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS_MESSAGE_ID (0xe6U) + +typedef struct NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS { + NvU32 firstAsyncCEIdx; +} NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS; +#define NV2080_CTRL_CMD_GPU_GET_FIRST_ASYNC_CE_IDX (0x208001e6U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS_MESSAGE_ID" */ + + +/* + * NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE + * + * This command returns the VMMU page size + * + * vmmuSegmentSize + * Output parameter. + * Returns the VMMU segment size (in bytes) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE (0x2080017eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID (0x7EU) + +typedef struct NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 vmmuSegmentSize, 8); +} NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS; + +#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_32MB 0x02000000U +#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_64MB 0x04000000U +#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_128MB 0x08000000U +#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_256MB 0x10000000U +#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_512MB 0x20000000U +#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_1024MB 0x40000000U + +/* + * NV2080_CTRL_GPU_GET_PARTITION_CAPACITY + * + * This command returns the count of partitions of given size (represented by + * NV2080_CTRL_GPU_PARTITION_FLAG_*) which can be requested via + * NV2080_CTRL_GPU_SET_PARTITIONS ctrl call. + * Note that this API does not "reserve" any partitions, and there is no + * guarantee that the reported count of available partitions of a given size + * will remain consistent following creation of partitions of different size + * through NV2080_CTRL_GPU_SET_PARTITIONS. + * Note that this API is unsupported if SMC is feature-disabled. + * + * partitionFlag[IN] + * - Partition flag indicating size of requested partitions + * + * partitionCount[OUT] + * - Available number of partitions of the given size which can currently be created. + * + * availableSpans[OUT] + * - For each partition able to be created of the specified size, the span + * it could occupy. + * + * availableSpansCount[OUT] + * - Number of valid entries in availableSpans. + * + * totalPartitionCount[OUT] + * - Total number of partitions of the given size which can be created. + * + * totalSpans[OUT] + * - List of spans which can possibly be occupied by partitions of the + * given type. + * + * totalSpansCount[OUT] + * - Number of valid entries in totalSpans. + * + * bStaticInfo[IN] + * - Flag indicating that client requests only the information from + * totalPartitionCount and totalSpans. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_PARTITION_CAPACITY (0x20800181U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS { + NvU32 partitionFlag; + NvU32 partitionCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN availableSpans[NV2080_CTRL_GPU_MAX_PARTITIONS], 8); + NvU32 availableSpansCount; + NvU32 totalPartitionCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN totalSpans[NV2080_CTRL_GPU_MAX_PARTITIONS], 8); + NvU32 totalSpansCount; + NvBool bStaticInfo; +} NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_CACHED_INFO + * + * This command returns cached(SW only) gpu information for the associated GPU. + * Requests to retrieve gpu information use a list of one or more NV2080_CTRL_GPU_INFO + * structures. + * The gpuInfoList is aligned with NV2080_CTRL_GPU_GET_INFO_V2_PARAMS for security concern + * + * gpuInfoListSize + * This field specifies the number of entries on the caller's + * gpuInfoList. + * gpuInfoList + * This field specifies a pointer in the caller's address space + * to the buffer into which the gpu information is to be returned. + * This buffer must be at least as big as gpuInfoListSize multiplied + * by the size of the NV2080_CTRL_GPU_INFO structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_OPERATING_SYSTEM + */ +#define NV2080_CTRL_CMD_GPU_GET_CACHED_INFO (0x20800182U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS_MESSAGE_ID (0x82U) + +typedef NV2080_CTRL_GPU_GET_INFO_V2_PARAMS NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS; + +/* + * NV2080_CTRL_GPU_SET_PARTITIONING_MODE + * + * This command configures this GPU to control global mode for partitioning. + * This command may not be sent to a GPU with any active partitions. + * This command may be used to set the following modes: + * + * NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING + * NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_LEGACY + * This is the default mode. While this GPU is in this mode, no partitions + * will be allowed to be created via SET_PARTITIONS - a client must set one + * of the below modes prior to partitioning the GPU. When a client sets a + * GPU into this mode, any performance changes resulting from partitions + * made while in either of the below modes will be cleared. A + * physical-function-level reset is required after setting this mode. + * + * NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_MAX_PERF + * In this mode, when the GPU is partitioned, each partition will have the + * maximum possible performance which can be evenly distributed among all + * partitions. The total performance of the GPU, taking into account all + * partitions created in this mode, may be less than that of a GPU running + * in legacy non-SMC mode. Partitions created while in this mode require a + * physical-function-level reset before the partitioning may take full + * effect. Destroying all partitions while in this mode may be + * insufficient to restore full performance to the GPU - only by setting + * the mode to _LEGACY can this be achieved. A physical-function-level + * reset is NOT required after setting this mode. + * + * NV2080_CTRL_GPU_SET_PARTIITONING_MODE_REPARTITIONING_FAST_RECONFIG + * By setting this mode, the performance of the GPU will be restricted such + * that all partitions will have a consistent fraction of the total + * available performance, which may be less than the maximum possible + * performance available to each partition. Creating or destroying + * partitions on this GPU while in this mode will not require a + * physical-function-level reset, and will not affect other active + * partitions. Destroying all partitions while in this mode may be + * insufficient to restore full performance to the GPU - only by setting + * the mode to _LEGACY can this be achieved. A physical-function-level + * reset is required after setting this mode. + * + * Parameters: + * partitioningMode[IN] + * - Partitioning Mode to set for this GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE (0x20800183U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING 1:0 +#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_LEGACY 0U +#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_MAX_PERF 1U +#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_FAST_RECONFIG 2U + +#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID (0x83U) + +typedef struct NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS { + NvU32 partitioningMode; +} NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS; + + + +/* NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO + * + * This structure describes resources available in a partition requested of a + * given type. + * + * [OUT] partitionFlag + * - Flags to specify in NV2080_CTRL_CMD_GPU_SET_PARTITIONS to request this + * partition + * + * [OUT] grCount + * - Total Number of SMC engines/GR engines (including GFX capable ones in this parition) + * + * [OUT] gfxGrCount + * - Number of SMC engines/GR engines capable of GFX. This is a subset of the engines included in grCount + * + * [OUT] gpcCount + * - Number of GPCs in this partition, including the GFX Capable ones. + * + * [OUT] virtualGpcCount + * - Number of virtualized GPCs in this partition, including the GFX Capable ones. + * + * [OUT] gfxGpcCount + * - Number of GFX Capable GPCs in this partition. This is a subset of the GPCs included in gpcCount. + * + * [OUT] veidCount + * - Number of VEIDS in this partition + * + * [OUT] smCount + * - Number of SMs in this partition + * + * [OUT] ceCount + * - Copy Engines in this partition + * + * [OUT] nvEncCount + * - Encoder Engines in this partition + * + * [OUT] nvDecCount + * - Decoder Engines in this partition + * + * [OUT] nvJpgCount + * - Jpg Engines in this partition + * + * [OUT] nvOfaCount + * - Ofa engines in this partition + * [OUT] memorySize + * - Total available memory within this partition + */ +typedef struct NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO { + NvU32 partitionFlag; + NvU32 grCount; + NvU32 gfxGrCount; + NvU32 gpcCount; + NvU32 virtualGpcCount; + NvU32 gfxGpcCount; + NvU32 veidCount; + NvU32 smCount; + NvU32 ceCount; + NvU32 nvEncCount; + NvU32 nvDecCount; + NvU32 nvJpgCount; + NvU32 nvOfaCount; + NV_DECLARE_ALIGNED(NvU64 memorySize, 8); +} NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO; + +/* + * NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS + * + * This command returns information regarding GPU partitions which can be + * requested via NV2080_CTRL_CMD_GPU_SET_PARTITIONS. + * + * [OUT] descCount + * - Number of valid partition types + * + * [OUT] partitionDescs + * - Information describing available partitions + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS_MESSAGE_ID (0x85U) + +typedef struct NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS { + NvU32 descCount; + // C form: NV2080_CTRL_GPU_DESCRIBE_PARTITION_INFO partitionDescs[NV2080_CTRL_GPU_PARTITION_MAX_TYPES]; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO partitionDescs[NV2080_CTRL_GPU_PARTITION_MAX_TYPES], 8); +} NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS; + +#define NV2080_CTRL_CMD_GPU_DESCRIBE_PARTITIONS (0x20800185U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS_MESSAGE_ID" */ + + + +/* + * NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE + * + * This command returns information regarding maximum page size supported + * by GMMU on the platform on which RM is running. + * + * [OUT] maxSupportedPageSize + * - Maximum local vidmem page size supported by GMMU of a given GPU (HW) + * on a given platform (OS) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE (0x20800188U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID (0x88U) + +typedef struct NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 maxSupportedPageSize, 8); +} NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS; + + + +/* + * NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC + * + * This command returns the max number of MMUs per GPC + * + * gpcId [IN] + * Logical GPC id + * count [OUT] + * The number of MMUs per GPC + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. When SMC is enabled, this + * is a mandatory parameter. + */ +#define NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID (0x8AU) + +typedef struct NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS { + NvU32 gpcId; + NvU32 count; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS; + +#define NV2080_CTRL_CMD_GPU_GET_NUM_MMUS_PER_GPC (0x2080018aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS + * + * This command returns the GPU partition IDs for all active partitions + * If GPU is not partitioned, the control call will return partition count as "0" + * + * swizzId[OUT] + * - HW Partition ID associated with the active partitions + * + * partitionCount[OUT] + * - Number of active partitions in system + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS_MESSAGE_ID (0x8BU) + +typedef struct NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS { + NvU32 swizzId[NV2080_CTRL_GPU_MAX_PARTITION_IDS]; + NvU32 partitionCount; +} NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS; + +#define NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS (0x2080018bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS_MESSAGE_ID" */ + + + +/* + * NV2080_CTRL_CMD_GPU_GET_PIDS + * + * Given a resource identifier and its type, this command returns a set of + * process identifiers (PIDs) of processes that have instantiated this resource. + * For example, given a class number, this command returns a list of all + * processes with clients that have matching object allocations. + * This is a SMC aware call and the scope of the information gets restricted + * based on partition subscription. + * The call enforces partition subscription if SMC is enabled, and client is not + * a monitoring client. + * Monitoring clients get global information without any scope based filtering. + * Monitoring clients are also not expected to subscribe to a partition when + * SMC is enabled. + * + * idType + * Type of the resource identifier. See below for a list of valid types. + * id + * Resource identifier. + * pidTblCount + * Number of entries in the PID table. + * pidTbl + * Table which will contain the PIDs. Each table entry is of type NvU32. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_GPU_GET_PIDS (0x2080018dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID" */ + +/* max size of pidTable */ +#define NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT 950U + +#define NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID (0x8DU) + +typedef struct NV2080_CTRL_GPU_GET_PIDS_PARAMS { + NvU32 idType; + NvU32 id; + NvU32 pidTblCount; + NvU32 pidTbl[NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT]; +} NV2080_CTRL_GPU_GET_PIDS_PARAMS; + +/* + * Use class NV20_SUBDEVICE_0 with NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_CLASS to query + * PIDs with or without GPU contexts. For any other class id, PIDs only with GPU + * contexts are returned. + */ +#define NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_CLASS (0x00000000U) +#define NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_VGPU_GUEST (0x00000001U) + +/* + * NV2080_CTRL_SMC_SUBSCRIPTION_INFO + * + * This structure contains information about the SMC subscription type. + * If MIG is enabled a valid ID is returned, it is set to PARTITIONID_INVALID otherwise. + * + * computeInstanceId + * This parameter returns a valid compute instance ID + * gpuInstanceId + * This parameter returns a valid GPU instance ID + */ +typedef struct NV2080_CTRL_SMC_SUBSCRIPTION_INFO { + NvU32 computeInstanceId; + NvU32 gpuInstanceId; +} NV2080_CTRL_SMC_SUBSCRIPTION_INFO; + +/* + * NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA + * + * This structure contains the video memory usage information. + * + * memPrivate + * This parameter returns the amount of memory exclusively owned + * (i.e. private) to the client + * memSharedOwned + * This parameter returns the amount of shared memory owned by the client + * memSharedDuped + * This parameter returns the amount of shared memory duped by the client + * protectedMemPrivate + * This parameter returns the amount of protected memory exclusively owned + * (i.e. private) to the client whenever memory protection is enabled + * protectedMemSharedOwned + * This parameter returns the amount of shared protected memory owned by the + * client whenever memory protection is enabled + * protectedMemSharedDuped + * This parameter returns the amount of shared protected memory duped by the + * client whenever memory protection is enabled + */ +typedef struct NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA { + NV_DECLARE_ALIGNED(NvU64 memPrivate, 8); + NV_DECLARE_ALIGNED(NvU64 memSharedOwned, 8); + NV_DECLARE_ALIGNED(NvU64 memSharedDuped, 8); + NV_DECLARE_ALIGNED(NvU64 protectedMemPrivate, 8); + NV_DECLARE_ALIGNED(NvU64 protectedMemSharedOwned, 8); + NV_DECLARE_ALIGNED(NvU64 protectedMemSharedDuped, 8); +} NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA; + +#define NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE (0x00000000U) + +#define NV2080_CTRL_GPU_PID_INFO_INDEX_MAX NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE + +typedef union NV2080_CTRL_GPU_PID_INFO_DATA { + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA vidMemUsage, 8); +} NV2080_CTRL_GPU_PID_INFO_DATA; + + +/* + * NV2080_CTRL_GPU_PID_INFO + * + * This structure contains the per pid information. Each type of information + * retrievable via NV2080_CTRL_CMD_GET_PID_INFO is assigned a unique index + * below. In addition the process for which the lookup is for is also defined. + * This is a SMC aware call and the scope of the information gets restricted + * based on partition subscription. + * The call enforces partition subscription if SMC is enabled, and client is not + * a monitoring client. + * Monitoring clients get global information without any scope based filtering. + * Monitoring clients are also not expected to subscribe to a partition when + * SMC is enabled. + * + * pid + * This parameter specifies the PID of the process for which information is + * to be queried. + * index + * This parameter specifies the type of information being queried for the + * process of interest. + * result + * This parameter returns the result of the instruction's execution. + * data + * This parameter returns the data corresponding to the information which is + * being queried. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + * + * Valid PID information indices are: + * + * NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE + * This index is used to request the amount of video memory on this GPU + * allocated to the process. + */ +typedef struct NV2080_CTRL_GPU_PID_INFO { + NvU32 pid; + NvU32 index; + NvU32 result; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PID_INFO_DATA data, 8); + NV2080_CTRL_SMC_SUBSCRIPTION_INFO smcSubscription; +} NV2080_CTRL_GPU_PID_INFO; + +/* + * NV2080_CTRL_CMD_GPU_GET_PID_INFO + * + * This command allows querying per-process information from the RM. Clients + * request information by specifying a unique informational index and the + * Process ID of the process in question. The result is set to indicate success + * and the information queried (if available) is returned in the data parameter. + * + * pidInfoListCount + * The number of valid entries in the pidInfoList array. + * pidInfoList + * An array of NV2080_CTRL_GPU_PID_INFO of maximum length + * NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_GPU_GET_PID_INFO (0x2080018eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID" */ + +/* max size of pidInfoList */ +#define NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT 200U + +#define NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID (0x8EU) + +typedef struct NV2080_CTRL_GPU_GET_PID_INFO_PARAMS { + NvU32 pidInfoListCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PID_INFO pidInfoList[NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT], 8); +} NV2080_CTRL_GPU_GET_PID_INFO_PARAMS; + + + +/*! + * NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT + * + * @brief Handle VF PRI faults + * + * faultType + * BAR1, BAR2, PHYSICAL or UNBOUND_INSTANCE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * + */ + +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT (0x20800192U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_INVALID 0U +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR1 1U +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR2 2U +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_PHYSICAL 3U +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_UNBOUND_INSTANCE 4U + +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_MESSAGE_ID (0x92U) + +typedef struct NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS { + NvU32 faultType; +} NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS; + + +/*! + * Compute policy types to be specified by callers to set a config. + * + * _TIMESLICE + * Set the timeslice config for the requested GPU. + * Check @ref NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE for + * permissible timeslice values. + */ +#define NV2080_CTRL_GPU_COMPUTE_POLICY_TIMESLICE 0U +#define NV2080_CTRL_GPU_COMPUTE_POLICY_MAX 1U + +/*! + * Enum consisting of permissible timeslice options that can configured + * for a GPU. These can be queried by compute clients and the exact + * timeslice values can be chosen appropriately as per GPU support + */ +typedef enum NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE { + NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_DEFAULT = 0, + NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_SHORT = 1, + NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MEDIUM = 2, + NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_LONG = 3, + NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MAX = 4, +} NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE; + +typedef struct NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG { + /*! + * NV2080_CTRL_GPU_COMPUTE_POLICY_ + */ + NvU32 type; + + /*! + * Union of type-specific data + */ + union { + NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE timeslice; + } data; +} NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG; + +#define NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID (0x94U) + +typedef struct NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS { + NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG config; +} NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG + * + * This command retrieves all compute policies configs for the associated gpu. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG (0x20800195U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID" */ + +/*! + * This define limits the max number of policy configs that can be handled by + * NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG command. + * + * @note Needs to be in sync (greater or equal) to NV2080_CTRL_GPU_COMPUTE_POLICY_MAX. + */ + +#define NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX 32U + +#define NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID (0x95U) + +typedef struct NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS { + NvU32 numConfigs; + + /*! + * C form: + * NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG configList[NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX]; + */ + NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG configList[NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX]; +} NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_GFID + * + * This command returns the GFID (GPU Function ID) for a given SR-IOV + * Virtual Function (VF) of the physical GPU. + * + * domain [IN] + * This field specifies the respective domain of the PCI device. + * bus [IN] + * This field specifies the bus id for a given VF. + * device [IN] + * This field specifies the device id for a given VF. + * func [IN] + * This field specifies the function id for a given VF. + * gfid[OUT] + * - This field returns GFID for a given VF BDF. + * gfidMask[OUT] + * - This field returns GFID mask value. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ + +#define NV2080_CTRL_CMD_GPU_GET_GFID (0x20800196U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GFID_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_GFID_PARAMS_MESSAGE_ID (0x96U) + +typedef struct NV2080_CTRL_GPU_GET_GFID_PARAMS { + NvU32 domain; + NvU8 bus; + NvU8 device; + NvU8 func; + NvU32 gfid; + NvU32 gfidMask; +} NV2080_CTRL_GPU_GET_GFID_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY + * + * This command informs the GPU driver that the GPU partition associated with + * a given GFID has been activated or will be deactivated. + * + * gfid[IN] + * - The GPU function identifier for a given VF BDF + * bEnable [IN] + * - Set to NV_TRUE if the GPU partition has been activated. + * - Set to NV_FALSE if the GPU partition will be deactivated. + * fabricPartitionId [IN] + * - Set the fabric manager partition ID dring partition activation. + * - Ignored during partition deactivation. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ + +#define NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY (0x20800197U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS_MESSAGE_ID (0x97U) + +typedef struct NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS { + NvU32 gfid; + NvBool bEnable; + NvU32 fabricPartitionId; +} NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS; + +/*! + * NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST + * + * @brief Validate the address range for memory map request by comparing the + * user supplied address range with GPU BAR0/BAR1 range. + * + * @param[in] addressStart Start address for memory map request + * @param[in] addressLength Length for for memory map request + * @param[out] protection NV_PROTECT_READ_WRITE, if both read/write is allowed + * NV_PROTECT_READABLE, if only read is allowed + * + * Possible status values returned are: + * NV_OK + * NV_ERR_PROTECTION_FAULT + * + */ +#define NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST (0x20800198U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID (0x98U) + +typedef struct NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS { + NV_DECLARE_ALIGNED(NvU64 addressStart, 8); + NV_DECLARE_ALIGNED(NvU64 addressLength, 8); + NvU32 protection; +} NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES + * + * This command is used to retrieve the load time (latency) of each engine. + * + * engineCount + * This field specifies the number of entries of the following + * three arrays. + * + * engineList[NV2080_GPU_MAX_ENGINE_OBJECTS] + * An array of NvU32 which stores each engine's descriptor. + * + * engineStateLoadTime[NV2080_GPU_MAX_ENGINE_OBJECTS] + * A array of NvU64 which stores each engine's load time. + * + * engineIsInit[NV2080_GPU_MAX_ENGINE_OBJECTS] + * A array of NvBool which stores each engine's initialization status. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES (0x2080019bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS 0xC8U + +#define NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID (0x9BU) + +typedef struct NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS { + NvU32 engineCount; + NvU32 engineList[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS]; + NV_DECLARE_ALIGNED(NvU64 engineStateLoadTime[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS], 8); + NvBool engineIsInit[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS]; +} NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING + * + * This command is used to retrieve the mapping of engine ID and engine Name. + * + * engineCount + * This field specifies the size of the mapping. + * + * engineID + * An array of NvU32 which stores each engine's descriptor. + * + * engineName + * An array of char[100] which stores each engine's name. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING (0x2080019cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID (0x9CU) + +typedef struct NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS { + NvU32 engineCount; + NvU32 engineID[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS]; + char engineName[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS][100]; +} NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_NOPTRS + * + * Same as above NV2080_CTRL_CMD_GPU_EXEC_REG_OPS except that this CTRL CMD will + * not allow any embedded pointers. The regOps array is inlined as part of the + * struct. + * NOTE: This intended for gsp plugin only as it may override regOp access + * restrictions + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_NOPTRS (0x2080019dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID" */ + +/* setting this to 100 keeps it right below 4k in size */ +#define NV2080_CTRL_REG_OPS_ARRAY_MAX 100U +#define NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID (0x9DU) + +typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS { + NvHandle hClientTarget; + NvHandle hChannelTarget; + NvU32 bNonTransactional; + NvU32 reserved00[2]; + NvU32 regOpCount; + NV2080_CTRL_GPU_REG_OP regOps[NV2080_CTRL_REG_OPS_ARRAY_MAX]; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS; + +#define NV2080_CTRL_GPU_SKYLINE_INFO_MAX_SKYLINES 9U +#define NV2080_CTRL_GPU_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS 64U +/*! + * NV2080_CTRL_GPU_SKYLINE_INFO + * skylineVgpcSize[OUT] + * - TPC count of non-singleton VGPCs + * singletonVgpcMask[OUT] + * - Mask of active Singletons + * maxInstances[OUT] + * - Max allowed instances of this skyline concurrently on a GPU + * computeSizeFlag + * - One of NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* flags which is associated with this skyline + */ +typedef struct NV2080_CTRL_GPU_SKYLINE_INFO { + NvU8 skylineVgpcSize[NV2080_CTRL_GPU_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS]; + NvU32 singletonVgpcMask; + NvU32 maxInstances; + NvU32 computeSizeFlag; +} NV2080_CTRL_GPU_SKYLINE_INFO; + +/*! + * NV2080_CTRL_GPU_GET_SKYLINE_INFO_PARAMS + * skylineTable[OUT] + * - TPC count of non-singleton VGPCs + * - Mask of singleton vGPC IDs active + * - Max Instances of this skyline possible concurrently + * - Associated compute size with the indexed skyline + * validEntries[OUT] + * - Number of entries which contain valid info in skylineInfo + */ +#define NV2080_CTRL_GPU_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID (0x9FU) + +typedef struct NV2080_CTRL_GPU_GET_SKYLINE_INFO_PARAMS { + NV2080_CTRL_GPU_SKYLINE_INFO skylineTable[NV2080_CTRL_GPU_SKYLINE_INFO_MAX_SKYLINES]; + NvU32 validEntries; +} NV2080_CTRL_GPU_GET_SKYLINE_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_SKYLINE_INFO + * + * Retrieves skyline information about the GPU. Params are sized to currently known max + * values, but will need to be modified in the future should that change. + */ +#define NV2080_CTRL_CMD_GPU_GET_SKYLINE_INFO (0x2080019fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID" */ + +/*! + * NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO + * + * [in/out] gpuId + * GPU ID for which the capabilities are queried. + * For the NV2080_CTRL_CMD_GET_P2P_CAPS control: + * If bAllCaps == NV_TRUE, this parameter is an out parameter and equals to + * the GPU ID of an attached GPU. + * If bAllCaps == NV_FALSE, this parameter is an in parameter and the requester + * should set it to the ID of the GPU that needs to be queried from. + * [in] gpuUuid + * Alternative to gpuId; used to identify target GPU for which caps are being queried. + * Option only available for Guest RPCs. + * If bUseUuid == NV_TRUE, gpuUuid is used in lieu of gpuId to identify target GPU. + * If bUseUuid == NV_FALSE, gpuUuid is ignored and gpuId is used by default. + * If bAllCaps == NV_TRUE, gpuUuid is ignored. + * [out] p2pCaps + * Peer to peer capabilities discovered between the GPUs. + * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. + * [out] p2pOptimalReadCEs + * Mask of CEs to use for p2p reads over Nvlink. + * [out] p2pOptimalWriteCEs + * Mask of CEs to use for p2p writes over Nvlink. + * [out] p2pCapsStatus + * Status of all supported p2p capabilities. + * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. + * [out] busPeerId + * Bus peer ID. For an invalid or a non-existent peer this field + * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. + * [out] busEgmPeerId + * Bus EGM peer ID. For an invalid or a non-existent peer this field + * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. + */ +#define NV2080_GET_P2P_CAPS_UUID_LEN 16U + +typedef struct NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO { + NvU32 gpuId; + NvU8 gpuUuid[NV2080_GET_P2P_CAPS_UUID_LEN]; + NvU32 p2pCaps; + NvU32 p2pOptimalReadCEs; + NvU32 p2pOptimalWriteCEs; + NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; + NvU32 busPeerId; + NvU32 busEgmPeerId; +} NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO; + +/*! + * NV2080_CTRL_CMD_GET_P2P_CAPS + * + * Returns peer to peer capabilities present between GPUs. + * The caller must either specify bAllCaps to query the capabilities for + * all the attached GPUs or they must pass a valid list of GPU IDs. + * + * [in] bAllCaps + * Set to NV_TRUE to query the capabilities for all the attached GPUs. + * Set to NV_FALSE and specify peerGpuCount and peerGpuCaps[].gpuId + * to retrieve the capabilities only for the specified GPUs. + * [in] bUseUuid + * Option only available for Guest RPCs. + * Set to NV_TRUE to use gpuUuid in lieu of gpuId to identify target GPU. + * If bAllCaps == NV_TRUE, bUseUuid is ignored. + * [in/out] peerGpuCount + * The number of the peerGpuCaps entries. + * If bAllCaps == NV_TRUE, this parameter is an out parameter and equals to + * the total number of the attached GPUs. + * If bAllCaps == NV_FALSE, this parameter is an in parameter and the requester + * should set it to the number of the peerGpuCaps entries. + * [in/out] peerGpuCaps + * The array of NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO entries, describing + * the peer to peer capabilities of the GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT - Invalid peerGpuCount + * NV_ERR_OBJECT_NOT_FOUND - Invalid peerGpuCaps[].gpuId + */ +#define NV2080_CTRL_CMD_GET_P2P_CAPS (0x208001a0U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID (0xA0U) + +typedef struct NV2080_CTRL_GET_P2P_CAPS_PARAMS { + NvBool bAllCaps; + NvBool bUseUuid; + NvU32 peerGpuCount; + NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO peerGpuCaps[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; +} NV2080_CTRL_GET_P2P_CAPS_PARAMS; + + + +/*! + * NV2080_CTRL_GPU_COMPUTE_PROFILE + * + * This structure specifies resources in an execution partition + * + * computeSize[OUT] + * - NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* associated with this profile + * + * flags[OUT] + * - Bitmap of flags describing the profile NV2080_CTRL_GPU_COMPUTE_PROFILE_FLAG* + * + * gfxGpcCount[OUT] + * - Total Number of GFX Supporting GPCs in this partition + * + * gpcCount[OUT] + * - Total Number of GPCs in this partition (including GFX Supported GPCs) + * + * veidCount[OUT] + * - Number of VEIDs allocated to this profile + * + * smCount[OUT] + * - Number of SMs usable in this profile + */ +typedef struct NV2080_CTRL_GPU_COMPUTE_PROFILE { + NvU8 computeSize; + NvU16 flags; + NvU32 gfxGpcCount; + NvU32 gpcCount; + NvU32 veidCount; + NvU32 smCount; +} NV2080_CTRL_GPU_COMPUTE_PROFILE; + +// Indicates that the profile spans over multiple dielets +#define NV2080_CTRL_GPU_COMPUTE_PROFILE_FLAG_MULTIDIE 0:0 +#define NV2080_CTRL_GPU_COMPUTE_PROFILE_FLAG_MULTIDIE_FALSE 0U +#define NV2080_CTRL_GPU_COMPUTE_PROFILE_FLAG_MULTIDIE_TRUE 1U + +/*! + * NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS + * + * This structure specifies resources in an execution partition + * + * partitionFlag[IN] + * - GPU instance profile flags for which to query compute profiles + * Ignored, if subdevice is subscribed to a GPU instance + * + * profileCount[OUT] + * - Total Number of profiles filled + * + * profiles[OUT] + * - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles + */ +#define NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xA2U) + +typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS { + NvU32 partitionFlag; + NvU32 profileCount; + NV2080_CTRL_GPU_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE]; +} NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS; + +#define NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILES (0x208001a2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_UNSUPPORTED 0U +#define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_NOT_STARTED 1U +#define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_IN_PROGRESS 2U +#define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE 3U + +#define NV2080_GPU_FABRIC_CLUSTER_UUID_LEN 16U + +#define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_SUPPORTED NVBIT64(0) + +#define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_MUTLINODE_SUPPORTED NVBIT64(1) + + + +#define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_UC_LOOPBACK_SUPPORTED NVBIT64(2) + +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW 1:0 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED 0 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE 1 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE 2 + +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE 3:2 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_NOT_SUPPORTED 0 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_TRUE 1 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_FALSE 2 + +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY 5:4 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_NOT_SUPPORTED 0 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_TRUE 1 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_FALSE 2 + +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY 7:6 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_NOT_SUPPORTED 0 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_TRUE 1 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_FALSE 2 + +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION 11:8 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NOT_SUPPORTED 0 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NONE 1 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INCORRECT_SYSGUID 2 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INCORRECT_CHASSIS_SN 3 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NO_PARTITION 4 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INSUFFICIENT_NVLINKS 5 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INCOMPATIBLE_GPU_FW 6 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INVALID_LOCATION 7 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_GPU_STATE_INVALID 8 + +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_PARTITION_ASSIGNED 13:12 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_PARTITION_ASSIGNED_NOT_SUPPORTED 0 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_PARTITION_ASSIGNED_TRUE 1 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_PARTITION_ASSIGNED_FALSE 2 + +#define NV2080_CTRL_GPU_FABRIC_HEALTH_SUMMARY_NOT_SUPPORTED 0 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_SUMMARY_HEALTHY 1 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_SUMMARY_UNHEALTHY 2 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_SUMMARY_LIMITED_CAPACITY 3 + +/*! + * NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS + * + * This structure provides the GPU<-->FM probe state info on NVSwitch based + * systems + * + * state[OUT] + * - Current state of GPU<-->FM probe req/rsp + * Following values can be returned + * _UNSUPPORTED - system does not support this feature + * _NOT_STARTED - probe request is not yet sent to the FM + * _IN_PROGRESS - probe response is not yet received + * _COMPLETE - probe response is received + * When state is NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE + * status has to be checked for probe response success/failure + * status[OUT] + * - Inband Probe response status + * A GPU which returns NV_OK status upon receiving the probe response + * can participate in P2P + * clusterUuid[OUT] + * - Uuid of the cluster to which this node belongs + * fabricPartitionId[OUT] + * - Fabric partition Id + * fabricCaps[OUT] + * - Summary of fabric capabilities received from probe resp + * Possible values are + * NV2080_CTRL_GPU_FABRIC_PROBE_CAP_* + * fabricCliqueId[OUT] + * - Unique ID of a set of GPUs within a fabric partition that can perform P2P + * fabricHealthMask[OUT] + * - Mask where bits indicate different status about the health of the fabric + * fabricHealthSummary[OUT] + * - Summary of the Fabric Health + */ +#define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xA3U) + +typedef struct NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS { + NvU8 state; + NV_STATUS status; + NvU8 clusterUuid[NV2080_GPU_FABRIC_CLUSTER_UUID_LEN]; + NvU16 fabricPartitionId; + NV_DECLARE_ALIGNED(NvU64 fabricCaps, 8); + NvU32 fabricCliqueId; + NvU32 fabricHealthMask; + NvU8 fabricHealthSummary; +} NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS; + +#define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO (0x208001a3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS + * + * This command retrieves and constructs the GPU partnumber from the VBIOS. + * + * The following data are currently supported: + * + * pciDevId + * The PCI device ID + * + * chipSku + * The chip SKU information + * + * chipMajor + * The chip major number + * + * chipMinor + * The chip minor number + * + */ +#define NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS (0x208001a4U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID" */ + +/* + * The string format for a GPU part number + * The GPU part number is formatted with 4 hexadecimal digits for the PCI device ID, the chip SKU string, + * the chip major number, and then the chip minor number. + * Ordering of the fields for the string format must be synced with the NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS + * struct fields. + */ +#define GPU_PART_NUMBER_FMT "%04X-%s-%X%X" + +/* The maximum length for the chip sku */ +#define NV2080_MAX_CHIP_SKU_LENGTH 0x00000004U + +#define NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID (0xA4U) + +typedef struct NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS { + NvU32 pciDevId; + NvU8 chipSku[NV2080_MAX_CHIP_SKU_LENGTH]; + NvU32 chipMajor; + NvU32 chipMinor; +} NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP + * + * This command returns the host hardware defined engine ID of the specified engine(s). + * + * swizzId[IN] + * - HW Partition ID associated with the requested partition. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP (0x208001a5U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS_MESSAGE_ID (0xA5U) + +typedef struct NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS { + NvU32 swizzId; +} NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS; + +#define NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS (0x208001a6U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_GSP (0x208001a7U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_VGPU (0x208001a8U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID" */ + +/* setting this to 100 keeps it right below 4k in size */ +#define NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX 50U +typedef struct NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS { + NvHandle hClientTarget; + NvHandle hChannelTarget; + NvU32 bNonTransactional; + NvU32 regOpCount; + NvU32 smIds[NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX]; + NV2080_CTRL_GPU_REG_OP regOps[NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX]; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS; + +#define NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_MESSAGE_ID (0xA6U) + +typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS; +#define NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS_MESSAGE_ID (0xA7U) + +typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS; +#define NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID (0xA8U) + +typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_RESET + * + * INTERNAL DEBUG/TESTING USE ONLY + * + * Marks the device for reset. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_RESET (0x208001a9U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xA9" */ + +/* + * NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_RESET + * + * INTERNAL DEBUG/TESTING USE ONLY + * + * Unmarks the device for reset. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_RESET (0x208001aaU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xAA" */ + +/* + * NV2080_CTRL_CMD_GPU_GET_RESET_STATUS + * + * Gets the current reset status of the device. + * + * bResetNeeded + * Set to NV_TRUE if the device needs to be reset. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_RESET_STATUS (0x208001abU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS_MESSAGE_ID (0xABU) + +typedef struct NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS { + NvBool bResetRequired; +} NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_DRAIN_AND_RESET + * + * INTERNAL DEBUG/TESTING USE ONLY + * + * Marks the device for drain and reset. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_DRAIN_AND_RESET (0x208001acU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xAC" */ + +/* + * NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_DRAIN_AND_RESET + * + * INTERNAL DEBUG/TESTING USE ONLY + * + * Unmarks the device for drain and reset. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_DRAIN_AND_RESET (0x208001adU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xAD" */ + +/* + * NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS + * + * Gets the current drain and reset status of the device. Drain and reset is used only SMC configs. + * + * bDrainRecommended + * Set to NV_TRUE if a drain and reset is recommended for the device. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS (0x208001aeU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS_MESSAGE_ID (0xAEU) + +typedef struct NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS { + NvBool bDrainRecommended; +} NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS; + +/* + * NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 + * + * This command returns NVENC software sessions information for the associate GPU. + * This command is similar to NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO but doesn't have + * embedded pointers. + * + * Check NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO for detailed information. + */ + +#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID (0xAFU) + +typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS { + NvU32 sessionInfoTblEntry; + NV2080_CTRL_NVENC_SW_SESSION_INFO sessionInfoTbl[NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES]; +} NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS; + +#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 (0x208001afU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID" */ + +typedef struct NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO { + NvU32 engDesc; + NvU32 ctxAttr; + NvU32 ctxBufferSize; + NvU32 addrSpaceList; + NvU32 registerBase; +} NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO; +#define NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS 0x40 + +#define NV2080_CTRL_CMD_GPU_GET_CONSTRUCTED_FALCON_INFO (0x208001b0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID (0xB0U) + +typedef struct NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS { + NvU32 numConstructedFalcons; + NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS]; +} NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_VF_CAPS + * + * This command will return the MSIX capabilities for virtual function + * Parameters: + * + * gfid [IN] + * The GPU function identifier for a given VF BDF + * + * vfMsixCap [out] + * This field returns the VF MSIX cap values + * + * Possible status values returned are: + * NV_OK + */ +typedef struct NV2080_VF_MSIX_CAPS { + NvU32 msix_header; + NvU32 msix_table; + NvU32 msix_pba; +} NV2080_VF_MSIX_CAPS; + +#define NV2080_CTRL_CMD_GPU_GET_VF_CAPS (0x208001b1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS_MESSAGE_ID (0xB1U) + +typedef struct NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS { + NvU32 gfid; + NV2080_VF_MSIX_CAPS vfMsixCap; +} NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_RECOVERY_ACTION + * + * Gets the recovery action needed for the device after a failure. + * + * action [OUT] + * Returns the recovery action needed. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_RECOVERY_ACTION (0x208001b2U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_GPU_RECOVERY_ACTION { + NV2080_CTRL_GPU_RECOVERY_ACTION_NONE = 0, + NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_PF_FLR = 1, + NV2080_CTRL_GPU_RECOVERY_ACTION_OS_REBOOT = 2, + NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_P2P = 3, + NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_AND_RESET = 4, + NV2080_CTRL_GPU_RECOVERY_ACTION_RECOVER_IMEX_DOMAIN = 5, + NV2080_CTRL_GPU_RECOVERY_ACTION_BUS_RESET = 6, + NV2080_CTRL_GPU_RECOVERY_ACTION_SYSTEM_REBOOT = 7, +} NV2080_CTRL_GPU_RECOVERY_ACTION; + +#define NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_RESET NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_PF_FLR +#define NV2080_CTRL_GPU_RECOVERY_ACTION_NODE_REBOOT NV2080_CTRL_GPU_RECOVERY_ACTION_OS_REBOOT + +#define NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS_MESSAGE_ID (0xB2U) + +typedef struct NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS { + NV2080_CTRL_GPU_RECOVERY_ACTION action; +} NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS; + +/* + * NV2080_CTRL_GPU_GET_FIPS_STATUS + * + * @brief get FIPS status (enabled/disabled) from GSP-RM + * + * + * @return NV_OK on success + * @return NV_ERR_ otherwise + */ +#define NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS_MESSAGE_ID (0xe4U) + +typedef struct NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS { + NvBool bFipsEnabled; +} NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS; +#define NV2080_CTRL_GPU_GET_FIPS_STATUS (0x208001e4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_GPU_GET_RAFTS_FS_MASK + * + * @brief Get floorsweeping mask for given skyline configuration. + * + * tpcCountMatrix [IN] + * TPC per GPC distribution for which user require floorsweeping mask. + * + * gfxGpcCount [IN] + * Number of GFX capable GPC required. + * + * gfxTpcCount [IN] + * Number of GFX capable TPC required. + * + * floorSweepConfig [OUT] + * MODS floorsweeping mask. + * + * bValid [OUT] + * If entries in floorSweepConfig are valid or not. + * + * @return NV_OK : on success + * @return NV_ERR_INVALID_PARAMETER : Parameters in pParams are incompatible with each other + * @return NV_ERR_NOT_SUPPORTED : Requested skyline not supported by current chip but can be supported by a chip + * with fewer defects + */ +typedef enum NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE { + NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_INVALID = 0, + NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_TPC = 1, + NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_GPC = 2, +} NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE; + +typedef struct NV2080_RAFTS_FLOORSWEEP_INFO { + NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE unitType; + NvU32 parentId; + NvU32 mask; +} NV2080_RAFTS_FLOORSWEEP_INFO; + +#define NV2080_CTRL_GPU_RAFTS_NUM_MAX_UGPU 0x2 +#define NV2080_CTRL_GPU_RAFTS_NUM_MAX_GPC_PER_UGPU 0xC +#define NV2080_CTRL_GPU_RAFTS_NUM_MAX_NUM_GPC (0x18) /* finn: Evaluated from "NV2080_CTRL_GPU_RAFTS_NUM_MAX_UGPU * NV2080_CTRL_GPU_RAFTS_NUM_MAX_GPC_PER_UGPU" */ +#define NV2080_CTRL_GPU_RAFTS_NUM_MAX_FS_UNIT (0x1a) /* finn: Evaluated from "NV2080_CTRL_GPU_RAFTS_NUM_MAX_NUM_GPC + 2" */ + +#define NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS_MESSAGE_ID (0xB3U) + +typedef struct NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS { + NvU8 tpcCountMatrix[NV2080_CTRL_GPU_RAFTS_NUM_MAX_UGPU][NV2080_CTRL_GPU_RAFTS_NUM_MAX_GPC_PER_UGPU]; + NvBool bValid; + NV2080_RAFTS_FLOORSWEEP_INFO floorSweepConfig[NV2080_CTRL_GPU_RAFTS_NUM_MAX_FS_UNIT]; + NvU8 gfxGpcCount; + NvU8 gfxTpcPerGpcCount; + NvU8 maxUgpuTpcDiff; +} NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS; + +#define NV2080_CTRL_GPU_GET_RAFTS_FS_MASK (0x208001b3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS_MESSAGE_ID" */ + +/*! + * NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS + * + * This structure specifies resources in an execution partition + * + * partitionFlag[IN] + * - If GPU instance profile flag for which to query specified + * compute profile + * + * computeSize[IN] + * - Size specifying compute profile whose info to query + * + * totalProfileCount[OUT] + * - Total Number of profiles possible to create in instance of specified GPU + * profile + * + * totalSpans[OUT] + * - List of spans which can possibly be occupied by partitions of the + * given type. + * + * totalSpansCount[OUT] + * - Number of entries filled in totalSpans + * + */ +#define NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILE_CAPACITY (0x208001e5U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS_MESSAGE_ID (0xe5U) + +typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS { + NvU32 partitionFlag; + NvU32 computeSize; + NvU32 totalProfileCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_EXEC_PARTITION_SPAN totalSpans[NV2080_CTRL_GPU_MAX_PARTITIONS], 8); + NvU32 totalSpansCount; +} NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_TPC_RECONFIG_MASK + * + * This command returns the TPC reconfig mask for a specific GPC + * + * gpc[IN] + * The GPC for which the TPC reconfig mask needs to be queried. + * The GPC should be specified as a logical index. + * + * tpcReconfigMask[OUT] + * Mask of reconfigurable TPCs in the specified GPC + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_TPC_RECONFIG_MASK (0x208001e7U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID (0xe7U) + +typedef struct NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS { + NvU32 gpc; + NvU32 tpcReconfigMask; +} NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_RPC_GSP_TEST + * + * This command checks a variable sized RPC for a known pattern, then + * fills the data field with another pattern. It also records the timestamp + * before and after the RPC is sent to GSP. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + */ +#define NV2080_CTRL_CMD_GPU_RPC_GSP_TEST (0x208001e8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS_MESSAGE_ID (0xe8U) + +typedef struct NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS { + NvU8 test; + NvU32 dataSize; + NV_DECLARE_ALIGNED(NvU64 startTimestamp, 8); + NV_DECLARE_ALIGNED(NvU64 stopTimestamp, 8); + NV_DECLARE_ALIGNED(NvP64 data, 8); +} NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS; + +#define NV2080_CTRL_GPU_RPC_GSP_TEST_SERIALIZED_INTEGRITY 0x1 +#define NV2080_CTRL_GPU_RPC_GSP_TEST_UNSERIALIZED 0x2 +#define NV2080_CTRL_GPU_RPC_GSP_TEST_SERIALIZED_NOP 0x3 +#define NV2080_CTRL_GPU_RPC_GSP_TEST_TIMEOUT 0x4 + +/* + * NV2080_CTRL_CMD_GPU_RPC_GSP_QUERY_SIZES + * + * This command returns information necessary for GSP RPC integrity tests + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + */ +#define NV2080_CTRL_CMD_GPU_RPC_GSP_QUERY_SIZES (0x208001e9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS_MESSAGE_ID (0xe9U) + +typedef struct NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS { + NvU32 maxRpcSize; + NvU32 finnRmapiSize; + NvU32 rpcGspControlSize; + NvU32 rpcMessageHeaderSize; + NV_DECLARE_ALIGNED(NvU64 timestampFreq, 8); +} NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS; + +/* + * RUSD features. + * Each feature definition equates to a bit in the supportedFeatures bitmask. + */ +#define RUSD_FEATURE_NON_POLLING 0x1 +#define RUSD_FEATURE_POLLING 0x2 + +/* + * NV2080_CTRL_CMD_GPU_RUSD_GET_SUPPORTED_FEATURES + * + * @brief Returns bitmask of supported RUSD features. + * + * @param[out] supportedFeatures Bitmask of supported RUSD features + * + * @return NV_OK + */ +#define NV2080_CTRL_CMD_RUSD_GET_SUPPORTED_FEATURES (0x208001eaU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS_MESSAGE_ID (0xeaU) + +typedef struct NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS { + NvU32 supportedFeatures; +} NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_RUSD_SET_FEATURES + * + * @brief Set RUSD featuress + * + * permanentPolledDataMask + * When a permanent polling data mask is set, RUSD will start polling the + * set of specified polling data as long as there's an active userspace + * channel, even if there's no active RUSD clients. + * This field specifies which data to poll in permanent RUSD polling. + * + * @return NV_OK + */ +#define NV2080_CTRL_CMD_GPU_RUSD_SET_FEATURES (0x208001ebU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_RUSD_SET_FEATURES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_RUSD_SET_FEATURES_PARAMS_MESSAGE_ID (0xebU) + +typedef struct NV2080_CTRL_GPU_RUSD_SET_FEATURES_PARAMS { + NV_DECLARE_ALIGNED(NvU64 permanentPolledDataMask, 8); +} NV2080_CTRL_GPU_RUSD_SET_FEATURES_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_FORCE_GSP_UNLOAD + * + * This command is used to trigger GSP Unload + * + * flags[IN] + * Flags passed by caller - For future use. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_FORCE_GSP_UNLOAD (0x208001ecU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_FORCE_GSP_UNLOAD_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_FORCE_GSP_UNLOAD_PARAMS_MESSAGE_ID (0xecU) + +typedef struct NV2080_CTRL_GPU_FORCE_GSP_UNLOAD_PARAMS { + NvU32 flags; +} NV2080_CTRL_GPU_FORCE_GSP_UNLOAD_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_VGA_SR_READ_WRITE + * + * This control is supported only on MODS. + * + * bRead[IN] + * head[IN] + * index[IN] + * data[IN/OUT] + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_VGA_SR_READ_WRITE (0x208001edU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_VGA_SR_READ_WRITE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_VGA_SR_READ_WRITE_PARAMS_MESSAGE_ID (0xedU) + +typedef struct NV2080_CTRL_GPU_VGA_SR_READ_WRITE_PARAMS { + NvBool bWrite; + NvU32 head; + NvU8 index; + NvU8 data; +} NV2080_CTRL_GPU_VGA_SR_READ_WRITE_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GPU_ERROR_INJECTION_CONTROL + * + * @brief Injects an error for testing purposes + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +typedef enum NV2080_CTRL_GPU_INJECT_ERROR_TYPE { + NV2080_CTRL_GPU_INJECT_ERROR_MESSAGE_QUEUE = 0, + NV2080_CTRL_GPU_INJECT_ERROR__COUNT = 1, +} NV2080_CTRL_GPU_INJECT_ERROR_TYPE; + +#define NV2080_CTRL_CMD_GPU_ERROR_INJECTION_CONTROL (0x208001efU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_ERROR_INJECTION_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_ERROR_INJECTION_CONTROL_PARAMS_MESSAGE_ID (0xefU) + +typedef struct NV2080_CTRL_GPU_ERROR_INJECTION_CONTROL_PARAMS { + NvU32 errorType; +} NV2080_CTRL_GPU_ERROR_INJECTION_CONTROL_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_CHECK_MEM_SUBSYS_ERROR + * + * @brief Detect if there is a memory subsystem HW error + * + * flags[IN] + * Flags passed by caller - For future use. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_MEMORY_ERROR + */ +#define NV2080_CTRL_CMD_GPU_CHECK_MEM_SUBSYS_ERROR (0x208001f0U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_CHECK_MEM_SUBSYS_ERROR_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_CHECK_MEM_SUBSYS_ERROR_PARAMS_MESSAGE_ID (0xf0U) + +typedef struct NV2080_CTRL_GPU_CHECK_MEM_SUBSYS_ERROR_PARAMS { + NvU32 flags; +} NV2080_CTRL_GPU_CHECK_MEM_SUBSYS_ERROR_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_DEFAULT_TIMEOUT + * + * @brief Returns the RM default timeout in ms + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + */ + +#define NV2080_CTRL_CMD_GPU_GET_DEFAULT_TIMEOUT (0x208001f1U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_DEFAULT_TIMEOUT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_DEFAULT_TIMEOUT_PARAMS_MESSAGE_ID (0xf1U) + +typedef struct NV2080_CTRL_GPU_GET_DEFAULT_TIMEOUT_PARAMS { + NvU32 defaultTimeout; +} NV2080_CTRL_GPU_GET_DEFAULT_TIMEOUT_PARAMS; + +/* + * NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL + * + * This control is used to set up and perform various GSP crypto operations + * + */ +#define NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL (0x208001f2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GSP_CRYPTO_CONTROL_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_TYPE { + NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_RSA_DECRYPTION = 0, + NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_ECDSA = 1, + NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_RNG = 2, + NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_SHA = 3, +} NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_TYPE; + +#define NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_RSA_EXPONENT_SIZE 4 +#define NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_NONCE_SIZE 48 + +#define NV2080_CTRL_GSP_CRYPTO_CONTROL_PARAMS_MESSAGE_ID (0xf2U) + +typedef struct NV2080_CTRL_GSP_CRYPTO_CONTROL_PARAMS { + NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_TYPE opcode; + NvU32 inputMessageSize; + NV_DECLARE_ALIGNED(NvP64 inputMessage, 8); + NvU32 outputMessageSize; + NV_DECLARE_ALIGNED(NvP64 outputMessage, 8); + NvU32 modulusSize; + NV_DECLARE_ALIGNED(NvP64 modulus, 8); + NvU8 exponent[NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_RSA_EXPONENT_SIZE]; + NvBool usePresetKey; + NvU32 keySize; + NV_DECLARE_ALIGNED(NvP64 key, 8); + NvU8 nonce[NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_NONCE_SIZE]; +} NV2080_CTRL_GSP_CRYPTO_CONTROL_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_IS_RESET_COUPLED + * + * Identifies whether the GPU reset is coupled. + * + * isResetCoupled[OUT] + * This field is written with the value TRUE if the reset is coupled. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_GPU_IS_RESET_COUPLED (0x208081f3U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_IS_RESET_COUPLED_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_GPU_IS_RESET_COUPLED_PARAMS_MESSAGE_ID (0xf3U) + +typedef struct NV2080_CTRL_CMD_GPU_IS_RESET_COUPLED_PARAMS { + NvBool isResetCoupled; +} NV2080_CTRL_CMD_GPU_IS_RESET_COUPLED_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_DIELET_INFO + * + * Returns a list of dielet type/physical mask pairs. + * + * If a given dielet type may be present on a given arch but all instances are floorswept, a mask of 0x0 will be returned. + * If a given dielet type cannot exist on a given arch, no record for the dielet should be returned. + * + * dieletPairs[OUT] + * This field returns a series of key-value pairs of the format + * + * Possible status values returned are: + * NV_OK + */ + + +typedef enum NV2080_CTRL_GPU_DIELET_TYPE { + NV2080_CTRL_GPU_DIELET_TYPE_UGD = 0, + NV2080_CTRL_GPU_DIELET_TYPE_IODN = 1, + NV2080_CTRL_GPU_DIELET_TYPE_IODS = 2, + NV2080_CTRL_GPU_DIELET_TYPE_LAST = 3, +} NV2080_CTRL_GPU_DIELET_TYPE; + +typedef struct NV2080_CTRL_GPU_GET_DIELET_INFO { + NV2080_CTRL_GPU_DIELET_TYPE dieletType; + NvU32 typeSpecificId; +} NV2080_CTRL_GPU_GET_DIELET_INFO; + +#define NV2080_CTRL_GPU_GET_DIELET_INFO_MAX_SIZE (256U) + +#define NV2080_CTRL_CMD_GPU_GET_DIELET_INFO (0x208081f4U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_DIELET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_DIELET_INFO_PARAMS_MESSAGE_ID (0xf4U) + +typedef struct NV2080_CTRL_GPU_GET_DIELET_INFO_PARAMS { + NvU32 dieletListSize; + NV2080_CTRL_GPU_GET_DIELET_INFO dielets[NV2080_CTRL_GPU_GET_DIELET_INFO_MAX_SIZE]; +} NV2080_CTRL_GPU_GET_DIELET_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_UNIT_INFO_FROM_DIELET + * + * Returns a floorswept mask of a HW unit given a dielet type, dielet index, and HW unit. + * + * dieletType [IN] + * One of the types defined in NV2080_CTRL_GPU_DIELET_TYPE. + * dieletIndex [IN] + * Index of dielet used to query FS info. + * unitType [IN] + * One of the types defined in NV2080_CTRL_GPU_UNIT_TYPE. + * unitMask[OUT] + * This field returns a floorswept mask for a given HW unit type. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_GPU_GET_UNIT_FS_INFO_FROM_DIELET (0x208081f5U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_UNIT_FS_INFO_FROM_DIELET_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_GPU_UNIT_TYPE { + NV2080_CTRL_GPU_UNIT_TYPE_SYSLTC = 0, + NV2080_CTRL_GPU_UNIT_TYPE_SYSLTS = 1, + NV2080_CTRL_GPU_UNIT_TYPE_HSHUBCHI = 2, + NV2080_CTRL_GPU_UNIT_TYPE_HSHUBNVL = 3, + NV2080_CTRL_GPU_UNIT_TYPE_LAST = 4, +} NV2080_CTRL_GPU_UNIT_TYPE; + +#define NV2080_CTRL_GPU_GET_UNIT_FS_INFO_FROM_DIELET_PARAMS_MESSAGE_ID (0xf5U) + +typedef struct NV2080_CTRL_GPU_GET_UNIT_FS_INFO_FROM_DIELET_PARAMS { + NV2080_CTRL_GPU_DIELET_TYPE dieletType; + NvU32 dieletTypeSpecificId; + NV2080_CTRL_GPU_UNIT_TYPE unitType; + NvU32 unitMask; +} NV2080_CTRL_GPU_GET_UNIT_FS_INFO_FROM_DIELET_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GPU_SET_MIGRATION_BLOCK + * + * This command allows devtools processes to notify the Resource Manager when + * they enter or exit critical sections that cannot survive vGPU live migration. + * This enables selective migration blocking only during devtools critical + * operations, rather than blanket disabling migration when devtools are active. + * + * bIsDevtoolInUse + * This boolean parameter indicates whether the devtools is entering or + * exiting a critical section: + * NV_TRUE - Devtools is entering a critical section (block migration) + * NV_FALSE - Devtools is exiting a critical section (may allow migration) + */ +#define NV2080_CTRL_CMD_GPU_SET_MIGRATION_BLOCK (0x208001faU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_MIGRATION_BLOCK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_SET_MIGRATION_BLOCK_PARAMS_MESSAGE_ID (0xfaU) + +typedef struct NV2080_CTRL_GPU_SET_MIGRATION_BLOCK_PARAMS { + NvBool bIsDevtoolInUse; +} NV2080_CTRL_GPU_SET_MIGRATION_BLOCK_PARAMS; + +/* _ctrl2080gpu_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gpumon.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gpumon.h new file mode 100644 index 0000000..2398a0c --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gpumon.h @@ -0,0 +1,96 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080gpumon.finn +// + + + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/*! + * This structure represents base class of GPU monitoring sample. + */ +typedef struct NV2080_CTRL_GPUMON_SAMPLE { + /*! + * Timestamps in nano-seconds. + */ + NV_DECLARE_ALIGNED(NvU64 timeStamp, 8); +} NV2080_CTRL_GPUMON_SAMPLE; + +/*! + * This structure represents base GPU monitoring sample. + */ +typedef struct NV2080_CTRL_GPUMON_SAMPLES { + /*! + * Type of the sample, see NV2080_CTRL_GPUMON_SAMPLE_TYPE_* for reference. + */ + NvU8 type; + /*! + * Size of the buffer, this should be + * bufSize == NV2080_CTRL_*_GPUMON_SAMPLE_COUNT_* + * sizeof(derived type of NV2080_CTRL_GPUMON_SAMPLE). + */ + NvU32 bufSize; + /*! + * Number of samples in ring buffer. + */ + NvU32 count; + /*! + * tracks the offset of the tail in the circular queue array pSamples. + */ + NvU32 tracker; + /*! + * Pointer to a circular queue based on array of NV2080_CTRL_GPUMON_SAMPLE + * or its derived types structs with size == bufSize. + * + * @note This circular queue wraps around after 10 seconds of sampling, + * and it is clients' responsibility to query within this time frame in + * order to avoid losing samples. + * @note With one exception, this queue contains last 10 seconds of samples + * with tracker poiniting to oldest entry and entry before tracker as the + * newest entry. Exception is when queue is not full (i.e. tracker is + * pointing to a zeroed out entry), in that case valid entries are between 0 + * and tracker. + * @note Clients can store tracker from previous query in order to provide + * samples since last read. + */ + NV_DECLARE_ALIGNED(NvP64 pSamples, 8); +} NV2080_CTRL_GPUMON_SAMPLES; + +/*! + * Enumeration of GPU monitoring sample types. + */ +#define NV2080_CTRL_GPUMON_SAMPLE_TYPE_PWR_MONITOR_STATUS 0x00000001 +#define NV2080_CTRL_GPUMON_SAMPLE_TYPE_PERFMON_UTIL 0x00000002 + +/*! + * Macro for invalid PID. + */ +#define NV2080_GPUMON_PID_INVALID ((NvU32)(~0)) diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gr.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gr.h new file mode 100644 index 0000000..93172ac --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gr.h @@ -0,0 +1,2034 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080gr.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +#include "ctrl/ctrl0080/ctrl0080gr.h" /* 2080 is partially derivative of 0080 */ +#include "nvcfg_sdk.h" + +/* + * NV2080_CTRL_GR_ROUTE_INFO + * + * This structure specifies the routing information used to + * disambiguate the target GR engine. + * + * flags + * This field decides how the route field is interpreted + * + * route + * This field has the data to identify target GR engine + * + */ +#define NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE 1:0 +#define NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_NONE 0x0U +#define NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_ENGID 0x1U +#define NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_CHANNEL 0x2U + +#define NV2080_CTRL_GR_ROUTE_INFO_DATA_CHANNEL_HANDLE 31:0 +#define NV2080_CTRL_GR_ROUTE_INFO_DATA_ENGID 31:0 + +typedef NV0080_CTRL_GR_ROUTE_INFO NV2080_CTRL_GR_ROUTE_INFO; + +/* NV20_SUBDEVICE_XX gr control commands and parameters */ + +/* + * NV2080_CTRL_GR_INFO + * + * This structure represents a single 32bit gr engine value. Clients + * request a particular gr engine value by specifying a unique gr + * information index. + * + * Legal gr information index values are: + * NV2080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT + * This index is used to request the surface buffer alignment (in bytes) + * required by the associated subdevice. The return value is GPU + * implementation-dependent. + * NV2080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT + * This index is used to request the required swizzled surface alignment + * (in bytes) supported by the associated subdevice. The return value + * is GPU implementation-dependent. A return value of 0 indicates the GPU + * does not support swizzled surfaces. + * NV2080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE + * This index is used to request the vertex cache size (in entries) + * supported by the associated subdevice. The return value is GPU + * implementation-dependent. A value of 0 indicates the GPU does + * have a vertex cache. + * NV2080_CTRL_GR_INFO_INDEX_VPE_COUNT + * This index is used to request the number of VPE units supported by the + * associated subdevice. The return value is GPU implementation-dependent. + * A return value of 0 indicates the GPU does not contain VPE units. + * NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT + * This index is used to request the number of shader pipes supported by + * the associated subdevice. The return value is GPU + * implementation-dependent. A return value of 0 indicates the GPU does + * not contain dedicated shader units. + * For tesla: this value is the number of enabled TPCs + * NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT + * This index is used to request the number of sub units per + * shader pipes supported by the associated subdevice. The return + * value is GPU implementation-dependent. A return value of 0 indicates + * the GPU does not contain dedicated shader units. + * For tesla: this value is the number of enabled SMs (per TPC) + * NV2080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR + * This index is used to request the scaling factor for thread stack + * memory. + * A value of 0 indicates the GPU does not support this function. + * NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT + * This index is used to request the number of SM register banks supported. + * A value of 0 indicates the GPU does not support this function. + * NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT + * This index is used to request the number of registers per SM register + * bank. A value of 0 indicates the GPU does not support this function. + * NV2080_CTRL_GR_INFO_INDEX_SM_VERSION + * This index is used to determine the SM version. + * A value of 0 indicates the GPU does not support this function. + * Otherwise one of NV2080_CTRL_GR_INFO_SM_VERSION_*. + * NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM + * This index is used to determine the maximum number of warps + * (thread groups) per SM. + * A value of 0 indicates the GPU does not support this function. + * NV2080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP + * This index is used to determine the maximum number of threads + * in each warp (thread group). + * A value of 0 indicates the GPU does not support this function. + * NV2080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY + * This index is used to request the default fb memory read/write request + * size in bytes (typically based on the memory configuration/controller). + * Smaller memory requests are likely to take as long as a full one. + * A value of 0 indicates the GPU does not support this function. + * NV2080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY + * This index is used to request the default host memory read/write request + * size in bytes (typically based on the memory configuration/controller). + * Smaller memory requests are likely to take as long as a full one. + * A value of 0 indicates the GPU does not support this function. + * NV2080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM + * This index is used to request the maximum number of streaming processors + * per SM. + * NV2080_CTRL_GR_INFO_INDEX_LITTER_* + * This index is used to query the various LITTER size information from + * the chip. + * NV2080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED + * This index is used to query whether the chip has timeslice mode enabled. + * NV2080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT + * This index is used to return the number of "GPU Cores" + * supported by the graphics pipeline + * NV2080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT + * This index is used to return the number of "Ray Tracing Cores" + * supported by the graphics pipeline + * NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT + * This index is used to return the number of "Tensor Cores" + * supported by the graphics pipeline + * NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES + * This index is used to return the Graphics capabilities + * supported by the graphics pipeline + */ +typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO; + +/* + * Valid GR info index values + * These indices are offset from supporting the 0080 version of this call + */ +#define NV2080_CTRL_GR_INFO_INDEX_MAXCLIPS NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS +#define NV2080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 +#define NV2080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK +/** + * This index is used to request the surface buffer alignment (in bytes) + * required by the associated subdevice. The return value is GPU + * implementation-dependent. + */ +#define NV2080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT +#define NV2080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT +#define NV2080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE +/** + * This index is used to request the number of VPE units supported by the + * associated subdevice. The return value is GPU implementation-dependent. + * A return value of 0 indicates the GPU does not contain VPE units. + */ +#define NV2080_CTRL_GR_INFO_INDEX_VPE_COUNT NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT +/** + * This index is used to request the number of shader pipes supported by + * the associated subdevice. The return value is GPU + * implementation-dependent. A return value of 0 indicates the GPU does + * not contain dedicated shader units. + * For tesla: this value is the number of enabled TPCs + */ +#define NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT +/** + * This index is used to request the scaling factor for thread stack + * memory. + * A value of 0 indicates the GPU does not support this function. + */ +#define NV2080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR +/** + * This index is used to request the number of sub units per + * shader pipes supported by the associated subdevice. The return + * value is GPU implementation-dependent. A return value of 0 indicates + * the GPU does not contain dedicated shader units. + * For tesla: this value is the number of enabled SMs (per TPC) + */ +#define NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT +#define NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT +#define NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT +/** + * This index is used to determine the SM version. + * A value of 0 indicates the GPU does not support this function. + * Otherwise one of NV2080_CTRL_GR_INFO_SM_VERSION_*. + */ +#define NV2080_CTRL_GR_INFO_INDEX_SM_VERSION NV0080_CTRL_GR_INFO_INDEX_SM_VERSION +/** + * This index is used to determine the maximum number of warps + * (thread groups) per SM. + * A value of 0 indicates the GPU does not support this function. + */ +#define NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM +/** + * This index is used to determine the maximum number of threads + * in each warp (thread group). + * A value of 0 indicates the GPU does not support this function. + */ +#define NV2080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP +#define NV2080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES +#define NV2080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES +#define NV2080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY +#define NV2080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY +#define NV2080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS +#define NV2080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC +#define NV2080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS +/** + * This index is used to return the number of "Ray Tracing Cores" + * supported by the graphics pipeline + */ +#define NV2080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT +#define NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC +#define NV2080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP +#define NV2080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT +#define NV2080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT +#define NV2080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC + +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES + + +#define NV2080_CTRL_GR_INFO_INDEX_RESERVED NV0080_CTRL_GR_INFO_INDEX_RESERVED +#define NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES +#define NV2080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES +#define NV2080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET NV0080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_CPC_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_CPC_PER_GPC +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_HSHUB_NVLINK_MASK NV0080_CTRL_GR_INFO_INDEX_LITTER_HSHUB_NVLINK_MASK +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_HSHUB_C2C_MASK NV0080_CTRL_GR_INFO_INDEX_LITTER_HSHUB_C2C_MASK +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_HSHUB_PCIE_MASK NV0080_CTRL_GR_INFO_INDEX_LITTER_HSHUB_PCIE_MASK + + +#define NV2080_CTRL_GR_INFO_INDEX_RESERVED1 NV0080_CTRL_GR_INFO_INDEX_RESERVED1 + +/* When adding a new INDEX, please update INDEX_MAX and MAX_SIZE accordingly + * NOTE: 0080 functionality is merged with 2080 functionality, so this max size + * reflects that. + */ +#define NV2080_CTRL_GR_INFO_INDEX_MAX NV0080_CTRL_GR_INFO_INDEX_MAX +#define NV2080_CTRL_GR_INFO_MAX_SIZE NV0080_CTRL_GR_INFO_MAX_SIZE + +/* valid SM version return values */ + +#define NV2080_CTRL_GR_INFO_SM_VERSION_NONE (0x00000000U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_1_05 (0x00000105U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_1_1 (0x00000110U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_1_2 (0x00000120U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_1_3 (0x00000130U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_1_4 (0x00000140U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_1_5 (0x00000150U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_2_0 (0x00000200U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_2_1 (0x00000210U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_2_2 (0x00000220U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_3_0 (0x00000300U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_3_1 (0x00000310U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_3_2 (0x00000320U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_3_3 (0x00000330U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_3_5 (0x00000350U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_3_6 (0x00000360U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_3_8 (0x00000380U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_3_9 (0x00000390U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_4_0 (0x00000400U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_5_0 (0x00000500U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_5_02 (0x00000502U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_5_03 (0x00000503U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_6_0 (0x00000600U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_6_01 (0x00000601U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_6_02 (0x00000602U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_0 (0x00000700U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_01 (0x00000701U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_02 (0x00000702U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_03 (0x00000703U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_05 (0x00000705U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_02 (0x00000802U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_06 (0x00000806U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_07 (0x00000807U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_08 (0x00000808U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_09 (0x00000809U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_9_00 (0x00000900U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_10_00 (0x00000A00U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_10_01 (0x00000A01U) + +#define NV2080_CTRL_GR_INFO_SM_VERSION_10_03 (0x00000A03U) + + +/* + * TODO Bug 4333440 is introducing versions 12_*. + * Eventually once 12_* is tested and validated, another + * follow up change will be needed to remove 10_04 support. + */ +#define NV2080_CTRL_GR_INFO_SM_VERSION_10_04 (0x00000A04U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_12_00 (0x00000C00U) + + +#define NV2080_CTRL_GR_INFO_SM_VERSION_12_01 (0x00000C01U) + + +#define NV2080_CTRL_GR_INFO_SM_VERSION_10_05 (0x00000A05U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_13_00 (0x00000D00U) + + + +/* compatibility SM versions to match the official names in the ISA (e.g., SM5.2) */ +#define NV2080_CTRL_GR_INFO_SM_VERSION_5_2 (NV2080_CTRL_GR_INFO_SM_VERSION_5_02) +#define NV2080_CTRL_GR_INFO_SM_VERSION_5_3 (NV2080_CTRL_GR_INFO_SM_VERSION_5_03) +#define NV2080_CTRL_GR_INFO_SM_VERSION_6_1 (NV2080_CTRL_GR_INFO_SM_VERSION_6_01) +#define NV2080_CTRL_GR_INFO_SM_VERSION_6_2 (NV2080_CTRL_GR_INFO_SM_VERSION_6_02) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_1 (NV2080_CTRL_GR_INFO_SM_VERSION_7_01) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_2 (NV2080_CTRL_GR_INFO_SM_VERSION_7_02) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_3 (NV2080_CTRL_GR_INFO_SM_VERSION_7_03) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_5 (NV2080_CTRL_GR_INFO_SM_VERSION_7_05) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_2 (NV2080_CTRL_GR_INFO_SM_VERSION_8_02) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_6 (NV2080_CTRL_GR_INFO_SM_VERSION_8_06) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_7 (NV2080_CTRL_GR_INFO_SM_VERSION_8_07) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_8 (NV2080_CTRL_GR_INFO_SM_VERSION_8_08) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_9 (NV2080_CTRL_GR_INFO_SM_VERSION_8_09) +#define NV2080_CTRL_GR_INFO_SM_VERSION_9_0 (NV2080_CTRL_GR_INFO_SM_VERSION_9_00) +#define NV2080_CTRL_GR_INFO_SM_VERSION_10_0 (NV2080_CTRL_GR_INFO_SM_VERSION_10_00) +#define NV2080_CTRL_GR_INFO_SM_VERSION_10_1 (NV2080_CTRL_GR_INFO_SM_VERSION_10_01) + +#define NV2080_CTRL_GR_INFO_SM_VERSION_10_3 (NV2080_CTRL_GR_INFO_SM_VERSION_10_03) + + +#define NV2080_CTRL_GR_INFO_SM_VERSION_10_4 (NV2080_CTRL_GR_INFO_SM_VERSION_10_04) + + +#define NV2080_CTRL_GR_INFO_SM_VERSION_10_5 (NV2080_CTRL_GR_INFO_SM_VERSION_10_05) +#define NV2080_CTRL_GR_INFO_SM_VERSION_13_0 (NV2080_CTRL_GR_INFO_SM_VERSION_13_00) + + + +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D 0:0 +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_FALSE 0x0U +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_TRUE 0x1U +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D 1:1 +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_FALSE 0x0U +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_TRUE 0x1U +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE 2:2 +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_FALSE 0x0U +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_TRUE 0x1U +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M 3:3 +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_FALSE 0x0U +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_TRUE 0x1U + +/** + * NV2080_CTRL_CMD_GR_GET_INFO + * + * This command returns gr engine information for the associated GPU. + * Requests to retrieve gr information use a list of one or more + * NV2080_CTRL_GR_INFO structures. + * + * grInfoListSize + * This field specifies the number of entries on the caller's + * grInfoList. + * grInfoList + * This field specifies a pointer in the caller's address space + * to the buffer into which the gr information is to be returned. + * This buffer must be at least as big as grInfoListSize multiplied + * by the size of the NV2080_CTRL_GR_INFO structure. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. When MIG is enabled, this + * is a mandatory parameter. + */ +#define NV2080_CTRL_CMD_GR_GET_INFO (0x20801201U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_GR_GET_INFO_PARAMS { + NvU32 grInfoListSize; + NV_DECLARE_ALIGNED(NvP64 grInfoList, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_GET_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE + * + * This command is used to set the zcull context switch mode for the specified + * channel. A value of NV_ERR_NOT_SUPPORTED is returned if the + * target channel does not support zcull context switch mode changes. + * + * hChannel + * This parameter specifies the channel handle of + * the channel that is to have it's zcull context switch mode changed. + * hShareClient + * Support for sharing zcull buffers across RM clients is no longer + * supported. To maintain API compatibility, this field must match + * the hClient used in the control call. + * hShareChannel + * This parameter specifies the channel handle of + * the channel with which the zcull context buffer is to be shared. This + * parameter is valid when zcullMode is set to SEPARATE_BUFFER. This + * parameter should be set to the same value as hChannel if no + * sharing is intended. + * zcullMode + * This parameter specifies the new zcull context switch mode. + * Legal values for this parameter include: + * NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_GLOBAL + * This mode is the normal zcull operation where it is not + * context switched and there is one set of globally shared + * zcull memory and tables. This mode is only supported as + * long as all channels use this mode. + * NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_NO_CTXSW + * This mode causes the zcull tables to be reset on a context + * switch, but the zcull buffer will not be saved/restored. + * NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_SEPARATE_BUFFER + * This mode will cause the zcull buffers and tables to be + * saved/restored on context switches. If a share channel + * ID is given (shareChID), then the 2 channels will share + * the zcull context buffers. + */ +#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE (0x20801205U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS { + NvHandle hChannel; + NvHandle hShareClient; + NvHandle hShareChannel; + NvU32 zcullMode; +} NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS; +/* valid zcullMode values */ +#define NV2080_CTRL_CTXSW_ZCULL_MODE_GLOBAL (0x00000000U) +#define NV2080_CTRL_CTXSW_ZCULL_MODE_NO_CTXSW (0x00000001U) +#define NV2080_CTRL_CTXSW_ZCULL_MODE_SEPARATE_BUFFER (0x00000002U) + +/** + * NV2080_CTRL_CMD_GR_GET_ZCULL_INFO + * + * This command is used to query the RM for zcull information that the + * driver will need to allocate and manage the zcull regions. + * + * widthAlignPixels + * This parameter returns the width alignment restrictions in pixels + * used to adjust a surface for proper aliquot coverage (typically + * #TPC's * 16). + * + * heightAlignPixels + * This parameter returns the height alignment restrictions in pixels + * used to adjust a surface for proper aliquot coverage (typically 32). + * + * pixelSquaresByAliquots + * This parameter returns the pixel area covered by an aliquot + * (typically #Zcull_banks * 16 * 16). + * + * aliquotTotal + * This parameter returns the total aliquot pool available in HW. + * + * zcullRegionByteMultiplier + * This parameter returns multiplier used to convert aliquots in a region + * to the number of bytes required to save/restore them. + * + * zcullRegionHeaderSize + * This parameter returns the region header size which is required to be + * allocated and accounted for in any save/restore operation on a region. + * + * zcullSubregionHeaderSize + * This parameter returns the subregion header size which is required to be + * allocated and accounted for in any save/restore operation on a region. + * + * subregionCount + * This parameter returns the subregion count. + * + * subregionWidthAlignPixels + * This parameter returns the subregion width alignment restrictions in + * pixels used to adjust a surface for proper aliquot coverage + * (typically #TPC's * 16). + * + * subregionHeightAlignPixels + * This parameter returns the subregion height alignment restrictions in + * pixels used to adjust a surface for proper aliquot coverage + * (typically 62). + * + * The callee should compute the size of a zcull region as follows. + * (numBytes = aliquots * zcullRegionByteMultiplier + + * zcullRegionHeaderSize + zcullSubregionHeaderSize) + */ +#define NV2080_CTRL_CMD_GR_GET_ZCULL_INFO (0x20801206U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_SUBREGION_SUPPORTED +#define NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS { + NvU32 widthAlignPixels; + NvU32 heightAlignPixels; + NvU32 pixelSquaresByAliquots; + NvU32 aliquotTotal; + NvU32 zcullRegionByteMultiplier; + NvU32 zcullRegionHeaderSize; + NvU32 zcullSubregionHeaderSize; + NvU32 subregionCount; + NvU32 subregionWidthAlignPixels; + NvU32 subregionHeightAlignPixels; +} NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_CTXSW_PM_MODE + * + * This command is used to set the pm context switch mode for the specified + * channel. A value of NV_ERR_NOT_SUPPORTED is returned if the + * target channel does not support pm context switch mode changes. + * + * hChannel + * This parameter specifies the channel handle of + * the channel that is to have its pm context switch mode changed. + * pmMode + * This parameter specifies the new pm context switch mode. + * Legal values for this parameter include: + * NV2080_CTRL_CTXSW_PM_MODE_NO_CTXSW + * This mode says that the pms are not to be context switched. + * NV2080_CTRL_CTXSW_PM_MODE_CTXSW + * This mode says that the pms in Mode-B are to be context switched. + * NV2080_CTRL_CTXSW_PM_MODE_STREAM_OUT_CTXSW + * This mode says that the pms in Mode-E (stream out) are to be context switched. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_CTXSW_PM_MODE (0x20801207U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS { + NvHandle hChannel; + NvU32 pmMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS; + +/* valid pmMode values */ +#define NV2080_CTRL_CTXSW_PM_MODE_NO_CTXSW (0x00000000U) +#define NV2080_CTRL_CTXSW_PM_MODE_CTXSW (0x00000001U) +#define NV2080_CTRL_CTXSW_PM_MODE_STREAM_OUT_CTXSW (0x00000002U) + +/* + * NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND + * + * This command is used to set the zcull context switch mode and virtual address + * for the specified channel. A value of NV_ERR_NOT_SUPPORTED is + * returned if the target channel does not support zcull context switch mode + * changes. + * + * hClient + * This parameter specifies the client handle of + * that owns the zcull context buffer. This field must match + * the hClient used in the control call for non-kernel clients. + * hChannel + * This parameter specifies the channel handle of + * the channel that is to have its zcull context switch mode changed. + * vMemPtr + * This parameter specifies the 64 bit virtual address + * for the allocated zcull context buffer. + * zcullMode + * This parameter specifies the new zcull context switch mode. + * Legal values for this parameter include: + * NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_GLOBAL + * This mode is the normal zcull operation where it is not + * context switched and there is one set of globally shared + * zcull memory and tables. This mode is only supported as + * long as all channels use this mode. + * NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_NO_CTXSW + * This mode causes the zcull tables to be reset on a context + * switch, but the zcull buffer will not be saved/restored. + * NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_SEPARATE_BUFFER + * This mode will cause the zcull buffers and tables to be + * saved/restored on context switches. If a share channel + * ID is given (shareChID), then the 2 channels will share + * the zcull context buffers. + */ +#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND (0x20801208U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS { + NvHandle hClient; + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 vMemPtr, 8); + NvU32 zcullMode; +} NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS; +/* valid zcullMode values same as above NV2080_CTRL_CTXSW_ZCULL_MODE */ + +/* + * NV2080_CTRL_CMD_GR_CTXSW_PM_BIND + * + * This command is used to set the PM context switch mode and virtual address + * for the specified channel. A value of NV_ERR_NOT_SUPPORTED is + * returned if the target channel does not support PM context switch mode + * changes. + * + * hClient + * This parameter specifies the client handle of + * that owns the PM context buffer. + * hChannel + * This parameter specifies the channel handle of + * the channel that is to have its PM context switch mode changed. + * vMemPtr + * This parameter specifies the 64 bit virtual address + * for the allocated PM context buffer. + * pmMode + * This parameter specifies the new PM context switch mode. + * Legal values for this parameter include: + * NV2080_CTRL_GR_SET_CTXSW_PM_MODE_NO_CTXSW + * This mode says that the pms are not to be context switched + * NV2080_CTRL_GR_SET_CTXSW_PM_MODE_CTXSW + * This mode says that the pms are to be context switched + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_CTXSW_PM_BIND (0x20801209U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS { + NvHandle hClient; + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 vMemPtr, 8); + NvU32 pmMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS; +/* valid pmMode values same as above NV2080_CTRL_CTXSW_PM_MODE */ + +/* + * NV2080_CTRL_CMD_GR_CTXSW_SETUP_BIND + * + * This command is used to set the Setup context switch mode and virtual address + * for the specified channel. A value of NV_ERR_NOT_SUPPORTED is + * returned if the target channel does not support setup context switch mode + * changes. + * + * hClient + * This parameter specifies the client handle of + * that owns the Setup context buffer. This field must match + * the hClient used in the control call for non-kernel clients. + * hChannel + * This parameter specifies the channel handle of + * the channel that is to have its Setup context switch mode changed. + * vMemPtr + * This parameter specifies the 64 bit virtual address + * for the allocated Setup context buffer. + */ +#define NV2080_CTRL_CMD_GR_CTXSW_SETUP_BIND (0x2080123aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID (0x3AU) + +typedef struct NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS { + NvHandle hClient; + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 vMemPtr, 8); +} NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP + * + * Send a list of values used to describe GPC/TPC tile mapping tables. + * + * mapValueCount + * This field specifies the number of actual map entries. This count + * should equal the number of TPCs in the system. + * mapValues + * This field is a pointer to a buffer of NvU08 values representing map + * data. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_GR_SET_GPC_TILE_MAP_MAX_VALUES 128U +#define NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP (0x2080120aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS { + NvU32 mapValueCount; + NvU8 mapValues[NV2080_CTRL_GR_SET_GPC_TILE_MAP_MAX_VALUES]; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE + * + * This command is used to set the SMPC context switch mode for the specified + * channel or channel group (TSG). A value of NV_ERR_NOT_SUPPORTED + * is returned if the target channel/TSG does not support SMPC context switch + * mode changes. If a channel is part of a TSG, the user must send in the TSG + * handle and not an individual channel handle, an error will be returned if a + * channel handle is used in this case. + * + * SMPC = SM Performance Counters + * + * hChannel + * This parameter specifies the channel or channel group (TSG) handle + * that is to have its SMPC context switch mode changed. + * If this parameter is set to 0, then the mode below applies to all current + * and future channels (i.e. we will be enabling/disabling global mode) + * smpcMode + * This parameter specifies the new SMPC context switch mode. + * Legal values for this parameter include: + * NV2080_CTRL_GR_SET_CTXSW_SMPC_MODE_NO_CTXSW + * This mode says that the SMPC data is not to be context switched. + * NV2080_CTRL_GR_SET_CTXSW_SMPC_MODE_CTXSW + * This mode says that the SMPC data is to be context switched. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE (0x2080120eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS { + NvHandle hChannel; + NvU32 smpcMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS; + +/* valid smpcMode values */ +#define NV2080_CTRL_CTXSW_SMPC_MODE_NO_CTXSW (0x00000000U) +#define NV2080_CTRL_CTXSW_SMPC_MODE_CTXSW (0x00000001U) + +/* + * NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS + * + * This command returns an array of the mappings between SMs and GPC/TPCs. + * + * smId + * An array of the mappings between SMs and GPC/TPCs. + * smCount + * Returns the number of valid mappings in the array. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS (0x2080120fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_MAX_SM_COUNT 512U +#define NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS { + struct { + NvU32 gpcId; + NvU32 tpcId; + } smId[NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_MAX_SM_COUNT]; + NvU32 smCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE + * + * This command is used to set the preemption context switch mode for the specified + * channel. A value of NV_ERR_NOT_SUPPORTED is returned if the + * target channel does not support preemption context switch mode changes. + * + * flags + * This field specifies flags for the preemption mode changes. + * These flags can tell callee which mode is valid in the call + * since we handle graphics and/or compute + * hChannel + * This parameter specifies the channel handle of the channel + * that is to have it's preemption context switch mode set. + * gfxpPreemptMode + * This parameter specifies the new Graphics preemption context switch + * mode. Legal values for this parameter include: + * NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_WFI + * This mode is the normal wait-for-idle context switch mode. + * NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP + * This mode causes the graphics engine to allow preempting the + * channel mid-triangle. + * NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP_POOL + * This mode causes the graphics engine to use a shared pool of buffers + * to support GfxP with lower memory overhead + * cilpPreemptMode + * This parameter specifies the new Compute preemption context switch + * mode. Legal values for this parameter include: + * NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_WFI + * This mode is the normal wait-for-idle context switch mode. + * NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CTA + * This mode causes the compute engine to allow preempting the channel + * at the instruction level. + * NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CILP + * This mode causes the compute engine to allow preempting the channel + * at the instruction level. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE (0x20801210U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS { + NvU32 flags; + NvHandle hChannel; + NvU32 gfxpPreemptMode; + NvU32 cilpPreemptMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS; + +/* valid preemption flags */ +#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP 0:0 +#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_IGNORE (0x00000000U) +#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_SET (0x00000001U) +#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP 1:1 +#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_IGNORE (0x00000000U) +#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_SET (0x00000001U) + +/* valid Graphics mode values */ +#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_WFI (0x00000000U) +#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP (0x00000001U) +#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP_POOL (0x00000002U) + +/* valid Compute mode values */ +#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_WFI (0x00000000U) +#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CTA (0x00000001U) +#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CILP (0x00000002U) + +/* valid preemption buffers */ +typedef enum NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS { + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_MAIN = 0, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SPILL = 1, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_PAGEPOOL = 2, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_BETACB = 3, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_RTV = 4, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL = 5, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL = 6, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL_CPU = 7, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SETUP = 8, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END = 9, +} NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS; + +/* + * NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND + * + * This command is used to set the preemption context switch mode and virtual + * addresses of the preemption buffers for the specified channel. A value of + * NV_ERR_NOT_SUPPORTED is returned if the target channel does not + * support preemption context switch mode changes. + * + * flags + * This field specifies flags for the preemption mode changes. + * These flags can tell callee which mode is valid in the call + * since we handle graphics and/or compute + * hClient + * This parameter specifies the client handle of + * that owns the preemption context buffer. + * hChannel + * This parameter specifies the channel handle of the channel + * that is to have its preemption context switch mode set. + * vMemPtr + * This parameter specifies the 64 bit virtual address + * for the allocated preemption context buffer. + * gfxpPreemptMode + * This parameter specifies the new Graphics preemption context switch + * mode. Legal values for this parameter include: + * NV2080_CTRL_CTXSW_PREEMPTION_MODE_GFX_WFI + * This mode is the normal wait-for-idle context switch mode. + * NV2080_CTRL_CTXSW_PREEMPTION_MODE_GFX_GFXP + * This mode causes the graphics engine to allow preempting the + * channel mid-triangle. + * cilpPreemptMode + * This parameter specifies the new Compute preemption context switch + * mode. Legal values for this parameter include: + * NV2080_CTRL_CTXSW_PREEMPTION_MODE_COMPUTE_WFI + * This mode is the normal wait-for-idle context switch mode. + * NV2080_CTRL_CTXSW_PREEMPTION_MODE_COMPUTE_CTA + * This mode causes the compute engine to allow preempting the channel + * at the instruction level. + * NV2080_CTRL_CTXSW_PREEMPTION_MODE_COMPUTE_CILP + * This mode causes the compute engine to allow preempting the channel + * at the instruction level. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND (0x20801211U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS { + NvU32 flags; + NvHandle hClient; + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 vMemPtrs[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END], 8); + NvU32 gfxpPreemptMode; + NvU32 cilpPreemptMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS; +/* valid mode and flag values same as above NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE */ + +/* + * NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE + * + * This command is used to apply the WAR for PC sampling to avoid hang in + * multi-ctx scenario. + * + * hChannel + * This parameter specifies the channel or channel group (TSG) handle + * that is to have its PC Sampling mode changed. + * samplingMode + * This parameter specifies whether sampling is turned ON or OFF. + * Legal values for this parameter include: + * NV2080_CTRL_GR_SET_PC_SAMPLING_MODE_DISABLED + * This mode says that PC sampling is disabled for current context. + * NV2080_CTRL_GR_SET_PC_SAMPLING_MODE_ENABLED + * This mode says that PC sampling is disabled for current context. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE (0x20801212U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS { + NvHandle hChannel; + NvU32 samplingMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS; + +/* valid samplingMode values */ +#define NV2080_CTRL_PC_SAMPLING_MODE_DISABLED (0x00000000U) +#define NV2080_CTRL_PC_SAMPLING_MODE_ENABLED (0x00000001U) + +/* + * NV2080_CTRL_CMD_GR_GET_ROP_INFO + * + * Gets information about ROPs including the ROP unit count and information + * about ROP operations per clock. + * + * ropUnitCount + * The count of active ROP units. + * ropOperationsFactor. + * The number of ROP operations per clock for a single ROP unit. + * ropOperationsCount + * The number of ROP operations per clock across all active ROP units. + */ +#define NV2080_CTRL_CMD_GR_GET_ROP_INFO (0x20801213U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV2080_CTRL_GR_GET_ROP_INFO_PARAMS { + NvU32 ropUnitCount; + NvU32 ropOperationsFactor; + NvU32 ropOperationsCount; +} NV2080_CTRL_GR_GET_ROP_INFO_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GR_GET_CTXSW_STATS + * + * This command is used to get the context switch statistics. The user can + * also add a flag to tell RM to reset the stats counters back to 0. + * + * hChannel + * This parameter specifies the channel or channel group (TSG) handle + * that is to have the stats returned. Note, must be the TSG handle if + * channel is part of a TSG. + * flags + * This parameter specifies processing flags. See possible flags below. + * saveCnt + * This parameter returns the number of saves on the channel. + * restoreCnt + * This parameter returns the number of restores on the channel. + * wfiSaveCnt + * This parameter returns the number of WFI saves on the channel. + * ctaSaveCnt + * This parameter returns the number of CTA saves on the channel. + * cilpSaveCnt + * This parameter returns the number of CILP saves on the channel. + * gfxpSaveCnt + * This parameter returns the number of GfxP saves on the channel. + */ +#define NV2080_CTRL_CMD_GR_GET_CTXSW_STATS (0x20801215U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS { + NvHandle hChannel; + NvU32 flags; + NvU32 saveCnt; + NvU32 restoreCnt; + NvU32 wfiSaveCnt; + NvU32 ctaSaveCnt; + NvU32 cilpSaveCnt; + NvU32 gfxpSaveCnt; +} NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS; +/* valid GET_CTXSW_STATS flags settings */ +#define NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET 0:0 +#define NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_FALSE (0x00000000U) +#define NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_TRUE (0x00000001U) + + + +/* + * NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE + * + * This command provides the size, alignment of all context buffers including global and + * local context buffers which has been created & will be mapped on a context + * + * hChannel [IN] + * This parameter specifies the channel or channel group (TSG) handle + * totalBufferSize [OUT] + * This parameter returns the total context buffers size. + */ +#define NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE (0x20801218U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS { + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 totalBufferSize, 8); +} NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS; + +/* + * NV2080_CTRL_GR_CTX_BUFFER_INFO + * alignment + * Specifies the alignment requirement for each context buffer + * size + * Aligned size of context buffer + * bufferHandle [deprecated] + * Opaque pointer to memdesc. Used by kernel clients for tracking purpose only. + * pageCount + * allocation size in the form of pageCount + * physAddr + * Physical address of the buffer first page + * bufferType + * NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID type of this buffer + * aperture + * allocation aperture. Could be SYSMEM, VIDMEM, UNKNOWN + * kind + * PTE kind of this allocation. + * pageSize + * Page size of the buffer. + * bIsContigous + * States if physical allocation for this buffer is contiguous. PageSize will + * have no meaning if this flag is set. + * bGlobalBuffer + * States if a defined buffer is global as global buffers need to be mapped + * only once in TSG. + * bLocalBuffer + * States if a buffer is local to a channel. + * bDeviceDescendant + * TRUE if the allocation is a constructed under a Device or Subdevice. + * uuid + * SHA1 UUID of the Device or Subdevice. Valid when deviceDescendant is TRUE. + */ +typedef struct NV2080_CTRL_GR_CTX_BUFFER_INFO { + NV_DECLARE_ALIGNED(NvU64 alignment, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NV_DECLARE_ALIGNED(NvP64 bufferHandle, 8); + NV_DECLARE_ALIGNED(NvU64 pageCount, 8); + NV_DECLARE_ALIGNED(NvU64 physAddr, 8); + NvU32 bufferType; + NvU32 aperture; + NvU32 kind; + NvU32 pageSize; + NvBool bIsContigous; + NvBool bGlobalBuffer; + NvBool bLocalBuffer; + NvBool bDeviceDescendant; + NvU8 uuid[16]; +} NV2080_CTRL_GR_CTX_BUFFER_INFO; +typedef struct NV2080_CTRL_GR_CTX_BUFFER_INFO *PNV2080_CTRL_GR_CTX_BUFFER_INFO; + +#define NV2080_CTRL_GR_MAX_CTX_BUFFER_COUNT 64U + +/* + * NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_INFO + * + * This command provides the size, alignment of all context buffers including global and + * local context buffers which has been created & will be mapped on a context. + * If the client invoking the command is a kernel client, the buffers are retained. + * + * hUserClient [IN] + * This parameter specifies the client handle that owns this channel. + * hChannel [IN] + * This parameter specifies the channel or channel group (TSG) handle + * bufferCount [OUT] + * This parameter specifies the number of entries in ctxBufferInfo filled + * by the command. + * ctxBufferInfo [OUT] + * Array of context buffer info containing alignment, size etc. + */ +#define NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_INFO (0x20801219U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS { + NvHandle hUserClient; + NvHandle hChannel; + NvU32 bufferCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTX_BUFFER_INFO ctxBufferInfo[NV2080_CTRL_GR_MAX_CTX_BUFFER_COUNT], 8); +} NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS; + +// Aperture flags. The defines should match the defines in mem_desc.h +#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_UNKNOWN 0 +#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_SYSMEM 1 +#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_FBMEM 2 + +/* + * NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER + * This command returns the global logical ordering of SM w.r.t GPCs/TPCs. + * + * NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS + * This structure holds the TPC/SM ordering info. + * + * gpcId + * Logical GPC Id. + * This is the ordering of enabled GPCs post floor sweeping. + * The GPCs are numbered from 0 to N-1, where N is the enabled GPC count. + * + * localTpcId + * Local Logical TPC Id. + * This is the ordering of enabled TPCs within a GPC post floor sweeping. + * This ID is used in conjunction with the gpcId. + * The TPCs are numbered from 0 to N-1, where N is the enabled TPC count for the given GPC. + * + * localSmId + * Local Logical SM Id. + * This is the ordering of enabled SMs within a TPC post floor sweeping. + * This ID is used in conjunction with the localTpcId. + * The SMs are numbered from 0 to N-1, where N is the enabled SM count for the given TPC. + * + * globalTpcId + * Global Logical TPC Id. + * This is the ordering of all enabled TPCs in the GPU post floor sweeping. + * The TPCs are numbered from 0 to N-1, where N is the enabled TPC count across all GPCs + * + * globalSmId + * Global Logical SM Id array. + * This is the global ordering of all enabled SMs in the GPU post floor sweeping. + * The SMs are numbered from 0 to N-1, where N is the enabled SM count across all GPCs. + * + * virtualGpcId + * Virtual GPC Id. + * This is the ordering of enabled GPCs post floor sweeping (ordered in increasing + * number of TPC counts) The GPCs are numbered from 0 to N-1, where N is the + * enabled GPC count and 8-23 for singleton TPC holders. + * + * migratableTpcId + * Migratable TPC Id. + * This is the same as the Local Tpc Id for virtual GPC 0-8 (true physical gpcs) and 0 for + * virtual gpcs 8-23 that represent singleton tpcs. + * + * numSm + * Enabled SM count across all GPCs. + * This represent the valid entries in the globalSmId array + * + * numTpc + * Enabled TPC count across all GPCs. + * + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + * ugpuId + * Specifies the uGPU ID on Hopper+. + * + */ +#define NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER (0x2080121bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER_MAX_SM_COUNT 512U + +#define NV2080_CTRL_GR_DISABLED_SM_VGPC_ID 0xFFU + +#define NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x1BU) + +typedef struct NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS { + struct { + NvU16 gpcId; + NvU16 localTpcId; + NvU16 localSmId; + NvU16 globalTpcId; + NvU16 virtualGpcId; + NvU16 migratableTpcId; + NvU16 ugpuId; + NvU16 physicalCpcId; + NvU16 virtualTpcId; + } globalSmId[NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER_MAX_SM_COUNT]; + + NvU16 numSm; + NvU16 numTpc; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS; + +/* +* NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL +* +* This command gives current resident channel on GR engine +* +* chID [OUT] +* RM returns current resident channel on GR engine +* grRouteInfo [IN] +* This parameter specifies the routing information used to +* disambiguate the target GR engine. +*/ +#define NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL (0x2080121cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS_MESSAGE_ID (0x1CU) + +typedef struct NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS { + NvU32 chID; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE + * + * This command provides the size of GR attribute buffer. + * + * attribBufferSize [OUT] + * This parameter returns the attribute buffer size. + */ +#define NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE (0x2080121eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x1EU) + +typedef struct NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS { + NvU32 attribBufferSize; +} NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE + * + * This API queries size parameters for a request maximum graphics preemption + * pool size. It is only available to kernel callers + * + * NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS + * struct to return the size parameters + * + * maxSlots + * Input specifying the maximum number of slots, RM will calculate the output + * parameters based on this. Must be non-zero + * ctrlStructSize + * Output indicating the required size in bytes of the control structure to + * support a pool of maxSlots size. + * ctrlStructAlign + * Output indicating the required alignment of the control structure + * poolSize + * Output indicating the required size in bytes of the GfxP Pool. + * poolAlign + * Output indicating the required alignment of the GfxP Pool + * slotStride + * The number of bytes in each slot, i * slotStride gives the offset from the + * base of the pool to a given slot + */ +#define NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE (0x2080121fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS_MESSAGE_ID (0x1FU) + +typedef struct NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS { + NvU32 maxSlots; + NvU32 slotStride; + NV_DECLARE_ALIGNED(NvU64 ctrlStructSize, 8); + NV_DECLARE_ALIGNED(NvU64 ctrlStructAlign, 8); + NV_DECLARE_ALIGNED(NvU64 poolSize, 8); + NV_DECLARE_ALIGNED(NvU64 poolAlign, 8); +} NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE + * + * This API takes a CPU pointer to a GFxP Pool Control Structure and does the + * required onetime initialization. It should be called once and only once + * before a pool is used. It is only accessible to kernel callers. + * + * NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS + * struct to hand in the required info to RM + * + * maxSlots + * Max pool slots + * hMemory + * Handle to GFX Pool memory + * offset + * Offset of the control structure in GFX Pool memory + * size + * Size of the control structure + */ +#define NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE (0x20801220U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS { + NvU32 maxSlots; + NvHandle hMemory; + NvU32 offset; + NvU32 size; +} NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS; + +#define NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS 64U + +/* + * NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS + * + * This API adds a list of buffer slots to a given control structure. It can + * only be called when no channel using the given pool is running or may become + * running for the duration of this call. If more slots are added than there + * is room for in the control structure the behavior is undefined. It is only + * accessible to kernel callers. + * + * NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS + * + * numSlots + * This input indicates how many slots are being added and are contained in the slots parameter + * slots + * This input contains an array of the slots to be added to the control structure + * hMemory + * Handle to GFX Pool memory + * offset + * Offset of the control structure in GFX Pool memory + * size + * Size of the control structure + */ +#define NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS (0x20801221U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID (0x21U) + +typedef struct NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS { + NvU32 numSlots; + NvU32 slots[NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS]; + NvHandle hMemory; + NvU32 offset; + NvU32 size; +} NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS + * + * This API removes buffer slots from a given control structure. It can + * only be called when no channel using the given pool is running or may become + * running for the duration of this call. It can operate in two modes, either + * it will a specified number of slots, or a specified list of slots. + * + * It is only accessible to kernel callers. + * + * NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS_PARAMS + * + * numSlots + * This input indicates how many slots are being removed. if + * bRemoveSpecificSlots is true, then it also indicates how many entries in + * the slots array are populated. + * slots + * This array is either an input or output. If bRemoveSpecificSlots is true, + * then this will contain the list of slots to remove. If it is false, then + * it will be populated by RM with the indexes of the slots that were + * removed. + * bRemoveSpecificSlots + * This input determines which mode the call will run in. If true the caller + * will specify the list of slots they want removed, if any of those slots + * are not on the freelist, the call will fail. If false they only specify + * the number of slots they want removed and RM will pick up to that + * many. If there are not enough slots on the freelist to remove the + * requested amount, RM will return the number it was able to remove. + * hMemory + * Handle to GFX Pool memory + * offset + * Offset of the control structure in GFX Pool memory + * size + * Size of the control structure + */ +#define NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS (0x20801222U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS { + NvU32 numSlots; + NvU32 slots[NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS]; + NvBool bRemoveSpecificSlots; + NvHandle hMemory; + NvU32 offset; + NvU32 size; +} NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS; + + + +#define NV2080_CTRL_CMD_GR_GET_CAPS_V2 (0x20801227U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x27U) + +typedef NV0080_CTRL_GR_GET_CAPS_V2_PARAMS NV2080_CTRL_GR_GET_CAPS_V2_PARAMS; + +#define NV2080_CTRL_CMD_GR_GET_INFO_V2 (0x20801228U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID (0x28U) + +typedef NV0080_CTRL_GR_GET_INFO_V2_PARAMS NV2080_CTRL_GR_GET_INFO_V2_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GR_GET_GPC_MASK + * + * This command returns a mask of enabled GPCs for the associated subdevice. + * + * grRouteInfo[IN] + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + * gpcMask[OUT] + * This parameter returns a mask of enabled GPCs. Each GPC has an ID + * that's equivalent to the corresponding bit position in the mask. + */ +#define NV2080_CTRL_CMD_GR_GET_GPC_MASK (0x2080122aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GPC_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_GPC_MASK_PARAMS_MESSAGE_ID (0x2AU) + +typedef struct NV2080_CTRL_GR_GET_GPC_MASK_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvU32 gpcMask; +} NV2080_CTRL_GR_GET_GPC_MASK_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_TPC_MASK + * + * This command returns a mask of enabled TPCs for a specified GPC. + * + * grRouteInfo[IN] + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + * gpcId[IN] + * This parameter specifies the GPC for which TPC information is + * to be retrieved. If the GPC with this ID is not enabled this command + * will return an tpcMask value of zero. + * + * tpcMask[OUT] + * This parameter returns a mask of enabled TPCs for the specified GPC. + * Each TPC has an ID that's equivalent to the corresponding bit + * position in the mask. + */ +#define NV2080_CTRL_CMD_GR_GET_TPC_MASK (0x2080122bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_TPC_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_TPC_MASK_PARAMS_MESSAGE_ID (0x2BU) + +typedef struct NV2080_CTRL_GR_GET_TPC_MASK_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvU32 gpcId; + NvU32 tpcMask; +} NV2080_CTRL_GR_GET_TPC_MASK_PARAMS; + +#define NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x2080122cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID (0x2CU) + +typedef NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES + * + * This command is used to provide the caller with the alignment and size + * of the context save region for an engine + * + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * engineId + * This parameter is an input parameter specifying the engineId for which + * the alignment/size is requested. + * alignment + * This parameter is an output parameter which will be filled in with the + * minimum alignment requirement. + * size + * This parameter is an output parameter which will be filled in with the + * minimum size of the context save region for the engine. + * bInfoPopulated + * This parameter will be set if alignment and size are already set with + * valid values from a previous call. + */ + +#define NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES (0x2080122dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID (0x2DU) + +typedef struct NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvU32 engineId; + NvU32 alignment; + NvU32 size; + NvBool bInfoPopulated; +} NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER + * + * This command provides an interface to retrieve the speed select values of + * various instruction types. + * + * grRouteInfo[IN] + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + * imla0[OUT] + * The current speed select for IMLA0. + * + * fmla16[OUT] + * The current speed select for FMLA16. + * + * dp[OUT] + * The current speed select for DP. + * + * fmla32[OUT] + * The current speed select for FMLA32. + * + * ffma[OUT] + * The current speed select for FFMA. + * + * imla1[OUT] + * The current speed select for IMLA1. + * + * imla2[OUT] + * The current speed select for IMLA2. + * + * imla3[OUT] + * The current speed select for IMLA3. + * + * imla4[OUT] + * The current speed select for IMLA4. + */ +#define NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER (0x20801230U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_2 (0x1U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_4 (0x2U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_8 (0x3U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_16 (0x4U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_32 (0x5U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_64 (0x6U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_2 (0x1U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_4 (0x2U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_8 (0x3U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_16 (0x4U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_32 (0x5U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_REDUCED_SPEED (0x1U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_2 (0x1U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_4 (0x2U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_8 (0x3U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_16 (0x4U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_32 (0x5U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_2 (0x1U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_4 (0x2U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_8 (0x3U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_16 (0x4U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_32 (0x5U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_2 (0x1U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_4 (0x2U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_8 (0x3U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_16 (0x4U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_32 (0x5U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_64 (0x6U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_2 (0x1U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_4 (0x2U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_8 (0x3U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_16 (0x4U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_32 (0x5U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_64 (0x6U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_2 (0x1U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_4 (0x2U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_8 (0x3U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_16 (0x4U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_32 (0x5U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_64 (0x6U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_2 (0x1U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_4 (0x2U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_8 (0x3U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_16 (0x4U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_32 (0x5U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_64 (0x6U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x30U) + +typedef struct NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvU8 imla0; + NvU8 fmla16; + NvU8 dp; + NvU8 fmla32; + NvU8 ffma; + NvU8 imla1; + NvU8 imla2; + NvU8 imla3; + NvU8 imla4; +} NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS; + +#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_MAX_LIST_SIZE (0xFFU) +#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FMLA16 (0x0U) +#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_DP (0x1U) +#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FMLA32 (0x2U) +#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FFMA (0x3U) +#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA0 (0x4U) +#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA1 (0x5U) +#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA2 (0x6U) +#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA3 (0x7U) +#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA4 (0x8U) +#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FP16 (0x9U) +#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FP32 (0xAU) +#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_DFMA (0xBU) +#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_DMLA (0xCU) + +/* + * NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER_V2 + * + * This command provides an interface to retrieve the speed select values of + * various instruction types. + * + * smIssueRateModifierListSize + * This field specifies the number of entries on the caller's + * smIssueRateModifierList. + * When caller passes smIssueRateModifierListSize = 0, all fuse + * values are returned. + * smIssueRateModifierList + * This field specifies a pointer in the caller's address space + * to the buffer into which the speed select values are to be returned. + */ +#define NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER_V2 (0x2080123cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID" */ + +typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2; + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID (0x3CU) + +typedef struct NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS { + NvU32 smIssueRateModifierListSize; + NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2 smIssueRateModifierList[NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_MAX_LIST_SIZE]; +} NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS; + +#define NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL_MAX_LIST_SIZE (0xFFU) +#define NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL_MASK (0x0U) +#define NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL_CREDIT (0x1U) + +/* + * NV2080_CTRL_CMD_GR_GET_SM_ISSUE_THROTTLE_CTRL + * + * This command provides an interface to retrieve the throttle contol values of + * various instruction types for a GR engine. + * + * smIssueThrottleCtrlListSize + * This field specifies the number of entries on the caller's + * smIssueThrottleCtrlList. + * When caller passes smIssueThrottleCtrlListSize = 0, all fuse + * values are returned. + * smIssueThrottleCtrlList + * This field specifies a pointer in the caller's address space + * to the buffer into which the throttle control values are to be returned. + */ +#define NV2080_CTRL_CMD_GR_GET_SM_ISSUE_THROTTLE_CTRL (0x2080123dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS_MESSAGE_ID" */ + +typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL; + +#define NV2080_CTRL_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS_MESSAGE_ID (0x3DU) + +typedef struct NV2080_CTRL_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS { + NvU32 smIssueThrottleCtrlListSize; + NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL smIssueThrottleCtrlList[NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL_MAX_LIST_SIZE]; +} NV2080_CTRL_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID + * + * *DEPRECATED* Use NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID_V2 instead + * + * This command is used to create a FECS bind-point to an event buffer that + * is filtered by UID. + * + * hEventBuffer[IN] + * The event buffer to bind to + * + * recordSize[IN] + * The size of the FECS record in bytes + * + * levelOfDetail[IN] + * One of NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_: + * FULL: Report all CtxSw events + * SIMPLE: Report ACTIVE_REGION_START and ACTIVE_REGION_END only + * COMPAT: Events that KMD is interested in (for backwards compatibility) + * CUSTOM: Report events in the eventFilter field + * NOTE: RM may override the level-of-detail depending on the caller + * + * eventFilter[IN] + * Bitmask of events to report if levelOfDetail is CUSTOM + * + * bAllUsers[IN] + * Only report FECS CtxSw data for the current user if false, for all users if true + */ + +#define NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID (0x20801231U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD { + NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_FULL = 0, + NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_SIMPLE = 1, + NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_COMPAT = 2, + NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_CUSTOM = 3, +} NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD; + +#define NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS_MESSAGE_ID (0x31U) + +typedef struct NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS { + NvHandle hEventBuffer; + NvU32 recordSize; + NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD levelOfDetail; + NvU32 eventFilter; + NvBool bAllUsers; +} NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK + * + * This command returns a mask of physical GPC Ids for the associated syspipe + * + * physSyspipeId[IN] + * This parameter specifies syspipe for which phys GPC mask is requested + * + * gpcMask[OUT] + * This parameter returns a mask of mapped GPCs to provided syspipe. + * Each GPC-ID has a corresponding bit position in the mask. + */ +#define NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK (0x20801232U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS_MESSAGE_ID (0x32U) + +typedef struct NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS { + NvU32 physSyspipeId; + NvU32 gpcMask; +} NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_PPC_MASK + * + * This command returns a mask of enabled PPCs for a specified GPC. + * + * grRouteInfo[IN] + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + * gpcId[IN] + * This parameter specifies the GPC for which TPC information is + * to be retrieved. If the GPC with this ID is not enabled this command + * will return an ppcMask value of zero. + * + * ppcMask[OUT] + * This parameter returns a mask of enabled PPCs for the specified GPC. + * Each PPC has an ID that's equivalent to the corresponding bit + * position in the mask. + */ +#define NV2080_CTRL_CMD_GR_GET_PPC_MASK (0x20801233U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_PPC_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_PPC_MASK_PARAMS_MESSAGE_ID (0x33U) + +typedef struct NV2080_CTRL_GR_GET_PPC_MASK_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvU32 gpcId; + NvU32 ppcMask; +} NV2080_CTRL_GR_GET_PPC_MASK_PARAMS; + +#define NV2080_CTRL_CMD_GR_GET_NUM_TPCS_FOR_GPC (0x20801234U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS_MESSAGE_ID (0x34U) + +typedef struct NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS { + NvU32 gpcId; + NvU32 numTpcs; +} NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_CTXSW_MODES + * + * This command is used to get context switch modes for the specified + * channel. A value of NV_ERR_NOT_SUPPORTED is returned if the + * target channel does not support context switch mode changes. + * + * hChannel + * This parameter specifies the channel handle of + * the channel that is to have its context switch modes retrieved. + * zcullMode + * See NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE for possible return values + * pmMode + * See NV2080_CTRL_CMD_GR_CTXSW_PM_MODE for possible return values + * smpcMode + * See NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE for possible return values + * cilpPreemptMode + * See NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE for possible return values + * gfxpPreemptMode + * See NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE for possible return values + */ +#define NV2080_CTRL_CMD_GR_GET_CTXSW_MODES (0x20801235U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID (0x35U) + +typedef struct NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS { + NvHandle hChannel; + NvU32 zcullMode; + NvU32 pmMode; + NvU32 smpcMode; + NvU32 cilpPreemptMode; + NvU32 gfxpPreemptMode; +} NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP + * + * Get a list of values used to describe GPC/TPC tile mapping tables. + * + * mapValueCount + * This field specifies the number of actual map entries. This count + * should equal the number of TPCs in the system. + * mapValues + * This field is a pointer to a buffer of NvU08 values representing map + * data. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP (0x20801236U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS_MESSAGE_ID (0x36U) + +typedef NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_ZCULL_MASK + * + * This command returns a mask of enabled ZCULLs for a specified GPC. + * + * gpcId[IN] + * This parameter, physical GPC index, specifies the GPC for which ZCULL + * information is to be retrieved. If the GPC with this ID is not enabled + * this command will return a zcullMask value of zero. + * + * zcullMask[OUT] + * This parameter returns a mask of enabled ZCULLs for the specified GPC. + * Each ZCULL has an ID that's equivalent to the corresponding bit + * position in the mask. + */ + +#define NV2080_CTRL_CMD_GR_GET_ZCULL_MASK (0x20801237U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS_MESSAGE_ID (0x37U) + +typedef struct NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS { + NvU32 gpcId; + NvU32 zcullMask; +} NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID_V2 + * + * This command is used to create a FECS bind-point to an event buffer that + * is filtered by UID. + * + * hEventBuffer[IN] + * The event buffer to bind to + * + * recordSize[IN] + * The size of the FECS record in bytes + * + * levelOfDetail[IN] + * One of NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_: + * FULL: Report all CtxSw events + * SIMPLE: Report ACTIVE_REGION_START and ACTIVE_REGION_END only + * COMPAT: Events that KMD is interested in (for backwards compatibility) + * CUSTOM: Report events in the eventFilter field + * NOTE: RM may override the level-of-detail depending on the caller + * + * eventFilter[IN] + * Bitmask of events to report if levelOfDetail is CUSTOM + * + * bAllUsers[IN] + * Only report FECS CtxSw data for the current user if false, for all users if true + * + * reasonCode [OUT] + * Reason for failure + */ +#define NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID_V2 (0x20801238U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE { + NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NONE = 0, + NV2080_CTRL_GR_FECS_BIND_REASON_CODE_GPU_TOO_OLD = 1, + NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED_GPU = 2, + NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED = 3, + NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_ADMIN = 4, + NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_CAPABILITY = 5, +} NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE; + +#define NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS_MESSAGE_ID (0x38U) + +typedef struct NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS { + NvHandle hEventBuffer; + NvU32 recordSize; + NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD levelOfDetail; + NvU32 eventFilter; + NvBool bAllUsers; + NvU32 reasonCode; +} NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_GFX_GPC_AND_TPC_INFO + * + * This command grabs information on GFX capable GPC's and TPC's for a specifc GR engine + * + * grRouteInfo[IN] + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + * physGfxGpcMask [OUT] + * Physical mask of Gfx capable GPC's + * + * numGfxTpc [OUT] + * Total number of Gfx capable TPC's + */ +#define NV2080_CTRL_CMD_GR_GET_GFX_GPC_AND_TPC_INFO (0x20801239U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS_MESSAGE_ID (0x39U) + +typedef struct NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvU32 physGfxGpcMask; + NvU32 numGfxTpc; +} NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_TPC_RECONFIG_MASK + * + * This command returns the TPC reconfig mask for a specific GPC + * + * gpc[IN] + * The GPC for which the TPC reconfig mask needs to be queried. + * The GPC should be specified as a logical index. + * + * tpcReconfigMask[OUT] + * Mask of reconfigurable TPCs in the specified GPC + * + * grRouteInfo[IN] + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_GET_TPC_RECONFIG_MASK (0x2080123bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID (0x3bU) + +typedef struct NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS { + NvU32 gpc; + NvU32 tpcReconfigMask; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_TEST_CTXSW_ERROR_LOGS + * + * This command provides an interface to test CTXSW print logs from + * the context switch microcode. This is test only interface. + * + * expectedCharCount[IN] + * This parameter specifies the number of characters to retrieve + * and print. + * bUseInterrupt[IN] + * This flag is used to indicate if an interrupt is to be issued prior to + * ctxsw ucode dumping its prints to the buffer. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_GR_TEST_CTXSW_ERROR_LOGS (0x2080123eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_TEST_CTXSW_ERROR_LOGS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_TEST_CTXSW_ERROR_LOGS_PARAMS_MESSAGE_ID (0x3EU) + +typedef struct NV2080_CTRL_GR_TEST_CTXSW_ERROR_LOGS_PARAMS { + NvU32 expectedCharCount; + NvBool bUseInterrupt; +} NV2080_CTRL_GR_TEST_CTXSW_ERROR_LOGS_PARAMS; + +/* _ctrl2080gr_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080grmgr.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080grmgr.h new file mode 100644 index 0000000..8d41d3a --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080grmgr.h @@ -0,0 +1,299 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080grmgr.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX grmgr control commands and parameters */ + +// +// NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO +// +// This control call works as a batched query interface where we +// have multiple different queries that can be passed in +// and RM will return the associated data and status type +// If there is any error in NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS, +// we will immediately fail the call. +// However, if there is an error in the query-specific calls, we will +// log the error and march on. +// +// NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS +// numQueries[in] +// - Specifies the number of valid queries that the caller will be passing in +// +// Possible status values returned are: +// NV_OK +// NV_ERR_INVALID_ARGUMENT +// NV_ERR_INVALID_STATE +// +#define NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO (0x20803801) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GRMGR_INTERFACE_ID << 8) | NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_MESSAGE_ID" */ + +// Max number of queries that can be batched in a single call to NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO +#define NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES 96 + +// +// Preference is to keep max.size of union at 24 bytes (i.e. 6 32-bit members) +// so that the size of entire query struct is maintained at 32 bytes, to ensure +// that overall params struct does not exceed 4kB +// +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_MAX_SIZE 32 +#define NV2080_CTRL_GRMGR_MAX_SMC_IDS 8 + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS + * gpcCount[out] + * - No. of logical/local GPCs which client can use to create the + * logical/local mask respectively + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS { + NvU32 gpcCount; // param[out] - logical/local GPC mask +} NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS + * gpcId[in] + * - Logical/local GPC ID + * chipletGpcMap[out] + * - Returns chiplet GPC ID for legacy case and device monitoring client + * - Returns local GPC ID (== input gpcId) for SMC client + * - Does not support DM attribution case + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS { + NvU32 gpcId; // param[in] - logical/local GPC ID + NvU32 chipletGpcMap; // param[out] - chiplet GPC ID +} NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS + * gpcId[in] + * - Logical/local GPC ID + * tpcMask[out] + * - Returns physical TPC mask for legacy, DM client and SMC cases + * - Does not support DM attribution case + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS { + NvU32 gpcId; // param[in] - logical/local GPC ID + NvU32 tpcMask; // param[out] - physical TPC mask +} NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS + * gpcId[in] + * - Logical/local GPC ID + * ppcMask[out] + * - Returns physical PPC mask for legacy, DM client and SMC cases + * - Does not support DM attribution case + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS { + NvU32 gpcId; // param[in] - logical/local GPC ID + NvU32 ppcMask; // param[out] - physical PPC mask +} NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS; + +/*! + * !!! DEPRECATED - This query will return NV_ERR_NOT_SUPPORTED since deleting + * it would break driver compatibility !!! + * + * NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS + * swizzId[in] + * - Swizz ID of partition + * - A DM client with an invalid swizz ID, will fail this call + * - This parameter is not compulsory for an SMC client; the subscription + * itself will do the necessary validation. + * gpcId[in] + * - Logical/local GPC ID + * chipletGpcMap[out] + * - Returns chiplet GPC ID for legacy case and device monitoring client + * - Returns local GPC ID (== input gpcId) for SMC client + * - Does not support non-attribution case for DM client + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS { + NvU32 swizzId; // param[in] - swizz ID of partition + NvU32 gpcId; // param[in] - logical/local GPC ID + NvU32 chipletGpcMap; // param[out] - chiplet GPC ID +} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS + * gpcId[in] + * - Logical/local GPC ID + * ropMask[out] + * - Returns physical ROP mask for legacy, DM client + * - Returns logical ROP mask for SMC + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS { + NvU32 gpcId; // param[in] - logical/local GPC ID + NvU32 ropMask; // param[out] - physical ROP mask +} NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS + * chipletSyspipeMask [out] + * - Mask of chiplet SMC-IDs for DM client attribution case + * - Mask of local SMC-IDs for SMC client + * - Legacy case returns 1 GR + * - Does not support attribution case for DM client + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS { + NvU32 chipletSyspipeMask; // param[out] - Mask of chiplet SMC IDs +} NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS + * swizzId[in] + * - Swizz ID of partition + * - A DM client with an invalid swizz ID, will fail this call + * physSyspipeId[GRMGR_MAX_SMC_IDS] [out] + * - Physical SMC-IDs mapped to partition local idx for DM client attribution case + * - Does not support non-attribution case for DM client, SMC clients, legacy case + * physSyspipeIdCount[out] + * - Valid count of physSmcIds which has been populated in above array. + * - Failure case will return 0 + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS { + NvU16 swizzId; // param[in] - swizz ID of partition + NvU16 physSyspipeIdCount; // param[out] - Count of physSmcIds in above array + NvU8 physSyspipeId[NV2080_CTRL_GRMGR_MAX_SMC_IDS]; // param[out] - physical/local SMC IDs +} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS + * swizzId[in] + * - Swizz ID of partition + * - Mandatory parameter + * - A DM client with an invalid swizz ID, will fail this call + * grIdx[in] + * - Local grIdx for a partition + * - Mandatory parameter + * gpcEnMask[out] + * - Logical enabled GPC mask associated with requested grIdx of the partition i.e swizzid->engineId->gpcMask + * - These Ids should be used as input further + * - Does not support non-attribution case for DM client, SMC clients, legacy case + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS { + NvU32 swizzId; // param[in] - swizz ID of partition + NvU32 grIdx; // param[in] - partition local GR ID + NvU32 gpcEnMask; // param[out] - logical enabled GPC mask +} NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID + * syspipeId[out] + * - Partition-local GR idx for client subscribed to exec partition + * - Does not support legacy case, DM client, or SMC client subscribed only to partition + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS { + NvU32 syspipeId; // param[out] - partition-local Gr idx +} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GRAPHICS_SYSPIPE_MASK_PARAMS + * chipletSyspipeMask [out] + * - Mask of chiplet GFX capable SMC-IDs for DM client attribution case + * - Mask of local GFX capable SMC-IDs for SMC client + * - Legacy case returns GR0 if GFX capable, else 0 + * - Does not support attribution case for DM client + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GRAPHICS_SYSPIPE_MASK_PARAMS { + NvU32 chipletSyspipeMask; // param[out] - Mask of chiplet SMC IDs +} NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GRAPHICS_SYSPIPE_MASK_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_GFX_CAPABLE_GPC_MASK_PARAMS + * swizzId[in] + * - Swizz ID of partition + * - Mandatory parameter + * - A DM client with an invalid swizz ID, will fail this call + * grIdx[in] + * - Local grIdx for a partition + * - Mandatory parameter + * gpcEnMask[out] + * - Logical enabled GPC mask associated with requested grIdx of the partition i.e swizzid->engineId->gpcMask + * - These Ids should be used as input further + * - Does not support non-attribution case for DM client, SMC clients, legacy case + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_GFX_CAPABLE_GPC_MASK_PARAMS { + NvU32 swizzId; // param[in] - swizz ID of partition + NvU32 grIdx; // param[in] - partition local GR ID + NvU32 gpcEnMask; // param[out] - logical enabled GPC mask +} NV2080_CTRL_GRMGR_GR_FS_INFO_GFX_CAPABLE_GPC_MASK_PARAMS; + +/*! + * queryType[in] + * - Use queryType defines to specify what information is being requested + * status[out] + * - Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS { + NvU16 queryType; + NvU8 reserved[2]; // To keep the struct aligned for now and available for future use (if needed) + NvU32 status; + union { + NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS gpcCountData; + NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS chipletGpcMapData; + NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS tpcMaskData; + NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS ppcMaskData; + NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS partitionGpcMapData; + NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS syspipeMaskData; + NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS partitionChipletSyspipeData; + NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS dmGpcMaskData; + NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS partitionSyspipeIdData; + NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS ropMaskData; + NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GRAPHICS_SYSPIPE_MASK_PARAMS gfxSyspipeMaskData; + NV2080_CTRL_GRMGR_GR_FS_INFO_GFX_CAPABLE_GPC_MASK_PARAMS gfxGpcMaskData; + } queryData; +} NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS; + +#define NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS { + NvU16 numQueries; + NvU8 reserved[6]; // To keep the struct aligned for now and available for future use (if needed) + NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS queries[NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES]; +} NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS; + +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_INVALID 0 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GPC_COUNT 1 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GPC_MAP 2 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_TPC_MASK 3 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PPC_MASK 4 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_GPC_MAP 5 /* deprecated */ +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_SYSPIPE_MASK 6 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_SYSPIPE_IDS 7 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PROFILER_MON_GPC_MASK 8 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_SYSPIPE_ID 9 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_ROP_MASK 10 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GRAPHICS_SYSPIPE_MASK 11 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GFX_CAPABLE_GPC_MASK 12 + +/* _ctrl2080grmgr_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gsp.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gsp.h new file mode 100644 index 0000000..404c988 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080gsp.h @@ -0,0 +1,273 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080gsp.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX GSP control commands and parameters */ + +/* + * NV2080_CTRL_CMD_GSP_GET_FEATURES + * + * This command is used to determine which GSP features are + * supported on this GPU. + * + * gspFeatures + * Bit mask that specifies GSP features supported. + * bValid + * If this field is set to NV_TRUE, then above bit mask is + * considered valid. Otherwise, bit mask should be ignored + * as invalid. bValid will be set to NV_TRUE when RM is a + * GSP client with GPU support offloaded to GSP firmware. + * bDefaultGspRmGpu + * If this field is set to NV_TRUE, it indicates that the + * underlying GPU has GSP-RM enabled by default. If set to NV_FALSE, + * it indicates that the GPU has GSP-RM disabled by default. + * firmwareVersion + * This field contains the buffer into which the firmware build version + * should be returned, if GPU is offloaded. Otherwise, the buffer + * will remain untouched. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_GSP_GET_FEATURES (0x20803601) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_GSP_GET_FEATURES_PARAMS_MESSAGE_ID" */ + +#define NV2080_GSP_MAX_BUILD_VERSION_LENGTH (0x0000040) + +#define NV2080_CTRL_GSP_GET_FEATURES_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_GSP_GET_FEATURES_PARAMS { + NvU32 gspFeatures; + NvBool bValid; + NvBool bDefaultGspRmGpu; + NvU8 firmwareVersion[NV2080_GSP_MAX_BUILD_VERSION_LENGTH]; +} NV2080_CTRL_GSP_GET_FEATURES_PARAMS; + +/* Valid feature values */ +#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED 0:0 +#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE (0x00000000) +#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE (0x00000001) +#define NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED 1:1 +#define NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_FALSE (0x00000000) +#define NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_TRUE (0x00000001) + +/* + * NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS + * + * This command reports the current GSP-RM heap usage statistics. + * + * gfid + * The gfid that's under query: When gfid = 0, it will report the stats of PF. + * Otherwise, it will report stats for RM task's memory consumption associated + * with a given gfid. + * managedSize + * The total size in bytes of the underlying heap. Note that not all memory + * will be allocatable, due to fragmentation and memory allocator/tracking + * overhead. + * current + * An NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT record corresponding to + * GSP-RM heap usage at the time this command is called. + * peak + * An NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT record corresponding to + * the "high water mark" of heap usage since GSP-RM was started. + */ +#define NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS (0x20803602) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT + * + * This record represents a set of heap measurements at a given point in time. + * + * allocatedSize + * Allocated memory size, in bytes. This value does not include overhead used + * by the underlying allocator for padding/metadata, but does include the + * NvPort memory tracking overhead. + * usableSize + * Allocated memory size excluding all metadata, in bytes. This value does + * not include the NvPort memory tracking overhead. + * memTrackOverhead + * Allocated memory size used for NvPort memory tracking. + */ +typedef struct NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT { + NV_DECLARE_ALIGNED(NvU64 allocatedSize, 8); + NV_DECLARE_ALIGNED(NvU64 usableSize, 8); + NV_DECLARE_ALIGNED(NvU64 memTrackOverhead, 8); + NvU32 allocationCount; +} NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT; + +#define NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS { + NvU32 gfid; + NV_DECLARE_ALIGNED(NvU64 managedSize, 8); + NV_DECLARE_ALIGNED(NvU64 largestFreeChunkSize, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT current, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT peak, 8); +} NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS; + +/* + * NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS + * + * This command reports the current partition's VGPU-GSP plugin's heap usage statistics. + * + * managedSize + * The total size in bytes of the underlying heap. Note that not all memory + * will be allocatable, due to fragmentation and memory allocator/tracking + * overhead. + * allocatedSize + * Allocated memory size, in bytes. This value does not include overhead used + * by the underlying allocator for padding/metadata. + * allocationCount + * The number of active allocations. This count reflects the current number of + * memory blocks that have been allocated but not yet freed. + * peakAllocatedSize + * The highest recorded allocated memory size, in bytes. This value represents the + * maximum amount of memory that has been allocated at any point in time. When a new + * highest allocated size is recorded, the peakAllocatedSize is updated. + * peakAllocationCount + * The number of active allocations corresponding to the highest recorded peakAllocatedSize. + */ + +#define NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS (0x20803603) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 allocatedSize, 8); + NV_DECLARE_ALIGNED(NvU64 peakAllocatedSize, 8); + NV_DECLARE_ALIGNED(NvU64 managedSize, 8); + NvU32 allocationCount; + NvU32 peakAllocationCount; + NV_DECLARE_ALIGNED(NvU64 largestFreeChunkSize, 8); +} NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS; + +#define NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS (0x20803604) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_GSP_LIBOS_POOL_COUNT_MAX 64 + +typedef struct NV2080_CTRL_GSP_LIBOS_POOL_STATS { + NvU32 allocations; + NvU32 peakAllocations; + NV_DECLARE_ALIGNED(NvU64 objectSize, 8); +} NV2080_CTRL_GSP_LIBOS_POOL_STATS; + + +#define NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GSP_LIBOS_POOL_STATS poolStats[NV2080_CTRL_GSP_LIBOS_POOL_COUNT_MAX], 8); + NV_DECLARE_ALIGNED(NvU64 totalHeapSize, 8); + NvU8 poolCount; +} NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS; + +/* + * NV2080_CTRL_CMD_GSP_GDMA_FUZZ_TEST + * + * This control spams GDMA requests of random size, location, and source memory. + * + * iters + * Number of DMA requests to send. Large values should be paired with RmDefaultTimeout + * increase in order to avoid XID 119. + * + * pSysmemPA + * Internal param + * + */ +#define NV2080_CTRL_CMD_GSP_GDMA_FUZZ_TEST (0x20803605) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GSP_GDMA_FUZZ_TEST_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GSP_GDMA_FUZZ_TEST_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV2080_CTRL_CMD_GSP_GDMA_FUZZ_TEST_PARAMS { + NV_DECLARE_ALIGNED(NvU64 iters, 8); + NV_DECLARE_ALIGNED(NvU64 pSysmemPA, 8); +} NV2080_CTRL_CMD_GSP_GDMA_FUZZ_TEST_PARAMS; + +#define NV2080_CTRL_CMD_GSP_CORE_TEST (0x20803606) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GSP_CORE_TEST_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_GSP_CORE_TEST_OP { + NV2080_CTRL_GSP_CORE_TEST_OP_WRITE_LATENCY = 0, + NV2080_CTRL_GSP_CORE_TEST_OP_READ_LATENCY = 1, + NV2080_CTRL_GSP_CORE_TEST_OP_WRITE_BLOCK = 2, + NV2080_CTRL_GSP_CORE_TEST_OP_READ_BLOCK = 3, + NV2080_CTRL_GSP_CORE_TEST_SYSMEM_TO_FB_OP_COPY_NAIVE = 4, + NV2080_CTRL_GSP_CORE_TEST_FB_TO_FB_OP_COPY_NAIVE = 5, + NV2080_CTRL_GSP_CORE_TEST_DMEM_TO_FB_OP_PORT_MEM_COPY = 6, + NV2080_CTRL_GSP_CORE_TEST_FB_TO_DMEM_OP_PORT_MEM_COPY = 7, + NV2080_CTRL_GSP_CORE_TEST_FB_TO_FB_OP_PORT_MEM_COPY = 8, + NV2080_CTRL_GSP_CORE_TEST_DMEM_TO_FB_OP_DMA = 9, + NV2080_CTRL_GSP_CORE_TEST_FB_TO_DMEM_OP_DMA = 10, + NV2080_CTRL_GSP_CORE_TEST_FB_TO_FB_OP_DMA = 11, + NV2080_CTRL_GSP_CORE_TEST_L1D_INVAL_TIME = 12, +} NV2080_CTRL_GSP_CORE_TEST_OP; + +typedef enum NV2080_CTRL_GSP_CORE_TEST_MEM { + NV2080_CTRL_GSP_CORE_TEST_MEM_DMEM = 0, + NV2080_CTRL_GSP_CORE_TEST_MEM_FB = 1, + NV2080_CTRL_GSP_CORE_TEST_MEM_SYSMEM = 2, +} NV2080_CTRL_GSP_CORE_TEST_MEM; + +#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_INVAL_L1_LIBOS 0:0 +#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_INVAL_L1_LIBOS_YES (0x00000001) +#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_INVAL_L1_LIBOS_NO (0x00000000) + +#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_EVICT_L2 1:1 +#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_EVICT_L2_YES (0x00000001) +#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_EVICT_L2_NO (0x00000000) + +#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_INVAL_L2 2:2 +#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_INVAL_L2_YES (0x00000001) +#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_INVAL_L2_NO (0x00000000) + +#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_UNCACHED 3:3 +#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_UNCACHED_YES (0x00000001) +#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_UNCACHED_NO (0x00000000) + +#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_FENCE 4:4 +#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_FENCE_YES (0x00000001) +#define NV2080_CTRL_GSP_CORE_TEST_FLAGS_FENCE_NO (0x00000000) + +#define NV2080_CTRL_GSP_CORE_TEST_SIZE_MAX (0x400000) // 4MiB +#define NV2080_CTRL_GSP_CORE_TEST_ITERS_MAX (10000) + +#define NV2080_CTRL_CMD_GSP_CORE_TEST_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_CMD_GSP_CORE_TEST_PARAMS { + NV2080_CTRL_GSP_CORE_TEST_OP op; + NV2080_CTRL_GSP_CORE_TEST_MEM mem; + NV_DECLARE_ALIGNED(NvU64 flags, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NV_DECLARE_ALIGNED(NvU64 iters, 8); + NV_DECLARE_ALIGNED(NvU64 timeNs, 8); + NV_DECLARE_ALIGNED(NvU64 cycles, 8); +} NV2080_CTRL_CMD_GSP_CORE_TEST_PARAMS; + +// _ctrl2080gsp_h_ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080hshub.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080hshub.h new file mode 100644 index 0000000..0160705 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080hshub.h @@ -0,0 +1,73 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080hshub.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* + * NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK + * + * This command get active HSHUB masks. + * + * hshubNcisocMask + * NCISOC enabled active HSHUBs + * hshubNvlMask + * NVLINK capable active HSHUBs. + */ + +#define NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS { + NvU32 hshubNcisocMask; + NvU32 hshubNvlMask; +} NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS; + +#define NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK (0x20804101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_HSHUB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE + * + * This command sets EC throttle mode registers + * + * ecMode + * EC Mode 0-7 to write to mode register + * status + * return status + */ +#define NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS { + NvU32 ecMode; + NvU32 status; +} NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS; + +#define NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE (0x20804102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_HSHUB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS_MESSAGE_ID" */ +/* _ctrl2080hshub_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080i2c.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080i2c.h new file mode 100644 index 0000000..99e78c2 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080i2c.h @@ -0,0 +1,372 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080i2c.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX i2c-related control commands and parameters */ + +/* + * NV2080_CTRL_I2C_VERSION + * + * NV2080_CTRL_I2C_VERSION_0_0: + * This return state specifies that support is only available + * for single subAddr reads. + * + */ +#define NV2080_CTRL_I2C_VERSION_0 0x00 + +/* maximum number of i2c entries support */ +#define NV2080_CTRL_I2C_MAX_ENTRIES 256 +#define NV2080_CTRL_I2C_MAX_REG_LEN 8 +#define NV2080_CTRL_I2C_MAX_ADDR_ENTRIES 20 + +/* + * NV2080_CTRL_I2C_FLAGS + * + * NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC: + * This option specified that non-compliant i2c for SI1930UC is required + * + * NV2080_CTRL_I2C_FLAGS_PRIVILEGE + * This option specified that the i2c access is privileged + * + * NV2080_CTRL_I2C_FLAGS_PX3540 + * This option specified that the i2c device -PX3540/3544- is accessed + */ +#define NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC (0x00000001) +#define NV2080_CTRL_I2C_FLAGS_PRIVILEGE (0x00000002) +#define NV2080_CTRL_I2C_FLAGS_DATA_ENCRYPTED (0x00000004) +#define NV2080_CTRL_I2C_FLAGS_PX3540 (0x00000010) +#define NV2080_CTRL_I2C_FLAGS_ADDR_AUTO_INC_NOT_SUPPORTED (0x00000008) + +/* + * NV2080_CTRL_CMD_I2C_READ_BUFFER + * + * This command allocates video memory for a particular subset of microcode. + * + * version + * This field is returned to the client and indicates the current + * supported I2C controls available. + * + * port + * This field must be specified by the client to indicate which port/bus + * in which i2c access is desired. + * + * flags + * This field is specified by the client to request additional options + * as provided by NV2080_CTRL_I2C_FLAGS. + * + * inputCount + * This field specifies the total # of elements contained in inputBuffer + * + * inputBuffer + * This should contain the chipaddr as the first element, followed by + * the each subAddress in which to access the first element of data + * Eg. ... + * In general, client will only have 2 elements + * + * outputCount + * This field specifies how many registers from the start register index. + * The maximum values allow are NV2080_CTRL_I2C_MAX_ENTRIES. + * + * outputBuffer + * This buffer is returned to the client with the data read from + * the start register index. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_STATE_IN_USE + * NV_ERR_INVALID_STATE + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV2080_CTRL_I2C_READ_BUFFER_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_I2C_READ_BUFFER_PARAMS { + NvU32 version; + NvU32 port; + NvU32 flags; + NvU32 inputCount; + // C form: NvU8 inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES]; + NvU8 inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES]; + NvU32 outputCount; + // C form: NvU8 outputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES]; + NvU8 outputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES]; +} NV2080_CTRL_I2C_READ_BUFFER_PARAMS; + +#define NV2080_CTRL_CMD_I2C_READ_BUFFER (0x20800601) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_READ_BUFFER_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_I2C_WRITE_BUFFER + * + * This command allocates video memory for a particular subset of microcode. + * + * version + * This field is returned to the client and indicates the current + * supported I2C controls available. + * + * port + * This field must be specified by the client to indicate which port/bus + * in which i2c access is desired. + * + * flags + * This field is specified by the client to request additional options. + * NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC: + * - Specifies that non-compliant i2c access for SI1930UC is required + * + * inputCount + * This field specifies the total # of elements contained in inputBuffer + * + * inputBuffer + * This should contain the chipaddr as the first element, followed by + * the each subAddress in which to access the first element of data, + * and finally the data to be programmed. + * Eg. ... ... + * In general, client will have 2 elements + data to be programmed. + * ... + * + * encrClientID + * This field is specified by client, which is used to uniquely access + * the client's encryption context + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_STATE_IN_USE + * NV_ERR_INVALID_STATE + * + */ + +#define NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS { + NvU32 version; + NvU32 port; + NvU32 flags; + NvU32 inputCount; + // C form: NvU8 inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES]; + NvU8 inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES]; + NvU32 encrClientID; +} NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS; + +#define NV2080_CTRL_CMD_I2C_WRITE_BUFFER (0x20800602) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS_MESSAGE_ID" */ + + +/* + * NV2080_CTRL_CMD_I2C_READ_REG + * + * This command allocates video memory for a particular subset of microcode. + * + * version + * This field is returned to the client and indicates the current + * supported I2C controls available. + * + * port + * This field must be specified by the client to indicate which port/bus + * in which i2c access is desired. + * + * flags + * This field is specified by the client to request additional options. + * NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC: + * - Specifies that non-compliant i2c access for SI1930UC is required + * addr + * This field is specified by the client to target address. + * reg + * This field is specified by the client to target register address. + * + * bufsize + * This field specifies the total bytes # of register size + * + * buffer + * when used for read, it used as buffer that store returned register content + * when used for write, It include data that will be written. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_STATE_IN_USE + * NV_ERR_INVALID_STATE + * + */ +typedef struct NV2080_CTRL_I2C_RW_REG_PARAMS { + NvU32 version; + NvU32 port; + NvU32 flags; + NvU32 addr; + NvU8 reg; + NvU8 bufsize; + // C form: NvU8 buffer[NV2080_CTRL_I2C_MAX_ENTRIES - 1]; + NvU8 buffer[(NV2080_CTRL_I2C_MAX_ENTRIES - 1)]; +} NV2080_CTRL_I2C_RW_REG_PARAMS; + +#define NV2080_CTRL_CMD_I2C_READ_REG (0x20800603) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_READ_REG_PARAMS_MESSAGE_ID" */ + +// provide NV2080_CTRL_I2C_READ_REG_PARAMS as the historical name +#define NV2080_CTRL_I2C_READ_REG_PARAMS_MESSAGE_ID (0x3U) + +typedef NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_READ_REG_PARAMS; + +#define NV2080_CTRL_CMD_I2C_WRITE_REG (0x20800604) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_WRITE_REG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_I2C_WRITE_REG_PARAMS_MESSAGE_ID (0x4U) + +typedef NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_WRITE_REG_PARAMS; + +/* + * NV006F_CTRL_CMD_SYSTEM_I2C_ACCESS + * + * This command allows Clients to read and write data using the I2C ports + * + * token [IN] + * This used in i2cAcquirePort + * + * cmd [IN] + * The I2CAccess command + * + * port [IN] + * The port ID of the concerned display + * + * flags [IN] + * The I2CAccess Flags such ack,start,stop + * + * data [OUT/IN] + * Data that needs to be pass or read out + * + * dataBuffSize [IN] + * Size of the data buffer. + * + * speed [IN] + * Speed of transaction. + * + * status [OUT] + * The I2CAccess Status returned + * + * encrClientID [IN] + * This field is specified by client, which is used to uniquely access + * the client's encryption context + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_I2C_ACCESS (0x20800610) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV2080_CTRL_I2C_ACCESS_PARAMS { + NvU32 token; + NvU32 cmd; + NvU32 port; + NvU32 flags; + NV_DECLARE_ALIGNED(NvP64 data, 8); + NvU32 status; + NvU32 dataBuffSize; + NvU32 speed; + NvU32 encrClientID; +} NV2080_CTRL_I2C_ACCESS_PARAMS; + +// commands +#define NV2080_CTRL_I2C_ACCESS_CMD_ACQUIRE 0x1 +#define NV2080_CTRL_I2C_ACCESS_CMD_RELEASE 0x2 +#define NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BYTE 0x3 +#define NV2080_CTRL_I2C_ACCESS_CMD_READ_BYTE 0x4 +#define NV2080_CTRL_I2C_ACCESS_CMD_NULL 0x5 +#define NV2080_CTRL_I2C_ACCESS_CMD_RESET 0x6 +#define NV2080_CTRL_I2C_ACCESS_CMD_TEST_PORT 0x11 +#define NV2080_CTRL_I2C_ACCESS_CMD_SET_FAST_MODE 0x12 +#define NV2080_CTRL_I2C_ACCESS_CMD_SET_NORMAL_MODE 0x13 +#define NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BUFFER 0x14 +#define NV2080_CTRL_I2C_ACCESS_CMD_READ_BUFFER 0x15 +#define NV2080_CTRL_I2C_ACCESS_CMD_START 0x17 +#define NV2080_CTRL_I2C_ACCESS_CMD_STOP 0x18 +#define NV2080_CTRL_I2C_ACCESS_CMD_SET_SLOW_MODE 0x20 + +// flags +#define NV2080_CTRL_I2C_ACCESS_FLAG_START 0x1 +#define NV2080_CTRL_I2C_ACCESS_FLAG_STOP 0x2 +#define NV2080_CTRL_I2C_ACCESS_FLAG_ACK 0x4 +#define NV2080_CTRL_I2C_ACCESS_FLAG_RAB 0x8 +#define NV2080_CTRL_I2C_ACCESS_FLAG_ADDR_10BITS 0x10 +#define NV2080_CTRL_I2C_ACCESS_FLAG_PRIVILEGE 0x20 +#define NV2080_CTRL_I2C_ACCESS_FLAG_DATA_ENCRYPTED 0x40 +#define NV2080_CTRL_I2C_ACCESS_FLAG_RESTART 0x80 +#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33_33PCT 0x100 +#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33PCT 0x200 +#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_10PCT 0x400 +#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3_33PCT 0x800 +#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3PCT 0x1000 + +// port +#define NV2080_CTRL_I2C_ACCESS_PORT_DYNAMIC 0x0 +#define NV2080_CTRL_I2C_ACCESS_PORT_PRIMARY 0x1 +#define NV2080_CTRL_I2C_ACCESS_PORT_SECONDARY 0x2 +#define NV2080_CTRL_I2C_ACCESS_PORT_TERTIARY 0x3 +#define NV2080_CTRL_I2C_ACCESS_PORT_QUARTIARY 0x4 + +// Alternate numeric port designators +#define NV2080_CTRL_I2C_ACCESS_PORT_1 0x1 +#define NV2080_CTRL_I2C_ACCESS_PORT_2 0x2 +#define NV2080_CTRL_I2C_ACCESS_PORT_3 0x3 +#define NV2080_CTRL_I2C_ACCESS_PORT_4 0x4 +#define NV2080_CTRL_I2C_ACCESS_PORT_5 0x5 +#define NV2080_CTRL_I2C_ACCESS_PORT_6 0x6 +#define NV2080_CTRL_I2C_ACCESS_PORT_7 0x7 +#define NV2080_CTRL_I2C_ACCESS_PORT_8 0x8 +#define NV2080_CTRL_I2C_ACCESS_PORT_9 0x9 +#define NV2080_CTRL_I2C_ACCESS_PORT_10 0x10 + +// Total ports count +#define NV2080_CTRL_I2C_ACCESS_NUM_PORTS NV2080_CTRL_I2C_ACCESS_PORT_10 + +// status +#define NV2080_CTRL_I2C_ACCESS_STATUS_SUCCESS 0x0 +#define NV2080_CTRL_I2C_ACCESS_STATUS_ERROR 0x1 +#define NV2080_CTRL_I2C_ACCESS_STATUS_PROTOCOL_ERROR 0x2 +#define NV2080_CTRL_I2C_ACCESS_STATUS_DEVICE_BUSY 0x3 +#define NV2080_CTRL_I2C_ACCESS_STATUS_NACK_AFTER_SEND 0x4 +#define NV2080_CTRL_I2C_ACCESS_STATUS_DP2TMDS_DONGLE_MISSING 0x5 + +#define NV2080_CTRL_CMD_I2C_ENABLE_MONITOR_3D_MODE (0x20800620) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS { + NvU32 head; + NvU32 authType; + NvU32 status; +} NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS; + +/* _ctrl2080i2c_h_ */ + + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080illum.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080illum.h new file mode 100644 index 0000000..ee2ada8 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080illum.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080illum.finn +// + + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080internal.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080internal.h new file mode 100644 index 0000000..da90d5d --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080internal.h @@ -0,0 +1,5589 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080internal.finn +// + +#include "nvimpshared.h" +#include "cc_drv.h" +#include "ctrl/ctrl2080/ctrl2080base.h" + +#include "ctrl/ctrl2080/ctrl2080gpu.h" +#include "ctrl/ctrl2080/ctrl2080gr.h" /* Some controls derivative of 2080gr */ +#include "ctrl/ctrl0080/ctrl0080nvenc.h" /* NV0080_CTRL_NVENC_CAPS_TBL_SIZE */ +#include "ctrl/ctrl0080/ctrl0080nvdec.h" /* NV0080_CTRL_NVDEC_CAPS_TBL_SIZE */ +#include "ctrl/ctrl2080/ctrl2080fifo.h" /* NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO */ +#include "ctrl/ctrl2080/ctrl2080mc.h" /* NV2080_INTR_* */ +#include "ctrl/ctrl0073/ctrl0073system.h" /* NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS */ +#include "ctrl/ctrl0000/ctrl0000system.h" +#include "ctrl/ctrl2080/ctrl2080nvlink_common.h" /* NV2080_CTRL_NVLINK_LINK_MASK */ +#include "ctrl/ctrl2080/ctrl2080nvlink.h" /* NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS */ +#include "ctrl/ctrl90f1.h" +#include "ctrl/ctrl30f1.h" +#include "nvcfg_sdk.h" + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO + * + * This command obtains information from physical RM for use by CPU-RM. + * + * feHwSysCap + * Display IP v03_00 and later. + * Contents of capability register. + * + * windowPresentMask + * Display IP v03_00 and later. + * Mask for the present WINDOWs actually on the current chip. + * numHeads + * Display IP v02_01 and later. + * Provides the number of heads HW support. + */ + +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO (0x20800a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS { + NvU32 feHwSysCap; + NvU32 windowPresentMask; + NvU32 numHeads; + NvU32 i2cPort; + NvU32 internalDispActiveMask; + NvU32 embeddedDisplayPortMask; + NvBool bExternalMuxSupported; + NvBool bInternalMuxSupported; + NvU32 numDispChannels; +} NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS; + + + +// +// MemorySystem settings that are static after GPU state init/load is finished. +// +// Fields are shared between the VGPU guest/GSP Client as well as the VGPU +// host/GSP-RM. +// +#define NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID (0x1CU) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS { + /*! Determines if RM should use 1 to 1 Comptagline allocation policy */ + NvBool bOneToOneComptagLineAllocation; + + /*! Determines if RM should use 1 to 4 Comptagline allocation policy */ + NvBool bUseOneToFourComptagLineAllocation; + + /*! Determines if RM should use raw Comptagline allocation policy */ + NvBool bUseRawModeComptaglineAllocation; + + /*! Has COMPBIT_BACKING_SIZE been overridden to zero (i.e. disabled)? */ + NvBool bDisableCompbitBacking; + + /*! Determine if we need to disable post L2 compression */ + NvBool bDisablePostL2Compression; + + /*! Is ECC DRAM feature supported? */ + NvBool bEnabledEccFBPA; + + NvBool bL2PreFill; + + /*! L2 cache size */ + NV_DECLARE_ALIGNED(NvU64 l2CacheSize, 8); + + /*! Indicate whether fpba is present or not */ + NvBool bFbpaPresent; + + /*! Size covered by one comptag */ + NvU32 comprPageSize; + + /*! log32(comprPageSize) */ + NvU32 comprPageShift; + + /*! RAM type */ + NvU32 ramType; + + /*! LTC count */ + NvU32 ltcCount; + + /*! LTS per LTC count */ + NvU32 ltsPerLtcCount; +} NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS; + +/*! + * Retrieve Memory System Static data. + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_STATIC_CONFIG (0x20800a1c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_REGISTER_UVM_ACCESS_CNTR_BUFFER + * + * This command sends access counter buffer pages allocated by CPU-RM + * to be setup and enabled in physical RM. + * + * accessCounterIndex + * Index of access counter buffer to register. + * + * bufferSize + * Size of the access counter buffer to register. + * + * bufferPteArray + * Pages of access counter buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER (0x20800a1d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES 64 +#define NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID (0x1DU) + +typedef struct NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS { + NvU32 accessCounterIndex; + NvU32 bufferSize; + NV_DECLARE_ALIGNED(NvU64 bufferPteArray[NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES], 8); +} NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER + * + * This command requests physical RM to disable the access counter buffer. + * + * accessCounterIndex + * Index of access counter buffer to unregister. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER (0x20800a1e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID (0x1EU) + +typedef struct NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS { + NvU32 accessCounterIndex; +} NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS; + +#define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES 8 + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_CAPS_V2 + */ + + + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CAPS { + NvU8 capsTbl[NV0080_CTRL_GR_CAPS_TBL_SIZE]; +} NV2080_CTRL_INTERNAL_STATIC_GR_CAPS; + +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_CAPS engineCaps[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS (0x20800a1f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID (0x1FU) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER + * @ref NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS + */ + + + +#define NV2080_CTRL_INTERNAL_GR_MAX_SM 512 + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER { + struct { + NvU16 gpcId; + NvU16 localTpcId; + NvU16 localSmId; + NvU16 globalTpcId; + NvU16 virtualGpcId; + NvU16 migratableTpcId; + NvU16 ugpuId; + NvU16 physicalCpcId; + NvU16 virtualTpcId; + } globalSmId[NV2080_CTRL_INTERNAL_GR_MAX_SM]; + + NvU16 numSm; + NvU16 numTpc; +} NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER; + +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x23U) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER globalSmOrder[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER (0x20800a22) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x22U) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS; + +/*! + * NVDEC Static data. + */ + +#define NV2080_CTRL_CMD_INTERNAL_MAX_NVDECS 8 +#define NV2080_CTRL_CMD_INTERNAL_MAX_BSPS NV2080_CTRL_CMD_INTERNAL_MAX_NVDECS + +typedef struct NV2080_CTRL_INTERNAL_NVDEC_CAPS { + NvU8 capsTbl[NV0080_CTRL_NVDEC_CAPS_TBL_SIZE]; +} NV2080_CTRL_INTERNAL_NVDEC_CAPS; +#define NV2080_CTRL_INTERNAL_BSP_CAPS NV2080_CTRL_INTERNAL_NVDEC_CAPS + +typedef struct NV2080_CTRL_INTERNAL_NVDEC_GET_CAPS_PARAMS { + NV2080_CTRL_INTERNAL_NVDEC_CAPS caps[NV2080_CTRL_CMD_INTERNAL_MAX_NVDECS]; + NvBool valid[NV2080_CTRL_CMD_INTERNAL_MAX_NVDECS]; +} NV2080_CTRL_INTERNAL_NVDEC_GET_CAPS_PARAMS; +#define NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS NV2080_CTRL_INTERNAL_NVDEC_GET_CAPS_PARAMS + +/*! + * NVENC Static data. + */ + +#define NV2080_CTRL_CMD_INTERNAL_MAX_NVENCS 8 +#define NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS NV2080_CTRL_CMD_INTERNAL_MAX_NVENCS + +typedef struct NV2080_CTRL_INTERNAL_NVENC_CAPS { + NvU8 capsTbl[NV0080_CTRL_NVENC_CAPS_TBL_SIZE]; +} NV2080_CTRL_INTERNAL_NVENC_CAPS; +#define NV2080_CTRL_INTERNAL_MSENC_CAPS NV2080_CTRL_INTERNAL_NVENC_CAPS + +typedef struct NV2080_CTRL_INTERNAL_NVENC_GET_CAPS_PARAMS { + NV2080_CTRL_INTERNAL_NVENC_CAPS caps[NV2080_CTRL_CMD_INTERNAL_MAX_NVENCS]; + NvBool valid[NV2080_CTRL_CMD_INTERNAL_MAX_NVENCS]; +} NV2080_CTRL_INTERNAL_NVENC_GET_CAPS_PARAMS; +#define NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS NV2080_CTRL_INTERNAL_NVENC_GET_CAPS_PARAMS + + +#define NV2080_CTRL_INTERNAL_GR_MAX_GPC 64 +#define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT 10 + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_GPC_MASK + * @ref NV2080_CTRL_CMD_GR_GET_TPC_MASK + * @ref NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK + */ + + + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS { + NvU32 gpcMask; + + /*! + * tpcMask is indexed by logical GPC ID for MIG case + * and indexed by physical GPC ID for non-MIG case + */ + NvU32 tpcMask[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; + + /*! + * tpcCount is always indexed by logical GPC ID + */ + NvU32 tpcCount[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; + NvU32 physGpcMask; + NvU32 mmuPerGpc[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; + + NvU32 tpcToPesMap[NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT]; + NvU32 numPesPerGpc[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; + + /*! + * zcullMask is always indexed by physical GPC ID + */ + NvU32 zcullMask[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; + + NvU32 physGfxGpcMask; + NvU32 numGfxTpc; +} NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS; + +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID (0x27U) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS { + /*! + * floorsweeping masks which are indexed via local GR index + */ + NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS floorsweepingMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS (0x20800a26) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID (0x26U) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS; + +/* + * NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES + * + * This command returns physical addresses of specified context buffer. + * To obtain addresses of whole buffer firstPage has to be advanced on + * subsequent invocations of the control until whole buffer is probed. + * If the buffer is contiguous, only single address will be returned by + * this control. + * + * bufferType[IN] + * Buffer type as returned by GET_CTX_BUFFER_INFO. + * + * firstPage[IN] + * Index of the first page to return in 'physAddrs' array. + * + * numPages[OUT] + * Number of entries filled in 'physAddrs' array. This will be 0 + * if firstPage is greater or equal to number of pages managed by 'hBuffer'. + * + * physAddrs[OUT] + * Physical addresses of pages comprising specified buffer. + * + * bNoMorePages[OUT] + * End of buffer reached. Either 'physAddrs' contains last page of the + * buffer or 'firstPage' specifies index past the buffer. + */ +#define NV2080_CTRL_KGR_MAX_BUFFER_PTES 128 +#define NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES (0x20800a28) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID (0x28U) + +typedef struct NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS { + NvHandle hUserClient; + NvHandle hChannel; + NvU32 bufferType; + NvU32 firstPage; + NvU32 numPages; + NV_DECLARE_ALIGNED(NvU64 physAddrs[NV2080_CTRL_KGR_MAX_BUFFER_PTES], 8); + NvBool bNoMorePages; +} NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS; + +/*! + * NV2080_CTRL_INTERNAL_MEMDESC_INFO + * + * A generic container structure representing a memory region to be used as a + * component of other control call parameters. + * + */ +typedef struct NV2080_CTRL_INTERNAL_MEMDESC_INFO { + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NV_DECLARE_ALIGNED(NvU64 alignment, 8); + NvU32 addressSpace; + NvU32 cpuCacheAttrib; +} NV2080_CTRL_INTERNAL_MEMDESC_INFO; + +/*! + * @ref NV0080_CTRL_CMD_GR_GET_INFO + * @ref NV0080_CTRL_CMD_GR_GET_INFO_V2 + * @ref NV2080_CTRL_CMD_GR_GET_INFO + * @ref NV2080_CTRL_CMD_GR_GET_INFO_V2 + */ + + + +/*! + * @ref NV2080_CTRL_GR_INFO + */ +typedef struct NV2080_CTRL_INTERNAL_GR_INFO { + NvU32 index; + NvU32 data; +} NV2080_CTRL_INTERNAL_GR_INFO; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_INFO { + NV2080_CTRL_INTERNAL_GR_INFO infoList[NV0080_CTRL_GR_INFO_MAX_SIZE]; +} NV2080_CTRL_INTERNAL_STATIC_GR_INFO; +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_MESSAGE_ID (0x2BU) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_INFO engineInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO (0x20800a2a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID (0x2AU) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_ZCULL_INFO + */ + + + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO { + NvU32 widthAlignPixels; + NvU32 heightAlignPixels; + NvU32 pixelSquaresByAliquots; + NvU32 aliquotTotal; + NvU32 zcullRegionByteMultiplier; + NvU32 zcullRegionHeaderSize; + NvU32 zcullSubregionHeaderSize; + NvU32 subregionCount; + NvU32 subregionWidthAlignPixels; + NvU32 subregionHeightAlignPixels; +} NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO; + +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x2DU) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO engineZcullInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO (0x20800a2c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x2CU) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_ROP_INFO + */ + + + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO { + NvU32 ropUnitCount; + NvU32 ropOperationsFactor; + NvU32 ropOperationsCount; +} NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO; + +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x2FU) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO engineRopInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO (0x20800a2e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x2EU) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_PPC_MASK + */ + + + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS { + NvU32 mask[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; +} NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS; + +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_MESSAGE_ID (0x31U) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS enginePpcMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS (0x20800a30) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID (0x30U) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES + * @ref NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE + */ + + + +#define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT 0x1a + +typedef struct NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO { + NvU32 size; + NvU32 alignment; +} NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO { + NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO engine[NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT]; +} NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO; + +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID (0x33U) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO engineContextBuffersInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO (0x20800a32) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID (0x32U) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER + */ + + + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER { + NvU8 imla0; + NvU8 fmla16; + NvU8 dp; + NvU8 fmla32; + NvU8 ffma; + NvU8 imla1; + NvU8 imla2; + NvU8 imla3; + NvU8 imla4; +} NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER; + +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x35U) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER smIssueRateModifier[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER (0x20800a34) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x34U) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS; + +/* + * NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS + * + * This command obtains information from physical RM for use by CPU-RM. + */ + +#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_CHIP_INFO (0x20800a36) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID" */ + +/* + * Maximum number of register bases to return. + * These are indexed by NV_REG_BASE_* constants from gpu.h, and this value needs + * to be updated if NV_REG_BASE_LAST ever goes over it. See the ct_assert() in gpu.h + */ +#define NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX 16 +#define NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID (0x36U) + +typedef struct NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS { + NvU8 chipSubRev; + NvU32 emulationRev1; + NvBool isCmpSku; + NvU32 pciDeviceId; + NvU32 pciSubDeviceId; + NvU32 pciRevisionId; + NvU32 regBases[NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX]; +} NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS; + +/** + * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE + * + * Set whether or not context switch logging is enabled + * + * bEnable + * Enable/Disable status for context switch logging + */ +#define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE (0x20800a37) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID" */ + +/** + * NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE + * + * Retrieve whether or not context switch logging is enabled + * + * bEnable + * Enable/Disable status for context switch logging + */ +#define NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE (0x20800a38) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID" */ + +typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvBool bEnable; +} NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS; + +#define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x37U) + +typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS; + +#define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x38U) + +typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS; + +/** + * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET + * + * Set read offset into FECS context switch trace record + * + * offset + * Value indicating number of records by which to offset + */ +#define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET (0x20800a39) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID" */ + +/** + * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET + * + * Set write offset into FECS context switch trace record + * + * offset + * Value indicating number of records by which to offset + */ +#define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET (0x20800a3a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID" */ + +/** + * NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET + * + * Get read offset into FECS context switch trace record + * + * offset + * Value indicating number of records by which to offset + */ + +#define NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET (0x20800a3b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID" */ + +typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvU32 offset; +} NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS; + +#define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x39U) + +typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS; + +#define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID (0x3AU) + +typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS; + +#define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x3BU) + +typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS; + +/** + * NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE + * + * Get size of FECS record + * + * fecsRecordSize + * Size of FECS record + */ + + + +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE (0x20800a3d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID" */ + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE { + NvU32 fecsRecordSize; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE; + +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID (0x3CU) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE fecsRecordSize[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID (0x3DU) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS; + +/** + * NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES + * + * Get HW defines used to extract information from FECS records + * + * fecsRecordSize + * Size of FECS record + * + * timestampHiTagMask + * Mask for high bits of raw timestamp to extract tag + * + * timestampHiTagShift + * Shift for high bits of raw timestamp to extract tag + * + * timestampVMask + * Mask to extract timestamp from raw timestamp + * + * numLowerBitsZeroShift + * Number of bits timestamp is shifted by + */ + + + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES { + NvU32 fecsRecordSize; + NvU32 timestampHiTagMask; + NvU8 timestampHiTagShift; + NV_DECLARE_ALIGNED(NvU64 timestampVMask, 8); + NvU8 numLowerBitsZeroShift; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES; + +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID (0x3EU) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES fecsTraceDefines[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES], 8); +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES (0x20800a3f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID (0x3FU) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS; + +/** + * NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE + * + * Parse the DEVICE_INFO2_TABLE on the physical side and return it to kernel. + */ +typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO { + NvU32 faultId; + NvU32 instanceId; + NvU32 typeEnum; + NvU32 resetId; + NvU32 devicePriBase; + NvU32 isEngine; + NvU32 rlEngId; + NvU32 runlistPriBase; + NvU32 groupId; + NvU32 ginTargetId; + NvU32 deviceBroadcastPriBase; + NvU32 groupLocalInstanceId; +} NV2080_CTRL_INTERNAL_DEVICE_INFO; +#define NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES 512 + +#define NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE (0x20800a40) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID (0x40U) + +typedef struct NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS { + NvU32 numEntries; + NV2080_CTRL_INTERNAL_DEVICE_INFO deviceInfoTable[NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES]; +} NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP (0x20800a41) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE 16384 +#define NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES 4096 + +#define NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID (0x41U) + +typedef struct NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS { + NvU32 userRegisterAccessMapSize; + NvU32 compressedSize; + NvU8 compressedData[NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE]; + NvU32 profilingRangesSize; + NvU8 profilingRanges[NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES]; +} NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS; + +/** + * Get GR PDB properties synchronized between Kernel and Physical + * + * bPerSubCtxheaderSupported + * @ref PDB_PROP_GR_SUPPORTS_PER_SUBCONTEXT_CONTEXT_HEADER + */ + + + +typedef struct NV2080_CTRL_INTERNAL_NV_RANGE { + NV_DECLARE_ALIGNED(NvU64 lo, 8); + NV_DECLARE_ALIGNED(NvU64 hi, 8); +} NV2080_CTRL_INTERNAL_NV_RANGE; + +/*! + * NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS + * + * This structure specifies a target swizz-id and mem_range to update + * + * swizzId[IN] + * - Targeted swizz-id for which the memRange is being set + * + * memAddrRange[IN] + * - Memory Range for given GPU instance + */ +#define NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x43U) + +typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS { + NvU32 swizzId; + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NV_RANGE memAddrRange, 8); +} NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a44) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x44U) + +typedef NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a43) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */ + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES { + NvBool bPerSubCtxheaderSupported; +} NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GPU_CHECK_CTS_ID_VALID + * + * This command validates whether a given CTS ID can be used within a GPU Instance by checking + * if the required GPCs can be allocated from the GPU Instance. + * + * ctsId [in] + * The CTS ID to validate + * + * bCheckClientGI [in] + * Validate the CTS ID against the GPU Instance owned by the client. + * + * giComputeSize [in] + * The compute size for the GPU Instance, which determines the number of GPCs in the GPU Instance. + * + * bCtsIdValid [out] + * Returns whether the CTS ID is valid within the specified GPU Instance. + */ +#define NV2080_CTRL_CMD_INTERNAL_GPU_CHECK_CTS_ID_VALID (0x20800a46) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_CHECK_CTS_ID_VALID_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GPU_CHECK_CTS_ID_VALID_PARAMS_MESSAGE_ID (0x46U) + +typedef struct NV2080_CTRL_INTERNAL_GPU_CHECK_CTS_ID_VALID_PARAMS { + NvU32 ctsId; + NvBool bCheckClientGI; + NvU32 giComputeSize; + NvBool bCtsIdValid; +} NV2080_CTRL_INTERNAL_GPU_CHECK_CTS_ID_VALID_PARAMS; + +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID (0x47U) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES pdbTable[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES (0x20800a48) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID (0x48U) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM + * + * This command writes instance memory information in the display hardware registers. + * + * instMemPhysAddr + * GPU physical address or IOVA address of the display instance memory. + * + * instMemSize + * Size of the display instance memory. + * + * instMemAddrSpace + * Address space of the display instance memory. + * + * instMemCpuCacheAttr + * Cache attribute of the display instance memory. + */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM (0x20800a49) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID (0x49U) + +typedef struct NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS { + NV_DECLARE_ALIGNED(NvU64 instMemPhysAddr, 8); + NV_DECLARE_ALIGNED(NvU64 instMemSize, 8); + NvU32 instMemAddrSpace; + NvU32 instMemCpuCacheAttr; +} NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS; + +/* + * NV2080_CTRL_INTERNAL_GPU_RECOVER_ALL_COMPUTE_CONTEXTS + * + * This command issues RC recovery for all compute contexts running on the given GPU. + */ +#define NV2080_CTRL_CMD_INTERNAL_RECOVER_ALL_COMPUTE_CONTEXTS (0x20800a4a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x4A" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION + * + * This command obtains IP version of display engine for use by Kernel RM. + * + * ipVersion + * IP Version of display engine. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED - DISP has been disabled + */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION (0x20800a4b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID (0x4BU) + +typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS { + NvU32 ipVersion; +} NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE + * + * This command determines the current status of MIG MODE from Physical RM. + * + * smcMode [OUT] + * Current MIG MODE of the GPU. Values range NV2080_CTRL_GPU_INFO_GPU_SMC_MODE* + */ +#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE (0x20800a4c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID (0x4CU) + +typedef struct NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS { + NvU32 smcMode; +} NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR + * + * head + * This parameter specifies the head for which the callback is to be registered/unregistered. This value must be + * less than the maximum number of heads supported by the GPU subdevice. + * + * rgLineNum + * This indicates the RG scanout line number on which the callback will be executed. + * + * intrLine + * Enable: [out] Which interrupt line was allocated for this head. + * Disable: [in] Which interrupt line to deallocate. + * + * bEnable + * Should we allocate or deallocate an interrupt line? + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC - There was no available interrupt to allocate. + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR (0x20800a4d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID (0x4DU) + +typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS { + NvU32 head; + NvU32 rgLineNum; + NvU32 intrLine; + NvBool bEnable; +} NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS; + +/*! + * NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO + * + * Description of a supported GPU instance. + * + * partitionFlag [OUT] + * Allocation flag to be used to allocate a partition with this profile. + * + * grCount [OUT] + * # GR engines, including the GFX capable ones. + * + * gfxGrCount [OUT] + * # GR engines capable of Gfx, which is a subset of the GR engines included in grCount + * + * gpcCount [OUT] + * # total gpcs, including the GFX capable ones. + * + * virtualGpcCount [OUT] + * # virtualized gpcs, including the GFX capable ones. + * + * gfxGpcCount [OUT] + * # total gpcs capable of Gfx. This is a subset of the GPCs included in gpcCount. + * + * veidCount [OUT] + * # total veids + * + * smCount [OUT] + * # total SMs + * + * ceCount [OUT] + * # CE engines + * + * nvEncCount [OUT] + * # NVENC engines + * + * nvDecCount [OUT] + * # NVDEC engines + * + * nvJpgCount [OUT] + * # NVJPG engines + * + * nvOfaCount [OUT] + * # NVOFA engines + * + * validCTSIdMask [OUT] + * # mask of CTS IDs which can be assigned under this profile + * + * validGfxCTSIdMask [OUT] + * # mask of CTS IDs that contain Gfx capable Grs which can be assigned under this profile + */ +#define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 90 + + + +typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO { + NvU32 partitionFlag; + NvU32 grCount; + NvU32 gfxGrCount; + NvU32 gpcCount; + NvU32 virtualGpcCount; + NvU32 gfxGpcCount; + NvU32 veidCount; + NvU32 smCount; + NvU32 ceCount; + NvU32 nvEncCount; + NvU32 nvDecCount; + NvU32 nvJpgCount; + NvU32 nvOfaCount; + NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8); + NV_DECLARE_ALIGNED(NvU64 validGfxCTSIdMask, 8); +} NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO; + +/*! + * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS + * + * Returns the list of supported GPU instance profiles. + * + * count [OUT] + * Number of supported profiles. + * + * table [OUT] + * Supported profiles. + */ +#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID (0x4FU) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS { + NvU32 count; + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO table[NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES], 8); +} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM + * + * This command instructs the physical MemorySystem to set up memory partitioning + * exterior boundaries in hardware. + * + * partitionableMemSize [input] + * Size of the partitionable memory in bytes + * + * bottomRsvdSize [input] + * Size of the reserved region below partitionable memory in bytes + * + * topRsvdSize [input] + * Size of the reserved region above partitionable memory in bytes + * + * partitionableStartAddr [output] + * Start address of the partitionable memory, aligned to HW constraints + * + * partitionableEndAddr [output] + * End address of the partitionable memory, aligned to HW constraints + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM (0x20800a51) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID (0x51U) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS { + NV_DECLARE_ALIGNED(NvU64 partitionableMemSize, 8); + NV_DECLARE_ALIGNED(NvU64 bottomRsvdSize, 8); + NV_DECLARE_ALIGNED(NvU64 topRsvdSize, 8); + NV_DECLARE_ALIGNED(NvU64 partitionableStartAddr, 8); + NV_DECLARE_ALIGNED(NvU64 partitionableEndAddr, 8); +} NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS; + + + +#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_MAX_ENGINES_MASK_SIZE 4 + +#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x52U) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS { + NV_DECLARE_ALIGNED(NvU64 engineMask[NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_MAX_ENGINES_MASK_SIZE], 8); +} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS; + +#define NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS 2 +#define NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID 64 +/*! + * NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS + * + * Promote a single partition's runlist buffers allocated by kernel Client RM to Physical RM + * + * rlBuffers [IN] + * 2D array of runlist buffers for a single partition + * + * runlistIdMask [IN] + * Mask of runlists belonging to partition + * + */ +#define NV2080_CTRL_CMD_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS (0x20800a53) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID (0x53U) + +typedef struct NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MEMDESC_INFO rlBuffers[NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID][NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS], 8); + NV_DECLARE_ALIGNED(NvU64 runlistIdMask, 8); + NvU32 swizzId; +} NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_SET_IMP_INIT_INFO (0x20800a54) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID (0x54U) + +typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS { + TEGRA_IMP_IMPORT_DATA tegraImpImportData; +} NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_GET_EGPU_BRIDGE_INFO (0x20800a55) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS_MESSAGE_ID (0x55U) + +typedef struct NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS { + NvU16 pciDeviceId; + NvU16 pciSubDeviceId; + NvBool iseGPUBridge; + NvU8 approvedBusType; +} NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS; + +#define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_NONE (0x00000000) +#define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_CUSTOM (0x00000001) +#define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB2 (0x00000002) +#define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB3 (0x00000003) + + +/*! + * NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR + * + * This command triggers a sysmembar to flush VIDMEM writes. + * This command accepts no parameters. + * + */ +#define NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR (0x20800a70) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x70" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL + * + * Setup local PCIE P2P Mailbox + * + * local2Remote[IN] + * Local peer ID of remote gpu on local gpu + * + * remote2Local[IN] + * Remote peer ID of local gpu on remote gpu + * + * localP2PDomainRemoteAddr[IN] + * P2P domain remote address on local gpu + * + * remoteP2PDomainLocalAddr[IN] + * P2P domain local address on remote gpu + * + * remoteWMBoxLocalAddr[IN] + * Local mailbox address on remote gpu + * + * p2pWmbTag[OUT] + * Tag for mailbox to transport from local to remote GPU + * + * bNeedWarBug999673[IN] + * Set to true if WAR for bug 999673 is required + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL (0x20800a71) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID (0x71U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS { + NvU32 local2Remote; + NvU32 remote2Local; + NV_DECLARE_ALIGNED(NvU64 localP2PDomainRemoteAddr, 8); + NV_DECLARE_ALIGNED(NvU64 remoteP2PDomainLocalAddr, 8); + NV_DECLARE_ALIGNED(NvU64 remoteWMBoxLocalAddr, 8); + NV_DECLARE_ALIGNED(NvU64 p2pWmbTag, 8); + NvBool bNeedWarBug999673; +} NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS; + + /* + * NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE + * + * Setup remote PCIE P2P Mailbox + * + * local2Remote[IN] + * Local peer ID of remote gpu on local gpu + * + * remote2Local[IN] + * Remote peer ID of local gpu on remote gpu + * + * localP2PDomainRemoteAddr[IN] + * P2P domain remote address on local gpu + * + * remoteP2PDomainLocalAddr[IN] + * P2P domain local address on remote gpu + * + * remoteWMBoxAddrU64[IN] + * Mailbox address on remote gpu + * + * p2pWmbTag[IN] + * Tag for mailbox to transport from local to remote GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE (0x20800a72) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID (0x72U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS { + NvU32 local2Remote; + NvU32 remote2Local; + NV_DECLARE_ALIGNED(NvU64 localP2PDomainRemoteAddr, 8); + NV_DECLARE_ALIGNED(NvU64 remoteP2PDomainLocalAddr, 8); + NV_DECLARE_ALIGNED(NvU64 remoteWMBoxAddrU64, 8); + NV_DECLARE_ALIGNED(NvU64 p2pWmbTag, 8); +} NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX + * + * Destroy PCIE P2P Mailbox + * + * peerIdx[IN] + * Peer ID of the P2P destination GPU + * + * bNeedWarBug999673[IN] + * Set to true if WAR for bug 999673 is required + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX (0x20800a73) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID (0x73U) + +typedef struct NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS { + NvU32 peerIdx; + NvBool bNeedWarBug999673; +} NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING + * + * Create C2C mapping to a given peer GPU + * + * peerId[IN] + * Peer ID for local to remote GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING (0x20800a74) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID (0x74U) + +typedef struct NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS { + NvU32 peerId; +} NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING + * + * Remove C2C mapping to a given peer GPU + * + * peerId[IN] + * Peer ID for local to remote GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING (0x20800a75) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID (0x75U) + +typedef struct NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS { + NvU32 peerId; +} NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES + * + * Retrieves the corresponding SPAs (per the given GFID's VMMU mappings) + * for the given array of GPAs. + * + * gfid [IN] + * GFID to translate GPAs for + * + * numEntries [IN] + * Number of entries (<= NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES) + * to translate (i.e. number of elements in gpaEntries) + * + * gpaEntries [IN] + * Array of GPAs to translate + * + * spaEntries [OUT] + * Resulting array of SPAs + */ +#define NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES (0x20800a57) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES 128 + +#define NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID (0x57U) + +typedef struct NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS { + NvU32 gfid; + NvU32 numEntries; + NV_DECLARE_ALIGNED(NvU64 gpaEntries[NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES], 8); + NV_DECLARE_ALIGNED(NvU64 spaEntries[NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES], 8); +} NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER + * + * Pass required pushbuffer parameters from kernel RM to Physical RM + * + * addressSpace [IN] + * Address space of pushbuffer whtether it is ADDR_SYSMEM or ADDR_FBMEM + * + * physicalAddr [IN] + * Physical address of pushbuffer + * + * addressSpace [IN] + * Limit of the pushbuffer address, it should be less than 4K + * + * cacheSnoop [IN] + * Cachesnoop supported or not + * + * channelInstance [IN] + * Channel instance pass by the client to get corresponding dispchannel + * + * hclass [IN] + * External class ID pass by the client to get the channel class + * + * valid [IN] + * This bit indicates whether pushbuffer parameters are valid or not + * + * pbTargetAperture [IN] + * Indicates the PushBuffer Target Aperture type (IOVA, PCI, PCI_COHERENT or NVM) + * + * channelPBSize [IN] + * Indicates the PushBuffer size requested by client + * + * subDeviceId [IN] + * One-hot encoded subDeviceId (i.e. SDM) that will be used to address the channel + * in the pushbuffer stream (via SSDM method) + */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER (0x20800a58) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID (0x58U) + +typedef struct NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS { + NvU32 addressSpace; + NV_DECLARE_ALIGNED(NvU64 physicalAddr, 8); + NV_DECLARE_ALIGNED(NvU64 limit, 8); + NvU32 cacheSnoop; + NvU32 hclass; + NvU32 channelInstance; + NvBool valid; + NvU32 pbTargetAperture; + NvU32 channelPBSize; + NvU32 subDeviceId; +} NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO + * + * This command obtains information from physical RM for use by CPU-RM. + * + * replayableFaultBufferSize + * Default size of replayable fault buffer + * + * nonReplayableFaultBufferSize + * Default size of non-replayable fault buffer + * + */ + +#define NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO (0x20800a59) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0x59U) + +typedef struct NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS { + NvU32 replayableFaultBufferSize; + NvU32 replayableShadowFaultBufferMetadataSize; + NvU32 nonReplayableFaultBufferSize; + NvU32 nonReplayableShadowFaultBufferMetadataSize; +} NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_CTXSW_MODES + */ +#define NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES (0x20800a5a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID (0x5AU) + +typedef NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE + * + * Get heap reservation size needed by different module + */ +#define NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE (0x20800a5b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID (0x5BU) + +typedef struct NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS { + NvU32 moduleIndex; + NvU32 size; +} NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE + * + * tableLen [OUT] + * Number of valid records in table field. + * + * table [OUT] + * Interrupt table for Kernel RM. + * + * subtreeMap [OUT] + * Subtree mask for each NV2080_INTR_CATEGORY. + */ +#define NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE (0x20800a5c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE 128 + +typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY { + NvU16 engineIdx; + NvU32 pmcIntrMask; + NvU32 vectorStall; + NvU32 vectorNonStall; +} NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY; + +#define NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID (0x5CU) + +typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS { + NvU32 tableLen; + NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY table[NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE]; + NV_DECLARE_ALIGNED(NV2080_INTR_CATEGORY_SUBTREE_MAP subtreeMap[NV2080_INTR_CATEGORY_ENUM_COUNT], 8); +} NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS; + +/* Index to retrieve the needed heap space for specific module */ +#define NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_GR (0x00000000) + +/* + * NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK + * + * Checking if the reservation / release of the PERFMON HW is possible + * + * bReservation [IN] + * NV_TRUE -> request for reservation, NV_FALSE -> request for release + * + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK (0x20800a98) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID" */ + + +#define NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID (0x98U) + +typedef struct NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS { + NvBool bReservation; +} NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET + * + * Reserving / Releasing PERFMON HW + * + * bReservation [IN] + * NV_TRUE -> request for reservation, NV_FALSE -> request for release + * + * bClientHandlesGrGating [IN] + * DM-TODO: Add comment for this + * + * bRmHandlesIdleSlow [IN] + * If the IDLE slowdown is required + * + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET (0x20800a99) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID (0x99U) + +typedef struct NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS { + NvBool bReservation; + NvBool bClientHandlesGrGating; + NvBool bRmHandlesIdleSlow; +} NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES + * + * Get active display devices + * + * displayMask [OUT] + * Get the mask of the active display devices in VBIOS + * + * numHeads [OUT] + * Number of heads display supported. + * + */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES (0x20800a5d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID (0x5DU) + +typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS { + + NvU32 displayMask; + NvU32 numHeads; +} NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS; + + + +/* + * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES + * + * Get FB Mem page ranges for all possible swizzIds + * + * fbMemPageRanges [OUT] + * Mem page ranges for each swizzId in the form of {lo, hi} + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a60) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID 15 + +#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x60U) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NV_RANGE fbMemPageRanges[NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID], 8); +} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS + * + * This command is an internal command sent from Kernel RM to Physical RM + * to get number of channels for a given runlist ID + * + * runlistId [IN] + * numChannels [OUT] + */ +#define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS (0x20800a61) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID (0x61U) + +typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS { + NvU32 runlistId; + NvU32 numChannels; +} NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES + * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PROFILES + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES (0x20800a63) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID (0x63U) + +typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES + * NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES (0x20800a65) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x65U) + +typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES + * NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a66) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x66U) + +typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG + * NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG + * + * This command retrieves memory config from HW + * + * memBoundaryCfgA [OUT] + * Memory boundary config A (4KB aligned) + * + * memBoundaryCfgB [OUT] + * Memory boundary config B (4KB aligned) + * + * memBoundaryCfgC [OUT] + * Memory boundary config C (64KB aligned) + * + * memBoundaryCfg [OUT] + * Memory boundary config (64KB aligned) + * + * memBoundaryCfgValInit [OUT] + * Memory boundary config initial value (64KB aligned) + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a68) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID (0x68U) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS { + NV_DECLARE_ALIGNED(NvU64 memBoundaryCfgA, 8); + NV_DECLARE_ALIGNED(NvU64 memBoundaryCfgB, 8); + NvU32 memBoundaryCfgC; + NvU32 memBoundaryCfg; + NvU32 memBoundaryCfgValInit; +} NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a67) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID (0x67U) + +typedef NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE (0x20800a6b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE 8 + +#define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID (0x6BU) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS { + NvU32 data[NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE]; +} NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT + * + * Invoke RC recovery after watchdog timeout is hit. + */ +#define NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT (0x20800a6a) /* finn: Evaluated from "((FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6a)" */ + +/* ! + * This command is used to get the current AUX power state of the sub-device. + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_GET_AUX_POWER_STATE (0x20800a81) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS { + NvU32 powerState; +} NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS; + +/*! + * This command can be used to boost P-State up one level or to the highest for a limited + * duration for the associated subdevice. Boosts from different clients are being tracked + * independently. Note that there are other factors that can limit P-States so the resulting + * P-State may differ from expectation. + * + * flags + * This parameter specifies the actual command. _CLEAR is to clear existing boost. + * _BOOST_1LEVEL is to boost P-State one level higher. _BOOST_TO_MAX is to boost + * to the highest P-State. + * duration + * This parameter specifies the duration of the boost in seconds. This has to be less + * than NV2080_CTRL_PERF_BOOST_DURATION_MAX. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_2X (0x20800a9a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID (0x9AU) + +typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X { + + NvBool flags; + NvU32 duration; +} NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X; + +#define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_PSTATE 0U +#define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK 1U +#define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK +#define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM (0x2U) /* finn: Evaluated from "NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST + 1" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL + * + * Activate/Deactivate GPU Boost Sync algorithm + * + * bActivate [IN] + * GPU Boost Sync algorithm: + * NV_TRUE -> activate + * NV_FALSE -> deactivate + * + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL (0x20800a7e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID (0x7EU) + +typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS { + NvBool bActivate; +} NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS + * + * Apply given limits to a specific subdevice + * + * flags [IN] + * DM-TODO: write description here + * + * bBridgeless [IN] + * Bridgeless information, for now supporting only MIO bridges + * + * currLimits + * Array of limits that will be applied + * + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS (0x20800a7f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID (0x7FU) + +typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS { + NvU32 flags; + NvBool bBridgeless; + NvU32 currLimits[NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM]; +} NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO + * + * Data for GPU Boost Sync structure initialization + * + * hysteresisus [OUT] + * Hysteresis value for GPU Boost synchronization hysteresis algorithm. + * + * bHystersisEnable [OUT] + * hysteresis algorithm for SLI GPU Boost synchronization: + * NV_TRUE -> enabled, + * NV_FALSE -> disabled + * + * bSliGpuBoostSyncEnable [OUT] + * SLI GPU Boost feature is: + * NV_TRUE -> enabled, + * NV_FALSE -> disabled + * + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO (0x20800a80) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID (0x80U) + +typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 hysteresisus, 8); + NvBool bHystersisEnable; + NvBool bSliGpuBoostSyncEnable; +} NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER + * + * This command sends replayable fault buffer pages allocated by CPU-RM + * to be setup and enabled in physical RM. + * + * hClient + * Client handle. + * + * hObject + * Object handle. + * + * faultBufferSize + * Size of the replayable fault buffer to register. + * + * faultBufferPteArray + * Pages of replayable fault buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER (0x20800a9b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES 256 +#define NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9BU) + +typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS { + NvHandle hClient; + NvHandle hObject; + NvU32 faultBufferSize; + NV_DECLARE_ALIGNED(NvU64 faultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES], 8); +} NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER + * + * This command requests physical RM to disable the replayable fault buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER (0x20800a9c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x9C" */ + +// Valid fault buffer types +#define NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE (0x00000000) +#define NV2080_CTRL_FAULT_BUFFER_REPLAYABLE (0x00000001) + +/* + * NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER + * + * This command sends client shadow fault buffer pages allocated by CPU-RM + * to be setup and enabled in physical RM. + * + * shadowFaultBufferQueuePhysAddr + * Physical address of shadow fault buffer queue. + * + * faultBufferSize + * Size of the client shadow fault buffer to register. + * + * shadowFaultBufferPteArray + * Pages of client shadow fault buffer. + * + * shadowFaultBufferType + * Replayable or non-replayable fault buffer + * + * faultBufferSharedMemoryPhysAddr + * Fault buffer shared memory address. Used only by the Replayable fault buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES 3000 +#define NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9DU) + +typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS { + NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferQueuePhysAddr, 8); + NvU32 shadowFaultBufferSize; + NvU32 shadowFaultBufferMetadataSize; + NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES], 8); + NvU32 shadowFaultBufferType; + NV_DECLARE_ALIGNED(NvU64 faultBufferSharedMemoryPhysAddr, 8); +} NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER + * + * This command requests physical RM to disable the client shadow fault buffer. + * + * shadowFaultBufferType + * Replayable or non-replayable fault buffer + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9EU) + +typedef struct NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS { + NvU32 shadowFaultBufferType; +} NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER + * + * Pin PDEs for Global VA range on the server RM and then mirror the client's page + * directory/tables in the server. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER (0x20800a9f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID (0x9FU) + +typedef struct NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS { + NV_DECLARE_ALIGNED(NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS PdeCopyParams, 8); +} NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X + * + * This command can be used to boost P-State the highest for a limited + * duration for the associated subdevice. Boosts from different clients are being tracked + * independently. Note that there are other factors that can limit P-States so the resulting + * P-State may differ from expectation. + * + * flags [IN] + * This parameter specifies the actual command. _CLEAR is to clear existing boost. + * and _BOOST_TO_MAX is to boost to the highest P-State. + * + * boostDuration [IN] + * This parameter specifies the duration of the boost in seconds. This has to be less + * than NV2080_CTRL_PERF_BOOST_DURATION_MAX. + * + * gfId [IN] + * This specifies Id of the Kernel RM that is requesting the Boost + * + * bOverrideInfinite[IN] + * This parameter specifies if we want to override already registered infinite boost for the specific Kernel RM. + * This should be NV_TRUE only in case when we are removing the current infinite boost for a specific Kernel RM + * and setting the boost duration to a next maximum duration registered for the Kernel RM in question. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X (0x20800aa0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID (0xA0U) + +typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X { + NvU32 flags; + NvU32 boostDuration; + NvU32 gfId; + NvBool bOverrideInfinite; +} NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X + * + * Clear the boost for specific Kernel RM + * + * bIsCudaClient [IN] + * Specifies if the request is for clearing the CUDA boost or regular boost + * NV_TRUE -> CUDA boost, NV_FALSE otherwise + * + * gfId [IN] + * Specifies Id of the Kernel RM that is requesting Boost clear + * + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X (0x20800aa1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID (0xA1U) + +typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X { + + NvBool bIsCudaClient; + NvU32 gfId; +} NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X; + +/* + * NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO + * + * Retrieves skyline information about the GPU. Params are sized to currently known max + * values, but will need to be modified in the future should that change. + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO (0x20800aa2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES 9 +#define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS 64 +/*! + * NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO + * skylineVgpcSize[OUT] + * - TPC count of non-singleton VGPCs + * singletonVgpcMask[OUT] + * - Mask of active Singletons + * maxInstances[OUT] + * - Max allowed instances of this skyline concurrently on a GPU + * computeSizeFlag + * - One of NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* flags which is associated with this skyline + * numNonSingletonVgpcs + * - Number of VGPCs with non-zero TPC counts which are not singletons + */ +typedef struct NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO { + NvU8 skylineVgpcSize[NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS]; + NvU32 singletonVgpcMask; + NvU32 maxInstances; + NvU32 computeSizeFlag; + NvU32 numNonSingletonVgpcs; +} NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO; + +/*! + * NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS + * skylineTable[OUT] + * - TPC count of non-singleton VGPCs + * - Mask of singleton vGPC IDs active + * - Max Instances of this skyline possible concurrently + * - Associated compute size with the indexed skyline + * - Number of VGPCs with non-zero TPC counts which are not singletons + * validEntries[OUT] + * - Number of entries which contain valid info in skylineInfo + */ +#define NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID (0xA2U) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS { + NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO skylineTable[NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES]; + NvU32 validEntries; +} NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE + */ +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE (0x20800aa3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID (0xA3U) + +typedef NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION + */ +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE (0x20800aa4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA4U) + +typedef NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONS + */ +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES (0x20800aa5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID (0xA5U) + +typedef NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GPU_GET_PARTITIONS + */ +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES (0x20800aa6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID (0xA6U) + +typedef NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED + * + * Tell Physical RM whether any ZBC-kind surfaces are allocated. + * If PF and all VFs report false, ZBC table can be flushed by Physical RM. + * + * bZbcReferenced [IN] + * NV_TRUE -> ZBC-kind (and no _SKIP_ZBCREFCOUNT flag) are allocated in Kernel RM + * + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED (0x20800a69) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID (0x69U) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS { + NvBool bZbcSurfacesExist; +} NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE + * + * Export the resource and placement information about a gpu instance such that a + * similar gpu instance can be recreated from scratch in the same position on the + * same or similar GPU. Note that different GPUs may have different physical + * resources due to floorsweeping, and an imported gpu instance is not guaranteed + * to get the exact same resources as the exported gpu instance, but the imported + * gpu instance should behave identically with respect to fragmentation and + * placement / span positioning. + */ +#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE (0x20800aa7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE (0x20800aa8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE + * + * Create a gpu instance resembling the exported instance info. Note that + * different GPUs may have different physical resources due to floorsweeping, + * and an imported gpu instance is not guaranteed to get the exact same resources + * as the exported gpu instance, but the imported gpu instance should behave + * identically with respect to fragmentation and placement / span positioning. + */ +#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE (0x20800aa9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE (0x20800aaa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE 4 +typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO { + NV_DECLARE_ALIGNED(NvU64 enginesMask[NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE], 8); + NvU32 partitionFlags; + NvU32 gpcMask; + NvU32 virtualGpcCount; + NvU32 veidOffset; + NvU32 veidCount; +} NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO; + +typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS { + NvU32 swizzId; + NvU8 uuid[NV_GI_UUID_LEN]; + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO info, 8); +} NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS; + +#define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA7U) + +typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS; + +#define NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA8U) + +typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS; + +#define NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA9U) + +typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS; + +#define NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xAAU) + +typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT + * + * Invalidate and/or evict the L2 cache + * + * flags [IN] + * flags that specify required actions + * + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT (0x20800a6c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID (0x6cU) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS { + NvU32 flags; +} NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS; + +#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL (0x00000001) +#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_FIRST (0x00000002) +#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_LAST (0x00000004) +#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_NORMAL (0x00000008) +#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_CLEAN (0x00000010) +#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_WAIT_FB_PULL (0x00000020) + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES + * + * Flush all L2 Rams and Caches using the ELPG flush + * + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES (0x20800a6d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6D" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_CLEAN_LTC_PROBE_FILTER + * + * Set the L2 coherence probe filter to CLEAN state. + * This evicts all checked-out lines from the probe filter. + * + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_CLEAN_LTC_PROBE_FILTER (0x20800ab0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xB0" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO + * + * This command obtains information from physical RM for use by CPU-RM + * + * Data fields -> + * bPcieGen4Capable - tells whether PCIe is Gen4 capable + */ +#define NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO (0x20800aac) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0xacU) + +typedef struct NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS { + NvBool bPcieGen4Capable; + NvBool bIsC2CLinkUp; + NvBool bIsDeviceMultiFunction; + NvBool bGcxPmuCfgSpaceRestore; +} NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_BIF_GET_DATA + * + * This command is used to redirect calls to physical RM if the info required by various clients is present in physical RM + */ +#define NV2080_CTRL_CMD_INTERNAL_BIF_GET_DATA (0x20800a00) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8)" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG + * + * Program HSHUB Peer Conn Config space. + * + * programPeerMask[IN] + * If nonzero, the peer mask for programming peers based on hshub connectivity. + * + * invalidatePeerMask[IN] + * If nonzero, the peer mask for invalidating peers. + * + * programPciePeerMask[IN] + * If nonzero, the peer mask for programming peers in pcie case. + * + * Possible status values returned are: + * NV_OK + * NV_WARN_NOTHING_TO_DO + * If all peer masks are zero. + */ +#define NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG (0x20800a88) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID (0x88U) + +typedef struct NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS { + NvU32 programPeerMask; + NvU32 invalidatePeerMask; + NvU32 programPciePeerMask; +} NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS + * + * Get the Hshub Ids connected to the other end of links. + * + * linkMask[IN] + * A mask of link ids to query. + * + * hshubIds[OUT] + * For each set bit in the link mask, the peer Hshub Id. + * + * Possible status values returned are: + * NV_OK + * NV_WARN_NOTHING_TO_DO + * If the mask is zero. + */ +#define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS (0x20800a8a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE 32 + +#define NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID (0x8aU) + +typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS { + NvU32 linkMask; + NvU8 hshubIds[NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE]; +} NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS + * + * Return the number of HSHUB units. + * + * numHshubs[OUT] + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS (0x20800a8b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID (0x8bU) + +typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS { + NvU32 numHshubs; +} NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID + * + * Return the next hshubId after the given hshubId. + * + * hshubId[IN/OUT] + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID (0x20800a8c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID (0x8cU) + +typedef struct NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS { + NvU8 hshubId; +} NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG + * + * Program HSHUB for EGM peer id. + * + * egmPeerId[IN] + * EGM peer id to program in the HSHUB registers. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG (0x20800a8d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID (0x8dU) + +typedef struct NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS { + NvU32 egmPeerId; +} NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR + * + * Enable compute peer addressing mode + * This command accepts no parameters. + */ + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR (0x20800aad) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xad" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR + * + * Get/Set NVSwitch fabric address for FLA + * + * [In] bGet + * Whether to get or set the NVSwitch fabric address + * [In/Out] addr + * Address that is to be set or retrieved. + */ +#define NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID (0xaeU) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS { + NvBool bGet; + NV_DECLARE_ALIGNED(NvU64 addr, 8); +} NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR (0x20800aae) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT + * + * Sets number of VM slots that are active in VGPU's scheduler + * + * maxActiveVGpuVMCount [IN] + * Number of VM slots that are active in vGPU's scheduler. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OUT_OF_RANGE - Passed value is out of range + * NV_ERR_NO_MEMORY - Out of memory + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT (0x20800ab1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID" */ + +/*! + * Maximum value of VM slots that are active in vGPU's scheduler. + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_MAX_ACTIVE_VGPU_VM_COUNT_MAX_VALUE 32 + +#define NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID (0xB1U) + +typedef struct NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS { + NvU8 maxActiveVGpuVMCount; +} NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS + * + * Disable all NVLINK FB peers + * + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS (0x20800a6e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6E" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE + * + * Program GPU in raw / legacy compression mode + * + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE (0x20800a6f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID (0x6fU) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS { + NvBool bRawMode; +} NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_CCU_GET_SAMPLE_INFO + * + * This command gets the CCU samples Info from physical-RM. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_CCU_GET_SAMPLE_INFO (0x20800ab2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xB2" */ + +typedef struct NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS { + NvU32 ccuSampleSize; +} NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_CCU_MAP + * + * This command gets the shared buffer memory descriptor from the CPU-RM and maps to it + * in physical-RM. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_ADDRESS + */ +#define NV2080_CTRL_CMD_INTERNAL_CCU_MAP (0x20800ab3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX 1 + +typedef struct NV2080_CTRL_INTERNAL_CCU_MAP_INFO { + NV_DECLARE_ALIGNED(NvU64 phyAddr, 8); + NvU32 shrBufSize; + NvU32 cntBlkSize; +} NV2080_CTRL_INTERNAL_CCU_MAP_INFO; + +#define NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID (0xB3U) + +typedef struct NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_CCU_MAP_INFO mapInfo[NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE + NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX], 8); +} NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP + * + * This command unmaps the shared buffer memory mapping in physical-RM + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP (0x20800ab4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID (0xB4U) + +typedef struct NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS { + NvBool bDevShrBuf; + NvBool bMigShrBuf; +} NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS; + +/*! + * NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO + * + * [in] gpuId + * GPU ID. + * [in] gpuInstance + * GPU instance. + * [in] p2pCaps + * Peer to peer capabilities discovered between the GPUs. + * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. + * [in] p2pOptimalReadCEs + * Mask of CEs to use for p2p reads over Nvlink. + * [in] p2pOptimalWriteCEs + * Mask of CEs to use for p2p writes over Nvlink. + * [in] p2pCapsStatus + * Status of all supported p2p capabilities. + * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. + * [in] busPeerId + * Bus peer ID. For an invalid or a non-existent peer this field + * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. + * [in] busEgmPeerId + * Bus EGM peer ID. For an invalid or a non-existent peer this field + * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. + */ +typedef struct NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO { + NvU32 gpuId; + NvU32 gpuInstance; + NvU32 p2pCaps; + NvU32 p2pOptimalReadCEs; + NvU32 p2pOptimalWriteCEs; + NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; + NvU32 busPeerId; + NvU32 busEgmPeerId; +} NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO; + +/*! + * NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS + * + * An internal call to propagate the peer to peer capabilities of peer GPUs + * to the Physical RM. These capabilities are to be consumed by the vGPU GSP plugin. + * This control is used to both add and and update the peer to peer capabilities. + * The existing GPU entries will be updated and those which don't exist will be added. + * Use NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS to remove the added entries. + * + * [in] peerGpuCount + * The number of the peerGpuInfos entries. + * [in] peerGpuInfos + * The array of NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS entries, describing + * the peer to peer capabilities of the specified GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT - Invalid peerGpuCount + * NV_ERR_INSUFFICIENT_RESOURCES - Total GPU count exceeds the maximum value + */ +#define NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS (0x20800ab5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID (0xB5U) + +typedef struct NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS { + NvU32 peerGpuCount; + NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO peerGpuInfos[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; +} NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS + * + * An internal call to remove the cached peer to peer capabilities of peer GPUs + * from the Physical RM. + * + * [in] peerGpuIdCount + * The number of the peerGpuIds entries. + * [in] peerGpuIds + * The array of GPU IDs, specifying the GPU for which the entries need to be removed. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT - Invalid peerGpuIdCount + * NV_ERR_OBJECT_NOT_FOUND - Invalid peerGpuIds[] entry + */ +#define NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS (0x20800ab6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID (0xB6U) + +typedef struct NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS { + NvU32 peerGpuIdCount; + NvU32 peerGpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; +} NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS; + + + +/*! + * NV2080_CTRL_CMD_INTERNAL_BUS_GET_PCIE_P2P_CAPS + * + * This command returns the GPU's PCIE P2P caps + * + * [in] bCommonPciSwitchFound + * All GPUs are under the same PCI switch + * [out] p2pReadCapsStatus + * [out] p2pWriteCapsStatus + * These members returns status of all supported p2p capabilities. Valid + * status values include: + * NV0000_P2P_CAPS_STATUS_OK + * P2P capability is supported. + * NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED + * Chipset doesn't support p2p capability. + * NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED + * GPU doesn't support p2p capability. + * NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED + * IOH topology isn't supported. For e.g. root ports are on different + * IOH. + * NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY + * P2P Capability is disabled by a regkey. + * NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED + * P2P Capability is not supported. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_INTERNAL_GET_PCIE_P2P_CAPS (0x20800ab8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID (0xB8U) + +typedef struct NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS { + NvBool bCommonPciSwitchFound; + NvU8 p2pReadCapsStatus; + NvU8 p2pWriteCapsStatus; +} NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO + * + * Enable/disable PCIe Relaxed Ordering. + * + */ +#define NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO (0x20800ab9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID (0xB9U) + +typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS { + // Enable/disable PCIe relaxed ordering + NvBool enableRo; +} NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE + * + * An internal call to invoke the sequence VGA register reads & writes to + * perform save and restore of VGA + * + * [in] bSave + * To indicate whether save or restore needs to be performed. + * [in] bUseVbios + * Primary VGA indication from OS. + * [out] bReturnEarly + * To indicate caller to return after this call. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OPERATION + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE (0x20800a76) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS_MESSAGE_ID (0x76U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS { + NvBool bSave; + NvBool bUseVbios; + NvBool bReturnEarly; +} NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE + * + * To perform save or restore operation from/to saved fonts. + * + * [in] bSave + * To indicate whether save or restore needs to be performed. + * [in] bUseVbios + * Primary VGA indication from OS. + * [in] bVbiosCallSuccessful + * Indicates if vbios invocation was successful or not. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE (0x20800a77) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS_MESSAGE_ID (0x77U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS { + NvBool bSave; + NvBool bUseVbios; + NvBool bVbiosCallSuccessful; +} NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES + * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES + */ + +/*! + * NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE + * + * This structure specifies resources in an execution partition + * + * computeSize[OUT] + * - NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* associated with this profile + * + * flags[OUT] + * - Bitmap of flags describing the profile NV2080_CTRL_GPU_COMPUTE_PROFILE_FLAG* + * + * gfxGpcCount[OUT] + * - Total Number of GFX Supporting GPCs in this partition + * + * gpcCount[OUT] + * - Total Number of GPCs in this partition (including GFX Supported GPCs) + * + * veidCount[OUT] + * - Number of VEIDs allocated to this profile + * + * smCount[OUT] + * - Number of SMs usable in this profile + */ +typedef struct NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE { + NvU8 computeSize; + NvU16 flags; + NvU32 gfxGpcCount; + NvU32 gpcCount; + NvU32 veidCount; + NvU32 smCount; + NvU32 physicalSlots; +} NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE; + +/*! + * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS + * + * This structure specifies resources in an execution partition + * + * profileCount[OUT] + * - Total Number of profiles filled + * + * profiles[OUT] + * - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles + */ +#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBBU) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS { + NvU32 profileCount; + NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE]; +} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBAU) + +typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS; + + + +/* + * NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE + * + * This command sets the ccu stream to enable/disable state. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE (0x20800abd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID (0xBDU) + +typedef struct NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS { + NvBool bStreamState; +} NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT + * + * Attach GPU to the external device. + * + * [in] bExtDevFound + * To enable GPIO interrupts. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT (0x20800abe) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID (0xBEU) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS { + NvBool bExtDevFound; +} NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS + * + * Optimize the Gsync timing parameters + * + * [in] timingParameters + * Timing parameters passed by client. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS (0x20800abf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID (0xBFU) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS { + NV_DECLARE_ALIGNED(NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS timingParameters, 8); +} NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS + * + * Get displayIDs supported by the display. + * + * [out] displayIds + * Associated display ID with head. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS (0x20800ac0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID" */ + +#define NV2080_MAX_NUM_HEADS 4 + +#define NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID (0xC0U) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS { + NvU32 displayIds[NV2080_MAX_NUM_HEADS]; +} NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC + * + * Set the Stereo sync for Gsync + * + * [in] slave + * Slave GPU head status. + * [in] localSlave + * Slave GPU head status but are not coupled. + * [in] master + * Master GPU head status. + * [in] regstatus + * Register status of status1 register. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC (0x20800ac1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID (0xC1U) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS { + NvU32 slave[NV2080_MAX_NUM_HEADS]; + NvU32 localSlave[NV2080_MAX_NUM_HEADS]; + NvU32 master[NV2080_MAX_NUM_HEADS]; + NvU32 regStatus; +} NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES + * + * Get vertical active lines for given head. + * + * [in] head + * For the headIdx which we need active. + * [out] vActiveLines + * Vertical active lines. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES (0x20800ac4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID (0xC4U) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS { + NvU32 headIdx; + NvU32 vActiveLines; +} NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID + * + * Verifies if this displayId is valid. + * + * [in] displays + * Displays given by the client + * + * [out] displayId + * DisplayId for the given display + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID (0x20800ac9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID (0xC9U) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS { + NvU32 displays; + NvU32 displayId; +} NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC + * + * Disable the raster sync gpio on the other P2060 GPU + * that's connected to master over Video bridge. + * + * [in] bEnableMaster + * If it is master gpu. + * + * [out] bRasterSyncGpioSaved + * If raster sync GPIO direction is saved or not. + * + * [in/out] bRasterSyncGpioDirection + * During save it gets the direction. + * In restores it sets the direction. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC (0x20800aca) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID (0xCAU) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS { + NvBool bEnableMaster; + NvBool bRasterSyncGpioSaved; + NvU32 bRasterSyncGpioDirection; +} NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS; + + + +/*! + * NV2080_CTRL_CMD_INTERNAL_FBSR_INIT + * + * Initialize FBSR on GSP to prepare for suspend-resume + * + * [in] hClient + * Handle to client of SYSMEM memlist object + * [in] hSysMem + * Handle to SYSMEM memlist object + * [in] bEnteringGcoffState + * Value of PDB_PROP_GPU_GCOFF_STATE_ENTERING + * [in] sysmemAddrOfSuspendResumeData + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_FBSR_INIT (0x20800ac2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID (0xC2U) + +typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS { + NvHandle hClient; + NvHandle hSysMem; + NvBool bEnteringGcoffState; + NV_DECLARE_ALIGNED(NvU64 sysmemAddrOfSuspendResumeData, 8); +} NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING + * + * Disable all the active channels during suspend + * Resume FIFO scheduling from GSP after resume on Kernel-RM + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING (0x20800ac3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS_MESSAGE_ID (0xC3U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS { + NvBool bDisableActiveChannels; +} NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB + * + * This command is used to get the amount of host reserved FB + * + * hostReservedFb [OUT] + * Amount of FB reserved for the host + * vgpuTypeId [IN] + * The Type ID for VGPU profile + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB (0x20800ac5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID (0xC5U) + +typedef struct NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS { + NV_DECLARE_ALIGNED(NvU64 hostReservedFb, 8); + NvU32 vgpuTypeId; +} NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD + * + * This command initiates brightc module state load. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD (0x20800ac6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_ACPI_DSM_READ_SIZE (0x1000) /* finn: Evaluated from "(4 * 1024)" */ + +#define NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID (0xC6U) + +typedef struct NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS { + NvU32 status; + NvU16 backLightDataSize; + NvU8 backLightData[NV2080_CTRL_ACPI_DSM_READ_SIZE]; +} NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS; + +/* + * NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL + * + * Returns number of active links allowed per IOCTRL + * + * [Out] numActiveLinksPerIoctrl + */ +#define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xC7U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS { + NvU32 numActiveLinksPerIoctrl; +} NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS; +#define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL (0x20800ac7U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */ +/* + * NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL + * + * Returns number of links per IOCTRL + * + * [Out] numLinksPerIoctrl + */ +#define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xC8U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS { + NvU32 numLinksPerIoctrl; +} NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS; +#define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL (0x20800ac8U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE + * + * Update the system control capability + * + * bIsSysCtrlSupported [IN] + If the system control is supported + * bIsPlatformLegacy [OUT] + If the platform is legacy + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE (0x20800acb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID (0xCBU) + +typedef struct NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS { + NvBool bIsSysCtrlSupported; + NvBool bIsPlatformLegacy; +} NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS; + +/*! + * Macros for PFM_REQ_HNDLR_STATE_SYNC data types. + */ +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_PMGR 0x00U +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_THERM 0x01U +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_SMBPBI 0x02U + +/*! + * Structure representing static data for a PFM_REQ_HNDLR_STATE_SYNC_SMBPBI. + */ +typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI { + /*! + * PFM sensor ID + */ + NvU32 sensorId; + + /*! + * PFM sensor limit value if required + */ + NvU32 limit; +} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI; + +/*! + * Structure of static information describing PFM_REQ_HNDLR_STATE_SYNC data types. + */ +typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA { + /*! + * @ref NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_ + */ + NvU8 type; + + /*! + * Type-specific information. + */ + union { + NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI smbpbi; + } data; +} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA; + +/*! + * Macros for PFM_REQ_HNDLR_STATE_SYNC flags for specific operation. + */ +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_PMGR_LOAD 0x00U +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_THERM_INIT 0x01U +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_CLEAR 0x02U +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_SET 0x03U + +/*! + * Structure of static information describing PFM_REQ_HNDLR_STATE_SYNC params. + */ +typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS { + /*! + * @ref NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_ + */ + NvU8 flags; + + /*! + * Type-specific information. + */ + NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA syncData; +} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC + * + * State sync with platform req handler and SMBPBI + * + * flags [IN] + * Flags that needs sync operation between physical and kernel + * + * syncData [IN] + * Sync payload data + * + */ +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC (0x20800acc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID (0xCCU) + +typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC + * + * State sync with platform req handler and SMBPBI + * + * flags [IN] + * Flags that needs sync operation between physical and kernel + * + * syncData [IN] + * Sync payload data + * + */ +#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC (0x20800acd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID (0xCDU) + +typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS; + +/*! + * Macros for NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE flag + */ +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_FORCED_OFF_STATUS 0x00U +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_STATUS 0x01U + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE + * + * Queries PM1 Forced off / PM1 Available status + * + * flag [IN] + * Fetch PM1 Forced off / PM1 Available status based on value. + * bStatus [OUT] + * PM1 Forced off / PM1 Available is true or false. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMETS + */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE (0x20800ace) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID (0xCEU) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS { + /*! + * Fetch PM1 Forced off / PM1 Available status based on value. + */ + NvU8 flag; + + /*! + * PM1 Forced off / PM1 Available status + */ + NvBool bStatus; +} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE + * + * Set PM1 state to enabled / disabled (boost clocks). + * + * bEnable [IN] + * NV_TRUE means enable PM1, NV_FALSE means disable. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE (0x20800acf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID (0xCFU) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS { + + /*! + * NV_TRUE means enable PM1, NV_FALSE means disable. + */ + NvBool bEnable; +} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT + * + * Updates EDPpeak Limit of GPU + * + * bEnable [IN] + * Enable or Reset the settings + * clientLimit [IN] + * Client requested limit + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + * NV_ERR_NOT_READY + */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT (0x20800ad0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID (0xD0U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS { + NvBool bEnable; + NvU32 clientLimit; +} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT + * + * Updates Target Temperature of GPU + * + * targetTemp [IN] + * Target Temperature Set from SBIOS + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT (0x20800ad1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID (0xD1U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS { + NvS32 targetTemp; +} NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE + * + * Enable / disable CTGP MODE + * + * bEnable [IN] + * Enable or Reset the settings + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE (0x20800ad2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID (0xD2U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS { + NvBool bEnable; +} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2 + * + * Configuration of the turbo v2 parameters for NVPCF-Turbo arb control + * + * ctgpOffsetmW [IN] + * TGP MODE Offset in mW + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2 (0x20800ad3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID (0xD3U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS { + NvU32 ctgpOffsetmW; +} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO + * + * Query VPstatese info. Get VPS PS2.0 support / get highest VP State Idx and requested VP State Idx + * + * bVpsPs20Supported [OUT] + * Reflects Vpstates PS20 support + * vPstateIdxHighest [OUT} + * Reflects Highest VPstate Idx + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO (0x20800ad4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID (0xD4U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS { + /*! + * Reflects Vpstates PS20 support + */ + NvBool bVpsPs20Supported; + + /*! + * Get highest VPState Idx from VBIOS + */ + NvU32 vPstateIdxHighest; +} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING + * + * Get vPstate mapping for requested pStateIdx + * + * pStateIdx [IN] + * Requested PState Idx + * vPstateIdx [OUT} + * Mapped VPstate Idx + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING (0x20800ad5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID (0xD5U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS { + /*! + * Requested PState Idx + */ + NvU32 pStateIdx; + + /*! + * Mapped VPstate Idx + */ + NvU32 vPstateIdxMapping; +} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE + * + * Set requested VPstate + * + * vPstateIdx [IN] + * VPstate Idx to be set + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE (0x20800ad6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID (0xD6U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS { + + /*! + * NV_TRUE means enable PM1, NV_FALSE means disable. + */ + NvU32 vPstateIdx; +} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE + * + * This command gets if GPU is in a proper state (P8 and engine idle) to be ready to enter RTD3 + * + * Possible status return values are: + * NV_OK Success + */ +#define NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE (0x2080a7d7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID (0xD7U) + +typedef struct NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS { + NvBool bIsGC6Satisfied; + NvBool bIsGCOFFSatisfied; +} NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS; + +/* + * This command unsets Dynamic Boost limit when nvidia-powerd is terminated unexpectedly. + */ +#define NV2080_CTRL_CMD_INTERNAL_PMGR_UNSET_DYNAMIC_BOOST_LIMIT (0x20800a7b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7B" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS + * + * This command is an internal command sent from Kernel RM to Physical RM + * to get number of secure channels supported on SEC2 and CE + * + * maxSec2SecureChannels [OUT] + * maxCeSecureChannels [OUT] + */ +#define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS (0x20800ad8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID (0xD8U) + +typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS { + NvU32 maxSec2SecureChannels; + NvU32 maxCeSecureChannels; +} NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_DEPENDENCY_CHECK + * + * This command checks if all the dependant modules to PRH have been initialized. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_DEPENDENCY_CHECK (0x20800a45) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x45" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS + * + * This command is an internal command sent from Kernel RM to Physical RM + * to disable the GPU system memory access after quiescing the GPU or + * re-enable sysmem access. + * + * bDisable [IN] + * If NV_TRUE the GPU is quiesced and system memory access is disabled . + * If NV_FALSE the GPU system memory access is re-enabled and the GPU is resumed. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS (0x20800adb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID (0xDBU) + +typedef struct NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS { + NvBool bDisable; +} NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_DISP_PINSETS_TO_LOCKPINS (0x20800adc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID (0xDCU) + +typedef struct NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS { + NvU32 pinSetIn; // in + NvU32 pinSetOut; // in + NvBool bMasterScanLock; // out + NvU32 masterScanLockPin; // out + NvBool bSlaveScanLock; // out + NvU32 slaveScanLockPin; // out +} NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_DETECT_HS_VIDEO_BRIDGE (0x20800add) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xDD" */ + +#define NV2080_CTRL_CMD_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL (0x20800ade) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID (0xDEU) + +typedef struct NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS { + NvU32 pinSet; // in + NvU32 gpioFunction; // out + NvU32 gpioPin; // out + NvBool gpioDirection; // out +} NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS; + +/* NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA + * + * This command sets up ACPI DDC Edid data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA (0x20800adf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID" */ + +/* From ACPI6.5 spec., the max size of EDID data from SBIOS(_DDC) is 512B */ +#define MAX_EDID_SIZE_FROM_SBIOS 512U + +typedef struct NV2080_CTRL_INTERNAL_EDID_DATA { + NvU32 status; + NvU32 acpiId; + NvU32 bufferSize; + NvU8 edidBuffer[MAX_EDID_SIZE_FROM_SBIOS]; +} NV2080_CTRL_INTERNAL_EDID_DATA; + +#define NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID (0xDFU) + +typedef struct NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS { + NvU32 tableLen; + NV2080_CTRL_INTERNAL_EDID_DATA edidTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS]; +} NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED + * + * This command intializes display ACPI child devices. + * This command accepts no parameters. + * + */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED (0x20800af0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF0" */ + +/* NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET (0x20800af1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF1" */ + +/* NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET (0x20800af2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF2" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS + * + * This structure provides the params for getting GPU Fabric Probe Internal + * Info from GSP to CPU RM + * + * numProbes[OUT] + * - Number of probe requests sent + */ +#define NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF4U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 numProbes, 8); +} NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO + * + * This command is used to get NV2080_CTRL_CMD_INTERNAL_GPU_FABRIC_PROBE_INFO_PARAMS + * from GSP to CPU RM. + * This command accepts NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS + * + */ +#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO (0x208001f4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS + * + * This structure provides the params for starting GPU Fabric Probe + * + * bwMode[IN] + * - Nvlink Bandwidth mode + * + * bLocalEgmEnabled[IN] + * - EGM Enablement Status that needs to be set in GSP-RM + */ +#define NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF5U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS { + NvU16 bwMode; + NvBool bLocalEgmEnabled; +} NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE + * + * This command is used to trigger start of GPU FABRIC PROBE PROCESS on GSP. + * This command accepts NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS + * + */ +#define NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE (0x208001f5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE + * + * This command is used to trigger stop of GPU FABRIC PROBE PROCESS on GSP. + * This command accepts no parameters + * + */ +#define NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE (0x208001f6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF6" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE + * + * This command is used to trigger suspend of GPU FABRIC PROBE PROCESS on GSP. + * This command accepts no parameters + * + */ +#define NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE (0x208001f7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF7" */ + + +/*! + * NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS + * + * This structure provides the params for resuming GPU Fabric Probe + * + * bwMode[IN] + * - Nvlink Bandwidth mode + */ +#define NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF8U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS { + NvU16 bwMode; +} NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE + * + * This command is used to trigger resume of GPU FABRIC PROBE PROCESS on GSP. + * This command accepts NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS + * + */ +#define NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE (0x208001f8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE + * + * This command is used to invalidate/reset GPU_FABRIC_PROBE_INFO on GSP. + * This command accepts no parameters + * + */ +#define NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE (0x208001f9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF9" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO + * + * This command is an internal command sent from Kernel RM to Physical RM + * to get static conf compute info + * + * bIsBar1Trusted: [OUT] + * Is BAR1 trusted to access CPR + * bIsPcieTrusted: [OUT] + * Is PCIE trusted to access CPR + */ +#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO (0x20800af3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0xF3U) + +typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS { + NvBool bIsBar1Trusted; + NvBool bIsPcieTrusted; +} NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS + * + * This command is an internal command sent from Kernel RM to Physical RM + * to derive SWL keys and IV masks for a given engine + * + * engineId: [IN] + * NV2080_ENGINE_TYPE_* for engine for which keys and IV mask should be derived + * ivMaskSet: [OUT] + * Set of IV masks for given engine + */ +#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS (0x20800ae1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE 3U +#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_KERNEL 0U +#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_USER 1U +#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_SCRUBBER 2U +#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT 3U +#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT 6U + +typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK { + NvU32 ivMask[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE]; +} NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK; + +#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS_MESSAGE_ID (0xE1U) + +typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS { + NvU32 engineId; + NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK ivMaskSet[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT]; +} NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS + * + * This command is an internal command sent from Kernel RM to Physical RM + * to derive LCE keys and IV masks for a given engine + * + * engineId: [IN] + * NV2080_ENGINE_TYPE_* for engine for which keys and IV mask should be derived + * ivMaskSet: [OUT] + * Set of IV masks for given engine + */ +#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS (0x20800ae2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS_MESSAGE_ID (0xE2U) + +typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS { + NvU32 engineId; + NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK ivMaskSet[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT]; +} NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_KEY + * + * This command handles key rotation for a given H2D key (and corresponding D2H key) + * by deriving new key on GSP and updating the key on relevant SEC2 or LCE. + * It also updates IVs for all channels using the key and conditionally re-enables them + * and notifies clients of key rotation status at the end. + * + * globalH2DKey : [IN] + * global h2d key to be rotated + * updatedEncryptIVMask: [OUT] + * Encrypt IV mask post IV key rotation for a given engine's kernel channel + * updatedDecryptIVMask: [OUT] + * Decrypt IV mask post IV key rotation for a given engine's kernel channel + */ +#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_KEYS (0x20800ae5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS_MESSAGE_ID (0xE5U) + +typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS { + NvU32 globalH2DKey; + NvU32 updatedEncryptIVMask[CC_AES_256_GCM_IV_SIZE_DWORD]; + NvU32 updatedDecryptIVMask[CC_AES_256_GCM_IV_SIZE_DWORD]; +} NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION + * + * This command RCs all channels that use the given key and have not reported + * idle via NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION yet. + * RM needs to RC such channels before going ahead with key rotation. + * + * globalH2DKey : [IN] + * global h2d key whose channels will be RCed + */ +#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION (0x20800ae6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID (0xE6U) + +typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS { + NvU32 exceptionType; + NvU32 globalH2DKey; +} NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE + * + * This control call can be used to set gpu state on GSP to accept client requests + * or to block client requests. + * This is a internal command sent from Kernel RM to Physical RM. + * + * bAcceptClientRequest:[IN] + * NV_TRUE : set gpu state to accept client work requests + * NV_FALSE: set gpu state to block client work requests + * + */ +#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE (0x20800ae7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS_MESSAGE_ID (0xE7U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS { + NvBool bAcceptClientRequest; +} NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY + * + * This control call can be used to set CC security policy on GSP. + * This is a internal command sent from Kernel RM to Physical RM. + * + * attackerAdvantage [IN] + * The minimum and maximum values for attackerAdvantage. + * The probability of an attacker successfully guessing the contents of + * an encrypted packet go up ("attacker advantage"). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY (0x20800ae8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID (0xE8U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS { + NV_DECLARE_ALIGNED(NvU64 attackerAdvantage, 8); +} NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS; + + +/*! + * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID + * + * This command is an internal command sent from Kernel RM to Physical RM + * to update the logical Uproc Id for the configuration. + * + * logicalUprocId [OUT] + */ +#define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID (0x20800aef) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS_MESSAGE_ID (0xEFU) + +typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS { + NvU8 logicalUprocId; +} NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS; + + + +/* + * NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP + * + * This command is used by CPU-RM to perform memory operations using GSP + * + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_TIMEOUT_RETRY + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP (0x20800afa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_MEMMGR_MEMORY_OP { + NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY = 0, + NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET = 1, +} NV2080_CTRL_MEMMGR_MEMORY_OP; + +typedef struct NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO { + /*! + * Base physical address of the surface + */ + NV_DECLARE_ALIGNED(NvU64 baseAddr, 8); + + /*! + * Size of the surface in bytes + */ + NV_DECLARE_ALIGNED(NvU64 size, 8); + + /*! + * Offset in bytes into the surface where read/write must happen + */ + NV_DECLARE_ALIGNED(NvU64 offset, 8); + + /*! + * Aperture where the surface is allocated + */ + NvU32 aperture; + + /*! + * CPU caching attribute of the surface + */ + NvU32 cpuCacheAttrib; +} NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO; + +#define CC_AES_256_GCM_AUTH_TAG_SIZE_BYTES (0x10U) /* finn: Evaluated from "(128 / 8)" */ + +#define NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID (0xFAU) + +typedef struct NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS { + + /*! + * Source surface info + */ + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO src, 8); + + /*! + * Authentication tag if data is encrypted + */ + NvU8 authTag[CC_AES_256_GCM_AUTH_TAG_SIZE_BYTES]; + + /*! + * Destination surface info + */ + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO dst, 8); + + /*! + * Size of the data to be transferred + */ + NV_DECLARE_ALIGNED(NvU64 transferSize, 8); + + /*! + * To be set in case of memset + */ + NvU32 value; + + /*! + * Memory op to be performed + */ + NV2080_CTRL_MEMMGR_MEMORY_OP memop; +} NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG + * + * This command is an internal command sent from Kernel RM to Physical RM + * to get local GPU's ATS config + * + * addrSysPhys : [OUT] + * System Physical Address + * addrWidth : [OUT] + * Address width value + * mask : [OUT] + * Mask value + * maskWidth : [OUT] + * Mask width value + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG (0x20800afb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID (0xFBU) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS { + NV_DECLARE_ALIGNED(NvU64 addrSysPhys, 8); + NvU32 addrWidth; + NvU32 mask; + NvU32 maskWidth; +} NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG + * + * This command is an internal command sent from Kernel RM to Physical RM + * to set peer ATS config using the parameters passed in. + * + * peerId : [IN] + * Peer Id of the peer for which ATS config is to be programmed + * addrSysPhys : [IN] + * System Physical Address + * addrWidth : [IN] + * Address width value + * mask : [IN] + * Mask value + * maskWidth : [IN] + * Mask width value + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG (0x20800afc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID (0xFCU) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS { + NvU32 peerId; + NV_DECLARE_ALIGNED(NvU64 addrSysPhys, 8); + NvU32 addrWidth; + NvU32 mask; + NvU32 maskWidth; +} NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO + * + * Get GPU EDPpeak Limit information + * + * limitMin [OUT] + * Minimum allowed limit value on EDPp policy on both AC and DC + * limitRated [OUT] + * Rated/default allowed limit value on EDPp policy on AC + * limitMax [OUT] + * Maximum allowed limit value on EDPp policy on AC + * limitCurr [OUT] + * Current resultant limit effective on EDPp policy on AC and DC + * limitBattRated [OUT] + * Default/rated allowed limit on EDPp policy on DC + * limitBattMax [OUT] + * Maximum allowed limit on EDPp policy on DC + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO (0x20800afd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID (0xFDU) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS { + NvU32 limitMin; + NvU32 limitRated; + NvU32 limitMax; + NvU32 limitCurr; + NvU32 limitBattRated; + NvU32 limitBattMax; +} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA + * + * @brief Initialize/Destroy RM User Shared Data memory mapping on physical RM + * + * @param[in] bInit If this is an init or a destroy request + * @param[in] physAddr Physical address of memdesc to link physical to kernel + * 0 to de-initialize + * + * @return NV_OK on success + * @return NV_ERR_ otherwise + */ +#define NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID (0xFEU) + +typedef struct NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS { + NvBool bInit; + NV_DECLARE_ALIGNED(NvU64 physAddr, 8); +} NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA (0x20800afe) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL + * + * @brief Set mask of data to be polled on physical for RUSD + * + * @param[in] polledDataMask Bitmask of data requested, defined in cl00de + * @param[in] pollIntervalMs Requested polling interval, in ms + * + * @return NV_OK on success + * @return NV_ERR_ otherwise + */ +#define NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID (0xFFU) + +typedef struct NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS { + NV_DECLARE_ALIGNED(NvU64 polledDataMask, 8); + NvU32 pollIntervalMs; +} NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL (0x20800aff) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS + * + * This structure provides the params for starting GPU Fabric Probe + * + * tracepointMask[IN] + * - tracepoint selection filter + * bufferAddr[IN] + * - physical address of tracing buffer for VGPU + * bufferSize[IN] + * - size of gsp side logging buffer + * bufferWatermark[IN] + * - entry threshold for GSP to issue RPC of logged entries to kernel RM + * flag[IN] + * - indicates which operation to perform + */ +#define NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS_MESSAGE_ID (0xE3U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 tracepointMask, 8); + NV_DECLARE_ALIGNED(NvU64 bufferAddr, 8); + NvU32 bufferSize; + NvU32 bufferWatermark; + NvU8 flag; +} NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS; + +/*! + * Macros for INTERNAL_CONTROL_GSP_TRACE flags for specific operation. + */ +#define NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_START_KEEP_OLDEST 0x00U +#define NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_START_KEEP_NEWEST 0x01U +#define NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_STOP 0x02U + +/* + * NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE + * + * This command is used to start GSP-RM trace tool. + * This command accepts NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS + * + */ +#define NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE (0x208001e3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES + * + * @brief get state (enabled/disabled) of SEC2 classes + * + * + * @return NV_OK on success + * @return NV_ERR_ otherwise + */ +#define NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS_MESSAGE_ID (0xAFU) + +typedef struct NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS { + NvBool bMaxwellSec2Enabled; + NvBool bNv95A1TsecEnabled; + NvBool bHopperSec2WorkLaunchAEnabled; +} NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES (0x20800aaf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS_MESSAGE_ID" */ + + +/*! + * @ref NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_SETUP_BIND + */ +#define NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_SETUP_BIND (0x20800ae4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID (0xE4U) + +typedef NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS; + +/*! + * NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER + * + * @brief Notify the offloaded RM that CPU-RM enters the power management cycle. + * + * bInPMTransition : [IN] + * newPMLevel : [IN] + * New PM Level : NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_[0-7] + * + * @return NV_OK on success + * @return NV_ERR_ otherwise + */ +#define NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS_MESSAGE_ID (0xE9U) + +typedef struct NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS { + NvBool bInPMTransition; + NvU32 newPMLevel; +} NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS; +#define NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER (0x20800ae9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS_MESSAGE_ID" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_FATAL_RECOVERY + * + * This command is used to perform recovery actions after the fabric has been + * idled due to a fatal nvlink error. + * This command accepts no parameters. + * + * bSuccessful + * NV_TRUE if recovery was successful, NV_FALSE otherwise + */ +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY (0x20800aea) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS_MESSAGE_ID (0xEAU) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS { + NvBool bSuccessful; +} NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP + * + * @brief To get the free heap size of GSP-RM + * + * freeHeapSize : [OUT] + * + * @return NV_OK + */ +#define NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS_MESSAGE_ID (0xEBU) + +typedef struct NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS { + NV_DECLARE_ALIGNED(NvU64 freeHeapSize, 8); +} NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP (0x20800aeb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_GPU_SET_ILLUM + * + * This command sets a new value for the specified Illumination control attribute. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID (0xECU) + +typedef struct NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS { + NvU32 attribute; + NvU32 value; +} NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_GPU_SET_ILLUM (0x20800aecU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID" */ +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR + * + * @brief NVIDIA RTX 5000 (GP180 SKU500) Windows-specific war + * to pull gpio19 (stereo pin) low for bug3362661. + * + * [in] bApplyStereoPinAlwaysHiWar + * If need to driver stereo pin(GPIO19) low(_IO_INPUT) + * + * @return NV_OK on success + * @return NV_ERR_ otherwise + */ +#define NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS_MESSAGE_ID (0xEDU) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS { + NvBool bApplyStereoPinAlwaysHiWar; +} NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR (0x20800aed) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS_MESSAGE_ID" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM + * + * Returns the maximum number of HSHUBs in a shim instance. + * + * maxHshubs[OUT] + * The maximum number of HSHUBs in a shim instance. + * + * @return NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM (0x20800a79) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS_MESSAGE_ID (0x79U) + +typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS { + NvU32 maxHshubs; +} NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS; + + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_RASTER_MODE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS { + NvU32 rasterSyncDecodeMode; +} NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE (0x20800a14) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS + * + * This is an internal command sent from kernel-RM to physical-RM to retrieve GPU PF BAR1 SPA + * BAR1 SPA is required for BAR1 mapping in Direct NIC case for DMA(Direct Memory Access) of FB. + * + * spaValue[OUT] + * - BAR1 SPA of GPU PF + */ +#define NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS_MESSAGE_ID (0xEEU) + +typedef struct NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS { + NV_DECLARE_ALIGNED(NvU64 spaValue, 8); +} NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_PF_BAR1_SPA (0x20800aee) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_NVLINK_PEER + * + * This command is used to enable RM NVLink enabled peer state. + * Note: This just updates the RM state. To reflect the state in the registers, + * use NV2080_CTRL_CMD_NVLINK_SET_NVLINK_PEER + * + * [in] peerMask + * Mask of Peer IDs for which USE_NVLINK_PEER needs to be enabled + * [in] bEnable + * Whether the bit needs to be set or unset + * + * Possible status values returned are: + * NV_OK + * If the USE_NVLINK_PEER bit was enabled successfully + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip, or + * If unsetting USE_NVLINK_PEER bit is not supported + * + */ +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_NVLINK_PEER (0x20800a21U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID (0x21U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS { + NvU32 peerMask; + NvBool bEnable; +} NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS; + +/* + * NVLINK Link states + * These should ALWAYS match the nvlink core library defines in nvlink.h + */ +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_OFF 0x00U +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_HS 0x01U +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SAFE 0x02U +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_FAULT 0x03U +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RECOVERY 0x04U +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_FAIL 0x05U +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DETECT 0x06U +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RESET 0x07U +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ENABLE_PM 0x08U +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_PM 0x09U +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SLEEP 0x0AU +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SAVE_STATE 0x0BU +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RESTORE_STATE 0x0CU +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_PRE_HS 0x0EU +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_ERR_DETECT 0x0FU +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_LANE_DISABLE 0x10U +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_LANE_SHUTDOWN 0x11U +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_TRAFFIC_SETUP 0x12U +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITPHASE1 0x13U +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITNEGOTIATE 0x14U +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_POST_INITNEGOTIATE 0x15U +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITOPTIMIZE 0x16U +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_POST_INITOPTIMIZE 0x17U +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_HEARTBEAT 0x18U +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_CONTAIN 0x19U +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITTL 0x1AU +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITPHASE5 0x1BU +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ALI 0x1CU +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ACTIVE_PENDING 0x1DU +#define NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INVALID 0xFFU + +/* + * NVLINK TX Sublink states + * These should ALWAYS match the nvlink core library defines in nvlink.h + */ +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_HS 0x00U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SINGLE_LANE 0x04U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_LOW_POWER 0x04U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_TRAIN 0x05U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SAFE 0x06U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_OFF 0x07U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE 0x08U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE_DISABLE 0x09U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_DATA_READY 0x0AU +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_EQ 0x0BU +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_PRBS_EN 0x0CU +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_POST_HS 0x0DU + +/* + * NVLINK RX Sublink states + * These should ALWAYS match the nvlink core library defines in nvlink.h + */ +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_HS 0x00U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SINGLE_LANE 0x04U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_LOW_POWER 0x04U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_TRAIN 0x05U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SAFE 0x06U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_OFF 0x07U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_RXCAL 0x08U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_INIT_TERM 0x09U + +/* + * Link training seed values + * These should ALWAYS match the values defined in nvlink.h + */ +#define NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_NUM 6U +#define NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_BUFFER_SIZE (0x7U) /* finn: Evaluated from "NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_NUM + 1" */ + +// NVLINK callback types +#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_DL_LINK_MODE 0x00U +#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_DL_LINK_MODE 0x01U +#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_TL_LINK_MODE 0x02U +#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_TL_LINK_MODE 0x03U +#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_TX_SUBLINK_MODE 0x04U +#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_TX_SUBLINK_MODE 0x05U +#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_MODE 0x06U +#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_MODE 0x07U +#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_DETECT 0x08U +#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_DETECT 0x09U +#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_WRITE_DISCOVERY_TOKEN 0x0AU +#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_READ_DISCOVERY_TOKEN 0x0BU +#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_TRAINING_COMPLETE 0x0CU +#define NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_UPHY_LOAD 0x0DU + +/* + * Structure to store the GET_DL_MODE callback params. + * mode + * The current Nvlink DL mode + */ +typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS { + NvU32 mode; +} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS; + +/* + * Structure to store the SET_DL_LINK_MODE callback OFF params + * seedData + * The output seed data + */ +typedef struct NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS { + NvU32 seedData[NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_BUFFER_SIZE]; +} NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS; + +/* + * Structure to store the SET_DL_LINK_MODE callback PRE_HS params + * remoteDeviceType + * The input remote Device Type + * ipVerDlPl + * The input DLPL version + */ +typedef struct NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS { + NvU32 remoteDeviceType; + NvU32 ipVerDlPl; +} NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS; + +/* + * Structure to store SET_DL_LINK_MODE callback INIT_PHASE1 params + * seedData[] + * The input seed data + */ +typedef struct NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS { + NvU32 seedData[NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_BUFFER_SIZE]; +} NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS; + +/* + * Structure to store the Nvlink Remote and Local SID info + * remoteSid + * The output remote SID + * remoteDeviceType + * The output remote Device Type + * remoteLinkId + * The output remote link ID + * localSid + * The output local SID + */ +typedef struct NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO { + NV_DECLARE_ALIGNED(NvU64 remoteSid, 8); + NvU32 remoteDeviceType; + NvU32 remoteLinkId; + NV_DECLARE_ALIGNED(NvU64 localSid, 8); +} NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO; + +/* + * Structure to store the SET_DL_LINK_MODE callback POST_INITNEGOTIATE params + * bInitnegotiateConfigGood + * The output bool if the config is good + * remoteLocalSidInfo + * The output structure containing the Nvlink Remote/Local SID info + */ +typedef struct NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS { + NvBool bInitnegotiateConfigGood; + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO remoteLocalSidInfo, 8); +} NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS; + +/* + * Structure to store the SET_DL_LINK_MODE callback POST_INITOPTIMIZE params + * bPollDone + * The output bool if the polling has finished + */ +typedef struct NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS { + NvBool bPollDone; +} NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS; + +/* + * Structure to store the SET_DL_LINK_MODE callback params + * mode + * The input nvlink state to set + * bSync + * The input sync boolean + * linkMode + * The input link mode to be set for the callback + */ +typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 mode, 8); + NvBool bSync; + NvU32 linkMode; + union { + NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS linkModeOffParams; + NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS linkModePreHsParams; + NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS linkModeInitPhase1Params; + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS linkModePostInitNegotiateParams, 8); + NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS linkModePostInitOptimizeParams; + } linkModeParams; +} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS; + +/* + * Structure to store the GET_TL_MODE callback params. + * mode + * The current Nvlink TL mode + */ +typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS { + NvU32 mode; +} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS; + +/* + * Structure to store the SET_TL_LINK_MODE callback params + * mode + * The input nvlink mode to set + * bSync + * The input sync boolean + */ +typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 mode, 8); + NvBool bSync; +} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS; + +/* + * Structure to store the GET_RX/TX_SUBLINK_MODE callback params + * sublinkMode + * The current Sublink mode + * sublinkSubMode + * The current Sublink sub mode + */ +typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS { + NvU32 sublinkMode; + NvU32 sublinkSubMode; +} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS; + +/* + * Structure to store the SET_TL_LINK_MODE callback params + * mode + * The input nvlink mode to set + * bSync + * The input sync boolean + */ +typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 mode, 8); + NvBool bSync; +} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS; + +/* + * Structure to store the SET_RX_SUBLINK_MODE callback params + * mode + * The input nvlink mode to set + * bSync + * The input sync boolean + */ +typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 mode, 8); + NvBool bSync; +} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS; + +/* + * Structure to store the GET_RX_SUBLINK_DETECT callback params + * laneRxdetStatusMask + * The output RXDET per-lane status mask + */ +typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS { + NvU32 laneRxdetStatusMask; +} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS; + +/* + * Structure to store the SET_RX_DETECT callback params + * bSync + * The input bSync boolean + */ +typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS { + NvBool bSync; +} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS; + +/* + * Structure to store the RD_WR_DISCOVERY_TOKEN callback params + * ipVerDlPl + * The input DLPL version + * token + * The output token + */ +typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS { + NvU32 ipVerDlPl; + NV_DECLARE_ALIGNED(NvU64 token, 8); +} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS; + +/* + * Structure to store the GET_UPHY_LOAD callback params + * bUnlocked + * The output unlocked boolean + */ +typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS { + NvBool bUnlocked; +} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS; + +/* + * Structure to store the Union of Callback params + * type + * The input type of callback to be executed + */ +typedef struct NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE { + NvU8 type; + union { + NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS getDlLinkMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS setDlLinkMode, 8); + NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS getTlLinkMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS setTlLinkMode, 8); + NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS getTxSublinkMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS setTxSublinkMode, 8); + NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS getRxSublinkMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS setRxSublinkMode, 8); + NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS getRxSublinkDetect; + NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS setRxSublinkDetect; + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS writeDiscoveryToken, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS readDiscoveryToken, 8); + NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS getUphyLoad; + } callbackParams; +} NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE; + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_CORE_CALLBACK + * + * Generic NvLink callback RPC to route commands to GSP + * + * [In] linkdId + * ID of the link to be used + * [In/Out] callBackType + * Callback params + */ +#define NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID (0x24U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS { + NvU32 linkId; + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE callbackType, 8); +} NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_CORE_CALLBACK (0x20800a24U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID + * + * Update Remote and Local Sid info via GSP + * + * [In] linkId + * ID of the link to be used + * [Out] remoteLocalSidInfo + * The output structure containing the Nvlink Remote/Local SID info + */ +#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID (0x25U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS { + NvU32 linkId; + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO remoteLocalSidInfo, 8); +} NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID (0x20800a25U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_ALI_ENABLED + * + * Returns if ALI is enabled + * + * [Out] bEnableAli + * Output boolean for ALI enablement + */ +#define NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID (0x29U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS { + NvBool bEnableAli; +} NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_ALI_ENABLED (0x20800a29U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_TYPE_PROGRAM 0x0U +#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_TYPE_RESET 0x1U + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_HSHUB_MUX + * + * Generic Hshub Mux Update RPC to route commands to GSP + * + * [In] updateType + * HSHUB Mux update type to program or reset Mux + * [In] bSysMem + * Boolean to differentiate between sysmen and peer mem + * [In] peerMask + * Mask of peer IDs. Only parsed when bSysMem is false + */ +#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID (0x42U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS { + NvBool updateType; + NvBool bSysMem; + NvU32 peerMask; +} NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_HSHUB_MUX (0x20800a42U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER + * + * Performs all the necessary actions required before setting a peer on NVLink + * + * [In] peerId + * Peer ID which will be set on NVLink + * [In] peerLinkMask + * Mask of links that connects the given peer + * [In] bNvswitchConn + * Is the GPU connected to NVSwitch + */ +#define NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID (0x4EU) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS { + NvU32 peerId; + NV_DECLARE_ALIGNED(NvU64 peerLinkMask, 8); + NvBool bEgmPeer; + NvBool bNvswitchConn; +} NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER (0x20800a4eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER + * + * Performs all the necessary actions required after setting a peer on NVLink + * + * [In] peerMask + * Mask of Peer IDs which has been set on NVLink + */ +#define NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID (0x50U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS { + NvU32 peerMask; +} NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER (0x20800a50U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_LOG_OOB_XID + * + * Log an XID message to OOB. + * + * xid [in] + * The XID number of the message. + * + * message [in] + * The text message, including the NULL terminator. + * + * len [in] + * The length, in bytes, of the text message, excluding the NULL terminator. + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_INTERNAL_LOG_OOB_XID (0x20800a56U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS_MESSAGE_ID" */ + +#define NV2080_INTERNAL_OOB_XID_MESSAGE_BUFFER_SIZE (81U) + +#define NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS_MESSAGE_ID (0x56U) + +typedef struct NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS { + NvU32 xid; + NvU8 message[NV2080_INTERNAL_OOB_XID_MESSAGE_BUFFER_SIZE]; + NvU32 len; +} NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS; + +#define NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_SYSMEM 0x1U +#define NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_PEER 0x2U + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING + * + * Performs all the necessary actions required to remove NVLink mapping (sysmem or peer or both) + * + * [In] mapTypeMask + * Remove NVLink mapping for the given map types (sysmem or peer or both) + * [In] peerMask + * Mask of Peer IDs which needs to be removed on NVLink + * Only parsed if mapTypeMask accounts peer + * [In] bL2Entry + * Is the peer removal happening because links are entering L2 low power state? + * Only parsed if mapTypeMask accounts peer + */ +#define NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID (0x5FU) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS { + NvU32 mapTypeMask; + NvU32 peerMask; + NvBool bL2Entry; +} NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING (0x20800a5fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE + * + * Performs all the necessary actions required to save/restore HSHUB state during NVLink L2 entry/exit + * + * [In] bSave + * Whether this is a save/restore operation + * [In] linkMask + * Mask of links for which HSHUB config registers need to be saved/restored + */ +#define NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID (0x62U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS { + NvBool bSave; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK linkMask, 8); +} NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE (0x20800a62U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SET (0x00000000) +#define NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SAVE (0x00000001) +#define NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_RESTORE (0x00000002) + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_BUFFERREADY + * + * Performs all the necessary actions required to save/restore bufferready state during NVLink L2 entry/exit + * + * [In] flags + * Whether to set, save or restore bufferready + * [In] bSysmem + * Whether to perform the operation for sysmem links or peer links + * [In] peerLinkMask + * Mask of peer links for which bufferready state need to be set/saved/restored + */ +#define NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID (0x64U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS { + NvU32 flags; + NvBool bSysmem; + NV_DECLARE_ALIGNED(NvU64 peerLinkMask, 8); +} NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_BUFFERREADY (0x20800a64U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG + * + * Performs all the necessary actions required to update the current Nvlink configuration + * + * [out] bNvlinkSysmemEnabled + * Whether sysmem nvlink support was enabled + */ +#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID (0x78U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS { + NvBool bNvlinkSysmemEnabled; +} NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG (0x20800a78U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK + * + * Synchronizes the peerLinkMask between CPU-RM and GSP-RM + * + * [In] gpuInst + * Gpu instance + * [In] peerLinkMask + * Mask of links to the given peer GPU + */ +#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID (0x7DU) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS { + NvU32 gpuInst; + NV_DECLARE_ALIGNED(NvU64 peerLinkMask, 8); +} NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK (0x20800a7dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION + * + * Updates the remote connection information for a link + * + * [In] linkId + * Id of the link to be used + * [In] bConnected + * Boolean that tracks whether the link is connected + * [In] remoteDeviceType + * Tracks whether the remote device is switch/gpu/ibmnpu/tegra + * [In] remoteLinkNumber + * Tracks the link number for the connected remote device + */ +#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID (0x82U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS { + NV_DECLARE_ALIGNED(NvU64 remoteDeviceType, 8); + NV_DECLARE_ALIGNED(NvU64 remoteChipSid, 8); + NvU32 linkId; + NvU32 laneRxdetStatusMask; + NvU32 remoteLinkNumber; + NvU32 remotePciDeviceId; + NvU32 remoteDomain; + NvU8 remoteBus; + NvU8 remoteDevice; + NvU8 remoteFunction; + NvBool bConnected; +} NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION (0x20800a82U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY + * + * Enable links post topology via GSP + * + * [In] linkMask + * Mask of links to enable + * [Out] initializedLinks + * Mask of links that were initialized + */ +#define NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID (0x83U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS { + NvU32 linkMask; + NvU32 initializedLinks; +} NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY (0x20800a83U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI + * + * [In] linkMask + * Mask of enabled links to train + * [In] bSync + * The input sync boolean + */ +#define NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID (0x84U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS { + NvU32 linkMask; + NvBool bSync; +} NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI (0x20800a84U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE 64 + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET + * + * Get link mask post Rx detection + * + * [Out] postRxDetLinkMask + * Mask of links discovered + * [Out] laneRxdetStatusMask + * RXDET per-lane status mask + */ +#define NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID (0x85U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS { + NV_DECLARE_ALIGNED(NvU64 postRxDetLinkMask, 8); + NvU32 laneRxdetStatusMask[NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE]; +} NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET (0x20800a85U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_LINK_TRAIN_ALI + * + * [In] linkMask (This field will be deprecated in the future, please use links) + * Mask of enabled links to train + * [In] links + * Mask of enabled links to train + * [In] bSync + * The input sync boolean + */ +#define NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID (0x86U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS { + NvU32 linkMask; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8); + NvBool bSync; +} NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_LINK_TRAIN_ALI (0x20800a86U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID" */ + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES { + NvBool bValid; + NvU8 linkId; + NvU32 ioctrlId; + NvU8 pllMasterLinkId; + NvU8 pllSlaveLinkId; + NvU32 ipVerDlPl; +} NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES; + +#define NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_INVALID_TIME_MS 0 +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO + * + * [Out] ioctrlMask + * Mask of IOCTRLs discovered from PTOP device info table + * [Out] ioctrlNumEntries + * Number of IOCTRL entries in the PTOP device info table + * [Out] ioctrlSize + * Maximum number of entries in the PTOP device info table + * [Out] discoveredLinks + * Mask of links discovered from all the IOCTRLs + * [Out] ipVerNvlink + * IP revision of the NVLink HW + * [Out] maxSupportedLinks + * Maximum number of links supported for a given arch + * [Out] linkInfo + * Per link information + * [Out] probeRequestTimeMs + * nominal time needed for a probe request + * [Out] linkStateChangeTimeMs + * max amount of time needed for a link to transition states + */ + +#define NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID (0x87U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS { + NvU32 ioctrlMask; + NvU8 ioctrlNumEntries; + NvU32 ioctrlSize; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK discoveredLinks, 8); + NvU32 ipVerNvlink; + NvU32 maxSupportedLinks; + NvU32 probeRequestTimeMs; + NvU32 linkStateChangeTimeMs; + NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES linkInfo[NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE]; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS supportedCounterMask, 8); +} NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO (0x20800a87U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_NVLINK_MAX_LINKS_PER_IOCTRL_SW 6U + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES { + NvU32 ipVerIoctrl; + NvU32 ipVerMinion; +} NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES; + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO + * + * [In] ioctrlIdx + * IOCTRL index + * [Out] PublicId + * PublicId of the IOCTRL discovered + * [Out] localDiscoveredLinks + * Mask of discovered links local to the IOCTRL + * [Out] localGlobalLinkOffset + * Global link offsets for the locally discovered links + * [Out] ioctrlDiscoverySize + * IOCTRL table size + * [Out] numDevices + * Number of devices discovered from the IOCTRL + * [Out] deviceIpRevisions + * IP revisions for the devices discovered in the IOCTRL + */ + +#define NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID (0x8EU) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS { + NvU32 ioctrlIdx; + NvU32 PublicId; + NvU32 localDiscoveredLinks; + NvU32 localGlobalLinkOffset; + NvU32 ioctrlDiscoverySize; + NvU8 numDevices; + NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES ipRevisions; +} NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO (0x20800a8eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_LINK_SPEED + * + * Program NVLink Speed from OS/VBIOS + * + * [In] bPlatformLinerateDefined + * Whether line rate is defined in the platform + * [In] platformLineRate + * Platform defined line rate + * [Out] nvlinkLinkSpeed + * The line rate that was programmed for the links + */ +#define NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID (0x8FU) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS { + NvBool bPlatformLinerateDefined; + NvU32 platformLineRate; + NvU32 nvlinkLinkSpeed; +} NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_LINK_SPEED (0x20800a8fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_ARE_LINKS_TRAINED + * + * [In] linkMask + * Mask of links whose state will be checked + * [In] bActiveOnly + * The input boolean to check for Link Active state + * [Out] bIsLinkActive + * Boolean array to track if the link is trained + */ +#define NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID (0x90U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK linkMask, 8); + NvBool bActiveOnly; + NvBool bIsLinkActive[NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE]; +} NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_ARE_LINKS_TRAINED (0x20800a90U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_ASSERT (0x00000000) +#define NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_DEASSERT (0x00000001) +#define NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_TOGGLE (0x00000002) + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_RESET_LINKS + * + * [In] linkMask + * Mask of links which need to be reset + * [In] flags + * Whether to assert, de-assert or toggle the Nvlink reset + */ + +#define NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID (0x91U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS { + NvU32 linkMask; + NvU32 flags; +} NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_RESET_LINKS (0x20800a91U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS + * + * [In] linkMask + * Mask of links for which DL interrrupts need to be disabled + */ +#define NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID (0x92U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS { + NvU32 linkMask; +} NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS (0x20800a92U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID" */ + +/* + * Structure to store the GET_LINK_AND_CLOCK__INFO params + * + * [Out] bLinkConnectedToSystem + * Boolean indicating sysmem connection of a link + * [Out] bLinkConnectedToPeer + * Boolean indicating peer connection of a link + * [Out] bLinkReset + * Whether the link is in reset + * [Out] subLinkWidth + * Number of lanes per sublink + * [Out] linkState + * Mode of the link + * [Out] txSublinkState + * Tx sublink state + * [Out] rxSublinkState + * Rx sublink state + * [Out] bLaneReversal + * Boolean indicating if a link's lanes are reversed + * [Out] nvlinkLinkClockKHz + * Link clock value in KHz + * [Out] nvlinkLineRateMbps + * Link line rate in Mbps. This is on a per Lane Basis. + * [Out] nvlinkLinkClockMhz + * Link clock in MHz + * [Out] nvlinkLinkDataRateKiBps + * Link Data rate in KiBps. This is on a per Link Basis. + * [Out] nvlinkRefClkType + * Current Nvlink refclk source + * [Out] nvlinkReqLinkClockMhz + * Requested link clock value + * [Out] nvlinkMinL1Threshold + * Requested link Min L1 Threshold + * [Out] nvlinkMaxL1Threshold + * Requested link Max L1 Threshold + * [Out] nvlinkL1ThresholdUnits + * Requested link L1 Threshold Units + * [Out] nvlpwIdx + * Nvlpw Index for link + */ +typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES { + NvBool bLinkConnectedToSystem; + NvBool bLinkConnectedToPeer; + NvBool bLinkReset; + NvU8 subLinkWidth; + NvU32 linkState; + NvU32 txSublinkState; + NvU32 rxSublinkState; + NvBool bLaneReversal; + NvU32 nvlinkLinkClockKHz; + NvU32 nvlinkLineRateMbps; + NvU32 nvlinkLinkClockMhz; + NvU32 nvlinkLinkDataRateKiBps; + NvU8 nvlinkRefClkType; + NvU32 nvlinkReqLinkClockMhz; + NvU32 nvlinkMinL1Threshold; + NvU32 nvlinkMaxL1Threshold; + NvU32 nvlinkL1ThresholdUnits; + NvU32 nvlpwIdx; +} NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES; + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO + * + * [In] linkMask + * Mask of enabled links to loop over + * [Out] enabledNvlpwMask + * mask of nvlpw indices available + * [Out] nvlinkRefClkSpeedKHz + * Ref clock value n KHz + * [Out] linkInfo + * Per link information + */ +#define NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID (0x93U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 linkMask, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8); + NV_DECLARE_ALIGNED(NvU64 enabledNvlpwMask, 8); + NvU32 nvlinkRefClkSpeedKHz; + NvBool bSublinkStateInst; // whether instantaneous sublink state is needed + NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES linkInfo[NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE]; +} NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO (0x20800a93U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM + * + * Updates the HSHUB sysmem config resgister state to reflect sysmem NVLinks + * + * [In] sysmemLinkMask + * Mask of discovered sysmem NVLinks + */ +#define NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID (0x94U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS { + NvU32 sysmemLinkMask; +} NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM (0x20800a94U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS + * + * Process NVLink forced configurations which includes setting of HSHUB and memory system + * + * [In] bLegacyForcedConfig + * Tracks whether the forced config is legacy forced config or chiplib config + * [Out] bOverrideComputePeerMode + * Whether compute peer mode was enabled + * [In] phase + * Only applicable when bLegacyForcedConfig is true + * Tracks the set of registers to program from the NVLink table + * [In] linkConnection + * Array of chiplib configurations + */ +#define NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID (0x95U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS { + NvBool bLegacyForcedConfig; + NvBool bOverrideComputePeerMode; + NvU32 phase; + NvU32 linkConnection[NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE]; +} NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS (0x20800a95U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS + * + * Sync the NVLink lane shutdown properties with GSP-RM + * + * [In] bLaneShutdownOnUnload + * Whether nvlink shutdown should be triggered on driver unload + */ +#define NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID (0x96U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS { + NvBool bLaneShutdownOnUnload; +} NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS (0x20800a96U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS + * + * Enable ATS functionality related to NVLink sysmem if hardware support is available + * + * [In] notUsed + */ +#define NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID (0x97U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS { + NvU32 notUsed; +} NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS (0x20800a97U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK + * + * Get the mask of Nvlink links connected to system + * + * [Out] sysmemLinkMask + * Mask of Nvlink links connected to system + */ +#define NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID (0xABU) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS { + NvU32 sysmemLinkMask; +} NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK (0x20800aabU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO + * + * Send CMC gsplite the address and size of log buffer allocated on sysmem + * + * [In] PublicId + * ID of the gsplite engine + * [In] logBufferSize + * Size of the log buffer allocated on sysmem + * [In] logBufferAddr + * Start address of the log buffer + */ +#define NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS_MESSAGE_ID (0x89U) + +typedef struct NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS { + NvU32 PublicId; + NV_DECLARE_ALIGNED(NvU64 logBufferSize, 8); + NV_DECLARE_ALIGNED(NvU64 logBufferAddr, 8); +} NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO (0x20800a89U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_HFRP_INSTANCE_SIZE 5 + +/* + * NV2080_CTRL_CMD_INTERNAL_GPU_GET_HFRP_INFO + * + * This command retrives HFRP info from physical RM + * + * [Out] hfrpPrivBase + * HFRP device PRIV base + * [Out] hfrpIntrCtrlReg + * HFRP intr control base + * + */ +#define NV2080_CTRL_INTERNAL_GPU_GET_HFRP_INFO_PARAMS_MESSAGE_ID (0x7AU) + +typedef struct NV2080_CTRL_INTERNAL_GPU_GET_HFRP_INFO_PARAMS { + NvU32 hfrpPrivBase[NV2080_CTRL_INTERNAL_HFRP_INSTANCE_SIZE]; + NvU32 hfrpIntrCtrlReg[NV2080_CTRL_INTERNAL_HFRP_INSTANCE_SIZE]; +} NV2080_CTRL_INTERNAL_GPU_GET_HFRP_INFO_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_HFRP_INFO (0x20800a7aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_HFRP_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_SEND_CMC_UMD_API_OP_PARAMS + * + * Send UMD API operations to CMC + * + * [in] opType + * UMD Task construct/destroy operation to perform on CMC + * [in] flags + * Additional flags depending on the operation type. + * TASK_CONSTRUCT: Flags should be passed from CMC_UMD_API_ALLOCATION_PARAMETERS. + * TASK_DESTROY: Currently unused. + * [in] handle + * Handle of CmcUmdApi object for CMC to identify + * [in] ringBufferSize + * Size of ring buffer in bytes + * [in] ringBufferOffset + * Offset of ring buffer + * [in] userdPa + * PA of USERD memory + * [in] userdVa + * VA of USERD memory + * [in] instBlkAddr + * Address of instance block holding VASpace PDB info + * [in] instBlkAperture + * Aperture of instance block + * [in] usermodeGpuVA + * GPU VA offset of the usermode page + * [in] inputWorkSubmitToken + * Work submit token for task + * [out] cmcWorkSubmitToken + * WorkSubmitToken generated by CMC for UMD_API object + * + */ +#define NV2080_CTRL_INTERNAL_SEND_CMC_UMD_API_OP_PARAMS_MESSAGE_ID (0x7CU) + +typedef struct NV2080_CTRL_INTERNAL_SEND_CMC_UMD_API_OP_PARAMS { + NvU32 opType; + NvU32 flags; + NvU32 ringBufferSize; + NV_DECLARE_ALIGNED(NvU64 ringBufferOffset, 8); + NV_DECLARE_ALIGNED(NvU64 userdPa, 8); + NV_DECLARE_ALIGNED(NvU64 userdVa, 8); + NV_DECLARE_ALIGNED(NvU64 usermodeGpuVa, 8); + NV_DECLARE_ALIGNED(NvU64 instBlkAddr, 8); + NvU8 instBlkAperture; + NvU8 userdAperture; + NvU32 inputWorkSubmitToken; + NvU32 cmcWorkSubmitToken; + NvU32 cmcHandle; +} NV2080_CTRL_INTERNAL_SEND_CMC_UMD_API_OP_PARAMS; + +#define NV2080_INTERNAL_CMC_UMD_API_TASK_CONSTRUCT 0x0U +#define NV2080_INTERNAL_CMC_UMD_API_TASK_DESTROY 0x1U +#define NV2080_INTERNAL_CMC_UMD_API_TASK_ADD_QUEUE 0x2U + +#define NV2080_CTRL_CMD_INTERNAL_SEND_CMC_UMD_API_OP (0x20800a7cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SEND_CMC_UMD_API_OP_PARAMS_MESSAGE_ID" */ +#include "ctrl/ctrl2080/ctrl2080fifo.h" /* NV2080_CTRL_CMD_FIFO_ROTATE_KEYS */ + +/* +* NV2080_CTRL_CMD_INTERNAL_NVLINK_REPLAY_SUPPRESSED_ERRORS +* +* Request from CPU-RM to proccess supressed errors during boot on GSP +* This command accepts no parameters. +*/ +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_REPLAY_SUPPRESSED_ERRORS (0x20800b01U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | 0x1" */ + + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER_V2 + */ + + + + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_V2 { + NvU32 smIssueRateModifierListSize; + NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2 smIssueRateModifierList[NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_MAX_LIST_SIZE]; +} NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_V2; + +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID (0x02U) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_V2 smIssueRateModifierV2[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_V2 (0x20800b03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID (0x03U) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS; + + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_SM_ISSUE_THROTTLE_CTRL + * + * This command returns the throttle controls for all the GR engines. + * + */ + + + + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_THROTTLE_CTRL { + NvU32 smIssueThrottleCtrlListSize; + NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL smIssueThrottleCtrlList[NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL_MAX_LIST_SIZE]; +} NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_THROTTLE_CTRL; + +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS_MESSAGE_ID (0x04U) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_THROTTLE_CTRL smIssueThrottleCtrl[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_THROTTLE_CTRL (0x20800b05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS_MESSAGE_ID (0x05U) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY + * + * Set memory for use by the video event buffer + * + * memDescInfo + * Information to set up memory descriptor on GSP + * + * engDesc + * Video engdesc to find correct engine + * + * bEngineFound + * Bool for whether or not the engine is actually assigned to a video object + */ +#define NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY (0x20800b11) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MEMDESC_INFO memDescInfo, 8); + NvU32 engDesc; + NvBool bEngineFound; +} NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_PER_CHANNEL_KEY + * + * This command handles key rotation for a given channel + * by deriving new key on GSP and updating the key on relevant LCE. + * It also updates IVs for the channels using the key and conditionally re-enables them + * and notifies clients of key rotation status at the end. + * + * pParams : [IN] + * Rotation related information provided by client for triggering key rotation. + * + */ +#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_PER_CHANNEL_KEYS (0x20800b07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_PER_CHANNEL_KEYS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_PER_CHANNEL_KEYS_PARAMS_MESSAGE_ID (0x07U) + +typedef NV2080_CTRL_CMD_FIFO_ROTATE_KEYS_PARAMS NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_PER_CHANNEL_KEYS_PARAMS; + + + +/*! + * NV2080_CTRL_CMD_INTERNAL_NVLINK_RC_USER_MODE_CHANNELS + * + * This command is used to perform recovery actions after the fabric has been + * idled due to a fatal nvlink error. + * This command accepts no parameters. + * + */ +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_RC_USER_MODE_CHANNELS (0x20800b08) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | 0x08" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_POSSIBLE_REFRESH_RATES + * + * This command queries physical RM for the answers to + * NV30F1_CTRL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS. + * + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_POSSIBLE_REFRESH_RATES (0x20800b06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS_MESSAGE_ID (0x06U) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS { + NV_DECLARE_ALIGNED(NV30F1_CTRL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS params, 8); +} NV2080_CTRL_INTERNAL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_UCODE_INSTRUMENTATION_GET_STATE + * + * Internal control to get instrumentation state from GSP-RM. + * + * ucode [in] Numeric ID of the ucode to query + * gfid [in] GFID for vGPU partitions + * bEnabled [out] Whether instrumentation is enabled + * bClear [out] Reserved + * instrumentationType [in] Type of instrumentation (SanitizerCoverage or BullseyeCoverage) + */ +#define NV2080_CTRL_CMD_INTERNAL_UCODE_INSTRUMENTATION_GET_STATE (0x20800b12) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_STATE_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_STATE_PARAMS { + NvU32 ucode; + NvU32 gfid; + NvBool bEnabled; + NvBool bClear; + NvU32 instrumentationType; +} NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_STATE_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_UCODE_INSTRUMENTATION_SET_STATE + * + * Internal control to set instrumentation state on GSP-RM. + * + * ucode [in] Numeric ID of the ucode to control + * gfid [in] GFID for vGPU partitions + * bEnabled [in] Whether to enable instrumentation + * bClear [in] Whether to clear existing data + * instrumentationType [in] Type of instrumentation (SanitizerCoverage or BullseyeCoverage) + */ +#define NV2080_CTRL_CMD_INTERNAL_UCODE_INSTRUMENTATION_SET_STATE (0x20800b13) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_SET_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_SET_STATE_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_SET_STATE_PARAMS { + NvU32 ucode; + NvU32 gfid; + NvBool bEnabled; + NvBool bClear; + NvU32 instrumentationType; +} NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_SET_STATE_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_UCODE_INSTRUMENTATION_GET_DATA + * + * Internal control to get instrumentation data from GSP-RM. + * + * ucode [in] Numeric ID of the ucode to retrieve data from + * gfid [in] GFID for vGPU partitions + * offset [in] Byte offset into coverage data stream + * instrumentationType [in] Type of instrumentation (SanitizerCoverage or BullseyeCoverage) + * data [out] Buffer containing retrieved coverage data + * dataSize [out] Number of bytes written to data[] in this call + * bComplete [out] NV_TRUE when all data has been retrieved + */ +#define NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_MAX_DATA_SIZE 65536 + +#define NV2080_CTRL_CMD_INTERNAL_UCODE_INSTRUMENTATION_GET_DATA (0x20800b14) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_DATA_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_DATA_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_DATA_PARAMS { + NvU32 ucode; + NvU32 gfid; + NvU32 offset; + NvU32 instrumentationType; + NvU8 data[NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_MAX_DATA_SIZE]; + NvU32 dataSize; + NvBool bComplete; +} NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_DATA_PARAMS; + +/* ctrl2080internal_h */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080lpwr.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080lpwr.h new file mode 100644 index 0000000..707a256 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080lpwr.h @@ -0,0 +1,100 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080lpwr.finn +// + + + +/*! + * NV2080_CTRL_CMD_LPWR_DIFR_CTRL + * + * This command is used to control the DIFR + * feature behavior. + * + */ +#define NV2080_CTRL_CMD_LPWR_DIFR_CTRL (0x20802801) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_LPWR_INTERFACE_ID << 8) | NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS_MESSAGE_ID" */ + +/*! + * @brief Various Values for control + */ +// Disable the DIFR +#define NV2080_CTRL_LPWR_DIFR_CTRL_DISABLE (0x00000001) +// Enable the DIFR +#define NV2080_CTRL_LPWR_DIFR_CTRL_ENABLE (0x00000002) + +// Support status for DIFR +#define NV2080_CTRL_LPWR_DIFR_CTRL_SUPPORT_STATUS (0x00000003) + +/*! + * Structure containing DIFR control call Parameters + */ +#define NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS { + NvU32 ctrlParamVal; +} NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS; + +// Values for the SUPPORT Control Status +#define NV2080_CTRL_LPWR_DIFR_SUPPORTED (0x00000001) +#define NV2080_CTRL_LPWR_DIFR_NOT_SUPPORTED (0x00000002) + +/*! + * NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE + * + * This control call is used to send the prefetch response + * + */ +#define NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE (0x20802802) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_LPWR_INTERFACE_ID << 8) | NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS_MESSAGE_ID" */ + +/*! + * @brief Various Values of Reponses for Prefetch Status + */ + +// Prefetch is successfull. +#define NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS (0x00000001) +// OS Filps are enabled, so prefetch can not be done. +#define NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_OS_FLIPS_ENABLED (0x00000002) +// Current Display surface can not fit in L2 +#define NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_INSUFFICIENT_L2_SIZE (0x00000003) +// Fatal and un recoverable Error +#define NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_CE_HW_ERROR (0x00000004) + +/*! + * Structure containing DIFR prefetch response control call Parameters + */ +#define NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS { + NvU32 responseVal; +} NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS; + + +// _ctrl2080lpwr_h_ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080mc.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080mc.h new file mode 100644 index 0000000..e7339d3 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080mc.h @@ -0,0 +1,368 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080mc.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "nvcfg_sdk.h" + +/* NV20_SUBDEVICE_XX mc control commands and parameters */ + +/** + * NV2080_CTRL_CMD_MC_GET_ARCH_INFO + * + * This command returns chip architecture information from the + * master control engine in the specified GPU. + * + * architecture + * This parameter specifies the architecture level for the GPU. + * implementation + * This parameter specifies the implementation of the architecture + * for the GPU. + * revision + * This parameter specifies the revision of the mask used to produce + * the GPU. + * subRevision + * This parameter specific the sub revision of the GPU. Value is one of + * NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_* + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_MC_GET_ARCH_INFO (0x20801701) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS { + NvU32 architecture; + NvU32 implementation; + NvU32 revision; + NvU8 subRevision; +} NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS; + +/* valid architecture values */ + +#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_T23X (0xE0000023) + + +#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100 (0x00000160) +#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100 (0x00000170) +#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GH100 (0x00000180) +#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100 (0x00000190) +#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB100 (0x000001A0) + +#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB200 (0x000001B0) + + +#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GR100 (0x000001C0) + + + +/* valid ARCHITECTURE_T23X implementation values */ + + +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234 (0x00000004) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234D (0x00000005) + + +/* valid ARCHITECTURE_TU10x implementation values */ +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU100 (0x00000000) + + +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU102 (0x00000002) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU104 (0x00000004) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU106 (0x00000006) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU116 (0x00000008) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU117 (0x00000007) + + +/* valid ARCHITECTURE_GA10x implementation values */ +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA100 (0x00000000) + + +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA102 (0x00000002) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA103 (0x00000003) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA104 (0x00000004) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA106 (0x00000006) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA107 (0x00000007) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA10B (0x0000000B) + + +/* valid ARCHITECTURE_GH10x implementation values */ +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100 (0x00000000) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100_SOC (0x00000001) + +/* valid ARCHITECTURE_AD10x implementation values */ +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD100 (0x00000000) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD000 (0x00000001) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD101 (0x00000001) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD102 (0x00000002) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD103 (0x00000003) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD104 (0x00000004) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD106 (0x00000006) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD107 (0x00000007) +/* valid ARCHITECTURE_GB10x implementation values */ +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB100 (0x00000000) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB102 (0x00000002) + +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB110 (0x00000003) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB112 (0x00000004) + + +/* valid ARCHITECTURE_GB20x implementation values */ +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB200 (0x00000000) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB202 (0x00000002) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB203 (0x00000003) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB205 (0x00000005) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB206 (0x00000006) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB207 (0x00000007) + + +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB20B (0x0000000B) + + +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB20C (0x0000000C) + + +/* valid ARCHITECTURE_GR10x implementation values */ +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GR100 (0x00000000) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GR102 (0x00000002) + + + +/* Valid Chip sub revisions */ +#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_NO_SUBREVISION (0x00000000) +#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_P (0x00000001) +#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_Q (0x00000002) +#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_R (0x00000003) + +/* + * NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS + * + * This command instructs the RM to service interrupts for the specified + * engine(s). + * + * engines + * This parameter specifies which engines should have their interrupts + * serviced. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS (0x20801702) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MC_ENGINE_ID_GRAPHICS 0x00000001 +#define NV2080_CTRL_MC_ENGINE_ID_ALL 0xFFFFFFFF + +#define NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS { + NvU32 engines; +} NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS; + + +/* + * NV2080_CTRL_CMD_MC_GET_MANUFACTURER + * + * This command returns the GPU manufacturer information for the associated + * subdevice. + * + * manufacturer + * This parameter returns the manufacturer value for the GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_MC_GET_MANUFACTURER (0x20801703) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS { + NvU32 manufacturer; +} NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS; + + + +/* + * NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP + * + * This call will setup RM to either service or ignore the + * repayable fault interrupt. + * This is a privileged call that can only be called by the UVM driver + * when it will take ownership of the repalayable fault interrupt. + * + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + * NVOS_STATUS_ERROR_INVALID_ARGUMENT + * NVOS_STATUS_ERROR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP (0x2080170c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS { + NvBool bOwnedByRm; +} NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS; + +/* + * NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS + * + * This command gets the notification interrupt vectors device for all VGPU engines from Host RM. + * + * Parameters: + * + * entries [out] + * A buffer to store up to MAX_ENGINES entries of type + * NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY. + * + * numEntries [out] + * Number of populated entries in the provided buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS (0x2080170d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES 256 + +typedef struct NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY { + NvU32 nv2080EngineType; + NvU32 notificationIntrVector; +} NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY; + +#define NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS { + NvU32 numEntries; + NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY entries[NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES]; +} NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS; + +/* + * NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE + * + * This command gets the static interrupts needed by VGPU from Host RM. + * + * Parameters: + * + * entries [out] + * A buffer to store up to MAX_ENGINES entries of type + * NV2080_CTRL_MC_STATIC_INTR_ENTRY. + * + * numEntries [out] + * Number of populated entries in the provided buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE (0x2080170e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX 32 + +// Interface defines for static MC_ENGINE_IDX defines +#define NV2080_INTR_TYPE_NULL (0x00000000) +#define NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT (0x00000001) +#define NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT_ERROR (0x00000002) +#define NV2080_INTR_TYPE_INFO_FAULT (0x00000003) +#define NV2080_INTR_TYPE_REPLAYABLE_FAULT (0x00000004) +#define NV2080_INTR_TYPE_REPLAYABLE_FAULT_ERROR (0x00000005) +#define NV2080_INTR_TYPE_ACCESS_CNTR (0x00000006) +#define NV2080_INTR_TYPE_TMR (0x00000007) +#define NV2080_INTR_TYPE_CPU_DOORBELL (0x00000008) +#define NV2080_INTR_TYPE_GR0_FECS_LOG (0x00000009) +#define NV2080_INTR_TYPE_GR1_FECS_LOG (0x0000000A) +#define NV2080_INTR_TYPE_GR2_FECS_LOG (0x0000000B) +#define NV2080_INTR_TYPE_GR3_FECS_LOG (0x0000000C) +#define NV2080_INTR_TYPE_GR4_FECS_LOG (0x0000000D) +#define NV2080_INTR_TYPE_GR5_FECS_LOG (0x0000000E) +#define NV2080_INTR_TYPE_GR6_FECS_LOG (0x0000000F) +#define NV2080_INTR_TYPE_GR7_FECS_LOG (0x00000010) + +typedef struct NV2080_CTRL_MC_STATIC_INTR_ENTRY { + NvU32 nv2080IntrType; + NvU32 pmcIntrMask; + NvU32 intrVectorStall; + NvU32 intrVectorNonStall; +} NV2080_CTRL_MC_STATIC_INTR_ENTRY; + +#define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS { + NvU32 numEntries; + NV2080_CTRL_MC_STATIC_INTR_ENTRY entries[NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX]; +} NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS; + + +/*! + * Categories of interrupts. + * + * Each of these categories get a separate range of interrupt subtrees (top + * level bits) corresponding to a set of interrupt leaves. + * Interrupt leaves may overlap between two or more categories. + * Interrupt leaves may or may not be contiguous. + */ +typedef enum NV2080_INTR_CATEGORY { + NV2080_INTR_CATEGORY_DEFAULT = 0, + NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE = 1, + NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION = 2, + NV2080_INTR_CATEGORY_RUNLIST = 3, + NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION = 4, + NV2080_INTR_CATEGORY_UVM_OWNED = 5, + NV2080_INTR_CATEGORY_UVM_SHARED = 6, + NV2080_INTR_CATEGORY_ENUM_COUNT = 7, +} NV2080_INTR_CATEGORY; + +#define NV2080_INTR_INVALID_SUBTREE NV_U8_MAX + +typedef struct NV2080_INTR_CATEGORY_SUBTREE_MAP { + // Maximum possible 64 subtrees, but 16 is enough for any existing silicon. + NV_DECLARE_ALIGNED(NvU64 subtreeMask, 8); +} NV2080_INTR_CATEGORY_SUBTREE_MAP; + +/* + * NV2080_CTRL_CMD_MC_GET_INTR_CATEGORY_SUBTREE_MAP + * + * This command gets a mapping from every interrupt category -> subtrees used from + * Host RM. + */ +#define NV2080_CTRL_CMD_MC_GET_INTR_CATEGORY_SUBTREE_MAP (0x2080170f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_INTR_CATEGORY_SUBTREE_MAP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MC_GET_INTR_CATEGORY_SUBTREE_MAP_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NV2080_CTRL_MC_GET_INTR_CATEGORY_SUBTREE_MAP_PARAMS { + NV_DECLARE_ALIGNED(NV2080_INTR_CATEGORY_SUBTREE_MAP subtreeMap[NV2080_INTR_CATEGORY_ENUM_COUNT], 8); +} NV2080_CTRL_MC_GET_INTR_CATEGORY_SUBTREE_MAP_PARAMS; + +/* _ctrl2080mc_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080nvd.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080nvd.h new file mode 100644 index 0000000..0954acf --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080nvd.h @@ -0,0 +1,385 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080nvd.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +#include "ctrl/ctrlxxxx.h" +/* + * NV2080_CTRL_CMD_NVD_GET_DUMP_SIZE + * + * This command gets the expected dump size of a particular GPU dump component. + * Note that events that occur between this command and a later + * NV2080_CTRL_CMD_NVD_GET_DUMP command could alter the size of + * the buffer required. + * + * component + * One of NVDUMP_COMPONENT < 0x400 defined in nvdump.h to estimate + * the size of. + * size + * This parameter returns the expected size. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT if component is invalid. + * + */ + +#define NV2080_CTRL_CMD_NVD_GET_DUMP_SIZE (0x20802401) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS { + NvU32 component; + NvU32 size; +} NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS; + +/* + * NV2080_CTRL_CMD_NVD_GET_DUMP + * + * This command gets a dump of a particular GPU dump component. If triggers + * is non-zero, the command waits for the trigger to occur + * before it returns. + * + * pBuffer + * This parameter points to the buffer for the data. + * component + * One of NVDUMP_COMPONENT < 0x400 defined in nvdump.h to select + * for dumping. + * size + * On entry, this parameter specifies the maximum length for + * the returned data. On exit, it specifies the number of bytes + * returned. + * + * Possible status values returned are: + * NV_OK + * NVOS_ERROR_INVALID_ARGUMENT if component is invalid. + * NVOS_ERROR_INVALID_ADDRESS if pBuffer is invalid + * NVOS_ERROR_INVALID_???? if the buffer was too small + * + * + */ +#define NV2080_CTRL_CMD_NVD_GET_DUMP (0x20802402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_NVD_GET_DUMP_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pBuffer, 8); + NvU32 component; + NvU32 size; +} NV2080_CTRL_NVD_GET_DUMP_PARAMS; + +/* + * NV2080_CTRL_CMD_NVD_GET_NOCAT_JOURNAL + * + * This command returns the contents of the Journal used by NOCAT, and + * optionally clears the data + * + * clear: + * [IN] indicates if should the data be cleared after reporting + * + * JournalRecords : + * [OUT] an array of Journal records reported. + * + * outstandingAssertCount: + * [OUT] number of asserts that remain to be reported on. + * + * reportedAssertCount: + * [OUT] the number of asserts contained in the report + * + * asserts: + * [OUT] an array of up to NV2080_NOCAT_JOURNAL_MAX_ASSERT_RECORDS assert reports + */ + + +#define NV2080_CTRL_CMD_NVD_GET_NOCAT_JOURNAL (0x20802409) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID" */ + +#define NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER 1024 +#define NV2080_NOCAT_JOURNAL_MAX_STR_LEN 65 +#define NV2080_NOCAT_JOURNAL_MAX_JOURNAL_RECORDS 10 +#define NV2080_NOCAT_JOURNAL_MAX_ASSERT_RECORDS 32 + +// structure to hold clock details. +typedef struct NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS { + NvS32 userMinOffset; + NvS32 userMaxOffset; + NvU32 factoryMinOffset; + NvU32 factoryMaxOffset; + NvU32 lastActiveClock; + NvU32 lastActiveVolt; + NvU32 lastActivePoint; + NvU32 kappa; +} NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS; + + +// structure to hold clock configuration & state. +typedef struct NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG { + NvU32 pstateVer; + NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS gpcOverclock; + NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS mclkOverclock; + NvBool bUserOverclocked; + NvBool bFactoryOverclocked; +} NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG; + +// structure to hold the GPU context at the time of the report. +typedef struct NV2080_NOCAT_JOURNAL_GPU_STATE { + NvBool bValid; + NvU32 strap; + NvU16 deviceId; + NvU16 vendorId; + NvU16 subsystemVendor; + NvU16 subsystemId; + NvU16 revision; + NvU16 type; + NvU32 vbiosVersion; + NvBool bOptimus; + NvBool bMsHybrid; + NvBool bFullPower; + NvU32 vbiosOemVersion; + NvU16 memoryType; + NvU8 tag[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; + NvU8 vbiosProject[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; + NvBool bInFullchipReset; + NvBool bInSecBusReset; + NvBool bInGc6Reset; + NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG overclockCfg; +} NV2080_NOCAT_JOURNAL_GPU_STATE; + +#define NV2080_NOCAT_JOURNAL_REC_TYPE_UNKNOWN 0 +#define NV2080_NOCAT_JOURNAL_REC_TYPE_BUGCHECK 1 +#define NV2080_NOCAT_JOURNAL_REC_TYPE_ENGINE 2 +#define NV2080_NOCAT_JOURNAL_REC_TYPE_TDR 3 +#define NV2080_NOCAT_JOURNAL_REC_TYPE_RC 4 +#define NV2080_NOCAT_JOURNAL_REC_TYPE_ASSERT 5 +#define NV2080_NOCAT_JOURNAL_REC_TYPE_ANY 6 + +// this should be relative to the highest type value +#define NV2080_NOCAT_JOURNAL_REC_TYPE_COUNT (0x7) /* finn: Evaluated from "NV2080_NOCAT_JOURNAL_REC_TYPE_ANY + 1" */ +typedef struct NV2080_NOCAT_JOURNAL_ENTRY { + NvU8 recType; + NvU32 bugcheck; + NvU32 tdrBucketId; + NvU8 source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; + NvU32 subsystem; + NV_DECLARE_ALIGNED(NvU64 errorCode, 8); + NvU32 diagBufferLen; + NvU8 diagBuffer[NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER]; + NvU8 faultingEngine[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; + NvU32 mmuFaultType; + NvU32 mmuErrorSrc; + NvU8 tdrReason[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; +} NV2080_NOCAT_JOURNAL_ENTRY; + +typedef struct NV2080_NOCAT_JOURNAL_RECORD { + NvU32 GPUTag; + NV_DECLARE_ALIGNED(NvU64 loadAddress, 8); + NV_DECLARE_ALIGNED(NvU64 timeStamp, 8); + NV_DECLARE_ALIGNED(NvU64 stateMask, 8); + NV2080_NOCAT_JOURNAL_GPU_STATE nocatGpuState; + NV_DECLARE_ALIGNED(NV2080_NOCAT_JOURNAL_ENTRY nocatJournalEntry, 8); +} NV2080_NOCAT_JOURNAL_RECORD; + +// NOCAT activity counter indexes +// collection activity +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_IDX 0 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_GRANDFATHERED_RECORD_IDX 1 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX 2 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECTED_IDX 3 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATIONS_IDX 4 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATION_FAIL_IDX 5 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX 6 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX 7 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_LOCKED_OUT_IDX 8 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CTRL_INSERT_RECORDS_IDX 9 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RPC_INSERT_RECORDS_IDX 10 + +// Journal Lock activity +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCKED_IDX 11 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCK_UPDATED_IDX 12 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_UNLOCKED_IDX 13 + +// lookup activity +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_RECORDS_IDX 14 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_BUFFER_IDX 15 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MATCH_FOUND_IDX 16 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_MATCH_IDX 17 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CLOSEST_FOUND_IDX 18 + +// reporting activity +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX 19 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX 20 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX 21 + +// update activity +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX 22 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX 23 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX 24 + +// general errors +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX 25 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX 26 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX 27 + +// reserved entries for temporary use. +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES4_IDX 28 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES3_IDX 29 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES2_IDX 30 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX 31 + +// this should be relative to the highest counter index +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT (0x20) /* finn: Evaluated from "NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX + 1" */ + +#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY 0:0 +#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_YES 1 +#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_NO 0 + +#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS 1:1 +#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_YES 1 +#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_NO 0 + + +#define NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS { + NvU32 flags; + NvU32 nocatRecordCount; + NvU32 nocatOutstandingRecordCount; + NV_DECLARE_ALIGNED(NV2080_NOCAT_JOURNAL_RECORD journalRecords[NV2080_NOCAT_JOURNAL_MAX_JOURNAL_RECORDS], 8); + NvU32 activityCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT]; + NvU8 reserved[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; +} NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS; + + /* + * NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA + * + * This command reports the TDR data collected by KMD to be added to the + * nocat record + * + * dataType + * [IN] specifies the type of data provided. + * targetRecordType + * [IN] specifies record type the data is intended for. + * nocatJournalData + * [IN] specifies the data to be added. + */ + +#define NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA (0x2080240b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID" */ + +// data types & structures +#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_EMPTY 0 +#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_TDR_REASON 1 +#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG 2 +#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_RCLOG 3 + +#define NV2080_CTRL_NOCAT_TDR_TYPE_NONE 0 +#define NV2080_CTRL_NOCAT_TDR_TYPE_LEGACY 1 +#define NV2080_CTRL_NOCAT_TDR_TYPE_FULLCHIP 2 +#define NV2080_CTRL_NOCAT_TDR_TYPE_BUSRESET 3 +#define NV2080_CTRL_NOCAT_TDR_TYPE_GC6_RESET 4 +#define NV2080_CTRL_NOCAT_TDR_TYPE_SURPRISE_REMOVAL 5 +#define NV2080_CTRL_NOCAT_TDR_TYPE_UCODE_RESET 6 +#define NV2080_CTRL_NOCAT_TDR_TYPE_GPU_RC_RESET 7 +#define NV2080_CTRL_NOCAT_TDR_TYPE_TEST 8 + +typedef struct NV2080CtrlNocatJournalDataTdrReason { + NvU32 flags; + NvU8 source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; + NvU32 subsystem; + NV_DECLARE_ALIGNED(NvU64 errorCode, 8); + NvU32 reasonCode; +} NV2080CtrlNocatJournalDataTdrReason; + +#define NV2080_CTRL_NOCAT_TAG_CLEAR 0:0 +#define NV2080_CTRL_NOCAT_TAG_CLEAR_YES 1 +#define NV2080_CTRL_NOCAT_TAG_CLEAR_NO 0 +typedef struct NV2080CtrlNocatJournalSetTag { + NvU32 flags; + NvU8 tag[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; +} NV2080CtrlNocatJournalSetTag; + +typedef struct NV2080CtrlNocatJournalRclog { + NvU32 flags; + NvU32 rclogSize; // rclog size + NvU32 rmGpuId; // RMGpuId associated with the adapter + NvU32 APIType; // API Type (dx9, dx1x, ogl, etc.) + NvU32 contextType; // Context type (OGL, DX, etc.) + NvU32 exceptType; // ROBUST_CHANNEL_* error identifier + NvU8 processImageName[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; // process image name (without path) +} NV2080CtrlNocatJournalRclog; + +#define NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS { + NvU32 dataType; + NvU32 targetRecordType; + union { + NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalDataTdrReason tdrReason, 8); + NV2080CtrlNocatJournalSetTag tagData; + NV2080CtrlNocatJournalRclog rclog; + } nocatJournalData; +} NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS; + /* + * NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD + * + * This command Inserts a NOCAT Journal record from an outside component. + * + * nocatJournalData + * [IN] specifies the data to be added. + */ + +#define NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD (0x2080240c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR 0:0 +#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_YES 1 +#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_NO 0 +#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER 1:1 +#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_YES 1 +#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_NO 0 + +typedef struct NV2080CtrlNocatJournalInsertRecord { + NvU32 flags; + NV_DECLARE_ALIGNED(NvU64 timestamp, 8); + NvU8 recType; + NvU32 bugcheck; + char source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; + NvU32 subsystem; + NV_DECLARE_ALIGNED(NvU64 errorCode, 8); + char faultingEngine[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; + NvU32 tdrReason; + NvU32 diagBufferLen; + NvU8 diagBuffer[NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER]; +} NV2080CtrlNocatJournalInsertRecord; +#define NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS { + NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalInsertRecord nocatJournalRecord, 8); +} NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS; +/* _ctr2080nvd_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080nvlink.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080nvlink.h new file mode 100644 index 0000000..ba40f71 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080nvlink.h @@ -0,0 +1,3520 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080nvlink.finn +// + +#include "nvlimits.h" +#include "nvfixedtypes.h" +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "ctrl/ctrl2080/ctrl2080nvlink_common.h" +#include "nvcfg_sdk.h" + +/* NV20_SUBDEVICE_XX bus control commands and parameters */ + +/* + * NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS + * + * This command returns the NVLink capabilities supported by the subdevice. + * + * capsTbl + * This is bit field for getting different global caps. The individual bitfields are specified by NV2080_CTRL_NVLINK_CAPS_* + * lowestNvlinkVersion + * This field specifies the lowest supported NVLink version for this subdevice. + * highestNvlinkVersion + * This field specifies the highest supported NVLink version for this subdevice. + * lowestNciVersion + * This field specifies the lowest supported NCI version for this subdevice. + * highestNciVersion + * This field specifies the highest supported NCI version for this subdevice. + * discoveredLinkMask // deprecated use discovered links + * This field provides a bitfield mask of NVLink links discovered on this subdevice. + * enabledLinkMask // deprecated use enabled Links + * This field provides a bitfield mask of NVLink links enabled on this subdevice. + * discoveredLinks + * This field provides a bitfield mask of NVLink links discovered on this subdevice. + * enabledLinks + * This field provides a bitfield mask of NVLink links enabled on this subdevice. + * + */ +#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS { + NvU32 capsTbl; + + NvU8 lowestNvlinkVersion; + NvU8 highestNvlinkVersion; + NvU8 lowestNciVersion; + NvU8 highestNciVersion; + + NvU32 discoveredLinkMask; + NvU32 enabledLinkMask; + + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK discoveredLinks, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK enabledLinks, 8); +} NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS; + +/* extract cap bit setting from tbl */ +#define NV2080_CTRL_NVLINK_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* + * NV2080_CTRL_NVLINK_CAPS + * + * SUPPORTED + * Set if NVLink is present and supported on this subdevice, NV_FALSE otherwise. This field is used for *global* caps only and NOT for per-link caps + * P2P_SUPPORTED + * Set if P2P over NVLink is supported on this subdevice, NV_FALSE otherwise. + * SYSMEM_ACCESS + * Set if sysmem can be accessed over NVLink on this subdevice, NV_FALSE otherwise. + * PEER_ATOMICS + * Set if P2P atomics are supported over NVLink on this subdevice, NV_FALSE otherwise. + * SYSMEM_ATOMICS + * Set if sysmem atomic transcations are supported over NVLink on this subdevice, NV_FALSE otherwise. + * PEX_TUNNELING + * Set if PEX tunneling over NVLink is supported on this subdevice, NV_FALSE otherwise. + * SLI_BRIDGE + * GLOBAL: Set if SLI over NVLink is supported on this subdevice, NV_FALSE otherwise. + * LINK: Set if SLI over NVLink is supported on a link, NV_FALSE otherwise. + * SLI_BRIDGE_SENSABLE + * GLOBAL: Set if the subdevice is capable of sensing SLI bridges, NV_FALSE otherwise. + * LINK: Set if the link is capable of sensing an SLI bridge, NV_FALSE otherwise. + * POWER_STATE_L0 + * Set if L0 is a supported power state on this subdevice/link, NV_FALSE otherwise. + * POWER_STATE_L1 + * Set if L1 is a supported power state on this subdevice/link, NV_FALSE otherwise. + * POWER_STATE_L2 + * Set if L2 is a supported power state on this subdevice/link, NV_FALSE otherwise. + * POWER_STATE_L3 + * Set if L3 is a supported power state on this subdevice/link, NV_FALSE otherwise. + * VALID + * Set if this link is supported on this subdevice, NV_FALSE otherwise. This field is used for *per-link* caps only and NOT for global caps. + * UNCONTAINED_ERROR_RECOVERY + * Set if this GPU supports resetless recovery from uncontained packet errors. + * + */ + +/* caps format is byte_index:bit_mask */ +#define NV2080_CTRL_NVLINK_CAPS_SUPPORTED 0:0x01 +#define NV2080_CTRL_NVLINK_CAPS_P2P_SUPPORTED 0:0x02 +#define NV2080_CTRL_NVLINK_CAPS_SYSMEM_ACCESS 0:0x04 +#define NV2080_CTRL_NVLINK_CAPS_P2P_ATOMICS 0:0x08 +#define NV2080_CTRL_NVLINK_CAPS_SYSMEM_ATOMICS 0:0x10 +#define NV2080_CTRL_NVLINK_CAPS_PEX_TUNNELING 0:0x20 +#define NV2080_CTRL_NVLINK_CAPS_SLI_BRIDGE 0:0x40 +#define NV2080_CTRL_NVLINK_CAPS_SLI_BRIDGE_SENSABLE 0:0x80 +#define NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L0 1:0x01 +#define NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L1 1:0x02 +#define NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L2 1:0x04 +#define NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L3 1:0x08 +#define NV2080_CTRL_NVLINK_CAPS_VALID 1:0x10 +#define NV2080_CTRL_NVLINK_CAPS_UNCONTAINED_ERROR_RECOVERY 1:0x20 + +/* + * Size in bytes of nvlink caps table. This value should be one greater + * than the largest byte_index value above. + */ +#define NV2080_CTRL_NVLINK_CAPS_TBL_SIZE 2U + +#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_INVALID (0x00000000U) +#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0 (0x00000001U) +#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0 (0x00000002U) +#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2 (0x00000004U) +#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0 (0x00000005U) +#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1 (0x00000006U) +#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0 (0x00000007U) +#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_5_0 (0x00000008U) +#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_6_0 (0x00000009U) +#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID (0x00000000U) +#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0 (0x00000001U) +#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_0 (0x00000002U) +#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_2 (0x00000004U) +#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_0 (0x00000005U) +#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1 (0x00000006U) +#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0 (0x00000007U) +#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_5_0 (0x00000008U) +#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_6_0 (0x00000009U) +/* + * NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS (0x20803001U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_NVLINK_DEVICE_INFO + * + * This structure stores information about the device to which this link is associated + * + * deviceIdFlags + * Bitmask that specifies which IDs are valid for the device + * Refer NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_* for possible values + * If NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI is set, PCI information is valid + * If NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID is set, UUID is valid + * domain, bus, device, function, pciDeviceId + * PCI information for the device + * deviceType + * Type of the device + * See NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_* for possible values + * deviceUUID + * This field specifies the device UUID of the device. Useful for identifying the device (or version) + * fabricRecoveryStatusMask + * This field contains flags which advertise the current GPU-centric health status of the NVLINKs + */ +typedef struct NV2080_CTRL_NVLINK_DEVICE_INFO { + // ID Flags + NvU32 deviceIdFlags; + + // PCI Information + NvU32 domain; + NvU16 bus; + NvU16 device; + NvU16 function; + NvU32 pciDeviceId; + + // Device Type + NV_DECLARE_ALIGNED(NvU64 deviceType, 8); + + // Device UUID + NvU8 deviceUUID[16]; + + // GPU-centric fabric health + NvU32 fabricRecoveryStatusMask; +} NV2080_CTRL_NVLINK_DEVICE_INFO; + +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS 31:0 +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_NONE (0x00000000U) +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI (0x00000001U) +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID (0x00000002U) + +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_EBRIDGE (0x00000000U) +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU (0x00000001U) +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU (0x00000002U) +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH (0x00000003U) +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA (0x00000004U) +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE (0x000000FFU) + +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_UUID_INVALID (0xFFFFFFFFU) + +#define NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED 0:0 +#define NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED_FALSE (0x00000000U) +#define NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED_TRUE (0x00000001U) +#define NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY 1:1 +#define NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY_INACTIVE (0x00000000U) +#define NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY_ACTIVE (0x00000001U) + +/* + * NV2080_CTRL_NVLINK_NVLINK_LINK_STATUS_INFO + * + * This structure stores the per-link status of different NVLink parameters. + * + * capsTbl + * This is bit field for getting different global caps. The individual bitfields + * are specified by NV2080_CTRL_NVLINK_CAPS_* + * phyType + * This field specifies the type of PHY (NVHS or GRS) being used for this link. + * subLinkWidth + * This field specifies the no. of lanes per sublink. + * linkState + * This field specifies the current state of the link. + * See NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_LINK_STATE_* for possible values. + * rxSublinkStatus + * This field specifies the current state of RX sublink. + * See NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_SUBLINK_RX_STATE_* for possible values. + * txSublinkStatus + * This field specifies the current state of TX sublink. + * See NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_SUBLINK_TX_STATE_* for possible values. + * bLaneReversal + * This field indicates that lane reversal is in effect on this link. + * nvlinkVersion + * This field specifies the NVLink version supported by the link. + * nciVersion + * This field specifies the NCI version supported by the link. + * phyVersion + * This field specifies the version of PHY being used by the link. + * nvlinkLineRateMbps + * Bit rate at which bits toggle on wires in megabits per second. This is on + * a per Lane basis. + * NOTE: This value is the full speed line rate, not the instantaneous line rate of the link. + * nvlinkLinkClockMhz + * Clock corresponding to link logic in mega hertz + * nvlinkRefClkType + * This field specifies whether the link clock is taken from NVHS reflck + * or PEX refclk for the current GPU. + * nvlinkLinkDataRateKiBps + * Effective rate available for transactions after subtracting overhead, + * as seen at Data Layer in kibibytes (1024 bytes) per second. This is on a + * per Link basis. + * Only valid in GA100+, reported as 0 otherwise + * NOTE: Because minion calculates these values, it will only be valid if + * links are in ACTIVE state + * nvlinkRefClkSpeedMhz + * The input reference frequency to the PLL + * connected + * This field specifies if any device is connected on the other end of the link + * loopProperty + * This field specifies if the link is a loopback/loopout link. See NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_* for possible values. + * remoteDeviceLinkNumber + * This field specifies the link number on the remote end of the link + * remoteDeviceInfo + * This field stores the device information for the remote end of the link + * nvlinkMinL1Threshold + * This field stores the Min L1 Thresohld of the link + * nvlinkMaxL1Threshold + * This field stores the Max L1 Threshold of the link + * nvlinkL1ThresholdUnits + * This field stores the L1 Threshold Units of the link + * nvlpwIdx + * This field stores the nvlpw index in use + * + */ +typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO { + // Top level capablilites + NvU32 capsTbl; + + NvU8 phyType; + NvU8 subLinkWidth; + + // Link and sublink states + NvU32 linkState; + NvU8 rxSublinkStatus; + NvU8 txSublinkStatus; + + // Indicates that lane reversal is in effect on this link. + NvBool bLaneReversal; + + NvU8 nvlinkVersion; + NvU8 nciVersion; + NvU8 phyVersion; + + // Legacy clock information (to be deprecated) + NvU32 nvlinkLinkClockKHz; + NvU32 nvlinkCommonClockSpeedKHz; + NvU32 nvlinkRefClkSpeedKHz; + + NvU32 nvlinkCommonClockSpeedMhz; + + // Clock Speed and Data Rate Reporting + NvU32 nvlinkLineRateMbps; + NvU32 nvlinkLinkClockMhz; + NvU8 nvlinkRefClkType; + NvU32 nvlinkLinkDataRateKiBps; + NvU32 nvlinkRefClkSpeedMhz; + + // Connection information + NvBool connected; + NvU8 loopProperty; + NvU8 remoteDeviceLinkNumber; + NvU8 localDeviceLinkNumber; + + // + // Added as part of NvLink 3.0 + // Note: SID has link info appended to it when provided by minion + // + NV_DECLARE_ALIGNED(NvU64 remoteLinkSid, 8); + NV_DECLARE_ALIGNED(NvU64 localLinkSid, 8); + + // Ampere+ only + NvU32 laneRxdetStatusMask; + + // L1 Threshold Info + NvU32 nvlinkMinL1Threshold; + NvU32 nvlinkMaxL1Threshold; + NvU32 nvlinkL1ThresholdUnits; + + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_DEVICE_INFO remoteDeviceInfo, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_DEVICE_INFO localDeviceInfo, 8); + + NvU32 nvlpwIdx; +} NV2080_CTRL_NVLINK_LINK_STATUS_INFO; + +// NVLink link states +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INIT (0x00000000U) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_HWCFG (0x00000001U) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SWCFG (0x00000002U) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_ACTIVE (0x00000003U) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_FAULT (0x00000004U) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SLEEP (0x00000005U) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY (0x00000006U) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_AC (0x00000008U) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_RX (0x0000000aU) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INVALID (0xFFFFFFFFU) + +// NVLink Rx sublink states +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_HIGH_SPEED_1 (0x00000000U) +// TODO: @achaudhry remove SINGLE_LANE define once references switch to LOW_POWER +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SINGLE_LANE (0x00000004) // Deprecated +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_LOW_POWER (0x00000004) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TRAINING (0x00000005U) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SAFE_MODE (0x00000006U) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_OFF (0x00000007U) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TEST (0x00000008U) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_FAULT (0x0000000eU) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_INVALID (0x000000FFU) + +// NVLink Tx sublink states +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_HIGH_SPEED_1 (0x00000000U) +// TODO: @achaudhry remove SINGLE_LANE define once references switch to LOW_POWER +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SINGLE_LANE (0x00000004) // Deprecated +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_LOW_POWER (0x00000004) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TRAINING (0x00000005U) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SAFE_MODE (0x00000006U) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_OFF (0x00000007U) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TEST (0x00000008U) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_FAULT (0x0000000eU) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_INVALID (0x000000FFU) + +#define NV2080_CTRL_NVLINK_STATUS_PHY_NVHS (0x00000001U) +#define NV2080_CTRL_NVLINK_STATUS_PHY_GRS (0x00000002U) +#define NV2080_CTRL_NVLINK_STATUS_PHY_INVALID (0x000000FFU) + +// Version information +#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_1_0 (0x00000001U) +#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_0 (0x00000002U) +#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_2 (0x00000004U) +#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_0 (0x00000005U) +#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_1 (0x00000006U) +#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_4_0 (0x00000007U) +#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_5_0 (0x00000008U) +#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_6_0 (0x00000009U) +#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID (0x000000FFU) + +#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_1_0 (0x00000001U) +#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_0 (0x00000002U) +#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_2 (0x00000004U) +#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_0 (0x00000005U) +#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_1 (0x00000006U) +#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_4_0 (0x00000007U) +#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_5_0 (0x00000008U) +#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_6_0 (0x00000009U) +#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_INVALID (0x000000FFU) + +#define NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_1_0 (0x00000001U) +#define NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_INVALID (0x000000FFU) + +#define NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_1_0 (0x00000001U) +#define NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_INVALID (0x000000FFU) + +// Connection properties +#define NV2080_CTRL_NVLINK_STATUS_CONNECTED_TRUE (0x00000001U) +#define NV2080_CTRL_NVLINK_STATUS_CONNECTED_FALSE (0x00000000U) + +#define NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPBACK (0x00000001U) +#define NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPOUT (0x00000002U) +#define NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_NONE (0x00000000U) + +#define NV2080_CTRL_NVLINK_STATUS_REMOTE_LINK_NUMBER_INVALID (0x000000FFU) + +// L1 Threshold Units +typedef enum NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT { + NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_100US = 0, + NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_50US = 1, +} NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT; + +// NVLink REFCLK types +#define NV2080_CTRL_NVLINK_REFCLK_TYPE_INVALID (0x00U) +#define NV2080_CTRL_NVLINK_REFCLK_TYPE_NVHS (0x01U) +#define NV2080_CTRL_NVLINK_REFCLK_TYPE_PEX (0x02U) + +#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS { + NvU32 enabledLinkMask; // (This field will be deprecated in the future, use enabledLinks) + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK enabledLinks, 8); + NvBool bSublinkStateInst; // whether instantaneous sublink state is needed + NvBool bNvleModeEnabled; // whether Nvlink Encryption is enabled or not + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_STATUS_INFO linkInfo[NV2080_CTRL_NVLINK_MAX_ARR_SIZE], 8); + NV_DECLARE_ALIGNED(NvU64 enabledNvlpwMask, 8); +} NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS + * + * enabledLinkMask + * This field specifies the mask of available links on this subdevice. + * bNvleModeEnabled + * This field indicates if Nvlink Encryption is enabled or not. + * linkInfo + * This structure stores the per-link status of different NVLink parameters. The link is identified using an index. + * enabledNvlpwMask + * This field specifics mask of Nvlpw indices available + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS (0x20803002U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_NVLINK_ERR_INFO + * Error information per link + * + * TLErrlog + * Returns the error mask for NVLINK TL errors + * Used in Pascal + * + * TLIntrEn + * Returns the intr enable mask for NVLINK TL errors + * Used in Pascal + * + * TLCTxErrStatus0 + * Returns the TLC Tx Error Mask 0 + * Used in Volta and later + * + * TLCTxErrStatus1 + * Returns the TLC Tx Error Mask 1 + * Used in Ampere and later + * + * TLCTxSysErrStatus0 + * Returns the TLC Tx Sys Error Mask 0 + * Used in Ampere and later. + * + * TLCRxErrStatus0 + * Returns the TLC Rx Error Mask 0 + * Used in Volta and later + * + * TLCRxErrStatus1 + * Returns the TLC Rx Error Mask 1 + * Used in Volta and later + * + * TLCRxSysErrStatus0 + * Returns the TLC Rx Sys Error Mask 0 + * Used in Ampere and later. + * + * TLCTxErrLogEn0 + * Returns the TLC Tx Error Log En 0 + * Used in Volta and later + * + * TLCTxErrLogEn1 + * Returns the TLC Tx Error Log En 1 + * Used in Ampere and later + * + * TLCTxSysErrLogEn0 + * Returns the TLC Tx Sys Error Log En 0 + * Used in Ampere and later + * + * TLCRxErrLogEn0 + * Returns the TLC Rx Error Log En 0 + * Used in Volta and later + * + * TLCRxErrLogEn1 + * Returns the TLC Rx Error Log En 1 + * Used in Volta and later + * + * TLCRxSysErrLogEn0 + * Returns the TLC Rx Sys Error Log En 0 + * Used in Ampere and later + * + * MIFTxErrStatus0 + * Returns the MIF Rx Error Mask 0 + * Used in Volta and Turing + * + * MIFRxErrStatus0 + * Returns the MIF Tx Error Mask 0 + * Used in Volta and Turing + * + * NVLIPTLnkErrStatus0 + * Returns the NVLIPT_LNK Error Mask 0 + * Used in Ampere and later + * + * NVLIPTLnkErrLogEn0 + * Returns the NVLIPT_LNK Log En Mask 0 + * Used in Ampere and later + * + * NVLIPTLnkCtrlLinkStateRequest + * Returns the NVLIPT_LNK Control Link State Request value + * Used in Ampere and later + * + * DLSpeedStatusTx + * Returns the NVLINK DL speed status for sublink Tx + * + * DLSpeedStatusRx + * Returns the NVLINK DL speed status for sublink Rx + * + * NVLDLRxSlsmErrCntl + * Returns the NVLDL_RXSLSM_ERR_CNTL value + * Used in Hopper and later + * + * NVLDLTopLinkState + * Returns the NVLDL_TOP_LINK_STATE value + * Used in Hopper and later + * + * NVLDLTopIntr + * Returns the NVLDL_TOP_INTR value + * Used in Hopper and later + * + * DLStatMN00 + * Returns the DLSTAT MN00 Code and subcode + * Used in Hopper and later + * + * DLStatUC01 + * Returns the DLSTAT UC01 value + * Used in Hopper and later + * + * MinionNvlinkLinkIntr + * Returns the MINION_NVLINK_LINK_INTR code and subcode + * Used in Hopper and later + * + * bExcessErrorDL + * Returns true for excessive error rate interrupt from DL + */ +typedef struct NV2080_CTRL_NVLINK_ERR_INFO { + NvU32 TLErrlog; + NvU32 TLIntrEn; + NvU32 TLCTxErrStatus0; + NvU32 TLCTxErrStatus1; + NvU32 TLCTxSysErrStatus0; + NvU32 TLCRxErrStatus0; + NvU32 TLCRxErrStatus1; + NvU32 TLCRxSysErrStatus0; + NvU32 TLCTxErrLogEn0; + NvU32 TLCTxErrLogEn1; + NvU32 TLCTxSysErrLogEn0; + NvU32 TLCRxErrLogEn0; + NvU32 TLCRxErrLogEn1; + NvU32 TLCRxSysErrLogEn0; + NvU32 MIFTxErrStatus0; + NvU32 MIFRxErrStatus0; + NvU32 NVLIPTLnkErrStatus0; + NvU32 NVLIPTLnkErrLogEn0; + NvU32 NVLIPTLnkCtrlLinkStateRequest; + NvU32 DLSpeedStatusTx; + NvU32 DLSpeedStatusRx; + NvU32 NVLDLRxSlsmErrCntl; + NvU32 NVLDLTopLinkState; + NvU32 NVLDLTopIntr; + NvU32 DLStatMN00; + NvU32 DLStatUC01; + NvU32 MinionNvlinkLinkIntr; + NvBool bExcessErrorDL; +} NV2080_CTRL_NVLINK_ERR_INFO; + +/* + * NV2080_CTRL_NVLINK_COMMON_ERR_INFO + * Error information per IOCTRL + * + * NVLIPTErrStatus0 + * Returns the NVLIPT_COMMON Error Mask 0 + * Used in Ampere and later + * + * NVLIPTErrLogEn0 + * Returns the NVLIPT_COMMON Log En Mask 0 + * Used in Ampere and later + */ +typedef struct NV2080_CTRL_NVLINK_COMMON_ERR_INFO { + NvU32 NVLIPTErrStatus0; + NvU32 NVLIPTErrLogEn0; +} NV2080_CTRL_NVLINK_COMMON_ERR_INFO; + +/* Extract the error status bit for a given TL error index i */ +#define NV2080_CTRL_NVLINK_GET_TL_ERRLOG_BIT(intr, i) (((1U << i) & (intr)) >> i) + +/* Extract the intr enable bit for a given TL error index i */ +#define NV2080_CTRL_NVLINK_GET_TL_INTEN_BIT(intr, i) NV2080_CTRL_NVLINK_GET_TL_ERRLOG_BIT(intr, i) + +/* Error status values for a given NVLINK TL error */ +#define NV2080_CTRL_NVLINK_TL_ERRLOG_TRUE (0x00000001U) +#define NV2080_CTRL_NVLINK_TL_ERRLOG_FALSE (0x00000000U) + +/* Intr enable/disable for a given NVLINK TL error */ +#define NV2080_CTRL_NVLINK_TL_INTEN_TRUE (0x00000001U) +#define NV2080_CTRL_NVLINK_TL_INTEN_FALSE (0x00000000U) + +/* NVLINK TL interrupt enable fields for errors */ +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLDATAPARITYEN 0U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLCTRLPARITYEN 1U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPROTOCOLEN 2U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXOVERFLOWEN 3U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMDATAPARITYEN 4U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMHDRPARITYEN 5U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRESPEN 6U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPOISONEN 7U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMDATAPARITYEN 8U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMHDRPARITYEN 9U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLFLOWPARITYEN 10U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLHDRPARITYEN 12U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXCREDITEN 13U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_MAX 14U + +/* NVLINK TL error fields */ +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLDATAPARITYERR 0U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLCTRLPARITYERR 1U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPROTOCOLERR 2U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXOVERFLOWERR 3U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMDATAPARITYERR 4U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMHDRPARITYERR 5U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRESPERR 6U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPOISONERR 7U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMDATAPARITYERR 8U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMHDRPARITYERR 9U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLFLOWPARITYERR 10U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLHDRPARITYERR 12U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXCREDITERR 13U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_MAX 14U + +/* NVLINK DL speed status for sublink Tx*/ +#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_HS (0x00000000U) +#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SINGLE_LANE (0x00000004U) +#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_TRAIN (0x00000005U) +#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SAFE (0x00000006U) +#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_OFF (0x00000007U) + +/* NVLINK DL speed status for sublink Rx*/ +#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_HS (0x00000000U) +#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SINGLE_LANE (0x00000004U) +#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_TRAIN (0x00000005U) +#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SAFE (0x00000006U) +#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_OFF (0x00000007U) + +/* Flags to query different debug registers */ +#define NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_DEFAULT (0x0U) +#define NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_INTR_STATUS (0x1U) +#define NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_ALI_STATUS (0x2U) + +#define NV2080_CTRL_NVLINK_MAX_IOCTRLS 3U +/* + * NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS + * + * linkMask (This field will be deprecated in the future, please use links) + * Returns the mask of links enabled + * + * links + * Returns the mask of links enabled + * + * linkErrInfo + * Returns the error information for all the links + * + * ioctrlMask + * Returns the mask of ioctrls + * + * commonErrInfo + * Returns the error information common to each IOCTRL + * + * ErrInfoFlags + * Input for determining which values to query. Possible values: + * NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_INTR_STATUS + * NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_ALI_STATUS + * + */ +#define NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS { + NvU32 linkMask; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8); + NV2080_CTRL_NVLINK_ERR_INFO linkErrInfo[NV2080_CTRL_NVLINK_MAX_ARR_SIZE]; + NvU32 ioctrlMask; + NV2080_CTRL_NVLINK_COMMON_ERR_INFO commonErrInfo[NV2080_CTRL_NVLINK_MAX_IOCTRLS]; + NvU8 ErrInfoFlags; +} NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_ERR_INFO + * This command is used to query the NVLINK error information + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_NVLINK_GET_ERR_INFO (0x20803003U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS_MESSAGE_ID" */ + +/* + * APIs for getting NVLink counters + */ + +// These are the bitmask definitions for different counter types + +#define NV2080_CTRL_NVLINK_COUNTER_INVALID 0x00000000U + +#define NV2080_CTRL_NVLINK_COUNTER_TL_TX0 0x00000001U +#define NV2080_CTRL_NVLINK_COUNTER_TL_TX1 0x00000002U +#define NV2080_CTRL_NVLINK_COUNTER_TL_RX0 0x00000004U +#define NV2080_CTRL_NVLINK_COUNTER_TL_RX1 0x00000008U + +#define NV2080_CTRL_NVLINK_LP_COUNTERS_DL 0x00000010U + +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L(i) (1 << (i + 8)) +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE__SIZE 4U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L0 0x00000100U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L1 0x00000200U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L2 0x00000400U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L3 0x00000800U + +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT 0x00010000U + +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L(i) (1 << (i + 17)) +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE__SIZE 8U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0 0x00020000U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1 0x00040000U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2 0x00080000U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3 0x00100000U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4 0x00200000U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5 0x00400000U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6 0x00800000U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7 0x01000000U + +#define NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_REPLAY 0x02000000U +#define NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_RECOVERY 0x04000000U + +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_REPLAY 0x08000000U + +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_MASKED 0x10000000U + +/* + * Note that COUNTER_MAX_TYPES will need to be updated each time + * a new counter type gets added to the list above. + * + */ +#define NV2080_CTRL_NVLINK_COUNTER_MAX_TYPES 32U + +/* + * NV2080_CTRL_CMD_NVLINK_GET_COUNTERS + * This command gets the counts for different counter types. + * + * [in] counterMask + * Mask of counter types to be queried + * One of NV2080_CTRL_NVLINK_COUNTERS_TYPE_* macros + * + * [in] linkMask (This field will be deprecated in the future, please use links) + * Mask of links to be queried + * + * [in] links + * Mask of links to be queried + * + * [out] counters + * Counter value returned + * + * [out] bTx0TlCounterOverflow + * This boolean is set to NV_TRUE if TX Counter 0 has rolled over. + * + * [out] bTx1TlCounterOverflow + * This boolean is set to NV_TRUE if TX Counter 1 has rolled over. + * + * [out] bRx0TlCounterOverflow + * This boolean is set to NV_TRUE if RX Counter 0 has rolled over. + * + * [out] bRx1TlCounterOverflow + * This boolean is set to NV_TRUE if RX Counter 1 has rolled over. + * + * [out] value + * This array contains the error counts for each error type as requested from + * the counterMask. The array indexes correspond to the mask bits one-to-one. + */ +typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES { + NvBool bTx0TlCounterOverflow; + NvBool bTx1TlCounterOverflow; + NvBool bRx0TlCounterOverflow; + NvBool bRx1TlCounterOverflow; + NV_DECLARE_ALIGNED(NvU64 value[NV2080_CTRL_NVLINK_COUNTER_MAX_TYPES], 8); +} NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES; + +#define NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS { + NvU32 counterMask; + NV_DECLARE_ALIGNED(NvU64 linkMask, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES counters[NV2080_CTRL_NVLINK_MAX_ARR_SIZE], 8); +} NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_COUNTERS (0x20803004U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS_MESSAGE_ID" */ + + +/* + * NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS + * This command clears/resets the counters for the specified types. + * + * [in] linkMask (This field will be deprecated in the future, please use links) + * This parameter specifies for which links we want to clear the + * counters. + * + * [in] links + * This parameter specifies for which links we want to clear the + * counters. + * + * [in] counterMask + * This parameter specifies the input mask for desired counters to be + * cleared. Note that all counters cannot be cleared. + * + * NOTE: Bug# 2098529: On Turing all DL errors and LP counters are cleared + * together. They cannot be cleared individually per error type. RM + * would possibly move to a new API on Ampere and beyond + */ + +#define NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS (0x20803005U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS { + NvU32 counterMask; + NV_DECLARE_ALIGNED(NvU64 linkMask, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8); +} NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS; + + +#define NV2080_CTRL_NVLINK_COUNTER_TP_TL_TX0 0U +#define NV2080_CTRL_NVLINK_COUNTER_TP_TL_TX1 1U +#define NV2080_CTRL_NVLINK_COUNTER_TP_TL_RX0 2U +#define NV2080_CTRL_NVLINK_COUNTER_TP_TL_RX1 3U + +#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_SIZE 4U +#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L0 4U +#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L1 5U +#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L2 6U +#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L3 7U + +#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_SIZE 8U +#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L0 8U +#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L1 9U +#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L2 10U +#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L3 11U +#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L4 12U +#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L5 13U +#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L6 14U +#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L7 15U + +#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_TX_ERR_RECOVERY 16U + +#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_TX_ERR_REPLAY 17U +#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_REPLAY 18U + +#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_MASKED 19U +#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_FLIT 20U + +#define NV2080_CTRL_NVLINK_COUNTER_LP_DL 21U + +#define NV2080_CTRL_NVLINK_COUNTER_V1_MAX_COUNTER NV2080_CTRL_NVLINK_COUNTER_LP_DL + +/* Transmit Counters */ +#define NV2080_CTRL_NVLINK_COUNTER_XMIT_PACKETS 22U +#define NV2080_CTRL_NVLINK_COUNTER_XMIT_BYTES 23U +/* Received Counters */ +#define NV2080_CTRL_NVLINK_COUNTER_RCV_PACKETS 24U +#define NV2080_CTRL_NVLINK_COUNTER_RCV_BYTES 25U +/* Link Events */ +#define NV2080_CTRL_NVLINK_COUNTER_LINK_ERROR_RECOVERY_COUNTER 26U +#define NV2080_CTRL_NVLINK_COUNTER_LINK_DOWNED_COUNTER 27U +#define NV2080_CTRL_NVLINK_COUNTER_LINK_RECOVERY_SUCCESSFUL_COUNTER 28U +/* Link Receive Errors */ +#define NV2080_CTRL_NVLINK_COUNTER_RCV_ERRORS 29U +#define NV2080_CTRL_NVLINK_COUNTER_RCV_REMOTE_ERRORS 30U +#define NV2080_CTRL_NVLINK_COUNTER_RCV_GENERAL_ERRORS 31U +/* Link Receive Errors Detail */ +#define NV2080_CTRL_NVLINK_COUNTER_RCV_MALFORMED_PKT_ERROR 32U +#define NV2080_CTRL_NVLINK_COUNTER_RCV_BUFFER_OVERRUN_ERROR 33U +#define NV2080_CTRL_NVLINK_COUNTER_RCV_VL15DROPPED_ERROR 34U +/* Link Other Errors Detail */ +#define NV2080_CTRL_NVLINK_COUNTER_LINK_INTEGRITY_ERRORS 35U +#define NV2080_CTRL_NVLINK_COUNTER_BUFFER_OVERRUN_ERRORS 36U +/* Link Transmit Errors */ +#define NV2080_CTRL_NVLINK_COUNTER_XMIT_WAIT_TIME 37U +#define NV2080_CTRL_NVLINK_COUNTER_XMIT_ERRORS 38U +/* FEC Block Counters */ +#define NV2080_CTRL_NVLINK_COUNTER_SINGLE_ERROR_BLOCKS 39U +#define NV2080_CTRL_NVLINK_COUNTER_CORRECTED_BLOCKS 40U +#define NV2080_CTRL_NVLINK_COUNTER_UNCORRECTED_BLOCKS 41U +/* FEC Symbol Counters */ +#define NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_LANE_0 42U +#define NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_LANE_1 43U +#define NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_TOTAL 44U +/* FEC Raw Error Counters */ +#define NV2080_CTRL_NVLINK_COUNTER_RAW_ERRORS_LANE_0 45U +#define NV2080_CTRL_NVLINK_COUNTER_RAW_ERRORS_LANE_1 46U +#define NV2080_CTRL_NVLINK_COUNTER_CORRECTED_BITS 47U +/* FEC Raw BER */ +#define NV2080_CTRL_NVLINK_COUNTER_RAW_BER_LANE_0 48U +#define NV2080_CTRL_NVLINK_COUNTER_RAW_BER_LANE_1 49U +#define NV2080_CTRL_NVLINK_COUNTER_RAW_BER_TOTAL 50U +/* FEC Effective BER */ +#define NV2080_CTRL_NVLINK_COUNTER_NO_ERROR_BLOCKS 51U +#define NV2080_CTRL_NVLINK_COUNTER_EFFECTIVE_ERRORS 52U +#define NV2080_CTRL_NVLINK_COUNTER_EFFECTIVE_BER 53U +/* Phy Symbol Errors Counters */ +#define NV2080_CTRL_NVLINK_COUNTER_SYMBOL_ERRORS 54U +#define NV2080_CTRL_NVLINK_COUNTER_SYMBOL_BER 55U +#define NV2080_CTRL_NVLINK_COUNTER_RECEIVED_BITS 56U +/* Phy Other Errors Counters */ +#define NV2080_CTRL_NVLINK_COUNTER_SYNC_HEADER_ERRORS 57U +#define NV2080_CTRL_NVLINK_COUNTER_TIME_SINCE_LAST_CLEAR 58U +/* PLR Receive Counters */ +#define NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS 59U +#define NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS_WITH_UNCORRECTABLE_ERRORS 60U +#define NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS_WITH_ERRORS 61U +/* PLR Transmit Counters */ +#define NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_BLOCKS 62U +#define NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_BLOCKS 63U +#define NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_EVENTS 64U +/* PLR BW Loss Counters */ +#define NV2080_CTRL_NVLINK_COUNTER_PLR_BW_LOSS 65U +/* NVLE Rx counters */ +#define NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_GOOD 66U +#define NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_ERROR 67U +#define NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_AUTH 68U +/* NVLE Tx Counters */ +#define NV2080_CTRL_NVLINK_COUNTER_NVLE_TX_GOOD 69U +#define NV2080_CTRL_NVLINK_COUNTER_NVLE_TX_ERROR 70U +/* FEC Histogram */ +#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_0 71U +#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_1 72U +#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_2 73U +#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_3 74U +#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_4 75U +#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_5 76U +#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_6 77U +#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_7 78U +#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_8 79U +#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_9 80U +#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_10 81U +#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_11 82U +#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_12 83U +#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_13 84U +#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_14 85U +#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_15 86U + +/* Throughput counters */ +#define NV2080_CTRL_NVLINK_COUNTER_TP_RX_DATA 87U +#define NV2080_CTRL_NVLINK_COUNTER_TP_TX_DATA 88U +#define NV2080_CTRL_NVLINK_COUNTER_TP_RX_RAW 89U +#define NV2080_CTRL_NVLINK_COUNTER_TP_TX_RAW 90U + +/* Low power counters */ +#define NV2080_CTRL_NVLINK_COUNTER_L1_ENTRY 91U +#define NV2080_CTRL_NVLINK_COUNTER_L1_ENTRY_FORCE 92U +#define NV2080_CTRL_NVLINK_COUNTER_L1_EXIT 93U +#define NV2080_CTRL_NVLINK_COUNTER_L1_EXIT_RECAL 94U +#define NV2080_CTRL_NVLINK_COUNTER_L1_EXIT_REMOTE 95U +#define NV2080_CTRL_NVLINK_COUNTER_L1_LP_STEADY_STATE_TIME 96U +#define NV2080_CTRL_NVLINK_COUNTER_L1_HIGH_SPEED_STEADY_STATE_TIME 97U +#define NV2080_CTRL_NVLINK_COUNTER_L1_OTHER_STATE_TIME 98U +#define NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_ENTRY_TIME 99U +#define NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_EXIT_TIME 100U +#define NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_FULL_BW_ENTRY_TIME 101U +#define NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_FULL_BW_EXIT_TIME 102U +#define NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_ENTRY_TIME 103U +#define NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_EXIT_TIME 104U +#define NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_FULL_BW_ENTRY_TIME 105U +#define NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_FULL_BW_EXIT_TIME 106U + +#define NV2080_CTRL_NVLINK_COUNTER_PLR_LAST_RAW_BER 107U +#define NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_EVENTS_WITHIN_T_SEC_MAX_LOW 108U +#define NV2080_CTRL_NVLINK_COUNTER_L0_TX_IDLE_ENTRY 109U +#define NV2080_CTRL_NVLINK_COUNTER_L0_TX_IDLE_ENTRY_DUE_TO_L1 110U +#define NV2080_CTRL_NVLINK_COUNTER_L0_TX_IDLE_REQ_NOT_YET_ACTIVE 111U +#define NV2080_CTRL_NVLINK_COUNTER_L0_TX_IDLE_ACTIVE_DUE_TO_L1_REQ 112U +#define NV2080_CTRL_NVLINK_COUNTER_L0_TX_IDLE_ACTIVE 113U + +#define NV2080_CTRL_NVLINK_COUNTERS_MAX 114U + +#define NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS 2U +#define NV2080_CTRL_NVLINK_COUNTER_MAX_COUNTERS_PER_LINK_IN_REQ 28 +#define NV2080_CTRL_NVLINK_COUNTER_V2_GROUP(i) ((i) / 64) +#define NV2080_CTRL_NVLINK_COUNTER_V2_COUNTER_MASK(i) ((NvU64)1 << ((i) % 64)) + +/* + * NV2080_CTRL_CMD_NVLINK_GET_COUNTERS_V2 + * This command gets the counts for different counter types. + * + * [in] linkMask (This field will be deprecated in the future, please use links) + * Mask of links to be queried + * + * [in] links + * Mask of links to be queried + * + * [in] counterMask + * Mask of counter types to be queried + * One of NV2080_CTRL_NVLINK_COUNTERS_TYPE_* macros + * + * [out] counter + * This array contains the error counts for each error type as requested from + * the counterMask. The array indexes correspond to the mask bits one-to-one. + */ + +typedef struct NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES { + NvBool overFlow; + NV_DECLARE_ALIGNED(NvU64 value, 8); +} NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES; + +#define NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS_MESSAGE_ID (0x50U) + +typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS { + NV_DECLARE_ALIGNED(NvU64 linkMask, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8); + NV_DECLARE_ALIGNED(NvU64 counterMask[NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS], 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES counter[NV2080_CTRL_NVLINK_MAX_ARR_SIZE][NV2080_CTRL_NVLINK_COUNTER_MAX_COUNTERS_PER_LINK_IN_REQ], 8); +} NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS; +#define NV2080_CTRL_CMD_NVLINK_GET_COUNTERS_V2 (0x20803050U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8 | NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS_MESSAGE_ID)" */ + +/* + * NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS_V2 + * This command clears/resets the counters for the specified types. + * + * [in] linkMask (This field will be deprecated in the future, please use links) + * This parameter specifies for which links we want to clear the + * counters. + * + * [in] links + * This parameter specifies for which links we want to clear the + * counters. + * + * [in] counterMask + * This parameter specifies the input mask for desired counters to be + * cleared. Note that all counters cannot be cleared. +*/ + +#define NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS_MESSAGE_ID (0x51U) + +typedef struct NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS { + NV_DECLARE_ALIGNED(NvU64 linkMask, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8); + NV_DECLARE_ALIGNED(NvU64 counterMask[NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS], 8); +} NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS; +#define NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS_V2 (0x20803051U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8 | NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS_MESSAGE_ID)" */ + +/* + * NV2080_CTRL_CMD_NVLINK_INJECT_ERROR + * This command causes all the same actions to occur as if the related + * error were to occur, either fatal or recoverable. + * + * [in] linkMask (This field will be deprecated in the future, please use links) + * Controls which links to apply error injection to. + * + * [in] links + * Controls which links to apply error injection to. + * + * [in] bFatal + * This parameter specifies that the error should be fatal. + * + */ +#define NV2080_CTRL_CMD_NVLINK_INJECT_ERROR (0x20803006U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS { + NvU32 linkMask; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8); + NvBool bFatalError; +} NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS; + +/* NVLINK unit list - to be used with error notifiers */ +#define NV2080_CTRL_NVLINK_UNIT_DL 0x01U +#define NV2080_CTRL_NVLINK_UNIT_TL 0x02U +#define NV2080_CTRL_NVLINK_UNIT_TLC_RX_0 0x03U +#define NV2080_CTRL_NVLINK_UNIT_TLC_RX_1 0x04U +#define NV2080_CTRL_NVLINK_UNIT_TLC_TX_0 0x05U +#define NV2080_CTRL_NVLINK_UNIT_MIF_RX_0 0x06U +#define NV2080_CTRL_NVLINK_UNIT_MIF_TX_0 0x07U +#define NV2080_CTRL_NVLINK_UNIT_MINION 0x08U + +/* + * NV2080_CTRL_NVLINK_ERROR_INJECT_CFG + * + * [in] errType + * This parameter specifies the type of error injection settings + * [in] errSettings + * This parameter specifies the settings for the error type in NVL5 + */ + +typedef enum NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE { + NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_TX_ERR = 1, + NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_PKT_ERR = 2, + NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_AUTH_TAG_ERR = 3, + NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_LINK_ERR = 4, + NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_MAX = 5, +} NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE; + +typedef struct NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG { + NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE errType; + NV_DECLARE_ALIGNED(NvU64 errSettings, 8); +} NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG; + +/* + * Tx error type settings + */ +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE 31:28 +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_NO_ERROR 0x00000000U +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_RAW_BER 0x00000001U +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_EFFECTIVE_BER 0x00000002U +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_ERR_INJECT_DURATION 27:12 // Error Injection Duration, in 10ms units. +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_BER_MANTISSA 11:8 +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_BER_EXPONENT 7:0 + +/* + * Packet error type settings + */ +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_INJECT_COUNT 15:0 +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP 16:16 +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP_DIS 0x00000000U +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP_EN 0x00000001U +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON 17:17 +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON_DIS 0x00000000U +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON_EN 0x00000001U +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_CLEAR_COUNTERS 18:18 + +/* + * Authentication error type settings + */ +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_PIPE_INDEX 3:0 +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR 4:4 +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR_DIS 0x00000000U +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR_EN 0x00000001U + +/* + * Link Error type settings + */ +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN 0:0 +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN_DIS 0x00000000U +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN_EN 0x00000001U + +/* + * NV2080_CTRL_CMD_NVLINK_SET_HW_ERROR_INJECT + * This command causes all the same actions to occur as if the related + * error were to occur, either fatal or recoverable. + * + * [in] linkMask size: 64 bits (This field will be deprecated in the future, please use links) + * Mask of the links to be configured. + * + * [in] links + * Mask of the links to be configured. + * + * [in] errCfg + * This parameter specifies that the error configurations. + */ + +#define NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS { + NV_DECLARE_ALIGNED(NvU64 linkMask, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG errCfg[NV2080_CTRL_NVLINK_MAX_ARR_SIZE], 8); +} NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_SET_HW_ERROR_INJECT (0x20803081U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE 1:0 +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_UP 0x00000000U +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_DOWN_BY_REQUEST 0x00000001U +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_DOWN_BY_HW_ERR 0x00000002U + +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS 0:0 +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS_NO_ERR_INJECT 0x00000000U +#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS_PERFORMING_ERR_INJECT 0x00000001U + +/* + * NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO + * + * [out] txErrInfo + * This info specifies the settings for Tx errs in NVL5 + * [out] packetErrSettings + * This info specifies the settings for Pkt errs in NVL5 + * [out] authErrSettings + * This info specifies the settings for NVLE errs in NVL5 + * [out] linkStatus + * This specifies the status of the link in NVL5 + * [out] errInjectStatus + * This specifies the status of error injection + */ + +typedef struct NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO { + NvU32 txErrInfo; + NvU32 packetErrInfo; + NvU32 authErrInfo; + NvU32 linkStatus; + NvU32 errInjectStatus; +} NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_HW_ERROR_INJECT + * This command get all the current nvlink error config + * + * [in] linkMask size: 64 bits (This field will be deprecated in the future, please use links) + * Mask of the links to be configured. + * + * [in] links + * Mask of the links to be configured. + * + * [in] errCfg + * This parameter specifies that the error configurations. + */ + +#define NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID (0x82U) + +typedef struct NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS { + NV_DECLARE_ALIGNED(NvU64 linkMask, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8); + NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO errInfo[NV2080_CTRL_NVLINK_MAX_ARR_SIZE]; +} NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_HW_ERROR_INJECT (0x20803082U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES + * This command gets the number of successful error recoveries + * + * [in] linkMask size: 32 bits (This field will be deprecated in the future, please use links) + * This parameter controls which links to get recoveries for. + * + * [in] links + * This parameter controls which links to get recoveries for. + * + * [out] numRecoveries + * This parameter specifies the number of successful per link error recoveries + */ +#define NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES (0x20803007U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS { + NvU32 linkMask; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8); + NvU32 numRecoveries[NV2080_CTRL_NVLINK_MAX_ARR_SIZE]; +} NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE + * + * This command queries the remote endpoint type of the link recorded at the + * time the last error occurred on the link. + * + * [in] linkId + * This parameter specifies the link to get the last remote endpoint type + * recorded for. + * + * [out] remoteType + * This parameter returns the remote endpoint type of the link recorded at + * the time the last error occurred on the link. Possible values are: + * NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE + * The link is not connected to an active remote endpoint. + * NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU + * The remote endpoint of the link is a peer GPU. + * NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU + * The remote endpoint of the link is the host system (e.g., an NPU + * on IBM POWER platforms). + * NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA + * The remote endpoint of the link a tegra device + * + * Possible return status values are: + * NV_OK + * If the remoteType parameter value is valid upon return. + * NV_ERR_INVALID_ARGUMENT + * If the linkId parameter does not specify a valid link. + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on this GPU or the remote endpoint type is + * not recorded in non-volatile storage. + */ +#define NV2080_CTRL_CMD_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE (0x20803008U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS { + NvU32 linkId; + NvU32 remoteType; +} NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_LINK_FATAL_ERROR_COUNTS + * + * This command queries the number of each type of fatal errors that have + * occurred on the given link. + * + * [in] linkId + * This parameter specifies the link to get the fatal error information + * for. + * + * [out] supportedCounts + * This parameter identifies which counts in the fatalErrorCounts array + * are valid for the given link. A bit set in this field means that the + * corresponding index is valid in the fatalErrorCounts array. + * + * [out] fatalErrorCounts + * This parameter returns an array of 8-bit counts, one for each type of + * fatal error that can occur on the link. The valid indices of this array + * are: + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_RX_DL_DATA_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_RX_DL_CTRL_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_PROTOCOL + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_OVERFLOW + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_RX_RAM_DATA_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_RX_RAM_HDR_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RESP + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_POISON + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_POISONED_PKT_RCVD + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_TX_RAM_DATA_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_TX_RAM_HDR_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_CREDIT + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_FLOW_CTRL_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_FLOW_CTRL_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_HDR_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_RECOVERY_LONG + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_RAM + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_INTERFACE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_DL_PROTOCOL + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_HDR_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_AE_FLIT_RCVD + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_BE_FLIT_RCVD + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_ADDR_ALIGN + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_PKT_LEN + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CMD_ENC + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_DAT_LEN_ENC + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_ADDR_TYPE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_RSP_STATUS + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_PKT_STATUS + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_PO_FOR_CACHE_ATTR + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COMPRESSED_RESP + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_TARGET + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_HDR_OVERFLOW + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_OVERFLOW + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_STOMPED_PKT_RCVD + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_CORRECTABLE_INTERNAL + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_VC_OVERFLOW + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_HDR_CREDIT_OVERFLOW + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_CREDIT_OVERFLOW + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_REPLAY_CREDIT_OVERFLOW + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_UNSUPPORTED_VC_OVERFLOW + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_STOMPED_PKT_SENT + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_POISONED_PKT_SENT + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_TARGET + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_DATA_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_HDR_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_DATA_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_HDR_PARITY + * + * Possible return status values are: + * NV_OK + * If the values in the fatalErrorCounts array are valid upon return. + * NV_ERR_INVALID_ARGUMENT + * If the linkId parameter does not specify a valid link. + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on this GPU or aggregate NVLINK fatal error + * counts are not recorded in non-volatile storage. + */ +#define NV2080_CTRL_CMD_NVLINK_GET_LINK_FATAL_ERROR_COUNTS (0x20803009U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS_MESSAGE_ID" */ + +/* + * NVLink 1 Fatal Error Types + */ +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_DATA_PARITY 0U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_CTRL_PARITY 1U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_PROTOCOL 2U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_OVERFLOW 3U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_DATA_PARITY 4U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_HDR_PARITY 5U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RESP 6U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_POISON 7U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_DATA_PARITY 8U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_HDR_PARITY 9U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_CREDIT 10U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_FLOW_CTRL_PARITY 11U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_HDR_PARITY 12U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_RECOVERY_LONG 13U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_RAM 14U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_INTERFACE 15U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE 16U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE 17U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_DL_PROTOCOL 18U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT 19U + +/* + * NVLink 2 Fatal Error Types + */ +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_DATA_PARITY 0U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_CTRL_PARITY 1U +// No direct equivalent to: TL_RX_PROTOCOL 2 +// No direct equivalent to: TL_RX_OVERFLOW 3 +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_DATA_PARITY 4U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_HDR_PARITY 5U +// No direct equivalent to: TL_RX_RESP 6 +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_POISONED_PKT_RCVD 7U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_DATA_PARITY 8U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_HDR_PARITY 9U +// No direct equivalent to: TL_TX_CREDIT 10 +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_FLOW_CONTROL_PARITY 11U +// No direct equivalent to: TL_DL_HDR_PARITY 12 +// Identical to NVLink 1: DL_TX_RECOVERY_LONG 13 +// Identical to NVLink 1: DL_TX_FAULT_RAM 14 +// Identical to NVLink 1: DL_TX_FAULT_INTERFACE 15 +// Identical to NVLink 1: DL_TX_FAULT_SUBLINK_CHANGE 16 +// Identical to NVLink 1: DL_RX_FAULT_SUBLINK_CHANGE 17 +// Identical to NVLink 1: DL_RX_FAULT_DL_PROTOCOL 18 +// Identical to NVLink 1: DL_LTSSM_FAULT 19 +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_HDR_PARITY 20U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_AE_FLIT_RCVD 21U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_BE_FLIT_RCVD 22U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_ADDR_ALIGN 23U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_PKT_LEN 24U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CMD_ENC 25U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_DAT_LEN_ENC 26U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_ADDR_TYPE 27U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_RSP_STATUS 28U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_PKT_STATUS 29U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ 30U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP 31U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE 32U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE 33U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE 34U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_PO_FOR_CACHE_ATTR 35U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COMPRESSED_RESP 36U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_TARGET 37U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST 38U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_HDR_OVERFLOW 39U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_OVERFLOW 40U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_STOMPED_PKT_RCVD 41U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_CORRECTABLE_INTERNAL 42U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_VC_OVERFLOW 43U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE 44U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE 45U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_HDR_CREDIT_OVERFLOW 46U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_CREDIT_OVERFLOW 47U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_REPLAY_CREDIT_OVERFLOW 48U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_UNSUPPORTED_VC_OVERFLOW 49U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_STOMPED_PKT_SENT 50U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_POISONED_PKT_SENT 51U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_TARGET 52U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST 53U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_DATA_PARITY 54U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_HDR_PARITY 55U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_DATA_PARITY 56U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_HDR_PARITY 57U + +/* + * NVLink 3 Fatal Error Types + */ +// Identical to NVLink 2: TLC_RX_DL_DATA_PARITY 0 +// Identical to NVLink 2: TLC_RX_DL_CTRL_PARITY 1 +// No direct equivalent to: TL_RX_PROTOCOL 2 +// No direct equivalent to: TL_RX_OVERFLOW 3 +// No direct equivalent to: TLC_RX_RAM_DATA_PARITY 4 +// No direct equivalent to: RX_RAM_HDR_PARITY 5 +// No direct equivalent to: TL_RX_RESP 6 +// No direct equivalent to: TLC_RX_DATA_POISONED_PKT_RCVD 7 +// No direct equivalent to: TLC_TX_RAM_DATA_PARITY 8 +// No direct equivalent to: TLC_TX_RAM_HDR_PARITY 9 +// No direct equivalent to: TL_TX_CREDIT 10 +// Identical to NVLink 2: TLC_TX_DL_FLOW_CONTROL_PARITY 11 +// No direct equivalent to: TL_DL_HDR_PARITY 12 +// No direct equivalent to: DL_TX_RECOVERY_LONG 13 +// Identical to NVLink 1: DL_TX_FAULT_RAM 14 +// Identical to NVLink 1: DL_TX_FAULT_INTERFACE 15 +// Identical to NVLink 1: DL_TX_FAULT_SUBLINK_CHANGE 16 +// Identical to NVLink 1: DL_RX_FAULT_SUBLINK_CHANGE 17 +// Identical to NVLink 1: DL_RX_FAULT_DL_PROTOCOL 18 +// No direct equivalent to: DL_LTSSM_FAULT 19 +// Identical to NVLink 2: TLC_RX_DL_HDR_PARITY 20 +// Identical to NVLink 2: TLC_RX_INVALID_AE_FLIT_RCVD 21 +// Identical to NVLink 2: TLC_RX_INVALID_BE_FLIT_RCVD 22 +// Identical to NVLink 2: TLC_RX_INVALID_ADDR_ALIGN 23 +// Identical to NVLink 2: TLC_RX_PKT_LEN 24 +// Identical to NVLink 2: TLC_RX_RSVD_CMD_ENC 25 +// Identical to NVLink 2: TLC_RX_RSVD_DAT_LEN_ENC 26 +// No direct equivalent to: TLC_RX_RSVD_ADDR_TYPE 27 +// No direct equivalent to: TLC_RX_RSVD_RSP_STATUS 28 +// Identical to NVLink 2: TLC_RX_RSVD_PKT_STATUS 29 +// Identical to NVLink 2: TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ 30 +// Identical to NVLink 2: TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP 31 +// No direct equivalent to: TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE 32 +// Identical to NVLink 2: TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE 33 +// Identical to NVLink 2: TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE 34 +// Identical to NVLink 2: TLC_RX_INVALID_PO_FOR_CACHE_ATTR 35 +// Identical to NVLink 2: TLC_RX_INVALID_COMPRESSED_RESP 36 +// No direct equivalent to: TLC_RX_RESP_STATUS_TARGET 37 +// No direct equivalent to: TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST 38 +// Identical to NVLink 2: TLC_RX_HDR_OVERFLOW 39 +// Identical to NVLink 2: TLC_RX_DATA_OVERFLOW 40 +// Identical to NVLink 2: TLC_RX_STOMPED_PKT_RCVD 41 +// No direct equivalent to: TLC_RX_CORRECTABLE_INTERNAL 42 +// No direct equivalent to: TLC_RX_UNSUPPORTED_VC_OVERFLOW 43 +// No direct equivalent to: TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE 44 +// No direct equivalent to: TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE 45 +// No direct equivalent to: TLC_TX_HDR_CREDIT_OVERFLOW 46 +// No direct equivalent to: TLC_TX_DATA_CREDIT_OVERFLOW 47 +// No direct equivalent to: TLC_TX_DL_REPLAY_CREDIT_OVERFLOW 48 +// No direct equivalent to: TLC_TX_UNSUPPORTED_VC_OVERFLOW 49 +// No direct equivalent to: TLC_TX_STOMPED_PKT_SENT 50 +// No direct equivalent to: TLC_TX_DATA_POISONED_PKT_SENT 51 +// No direct equivalent to: TLC_TX_RESP_STATUS_TARGET 52 +// No direct equivalent to: TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST 53 +// No direct equivalent to: MIF_RX_RAM_DATA_PARITY 54 +// No direct equivalent to: MIF_RX_RAM_HDR_PARITY 55 +// No direct equivalent to: MIF_TX_RAM_DATA_PARITY 56 +// No direct equivalent to: MIF_TX_RAM_HDR_PARITY 57 +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COLLAPSED_RESPONSE 58U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_HDR_ECC_DBE 59U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_PARITY 60U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_UP 61U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_DOWN 62U + +#define NV2080_CTRL_NVLINK_NUM_FATAL_ERROR_TYPES 63U + +#define NV2080_CTRL_NVLINK_IS_FATAL_ERROR_COUNT_VALID(count, supportedCounts) \ + (!!((supportedCounts) & NVBIT64(count))) + +#define NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS { + NvU32 linkId; + NV_DECLARE_ALIGNED(NvU64 supportedCounts, 8); + NvU8 fatalErrorCounts[NV2080_CTRL_NVLINK_NUM_FATAL_ERROR_TYPES]; +} NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_LINK_NONFATAL_ERROR_RATES + * + * This command queries recent non-fatal error rates for the given link. + * + * The error rates specify the maximum number of errors per minute recorded + * for the given link within a 24-hour period for daily maximums or a 30-day + * period for monthly maximums. + * + * [in] linkId + * This parameter specifies the link to get the nonfatal error information + * for. + * + * [out] numDailyMaxNonfatalErrorRates + * This parameter returns the number of valid nonfatal error rate entries + * in the dailyMaxNonfatalErrorRates parameter. + * + * [out] dailyMaxNonfatalErrorRates + * This parameter returns maximum nonfatal error rate entries recorded + * over the last few 24-hour periods. For example, index 0 contains the + * maximum nonfatal error rate recorded in the current day, index 1 + * contains the maximum nonfatal error rate recorded yesterday ago, etc. + * + * [out] numMonthlyMaxNonfatalErrorRates + * This parameter returns the number of valid nonfatal error rate entries + * in the monthlyMaxNonfatalErrorRates parameter. + * + * [out] monthlyMaxNonfatalErrorRates + * THis parameter returns maximum nonfatal error rate entries recorded + * over the last few 30-day periods. For example, index 0 contains the + * maximum nonfatal error rate recorded in the current month, index 1 + * contains the maximum nonfatal error recorded last month, etc. + * + * Possible status values returned are: + * NV_OK + * If any nonfatal error rates are valid upon return. + * NV_ERR_INVALID_ARGUMENT + * If the linkId parameter does not specify a valid link. + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on this GPU or NVLINK nonfatal error rates + * are not recorded in non-volatile storage. + */ +#define NV2080_CTRL_CMD_NVLINK_GET_LINK_NONFATAL_ERROR_RATES (0x2080300aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS_MESSAGE_ID" */ + +typedef struct NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE { + NvU32 errorsPerMinute; + NvU32 timestamp; +} NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE; + +#define NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE_ENTRIES 5U + +#define NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS { + NvU32 linkId; + NvU32 numDailyMaxNonfatalErrorRates; + NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE dailyMaxNonfatalErrorRates[NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE_ENTRIES]; + NvU32 numMonthlyMaxNonfatalErrorRates; + NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE monthlyMaxNonfatalErrorRates[NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE_ENTRIES]; +} NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_SET_ERROR_INJECTION_MODE + * + * This command sets the injection mode so that error handling and error + * logging software can be aware that errors cropping up on links are + * intentional and not due to HW failures. + * + * [in] bEnabled + * This parameter specifies whether injection mode should be enabled or + * disabled. + * + * Possible status values returned are: + * NV_OK + * If injection mode is enabled or disabled according to the parameters. + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on this GPU. + */ +#define NV2080_CTRL_CMD_NVLINK_SET_ERROR_INJECTION_MODE (0x2080300bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS { + NvBool bEnabled; +} NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_SETUP_EOM + * + * This command passes a packed 32bit params value to NV_PMINION_MISC_0_SCRATCH_SWRW_0 + * and then issues an EOM DLCMD to minion for the desired link. Only one DLCMD + * at a time can be issued to any given link. + * + * Params Packing is specified in Minion IAS + */ +#define NV2080_CTRL_CMD_NVLINK_SETUP_EOM (0x2080300cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS { + NvU8 linkId; + NvU32 params; +} NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_SET_POWER_STATE + * + * This command sets the mask of links associated with the GPU + * to a target power state + * + * [in] linkMask (This field will be deprecated in the future, please use links) + * Mask of links that will be put to desired power state + * Note: In Turing RM supports only tansitions into/out of L2 + * + * [in] links + * Mask of links that will be put to desired power state + * Note: In Turing RM supports only tansitions into/out of L2 + * + * [in] powerState + * Target power state to which the links will transition + * This can be any one of NV2080_CTRL_NVLINK_POWER_STATE_* states + * + * Possible status values returned are: + * NV_OK + * If all links transitioned successfully to the target state + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip or if the power state + * is not enabled on the chip + * NV_ERR_INVALID_ARGUMENT + * If the any of the links in the mask is not enabled + * NV_ERR_INVALID_REQUEST + * If the power state transition is not supported + * NV_WARN_MORE_PROCESSING_REQUIRED + * Link has received the request for the power transition + * The transition will happen when the remote end also agrees + * + * Note: Currently only L0->L2 and L2->L0 is supported + */ +#define NV2080_CTRL_CMD_NVLINK_SET_POWER_STATE (0x2080300dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS { + NvU32 linkMask; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8); + NvU32 powerState; +} NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS; + +// NVLink Power States +#define NV2080_CTRL_NVLINK_POWER_STATE_L0 (0x00U) +#define NV2080_CTRL_NVLINK_POWER_STATE_L1 (0x01U) +#define NV2080_CTRL_NVLINK_POWER_STATE_L2 (0x02U) +#define NV2080_CTRL_NVLINK_POWER_STATE_L3 (0x03U) + +/* + * NV2080_CTRL_CMD_NVLINK_GET_POWER_STATE + * + * This command gets the power state of a link associated + * with the GPU + * + * [in] linkId + * Link whose power state is being requested + * [out] powerState + * Current power state of the link + * Is any one the NV2080_CTRL_NVLINK_POWER_STATE_* states + * + * Possible status values returned are: + * NV_OK + * If the power state is retrieved successfully + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip + * NV_ERR_INVALID_ARGUMENT + * If the link is not enabled on the GPU + * NV_ERR_INVALID_STATE + * If the link is in an invalid state + */ +#define NV2080_CTRL_CMD_NVLINK_GET_POWER_STATE (0x2080300eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS { + NvU32 linkId; + NvU32 powerState; +} NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_INJECT_TLC_ERROR + * + * This command injects TLC_*_REPORT_INJECT error. An RM interrupt + * will be triggered after injection. Currently the injection call + * only deals with HW_ERR, UR_ERR, PRIV_ERR in TX_SYS and RX_LNK devices + * + * [in] linkId + * Link whose power state is being requested. + * [in] errorType + * error type that needs to be injected. + * [in] device + * The device this injection is intended for. + * [in] bBroadcast + * Whether the link report error should be fired in multiple links. + + * Possible status values returned are: + * NV_OK + * If the injection succeeds. + * NV_ERR_NOT_SUPPORTED + * If the error type of NVLINK is not supported on the chip + */ +#define NV2080_CTRL_CMD_NVLINK_INJECT_TLC_ERROR (0x2080300fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE { + TLC_RX_LNK = 0, + TLC_TX_SYS = 1, +} NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE; + +typedef enum NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE { + TX_SYS_TX_RSP_STATUS_HW_ERR = 0, + TX_SYS_TX_RSP_STATUS_UR_ERR = 1, + TX_SYS_TX_RSP_STATUS_PRIV_ERR = 2, +} NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE; + +typedef enum NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE { + RX_LNK_RX_RSP_STATUS_HW_ERR = 0, + RX_LNK_RX_RSP_STATUS_UR_ERR = 1, + RX_LNK_RX_RSP_STATUS_PRIV_ERR = 2, +} NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE; + +typedef union NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE { + NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE txSysErrorType; + NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE rxLnkErrorType; +} NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE; + + +#define NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS { + NvU32 linkId; + NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE device; + NvBool bBroadcast; + NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE errorType; +} NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS; + + + +/* + * NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES + * + * This command returns the per-lane Figure Of Merit (FOM) Values from a link + * + * [in] linkId + * The NVLink link ID to report FOM values for + * [out] numLanes + * This field specifies the no. of lanes per link + * [out] figureOfMeritValues + * This field contains the FOM values per lane + * + */ +#define NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES (0x20803011U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_MAX_LANES 4U + +#define NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS { + NvU32 linkId; + NvU8 numLanes; + NvU16 figureOfMeritValues[NV2080_CTRL_NVLINK_MAX_LANES]; +} NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS; + +/* + * NV2080_CTRL_NVLINK_SET_NVLINK_PEER + * + * This command sets/unsets the USE_NVLINK_PEER bit for a given + * mask of peers + * + * [in] peerMask + * Mask of Peer IDs for which USE_NVLINK_PEER needs to be updated + * [in] bEnable + * Whether the bit needs to be set or unset + * + * Possible status values returned are: + * NV_OK + * If the USE_NVLINK_PEER bit was updated successfully + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip, or + * If unsetting USE_NVLINK_PEER bit is not supported + * + * NOTE: This is only supported on Windows + * + */ +#define NV2080_CTRL_CMD_NVLINK_SET_NVLINK_PEER (0x20803012U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS { + NvU32 peerMask; + NvBool bEnable; +} NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_READ_UPHY_PAD_LANE_REG + * + * This command packs the lane and addr values into NV_PMINION_MISC_0_SCRATCH_SWRW_0 + * and then issues a READPADLANEREG DLCMD to minion for the desired link. Only one DLCMD + * at a time can be issued to any given link. + * + * After this command completes it is necessary to read the appropriate + * NV_PNVL_BR0_PAD_CTL_7_CFG_RDATA register to retrieve the results of the read + * Only GV100 should read NV_PNVL_BR0_PAD_CTL_7_CFG_RDATA. + * From TU102+ the ctrl the required data would be updated in phyConfigData. + * + * [in] linkId + * Link whose pad lane register is being read + * [in] lane + * Lane whose pad lane register is being read + * [in] addr + * Address of the pad lane register to read + * [out] phyConfigData + * Provides phyconfigaddr and landid + * + * Possible status values returned are: + * NV_OK + * If the minion command completed successfully + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip + * NV_ERR_INVALID_ARGUMENT + * If the link is not enabled on the GPU or the lane is invalid + * NV_ERR_TIMEOUT + * If a timeout occurred waiting for minion response + */ +#define NV2080_CTRL_CMD_NVLINK_READ_UPHY_PAD_LANE_REG (0x20803013U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS { + NvU8 linkId; + NvU8 lane; + NvU16 addr; + NvU32 phyConfigData; +} NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS; + +/* + * Structure to store the ECC error data. + * valid + * Is the lane valid or not + * eccErrorValue + * Value of the Error. + * overflowed + * If the error overflowed or not + */ +typedef struct NV2080_CTRL_NVLINK_LANE_ERROR { + NvBool bValid; + NvU32 eccErrorValue; + NvBool overflowed; +} NV2080_CTRL_NVLINK_LANE_ERROR; + +/* + * Structure to store ECC error data for Links + * errorLane array index corresponds to the lane number. + * + * errorLane[] + * Stores the ECC error data per lane. + */ +typedef struct NV2080_CTRL_NVLINK_LINK_ECC_ERROR { + NV2080_CTRL_NVLINK_LANE_ERROR errorLane[NV2080_CTRL_NVLINK_MAX_LANES]; + NvU32 eccDecFailed; + NvBool eccDecFailedOverflowed; +} NV2080_CTRL_NVLINK_LINK_ECC_ERROR; + +/* + * NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS + * + * Control to get the values of ECC ERRORS + * + * Parameters: + * linkMask [IN] (This field will be deprecated in the future, please use links) + * Links on which the ECC error data requested + * A valid link/port mask returned by the port masks returned by + * NVSWITCH_GET_INFO + * links [IN] + * Links on which the ECC error data requested + * A valid link/port mask returned by the port masks returned by + * NVSWITCH_GET_INFO + * errorLink[] [OUT] + * Stores the ECC error related information for each link. + * errorLink array index corresponds to the link Number. + */ + +#define NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS { + NvU32 linkMask; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8); + NV2080_CTRL_NVLINK_LINK_ECC_ERROR errorLink[NV2080_CTRL_NVLINK_MAX_ARR_SIZE]; +} NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS; + + +#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_ECC_ERRORS (0x20803014U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS_MESSAGE_ID" */ + +// Nvlink throughput counters reading data flits in TX +#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_TX 0U + +// Nvlink throughput counters reading data flits in RX +#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_RX 1U + +// Nvlink throughput counters reading all flits in TX +#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_TX 2U + +// Nvlink throughput counters reading all flits in RX +#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_RX 3U + +#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_MAX 4U + +/* + * NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS + * + * Reads reserved monotonically increasing NVLINK throughput counters for given linkIds + * + * [in] counterMask + * Mask of counter types to be queried + * One of NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_* macros + * [in] linkMask (This field will be deprecated in the future, please use links) + * Mask of links to be queried + * [in] links + * Mask of links to be queried + * [out] value + * Throughput counter value returned + * + * Possible status values returned are: + * NV_OK + * If command completed successfully + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip + * NV_ERR_INVALID_ARGUMENT + * If numLinks is out-of-range or requested link is inactive + * + * Note: + * The following commands will be deprecated in favor of NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS: + * NV90CC_CTRL_CMD_NVLINK_GET_COUNTERS + * NV2080_CTRL_CMD_NVLINK_GET_COUNTERS + * Other commands that will be deprecated due to the change in design: + * NV90CC_CTRL_CMD_NVLINK_RESERVE_COUNTERS + * NV90CC_CTRL_CMD_NVLINK_RELEASE_COUNTERS + * NV90CC_CTRL_CMD_NVLINK_SET_COUNTERS_FROZEN + * NV90CC_CTRL_CMD_NVLINK_GET_TL_COUNTER_CFG + * NV90CC_CTRL_CMD_NVLINK_SET_TL_COUNTER_CFG + * NV90CC_CTRL_CMD_NVLINK_CLEAR_COUNTERS + * + * Also, note that there is no counter overflow handling for these calls. + * These counters would be counting in flits and assuming 25GB/s bandwidth per link, + * with traffic flowing continuously, it would take 174 years for overflow to happen. + * It is reasonable to assume an overflow will not occur within the GPU operation, + * given that the counters get reset at system reboot or GPU reset. Counters are 63-bit. + */ + +typedef struct NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES { + NV_DECLARE_ALIGNED(NvU64 value[NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_MAX], 8); +} NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES; + +#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS { + NvU16 counterMask; + NV_DECLARE_ALIGNED(NvU64 linkMask, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES counters[NV2080_CTRL_NVLINK_MAX_ARR_SIZE], 8); +} NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS (0x20803015U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE + * + * This command locks the link power state so that RM doesn't modify the state + * of the link during pstate switch. + * + * [in] linkMask Links for which power mode needs to be locked. + */ +#define NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE (0x20803016U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS { + NvBool bLockPowerMode; +} NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS; + +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_NVHS 0U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_EIGHTH 1U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_OTHER 2U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_ENTER 3U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_EXIT 4U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_SLEEP 5U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_HS_TIME 6U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_EXIT_TIME 7U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_ENTRY_TIME 8U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_EXIT_TIME 9U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_ENTRY_TIME 10U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_EXIT_TIME 11U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_ENTRY_TIME 12U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_EXIT_TIME 13U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_ENTRY_TIME 14U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_OTHER_STATE_TIME 15U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS 16U + +/* + * NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS + * + * Reads NVLINK low power counters for given linkId + * + * [in] linkId + * ID of the link to be queried + * [in,out] counterValidMask + * Mask of valid counters + * [out] counterValues + * Low power counter values returned + * + * Possible status values returned are: + * NV_OK + * If command completed successfully + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip + * NV_ERR_INVALID_ARGUMENT + * If linkId is out-of-range or requested link is inactive + */ + +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS { + NvU32 linkId; + NvU32 counterValidMask; + NvU32 counterValues[NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS]; +} NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS (0x20803018U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_NVLINK_CLEAR_LP_COUNTERS (0x20803052U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8 | 0x52)" */ + + +// +// Set the near end loopback mode using the following +// Currently, three modes - NEA, NEDR, NEW +// +#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_DEFAULT (0x00000000) +#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEA (0x00000001) +#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDR (0x00000002) +#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDW (0x00000003) +#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PHY_REMOTE (0x00000004) +#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PHY_LOCAL (0x00000005) +#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_EXT_LOCAL (0x00000006) + +/* + * NV2080_CTRL_CMD_NVLINK_SET_LOOPBACK_MODE + * + * Generic NvLink callback for MODS + * + * [In] linkdId + * ID of the link to be used + * [In] loopbackMode + * This value will decide which loopback mode need to + * set on the specified link. + * Modes are NEA / NEDR / NEDW + */ +#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS_MESSAGE_ID (0x23U) + +typedef struct NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS { + NvU32 linkId; + NvU8 loopbackMode; +} NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_SET_LOOPBACK_MODE (0x20803023U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS_MESSAGE_ID" */ + +// +// Read Refresh counter - the pass/fail occurrences +// + +typedef struct NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO { + // requested links or not + NvBool bValid; + + // counters + NvU16 passCount; + NvU16 failCount; +} NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO; + +#define NV2080_CTRL_NVLINK_MAX_LINK_COUNT 32 + +/* + * NV2080_CTRL_CMD_NVLINK_GET_REFRESH_COUNTERS + * + * + * [In] linkMask (This field will be deprecated in the future, please use links) + * Specifies for which links we want to read the counters + * [In] links + * Specifies for which links we want to read the counters + * [Out] refreshCountPass + * Count of number of times PHY refresh pass + * [Out] refreshCountFail + * Count of number of times PHY refresh fail + */ +#define NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS_MESSAGE_ID (0x28U) + +typedef struct NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS { + NvU32 linkMask; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8); + NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO refreshCount[NV2080_CTRL_NVLINK_MAX_LINK_COUNT]; +} NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_REFRESH_COUNTERS (0x20803028U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS_MESSAGE_ID" */ + +// +// Clear Refresh counter - the pass/fail occurrences +// + +/* + * NV2080_CTRL_CMD_NVLINK_CLEAR_REFRESH_COUNTERS + * + * + * [In] linkMask (This field will be deprecated in the future, please use links) + * Specifies for which links we want to clear the counters + * [In] links + * Specifies for which links we want to clear the counters + */ +#define NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS_MESSAGE_ID (0x29U) + +typedef struct NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS { + NvU32 linkMask; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8); +} NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_CLEAR_REFRESH_COUNTERS (0x20803029U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_GET_SET_NVSWITCH_FLA_ADDR + * + * Get/Set NVSwitch FLA address + * + * [In] bGet + * Whether to get or set the NVSwitch FLA address + * [In/Out] addr + * Address that is to be set or retrieved. + */ +#define NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS_MESSAGE_ID (0x38U) + +typedef struct NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS { + NvBool bGet; + NV_DECLARE_ALIGNED(NvU64 addr, 8); +} NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_SET_NVSWITCH_FLA_ADDR (0x20803038) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO + * + * Syncs the different link masks and vbios defined values between CPU-RM and GSP-RM + * + * [in] discoveredLinks (This field will be deprecated in the future, please use discoveredLinkMask) + * Mask of links discovered from IOCTRLs + * + * [in] discoveredLinkMask + * Mask of links discovered from IOCTRLs + * + * [in] connectedLinksMask (This field will be deprecated in the future, please use connectedLinks) + * Mask of links which are connected (remote present) + * + * [in] connectedLinks + * Mask of links which are connected (remote present) + * + * [in] bridgeSensableLinks (This field will be deprecated in the future, please use bridgeSensableLinkMask) + * Mask of links whose remote endpoint presence can be sensed + * + * [in] bridgeSensableLinkMask + * Mask of links whose remote endpoint presence can be sensed + * + * [in] bridgedLinks (This field will be deprecated in the future, please use bridgedLinkMask) + * Mask of links which are connected (remote present) + * Same as connectedLinksMask, but also tracks the case where link + * is connected but marginal and could not initialize + * + * [in] bridgedLinkMask + * Mask of links which are connected (remote present) + * Same as connectedLinks, but also tracks the case where link + * is connected but marginal and could not initialize + * + * [out] initDisabledLinksMask (This field will be deprecated in the future, please use initDisabledLinks) + * Mask of links for which initialization is disabled + * + * [out] initDisabledLinks + * Mask of links for which initialization is disabled + * + * [out] vbiosDisabledLinkMask (This field will be deprecated in the future, please use vbiosDisabledLinks) + * Mask of links disabled in the VBIOS + * + * [out] vbiosDisabledLinks + * Mask of links disabled in the VBIOS + * + * [out] initializedLinks (This field will be deprecated in the future, please use initializedLinkMask) + * Mask of initialized links + * + * [out] initializedLinkMask + * Mask of initialized links + * + * [out] bEnableTrainingAtLoad + * Whether the links should be trained to active during driver load + * + * [out] bEnableSafeModeAtLoad + * Whether the links should be initialized to swcfg during driver load + */ + +#define NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS_MESSAGE_ID (0x39U) + +typedef struct NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 discoveredLinks, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK discoveredLinkMasks, 8); + NvU32 connectedLinksMask; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK connectedLinks, 8); + NV_DECLARE_ALIGNED(NvU64 bridgeSensableLinks, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK bridgeSensableLinkMasks, 8); + NvU32 bridgedLinks; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK bridgedLinkMasks, 8); + NvU32 initDisabledLinksMask; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK initDisabledLinks, 8); + NV_DECLARE_ALIGNED(NvU64 vbiosDisabledLinkMask, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK vbiosDisabledLinks, 8); + NvU32 initializedLinks; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK initializedLinkMasks, 8); + NvBool bEnableTrainingAtLoad; + NvBool bEnableSafeModeAtLoad; +} NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO (0x20803039U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS + * + * Enable pre-topology setup on the mask of enabled links + * This command accepts no parameters. + */ + +#define NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS (0x2080303aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | 0x3a" */ + +/* + * NV2080_CTRL_CMD_NVLINK_PROCESS_INIT_DISABLED_LINKS + * + * Process the init disabled NVLinks and filter those out + * + * [in/out] initDisabledLinksMask (This field will be deprecated in the future, please use initDisabledLinks) + * Mask of links initdisabled on a given GPU + * + * [in/out] initDisabledLinks + * Mask of links initdisabled on a given GPU + * + * [in] bSkipHwNvlinkDisable + * Whether to consider skipping the HW initdisable links + */ + +#define NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS_MESSAGE_ID (0x3bU) + +typedef struct NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS { + NvU32 initDisabledLinksMask; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK initDisabledLinks, 8); + NvBool bSkipHwNvlinkDisable; +} NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_PROCESS_INIT_DISABLED_LINKS (0x2080303bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_EOM_CONTROL + * + * cmd [IN] enum identifying the EOM related command for the driver to process + * link [IN] linkId + * params [IN] NvU32 word that is written into NV_PMINION_SCRATCH_SWRW_0 before calling CONFIGEOM dlcmd + * measurements [OUT] output of EOM + * + * Params Packing is specified in Minion IAS + */ + +typedef enum NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND { + NVLINK_EOM_CONTROL_START_EOM = 0, + NVLINK_EOM_CONTROL_END_EOM = 1, + NVLINK_EOM_CONTROL_CONFIG_EOM = 2, + NVLINK_EOM_CONTROL_FULL_EOM_SEQUENCE = 3, +} NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND; + +typedef struct NV2080_CTRL_NVLINK_EOM_MEASUREMENT { + NvU8 upper; + NvU8 middle; + NvU8 lower; + NvU8 composite; +} NV2080_CTRL_NVLINK_EOM_MEASUREMENT; + +#define NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID (0x3cU) + +typedef struct NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS { + NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND cmd; + NvU32 linkId; + NvU32 params; + NV2080_CTRL_NVLINK_EOM_MEASUREMENT measurements[NV2080_CTRL_NVLINK_MAX_LANES]; +} NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_EOM_CONTROL (0x2080303c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID" */ + +/*! + * Inband Received Data + */ +#define NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE 5120 +#define NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_MESSAGE_ID (0x3dU) + +typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS { + NvU8 data[NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE]; + NvU32 dataSize; +} NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS; + +#define NV2080_CTRL_CMD_READ_NVLINK_INBAND_RESPONSE (0x2080303d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_L1_THRESHOLD_VALUE_DEFAULT (0xFFFFFFFF) + +/* + * NV2080_CTRL_CMD_NVLINK_SET_L1_THRESHOLD + * + * This command is used to set the L1 threshold value. + * A value of NV2080_CTRL_NVLINK_L1_THRESHOLD_VALUE_DEFAULT + * will reset the L1 Threshold to the default values. + * + * [in] l1Threshold + * Used to set the L1 threshold value + * + * [in] l1ExitThreshold + * Used to set the L1 Exit threshold value + */ +#define NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS_MESSAGE_ID (0x3eU) + +typedef struct NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS { + NvU32 l1Threshold; + NvU32 l1ExitThreshold; +} NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_SET_L1_THRESHOLD (0x2080303eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_GET_L1_THRESHOLD + * + * This command is used to get the L1 threshold value + * + * [out] l1Threshold + * Used to get the L1 threshold value + * + * [out] l1ExitThreshold + * Used to get the L1 Exit Thrshold value + */ +#define NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS_MESSAGE_ID (0x3fU) + +typedef struct NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS { + NvU32 l1Threshold; + NvU32 l1ExitThreshold; + NvBool bL1Enabled; + NvBool bL1ThermThrottlingEnabled; +} NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_L1_THRESHOLD (0x2080303fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_INBAND_SEND_DATA + * + * RPC for sending Inband data + * + * [In] data[] + * data to be sent over inband + * [In] dataSize + * Size of valid data in data array + */ +#define NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID (0x40U) + +typedef struct NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS { + NvU8 buffer[NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE]; + NvU32 dataSize; +} NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_INBAND_SEND_DATA (0x20803040U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_IS_GPU_DEGRADED + * + * RPC for Getting GPU degraded status upon link error + * + * [In] linkId + * Id of the link on which error occured + * [Out] bIsGpuDegraded + * Boolean to track corresponding GPU is degraded or not + */ +#define NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID (0x41U) + +typedef struct NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS { + NvU32 linkId; + NvBool bIsGpuDegraded; +} NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_IS_GPU_DEGRADED (0x20803041U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_DIRECT_CONNECT_CHECK + * + * This command is used to check for missing + * bridge/nvlink for direct connect GPU + * + * [out] bIsEnoughNvLink + * Check if number of active nvlink meet the minimum requirements. + * [out] numBridge + * Number of NVLink bridge + * [out] bridgePresenceMask + * Bit mask of NVLink bridges's presence + */ +#define NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS_MESSAGE_ID (0x42U) + +typedef struct NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS { + NvBool bIsEnoughNvLink; + NvU32 numBridge; + NvU32 bridgePresenceMask; +} NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_DIRECT_CONNECT_CHECK (0x20803042U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_POST_FAULT_UP + * + * This command is to trigger the next sequence after the 10 sec delay + * + * [out] linkId + * Link number which the sequence should be triggered + */ +#define NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS_MESSAGE_ID (0x43U) + +typedef struct NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS { + NvU32 linkId; +} NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_POST_FAULT_UP (0x20803043U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_PORT_EVENT_COUNT_SIZE 64U + +/* +* Structure to store port event information +* +* portEventType +* Type of port even that occurred: NVLINK_PORT_EVENT_TYPE* +* +* gpuId +* Gpu that port event occurred on +* +* linkId +* Link id that port event occurred on +* +* time +* Platform time (nsec) when event occurred +*/ +typedef struct NV2080_CTRL_NVLINK_PORT_EVENT { + NvU32 portEventType; + NvU32 gpuId; + NvU32 linkId; + NV_DECLARE_ALIGNED(NvU64 time, 8); +} NV2080_CTRL_NVLINK_PORT_EVENT; + +/* +* NV2080_CTRL_CMD_NVLINK_GET_PORT_EVENTS +* +* This command returns the port up and port down events that have occurred +* +* Parameters: +* +* portEventIndex [IN/OUT] +* On input: The index of the first port event at which to start reading out of the driver. +* +* On output: The index of the first port event that wasn't reported through the 'port event' array +* in this call to NV2080_CTRL_CMD_NVLINK_GET_PORT_EVENTS. +* +* nextPortEventIndex[OUT] +* The index that will be assigned to the next port event that occurs. +* Users of the GET_PORT_EVENTS control call may set 'portEventIndex' to this field on initialization +* to bypass port events that have already occurred without making multiple control calls. +* +* portEventCount [OUT] +* Number of port events returned by the call. Currently, portEventCount is limited +* by NV2080_CTRL_NVLINK_PORT_EVENT_COUNT_SIZE. In order to query all the port events, a +* client needs to keep calling the control till portEventCount is zero. +* +* bOverflow [OUT] +* True when the port event log is overflowed and no longer contains all the port +* events that have occurred, false otherwise. +* +* portEvent [OUT] +* The port event entires. +*/ +#define NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS_MESSAGE_ID (0x44U) + +typedef struct NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 portEventIndex, 8); + NV_DECLARE_ALIGNED(NvU64 nextPortEventIndex, 8); + NvU32 portEventCount; + NvBool bOverflow; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_PORT_EVENT portEvent[NV2080_CTRL_NVLINK_PORT_EVENT_COUNT_SIZE], 8); +} NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_PORT_EVENTS (0x20803044U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS_MESSAGE_ID" */ + +/* +* NV2080_CTRL_CMD_NVLINK_CYCLE_LINK +* +* This command cycles a link by faulting it and then retraining the link +* +* Parameters: +* +* linkId [IN] +* The link id of the link to be cycled +*/ +#define NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS_MESSAGE_ID (0x45U) + +typedef struct NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS { + NvU32 linkId; +} NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_CYCLE_LINK (0x20803045U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG + * + * This command is to check if a GPU has a reduced nvlink configuration + * + * [out] bReducedNvlinkConfig + * Link number which the sequence should be triggered + */ +#define NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID (0x46U) + +typedef struct NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS { + NvBool bReducedNvlinkConfig; +} NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG (0x20803046U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID" */ + + +#define NV2080_CTRL_NVLINK_PRM_ACCESS_MAX_LENGTH 496U + +typedef struct NV2080_CTRL_NVLINK_PRM_DATA { + NvU8 data[NV2080_CTRL_NVLINK_PRM_ACCESS_MAX_LENGTH]; +} NV2080_CTRL_NVLINK_PRM_DATA; + +#define NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_COUNTERS (0x20803074U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS_MESSAGE_ID (0x74U) + +typedef struct NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 counterMask[NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS], 8); +} NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS; +/* + * NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS + * + * This command returns platform-specific information related to the GPU's NVLink setup. + * + * ibGuid + * Infiniband GUID reported by platform (for Blackwell, ibGuid is 8 bytes so indices 8-15 are zero) + * rackGuid + * GUID of the rack containing this GPU (for Blackwell rackGuid is 13 bytes so indices 13-15 are zero) + * chassisPhysicalSlotNumber + * The slot number in the rack containing this GPU (includes switches) + * computeSlotIndex + * The index within the compute slots in the rack containing this GPU (does not include switches) + * nodeIndex + * Index of the node within the slot containing this GPU + * peerType + * Platform indicated NVLink-peer type (e.g. switch present or not) + * moduleId + * ID of this GPU within the node + * nvlinkSignalingProtocol // Deprecated + * signaling protocol used for this platform + */ + +#define NV2080_CTRL_CMD_NVLINK_GET_PLATFORM_INFO (0x20803083U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS_MESSAGE_ID (0x83U) + +typedef struct NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS { + NvU8 ibGuid[16]; + NvU8 rackGuid[16]; + NvU8 chassisPhysicalSlotNumber; + NvU8 computeSlotIndex; + NvU8 nodeIndex; + NvU8 peerType; + NvU8 moduleId; + NvU8 nvlinkSignalingProtocol; + NvU8 linksPerSpigot; +} NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS; + +/* + * Structure to store UPHY cmd data. + * laneId + * Lane ID for specified link + * address + * Desired address for read + */ +typedef struct NV2080_CTRL_NVLINK_UPHY_CLN_CMD { + NvU8 pllIndex; + NvU16 address; +} NV2080_CTRL_NVLINK_UPHY_CLN_CMD; + +/* + * NV2080_CTRL_CMD_NVLINK_READ_UPHY_CLN + * + * + * This command retrieves the land id cln select, lane id, and pll index. + * + * [in] linkMask (This field will be deprecated in the future, please use links) + * Mask of links whose uphy should be read + * [in] links + * Mask of links whose uphy should be read + * [in] uphyCmd + * Array of input data (pll index and address) for each link, + * where index 0 represents link 0's pll index + * and index 16 represents link 16's pll index. + * [out] data + * Data from uphy cln for each link where index 0 represents link 0's pll index + * and index 16 represents link 16's pll index. + * + * Possible status values returned are: + * NV_OK + * If the minion command completed successfully + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip + * NV_ERR_INVALID_ARGUMENT + * If the link is not enabled on the GPU or the lane is invalid + * NV_ERR_TIMEOUT + * If a timeout occurred waiting for minion response + */ +#define NV2080_CTRL_CMD_NVLINK_READ_UPHY_CLN (0x20803084U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS_MESSAGE_ID (0x84U) + +typedef struct NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS { + NvU32 linkMask; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8); + NV2080_CTRL_NVLINK_UPHY_CLN_CMD uphyCmd[NV2080_CTRL_NVLINK_MAX_LINKS]; + NvU32 data[NV2080_CTRL_NVLINK_MAX_LINKS]; +} NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS; + +#define NV2080_CTRL_NVLINK_SUPPORTED_MAX_BW_MODE_COUNT 23U + +/* + * NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_BW_MODE + * + * This command gets the supported RBMs of the GPU + * + * [out] rbmModesList + * List of supported RBM modes + * [out] rbmTotalModes + * Total RBM modes supported + * Possible status values returned are: TODO: Update this + * NV_OK + * If the BW mode is retrieved successfully + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip + * NV_ERR_INVALID_ARGUMENT + * If the link is not enabled on the GPU + * NV_ERR_INVALID_STATE + * If the link is in an invalid state + */ +#define NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_BW_MODE (0x20803085U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS_MESSAGE_ID (0x85U) + +typedef struct NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS { + NvU16 rbmModesList[NV2080_CTRL_NVLINK_SUPPORTED_MAX_BW_MODE_COUNT]; + NvU8 rbmTotalModes; +} NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_SET_BW_MODE_POLL_TIMEOUT_MS_INVALID 0 + +/* + * NV2080_CTRL_CMD_NVLINK_SET_BW_MODE + * + * This command sets the requested RBM of the GPU + * GB100 -- Control call is synchronous and will try to set the RBM mode within the control handling + * + * [in] rbmMode + * Possible Legacy values that can be set in bits 2:0: + * NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_FULL + * NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_OFF + * NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_MIN + * NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_HALF + * NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_3QUARTER + * Blackwell bits 3:7 can be used to specify link count + * bits 8:15 are reserved + * [in] bForceSync + * Force synchronous behavior + * [out] rbmSetPollTimeoutMs + * timeout value for client to poll for RBM to complete. + * This will be set to NV2080_CTRL_CMD_NVLINK_SET_BW_MODE_POLL_TIMEOUT_MS_INVALID if + * synchronous behavior is applied + * + * Possible status values returned are: TODO: Update this + * NV_OK + * If the BW mode is set successfully + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip + * NV_ERR_INVALID_ARGUMENT + * If the link is not enabled on the GPU + * NV_ERR_INVALID_STATE + * If the link is in an invalid state + */ +#define NV2080_CTRL_CMD_NVLINK_SET_BW_MODE (0x20803086U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS_MESSAGE_ID (0x86U) + +typedef struct NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS { + NvU16 rbmMode; + NvBool bForceSync; + NvU32 rbmSetPollTimeoutMs; +} NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_BW_MODE + * + * This command gets the set RBM of the GPU + * + * [out] rbmMode + * RBM mode currently set + * + * Possible status values returned are: TODO: Update this + * NV_OK + * If the BW mode is set successfully + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip + * NV_ERR_INVALID_ARGUMENT + * If the link is not enabled on the GPU + * NV_ERR_INVALID_STATE + * If the link is in an invalid state + */ +#define NV2080_CTRL_CMD_NVLINK_GET_BW_MODE (0x20803087U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS_MESSAGE_ID (0x87U) + +typedef struct NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS { + NvU16 rbmMode; +} NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_LOCAL_DEVICE_INFO + * + * localDeviceInfo + * NVLINK-relevant information about the device + */ + +#define NV2080_CTRL_CMD_NVLINK_GET_LOCAL_DEVICE_INFO (0x20803088U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS_MESSAGE_ID (0x88U) + +typedef struct NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_DEVICE_INFO localDeviceInfo, 8); +} NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_INJECT_SW_ERROR + * + * This command is used to inject NVL5 ERROR_INJECT_V2 commands + * + * [in] links + * link mask of which links to inject the error on + * [out] + * Error Types to be injected + * + * Possible status values returned are: + * NV_OK + * If the Error is injected successfully + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip + * NV_ERR_INVALID_ARGUMENT + * If the link is not enabled on the GPU + * NV_ERR_INVALID_STATE + * If the link is in an invalid state + */ +#define NV2080_CTRL_CMD_NVLINK_INJECT_SW_ERROR (0x20803089U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS_MESSAGE_ID" */ +typedef enum NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY { + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_NONFATAL = 0, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_APP_FATAL = 1, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_FATAL = 2, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_DEGRADATION = 3, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_WATCHDOG_TIMEOUT = 4, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_NON_FATAL = 5, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MSE = 6, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_NON_FATAL = 7, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_FATAL = 8, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_PRIV_ERR = 9, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_NON_FATAL = 10, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_FATAL = 11, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TREX_NON_FATAL = 12, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_NON_FATAL = 13, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_FATAL = 14, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_NON_FATAL = 15, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_FATAL = 16, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_NON_FATAL = 17, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_FATAL = 18, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_NON_FATAL = 19, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_FATAL = 20, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_FATAL = 21, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MAX = 22, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_MVB_NON_FATAL = 23, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_MVB_FATAL = 24, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_MVB_NON_FATAL = 25, + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_MVB_FATAL = 26, +} NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY; + +#define NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS_MESSAGE_ID (0x89U) + +typedef struct NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS { + NvU32 linkMask; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8); + NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY severity; +} NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS; + +/* + * NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY + * + * This command is used to update the NVLE topology in GSP RM + * + * [in] localGpuAlid + * ALID of local GPU in P2P object + * [in] localGpuClid + * CLID of local GPU in P2P object + * [in] remoteGpuAlid + * ALID of remote GPU in P2P object + * [in] remoteGpuClid + * CLID of remote GPU in P2P object + * [in] bNvleQualMode + * Implies NVLE Qual mode, which would be using hardcoded keys + * [in] localGpuPlatformInfo + * Platform information for the local GPU + * [in] remoteGpuPlatformInfo + * Platform information for the remote GPU + */ +#define NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY (0x2080308cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS_MESSAGE_ID (0x8cU) + +typedef struct NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS { + NvU32 localGpuAlid; + NvU32 localGpuClid; + NvU32 remoteGpuAlid; + NvU32 remoteGpuClid; + NvBool bNvleQualMode; + NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS localGpuPlatformInfo; + NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS remoteGpuPlatformInfo; +} NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS; + +/* + * Structure to store the NVLE ALID and the corresponding mapped CLID + * + * [in] alid + * Represents the ALID + * [in] clid + * Represents the corresponding CLID + */ +typedef struct NV2080_CTRL_NVLINK_NVLE_ALID_CLID_MAP { + NvU32 alid; + NvU32 clid; +} NV2080_CTRL_NVLINK_NVLE_ALID_CLID_MAP; + +#define NV2080_CTRL_NVLINK_MAX_REMAP_TABLE_ENTRIES 32U + +#define NV2080_CTRL_NVLINK_MAX_REMAP_TABLE_ENTRIES_V2 4096U +#define NV2080_CTRL_NVLINK_REMAP_TABLE_ENTRIES_CHUNK 128U +#define NV2080_CTRL_NVLINK_MAX_ALID_CLID_TABLE_ENTRIES 128U + +/* + * Structure to store the NVLE ALID-CLID maps + * + * [in] alidClidMap + * Array of NV2080_CTRL_NVLINK_NVLE_ALID_CLID_MAP + * [in] numEntries + * Represents the number of entries in the ALID-CLID table + */ +typedef struct NV2080_CTRL_NVLINK_NVLE_ALID_CLID_TABLE { + NV2080_CTRL_NVLINK_NVLE_ALID_CLID_MAP alidClidMap[NV2080_CTRL_NVLINK_MAX_REMAP_TABLE_ENTRIES]; + NvU32 numEntries; +} NV2080_CTRL_NVLINK_NVLE_ALID_CLID_TABLE; + +/* + * Structure to store the NVLE ALID-CLID maps - version 2 to handle more ALID-CLID mappings + * + * [in] alidClidMap + * Array of NV2080_CTRL_NVLINK_NVLE_ALID_CLID_MAP + * [in] numEntries + * Represents the number of entries in the ALID-CLID table + */ +typedef struct NV2080_CTRL_NVLINK_NVLE_ALID_CLID_TABLE_V2 { + NV2080_CTRL_NVLINK_NVLE_ALID_CLID_MAP alidClidMap[NV2080_CTRL_NVLINK_MAX_ALID_CLID_TABLE_ENTRIES]; + NvU32 numEntries; +} NV2080_CTRL_NVLINK_NVLE_ALID_CLID_TABLE_V2; + +/* + * NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS + * + * This command is used for the following operations. + * If getting the LID information, the command gets the ALID and CLID of the GPU. + * If setting the LID information, the command passes the complete ALID-CLID map. + * The also command returns the status of whether the CLIDs are updated in the remap tables. + * + * [in] bGet + * Whether to get the ALIDs or set the CLIDs in the remap table or update the LIDs in the remap tables + * [out] alid + * ALID of the given GPU + * [out] clid + * CLID of the given GPU + * [in] alidClidTable + * Table with the ALIDs and corresponding mapped CLIDs + * [out] bClidUpdated + * Whether CLIDs have been updated in the FLA and GPA remap tables + */ +#define NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS (0x2080308dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_PARAMS_MESSAGE_ID (0x8dU) + +typedef struct NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_PARAMS { + NvBool bGet; + NvU32 alid; + NvU32 clid; + NV2080_CTRL_NVLINK_NVLE_ALID_CLID_TABLE alidClidTable; + NvBool bClidUpdated; +} NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_POST_LAZY_ERROR_RECOVERY + * + * Signal to GSP that lazy error recovery can proceed. + */ + +#define NV2080_CTRL_CMD_NVLINK_POST_LAZY_ERROR_RECOVERY (0x2080308aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | 0x8A" */ + +/* + * NV2080_CTRL_CMD_SET_NVLINK_CONFIGURE_L1_TOGGLE + * + * This command configures the nvlink L1 toggle pattern + * + * Commands returns SUCCESS only when it successfully sets value of all + * parameter in the list. + * + * Possible status return values are: + * NV_OK + * + * Reference: + * + */ +#define NV2080_CTRL_CMD_NVLINK_CONFIGURE_L1_TOGGLE (0x2080308eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE { + NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DISABLED = 0, + NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_TRIGGER_ONCE = 1, + NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_EXITED = 2, + NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_ENTERED = 3, + NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DUTY_CYCLE = 4, +} NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE; + +typedef struct NV2080_CTRL_NVLINK_L1_FORCE_CONFIG { + NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE mode; + NvU8 toggleActiveTime; + NvU8 toggleInactiveTime; + NvBool bTrigger; +} NV2080_CTRL_NVLINK_L1_FORCE_CONFIG; + +#define NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS_MESSAGE_ID (0x8EU) + +typedef struct NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS { + NvU32 linkMask; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8); + NV2080_CTRL_NVLINK_L1_FORCE_CONFIG config; +} NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_L1_TOGGLE (0x2080308fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS_MESSAGE_ID (0x8FU) + +typedef struct NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS { + NvU32 linkMask; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8); + NV2080_CTRL_NVLINK_L1_FORCE_CONFIG config[NV2080_CTRL_NVLINK_MAX_LINKS]; +} NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_NVLE_ENCRYPT_EN_INFO + * + * This command is used to get the ENCRYPT_EN register info + * + * [out] bMmuNvlinkEncryptEn + * Boolean that shows if ENCRYPTION_ENABLED bit in MMU is enabled or not. + * [out] bNvlinkTlwEncryptEn + * Boolean that shows if ENCRYPT_EN bit in NVLPLW TLW is enabled or not. + */ + +#define NV2080_CTRL_CMD_NVLINK_GET_NVLE_ENCRYPT_EN_INFO (0x2080308bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS_MESSAGE_ID (0x8bU) + +typedef struct NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS { + NvBool bMmuNvlinkEncryptEn; + NvBool bNvlinkTlwEncryptEn; +} NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS; + +/* + * NV2080_CTRL_NVLINK_GET_FIRMWARE_VERSION_INFO + * + * This command is used to get the firmware version info + * + * [out] firmwareVersion + * Array of firmware versions specifying their ucode type, and major/minor/subminor version + * [out] chipTypeArch + * Chip type arch + * [out] numValidEntries + * Number of valid entries in firmwareVersion array + */ + +#define NV2080_CTRL_NVLINK_FIRMWARE_VERSION_LENGTH (0x10U) +#define NV2080_CTRL_NVLINK_SEMANTIC_VERSION_UCODE_TYPE_MSE (0x01U) +#define NV2080_CTRL_NVLINK_SEMANTIC_VERSION_UCODE_TYPE_NETIR (0x02U) +#define NV2080_CTRL_NVLINK_SEMANTIC_VERSION_UCODE_TYPE_NETIR_UPHY (0x03U) +#define NV2080_CTRL_NVLINK_SEMANTIC_VERSION_UCODE_TYPE_NETIR_CLN (0x04U) +#define NV2080_CTRL_NVLINK_SEMANTIC_VERSION_UCODE_TYPE_NETIR_DLN (0x05U) + +typedef struct NV2080_CTRL_NVLINK_SEMANTIC_VERSION { + NvU8 ucodeType; + NvU32 major; + NvU32 minor; + NvU32 subMinor; +} NV2080_CTRL_NVLINK_SEMANTIC_VERSION; + +#define NV2080_CTRL_NVLINK_GET_FIRMWARE_VERSION_INFO (0x20803091U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_FIRMWARE_VERSION_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_GET_FIRMWARE_VERSION_INFO_PARAMS_MESSAGE_ID (0x91U) + +typedef struct NV2080_CTRL_NVLINK_GET_FIRMWARE_VERSION_INFO_PARAMS { + NV2080_CTRL_NVLINK_SEMANTIC_VERSION firmwareVersion[NV2080_CTRL_NVLINK_FIRMWARE_VERSION_LENGTH]; + NvU8 chipTypeArch; + NvU32 numValidEntries; +} NV2080_CTRL_NVLINK_GET_FIRMWARE_VERSION_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_SET_NVLE_ENABLED_STATE + * + * This command is used to set the NVLE enablement status in GSP-RM + * + * [Out] bIsNvleEnabled + * Boolean to determine if Nvlink Encryption is enabled or not + */ + +#define NV2080_CTRL_CMD_NVLINK_SET_NVLE_ENABLED_STATE (0x20803092U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_NVLE_ENABLED_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_SET_NVLE_ENABLED_STATE_PARAMS_MESSAGE_ID (0x92U) + +typedef struct NV2080_CTRL_NVLINK_SET_NVLE_ENABLED_STATE_PARAMS { + NvBool bIsNvleEnabled; +} NV2080_CTRL_NVLINK_SET_NVLE_ENABLED_STATE_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS (0x20803095U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS_MESSAGE_ID (0x95U) + +typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS { + NV2080_CTRL_NVLINK_PRM_DATA prm; +} NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS; + +#define NV2080_CTRL_NVLINK_FIXED_POINT_HISTOGRAM_MAX_SIZE 32U + +typedef struct NV2080_CTRL_NVLINK_FIXED_POINT_HISTOGRAM { + NvUFXP0_8 data[NV2080_CTRL_NVLINK_FIXED_POINT_HISTOGRAM_MAX_SIZE]; + NvU32 size; +} NV2080_CTRL_NVLINK_FIXED_POINT_HISTOGRAM; + +typedef struct NV2080_CTRL_NVLINK_PLR_TX_BW_LOSS_LOW_FREQUENCY { + NvU16 lastPlrTxBwLossLf; + NvU16 meanPlrTxBwLossLf; + NvU16 maxPlrTxBwLossLf; + NvU16 consBelowPlrTxBwLossLfThreshold; + NvU16 numOfPlrTxBwLossLfWarnings; + NvU16 numOfPlrTxBwLossLfAlarms; +} NV2080_CTRL_NVLINK_PLR_TX_BW_LOSS_LOW_FREQUENCY; + +typedef struct NV2080_CTRL_NVLINK_RECOVERY_BW_LOSS_LOW_FREQUENCY { + NvU16 lastRecoveryBwLossLf; + NvU16 meanRecoveryBwLossLf; + NvU16 maxRecoveryBwLossLf; + NvU16 consBelowRecoveryBwLossLfThreshold; + NvU16 numOfRecoveryBwLossLfWarnings; + NvU16 numOfRecoveryBwLossLfAlarms; +} NV2080_CTRL_NVLINK_RECOVERY_BW_LOSS_LOW_FREQUENCY; + +typedef struct NV2080_CTRL_NVLINK_EFFECTIVE_BER_LOW_FREQUENCY { + NvU16 consBelowEffBerLfThreshold; + NvU16 numOfEffBerLfWarnings; + NvU16 numOfEffBerLfAlarms; + NvU8 meanEffBerLfMagnitude; + NvU8 lastEffBerLfMagnitude; + NvU8 maxEffBerLfMagnitude; + NvU8 maxEffBerLfCoef; +} NV2080_CTRL_NVLINK_EFFECTIVE_BER_LOW_FREQUENCY; + +/* + * NV2080_CTRL_NVLINK_GET_LINK_ACCUMULATIVE_METRIC_DATA + * + * This command is used to retrieve persistent per-link metrics from beginning of life. + * This command is supported for NVL IP version 5.0 + * + * [in] linkId + * link ID to query + * [out] globalMaxRawBERExp // Blackwell Only + * Largest lifetime RAW BER (exponent only) + * [out] globalMaxEffBERExp // Blackwell Only + * Largest lifetime EFF BER (exponent only) + * [out] linkDownCount + * Lifetime count of link down events (saturates) + * [out] downReasonHistogram + * Fixed-point histogram of unintentional link down reason codes with + * recency bias + * [out] linkXidHistogram + * Fixed-point histogram of link xid codes with + * recency bias + */ + +#define NV2080_CTRL_CMD_NVLINK_GET_LINK_ACCUMULATIVE_METRIC_DATA (0x20803097U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_ACCUMULATIVE_METRIC_DATA_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_GET_LINK_ACCUMULATIVE_METRIC_DATA_PARAMS_MESSAGE_ID (0x97U) + +typedef struct NV2080_CTRL_NVLINK_GET_LINK_ACCUMULATIVE_METRIC_DATA_PARAMS { + NvU32 linkId; + NvU8 globalMaxRawBERExp; + NvU8 globalMaxEffBERExp; + NvU32 linkDownCount; + NV2080_CTRL_NVLINK_FIXED_POINT_HISTOGRAM downReasonHistogram; + NV2080_CTRL_NVLINK_FIXED_POINT_HISTOGRAM linkXidHistogram; +} NV2080_CTRL_NVLINK_GET_LINK_ACCUMULATIVE_METRIC_DATA_PARAMS; + +/* + * NV2080_CTRL_NVLINK_GET_LINK_RECORD_METRIC_DATA + * + * This command is used to retrieve most recent persistent per-link metrics. + * This command is supported for NVL IP version 5.0 + * + * [in] linkId + * link ID to query + * [out] initialRawBERExp + * Raw BER from most recent linkup (exponent only) + * [out] initialEffBERExp + * Eff BER from most recent linkup (exponent only) + * [out] lastDownReason + * Port down reason code from most recent linkdown + * [out] uptime + * Total time port has been up since most recent linkup (floating point msec) + * [out] localMaxRawBERExp // Blackwell Only + * Largest Raw BER reading since most recent linkup (exponent only) + * [out] localMaxEffBERExp // Blackwell Only + * Largest Eff BER reading since most recent linkup (exponent only) + * [out] currEffBERMonitor + * Current Eff BER monitor from most recent linkup + * [out] plrXmitRetryWithinTSecMaxLo // Deprecated + * PLR retransmissions in time window + * [out] totalSuccessfulRecoveryEvents + * Total number of times the Port Training state machine has + * successfully completed the link error recovery process + * [out] plrTxBwLossLf + * Link health statistics - PLR Tx BW loss low frequency + * [out] recoveryBwLossLf + * Link health statistics - Recovery BW loss low frequency + * [out] effBerLf + * Link health statistics - effective BER low frequency + * [out] lastDownAdvancedReason + * More detailed reason code for the link going down + */ +#define NV2080_CTRL_CMD_NVLINK_GET_LINK_RECORD_METRIC_DATA (0x20803098U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_RECORD_METRIC_DATA_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_GET_LINK_RECORD_METRIC_DATA_PARAMS_MESSAGE_ID (0x98U) + +typedef struct NV2080_CTRL_NVLINK_GET_LINK_RECORD_METRIC_DATA_PARAMS { + NvU32 linkId; + NvU8 initialRawBERExp; + NvU8 initialEffBERExp; + NvU8 lastDownReason; + NvU32 uptime; + NvU8 localMaxRawBERExp; + NvU8 localMaxEffBERExp; + NvU16 currEffBERMonitor; + NvU32 plrXmitRetryWithinTSecMaxLo; + NvU32 totalSuccessfulRecoveryEvents; + NV2080_CTRL_NVLINK_PLR_TX_BW_LOSS_LOW_FREQUENCY plrTxBwLossLf; + NV2080_CTRL_NVLINK_RECOVERY_BW_LOSS_LOW_FREQUENCY recoveryBwLossLf; + NV2080_CTRL_NVLINK_EFFECTIVE_BER_LOW_FREQUENCY effBerLf; + NvU16 lastDownAdvancedReason; +} NV2080_CTRL_NVLINK_GET_LINK_RECORD_METRIC_DATA_PARAMS; + +/* + * NV2080_CTRL_NVLINK_GET_DEVICE_RECORD_METRIC_DATA + * + * This command is used to retrieve most recent persistent per-device metrics. + * This command is supported for NVL IP version 5.0 + * + * [out] MFDE + * PRM payload of most recent NETIR_MFDE_EVENT error + */ + +#define NV2080_CTRL_CMD_NVLINK_GET_DEVICE_RECORD_METRIC_DATA (0x20803099U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_DEVICE_RECORD_METRIC_DATA_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_GET_DEVICE_RECORD_METRIC_DATA_PARAMS_MESSAGE_ID (0x99U) + +typedef struct NV2080_CTRL_NVLINK_GET_DEVICE_RECORD_METRIC_DATA_PARAMS { + NV2080_CTRL_NVLINK_PRM_DATA MFDE; +} NV2080_CTRL_NVLINK_GET_DEVICE_RECORD_METRIC_DATA_PARAMS; + +/* + * NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME + * NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME + * + * These commands store/retrieve a 64 char null-terminated ASCII string which is + * treated by the NVLINK firmware as the node's hostname for fabric reporting + * purposes. + */ +typedef struct NV2080_CTRL_NVLINK_NODE_HOSTNAME { + NvU8 name[64]; +} NV2080_CTRL_NVLINK_NODE_HOSTNAME; + +#define NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS_MESSAGE_ID (0x9AU) + +typedef struct NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS { + NV2080_CTRL_NVLINK_NODE_HOSTNAME hostname; +} NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS; +#define NV2080_CTRL_CMD_NVLINK_SAVE_NODE_HOSTNAME (0x2080309aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS_MESSAGE_ID (0x9BU) + +typedef struct NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS { + NV2080_CTRL_NVLINK_NODE_HOSTNAME hostname; +} NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS; +#define NV2080_CTRL_CMD_NVLINK_GET_SAVED_NODE_HOSTNAME (0x2080309bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_UPDATE_CLID + * + * Update the NVLE CLID + */ +#define NV2080_CTRL_NVLINK_UPDATE_CLID_PARAMS_MESSAGE_ID (0x9CU) + +typedef struct NV2080_CTRL_NVLINK_UPDATE_CLID_PARAMS { + NvU32 clid; +} NV2080_CTRL_NVLINK_UPDATE_CLID_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_UPDATE_CLID (0x2080309cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_CLID_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_LOCK_REMAP_TABLE_AND_MSE + * + * Request to lock the remap table to prevent MSE from making any further updates to the remap table for the given links + * + * linkMask [IN] + * NVLINK mask + * + * bRemapTableMseLocked [OUT] + * Whether remap table of the GPU is locked + * + * bRemapTableLockDisabled [OUT] + * Whether locking of remap table is disabled + */ +#define NV2080_CTRL_NVLINK_LOCK_REMAP_TABLE_AND_MSE_PARAMS_MESSAGE_ID (0x9DU) + +typedef struct NV2080_CTRL_NVLINK_LOCK_REMAP_TABLE_AND_MSE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 linkMask, 8); + NvBool bRemapTableMseLocked; + NvBool bRemapTableLockDisabled; +} NV2080_CTRL_NVLINK_LOCK_REMAP_TABLE_AND_MSE_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_LOCK_REMAP_TABLE_AND_MSE (0x2080309d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_LOCK_REMAP_TABLE_AND_MSE_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_GET_REMAP_TABLE_INFO + * + * Return the remap table addrs for all the entries in the FLA and SPA/GPA rempa tables + * + * [out] flaRemapTabAddr + * FLA remap table addrs for all the remap table entries + * [out] gpaRemapTabAddr + * SPA/GPA remap table addrs for all the remap table entries + * [out] remapTabSize + * Number of entries in the remap tables + */ +#define NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_PARAMS_MESSAGE_ID (0x9EU) + +typedef struct NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_PARAMS { + NvU32 flaRemapTabAddr[NV_MAX_DEVICES]; + NvU32 gpaRemapTabAddr[NV_MAX_DEVICES]; + NvU32 remapTabSize; +} NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_REMAP_TABLE_INFO (0x2080309e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_NVLINK_NVLE_PKT_CNTRS + * + * This structure stores the NVLE acket counter information for both pipes of Tx and Rx link + * + * txPipe0Cntr + * 64 bit counter for Tx pipe0 + * txPipe1Cntr + * 64 bit counter for Tx pipe1 + * rxPipe0Cntr + * 64 bit counter for Rx pipe0 + * rxPipe1Cntr + * 64 bit counter for Rx pipe1 + */ +typedef struct NV2080_CTRL_NVLINK_NVLE_PKT_CNTRS { + NV_DECLARE_ALIGNED(NvU64 txPipe0Cntr, 8); + NV_DECLARE_ALIGNED(NvU64 txPipe1Cntr, 8); + NV_DECLARE_ALIGNED(NvU64 rxPipe0Cntr, 8); + NV_DECLARE_ALIGNED(NvU64 rxPipe1Cntr, 8); +} NV2080_CTRL_NVLINK_NVLE_PKT_CNTRS; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_NVLE_PKT_COUNTERS + * + * Get the Tx and Rx pipe0/1 NVLE packet counters for the mask of links passed + * + * [in] linkMask + * Mask of links for which NVLE packet counters are queried + * [out] nvleCounters + * The count of Tx and Rx pipe0/1 NVLE packet counters to be retrieved + */ +#define NV2080_CTRL_NVLINK_GET_NVLE_PKT_COUNTERS_PARAMS_MESSAGE_ID (0x9FU) + +typedef struct NV2080_CTRL_NVLINK_GET_NVLE_PKT_COUNTERS_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK linkMask, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_NVLE_PKT_CNTRS nvleCounters[NV2080_CTRL_NVLINK_MAX_LINKS], 8); +} NV2080_CTRL_NVLINK_GET_NVLE_PKT_COUNTERS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_NVLE_PKT_COUNTERS (0x2080309f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_NVLE_PKT_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_NVLE_AES_256_GCM_KEY_SIZE_BYTES 32U + +/* + * NV2080_CTRL_CMD_NVLINK_SETUP_NVLE_ENCRYPTION_KEY + * + * Sets the NVLE encryption key between GPUs with the given ALIDs + * + * [in] nvleKey + * Key secret from which keyMgr will derive the key + * [in] localGpuAlid + * ALID of the local GPU + * [in] remoteGpuAlid + * ALID of the remote GPU + * [in] localGpuPlatformInfo + * Platform information for the local GPU + * [in] remoteGpuPlatformInfo + * Platform information for the remote GPU + */ +#define NV2080_CTRL_NVLINK_SETUP_NVLE_ENCRYPTION_KEY_PARAMS_MESSAGE_ID (0xA0U) + +typedef struct NV2080_CTRL_NVLINK_SETUP_NVLE_ENCRYPTION_KEY_PARAMS { + NvU8 nvleKey[NV2080_CTRL_NVLINK_NVLE_AES_256_GCM_KEY_SIZE_BYTES]; + NvU32 localGpuAlid; + NvU32 remoteGpuAlid; + NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS localGpuPlatformInfo; + NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS remoteGpuPlatformInfo; +} NV2080_CTRL_NVLINK_SETUP_NVLE_ENCRYPTION_KEY_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_SETUP_NVLE_ENCRYPTION_KEY (0x208030a0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SETUP_NVLE_ENCRYPTION_KEY_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_GET_REMAP_TABLE_INFO_V2 + * + * Return the remap table addrs for a given set of entries in the FLA and SPA/GPA rempa tables + * + * [out] flaRemapTabAddr + * FLA remap table addrs for the given set of remap table entries + * [out] gpaRemapTabAddr + * SPA/GPA remap table addrs for the given set of remap table entries + * [out] remapTabSize + * Number of entries in the remap tables + * [in] remapEntryStart + * Entry to start parsing from + * [in] remapEntryEnd + * Entry to end parsing at + */ +#define NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_V2_PARAMS_MESSAGE_ID (0xA1U) + +typedef struct NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_V2_PARAMS { + NvU32 flaRemapTabAddr[NV2080_CTRL_NVLINK_REMAP_TABLE_ENTRIES_CHUNK]; + NvU32 gpaRemapTabAddr[NV2080_CTRL_NVLINK_REMAP_TABLE_ENTRIES_CHUNK]; + NvU32 remapTabSize; + NvU32 remapEntryStart; + NvU32 remapEntryEnd; +} NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_V2_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_REMAP_TABLE_INFO_V2 (0x208030a1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_V2_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_V2 + * + * This command is used for the following operations. + * If getting the LID information, the command gets the ALID and CLID of the GPU. + * If setting the LID information, the command passes the complete ALID-CLID map. + * The also command returns the status of whether the CLIDs are updated in the remap tables. + * + * [in] bGet + * Whether to get the ALIDs or set the CLIDs in the remap table or update the LIDs in the remap tables + * [out] alid + * ALID of the given GPU + * [out] clid + * CLID of the given GPU + * [in] alidClidTable + * Table with the ALIDs and corresponding mapped CLIDs - new version supporting more ALID-CLID mappings + * [out] bClidUpdated + * Whether CLIDs have been updated in the FLA and GPA remap tables + */ +#define NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_V2_PARAMS_MESSAGE_ID (0xA2U) + +typedef struct NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_V2_PARAMS { + NvBool bGet; + NvU32 alid; + NvU32 clid; + NV2080_CTRL_NVLINK_NVLE_ALID_CLID_TABLE_V2 alidClidTable; + NvBool bClidUpdated; +} NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_V2_PARAMS; + +#define NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_V2 (0x208030a2U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_V2_PARAMS_MESSAGE_ID" */ + + +/* _ctrl2080nvlink_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080nvlink_common.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080nvlink_common.h new file mode 100644 index 0000000..8a851b8 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080nvlink_common.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080nvlink_common.finn +// + + + +#define NV2080_CTRL_NVLINK_MAX_LINKS 64 +#define NV2080_CTRL_NVLINK_MAX_ARR_SIZE 64 +#define NV2080_CTRL_LINKS_PER_MASK_INDEX 64 +#define NV2080_CTRL_NVLINK_MAX_MASK_SIZE (0x1) /* finn: Evaluated from "((NV2080_CTRL_NVLINK_MAX_LINKS + 63) / NV2080_CTRL_LINKS_PER_MASK_INDEX)" */ + +typedef struct NV2080_CTRL_NVLINK_LINK_MASK { + NvU8 lenMasks; + NV_DECLARE_ALIGNED(NvU64 masks[NV2080_CTRL_NVLINK_MAX_MASK_SIZE], 8); +} NV2080_CTRL_NVLINK_LINK_MASK; diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080perf.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080perf.h new file mode 100644 index 0000000..778736a --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080perf.h @@ -0,0 +1,927 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080perf.finn +// + +#include "nvfixedtypes.h" +#include "ctrl/ctrl2080/ctrl2080base.h" + +#define NV_SUBPROC_NAME_MAX_LENGTH 100 + +#include "nvmisc.h" + +#include "ctrl/ctrl2080/ctrl2080clk.h" +#include "ctrl/ctrl2080/ctrl2080gpumon.h" +#include "ctrl/ctrl2080/ctrl2080volt.h" +#include "ctrl/ctrl2080/ctrl2080vfe.h" +#include "ctrl/ctrl2080/ctrl2080pmumon.h" +#include "ctrl/ctrl0080/ctrl0080perf.h" +// +// XAPICHK/XAPI_TEST chokes on the "static NVINLINE" defines in nvmisc.h. +// However, we don't need any of those definitions for those tests (XAPICHK is a +// syntactical check, not a functional test). So, instead, just #define out the +// macros referenced below. +// + +/* + * NV2080_CTRL_CMD_PERF_BOOST + * + * This command can be used to boost P-State up one level or to the highest for a limited + * duration for the associated subdevice. Boosts from different clients are being tracked + * independently. Note that there are other factors that can limit P-States so the resulting + * P-State may differ from expectation. + * + * flags + * This parameter specifies the actual command. _CLEAR is to clear existing boost. + * _BOOST_1LEVEL is to boost P-State one level higher. _BOOST_TO_MAX is to boost + * to the highest P-State. + * duration + * This parameter specifies the duration of the boost in seconds. This has to be less + * than NV2080_CTRL_PERF_BOOST_DURATION_MAX. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD 1:0 +#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_CLEAR (0x00000000) +#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_1LEVEL (0x00000001) +#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_TO_MAX (0x00000002) + +#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA 4:4 +#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_NO (0x00000000) +#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_YES (0x00000001) + +#define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC 5:5 +#define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_NO (0x00000000) +#define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_YES (0x00000001) + +#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY 6:6 +#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_DEFAULT (0x00000000) +#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_HIGH (0x00000001) + +#define NV2080_CTRL_PERF_BOOST_DURATION_MAX 3600 //The duration can be specified up to 1 hour +#define NV2080_CTRL_PERF_BOOST_DURATION_INFINITE 0xffffffff // If set this way, the boost will last until cleared. + +#define NV2080_CTRL_CMD_PERF_BOOST (0x2080200a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_BOOST_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_BOOST_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV2080_CTRL_PERF_BOOST_PARAMS { + NvU32 flags; + NvU32 duration; +} NV2080_CTRL_PERF_BOOST_PARAMS; + +/* + * NV2080_CTRL_CMD_PERF_RESERVE_PERFMON_HW + * + * This command reserves HW Performance Monitoring capabilities for exclusive + * use by the requester. If the HW Performance Monitoring capabilities are + * currently in use then NVOS_STATUS_ERROR_STATE_IN_USE is returned. + * + * bAcquire + * When set to TRUE this parameter indicates that the client wants to + * acquire the Performance Monitoring capabilities on the subdevice. + * When set to FALSE this parameter releases the Performance Monitoring + * capabilities on the subdevice. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_ERROR_STATE_IN_USE + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_PERF_RESERVE_PERFMON_HW (0x20802093) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS_MESSAGE_ID (0x93U) + +typedef struct NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS { + NvBool bAcquire; +} NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS; + +/* + * NV2080_CTRL_PERF_POWERSTATE + * + * This structure describes power state information. + * + * powerState + * This parameter specifies the type of power source. + * Legal values for this parameter include: + * NV2080_CTRL_PERF_POWER_SOURCE_AC + * This values indicates that the power state is AC. + * NV2080_CTRL_PERF_POWER_SOURCE_BATTERY + * This values indicates that the power state is battery. + */ +#define NV2080_CTRL_PERF_POWER_SOURCE_AC (0x00000000) +#define NV2080_CTRL_PERF_POWER_SOURCE_BATTERY (0x00000001) + +typedef struct NV2080_CTRL_PERF_POWERSTATE_PARAMS { + NvU32 powerState; +} NV2080_CTRL_PERF_POWERSTATE_PARAMS; + +/* + * NV2080_CTRL_CMD_PERF_SET_POWERSTATE + * + * This command can be used to set the perf power state as AC or battery. + * + * powerStateInfo + * This parameter specifies the power source type to set. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_PERF_SET_POWERSTATE (0x2080205b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS_MESSAGE_ID (0x5BU) + +typedef struct NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS { + NV2080_CTRL_PERF_POWERSTATE_PARAMS powerStateInfo; +} NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS; + +/* + * NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE + * + * This command allows the forcing of a performance level based on auxiliary + * power-states. + * + * powerState + * This parameter specifies the target auxiliary Power state. Legal aux + * power-states for this parameter are defined by the + * NV2080_CTRL_PERF_AUX_POWER_STATE_P* definitions that follow. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE (0x20802092) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS_MESSAGE_ID (0x92U) + +typedef struct NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS { + NvU32 powerState; +} NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS; + +#define NV2080_CTRL_PERF_AUX_POWER_STATE_P0 (0x00000000) +#define NV2080_CTRL_PERF_AUX_POWER_STATE_P1 (0x00000001) +#define NV2080_CTRL_PERF_AUX_POWER_STATE_P2 (0x00000002) +#define NV2080_CTRL_PERF_AUX_POWER_STATE_P3 (0x00000003) +#define NV2080_CTRL_PERF_AUX_POWER_STATE_P4 (0x00000004) +#define NV2080_CTRL_PERF_AUX_POWER_STATE_COUNT (0x00000005) + +/*! + * Enumeration of the RATED_TDP arbitration clients which make requests to force + * enable/disable VF points above the RATED_TDP point. + * + * These clients are sorted in descending priority - the RM will arbitrate + * between all clients in order of priority, taking as output the first client + * whose input action != @ref NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT. + */ +typedef enum NV2080_CTRL_PERF_RATED_TDP_CLIENT { + /*! + * Internal RM client corresponding to the RM's internal state and features. + * The RM client will either allow default behavior (@ref + * NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT) or will limit to RATED_TDP + * (@ref NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT) when no power + * controllers are active. + */ + NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM = 0, + /*! + * This Client is specifically for Bug 1785342 where we need to limit the TDP + * to Min value on boot. And clear the Max TDP limit. + */ + NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342 = 1, + /*! + * Global client request. This client is expected to be used by a global + * switch functionality in an end-user tool, such as EVGA Precision, to + * either force enabling boost above RATED_TDP (@ref + * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED) or to force limiting to + * RATED_TDP (@ref NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT) across the + * board, regardless of any app-profie settings. + */ + NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL = 2, + /*! + * Operating system request. This client is expected to be used by the + * operating system to set @ref NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK + * for performance profiling. + */ + NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS = 3, + /*! + * App profile client requests. This client is expected to be used by the + * app-profile settings to either default to whatever was requested by + * higher-priority clients (@ref NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT) + * or to limit to RATED_TDP (@ref + * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT) for apps which have shown + * bad behavior when boosting. + */ + NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE = 4, + /*! + * Number of supported clients. + * + * @Note MUST ALWAYS BE LAST! + */ + NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS = 5, +} NV2080_CTRL_PERF_RATED_TDP_CLIENT; + +/*! + * Enumeration RATED_TDP actions - these are the requested actions clients can + * make to change the behavior of the RATED_TDP functionality. + */ +typedef enum NV2080_CTRL_PERF_RATED_TDP_ACTION { + /*! + * The default action - meaning no explicit request from the client other + * than to take the default behavior (allowing boosting above RATED_TDP) or + * any explicit actions from lower priority clients. + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT = 0, + /*! + * Force allow boosting above RATED_TDP - this action explicitly requests + * boosting above RATED_TDP, preventing lower priority clients to limit to + * RATED_TDP. + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED = 1, + /*! + * Force to limit above RATED_TDP - this action explicitly requests to limit + * to RATED_TDP. This is the opposite of the default behavior to allow + * boosting above RATED_TDP. Clients specify this action when they + * explicitly need boost to be disabled (e.g. eliminating perf variation, + * special apps which exhibit bad behavior, etc.). + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT = 2, + /*! + * Lock to RATED_TDP - this action requests the clocks to be fixed at the + * RATED_TDP. Used for achieving stable clocks required for profiling. + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK = 3, + /*! + * Lock to Min TDP - This requests min to be fixed at RATED_TDP but allow + * boosting for max + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR = 4, +} NV2080_CTRL_PERF_RATED_TDP_ACTION; + +/*! + * Enumeration VPstates - these are possible VPStates that clients can + * request + */ +typedef enum NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE { + /*! + * Choise of the RATED TDP VPstate + */ + NV2080_CTRL_PERF_VPSTATE_RATED_TDP = 0, + /*! + * Choise of the TURBO BOOST VPstate + */ + NV2080_CTRL_PERF_VPSTATE_TURBO_BOOST = 1, + /*! + * Number of supported vpstates. + * + * @Note MUST ALWAYS BE LAST! + */ + NV2080_CTRL_PERF_VPSTATE_NUM_VPSTATES = 2, +} NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE; + +/*! + * Enumeration VPstates - these are possible VPStates that clients can + * request + */ +typedef struct NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST { + /*! + * [in] - Specified client for request. + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION action; + /*! + * [in/out] - Client's requested action. + */ + NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE vPstateType; +} NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST; + +/*! + * Structure describing dynamic state of the RATED_TDP feature. + */ +#define NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_MESSAGE_ID (0x6DU) + +typedef struct NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS { + /*! + * Structure of internal RM state - these values are used to determine the + * behavior of NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM per the RM's @ref + * perfPwrRatedTdpLimitRegisterClientActive() interface. + */ + struct { + /*! + * [out] - Mask of active client controllers (@ref + * PERF_PWR_RATED_TDP_CLIENT) which are currently regulating TDP. When + * this mask is zero, NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM will request + * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT. + */ + NvU32 clientActiveMask; + /*! + * [out] - Boolean indicating that user has requested locking to + * RATED_TDP vPstate via corresponding regkey + * NV_REG_STR_RM_PERF_RATED_TDP_LIMIT. When the boolean value is true, + * NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM will request + * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT. + */ + NvU8 bRegkeyLimitRatedTdp; + } rm; + + /*! + * [out] - Arbitrated output action of all client requests (@ref inputs). + * This is the current state of the RATED_TDP feature. Will only be @ref + * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED or @ref + * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT. + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION output; + /* + * [out] - Arbitrated output VPStates of all client requests (@ref inputs). + * This is the current VPState of the RATED_TDP feature. + */ + NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE outputVPstate; + /*! + * [out] - Array of input client request actions, indexed via @ref + * NV2080_CTRL_PERF_RATED_TDP_CLIENT_. RM will arbitrate between these + * requests, choosing the highest priority request != @ref + * NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT or fallback to choosing @ref + * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED. + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION inputs[NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS]; + /*! + * [out] - Array of input client request VPstates, indexed via @ref + * NV2080_CTRL_PERF_RATED_TDP_CLIENT_. RM will arbitrate between these + * requests, choosing the highest priority request != @ref + * NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT or fallback to choosing @ref + * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED. + */ + NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE vPstateTypes[NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS]; +} NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS; + +/*! + * NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL + * + * This command retrieves the current requested RATED_TDP action corresponding + * to the specified client. + * + * See @ref NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS for documentation of + * parameters. + * + * Possible status values returned are + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL (0x2080206e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS_MESSAGE_ID" */ + +/*! + * Structure containing the requested action for a RATED_TDP client (@ref + * NV2080_CTRL_PERF_RATED_TDP_CLIENT). + */ +typedef struct NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS { + /*! + * [in] - Specified client for request. + */ + NV2080_CTRL_PERF_RATED_TDP_CLIENT client; + /*! + * [in/out] - Client's requested action. + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION input; + /* + * [in] - Specified VPState of the request + */ + NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE vPstateType; +} NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS; + +#define NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS_MESSAGE_ID (0x6EU) + +typedef NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS; + +/*! + * NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL + * + * This command sets the requested RATED_TDP action corresponding to the + * specified client. @Note, however, that this command is unable to set @ref + * NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM. + * + * See @ref NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS for documentation of + * parameters. + * + * Possible status values returned are + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL (0x2080206f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS_MESSAGE_ID (0x6FU) + +typedef NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS; + +/*! + * This struct represents the GPU monitoring perfmon sample for an engine. + */ +typedef struct NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE { + /*! + * Percentage during the sample that the engine remains busy. This + * is in units of pct*100. + */ + NvU32 util; + /*! + * Scaling factor to convert utilization from full GPU to per vGPU. + */ + NvU32 vgpuScale; + /*! + * Process ID of the process that was active on the engine when the + * sample was taken. If no process is active then NV2080_GPUMON_PID_INVALID + * will be returned. + */ + NvU32 procId; + /*! + * Process ID of the process in the vGPU VM that was active on the engine when + * the sample was taken. If no process is active then NV2080_GPUMON_PID_INVALID + * will be returned. + */ + NvU32 subProcessID; + /*! + * Process name of the process in the vGPU VM that was active on the engine when + * the sample was taken. If no process is active then NULL will be returned. + */ + char subProcessName[NV_SUBPROC_NAME_MAX_LENGTH]; + /*! + * PID struct pointer of the process that was active on the engine when the + * the sample was taken. If no process is active then NULL pointer + * will be returned + */ + NV_DECLARE_ALIGNED(NvU64 pOsPidInfo, 8); +} NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE; + +/*! + * This struct represents the GPU monitoring perfmon sample. + */ +typedef struct NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE { + /*! + * Base GPU monitoring sample. + */ + NV_DECLARE_ALIGNED(NV2080_CTRL_GPUMON_SAMPLE base, 8); + /*! + * FB bandwidth utilization sample. + */ + NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE fb, 8); + /*! + * GR utilization sample. + */ + NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE gr, 8); + /*! + * NV ENCODER utilization sample. + */ + NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvenc, 8); + /*! + * NV DECODER utilization sample. + */ + NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvdec, 8); + /*! + * NV JPEG utilization sample. + */ + NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvjpg, 8); + /*! + * NV OFA utilization sample. + */ + NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvofa, 8); +} NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE; + +/*! + * This struct represents the GPU monitoring samples of perfmon values that + * client wants the access to. + */ +#define NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM_MESSAGE_ID (0x83U) + +typedef NV2080_CTRL_GPUMON_SAMPLES NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM; + +/*! + * Number of GPU monitoring sample in their respective buffers. + */ +#define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL 72 + +#define NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_BUFFER_SIZE \ + sizeof(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE) * \ + NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL + +/*! + * NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2 + * + * This command returns perfmon gpu monitoring utilization samples. + * This command is not supported with SMC enabled. + * + * See NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM_V2 for documentation + * on the parameters. + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + * Note this is the same as NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES + * but without the embedded pointer. + * + */ +#define NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2 (0x20802096) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_MESSAGE_ID" */ + +/*! + * This structure represents the GPU monitoring samples of utilization values that + * the client wants access to. + */ +#define NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_MESSAGE_ID (0x96U) + +typedef struct NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS { + /*! + * Type of the sample, see NV2080_CTRL_GPUMON_SAMPLE_TYPE_* for reference. + */ + NvU8 type; + /*! + * Size of the buffer, this should be + * bufSize == NV2080_CTRL_*_GPUMON_SAMPLE_COUNT_* + * sizeof(derived type of NV2080_CTRL_GPUMON_SAMPLE). + */ + NvU32 bufSize; + /*! + * Number of samples in ring buffer. + */ + NvU32 count; + /*! + * tracks the offset of the tail in the circular queue array pSamples. + */ + NvU32 tracker; + /*! + * A circular queue with size == bufSize. + * + * @note This circular queue wraps around after 10 seconds of sampling, + * and it is clients' responsibility to query within this time frame in + * order to avoid losing samples. + * @note With one exception, this queue contains last 10 seconds of samples + * with tracker poiniting to oldest entry and entry before tracker as the + * newest entry. Exception is when queue is not full (i.e. tracker is + * pointing to a zeroed out entry), in that case valid entries are between 0 + * and tracker. + * @note Clients can store tracker from previous query in order to provide + * samples since last read. + */ + NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE samples[NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL], 8); +} NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS; + +/* + * NV2080_CTRL_CMD_PERF_GPU_IS_IDLE + * + * This command notifies RM to make p state switching aggressive by setting + * required limiting factors to speed up GC6 Entry initiation. + * + * prevPstate [out] + * This parameter will contain the pstate before the switch was initiated + * + * Possible status return values are: + * NV_OK : If P State Switch is successful + * NV_INVALID_STATE : If unable to access P State structure + * NVOS_STATUS_ERROR : If P State Switch is unsuccessful + */ +#define NV2080_CTRL_CMD_PERF_GPU_IS_IDLE (0x20802089) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS_MESSAGE_ID (0x89U) + +typedef struct NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS { + NvU32 prevPstate; + NvU32 action; +} NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS; + +#define NV2080_CTRL_PERF_GPU_IS_IDLE_TRUE (0x00000001) +#define NV2080_CTRL_PERF_GPU_IS_IDLE_FALSE (0x00000002) + +/* + * NV2080_CTRL_CMD_PERF_AGGRESSIVE_PSTATE_NOTIFY + * + * This command is for the KMD Aggressive P-state feature. + * + * bGpuIsIdle [in] + * When true, applies cap to lowest P-state/GPCCLK. When false, releases cap. + * idleTimeUs [in] + * The amount of time (in microseconds) the GPU was idle since previous + * call, part of the GPU utilization data from KMD. + * busyTimeUs [in] + * The amount of time (in microseconds) the GPU was not idle since + * previous call, part of the GPU utilization data from KMD. + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + + +#define NV2080_CTRL_CMD_PERF_AGGRESSIVE_PSTATE_NOTIFY (0x2080208f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS_MESSAGE_ID (0x8FU) + +typedef struct NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS { + NvBool bGpuIsIdle; + NvBool bRestoreToMax; + NV_DECLARE_ALIGNED(NvU64 idleTimeUs, 8); + NV_DECLARE_ALIGNED(NvU64 busyTimeUs, 8); +} NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS; + + +typedef struct NV2080_CTRL_PERF_GET_CLK_INFO { + NvU32 flags; + NvU32 domain; + NvU32 currentFreq; + NvU32 defaultFreq; + NvU32 minFreq; + NvU32 maxFreq; +} NV2080_CTRL_PERF_GET_CLK_INFO; + + +#define NV2080_CTRL_PERF_CLK_MAX_DOMAINS 32U + +#define NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO (0x20802002) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS { + NvU32 level; + NvU32 flags; + NV_DECLARE_ALIGNED(NvP64 perfGetClkInfoList, 8); + NvU32 perfGetClkInfoListSize; +} NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS; + +#define NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO_V2 (0x2080200b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS { + NvU32 level; + NvU32 flags; + NV2080_CTRL_PERF_GET_CLK_INFO perfGetClkInfoList[NV2080_CTRL_PERF_CLK_MAX_DOMAINS]; + NvU32 perfGetClkInfoListSize; +} NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS; + +#define NV2080_CTRL_PERF_GET_LEVEL_INFO_LEVEL_STANDARD 0 +#define NV2080_CTRL_PERF_GET_LEVEL_INFO_LEVEL_CONSERVATIVE 1 +#define NV2080_CTRL_PERF_GET_LEVEL_INFO_LEVEL_AGGRESSIVE 2 + +#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE 0:0 +#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_DEFAULT (0x00000000) +#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_OVERCLOCK (0x00000001) +#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE 2:1 +#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_NONE (0x00000000) +#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_DESKTOP (0x00000001) +#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_MAXPERF (0x00000002) + +/* + * NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE + * + * This command can be used to obtain video decoder utilization of + * the associated subdevice. + * This command is not supported with SMC enabled. + * + * engineType + * This parameter will allow clients to set type of video + * engine in question. It can be NVENC or NVDEC. + * clkPercentBusy + * This parameter contains the percentage during the sample that + * the clock remains busy. + * samplingPeriodUs + * This field returns the sampling period in microseconds. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE (0x20802087) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_CMD_PERF_VID_ENG { + /*! + * GPU Video encoder engine. + */ + NV2080_CTRL_CMD_PERF_VID_ENG_NVENC = 1, + + /*! + * GPU video decoder engine. + */ + NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC = 2, + + /*! + * GPU JPEG engine. + */ + NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG = 3, + + /*! + * GPU OFA engine. + */ + NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA = 4, +} NV2080_CTRL_CMD_PERF_VID_ENG; + +#define NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_MESSAGE_ID (0x87U) + +typedef struct NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS { + NV2080_CTRL_CMD_PERF_VID_ENG engineType; + NvU32 clkPercentBusy; + NvU32 samplingPeriodUs; +} NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS; + +/* + * NV2080_CTRL_CMD_PERF_GET_POWERSTATE + * + * This command can be used to find out whether the perf power state is AC/battery. + * + * powerStateInfo + * This parameter specifies the power source type. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_PERF_GET_POWERSTATE (0x2080205a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS_MESSAGE_ID (0x5AU) + +typedef struct NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS { + NV2080_CTRL_PERF_POWERSTATE_PARAMS powerStateInfo; +} NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS; + +/* + * NV2080_CTRL_CMD_PERF_NOTIFY_VIDEOEVENT + * + * This command can be used by video driver to notify RM concerning + * performance related events. + * + * videoEvent + * This parameter specifies the video event to notify. + * Legal values for this parameter include: + * NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START + * NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP + * These values indicate that a HD video stream (less than 4K) + * has started/stopped. + * NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_START + * NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_STOP + * These are now obsolete in new products as we no longer + * need to differentiate between SD and HD. + * NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_START + * NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_STOP + * These value indicates that a 4K video stream (3840x2160 pixels + * or higher) has started/stopped. + * NV2080_CTRL_PERF_VIDEOEVENT_OFA_START + * NV2080_CTRL_PERF_VIDEOEVENT_OFA_STOP + * These value indicates that Optical Flow Accelerator usage has + * started/stopped. + * The following flags may be or'd into the event value: + * NV2080_CTRL_PERF_VIDEOEVENT_FLAG_LINEAR_MODE + * The stream operates BSP/VP2 or MSVLD/MSPDEC communication in + * linear mode (default is ring mode). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_PERF_NOTIFY_VIDEOEVENT (0x2080205d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS_MESSAGE_ID (0x5DU) + +typedef struct NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS { + NvU32 videoEvent; +} NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS; + +#define NV2080_CTRL_PERF_VIDEOEVENT_EVENT_MASK (0x0000ffff) +#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START (0x00000001) +#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP (0x00000002) +#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_START NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START +#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_STOP NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP +#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_START (0x00000003) +#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_STOP (0x00000004) +#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_START (0x00000005) +#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_STOP (0x00000006) +#define NV2080_CTRL_PERF_VIDEOEVENT_OFA_START (0x00000007) +#define NV2080_CTRL_PERF_VIDEOEVENT_OFA_STOP (0x00000008) +#define NV2080_CTRL_PERF_VIDEOEVENT_FLAG_LINEAR_MODE (0x00010000) + +/*! + * @defgroup NV2080_CTRL_PERF_PSTATES + * + * These are definitions of performance states (P-states) values. + * P0 has the maximum performance capability and consumes maximum + * power. P1 has a lower perf and power than P0, and so on. + * For NVIDIA GPUs, the following definitions are made: + * P0 - maximum 3D performance + * P1 - original P0 when active clocked + * P2-P3 - balanced 3D performance-power + * P8 - basic HD video playback + * P10 - SD video playback + * P12 - minimum idle power + * P15 - max possible P-state under current scheme (currently not used) + * Not all P-states are available on a given system. + * + * @note The @ref NV2080_CTRL_PERF_PSTATES_ID was introduced after the + * original constants were added, so not all places that intend to use + * these values are using the type. They should be updated to do so. + * @{ + */ +typedef NvU32 NV2080_CTRL_PERF_PSTATES_ID; +#define NV2080_CTRL_PERF_PSTATES_UNDEFINED (0x00000000U) +#define NV2080_CTRL_PERF_PSTATES_CLEAR_FORCED (0x00000000U) +#define NV2080_CTRL_PERF_PSTATES_MIN (0x00000001U) +#define NV2080_CTRL_PERF_PSTATES_P0 (0x00000001U) +#define NV2080_CTRL_PERF_PSTATES_P1 (0x00000002U) +#define NV2080_CTRL_PERF_PSTATES_P2 (0x00000004U) +#define NV2080_CTRL_PERF_PSTATES_P3 (0x00000008U) +#define NV2080_CTRL_PERF_PSTATES_P4 (0x00000010U) +#define NV2080_CTRL_PERF_PSTATES_P5 (0x00000020U) +#define NV2080_CTRL_PERF_PSTATES_P6 (0x00000040U) +#define NV2080_CTRL_PERF_PSTATES_P7 (0x00000080U) +#define NV2080_CTRL_PERF_PSTATES_P8 (0x00000100U) +#define NV2080_CTRL_PERF_PSTATES_P9 (0x00000200U) +#define NV2080_CTRL_PERF_PSTATES_P10 (0x00000400U) +#define NV2080_CTRL_PERF_PSTATES_P11 (0x00000800U) +#define NV2080_CTRL_PERF_PSTATES_P12 (0x00001000U) +#define NV2080_CTRL_PERF_PSTATES_P13 (0x00002000U) +#define NV2080_CTRL_PERF_PSTATES_P14 (0x00004000U) +#define NV2080_CTRL_PERF_PSTATES_P15 (0x00008000U) +#define NV2080_CTRL_PERF_PSTATES_MAX NV2080_CTRL_PERF_PSTATES_P15 +#define NV2080_CTRL_PERF_PSTATES_SKIP_ENTRY (0x10000U) /* finn: Evaluated from "(NV2080_CTRL_PERF_PSTATES_MAX << 1)" */ +#define NV2080_CTRL_PERF_PSTATES_ALL (0xffffU) /* finn: Evaluated from "(NV2080_CTRL_PERF_PSTATES_MAX | (NV2080_CTRL_PERF_PSTATES_MAX - 1))" */ +/*!@}*/ + +/* + * NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE + * + * This command returns the current performance state of the GPU. + * + * currPstate + * This parameter returns the current P-state, as defined in + * NV2080_CTRL_PERF_PSTATES values. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE (0x20802068) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_MESSAGE_ID (0x68U) + +typedef struct NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS { + NvU32 currPstate; +} NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS; + +/* + * NV2080_CTRL_CMD_PERF_GET_TEGRA_PERFMON_SAMPLE + * + * Fetch the busyness of the specified clock domain in percentage + * for Tegra chips. + * + * clkDomain + * Clock domain identifier for Tegra platforms. + * + * clkPercentBusy + * Busyness of the specified clock domain in percentage + * unit ranging from 0 to 100. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_PERF_GET_TEGRA_PERFMON_SAMPLE (0x20802069) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_TEGRA_PERFMON_SAMPLE_PARAMS_MESSAGE_ID" */ + +typedef NvU32 NV2080_CTRL_CLK_DOMAIN_TEGRA; + +#define NV2080_CTRL_PERF_GET_TEGRA_PERFMON_SAMPLE_PARAMS_MESSAGE_ID (0x69U) + +typedef struct NV2080_CTRL_PERF_GET_TEGRA_PERFMON_SAMPLE_PARAMS { + NV2080_CTRL_CLK_DOMAIN_TEGRA clkDomain; + NvU32 clkPercentBusy; +} NV2080_CTRL_PERF_GET_TEGRA_PERFMON_SAMPLE_PARAMS; + + +/* _ctrl2080perf_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080perf_cf.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080perf_cf.h new file mode 100644 index 0000000..137549f --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080perf_cf.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080perf_cf.finn +// + + +/* _ctrl2080perf_cf_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h new file mode 100644 index 0000000..a0b1190 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.finn +// + + + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080pmgr.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080pmgr.h new file mode 100644 index 0000000..6fcd9ac --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080pmgr.h @@ -0,0 +1,67 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080pmgr.finn +// + + + +#define NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED 0U +#define NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED 1U +#define NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_APPLICABLE 2U + +/*! + * NV2080_CTRL_PMGR_MODULE_INFO_PARAMS + * + * This provides information about different module properties + * + * moduleId[OUT] + * - This is a static HW identifier that is unique for each module on a given baseboard. + * For non-baseboard products this would always be 0. + * nvswitchSupport[OUT] + * - NVSwitch present or not. Possible values are + * NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED + * NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED + * NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_APPLICABLE + */ +#define NV2080_CTRL_PMGR_MODULE_INFO_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_PMGR_MODULE_INFO_PARAMS { + NvU32 moduleId; + NvU8 nvswitchSupport; +} NV2080_CTRL_PMGR_MODULE_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_PMGR_GET_MODULE_INFO + * + * Control call to query the subdevice module INFO. + * + */ +#define NV2080_CTRL_CMD_PMGR_GET_MODULE_INFO (0x20802609) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PMGR_INTERFACE_ID << 8) | NV2080_CTRL_PMGR_MODULE_INFO_PARAMS_MESSAGE_ID" */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080pmu.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080pmu.h new file mode 100644 index 0000000..a364a64 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080pmu.h @@ -0,0 +1,38 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080pmu.finn +// + + + +/*! + * @file + * + * @brief Enumeration of all PMU RMCTRL identifiers. + */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080pmumon.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080pmumon.h new file mode 100644 index 0000000..2cdde1e --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080pmumon.h @@ -0,0 +1,100 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080pmumon.finn +// + + + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/*! + * Enumeration of retrieval modes that dictate how many + * samples to grab from the PMUMON queue. + */ +typedef enum NV2080_CTRL_PMUMON_RETRIEVAL_MODE { + NV2080_CTRL_PMUMON_RETRIEVAL_MODE_ALL_SAMPLES = 0, + NV2080_CTRL_PMUMON_RETRIEVAL_MODE_LATEST_SAMPLE_ONLY = 1, +} NV2080_CTRL_PMUMON_RETRIEVAL_MODE; + +/*! + * This structure represents base class of PMUMON sample. + */ +typedef struct NV2080_CTRL_PMUMON_SAMPLE { + /*! + * Ptimer timestamp in nano-seconds at the time this sample was taken. + */ + NV_DECLARE_ALIGNED(NvU64 timestamp, 8); +} NV2080_CTRL_PMUMON_SAMPLE; + +/*! + * Common meta-data to be used in control call parameters regarding sampling of + * FB Circular Queues. + */ +typedef struct NV2080_CTRL_PMUMON_GET_SAMPLES_SUPER { + /*! + * [in/out] Requested starting index for reading into the circular queue. + * This field will be set to (headIndex + 1) % QUEUE_SIZE + * automatically by the control call. + */ + NvU32 tailIndex; + + /*! + * [in/out] Current sequence ID of the underlying PMUMON queue. Not to be + * modified by the caller. Will be modified automatically by the + * control call. + */ + NvU32 sequenceId; + + /*! + * [out] Current head of the queue. The entry at this index in the queue + * is the most recently published. + */ + NvU32 headIndex; + + /*! + * [out] Number of elements copied into samples[] starting from samples[0] + * of parent structure. This is the number of elements between the + * input tailIndex and current headIndex + */ + NvU32 numSamples; + + /*! + * [out] Number of times the PMUMON queue in FB has been reset + * (i.e. pmuStateLoad). When resetCount of the RM and the client + * differ, the RM will correctly resume reading of queue from index 0 + * instead of attempting to catch up from last read. + */ + NvU32 resetCount; + + /*! + * [in] @copydoc NV2080_CTRL_PMUMON_RETRIEVAL_MODE + */ + NV2080_CTRL_PMUMON_RETRIEVAL_MODE retrievalMode; +} NV2080_CTRL_PMUMON_GET_SAMPLES_SUPER; diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080power.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080power.h new file mode 100644 index 0000000..2f0abcb --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080power.h @@ -0,0 +1,123 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080power.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + + + +/*! + * @brief GC6 flavor ids + */ +typedef enum NV2080_CTRL_GC6_FLAVOR_ID { + NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID = 0, + NV2080_CTRL_GC6_FLAVOR_ID_OPTIMUS = 1, + + + NV2080_CTRL_GC6_FLAVOR_ID_MAX = 4, +} NV2080_CTRL_GC6_FLAVOR_ID; + +/* + * NV2080_CTRL_CMD_GC6_ENTRY + * + * This command executes the steps of GC6 entry sequence + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED (non-fatal) + * NV_ERR_INVALID_STATE (non-fatal) + * NV_ERR_INVALID_ARGUMENT (non-fatal) + * NV_ERR_NOT_READY (non-fatal) + * NV_ERR_TIMEOUT + * NV_ERR_GENERIC + */ +#define NV2080_CTRL_CMD_GC6_ENTRY (0x2080270d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_INTERFACE_ID << 8) | NV2080_CTRL_GC6_ENTRY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GC6_ENTRY_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV2080_CTRL_GC6_ENTRY_PARAMS { + NV2080_CTRL_GC6_FLAVOR_ID flavorId; + NvU32 stepMask; + struct { + + + NvBool bIsRTD3Transition; + NvBool bIsRTD3CoreRailPowerCut; + + + NvBool bSkipPstateSanity; + } params; +} NV2080_CTRL_GC6_ENTRY_PARAMS; + +/* + * NV2080_CTRL_CMD_GC6_EXIT + * + * This command executes the steps of GC6 exit sequence + * + * Possible status return values are: + * NV_OK + * NV_ERR_GENERIC + */ +#define NV2080_CTRL_CMD_GC6_EXIT (0x2080270e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_INTERFACE_ID << 8) | NV2080_CTRL_GC6_EXIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GC6_EXIT_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV2080_CTRL_GC6_EXIT_PARAMS { + NV2080_CTRL_GC6_FLAVOR_ID flavorId; + struct { + NvBool bIsGpuSelfWake; + NvBool bIsRTD3Transition; + + + NvBool bIsRTD3HotTransition; //output + } params; +} NV2080_CTRL_GC6_EXIT_PARAMS; + +/*! + * @brief GC6 step ids + */ +typedef enum NV2080_CTRL_GC6_STEP_ID { + NV2080_CTRL_GC6_STEP_ID_SR_ENTRY = 0, + NV2080_CTRL_GC6_STEP_ID_GPU_OFF = 1, + NV2080_CTRL_GC6_STEP_ID_MAX = 2, +} NV2080_CTRL_GC6_STEP_ID; + +typedef struct NV2080_CTRL_GC6_FLAVOR_INFO { + NV2080_CTRL_GC6_FLAVOR_ID flavorId; + NvU32 stepMask; +} NV2080_CTRL_GC6_FLAVOR_INFO; + + + +/* _ctrl2080power_h_ */ + + + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080rc.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080rc.h new file mode 100644 index 0000000..25039c5 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080rc.h @@ -0,0 +1,414 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080rc.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* + * NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM + * + * This command returns data read from the specified virtual memory address for + * the associated subdevice. + * + * hChannel + * This parameter specifies the channel object handle from which the virtual + * memory range applies. + * virtAddress + * This parameter specifies the GPU base virtual memory address from which data should + * be read. The amount of data read is specified by the bufferSize parameter. + * bufferPtr + * This parameter specifies the buffer address in the caller's address space into which + * the data is to be returned. The address must be aligned on an 8-byte boundary. + * The buffer must be at least as big as the value specified bufferSize parameter (in bytes). + * bufferSize + * This parameter specifies the size of the buffer referenced by the bufferPtr parameter. + * This parameter also indicates the total number of bytes to be returned. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_XLATE + */ +#define NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS { + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 virtAddress, 8); + NV_DECLARE_ALIGNED(NvP64 bufferPtr, 8); + NvU32 bufferSize; +} NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS; + +#define NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM (0x20802204) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_RC_GET_ERROR_COUNT + * + * This command returns the number of RC errors. + * + * errorCount + * Number of RC errors. + * + * Note: If SMC is enabled, mig/monitor capability must be acquired to query + * aggregate information. Otherwise, the control call returns + * NV_ERR_INSUFFICIENT_PERMISSIONS. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INSUFFICIENT_PERMISSIONS. + */ +#define NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS { + NvU32 errorCount; +} NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS; + +#define NV2080_CTRL_CMD_RC_GET_ERROR_COUNT (0x20802205) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_RC_ERROR_PARAMS_BUFFER_SIZE (0x2000) /* finn: Evaluated from "(8 * 1024)" */ + +#define NV2080_CTRL_CMD_RC_GET_ERROR (0x20802206) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x6" */ + +/* + * NV2080_CTRL_CMD_RC_GET_ERROR_V2 + * + * This command returns an error element in the RC error list. + * + * whichBuffer + * Which Error to return (0 is oldest) + * outputRecordSize + * Output Size of Buffer -- Zero if error record doesn't exist + * recordBuffer + * buffer + * + * Note: If SMC is enabled, mig/monitor capability must be acquired to query + * aggregate information. Otherwise, the control call returns + * NV_ERR_INSUFFICIENT_PERMISSIONS. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INSUFFICIENT_PERMISSIONS. + * + */ + +#define NV2080_CTRL_RC_GET_ERROR_V2_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV2080_CTRL_RC_GET_ERROR_V2_PARAMS { + + NvU32 whichBuffer; // [IN] - which error to return (0 is oldest) + NvU32 outputRecordSize; // [OUT] + NvU8 recordBuffer[NV2080_CTRL_RC_ERROR_PARAMS_BUFFER_SIZE]; +} NV2080_CTRL_RC_GET_ERROR_V2_PARAMS; + +#define NV2080_CTRL_CMD_RC_GET_ERROR_V2 (0x20802213) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_GET_ERROR_V2_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_RC_SET_CLEAN_ERROR_HISTORY + * + * This command cleans error history. + * + * This command has no input parameters. + * + * Possible status values returned are: + * NV_OK + */ + +#define NV2080_CTRL_CMD_RC_SET_CLEAN_ERROR_HISTORY (0x20802207) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x7" */ + +/* + * NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO + * + * This command returns information about the RC watchdog. + * + * watchdogStatusFlags + * This output parameter is a combination of one or more of the following: + * + * NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_NONE + * This is the value of watchdogStatusFlags if no flags are set. + * + * NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_DISABLED + * This means that the watchdog is disabled. + * + * NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_RUNNING + * This means that the watchdog is running. + * + * NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_INITIALIZED + * This means that the watchdog has been initialized. + * + * A typical result would be either "running and initialized", or + * "disabled". However, "initialized, but not running, and not disabled" + * is also quite reasonable (if the computer is hibernating, for example). + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS { + NvU32 watchdogStatusFlags; +} NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS; + +#define NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO (0x20802209) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS_MESSAGE_ID" */ + +/* valid values for watchdogStatusFlags */ +#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_NONE (0x00000000) +#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_DISABLED (0x00000001) +#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_RUNNING (0x00000002) +#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_INITIALIZED (0x00000004) + +/* + * NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG + * + * This command disables the RC watchdog, if possible. + * If, however, another RM client has already explicitly (via NV2080 call) enabled + * the RC watchdog, then this method returns NV_ERR_STATE_IN_USE. + * + * This command, if successful, will prevent other clients from enabling the + * watchdog until the calling RM client releases its request with + * NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS or frees its NV20_SUBDEVICE. + * + * See NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG for disabling the watchdog + * without preventing other clients from enabling it. + * + * Possible status return values are: + * NV_OK + * NV_ERR_STATE_IN_USE + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG (0x2080220a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xA" */ + +/* + * NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG + * + * This command enables the RC watchdog, if possible. + * If, however, another RM client has already explicitly (via NV2080 call) disabled + * the RC watchdog, then this method returns NV_ERR_STATE_IN_USE. + * + * Possible status return values are: + * NV_OK + * NV_ERR_STATE_IN_USE + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG (0x2080220b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xB" */ + +/* + * NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS + * + * This command releases all of the RM client's outstanding requests to enable + * or disable the watchdog. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS (0x2080220c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xC" */ + +/* + * NV2080_CTRL_CMD_SET_RC_RECOVERY/NV2080_CTRL_CMD_GET_RC_RECOVERY + * + * This command disables/enables RC recovery. + * + * rcEnable + * NV2080_CTRL_CMD_SET_RC_RECOVERY_DISABLED + * Disable robust channel recovery. + * + * NV2080_CTRL_CMD_SET_RC_RECOVERY_ENABLED + * Enable robust channel recovery with default breakpoint handling. + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +typedef struct NV2080_CTRL_CMD_RC_RECOVERY_PARAMS { + NvU32 rcEnable; +} NV2080_CTRL_CMD_RC_RECOVERY_PARAMS; + +#define NV2080_CTRL_CMD_SET_RC_RECOVERY (0x2080220d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_SET_RC_RECOVERY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_SET_RC_RECOVERY_PARAMS_MESSAGE_ID (0xDU) + +typedef NV2080_CTRL_CMD_RC_RECOVERY_PARAMS NV2080_CTRL_SET_RC_RECOVERY_PARAMS; + +#define NV2080_CTRL_CMD_GET_RC_RECOVERY (0x2080220e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_GET_RC_RECOVERY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GET_RC_RECOVERY_PARAMS_MESSAGE_ID (0xEU) + +typedef NV2080_CTRL_CMD_RC_RECOVERY_PARAMS NV2080_CTRL_GET_RC_RECOVERY_PARAMS; + +/* valid values for rcEnable */ +#define NV2080_CTRL_CMD_RC_RECOVERY_DISABLED (0x00000000) +#define NV2080_CTRL_CMD_RC_RECOVERY_ENABLED (0x00000001) + +/* + * NV2080_CTRL_CMD_TDR_SET_TIMEOUT_STATE + * + * This command can be used to set TDR timeout state. + * + * It can be used to indicate that a timeout has occurred and that a GPU + * reset will start. It can also be used to indicate that the reset has + * completed along with the corresponding complition status. + * + * cmd + * This parameter is used to indicate the stage of the TDR recovery + * process. Legal values for this parameter are: + * NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_BEGIN + * This value indicates that TDR recovery is about to begin. + * NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END + * This value indicates that TDR recovery has completed. + * + * status + * This parameter is valid when the cmd parameter is set to + * NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END. It is used + * to specify the completion status of the TDR recovery. Legal + * values for this parameter include: + * NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_FAIL + * This value indicates the recovery failed. + * NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_SUCCESS + * This value indicates the recovery succeeded. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_COMMAND + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_TDR_SET_TIMEOUT_STATE (0x2080220f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS { + NvU32 cmd; + NvS32 status; +} NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS; + +/* valid cmd values */ +#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_BEGIN (0x00000000) +#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END (0x00000001) + +/* valid status values */ +#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_SUCCESS (0x00000000) +#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_FAIL (0x00000001) + +/* + * NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG + * + * This command disables the RC watchdog, similarly to how + * NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG does. However, unlike that command, this + * command will not prevent another RM client from explicitly enabling the RC + * watchdog with NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG. + * + * Possible status return values are: + * NV_OK + * NV_ERR_STATE_IN_USE + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG (0x20802210) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x10" */ + +/* + * NV2080_CTRL_CMD_GET_RC_INFO/NV2080_CTRL_CMD_SET_RC_INFO + * + * This command can be used to set robust channel parameters. + * + * rcMode + * NV2080_CTRL_CMD_SET_RC_INFO_MODE_DISABLE + * Disable robust channel operation. + * + * NV2080_CTRL_CMD_SET_RC_INFO_MODE_ENABLE + * Enable robust channel operation. + * + * rcBreak + * NV2080_CTRL_CMD_SET_RC_INFO_BREAK_DISABLE + * Disable breakpoint handling during robust channel operation. + * + * NV2080_CTRL_CMD_SET_RC_INFO_BREAK_ENABLE + * Enable breakpoint handling during robust channel operation. + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +typedef struct NV2080_CTRL_CMD_RC_INFO_PARAMS { + NvU32 rcMode; + NvU32 rcBreak; +} NV2080_CTRL_CMD_RC_INFO_PARAMS; + +#define NV2080_CTRL_CMD_SET_RC_INFO (0x20802211) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_SET_RC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_SET_RC_INFO_PARAMS_MESSAGE_ID (0x11U) + +typedef NV2080_CTRL_CMD_RC_INFO_PARAMS NV2080_CTRL_SET_RC_INFO_PARAMS; + +#define NV2080_CTRL_CMD_GET_RC_INFO (0x20802212) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_GET_RC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GET_RC_INFO_PARAMS_MESSAGE_ID (0x12U) + +typedef NV2080_CTRL_CMD_RC_INFO_PARAMS NV2080_CTRL_GET_RC_INFO_PARAMS; + +/* valid rcMode values */ +#define NV2080_CTRL_CMD_RC_INFO_MODE_DISABLE (0x00000000) +#define NV2080_CTRL_CMD_RC_INFO_MODE_ENABLE (0x00000001) + +/* valid rcBreak values */ +#define NV2080_CTRL_CMD_RC_INFO_BREAK_DISABLE (0x00000000) +#define NV2080_CTRL_CMD_RC_INFO_BREAK_ENABLE (0x00000001) + +/* + * NV2080_CTRL_CMD_GET_RC_WATCHDOG_INFO/NV2080_CTRL_CMD_SET_RC_WATCHDOG_INFO + * + * This command can be used to set RC watchdog parameters. + * This control is supported only on MODS. + * + * Possible status return values are: + * NV_OK + */ +typedef struct NV2080_CTRL_CMD_RC_WATCHDOG_INFO_PARAMS { + NvU32 channelTestInterval; + NvU32 thwapChannelMask; + NvU32 stompChannelMask; + NvU32 thwapRepeatMask; + NvU32 stompRepeatMask; + NvU32 allocFailMask; +} NV2080_CTRL_CMD_RC_WATCHDOG_INFO_PARAMS; + +#define NV2080_CTRL_CMD_SET_RC_WATCHDOG_INFO (0x20802214) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_SET_RC_WATCHDOG_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_SET_RC_WATCHDOG_INFO_PARAMS_MESSAGE_ID (0x14U) + +typedef NV2080_CTRL_CMD_RC_WATCHDOG_INFO_PARAMS NV2080_CTRL_SET_RC_WATCHDOG_INFO_PARAMS; + +#define NV2080_CTRL_CMD_GET_RC_WATCHDOG_INFO (0x20802215) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_GET_RC_WATCHDOG_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GET_RC_WATCHDOG_INFO_PARAMS_MESSAGE_ID (0x15U) + +typedef NV2080_CTRL_CMD_RC_WATCHDOG_INFO_PARAMS NV2080_CTRL_GET_RC_WATCHDOG_INFO_PARAMS; + +/* _ctrl2080rc_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080spdm.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080spdm.h new file mode 100644 index 0000000..4c25165 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080spdm.h @@ -0,0 +1,248 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080spdm.finn +// + + + +/*************************** SPDM COMMANDS ************************************/ + +#include "cc_drv.h" + +/*! + * @brief SPDM Command Types + * + */ +#define RM_GSP_SPDM_CMD_ID_CC_INIT (0x1) +#define RM_GSP_SPDM_CMD_ID_CC_DEINIT (0x2) +#define RM_GSP_SPDM_CMD_ID_CC_CTRL (0x3) +#define RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA (0x4) +#define RM_GSP_SPDM_CMD_ID_CC_HEARTBEAT_CTRL (0x5) +#define RM_GSP_SPDM_CMD_ID_FIPS_SELFTEST (0x6) + + +#define RM_GSP_SPDM_CMD_ID_INVALID_COMMAND (0xFF) + +#define SPDM_SESSION_ESTABLISHMENT_TRANSCRIPT_BUFFER_SIZE 0x2400 + + + +#define RSVD7_SIZE 16 + +#define RSVD8_SIZE 2 + +/*! + * Guest RM provides INIT context + */ +typedef struct RM_GSP_SPDM_CMD_CC_INIT { + // Command must be first as this struct is the part of union + NvU8 cmdType; +} RM_GSP_SPDM_CMD_CC_INIT; +typedef struct RM_GSP_SPDM_CMD_CC_INIT *PRM_GSP_SPDM_CMD_CC_INIT; + +/*! + * Guest RM provides INIT context + */ +typedef struct RM_GSP_SPDM_CMD_CC_DEINIT { + // Command must be first as this struct is the part of union + NvU8 cmdType; +} RM_GSP_SPDM_CMD_CC_DEINIT; +typedef struct RM_GSP_SPDM_CMD_CC_DEINIT *PRM_GSP_SPDM_CMD_CC_DEINIT; + +/*! + * RM provides the SPDM request info to GSP + */ +typedef struct RM_GSP_SPDM_CMD_CC_CTRL { + // Command must be first as this struct is the part of union + NvU8 cmdType; +} RM_GSP_SPDM_CMD_CC_CTRL; +typedef struct RM_GSP_SPDM_CMD_CC_CTRL *PRM_GSP_SPDM_CMD_CC_CTRL; + +typedef struct RM_GSP_SPDM_CMD_CC_INIT_RM_DATA { + // Command must be first as this struct is the part of union + NvU8 cmdType; + + NvU32 rsvd0[2]; + + NvU32 rsvd1; + + char rsvd2[9]; + + char rsvd3[5]; + + char rsvd4[5]; + + char rsvd5[5]; + + char rsvd6[2]; + + char rsvd7[RSVD7_SIZE]; + + NvU32 rsvd8[RSVD8_SIZE]; +} RM_GSP_SPDM_CMD_CC_INIT_RM_DATA; +typedef struct RM_GSP_SPDM_CMD_CC_INIT_RM_DATA *PRM_GSP_SPDM_CMD_CC_INIT_RM_DATA; + +typedef struct RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL { + // Command must be first as this struct is the part of union + NvU8 cmdType; + + // Whether to enable or disable heartbeats + NvBool bEnable; +} RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL; +typedef struct RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL *PRM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL; + + + +/*! + * HCC FIPS Self-test. + */ +#define CE_FIPS_SELF_TEST_DATA_SIZE 16 +#define CE_FIPS_SELF_TEST_AUTH_TAG_SIZE 16 +#define CE_FIPS_SELF_TEST_IV_SIZE 12 + +typedef struct RM_GSP_SPDM_CMD_FIPS_SELFTEST { + NvU8 cmdType; + NvU8 isEnc; + CC_KMB kmb; + NvU8 text[CE_FIPS_SELF_TEST_DATA_SIZE]; + NvU8 authTag[CE_FIPS_SELF_TEST_AUTH_TAG_SIZE]; +} RM_GSP_SPDM_CMD_FIPS_SELFTEST; +typedef struct RM_GSP_SPDM_CMD_FIPS_SELFTEST *PRM_GSP_SPDM_CMD_FIPS_SELFTEST; + + + +/*! + * NOTE : Do not include structure members that have alignment requirement >= 8 to avoid alignment directives + * getting added in FINN generated structures / unions as RM_GSP_SPDM_CMD / RM_GSP_SPDM_MSG are pragma packed in + * other structures like RM_FLCN_CMD_GSP / RM_FLCN_MSG_GSP and pragma pack does not produce consistent behavior + * when paired with alignment directives on Linux and Windows. + */ + +/*! + * A union of all SPDM Commands. + */ +typedef union RM_GSP_SPDM_CMD { + NvU8 cmdType; + RM_GSP_SPDM_CMD_CC_INIT ccInit; + RM_GSP_SPDM_CMD_CC_DEINIT ccDeinit; + RM_GSP_SPDM_CMD_CC_CTRL ccCtrl; + RM_GSP_SPDM_CMD_CC_INIT_RM_DATA rmDataInitCmd; + RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL ccHeartbeatCtrl; + + + RM_GSP_SPDM_CMD_FIPS_SELFTEST ccFipsTest; + +} RM_GSP_SPDM_CMD; +typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD; + +/***************************** SPDM MESSAGES *********************************/ + +/*! + * SPDM Message Status + */ + +/*! + * Returns the status for program CE keys to RM + */ +#define RM_GSP_SPDM_MSG_ID_CC_INIT (0x1) +#define RM_GSP_SPDM_MSG_ID_CC_DEINIT (0x2) +#define RM_GSP_SPDM_MSG_ID_CC_CTRL (0x3) +#define RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA (0x4) +#define RM_GSP_SPDM_MSG_ID_CC_HEARTBEAT_CTRL (0x5) +#define RM_GSP_SPDM_MSG_ID_FIPS_SELFTEST (0x6) + + + +/*! + * Returns the Error Status for Invalid Command + */ +#define RM_GSP_SPDM_MSG_ID_INVALID_COMMAND (0xFF) + +/*! + * NOTE : Do not include structure members that have alignment requirement >= 8 to avoid alignment directives + * getting added in FINN generated structures / unions as RM_GSP_SPDM_CMD / RM_GSP_SPDM_MSG are pragma packed in + * other structures like RM_FLCN_CMD_GSP / RM_FLCN_MSG_GSP and pragma pack does not produce consistent behavior + * when paired with alignment directives on Linux and Windows. + */ + +/*! + * SPDM message structure. + */ +typedef struct RM_GSP_SPDM_MSG { + NvU8 msgType; + + // status returned from GSP message infrastructure. + NvU32 status; + + NvU32 rsvd1; + + NvU32 rsvd2; + + NvU32 rsvd3; + + NvU32 rsvd4; + + NvU32 rsvd5; +} RM_GSP_SPDM_MSG; +typedef struct RM_GSP_SPDM_MSG *PRM_GSP_SPDM_MSG; + +/* + * NV2080_CTRL_CMD_INTERNAL_SPDM_PARTITION + * + * This command does a partition switch to SPDM partition + * + */ +#define NV2080_CTRL_INTERNAL_SPDM_PARTITION (0x20800ad9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS_MESSAGE_ID (0xD9U) + +typedef struct NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS { + NvU8 index; + RM_GSP_SPDM_CMD cmd; + RM_GSP_SPDM_MSG msg; +} NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS; + +/* + * NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT + * + * This command retrieves the transcript of SPDM session establishment messages. + * + */ +#define NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS_MESSAGE_ID (0xDAU) + +typedef struct NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS { + NvU8 transcript[SPDM_SESSION_ESTABLISHMENT_TRANSCRIPT_BUFFER_SIZE]; + NvU32 transcriptSize; +} NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS; + + + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080spi.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080spi.h new file mode 100644 index 0000000..0b378d2 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080spi.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080spi.finn +// + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080thermal.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080thermal.h new file mode 100644 index 0000000..25d6c42 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080thermal.h @@ -0,0 +1,417 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080thermal.finn +// + + + +/* + * Thermal System rmcontrol api versioning + */ +#define THERMAL_SYSTEM_API_VER 1U +#define THERMAL_SYSTEM_API_REV 0U + +/* + * NV2080_CTRL_THERMAL_SYSTEM constants + * + */ + +/* + * NV2080_CTRL_THERMAL_SYSTEM_TARGET + * + * Targets (ie the things the thermal system can observe). Target mask + * have to be in sync with corresponding element of NVAPI_THERMAL_TARGET + * enum, until there is a translation layer between these two. + * + * NV2080_CTRL_THERMAL_SYSTEM_TARGET_NONE + * There is no target. + * + * NV2080_CTRL_THERMAL_SYSTEM_TARGET_GPU + * The GPU is the target. + * + * NV2080_CTRL_THERMAL_SYSTEM_TARGET_MEMORY + * The memory is the target. + * + * NV2080_CTRL_THERMAL_SYSTEM_TARGET_POWER_SUPPLY + * The power supply is the target. + * + * NV2080_CTRL_THERMAL_SYSTEM_TARGET_BOARD + * The board (PCB) is the target. + */ + + + /* NV2080_CTRL_THERMAL_SYSTEM_TARGET_UNKNOWN + * The target is unknown. + */ +#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_NONE (0x00000000U) +#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_GPU (0x00000001U) +#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_MEMORY (0x00000002U) +#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_POWER_SUPPLY (0x00000004U) +#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_BOARD (0x00000008U) + + +#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_UNKNOWN (0xFFFFFFFFU) + +/* + * executeFlags values + */ +#define NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_FLAGS_DEFAULT (0x00000000U) +#define NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_FLAGS_IGNORE_FAIL (0x00000001U) + + +/* + * NV2080_CTRL_CMD_THERMAL_SYSTEM_EXECUTE_V2 + * + * This command will execute a list of thermal system instructions: + * + * clientAPIVersion + * This field must be set by the client to THERMAL_SYSTEM_API_VER, + * which allows the driver to determine api compatibility. + * + * clientAPIRevision + * This field must be set by the client to THERMAL_SYSTEM_API_REV, + * which allows the driver to determine api compatibility. + * + * clientInstructionSizeOf + * This field must be set by the client to + * sizeof(NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION), which allows the + * driver to determine api compatibility. + * + * executeFlags + * This field is set by the client to control instruction execution. + * NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_FLAGS_DEFAULT + * Execute instructions normally. The first instruction + * failure will cause execution to stop. + * NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_FLAGS_IGNORE_FAIL + * Execute all instructions, ignoring individual instruction failures. + * + * successfulInstructions + * This field is set by the driver and is the number of instructions + * that returned NV_OK on execution. If this field + * matches instructionListSize, all instructions executed successfully. + * + * instructionListSize + * This field is set by the client to the number of instructions in + * instruction list. + * + * instructionList + * This field is set an array of thermal system instructions + * (NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION) to execute, filled in by the + * client. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV2080_CTRL_CMD_THERMAL_SYSTEM_EXECUTE_V2 (0x20800513U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_THERMAL_INTERFACE_ID << 8) | NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_THERMAL_SYSTEM_EXECUTE_V2_PHYSICAL (0x20808513U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_THERMAL_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO instructions... + * + */ + +/* + * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE instruction + * + * Get the number of available targets. + * + * availableTargets + * Returns the number of available targets. Targets are + * identified by an index, starting with 0. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPCODE (0x00000100U) +typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPERANDS { + NvU32 availableTargets; +} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPERANDS; + +/* + * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE instruction + * + * Get a target's type. + * + * targetIndex + * Set by the client to the desired target index. + * + * type + * Returns a target's type. + * Possible values returned are: + * NV2080_CTRL_THERMAL_SYSTEM_TARGET_NONE + * NV2080_CTRL_THERMAL_SYSTEM_TARGET_GPU + * NV2080_CTRL_THERMAL_SYSTEM_TARGET_MEMORY + * NV2080_CTRL_THERMAL_SYSTEM_TARGET_POWER_SUPPLY + * NV2080_CTRL_THERMAL_SYSTEM_TARGET_BOARD + * NV2080_CTRL_THERMAL_SYSTEM_TARGET_UNKNOWN + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPCODE (0x00000101U) +typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS { + NvU32 targetIndex; + NvU32 type; +} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS; + +/* + * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE instruction + * + * Get a providers's type. + * + * providerIndex + * Set by the client to the desired provider index. + * + * type + * Returns a provider's type. + */ + + + /* + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPCODE (0x00000301U) +typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS { + NvU32 providerIndex; + NvU32 type; +} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS; + +/* + * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE instruction + * + * Get the number of available sensors. + * + * availableSensors + * Returns the number of available sensors. Sensors are + * identified by an index, starting with 0. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPCODE (0x00000500U) +typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS { + NvU32 availableSensors; +} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS; + +/* + * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER instruction + * + * Get a sensor's provider index. + * + * sensorIndex + * Set by the client to the desired sensor index. + * + * providerIndex + * Returns a sensor's provider index. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPCODE (0x00000510U) +typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS { + NvU32 sensorIndex; + NvU32 providerIndex; +} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS; + +/*! + * Union of mode-specific arguments. + */ + + +/* + * NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING instruction + * + * Get a sensor's current reading. + * + * sensorIndex + * Set by the client to the desired sensor index. + * + * value + * Returns a sensor's current reading. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPCODE (0x00001500U) +typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS { + NvU32 sensorIndex; + NvS32 value; +} NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS; + +/* + * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET instruction + * + * Get a sensor's target index. + * + * sensorIndex + * Set by the client to the desired sensor index. + * + * targetIndex + * Returns a sensor's target index. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPCODE (0x00000520U) +typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS { + NvU32 sensorIndex; + NvU32 targetIndex; +} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS; + +/* + * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE instruction + * + * Get a sensor's readings range (ie min, max). + * + * sensorIndex + * Set by the client to the desired sensor index. + * + * minimum + * Returns a sensor's range minimum. + * + * maximum + * Returns a sensor's range maximum. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPCODE (0x00000540U) +typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS { + NvU32 sensorIndex; + NvS32 minimum; + NvS32 maximum; +} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS; + +/* + * Thermal System instruction operand + */ +typedef union NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_OPERANDS { + + NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPERANDS getInfoTargetsAvailable; + + NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS getInfoTargetType; + + NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS getInfoProviderType; + + NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS getInfoSensorsAvailable; + + NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS getInfoSensorProvider; + + NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS getInfoSensorTarget; + + NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS getInfoSensorReadingRange; + + NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS getStatusSensorReading; + + + NvU32 space[8]; +} NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_OPERANDS; + +/* + * NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION + * + * All thermal system instructions have the following layout: + * + * result + * This field is set by the driver, and is the result of the + * instruction's execution. This value is only valid if the + * executed field is not 0 upon return. + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + * + * executed + * This field is set by the driver, and + * indicates if the instruction was executed. + * Possible status values returned are: + * 0: Not executed + * 1: Executed + * + * opcode + * This field is set by the client to the desired instruction opcode. + * Possible values are: + * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPCODE + * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPCODE + * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPCODE + * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPCODE + * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPCODE + * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPCODE + * NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPCODE + */ + + + /* + * operands + * This field is actually a union of all of the available operands. + * The interpretation of this field is opcode context dependent. + * Possible values are: + * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS + * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS + * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS + * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS + * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS + * NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS + * NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS + */ + + +typedef struct NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION { + NvU32 result; + NvU32 executed; + NvU32 opcode; + NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_OPERANDS operands; +} NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION; + +#define NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_MAX_COUNT 0x20U +#define NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS { + NvU32 clientAPIVersion; + NvU32 clientAPIRevision; + NvU32 clientInstructionSizeOf; + NvU32 executeFlags; + NvU32 successfulInstructions; + NvU32 instructionListSize; + NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION instructionList[NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_MAX_COUNT]; +} NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS; + +/* _ctrl2080thermal_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080tmr.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080tmr.h new file mode 100644 index 0000000..4d51f63 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080tmr.h @@ -0,0 +1,260 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2008-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080tmr.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_TIMER related control commands and parameters */ + +/* + * NV2080_CTRL_CMD_TIMER_SCHEDULE + * + * This command schedules a GPU timer event to fire at the specified time interval. + * Can be called without API & GPU locks if NVOS54_FLAGS_IRQL_RAISED and + * NVOS54_FLAGS_LOCK_BYPASS are set in NVOS54_PARAMETERS.flags + * + * time_nsec + * This parameter specifies the time in nanoseconds at which the GPU timer + * event is to fire. + * flags + * This parameter determines the interpretation of the value specified by + * the time_nsec parameter: + * NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_ABS + * This flag indicates that time_nsec is in absolute time. + * NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_REL + * This flag indicates that time_nsec is in relative time. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_TIMER_SCHEDULE (0x20800401) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 time_nsec, 8); + NvU32 flags; +} NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS; + +/* valid flag values */ +#define NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME 0:0 +#define NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_ABS (0x00000000) +#define NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_REL (0x00000001) + +/* + * NV2080_CTRL_CMD_TIMER_CANCEL + * + * This command cancels any pending timer events initiated with the + * NV2080_CTRL_CMD_TIMER_SCHEDULE command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_TIMER_CANCEL (0x20800402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | 0x2" */ + +/* + * NV2080_CTRL_CMD_TIMER_GET_TIME + * + * This command returns the current GPU timer value. The current time is + * expressed in elapsed nanoseconds since 00:00 GMT, January 1, 1970 + * (zero hour) with a resolution of 32 nanoseconds. + * + * Can be called without API & GPU locks if NVOS54_FLAGS_IRQL_RAISED and + * NVOS54_FLAGS_LOCK_BYPASS are set in NVOS54_PARAMETERS.flags + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_TIMER_GET_TIME (0x20800403) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_TIMER_GET_TIME_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_TIMER_GET_TIME_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_TIMER_GET_TIME_PARAMS { + NV_DECLARE_ALIGNED(NvU64 time_nsec, 8); +} NV2080_CTRL_TIMER_GET_TIME_PARAMS; + +/* + * NV2080_CTRL_CMD_TIMER_GET_REGISTER_OFFSET + * + * The command returns the offset of the timer registers, so that clients may + * map them directly. + * + * Possible status values returned are: + * NV_OK + */ + +#define NV2080_CTRL_CMD_TIMER_GET_REGISTER_OFFSET (0x20800404) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS { + NvU32 tmr_offset; +} NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS; + +/* + * NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE + * + * This structure describes the information obtained with + * NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO command. + * + * gpuTime + * GPU time is the value of GPU global timer (PTIMER) with a resolution + * of 32 nano seconds. + * cpuTime + * CPU time. Resolution of the cpu time depends on its source. Refer to + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_* for more information. + + */ +typedef struct NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE { + NV_DECLARE_ALIGNED(NvU64 cpuTime, 8); + NV_DECLARE_ALIGNED(NvU64 gpuTime, 8); +} NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE; + + +/* + * NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO + * + * This command returns correlation information between GPU time and CPU time + * for a given CPU clock type. + * + * cpuClkId + * This parameter specifies the source of the CPU clock. This parameter is + * composed of two fields: + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_SOURCE + * This field specifies source ID of the CPU clock in question. Legal + * values for this parameter include: + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME + * This clock id will provide real time in microseconds since + * 00:00:00 UTC on January 1, 1970, as reported by the host OS. + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API + * This clock id will provide time stamp that is constant-rate, high + * precision using platform API that is also available in the user + * mode. + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC + * This clock id will provide time stamp using CPU's time stamp + * counter. + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR + * This field specifies the processor whose clock should be used for the + * source. The control call and cpuClkId parameter remain named for the + * CPU specifically for legacy reasons. Not all processors will support + * all clock sources. Legal values for this parameter include: + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_CPU + * The clock information will be fulfilled by the CPU. This value + * is defined to be 0 so that it is the default for backwards + * compatibility. + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_GSP + * The clock information will be fulfilled by the GSP. + * + * sampleCount + * This field specifies the number of clock samples to be taken. + * This value cannot exceed NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES. + * + * samples + * This field returns an array of requested samples. Refer to + * NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE to get details about each entry + * in the array. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO (0x20800406) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES 16 + +#define NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS { + NvU8 cpuClkId; + NvU8 sampleCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE samples[NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES], 8); +} NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS; + +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_SOURCE 3:0 + +/* Legal NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_SOURCE values */ +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME (0x00000001) +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC (0x00000002) +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API (0x00000003) +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_GSP_OS (0x00000004) + +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR 7:4 + +/* Legal NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR values */ +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_CPU (0x00000000) +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_GSP (0x00000001) + + +/*! + * NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ + * + * This command changes the frequency at which Graphics Engine time stamp is + * updated. Frequency can either be set to max or restored to default. + * Clients can independently use this call to increase the timer frequency + * as a global reference count is maintained for requests to Max frequency. + * Client is assured that the system stays in this state till the requested + * client releases the state or is killed. Timer frequency will automatically + * be restored to default when there is no pending request to increase. + * + * Note that recursive requests for the same state from the same client + * are considered invalid. + * + * bSetMaxFreq + * Set to NV_TRUE if GR tick frequency needs to be set to Max. + * + * See @ref NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS for + * documentation of parameters. + * + * Possible status values returned are + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_STATE_IN_USE + * NV_ERR_INVALID_OPERATION + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ (0x20800407) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID" */ + +/*! + * This struct contains bSetMaxFreq flag. + */ +#define NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS { + NvBool bSetMaxFreq; +} NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS; + +/* _ctrl2080tmr_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h new file mode 100644 index 0000000..56463fb --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080ucodefuzzer.finn +// + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080unix.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080unix.h new file mode 100644 index 0000000..b058211 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080unix.h @@ -0,0 +1,190 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080unix.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX OS control commands and parameters */ + +/* + * NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT + * + * This command increases or decreases the value of the per-GPU GC6 blocker + * refCount used by Linux kernel clients to prevent the GPU from entering GC6. + * + * When the refCount is non-zero, the GPU cannot enter GC6. When the refCount + * transitions from zero to non-zero as a result of this command, the GPU will + * automatically come out of GC6. + * + * action Whether to increment or decrement the value of the refCount. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT (0x20803d01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS { + NvU32 action; +} NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS; + +// Possible values for action +#define NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_INC (0x00000001) +#define NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_DEC (0x00000002) + +/* + * NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF + * + * RM by default allows GCOFF but when the X driver disallows to enter in GCOFF + * then this rmcontrol sets flag as NV_FALSE and if it allows to enter in GCOFF + * then the flag is set as NV_TRUE. + * + * action Whether to allow or disallow the user mode clients to enter in GCOFF. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF (0x20803d02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS { + NvU32 action; +} NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS; + +// Possible values for action +#define NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_ALLOW (0x00000001) +#define NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_DISALLOW (0x00000002) + +/* + * NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER + * + * GPU can have integrated HDA (High Definition Audio) controller which + * can be in active or suspended state during dynamic power management. + * This command will perform HDA controller wakeup (if bEnter is false) or + * suspend (if bEnter is true). + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER (0x20803d03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS { + NvBool bEnter; +} NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS; + +/* + * NV2080_CTRL_CMD_OS_UNIX_INSTALL_PROFILER_HOOKS + * + * Initialize cyclestats HWPM support in the kernel. This will set up a callback + * event for the channel indicated by hNotifierResource. This callback will execute + * perf register read / write commands enqueued in the shared buffer indicated by + * hNotifyDataMemory. Only one client may use HWPM functionality at a time. + * + * Additionally, if perfmonIdCount is greater than zero, mode-e HWPM streaming into + * the buffer indicated by hSnapshotMemory will be initialized (but not turned on). + * Data will be copied into the provided buffer every 10ms, or whenever a + * NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER command is issued. + */ +#define NV2080_CTRL_CMD_OS_UNIX_INSTALL_PROFILER_HOOKS (0x20803d04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS { + NvHandle hNotifierResource; + NvU32 notifyDataSize; + NvHandle hNotifyDataMemory; + NvU32 perfmonIdCount; + NvU32 snapshotBufferSize; + NvHandle hSnapshotMemory; +} NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS; + +/* + * NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER + * + * Immediately copies any pending mode-e HWPM data into the previously + * installed snapshot buffer instead of waiting for the timer. + */ +#define NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER (0x20803d05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | 0x5" */ + +/* + * NV2080_CTRL_CMD_OS_UNIX_STOP_PROFILER + * + * Stop the timer responsible for copying mode-e HWPM data to the snapshot buffer. + * The snapshot buffer must not be freed by the client before this command is issued. + */ +#define NV2080_CTRL_CMD_OS_UNIX_STOP_PROFILER (0x20803d06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | 0x6" */ + +/* + * NV2080_CTRL_CMD_OS_UNIX_VIDMEM_PERSISTENCE_STATUS + * + * This command will be used by clients to check if the GPU video memory will + * be persistent during system suspend/resume cycle. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_OS_UNIX_VIDMEM_PERSISTENCE_STATUS (0x20803d07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS { + NvBool bVidmemPersistent; +} NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_OS_UNIX_UPDATE_TGP_STATUS + * + * This command will be used by clients to set restore TGP flag which will + * help to restore TGP limits when clients are destroyed. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_OS_UNIX_UPDATE_TGP_STATUS (0x20803d08) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS { + NvBool bUpdateTGP; +} NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS; +/* _ctrl2080unix_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080vfe.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080vfe.h new file mode 100644 index 0000000..5742c5e --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080vfe.h @@ -0,0 +1,42 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080vfe.finn +// + + + +/* _ctrl2080vfe_h_ */ +#include "nvfixedtypes.h" +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "ctrl/ctrl2080/ctrl2080boardobj.h" +#include "ctrl/ctrl2080/ctrl2080bios.h" + +/* --------------------------- Forward Defines ----------------------------- */ +/* --------------------------- VFE Variable -------------------------------- */ +/* --------------------------- VFE Equation -------------------------------- */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h new file mode 100644 index 0000000..4b63733 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h @@ -0,0 +1,522 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080vgpumgrinternal.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "ctrl/ctrla081.h" + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK + * + * This command is used to bootload GSP VGPU plugin task. + * Can be called only with SR-IOV and with VGPU_GSP_PLUGIN_OFFLOAD feature. + * + * dbdf - domain (31:16), bus (15:8), device (7:3), function (2:0) + * gfid - Gfid + * vgpuType - The Type ID for VGPU profile + * vmPid - Plugin process ID of vGPU guest instance + * swizzId - SwizzId + * numChannels - Number of channels + * numPluginChannels - Number of plugin channels + * bDisableSmcPartitionRestore - If set to true, SMC default execution partition + * save/restore will not be done in host-RM + * guestFbPhysAddrList - list of VMMU segment aligned physical address of guest FB memory + * guestFbLengthList - list of guest FB memory length in bytes + * pluginHeapMemoryPhysAddr - plugin heap memory offset + * pluginHeapMemoryLength - plugin heap memory length in bytes + * migRmHeapMemoryPhysAddr - Mig rm heap memory region's physical offset. + * migRmHeapMemoryLength - Mig rm heap memory length in bytes + * bDeviceProfilingEnabled - If set to true, profiling is allowed + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK (0x20804001) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MAX_VMMU_SEGMENTS 384 + +/* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */ +#define NV2080_GPU_MAX_ENGINES 0x54 + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS { + NvU32 dbdf; + NvU32 gfid; + NvU32 vgpuType; + NvU32 vmPid; + NvU32 swizzId; + NvU32 numChannels; + NvU32 numPluginChannels; + NvU32 chidOffset[NV2080_GPU_MAX_ENGINES]; + NvBool bDisableDefaultSmcExecPartRestore; + NvU32 numGuestFbSegments; + NV_DECLARE_ALIGNED(NvU64 guestFbPhysAddrList[NV2080_CTRL_MAX_VMMU_SEGMENTS], 8); + NV_DECLARE_ALIGNED(NvU64 guestFbLengthList[NV2080_CTRL_MAX_VMMU_SEGMENTS], 8); + NV_DECLARE_ALIGNED(NvU64 pluginHeapMemoryPhysAddr, 8); + NV_DECLARE_ALIGNED(NvU64 pluginHeapMemoryLength, 8); + NV_DECLARE_ALIGNED(NvU64 ctrlBuffOffset, 8); + NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffOffset, 8); + NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffSize, 8); + NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffOffset, 8); + NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffSize, 8); + NV_DECLARE_ALIGNED(NvU64 kernelLogBuffOffset, 8); + NV_DECLARE_ALIGNED(NvU64 kernelLogBuffSize, 8); + NV_DECLARE_ALIGNED(NvU64 migRmHeapMemoryPhysAddr, 8); + NV_DECLARE_ALIGNED(NvU64 migRmHeapMemoryLength, 8); + NvBool bDeviceProfilingEnabled; +} NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK + * + * This command is used to shutdown GSP VGPU plugin task. + * Can be called only with SR-IOV and with VGPU_GSP_PLUGIN_OFFLOAD feature. + * + * gfid - Gfid + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK (0x20804002) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS { + NvU32 gfid; +} NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE + * + * This command is used to add a new vGPU config to the pGPU in physical RM. + * Unlike NVA081_CTRL_CMD_VGPU_CONFIG_SET_INFO, it does no validation + * and is only to be used internally. + * + * discardVgpuTypes [IN] + * This parameter specifies if existing vGPU configuration should be + * discarded for given pGPU + * + * vgpuInfoCount [IN] + * This parameter specifies the number of entries of virtual GPU type +* information + * + * vgpuInfo [IN] + * This parameter specifies virtual GPU type information + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE (0x20804003) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS { + NvBool discardVgpuTypes; + NvU32 vgpuInfoCount; + NV_DECLARE_ALIGNED(NVA081_CTRL_VGPU_INFO vgpuInfo[NVA081_MAX_VGPU_TYPES_PER_PGPU], 8); +} NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS; + +/* + * NV2080_GUEST_VM_INFO + * + * This structure represents vGPU guest's (VM's) information + * + * vmPid [OUT] + * This param specifies the vGPU plugin process ID + * guestOs [OUT] + * This param specifies the vGPU guest OS type + * migrationProhibited [OUT] + * This flag indicates whether migration is prohibited for VM or not + * guestNegotiatedVgpuVersion [OUT] + * This param specifies the vGPU version of guest driver after negotiation + * frameRateLimit [OUT] + * This param specifies the current value of FRL set for guest + * licensed [OUT] + * This param specifies whether the VM is Unlicensed/Licensed + * licenseState [OUT] + * This param specifies the current state of the GRID license state machine + * licenseExpiryTimestamp [OUT] + * License expiry time in seconds since UNIX epoch + * licenseExpiryStatus [OUT] + * License expiry status + * guestDriverVersion [OUT] + * This param specifies the driver version of the driver installed on the VM + * guestDriverBranch [OUT] + * This param specifies the driver branch of the driver installed on the VM + * guestVmInfoState [OUT] + * This param stores the current state of guest dependent fields + * + */ +typedef struct NV2080_GUEST_VM_INFO { + NvU32 vmPid; + NvU32 guestOs; + NvU32 migrationProhibited; + NvU32 guestNegotiatedVgpuVersion; + NvU32 frameRateLimit; + NvBool licensed; + NvU32 licenseState; + NvU32 licenseExpiryTimestamp; + NvU8 licenseExpiryStatus; + NvU8 guestDriverVersion[NVA081_VGPU_STRING_BUFFER_SIZE]; + NvU8 guestDriverBranch[NVA081_VGPU_STRING_BUFFER_SIZE]; + GUEST_VM_INFO_STATE guestVmInfoState; +} NV2080_GUEST_VM_INFO; + +/* + * NV2080_GUEST_VGPU_DEVICE + * + * This structure represents host vgpu device's (assigned to VM) information + * + * gfid [OUT] + * This parameter specifies the gfid of vGPU assigned to VM. + * vgpuPciId [OUT] + * This parameter specifies vGPU PCI ID + * vgpuDeviceInstanceId [OUT] + * This paramter specifies the vGPU device instance per VM to be used for supporting + * multiple vGPUs per VM. + * fbUsed [OUT] + * This parameter specifies FB usage in bytes + * eccState [OUT] + * This parameter specifies the ECC state of the virtual GPU. + * One of NVA081_CTRL_ECC_STATE_xxx values. + * bDriverLoaded [OUT] + * This parameter specifies whether driver is loaded on this particular vGPU. + * + */ +typedef struct NV2080_HOST_VGPU_DEVICE { + NvU32 gfid; + NV_DECLARE_ALIGNED(NvU64 vgpuPciId, 8); + NvU32 vgpuDeviceInstanceId; + NvU32 accountingPid; + NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); + NvU32 encoderCapacity; + NvU32 eccState; + NvBool bDriverLoaded; +} NV2080_HOST_VGPU_DEVICE; + +/* + * NV2080_VGPU_GUEST + * + * This structure represents a vGPU guest + * + */ +typedef struct NV2080_VGPU_GUEST { + NV2080_GUEST_VM_INFO guestVmInfo; + NV_DECLARE_ALIGNED(NV2080_HOST_VGPU_DEVICE vgpuDevice, 8); +} NV2080_VGPU_GUEST; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU + * + * This command enumerates list of vGPU guest instances per pGpu + * + * numVgpu [OUT] + * This parameter specifies the number of virtual GPUs created on this physical GPU + * + * vgpuGuest [OUT] + * This parameter specifies an array containing guest vgpu's information for + * all vGPUs created on this physical GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU (0x20804004) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS { + NvU32 numVgpu; + NV_DECLARE_ALIGNED(NV2080_VGPU_GUEST vgpuGuest[NVA081_MAX_VGPU_PER_PGPU], 8); +} NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO + * + * This command is used clear guest vm info. It should be used when + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE + * is called with NVA081_NOTIFIERS_EVENT_VGPU_GUEST_DESTROYED state. + * + * gfid [IN] + * This parameter specifies the gfid of vGPU assigned to VM. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO (0x20804005) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS { + NvU32 gfid; +} NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE + * + * This command is used to get the FB usage of all vGPU instances running on a GPU. + * + * vgpuCount [OUT] + * This field specifies the number of vGPU devices for which FB usage is returned. + * vgpuFbUsage [OUT] + * This is an array of type NV2080_VGPU_FB_USAGE, which contains a list of vGPU gfid + * and their corresponding FB usage in bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE (0x20804006) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID" */ + +typedef struct NV2080_VGPU_FB_USAGE { + NvU32 gfid; + NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); +} NV2080_VGPU_FB_USAGE; + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS { + NvU32 vgpuCount; + NV_DECLARE_ALIGNED(NV2080_VGPU_FB_USAGE vgpuFbUsage[NVA081_MAX_VGPU_PER_PGPU], 8); +} NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY + * + * This command is used to set vGPU instance's (represented by gfid) encoder Capacity. + * + * gfid [IN] + * This parameter specifies the gfid of vGPU assigned to VM. + * encoderCapacity [IN] + * Encoder capacity value from 0 to 100. Value of 0x00 indicates encoder performance + * may be minimal for this GPU and software should fall back to CPU-based encode. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY (0x20804007) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS { + NvU32 gfid; + NvU32 encoderCapacity; +} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP + * + * This command is used to cleanup all the GSP VGPU plugin task allocated resources after its shutdown. + * Can be called only with SR-IOV and with VGPU_GSP_PLUGIN_OFFLOAD feature. + * + * gfid [IN] + * This parameter specifies the gfid of vGPU assigned to VM. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP (0x20804008) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS { + NvU32 gfid; +} NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS; + +#define NV2080_CTRL_MAX_NVU32_TO_CONVERTED_STR_LEN 8 +#define NV2080_CTRL_MAX_GPC_COUNT 32 + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING + * + * Reroutes kvgpumgrGetPgpuFSEncoding to vgpuMgrGetPgpuFSEncoding. + * + * pgpuString [OUT] + * Resulting PGPU string + * pgpuStringSize + * PGPU string size + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING (0x20804009) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS { + NvU8 pgpuString[NVA081_PGPU_METADATA_STRING_SIZE]; + NvU32 pgpuStringSize; +} NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT + * + * Reroutes kvgpumgrCheckPgpuMigrationSupport to vgpuMgrCheckPgpuMigrationSupport. + * + * bIsMigrationSupported [OUT] + * Resulting status of the migration support + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT (0x2080400a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS { + NvBool bIsMigrationSupported; +} NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG + * + * Sets vgpu manager parameters. This control is used after GSP initialization. + * + * bSupportHeterogeneousTimeSlicedVgpuTypes [IN] + * Enable/disable heterogeneous time-sliced vgpu types + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG (0x2080400b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS { + NvBool bSupportHeterogeneousTimeSlicedVgpuTypes; +} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT + * + * Reroutes NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_FREE_STATES to GSP RM to enable + * kernel clients to utilize NVA082_CTRL_CMD_HOST_VGPU_DEVICE_FREE_STATES. + * + * gfid [IN] + * This parameter specifies the gfid of vGPU assigned to VM. + * flags [IN] + * Specifies what component of HostVgpuDevice to free. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_FREE_STATES (0x2080400c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS { + NvU32 gfid; + NvU32 flags; +} NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_FRAME_RATE_LIMITER_STATUS + * + * Returns information whether frame rate limiter is disabled. + * + * bFlrDisabled [OUT] + * True, if frame rate limiter is disabled. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_FRAME_RATE_LIMITER_STATUS (0x2080400d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS { + NvBool bFlrDisabled; +} NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE + * + * This command will set heterogenous mode in GSP RM + * + * bHeterogeneousMode + * Mode of heterogeneous + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE (0x2080400e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS { + NvBool bHeterogeneousMode; +} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE + * + * This command will set MIG timeslice mode in GSP RM + * + * bMigTimeslicingModeEnabled + * Mode of MIG timeslice + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE (0x2080400f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS { + NvBool bMigTimeslicingModeEnabled; +} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS; + + + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_POWER_STATE + * + * This command is used to share the Power State from KMD side to GSP-RM. + * + * state + * This parameter contains Power State Information. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_POWER_STATE (0x20804010) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_POWER_STATE_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_POWER_STATE_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_POWER_STATE_PARAMS { + NvU32 state; +} NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_POWER_STATE_PARAMS; + +/* _ctrl2080vgpumgrinternal_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080volt.h b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080volt.h new file mode 100644 index 0000000..a136214 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl2080/ctrl2080volt.h @@ -0,0 +1,38 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080volt.finn +// + + + +/* _ctrl2080volt_h_ */ + +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "ctrl/ctrl2080/ctrl2080boardobj.h" +#include "ctrl/ctrl2080/ctrl2080pmumon.h" + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl208f.h b/userspace/sdks/nv570/inc/ctrl/ctrl208f.h new file mode 100644 index 0000000..aa72059 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl208f.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f.finn +// + + + + +#include "ctrl/ctrlxxxx.h" +#include "ctrl208f/ctrl208fpower.h" +#include "ctrl208f/ctrl208ffifo.h" +#include "ctrl208f/ctrl208ffb.h" +#include "ctrl208f/ctrl208ffbio.h" + + +#include "ctrl208f/ctrl208fbif.h" +#include "ctrl208f/ctrl208fbus.h" +#include "ctrl208f/ctrl208fgpu.h" +#include "ctrl208f/ctrl208fgr.h" +#include "ctrl208f/ctrl208fpmgr.h" +#include "ctrl208f/ctrl208fdma.h" +#include "ctrl208f/ctrl208fmmu.h" +#include "ctrl208f/ctrl208fucodeinstrumentation.h" +#include "ctrl208f/ctrl208fnvlink.h" +#include "ctrl208f/ctrl208fpmu.h" +#include "ctrl208f/ctrl208fsec2.h" + + +#include "ctrl208f/ctrl208fce.h" diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fbase.h b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fbase.h new file mode 100644 index 0000000..934c6d0 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fbase.h @@ -0,0 +1,69 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fbase.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV20_SUBDEVICE_DIAG: diagnostic class control commands and parameters */ + +#define NV208F_CTRL_CMD(cat, idx) NVXXXX_CTRL_CMD(0x208F, NV208F_CTRL_##cat, idx) + +/* Subdevice diag command categories (6 bits) */ +#define NV208F_CTRL_RESERVED (0x00) +#define NV208F_CTRL_POWER (0x01) +#define NV208F_CTRL_FIFO (0x04) +#define NV208F_CTRL_FB (0x05) +#define NV208F_CTRL_MC (0x06) +#define NV208F_CTRL_BIF (0x07) +#define NV208F_CTRL_FBIO (0x0A) +#define NV208F_CTRL_MMU (0x0B) +#define NV208F_CTRL_PMU (0x0C) +#define NV208F_CTRL_GPU (0x11) +#define NV208F_CTRL_GR (0x12) +#define NV208F_CTRL_PMGR (0x13) +#define NV208F_CTRL_DMA (0x14) +#define NV208F_CTRL_GSPMSGTIMING (0x17) +#define NV208F_CTRL_BUS (0x18) +#define NV208F_CTRL_UCODE_INSTRUMENTATION (0x19) +#define NV208F_CTRL_NVLINK (0x1A) +#define NV208F_CTRL_PROFILING (0x1B) +#define NV208F_CTRL_CE (0x1C) +#define NV208F_CTRL_SEC2 (0x1D) + +/* + * NV208F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV208F_CTRL_CMD_NULL (0x208f0000) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrl208fbase_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fbif.h b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fbif.h new file mode 100644 index 0000000..6054bf5 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fbif.h @@ -0,0 +1,194 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fbif.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* +* NV208F_CTRL_CMD_BIF_PBI_WRITE_COMMAND +* +* Control command to send a write command to the Post Box Interface +* +* Parameters: +* +*cmdFuncId +* this specifies the function that needs to be performed on pbi +*data +* the data to be set in the data in register +* status +* this corresponds to pbi status register +* sysNotify +* this corresponds to system notify event, i.e. whether system +* needs to be notified of command completion +* drvNotify +* this corresponds to driver notify event, i.e. whether driver +* needs to be notified of command completion +* +* For the possible values of the above parameters refer rmpbicmdif.h +*/ +#define NV208F_CTRL_CMD_BIF_PBI_WRITE_COMMAND (0x208f0701) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_PBI_WRITE_COMMAND_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_BIF_PBI_WRITE_COMMAND_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV208F_CTRL_BIF_PBI_WRITE_COMMAND_PARAMS { + NvU8 cmdFuncId; + NvU32 data; + NvU8 status; + NvBool sysNotify; + NvBool drvNotify; +} NV208F_CTRL_BIF_PBI_WRITE_COMMAND_PARAMS; + +/* +* NV208F_CTRL_CMD_BIF_CONFIG_REG_READ +* This command is used to read any of the PBI registers in the config space +* +* Parameters: +* +* RegIndex +* Defines the index of the PBI register +* data +* Data that is read +*/ +#define NV208F_CTRL_CMD_BIF_CONFIG_REG_READ (0x208f0702) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_CONFIG_REG_READ_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_BIF_CONFIG_REG_READ_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV208F_CTRL_BIF_CONFIG_REG_READ_PARAMS { + NvU8 RegIndex; + NvU32 data; +} NV208F_CTRL_BIF_CONFIG_REG_READ_PARAMS; + +/* +* NV208F_CTRL_CMD_BIF_CONFIG_REG_WRITE +* This command is used to write any of the PBI registers in the config space +* +* Parameters: +* +* RegIndex +* Defines the index of the PBI register +* data +* Data that is to be written +*/ +#define NV208F_CTRL_CMD_BIF_CONFIG_REG_WRITE (0x208f0703) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_CONFIG_REG_WRITE_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_BIF_CONFIG_REG_WRITE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV208F_CTRL_BIF_CONFIG_REG_WRITE_PARAMS { + NvU8 RegIndex; + NvU32 data; +} NV208F_CTRL_BIF_CONFIG_REG_WRITE_PARAMS; + +/* +* NV208F_CTRL_CMD_BIF_INFO +* This command is used to read a bif property +* +* Parameters: +* +* index +* Defines the index of the property to read +* data +* Data that is read +*/ +#define NV208F_CTRL_CMD_BIF_INFO (0x208f0704) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_INFO_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_BIF_INFO_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV208F_CTRL_BIF_INFO_PARAMS { + NvU32 index; + NvU32 data; +} NV208F_CTRL_BIF_INFO_PARAMS; + +/* valid bif info index values */ +#define NV208F_CTRL_BIF_INFO_INDEX_L0S_ENABLED (0x00000000) +#define NV208F_CTRL_BIF_INFO_INDEX_L1_ENABLED (0x00000001) + +/* + * NV208F_CTRL_CMD_BIF_ECC_INJECT_ERROR + * + * This ctrl call injects PCI-E XPL-EP ECC errors. Please see the confluence + * page "ECC" for more information on ECC and ECC injection: + * + * Parameters: + * + * errorUnit + * Specifies the HW unit where the injection will occur. + * + * errorType + * Specifies whether the injected error will be correctable or uncorrectable. + * Correctable errors have no effect on running programs while uncorrectable + * errors will cause all channels to be torn down. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_BIF_ECC_INJECT_ERROR (0x208f0705) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */ + + + +#define NV208F_CTRL_BIF_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV208F_CTRL_BIF_ECC_INJECT_ERROR_PARAMS { + NvU8 errorType; + NvU8 errorUnit; +} NV208F_CTRL_BIF_ECC_INJECT_ERROR_PARAMS; + +/* + * NV208F_CTRL_CMD_BIF_ECC_INJECTION_SUPPORTED + * + * Reports if error injection is supported for XPL-EP + * + * bCorrectableSupported [out]: + * Boolean value that shows if correcatable errors can be injected. + * + * bUncorrectableSupported [out]: + * Boolean value that shows if uncorrecatable errors can be injected. + * + * Return values: + * NV_OK on success + * NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled. + * NV_ERR_NOT_SUPPORTED otherwise + * + * + */ +#define NV208F_CTRL_CMD_BIF_ECC_INJECTION_SUPPORTED (0x208f0706) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_BIF_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV208F_CTRL_BIF_ECC_INJECTION_SUPPORTED_PARAMS { + NvU8 errorUnit; + NvBool bCorrectableSupported; + NvBool bUncorrectableSupported; +} NV208F_CTRL_BIF_ECC_INJECTION_SUPPORTED_PARAMS; + +/* _ctrl208fbif_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fbus.h b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fbus.h new file mode 100644 index 0000000..0845699 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fbus.h @@ -0,0 +1,113 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fbus.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* + * NV208F_CTRL_CMD_BUS_IS_BAR1_VIRTUAL + * + * This command checks whether or not BAR1 is in virtual mode. + * This API is intended for internal testing only. + * + * bIsVirtual + * Whether or not Bar1 is in virtual mode. + */ +#define NV208F_CTRL_CMD_BUS_IS_BAR1_VIRTUAL (0x208f1801) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BUS_INTERFACE_ID << 8) | NV208F_CTRL_BUS_IS_BAR1_VIRTUAL_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_BUS_IS_BAR1_VIRTUAL_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV208F_CTRL_BUS_IS_BAR1_VIRTUAL_PARAMS { + NvBool bIsVirtual; +} NV208F_CTRL_BUS_IS_BAR1_VIRTUAL_PARAMS; + +/* + * NV208F_CTRL_CMD_BUS_ECC_INJECT_ERROR + * + * This ctrl call injects BUS ECC errors. Please see the confluence + * page "ECC" for more information on ECC and ECC injection: + * + * Parameters: + * + * location + * Specifies the BUS HW unit where the injection will occur. + * + * errorType + * Specifies whether the injected error will be correctable or uncorrectable. + * Correctable errors have no effect on running programs while uncorrectable + * errors will cause all channels to be torn down. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_BUS_ECC_INJECT_ERROR (0x208f1802) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BUS_INTERFACE_ID << 8) | NV208F_CTRL_BUS_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */ + + + +#define NV208F_CTRL_BUS_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV208F_CTRL_BUS_ECC_INJECT_ERROR_PARAMS { + NvU8 errorType; + NvU8 errorUnit; +} NV208F_CTRL_BUS_ECC_INJECT_ERROR_PARAMS; + +/* + * NV208F_CTRL_CMD_BUS_ECC_INJECTION_SUPPORTED + * + * Reports if error injection is supported for BUS units + * + * bCorrectableSupported [out]: + * Boolean value that shows if correcatable errors can be injected. + * + * bUncorrectableSupported [out]: + * Boolean value that shows if uncorrecatable errors can be injected. + * + * Return values: + * NV_OK on success + * NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled. + * NV_ERR_NOT_SUPPORTED otherwise + * + * + */ +#define NV208F_CTRL_CMD_BUS_ECC_INJECTION_SUPPORTED (0x208f1803) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BUS_INTERFACE_ID << 8) | NV208F_CTRL_BUS_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_BUS_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV208F_CTRL_BUS_ECC_INJECTION_SUPPORTED_PARAMS { + NvU8 errorUnit; + NvBool bCorrectableSupported; + NvBool bUncorrectableSupported; +} NV208F_CTRL_BUS_ECC_INJECTION_SUPPORTED_PARAMS; + +/* _ctrl208fbus_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fce.h b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fce.h new file mode 100644 index 0000000..99ebdd4 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fce.h @@ -0,0 +1,178 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fce.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* + * NV208F_CTRL_CMD_CE_GET_NUM_SHIM_INSTANCES + * + * This command returns the number of CE shims on the GPU. + * + * [out] numShimInstances + * Returns the number of CE shims on the GPU. + */ +#define NV208F_CTRL_CMD_CE_GET_NUM_SHIM_INSTANCES (0x208f1c01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_CE_INTERFACE_ID << 8) | NV208F_CTRL_CE_GET_NUM_SHIM_INSTANCES_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_CE_GET_NUM_SHIM_INSTANCES_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV208F_CTRL_CE_GET_NUM_SHIM_INSTANCES_PARAMS { + NvU32 numShimInstances; +} NV208F_CTRL_CE_GET_NUM_SHIM_INSTANCES_PARAMS; + +/* + * NV208F_CTRL_CMD_CE_GET_MAX_NUM_PCES_PER_SHIM + * + * This command returns the maximum number of PCEs per CE shim on the GPU. + * + * [out] numPces + * Returns the maximum number of PCEs on the GPU. + */ +#define NV208F_CTRL_CMD_CE_GET_MAX_NUM_PCES_PER_SHIM (0x208f1c02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_CE_INTERFACE_ID << 8) | NV208F_CTRL_CE_GET_MAX_NUM_PCES_PER_SHIM_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_CE_GET_MAX_NUM_PCES_PER_SHIM_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV208F_CTRL_CE_GET_MAX_NUM_PCES_PER_SHIM_PARAMS { + NvU32 numPces; +} NV208F_CTRL_CE_GET_MAX_NUM_PCES_PER_SHIM_PARAMS; + +/* + * NV208F_CTRL_CMD_CE_GET_AVAILABLE_LCE_MASK + * + * This command gets the mask of LCEs that are available for the specified CE shim. + * + * [in] shimInstance + * Specify which CE shim instance to operate on. + * [out] lceMask + * Returns a 32-bit mask of which LCEs in the given shim are available. + */ +#define NV208F_CTRL_CMD_CE_GET_AVAILABLE_LCE_MASK (0x208f1c03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_CE_INTERFACE_ID << 8) | NV208F_CTRL_CE_GET_AVAILABLE_LCE_MASK_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_CE_GET_AVAILABLE_LCE_MASK_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV208F_CTRL_CE_GET_AVAILABLE_LCE_MASK_PARAMS { + NvU32 shimInstance; + NvU32 lceMask; +} NV208F_CTRL_CE_GET_AVAILABLE_LCE_MASK_PARAMS; + +/* + * NV208F_CTRL_CMD_CE_GET_FLOORSWEPT_PCE_MASK + * + * This command gets the mask of floorswept PCEs for the specified CE shim. + * + * [in] shimInstance + * Specify which CE shim instance to operate on. + * [out] pceMask + * Returns a 32-bit mask of which PCEs in the given shim are available. + */ +#define NV208F_CTRL_CMD_CE_GET_FLOORSWEPT_PCE_MASK (0x208f1c04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_CE_INTERFACE_ID << 8) | NV208F_CTRL_CE_GET_FLOORSWEPT_PCE_MASK_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_CE_GET_FLOORSWEPT_PCE_MASK_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV208F_CTRL_CE_GET_FLOORSWEPT_PCE_MASK_PARAMS { + NvU32 shimInstance; + NvU32 pceMask; +} NV208F_CTRL_CE_GET_FLOORSWEPT_PCE_MASK_PARAMS; + +/* + * NV208F_CTRL_CMD_CE_ECC_INJECTION_SUPPORTED + * + * Reports if error injection is supported for the CE + * + * bCorrectableSupported [out]: + * Boolean value that shows if correcatable errors can be injected. + * bUncorrectableSupported [out]: + * Boolean value that shows if uncorrecatable errors can be injected. + * + * Return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +#define NV208F_CTRL_CMD_CE_ECC_INJECTION_SUPPORTED (0x208f1c05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_CE_INTERFACE_ID << 8) | NV208F_CTRL_CE_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_CE_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV208F_CTRL_CE_ECC_INJECTION_SUPPORTED_PARAMS { + NvBool bCorrectableSupported; + NvBool bUncorrectableSupported; +} NV208F_CTRL_CE_ECC_INJECTION_SUPPORTED_PARAMS; + +/* + * NV208F_CTRL_CMD_CE_ECC_ENABLE_ERROR_INJECTION + * + * This ctrl call enables CE ECC error injection for a given group and PCE. + * A copy using the target PCE is required to inject the error. + * + * Parameters: + * + * dietletLoc [in] + * Specifies the CE dielet location where the injection will occur. Specify using NV2080_ECC_LOCATION_INFO_DIELET_*. + * pceIdx [in] + * Specifies the PCE index where the injection will occur. + * errorType [in] + * Specifies whether the injected error will be correctable or uncorrectable. + * Correctable errors have no effect on running programs while uncorrectable + * errors will cause all channels to be torn down. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +#define NV208F_CTRL_CMD_CE_ECC_ENABLE_ERROR_INJECTION (0x208f1c06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_CE_INTERFACE_ID << 8) | NV208F_CTRL_CE_ECC_ENABLE_ERROR_INJECTION_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_CE_ECC_ENABLE_ERROR_INJECTION_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV208F_CTRL_CE_ECC_ENABLE_ERROR_INJECTION_PARAMS { + NvU32 dietletLoc; + NvU32 pceIdx; + NvU8 errorType; +} NV208F_CTRL_CE_ECC_ENABLE_ERROR_INJECTION_PARAMS; + + + +/* + * NV208F_CTRL_CMD_CE_ECC_DISABLE_ERROR_INJECTION + * + * This ctrl call disables CE ECC error injection for all groups and PCEs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +#define NV208F_CTRL_CMD_CE_ECC_DISABLE_ERROR_INJECTION (0x208f1c07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_CE_INTERFACE_ID << 8) | 0x7" */ + +/* _ctrl208fce_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fdma.h b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fdma.h new file mode 100644 index 0000000..be4d8e4 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fdma.h @@ -0,0 +1,92 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fdma.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* + * NV208F_CTRL_CMD_DMA_IS_SUPPORTED_SPARSE_VIRTUAL + * + * This command checks whether or not "sparse" virtual address ranges are + * supported for a given chip. This API is intended for debug-use only. + * + * bIsSupported + * Whether or not "sparse" virtual address ranges are supported. + */ +#define NV208F_CTRL_CMD_DMA_IS_SUPPORTED_SPARSE_VIRTUAL (0x208f1401) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_DMA_INTERFACE_ID << 8) | NV208F_CTRL_DMA_IS_SUPPORTED_SPARSE_VIRTUAL_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_DMA_IS_SUPPORTED_SPARSE_VIRTUAL_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV208F_CTRL_DMA_IS_SUPPORTED_SPARSE_VIRTUAL_PARAMS { + NvBool bIsSupported; +} NV208F_CTRL_DMA_IS_SUPPORTED_SPARSE_VIRTUAL_PARAMS; + +/* + * NV208F_CTRL_CMD_DMA_GET_VAS_BLOCK_DETAILS + * + * This command retrieves various details of the virtual address space block + * allocated from the virtual address space heap for the given virtual address. + * + * virtualAddress + * Virtual address to get information about. + * + * beginAddress + * Start address of the corresponding virtual address space block. + * + * endAddress + * End address (inclusive) of the corresponding virtual address space + * block. + * + * alignedAddress + * Aligned address of the corresponding virtual address space block. + * + * pageSize + * Page size of the virtual address space block. + * + * hVASpace + * Handle to an allocated VA space. If 0, it is assumed that the device's + * VA space should be used. + */ +#define NV208F_CTRL_CMD_DMA_GET_VAS_BLOCK_DETAILS (0x208f1402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_DMA_INTERFACE_ID << 8) | NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 virtualAddress, 8); + NV_DECLARE_ALIGNED(NvU64 beginAddress, 8); + NV_DECLARE_ALIGNED(NvU64 endAddress, 8); + NV_DECLARE_ALIGNED(NvU64 alignedAddress, 8); + NvU32 pageSize; + NvHandle hVASpace; +} NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS; + +/* _ctrl208fdma_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208ffb.h b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208ffb.h new file mode 100644 index 0000000..2add87a --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208ffb.h @@ -0,0 +1,842 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208ffb.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* + * NV208F_CTRL_CMD_FB_GET_INFO + * + * This command returns fb engine information for the associated GPU. + * The client specifies what information to query through 'index' param. + * On success, the information is stored in the 'data' param. + * + * index + * Specify what information to query. Please see below for valid values of + * indexes for this command. + * data + * On success, this param will hold the data that the client queried for. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_FB_GET_INFO (0x208f0501) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV208F_CTRL_FB_GET_INFO_PARAMS { + NvU32 index; + NV_DECLARE_ALIGNED(NvU64 data, 8); +} NV208F_CTRL_FB_GET_INFO_PARAMS; + +/* valid fb info index values */ +#define NV208F_CTRL_FB_INFO_INDEX_FREE_CONTIG_COMPRESSION_SIZE (0x00000001) + +#define NV208F_CTRL_FB_INFO_INDEX_MAX NV208F_CTRL_FB_INFO_INDEX_FREE_CONTIG_COMPRESSION_SIZE + +/* + * NV208F_CTRL_CMD_FB_GET_ZBC_REFCOUNT + * + * This command gets the ZBC reference count associated with a given + * compression tag address. It is not supported on GPUs which support class + * GF100_ZBC_CLEAR as it is specific to a different hardware implementation. + * + * compTagAddress + * The input parameter indicating the compression tag address for which the + * associated ZBC refcount should be looked up. + * zbcRefCount + * An array of reference counts for the ZBC clear values associated with + * compTagAddress. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_FB_GET_ZBC_REFCOUNT (0x208f0505) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | 0x5" */ // Deprecated, removed form RM + +#define NV208F_CTRL_FB_GET_ZBC_REFCOUNT_MAX_REFCOUNTS 2 +typedef struct NV208F_CTRL_FB_GET_ZBC_REFCOUNT_PARAMS { + NvU32 compTagAddress; + NvU32 zbcRefCount[NV208F_CTRL_FB_GET_ZBC_REFCOUNT_MAX_REFCOUNTS]; +} NV208F_CTRL_FB_GET_ZBC_REFCOUNT_PARAMS; + +/* + * NV208F_CTRL_CMD_FB_CTRL_GPU_CACHE + * + * This command controls the state of a cache which all GPU memory accesses go + * through. If supported, it allows changing of the power state and the write + * mode. This is only supported when NV_VERIF_FEATURES is defined. An error + * will be returned if the requested combination of settings is not possible. + * + * writeMode + * Specifies the write mode of the cache. Possible values are defined in + * NV208F_CTRL_FB_CTRL_GPU_CACHE_WRITE_MODE. Passing _DEFAULT means to + * maintain the current write mode. It is illegal to change the write mode + * while the cache is disabled or in the same call as a request to disable + * it. + * powerState + * Specifies the power state of the cache. Possible values are defined in + * NV208F_CTRL_FB_CTRL_GPU_CACHE_POWER_STATE. Passing _DEFAULT means + * to maintain the current power state. + * rcmState + * Specifies the reduced cache mode of the cache. Possible values are + * defined in NV208F_CTRL_FB_CTRL_GPU_CACHE_RCM_STATE. Passing _DEFAULT + * means to maintain the current RCM state. + * vgaCacheMode + * Specifies whether or not to enable VGA out-of-cache mode. Possible + * values are defined in NV208F_CTRL_FB_CTRL_GPU_CACHE_VGA_MODE. Passing + * _DEFAULT means to maintain the current VGA caching mode. + * cacheReset + * Triggers a hardware reset of the cache. Possible values are defined in + * NV208F_CTRL_FB_CTRL_GPU_CACHE_CACHE_RESET. Passing _DEFAULT does + * nothing while passing _RESET clears all data in the cache. + * flags + * Contains flags to control the details of how transitions should be + * handled. Possible values are defined in + * NV208F_CTRL_FB_CTRL_GPU_CACHE_FLAGS. Passing _DEFAULT for any of + * the fields means to use the defaults specified by the Resource Manager. + * Note not all options are available for all transitions. Flags that are + * set but not applicable will be silently ignored. + * bypassMode + * (Fermi only) Specifies the bypass mode of the L2 cache. Normal GPU + * operation is _DISABLE. For TEST ONLY, setting _ENABLE enables a debug + * mode where all transactions miss in L2 and no writes are combined, + * essentially disabling the caching feature of the L2 cache. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV208F_CTRL_CMD_FB_CTRL_GPU_CACHE (0x208f0506) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_CTRL_GPU_CACHE_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV208F_CTRL_FB_CTRL_GPU_CACHE_PARAMS { + NvU32 writeMode; + NvU32 powerState; + NvU32 rcmState; + NvU32 vgaCacheMode; + NvU32 cacheReset; + NvU32 flags; + NvU32 bypassMode; +} NV208F_CTRL_FB_CTRL_GPU_CACHE_PARAMS; + +/* valid values for writeMode */ +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_WRITE_MODE_DEFAULT (0x00000000) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_WRITE_MODE_WRITETHROUGH (0x00000001) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_WRITE_MODE_WRITEBACK (0x00000002) + +/* valid values for powerState */ +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_POWER_STATE_DEFAULT (0x00000000) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_POWER_STATE_ENABLED (0x00000001) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_POWER_STATE_DISABLED (0x00000002) + +/* valid values for rcmState */ +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_RCM_STATE_DEFAULT (0x00000000) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_RCM_STATE_FULL (0x00000001) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_RCM_STATE_REDUCED (0x00000002) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_RCM_STATE_ZERO_CACHE (0x00000003) + +/* valid values for vgaCacheMode */ +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_VGA_MODE_DEFAULT (0x00000000) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_VGA_MODE_ENABLED (0x00000001) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_VGA_MODE_DISABLED (0x00000002) + +/* valid values for cacheReset */ +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_CACHE_RESET_DEFAULT (0x00000000) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_CACHE_RESET_RESET (0x00000001) + +/* valid fields and values for flags */ +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_FLAGS_MODE 1:0 +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_FLAGS_MODE_DEFAULT (0x00000000) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_FLAGS_MODE_RM (0x00000001) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_FLAGS_MODE_PMU (0x00000002) + +/* valid values for bypassMode */ +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_BYPASS_MODE_DEFAULT (0x00000000) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_BYPASS_MODE_DISABLED (0x00000001) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_BYPASS_MODE_ENABLED (0x00000002) + + + +/* + * NV208F_CTRL_CMD_FB_SET_STATE + * + * This command is used to put fb engine in a state requested by the caller. + * + * state + * This parameter specifies the desired engine state: + * NV208F_CTRL_FB_SET_STATE_STOPPED + * This value stops/halts the fb engine. + * NV208F_CTRL_FB_SET_STATE_RESTART + * This value restarts fb from a stopped state. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_FB_SET_STATE (0x208f0508) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_SET_STATE_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_SET_STATE_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV208F_CTRL_FB_SET_STATE_PARAMS { + NvU32 state; +} NV208F_CTRL_FB_SET_STATE_PARAMS; + +/* valid values for state */ +#define NV208F_CTRL_FB_SET_STATE_STOPPED (0x00000000) +#define NV208F_CTRL_FB_SET_STATE_RESTART (0x00000001) + +/* + * NV208F_CTRL_CMD_GPU_ECC_SCRUB_DIAG + * + * This command reads all the settings internal to scrubbing (both asynchronous + * and synchronous. + * + * Currently implemented: FB offset scrubber has completed, FB offset that scrubber + * is completing to, whether or not asynchronous scrubbing is enabled. + * + * fbOffsetCompleted + * This is the offset into FB that the scrubber has completed up to at the + * time this function is invoked. Note that the scrubber is top-down. Therefore + * the memory that remains unscrubbed is from 0x0 to fbOffsetCompleted. + * + * fbEndOffset + * This is the offset of the base of the last block that ECC asynchronous + * scrubber has been tasked to scrub. + * + * bAsyncScru bDisabled + * This is NV_TRUE if asynchronous scrubbing is disabled and NV_FALSE if + * asynchronous scrubbing is enabled. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV208F_CTRL_CMD_FB_ECC_SCRUB_DIAG (0x208f0509) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_CMD_FB_ECC_SCRUB_DIAG_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_CMD_FB_ECC_SCRUB_DIAG_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV208F_CTRL_CMD_FB_ECC_SCRUB_DIAG_PARAMS { + NV_DECLARE_ALIGNED(NvU64 fbOffsetCompleted, 8); + NV_DECLARE_ALIGNED(NvU64 fbEndOffset, 8); + NvBool bAsyncScrubDisabled; +} NV208F_CTRL_CMD_FB_ECC_SCRUB_DIAG_PARAMS; + +/* + * NV208F_CTRL_CMD_GPU_ECC_ASYNCH_SCRUB_REGION + * + * This command launches the ECC scrubber in asynchronous mode. The scrubber, as + * in normal operation, will continue to operate until all of FB (excluding + * dedicated system memory) has been scrubbed. Like usual operation, scrubbing is + * only done on silicon. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV208F_CTRL_CMD_FB_ECC_ASYNC_SCRUB_REGION (0x208f050a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_CMD_FB_ECC_ASYNC_SCRUB_REGION_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_CMD_FB_ECC_ASYNC_SCRUB_REGION_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV208F_CTRL_CMD_FB_ECC_ASYNC_SCRUB_REGION_PARAMS { + NV_DECLARE_ALIGNED(NvU64 startBlock, 8); + NV_DECLARE_ALIGNED(NvU64 endBlock, 8); +} NV208F_CTRL_CMD_FB_ECC_ASYNC_SCRUB_REGION_PARAMS; + +/* + * NV208F_CTRL_CMD_GPU_ECC_ERROR_INFO + * This is a structure that is defined here for diag/debug purposes in mods. + * It is used to return the error information as part of the callback to + * kernel clients registering for SBE/DBE callbacks. + */ + +typedef struct NV208F_CTRL_CMD_FB_ECC_ERROR_INFO { + NvU32 row; + NvU32 bank; + NvU32 col; + NvU32 extBank; + NvU32 xbarAddress; + NV_DECLARE_ALIGNED(NvU64 physAddress, 8); +} NV208F_CTRL_CMD_FB_ECC_ERROR_INFO; + + +#define NV208F_CTRL_CMD_FB_ECC_GET_FORWARD_MAP_ADDRESS (0x208f050c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_CMD_FB_ECC_GET_FORWARD_MAP_ADDRESS_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_CMD_FB_ECC_GET_FORWARD_MAP_ADDRESS_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV208F_CTRL_CMD_FB_ECC_GET_FORWARD_MAP_ADDRESS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 pAddr, 8); + NvU32 row; + NvU32 bank; + NvU32 col; + NvU32 extBank; + NvU32 rank; + NvU32 pseudoChannel; + NvU32 physicalSublocation; + NvU32 physicalPartition; + NvU32 logicalSublocation; + NvU32 logicalPartition; + NvU32 writeKillPtr0; + NvU32 injectionAddr; + NvU32 injectionAddrExt; + NvU32 rbcAddress; + NvU32 rbcAddressExt; + NvU32 rbcAddressExt2; + NvU32 eccCol; +} NV208F_CTRL_CMD_FB_ECC_GET_FORWARD_MAP_ADDRESS_PARAMS; + +/* + * NV208F_CTRL_CMD_FB_ECC_SET_KILL_PTR + * + * This command sets the kill pointer for the specified DRAM address. If + * the kill pointer is set to NV208F_CTRL_FB_ERROR_TYPE_CORRECTABLE + * or NV208F_CTRL_FB_ERROR_TYPE_UNCORRECTABLE, accesses to the specified + * address will result in ECC errors until all kill pointers are unset + * using NV208F_CTRL_FB_ERROR_TYPE_NONE. + * + * Only one kill pointer can be set at a time. Setting a kill pointer will + * clear all currently set kill pointers and set the new kill pointer. + * Calling NV208F_CTRL_FB_ERROR_TYPE_NONE simply clears all currently set + * kill pointers. + * + * errorType + * The type of kill pointer to set. NV208F_CTRL_FB_ERROR_TYPE_CORRECTABLE + * will set a single kill pointer resulting in a correctable error. + * NV208F_CTRL_FB_ERROR_TYPE_UNCORRECTABLE will set both kill pointers + * resulting in an uncorrectable error. NV208F_CTRL_FB_ERROR_TYPE_NONE + * will clear all kill pointers, which stops the associated addresses + * from generating ECC errors if NV208F_CTRL_FB_ERROR_TYPE_CORRECTABLE + * or NV208F_CTRL_FB_ERROR_TYPE_UNCORRECTABLE was previously set. + * Only one kill pointer can be set at a time and setting a new + * kill pointer will clear the previous kill pointer. + * + * address + * The physical DRAM address to be targeted by the kill pointer + * + * bProdInjection + * Whether the kill pointer is set through the production injection flow or not + */ +#define NV208F_CTRL_CMD_FB_ECC_SET_KILL_PTR (0x208f050e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_ECC_SET_KILL_PTR_PARAMS_MESSAGE_ID" */ + +typedef enum NV208F_CTRL_FB_ERROR_TYPE { + NV208F_CTRL_FB_ERROR_TYPE_CORRECTABLE = 0, + NV208F_CTRL_FB_ERROR_TYPE_UNCORRECTABLE = 1, + NV208F_CTRL_FB_ERROR_TYPE_NONE = 2, +} NV208F_CTRL_FB_ERROR_TYPE; + +#define NV208F_CTRL_FB_ECC_SET_KILL_PTR_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV208F_CTRL_FB_ECC_SET_KILL_PTR_PARAMS { + NV208F_CTRL_FB_ERROR_TYPE errorType; + NV_DECLARE_ALIGNED(NvU64 address, 8); + NvBool bProdInjection; +} NV208F_CTRL_FB_ECC_SET_KILL_PTR_PARAMS; + + + +/* + * NV208F_CTRL_CMD_FB_INJECT_LTC_ECC_ERROR + * + * This API allows a client to inject ECC errors in the L2. + * + * ltc: + * The physical LTC number to inject the error into. + * slice: + * THe physical slice number within the LTC to inject the error into. + * locationMask + * LTC location subtype(s) where error is to be injected. (Valid on Ampere and later) + * errorType + * Type of error to inject + * NV208F_CTRL_FB_ERROR_TYPE_CORRECTABLE for SBE. + * NV208F_CTRL_FB_ERROR_TYPE_UNCORRECTABLE for DBE. + * + */ +#define NV208F_CTRL_CMD_FB_INJECT_LTC_ECC_ERROR (0x208f050f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_INJECT_LTC_ECC_ERROR_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_INJECT_LTC_ECC_ERROR_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NV208F_CTRL_FB_INJECT_LTC_ECC_ERROR_PARAMS { + NvU8 ltc; + NvU8 slice; + NvU8 locationMask; + NV208F_CTRL_FB_ERROR_TYPE errorType; +} NV208F_CTRL_FB_INJECT_LTC_ECC_ERROR_PARAMS; + +/* + * NV208F_CTRL_CMD_FB_ECC_INJECTION_SUPPORTED + * + * Reports if error injection is supported for a given HW unit + * + * location [in]: + * The ECC protected unit for which ECC injection support is being checked. + * The location type is defined by NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC. + * + * bCorrectableSupported [out]: + * Boolean value that shows if correcatable errors can be injected. + * + * bUncorrectableSupported [out]: + * Boolean value that shows if uncorrecatable errors can be injected. + * + * Return values: + * NV_OK on success + * NV_ERR_INVALID_ARGUMENT if the requested location is invalid. + * NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled. + * NV_ERR_NOT_SUPPORTED otherwise + * + * + */ +#define NV208F_CTRL_CMD_FB_ECC_INJECTION_SUPPORTED (0x208f0510) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_PARAMS { + NvU8 location; + NvBool bCorrectableSupported; + NvBool bUncorrectableSupported; +} NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_PARAMS; + +#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC 1:0 +#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC_LTC (0x00000000) +#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC_DRAM (0x00000001) +#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC_LRC (0x00000002) +#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC_SYSL2 (0x00000003) + +/* + * NV208F_CTRL_CMD_FB_ECC_SET_WRITE_KILL + * + * This command sets the write kill for the specified DRAM address. If set, + * writes to the specified address won't update the ECC checkbits. When unset, + * writes the specified address will update the ECC checkbits. + * + * Only one write kill register can be set at a time. Setting a write kill + * will clear all currently set write kills and set the new write kill. + * Calling this ctrl call with setWriteKill = false simply clears all currently + * set write kills. + * + * setWriteKill + * When true, the ECC checkbits for the specified address won't update on + * writes. When false, the ECC checkbits for the specified address will + * revert to normal behavior and update on all writes. + * + * address + * The physical DRAM address to be targeted by the write kill + * + * bProdInjection + * Whether the write kill is set through the production injection flow or not + */ +#define NV208F_CTRL_CMD_FB_ECC_SET_WRITE_KILL (0x208f0511) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS { + NvBool setWriteKill; + NvBool bProdInjection; + NV_DECLARE_ALIGNED(NvU64 address, 8); +} NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS; + +typedef struct NV208F_CTRL_FB_REMAPPING_RBC_ADDRESS_INFO { + NvU32 bank; + NvU32 stackId; + NvU32 row; + NvU32 partition; + NvU32 sublocation; + NvU32 pseudoChannel; +} NV208F_CTRL_FB_REMAPPING_RBC_ADDRESS_INFO; + +#define NV208F_CTRL_FB_REMAP_ADDRESS_TYPE_PHYSICAL 0x0 +#define NV208F_CTRL_FB_REMAP_ADDRESS_TYPE_RBC 0x1 + +/* + * NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO + * + * source + * The reason for retirement. Valid values for this parameter are + * from NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_* + * status + * Reason for row remapping failure. Valid values are: + * NV208F_CTRL_FB_REMAP_ROW_STATUS_OK + * No error + * NV208F_CTRL_FB_REMAP_ROW_STATUS_REMAPPING_PENDING + * The remapping is pending + * NV208F_CTRL_FB_REMAP_ROW_STATUS_TABLE_FULL + * Table full + * NV208F_CTRL_FB_REMAP_ROW_STATUS_ALREADY_REMAPPED + * Attempting to remap a reserved row + * NV208F_CTRL_FB_REMAP_ROW_STATUS_INTERNAL_ERROR + * Some other RM failure + * addressType + * Type of address passed. Valid values are: + * NV208F_CTRL_FB_REMAP_ADDRESS_TYPE_PHYSICAL + * The specified address is physical address. + * NV208F_CTRL_FB_REMAP_ADDRESS_TYPE_RBC + * The specified address is DRAM Row Bank Column address. + * address + * Union of physicalAddress and rbcAddress. Set the appropriate one based on the address type. + */ +typedef struct NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO { + NvU8 source; + NvU32 status; + NvU8 addressType; + union { + NV_DECLARE_ALIGNED(NvU64 physicalAddress, 8); + NV208F_CTRL_FB_REMAPPING_RBC_ADDRESS_INFO rbcAddress; + } address; +} NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO; + +/* valid values for status */ +#define NV208F_CTRL_FB_REMAP_STATUS_OK (0x00000000) +#define NV208F_CTRL_FB_REMAP_STATUS_REMAPPING_PENDING (0x00000001) +#define NV208F_CTRL_FB_REMAP_STATUS_TABLE_FULL (0x00000002) +#define NV208F_CTRL_FB_REMAP_STATUS_ALREADY_REMAPPED (0x00000003) +#define NV208F_CTRL_FB_REMAP_STATUS_INTERNAL_ERROR (0x00000004) +#define NV208F_CTRL_FB_REMAP_STATUS_NO_SPARE (0x00000005) +#define NV208F_CTRL_FB_REMAP_STATUS_INVALID_ARGUMENT (0x00000006) + +typedef NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO NV208F_CTRL_FB_REMAPPING_ROW_ADDRESS_INFO; + +#define NV208F_CTRL_FB_REMAP_ROW_ADDRESS_TYPE_PHYSICAL NV208F_CTRL_FB_REMAP_ADDRESS_TYPE_PHYSICAL +#define NV208F_CTRL_FB_REMAP_ROW_ADDRESS_TYPE_RBC NV208F_CTRL_FB_REMAP_ADDRESS_TYPE_RBC + +/* valid values for status */ +#define NV208F_CTRL_FB_REMAP_ROW_STATUS_OK NV208F_CTRL_FB_REMAP_STATUS_OK +#define NV208F_CTRL_FB_REMAP_ROW_STATUS_REMAPPING_PENDING NV208F_CTRL_FB_REMAP_STATUS_REMAPPING_PENDING +#define NV208F_CTRL_FB_REMAP_ROW_STATUS_TABLE_FULL NV208F_CTRL_FB_REMAP_STATUS_TABLE_FULL +#define NV208F_CTRL_FB_REMAP_ROW_STATUS_ALREADY_REMAPPED NV208F_CTRL_FB_REMAP_STATUS_ALREADY_REMAPPED +#define NV208F_CTRL_FB_REMAP_ROW_STATUS_INTERNAL_ERROR NV208F_CTRL_FB_REMAP_STATUS_INTERNAL_ERROR +#define NV208F_CTRL_FB_REMAP_ROW_STATUS_NO_SPARE NV208F_CTRL_FB_REMAP_STATUS_NO_SPARE +#define NV208F_CTRL_FB_REMAP_ROW_STATUS_INVALID_ARGUMENT NV208F_CTRL_FB_REMAP_STATUS_INVALID_ARGUMENT + +#define NV208F_CTRL_FB_REMAPPED_ROWS_MAX_ROWS (0x00000200) +/* + * NV208F_CTRL_CMD_FB_REMAP_ROW + * + * This command will write entries to Inforom. During init the entries will be + * read and used to remap a row. + * + * addressList + * This input parameter is an array of NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO + * structures containing information used for row remapping. Valid entries + * are adjacent + * validEntries + * This input parameter specifies the number of valid entries in the + * address array + * numEntriesAdded + * This output parameter specifies how many validEntries were successfully + * added to the Inforom + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_FB_REMAP_ROW (0x208f0512) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_REMAP_ROW_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_REMAP_ROW_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV208F_CTRL_FB_REMAP_ROW_PARAMS { + NV_DECLARE_ALIGNED(NV208F_CTRL_FB_REMAPPING_ROW_ADDRESS_INFO addressList[NV208F_CTRL_FB_REMAPPED_ROWS_MAX_ROWS], 8); + NvU32 validEntries; + NvU32 numEntriesAdded; +} NV208F_CTRL_FB_REMAP_ROW_PARAMS; + + +#define NV208F_CTRL_CMD_FB_REVERSE_MAP_RBC_ADDR_TO_PA (0x208f0513) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_REVERSE_MAP_RBC_ADDR_TO_PA_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_REVERSE_MAP_RBC_ADDR_TO_PA_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV208F_CTRL_FB_REVERSE_MAP_RBC_ADDR_TO_PA_PARAMS { + NV_DECLARE_ALIGNED(NvU64 address, 8); + NvU32 rbcAddress; + NvU32 rbcAddressExt; + NvU32 rbcAddressExt2; + NvU32 partition; + NvU32 sublocation; +} NV208F_CTRL_FB_REVERSE_MAP_RBC_ADDR_TO_PA_PARAMS; + +/** + * NV208F_CTRL_CMD_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF + * + * This command will convert a physical address when ECC is on to the physical + * address when ECC is off or vice versa + * + * @params[in] NvU64 inputAddress + * Input physical address + * + * @params[in] NvBool eccOn + * Whether or not input physical address is with ECC on or off + * + * @params[out] NvU64 outputAddress + * Output physical address + */ +#define NV208F_CTRL_CMD_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF (0x208f0514) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV208F_CTRL_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF_PARAMS { + NV_DECLARE_ALIGNED(NvU64 inputAddress, 8); + NvBool eccOn; + NV_DECLARE_ALIGNED(NvU64 outputAddress, 8); +} NV208F_CTRL_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF_PARAMS; + +/* + * NV208F_CTRL_CMD_FB_CLEAR_REMAPPED_ROWS + * + * This command clears remapping entries from the Inforom's row remapping table. + * + * sourceMask + * This is a bit mask of NV2080_CTRL_FB_REMAPPED_ROW_SOURCE. Rows + * remapped from the specified sources will be cleared/removed from the + * Inforom RRL object entries list. + * + * bForcePurge + * This flag will force purge the RRL object and associated data structures + * + * Possbile status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV208F_CTRL_CMD_FB_CLEAR_REMAPPED_ROWS (0x208f0515) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS { + NvU32 sourceMask; + NvBool bForcePurge; +} NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS; + + + +/* + * NV208F_CTRL_CMD_FB_INJECT_LRC_ECC_ERROR + * + * This API allows a client to inject ECC errors in the LRC. + * + * lrcc: + * The physical LRCC number to inject the error into. + * lrc: + * THe physical LRC number within the LRCC to inject the error into. + * locationMask + * LTC location subtype(s) where error is to be injected. (Valid on Ampere and later) + * errorType + * Type of error to inject + * NV208F_CTRL_FB_ERROR_TYPE_CORRECTABLE for SBE. + * NV208F_CTRL_FB_ERROR_TYPE_UNCORRECTABLE for DBE. + * + */ +#define NV208F_CTRL_CMD_FB_INJECT_LRC_ECC_ERROR (0x208f0516) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_INJECT_LRC_ECC_ERROR_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_INJECT_LRC_ECC_ERROR_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV208F_CTRL_FB_INJECT_LRC_ECC_ERROR_PARAMS { + NvU8 lrcc; + NvU8 lrc; + NvU8 locationMask; + NV208F_CTRL_FB_ERROR_TYPE errorType; +} NV208F_CTRL_FB_INJECT_LRC_ECC_ERROR_PARAMS; + +/* + * NV208F_CTRL_CMD_FB_INJECT_SYSLTC_ECC_ERROR + * + * This API allows a client to inject ECC errors in the SYSLTC. + * + * group: + * The physical group number to inject the error into. + * instance: + * The physical instance number within the group to inject the error into. + * instance: + * The physical slice number within the instance to inject the error into. + * locationMask + * SYSLTC location subtype(s) where error is to be injected. Same as LTC. + * errorType + * Type of error to inject + * NV208F_CTRL_FB_ERROR_TYPE_CORRECTABLE for SBE. + * NV208F_CTRL_FB_ERROR_TYPE_UNCORRECTABLE for DBE. + * + */ +#define NV208F_CTRL_CMD_FB_INJECT_SYSLTC_ECC_ERROR (0x208f0517) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_INJECT_SYSLTC_ECC_ERROR_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_INJECT_SYSLTC_ECC_ERROR_PARAMS_MESSAGE_ID (0x17U) + +typedef struct NV208F_CTRL_FB_INJECT_SYSLTC_ECC_ERROR_PARAMS { + NvU8 group; + NvU8 instance; + NvU8 slice; + NvU8 locationMask; + NV208F_CTRL_FB_ERROR_TYPE errorType; +} NV208F_CTRL_FB_INJECT_SYSLTC_ECC_ERROR_PARAMS; + +/* + * NV208F_CTRL_CMD_FB_GET_FBPA_PAC_MASKS + * + * This API returns the PAC mask for an FBPA. The format is an array where the + * index is the physical FBPA value and the value at the index is the channel + * mask at the corresponding FBPA. At this time there can only be max 4 + * channels per FBPA. A floorswept FBPA will have a value of 0x0, vs a + * non-floorswept FBPA with no floorswept channels will have a value of 0xf + * + */ +#define NV208F_CTRL_FB_GET_FBPA_PAC_MASKS_MAX_FBPAS 64 + +#define NV208F_CTRL_CMD_FB_GET_FBPA_PAC_MASKS (0x208f0518) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_GET_FBPA_PAC_MASKS_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_GET_FBPA_PAC_MASKS_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV208F_CTRL_FB_GET_FBPA_PAC_MASKS_PARAMS { + NvU8 fbpas[NV208F_CTRL_FB_GET_FBPA_PAC_MASKS_MAX_FBPAS]; +} NV208F_CTRL_FB_GET_FBPA_PAC_MASKS_PARAMS; + +/* + * NV208F_CTRL_CMD_FB_CONVERT_SUBLOCATION + * + * This API converts either the given sublocation from physical to logical or vice-versa + * + * conversionType: + * See NV208F_CTRL_FB_SUBLOCATION_CONVERSION_TYPE + * fbpa: + * The physical fbpa the sublocation resides + * input: + * Input sublocation + * output: + * Output sublocation + */ +#define NV208F_CTRL_CMD_FB_CONVERT_SUBLOCATION (0x208f0519) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_CONVERT_SUBLOCATION_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_CONVERT_SUBLOCATION_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV208F_CTRL_FB_CONVERT_SUBLOCATION_PARAMS { + NvU32 conversionType; + NvU32 fbpa; + NvU32 input; + NvU32 output; +} NV208F_CTRL_FB_CONVERT_SUBLOCATION_PARAMS; + +#define NV208F_CTRL_FB_SUBLOCATION_CONVERSION_TYPE_LOGICAL_TO_PHYSICAL (0x00000000U) +#define NV208F_CTRL_FB_SUBLOCATION_CONVERSION_TYPE_PHYSICAL_TO_LOGICAL (0x00000001U) + +#define NV208F_CTRL_FB_REMAPPED_BANKS_MAX_BANKS (0x00000200) + +typedef NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO NV208F_CTRL_FB_REMAPPING_BANK_ADDRESS_INFO; + +#define NV208F_CTRL_FB_REMAP_BANK_ADDRESS_TYPE_PHYSICAL NV208F_CTRL_FB_REMAP_ADDRESS_TYPE_PHYSICAL +#define NV208F_CTRL_FB_REMAP_BANK_ADDRESS_TYPE_RBC NV208F_CTRL_FB_REMAP_ADDRESS_TYPE_RBC + +/* valid values for status */ +#define NV208F_CTRL_FB_REMAP_BANK_STATUS_OK NV208F_CTRL_FB_REMAP_STATUS_OK +#define NV208F_CTRL_FB_REMAP_BANK_STATUS_REMAPPING_PENDING NV208F_CTRL_FB_REMAP_STATUS_REMAPPING_PENDING +#define NV208F_CTRL_FB_REMAP_BANK_STATUS_TABLE_FULL NV208F_CTRL_FB_REMAP_STATUS_TABLE_FULL +#define NV208F_CTRL_FB_REMAP_BANK_STATUS_NO_SPARE NV208F_CTRL_FB_REMAP_STATUS_NO_SPARE +#define NV208F_CTRL_FB_REMAP_BANK_STATUS_INTERNAL_ERROR NV208F_CTRL_FB_REMAP_STATUS_INTERNAL_ERROR +#define NV208F_CTRL_FB_REMAP_BANK_STATUS_INVALID_ARGUMENT NV208F_CTRL_FB_REMAP_STATUS_INVALID_ARGUMENT + +/* + * NV208F_CTRL_CMD_FB_REMAP_BANK + * + * This command will write entries to Inforom. During init the entries will be + * read and used to remap banks. + * + * addressList + * This input parameter is an array of NV208F_CTRL_FB_REMAPPING_BANK_ADDRESS_INFO + * structures containing information used for row remapping. Valid entries + * are adjacent. The row field is ignored if RBC address info is given. + * validEntries + * This input parameter specifies the number of valid entries in the + * address array + * numEntriesAdded + * This output parameter specifies how many validEntries were successfully + * added to the Inforom + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_FB_REMAP_BANK (0x208f051a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_REMAP_BANK_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_REMAP_BANK_PARAMS_MESSAGE_ID (0x1aU) + +typedef struct NV208F_CTRL_FB_REMAP_BANK_PARAMS { + NV_DECLARE_ALIGNED(NV208F_CTRL_FB_REMAPPING_BANK_ADDRESS_INFO addressList[NV208F_CTRL_FB_REMAPPED_BANKS_MAX_BANKS], 8); + NvU32 validEntries; + NvU32 numEntriesAdded; +} NV208F_CTRL_FB_REMAP_BANK_PARAMS; + +/* + * NV208F_CTRL_CMD_FB_CLEAR_REMAPPED_BANKS + * + * This command clears remapping entries from the Inforom's bank remapping table. + * + * sourceMask + * This is a bit mask of NV2080_CTRL_FB_REMAPPED_BANK_SOURCE. Rows + * remapped from the specified sources will be cleared/removed from the + * Inforom RRL object entries list. + * + * bForcePurge + * This flag will force purge the BRL object and associated data structures + * + * Possbile status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV208F_CTRL_CMD_FB_CLEAR_REMAPPED_BANKS (0x208f051b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_CLEAR_REMAPPED_BANKS_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_CLEAR_REMAPPED_BANKS_PARAMS_MESSAGE_ID (0x1bU) + +typedef struct NV208F_CTRL_FB_CLEAR_REMAPPED_BANKS_PARAMS { + NvU32 sourceMask; + NvBool bForcePurge; +} NV208F_CTRL_FB_CLEAR_REMAPPED_BANKS_PARAMS; + +/* + * NV208F_CTRL_CMD_FB_SET_ROW_REMAP_FAILURE_FLAG + * + * This command sets the status of row remap failure flag to the passed value. + * + * value + * The value to set for row remap failure flag + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV208F_CTRL_CMD_FB_SET_ROW_REMAP_FAILURE_FLAG (0x208f051cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_SET_ROW_REMAP_FAILURE_FLAG_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_SET_ROW_REMAP_FAILURE_FLAG_PARAMS_MESSAGE_ID (0x1cU) + +typedef struct NV208F_CTRL_FB_SET_ROW_REMAP_FAILURE_FLAG_PARAMS { + NvBool value; +} NV208F_CTRL_FB_SET_ROW_REMAP_FAILURE_FLAG_PARAMS; + +/* _ctrl208ffb_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208ffbio.h b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208ffbio.h new file mode 100644 index 0000000..e9abbf4 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208ffbio.h @@ -0,0 +1,249 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208ffbio.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* + * NV208F_CTRL_CMD_FBIO_SETUP_TRAINING_EXP + * + * This command defines an fbio training experiment for later use. + * + * This command has the form of a 'cmd' operation descriminant + * followed by a union populated with an operand to match the 'cmd'. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_COMMAND + * + */ +#define NV208F_CTRL_CMD_FBIO_SETUP_TRAINING_EXP (0x208f0a03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FBIO_INTERFACE_ID << 8) | NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_PARAMS_MESSAGE_ID" */ + +/* + * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_NULL + * + * This command has no effect when used. + */ +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_NULL 0 + +/* + * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS + * + * This command defines the number of register modification slots to be used + * in the setup phase of the pass/fail training exercise. Using this cmd + * causes any previously defined modification table to be cleared/released. + * The maximum size of the table is defined by + * _SETUP_FBIO_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS__MAX + * Using the value of zero for number of mod slots is valid. "Mod slots" + * are defined below. + * + * Possible status values returned are: + * NV_ERR_INVALID_LIMIT + * if modSlots is > __MAX + * NV_ERR_INSUFFICIENT_RESOURCES + * if we're out of memory setting up the mod slot table + */ +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS 1 +typedef struct NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS_OPERANDS { + NvU32 modSlots; +} NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS_OPERANDS; + +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS__MAX 256 + +/* + * NV208F_CTRL_FBIO_SETUPFBIO_TRAINING_EXP_SET_MOD_SLOT + * + * This command is used to define each individual element of the the sequence + * of operations which will be performed before running the pass/fail training + * exercise. Note that this cmd is multi-cmd (with a null cmd all its own, + * etc). + * + * Possible status values returned are: + * NV_ERR_INVALID_INDEX + * if seq is out of range for previously set SET_NUMBER_OF_MOD_SLOTS + * operation. + * NV_ERR_INVALID_COMMAND + * if cmd isn't recognized + */ +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT 2 + +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_NULL 0 + +/* + * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_SET_REGISTER + * + * This cmd is used to define a register transaction to be applied in + * sequence before running the pass/fail experiment. This is where + * NV_PFB_TRAINING_ADR, NV_PFB_TRAINING_CMD, NV_PFB_TRAINING_DP(i), + * NV_PFB_TRAINING_THRESHOLD and NV_PFB_TRAINING_MASK, etc. should be + * configured before calling back with cmd + * NV208F_CTRL_CMD_FBIO_RUN_TRAINING_EXP. + * + * reg + * This parameter specifies the BAR0 register offset to affect. + * andMask + * orMask + * These parameter specify the RMW values to be used in the following: + * write32(reg, (read32(reg) & andMask) | orMask) + */ +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_SET_REGISTER 1 +typedef struct NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_SET_REGISTER_OPERANDS { + NvU32 reg; + NvU32 andMask; + NvU32 orMask; +} NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_SET_REGISTER_OPERANDS; + +/* + * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_DELAY + * + * This cmd is used to define a delay to be applied in the setup sequence + * before running the pass/fail experiment. + * + * usec + * Specifies delay to be used in microseconds. + */ + +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_DELAY 2 +typedef struct NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_DELAY_OPERANDS { + NvU32 usec; +} NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_DELAY_OPERANDS; + +/* + * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_INIT_LT + * + * This cmd is used to define a point where normal link training initialization + * may be executed in the sequence before running the pass/fail experiment. + * In general, this is not needed since it is done during normal + * initialization, but does allow re-initialization during the sequence. + */ +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_INIT_LT 3 + +/* + * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_RUN_LT + * + * This cmd is used to define a point where normal link training may be + * executed in the sequence before running the pass/fail experiment. + * In general, this is not needed since it is somewhat redundant. + */ +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_RUN_LT 4 + +/* + * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_STOP_SEQ + * + * This cmd is used to define a point where the sequence stops without + * running the pass/fail experiment. + */ +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_STOP_SEQ 5 + + + +typedef struct NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_PARAMS { + NvU32 cmd; + /* C form: NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_OPERANDS op; */ + union { + + NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_SET_REGISTER_OPERANDS setRegister; + + NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_DELAY_OPERANDS delay; + } op; + NvU32 seq; +} NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_PARAMS; + + + +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_PARAMS { + NvU32 cmd; + + /* C form: NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_OPERANDS op; */ + union { + + NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS_OPERANDS setNumberOfModSlots; + + NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_PARAMS setModSlot; + } op; +} NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_PARAMS; + +/* + * NV208F_CTRL_CMD_FBIO_RUN_TRAINING_EXP + * + * This command runs the previously defined experiment and returns status on + * pass/fail. NV_OK is returned in the case of both pass + * and fail. + * + * The risingPasses and fallingPasses outputs represents the results across + * all partitions and bytelanes. Each array entry corresponds to a partition + * and the bits within each member represent the bytelane. So e.g.: + * risingPasses[4] represents the rising pass results for all of partition 4's + * byte lanes. + * + * The partitionsValid bitmask represents the partitions for which the results + * in risingPasses and fallingPasses are valid (not floorswept). + * + * The bytelanesValid bitmask represents the bytelanes for which the results + * are valid (available bytelanes). + * + * The failingDebug[] represent debug data for why (if so) a test fails. + * This is basically NV_PFB_TRAINING_DEBUG(i) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_TIMEOUT + * if hardware doesn't respond to request in a timely manner. + * NV_ERR_INVALID_DATA + * if there was some sort of very weird data corruption issue. + */ +#define NV208F_CTRL_CMD_FBIO_RUN_TRAINING_EXP (0x208f0a04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FBIO_INTERFACE_ID << 8) | NV208F_CTRL_FBIO_RUN_TRAINING_EXP_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FBIO_RUN_TRAINING_EXP_RESULT__SIZE 8 +#define NV208F_CTRL_FBIO_RUN_TRAINING_EXP_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV208F_CTRL_FBIO_RUN_TRAINING_EXP_PARAMS {NvU32 risingPasses[NV208F_CTRL_FBIO_RUN_TRAINING_EXP_RESULT__SIZE]; + NvU32 fallingPasses[NV208F_CTRL_FBIO_RUN_TRAINING_EXP_RESULT__SIZE]; + NvU32 failingDebug[NV208F_CTRL_FBIO_RUN_TRAINING_EXP_RESULT__SIZE]; + NvU32 partitionsValid; + NvU32 bytelanesValid; +} NV208F_CTRL_FBIO_RUN_TRAINING_EXP_PARAMS; + +#define NV208F_CTRL_CMD_FBIO_GET_TRAINING_CAPS (0x208f0a05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FBIO_INTERFACE_ID << 8) | NV208F_CTRL_FBIO_GET_TRAINING_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FBIO_GET_TRAINING_CAPS_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV208F_CTRL_FBIO_GET_TRAINING_CAPS_PARAMS { + NvU32 supported; +} NV208F_CTRL_FBIO_GET_TRAINING_CAPS_PARAMS; + +// _ctrl208ffbio_h_ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208ffifo.h b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208ffifo.h new file mode 100644 index 0000000..d5b8849 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208ffifo.h @@ -0,0 +1,134 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208ffifo.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* + * NV208F_CTRL_CMD_FIFO_CHECK_ENGINE_CONTEXT + * + * This command checks whether or not engine context exists for a given + * engine for the channel with a given channel ID. This API is intended + * for testing virtual context. For debug only. + * + * hChannel + * The handle to the channel. + * engine + * The engine ID. + * Valid values are: + * NV2080_ENGINE_TYPE_GRAPHICS + * exists + * The output are TRUE or FALSE. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_CHANNEL + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_FIFO_CHECK_ENGINE_CONTEXT (0x208f0401) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FIFO_INTERFACE_ID << 8) | NV208F_CTRL_FIFO_CHECK_ENGINE_CONTEXT_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FIFO_CHECK_ENGINE_CONTEXT_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV208F_CTRL_FIFO_CHECK_ENGINE_CONTEXT_PARAMS { + NvHandle hChannel; + NvU32 engine; + NvBool exists; +} NV208F_CTRL_FIFO_CHECK_ENGINE_CONTEXT_PARAMS; + +/* + * NV208F_CTRL_CMD_FIFO_GET_CHANNEL_STATE + * + * This command returns the fifo channel state for the given channel. + * This is for testing channel behavior. For debug only. + * + * hChannel + * The handle to the channel + * hClient + * The handle to the client + * enabled + * The channel is able to run. + * scheduled + * The channel has been scheduled to run. + * cpuMap + * There is a cpu mapping available to this channel. + * contention + * The virtual channel is under contention + * runlistSet + * A runlist has been chosen for this channel + * deferRC + * An RC error has occurred, but recovery will occur at channel teardown. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_CHANNEL + */ +#define NV208F_CTRL_CMD_FIFO_GET_CHANNEL_STATE (0x208f0403) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FIFO_INTERFACE_ID << 8) | NV208F_CTRL_FIFO_GET_CHANNEL_STATE_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FIFO_GET_CHANNEL_STATE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV208F_CTRL_FIFO_GET_CHANNEL_STATE_PARAMS { + NvHandle hChannel; + NvHandle hClient; + NvBool bEnabled; + NvBool bScheduled; + NvBool bCpuMap; + NvBool bContention; + NvBool bRunlistSet; + NvBool bDeferRC; +} NV208F_CTRL_FIFO_GET_CHANNEL_STATE_PARAMS; + +/* + * NV208F_CTRL_CMD_FIFO_GET_CONTIG_RUNLIST_POOL + * + * This command returns the location of the pool runlists are allocated from for + * WPR testing. + * For debug only. + * + * physAddr [out] + * Physical address of the pool + * + * size [out] + * Size in bytes of the pool + * + */ +#define NV208F_CTRL_CMD_FIFO_GET_CONTIG_RUNLIST_POOL (0x208f0404) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FIFO_INTERFACE_ID << 8) | NV208F_CTRL_FIFO_GET_CONTIG_RUNLIST_POOL_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FIFO_GET_CONTIG_RUNLIST_POOL_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV208F_CTRL_FIFO_GET_CONTIG_RUNLIST_POOL_PARAMS { + NV_DECLARE_ALIGNED(NvU64 physAddr, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); +} NV208F_CTRL_FIFO_GET_CONTIG_RUNLIST_POOL_PARAMS; + +/* _ctrl208ffifo_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fgpu.h b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fgpu.h new file mode 100644 index 0000000..2edc89b --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fgpu.h @@ -0,0 +1,169 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fgpu.finn +// + +#include "ctrl/ctrl2080/ctrl2080gr.h" /* 208F is partially derivative of 2080 */ +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* + * NV208F_CTRL_CMD_GPU_GET_RAM_SVOP_VALUES + * + * This command can be used to get the RAM SVOP values. + * + * sp + * This field outputs RAM_SVOP_SP + * rg + * This field outputs RAM_SVOP_REG + * pdp + * This field outputs RAM_SVOP_PDP + * dp + * This field outputs RAM_SVOP_DP + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV208F_CTRL_CMD_GPU_GET_RAM_SVOP_VALUES (0x208f1101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | NV208F_CTRL_GPU_GET_RAM_SVOP_VALUES_PARAMS_MESSAGE_ID" */ + +typedef struct NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS { + NvU32 sp; + NvU32 rg; + NvU32 pdp; + NvU32 dp; +} NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS; + +#define NV208F_CTRL_GPU_GET_RAM_SVOP_VALUES_PARAMS_MESSAGE_ID (0x1U) + +typedef NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS NV208F_CTRL_GPU_GET_RAM_SVOP_VALUES_PARAMS; + +/* + * NV208F_CTRL_CMD_GPU_SET_RAM_SVOP_VALUES + * + * This command can be used to set the RAM SVOP values. + * + * sp + * Input for RAM_SVOP_SP + * rg + * Input for RAM_SVOP_REG + * pdp + * Input for RAM_SVOP_PDP + * dp + * Input for RAM_SVOP_DP + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV208F_CTRL_CMD_GPU_SET_RAM_SVOP_VALUES (0x208f1102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | NV208F_CTRL_GPU_SET_RAM_SVOP_VALUES_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_GPU_SET_RAM_SVOP_VALUES_PARAMS_MESSAGE_ID (0x2U) + +typedef NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS NV208F_CTRL_GPU_SET_RAM_SVOP_VALUES_PARAMS; + + + +/* + * NV208F_CTRL_CMD_GPU_VERIFY_INFOROM + * + * This command can be used by clients to determine if an InfoROM + * with a valid image is present. If the SKU in question does + * not feature an InfoROM, the NV_ERR_NOT_SUPPORTED + * error is returned. Else the RM attempts to read the ROM object + * and any objects listed in the ROM object. The checksum of + * each object read is verified. If all checksums are valid, the + * RM will report the InfoROM as being valid. If image is valid then + * RM will return a checksum for all of the dynamically configurable + * data in InfoROM. This checksum is expected to be same for all the + * boards with an identical InfoROM version and similarly configured. + * + * result + * The result of the InfoROM verification attempt. Possible + * values are: + * NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULTS_NONE + * This value indicates that a validation couldn't be done + * due to some software/OS related error. + * NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULTS_IO_ERROR + * This value indicates that a validation couldn't be done + * due to some IO error. + * NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULTS_VALID + * This value indicates that all InfoROM objects have valid + * checksum. + * NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULTS_INVALID + * This value indicates that some InfoROM objects have invalid + * checksum. + * checksum + * Checksum for all of the dynamically configurable data + * in InfoROM for e.g. PWR and CFG objects. + * + * NOTE: For the result values to be valid, return status should be: + * NV_OK + * + * Possible return status values: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV208F_CTRL_CMD_GPU_VERIFY_INFOROM (0x208f1105) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | NV208F_CTRL_GPU_VERIFY_INFOROM_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_GPU_VERIFY_INFOROM_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV208F_CTRL_GPU_VERIFY_INFOROM_PARAMS { + NvU32 result; + NvU32 checksum; +} NV208F_CTRL_GPU_VERIFY_INFOROM_PARAMS; + +/* valid result values */ +#define NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULT_NONE (0x00000000) +#define NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULT_IO_ERROR (0x00000001) +#define NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULT_VALID (0x00000002) +#define NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULT_INVALID (0x00000003) + +/* + * NV208F_CTRL_CMD_GPU_DISABLE_ECC_INFOROM_REPORTING + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + + + +#define NV208F_CTRL_CMD_GPU_DISABLE_ECC_INFOROM_REPORTING (0x208f1107) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | 0x7" */ + + + +/* _ctrl208fgpu_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fgr.h b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fgr.h new file mode 100644 index 0000000..0317168 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fgr.h @@ -0,0 +1,169 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fgr.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +#include "ctrl/ctrl2080/ctrl2080gr.h" + +/* + * NV208F_CTRL_CMD_GR_ECC_INJECT_ERROR + * + * Control command to inject a gr ecc error + * + * Parameters: + * + * location + * location index + * sublocation + * sublocation index + * unit + * unit to inject error into + * errorType + * SBE or DBE + * grRouteInfo + * Routing info for SMC + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_GR_ECC_INJECT_ERROR (0x208f1203) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GR_INTERFACE_ID << 8) | NV208F_CTRL_GR_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_GR_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV208F_CTRL_GR_ECC_INJECT_ERROR_PARAMS { + NvU32 location; + NvU32 sublocation; + NvU8 unit; + NvU8 errorType; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV208F_CTRL_GR_ECC_INJECT_ERROR_PARAMS; + + + +/* + * NV208F_CTRL_CMD_GR_ECC_INJECTION_SUPPORTED + * + * Reports if error injection is supported for a given HW unit + * + * unit [in]: + * The ECC protected unit for which ECC injection support is being checked. + * + * bCorrectableSupported [out]: + * Boolean value that shows if correcatable errors can be injected. + * + * bUncorrectableSupported [out]: + * Boolean value that shows if uncorrecatable errors can be injected. + * + * Return values: + * NV_OK on success + * NV_ERR_INVALID_ARGUMENT if the requested unit is invalid. + * NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled. + * NV_ERR_NOT_SUPPORTED otherwise + * + * + */ +#define NV208F_CTRL_CMD_GR_ECC_INJECTION_SUPPORTED (0x208f1204) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GR_INTERFACE_ID << 8) | NV208F_CTRL_GR_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_GR_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV208F_CTRL_GR_ECC_INJECTION_SUPPORTED_PARAMS { + NvU8 unit; + NvBool bCorrectableSupported; + NvBool bUncorrectableSupported; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV208F_CTRL_GR_ECC_INJECTION_SUPPORTED_PARAMS; + +/* + * NV208F_CTRL_CMD_GR_ECC_SET_TRANSIENT_CLEARING_POLICY + * + * Control command to determine whether or not the actions to clear potential transient + * errors in the SM should be taken + * + * Parameters: + * + * policy + * NV208F_CTRL_GR_ECC_TRANSIENT_CLEARING_DISABLED + * Don't attempt to clear a transient error in the SM + * NV208F_CTRL_GR_ECC_TRANSIENT_CLEARING_ENABLED + * Attempt to clear a transient error in the SM + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_GR_ECC_TRANSIENT_CLEARING_DISABLED (0x00000000) +#define NV208F_CTRL_GR_ECC_TRANSIENT_CLEARING_ENABLED (0x00000001) + +#define NV208F_CTRL_CMD_GR_ECC_SET_TRANSIENT_CLEARING_POLICY (0x208f1205) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GR_INTERFACE_ID << 8) | NV208F_CTRL_GR_ECC_SET_TRANSIENT_CLEARING_POLICY_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_GR_ECC_SET_TRANSIENT_CLEARING_POLICY_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV208F_CTRL_GR_ECC_SET_TRANSIENT_CLEARING_POLICY_PARAMS { + NvU32 policy; +} NV208F_CTRL_GR_ECC_SET_TRANSIENT_CLEARING_POLICY_PARAMS; + +/* + * NV208F_CTRL_CMD_GR_INJECT_CTXSW_UCODE_ERROR + * + * Control command to inject a CTXSW ucode error + * + * Parameters: + * + * errorType + * Warning, Partial GR Reset, Full GR Reset, or GPU Reset + * + * errorMethod + * Main, Firmware, or Sideband error + * + * bInjectGpccs + * TRUE - inject into GPCCS + * FALSE - inject into FECS + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_GR_INJECT_CTXSW_UCODE_ERROR (0x208f1206) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GR_INTERFACE_ID << 8) | NV208F_CTRL_GR_INJECT_CTXSW_UCODE_ERROR_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_GR_INJECT_CTXSW_UCODE_ERROR_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV208F_CTRL_GR_INJECT_CTXSW_UCODE_ERROR_PARAMS { + NvU32 errorType; + NvU32 errorMethod; + NvBool bInjectGpccs; +} NV208F_CTRL_GR_INJECT_CTXSW_UCODE_ERROR_PARAMS; + + +/* _ctrl208fgr_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fmmu.h b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fmmu.h new file mode 100644 index 0000000..0f0c137 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fmmu.h @@ -0,0 +1,169 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fmmu.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* + * NV208F_CTRL_CMD_MMU_ECC_INJECT_ERROR + * + * This ctrl call injects MMU ECC errors. Please see the confluence + * page "ECC" for more information on ECC and ECC injection: + * + * Parameters: + * + * location + * Only used for HSHUBMMU for pre-Blackwell. + * + * sublocation + * Only used for HSHUBMMU. + * + * unit + * Specifies the MMU HW unit where the injection will occur. + * + * errorType + * Specifies whether the injected error will be correctable or uncorrectable. + * Correctable errors have no effect on running programs while uncorrectable + * errors will cause all channels to be torn down. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_MMU_ECC_INJECT_ERROR (0x208f0b01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID << 8) | NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS { + NvU32 location; + NvU32 sublocation; + NvU8 unit; + NvU8 errorType; +} NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS; + + + +/* + * NV208F_CTRL_CMD_MMU_ECC_INJECTION_SUPPORTED + * + * Reports if error injection is supported for a given HW unit + * + * unit [in]: + * The ECC protected unit for which ECC injection support is being checked. + * + * bCorrectableSupported [out]: + * Boolean value that shows if correcatable errors can be injected. + * + * bUncorrectableSupported [out]: + * Boolean value that shows if uncorrecatable errors can be injected. + * + * Return values: + * NV_OK on success + * NV_ERR_INVALID_ARGUMENT if the requested location is invalid. + * NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled. + * NV_ERR_NOT_SUPPORTED otherwise + * + */ +#define NV208F_CTRL_CMD_MMU_ECC_INJECTION_SUPPORTED (0x208f0b02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID << 8) | NV208F_CTRL_MMU_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */ + + + +#define NV208F_CTRL_MMU_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV208F_CTRL_MMU_ECC_INJECTION_SUPPORTED_PARAMS { + NvU8 unit; + NvBool bCorrectableSupported; + NvBool bUncorrectableSupported; +} NV208F_CTRL_MMU_ECC_INJECTION_SUPPORTED_PARAMS; + +/* + * NV208F_CTRL_CMD_MMU_GET_NUM_HSHUBMMUS + * + * Returns the number of ECC Capable HSHUBMMUS. + * + * numHshubmmus [out] + * Number of Hshubmmus + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV208F_CTRL_CMD_MMU_GET_NUM_HSHUBMMUS (0x208f0b03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID << 8) | NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS { + NvU32 numHshubmmus; +} NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS; + +/* +* NV208F_CTRL_CMD_MMU_GET_NUM_HUBMMUS +* +* Returns the number of ECC Capable HUBMMUS. +* +* numHubmmus [out] +* Number of Hubmmus +* +* Possible status values returned are: +* NV_OK +* NV_ERR_NOT_SUPPORTED +*/ +#define NV208F_CTRL_CMD_MMU_GET_NUM_HUBMMUS (0x208f0b04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID << 8) | NV208F_CTRL_MMU_GET_NUM_HUBMMUS_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_MMU_GET_NUM_HUBMMUS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV208F_CTRL_MMU_GET_NUM_HUBMMUS_PARAMS { + NvU32 numHubmmus; +} NV208F_CTRL_MMU_GET_NUM_HUBMMUS_PARAMS; + + // extension NV_VERIF_FEATURES + +/* +* NV208F_CTRL_CMD_MMU_GET_NUM_L2TLBS +* +* Returns the number of ECC Capable L2TLBs. +* +* numL2tlbs [out] +* Number of L2tlbs +* +* Possible status values returned are: +* NV_OK +* NV_ERR_NOT_SUPPORTED +*/ +#define NV208F_CTRL_CMD_MMU_GET_NUM_L2TLBS (0x208f0b06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID << 8) | NV208F_CTRL_MMU_GET_NUM_L2TLBS_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_MMU_GET_NUM_L2TLBS_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV208F_CTRL_MMU_GET_NUM_L2TLBS_PARAMS { + NvU32 numL2tlbs; +} NV208F_CTRL_MMU_GET_NUM_L2TLBS_PARAMS; +/* _ctrl208fmmu_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fnvlink.h b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fnvlink.h new file mode 100644 index 0000000..ee593b5 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fnvlink.h @@ -0,0 +1,97 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fnvlink.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" +#include "ctrl/ctrl2080/ctrl2080nvlink_common.h" + +/* + * NV208F_CTRL_CMD_NVLINK_ECC_INJECT_ERROR + * + * This ctrl call injects NVLink SAW, RLW, and TLW ECC errors. Please see the confluence + * page "ECC" for more information on ECC and ECC injection: + * + * Parameters: + * + * errorUnit + * Specifies the HW unit where the injection will occur. + * + * errorType + * Specifies whether the injected error will be correctable or uncorrectable. + * Correctable errors have no effect on running programs while uncorrectable + * errors will cause all channels to be torn down. + * + * linkMask + * Specifies the mask of links to inject into where bit 0 = link 0, etc. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_NVLINK_ECC_INJECT_ERROR (0x208f1a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_NVLINK_INTERFACE_ID << 8) | NV208F_CTRL_NVLINK_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */ + + + +#define NV208F_CTRL_NVLINK_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV208F_CTRL_NVLINK_ECC_INJECT_ERROR_PARAMS { + NvU8 errorUnit; + NvU8 errorType; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_MASK links, 8); +} NV208F_CTRL_NVLINK_ECC_INJECT_ERROR_PARAMS; + +/* + * NV208F_CTRL_CMD_NVLINK_ECC_INJECTION_SUPPORTED + * + * Reports if error injection is supported for the NVLink + * + * bCorrectableSupported [out]: + * Boolean value that shows if correcatable errors can be injected. + * + * bUncorrectableSupported [out]: + * Boolean value that shows if uncorrecatable errors can be injected. + * + * Return values: + * NV_OK on success + * NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled. + * NV_ERR_NOT_SUPPORTED otherwise + */ +#define NV208F_CTRL_CMD_NVLINK_ECC_INJECTION_SUPPORTED (0x208f1a02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_NVLINK_INTERFACE_ID << 8) | NV208F_CTRL_NVLINK_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_NVLINK_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV208F_CTRL_NVLINK_ECC_INJECTION_SUPPORTED_PARAMS { + NvU8 errorUnit; + NvBool bCorrectableSupported; + NvBool bUncorrectableSupported; +} NV208F_CTRL_NVLINK_ECC_INJECTION_SUPPORTED_PARAMS; +/* _ctrl208fnvlink_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fpmgr.h b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fpmgr.h new file mode 100644 index 0000000..7b2a5dd --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fpmgr.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fpmgr.finn +// + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fpmu.h b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fpmu.h new file mode 100644 index 0000000..07cf579 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fpmu.h @@ -0,0 +1,115 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fpmu.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* + * NV208F_CTRL_CMD_PMU_ECC_INJECT_ERROR + * + * This ctrl call injects PMU ECC errors. Please see the confluence + * page "ECC" for more information on ECC and ECC injection. + * + * Parameters: + * + * location + * Specifies the PMU HW unit where the injection will occur. + * + * errorType + * Specifies whether the injected error will be correctable or uncorrectable. + * Correctable errors have no effect on running programs while uncorrectable + * errors will cause all channels to be torn down. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_PMU_ECC_INJECT_ERROR (0x208f0c01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_PMU_INTERFACE_ID << 8) | NV208F_CTRL_PMU_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_PMU_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV208F_CTRL_PMU_ECC_INJECT_ERROR_PARAMS { + NvU8 errorType; + NvU32 errorIdx; +} NV208F_CTRL_PMU_ECC_INJECT_ERROR_PARAMS; + +#define NV208F_CTRL_PMU_ECC_INJECT_ERROR_TYPE 0:0 +#define NV208F_CTRL_PMU_ECC_INJECT_ERROR_TYPE_CORRECTABLE (0x00000000) +#define NV208F_CTRL_PMU_ECC_INJECT_ERROR_TYPE_UNCORRECTABLE (0x00000001) + +/* + * NV208F_CTRL_CMD_PMU_ECC_INJECTION_SUPPORTED + * + * Reports if error injection is supported for the PMU + * + * bCorrectableSupported [out]: + * Boolean value that shows if correcatable errors can be injected. + * + * bUncorrectableSupported [out]: + * Boolean value that shows if uncorrecatable errors can be injected. + * + * Return values: + * NV_OK on success + * NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled. + * NV_ERR_NOT_SUPPORTED otherwise + * + * + */ +#define NV208F_CTRL_CMD_PMU_ECC_INJECTION_SUPPORTED (0x208f0c02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_PMU_INTERFACE_ID << 8) | NV208F_CTRL_PMU_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_PMU_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV208F_CTRL_PMU_ECC_INJECTION_SUPPORTED_PARAMS { + NvBool bCorrectableSupported; + NvBool bUncorrectableSupported; +} NV208F_CTRL_PMU_ECC_INJECTION_SUPPORTED_PARAMS; + +/* + * NV208F_CTRL_PMU_ECC_GET_NUM_ERROR_INDEXES + * + * Returns the number of error indexes. + * + * numErrors [out] + * Number of error indexes + * + * Return values: + * NV_OK + */ +#define NV208F_CTRL_CMD_PMU_ECC_GET_NUM_ERROR_INDEXES (0x208f0c03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_PMU_INTERFACE_ID << 8) | NV208F_CTRL_PMU_ECC_GET_NUM_ERROR_INDEXES_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_PMU_ECC_GET_NUM_ERROR_INDEXES_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV208F_CTRL_PMU_ECC_GET_NUM_ERROR_INDEXES_PARAMS { + NvU32 numErrors; +} NV208F_CTRL_PMU_ECC_GET_NUM_ERROR_INDEXES_PARAMS; + +/* _ctrl208fpmu_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fpower.h b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fpower.h new file mode 100644 index 0000000..03f1631 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fpower.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fpower.finn +// + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fsec2.h b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fsec2.h new file mode 100644 index 0000000..cece3c6 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fsec2.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fsec2.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* + * NV208F_CTRL_SEC2_ECC_GET_NUM_ERROR_INDEXES + * + * Returns the number of error indexes. + * + * numErrors [out] + * Number of error indexes + * + * Return values: + * NV_OK + */ +#define NV208F_CTRL_CMD_SEC2_ECC_GET_NUM_ERROR_INDEXES (0x208f1d01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_SEC2_INTERFACE_ID << 8) | NV208F_CTRL_SEC2_ECC_GET_NUM_ERROR_INDEXES_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_SEC2_ECC_GET_NUM_ERROR_INDEXES_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV208F_CTRL_SEC2_ECC_GET_NUM_ERROR_INDEXES_PARAMS { + NvU32 numErrors; +} NV208F_CTRL_SEC2_ECC_GET_NUM_ERROR_INDEXES_PARAMS; + +/* _ctrl208fsec2_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fucodeinstrumentation.h b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fucodeinstrumentation.h new file mode 100644 index 0000000..f368cc4 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl208f/ctrl208fucodeinstrumentation.h @@ -0,0 +1,156 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fucodeinstrumentation.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* Numerical ID for each ucode */ +#define NV208F_UCODE_INSTRUMENTATION_SEC2 1 +#define NV208F_UCODE_INSTRUMENTATION_PMU 2 +#define NV208F_UCODE_INSTRUMENTATION_GSP_TASK_RM 3 +#define NV208F_UCODE_INSTRUMENTATION_GSP_TASK_VGPU 4 + +/* Coverage Type */ +#define NV208F_SANITIZER_COVERAGE_TYPE 0 +#define NV208F_BULLSEYE_COVERAGE_TYPE 1 + +/* + * NV208F_CTRL_UCODE_INSTRUMENTATION_STATE_PARAMS + * + * Parameters struct shared by the control calls + * NV208F_CTRL_CMD_UCODE_INSTRUMENTATION_GET_STATE and + * NV208F_CTRL_CMD_UCODE_INSTRUMENTATION_SET_STATE. + */ +typedef struct NV208F_CTRL_UCODE_INSTRUMENTATION_STATE_PARAMS { + NvU32 ucode; + NvU32 gfid; + NvBool bEnabled; + NvBool bClear; + NvU32 instrumentationType; +} NV208F_CTRL_UCODE_INSTRUMENTATION_STATE_PARAMS; + +/* + * NV208F_CTRL_CMD_UCODE_INSTRUMENTATION_GET_STATE + * + * Retrieves the status of the target ucode's instrumentation + * + * ucode numeric id of the desired ucode to target + * gfid specifies which partition to send the command to + * (applies to ucode=NV208F_UCODE_INSTRUMENTATION_GSP_TASK_VGPU only) + * bEnabled whether the ucode's SanitizerCoverage run-time data gathering + * is enabled (NV_TRUE) or not (NV_FALSE) + * instrumentationType determines if using SanitizerCoverage or BullseyeCoverage + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV208F_CTRL_CMD_UCODE_INSTRUMENTATION_GET_STATE (0x208f1901) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_UCODE_INSTRUMENTATION_INTERFACE_ID << 8) | NV208F_CTRL_UCODE_INSTRUMENTATION_GET_STATE_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_UCODE_INSTRUMENTATION_GET_STATE_PARAMS_MESSAGE_ID (0x1U) + +typedef NV208F_CTRL_UCODE_INSTRUMENTATION_STATE_PARAMS NV208F_CTRL_UCODE_INSTRUMENTATION_GET_STATE_PARAMS; + +/* + * NV208F_CTRL_CMD_UCODE_INSTRUMENTATION_SET_STATE + * + * Enables/disables and optionally clears instrumentation data of the target ucode + * + * ucode numeric id of the desired ucode to target + * gfid specifies which partition to send the command to + * (applies to ucode=NV208F_UCODE_INSTRUMENTATION_GSP_TASK_VGPU only) + * bEnabled whether to enable (NV_TRUE) or disable (NV_FALSE) instrumentation for the given ucode + * bClear whether to clear instrumentation prior to enabling enabling instrumentation + * instrumentationType determines if using SanitizerCoverage or BullseyeCoverage + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV208F_CTRL_CMD_UCODE_INSTRUMENTATION_SET_STATE (0x208f1902) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_UCODE_INSTRUMENTATION_INTERFACE_ID << 8) | NV208F_CTRL_UCODE_INSTRUMENTATION_SET_STATE_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_UCODE_INSTRUMENTATION_SET_STATE_PARAMS_MESSAGE_ID (0x2U) + +typedef NV208F_CTRL_UCODE_INSTRUMENTATION_STATE_PARAMS NV208F_CTRL_UCODE_INSTRUMENTATION_SET_STATE_PARAMS; + +/* + * NV208F_UCODE_INSTRUMENTATION_RPC_MAX_BYTES_* + * + * Maximum number of bytes that can be retrieved by one RPC call + * (potentially differs per-ucode). These are used to size the buffer in the + * respective ucode RPC parameters. + */ +#define NV208F_UCODE_INSTRUMENTATION_RPC_MAX_BYTES_PMU 128 +#define NV208F_UCODE_INSTRUMENTATION_RPC_MAX_BYTES_GSPRM 65536 + +/* + * NV208F_CTRL_CMD_UCODE_INSTRUMENTATION_GET_DATA + * + * Retrieves instrumentation data of the target ucode in chunks. + * Call repeatedly with increasing offset until bComplete is NV_TRUE. + * + * Inputs: + * ucode [in] Numeric ID of the desired ucode to retrieve data from + * gfid [in] Specifies which partition to send the command to + * (applies to ucode=NV208F_UCODE_INSTRUMENTATION_GSP_TASK_VGPU only) + * offset [in] Byte offset from start of coverage data stream. + * Pass 0 on first call, then pass cumulative dataSize + * from previous calls. + * instrumentationType [in] Determines if using SanitizerCoverage or BullseyeCoverage + * + * Outputs: + * data [out] Buffer containing retrieved coverage data + * dataSize [out] Number of bytes written to data[] in this call + * bComplete [out] NV_TRUE when all data has been retrieved, + * NV_FALSE if more chunks remain + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV208F_CTRL_CMD_UCODE_INSTRUMENTATION_GET_DATA (0x208f1903) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_UCODE_INSTRUMENTATION_INTERFACE_ID << 8) | NV208F_CTRL_UCODE_INSTRUMENTATION_GET_DATA_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_UCODE_INSTRUMENTATION_GET_DATA_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV208F_CTRL_UCODE_INSTRUMENTATION_GET_DATA_PARAMS { + NvU32 ucode; + NvU32 gfid; + NvU32 offset; + NvU32 instrumentationType; + NvU8 data[NV208F_UCODE_INSTRUMENTATION_RPC_MAX_BYTES_GSPRM]; + NvU32 dataSize; + NvBool bComplete; +} NV208F_CTRL_UCODE_INSTRUMENTATION_GET_DATA_PARAMS; + +/* _ctrl208fucodeinstrumentation_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl30f1.h b/userspace/sdks/nv570/inc/ctrl/ctrl30f1.h new file mode 100644 index 0000000..064a068 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl30f1.h @@ -0,0 +1,1619 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl30f1.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV30_GSYNC_CTRL control commands and parameters */ + +#define NV30F1_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x30F1, NV30F1_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NV30F1_CTRL_RESERVED (0x00) +#define NV30F1_CTRL_GSYNC (0x01) + +/* + * NV30F1_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV30F1_CTRL_CMD_NULL (0x30f10000) /* finn: Evaluated from "(FINN_NV30_GSYNC_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* NV30F1_CTRL_GSYNC + * + * Gsync board access/control functionality. + * + */ + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_VERSION + * + * This command will get the current gsync api version info. + * + * version + * The api's major version. Does not change often. + * + * revision + * The api's minor version. + * Bumped with each change, no matter how minor. + * + * Possible status values returned are: + * NV_OK + * + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_VERSION (0x30f10101) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS { + NvU32 version; + NvU32 revision; +} NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS; + +#define NV30F1_CTRL_GSYNC_API_VER 1 +#define NV30F1_CTRL_GSYNC_API_REV 0 + +/* + * NV30F1_CTRL_GSYNC api + * + * The gsync interface provides access to gsync devices in the system. + * + * There are commands: + * NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SIGNALS + * Status on input sync signals. + * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_PARAMS + * Get gsync parameters. + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_PARAMS + * Get gsync parameters. + * NV30F1_CTRL_CMD_GSYNC_GET_INFO_CAPS + * Get basic info about the device and its connected displays + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SYNC + * Enable frame sync. + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_UNSYNC + * Disable frame sync. + * NV30F1_CTRL_CMD_GSYNC_GET_STATUS + * Get status info relevant for the control panel + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_TESTING + * Test signal enabling/disabling + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_WATCHDOG + * Control the gsync watchdog + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_INTERLACE_MODE + * Set the interlace mode + * + */ + + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SIGNALS + * + * This command returns information associated with incoming signals to the + * gsync device. + * + * RJ45 + * This parameter contains the signal information for each of the two RJ45 + * ports on the gsync device. A value of ~0 indicates that a signal is + * detected, but no rate information is available. Anything else is a rate + * in units of 10e-4 Hz. + * house + * This parameter contains the signal information for the house sync signal + * (i.e. the bnc port). A value of 0 means that no signal is present. A value + * of ~0 indicates that a signal is detected, but no rate information is + * available. Anything else is a rate in units of 10e-4 Hz. + * rate + * A mask representing signals for which we would like rate information (if + * available). + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + * + */ + +#define NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SIGNALS (0x30f10102) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS { + NvU32 RJ45[2]; + NvU32 house; + NvU32 rate; +} NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS; + +/* + * rate values + * + */ + +#define NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_RJ45_0 (0x00000001) +#define NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_RJ45_1 (0x00000002) +#define NV30F1_CTRL_GSYNC_GET_SIGNALS_HOUSE (0x00000004) + + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_PARAMS + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_PARAMS + * + * These commands respectively return and set state related to the operation + * of the gsync device. + * + * which + * This value is a mask set by the client representing which parameters are + * to be updated. In the case of a GET command, these parameters will + * be used to change the state of the hardware. For both a GET + * command and a SET command, the hardware state will be returned by + * the RM in the respective parameter. All other parameters are untouched. + * syncPolarity + * This parameter specifies which edge of the house sync signal to sync with. + * videoMode + * This parameter specifies which video mode to use to decode the house sync + * signal. + * nSync + * This parameter specifies the number of pulses to wait between frame lock + * signal generation. 0 indicates that every incomming pulse should result in + * a frame lock sync pulse being generated (i.e. the input and output rate + * matches). + * syncSkew + * This parameter specifies the time delay between the frame sync signal and + * the GPUs signal in units of 0.977 us. Maximum value for SyncSkew is defined + * in respective header files of gsync boards. e.g. For P2060 board value + * is defined in drivers/resman/kernel/inc/dacp2060.h + * syncStartDelay + * In master mode, the amount of time to wait before generating the first + * sync pulse in units of 7.81 us, max 512 ms (i.e 65535 units). + * useHouseSync + * When a house sync signal is detected, this parameter indicates that it + * should be used as the reference to generate the frame sync signal. + * syncMulDiv + * Enables multiply/divide of the frequency of the house sync signal by an + * integer. Only supported if the + * NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_MULTIPLY_DIVIDE_SYNC bit is set. The + * maximum value of multiplyDivideValue is given by + * NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS.maxMulDivValue. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ + +#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_PARAMS (0x30f10103) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_PARAMS (0x30f10104) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS_MESSAGE_ID" */ + +typedef struct NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS { + NvU8 multiplyDivideValue; + NvU8 multiplyDivideMode; + NvU16 rsvd; +} NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS; + +typedef struct NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS { + NvU32 which; + NvU32 syncPolarity; + NvU32 syncVideoMode; + NvU32 nSync; + NvU32 syncSkew; + NvU32 syncStartDelay; + NvU32 useHouseSync; + NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS syncMulDiv; + NvU32 syncVRR; +} NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS; + +#define NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS_MESSAGE_ID (0x3U) + +typedef NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS; + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS_MESSAGE_ID (0x4U) + +typedef NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS; + +/* + * which values + * + */ + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY 0x0001 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE 0x0002 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC 0x0004 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW 0x0008 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY 0x0010 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE 0x0020 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MULTIPLY_DIVIDE 0x0040 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_VRR 0x0080 + +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_POLARITY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE +#define NV30F1_CTRL_GSYNC_GET_CONTROL_NSYNC NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_SKEW NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_START_DELAY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_USE_HOUSE NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_MULTIPLY_DIVIDE NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MULTIPLY_DIVIDE +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_VRR NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_VRR + +/* + * syncPolarity values + * + */ + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_RISING_EDGE 0 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_FALLING_EDGE 1 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_BOTH_EDGES 2 + +/* + * syncVideoMode values + * Video_Mode_Composite is valid for P2060 only. + * + */ + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE 0 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL 1 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM 2 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV 3 + +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NONE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_TTL NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NTSCPALSECAM NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_HDTV NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_COMPOSITE 4 + +/* + * multiplyDivide values + * + */ +#define NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_MULTIPLY 0 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_DIVIDE 1 + +/* + * VRR values + * + */ +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MODE_FIXED_REFRESH_RATE 0 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MODE_VARIABLE_REFRESH_RATE 1 + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_CAPS + * + * This command returns the capabilities of this gsync device. + * + * revId + * This parameter is set by the RM to indicate the combined + * FPGA revision (low 4 bits) and board ID (high 4 bits). + * + * boardId + * This parameter is set by the RM to indicate the board ID, + * allowing disambiguation of P2060 and so forth. + * + * minRevRequired + * This parameter is set by the RM to indicate the minimum + * Qsync FPGA revision required for a specific CHIP Familiy + * + * isFirmwareRevMismatch + * This parameter is set to TRUE by RM when the Qsync Firmware + * Revision is incompatibled with the connected GPU chip family. + * + * revision + * This parameter is set by the RM to indicate the device revision, + * also known as major version. + * + * extendedRevision + * This parameter is set by the RM to indicate the device extended + * revision, also known as minor version. + * + * capFlags + * This parameter is set by the RM to indicate capabilities of + * the board, preventing the client from needing to keep track + * of the feature lists supported by each revision of each board. + * + * maxSyncSkew + * This parameter returns that maximum units of sync skew the + * board supports. The value prgrammed into the board has to be + * between 0 and maxSyncSkew, inclusive. The value of each unit + * can be learned from the syncSkewResolution parameter. + * + * syncSkewResolution + * This parameter returns the number of nanoseconds that one unit + * of sync skew corresponds to. + * + * maxStartDelay + * This parameter returns that maximum units of sync start delay + * the board supports. The value prgrammed into the board has to be + * between 0 and maxStartDelay, inclusive. The value of each unit + * can be learned from the startDelayResolution parameter. + * + * startDelayResolution + * This parameter returns the number of nanoseconds that one unit + * of sync start delay corresponds to. + * + * maxSyncInterval + * This parameter returns the maximum duration of house sync interval + * between frame lock sync cycle that the board supports. The value + * programmed into the board has to be between 0 and maxSyncInterval, + * inclusive. + * + * maxMulDivValue + * This parameter returns the maximum possible value that can be + * programmed for multiplying / dividing house sync. Only valid if + * NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_MULTIPLY_DIVIDE_SYNC is set. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV30F1_CTRL_CMD_GSYNC_GET_CAPS (0x30f10105) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS { + NvU32 revId; + NvU32 boardId; + NvU32 minRevRequired; + NvBool isFirmwareRevMismatch; + NvU32 revision; + NvU32 extendedRevision; + NvU32 capFlags; + NvU32 maxSyncSkew; + NvU32 syncSkewResolution; + NvU32 maxStartDelay; + NvU32 startDelayResolution; + NvU32 maxSyncInterval; + NvU32 maxMulDivValue; +} NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS; + +#define NV30F1_CTRL_GSYNC_GET_CAPS_BOARD_ID_P2060 (0x00002060) +#define NV30F1_CTRL_GSYNC_GET_CAPS_BOARD_ID_P2061 (0x00002061) + +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_FREQ_ACCURACY_2DPS (0x00000001) +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_FREQ_ACCURACY_3DPS (0x00000002) +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_FREQ_ACCURACY_4DPS (0x00000004) + +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_NEED_MASTER_BARRIER_WAR (0x00000010) +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_MULTIPLY_DIVIDE_SYNC (0x00000020) + +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_SYNC_LOCK_EVENT (0x10000000) +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_HOUSE_SYNC_EVENT (0x20000000) +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_FRAME_COUNT_EVENT (0x40000000) + +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_ONLY_PRIMARY_CONNECTOR_EVENT (0x01000000) +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_ALL_CONNECTOR_EVENT (0x02000000) + +// For P2060, clients can only request for video modes at BNC connector +// e.g. NO HS, TTL and Composite etc. +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_ONLY_GET_VIDEO_MODE (0x00100000) + +/* + * NV30F1_CTRL_CMD_GET_GSYNC_GPU_TOPOLOGY + * + * This command returns the list of GPU IDs connected with the associated + * gsync device. + * + * gpus + * This array is set by RM to contain the gpu connection information + * for gpus attached to the gsync device. Valid entries are contiguous, + * beginning with the first entry in the list. The elements of this array contain + * the following fields: + * gpuId + * This field contains the ID of the connected GPU. If the entry in the + * table is invalid, this fields contains NV30F1_CTRL_GPU_INVALID_ID. + * connector + * This field indicates which connector on the device the GPU is connected + * to (i.e. the primary or secondary connector), if any. + * proxyGpuId + * If the 'connector' field indicates that the GPU is not connected to + * a G-Sync device directly, then this field contains the ID of the + * GPU that acts as a proxy, i.e. the GPU to which this GPU should be + * a RasterLock slave. + * gpuCapFlags + a bitmap of Gsync-oriented capabilities that this GPU has + * connectorCount + * This parameter indicates the number of GPU connectors available on + * the gsync device. The connector count of the gsync device may be + * less than NV30F1_CTRL_MAX_GPUS_PER_GSYNC. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV30F1_CTRL_CMD_GET_GSYNC_GPU_TOPOLOGY (0x30f10106) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_MAX_GPUS_PER_GSYNC 4 +#define NV30F1_CTRL_GPU_INVALID_ID (0xffffffff) + +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS { + struct { + NvU32 gpuId; + NvU32 connector; + NvU32 proxyGpuId; + NvU32 gpuCapFlags; + } gpus[NV30F1_CTRL_MAX_GPUS_PER_GSYNC]; + NvU32 connectorCount; +} NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS; + +/* + * connector values + * + */ +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_ONE 1 +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_TWO 2 +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_THREE 3 +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_FOUR 4 + +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_NONE 0 +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PRIMARY NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_ONE +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_SECONDARY NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_TWO + +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_GPU_CAP_FLAGS_FRAMELOCK_DIFF_RESOLUTIONS (0x00000001) + + + +/* + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SYNC + * + * This command enables frame sync on displays. + * + * gpuId + * The parameter is set by the client to indicate the gpuId on which + * frame lock will be enabled. + * master + * This parameter is set by the client to specify whether this/these + * displays should be set as the master or as slaves. If this is a GET + * and displays is not 0, this will be set by the RM to indicate if + * the display can be the master. + * displays + * This is a device mask set by the client to indicate which display(s) + * are to be synched. Note that only one display may be set as master. + * If this is a GET, this set by the client to indicate which display + * is to be queried. If the display cannot be synched to this device, + * the RM will overwrite the mask with a 0. + * validateExternal + * This parameter is set by the client to tell the RM to validate the + * presence of an external sync source when enabling a master. + * refresh + * This parameter is set by the client to indicate the desired refresh rate + * The value is in 0.0001 Hertz (i.e. it has been multiplied by 10000). + * configFlags + * contains flags for specific options. So far only + * NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_CONFIG_FLAGS_KEEP_MASTER_SWAPBARRIER_DISABLED + * is supported which allows the caller to prevent the rm code to automatically + * enable the swapbarrier on framelock masters on fpga revisions <= 5. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SYNC (0x30f10110) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SYNC (0x30f10111) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS_MESSAGE_ID" */ + +// If set the swapbarrier is not enable automatically when enablign a framelock master on fpga revs <= 5. +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_CONFIG_FLAGS_KEEP_MASTER_SWAPBARRIER_DISABLED (0x00000001) + +typedef struct NV30F1_CTRL_GSYNC_CONTROL_SYNC_PARAMS { + NvU32 gpuId; + NvU32 master; + NvU32 displays; + NvU32 validateExternal; + NvU32 refresh; + NvU32 configFlags; +} NV30F1_CTRL_GSYNC_CONTROL_SYNC_PARAMS; + +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS_MESSAGE_ID (0x10U) + +typedef NV30F1_CTRL_GSYNC_CONTROL_SYNC_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS; + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS_MESSAGE_ID (0x11U) + +typedef NV30F1_CTRL_GSYNC_CONTROL_SYNC_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS; + +/* + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_UNSYNC + * + * This command disables frame sync on displays + * + * gpuId + * The parameter is set by the client to indicate the gpuId on which + * frame lock will be disabled. + * master + * This parameter is set by the client to specify whether this/these + * display(s) to be unset is a master/are slaves. + * displays + * This is a device mask set by the client to indicate which display(s) + * are to be unsynched. + * retainMaster + * Retain the designation as master, but unsync the displays. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + */ +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_UNSYNC (0x30f10112) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS { + NvU32 gpuId; + NvU32 master; + NvU32 displays; + NvU32 retainMaster; +} NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS; + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SYNC + * + * This command gets the sync state for the gpus attached to the + * framelock device. Note that the frame lock device only has + * knowledge of sync status at the gpu level, not the display + * device level. + * + * gpuId + * The parameter is set by the client to indicate which gpuId is to be + * queried. + * bTiming + * This parameter is set by the RM to indicate that timing on the GPU is + * in sync with the master sync signal. + * bStereoSync + * This parameter is set by the RM to indicate whether the phase of the + * timing signal coming from the GPU is the same as the phase of the + * master sync signal. + * bSyncReady + * This parameter is set by the RM to indicate if a sync signal has + * been detected. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ + +#define NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SYNC (0x30f10113) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS { + NvU32 gpuId; + NvU32 bTiming; + NvU32 bStereoSync; + NvU32 bSyncReady; +} NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS; + + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_STATUS + * + * This command gets status information for the frame lock device + * relevant to a control panel. + * + * which + * This is a mask set by the client describing which of the other + * parameters we should collect status information for. + * bLeadingEdge + * This parameter is set by the RM to indicate that the gsync device is + * set to sync to the leading edge of a house sync signal. Note that + * this does not mean that house sync is the signal source. + * bFallingEdge + * This parameter is set by the RM to indicate that the gsync device is + * set to sync to the falling edge of a house sync signal. Note that + * this does not mean that house sync is the signal source. + * syncDelay + * This parameter is set by the RM to indicate the sync delay in + * microseconds, + * refresh + * This parameter is set by the RM to indicate the rate of frame sync pulse in + * 0.0001 Hertz (i.e. it has been multiplied by 10000). This is not the refresh + * rate of display device. This is same as incoming house sync rate if + * framelocked to an external house sync signal. Otherwise, this is same + * as the refresh rate of the master display device. + * houseSyncIncomming + * This parameter is set by the RM to indicate the rate of an incomming + * house sync signal in 0.0001 Hertz (i.e. it has been multiplied by 10000). + * syncInterval + * This parameter is set by the RM to indicate the number of incoming + * sync pulses to wait before the generation of the frame sync pulse. + * bSyncReady + * This paramater is set by the RM to indicate if a sync signal has + * been detected (this parameter is also available from the + * NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SYNC method). + * bSwapReady + * This paramater is set by the RM to indicate if the hardware is + * ready to swap. + * bHouseSync + * This parameter is set by the RM to indicate that a house sync signal + * should be used as the source signal if it is available. + * bPort0Input + * This parameter is set by the RM to indicate that RJ45 port 0 is + * configured as an input. + * bPort1Input + * This parameter is set by the RM to indicate that RJ45 port 1 is + * configured as an input + * bPort0Ehternet + * This parameter is set by the RM to indicate that RJ45 port 0 has + * been connected to an ethernet hub (this is not the right thing to do). + * bPort1Ehternet + * This parameter is set by the RM to indicate that RJ45 port 1 has + * been connected to an ethernet hub (this is not the right thing to do). + * universalFrameCount + * This parameter is set by the RM to indicate the value of the + * Universal frame counter. + * bInternalSlave + * This parameter is set by the RM to indicate that a p2061 has been + * configured as internal slave. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_STATUS (0x30f10114) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS { + NvU32 which; + NvU32 bLeadingEdge; + NvU32 bFallingEdge; + NvU32 syncDelay; + NvU32 refresh; + NvU32 houseSyncIncoming; + NvU32 syncInterval; + NvU32 bSyncReady; + NvU32 bSwapReady; + NvU32 bHouseSync; + NvU32 bPort0Input; + NvU32 bPort1Input; + NvU32 bPort0Ethernet; + NvU32 bPort1Ethernet; + NvU32 universalFrameCount; + NvU32 bInternalSlave; +} NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS; + +/* + * which values + * + */ + +#define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_POLARITY (0x00000001) +#define NV30F1_CTRL_GSYNC_GET_STATUS_LEADING_EDGE (0x00000001) +#define NV30F1_CTRL_GSYNC_GET_STATUS_FALLING_EDGE (0x00000001) +#define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_DELAY (0x00000002) +#define NV30F1_CTRL_GSYNC_GET_STATUS_REFRESH (0x00000004) +#define NV30F1_CTRL_GSYNC_GET_STATUS_HOUSE_SYNC_INCOMING (0x00000008) +#define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_INTERVAL (0x00000010) +#define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_READY (0x00000020) +#define NV30F1_CTRL_GSYNC_GET_STATUS_SWAP_READY (0x00000040) +#define NV30F1_CTRL_GSYNC_GET_STATUS_TIMING (0x00000080) +#define NV30F1_CTRL_GSYNC_GET_STATUS_STEREO_SYNC (0x00000100) +#define NV30F1_CTRL_GSYNC_GET_STATUS_HOUSE_SYNC (0x00000200) +#define NV30F1_CTRL_GSYNC_GET_STATUS_PORT_INPUT (0x00000400) +#define NV30F1_CTRL_GSYNC_GET_STATUS_PORT0_INPUT (0x00000400) +#define NV30F1_CTRL_GSYNC_GET_STATUS_PORT1_INPUT (0x00000400) +#define NV30F1_CTRL_GSYNC_GET_STATUS_PORT_ETHERNET (0x00000800) +#define NV30F1_CTRL_GSYNC_GET_STATUS_PORT0_ETHERNET (0x00000800) +#define NV30F1_CTRL_GSYNC_GET_STATUS_PORT1_ETHERNET (0x00000800) +#define NV30F1_CTRL_GSYNC_GET_STATUS_UNIVERSAL_FRAME_COUNT (0x00001000) +#define NV30F1_CTRL_GSYNC_GET_STATUS_INTERNAL_SLAVE (0x00002000) + +/* + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_TESTING + * + * This command controls the test signal on the gsync device. + * + * bEmitTestSignal + * This parameter is set by the client to emit or stop emitting the test + * signal. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_TESTING (0x30f10120) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_TESTING (0x30f10121) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS_MESSAGE_ID" */ + +typedef struct NV30F1_CTRL_GSYNC_CONTROL_TESTING_PARAMS { + NvU32 bEmitTestSignal; +} NV30F1_CTRL_GSYNC_CONTROL_TESTING_PARAMS; + +#define NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS_MESSAGE_ID (0x20U) + +typedef NV30F1_CTRL_GSYNC_CONTROL_TESTING_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS; + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS_MESSAGE_ID (0x21U) + +typedef NV30F1_CTRL_GSYNC_CONTROL_TESTING_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS; + +/* + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_WATCHDOG + * + * This command enables and disables the gsync watchdog + * + * enable + * This parameter is set by the client to enable or disable the + * gsync watchdog. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + */ +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_WATCHDOG (0x30f10130) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS_MESSAGE_ID (0x30U) + +typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS { + NvU32 enable; +} NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS; + + +/* + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_INTERLACE_MODE + * + * This command enables or disables interlace mode. + * + * enable + * This parameter is set by the client to enable or disable + * interlace mode + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_INTERLACE_MODE (0x30f10140) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_INTERLACE_MODE (0x30f10141) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID" */ + +typedef struct NV30F1_CTRL_GSYNC_CONTROL_INTERLACE_MODE_PARAMS { + NvU32 enable; +} NV30F1_CTRL_GSYNC_CONTROL_INTERLACE_MODE_PARAMS; + +#define NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID (0x40U) + +typedef NV30F1_CTRL_GSYNC_CONTROL_INTERLACE_MODE_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS; + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID (0x41U) + +typedef NV30F1_CTRL_GSYNC_CONTROL_INTERLACE_MODE_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS; + +/* + * + * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SWAP_BARRIER + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SWAP_BARRIER + * + * These commands enables or disables the swap barrier + * connection between a GPU and the rest of the gsync + * network + * + * gpuId + * The parameter is set by the client to indicate which gpuId is to be + * queried. + * enable + * In a set command, this parameter is set by the client to + * indicate if the barrier should be enabled (i.e. connected + * to the rest of the network) or disabled (disconnected). + * In both a set and a get command, if successful, the RM + * uses this parameter to return the current (i.e. post-set) + * value. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SWAP_BARRIER (0x30f10150) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SWAP_BARRIER (0x30f10151) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID" */ + +typedef struct NV30F1_CTRL_GSYNC_CONTROL_SWAP_BARRIER_PARAMS { + NvU32 gpuId; + NvBool enable; +} NV30F1_CTRL_GSYNC_CONTROL_SWAP_BARRIER_PARAMS; + +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID (0x50U) + +typedef NV30F1_CTRL_GSYNC_CONTROL_SWAP_BARRIER_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS; + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID (0x51U) + +typedef NV30F1_CTRL_GSYNC_CONTROL_SWAP_BARRIER_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS; + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW + * + * This command allow clients to obtain time period for which SwapLock window will + * remain HIGH for GSYNC III (P2060) i.e. TswapRdyHi. RM clients will use this value + * for programming SWAP_LOCKOUT_START on all heads of GPU connected to P2060. + * + * tSwapRdyHi + * RM will return swap lock window High time period in this variable. By default + * tSwapRdyHi is 250 micro seconds. RM also provide regkey to change this value. + * tSwapRdyHi also used by RM to configure value of LSR_MIN_TIME while programming + * swap barrier. + * Client should consider tSwapRdyHi only for Gsync III (P2060) network. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW (0x30f10153) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS_MESSAGE_ID (0x53U) + +typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS { + NvU32 tSwapRdyHi; +} NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS; + + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_OPTIMIZED_TIMING + * + * This command allows the client to obtain suggested + * adjustments to vertical and horizontal timing values + * that will improve the ability of gsync to lock. + * + * gpuId + * This parameter is set by the client to indicate the + * gpuId of the GPU to which the display to be optimized + * is attached. + * output + * This parameter is set by the client to indicate the + * output resource type of the display to be optimized. + * For example, CRTs use DAC output, while DFPs use SOR + * (Serial Output Resource) type. + * protocol + * This parameter is set by the client to indicate the + * data protocol of output resource. For DAC displays, + * the format of the standard mode most closely matching + * the desired mode is used. For SOR display devices, + * the LVDS/TMDS/etc format is the protocol. + * structure + * This parameter is set by the client to indicate the + * raster structure of the mode, either progressive or + * interlaced. Diagrams of the raster structures are + * provided below. + * adjust + * This parameter is set by the client to specify which + * of the timing values, other than hTotal and vTotal, + * may be adjusted during optimization. + * If the client does not obtain instructions from the + * user about where adjustments should be applied, safe + * default values for progressive/interlaced modes are + * provided below. + * hTotal + * This parameter is set by the client to specify the + * initial Horizontal Pixel Total, from which the + * RM will begin optimizing. The RM also uses the + * parameter to return the optimized value. + * vTotal + * This parameter is set by the client to specify the + * initial Vertical Pixel Total, from which the + * RM will begin optimizing. The RM also uses the + * parameter to return the optimized value. + * hBlankStart + * This parameter is set by the client to specify the + * initial Horizontal Blanking Start, from which the + * RM will begin optimizing. The RM also uses the + * parameter to return the optimized value. + * vBlankStart + * This parameter is set by the client to specify the + * initial Vertical Blanking Start, from which the + * RM will begin optimizing. The RM also uses the + * parameter to return the optimized value. + * hBlankEnd + * This parameter is set by the client to specify the + * initial Horizontal Blanking End, from which the + * RM will begin optimizing. The RM also uses the + * parameter to return the optimized value. + * vBlankEnd + * This parameter is set by the client to specify the + * initial Vertical Blanking End, from which the + * RM will begin optimizing. The RM also uses the + * parameter to return the optimized value. + * vInterlacedBlankStart + * This parameter is set by the client to specify the + * initial Interlaced Vertical Blanking Start, from + * which the RM will begin optimizing. The RM will + * ignore this parameter for non-interlaced modes, as + * it has no meaning in those modes. In modes where + * it is meaningful, the RM also uses the parameter + * to return the optimized value. + * vInterlacedBlankEnd + * This parameter is set by the client to specify the + * initial Interlaced Vertical Blanking End, from + * which the RM will begin optimizing. The RM will + * ignore this parameter for non-interlaced modes, as + * it has no meaning in those modes. In modes where + * it is meaningful, the RM also uses the parameter + * to return the optimized value. + * hSyncEnd + * This parameter is set by the client to specify the + * initial Horizontal Raster Sync End, from which the + * RM will begin optimizing. The RM also uses the + * parameter to return the optimized value. + * vSyncEnd + * This parameter is set by the client to specify the + * initial Vertical Raster Sync End, from which the + * RM will begin optimizing. The RM also uses the + * parameter to return the optimized value. + * hDeltaStep + * This parameter is set by the client to specify the + * increments by which the Horizontal Pixel Total may + * be adjusted by the RM, during optimization. + * If the client does not obtain a custom value for + * this parameter from the user, setting all four of + * hDeltaStep, vDeltaStep, hDeltaMax, and vDeltaMax + * to zero will result in a safe default for all four. + * vDeltaStep + * This parameter is set by the client to specify the + * increments by which the vertical timings of each + * frame (in interlaced modes, each field) may be + * adjusted by the RM, during optimization. + * In interlaced modes, the adjustments to vTotal, + * vInterlacedBlankStart, and vInterlacedBlankEnd may + * be in increments of vDeltaStep or twice vDeltaStep, + * depending on where adjustments are made. + * In progressive modes, the adjustment to the vTotal + * will simply be in increments of vDeltaStep. + * If the client does not obtain a custom value for + * this parameter from the user, setting all four of + * hDeltaStep, vDeltaStep, hDeltaMax, and vDeltaMax + * to zero will result in a safe default for all four. + * hDeltaMax + * This parameter is set by the client to specify the + * maximum amount that the Horizontal Pixel Total may + * be adjusted by the RM, during optimization. + * If the client does not obtain a custom value for + * this parameter from the user, setting all four of + * hDeltaStep, vDeltaStep, hDeltaMax, and vDeltaMax + * to zero will result in a safe default for all four. + * vDeltaMax + * This parameter is set by the client to specify the + * maximum amount that vertical timings of each frame + * (in interlaced modes, each field) may be adjusted + * by the RM, during optimization. + * In interlaced modes, the adjustments to vTotal, + * vInterlacedBlankStart, and vInterlacedBlankEnd may + * be up to twice vDeltaMax. + * In progressive modes, the adjustment to the vTotal + * may simply be up to vDeltaMax. + * If the client does not obtain a custom value for + * this parameter from the user, setting all four of + * hDeltaStep, vDeltaStep, hDeltaMax, and vDeltaMax + * to zero will result in a safe default for all four. + * refreshX10K + * This parameter is set by the client to specify the + * desired refresh rate, multiplied by 10000. This + * allows refresh rate to be set in units of 0.0001 Hz. + * For example, a 59.94 Hz rate would be set as 599400. + * The client can alternatively specify a the + * pixelClockHz parameter (if the passed in refreshX10K + * parameter is set to 0, the pixelClockHz parameter + * will be used). + * pixelClockHz + * This parameter is set by the client to specify the + * desired pixel clock frequency in units of Hz. The + * client can alternatively specify the refreshX10K parameter. + * This parameter is returned by the RM to report the + * optimal pixel clock to use with the adjusted mode, + * in units of Hz. + * + * + * bOptimized[out] + * This is set to NV_TRUE if the timings were successfully optimized, and + * NV_FALSE otherwise. + * + * + * Progressive Raster Structure + * + * hSyncEnd hTotal + * 0 | hBlankEnd hBlankStart | + * | | | | | vSync vBlank + * 0--+--------------------------------------------+ +-+ | + * | Sync | | | + * vSyncEnd--| +----------------------------------------+ +-+ | + * | | Back Porch | | | + * vBlankEnd--| | +--------------------------------+ | | +-+ + * | | | Active Area | | | | + * | | | +------------------------+ | | | | + * | | | | | | | | | + * | S | B | A | | A | F | | | + * | y | a | c | | c | r | | | + * | n | c | t | | t | o | | | + * | c | k | i | | i | n | | | + * | | | v | | v | t | | | + * | | P | e | Output Viewport | e | | | | + * | | o | | | | P | | | + * | | r | A | | A | o | | | + * | | c | r | | r | r | | | + * | | h | e | | e | c | | | + * | | | a | | a | h | | | + * | | | | | | | | | + * | | | +------------------------+ | | | | + * | | | Active Area | | | | + * vBlankStart-| | +--------------------------------+ | | +-+ + * | | Front Porch | | | + * vTotal--+---+----------------------------------------+ +-+ | + * ___ + * / \________________________________________/ hSync + * ________ ____ + * \________________________________/ hBlank + * + * + * + * Interlaced Raster Structure + * + * hSyncEnd hTotal + * 0 | hBlankEnd hBlankStart | + * | | | | | vSync vBlank + * 0--+--------------------------------------------+ +-+ | + * | Sync | | | + * vSyncEnd--| +----------------------------------------+ +-+ | + * | | Back Porch | | | + * vBlankEnd--| | +--------------------------------+ | | +-+ + * | | | Active Area | | | | + * | | | +------------------------+ | | | | + * | | | | | | | | | + * | S | B | A | | A | F | | | + * | y | a | c | | c | r | | | + * | n | c | t | | t | o | | | + * | c | k | i | | i | n | | | + * | | | v | | v | t | | | + * | | P | e | Output Viewport | e | | | | + * | | o | | | | P | | | + * | | r | A | | A | o | | | + * | | c | r | | r | r | | | + * | | h | e | | e | c | | | + * | | | a | | a | h | | | + * | | | | | | | | | + * | | | +------------------------+ | | | | + * | | | Active Area | | | | + * vBlankStart-| | +--------------------------------+ | | +-+ + * | | | | | + * | | Front Porch +--------------------+ | | + * | | | | +-+ | + * | +-------------------+ | | | + * | | | | + * | Sync +--------------------+ | | + * | | | +-+ | + * | +-------------------+ | | | + * vInterlaced | | Back Porch | | | + * BlankEnd--| | +--------------------------------+ | | +-+ + * | | | Active Area | | | | + * | | | +------------------------+ | | | | + * | | | | | | | | | + * | S | B | A | | A | F | | | + * | y | a | c | | c | r | | | + * | n | c | t | | t | o | | | + * | c | k | i | | i | n | | | + * | | | v | | v | t | | | + * | | P | e | Output Viewport | e | | | | + * | | o | | | | P | | | + * | | r | A | | A | o | | | + * | | c | r | | r | r | | | + * | | h | e | | e | c | | | + * | | | a | | a | h | | | + * | | | | | | | | | + * | | | +------------------------+ | | | | + * vInterlaced | | | Active Area | | | | + * BlankStart-| | +--------------------------------+ | | +-+ + * | | Front Porch | | | + * vTotal--+---+----------------------------------------+ +-+ | + * ___ + * / \________________________________________/ hSync + * ________ ____ + * \________________________________/ hBlank + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * +*/ + +#define NV30F1_CTRL_CMD_GSYNC_GET_OPTIMIZED_TIMING (0x30f10160) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS_MESSAGE_ID (0x60U) + +typedef struct NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS { + NvU32 gpuId; + NvU32 output; + NvU32 protocol; + NvU32 structure; + NvU32 adjust; + NvU32 hDeltaStep; + NvU32 hDeltaMax; + NvU32 vDeltaStep; + NvU32 vDeltaMax; + NvU32 hSyncEnd; + NvU32 hBlankEnd; + NvU32 hBlankStart; + NvU32 hTotal; + NvU32 vSyncEnd; + NvU32 vBlankEnd; + NvU32 vBlankStart; + NvU32 vInterlacedBlankEnd; + NvU32 vInterlacedBlankStart; + NvU32 vTotal; + NvU32 refreshX10K; + NV_DECLARE_ALIGNED(NvU64 pixelClockHz, 8); + + NvBool bOptimized; +} NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS; + +/* output values */ +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_OUTPUT_DAC (0x00000001) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_OUTPUT_SOR (0x00000004) + +/* protocol values for DAC displays (e.g. CRTs) */ +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_DAC_RGB_CRT (0x00000000) + +/* protocol values for SOR displays (e.g. DFPs) */ +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_LVDS_CUSTOM (0x00000000) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_SINGLE_TMDS_A (0x00000001) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_SINGLE_TMDS_B (0x00000002) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_DUAL_TMDS (0x00000005) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_DP_A (0x00000008) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_DP_B (0x00000009) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_HDMI_FRL (0x0000000C) + +/* structure values */ +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_STRUCTURE_INTERLACED (0x00000001) + +/* adjust values */ +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_H_FRONT_PORCH (0x00000001) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_V_FRONT_PORCH (0x00000002) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_H_ACTIVE_AREA (0x00000004) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_V_ACTIVE_AREA (0x00000008) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_H_BACK_PORCH (0x00000010) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_V_BACK_PORCH (0x00000020) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_H_RASTER_SYNC (0x00000040) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_V_RASTER_SYNC (0x00000080) + +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_DEFAULT_CRT (0x00000030) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_DEFAULT_DFP (0x00000020) + +/* DeltaStep and DeltaMax values to trigger default settings */ +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_H_DELTA_STEP_USE_DEFAULTS (0x00000000) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_H_DELTA_MAX_USE_DEFAULTS (0x00000000) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_V_DELTA_STEP_USE_DEFAULTS (0x00000000) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_V_DELTA_MAX_USE_DEFAULTS (0x00000000) + +/* + * NV30F1_CTRL_CMD_GSYNC_SET_EVENT_NOTIFICATION + * + * This command sets event notification state for the associated Gsync + * object. This command requires that an instance of NV01_EVENT has + * been previously bound to the associated Gsync object. + * + * If one or more of the "smart event notification" options are set in the + * action parameter, multiple sequential events of the same type will only + * trigger one notification. After that, only an event of a different type + * will trigger a new notification. + * + * action + * This member specifies the desired event notification action. + * Valid notification actions include: + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_DISABLE + * This action disables event notification for the associated + * Gsync object. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_LOSS + * This action enables smart event notification for the + * associated Gsync object, for "sync loss" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_GAIN + * This action enables smart event notification for the + * associated Gsync object, for "sync gained" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_STEREO_LOSS + * This action enables smart event notification for the + * associated Gsync object, for "stereo lost" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_STEREO_GAIN + * This action enables smart event notification for the + * associated Gsync object, for "stereo gained" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_HOUSE_GAIN + * This action enables smart event notification for the + * associated Gsync object, for "house sync (BNC) plug in" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_HOUSE_LOSS + * This action enables smart event notification for the + * associated Gsync object, for "house sync (BNC) plug out" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_RJ45_GAIN + * This action enables smart event notification for the + * associated Gsync object, for "ethernet (RJ45) plug in" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_RJ45_LOSS + * This action enables smart event notification for the + * associated Gsync object, for "ethernet (RJ45) plug out" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_COUNT_MATCH + * This action enables smart event notification for the + * associated Gsync object, for "frame counter match" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_ALL + * This action enables smart event notification for the + * associated Gsync object, for any type of event. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV30F1_CTRL_CMD_GSYNC_SET_EVENT_NOTIFICATION (0x30f10170) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS_MESSAGE_ID (0x70U) + +typedef struct NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS { + NvU32 action; +} NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS; + +/* valid action values */ + +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_LOSS (0x00000001) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_GAIN (0x00000002) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_STEREO_LOSS (0x00000004) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_STEREO_GAIN (0x00000008) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_HOUSE_GAIN (0x00000010) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_HOUSE_LOSS (0x00000020) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_RJ45_GAIN (0x00000040) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_RJ45_LOSS (0x00000080) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_COUNT_MATCH (0x00000100) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_ALL (0x000001FF) + +#define NV30F1_CTRL_GSYNC_EVENT_TYPES 9 + +/* + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE + * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE + * + * These commands can be used to get/set the stereo lock assistance mode of + * the GSYNC device. This is supported by GSYNC III device only. + * 1] In this mode the GSYNC recreates the hidden VS either by -> + * (a) using local stereo edge if stereo is toggle or + * (b) counting lines and generate the missing VS. + * 2] Master GSYNC card recreates the stereo and passes it along to + * the slave GSYNC cards. + * 3] Slave GSYNC cards generates the stereo raster sync structure to + * synchronize the GPU. + * 4] For stereo sync status reporting, under this mode, the GSYNC automatically + * reports stereo lock whenever it gets the master stereo signal. The + * assumption is local stereo will be in synced with the new structure. + * 5] If the slave GSYNC card does not observed master stereo for any reason, + * (a) it clears the stereo sync bit and + * (b) it generates its own version of stereo and sync the GPU. + * + * Parameters: + * gpuId + * This parameter is set by the client to indicate the gpuId on which + * the stereo lock mode should be enabled/disabled. + * + * enable + * In SET query, this parameter is set by the client to indicate whether + * RM should enable or disable stereo lock mode for GPU specified in gpuId. + * 1 and 0 indicates enable and disable stereo lock mode respectively. In + * GET query, RM will set this parameter to 1 or 0 depending on StereoLock + * mode is enabled or not respectively for specified GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE (0x30f10172) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE (0x30f10173) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID" */ + +typedef struct NV30F1_CTRL_CMD_GSYNC_CONTROL_STEREO_LOCK_MODE_PARAMS { + NvU32 gpuId; + NvU32 enable; +} NV30F1_CTRL_CMD_GSYNC_CONTROL_STEREO_LOCK_MODE_PARAMS; + +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID (0x72U) + +typedef NV30F1_CTRL_CMD_GSYNC_CONTROL_STEREO_LOCK_MODE_PARAMS NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS; + +#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID (0x73U) + +typedef NV30F1_CTRL_CMD_GSYNC_CONTROL_STEREO_LOCK_MODE_PARAMS NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS; + +/* + * NV30F1_CTRL_CMD_GSYNC_READ_REGISTER + * + * This command is used to read raw i2c registers from the gsync device, via + * the given GPU (registers on the same gsync device may have different values + * depending on which GPU is used to do the read). + * + * This may only be used by a privileged client. + * + * Parameters: + * gpuId + * This parameter is set by the client to specify which GPU to use to + * perform the read. + * + * reg + * This parameter is set by the client to specify which i2c register to + * read. + * + * data + * This parameter is written by the RM and returned to the client upon a + * successful read. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +#define NV30F1_CTRL_CMD_GSYNC_READ_REGISTER (0x30f10180) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS_MESSAGE_ID (0x80U) + +typedef struct NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS { + NvU32 gpuId; + NvU8 reg; + NvU8 data; +} NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS; + +/* + * NV30F1_CTRL_CMD_GSYNC_WRITE_REGISTER + * + * This command is used to write raw i2c registers on the gsync device, via the + * given GPU (registers on the same gsync device may have different values + * depending on which GPU is used to do the write). + * + * This may only be used by a privileged client. + * + * Parameters: + * gpuId + * This parameter is set by the client to specify which GPU to use to + * perform the write. + * + * reg + * This parameter is set by the client to specify which i2c register to + * write. + * + * data + * This parameter is set by the client to specify what data to write to the + * given i2c register. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ + +#define NV30F1_CTRL_CMD_GSYNC_WRITE_REGISTER (0x30f10181) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS { + NvU32 gpuId; + NvU8 reg; + NvU8 data; +} NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS; + + + +/* + * NV30F1_CTRL_CMD_GSYNC_SET_LOCAL_SYNC + * + * This command enables/disables raster sync on displays i.e. + * mosaic groups between gpus. + * + * gpuTimingSource + * The parameter is set by the client to indicate the gpuId of the + * Timing Source gpu for specified mosaic group. + * gpuTimingSlaves[] + * This parameter is set by the client to indicate the gpuIds of the + * timing slave gpus for specified mosaic group. It should not contain + * more gpuids than slaveGpuCount. + * slaveGpuCount + * This parameter is set by the client to indicate the count of timing + * slave gpus under specified group. + * Referring to gsync3-P2060, slaveGpuCount can vary from 0x01 to 0x03 + * as maximum possible connected gpus are four and one gpu must be + * timing master for mosaic group. + * mosaicGroupNumber + * This parameter is set by the client to tell the RM to which mosaic + * group it should refer. + * Referring to gsync3-P2060, mosaicGroupNumber can contain 0x00 or + * 0x01 as only two mosaic groups are possible. + * enableMosaic + * This parameter is set by the client to indicate RM that whether RM + * should enable mosaic or disable mosaic. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV30F1_CTRL_CMD_GSYNC_SET_LOCAL_SYNC (0x30f10185) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS_MESSAGE_ID (0x85U) + +typedef struct NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS { + NvU32 gpuTimingSource; + NvU32 gpuTimingSlaves[NV30F1_CTRL_MAX_GPUS_PER_GSYNC]; + NvU32 slaveGpuCount; + NvU32 mosaicGroupNumber; + NvBool enableMosaic; +} NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS; + +/* + * NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH + * + * This command configure GSYNC registers for pre-flash and post-flash + * operations. This is currenly used for GSYNC-3 (P2060) only. RM clients + * has to make sure that they perform both pre-flash and post-flash + * operations on GSYNC board. Avoiding, post-flash will cause mismatch + * between RM cached-data and GSYNC register values. + * + * Parameters: + * gpuId + * This parameter is set by the client to indicate the gpuId for which + * GSYNC board connected to that GPU will be configured for pre-flash + * or post-flash operation depending on preFlash value. + * + * preFlash + * This parameter is set by the client to indicate whether RM has to configure + * GSYNC registers and SW state for pre-flash or post-flash operation. Values + * 1 and 0 indicates that RM will configure GSYNC board for pre-flash and + * post-flash operations respectively. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH (0x30f10186) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS_MESSAGE_ID (0x86U) + +typedef struct NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS { + NvU32 gpuId; + NvU32 preFlash; +} NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS; + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_HOUSE_SYNC_MODE + * NV30F1_CTRL_CMD_GSYNC_SET_HOUSE_SYNC_MODE + * + * These two commands gets/sets house sync mode as input or output. + * + * Parameters: + * houseSyncMode + * This parameter indicates whether the house sync mode is input or + * output. For GET_HOUSE_SYNC_MODE, the current mode will be written + * by RM and returned to the client; for SET_HOUSE_SYNC_MODE, the client + * will write the new mode value to this parameter and pass it to RM + * for execution. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_STATE + * + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_HOUSE_SYNC_MODE (0x30f10187) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_HOUSE_SYNC_MODE_PARAMS_MESSAGE_ID" */ + +typedef struct NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS { + NvU8 houseSyncMode; +} NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS; + +#define NV30F1_CTRL_GSYNC_GET_HOUSE_SYNC_MODE_PARAMS_MESSAGE_ID (0x87U) + +typedef NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS NV30F1_CTRL_GSYNC_GET_HOUSE_SYNC_MODE_PARAMS; + +#define NV30F1_CTRL_CMD_GSYNC_SET_HOUSE_SYNC_MODE (0x30f10188) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_HOUSE_SYNC_MODE_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_SET_HOUSE_SYNC_MODE_PARAMS_MESSAGE_ID (0x88U) + +typedef NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS NV30F1_CTRL_GSYNC_SET_HOUSE_SYNC_MODE_PARAMS; + +#define NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_INPUT (0x00) +#define NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_OUTPUT (0x01) + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_POSSIBLE_REFRESH_RATES + * + * This command queries what refresh rates a GPU could support for a particular hTotal/vTotal. + * RM returns a number of answers in the form of Refresh Rate = (numerator / denominator) * Hz. + * + * Parameters: + * gpuId + * This parameter is set by the client to indicate the gpuId to query + * hTotal + * This parameter specifies what hTotal to query about + * vTotal + * This parameter specifies what vTotal to query about + * minRefreshRatex10000 + * This parameter specifies the minimum refresh rate of answers we are interested in. + * Given in units of 0.0001 Hz + * maxRefreshRatex10000 + * This parameter specifies the maximum refresh rate of answers we are interested in. + * Given in units of 0.0001 Hz + * numFractions + * This parameter is returned by RM and declares how many fractions have been returned. + * fractions + * an array of length numFractions containing: + * numerator + * This parameter is returned by RM and is the numerator of the refresh rate. + * denominator + * This parameter is returned by RM and is the denominator of the refresh rate. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_DEVICE + * NV_ERR_NO_MEMORY + * NV_ERR_GENERIC + * + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_POSSIBLE_REFRESH_RATES (0x30f10189) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_MAX_POSSIBLE_REFRESH_RATE_FRACTIONS 5000 + +#define NV30F1_CTRL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS_MESSAGE_ID (0x89U) + +typedef struct NV30F1_CTRL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS { + NvU32 gpuId; + NvU32 hTotal; + NvU32 vTotal; + NvU32 minRefreshRatex10000; + NvU32 maxRefreshRatex10000; + NvU32 numFractions; + struct { + NV_DECLARE_ALIGNED(NvU64 numerator, 8); + NV_DECLARE_ALIGNED(NvU64 denominator, 8); + } fractions[NV30F1_CTRL_MAX_POSSIBLE_REFRESH_RATE_FRACTIONS]; +} NV30F1_CTRL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS; + +/* _ctrl30f1_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl402c.h b/userspace/sdks/nv570/inc/ctrl/ctrl402c.h new file mode 100644 index 0000000..3d2bb0e --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl402c.h @@ -0,0 +1,971 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl402c.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV40_I2C control commands and parameters */ +#define NV402C_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0x402C, NV402C_CTRL_##cat, idx) + +/* I2C command categories (6 bits) */ +#define NV402C_CTRL_RESERVED (0x00) +#define NV402C_CTRL_I2C (0x01) + + +/* This field specifies the maximum regular port identifier allowed. */ +#define NV402C_CTRL_NUM_I2C_PORTS 16 +/* This temporary field specifies the dynamic port identifier. */ +#define NV402C_CTRL_DYNAMIC_PORT NV_U8_MAX + +/* + * NV402C_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV402C_CTRL_CMD_NULL (0x402c0000) /* finn: Evaluated from "(FINN_NV40_I2C_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV402C_CTRL_I2C_GET_PORT_INFO_IMPLEMENTED + * The port exists on this hardware. + * NV402C_CTRL_I2C_GET_PORT_INFO_DCB_DECLARED + * The port has an entry in the DCB. + * NV402C_CTRL_I2C_GET_PORT_INFO_DDC_CHANNEL + * The port is used to read EDIDs via DDC. + * NV402C_CTRL_I2C_GET_PORT_INFO_CRTC_MAPPED + * The port is accessible via the CRTC register space. + * NV402C_CTRL_I2C_GET_PORT_INFO_VALID + * The port is validated using I2C device. + */ +#define NV402C_CTRL_I2C_GET_PORT_INFO_IMPLEMENTED 0:0 +#define NV402C_CTRL_I2C_GET_PORT_INFO_IMPLEMENTED_NO 0x00 +#define NV402C_CTRL_I2C_GET_PORT_INFO_IMPLEMENTED_YES 0x01 +#define NV402C_CTRL_I2C_GET_PORT_INFO_DCB_DECLARED 1:1 +#define NV402C_CTRL_I2C_GET_PORT_INFO_DCB_DECLARED_NO 0x00 +#define NV402C_CTRL_I2C_GET_PORT_INFO_DCB_DECLARED_YES 0x01 +#define NV402C_CTRL_I2C_GET_PORT_INFO_DDC_CHANNEL 2:2 +#define NV402C_CTRL_I2C_GET_PORT_INFO_DDC_CHANNEL_ABSENT 0x00 +#define NV402C_CTRL_I2C_GET_PORT_INFO_DDC_CHANNEL_PRESENT 0x01 +#define NV402C_CTRL_I2C_GET_PORT_INFO_CRTC_MAPPED 3:3 +#define NV402C_CTRL_I2C_GET_PORT_INFO_CRTC_MAPPED_NO 0x00 +#define NV402C_CTRL_I2C_GET_PORT_INFO_CRTC_MAPPED_YES 0x01 +#define NV402C_CTRL_I2C_GET_PORT_INFO_VALID 4:4 +#define NV402C_CTRL_I2C_GET_PORT_INFO_VALID_NO 0x00 +#define NV402C_CTRL_I2C_GET_PORT_INFO_VALID_YES 0x01 +#define NV402C_CTRL_I2C_GET_PORT_INFO_ALL 4:0 +#define NV402C_CTRL_I2C_GET_PORT_INFO_ALL_DEFAULT 0x00 + +/* + * NV402C_CTRL_CMD_I2C_GET_PORT_INFO + * + * Returns information for the first eight I2C ports. + * + * info + * This parameter is an output from the command and is ignored as an + * input. Each element contains the flags described previously named + * NV402C_CTRL_I2C_GET_PORT_INFO*. Note that the index into the info + * array is one less than the port identifier that would be returned from + * NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID; the port numbers here are + * 0-indexed as opposed to 1-indexed. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + + +#define NV402C_CTRL_CMD_I2C_GET_PORT_INFO (0x402c0101) /* finn: Evaluated from "(FINN_NV40_I2C_I2C_INTERFACE_ID << 8) | NV402C_CTRL_I2C_GET_PORT_INFO_PARAMS_MESSAGE_ID" */ + + + +#define NV402C_CTRL_I2C_GET_PORT_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV402C_CTRL_I2C_GET_PORT_INFO_PARAMS { + NvU8 info[NV402C_CTRL_NUM_I2C_PORTS]; +} NV402C_CTRL_I2C_GET_PORT_INFO_PARAMS; +#define NV402C_CTRL_I2C_INDEX_LENGTH_MAX 4 +#define NV402C_CTRL_I2C_MESSAGE_LENGTH_MAX 4096 + +//! Minimum and maximum valid read/write message length for block process protocol. +#define NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MIN 3 +#define NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX 32 + +/* + * NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE + * A client uses this field to indicate the I2C addressing mode to be + * used. + * Possible values are: + * NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE_7BIT + * The default, this value specifies the master to operate in the + * basic 7-bit addressing mode, which is available on all + * implementations. + * NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE_10BIT + * This I2C mode allows for 10 bits of addressing space and is + * reverse compatible with 7-bit addressing. + */ +#define NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE 0:0 +#define NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE_7BIT (0x00000000) +#define NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE_10BIT (0x00000001) +#define NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE_DEFAULT NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE_7BIT +/* + * NV402C_CTRL_I2C_FLAGS_SPEED_MODE + * A client uses this field to indicate the target speed at which the + * I2C master should attempt to drive the bus. The master may throttle + * its own speed for various reasons, and devices may slow the bus + * using clock-streching. Neither of these possibilities are + * considered failures. + */ +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE 4:1 +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_100KHZ (0x00000000) +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_200KHZ (0x00000001) +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_400KHZ (0x00000002) +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_33KHZ (0x00000003) +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_10KHZ (0x00000004) +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_3KHZ (0x00000005) +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_DEFAULT (0x00000006) +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_300KHZ (0x00000007) + + +/* + * NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE + * A client uses this field to specify a transaction mode. + * Possible values are: + * NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE_NORMAL + * The default, this value indicates to use the normal I2C transaction + * mode which will involve read/write operations depending on client's + * needs. + * NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE_PING + * This value specifies that the device only needs to be pinged. No need + * of performing a complete read/write transaction. This will send a + * single byte to the device to be pinged. On receiving an ACK, we will + * get a confirmation on the device's availability. + */ +#define NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE 11:10 +#define NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE_NORMAL (0x00000000) +#define NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE_PING (0x00000001) +#define NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE_DEFAULT NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE_NORMAL +/*! + * NV402C_CTRL_I2C_FLAGS_RESERVED + * A client must leave this field as 0, as it is reserved for future use. + */ +#define NV402C_CTRL_I2C_FLAGS_RESERVED 31:12 + +/*! + * The following defines specify WAR flags that can be specified during + * I2C Quick Read or Write command (Refer NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW). + * + * _NONE + * No workaround is needed. + * + * _TEST_PORT + * Use this flag to have the client sent a request to test a port instead + * of performing any transaction on it. Transaction type has to be + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW. + */ +#define NV402C_CTRL_I2C_SMBUS_QUICK_RW_WAR_FLAGS 0:0 +#define NV402C_CTRL_I2C_SMBUS_QUICK_RW_WAR_FLAGS_NONE 0x00000000 +#define NV402C_CTRL_I2C_SMBUS_QUICK_RW_WAR_FLAGS_TEST_PORT 0x00000001 + +/*! + * The following defines specify WAR flags that can be specified during + * I2C Register Read or Write buffer command + * (Refer NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW) + * + * _NONE + * No workaround is needed. + * + * _SI1930 + * SI1930 microcontroller register read or write requested by a client. + * Transaction type has to be NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW. + * + * _PX3540 + * Register read from PX3540 or PX3544 device. Transaction type has to be + * NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW and bWrite must be TRUE to + * indicate READ operation + */ +#define NV402C_CTRL_I2C_BUFFER_RW_WAR_FLAGS 1:0 +#define NV402C_CTRL_I2C_BUFFER_RW_WAR_FLAGS_NONE 0x00000000 +#define NV402C_CTRL_I2C_BUFFER_RW_WAR_FLAGS_SI1930 0x00000001 +#define NV402C_CTRL_I2C_BUFFER_RW_WAR_FLAGS_PX3540 0x00000002 + +/*! + * The following defines specify WAR flags that can be specified during + * I2C buffer Read or Write to Multibyte Register + * (Refer NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW) + * + * _NONE + * No workaround is needed. + * + * _NO_AUTO_INC + * This value specifies that the device does not support auto-increment. + * Most devices allow you to write multiple bytes after specifying a + * register address, and the subsequent bytes will go to incremented + * addresses. Without auto-increment, we write a buffer of data as a + * sequence of address-register-value triplets separated by starts. + */ +#define NV402C_CTRL_I2C_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW_WAR_FLAGS 0:0 +#define NV402C_CTRL_I2C_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW_WAR_FLAGS_NONE 0x00000000 +#define NV402C_CTRL_I2C_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW_WAR_FLAGS_NO_AUTO_INC 0x00000001 + +/* + * NV402C_CTRL_CMD_I2C_SYNC + * + * Perform a basic I2C transaction synchronously. + * + * portId + * This field must be specified by the client to indicate the logical + * port/bus for which the transaction is requested. The port identifier + * is one less than the value returned by + * NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID unless that value was 0 (the + * 'dynamic' port). For the 'dynamic' port, this should be 0xFF. Note + * that future versions of the API may obsolete use of the 'dynamic' port; + * please contact the RM if you begin using this portion of the API so we + * can help you migrate when the time comes. + * + * bIsWrite + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + * + * flags + * This parameter specifies optional flags used to control certain modal + * features such as target speed and addressing mode. The currently + * defined fields are described previously; see NV402C_I2C_FLAGS_*. + * + * address + * The address of the I2C slave. The address should be shifted left by + * one. For example, the I2C address 0x50, often used for reading EDIDs, + * would be stored here as 0xA0. This matches the position within the + * byte sent by the master, as the last bit is reserved to specify the + * read or write direction. + * + * indexLength + * This required parameter specifies how many bytes to write as part of the + * first index. If zero is specified, then no index will be sent. + * + * index + * This parameter, required of the client if index is one or more, + * specifies the index to be written. The buffer should be arranged such + * that index[0] will be the first byte sent. + * + * messageLength + * This parameter, required of the client, specifies the number of bytes to + * read or write from the slave after the index is written. + * + * pMessage + * This parameter, required of the client, specifies the data to be written + * to the slave. The buffer should be arranged such that pMessage[0] will + * be the first byte read or written. If the transaction is a read, then + * it will follow the combined format described in the I2C specification. + * If the transaction is a write, the message will immediately follow the + * index without a restart. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_STATE_IN_USE + * NV_ERR_GENERIC, if the I2C transaction fails. + */ +#define NV402C_CTRL_I2C_INDEXED_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV402C_CTRL_I2C_INDEXED_PARAMS { + NvU8 portId; + NvU8 bIsWrite; + NvU16 address; + NvU32 flags; + + NvU32 indexLength; + NvU8 index[NV402C_CTRL_I2C_INDEX_LENGTH_MAX]; + + NvU32 messageLength; + NV_DECLARE_ALIGNED(NvP64 pMessage, 8); +} NV402C_CTRL_I2C_INDEXED_PARAMS; + +#define NV402C_CTRL_CMD_I2C_INDEXED (0x402c0102) /* finn: Evaluated from "(FINN_NV40_I2C_I2C_INTERFACE_ID << 8) | NV402C_CTRL_I2C_INDEXED_PARAMS_MESSAGE_ID" */ + +/* + * NV402C_CTRL_CMD_I2C_GET_PORT_SPEED + * + * Returns information for the I2C ports. + * + * portSpeed + * This parameter is an output from the command and is ignored as an + * input. Each element contains the current I2C speed of the port. + * Note that the index into the info array is one less than the + * port identifier that would be returned from + * NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID; the port numbers here are + * 0-indexed as opposed to 1-indexed. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV402C_CTRL_I2C_GET_PORT_SPEED_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV402C_CTRL_I2C_GET_PORT_SPEED_PARAMS { + NvU32 portSpeed[NV402C_CTRL_NUM_I2C_PORTS]; +} NV402C_CTRL_I2C_GET_PORT_SPEED_PARAMS; + +#define NV402C_CTRL_CMD_I2C_GET_PORT_SPEED (0x402c0103) /* finn: Evaluated from "(FINN_NV40_I2C_I2C_INTERFACE_ID << 8) | NV402C_CTRL_I2C_GET_PORT_SPEED_PARAMS_MESSAGE_ID" */ + +/* + * NV402C_CTRL_I2C_DEVICE_INFO + * + * This structure describes the basic I2C Device information. + * + * type + * This field return the type of device NV_DCB4X_I2C_DEVICE_TYPE_ + * i2cAddress + * This field contains the 7 bit/10 bit address of the I2C device. + * i2cLogicalPort + * This field contains the Logical port of the I2C device. + */ +typedef struct NV402C_CTRL_I2C_DEVICE_INFO { + NvU8 type; + NvU16 i2cAddress; + NvU8 i2cLogicalPort; + NvU8 i2cDevIdx; +} NV402C_CTRL_I2C_DEVICE_INFO; + +/* Maximum number of I2C devices in DCB */ +#define NV402C_CTRL_I2C_MAX_DEVICES 32 + +/* + * NV402C_CTRL_CMD_I2C_TABLE_GET_DEV_INFO + * + * RM Control to get I2C device info from the DCB I2C Devices Table. + * + * i2cDevCount + * The value of this parameter will give the number of + * I2C devices found in DCB. + * + * i2cDevInfo + * For each device found in DCB the control call will write the info + * in this parameter. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV402C_CTRL_I2C_TABLE_GET_DEV_INFO_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV402C_CTRL_I2C_TABLE_GET_DEV_INFO_PARAMS { + NvU8 i2cDevCount; + NV402C_CTRL_I2C_DEVICE_INFO i2cDevInfo[NV402C_CTRL_I2C_MAX_DEVICES]; +} NV402C_CTRL_I2C_TABLE_GET_DEV_INFO_PARAMS; + +#define NV402C_CTRL_CMD_I2C_TABLE_GET_DEV_INFO (0x402c0104) /* finn: Evaluated from "(FINN_NV40_I2C_I2C_INTERFACE_ID << 8) | NV402C_CTRL_I2C_TABLE_GET_DEV_INFO_PARAMS_MESSAGE_ID" */ + +/*! + * The IDs of each type of I2C command available. + */ +typedef enum NV402C_CTRL_I2C_TRANSACTION_TYPE { + /*! + * This transaction type is used to perform the Quick SMBus Read/write command + * on a slave device. No data is sent or received, just used to verify the + * presence of the device. + * Refer SMBus spec 2.0 (section 5.5.1 Quick Command) + * SMBus Quick Write : S Addr|Wr [A] P + * SMBus Quick Read : S Addr|Rd [A] P + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW = 0, + /*! + * This transaction type is used to perform the I2C byte read/write from/to + * a slave device. As per the spec last byte should be NA (Not Acknolwedged) + * by slave. + * Refer I2CBus spec 3.0 (section 9 Fig 11 and Fig 12) or Refer SMBus spec + * 2.0 (section 5.5.2 Send Byte and 5.5.3 Receive Byte). + * I2C Byte Write : S Addr|Wr [A] Data [NA] P + * I2C Byte Read : S Addr|Rd [A] Data NA P + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW = 1, + /*! + * This transaction type is used to perform the I2C block (buffer) + * read/write from/to a slave device. As per the spec last byte should be NA + * (Not Acknolwedged) by slave. + * Refer I2CBus spec 3.0 (section 9 Fig 11 and Fig 12) + * I2C Byte Write : S Addr|Wr [A] Data1 [A]...Data(N-1) [A] DataN [NA] P + * I2C Byte Read : S Addr|Rd [A] Data1 A...Data(N-1) A DataN NA P + * + * Distinction between I2C_BLOCK and SMBUS_BLOCK protocol: + * In I2C Block write it is the slave device (and in I2C Block read it's + * the master device) that determines the number of bytes to transfer by + * asserting the NAK at last bit before stop. This differs from the SMBus + * block mode write command in which the master determines the block + * write transfer size. In I2c Block read there is no limit to maximum size + * of data that could be transferred whereas in SMBus block it is restricted + * to 255 bytes (0xFF). + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW = 2, + /*! + * This transaction type is used to perform the I2C Buffer read/write + * from/to a register of a slave device. It does not send bytecount as + * part of data buffer. + * Not a part of SMBus spec. + * I2C Buffer Write : S Addr|Wr [A] cmd [A] Data1 [A]...DataN[A] P + * I2C Buffer Read : S Addr|Wr [A] cmd [A] Sr Addr|Rd [A] Data1 A... + * DataN-1 A DataN A P + * + * Distinction between SMBUS_BLOCK and I2C_BUFFER protocol: + * In SMBUS_BLOCK Read/write the first byte of data buffer contains the + * count size (The number of bytes to be transferred) and it is restricted + * to 255 bytes whereas in I2C_BUFFER, count size is not sent during the + * transfer and there is no restriction in terms of size. + * + * Distinction between I2C_BLOCK and I2C_BUFFER protocol: + * I2C_BUFFER takes the register address as argument whereas I2C_BLOCK does + * not have any register or command provision. + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW = 3, + /*! + * This transaction type is used to perform the I2C byte read/write from/to + * a slave device + * Refer SMBus spec 2.0 (section 5.5.4 Write Byte and 5.5.5 Read Byte) + * SMBus Byte Write : S Addr|Wr [A] cmd [A] Data [A] P + * SMBus Byte Read : S Addr|Wr [A] cmd [A] Sr Addr|Rd [A] Data A P + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW = 4, + /*! + * This transaction type is used to perform the SMBus byte read/write + * from/to a register of a slave device + * Refer SMBus spec 2.0 (section 5.5.4 Write Word and 5.5.5 Read Word) + * SMBus Word Write : S Addr|Wr [A] cmd [A] DataLow [A] DataHigh [A] P + * SMBus Word Read : S Addr|Wr [A] cmd [A] Sr Addr|Rd [A] DataLow A + * DataHigh A P + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW = 5, + /*! + * This transaction type is used to perform the SMBus Block read/write + * from/to a register of a slave device + * Refer SMBus spec 2.0 (section 5.5.7 Block Write/Read) + * SMBus Block Write : S Addr|Wr [A] cmd [A] ByteCount [A] Data1 [A]... + * DataN-1 [A] DataN[A] P + * SMBus Block Read : S Addr|Wr [A] cmd [A] Sr Addr|Rd [A] ByteCount A + * Data1 A...DataN-1 A DataN A P + * + * Distinction between I2C_BLOCK and SMBUS_BLOCK protocol: + * In I2C Block write it is the slave device (and in I2C Block read it's + * the master device) that determines the number of bytes to transfer by + * asserting the NAK at last bit before stop. This differs from the SMBus + * block mode write/Read command in which the master determines the block + * write transfer size. In I2c Block read/Write there is no limit to maximum + * size of data that could be transferred whereas in SMBus block it is + * restricted to 255 bytes (0xFF). + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW = 6, + /*! + * This transaction type is used to perform the SMBus process call. It sends + * data and waits for the slave to return a value dependent on that data. + * The protocol is simply a SMBus write Word followed by a SMBus Read Word + * without the Read-Word command field and the Write-Word STOP bit. + * Note that there is no STOP condition before the repeated START condition, + * and that a NACK signifies the end of the read transfer. + * + * Refer SMBus spec 2.0 (section 5.5.6 Process Call) + * SMBus Process Call : S Addr|Wr [A] cmd [A] DataLow [A] DataHigh [A] + * Sr Addr|Rd [A] DataLow [A] DataHigh [NA] P + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL = 7, + /*! + * This transaction type is used to perform the SMBus Block Write Block Read + * process call. + * The block write-block read process call is a two-part message. The call + * begins with a slave address and a write condition. After the command code + * the host issues a write byte count (M) that describes how many more bytes + * will be written in the first part of the message. + * If a master has 6 bytes to send, the byte count field will have the value + * 6 (0000 0110b), followed by the 6 bytes of data. The write byte count (M) + * cannot be zero. + * The second part of the message is a block of read data beginning with a + * repeated start condition followed by the slave address and a Read bit. + * The next byte is the read byte count (N), which may differ from the write + * byte count (M). The read byte count (N) cannot be zero. The combined data + * payload must not exceed 32 bytes. + * The byte length restrictions of this process call are summarized as + * follows: + * M >= 1 byte + * N >= 1 byte + * M + N <= 32 bytes + * Note that there is no STOP condition before the repeated START condition, + * and that a NACK signifies the end of the read transfer. + * + * Refer SMBus spec 2.0 (section 5.5.8 Block Write Block Read Process Call) + * SMBus Process Call : S Addr|Wr [A] cmd [A] ByteCount=M [A] Data1 [A]... + * DataN-1 [A] DataM[A] Sr Addr|Rd [A] ByteCount=N [A] + * Data1 [A]...DataN [NA] P + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL = 8, + /*! + * This transaction type is used to perform SMBus buffer read/write + * from/to multiple registers of a slave device known as Auto Increment. + * It is not a part of any standard I2C/SMBus spec but a feature of many + * SMBus devices like EEPROM. + * It is also used for reading a block of bytes from a designated register + * that is specified through the two Comm bytes.of a slave device or writing + * a block of bytes from a designated register of a slave device (Note : The + * command byte in this case could be 0, 2 or 4 Bytes) + * SMBus Multi-Byte Register Block Write : S Addr|Wr [A] cmd1 A cmd 2 [A]... + * cmdN [A] data1 [A] Data2 [A].....DataN [A] P + * SMBus Multi-Byte Register Block Read : S Addr|Rd [A] cmd1 A cmd 2 [A]... + * cmdN [A] data1 [A] Sr Addr [A] Data1 A Data2 A...DataN A P + * + * This transaction type could be also used for those devices which supports + * AUTO_INC. Even though it is frequently related to I2C/SMBus, automatic + * incrementation is not part of any I2C standard but rather a common + * feature found in many I2C devices. What it means is that the device + * maintains in internal pointer which is automatically incremented upon + * data read or write activities and which can be manually set to a fixed + * value. This comes in handy when storing larger amounts of data for + * instance in an ordinary I2C RAM or EEPROM. + * SMBus AUTO_INC Write : S Addr|Wr [A] cmd1 A Data1 [A] Data2 [A]... + * DataN [A] P + * SMBus AUTO_INC Read : S Addr|Rd [A] cmd1 A data1 [A] Sr Addr [A] Data1 A + * Data2 A...DataN A P + * If the device does not support AUTO_INC set warFlags of + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW to + * NV402C_CTRL_I2C_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW_WAR_FLAGS_NO_AUTO_INC. + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW = 9, + /*! + * This transaction type is used to perform the EDID read via DDC. + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC = 10, +} NV402C_CTRL_I2C_TRANSACTION_TYPE; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW. + * + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW { + /*! + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + */ + NvBool bWrite; + /*! + * Transaction specific flags + * (see NV402C_CTRL_I2C_SMBUS_QUICK_RW_WAR_FLAGS_*). + */ + NvU32 warFlags; +} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW. + * + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW { + /*! + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + */ + NvBool bWrite; + /*! + * The main message data. + */ + NvU8 message; +} NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW + * + * Specifies the structure of data filled by the client for I2C transaction + * when the transaction type is NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW. + * + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW { + /*! + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + */ + NvBool bWrite; + /*! + * This parameter specifies the number of bytes to read or + * write from the slave after the register address is written. + */ + NvU32 messageLength; + /*! + * The main message data. + */ + NV_DECLARE_ALIGNED(NvP64 pMessage, 8); +} NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW. + * + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW { + /*! + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + */ + NvBool bWrite; + /*! + * The address of the register. + */ + NvU8 registerAddress; + /*! + * The main message data. + */ + NvU8 message; +} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW. + * + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW { + /*! + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + */ + NvBool bWrite; + /*! + * The address of the register. + */ + NvU8 registerAddress; + /*! + * The main message data. + */ + NvU16 message; +} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BUFFER_RW + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BUFFER_RW. + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW { + /*! + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + */ + NvBool bWrite; + /*! + * Transaction specific flags to be set (see + * NV_NV402C_CTRL_I2C_BUFFER_RW_WAR_FLAGS_*) + */ + NvU32 warFlags; + /*! + * This parameter specifies how many bytes to write as part of the + * register address. If zero is specified, then no index will be sent. + */ + NvU8 registerAddress; + /*! + * This parameter specifies the number of bytes to read or + * write from the slave after the register address is written. + */ + NvU32 messageLength; + /*! + * The main message data. + * C form: NvU8 message[NV402C_CTRL_I2C_MESSAGE_LENGTH_MAX] + */ + NV_DECLARE_ALIGNED(NvP64 pMessage, 8); +} NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW. + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW { + /*! + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + */ + NvBool bWrite; + /*! + * This parameter specifies how many bytes to write as part of the + * register address. If zero is specified, then no index will be sent. + */ + NvU8 registerAddress; + /*! + * This parameter specifies the number of bytes to read or + * write from the slave after the register address is written. + */ + NvU32 messageLength; + /*! + * The main message data. + * C form: NvU8 message[NV402C_CTRL_I2C_MESSAGE_LENGTH_MAX] + */ + NV_DECLARE_ALIGNED(NvP64 pMessage, 8); +} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL. + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL { + /*! + * This parameter specifies how many bytes to write as part of the + * register address. If zero is specified, then no index will be sent. + */ + NvU8 registerAddress; + /*! + * The message data to be written to the slave. + */ + NvU16 writeMessage; + /*! + * The message data to be read from the slave. + */ + NvU16 readMessage; +} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL. + * + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL { + /*! + * This parameter specifies how many bytes to write as part of the + * register address. If zero is specified, then no index will be sent. + */ + NvU8 registerAddress; + /*! + * This parameter specifies the number of bytes to write the the slave + * after the writeByteCount is sent to the slave. + */ + NvU32 writeMessageLength; + /*! + * The message buffer to be written to the slave. + * C form: NvU8 writeMessage[NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX] + */ + NvU8 writeMessage[NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX]; + /*! + * This parameter specifies the number of bytes to read from the slave + * after the readByteCount is sent to the slave. + */ + NvU32 readMessageLength; + /*! + * The message buffer to be read from the slave. + * C form: NvU8 readMessage[NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX] + */ + NvU8 readMessage[NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX]; +} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW. + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW { + /*! + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + */ + NvBool bWrite; + /*! + * Transaction specific flags (see + * NV402C_CTRL_I2C_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW_WAR_FLAGS_*) + */ + NvU32 warFlags; + /*! + * This parameter specifies how many bytes to write as part of the + * register address. If zero is specified, then no index will be sent. + */ + NvU32 indexLength; + /*! + * Optional indexing data; aka register address. + * C form: NvU8 index[NV402C_CTRL_I2C_INDEX_LENGTH_MAX] + */ + NvU8 index[NV402C_CTRL_I2C_INDEX_LENGTH_MAX]; + /*! + * This parameter specifies the number of bytes to read or + * write from the slave after the register address is written. + */ + NvU32 messageLength; + /*! + * The main message data. + * C form: NvU8 message[NV402C_CTRL_I2C_MESSAGE_LENGTH_MAX] + */ + NV_DECLARE_ALIGNED(NvP64 pMessage, 8); +} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC. + * + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC { + /*! + * The segment number of the EDID block which is to be read. + */ + NvU8 segmentNumber; + /*! + * The address of the register. + */ + NvU8 registerAddress; + /*! + * This parameter specifies the number of bytes to read or + * write from the slave after the register address is written. + */ + NvU32 messageLength; + /*! + * The main message data. + * C form: NvU8 message[NV402C_CTRL_I2C_MESSAGE_LENGTH_MAX] + */ + NV_DECLARE_ALIGNED(NvP64 pMessage, 8); +} NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA + * + * This union encapsulates the transaction data corresponding to the + * transaction type enlisted above. + */ +typedef union NV402C_CTRL_I2C_TRANSACTION_DATA { + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW. + */ + NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW smbusQuickData; + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW. + */ + NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW i2cByteData; + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW. + */ + NV_DECLARE_ALIGNED(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW i2cBlockData, 8); + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW. + */ + NV_DECLARE_ALIGNED(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW i2cBufferData, 8); + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW. + */ + NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW smbusByteData; + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW. + */ + NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW smbusWordData; + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW. + */ + NV_DECLARE_ALIGNED(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW smbusBlockData, 8); + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL. + */ + NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL smbusProcessData; + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL. + */ + NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL smbusBlockProcessData; + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW. + */ + NV_DECLARE_ALIGNED(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW smbusMultibyteRegisterData, 8); + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC. + */ + NV_DECLARE_ALIGNED(NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC edidData, 8); +} NV402C_CTRL_I2C_TRANSACTION_DATA; + + +/*! + * NV402C_CTRL_I2C_TRANSACTION_PARAMS + * + * The params data structure for NV402C_CTRL_CMD_I2C_TRANSACTION. + */ +#define NV402C_CTRL_I2C_TRANSACTION_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV402C_CTRL_I2C_TRANSACTION_PARAMS { + /*! + * The logical port ID. + */ + NvU8 portId; + /*! + * This parameter specifies optional flags used to control certain modal + * features such as target speed and addressing mode. The currently + * defined fields are described previously; see NV402C_CTRL_I2C_FLAGS_* + */ + NvU32 flags; + /*! + * The address of the I2C slave. + */ + NvU16 deviceAddress; + /*! + * The transaction type. + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE transType; + /*! + * The transaction data corresponding transaction type. + */ + NV_DECLARE_ALIGNED(NV402C_CTRL_I2C_TRANSACTION_DATA transData, 8); +} NV402C_CTRL_I2C_TRANSACTION_PARAMS; + +#define NV402C_CTRL_CMD_I2C_TRANSACTION (0x402c0105) /* finn: Evaluated from "(FINN_NV40_I2C_I2C_INTERFACE_ID << 8) | NV402C_CTRL_I2C_TRANSACTION_PARAMS_MESSAGE_ID" */ + + +/* _ctrl402c_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl503c.h b/userspace/sdks/nv570/inc/ctrl/ctrl503c.h new file mode 100644 index 0000000..33ffad1 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl503c.h @@ -0,0 +1,200 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl503c.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl503c/ctrl503cbase.h" + +/* + * NV503C_CTRL_CMD_REGISTER_VA_SPACE + * + * This command registers the specified GPU VA space with the given + * NV50_THIRD_PARTY_P2P object, and returns a token that + * uniquely identifies the VA space within the object's parent + * client. + * + * Its parameter structure has the following fields: + * + * hVASpace + * This field specifies the GPU VA space to be registered + * with the third-party P2P object. + * + * vaSpaceToken + * Upon successful completion of the regristration attempt, + * this field holds the new VA space identifier. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INVALID_OBJECT_HANDLE + * NVOS_STATUS_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_RESOURCES + */ +#define NV503C_CTRL_CMD_REGISTER_VA_SPACE (0x503c0102) /* finn: Evaluated from "(FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID << 8) | NV503C_CTRL_REGISTER_VA_SPACE_PARAMS_MESSAGE_ID" */ + +#define NV503C_CTRL_REGISTER_VA_SPACE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV503C_CTRL_REGISTER_VA_SPACE_PARAMS { + NvHandle hVASpace; + NV_DECLARE_ALIGNED(NvU64 vaSpaceToken, 8); +} NV503C_CTRL_REGISTER_VA_SPACE_PARAMS; + + +/* + * NV503C_CTRL_CMD_UNREGISTER_VA_SPACE + * + * This command unregisters (a previously registered) GPU VA space. + * + * Its parameter structure has the following field: + * + * hVASpace + * This field specifies the GPU VA space to be + * unregistered. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV503C_CTRL_CMD_UNREGISTER_VA_SPACE (0x503c0103) /* finn: Evaluated from "(FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID << 8) | NV503C_CTRL_UNREGISTER_VA_SPACE_PARAMS_MESSAGE_ID" */ + +#define NV503C_CTRL_UNREGISTER_VA_SPACE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV503C_CTRL_UNREGISTER_VA_SPACE_PARAMS { + NvHandle hVASpace; +} NV503C_CTRL_UNREGISTER_VA_SPACE_PARAMS; + + +/* + * NV503C_CTRL_CMD_REGISTER_VIDMEM + * + * This command registers a video memory allocation with the given + * NV50_THIRD_PARTY_P2P object. Registration of video memory + * allocations is required if they are to be made accessible via the + * third-party P2P infrastructure. + * + * The vidmem allocation is made available to the users of the third-party P2P + * APIs. It's exposed at the range specified by address and size starting at the + * specified offset within the physical allocation. The same physical memory is + * exposed as the NvRmMapMemoryDma() API would make accessible to the GPU if + * used with equivalent parameters. Notably this API doesn't create any virtual + * mappings nor verifies that any mappings are present, it only registers the + * memory for the purpose of the third-party P2P infrastructure. + * + * The address range specified by address and size cannot overlap any previously + * registered ranges for the given NV50_THIRD_PARTY_P2P object. + * + * Its parameter structure has the following field: + * + * hMemory + * This field specifies the video memory allocation to be + * registered with the third-party P2P object. + * + * address + * The address to register the video memory allocation at. Has to be + * aligned to 64K. + * + * size + * Size in bytes, has to be non-0 and aligned to 64K. Offset + size cannot + * be larger than the vidmem allocation. + * + * offset + * Offset within the video memory allocation where the registered address + * range starts. Has to be aligned to 64K. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_RESOURCES + */ +#define NV503C_CTRL_CMD_REGISTER_VIDMEM (0x503c0104) /* finn: Evaluated from "(FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID << 8) | NV503C_CTRL_REGISTER_VIDMEM_PARAMS_MESSAGE_ID" */ + +#define NV503C_CTRL_REGISTER_VIDMEM_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV503C_CTRL_REGISTER_VIDMEM_PARAMS { + NvHandle hMemory; + NV_DECLARE_ALIGNED(NvU64 address, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NV_DECLARE_ALIGNED(NvU64 offset, 8); +} NV503C_CTRL_REGISTER_VIDMEM_PARAMS; + + +/* + * NV503C_CTRL_CMD_UNREGISTER_VIDMEM + * + * This command unregisters (a previously registered) video memory + * allocation. + * + * Its parameter structure has the following field: + * + * hMemory + * This field specifies the video memory allocation to be + * unregistered. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV503C_CTRL_CMD_UNREGISTER_VIDMEM (0x503c0105) /* finn: Evaluated from "(FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID << 8) | NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS_MESSAGE_ID" */ + +#define NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS { + NvHandle hMemory; +} NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS; + +/* + * NV503C_CTRL_CMD_REGISTER_PID + * + * This command registers the PID of the process that allocated + * the RM client identified by the hClient argument with the + * third-party P2P object, granting this process access to any + * underlying video memory. + * + * Its parameter structure has the following field: + * + * hClient + * This field specifies the client id and should be the handle + * to a valid NV01_ROOT_USER instance. + * + * Possible status values returned are: + * NVOS_STATUS_SUCCES + * NV_ERR_INVALID_ARGUMENT + */ +#define NV503C_CTRL_CMD_REGISTER_PID (0x503c0106) /* finn: Evaluated from "(FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID << 8) | NV503C_CTRL_REGISTER_PID_PARAMS_MESSAGE_ID" */ + +#define NV503C_CTRL_REGISTER_PID_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV503C_CTRL_REGISTER_PID_PARAMS { + NvHandle hClient; +} NV503C_CTRL_REGISTER_PID_PARAMS; + +/* _ctrl503c_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl503c/ctrl503cbase.h b/userspace/sdks/nv570/inc/ctrl/ctrl503c/ctrl503cbase.h new file mode 100644 index 0000000..e6a1d03 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl503c/ctrl503cbase.h @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl503c/ctrl503cbase.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV50_THIRD_PARTY_P2P control commands and parameters */ +#define NV503C_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x503C,NV503C_CTRL_##cat,idx) + +/* NV50_THIRD_PARTY_P2P command categories (6bits) */ +#define NV503C_CTRL_RESERVED (0x00) +#define NV503C_CTRL_P2P (0x01) + +/* + * NV503C_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV503C_CTRL_CMD_NULL (0x503c0000) /* finn: Evaluated from "(FINN_NV50_THIRD_PARTY_P2P_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrl503cbase_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl506f.h b/userspace/sdks/nv570/inc/ctrl/ctrl506f.h new file mode 100644 index 0000000..5173336 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl506f.h @@ -0,0 +1,101 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl506f.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV50_GPFIFO control commands and parameters */ + +#define NV506F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0x506F, NV506F_CTRL_##cat, idx) + +/* NV50_GPFIFO command categories (6bits) */ +#define NV506F_CTRL_RESERVED (0x00) +#define NV506F_CTRL_GPFIFO (0x01) + +/* + * NV506F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV506F_CTRL_CMD_NULL (0x506f0000) /* finn: Evaluated from "(FINN_NV50_CHANNEL_GPFIFO_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* + * NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL + * + * This command resets a channel which was isolated previously by RC recovery. + * + * exceptType + * This input parameter specifies the type of RC error that occurred. See the + * description of the ROBUST_CHANNEL_* values in nverror.h for valid exceptType + * values. info32 field of the error notifier is set with the exceptType when + * the error notifier is signaled. + * + * engineID + * This input parameter specifies the engine to be reset. See the description + * of the NV2080_ENGINE_TYPE values in cl2080.h for valid engineID values. info16 + * field of the error notifier is set with the engineID when the error notifier is + * signaled. + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + + +#define NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL (0x506f0105) /* finn: Evaluated from "(FINN_NV50_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS { + NvU32 exceptType; + NvU32 engineID; +} NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS; + +/* + * NV506F_CTRL_CMD_INTERNAL_RESET_ISOLATED_CHANNEL + * + * This command is an internal command sent from Kernel RM to Physical RM + * to perform the channel reset operations in hardware on an isolated channel + * + * Please see description of NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL for more information. + * + */ +#define NV506F_CTRL_CMD_INTERNAL_RESET_ISOLATED_CHANNEL (0x506f0106) /* finn: Evaluated from "(FINN_NV50_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV506F_CTRL_CMD_INTERNAL_RESET_ISOLATED_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NV506F_CTRL_CMD_INTERNAL_RESET_ISOLATED_CHANNEL_PARAMS_MESSAGE_ID (0x6U) + +typedef NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS NV506F_CTRL_CMD_INTERNAL_RESET_ISOLATED_CHANNEL_PARAMS; + +/* _ctrl506f.h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl5070/ctrl5070base.h b/userspace/sdks/nv570/inc/ctrl/ctrl5070/ctrl5070base.h new file mode 100644 index 0000000..fe28542 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl5070/ctrl5070base.h @@ -0,0 +1,66 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070base.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV5070_DISPLAY control commands and parameters */ + +#define NV5070_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x5070, NV5070_CTRL_##cat, idx) + +/* Display command categories (6bits) */ +#define NV5070_CTRL_RESERVED (0x00) +#define NV5070_CTRL_CHNCTL (0x01) +#define NV5070_CTRL_RG (0x02) +#define NV5070_CTRL_OR (0x04) +#define NV5070_CTRL_INST (0x05) +#define NV5070_CTRL_VERIF (0x06) +#define NV5070_CTRL_SYSTEM (0x07) +#define NV5070_CTRL_EVENT (0x09) + +/* + * NV5070_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV5070_CTRL_CMD_NULL (0x50700000) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + +// This struct must be the first member of all +// 5070 control calls +typedef struct NV5070_CTRL_CMD_BASE_PARAMS { + NvU32 subdeviceIndex; +} NV5070_CTRL_CMD_BASE_PARAMS; + +/* _ctrl5070base_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl5070/ctrl5070chnc.h b/userspace/sdks/nv570/inc/ctrl/ctrl5070/ctrl5070chnc.h new file mode 100644 index 0000000..71e6499 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl5070/ctrl5070chnc.h @@ -0,0 +1,1062 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070chnc.finn +// + +#include "ctrl/ctrl5070/ctrl5070base.h" +#include "ctrl5070common.h" +#include "nvdisptypes.h" + +#define NV5070_CTRL_CMD_NUM_DISPLAY_ID_DWORDS_PER_HEAD 2 + + + +#define NV5070_CTRL_IDLE_CHANNEL_ACCL_NONE (0x00000000) +#define NV5070_CTRL_IDLE_CHANNEL_ACCL_IGNORE_PI (NVBIT(0)) +#define NV5070_CTRL_IDLE_CHANNEL_ACCL_SKIP_NOTIF (NVBIT(1)) +#define NV5070_CTRL_IDLE_CHANNEL_ACCL_SKIP_SEMA (NVBIT(2)) +#define NV5070_CTRL_IDLE_CHANNEL_ACCL_IGNORE_INTERLOCK (NVBIT(3)) +#define NV5070_CTRL_IDLE_CHANNEL_ACCL_IGNORE_FLIPLOCK (NVBIT(4)) +#define NV5070_CTRL_IDLE_CHANNEL_ACCL_TRASH_ONLY (NVBIT(5)) +#define NV5070_CTRL_IDLE_CHANNEL_ACCL_TRASH_AND_ABORT (NVBIT(6)) + +#define NV5070_CTRL_IDLE_CHANNEL_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV5070_CTRL_IDLE_CHANNEL_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 channelClass; + NvU32 channelInstance; + + NvU32 desiredChannelStateMask; + NvU32 accelerators; // For future expansion. Not yet implemented + NvU32 timeout; // For future expansion. Not yet implemented + NvBool restoreDebugMode; +} NV5070_CTRL_IDLE_CHANNEL_PARAMS; + + + +/* + * NV5070_CTRL_CMD_IS_MODE_POSSIBLE + * + * This command is used by DD to determine whether or not a given mode + * is possible given the current nvclk, mclk, dispclk and potentially some + * other parameters that are normally hidden from it. All the parameters + * except IsPossible (output), Force422(output), MinPstate (input/output), + * minPerfLevel (output), CriticalWatermark (output), worstCaseMargin (output), + * and worstCaseDomain (output) params are supplied by the caller. + * + * HeadActive + * Whether or not the params for this head are relevant. + * + * PixelClock + * Frequency: Pixel clk frequency in KHz. + * Adj1000Div1001: 1000/1001 multiplier for pixel clock. + * + * RasterSize + * Width: Total width of the raster. Also referred to as HTotal. + * Height: Total height of the raster. Also referred to as VTotal. + * + * RasterBlankStart + * X: Start of horizontal blanking for the raster. + * Y: Start of vertical blanking for the raster. + * + * RasterBlankEnd + * X: End of horizontal blanking for the raster. + * Y: End of vertical blanking for the raster. + * + * RasterVertBlank2 + * YStart: Start of second blanking for second field for an + * interlaced raster. This field is irrelevant when raster is + * progressive. + * YEnd: End of second blanking for second field for an + * interlaced raster. This field is irrelevant when raster is + * progressive. + * + * Control + * RasterStructure: Whether the raster ir progressive or interlaced. + * + * OutputScaler + * VerticalTaps: Vertical scaler taps. + * HorizontalTaps: Horizontal scaler taps. + * Force422: Whether OutputScaler is operating in 422 mode or not. + * + * ViewportSizeOut + * Width: Width of output viewport. + * Height: Height of output viewport. + * Both the above fields are irrelevant for G80. + * + * ViewportSizeOutMin + * Width: Minimum possible/expected width of output viewport. + * Height: Minimum possible/expected height of output viewport. + * + * ViewportSizeIn + * Width: Width of input viewport. + * Height: Height of input viewport. + * + * Params + * Format: Core channel's pixel format. See the enumerants following + * the variable declaration for possible options. + * SuperSample: Whether to use X1AA or X4AA in core channel. + * This parameter is ignored for G80. + * + * BaseUsageBounds + * Usable: Whether or not the base channel is expected to be used. + * PixelDepth: Maximum pixel depth allowed in base channel. + * SuperSample: Whether or not X4AA is allowed in base channel. + * BaseLutUsage: Base LUT Size + * OutputLutUsage: Output LUT size + * + * OverlayUsageBounds + * Usable: Whether or not the overlay channel is expected to be used. + * PixelDepth: Maximum pixel depth allowed in overlay channel. + * OverlayLutUsage: Overlay LUT Size + * + * BaseLutLo + * Enable: Specifies Core Channel's Base LUT is enable or not. + * Mode: Specifies the LUT Mode. + * NeverYieldToBase: Specifies whether NEVER_YIELD_TO_BASE is enabled or not. + * + * OutputLutLo + * Enable: Specifies Core Channel's Output LUT is enable or not. + * Mode: Specifies the LUT Mode. + * NeverYieldToBase: Specifies whether NEVER_YIELD_TO_BASE is enabled or not. + * + * outputResourcePixelDepthBPP + * Specifies the output pixel depth with scaler mode. + * + * CriticalWatermark + * If MinPState is set to _NEED_MIN_PSTATE, this will return the critical + * watermark level at the minimum Pstate. Otherwise, this will return + * the critical watermark at the level that the IMP calculations are + * otherwise performed at. + * + * pixelReplicateMode + * Specifies the replication mode whether it is X2 or X4. Need to set the parameter + * to OFF if there is no pixel replication. + * + * numSSTLinks + * Number of Single Stream Transport links which will be used by the + * SOR. "0" means to use the number indicated by the most recent + * NV0073_CTRL_CMD_DP_SINGLE_HEAD_MULTI_STREAM_MODE_SST call. + * + * RequestedOperation + * This parameter is used to determine whether + * 1. DD is simplying querying whether or not the specified mode is + * possible (REQUESTED_OPER = _QUERY) or + * 2. DD is about to set the specified mode and RM should make + * appropriate preparations to make the mode possible. DD should + * never pass in a mode that was never indicated by RM as possible + * when DD queried for the possibility of the mode. This + * corresponds to REQUESTED_OPER = _PRE_MODESET. + * 3. DD just finished setting the specified mode. RM can go ahead + * and make changes like lowering the perf level if desired. This + * corresponds to REQUESTED_OPER = _POST_MODESET. This parameter is + * useful when we are at a higher perf level in a mode that's not + * possible at a lower perf level and want to go to a mode that is + * possible even at a lower perf level. In such cases, lowering + * perf level before modeset is complete is dangerous as it will + * cause underflow. RM will wait until the end of modeset to lower + * the perf level. + * + * options + * Specifies a bitmask for options. + * NV5070_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN + * Tells IMP to calculate worstCaseMargin and worstCaseDomain. + * + * IsPossible + * This is the first OUT param for this call. It indicates whether + * or not the current mode is possible. + * + * MinPState + * MinPState is an IO (in/out) variable; it gives the minimum p-state + * value at which the mode is possible on a PStates 2.0 system if the + * parameter is initialized by the caller with _NEED_MIN_PSTATE. If + * _NEED_MIN_PSTATE is not specified, IMP query will just run at the + * max available perf level and return results for that pstate. + * + * If the minimum pstate is required, then MasterLockMode, + * MasterLockPin, SlaveLockMode, and SlaveLockPin must all be + * initialized. + * + * On a PStates 3.0 system, the return value for MinPState is + * undefined, but minPerfLevel can return the minimum IMP v-pstate. + * + * minPerfLevel + * On a PStates 3.0 system, minPerfLevel returns the minimum IMP + * v-pstate at which the mode is possible. On a PStates 2.0 system, + * minPerfLevel returns the minimum perf level at which the mode is + * possible. + * + * minPerfLevel is valid only if MinPState is initialized to + * _NEED_MIN_PSTATE. + * + * worstCaseMargin + * Returns the ratio of available bandwidth to required bandwidth, + * multiplied by NV5070_CTRL_IMP_MARGIN_MULTIPLIER. Available + * bandwidth is calculated in the worst case bandwidth domain, i.e., + * the domain with the least available margin. Bandwidth domains + * include the IMP-relevant clock domains, and possibly other virtual + * bandwidth domains such as AWP. + * + * Note that IMP checks additional parameters besides the bandwidth + * margins, but only the bandwidth margin is reported here, so it is + * possible for a mode to have a more restrictive domain that is not + * reflected in the reported margin result. + * + * This result is not guaranteed to be valid if the mode is not + * possible. + * + * Note also that the result is generally calculated for the highest + * pstate possible (usually P0). But if _NEED_MIN_PSTATE is specified + * with the MinPState parameter, the result will be calculated for the + * min possible pstate (or the highest possible pstate, if the mode is + * not possible). + * + * The result is valid only if + * NV5070_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN is set in + * "options". + * + * worstCaseDomain + * Returns a short text string naming the domain for the margin + * returned in "worstCaseMargin". See "worstCaseMargin" for more + * information. + * + * bUseCachedPerfState + * Indicates that RM should use cached values for the fastest + * available perf level (v-pstate for PStates 3.0 or pstate for + * PStates 2.0) and dispclk. This feature allows the query call to + * execute faster, and is intended to be used, for example, during + * mode enumeration, when many IMP query calls are made in close + * succession, and perf conditions are not expected to change between + * query calls. When IMP has not been queried recently, it is + * recommended to NOT use cached values, in case perf conditions have + * changed and the cached values no longer reflect the current + * conditions. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * + * Assumptions/Limitations: + * - If the caller sends any methods to alter the State Cache, before calling of + * the following functions: + * NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_QUERY_USE_SC + * NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_PRE_MODESET_USE_SC + * NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_POST_MODESET_USE_SC + * the caller must repeatedly issue NV5070_CTRL_CMD_GET_CHANNEL_INFO, and delay until the + * returned channelState is either: + * NV5070_CTRL_CMD_GET_CHANNEL_INFO_STATE_IDLE, + * NV5070_CTRL_CMD_GET_CHANNEL_INFO_STATE_WRTIDLE, or + * NV5070_CTRL_CMD_GET_CHANNEL_INFO_STATE_EMPTY. + * This ensures that all commands have reached the State Cache before RM reads + * them. + * + * + */ +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE (0x50700109) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_QUERY (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_PRE_MODESET (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_POST_MODESET (0x00000002) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_QUERY_USE_SC (0x00000003) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_PRE_MODESET_USE_SC (0x00000004) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_POST_MODESET_USE_SC (0x00000005) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_SUPERVISOR (0x00000007) + +#define NV5070_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN (0x00000001) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_IS_POSSIBLE_NO (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_IS_POSSIBLE_YES (0x00000001) + +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_UNDEFINED (0x00000000) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P0 (0x00000001) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P1 (0x00000002) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P2 (0x00000004) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P3 (0x00000008) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P8 (0x00000100) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P10 (0x00000400) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P12 (0x00001000) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P15 (0x00008000) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_MAX NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P15 +#define NV5070_CTRL_IS_MODE_POSSIBLE_NEED_MIN_PSTATE (0x10101010) +#define NV5070_CTRL_IS_MODE_POSSIBLE_NEED_MIN_PSTATE_DEFAULT (0x00000000) + +#define NV5070_CTRL_IMP_MARGIN_MULTIPLIER (0x00000400) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_HEAD_ACTIVE_NO (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_HEAD_ACTIVE_YES (0x00000001) + +#define NV5070_CTRL_IS_MODE_POSSIBLE_DISPLAY_ID_SKIP_IMP_OUTPUT_CHECK (0xAAAAAAAA) + +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000009) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PIXEL_CLOCK_ADJ1000DIV1001_NO (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PIXEL_CLOCK_ADJ1000DIV1001_YES (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_CONTROL_STRUCTURE_INTERLACED (0x00000001) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_VERTICAL_TAPS_1 (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_VERTICAL_TAPS_2 (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_VERTICAL_TAPS_3 (0x00000002) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_VERTICAL_TAPS_3_ADAPTIVE (0x00000003) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_VERTICAL_TAPS_5 (0x00000004) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_HORIZONTAL_TAPS_1 (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_HORIZONTAL_TAPS_2 (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_HORIZONTAL_TAPS_8 (0x00000002) + +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_SCALER_FORCE422_MODE_DISABLE (0x00000000) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_SCALER_FORCE422_MODE_ENABLE (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_I8 (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_VOID16 (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_VOID32 (0x00000002) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x00000003) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_A8R8G8B8 (0x00000004) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_A2B10G10R10 (0x00000005) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_A8B8G8R8 (0x00000006) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_R5G6B5 (0x00000007) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_A1R5G5B5 (0x00000008) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_SUPER_SAMPLE_X1AA (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_SUPER_SAMPLE_X4AA (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_USABLE_USE_CURRENT (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_USABLE_NO (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_USABLE_YES (0x00000002) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_PIXEL_DEPTH_USE_CURRENT (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_PIXEL_DEPTH_8 (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_PIXEL_DEPTH_16 (0x00000002) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_PIXEL_DEPTH_32 (0x00000003) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_PIXEL_DEPTH_64 (0x00000004) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_SUPER_SAMPLE_USE_CURRENT (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_SUPER_SAMPLE_X1AA (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_SUPER_SAMPLE_X4AA (0x00000002) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_BASE_LUT_USAGE_NONE (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_BASE_LUT_USAGE_257 (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_BASE_LUT_USAGE_1025 (0x00000002) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_USABLE_USE_CURRENT (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_USABLE_NO (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_USABLE_YES (0x00000002) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_USE_CURRENT (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_16 (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_32 (0x00000002) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_64 (0x00000003) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257 (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025 (0x00000002) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000002) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000003) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000004) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000005) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000006) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000007) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000002) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000003) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000004) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000005) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000006) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000007) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PIXEL_REPLICATE_MODE_X4 (0x00000002) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + struct { + NvU32 HeadActive; + struct { + NvU32 Frequency; + + NvU32 Adj1000Div1001; + } PixelClock; + + struct { + NvU32 Width; + NvU32 Height; + } RasterSize; + + struct { + NvU32 X; + NvU32 Y; + } RasterBlankStart; + + struct { + NvU32 X; + NvU32 Y; + } RasterBlankEnd; + + struct { + NvU32 YStart; + NvU32 YEnd; + } RasterVertBlank2; + + struct { + NvU32 Structure; +/* + * Note: For query calls, the lock modes and lock pins are used only if the min + * pstate is required (i.e., if MinPState is set to + * NV5070_CTRL_IS_MODE_POSSIBLE_NEED_MIN_PSTATE). + */ + NV_DISP_LOCK_MODE MasterLockMode; + NV_DISP_LOCK_PIN MasterLockPin; + NV_DISP_LOCK_MODE SlaveLockMode; + NV_DISP_LOCK_PIN SlaveLockPin; + } Control; + + struct { + NvU32 VerticalTaps; + NvU32 HorizontalTaps; + NvBool Force422; + } OutputScaler; + + struct { + NvU32 Width; + NvU32 Height; + } ViewportSizeOut; + + struct { + NvU32 Width; + NvU32 Height; + } ViewportSizeOutMin; + + struct { + NvU32 Width; + NvU32 Height; + } ViewportSizeOutMax; + + struct { + NvU32 Width; + NvU32 Height; + } ViewportSizeIn; + + struct { + NvU32 Format; + NvU32 SuperSample; + } Params; + + struct { + NvU32 Usable; + NvU32 PixelDepth; + NvU32 SuperSample; + NvU32 BaseLutUsage; + NvU32 OutputLutUsage; + } BaseUsageBounds; + + struct { + NvU32 Usable; + NvU32 PixelDepth; + NvU32 OverlayLutUsage; + } OverlayUsageBounds; + + struct { + NvBool Enable; + NvU32 Mode; + NvBool NeverYieldToBase; + } BaseLutLo; + + struct { + NvBool Enable; + NvU32 Mode; + NvBool NeverYieldToBase; + } OutputLutLo; + + NvU32 displayId[NV5070_CTRL_CMD_NUM_DISPLAY_ID_DWORDS_PER_HEAD]; + NvU32 outputResourcePixelDepthBPP; + + NvU32 CriticalWatermark; // in pixels + + } Head[NV5070_CTRL_CMD_MAX_HEADS]; + + struct { + NvU32 owner; + NvU32 protocol; + } Dac[NV5070_CTRL_CMD_MAX_DACS]; + + struct { +// +// owner field is deprecated. In the future, all client calls should set +// ownerMask and bUseSorOwnerMask. bUseSorOwnerMask must be set in order +// to use ownerMask. +// + NvU32 owner; + NvU32 ownerMask; // Head mask owned this sor + + NvU32 protocol; + NvU32 pixelReplicateMode; + + NvU8 numSSTLinks; + } Sor[NV5070_CTRL_CMD_MAX_SORS]; + + NvBool bUseSorOwnerMask; + + struct { + NvU32 owner; + NvU32 protocol; + } Pior[NV5070_CTRL_CMD_MAX_PIORS]; + + + NvU32 RequestedOperation; +// This argument is for VERIF and INTERNAL use only + NvU32 options; + NvU32 IsPossible; + NvU32 MinPState; + + NvU32 minPerfLevel; +// +// Below are the possible Output values for MinPState variable. +// Lower the p-state value higher the power consumption; if no p-states are defined on chip +// then it will return as zero. +// + +// +// Below are the possible input values for MinPstate Variable, by default it calculate +// mode is possible or not at max available p-state and return the same state in that variable. +// + NvU32 worstCaseMargin; + +// +// The calculated margin is multiplied by a constant, so that it can be +// represented as an integer with reasonable precision. "0x400" was chosen +// because it is a power of two, which might allow some compilers/CPUs to +// simplify the calculation by doing a shift instead of a multiply/divide. +// (And 0x400 is 1024, which is close to 1000, so that may simplify visual +// interpretation of the raw margin value.) +// + char worstCaseDomain[8]; + + NvBool bUseCachedPerfState; +} NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS; + +/* + * NV5070_CTRL_CMD_GET_CHANNEL_INFO + * + * This command returns the current channel state. + * + * channelClass + * This field indicates the hw class number (507A-507E) + * + * channelInstance + * This field indicates which of the two instances of the channel + * (in case there are two. ex: base, overlay etc) the cmd is meant for. + * Note that core channel has only one instance and the field should + * be set to 0 for core channel. + * + * channelState + * This field indicates the desired channel state in a mask form that + * is compatible with NV5070_CTRL_CMD_IDLE_CHANNEL. A mask format + * allows clients to check for one from a group of states. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + * + * Display driver uses this call to ensure that all it's methods have + * propagated through hardware's internal fifo + * (NV5070_CTRL_GET_CHANNEL_INFO_STATE_NO_METHOD_PENDING) before it calls + * RM to check whether or not the mode it set up in Assembly State Cache will + * be possible. Note that display driver can not use completion notifier in + * this case because completion notifier is associated with Update and Update + * will propagate the state from Assembly to Armed and when checking the + * possibility of a mode, display driver wouldn't want Armed state to be + * affected. + */ +#define NV5070_CTRL_CMD_GET_CHANNEL_INFO (0x5070010b) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_CHANNEL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_IDLE NV5070_CTRL_CMD_CHANNEL_STATE_IDLE +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_WRTIDLE NV5070_CTRL_CMD_CHANNEL_STATE_WRTIDLE +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_EMPTY NV5070_CTRL_CMD_CHANNEL_STATE_EMPTY +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_FLUSHED NV5070_CTRL_CMD_CHANNEL_STATE_FLUSHED +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_BUSY NV5070_CTRL_CMD_CHANNEL_STATE_BUSY +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_DEALLOC NV5070_CTRL_CMD_CHANNEL_STATE_DEALLOC +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_DEALLOC_LIMBO NV5070_CTRL_CMD_CHANNEL_STATE_DEALLOC_LIMBO +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_LIMBO1 NV5070_CTRL_CMD_CHANNEL_STATE_LIMBO1 +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_LIMBO2 NV5070_CTRL_CMD_CHANNEL_STATE_LIMBO2 +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_FCODEINIT NV5070_CTRL_CMD_CHANNEL_STATE_FCODEINIT +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_FCODE NV5070_CTRL_CMD_CHANNEL_STATE_FCODE +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_VBIOSINIT NV5070_CTRL_CMD_CHANNEL_STATE_VBIOSINIT +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_VBIOSOPER NV5070_CTRL_CMD_CHANNEL_STATE_VBIOSOPER +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_UNCONNECTED NV5070_CTRL_CMD_CHANNEL_STATE_UNCONNECTED +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_INITIALIZE NV5070_CTRL_CMD_CHANNEL_STATE_INITIALIZE +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_SHUTDOWN1 NV5070_CTRL_CMD_CHANNEL_STATE_SHUTDOWN1 +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_SHUTDOWN2 NV5070_CTRL_CMD_CHANNEL_STATE_SHUTDOWN2 +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_NO_METHOD_PENDING (NV5070_CTRL_GET_CHANNEL_INFO_STATE_EMPTY | NV5070_CTRL_GET_CHANNEL_INFO_STATE_WRTIDLE | NV5070_CTRL_GET_CHANNEL_INFO_STATE_IDLE) +#define NV5070_CTRL_CMD_GET_CHANNEL_INFO_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV5070_CTRL_CMD_GET_CHANNEL_INFO_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 channelClass; + NvU32 channelInstance; + NvBool IsChannelInDebugMode; + + NvU32 channelState; +} NV5070_CTRL_CMD_GET_CHANNEL_INFO_PARAMS; + + + +/* + * NV5070_CTRL_CMD_SET_ACCL + * + * This command turns accelerators on and off. The use of this command + * should be restricted as it may have undesirable effects. It's + * purpose is to provide a mechanism for clients to use the + * accelerator bits to get into states that are either not detectable + * by the RM or may take longer to reach than we think is reasonable + * to wait in the RM. + * + * NV5070_CTRL_CMD_GET_ACCL + * + * This command queries the current state of the accelerators. + * + * channelClass + * This field indicates the hw class number (507A-507E) + * + * channelInstance + * This field indicates which of the two instances of the channel + * (in case there are two. ex: base, overlay etc) the cmd is meant for. + * Note that core channel has only one instance and the field should + * be set to 0 for core channel. + * + * accelerators + * Accelerators to be set in the SET_ACCEL command. Returns the + * currently set accelerators on the GET_ACCEL command. + * + * accelMask + * A mask to specify which accelerators to change with the + * SET_ACCEL command. This field does nothing in the GET_ACCEL + * command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_CHANNEL + * NV_ERR_INVALID_OWNER + * NV_ERR_GENERIC + * + */ + +#define NV5070_CTRL_CMD_SET_ACCL (0x5070010c) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_SET_ACCL_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_ACCL (0x5070010d) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_GET_ACCL_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_ACCL_NONE NV5070_CTRL_IDLE_CHANNEL_ACCL_NONE +#define NV5070_CTRL_ACCL_IGNORE_PI NV5070_CTRL_IDLE_CHANNEL_ACCL_IGNORE_PI +#define NV5070_CTRL_ACCL_SKIP_NOTIF NV5070_CTRL_IDLE_CHANNEL_ACCL_SKIP_NOTIF +#define NV5070_CTRL_ACCL_SKIP_SEMA NV5070_CTRL_IDLE_CHANNEL_ACCL_SKIP_SEMA +#define NV5070_CTRL_ACCL_IGNORE_INTERLOCK NV5070_CTRL_IDLE_CHANNEL_ACCL_IGNORE_INTERLOCK +#define NV5070_CTRL_ACCL_IGNORE_FLIPLOCK NV5070_CTRL_IDLE_CHANNEL_ACCL_IGNORE_FLIPLOCK +#define NV5070_CTRL_ACCL_TRASH_ONLY NV5070_CTRL_IDLE_CHANNEL_ACCL_TRASH_ONLY +#define NV5070_CTRL_ACCL_TRASH_AND_ABORT NV5070_CTRL_IDLE_CHANNEL_ACCL_TRASH_AND_ABORT +#define NV5070_CTRL_SET_ACCL_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV5070_CTRL_SET_ACCL_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 channelClass; + NvU32 channelInstance; + + NvU32 accelerators; + NvU32 accelMask; +} NV5070_CTRL_SET_ACCL_PARAMS; +#define NV5070_CTRL_GET_ACCL_PARAMS_MESSAGE_ID (0xDU) + +typedef NV5070_CTRL_SET_ACCL_PARAMS NV5070_CTRL_GET_ACCL_PARAMS; + + + +/* + * NV5070_CTRL_CMD_GET_PINSET_COUNT + * + * Get number of pinsets on this GPU. + * + * pinsetCount [out] + * Number of pinsets on this GPU is returned in this parameter. + * This count includes pinsets that are not connected. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV5070_CTRL_CMD_GET_PINSET_COUNT (0x50700115) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_GET_PINSET_COUNT_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_GET_PINSET_COUNT_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV5070_CTRL_GET_PINSET_COUNT_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 pinsetCount; +} NV5070_CTRL_GET_PINSET_COUNT_PARAMS; + +/* + * NV5070_CTRL_CMD_GET_PINSET_PEER + * + * Retrieve the pinset/GPU that is connected to the specified pinset on + * this GPU. + * + * pinset [in] + * Pinset on this GPU for which peer info is to be returned must be + * specified in this parameter. + * + * peerGpuId [out] + * Instance of the GPU on the other side of the connection is + * returned in this parameter. + * + * peerPinset [out] + * Pinset on the other side of the connection is returned in this + * parameter. If there is no connection then the value is + * NV5070_CTRL_CMD_GET_PINSET_PEER_PEER_PINSET_NONE. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV5070_CTRL_CMD_GET_PINSET_PEER (0x50700116) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_GET_PINSET_PEER_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_PINSET_PEER_PEER_GPUINSTANCE_NONE (0xffffffff) + +#define NV5070_CTRL_CMD_GET_PINSET_PEER_PEER_PINSET_NONE (0xffffffff) + +#define NV5070_CTRL_GET_PINSET_PEER_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV5070_CTRL_GET_PINSET_PEER_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 pinset; + + NvU32 peerGpuInstance; + NvU32 peerPinset; +} NV5070_CTRL_GET_PINSET_PEER_PARAMS; + +/* + * NV5070_CTRL_CMD_SET_RMFREE_FLAGS + * + * This command sets the flags for an upcoming call to RmFree(). + * After the RmFree() API runs successfully or not, the flags are cleared. + * + * flags + * This parameter holds the NV0000_CTRL_GPU_SET_RMFREE_FLAGS_* + * flags to be passed for the next RmFree() command only. + * The flags can be one of those: + * - NV0000_CTRL_GPU_SET_RMFREE_FLAGS_NONE: + * explicitly clears the flags + * - NV0000_CTRL_GPU_SET_RMFREE_FLAGS_FREE_PRESERVES_HW: + * instructs RmFree() to preserve the HW configuration. After + * RmFree() is run this flag is cleared. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV5070_CTRL_CMD_SET_RMFREE_FLAGS (0x50700117) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_SET_RMFREE_FLAGS_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_SET_RMFREE_FLAGS_NONE 0x00000000 +#define NV5070_CTRL_SET_RMFREE_FLAGS_PRESERVE_HW 0x00000001 +#define NV5070_CTRL_SET_RMFREE_FLAGS_PARAMS_MESSAGE_ID (0x17U) + +typedef struct NV5070_CTRL_SET_RMFREE_FLAGS_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 flags; +} NV5070_CTRL_SET_RMFREE_FLAGS_PARAMS; + + +/* + * NV5070_CTRL_CMD_IMP_SET_GET_PARAMETER + * + * This command allows to set or get certain IMP parameters. Change of + * values take effect on next modeset and is persistent across modesets + * until the driver is unloaded or user changes the override. + * + * index + * One of NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_XXX defines - + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IMP_ENABLE + * Only supports "get" operation. If FALSE, IMP is being bypassed and + * all Is Mode Possible queries are answered with "mode is possible" + * and registers normally set by IMP are not changed from their defaults. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED + * Should IMP consider using ASR. ASR won't be allowed unless it is set to + * "allowed" through both _IS_ASR_ALLOWED and _IS_ASR_ALLOWED_PER_PSTATE. + * Note that IMP will not run ASR and MSCG at the same time. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED_PER_PSTATE + * Should IMP consider using ASR when this pstate is being used. ASR won't + * be allowed unless it is set to "allowed" through both + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED and + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED_PER_PSTATE. + * So when NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED + * returns FALSE, IMP won't consider ASR for any p-state. Note that IMP + * will not run ASR and MSCG at the same time. This function is valid + * only on PStates 2.0 systems. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_MSCG_ALLOWED_PER_PSTATE + * Should IMP consider using MSCG when this pstate is being used. MSCG + * won't be allowed if the MSCG feature isn't enabled even if we set to + * "allowed" through + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_MSCG_ALLOWED_PER_PSTATE. + * Use NV2080_CTRL_CMD_MC_QUERY_POWERGATING_PARAMETER to query if MSCG is + * supported and enabled. Note that IMP will not run ASR and MSCG at the + * same time. This function is valid only on PStates 2.0 systems. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_STUTTER_FEATURE_PER_PSTATE + * Only supports "get" operation. Returns which stutter feature is being + * engaged in hardware when running on the given pstate. Valid values are: + * NV5070_CTRL_IMP_STUTTER_FEATURE_NONE + * This value indicates no stutter feature is enabled. + * NV5070_CTRL_IMP_STUTTER_FEATURE_ASR + * This value indicates ASR is the current enabled stutter feature. + * NV5070_CTRL_IMP_STUTTER_FEATURE_MSCG + * This value indicates MSCG is the current enabled stutter feature. + * Note that system will not run ASR and MSCG at the same time. This + * function is valid only on PStates 2.0 systems. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_STUTTER_FEATURE_PREDICTED_EFFICIENCY_PER_PSTATE + * Only supports "get" operation. Returns the efficiency which IMP + * predicted for the engaged stutter feature (ASR or MSCG) when running + * on the given pstate. Normally, the actual efficiency should be higher + * than the calculated predicted efficiency. For MSCG, the predicted + * efficiency assumes no mempool compression. If compression is enabled + * with MSCG, the actual efficiency may be significantly higher. Returns + * 0 if no stutter feature is running. On PStates 3.0 systems, the + * pstateApi parameter is ignored, and the result is returned for the min + * IMP v-pstate possible. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS + * Only supports "get" operation. Returns information about what the possible + * mclk switch is. Valid fields are: + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_POSSIBLE + * This field is not head-specific and indicates if mclk switch is + * possible with the current mode. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_OVERRIDE_MEMPOOL + * This field is not head-specific and indicates if mclk switch is + * possible with the nominal mempool settings (_NO) or if special + * settings are required in order for mclk switch to be possible (_YES). + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_MID_WATERMARK + * Each head has its own setting for this field. If this field is + * set to _YES, then the specified head will allow mclk switch to + * begin if mempool occupancy exceeds the MID_WATERMARK setting. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_DWCF + * Each head has its own setting for this field. If this field is + * set to _YES, then the specified head will allow mclk switch to + * begin if the head is in its DWCF interval, and the mempool + * occupancy is greater than or equal to the DWCF watermark. + * Note: If neither _MID_WATERMARK nor _DWCF is set to _YES, then the + * specified head is ignored when determining when it is OK to start an + * mclk switch. Mclk switch must be allowed (or ignored) by all heads + * before an mclk switch will actually begin. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_FORCE_MIN_MEMPOOL + * Should min mempool be forced. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MEMPOOL_COMPRESSION + * Should mempool compression be enabled. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_CURSOR_SIZE + * The cursor size (in horizontal pixels) used by IMP (rather than the + * actual cursor size) for its computation. + * A maximum value is in place for what can be set. It can be queried + * after resetting the value - it gets reset to the maximum possible + * value. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_ENABLE + * This is to Enable/Disable ISO FB Latency Test. + * The test records the max ISO FB latency for all heads during the test period (excluding modeset time). + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_WC_TOTAL_LATENCY + * This is used to retrieve calculated wcTotalLatency of ISO FB Latency Test. + * wcTotalLatency is the worst case time for a request's data to come back after the request is issued. + * It is the sum of IMP calculated FbLatency and stream delay. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_MAX_LATENCY + * This is used to retrieve the max latency among all heads during the whole ISO FB Latency Test. + * The max latency can be used to compare with the wcTotalLatency we calculated. + * It decides whether the ISO FB Latency Test is passed or not. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_MAX_TEST_PERIOD + * This is used to retrieve the max test period during the whole ISO FB Latency Test. + * By experimental result, the test period should be at least 10 secs to approximate the + * worst case Fb latency in real situation. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_GLITCHLESS_MODESET_ENABLE + * This enables or disables glitchless modesets. Modesets can be + * glitchless if: + * (1) There are no raster timing changes, and + * (2) The resource requirements of all bandwidth clients are either not + * changing, or they are all changing in the same direction (all + * increasing or all decreasing). + * If glitchless modeset is disabled, or is not possible, heads will be + * blanked during the modeset transition. + * pstateApi + * NV2080_CTRL_PERF_PSTATES_PXXX value. + * Required for NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED_PER_PSTATE, + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_MSCG_ALLOWED_PER_PSTATE, + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_STUTTER_FEATURE_PER_PSTATE and + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_STUTTER_FEATURE_PREDICTED_EFFICIENCY_PER_PSTATE + * on PStates 2.0 systems. For other indices must be + * NV2080_CTRL_PERF_PSTATES_UNDEFINED. Not used on PStates 3.0 systems. + * head + * Head index, which is required when querying Mclk switch feature. + * (index = NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS) + * operation + * NV5070_CTRL_IMP_SET_GET_PARAMETER_OPERATION_GET + * Indicates a "get" operation. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_OPERATION_SET + * Indicates a "set" operation. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_OPERATION_RESET + * Indicates a "reset" operation. This operation will reset the values for + * all indices to their RM defaults. + * value + * Value for new setting of a "set" operation, or the returned value of a + * "get" operation; for enable/disable operations, "enable" is non-zero, + * and "disable" is zero. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_POINTER + * NV_ERR_INVALID_INDEX specified index is not supported + * NV_ERR_INSUFFICIENT_RESOURCES cannot handle any more overrides + * NV_ERR_INVALID_OBJECT the struct needed to get the specified information + * is not marked as valid + * NV_ERR_INVALID_STATE the parameter has been set but resetting will + * not be possible + */ +#define NV5070_CTRL_CMD_IMP_SET_GET_PARAMETER (0x50700118) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_IMP_SET_GET_PARAMETER_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV5070_CTRL_IMP_SET_GET_PARAMETER_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 index; + NvU32 pstateApi; + NvU32 head; + NvU32 operation; + NvU32 value; +} NV5070_CTRL_IMP_SET_GET_PARAMETER_PARAMS; + +/* valid operation values */ +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_OPERATION_GET 0 +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_OPERATION_SET 1 +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_OPERATION_RESET 2 + +/* valid index value */ +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_NONE (0x00000000) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IMP_ENABLE (0x00000001) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED (0x00000002) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED_PER_PSTATE (0x00000003) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_MSCG_ALLOWED_PER_PSTATE (0x00000004) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_STUTTER_FEATURE_PER_PSTATE (0x00000005) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_STUTTER_FEATURE_PREDICTED_EFFICIENCY_PER_PSTATE (0x00000006) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS (0x00000007) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_FORCE_MIN_MEMPOOL (0x00000008) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MEMPOOL_COMPRESSION (0x00000009) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_CURSOR_SIZE (0x0000000A) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_ENABLE (0x0000000B) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_WC_TOTAL_LATENCY (0x0000000C) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_MAX_LATENCY (0x0000000D) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_MAX_TEST_PERIOD (0x0000000E) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_GLITCHLESS_MODESET_ENABLE (0x0000000F) + +/* valid NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOHUB_STUTTER_FEATURE values */ +#define NV5070_CTRL_IMP_STUTTER_FEATURE_NONE 0 +#define NV5070_CTRL_IMP_STUTTER_FEATURE_ASR 1 +#define NV5070_CTRL_IMP_STUTTER_FEATURE_MSCG 2 + +/* valid NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE values */ +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_POSSIBLE 0:0 +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_POSSIBLE_NO (0x00000000) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_POSSIBLE_YES (0x00000001) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_OVERRIDE_MEMPOOL 1:1 +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_OVERRIDE_MEMPOOL_NO (0x00000000) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_OVERRIDE_MEMPOOL_YES (0x00000001) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_MID_WATERMARK 2:2 +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_MID_WATERMARK_NO (0x00000000) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_MID_WATERMARK_YES (0x00000001) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_DWCF 3:3 +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_DWCF_NO (0x00000000) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_DWCF_YES (0x00000001) + +/* + * NV5070_CTRL_CMD_SET_MEMPOOL_WAR_FOR_BLIT_TEARING + * + * This command engages the WAR for blit tearing caused by huge mempool size and + * mempool compression. The EVR in aero off mode uses scanline info to predict + * where the scanline will be at a later time. Since RG scanline is used to perform + * front buffer blits and isohub buffers large amount of display data it may have + * fetched several lines of data ahead of where the RG is scanning out leading to + * video tearing. The WAR for this problem is to reduce the amount of data fetched. + * + * base + * This struct must be the first member of all 5070 control calls containing + * the subdeviceIndex. + * bEngageWAR + * Indicates if mempool WAR has to be engaged or disengaged. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV5070_CTRL_CMD_SET_MEMPOOL_WAR_FOR_BLIT_TEARING (0x50700119) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_SET_MEMPOOL_WAR_FOR_BLIT_TEARING_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_SET_MEMPOOL_WAR_FOR_BLIT_TEARING_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV5070_CTRL_SET_MEMPOOL_WAR_FOR_BLIT_TEARING_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvBool bEngageWAR; +} NV5070_CTRL_SET_MEMPOOL_WAR_FOR_BLIT_TEARING_PARAMS; +typedef struct NV5070_CTRL_SET_MEMPOOL_WAR_FOR_BLIT_TEARING_PARAMS *PNV5070_CTRL_SET_MEMPOOL_WAR_FOR_BLIT_TEARING_PARAMS; + +/* _ctrl5070chnc_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl5070/ctrl5070common.h b/userspace/sdks/nv570/inc/ctrl/ctrl5070/ctrl5070common.h new file mode 100644 index 0000000..75d7295 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl5070/ctrl5070common.h @@ -0,0 +1,79 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070common.finn +// + + + +#define NV5070_CTRL_CMD_CHANNEL_STATE_IDLE NVBIT(0) +#define NV5070_CTRL_CMD_CHANNEL_STATE_WRTIDLE NVBIT(1) +#define NV5070_CTRL_CMD_CHANNEL_STATE_QUIESCENT1 NVBIT(2) +#define NV5070_CTRL_CMD_CHANNEL_STATE_QUIESCENT2 NVBIT(3) +#define NV5070_CTRL_CMD_CHANNEL_STATE_EMPTY NVBIT(4) +#define NV5070_CTRL_CMD_CHANNEL_STATE_FLUSHED NVBIT(5) +#define NV5070_CTRL_CMD_CHANNEL_STATE_BUSY NVBIT(6) +#define NV5070_CTRL_CMD_CHANNEL_STATE_DEALLOC NVBIT(7) +#define NV5070_CTRL_CMD_CHANNEL_STATE_DEALLOC_LIMBO NVBIT(8) +#define NV5070_CTRL_CMD_CHANNEL_STATE_LIMBO1 NVBIT(9) +#define NV5070_CTRL_CMD_CHANNEL_STATE_LIMBO2 NVBIT(10) +#define NV5070_CTRL_CMD_CHANNEL_STATE_FCODEINIT NVBIT(11) +#define NV5070_CTRL_CMD_CHANNEL_STATE_FCODE NVBIT(12) +#define NV5070_CTRL_CMD_CHANNEL_STATE_VBIOSINIT NVBIT(13) +#define NV5070_CTRL_CMD_CHANNEL_STATE_VBIOSOPER NVBIT(14) +#define NV5070_CTRL_CMD_CHANNEL_STATE_UNCONNECTED NVBIT(15) +#define NV5070_CTRL_CMD_CHANNEL_STATE_INITIALIZE NVBIT(16) +#define NV5070_CTRL_CMD_CHANNEL_STATE_SHUTDOWN1 NVBIT(17) +#define NV5070_CTRL_CMD_CHANNEL_STATE_SHUTDOWN2 NVBIT(18) +#define NV5070_CTRL_CMD_CHANNEL_STATE_INIT NVBIT(19) + +#define NV5070_CTRL_CMD_MAX_HEADS 4U +#define NV5070_CTRL_CMD_MAX_DACS 4U +#define NV5070_CTRL_CMD_MAX_SORS 8U +#define NV5070_CTRL_CMD_MAX_PIORS 4U + +#define NV5070_CTRL_CMD_OR_OWNER_NONE (0xFFFFFFFFU) +#define NV5070_CTRL_CMD_OR_OWNER_HEAD(i) (i) +#define NV5070_CTRL_CMD_OR_OWNER_HEAD__SIZE_1 NV5070_CTRL_CMD_MAX_HEADS + +#define NV5070_CTRL_CMD_SOR_OWNER_MASK_NONE (0x00000000U) +#define NV5070_CTRL_CMD_SOR_OWNER_MASK_HEAD(i) (1 << i) + +#define NV5070_CTRL_CMD_DAC_PROTOCOL_RGB_CRT (0x00000000U) + + + +#define NV5070_CTRL_CMD_SOR_PROTOCOL_SINGLE_TMDS_A (0x00000000U) +#define NV5070_CTRL_CMD_SOR_PROTOCOL_SINGLE_TMDS_B (0x00000001U) +#define NV5070_CTRL_CMD_SOR_PROTOCOL_DUAL_TMDS (0x00000002U) +#define NV5070_CTRL_CMD_SOR_PROTOCOL_LVDS_CUSTOM (0x00000003U) +#define NV5070_CTRL_CMD_SOR_PROTOCOL_DP_A (0x00000004U) +#define NV5070_CTRL_CMD_SOR_PROTOCOL_DP_B (0x00000005U) +#define NV5070_CTRL_CMD_SOR_PROTOCOL_SUPPORTED (0xFFFFFFFFU) + +#define NV5070_CTRL_CMD_PIOR_PROTOCOL_EXT_TMDS_ENC (0x00000000U) + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl5070/ctrl5070impoverrides.h b/userspace/sdks/nv570/inc/ctrl/ctrl5070/ctrl5070impoverrides.h new file mode 100644 index 0000000..0f2864a --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl5070/ctrl5070impoverrides.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070impoverrides.finn +// + + + + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl5070/ctrl5070or.h b/userspace/sdks/nv570/inc/ctrl/ctrl5070/ctrl5070or.h new file mode 100644 index 0000000..eefafa4 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl5070/ctrl5070or.h @@ -0,0 +1,448 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070or.finn +// + +#include "ctrl5070common.h" +#include "ctrl/ctrl5070/ctrl5070base.h" + +/* + * NV5070_CTRL_CMD_GET_SOR_OP_MODE + * + * This command returns current settings for the specified SOR. + * + * orNumber + * The OR number for which the operating mode needs to be read. + * + * category + * Whether LVDS or CSTM setting are desired. + * + * puTxda + * Status of data pins of link A + * + * puTxdb + * Status of data pins of link B + * + * puTxca + * Status of link A clock + * + * puTxcb + * Status of link B clock + * + * upper + * Whether LVDS bank A is the upper, odd, or first pixel. + * + * mode + * Current protocol. + * + * linkActA + * Status of link B clock + * + * linkActB + * Status of link B clock + * + * lvdsEn + * Output driver configuration. + * + * lvdsDual + * Whether LVDS dual-link mode is turned on or not. + * + * dupSync + * Whether DE, HSYNC, and VSYNC are used for encoding instead of + * RES, CNTLE, and CNTLF. + * + * newMode + * Whether new or old mode is being used. + * + * balanced + * Whether balanced encoding is enabled. + * + * plldiv + * Feedback divider for the hi-speed pll + * + * rotClk + * Skew of TXC clock. + * + * rotDat + * How much are the 8 bits of each color channel rotated by + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE (0x50700422) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_SOR_OP_MODE_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_CATEGORY 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_CATEGORY_LVDS 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_CATEGORY_CUSTOM 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_0 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_0_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_0_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_1 1:1 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_1_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_1_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_2 2:2 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_2_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_2_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_3 3:3 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_3_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_3_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_0 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_0_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_0_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_1 1:1 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_1_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_1_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_2 2:2 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_2_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_2_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_3 3:3 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_3_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_3_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXCA 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXCA_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXCA_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXCB 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXCB_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXCB_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_UPPER 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_UPPER_UPPER_RESET 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_MODE 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_MODE_LVDS 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_MODE_TMDS 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LINKACTA 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LINKACTA_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LINKACTA_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LINKACTB 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LINKACTB_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LINKACTB_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LVDS_EN 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LVDS_EN_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LVDS_EN_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LVDS_DUAL 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LVDS_DUAL_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LVDS_DUAL_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_DUP_SYNC 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_DUP_SYNC_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_DUP_SYNC_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_NEW_MODE 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_NEW_MODE_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_NEW_MODE_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_BALANCED 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_BALANCED_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_BALANCED_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PLLDIV 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PLLDIV_BY_7 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PLLDIV_BY_10 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_ROTCLK 3:0 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_ROTDAT 2:0 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NV5070_CTRL_CMD_GET_SOR_OP_MODE_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 orNumber; + + NvU32 category; + NvU32 puTxda; + NvU32 puTxdb; + NvU32 puTxca; + NvU32 puTxcb; + NvU32 upper; + NvU32 mode; + NvU32 linkActA; + NvU32 linkActB; + NvU32 lvdsEn; + NvU32 lvdsDual; + NvU32 dupSync; + NvU32 newMode; + NvU32 balanced; + NvU32 plldiv; + NvU32 rotClk; + NvU32 rotDat; +} NV5070_CTRL_CMD_GET_SOR_OP_MODE_PARAMS; + + +/* + * NV5070_CTRL_CMD_SET_SOR_OP_MODE + * + * This command applies the specified settings to the specified SOR. + * + * orNumber + * The OR number for which the operating mode needs to be read. + * Note that if DCB doesn't report LVDS for the specified orNumber, + * the call will return failure. + * + * category + * Whether LVDS or CSTM settings are specified. + * + * puTxda + * Used to enable or disable the data pins of link A. + * + * puTxdb + * Used to enable or disable the data pins of link B. + * + * puTxca + * Used to enable or disable link A clock. + * + * puTxcb + * Used to enable or disable link B clock. + * + * upper + * Whether LVDS bank A should be the upper, odd, or first pixel. + * + * mode + * What protocol (LVDS/TMDS to use). + * + * linkActA + * Used to enable or disable the digital logic of link A. + * + * linkActB + * Used to enable or disable the digital logic of link B. + * + * lvdsEn + * Output driver configuration. + * + * lvdsDual + * Whether to turn on LVDS dual-link mode. + * + * dupSync + * Whether to use DE, HSYNC, and VSYNC for encoding instead of + * RES, CNTLE, and CNTLF. + * + * newMode + * Whether to use new or old mode. + * + * balanced + * Whether or not to use balanced encoding. + * + * plldiv + * Feedback divider to use for the hi-speed pll. + * + * rotClk + * How much to skew TXC clock. + * + * rotDat + * How much to rotate the 8 bits of each color channel by. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE (0x50700423) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_SOR_OP_MODE_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_CATEGORY 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_CATEGORY_LVDS 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_CATEGORY_CUSTOM 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_0 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_0_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_0_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_1 1:1 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_1_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_1_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_2 2:2 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_2_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_2_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_3 3:3 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_3_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_3_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_0 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_0_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_0_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_1 1:1 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_1_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_1_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_2 2:2 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_2_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_2_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_3 3:3 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_3_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_3_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXCA 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXCA_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXCA_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXCB 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXCB_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXCB_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_UPPER 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_UPPER_UPPER_RESET 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_MODE 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_MODE_LVDS 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_MODE_TMDS 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LINKACTA 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LINKACTA_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LINKACTA_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LINKACTB 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LINKACTB_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LINKACTB_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LVDS_EN 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LVDS_EN_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LVDS_EN_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LVDS_DUAL 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LVDS_DUAL_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LVDS_DUAL_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_DUP_SYNC 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_DUP_SYNC_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_DUP_SYNC_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_NEW_MODE 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_NEW_MODE_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_NEW_MODE_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_BALANCED 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_BALANCED_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_BALANCED_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PLLDIV 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PLLDIV_BY_7 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PLLDIV_BY_10 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_ROTCLK 3:0 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_ROTDAT 2:0 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PARAMS_MESSAGE_ID (0x23U) + +typedef struct NV5070_CTRL_CMD_SET_SOR_OP_MODE_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 orNumber; + + NvU32 category; + NvU32 puTxda; + NvU32 puTxdb; + NvU32 puTxca; + NvU32 puTxcb; + NvU32 upper; + NvU32 mode; + NvU32 linkActA; + NvU32 linkActB; + NvU32 lvdsEn; + NvU32 lvdsDual; + NvU32 dupSync; + NvU32 newMode; + NvU32 balanced; + NvU32 plldiv; + NvU32 rotClk; + NvU32 rotDat; +} NV5070_CTRL_CMD_SET_SOR_OP_MODE_PARAMS; + +/* + * NV5070_CTRL_CMD_SET_SOR_FLUSH_MODE + * + * Set the given SOR number into flush mode in preparation for DP link training. + * + * orNumber [in] + * The SOR number to set into flush mode. + * + * bEnable [in] + * Whether to enable or disable flush mode on this SOR. + * + * bImmediate [in] + * If set to true, will enable flush in immediate mode. + * If not, will enable flush in loadv mode. + * NOTE: We do not support exit flush in LoadV mode. + * + * headMask [in] + * Optional. If set brings only the heads in the head mask out of flush + * OR will stay in flush mode until last head is out of flush mode. + * Caller can use _HEAD__ALL to specify all the heads are to be brought out. + * NOTE: headMask would be considered only while exiting from flush mode. + * + * bForceRgDiv [in] + * If set forces RgDiv. Should be used only for HW/SW testing + * + * bUseBFM [in] + * If Set then it mean we are using BFM else executing on non-BFM paltforms. + * + * bFireAndForget [in] + * Fire the flush mode & perform post-processing without waiting for it + * to be done. This is required for special cases like GC5 where we have + * ELV blocked, RG stall & we trigger flush for one shot mode & then do + * a modeset by disabling it without actually waiting for it to get + * disabled. We will not get any vblank interrupt in this case as we have + * stalled RG. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV5070_CTRL_CMD_SET_SOR_FLUSH_MODE (0x50700457) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS_MESSAGE_ID (0x57U) + +typedef struct NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 sorNumber; + NvBool bEnable; + NvBool bImmediate; + NvU32 headMask; + NvBool bForceRgDiv; + NvBool bUseBFM; + NvBool bFireAndForget; +} NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS; + +#define NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS_HEADMASK_HEAD(i) (i):(i) +#define NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS_HEADMASK_HEAD__SIZE_1 NV5070_CTRL_CMD_MAX_HEADS +#define NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS_HEADMASK_HEAD_ALL 0xFFFFFFFF + + + +/* _ctrl5070or_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl5070/ctrl5070rg.h b/userspace/sdks/nv570/inc/ctrl/ctrl5070/ctrl5070rg.h new file mode 100644 index 0000000..88f66ab --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl5070/ctrl5070rg.h @@ -0,0 +1,437 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070rg.finn +// + +#include "ctrl/ctrl5070/ctrl5070base.h" + + + +/* + * NV5070_CTRL_CMD_GET_RG_STATUS + * + * This 'get' command returns the status of raster generator + * + * head + * The head for which RG status is desired. + * + * scanLocked + * Whether or not RG is scan (raster or frame) locked. + * flipLocked + * Whether or not RG is flip locked. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_GET_RG_STATUS (0x50700202) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_RG_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_RG_STATUS_SCANLOCKED_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_STATUS_SCANLOCKED_YES (0x00000001) + +#define NV5070_CTRL_CMD_GET_RG_STATUS_FLIPLOCKED_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_STATUS_FLIPLOCKED_YES (0x00000001) + +#define NV5070_CTRL_CMD_GET_RG_STATUS_STALLED_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_STATUS_STALLED_YES (0x00000001) + +#define NV5070_CTRL_CMD_GET_RG_STATUS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV5070_CTRL_CMD_GET_RG_STATUS_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 head; + + NvU32 scanLocked; // [OUT] + NvU32 flipLocked; // [OUT] + NvU32 rgStalled; +} NV5070_CTRL_CMD_GET_RG_STATUS_PARAMS; + +/* + * NV5070_CTRL_CMD_UNDERFLOW_PARAMS + * + * This structure contains data for + * NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP and + * NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP CTRL calls + * + * head + * The head for which RG underflow properties needed to be set/get. + * Valid values for this parameter are 0 to NV5070_CTRL_CMD_MAX_HEADS. + * enable + * _SET_RG_: Whether to enable or disable RG underflow reporting. + * _GET_RG_: Whether or not RG underflow reporting is enabled. + * underflow + * _SET_RG_: Clear underflow (CLEAR_UNDERFLOW_YES) or leave it alone + * (CLEAR_UNDERFLOW_NO). + * Note: The GET_RG function automatically clears the underflow. + * It is recommended that GET_RG be used to clear any initial + * underflows, and that the "underflow" field be set to + * CLEAR_UNDERFLOW_NO in any SET_RG calls. This field may be + * deprecated in the future, for SET_RG calls. + * _GET_RG_: UNDERFLOWED_YES if an RG underflow occurred since the most + * recent prior call to to NV5070_CTRL_CMD_GET_RG_STATUS. + * epfifoUnderflow + * _SET_RG_: Not used. + * _GET_RG_: EPFIFO_UNDERFLOWED_YES if an EPFIFO underflow occurred since + * the most recent prior call to NV5070_CTRL_CMD_GET_RG_STATUS. + * mode + * _SET_RG_: What mode to use when underflow occurs. This is + * independent from enable field. This is always active. + * _GET_RG_: What mode is used when underflow occurs. This is + * independent from enable field. This is always active. + */ +typedef struct NV5070_CTRL_CMD_UNDERFLOW_PARAMS { + NvU32 head; + NvU32 enable; + NvU32 underflow; + NvU32 epfifoUnderflow; + NvU32 mode; +} NV5070_CTRL_CMD_UNDERFLOW_PARAMS; + +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_ENABLED_NO (0x00000000) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_ENABLED_YES (0x00000001) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_UNDERFLOWED_NO (0x00000000) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_UNDERFLOWED_YES (0x00000001) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_EPFIFO_UNDERFLOWED_NO (0x00000000) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_EPFIFO_UNDERFLOWED_YES (0x00000001) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_MODE_REPEAT (0x00000000) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_MODE_RED (0x00000001) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_ENABLE_NO (0x00000000) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_ENABLE_YES (0x00000001) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_CLEAR_UNDERFLOW_NO (0x00000000) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_CLEAR_UNDERFLOW_YES (0x00000001) + +/* + * NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP + * + * This command returns the underflow reporting parameters inside + * NV5070_CTRL_CMD_UNDERFLOW_PARAMS structure + * + * underflowParams + * Contains data for underflow logging. + * Check NV5070_CTRL_CMD_UNDERFLOW_PARAMS structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP (0x50700203) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NV5070_CTRL_CMD_UNDERFLOW_PARAMS underflowParams; +} NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP_PARAMS; + + +/* + * NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP + * + * This command sets up the underflow parameters using + * NV5070_CTRL_CMD_UNDERFLOW_PARAMS structure + * + * underflowParams + * Contains data for underflow logging. + * Check NV5070_CTRL_CMD_UNDERFLOW_PARAMS structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP (0x50700204) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NV5070_CTRL_CMD_UNDERFLOW_PARAMS underflowParams; +} NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP_PARAMS; + + +/* + * NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP + * + * This command gets the timing parameters associated with the lockout period. + * + * head + * The head for which RG fliplock properties are desired. + * + * maxSwapLockoutSkew + * The maximum possible skew between the swap lockout signals for all + * heads which are fliplocked to this head. + * + * swapLockoutStart + * Determines the start of the start lockout period, expressed as the + * number of lines before the end of the frame. The minimum allowed + * value is 1. + + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP (0x50700205) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_MAX_SWAP_LOCKOUT_SKEW 9:0 + +#define NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_SWAP_LOCKOUT_START 15:0 + +#define NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 head; + + NvU32 maxSwapLockoutSkew; + NvU32 swapLockoutStart; +} NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_PARAMS; + +/* + * NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP + * + * This command sets the timing parameters associated with the lockout period. + * + * head + * The head for which RG fliplock properties are desired. + * + * maxSwapLockoutSkew + * The maximum possible skew between the swap lockout signals for all + * heads which are fliplocked to this head. + * + * swapLockoutStart + * Determines the start of the start lockout period, expressed as the + * number of lines before the end of the frame. The minimum allowed + * value is 1. + + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP (0x50700206) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_MAX_SWAP_LOCKOUT_SKEW 9:0 +#define NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_MAX_SWAP_LOCKOUT_SKEW_INIT (0x00000000) + +#define NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_SWAP_LOCKOUT_START 15:0 +#define NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_SWAP_LOCKOUT_START_INIT (0x00000000) + +#define NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 head; + + NvU32 maxSwapLockoutSkew; + NvU32 swapLockoutStart; +} NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS; + +/* + * NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS + * + * This command returns which set of lockpins needs to be used in order to + * successfully raster lock two heads on different GPUs together. The + * second GPU is not inferred from linked SLI state, if any, and needs to + * be specified explicitly. + * + * head + * The local head to be locked with the peer head. + * + * peer.hDisplay + * The handle identifying a display object allocated on another + * GPU. It specifies the peer of interest with a subdevice + * index (see below) and needs to be be distinct from the handle + * supplied directly to NvRmControl(). + * + * peer.subdeviceIndex + * The index of the peer subdevice of interest. + * + * peer.head + * The peer head to be locked with the local head. + * + * masterScanLockPin + * slaveScanLockPin + * Returns the master and slave scanlock pins that would need to + * be used to lock the specified heads together, if any. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_OBJECT_PARENT + */ +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS (0x5070020a) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_MASTER_SCAN_LOCK_CONNECTED 0:0 +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_MASTER_SCAN_LOCK_CONNECTED_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_MASTER_SCAN_LOCK_CONNECTED_YES (0x00000001) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_MASTER_SCAN_LOCK_PIN 2:1 + +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_SLAVE_SCAN_LOCK_CONNECTED 0:0 +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_SLAVE_SCAN_LOCK_CONNECTED_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_SLAVE_SCAN_LOCK_CONNECTED_YES (0x00000001) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_SLAVE_SCAN_LOCK_PIN 2:1 + +#define NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 head; + + struct { + NvHandle hDisplay; + NvU32 subdeviceIndex; + NvU32 head; + } peer; + + NvU32 masterScanLock; + NvU32 slaveScanLock; +} NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS; + +/* + * NV5070_CTRL_CMD_GET_PINSET_LOCKPINS + * + * Get the lockpins for the specified pinset. + * + * pinset [in] + * The pinset whose corresponding lockpin numbers need to be determined + * must be specified with this parameter. + * + * scanLockPin [out] + * The scanlock lockpin (rasterlock or framelock) index, which can be + * either master or slave, is returned in this parameter. + * + * flipLockPin [out] + * The fliplock lockpin index, is returned in this parameter. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV5070_CTRL_CMD_GET_PINSET_LOCKPINS (0x5070020b) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_GET_PINSET_LOCKPINS_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_GET_PINSET_LOCKPINS_SCAN_LOCK_PIN_NONE 0xffffffff + +#define NV5070_CTRL_GET_PINSET_LOCKPINS_FLIP_LOCK_PIN_NONE 0xffffffff + +#define NV5070_CTRL_GET_PINSET_LOCKPINS_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV5070_CTRL_GET_PINSET_LOCKPINS_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 pinset; + NvU32 scanLockPin; + NvU32 flipLockPin; +} NV5070_CTRL_GET_PINSET_LOCKPINS_PARAMS; + +/* + * NV5070_CTRL_CMD_GET_RG_SCAN_LINE + * + * This 'get' command returns the current scan line value from raster generator + * + * head + * The head for which current scan line number is desired. + * + * scanLine + * Current scan line number. + * + * inVblank + * Whether or not in vblank. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_GET_RG_SCAN_LINE (0x5070020c) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_RG_SCAN_LINE_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_RG_SCAN_LINE_IN_VBLANK_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_SCAN_LINE_IN_VBLANK_YES (0x00000001) + +#define NV5070_CTRL_CMD_GET_RG_SCAN_LINE_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV5070_CTRL_CMD_GET_RG_SCAN_LINE_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 head; + NvU32 scanLine; // [OUT] + NvU32 inVblank; // [OUT] +} NV5070_CTRL_CMD_GET_RG_SCAN_LINE_PARAMS; + +/* + * NV5070_CTRL_CMD_GET_FRAMELOCK_HEADER_LOCKPINS + * + * This command returns FrameLock header lock pin information. + * Lock pin index returned by this command corresponds to the + * evo lock pin number. Example - lock pin index 0 means + * LOCKPIN_0. + * + * frameLockPin [out] + * This parameter returns the FrameLock pin index + * connected to FrameLock header. + * + * rasterLockPin [out] + * This parameter returns the RasterLock pin index + * connected to FrameLock header. + * + * flipLockPin [out] + * This parameter returns the FlipLock pin index + * connected to FrameLock header. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV5070_CTRL_CMD_GET_FRAMELOCK_HEADER_LOCKPINS (0x5070020d) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_FRAME_LOCK_PIN_NONE (0xffffffff) +#define NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_RASTER_LOCK_PIN_NONE (0xffffffff) +#define NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_FLIP_LOCK_PIN_NONE (0xffffffff) +#define NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 frameLockPin; + NvU32 rasterLockPin; + NvU32 flipLockPin; +} NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_PARAMS; + + + +/* _ctrl5070rg_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl5070/ctrl5070system.h b/userspace/sdks/nv570/inc/ctrl/ctrl5070/ctrl5070system.h new file mode 100644 index 0000000..c222907 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl5070/ctrl5070system.h @@ -0,0 +1,81 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070system.finn +// + +#include "ctrl/ctrl5070/ctrl5070base.h" +#include "ctrl/ctrl5070/ctrl5070common.h" // NV5070_CTRL_CMD_MAX_HEADS + +/* extract cap bit setting from tbl */ +#define NV5070_CTRL_SYSTEM_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* caps format is byte_index:bit_mask */ +#define NV5070_CTRL_SYSTEM_CAPS_BUG_237734_REQUIRES_DMI_WAR 0:0x01 // Deprecated +#define NV5070_CTRL_SYSTEM_CAPS_STEREO_DIN_AVAILABLE 0:0x02 +#define NV5070_CTRL_SYSTEM_CAPS_BUG_381003_MULTIWAY_AFR_WAR 0:0x04 +#define NV5070_CTRL_SYSTEM_CAPS_BUG_538079_COLOR_COMPRESSION_SUPPORTED 0:0x08 // Deprecated +#define NV5070_CTRL_SYSTEM_CAPS_BUG_2052012_GLITCHY_MCLK_SWITCH 0:0x10 +#define NV5070_CTRL_SYSTEM_CAPS_DEEP_COLOR_SUPPORT 0:0x20 +#define NV5070_CTRL_SYSTEM_CAPS_BUG_644815_DNISO_VIDMEM_ONLY 0:0x40 + + +/* size in bytes of display caps table */ +#define NV5070_CTRL_SYSTEM_CAPS_TBL_SIZE 1 + +/* + * NV5070_CTRL_CMD_SYSTEM_GET_CAPS_V2 + * + * This command returns the set of display capabilities for the parent device + * in the form of an array of unsigned bytes. Display capabilities + * include supported features and required workarounds for the display + * engine(s) within the device, each represented by a byte offset into the + * table and a bit position within that byte. The set of display capabilities + * will be normalized across all GPUs within the device (a feature capability + * will be set only if it's supported on all GPUs while a required workaround + * capability will be set if any of the GPUs require it). + * + * [out] capsTbl + * This caps table array is where the display cap bits will be transferred + * by the RM. The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + */ +#define NV5070_CTRL_CMD_SYSTEM_GET_CAPS_V2 (0x50700709) /* finn: Evaluated from "(FINN_NV50_DISPLAY_SYSTEM_INTERFACE_ID << 8) | NV5070_CTRL_SYSTEM_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_SYSTEM_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV5070_CTRL_SYSTEM_GET_CAPS_V2_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + + NvU8 capsTbl[NV5070_CTRL_SYSTEM_CAPS_TBL_SIZE]; +} NV5070_CTRL_SYSTEM_GET_CAPS_V2_PARAMS; + +/* _ctrl5070system_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl5070/ctrl5070verif.h b/userspace/sdks/nv570/inc/ctrl/ctrl5070/ctrl5070verif.h new file mode 100644 index 0000000..ab31072 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl5070/ctrl5070verif.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070verif.finn +// + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl5080.h b/userspace/sdks/nv570/inc/ctrl/ctrl5080.h new file mode 100644 index 0000000..0b46927 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl5080.h @@ -0,0 +1,211 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5080.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl0080/ctrl0080dma.h" /* NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS */ +#include "ctrl/ctrl2080/ctrl2080dma.h" /* NV2080_CTRL_DMA_* */ +#include "ctrl/ctrl2080/ctrl2080fifo.h" /* NV2080_CTRL_FIFO_* */ +#include "ctrl/ctrl2080/ctrl2080gpu.h" /* NV2080_CTRL_GPU_* */ +#include "ctrl/ctrl2080/ctrl2080gr.h" /* NV2080_CTRL_GR_* */ +/* NV5080_DEFERRED_API - deferred RmControl commands */ + + +#define NV5080_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x5080, NV5080_CTRL_##cat,idx) + +/* Command categories (6bits) */ +#define NV5080_CTRL_RESERVED (0x00) +#define NV5080_CTRL_DEFERRED (0x01) + +/* + * NV5080_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV5080_CTRL_CMD_NULL (0x50800000) /* finn: Evaluated from "(FINN_NV50_DEFERRED_API_CLASS_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + + +/* + * NV5080_CTRL_CMD_DEFERRED_API (deprecated; use NV5080_CTRL_CMD_DEFERRED_API_V2 instead) + * + * This command sets up a deferred api call. + * hApiHandle + * Client Unique Handle which is used as the data of a sw method to invoke + * the api in the future + * cmd + * The rmcontrol cmd to invoke as a deferred api. + * flags_delete + * Indicates if an explicit delete is needed (default behavior is to + * auto delete after SW method has executed/completed). + * flags_wait_for_tlb_flush + * Indicates if the API should wait for an InvalidateTlb to also occur + * (not just that it's executed) before being considered completed and + * works in conjunction with flags_delete. + * hClientVA, hDeviceVA + * Client/Device handles of the owner of the virtual address space to + * to be updated (used with the FillPteMem API bundle) + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV5080_CTRL_CMD_DEFERRED_API (0x50800101) /* finn: Evaluated from "(FINN_NV50_DEFERRED_API_CLASS_DEFERRED_INTERFACE_ID << 8) | NV5080_CTRL_DEFERRED_API_PARAMS_MESSAGE_ID" */ + +#define NV5080_CTRL_DEFERRED_API_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV5080_CTRL_DEFERRED_API_PARAMS { + NvHandle hApiHandle; + NvU32 cmd; + NvU32 flags; + NvHandle hClientVA; + NvHandle hDeviceVA; + + union { + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS InitCtx, 8); + + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS PromoteCtx, 8); + + NV2080_CTRL_GPU_EVICT_CTX_PARAMS EvictCtx; + + NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS InvalidateTlb; + + NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS FillPteMem, 8); + + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS ZcullCtxsw, 8); + + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS PmCtxsw, 8); + + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS PreemptionCtxsw, 8); + } api_bundle; +} NV5080_CTRL_DEFERRED_API_PARAMS; + +#define NV5080_CTRL_CMD_DEFERRED_API_FLAGS_DELETE 0:0 +#define NV5080_CTRL_CMD_DEFERRED_API_FLAGS_DELETE_EXPLICIT (0x00000001) +#define NV5080_CTRL_CMD_DEFERRED_API_FLAGS_DELETE_IMPLICIT (0x00000000) + +#define NV5080_CTRL_CMD_DEFERRED_API_FLAGS_WAIT_FOR_TLB_FLUSH 1:1 +#define NV5080_CTRL_CMD_DEFERRED_API_FLAGS_WAIT_FOR_TLB_FLUSH_FALSE (0x00000000) +#define NV5080_CTRL_CMD_DEFERRED_API_FLAGS_WAIT_FOR_TLB_FLUSH_TRUE (0x00000001) +/* + * NV5080_CTRL_CMD_DEFERRED_API_V2 + * + * This command sets up a deferred api call. + * hApiHandle + * Client Unique Handle which is used as the data of a sw method to invoke + * the api in the future + * cmd + * The rmcontrol cmd to invoke as a deferred api. + * flags_delete + * Indicates if an explicit delete is needed (default behavior is to + * auto delete after SW method has executed/completed). + * flags_wait_for_tlb_flush + * Indicates if the API should wait for an InvalidateTlb to also occur + * (not just that it's executed) before being considered completed and + * works in conjunction with flags_delete. + * hClientVA, hDeviceVA + * Client/Device handles of the owner of the virtual address space to + * to be updated (used with the FillPteMem API bundle) + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV5080_CTRL_CMD_DEFERRED_API_V2 (0x50800103) /* finn: Evaluated from "(FINN_NV50_DEFERRED_API_CLASS_DEFERRED_INTERFACE_ID << 8) | NV5080_CTRL_DEFERRED_API_V2_PARAMS_MESSAGE_ID" */ + +#define NV5080_CTRL_DEFERRED_API_V2_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV5080_CTRL_DEFERRED_API_V2_PARAMS { + NvHandle hApiHandle; + NvU32 cmd; + NvU32 flags; + NvHandle hClientVA; + NvHandle hDeviceVA; + + union { + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS InitCtx, 8); + + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS PromoteCtx, 8); + + NV2080_CTRL_GPU_EVICT_CTX_PARAMS EvictCtx; + + NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS InvalidateTlb; + + NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS FillPteMem, 8); + + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS ZcullCtxsw, 8); + + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS PmCtxsw, 8); + + NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS DisableChannels, 8); + + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS PreemptionCtxsw, 8); + + NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS ChannelInfoUpdate, 8); + } api_bundle; +} NV5080_CTRL_DEFERRED_API_V2_PARAMS; + +/* This is just used to forward NV5080_CTRL_CMD_DEFERRED_API_V2 from kernel RM + * to physical RM. The parameters are unchanged. */ +#define NV5080_CTRL_CMD_DEFERRED_API_INTERNAL (0x50800104) /* finn: Evaluated from "(FINN_NV50_DEFERRED_API_CLASS_DEFERRED_INTERFACE_ID << 8) | NV5080_CTRL_DEFERRED_API_INTERNAL_PARAMS_MESSAGE_ID" */ + +#define NV5080_CTRL_DEFERRED_API_INTERNAL_PARAMS_MESSAGE_ID (0x4U) + +typedef NV5080_CTRL_DEFERRED_API_V2_PARAMS NV5080_CTRL_DEFERRED_API_INTERNAL_PARAMS; + +/* + * NV5080_CTRL_CMD_REMOVE_API + * + * This command removes an explicit deferred api call. + * hApiHandle + * Client Unique Handle which is used as the data of a sw method to invoke + * the api in the future + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV5080_CTRL_CMD_REMOVE_API (0x50800102) /* finn: Evaluated from "(FINN_NV50_DEFERRED_API_CLASS_DEFERRED_INTERFACE_ID << 8) | NV5080_CTRL_REMOVE_API_PARAMS_MESSAGE_ID" */ + +#define NV5080_CTRL_REMOVE_API_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV5080_CTRL_REMOVE_API_PARAMS { + NvHandle hApiHandle; +} NV5080_CTRL_REMOVE_API_PARAMS; + +/* _ctrl5080_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl83de.h b/userspace/sdks/nv570/inc/ctrl/ctrl83de.h new file mode 100644 index 0000000..5b9b49e --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl83de.h @@ -0,0 +1,36 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl83de.finn +// + + + + +#include "ctrl/ctrlxxxx.h" +#include "ctrl83de/ctrl83dedebug.h" + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl83de/ctrl83debase.h b/userspace/sdks/nv570/inc/ctrl/ctrl83de/ctrl83debase.h new file mode 100644 index 0000000..80b69c4 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl83de/ctrl83debase.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl83de/ctrl83debase.finn +// + +#include "ctrl/ctrlxxxx.h" +/* GT200_DEBUG control commands and parameters */ + +#define NV83DE_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x83DEU, NV83DE_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NV83DE_CTRL_RESERVED (0x00) +#define NV83DE_CTRL_GR (0x01) +#define NV83DE_CTRL_FIFO (0x02) +#define NV83DE_CTRL_DEBUG (0x03) +#define NV83DE_CTRL_INTERNAL (0x04) + + +/* + * NV83DE_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV83DE_CTRL_CMD_NULL (0x83de0000) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrl83debase_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl83de/ctrl83dedebug.h b/userspace/sdks/nv570/inc/ctrl/ctrl83de/ctrl83dedebug.h new file mode 100644 index 0000000..3a4dc34 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl83de/ctrl83dedebug.h @@ -0,0 +1,1284 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl83de/ctrl83dedebug.finn +// + +#include "ctrl/ctrl83de/ctrl83debase.h" +#include "nvstatus.h" + +#include "ctrl/ctrl2080/ctrl2080gpu.h" + +/* + * NV83DE_CTRL_CMD_SM_DEBUG_MODE_ENABLE + * + * The RmCtrl enables the debug mode for a given context. + * When enabled: + * - The program execution on a SM stops at breakpoints. + * - It allows the user to handle the RC recovery process and + * exceptions. (Yet to be supported) + * - It allows the user to suspend, resume the context. (Yet to be supported) + * + * This command accepts no parameters. + * + * Possible return values: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + * + */ +#define NV83DE_CTRL_CMD_SM_DEBUG_MODE_ENABLE (0x83de0301) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x1" */ + +/* + * NV83DE_CTRL_CMD_SM_DEBUG_MODE_DISABLE + * + * The RmCtrl disables the debug mode for a given context. + * When disabled: + * - The program execution on a SM ignores the breakpoints. + * - RC recovery process and exceptions are handled in the usual way. + * - A request to suspend, resume the context will return error + * NV_ERR_INVALID_COMMAND. + * + * This command accepts no parameters. + * + * Possible return values: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_SM_DEBUG_MODE_DISABLE (0x83de0302) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x2" */ + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG + * + * This command sets the MMU DEBUG mode. This is Fermi-onwards feature. + * If the query is made on an incorrect platform (for example, pre-Fermi) + * the call will return with an NV_ERR_NOT_SUPPORTED error. + * + * action + * The possible action values are: + * - NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_ENABLE + * This enables the MMU debug mode if possible. If however, any another + * client has already disabled the mode (via NV83DE call) then this + * operation returns NV_ERR_STATE_IN_USE. + * + * - NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_DISABLE + * This disables the MMU debug mode if possible. If however, any another + * client has already enabled the mode (via NV83DE call) then this + * operation returns NV_ERR_STATE_IN_USE. + * + * - NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_DEBUG_REQUESTS + * This operation releases all the client's outstanding requests to enable + * or disable the MMU debug mode. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG (0x83de0307) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS { + NvU32 action; +} NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS; + +#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_ENABLE (0x00000001) +#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_DISABLE (0x00000002) +#define NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_DEBUG_REQUESTS (0x00000003) + +/* + * NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG + * + * This command gets the value of currently configured MMU DEBUG mode. + * This is Fermi-onwards feature. If the query is made on an incorrect + * platform (for example, pre-Fermi) the call will return with an + * NV_ERR_NOT_SUPPORTED error. + * + * value + * This parameter returns the configured value. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG (0x83de0308) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS { + NvU32 value; +} NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS; + +#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG_ENABLED (0x00000001) +#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG_DISABLED (0x00000002) + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_EXCEPTION_MASK + * + * This command allows the caller to filter events (which are also referred to + * as "notifications", not to be confused with true notifiers), in the RM, + * fairly close to the source of the events. In other words, depending on the + * value of the exceptionMask, some events may not be raised. + * + * The original reason for creating this command is that the CUDA driver needs + * to place the RM and the GPU(s) into SM debug mode, for some GPUs, in order to + * activate various features and HW bug WARs. Being in SM debug mode has the + * side effect of exposing the caller to debug events, which are generally + * undesirable for the CUDA driver, but desirable for the CUDA debugger. This + * command allows each client to receive only the events that it is + * specifically interested in. + * + * If this command is never invoked, then the RM will behave as if + * exceptionMask==NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_ALL. + * + * As with many of the debugger features, this is Fermi-onwards feature. If this + * API call is issued on an earlier platform, it will return an + * NV_ERR_NOT_SUPPORTED error. + * + * exceptionMask + * This identifies the category of notifications that the debug client + * is interested in. + * + * Here are the allowed values for exceptionMask: + * + * - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_FATAL + * This means that the caller wishes to receive events for any exceptions + * that are classified as fatal. For example, + * HWW_WARP_ESR_ERROR_PC_OVERFLOW is one such exception. + * + * If any debug object, in any channel, has registered to receive events + * for _FATAL exceptions, then RC recovery will be deferred if such an + * exception occurs. + * + * Also, if a client is registered for fatal exceptions, RC error recovery + * will be deferred. If not registered for fatal exceptions, then fatal + * errors will (as usual) cause RC recovery to run immediately. + * + * - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_TRAP + * This means that an event will be raised when an SM executes a bpt.pause + * instruction. Note that on Fermi, the SM raises HWW when bpt.trap is + * executed as well, so this event will also be raised in that situation. + * + * - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_SINGLE_STEP + * This means that an event will be raised a single step completion + * interrupt is received. + * + * - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_INT + * This means that an event will be raised when an SM executes a bpt.int + * instruction. + * + * - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_NONE + * This means that no debug events will be raised. + * + * - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_ALL + * This means that an event will be raised for any and all debug + * exceptions. This is the default behavior. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_EXCEPTION_MASK (0x83de0309) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS { + NvU32 exceptionMask; +} NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS; + +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_FATAL (0x00000001) +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_TRAP (0x00000002) +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_SINGLE_STEP (0x00000004) +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_INT (0x00000008) +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_CILP (0x00000010) +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PREEMPTION_STARTED (0x00000020) +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_NONE (0x00000000) +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_ALL (0x0000FFFF) + + + +/* + * NV83DE_CTRL_CMD_READ_SINGLE_SM_ERROR_STATE + * + * This command reads the SM error state of a single SM. The error state + * consists of several 32-bit values. + * + * Note that this acts upon the currently resident GR (graphics) context. It is + * up to the RM client to ensure that the desired GR context is resident, before + * making this API call. + * + * See also: NV83DE_CTRL_CMD_READ_ALL_SM_ERROR_STATES. + * + * This is a Fermi-and-later feature. If this API call is issued on an earlier + * platform, it will return an NV_ERR_NOT_SUPPORTED error. + * + * Parameters: + * + * hTargetChannel (input) + * This identifies the channel. + * + * smID (input) + * This identifies the SM. Allowed values are any valid SM ID. The RM + * grProgramSmIdNumbering_HAL() routines are a good place to look, in order + * to see how SM IDs are set up. The main idea is that the RM chooses a + * numbering scheme, and then informs the GPU hardware of that scheme, by + * actually recording each SM ID into the GPU, via a series of PRI (GPU + * register) writes. + * + * smErrorState.hwwGlobalEsr (output) + * Value of the Global Error Status Register. + * + * smErrorState.hwwWarpEsr (output) + * Value of the Warp Error Status Register. + * + * smErrorState.hwwWarpEsrPc (output) : DEPRECATED for 64b PC below, will hold low 32b for now + * Value of the Warp Error Status Register Program Counter. + * + * smErrorState.hwwGlobalEsrReportMask (output) + * Value of the Global Error Status Register Report Mask. + * + * smErrorState.hwwWarpEsrReportMask (output) + * Value of the Error Status Register Report Mask. + * + * smErrorState.hwwWarpEsrPc64 (output) + * Value of the 64b Warp Error Status Register Program Counter. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_READ_SINGLE_SM_ERROR_STATE (0x83de030b) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID" */ + +typedef struct NV83DE_SM_ERROR_STATE_REGISTERS { + NvU32 hwwGlobalEsr; + NvU32 hwwWarpEsr; + NvU32 hwwWarpEsrPc; + NvU32 hwwGlobalEsrReportMask; + NvU32 hwwWarpEsrReportMask; + NV_DECLARE_ALIGNED(NvU64 hwwEsrAddr, 8); + NV_DECLARE_ALIGNED(NvU64 hwwWarpEsrPc64, 8); + NvU32 hwwCgaEsr; + NvU32 hwwCgaEsrReportMask; +} NV83DE_SM_ERROR_STATE_REGISTERS; + +#define NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS { + NvHandle hTargetChannel; + NvU32 smID; + NV_DECLARE_ALIGNED(NV83DE_SM_ERROR_STATE_REGISTERS smErrorState, 8); +} NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS; + +/* + * NV83DE_CTRL_CMD_READ_ALL_SM_ERROR_STATES + * + * This command reads the SM error state of all SMs. + * + * Note that this acts upon the currently resident GR (graphics) context. It is + * up to the RM client to ensure that the desired GR context is resident, before + * making this API call. + * + * Parameters: + * + * hTargetChannel (input) + * This identifies the channel. + * + * numSMsToRead (input) + * This should be set to the number of SMs that the RM is supposed to read. + * It will typically be the total number of SMs in the GPU. For best + * results, you should not pass in a value that is greater than the number + * of SMs that the GPU actually contains. + * + * startingSM (input) + * This should be set to the starting index of the first SM to read. + * Clients may use this to read data from SMs beyond the maximum specified + * in NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL. + * + * smErrorStateArray (output) + * This is an array of NV83DE_SM_ERROR_STATE_REGISTERS structs. Please see + * the description of NV83DE_CTRL_CMD_READ_SINGLE_SM_ERROR_STATE, above, for + * a description of the individual fields. + * + * mmuFault.valid (output) + * This is NV_TRUE if an MMU fault occurred on the target channel since the last call to + * NV83DE_CTRL_CMD_CLEAR_ALL_SM_ERROR_STATES to this channel. + * + * mmuFault.faultInfo (output) + * This is the value of the first NV_PFIFO_INTR_MMU_FAULT_INFO that caused the MMU fault. + * + * mmuFaultInfo (output) + * Deprecated field, see mmuFault.faultInfo + * + * This is a Fermi-and-later feature. If this API call is issued on an earlier + * platform, it will return an NV_ERR_NOT_SUPPORTED error. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_READ_ALL_SM_ERROR_STATES (0x83de030c) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL 100 + +typedef struct NV83DE_MMU_FAULT_INFO { + NvBool valid; + NvU32 faultInfo; +} NV83DE_MMU_FAULT_INFO; + +#define NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS { + NvHandle hTargetChannel; + NvU32 numSMsToRead; + NV_DECLARE_ALIGNED(NV83DE_SM_ERROR_STATE_REGISTERS smErrorStateArray[NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL], 8); + NvU32 mmuFaultInfo; // Deprecated, use mmuFault field instead + NV83DE_MMU_FAULT_INFO mmuFault; + NvU32 startingSM; +} NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS; + +/* + * NV83DE_CTRL_CMD_CLEAR_SINGLE_SM_ERROR_STATE + * + * This command clears the SM error state of a single SM. The error state + * consists of several 32-bit values. + * + * Note that this acts upon the currently resident GR (graphics) context. It is + * up to the RM client to ensure that the desired GR context is resident, before + * making this API call. + * + * See also: NV83DE_CTRL_CMD_CLEAR_ALL_SM_ERROR_STATES. + * + * This API call has a slightly different effect than what would occur as a + * result of issuing a read-modify-write via _READ_SINGLE_SM_ERROR_STATE and + * _WRITE_SINGLE_SM_ERROR_STATE. The difference arises due to the fact that RM + * is caching the error state, to compensate for the fact that the real GPU + * error state must be cleared very early on in the exception handling routine. + * + * In other words, the _READ data is stale by design, and cannot be used in a + * read-modify-write routine from user space. Therefore, in order to clear the + * SM error state, a separate RM API call is required. + * + * This is a Fermi-and-later feature. If this API call is issued on an earlier + * platform, it will return an NV_ERR_NOT_SUPPORTED error. + * + * Parameters: + * + * hTargetChannel (input) + * This identifies the channel. + * + * smID (input) + * This identifies the SM. Allowed values are any valid SM ID. Please see + * NV83DE_CTRL_CMD_READ_SINGLE_SM_ERROR_STATE for further details. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE (0x83de030f) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS { + NvHandle hTargetChannel; + NvU32 smID; +} NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS; + +/* + * NV83DE_CTRL_CMD_CLEAR_ALL_SM_ERROR_STATES + * + * This command clears the SM error state of all SMs. + * + * Note that this acts upon the currently resident GR (graphics) context. It is + * up to the RM client to ensure that the desired GR context is resident, before + * making this API call. + * + * Parameters: + * + * hTargetChannel (input) + * This identifies the channel. + * + * numSMsToClear (input) + * This should be set to the number of SMs that the RM is supposed to write. + * It will typically be the total number of SMs in the GPU. For best + * results, you should not pass in a value that is greater than the number + * of SMs that the GPU actually contains. + * + * Please see the description of + * NV83DE_CTRL_CMD_CLEAR_SINGLE_SM_ERROR_STATE, above, for a description of + * why these two _CLEAR API calls are required. + * + * This is a Fermi-and-later feature. If this API call is issued on an earlier + * platform, it will return an NV_ERR_NOT_SUPPORTED error. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_CLEAR_ALL_SM_ERROR_STATES (0x83de0310) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS { + NvHandle hTargetChannel; + NvU32 numSMsToClear; +} NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS; + + + +#define NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS_DEFINED 1 +#define NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_HAS_RESIDENT_CHANNEL 1 +typedef struct NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS { + NvU32 waitForEvent; + NvHandle hResidentChannel; +} NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS; + + + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE + * + * This command set the type of action we want on RM encountering an error + * and issuing a STOP_TRIGGER. The action will be to either braodcast the + * STOP_TRIGGER to all SM's, or just send to the SM hitting an exception. + * + * stopTriggerType + * This identifies trigger type to initiate. + * + * Here are the allowed values for stopTriggerType: + * + * - NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_SINGLE_SM + * This means that we will issue STOP_TRIGGER to the single SM + * noted in the exception + * + * - NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_BROADCAST + * This means that we will issue STOP_TRIGGER to all SM's + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE (0x83de0313) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS { + NvU32 stopTriggerType; +} NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS; + +#define NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_SINGLE_SM (0x00000001) +#define NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_BROADCSAT (0x00000002) + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING + * + * This command sets the type of action we want on RM encountering a + * SINGLE_STEP exception while in CILP debug mode. In the normal case, + * non-pausing, we ignore these exceptions as on prior chips. When the + * user selects pausing, it will cause the exception to be treated just + * like we had seen an SM error or BPT_PAUSE. + * + * singleStepHandling + * This identifies single step handling type to use. + * + * Here are the allowed values for singleStepHandling: + * + * - NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_NONPAUSING + * Treat SINGLE_STEP exceptions while in debug mode as non-pausing, + * which is the default/normal mode in the interrupt pre-process + * function, where they are ignored. + * + * - NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PAUSING + * Treat SINGLE_STEP exceptions while in debug mode as pausing, + * which means in the interrupt pre-process function they will + * be treated like BPT_PAUSE and SM error exceptions + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING (0x83de0314) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS { + NvU32 singleStepHandling; +} NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS; + +#define NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_NONPAUSING (0x00000001) +#define NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PAUSING (0x00000002) + +/* + * NV83DE_CTRL_CMD_DEBUG_READ_MEMORY + * + * This command reads a block of memory. + * This command is deprecated in favor of NV83DE_CTRL_CMD_DEBUG_READ_BATCH_MEMORY + * + * hMemory [IN] + * The handle to the memory being accessed. If hMemory is not accessible + * from the caller's address space, NV_ERR_INSUFFICIENT_PERMISSIONS + * is returned. + * + * length [IN/OUT] + * Number of bytes to read, as well as the number of bytes actually read + * returned. + * + * offset [IN] + * The offset into the physical memory region given by the handle above. + * + * buffer [OUT] + * The data read is returned in this buffer. + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ACCESS_TYPE + * NV_ERR_INSUFFICIENT_PERMISSIONS + * + */ +#define NV83DE_CTRL_CMD_DEBUG_READ_MEMORY (0x83de0315) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS { + NvU32 hMemory; + NvU32 length; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvP64 buffer, 8); +} NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_WRITE_MEMORY + * + * This command writes a block of memory. + * This command is deprecated in favor of NV83DE_CTRL_CMD_DEBUG_WRITE_BATCH_MEMORY + * + * hMemory [IN] + * The handle to the memory being accessed. If hMemory is not accessible + * from the caller's address space, NV_ERR_INSUFFICIENT_PERMISSIONS + * is returned. + * + * length [IN/OUT] + * Number of bytes to write, as well as the number of bytes actually + * written. + * + * offset [IN] + * The offset into the physical memory region given by the handle above. + * + * buffer [IN] + * The data to be written is sent in this buffer. + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ACCESS_TYPE + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +#define NV83DE_CTRL_CMD_DEBUG_WRITE_MEMORY (0x83de0316) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS { + NvU32 hMemory; + NvU32 length; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvP64 buffer, 8); +} NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT + * + * This command suspends a SM context associated with the debugger object. + * + * When the suspend call returns, context associated with the debugger object + * should not be actively executing any code on any SM. The channel will have + * been disabled if not resident on GR, or have its SM suspended if it was resident. + * + * This is a Fermi-and-later feature. If this API call is issued on an earlier + * platform, it will return an NV_ERR_NOT_SUPPORTED error. + * + * waitForEvent + * This return param indicates if the call had to issue a Preempt, + * therefore it is in process and user may need to wait for it. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_STATE + */ +#define NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT (0x83de0317) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_MESSAGE_ID (0x17U) + +typedef NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_RESUME_CONTEXT + * + * This command safely resumes the SM context associated with the debugger object. + * + * This is a Fermi-and-later feature. If this API call is issued on an earlier + * platform, it will return an NV_ERR_NOT_SUPPORTED error. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_STATE + */ +#define NV83DE_CTRL_CMD_DEBUG_RESUME_CONTEXT (0x83de0318) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x18" */ + +/* + * NV83DE_CTRL_CMD_DEBUG_GET_HANDLES + * + * This command returns relevant handles for the debug object + * This command is only available on debug and develop builds. + * + * Possible return values: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_CLIENT + * NV_ERR_INVALID_OBJECT_HANDLE + * + */ +#define NV83DE_CTRL_CMD_DEBUG_GET_HANDLES (0x83de0319) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x19" */ + +typedef struct NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS { + NvHandle hChannel; + NvHandle hSubdevice; +} NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS; + +/* + * NV83DE_CTRL_CMD_READ_SURFACE + * + * This command allows the caller to copy the data from a specified gpuVA + * to a usermode buffer. Before copying, this command validates whether or + * not the virtual address (VA) range provided as input has valid and allocated + * pages mapped to it in its entirety. + * + * This command's input is NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS which + * contains a buffer of NV83DE_CTRL_DEBUG_ACCESS_OPs + * + * Possible return values: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_XLATE + */ +#define NV83DE_CTRL_CMD_READ_SURFACE (0x83de031a) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x1A" */ + +/* + * NV83DE_CTRL_CMD_WRITE_SURFACE + * + * This command allows the caller to copy the data from a provided usermode + * buffer to a specified GPU VA. Before copying, this command validates whether or + * not the virtual address (VA) range provided as input has valid and allocated + * pages mapped to it in its entirety. + * + * This command's input is NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS which + * contains a buffer of NV83DE_CTRL_DEBUG_ACCESS_OPs + * + * Possible return values: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_XLATE + */ +#define NV83DE_CTRL_CMD_WRITE_SURFACE (0x83de031b) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x1B" */ + +#define MAX_ACCESS_OPS 64 + +typedef struct NV83DE_CTRL_DEBUG_ACCESS_OP { + NV_DECLARE_ALIGNED(NvU64 gpuVA, 8); // IN + NV_DECLARE_ALIGNED(NvP64 pCpuVA, 8); // IN/OUT Debugger CPU Pointer of buffer + NvU32 size; // IN Size in bytes + NvU32 valid; // OUT Whether the GpuVA is accessible +} NV83DE_CTRL_DEBUG_ACCESS_OP; + +typedef struct NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS { + NvU32 count; // IN Number of ops in this call + NV_DECLARE_ALIGNED(NV83DE_CTRL_DEBUG_ACCESS_OP opsBuffer[MAX_ACCESS_OPS], 8); +} NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS; + +/* + * NV83DE_CTRL_CMD_GET_MAPPINGS + * + * This command traverses through the virtual memory page hierarchy and + * fetches the valid virtual mappings and their sizes for a provided virtual + * address (VA) range. + * If a given VA range has more than MAX_GET_MAPPINGS_OPS valid mappings, + * hasMore is set to 1, and opsBuffer is still filled with MAX_GET_MAPPINGS_OPS + * valid mappings. In this case, this command should be called again with + * vaLo = opsBuffer[MAX_GET_MAPPINGS_OPS - 1].gpuVA + + * opsBuffer[MAX_GET_MAPPINGS_OPS - 1].size; + * and vaHi set to the next desired upper limit. + * + * This command's input is NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS which + * contains a buffer of NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP + * + * Possible return values: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_XLATE + */ +#define NV83DE_CTRL_CMD_GET_MAPPINGS (0x83de031c) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x1C" */ + +#define MAX_GET_MAPPINGS_OPS 64 + +typedef struct NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP { + NV_DECLARE_ALIGNED(NvU64 gpuVA, 8); // OUT Start of GPU VA for this mapping + NvU32 size; // OUT Size in bytes of this mapping +} NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP; + +typedef struct NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS { + NV_DECLARE_ALIGNED(NvU64 vaLo, 8); // IN Lower VA range, inclusive + NV_DECLARE_ALIGNED(NvU64 vaHi, 8); // IN Upper VA range, inclusive + NvU32 count; // OUT Number of ops in this call + NvU32 hasMore; // OUT Whether there are more valid mappings in this range than MAX_GET_MAPPINGS_OPS + NV_DECLARE_ALIGNED(NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP opsBuffer[MAX_GET_MAPPINGS_OPS], 8); +} NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS; + +/* + * NV83DE_CTRL_CMD_DEBUG_EXEC_REG_OPS + * + * This command is used to submit a buffer containing one or more + * NV2080_CTRL_GPU_REG_OP structures for processing. Each entry in the + * buffer specifies a single read or write operation. Each entry is checked + * for validity in an initial pass over the buffer with the results for + * each operation stored in the corresponding regStatus field. Unless + * bNonTransactional flag is set to true, if any invalid entries are found + * during this initial pass then none of the operations are executed. Entries + * are processed in order within each regType with NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL + * entries processed first followed by NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX entries. + * + * [IN] bNonTransactional + * This field specifies if command is non-transactional i.e. if set to + * true, all the valid operations will be executed. + * + * [IN] regOpCount + * This field specifies the number of valid entries in the regops list. + * + * [IN/OUT] regOps + * This field is to be filled with the desired register information that is + * to be retrieved. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV83DE_CTRL_CMD_DEBUG_EXEC_REG_OPS (0x83de031d) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_GPU_EXEC_REG_OPS_MAX_OPS 100 +#define NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_MESSAGE_ID (0x1DU) + +typedef struct NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS { + NvBool bNonTransactional; + NvU32 regOpCount; + // C form: NV2080_CTRL_GPU_REG_OP regOps[NV2080_CTRL_GPU_EXEC_REG_OPS_MAX_OPS] + NV2080_CTRL_GPU_REG_OP regOps[NV83DE_CTRL_GPU_EXEC_REG_OPS_MAX_OPS]; +} NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR + * + * This command sets the Errbar Debug mode. This is Volta-onwards feature. + * If the query is made on an incorrect platform (for example, pre-Volta) + * the call will return with an NV_ERR_NOT_SUPPORTED error. + * + * action + * The possible action values are: + * - NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_ENABLE + * This enables the Errbar debug mode. + * + * - NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DISABLE + * This disables the Errbar debug mode. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_WRITE + * NV_ERR_INVALID_ARGUMENT + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG (0x83de031f) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID (0x1FU) + +typedef struct NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS { + NvU32 action; +} NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS; + +#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG_DISABLE (0x00000000) +#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG_ENABLE (0x00000001) + +/* + * NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR + * + * This command gets the value of currently configured Errbar DEBUG mode. + * This is Volta-onwards feature. If the query is made on an incorrect + * platform (for example, pre-Volta) the call will return with an + * NV_ERR_NOT_SUPPORTED error. + * + * value + * This parameter returns the configured value. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_READ + * NV_ERR_INVALID_ARGUMENT + */ +#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG (0x83de0320) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS { + NvU32 value; +} NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS; + +#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG_DISABLED (0x00000000) +#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG_ENABLED (0x00000001) + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SINGLE_STEP + * + * This command either enables or disables single step mode for the given SM. + * + * smID (input) + * This identifies the SM. + * bSingleStep (input) + * This indicates the single step mode. NV_TRUE for ENABLED. + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SINGLE_STEP (0x83de0321) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_MESSAGE_ID (0x21U) + +typedef struct NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS { + NvU32 smID; + NvBool bSingleStep; +} NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_STOP_TRIGGER + * + * This command sets or clears the stop trigger for the given SM. + * + * smID (input) + * This identifies the SM. + * bStopTrigger (input) + * This indicates whether to set or clear the trigger. NV_TRUE for ENABLED. + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_STOP_TRIGGER (0x83de0322) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_BROADCAST ((NvU32)~0) + +#define NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS { + NvU32 smID; + NvBool bStopTrigger; +} NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_RUN_TRIGGER + * + * This command sets or clears the run trigger for the given SM. + * + * smID (input) + * This identifies the SM. + * bRunTrigger (input) + * This indicates whether to set or clear the trigger. NV_TRUE for ENABLED. + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_RUN_TRIGGER (0x83de0323) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS_MESSAGE_ID (0x23U) + +typedef struct NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS { + NvU32 smID; + NvBool bRunTrigger; +} NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT + * + * This command enables or disables skip idle warp detect for the given sm. + * + * smID (input) + * This identifies the SM. + * bSkipIdleWarpDetect (input) + * This indicates whether to enable or disable the mode. NV_TRUE for ENABLED. + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT (0x83de0324) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS_MESSAGE_ID (0x24U) + +typedef struct NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS { + NvU32 smID; + NvBool bSkipIdleWarpDetect; +} NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS + * + * This command retrieves the debugger status states of the given SM. + * + * smID (input) + * This identifies the SM. + * bInTrapMode (output) + * This indicates whether the SM is in trap mode. + * bCrsFlushDone (output) + * Deprecated GK110+. Always 0 Volta+. + * bRunTriggerInProgress (output) + * Deprecated GM10X+. Always 0 Volta+. + * bComputeContext (output) + * Deprecated GM10X+. Always 0 Volta+. + * bLockedDown (output) + * This indicates whether the SM is locked down. + */ +#define NV83DE_CTRL_CMD_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS (0x83de0325) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS_MESSAGE_ID" */ + +typedef struct NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS { + NvBool bInTrapMode; + NvBool bCrsFlushDone; + NvBool bRunTriggerInProgress; + NvBool bComputeContext; + NvBool bLockedDown; +} NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS; + +#define NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS_MESSAGE_ID (0x25U) + +typedef struct NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS { + NvU32 smID; + NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS smDebuggerStatus; +} NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS; + +/*! + * NV83DE_CTRL_CMD_DEBUG_ACCESS_MEMORY_ENTRY + * + * This struct represents a requet to read/write a block of memory. + * + * hMemory [IN] + * The handle to the memory being accessed. If hMemory is not accessible + * from the caller's address space, NV_ERR_INSUFFICIENT_PERMISSIONS + * is returned. + * + * length [IN] + * Number of bytes to read/write + * + * memOffset [IN] + * The offset into the physical memory region given by the handle above. + * + * dataOffset [IN] + * An offset into the usermode memory region provided by the enclosing + * params indicating where to read/write data from/to. + * + * status [OUT] + * The result status of the operation will be output. If NV_OK, even if + * command returned error status, the given operation was successful. If + * not NV_OK, it is guaranteed that the command will return error status. + */ +typedef struct NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY { + NvHandle hMemory; + NvU32 length; + NV_DECLARE_ALIGNED(NvU64 memOffset, 8); + NvU32 dataOffset; + NV_STATUS status; +} NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY; + +/*! + * NV83DE_CTRL_CMD_DEBUG_READ_BATCH_MEMORY + * + * Execute a batch of read memory operations. + * + * count [IN] + * Number of read/write operations to perform. + * + * dataLength [IN] + * Length of the usermode buffer passed in, in bytes. + * + * pData [OUT] + * Usermode buffer to store the output of the read operations. Each + * operation is expected to provide an offset into this buffer. + * + * entries [IN] + * List of operations to perform. First `count` entries are used. + */ +#define NV83DE_CTRL_CMD_DEBUG_READ_BATCH_MEMORY (0x83de0326) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x26" */ + +/*! + * NV83DE_CTRL_CMD_DEBUG_WRITE_BATCH_MEMORY + * + * Execute a batch of write memory operations. + * + * count [IN] + * Number of read/write operations to perform. + * + * dataLength [IN] + * Length of the usermode buffer passed in, in bytes. + * + * pData [IN] + * Usermode buffer to store the input of the write operations. Each + * operation is expected to provide an offset into this buffer. + * + * entries [IN] + * List of operations to perform. First `count` entries are used. + */ +#define NV83DE_CTRL_CMD_DEBUG_WRITE_BATCH_MEMORY (0x83de0327) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x27" */ + +#define MAX_ACCESS_MEMORY_OPS 150 +typedef struct NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pData, 8); + NvU32 dataLength; + NvU32 count; + NV_DECLARE_ALIGNED(NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY entries[MAX_ACCESS_MEMORY_OPS], 8); +} NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS; + +/* + * NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY + * + * faultAddress (OUT) + * Faulting address + * faultType (OUT) + * Type of MMU fault + * accessType (OUT) + * Type of access that caused this fault + */ +#define NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_MAX_ENTRIES 4 +typedef struct NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY { + NV_DECLARE_ALIGNED(NvU64 faultAddress, 8); + NvU32 faultType; + NvU32 accessType; +} NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY; + +/* + * NV83DE_CTRL_CMD_DEBUG_READ_MMU_FAULT_INFO + * + * mmuFaultInfoList (OUT) + * Entries of MMU faults recorded for the attached context. The cached data is only cleared via LRU policy when new MMU faults arrive so repeat data may be returned by this command. + * count (OUT) + * Number of MMU fault entries contain valid data. + */ +#define NV83DE_CTRL_CMD_DEBUG_READ_MMU_FAULT_INFO (0x83de0328) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x28U) + +typedef struct NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS { + NV_DECLARE_ALIGNED(NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY mmuFaultInfoList[NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_MAX_ENTRIES], 8); + NvU32 count; +} NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_DROP_DEFERRED_RC + * + * bDropDeferredRc (OUT) + * This indicates whether debugger wants a fault to eventually trigger RC on teardown or be dropped. + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_DROP_DEFERRED_RC (0x83de0329) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS_MESSAGE_ID (0x29U) + +typedef struct NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS { + NvBool bDropDeferredRc; +} NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG + * + * This command sets the MMU GCC DEBUG mode. This is Blackwell-onwards feature. + * If the query is made on an incorrect platform (for example, pre-Blackwell) + * the call will return with an NV_ERR_NOT_SUPPORTED error. + * + * action + * The possible action values are: + * - NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG_ENABLE + * This enables the MMU GCC debug mode if possible. If however, any another + * client has already disabled the mode (via NV83DE call) then this + * operation returns NV_ERR_STATE_IN_USE. + * + * - NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG_DISABLE + * This disables the MMU GCC debug mode if possible. If however, any another + * client has already enabled the mode (via NV83DE call) then this + * operation returns NV_ERR_STATE_IN_USE. + * + * - NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_GCC_DEBUG_REQUESTS + * This operation releases all the client's outstanding requests to enable + * or disable the MMU debug mode. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG (0x83de032a) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_MESSAGE_ID (0x2AU) + +typedef struct NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS { + NvU32 action; +} NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS; + +#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG_ENABLE (0x00000001) +#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG_DISABLE (0x00000002) +#define NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_GCC_DEBUG_REQUESTS (0x00000003) + +/* + * NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG + * + * This command gets the value of currently configured MMU GCC DEBUG mode. + * This is Blackwell-onwards feature. If the query is made on an incorrect + * platform (for example, pre-Blackwell) the call will return with an + * NV_ERR_NOT_SUPPORTED error. + * + * value + * This parameter returns the configured value. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG (0x83de032b) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_MESSAGE_ID (0x2BU) + +typedef struct NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS { + NvU32 value; +} NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS; + +#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG_ENABLED (0x00000001) +#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG_DISABLED (0x00000002) + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_NON_PREEMPTABLE_DEBUGGER_CONTEXT + * + * This command sets the preemptable mode of the debugger session. + * This allows the caller to control the behaviour of preemption-related events for the 3D-class object. + * + * If this command is not called, then the default behaviour is to preempt the current debugging session (ie. do not disable the ctxsw timeout) + * + * state [IN] + * Determines the behaviour of preemption-related events for the 3D-class object. This control call must be called via + * the escape NVL_ESC_ID_COMMON_DEBUG_SET_NON_PREEMPTABLE_DEBUGGER_CONTEXT. + * If NV_TRUE, ctxsw timeout will be disabled for the resident channel on which a 3D context is currently being debugged. + * If NV_FALSE, the debugged session will be preempted once ctxsw timeout is encountered. + * + * If this is called on Linux, the call will return NV_ERR_NOT_SUPPORTED. + */ + +#define NV83DE_CTRL_CMD_DEBUG_SET_NON_PREEMPTABLE_DEBUGGER_CONTEXT (0x83de022d) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_FIFO_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_NON_PREEMPTABLE_DEBUGGER_CONTEXT_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_NON_PREEMPTABLE_DEBUGGER_CONTEXT_PARAMS_MESSAGE_ID (0x2DU) + +typedef struct NV83DE_CTRL_DEBUG_SET_NON_PREEMPTABLE_DEBUGGER_CONTEXT_PARAMS { + NvBool state; +} NV83DE_CTRL_DEBUG_SET_NON_PREEMPTABLE_DEBUGGER_CONTEXT_PARAMS; + +#define NV83DE_CTRL_CMD_DEBUG_SET_NON_PREEMPTABLE_DEBUGGER_CONTEXT_ACTIVE (0x00000001) +#define NV83DE_CTRL_CMD_DEBUG_SET_NON_PREEMPTABLE_DEBUGGER_CONTEXT_INACTIVE (0x00000000) + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_RECOVERY_SUPPRESSION_TIMEOUT + * + * This command updates the timeout used to disable RC recovery. + * If this command is not called, the timeout will use a default value of 1 second on all OS. + * + * timeoutSec [IN] + * Sets the timeout for suppressing RC recovery. Once this timeout expires, a CTXSW timeout on the TSG associated with the debugging session will result in RC recovery. + * The timeout will get reset each time a BPT.PAUSE event is trigered. + * + * If this is called before NV83DE_CTRL_CMD_DEBUG_SET_NON_PREEMPTABLE_DEBUGGER_CONTEXT, the call will return NV_ERR_NOT_SUPPORTED. +*/ +#define NV83DE_CTRL_CMD_DEBUG_SET_RECOVERY_SUPPRESSION_TIMEOUT (0x83de022e) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_FIFO_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_RECOVERY_SUPPRESSION_TIMEOUT_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_RECOVERY_SUPPRESSION_TIMEOUT_PARAMS_MESSAGE_ID (0x2EU) + +typedef struct NV83DE_CTRL_DEBUG_SET_RECOVERY_SUPPRESSION_TIMEOUT_PARAMS { + NvU32 timeoutSec; +} NV83DE_CTRL_DEBUG_SET_RECOVERY_SUPPRESSION_TIMEOUT_PARAMS; + + + +/* _ctrl83dedebug_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl9010.h b/userspace/sdks/nv570/inc/ctrl/ctrl9010.h new file mode 100644 index 0000000..e26ce0d --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl9010.h @@ -0,0 +1,83 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl9010.finn +// + +#include "ctrl/ctrlxxxx.h" +#define NV9010_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0x9010, NV9010_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NV9010_CTRL_RESERVED (0x00) +#define NV9010_CTRL_VBLANK_CALLBACK (0x01) + + +/* + * NV9010_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV9010_CTRL_CMD_NULL (0x90100000) /* finn: Evaluated from "(FINN_NV9010_VBLANK_CALLBACK_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION + * + * This command is used to enable and disable vblank notifications. This + * is specially intended for cases where the RM client is calling from a + * high IRQL context, where other mechanisms to toggle vblank notification + * (such as freeing and reallocating the NV9010_VBLANK_CALLBACK object) + * would not be suitable. As this is being invoked at the high IRQL, + * locking can be bypassed, if the NVOS54_FLAGS_LOCK_BYPASS flag is set on + * the control call.Here the OS will take care of the synchronization. + * The Windows Display Driver for Cobalt requires this, for example. + * + * bSetVBlankNotifyEnable + * This parameter tell whether to enable or disable the Vblank notification + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION (0x90100101) /* finn: Evaluated from "(FINN_NV9010_VBLANK_CALLBACK_INTERFACE_ID << 8) | NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION_PARAMS_MESSAGE_ID (0x01U) + +typedef struct NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION_PARAMS { + NvBool bSetVBlankNotifyEnable; +} NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION_PARAMS; + +/* _ctrl9010_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl9067.h b/userspace/sdks/nv570/inc/ctrl/ctrl9067.h new file mode 100644 index 0000000..4342765 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl9067.h @@ -0,0 +1,157 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl9067.finn +// + +#include "ctrl/ctrlxxxx.h" +/* Subcontext control commands and parameters */ +#define NV9067_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x9067, NV9067_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NV9067_CTRL_RESERVED (0x00) +#define NV9067_CTRL_TPC_PARTITION (0x01) +#define NV9067_CTRL_CWD_WATERMARK (0x02) + +/*! + * Does nothing. + */ +#define NV9067_CTRL_CMD_NULL (0x90670000) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/*! + * NV9067_CTRL_CMD_GET_TPC_PARTITION_TABLE + * This command gets the current partition table configuration of a subcontext + * + * NV9067_CTRL_CMD_SET_TPC_PARTITION_TABLE + * This command sets the partition table of a subcontext + * + * NV9067_CTRL_TPC_PARTITION_TABLE_PARAMS + * This structure defines the parameters used for SET/GET per-subcontext TPC partitioning table configuration + * + * numUsedTpc [in/out] + * Specifies the number of TPCs used by the subcontext + * While querying the enabled TPCs, this is an output paramter + * While configuring the TPCs, this is an input parameter + * + * tpcList [in/out] + * Array containing the TPCs enabled for the subcontext. + * The first numUsedTpc in the array interpreted as the valid entries. + * + * Only applicable for STATIC and DYNAMIC modes. + * + * NV9067_CTRL_TPC_PARTITION_TABLE_MAX_TPC_COUNT + * Max TPC count supported by this ctrl call + * + * NV9067_CTRL_TPC_PARTITION_TABLE_TPC_INFO + * This structure defines the parameters for a TPC + * + * globalTpcIndex + * Global logical index of the enabled TPC + * + * lmemBlockIndex + * Block index of the Local memory backing store for the enabled TPC. + * For GET command, we will return the current lmem block assigment for STATIC & DYNAMIC modes. + * For SET command, this index is relevant only for STATIC mode. + * HW automatically assign it for other modes. So should be zeroed out for other modes. + * + */ +#define NV9067_CTRL_CMD_GET_TPC_PARTITION_TABLE (0x90670101) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_TPC_PARTITION_INTERFACE_ID << 8) | 0x1" */ + +#define NV9067_CTRL_CMD_SET_TPC_PARTITION_TABLE (0x90670102) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_TPC_PARTITION_INTERFACE_ID << 8) | NV9067_CTRL_TPC_PARTITION_TABLE_PARAMS_MESSAGE_ID" */ + +#define NV9067_CTRL_TPC_PARTITION_TABLE_TPC_COUNT_MAX 256 + +typedef struct NV9067_CTRL_TPC_PARTITION_TABLE_TPC_INFO { + NvU16 globalTpcIndex; + NvU16 lmemBlockIndex; +} NV9067_CTRL_TPC_PARTITION_TABLE_TPC_INFO; + +#define NV9067_CTRL_TPC_PARTITION_TABLE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV9067_CTRL_TPC_PARTITION_TABLE_PARAMS { + NvU16 numUsedTpc; + NV9067_CTRL_TPC_PARTITION_TABLE_TPC_INFO tpcList[NV9067_CTRL_TPC_PARTITION_TABLE_TPC_COUNT_MAX]; +} NV9067_CTRL_TPC_PARTITION_TABLE_PARAMS; + + +/*! + * NV9067_CTRL_CMD_GET_CWD_WATERMARK + * This command gets the cached watermark value for a subcontext + * + * NV9067_CTRL_CMD_SET_CWD_WATERMARK + * This command sets the watermark value for a subcontexts + * + * NV9067_CTRL_CWD_WATERMARK_PARAMS + * This structure defines the parameters used to SET/GET watermark value per-subcontext. + * + * watermarkValue [in/out] + * Value of watermark per-subcontext + * Acts as a output parameter to get the current value of watermark for a subcontext. + * Acts as a input parameter to set the current value of watermark for a subcontexts. + * + * NV9067_CTRL_CWD_WATERMARK_VALUE_MIN + * Minimum value of watermark for any subcontext + * RM will throw an error if any value less than this value is specified + * + * NV9067_CTRL_CWD_WATERMARK_VALUE_DEFAULT + * Default value of watermark for any subcontext + * RM will set watermark of a subcontext to this value when the subcontext + * is created/initialized for the first time + * + * NV9067_CTRL_CWD_WATERMARK_VALUE_MAX + * Maximum value of watermark for any subcontext + * RM will throw an error if any value more than this value is specified + * + */ + +#define NV9067_CTRL_CMD_GET_CWD_WATERMARK (0x90670201) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID << 8) | NV9067_CTRL_GET_CWD_WATERMARK_PARAMS_MESSAGE_ID" */ + +#define NV9067_CTRL_CWD_WATERMARK_VALUE_MIN 1 +#define NV9067_CTRL_CWD_WATERMARK_VALUE_DEFAULT 2 +#define NV9067_CTRL_CWD_WATERMARK_VALUE_MAX 256 + +typedef struct NV9067_CTRL_CWD_WATERMARK_PARAMS { + NvU32 watermarkValue; +} NV9067_CTRL_CWD_WATERMARK_PARAMS; + +#define NV9067_CTRL_GET_CWD_WATERMARK_PARAMS_MESSAGE_ID (0x1U) + +typedef NV9067_CTRL_CWD_WATERMARK_PARAMS NV9067_CTRL_GET_CWD_WATERMARK_PARAMS; + +#define NV9067_CTRL_CMD_SET_CWD_WATERMARK (0x90670202) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID << 8) | NV9067_CTRL_SET_CWD_WATERMARK_PARAMS_MESSAGE_ID" */ + +#define NV9067_CTRL_SET_CWD_WATERMARK_PARAMS_MESSAGE_ID (0x2U) + +typedef NV9067_CTRL_CWD_WATERMARK_PARAMS NV9067_CTRL_SET_CWD_WATERMARK_PARAMS; + +/* _ctrl9067_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl906f.h b/userspace/sdks/nv570/inc/ctrl/ctrl906f.h new file mode 100644 index 0000000..a9c573f --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl906f.h @@ -0,0 +1,223 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl906f.finn +// + + + + +/* GF100_GPFIFO control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#define NV906F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0x906F, NV906F_CTRL_##cat, idx) + +/* GF100_GPFIFO command categories (6bits) */ +#define NV906F_CTRL_RESERVED (0x00) +#define NV906F_CTRL_GPFIFO (0x01) + + +/* + * NV906F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV906F_CTRL_CMD_NULL (0x906f0000) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + + +/* + * NV906F_CTRL_GET_CLASS_ENGINEID + * + * Takes an object handle as input and returns + * the Class and Engine that this object uses. + * + * hObject + * Handle to an object created. For example a + * handle to object of type FERMI_A created by + * the client. This is supplied by the client + * of this call. + * + * classEngineID + * A concatenation of class and engineid + * that the object with handle hObject + * belongs to. This is returned by RM. The internal + * format of this data structure is opaque to clients. + * + * classID + * ClassID for object represented by hObject + * + * engineID + * EngineID for object represented by hObject + * + * Possible status values returned are: + * NV_OK + * If the call was successful. + * + * NV_ERR_INVALID_OBJECT_HANDLE + * No object of handle hObject was found. + */ +#define NV906F_CTRL_GET_CLASS_ENGINEID (0x906f0101) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */ + +#define NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS { + NvHandle hObject; + NvU32 classEngineID; + NvU32 classID; + NvU32 engineID; +} NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS; + +/* + * NV906F_CTRL_RESET_CHANNEL + * + * This command resets the channel corresponding to specified engine and also + * resets the specified engine. + * + * Takes an engine ID as input. + * + * engineID + * This parameter specifies the engine to be reset. See the description of the + * NV2080_ENGINE_TYPE values in cl2080.h for more information. + * subdeviceInstance + * This parameter specifies the subdevice to be reset when in SLI. + * resetReason + * Specifies reason to reset a channel. + * + * bIsRcPending + * Specifies if an RC is pending on the channel + * + * Possible status values returned are: + * NV_OK + */ +#define NV906F_CTRL_CMD_RESET_CHANNEL_REASON_DEFAULT 0 +#define NV906F_CTRL_CMD_RESET_CHANNEL_REASON_VERIF 1 +#define NV906F_CTRL_CMD_RESET_CHANNEL_REASON_MMU_FLT 2 +#define NV906F_CTRL_CMD_RESET_CHANNEL_REASON_KILL_PROCESS 3 +#define NV906F_CTRL_CMD_RESET_CHANNEL_REASON_ENUM_MAX 4 +/* + * Internal values for NV906F_CTRL_CMD_RESET_REASON. External values will be + * checked and enforced to be < NV906F_CTRL_CMD_RESET_CHANNEL_REASON_ENUM_MAX + */ +#define NV906F_CTRL_CMD_INTERNAL_RESET_CHANNEL_REASON_FAKE_ERROR (0x5) /* finn: Evaluated from "NV906F_CTRL_CMD_RESET_CHANNEL_REASON_ENUM_MAX + 1" */ + + +#define NV906F_CTRL_CMD_RESET_CHANNEL (0x906f0102) /* finn: Evaluated from "((FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID)" */ + +#define NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS { + NvU32 engineID; + NvU32 subdeviceInstance; + NvU32 resetReason; + NvBool bIsRcPending; +} NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS; + + + +/* + * NV906F_CTRL_CMD_GET_DEFER_RC_STATE + * + * If SM Debugger is attached then on a MMU fault, RM defers the RC error + * recovery and keeps a flag indicating that RC is deferred. This command + * checks whether or not deferred RC is pending in RM for the associated + * channel. + * + * bDeferRCPending + * The output are TRUE and FALSE. + * + * Possible status values returned are: + * NV_OK + */ + +#define NV906F_CTRL_CMD_GET_DEFER_RC_STATE (0x906f0105) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV906F_CTRL_CMD_GET_DEFER_RC_STATE_PARAMS_MESSAGE_ID" */ + +#define NV906F_CTRL_CMD_GET_DEFER_RC_STATE_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV906F_CTRL_CMD_GET_DEFER_RC_STATE_PARAMS { + NvBool bDeferRCPending; +} NV906F_CTRL_CMD_GET_DEFER_RC_STATE_PARAMS; + +#define NV906F_CTRL_CMD_GET_MMU_FAULT_INFO (0x906f0106) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */ + +/* + * Shader types supported by MMU fault info + * The types before compute shader refer to NV9097_SET_PIPELINE_SHADER_TYPE + */ +#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_VERTEX 0x00000001 +#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_TESSELLATION 0x00000003 +#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_GEOMETRY 0x00000004 +#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_PIXEL 0x00000005 +#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_COMPUTE 0x00000006 +#define NV906F_CTRL_MMU_FAULT_SHADER_TYPES 7 + +/* + * NV906F_CTRL_CMD_GET_MMU_FAULT_INFO + * + * This command returns MMU fault information for a given channel. The MMU + * fault information will be cleared once this command is executed. + * + * addrHi - [out] + * Upper 32 bits of faulting address + * addrLo [out] + * Lower 32 bits of faulting address + * faultType [out] + * MMU fault type. Please see NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE_* in + * dev_fifo.h for details about MMU fault type. + * faultString [out] + * String indicating the MMU fault type + * shaderProgramVA [out] + * an array of shader program virtual addresses to indicate faulted shaders in the pipeline + * + * Possible status values returned are: + * NV_OK + */ +#define NV906F_CTRL_MMU_FAULT_STRING_LEN 32 +#define NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS { + NvU32 addrHi; + NvU32 addrLo; + NvU32 faultType; + char faultString[NV906F_CTRL_MMU_FAULT_STRING_LEN]; + NV_DECLARE_ALIGNED(NvU64 shaderProgramVA[NV906F_CTRL_MMU_FAULT_SHADER_TYPES], 8); +} NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS; + + +/* _ctrl906f.h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl9072.h b/userspace/sdks/nv570/inc/ctrl/ctrl9072.h new file mode 100644 index 0000000..61eb32f --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl9072.h @@ -0,0 +1,86 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl9072.finn +// + +#include "ctrl/ctrlxxxx.h" +#define NV9072_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0x9072, NV9072_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NV9072_CTRL_RESERVED (0x00) +#define NV9072_CTRL_DISP_SW (0x01) + + +/* + * NV9072_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV9072_CTRL_CMD_NULL (0x90720000) /* finn: Evaluated from "(FINN_GF100_DISP_SW_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV9072_CTRL_CMD_NOTIFY_ON_VBLANK + * + * This command implements an out-of-band version of the + * GF100_DISP_SW class's NV9072_NOTIFY_ON_VBLANK method. + * + * Parameters: + * + * data + * Valid data accepted by the NV9072_NOTIFY_ON_VBLANK method. + * bHeadDisabled + * Specifies whether head is active while adding vblank + * callback. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ +#define NV9072_CTRL_CMD_NOTIFY_ON_VBLANK (0x90720101) /* finn: Evaluated from "(FINN_GF100_DISP_SW_DISP_SW_INTERFACE_ID << 8) | NV9072_CTRL_CMD_NOTIFY_ON_VBLANK_PARAMS_MESSAGE_ID" */ + +#define NV9072_CTRL_CMD_NOTIFY_ON_VBLANK_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV9072_CTRL_CMD_NOTIFY_ON_VBLANK_PARAMS { + NvU32 data; + NvBool bHeadDisabled; +} NV9072_CTRL_CMD_NOTIFY_ON_VBLANK_PARAMS; + +/* _ctrl9072.h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl9074.h b/userspace/sdks/nv570/inc/ctrl/ctrl9074.h new file mode 100644 index 0000000..9970e9f --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl9074.h @@ -0,0 +1,148 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl9074.finn +// + +#include "ctrl/ctrlxxxx.h" +#define NV9074_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x9074, NV9074_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NV9074_CTRL_RESERVED (0x00) +#define NV9074_CTRL_SEM (0x01) + +/* + * NV9074_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV9074_CTRL_CMD_NULL (0x90740000) /* finn: Evaluated from "(FINN_GF100_TIMED_SEMAPHORE_SW_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV9074_CTRL_CMD_FLUSH + * + * This command is intended to aid in idling/flushing a channel containing + * methods invoked against a specific NV9074 object. + * + * This control manipulates an NV9074 object's "flushing" state. + * + * Typical usage is: + * NvRmControl(NV9074_CTRL_CMD_FLUSH, {TRUE, flushDelay}); + * NvRmIdleChannel(channel_containing_the_9074_object); + * NvRmControl(NV9074_CTRL_CMD_FLUSH, {FALSE, 0}); + * + * When an NV9074 object is placed into the flushing state, a snaphot of the + * current timer value is taken, and "maxFlushTime" is added to this. This + * value is the "flush limit timestamp". Any previously or newly invoked + * NV9074_SEMAPHORE_SCHED methods and NV9074_CTRL_CMD_RELEASE requests that + * specify a release timestamp at or after this "flush limit timestamp" will + * immediately release the specified semaphore, without waiting for the + * specified timestamp, and write a DONE_FORCED value to the specified notifier. + */ +#define NV9074_CTRL_CMD_FLUSH (0x90740101) /* finn: Evaluated from "(FINN_GF100_TIMED_SEMAPHORE_SW_SEM_INTERFACE_ID << 8) | NV9074_CTRL_CMD_FLUSH_PARAMS_MESSAGE_ID" */ + +#define NV9074_CTRL_CMD_FLUSH_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV9074_CTRL_CMD_FLUSH_PARAMS { + NvU32 isFlushing; + NV_DECLARE_ALIGNED(NvU64 maxFlushTime, 8); +} NV9074_CTRL_CMD_FLUSH_PARAMS; + +/* + * NV9074_CTRL_CMD_GET_TIME + * + * Retrieve the current time value. + */ +#define NV9074_CTRL_CMD_GET_TIME (0x90740102) /* finn: Evaluated from "(FINN_GF100_TIMED_SEMAPHORE_SW_SEM_INTERFACE_ID << 8) | NV9074_CTRL_CMD_GET_TIME_PARAMS_MESSAGE_ID" */ + +#define NV9074_CTRL_CMD_GET_TIME_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV9074_CTRL_CMD_GET_TIME_PARAMS { + NV_DECLARE_ALIGNED(NvU64 currentTime, 8); +} NV9074_CTRL_CMD_GET_TIME_PARAMS; + +/* + * NV9074_CTRL_CMD_RELEASE + * + * This command adds a timed semaphore release request. When the desired time is + * reached, the semaphore is written with the release value, the notifier is + * filled with status and timestamp, and optionally an event is sent to all the + * client waiting on it. + * + * notifierGPUVA + * This parameter specifies the GPU VA of the notifier to receive the status + * for this particular release. + * + * semaphoreGPUVA + * This parameter specifies the GPU VA of the semaphore to release. + * + * waitTimestamp + * This parameter specifies the timestamp at which to release the semaphore. + * + * releaseValue + * This parameter specifies the semaphore value to release. + * + * releaseFlags + * This parameter specifies the flags: + * _NOTIFY wake client or not. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ADDRESS + * NV_ERR_INVALID_EVENT + * NV_ERR_INVALID_STATE + * + */ +#define NV9074_CTRL_CMD_RELEASE (0x90740103) /* finn: Evaluated from "(FINN_GF100_TIMED_SEMAPHORE_SW_SEM_INTERFACE_ID << 8) | NV9074_CTRL_CMD_RELEASE_PARAMS_MESSAGE_ID" */ + +#define NV9074_CTRL_CMD_RELEASE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV9074_CTRL_CMD_RELEASE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 notifierGPUVA, 8); + NV_DECLARE_ALIGNED(NvU64 semaphoreGPUVA, 8); + NV_DECLARE_ALIGNED(NvU64 waitTimestamp, 8); + NvU32 releaseValue; + NvU32 releaseFlags; +} NV9074_CTRL_CMD_RELEASE_PARAMS; + +#define NV9074_CTRL_CMD_RELEASE_FLAGS +#define NV9074_CTRL_CMD_RELEASE_FLAGS_NOTIFY 1:0 +#define NV9074_CTRL_CMD_RELEASE_FLAGS_NOTIFY_WRITE_ONLY (0x00000000) +#define NV9074_CTRL_CMD_RELEASE_FLAGS_NOTIFY_WRITE_THEN_AWAKEN (0x00000001) + +/* _ctrl9074.h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl9096.h b/userspace/sdks/nv570/inc/ctrl/ctrl9096.h new file mode 100644 index 0000000..d53413b --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl9096.h @@ -0,0 +1,444 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl9096.finn +// + +#include "ctrl/ctrlxxxx.h" +#define NV9096_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0x9096, NV9096_CTRL_##cat, idx) + +/* NV9096 command categories (6bits) */ +#define NV9096_CTRL_RESERVED (0x00U) +#define NV9096_CTRL_ZBC (0x01U) + + +/* + * NV9096_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV9096_CTRL_CMD_NULL (0x90960000U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* + * NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_ + * These are various possible CtFormats which + * the Client passes down to RM to set in the DS + * Color Table. + */ + + + +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_INVALID 0x00000000U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_ZERO 0x00000001U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_UNORM_ONE 0x00000002U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_RF32_GF32_BF32_AF32 0x00000004U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_R16_G16_B16_A16 0x00000008U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_RN16_GN16_BN16_AN16 0x0000000cU +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_RS16_GS16_BS16_AS16 0x00000010U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_RU16_GU16_BU16_AU16 0x00000014U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_RF16_GF16_BF16_AF16 0x00000016U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_A8R8G8B8 0x00000018U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_A8RL8GL8BL8 0x0000001cU +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_A2B10G10R10 0x00000020U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_AU2BU10GU10RU10 0x00000024U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_A8B8G8R8 0x00000028U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_A8BL8GL8RL8 0x0000002cU +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_AN8BN8GN8RN8 0x00000030U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_AS8BS8GS8RS8 0x00000034U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_AU8BU8GU8RU8 0x00000038U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_A2R10G10B10 0x0000003cU +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_BF10GF11RF11 0x00000040U + +/* + * NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR + * + * This command attempts to add a new entry to Color ZBC Tables. + * + * colorFB + * This field sets the raw framebuffer values for the ZBC table entries. Prior to + * GA10x, these values are written into the "L2" table. + * From GA10x and later, these values are written in "CROP" table. + * colorDS + * This field sets format-independent values for ZBC table entries. Prior to GA10X, + * these values are written in the "DS" table and matched with the format-independent + * clear color sent in the 3D class. These values are ignored on GA10X and later + * format + * This field specifies color format for ZBC table entries and should be one of the + * NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT* enums. Prior to GA10X, these values + * are written in the format field of the hardware ZBC table entry and are matched + * against the color format sent in the 3D class. These values are ignored on GA10X and later. + * bSkipL2Table + * This parameter specifies if the L2 ZBC table should be updated or not. If + * this parameter is set to a non-zero value, the L2 ZBC table will not be + * updated. If this parameter is set to 0, the L2 ZBC table will be updated. This + * parameter will skip programming DS table values in Pre-GA10x. From GA10x and later + * this parameter will skip programming CROP table entries. + * Note: This parameter will only be supported in verification platforms. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INSUFFICIENT_RESOURCES + */ +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR (0x90960101U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_MESSAGE_ID" */ + +#define NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE 4U +#define NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS { + NvU32 colorFB[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 colorDS[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 format; + NvBool bSkipL2Table; +} NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS; + + +/* + * NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR_FMT_VAL + * These are various possible formats which the Client passes down to RM to set in the ZBC clear + * Table. + * + * Though the "Depth" data written in both the DS as well as L2 Version of the + * depth table are of (only available!) FP32 Format. Still the format + * support is currently given with _CTRL_CMD_SET_ZBC_DEPTH_CLEAR as this format will + * be used later on to disable/remove an entry from the table. + * In future this field is going to be significant for + * "Depth" entries too. + */ + +#define NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR_FMT_VAL_INVALID 0x00000000U +// Fix me: Fix the name to FMT_VAL_FP32 +#define NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR_FMT_FP32 0x00000001U + +/* + * NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR + * + * This command attempts to add a new entry to Depth ZBC Tables. + * + * depth + * This field specifies the ZBC depth clear value to be set. + * format + * This field specifies the Depth format for the data send in by the client. + * bSkipL2Table + * This parameter specifies if the L2 ZBC table should be updated or not. If + * this parameter is set to a non-zero value, the L2 ZBC table will not be + * updated. If this parameter is set to 0, the L2 ZBC table will be updated. + * Note: This parameter will only be supported in verification platforms. + * + + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INSUFFICIENT_RESOURCES + */ +#define NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR (0x90960102U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_MESSAGE_ID" */ + +#define NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS { + NvU32 depth; + NvU32 format; + NvBool bSkipL2Table; +} NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS; + +/* + * NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE + * + * + * This command is used to get the ZBC Clear Color/Depth/Stencil table data i.e. color + * values and the status "Use-satatus" of each value in the table from RM. + * + * colorFB + * This value returns raw framebuffer values for color ZBC table entries. Pre-GA10x, these values + * are taken from the "L2" table. From GA10x+, these values are taken from CROP table. This value is + * set only when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_COLOR" + * colorDS + * Pre-GA10x, returns the DS color value set for ZBC. From GA10x+, returns zeroes since this format is + * deprecated in HW. This value is set only when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_COLOR" + * depth + * This field returns the ZBC depth clear value set, when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_DEPTH". + * stencil + * This field returns the ZBC stencil clear value set, when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_STENCIL" + * format + * This field returns the format of color, depth, or stencil ZBC table entries, using the + * NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT, + * NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR_FMT, + * NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR_FMT* enums depending on the table identified by valType. + * On GA10X and later, color ZBC table entries do not have a format in hardware and this query + * returns a format of "INVALID". + * valType + * This filed specifies the type of the Table data to be fetched. + * Possible Types are : + * NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_COLOR + * NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_DEPTH + * NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_STENCIL + * indexUsed + * This boolean parameter indicates if a particular index of the table is valid or not. + * + * Note: The following parameters are deprecated after Tegra interface is also changed. Clients need + * to use NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_SIZE to query the (start, end) indexes of respective ZBC tables + * + * indexSize + * This parameter is used to fetch the table size when "valType" parameter + * is specified as " 0 ".(INVALID TYPE). It is also used to pass in the + * index of the ZBC table for which we want the COLOR/DEPTH info. + * indexStart + * This parameter is used to return the valid starting index of ZBC table, when + * "valType" parameter is specified as "INVALID_TYPE". It will also be used + * as input index to query the ZBC table for COLOR/QUERY/STENCIL Info. + * indexEnd + * This parameter is used to return the valid ending index of ZBC table, when + * "valType" parameter is specified as "INVALID_TYPE". + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE (0x90960103U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_MESSAGE_ID" */ + +#define NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_INVALID 0U +#define NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_COLOR 1U +#define NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_DEPTH 2U +#define NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_STENCIL 3U +#define NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS { + struct { + NvU32 colorFB[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 colorDS[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 depth; + NvU32 stencil; + } value; + NvU32 indexSize; + NvU32 indexStart; + NvU32 indexEnd; + NvU32 indexUsed; /* TODO: Change to NvBool, need to fix the tegra interface too */ + NvU32 format; + NvU32 valType; +} NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS; + +/* + * Note: This ctrl call is deprecated. To program ZBC table entries, please use + * NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR + * NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR + * NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR + * which will update a single entry in single table at a time. + * + * + * NV9096_CTRL_CMD_SET_ZBC_CLEAR_TABLE + * + * This command is used to set the ZBC Clear Color/Depth/Stencil table data at a specified + * index. The parameters to this command are described below. + * + * colorFB + * This array field specifies the L2 color value to be written to the ZBC table. + * colorDS + * This array field specifies the DS color value to be written to the ZBC table. + * colorFormat + * This field specifies the ZBC color format to be set. This field must be set + * to one of the valid NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL* defines. + * depth + * This field specifies the ZBC depth clear value to be set. + * depthFormat + * This field specifies the ZBC depth format to be set. This field must be set + * to one of the valid NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR_FMT_VAL* defines. + * stencil + * This field specifies the ZBC stencil clear value to be set. + * stencilFormat + * This field specifies the ZBC stencil format to be set. This field must be set + * to one of the valid NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR_FMT_VAL* defines. + * index + * This field specifies the index at which the color/depth data is to be + * written into the ZBC table. Legal values for this field must lie between + * 1 and the value returned in the indexSize parameter of the + * NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE control call when called with the + * parameter valType set to NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_INVALID. + * bSkipL2Table + * This parameter specifies if the L2 ZBC table should be updated or not. If + * this parameter is set to a non-zero value, the L2 ZBC table will not be + * updated. If this parameter is set to 0, the L2 ZBC table will be updated. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_RESOURCES + */ +#define NV9096_CTRL_CMD_SET_ZBC_CLEAR_TABLE (0x90960104U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_SET_ZBC_CLEAR_TABLE_PARAMS_MESSAGE_ID" */ + +#define NV9096_CTRL_SET_ZBC_CLEAR_TABLE_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV9096_CTRL_SET_ZBC_CLEAR_TABLE_PARAMS { + NvU32 colorFB[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 colorDS[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 colorFormat; + NvU32 depth; + NvU32 depthFormat; + NvU32 stencil; + NvU32 stencilFormat; + NvU32 index; + NvBool bSkipL2Table; +} NV9096_CTRL_SET_ZBC_CLEAR_TABLE_PARAMS; + +/* + * NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR_FMT_VAL_ + * These are various possible Formats which the Client passes down to RM to set in the + * ZBC clear(DSS) Table. + */ + +#define NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR_FMT_VAL_INVALID 0x00000000U +// Fix me: Change it to CLEAR_FMT_VAL_U8 +#define NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR_FMT_U8 0x00000001U + +/* + * NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR + * + * This command attempts to add a new entry to Stencil ZBC Tables. + * + * stencil + * This field specifies the ZBC stencil clear value to be set. + * format + * This field specifies the stencil format for the data send in by the client. + * bSkipL2Table + * This parameter specifies if the L2 ZBC table should be updated or not. If + * this parameter is set to a non-zero value, the L2 ZBC table will not be + * updated. If this parameter is set to 0, the L2 ZBC table will be updated. + * Note: This parameter will only be supported in verification platforms. + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INSUFFICIENT_RESOURCES + */ +#define NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR (0x90960105U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_MESSAGE_ID" */ + +#define NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS { + NvU32 stencil; + NvU32 format; + NvBool bSkipL2Table; +} NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS; + +/* + * NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_SIZE + * This command returns the range of valid indices in the color, depth, or stencil ZBC tables. + * + * indexStart + * This parameter is used to return the first valid index in the color, depth, or stencil ZBC table, + * depending on the value passed in the tableType + * indexEnd + * This parameter is used to return the last valid index in the color, depth, or stencil ZBC table, + * depending on the value passed in the tableType + * tableType + * This field specifies the type of the Table data to be fetched. + * Possible Types are : + * NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR + * NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_DEPTH + * NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_STENCIL + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +typedef enum NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE { + NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_INVALID = 0, + NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR = 1, + NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_DEPTH = 2, + NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_STENCIL = 3, + NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT = 4, +} NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE; + +#define NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_SIZE (0x90960106U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS { + NvU32 indexStart; + NvU32 indexEnd; + NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE tableType; +} NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS; + +/* + * NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_ENTRY + * This command returns the ZBC entry stored in the color, depth or stencil ZBC tables + * + * colorFB[out] + * This value returns raw framebuffer values for color ZBC table entries. Pre-GA10x, these values + * are taken from the "L2" table. From GA10x+, these values are taken from CROP table. This value is + * set only when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR" + * colorDS[out] + * Pre-GA10x, returns the DS color value set for ZBC. From GA10x+, returns zeroes since this format is + * deprecated in HW. This value is set only when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR" + * depth[out] + * This field specifies the ZBC depth clear value set, when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_DEPTH". + * stencil[out] + * This field specifies the ZBC stencil clear value set, when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_STENCIL" + * format + * This field returns the format of color, depth, or stencil ZBC table entries, using the + * NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL*, + * NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR_FMT*, + * NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR_FMT* enums depending on the table identified by valType. + * On GA10X and later, color ZBC table entries do not have a format in hardware and this query + * returns a format of "INVALID". + * index[in] + * This field specifies table index for which the ZBC entry information needs to be fetched. + * bIndexValid[out] + * This field specifies whether the entry is valid or not. + * tableType[in] + * This field specifies the type of the Table data to be fetched. + * Possible Types are : + * NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR + * NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_DEPTH + * NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_STENCIL + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_ENTRY (0x90960107U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_MESSAGE_ID" */ + +#define NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS { + struct { + NvU32 colorFB[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 colorDS[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 depth; + NvU32 stencil; + } value; + NvU32 format; + NvU32 index; + NvBool bIndexValid; + NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE tableType; +} NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS; + +/* _ctrl9096_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl90cc.h b/userspace/sdks/nv570/inc/ctrl/ctrl90cc.h new file mode 100644 index 0000000..3b12db4 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl90cc.h @@ -0,0 +1,455 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90cc.finn +// + + + + +#include "ctrl/ctrlxxxx.h" +#include "ctrl90cc/ctrl90ccbase.h" + +#include "ctrl90cc/ctrl90cchwpm.h" + + +#include "ctrl90cc/ctrl90ccpower.h" + + +/* + * NV90CC_CTRL_CMD_PROFILER_RESERVE_HWPM + * + * This command is deprecated; please use NV90CC_CTRL_CMD_HWPM_RESERVE. + * + * This command attempts to reserve the perfmon for use by the calling client. + * If this object was allocated as a child of a subdevice, then the + * reservation will be global among all contexts on that subdevice. If this + * object was allocated as a child of a channel group or a channel, then the + * reservation will only be for the hardware context of that channel group or + * channel. + * + * If the global reservation is held on a subdevice by another client, then + * this command will fail, regardless of the parent class. + * + * If one or more per-context reservations are held by other clients, then + * this command will fail if the parent object is a subdevice or another + * client already holds the perfmon reservation for the parent context. + * + * This command will return NV_ERR_STATE_IN_USE for all of the failure + * cases described above. A return status of NV_OK guarantees + * that the client holds the perfmon reservation of the appropriate scope. + * + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_STATE_IN_USE + */ +#define NV90CC_CTRL_CMD_PROFILER_RESERVE_HWPM NV90CC_CTRL_CMD_HWPM_RESERVE + +/* + * NV90CC_CTRL_CMD_PROFILER_RELEASE_HWPM + * + * This command is deprecated; please use NV90CC_CTRL_CMD_HWPM_RELEASE. + * + * This command releases an existing reservation of the perfmon for the + * calling client. If the calling client does not currently have the perfmon + * reservation as acquired by NV90CC_CTRL_CMD_PROFILER_RESERVE_HWPM, this + * command will return NV_ERR_INVALID_REQUEST. + * + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + */ +#define NV90CC_CTRL_CMD_PROFILER_RELEASE_HWPM NV90CC_CTRL_CMD_HWPM_RELEASE + + + +/* + * NV90CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS + * + * This command is deprecated; please use + * NV90CC_CTRL_CMD_POWER_REQUEST_POWER_FEATURES. + * + * This command attempts to enable or disable various clock-gating features of + * the GPU on behalf of the profiler. If this command is unable to set the + * clock-gating feature state of any of the requested features, this command + * will fail and none of the requested features will be modified. If this + * command fails because one or more clock-gating feature requests were + * rejected, it will return NV_ERR_STATE_IN_USE in the globalStatus + * parameter and the fields in the statusMask parameter for the features for + * which the requests were rejected will have the value + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_REJECTED. + * If a given feature is not supported on the GPU, the field for that clock- + * gating feature will have the value + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_NOT_SUPPORTED in the + * statusMask parameter, but this condition by itself will not cause the + * command to fail. Even if this command fails, the field for clock-gating + * features which would have successfully changed will have the value + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_FULFILLED in the statusMask + * parameter. + * + * Each of the clock-gating features is reference-counted individually, so + * that multiple GF100_PROFILER objects may request and rely on the same + * settings for the features simultaneously. Each clock-gating feature is + * locked to the requested state until the GF100_PROFILER object is freed or + * the NV90CC_CTRL_CMD_PROFILER_RELEASE_CG_CONTROLS command is called for that + * feature. + * + * Currently, only GF100_PROFILER requests for power features using this + * command are reference counted. Changes to the power feature settings made + * either by other control commands or the RM itself may interfere with the + * settings requested by GF100_PROFILER instances. + * + * This command will always return NV_OK when given valid + * parameters. If there is any other failure that prevents the clock-gating + * features from being set appropriately, the globalStatus parameter will + * indicate this and the statusMask parameter will indicate which clock-gating + * feature requests failed and why. + * + * controlMask + * This parameter indicates which clock-gating features the request should + * apply to. This parameter has the following fields: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG + * The value of this field indicates whether this request should apply + * to engine-level clock-gating of the GR engine. Valid values for + * this field are: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_IGNORE + * This value indicates that the GR engine-level clock-gating + * should be ignored. This will not affect the reference count for + * this feature. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_DISABLE + * This value indicates that the GR engine-level clock-gating + * should be disabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_ENABLE + * This value indicates that the GR engine-level clock-gating + * should be enabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG + * The value of this field indicates whether this request should apply + * to block-level clock-gating. Valid values for this field are: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_IGNORE + * This value indicates that block-level clock-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_DISABLE + * This value indicates that block-level clock-gating should be + * disabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_ENABLE + * This value indicates that block-level clock-gating should be + * enabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG + * The value of this field indicates whether this request should apply + * to second-level clock-gating. Valid values for this field are: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_IGNORE + * This value indicates that second-level clock-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_DISABLE + * This value indicates that second-level clock-gating should be + * disabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_ENABLE + * This value indicates that second-level clock-gating should be + * enabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG + * The value of this field indicates whether this request should apply + * to GR engine-level power-gating. Valid values for this field are: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_IGNORE + * This value indicates that engine-level power-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_DISABLE + * This value indicates that engine-level power-gating should be + * disabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_ENABLE + * This value indicates that engine-level power-gating should be + * enabled. + * Note that this field is only temporary to allow reference counting + * restricted to GF100_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN + * The value of this field indicates whether this request should apply + * to SM idle slowdown. Valid values for this field are: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_IGNORE + * This value indicates that SM idle slowdown should be ignored. + * This will not affect the reference count for this feature. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_DISABLE + * This value indicates that SM idle slowdown should be disabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_ENABLE + * This value indicates that SM idle slowdown should be enabled. + * Note that this field is only temporary to allow reference counting + * restricted to GF100_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT + * The value of this field indicates whether this request should apply + * to VAT. Valid values for this field are: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_IGNORE + * This value indicates that VAT should be ignored. + * This will not affect the reference count for this feature. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_DISABLE + * This value indicates that VAT should be disabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_ENABLE + * This value indicates that VAT should be enabled. + * Note that this field is only temporary to allow reference counting + * restricted to GF100_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * globalStatus + * This parameter returns the overall status of the requests for all + * clock-gating controls. If the value of this parameter is not + * NV_OK, none of the clock-gating controls will be set as + * requested. Possible values for this parameter are: + * NV_OK + * This value indicates that all of the clock-gating control requests + * were either fulfilled or not supported on the hardware. + * NV_ERR_INVALID_REQUEST + * This value indicates that at least one of the clock-gating control + * requests were invalid given the GF100_PROFILER instance's + * outstanding requests. + * NV_ERR_STATE_IN_USE + * This value indicates that at least one of the clock-gating controls + * has already been locked to a conflicting state by another + * GF100_PROFILER instance or the RM itself. + * statusMask + * This parameter returns the status of the request to set each clock- + * gating control specified by the controlMask parameter. The fields are + * identical to those of the controlMask parameter. For each field for + * which the corresponding field in the controlMask parameter has the + * value NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_IGNORE, the value is + * undefined. For each field for which the corresponding field in the + * controlMask parameter has the value + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST, the value will be + * one of the following: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_FULFILLED + * This value indicates that the clock-gating feature corresponding to + * the field in question was enabled or disabled according to the + * controlMask parameter, and the reference count for the feature was + * incremented accordingly. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_REJECTED + * This value indicates that the clock-gating feature corresponding to + * the field in question was not set to the expected state according + * to the controlMask parameter because another conflicting request is + * currently outstanding for the clock-gating feature. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_FAILED + * This value indicates that the clock-gating feature corresponding to + * the field in question was not set to the expected state according + * to the controlMask parameter because the attempt to do so failed + * with an error other than a conflicting request. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_NOT_SUPPORTED + * This value indicates that the clock-gating feature corresponding to + * the field in question is not supported on this GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV90CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES + +typedef NV90CC_CTRL_POWER_REQUEST_FEATURES_PARAMS NV90CC_CTRL_PROFILER_REQUEST_CG_CONTROLS_PARAMS; + +/* valid fields for the controlMask and statusMask parameters */ +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG 1:0 +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG 3:2 +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG 5:4 + +/* + * The following are temporary fields for the controlMask and statusMask + * parameters. They are required to reference count their respective features + * until the existing RM controls can be safely updated, and the definitions + * for these features will be removed soon after that. + */ +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG 7:6 +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN 9:8 +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT 11:10 + +/* valid values for fields in the controlMask parameter */ +#define NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE (0x00000000) +#define NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE (0x00000001) +#define NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE (0x00000002) + +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_IGNORE NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_DISABLE NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_ENABLE NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_IGNORE NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_DISABLE NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_ENABLE NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_IGNORE NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_DISABLE NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_ENABLE NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_IGNORE NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_DISABLE NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_ENABLE NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_IGNORE NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_DISABLE NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_ENABLE NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_IGNORE NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_DISABLE NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_ENABLE NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE +/* possible values for fields in the statusMask parameter */ +#define NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED (0x00000000) +#define NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED (0x00000001) +#define NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED (0x00000002) +#define NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED (0x00000003) + +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_FULFILLED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_REJECTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_NOT_SUPPORTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_FAILED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_FULFILLED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_REJECTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_NOT_SUPPORTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_FAILED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_FULFILLED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_REJECTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_NOT_SUPPORTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_FAILED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_FULFILLED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_REJECTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_NOT_SUPPORTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_FAILED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_FULFILLED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_REJECTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_NOT_SUPPORTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_FAILED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_FULFILLED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_REJECTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_NOT_SUPPORTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_FAILED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED + +/* utility masks for the controlMask parameter for all controls */ +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL \ + DRF_SHIFTMASK(NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG) | \ + DRF_SHIFTMASK(NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG) | \ + DRF_SHIFTMASK(NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG) | \ + DRF_SHIFTMASK(NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG) | \ + DRF_SHIFTMASK(NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN) | \ + DRF_SHIFTMASK(NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT) +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_IGNORE \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _IGNORE) +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_DISABLE \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _DISABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _DISABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _DISABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _DISABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _DISABLE)| \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _DISABLE) +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_ENABLE \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _ENABLE) + +/* + * NV90CC_CTRL_CMD_PROFILER_RELEASE_CG_CONTROLS + * + * This command is deprecated; please us + * NV90CC_CTRL_CMD_POWER_RELEASE_FEATURES. + * + * This command releases the GF100_PROFILER's request for the given clock- + * gating features that was previously created by the + * NV90CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS command. If the GF100_PROFILER + * object does not have an outstanding request to one or more of the given + * clock-gating features, those features will be ignored while the other + * feature requests will be released. + * + * After calling this command, the calling client may not rely on the current + * value of any of the released clock-gating features to remain, even if + * several identical requests for the given clock-gating features were made + * using NV90CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS. The RM only reference- + * counts the settings requested by GF100_PROFILER instances - it does not + * reference-count multiple identical requests made using the same + * GF100_PROFILER instance. + * + * All outstanding requests made using this GF100_PROFILER object are + * implicitly released when the GF100_PROFILER is freed. + * + * controlMask + * This parameter indicates which clock-gating features the RM should + * release the GF100_PROFILER's reference to. See + * NV90CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS for valid fields. Valid + * values for each field are: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_IGNORE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_IGNORE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_IGNORE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_IGNORE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_IGNORE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_IGNORE + * This value indicates that the clock-gating feature associated with + * the field should not be released, even if the GF100_PROFILER has an + * outstanding request for it. This will not affect the reference + * count for the feature. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_RELEASE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_RELEASE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_RELEASE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_RELEASE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_RELEASE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_RELEASE + * This value indicates that the GF100_PROFILER's outstanding request + * for the clock-gating feature associated with the field should be + * released. This will decrement the reference count for the feature + * if the GF100_PROFILER has an outstanding request for it. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV90CC_CTRL_CMD_PROFILER_RELEASE_CG_CONTROLS NV90CC_CTRL_CMD_POWER_RELEASE_FEATURES + +typedef NV90CC_CTRL_POWER_RELEASE_FEATURES_PARAMS NV90CC_CTRL_PROFILER_RELEASE_CG_CONTROLS_PARAMS; + +/* + * valid values for the controlMask parameter in addition to + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_IGNORE + */ +#define NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE (0x00000003) + +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_RELEASE NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_RELEASE NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_RELEASE NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_RELEASE NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_RELEASE NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_RELEASE NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE + +/* utility mask for the controlMask parameter for all fields */ +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_RELEASE \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _RELEASE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _RELEASE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _RELEASE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _RELEASE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _RELEASE)| \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _RELEASE) + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl90cc/ctrl90ccbase.h b/userspace/sdks/nv570/inc/ctrl/ctrl90cc/ctrl90ccbase.h new file mode 100644 index 0000000..5a6698b --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl90cc/ctrl90ccbase.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90cc/ctrl90ccbase.finn +// + +#include "ctrl/ctrlxxxx.h" +/* GF100_PROFILER control commands and parameters */ + +#define NV90CC_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x90CC, NV90CC_CTRL_##cat, idx) + +/* GF100_PROFILER command categories (6 bits) */ +#define NV90CC_CTRL_RESERVED (0x00) +#define NV90CC_CTRL_HWPM (0x01) + + +#define NV90CC_CTRL_POWER (0x03) + +/* + * NV90CC_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV90CC_CTRL_CMD_NULL (0x90cc0000) /* finn: Evaluated from "(FINN_GF100_PROFILER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrl90ccbase_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl90cc/ctrl90cchwpm.h b/userspace/sdks/nv570/inc/ctrl/ctrl90cc/ctrl90cchwpm.h new file mode 100644 index 0000000..0abb89a --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl90cc/ctrl90cchwpm.h @@ -0,0 +1,135 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90cc/ctrl90cchwpm.finn +// + +#include "ctrl/ctrl90cc/ctrl90ccbase.h" + +/* GF100_PROFILER HWPM control commands and parameters */ + +/* + * NV90CC_CTRL_CMD_HWPM_RESERVE + * + * This command attempts to reserve the perfmon for use by the calling client. + * If this object was allocated as a child of a subdevice, then the + * reservation will be global among all contexts on that subdevice. If this + * object was allocated as a child of a channel group or a channel, then the + * reservation will only be for the hardware context of that channel group or + * channel. + * + * If the global reservation is held on a subdevice by another client, then + * this command will fail, regardless of the parent class. + * + * If one or more per-context reservations are held by other clients, then + * this command will fail if the parent object is a subdevice or another + * client already holds the perfmon reservation for the parent context. + * + * This command will return NV_ERR_STATE_IN_USE for all of the failure + * cases described above. A return status of NV_OK guarantees + * that the client holds the perfmon reservation of the appropriate scope. + * + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_STATE_IN_USE + */ +#define NV90CC_CTRL_CMD_HWPM_RESERVE (0x90cc0101) /* finn: Evaluated from "(FINN_GF100_PROFILER_HWPM_INTERFACE_ID << 8) | 0x1" */ + +/* + * NV90CC_CTRL_CMD_HWPM_RELEASE + * + * This command releases an existing reservation of the perfmon for the + * calling client. If the calling client does not currently have the perfmon + * reservation as acquired by NV90CC_CTRL_CMD_PROFILER_RESERVE_HWPM, this + * command will return NV_ERR_INVALID_REQUEST. + * + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + */ +#define NV90CC_CTRL_CMD_HWPM_RELEASE (0x90cc0102) /* finn: Evaluated from "(FINN_GF100_PROFILER_HWPM_INTERFACE_ID << 8) | 0x2" */ + +/* + * NV90CC_CTRL_CMD_HWPM_GET_RESERVATION_INFO + * + * This command returns information about any outstanding perfmon + * reservations. If this object was allocated as a child of a subdevice, then + * this command will return information about all reservations on the + * subdevice (global or per-context). If this object was allocated as a child + * of a channel group or channel, then this command will only return + * information about the per-context reservation for that context or the + * global reservation, if one exists. + * + * reservationCount + * This parameter returns the number of outstanding perfmon reservations + * in the applicable scope. If the value of the bGlobal parameter is + * NV_TRUE, then this parameter will have a value of 1. If this object was + * allocated as a child of a channel group or channel, then this parameter + * will have a value of either 0 or 1. If this object was allocated as a + * child of a subdevice and the bGlobal parameter is NV_FALSE, then this + * parameter will return the number of per-context reservations on the + * subdevice. + * pid + * This parameter returns the PID of a process that holds a reservation in + * the applicable scope. If the value of the bGlobal parameter is NV_TRUE, + * then this parameter will be the PID of the process holding the global + * perfmon reservation on the subdevice. Otherwise, if the value of + * reservationCount is greater than 0, the value of this parameter will be + * the PID of one of the process that holds the per-context lock in the + * applicable scope. If the value of the reservationCount parameter is 0, + * the value of this parameter is undefined. + * bGlobal + * This parameter returns whether the outstanding perfmon reservation held + * by any client is global or per-context. If the value of this parameter + * is NV_TRUE, then the value of the reservationCount parameter should be 1 + * and the value of the pid parameter should be the pid of the process + * that holds the global perfmon reservation. The value of this parameter + * will be NV_FALSE when there is no global perfmon reservation. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV90CC_CTRL_CMD_HWPM_GET_RESERVATION_INFO (0x90cc0103) /* finn: Evaluated from "(FINN_GF100_PROFILER_HWPM_INTERFACE_ID << 8) | NV90CC_CTRL_HWPM_GET_RESERVATION_INFO_PARAMS_MESSAGE_ID" */ + +#define NV90CC_CTRL_HWPM_GET_RESERVATION_INFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV90CC_CTRL_HWPM_GET_RESERVATION_INFO_PARAMS { + NvU32 reservationCount; + NvU32 pid; + NvBool bGlobal; +} NV90CC_CTRL_HWPM_GET_RESERVATION_INFO_PARAMS; + + + +/* _ctrl90cchwpm_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl90cc/ctrl90ccpower.h b/userspace/sdks/nv570/inc/ctrl/ctrl90cc/ctrl90ccpower.h new file mode 100644 index 0000000..58bd91e --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl90cc/ctrl90ccpower.h @@ -0,0 +1,403 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90cc/ctrl90ccpower.finn +// + +#include "ctrl/ctrl90cc/ctrl90ccbase.h" + +/* GF100_PROFILER GPU control commands and parameters */ +/* + * NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES + * + * This command attempts to enable or disable various clock-gating features of + * the GPU on behalf of the profiler. If this command is unable to set the + * clock-gating feature state of any of the requested features, this command + * will fail and none of the requested features will be modified. If this + * command fails because one or more clock-gating feature requests were + * rejected, it will return NV_ERR_STATE_IN_USE in the globalStatus + * parameter and the fields in the statusMask parameter for the features for + * which the requests were rejected will have the value + * NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_REJECTED. + * If a given feature is not supported on the GPU, the field for that clock- + * gating feature will have the value + * NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_NOT_SUPPORTED in the + * statusMask parameter, but this condition by itself will not cause the + * command to fail. Even if this command fails, the field for clock-gating + * features which would have successfully changed will have the value + * NV90CC_CTRL_POWER_FEATURE_MASK_*_FULFILLED in the statusMask + * parameter. + * + * Each of the clock-gating features is reference-counted individually, so + * that multiple GF100_PROFILER objects may request and rely on the same + * settings for the features simultaneously. Each clock-gating feature is + * locked to the requested state until the GF100_PROFILER object is freed or + * the NV90CC_CTRL_CMD_POWER_RELEASE_FEATURES command is called for that + * feature. + * + * Currently, only GF100_PROFILER requests for power features using this + * command are reference counted. Changes to the power feature settings made + * either by other control commands or the RM itself may interfere with the + * settings requested by GF100_PROFILER instances. + * + * This command will always return NV_OK when given valid + * parameters. If there is any other failure that prevents the clock-gating + * features from being set appropriately, the globalStatus parameter will + * indicate this and the statusMask parameter will indicate which clock-gating + * feature requests failed and why. + * + * controlMask + * This parameter indicates which clock-gating features the request should + * apply to. This parameter has the following fields: + * NV90CC_CTRL_POWER_FEATURE_MASK_ELCG + * The value of this field indicates whether this request should apply + * to engine-level clock-gating of the GR engine. Valid values for + * this field are: + * NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE + * This value indicates that the GR engine-level clock-gating + * should be ignored. This will not affect the reference count for + * this feature. + * NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_DISABLE + * This value indicates that the GR engine-level clock-gating + * should be disabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_ENABLE + * This value indicates that the GR engine-level clock-gating + * should be enabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_BLCG + * The value of this field indicates whether this request should apply + * to block-level clock-gating. Valid values for this field are: + * NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE + * This value indicates that block-level clock-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_DISABLE + * This value indicates that block-level clock-gating should be + * disabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_ENABLE + * This value indicates that block-level clock-gating should be + * enabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_SLCG + * The value of this field indicates whether this request should apply + * to second-level clock-gating. Valid values for this field are: + * NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE + * This value indicates that second-level clock-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_DISABLE + * This value indicates that second-level clock-gating should be + * disabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_ENABLE + * This value indicates that second-level clock-gating should be + * enabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_ELPG + * The value of this field indicates whether this request should apply + * to GR engine-level power-gating. Valid values for this field are: + * NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE + * This value indicates that engine-level power-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_DISABLE + * This value indicates that engine-level power-gating should be + * disabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_ENABLE + * This value indicates that engine-level power-gating should be + * enabled. + * Note that this field is only temporary to allow reference counting + * restricted to GF100_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN + * The value of this field indicates whether this request should apply + * to SM idle slowdown. Valid values for this field are: + * NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE + * This value indicates that SM idle slowdown should be ignored. + * This will not affect the reference count for this feature. + * NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_DISABLE + * This value indicates that SM idle slowdown should be disabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_ENABLE + * This value indicates that SM idle slowdown should be enabled. + * Note that this field is only temporary to allow reference counting + * restricted to GF100_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * NV90CC_CTRL_POWER_FEATURE_MASK_VAT + * The value of this field indicates whether this request should apply + * to VAT. Valid values for this field are: + * NV90CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE + * This value indicates that VAT should be ignored. + * This will not affect the reference count for this feature. + * NV90CC_CTRL_POWER_FEATURE_MASK_VAT_DISABLE + * This value indicates that VAT should be disabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_VAT_ENABLE + * This value indicates that VAT should be enabled. + * Note that this field is only temporary to allow reference counting + * restricted to GF100_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * globalStatus + * This parameter returns the overall status of the requests for all + * clock-gating controls. If the value of this parameter is not + * NV_OK, none of the clock-gating controls will be set as + * requested. Possible values for this parameter are: + * NV_OK + * This value indicates that all of the clock-gating control requests + * were either fulfilled or not supported on the hardware. + * NV_ERR_INVALID_REQUEST + * This value indicates that at least one of the clock-gating control + * requests were invalid given the GF100_PROFILER instance's + * outstanding requests. + * NV_ERR_STATE_IN_USE + * This value indicates that at least one of the clock-gating controls + * has already been locked to a conflicting state by another + * GF100_PROFILER instance or the RM itself. + * statusMask + * This parameter returns the status of the request to set each clock- + * gating control specified by the controlMask parameter. The fields are + * identical to those of the controlMask parameter. For each field for + * which the corresponding field in the controlMask parameter has the + * value NV90CC_CTRL_POWER_FEATURE_MASK_*_IGNORE, the value is + * undefined. For each field for which the corresponding field in the + * controlMask parameter has the value + * NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST, the value will be + * one of the following: + * NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_FULFILLED + * This value indicates that the clock-gating feature corresponding to + * the field in question was enabled or disabled according to the + * controlMask parameter, and the reference count for the feature was + * incremented accordingly. + * NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_REJECTED + * This value indicates that the clock-gating feature corresponding to + * the field in question was not set to the expected state according + * to the controlMask parameter because another conflicting request is + * currently outstanding for the clock-gating feature. + * NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_FAILED + * This value indicates that the clock-gating feature corresponding to + * the field in question was not set to the expected state according + * to the controlMask parameter because the attempt to do so failed + * with an error other than a conflicting request. + * NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_NOT_SUPPORTED + * This value indicates that the clock-gating feature corresponding to + * the field in question is not supported on this GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES (0x90cc0301) /* finn: Evaluated from "(FINN_GF100_PROFILER_POWER_INTERFACE_ID << 8) | NV90CC_CTRL_POWER_REQUEST_FEATURES_PARAMS_MESSAGE_ID" */ + +#define NV90CC_CTRL_POWER_REQUEST_FEATURES_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV90CC_CTRL_POWER_REQUEST_FEATURES_PARAMS { + NvU32 globalStatus; + NvU32 controlMask; + NvU32 statusMask; +} NV90CC_CTRL_POWER_REQUEST_FEATURES_PARAMS; + +/* valid fields for the controlMask and statusMask parameters */ +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG 1:0 +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG 3:2 +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG 5:4 + +/* + * The following are temporary fields for the controlMask and statusMask + * parameters. They are required to reference count their respective features + * until the existing RM controls can be safely updated, and the definitions + * for these features will be removed soon after that. + */ +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG 7:6 +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN 9:8 +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT 11:10 + +/* valid values for fields in the controlMask parameter */ +#define NV90CC_CTRL_POWER_FEATURE_IGNORE (0x00000000) +#define NV90CC_CTRL_POWER_FEATURE_DISABLE (0x00000001) +#define NV90CC_CTRL_POWER_FEATURE_ENABLE (0x00000002) + +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE NV90CC_CTRL_POWER_FEATURE_IGNORE +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_DISABLE NV90CC_CTRL_POWER_FEATURE_DISABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_ENABLE NV90CC_CTRL_POWER_FEATURE_ENABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE NV90CC_CTRL_POWER_FEATURE_IGNORE +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_DISABLE NV90CC_CTRL_POWER_FEATURE_DISABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_ENABLE NV90CC_CTRL_POWER_FEATURE_ENABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE NV90CC_CTRL_POWER_FEATURE_IGNORE +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_DISABLE NV90CC_CTRL_POWER_FEATURE_DISABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_ENABLE NV90CC_CTRL_POWER_FEATURE_ENABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE NV90CC_CTRL_POWER_FEATURE_IGNORE +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_DISABLE NV90CC_CTRL_POWER_FEATURE_DISABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_ENABLE NV90CC_CTRL_POWER_FEATURE_ENABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE NV90CC_CTRL_POWER_FEATURE_IGNORE +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_DISABLE NV90CC_CTRL_POWER_FEATURE_DISABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_ENABLE NV90CC_CTRL_POWER_FEATURE_ENABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE NV90CC_CTRL_POWER_FEATURE_IGNORE +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_DISABLE NV90CC_CTRL_POWER_FEATURE_DISABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_ENABLE NV90CC_CTRL_POWER_FEATURE_ENABLE +/* possible values for fields in the statusMask parameter */ +#define NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED (0x00000000) +#define NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED (0x00000001) +#define NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED (0x00000002) +#define NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED (0x00000003) + +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_FULFILLED NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_REJECTED NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_NOT_SUPPORTED NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_FAILED NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_FULFILLED NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_REJECTED NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_NOT_SUPPORTED NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_FAILED NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_FULFILLED NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_REJECTED NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_NOT_SUPPORTED NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_FAILED NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_FULFILLED NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_REJECTED NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_NOT_SUPPORTED NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_FAILED NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_FULFILLED NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_REJECTED NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_NOT_SUPPORTED NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_FAILED NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_FULFILLED NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_REJECTED NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_NOT_SUPPORTED NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_FAILED NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED + +/* utility masks for the controlMask parameter for all controls */ +#define NV90CC_CTRL_POWER_FEATURE_MASK_ALL \ + DRF_SHIFTMASK(NV90CC_CTRL_POWER_FEATURE_MASK_ELCG) | \ + DRF_SHIFTMASK(NV90CC_CTRL_POWER_FEATURE_MASK_BLCG) | \ + DRF_SHIFTMASK(NV90CC_CTRL_POWER_FEATURE_MASK_SLCG) | \ + DRF_SHIFTMASK(NV90CC_CTRL_POWER_FEATURE_MASK_ELPG) | \ + DRF_SHIFTMASK(NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN) | \ + DRF_SHIFTMASK(NV90CC_CTRL_POWER_FEATURE_MASK_VAT) +#define NV90CC_CTRL_POWER_FEATURE_MASK_ALL_IGNORE \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _VAT, _IGNORE) +#define NV90CC_CTRL_POWER_FEATURE_MASK_ALL_DISABLE \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _DISABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _DISABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _DISABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _DISABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _DISABLE)| \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _VAT, _DISABLE) +#define NV90CC_CTRL_POWER_FEATURE_MASK_ALL_ENABLE \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _VAT, _ENABLE) + +/* + * NV90CC_CTRL_CMD_POWER_RELEASE_FEATUERS + * + * This command releases the GF100_PROFILER's request for the given clock- + * gating features that was previously created by the + * NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES command. If the GF100_PROFILER + * object does not have an outstanding request to one or more of the given + * clock-gating features, those features will be ignored while the other + * feature requests will be released. + * + * After calling this command, the calling client may not rely on the current + * value of any of the released clock-gating features to remain, even if + * several identical requests for the given clock-gating features were made + * using NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES. The RM only reference- + * counts the settings requested by GF100_PROFILER instances - it does not + * reference-count multiple identical requests made using the same + * GF100_PROFILER instance. + * + * All outstanding requests made using this GF100_PROFILER object are + * implicitly released when the GF100_PROFILER is freed. + * + * controlMask + * This parameter indicates which clock-gating features the RM should + * release the GF100_PROFILER's reference to. See + * NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES for valid fields. Valid + * values for each field are: + * NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE + * NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE + * NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE + * NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE + * NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE + * NV90CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE + * This value indicates that the clock-gating feature associated with + * the field should not be released, even if the GF100_PROFILER has an + * outstanding request for it. This will not affect the reference + * count for the feature. + * NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_RELEASE + * NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_RELEASE + * NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_RELEASE + * NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_RELEASE + * NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_RELEASE + * NV90CC_CTRL_POWER_FEATURE_MASK_VAT_RELEASE + * This value indicates that the GF100_PROFILER's outstanding request + * for the clock-gating feature associated with the field should be + * released. This will decrement the reference count for the feature + * if the GF100_PROFILER has an outstanding request for it. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV90CC_CTRL_CMD_POWER_RELEASE_FEATURES (0x90cc0302) /* finn: Evaluated from "(FINN_GF100_PROFILER_POWER_INTERFACE_ID << 8) | NV90CC_CTRL_POWER_RELEASE_FEATURES_PARAMS_MESSAGE_ID" */ + +#define NV90CC_CTRL_POWER_RELEASE_FEATURES_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV90CC_CTRL_POWER_RELEASE_FEATURES_PARAMS { + NvU32 controlMask; +} NV90CC_CTRL_POWER_RELEASE_FEATURES_PARAMS; + +/* + * valid values for the controlMask parameter in addition to + * NV90CC_CTRL_POWER_FEATURE_MASK_*_IGNORE + */ +#define NV90CC_CTRL_POWER_FEATURE_RELEASE (0x00000003) + +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_RELEASE NV90CC_CTRL_POWER_FEATURE_RELEASE +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_RELEASE NV90CC_CTRL_POWER_FEATURE_RELEASE +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_RELEASE NV90CC_CTRL_POWER_FEATURE_RELEASE +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_RELEASE NV90CC_CTRL_POWER_FEATURE_RELEASE +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_RELEASE NV90CC_CTRL_POWER_FEATURE_RELEASE +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_RELEASE NV90CC_CTRL_POWER_FEATURE_RELEASE + + +/* _ctrl90ccpower_h_ */ + +/* utility mask for the controlMask parameter for all fields */ +#define NV90CC_CTRL_POWER_FEATURE_MASK_ALL_RELEASE \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _RELEASE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _RELEASE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _RELEASE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _RELEASE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _RELEASE)| \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _VAT, _RELEASE) diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl90cd.h b/userspace/sdks/nv570/inc/ctrl/ctrl90cd.h new file mode 100644 index 0000000..6113271 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl90cd.h @@ -0,0 +1,174 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90cd.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV_EVENT_BUFFER control commands and parameters */ + +#define NV_EVENT_BUFFER_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x90CD, NV90CD_CTRL_##cat, idx) + +#define NV90CD_CTRL_RESERVED (0x00) +#define NV90CD_CTRL_EVENT (0x01) + +/* +* NV_EVENT_BUFFER_CTRL_CMD_NULL +* +* This command does nothing. +* This command does not take any parameters. +* +* Possible status values returned are: +* NV_OK +*/ +#define NV_EVENT_BUFFER_CTRL_CMD_NULL (0x90cd0000) /* finn: Evaluated from "(FINN_NV_EVENT_BUFFER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* +* NV_EVENT_BUFFER_CTRL_CMD_ENABLE_EVENTS +* This interface enables all the events that are associated to the event buffer +*/ +#define NV_EVENT_BUFFER_CTRL_CMD_ENABLE_EVENTS (0x90cd0101) /* finn: Evaluated from "(FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID << 8) | 0x1" */ + +#define NV_EVENT_BUFFER_FLAG 0:32 + +/* +* NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY +* This flag defines the kernel behavior when the buffer is full +* +* DEFAULT/DISABLED: By default kernel doesn't assume any policy. To enable events +* an overflow policy has to be set to retain older or newer events +* +* KEEP_OLDEST: kernel would retain older events and drop newer events if the buffer is full +* +* KEEP_NEWEST: kernel would retain newer events and drop older events if the buffer is full +* +*/ +#define NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY 0:1 +#define NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY_DISABLED 0 +#define NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY_KEEP_OLDEST 1 +#define NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY_KEEP_NEWEST 2 +#define NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY_DEFAULT NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY_DISABLED + +/* +* NV_EVENT_BUFFER_CTRL_CMD_ENABLE_EVENTS_PARAMS +* +* enable [IN] +* This field is used to enable or disable events +* +* flags[IN] +* This field sets NV_EVENT_BUFFER_FLAG parameter used to configure event buffer overflow options +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_ARGUMENT +*/ +typedef struct NV_EVENT_BUFFER_CTRL_CMD_ENABLE_EVENTS_PARAMS { + NvBool enable; + NvU32 flags; +} NV_EVENT_BUFFER_CTRL_CMD_ENABLE_EVENTS_PARAMS; + +/* +* NV_EVENT_BUFFER_CTRL_CMD_UPDATE_GET +* This interface allows the user to update get pointers. +* This call is useful in the KEEP_OLDEST policy to update free space available in the buffer. +* In keep oldest policy, kernel adds new entries in the buffer only if there is free space. +* The full/empty decision is made as follows: +* - when GET==PUT, the fifo is empty +* - when GET==PUT+1, the fifo is full +*/ +#define NV_EVENT_BUFFER_CTRL_CMD_UPDATE_GET (0x90cd0102) /* finn: Evaluated from "(FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID << 8) | 0x2" */ + +/* +* NV_EVENT_BUFFER_CTRL_CMD_UPDATE_GET_PARAMS +* +* recordBufferGet [IN] +* Value to be used to update the get offset of record buffer +* +* varDataBufferGet[IN] +* This is the buffer offset up to which user has consumed the vardataBuffer +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_ARGUMENT: if any of the get offsets is greater than respective bufferSize. +*/ +typedef struct NV_EVENT_BUFFER_CTRL_CMD_UPDATE_GET_PARAMS { + NvU32 recordBufferGet; + NvU32 varDataBufferGet; +} NV_EVENT_BUFFER_CTRL_CMD_UPDATE_GET_PARAMS; + +/* + * Send a test event-buffer notification (verification-only) + */ +#define NV_EVENT_BUFFER_CTRL_CMD_VERIF_NOTIFY (0x90cd0103) /* finn: Evaluated from "(FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID << 8) | 0x3" */ + +/* + * Synchronous flush + */ +#define NV_EVENT_BUFFER_CTRL_CMD_FLUSH (0x90cd0104) /* finn: Evaluated from "(FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID << 8) | 0x4" */ + +/* + * post event + */ +#define NV_EVENT_BUFFER_CTRL_CMD_POST_TELEMETRY_EVENT (0x90cd0105) /* finn: Evaluated from "(FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID << 8) | 0x5" */ + + /* + * NV_EVENT_BUFFER_CTRL_CMD_POST_TELEMETRY_EVENT_PARAMS + * + * eventType [IN] + * the NvTelemetry event type. + * typeVersion [IN] + * the version of the event structure + * eventData [IN] + * an array of 256 bytes used to hold the event data. + * eventDataSz [IN] + * the amount of valid data in the eventData buffer. + * varData [IN] + * an array of 256 bytes used to hold the var data. + * varDataSz [IN] + * the amount of valid data in the varData buffer. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +typedef struct NV_EVENT_BUFFER_CTRL_CMD_POST_TELEMETRY_EVENT_PARAMS { + NvU32 eventType; + NvU16 typeVersion; + NvU8 eventData[256]; + NvU16 eventDataSz; + NvU8 varData[256]; + NvU16 varDataSz; +} NV_EVENT_BUFFER_CTRL_CMD_POST_TELEMETRY_EVENT_PARAMS; + +/* _ctr l90cd_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl90e6.h b/userspace/sdks/nv570/inc/ctrl/ctrl90e6.h new file mode 100644 index 0000000..c05837d --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl90e6.h @@ -0,0 +1,137 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90e6.finn +// + +#include "ctrl/ctrlxxxx.h" +#define NV90E6_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0x90E6, NV90E6_CTRL_##cat, idx) + + +/* NV90E6 command categories (6bits) */ +#define NV90E6_CTRL_RESERVED (0x00) +#define NV90E6_CTRL_MASTER (0x01) + + +/* + * NV90E6_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ + +#define NV90E6_CTRL_CMD_NULL (0x90e60000) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_MASTER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV90E6_CTRL_CMD_MASTER_GET_ERROR_INTR_OFFSET_MASK + * + * This command is used to query the offset and mask within the object mapping + * that can be used to query for ECC and NVLINK interrupts. + * + * If a read of the given offset+mask is non-zero then it is possible an ECC or + * an NVLINK error has been reported and not yet handled. If this is true then + * the caller must either wait until the read returns zero or call into the + * corresponding count reporting APIs to get updated counts. + * + * offset + * The offset into a GF100_SUBDEVICE_MASTSER's mapping where the top level + * interrupt register can be found. + * mask + * Compatibility field that contains the same bits as eccMask. This field is + * deprecated and will be removed. + * eccMask + * The mask to AND with the value found at offset to determine if any ECC + * interrupts are pending. + * nvlinkMask + * The mask to AND with the value found at offset to determine if any NVLINK + * interrupts are pending. + * + * Possible return status values are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV90E6_CTRL_CMD_MASTER_GET_ERROR_INTR_OFFSET_MASK (0x90e60101) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_MASTER_MASTER_INTERFACE_ID << 8) | NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS_MESSAGE_ID" */ + +#define NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS { + NvU32 offset; + NvU32 mask; // TODO: remove after all users have switched to use eccMask + NvU32 eccMask; + NvU32 nvlinkMask; +} NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS; + +// TODO: remove once users of this interface have switched to the new name. +#define NV90E6_CTRL_CMD_MASTER_GET_ECC_INTR_OFFSET_MASK NV90E6_CTRL_CMD_MASTER_GET_ERROR_INTR_OFFSET_MASK + +typedef NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS NV90E6_CTRL_MASTER_GET_ECC_INTR_OFFSET_MASK_PARAMS; + +/* + * NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK + * + * This command is used to query the mask within the fastpath register + * (VIRTUAL_FUNCTION_ERR_CONT) that can be used to query for ECC and NVLINK interrupts. + * + * If a read of the given mask is non-zero then it is possible an ECC or + * an NVLINK error has been reported and not yet handled. If this is true then + * the caller must either wait until the read returns zero or call into the + * corresponding count reporting APIs to get updated counts. + * + * [out] eccMask + * The mask to AND with the value found at offset to determine if any ECC + * interrupts are possibly pending. + * [out] nvlinkMask + * The mask to AND with the value found at offset to determine if any NVLINK + * interrupts are possibly pending. + * + * Possible return status values are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK (0x90e60102) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_MASTER_MASTER_INTERFACE_ID << 8) | NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_MESSAGE_ID" */ + +#define NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS { + NvU32 eccMask; + NvU32 nvlinkMask; +} NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS; + +/* _ctrl90e6_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl90e7.h b/userspace/sdks/nv570/inc/ctrl/ctrl90e7.h new file mode 100644 index 0000000..b9a8cf7 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl90e7.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90e7.finn +// + + + +#include "ctrl90e7/ctrl90e7bbx.h" + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl90e7/ctrl90e7base.h b/userspace/sdks/nv570/inc/ctrl/ctrl90e7/ctrl90e7base.h new file mode 100644 index 0000000..2736d6b --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl90e7/ctrl90e7base.h @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90e7/ctrl90e7base.finn +// + +#include "ctrl/ctrlxxxx.h" + +/* GF100_SUBDEVICE_INFOROM control commands and parameters */ + +#define NV90E7_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x90E7, NV90E7_CTRL_##cat, idx) + +/* Command categories (6 bits) */ +#define NV90E7_CTRL_RESERVED (0x00) +#define NV90E7_CTRL_BBX_LEGACY_PRIVILEGED (0xc1) /* finn: Evaluated from "(NV90E7_CTRL_BBX | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */ +#define NV90E7_CTRL_BBX (0x01) +#define NV90E7_CTRL_RPR (0x02) +#define NV90E7_CTRL_RPR_LEGACY_PRIVILEGED (0xc2) /* finn: Evaluated from "(NV90E7_CTRL_RPR | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */ +#define NV90E7_CTRL_PREDICTIVE (0x03) + +/* + * NV90E7_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ + +#define NV90E7_CTRL_CMD_NULL (0x90e70000) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_INFOROM_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl90e7/ctrl90e7bbx.h b/userspace/sdks/nv570/inc/ctrl/ctrl90e7/ctrl90e7bbx.h new file mode 100644 index 0000000..15b88f7 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl90e7/ctrl90e7bbx.h @@ -0,0 +1,122 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90e7/ctrl90e7bbx.finn +// + +#include "nvfixedtypes.h" +#include "ctrl/ctrl90e7/ctrl90e7base.h" + + + +/* + * NV90E7_CTRL_CMD_BBX_GET_LAST_FLUSH_TIME + * + * This command is used to query the last BBX flush timestamp and duration. If BBX has not yet + * been flushed, the status returned is NV_ERR_NOT_READY. + * + * timestamp + * This parameter specifies the start timestamp of the last BBX flush. + * + * durationUs + * This parameter specifies the duration (us) of the last BBX flush. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_READY + * NV_ERR_NOT_SUPPORTED + */ +#define NV90E7_CTRL_CMD_BBX_GET_LAST_FLUSH_TIME (0x90e70113) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_INFOROM_BBX_INTERFACE_ID << 8) | NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS_MESSAGE_ID" */ + +#define NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS { + NV_DECLARE_ALIGNED(NvU64 timestamp, 8); + NvU32 durationUs; +} NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS; + + + +/* + * NV90E7_CTRL_CMD_BBX_GET_TIME_DATA + * + * This command is used to query BBX recorded timing data. + * + * timeStart + * First time (since EPOCH in sec) when RM was loaded and BBX was updated. + * + * timeEnd + * Last time (since EPOCH in sec) when BBX was updated. + * + * timeRun + * Total time (in sec) the GPU was running. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV90E7_CTRL_CMD_BBX_GET_TIME_DATA (0x90e70102) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_INFOROM_BBX_INTERFACE_ID << 8) | NV90E7_CTRL_BBX_GET_TIME_DATA_PARAMS_MESSAGE_ID" */ + +#define NV90E7_CTRL_BBX_GET_TIME_DATA_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV90E7_CTRL_BBX_GET_TIME_DATA_PARAMS { + NvU32 timeStart; + NvU32 timeEnd; + NvU32 timeRun; + NvU32 time24Hours; + NvU32 time100Hours; +} NV90E7_CTRL_BBX_GET_TIME_DATA_PARAMS; + +/* + * NV90E7_CTRL_CMD_BBX_IS_NVM_FLUSH_ENABLED + * + * This command is used to query whether BBX flushing to non-volatile memory is enabled. + * + * bIsEnabled + * Whether BBX flushing to non-volatile memory is enabled. + * bPeriodicFlush + * Whether BBX periodically flushes to non-volatile memory. + * periodicFlushIntervalSec + * The minimum interval (in seconds) between two consecutive periodic BBX flushes + * if periodic flush is enabled. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV90E7_CTRL_CMD_BBX_IS_NVM_FLUSH_ENABLED (0x90e70119) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_INFOROM_BBX_INTERFACE_ID << 8) | NV90E7_CTRL_BBX_IS_NVM_FLUSH_ENABLED_PARAMS_MESSAGE_ID" */ + +#define NV90E7_CTRL_BBX_IS_NVM_FLUSH_ENABLED_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV90E7_CTRL_BBX_IS_NVM_FLUSH_ENABLED_PARAMS { + NvBool bIsEnabled; + NvBool bPeriodicFlush; + NvU32 periodicFlushIntervalSec; +} NV90E7_CTRL_BBX_IS_NVM_FLUSH_ENABLED_PARAMS; + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl90ec.h b/userspace/sdks/nv570/inc/ctrl/ctrl90ec.h new file mode 100644 index 0000000..1ee51f7 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl90ec.h @@ -0,0 +1,124 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90ec.finn +// + +#include "ctrl/ctrlxxxx.h" +/* GK104 HDACODEC control commands and parameters */ + +#define NV90EC_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x90EC, NV90EC_CTRL_##cat, idx) + +/* NV04_DISPLAY_COMMON command categories (6bits) */ +#define NV90EC_CTRL_RESERVED (0x00) +#define NV90EC_CTRL_HDACODEC (0x01) + +/* + * NV90EC_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV90EC_CTRL_CMD_NULL (0x90ec0000) /* finn: Evaluated from "(FINN_GF100_HDACODEC_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV90EC_CTRL_CMD_HDACODEC_SET_CP_READY_ENABLE + * + * This command sets the CP_READY bit. It basically informs RM whether + * the DD has worked upon the HDCP request requested by the Audio driver + * or not. DD asks RM to enable CP_READY bit (by setting CpReadyEnable to NV_TRUE) + * once it is done honouring/dishonouring the request. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the cp ready + * bit should be enabled. The display ID must a dfp display. + * If the displayId is not a dfp, this call will return + * NV_ERR_INVALID_ARGUMENT. + * CpReadyEnable + * This parameter specifies whether to enable (NV_TRUE) or not. If CpReady + * is enabled then AudioCodec can send more HDCP requests. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + * + */ +#define NV90EC_CTRL_CMD_HDACODEC_SET_CP_READY_ENABLE (0x90ec0101) /* finn: Evaluated from "(FINN_GF100_HDACODEC_HDACODEC_INTERFACE_ID << 8) | NV90EC_CTRL_CMD_HDACODEC_SET_CP_READY_ENABLE_PARAMS_MESSAGE_ID" */ + +#define NV90EC_CTRL_CMD_HDACODEC_SET_CP_READY_ENABLE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV90EC_CTRL_CMD_HDACODEC_SET_CP_READY_ENABLE_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bCpReadyEnable; +} NV90EC_CTRL_CMD_HDACODEC_SET_CP_READY_ENABLE_PARAMS; + +/* + * NV90EC_CTRL_CMD_HDACODEC_NOTIFY_AUDIO_EVENT + * + * This command notifies Audio of any events to audio + * like notification of PD bit being set. + * + * audioEvent + * This parameter specifies the event type. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + * + */ +#define NV90EC_CTRL_CMD_HDACODEC_NOTIFY_AUDIO_EVENT (0x90ec0102) /* finn: Evaluated from "(FINN_GF100_HDACODEC_HDACODEC_INTERFACE_ID << 8) | NV90EC_CTRL_HDACODEC_NOTIFY_AUDIO_EVENT_PARAMS_MESSAGE_ID" */ + +#define NV90EC_CTRL_HDACODEC_NOTIFY_AUDIO_EVENT_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV90EC_CTRL_HDACODEC_NOTIFY_AUDIO_EVENT_PARAMS { + NvU32 audioEvent; +} NV90EC_CTRL_HDACODEC_NOTIFY_AUDIO_EVENT_PARAMS; + +/* + * This command notifies audio driver that PD bit is set by DD, by writing to scratch register + */ +#define NV90EC_CTRL_HDACODEC_AUDIOEVENT_PD_BIT_SET (0x00000001) + +/* _ctrl90ec_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrl90f1.h b/userspace/sdks/nv570/inc/ctrl/ctrl90f1.h new file mode 100644 index 0000000..73555b5 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrl90f1.h @@ -0,0 +1,407 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90f1.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "mmu_fmt_types.h" +#include "nvcfg_sdk.h" + +#define GMMU_FMT_MAX_LEVELS 6U + +/* Fermi+ GPU VASpace control commands and parameters */ +#define NV90F1_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x90F1, NV90F1_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NV90F1_CTRL_RESERVED (0x00U) +#define NV90F1_CTRL_VASPACE (0x01U) + +/*! + * Does nothing. + */ +#define NV90F1_CTRL_CMD_NULL (0x90f10000U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/*! + * Get VAS GPU MMU format. + */ +#define NV90F1_CTRL_CMD_VASPACE_GET_GMMU_FORMAT (0x90f10101U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS_MESSAGE_ID" */ + +#define NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS { + /*! + * [in] GPU sub-device handle - this API only supports unicast. + * Pass 0 to use subDeviceId instead. + */ + NvHandle hSubDevice; + + /*! + * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. + */ + NvU32 subDeviceId; + + /*! + * [out] GMMU format struct. This is of RM-internal type "struct GMMU_FMT*" + * which can only be accessed by kernel builds since this is a kernel + * only API. + */ + NV_DECLARE_ALIGNED(NvP64 pFmt, 8); +} NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS; + +/*! + * Get VAS page level information. + */ +#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO (0x90f10102U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID" */ + +typedef struct NV_CTRL_VASPACE_PAGE_LEVEL { + /*! + * Format of this level. + */ + NV_DECLARE_ALIGNED(struct MMU_FMT_LEVEL *pFmt, 8); + + /*! + * Level/Sublevel Formats flattened + */ + NV_DECLARE_ALIGNED(MMU_FMT_LEVEL levelFmt, 8); + NV_DECLARE_ALIGNED(MMU_FMT_LEVEL sublevelFmt[MMU_FMT_MAX_SUB_LEVELS], 8); + + /*! + * Physical address of this page level instance. + */ + NV_DECLARE_ALIGNED(NvU64 physAddress, 8); + + /*! + * Aperture in which this page level instance resides. + */ + NvU32 aperture; + + /*! + * Size in bytes allocated for this level instance. + */ + NV_DECLARE_ALIGNED(NvU64 size, 8); + + /*! + * Entry Index for this offset. + */ + NvU32 entryIndex; +} NV_CTRL_VASPACE_PAGE_LEVEL; + +#define NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS { + /*! + * [in] GPU sub-device handle - this API only supports unicast. + * Pass 0 to use subDeviceId instead. + */ + NvHandle hSubDevice; + + /*! + * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. + */ + NvU32 subDeviceId; + + /*! + * [in] GPU virtual address to query. + */ + NV_DECLARE_ALIGNED(NvU64 virtAddress, 8); + + /*! + * [in] Page size to query. + */ + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); + + /*! + * [in] Flags + * Contains flags to control various aspects of page level info. + */ + NV_DECLARE_ALIGNED(NvU64 flags, 8); + + /*! + * [out] Number of levels populated. + */ + NvU32 numLevels; + + /*! + * [out] Per-level information. + */ + NV_DECLARE_ALIGNED(NV_CTRL_VASPACE_PAGE_LEVEL levels[GMMU_FMT_MAX_LEVELS], 8); +} NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS; + +/* valid flags parameter values */ +#define NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_FLAG_NONE 0x0ULL +#define NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_FLAG_BAR1 NVBIT64(0) + + +/*! + * Reserve (allocate and bind) page directory/table entries up to + * a given level of the MMU format. Also referred to as "lock-down". + * + * Each range that has been reserved must be released + * eventually with @ref NV90F1_CTRL_CMD_VASPACE_RELEASE_ENTRIES. + * A particular VA range and level (page size) combination may only be + * locked down once at a given time, but each level is independent. + */ +#define NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES (0x90f10103U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID" */ + +#define NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS { + /*! + * [in] GPU sub-device handle - this API only supports unicast. + * Pass 0 to use subDeviceId instead. + */ + NvHandle hSubDevice; + + /*! + * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. + */ + NvU32 subDeviceId; + + /*! + * [in] Page size (VA coverage) of the level to reserve. + * This need not be a leaf (page table) page size - it can be + * the coverage of an arbitrary level (including root page directory). + */ + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); + + /*! + * [in] First GPU virtual address of the range to reserve. + * This must be aligned to pageSize. + */ + NV_DECLARE_ALIGNED(NvU64 virtAddrLo, 8); + + /*! + * [in] Last GPU virtual address of the range to reserve. + * This (+1) must be aligned to pageSize. + */ + NV_DECLARE_ALIGNED(NvU64 virtAddrHi, 8); +} NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS; + +/*! + * Release (unbind and free) page directory/table entries up to + * a given level of the MMU format that has been reserved through a call to + * @ref NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES. Also referred to as "unlock". + */ +#define NV90F1_CTRL_CMD_VASPACE_RELEASE_ENTRIES (0x90f10104U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_MESSAGE_ID" */ + +#define NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS { + /*! + * [in] GPU sub-device handle - this API only supports unicast. + * Pass 0 to use subDeviceId instead. + */ + NvHandle hSubDevice; + + /*! + * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. + */ + NvU32 subDeviceId; + + /*! + * [in] Page size (VA coverage) of the level to release. + * This need not be a leaf (page table) page size - it can be + * the coverage of an arbitrary level (including root page directory). + */ + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); + + /*! + * [in] First GPU virtual address of the range to release. + * This must be aligned to pageSize. + */ + NV_DECLARE_ALIGNED(NvU64 virtAddrLo, 8); + + /*! + * [in] Last GPU virtual address of the range to release. + * This (+1) must be aligned to pageSize. + */ + NV_DECLARE_ALIGNED(NvU64 virtAddrHi, 8); +} NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS; + +/*! + * Get VAS page level information without kernel priviledge. This will internally call + * NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO. + */ +#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO_VERIF (0x90f10105U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS_MESSAGE_ID" */ + +#define NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS_MESSAGE_ID (0x5U) + +typedef NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS; + +/*! + * Pin PDEs for a given VA range on the server RM and then mirror the client's page + * directory/tables in the server. + * + * @ref + */ +#define NV90F1_CTRL_CMD_VASPACE_COPY_SERVER_RESERVED_PDES (0x90f10106U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID" */ + +#define NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS { + /*! + * [in] GPU sub-device handle - this API only supports unicast. + * Pass 0 to use subDeviceId instead. + */ + NvHandle hSubDevice; + + /*! + * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. + */ + NvU32 subDeviceId; + + /*! + * [in] Page size (VA coverage) of the level to reserve. + * This need not be a leaf (page table) page size - it can be + * the coverage of an arbitrary level (including root page directory). + */ + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); + + /*! + * [in] First GPU virtual address of the range to reserve. + * This must be aligned to pageSize. + */ + NV_DECLARE_ALIGNED(NvU64 virtAddrLo, 8); + + /*! + * [in] Last GPU virtual address of the range to reserve. + * This (+1) must be aligned to pageSize. + */ + NV_DECLARE_ALIGNED(NvU64 virtAddrHi, 8); + + /*! + * [in] Number of PDE levels to copy. + */ + NvU32 numLevelsToCopy; + + /*! + * [in] Per-level information. + */ + struct { + /*! + * Physical address of this page level instance. + */ + NV_DECLARE_ALIGNED(NvU64 physAddress, 8); + + /*! + * Size in bytes allocated for this level instance. + */ + NV_DECLARE_ALIGNED(NvU64 size, 8); + + /*! + * Aperture in which this page level instance resides. + */ + NvU32 aperture; + + /*! + * Page shift corresponding to the level + */ + NvU8 pageShift; + } levels[GMMU_FMT_MAX_LEVELS]; +} NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS; + +/*! + * Retrieve extra VA range that RM needs to reserve from the OS + */ +#define NV90F1_CTRL_CMD_VASPACE_GET_HOST_RM_MANAGED_SIZE (0x90f10107U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS_MESSAGE_ID" */ +#define NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS { + /*! + * [in] GPU sub-device handle - this API only supports unicast. + * Pass 0 to use subDeviceId instead. + */ + NvHandle hSubDevice; + + /*! + * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. + */ + NvU32 subDeviceId; + + /*! + * [out] The required VA range, in Megabytes + */ + NV_DECLARE_ALIGNED(NvU64 requiredVaRange, 8); +} NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS; + +/*! + * Retrieve info on a VAS heap - used only for the MODS test RandomVATest + */ +#define NV90F1_CTRL_CMD_VASPACE_GET_VAS_HEAP_INFO (0x90f10108U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS_MESSAGE_ID" */ +#define NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS { + /*! + * [in] GPU sub-device handle - this API only supports unicast. + * Pass 0 to use subDeviceId instead. + */ + NvHandle hSubDevice; + + /*! + * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. + */ + NvU32 subDeviceId; + + /*! + * [out] Number of free bytes in the heap + */ + NV_DECLARE_ALIGNED(NvU64 bytesFree, 8); + + /*! + * [out] Number of bytes in the heap + */ + NV_DECLARE_ALIGNED(NvU64 bytesTotal, 8); + + /*! + * [out] Offset of largest free block + */ + NV_DECLARE_ALIGNED(NvU64 largestFreeOffset, 8); + + /*! + * [out] Size of the largest free block + */ + NV_DECLARE_ALIGNED(NvU64 largestFreeSize, 8); + + /*! + * [out] Number of usable free bytes + */ + NV_DECLARE_ALIGNED(NvU64 usableBytesFree, 8); + + /*! + * [out] Number of free blocks + */ + NvU32 numFreeBlocks; +} NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS; + +/* _ctrl90f1_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrla06c.h b/userspace/sdks/nv570/inc/ctrl/ctrla06c.h new file mode 100644 index 0000000..0dc6cc9 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrla06c.h @@ -0,0 +1,438 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla06c.finn +// + + + + +/* + * KEPLER_CHANNEL_GROUP_A control commands and parameters + * + * A channel group is a collection of channels which are executed in a specific + * order by hardware. Hardware will not move from one channel in the group + * until it is finished executing all its work or gives up control to the next + * channel. + * + * Channels are added to the group by allocating them as a child of the + * KEPLER_CHANNEL_GROUP_A object. + * + * A channel in a channel group may be restricted with respect to what objects + * can be allocated on it and what APIs are allowed to operate on the channel. + * For more details on specifics of how groups behave see the Software and + * Hardware documetation for the specific architecture in which you are + * interested. + * + */ + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrla06f/ctrla06fgpfifo.h" /* A06C is partially derived from A06F */ + +#include "ctrl/ctrl2080/ctrl2080internal.h" /* For NV2080_CTRL_INTERNAL_MEMDESC_INFO */ +#include "ctrl/ctrlc36f.h" /* For NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES */ + +#define NVA06C_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xA06C, NVA06C_CTRL_##cat, idx) + +/* KEPLER_CHANNEL_GROUP_A command categories (6bits) */ +#define NVA06C_CTRL_RESERVED (0x00) +#define NVA06C_CTRL_GPFIFO (0x01) +#define NVA06C_CTRL_INTERNAL (0x02) + +/* + * NVA06C_CTRL_CMD_NULL + * + * Please see description of NV906D_CTRL_CMD_NULL. + * + */ +#define NVA06C_CTRL_CMD_NULL (0xa06c0000) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NVA06C_CTRL_CMD_GPFIFO_SCHEDULE + * + * This command schedules a channel group in hardware. This command should be + * called after objects have been allocated on the channel or a call to + * NVA06C_CTRL_CMD_BIND has been made. + * + * See NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for parameter definitions. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_OPERATION + * + */ +#define NVA06C_CTRL_CMD_GPFIFO_SCHEDULE (0xa06c0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */ + +#define NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x1U) + +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS; + +/* + * NVA06C_CTRL_CMD_BIND + * + * This command uses the given engine to configure the group for scheduling. + * It alleviates the need to call NVA06C_CTRL_CMD_GPFIFO_SCHEDULE after objects + * have been allocated. However, it requires that the caller know which engine + * they want to be able to execute in the group. Once this has been called + * only objects that can be allocated on the specified engine or other engines + * allowed to coexist in the group will be allowed. See + * NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST to determine which engines can + * share a parent. + * + * See NVA06F_CTRL_CMD_BIND for parameter definitions. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06C_CTRL_CMD_BIND (0xa06c0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_BIND_PARAMS_MESSAGE_ID" */ + +#define NVA06C_CTRL_BIND_PARAMS_MESSAGE_ID (0x2U) + +typedef NVA06F_CTRL_BIND_PARAMS NVA06C_CTRL_BIND_PARAMS; + +/* + * NVA06C_CTRL_CMD_SET_TIMESLICE + * + * This command modifies the timeslice for a channel group. Hardware may not + * support all possible values, so the input will be rounded down to a valid + * hardware value. + * + * This takes effect immediately, meaning the channel may be forced off of the + * GPU so the change can be made. + * + * timesliceUs + * This parameter is an input containing the desired timeslice in microseconds + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06C_CTRL_CMD_SET_TIMESLICE (0xa06c0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_SET_TIMESLICE_PARAMS_MESSAGE_ID" */ + +typedef struct NVA06C_CTRL_TIMESLICE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 timesliceUs, 8); +} NVA06C_CTRL_TIMESLICE_PARAMS; + +#define NVA06C_CTRL_SET_TIMESLICE_PARAMS_MESSAGE_ID (0x3U) + +typedef NVA06C_CTRL_TIMESLICE_PARAMS NVA06C_CTRL_SET_TIMESLICE_PARAMS; + +/* + * NVA06C_CTRL_CMD_GET_TIMESLICE + * + * This command returns the timeslice for a channel group. If + * NVA06C_CTRL_CMD_SET_TIMESLICE has been used this call will return the exact + * value passed to that function, which may not be exactly what is programmed + * to hardware (see NVA06C_CTRL_CMD_SET_TIMESLICE for more details). + * + * timesliceUs + * This parameter is an output containing current timeslice in microseconds. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06C_CTRL_CMD_GET_TIMESLICE (0xa06c0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_GET_TIMESLICE_PARAMS_MESSAGE_ID" */ + +#define NVA06C_CTRL_GET_TIMESLICE_PARAMS_MESSAGE_ID (0x4U) + +typedef NVA06C_CTRL_TIMESLICE_PARAMS NVA06C_CTRL_GET_TIMESLICE_PARAMS; + +/* + * NVA06C_CTRL_CMD_PREEMPT + * + * This command preempts a channel group. It optionally waits for the preempt to + * complete before returning. + * + * bWait + * If bWait evaluates to NV_TRUE then this control call waits till the preempt + * completes, else it returns immediately after issuing the preempt. Calling + * this control call multiple times with bWait = NV_FALSE without waiting for + * the preempt to complete by some other means can lead to undefined results. + * bManualTimeout + * If bManualTimer evaluates to NV_TRUE then timeoutUs will be used as the + * timeout value. + * timeoutUs + * The desired timeout in microseconds. Only used if bManualTimeout evaluates + * to NV_TRUE. The maximum value of timeoutUs is + * NVA06C_CTRL_CMD_PREEMPT_MAX_MANUAL_TIMEOUT_US. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + * + */ +#define NVA06C_CTRL_CMD_PREEMPT (0xa06c0105) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_PREEMPT_PARAMS_MESSAGE_ID" */ + +#define NVA06C_CTRL_PREEMPT_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVA06C_CTRL_PREEMPT_PARAMS { + NvBool bWait; + NvBool bManualTimeout; + NvU32 timeoutUs; +} NVA06C_CTRL_PREEMPT_PARAMS; + +#define NVA06C_CTRL_CMD_PREEMPT_MAX_MANUAL_TIMEOUT_US (1000000) // 1 second + +/* + * NVA06C_CTRL_CMD_GET_INFO + * + * This command returns information about the channel group. + * + * tsgID + * Output parameter containing the hardware TSG ID for this channel group. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NVA06C_CTRL_CMD_GET_INFO (0xa06c0106) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NVA06C_CTRL_GET_INFO_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NVA06C_CTRL_GET_INFO_PARAMS { + NvU32 tsgID; +} NVA06C_CTRL_GET_INFO_PARAMS; + +/* + * NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL + * + * Used to change the target TSG's interleave level in the runlist. The + * interleave level indicates how often channels in the TSG appear in the + * runlist according to the following policy: + * + * - LOW: Appear once + * - MEDIUM: If L > 0, appear L times + * Else, appear once + * - HIGH: If L > 0, appear (M + 1) * L times + * Else if M > 0, appear M times + * Else, appear once + * where + * - L = # of LOW interleave level TSGs + * - M = # of MEDIUM interleave level TSGs + * + * For safety reasons, setting this property requires PRIVILEGED user level. + * + * tsgInterleaveLevel + * Input parameter. One of: + * - NVA06C_CTRL_INTERLEAVE_LEVEL_LOW + * - NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM + * - NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +#define NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL (0xa06c0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID" */ + +typedef struct NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS { + NvU32 tsgInterleaveLevel; +} NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS; + +#define NVA06C_CTRL_INTERLEAVE_LEVEL_LOW (0x00000000) +#define NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM (0x00000001) +#define NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH (0x00000002) + +#define NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID (0x7U) + +typedef NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS; + +/* + * NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL + * + * Returns the target TSG's interleave level. + * + * tsgInterleaveLevel + * Output parameter. One of: + * - NVA06C_CTRL_INTERLEAVE_LEVEL_LOW + * - NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM + * - NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL (0xa06c0108) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID" */ + +#define NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID (0x8U) + +typedef NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS; + +/* + * NVA06C_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE + * This ctrl call is deprecated in favor of NV0090_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE. + * @see NV0090_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE + */ +#define NVA06C_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE (0xa06c0109) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS_MESSAGE_ID" */ + +typedef enum NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE { + NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_NONE = 0, + NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_64B = 1, + NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_128B = 2, +} NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE; + +typedef struct NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD { + NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE size; +} NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD; + +#define NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS { + NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD l1; + NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD t1; +} NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS; + +/*! + * NVA06C_CTRL_CMD_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS + * + * This control call is used to + * - set the fault method buffer addresses in vGpu host / GSP after the fault + * method buffers are allocated by vGpu guest / GSP_CLIENT during channel + * group allocation + * - destroy the method buffer memory descriptors during channel group free + * + * methodBufferMemdesc [input] + * Details about the memory allocated for method buffer for each runqueue. + * If the size of the memory region is zero, the descriptor will be destroyed. + * + * bar2Addr [input] + * CPU invisible BAR2 address that the method buffer is mapped to for each + * runqueue + * + * numValidEntries [input] + * The number of valid entries upto + * NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES actually filled in + * the control call parameters. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA06C_CTRL_CMD_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS (0xa06c010a) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8 | NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_MESSAGE_ID)" */ + +#define NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES (NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES) + +#define NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_MESSAGE_ID (0xaU) + +typedef struct NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MEMDESC_INFO methodBufferMemdesc[NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES], 8); + NV_DECLARE_ALIGNED(NvU64 bar2Addr[NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES], 8); + NvU32 numValidEntries; +} NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS; + +/* + * NVA06C_CTRL_CMD_MAKE_REALTIME + * + * Promote the specified TSG to realtime, or demote to non-realtime, + * depending on the given bRealtime parameter. A realtime TSG will have the + * highest interleave level when the scheduling policy is CHANNEL_INTERLEAVED, + * and will also precede any non-realtime channel/TSG in the order channels are + * added to the corresponding runlist. + * + * Whenever a realtime TSG is added to a runlist, all non-realtime channels/TSGs + * are made preemptible by setting a COMPUTE preemption mode to CTA. + * + * Preemption modes for realtime TSGs remain WFI. + * + * A client must then issue a NVA06F_CTRL_CMD_RESTART_RUNLIST control call when + * kicking off work on a realtime TSG to preempt non-realtime channels and + * restart the runlist such that the realtime TSG will start executing next. + * + * bRealtime + * Whether the TSG is to be promoted to/demoted from realtime. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAMETER + * NV_ERR_INVALID_OBJECT + * NV_ERR_INVALID_STATE + * NV_ERR_NOT_SUPPORTED + */ +#define NVA06C_CTRL_CMD_MAKE_REALTIME (0xa06c0110) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_MAKE_REALTIME_PARAMS_MESSAGE_ID" */ + +#define NVA06C_CTRL_MAKE_REALTIME_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NVA06C_CTRL_MAKE_REALTIME_PARAMS { + NvBool bRealtime; +} NVA06C_CTRL_MAKE_REALTIME_PARAMS; + + + + + +/* + * NVA06C_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE + * + * This command is an internal command sent from Kernel RM to Physical RM + * to schedule a channel group in hardware. + * + * Please see description of NVA06C_CTRL_CMD_GPFIFO_SCHEDULE for more information. + * + */ +#define NVA06C_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE (0xa06c0201) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID << 8) | NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */ + +#define NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x1U) + +typedef NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS; + +/* + * NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE + * + * This command is an internal command sent from Kernel RM to Physical RM + * to modify the timeslice for a channel group in hardware. + * + * Please see description of NVA06C_CTRL_CMD_SET_TIMESLICE for more information. + * + */ +#define NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE (0xa06c0202) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID << 8) | NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS_MESSAGE_ID" */ + +#define NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS_MESSAGE_ID (0x2U) + +typedef NVA06C_CTRL_TIMESLICE_PARAMS NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS; + +/* _ctrla06c.h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrla06f.h b/userspace/sdks/nv570/inc/ctrl/ctrla06f.h new file mode 100644 index 0000000..c3a0356 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrla06f.h @@ -0,0 +1,36 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla06f.finn +// + + + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrla06f/ctrla06fbase.h" +#include "ctrl/ctrla06f/ctrla06fgpfifo.h" +#include "ctrl/ctrla06f/ctrla06finternal.h" diff --git a/userspace/sdks/nv570/inc/ctrl/ctrla06f/ctrla06fbase.h b/userspace/sdks/nv570/inc/ctrl/ctrla06f/ctrla06fbase.h new file mode 100644 index 0000000..521132e --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrla06f/ctrla06fbase.h @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla06f/ctrla06fbase.finn +// + + + + +/* GK100_GPFIFO control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl906f.h" /* A06F is partially derived from 906F */ + +#define NVA06F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xA06F, NVA06F_CTRL_##cat, idx) + +/* GK100_GPFIFO command categories (6bits) */ +#define NVA06F_CTRL_RESERVED (0x00) +#define NVA06F_CTRL_GPFIFO (0x01) +#define NVA06F_CTRL_INTERNAL (0x03) + +/* + * NVA06F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + * + */ +#define NVA06F_CTRL_CMD_NULL (0xa06f0000) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrla06fbase_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrla06f/ctrla06fgpfifo.h b/userspace/sdks/nv570/inc/ctrl/ctrla06f/ctrla06fgpfifo.h new file mode 100644 index 0000000..65b82d5 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrla06f/ctrla06fgpfifo.h @@ -0,0 +1,261 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla06f/ctrla06fgpfifo.finn +// + +#include "ctrl/ctrla06f/ctrla06fbase.h" + +/* + * NVA06F_CTRL_CMD_GPFIFO_SCHEDULE + * + * This command schedules a channel in hardware. This command should be called + * after objects have been allocated on the channel or a call to + * NVA06F_CTRL_CMD_BIND has been made. + * + * bEnable + * This parameter indicates whether or not the channel should be scheduled in hardware. + * When set, the channel will be enabled in addition to being added to the appropriate runlist. + * When not set, the channel will be disabled and removed from runlist. + * + * bSkipSubmit + * This parameter indicates whether this channel is not to be scheduled, even though it is enabled. + * When set, the channel will not be scheduled. + * When not set, the channel will be scheduled. + * + * bSkipEnable + * This parameter indicates whether this channel is not to be enabled, even though it is scheduled. + * When set, the channel will not be enabled. + * When not set, the channel will be enabled. + * + * When bEnable is set, both bSkipSubmit and bSkipEnable can't be set. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_OPERATION + * + */ +#define NVA06F_CTRL_CMD_GPFIFO_SCHEDULE (0xa06f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */ +#define NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS { + NvBool bEnable; + NvBool bSkipSubmit; + NvBool bSkipEnable; +} NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS; + +/* + * NVA06F_CTRL_CMD_BIND + * + * This command uses the given engine to configure the channel for scheduling. + * It alleviates the need to call NVA06F_CTRL_CMD_GPFIFO_SCHEDULE after objects + * have been allocated. However, it requires that the caller know which engine + * they want to be able to execute on the channel. Once this has been called + * only objects that can be allocated on the specified engine or other engines + * allowed to coexist on the channel will be allowed. See + * NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST to determine which engines can + * share a parent. + * + * engineType + * This parameter specifies an NV2080_ENGINE_TYPE value indicating the + * engine to which this channel should be bound. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06F_CTRL_CMD_BIND (0xa06f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_BIND_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_BIND_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVA06F_CTRL_BIND_PARAMS { + NvU32 engineType; +} NVA06F_CTRL_BIND_PARAMS; + +/* + * NVA06F_CTRL_CMD_SET_ERROR_NOTIFIER + * + * This command sets the channel error notifier of the target channel. + * bNotifyEachChannelInTSG + * When true, the error notifier will be set on every channel in + * the TSG that contains the channel. + * + * Possible status values returned are: + * NV_OK + */ +#define NVA06F_CTRL_CMD_SET_ERROR_NOTIFIER (0xa06f0108) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS { + NvBool bNotifyEachChannelInTSG; +} NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS; + +/* + * NVA06F_CTRL_CMD_SET_INTERLEAVE_LEVEL + * + * Symmetric to NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL, applied to the individual + * target channel. + * + * When belonging to a TSG, same interleave level will be set to every channel + * in the TSG. + * + * channelInterleaveLevel + * Input parameter. One of: + * - NVA06C_CTRL_INTERLEAVE_LEVEL_LOW + * - NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM + * - NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +#define NVA06F_CTRL_CMD_SET_INTERLEAVE_LEVEL (0xa06f0109) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID" */ + +typedef struct NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS { + NvU32 channelInterleaveLevel; +} NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS; + +#define NVA06F_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID (0x9U) + +typedef NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS NVA06F_CTRL_SET_INTERLEAVE_LEVEL_PARAMS; + +/* + * NVA06F_CTRL_CMD_GET_INTERLEAVE_LEVEL + * + * Returns the target channel's interleave level. + * + * channelInterleaveLevel + * Output parameter. One of: + * - NVA06C_CTRL_INTERLEAVE_LEVEL_LOW + * - NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM + * - NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06F_CTRL_CMD_GET_INTERLEAVE_LEVEL (0xa06f0110) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID (0x10U) + +typedef NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS NVA06F_CTRL_GET_INTERLEAVE_LEVEL_PARAMS; + +/* + * NVA06F_CTRL_CMD_RESTART_RUNLIST + * + * This command expires the current timeslice and restarts the runlist the given + * channel belongs to. This effectively preempts the current channel on the + * corresponding engine. + * + * This is useful for clients to trigger preemption manually and reduce start + * latency for higher priority channels as they are added first to the runlist + * if NV0080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED policy is + * configured. + * + * This command interacts with the scheduler and may cause certain low priority + * channels to starve under certain circumstances. Therefore, it is only + * available to privileged clients. + * + * bForceRestart + * Input parameter. If NV_FALSE, the runlist restart will be skipped + * whenever the given channel (or its group) is already running on the + * corresponding engine. + * + * bBypassWait + * Input parameter. If NV_TRUE, the command will return immediately after + * issuing the hardware preemption request, without actually waiting for the + * context switch to complete. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06F_CTRL_CMD_RESTART_RUNLIST (0xa06f0111) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_RESTART_RUNLIST_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_RESTART_RUNLIST_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NVA06F_CTRL_RESTART_RUNLIST_PARAMS { + NvBool bForceRestart; + NvBool bBypassWait; +} NVA06F_CTRL_RESTART_RUNLIST_PARAMS; + +/* + * NVA06F_CTRL_CMD_STOP_CHANNEL + * + * This command is used to stop the channel + * + * Stopping the channel here means disabling and unbinding the channel and removing it from runlist. + * So, if the channel needs to run again, it has to be scheduled, bound and enabled again. + * If we fail to preempt channel or remove it from runlist, then we RC the channel. + * Also set an error notifier to notify user space that channel is stopped. + * + * bImmediate + * Input parameter. If NV_FALSE, we will wait for default RM timeout + * for channel to idle. If NV_TRUE, we don't wait for channel to idle. + * If channel is not idle, we forcefully preempt it off the runlist. + * If the preempt times out, we will RC the channel. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06F_CTRL_CMD_STOP_CHANNEL (0xa06f0112) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_STOP_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_STOP_CHANNEL_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NVA06F_CTRL_STOP_CHANNEL_PARAMS { + NvBool bImmediate; +} NVA06F_CTRL_STOP_CHANNEL_PARAMS; + +/* + * NVA06F_CTRL_CMD_GET_CONTEXT_ID + * + * This command returns the context ID of a given channel. + * + * Possible status values returned are: + * NV_OK + */ +#define NVA06F_CTRL_CMD_GET_CONTEXT_ID (0xa06f0113) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_GET_CONTEXT_ID_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_GET_CONTEXT_ID_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NVA06F_CTRL_GET_CONTEXT_ID_PARAMS { + NvU32 contextId; +} NVA06F_CTRL_GET_CONTEXT_ID_PARAMS; + +/* _ctrla06fgpfifo_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrla06f/ctrla06finternal.h b/userspace/sdks/nv570/inc/ctrl/ctrla06f/ctrla06finternal.h new file mode 100644 index 0000000..354a750 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrla06f/ctrla06finternal.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla06f/ctrla06finternal.finn +// + +#include "ctrl/ctrla06f/ctrla06fbase.h" +#include "ctrl/ctrla06f/ctrla06fgpfifo.h" + +/* + * NVA06F_CTRL_CMD_INTERNAL_STOP_CHANNEL + * + * This command is an internal command sent from Kernel RM to Physical RM + * to stop the channel in hardware + * + * Please see description of NVA06F_CTRL_CMD_STOP_CHANNEL for more information. + * + */ +#define NVA06F_CTRL_CMD_INTERNAL_STOP_CHANNEL (0xa06f0301) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | NVA06F_CTRL_INTERNAL_STOP_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_INTERNAL_STOP_CHANNEL_PARAMS_MESSAGE_ID (0x1U) + +typedef NVA06F_CTRL_STOP_CHANNEL_PARAMS NVA06F_CTRL_INTERNAL_STOP_CHANNEL_PARAMS; + +/* + * NVA06F_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE + * + * This command is an internal command sent from Kernel RM to Physical RM + * to schedule the channel in hardware + * + * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. + * + */ +#define NVA06F_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE (0xa06f0303) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | NVA06F_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U) + +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA06F_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS; + +/* ctrla06finternal_h */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrla080.h b/userspace/sdks/nv570/inc/ctrl/ctrla080.h new file mode 100644 index 0000000..5211a1c --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrla080.h @@ -0,0 +1,438 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla080.finn +// + +#include "ctrl/ctrlxxxx.h" +/* KEPLER_DEVICE_VGPU control commands and parameters */ + +#define NVA080_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xA080, NVA080_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NVA080_CTRL_RESERVED (0x00) +#define NVA080_CTRL_VGPU_DISPLAY (0x01) +#define NVA080_CTRL_VGPU_MEMORY (0x02) +#define NVA080_CTRL_VGPU_OTHERS (0x03) + +/* + * NVA080_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ + +#define NVA080_CTRL_CMD_NULL (0xa0800000) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NVA080_CTRL_CMD_VGPU_DISPLAY_SET_SURFACE_PROPERTIES + * + * This command sets primary surface properties on a virtual GPU in displayless mode + * + * Parameters: + * headIndex + * This parameter specifies the head for which surface properties are + * + * isPrimary + * This parameter indicates whether surface information is for primary surface. set to 1 if its a primary surface. + * + * hMemory + * Memory handle containing the surface (only for RM-managed heaps) + * + * offset + * Offset from base of allocation (hMemory for RM-managed heaps; physical + * memory otherwise) + * + * surfaceType + * This parameter indicates whether surface type is block linear or pitch + * + * surfaceBlockHeight + * This parameter indicates block height for the surface + * + * surfacePitch + * This parameter indicates pitch value for the surface + * + * surfaceFormat + * This parameter indicates surface format (A8R8G8B8/A1R5G5B5) + * + * surfaceWidth + * This parameter indicates width value for the surface + * + * surfaceHeight + * This parameter indicates height value for the surface + * + * surfaceSize + * This parameter indicates size of the surface + * + * surfaceKind + * This parameter indicates surface kind (only for externally-managed + * heaps) + * + * rectX [unused] + * This parameter indicates X coordinate of the region to be displayed + * + * rectY [unused] + * This parameter indicates Y coordinate of the region to be displayed + * + * rectWidth + * This parameter indicates width of the region to be displayed + * + * rectHeight + * This parameter indicates height of the region to be displayed + * + * hHwResDevice + * This parameter indicates the device associated with surface + * + * hHwResHandle + * This parameter indicates the handle to hardware resources allocated to surface + * + * effectiveFbPageSize + * This parameter indicates the actual page size used by KMD for the surface + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_NOT_SUPPORTED + */ + +#define NVA080_CTRL_CMD_VGPU_DISPLAY_SET_SURFACE_PROPERTIES (0xa0800103) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MESSAGE_ID" */ + +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MESSAGE_ID (0x3U) + +typedef struct NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES { + NvU32 headIndex; + NvU32 isPrimary; + NvU32 hMemory; + NvU32 offset; + NvU32 surfaceType; + NvU32 surfaceBlockHeight; + NvU32 surfacePitch; + NvU32 surfaceFormat; + NvU32 surfaceWidth; + NvU32 surfaceHeight; + NvU32 rectX; + NvU32 rectY; + NvU32 rectWidth; + NvU32 rectHeight; + NvU32 surfaceSize; + NvU32 surfaceKind; + NvU32 hHwResDevice; + NvU32 hHwResHandle; + NvU32 effectiveFbPageSize; +} NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES; + +/* valid surfaceType values */ +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MEMORY_LAYOUT 0:0 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MEMORY_LAYOUT_PITCH 0x00000001 +/* valid surfaceBlockHeight values */ +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +/* valid surfaceFormat values */ +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_I8 0x0000001E +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_RF16_GF16_BF16_AF16 0x000000CA +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A8R8G8B8 0x000000CF +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A2B10G10R10 0x000000D1 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_X2BL10GL10RL10_XRBIAS 0x00000022 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A8B8G8R8 0x000000D5 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_R5G6B5 0x000000E8 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A1R5G5B5 0x000000E9 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_R16_G16_B16_A16 0x000000C6 + +/* + * NVA080_CTRL_CMD_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS + * + * This command clears surface information related to head. + * It should be called while shutting down head in displayless mode on virtual GPU + * + * Parameters: + * headIndex + * This parameter specifies the head for which cleanup is requested. + * + * blankingEnabled + * This parameter must be set to 1 to enable blanking. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_NOT_SUPPORTED + */ +#define NVA080_CTRL_CMD_VGPU_DISPLAY_CLEANUP_SURFACE (0xa0800104) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS { + NvU32 headIndex; + NvU32 blankingEnabled; +} NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS; + + + +/*! + * NVA080_CTRL_CMD_SET_FB_USAGE + * + * This command sets the current framebuffer usage value in the plugin. + * + * Parameters: + * fbUsed [in] + * This parameter holds the current FB usage value in bytes. + * + * Possible status values returned are: + * NV_OK + */ +#define NVA080_CTRL_CMD_SET_FB_USAGE (0xa0800204) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVA080_CTRL_SET_FB_USAGE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); +} NVA080_CTRL_SET_FB_USAGE_PARAMS; + + +/* + * NVA080_CTRL_CMD_VGPU_GET_CONFIG + * + * This command returns VGPU configuration information for the associated GPU. + * + * Parameters: + * frameRateLimiter + * This parameter returns value of frame rate limiter + * swVSyncEnabled + * This parameter returns value of SW VSync flag (zero for disabled, + * non-zero for enabled) + * cudaEnabled + * This parameter returns whether CUDA is enabled or not + * pluginPteBlitEnabled + * This parameter returns whether to use plugin pte blit path + * disableWddm1xPreemption + * This parameter returns whether to disable WDDM 1.x Preemption or not + * debugBuffer + * This parameter specifies a pointer to memory which is filled with + * debugging information. + * debugBufferSize + * This parameter specifies the size of the debugging buffer in bytes. + * guestFbOffset + * This parameter returns FB offset start address for VM + * mappableCpuHostAperture + * This parameter returns mappable CPU host aperture size + * linuxInterruptOptimization + * This parameter returns whether stall interrupts are enabled/disabled for + * Linux VM + * vgpuDeviceCapsBits + * This parameter specifies CAP bits to ON/OFF features from guest OS. + * CAPS_SW_VSYNC_ENABLED + * cap bit to indicate if SW VSync flag enabled/disabled. + * Please note, currently, guest doesn't honour this bit. + * CAPS_CUDA_ENABLED + * cap bit to indicate if CUDA enabled/disabled. + * Please note, currently, guest doesn't honour this bit. + * CAPS_WDDM1_PREEMPTION_DISABLED + * cap bit to indicate if WDDM 1.x Preemption disabled/enabled. + * Please note, currently, guest doesn't honour this bit. + * CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED + * cap bit to indicate if stall interrupts are enabled/disabled for + * Linux VM. Please note, currently, guest doesn't honour this bit. + * CAPS_PTE_BLIT_ENABLED + * cap bit to indicate if PTE blit is enabled/disabled. + * Please note, currently, guest doesn't honour this bit. + * CAPS_PDE_BLIT_ENABLED + * cap bit to indicate if PDE blit is enabled/disabled. + * CAPS_GET_PDE_INFO_CTRL_DISABLED + * cap bit to indicate if GET_PDE_INFO RM Ctrl is disabled/enabled. + * CAPS_GUEST_FB_OFFSET_DISABLED + * cap bit to indicate if FB Offset is exposed to guest or not. + * If set, FB Offset is not exposed to guest. + * CAPS_CILP_DISABLED_ON_WDDM + * cap bit to indicate if CILP on WDDM disabled/enabled. + * CAPS_UPDATE_DOORBELL_TOKEN_ENABLED + * cap bit to indicate if guest needs to use doorbell token value updated + * dynamically by host after migration. + * CAPS_SRIOV_ENABLED + * Cap bit to indicate if the vGPU is running in SRIOV mode or not. + * CAPS_GUEST_MANAGED_VA_ENABLED + * Cap bit to indicate if the Guest is managing the VA. + * CAPS_VGPU_1TO1_COMPTAG_ENABLED + * Cap bit to indicate if the 1to1 comptag enabled. This is always TRUE + * when SR-IOV is enabled. + * CAPS_MBP_ENABLED + * Cap bit to indicate if the Mid Buffer Preemption enabled. + * CAPS_ASYNC_MBP_ENABLED + * Cap bit to indicate if the asynchronus Mid buffer Preemption enabled. + * CAPS_TLB_INVALIDATE_ENABLED + * Cap bit to indicate if the vGPU supports TLB Invalidation operation or not. + * CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED + * Cap bit to indicate if the vGPU supports PTE blit for page table updates using BAR1 + * CAPS_SRIOV_HEAVY_ENABLED + * Cap bit to indicate if vGPU is running in SRIOV Heavy mode or not. + * When set true SRIOV Heavy is enabled. + * When set false and CAPS_SRIOV_ENABLED is set true, SRIOV Standard is enabled. + * CAPS_TIMESLICE_OVERRIDE_ENABLED + * Cap bit to indicate whether TSG timeslice override is enabled or not. + * When set true, TSG timeslice override is enabled. + * When false, TSG timeslice override is disabled. + * CAPS_GUEST_HIBERNATION_ENABLED + * Cap bit to indicate whether Guest OS Hibernation is supported or not. + * uvmEnabledFeatures + * This parameter returns mask of UVM enabled features on vGPU. It comprises of + * UVM managed APIs and replayable faults that are enabled or disabled based on + * vGPU version. + * enableKmdSysmemScratch + * This parameter is used to overwrite guest regkey PreferSystemMemoryScratch. + * Setting vgpu parameter "vgpu_enable_kmd_sysmem_scratch" in plugin will + * set this parameter. If the parameter is set, guest moves shader buffer + * allocation from FB to sysmem. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG (0xa0800301) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_OTHERS_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED 0:0 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CUDA_ENABLED 1:1 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CUDA_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CUDA_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_WDDM1_PREEMPTION_DISABLED 2:2 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_WDDM1_PREEMPTION_DISABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_WDDM1_PREEMPTION_DISABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED 3:3 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_ENABLED 4:4 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PDE_BLIT_ENABLED 5:5 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PDE_BLIT_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PDE_BLIT_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GET_PDE_INFO_CTRL_DISABLED 6:6 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GET_PDE_INFO_CTRL_DISABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GET_PDE_INFO_CTRL_DISABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_FB_OFFSET_DISABLED 7:7 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_FB_OFFSET_DISABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_FB_OFFSET_DISABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CILP_DISABLED_ON_WDDM 8:8 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CILP_DISABLED_ON_WDDM_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CILP_DISABLED_ON_WDDM_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_SEMAPHORE_DISABLED 9:9 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_SEMAPHORE_DISABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_SEMAPHORE_DISABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_UPDATE_DOORBELL_TOKEN_ENABLED 10:10 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_UPDATE_DOORBELL_TOKEN_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_UPDATE_DOORBELL_TOKEN_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED 11:11 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_MANAGED_VA_ENABLED 12:12 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_MANAGED_VA_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_MANAGED_VA_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_1TO1_COMPTAG_ENABLED 13:13 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_1TO1_COMPTAG_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_1TO1_COMPTAG_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_MBP_ENABLED 14:14 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_MBP_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_MBP_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_ASYNC_MBP_ENABLED 15:15 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_ASYNC_MBP_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_ASYNC_MBP_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TLB_INVALIDATE_ENABLED 16:16 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TLB_INVALIDATE_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TLB_INVALIDATE_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED 17:17 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED 18:18 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED 19:19 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED 20:20 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_USE_NON_STALL_LINUX_EVENTS 21:21 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_USE_NON_STALL_LINUX_EVENTS_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_USE_NON_STALL_LINUX_EVENTS_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED 22:22 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VF_INVALIDATE_TLB_TRAP_ENABLED 23:23 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VF_INVALIDATE_TLB_TRAP_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VF_INVALIDATE_TLB_TRAP_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPM_ENABLED 24:24 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPM_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPM_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CI_MANIPULATION_ENABLED 25:25 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CI_MANIPULATION_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CI_MANIPULATION_ENABLED_TRUE (0x00000001) + +/* UVM supported features */ +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED 0:0 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_API_ENABLED 1:1 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_API_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_API_ENABLED_TRUE (0x00000001) + +#define NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA080_CTRL_VGPU_GET_CONFIG_PARAMS { + NvU32 frameRateLimiter; + NvU32 swVSyncEnabled; + NvU32 cudaEnabled; + NvU32 pluginPteBlitEnabled; + NvU32 disableWddm1xPreemption; + NvU32 debugBufferSize; + NV_DECLARE_ALIGNED(NvP64 debugBuffer, 8); + NV_DECLARE_ALIGNED(NvU64 guestFbOffset, 8); + NV_DECLARE_ALIGNED(NvU64 mappableCpuHostAperture, 8); + NvU32 linuxInterruptOptimization; + NvU32 vgpuDeviceCapsBits; + NvU32 maxPixels; + NvU32 uvmEnabledFeatures; + NvBool enableKmdSysmemScratch; +} NVA080_CTRL_VGPU_GET_CONFIG_PARAMS; + + + +/* _ctrla080_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrla081.h b/userspace/sdks/nv570/inc/ctrl/ctrla081.h new file mode 100644 index 0000000..e63a7fa --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrla081.h @@ -0,0 +1,1078 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla081.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl2080/ctrl2080gpu.h" +#include "nv_vgpu_types.h" +#include "nvcfg_sdk.h" +/* NVA081_VGPU_CONFIG control commands and parameters */ + +#define NVA081_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xA081, NVA081_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NVA081_CTRL_RESERVED (0x00) +#define NVA081_CTRL_VGPU_CONFIG (0x01) + +#define NVA081_CTRL_VGPU_CONFIG_INVALID_TYPE 0x00 +#define NVA081_MAX_VGPU_TYPES_PER_PGPU 0x80 +#define NVA081_MAX_VGPU_PER_PGPU 48 +#define NVA081_MAX_VGPU_PER_PGPU_NON_MIG 32 +#define NVA081_MAX_VGPU_PER_GI 12 +#define NVA081_VM_UUID_SIZE 16 +#define NVA081_VGPU_STRING_BUFFER_SIZE 64 +#define NVA081_VGPU_SIGNATURE_SIZE 128 +#define NVA081_VM_NAME_SIZE 128 +#define NVA081_PCI_CONFIG_SPACE_SIZE 0x100 +#define NVA081_PGPU_METADATA_STRING_SIZE 256 +#define NVA081_EXTRA_PARAMETERS_SIZE 1024 +#define NVA081_PLACEMENT_ID_INVALID 0xFFFFU +#define NVA081_CONFIG_PARAMS_MAX_LENGTH 1024 + +#define NVA081_MAX_BAR_REGION_COUNT 4 +#define NVA081_MAX_SPARSE_REGION_COUNT 5 + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_SET_INFO + * + * This command sets the vGPU config information in RM + * + * Parameters: + * + * discardVgpuTypes [IN] + * This parameter specifies if existing vGPU configuration should be + * discarded for given pGPU + * + * vgpuInfo [IN] + * This parameter specifies virtual GPU type information + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_SET_INFO (0xa0810101) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NVA081_CTRL_VGPU_CONFIG_INFO + * + * This structure represents the per vGPU information + * + */ +typedef struct NVA081_CTRL_VGPU_INFO { + // This structure should be in sync with NVA082_CTRL_CMD_HOST_VGPU_DEVICE_GET_VGPU_TYPE_INFO_PARAMS + NvU32 vgpuType; + NvU8 vgpuName[NVA081_VGPU_STRING_BUFFER_SIZE]; + NvU8 vgpuClass[NVA081_VGPU_STRING_BUFFER_SIZE]; + NvU8 vgpuSignature[NVA081_VGPU_SIGNATURE_SIZE]; + NvU8 license[NV_GRID_LICENSE_INFO_MAX_LENGTH]; + NvU32 maxInstance; + NvU32 numHeads; + NvU32 maxResolutionX; + NvU32 maxResolutionY; + NvU32 maxPixels; + NvU32 frlConfig; + NvU32 cudaEnabled; + NvU32 eccSupported; + NvU32 gpuInstanceSize; + NvU32 nominalFbRegionSize; + NvU32 multiVgpuSupported; + NV_DECLARE_ALIGNED(NvU64 vdevId, 8); + NV_DECLARE_ALIGNED(NvU64 pdevId, 8); + NV_DECLARE_ALIGNED(NvU64 profileSize, 8); + NV_DECLARE_ALIGNED(NvU64 fbLength, 8); + NV_DECLARE_ALIGNED(NvU64 gspHeapSize, 8); + NV_DECLARE_ALIGNED(NvU64 fbReservation, 8); + NV_DECLARE_ALIGNED(NvU64 mappableVideoSize, 8); + NvU32 encoderCapacity; + NV_DECLARE_ALIGNED(NvU64 bar1Length, 8); + NvU32 frlEnable; + NvU16 vgpuSsvid; + NvU8 adapterName[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + NvU16 adapterName_Unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + NvU8 shortGpuNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + NvU8 licensedProductName[NV_GRID_LICENSE_INFO_MAX_LENGTH]; + NvU32 vgpuExtraParams[NVA081_EXTRA_PARAMETERS_SIZE]; + NvU32 ftraceEnable; + NvU32 gpuDirectSupported; + NvU32 nvlinkP2PSupported; + NvU32 maxInstancePerGI; + NvU32 multiVgpuExclusive; + NvU32 exclusiveType; + NvU32 exclusiveSize; + // used only by NVML + NvU32 gpuInstanceProfileId; + NvU32 placementSize; + NvU32 homogeneousPlacementCount; + NvU32 homogeneousPlacementIds[NVA081_MAX_VGPU_PER_PGPU]; + NvU32 heterogeneousPlacementCount; + NvU32 heterogeneousPlacementIds[NVA081_MAX_VGPU_PER_PGPU]; +} NVA081_CTRL_VGPU_INFO; + +/* + * NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS + * + * This structure represents the vGPU configuration information + * + */ +#define NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS { + NvBool discardVgpuTypes; + NV_DECLARE_ALIGNED(NVA081_CTRL_VGPU_INFO vgpuInfo, 8); + NvU32 vgpuConfigState; +} NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS; + +/* VGPU Config state values */ +#define NVA081_CTRL_VGPU_CONFIG_STATE_UNINITIALIZED 0 +#define NVA081_CTRL_VGPU_CONFIG_STATE_IN_PROGRESS 1 +#define NVA081_CTRL_VGPU_CONFIG_STATE_READY 2 + +/* + * NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU + * + * This command enumerates list of vGPU guest instances per pGpu + * + * Parameters: + * + * vgpuType [OUT] + * This parameter specifies the virtual GPU type for this physical GPU + * + * numVgpu [OUT] + * This parameter specifies the number of virtual GPUs created on this physical GPU + * + * guestInstanceInfo [OUT] + * This parameter specifies an array containing guest instance's information for + * all instances created on this physical GPU + * + * guestVgpuInfo [OUT] + * This parameter specifies an array containing guest vgpu's information for + * all vGPUs created on this physical GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU (0xa0810102) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID" */ + +/* + * NVA081_GUEST_VM_INFO + * + * This structure represents vGPU guest's (VM's) information + * + * vmPid [OUT] + * This param specifies the vGPU plugin process ID + * vmIdType [OUT] + * This param specifies the VM ID type, i.e. DOMAIN_ID or UUID + * guestOs [OUT] + * This param specifies the vGPU guest OS type + * migrationProhibited [OUT] + * This flag indicates whether migration is prohibited for VM or not + * guestNegotiatedVgpuVersion [OUT] + * This param specifies the vGPU version of guest driver after negotiation + * frameRateLimit [OUT] + * This param specifies the current value of FRL set for guest + * licensed [OUT] + * This param specifies whether the VM is Unlicensed/Licensed + * licenseState [OUT] + * This param specifies the current state of the GRID license state machine + * licenseExpiryTimestamp [OUT] + * License expiry time in seconds since UNIX epoch + * licenseExpiryStatus [OUT] + * License expiry status + * guestDriverVersion [OUT] + * This param specifies the driver version of the driver installed on the VM + * guestDriverBranch [OUT] + * This param specifies the driver branch of the driver installed on the VM + * vmName [OUT] + * This param stores the name assigned to VM (KVM only) + * guestVmInfoState [OUT] + * This param stores the current state of guest dependent fields + * + */ +typedef struct NVA081_GUEST_VM_INFO { + NvU32 vmPid; + VM_ID_TYPE vmIdType; + NvU32 guestOs; + NvU32 migrationProhibited; + NvU32 guestNegotiatedVgpuVersion; + NvU32 frameRateLimit; + NvBool licensed; + NvU32 licenseState; + NvU32 licenseExpiryTimestamp; + NvU8 licenseExpiryStatus; + NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); + NvU8 guestDriverVersion[NVA081_VGPU_STRING_BUFFER_SIZE]; + NvU8 guestDriverBranch[NVA081_VGPU_STRING_BUFFER_SIZE]; + NvU8 vmName[NVA081_VM_NAME_SIZE]; + GUEST_VM_INFO_STATE guestVmInfoState; +} NVA081_GUEST_VM_INFO; + +/* + * NVA081_GUEST_VGPU_DEVICE + * + * This structure represents host vgpu device's (assigned to VM) information + * + * eccState [OUT] + * This parameter specifies the ECC state of the virtual GPU. + * One of NVA081_CTRL_ECC_STATE_xxx values. + * bDriverLoaded [OUT] + * This parameter specifies whether driver is loaded on this particular vGPU. + * swizzId [OUT] + * This param specifies the GPU Instance ID or Swizz ID + * placementId [OUT] + * This param specifies the placement ID of heterogeneous timesliced vGPU instance. + * Otherwise it is NVA081_PLACEMENT_ID_INVALID. + * vgpuDevName [OUT] + * This param specifies the VF BDF of the virtual GPU. + * + */ +typedef struct NVA081_HOST_VGPU_DEVICE { + NvU32 vgpuType; + NvU32 vgpuDeviceInstanceId; + NV_DECLARE_ALIGNED(NvU64 vgpuPciId, 8); + NvU8 vgpuUuid[VM_UUID_SIZE]; + NvU8 vgpuDevName[VM_UUID_SIZE]; + NvU32 encoderCapacity; + NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); + NvU32 eccState; + NvBool bDriverLoaded; + NvU32 swizzId; + NvU32 placementId; + NvU32 accountingPid; +} NVA081_HOST_VGPU_DEVICE; + +/* ECC state values */ +#define NVA081_CTRL_ECC_STATE_UNKNOWN 0 +#define NVA081_CTRL_ECC_STATE_NOT_SUPPORTED 1 +#define NVA081_CTRL_ECC_STATE_DISABLED 2 +#define NVA081_CTRL_ECC_STATE_ENABLED 3 + +/* + * NVA081_VGPU_GUEST + * + * This structure represents a vGPU guest + * + */ +typedef struct NVA081_VGPU_GUEST { + NV_DECLARE_ALIGNED(NVA081_GUEST_VM_INFO guestVmInfo, 8); + NV_DECLARE_ALIGNED(NVA081_HOST_VGPU_DEVICE vgpuDevice, 8); +} NVA081_VGPU_GUEST; + +/* + * NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS + * + * This structure represents the information of vGPU guest instances per pGpu + * + */ +#define NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS { + NvU32 vgpuType; + NvU32 numVgpu; + NV_DECLARE_ALIGNED(NVA081_VGPU_GUEST vgpuGuest[NVA081_MAX_VGPU_PER_PGPU], 8); +} NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_VGPU_TYPE_INFO + * + * This command fetches vGPU type info from RM. + * + * Parameters: + * + * vgpuType [IN] + * This parameter specifies the virtual GPU type for which vGPU info should be returned. + * + * vgpuTypeInfo [OUT] + * This parameter returns NVA081_CTRL_VGPU_INFO data for the vGPU type specified by vgpuType. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ + +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_VGPU_TYPE_INFO (0xa0810103) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS + * + */ +#define NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS { + NvU32 vgpuType; + NV_DECLARE_ALIGNED(NVA081_CTRL_VGPU_INFO vgpuTypeInfo, 8); +} NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS; + +/* + * NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS + * This structure represents supported/creatable vGPU types on a pGPU + */ +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS { + /* + * [IN] GPU Instance ID or Swizz ID + */ + NvU32 gpuInstanceId; + + /* + * [OUT] vGPU config state on a pGPU + */ + NvU32 vgpuConfigState; + + /* + * [OUT] Count of supported/creatable vGPU types on a pGPU + */ + NvU32 numVgpuTypes; + + /* + * [OUT] - Array of vGPU type ids supported/creatable on a pGPU + */ + NvU32 vgpuTypes[NVA081_MAX_VGPU_TYPES_PER_PGPU]; +} NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS; + + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES + * + * This command fetches count and list of vGPU types supported on a pGpu from RM + * + * Parameters: + * + * numVgpuTypes [OUT] + * This parameter returns the number of vGPU types supported on this pGPU + * + * vgpuTypes [OUT] + * This parameter returns list of supported vGPUs types on this pGPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + */ + +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES (0xa0810104) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES_PARAMS_MESSAGE_ID (0x4U) + +typedef NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS NVA081_CTRL_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES + * + * This command fetches count and list of vGPU types creatable on a pGpu from RM + * + * Parameters: + * + * numVgpuTypes [OUT] + * This parameter returns the number of vGPU types creatable on this pGPU + * + * vgpuTypes [OUT] + * This parameter returns list of creatable vGPUs types on this pGPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + */ + +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES (0xa0810105) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES_PARAMS_MESSAGE_ID (0x5U) + +typedef NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_EVENT_SET_NOTIFICATION + * + * This command sets event notification state for the associated subdevice/pGPU. + * This command requires that an instance of NV01_EVENT has been previously + * bound to the associated subdevice object. + * + * event + * This parameter specifies the type of event to which the specified + * action is to be applied. This parameter must specify a valid + * NVA081_NOTIFIERS value (see cla081.h for more details) and should + * not exceed one less NVA081_NOTIFIERS_MAXCOUNT. + * action + * This parameter specifies the desired event notification action. + * Valid notification actions include: + * NVA081_CTRL_SET_EVENT_NOTIFICATION_DISABLE + * This action disables event notification for the specified + * event for the associated subdevice object. + * NVA081_CTRL_SET_EVENT_NOTIFICATION_SINGLE + * This action enables single-shot event notification for the + * specified event for the associated subdevice object. + * NVA081_CTRL_SET_EVENT_NOTIFICATION_REPEAT + * This action enables repeated event notification for the specified + * event for the associated system controller object. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_EVENT_SET_NOTIFICATION (0xa0810106) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS { + NvU32 event; + NvU32 action; +} NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS; + + +/* valid event action values */ +#define NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001) +#define NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002) + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_UPDATE_PGPU_INFO + * + * This command register the GPU to Linux kernel's mdev module for vGPU on KVM. + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_UPDATE_PGPU_INFO (0xa0810109) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | 0x9" */ + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_SET_VGPU_INSTANCE_ENCODER_CAPACITY + * + * This command is used to set vGPU instance's (represented by vgpuUuid) encoder Capacity. + * + * vgpuUuid + * This parameter specifies the uuid of vGPU assigned to VM. + * encoderCapacity + * Encoder capacity value from 0 to 100. Value of 0x00 indicates encoder performance + * may be minimal for this GPU and software should fall back to CPU-based encode. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVA081_CTRL_CMD_VGPU_CONFIG_SET_VGPU_INSTANCE_ENCODER_CAPACITY (0xa0810110) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS_MESSAGE_ID" */ + +/* + * NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS + * + * This structure represents encoder capacity for vgpu instance. + */ +#define NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS { + NvU8 vgpuUuid[VM_UUID_SIZE]; + NvU32 encoderCapacity; +} NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_VGPU_FB_USAGE + * + * This command is used to get the FB usage of all vGPU instances running on a GPU. + * + * vgpuCount + * This field specifies the number of vGPU devices for which FB usage is returned. + * vgpuFbUsage + * This is an array of type NVA081_VGPU_FB_USAGE, which contains a list of vGPUs + * and their corresponding FB usage in bytes; + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_VGPU_FB_USAGE (0xa0810111) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID" */ + +typedef struct NVA081_VGPU_FB_USAGE { + NvU8 vgpuUuid[VM_UUID_SIZE]; + NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); +} NVA081_VGPU_FB_USAGE; + +/* + * NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS + * + * This structure represents the FB usage information of vGPU instances running on a GPU. + */ +#define NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS { + NvU32 vgpuCount; + NV_DECLARE_ALIGNED(NVA081_VGPU_FB_USAGE vgpuFbUsage[NVA081_MAX_VGPU_PER_PGPU], 8); +} NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP + * + * This command is used to query whether pGPU is live migration capable or not. + * + * bMigrationCap + * Set to NV_TRUE if pGPU is migration capable. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_REQUEST + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP (0xa0810112) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS_MESSAGE_ID" */ + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS { + NvBool bMigrationCap; +} NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_HOST_FB_RESERVATION + * + * This command is used to get the host FB requirements + * + * hostReservedFb [OUT] + * Amount of FB reserved for the host + * eccAndPrReservedFb [OUT] + * Amount of FB reserved for the ecc and page retirement + * totalReservedFb [OUT] + * Total FB reservation + * vgpuTypeId [IN] + * The Type ID for VGPU profile + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_HOST_FB_RESERVATION (0xa0810113) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS { + NV_DECLARE_ALIGNED(NvU64 hostReservedFb, 8); + NV_DECLARE_ALIGNED(NvU64 eccAndPrReservedFb, 8); + NV_DECLARE_ALIGNED(NvU64 totalReservedFb, 8); + NvU32 vgpuTypeId; +} NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_PGPU_METADATA_STRING + * + * This command is used to get the pGpu metadata string. + * + * pGpuString + * String holding pGpu Metadata + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_STATE + * NV_ERR_INSUFFICIENT_RESOURCES + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_PGPU_METADATA_STRING (0xa0810114) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS { + NvU8 pGpuString[NVA081_PGPU_METADATA_STRING_SIZE]; +} NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS; + +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT (0xa0810115) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS { + NvBool doorbellEmulationEnabled; +} NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_FREE_SWIZZID + * + * This command is used to get free swizzid from RM + * + * gpuPciId [IN] + * This param specifies the PCI device ID of VF on which VM is running + * + * vgpuTypeId [IN] + * This param specifies the Type ID for VGPU profile + * + * swizzId [OUT] + * This param specifies the GPU Instance ID or Swizz ID + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_FREE_SWIZZID (0xa0810116) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS { + NvU32 gpuPciId; + NvU32 vgpuTypeId; + NvU32 swizzId; +} NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS; + +/* + * NVA081_CTRL_CMD_PGPU_GET_MULTI_VGPU_SUPPORT_INFO + * + * This command is used to get multi vGPU related info for the physical GPU. + * + * fractionalmultiVgpuSupported [OUT] + * This param specifies whether fractional multi-vGPU is supported + * + * heterogeneousTimesliceProfilesSupported [OUT] + * This param specifies whether concurrent execution of timesliced vGPU profiles of differing types is supported + * + * heterogeneousTimesliceSizesSupported [OUT] + * This param specifies whether concurrent execution of timesliced vGPU profiles of differing framebuffer sizes is supported + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVA081_CTRL_CMD_PGPU_GET_MULTI_VGPU_SUPPORT_INFO (0xa0810117) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS_MESSAGE_ID (0x17U) + +typedef struct NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS { + NvU32 fractionalmultiVgpuSupported; + NvU32 heterogeneousTimesliceProfilesSupported; + NvU32 heterogeneousTimesliceSizesSupported; +} NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS; + +/* + * NVA081_CTRL_CMD_GET_VGPU_DRIVER_CAPS + * + * This command is used to get vGPU driver capabilities. + * + * heterogeneousMultiVgpuSupported [OUT] + * This param specifies whether heterogeneous multi-vGPU is supported + * warmUpdateSupported [OUT] + * This param specifies FSR / warm driver update operation is supported + * ie. supports FSR and warm update of vGPU host driver without terminating the running guest VM + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVA081_CTRL_CMD_GET_VGPU_DRIVER_CAPS (0xa0810118) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS { + NvU32 heterogeneousMultiVgpuSupported; + NvU32 warmUpdateSupported; +} NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_SET_PGPU_INFO + * + * This command is to set pgpu info + * + * fractionalMultiVgpu [IN] + * This param specifies the fractional multivgpu is enabled or disabled on GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ + +#define NVA081_CTRL_CMD_VGPU_CONFIG_SET_PGPU_INFO (0xa0810119) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS { + NvU32 fractionalMultiVgpu; +} NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_VALIDATE_SWIZZID + * + * This command is used to vallidate input swizzid from RM + * + * vgpuTypeId [IN] + * This param specifies the Type ID for VGPU profile + * + * swizzId [IN] + * This param specifies the GPU Instance ID or Swizz ID + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_VALIDATE_SWIZZID (0xa081011a) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS_MESSAGE_ID (0x1aU) + +typedef struct NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS { + NvU32 vgpuTypeId; + NvU32 swizzId; +} NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_UPDATE_PLACEMENT_INFO + * + * This command is used to get a placement Id from RM for timesliced + * heterogeneous or homogeneous vGPUs. The physical GPU shall be used + * in either heterogeneous or homogeneous mode at a time. + * + * isHeterogeneousEnabled [OUT] + * This param specific whether timesliced heterogeneous vGPU is enabled + * for different FB sized profiles. + * + * placementId [IN / OUT] + * This param specifies the input placement ID provided by hypervisor + * or output placement ID reserved by RM for vGPU type ID. + * + * vgpuTypeId [IN] + * This param specifies the Type ID for VGPU profile + * + * vgpuDevName [IN] + * This param specifies the VF BDF of the virtual GPU. + * + * guestFbLength [OUT] + * This param specifies the FB size assigned to the VM. + * + * guestFbOffset [OUT] + * This param specifies the starting FB offset assigned to the VM. + * + * gspHeapOffset [OUT] + * This param specifies the heap offset of gsp vgpu task. + * + * guestBar1PFOffset [OUT] + * This param specifies the starting PF BAR1 offset assigned to the VM. + * Only applicable for the legacy GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_UPDATE_PLACEMENT_INFO (0xa081011b) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_UPDATE_PLACEMENT_INFO_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_UPDATE_PLACEMENT_INFO_PARAMS_MESSAGE_ID (0x1bU) + +typedef struct NVA081_CTRL_VGPU_CONFIG_UPDATE_PLACEMENT_INFO_PARAMS { + NvBool isHeterogeneousEnabled; + NvU16 placementId; + NvU32 vgpuTypeId; + NvU8 vgpuDevName[VM_UUID_SIZE]; + NV_DECLARE_ALIGNED(NvU64 guestFbLength, 8); + NV_DECLARE_ALIGNED(NvU64 guestFbOffset, 8); + NV_DECLARE_ALIGNED(NvU64 gspHeapOffset, 8); + NV_DECLARE_ALIGNED(NvU64 guestBar1PFOffset, 8); +} NVA081_CTRL_VGPU_CONFIG_UPDATE_PLACEMENT_INFO_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS + * + * This command fetches count and list of creatable vGPU placements + * + * Parameters: + * + * gpuInstanceId [IN] + * GPU Instance ID or Swizz ID + * + * vgpuTypeId [IN] + * The client provided vGPU type ID + * + * placementSize [OUT] + * The number of placement slots occupied by the vGPU type + * + * count [OUT] + * This parameter returns the number of placements supported for the vGPU + * + * placementIds [OUT] + * Array of creatable placement IDs + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + */ + +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS (0xa081011c) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS_MESSAGE_ID (0x1cU) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS { + NvU32 gpuInstanceId; + NvU32 vgpuTypeId; + NvU32 placementSize; + NvU32 count; + NvU32 placementIds[NVA081_MAX_VGPU_PER_PGPU]; +} NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS; + +/* + * NVA081_CTRL_CMD_PGPU_GET_VGPU_STREAMING_CAPABILITY + * + * This command is used to get streaming capability for the physical GPU. + * + * streamingCapability [OUT] + * This param specifies whether vGPU profiles on the GPU supports migration data streaming + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA081_CTRL_CMD_PGPU_GET_VGPU_STREAMING_CAPABILITY (0xa081011d) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS_MESSAGE_ID (0x1dU) + +typedef struct NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS { + NvBool streamingCapability; +} NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS; + +/* vGPU capabilities */ +#define NVA081_CTRL_VGPU_CAPABILITY_MINI_QUARTER_GPU 0 +#define NVA081_CTRL_VGPU_CAPABILITY_COMPUTE_MEDIA_ENGINE_GPU 1 +#define NVA081_CTRL_VGPU_CAPABILITY_WARM_UPDATE 2 +#define NVA081_CTRL_VGPU_CAPABILITY_DEVICE_STREAMING 3 +#define NVA081_CTRL_VGPU_CAPABILITY_READ_DEVICE_BUFFER_BW 4 +#define NVA081_CTRL_VGPU_CAPABILITY_WRITE_DEVICE_BUFFER_BW 5 +#define NVA081_CTRL_VGPU_CAPABILITY_HETEROGENEOUS_TIMESLICE_SIZES 6 +#define NVA081_CTRL_VGPU_CAPABILITY_HETEROGENEOUS_TIMESLICE_PROFILES 7 +#define NVA081_CTRL_VGPU_CAPABILITY_FRACTIONAL_MULTI_VGPU 8 +#define NVA081_CTRL_VGPU_CAPABILITY_HOMOGENEOUS_PLACEMENT_ID 9 + +#define NVA081_CTRL_VGPU_CAPABILITY_MIG_TIMESLICING_SUPPORTED 10 +#define NVA081_CTRL_VGPU_CAPABILITY_MIG_TIMESLICING_MODE_ENABLED 11 + + + +/* + * NVA081_CTRL_CMD_VGPU_SET_CAPABILITY + * + * This command is used to set vGPU capability for the physical GPU. + * + * capability [IN] + * This param specifies the requested capabiity of the device that is to be set + * One of NVA081_CTRL_VGPU_CAPABILITY* values + * + * state [IN] + * This param specifies the state of the capability + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA081_CTRL_CMD_VGPU_SET_CAPABILITY (0xa081011e) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS_MESSAGE_ID (0x1eU) + +typedef struct NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS { + NvU32 capability; + NvBool state; +} NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_GET_CAPABILITY + * + * This command is to get state of vGPU capability for the physical GPU. + * + * capability [IN] + * This param specifies the requested capabiity of the device that is to be set + * One of NVA081_CTRL_VGPU_CAPABILITY* values + * + * state [OUT] + * This param specifies the state of the capability + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA081_CTRL_CMD_VGPU_GET_CAPABILITY (0xa081011f) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_GET_CAPABILITY_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_GET_CAPABILITY_PARAMS_MESSAGE_ID (0x1fU) + +typedef struct NVA081_CTRL_VGPU_GET_CAPABILITY_PARAMS { + NvU32 capability; + NvU32 state; +} NVA081_CTRL_VGPU_GET_CAPABILITY_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_SET_VM_NAME + * + * This command is to set VM name for the host. + * + * vmIdType [IN] + * This param provides the guest VM ID type based on the host. + * + * guestVmId [IN] + * This param provides the guest VM indentifier to RM based on the host. + * + * vmName [IN] + * This param provides the VM name of the vGPU device attached + * to the above mentioned host VM. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVA081_CTRL_CMD_VGPU_SET_VM_NAME (0xa0810120) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_SET_VM_NAME_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_SET_VM_NAME_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NVA081_CTRL_VGPU_SET_VM_NAME_PARAMS { + VM_ID_TYPE vmIdType; + NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); + NvU8 vmName[NVA081_VM_NAME_SIZE]; +} NVA081_CTRL_VGPU_SET_VM_NAME_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_GET_BAR_INFO + * + * This command is to get the bar info for a vGPU. + * + * gpuPciId [IN] + * This param specifies the PCI device ID of VF on which VM is running + * + * vgpuName [IN] + * This param provides the vGPU device name to RM. + * + * configParams [IN] + * This param provides the vGPU config params to RM + * + * barSizes [OUT] + * This param provides the BAR size for each region index of the device + * + * sparseOffsets [OUT] + * This param provides the offset of each sparse mmap region in BAR0 + * + * sparseSizes [OUT] + * This param provides the size of each sparse mmap region in BAR0 + * + * sparseCount [OUT] + * This param provides the number of sparse mmap regions in BAR0 + * + * isBar064bit [OUT] + * This param provides whether the BAR0 is 64bit of the vGPU device + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVA081_CTRL_CMD_VGPU_GET_BAR_INFO (0xa0810121) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_GET_BAR_INFO_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_GET_BAR_INFO_PARAMS_MESSAGE_ID (0x21U) + +typedef struct NVA081_CTRL_VGPU_GET_BAR_INFO_PARAMS { + NvU32 gpuPciId; + NvU8 vgpuName[VM_UUID_SIZE]; + NvU8 configParams[NVA081_CONFIG_PARAMS_MAX_LENGTH]; + NV_DECLARE_ALIGNED(NvU64 barSizes[NVA081_MAX_BAR_REGION_COUNT], 8); + NV_DECLARE_ALIGNED(NvU64 sparseOffsets[NVA081_MAX_SPARSE_REGION_COUNT], 8); + NV_DECLARE_ALIGNED(NvU64 sparseSizes[NVA081_MAX_SPARSE_REGION_COUNT], 8); + NvU32 sparseCount; + NvBool isBar064bit; +} NVA081_CTRL_VGPU_GET_BAR_INFO_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH + * + * This command is to get the migration bandwidth of the physical GPU. + * + * migrationBandwidth [OUT] + * This param specifies the migration bandwidth of GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH (0xa0810122) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH_PARAMS { + NvU32 migrationBandwidth; +} NVA081_CTRL_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_ENUMERATE_VGPU_PER_GPU_INSTANCE + * + * This command enumerates list of vGPU guest instances per GPU instance + * + * gpuInstanceId [IN] + * This parameter specifies the GPU Instance Id or Swizz Id + * + * numVgpu [OUT] + * This parameter specifies the number of virtual GPUs created on a GPU instance + * + * vgpuInstanceIds [OUT] + * This parameter specifies an array of vGPU type ids active on a GPU instance + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_ENUMERATE_VGPU_PER_GPU_INSTANCE (0xa0810124) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_GPU_INSTANCE_PARAMS_MESSAGE_ID (0x24U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_GPU_INSTANCE_PARAMS { + NvU32 gpuInstanceId; + NvU32 numVgpu; + NvU32 vgpuInstanceIds[NVA081_MAX_VGPU_PER_GI]; +} NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_GPU_INSTANCE_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_CLEAR_SWIZZID_MASK + * + * This Command Clears the Assigned SwizzId Mask during vGPU destroy + * + * swizzId [IN] + * This parameter specifies the SwizzId of vGPU device + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_CLEAR_SWIZZID_MASK (0xa0810125) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_CMD_VGPU_CONFIG_CLEAR_SWIZZID_MASK_PARAMS_MESSAGE_ID" */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_CLEAR_SWIZZID_MASK_PARAMS_MESSAGE_ID (0x25U) + +typedef struct NVA081_CTRL_CMD_VGPU_CONFIG_CLEAR_SWIZZID_MASK_PARAMS { + NvU32 swizzId; +} NVA081_CTRL_CMD_VGPU_CONFIG_CLEAR_SWIZZID_MASK_PARAMS; + +/* _ctrlA081vgpuconfig_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrla083.h b/userspace/sdks/nv570/inc/ctrl/ctrla083.h new file mode 100644 index 0000000..33fdebc --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrla083.h @@ -0,0 +1,227 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla083.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NVA083_GRID_DISPLAYLESS control commands and parameters */ + +#define NVA083_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xA083, NVA083_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NVA083_CTRL_RESERVED (0x00) +#define NVA083_CTRL_VIRTUAL_DISPLAY (0x01) + +/* + * NVA083_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ + +#define NVA083_CTRL_CMD_NULL (0xa0830000) /* finn: Evaluated from "(FINN_NVA083_GRID_DISPLAYLESS_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NVA083_CTRL_CMD_VIRTUAL_DISPLAY_GET_NUM_HEADS + * + * This command returns the number of heads supported on a GPU with + * Displayless path enabled OR on a virtual GPU. + * + * numHeads + * This parameter returns total number of heads supported. + * + * maxNumHeads + * This parameter returns the MAX number of heads supported on this + * Displayless GRID GPU without any overrides of GPU capabilities. + * On Windows/Linux, we cannot dynamically change number of display + * head/source exposed to OS. Hence DD is required to report total + * number of display heads during init. + * DD registers during initialization the MAX number of heads supported and + * post that ensure only fixed allowed number of heads (reported via + * numHeads) can be made active (usable). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NVA083_CTRL_CMD_VIRTUAL_DISPLAY_GET_NUM_HEADS (0xa0830101) /* finn: Evaluated from "(FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY_INTERFACE_ID << 8) | NVA083_CTRL_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS_MESSAGE_ID" */ + +#define NVA083_CTRL_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA083_CTRL_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS { + NvU32 numHeads; + NvU32 maxNumHeads; +} NVA083_CTRL_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS; + +/* + * NVA083_CTRL_CMD_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION + * + * This command returns the maximum resolution supported on a GPU with + * Displayless path enabled OR on a virtual GPU. + * + * headIndex + * This parameter specifies the head for which the maximum resolution is to be + * retrieved. + * + * maxHResolution + * This parameter returns the maximum horizontal resolution. + * + * maxVResolution + * This parameter returns the maximum vertical resolution. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVA083_CTRL_CMD_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION (0xa0830102) /* finn: Evaluated from "(FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY_INTERFACE_ID << 8) | NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS_MESSAGE_ID" */ + +#define NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS { + NvU32 headIndex; + NvU32 maxHResolution; + NvU32 maxVResolution; +} NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS; + +/* + * NVA083_CTRL_CMD_VIRTUAL_DISPLAY_GET_DEFAULT_EDID + * + * This command returns the default EDID for GRID + * displayless path. + * + * pEdidBuffer + * This field provides a pointer to a buffer into which the + * default EDID for GRID displayless is retrieved. + * edidSize + * This field is used as an input/output. It specifies the maximum size of + * pEdidBuffer. If edidSize is set to zero on input, the actual required + * size of buffer will be updated in this field before returning. + * If however, edidSize is non-zero and smaller than that required, an + * error will be returned indicating the buffer was too small. + * connectorType + * This field is used as an input. It takes the connector information + * for which EDID for GRID displayless is queried. + * for DVI_D, Digital EDID is returned + * for VGA_15_PIN, Analog EDID is returned + * Both Digital and Analog EDIDs have same set of resolutions + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NVOS_ERR_BUFFER_TOO_SMALL + */ + +#define NVA083_CTRL_CMD_VIRTUAL_DISPLAY_GET_DEFAULT_EDID (0xa0830103) /* finn: Evaluated from "(FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY_INTERFACE_ID << 8) | NVA083_CTRL_VIRTUAL_DISPLAY_GET_DEFAULT_EDID_PARAMS_MESSAGE_ID" */ + +#define NVA083_CTRL_VIRTUAL_DISPLAY_GET_DEFAULT_EDID_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVA083_CTRL_VIRTUAL_DISPLAY_GET_DEFAULT_EDID_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pEdidBuffer, 8); + NvU32 edidSize; + NvU8 connectorType; +} NVA083_CTRL_VIRTUAL_DISPLAY_GET_DEFAULT_EDID_PARAMS; + +/* valid connector type values. Keeping DVI as the default one for displayless */ +#define NVA083_CTRL_CMD_CONNECTOR_INFO_TYPE_DVI_D (0x00) +#define NVA083_CTRL_CMD_CONNECTOR_INFO_TYPE_VGA_15_PIN (0x01) + +/* + * NVA083_CTRL_CMD_VIRTUAL_DISPLAY_IS_ACTIVE + * + * This command to query if any display is active or not + * + * Parameters: + * + * isDisplayActive + * Indicates if display is currently active or not. + * + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + */ +#define NVA083_CTRL_CMD_VIRTUAL_DISPLAY_IS_ACTIVE (0xa0830104) /* finn: Evaluated from "(FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY_INTERFACE_ID << 8) | NVA083_CTRL_VIRTUAL_DISPLAY_IS_ACTIVE_PARAMS_MESSAGE_ID" */ + +#define NVA083_CTRL_VIRTUAL_DISPLAY_IS_ACTIVE_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVA083_CTRL_VIRTUAL_DISPLAY_IS_ACTIVE_PARAMS { + NvBool isDisplayActive; +} NVA083_CTRL_VIRTUAL_DISPLAY_IS_ACTIVE_PARAMS; + +/* + * NVA083_CTRL_CMD_VIRTUAL_DISPLAY_IS_CONNECTED + * + * This command to query if any display is connected or not + * + * Parameters: + * + * isDisplayConnected + * Indicates if display is currently connected or not. + * + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + */ +#define NVA083_CTRL_CMD_VIRTUAL_DISPLAY_IS_CONNECTED (0xa0830105) /* finn: Evaluated from "(FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY_INTERFACE_ID << 8) | NVA083_CTRL_VIRTUAL_DISPLAY_IS_CONNECTED_PARAMS_MESSAGE_ID" */ + +#define NVA083_CTRL_VIRTUAL_DISPLAY_IS_CONNECTED_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVA083_CTRL_VIRTUAL_DISPLAY_IS_CONNECTED_PARAMS { + NvU32 isDisplayConnected; +} NVA083_CTRL_VIRTUAL_DISPLAY_IS_CONNECTED_PARAMS; + + +/* + * NVA083_CTRL_CMD_VIRTUAL_DISPLAY_GET_MAX_PIXELS + * + * This command returns the maximum pixel count for on a GPU with + * Displayless path enabled OR on a virtual GPU. + * + * maxPixels + * This parameter returns the max pixel limit for a displayless GPU + * OR a vGPU + * + * Possible status values returned are: + * NV_OK + */ + +#define NVA083_CTRL_CMD_VIRTUAL_DISPLAY_GET_MAX_PIXELS (0xa0830106) /* finn: Evaluated from "(FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY_INTERFACE_ID << 8) | NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_PIXELS_PARAMS_MESSAGE_ID" */ + +#define NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_PIXELS_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_PIXELS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 maxPixels, 8); +} NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_PIXELS_PARAMS; + +/* _ctrla083_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrla084.h b/userspace/sdks/nv570/inc/ctrl/ctrla084.h new file mode 100644 index 0000000..d740c7c --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrla084.h @@ -0,0 +1,387 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla084.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl2080/ctrl2080gpu.h" // NV2080_GPU_MAX_GID_LENGTH +#include "ctrl/ctrl2080/ctrl2080fb.h" // NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES + +/* NVA084_KERNEL_HOST_VGPU_DEVICE control commands and parameters */ +#define NVA084_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xA084U, NVA084_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NVA084_CTRL_RESERVED (0x00) +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE (0x01) + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO + * + * This command sets the guest vgpu device's information + * + * Parameter: + * + * vgpuUuid [IN] + * This parameter specifies the universaly unique identifier of the guest vGPU device + * + * vgpuDeviceInstanceId [IN] + * This parameter specifies the vGPU device instance + * + * Possible status values returned are: + * NV_OK + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO (0xa0840101) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS { + NvU8 vgpuUuid[NV2080_GPU_MAX_GID_LENGTH]; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS; + +/* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE + * + * This command triggers the notifier for vGPU guest. + * + * Parameters: + * + * vmLifeCycleState[IN] + * The life cycle event of the vGPU guest. This can be: + * NVA081_NOTIFIERS_EVENT_VGPU_GUEST_DESTROYED + * NVA081_NOTIFIERS_EVENT_VGPU_GUEST_CREATED + * + * Possible status values returned are: + * NV_OK + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE (0xa0840102) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS { + NvU32 vmLifeCycleState; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS; + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO + * + * This command is used to copy offlined page mapping info from plugin to host vgpu device + * + * guestFbSegmentPageSize [in] + * Guest FB segment page size + * + * offlinedPageCount [in] + * Offlined page count in the guest FB range + * + * gpa [in] + * This array represents guest page address list of offlined page + * + * hMemory [in] + * This array represents memory handle list of good page + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO (0xa0840103) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS { + NvU32 guestFbSegmentPageSize; + NvU32 offlinedPageCount; + NV_DECLARE_ALIGNED(NvU64 gpa[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES], 8); + NvHandle hMemory[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES]; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS; + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS + * + * Config space access for the virtual function + * + * Parameters: + * + * offset [IN] + * Offset within the config space + * + * numBytes [IN] + * Number of bytes to be read/written: 1/2/4 + * + * accessType [IN] + * To indicate whether it is a read operation or a write operation + * + * value [INOUT] + * Value to be read or written + * + * Possible status values returned are: + * NV_OK + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS (0xa0840104) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_VF_CONFIG_SPACE_ACCESS_TYPE_READ 0x1 +#define NVA084_CTRL_VF_CONFIG_SPACE_ACCESS_TYPE_WRITE 0x2 + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS { + NvU16 offset; + NvU8 numBytes; + NvU8 accessType; + NvU32 value; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS; + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF + * + * This command is used to create a bind-point on a host system + * for the collection of guest VM FECS events + * + * hEventBufferClient[IN] + * The client of the event buffer to bind to + * + * hEventBufferSubdevice[IN] + * The subdevice of the event buffer to bind to + * + * hEventBuffer[IN] + * The event buffer to bind to + * + * reasonCode[OUT] + * The reason for failure (if any); see NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF (0xa0840105) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS { + NvHandle hEventBufferClient; + NvHandle hEventBufferSubdevice; + NvHandle hEventBuffer; + NvU32 reasonCode; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS; + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL + * + * The command will trigger the specified interrupt on the host from CPU Plugin. + * + * handle[IN] + * - An opaque handle that will be passed in along with the interrupt + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL (0xa0840106) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS { + NvU32 handle; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS; + +/* valid action values */ +#define NVA084_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NVA084_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001) +#define NVA084_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002) + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION + * + * This command sets event notification state for the associated host vgpu device. + * This command requires that an instance of NV01_EVENT has been previously + * bound to the associated host vgpu device object. + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION (0xa0840107) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS { + // + // @todo: We will define the actual event values later based on the use case. + // These event values are only for Test purpose. + // + NvU32 event; + NvU32 action; + NvBool bNotifyState; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS; + +/* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_GER_BAR_MAPPING_RANGES + * + * This command is used to get Bar mapping ranges in RM. + * + * Parameters: + * offsets [OUT] + * Offsets of the ranges + * sizes [OUT] + * Sizes of the ranges + * mitigated [OUT] + * Specifies whether it's mitigated range + * numRanges [OUT] + * Number of ranges + * + * osPageSize [IN] + * Page size. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES (0xa084010a) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES 10 + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offsets[NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES], 8); + NV_DECLARE_ALIGNED(NvU64 sizes[NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES], 8); + NvU32 numRanges; + NvU32 osPageSize; + NvBool mitigated[NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES]; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS; + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_RESTORE_DEFAULT_EXEC_PARTITION + * + * This command restores the vGPU device's default EXEC partition saved in + * KERNEL_HOST_VGPU_DEVICE. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_RESTORE_DEFAULT_EXEC_PARTITION (0xa084010b) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | 0xB" */ + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_FREE_STATES + * + * This command is a KernelHostVgpuDeviceApi counterpart of + * NVA082_CTRL_CMD_HOST_VGPU_DEVICE_FREE_STATES, that allows + * to clean up a VF state. + * + * Parameters: + * + * flags [IN] + * Specifies what states need to be freed, same as in NVA082_CTRL_CMD_HOST_VGPU_DEVICE_FREE_STATES + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_FREE_STATES (0xa084010c) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_FREE_STATES_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_FREE_STATES_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_FREE_STATES_PARAMS { + NvU32 flags; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_FREE_STATES_PARAMS; + +#define NVA084_MAX_VMMU_SEGMENTS_COUNT 384 + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_BOOTLOAD_VGPU_TASK + * + * This command will update the bootload vGPU task + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_CLIENT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + * + * Parameters: + * numGuestFbHandles -> number of guest memory handles, the client handle is hPluginClient + * guestFbHandleList -> handle list to guest memory + * hPluginHeapMemory -> plugin heap memory handle, the client handle is hPluginClient + * ctrlBuffOffset -> offset of control buffer + * initTaskLogBuffOffset -> offset of init task log buffer + * initTaskLogBuffSize -> size of init task log buffer + * vgpuTaskLogBuffOffset -> offset of vgpu task log buffer + * vgpuTaskLogBuffSize -> size of vgpu task log buffer + * kernelLogBuffOffset -> offset of kernel log buffer + * kernelLogBuffSize -> size of kernel log buffer + * hMigRmHeapMemory -> MIG-RM heap memory handle + * bDeviceProfilingEnabled -> If set to true, profiling is allowed + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_BOOTLOAD_VGPU_TASK (0xa084010d) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BOOTLOAD_VGPU_TASK_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BOOTLOAD_VGPU_TASK_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BOOTLOAD_VGPU_TASK_PARAMS { + NvU32 numGuestFbHandles; + NvHandle guestFbHandleList[NVA084_MAX_VMMU_SEGMENTS_COUNT]; + NvHandle hPluginHeapMemory; + NV_DECLARE_ALIGNED(NvU64 ctrlBuffOffset, 8); + NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffOffset, 8); + NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffSize, 8); + NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffOffset, 8); + NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffSize, 8); + NV_DECLARE_ALIGNED(NvU64 kernelLogBuffOffset, 8); + NV_DECLARE_ALIGNED(NvU64 kernelLogBuffSize, 8); + NvHandle hMigRmHeapMemory; + NvBool bDeviceProfilingEnabled; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BOOTLOAD_VGPU_TASK_PARAMS; + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_PLACEMENT_ID + * + * This command will set the placementId and reserve system channel Ids + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_CLIENT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + * + * Parameters: + * numChannels -> Used only when SRIOV is enabled. + * placementId -> Used to provide placement Id of vGPU device with heterogeneous timesliced vGPUs. + * Also Ada onwards for Homogeneous GPUs as well. + * Otherwise set to NVA081_PLACEMENT_ID_INVALID. + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_PLACEMENT_ID (0xa084010e) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_PLACEMENT_ID_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_PLACEMENT_ID_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_PLACEMENT_ID_PARAMS { + NvU32 numChannels; + NvU16 placementId; +} NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_PLACEMENT_ID_PARAMS; + +/* _ctrla084_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrla0bc.h b/userspace/sdks/nv570/inc/ctrl/ctrla0bc.h new file mode 100644 index 0000000..68e4810 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrla0bc.h @@ -0,0 +1,119 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla0bc.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NVENC_SW_SESSION control commands and parameters */ +#define NVA0BC_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xA0BC, NVA0BC_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NVA0BC_CTRL_RESERVED (0x00) +#define NVA0BC_CTRL_NVENC_SW_SESSION (0x01) + +#define NVA0BC_CTRL_CMD_NVENC_MAX_BUFFER_ENTRIES 60 + +/* + * NVA0BC_CTRL_CMD_NVENC_SW_SESSION_UPDATE_INFO + * + * This command is used to let RM know about runtime information about + * running NVENC session on given GPU. + * * + * hResolution + * This parameter specifies the current horizontal resolution of NVENC session. + * vResolution + * This parameter specifies the current vertical resolution of NVENC session. + * averageEncodeLatency + * This field specifies the average encode latency over last 1 second. + * averageEncodeFps + * This field specifies the average encode FPS over last 1 second. + * timestampBufferSize + * This field specifies the number of entries in the caller's timestampBuffer. + * It should not be greater than NVA0BC_CTRL_CMD_NVENC_MAX_BUFFER_ENTRIES. + * When this field is zero, RM will assume that client has calculated averageEncodeFps + * and averageEncodeLatency, thus ignore timestampBuffer. + * timestampBuffer + * This field specifies a pointer in the caller's address space + * to the buffer holding encode timestamps in microseconds. + * This buffer must be at least as big as timestampBufferSize multiplied + * by the size of the NVA0BC_CTRL_NVENC_TIMESTAMP structure. + * e.g. if there are 10 fps, buffer will contain only 10 entries and rest of + * entries should be 0x00. However if there are more than 60 fps, buffer will + * contain last/latest 60 entries of frame encoding start-end timestamps. Caller + * should make sure timestamps won't wrap around. RM assume that for each + * frame timestamp value endTime would be greater than startTime. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVA0BC_CTRL_CMD_NVENC_SW_SESSION_UPDATE_INFO (0xa0bc0101) /* finn: Evaluated from "(FINN_NVENC_SW_SESSION_NVENC_SW_SESSION_INTERFACE_ID << 8) | NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_MESSAGE_ID" */ + +typedef struct NVA0BC_CTRL_NVENC_TIMESTAMP { + NV_DECLARE_ALIGNED(NvU64 startTime, 8); + NV_DECLARE_ALIGNED(NvU64 endTime, 8); +} NVA0BC_CTRL_NVENC_TIMESTAMP; + +#define NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS { + NvU32 hResolution; + NvU32 vResolution; + NvU32 averageEncodeLatency; + NvU32 averageEncodeFps; + NvU32 timestampBufferSize; + NV_DECLARE_ALIGNED(NvP64 timestampBuffer, 8); +} NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS; + +/* +* NVA0BC_CTRL_CMD_NVENC_SW_SESSION_UPDATE_INFO_V2 +* +* This command updates the NVENC software sessions information for the associate GPU. +* This command is similar to NVA0BC_CTRL_CMD_NVENC_SW_SESSION_UPDATE_INFO but doesn't have +* embedded pointers. +* +* Check NVA0BC_CTRL_CMD_NVENC_SW_SESSION_UPDATE_INFO for detailed information. +*/ + +#define NVA0BC_CTRL_CMD_NVENC_SW_SESSION_UPDATE_INFO_V2 (0xa0bc0102) /* finn: Evaluated from "(FINN_NVENC_SW_SESSION_NVENC_SW_SESSION_INTERFACE_ID << 8) | NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_V2_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_V2_PARAMS { + NvU32 hResolution; + NvU32 vResolution; + NvU32 averageEncodeLatency; + NvU32 averageEncodeFps; + NvU32 timestampBufferSize; + NV_DECLARE_ALIGNED(NVA0BC_CTRL_NVENC_TIMESTAMP timestampBuffer[NVA0BC_CTRL_CMD_NVENC_MAX_BUFFER_ENTRIES], 8); +} NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_V2_PARAMS; + +/* _ctrla0bc_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrla0bd.h b/userspace/sdks/nv570/inc/ctrl/ctrla0bd.h new file mode 100644 index 0000000..2d046ac --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrla0bd.h @@ -0,0 +1,100 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla0bd.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NVFBC_SW_SESSION control commands and parameters */ +#define NVA0BD_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xA0BD, NVA0BD_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NVA0BD_CTRL_RESERVED (0x00) +#define NVA0BD_CTRL_NVFBC_SW_SESSION (0x01) + +#define NVA0BD_CTRL_CMD_NVFBC_MAX_TIMESTAMP_ENTRIES 60 + +/* + * NVA0BD_CTRL_CMD_NVFBC_SW_SESSION_UPDATE_INFO + * + * This command is used to let RM know about runtime information about + * NVFBC session on given GPU. + * * + * hResolution + * This parameter specifies the current horizontal resolution of NVFBC session. + * vResolution + * This parameter specifies the current vertical resolution of NVFBC session. + * captureCallFlags + * This field specifies the flags associated with the capture call and the session. + * One of the flags specifies whether the user made the capture with wait or not. + * totalGrabCalls + * This field specifies the total number of grab calls made by the user. + * averageLatency + * This field specifies the average capture latency over last 1 second. + * averageFPS + * This field specifies the average frames captured. + * timestampEntryCount + * This field specifies the number of entries in the timestampEntry array. + * It should not be greater than NVA0BD_CTRL_CMD_NVFBC_MAX_TIMESTAMP_ENTRIES. + * When this field is zero, RM will assume that client has calculated averageFBCFps + * and averageFBCLatency, thus ignore timestampEntry array. + * timestampEntry + * This field specifies a array holding capture timestamps in microseconds. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVA0BD_CTRL_CMD_NVFBC_SW_SESSION_UPDATE_INFO (0xa0bd0101) /* finn: Evaluated from "(FINN_NVFBC_SW_SESSION_NVFBC_SW_SESSION_INTERFACE_ID << 8) | NVA0BD_CTRL_NVFBC_SW_SESSION_UPDATE_INFO_PARAMS_MESSAGE_ID" */ + +typedef struct NVA0BD_CTRL_NVFBC_TIMESTAMP { + NV_DECLARE_ALIGNED(NvU64 startTime, 8); + NV_DECLARE_ALIGNED(NvU64 endTime, 8); +} NVA0BD_CTRL_NVFBC_TIMESTAMP; + +#define NVA0BD_CTRL_NVFBC_SW_SESSION_UPDATE_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA0BD_CTRL_NVFBC_SW_SESSION_UPDATE_INFO_PARAMS { + NvU32 hResolution; + NvU32 vResolution; + NvU32 captureCallFlags; + NvU32 totalGrabCalls; + NvU32 averageLatency; + NvU32 averageFPS; + NvU32 timestampEntryCount; + NV_DECLARE_ALIGNED(NVA0BD_CTRL_NVFBC_TIMESTAMP timestampEntry[NVA0BD_CTRL_CMD_NVFBC_MAX_TIMESTAMP_ENTRIES], 8); +} NVA0BD_CTRL_NVFBC_SW_SESSION_UPDATE_INFO_PARAMS; + +#define NVA0BD_NVFBC_WITH_WAIT 1:0 +#define NVA0BD_NVFBC_WITH_WAIT_FALSE (0x00000000) +#define NVA0BD_NVFBC_WITH_WAIT_INFINITE (0x00000001) +#define NVA0BD_NVFBC_WITH_WAIT_TIMEOUT (0x00000010) + +/* _ctrla0bd_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlb069.h b/userspace/sdks/nv570/inc/ctrl/ctrlb069.h new file mode 100644 index 0000000..a2e313b --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlb069.h @@ -0,0 +1,175 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlb069.finn +// + +#include "ctrl/ctrlxxxx.h" +/* MAXWELL_FAULT_BUFFER_A control commands and parameters */ + +#define NVB069_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xB069, NVB069_CTRL_##cat, idx) + +/* MAXWELL_FAULT_BUFFER_A command categories (6bits) */ +#define NVB069_CTRL_RESERVED (0x00) +#define NVB069_CTRL_FAULTBUFFER (0x01) + +/* + * NVB069_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVB069_CTRL_CMD_NULL (0xb0690000) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + + +/* + * NVB069_CTRL_CMD_FAULTBUFFER_READ_GET + * + * This command returns the current HW GET pointer for the requested type fault buffer + * + * faultBufferGetOffset + * Value of current HW GET pointer + * faultBufferType + * Type of fault buffer. FAULT_BUFFER_REPLAYABLE or FAULT_BUFFER_NON_REPLAYABLE + */ +#define NVB069_CTRL_CMD_FAULTBUFFER_READ_GET (0xb0690101) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_FAULTBUFFER_READ_GET_PARAMS_MESSAGE_ID" */ + +#define NVB069_CTRL_FAULTBUFFER_READ_GET_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVB069_CTRL_FAULTBUFFER_READ_GET_PARAMS { + NvU32 faultBufferGetOffset; + NvU32 faultBufferType; +} NVB069_CTRL_FAULTBUFFER_READ_GET_PARAMS; + +// +// Valid Fault buffer Types +// NON_REPLAYABLE is only supported in Volta+ GPUs. +// +#define NVB069_CTRL_FAULT_BUFFER_NON_REPLAYABLE (0x00000000) +#define NVB069_CTRL_FAULT_BUFFER_REPLAYABLE (0x00000001) + +/* + * NVB069_CTRL_CMD_FAULTBUFFER_WRITE_GET + * + * This command writes the HW GET pointer for the requested type of fault buffer + * + * NOTE: The caller must issue a write barrier before this function to + * ensure modifications to the current buffer entry are committed before + * the GET pointer is updated. + * + * faultBufferGetOffset + * Value to be written to HW GET pointer + * faultBufferType + * Type of fault buffer. FAULT_BUFFER_REPLAYABLE or FAULT_BUFFER_NON_REPLAYABLE + */ +#define NVB069_CTRL_CMD_FAULTBUFFER_WRITE_GET (0xb0690102) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_FAULTBUFFER_WRITE_GET_PARAMS_MESSAGE_ID" */ + +#define NVB069_CTRL_FAULTBUFFER_WRITE_GET_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVB069_CTRL_FAULTBUFFER_WRITE_GET_PARAMS { + NvU32 faultBufferGetOffset; + NvU32 faultBufferType; +} NVB069_CTRL_FAULTBUFFER_WRITE_GET_PARAMS; + +/* + * NVB069_CTRL_CMD_FAULTBUFFER_READ_PUT + * + * This command returns the current HW PUT pointer for the requested type fault buffer + * + * faultBufferGetOffset + * Value of current HW PUT pointer + * faultBufferType + * Type of fault buffer. FAULT_BUFFER_REPLAYABLE or FAULT_BUFFER_NON_REPLAYABLE + */ +#define NVB069_CTRL_CMD_FAULTBUFFER_READ_PUT (0xb0690103) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_FAULTBUFFER_READ_PUT_PARAMS_MESSAGE_ID" */ + +#define NVB069_CTRL_FAULTBUFFER_READ_PUT_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVB069_CTRL_FAULTBUFFER_READ_PUT_PARAMS { + NvU32 faultBufferPutOffset; + NvU32 faultBufferType; +} NVB069_CTRL_FAULTBUFFER_READ_PUT_PARAMS; + +#define NVB069_CTRL_CMD_FAULTBUFFER_GET_SIZE (0xb0690105) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_FAULTBUFFER_GET_SIZE_PARAMS_MESSAGE_ID" */ + +#define NVB069_CTRL_FAULTBUFFER_GET_SIZE_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVB069_CTRL_FAULTBUFFER_GET_SIZE_PARAMS { + NvU32 faultBufferSize; +} NVB069_CTRL_FAULTBUFFER_GET_SIZE_PARAMS; + + +/* + * NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS + * + * This command provides kernel mapping to a few registers. + * These mappings are needed by UVM driver to handle non fatal gpu faults + * + * pFaultBufferGet + * Mapping for fault buffer's get pointer (NV_PFIFO_REPLAYABLE_FAULT_BUFFER_GET) + * pFaultBufferPut + * Mapping for fault buffer's put pointer (NV_PFIFO_REPLAYABLE_FAULT_BUFFER_PUT) + * pFaultBufferInfo + * Mapping for fault buffer's Info pointer (NV_PFIFO_REPLAYABLE_FAULT_BUFFER_INFO) + * Note: this variable is deprecated since buffer overflow is not a seperate register from Volta + * pPmcIntr + * Mapping for PMC intr register (NV_PMC_INTR(0)) + * pPmcIntrEnSet + * Mapping for PMC intr set register - used to enable an intr (NV_PMC_INTR_EN_SET(0)) + * pPmcIntrEnClear + * Mapping for PMC intr clear register - used to disable an intr (NV_PMC_INTR_EN_CLEAR(0)) + * replayableFaultMask + * Mask for the replayable fault bit(NV_PMC_INTR_REPLAYABLE_FAULT) + * faultBufferType + * This is an input param denoting replayable/non-replayable fault buffer + */ +#define NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS (0xb0690106) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS_MESSAGE_ID" */ + +#define NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pFaultBufferGet, 8); + NV_DECLARE_ALIGNED(NvP64 pFaultBufferPut, 8); + NV_DECLARE_ALIGNED(NvP64 pFaultBufferInfo, 8); + NV_DECLARE_ALIGNED(NvP64 pPmcIntr, 8); + NV_DECLARE_ALIGNED(NvP64 pPmcIntrEnSet, 8); + NV_DECLARE_ALIGNED(NvP64 pPmcIntrEnClear, 8); + NvU32 replayableFaultMask; + NV_DECLARE_ALIGNED(NvP64 pPrefetchCtrl, 8); + NvU32 faultBufferType; +} NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS; + +/* _ctrlb069_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlb06f.h b/userspace/sdks/nv570/inc/ctrl/ctrlb06f.h new file mode 100644 index 0000000..9b24b20 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlb06f.h @@ -0,0 +1,365 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlb06f.finn +// + + + + +/* MAXWELL_CHANNEL_GPFIFO_A control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#define NVB06F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xB06F, NVB06F_CTRL_##cat, idx) + +/* MAXWELL_CHANNEL_GPFIFO_A command categories (6bits) */ +#define NVB06F_CTRL_RESERVED (0x00) +#define NVB06F_CTRL_GPFIFO (0x01) + +/* + * NVB06F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVB06F_CTRL_CMD_NULL (0xb06f0000) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NVB06F_CTRL_CMD_GET_ENGINE_CTX_SIZE + * + * This command returns the size of the engine context. + * + * engineID + * This parameter specifies the engine context size to be retrieved. + * + * See the description of the NV2080_ENGINE_TYPE values in cl2080.h for more + * information + * + * size + * This parameter returns the size of the engine context + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVB06F_CTRL_CMD_GET_ENGINE_CTX_SIZE (0xb06f010b) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GET_ENGINE_CTX_SIZE_PARAMS_MESSAGE_ID" */ + +#define NVB06F_CTRL_GET_ENGINE_CTX_SIZE_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NVB06F_CTRL_GET_ENGINE_CTX_SIZE_PARAMS { + NvU32 engineID; + NvU32 size; +} NVB06F_CTRL_GET_ENGINE_CTX_SIZE_PARAMS; + +/* + * NVB06F_CTRL_CMD_GET_ENGINE_CTX_DATA + * + * This command returns the context buffer data for the given engine for vGPU motion. + * + * engineID + * This parameter specifies the engine context to be retrieved. + * + * See the description of the NV2080_ENGINE_TYPE values in cl2080.h for + * more information + * + * size + * This parameter specifies the size of the context buffer. + * + * pEngineCtxBuff + * This parameter specifies the context buffer for motion operation to be filled in. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ + +#define NVB06F_CTRL_CMD_GET_ENGINE_CTX_DATA (0xb06f010c) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID" */ + +typedef struct SW_OBJECT_ENGINE_CTX { + NvU32 hObject; + NvU32 subCh; +} SW_OBJECT_ENGINE_CTX; + +#define NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS { + NvU32 engineID; + NvU32 size; + NV_DECLARE_ALIGNED(NvP64 pEngineCtxBuff, 8); +} NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS; + +/* + * NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA + * + * This command restores the context buffer for the given engine for vGPU motion. + * + * engineID + * This parameter specifies the engine context to be restored. + * + * See the description of the NV2080_ENGINE_TYPE values in cl2080.h for + * more information + * + * size + * This parameter specifies the size of the context buffer. + * + * pEngineCtxBuff + * This parameter specifies the context buffer for motion operation restore. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ + +#define NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA (0xb06f010d) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID" */ + +#define NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID (0xDU) + +typedef NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS; + +/* + * NVB06F_CTRL_CMD_GET_ENGINE_CTX_STATE + * + * This command returns the context buffer state of the given engine for vGPU motion. + * + * engineID + * This input parameter specifies the engine context to be restored. + * + * See the description of the NV2080_ENGINE_TYPE values in cl2080.h for + * more information + * + * hObject + * This parameter specifies the channel object that is running on the SW engine. + * + * engineCtxState + * This parameter specifies the engine context state. For SW engine, the only meaningful + * field is INVALID, INITIALIZED and the subch. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ + +#define NVB06F_CTRL_CMD_GET_ENGINE_CTX_STATE (0xb06f010e) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GET_ENGINE_CTX_STATE_PARAMS_MESSAGE_ID" */ + +#define NVB06F_CTRL_GET_ENGINE_CTX_STATE_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NVB06F_CTRL_GET_ENGINE_CTX_STATE_PARAMS { + NvU32 engineID; + NvU32 hObject; + NvU32 engineCtxState; +} NVB06F_CTRL_GET_ENGINE_CTX_STATE_PARAMS; + +#define NVB06F_CTRL_GET_ENGINE_CTX_VIRTUAL_CONTEXT 0:0 +#define NVB06F_CTRL_GET_ENGINE_CTX_VIRTUAL_CONTEXT_DISABLED (0x00000000) +#define NVB06F_CTRL_GET_ENGINE_CTX_VIRTUAL_CONTEXT_ENABLED (0x00000001) +#define NVB06F_CTRL_GET_ENGINE_CTX_STATE 2:1 +#define NVB06F_CTRL_GET_ENGINE_CTX_STATE_INVALID (0x00000000) +#define NVB06F_CTRL_GET_ENGINE_CTX_STATE_INITIALIZED (0x00000001) +#define NVB06F_CTRL_GET_ENGINE_CTX_STATE_PROMOTED (0x00000002) +#define NVB06F_CTRL_GET_ENGINE_CTX_STATE_EVICTED (0x00000003) +#define NVB06F_CTRL_GET_ENGINE_CTX_SUBCH 6:4 + +/* + * NVB06F_CTRL_CMD_GET_CHANNEL_HW_STATE + * + * This command returns the channel HW state. + * + * state + * This parameter stores single bit-fields corresponding to the following + * channel HW states: + * NEXT + * A value of NV_TRUE indicates that this channel should be scheduled + * first when GPU Host chooses this TSG to run next on the runlist. + * + * CTX_RELOAD + * A value of NV_TRUE indicates that this channel's context was + * preempted and needs to be reloaded. + * + * PENDING + * A value of NV_TRUE indicates that this channel is not loaded on the + * PBDMA but methods still remain. This includes the completion of + * semaphores acquires and WFI methods. This field is deprecated + * from Volta onwards, and can be ignored. + * + * ENG_FAULTED + * A value of NV_TRUE indicates that the channel's engine has faulted, + * and the channel will not be rescheduled until the fault has been + * cleared. This bit should only be set as part of migration, and will + * not necessarily cause the channel to be prevented from being + * scheduled. + * + * PBDMA_FAULTED + * A value of NV_TRUE indicates that the channel's PBDMA has faulted, + * and the channel will not be rescheduled until the fault has been + * cleared. This bit should only be set as part of migration, and will + * not necessarily cause the channel to be prevented from being + * scheduled. + * + * ACQUIRE_FAIL + * A value of NV_TRUE indicates that the engine scheduler failed to + * acquire a semaphore for this channel. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ +#define NVB06F_CTRL_CMD_GET_CHANNEL_HW_STATE (0xb06f010f) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS_MESSAGE_ID" */ + +#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_NEXT 0:0 +#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_CTX_RELOAD 1:1 +#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_PENDING 2:2 +#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_ENG_FAULTED 3:3 +#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_PBDMA_FAULTED 4:4 +#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_ACQUIRE_FAIL 5:5 + +typedef struct NVB06F_CTRL_CHANNEL_HW_STATE_PARAMS { + NvU32 state; +} NVB06F_CTRL_CHANNEL_HW_STATE_PARAMS; + +#define NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS_MESSAGE_ID (0xFU) + +typedef NVB06F_CTRL_CHANNEL_HW_STATE_PARAMS NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS; + +/* + * NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE + * + * This command restores the channel HW state. + * + * state + * This parameter stores single bit-fields corresponding to the following + * channel HW states: + * NEXT + * A value of NV_TRUE indicates that this channel should be scheduled + * first when GPU Host chooses this TSG to run next on the runlist. + * + * CTX_RELOAD + * A value of NV_TRUE indicates that this channel's context was + * preempted and needs to be reloaded. + * + * PENDING + * A value of NV_TRUE indicates that this channel is not loaded on the + * PBDMA but methods still remain. This includes the completion of + * semaphores acquires and WFI methods. This field is deprecated + * from Volta onwards, and can be ignored. + * + * ENG_FAULTED + * A value of NV_TRUE indicates that the channel's engine has faulted, + * and the channel will not be rescheduled until the fault has been + * cleared. This bit should only be set as part of migration, and will + * not necessarily cause the channel to be prevented from being + * scheduled. + * + * PBDMA_FAULTED + * A value of NV_TRUE indicates that the channel's PBDMA has faulted, + * and the channel will not be rescheduled until the fault has been + * cleared. This bit should only be set as part of migration, and will + * not necessarily cause the channel to be prevented from being + * scheduled. + * + * ACQUIRE_FAIL + * A value of NV_TRUE indicates that the engine scheduler failed to + * acquire a semaphore for this channel. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ +#define NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE (0xb06f0110) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS_MESSAGE_ID" */ + +#define NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS_MESSAGE_ID (0x10U) + +typedef NVB06F_CTRL_CHANNEL_HW_STATE_PARAMS NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS; + +/* + * NVB06F_CTRL_CMD_SAVE_ENGINE_CTX_DATA + * + * This command returns the context buffer data for the given engine for vGPU migration. + * + * engineID + * This parameter specifies the engine context to be retrieved. + * + * See the description of the NV2080_ENGINE_TYPE values in cl2080.h for + * more information + * + * size + * This parameter specifies the size of the context buffer. The maximum size + * of engine context buffer is choosen to support only RAMFC and instance + * memory block. To use this RmCtrl for a higher sized buffer, like the GR + * context, the max size would have to be increased. + * + * engineCtxBuff + * This parameter specifies the context buffer data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ + +#define NVB06F_CTRL_CMD_SAVE_ENGINE_CTX_DATA (0xb06f0111) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID" */ + +#define NVB06F_CTRL_ENGINE_CTX_BUFFER_SIZE_MAX 4096 + +#define NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS { + NvU32 engineID; + NvU32 size; + NvU8 engineCtxBuff[NVB06F_CTRL_ENGINE_CTX_BUFFER_SIZE_MAX]; +} NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS; + +/* + * NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA + * + * This command restores the context buffer for the given engine for vGPU migration. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ + +#define NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA (0xb06f0112) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS_MESSAGE_ID" */ + +typedef NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS NVB06F_CTRL_RESTORE_ENGINE_CTX_DATA_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS { + NVB06F_CTRL_RESTORE_ENGINE_CTX_DATA_PARAMS params; +} NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS; + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlb0cc.h b/userspace/sdks/nv570/inc/ctrl/ctrlb0cc.h new file mode 100644 index 0000000..1148c9a --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlb0cc.h @@ -0,0 +1,397 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlb0cc.finn +// + + + + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl2080/ctrl2080gpu.h" // NV2080_CTRL_GPU_REG_OP +#include "ctrlb0cc/ctrlb0ccprofiler.h" +#include "ctrlb0cc/ctrlb0ccinternal.h" +#include "ctrlb0cc/ctrlb0ccpower.h" + +/* + * NVB0CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS + * + * This command attempts to enable or disable various clock-gating features of + * the GPU on behalf of the profiler. If this command is unable to set the + * clock-gating feature state of any of the requested features, this command + * will fail and none of the requested features will be modified. If this + * command fails because one or more clock-gating feature requests were + * rejected, it will return NV_ERR_STATE_IN_USE in the globalStatus + * parameter and the fields in the statusMask parameter for the features for + * which the requests were rejected will have the value + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_REJECTED. + * If a given feature is not supported on the GPU, the field for that clock- + * gating feature will have the value + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_NOT_SUPPORTED in the + * statusMask parameter, but this condition by itself will not cause the + * command to fail. Even if this command fails, the field for clock-gating + * features which would have successfully changed will have the value + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_FULFILLED in the statusMask + * parameter. + * + * Each of the clock-gating features is reference-counted individually, so + * that multiple MAXWELL_PROFILER objects may request and rely on the same + * settings for the features simultaneously. Each clock-gating feature is + * locked to the requested state until the MAXWELL_PROFILER object is freed or + * the NVB0CC_CTRL_CMD_PROFILER_RELEASE_CG_CONTROLS command is called for that + * feature. + * + * Currently, only MAXWELL_PROFILER requests for power features using this + * command are reference counted. Changes to the power feature settings made + * either by other control commands or the RM itself may interfere with the + * settings requested by MAXWELL_PROFILER instances. + * + * This command will always return NV_OK when given valid + * parameters. If there is any other failure that prevents the clock-gating + * features from being set appropriately, the globalStatus parameter will + * indicate this and the statusMask parameter will indicate which clock-gating + * feature requests failed and why. + * + * controlMask + * This parameter indicates which clock-gating features the request should + * apply to. This parameter has the following fields: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG + * The value of this field indicates whether this request should apply + * to engine-level clock-gating of the GR engine. Valid values for + * this field are: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_IGNORE + * This value indicates that the GR engine-level clock-gating + * should be ignored. This will not affect the reference count for + * this feature. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_DISABLE + * This value indicates that the GR engine-level clock-gating + * should be disabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_ENABLE + * This value indicates that the GR engine-level clock-gating + * should be enabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG + * The value of this field indicates whether this request should apply + * to block-level clock-gating. Valid values for this field are: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_IGNORE + * This value indicates that block-level clock-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_DISABLE + * This value indicates that block-level clock-gating should be + * disabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_ENABLE + * This value indicates that block-level clock-gating should be + * enabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG + * The value of this field indicates whether this request should apply + * to second-level clock-gating. Valid values for this field are: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_IGNORE + * This value indicates that second-level clock-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_DISABLE + * This value indicates that second-level clock-gating should be + * disabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_ENABLE + * This value indicates that second-level clock-gating should be + * enabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG + * The value of this field indicates whether this request should apply + * to GR engine-level power-gating. Valid values for this field are: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_IGNORE + * This value indicates that engine-level power-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_DISABLE + * This value indicates that engine-level power-gating should be + * disabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_ENABLE + * This value indicates that engine-level power-gating should be + * enabled. + * Note that this field is only temporary to allow reference counting + * restricted to MAXWELL_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN + * The value of this field indicates whether this request should apply + * to SM idle slowdown. Valid values for this field are: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_IGNORE + * This value indicates that SM idle slowdown should be ignored. + * This will not affect the reference count for this feature. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_DISABLE + * This value indicates that SM idle slowdown should be disabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_ENABLE + * This value indicates that SM idle slowdown should be enabled. + * Note that this field is only temporary to allow reference counting + * restricted to MAXWELL_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT + * The value of this field indicates whether this request should apply + * to VAT. Valid values for this field are: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_IGNORE + * This value indicates that VAT should be ignored. + * This will not affect the reference count for this feature. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_DISABLE + * This value indicates that VAT should be disabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_ENABLE + * This value indicates that VAT should be enabled. + * Note that this field is only temporary to allow reference counting + * restricted to MAXWELL_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * globalStatus + * This parameter returns the overall status of the requests for all + * clock-gating controls. If the value of this parameter is not + * NV_OK, none of the clock-gating controls will be set as + * requested. Possible values for this parameter are: + * NV_OK + * This value indicates that all of the clock-gating control requests + * were either fulfilled or not supported on the hardware. + * NV_ERR_INVALID_REQUEST + * This value indicates that at least one of the clock-gating control + * requests were invalid given the MAXWELL_PROFILER instance's + * outstanding requests. + * NV_ERR_STATE_IN_USE + * This value indicates that at least one of the clock-gating controls + * has already been locked to a conflicting state by another + * MAXWELL_PROFILER instance or the RM itself. + * statusMask + * This parameter returns the status of the request to set each clock- + * gating control specified by the controlMask parameter. The fields are + * identical to those of the controlMask parameter. For each field for + * which the corresponding field in the controlMask parameter has the + * value NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_IGNORE, the value is + * undefined. For each field for which the corresponding field in the + * controlMask parameter has the value + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST, the value will be + * one of the following: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_FULFILLED + * This value indicates that the clock-gating feature corresponding to + * the field in question was enabled or disabled according to the + * controlMask parameter, and the reference count for the feature was + * incremented accordingly. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_REJECTED + * This value indicates that the clock-gating feature corresponding to + * the field in question was not set to the expected state according + * to the controlMask parameter because another conflicting request is + * currently outstanding for the clock-gating feature. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_FAILED + * This value indicates that the clock-gating feature corresponding to + * the field in question was not set to the expected state according + * to the controlMask parameter because the attempt to do so failed + * with an error other than a conflicting request. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_NOT_SUPPORTED + * This value indicates that the clock-gating feature corresponding to + * the field in question is not supported on this GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVB0CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES + +typedef NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS NVB0CC_CTRL_PROFILER_REQUEST_CG_CONTROLS_PARAMS; + +/* valid fields for the controlMask and statusMask parameters */ +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG 1:0 +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG 3:2 +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG 5:4 + +/* + * The following are temporary fields for the controlMask and statusMask + * parameters. They are required to reference count their respective features + * until the existing RM controls can be safely updated, and the definitions + * for these features will be removed soon after that. + */ +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG 7:6 +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN 9:8 +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT 11:10 + +/* valid values for fields in the controlMask parameter */ +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_IGNORE (0x00000000) +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_DISABLE (0x00000001) +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_ENABLE (0x00000002) + +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_IGNORE NVB0CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_DISABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_ENABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_IGNORE NVB0CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_DISABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_ENABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_IGNORE NVB0CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_DISABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_ENABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_IGNORE NVB0CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_DISABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_ENABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_IGNORE NVB0CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_DISABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_ENABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_IGNORE NVB0CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_DISABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_ENABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_ENABLE +/* possible values for fields in the statusMask parameter */ +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED (0x00000000) +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED (0x00000001) +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED (0x00000002) +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED (0x00000003) + +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_FULFILLED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_REJECTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_FAILED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_FULFILLED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_REJECTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_FAILED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_FULFILLED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_REJECTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_FAILED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_FULFILLED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_REJECTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_FAILED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_FULFILLED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_REJECTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_FAILED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_FULFILLED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_REJECTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_FAILED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED + +/* utility masks for the controlMask parameter for all controls */ +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL \ + DRF_SHIFTMASK(NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT) +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_IGNORE \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _IGNORE) +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_DISABLE \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _DISABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _DISABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _DISABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _DISABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _DISABLE)| \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _DISABLE) +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_ENABLE \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _ENABLE) + +/* + * NVB0CC_CTRL_CMD_PROFILER_RELEASE_CG_CONTROLS + * + * This command is deprecated; please us + * NVB0CC_CTRL_CMD_POWER_RELEASE_FEATURES. + * + * This command releases the MAXWELL_PROFILER's request for the given clock- + * gating features that was previously created by the + * NVB0CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS command. If the MAXWELL_PROFILER + * object does not have an outstanding request to one or more of the given + * clock-gating features, those features will be ignored while the other + * feature requests will be released. + * + * After calling this command, the calling client may not rely on the current + * value of any of the released clock-gating features to remain, even if + * several identical requests for the given clock-gating features were made + * using NVB0CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS. The RM only reference- + * counts the settings requested by MAXWELL_PROFILER instances - it does not + * reference-count multiple identical requests made using the same + * MAXWELL_PROFILER instance. + * + * All outstanding requests made using this MAXWELL_PROFILER object are + * implicitly released when the MAXWELL_PROFILER is freed. + * + * controlMask + * This parameter indicates which clock-gating features the RM should + * release the MAXWELL_PROFILER's reference to. See + * NVB0CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS for valid fields. Valid + * values for each field are: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_IGNORE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_IGNORE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_IGNORE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_IGNORE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_IGNORE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_IGNORE + * This value indicates that the clock-gating feature associated with + * the field should not be released, even if the MAXWELL_PROFILER has an + * outstanding request for it. This will not affect the reference + * count for the feature. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_RELEASE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_RELEASE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_RELEASE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_RELEASE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_RELEASE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_RELEASE + * This value indicates that the MAXWELL_PROFILER's outstanding request + * for the clock-gating feature associated with the field should be + * released. This will decrement the reference count for the feature + * if the MAXWELL_PROFILER has an outstanding request for it. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVB0CC_CTRL_CMD_PROFILER_RELEASE_CG_CONTROLS NVB0CC_CTRL_CMD_POWER_RELEASE_FEATURES + +typedef NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS NVB0CC_CTRL_PROFILER_RELEASE_CG_CONTROLS_PARAMS; + +/* + * valid values for the controlMask parameter in addition to + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_IGNORE + */ +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_RELEASE (0x00000003) + +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_RELEASE NVB0CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_RELEASE NVB0CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_RELEASE NVB0CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_RELEASE NVB0CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_RELEASE NVB0CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_RELEASE NVB0CC_CTRL_PROFILER_CG_CONTROL_RELEASE + +/* utility mask for the controlMask parameter for all fields */ +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_RELEASE \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _RELEASE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _RELEASE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _RELEASE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _RELEASE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _RELEASE)| \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _RELEASE) diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h b/userspace/sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h new file mode 100644 index 0000000..54c6441 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlb0cc/ctrlb0ccbase.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl2080/ctrl2080gpu.h" // NV2080_CTRL_GPU_REG_OP +#define NVB0CC_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xB0CC, NVB0CC_CTRL_##cat, idx) + +/* MAXWELL_PROFILER command categories (6 bits) */ +#define NVB0CC_CTRL_RESERVED (0x00) +#define NVB0CC_CTRL_PROFILER (0x01) +#define NVB0CC_CTRL_INTERNAL (0x02) + +/*! + * NVB0CC_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVB0CC_CTRL_CMD_NULL (0xb0cc0000) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + +/* _ctrlb0ccbase_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h b/userspace/sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h new file mode 100644 index 0000000..3723dea --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h @@ -0,0 +1,283 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlb0cc/ctrlb0ccinternal.finn +// + +#include "ctrl/ctrlb0cc/ctrlb0ccbase.h" + +#include "ctrl/ctrlb0cc/ctrlb0ccprofiler.h" /* Some controls derivative of b0ccprofiler */ +/*! + * @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM + */ +#define NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM (0xb0cc0204) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID" */ + + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS_MESSAGE_ID (0x0U) + +typedef struct NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS { + NV_DECLARE_ALIGNED(NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS params, 8); +} NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_INTERNAL_QUIESCE_PMA_CHANNEL + * + * This command is used to quiesce ongoing HWPM streamout and wait for PMA engine to + * become idle. After this point, no new PMA records would be generated and + * membytes streaming would be triggered if GR context is resident or HWPM ctxsw is disabled. + */ +#define NVB0CC_CTRL_CMD_INTERNAL_QUIESCE_PMA_CHANNEL (0xb0cc0201) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS { + /*! + * [in] The PMA Channel Index associated with a given PMA stream. + */ + NvU32 pmaChannelIdx; + + /*! + * [out] Will return if membytes streaming was triggered, to decide if + * we need to poll membytes value on guest to complete streamout. + */ + NvBool bMembytesPollingRequired; +} NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_INTERNAL_SRIOV_PROMOTE_PMA_STREAM + * + * Currently only used in vGPU full SRIOV mode. + * This command is used to promote VAs and required info about the HWPM IB + * and PMA buffers from guest to host in full SRIOV mode. + */ +#define NVB0CC_CTRL_CMD_INTERNAL_SRIOV_PROMOTE_PMA_STREAM (0xb0cc0202) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS { + /*! + * [in] The PMA Channel Index associated with a given PMA stream. + */ + NvU32 pmaChannelIdx; + /*! + * [in] PMA records buffer VA. + */ + NV_DECLARE_ALIGNED(NvU64 pmaBufferVA, 8); + + /*! + * [in] size of the PMA records buffer. This must be <= NVB0CC_PMA_BUFFER_SIZE_MAX. + */ + NV_DECLARE_ALIGNED(NvU64 pmaBufferSize, 8); + + /*! + * [in] Membytes buffer VA. + */ + NV_DECLARE_ALIGNED(NvU64 membytesVA, 8); + + /*! + * [in] HWPM PMA Instance Block PA + */ + NV_DECLARE_ALIGNED(NvU64 hwpmIBPA, 8); + + /*! + * [in] HWPM PMA Instance Block aperture + */ + NvU8 hwpmIBAperture; +} NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_INTERNAL_PERMISSIONS_INIT + * + * This command is used to convey the client permissions for appropriate + * profiling capability initialization + */ +#define NVB0CC_CTRL_CMD_INTERNAL_PERMISSIONS_INIT (0xb0cc0203) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS { + /*! + * [in] Is Admin profiling permitted + */ + NvBool bAdminProfilingPermitted; + + /*! + * [in] Is Device profiling permitted + */ + NvBool bDevProfilingPermitted; + + /*! + * [in] Is Device tracing permitted + */ + NvBool bDevTracePermitted; + + /*! + * [in] Is Context profiling permitted + */ + NvBool bCtxProfilingPermitted; + + /*! + * [in] Is Video memory profiling permitted + */ + NvBool bVideoMemoryProfilingPermitted; + + /*! + * [in] Is SYS memory profiling permitted + */ + NvBool bSysMemoryProfilingPermitted; + + /*! + * [in] Is Async CE profiling permitted + */ + NvBool bAsyncCeProfilingPermitted; +} NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS; + +#define NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS { + /*! + * [in] Memory handle (RW memory) for streaming records. + * Size of this must be >= @ref pmaBufferOffset + @ref pmaBufferSize. + */ + NvHandle hMemPmaBuffer; + + /*! + * [in] Start offset of PMA buffer (offset in @ref hMemPmaBuffer). + */ + NV_DECLARE_ALIGNED(NvU64 pmaBufferOffset, 8); + + /*! + * [in] size of the buffer. This must be <= NVB0CC_PMA_BUFFER_SIZE_MAX. + */ + NV_DECLARE_ALIGNED(NvU64 pmaBufferSize, 8); + + /*! + * [in] Memory handle (RO memory) for streaming number of bytes available. + * Size of this must be of at least @ref pmaBytesAvailableOffset + + * @ref NVB0CC_PMA_BYTES_AVAILABLE_SIZE. + */ + NvHandle hMemPmaBytesAvailable; + + /*! + * [in] Start offset of PMA bytes available buffer (offset in @ref hMemPmaBytesAvailable). + */ + NV_DECLARE_ALIGNED(NvU64 pmaBytesAvailableOffset, 8); + + /*! + * [in] Enable ctxsw for PMA stream. + */ + NvBool ctxsw; + + /*! + * [in/out] The PMA Channel Index associated with a given PMA stream. + * This parameter is input when bInputPmaChIdx is true, else it's output parameter. + */ + NvU32 pmaChannelIdx; + + /*! + * [out] PMA buffer VA. Note that this is a HWPM Virtual address. + */ + NV_DECLARE_ALIGNED(NvU64 pmaBufferVA, 8); + + /*! + * [In] This field must be specified by the client to indicate whether the + * pmaChannelIdx is input parameter or output parameter. + */ + NvBool bInputPmaChIdx; +} NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS; + + + +/*! + * NVB0CC_CTRL_CMD_INTERNAL_FREE_PMA_STREAM + * + * Internal logic for PMA Stream Free + */ +#define NVB0CC_CTRL_CMD_INTERNAL_FREE_PMA_STREAM (0xb0cc0206) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS { + /*! + * [in] The PMA channel index associated with a given PMA stream. + */ + NvU32 pmaChannelIdx; +} NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_INTERNAL_GET_MAX_PMAS + * + * Get the maximum number of PMA channels + */ +#define NVB0CC_CTRL_CMD_INTERNAL_GET_MAX_PMAS (0xb0cc0207) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS { + /*! + * [out] Max number of PMA channels + */ + NvU32 maxPmaChannels; +} NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_INTERNAL_BIND_PM_RESOURCES + * + * Internally bind PM resources. + */ +#define NVB0CC_CTRL_CMD_INTERNAL_BIND_PM_RESOURCES (0xb0cc0208) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | 0x8" */ + + +/*! + * NVB0CC_CTRL_CMD_INTERNAL_UNBIND_PM_RESOURCES + * + * Internally unbind PM resources. + */ +#define NVB0CC_CTRL_CMD_INTERNAL_UNBIND_PM_RESOURCES (0xb0cc0209) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | 0x9" */ + +/*! + * NVB0CC_CTRL_CMD_INTERNAL_RESERVE_HWPM_LEGACY + * + * Reserve legacy HWPM resources + */ +#define NVB0CC_CTRL_CMD_INTERNAL_RESERVE_HWPM_LEGACY (0xb0cc020a) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID (0xaU) + +typedef struct NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS { + /*! + * [in] Enable ctxsw for HWPM. + */ + NvBool ctxsw; +} NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS; + +/* _ctrlb0ccinternal_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccpower.h b/userspace/sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccpower.h new file mode 100644 index 0000000..672aa24 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccpower.h @@ -0,0 +1,402 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlb0cc/ctrlb0ccpower.finn +// + +#include "ctrl/ctrlb0cc/ctrlb0ccbase.h" + +/* + * NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES + * + * This command attempts to enable or disable various clock-gating features of + * the GPU on behalf of the profiler. If this command is unable to set the + * clock-gating feature state of any of the requested features, this command + * will fail and none of the requested features will be modified. If this + * command fails because one or more clock-gating feature requests were + * rejected, it will return NV_ERR_STATE_IN_USE in the globalStatus + * parameter and the fields in the statusMask parameter for the features for + * which the requests were rejected will have the value + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_REJECTED. + * If a given feature is not supported on the GPU, the field for that clock- + * gating feature will have the value + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_NOT_SUPPORTED in the + * statusMask parameter, but this condition by itself will not cause the + * command to fail. Even if this command fails, the field for clock-gating + * features which would have successfully changed will have the value + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_FULFILLED in the statusMask + * parameter. + * + * Each of the clock-gating features is reference-counted individually, so + * that multiple MAXWELL_PROFILER objects may request and rely on the same + * settings for the features simultaneously. Each clock-gating feature is + * locked to the requested state until the MAXWELL_PROFILER object is freed or + * the NVB0CC_CTRL_CMD_POWER_RELEASE_FEATURES command is called for that + * feature. + * + * Currently, only MAXWELL_PROFILER requests for power features using this + * command are reference counted. Changes to the power feature settings made + * either by other control commands or the RM itself may interfere with the + * settings requested by MAXWELL_PROFILER instances. + * + * This command will always return NV_OK when given valid + * parameters. If there is any other failure that prevents the clock-gating + * features from being set appropriately, the globalStatus parameter will + * indicate this and the statusMask parameter will indicate which clock-gating + * feature requests failed and why. + * + * controlMask + * This parameter indicates which clock-gating features the request should + * apply to. This parameter has the following fields: + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG + * The value of this field indicates whether this request should apply + * to engine-level clock-gating of the GR engine. Valid values for + * this field are: + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE + * This value indicates that the GR engine-level clock-gating + * should be ignored. This will not affect the reference count for + * this feature. + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_DISABLE + * This value indicates that the GR engine-level clock-gating + * should be disabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_ENABLE + * This value indicates that the GR engine-level clock-gating + * should be enabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG + * The value of this field indicates whether this request should apply + * to block-level clock-gating. Valid values for this field are: + * NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE + * This value indicates that block-level clock-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_DISABLE + * This value indicates that block-level clock-gating should be + * disabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_ENABLE + * This value indicates that block-level clock-gating should be + * enabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG + * The value of this field indicates whether this request should apply + * to second-level clock-gating. Valid values for this field are: + * NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE + * This value indicates that second-level clock-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_DISABLE + * This value indicates that second-level clock-gating should be + * disabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_ENABLE + * This value indicates that second-level clock-gating should be + * enabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG + * The value of this field indicates whether this request should apply + * to GR engine-level power-gating. Valid values for this field are: + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE + * This value indicates that engine-level power-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_DISABLE + * This value indicates that engine-level power-gating should be + * disabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_ENABLE + * This value indicates that engine-level power-gating should be + * enabled. + * Note that this field is only temporary to allow reference counting + * restricted to MAXWELL_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN + * The value of this field indicates whether this request should apply + * to SM idle slowdown. Valid values for this field are: + * NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE + * This value indicates that SM idle slowdown should be ignored. + * This will not affect the reference count for this feature. + * NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_DISABLE + * This value indicates that SM idle slowdown should be disabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_ENABLE + * This value indicates that SM idle slowdown should be enabled. + * Note that this field is only temporary to allow reference counting + * restricted to MAXWELL_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * NVB0CC_CTRL_POWER_FEATURE_MASK_VAT + * The value of this field indicates whether this request should apply + * to VAT. Valid values for this field are: + * NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE + * This value indicates that VAT should be ignored. + * This will not affect the reference count for this feature. + * NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_DISABLE + * This value indicates that VAT should be disabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_ENABLE + * This value indicates that VAT should be enabled. + * Note that this field is only temporary to allow reference counting + * restricted to MAXWELL_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * globalStatus + * This parameter returns the overall status of the requests for all + * clock-gating controls. If the value of this parameter is not + * NV_OK, none of the clock-gating controls will be set as + * requested. Possible values for this parameter are: + * NV_OK + * This value indicates that all of the clock-gating control requests + * were either fulfilled or not supported on the hardware. + * NV_ERR_INVALID_REQUEST + * This value indicates that at least one of the clock-gating control + * requests were invalid given the MAXWELL_PROFILER instance's + * outstanding requests. + * NV_ERR_STATE_IN_USE + * This value indicates that at least one of the clock-gating controls + * has already been locked to a conflicting state by another + * MAXWELL_PROFILER instance or the RM itself. + * statusMask + * This parameter returns the status of the request to set each clock- + * gating control specified by the controlMask parameter. The fields are + * identical to those of the controlMask parameter. For each field for + * which the corresponding field in the controlMask parameter has the + * value NVB0CC_CTRL_POWER_FEATURE_MASK_*_IGNORE, the value is + * undefined. For each field for which the corresponding field in the + * controlMask parameter has the value + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST, the value will be + * one of the following: + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_FULFILLED + * This value indicates that the clock-gating feature corresponding to + * the field in question was enabled or disabled according to the + * controlMask parameter, and the reference count for the feature was + * incremented accordingly. + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_REJECTED + * This value indicates that the clock-gating feature corresponding to + * the field in question was not set to the expected state according + * to the controlMask parameter because another conflicting request is + * currently outstanding for the clock-gating feature. + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_FAILED + * This value indicates that the clock-gating feature corresponding to + * the field in question was not set to the expected state according + * to the controlMask parameter because the attempt to do so failed + * with an error other than a conflicting request. + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_NOT_SUPPORTED + * This value indicates that the clock-gating feature corresponding to + * the field in question is not supported on this GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES (0xb0cc0301) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_POWER_INTERFACE_ID << 8) | NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS { + NvU32 globalStatus; + NvU32 controlMask; + NvU32 statusMask; +} NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS; + +/* valid fields for the controlMask and statusMask parameters */ +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG 1:0 +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG 3:2 +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG 5:4 + +/* + * The following are temporary fields for the controlMask and statusMask + * parameters. They are required to reference count their respective features + * until the existing RM controls can be safely updated, and the definitions + * for these features will be removed soon after that. + */ +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG 7:6 +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN 9:8 +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT 11:10 + +/* valid values for fields in the controlMask parameter */ +#define NVB0CC_CTRL_POWER_FEATURE_IGNORE (0x00000000) +#define NVB0CC_CTRL_POWER_FEATURE_DISABLE (0x00000001) +#define NVB0CC_CTRL_POWER_FEATURE_ENABLE (0x00000002) + +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE NVB0CC_CTRL_POWER_FEATURE_IGNORE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_DISABLE NVB0CC_CTRL_POWER_FEATURE_DISABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_ENABLE NVB0CC_CTRL_POWER_FEATURE_ENABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE NVB0CC_CTRL_POWER_FEATURE_IGNORE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_DISABLE NVB0CC_CTRL_POWER_FEATURE_DISABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_ENABLE NVB0CC_CTRL_POWER_FEATURE_ENABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE NVB0CC_CTRL_POWER_FEATURE_IGNORE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_DISABLE NVB0CC_CTRL_POWER_FEATURE_DISABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_ENABLE NVB0CC_CTRL_POWER_FEATURE_ENABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE NVB0CC_CTRL_POWER_FEATURE_IGNORE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_DISABLE NVB0CC_CTRL_POWER_FEATURE_DISABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_ENABLE NVB0CC_CTRL_POWER_FEATURE_ENABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE NVB0CC_CTRL_POWER_FEATURE_IGNORE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_DISABLE NVB0CC_CTRL_POWER_FEATURE_DISABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_ENABLE NVB0CC_CTRL_POWER_FEATURE_ENABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE NVB0CC_CTRL_POWER_FEATURE_IGNORE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_DISABLE NVB0CC_CTRL_POWER_FEATURE_DISABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_ENABLE NVB0CC_CTRL_POWER_FEATURE_ENABLE +/* possible values for fields in the statusMask parameter */ +#define NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED (0x00000000) +#define NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED (0x00000001) +#define NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED (0x00000002) +#define NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED (0x00000003) + +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_FULFILLED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_REJECTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_FAILED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_FULFILLED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_REJECTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_FAILED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_FULFILLED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_REJECTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_FAILED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_FULFILLED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_REJECTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_FAILED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_FULFILLED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_REJECTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_FAILED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_FULFILLED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_REJECTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_FAILED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED + +/* utility masks for the controlMask parameter for all controls */ +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL \ + DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_VAT) +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL_IGNORE \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _VAT, _IGNORE) +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL_DISABLE \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _DISABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _DISABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _DISABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _DISABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _DISABLE)| \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _VAT, _DISABLE) +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL_ENABLE \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _VAT, _ENABLE) + +/* + * NVB0CC_CTRL_CMD_POWER_RELEASE_FEATUERS + * + * This command releases the MAXWELL_PROFILER's request for the given clock- + * gating features that was previously created by the + * NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES command. If the MAXWELL_PROFILER + * object does not have an outstanding request to one or more of the given + * clock-gating features, those features will be ignored while the other + * feature requests will be released. + * + * After calling this command, the calling client may not rely on the current + * value of any of the released clock-gating features to remain, even if + * several identical requests for the given clock-gating features were made + * using NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES. The RM only reference- + * counts the settings requested by MAXWELL_PROFILER instances - it does not + * reference-count multiple identical requests made using the same + * MAXWELL_PROFILER instance. + * + * All outstanding requests made using this MAXWELL_PROFILER object are + * implicitly released when the MAXWELL_PROFILER is freed. + * + * controlMask + * This parameter indicates which clock-gating features the RM should + * release the MAXWELL_PROFILER's reference to. See + * NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES for valid fields. Valid + * values for each field are: + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE + * NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE + * NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE + * NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE + * NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE + * This value indicates that the clock-gating feature associated with + * the field should not be released, even if the MAXWELL_PROFILER has an + * outstanding request for it. This will not affect the reference + * count for the feature. + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_RELEASE + * NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_RELEASE + * NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_RELEASE + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_RELEASE + * NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_RELEASE + * NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_RELEASE + * This value indicates that the MAXWELL_PROFILER's outstanding request + * for the clock-gating feature associated with the field should be + * released. This will decrement the reference count for the feature + * if the MAXWELL_PROFILER has an outstanding request for it. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVB0CC_CTRL_CMD_POWER_RELEASE_FEATURES (0xb0cc0302) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_POWER_INTERFACE_ID << 8) | NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS { + NvU32 controlMask; +} NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS; + +/* + * valid values for the controlMask parameter in addition to + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_IGNORE + */ +#define NVB0CC_CTRL_POWER_FEATURE_RELEASE (0x00000003) + +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE + + +/* _ctrlb0ccpower_h_ */ + +/* utility mask for the controlMask parameter for all fields */ +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL_RELEASE \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _RELEASE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _RELEASE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _RELEASE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _RELEASE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _RELEASE)| \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _VAT, _RELEASE) diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h b/userspace/sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h new file mode 100644 index 0000000..e55436a --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h @@ -0,0 +1,727 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlb0cc/ctrlb0ccprofiler.finn +// + +#include "ctrl/ctrlb0cc/ctrlb0ccbase.h" + + +/*! + * NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY + * + * Reserves the HWPM legacy PM system for use by the calling client. + * This PM system will only be accessible if this reservation is + * taken. + * + * If a device level reservation is held by another client, then this command + * will fail regardless of reservation scope. + * + * This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_HWPM_LEGACY. + * + */ + + +#define NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY (0xb0cc0101) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS { + /*! + * [in] Enable ctxsw for HWPM. + */ + NvBool ctxsw; +} NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_RELEASE_HWPM_LEGACY + * + * Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY. + * + * This command does not take any parameters. + * + */ +#define NVB0CC_CTRL_CMD_RELEASE_HWPM_LEGACY (0xb0cc0102) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x2" */ + +/*! + * NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC + * + * Reserves the SMPC PM system for use by the calling client. + * This PM system will only be accessible if this reservation is + * taken. + * + * Reservation scope and rules are same as for @ref NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY. + * + * This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_PM_AREA_SMPC. + * + */ +#define NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC (0xb0cc0103) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS { + /*! + * [in] Enable ctxsw for SMPC. + */ + NvBool ctxsw; +} NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_RELEASE_PM_AREA_SMPC + * + * Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC. + * + * This command does not take any parameters. + * + */ +#define NVB0CC_CTRL_CMD_RELEASE_PM_AREA_SMPC (0xb0cc0104) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x4" */ + +/*! + * NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM + * + * Allocates PMA VA and map it to the buffers for streaming records and for + * for streaming the updated bytes available in the buffer. + * + */ +#define NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM (0xb0cc0105) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID" */ + +/*! + * Defines the maximum size of PMA buffer for streamout. It can be up to 4GB minus one page + * reserved for streaming mem_bytes (see @ref NVB0CC_PMA_BYTES_AVAILABLE_SIZE). + */ +#define NVB0CC_PMA_BUFFER_SIZE_MAX (0xffe00000ULL) /* finn: Evaluated from "(4 * 1024 * 1024 * 1024 - 2 * 1024 * 1024)" */ +#define NVB0CC_PMA_BYTES_AVAILABLE_SIZE (0x1000) /* finn: Evaluated from "(4 * 1024)" */ + +#define NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS { + /*! + * [in] Memory handle (RW memory) for streaming records. + * Size of this must be >= @ref pmaBufferOffset + @ref pmaBufferSize. + */ + NvHandle hMemPmaBuffer; + + /*! + * [in] Start offset of PMA buffer (offset in @ref hMemPmaBuffer). + */ + NV_DECLARE_ALIGNED(NvU64 pmaBufferOffset, 8); + + /*! + * [in] size of the buffer. This must be <= NVB0CC_PMA_BUFFER_SIZE_MAX. + */ + NV_DECLARE_ALIGNED(NvU64 pmaBufferSize, 8); + + /*! + * [in] Memory handle (RO memory) for streaming number of bytes available. + * Size of this must be of at least @ref pmaBytesAvailableOffset + + * @ref NVB0CC_PMA_BYTES_AVAILABLE_SIZE. + */ + NvHandle hMemPmaBytesAvailable; + + /*! + * [in] Start offset of PMA bytes available buffer (offset in @ref hMemPmaBytesAvailable). + */ + NV_DECLARE_ALIGNED(NvU64 pmaBytesAvailableOffset, 8); + + /*! + * [in] Enable ctxsw for PMA stream. + */ + NvBool ctxsw; + + /*! + * [out] The PMA Channel Index associated with a given PMA stream. + */ + NvU32 pmaChannelIdx; + + /*! + * [out] PMA buffer VA. Note that this is a HWPM Virtual address. + */ + NV_DECLARE_ALIGNED(NvU64 pmaBufferVA, 8); +} NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_FREE_PMA_STREAM + * + * Releases (unmap and free) PMA stream allocated through + * @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM. + * + */ +#define NVB0CC_CTRL_CMD_FREE_PMA_STREAM (0xb0cc0106) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS { + /*! + * [in] The PMA channel index associated with a given PMA stream. + */ + NvU32 pmaChannelIdx; +} NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS; + + + +/*! + * NVB0CC_CTRL_CMD_BIND_PM_RESOURCES + * + * Binds all PM resources reserved through @ref NVB0CC_CTRL_CMD_RESERVE_* + * and with @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM with PMA engine. + * After this call, interface is ready for programming a collection + * of counters. + * @Note: Any new PM resource reservation via NVB0CC_CTRL_CMD_RESERVE_* or + * @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM request after this call will fail, + * clients need to unbind (see @ref NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES) to + * reserve more resources. + * + * This can be unbound with @ref NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES. + * + */ +#define NVB0CC_CTRL_CMD_BIND_PM_RESOURCES (0xb0cc0107) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x7" */ + +/*! + * NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES + * + * Unbinds PM resources that were bound with @ref NVB0CC_CTRL_CMD_BIND_PM_RESOURCES + * + */ +#define NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES (0xb0cc0108) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x8" */ + +/*! + * NVB0CC_CTRL_CMD_PMA_STREAM_UPDATE_GET_PUT + * + * This command updates bytes consumed by the SW and optionally gets the + * current available bytes in the buffer. + * + */ +#define NVB0CC_CTRL_CMD_PMA_STREAM_UPDATE_GET_PUT (0xb0cc0109) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_AVAILABLE_BYTES_DEFAULT_VALUE 0xFFFFFFFF +#define NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS { + /*! + * [in] Total bytes consumed by SW since last update. + */ + NV_DECLARE_ALIGNED(NvU64 bytesConsumed, 8); + + /*! + * [in] Initiate streaming of the bytes available (see @ref hMemPmaBytesAvailable). + * RM will set the memory for streaming (see @ref hMemPmaBytesAvailable) to NVB0CC_AVAILABLE_BYTES_DEFAULT_VALUE and + * client can optionally wait (see @ref bWait) for it to change from this value. + */ + NvBool bUpdateAvailableBytes; + + /*! + * [in] Waits for available bytes to get updated + */ + NvBool bWait; + + /*! + * [out] Bytes available in the PMA buffer (see @ref hMemPmaBuffer) for SW to consume. + * This will only be populated if both bUpdateAvailableBytes and bWait are set + * to TRUE. + */ + NV_DECLARE_ALIGNED(NvU64 bytesAvailable, 8); + + /*! + * [in] If set to TRUE, current put pointer will be returned in @ref putPtr. + */ + NvBool bReturnPut; + + /*! + * [out] Current PUT pointer (MEM_HEAD). + * This will only be populated if bReturnPut is set to TRUE. + */ + NV_DECLARE_ALIGNED(NvU64 putPtr, 8); + + /*! + * [in] The PMA Channel Index associated with a given PMA stream. + */ + NvU32 pmaChannelIdx; + + /*! + * [out] Set to TRUE if PMA buffer has overflowed. + */ + NvBool bOverflowStatus; +} NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS; + +/*! + * Maximum number of register operations allowed in a single request. + * @NOTE: @ref NVB0CC_REGOPS_MAX_COUNT is chosen to keep struct size + * of @ref NVB0CC_CTRL_EXEC_REG_OPS_PARAMS under 4KB. + */ +#define NVB0CC_REGOPS_MAX_COUNT (124) + +/*! + * NVB0CC_CTRL_CMD_EXEC_REG_OPS + * + * This command is used to submit an array containing one or more + * register operations for processing. Each entry in the + * array specifies a single read or write operation. Each entry is + * checked for validity in the initial pass: Only registers from PM area + * are allowed using this interface and only register from PM systems for + * which user has a valid reservation are allowed (see @ref NVB0CC_CTRL_CMD_RESERVE_*). + * Operation type (@ref NV2080_CTRL_GPU_REG_OP_TYPE_*) is not required to be passed in. + */ +#define NVB0CC_CTRL_CMD_EXEC_REG_OPS (0xb0cc010a) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_MESSAGE_ID" */ + +/*! + * Structure definition for register operation. See @ref NV2080_CTRL_GPU_REG_OP. + */ +typedef NV2080_CTRL_GPU_REG_OP NVB0CC_GPU_REG_OP; + +/*! + * Enumeration of different REG_OPS modes. This mode determines how a failure + * of a regop is handled in a batch of regops. + */ +typedef enum NVB0CC_REGOPS_MODE { + + /*! + * Either all regops will be executed or none of them will be executed. + * Failing regop will have the appropriate status (see @ref NVB0CC_GPU_REG_OP::regStatus). + */ + NVB0CC_REGOPS_MODE_ALL_OR_NONE = 0, + /*! + * All regops will be attempted and the ones that failed will have the + * the appropriate status (see @ref NVB0CC_GPU_REG_OP::regStatus). + */ + NVB0CC_REGOPS_MODE_CONTINUE_ON_ERROR = 1, +} NVB0CC_REGOPS_MODE; + +#define NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NVB0CC_CTRL_EXEC_REG_OPS_PARAMS { + /*! + * [in] Number of valid entries in the regOps array. This value cannot + * exceed NVB0CC_REGOPS_MAX_COUNT. + */ + NvU32 regOpCount; + + /*! + * [in] Specifies the mode for the entire operation see @ref NVB0CC_REGOPS_MODE. + */ + NVB0CC_REGOPS_MODE mode; + + /*! + * [out] Provides status for the entire operation. This is only valid for + * mode @ref NVB0CC_REGOPS_MODE_CONTINUE_ON_ERROR. + */ + NvBool bPassed; + + /*! + * [out] This is currently not populated. + */ + NvBool bDirect; + + /*! + * [in/out] An array (of fixed size NVB0CC_REGOPS_MAX_COUNT) of register read or write + * operations (see @ref NVB0CC_GPU_REG_OP) + * + */ + NVB0CC_GPU_REG_OP regOps[NVB0CC_REGOPS_MAX_COUNT]; +} NVB0CC_CTRL_EXEC_REG_OPS_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_RESERVE_PM_AREA_PC_SAMPLER + * + * Reserves the PC sampler system for use by the calling client. + * + * This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_PM_AREA_PC_SAMPLER. + * + * This command does not take any parameters. + * + * PC sampler is always context switched with a GR context, so reservation scope is + * always context. This requires that profiler object is instantiated with a valid GR + * context. See @ref NVB2CC_ALLOC_PARAMETERS. + */ + +#define NVB0CC_CTRL_CMD_RESERVE_PM_AREA_PC_SAMPLER (0xb0cc010b) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0xB" */ + +/*! + * NVB0CC_CTRL_CMD_RELEASE_PM_AREA_PC_SAMPLER + * + * Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_PM_AREA_PC_SAMPLER. + * + * This command does not take any parameters. + * + */ +#define NVB0CC_CTRL_CMD_RELEASE_PM_AREA_PC_SAMPLER (0xb0cc010c) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0xC" */ + +/*! + * NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS + * + * Gets the total high speed streaming credits available for the client. + * + * This command can only be performed after a bind using NVB0CC_CTRL_CMD_BIND_PM_RESOURCES. + * + */ +#define NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS (0xb0cc010d) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS { + NvU32 numCredits; +} NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_SET_HS_CREDITS_CHIPLET + * + * Sets per chiplet (pmm router) credits for high speed streaming for a pma channel. + * + * @note: This command resets the current credits to 0 before setting the new values also + * if programming fails, it will reset credits to 0 for all the chiplets. + * + */ +#define NVB0CC_CTRL_CMD_SET_HS_CREDITS (0xb0cc010e) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_MESSAGE_ID" */ + +typedef enum NVB0CC_CHIPLET_TYPE { + NVB0CC_CHIPLET_TYPE_INVALID = 0, + NVB0CC_CHIPLET_TYPE_FBP = 1, + NVB0CC_CHIPLET_TYPE_GPC = 2, + NVB0CC_CHIPLET_TYPE_SYS = 3, + + NVB0CC_CHIPLET_TYPE_IODN = 4, + NVB0CC_CHIPLET_TYPE_IODS = 5, + +} NVB0CC_CHIPLET_TYPE; + +typedef enum NVB0CC_HS_CREDITS_CMD_STATUS { + NVB0CC_HS_CREDITS_CMD_STATUS_OK = 0, + /*! + * More credits are requested than the total credits. Total credits can be queried using @ref NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS + */ + NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CREDITS = 1, + /*! + * Chiplet index is invalid. + */ + NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CHIPLET = 2, +} NVB0CC_HS_CREDITS_CMD_STATUS; + +typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO { + /*! + * Specifies the chiplet type @ref NVB0CC_CHIPLET_TYPE. + */ + NvU8 chipletType; + + /*! + * Specifies the logical index of the chiplet. + */ + NvU8 chipletIndex; + + /*! + * Specifies the number of credits for the chiplet. + */ + NvU16 numCredits; +} NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO; + +typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS { + /*! + * Status for the command @ref NVB0CC_HS_CREDITS_CMD_STATUS. + */ + NvU8 status; + + /*! + * Index of the failing @ref NVB0CC_CTRL_SET_HS_CREDITS_PARAMS::creditInfo entry. This + * is only relevant if status is NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CHIPLET. + */ + NvU8 entryIndex; +} NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS; + +#define NVB0CC_MAX_CREDIT_INFO_ENTRIES (63) + +typedef struct NVB0CC_CTRL_HS_CREDITS_PARAMS { + /*! + * [in] The PMA Channel Index associated with a given PMA stream. + */ + NvU8 pmaChannelIdx; + + /*! + * [in] Number of valid entries in creditInfo. + */ + NvU8 numEntries; + + /*! + * [out] Provides status for the entire operation. + */ + NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS statusInfo; + + /*! + * [in] Credit programming per chiplet + */ + NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO creditInfo[NVB0CC_MAX_CREDIT_INFO_ENTRIES]; +} NVB0CC_CTRL_HS_CREDITS_PARAMS; + +#define NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_MESSAGE_ID (0xEU) + +typedef NVB0CC_CTRL_HS_CREDITS_PARAMS NVB0CC_CTRL_SET_HS_CREDITS_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_GET_HS_CREDITS + * + * Gets per chiplet (pmm router) high speed streaming credits for a pma channel. + * + */ +#define NVB0CC_CTRL_CMD_GET_HS_CREDITS (0xb0cc010f) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_MESSAGE_ID (0xFU) + +typedef NVB0CC_CTRL_HS_CREDITS_PARAMS NVB0CC_CTRL_GET_HS_CREDITS_PARAMS; + + + +#define NVB0CC_CTRL_HES_INVALID (0x00000000) +#define NVB0CC_CTRL_HES_CWD (0x00000001) + +#define NVB0CC_CTRL_HES_TPC (0x00000002) + + + +typedef struct NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS { + /*! + * [in] Enable ctxsw for HES_CWD. + */ + NvBool ctxsw; +} NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS; + +typedef struct NVB0CC_CTRL_RESERVE_HES_TPC_PARAMS { + /*! + * [in] Enable ctxsw for HES_TPC. + */ + NvBool ctxsw; +} NVB0CC_CTRL_RESERVE_HES_TPC_PARAMS; + + + +/* + * NVB0CC_CTRL_HES_RESERVATION_UNION + * + * Union of all HES reservation params + * + */ +typedef union NVB0CC_CTRL_HES_RESERVATION_UNION { + NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS cwd; + + NVB0CC_CTRL_RESERVE_HES_TPC_PARAMS tpc; + +} NVB0CC_CTRL_HES_RESERVATION_UNION; + +/*! + * NVB0CC_CTRL_CMD_RESERVE_HES + * + * Reserves HES for use by the calling client. + * This PM system will only be accessible if this reservation is + * taken. + * + * This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_HES. + * + * Reservation scope and rules are same as for @ref NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY. + * + */ +#define NVB0CC_CTRL_CMD_RESERVE_HES (0xb0cc0113) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RESERVE_HES_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_RESERVE_HES_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NVB0CC_CTRL_RESERVE_HES_PARAMS { + /*! + * [in] Denotes the HES reservation type. Choose from @NVB0CC_CTRL_HES_TYPE. + */ + NvU32 type; + + /*! + * [in] Union of all possible reserve param structs. Initialize the reserveParams corresponding to the chosen type. + */ + NVB0CC_CTRL_HES_RESERVATION_UNION reserveParams; +} NVB0CC_CTRL_RESERVE_HES_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_RELEASE_HES + * + * Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_HES. + * + */ +#define NVB0CC_CTRL_CMD_RELEASE_HES (0xb0cc0114) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RELEASE_HES_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_RELEASE_HES_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NVB0CC_CTRL_RELEASE_HES_PARAMS { + /*! + * [in] type of HES needs to be released. + */ + NvU32 type; +} NVB0CC_CTRL_RELEASE_HES_PARAMS; + +/*! + * Defines the maximum count of output credit pools. + * 30 is estimate based on the # of PMAs (2) and chiplet types(3), + * which should be big enough to accommodate the required number of credit pools + */ +#define NVB0CC_CREDIT_POOL_MAX_COUNT 30 + +/*! + * NVB0CC_CTRL_CMD_GET_CHIPLET_HS_CREDIT_POOL + * + * Gets the total high speed streaming credits available for the client + * in each chiplet pool. + * + * This command is similar to @ref NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS but + * supports multiple chiplet credit pools. + * + */ +typedef struct NVB0CC_CTRL_CREDIT_POOL_INFO { + /*! + * [out] number of credits. + */ + NvU16 numCredits; + + /*! + * [out] index of credit pool. + */ + NvU8 poolIndex; + + /*! + * [out] chiplet type of credit pool. + */ + NvU8 chipletType; +} NVB0CC_CTRL_CREDIT_POOL_INFO; +#define NVB0CC_CTRL_CMD_GET_CHIPLET_HS_CREDIT_POOL (0xb0cc0115) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL_MESSAGE_ID" */ + +#define NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL_MESSAGE_ID (0x15U) + +typedef struct NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL { + /*! + * [out] chiplet-level credit pool. + */ + NVB0CC_CTRL_CREDIT_POOL_INFO poolInfos[NVB0CC_CREDIT_POOL_MAX_COUNT]; + + /*! + * [out] number of credit pools. + */ + NvU32 poolInfosCount; +} NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL; + +typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_MAPPING_INFO { + /*! + * [in] Specifies the chiplet type @ref NVB0CC_CHIPLET_TYPE. + */ + NvU8 chipletType; + + /*! + * [in] Specifies the logical index of the chiplet. + */ + NvU8 chipletIndex; + + /*! + * [out] Specifies the index of credits pool for the chiplet. + */ + NvU8 poolIndex; +} NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_MAPPING_INFO; + +/*! + * NVB0CC_CTRL_CMD_GET_HS_CREDITS_MAPPING + * + * Query the associated PMA credit pool index for given chiplet. + * + */ +#define NVB0CC_CTRL_CMD_GET_HS_CREDITS_MAPPING (0xb0cc0116) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS_MESSAGE_ID" */ +#define NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS { + /*! + * [in]: number of input queries. + */ + NvU16 numQueries; + + /*! + * [out] Provides status for the entire operation. + */ + NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS statusInfo; + + /*! + * [in/out]: Used to query the PMA credit pool index of specified chiplet. + */ + NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_MAPPING_INFO queries[NVB0CC_MAX_CREDIT_INFO_ENTRIES]; +} NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS; + + +/*! + * NVB0CC_CTRL_CMD_DISABLE_DYNAMIC_MMA_BOOST + * + * Disable the Dynamic MMA clock boost during profiler lifetime. + * + */ +#define NVB0CC_CTRL_CMD_DISABLE_DYNAMIC_MMA_BOOST (0xb0cc0117) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS_MESSAGE_ID" */ +#define NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS_MESSAGE_ID (0x17U) + +typedef struct NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS { + /*! + * [in]: En/Disable Dynamic MMA Boost. True = disable Boost; False = re-enable Boost. + */ + NvBool disable; +} NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_GET_DYNAMIC_MMA_BOOST_STATUS + * + * Request the Dynamic MMA clock boost feature enablement status. + * + */ +#define NVB0CC_CTRL_CMD_GET_DYNAMIC_MMA_BOOST_STATUS (0xb0cc0118) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS_MESSAGE_ID" */ +#define NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS { + /*! + * [out]: Dynamic MMA Boost status: true = boost enabled/available; False = Boost disabled/unavailable. + */ + NvBool enabled; +} NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS; + + +/*! + * NVB0CC_CTRL_CMD_RESERVE_CCU_PROF + * + * Reserves CCU Prof resource for use by the calling client. + * This CCU prof resource will be accessible only if this reservation is + * taken. + * + * This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_CCU_PROF. + * + */ +#define NVB0CC_CTRL_CMD_RESERVE_CCU_PROF (0xb0cc0119) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS_MESSAGE_ID" */ +#define NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS { + /*! + * [in] Enable ctxsw for CCU prof. + */ + NvBool ctxsw; +} NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS; + +#define NVB0CC_CTRL_CMD_RELEASE_CCU_PROF (0xb0cc011a) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x1a" */ + + + +/* _ctrlb0ccprofiler_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlc365.h b/userspace/sdks/nv570/inc/ctrl/ctrlc365.h new file mode 100644 index 0000000..55afe38 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlc365.h @@ -0,0 +1,331 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc365.finn +// + +#include "ctrl/ctrlxxxx.h" +#define NVC365_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xC365, NVC365_CTRL_##cat, idx) + + +#define NVC365_CTRL_RESERVED (0x00) +#define NVC365_CTRL_ACCESS_CNTR_BUFFER (0x01) + + +/* + * NVC365_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVC365_CTRL_CMD_NULL (0xc3650000) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_READ_GET + * + * This command provides the value of the GET register + * + * accessCntrBufferGetOffset [OUT] + * This parameter returns the value of the GET register + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_READ_GET (0xc3650101) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_GET_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_GET_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_GET_PARAMS { + NvU32 accessCntrBufferGetOffset; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_GET_PARAMS; + + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_WRITE_GET + * + * This command writes a value into the GET register + * + * accessCntrBufferGetValue [IN] + * This parameter specifies the new value of the GET register + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_WRITE_GET (0xc3650102) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_WRITE_GET_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_WRITE_GET_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_WRITE_GET_PARAMS { + NvU32 accessCntrBufferGetValue; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_WRITE_GET_PARAMS; + + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_READ_PUT + * + * This command provides the value of the PUT register + * + * accessCntrBufferPutOffset [OUT] + * This parameter returns the value of the PUT register + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_READ_PUT (0xc3650103) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_PUT_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_PUT_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_PUT_PARAMS { + NvU32 accessCntrBufferPutOffset; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_PUT_PARAMS; + + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_ENABLE + * + * This command enables/disables the access counters + * It also sets up RM to either service or ignore the Access Counter interrupts. + * + * intrOwnership [IN] + * This parameter specifies whether RM should own the interrupt upon return + * enable [IN] + * NV_TRUE = Access counters will be enabled + * NV_FALSE = Access counters will be disabled + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_ENABLE (0xc3650104) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_PARAMS { + NvU32 intrOwnership; + NvBool enable; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_PARAMS; + +#define NVC365_CTRL_ACCESS_COUNTER_INTERRUPT_OWNERSHIP_NO_CHANGE (0x0) +#define NVC365_CTRL_ACCESS_COUNTER_INTERRUPT_OWNERSHIP_RM (0x1) +#define NVC365_CTRL_ACCESS_COUNTER_INTERRUPT_OWNERSHIP_NOT_RM (0x2) + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_SIZE + * + * This command provides the size of the notification buffer + * + * accessCntrBufferSize [OUT] + * This parameter returns the size of the notification buffer + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_SIZE (0xc3650105) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_SIZE_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_SIZE_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_SIZE_PARAMS { + NvU32 accessCntrBufferSize; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_SIZE_PARAMS; + + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS + * + * This command provides the access counter register mappings + * + * pAccessCntrBufferGet [OUT] + * This parameter returns the pointer to the GET register + * pAccessCntrBufferPut [OUT] + * This parameter returns the pointer to the PUT register + * pAccessCntrlBufferFull [OUT] + * This parameter returns the pointer to the FULL register + * pHubIntr [OUT] + * This parameter returns the pointer to the hub interrupt register + * pHubIntrEnSet [OUT] + * This parameter returns the pointer to the set register + * pHubIntrEnClear [OUT] + * This parameter returns the pointer to the clear register + * accessCntrMask [OUT] + * This parameter returns the interrupt mask + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS (0xc3650106) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pAccessCntrBufferGet, 8); + NV_DECLARE_ALIGNED(NvP64 pAccessCntrBufferPut, 8); + NV_DECLARE_ALIGNED(NvP64 pAccessCntrBufferFull, 8); + NV_DECLARE_ALIGNED(NvP64 pHubIntr, 8); + NV_DECLARE_ALIGNED(NvP64 pHubIntrEnSet, 8); + NV_DECLARE_ALIGNED(NvP64 pHubIntrEnClear, 8); + NvU32 accessCntrMask; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS_PARAMS; + + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_FULL_INFO + * + * This command gives information whether the buffer is full + * + * fullFlag [OUT] + * This parameter specifies whether the buffer is full + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_FULL_INFO (0xc3650107) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_FULL_INFO_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_FULL_INFO_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_FULL_INFO_PARAMS { + NvBool fullFlag; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_FULL_INFO_PARAMS; + + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_RESET_COUNTERS + * + * This command resets access counters of specified type + * + * resetFlag [OUT] + * This parameter specifies that counters have been reset + * counterType [IN] + * This parameter specifies the type of counters that should be reset (MIMC, MOMC or ALL) + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_RESET_COUNTERS (0xc3650108) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_RESET_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_RESET_COUNTERS_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_RESET_COUNTERS_PARAMS { + NvBool resetFlag; + NvU32 counterType; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_RESET_COUNTERS_PARAMS; + +#define NVC365_CTRL_ACCESS_COUNTER_TYPE_MIMC (0x0) +#define NVC365_CTRL_ACCESS_COUNTER_TYPE_MOMC (0x1) +#define NVC365_CTRL_ACCESS_COUNTER_TYPE_ALL (0x2) + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_SET_CONFIG + * + * This command configures the access counters + * + * mimcGranularity [IN] + * This parameter specifies the desired granularity for mimc (64K, 2M, 16M, 16G) + * momcGranularity [IN] + * This parameter specifies the desired granularity for momc (64K, 2M, 16M, 16G) + * mimcLimit [IN] + * This parameter specifies mimc limit (none, qtr, half, full) + * momcLimit [IN] + * This parameter specifies momc limit (none, qtr, half, full) + * threshold [IN] + * This parameter specifies the threshold + * flag [IN] + * This parameter is a bitmask denoting what configurations should be made + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_SET_CONFIG (0xc3650109) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_SET_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_SET_CONFIG_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_SET_CONFIG_PARAMS { + NvU32 mimcGranularity; + NvU32 momcGranularity; + NvU32 mimcLimit; + NvU32 momcLimit; + NvU32 threshold; + NvU32 cmd; +} NVC365_CTRL_ACCESS_CNTR_SET_CONFIG_PARAMS; + +#define NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_64K (0x0) +#define NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_2M (0x1) +#define NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_16M (0x2) +#define NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_16G (0x3) + +#define NVC365_CTRL_ACCESS_COUNTER_MIMC_LIMIT (0x0) +#define NVC365_CTRL_ACCESS_COUNTER_MOMC_LIMIT (0x1) + +#define NVC365_CTRL_ACCESS_COUNTER_USE_LIMIT_NONE (0x0) +#define NVC365_CTRL_ACCESS_COUNTER_USE_LIMIT_QTR (0x1) +#define NVC365_CTRL_ACCESS_COUNTER_USE_LIMIT_HALF (0x2) +#define NVC365_CTRL_ACCESS_COUNTER_USE_LIMIT_FULL (0x3) + +#define NVC365_CTRL_ACCESS_COUNTER_SET_MIMC_GRANULARITY (0x1) +#define NVC365_CTRL_ACCESS_COUNTER_SET_MOMC_GRANULARITY (0x2) +#define NVC365_CTRL_ACCESS_COUNTER_SET_MIMC_LIMIT (0x4) +#define NVC365_CTRL_ACCESS_COUNTER_SET_MOMC_LIMIT (0x8) +#define NVC365_CTRL_ACCESS_COUNTER_SET_THRESHOLD (0x10) + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_ENABLE_INTR + * + * This command enables the access counters interrupts + * + * enable [OUT] + * This parameter specifies that the access counters interrupts are enabled + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_ENABLE_INTR (0xc365010b) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_INTR_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_INTR_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_INTR_PARAMS { + NvBool enable; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_INTR_PARAMS; +/* _ctrlc365_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlc369.h b/userspace/sdks/nv570/inc/ctrl/ctrlc369.h new file mode 100644 index 0000000..00f63e8 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlc369.h @@ -0,0 +1,157 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc369.finn +// + +#include "ctrl/ctrlxxxx.h" +/* MMU_FAULT_BUFFER control commands and parameters */ + +#define NVC369_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xC369, NVC369_CTRL_##cat, idx) + +/* MMU_FAULT_BUFFER command categories (6bits) */ +#define NVC369_CTRL_RESERVED (0x00) +#define NVC369_CTRL_MMU_FAULT_BUFFER (0x01) + +/* + * NVC369_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVC369_CTRL_CMD_NULL (0xc3690000) /* finn: Evaluated from "(FINN_MMU_FAULT_BUFFER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + + +/* + * NVC369_CTRL_CMD_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUFFER + * + * This call creates and registers a client buffer for the non replayable faults + * + * pShadowBuffer [OUT] + * This parameter represents the pointer to the shadow buffer + * + * pShadowBufferContext [OUT] + * Execution context for pShadowBuffer queue + * + * bufferSize [OUT] + * Size in bytes of the shadow buffer for non replayable faults + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC369_CTRL_CMD_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF (0xc3690101) /* finn: Evaluated from "(FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER_INTERFACE_ID << 8) | NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF_PARAMS_MESSAGE_ID" */ + +#define NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pShadowBuffer, 8); + NV_DECLARE_ALIGNED(NvP64 pShadowBufferContext, 8); + NV_DECLARE_ALIGNED(NvP64 pShadowBufferMetadata, 8); + NvU32 bufferSize; +} NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF_PARAMS; + + +/* + * NVC369_CTRL_CMD_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUFFER + * + * This call unregisters and destroys a client buffer for the non replayable + * faults + * + * pShadowBuffer [IN] + * This parameter represents the pointer to the shadow buffer + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVC369_CTRL_CMD_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF (0xc3690102) /* finn: Evaluated from "(FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER_INTERFACE_ID << 8) | NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS_MESSAGE_ID" */ + +#define NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pShadowBuffer, 8); +} NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS; + +/* + * NVC369_CTRL_CMD_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUFFER + * + * This call creates and registers a client buffer for the replayable faults + * + * pShadowBuffer [OUT] + * This parameter represents the pointer to the shadow buffer + * + * bufferSize [OUT] + * Size in bytes of the shadow buffer for non replayable faults + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC369_CTRL_CMD_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF (0xc3690103) /* finn: Evaluated from "(FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER_INTERFACE_ID << 8) | NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS_MESSAGE_ID" */ + +#define NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pShadowBuffer, 8); + NV_DECLARE_ALIGNED(NvP64 pShadowBufferMetadata, 8); + NvU32 bufferSize; +} NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS; + +/* + * NVC369_CTRL_CMD_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUFFER + * + * This call unregisters and destroys a client buffer for the replayable + * faults + * + * pShadowBuffer [IN] + * This parameter represents the pointer to the shadow buffer + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVC369_CTRL_CMD_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF (0xc3690104) /* finn: Evaluated from "(FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER_INTERFACE_ID << 8) | NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS_MESSAGE_ID" */ + +#define NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pShadowBuffer, 8); +} NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS; + +/* _ctrlc369_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlc36f.h b/userspace/sdks/nv570/inc/ctrl/ctrlc36f.h new file mode 100644 index 0000000..c4dee8f --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlc36f.h @@ -0,0 +1,159 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc36f.finn +// + + + + +/* VOLTA_CHANNEL_GPFIFO_A control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#define NVC36F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xC36F, NVC36F_CTRL_##cat, idx) + +/* VOLTA_CHANNEL_GPFIFO_A command categories (6bits) */ +#define NVC36F_CTRL_RESERVED (0x00) +#define NVC36F_CTRL_GPFIFO (0x01) +#define NVC36F_CTRL_INTERNAL (0x03) + +/* + * NVC36F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned is: NV_OK +*/ +#define NVC36F_CTRL_CMD_NULL (0xc36f0000) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN + * + * This command returns an opaque work submit token to the caller which + * can be used to write to doorbell register to finish submitting work. If + * the client has provided an error context handle during channel allocation, + * and the error context is large enough to write the doorbell token, a + * notification at index NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN + * will be sent with the work submit token value. This index may be modified + * by NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX. + * + * workSubmitToken The 32-bit work submit token + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + * + */ + +#define NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN (0xc36f0108) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID" */ + +#define NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS { + NvU32 workSubmitToken; +} NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS; + +/** + * NVC36F_CTRL_CMD_GPFIFO_UPDATE_FAULT_METHOD_BUFFER + * + * This command updates the HOST CE Fault method buffer + * data structure of Virtual channel created for SR-IOV guest. It will also + * update the fault method buffer address in the instance block of the channel + * + * bar2Addr[] + * Array contains the Virtual BAR2 address mapped by the Guest during channel + * creation. + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_INSUFFICIENT_RESOURCES + * + */ +#define NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES 0x2 +#define NVC36F_CTRL_CMD_GPFIFO_UPDATE_FAULT_METHOD_BUFFER (0xc36f0109) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS_MESSAGE_ID" */ + +#define NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS { + NV_DECLARE_ALIGNED(NvU64 bar2Addr[NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES], 8); +} NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS; + +/* + * NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX + * + * This command updates the notifier index within the error context notifier + * to write the doorbell token to. This interface cannot be used to cause the + * token to overwrite the RC notification slot. The notification slot + * referred to by the passed index must be within the bounds of the error + * context notifier object. In the case that multiple channels share the same + * error context, it is not illegal for the client to set the same index for + * multiple channels (however it is not recommended). + * + * [IN] index + * Notification slot to write the doorbell token. The initial value of this + * index is NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX (0xc36f010a) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_MESSAGE_ID" */ + +#define NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS { + NvU32 index; +} NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS; + + + +/* + * NVC36F_CTRL_CMD_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN + * + * This command is an internal command sent from Kernel RM to Physical RM + * to get work submit token + * + * Please see description of NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN for more information. + * + */ + +#define NVC36F_CTRL_CMD_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN (0xc36f0301) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | NVC36F_CTRL_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID" */ + +#define NVC36F_CTRL_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID (0x1U) + +typedef NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS NVC36F_CTRL_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS; + +/* _ctrlc36f.h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlc370/ctrlc370base.h b/userspace/sdks/nv570/inc/ctrl/ctrlc370/ctrlc370base.h new file mode 100644 index 0000000..99612e8 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlc370/ctrlc370base.h @@ -0,0 +1,66 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc370/ctrlc370base.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NVC370_DISPLAY control commands and parameters */ + +#define NVC370_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0XC370, NVC370_CTRL_##cat, idx) + +/* NVC370_DISPLAY command categories (6bits) */ +#define NVC370_CTRL_RESERVED (0x00) +#define NVC370_CTRL_CHNCTL (0x01) +#define NVC370_CTRL_RG (0x02) +#define NVC370_CTRL_OR (0x04) +#define NVC370_CTRL_INST (0x05) +#define NVC370_CTRL_VERIF (0x06) +#define NVC370_CTRL_SYSTEM (0x07) +#define NVC370_CTRL_EVENT (0x09) + +// This struct must be the first member of all C370 control calls +typedef struct NVC370_CTRL_CMD_BASE_PARAMS { + NvU32 subdeviceIndex; +} NVC370_CTRL_CMD_BASE_PARAMS; + + +/* + * NVC370_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVC370_CTRL_CMD_NULL (0xc3700000) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + +/* _ctrlc370base_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlc370/ctrlc370chnc.h b/userspace/sdks/nv570/inc/ctrl/ctrlc370/ctrlc370chnc.h new file mode 100644 index 0000000..ef2b3ad --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlc370/ctrlc370chnc.h @@ -0,0 +1,303 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc370/ctrlc370chnc.finn +// + +#include "ctrl/ctrlc370/ctrlc370base.h" +/* C370 is partially derived from 5070 */ +#include "ctrl/ctrl5070/ctrl5070chnc.h" + + + + +#define NVC370_CTRL_CMD_CHANNEL_STATE_IDLE NVBIT(0) +#define NVC370_CTRL_CMD_CHANNEL_STATE_QUIESCENT1 NVBIT(2) +#define NVC370_CTRL_CMD_CHANNEL_STATE_QUIESCENT2 NVBIT(3) +#define NVC370_CTRL_CMD_CHANNEL_STATE_BUSY NVBIT(6) +#define NVC370_CTRL_CMD_CHANNEL_STATE_DEALLOC NVBIT(7) +#define NVC370_CTRL_CMD_CHANNEL_STATE_DEALLOC_LIMBO NVBIT(8) +#define NVC370_CTRL_CMD_CHANNEL_STATE_EFI_INIT1 NVBIT(11) +#define NVC370_CTRL_CMD_CHANNEL_STATE_EFI_INIT2 NVBIT(12) +#define NVC370_CTRL_CMD_CHANNEL_STATE_EFI_OPERATION NVBIT(13) +#define NVC370_CTRL_CMD_CHANNEL_STATE_VBIOS_INIT1 NVBIT(14) +#define NVC370_CTRL_CMD_CHANNEL_STATE_VBIOS_INIT2 NVBIT(15) +#define NVC370_CTRL_CMD_CHANNEL_STATE_VBIOS_OPERATION NVBIT(16) +#define NVC370_CTRL_CMD_CHANNEL_STATE_UNCONNECTED NVBIT(17) +#define NVC370_CTRL_CMD_CHANNEL_STATE_INIT1 NVBIT(18) +#define NVC370_CTRL_CMD_CHANNEL_STATE_INIT2 NVBIT(19) +#define NVC370_CTRL_CMD_CHANNEL_STATE_SHUTDOWN1 NVBIT(20) +#define NVC370_CTRL_CMD_CHANNEL_STATE_SHUTDOWN2 NVBIT(21) + +#define NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CORE 1 +#define NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW 32 +#define NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW_IMM 32 +#define NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WRITEBACK 8 +#define NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CURSOR 8 + +/* + * NVC370_CTRL_CMD_IDLE_CHANNEL + * + * This command tries to wait or forces the desired channel state. + * + * channelClass + * This field indicates the hw class number (0xC378 - 0xC37E). + * It's defined in the h/w header (i.e. clc37d.h, etc.). + * + * channelInstance + * This field indicates which instance of the channelClass the cmd is + * meant for. (zero-based) + * + * desiredChannelStateMask + * This field indicates the desired channel states. When more than + * one bit is set, RM will return whenever it finds hardware on one + * of the states in the bistmask. + * Normal options are IDLE, QUIESCENT1 and QUIESCENT2. + * Verif only option includes BUSY as well. + * Note: + * (1) When QUIESCENT1 or QUIESCENT2 is chosen only one bit should + * be set in the bitmask. RM will ignore any other state. + * (2) Accelerators should not be required for QUIESCENT states as + * RM tries to ensure QUIESCENT forcibly on it's own. + * + * accelerators + * What accelerator bits should be used if RM timesout trying to + * wait for the desired state. This is not yet implemented since it + * should normally not be required to use these. Usage of accelerators + * should be restricted and be done very carefully as they may have + * undesirable effects. + * NOTE: accelerators should not be used directly in production code. + * + * timeout + * Timeout to use when waiting for the desired state. This is also for + * future expansion and not yet implemented. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_TIMEOUT + */ +#define NVC370_CTRL_CMD_IDLE_CHANNEL (0xc3700101) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NVC370_CTRL_IDLE_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NVC370_CTRL_IDLE_CHANNEL_MAX_INSTANCE_CORE NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CORE +#define NVC370_CTRL_IDLE_CHANNEL_MAX_INSTANCE_WINDOW NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW +#define NVC370_CTRL_IDLE_CHANNEL_MAX_INSTANCE_WINDOW_IMM NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW_IMM +#define NVC370_CTRL_IDLE_CHANNEL_MAX_INSTANCE_WRITEBACK NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WRITEBACK +#define NVC370_CTRL_IDLE_CHANNEL_MAX_INSTANCE_CURSOR NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CURSOR + +#define NVC370_CTRL_IDLE_CHANNEL_STATE_IDLE NVC370_CTRL_CMD_CHANNEL_STATE_IDLE +#define NVC370_CTRL_IDLE_CHANNEL_STATE_QUIESCENT1 NVC370_CTRL_CMD_CHANNEL_STATE_QUIESCENT1 +#define NVC370_CTRL_IDLE_CHANNEL_STATE_QUIESCENT2 NVC370_CTRL_CMD_CHANNEL_STATE_QUIESCENT2 + +#define NVC370_CTRL_IDLE_CHANNEL_STATE_BUSY NVC370_CTRL_CMD_CHANNEL_STATE_BUSY + +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_NONE (0x00000000) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_PI (NVBIT(0)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_NOTIF (NVBIT(1)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_SEMA (NVBIT(2)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_INTERLOCK (NVBIT(3)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_FLIPLOCK (NVBIT(4)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_TRASH_ONLY (NVBIT(5)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_TRASH_AND_ABORT (NVBIT(6)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_SYNCPOINT (NVBIT(7)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_TIMESTAMP (NVBIT(8)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_MGI (NVBIT(9)) + +#define NVC370_CTRL_IDLE_CHANNEL_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC370_CTRL_IDLE_CHANNEL_PARAMS { + NVC370_CTRL_CMD_BASE_PARAMS base; + NvU32 channelClass; + NvU32 channelInstance; + NvU32 desiredChannelStateMask; + NvU32 accelerators; // For future expansion. Not yet implemented + NvU32 timeout; // For future expansion. Not yet implemented + NvBool restoreDebugMode; +} NVC370_CTRL_IDLE_CHANNEL_PARAMS; + +/* + * NVC370_CTRL_CMD_SET_ACCL + * + * This command turns accelerators on and off. The use of this command + * should be restricted as it may have undesirable effects. It's + * purpose is to provide a mechanism for clients to use the + * accelerator bits to get into states that are either not detectable + * by the RM or may take longer to reach than we think is reasonable + * to wait in the RM. + * + * NVC370_CTRL_CMD_GET_ACCL + * + * This command queries the current state of the accelerators. + * + * channelClass + * This field indicates the hw class number (0xC378 - 0xC37E). + * It's defined in the h/w header (i.e. clc37d.h, etc.). + * + * channelInstance + * This field indicates which instance of the channelClass the cmd is + * meant for. (zero-based) + * + * accelerators + * Accelerators to be set in the SET_ACCEL command. Returns the + * currently set accelerators on the GET_ACCEL command. + */ + + +/* + * + * accelMask + * A mask to specify which accelerators to change with the + * SET_ACCEL command. This field does nothing in the GET_ACCEL + * command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_CHANNEL + * NV_ERR_INVALID_OWNER + * NV_ERR_GENERIC + * + */ + +#define NVC370_CTRL_CMD_SET_ACCL (0xc3700102) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NVC370_CTRL_SET_ACCL_PARAMS_MESSAGE_ID" */ + +#define NVC370_CTRL_CMD_GET_ACCL (0xc3700103) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NVC370_CTRL_GET_ACCL_PARAMS_MESSAGE_ID" */ + +#define NVC370_CTRL_CMD_CHANNEL_CANCEL_FLIP (0xc3700105) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NVC370_CTRL_CHANNEL_CANCEL_FLIP_PARAMS_MESSAGE_ID" */ + +#define NVC370_CTRL_ACCL_MAX_INSTANCE_CORE NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CORE +#define NVC370_CTRL_ACCL_MAX_INSTANCE_WINDOW NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW +#define NVC370_CTRL_ACCL_MAX_INSTANCE_WINDOW_IMM NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW_IMM +#define NVC370_CTRL_ACCL_MAX_INSTANCE_WRITEBACK NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WRITEBACK +#define NVC370_CTRL_ACCL_MAX_INSTANCE_CURSOR NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CURSOR + +#define NVC370_CTRL_ACCL_NONE NVC370_CTRL_IDLE_CHANNEL_ACCL_NONE +#define NVC370_CTRL_ACCL_IGNORE_PI NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_PI +#define NVC370_CTRL_ACCL_SKIP_NOTIF NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_NOTIF +#define NVC370_CTRL_ACCL_SKIP_SEMA NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_SEMA +#define NVC370_CTRL_ACCL_IGNORE_INTERLOCK NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_INTERLOCK +#define NVC370_CTRL_ACCL_IGNORE_FLIPLOCK NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_FLIPLOCK +#define NVC370_CTRL_ACCL_TRASH_ONLY NVC370_CTRL_IDLE_CHANNEL_ACCL_TRASH_ONLY +#define NVC370_CTRL_ACCL_TRASH_AND_ABORT NVC370_CTRL_IDLE_CHANNEL_ACCL_TRASH_AND_ABORT +#define NVC370_CTRL_ACCL_SKIP_SYNCPOINT NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_SYNCPOINT +#define NVC370_CTRL_ACCL_IGNORE_TIMESTAMP NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_TIMESTAMP +#define NVC370_CTRL_ACCL_IGNORE_MGI NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_MGI +typedef struct NVC370_CTRL_ACCL_PARAMS { + NVC370_CTRL_CMD_BASE_PARAMS base; + NvU32 channelClass; + NvU32 channelInstance; + NvU32 accelerators; + NvU32 accelMask; +} NVC370_CTRL_ACCL_PARAMS; + +#define NVC370_CTRL_SET_ACCL_PARAMS_MESSAGE_ID (0x2U) + +typedef NVC370_CTRL_ACCL_PARAMS NVC370_CTRL_SET_ACCL_PARAMS; + +#define NVC370_CTRL_GET_ACCL_PARAMS_MESSAGE_ID (0x3U) + +typedef NVC370_CTRL_ACCL_PARAMS NVC370_CTRL_GET_ACCL_PARAMS; + +#define NVC370_CTRL_CHANNEL_CANCEL_FLIP_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVC370_CTRL_CHANNEL_CANCEL_FLIP_PARAMS { + NVC370_CTRL_CMD_BASE_PARAMS base; + NvU32 channelClass; + NvU32 channelInstance; +} NVC370_CTRL_CHANNEL_CANCEL_FLIP_PARAMS; + +/* + * NVC370_CTRL_CMD_GET_CHANNEL_INFO + * + * This command returns the current channel state. + * + * channelClass + * This field indicates the hw class number (0xC378 - 0xC37E). + * It's defined in the h/w header (i.e. clc37d.h, etc.). + * + * channelInstance + * This field indicates which instance of the channelClass the cmd is + * meant for. (zero-based) + * + * channelState + * This field indicates the desired channel state in a mask form that + * is compatible with NVC370_CTRL_CMD_IDLE_CHANNEL. A mask format + * allows clients to check for one from a group of states. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + * + * Display driver uses this call to ensure that all it's methods have + * propagated through hardware's internal fifo + * (NVC370_CTRL_GET_CHANNEL_INFO_STATE_NO_METHOD_PENDING) before it calls + * RM to check whether or not the mode it set up in Assembly State Cache will + * be possible. Note that display driver can not use completion notifier in + * this case because completion notifier is associated with Update and Update + * will propagate the state from Assembly to Armed and when checking the + * possibility of a mode, display driver wouldn't want Armed state to be + * affected. + */ + + + +#define NVC370_CTRL_CMD_GET_CHANNEL_INFO (0xc3700104) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NVC370_CTRL_CMD_GET_CHANNEL_INFO_PARAMS_MESSAGE_ID" */ + +#define NVC370_CTRL_GET_CHANNEL_INFO_MAX_INSTANCE_CORE NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CORE +#define NVC370_CTRL_GET_CHANNEL_INFO_MAX_INSTANCE_WINDOW NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW +#define NVC370_CTRL_GET_CHANNEL_INFO_MAX_INSTANCE_WINDOW_IMM NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW_IMM +#define NVC370_CTRL_GET_CHANNEL_INFO_MAX_INSTANCE_WRITEBACK NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WRITEBACK +#define NVC370_CTRL_GET_CHANNEL_INFO_MAX_INSTANCE_CURSOR NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CURSOR + +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_IDLE NVC370_CTRL_CMD_CHANNEL_STATE_IDLE +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_BUSY NVC370_CTRL_CMD_CHANNEL_STATE_BUSY +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_DEALLOC NVC370_CTRL_CMD_CHANNEL_STATE_DEALLOC +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_DEALLOC_LIMBO NVC370_CTRL_CMD_CHANNEL_STATE_DEALLOC_LIMBO +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_EFI_INIT1 NVC370_CTRL_CMD_CHANNEL_STATE_EFI_INIT1 +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_EFI_INIT2 NVC370_CTRL_CMD_CHANNEL_STATE_EFI_INIT2 +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_EFI_OPERATION NVC370_CTRL_CMD_CHANNEL_STATE_EFI_OPERATION +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_VBIOS_INIT1 NVC370_CTRL_CMD_CHANNEL_STATE_VBIOS_INIT1 +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_VBIOS_INIT2 NVC370_CTRL_CMD_CHANNEL_STATE_VBIOS_INIT2 +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_VBIOS_OPERATION NVC370_CTRL_CMD_CHANNEL_STATE_VBIOS_OPERATION +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_UNCONNECTED NVC370_CTRL_CMD_CHANNEL_STATE_UNCONNECTED +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_INIT1 NVC370_CTRL_CMD_CHANNEL_STATE_INIT1 +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_INIT2 NVC370_CTRL_CMD_CHANNEL_STATE_INIT2 +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_SHUTDOWN1 NVC370_CTRL_CMD_CHANNEL_STATE_SHUTDOWN1 +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_SHUTDOWN2 NVC370_CTRL_CMD_CHANNEL_STATE_SHUTDOWN2 +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_NO_METHOD_PENDING NVC370_CTRL_GET_CHANNEL_INFO_STATE_IDLE +#define NVC370_CTRL_CMD_GET_CHANNEL_INFO_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVC370_CTRL_CMD_GET_CHANNEL_INFO_PARAMS { + NVC370_CTRL_CMD_BASE_PARAMS base; + NvU32 channelClass; + NvU32 channelInstance; + NvBool IsChannelInDebugMode; + NvU32 channelState; +} NVC370_CTRL_CMD_GET_CHANNEL_INFO_PARAMS; + + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlc370/ctrlc370event.h b/userspace/sdks/nv570/inc/ctrl/ctrlc370/ctrlc370event.h new file mode 100644 index 0000000..d92128f --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlc370/ctrlc370event.h @@ -0,0 +1,102 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc370/ctrlc370event.finn +// + +#include "ctrl/ctrlc370/ctrlc370base.h" +/* C370 is partially derived from 0073 */ +#include "ctrl/ctrl0073/ctrl0073event.h" + +/* +* headId +* This parameter indicates the ID of head on which we received interrupt +* RgSemId +* This parameter indicates the RG Semaphore Index for given head +*/ +typedef struct NVC370_RG_SEM_NOTIFICATION_PARAMS { + NvU32 headId; + NvU32 rgSemId; +} NVC370_RG_SEM_NOTIFICATION_PARAMS; + +/* NVC370_SUBDEVICE_XX event-related control commands and parameters */ + +/* + * NVC370_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * This command sets event notification state for the associated subdevice. + * This command requires that an instance of NV01_EVENT has been previously + * bound to the associated subdevice object. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the NV50_DISPLAY + * parent device to which the operation should be directed. This parameter + * must specify a value between zero and the total number of subdevices + * within the parent device. This parameter should be set to zero for + * default behavior. + * hEvent + * This parameter specifies the handle of the NV01_EVENT instance + * to be bound to the given subDeviceInstance. + * event + * This parameter specifies the type of event to which the specified + * action is to be applied. This parameter must specify a valid + * NV2080_NOTIFIERS value (see cl2080.h for more details) and should + * not exceed one less NV2080_NOTIFIERS_MAXCOUNT. + * action + * This parameter specifies the desired event notification action. + * Valid notification actions include: + * NVC370_CTRL_SET_EVENT_NOTIFICATION_DISABLE + * This action disables event notification for the specified + * event for the associated subdevice object. + * NVC370_CTRL_SET_EVENT_NOTIFICATION_SINGLE + * This action enables single-shot event notification for the + * specified event for the associated subdevice object. + * NVC370_CTRL_SET_EVENT_NOTIFICATION_REPEAT + * This action enables repeated event notification for the specified + * event for the associated system controller object. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVC370_CTRL_CMD_EVENT_SET_NOTIFICATION (0xc3700901) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_EVENT_INTERFACE_ID << 8) | NVC370_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NVC370_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U) + +typedef NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC370_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + + +/* valid action values */ +#define NVC370_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE +#define NVC370_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE +#define NVC370_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT + +/* _ctrlc370event_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlc370/ctrlc370or.h b/userspace/sdks/nv570/inc/ctrl/ctrlc370/ctrlc370or.h new file mode 100644 index 0000000..0227852 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlc370/ctrlc370or.h @@ -0,0 +1,93 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc370/ctrlc370or.finn +// + + + +#include "ctrl/ctrlc370/ctrlc370base.h" +/* C370 is partially derived from 5070 */ +#include "ctrl/ctrl5070/ctrl5070or.h" + + +// +// NVC370_CTRL_CMD_SET_SOR_FLUSH_MODE +// +// This command is used enable/disable flush mode on all the heads attached to the SOR +// Applies to NV Display 5.0+ (GB20X+ and T264+) +// [in] subDeviceInstance +// This parameter specifies the subdevice instance within the +// NV04_DISPLAY_COMMON parent device to which the operation should be +// directed. This parameter must specify a value between zero and the +// total number of subdevices within the parent device. This parameter +// should be set to zero for default behavior. +// [in] sorNumber +// All heads connected to this SOR will be programmed +// [in] headIndex +// Phase 1 flush exit programs SF_DP_LINKCTL for each head separately +// [in] attachFailedHeadMask +// Head mask for the heads where add stream failed +// [in] phase +// Flush has 2 Phases (Broad overview): +// - For Entry +// - Phase 1: Set core to debug, disable AUDIO and HDCP and engage flush +// - Phase 2: Disable SOR and SF +// - For Exit +// - Phase 1: Program SF for each stream +// - Phase 2: Exit flush, enable AUDIO and HDCP and disengage flush +// This design allows interleaving add/delete MST information in-between them +// [in] bEnable +// Whether to enable/disable flush +// Possible return values: +// NV_OK +// NV_ERR_NOT_SUPPORTED +// + +#define NVC370_CTRL_CMD_SET_SOR_FLUSH_MODE (0xc3700401U) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_OR_INTERFACE_ID << 8) | NVC370_CTRL_SET_SOR_FLUSH_MODE_PARAMS_MESSAGE_ID" */ + +#define NVC370_CTRL_SET_SOR_FLUSH_MODE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC370_CTRL_SET_SOR_FLUSH_MODE_PARAMS { + NvU32 subDeviceInstance; + NvU32 sorNumber; + NvU32 headIndex; + NvU32 attachFailedHeadMask; + NvU8 phase; + NvBool bEnable; +} NVC370_CTRL_SET_SOR_FLUSH_MODE_PARAMS; + + +/* _ctrlc370or_h_ */ + +#define NVC370_CTRL_SET_SOR_FLUSH_RUN 1:0 +#define NVC370_CTRL_SET_SOR_FLUSH_RUN_PHASE_INVALID (0x00000000U) +#define NVC370_CTRL_SET_SOR_FLUSH_RUN_PHASE1 (0x00000001U) +#define NVC370_CTRL_SET_SOR_FLUSH_RUN_PHASE2 (0x00000002U) + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlc370/ctrlc370rg.h b/userspace/sdks/nv570/inc/ctrl/ctrlc370/ctrlc370rg.h new file mode 100644 index 0000000..296760e --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlc370/ctrlc370rg.h @@ -0,0 +1,98 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc370/ctrlc370rg.finn +// + +#include "ctrl/ctrlc370/ctrlc370base.h" +/* C370 is partially derived from 5070 */ +#include "ctrl/ctrl5070/ctrl5070rg.h" + + + + +/* + * NVC370_CTRL_CMD_GET_LOCKPINS_CAPS + * + * This command returns lockpins for the specified pinset, + * as well as lockpins' HW capabilities. + * + * pinset [in] + * This parameter takes the pinset whose corresponding + * lockpin numbers need to be determined. This only affects + * the return value for the RaterLock and FlipLock pins. + * + * frameLockPin [out] + * This parameter returns the FrameLock pin index. + * + * rasterLockPin [out] + * This parameter returns the RasterLock pin index. + * + * flipLockPin [out] + * This parameter returns the FlipLock pin index. + * + * stereoPin [out] + * This parameter returns the Stereo pin index. + * + * numScanLockPins [out] + * This parameter returns the HW capability of ScanLock pins. + * + * numFlipLockPins [out] + * This parameter returns the HW capability of FlipLock pins. + * + * numStereoPins [out] + * This parameter returns the HW capability of Stereo pins. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NVC370_CTRL_CMD_GET_LOCKPINS_CAPS (0xc3700201) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_RG_INTERFACE_ID << 8) | NVC370_CTRL_GET_LOCKPINS_CAPS_PARAMS_MESSAGE_ID" */ + +#define NVC370_CTRL_GET_LOCKPINS_CAPS_FRAME_LOCK_PIN_NONE (0xffffffff) +#define NVC370_CTRL_GET_LOCKPINS_CAPS_RASTER_LOCK_PIN_NONE (0xffffffff) +#define NVC370_CTRL_GET_LOCKPINS_CAPS_FLIP_LOCK_PIN_NONE (0xffffffff) +#define NVC370_CTRL_GET_LOCKPINS_CAPS_STEREO_PIN_NONE (0xffffffff) +#define NVC370_CTRL_GET_LOCKPINS_CAPS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC370_CTRL_GET_LOCKPINS_CAPS_PARAMS { + NVC370_CTRL_CMD_BASE_PARAMS base; + NvU32 pinset; + NvU32 frameLockPin; + NvU32 rasterLockPin; + NvU32 flipLockPin; + NvU32 stereoPin; + NvU32 numScanLockPins; + NvU32 numFlipLockPins; + NvU32 numStereoPins; +} NVC370_CTRL_GET_LOCKPINS_CAPS_PARAMS; + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlc370/ctrlc370verif.h b/userspace/sdks/nv570/inc/ctrl/ctrlc370/ctrlc370verif.h new file mode 100644 index 0000000..bb58fae --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlc370/ctrlc370verif.h @@ -0,0 +1,133 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc370/ctrlc370verif.finn +// + +#include "ctrl/ctrlc370/ctrlc370base.h" +/* C370 is partially derived from 5070 */ +#include "ctrl/ctrl5070/ctrl5070verif.h" + + + + +#define NVC370_CTRL_CMD_GET_FORCE_MODESWITCH_FLAGS_OVERRIDES (0xc3700601) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_VERIF_INTERFACE_ID << 8) | NVC370_CTRL_CMD_GET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS_MESSAGE_ID" */ + +#define NVC370_CTRL_CMD_GET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC370_CTRL_CMD_GET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS { + NVC370_CTRL_CMD_BASE_PARAMS base; + NvU32 headInstance; + NvU32 modesetValue; +} NVC370_CTRL_CMD_GET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS; + +/* + * NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES + * + * This command sets modeswitch flags, prior to a modeset. The flags will be + * automatically cleared at the end of each modeset, so this function must be + * called for each modeset where overrides are desired. + * + * headInstance + * this field specifies the head for which modeswitch flags will be overridden + * + * modesetMaskValid + * this field specifies the maskset at which modeswitch flags will be overridden + * + * modesetValue + * this field specifies the override value + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES (0xc3700602) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_VERIF_INTERFACE_ID << 8) | NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS_MESSAGE_ID" */ + +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS { + NVC370_CTRL_CMD_BASE_PARAMS base; + NvU32 headInstance; + NvU32 modesetMaskValid; + NvU32 modesetValue; +} NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS; + +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_BLANK 0:0 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_BLANK_VALID 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_BLANK_INVALID 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK 1:1 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_VALID 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_INVALID 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_SHUTDOWN 2:2 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_SHUTDOWN_VALID 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_SHUTDOWN_INVALID 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOSHUTDOWN 3:3 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOSHUTDOWN_VALID 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOSHUTDOWN_INVALID 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_CHANGE_VPLL 4:4 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_CHANGE_VPLL_VALID 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_CHANGE_VPLL_INVALID 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOCHANGE_VPLL 5:5 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOCHANGE_VPLL_VALID 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOCHANGE_VPLL_INVALID 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_WAKEUP 6:6 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_WAKEUP_VALID 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_WAKEUP_INVALID 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_SHUTDOWN 7:7 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_SHUTDOWN_VALID 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_SHUTDOWN_INVALID 0x00000000 + + +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_BLANK 0:0 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_BLANK_YES 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_BLANK_NO 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK 1:1 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_YES 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_NO 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_SHUTDOWN 2:2 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_SHUTDOWN_YES 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_SHUTDOWN_NO 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOSHUTDOWN 3:3 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOSHUTDOWN_YES 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOSHUTDOWN_NO 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_CHANGE_VPLL 4:4 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_CHANGE_VPLL_YES 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_CHANGE_VPLL_NO 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOCHANGE_VPLL 5:5 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOCHANGE_VPLL_YES 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOCHANGE_VPLL_NO 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_WAKEUP 6:6 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_WAKEUP_YES 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_WAKEUP_NO 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_SHUTDOWN 7:7 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_SHUTDOWN_YES 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_SHUTDOWN_NO 0x00000000 + + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlc372/ctrlc372base.h b/userspace/sdks/nv570/inc/ctrl/ctrlc372/ctrlc372base.h new file mode 100644 index 0000000..d8423a2 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlc372/ctrlc372base.h @@ -0,0 +1,61 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc372/ctrlc372base.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NVC372_DISPLAY_SW control commands and parameters */ + +#define NVC372_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0XC372, NVC372_CTRL_##cat, idx) + +/* NVC372_DISPLAY_SW command categories (6 bits) */ +#define NVC372_CTRL_RESERVED (0x00) +#define NVC372_CTRL_CHNCTL (0x01) +#define NVC372_CTRL_VERIF (0x02) + +/* + * NVC372_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVC372_CTRL_CMD_NULL (0xc3720000) /* finn: Evaluated from "(FINN_NVC372_DISPLAY_SW_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + +// This struct must be the first member of all +// C372 control calls +typedef struct NVC372_CTRL_CMD_BASE_PARAMS { + NvU32 subdeviceIndex; +} NVC372_CTRL_CMD_BASE_PARAMS; + +/* _ctrlc372base_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlc372/ctrlc372chnc.h b/userspace/sdks/nv570/inc/ctrl/ctrlc372/ctrlc372chnc.h new file mode 100644 index 0000000..beb80dc --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlc372/ctrlc372chnc.h @@ -0,0 +1,903 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc372/ctrlc372chnc.finn +// + +#include "nvdisptypes.h" +#include "ctrl/ctrlc372/ctrlc372base.h" + +#define NVC372_CTRL_MAX_POSSIBLE_HEADS 8 +#define NVC372_CTRL_MAX_POSSIBLE_WINDOWS 32 +#define NVC372_CTRL_MAX_POSSIBLE_TILES 8 + +#define NVC372_CTRL_CMD_IS_MODE_POSSIBLE (0xc3720101) /* finn: Evaluated from "(FINN_NVC372_DISPLAY_SW_CHNCTL_INTERFACE_ID << 8) | NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS_MESSAGE_ID" */ + +/* + * NVC372_CTRL_CMD_IS_MODE_POSSIBLE + * + * This command tells whether or not the specified display config is possible. + * A config might not be possible if the display requirements exceed the GPU + * capabilities. Display requirements will be higher with more display + * surfaces, higher resolutions, higher downscaling factors, etc. GPU + * capabilities are determined by clock frequencies, the width of data pipes, + * amount of mempool available, number of thread groups available, etc. + * + * Inputs: + * head.headIndex + * This is the hardware index number for the head. Only active heads + * should be included in the input structure. + * + * head.maxPixelClkKHz + * This parameter specifies the pixel scanout rate (in KHz). + * + * head.rasterSize + * This structure specifies the total width and height of the raster that + * is sent to the display. (The width and height are also referred to as + * HTotal and VTotal, respectively.) + * + * head.rasterBlankStart + * X specifies the pixel column where horizontal blanking begins; + * Y specifies the pixel row where vertical blanking begins. + * + * head.rasterBlankEnd + * X specifies the pixel column where horizontal blanking ends; + * Y specifies the pixel row where vertical blanking ends. + * + * head.rasterVertBlank2 + * X and Y specify the pixel column/row where horizontal/vertical blanking + * ends on the second field of every pair for an interlaced raster. This + * field is not used when the raster is progressive. + * + * head.control.masterLockMode + * head.control.masterLockPin + * head.control.slaveLockMode + * head.control.slaveLockPin + * Heads that are raster locked or frame locked together will have + * synchronized timing. For example, vblank will occur at the same time on + * all of the heads that are locked together. + * + * "LockMode" tells if a head is raster locked, frame locked, or not locked. + * + * "LockPin" tells which heads are in a group of locked heads. There + * should be one master per group, and all slave heads that are locked to + * that master should have the same slaveLockPin number as the master's + * masterLockPin number. + * + * Note: The LockModes and LockPins are used only if the min v-pstate is + * required (i.e., if NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE + * is set). + * + * head.maxDownscaleFactorH + * head.maxDownscaleFactorV + * maxDownscaleFactorH and maxDownscaleFactorV represent the maximum amount + * by which the the composited image can be reduced in size, horizontally + * and vertically, respectively, multiplied by 0x400. For example, if the + * scaler input width is 1024, and the scaler output width is 2048, the + * downscale factor would be 1024 / 2048 = 0.5, and multiplying by 0x400 + * would give 512. + * + * head.outputScalerVerticalTaps + * scalerVerticalTaps indicates the maximum number of vertical taps + * allowed in the output scaler. + * + * Note that there are no #defines for tap values; the parameter is simply + * the number of taps (e.g., "2" for 2 taps). + * + * head.bUpscalingAllowedV + * bUpscalingAllowed indicates whether or not the composited image can be + * increased in size, vertically. + * + * head.bOverfetchEnabled + * bOverfetchEnabled indicates whether or not the vertical overfetch is + * enabled in postcomp scaler. + * + * head.bLtmAllowed + * bLtmAllowed indicates whether or not the Local Tone Mapping (LTM) is + * enabled in postcomp. + * + * head.minFrameIdle.leadingRasterLines + * leadingRasterLines defines the number of lines between the start of the + * frame (vsync) and the start of the active region. This includes Vsync, + * Vertical Back Porch, and the top part of the overscan border. The + * minimum value is 2 because vsync and VBP must be at least 1 line each. + * + * head.minFrameIdle.trailingRasterLines + * trailingRasterLines defines the number of lines between the end of the + * active region and the end of the frame. This includes the bottom part + * of the overscan border and the Vertical Front Porch. + * + * head.lut + * This parameter specifies whether or not the output LUT is enabled, and + * the size of the LUT. The parameter should be an + * NVC372_CTRL_IMP_LUT_USAGE_xxx value. + * On Volta, the value should be one of these: + * NVC372_CTRL_IMP_LUT_USAGE_1025, NVC372_CTRL_IMP_LUT_USAGE_257 or + * NVC372_CTRL_IMP_LUT_USAGE_NONE + * + * After Volta, the value should be one of these: + * NVC372_CTRL_IMP_LUT_USAGE_HW_MAX (this indicates that LUT is allowed) or + * NVC372_CTRL_IMP_LUT_USAGE_NONE + * (On older post-Volta products, clients may set other + * NVC372_CTRL_IMP_LUT_USAGE_xxx values, but they map to + * NVC372_CTRL_IMP_LUT_USAGE_HW_MAX in RM-SW.) + * + * head.cursorSize32p + * This parameter specifies the width of the cursor, in units of 32 pixels. + * So, for example, "8" would mean 8 * 32 = 256, for a 256x256 cursor. Zero + * means the cursor is disabled. + * + * head.tileMask + * This parameter contains a bitmask specifying which tiles must be + * assigned to the head. Normally, this parameter is set to zero, allowing + * IMP to calculate the number of tiles, but the tiles may be specified + * explicitly for test or debug. If the mode is not possible with the + * specified number of tiles, IMP will report the result as such; the + * number of tiles will not be adjusted. + * + * If tiles are forced for only a subset of active heads, IMP will + * calculate the tiles for the remaining heads (if possible). + * + * If head.bEnableDsc is enabled, head.possibleDscSliceCountMask may + * optionally be used to force the number of DSC slices. + * + * head.bEnableDsc + * bEnableDsc indicates whether or not DSC is enabled, by default. If it + * is disabled by default, but head.possibleDscSliceCountMask is non-zero, + * IMP may still present tiling solutions with DSC enabled, but only if the + * mode is not possible otherwise. (This will be indicated by a non-zero + * tileList.headDscSlices output.) + * + * head.dscTargetBppX16 + * dscTargetBppX16 is the DSC encoder's target bits per pixel, multiplied + * by 16. + * + * This field is required only on systems that support tiling, and only if + * head.possibleDscSliceCountMask is true. + * + * head.possibleDscSliceCountMask + * This is a bit mask indicating how many DSC slices are allowed in a + * scanline. If a bit n is set in the bit mask, it means that one possible + * configuration has n+1 DSC slices per scanline. + * + * This field is required only on systems that support tiling. + * + * head.maxDscSliceWidth + * The maximum allowed DSC slice width is determined by spec restrictions + * and monitor capabilities. + * + * This field is required only on systems that support tiling, and only if + * head.possibleDscSliceCountMask is true. + * + * head.bYUV420Format + * This parameter indicates output format is YUV420. + * Refer to NVD_YUV420_Output_Functional_Description.docx for more details. + * + * head.bIs2Head1Or + * This parameter specifies if the head operates in 2Head1Or mode. + * Refer to NVD_2_Heads_Driving_1_OR_Functional_Description.docx for more details. + * + * head.bGetOSLDOutput + * This parameter specifies if the client requires output for the OSLD + * (One Shot Mode with Stall Lock Disabled) mode along with legacy outputs. + * + * head.bDisableMidFrameAndDWCFWatermark + * WAR for bug 200508242. + * In linux it is possible that there will be no fullscreen window visible + * for a head. For these cases we would not hit dwcf or midframe watermarks + * leading to fbflcn timing out waiting on ok_to_switch and forcing mclk + * switch. This could lead to underflows. So if that scenario is caught (by + * Display Driver) bDisableMidFrameAndDWCFWatermark will be set to true and + * IMP will exclude dwcf and midframe contribution from the "is mclk switch + * guaranteed" calculation for the bandwidth clients of that head. + * + * window.windowIndex + * This is the hardware index number for the window. Only active windows + * should be included in the input structure. + * + * window.owningHead + * This is the hardware index of the head that will receive the window's + * output. + * + * window.formatUsageBound + * This parameter is a bitmask of all possible non-rotated mode data + * formats (NVC372_CTRL_FORMAT_xxx values). + * + * window.rotatedFormatUsageBound + * This parameter is a bitmask of all possible rotated mode data formats + * (NVC372_CTRL_FORMAT_xxx values). + * + * window.surfaceLayout + * This parameter is the surface layout of the window. It is one of + * NVC372_CTRL_LAYOUT_xxx values. + * The default value of 0U would imply that SW uses legacy equations + * (pre NVD5.0) in its computation for fetch BW. + * + * window.maxPixelsFetchedPerLine + * This parameter defines the maximum number of pixels that may need to be + * fetched in a single line for this window. Often, this can be set to the + * viewportSizeIn.Width. But if the window is known to be clipped, such + * that an entire line will never be fetched, then this parameter can be + * set to the clipped size (to improve the chances of the mode being + * possible, or possible at a lower v-pstate). + * + * In some cases, the value of this parameter must be increased by a few + * pixels in order to account for scaling overfetch, input chroma overfetch + * (420/422->444), and/or chroma output low pass filter overfetch + * (444->422/420). This value is chip dependent; refer to the + * MaxPixelsFetchedPerLine parameter in nvdClass_01.mfs for the exact + * value. In no case does the maxPixelsFetchedPerLine value need to exceed + * the surface width. + * + * window.maxDownscaleFactorH + * window.maxDownscaleFactorV + * maxDownscaleFactorH and maxDownscaleFactorV represent the maximum amount + * by which the the window image can be reduced in size, horizontally and + * vertically, respectively, multiplied by + * NVC372_CTRL_SCALING_FACTOR_MULTIPLIER. For example, + * if the scaler input width is 1024, and the scaler output width is 2048, + * the downscale factor would be 1024 / 2048 = 0.5, and multiplying by + * NVC372_CTRL_SCALING_FACTOR_MULTIPLIER if 0x400 would give 512. + * + * window.inputScalerVerticalTaps + * scalerVerticalTaps indicates the maximum number of vertical taps + * allowed in the input scaler. + * + * Note that there are no #defines for tap values; the parameter is simply + * the number of taps (e.g., "2" for 2 taps). + * + * window.bUpscalingAllowedV + * bUpscalingAllowed indicates whether or not the composited image can be + * increased in size, vertically. + * + * window.bOverfetchEnabled + * bOverfetchEnabled indicates whether or not the vertical overfetch is + * enabled in precomp scaler. + * + * window.lut + * This parameter specifies whether or not the input LUT is enabled, and + * the size of the LUT. The parameter should be an + * NVC372_CTRL_IMP_LUT_USAGE_xxx value. + * On Volta, the value should be one of these: + * NVC372_CTRL_IMP_LUT_USAGE_1025, NVC372_CTRL_IMP_LUT_USAGE_257 or + * NVC372_CTRL_IMP_LUT_USAGE_NONE + * + * After Volta, the value should be one of these: + * NVC372_CTRL_IMP_LUT_USAGE_HW_MAX (this indicates that LUT is allowed) or + * NVC372_CTRL_IMP_LUT_USAGE_NONE + * (On older post-Volta products, clients may set other + * NVC372_CTRL_IMP_LUT_USAGE_xxx values, but they map to + * NVC372_CTRL_IMP_LUT_USAGE_HW_MAX in RM-SW.) + * + * window.tmoLut + * This parameter specifies whether or not the tmo LUT is enabled, and + * the size of the LUT. This lut is used for HDR. The parameter should be + * an NVC372_CTRL_IMP_LUT_USAGE_xxx value. + * On Volta, the value should be one of these: + * NVC372_CTRL_IMP_LUT_USAGE_1025, NVC372_CTRL_IMP_LUT_USAGE_257 or + * NVC372_CTRL_IMP_LUT_USAGE_NONE + * + * After Volta, the value should be one of these: + * NVC372_CTRL_IMP_LUT_USAGE_HW_MAX (this indicates that LUT is allowed) or + * NVC372_CTRL_IMP_LUT_USAGE_NONE + * (On older post-Volta products, clients may set other + * NVC372_CTRL_IMP_LUT_USAGE_xxx values, but they map to + * NVC372_CTRL_IMP_LUT_USAGE_HW_MAX in RM-SW.) + * + * numHeads + * This is the number of heads in the "head" array of the + * NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS struct. Only active heads should be + * included in the struct. + * + * numWindows + * This is the number of windows in the "window" array of the + * NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS struct. Only active windows should + * be included in the struct. + * + * options + * This parameter specifies a bitmask for options. + * + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN + * tells IMP to calculate worstCaseMargin and worstCaseDomain. + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE + * tells IMP to calculate and report the minimum v-pstate at which the + * mode is possible. + * + * bUseCachedPerfState + * Indicates that RM should use cached values for the fastest + * available perf level (v-pstate for PStates 3.0 or pstate for + * PStates 2.0) and dispclk. This feature allows the query call to + * execute faster, and is intended to be used, for example, during + * mode enumeration, when many IMP query calls are made in close + * succession, and perf conditions are not expected to change between + * query calls. When IMP has not been queried recently, it is + * recommended to NOT use cached values, in case perf conditions have + * changed and the cached values no longer reflect the current + * conditions. + * + * testMclkFreqKHz + * This is the mclk frequency specified by the client, in KHz. RM will + * use this value to compare with the minimum dramclk required by the + * given mode. The parameter will have value 0 if the client doesn't want + * IMP query to consider this. This input is valid only on Tegra and only + * for verification purposes on internal builds. + * For this input to work, client must set + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE in the + * "options" field. + * + * Outputs: + * bIsPossible + * This output tells if the specified mode can be supported. To know if + * the mode is possible with OSLD, the bIsOSLDPossible result must + * be checked. + * + * bIsOSLDPossible + * This output is returned for each head and suggests to the clients + * if the mode will be possible or not on that head when OSLD is enabled. + * The output is only valid if bGetOSLDOutput is set in the head input. + * Note that bIsOSLDPossible is only valid if bIsPossible is true. + * + * minImpVPState + * minImpVPState returns the minimum v-pstate at which the mode is possible + * (assuming bIsPossible is TRUE). This output is valid only on dGPU, and + * only if NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in + * the "options" field. + * + * If the minimum v-pstate is required for a multi-head config, then + * masterLockMode, masterLockPin, slaveLockMode, and slaveLockPin must all + * be initialized. + * minPState + * minPState returns the pstate value corresponding to minImpVPState. It + * is returned as the numeric value of the pstate (P0 -> 0, P1 -> 1, etc.). + * This output is valid only on dGPU, and only if + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set + * in the "options" field. + * + * Note that the pstate returned by minPstateForGlitchless is not + * necessarily sufficient to meet IMP requirements. The pstate corresponds + * to the vpstate returned by minImpVPState, and this vpstate represents + * clocks that are sufficient for IMP requirements, but the pstate + * typically covers a range of frequencies (depending on the clock), and it + * is possible that only part of the range is sufficient for IMP. + * + * minRequiredBandwidthKBPS + * minRequiredBandwidthKBPS returns the minimum bandwidth that must be + * allocated to display in order to make the mode possible (assuming + * bIsPossible is TRUE). This output is valid only on Tegra, and only if + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in the + * "options" field. + * + * floorBandwidthKBPS + * floorBandwidthKBPS returns the minimum mclk frequency that can support + * the mode, and allow glitchless mclk switch, multiplied by the width of + * the data pipe. (This is an approximation of the bandwidth that can be + * provided by the min required mclk frequency, ignoring overhead.) If the + * mode is possible, but glitchless mclk switch is not, floorBandwidthKBPS + * will be calculated based on the maximum possible mclk frequency. This + * output is valid only on Tegra, and only if + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in the + * "options" field. + * + * minRequiredHubclkKHz + * minRequiredHubclkKHz returns the minimum hubclk frequency that can + * support the mode. This output is valid only on Tegra, and only if + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in the + * "options" field. + * + * vblankIncreaseInLinesForOSLDMode + * vblankIncreaseInLinesForOSLDMode returns the amount, in lines, by + * which vblank needs to be extended to achieve optimized MSCG when OSLD + * Mode is enabled (assuming bIsPossible is TRUE). Features like Panel + * Replay and Panel Self Refresh enable OSLD mode. This value is 0 if + * the vblank is large enough to accommodate spool up and MSCG latencies. + * This output is valid only if + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in the + * "options" field and bGetOSLDOutput was specified in the head input. + * + * wakeUpRgLineForOSLDMode + * wakeUpRgLineForOSLDMode returns the rg line in the vblank region at which + * the clients will be required to send a timestamped update to achieve + * optimized MSCG when OSLD Mode is enabled (assuming bIsPossible is + * is TRUE). Features like Panel Replay and Panel Self Refresh enable + * OSLD mode. This output is valid only if + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in the + * "options" field and bGetOSLDOutput was specified in the head input. + * + * worstCaseMargin + * worstCaseMargin returns the ratio of available bandwidth to required + * bandwidth, multiplied by NV5070_CTRL_IMP_MARGIN_MULTIPLIER. Available + * bandwidth is calculated in the worst case bandwidth domain, i.e., the + * domain with the least available margin. Bandwidth domains include the + * IMP-relevant clock domains, and possibly other virtual bandwidth + * domains such as AWP. + * + * Note that IMP checks additional parameters besides the bandwidth margins + * but only the bandwidth margin is reported here, so it is possible for a + * mode to have a more restrictive domain that is not reflected in the + * reported margin result. + * + * This result is not guaranteed to be valid if the mode is not possible. + * + * Note also that the result is generally calculated for the highest + * v-pstate possible (usually P0). But if the _NEED_MIN_VPSTATE is + * specified, the result will be calculated for the min possible v-pstate + * (or the highest possible v-pstate, if the mode is not possible). + * + * The result is valid only if + * NV5070_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN is set in "options". + * + * dispClkKHz + * This is the dispclk frequency selected by IMP for this mode. For dGPU, + * it will be one of the fixed frequencies from the list of frequencies + * supported by the vbios. + * + * worstCaseDomain + * Returns a short text string naming the domain for the margin returned in + * "worstCaseMargin". See "worstCaseMargin" for more information. + * + * numTilingAssignments + * This is the number of entries in the tilingAssignments array, each of + * which represents a possible distinct tiling configuration. The client + * will do the actual assignment of tiles during the modeset, but the + * information provided here will help the client to know how many tiles + * to assign to each head. + * + * The first tiling assignment (tilingAssignments[0]) is required; it will + * specify that one or more tiles must be assigned to each active head in + * order for the mode to be possible. Subsequent tiling assignments are + * optional; each higher assignment will reduce the required dispclk to a + * lower frequency, so the client may choose to use some or all of these + * assignments because they might reduce power consumption. + * + * The tiling assignments are incremental; the client may choose how many + * assignments to use (after the first one, which is required), but they + * must be used in sequence. For example, if there are five possible + * assignments (numTilingAssignments = 5), and the client wishes to apply + * the third assignment, the tiles from the first two assignments must also + * be allocated. + * + * If the client decides to use a particular tiling assignment, it should + * assign all tiles specified in that assignment. (Otherwise, there will + * be no benefit from that assignment for reducing dispclk.) + * + * A 3-head example of a set of tiling assignments is: + * numTilingAssignments = 3 + * tilingAssignments[0].numTiles = 4 + * tilingAssignments[1].numTiles = 2 + * tilingAssignments[2].numTiles = 1 + * tileList[0].head = 0 (first tile for tilingAssignments[0]) + * tileList[0].headDscSlices = 2 + * tileList[1].head = 0 (second tile for tilingAssignments[0]) + * tileList[1].headDscSlices = xxx (not used, because it is specified in + * tileList[0].headDscSlices) + * tileList[2].head = 1 (third tile for tilingAssignments[0]) + * tileList[2].headDscSlices = 1 + * tileList[3].head = 2 (fourth tile for tilingAssignments[0]) + * tileList[3].headDscSlices = 1 + * tileList[4].head = 1 (first tile for tilingAssignments[1]) + * tileList[4].headDscSlices = 2 + * tileList[5].head = 2 (second tile for tilingAssignments[1]) + * tileList[5].headDscSlices = 2 + * tileList[6].head = 0 (tile for tilingAssignments[2] + * tileList[6].headDscSlices = 3 + * + * tilingAssignments[0] always specifies the minimum tiling assignment + * necessary to make the mode possible. In this example, two tiles are + * required on head 0, but heads 1 and 2 can work with a single tile each. + * + * After the four required tiles are assigned for tilingAssignments[0], the + * client may choose to apply tilingAssignment[1] as well, to reduce + * dispclk further. Two additional tiles would be required for this, one + * on head 1 and one on head 2. Note that there would be no benefit to + * assigning a tile to only one of these two heads; all heads specified in + * the tilingAssignment must be assigned (if the tilingAssignment is to be + * used). After this assignment, head 1 and head 2 would each have two + * tiles assigned (one from tilingAssignment[0] and one from + * tilingAssignent[1]). Head 0 would still have 2 tiles assigned. + * + * If tilingAssignments[2] is also used, an additional tile would be + * assigned to head 0, bringing the tile total to three for that head. The + * number of DSC slices required for that head would be increased to three. + * + * Note that the tiling assignments do not specify which tiles to use; they + * only specify how many tiles to assign to each head. The client must + * choose which tiles to assign, based on their capabilities. + * + * tilingAssignments.numTiles + * This is the number of additional tiles required for the indexed tiling + * assignment. The tilingAssignment does not provide any benefit unless + * all of its specified tiles are assigned. + * + * tileList.head + * This specifies the head to which a tile must be assigned, to receive a + * benefit (dispclk reduction) for a given tiling assignment. + * tileList entries (head indexes) are assigned consecutively, based on the + * tilingAssignments.numTiles entries. For example, if + * tilingAssignments[0].numTiles = 3 and tilingAssignments[1].numTiles = 2, + * then the first three tileList entries (indexes 0, 1, and 2) would be for tiling + * assignment 0 and the next 2 entries (indexes 3 and 4) would be for + * tiling assignment 1. + * + * A single assignment may have multiple tileList.head entries for the same + * head (if a single head requires that more than one additional tile be + * assigned). + * + * tilelist.head indexes heads as they are indexed in the + * NVC372_CTRL_IMP_HEAD array within the IMP input data structure. (These + * do not necessarily correspond to physical head indexes.) + * + * tileList.headDscSlices + * headDscSlices gives the recommended number of DSC slices for each + * scanline for the head specified in tileList.head. If a specific tiling + * assignment has multiple tiles assigned to the same head, the + * headDscSlices value for the first tileList entry should be used; + * subsequent entries may be ignored. If multiple tilingAssignments are + * applied, the headDscSlices entry for the highest indexed + * tilingAssignment takes precedence over any entries from lower indexed + * assignments, for the same head. + * + * This field is relevant only if head.bEnableDsc is true. + * + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + * NVOS_STATUS_ERROR_GENERIC + */ +#define NVC372_CTRL_IMP_LUT_USAGE_NONE 0 +#define NVC372_CTRL_IMP_LUT_USAGE_257 1 +#define NVC372_CTRL_IMP_LUT_USAGE_1025 2 +#define NVC372_CTRL_IMP_LUT_USAGE_HW_MAX 3 + +typedef struct NVC372_CTRL_IMP_HEAD { + NvU8 headIndex; + + NvU32 maxPixelClkKHz; + + struct { + NvU32 width; + NvU32 height; + } rasterSize; + + struct { + NvU32 X; + NvU32 Y; + } rasterBlankStart; + + struct { + NvU32 X; + NvU32 Y; + } rasterBlankEnd; + + struct { + NvU32 yStart; + NvU32 yEnd; + } rasterVertBlank2; + + struct { + NV_DISP_LOCK_MODE masterLockMode; + NV_DISP_LOCK_PIN masterLockPin; + NV_DISP_LOCK_MODE slaveLockMode; + NV_DISP_LOCK_PIN slaveLockPin; + } control; + + NvU32 maxDownscaleFactorH; + NvU32 maxDownscaleFactorV; + NvU8 outputScalerVerticalTaps; + NvBool bUpscalingAllowedV; + NvBool bOverfetchEnabled; + NvBool bLtmAllowed; + + struct { + NvU16 leadingRasterLines; + NvU16 trailingRasterLines; + } minFrameIdle; + + NvU8 lut; + NvU8 cursorSize32p; + + NvU8 tileMask; + + NvBool bEnableDsc; + + NvU16 dscTargetBppX16; + + NvU32 possibleDscSliceCountMask; + + NvU32 maxDscSliceWidth; + + NvBool bYUV420Format; + + NvBool bIs2Head1Or; + + NvBool bGetOSLDOutput; + + NvBool bDisableMidFrameAndDWCFWatermark; +} NVC372_CTRL_IMP_HEAD; +typedef struct NVC372_CTRL_IMP_HEAD *PNVC372_CTRL_IMP_HEAD; + +typedef struct NVC372_CTRL_IMP_WINDOW { + NvU32 windowIndex; + NvU32 owningHead; + NvU32 formatUsageBound; + NvU32 rotatedFormatUsageBound; + NvU32 maxPixelsFetchedPerLine; + NvU32 maxDownscaleFactorH; + NvU32 maxDownscaleFactorV; + NvU8 inputScalerVerticalTaps; + NvBool bUpscalingAllowedV; + NvBool bOverfetchEnabled; + NvU8 lut; + NvU8 tmoLut; + NvU8 surfaceLayout; +} NVC372_CTRL_IMP_WINDOW; +typedef struct NVC372_CTRL_IMP_WINDOW *PNVC372_CTRL_IMP_WINDOW; + +typedef struct NVC372_TILING_ASSIGNMENT { + NvU8 numTiles; +} NVC372_TILING_ASSIGNMENT; + +typedef struct NVC372_TILE_ENTRY { + NvU8 head; + NvU8 headDscSlices; +} NVC372_TILE_ENTRY; + +#define NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN (0x00000001) +#define NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE (0x00000002) + +#define NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS { + NVC372_CTRL_CMD_BASE_PARAMS base; + + NvU8 numHeads; + NvU8 numWindows; + + NVC372_CTRL_IMP_HEAD head[NVC372_CTRL_MAX_POSSIBLE_HEADS]; + + // C form: NVC372_CTRL_IMP_WINDOW window[NVC372_CTRL_MAX_POSSIBLE_WINDOWS]; + NVC372_CTRL_IMP_WINDOW window[NVC372_CTRL_MAX_POSSIBLE_WINDOWS]; + + NvU32 options; + + NvU32 testMclkFreqKHz; + + NvBool bIsPossible; + + NvBool bIsOSLDPossible[NVC372_CTRL_MAX_POSSIBLE_HEADS]; + + NvU32 minImpVPState; + + NvU32 minPState; + + NvU32 minRequiredBandwidthKBPS; + + NvU32 floorBandwidthKBPS; + + NvU32 minRequiredHubclkKHz; + + NvU32 vblankIncreaseInLinesForOSLDMode[NVC372_CTRL_MAX_POSSIBLE_HEADS]; + + NvU32 wakeUpRgLineForOSLDMode[NVC372_CTRL_MAX_POSSIBLE_HEADS]; + + NvU32 worstCaseMargin; + + NvU32 dispClkKHz; + + NvU32 numTilingAssignments; + + NVC372_TILING_ASSIGNMENT tilingAssignments[NVC372_CTRL_MAX_POSSIBLE_TILES]; + + NVC372_TILE_ENTRY tileList[NVC372_CTRL_MAX_POSSIBLE_TILES]; + + char worstCaseDomain[8]; + + NvBool bUseCachedPerfState; +} NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS; +typedef struct NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS *PNVC372_CTRL_IS_MODE_POSSIBLE_PARAMS; + +/* valid format values */ +#define NVC372_CTRL_FORMAT_RGB_PACKED_1_BPP (0x00000001) +#define NVC372_CTRL_FORMAT_RGB_PACKED_2_BPP (0x00000002) +#define NVC372_CTRL_FORMAT_RGB_PACKED_4_BPP (0x00000004) +#define NVC372_CTRL_FORMAT_RGB_PACKED_8_BPP (0x00000008) +#define NVC372_CTRL_FORMAT_YUV_PACKED_422 (0x00000010) +#define NVC372_CTRL_FORMAT_YUV_PLANAR_420 (0x00000020) +#define NVC372_CTRL_FORMAT_YUV_PLANAR_444 (0x00000040) +#define NVC372_CTRL_FORMAT_YUV_SEMI_PLANAR_420 (0x00000080) +#define NVC372_CTRL_FORMAT_YUV_SEMI_PLANAR_422 (0x00000100) +#define NVC372_CTRL_FORMAT_YUV_SEMI_PLANAR_422R (0x00000200) +#define NVC372_CTRL_FORMAT_YUV_SEMI_PLANAR_444 (0x00000400) +#define NVC372_CTRL_FORMAT_EXT_YUV_PLANAR_420 (0x00000800) +#define NVC372_CTRL_FORMAT_EXT_YUV_PLANAR_444 (0x00001000) +#define NVC372_CTRL_FORMAT_EXT_YUV_SEMI_PLANAR_420 (0x00002000) +#define NVC372_CTRL_FORMAT_EXT_YUV_SEMI_PLANAR_422 (0x00004000) +#define NVC372_CTRL_FORMAT_EXT_YUV_SEMI_PLANAR_422R (0x00008000) +#define NVC372_CTRL_FORMAT_EXT_YUV_SEMI_PLANAR_444 (0x00010000) + +/* valid layout values */ +#define NVC372_CTRL_LAYOUT_PITCH_BLOCKLINEAR 0 +#define NVC372_CTRL_LAYOUT_PITCH 1 +#define NVC372_CTRL_LAYOUT_BLOCKLINEAR 2 + +/* valid impResult values */ +#define NVC372_CTRL_IMP_MODE_POSSIBLE 0 +#define NVC372_CTRL_IMP_NOT_ENOUGH_MEMPOOL 1 +#define NVC372_CTRL_IMP_REQ_LIMIT_TOO_HIGH 2 +#define NVC372_CTRL_IMP_VBLANK_TOO_SMALL 3 +#define NVC372_CTRL_IMP_HUBCLK_TOO_LOW 4 +#define NVC372_CTRL_IMP_INSUFFICIENT_BANDWIDTH 5 +#define NVC372_CTRL_IMP_DISPCLK_TOO_LOW 6 +#define NVC372_CTRL_IMP_ELV_START_TOO_HIGH 7 +#define NVC372_CTRL_IMP_OSLD_ELV_START_TOO_HIGH 8 +#define NVC372_CTRL_IMP_INSUFFICIENT_THREAD_GROUPS 9 +#define NVC372_CTRL_IMP_INVALID_PARAMETER 10 +#define NVC372_CTRL_IMP_UNRECOGNIZED_FORMAT 11 +#define NVC372_CTRL_IMP_UNSPECIFIED 12 + +/* + * The calculated margin is multiplied by a constant, so that it can be + * represented as an integer with reasonable precision. "0x400" was chosen + * because it is a power of two, which might allow some compilers/CPUs to + * simplify the calculation by doing a shift instead of a multiply/divide. + * (And 0x400 is 1024, which is close to 1000, so that may simplify visual + * interpretation of the raw margin value.) + */ +#define NVC372_CTRL_IMP_MARGIN_MULTIPLIER (0x00000400) + +/* scaling factor */ +#define NVC372_CTRL_SCALING_FACTOR_MULTIPLIER (0x00000400) + +#define NVC372_CTRL_CMD_NUM_DISPLAY_ID_DWORDS_PER_HEAD 2 +#define NVC372_CTRL_CMD_MAX_SORS 4 + +#define NVC372_CTRL_CMD_IS_MODE_POSSIBLE_OR_SETTINGS (0xc3720102) /* finn: Evaluated from "(FINN_NVC372_DISPLAY_SW_CHNCTL_INTERFACE_ID << 8) | NVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS_MESSAGE_ID" */ + +/* + * NVC372_CTRL_CMD_IS_MODE_POSSIBLE_OR_SETTINGS + * + * This command tells us if output resource pixel clocks requested by client + * is possible or not. Note that this will not be used for displayport sor as + * it will be handled by displayport library. + * + * Inputs: + * numHeads + * This is the number of heads in the "head" array of the + * NVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS struct. Only active heads + * should be included in the struct. + * + * head.headIndex + * This is the hardware index number for the head. Only an active head + * should be included in the input structure. + * + * head.maxPixelClkKHz + * This parameter specifies the pixel scanout rate (in KHz). + * + * head.displayId + * Array of displayId's associated with the head. This is limited by + * NVC372_CTRL_CMD_NUM_DISPLAY_ID_DWORDS_PER_HEAD. + * + * sor.ownerMask + * Consists of a mask of all heads that drive this sor. + * + * sor.protocol + * Defines the protocol of the sor in question. + * + * sor.pixelReplicateMode + * Defines which pixel replication mode is requested. This can be off + * or X2 or X4 mode. + * + * Outputs: + * bIsPossible + * This tells us that the requested pixel clock can be supported. + */ + + +#define NVC372_CTRL_IS_MODE_POSSIBLE_DISPLAY_ID_SKIP_IMP_OUTPUT_CHECK (0xAAAAAAAA) + +typedef struct NVC372_CTRL_IMP_OR_SETTINGS_HEAD { + NvU8 headIndex; + NvU32 maxPixelClkKhz; + + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP outputResourcePixelDepthBPP; + + NvU32 displayId[NVC372_CTRL_CMD_NUM_DISPLAY_ID_DWORDS_PER_HEAD]; +} NVC372_CTRL_IMP_OR_SETTINGS_HEAD; +typedef struct NVC372_CTRL_IMP_OR_SETTINGS_HEAD *PNVC372_CTRL_IMP_OR_SETTINGS_HEAD; + +#define NVC372_CTRL_CMD_SOR_OWNER_MASK_NONE (0x00000000) +#define NVC372_CTRL_CMD_SOR_OWNER_MASK_HEAD(i) (1 << i) + +#define NVC372_CTRL_CMD_SOR_PROTOCOL_SINGLE_TMDS_A (0x00000000) +#define NVC372_CTRL_CMD_SOR_PROTOCOL_SINGLE_TMDS_B (0x00000001) +#define NVC372_CTRL_CMD_SOR_PROTOCOL_DUAL_TMDS (0x00000002) +#define NVC372_CTRL_CMD_SOR_PROTOCOL_SUPPORTED (0xFFFFFFFF) + +#define NVC372_CTRL_IS_MODE_POSSIBLE_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NVC372_CTRL_IS_MODE_POSSIBLE_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NVC372_CTRL_IS_MODE_POSSIBLE_PIXEL_REPLICATE_MODE_X4 (0x00000002) + +typedef struct NVC372_CTRL_IMP_OR_SETTINGS_SOR { + NvU32 ownerMask; + NvU32 protocol; + NvU32 pixelReplicateMode; +} NVC372_CTRL_IMP_OR_SETTINGS_SOR; +typedef struct NVC372_CTRL_IMP_OR_SETTINGS_SOR *PNVC372_CTRL_IMP_OR_SETTINGS_SOR; + +#define NVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS { + NVC372_CTRL_CMD_BASE_PARAMS base; + + NvU32 numHeads; + + NVC372_CTRL_IMP_OR_SETTINGS_HEAD head[NVC372_CTRL_MAX_POSSIBLE_HEADS]; + + NVC372_CTRL_IMP_OR_SETTINGS_SOR sor[NVC372_CTRL_CMD_MAX_SORS]; + + NvBool bIsPossible; +} NVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS; +typedef struct NVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS *PNVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS; + +#define NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN (0xc3720104) /* finn: Evaluated from "(FINN_NVC372_DISPLAY_SW_CHNCTL_INTERFACE_ID << 8) | NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS_MESSAGE_ID" */ + +/* + * NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN + * + * This control call is used by clients to query the active viewport for the + * provided window precalculated at the beginning of each frame. + * + * Inputs: + * windowIndex + * Index of the window to be queried. Must be connected to an active head. + * + * Outputs: + * activeViewportPointIn + * X and Y coordinates of the active viewport on the provided window for + * the most recent frame. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT if the window index is invalid + * NV_ERR_INVALID_STATE if the window index isn't connected to a head + * NV_ERR_NOT_SUPPORTED + */ +#define NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS { + NVC372_CTRL_CMD_BASE_PARAMS base; + + NvU32 windowIndex; + + struct { + NvU32 x; + NvU32 y; + } activeViewportPointIn; +} NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS; +typedef struct NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS *PNVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS; + +/* _ctrlc372chnc_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlc56f.h b/userspace/sdks/nv570/inc/ctrl/ctrlc56f.h new file mode 100644 index 0000000..8f30a74 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlc56f.h @@ -0,0 +1,187 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc56f.finn +// + + + + +/* AMPERE_CHANNEL_GPFIFO_A control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F + +#include "cc_drv.h" + + + +#define NVC56F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xC36F, NVC56F_CTRL_##cat, idx) + +/* AMPERE_CHANNEL_GPFIFO_A command categories (6bits) */ +#define NVC56F_CTRL_RESERVED (0x00) +#define NVC56F_CTRL_GPFIFO (0x01) + +/* + * NVC56F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned is: NV_OK +*/ +#define NVC56F_CTRL_CMD_NULL (NVC36F_CTRL_CMD_NULL) + +/* + * NVC56F_CTRL_CMD_GET_KMB_STAT_ADDR + * + * This struct defines the addresses to log encryption statistics + * amountEncryptedAddr + * Amount of bytes encrypted + * numberEncryptedAddr + * Number of times data was encrypted. + */ +typedef struct NVC56F_CTRL_CMD_GET_KMB_STAT_ADDR { + NV_DECLARE_ALIGNED(NvP64 amountEncryptedAddr, 8); + NV_DECLARE_ALIGNED(NvP64 numberEncryptedAddr, 8); +} NVC56F_CTRL_CMD_GET_KMB_STAT_ADDR; + +/* + * NVC56F_CTRL_CMD_GET_KMB + * + * This command returns the Key Material Bundle (KMB) for the current channel. + * + * kmb [OUT] The KMB for the channel. + * hMemory [IN] Memory handle to the encryption statistics buffer for the channel. + * keyRotationLowerThreshold [OUT] Key rotation lower threshold. + * keyRotationUpperThreshold [OUT] Key rotation upper threshold. + * + * The key rotation thresholds are in units of + * (amount of data encrypted in units of 16 bytes + number of encryption invocations). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NVC56F_CTRL_CMD_GET_KMB (0xc56f010b) /* finn: Evaluated from "(FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC56F_CTRL_CMD_GET_KMB_PARAMS_MESSAGE_ID" */ + +#define NVC56F_CTRL_CMD_GET_KMB_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NVC56F_CTRL_CMD_GET_KMB_PARAMS { + CC_KMB kmb; + NvHandle hMemory; + NV_DECLARE_ALIGNED(NvU64 keyRotationLowerThreshold, 8); + NV_DECLARE_ALIGNED(NvU64 keyRotationUpperThreshold, 8); +} NVC56F_CTRL_CMD_GET_KMB_PARAMS; + +/* + * NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV + * + * This command rotates the IVs for secure channels. + * + * rotateIvType [IN] Which IVs to rotate. + * updatedKmb [OUT] Updated KMB after the IV rotation. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV (0xc56f010c) /* finn: Evaluated from "(FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS_MESSAGE_ID" */ + +#define NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS { + ROTATE_IV_TYPE rotateIvType; + CC_KMB updatedKmb; +} NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY + * + * This command sets the CC security policy. + * It can only be set before GpuReadyState is set. + * Is ignored after GpuReadyState is set. + * + * attackerAdvantage [IN] + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +/* + * The minimum and maximum values for attackerAdvantage. + * The probability of an attacker successfully guessing the contents of an encrypted packet go up ("attacker advantage"). + */ +#define SECURITY_POLICY_ATTACKER_ADVANTAGE_DEFAULT (60) +#define SET_SECURITY_POLICY_ATTACKER_ADVANTAGE_MIN (50) +#define SET_SECURITY_POLICY_ATTACKER_ADVANTAGE_MAX (65) + +#define NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY (0xc56f010d) /* finn: Evaluated from "(FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID" */ + +#define NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY_PARAMS { + NV_DECLARE_ALIGNED(NvU64 attackerAdvantage, 8); +} NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_GET_SECURITY_POLICY + * + * This command get the CC security policy. + * + * attackerAdvantage [OUT] + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV_CONF_COMPUTE_CTRL_GET_SECURITY_POLICY (0xc56f010e) /* finn: Evaluated from "(FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NV_CONF_COMPUTE_CTRL_GET_SECURITY_POLICY_PARAMS_MESSAGE_ID" */ + +#define NV_CONF_COMPUTE_CTRL_GET_SECURITY_POLICY_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV_CONF_COMPUTE_CTRL_GET_SECURITY_POLICY_PARAMS { + NV_DECLARE_ALIGNED(NvU64 attackerAdvantage, 8); +} NV_CONF_COMPUTE_CTRL_GET_SECURITY_POLICY_PARAMS; + + + +/* _ctrlc56f.h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlc637.h b/userspace/sdks/nv570/inc/ctrl/ctrlc637.h new file mode 100644 index 0000000..fcb1dff --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlc637.h @@ -0,0 +1,436 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc637.finn +// + +#include "nvlimits.h" +#include "ctrl/ctrlxxxx.h" +/* AMPERE_SMC_PARTITION_REF commands and parameters */ + +#define NVC637_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xC637, NVC637_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NVC637_CTRL_RESERVED (0x00) +#define NVC637_CTRL_EXEC_PARTITIONS (0x01) + + +/*! + * NVC637_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVC637_CTRL_CMD_NULL (0xc6370000) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/*! + * NVC637_CTRL_EXEC_PARTITIONS_INFO + * + * This structure specifies resources in an execution partition + * + * gpcCount[IN/OUT] + * - Total Number of GPCs in this partition (including GFX Supported GPCs) + * + * gfxGpcCount[IN/OUT] + * - Number of GFX GPCs in this partition. This should be a subset of gpcs inlcuded in gpcCount + * + * VeidCount[OUT] + * - Number of VEIDs available in this partition. + * + * ceCount[IN/OUT] + * - Copy Engines in this partition + * + * nvEncCount[IN/OUT] + * - Encoder Engines in this partition + * + * nvDecCount[IN/OUT] + * - Decoder Engines in this partition + * + * nvJpgCount[IN/OUT] + * - Jpg Engines in this partition + * + * nvOfaCount[IN/OUT] + * - Ofa engines in this partition + * + * sharedEngFlag[IN/OUT] + * - Flags determining whether above engines are shared with other execution partitions + * + * veidStartOffset[OUT] + * - VEID start offset within GPU partition + * + * smCount[IN/OUT] + * - Number of active SMs in this partition + * + * spanStart[IN/OUT] + * - First slot in the span for an execution partition placement + * + * computeSize[IN/OUT] + * - Flag corresponding to the compute profile used + * + * execPartFlags[IN/OUT] + * - Bitmap of NVC637_CTRL_EXEC_PARTITIONS_FLAGS* + */ +typedef struct NVC637_CTRL_EXEC_PARTITIONS_INFO { + NvU32 gpcCount; + NvU32 gfxGpcCount; + NvU32 veidCount; + NvU32 ceCount; + NvU32 nvEncCount; + NvU32 nvDecCount; + NvU32 nvJpgCount; + NvU32 ofaCount; + NvU32 sharedEngFlag; + NvU32 veidStartOffset; + NvU32 smCount; + NvU32 spanStart; + NvU32 computeSize; + NvU32 execPartFlags; +} NVC637_CTRL_EXEC_PARTITIONS_INFO; + +#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG 31:0 +#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NONE 0x0 +#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_CE NVBIT(0) +#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVDEC NVBIT(1) +#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVENC NVBIT(2) +#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_OFA NVBIT(3) +#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVJPG NVBIT(4) + +#define NVC637_CTRL_EXEC_PARTITIONS_FLAGS 31:0 +// +// NVC637_CTRL_EXEC_PARTITIONS_FLAGS_OPTIMIZE +// If set, RM will try to select partition HW resources giving better performance for a +// specified usecase. +// OPTIMIZE_FOR_MGPU: +// optimize for an interface to communicate with other GPUs. This can give latency +// reduction benefit to applications using multi-GPU communication. +// OPTIMIZE_FOR_HOSTIF: +// optimal config for a better Host interface and memory access performance. +// +// The flag makes sense only on GPUs with multiple compute dielets because one of the +// dielets can be closer to MGPU communication interface (e.g. NVLINK). While HW compute +// work scheduler on any dielet is capable of driving a computation work, selecting the +// one closer to NVLINK will decrease latencies for NVLINK communications. +// Default behavior (if flag is not provided) is for RM to select dielet closer to host +// interface and memory, to reduce new work scheduling latency. +// On a single dielet GPUs this flag has no effect. +// Currently this flag is used by RM for Full compute instances only. +// +#define NVC637_CTRL_EXEC_PARTITIONS_FLAGS_OPTIMIZE 1:0 +#define NVC637_CTRL_EXEC_PARTITIONS_FLAGS_OPTIMIZE_FOR_HOSTIF (0x00000000) +#define NVC637_CTRL_EXEC_PARTITIONS_FLAGS_OPTIMIZE_FOR_MGPU (0x00000001) +#define NVC637_CTRL_EXEC_PARTITIONS_FLAGS_OPTIMIZE_DEFAULT NVC637_CTRL_EXEC_PARTITIONS_FLAGS_OPTIMIZE_FOR_HOSTIF + +#define NVC637_CTRL_MAX_EXEC_PARTITIONS 8 +#define NVC637_CTRL_EXEC_PARTITIONS_ID_INVALID 0xFFFFFFFF + +/*! + * NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS + * + * This command will create requested execution partitions under the subscribed + * memory partition. The memory partition is expected to be configured before + * execution partition creation. + * + * bQuery[IN] + * - If NV_TRUE, execution partitions will not be created, but return + * status of NV_OK will indicate that the request is valid and can + * currently be fulfilled + * flag [IN] + * REQUEST_WITH_PART_ID + * - If set, RM will try to assign execution partition id requested by clients. + * This flag is only supported on vGPU enabled RM build and will be removed + * when vgpu plugin implements virtualized execution partition ID support. + * (bug 2938187) + * + * REQUEST_AT_SPAN + * - If set, RM will try to assign execution partition resources at the specified span. + * This flag currently is only useful for chips in which CTS IDs are mandatory in RM, + * as it allows the requester to position compute instances without using RM best fit + * allocation. + * + * execPartCount[IN] + * - Number of execution partitions requested + * + * execPartInfo[IN] + * - Requested execution partition resources for each requested partition + * + * execPartId[OUT] + * - ID of each requested execution partition + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_WITH_PART_ID 0:0 +#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_WITH_PART_ID_FALSE (0x00000000) +#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_WITH_PART_ID_TRUE (0x00000001) +#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_AT_SPAN 1:1 +#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_AT_SPAN_FALSE (0x00000000) +#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_AT_SPAN_TRUE (0x00000001) + +#define NVC637_CTRL_CMD_EXEC_PARTITIONS_CREATE (0xc6370101) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_MESSAGE_ID" */ + +/*! + * NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS + * + * This command will delete requested execution partitions. + * + * execPartCount[IN] + * - Number of execution partitions to delete. + * + * execPartId[IN] + * - Execution partition IDs to delete + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS { + NvBool bQuery; + NvU32 flags; + NvU32 execPartCount; + // C form: NVC637_CTRL_EXEC_PARTITIONS_INFO execPartInfo[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + NVC637_CTRL_EXEC_PARTITIONS_INFO execPartInfo[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + // C form: NvU32 execPartId[NVC637_CTRL_MAX_EXECUTION_PARTITIONS]; + NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS]; +} NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS; +#define NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS { + NvU32 execPartCount; + NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS]; +} NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS; + +#define NVC637_CTRL_CMD_EXEC_PARTITIONS_DELETE (0xc6370102) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_MESSAGE_ID" */ + +/*! + * NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS + * + * This command will return information about execution partitions which + * currently exist within the subscribed memory partition. + * + * execPartCount[OUT] + * - Number of existing execution partitions + * + * execPartId[OUT] + * - ID of existing execution partitions + * + * execPartInfo[OUT] + * - Resources within each existing execution partition + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS { + NvU32 execPartCount; + // C form: NvU32 execPartId[NVC637_CTRL_MAX_EXECUTION_PARTITIONS]; + NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + // C form: NVC637_CTRL_EXEC_PARTITIONS_INFO execPartInfo[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + NVC637_CTRL_EXEC_PARTITIONS_INFO execPartInfo[NVC637_CTRL_MAX_EXEC_PARTITIONS]; +} NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS; + +#define NVC637_CTRL_CMD_EXEC_PARTITIONS_GET (0xc6370103) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_MESSAGE_ID" */ + +/*! + * NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS + * + * This command will return IDs of all active execution partitions in a memory + * partition + * + * execPartCount[OUT] + * - Number of existing execution partitions + * + * execPartId[OUT] + * - ID of existing execution partitions + * + * execPartUuid[OUT] + * - ASCII UUID string of existing execution partitions + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NVC637_UUID_LEN 16 +#define NVC637_UUID_STR_LEN NV_MIG_DEVICE_UUID_STR_LENGTH + +typedef struct NVC637_EXEC_PARTITION_UUID { + // C form: char str[NVC638_UUID_STR_LEN]; + char str[NVC637_UUID_STR_LEN]; +} NVC637_EXEC_PARTITION_UUID; + +#define NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS { + NvU32 execPartCount; + + // C form: NvU32 execPartId[NVC637_CTRL_MAX_EXECUTION_PARTITIONS]; + NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + + // C form: NVC637_EXEC_PARTITION_UUID execPartUuid[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + NVC637_EXEC_PARTITION_UUID execPartUuid[NVC637_CTRL_MAX_EXEC_PARTITIONS]; +} NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS; + +#define NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS (0xc6370104) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS_MESSAGE_ID" */ + +/* + * NVC637_CTRL_CMD_EXEC_PARTITIONS_EXPORT + * + * Export the resource and placement information about an exec partition such + * that a similar partition can be recreated from scratch in the same position. + */ +#define NVC637_CTRL_CMD_EXEC_PARTITIONS_EXPORT (0xc6370105) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | 0x5" */ + +/* + * NVC637_CTRL_CMD_EXEC_PARTITIONS_IMPORT + * + * Create an exec partition resembling the exported partition info. The imported + * partition should behave identically with respect to fragmentation. + */ +#define NVC637_CTRL_CMD_EXEC_PARTITIONS_IMPORT (0xc6370106) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | 0x6" */ + +#define NVC637_CTRL_EXEC_PARTITIONS_EXPORT_MAX_ENGINES_MASK_SIZE 4 +typedef struct NVC637_CTRL_EXEC_PARTITIONS_EXPORTED_INFO { + NV_DECLARE_ALIGNED(NvU64 enginesMask[NVC637_CTRL_EXEC_PARTITIONS_EXPORT_MAX_ENGINES_MASK_SIZE], 8); + NvU8 uuid[NVC637_UUID_LEN]; + NvU32 sharedEngFlags; + NvU32 gpcMask; + NvU32 gfxGpcCount; + NvU32 veidOffset; + NvU32 veidCount; + NvU32 smCount; + NvU32 spanStart; + NvU32 computeSize; + NvU32 execPartFlags; +} NVC637_CTRL_EXEC_PARTITIONS_EXPORTED_INFO; + +typedef struct NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS { + NvU32 id; + NV_DECLARE_ALIGNED(NVC637_CTRL_EXEC_PARTITIONS_EXPORTED_INFO info, 8); + NvBool bCreateCap; +} NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS; + +/* + * NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN + * + * This struct represents the span of a compute instance, which represents the + * resource slots a given partition occupies (or may occupy) within a fixed range which + * is defined per-chip. A partition containing more resources will cover more + * resource slots and therefore cover a larger span. + * + * lo + * - The starting unit of this span, inclusive + * + * hi + * - The ending unit of this span, inclusive + * + */ +typedef struct NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN { + NV_DECLARE_ALIGNED(NvU64 lo, 8); + NV_DECLARE_ALIGNED(NvU64 hi, 8); +} NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN; + +/* + * NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY + * + * This command returns the count of compute instances which can be created + * of the given commpute profile size (represented by the computeSize field + * within a profile) which can be requested via NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILES + * Note that this API does not "reserve" any partitions, and there is no + * guarantee that the reported count of available partitions of a given size + * will remain consistent following creation of partitions of different size + * through NV2080_CTRL_GPU_SET_PARTITIONS. + * Note that this API is unsupported if SMC is feature-disabled. + * Note that the caller of this CTRL must be subscribed to a valid GPU instance + * + * computeSize[IN] + * - Partition flag indicating size of requested profile + * + * profileCount[OUT] + * - Available number of profiles of the given size which can currently be created. + * + * availableSpans[OUT] + * - For each profile able to be created of the specified size, the span + * it could occupy. + * + * availableSpansCount[OUT] + * - Number of valid entries in availableSpans. + * + * totalProfileCount[OUT] + * - Total number of profiles of the given size which can be created. + * + * totalSpans[OUT] + * - List of spans which can possibly be occupied by profiles of the + * given type. + * + * totalSpansCount[OUT] + * - Number of valid entries in totalSpans. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NVC637_CTRL_CMD_EXEC_PARTITIONS_GET_PROFILE_CAPACITY (0xc63701a9U) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS_MESSAGE_ID" */ + +#define NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS_MESSAGE_ID (0xA9U) + +typedef struct NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS { + NvU32 computeSize; + NvU32 profileCount; + NV_DECLARE_ALIGNED(NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN availableSpans[NVC637_CTRL_MAX_EXEC_PARTITIONS], 8); + NvU32 availableSpansCount; + NvU32 totalProfileCount; + NV_DECLARE_ALIGNED(NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN totalSpans[NVC637_CTRL_MAX_EXEC_PARTITIONS], 8); + NvU32 totalSpansCount; +} NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS; + +/* + * NVC637_CTRL_CMD_GET_UUID + */ +#define NVC637_CTRL_CMD_GET_UUID (0xc63701aaU) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_GET_UUID_PARAMS_MESSAGE_ID" */ + +#define NVC637_CTRL_GET_UUID_PARAMS_MESSAGE_ID (0xAAU) + +typedef struct NVC637_CTRL_GET_UUID_PARAMS { + NvU8 uuid[NVC637_UUID_LEN]; + + char uuidStr[NVC637_UUID_STR_LEN]; +} NVC637_CTRL_GET_UUID_PARAMS; + +// _ctrlc637_h_ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlc638.h b/userspace/sdks/nv570/inc/ctrl/ctrlc638.h new file mode 100644 index 0000000..5e848a9 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlc638.h @@ -0,0 +1,91 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc638.finn +// + +#include "ctrl/ctrlxxxx.h" +/* AMPERE_SMC_EXEC_PARTITION_REF commands and parameters */ + +#define NVC638_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xC638, NVC638_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NVC638_CTRL_RESERVED (0x00) +#define NVC638_CTRL_EXEC_PARTITION (0x01) + +/*! + * NVC638_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVC638_CTRL_CMD_NULL (0xc6380000) /* finn: Evaluated from "(FINN_AMPERE_SMC_EXEC_PARTITION_REF_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/*! + * NVC638_CTRL_CMD_GET_UUID + * + * This command returns SHA1 ASCII UUID string as well as the binary UUID for + * the execution partition. The ASCII string format is, + * "MIG-%16x-%08x-%08x-%08x-%024x" (the canonical format of a UUID) + * + * uuid[OUT] + * - Raw UUID bytes + * + * uuidStr[OUT] + * - ASCII UUID string + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + */ + +#define NVC638_UUID_LEN 16 + +/* 'M' 'I' 'G' '-'(x5), '\0x0', extra = 9 */ +#define NVC638_UUID_STR_LEN (0x29) /* finn: Evaluated from "((NVC638_UUID_LEN << 1) + 9)" */ + + + +#define NVC638_CTRL_CMD_GET_UUID (0xc6380101) /* finn: Evaluated from "(FINN_AMPERE_SMC_EXEC_PARTITION_REF_EXEC_PARTITION_INTERFACE_ID << 8) | NVC638_CTRL_GET_UUID_PARAMS_MESSAGE_ID" */ + + + +#define NVC638_CTRL_GET_UUID_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC638_CTRL_GET_UUID_PARAMS { + // C form: NvU8 uuid[NVC638_UUID_LEN]; + NvU8 uuid[NVC638_UUID_LEN]; + + // C form: char uuidStr[NVC638_UUID_STR_LEN]; + char uuidStr[NVC638_UUID_STR_LEN]; +} NVC638_CTRL_GET_UUID_PARAMS;// _ctrlc638_h_ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlc763.h b/userspace/sdks/nv570/inc/ctrl/ctrlc763.h new file mode 100644 index 0000000..861935f --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlc763.h @@ -0,0 +1,242 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc763.finn +// + +#include "ctrl/ctrlxxxx.h" +/* Vidmem Access bit buffer control commands and parameters */ + +#define NVC763_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xC763, NVC763_CTRL_##cat, idx) + +/* MMU_VIDMEM_ACCESS_BIT_BUFFER command categories (6bits) */ +#define NVC763_CTRL_RESERVED (0x00) +#define NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER (0x01) + +/* + * SW def for number of range checkers. Current value taken from + * NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO__SIZE_1 + * on GA102. Compile time assert to check that the below + * definition is consistent with HW manuals is included in + * each gmmu HAL where this is relevant. + */ +#define NV_VIDMEM_ACCESS_BIT_BUFFER_NUM_CHECKERS 8 + +/* + * NVC763_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVC763_CTRL_CMD_NULL (0xc7630000) /* finn: Evaluated from "(FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +#define NVC763_CTRL_CMD_VIDMEM_ACCESS_BIT_ENABLE_LOGGING (0xc7630101) /* finn: Evaluated from "(FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER_INTERFACE_ID << 8) | NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_ENABLE_LOGGING_PARAMS_MESSAGE_ID" */ + +// Supported granularities for the vidmem access bit buffer logging +typedef enum NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY { + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_64KB = 0, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_128KB = 1, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_256KB = 2, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_512KB = 3, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_1MB = 4, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_2MB = 5, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_4MB = 6, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_8MB = 7, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_16MB = 8, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_32MB = 9, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_64MB = 10, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_128MB = 11, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_256MB = 12, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_512MB = 13, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_1GB = 14, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_2GB = 15, +} NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY; + +/** + * enum of disable mode to be used when the MMU enters protected mode + */ +typedef enum NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DISABLE_MODE { + /*! + * Disable mode will set all the access/dirty bits as '0' + */ + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DISABLE_MODE_CLEAR = 0, + /*! + * Disable mode will set all the access/dirty bits as '1' + */ + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DISABLE_MODE_SET = 1, +} NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DISABLE_MODE; + + +// +// If clients want to enable logging specifically for some MMU, clients need to +// do it in a loop +// +typedef enum NV_VIDMEM_ACCESS_BIT_BUFFER_MMU_TYPE { + /*! + * Read/Write Attrs only for HUBMMU registers + */ + NV_VIDMEM_ACCESS_BIT_BUFFER_HUBMMU = 0, + /*! + * Read/Write Attrs only for GPCMMU registers + */ + NV_VIDMEM_ACCESS_BIT_BUFFER_GPCMMU = 1, + /*! + * Read/Write Attrs only for HSHUBMMU registers + */ + NV_VIDMEM_ACCESS_BIT_BUFFER_HSHUBMMU = 2, + /*! + * Default will enable for all MMU possible + */ + NV_VIDMEM_ACCESS_BIT_BUFFER_DEFAULT = 3, +} NV_VIDMEM_ACCESS_BIT_BUFFER_MMU_TYPE; + +typedef enum NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_TRACK_MODE { + /*! + Mode to track access bits + */ + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_TRACK_MODE_ACCESS = 0, + /*! + Mode to track dirty bits + */ + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_TRACK_MODE_DIRTY = 1, +} NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_TRACK_MODE; + +/* + * NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_ENABLE_LOGGING_PARAMS + * + * This structure is used to enable logging of the VAB and specifies + * the requested configuration for the 8 independent range checkers. + * The tracking mode and disable mode are the same for all range checkers. + */ +#define NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_ENABLE_LOGGING_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_ENABLE_LOGGING_PARAMS { + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY granularity[NV_VIDMEM_ACCESS_BIT_BUFFER_NUM_CHECKERS]; + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_TRACK_MODE trackMode; + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DISABLE_MODE disableMode; + NV_DECLARE_ALIGNED(NvU64 startAddress[NV_VIDMEM_ACCESS_BIT_BUFFER_NUM_CHECKERS], 8); + NvU8 rangeCount; + NV_VIDMEM_ACCESS_BIT_BUFFER_MMU_TYPE mmuType; +} NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_ENABLE_LOGGING_PARAMS; + + +#define NVC763_CTRL_CMD_VIDMEM_ACCESS_BIT_DISABLE_LOGGING (0xc7630102) /* finn: Evaluated from "(FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER_INTERFACE_ID << 8) | 0x2" */ + +/* + * NVC763_CTRL_CMD_VIDMEM_ACCESS_BIT_BUFFER_DUMP + * + * This call initiates the dump request with the properties set using enable + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVC763_CTRL_CMD_VIDMEM_ACCESS_BIT_DUMP (0xc7630103) /* finn: Evaluated from "(FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER_INTERFACE_ID << 8) | NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS_MESSAGE_ID" */ + +/* + * NV_VAB_OP enumerates the types of dumps supported + * + * The options are: + * + * AGGREGATE + * Collects access buffer bits over multiple dumps using a bitwise OR. + * + * DIFF + * Sets a bit to 1 if it changed from 0 to 1 with this dump. If a bit was + * cleared since the last dump it will be 0. If a bit does not change + * with this dump it will be 0. + * + * CURRENT + * Copies the current access bit buffer state as is from HW. This operation + * clears any underlying aggregation from previous dumps with the other + * two operations. + * + * INVALID + * Should be unused and otherwise indicates error + */ +typedef enum NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP { + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP_AGGREGATE = 0, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP_DIFF = 1, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP_CURRENT = 2, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP_INVALID = 3, +} NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP; + +/* + * NVC763_CTRL_VIDMEM_ACCESS_BIT_DUMP_PARAMS + * + * This structure records the dumped bits for the client + * masked by the client's access bit mask determined + * during VidmemAccessBitBuffer construction. + * + * bMetadata [IN] + * Whether or not clients want disable data. + * + * op_enum [IN] + * A member of NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP controlling the type of dump. + * + * accessBits [OUT] + * The client's access bits masked according to the client's access bit mask. + * + * gpcDisable [OUT] + * The GPC disable data from the VAB dump. See GPC_DISABLE in the Ampere-801 FD. + * + * hubDisable [OUT] + * The HUB disable data from the VAB dump. See HUB_DISABLE in the Ampere-801 FD. + * + * hsceDisable [OUT] + * The HSCE disable data from the VAB dump. See HSCE_DIS in the Ampere-801 FD. + * + * linkDisable [OUT] + * The LINK disable data from the VAB dump. See LINK_DIS in the Ampere-801 FD. + */ +#define NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS { + NvBool bMetadata; + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP op_enum; + NV_DECLARE_ALIGNED(NvU64 accessBits[64], 8); + NV_DECLARE_ALIGNED(NvU64 gpcDisable, 8); + NvU32 hubDisable; + NvU16 hsceDisable; + NvU8 linkDisable; +} NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS; + + +#define NVC763_CTRL_CMD_VIDMEM_ACCESS_BIT_PUT_OFFSET (0xc7630104) /* finn: Evaluated from "(FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER_INTERFACE_ID << 8) | NVC763_CTRL_VIDMEM_ACCESS_BIT_PUT_OFFSET_PARAMS_MESSAGE_ID" */ + +#define NVC763_CTRL_VIDMEM_ACCESS_BIT_PUT_OFFSET_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVC763_CTRL_VIDMEM_ACCESS_BIT_PUT_OFFSET_PARAMS { + NvU32 vidmemAccessBitPutOffset; +} NVC763_CTRL_VIDMEM_ACCESS_BIT_PUT_OFFSET_PARAMS; +/* _ctrlc763_h_ */ diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlcb33.h b/userspace/sdks/nv570/inc/ctrl/ctrlcb33.h new file mode 100644 index 0000000..326a675 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlcb33.h @@ -0,0 +1,425 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlcb33.finn +// + + + +#include "nvcfg_sdk.h" +#include "ctrl/ctrlxxxx.h" +/* NV_CONF_COMPUTE control commands and parameters */ + +#define NV_CONF_COMPUTE_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xCB33, NVCB33_CTRL_##cat, idx) + +#define NVCB33_CTRL_RESERVED (0x00) +#define NVCB33_CTRL_CONF_COMPUTE (0x01) + +/* + * NV_CONF_COMPUTE_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible return values: + * NV_OK + */ +#define NV_CONF_COMPUTE_CTRL_CMD_NULL (0xcb330000) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES + * This control call returns overall system and gpu capabilities + * + * Final operating environment depends on a lot of factors: + * APM: Ampere Protected Memory + * HCC: Hopper Confidential Compute + * --------------------------------------------------------------------------- + * SrNo CPU TEE GPU TEE GPU Platform GPU mode SW Status System Env + * --------------------------------------------------------------------------- + * 1 AMD SEV APM/HCC Silicon Production Production Production + * 2 AMD SEV APM/HCC Silicon Production Development Simulation + * 3 APM/HCC Debug Simulation + * 4 Non SEV APM/HCC Simulation + * 5 APM/HCC FMOD/EMU/RTL Simulation + * --------------------------------------------------------------------------- + * + * Prameters: + * cpuCapability: [OUT] + * This indicates if cpu is capable of AMD SEV + * gpusCapability: [OUT] + * This indicates if all gpus in the system support APM/HCC. + * This field doesn't mean APM/HCC is enabled. + * environment: [OUT] + * System environment can be production or simulation + * ccFeature: [OUT] + * Specifies if all gpus in the system have APM/HCC feature enabled + * CC feature can be enabled/disabled using this control call: + * NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_CC_FEATURE + * devToolsMode: [OUT] + * Dev tools mode is used for debugging/profiling + * Dev tools mode is set at system level and implies that all GPUs in + * the system have this mode enabled/disabled + * multiGpuMode: [OUT] + * Specifies the mode in which a multi gpu system is operating + * + * cpuCapability, gpusCapability & environment are determined by the + * driver and cannot be modified later on + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES (0xcb330101) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x1" */ + +#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_NONE 0 +#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV 1 +#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_INTEL_TDX 2 +#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV_SNP 3 +#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SNP_VTOM 4 + +#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_NONE 0 +#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_APM 1 +#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_HCC 2 + +#define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_UNAVAILABLE 0 +#define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_SIM 1 +#define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_PROD 2 + +#define NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED 0 +#define NV_CONF_COMPUTE_SYSTEM_FEATURE_APM_ENABLED 1 +#define NV_CONF_COMPUTE_SYSTEM_FEATURE_HCC_ENABLED 2 + +#define NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_DISABLED 0 +#define NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_ENABLED 1 + +#define NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_NONE 0 +#define NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_PROTECTED_PCIE 1 +#define NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_NVLE 2 + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS { + NvU8 cpuCapability; + NvU8 gpusCapability; + NvU8 environment; + NvU8 ccFeature; + NvU8 devToolsMode; + NvU8 multiGpuMode; +} NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE + * This control call can be used to determine if all GPUs are ready to accept + * work form clients. + * + * bAcceptClientRequest: [OUT] + * NV_TRUE: all gpus accepting client work requests + * NV_FALSE: all gpus blocking client work requests + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE (0xcb330104) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x4" */ + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS { + NvBool bAcceptClientRequest; +} NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE + * This control call can be used to set gpu state to accept client requests + * or to block client requests + * This is a PRIVILEGED control call and can be set via admin tools + * + * bAcceptClientRequest:[IN] + * NV_TRUE: set all gpus state to accept client work requests + * NV_FALSE: set all gpus state to block client work requests + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +#define NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE (0xcb330105) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x5" */ + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS { + NvBool bAcceptClientRequest; +} NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE + * This control call returns protected and unprotected vidmem size + * + * hSubDevice: [IN] + * subdevice handle for the gpu whose vidmem size is requested + * protectedMemSizeInKb: [OUT] + * total protected memory size in kB + * unprotectedMemSizeInKb: [OUT] + * total unprotected memory size in kB + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE (0xcb330106) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x6" */ + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS { + NvHandle hSubDevice; + NV_DECLARE_ALIGNED(NvU64 protectedMemSizeInKb, 8); + NV_DECLARE_ALIGNED(NvU64 unprotectedMemSizeInKb, 8); +} NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE + * This control call updates protected and unprotected vidmem size. + * All memory is protected if APM/HCC is enabled. User can override + * unprotectedMemSizeInKb and that will adjust protectedMemSizeInKb accordingly. + * This is a PRIVILEGED control call and can be set via tools like nvidia-smi. + * Vidmem size can be updated after driver load and before any client FB + * allocations are made. + * + * hSubDevice: [IN] + * subdevice handle for the gpu whose vidmem size is requested + * protectedMemSizeInKb: [OUT] + * total protected memory size in kB + * unprotectedMemSizeInKb: [IN/OUT] + * total unprotected memory size in kB + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +#define NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE (0xcb330107) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x7" */ + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS { + NvHandle hSubDevice; + NV_DECLARE_ALIGNED(NvU64 protectedMemSizeInKb, 8); + NV_DECLARE_ALIGNED(NvU64 unprotectedMemSizeInKb, 8); +} NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS + * This control call returns the max number of AES capable channels SEC2 and CE support. + * + * hSubDevice: [IN] + * subdevice handle for the GPU queried + * numSupportedSec2CCSecureChannels: [OUT] + * Max number of AES capable channels SEC2 supports + * numSupportedCeCCSecureChannels: [OUT] + * Max number of channels CE supports with encrypt/decrypt + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS (0xcb330108) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x8" */ + +#define NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS { + NvHandle hSubDevice; + NvU32 numSupportedSec2CCSecureChannels; + NvU32 numSupportedCeCCSecureChannels; +} NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE + * This control call returns the GPU session certificate for the specified GPU. + * The certificate size is the maximum of the certificate size of APM and CC. + * + * hSubDevice: [IN] + * Subdevice handle for the GPU queried + * certChain: [OUT] + * Certificate chain for the GPU queried + * certChainSize: [OUT] + * Actual size of certChain data + * attestationCertChain: [OUT] + * Attestation certificate chain for the GPU queried + * attestationCertChainSize: [OUT] + * Actual size of attestationCertChain data + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE (0xcb330109) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x9" */ + +#define NV_CONF_COMPUTE_CERT_CHAIN_MAX_SIZE 0x1000 +#define NV_CONF_COMPUTE_ATTESTATION_CERT_CHAIN_MAX_SIZE 0x1400 + +#define NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS { + NvHandle hSubDevice; + NvU8 certChain[NV_CONF_COMPUTE_CERT_CHAIN_MAX_SIZE]; + NvU32 certChainSize; + NvU8 attestationCertChain[NV_CONF_COMPUTE_ATTESTATION_CERT_CHAIN_MAX_SIZE]; + NvU32 attestationCertChainSize; +} NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS; + + /* + * NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION + * This control call returns the GPU attestation report for the specified GPU. + * The attestation report size is the maximum of the attestation report size of APM and CC. + * + * hSubDevice: [IN] + * Subdevice handle for the GPU queried + * nonce: [IN] + * spdm supports 32 bytes on nonce + * attestationReport: [OUT] + * Attestation report of the GPU queried + * attestationReportSize: [OUT] + * Actual size of the report + * isCecAttestationReportPresent : [OUT] + * Indicates if the next 2 feilds are valid + * cecAttestationReport: [OUT] + * Cec attestation report for the gpu queried + * cecAttestationReportSize: [OUT] + * Actual size of the cec attestation report + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT (0xcb33010a) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0xA" */ + +#define NV_CONF_COMPUTE_GPU_ATTESTATION_REPORT_MAX_SIZE 0x2000 +#define NV_CONF_COMPUTE_GPU_CEC_ATTESTATION_REPORT_MAX_SIZE 0x1000 +#define NV_CONF_COMPUTE_NONCE_SIZE 0x20 + +#define NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS { + NvHandle hSubDevice; + NvU8 nonce[NV_CONF_COMPUTE_NONCE_SIZE]; + NvU8 attestationReport[NV_CONF_COMPUTE_GPU_ATTESTATION_REPORT_MAX_SIZE]; + NvU32 attestationReportSize; + NvBool isCecAttestationReportPresent; + NvU8 cecAttestationReport[NV_CONF_COMPUTE_GPU_CEC_ATTESTATION_REPORT_MAX_SIZE]; + NvU32 cecAttestationReportSize; +} NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS + * This control call returns the max number of Conf Compute capable channels SEC2 and CE support. + * + * hSubDevice: [IN] + * subdevice handle for the GPU queried + * maxSec2Channels: [OUT] + * Max number of conf compute capable channels SEC2 supports + * maxCeChannels: [OUT] + * Max number of channels CE supports with encrypt/decrypt + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS (0xcb33010b) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0xB" */ + +#define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS { + NvHandle hSubDevice; + NvU32 maxSec2Channels; + NvU32 maxCeChannels; +} NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE + * This control call returns if key rotation is enabled. + * + * hSubDevice: [IN] + * subdevice handle for the GPU queried + * keyRotationState: [OUT] + * NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_* value + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE (0xcb33010c) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0xC" */ + +#define NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_DISABLED 0 // key rotation is disabled +#define NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_KERN_ENABLED 1 // key rotation enabled for kernel keys +#define NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_USER_ENABLED 2 // key rotation enabled for user keys +#define NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_BOTH_ENABLED 3 // key rotation enabled for both keys + +#define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS { + NvHandle hSubDevice; + NvU32 keyRotationState; +} NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS; + +/* _ctrlcb33_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlcbca.h b/userspace/sdks/nv570/inc/ctrl/ctrlcbca.h new file mode 100644 index 0000000..a034f92 --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlcbca.h @@ -0,0 +1,120 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlcbca.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV_COUNTER_COLLECTION_UNIT control commands and parameters */ + +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xCBCA, NVCBCA_CTRL_##cat, idx) + +#define NVCBCA_CTRL_RESERVED (0x00) +#define NVCBCA_CTRL_COUNTER_COLLECTION_UNIT (0x01) + +/* + * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible return values: + * NV_OK + */ +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_NULL (0xcbca0000) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_SUBSCRIBE + * + * This command is used to subscribe performance counter data + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_SUBSCRIBE (0xcbca0101) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID << 8) | NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS_MESSAGE_ID" */ + +#define NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 bufferSize, 8); + NvU32 counterBlockSize; +} NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS; + +/* + * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_UNSUBSCRIBE + * + * This command is used to unsubscribe performance counter data + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_UNSUBSCRIBE (0xcbca0102) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID << 8) | 0x2" */ + +/* + * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_SET_STREAM_STATE + * + * This command is used to set the counter collection unit stream state + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_SET_STREAM_STATE (0xcbca0103) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID << 8) | NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS_MESSAGE_ID" */ + +#define NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS { + NvBool bStreamState; +} NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS; + +/* + * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_GET_STREAM_STATE + * + * This command is used to get the counter collection unit stream state + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_GET_STREAM_STATE (0xcbca0104) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID << 8) | 0x4" */ + +/* _ctrlcbca_h_ */ + diff --git a/userspace/sdks/nv570/inc/ctrl/ctrlxxxx.h b/userspace/sdks/nv570/inc/ctrl/ctrlxxxx.h new file mode 100644 index 0000000..c51ea2b --- /dev/null +++ b/userspace/sdks/nv570/inc/ctrl/ctrlxxxx.h @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlxxxx.finn +// + + + +#include "nvtypes.h" + +/* definitions shared by all CTRL interfaces */ + +/* Basic command format: +* cmd_class [31:16], +* cmd_reserved [15:15], +* cmd_reserved [14:14], +* cmd_category [13:8], +* cmd_index [7:0] +*/ + +#define NVXXXX_CTRL_CMD_CLASS 31:16 + +#define NVXXXX_CTRL_CMD_CATEGORY 13:8 +#define NVXXXX_CTRL_CMD_INDEX 7:0 + +/* don't use DRF_NUM - not always available */ +# define NVXXXX_CTRL_CMD(cls,cat,idx) \ + (((cls) << 16) | ((0) << 15) | ((0) << 14) \ + | ((cat) << 8) | ((idx) & 0xFF)) +/* + * NVXXXX_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * This command is valid for all classes. + * + * Possible status values returned are: + * NV_OK + */ +#define NVXXXX_CTRL_CMD_NULL (0x00000000) + +#define NVxxxx_CTRL_LEGACY_PRIVILEGED (0xC0) +#define NVxxxx_CTRL_LEGACY_NON_PRIVILEGED (0x80) + +typedef struct NVXXXX_CTRL_XXX_INFO { + NvU32 index; + NvU32 data; +} NVXXXX_CTRL_XXX_INFO; diff --git a/userspace/sdks/nv570/inc/dpringbuffertypes.h b/userspace/sdks/nv570/inc/dpringbuffertypes.h new file mode 100644 index 0000000..b61abaf --- /dev/null +++ b/userspace/sdks/nv570/inc/dpringbuffertypes.h @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2002-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef INCLUDED_DPRINGBUFFERTYPES_H +#define INCLUDED_DPRINGBUFFERTYPES_H + +#define MAX_MESSAGE_LEN 100 +#define MAX_RECORD_COUNT 15 + +typedef enum _DP_RECORD_TYPE +{ + ASSERT_HIT = 135, + LOG_CALL = 136, +} DP_RECORD_TYPE; + +typedef struct _DpAssertHitRecord +{ + NvU64 breakpointAddr; +} DpAssertHitRecord, *PDpAssertHitRecord; + +typedef struct _DpLogCallRecord +{ + char msg[MAX_MESSAGE_LEN]; + NvU64 addr; +} DpLogCallRecord, *PDpLogCallRecord; + +typedef union _DpLogRecord +{ + DpAssertHitRecord dpAssertHitRecord; + DpLogCallRecord dpLogCallRecord; +} DpLogRecord, *PDpLogRecord; + +typedef enum _DpLogQueryType +{ + DpLogQueryTypeAssert = 1, + DpLogQueryTypeCallLog = 2, +} DpLogQueryType, *PDpLogQueryType; + +#endif //INCLUDED_DPRINGBUFFERTYPES_H diff --git a/userspace/sdks/nv570/inc/g_finn_rm_api.h b/userspace/sdks/nv570/inc/g_finn_rm_api.h new file mode 100644 index 0000000..1f149ba --- /dev/null +++ b/userspace/sdks/nv570/inc/g_finn_rm_api.h @@ -0,0 +1,728 @@ +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// + + +#include + + +#include +#include + +#define FINN_INTERFACE_ID(T) (T ## _INTERFACE_ID) +#define FINN_MESSAGE_ID(T) (T ## _MESSAGE_ID) + +#if !defined(_MSC_VER) && (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L) && !defined(__arm) +#define FINN_PACK_COMPOSITE(b) b __attribute__ ((packed)) +#else +#define FINN_PACK_COMPOSITE(b) b +#endif + +/* + * FINN serialization version. A version mismatch indicates incompatibility + * between the serializer and the deserializer. + * + * WARNING: Current serialization version is 0. This is a pre-release version of + * serialization and is only intended to be used in a driver and client compiled + * together. DO NOT use this in firmware or versioned clients. + */ +#define FINN_SERIALIZATION_VERSION 0 + +/* + * FINN compiler version + */ +#define FINN_VERSION_MAJOR 1 +#define FINN_VERSION_MINOR 25 +#define FINN_VERSION_PATCH 0 + +typedef struct FINN_RM_API +{ + NV_DECLARE_ALIGNED(NvU64 version, 8); + NV_DECLARE_ALIGNED(NvU64 payloadSize, 8); + NV_DECLARE_ALIGNED(NvU64 interface, 8); + NV_DECLARE_ALIGNED(NvU64 message, 8); +} FINN_RM_API; + + + + +/*! + * @brief Private functions not to be called directly + */ +/**@{*/ +NV_STATUS finnSerializeInternal_FINN_RM_API(NvU64 interface, NvU64 message, const char *api, char *dst, NvLength dst_size, NvBool seri_up); +NV_STATUS finnDeserializeInternal_FINN_RM_API(const char *src, NvLength src_size, char *api, NvLength api_size, NvBool deser_up); +/**@}*/ + + +/*! + * @brief Serializes an RM API control params struct and copies it into the + * serialization buffer as a FINN message. + * + * @note FinnRmApiSerializeDown is for serializing down the call stack. + * + * FinnRmApiSerializeUp is for serializing up the call stack. It + * frees memory allocated by FinnRmApiDeserializeDown. Use only + * when handling RM API control requests. + * + * @warning One of these may be unimplemented depending on platform. If both + * are implemented, misuse causes memory corruption and memory leaks. + * + * @param[in] interface FINN interface ID of the param struct. + * @param[in] message FINN message ID of the param struct. + * @param[in] api Source param struct from which to copy the data. + * @param[in] dst Destination buffer into which to copy the data. + * @param[in] dst_size Maximum size of the destination buffer measured in + * `NvU8` units. + * + * @retval NV_OK Serialization successful. + * @retval NV_ERR_INVALID_ARGUMENT Bad function arguments, invalid union + * selector, or invalid enum value. + * @retval NV_ERR_NOT_SUPPORTED Unserializable or nonexistent ID. + * @retval NV_ERR_NOT_COMPATIBLE Container count too large. + * @retval NV_ERR_OUT_OF_RANGE Ranged field exceeded bounds. + * @retval NV_ERR_BUFFER_TOO_SMALL Destination buffer size too small. + */ +/**@{*/ +static NV_INLINE NV_STATUS FinnRmApiSerializeUp(NvU64 interface, NvU64 message, const void *api, NvU8 *dst, NvLength dst_size) +{ + return finnSerializeInternal_FINN_RM_API(interface, message, (const char *) api, (char *) dst, dst_size, NV_TRUE); +} +static NV_INLINE NV_STATUS FinnRmApiSerializeDown(NvU64 interface, NvU64 message, const void *api, NvU8 *dst, NvLength dst_size) +{ + return finnSerializeInternal_FINN_RM_API(interface, message, (const char *) api, (char *) dst, dst_size, NV_FALSE); +} +/**@}*/ + + +/*! + * @brief The following APIs deserialize a FINN message from the serialization + * buffer and copy it into an RM API control params struct. + * + * @note FinnRmApiDeserializeDown is for deserializing down the call stack. It + * allocates deep buffers for primitive pointers in the serialization + * buffer, assuming that it remains in memory. Use only when handling + * RM API control requests. + * + * FinnRmApiDeserializeUp is for deserializing up the call stack. It + * copies deep buffers of primitive pointers into the params struct, + * assuming that memory is already allocated for them. Use only when + * receiving RM API control results. + * + * @warning One of these may be unimplemented depending on platform. If both + * are implemented, misuse causes memory corruption and memory leaks. + * + * @param[in] src Source buffer from which to copy the data. + * @param[in] src_size Maximum size of the source buffer measured in + * `NvU8` units. + * @param[in, out] api Destination param struct into which to copy the data. + * @param[in] api_size Size of the destination param struct measured in + * `char` units per `sizeof` operator. + * + * @retval NV_OK Deserialization successful. + * @retval NV_ERR_INVALID_ARGUMENT Bad function arguments, invalid union + * selector, invalid enum value, or + * mismatch between expected and actual + * serialized size. + * @retval NV_ERR_NOT_SUPPORTED Unserializable or nonexistent ID. + * @retval NV_ERR_OUT_OF_RANGE Ranged field exceeded bounds. + * @retval NV_ERR_BUFFER_TOO_SMALL Source/destination buffer too small. + * @retval NV_ERR_LIB_RM_VERSION_MISMATCH Version mismatch. + */ +/**@{*/ +static NV_INLINE NV_STATUS FinnRmApiDeserializeDown(NvU8 *src, NvLength src_size, void *api, NvLength api_size) +{ + return finnDeserializeInternal_FINN_RM_API((const char *) src, src_size / sizeof(NvU8), (char *) api, api_size, NV_FALSE); +} +static NV_INLINE NV_STATUS FinnRmApiDeserializeUp(NvU8 *src, NvLength src_size, void *api, NvLength api_size) +{ + return finnDeserializeInternal_FINN_RM_API((const char *) src, src_size / sizeof(NvU8), (char *) api, api_size, NV_TRUE); +} +/**@}*/ + + +/*! + * @brief Calculates the serialized size of an RM API param struct. + * + * @param[in] interface FINN interface ID of the param struct. + * @param[in] message FINN message ID of the param struct. + * @param[in] src Pointer to the param struct. + * + * @retval Non-zero serialized size of param struct on success. + * @retval 0 if the API is unsupported by serialization or src is NULL. + */ +NvU64 FinnRmApiGetSerializedSize(NvU64 interface, NvU64 message, const NvP64 src); + + +/*! + * @brief Fetches the unserialized size of an API param struct. + * + * @note The size is measured in `char` units like the `sizeof` operator. + * + * @param[in] interface FINN interface ID of the param struct. + * @param[in] message FINN message ID of the param struct. + * + * @retval Non-zero sizeof param struct on success. + * @retval 0 if the API is unsupported by serialization. + */ +NvU64 FinnRmApiGetUnserializedSize(NvU64 interface, NvU64 message); + + +#define NV_RM_ALLOC_INTERFACE_INTERFACE_ID (0xA000U) +typedef FINN_RM_API NV_RM_ALLOC_INTERFACE; +#define FINN_NV01_ROOT_RESERVED_INTERFACE_ID (0x0U) +typedef FINN_RM_API FINN_NV01_ROOT_RESERVED; +#define FINN_NV01_ROOT_CLIENT_INTERFACE_ID (0xdU) +typedef FINN_RM_API FINN_NV01_ROOT_CLIENT; +#define FINN_NV01_ROOT_DIAG_INTERFACE_ID (0x4U) +typedef FINN_RM_API FINN_NV01_ROOT_DIAG; +#define FINN_NV01_ROOT_EVENT_INTERFACE_ID (0x5U) +typedef FINN_RM_API FINN_NV01_ROOT_EVENT; +#define FINN_NV01_ROOT_GPU_INTERFACE_ID (0x2U) +typedef FINN_RM_API FINN_NV01_ROOT_GPU; +#define FINN_NV01_ROOT_GPUACCT_INTERFACE_ID (0xbU) +typedef FINN_RM_API FINN_NV01_ROOT_GPUACCT; +#define FINN_NV01_ROOT_GSYNC_INTERFACE_ID (0x3U) +typedef FINN_RM_API FINN_NV01_ROOT_GSYNC; +#define FINN_NV01_ROOT_NVD_INTERFACE_ID (0x6U) +typedef FINN_RM_API FINN_NV01_ROOT_NVD; +#define FINN_NV01_ROOT_PROC_INTERFACE_ID (0x9U) +typedef FINN_RM_API FINN_NV01_ROOT_PROC; + +#define FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID (0xaU) +typedef FINN_RM_API FINN_NV01_ROOT_SYNC_GPU_BOOST; +#define FINN_NV01_ROOT_SYSTEM_INTERFACE_ID (0x1U) +typedef FINN_RM_API FINN_NV01_ROOT_SYSTEM; +#define FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID (0x3dU) +typedef FINN_RM_API FINN_NV01_ROOT_OS_UNIX; +#define FINN_NV01_ROOT_VGPU_INTERFACE_ID (0xcU) +typedef FINN_RM_API FINN_NV01_ROOT_VGPU; +#define FINN_NV01_ROOT_OS_WINDOWS_INTERFACE_ID (0x3fU) +typedef FINN_RM_API FINN_NV01_ROOT_OS_WINDOWS; +#define FINN_NV01_CONTEXT_DMA_RESERVED_INTERFACE_ID (0x200U) +typedef FINN_RM_API FINN_NV01_CONTEXT_DMA_RESERVED; +#define FINN_NV01_CONTEXT_DMA_DMA_INTERFACE_ID (0x201U) +typedef FINN_RM_API FINN_NV01_CONTEXT_DMA_DMA; +#define FINN_NV01_TIMER_RESERVED_INTERFACE_ID (0x400U) +typedef FINN_RM_API FINN_NV01_TIMER_RESERVED; +#define FINN_NV01_TIMER_TMR_INTERFACE_ID (0x401U) +typedef FINN_RM_API FINN_NV01_TIMER_TMR; +#define FINN_FABRIC_MANAGER_SESSION_RESERVED_INTERFACE_ID (0xf00U) +typedef FINN_RM_API FINN_FABRIC_MANAGER_SESSION_RESERVED; +#define FINN_FABRIC_MANAGER_SESSION_FM_INTERFACE_ID (0xf01U) +typedef FINN_RM_API FINN_FABRIC_MANAGER_SESSION_FM; +#define FINN_NV0020_GPU_MANAGEMENT_RESERVED_INTERFACE_ID (0x2000U) +typedef FINN_RM_API FINN_NV0020_GPU_MANAGEMENT_RESERVED; +#define FINN_NV0020_GPU_MANAGEMENT_GPU_MGMT_INTERFACE_ID (0x2001U) +typedef FINN_RM_API FINN_NV0020_GPU_MANAGEMENT_GPU_MGMT; +#define FINN_NV01_MEMORY_SYSTEM_RESERVED_INTERFACE_ID (0x3e00U) +typedef FINN_RM_API FINN_NV01_MEMORY_SYSTEM_RESERVED; +#define FINN_NV01_MEMORY_SYSTEM_MEMORY_INTERFACE_ID (0x3e01U) +typedef FINN_RM_API FINN_NV01_MEMORY_SYSTEM_MEMORY; +#define FINN_NV01_ROOT_USER_RESERVED_INTERFACE_ID (0x4100U) +typedef FINN_RM_API FINN_NV01_ROOT_USER_RESERVED; +#define FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID (0x4101U) +typedef FINN_RM_API FINN_NV01_ROOT_USER_MEMORY; +#define FINN_NV_CE_UTILS_RESERVED_INTERFACE_ID (0x0050U) +typedef FINN_RM_API FINN_NV_CE_UTILS_RESERVED; +#define FINN_NV_CE_UTILS_UTILS_INTERFACE_ID (0x5001U) +typedef FINN_RM_API FINN_NV_CE_UTILS_UTILS; +#define FINN_NV04_DISPLAY_COMMON_RESERVED_INTERFACE_ID (0x7300U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_RESERVED; +#define FINN_NV04_DISPLAY_COMMON_COMMON_INTERFACE_ID (0x7305U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_COMMON; +#define FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID (0x7311U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_DFP; +#define FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID (0x7313U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_DP; + +#define FINN_NV04_DISPLAY_COMMON_EVENT_INTERFACE_ID (0x7303U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_EVENT; +#define FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID (0x7304U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_INTERNAL; +#define FINN_NV04_DISPLAY_COMMON_PSR_INTERFACE_ID (0x7316U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_PSR; +#define FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID (0x7302U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_SPECIFIC; +#define FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID (0x7317U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_STEREO; + +#define FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID (0x7301U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_SYSTEM; +#define FINN_NV01_FRAMEBUFFER_CONSOLE_INTERFACE_ID (0x007601U) +typedef FINN_RM_API FINN_NV01_FRAMEBUFFER_CONSOLE; +#define FINN_NV01_DEVICE_0_RESERVED_INTERFACE_ID (0x8000U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_RESERVED; +#define FINN_NV01_DEVICE_0_BIF_INTERFACE_ID (0x8001U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_BIF; + +#define FINN_NV01_DEVICE_0_DMA_INTERFACE_ID (0x8018U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_DMA; +#define FINN_NV01_DEVICE_0_FB_INTERFACE_ID (0x8013U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_FB; +#define FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID (0x8017U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_FIFO; +#define FINN_NV01_DEVICE_0_GPU_INTERFACE_ID (0x8002U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_GPU; +#define FINN_NV01_DEVICE_0_GR_INTERFACE_ID (0x8011U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_GR; +#define FINN_NV01_DEVICE_0_HOST_INTERFACE_ID (0x8014U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_HOST; +#define FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID (0x8020U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_INTERNAL; +#define FINN_NV01_DEVICE_0_NVDEC_INTERFACE_ID (0x801cU) +typedef FINN_RM_API FINN_NV01_DEVICE_0_NVDEC; +#define FINN_NV01_DEVICE_0_NVENC_INTERFACE_ID (0x801bU) +typedef FINN_RM_API FINN_NV01_DEVICE_0_NVENC; +#define FINN_NV01_DEVICE_0_NVJPG_INTERFACE_ID (0x801fU) +typedef FINN_RM_API FINN_NV01_DEVICE_0_NVJPG; +#define FINN_NV01_DEVICE_0_PERF_INTERFACE_ID (0x8019U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_PERF; + +#define FINN_NV01_DEVICE_0_OS_UNIX_INTERFACE_ID (0x801eU) +typedef FINN_RM_API FINN_NV01_DEVICE_0_OS_UNIX; + +#define FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID (0x9001U) +typedef FINN_RM_API FINN_NV0090_KERNEL_GRAPHICS_CONTEXT; +#define FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID (0x00da00U) +typedef FINN_RM_API FINN_NV_SEMAPHORE_SURFACE; +#define FINN_RM_USER_SHARED_DATA_INTERFACE_ID (0xde00U) +typedef FINN_RM_API FINN_RM_USER_SHARED_DATA; +#define FINN_NV_MEMORY_EXPORT_RESERVED_INTERFACE_ID (0xE000U) +typedef FINN_RM_API FINN_NV_MEMORY_EXPORT_RESERVED; +#define FINN_NV_MEMORY_EXPORT_INTERFACE_ID (0xE001U) +typedef FINN_RM_API FINN_NV_MEMORY_EXPORT; +#define FINN_IMEX_SESSION_INTERFACE_ID (0xf100U) +typedef FINN_RM_API FINN_IMEX_SESSION; +#define FINN_NV_MEMORY_FABRIC_RESERVED_INTERFACE_ID (0xf800U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_RESERVED; +#define FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID (0xf801U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_FABRIC; +#define FINN_NV_MEMORY_FABRIC_IMPORT_V2_RESERVED_INTERFACE_ID (0xf900U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORT_V2_RESERVED; +#define FINN_NV_MEMORY_FABRIC_IMPORT_V2_IMPORT_INTERFACE_ID (0xf901U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORT_V2_IMPORT; +#define FINN_NV_MEMORY_FABRIC_IMPORTED_REF_RESERVED_INTERFACE_ID (0xfb00U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORTED_REF_RESERVED; +#define FINN_NV_MEMORY_FABRIC_IMPORTED_REF_IMPORT_REF_INTERFACE_ID (0xfb01U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORTED_REF_IMPORT_REF; +#define FINN_NV_MEMORY_MULTICAST_FABRIC_RESERVED_INTERFACE_ID (0xfd00U) +typedef FINN_RM_API FINN_NV_MEMORY_MULTICAST_FABRIC_RESERVED; +#define FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID (0xfd01U) +typedef FINN_RM_API FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC; +#define FINN_NV_MEMORY_MAPPER_INTERFACE_ID (0xfe01U) +typedef FINN_RM_API FINN_NV_MEMORY_MAPPER; +#define FINN_LOCK_STRESS_OBJECT_RESERVED_INTERFACE_ID (0x10000U) +typedef FINN_RM_API FINN_LOCK_STRESS_OBJECT_RESERVED; +#define FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID (0x10001U) +typedef FINN_RM_API FINN_LOCK_STRESS_OBJECT_LOCK_STRESS; + +#define FINN_NV20_SUBDEVICE_0_RESERVED_INTERFACE_ID (0x208000U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_RESERVED; +#define FINN_NV20_SUBDEVICE_0_BIF_INTERFACE_ID (0x20803BU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_BIF; +#define FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID (0x208008U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_BIOS; +#define FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID (0x208018U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_BUS; +#define FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID (0x20802aU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_CE; + +#define FINN_NV20_SUBDEVICE_0_CLK_INTERFACE_ID (0x208010U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_CLK; + +#define FINN_NV20_SUBDEVICE_0_DMA_INTERFACE_ID (0x208025U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_DMA; +#define FINN_NV20_SUBDEVICE_0_DMABUF_INTERFACE_ID (0x20803AU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_DMABUF; +#define FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID (0x208034U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_ECC; + +#define FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID (0x208003U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_EVENT; +#define FINN_NV20_SUBDEVICE_0_THERMAL_INTERFACE_ID (0x208005U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_THERMAL; + +#define FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID (0x208013U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FB; +#define FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID (0x208011U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FIFO; +#define FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID (0x208035U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FLA; +#define FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID (0x208031U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FLCN; +#define FINN_NV20_SUBDEVICE_0_FUSE_INTERFACE_ID (0x208002U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FUSE; + +#define FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID (0x208023U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GPIO; + +#define FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID (0x208001U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GPU; + +#define FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID (0x208012U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GR; +#define FINN_NV20_SUBDEVICE_0_GRMGR_INTERFACE_ID (0x208038U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GRMGR; +#define FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID (0x208036U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GSP; +#define FINN_NV20_SUBDEVICE_0_HSHUB_INTERFACE_ID (0x208041U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_HSHUB; +#define FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID (0x208006U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_I2C; +#define FINN_NV20_SUBDEVICE_0_PMGR_INTERFACE_ID (0x208026U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_PMGR; + +#define FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID (0x20800aU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_INTERNAL; +#define FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID (0x20800bU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_INTERNAL_2; +#define FINN_NV20_SUBDEVICE_0_LPWR_INTERFACE_ID (0x208028U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_LPWR; + +#define FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID (0x208017U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_MC; +#define FINN_NV20_SUBDEVICE_0_NNE_INTERFACE_ID (0x208037U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_NNE; + +#define FINN_NV20_SUBDEVICE_0_NOISE_INTERFACE_ID (0x208015U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_NOISE; + +#define FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID (0x208024U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_NVD; + +#define FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID (0x208030U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_NVLINK; + +#define FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID (0x208020U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_PERF; + +#define FINN_NV20_SUBDEVICE_0_POWER_INTERFACE_ID (0x208027U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_POWER; + +#define FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID (0x208022U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_RC; +#define FINN_NV20_SUBDEVICE_0_RIST_INTERFACE_ID (0x208033U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_RIST; + +#define FINN_NV20_SUBDEVICE_0_SEC2_INTERFACE_ID (0x208042U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_SEC2; + +#define FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID (0x208004U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_TIMER; + +#define FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID (0x20803dU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_OS_UNIX; +#define FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID (0x208040U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL; +#define FINN_NV20_SUBDEVICE_0_VOLT_INTERFACE_ID (0x208032U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_VOLT; + +#define FINN_NV2081_BINAPI_RESERVED_INTERFACE_ID (0x208100U) +typedef FINN_RM_API FINN_NV2081_BINAPI_RESERVED; +#define FINN_NV2081_BINAPI_INTERFACE_ID (0x208101U) +typedef FINN_RM_API FINN_NV2081_BINAPI; +#define FINN_NV2082_BINAPI_RESERVED_INTERFACE_ID (0x208200U) +typedef FINN_RM_API FINN_NV2082_BINAPI_RESERVED; +#define FINN_NV2082_BINAPI_INTERFACE_ID (0x208201U) +typedef FINN_RM_API FINN_NV2082_BINAPI; +#define FINN_NV20_SUBDEVICE_DIAG_RESERVED_INTERFACE_ID (0x208f00U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_RESERVED; +#define FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID (0x208f07U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_BIF; +#define FINN_NV20_SUBDEVICE_DIAG_BUS_INTERFACE_ID (0x208f18U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_BUS; +#define FINN_NV20_SUBDEVICE_DIAG_CE_INTERFACE_ID (0x208f1cU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_CE; +#define FINN_NV20_SUBDEVICE_DIAG_DMA_INTERFACE_ID (0x208f14U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_DMA; +#define FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID (0x208f05U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_FB; +#define FINN_NV20_SUBDEVICE_DIAG_FBIO_INTERFACE_ID (0x208f0aU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_FBIO; +#define FINN_NV20_SUBDEVICE_DIAG_FIFO_INTERFACE_ID (0x208f04U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_FIFO; +#define FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID (0x208f11U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_GPU; +#define FINN_NV20_SUBDEVICE_DIAG_GR_INTERFACE_ID (0x208f12U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_GR; + +#define FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID (0x208f0bU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_MMU; +#define FINN_NV20_SUBDEVICE_DIAG_NVLINK_INTERFACE_ID (0x208f1AU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_NVLINK; + +#define FINN_NV20_SUBDEVICE_DIAG_PMU_INTERFACE_ID (0x208f0cU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_PMU; + +#define FINN_NV20_SUBDEVICE_DIAG_PROFILING_INTERFACE_ID (0x208f30U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_PROFILING; +#define FINN_NV20_SUBDEVICE_DIAG_SEC2_INTERFACE_ID (0x208f1dU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_SEC2; +#define FINN_NV20_SUBDEVICE_DIAG_UCODE_INSTRUMENTATION_INTERFACE_ID (0x208f19U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_UCODE_INSTRUMENTATION; +#define FINN_NV30_GSYNC_RESERVED_INTERFACE_ID (0x30f100U) +typedef FINN_RM_API FINN_NV30_GSYNC_RESERVED; +#define FINN_NV30_GSYNC_GSYNC_INTERFACE_ID (0x30f101U) +typedef FINN_RM_API FINN_NV30_GSYNC_GSYNC; +#define FINN_NV40_I2C_RESERVED_INTERFACE_ID (0x402c00U) +typedef FINN_RM_API FINN_NV40_I2C_RESERVED; +#define FINN_NV40_I2C_I2C_INTERFACE_ID (0x402c01U) +typedef FINN_RM_API FINN_NV40_I2C_I2C; +#define FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID (0x503c01U) +typedef FINN_RM_API FINN_NV50_THIRD_PARTY_P2P_P2P; +#define FINN_NV50_THIRD_PARTY_P2P_RESERVED_INTERFACE_ID (0x503c00U) +typedef FINN_RM_API FINN_NV50_THIRD_PARTY_P2P_RESERVED; +#define FINN_NV50_CHANNEL_GPFIFO_RESERVED_INTERFACE_ID (0x506f00U) +typedef FINN_RM_API FINN_NV50_CHANNEL_GPFIFO_RESERVED; +#define FINN_NV50_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID (0x506f01U) +typedef FINN_RM_API FINN_NV50_CHANNEL_GPFIFO_GPFIFO; +#define FINN_NV50_DISPLAY_RESERVED_INTERFACE_ID (0x507000U) +typedef FINN_RM_API FINN_NV50_DISPLAY_RESERVED; +#define FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID (0x507001U) +typedef FINN_RM_API FINN_NV50_DISPLAY_CHNCTL; +#define FINN_NV50_DISPLAY_OR_INTERFACE_ID (0x507004U) +typedef FINN_RM_API FINN_NV50_DISPLAY_OR; +#define FINN_NV50_DISPLAY_RG_INTERFACE_ID (0x507002U) +typedef FINN_RM_API FINN_NV50_DISPLAY_RG; +#define FINN_NV50_DISPLAY_SYSTEM_INTERFACE_ID (0x507007U) +typedef FINN_RM_API FINN_NV50_DISPLAY_SYSTEM; + +#define FINN_NV50_DEFERRED_API_CLASS_RESERVED_INTERFACE_ID (0x508000U) +typedef FINN_RM_API FINN_NV50_DEFERRED_API_CLASS_RESERVED; +#define FINN_NV50_DEFERRED_API_CLASS_DEFERRED_INTERFACE_ID (0x508001U) +typedef FINN_RM_API FINN_NV50_DEFERRED_API_CLASS_DEFERRED; +#define FINN_GT200_DEBUGGER_RESERVED_INTERFACE_ID (0x83de00U) +typedef FINN_RM_API FINN_GT200_DEBUGGER_RESERVED; +#define FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID (0x83de03U) +typedef FINN_RM_API FINN_GT200_DEBUGGER_DEBUG; +#define FINN_GT200_DEBUGGER_FIFO_INTERFACE_ID (0x83de02U) +typedef FINN_RM_API FINN_GT200_DEBUGGER_FIFO; +#define FINN_GT200_DEBUGGER_INTERNAL_INTERFACE_ID (0x83de04U) +typedef FINN_RM_API FINN_GT200_DEBUGGER_INTERNAL; + +#define FINN_NV9010_VBLANK_CALLBACK_RESERVED_INTERFACE_ID (0x901000U) +typedef FINN_RM_API FINN_NV9010_VBLANK_CALLBACK_RESERVED; +#define FINN_NV9010_VBLANK_CALLBACK_INTERFACE_ID (0x901001U) +typedef FINN_RM_API FINN_NV9010_VBLANK_CALLBACK; +#define FINN_FERMI_CONTEXT_SHARE_A_RESERVED_INTERFACE_ID (0x906700U) +typedef FINN_RM_API FINN_FERMI_CONTEXT_SHARE_A_RESERVED; +#define FINN_FERMI_CONTEXT_SHARE_A_TPC_PARTITION_INTERFACE_ID (0x906701U) +typedef FINN_RM_API FINN_FERMI_CONTEXT_SHARE_A_TPC_PARTITION; +#define FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID (0x906702U) +typedef FINN_RM_API FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK; +#define FINN_GF100_CHANNEL_GPFIFO_RESERVED_INTERFACE_ID (0x906f00U) +typedef FINN_RM_API FINN_GF100_CHANNEL_GPFIFO_RESERVED; +#define FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID (0x906f01U) +typedef FINN_RM_API FINN_GF100_CHANNEL_GPFIFO_GPFIFO; +#define FINN_GF100_DISP_SW_RESERVED_INTERFACE_ID (0x907200U) +typedef FINN_RM_API FINN_GF100_DISP_SW_RESERVED; +#define FINN_GF100_DISP_SW_DISP_SW_INTERFACE_ID (0x907201U) +typedef FINN_RM_API FINN_GF100_DISP_SW_DISP_SW; +#define FINN_GF100_TIMED_SEMAPHORE_SW_RESERVED_INTERFACE_ID (0x907400U) +typedef FINN_RM_API FINN_GF100_TIMED_SEMAPHORE_SW_RESERVED; +#define FINN_GF100_TIMED_SEMAPHORE_SW_SEM_INTERFACE_ID (0x907401U) +typedef FINN_RM_API FINN_GF100_TIMED_SEMAPHORE_SW_SEM; +#define FINN_GF100_REMAPPER_RESERVED_INTERFACE_ID (0x907f00U) +typedef FINN_RM_API FINN_GF100_REMAPPER_RESERVED; +#define FINN_GF100_REMAPPER_REMAPPER_INTERFACE_ID (0x907f01U) +typedef FINN_RM_API FINN_GF100_REMAPPER_REMAPPER; +#define FINN_GF100_ZBC_CLEAR_RESERVED_INTERFACE_ID (0x909600U) +typedef FINN_RM_API FINN_GF100_ZBC_CLEAR_RESERVED; +#define FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID (0x909601U) +typedef FINN_RM_API FINN_GF100_ZBC_CLEAR_ZBC; +#define FINN_GF100_PROFILER_RESERVED_INTERFACE_ID (0x90cc00U) +typedef FINN_RM_API FINN_GF100_PROFILER_RESERVED; +#define FINN_GF100_PROFILER_HWPM_INTERFACE_ID (0x90cc01U) +typedef FINN_RM_API FINN_GF100_PROFILER_HWPM; +#define FINN_GF100_PROFILER_NVLINK_INTERFACE_ID (0x90cc02U) +typedef FINN_RM_API FINN_GF100_PROFILER_NVLINK; +#define FINN_GF100_PROFILER_POWER_INTERFACE_ID (0x90cc03U) +typedef FINN_RM_API FINN_GF100_PROFILER_POWER; +#define FINN_NV_EVENT_BUFFER_RESERVED_INTERFACE_ID (0x90cd00U) +typedef FINN_RM_API FINN_NV_EVENT_BUFFER_RESERVED; +#define FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID (0x90cd01U) +typedef FINN_RM_API FINN_NV_EVENT_BUFFER_EVENT; +#define FINN_GF100_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0x90e000U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_GRAPHICS_RESERVED; +#define FINN_GF100_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0x90e001U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_GRAPHICS_GRAPHICS; +#define FINN_GF100_SUBDEVICE_FB_RESERVED_INTERFACE_ID (0x90e100U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_FB_RESERVED; +#define FINN_GF100_SUBDEVICE_FB_FB_INTERFACE_ID (0x90e101U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_FB_FB; +#define FINN_GF100_SUBDEVICE_MASTER_RESERVED_INTERFACE_ID (0x90e600U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_MASTER_RESERVED; +#define FINN_GF100_SUBDEVICE_MASTER_MASTER_INTERFACE_ID (0x90e601U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_MASTER_MASTER; +#define FINN_GF100_SUBDEVICE_INFOROM_RESERVED_INTERFACE_ID (0x90e700U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_RESERVED; +#define FINN_GF100_SUBDEVICE_INFOROM_BBX_INTERFACE_ID (0x90e701U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_BBX; + +#define FINN_GF100_SUBDEVICE_INFOROM_RPR_INTERFACE_ID (0x90e702U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_RPR; + +#define FINN_GF100_HDACODEC_RESERVED_INTERFACE_ID (0x90ec00U) +typedef FINN_RM_API FINN_GF100_HDACODEC_RESERVED; +#define FINN_GF100_HDACODEC_HDACODEC_INTERFACE_ID (0x90ec01U) +typedef FINN_RM_API FINN_GF100_HDACODEC_HDACODEC; +#define FINN_FERMI_VASPACE_A_RESERVED_INTERFACE_ID (0x90f100U) +typedef FINN_RM_API FINN_FERMI_VASPACE_A_RESERVED; +#define FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID (0x90f101U) +typedef FINN_RM_API FINN_FERMI_VASPACE_A_VASPACE; +#define FINN_KEPLER_CHANNEL_GROUP_A_RESERVED_INTERFACE_ID (0xa06c00U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GROUP_A_RESERVED; +#define FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID (0xa06c01U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO; +#define FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID (0xa06c02U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL; +#define FINN_KEPLER_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xa06f00U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xa06f01U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID (0xa06f03U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL; +#define FINN_KEPLER_DEVICE_VGPU_RESERVED_INTERFACE_ID (0xa08000U) +typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_RESERVED; +#define FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID (0xa08001U) +typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY; +#define FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID (0xa08002U) +typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY; +#define FINN_KEPLER_DEVICE_VGPU_VGPU_OTHERS_INTERFACE_ID (0xa08003U) +typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_VGPU_OTHERS; +#define FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID (0xa08101U) +typedef FINN_RM_API FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG; + +#define FINN_NVA083_GRID_DISPLAYLESS_RESERVED_INTERFACE_ID (0xa08300U) +typedef FINN_RM_API FINN_NVA083_GRID_DISPLAYLESS_RESERVED; +#define FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY_INTERFACE_ID (0xa08301U) +typedef FINN_RM_API FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY; +#define FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID (0xa08401U) +typedef FINN_RM_API FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE; +#define FINN_NVENC_SW_SESSION_NVENC_SW_SESSION_INTERFACE_ID (0xa0bc01U) +typedef FINN_RM_API FINN_NVENC_SW_SESSION_NVENC_SW_SESSION; +#define FINN_NVFBC_SW_SESSION_NVFBC_SW_SESSION_INTERFACE_ID (0xa0bd01U) +typedef FINN_RM_API FINN_NVFBC_SW_SESSION_NVFBC_SW_SESSION; +#define FINN_GK110_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0xa0e000U) +typedef FINN_RM_API FINN_GK110_SUBDEVICE_GRAPHICS_RESERVED; +#define FINN_GK110_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0xa0e001U) +typedef FINN_RM_API FINN_GK110_SUBDEVICE_GRAPHICS_GRAPHICS; +#define FINN_GK110_SUBDEVICE_FB_RESERVED_INTERFACE_ID (0xa0e100U) +typedef FINN_RM_API FINN_GK110_SUBDEVICE_FB_RESERVED; +#define FINN_GK110_SUBDEVICE_FB_FB_INTERFACE_ID (0xa0e101U) +typedef FINN_RM_API FINN_GK110_SUBDEVICE_FB_FB; +#define FINN_MAXWELL_FAULT_BUFFER_A_RESERVED_INTERFACE_ID (0xb06900U) +typedef FINN_RM_API FINN_MAXWELL_FAULT_BUFFER_A_RESERVED; +#define FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID (0xb06901U) +typedef FINN_RM_API FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER; +#define FINN_MAXWELL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xb06f00U) +typedef FINN_RM_API FINN_MAXWELL_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xb06f01U) +typedef FINN_RM_API FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_MAXWELL_PROFILER_RESERVED_INTERFACE_ID (0xb0cc00U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_RESERVED; +#define FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID (0xb0cc02U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_INTERNAL; +#define FINN_MAXWELL_PROFILER_POWER_INTERFACE_ID (0xb0cc03U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_POWER; +#define FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID (0xb0cc01U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_PROFILER; +#define FINN_MAXWELL_PROFILER_CONTEXT_RESERVED_INTERFACE_ID (0xb1cc00U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_CONTEXT_RESERVED; +#define FINN_MAXWELL_PROFILER_CONTEXT_PROFILER_INTERFACE_ID (0xb1cc01U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_CONTEXT_PROFILER; +#define FINN_MAXWELL_PROFILER_DEVICE_RESERVED_INTERFACE_ID (0xb2cc00U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_DEVICE_RESERVED; + +#define FINN_MAXWELL_SEC2_SEC2_INTERFACE_ID (0xb6b901U) +typedef FINN_RM_API FINN_MAXWELL_SEC2_SEC2; +#define FINN_GP100_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0xc0e000U) +typedef FINN_RM_API FINN_GP100_SUBDEVICE_GRAPHICS_RESERVED; +#define FINN_GP100_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0xc0e001U) +typedef FINN_RM_API FINN_GP100_SUBDEVICE_GRAPHICS_GRAPHICS; +#define FINN_GP100_SUBDEVICE_FB_RESERVED_INTERFACE_ID (0xc0e100U) +typedef FINN_RM_API FINN_GP100_SUBDEVICE_FB_RESERVED; +#define FINN_GP100_SUBDEVICE_FB_FB_INTERFACE_ID (0xc0e101U) +typedef FINN_RM_API FINN_GP100_SUBDEVICE_FB_FB; +#define FINN_VOLTA_GSP_GSP_INTERFACE_ID (0xc31001U) +typedef FINN_RM_API FINN_VOLTA_GSP_GSP; +#define FINN_ACCESS_COUNTER_NOTIFY_BUFFER_RESERVED_INTERFACE_ID (0xc36500U) +typedef FINN_RM_API FINN_ACCESS_COUNTER_NOTIFY_BUFFER_RESERVED; +#define FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID (0xc36501U) +typedef FINN_RM_API FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER; +#define FINN_MMU_FAULT_BUFFER_RESERVED_INTERFACE_ID (0xc36900U) +typedef FINN_RM_API FINN_MMU_FAULT_BUFFER_RESERVED; +#define FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER_INTERFACE_ID (0xc36901U) +typedef FINN_RM_API FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER; +#define FINN_VOLTA_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc36f00U) +typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc36f01U) +typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_VOLTA_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID (0xc36f03U) +typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_INTERNAL; +#define FINN_NVC370_DISPLAY_RESERVED_INTERFACE_ID (0xc37000U) +typedef FINN_RM_API FINN_NVC370_DISPLAY_RESERVED; +#define FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID (0xc37001U) +typedef FINN_RM_API FINN_NVC370_DISPLAY_CHNCTL; +#define FINN_NVC370_DISPLAY_EVENT_INTERFACE_ID (0xc37009U) +typedef FINN_RM_API FINN_NVC370_DISPLAY_EVENT; +#define FINN_NVC370_DISPLAY_OR_INTERFACE_ID (0xc37004U) +typedef FINN_RM_API FINN_NVC370_DISPLAY_OR; +#define FINN_NVC370_DISPLAY_RG_INTERFACE_ID (0xc37002U) +typedef FINN_RM_API FINN_NVC370_DISPLAY_RG; +#define FINN_NVC370_DISPLAY_VERIF_INTERFACE_ID (0xc37006U) +typedef FINN_RM_API FINN_NVC370_DISPLAY_VERIF; +#define FINN_NVC372_DISPLAY_SW_RESERVED_INTERFACE_ID (0xc37200U) +typedef FINN_RM_API FINN_NVC372_DISPLAY_SW_RESERVED; +#define FINN_NVC372_DISPLAY_SW_CHNCTL_INTERFACE_ID (0xc37201U) +typedef FINN_RM_API FINN_NVC372_DISPLAY_SW_CHNCTL; + +#define FINN_GV100_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0xc3e000U) +typedef FINN_RM_API FINN_GV100_SUBDEVICE_GRAPHICS_RESERVED; +#define FINN_GV100_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0xc3e001U) +typedef FINN_RM_API FINN_GV100_SUBDEVICE_GRAPHICS_GRAPHICS; +#define FINN_GV100_SUBDEVICE_FB_RESERVED_INTERFACE_ID (0xc3e100U) +typedef FINN_RM_API FINN_GV100_SUBDEVICE_FB_RESERVED; +#define FINN_GV100_SUBDEVICE_FB_FB_INTERFACE_ID (0xc3e101U) +typedef FINN_RM_API FINN_GV100_SUBDEVICE_FB_FB; +#define FINN_AMPERE_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc56f00U) +typedef FINN_RM_API FINN_AMPERE_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc56f01U) +typedef FINN_RM_API FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_AMPERE_SMC_PARTITION_REF_RESERVED_INTERFACE_ID (0xc63700U) +typedef FINN_RM_API FINN_AMPERE_SMC_PARTITION_REF_RESERVED; +#define FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID (0xc63701U) +typedef FINN_RM_API FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS; +#define FINN_AMPERE_SMC_EXEC_PARTITION_REF_RESERVED_INTERFACE_ID (0xc63800U) +typedef FINN_RM_API FINN_AMPERE_SMC_EXEC_PARTITION_REF_RESERVED; +#define FINN_AMPERE_SMC_EXEC_PARTITION_REF_EXEC_PARTITION_INTERFACE_ID (0xc63801U) +typedef FINN_RM_API FINN_AMPERE_SMC_EXEC_PARTITION_REF_EXEC_PARTITION; +#define FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_RESERVED_INTERFACE_ID (0xc76300U) +typedef FINN_RM_API FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_RESERVED; +#define FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER_INTERFACE_ID (0xc76301U) +typedef FINN_RM_API FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER; +#define FINN_NV_CONFIDENTIAL_COMPUTE_RESERVED_INTERFACE_ID (0xcb3300U) +typedef FINN_RM_API FINN_NV_CONFIDENTIAL_COMPUTE_RESERVED; +#define FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID (0xcb3301U) +typedef FINN_RM_API FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE; + +#define FINN_NV_COUNTER_COLLECTION_UNIT_RESERVED_INTERFACE_ID (0xcbca00U) +typedef FINN_RM_API FINN_NV_COUNTER_COLLECTION_UNIT_RESERVED; +#define FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID (0xcbca01U) +typedef FINN_RM_API FINN_NV_COUNTER_COLLECTION_UNIT_CCU; +#define FINN_NV_SCHEDULER_RESERVED_INTERFACE_ID (0xcbcb00U) +typedef FINN_RM_API FINN_NV_SCHEDULER_RESERVED; +#define FINN_NV_SCHEDULER_SCHEDULER_INTERFACE_ID (0xcbcb01U) +typedef FINN_RM_API FINN_NV_SCHEDULER_SCHEDULER; +#define CMC_UMD_API_RESERVED_INTERFACE_ID (0xcbcd00U) +typedef FINN_RM_API CMC_UMD_API_RESERVED; +#define CMC_UMD_API_CONTROL_INTERFACE_ID (0xcbcd01U) +typedef FINN_RM_API CMC_UMD_API_CONTROL; + +#define FINN_NVE2_SYNCPOINT_BASE_RESERVED_INTERFACE_ID (0xe2ad00U) +typedef FINN_RM_API FINN_NVE2_SYNCPOINT_BASE_RESERVED; +#define FINN_NVE2_SYNCPOINT_BASE_SYNCPOINT_BASE_INTERFACE_ID (0xe2ad01U) +typedef FINN_RM_API FINN_NVE2_SYNCPOINT_BASE_SYNCPOINT_BASE; diff --git a/userspace/sdks/nv570/inc/mmu_fmt_types.h b/userspace/sdks/nv570/inc/mmu_fmt_types.h new file mode 100644 index 0000000..13bb88f --- /dev/null +++ b/userspace/sdks/nv570/inc/mmu_fmt_types.h @@ -0,0 +1,151 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: mmu_fmt_types.finn +// + + + + +/*! + * @file mmu_fmt_types.h + * + * @brief Types used to describre MMU HW formats. + */ +#include "nvtypes.h" + +// Forward declarations. + + +/*! + * Generic MMU page directory/table level format description. + * + * Since the terminology of page directories and tables varies, + * the following describes the interpretation assumed here. + * + * Each level of virtual address translation is described by a range of + * virtual address bits. + * These bits index into a contiguous range of physical memory referred to + * generally as a "page level." + * Page level memory is interpreted as an array of entries, with each entry + * describing the next step of virtual to physical translation. + * + * Each entry in a given level may be interpreted as either a PDE or PTE. + * 1. A PDE (page directory entry) points to one or more "sub-levels" that + * continue the VA translation recursively. + * 2. A PTE (page table entry) is the base case, pointing to a physical page. + * + * The decision to treat an entry as a PDE or PTE may be static for a level. + * Levels that only contain PDEs are referred to as page directories. + * Levels that only contain PTEs are referred to as page tables. + * + * However, some formats have levels that may contain a mix of PDEs and PTEs, + * with the intpretation based on a "cutoff" bit in each entry (e.g. PTE valid bit). + * Such levels are referred to as "polymorphic page levels" since they can be + * viewed as both a page directory and a page table. + */ +typedef struct MMU_FMT_LEVEL { + /*! + * First virtual address bit that this page level covers. + */ + NvU8 virtAddrBitLo; + + /*! + * Last virtual address bit that this page level covers. + */ + NvU8 virtAddrBitHi; + + /*! + * Size in bytes of each entry within a level instance. + */ + NvU8 entrySize; + + /*! + * Indicates if this level can contain PTEs. + */ + NvBool bPageTable; + + /*! + * Number of sub-levels pointed to by PDEs in this level in + * range [0, MMU_FMT_MAX_SUB_LEVELS]. + * 0 indicates this level cannot contain PDEs. + */ + NvU8 numSubLevels; + + /*! + * Information tag used to decode internal level naming. + * Used for verif. + * */ + NvU32 pageLevelIdTag; + + + /*! + * Array of sub-level formats of length numSubLevels. + * + * @warning This array results in a circular reference to MMU_FMT_LEVEL. + * This can present an issue for FINN serialization and may have to + * be refactored before MMU_FMT_LEVEL can be serialized. + */ + NV_DECLARE_ALIGNED(struct MMU_FMT_LEVEL *subLevels, 8); +} MMU_FMT_LEVEL; + +/*! + * Maximum number of pointers to sub-levels within a page directory entry. + * + * Standard page directory entries (PDEs) point to a single sub-level, + * either the next page directory level in the topology or a leaf page table. + * + * However, some formats contain PDEs that point to more than one sub-level. + * These sub-levels are translated by HW in parallel to support multiple + * page sizes at a higher granularity (e.g. for migration between + * 4K system memory pages and big video memory pages for GPU MMU). + * + * The current supported formats have a maximum of 2 parallel sub-levels, + * often referred to as "dual PDE" or "dual page table" support. + * + * Example for Fermi GPU HW: + * Sub-level 0 corresponds to big page table pointer. + * Sub-level 1 corresponds to small page table pointer. + * + * This number is very unlikely to change, but it is defined to + * simplify SW handling, encouraging loops over "dual copy-paste." + */ +#define MMU_FMT_MAX_SUB_LEVELS 2 + +/*! + * Valid values for the pageLevelIdTag field. + * These values are used to identify the internal naming of the page level. + * Used for verif purposes. + */ +#define MMU_FMT_PT_SURF_ID_PD0 0 +#define MMU_FMT_PT_SURF_ID_PD1 1 +#define MMU_FMT_PT_SURF_ID_PD2 2 +#define MMU_FMT_PT_SURF_ID_PD3 3 +#define MMU_FMT_PT_SURF_ID_PD4 4 +#define MMU_FMT_PT_SURF_ID_PT_4K 5 +#define MMU_FMT_PT_SURF_ID_PT_BIG 6 diff --git a/userspace/sdks/nv570/inc/nv-hypervisor.h b/userspace/sdks/nv570/inc/nv-hypervisor.h new file mode 100644 index 0000000..a2b2649 --- /dev/null +++ b/userspace/sdks/nv570/inc/nv-hypervisor.h @@ -0,0 +1,93 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NV_HYPERVISOR_H_ +#define _NV_HYPERVISOR_H_ + +#include + +// Enums for supported hypervisor types. +// New hypervisor type should be added before OS_HYPERVISOR_UNKNOWN +typedef enum _HYPERVISOR_TYPE +{ + OS_HYPERVISOR_XEN = 0, + OS_HYPERVISOR_VMWARE, + OS_HYPERVISOR_HYPERV, + OS_HYPERVISOR_KVM, + OS_HYPERVISOR_UNKNOWN +} HYPERVISOR_TYPE; + +#define CMD_VFIO_WAKE_REMOVE_GPU 1 +#define CMD_VGPU_VFIO_PRESENT 2 +#define CMD_VFIO_PCI_CORE_PRESENT 3 + +#define MAX_VF_COUNT_PER_GPU 64 + +typedef enum _VGPU_TYPE_INFO +{ + VGPU_TYPE_NAME = 0, + VGPU_TYPE_DESCRIPTION, + VGPU_TYPE_INSTANCES, +} VGPU_TYPE_INFO; + +typedef struct +{ + void *nv; + NvU32 domain; + NvU32 bus; + NvU32 device; + NvU32 return_status; +} vgpu_vfio_info; + +typedef struct +{ + NvU32 domain; + NvU8 bus; + NvU8 slot; + NvU8 function; + NvBool isNvidiaAttached; + NvBool isMdevAttached; +} vgpu_vf_pci_info; + +typedef enum VGPU_CMD_PROCESS_VF_INFO_E +{ + NV_VGPU_SAVE_VF_INFO = 0, + NV_VGPU_REMOVE_VF_PCI_INFO = 1, + NV_VGPU_REMOVE_VF_MDEV_INFO = 2, + NV_VGPU_GET_VF_INFO = 3 +} VGPU_CMD_PROCESS_VF_INFO; + +typedef enum VGPU_DEVICE_STATE_E +{ + NV_VGPU_DEV_UNUSED = 0, + NV_VGPU_DEV_OPENED = 1, + NV_VGPU_DEV_IN_USE = 2 +} VGPU_DEVICE_STATE; + +/* + * Function prototypes + */ + +HYPERVISOR_TYPE NV_API_CALL nv_get_hypervisor_type(void); + +#endif // _NV_HYPERVISOR_H_ diff --git a/userspace/sdks/nv570/inc/nv-kernel-interface-api.h b/userspace/sdks/nv570/inc/nv-kernel-interface-api.h new file mode 100644 index 0000000..183f9b4 --- /dev/null +++ b/userspace/sdks/nv570/inc/nv-kernel-interface-api.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NV_KERNEL_INTERFACE_API_H +#define _NV_KERNEL_INTERFACE_API_H +/************************************************************************************************************** +* +* File: nv-kernel-interface-api.h +* +* Description: +* Defines the NV API related macros. +* +**************************************************************************************************************/ + +#if NVOS_IS_UNIX && NVCPU_IS_X86_64 && defined(__use_altstack__) +#define NV_API_CALL __attribute__((altstack(0))) +#else +#define NV_API_CALL +#endif + +#endif /* _NV_KERNEL_INTERFACE_API_H */ diff --git a/userspace/sdks/nv570/inc/nv_stdarg.h b/userspace/sdks/nv570/inc/nv_stdarg.h new file mode 100644 index 0000000..b23f7f7 --- /dev/null +++ b/userspace/sdks/nv570/inc/nv_stdarg.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _NV_STDARG_H_ +#define _NV_STDARG_H_ + +#if defined(NV_KERNEL_INTERFACE_LAYER) && defined(NV_LINUX) + #include "conftest.h" + #if defined(NV_LINUX_STDARG_H_PRESENT) + #include + #else + #include + #endif +#else + #include +#endif + +#endif // _NV_STDARG_H_ diff --git a/userspace/sdks/nv570/inc/nv_vgpu_types.h b/userspace/sdks/nv570/inc/nv_vgpu_types.h new file mode 100644 index 0000000..eea5638 --- /dev/null +++ b/userspace/sdks/nv570/inc/nv_vgpu_types.h @@ -0,0 +1,61 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: nv_vgpu_types.finn +// + + + + +/* XAPIGEN - this file is not suitable for (nor needed by) xapigen. */ +/* Rather than #ifdef out every such include in every sdk */ +/* file, punt here. */ +#include "nvtypes.h" + /* ! XAPIGEN */ + +#define VM_UUID_SIZE 16 +#define INVALID_VGPU_DEV_INST 0xFFFFFFFFU +#define MAX_VGPU_DEVICES_PER_VM 16U + +/* This enum represents the current state of guest dependent fields */ +typedef enum GUEST_VM_INFO_STATE { + GUEST_VM_INFO_STATE_UNINITIALIZED = 0, + GUEST_VM_INFO_STATE_INITIALIZED = 1, +} GUEST_VM_INFO_STATE; + +/* This enum represents types of VM identifiers */ +typedef enum VM_ID_TYPE { + VM_ID_DOMAIN_ID = 0, + VM_ID_UUID = 1, +} VM_ID_TYPE; + +/* This structure represents VM identifier */ +typedef union VM_ID { + NvU8 vmUuid[VM_UUID_SIZE]; + NV_DECLARE_ALIGNED(NvU64 vmId, 8); +} VM_ID; diff --git a/userspace/sdks/nv570/inc/nvcd.h b/userspace/sdks/nv570/inc/nvcd.h new file mode 100644 index 0000000..6c462eb --- /dev/null +++ b/userspace/sdks/nv570/inc/nvcd.h @@ -0,0 +1,159 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2002-2002 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVCD_H +#define NVCD_H + +//****************************************************************************** +// +// Module Name: NVCD.H +// +// This file contains structures and constants that define the NV specific +// data to be returned by the miniport's new VideoBugCheckCallback. The callback +// can return up to 4k bytes of data that will be appended to the dump file. +// The bugcheck callback is currently only invoked for bugcheck 0xEA failures. +// The buffer returned contains a top level header, followed by a variable +// number of data records. The top level header contains an ASCII signature +// that can be located with a search as well as a GUID for unique identification +// of the crash dump layout, i.e. future bugcheck callbacks can define a new +// GUID to redefine the entire crash dump layout. A checksum and crash dump +// size values are also included to insure crash dump data integrity. The +// data records each contain a header indicating what group the data belongs to +// as well as the actual record type and size. This flexibility allows groups +// to define and extend the information in their records without adversely +// affecting the code in the debugger extension that has to parse and display +// this information. The structures for these individual data records are +// contained in separate header files for each group. +// +//****************************************************************************** +#include "nvtypes.h" + +// Define the GUID type for non-Windows OSes + +#ifndef GUID_DEFINED +#define GUID_DEFINED +typedef struct _GUID { + NvU32 Data1; + NvU16 Data2; + NvU16 Data3; + NvU8 Data4[8]; +} GUID, *LPGUID; +#endif + +// Define the crash dump ASCII tag value and the dump format GUIDs +#define NVCD_SIGNATURE 0x4443564E /* ASCII crash dump signature "NVCD" */ + +#define GUID_NVCD_DUMP_V1 { /* e3d5dc6e-db7d-4e28-b09e-f59a942f4a24 */ \ + 0xe3d5dc6e, 0xdb7d, 0x4e28, \ + {0xb0, 0x9e, 0xf5, 0x9a, 0x94, 0x2f, 0x4a, 0x24}\ +}; +#define GUID_NVCD_DUMP_V2 { /* cd978ac1-3aa1-494b-bb5b-e93daf2b0536 */ \ + 0xcd978ac1, 0x3aa1, 0x494b, \ + {0xbb, 0x5b, 0xe9, 0x3d, 0xaf, 0x2b, 0x05, 0x36}\ +}; +#define GUID_NVCDMP_RSVD1 { /* 391fc656-a37c-4574-8d57-b29a562f909b */ \ + 0x391fc656, 0xa37c, 0x4574, \ + {0x8d, 0x57, 0xb2, 0x9a, 0x56, 0x2f, 0x90, 0x9b}\ +}; +#define GUID_NVCDMP_RSVD2 { /* c6d9982d-1ba9-4f80-badd-3dc992d41b46 */ \ + 0xc6d9982d, 0x1ba9, 0x4f80, \ + {0xba, 0xdd, 0x3d, 0xc9, 0x92, 0xd4, 0x1b, 0x46}\ +}; + +// RC 2.0 NVCD (NV crash dump) GUID +#define GUID_NVCD_RC2_V1 { /* d3793533-a4a6-46d3-97f2-1446cfdc1ee7 */ \ + 0xd3793533, 0xa4a6, 0x46d3, \ + {0x97, 0xf2, 0x14, 0x46, 0xcf, 0xdc, 0x1e, 0xe7}\ +}; + + +// Define NVIDIA crash dump header structure (First data block in crash dump) +typedef struct +{ + NvU32 dwSignature; // ASCII crash dump signature "NVCD" + GUID gVersion; // GUID for crashdump file (Version) + NvU32 dwSize; // Size of the crash dump data + NvU8 cCheckSum; // Crash dump checksum (Zero = ignore) + NvU8 cFiller[3]; // Filler (Possible CRC value) +} NVCD_HEADER; +typedef NVCD_HEADER *PNVCD_HEADER; + +// Define the crash dump record groups +typedef enum +{ + NvcdGroup = 0, // NVIDIA crash dump group (System NVCD records) + RmGroup = 1, // Resource manager group (RM records) + DriverGroup = 2, // Driver group (Driver/miniport records) + HardwareGroup = 3, // Hardware group (Hardware records) + InstrumentationGroup = 4, // Instrumentation group (Special records) +} NVCD_GROUP_TYPE; + +// Define the crash dump group record types (Single end of data record type) +typedef enum +{ + EndOfData = 0, // End of crash dump data record + CompressedDataHuffman = 1, // Compressed huffman data +} NVCD_RECORD_TYPE; + +// Define the crash dump data record header +typedef struct +{ + NvU8 cRecordGroup; // Data record group (NVCD_GROUP_TYPE) + NvU8 cRecordType; // Data record type (See group header) + NvU16 wRecordSize; // Size of the data record in bytes +} NVCD_RECORD; +typedef NVCD_RECORD *PNVCD_RECORD; + +// Define the EndOfData record structure +typedef struct +{ + NVCD_RECORD Header; // End of data record header +} EndOfData_RECORD; +typedef EndOfData_RECORD *PEndOfData_RECORD; + +// +// Generic mini-record type (keep the size at 64bits) +// +typedef struct +{ + NVCD_RECORD Header; // header for mini record + NvU32 Payload; // 32 bit payload value +} NVCDMiniRecord; +typedef NVCDMiniRecord *PNVCDMiniRecord; + +// +// Generic record collection type +// +typedef struct +{ + NVCD_RECORD Header; // generic header to binary type this in OCA buffer + // size is actual size of this struct + all items in collection + NvU32 NumRecords; // number of records this collection contain + NVCD_RECORD FirstRecord; // first record, its data follow +} NVCDRecordCollection; +typedef NVCDRecordCollection *PNVCDRecordCollection; + +#define COLL_HEADER_SIZEOF (sizeof(NVCDRecordCollection) - sizeof(NVCD_RECORD)) + + +#endif // NVCD_H diff --git a/userspace/sdks/nv570/inc/nvcfg_sdk.h b/userspace/sdks/nv570/inc/nvcfg_sdk.h new file mode 100644 index 0000000..4ce8d4b --- /dev/null +++ b/userspace/sdks/nv570/inc/nvcfg_sdk.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef NV_CFG_SDK_INCLUDED +#define NV_CFG_SDK_INCLUDED + + +#endif // NV_CFG_SDK_INCLUDED diff --git a/userspace/sdks/nv570/inc/nvdeprecated.h b/userspace/sdks/nv570/inc/nvdeprecated.h new file mode 100644 index 0000000..64729da --- /dev/null +++ b/userspace/sdks/nv570/inc/nvdeprecated.h @@ -0,0 +1,125 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NV_DEPRECATED_H +#define NV_DEPRECATED_H + +/*! + * @file nvdeprecated.h + * + * @brief Deprecation in the NVIDIA SDK + * + * Why deprecate: + * Code is deprecated when you want to remove a feature entirely, but cannot + * do so immediately, nor in a single step, due to a requirement to remain + * backward compatible (keep older clients working). + * + * Backwards compatibility: + * Deprecated symbols and features may be supported for an unknown amount of + * time. "Deprecated" means that we want that time interval to be small, but + * that may not be under our control. + * + * This file provides the following ways to support deprecated features: + * + * 1) Defining NV_STRICT_SDK before including a SDK headers. This will + * remove *all* deprecated APIs from the NV SDK, for example: + * + * #define NV_STRICT_SDK + * #include "sdk/foo.h" + * + * 2) Defining the per-feature compatibility setting before including the + * SDK, for example: + * + * #define NV_DEPRECATED_NVOS_STATUS 0 // enable compatibility mode + * #include "sdk/foo.h" + * + * How to deprecate a feature in the SDK: + * + * 1) Define the deprecated feature in this file. Often, you'll want to + * start with SDK compatibility enabled by default, for example: + * + * #ifndef NV_DEPRECATED_FEATURE_NAME + * #define NV_DEPRECATED_FEATURE_NAME 0 + * #endif + * + * 2) Wrap SDK definitions with compatibility #ifdefs: + * + * #if NV_DEPRECATED_COMPAT(FEATURE_NAME) + * ...legacy definitions... + * #endif + * + * 3) In the API implementation, consider stubbing or wrapping the new API. + * + * 4) Update older clients: file bugs to track this effort. Bug numbers + * should be placed in comments near the deprecated features that RM is + * supporting. That way, people reading the code can easily find the + * bug(s) that show the status of completely removing the deprecated + * feature. + * + * 5) Once all the client (calling) code has been upgraded, change the + * macro to "compatibility off". This is a little more cautious and + * conservative than jumping directly to step (6), because it allows you + * to recover from a test failure (remember, there are extended, offline + * tests that are not, unfortunately, run in DVS, nor per-CL checkin) + * with a tiny change in code. + * + * 6) Once the code base has migrated, remove all definitions from the SDK. + */ + +/* + * \defgroup Deprecated SDK Features + * + * 0 = Compatibility on by default (i.e.: defines present in SDK) + * 1 = Compatibility off by default (i.e.: defines NOT in SDK) + * + * @{ + */ + +#ifndef NV_DEPRECATED_NVOS_STATUS +/* NVOS_STATUS codes is deprecated. NV_STATUS to be used instead */ +#define NV_DEPRECATED_NVOS_STATUS 0 +#endif + +#ifndef NV_DEPRECATED_RM_STATUS +/* RM_STATUS codes is deprecated. NV_STATUS to be used instead */ +#define NV_DEPRECATED_RM_STATUS 0 +#endif + +#ifndef NV_DEPRECATED_UNSAFE_HANDLES +/* Using NvU32 for handles is deprecated. NvHandle to be used instead */ +#define NV_DEPRECATED_UNSAFE_HANDLES 0 +#endif + +/**@}*/ + +/*! + * Utility Macros + */ + +#ifdef NV_STRICT_SDK +// In strict mode, all obsolete features are unavailable in the SDK. +#define NV_DEPRECATED_COMPAT(feature) 0 +#else +#define NV_DEPRECATED_COMPAT(feature) (!NV_DEPRECATED_##feature) +#endif + +#endif diff --git a/userspace/sdks/nv570/inc/nvdisptypes.h b/userspace/sdks/nv570/inc/nvdisptypes.h new file mode 100644 index 0000000..adcfb98 --- /dev/null +++ b/userspace/sdks/nv570/inc/nvdisptypes.h @@ -0,0 +1,92 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2016,2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + /***************************************************************************\ +|* *| +|* NV Display Common Types *| +|* *| +|* defines the common display types. *| +|* *| + \***************************************************************************/ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: nvdisptypes.finn +// + + + + +#include "nvtypes.h" + + + +typedef enum NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP { + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_DEFAULT = 0, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 = 1, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 = 2, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 = 3, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 = 4, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 = 5, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 = 6, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 = 7, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 = 8, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 = 9, +} NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP; + + + +typedef NvU32 NV_DISP_LOCK_PIN; + +#define NV_DISP_LOCK_PIN_0 0x0 +#define NV_DISP_LOCK_PIN_1 0x1 +#define NV_DISP_LOCK_PIN_2 0x2 +#define NV_DISP_LOCK_PIN_3 0x3 +#define NV_DISP_LOCK_PIN_4 0x4 +#define NV_DISP_LOCK_PIN_5 0x5 +#define NV_DISP_LOCK_PIN_6 0x6 +#define NV_DISP_LOCK_PIN_7 0x7 +#define NV_DISP_LOCK_PIN_8 0x8 +#define NV_DISP_LOCK_PIN_9 0x9 +#define NV_DISP_LOCK_PIN_A 0xA +#define NV_DISP_LOCK_PIN_B 0xB +#define NV_DISP_LOCK_PIN_C 0xC +#define NV_DISP_LOCK_PIN_D 0xD +#define NV_DISP_LOCK_PIN_E 0xE +#define NV_DISP_LOCK_PIN_F 0xF + +// Value used solely for HW initialization +#define NV_DISP_LOCK_PIN_UNSPECIFIED 0x10 + + + +typedef NvU32 NV_DISP_LOCK_MODE; + +#define NV_DISP_LOCK_MODE_NO_LOCK 0x0 +#define NV_DISP_LOCK_MODE_FRAME_LOCK 0x1 +#define NV_DISP_LOCK_MODE_RASTER_LOCK 0x3 + diff --git a/userspace/sdks/nv570/inc/nvdump.h b/userspace/sdks/nv570/inc/nvdump.h new file mode 100644 index 0000000..45f607f --- /dev/null +++ b/userspace/sdks/nv570/inc/nvdump.h @@ -0,0 +1,164 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +//////////////////////////////////////////////////////////////////////////////// +// +// Module: nvDump.h +// Shared definitions for HW/SW dumping facility residing in resman/rc. +// +// ************************************************************************** + +#ifndef _NVDUMP_H_ +#define _NVDUMP_H_ + +#include "nvtypes.h" + +//------------------------------------------------------------------------- +// DEFINTIONS +//------------------------------------------------------------------------- + +#define NVDUMP_SUB_ALLOC_NOT_ENCODED 0x01 +#define NVDUMP_SUB_ALLOC_VALID 0x02 +#define NVDUMP_SUB_ALLOC_HAS_MORE 0x04 + +#define NVDUMP_DEBUG_BUFFER_MAX_SIZE 4096 // max of 4K per buffer +#define NVDUMP_DEBUG_BUFFER_MAX_SUBALLOCATIONS 256 + +#define NVDUMP_CONFIG_SIGNATURE "NVDUMPCONFIGSIG" // multiple of 8 bytes + +typedef enum +{ + // The following components are GPU instance specific: + NVDUMP_COMPONENT_DEBUG_BUFFERS = 0, + NVDUMP_COMPONENT_ENG_MC, + NVDUMP_COMPONENT_ENG_FIFO, + NVDUMP_COMPONENT_ENG_GRAPHICS, + NVDUMP_COMPONENT_ENG_FB, + NVDUMP_COMPONENT_ENG_DISP, + NVDUMP_COMPONENT_ENG_FAN, + NVDUMP_COMPONENT_ENG_THERMAL, + NVDUMP_COMPONENT_ENG_FUSE, + NVDUMP_COMPONENT_ENG_VBIOS, + NVDUMP_COMPONENT_ENG_PERF, + NVDUMP_COMPONENT_ENG_BUS, + NVDUMP_COMPONENT_ENG_PMU, + NVDUMP_COMPONENT_ENG_ALL, + NVDUMP_COMPONENT_ENG_CE, + NVDUMP_COMPONENT_ENG_GPU, + NVDUMP_COMPONENT_ENG_LPWR, + NVDUMP_COMPONENT_ENG_NVD, + NVDUMP_COMPONENT_ENG_VOLT, + NVDUMP_COMPONENT_ENG_CLK, + NVDUMP_COMPONENT_ENG_SEC2, + NVDUMP_COMPONENT_ENG_NVLINK, + NVDUMP_COMPONENT_ENG_NVDEC, + NVDUMP_COMPONENT_ENG_DPU, + NVDUMP_COMPONENT_ENG_FBFLCN, + NVDUMP_COMPONENT_ENG_HDA, + NVDUMP_COMPONENT_ENG_NVENC, + NVDUMP_COMPONENT_ENG_GSP, + NVDUMP_COMPONENT_ENG_INFOROM, + NVDUMP_COMPONENT_ENG_GCX, + NVDUMP_COMPONENT_ENG_KGSP, + // The following components are global to the system: + NVDUMP_COMPONENT_SYS_RCDB = 0x400, + NVDUMP_COMPONENT_SYS_SYSINFO, + NVDUMP_COMPONENT_SYS_ALL, + // The following components are nvlog related. + NVDUMP_COMPONENT_NVLOG_RM = 0x800, + NVDUMP_COMPONENT_NVLOG_ALL, + // Reserved + NVDUMP_COMPONENT_NVLOG_RESERVED = 0xB00, +} NVDUMP_COMPONENT; + +#define NVDUMP_IS_GPU_COMPONENT(c) ((c) < NVDUMP_COMPONENT_SYS_RCDB) +#define NVDUMP_IS_SYS_COMPONENT(c) (((c) >= NVDUMP_COMPONENT_SYS_RCDB) && \ + ((c) < NVDUMP_COMPONENT_NVLOG_RM)) +#define NVDUMP_IS_NVLOG_COMPONENT(c) (((c) >= NVDUMP_COMPONENT_NVLOG_RM) && \ + ((c) < NVDUMP_COMPONENT_NVLOG_RESERVED)) + +typedef enum +{ + NVDUMP_BUFFER_PROVIDED = 0, // Dump buffer provided by caller + NVDUMP_BUFFER_ALLOCATE, // Dump buffer to be allocated + NVDUMP_BUFFER_COUNT, // Just count, no buffer needed +} NVDUMP_BUFFER_POLICY; + +typedef enum +{ + NVDUMP_STATUS_IDLE, + NVDUMP_STATUS_ERROR, + NVDUMP_STATUS_COUNT_REQUESTED, + NVDUMP_STATUS_COUNT_COMPLETE, + NVDUMP_STATUS_DUMP_REQUESTED, + NVDUMP_STATUS_DUMP_BUFFER_FULL, + NVDUMP_STATUS_DUMP_END_OF_MSG, + NVDUMP_STATUS_DUMP_COMPLETE, +} NVDUMP_STATUS; + +// +// The following structures require that all elements are precisely sized +// and aligned on natural boundaries. +// + +typedef struct +{ + NvP64 address NV_ALIGN_BYTES(8); + NvU32 size; + NvU32 curNumBytes; +} NVDUMP_BUFFER; + +// Max number of bytes that can be returned in a dump buffer +#define NVDUMP_MAX_DUMP_SIZE (1 << 20) // 1 MB + +typedef struct +{ + NvU8 sigHead[sizeof(NVDUMP_CONFIG_SIGNATURE)] NV_ALIGN_BYTES(8); + + NvP64 debuggerControlFuncAddr NV_ALIGN_BYTES(8); + NVDUMP_BUFFER buffer; + NvU32 gpuSelect; + NvU32 component; + NvU32 dumpStatus; + NvU32 rmStatus; + + NvU8 sigTail[sizeof(NVDUMP_CONFIG_SIGNATURE)] NV_ALIGN_BYTES(8); +} NVDUMP_CONFIG; + +typedef struct +{ + NvU16 length; + NvU16 start; + NvU16 end; + NvU16 flags; + NvU16 tag; +} NVDUMP_SUB_ALLOC_HEADER; + +// +// Export is needed to allow remote kernel debuggers without symbols +// to find global NVDUMP_CONFIG variables in driver export address table. +// +#define NVDUMP_EXPORT + +#endif // _NVDUMP_H_ + diff --git a/userspace/sdks/nv570/inc/nverror.h b/userspace/sdks/nv570/inc/nverror.h new file mode 100644 index 0000000..28c2ab6 --- /dev/null +++ b/userspace/sdks/nv570/inc/nverror.h @@ -0,0 +1,303 @@ +/* + * Copyright (c) 1993-2026, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVERROR_H +#define NVERROR_H +/****************************************************************************** +* +* File: nverror.h +* +* Description: +* This file contains the error codes set when the error notifier +* is signaled. +* +******************************************************************************/ + +#include "nvcfg_sdk.h" + +#define ROBUST_CHANNEL_GR_EXCEPTION (13) +#define ROBUST_CHANNEL_FAKE_ERROR (14) +#define ROBUST_CHANNEL_VBLANK_CALLBACK_TIMEOUT (16) +#define ROBUST_CHANNEL_DISP_MISSED_NOTIFIER (19) +#define ROBUST_CHANNEL_MPEG_ERROR_SW_METHOD (20) +#define ROBUST_CHANNEL_ME_ERROR_SW_METHOD (21) +#define ROBUST_CHANNEL_VP_ERROR_SW_METHOD (22) +#define ROBUST_CHANNEL_RC_LOGGING_ENABLED (23) +#define ROBUST_CHANNEL_VP_ERROR (27) +#define ROBUST_CHANNEL_VP2_ERROR (28) +#define ROBUST_CHANNEL_BSP_ERROR (29) +#define ROBUST_CHANNEL_UNUSED_ERROR_30 (30) +#define ROBUST_CHANNEL_FIFO_ERROR_MMU_ERR_FLT (31) +#define ROBUST_CHANNEL_PBDMA_ERROR (32) +#define ROBUST_CHANNEL_SEC_ERROR (33) +#define ROBUST_CHANNEL_MSVLD_ERROR (34) +#define ROBUST_CHANNEL_MSPDEC_ERROR (35) +#define ROBUST_CHANNEL_MSPPP_ERROR (36) +#define ROBUST_CHANNEL_CE0_ERROR (39) +#define ROBUST_CHANNEL_CE1_ERROR (40) +#define ROBUST_CHANNEL_CE2_ERROR (41) +#define ROBUST_CHANNEL_VIC_ERROR (42) +#define ROBUST_CHANNEL_RESETCHANNEL_VERIF_ERROR (43) +#define ROBUST_CHANNEL_GR_FAULT_DURING_CTXSW (44) +#define ROBUST_CHANNEL_PREEMPTIVE_REMOVAL (45) +#define ROBUST_CHANNEL_NVENC0_ERROR (47) +#define ROBUST_CHANNEL_GPU_ECC_DBE (48) +#define FB_MEMORY_ERROR (58) +#define PMU_ERROR (59) +#define ROBUST_CHANNEL_SEC2_ERROR (60) +#define PMU_BREAKPOINT (61) +#define PMU_HALT_ERROR (62) +#define INFOROM_PAGE_RETIREMENT_EVENT (63) +#define INFOROM_DRAM_RETIREMENT_EVENT INFOROM_PAGE_RETIREMENT_EVENT +#define INFOROM_PAGE_RETIREMENT_FAILURE (64) +#define INFOROM_DRAM_RETIREMENT_FAILURE INFOROM_PAGE_RETIREMENT_FAILURE +#define ROBUST_CHANNEL_NVENC1_ERROR (65) +#define ROBUST_CHANNEL_NVDEC0_ERROR (68) +#define ROBUST_CHANNEL_GR_CLASS_ERROR (69) +#define ROBUST_CHANNEL_CE3_ERROR (70) +#define ROBUST_CHANNEL_CE4_ERROR (71) +#define ROBUST_CHANNEL_CE5_ERROR (72) +#define ROBUST_CHANNEL_NVENC2_ERROR (73) +#define NVLINK_ERROR (74) +#define ROBUST_CHANNEL_CE6_ERROR (75) +#define ROBUST_CHANNEL_CE7_ERROR (76) +#define ROBUST_CHANNEL_CE8_ERROR (77) +#define VGPU_START_ERROR (78) +#define ROBUST_CHANNEL_GPU_HAS_FALLEN_OFF_THE_BUS (79) +#define PBDMA_PUSHBUFFER_CRC_MISMATCH (80) +#define ROBUST_CHANNEL_VGA_SUBSYSTEM_ERROR (81) +#define ROBUST_CHANNEL_NVJPG0_ERROR (82) +#define ROBUST_CHANNEL_NVDEC1_ERROR (83) +#define ROBUST_CHANNEL_NVDEC2_ERROR (84) +#define ROBUST_CHANNEL_CE9_ERROR (85) +#define ROBUST_CHANNEL_OFA0_ERROR (86) +#define NVTELEMETRY_DRIVER_REPORT (87) +#define ROBUST_CHANNEL_NVDEC3_ERROR (88) +#define ROBUST_CHANNEL_NVDEC4_ERROR (89) +#define LTC_ERROR (90) +#define RESERVED_XID (91) +#define EXCESSIVE_SBE_INTERRUPTS (92) +#define INFOROM_ERASE_LIMIT_EXCEEDED (93) +#define ROBUST_CHANNEL_CONTAINED_ERROR (94) +#define ROBUST_CHANNEL_UNCONTAINED_ERROR (95) +#define ROBUST_CHANNEL_NVDEC5_ERROR (96) +#define ROBUST_CHANNEL_NVDEC6_ERROR (97) +#define ROBUST_CHANNEL_NVDEC7_ERROR (98) +#define ROBUST_CHANNEL_NVJPG1_ERROR (99) +#define ROBUST_CHANNEL_NVJPG2_ERROR (100) +#define ROBUST_CHANNEL_NVJPG3_ERROR (101) +#define ROBUST_CHANNEL_NVJPG4_ERROR (102) +#define ROBUST_CHANNEL_NVJPG5_ERROR (103) +#define ROBUST_CHANNEL_NVJPG6_ERROR (104) +#define ROBUST_CHANNEL_NVJPG7_ERROR (105) +#define NVLINK_REMOTE_TRANSLATION_ERROR (108) +#define SEC_FAULT_ERROR (110) +#define GSP_RPC_TIMEOUT (119) +#define GSP_ERROR (120) +#define C2C_ERROR (121) +#define SPI_PMU_RPC_READ_FAIL (122) +#define SPI_PMU_RPC_WRITE_FAIL (123) +#define SPI_PMU_RPC_ERASE_FAIL (124) +#define INFOROM_FS_ERROR (125) +#define ROBUST_CHANNEL_CE10_ERROR (126) +#define ROBUST_CHANNEL_CE11_ERROR (127) +#define ROBUST_CHANNEL_CE12_ERROR (128) +#define ROBUST_CHANNEL_CE13_ERROR (129) +#define ROBUST_CHANNEL_CE14_ERROR (130) +#define ROBUST_CHANNEL_CE15_ERROR (131) +#define ROBUST_CHANNEL_CE16_ERROR (132) +#define ROBUST_CHANNEL_CE17_ERROR (133) +#define ROBUST_CHANNEL_CE18_ERROR (134) +#define ROBUST_CHANNEL_CE19_ERROR (135) +#define ALI_TRAINING_FAIL (136) +#define NVLINK_PRIV_ERR (137) +#define ROBUST_CHANNEL_DLA_ERROR (138) +#define ROBUST_CHANNEL_OFA1_ERROR (139) +#define UNRECOVERABLE_ECC_ERROR_ESCAPE (140) +#define ROBUST_CHANNEL_FAST_PATH_ERROR (141) +#define ROBUST_CHANNEL_NVENC3_ERROR (142) +#define GPU_INIT_ERROR (143) +#define NVLINK_SAW_ERROR (144) +#define NVLINK_RLW_ERROR (145) +#define NVLINK_TLW_ERROR (146) +#define NVLINK_TREX_ERROR (147) +#define NVLINK_NVLPW_CTRL_ERROR (148) +#define NVLINK_NETIR_ERROR (149) +#define NVLINK_MSE_ERROR (150) +#define ROBUST_CHANNEL_KEY_ROTATION_ERROR (151) +#define RESERVED7_ERROR (152) +#define RESERVED8_ERROR (153) +#define GPU_RECOVERY_ACTION_CHANGED (154) +#define NVLINK_SW_DEFINED_ERROR (155) +#define RESOURCE_RETIREMENT_EVENT (156) +#define RESOURCE_RETIREMENT_FAILURE (157) +#define GPU_FATAL_TIMEOUT (158) +#define ROBUST_CHANNEL_CHI_NON_DATA_ERROR (159) +#define CHANNEL_RETIREMENT_EVENT (160) +#define CHANNEL_RETIREMENT_FAILURE (161) +#define ISINK_REENGAGED (162) +#define ISINK_DISENGAGED (163) +#define ISINK_LOW_LIFETIME (164) +#define ISINK_ZERO_LIFETIME (165) +#define NVLINK_SECURE_NVLE_ERROR (166) +#define PCIE_FATAL_TIMEOUT (167) +#define REDUCED_GPU_MEMORY_CAPACITY (168) +#define SEC2_HALT_ERROR (169) +#define NVLINK_SECURE_ERROR (170) +#define UNCORRECTABLE_DRAM_ERROR (171) +#define UNCORRECTABLE_SRAM_ERROR (172) +#define C2C_FATAL_LINK_FAILURE (173) +#define ROBUST_CHANNEL_RESETCHANNEL_KILL_PROCESS_SILENT (174) +#define MEMORY_SUBSYSTEM_ERROR (175) +#define PCIE_CORRECTABLE_ERROR_FAULT (176) +#define BANK_REMAPPING_EVENT (177) +#define REMOTE_TRANSLATION_POISON_ERROR (178) +#define ROBUST_CHANNEL_LAST_ERROR (178) + +// Indexed CE reference +#define ROBUST_CHANNEL_CE_ERROR(x) \ + ((x < 3) ? \ + (ROBUST_CHANNEL_CE0_ERROR + (x)) : \ + ((x < 6) ? \ + (ROBUST_CHANNEL_CE3_ERROR + (x - 3)) : \ + ((x < 9) ? \ + (ROBUST_CHANNEL_CE6_ERROR + (x - 6)) : \ + ((x == 9) ? \ + (ROBUST_CHANNEL_CE9_ERROR) : \ + (ROBUST_CHANNEL_CE10_ERROR + (x - 10)))))) + +#define ROBUST_CHANNEL_IS_CE_ERROR(x) \ + ((x == ROBUST_CHANNEL_CE0_ERROR) || (x == ROBUST_CHANNEL_CE1_ERROR) || \ + (x == ROBUST_CHANNEL_CE2_ERROR) || (x == ROBUST_CHANNEL_CE3_ERROR) || \ + (x == ROBUST_CHANNEL_CE4_ERROR) || (x == ROBUST_CHANNEL_CE5_ERROR) || \ + (x == ROBUST_CHANNEL_CE6_ERROR) || (x == ROBUST_CHANNEL_CE7_ERROR) || \ + (x == ROBUST_CHANNEL_CE8_ERROR) || (x == ROBUST_CHANNEL_CE9_ERROR) || \ + (x == ROBUST_CHANNEL_CE10_ERROR) || (x == ROBUST_CHANNEL_CE11_ERROR) || \ + (x == ROBUST_CHANNEL_CE12_ERROR) || (x == ROBUST_CHANNEL_CE13_ERROR) || \ + (x == ROBUST_CHANNEL_CE14_ERROR) || (x == ROBUST_CHANNEL_CE15_ERROR) || \ + (x == ROBUST_CHANNEL_CE16_ERROR) || (x == ROBUST_CHANNEL_CE17_ERROR) || \ + (x == ROBUST_CHANNEL_CE18_ERROR) || (x == ROBUST_CHANNEL_CE19_ERROR)) + +#define ROBUST_CHANNEL_CE_ERROR_IDX(x) \ + (((x >= ROBUST_CHANNEL_CE0_ERROR) && (x <= ROBUST_CHANNEL_CE2_ERROR)) ? \ + (x - ROBUST_CHANNEL_CE0_ERROR) : \ + (((x >= ROBUST_CHANNEL_CE3_ERROR) && (x <= ROBUST_CHANNEL_CE5_ERROR)) ? \ + (x - ROBUST_CHANNEL_CE3_ERROR + 3) : \ + (((x >= ROBUST_CHANNEL_CE6_ERROR) && (x <= ROBUST_CHANNEL_CE8_ERROR)) ? \ + (x - ROBUST_CHANNEL_CE6_ERROR + 6) : \ + ((x == ROBUST_CHANNEL_CE9_ERROR) ? \ + (x - ROBUST_CHANNEL_CE9_ERROR + 9) : \ + (x - ROBUST_CHANNEL_CE10_ERROR + 10))))) + +// Indexed NVDEC reference +#define ROBUST_CHANNEL_NVDEC_ERROR(x) \ + ((x < 1) ? \ + (ROBUST_CHANNEL_NVDEC0_ERROR) : \ + ((x < 3) ? \ + (ROBUST_CHANNEL_NVDEC1_ERROR + (x - 1)) : \ + ((x < 5) ? \ + (ROBUST_CHANNEL_NVDEC3_ERROR + (x - 3)): \ + (ROBUST_CHANNEL_NVDEC5_ERROR + (x - 5))))) + +#define ROBUST_CHANNEL_IS_NVDEC_ERROR(x) \ + ((x == ROBUST_CHANNEL_NVDEC0_ERROR) || \ + (x == ROBUST_CHANNEL_NVDEC1_ERROR) || \ + (x == ROBUST_CHANNEL_NVDEC2_ERROR) || \ + (x == ROBUST_CHANNEL_NVDEC3_ERROR) || \ + (x == ROBUST_CHANNEL_NVDEC4_ERROR) || \ + (x == ROBUST_CHANNEL_NVDEC5_ERROR) || \ + (x == ROBUST_CHANNEL_NVDEC6_ERROR) || \ + (x == ROBUST_CHANNEL_NVDEC7_ERROR)) + +#define ROBUST_CHANNEL_NVDEC_ERROR_IDX(x) \ + ((x == ROBUST_CHANNEL_NVDEC0_ERROR) ? \ + (x - ROBUST_CHANNEL_NVDEC0_ERROR) : \ + (((x >= ROBUST_CHANNEL_NVDEC1_ERROR) && (x <= ROBUST_CHANNEL_NVDEC2_ERROR)) ? \ + (x - ROBUST_CHANNEL_NVDEC1_ERROR + 1) : \ + (((x >= ROBUST_CHANNEL_NVDEC3_ERROR) && (x <= ROBUST_CHANNEL_NVDEC4_ERROR)) ? \ + (x - ROBUST_CHANNEL_NVDEC3_ERROR + 3) : \ + (x - ROBUST_CHANNEL_NVDEC5_ERROR + 5)))) + +// Indexed NVENC reference +#define ROBUST_CHANNEL_NVENC_ERROR(x) \ + ((x == 0) ? (ROBUST_CHANNEL_NVENC0_ERROR) : \ + ((x == 1) ? (ROBUST_CHANNEL_NVENC1_ERROR) : \ + ((x == 2) ? (ROBUST_CHANNEL_NVENC2_ERROR) : \ + (ROBUST_CHANNEL_NVENC3_ERROR)))) + +#define ROBUST_CHANNEL_IS_NVENC_ERROR(x) \ + ((x == ROBUST_CHANNEL_NVENC0_ERROR) || \ + (x == ROBUST_CHANNEL_NVENC1_ERROR) || \ + (x == ROBUST_CHANNEL_NVENC2_ERROR) || \ + (x == ROBUST_CHANNEL_NVENC3_ERROR)) + +#define ROBUST_CHANNEL_NVENC_ERROR_IDX(x) \ + ((x == ROBUST_CHANNEL_NVENC0_ERROR) ? \ + (x - ROBUST_CHANNEL_NVENC0_ERROR) : \ + ((x == ROBUST_CHANNEL_NVENC1_ERROR) ? \ + (x - ROBUST_CHANNEL_NVENC1_ERROR + 1) : \ + ((x == ROBUST_CHANNEL_NVENC2_ERROR) ? \ + (x - ROBUST_CHANNEL_NVENC2_ERROR + 2) : \ + (x - ROBUST_CHANNEL_NVENC3_ERROR + 3)))) + +// Indexed NVJPG reference +#define ROBUST_CHANNEL_NVJPG_ERROR(x) \ + ((x < 1) ? \ + (ROBUST_CHANNEL_NVJPG0_ERROR) : \ + (ROBUST_CHANNEL_NVJPG1_ERROR + (x - 1))) + +#define ROBUST_CHANNEL_IS_NVJPG_ERROR(x) \ + ((x == ROBUST_CHANNEL_NVJPG0_ERROR) || \ + (x == ROBUST_CHANNEL_NVJPG1_ERROR) || \ + (x == ROBUST_CHANNEL_NVJPG2_ERROR) || \ + (x == ROBUST_CHANNEL_NVJPG3_ERROR) || \ + (x == ROBUST_CHANNEL_NVJPG4_ERROR) || \ + (x == ROBUST_CHANNEL_NVJPG5_ERROR) || \ + (x == ROBUST_CHANNEL_NVJPG6_ERROR) || \ + (x == ROBUST_CHANNEL_NVJPG7_ERROR)) + +#define ROBUST_CHANNEL_NVJPG_ERROR_IDX(x) \ + ((x == ROBUST_CHANNEL_NVJPG0_ERROR) ? \ + (x - ROBUST_CHANNEL_NVJPG0_ERROR) : \ + (x - ROBUST_CHANNEL_NVJPG1_ERROR + 1)) + +// Indexed OFA reference +#define ROBUST_CHANNEL_OFA_ERROR(x) \ + ((x == 0) ? \ + (ROBUST_CHANNEL_OFA0_ERROR) : \ + (ROBUST_CHANNEL_OFA1_ERROR)) + +#define ROBUST_CHANNEL_IS_OFA_ERROR(x) \ + ((x == ROBUST_CHANNEL_OFA0_ERROR) || \ + (x == ROBUST_CHANNEL_OFA1_ERROR)) + +#define ROBUST_CHANNEL_OFA_ERROR_IDX(x) \ + ((x == ROBUST_CHANNEL_OFA0_ERROR) ? \ + (x - ROBUST_CHANNEL_OFA0_ERROR) : \ + (x - ROBUST_CHANNEL_OFA1_ERROR + 1)) + +// Error Levels +#define ROBUST_CHANNEL_ERROR_RECOVERY_LEVEL_INFO (0) +#define ROBUST_CHANNEL_ERROR_RECOVERY_LEVEL_NON_FATAL (1) +#define ROBUST_CHANNEL_ERROR_RECOVERY_LEVEL_FATAL (2) + +#endif // NVERROR_H diff --git a/userspace/sdks/nv570/inc/nvfixedtypes.h b/userspace/sdks/nv570/inc/nvfixedtypes.h new file mode 100644 index 0000000..3adc779 --- /dev/null +++ b/userspace/sdks/nv570/inc/nvfixedtypes.h @@ -0,0 +1,408 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVFIXEDTYPES_INCLUDED +#define NVFIXEDTYPES_INCLUDED + +#include "nvtypes.h" + +/*! + * Fixed-point master data types. + * + * These are master-types represent the total number of bits contained within + * the FXP type. All FXP types below should be based on one of these master + * types. + */ +typedef NvS16 NvSFXP16; +typedef NvS32 NvSFXP32; +typedef NvS64 NvSFXP64; +typedef NvU8 NvUFXP8; +typedef NvU16 NvUFXP16; +typedef NvU32 NvUFXP32; +typedef NvU64 NvUFXP64; + + +/*! + * Fixed-point data types. + * + * These are all integer types with precision indicated in the naming of the + * form: NvFXP_. The actual + * size of the data type is calculated as num_bits_above_radix + + * num_bit_below_radix. + * + * All of these FXP types should be based on one of the master types above. + */ +typedef NvSFXP16 NvSFXP11_5; +typedef NvSFXP16 NvSFXP4_12; +typedef NvSFXP16 NvSFXP8_8; +typedef NvSFXP32 NvSFXP8_24; +typedef NvSFXP32 NvSFXP10_22; +typedef NvSFXP32 NvSFXP16_16; +typedef NvSFXP32 NvSFXP18_14; +typedef NvSFXP32 NvSFXP20_12; +typedef NvSFXP32 NvSFXP24_8; +typedef NvSFXP32 NvSFXP27_5; +typedef NvSFXP32 NvSFXP28_4; +typedef NvSFXP32 NvSFXP29_3; +typedef NvSFXP32 NvSFXP31_1; +typedef NvSFXP64 NvSFXP52_12; + +typedef NvUFXP8 NvUFXP0_8; +typedef NvUFXP16 NvUFXP0_16; +typedef NvUFXP16 NvUFXP4_12; +typedef NvUFXP16 NvUFXP8_8; +typedef NvUFXP32 NvUFXP3_29; +typedef NvUFXP32 NvUFXP4_28; +typedef NvUFXP32 NvUFXP7_25; +typedef NvUFXP32 NvUFXP8_24; +typedef NvUFXP32 NvUFXP9_23; +typedef NvUFXP32 NvUFXP10_22; +typedef NvUFXP32 NvUFXP15_17; +typedef NvUFXP32 NvUFXP16_16; +typedef NvUFXP32 NvUFXP18_14; +typedef NvUFXP32 NvUFXP20_12; +typedef NvUFXP32 NvUFXP24_8; +typedef NvUFXP32 NvUFXP25_7; +typedef NvUFXP32 NvUFXP26_6; +typedef NvUFXP32 NvUFXP28_4; + +typedef NvUFXP64 NvUFXP37_27; +typedef NvUFXP64 NvUFXP40_24; +typedef NvUFXP64 NvUFXP48_16; +typedef NvUFXP64 NvUFXP52_12; +typedef NvUFXP64 NvUFXP54_10; +typedef NvUFXP64 NvUFXP60_4; +typedef NvUFXP64 NvUFXP36_28; +/*! + * Utility macros used in converting between signed integers and fixed-point + * notation. + * + * - COMMON - These are used by both signed and unsigned. + */ +#define NV_TYPES_FXP_INTEGER(x, y) ((x)+(y)-1):(y) +#define NV_TYPES_FXP_FRACTIONAL(x, y) ((y)-1):0 +#define NV_TYPES_FXP_FRACTIONAL_MSB(x, y) ((y)-1):((y)-1) +#define NV_TYPES_FXP_FRACTIONAL_MSB_ONE 0x00000001 +#define NV_TYPES_FXP_FRACTIONAL_MSB_ZERO 0x00000000 +#define NV_TYPES_FXP_ZERO (0) + +/*! + * - UNSIGNED - These are only used for unsigned. + */ +#define NV_TYPES_UFXP_INTEGER_MAX(x, y) (~(NVBIT((y))-1U)) +#define NV_TYPES_UFXP_INTEGER_MIN(x, y) (0U) + +/*! + * - SIGNED - These are only used for signed. + */ +#define NV_TYPES_SFXP_INTEGER_SIGN(x, y) ((x)+(y)-1):((x)+(y)-1) +#define NV_TYPES_SFXP_INTEGER_SIGN_NEGATIVE 0x00000001 +#define NV_TYPES_SFXP_INTEGER_SIGN_POSITIVE 0x00000000 +#define NV_TYPES_SFXP_S32_SIGN_EXTENSION(x, y) 31:(x) +#define NV_TYPES_SFXP_S32_SIGN_EXTENSION_POSITIVE(x, y) 0x00000000 +#define NV_TYPES_SFXP_S32_SIGN_EXTENSION_NEGATIVE(x, y) (NVBIT(32-(x))-1U) +#define NV_TYPES_SFXP_INTEGER_MAX(x, y) (NVBIT((x))-1U) +#define NV_TYPES_SFXP_INTEGER_MIN(x, y) (~(NVBIT((x))-1U)) +#define NV_TYPES_SFXP_S64_SIGN_EXTENSION(x, y) 63:(x) +#define NV_TYPES_SFXP_S64_SIGN_EXTENSION_POSITIVE(x, y) 0x0000000000000000 +#define NV_TYPES_SFXP_S64_SIGN_EXTENSION_NEGATIVE(x, y) (NVBIT64(64-(x))-1U) +#define NV_TYPES_SFXP_S64_INTEGER_MAX(x, y) (NVBIT64((x)-1)-1U) +#define NV_TYPES_SFXP_S64_INTEGER_MIN(x, y) (~(NVBIT64((x)-1)-1U)) + +/*! + * Conversion macros used for converting between integer and fixed point + * representations. Both signed and unsigned variants. + * + * Warning: + * Note that most of the macros below can overflow if applied on values that can + * not fit the destination type. It's caller responsibility to ensure that such + * situations will not occur. + * + * Some conversions perform some commonly performed tasks other than just + * bit-shifting: + * + * - _SCALED: + * For integer -> fixed-point we add handling divisors to represent + * non-integer values. + * + * - _ROUNDED: + * For fixed-point -> integer we add rounding to integer values. + */ + +// 32-bit Unsigned FXP: +#define NV_TYPES_U32_TO_UFXP_X_Y(x, y, integer) \ + ((NvUFXP##x##_##y) (((NvU32) (integer)) << \ + DRF_SHIFT(NV_TYPES_FXP_INTEGER((x), (y))))) + +#define NV_TYPES_U32_TO_UFXP_X_Y_SCALED(x, y, integer, scale) \ + ((NvUFXP##x##_##y) ((((((NvU32) (integer)) << \ + DRF_SHIFT(NV_TYPES_FXP_INTEGER((x), (y))))) / \ + (scale)) + \ + ((((((NvU32) (integer)) << \ + DRF_SHIFT(NV_TYPES_FXP_INTEGER((x), (y)))) % \ + (scale)) > ((scale) >> 1)) ? 1U : 0U))) + +#define NV_TYPES_UFXP_X_Y_TO_U32(x, y, fxp) \ + ((NvU32) (DRF_VAL(_TYPES, _FXP, _INTEGER((x), (y)), \ + ((NvUFXP##x##_##y) (fxp))))) + +#define NV_TYPES_UFXP_X_Y_TO_U32_ROUNDED(x, y, fxp) \ + (NV_TYPES_UFXP_X_Y_TO_U32(x, y, (fxp)) + \ + (FLD_TEST_DRF_NUM(_TYPES, _FXP, _FRACTIONAL_MSB((x), (y)), \ + NV_TYPES_FXP_FRACTIONAL_MSB_ONE, ((NvUFXP##x##_##y) (fxp))) ? \ + 1U : 0U)) + +// 64-bit Unsigned FXP +#define NV_TYPES_U64_TO_UFXP_X_Y(x, y, integer) \ + ((NvUFXP##x##_##y) (((NvU64) (integer)) << \ + DRF_SHIFT64(NV_TYPES_FXP_INTEGER((x), (y))))) + +#define NV_TYPES_U64_TO_UFXP_X_Y_SCALED(x, y, integer, scale) \ + ((NvUFXP##x##_##y) (((((NvU64) (integer)) << \ + DRF_SHIFT64(NV_TYPES_FXP_INTEGER((x), (y)))) + \ + ((scale) >> 1)) / \ + (scale))) + +#define NV_TYPES_UFXP_X_Y_TO_U64(x, y, fxp) \ + ((NvU64) (DRF_VAL64(_TYPES, _FXP, _INTEGER((x), (y)), \ + ((NvUFXP##x##_##y) (fxp))))) + +#define NV_TYPES_UFXP_X_Y_TO_U64_ROUNDED(x, y, fxp) \ + (NV_TYPES_UFXP_X_Y_TO_U64(x, y, (fxp)) + \ + (FLD_TEST_DRF_NUM64(_TYPES, _FXP, _FRACTIONAL_MSB((x), (y)), \ + NV_TYPES_FXP_FRACTIONAL_MSB_ONE, ((NvUFXP##x##_##y) (fxp))) ? \ + 1U : 0U)) + +// +// 32-bit Signed FXP: +// Some compilers do not support left shift negative values +// so typecast integer to NvU32 instead of NvS32 +// +// Note that there is an issue with the rounding in +// NV_TYPES_S32_TO_SFXP_X_Y_SCALED. In particular, when the signs of the +// numerator and denominator don't match, the rounding is done towards positive +// infinity, rather than away from 0. This will need to be fixed in a follow-up +// change. +// +#define NV_TYPES_S32_TO_SFXP_X_Y(x, y, integer) \ + ((NvSFXP##x##_##y) (((NvU32) (integer)) << \ + DRF_SHIFT(NV_TYPES_FXP_INTEGER((x), (y))))) + +#define NV_TYPES_S32_TO_SFXP_X_Y_SCALED(x, y, integer, scale) \ + ((NvSFXP##x##_##y) (((((NvS32) (integer)) << \ + DRF_SHIFT(NV_TYPES_FXP_INTEGER((x), (y)))) + \ + ((scale) >> 1)) / \ + (scale))) + +#define NV_TYPES_SFXP_X_Y_TO_S32(x, y, fxp) \ + ((NvS32) ((DRF_VAL(_TYPES, _FXP, _INTEGER((x), (y)), \ + ((NvSFXP##x##_##y) (fxp)))) | \ + ((DRF_VAL(_TYPES, _SFXP, _INTEGER_SIGN((x), (y)), (fxp)) == \ + NV_TYPES_SFXP_INTEGER_SIGN_NEGATIVE) ? \ + DRF_NUM(_TYPES, _SFXP, _S32_SIGN_EXTENSION((x), (y)), \ + NV_TYPES_SFXP_S32_SIGN_EXTENSION_NEGATIVE((x), (y))) : \ + DRF_NUM(_TYPES, _SFXP, _S32_SIGN_EXTENSION((x), (y)), \ + NV_TYPES_SFXP_S32_SIGN_EXTENSION_POSITIVE((x), (y)))))) + +/*! + * Note: The rounding action for signed numbers should ideally round away from + * 0 in both the positive and the negative regions. + * For positive numbers, we add 1 if the fractional MSb is 1. + * For negative numbers, we add -1 (equivalent to subtracting 1) if the + * fractional MSb is 1. + */ +#define NV_TYPES_SFXP_X_Y_TO_S32_ROUNDED(x, y, fxp) \ + (NV_TYPES_SFXP_X_Y_TO_S32(x, y, (fxp)) + \ + (FLD_TEST_DRF_NUM(_TYPES, _FXP, _FRACTIONAL_MSB((x), (y)), \ + NV_TYPES_FXP_FRACTIONAL_MSB_ONE, ((NvSFXP##x##_##y) (fxp))) ? \ + ((DRF_VAL(_TYPES, _SFXP, _INTEGER_SIGN((x), (y)), (fxp)) == \ + NV_TYPES_SFXP_INTEGER_SIGN_POSITIVE) ? 1 : -1) : 0)) + +#define NV_TYPES_SFXP_X_Y_TO_FLOAT32(x, y, fxp) \ + ((NvF32) NV_TYPES_SFXP_X_Y_TO_S32(x, y, (fxp)) + \ + ((NvF32) DRF_NUM(_TYPES, _FXP, _FRACTIONAL((x), (y)), \ + ((NvSFXP##x##_##y) (fxp))) / (NvF32) (1 << (y)))) + +// +// 64-bit Signed FXP: +// Some compilers do not support left shift negative values +// so typecast integer to NvU64 instead of NvS64 +// +// Note that there is an issue with the rounding in +// NV_TYPES_S64_TO_SFXP_X_Y_SCALED. In particular, when the signs of the +// numerator and denominator don't match, the rounding is done towards positive +// infinity, rather than away from 0. This will need to be fixed in a follow-up +// change. +// +#define NV_TYPES_S64_TO_SFXP_X_Y(x, y, integer) \ + ((NvSFXP##x##_##y) (((NvU64) (integer)) << \ + DRF_SHIFT64(NV_TYPES_FXP_INTEGER((x), (y))))) + +#define NV_TYPES_S64_TO_SFXP_X_Y_SCALED(x, y, integer, scale) \ + ((NvSFXP##x##_##y) (((((NvS64) (integer)) << \ + DRF_SHIFT64(NV_TYPES_FXP_INTEGER((x), (y)))) + \ + ((scale) >> 1)) / \ + (scale))) + +#define NV_TYPES_SFXP_X_Y_TO_S64(x, y, fxp) \ + ((NvS64) ((DRF_VAL64(_TYPES, _FXP, _INTEGER((x), (y)), \ + ((NvSFXP##x##_##y) (fxp)))) | \ + ((DRF_VAL64(_TYPES, _SFXP, _INTEGER_SIGN((x), (y)), (fxp)) == \ + NV_TYPES_SFXP_INTEGER_SIGN_NEGATIVE) ? \ + DRF_NUM64(_TYPES, _SFXP, _S64_SIGN_EXTENSION((x), (y)), \ + NV_TYPES_SFXP_S64_SIGN_EXTENSION_NEGATIVE((x), (y))) : \ + DRF_NUM64(_TYPES, _SFXP, _S64_SIGN_EXTENSION((x), (y)), \ + NV_TYPES_SFXP_S64_SIGN_EXTENSION_POSITIVE((x), (y)))))) + +/*! + * Note: The rounding action for signed numbers should ideally round away from + * 0 in both the positive and the negative regions. + * For positive numbers, we add 1 if the fractional MSb is 1. + * For negative numbers, we add -1 (equivalent to subtracting 1) if the + * fractional MSb is 1. + */ +#define NV_TYPES_SFXP_X_Y_TO_S64_ROUNDED(x, y, fxp) \ + (NV_TYPES_SFXP_X_Y_TO_S64(x, y, (fxp)) + \ + (FLD_TEST_DRF_NUM64(_TYPES, _FXP, _FRACTIONAL_MSB((x), (y)), \ + NV_TYPES_FXP_FRACTIONAL_MSB_ONE, ((NvSFXP##x##_##y) (fxp))) ? \ + ((DRF_VAL64(_TYPES, _SFXP, _INTEGER_SIGN((x), (y)), (fxp)) == \ + NV_TYPES_SFXP_INTEGER_SIGN_POSITIVE) ? 1 : -1) : 0)) + +/*! + * Macros representing the single-precision IEEE 754 floating point format for + * "binary32", also known as "single" and "float". + * + * Single precision floating point format wiki [1] + * + * _SIGN + * Single bit representing the sign of the number. + * _EXPONENT + * Unsigned 8-bit number representing the exponent value by which to scale + * the mantissa. + * _BIAS - The value by which to offset the exponent to account for sign. + * _MANTISSA + * Explicit 23-bit significand of the value. When exponent != 0, this is an + * implicitly 24-bit number with a leading 1 prepended. This 24-bit number + * can be conceptualized as FXP 9.23. + * + * With these definitions, the value of a floating point number can be + * calculated as: + * (-1)^(_SIGN) * + * 2^(_EXPONENT - _EXPONENT_BIAS) * + * (1 + _MANTISSA / (1 << 23)) + */ +// [1] : https://en.wikipedia.org/wiki/Single_precision_floating-point_format +#define NV_TYPES_SINGLE_SIGN 31:31 +#define NV_TYPES_SINGLE_SIGN_POSITIVE 0x00000000 +#define NV_TYPES_SINGLE_SIGN_NEGATIVE 0x00000001 +#define NV_TYPES_SINGLE_EXPONENT 30:23 +#define NV_TYPES_SINGLE_EXPONENT_ZERO 0x00000000 +#define NV_TYPES_SINGLE_EXPONENT_MAX 0x000000FE +#define NV_TYPES_SINGLE_EXPONENT_BIAS 0x0000007F +#define NV_TYPES_SINGLE_MANTISSA 22:0 + + +/*! + * Helper macro to return a IEEE 754 single-precision value's mantissa as an + * unsigned FXP 9.23 value. + * + * @param[in] single IEEE 754 single-precision value to manipulate. + * + * @return IEEE 754 single-precision values mantissa represented as an unsigned + * FXP 9.23 value. + */ +#define NV_TYPES_SINGLE_MANTISSA_TO_UFXP9_23(single) \ + ((NvUFXP9_23)(FLD_TEST_DRF(_TYPES, _SINGLE, _EXPONENT, _ZERO, single) ? \ + NV_TYPES_U32_TO_UFXP_X_Y(9, 23, 0) : \ + (NV_TYPES_U32_TO_UFXP_X_Y(9, 23, 1) + \ + DRF_VAL(_TYPES, _SINGLE, _MANTISSA, single)))) + +/*! + * Helper macro to return an IEEE 754 single-precision value's exponent, + * including the bias. + * + * @param[in] single IEEE 754 single-precision value to manipulate. + * + * @return Signed exponent value for IEEE 754 single-precision. + */ +#define NV_TYPES_SINGLE_EXPONENT_BIASED(single) \ + ((NvS32)(DRF_VAL(_TYPES, _SINGLE, _EXPONENT, single) - \ + NV_TYPES_SINGLE_EXPONENT_BIAS)) + +/*! + * Helper macro to convert an NvS8 unbiased exponent value to an IEEE 754 + * single-precision value's exponent, by adding the bias. + * Input exponent can range from -127 to 127 which is stored in the range + * [0, 254] + * + * @param[in] single IEEE 754 single-precision value to manipulate. + * + * @return Biased exponent value for IEEE 754 single-precision. + */ +#define NV_TYPES_NvS32_TO_SINGLE_EXPONENT_BIASED(exponent) \ + ((NvU32)((exponent) + NV_TYPES_SINGLE_EXPONENT_BIAS)) + +/*! + * NvTemp - temperature data type introduced to avoid bugs in conversion between + * various existing notations. + */ +typedef NvSFXP24_8 NvTemp; + +/*! + * Macros for NvType <-> Celsius temperature conversion. + */ +#define NV_TYPES_CELSIUS_TO_NV_TEMP(cel) \ + NV_TYPES_S32_TO_SFXP_X_Y(24,8,(cel)) +#define NV_TYPES_NV_TEMP_TO_CELSIUS_TRUNCED(nvt) \ + NV_TYPES_SFXP_X_Y_TO_S32(24,8,(nvt)) +#define NV_TYPES_NV_TEMP_TO_CELSIUS_ROUNDED(nvt) \ + NV_TYPES_SFXP_X_Y_TO_S32_ROUNDED(24,8,(nvt)) +#define NV_TYPES_NV_TEMP_TO_CELSIUS_FLOAT(nvt) \ + NV_TYPES_SFXP_X_Y_TO_FLOAT32(24,8,(nvt)) + +/*! + * Macro for NvType -> number of bits conversion + */ +#define NV_NBITS_IN_TYPE(type) (8 * sizeof(type)) + +/*! + * Macro to convert SFXP 11.5 to NvTemp. + */ +#define NV_TYPES_NVSFXP11_5_TO_NV_TEMP(x) ((NvTemp)(x) << 3) + +/*! + * Macro to convert NvTemp to SFXP 11.5. + */ +#define NV_TYPES_NV_TEMP_TO_NVSFXP11_5(x) ((NvSFXP11_5)(x) >> 3) + +/*! + * Macro to convert UFXP 5.3 to NvTemp. + */ +#define NV_TYPES_NVUFXP5_3_TO_NV_TEMP(x) ((NvTemp)(x) << 5) + +/*! + * Macro to convert UFXP11.5 Watts to NvU32 milli-Watts. + */ +#define NV_TYPES_NVUFXP11_5_WATTS_TO_NVU32_MILLI_WATTS(x) ((((NvU32)(x)) * ((NvU32)1000)) >> 5) + +#endif /* NVFIXEDTYPES_INCLUDED */ diff --git a/userspace/sdks/nv570/inc/nvgputypes.h b/userspace/sdks/nv570/inc/nvgputypes.h new file mode 100644 index 0000000..d018414 --- /dev/null +++ b/userspace/sdks/nv570/inc/nvgputypes.h @@ -0,0 +1,177 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2006 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + + /***************************************************************************\ +|* *| +|* NV GPU Types *| +|* *| +|* This header contains definitions describing NVIDIA's GPU hardware state. *| +|* *| + \***************************************************************************/ + + +#ifndef NVGPUTYPES_INCLUDED +#define NVGPUTYPES_INCLUDED +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + + /***************************************************************************\ +|* NvNotification *| + \***************************************************************************/ + +/***** NvNotification Structure *****/ +/* + * NV objects return information about method completion to clients via an + * array of notification structures in main memory. + * + * The client sets the status field to NV???_NOTIFICATION_STATUS_IN_PROGRESS. + * NV fills in the NvNotification[] data structure in the following order: + * timeStamp, otherInfo32, otherInfo16, and then status. + */ + +/* memory data structures */ +typedef volatile struct NvNotificationRec { + struct { /* 0000- */ + NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/ + } timeStamp; /* -0007*/ + NvV32 info32; /* info returned depends on method 0008-000b*/ + NvV16 info16; /* info returned depends on method 000c-000d*/ + NvV16 status; /* user sets bit 15, NV sets status 000e-000f*/ +} NvNotification; + + /***************************************************************************\ +|* NvGpuSemaphore *| + \***************************************************************************/ + +/***** NvGpuSemaphore Structure *****/ +/* + * NvGpuSemaphore objects are used by the GPU to synchronize multiple + * command-streams. + * + * Please refer to class documentation for details regarding the content of + * the data[] field. + */ + +/* memory data structures */ +typedef volatile struct NvGpuSemaphoreRec { + NvV32 data[2]; /* Payload/Report data 0000-0007*/ + struct { /* 0008- */ + NvV32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 8- f*/ + } timeStamp; /* -000f*/ +} NvGpuSemaphore; + + /***************************************************************************\ +|* NvGetReport *| + \***************************************************************************/ + +/* + * NV objects, starting with Kelvin, return information such as pixel counts to + * the user via the NV*_GET_REPORT method. + * + * The client fills in the "zero" field to any nonzero value and waits until it + * becomes zero. NV fills in the timeStamp, value, and zero fields. + */ +typedef volatile struct NVGetReportRec { + struct { /* 0000- */ + NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/ + } timeStamp; /* -0007*/ + NvU32 value; /* info returned depends on method 0008-000b*/ + NvU32 zero; /* always written to zero 000c-000f*/ +} NvGetReport; + + /***************************************************************************\ +|* NvRcNotification *| + \***************************************************************************/ + +/* + * NV robust channel notification information is reported to clients via + * standard NV01_EVENT objects bound to instance of the NV*_CHANNEL_DMA and + * NV*_CHANNEL_GPFIFO objects. + */ +typedef struct NvRcNotificationRec { + struct { + NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/ + } timeStamp; /* -0007*/ + NvU32 exceptLevel; /* exception level 000c-000f*/ + NvU32 exceptType; /* exception type 0010-0013*/ +} NvRcNotification; + + /***************************************************************************\ +|* NvSyncPointFence *| + \***************************************************************************/ + +/***** NvSyncPointFence Structure *****/ +/* + * NvSyncPointFence objects represent a syncpoint event. The syncPointID + * identifies the syncpoint register and the value is the value that the + * register will contain right after the event occurs. + * + * If syncPointID contains NV_INVALID_SYNCPOINT_ID then this is an invalid + * event. This is often used to indicate an event in the past (i.e. no need to + * wait). + * + * For more info on syncpoints refer to Mobile channel and syncpoint + * documentation. + */ +typedef struct NvSyncPointFenceRec { + NvU32 syncPointID; + NvU32 value; +} NvSyncPointFence; + +#define NV_INVALID_SYNCPOINT_ID ((NvU32)-1) + + /***************************************************************************\ +|* *| +|* 64 bit type definitions for use in interface structures. *| +|* *| + \***************************************************************************/ + +typedef NvU64 NvOffset; /* GPU address */ + +#define NvOffset_HI32(n) ((NvU32)(((NvU64)(n)) >> 32)) +#define NvOffset_LO32(n) ((NvU32)((NvU64)(n))) + +/* +* There are two types of GPU-UUIDs available: +* +* (1) a SHA-256 based 32 byte ID, formatted as a 64 character +* hexadecimal string as "GPU-%16x-%08x-%08x-%08x-%024x"; this is +* deprecated. +* +* (2) a SHA-1 based 16 byte ID, formatted as a 32 character +* hexadecimal string as "GPU-%08x-%04x-%04x-%04x-%012x" (the +* canonical format of a UUID); this is the default. +*/ +#define NV_GPU_UUID_SHA1_LEN (16) +#define NV_GPU_UUID_SHA256_LEN (32) +#define NV_GPU_UUID_LEN NV_GPU_UUID_SHA1_LEN + +#ifdef __cplusplus +}; +#endif + +#endif /* NVGPUTYPES_INCLUDED */ diff --git a/userspace/sdks/nv570/inc/nvi2c.h b/userspace/sdks/nv570/inc/nvi2c.h new file mode 100644 index 0000000..28c1ba5 --- /dev/null +++ b/userspace/sdks/nv570/inc/nvi2c.h @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef _NV_I2C_H_ +#define _NV_I2C_H_ + +#define NV_I2C_MSG_WR 0x0000 +#define NV_I2C_MSG_RD 0x0001 + +typedef struct nv_i2c_msg_s +{ + NvU16 addr; + NvU16 flags; + NvU16 len; + NvU8* buf; +} nv_i2c_msg_t; + +#endif diff --git a/userspace/sdks/nv570/inc/nvimpshared.h b/userspace/sdks/nv570/inc/nvimpshared.h new file mode 100644 index 0000000..7b821ff --- /dev/null +++ b/userspace/sdks/nv570/inc/nvimpshared.h @@ -0,0 +1,93 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/******************************************************************************\ +* * +* Description: * +* Accommodates sharing of IMP-related structures between kernel interface * +* files and core RM. * +* * +\******************************************************************************/ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: nvimpshared.finn +// + + + + +// +// There are only a small number of discrete dramclk frequencies available on +// the system. This structure contains IMP-relevant information associated +// with a specific dramclk frequency. +// +typedef struct DRAM_CLK_INSTANCE { + NvU32 dram_clk_freq_khz; + + NvU32 mchub_clk_khz; + + NvU32 mc_clk_khz; + + NvU32 max_iso_bw_kbps; + + // + // switch_latency_ns is the maximum time required to switch the dramclk + // frequency to the frequency specified in dram_clk_freq_khz. + // + NvU32 switch_latency_ns; +} DRAM_CLK_INSTANCE; + +// +// This table is used to collect information from other modules that is needed +// for RM IMP calculations. (Used on Tegra only.) +// +typedef struct TEGRA_IMP_IMPORT_DATA { + // + // max_iso_bw_kbps stores the maximum possible ISO bandwidth available to + // display, assuming display is the only active ISO client. (Note that ISO + // bandwidth will typically be allocated to multiple clients, so display + // will generally not have access to the maximum possible bandwidth.) + // + NvU32 max_iso_bw_kbps; + + // On Orin, each dram channel is 16 bits wide. + NvU32 num_dram_channels; + + // + // dram_clk_instance stores entries for all possible dramclk frequencies, + // sorted by dramclk frequency in increasing order. + // + // "24" is expected to be larger than the actual number of required entries + // (which is provided by a BPMP API), but it can be increased if necessary. + // + // num_dram_clk_entries is filled in with the actual number of distinct + // dramclk entries. + // + NvU32 num_dram_clk_entries; + DRAM_CLK_INSTANCE dram_clk_instance[24]; +} TEGRA_IMP_IMPORT_DATA; diff --git a/userspace/sdks/nv570/inc/nvlimits.h b/userspace/sdks/nv570/inc/nvlimits.h new file mode 100644 index 0000000..e7fad3f --- /dev/null +++ b/userspace/sdks/nv570/inc/nvlimits.h @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: nvlimits.finn +// + + + + +/* + * This is the maximum number of GPUs supported in a single system. + */ +#define NV_MAX_DEVICES 32 + +/* + * This is the maximum number of subdevices within a single device. + */ +#define NV_MAX_SUBDEVICES 8 + +/* + * This is the maximum length of the process name string. + */ +#define NV_PROC_NAME_MAX_LENGTH 100U + +/* + * This is the maximum number of heads per GPU. + */ +#define NV_MAX_HEADS 4 + +/* + * Maximum length of a MIG device UUID. It is a 36-byte UUID string plus a + * 4-byte prefix and NUL terminator: 'M' 'I' 'G' '-' UUID '\0x0' + */ +#define NV_MIG_DEVICE_UUID_STR_LENGTH 41U diff --git a/userspace/sdks/nv570/inc/nvmisc.h b/userspace/sdks/nv570/inc/nvmisc.h new file mode 100644 index 0000000..974a257 --- /dev/null +++ b/userspace/sdks/nv570/inc/nvmisc.h @@ -0,0 +1,1148 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * nvmisc.h + */ +#ifndef __NV_MISC_H +#define __NV_MISC_H + +#if !defined(NVRISCV_LIBFSP_BUILD) || !NVRISCV_LIBFSP_BUILD + +#ifdef __cplusplus +extern "C" { +#endif //__cplusplus + +#include "nvtypes.h" + +// Miscellaneous macros useful for bit field manipulations. +#ifndef NVBIT +#define NVBIT(b) (1U<<(b)) +#endif +#ifndef NVBIT_TYPE +#define NVBIT_TYPE(b, t) (((t)1U)<<(b)) +#endif +#ifndef NVBIT32 +#define NVBIT32(b) NVBIT_TYPE(b, NvU32) +#endif +#ifndef NVBIT64 +#define NVBIT64(b) NVBIT_TYPE(b, NvU64) +#endif + +//Concatenate 2 32bit values to a 64bit value +#define NV_CONCAT_32_TO_64(hi, lo) ((((NvU64)hi) << 32) | ((NvU64)lo)) + +// Helper macro's for 32 bit bitmasks +#define NV_BITMASK32_ELEMENT_SIZE (sizeof(NvU32) << 3) +#define NV_BITMASK32_IDX(chId) (((chId) & ~(0x1F)) >> 5) +#define NV_BITMASK32_OFFSET(chId) ((chId) & (0x1F)) +#define NV_BITMASK32_SET(pChannelMask, chId) \ + (pChannelMask)[NV_BITMASK32_IDX(chId)] |= NVBIT(NV_BITMASK32_OFFSET(chId)) +#define NV_BITMASK32_GET(pChannelMask, chId) \ + ((pChannelMask)[NV_BITMASK32_IDX(chId)] & NVBIT(NV_BITMASK32_OFFSET(chId))) + + +// Index of the 'on' bit (assuming that there is only one). +// Even if multiple bits are 'on', result is in range of 0-31. +#define BIT_IDX_32(n) \ + (((((n) & 0xFFFF0000U) != 0U) ? 0x10U: 0U) | \ + ((((n) & 0xFF00FF00U) != 0U) ? 0x08U: 0U) | \ + ((((n) & 0xF0F0F0F0U) != 0U) ? 0x04U: 0U) | \ + ((((n) & 0xCCCCCCCCU) != 0U) ? 0x02U: 0U) | \ + ((((n) & 0xAAAAAAAAU) != 0U) ? 0x01U: 0U) ) + +// Index of the 'on' bit (assuming that there is only one). +// Even if multiple bits are 'on', result is in range of 0-63. +#define BIT_IDX_64(n) \ + (((((n) & 0xFFFFFFFF00000000ULL) != 0U) ? 0x20U: 0U) | \ + ((((n) & 0xFFFF0000FFFF0000ULL) != 0U) ? 0x10U: 0U) | \ + ((((n) & 0xFF00FF00FF00FF00ULL) != 0U) ? 0x08U: 0U) | \ + ((((n) & 0xF0F0F0F0F0F0F0F0ULL) != 0U) ? 0x04U: 0U) | \ + ((((n) & 0xCCCCCCCCCCCCCCCCULL) != 0U) ? 0x02U: 0U) | \ + ((((n) & 0xAAAAAAAAAAAAAAAAULL) != 0U) ? 0x01U: 0U) ) + +/*! + * DRF MACRO README: + * + * Glossary: + * DRF: Device, Register, Field + * FLD: Field + * REF: Reference + * + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA 0xDEADBEEF + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_GAMMA 27:0 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA 31:28 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_ZERO 0x00000000 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_ONE 0x00000001 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_TWO 0x00000002 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_THREE 0x00000003 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_FOUR 0x00000004 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_FIVE 0x00000005 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_SIX 0x00000006 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_SEVEN 0x00000007 + * + * + * Device = _DEVICE_OMEGA + * This is the common "base" that a group of registers in a manual share + * + * Register = _REGISTER_ALPHA + * Register for a given block of defines is the common root for one or more fields and constants + * + * Field(s) = _FIELD_GAMMA, _FIELD_ZETA + * These are the bit ranges for a given field within the register + * Fields are not required to have defined constant values (enumerations) + * + * Constant(s) = _ZERO, _ONE, _TWO, ... + * These are named values (enums) a field can contain; the width of the constants should not be larger than the field width + * + * MACROS: + * + * DRF_SHIFT: + * Bit index of the lower bound of a field + * DRF_SHIFT(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 28 + * + * DRF_SHIFT_RT: + * Bit index of the higher bound of a field + * DRF_SHIFT_RT(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 31 + * + * DRF_MASK: + * Produces a mask of 1-s equal to the width of a field + * DRF_MASK(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 0xF (four 1s starting at bit 0) + * + * DRF_SHIFTMASK: + * Produces a mask of 1s equal to the width of a field at the location of the field + * DRF_SHIFTMASK(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 0xF0000000 + * + * DRF_DEF: + * Shifts a field constant's value to the correct field offset + * DRF_DEF(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, _THREE) == 0x30000000 + * + * DRF_NUM: + * Shifts a number to the location of a particular field + * DRF_NUM(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, 3) == 0x30000000 + * NOTE: If the value passed in is wider than the field, the value's high bits will be truncated + * + * DRF_SIZE: + * Provides the width of the field in bits + * DRF_SIZE(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 4 + * + * DRF_VAL: + * Provides the value of an input within the field specified + * DRF_VAL(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, 0xABCD1234) == 0xA + * This is sort of like the inverse of DRF_NUM + * + * DRF_IDX...: + * These macros are similar to the above but for fields that accept an index argumment + * + * FLD_SET_DRF: + * Set the field bits in a given value with the given field constant + * NvU32 x = 0x00001234; + * x = FLD_SET_DRF(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, _THREE, x); + * x == 0x30001234; + * + * FLD_SET_DRF_NUM: + * Same as FLD_SET_DRF but instead of using a field constant a literal/variable is passed in + * NvU32 x = 0x00001234; + * x = FLD_SET_DRF_NUM(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, 0xF, x); + * x == 0xF0001234; + * + * FLD_IDX...: + * These macros are similar to the above but for fields that accept an index argumment + * + * FLD_TEST_DRF: + * Test if location specified by drf in 'v' has the same value as NV_drfc + * FLD_TEST_DRF(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, _THREE, 0x3000ABCD) == NV_TRUE + * + * FLD_TEST_DRF_NUM: + * Test if locations specified by drf in 'v' have the same value as n + * FLD_TEST_DRF_NUM(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, 0x3, 0x3000ABCD) == NV_TRUE + * + * REF_DEF: + * Like DRF_DEF but maintains full symbol name (use in cases where "NV" is not prefixed to the field) + * REF_DEF(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, _THREE) == 0x30000000 + * + * REF_VAL: + * Like DRF_VAL but maintains full symbol name (use in cases where "NV" is not prefixed to the field) + * REF_VAL(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, 0xABCD1234) == 0xA + * + * REF_NUM: + * Like DRF_NUM but maintains full symbol name (use in cases where "NV" is not prefixed to the field) + * REF_NUM(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, 0xA) == 0xA00000000 + * + * FLD_SET_REF_NUM: + * Like FLD_SET_DRF_NUM but maintains full symbol name (use in cases where "NV" is not prefixed to the field) + * NvU32 x = 0x00001234; + * x = FLD_SET_REF_NUM(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, 0xF, x); + * x == 0xF0001234; + * + * FLD_TEST_REF: + * Like FLD_TEST_DRF but maintains full symbol name (use in cases where "NV" is not prefixed to the field) + * FLD_TEST_REF(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, _THREE, 0x3000ABCD) == NV_TRUE + * + * Other macros: + * There a plethora of other macros below that extend the above (notably Multi-Word (MW), 64-bit, and some + * reg read/write variations). I hope these are self explanatory. If you have a need to use them, you + * probably have some knowledge of how they work. + */ + +// tegra mobile uses nvmisc_macros.h and can't access nvmisc.h... and sometimes both get included. +#ifndef _NVMISC_MACROS_H +// Use Coverity Annotation to mark issues as false positives/ignore when using single bit defines. +#define DRF_ISBIT(bitval,drf) \ + ( /* coverity[identical_branches] */ \ + (bitval != 0) ? drf ) +#define DEVICE_BASE(d) (0?d) // what's up with this name? totally non-parallel to the macros below +#define DEVICE_EXTENT(d) (1?d) // what's up with this name? totally non-parallel to the macros below +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +#ifdef MISRA_14_3 +#define DRF_BASE(drf) (drf##_LOW_FIELD) +#define DRF_EXTENT(drf) (drf##_HIGH_FIELD) +#define DRF_SHIFT(drf) ((drf##_LOW_FIELD) % 32U) +#define DRF_SHIFT_RT(drf) ((drf##_HIGH_FIELD) % 32U) +#define DRF_SIZE(drf) ((drf##_HIGH_FIELD)-(drf##_LOW_FIELD)+1U) +#define DRF_MASK(drf) (0xFFFFFFFFU >> (31U - ((drf##_HIGH_FIELD) % 32U) + ((drf##_LOW_FIELD) % 32U))) +#else +#define DRF_BASE(drf) (NV_FALSE?drf) // much better +#define DRF_EXTENT(drf) (NV_TRUE?drf) // much better +#define DRF_SHIFT(drf) (((NvU32)DRF_BASE(drf)) % 32U) +#define DRF_SHIFT_RT(drf) (((NvU32)DRF_EXTENT(drf)) % 32U) +#define DRF_SIZE(drf) (DRF_EXTENT(drf)-DRF_BASE(drf)+1U) +#define DRF_MASK(drf) (0xFFFFFFFFU>>(31U - DRF_SHIFT_RT(drf) + DRF_SHIFT(drf))) +#endif +#define DRF_DEF(d,r,f,c) (((NvU32)(NV ## d ## r ## f ## c))<>(31-((DRF_ISBIT(1,drf)) % 32)+((DRF_ISBIT(0,drf)) % 32))) +#define DRF_DEF(d,r,f,c) ((NV ## d ## r ## f ## c)<>DRF_SHIFT(NV ## d ## r ## f))&DRF_MASK(NV ## d ## r ## f)) +#endif + +// Signed version of DRF_VAL, which takes care of extending sign bit. +#define DRF_VAL_SIGNED(d,r,f,v) (((DRF_VAL(d,r,f,(v)) ^ (NVBIT(DRF_SIZE(NV ## d ## r ## f)-1U)))) - (NVBIT(DRF_SIZE(NV ## d ## r ## f)-1U))) +#define DRF_IDX_DEF(d,r,f,i,c) ((NV ## d ## r ## f ## c)<>DRF_SHIFT(NV##d##r##f(i)))&DRF_MASK(NV##d##r##f(i))) +#define DRF_IDX_OFFSET_VAL(d,r,f,i,o,v) (((v)>>DRF_SHIFT(NV##d##r##f(i,o)))&DRF_MASK(NV##d##r##f(i,o))) +// Fractional version of DRF_VAL which reads Fx.y fixed point number (x.y)*z +#define DRF_VAL_FRAC(d,r,x,y,v,z) ((DRF_VAL(d,r,x,(v))*z) + ((DRF_VAL(d,r,y,v)*z) / (1<>(63-((DRF_ISBIT(1,drf)) % 64)+((DRF_ISBIT(0,drf)) % 64))) +#define DRF_SHIFTMASK64(drf) (DRF_MASK64(drf)<<(DRF_SHIFT64(drf))) + +#define DRF_DEF64(d,r,f,c) (((NvU64)(NV ## d ## r ## f ## c))<>DRF_SHIFT64(NV ## d ## r ## f))&DRF_MASK64(NV ## d ## r ## f)) + +#define DRF_VAL_SIGNED64(d,r,f,v) (((DRF_VAL64(d,r,f,(v)) ^ (NVBIT64(DRF_SIZE(NV ## d ## r ## f)-1)))) - (NVBIT64(DRF_SIZE(NV ## d ## r ## f)-1))) +#define DRF_IDX_DEF64(d,r,f,i,c) (((NvU64)(NV ## d ## r ## f ## c))<>DRF_SHIFT64(NV##d##r##f(i)))&DRF_MASK64(NV##d##r##f(i))) +#define DRF_IDX_OFFSET_VAL64(d,r,f,i,o,v) (((NvU64)(v)>>DRF_SHIFT64(NV##d##r##f(i,o)))&DRF_MASK64(NV##d##r##f(i,o))) + +#define FLD_SET_DRF64(d,r,f,c,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f)) | DRF_DEF64(d,r,f,c)) +#define FLD_SET_DRF_NUM64(d,r,f,n,v) ((((NvU64)(v)) & ~DRF_SHIFTMASK64(NV##d##r##f)) | DRF_NUM64(d,r,f,n)) +#define FLD_IDX_SET_DRF64(d,r,f,i,c,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f(i))) | DRF_IDX_DEF64(d,r,f,i,c)) +#define FLD_IDX_OFFSET_SET_DRF64(d,r,f,i,o,c,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f(i,o))) | DRF_IDX_OFFSET_DEF64(d,r,f,i,o,c)) +#define FLD_IDX_SET_DRF_DEF64(d,r,f,i,c,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f(i))) | DRF_IDX_DEF64(d,r,f,i,c)) +#define FLD_IDX_SET_DRF_NUM64(d,r,f,i,n,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f(i))) | DRF_IDX_NUM64(d,r,f,i,n)) +#define FLD_SET_DRF_IDX64(d,r,f,c,i,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f)) | DRF_DEF64(d,r,f,c(i))) + +#define FLD_TEST_DRF64(d,r,f,c,v) (DRF_VAL64(d, r, f, (v)) == NV##d##r##f##c) +#define FLD_TEST_DRF_AND64(d,r,f,c,v) (DRF_VAL64(d, r, f, (v)) & NV##d##r##f##c) +#define FLD_TEST_DRF_NUM64(d,r,f,n,v) (DRF_VAL64(d, r, f, (v)) == (n)) +#define FLD_IDX_TEST_DRF64(d,r,f,i,c,v) (DRF_IDX_VAL64(d, r, f, i, (v)) == NV##d##r##f##c) +#define FLD_IDX_OFFSET_TEST_DRF64(d,r,f,i,o,c,v) (DRF_IDX_OFFSET_VAL64(d, r, f, i, o, (v)) == NV##d##r##f##c) + +#define REF_DEF64(drf,d) (((drf ## d)&DRF_MASK64(drf))<>DRF_SHIFT64(drf))&DRF_MASK64(drf)) +#if defined(NV_MISRA_COMPLIANCE_REQUIRED) && defined(MISRA_14_3) +#define REF_NUM64(drf,n) (((NvU64)(n)&(0xFFFFFFFFFFFFFFFFU>>(63U-((drf##_HIGH_FIELD) % 63U)+((drf##_LOW_FIELD) % 63U)))) << ((drf##_LOW_FIELD) % 63U)) +#else +#define REF_NUM64(drf,n) (((NvU64)(n)&DRF_MASK64(drf))<>DRF_SHIFT(drf))&DRF_MASK(drf)) +#if defined(NV_MISRA_COMPLIANCE_REQUIRED) && defined(MISRA_14_3) +#define REF_NUM(drf,n) (((n)&(0xFFFFFFFFU>>(31U-((drf##_HIGH_FIELD) % 32U)+((drf##_LOW_FIELD) % 32U)))) << ((drf##_LOW_FIELD) % 32U)) +#else +#define REF_NUM(drf,n) (((n)&DRF_MASK(drf))<>DRF_SHIFT(CR ## d ## r ## f))&DRF_MASK(CR ## d ## r ## f)) + +// Multi-word (MW) field manipulations. For multi-word structures (e.g., Fermi SPH), +// fields may have bit numbers beyond 32. To avoid errors using "classic" multi-word macros, +// all the field extents are defined as "MW(X)". For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. +// +// DRF_VAL_MW() macro is meant to be used for native endian 32-bit aligned 32-bit word data, +// not for byte stream data. +// +// DRF_VAL_BS() macro is for byte stream data used in fbQueryBIOS_XXX(). +// +#define DRF_EXPAND_MW(drf) drf // used to turn "MW(a:b)" into "a:b" +#define DRF_PICK_MW(drf,v) ((v)? DRF_EXPAND_##drf) // picks low or high bits +#define DRF_WORD_MW(drf) (DRF_PICK_MW(drf,0)/32) // which word in a multi-word array +#define DRF_BASE_MW(drf) (DRF_PICK_MW(drf,0)%32) // which start bit in the selected word? +#define DRF_EXTENT_MW(drf) (DRF_PICK_MW(drf,1)%32) // which end bit in the selected word +#define DRF_SHIFT_MW(drf) (DRF_PICK_MW(drf,0)%32) +#define DRF_MASK_MW(drf) (0xFFFFFFFFU>>((31-(DRF_EXTENT_MW(drf))+(DRF_BASE_MW(drf)))%32)) +#define DRF_SHIFTMASK_MW(drf) ((DRF_MASK_MW(drf))<<(DRF_SHIFT_MW(drf))) +#define DRF_SIZE_MW(drf) (DRF_EXTENT_MW(drf)-DRF_BASE_MW(drf)+1) + +#define DRF_DEF_MW(d,r,f,c) ((NV##d##r##f##c) << DRF_SHIFT_MW(NV##d##r##f)) +#define DRF_NUM_MW(d,r,f,n) (((n)&DRF_MASK_MW(NV##d##r##f))<>DRF_SHIFT_MW(NV##d##r##f))&DRF_MASK_MW(NV##d##r##f)) +#define DRF_SPANS(drf) ((DRF_PICK_MW(drf,0)/32) != (DRF_PICK_MW(drf,1)/32)) +#define DRF_WORD_MW_LOW(drf) (DRF_PICK_MW(drf,0)/32) +#define DRF_WORD_MW_HIGH(drf) (DRF_PICK_MW(drf,1)/32) +#define DRF_MASK_MW_LOW(drf) (0xFFFFFFFFU) +#define DRF_MASK_MW_HIGH(drf) (0xFFFFFFFFU>>(31-(DRF_EXTENT_MW(drf)))) +#define DRF_SHIFT_MW_LOW(drf) (DRF_PICK_MW(drf,0)%32) +#define DRF_SHIFT_MW_HIGH(drf) (0) +#define DRF_MERGE_SHIFT(drf) ((32-((DRF_PICK_MW(drf,0)%32)))%32) +#define DRF_VAL_MW_2WORD(d,r,f,v) (((((v)[DRF_WORD_MW_LOW(NV##d##r##f)])>>DRF_SHIFT_MW_LOW(NV##d##r##f))&DRF_MASK_MW_LOW(NV##d##r##f)) | \ + (((((v)[DRF_WORD_MW_HIGH(NV##d##r##f)])>>DRF_SHIFT_MW_HIGH(NV##d##r##f))&DRF_MASK_MW_HIGH(NV##d##r##f)) << DRF_MERGE_SHIFT(NV##d##r##f))) +#define DRF_VAL_MW(d,r,f,v) ( DRF_SPANS(NV##d##r##f) ? DRF_VAL_MW_2WORD(d,r,f,v) : DRF_VAL_MW_1WORD(d,r,f,v) ) + +#define DRF_IDX_DEF_MW(d,r,f,i,c) ((NV##d##r##f##c)<>DRF_SHIFT_MW(NV##d##r##f(i)))&DRF_MASK_MW(NV##d##r##f(i))) + +// +// Logically OR all DRF_DEF constants indexed from zero to s (semiinclusive). +// Caution: Target variable v must be pre-initialized. +// +#define FLD_IDX_OR_DRF_DEF(d,r,f,c,s,v) \ +do \ +{ NvU32 idx; \ + for (idx = 0; idx < (NV ## d ## r ## f ## s); ++idx)\ + { \ + v |= DRF_IDX_DEF(d,r,f,idx,c); \ + } \ +} while(0) + + +#define FLD_MERGE_MW(drf,n,v) (((v)[DRF_WORD_MW(drf)] & ~DRF_SHIFTMASK_MW(drf)) | n) +#define FLD_ASSIGN_MW(drf,n,v) ((v)[DRF_WORD_MW(drf)] = FLD_MERGE_MW(drf, n, v)) +#define FLD_IDX_MERGE_MW(drf,i,n,v) (((v)[DRF_WORD_MW(drf(i))] & ~DRF_SHIFTMASK_MW(drf(i))) | n) +#define FLD_IDX_ASSIGN_MW(drf,i,n,v) ((v)[DRF_WORD_MW(drf(i))] = FLD_MERGE_MW(drf(i), n, v)) + +#define FLD_SET_DRF_MW(d,r,f,c,v) FLD_MERGE_MW(NV##d##r##f, DRF_DEF_MW(d,r,f,c), v) +#define FLD_SET_DRF_NUM_MW(d,r,f,n,v) FLD_ASSIGN_MW(NV##d##r##f, DRF_NUM_MW(d,r,f,n), v) +#define FLD_SET_DRF_DEF_MW(d,r,f,c,v) FLD_ASSIGN_MW(NV##d##r##f, DRF_DEF_MW(d,r,f,c), v) +#define FLD_IDX_SET_DRF_MW(d,r,f,i,c,v) FLD_IDX_MERGE_MW(NV##d##r##f, i, DRF_IDX_DEF_MW(d,r,f,i,c), v) +#define FLD_IDX_SET_DRF_DEF_MW(d,r,f,i,c,v) FLD_IDX_MERGE_MW(NV##d##r##f, i, DRF_IDX_DEF_MW(d,r,f,i,c), v) +#define FLD_IDX_SET_DRF_NUM_MW(d,r,f,i,n,v) FLD_IDX_ASSIGN_MW(NV##d##r##f, i, DRF_IDX_NUM_MW(d,r,f,i,n), v) + +#define FLD_TEST_DRF_MW(d,r,f,c,v) ((DRF_VAL_MW(d, r, f, (v)) == NV##d##r##f##c)) +#define FLD_TEST_DRF_NUM_MW(d,r,f,n,v) ((DRF_VAL_MW(d, r, f, (v)) == n)) +#define FLD_IDX_TEST_DRF_MW(d,r,f,i,c,v) ((DRF_IDX_VAL_MW(d, r, f, i, (v)) == NV##d##r##f##c)) + +#define DRF_VAL_BS(d,r,f,v) ( DRF_SPANS(NV##d##r##f) ? DRF_VAL_BS_2WORD(d,r,f,(v)) : DRF_VAL_BS_1WORD(d,r,f,(v)) ) + +//------------------------------------------------------------------------// +// // +// Common defines for engine register reference wrappers // +// // +// New engine addressing can be created like: // +// \#define ENG_REG_PMC(o,d,r) NV##d##r // +// \#define ENG_IDX_REG_CE(o,d,i,r) CE_MAP(o,r,i) // +// // +// See FB_FBPA* for more examples // +//------------------------------------------------------------------------// + +#define ENG_RD_REG(g,o,d,r) GPU_REG_RD32(g, ENG_REG##d(o,d,r)) +#define ENG_WR_REG(g,o,d,r,v) GPU_REG_WR32(g, ENG_REG##d(o,d,r), (v)) +#define ENG_RD_DRF(g,o,d,r,f) ((GPU_REG_RD32(g, ENG_REG##d(o,d,r))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) +#define ENG_WR_DRF_DEF(g,o,d,r,f,c) GPU_REG_WR32(g, ENG_REG##d(o,d,r),(GPU_REG_RD32(g,ENG_REG##d(o,d,r))&~(GPU_DRF_MASK(NV##d##r##f)<>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) +#define ENG_TEST_IDX_DRF_DEF(g,o,d,r,f,c,i) (ENG_RD_IDX_DRF(g, o, d, r, f, (i)) == NV##d##r##f##c) + +#define ENG_IDX_RD_REG(g,o,d,i,r) GPU_REG_RD32(g, ENG_IDX_REG##d(o,d,i,r)) +#define ENG_IDX_WR_REG(g,o,d,i,r,v) GPU_REG_WR32(g, ENG_IDX_REG##d(o,d,i,r), (v)) + +#define ENG_IDX_RD_DRF(g,o,d,i,r,f) ((GPU_REG_RD32(g, ENG_IDX_REG##d(o,d,i,r))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) + +// +// DRF_READ_1WORD_BS() and DRF_READ_1WORD_BS_HIGH() do not read beyond the bytes that contain +// the requested value. Reading beyond the actual data causes a page fault panic when the +// immediately following page happened to be protected or not mapped. +// +#define DRF_VAL_BS_1WORD(d,r,f,v) ((DRF_READ_1WORD_BS(d,r,f,v)>>DRF_SHIFT_MW(NV##d##r##f))&DRF_MASK_MW(NV##d##r##f)) +#define DRF_VAL_BS_2WORD(d,r,f,v) (((DRF_READ_4BYTE_BS(NV##d##r##f,v)>>DRF_SHIFT_MW_LOW(NV##d##r##f))&DRF_MASK_MW_LOW(NV##d##r##f)) | \ + (((DRF_READ_1WORD_BS_HIGH(d,r,f,v)>>DRF_SHIFT_MW_HIGH(NV##d##r##f))&DRF_MASK_MW_HIGH(NV##d##r##f)) << DRF_MERGE_SHIFT(NV##d##r##f))) + +#define DRF_READ_1BYTE_BS(drf,v) ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW(drf)*4])) +#define DRF_READ_2BYTE_BS(drf,v) (DRF_READ_1BYTE_BS(drf,v)| \ + ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW(drf)*4+1])<<8)) +#define DRF_READ_3BYTE_BS(drf,v) (DRF_READ_2BYTE_BS(drf,v)| \ + ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW(drf)*4+2])<<16)) +#define DRF_READ_4BYTE_BS(drf,v) (DRF_READ_3BYTE_BS(drf,v)| \ + ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW(drf)*4+3])<<24)) + +#define DRF_READ_1BYTE_BS_HIGH(drf,v) ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW_HIGH(drf)*4])) +#define DRF_READ_2BYTE_BS_HIGH(drf,v) (DRF_READ_1BYTE_BS_HIGH(drf,v)| \ + ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW_HIGH(drf)*4+1])<<8)) +#define DRF_READ_3BYTE_BS_HIGH(drf,v) (DRF_READ_2BYTE_BS_HIGH(drf,v)| \ + ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW_HIGH(drf)*4+2])<<16)) +#define DRF_READ_4BYTE_BS_HIGH(drf,v) (DRF_READ_3BYTE_BS_HIGH(drf,v)| \ + ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW_HIGH(drf)*4+3])<<24)) + +// Calculate 2^n - 1 and avoid shift counter overflow +// +// On Windows amd64, 64 << 64 => 1 +// +#define NV_TWO_N_MINUS_ONE(n) (((1ULL<<(n/2))<<((n+1)/2))-1) + +// +// Create a 64b bitmask with n bits set +// This is the same as ((1ULL<>((n>64) ? 0 : (64-n)))) + +#define DRF_READ_1WORD_BS(d,r,f,v) \ + ((DRF_EXTENT_MW(NV##d##r##f)<8)?DRF_READ_1BYTE_BS(NV##d##r##f,(v)): \ + ((DRF_EXTENT_MW(NV##d##r##f)<16)?DRF_READ_2BYTE_BS(NV##d##r##f,(v)): \ + ((DRF_EXTENT_MW(NV##d##r##f)<24)?DRF_READ_3BYTE_BS(NV##d##r##f,(v)): \ + DRF_READ_4BYTE_BS(NV##d##r##f,(v))))) + +#define DRF_READ_1WORD_BS_HIGH(d,r,f,v) \ + ((DRF_EXTENT_MW(NV##d##r##f)<8)?DRF_READ_1BYTE_BS_HIGH(NV##d##r##f,(v)): \ + ((DRF_EXTENT_MW(NV##d##r##f)<16)?DRF_READ_2BYTE_BS_HIGH(NV##d##r##f,(v)): \ + ((DRF_EXTENT_MW(NV##d##r##f)<24)?DRF_READ_3BYTE_BS_HIGH(NV##d##r##f,(v)): \ + DRF_READ_4BYTE_BS_HIGH(NV##d##r##f,(v))))) + +#define LOWESTBIT(x) ( (x) & (((x) - 1U) ^ (x)) ) +// Destructive operation on n32 +#define HIGHESTBIT(n32) \ +{ \ + HIGHESTBITIDX_32(n32); \ + n32 = NVBIT(n32); \ +} +#define ONEBITSET(x) ( ((x) != 0U) && (((x) & ((x) - 1U)) == 0U) ) + +// Destructive operation on n32 +#define NUMSETBITS_32(n32) \ +{ \ + n32 = n32 - ((n32 >> 1) & 0x55555555); \ + n32 = (n32 & 0x33333333) + ((n32 >> 2) & 0x33333333); \ + n32 = (((n32 + (n32 >> 4)) & 0x0F0F0F0F) * 0x01010101) >> 24; \ +} + +/*! + * Calculate number of bits set in a 32-bit unsigned integer. + * Pure typesafe alternative to @ref NUMSETBITS_32. + */ +static NV_FORCEINLINE NvU32 +nvPopCount32(const NvU32 x) +{ + NvU32 temp = x; + temp = temp - ((temp >> 1) & 0x55555555U); + temp = (temp & 0x33333333U) + ((temp >> 2) & 0x33333333U); + temp = (((temp + (temp >> 4)) & 0x0F0F0F0FU) * 0x01010101U) >> 24; + return temp; +} + +/*! + * Calculate number of bits set in a 64-bit unsigned integer. + */ +static NV_FORCEINLINE NvU32 +nvPopCount64(const NvU64 x) +{ + NvU64 temp = x; + temp = temp - ((temp >> 1) & 0x5555555555555555ULL); + temp = (temp & 0x3333333333333333ULL) + ((temp >> 2) & 0x3333333333333333ULL); + temp = (temp + (temp >> 4)) & 0x0F0F0F0F0F0F0F0FULL; + temp = (temp * 0x0101010101010101ULL) >> 56; + return (NvU32)temp; +} + +/*! + * Determine how many bits are set below a bit index within a mask. + * This assigns a dense ordering to the set bits in the mask. + * + * For example the mask 0xCD contains 5 set bits: + * nvMaskPos32(0xCD, 0) == 0 + * nvMaskPos32(0xCD, 2) == 1 + * nvMaskPos32(0xCD, 3) == 2 + * nvMaskPos32(0xCD, 6) == 3 + * nvMaskPos32(0xCD, 7) == 4 + */ +static NV_FORCEINLINE NvU32 +nvMaskPos32(const NvU32 mask, const NvU32 bitIdx) +{ + return nvPopCount32(mask & (NVBIT32(bitIdx) - 1U)); +} + +// Destructive operation on n32 +#define LOWESTBITIDX_32(n32) \ +{ \ + n32 = BIT_IDX_32(LOWESTBIT(n32));\ +} + +// Destructive operation on n64 +#define LOWESTBITIDX_64(n64) \ +{ \ + n64 = BIT_IDX_64(LOWESTBIT(n64));\ +} + +// Destructive operation on n32 +#define HIGHESTBITIDX_32(n32) \ +{ \ + NvU32 count = 0; \ + while (n32 >>= 1) \ + { \ + count++; \ + } \ + n32 = count; \ +} + +// Destructive operation on n64 +#define HIGHESTBITIDX_64(n64) \ +{ \ + NvU64 count = 0; \ + while (n64 >>= 1) \ + { \ + count++; \ + } \ + n64 = count; \ +} + +// Destructive operation on n32 +#define ROUNDUP_POW2(n32) \ +{ \ + n32--; \ + n32 |= n32 >> 1; \ + n32 |= n32 >> 2; \ + n32 |= n32 >> 4; \ + n32 |= n32 >> 8; \ + n32 |= n32 >> 16; \ + n32++; \ +} + +/*! + * Round up a 32-bit unsigned integer to the next power of 2. + * Pure typesafe alternative to @ref ROUNDUP_POW2. + * + * param[in] x must be in range [0, 2^31] to avoid overflow. + */ +static NV_FORCEINLINE NvU32 +nvNextPow2_U32(const NvU32 x) +{ + NvU32 y = x; + y--; + y |= y >> 1; + y |= y >> 2; + y |= y >> 4; + y |= y >> 8; + y |= y >> 16; + y++; + return y; +} + + +static NV_FORCEINLINE NvU32 +nvPrevPow2_U32(const NvU32 x ) +{ + NvU32 y = x; + y |= (y >> 1); + y |= (y >> 2); + y |= (y >> 4); + y |= (y >> 8); + y |= (y >> 16); + return y - (y >> 1); +} + +static NV_FORCEINLINE NvU64 +nvPrevPow2_U64(const NvU64 x ) +{ + NvU64 y = x; + y |= (y >> 1); + y |= (y >> 2); + y |= (y >> 4); + y |= (y >> 8); + y |= (y >> 16); + y |= (y >> 32); + return y - (y >> 1); +} + +// Destructive operation on n64 +#define ROUNDUP_POW2_U64(n64) \ +{ \ + n64--; \ + n64 |= n64 >> 1; \ + n64 |= n64 >> 2; \ + n64 |= n64 >> 4; \ + n64 |= n64 >> 8; \ + n64 |= n64 >> 16; \ + n64 |= n64 >> 32; \ + n64++; \ +} + +#define NV_SWAP_U8(a,b) \ +{ \ + NvU8 temp; \ + temp = a; \ + a = b; \ + b = temp; \ +} + +#define NV_SWAP_U32(a,b) \ +{ \ + NvU32 temp; \ + temp = a; \ + a = b; \ + b = temp; \ +} + +/*! + * @brief Macros allowing simple iteration over bits set in a given mask. + * + * @param[in] maskWidth bit-width of the mask (allowed: 8, 16, 32, 64) + * + * @param[in,out] index lvalue that is used as a bit index in the loop + * (can be declared as any NvU* or NvS* variable) + * @param[in] mask expression, loop will iterate over set bits only + */ +#define FOR_EACH_INDEX_IN_MASK(maskWidth,index,mask) \ +{ \ + NvU##maskWidth lclMsk = (NvU##maskWidth)(mask); \ + for ((index) = 0U; lclMsk != 0U; (index)++, lclMsk >>= 1U)\ + { \ + if (((NvU##maskWidth)NVBIT64(0) & lclMsk) == 0U) \ + { \ + continue; \ + } +#define FOR_EACH_INDEX_IN_MASK_END \ + } \ +} + +/*! + * Returns the position of nth set bit in the given mask. + * + * Returns -1 if mask has fewer than n bits set. + * + * n is 0 indexed and has valid values 0..31 inclusive, so "zeroth" set bit is + * the first set LSB. + * + * Example, if mask = 0x000000F0u and n = 1, the return value will be 5. + * Example, if mask = 0x000000F0u and n = 4, the return value will be -1. + */ +static NV_FORCEINLINE NvS32 +nvGetNthSetBitIndex32(NvU32 mask, NvU32 n) +{ + NvU32 seenSetBitsCount = 0; + NvS32 index; + FOR_EACH_INDEX_IN_MASK(32, index, mask) + { + if (seenSetBitsCount == n) + { + return index; + } + ++seenSetBitsCount; + } + FOR_EACH_INDEX_IN_MASK_END; + + return -1; +} + +// +// Size to use when declaring variable-sized arrays +// +#define NV_ANYSIZE_ARRAY 1 + +// +// Returns ceil(a/b) +// +#define NV_CEIL(a,b) (((a)+(b)-1)/(b)) + +// Clearer name for NV_CEIL +#ifndef NV_DIV_AND_CEIL +#define NV_DIV_AND_CEIL(a, b) NV_CEIL(a,b) +#endif + +#ifndef NV_MIN +#define NV_MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef NV_MAX +#define NV_MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +// +// Returns absolute value of provided integer expression +// +#define NV_ABS(a) ((a)>=0?(a):(-(a))) + +// +// Returns 1 if input number is positive, 0 if 0 and -1 if negative. Avoid +// macro parameter as function call which will have side effects. +// +#define NV_SIGN(s) ((NvS8)(((s) > 0) - ((s) < 0))) + +// +// Returns 1 if input number is >= 0 or -1 otherwise. This assumes 0 has a +// positive sign. +// +#define NV_ZERO_SIGN(s) ((NvS8)((((s) >= 0) * 2) - 1)) + +// Returns the offset (in bytes) of 'member' in struct 'type'. +#ifndef NV_OFFSETOF + #if defined(__GNUC__) && (__GNUC__ > 3) + #define NV_OFFSETOF(type, member) ((NvUPtr) __builtin_offsetof(type, member)) + #else + #define NV_OFFSETOF(type, member) ((NvUPtr) &(((type *)0)->member)) + #endif +#endif + +// Given a pointer and the member it is of the parent struct, return a pointer to the parent struct +#define NV_CONTAINEROF(ptr, type, member) ((type *) (((NvUPtr) ptr) - NV_OFFSETOF(type, member))) + +// +// Performs a rounded division of b into a (unsigned). For SIGNED version of +// NV_ROUNDED_DIV() macro check the comments in bug 769777. +// +#define NV_UNSIGNED_ROUNDED_DIV(a,b) (((a) + ((b) / 2U)) / (b)) + +/*! + * Performs a ceiling division of b into a (unsigned). A "ceiling" division is + * a division is one with rounds up result up if a % b != 0. + * + * @param[in] a Numerator + * @param[in] b Denominator + * + * @return a / b + a % b != 0 ? 1 : 0. + */ +#define NV_UNSIGNED_DIV_CEIL(a, b) (((a) + (b - 1)) / (b)) + +/*! + * Performs subtraction where a negative difference is raised to zero. + * Can be used to avoid underflowing an unsigned subtraction. + * + * @param[in] a Minuend + * @param[in] b Subtrahend + * + * @return a > b ? a - b : 0. + */ +#define NV_SUBTRACT_NO_UNDERFLOW(a, b) ((a)>(b) ? (a)-(b) : 0) + +/*! + * Performs a rounded right-shift of 32-bit unsigned value "a" by "shift" bits. + * Will round result away from zero. + * + * @param[in] a 32-bit unsigned value to shift. + * @param[in] shift Number of bits by which to shift. + * + * @return Resulting shifted value rounded away from zero. + */ +#define NV_RIGHT_SHIFT_ROUNDED(a, shift) \ + (((a) >> (shift)) + !!((NVBIT((shift) - 1) & (a)) == NVBIT((shift) - 1))) + +/*! + * Performs a rounded right-shift of 64-bit unsigned value "a" by "shift" bits. + * Will round result away from zero. + * + * @param[in] a 64-bit unsigned value to shift. + * @param[in] shift Number of bits by which to shift. + * + * @return Resulting shifted value rounded away from zero. + */ +#define NV_RIGHT_SHIFT_ROUNDED64(a, shift) \ + ((((NvU64)a) >> (shift)) + !!((NVBIT64((shift) - 1) & ((NvU64)a)) == NVBIT64((shift) - 1))) + +// +// Power of 2 alignment. +// (Will give unexpected results if 'gran' is not a power of 2.) +// +#ifndef NV_ALIGN_DOWN +// +// Notably using v - v + gran ensures gran gets promoted to the same type as v if gran has a smaller type. +// Otherwise, if aligning a NVU64 with NVU32 granularity, the top 4 bytes get zeroed. +// +#define NV_ALIGN_DOWN(v, gran) ((v) & ~((v) - (v) + (gran) - 1)) +#endif + +#ifndef NV_ALIGN_UP +// +// Notably using v - v + gran ensures gran gets promoted to the same type as v if gran has a smaller type. +// Otherwise, if aligning a NVU64 with NVU32 granularity, the top 4 bytes get zeroed. +// +#define NV_ALIGN_UP(v, gran) (((v) + ((gran) - 1)) & ~((v) - (v) + (gran) - 1)) +#endif + +#ifndef NV_ALIGN_DOWN64 +#define NV_ALIGN_DOWN64(v, gran) ((v) & ~(((NvU64)gran) - 1)) +#endif + +#ifndef NV_ALIGN_UP64 +#define NV_ALIGN_UP64(v, gran) (((v) + ((gran) - 1)) & ~(((NvU64)gran)-1)) +#endif + +#ifndef NV_IS_ALIGNED +#define NV_IS_ALIGNED(v, gran) (0U == ((v) & ((gran) - 1U))) +#endif + +#ifndef NV_IS_ALIGNED64 +#define NV_IS_ALIGNED64(v, gran) (0U == ((v) & (((NvU64)gran) - 1U))) +#endif + +#ifndef NVMISC_MEMSET +static NV_FORCEINLINE void *NVMISC_MEMSET(void *s, NvU8 c, NvLength n) +{ + NvU8 *b = (NvU8 *) s; + NvLength i; + + for (i = 0; i < n; i++) + { + b[i] = c; + } + + return s; +} +#endif + +#ifndef NVMISC_MEMCPY +static NV_FORCEINLINE void *NVMISC_MEMCPY(void *dest, const void *src, NvLength n) +{ + NvU8 *destByte = (NvU8 *) dest; + const NvU8 *srcByte = (const NvU8 *) src; + NvLength i; + + for (i = 0; i < n; i++) + { + destByte[i] = srcByte[i]; + } + + return dest; +} +#endif + +static NV_FORCEINLINE char *NVMISC_STRNCPY(char *dest, const char *src, NvLength n) +{ + NvLength i; + + for (i = 0; i < n; i++) + { + dest[i] = src[i]; + if (src[i] == '\0') + { + break; + } + } + + for (; i < n; i++) + { + dest[i] = '\0'; + } + + return dest; +} + +/*! + * Convert a void* to an NvUPtr. This is used when MISRA forbids us from doing a direct cast. + * + * @param[in] ptr Pointer to be converted + * + * @return Resulting NvUPtr + */ +static NV_FORCEINLINE NvUPtr NV_PTR_TO_NVUPTR(void *ptr) +{ + union + { + NvUPtr v; + void *p; + } uAddr; + + uAddr.p = ptr; + return uAddr.v; +} + +/*! + * Convert an NvUPtr to a void*. This is used when MISRA forbids us from doing a direct cast. + * + * @param[in] ptr Pointer to be converted + * + * @return Resulting void * + */ +static NV_FORCEINLINE void *NV_NVUPTR_TO_PTR(NvUPtr address) +{ + union + { + NvUPtr v; + void *p; + } uAddr; + + uAddr.v = address; + return uAddr.p; +} + +// Get bit at pos (k) from x +#define NV_BIT_GET(k, x) (((x) >> (k)) & 1) +// Get bit at pos (n) from (hi) if >= 64, otherwise from (lo). This is paired with NV_BIT_SET_128 which sets the bit. +#define NV_BIT_GET_128(n, lo, hi) (((n) < 64) ? NV_BIT_GET((n), (lo)) : NV_BIT_GET((n) - 64, (hi))) +// +// Set the bit at pos (b) for U64 which is < 128. Since the (b) can be >= 64, we need 2 U64 to store this. +// Use (lo) if (b) is less than 64, and (hi) if >= 64. +// +#define NV_BIT_SET_128(b, lo, hi) { nvAssert( (b) < 128 ); if ( (b) < 64 ) (lo) |= NVBIT64(b); else (hi) |= NVBIT64( b & 0x3F ); } +// +// Clear the bit at pos (b) for U64 which is < 128. +// Use (lo) if (b) is less than 64, and (hi) if >= 64. +// +#define NV_BIT_CLEAR_128(b, lo, hi) { nvAssert( (b) < 128 ); if ( (b) < 64 ) (lo) &= ~NVBIT64(b); else (hi) &= ~NVBIT64( b & 0x3F ); } + +// Get the number of elements the specified fixed-size array +#define NV_ARRAY_ELEMENTS(x) ((sizeof(x)/sizeof((x)[0]))) + +#if !defined(NVIDIA_UNDEF_LEGACY_BIT_MACROS) +// +// Deprecated macros whose definition can be removed once the code base no longer references them. +// Use the NVBIT* macros instead of these macros. +// +#ifndef BIT +#define BIT(b) (1U<<(b)) +#endif +#ifndef BIT32 +#define BIT32(b) ((NvU32)1U<<(b)) +#endif +#ifndef BIT64 +#define BIT64(b) ((NvU64)1U<<(b)) +#endif +#endif +//! 1 if @p x needs more than @p bits to represent +#define NV_BITFIELD_SIZE_ADD_ONE(x, bits) \ + ((!!(((NvU64)(x)) >> (bits))) ? 1 : 0) + +/*! + * Minimum bits required to represent a value between 1 and @p x inclusive. + * + * @param[in] x Highest unsigned value to represent: 1 <= x <= NV_U64_MAX + * + * Example + * @code + * enum Foo { + * E_A, + * E_B, + * E_C, + * E_D, + * E_LAST = E_D + * }; + * + * struct Bar { + * NvU32 fooValue : NV_BITFIELD_SIZE_64(E_LAST); + * // note, it is the highest value of the enum that needs to be + * // represented. + * // If you define a _COUNT as a convenient value for declaring arrays + * // indexed by the enum, remember to subtract 1. + * } + * @endcode + * + * @note This function assumes that the enums are defined from 0..x (inclusive, + * not necessarily contiguous) It is technically possible to have negative enum + * values, so to be safe, the underlying type should always be unsigned. + * + * If @p x is larger than what can fit in the underlying type, a + * 'width of exceeds its type' + * compiler warning is expected. + * + * @return -1 if @p x <= 0. This causes a compile time error if used as + * a bitfield size. + */ +#define NV_BITFIELD_SIZE_64(x) \ + (((x) <= 0) ? -1 : \ + (NV_BITFIELD_SIZE_ADD_ONE((x), 0) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 1) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 2) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 3) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 4) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 5) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 6) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 7) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 8) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 9) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 10) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 11) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 12) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 13) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 14) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 15) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 16) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 17) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 18) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 19) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 20) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 21) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 22) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 23) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 24) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 25) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 26) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 27) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 28) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 29) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 30) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 31) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 32) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 33) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 34) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 35) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 36) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 37) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 38) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 39) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 40) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 41) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 42) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 43) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 44) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 45) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 46) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 47) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 48) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 49) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 50) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 51) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 52) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 53) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 54) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 55) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 56) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 57) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 58) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 59) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 60) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 61) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 62) + \ + NV_BITFIELD_SIZE_ADD_ONE((x), 63))) +// +// Bug 4851259: Newly added functions must be hidden from certain HS-signed +// ucode compilers to avoid signature mismatch. +// +#ifndef NVDEC_1_0 +/*! + * Find the Greatest Common Denominator of two NvU64s + * + * @param[in] a first number + * @param[in] b second number + * + * @return GCD of a and b * + */ +static NV_FORCEINLINE NvU64 nvFindGcdU64(NvU64 a, NvU64 b) +{ + while (1) + { + NvU64 temp; + + if (a == 0) + return b; + temp = a; + a = b % a; + b = temp; + } +} +#endif // NVDEC_1_0 + +#ifdef __cplusplus +} +#endif //__cplusplus +#else +#include +#include +#endif // !defined(NVRISCV_LIBFSP_BUILD) || !NVRISCV_LIBFSP_BUILD +#endif // __NV_MISC_H diff --git a/userspace/sdks/nv570/inc/nvos.h b/userspace/sdks/nv570/inc/nvos.h new file mode 100644 index 0000000..c061f0a --- /dev/null +++ b/userspace/sdks/nv570/inc/nvos.h @@ -0,0 +1,3333 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + /***************************************************************************\ +|* *| +|* NV Architecture Interface *| +|* *| +|* defines the Operating System function and ioctl interfaces to *| +|* NVIDIA's Unified Media Architecture (TM). *| +|* *| + \***************************************************************************/ + +#ifndef NVOS_INCLUDED +#define NVOS_INCLUDED +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvstatus.h" + +#include "nvgputypes.h" +#include "rs_access.h" +#include "nvcfg_sdk.h" + +#if defined(NVRISCV_LIBFSP_BUILD) +#if NVRISCV_LIBFSP_BUILD +#include +#endif +#endif + +/* local defines here */ +#define FILE_DEVICE_NV 0x00008000 +#define NV_IOCTL_FCT_BASE 0x00000800 + +// This is the maximum number of subdevices supported in an SLI +// configuration. +#define NVOS_MAX_SUBDEVICES 8 + +/* Define to indicate the use of Unified status codes - bug 200043705*/ +#define UNIFIED_NV_STATUS 1 + + /***************************************************************************\ +|* NV OS Functions *| + \***************************************************************************/ + +/* + Result codes for RM APIs, shared for all the APIs + + *** IMPORTANT *** + + Ensure that no NVOS_STATUS value has the highest bit set. That bit + is used to passthrough the NVOS_STATUS on code expecting an RM_STATUS. +*/ +#define NVOS_STATUS NV_STATUS + +#define NVOS_STATUS_SUCCESS NV_OK +#define NVOS_STATUS_ERROR_CARD_NOT_PRESENT NV_ERR_CARD_NOT_PRESENT +#define NVOS_STATUS_ERROR_DUAL_LINK_INUSE NV_ERR_DUAL_LINK_INUSE +#define NVOS_STATUS_ERROR_GENERIC NV_ERR_GENERIC +#define NVOS_STATUS_ERROR_GPU_NOT_FULL_POWER NV_ERR_GPU_NOT_FULL_POWER +#define NVOS_STATUS_ERROR_ILLEGAL_ACTION NV_ERR_ILLEGAL_ACTION +#define NVOS_STATUS_ERROR_IN_USE NV_ERR_STATE_IN_USE +#define NVOS_STATUS_ERROR_INSUFFICIENT_RESOURCES NV_ERR_INSUFFICIENT_RESOURCES +#define NVOS_STATUS_ERROR_INSUFFICIENT_ZBC_ENTRY NV_ERR_INSUFFICIENT_ZBC_ENTRY +#define NVOS_STATUS_ERROR_INVALID_ACCESS_TYPE NV_ERR_INVALID_ACCESS_TYPE +#define NVOS_STATUS_ERROR_INVALID_ARGUMENT NV_ERR_INVALID_ARGUMENT +#define NVOS_STATUS_ERROR_INVALID_BASE NV_ERR_INVALID_BASE +#define NVOS_STATUS_ERROR_INVALID_CHANNEL NV_ERR_INVALID_CHANNEL +#define NVOS_STATUS_ERROR_INVALID_CLASS NV_ERR_INVALID_CLASS +#define NVOS_STATUS_ERROR_INVALID_CLIENT NV_ERR_INVALID_CLIENT +#define NVOS_STATUS_ERROR_INVALID_COMMAND NV_ERR_INVALID_COMMAND +#define NVOS_STATUS_ERROR_INVALID_DATA NV_ERR_INVALID_DATA +#define NVOS_STATUS_ERROR_INVALID_DEVICE NV_ERR_INVALID_DEVICE +#define NVOS_STATUS_ERROR_INVALID_DMA_SPECIFIER NV_ERR_INVALID_DMA_SPECIFIER +#define NVOS_STATUS_ERROR_INVALID_EVENT NV_ERR_INVALID_EVENT +#define NVOS_STATUS_ERROR_INVALID_FLAGS NV_ERR_INVALID_FLAGS +#define NVOS_STATUS_ERROR_INVALID_FUNCTION NV_ERR_INVALID_FUNCTION +#define NVOS_STATUS_ERROR_INVALID_HEAP NV_ERR_INVALID_HEAP +#define NVOS_STATUS_ERROR_INVALID_INDEX NV_ERR_INVALID_INDEX +#define NVOS_STATUS_ERROR_INVALID_LIMIT NV_ERR_INVALID_LIMIT +#define NVOS_STATUS_ERROR_INVALID_METHOD NV_ERR_INVALID_METHOD +#define NVOS_STATUS_ERROR_INVALID_OBJECT_BUFFER NV_ERR_BUFFER_TOO_SMALL +#define NVOS_STATUS_ERROR_INVALID_OBJECT_ERROR NV_ERR_INVALID_OBJECT +#define NVOS_STATUS_ERROR_INVALID_OBJECT_HANDLE NV_ERR_INVALID_OBJECT_HANDLE +#define NVOS_STATUS_ERROR_INVALID_OBJECT_NEW NV_ERR_INVALID_OBJECT_NEW +#define NVOS_STATUS_ERROR_INVALID_OBJECT_OLD NV_ERR_INVALID_OBJECT_OLD +#define NVOS_STATUS_ERROR_INVALID_OBJECT_PARENT NV_ERR_INVALID_OBJECT_PARENT +#define NVOS_STATUS_ERROR_INVALID_OFFSET NV_ERR_INVALID_OFFSET +#define NVOS_STATUS_ERROR_INVALID_OWNER NV_ERR_INVALID_OWNER +#define NVOS_STATUS_ERROR_INVALID_PARAM_STRUCT NV_ERR_INVALID_PARAM_STRUCT +#define NVOS_STATUS_ERROR_INVALID_PARAMETER NV_ERR_INVALID_PARAMETER +#define NVOS_STATUS_ERROR_INVALID_POINTER NV_ERR_INVALID_POINTER +#define NVOS_STATUS_ERROR_INVALID_REGISTRY_KEY NV_ERR_INVALID_REGISTRY_KEY +#define NVOS_STATUS_ERROR_INVALID_STATE NV_ERR_INVALID_STATE +#define NVOS_STATUS_ERROR_INVALID_STRING_LENGTH NV_ERR_INVALID_STRING_LENGTH +#define NVOS_STATUS_ERROR_INVALID_XLATE NV_ERR_INVALID_XLATE +#define NVOS_STATUS_ERROR_IRQ_NOT_FIRING NV_ERR_IRQ_NOT_FIRING +#define NVOS_STATUS_ERROR_MULTIPLE_MEMORY_TYPES NV_ERR_MULTIPLE_MEMORY_TYPES +#define NVOS_STATUS_ERROR_NOT_SUPPORTED NV_ERR_NOT_SUPPORTED +#define NVOS_STATUS_ERROR_OPERATING_SYSTEM NV_ERR_OPERATING_SYSTEM +#define NVOS_STATUS_ERROR_LIB_RM_VERSION_MISMATCH NV_ERR_LIB_RM_VERSION_MISMATCH +#define NVOS_STATUS_ERROR_PROTECTION_FAULT NV_ERR_PROTECTION_FAULT +#define NVOS_STATUS_ERROR_TIMEOUT NV_ERR_TIMEOUT +#define NVOS_STATUS_ERROR_TOO_MANY_PRIMARIES NV_ERR_TOO_MANY_PRIMARIES +#define NVOS_STATUS_ERROR_IRQ_EDGE_TRIGGERED NV_ERR_IRQ_EDGE_TRIGGERED +#define NVOS_STATUS_ERROR_INVALID_OPERATION NV_ERR_INVALID_OPERATION +#define NVOS_STATUS_ERROR_NOT_COMPATIBLE NV_ERR_NOT_COMPATIBLE +#define NVOS_STATUS_ERROR_MORE_PROCESSING_REQUIRED NV_WARN_MORE_PROCESSING_REQUIRED +#define NVOS_STATUS_ERROR_INSUFFICIENT_PERMISSIONS NV_ERR_INSUFFICIENT_PERMISSIONS +#define NVOS_STATUS_ERROR_TIMEOUT_RETRY NV_ERR_TIMEOUT_RETRY +#define NVOS_STATUS_ERROR_NOT_READY NV_ERR_NOT_READY +#define NVOS_STATUS_ERROR_GPU_IS_LOST NV_ERR_GPU_IS_LOST +#define NVOS_STATUS_ERROR_IN_FULLCHIP_RESET NV_ERR_GPU_IN_FULLCHIP_RESET +#define NVOS_STATUS_ERROR_INVALID_LOCK_STATE NV_ERR_INVALID_LOCK_STATE +#define NVOS_STATUS_ERROR_INVALID_ADDRESS NV_ERR_INVALID_ADDRESS +#define NVOS_STATUS_ERROR_INVALID_IRQ_LEVEL NV_ERR_INVALID_IRQ_LEVEL +#define NVOS_STATUS_ERROR_MEMORY_TRAINING_FAILED NV_ERR_MEMORY_TRAINING_FAILED +#define NVOS_STATUS_ERROR_BUSY_RETRY NV_ERR_BUSY_RETRY +#define NVOS_STATUS_ERROR_INSUFFICIENT_POWER NV_ERR_INSUFFICIENT_POWER +#define NVOS_STATUS_ERROR_OBJECT_NOT_FOUND NV_ERR_OBJECT_NOT_FOUND +#define NVOS_STATUS_ERROR_RESOURCE_LOST NV_ERR_RESOURCE_LOST +#define NVOS_STATUS_ERROR_BUFFER_TOO_SMALL NV_ERR_BUFFER_TOO_SMALL +#define NVOS_STATUS_ERROR_RESET_REQUIRED NV_ERR_RESET_REQUIRED +#define NVOS_STATUS_ERROR_INVALID_REQUEST NV_ERR_INVALID_REQUEST + +#define NVOS_STATUS_ERROR_PRIV_SEC_VIOLATION NV_ERR_PRIV_SEC_VIOLATION +#define NVOS_STATUS_ERROR_GPU_IN_DEBUG_MODE NV_ERR_GPU_IN_DEBUG_MODE +#define NVOS_STATUS_ERROR_ALREADY_SIGNALLED NV_ERR_ALREADY_SIGNALLED + +/* + Note: + This version of the architecture has been changed to allow the + RM to return a client handle that will subsequently used to + identify the client. NvAllocRoot() returns the handle. All + other functions must specify this client handle. + +*/ +/* macro NV01_FREE */ +#define NV01_FREE (0x00000000) + +/* NT ioctl data structure */ +typedef struct +{ + NvHandle hRoot; + NvHandle hObjectParent; + NvHandle hObjectOld; + NvV32 status; +} NVOS00_PARAMETERS; + +/* valid hClass values. */ +#define NV01_ROOT (0x0U) +// +// Redefining it here to maintain consistency with current code +// This is also defined in class cl0001.h +// +#define NV01_ROOT_NON_PRIV (0x00000001) + +// Deprecated, please use NV01_ROOT_CLIENT +#define NV01_ROOT_USER NV01_ROOT_CLIENT + +// +// This will eventually replace NV01_ROOT_USER in RM client code. Please use this +// RM client object type for any new RM client object allocations that are being +// added. +// +#define NV01_ROOT_CLIENT (0x00000041) + +/* macro NV01_ALLOC_MEMORY */ +#define NV01_ALLOC_MEMORY (0x00000002) + +/* parameter values */ +#define NVOS02_FLAGS_PHYSICALITY 7:4 +#define NVOS02_FLAGS_PHYSICALITY_CONTIGUOUS (0x00000000) +#define NVOS02_FLAGS_PHYSICALITY_NONCONTIGUOUS (0x00000001) +#define NVOS02_FLAGS_LOCATION 11:8 +#define NVOS02_FLAGS_LOCATION_PCI (0x00000000) +#define NVOS02_FLAGS_LOCATION_VIDMEM (0x00000002) +#define NVOS02_FLAGS_COHERENCY 15:12 +#define NVOS02_FLAGS_COHERENCY_UNCACHED (0x00000000) +#define NVOS02_FLAGS_COHERENCY_CACHED (0x00000001) +#define NVOS02_FLAGS_COHERENCY_WRITE_COMBINE (0x00000002) +#define NVOS02_FLAGS_COHERENCY_WRITE_THROUGH (0x00000003) +#define NVOS02_FLAGS_COHERENCY_WRITE_PROTECT (0x00000004) +#define NVOS02_FLAGS_COHERENCY_WRITE_BACK (0x00000005) +#define NVOS02_FLAGS_ALLOC 17:16 +#define NVOS02_FLAGS_ALLOC_NONE (0x00000001) +#define NVOS02_FLAGS_GPU_CACHEABLE 18:18 +#define NVOS02_FLAGS_GPU_CACHEABLE_NO (0x00000000) +#define NVOS02_FLAGS_GPU_CACHEABLE_YES (0x00000001) +// If requested, RM will create a kernel mapping of this memory. +// Default is no map. +#define NVOS02_FLAGS_KERNEL_MAPPING 19:19 +#define NVOS02_FLAGS_KERNEL_MAPPING_NO_MAP (0x00000000) +#define NVOS02_FLAGS_KERNEL_MAPPING_MAP (0x00000001) +#define NVOS02_FLAGS_ALLOC_NISO_DISPLAY 20:20 +#define NVOS02_FLAGS_ALLOC_NISO_DISPLAY_NO (0x00000000) +#define NVOS02_FLAGS_ALLOC_NISO_DISPLAY_YES (0x00000001) + +// +// If the flag is set, the RM will only allow read-only CPU user mappings to the +// allocation. +// +#define NVOS02_FLAGS_ALLOC_USER_READ_ONLY 21:21 +#define NVOS02_FLAGS_ALLOC_USER_READ_ONLY_NO (0x00000000) +#define NVOS02_FLAGS_ALLOC_USER_READ_ONLY_YES (0x00000001) + +// +// If the flag is set, the RM will only allow read-only DMA mappings to the +// allocation. +// +#define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY 22:22 +#define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_NO (0x00000000) +#define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_YES (0x00000001) + +// +// If the flag is set, the IO memory allocation can be registered with the RM if +// the RM regkey peerMappingOverride is set or the client is privileged. +// +// See Bug 1630288 "[PeerSync] threat related to GPU.." for more details. +// +#define NVOS02_FLAGS_PEER_MAP_OVERRIDE 23:23 +#define NVOS02_FLAGS_PEER_MAP_OVERRIDE_DEFAULT (0x00000000) +#define NVOS02_FLAGS_PEER_MAP_OVERRIDE_REQUIRED (0x00000001) + +// If the flag is set RM will assume the memory pages are of type syncpoint. +#define NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT 24:24 +#define NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT_APERTURE (0x00000001) + +// +// Allow client allocations to go to protected/unprotected video/system memory. +// When Ampere Protected Model aka APM or Confidential Compute is enabled and +// DEFAULT flag is set by client, allocations go to protected memory. When +// protected memory is not enabled, allocations go to unprotected memory. +// If APM or CC is not enabled, it is a bug for a client to set the PROTECTED +// flag to YES +// +#define NVOS02_FLAGS_MEMORY_PROTECTION 26:25 +#define NVOS02_FLAGS_MEMORY_PROTECTION_DEFAULT (0x00000000) +#define NVOS02_FLAGS_MEMORY_PROTECTION_PROTECTED (0x00000001) +#define NVOS02_FLAGS_MEMORY_PROTECTION_UNPROTECTED (0x00000002) + +// +// When allocating memory, register the memory descriptor to GSP-RM +// so that GSP-RM is aware of and can access it +// +#define NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM 27:27 +#define NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM_FALSE (0x00000000) +#define NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM_TRUE (0x00000001) + +// +// If _NO_MAP is requested, the RM in supported platforms will not map the +// allocated system or IO memory into user space. The client can later map +// memory through the RmMapMemory() interface. +// If _NEVER_MAP is requested, the RM will never map the allocated system or +// IO memory into user space +// +#define NVOS02_FLAGS_MAPPING 31:30 +#define NVOS02_FLAGS_MAPPING_DEFAULT (0x00000000) +#define NVOS02_FLAGS_MAPPING_NO_MAP (0x00000001) +#define NVOS02_FLAGS_MAPPING_NEVER_MAP (0x00000002) + +// ------------------------------------------------------------------------------------- + +/* parameters */ +typedef struct +{ + NvHandle hRoot; + NvHandle hObjectParent; + NvHandle hObjectNew; + NvV32 hClass; + NvV32 flags; + NvP64 pMemory NV_ALIGN_BYTES(8); + NvU64 limit NV_ALIGN_BYTES(8); + NvV32 status; +} NVOS02_PARAMETERS; + +/* parameter values */ +#define NVOS03_FLAGS_ACCESS 1:0 +#define NVOS03_FLAGS_ACCESS_READ_WRITE (0x00000000) +#define NVOS03_FLAGS_ACCESS_READ_ONLY (0x00000001) +#define NVOS03_FLAGS_ACCESS_WRITE_ONLY (0x00000002) + +#define NVOS03_FLAGS_PREALLOCATE 2:2 +#define NVOS03_FLAGS_PREALLOCATE_DISABLE (0x00000000) +#define NVOS03_FLAGS_PREALLOCATE_ENABLE (0x00000001) + +#define NVOS03_FLAGS_GPU_MAPPABLE 15:15 +#define NVOS03_FLAGS_GPU_MAPPABLE_DISABLE (0x00000000) +#define NVOS03_FLAGS_GPU_MAPPABLE_ENABLE (0x00000001) + +// ------------------------------------------------------------------------------------ +// This flag is required for a hack to be placed inside DD that allows it to +// access a dummy ctxdma as a block linear surface. Refer bug 1562766 for details. +// +// This flag is deprecated, use NVOS03_FLAGS_PTE_KIND. +// +#define NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE 16:16 +#define NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE_FALSE (0x00000000) +#define NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE_TRUE (0x00000001) + +/* + * This field allows to specify the page kind. If the page kind + * is not specified then the page kind associated with the memory will be used. + * + * In tegra display driver stack, the page kind remains unknown at the time + * of memory allocation/import, the page kind can only be known when display + * driver client creates a framebuffer from allocated/imported memory. + * + * This field compatible with NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE flag. + */ +#define NVOS03_FLAGS_PTE_KIND 17:16 +#define NVOS03_FLAGS_PTE_KIND_NONE (0x00000000) +#define NVOS03_FLAGS_PTE_KIND_BL (0x00000001) +#define NVOS03_FLAGS_PTE_KIND_PITCH (0x00000002) + +#define NVOS03_FLAGS_TYPE 23:20 +#define NVOS03_FLAGS_TYPE_NOTIFIER (0x00000001) + +/* + * This is an alias into the LSB of the TYPE field which + * actually indicates if a Kernel Mapping should be created. + * If the RM should have access to the memory then Enable this + * flag. + * + * Note that the NV_OS03_FLAGS_MAPPING is an alias to + * the LSB of the NV_OS03_FLAGS_TYPE. And in fact if + * type is NV_OS03_FLAGS_TYPE_NOTIFIER (bit 20 set) + * then it implicitly means that NV_OS03_FLAGS_MAPPING + * is _MAPPING_KERNEL. If the client wants to have a + * Kernel Mapping, it should use the _MAPPING_KERNEL + * flag set and the _TYPE_NOTIFIER should be used only + * with NOTIFIERS. + */ + +#define NVOS03_FLAGS_MAPPING 20:20 +#define NVOS03_FLAGS_MAPPING_NONE (0x00000000) +#define NVOS03_FLAGS_MAPPING_KERNEL (0x00000001) + +#define NVOS03_FLAGS_CACHE_SNOOP 28:28 +#define NVOS03_FLAGS_CACHE_SNOOP_ENABLE (0x00000000) +#define NVOS03_FLAGS_CACHE_SNOOP_DISABLE (0x00000001) + +// HASH_TABLE:ENABLE means that the context DMA is automatically bound into all +// channels in the client. This can lead to excessive hash table usage. +// HASH_TABLE:DISABLE means that the context DMA must be explicitly bound into +// any channel that needs to use it via NvRmBindContextDma. +// HASH_TABLE:ENABLE is not supported on NV50 and up, and HASH_TABLE:DISABLE should +// be preferred for all new code. +#define NVOS03_FLAGS_HASH_TABLE 29:29 +#define NVOS03_FLAGS_HASH_TABLE_ENABLE (0x00000000) +#define NVOS03_FLAGS_HASH_TABLE_DISABLE (0x00000001) + +/* macro NV01_ALLOC_OBJECT */ +#define NV01_ALLOC_OBJECT (0x00000005) + +/* parameters */ +typedef struct +{ + NvHandle hRoot; + NvHandle hObjectParent; + NvHandle hObjectNew; + NvV32 hClass; + NvV32 status; +} NVOS05_PARAMETERS; + +/* Valid values for hClass in Nv01AllocEvent */ +/* Note that NV01_EVENT_OS_EVENT is same as NV01_EVENT_WIN32_EVENT */ +/* TODO: delete the WIN32 name */ +#define NV01_EVENT_KERNEL_CALLBACK (0x00000078) +#define NV01_EVENT_OS_EVENT (0x00000079) +#define NV01_EVENT_WIN32_EVENT NV01_EVENT_OS_EVENT +#define NV01_EVENT_KERNEL_CALLBACK_EX (0x0000007E) + +/* NOTE: NV01_EVENT_KERNEL_CALLBACK is deprecated. Please use NV01_EVENT_KERNEL_CALLBACK_EX. */ +/* For use with NV01_EVENT_KERNEL_CALLBACK. */ +/* NVOS10_EVENT_KERNEL_CALLBACK data structure storage needs to be retained by the caller. */ +typedef void (*Callback1ArgVoidReturn)(void *arg); +typedef void (*Callback5ArgVoidReturn)(void *arg1, void *arg2, NvHandle hEvent, NvU32 data, NvU32 status); + +/* NOTE: the 'void* arg' below is ok (but unfortunate) since this interface + can only be used by other kernel drivers which must share the same ptr-size */ +typedef struct +{ + Callback1ArgVoidReturn func; + void *arg; +} NVOS10_EVENT_KERNEL_CALLBACK; + +/* For use with NV01_EVENT_KERNEL_CALLBACK_EX. */ +/* NVOS10_EVENT_KERNEL_CALLBACK_EX data structure storage needs to be retained by the caller. */ +/* NOTE: the 'void* arg' below is ok (but unfortunate) since this interface + can only be used by other kernel drivers which must share the same ptr-size */ +typedef struct +{ + Callback5ArgVoidReturn func; + void *arg; +} NVOS10_EVENT_KERNEL_CALLBACK_EX; + +/* Setting this bit in index will set the Event to a Broadcast type */ +/* i.e. each subdevice under a device needs to see the Event before it's signaled */ +#define NV01_EVENT_BROADCAST (0x80000000) + +/* allow non-root resman client to create NV01_EVENT_KERNEL_CALLBACK events */ +/* -- this works in debug/develop drivers only (for security reasons)*/ +#define NV01_EVENT_PERMIT_NON_ROOT_EVENT_KERNEL_CALLBACK_CREATION (0x40000000) + +/* RM event should be triggered only by the specified subdevice; see cl0005.h + * for details re: how to specify subdevice. */ +#define NV01_EVENT_SUBDEVICE_SPECIFIC (0x20000000) + +/* RM should trigger the event but shouldn't do the book-keeping of data + * associated with that event */ +#define NV01_EVENT_WITHOUT_EVENT_DATA (0x10000000) + +/* RM event should be triggered only by the non-stall interrupt */ +#define NV01_EVENT_NONSTALL_INTR (0x08000000) + +/* RM event was allocated from client RM, post events back to client RM */ +#define NV01_EVENT_CLIENT_RM (0x04000000) + +/* function OS19 */ +#define NV04_I2C_ACCESS (0x00000013) + +#define NVOS_I2C_ACCESS_MAX_BUFFER_SIZE 2048 + +/* parameters */ +typedef struct +{ + NvHandle hClient; + NvHandle hDevice; + NvU32 paramSize; + NvP64 paramStructPtr NV_ALIGN_BYTES(8); + NvV32 status; +} NVOS_I2C_ACCESS_PARAMS; + +/* current values for command */ +#define NVOS20_COMMAND_unused0001 0x0001 +#define NVOS20_COMMAND_unused0002 0x0002 +#define NVOS20_COMMAND_STRING_PRINT 0x0003 + +/* function OS21 */ +#define NV04_ALLOC (0x00000015) + +/* parameters */ +typedef struct +{ + NvHandle hRoot; + NvHandle hObjectParent; + NvHandle hObjectNew; + NvV32 hClass; + NvP64 pAllocParms NV_ALIGN_BYTES(8); + NvU32 paramsSize; + NvV32 status; +} NVOS21_PARAMETERS; + +#define NVOS64_FLAGS_NONE (0x00000000) +#define NVOS64_FLAGS_FINN_SERIALIZED (0x00000001) + +/* New struct with rights requested */ +typedef struct +{ + NvHandle hRoot; // [IN] client handle + NvHandle hObjectParent; // [IN] parent handle of new object + NvHandle hObjectNew; // [INOUT] new object handle, 0 to generate + NvV32 hClass; // [in] class num of new object + NvP64 pAllocParms NV_ALIGN_BYTES(8); // [IN] class-specific alloc parameters + NvP64 pRightsRequested NV_ALIGN_BYTES(8); // [IN] RS_ACCESS_MASK to request rights, or NULL + NvU32 paramsSize; // [IN] Size of alloc params + NvU32 flags; // [IN] flags for FINN serialization + NvV32 status; // [OUT] status +} NVOS64_PARAMETERS; + +/* RM Alloc header + * + * Replacement for NVOS21/64_PARAMETERS where embedded pointers are not allowed. + * Input layout for RM Alloc user space calls should be + * + * +--- NVOS62_PARAMETERS ---+--- RM Alloc parameters ---+ + * +--- NVOS65_PARAMETERS ---+--- Rights Requested ---+--- RM Alloc parameters ---+ + * + * NVOS62_PARAMETERS::paramsSize is the size of RM Alloc parameters + * If NVOS65_PARAMETERS::maskSize is 0, Rights Requested will not be present in memory. + * + */ +typedef struct +{ + NvHandle hRoot; // [IN] client handle + NvHandle hObjectParent; // [IN] parent handle of the new object + NvHandle hObjectNew; // [IN] new object handle + NvV32 hClass; // [IN] class num of the new object + NvU32 paramSize; // [IN] size in bytes of the RM alloc parameters + NvV32 status; // [OUT] status +} NVOS62_PARAMETERS; + +#define NVOS65_PARAMETERS_VERSION_MAGIC 0x77FEF81E + +typedef struct +{ + NvHandle hRoot; // [IN] client handle + NvHandle hObjectParent; // [IN] parent handle of the new object + NvHandle hObjectNew; // [INOUT] new object handle, 0 to generate + NvV32 hClass; // [IN] class num of the new object + NvU32 paramSize; // [IN] size in bytes of the RM alloc parameters + NvU32 versionMagic; // [IN] NVOS65_PARAMETERS_VERISON_MAGIC + NvU32 maskSize; // [IN] size in bytes of access mask, or 0 if NULL + NvV32 status; // [OUT] status +} NVOS65_PARAMETERS; + +/* function OS30 */ +#define NV04_IDLE_CHANNELS (0x0000001E) + +/* parameter values */ +#define NVOS30_FLAGS_BEHAVIOR 3:0 +#define NVOS30_FLAGS_BEHAVIOR_SPIN (0x00000000) +#define NVOS30_FLAGS_BEHAVIOR_SLEEP (0x00000001) +#define NVOS30_FLAGS_BEHAVIOR_QUERY (0x00000002) +#define NVOS30_FLAGS_BEHAVIOR_FORCE_BUSY_CHECK (0x00000003) +#define NVOS30_FLAGS_CHANNEL 7:4 +#define NVOS30_FLAGS_CHANNEL_LIST (0x00000000) +#define NVOS30_FLAGS_CHANNEL_SINGLE (0x00000001) +#define NVOS30_FLAGS_IDLE 30:8 +#define NVOS30_FLAGS_IDLE_PUSH_BUFFER (0x00000001) +#define NVOS30_FLAGS_IDLE_CACHE1 (0x00000002) +#define NVOS30_FLAGS_IDLE_GRAPHICS (0x00000004) +#define NVOS30_FLAGS_IDLE_MPEG (0x00000008) +#define NVOS30_FLAGS_IDLE_MOTION_ESTIMATION (0x00000010) +#define NVOS30_FLAGS_IDLE_VIDEO_PROCESSOR (0x00000020) +#define NVOS30_FLAGS_IDLE_MSPDEC (0x00000020) +#define NVOS30_FLAGS_IDLE_BITSTREAM_PROCESSOR (0x00000040) +#define NVOS30_FLAGS_IDLE_MSVLD (0x00000040) +#define NVOS30_FLAGS_IDLE_NVDEC0 NVOS30_FLAGS_IDLE_MSVLD +#define NVOS30_FLAGS_IDLE_CIPHER_DMA (0x00000080) +#define NVOS30_FLAGS_IDLE_SEC (0x00000080) +#define NVOS30_FLAGS_IDLE_CALLBACKS (0x00000100) +#define NVOS30_FLAGS_IDLE_MSPPP (0x00000200) +#define NVOS30_FLAGS_IDLE_CE0 (0x00000400) +#define NVOS30_FLAGS_IDLE_CE1 (0x00000800) +#define NVOS30_FLAGS_IDLE_CE2 (0x00001000) +#define NVOS30_FLAGS_IDLE_CE3 (0x00002000) +#define NVOS30_FLAGS_IDLE_CE4 (0x00004000) +#define NVOS30_FLAGS_IDLE_CE5 (0x00008000) +#define NVOS30_FLAGS_IDLE_VIC (0x00010000) +#define NVOS30_FLAGS_IDLE_MSENC (0x00020000) +#define NVOS30_FLAGS_IDLE_NVENC0 NVOS30_FLAGS_IDLE_MSENC +#define NVOS30_FLAGS_IDLE_NVENC1 (0x00040000) +#define NVOS30_FLAGS_IDLE_NVENC2 (0x00080000) +#define NVOS30_FLAGS_IDLE_NVJPG (0x00100000) +#define NVOS30_FLAGS_IDLE_NVDEC1 (0x00200000) +#define NVOS30_FLAGS_IDLE_NVDEC2 (0x00400000) +#define NVOS30_FLAGS_IDLE_ACTIVECHANNELS (0x00800000) +#define NVOS30_FLAGS_IDLE_ALL_ENGINES (NVOS30_FLAGS_IDLE_GRAPHICS | \ + NVOS30_FLAGS_IDLE_MPEG | \ + NVOS30_FLAGS_IDLE_MOTION_ESTIMATION | \ + NVOS30_FLAGS_IDLE_VIDEO_PROCESSOR | \ + NVOS30_FLAGS_IDLE_BITSTREAM_PROCESSOR | \ + NVOS30_FLAGS_IDLE_CIPHER_DMA | \ + NVOS30_FLAGS_IDLE_MSPDEC | \ + NVOS30_FLAGS_IDLE_NVDEC0 | \ + NVOS30_FLAGS_IDLE_SEC | \ + NVOS30_FLAGS_IDLE_MSPPP | \ + NVOS30_FLAGS_IDLE_CE0 | \ + NVOS30_FLAGS_IDLE_CE1 | \ + NVOS30_FLAGS_IDLE_CE2 | \ + NVOS30_FLAGS_IDLE_CE3 | \ + NVOS30_FLAGS_IDLE_CE4 | \ + NVOS30_FLAGS_IDLE_CE5 | \ + NVOS30_FLAGS_IDLE_NVENC0 | \ + NVOS30_FLAGS_IDLE_NVENC1 | \ + NVOS30_FLAGS_IDLE_NVENC2 | \ + NVOS30_FLAGS_IDLE_VIC | \ + NVOS30_FLAGS_IDLE_NVJPG | \ + NVOS30_FLAGS_IDLE_NVDEC1 | \ + NVOS30_FLAGS_IDLE_NVDEC2) +#define NVOS30_FLAGS_WAIT_FOR_ELPG_ON 31:31 +#define NVOS30_FLAGS_WAIT_FOR_ELPG_ON_NO (0x00000000) +#define NVOS30_FLAGS_WAIT_FOR_ELPG_ON_YES (0x00000001) + +/* parameters */ +typedef struct +{ + NvHandle hClient; + NvHandle hDevice; + NvHandle hChannel; + NvV32 numChannels; + + NvP64 phClients NV_ALIGN_BYTES(8); + NvP64 phDevices NV_ALIGN_BYTES(8); + NvP64 phChannels NV_ALIGN_BYTES(8); + + NvV32 flags; + NvV32 timeout; + NvV32 status; +} NVOS30_PARAMETERS; + +/* function OS32 */ +typedef void (*BindResultFunc)(void * pVoid, NvU32 gpuMask, NvU32 bState, NvU32 bResult); + +#define NV04_VID_HEAP_CONTROL (0x00000020) +/************************************************************************* +************************ New Heap Interface ****************************** +*************************************************************************/ +// NVOS32 Descriptor types +// +// NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR: The dma-buf object +// pointer, provided by the linux kernel buffer sharing sub-system. +// This descriptor can only be used by kernel space rm-clients. +// +#define NVOS32_DESCRIPTOR_TYPE_VIRTUAL_ADDRESS 0 +#define NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY 1 +#define NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY 2 +#define NVOS32_DESCRIPTOR_TYPE_OS_PHYS_ADDR 3 +#define NVOS32_DESCRIPTOR_TYPE_OS_FILE_HANDLE 4 +#define NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR 5 +#define NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR 6 +#define NVOS32_DESCRIPTOR_TYPE_KERNEL_VIRTUAL_ADDRESS 7 +// NVOS32 function +#define NVOS32_FUNCTION_ALLOC_SIZE 2 +#define NVOS32_FUNCTION_FREE 3 +#define NVOS32_FUNCTION_INFO 5 +#define NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT 6 +#define NVOS32_FUNCTION_ALLOC_SIZE_RANGE 14 +#define NVOS32_FUNCTION_REACQUIRE_COMPR 15 +#define NVOS32_FUNCTION_RELEASE_COMPR 16 +#define NVOS32_FUNCTION_GET_MEM_ALIGNMENT 18 +#define NVOS32_FUNCTION_HW_ALLOC 19 +#define NVOS32_FUNCTION_HW_FREE 20 +#define NVOS32_FUNCTION_ALLOC_OS_DESCRIPTOR 27 + +typedef struct +{ + NvP64 sgt NV_ALIGN_BYTES(8); + NvP64 gem NV_ALIGN_BYTES(8); +} NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS; + +// NVOS32 IVC-heap number delimiting value +#define NVOS32_IVC_HEAP_NUMBER_DONT_ALLOCATE_ON_IVC_HEAP 0 // When IVC heaps are present, + // IVC-heap number specified + // as part of 'NVOS32_PARAMETERS' + // which is less or equal to this + // constant indicates that allocation + // should not be done on IVC heap. + // Explanation of IVC-heap number is + // under 'AllocSize' structure below. + +typedef struct +{ + NvHandle hRoot; // [IN] - root object handle + NvHandle hObjectParent; // [IN] - device handle + NvU32 function; // [IN] - heap function, see below FUNCTION* defines + NvHandle hVASpace; // [IN] - VASpace handle + NvS16 ivcHeapNumber; // [IN] - When IVC heaps are present: either 1) number of the IVC heap + // shared between two VMs or 2) number indicating that allocation + // should not be done on an IVC heap. Values greater than constant + // 'NVOS32_IVC_HEAP_NUMBER_DONT_ALLOCATE_ON_IVC_HEAP' define set 1) + // and values less or equal to that constant define set 2). + // When IVC heaps are present, correct IVC-heap number must be specified. + // When IVC heaps are absent, IVC-heap number is diregarded. + // RM provides for each VM a bitmask of heaps with each bit + // specifying the other peer that can use the partition. + // Each bit set to one can be enumerated, such that the bit + // with lowest significance is enumerated with one. + // 'ivcHeapNumber' parameter specifies this enumeration value. + // This value is used to uniquely identify a heap shared between + // two particular VMs. + // Illustration: + // bitmask: 1 1 0 1 0 = 0x1A + // possible 'ivcHeapNumber' values: 3, 2, 1 + NvV32 status; // [OUT] - returned NVOS32* status code, see below STATUS* defines + NvU64 total NV_ALIGN_BYTES(8); // [OUT] - returned total size of heap + NvU64 free NV_ALIGN_BYTES(8); // [OUT] - returned free space available in heap + + union + { + // NVOS32_FUNCTION_ALLOC_SIZE + struct + { + NvU32 owner; // [IN] - memory owner ID + NvHandle hMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated) + NvU32 type; // [IN] - surface type, see below TYPE* defines + NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines + NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 format; // [IN/OUT] - format requested, and format allocated + NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated + NvU32 zcullCovg; // [OUT] - zcull covg allocated + NvU32 partitionStride; // [IN/OUT] - 0 means "RM" chooses + NvU32 width; // [IN] - width "hint" used for zcull region allocations + NvU32 height; // [IN] - height "hint" used for zcull region allocations + NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated + NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on + NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset + NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit + NvP64 address NV_ALIGN_BYTES(8);// [OUT] - returned address + NvU64 rangeBegin NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range + NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive. + NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET) + NvS32 numaNode; // [IN] - NUMA node from which memory should be allocated + } AllocSize; + + // NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT + struct + { + NvU32 owner; // [IN] - memory owner ID + NvHandle hMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated) + NvU32 type; // [IN] - surface type, see below TYPE* defines + NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines + NvU32 height; // [IN] - height of surface in pixels + NvS32 pitch; // [IN/OUT] - desired pitch AND returned actual pitch allocated + NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 width; //[IN] - width of surface in pixels + NvU32 format; // [IN/OUT] - format requested, and format allocated + NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated + NvU32 zcullCovg; // [OUT] - zcull covg allocated + NvU32 partitionStride; // [IN/OUT] - 0 means "RM" chooses + NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated + NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on + NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset + NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit + NvP64 address NV_ALIGN_BYTES(8);// [OUT] - returned address + NvU64 rangeBegin NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range + NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive. + NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET) + NvS32 numaNode; // [IN] - NUMA node from which memory should be allocated + } AllocTiledPitchHeight; + + // NVOS32_FUNCTION_FREE + struct + { + NvU32 owner; // [IN] - memory owner ID + NvHandle hMemory; // [IN] - unique memory handle + NvU32 flags; // [IN] - heap free flags (must be NVOS32_FREE_FLAGS_MEMORY_HANDLE_PROVIDED) + } Free; + + // NVOS32_FUNCTION_RELEASE_COMPR + struct + { + NvU32 owner; // [IN] - memory owner ID + NvU32 flags; // [IN] - must be NVOS32_RELEASE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED + NvHandle hMemory; // [IN] - unique memory handle (valid if _RELEASE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED + } ReleaseCompr; + + // NVOS32_FUNCTION_REACQUIRE_COMPR + struct + { + NvU32 owner; // [IN] - memory owner ID + NvU32 flags; // [IN] - must be NVOS32_REACQUIRE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED + NvHandle hMemory; // [IN] - unique memory handle (valid if _REACQUIRE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED + } ReacquireCompr; + + // NVOS32_FUNCTION_INFO + struct + { + NvU32 attr; // [IN] - memory heap attributes requested + NvU64 offset NV_ALIGN_BYTES(8); // [OUT] - base of largest free block + NvU64 size NV_ALIGN_BYTES(8); // [OUT] - size of largest free block + NvU64 base NV_ALIGN_BYTES(8); // [OUT] - returned heap phys base + } Info; + + // NVOS32_FUNCTION_ALLOC_SIZE_RANGE + struct + { + NvU32 owner; // [IN] - memory owner ID + NvHandle hMemory; // [IN] - unique memory handle + NvU32 type; // [IN] - surface type, see below TYPE* defines + NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines + NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 format; // [IN/OUT] - format requested, and format allocated + NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated + NvU32 zcullCovg; // [OUT] - zcull covg allocated + NvU32 partitionStride; // [IN/OUT] - 0 means "RM" chooses + NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated + NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on + NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset + NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit + NvU64 rangeBegin NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range + NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive. + NvP64 address NV_ALIGN_BYTES(8);// [OUT] - returned address + NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET) + NvS32 numaNode; // [IN] - NUMA node from which memory should be allocated + } AllocSizeRange; + + // NVOS32_FUNCTION_GET_MEM_ALIGNMENT + struct + { + NvU32 alignType; // Input + NvU32 alignAttr; + NvU32 alignInputFlags; + NvU64 alignSize NV_ALIGN_BYTES(8); + NvU32 alignHeight; + NvU32 alignWidth; + NvU32 alignPitch; + NvU32 alignPad; + NvU32 alignMask; + NvU32 alignKind; + NvU32 alignAdjust; // Output -- If non-zero the amount we need to adjust the offset + NvU32 alignAttr2; + } AllocHintAlignment; + + struct + { + NvU32 allocOwner; // [IN] - memory owner ID + NvHandle allochMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated) + NvU32 flags; + NvU32 allocType; // Input + NvU32 allocAttr; + NvU32 allocInputFlags; + NvU64 allocSize NV_ALIGN_BYTES(8); + NvU32 allocHeight; + NvU32 allocWidth; + NvU32 allocPitch; + NvU32 allocMask; + NvU32 allocComprCovg; + NvU32 allocZcullCovg; + NvP64 bindResultFunc NV_ALIGN_BYTES(8); // BindResultFunc + NvP64 pHandle NV_ALIGN_BYTES(8); + NvHandle hResourceHandle; // Handle to RM container + NvU32 retAttr; // Output Indicates the resources that we allocated + NvU32 kind; + NvU64 osDeviceHandle NV_ALIGN_BYTES(8); + NvU32 allocAttr2; + NvU32 retAttr2; // Output Indicates the resources that we allocated + NvU64 allocAddr NV_ALIGN_BYTES(8); + // [out] from GMMU_COMPR_INFO in drivers/common/shared/inc/mmu/gmmu_fmt.h + struct + { + NvU32 compPageShift; + NvU32 compressedKind; + NvU32 compTagLineMin; + NvU32 compPageIndexLo; + NvU32 compPageIndexHi; + NvU32 compTagLineMultiplier; + } comprInfo; + // [out] fallback uncompressed kind. + NvU32 uncompressedKind; + } HwAlloc; + + // NVOS32_FUNCTION_HW_FREE + struct + { + NvHandle hResourceHandle; // Handle to RM Resource Info + NvU32 flags; // Indicate if HW Resources and/or Memory + } HwFree; +// Updated interface check. +#define NV_RM_OS32_ALLOC_OS_DESCRIPTOR_WITH_OS32_ATTR 1 + + // NVOS32_FUNCTION_ALLOC_OS_DESCRIPTOR + struct + { + NvHandle hMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated) + NvU32 type; // [IN] - surface type, see below TYPE* defines + NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines + NvU32 attr; // [IN] - attributes for memory placement/properties, see below + NvU32 attr2; // [IN] - attributes GPU_CACHEABLE + NvP64 descriptor NV_ALIGN_BYTES(8); // [IN] - descriptor address + NvU64 limit NV_ALIGN_BYTES(8); // [IN] - allocated size -1 + NvU32 descriptorType; // [IN] - descriptor type(Virtual | nvmap Handle) + } AllocOsDesc; + + } data; +} NVOS32_PARAMETERS; + +#define NVOS32_DELETE_RESOURCES_ALL 0 + +// type field +#define NVOS32_TYPE_IMAGE 0 +#define NVOS32_TYPE_DEPTH 1 +#define NVOS32_TYPE_TEXTURE 2 +#define NVOS32_TYPE_VIDEO 3 +#define NVOS32_TYPE_FONT 4 +#define NVOS32_TYPE_CURSOR 5 +#define NVOS32_TYPE_DMA 6 +#define NVOS32_TYPE_INSTANCE 7 +#define NVOS32_TYPE_PRIMARY 8 +#define NVOS32_TYPE_ZCULL 9 +#define NVOS32_TYPE_UNUSED 10 +#define NVOS32_TYPE_SHADER_PROGRAM 11 +#define NVOS32_TYPE_OWNER_RM 12 +#define NVOS32_TYPE_NOTIFIER 13 +#define NVOS32_TYPE_RESERVED 14 +#define NVOS32_TYPE_PMA 15 +#define NVOS32_TYPE_STENCIL 16 +#define NVOS32_TYPE_SYNCPOINT 17 +#define NVOS32_NUM_MEM_TYPES 18 + +// Surface attribute field - bitmask of requested attributes the surface +// should have. +// This value is updated to reflect what was actually allocated, and so this +// field must be checked after every allocation to determine what was +// allocated. Pass in the ANY tags to indicate that RM should fall back but +// still succeed the alloc. +// for example, if tiled_any is passed in, but no tile ranges are available, +// RM will allocate normal memory and indicate that in the returned attr field. +// Each returned attribute will have the REQUIRED field set if that attribute +// applies to the allocated surface. + +#define NVOS32_ATTR_NONE 0x00000000 + +#define NVOS32_ATTR_DEPTH 2:0 +#define NVOS32_ATTR_DEPTH_UNKNOWN 0x00000000 +#define NVOS32_ATTR_DEPTH_8 0x00000001 +#define NVOS32_ATTR_DEPTH_16 0x00000002 +#define NVOS32_ATTR_DEPTH_24 0x00000003 +#define NVOS32_ATTR_DEPTH_32 0x00000004 +#define NVOS32_ATTR_DEPTH_64 0x00000005 +#define NVOS32_ATTR_DEPTH_128 0x00000006 + +#define NVOS32_ATTR_COMPR_COVG 3:3 +#define NVOS32_ATTR_COMPR_COVG_DEFAULT 0x00000000 +#define NVOS32_ATTR_COMPR_COVG_PROVIDED 0x00000001 + +// Surface description - number of AA samples +// This number should only reflect AA done in hardware, not in software. For +// example, OpenGL's 8x AA mode is a mix of 2x hardware multisample and 2x2 +// software supersample. +// OpenGL should specify ATTR_AA_SAMPLES of 2 in this case, not 8, because +// the hardware will be programmed to run in 2x AA mode. +// Note that X_VIRTUAL_Y means X real samples with Y samples total (i.e. Y +// does not indicate the number of virtual samples). For instance, what +// arch and HW describe as NV_PGRAPH_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 +// corresponds to NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_16 here. + +#define NVOS32_ATTR_AA_SAMPLES 7:4 +#define NVOS32_ATTR_AA_SAMPLES_1 0x00000000 +#define NVOS32_ATTR_AA_SAMPLES_2 0x00000001 +#define NVOS32_ATTR_AA_SAMPLES_4 0x00000002 +#define NVOS32_ATTR_AA_SAMPLES_4_ROTATED 0x00000003 +#define NVOS32_ATTR_AA_SAMPLES_6 0x00000004 +#define NVOS32_ATTR_AA_SAMPLES_8 0x00000005 +#define NVOS32_ATTR_AA_SAMPLES_16 0x00000006 +#define NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_8 0x00000007 +#define NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_16 0x00000008 +#define NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_16 0x00000009 +#define NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_32 0x0000000A + +// +// +// GPU_CACHE_SNOOPABLE_ON signals to RM that CPU (or other IO device) +// accesses to this surface will snoop the GPU cache. +// _OFF indicates no GPU cache snooping will take place. +// _MAPPING defers the decision to mapping time. +// +// Only applies to fully coherent platforms. +// +// +#define NVOS32_ATTR_GPU_CACHE_SNOOPABLE 9:8 +#define NVOS32_ATTR_GPU_CACHE_SNOOPABLE_MAPPING 0x00000000 +#define NVOS32_ATTR_GPU_CACHE_SNOOPABLE_OFF 0x00000001 +#define NVOS32_ATTR_GPU_CACHE_SNOOPABLE_ON 0x00000002 +#define NVOS32_ATTR_GPU_CACHE_SNOOPABLE_INVALID 0x00000003 + +// Zcull region (NV40 and up) +// If ATTR_ZCULL is REQUIRED or ANY and ATTR_DEPTH is UNKNOWN, the +// allocation will fail. +// If ATTR_DEPTH or ATTR_AA_SAMPLES is not accurate, erroneous rendering +// may result. +#define NVOS32_ATTR_ZCULL 11:10 +#define NVOS32_ATTR_ZCULL_NONE 0x00000000 +#define NVOS32_ATTR_ZCULL_REQUIRED 0x00000001 +#define NVOS32_ATTR_ZCULL_ANY 0x00000002 +#define NVOS32_ATTR_ZCULL_SHARED 0x00000003 + +// Compression (NV20 and up) +// If ATTR_COMPR is REQUIRED or ANY and ATTR_DEPTH is UNKNOWN, the +// allocation will fail. +// If ATTR_DEPTH or ATTR_AA_SAMPLES is not accurate, performance will +// suffer heavily +#define NVOS32_ATTR_COMPR 13:12 +#define NVOS32_ATTR_COMPR_NONE 0x00000000 +#define NVOS32_ATTR_COMPR_REQUIRED 0x00000001 +#define NVOS32_ATTR_COMPR_ANY 0x00000002 +#define NVOS32_ATTR_COMPR_PLC_REQUIRED NVOS32_ATTR_COMPR_REQUIRED +#define NVOS32_ATTR_COMPR_PLC_ANY NVOS32_ATTR_COMPR_ANY +#define NVOS32_ATTR_COMPR_DISABLE_PLC_ANY 0x00000003 + +// +// Force the allocation to go to the reserved heap. +// This flag is used for KMD allocations when MIG is enabled. +// +#define NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP 14:14 +#define NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP_NO 0x00000000 +#define NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP_YES 0x00000001 + +// Format +// _BLOCK_LINEAR is only available for nv50+. +#define NVOS32_ATTR_FORMAT 17:16 +// Macros representing the low/high bits of NVOS32_ATTR_FORMAT +// bit range. These provide direct access to the range limits +// without needing to split the low:high representation via +// ternary operator, thereby avoiding MISRA 14.3 violation. +#define NVOS32_ATTR_FORMAT_LOW_FIELD 16 +#define NVOS32_ATTR_FORMAT_HIGH_FIELD 17 +#define NVOS32_ATTR_FORMAT_PITCH 0x00000000 +#define NVOS32_ATTR_FORMAT_SWIZZLED 0x00000001 +#define NVOS32_ATTR_FORMAT_BLOCK_LINEAR 0x00000002 + +#define NVOS32_ATTR_Z_TYPE 18:18 +#define NVOS32_ATTR_Z_TYPE_FIXED 0x00000000 +#define NVOS32_ATTR_Z_TYPE_FLOAT 0x00000001 + +#define NVOS32_ATTR_ZS_PACKING 21:19 +#define NVOS32_ATTR_ZS_PACKING_S8 0x00000000 // Z24S8 and S8 share definition +#define NVOS32_ATTR_ZS_PACKING_Z24S8 0x00000000 +#define NVOS32_ATTR_ZS_PACKING_S8Z24 0x00000001 +#define NVOS32_ATTR_ZS_PACKING_Z32 0x00000002 +#define NVOS32_ATTR_ZS_PACKING_Z24X8 0x00000003 +#define NVOS32_ATTR_ZS_PACKING_X8Z24 0x00000004 +#define NVOS32_ATTR_ZS_PACKING_Z32_X24S8 0x00000005 +#define NVOS32_ATTR_ZS_PACKING_X8Z24_X24S8 0x00000006 +#define NVOS32_ATTR_ZS_PACKING_Z16 0x00000007 +// NOTE: ZS packing and color packing fields are overlaid +#define NVOS32_ATTR_COLOR_PACKING NVOS32_ATTR_ZS_PACKING +#define NVOS32_ATTR_COLOR_PACKING_A8R8G8B8 0x00000000 +#define NVOS32_ATTR_COLOR_PACKING_X8R8G8B8 0x00000001 + + + +// +// For virtual allocs to choose page size for the region. Specifying +// _DEFAULT will select a virtual page size that allows for a surface +// to be mixed between video and system memory and allow the surface +// to be migrated between video and system memory. For tesla chips, +// 4KB will be used. For fermi chips with dual page tables, a virtual +// address with both page tables will be used. +// +// For physical allocation on chips with page swizzle this field is +// used to select the page swizzle. This later also sets the virtual +// page size, but does not have influence over selecting a migratable +// virtual address. That must be selected when mapping the physical +// memory. +// +// BIG_PAGE = 64 KB on PASCAL +// = 64 KB or 128 KB on pre_PASCAL chips +// +// HUGE_PAGE = 2 MB on PASCAL+ +// = 2 MB or 512 MB on AMPERE+ +// = not supported on pre_PASCAL chips. +// +// To request for a HUGE page size, +// set NVOS32_ATTR_PAGE_SIZE to _HUGE and NVOS32_ATTR2_PAGE_SIZE_HUGE to +// the desired size. +// +#define NVOS32_ATTR_PAGE_SIZE 24:23 +#define NVOS32_ATTR_PAGE_SIZE_DEFAULT 0x00000000 +#define NVOS32_ATTR_PAGE_SIZE_4KB 0x00000001 +#define NVOS32_ATTR_PAGE_SIZE_BIG 0x00000002 +#define NVOS32_ATTR_PAGE_SIZE_HUGE 0x00000003 + +#define NVOS32_ATTR_LOCATION 26:25 +#define NVOS32_ATTR_LOCATION_VIDMEM 0x00000000 +#define NVOS32_ATTR_LOCATION_PCI 0x00000001 +#define NVOS32_ATTR_LOCATION_ANY 0x00000003 + +// +// _DEFAULT implies _CONTIGUOUS for video memory currently, but +// may be changed to imply _NONCONTIGUOUS in the future. +// _ALLOW_NONCONTIGUOUS enables falling back to the noncontiguous +// vidmem allocator if contig allocation fails. +// +#define NVOS32_ATTR_PHYSICALITY 28:27 +#define NVOS32_ATTR_PHYSICALITY_DEFAULT 0x00000000 +#define NVOS32_ATTR_PHYSICALITY_NONCONTIGUOUS 0x00000001 +#define NVOS32_ATTR_PHYSICALITY_CONTIGUOUS 0x00000002 +#define NVOS32_ATTR_PHYSICALITY_ALLOW_NONCONTIGUOUS 0x00000003 + +#define NVOS32_ATTR_COHERENCY 31:29 +#define NVOS32_ATTR_COHERENCY_UNCACHED 0x00000000 +#define NVOS32_ATTR_COHERENCY_CACHED 0x00000001 +#define NVOS32_ATTR_COHERENCY_WRITE_COMBINE 0x00000002 +#define NVOS32_ATTR_COHERENCY_WRITE_THROUGH 0x00000003 +#define NVOS32_ATTR_COHERENCY_WRITE_PROTECT 0x00000004 +#define NVOS32_ATTR_COHERENCY_WRITE_BACK 0x00000005 + +// ATTR2 fields +#define NVOS32_ATTR2_NONE 0x00000000 + +// +// DEFAULT - Let lower level drivers pick optimal page kind. +// PREFER_NO_ZBC - Prefer other types of compression over ZBC when +// selecting page kind. +// PREFER_ZBC - Prefer ZBC over other types of compression when +// selecting page kind. +// REQUIRE_ONLY_ZBC - Require a page kind that enables ZBC but disables +// other types of compression (i.e. 2C page kind). +// INVALID - Aliases REQUIRE_ONLY_ZBC, which is not supported +// by all RM implementations. +// +#define NVOS32_ATTR2_ZBC 1:0 +#define NVOS32_ATTR2_ZBC_DEFAULT 0x00000000 +#define NVOS32_ATTR2_ZBC_PREFER_NO_ZBC 0x00000001 +#define NVOS32_ATTR2_ZBC_PREFER_ZBC 0x00000002 +#define NVOS32_ATTR2_ZBC_REQUIRE_ONLY_ZBC 0x00000003 +#define NVOS32_ATTR2_ZBC_INVALID 0x00000003 + +// +// DEFAULT - Highest performance cache policy that is coherent with the highest +// performance CPU mapping. Typically this is gpu cached for video +// memory and gpu uncached for system memory. +// YES - Enable gpu caching if supported on this surface type. For system +// memory this will not be coherent with direct CPU mappings. +// NO - Disable gpu caching if supported on this surface type. +// INVALID - Clients should never set YES and NO simultaneously. +// +#define NVOS32_ATTR2_GPU_CACHEABLE 3:2 +#define NVOS32_ATTR2_GPU_CACHEABLE_DEFAULT 0x00000000 +#define NVOS32_ATTR2_GPU_CACHEABLE_YES 0x00000001 +#define NVOS32_ATTR2_GPU_CACHEABLE_NO 0x00000002 +#define NVOS32_ATTR2_GPU_CACHEABLE_INVALID 0x00000003 + +// +// DEFAULT - GPU-dependent cache policy +// YES - Enable gpu caching for p2p mem +// NO - Disable gpu caching for p2p mem +// +#define NVOS32_ATTR2_P2P_GPU_CACHEABLE 5:4 +#define NVOS32_ATTR2_P2P_GPU_CACHEABLE_DEFAULT 0x00000000 +#define NVOS32_ATTR2_P2P_GPU_CACHEABLE_YES 0x00000001 +#define NVOS32_ATTR2_P2P_GPU_CACHEABLE_NO 0x00000002 + +// This applies to virtual allocs only. See NVOS46_FLAGS_32BIT_POINTER. +#define NVOS32_ATTR2_32BIT_POINTER 6:6 +#define NVOS32_ATTR2_32BIT_POINTER_DISABLE 0x00000000 +#define NVOS32_ATTR2_32BIT_POINTER_ENABLE 0x00000001 + +// +// Whether or not a NUMA Node ID has been specified. +// If yes, the NUMA node ID specified in numaNode will be used. +// If no, memory can be allocated from any socket (numaNode will be ignored). +// Specified numaNode must be of a CPU's memory +// + +#define NVOS32_ATTR2_FIXED_NUMA_NODE_ID 7:7 +#define NVOS32_ATTR2_FIXED_NUMA_NODE_ID_NO 0x00000000 +#define NVOS32_ATTR2_FIXED_NUMA_NODE_ID_YES 0x00000001 + +// +// Force SMMU mapping on GPU physical allocation in Tegra +// SMMU mapping for GPU physical allocation decided internally by RM +// This attribute provide an override to RM policy for verification purposes. +// +#define NVOS32_ATTR2_SMMU_ON_GPU 9:8 +#define NVOS32_ATTR2_SMMU_ON_GPU_DEFAULT 0x00000000 +#define NVOS32_ATTR2_SMMU_ON_GPU_DISABLE 0x00000001 +#define NVOS32_ATTR2_SMMU_ON_GPU_ENABLE 0x00000002 + +// Used for allocating the memory from scanout carveout. +#define NVOS32_ATTR2_USE_SCANOUT_CARVEOUT 10:10 +#define NVOS32_ATTR2_USE_SCANOUT_CARVEOUT_FALSE 0x00000000 +#define NVOS32_ATTR2_USE_SCANOUT_CARVEOUT_TRUE 0x00000001 + +// +// Make comptag allocation aligned to compression cacheline size. +// Specifying this attribute will make RM allocate comptags worth an entire +// comp cacheline. The allocation will be offset aligned to number of comptags/comp cacheline. +// +#define NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN 11:11 +#define NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_OFF 0x0 +#define NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_ON 0x1 +#define NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_DEFAULT \ + NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_OFF + +// Allocation preferred in high or low priority memory +#define NVOS32_ATTR2_PRIORITY 13:12 +#define NVOS32_ATTR2_PRIORITY_DEFAULT 0x0 +#define NVOS32_ATTR2_PRIORITY_HIGH 0x1 +#define NVOS32_ATTR2_PRIORITY_LOW 0x2 + +// PMA: Allocation is an RM internal allocation (RM-only) +#define NVOS32_ATTR2_INTERNAL 14:14 +#define NVOS32_ATTR2_INTERNAL_NO 0x0 +#define NVOS32_ATTR2_INTERNAL_YES 0x1 + +// Allocate 2C instead of 2CZ +#define NVOS32_ATTR2_PREFER_2C 15:15 +#define NVOS32_ATTR2_PREFER_2C_NO 0x00000000 +#define NVOS32_ATTR2_PREFER_2C_YES 0x00000001 + +// Allocation used by display engine; RM verifies display engine has enough +// address bits or remapper available. +#define NVOS32_ATTR2_NISO_DISPLAY 16:16 +#define NVOS32_ATTR2_NISO_DISPLAY_NO 0x00000000 +#define NVOS32_ATTR2_NISO_DISPLAY_YES 0x00000001 + +// +// !!WARNING!!! +// +// This flag is introduced as a temporary WAR to enable color compression +// without ZBC. +// +// This dangerous flag can be used by UMDs to instruct RM to skip the zbc +// table refcounting that RM does today, when the chosen PTE kind has ZBC +// support. +// +// Currently we do not have a safe per process zbc slot management and +// refcounting mechanism between RM and UMD and hence, any process can +// access any other process's zbc entry in the global zbc table (without mask) +// Inorder to flush the ZBC table for slot reuse RM cannot track which +// process is using which zbc slot. Hence RM has a global refcount for the +// zbc table to flush and reuse the entries if the PTE kind supports zbc. +// +// This scheme poses a problem if there are apps that are persistent such as +// the desktop components that can have color compression enabled which will +// always keep the refcount active. Since these apps can live without +// ZBC, UMD can disable ZBC using masks. +// +// In such a case, if UMD so chooses to disable ZBC, this flag should be used +// to skip refcounting as by default RM would refcount the ZBC table. +// +// NOTE: There is no way for RM to enforce/police this, and we totally rely +// on UMD to use a zbc mask in the pushbuffer method to prevent apps from +// accessing the ZBC table. +// +#define NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT 17:17 +#define NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_NO 0x00000000 +#define NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_YES 0x00000001 + +// Allocation requires ISO bandwidth guarantees +#define NVOS32_ATTR2_ISO 18:18 +#define NVOS32_ATTR2_ISO_NO 0x00000000 +#define NVOS32_ATTR2_ISO_YES 0x00000001 + +// +// Turn off blacklist feature for video memory allocation +// This attribute should be used only by Kernel client (KMD), to mask +// the blacklisted pages for the allocation. This is done so that the clients +// will manage the above masked blacklisted pages after the allocation. It will +// return to RM's pool after the allocation was free-d.RmVidHeapCtrl returns +// NV_ERR_INSUFFICIENT_PERMISSIONS if it is being called by non-kernel clients. +// + +// TODO: Project ReLingo - This term is marked for deletion. Use PAGE_OFFLINING. +#define NVOS32_ATTR2_BLACKLIST 19:19 +#define NVOS32_ATTR2_BLACKLIST_ON 0x00000000 +#define NVOS32_ATTR2_BLACKLIST_OFF 0x00000001 +#define NVOS32_ATTR2_PAGE_OFFLINING 19:19 +#define NVOS32_ATTR2_PAGE_OFFLINING_ON 0x00000000 +#define NVOS32_ATTR2_PAGE_OFFLINING_OFF 0x00000001 + +// +// For virtual allocs to choose the HUGE page size for the region. +// NVOS32_ATTR_PAGE_SIZE must be set to _HUGE to use this. +// Currently, the default huge page is 2MB, so a request with _DEFAULT +// set will always be interpreted as 2MB. +// Not supported on pre_AMPERE chips. +// +#define NVOS32_ATTR2_PAGE_SIZE_HUGE 21:20 +#define NVOS32_ATTR2_PAGE_SIZE_HUGE_DEFAULT 0x00000000 +#define NVOS32_ATTR2_PAGE_SIZE_HUGE_2MB 0x00000001 +#define NVOS32_ATTR2_PAGE_SIZE_HUGE_512MB 0x00000002 +#define NVOS32_ATTR2_PAGE_SIZE_HUGE_256GB 0x00000003 + +// Allow read-only or read-write user CPU mappings +#define NVOS32_ATTR2_PROTECTION_USER 22:22 +#define NVOS32_ATTR2_PROTECTION_USER_READ_WRITE 0x00000000 +#define NVOS32_ATTR2_PROTECTION_USER_READ_ONLY 0x00000001 + +// Allow read-only or read-write device mappings +#define NVOS32_ATTR2_PROTECTION_DEVICE 23:23 +#define NVOS32_ATTR2_PROTECTION_DEVICE_READ_WRITE 0x00000000 +#define NVOS32_ATTR2_PROTECTION_DEVICE_READ_ONLY 0x00000001 + +// +// Allow client allocations to go to protected/unprotected video/system memory. +// When Ampere Protected Model aka APM or Confidential Compute is enabled and +// DEFAULT flag is set by client, allocations go to protected memory. When +// protected memory is not enabled, allocations go to unprotected memory. +// If APM or CC is not enabled, it is a bug for a client to set the PROTECTED +// flag to YES +// +#define NVOS32_ATTR2_MEMORY_PROTECTION 26:25 +#define NVOS32_ATTR2_MEMORY_PROTECTION_DEFAULT 0x00000000 +#define NVOS32_ATTR2_MEMORY_PROTECTION_PROTECTED 0x00000001 +#define NVOS32_ATTR2_MEMORY_PROTECTION_UNPROTECTED 0x00000002 +// +// Force the allocation to go to guest subheap. +// This flag is used by vmiop plugin to allocate from GPA +// +#define NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP 27:27 +#define NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_NO 0x00000000 +#define NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_YES 0x00000001 + +// +// Force the video memory allocation to localized allocation. +// Same attribute can be used to choose between uGPU0 and uGPU1. +// if set to default, RM will choose the next available uGPU memory. +// if set to _UGPU0, RM will choose the memory from uGPU0. +// if set to _UGPU1, RM will choose the memory from uGPU1. +// +#define NVOS32_ATTR2_ENABLE_LOCALIZED_MEMORY 30:29 +#define NVOS32_ATTR2_ENABLE_LOCALIZED_MEMORY_DEFAULT 0x00000000 +#define NVOS32_ATTR2_ENABLE_LOCALIZED_MEMORY_UGPU0 0x00000001 +#define NVOS32_ATTR2_ENABLE_LOCALIZED_MEMORY_UGPU1 0x00000002 + +#define NVOS32_ATTR2_ENABLE_LOCALIZED_MEMORY_UGPU_COUNT 2 + +// +// When allocating memory, register the memory descriptor to GSP-RM +// so that GSP-RM is aware of and can access it +// +#define NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM 31:31 +#define NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM_FALSE 0x00000000 +#define NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM_TRUE 0x00000001 + +/** + * NVOS32 ALLOC_FLAGS + * + * NVOS32_ALLOC_FLAGS_IGNORE_BANK_PLACEMENT + * + * NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_UP + * + * NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN + * + * NVOS32_ALLOC_FLAGS_FORCE_ALIGN_HOST_PAGE + * + * NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE + * + * NVOS32_ALLOC_FLAGS_BANK_HINT + * + * NVOS32_ALLOC_FLAGS_BANK_FORCE + * + * NVOS32_ALLOC_FLAGS_ALIGNMENT_HINT + * + * NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE + * + * NVOS32_ALLOC_FLAGS_BANK_GROW_UP + * Only relevant if bank_hint or bank_force are set + * + * NVOS32_ALLOC_FLAGS_BANK_GROW_DOWN + * Only relevant if bank_hint or bank_force are set + * + * NVOS32_ALLOC_FLAGS_LAZY + * Lazy allocation (deferred pde, pagetable creation) + * + * NVOS32_ALLOC_FLAGS_NO_SCANOUT + * Set if surface will never be scanned out + * + * NVOS32_ALLOC_FLAGS_PITCH_FORCE + * Fail alloc if supplied pitch is not aligned + * + * NVOS32_ALLOC_FLAGS_MEMORY_HANDLE_PROVIDED + * Memory handle provided to be associated with this allocation + * + * NVOS32_ALLOC_FLAGS_MAP_NOT_REQUIRED + * By default memory is mapped into the CPU address space + * + * NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM + * Allocate persistent video memory + * + * NVOS32_ALLOC_FLAGS_USE_BEGIN_END + * Use rangeBegin & rangeEnd fields in allocs other than size/range + * + * NVOS32_ALLOC_FLAGS_TURBO_CIPHER_ENCRYPTED + * Allocate TurboCipher encrypted region + * + * NVOS32_ALLOC_FLAGS_VIRTUAL + * Allocate virtual memory address space + * + * NVOS32_ALLOC_FLAGS_FORCE_INTERNAL_INDEX + * Force allocation internal index + * + * NVOS32_ALLOC_FLAGS_ZCULL_COVG_SPECIFIED + * This flag is depreciated and allocations will fail. + * + * NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED + * Must be used with NVOS32_ALLOC_FLAGS_VIRTUAL. + * Page tables for this allocation will be managed outside of RM. + * + * NVOS32_ALLOC_FLAGS_FORCE_DEDICATED_PDE + * + * NVOS32_ALLOC_FLAGS_PROTECTED + * Allocate in a protected memory region if available + * + * NVOS32_ALLOC_FLAGS_KERNEL_MAPPING_MAP + * Map kernel os descriptor + * + * NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE + * On WDDM all address spaces are created with MINIMIZE_PTETABLE_SIZE + * to reduce the overhead of private address spaces per application, + * at the cost of holes in the virtual address space. + * + * Shaders have short pointers that are required to be within a + * GPU dependent 32b range. + * + * MAXIMIZE_ADDRESS_SPACE will reverse the MINIMIZE_PTE_TABLE_SIZE + * flag with certain restrictions: + * - This flag only has an effect when the allocation has the side + * effect of creating a new PDE. It does not affect existing PDEs. + * - The first few PDEs of the address space are kept minimum to allow + * small applications to use fewer resources. + * - By default this operations on the 0-4GB address range. + * - If USE_BEGIN_END is specified the setting will apply to the + * specified range instead of the first 4GB. + * + * NVOS32_ALLOC_FLAGS_SPARSE + * Denote that a virtual address range is "sparse". Must be used with + * NVOS32_ALLOC_FLAGS_VIRTUAL. Creation of a "sparse" virtual address range + * denotes that an unmapped virtual address range should "not" fault but simply + * return 0's. + * + * NVOS32_ALLOC_FLAGS_SKIP_RESOURCE_ALLOC + * + * NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY + * If new pagetable need to be allocated prefer them in sysmem (if supported by the gpu) + * + * NVOS32_ALLOC_FLAGS_SKIP_ALIGN_PAD + * As per KMD request to eliminate extra allocation + * + * NVOS32_ALLOC_FLAGS_WPR1 + * Allocate in a WPR1 region if available + * + * NVOS32_ALLOC_FLAGS_ZCULL_DONT_ALLOCATE_SHARED_1X + * If using zcull sharing and this surface is fsaa, then don't allocate an additional non-FSAA region. + * + * NVOS32_ALLOC_FLAGS_WPR2 + * Allocate in a WPR1 region if available + */ +#define NVOS32_ALLOC_FLAGS_IGNORE_BANK_PLACEMENT 0x00000001 +#define NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_UP 0x00000002 +#define NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN 0x00000004 +#define NVOS32_ALLOC_FLAGS_FORCE_ALIGN_HOST_PAGE 0x00000008 +#define NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE 0x00000010 +#define NVOS32_ALLOC_FLAGS_BANK_HINT 0x00000020 +#define NVOS32_ALLOC_FLAGS_BANK_FORCE 0x00000040 +#define NVOS32_ALLOC_FLAGS_ALIGNMENT_HINT 0x00000080 +#define NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE 0x00000100 +#define NVOS32_ALLOC_FLAGS_BANK_GROW_UP 0x00000000 +#define NVOS32_ALLOC_FLAGS_BANK_GROW_DOWN 0x00000200 +#define NVOS32_ALLOC_FLAGS_LAZY 0x00000400 +#define NVOS32_ALLOC_FLAGS_FORCE_REVERSE_ALLOC 0x00000800 +#define NVOS32_ALLOC_FLAGS_NO_SCANOUT 0x00001000 +#define NVOS32_ALLOC_FLAGS_PITCH_FORCE 0x00002000 +#define NVOS32_ALLOC_FLAGS_MEMORY_HANDLE_PROVIDED 0x00004000 +#define NVOS32_ALLOC_FLAGS_MAP_NOT_REQUIRED 0x00008000 +#define NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM 0x00010000 +#define NVOS32_ALLOC_FLAGS_USE_BEGIN_END 0x00020000 +#define NVOS32_ALLOC_FLAGS_TURBO_CIPHER_ENCRYPTED 0x00040000 +#define NVOS32_ALLOC_FLAGS_VIRTUAL 0x00080000 +#define NVOS32_ALLOC_FLAGS_FORCE_INTERNAL_INDEX 0x00100000 +#define NVOS32_ALLOC_FLAGS_ZCULL_COVG_SPECIFIED 0x00200000 +#define NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED 0x00400000 +#define NVOS32_ALLOC_FLAGS_FORCE_DEDICATED_PDE 0x00800000 +#define NVOS32_ALLOC_FLAGS_PROTECTED 0x01000000 +#define NVOS32_ALLOC_FLAGS_KERNEL_MAPPING_MAP 0x02000000 // TODO BUG 2488679: fix alloc flag aliasing +#define NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE 0x02000000 +#define NVOS32_ALLOC_FLAGS_SPARSE 0x04000000 +#define NVOS32_ALLOC_FLAGS_USER_READ_ONLY 0x04000000 // TODO BUG 2488682: remove this after KMD transition +#define NVOS32_ALLOC_FLAGS_DEVICE_READ_ONLY 0x08000000 // TODO BUG 2488682: remove this after KMD transition +#define NVOS32_ALLOC_FLAGS_SKIP_RESOURCE_ALLOC 0x10000000 +#define NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY 0x20000000 +#define NVOS32_ALLOC_FLAGS_SKIP_ALIGN_PAD 0x40000000 +#define NVOS32_ALLOC_FLAGS_WPR1 0x40000000 // TODO BUG 2488672: fix alloc flag aliasing +#define NVOS32_ALLOC_FLAGS_ZCULL_DONT_ALLOCATE_SHARED_1X 0x80000000 +#define NVOS32_ALLOC_FLAGS_WPR2 0x80000000 // TODO BUG 2488672: fix alloc flag aliasing + +// Internal flags used for RM's allocation paths +#define NVOS32_ALLOC_INTERNAL_FLAGS_CLIENTALLOC 0x00000001 // RM internal flags - not sure if this should be exposed even. Keeping it here. +#define NVOS32_ALLOC_INTERNAL_FLAGS_SKIP_SCRUB 0x00000004 // RM internal flags - not sure if this should be exposed even. Keeping it here. +#define NVOS32_ALLOC_FLAGS_MAXIMIZE_4GB_ADDRESS_SPACE NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE // Legacy name + +// +// Bitmask of flags that are only valid for virtual allocations. +// +#define NVOS32_ALLOC_FLAGS_VIRTUAL_ONLY ( \ + NVOS32_ALLOC_FLAGS_VIRTUAL | \ + NVOS32_ALLOC_FLAGS_LAZY | \ + NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED | \ + NVOS32_ALLOC_FLAGS_SPARSE | \ + NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE | \ + NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY ) + +// COMPR_COVG_* allows for specification of what compression resources +// are required (_MIN) and necessary (_MAX). Default behavior is for +// RM to provide as much as possible, including none if _ANY is allowed. +// Values for min/max are (0-100, a %) * _COVG_SCALE (so max value is +// 100*100==10000). _START is used to specify the % offset into the +// region to begin the requested coverage. +// _COVG_BITS allows specification of the number of comptags per ROP tile. +// A value of 0 is default and allows RM to choose based upon MMU/FB rules. +// All other values for _COVG_BITS are arch-specific. +// Note: NVOS32_ATTR_COMPR_COVG_PROVIDED must be set for this feature +// to be available (verif-only). +#define NVOS32_ALLOC_COMPR_COVG_SCALE 10 +#define NVOS32_ALLOC_COMPR_COVG_BITS 1:0 +#define NVOS32_ALLOC_COMPR_COVG_BITS_DEFAULT 0x00000000 +#define NVOS32_ALLOC_COMPR_COVG_BITS_1 0x00000001 +#define NVOS32_ALLOC_COMPR_COVG_BITS_2 0x00000002 +#define NVOS32_ALLOC_COMPR_COVG_BITS_4 0x00000003 +#define NVOS32_ALLOC_COMPR_COVG_MAX 11:2 +#define NVOS32_ALLOC_COMPR_COVG_MIN 21:12 +#define NVOS32_ALLOC_COMPR_COVG_START 31:22 + + +// Note: NVOS32_ALLOC_FLAGS_ZCULL_COVG_SPECIFIED must be set for this feature +// to be enabled. +// If FALLBACK_ALLOW is set, a fallback from LOW_RES_Z or LOW_RES_ZS +// to HIGH_RES_Z is allowed if the surface can't be fully covered. +#define NVOS32_ALLOC_ZCULL_COVG_FORMAT 3:0 +#define NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_Z 0x00000000 +#define NVOS32_ALLOC_ZCULL_COVG_FORMAT_HIGH_RES_Z 0x00000002 +#define NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_ZS 0x00000003 +#define NVOS32_ALLOC_ZCULL_COVG_FALLBACK 4:4 +#define NVOS32_ALLOC_ZCULL_COVG_FALLBACK_DISALLOW 0x00000000 +#define NVOS32_ALLOC_ZCULL_COVG_FALLBACK_ALLOW 0x00000001 + + +// _ALLOC_COMPTAG_OFFSET allows the caller to specify the starting +// offset for the comptags for a given surface, primarily for test only. +// To specify an offset, set _USAGE_FIXED or _USAGE_MIN in conjunction +// with _START. +// +// _USAGE_FIXED sets a surface's comptagline to start at the given +// starting value. If the offset has already been assigned, then +// the alloc call fails. +// +// _USAGE_MIN sets a surface's comptagline to start at the given +// starting value or higher, depending on comptagline availability. +// In this case, if the offset has already been assigned, the next +// available comptagline (in increasing order) will be assigned. +// +// For Fermi, up to 2^17 comptags may be allowed, but the actual, +// usable limit depends on the size of the compbit backing store. +// +// For Pascal, up to 2 ^ 18 comptags may be allowed +// From Turing. up to 2 ^ 20 comptags may be allowed +// +// See also field ctagOffset in struct NVOS32_PARAMETERS. +#define NVOS32_ALLOC_COMPTAG_OFFSET_START 19:0 +#define NVOS32_ALLOC_COMPTAG_OFFSET_START_DEFAULT 0x00000000 +#define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE 31:30 +#define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_DEFAULT 0x00000000 +#define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_OFF 0x00000000 +#define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_FIXED 0x00000001 +#define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_MIN 0x00000002 + + +// REALLOC flags field +#define NVOS32_REALLOC_FLAGS_GROW_ALLOCATION 0x00000000 +#define NVOS32_REALLOC_FLAGS_SHRINK_ALLOCATION 0x00000001 +#define NVOS32_REALLOC_FLAGS_REALLOC_UP 0x00000000 // towards/from high memory addresses +#define NVOS32_REALLOC_FLAGS_REALLOC_DOWN 0x00000002 // towards/from memory address 0 + +// RELEASE_COMPR, REACQUIRE_COMPR flags field +#define NVOS32_RELEASE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED 0x000000001 + +#define NVOS32_REACQUIRE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED 0x000000001 + + +// FREE flags field +#define NVOS32_FREE_FLAGS_MEMORY_HANDLE_PROVIDED 0x00000001 + +// DUMP flags field +#define NVOS32_DUMP_FLAGS_TYPE 1:0 +#define NVOS32_DUMP_FLAGS_TYPE_FB 0x00000000 +#define NVOS32_DUMP_FLAGS_TYPE_CLIENT_PD 0x00000001 +#define NVOS32_DUMP_FLAGS_TYPE_CLIENT_VA 0x00000002 +#define NVOS32_DUMP_FLAGS_TYPE_CLIENT_VAPTE 0x00000003 + +#define NVOS32_BLOCK_TYPE_FREE 0xFFFFFFFF +#define NVOS32_INVALID_BLOCK_FREE_OFFSET 0xFFFFFFFF + +#define NVOS32_MEM_TAG_NONE 0x00000000 + +/* + * NV_CONTEXT_DMA_ALLOCATION_PARAMS - Allocation params to create context dma + through NvRmAlloc. + */ +typedef struct +{ + NvHandle hSubDevice; + NvV32 flags; + NvHandle hMemory; + NvU64 offset NV_ALIGN_BYTES(8); + NvU64 limit NV_ALIGN_BYTES(8); +} NV_CONTEXT_DMA_ALLOCATION_PARAMS; + +/* + * NV_MEMORY_ALLOCATION_PARAMS - Allocation params to create memory through + * NvRmAlloc. Flags are populated with NVOS32_ defines. + */ +typedef struct +{ + NvU32 owner; // [IN] - memory owner ID + NvU32 type; // [IN] - surface type, see below TYPE* defines + NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines + + NvU32 width; // [IN] - width of surface in pixels + NvU32 height; // [IN] - height of surface in pixels + NvS32 pitch; // [IN/OUT] - desired pitch AND returned actual pitch allocated + + NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated + + NvU32 format; // [IN/OUT] - format requested, and format allocated + NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated + NvU32 zcullCovg; // [OUT] - zcull covg allocated + + NvU64 rangeLo NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range + NvU64 rangeHi NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive. + + NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated + NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on + NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset + NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit + NvP64 address NV_ALIGN_BYTES(8); // [OUT] - returned address + + NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET) + NvHandle hVASpace; // [IN] - VASpace handle. Used when flag is VIRTUAL. + + NvU32 internalflags; // [IN] - internal flags to change allocation behaviors from internal paths + + NvU32 tag; // [IN] - memory tag used for debugging + + NvS32 numaNode; // [IN] - CPU NUMA node from which memory should be allocated +} NV_MEMORY_ALLOCATION_PARAMS; + +/* + * NV_OS_DESC_MEMORY_ALLOCATION_PARAMS - Allocation params to create OS + * described memory through NvRmAlloc. Flags are populated with NVOS32_ defines. + */ +typedef struct +{ + NvU32 type; // [IN] - surface type, see below TYPE* defines + NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines + NvU32 attr; // [IN] - attributes for memory placement/properties, see below + NvU32 attr2; // [IN] - attributes GPU_CACHEABLE + NvP64 descriptor NV_ALIGN_BYTES(8); // [IN] - descriptor address + NvU64 limit NV_ALIGN_BYTES(8); // [IN] - allocated size -1 + NvU32 descriptorType; // [IN] - descriptor type(Virtual | nvmap Handle) + NvU32 tag; // [IN] - memory tag used for debugging +} NV_OS_DESC_MEMORY_ALLOCATION_PARAMS; + +/* + * NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS - Allocation params to create a memory + * object from user allocated video memory. Flags are populated with NVOS32_* + * defines. + */ +typedef struct +{ + NvU32 flags; // [IN] - allocation modifier flags, see NVOS02_FLAGS* defines + NvU64 physAddr NV_ALIGN_BYTES(8); // [IN] - physical address + NvU64 size NV_ALIGN_BYTES(8); // [IN] - mem size + NvU32 tag; // [IN] - memory tag used for debugging + NvBool bGuestAllocated; // [IN] - Set if memory is guest allocated (mapped by VMMU) +} NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS; + +/* + * NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS - Allocation params to create + * memory HW resources through NvRmAlloc. Flags are populated with NVOS32_ + * defines. + */ +typedef struct +{ + NvU32 owner; // [IN] - memory owner ID + NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines + NvU32 type; // [IN] - surface type, see below TYPE* defines + + NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated + + NvU32 height; + NvU32 width; + NvU32 pitch; + NvU32 alignment; + NvU32 comprCovg; + NvU32 zcullCovg; + + NvU32 kind; + + NvP64 bindResultFunc NV_ALIGN_BYTES(8); // BindResultFunc + NvP64 pHandle NV_ALIGN_BYTES(8); + NvU64 osDeviceHandle NV_ALIGN_BYTES(8); + NvU64 size NV_ALIGN_BYTES(8); + NvU64 allocAddr NV_ALIGN_BYTES(8); + + // [out] from GMMU_COMPR_INFO in drivers/common/shared/inc/mmu/gmmu_fmt.h + NvU32 compPageShift; + NvU32 compressedKind; + NvU32 compTagLineMin; + NvU32 compPageIndexLo; + NvU32 compPageIndexHi; + NvU32 compTagLineMultiplier; + + // [out] fallback uncompressed kind. + NvU32 uncompressedKind; + + NvU32 tag; // [IN] - memory tag used for debugging +} NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS; + +/* function OS33 */ +#define NV04_MAP_MEMORY (0x00000021) + +// Legacy map and unmap memory flags that don't use DRF_DEF scheme +#define NV04_MAP_MEMORY_FLAGS_NONE (0x00000000) +#define NV04_MAP_MEMORY_FLAGS_USER (0x00004000) + +// New map and unmap memory flags. These flags are used for both NvRmMapMemory +// and for NvRmUnmapMemory. + +// Mappings can have restricted permissions (read-only, write-only). Some +// RM implementations may choose to ignore these flags, or they may work +// only for certain memory spaces (system, video memory); in such cases, +// you may get a read/write mapping even if you asked for a read-only or +// write-only mapping. +#define NVOS33_FLAGS_ACCESS 1:0 +#define NVOS33_FLAGS_ACCESS_READ_WRITE (0x00000000) +#define NVOS33_FLAGS_ACCESS_READ_ONLY (0x00000001) +#define NVOS33_FLAGS_ACCESS_WRITE_ONLY (0x00000002) + +// Persistent mappings are no longer supported +#define NVOS33_FLAGS_PERSISTENT 4:4 +#define NVOS33_FLAGS_PERSISTENT_DISABLE (0x00000000) +#define NVOS33_FLAGS_PERSISTENT_ENABLE (0x00000001) + +// This flag is a hack to work around bug 150889. It disables the error +// checking in the RM that verifies that the client is not trying to map +// memory past the end of the memory object. This error checking needs to +// be shut off in some cases for a PAE bug workaround in certain kernels. +#define NVOS33_FLAGS_SKIP_SIZE_CHECK 8:8 +#define NVOS33_FLAGS_SKIP_SIZE_CHECK_DISABLE (0x00000000) +#define NVOS33_FLAGS_SKIP_SIZE_CHECK_ENABLE (0x00000001) + +// Normally, a mapping is created in the same memory space as the client -- in +// kernel space for a kernel RM client, or in user space for a user RM client. +// However, a kernel RM client can specify MEM_SPACE:USER to create a user-space +// mapping in the current RM client. +#define NVOS33_FLAGS_MEM_SPACE 14:14 +#define NVOS33_FLAGS_MEM_SPACE_CLIENT (0x00000000) +#define NVOS33_FLAGS_MEM_SPACE_USER (0x00000001) + +// The client can ask for direct memory mapping (i.e. no BAR1) if remappers and +// blocklinear are not required. RM can do direct mapping in this case if +// carveout is available. +// DEFAULT: Use direct mapping if available and no address/data translation +// is necessary; reflected otherwise +// DIRECT: Use direct mapping if available, even if some translation is +// necessary (the client is responsible for translation) +// REFLECTED: Always use reflected mapping +#define NVOS33_FLAGS_MAPPING 16:15 +#define NVOS33_FLAGS_MAPPING_DEFAULT (0x00000000) +#define NVOS33_FLAGS_MAPPING_DIRECT (0x00000001) +#define NVOS33_FLAGS_MAPPING_REFLECTED (0x00000002) + +// The client requests a fifo mapping but doesn't know the offset or length +// DEFAULT: Do error check length and offset +// ENABLE: Don't error check length and offset but have the RM fill them in +#define NVOS33_FLAGS_FIFO_MAPPING 17:17 +#define NVOS33_FLAGS_FIFO_MAPPING_DEFAULT (0x00000000) +#define NVOS33_FLAGS_FIFO_MAPPING_ENABLE (0x00000001) + +// The client can require that the CPU mapping be to a specific CPU address +// (akin to MAP_FIXED for mmap). +// DISABLED: RM will map the allocation at a CPU VA that RM selects. +// ENABLED: RM will map the allocation at the CPU VA specified by the address +// pass-back parameter to NvRmMapMemory +// NOTES: +// - Used for controlling CPU addresses in CUDA's unified CPU+GPU virtual +// address space +// - Only valid on NvRmMapMemory +// - Implemented on Unix but not VMware +#define NVOS33_FLAGS_MAP_FIXED 18:18 +#define NVOS33_FLAGS_MAP_FIXED_DISABLE (0x00000000) +#define NVOS33_FLAGS_MAP_FIXED_ENABLE (0x00000001) + +// The client can specify to the RM that the CPU virtual address range for an +// allocation should remain reserved after the allocation is unmapped. +// DISABLE: When this mapping is destroyed, RM will unmap the CPU virtual +// address space used by this allocation. On Linux this corresponds +// to calling munmap on the CPU VA region. +// ENABLE: When the map object is freed, RM will leave the CPU virtual +// address space used by allocation reserved. On Linux this means +// that RM will overwrite the previous mapping with an anonymous +// mapping of instead calling munmap. +// NOTES: +// - When combined with MAP_FIXED, this allows the client to exert +// significant control over the CPU heap +// - Used in CUDA's unified CPU+GPU virtual address space +// - Valid in nvRmUnmapMemory +// - Valid on NvRmMapMemory (specifies RM's behavior whenever the +// mapping is destroyed, regardless of mechanism) +// - Implemented on Unix but not VMware +#define NVOS33_FLAGS_RESERVE_ON_UNMAP 19:19 +#define NVOS33_FLAGS_RESERVE_ON_UNMAP_DISABLE (0x00000000) +#define NVOS33_FLAGS_RESERVE_ON_UNMAP_ENABLE (0x00000001) + +// +// Internal use only +// Can be used to set mappings path to PCIe when coherent C2C link is present +// +#define NVOS33_FLAGS_BUS 21:20 +#define NVOS33_FLAGS_BUS_DEFAULT 0 +#define NVOS33_FLAGS_BUS_COHERENT_LINK 1 +#define NVOS33_FLAGS_BUS_PCIE 2 + +// Internal use only +#define NVOS33_FLAGS_OS_DESCRIPTOR 22:22 +#define NVOS33_FLAGS_OS_DESCRIPTOR_DISABLE (0x00000000) +#define NVOS33_FLAGS_OS_DESCRIPTOR_ENABLE (0x00000001) + +// +// For use in the linux mapping path. This flag sets the +// caching mode for pcie BAR mappings (from nv_memory_type.h). +// Internal use only. +// +#define NVOS33_FLAGS_CACHING_TYPE 25:23 +#define NVOS33_FLAGS_CACHING_TYPE_CACHED 0 +#define NVOS33_FLAGS_CACHING_TYPE_UNCACHED 1 +#define NVOS33_FLAGS_CACHING_TYPE_WRITECOMBINED 2 +#define NVOS33_FLAGS_CACHING_TYPE_WRITEBACK 5 +#define NVOS33_FLAGS_CACHING_TYPE_DEFAULT 6 +#define NVOS33_FLAGS_CACHING_TYPE_UNCACHED_WEAK 7 + +// +// For use when Hopper Confidential Compute is operating in devtools mode +// BAR1 access to CPR vidmem is blocked to CPU-RM by default when HCC is +// enabled in both devtools and prod modes. However, certain mappings are +// allowed to go through successfully only in devtools mode. For example, +// CPU mappings made on behalf of devtools, event buffer mappings are allowed +// to happen in devtools mode +// +#define NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC 26:26 +#define NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC_NO (0x00000000) +#define NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC_YES (0x00000001) + +/* parameters */ +typedef struct +{ + NvHandle hClient; + NvHandle hDevice; // device or sub-device handle + NvHandle hMemory; // handle to memory object if provided -- NULL if not + NvU64 offset NV_ALIGN_BYTES(8); + NvU64 length NV_ALIGN_BYTES(8); + NvP64 pLinearAddress NV_ALIGN_BYTES(8); // pointer for returned address + NvU32 status; + NvU32 flags; +} NVOS33_PARAMETERS; + + +/* function OS34 */ +#define NV04_UNMAP_MEMORY (0x00000022) + +/* parameters */ +typedef struct +{ + NvHandle hClient; + NvHandle hDevice; + NvHandle hMemory; + NvP64 pLinearAddress NV_ALIGN_BYTES(8); // ptr to virtual address of mapped memory + NvU32 status; + NvU32 flags; +} NVOS34_PARAMETERS; + +/* function OS38 */ +#define NV04_ACCESS_REGISTRY (0x00000026) + +/* parameter values */ +#define NVOS38_ACCESS_TYPE_READ_DWORD 1 +#define NVOS38_ACCESS_TYPE_WRITE_DWORD 2 +#define NVOS38_ACCESS_TYPE_READ_BINARY 6 +#define NVOS38_ACCESS_TYPE_WRITE_BINARY 7 + +#define NVOS38_MAX_REGISTRY_STRING_LENGTH 256 +#define NVOS38_MAX_REGISTRY_BINARY_LENGTH 256 + +/* parameters */ +typedef struct +{ + NvHandle hClient; + NvHandle hObject; + NvV32 AccessType; + + NvV32 DevNodeLength; + NvP64 pDevNode NV_ALIGN_BYTES(8); + + NvV32 ParmStrLength; + NvP64 pParmStr NV_ALIGN_BYTES(8); + + NvV32 BinaryDataLength; + NvP64 pBinaryData NV_ALIGN_BYTES(8); + + NvV32 Data; + NvV32 Entry; + NvV32 status; +} NVOS38_PARAMETERS; + +#define NV04_ALLOC_CONTEXT_DMA (0x00000027) + +/* parameter values are the same as NVOS03 -- not repeated here */ + +/* parameters */ +typedef struct +{ + NvHandle hObjectParent; + NvHandle hSubDevice; + NvHandle hObjectNew; + NvV32 hClass; + NvV32 flags; + NvU32 selector; + NvHandle hMemory; + NvU64 offset NV_ALIGN_BYTES(8); + NvU64 limit NV_ALIGN_BYTES(8); + NvV32 status; +} NVOS39_PARAMETERS; + + +#define NV04_GET_EVENT_DATA (0x00000028) + +typedef struct +{ + NvHandle hObject; + NvV32 NotifyIndex; + + // + // Holds same information as that of nvgputypes.h::NvNotification's + // info32 and info16. + // + NvV32 info32; + NvU16 info16; +} NvUnixEvent; + +/* parameters */ +typedef struct +{ + NvP64 pEvent NV_ALIGN_BYTES(8); + NvV32 MoreEvents; + NvV32 status; +} NVOS41_PARAMETERS; + +/* function NVOS43 -- deleted 4/09 */ +/* #define NV04_UNIFIED_FREE (0x0000002B) */ + + +#define NVSIM01_BUS_XACT (0x0000002C) + +/* parameters */ +typedef struct +{ + NvHandle hClient; // n/a currently + NvHandle hDevice; // n/a currently + NvU32 offset; // phy bus offset + NvU32 bar; // ~0 := phy addr, {0..2} specify gpu bar + NvU32 bytes; // # of bytes + NvU32 write; // 0 := read request + NvU32 data; // in/out based upon 'write' + NvU32 status; +} NVOS2C_PARAMETERS; + +/* function NVOS2D -- deleted 4/09 */ +/* #define NVSIM01_BUS_GET_IFACES (0x0000002D) */ + + +/* function OS46 */ +#define NV04_MAP_MEMORY_DMA (0x0000002E) + +/* parameter values */ +#define NVOS46_FLAGS_ACCESS 1:0 +#define NVOS46_FLAGS_ACCESS_READ_WRITE (0x00000000) +#define NVOS46_FLAGS_ACCESS_READ_ONLY (0x00000001) +#define NVOS46_FLAGS_ACCESS_WRITE_ONLY (0x00000002) + +// +// Compute shaders support both 32b and 64b pointers. This allows mappings +// to be restricted to the bottom 4GB of the address space. How _DISABLE +// is handled is chip specific and may force a pointer above 4GB. +// +#define NVOS46_FLAGS_32BIT_POINTER 2:2 +#define NVOS46_FLAGS_32BIT_POINTER_DISABLE (0x00000000) +#define NVOS46_FLAGS_32BIT_POINTER_ENABLE (0x00000001) + +#define NVOS46_FLAGS_PAGE_KIND 3:3 +#define NVOS46_FLAGS_PAGE_KIND_PHYSICAL (0x00000000) +#define NVOS46_FLAGS_PAGE_KIND_VIRTUAL (0x00000001) + +#define NVOS46_FLAGS_CACHE_SNOOP 4:4 +#define NVOS46_FLAGS_CACHE_SNOOP_DISABLE (0x00000000) +#define NVOS46_FLAGS_CACHE_SNOOP_ENABLE (0x00000001) + +// The client requests a CPU kernel mapping so that SW class could use it +// DEFAULT: Don't map CPU address +// ENABLE: Map CPU address +#define NVOS46_FLAGS_KERNEL_MAPPING 5:5 +#define NVOS46_FLAGS_KERNEL_MAPPING_NONE (0x00000000) +#define NVOS46_FLAGS_KERNEL_MAPPING_ENABLE (0x00000001) + +// +// Compute shader access control. +// GPUs that support this feature set the NV0080_CTRL_DMA_CAPS_SHADER_ACCESS_SUPPORTED +// property. These were first supported in Kepler. _DEFAULT will match the ACCESS field. +// +#define NVOS46_FLAGS_SHADER_ACCESS 7:6 +#define NVOS46_FLAGS_SHADER_ACCESS_DEFAULT (0x00000000) +#define NVOS46_FLAGS_SHADER_ACCESS_READ_ONLY (0x00000001) +#define NVOS46_FLAGS_SHADER_ACCESS_WRITE_ONLY (0x00000002) +#define NVOS46_FLAGS_SHADER_ACCESS_READ_WRITE (0x00000003) + +// +// How the PAGE_SIZE field is interpreted is architecture specific. +// +// On Curie chips it is ignored. +// +// On Tesla it is used to guide is used to select which type PDE +// to use. By default the RM will select 4KB for system memory +// and BIG (64KB) for video memory. BOTH is not supported. +// +// Likewise on Fermi this used to select the PDE type. Fermi cannot +// mix page sizes to a single mapping so the page size is determined +// at surface alloation time. 4KB or BIG may be specified but they +// must match the page size selected at allocation time. DEFAULT +// allows the RM to select either a single page size or both PDE, +// while BOTH forces the RM to select a dual page size PDE. +// +// BIG_PAGE = 64 KB on PASCAL +// = 64 KB or 128 KB on pre_PASCAL chips +// +// HUGE_PAGE = 2 MB on PASCAL +// = not supported on pre_PASCAL chips. +// +#define NVOS46_FLAGS_PAGE_SIZE 11:8 +#define NVOS46_FLAGS_PAGE_SIZE_DEFAULT (0x00000000) +#define NVOS46_FLAGS_PAGE_SIZE_4KB (0x00000001) +#define NVOS46_FLAGS_PAGE_SIZE_BIG (0x00000002) +#define NVOS46_FLAGS_PAGE_SIZE_BOTH (0x00000003) +#define NVOS46_FLAGS_PAGE_SIZE_HUGE (0x00000004) +#define NVOS46_FLAGS_PAGE_SIZE_512M (0x00000005) + +// Some systems allow the device to use the system L3 cache when accessing the +// system memory. For example, the iGPU on T19X can allocate from the system L3 +// provided the SoC L3 cache is configured for device allocation. +// +// NVOS46_FLAGS_SYSTEM_L3_ALLOC_DEFAULT - Use the default L3 allocation +// policy. When using this policy, device memory access will be coherent with +// non-snooping devices such as the display on Tegra. +// +// NVOS46_FLAGS_SYSTEM_L3_ALLOC_ENABLE_HINT - Enable L3 allocation if possible. +// When L3 allocation is enabled, device memory access may be cached, and the +// memory access will be coherent only with other snoop-enabled access. This +// flag is a hint and will be ignored if the system does not support L3 +// allocation for the device. NVOS46_FLAGS_CACHE_SNOOP_ENABLE must also be set +// for this flag to be effective. +// +// Note: This flag is implemented only by rmapi_tegra. It is not implemented by +// Resman. +// +#define NVOS46_FLAGS_SYSTEM_L3_ALLOC 13:13 +#define NVOS46_FLAGS_SYSTEM_L3_ALLOC_DEFAULT (0x00000000) +#define NVOS46_FLAGS_SYSTEM_L3_ALLOC_ENABLE_HINT (0x00000001) + +#define NVOS46_FLAGS_DMA_OFFSET_GROWS 14:14 +#define NVOS46_FLAGS_DMA_OFFSET_GROWS_UP (0x00000000) +#define NVOS46_FLAGS_DMA_OFFSET_GROWS_DOWN (0x00000001) + +// +// DMA_OFFSET_FIXED is overloaded for two purposes. +// +// 1. For CTXDMA mappings that use DMA_UNICAST_REUSE_ALLOC_FALSE, +// DMA_OFFSET_FIXED_TRUE indicates to use the dmaOffset parameter +// for a fixed address allocation out of the VA space heap. +// DMA_OFFSET_FIXED_FALSE indicates dmaOffset input will be ignored. +// +// 2. For CTXDMA mappings that use DMA_UNICAST_REUSE_ALLOC_TRUE and +// for *ALL* non-CTXDMA mappings, DMA_OFFSET_FIXED_TRUE indicates +// to treat the input dmaOffset as an absolute virtual address +// instead of an offset relative to the virtual allocation being +// mapped into. Whether relative or absolute, the resulting +// virtual address *must* be contained within the specified +// virtual allocation. +// +// Internally, it is also required that the virtual address be aligned +// to the page size of the mapping (obviously cannot map sub-pages). +// For client flexibility the physical offset does not require page alignment. +// This is handled by adding the physical misalignment +// (internally called pteAdjust) to the returned virtual address. +// The *input* dmaOffset can account for this pteAdjust (or not), +// but the returned virtual address always will. +// +#define NVOS46_FLAGS_DMA_OFFSET_FIXED 15:15 +#define NVOS46_FLAGS_DMA_OFFSET_FIXED_FALSE (0x00000000) +#define NVOS46_FLAGS_DMA_OFFSET_FIXED_TRUE (0x00000001) + +#define NVOS46_FLAGS_DISABLE_ENCRYPTION 16:16 +#define NVOS46_FLAGS_DISABLE_ENCRYPTION_FALSE (0x00000000) +#define NVOS46_FLAGS_DISABLE_ENCRYPTION_TRUE (0x00000001) + +// +// DEFAULT - Use the cache policy set at allocation +// YES - Enable gpu caching +// NO - Disable gpu caching +// +#define NVOS46_FLAGS_GPU_CACHEABLE 18:17 +#define NVOS46_FLAGS_GPU_CACHEABLE_DEFAULT (0x00000000) +#define NVOS46_FLAGS_GPU_CACHEABLE_YES (0x00000001) +#define NVOS46_FLAGS_GPU_CACHEABLE_NO (0x00000002) +#define NVOS46_FLAGS_GPU_CACHEABLE_INVALID (0x00000003) + +#define NVOS46_FLAGS_PAGE_KIND_OVERRIDE 19:19 +#define NVOS46_FLAGS_PAGE_KIND_OVERRIDE_NO (0x00000000) +#define NVOS46_FLAGS_PAGE_KIND_OVERRIDE_YES (0x00000001) + +#define NVOS46_FLAGS_P2P 27:20 + +#define NVOS46_FLAGS_P2P_ENABLE 21:20 +#define NVOS46_FLAGS_P2P_ENABLE_NO (0x00000000) +#define NVOS46_FLAGS_P2P_ENABLE_YES (0x00000001) +#define NVOS46_FLAGS_P2P_ENABLE_NONE NVOS46_FLAGS_P2P_ENABLE_NO +#define NVOS46_FLAGS_P2P_ENABLE_SLI NVOS46_FLAGS_P2P_ENABLE_YES +#define NVOS46_FLAGS_P2P_ENABLE_NOSLI (0x00000002) +// Subdevice ID. Reserved 3 bits for the possibility of 8-way SLI +#define NVOS46_FLAGS_P2P_SUBDEVICE_ID 24:22 +#define NVOS46_FLAGS_P2P_SUBDEV_ID_SRC NVOS46_FLAGS_P2P_SUBDEVICE_ID +#define NVOS46_FLAGS_P2P_SUBDEV_ID_TGT 27:25 +#define NVOS46_FLAGS_TLB_LOCK 28:28 +#define NVOS46_FLAGS_TLB_LOCK_DISABLE (0x00000000) +#define NVOS46_FLAGS_TLB_LOCK_ENABLE (0x00000001) +#define NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC 29:29 +#define NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_FALSE (0x00000000) +#define NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_TRUE (0x00000001) +// +// Force pte kind to compresssed for this and future mappings of the memory object +// Only affects mappings using NVOS46_FLAGS_PAGE_KIND_VIRTUAL +// Only has effect when physical allocation is compressed +// +#define NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP 30:30 +#define NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP_FALSE (0x00000000) +#define NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP_TRUE (0x00000001) + +// +// This flag must be used with caution. Improper use can leave stale entries in the TLB, +// and allow access to memory no longer owned by the RM client or cause page faults. +// Also see corresponding flag for NvUnmapMemoryDma. +// +#define NVOS46_FLAGS_DEFER_TLB_INVALIDATION 31:31 +#define NVOS46_FLAGS_DEFER_TLB_INVALIDATION_FALSE (0x00000000) +#define NVOS46_FLAGS_DEFER_TLB_INVALIDATION_TRUE (0x00000001) + +// +// This flag is used on fully coherent platforms to specify whether the GPU cache +// should be snooped by the CPU or other IO devices for this mapping. +// +// Only takes effect if the physical memory is allocated with +// _ATTR_GPU_CACHE_SNOOPABLE_MAPPING indicating the decision +// should be deferred to map time. +// +#define NVOS46_FLAGS2_GPU_CACHE_SNOOP 1:0 +#define NVOS46_FLAGS2_GPU_CACHE_SNOOP_DEFAULT (0x00000000) +#define NVOS46_FLAGS2_GPU_CACHE_SNOOP_ENABLE (0x00000001) +#define NVOS46_FLAGS2_GPU_CACHE_SNOOP_DISABLE (0x00000002) + +/* parameters */ +typedef struct +{ + NvHandle hClient; // [IN] client handle + NvHandle hDevice; // [IN] device handle for mapping + NvHandle hDma; // [IN] dma handle for mapping + NvHandle hMemory; // [IN] memory handle for mapping + NvU64 offset NV_ALIGN_BYTES(8); // [IN] offset of region + NvU64 length NV_ALIGN_BYTES(8); // [IN] limit of region + NvV32 flags; // [IN] flags + NvV32 flags2; // [IN] flags2 + NvV32 kindOverride; // [IN] page kind - applied if NVOS46_FLAGS_PAGE_KIND_OVERRIDE is YES + NvU64 dmaOffset NV_ALIGN_BYTES(8); // [OUT] offset of mapping + // [IN] if FLAGS_DMA_OFFSET_FIXED_TRUE + // *OR* hDma is NOT a CTXDMA handle + // (see NVOS46_FLAGS_DMA_OFFSET_FIXED) + NvV32 status; // [OUT] status +} NVOS46_PARAMETERS; + +typedef NVOS46_PARAMETERS NV_MAP_MEMORY_DMA_PARAMETERS; + +/* function OS47 */ +#define NV04_UNMAP_MEMORY_DMA (0x0000002F) + +#define NVOS47_FLAGS_DEFER_TLB_INVALIDATION 0:0 +#define NVOS47_FLAGS_DEFER_TLB_INVALIDATION_FALSE (0x00000000) +#define NVOS47_FLAGS_DEFER_TLB_INVALIDATION_TRUE (0x00000001) + +/* parameters */ +typedef struct +{ + NvHandle hClient; // [IN] client handle + NvHandle hDevice; // [IN] device handle for mapping + NvHandle hDma; // [IN] dma handle for mapping + NvHandle hMemory; // [IN] memory handle for mapping + NvV32 flags; // [IN] flags + NvU64 dmaOffset NV_ALIGN_BYTES(8); // [IN] dma offset from NV04_MAP_MEMORY_DMA + NvU64 size NV_ALIGN_BYTES(8); // [IN] size to unmap, 0 to unmap entire mapping + NvV32 status; // [OUT] status +} NVOS47_PARAMETERS; + +typedef NVOS47_PARAMETERS NV_UNMAP_MEMORY_DMA_PARAMETERS; + +#define NV04_BIND_CONTEXT_DMA (0x00000031) +/* parameters */ +typedef struct +{ + NvHandle hClient; // [IN] client handle + NvHandle hChannel; // [IN] channel handle for binding + NvHandle hCtxDma; // [IN] ctx dma handle for binding + NvV32 status; // [OUT] status +} NVOS49_PARAMETERS; + + +/* function OS54 */ +#define NV04_CONTROL (0x00000036) + +#define NVOS54_FLAGS_NONE (0x00000000) +#define NVOS54_FLAGS_IRQL_RAISED (0x00000001) +#define NVOS54_FLAGS_LOCK_BYPASS (0x00000002) +#define NVOS54_FLAGS_FINN_SERIALIZED (0x00000004) + +/* parameters */ +typedef struct +{ + NvHandle hClient; + NvHandle hObject; + NvV32 cmd; + NvU32 flags; + NvP64 params NV_ALIGN_BYTES(8); + NvU32 paramsSize; + NvV32 status; +} NVOS54_PARAMETERS; + +/* RM Control header + * + * Replacement for NVOS54_PARAMETERS where embedded pointers are not allowed. + * Input layout for user space RM Control calls should be: + * + * +--- NVOS63_PARAMETERS ---+--- RM Control parameters ---+ + * + * NVOS63_PARAMETERS::paramsSize is the size of RM Control parameters + * + */ +typedef struct +{ + NvHandle hClient; // [IN] client handle + NvHandle hObject; // [IN] object handle + NvV32 cmd; // [IN] control command ID + NvU32 paramsSize; // [IN] size in bytes of the RM Control parameters + NvV32 status; // [OUT] status +} NVOS63_PARAMETERS; + + +/* function OS55 */ +#define NV04_DUP_OBJECT (0x00000037) + +/* parameters */ +typedef struct +{ + NvHandle hClient; // [IN] destination client handle + NvHandle hParent; // [IN] parent of new object + NvHandle hObject; // [INOUT] destination (new) object handle + NvHandle hClientSrc; // [IN] source client handle + NvHandle hObjectSrc; // [IN] source (old) object handle + NvU32 flags; // [IN] flags + NvU32 status; // [OUT] status +} NVOS55_PARAMETERS; + +#define NV04_DUP_HANDLE_FLAGS_NONE (0x00000000) +#define NV04_DUP_HANDLE_FLAGS_REJECT_KERNEL_DUP_PRIVILEGE (0x00000001) // If set, prevents an RM kernel client from duping unconditionally + // NOTE: Do not declare a NV04_DUP_HANDLE_FLAGS_* value of 0x00000008 + // until Bug 2859347 is resolved! This is due to conflicting usage + // of RS_RES_DUP_PARAMS_INTERNAL.flags to pass + // NVOS32_ALLOC_INTERNAL_FLAGS_FLA_MEMORY to an object constructor. + +/* function OS56 */ +#define NV04_UPDATE_DEVICE_MAPPING_INFO (0x00000038) + +/* parameters */ +typedef struct +{ + NvHandle hClient; + NvHandle hDevice; + NvHandle hMemory; + NvP64 pOldCpuAddress NV_ALIGN_BYTES(8); + NvP64 pNewCpuAddress NV_ALIGN_BYTES(8); + NvV32 status; +} NVOS56_PARAMETERS; + +/* function OS57 */ +#define NV04_SHARE (0x0000003E) + +/* parameters */ +typedef struct +{ + NvHandle hClient; // [IN] owner client handle + NvHandle hObject; // [IN] resource to share + RS_SHARE_POLICY sharePolicy; // [IN] share policy entry + NvU32 status; // [OUT] status +} NVOS57_PARAMETERS; + +/*! + * @defgroup NVPOWERSTATE_STAGE + * + * An enumeration of various "stages" during @ref NVPOWERSTATE_PARAMETERS + * processing, particularly for tracking failures during a given stage. + * + * @{ + */ +typedef NvU32 NVPOWERSTATE_STAGE; +#define NVPOWERSTATE_STAGE_NONE 0U +#define NVPOWERSTATE_STAGE_WAIT_FOR_GFW_BOOT_OK 1U +#define NVPOWERSTATE_STAGE_INIT_LIBOS_LOGGING_STRUCTURES 2U +#define NVPOWERSTATE_STAGE_GSP_PREPARE_FOR_BOOTSTRAP 3U +#define NVPOWERSTATE_STAGE_GSP_BOOTSTRAP 4U +#define NVPOWERSTATE_STAGE_BOOT_GSP_RM_PROXY 5U +#define NVPOWERSTATE_STAGE_VBIOS_HANDLE_SECURE_BOOT 6U +#define NVPOWERSTATE_STAGE_RESTORE_PCIE_CONFIG_REGISTERS 7U +#define NVPOWERSTATE_STAGE_GCX_BOOT_TIMER_CB_SCHEDULE 8U +#define NVPOWERSTATE_STAGE_POWER_MANAGEMENT_RESUME_PRE_LOAD_PHYSICAL_UNATTACHED 9U +#define NVPOWERSTATE_STAGE_PMS_EXPECTED_CHECKPOINT_DONE 10U +#define NVPOWERSTATE_STAGE_POLL_FOR_NVLINK_READY 11U +#define NVPOWERSTATE_STAGE_CE_STATE_PRE_LOAD 12U +#define NVPOWERSTATE_STAGE_LOAD_PROXY_UCODE_EARLY_INIT 13U +#define NVPOWERSTATE_STAGE_RESTORE_NON_WPR_REGION 14U +#define NVPOWERSTATE_STAGE_PMU_20_OS_BOOTSTRAP 15U +#define NVPOWERSTATE_STAGE_STATE_PRE_LOAD_ENGINE 16U +#define NVPOWERSTATE_STAGE_STATE_PRE_LOAD_UNKNOWN 17U +#define NVPOWERSTATE_STAGE_STATE_LOAD_ENGINE 18U +#define NVPOWERSTATE_STAGE_STATE_LOAD_UNKNOWN 19U +#define NVPOWERSTATE_STAGE_STATE_LOAD_PHYSICAL 20U +#define NVPOWERSTATE_STAGE_STATE_POST_LOAD_ENGINE 21U +#define NVPOWERSTATE_STAGE_STATE_POST_LOAD_UNKNOWN 22U +#define NVPOWERSTATE_STAGE_GSP_PREPARE_SUSPEND_RESUME_DATA 23U +#define NVPOWERSTATE_STAGE_MC_POINTER_NULL 24U +#define NVPOWERSTATE_STAGE_SAVE_PCIE_CONFIG_REGISTERS 25U +#define NVPOWERSTATE_STAGE_STATE_PRE_UNLOAD_ENGINE 26U +#define NVPOWERSTATE_STAGE_STATE_PRE_UNLOAD_UNKNOWN 27U +#define NVPOWERSTATE_STAGE_STATE_UNLOAD_ENGINE 28U +#define NVPOWERSTATE_STAGE_STATE_UNLOAD_UNKNOWN 29U +#define NVPOWERSTATE_STAGE_STATE_POST_UNLOAD_ENGINE 30U +#define NVPOWERSTATE_STAGE_STATE_POST_UNLOAD_UNKNOWN 31U +#define NVPOWERSTATE_STAGE_GSP_UNLOAD_RM 32U +#define NVPOWERSTATE_STAGE_MONITOR_STATE_0 33U +#define NVPOWERSTATE_STAGE_MONITOR_STATE_1 34U +#define NVPOWERSTATE_STAGE_MONITOR_STATE_HIBERNATE 35U +#define NVPOWERSTATE_STAGE_SET_POWER_STATE_UNKNOWN 36U +#define NVPOWERSTATE_STAGE__COUNT 37U +/*!@}*/ + +/*! + * Common structure for any failure within a given GPU engine in a top-level GPU + * state transition + */ +typedef struct +{ + /*! + * NVOC class ID of the failing engine + */ + NvU32 classId; + + /*! + * Time from beginning of the state transition to this engine's failure + */ + NvU64 cumulativeTimeus; + + /*! + * Maximum time any of the engines took to transition + */ + NvU32 engineMaxTimeus; + + /*! + * NVOC class ID of the engine that took the longest time to transition + */ + NvU32 engineMaxTimeClassId; +} NVPOWERSTATE_FAILURE_ENGINE_TRANSITION; + +/*! + * @defgroup NVPOWERSTATE_FAILURE_STRUCTURE + * + * A set of structures for capturing additional, failure-specific data in a + * @ref NVPOWERSTATE_PARAMETERS processing failure. + * + * @note These structures should correspond 1:1 with the list of + * @ref NVPOWERSTATE_STAGE values + * + * @{ + */ +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_WAIT_FOR_GFW_BOOT_OK; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_INIT_LIBOS_LOGGING_STRUCTURES; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_GSP_PREPARE_FOR_BOOTSTRAP; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_GSP_BOOTSTRAP; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_BOOT_GSP_RM_PROXY; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_VBIOS_HANDLE_SECURE_BOOT; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_RESTORE_PCIE_CONFIG_REGISTERS; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_GCX_BOOT_TIMER_CB_SCHEDULE; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_POWER_MANAGEMENT_RESUME_PRE_LOAD_PHYSICAL_UNATTACHED; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_PMS_EXPECTED_CHECKPOINT_DONE; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_POLL_FOR_NVLINK_READY; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_CE_STATE_PRE_LOAD; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_LOAD_PROXY_UCODE_EARLY_INIT; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_RESTORE_NON_WPR_REGION; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_PMU_20_OS_BOOTSTRAP; + +typedef struct +{ + NVPOWERSTATE_FAILURE_ENGINE_TRANSITION engineTransition; +} NVPOWERSTATE_FAILURE_STATE_PRE_LOAD_ENGINE; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_STATE_PRE_LOAD_UNKNOWN; + +typedef struct +{ + NVPOWERSTATE_FAILURE_ENGINE_TRANSITION engineTransition; +} NVPOWERSTATE_FAILURE_STATE_LOAD_ENGINE; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_STATE_LOAD_UNKNOWN; + +typedef struct +{ + NVPOWERSTATE_FAILURE_ENGINE_TRANSITION engineTransition; +} NVPOWERSTATE_FAILURE_STATE_POST_LOAD_ENGINE; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_STATE_POST_LOAD_UNKNOWN; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_STATE_LOAD_PHYSICAL; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_GSP_PREPARE_SUSPEND_RESUME_DATA; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_MC_POINTER_NULL; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_SAVE_PCIE_CONFIG_REGISTERS; + +typedef struct +{ + NVPOWERSTATE_FAILURE_ENGINE_TRANSITION engineTransition; +} NVPOWERSTATE_FAILURE_STATE_PRE_UNLOAD_ENGINE; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_STATE_PRE_UNLOAD_UNKNOWN; + +typedef struct +{ + NVPOWERSTATE_FAILURE_ENGINE_TRANSITION engineTransition; +} NVPOWERSTATE_FAILURE_STATE_UNLOAD_ENGINE; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_STATE_UNLOAD_UNKNOWN; + +typedef struct +{ + NVPOWERSTATE_FAILURE_ENGINE_TRANSITION engineTransition; +} NVPOWERSTATE_FAILURE_STATE_POST_UNLOAD_ENGINE; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_STATE_POST_UNLOAD_UNKNOWN; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_GSP_UNLOAD_RM; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_MONITOR_STATE_0; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_MONITOR_STATE_1; + +typedef struct +{ + NvU8 rsvd; +} NVPOWERSTATE_FAILURE_MONITOR_STATE_HIBERNATE; + +typedef struct +{ + /*! + * NV_POWER_ADAPTER_STATE_* value + */ + NvU32 state; +} NVPOWERSTATE_FAILURE_SET_POWER_STATE_UNKNOWN; +/*!@}*/ + +/*! + * A union to hold failure-specific data for any failure that might happen while + * doing @ref NVPOWERSTATE_PARAMETERS processing + * + * @note Entries in the union should correspond 1:1 with + * @ref NVPOWERSTATE_STAGE values + */ +typedef union +{ + NVPOWERSTATE_FAILURE_WAIT_FOR_GFW_BOOT_OK waitForGfwBootOk; + NVPOWERSTATE_FAILURE_INIT_LIBOS_LOGGING_STRUCTURES initLibosLoggingStructures; + NVPOWERSTATE_FAILURE_GSP_PREPARE_FOR_BOOTSTRAP gspPrepareForBootstrap; + NVPOWERSTATE_FAILURE_GSP_BOOTSTRAP gspBootstrap; + NVPOWERSTATE_FAILURE_BOOT_GSP_RM_PROXY bootGspRmProxy; + NVPOWERSTATE_FAILURE_VBIOS_HANDLE_SECURE_BOOT vbiosHandleSecureBoot; + NVPOWERSTATE_FAILURE_RESTORE_PCIE_CONFIG_REGISTERS restorePcieConfigRegisters; + NVPOWERSTATE_FAILURE_GCX_BOOT_TIMER_CB_SCHEDULE gcxBootTimerCbSchedule; + NVPOWERSTATE_FAILURE_POWER_MANAGEMENT_RESUME_PRE_LOAD_PHYSICAL_UNATTACHED powerManagementResumePreLoadPhysicalUnattached; + NVPOWERSTATE_FAILURE_PMS_EXPECTED_CHECKPOINT_DONE pmsExpectedCheckpointDone; + NVPOWERSTATE_FAILURE_POLL_FOR_NVLINK_READY pollForNvlinkReady; + NVPOWERSTATE_FAILURE_CE_STATE_PRE_LOAD ceStatePreLoad; + NVPOWERSTATE_FAILURE_LOAD_PROXY_UCODE_EARLY_INIT loadProxyUcodeEarlyInit; + NVPOWERSTATE_FAILURE_RESTORE_NON_WPR_REGION restoreNonWprRegion; + NVPOWERSTATE_FAILURE_PMU_20_OS_BOOTSTRAP pmu20OsBootstrap; + NVPOWERSTATE_FAILURE_STATE_PRE_LOAD_ENGINE statePreLoadEngine; + NVPOWERSTATE_FAILURE_STATE_PRE_LOAD_UNKNOWN statePreLoadUnknown; + NVPOWERSTATE_FAILURE_STATE_LOAD_ENGINE stateLoadEngine; + NVPOWERSTATE_FAILURE_STATE_LOAD_UNKNOWN stateLoadUnknown; + NVPOWERSTATE_FAILURE_STATE_POST_LOAD_ENGINE statePostLoadEngine; + NVPOWERSTATE_FAILURE_STATE_POST_LOAD_UNKNOWN statePostLoadUnknown; + NVPOWERSTATE_FAILURE_STATE_LOAD_PHYSICAL stateLoadPhysical; + NVPOWERSTATE_FAILURE_GSP_PREPARE_SUSPEND_RESUME_DATA gspPrepareSuspendResumeData; + NVPOWERSTATE_FAILURE_MC_POINTER_NULL mcPointerNull; + NVPOWERSTATE_FAILURE_SAVE_PCIE_CONFIG_REGISTERS savePcieConfigRegisters; + NVPOWERSTATE_FAILURE_STATE_PRE_UNLOAD_ENGINE statePreUnloadEngine; + NVPOWERSTATE_FAILURE_STATE_PRE_UNLOAD_UNKNOWN statePreUnloadUnknown; + NVPOWERSTATE_FAILURE_STATE_UNLOAD_ENGINE stateUnloadEngine; + NVPOWERSTATE_FAILURE_STATE_UNLOAD_UNKNOWN stateUnloadUnknown; + NVPOWERSTATE_FAILURE_STATE_POST_UNLOAD_ENGINE statePostUnloadEngine; + NVPOWERSTATE_FAILURE_STATE_POST_UNLOAD_UNKNOWN statePostUnloadUnknown; + NVPOWERSTATE_FAILURE_GSP_UNLOAD_RM gspUnloadRm; + NVPOWERSTATE_FAILURE_MONITOR_STATE_0 monitorState0; + NVPOWERSTATE_FAILURE_MONITOR_STATE_1 monitorState1; + NVPOWERSTATE_FAILURE_MONITOR_STATE_HIBERNATE monitorStateHibernate; + NVPOWERSTATE_FAILURE_SET_POWER_STATE_UNKNOWN setPowerStateUnknown; +} NVPOWERSTATE_FAILURE_DATA; + +/*! + * Contains failure data for a failure that occurred during + * @ref NVPOWERSTATE_PARAMETERS processing + */ +typedef struct +{ + /*! + * The @ref NVPOWERSTATE_STAGE in which the failure occurred, or @ref + * @ref NVPOWERSTATE_STAGE_NONE if no failure occurred. + * + * @note This field is the discriminant for + * @ref NVPOWERSTATE_FAILURE::data + */ + NVPOWERSTATE_STAGE stage; + + /*! + * The @ref NV_STATUS value from the failure + */ + NV_STATUS status; + + /*! + * Failure-specific data + * + * @note Valid entry is determined by @ref NVPOWERSTATE_FAILURE::stage + */ + NVPOWERSTATE_FAILURE_DATA data; +} NVPOWERSTATE_FAILURE; + +/*! + * @brief Initializes a @ref NVPOWERSTATE_FAILURE for tracking + * during a transition + * + * @param[out] pFailure + * Pointer to @ref NVPOWERSTATE_FAILURE to initialize + */ +static NV_FORCEINLINE void +nvPowerStateFailureInit +( + NVPOWERSTATE_FAILURE *pFailure +) +{ +#if !defined(NVRISCV_LIBFSP_BUILD) || !NVRISCV_LIBFSP_BUILD + (void)NVMISC_MEMSET( + pFailure, + 0x0, + sizeof(*pFailure)); +#else + (void)memset( + pFailure, + 0x0, + sizeof(*pFailure)); +#endif +} + +/*! + * @brief Returns whether the given @ref NVPOWERSTATE_FAILURE is already + * populated with error data + * + * @param[in] pFailure + * @ref NVPOWERSTATE_FAILURE to check + * + * @return @ref NV_TRUE + * Structure is already populated with failure data + * @return @ref NV_FALSE + * Otherwise + */ +static NV_FORCEINLINE NvBool +nvPowerStateFailureIsPopulated +( + const NVPOWERSTATE_FAILURE *pFailure +) +{ + return pFailure->stage != NVPOWERSTATE_STAGE_NONE; +} + +/* parameters */ +typedef struct +{ + NvU32 deviceReference; + NvU32 head; + NvU32 state; + NvU8 forceMonitorState; + NvU8 bForcePerfBiosLevel; + NvU8 bIsD3HotTransition; // [OUT] To tell client if it's a D3Hot transition + NvU8 bForcePowerStateFail; + NvU32 errorStatus; // [OUT] To tell client if there is bubble up errors + NvU32 fastBootPowerState; + NvU8 bGC8Transition; + NvU8 bGC8InputRailCutOff; // [OUT] To tell client if input rail was cut off in GC8 + NVPOWERSTATE_FAILURE failure; +} NVPOWERSTATE_PARAMETERS, *PNVPOWERSTATE_PARAMETERS; + + /***************************************************************************\ +|* Object Allocation Parameters *| + \***************************************************************************/ + +// GR engine creation parameters +typedef struct { + NvU32 version; // set to 0x2 + NvU32 flags; // input param from a rm client (no flags are currently defined) + NvU32 size; // sizeof(NV_GR_ALLOCATION_PARAMETERS) + NvU32 caps; // output param for a rm client - class dependent +} NV_GR_ALLOCATION_PARAMETERS; + +// +// NvAlloc parameters for NV03_DEVICE_XX class +// hClientShare +// For NV50+ this can be set to virtual address space for this +// device. On previous chips this field is ignored. There are +// three possible settings +// NV01_NULL_OBJECT - Use the default global VA space +// Handle to current client - Create a new private address space +// Handle to another client - Attach to other clients address space +// flags +// MAP_PTE_GLOBALLY Deprecated. +// MINIMIZE_PTETABLE_SIZE Pass hint to DMA HAL to use partial page +// tables. Depending on allocation pattern +// this may actually use more instance memory. +// RETRY_PTE_ALLOC_IN_SYS Fallback to PTEs allocation in sysmem. This +// is now enabled by default. +// VASPACE_SIZE Honor vaSpaceSize field. +// +// MAP_PTE Deprecated. +// +// VASPACE_BIG_PAGE_SIZE_64k ***Warning this flag will be deprecated do not use***** +// VASPACE_BIG_PAGE_SIZE_128k This flag will choose the big page size of the VASPace +// to 64K/128k if the system supports a configurable size. +// If the system does not support a configurable size then +// defaults will be chosen. +// If the user sets both these bits then this API will fail. +// +// SHARED_MANAGEMENT +// *** Warning: This will be deprecated - see NV_VASPACE_ALLOCATION_PARAMETERS. *** +// +// +// hTargetClient/hTargetDevice +// Deprecated. Can be deleted once client code has removed references. +// +// vaBase +// *** Warning: This will be deprecated - see NV_VASPACE_ALLOCATION_PARAMETERS. *** +// +// vaSpaceSize +// Set the size of the VA space used for this client if allocating +// a new private address space. Is expressed as a size such as +// (1<<32) for a 32b address space. Reducing the size of the address +// space allows the dma chip specific code to reduce the instance memory +// used for page tables. +// +// vaMode +// The vaspace allocation mode. There are three modes supported: +// 1. SINGLE_VASPACE +// An old abstraction that provides a single VA space under a +// device and it's allocated implicityly when an object requires a VA +// space. Typically, this VA space is also shared across clients. +// +// 2. OPTIONAL_MULTIPLE_VASPACES +// Global + multiple private va spaces. In this mode, the old abstraction, +// a single vaspace under a device that is allocated implicitly is still +// being supported. A private VA space is an entity under a device, which/ +// cannot be shared with other clients, but multiple channels under the +// same device can still share a private VA space. +// Private VA spaces (class:90f1,FERMI_VASPACE_A) can be allocated as +// objects through RM APIs. This mode requires the users to know what they +// are doing in terms of using VA spaces. Page fault can easily occur if +// one is not careful with a mixed of an implicit VA space and multiple +// VA spaces. +// +// 3. MULTIPLE_VASPACES +// In this mode, all VA spaces have to be allocated explicitly through RM +// APIs and users have to specify which VA space to use for each object. +// This case prevents users to use context dma, which is not supported and +// can be misleading if used. Therefore, it's more a safeguard mode to +// prevent people making mistakes that are hard to debug. +// +// DEFAULT MODE: 2. OPTIONAL_MULTIPLE_VASPACES +// +// See NV0080_ALLOC_PARAMETERS for allocation parameter structure. +// + +#define NV_DEVICE_ALLOCATION_SZNAME_MAXLEN 128 +#define NV_DEVICE_ALLOCATION_FLAGS_NONE (0x00000000) +#define NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE_GLOBALLY (0x00000001) +#define NV_DEVICE_ALLOCATION_FLAGS_MINIMIZE_PTETABLE_SIZE (0x00000002) +#define NV_DEVICE_ALLOCATION_FLAGS_RETRY_PTE_ALLOC_IN_SYS (0x00000004) +#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SIZE (0x00000008) +#define NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE (0x00000010) +#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_IS_TARGET (0x00000020) +#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SHARED_MANAGEMENT (0x00000100) +#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_64k (0x00000200) +#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_128k (0x00000400) +#define NV_DEVICE_ALLOCATION_FLAGS_RESTRICT_RESERVED_VALIMITS (0x00000800) + +// XXX NV_DEVICE_ALLOCATION_FLAGS_VASPACE_PTABLE_PMA_MANAGED should not +// should not be exposed to clients. It should be the default RM +// behavior. +// +// Until it is made the default, certain clients such as OpenGL +// might still need PTABLE allocations to go through PMA, so this +// flag has been temporary exposed. +// +// See bug 1880192 +#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_PTABLE_PMA_MANAGED (0x00001000) + +// +// Indicates this device is being created by guest and requires a +// KernelHostVgpuDeviceApi creation in client. +// +#define NV_DEVICE_ALLOCATION_FLAGS_HOST_VGPU_DEVICE (0x00002000) + +// +// Indicates this device is being created for VGPU plugin use. +// Requires a HostVgpuDevice handle to indicate the guest on which +// this plugin operates. +// +#define NV_DEVICE_ALLOCATION_FLAGS_PLUGIN_CONTEXT (0x00004000) + +// +// For clients using unlinked SLI to catch allocations attempts on secondary GPUs +// not accompanied by a fixed offset. +// +#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_REQUIRE_FIXED_OFFSET (0x00008000) + +#define NV_DEVICE_ALLOCATION_VAMODE_OPTIONAL_MULTIPLE_VASPACES (0x00000000) +#define NV_DEVICE_ALLOCATION_VAMODE_SINGLE_VASPACE (0x00000001) +#define NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES (0x00000002) + + +#define NV_CHANNELGPFIFO_NOTIFICATION_TYPE_ERROR 0x00000000 +#define NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN 0x00000001 +#define NV_CHANNELGPFIFO_NOTIFICATION_TYPE_KEY_ROTATION_STATUS 0x00000002 +#define NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1 3 +#define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_VALUE 14:0 +#define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS 15:15 +#define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_TRUE 0x1 +#define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_FALSE 0x0 + +typedef enum +{ + PB_SIZE_4KB = 0, + PB_SIZE_8KB, + PB_SIZE_16KB, + PB_SIZE_32KB, + PB_SIZE_64KB +} ChannelPBSize; + +typedef struct +{ + NvV32 channelInstance; // One of the n channel instances of a given channel type. + // Note that core channel has only one instance + // while all others have two (one per head). + NvHandle hObjectBuffer; // ctx dma handle for DMA push buffer + NvHandle hObjectNotify; // ctx dma handle for an area (of type NvNotification defined in sdk/nvidia/inc/nvtypes.h) where RM can write errors/notifications + NvU32 offset; // Initial offset for put/get, usually zero. + NvP64 pControl NV_ALIGN_BYTES(8); // pControl gives virt addr of UDISP GET/PUT regs + + NvU32 flags; + ChannelPBSize channelPBSize; // Size of Push Buffer requested by client (allowed values in enum) +#define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB 1:1 +#define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_YES 0x00000000 +#define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_NO 0x00000001 + + NvU32 subDeviceId; // One-hot encoded subDeviceId (i.e. SDM) that will be used to address the channel in the pushbuffer stream (via SSDM method) +} NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS; + +typedef struct +{ + NvV32 channelInstance; // One of the n channel instances of a given channel type. + // All PIO channels have two instances (one per head). + NvHandle hObjectNotify; // ctx dma handle for an area (of type NvNotification defined in sdk/nvidia/inc/nvtypes.h) where RM can write errors. + NvP64 pControl NV_ALIGN_BYTES(8); // pControl gives virt addr of control region for PIO channel +} NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS; + +// Used for allocating a channel group +typedef struct +{ + NvHandle hObjectError; // Error notifier for TSG + NvHandle hObjectEccError; // ECC Error notifier for TSG + NvHandle hVASpace; // VA space handle for TSG + NvU32 engineType; // Engine to which all channels in this TSG are associated with + NvBool bIsCallingContextVgpuPlugin; +} NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS; + +/* +* @params: +* @engineId : Engine to which the software runlist be associated with. +* @maxTSGs : Maximum number of TSG entries that will be submitted in this software runlist +* The size of the runlist buffer will be determined by +* 2 * // double buffer +* maxTSGs * // determined by KMD +* maxChannelPerTSG * // Determined by RM +* sizeof(RunlistEntry) // Determined by HW format +* @qosIntrEnableMask: QOS Interrupt bitmask that needs to be enabled for the SW runlist defined below. +*/ +typedef struct +{ + NvU32 engineId; //(IN) + NvU32 maxTSGs; //(IN) // Size of the RM could return error if the request cannot be accommodated. + NvU32 qosIntrEnableMask; //(IN) // Bitmask for QOS interrupts that needs to be enabled +} NV_SWRUNLIST_ALLOCATION_PARAMS; + +#define NV_SWRUNLIST_QOS_INTR_NONE 0x00000000 +#define NV_SWRUNLIST_QOS_INTR_RUNLIST_AND_ENG_IDLE_ENABLE NVBIT32(0) +#define NV_SWRUNLIST_QOS_INTR_RUNLIST_IDLE_ENABLE NVBIT32(1) +#define NV_SWRUNLIST_QOS_INTR_RUNLIST_ACQUIRE_ENABLE NVBIT32(2) +#define NV_SWRUNLIST_QOS_INTR_RUNLIST_ACQUIRE_AND_ENG_IDLE_ENABLE NVBIT32(3) + +typedef struct +{ + NvU32 size; + NvU32 caps; +} NV_ME_ALLOCATION_PARAMETERS; + +typedef struct +{ + NvU32 size; + NvU32 prohibitMultipleInstances; + NvU32 engineInstance; // Select NVDEC0 or NVDEC1 or NVDEC2 +} NV_NVDEC_ALLOCATION_PARAMETERS; +#define NV_BSP_ALLOCATION_PARAMETERS NV_NVDEC_ALLOCATION_PARAMETERS + +// +// These are referenced by mdiag mods tests, but do not appear to be used during +// in the RM any longer +// +#define NV_VP_ALLOCATION_FLAGS_STANDARD_UCODE (0x00000000) +#define NV_VP_ALLOCATION_FLAGS_STATIC_UCODE (0x00000001) +#define NV_VP_ALLOCATION_FLAGS_DYNAMIC_UCODE (0x00000002) + +// +// NV_VP_ALLOCATION_PARAMETERS.flags +// +// NV_VP_ALLOCATION_FLAGS_AVP_CLIENT are used by Tegra to specify if +// the current allocation with be used by Video or Audio +// +#define NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_VIDEO (0x00000000) +#define NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_AUDIO (0x00000001) + +typedef struct +{ + NvU32 size; + NvU32 caps; + NvU32 flags; + NvU32 altUcode; + NvP64 rawUcode NV_ALIGN_BYTES(8); + NvU32 rawUcodeSize; + NvU32 numSubClasses; + NvU32 numSubSets; + NvP64 subClasses NV_ALIGN_BYTES(8); + NvU32 prohibitMultipleInstances; + NvP64 pControl NV_ALIGN_BYTES(8); // Used by Tegra to return a mapping to NvE276Control + NvHandle hMemoryCmdBuffer NV_ALIGN_BYTES(8); // Used by Tegra to specify cmd buffer + NvU64 offset NV_ALIGN_BYTES(8); // Used by Tegra to specify an offset into the cmd buffer + +} NV_VP_ALLOCATION_PARAMETERS; + +typedef struct +{ + NvU32 size; + NvU32 prohibitMultipleInstances; +} NV_PPP_ALLOCATION_PARAMETERS; + +typedef struct +{ + NvU32 size; + NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of NVENC? + NvU32 engineInstance; // Select NVENC0 or NVENC1 or NVENC2 +} NV_NVENC_ALLOCATION_PARAMETERS; +#define NV_MSENC_ALLOCATION_PARAMETERS NV_NVENC_ALLOCATION_PARAMETERS + +typedef struct +{ + NvU32 size; + NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of SEC2? +} NV_SEC2_ALLOCATION_PARAMETERS; + +typedef struct +{ + NvU32 size; + NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of NVJPG? + NvU32 engineInstance; +} NV_NVJPG_ALLOCATION_PARAMETERS; + +typedef struct +{ + NvU32 size; + NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of OFA? + NvU32 engineInstance; +} NV_OFA_ALLOCATION_PARAMETERS; + +#define NV04_ADD_VBLANK_CALLBACK (0x0000003D) + +#include "class/cl9010.h" // for OSVBLANKCALLBACKPROC + +/* parameters */ +/* NOTE: the "void* pParm's" below are ok (but unfortunate) since this interface + can only be used by other kernel drivers which must share the same ptr-size */ +typedef struct +{ + NvHandle hClient; // [IN] client handle + NvHandle hDevice; // [IN] device handle for mapping + NvHandle hVblank; // [IN] Vblank handle for control + OSVBLANKCALLBACKPROC pProc; // Routine to call at vblank time + + NvV32 LogicalHead; // Logical Head + void *pParm1; + void *pParm2; + NvU32 bAdd; // Add or Delete + NvV32 status; // [OUT] status +} NVOS61_PARAMETERS; + +/** + * @brief NvAlloc parameters for VASPACE classes + * + * Used to create a new private virtual address space. + * + * index + * Tegra: With TEGRA_VASPACE_A, index specifies the IOMMU + * virtual address space to be created. Based on the + * index, RM/NVMEM will decide the HW ASID to be used with + * this VA Space. "index" takes values from the + * NVMEM_CLIENT_* defines in + * "drivers/common/inc/tegra/memory/ioctl.h". + * + * Big GPU: With FERMI_VASPACE_A, see NV_VASPACE_ALLOCATION_INDEX_GPU_*. + * + * flags + * MINIMIZE_PTETABLE_SIZE Pass hint to DMA HAL to use partial page tables. + * Depending on allocation pattern this may actually + * use more instance memory. + * + * RETRY_PTE_ALLOC_IN_SYS Fallback to PTEs allocation in sysmem. This is now + * enabled by default. + * + * SHARED_MANAGEMENT + * Indicates management of the VA space is shared with another + * component (e.g. driver layer, OS, etc.). + * + * The initial VA range from vaBase (inclusive) through vaSize (exclusive) + * is managed by RM. The range must be aligned to a top-level PDE's VA + * coverage since backing page table levels for this range are managed by RM. + * All normal RM virtual memory management APIs work within this range. + * + * An external component can manage the remaining VA ranges, + * from 0 (inclusive) to vaBase (exclusive) and from vaSize (inclusive) up to the + * maximum VA limit supported by HW. + * Management of these ranges includes VA sub-allocation and the + * backing lower page table levels. + * + * The top-level page directory is special since it is a shared resource. + * Management of the page directory is as follows: + * 1. Initially RM allocates a page directory for RM-managed PDEs. + * 2. The external component may create a full page directory and commit it + * with NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY. + * This will copy the RM-managed PDEs from the RM-managed page directory + * into the external page directory and commit channels to the external page directory. + * After this point RM will update the external page directory directly for + * operations that modify RM-managed PDEs. + * 3. The external component may use NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY repeatedly + * if it needs to update the page directory again (e.g. to resize or migrate). + * This will copy the RM-managed PDEs from the old external page directory + * into the new external page directory and commit channels to the new page directory. + * 4. The external component may restore management of the page directory back to + * RM with NV0080_CTRL_CMD_DMA_UNSET_PAGE_DIRECTORY. + * This will copy the RM-managed PDEs from the external page directory + * into the RM-managed page directory and commit channels to the RM-managed page directory. + * After this point RM will update the RM-managed page directory for + * operations that modify RM-managed PDEs. + * Note that operations (2) and (4) are symmetric - the RM perspective of management is identical + * before and after a sequence of SET => ... => UNSET. + * + * ENABLE_PAGE_FAULTING + * Enable page faulting if the architecture supports it. + * As of now page faulting is only supported for compute on pascal+. + * IS_EXTERNALLY_OWNED + * This vaspace that has been allocated will be managed by + * an external driver. RM will not own the pagetables for this vaspace. + * + * ENABLE_NVLINK_ATS + * Enables VA translation for this address space using NVLINK ATS. + * Note, the GMMU page tables still exist and take priority over NVLINK ATS. + * VA space object creation will fail if: + * - hardware support is not available (NV_ERR_NOT_SUPPORTED) + * - incompatible option IS_EXTERNALLY_OWNED is set (NV_ERR_INVALID_ARGUMENT) + * IS_FLA + * Sets FLA flag for this VASPACE + * + * ALLOW_ZERO_ADDRESS + * Allows VASPACE Range to start from zero + * SKIP_SCRUB_MEMPOOL + * Skip scrubbing in MemPool + * + * vaBase [in, out] + * On input, the lowest usable base address of the VA space. + * If 0, RM will pick a default value - 0 is always reserved to respresent NULL pointers. + * The value must be aligned to the largest page size of the VA space. + * Larger values aid in debug since offsets added to NULL pointers will still fault. + * + * On output, the actual usable base address is returned. + * + * vaSize [in,out] + * On input, requested size of the virtual address space in bytes. + * Requesting a smaller size reduces the memory required for the initial + * page directory, but the VAS may be resized later (NV0080_CTRL_DMA_SET_VA_SPACE_SIZE). + * If 0, the default VA space size will be used. + * + * On output, the actual size of the VAS in bytes. + * NOTE: This corresponds to the VA_LIMIT + 1, so the usable size is (vaSize - vaBase). + * + * bigPageSIze + * Set the size of the big page in this address space object. Current HW supports + * either 64k or 128k as the size of the big page. HW that support multiple big + * page size per address space will use this size. Hw that do not support this feature + * will override to the default big page size that is supported by the system. + * If the big page size value is set to ZERO then we will pick the default page size + * of the system. + * pasid + * Process Address Space Identifier. Used by RM internally when + * NV_VASPACE_ALLOCATION_FLAGS_ENABLE_NVLINK_ATS_TEST is set + **/ +typedef struct +{ + NvU32 index; + NvV32 flags; + NvU64 vaSize NV_ALIGN_BYTES(8); + NvU64 vaStartInternal NV_ALIGN_BYTES(8); + NvU64 vaLimitInternal NV_ALIGN_BYTES(8); + NvU32 bigPageSize; + NvU64 vaBase NV_ALIGN_BYTES(8); + NvU32 pasid; +} NV_VASPACE_ALLOCATION_PARAMETERS; + +#define NV_VASPACE_ALLOCATION_FLAGS_NONE (0x00000000) +#define NV_VASPACE_ALLOCATION_FLAGS_MINIMIZE_PTETABLE_SIZE BIT(0) +#define NV_VASPACE_ALLOCATION_FLAGS_RETRY_PTE_ALLOC_IN_SYS BIT(1) +#define NV_VASPACE_ALLOCATION_FLAGS_SHARED_MANAGEMENT BIT(2) +#define NV_VASPACE_ALLOCATION_FLAGS_IS_EXTERNALLY_OWNED BIT(3) +#define NV_VASPACE_ALLOCATION_FLAGS_ENABLE_NVLINK_ATS BIT(4) +#define NV_VASPACE_ALLOCATION_FLAGS_ENABLE_PAGE_FAULTING BIT(6) +#define NV_VASPACE_ALLOCATION_FLAGS_VA_INTERNAL_LIMIT BIT(7) +#define NV_VASPACE_ALLOCATION_FLAGS_ALLOW_ZERO_ADDRESS BIT(8) +#define NV_VASPACE_ALLOCATION_FLAGS_IS_FLA BIT(9) +#define NV_VASPACE_ALLOCATION_FLAGS_SKIP_SCRUB_MEMPOOL BIT(10) +#define NV_VASPACE_ALLOCATION_FLAGS_OPTIMIZE_PTETABLE_MEMPOOL_USAGE BIT(11) +#define NV_VASPACE_ALLOCATION_FLAGS_REQUIRE_FIXED_OFFSET BIT(12) +#define NV_VASPACE_ALLOCATION_FLAGS_PTETABLE_HEAP_MANAGED BIT(13) +// To be used only by SRT for testing ATS within RM +#define NV_VASPACE_ALLOCATION_FLAGS_ENABLE_NVLINK_ATS_TEST BIT(14) + +#define NV_VASPACE_ALLOCATION_INDEX_GPU_NEW 0x00 // NV_STATUS_LEVEL_WARN + * to determine success v. failure of a call. + */ +#define NV_STATUS_LEVEL_WARN 1 + +/*! + * @def NV_STATUS_LEVEL_ERR + * @see NV_STATUS_LEVEL + * @brief Unrecoverable error condition + */ +#define NV_STATUS_LEVEL_ERR 3 + +/*! + * @def NV_STATUS_LEVEL + * @see NV_STATUS_LEVEL_OK + * @see NV_STATUS_LEVEL_WARN + * @see NV_STATUS_LEVEL_ERR + * @brief Level of the status code + * + * @warning IMPORTANT: When comparing NV_STATUS_LEVEL(_S) against one of + * these constants, it is important to use '<=' or '>' (rather + * than '<' or '>='). + * + * For example. do: + * if (NV_STATUS_LEVEL(status) <= NV_STATUS_LEVEL_WARN) + * rather than: + * if (NV_STATUS_LEVEL(status) < NV_STATUS_LEVEL_ERR) + * + * By being consistent in this manner, it is easier to systematically + * add additional level constants. New levels are likely to lower + * (rather than raise) the severity of _ERR codes. For example, + * if we were to add NV_STATUS_LEVEL_RETRY to indicate hardware + * failures that may be recoverable (e.g. RM_ERR_TIMEOUT_RETRY + * or RM_ERR_BUSY_RETRY), it would be less severe than + * NV_STATUS_LEVEL_ERR the level to which these status codes now + * belong. Using '<=' and '>' ensures your code is not broken in + * cases like this. + */ +#define NV_STATUS_LEVEL(_S) \ + ((_S) == NV_OK? NV_STATUS_LEVEL_OK: \ + ((_S) != NV_ERR_GENERIC && (_S) & 0x00010000? NV_STATUS_LEVEL_WARN: \ + NV_STATUS_LEVEL_ERR)) + +/*! + * @def NV_STATUS_LEVEL + * @see NV_STATUS_LEVEL_OK + * @see NV_STATUS_LEVEL_WARN + * @see NV_STATUS_LEVEL_ERR + * @brief Character representing status code level + */ +#define NV_STATUS_LEVEL_CHAR(_S) \ + ((_S) == NV_OK? '0': \ + ((_S) != NV_ERR_GENERIC && (_S) & 0x00010000? 'W': \ + 'E')) + +// Function definitions +const char *nvstatusToString(NV_STATUS nvStatusIn); + +#ifdef __cplusplus +} +#endif + +#endif /* SDK_NVSTATUS_H */ diff --git a/userspace/sdks/nv570/inc/nvstatuscodes.h b/userspace/sdks/nv570/inc/nvstatuscodes.h new file mode 100644 index 0000000..717a1fa --- /dev/null +++ b/userspace/sdks/nv570/inc/nvstatuscodes.h @@ -0,0 +1,184 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef SDK_NVSTATUSCODES_H +#define SDK_NVSTATUSCODES_H + +NV_STATUS_CODE(NV_OK, 0x00000000, "Success") +NV_STATUS_CODE(NV_ERR_GENERIC, 0x0000FFFF, "Failure: Generic Error") + +NV_STATUS_CODE(NV_ERR_BROKEN_FB, 0x00000001, "Frame-Buffer broken") +NV_STATUS_CODE(NV_ERR_BUFFER_TOO_SMALL, 0x00000002, "Buffer passed in is too small") +NV_STATUS_CODE(NV_ERR_BUSY_RETRY, 0x00000003, "System is busy, retry later") +NV_STATUS_CODE(NV_ERR_CALLBACK_NOT_SCHEDULED, 0x00000004, "The requested callback API not scheduled") +NV_STATUS_CODE(NV_ERR_CARD_NOT_PRESENT, 0x00000005, "Card not detected") +NV_STATUS_CODE(NV_ERR_CYCLE_DETECTED, 0x00000006, "Call cycle detected") +NV_STATUS_CODE(NV_ERR_DMA_IN_USE, 0x00000007, "Requested DMA is in use") +NV_STATUS_CODE(NV_ERR_DMA_MEM_NOT_LOCKED, 0x00000008, "Requested DMA memory is not locked") +NV_STATUS_CODE(NV_ERR_DMA_MEM_NOT_UNLOCKED, 0x00000009, "Requested DMA memory is not unlocked") +NV_STATUS_CODE(NV_ERR_DUAL_LINK_INUSE, 0x0000000A, "Dual-Link is in use") +NV_STATUS_CODE(NV_ERR_ECC_ERROR, 0x0000000B, "Generic ECC error") +NV_STATUS_CODE(NV_ERR_FIFO_BAD_ACCESS, 0x0000000C, "FIFO: Invalid access") +NV_STATUS_CODE(NV_ERR_FREQ_NOT_SUPPORTED, 0x0000000D, "Requested frequency is not supported") +NV_STATUS_CODE(NV_ERR_GPU_DMA_NOT_INITIALIZED, 0x0000000E, "Requested DMA not initialized") +NV_STATUS_CODE(NV_ERR_GPU_IS_LOST, 0x0000000F, "GPU lost from the bus") +NV_STATUS_CODE(NV_ERR_GPU_IN_FULLCHIP_RESET, 0x00000010, "GPU currently in full-chip reset") +NV_STATUS_CODE(NV_ERR_GPU_NOT_FULL_POWER, 0x00000011, "GPU not in full power") +NV_STATUS_CODE(NV_ERR_GPU_UUID_NOT_FOUND, 0x00000012, "GPU UUID not found") +NV_STATUS_CODE(NV_ERR_HOT_SWITCH, 0x00000013, "System in hot switch") +NV_STATUS_CODE(NV_ERR_I2C_ERROR, 0x00000014, "I2C Error") +NV_STATUS_CODE(NV_ERR_I2C_SPEED_TOO_HIGH, 0x00000015, "I2C Error: Speed too high") +NV_STATUS_CODE(NV_ERR_ILLEGAL_ACTION, 0x00000016, "Current action is not allowed") +NV_STATUS_CODE(NV_ERR_IN_USE, 0x00000017, "Generic busy error") +NV_STATUS_CODE(NV_ERR_INFLATE_COMPRESSED_DATA_FAILED, 0x00000018, "Failed to inflate compressed data") +NV_STATUS_CODE(NV_ERR_INSERT_DUPLICATE_NAME, 0x00000019, "Found a duplicate entry in the requested btree") +NV_STATUS_CODE(NV_ERR_INSUFFICIENT_RESOURCES, 0x0000001A, "Ran out of a critical resource, other than memory") +NV_STATUS_CODE(NV_ERR_INSUFFICIENT_PERMISSIONS, 0x0000001B, "The requester does not have sufficient permissions") +NV_STATUS_CODE(NV_ERR_INSUFFICIENT_POWER, 0x0000001C, "Generic Error: Low power") +NV_STATUS_CODE(NV_ERR_INVALID_ACCESS_TYPE, 0x0000001D, "This type of access is not allowed") +NV_STATUS_CODE(NV_ERR_INVALID_ADDRESS, 0x0000001E, "Address not valid") +NV_STATUS_CODE(NV_ERR_INVALID_ARGUMENT, 0x0000001F, "Invalid argument to call") +NV_STATUS_CODE(NV_ERR_INVALID_BASE, 0x00000020, "Invalid base") +NV_STATUS_CODE(NV_ERR_INVALID_CHANNEL, 0x00000021, "Given channel-id not valid") +NV_STATUS_CODE(NV_ERR_INVALID_CLASS, 0x00000022, "Given class-id not valid") +NV_STATUS_CODE(NV_ERR_INVALID_CLIENT, 0x00000023, "Given client not valid") +NV_STATUS_CODE(NV_ERR_INVALID_COMMAND, 0x00000024, "Command passed is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_DATA, 0x00000025, "Invalid data passed") +NV_STATUS_CODE(NV_ERR_INVALID_DEVICE, 0x00000026, "Current device is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_DMA_SPECIFIER, 0x00000027, "The requested DMA specifier is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_EVENT, 0x00000028, "Invalid event occurred") +NV_STATUS_CODE(NV_ERR_INVALID_FLAGS, 0x00000029, "Invalid flags passed") +NV_STATUS_CODE(NV_ERR_INVALID_FUNCTION, 0x0000002A, "Called function is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_HEAP, 0x0000002B, "Heap corrupted") +NV_STATUS_CODE(NV_ERR_INVALID_INDEX, 0x0000002C, "Index invalid") +NV_STATUS_CODE(NV_ERR_INVALID_IRQ_LEVEL, 0x0000002D, "Requested IRQ level is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_LIMIT, 0x0000002E, "Generic Error: Invalid limit") +NV_STATUS_CODE(NV_ERR_INVALID_LOCK_STATE, 0x0000002F, "Requested lock state not valid") +NV_STATUS_CODE(NV_ERR_INVALID_METHOD, 0x00000030, "Requested method not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OBJECT, 0x00000031, "Object not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_BUFFER, 0x00000032, "Object buffer passed is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_HANDLE, 0x00000033, "Object handle is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_NEW, 0x00000034, "New object is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_OLD, 0x00000035, "Old object is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_PARENT, 0x00000036, "Object parent is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OFFSET, 0x00000037, "The offset passed is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OPERATION, 0x00000038, "Requested operation is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OWNER, 0x00000039, "Owner not valid") +NV_STATUS_CODE(NV_ERR_INVALID_PARAM_STRUCT, 0x0000003A, "Invalid structure parameter") +NV_STATUS_CODE(NV_ERR_INVALID_PARAMETER, 0x0000003B, "At least one of the parameters passed is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_PATH, 0x0000003C, "The requested path is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_POINTER, 0x0000003D, "Pointer not valid") +NV_STATUS_CODE(NV_ERR_INVALID_REGISTRY_KEY, 0x0000003E, "Found an invalid registry key") +NV_STATUS_CODE(NV_ERR_INVALID_REQUEST, 0x0000003F, "Generic Error: Invalid request") +NV_STATUS_CODE(NV_ERR_INVALID_STATE, 0x00000040, "Generic Error: Invalid state") +NV_STATUS_CODE(NV_ERR_INVALID_STRING_LENGTH, 0x00000041, "The string length is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_READ, 0x00000042, "The requested read operation is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_WRITE, 0x00000043, "The requested write operation is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_XLATE, 0x00000044, "The requested translate operation is not valid") +NV_STATUS_CODE(NV_ERR_IRQ_NOT_FIRING, 0x00000045, "Requested IRQ is not firing") +NV_STATUS_CODE(NV_ERR_IRQ_EDGE_TRIGGERED, 0x00000046, "IRQ is edge triggered") +NV_STATUS_CODE(NV_ERR_MEMORY_TRAINING_FAILED, 0x00000047, "Failed memory training sequence") +NV_STATUS_CODE(NV_ERR_MISMATCHED_SLAVE, 0x00000048, "Slave mismatch") +NV_STATUS_CODE(NV_ERR_MISMATCHED_TARGET, 0x00000049, "Target mismatch") +NV_STATUS_CODE(NV_ERR_MISSING_TABLE_ENTRY, 0x0000004A, "Requested entry missing not found in the table") +NV_STATUS_CODE(NV_ERR_MODULE_LOAD_FAILED, 0x0000004B, "Failed to load the requested module") +NV_STATUS_CODE(NV_ERR_MORE_DATA_AVAILABLE, 0x0000004C, "There is more data available") +NV_STATUS_CODE(NV_ERR_MORE_PROCESSING_REQUIRED, 0x0000004D, "More processing required for the given call") +NV_STATUS_CODE(NV_ERR_MULTIPLE_MEMORY_TYPES, 0x0000004E, "Multiple memory types found") +NV_STATUS_CODE(NV_ERR_NO_FREE_FIFOS, 0x0000004F, "No more free FIFOs found") +NV_STATUS_CODE(NV_ERR_NO_INTR_PENDING, 0x00000050, "No interrupt pending") +NV_STATUS_CODE(NV_ERR_NO_MEMORY, 0x00000051, "Out of memory") +NV_STATUS_CODE(NV_ERR_NO_SUCH_DOMAIN, 0x00000052, "Requested domain does not exist") +NV_STATUS_CODE(NV_ERR_NO_VALID_PATH, 0x00000053, "Caller did not specify a valid path") +NV_STATUS_CODE(NV_ERR_NOT_COMPATIBLE, 0x00000054, "Generic Error: Incompatible types") +NV_STATUS_CODE(NV_ERR_NOT_READY, 0x00000055, "Generic Error: Not ready") +NV_STATUS_CODE(NV_ERR_NOT_SUPPORTED, 0x00000056, "Call not supported") +NV_STATUS_CODE(NV_ERR_OBJECT_NOT_FOUND, 0x00000057, "Requested object not found") +NV_STATUS_CODE(NV_ERR_OBJECT_TYPE_MISMATCH, 0x00000058, "Specified objects do not match") +NV_STATUS_CODE(NV_ERR_OPERATING_SYSTEM, 0x00000059, "Generic operating system error") +NV_STATUS_CODE(NV_ERR_OTHER_DEVICE_FOUND, 0x0000005A, "Found other device instead of the requested one") +NV_STATUS_CODE(NV_ERR_OUT_OF_RANGE, 0x0000005B, "The specified value is out of bounds") +NV_STATUS_CODE(NV_ERR_OVERLAPPING_UVM_COMMIT, 0x0000005C, "Overlapping unified virtual memory commit") +NV_STATUS_CODE(NV_ERR_PAGE_TABLE_NOT_AVAIL, 0x0000005D, "Requested page table not available") +NV_STATUS_CODE(NV_ERR_PID_NOT_FOUND, 0x0000005E, "Process-Id not found") +NV_STATUS_CODE(NV_ERR_PROTECTION_FAULT, 0x0000005F, "Protection fault") +NV_STATUS_CODE(NV_ERR_RC_ERROR, 0x00000060, "Generic RC error") +NV_STATUS_CODE(NV_ERR_REJECTED_VBIOS, 0x00000061, "Given Video BIOS rejected/invalid") +NV_STATUS_CODE(NV_ERR_RESET_REQUIRED, 0x00000062, "Reset required") +NV_STATUS_CODE(NV_ERR_STATE_IN_USE, 0x00000063, "State in use") +NV_STATUS_CODE(NV_ERR_SIGNAL_PENDING, 0x00000064, "Signal pending") +NV_STATUS_CODE(NV_ERR_TIMEOUT, 0x00000065, "Call timed out") +NV_STATUS_CODE(NV_ERR_TIMEOUT_RETRY, 0x00000066, "Call timed out, please retry later") +NV_STATUS_CODE(NV_ERR_TOO_MANY_PRIMARIES, 0x00000067, "Too many primaries") +NV_STATUS_CODE(NV_ERR_UVM_ADDRESS_IN_USE, 0x00000068, "Unified virtual memory requested address already in use") +NV_STATUS_CODE(NV_ERR_MAX_SESSION_LIMIT_REACHED, 0x00000069, "Maximum number of sessions reached") +NV_STATUS_CODE(NV_ERR_LIB_RM_VERSION_MISMATCH, 0x0000006A, "Library version doesn't match driver version") // Contained within the RMAPI library +NV_STATUS_CODE(NV_ERR_PRIV_SEC_VIOLATION, 0x0000006B, "Priv security violation") +NV_STATUS_CODE(NV_ERR_GPU_IN_DEBUG_MODE, 0x0000006C, "GPU currently in debug mode") +NV_STATUS_CODE(NV_ERR_FEATURE_NOT_ENABLED, 0x0000006D, "Requested Feature functionality is not enabled") +NV_STATUS_CODE(NV_ERR_RESOURCE_LOST, 0x0000006E, "Requested resource has been destroyed") +NV_STATUS_CODE(NV_ERR_PMU_NOT_READY, 0x0000006F, "PMU is not ready or has not yet been initialized") +NV_STATUS_CODE(NV_ERR_FLCN_ERROR, 0x00000070, "Generic falcon assert or halt") +NV_STATUS_CODE(NV_ERR_FATAL_ERROR, 0x00000071, "Fatal/unrecoverable error") +NV_STATUS_CODE(NV_ERR_MEMORY_ERROR, 0x00000072, "Generic memory error") +NV_STATUS_CODE(NV_ERR_INVALID_LICENSE, 0x00000073, "License provided is rejected or invalid") +NV_STATUS_CODE(NV_ERR_NVLINK_INIT_ERROR, 0x00000074, "Nvlink Init Error") +NV_STATUS_CODE(NV_ERR_NVLINK_MINION_ERROR, 0x00000075, "Nvlink Minion Error") +NV_STATUS_CODE(NV_ERR_NVLINK_CLOCK_ERROR, 0x00000076, "Nvlink Clock Error") +NV_STATUS_CODE(NV_ERR_NVLINK_TRAINING_ERROR, 0x00000077, "Nvlink Training Error") +NV_STATUS_CODE(NV_ERR_NVLINK_CONFIGURATION_ERROR, 0x00000078, "Nvlink Configuration Error") +NV_STATUS_CODE(NV_ERR_RISCV_ERROR, 0x00000079, "Generic RISC-V assert or halt") +NV_STATUS_CODE(NV_ERR_FABRIC_MANAGER_NOT_PRESENT, 0x0000007A, "Fabric Manager is not loaded") +NV_STATUS_CODE(NV_ERR_ALREADY_SIGNALLED, 0x0000007B, "Semaphore Surface value already >= requested wait value") +NV_STATUS_CODE(NV_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE, 0x0000007C, "PMU RPC error due to no queue slot available for this event") +NV_STATUS_CODE(NV_ERR_KEY_ROTATION_IN_PROGRESS, 0x0000007D, "Operation not allowed as key rotation is in progress") +NV_STATUS_CODE(NV_ERR_TEST_ONLY_CODE_NOT_ENABLED, 0x0000007E, "Test-only code path not enabled") +NV_STATUS_CODE(NV_ERR_SECURE_BOOT_FAILED, 0x0000007F, "GFW secure boot failed") +NV_STATUS_CODE(NV_ERR_INSUFFICIENT_ZBC_ENTRY, 0x00000080, "No more ZBC entry for the client") +NV_STATUS_CODE(NV_ERR_NVLINK_FABRIC_NOT_READY, 0x00000081, "Nvlink Fabric Status or Fabric Probe is not yet complete, caller needs to retry") +NV_STATUS_CODE(NV_ERR_NVLINK_FABRIC_FAILURE, 0x00000082, "Nvlink Fabric Probe failed") +NV_STATUS_CODE(NV_ERR_GPU_MEMORY_ONLINING_FAILURE, 0x00000083, "GPU Memory Onlining failed") +NV_STATUS_CODE(NV_ERR_REDUCTION_MANAGER_NOT_AVAILABLE, 0x00000084, "Reduction Manager is not available") +NV_STATUS_CODE(NV_ERR_THRESHOLD_CROSSED, 0x00000085, "A fatal threshold has been crossed") +NV_STATUS_CODE(NV_ERR_RESOURCE_RETIREMENT_ERROR, 0x00000086, "An error occurred while trying to retire a resource") +NV_STATUS_CODE(NV_ERR_FABRIC_STATE_OUT_OF_SYNC, 0x00000087, "NVLink fabric state cached by the driver is out of sync") +NV_STATUS_CODE(NV_ERR_BUFFER_FULL, 0x00000088, "Buffer is full") +NV_STATUS_CODE(NV_ERR_BUFFER_EMPTY, 0x00000089, "Buffer is empty") +NV_STATUS_CODE(NV_ERR_MC_FLA_OFFSET_TABLE_FULL, 0x0000008A, "Multicast FLA offset table has no available slots") +NV_STATUS_CODE(NV_ERR_OPERATION_ABORTED, 0x0000008B, "Operation has aborted") +NV_STATUS_CODE(NV_ERR_DMA_XFER_FAILED, 0x0000008C, "DMA transfer failed") +NV_STATUS_CODE(NV_ERR_RESOURCE_ACCOUNTING_HARD_LIMIT_EXCEEDED, 0x0000008D, "Resource accounting rejected request (hard limit)") + +// Warnings: +NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch") +NV_STATUS_CODE(NV_WARN_INCORRECT_PERFMON_DATA, 0x00010002, "WARNING Incorrect performance monitor data") +NV_STATUS_CODE(NV_WARN_MISMATCHED_SLAVE, 0x00010003, "WARNING Slave mismatch") +NV_STATUS_CODE(NV_WARN_MISMATCHED_TARGET, 0x00010004, "WARNING Target mismatch") +NV_STATUS_CODE(NV_WARN_MORE_PROCESSING_REQUIRED, 0x00010005, "WARNING More processing required for the call") +NV_STATUS_CODE(NV_WARN_NOTHING_TO_DO, 0x00010006, "WARNING Nothing to do") +NV_STATUS_CODE(NV_WARN_NULL_OBJECT, 0x00010007, "WARNING NULL object found") +NV_STATUS_CODE(NV_WARN_OUT_OF_RANGE, 0x00010008, "WARNING value out of range") +NV_STATUS_CODE(NV_WARN_THRESHOLD_CROSSED, 0x00010009, "WARNING Threshold has been crossed") +NV_STATUS_CODE(NV_WARN_RESOURCE_ACCOUNTING_SOFT_LIMIT_EXCEEDED, 0x0001000A, "Resource accounting rejected request (soft limit)") + +#endif /* SDK_NVSTATUSCODES_H */ diff --git a/userspace/sdks/nv570/inc/nvtypes.h b/userspace/sdks/nv570/inc/nvtypes.h new file mode 100644 index 0000000..7098d00 --- /dev/null +++ b/userspace/sdks/nv570/inc/nvtypes.h @@ -0,0 +1,793 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVTYPES_INCLUDED +#define NVTYPES_INCLUDED + +#include "cpuopsys.h" + +#ifndef NVTYPES_USE_STDINT +#define NVTYPES_USE_STDINT 0 +#endif + +#if NVTYPES_USE_STDINT +#ifdef __cplusplus +#include +#include +#else +#include +#include +#endif // __cplusplus +#endif // NVTYPES_USE_STDINT + +#ifndef __cplusplus +// Header includes to make sure wchar_t is defined for C-file compilation +// (C++ is not affected as it is a fundamental type there) +// _MSC_VER is a hack to avoid failures for old setup of UEFI builds which are +// currently set to msvc100 but do not properly set the include paths +#endif // __cplusplus + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(MAKE_NV64TYPES_8BYTES_ALIGNED) && defined(__i386__) +// ensure or force 8-bytes alignment of NV 64-bit types +#define OPTIONAL_ALIGN8_ATTR __attribute__((aligned(8))) +#else +// nothing needed +#define OPTIONAL_ALIGN8_ATTR +#endif // MAKE_NV64TYPES_8BYTES_ALIGNED && i386 + + /***************************************************************************\ +|* Typedefs *| + \***************************************************************************/ + +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +//Typedefs for MISRA COMPLIANCE +typedef unsigned long long UInt64; +typedef signed long long Int64; +typedef unsigned int UInt32; +typedef signed int Int32; +typedef unsigned short UInt16; +typedef signed short Int16; +typedef unsigned char UInt8 ; +typedef signed char Int8 ; + +typedef void Void; +typedef float float32_t; +typedef double float64_t; +#endif + + +// Floating point types +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +typedef float32_t NvF32; /* IEEE Single Precision (S1E8M23) */ +typedef float64_t NvF64 OPTIONAL_ALIGN8_ATTR; /* IEEE Double Precision (S1E11M52) */ +#else +typedef float NvF32; /* IEEE Single Precision (S1E8M23) */ +typedef double NvF64 OPTIONAL_ALIGN8_ATTR; /* IEEE Double Precision (S1E11M52) */ +#endif + + +// 8-bit: 'char' is the only 8-bit in the C89 standard and after. +#if NVTYPES_USE_STDINT +typedef uint8_t NvV8; /* "void": enumerated or multiple fields */ +typedef uint8_t NvU8; /* 0 to 255 */ +typedef int8_t NvS8; /* -128 to 127 */ +#else +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +typedef UInt8 NvV8; /* "void": enumerated or multiple fields */ +typedef UInt8 NvU8; /* 0 to 255 */ +typedef Int8 NvS8; /* -128 to 127 */ +#else +typedef unsigned char NvV8; /* "void": enumerated or multiple fields */ +typedef unsigned char NvU8; /* 0 to 255 */ +typedef signed char NvS8; /* -128 to 127 */ +#endif +#endif // NVTYPES_USE_STDINT + + +#if NVTYPES_USE_STDINT +typedef uint16_t NvV16; /* "void": enumerated or multiple fields */ +typedef uint16_t NvU16; /* 0 to 65535 */ +typedef int16_t NvS16; /* -32768 to 32767 */ +#else +// 16-bit: If the compiler tells us what we can use, then use it. +#ifdef __INT16_TYPE__ +typedef unsigned __INT16_TYPE__ NvV16; /* "void": enumerated or multiple fields */ +typedef unsigned __INT16_TYPE__ NvU16; /* 0 to 65535 */ +typedef signed __INT16_TYPE__ NvS16; /* -32768 to 32767 */ + +// The minimal standard for C89 and after +#else // __INT16_TYPE__ +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +typedef UInt16 NvV16; /* "void": enumerated or multiple fields */ +typedef UInt16 NvU16; /* 0 to 65535 */ +typedef Int16 NvS16; /* -32768 to 32767 */ +#else +typedef unsigned short NvV16; /* "void": enumerated or multiple fields */ +typedef unsigned short NvU16; /* 0 to 65535 */ +typedef signed short NvS16; /* -32768 to 32767 */ +#endif +#endif // __INT16_TYPE__ +#endif // NVTYPES_USE_STDINT + +// wchar type (fixed size types consistent across Linux/Windows boundaries) +#if defined(NV_HAS_WCHAR_T_TYPEDEF) + typedef wchar_t NvWchar; +#else + typedef NvV16 NvWchar; +#endif + +// Macro to build an NvU32 from four bytes, listed from msb to lsb +#define NvU32_BUILD(a, b, c, d) \ + ((NvU32)( \ + (((NvU32)(a) & 0xff) << 24) | \ + (((NvU32)(b) & 0xff) << 16) | \ + (((NvU32)(c) & 0xff) << 8) | \ + (((NvU32)(d) & 0xff)))) + +// Macro to build an NvU64 from two DWORDS, listed from msb to lsb +#define NvU64_BUILD(a, b) \ + ((NvU64)( \ + (((NvU64)(a) & ~0U) << 32) | \ + (((NvU64)(b) & ~0U)))) + +#if NVTYPES_USE_STDINT +typedef uint32_t NvV32; /* "void": enumerated or multiple fields */ +typedef uint32_t NvU32; /* 0 to 4294967295 */ +typedef int32_t NvS32; /* -2147483648 to 2147483647 */ +#else +// 32-bit: If the compiler tells us what we can use, then use it. +#ifdef __INT32_TYPE__ +typedef unsigned __INT32_TYPE__ NvV32; /* "void": enumerated or multiple fields */ +typedef unsigned __INT32_TYPE__ NvU32; /* 0 to 4294967295 */ +typedef signed __INT32_TYPE__ NvS32; /* -2147483648 to 2147483647 */ + +// Older compilers +#else // __INT32_TYPE__ + +// For historical reasons, NvU32/NvV32 are defined to different base intrinsic +// types than NvS32 on some platforms. +// Mainly for 64-bit linux, where long is 64 bits and win9x, where int is 16 bit. +#if (defined(NV_UNIX) || defined(vxworks) || defined(NV_WINDOWS_CE) || \ + defined(__arm) || defined(__IAR_SYSTEMS_ICC__) || defined(NV_QNX) || \ + defined(NV_INTEGRITY) || defined(NV_MODS) || \ + defined(__GNUC__) || defined(__clang__) || defined(NV_MACINTOSH_64)) && \ + (!defined(NV_MACINTOSH) || defined(NV_MACINTOSH_64)) +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +typedef UInt32 NvV32; /* "void": enumerated or multiple fields */ +typedef UInt32 NvU32; /* 0 to 4294967295 */ +#else +typedef unsigned int NvV32; /* "void": enumerated or multiple fields */ +typedef unsigned int NvU32; /* 0 to 4294967295 */ +#endif + +// The minimal standard for C89 and after +#else // (defined(NV_UNIX) || defined(vxworks) || ... +typedef unsigned long NvV32; /* "void": enumerated or multiple fields */ +typedef unsigned long NvU32; /* 0 to 4294967295 */ +#endif // (defined(NV_UNIX) || defined(vxworks) || ... + +// Mac OS 32-bit still needs this +#if defined(NV_MACINTOSH) && !defined(NV_MACINTOSH_64) +typedef signed long NvS32; /* -2147483648 to 2147483647 */ +#else +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +typedef Int32 NvS32; /* -2147483648 to 2147483647 */ +#else +typedef signed int NvS32; /* -2147483648 to 2147483647 */ +#endif +#endif // defined(NV_MACINTOSH) && !defined(NV_MACINTOSH_64) +#endif // __INT32_TYPE__ +#endif // NVTYPES_USE_STDINT + + + +#if NVTYPES_USE_STDINT +typedef uint64_t NvU64 OPTIONAL_ALIGN8_ATTR; /* 0 to 18446744073709551615 */ +typedef int64_t NvS64 OPTIONAL_ALIGN8_ATTR; /* -9223372036854775808 to 9223372036854775807 */ + +#define NvU64_fmtX PRIX64 +#define NvU64_fmtx PRIx64 +#define NvU64_fmtu PRIu64 +#define NvU64_fmto PRIo64 +#define NvS64_fmtd PRId64 +#define NvS64_fmti PRIi64 +#else +// 64-bit types for compilers that support them, plus some obsolete variants +#if defined(__GNUC__) || defined(__clang__) || defined(__arm) || \ + defined(__IAR_SYSTEMS_ICC__) || defined(__ghs__) || defined(_WIN64) || \ + defined(__SUNPRO_C) || defined(__SUNPRO_CC) || defined (__xlC__) +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +typedef UInt64 NvU64 OPTIONAL_ALIGN8_ATTR; /* 0 to 18446744073709551615 */ +typedef Int64 NvS64 OPTIONAL_ALIGN8_ATTR; /* -9223372036854775808 to 9223372036854775807 */ +#else +typedef unsigned long long NvU64 OPTIONAL_ALIGN8_ATTR; /* 0 to 18446744073709551615 */ +typedef long long NvS64 OPTIONAL_ALIGN8_ATTR; /* -9223372036854775808 to 9223372036854775807 */ +#endif + +#define NvU64_fmtX "llX" +#define NvU64_fmtx "llx" +#define NvU64_fmtu "llu" +#define NvU64_fmto "llo" +#define NvS64_fmtd "lld" +#define NvS64_fmti "lli" + +// Microsoft since 2003 -- https://msdn.microsoft.com/en-us/library/29dh1w7z.aspx +#else +typedef unsigned __int64 NvU64 OPTIONAL_ALIGN8_ATTR; /* 0 to 18446744073709551615 */ +typedef __int64 NvS64 OPTIONAL_ALIGN8_ATTR; /* -9223372036854775808 to 9223372036854775807 */ + +#define NvU64_fmtX "I64X" +#define NvU64_fmtx "I64x" +#define NvU64_fmtu "I64u" +#define NvU64_fmto "I64o" +#define NvS64_fmtd "I64d" +#define NvS64_fmti "I64i" + +#endif +#endif // NVTYPES_USE_STDINT + +#ifdef NV_TYPESAFE_HANDLES +/* + * Can't use opaque pointer as clients might be compiled with mismatched + * pointer sizes. TYPESAFE check will eventually be removed once all clients + * have transistioned safely to NvHandle. + * The plan is to then eventually scale up the handle to be 64-bits. + */ +typedef struct +{ + NvU32 val; +} NvHandle; +#else +/* + * For compatibility with modules that haven't moved typesafe handles. + */ +typedef NvU32 NvHandle; +#endif // NV_TYPESAFE_HANDLES + +/* Boolean type */ +typedef NvU8 NvBool; +#define NV_TRUE ((NvBool)(0 == 0)) +#define NV_FALSE ((NvBool)(0 != 0)) + +/* Tristate type: NV_TRISTATE_FALSE, NV_TRISTATE_TRUE, NV_TRISTATE_INDETERMINATE */ +typedef NvU8 NvTristate; +#define NV_TRISTATE_FALSE ((NvTristate) 0) +#define NV_TRISTATE_TRUE ((NvTristate) 1) +#define NV_TRISTATE_INDETERMINATE ((NvTristate) 2) + +/* Macros to extract the low and high parts of a 64-bit unsigned integer */ +/* Also designed to work if someone happens to pass in a 32-bit integer */ +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +#define NvU64_HI32(n) ((NvU32)((((NvU64)(n)) >> 32) & 0xffffffffU)) +#define NvU64_LO32(n) ((NvU32)(( (NvU64)(n)) & 0xffffffffU)) +#else +#define NvU64_HI32(n) ((NvU32)((((NvU64)(n)) >> 32) & 0xffffffff)) +#define NvU64_LO32(n) ((NvU32)(( (NvU64)(n)) & 0xffffffff)) +#endif +#define NvU40_HI32(n) ((NvU32)((((NvU64)(n)) >> 8) & 0xffffffffU)) +#define NvU40_HI24of32(n) ((NvU32)( (NvU64)(n) & 0xffffff00U)) + +/* Macros to get the MSB and LSB of a 32 bit unsigned number */ +#define NvU32_HI16(n) ((NvU16)((((NvU32)(n)) >> 16) & 0xffffU)) +#define NvU32_LO16(n) ((NvU16)(( (NvU32)(n)) & 0xffffU)) + + /***************************************************************************\ +|* *| +|* 64 bit type definitions for use in interface structures. *| +|* *| + \***************************************************************************/ + +#if defined(NV_64_BITS) + +typedef void* NvP64; /* 64 bit void pointer */ +typedef NvU64 NvUPtr; /* pointer sized unsigned int */ +typedef NvS64 NvSPtr; /* pointer sized signed int */ +typedef NvU64 NvLength; /* length to agree with sizeof */ + +#define NvP64_VALUE(n) (n) +#define NvP64_fmt "%p" + +#define KERNEL_POINTER_FROM_NvP64(p,v) ((p)(v)) +#define NvP64_PLUS_OFFSET(p,o) (NvP64)((NvU64)(p) + (NvU64)(o)) + +#define NvUPtr_fmtX NvU64_fmtX +#define NvUPtr_fmtx NvU64_fmtx +#define NvUPtr_fmtu NvU64_fmtu +#define NvUPtr_fmto NvU64_fmto +#define NvSPtr_fmtd NvS64_fmtd +#define NvSPtr_fmti NvS64_fmti + +#else + +typedef NvU64 NvP64; /* 64 bit void pointer */ +typedef NvU32 NvUPtr; /* pointer sized unsigned int */ +typedef NvS32 NvSPtr; /* pointer sized signed int */ +typedef NvU32 NvLength; /* length to agree with sizeof */ + +#define NvP64_VALUE(n) ((void *)(NvUPtr)(n)) +#define NvP64_fmt "0x%llx" + +#define KERNEL_POINTER_FROM_NvP64(p,v) ((p)(NvUPtr)(v)) +#define NvP64_PLUS_OFFSET(p,o) ((p) + (NvU64)(o)) + +#define NvUPtr_fmtX "X" +#define NvUPtr_fmtx "x" +#define NvUPtr_fmtu "u" +#define NvUPtr_fmto "o" +#define NvSPtr_fmtd "d" +#define NvSPtr_fmti "i" + +#endif + +#define NvP64_NULL (NvP64)0 + +/*! + * Helper macro to pack an @ref NvU64_ALIGN32 structure from a @ref NvU64. + * + * @param[out] pDst Pointer to NvU64_ALIGN32 structure to pack + * @param[in] pSrc Pointer to NvU64 with which to pack + */ +#define NvU64_ALIGN32_PACK(pDst, pSrc) \ +do { \ + (pDst)->lo = NvU64_LO32(*(pSrc)); \ + (pDst)->hi = NvU64_HI32(*(pSrc)); \ +} while (NV_FALSE) + +/*! + * Helper macro to unpack a @ref NvU64_ALIGN32 structure into a @ref NvU64. + * + * @param[out] pDst Pointer to NvU64 in which to unpack + * @param[in] pSrc Pointer to NvU64_ALIGN32 structure from which to unpack + */ +#define NvU64_ALIGN32_UNPACK(pDst, pSrc) \ +do { \ + (*(pDst)) = NvU64_ALIGN32_VAL(pSrc); \ +} while (NV_FALSE) + +/*! + * Helper macro to unpack a @ref NvU64_ALIGN32 structure as a @ref NvU64. + * + * @param[in] pSrc Pointer to NvU64_ALIGN32 structure to unpack + */ +#define NvU64_ALIGN32_VAL(pSrc) \ + ((NvU64) ((NvU64)((pSrc)->lo) | (((NvU64)(pSrc)->hi) << 32U))) + +/*! + * Helper macro to check whether the 32 bit aligned 64 bit number is zero. + * + * @param[in] _pU64 Pointer to NvU64_ALIGN32 structure. + * + * @return + * NV_TRUE _pU64 is zero. + * NV_FALSE otherwise. + */ +#define NvU64_ALIGN32_IS_ZERO(_pU64) \ + (((_pU64)->lo == 0U) && ((_pU64)->hi == 0U)) + +/*! + * Helper macro to sub two 32 aligned 64 bit numbers on 64 bit processor. + * + * @param[in] pSrc1 Pointer to NvU64_ALIGN32 source 1 structure. + * @param[in] pSrc2 Pointer to NvU64_ALIGN32 source 2 structure. + * @param[in/out] pDst Pointer to NvU64_ALIGN32 dest. structure. + */ +#define NvU64_ALIGN32_ADD(pDst, pSrc1, pSrc2) \ +do { \ + NvU64 __dst, __src1, __scr2; \ + \ + NvU64_ALIGN32_UNPACK(&__src1, (pSrc1)); \ + NvU64_ALIGN32_UNPACK(&__scr2, (pSrc2)); \ + __dst = __src1 + __scr2; \ + NvU64_ALIGN32_PACK((pDst), &__dst); \ +} while (NV_FALSE) + +/*! + * Helper macro to sub two 32 aligned 64 bit numbers on 64 bit processor. + * + * @param[in] pSrc1 Pointer to NvU64_ALIGN32 source 1 structure. + * @param[in] pSrc2 Pointer to NvU64_ALIGN32 source 2 structure. + * @param[in/out] pDst Pointer to NvU64_ALIGN32 dest. structure. + */ +#define NvU64_ALIGN32_SUB(pDst, pSrc1, pSrc2) \ +do { \ + NvU64 __dst, __src1, __scr2; \ + \ + NvU64_ALIGN32_UNPACK(&__src1, (pSrc1)); \ + NvU64_ALIGN32_UNPACK(&__scr2, (pSrc2)); \ + __dst = __src1 - __scr2; \ + NvU64_ALIGN32_PACK((pDst), &__dst); \ +} while (NV_FALSE) + +/*! + * Structure for representing 32 bit aligned NvU64 (64-bit unsigned integer) + * structures. This structure must be used because the 32 bit processor and + * 64 bit processor compilers will pack/align NvU64 differently. + * + * One use case is RM being 64 bit proc whereas PMU being 32 bit proc, this + * alignment difference will result in corrupted transactions between the RM + * and PMU. + * + * See the @ref NvU64_ALIGN32_PACK and @ref NvU64_ALIGN32_UNPACK macros for + * packing and unpacking these structures. + * + * @note The intention of this structure is to provide a datatype which will + * packed/aligned consistently and efficiently across all platforms. + * We don't want to use "NV_DECLARE_ALIGNED(NvU64, 8)" because that + * leads to memory waste on our 32-bit uprocessors (e.g. FALCONs) where + * DMEM efficiency is vital. + */ +typedef struct +{ + /*! + * Low 32 bits. + */ + NvU32 lo; + /*! + * High 32 bits. + */ + NvU32 hi; +} NvU64_ALIGN32; + +/* Useful macro to hide required double cast */ +#define NV_PTR_TO_NvP64(n) (NvP64)(NvUPtr)(n) +#define NV_SIGN_EXT_PTR_TO_NvP64(p) ((NvP64)(NvS64)(NvSPtr)(p)) +#define KERNEL_POINTER_TO_NvP64(p) ((NvP64)(uintptr_t)(p)) + + /***************************************************************************\ +|* *| +|* Limits for common types. *| +|* *| + \***************************************************************************/ + +/* Explanation of the current form of these limits: + * + * - Decimal is used, as hex values are by default positive. + * - Casts are not used, as usage in the preprocessor itself (#if) ends poorly. + * - The subtraction of 1 for some MIN values is used to get around the fact + * that the C syntax actually treats -x as NEGATE(x) instead of a distinct + * number. Since 214748648 isn't a valid positive 32-bit signed value, we + * take the largest valid positive signed number, negate it, and subtract 1. + */ +#define NV_S8_MIN (-128) +#define NV_S8_MAX (+127) +#define NV_U8_MIN (0U) +#define NV_U8_MAX (+255U) +#define NV_S16_MIN (-32768) +#define NV_S16_MAX (+32767) +#define NV_U16_MIN (0U) +#define NV_U16_MAX (+65535U) +#define NV_S32_MIN (-2147483647 - 1) +#define NV_S32_MAX (+2147483647) +#define NV_U32_MIN (0U) +#define NV_U32_MAX (+4294967295U) +#define NV_S64_MIN (-9223372036854775807LL - 1LL) +#define NV_S64_MAX (+9223372036854775807LL) +#define NV_U64_MIN (0ULL) +#define NV_U64_MAX (+18446744073709551615ULL) + +/* Aligns fields in structs so they match up between 32 and 64 bit builds */ +#if defined(__GNUC__) || defined(__clang__) || defined(NV_QNX) +#define NV_ALIGN_BYTES(size) __attribute__ ((aligned (size))) +#elif defined(__arm) +#define NV_ALIGN_BYTES(size) __align(ALIGN) +#else +// XXX This is dangerously nonportable! We really shouldn't provide a default +// version of this that doesn't do anything. +#define NV_ALIGN_BYTES(size) +#endif + +// NV_DECLARE_ALIGNED() can be used on all platforms. +// This macro form accounts for the fact that __declspec on Windows is required +// before the variable type, +// and NV_ALIGN_BYTES is required after the variable name. +#if defined(__GNUC__) || defined(__clang__) || defined(NV_QNX) +#define NV_DECLARE_ALIGNED(TYPE_VAR, ALIGN) TYPE_VAR __attribute__ ((aligned (ALIGN))) +#elif defined(__arm) +#define NV_DECLARE_ALIGNED(TYPE_VAR, ALIGN) __align(ALIGN) TYPE_VAR +#endif + +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) +#define NV_ALIGNOF(type) _Alignof(type) +#elif defined(__cplusplus) && (__cplusplus >= 201103L) +#define NV_ALIGNOF(type) alignof(type) +#elif defined(__GNUC__) || defined(__clang__) +#define NV_ALIGNOF(type) __alignof__(type) +#endif + + /***************************************************************************\ +|* Function Declaration Types *| + \***************************************************************************/ + +// stretching the meaning of "nvtypes", but this seems to least offensive +// place to re-locate these from nvos.h which cannot be included by a number +// of builds that need them + +#if defined(__GNUC__) || defined(__clang__) || defined(__INTEL_COMPILER) + #define NV_ATTRIBUTE_UNUSED __attribute__((__unused__)) +#else + #define NV_ATTRIBUTE_UNUSED +#endif + + #if defined(__GNUC__) + #if (__GNUC__ > 3) || \ + ((__GNUC__ == 3) && (__GNUC_MINOR__ >= 1) && (__GNUC_PATCHLEVEL__ >= 1)) + #define NV_NOINLINE __attribute__((__noinline__)) + #endif + #elif defined(__clang__) + #if __has_attribute(noinline) + #define NV_NOINLINE __attribute__((__noinline__)) + #endif + #elif defined(__arm) && (__ARMCC_VERSION >= 300000) + #define NV_NOINLINE __attribute__((__noinline__)) + #elif (defined(__SUNPRO_C) && (__SUNPRO_C >= 0x590)) ||\ + (defined(__SUNPRO_CC) && (__SUNPRO_CC >= 0x590)) + #define NV_NOINLINE __attribute__((__noinline__)) + #elif defined (__INTEL_COMPILER) + #define NV_NOINLINE __attribute__((__noinline__)) + #endif + + #if !defined(NV_NOINLINE) + #define NV_NOINLINE + #endif + + /* GreenHills compiler defines __GNUC__, but doesn't support + * __inline__ keyword. */ + #if defined(__ghs__) + #define NV_INLINE inline + #elif defined(__GNUC__) || defined(__clang__) || defined(__INTEL_COMPILER) + #define NV_INLINE __inline__ + #elif defined (macintosh) || defined(__SUNPRO_C) || defined(__SUNPRO_CC) + #define NV_INLINE inline + #elif defined(__arm) + #define NV_INLINE __inline + #else + #define NV_INLINE + #endif + + /* Don't force inline on DEBUG builds -- it's annoying for debuggers. */ + #if !defined(DEBUG) + /* GreenHills compiler defines __GNUC__, but doesn't support + * __attribute__ or __inline__ keyword. */ + #if defined(__ghs__) + #define NV_FORCEINLINE inline + #elif defined(__GNUC__) + // GCC 3.1 and beyond support the always_inline function attribute. + #if (__GNUC__ > 3) || ((__GNUC__ == 3) && (__GNUC_MINOR__ >= 1)) + #define NV_FORCEINLINE __attribute__((__always_inline__)) __inline__ + #else + #define NV_FORCEINLINE __inline__ + #endif + #elif defined(__clang__) + #if __has_attribute(always_inline) + #define NV_FORCEINLINE __attribute__((__always_inline__)) __inline__ + #else + #define NV_FORCEINLINE __inline__ + #endif + #elif defined(__arm) && (__ARMCC_VERSION >= 220000) + // RVDS 2.2 also supports forceinline, but ADS 1.2 does not + #define NV_FORCEINLINE __forceinline + #else /* defined(__GNUC__) */ + #define NV_FORCEINLINE NV_INLINE + #endif + #else + #define NV_FORCEINLINE NV_INLINE + #endif + + #define NV_APIENTRY + #define NV_FASTCALL + #define NV_CDECLCALL + #define NV_STDCALL + + /* + * The 'warn_unused_result' function attribute prompts GCC to issue a + * warning if the result of a function tagged with this attribute + * is ignored by a caller. In combination with '-Werror', it can be + * used to enforce result checking in RM code; at this point, this + * is only done on UNIX. + */ + #if defined(__GNUC__) && defined(NV_UNIX) + #if (__GNUC__ > 3) || ((__GNUC__ == 3) && (__GNUC_MINOR__ >= 4)) + #define NV_FORCERESULTCHECK __attribute__((__warn_unused_result__)) + #else + #define NV_FORCERESULTCHECK + #endif + #elif defined(__clang__) + #if __has_attribute(warn_unused_result) + #define NV_FORCERESULTCHECK __attribute__((__warn_unused_result__)) + #else + #define NV_FORCERESULTCHECK + #endif + #else /* defined(__GNUC__) */ + #define NV_FORCERESULTCHECK + #endif + + /* + * Functions decorated with NV_FORMAT_PRINTF(f, a) have a format string at + * parameter number 'f' and variadic arguments start at parameter number 'a'. + * (Note that for C++ methods, there is an implicit 'this' parameter so + * explicit parameters are numbered from 2.) + */ + #if defined(__GNUC__) + #define NV_FORMAT_PRINTF(_f, _a) __attribute__((format(printf, _f, _a))) + #else + #define NV_FORMAT_PRINTF(_f, _a) + #endif + + /***************************************************************************\ +|* *| +|* Definitions of binary/bytes representations of floating point values *| +|* *| +|* Intended for use when passing values across kernel contexts in which *| +|* floating point use is forbidden *| +|* *| + \***************************************************************************/ +// +// Determine whether we have to turn FP32 support off based on compiler flags. +// For now, this is only done when we can detect that we're compiling for x86_64 +// with GCC/clang and SSE is disabled. +// +// This is also currently only used to control NvF32Bytes definitions. +// +// In the future, it could be possible to: +// 1.) Define this more generally +// and +// 2.) Use it in more places +// +// This would allow us to fully prevent usage of NvF32 in codebases where it is +// not supported. +// +#if !defined(NVTYPES_NV_F32_SUPPORTED) && NVCPU_IS_X86_64 && (defined(__GNUC__) || defined(__clang__)) && !defined(__SSE__) +#define NVTYPES_NV_F32_SUPPORTED 0 +#else +#define NVTYPES_NV_F32_SUPPORTED 1 +#endif + +/*! + * A struct containing the 32-bit representation of an (IEEE-754 binary32) + * floating point value, i.e., the raw underlying bytes of an @ref NvF32 + * + * This struct must be used in places where a value may be passed across a + * kernel boundary, as use of floating point within some kernels is, in general, + * banned. + */ +typedef struct +{ + NvU32 value; +} NvF32Bytes; + +#if !defined(NVDEC_1_0) +/*! + * @brief Maps the bytes of a given @ref NvF32 to an @ref NvF32Bytes + * + * @param[in] pfValue + * Pointer to value to convert + * + * @return @ref NvF32Bytes byte-mapped from @p *pfValue + */ +static NV_FORCEINLINE NvF32Bytes +nvF32BytesMapFromNvF32 +( + const NvF32 *pfValue +) +{ + union + { + NvF32 f; + NvF32Bytes b; + } value; + + value.f = *pfValue; + + return value.b; +} + +#if NVTYPES_NV_F32_SUPPORTED +/*! + * @brief Maps the bytes of a given @ref NvF32Bytes to an @ref NvF32 + * + * @param[in] pfValue + * Pointer to value to convert + * + * @return @ref NvF32 byte-mapped from @p *pfValue + */ +static NV_FORCEINLINE NvF32 +nvF32BytesMapToNvF32 +( + const NvF32Bytes *pfValue +) +{ + union + { + NvF32Bytes b; + NvF32 f; + } value; + + value.b = *pfValue; + + return value.f; +} +#endif // NVTYPES_NV_F32_SUPPORTED + +/*! + * @brief Maps the bytes of a given @ref NvU32 to an @ref NvF32Bytes + * + * @details This function is intended for first "moving" raw byte values into + * the "floating point domain." + * + * @param[in] pfValue + * Pointer to value to convert + * + * @return @ref NvF32Bytes byte-mapped from @p *pfValue + */ +static NV_FORCEINLINE NvF32Bytes +nvF32BytesMapFromNvU32 +( + const NvU32 *pfValue +) +{ + union + { + NvU32 u; + NvF32Bytes b; + } value; + + value.u = *pfValue; + + return value.b; +} + +/*! + * @brief Maps the bytes of a given @ref NvF32Bytes to an @ref NvU32 + * + * @param[in] pfValue + * Pointer to value to convert + * + * @return @ref NvU32 byte-mapped from @p *pfValue + */ +static NV_FORCEINLINE NvU32 +nvF32BytesMapToNvU32 +( + const NvF32Bytes *pfValue +) +{ + union + { + NvF32Bytes b; + NvU32 u; + } value; + + value.b = *pfValue; + + return value.u; +} +#endif // !defined(NVDEC_1_0) + +#ifdef __cplusplus +} +#endif + +#endif /* NVTYPES_INCLUDED */ diff --git a/userspace/sdks/nv570/inc/rmcd.h b/userspace/sdks/nv570/inc/rmcd.h new file mode 100644 index 0000000..2461e56 --- /dev/null +++ b/userspace/sdks/nv570/inc/rmcd.h @@ -0,0 +1,394 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2002-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef RMCD_H +#define RMCD_H + +//****************************************************************************** +// +// Module Name: RMCD.H +// +// This file contains structures and constants that define the resource manager +// specific data for the crash dump file. The record definitions defined here +// are always stored after the crash dump file header. Each record defined here +// is preceded by the NVCD_RECORD structure. +// +//****************************************************************************** + +#include "nvgputypes.h" +#include "nvcd.h" + +#define NV_RMCD_VERSION (20) + +// Define RC Reset Callback function type +#define RM_RC_CALLBACK_HANDLE_UPDATE 1 +#if RM_RC_CALLBACK_HANDLE_UPDATE +typedef NvU32 RC_RESET_CALLBACK(NvHandle hClient, NvHandle hDevice, NvHandle hFifo, NvHandle hChannel, + void *pContext, NvBool clearRc); +#else +typedef NvU32 RC_RESET_CALLBACK(NvHandle hClient, NvHandle hDevice, NvHandle hChannel, void *pContext, NvBool clearRc); +#endif + +typedef struct _rc_error_context { + struct OBJGPU *pGpu; // GPU device + NvU32 ChId; // Channel ID of channel in RC recovery + NvU32 secChId; // Channel ID of secondary channel + NvHandle sechClient; // Client handle of secondary channel + NvU32 exceptType; // ROBUST_CHANNEL_* error identifier + NvU32 EngineId; // Engine ID of faulting engine + NvU32 subdeviceInstance; // This parameter returns the unicast subdevice instance number + // associated with the specified GPU. This value can be used to + // instantiate a unicast reference to the GPU using the NV20_SUBDEVICE + // classes. + + // FIFO_MMU_EXCEPTION_DATA + NvU32 addrLo; // MMU fault address (Lo) + NvU32 addrHi; // MMU fault address (Hi) + NvU32 faultType; // MMU fault code + const char *faultStr; // MMU fault string + +} RC_ERROR_CONTEXT, *PRC_ERROR_CONTEXT; + +#define MAX_FBBAS 0x2 +#define FBBA_MUX_SEL_MAX 0xF +#define FBBA_RXB_STATUS_SEL_MAX 0x10 +#define RDSTAT_MAX 0x2 + +// Define the resource manager group record types +typedef enum +{ + RmCurrentStateInfo_V2 = 4, // Revised Version 2 RM current state info. record + RmMissedNotifierInfo = 9, // RM Driver Indicates Missed Notifier + RmGlobalInfo_V3 = 10, // Revised Version 3 of Global Info + + RmProtoBuf = 131, // ProtoBuf + RmProtoBuf_V2 = 132, // ProtoBuf + NvDump + RmDclMsg = 133, // One of the optional DlcMsg fields, encoded + RmJournalEngDump = 134, + DP_ASSERT_HIT = 135, + DP_LOG_CALL = 136, + RmPrbFullDump = 137, // Full NvDump protobuf message + + // Includes RmRCCommonJournal_RECORD structure. + RmJournalBugCheck = 138, // Bugcheck record + RmRC2SwRmAssert_V3 = 139, // Retail logged RM_ASSERT info + RmRC2GpuTimeout_V3 = 140, // Retail logged RM_TIMEOUT events + RmRC2SwDbgBreakpoint_V3 = 141, // Uses same format as RmRC2SwRmAssert_V3 + RmBadRead_V2 = 142, // Record with Bad Read Information + RmSurpriseRemoval_V2 = 143, // Surprise Removal + RmPowerState = 144, // PowerState + RmPrbErrorInfo_V2 = 145, // Protobuf error record + RmPrbFullDump_V2 = 146, // Full NvDump protobuf message + RmRcDiagReport = 147, // Rc Diagnostic report message + RmNocatReport = 149, // Nocat reports. + RmDispState = 150, // Display error record + +} RMCD_RECORD_TYPE; + +typedef struct { + NVCD_RECORD Header; // Global information record header + NvU32 dwSize; // Total Protobuf Message Size +} RmProtoBuf_RECORD; +typedef RmProtoBuf_RECORD *PRmProtoBuf_RECORD; + +// +// Please include RmRCCommonJournal_RECORD structure at the top of all new and +// revised journal record structures. +// +#define NV_RM_JOURNAL_STATE_MASK_GC6_STATE 3:0 + +#define NV_RM_JOURNAL_STATE_MASK_IS_NOT_FULL_POWER 0x00000010 +#define NV_RM_JOURNAL_STATE_MASK_IS_NOT_CONNECTED 0x00000020 +#define NV_RM_JOURNAL_STATE_MASK_IS_IN_STANDBY 0x00000040 +#define NV_RM_JOURNAL_STATE_MASK_IS_IN_HIBERNATE 0x00000080 +#define NV_RM_JOURNAL_STATE_MASK_IS_IN_PM_CODEPATH 0x00000100 +#define NV_RM_JOURNAL_STATE_MASK_IS_IN_GC6_RESET 0x00000200 +#define NV_RM_JOURNAL_STATE_MASK_IS_IN_FULLCHIP_RESET 0x00000400 +#define NV_RM_JOURNAL_STATE_MASK_IS_IN_SEC_BUS_RESET 0x00000800 +#define NV_RM_JOURNAL_STATE_MASK_IS_IN_TIMEOUT_RECOVERY 0x00001000 +#define NV_RM_JOURNAL_STATE_MASK_IS_LOST 0x00002000 +#define NV_RM_JOURNAL_STATE_MASK_VIDMEM_FAILED_BAR0 0x00004000 +#define NV_RM_JOURNAL_STATE_MASK_VIDMEM_FAILED_BAR2 0x00008000 +#define NV_RM_JOURNAL_STATE_MASK_VIDMEM_FAILED_FBHUB 0x00010000 +#define NV_RM_JOURNAL_STATE_MASK_GSP_RM_ENABLED 0x00020000 + + +typedef struct _RmRCCommonJournal_RECORD +{ + NVCD_RECORD Header; + NvU32 GPUTag; + NvU64 CPUTag; + NvU64 timeStamp NV_ALIGN_BYTES(8); + NvU64 stateMask; + NvU8 *pNext; // temporary link used for sorting. + // note using type NvU8 because Linux + // generated code does not properly + // resove the refeerence to the struct type. + // & balks about void * type. +} RmRCCommonJournal_RECORD; +typedef RmRCCommonJournal_RECORD *PRmRCCommonJournal_RECORD; + +// RM_ASSERT + DBG_BREAKPOINT info +typedef struct +{ + RmRCCommonJournal_RECORD common; + NvU64 lastTimeStamp NV_ALIGN_BYTES(8); + NvU64 breakpointAddrHint NV_ALIGN_BYTES(8); // address that can identify bp module + NvU64 callStack[10] NV_ALIGN_BYTES(8); // Call stack when the assert occurred. + NvU32 count; + NvU32 lineNum; + NvU32 lastReportedCount; // last count reported to NOCAT + NvU64 nextReportedTimeStamp; // time stamp to use as start time for the + // next NOCAT report. +} RmRCCommonAssert_RECORD; +typedef RmRCCommonAssert_RECORD *PRmRCCommonAssert_RECORD; +#define NV_RM_ASSERT_UNKNOWN_LINE_NUM 0 + +typedef RmRCCommonAssert_RECORD RmRC2GpuTimeout3_RECORD; +typedef RmRC2GpuTimeout3_RECORD *PRmRC2GpuTimeout3_RECORD; + +// How Serious is this RM_ASSERT/DBG_BREAKPOINT +// (1) Info -- This is unexpected but we should continue to run +// (2) Error -- +// (3) Fatal -- This is hopeless -- FBI Timeout, Bus Error Etc +#define NV_RM_ASSERT_TYPE 3:0 +#define NV_RM_ASSERT_TYPE_INFO 0x00000001 +#define NV_RM_ASSERT_TYPE_ERROR 0x00000002 +#define NV_RM_ASSERT_TYPE_FATAL 0x00000003 + +// HW Unit which is having the issue +#define NV_RM_ASSERT_HW_UNIT 15:8 +#define NV_RM_ASSERT_HW_UNIT_NULL (0x00) +#define NV_RM_ASSERT_HW_UNIT_GRAPHICS (0x01) +#define NV_RM_ASSERT_HW_UNIT_COPY0 (0x02) +#define NV_RM_ASSERT_HW_UNIT_COPY1 (0x03) +#define NV_RM_ASSERT_HW_UNIT_VP (0x04) +#define NV_RM_ASSERT_HW_UNIT_ME (0x05) +#define NV_RM_ASSERT_HW_UNIT_PPP (0x06) +#define NV_RM_ASSERT_HW_UNIT_BSP (0x07) +#define NV_RM_ASSERT_HW_UNIT_NVDEC0 NV_RM_ASSERT_HW_UNIT_BSP +#define NV_RM_ASSERT_HW_UNIT_MPEG (0x08) +#define NV_RM_ASSERT_HW_UNIT_SW (0x09) +#define NV_RM_ASSERT_HW_UNIT_CIPHER (0x0a) +#define NV_RM_ASSERT_HW_UNIT_VIC (0x0b) +#define NV_RM_ASSERT_HW_UNIT_MSENC (0x0c) +#define NV_RM_ASSERT_HW_UNIT_NVENC0 NV_RM_ASSERT_HW_UNIT_MSENC +#define NV_RM_ASSERT_HW_UNIT_NVENC1 (0x0d) +#define NV_RM_ASSERT_HW_UNIT_HOST (0x0e) +#define NV_RM_ASSERT_HW_UNIT_ROM (0x0f) +#define NV_RM_ASSERT_HW_UNIT_INSTMEM (0x10) +#define NV_RM_ASSERT_HW_UNIT_DISP (0x11) +#define NV_RM_ASSERT_HW_UNIT_NVENC2 (0x12) +#define NV_RM_ASSERT_HW_UNIT_NVDEC1 (0x13) +#define NV_RM_ASSERT_HW_UNIT_NVDEC2 (0x14) +#define NV_RM_ASSERT_HW_UNIT_NVDEC3 (0x15) +#define NV_RM_ASSERT_HW_UNIT_NVDEC4 (0x16) +#define NV_RM_ASSERT_HW_UNIT_NVDEC5 (0x17) +#define NV_RM_ASSERT_HW_UNIT_NVDEC6 (0x18) +#define NV_RM_ASSERT_HW_UNIT_NVDEC7 (0x19) +#define NV_RM_ASSERT_HW_UNIT_ALLENGINES (0xff) +// SW Module which generated the error +#define NV_RM_ASSERT_SW_MODULE 15:8 + +// This is a specific error number which we wish to follow regardless of builds +// We want to use this for backend processing +// This is also a compromise. Ideally, each event would have a unique id but +// instead of doing this we use EIP which is unique per load. If we subtracted off +// the Module Load Address then it would be unique per build, Using EIP allows us +// to use the debugger to lookup the source code that corresponds to the event. +#define NV_RM_ASSERT_LEVEL_TAG 30:16 +// Host Errors +#define NV_RM_ASSERT_LEVEL_TAG_BAR1_PAGE_FAULT (0x0001) +#define NV_RM_ASSERT_LEVEL_TAG_IFB_PAGE_FAULT (0x0002) +#define NV_RM_ASSERT_LEVEL_TAG_PIO_ERROR (0x0003) +#define NV_RM_ASSERT_LEVEL_TAG_CHSW_SAVE_INVALID (0x0004) +#define NV_RM_ASSERT_LEVEL_TAG_CHSW_ERROR (0x0005) +#define NV_RM_ASSERT_LEVEL_TAG_FBIRD_TIMEOUT (0x0006) +#define NV_RM_ASSERT_LEVEL_TAG_CPUQ_FBIBUSY_TIMEOUT (0x0007) +#define NV_RM_ASSERT_LEVEL_TAG_CHSW_FSM_TIMEOUT (0x0008) +#define NV_RM_ASSERT_LEVEL_TAG_FB_FLUSH_TIMEOUT (0x0009) +#define NV_RM_ASSERT_LEVEL_TAG_P2PSTATE_TIMEOUT (0x000a) +#define NV_RM_ASSERT_LEVEL_TAG_VBIOS_CHECKSUM (0x000b) +#define NV_RM_ASSERT_LEVEL_TAG_DISP_SYNC (0x000c) + +// What is the generating Source -- GPU or SW +#define NV_RM_ASSERT_LEVEL_SOURCE 31:31 +#define NV_RM_ASSERT_LEVEL_SOURCE_SW 0x00000000 +#define NV_RM_ASSERT_LEVEL_SOURCE_HW 0x00000001 + + +// RM_ASSERT + DBG_BREAKPOINT info +typedef struct +{ + RmRCCommonAssert_RECORD commonAssert; + NvU32 level; +} RmRC2SwRmAssert3_RECORD; +typedef RmRC2SwRmAssert3_RECORD *PRmRC2SwRmAssert3_RECORD; + +// RM JOURNAL BUG CHECK +typedef struct +{ + RmRCCommonJournal_RECORD common; + NvU32 bugCheckCode; +} RmJournalBugcheck_RECORD, *PRmJournalBugcheck_RECORD; + +typedef struct +{ + NVCD_RECORD Header; + NvS32 GpuTemp; + NvS32 LocTemp; +} RmRC2TempReading_RECORD; +typedef RmRC2TempReading_RECORD *PRmRC2TempReading_RECORD; + +typedef enum { + MEMORY_BAR0 = 1, + MEMORY_FB, + MEMORY_INSTANCE, + MEMORY_PCI, +} RMCD_BAD_READ_SPACE; + +typedef struct +{ + RmRCCommonJournal_RECORD common; + NvU32 MemorySpace; // Which Memory Space + NvU32 Offset; // Offset in Memory Space + NvU32 Mask; // Mask used to detect bad read + NvU32 Value; // Value Return + NvU32 Reason; // Potential Reason why this might have happened +} RmRC2BadRead2_RECORD; + +typedef RmRC2BadRead2_RECORD *PRmRC2BadRead2_RECORD; + +typedef struct +{ + RmRCCommonJournal_RECORD common; + NvU32 hostEngTag; + NvU32 exceptType; + NvU32 exceptLevel; +} RmRCRecovery_RECORD; + +typedef RmRCRecovery_RECORD *PRmRCRecovery_RECORD; + +typedef struct +{ + RmRCCommonJournal_RECORD common; +} RmPrbInfo_RECORD_V2, *PRmPrbInfo_RECORD_V2; + +// Counters per type of RC Error. WIll only keep first n (10) types. +#define MAX_RC_ERROR_COUNTER 10 +#define RC_ERROR_COUNTER_OTHER_INDEX MAX_RC_ERROR_COUNTER-1 +#define RC_ERROR_COUNTER_TYPE_INVALID ((NvU32)(~0)) +#define RC_ERROR_COUNTER_OTHER_TYPE 1024 + +typedef struct +{ + NvU32 rcFaultType; + NvU32 rcErrorSrc; + NvU64 mmuFaultVA; + NvU32 mmuAccessType; +} rcExtraMMUInfo; + +typedef struct +{ + NvU32 rcGRErrType; + NvU32 rcGRExcptnSubTyp; +} rcExtraGRInfo; + +typedef struct +{ + NvU32 rcPBDMAID; + NvU64 rcPBDMAErrFlag; +} rcExtraPBDMAInfo; + +/* +* Union for storing extra data values for each kind of RC Error +* +* MMU +* ===== +* rcFaultType +* rcErrorSrc +* +* GR +* ======= +* rcGRErrType +* rcGRExcptnSubTyp +* +* PBDMA +* ========= +* rcPBDMAID +* rcPBDMAErrFlag +*/ + +typedef union +{ + rcExtraMMUInfo rcMMUData; + rcExtraGRInfo rcGRData; + rcExtraPBDMAInfo rcPBDMAData; +} rcExtraInfo; + +typedef struct +{ + NvU32 rcErrorType; + NvU32 rcErrorCount; + NvU32 rcLastCHID; + NvU64 rcLastTime; + rcExtraInfo rcExtrInfo; +} rcErrorCounterEntry; + +typedef struct +{ + NvU32 powerEvent; // The name of the point we are tracing + // Such as NVRM_OCA_PWR_EVENT_SET_POWER_ENTRY + NvU32 powerState; + NvU32 fastBootPowerState; // Tracking fast boot shutdown/hibernate states +} RmPowerState_RECORD, *PRmPowerState_RECORD; + +#define MAX_RCDB_RCDIAG_ENTRIES 200 +typedef struct +{ + NvU32 offset; + NvU32 tag; + NvU32 value; + NvU32 attribute; +} RmRcDiagRecordEntry; + +#define RCDB_RCDIAG_DEFAULT_OWNER 0 +typedef struct +{ + NvU16 idx; + NvU32 timeStamp; // time in seconds since 1/1/1970 + NvU16 type; + NvU32 flags; + NvU16 count; + NvU32 owner; // a handle indicating the ownership + NvU32 processId; // process Id of the originating process. + RmRcDiagRecordEntry data[MAX_RCDB_RCDIAG_ENTRIES]; +} RmRcDiag_RECORD, *PRmRcDiag_RECORD; + +#define MAX_RCDB_RCDIAG_WRAP_BUFF 32 +#define INVALID_RCDB_RCDIAG_INDEX 0xffffffff + +#define MAX_RCDB_NOCAT_WRAP_BUFF 100 +#define INVALID_RCDB_NOCAT_ID 0xffffffff + +#endif // RMCD_H diff --git a/userspace/sdks/nv570/inc/rs_access.h b/userspace/sdks/nv570/inc/rs_access.h new file mode 100644 index 0000000..7020677 --- /dev/null +++ b/userspace/sdks/nv570/inc/rs_access.h @@ -0,0 +1,273 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: rs_access.finn +// + + + + +#include "nvtypes.h" +#include "nvmisc.h" + + +/****************************************************************************/ +/* Access right definitions */ +/****************************************************************************/ + +// +// The meaning of each access right is documented in +// resman/docs/rmapi/resource_server/rm_capabilities.adoc +// +// RS_ACCESS_COUNT is the number of access rights that have been defined +// and are in use. All integers in the range [0, RS_ACCESS_COUNT) should +// represent valid access rights. +// +// When adding a new access right, don't forget to update +// 1) The descriptions in the resman/docs/rmapi/resource_server/rm_capabilities.adoc +// 2) RS_ACCESS_COUNT, defined below +// 3) The declaration of g_rsAccessMetadata in rs_access_rights.c +// 4) The list of access rights in drivers/common/chip-config/Chipcontrols.pm +// 5) Any relevant access right callbacks +// + +#define RS_ACCESS_DUP_OBJECT 0U +#define RS_ACCESS_NICE 1U +#define RS_ACCESS_DEBUG 2U +#define RS_ACCESS_PERFMON 3U +#define RS_ACCESS_COUNT 4U + + +/****************************************************************************/ +/* Access right data structures */ +/****************************************************************************/ + +/*! + * @brief A type that can be used to represent any access right. + */ +typedef NvU16 RsAccessRight; + +/*! + * @brief An internal type used to represent one limb in an access right mask. + */ +typedef NvU32 RsAccessLimb; +#define SDK_RS_ACCESS_LIMB_BITS 32 + +/*! + * @brief The number of limbs in the RS_ACCESS_MASK struct. + */ +#define SDK_RS_ACCESS_MAX_LIMBS 1 + +/*! + * @brief The maximum number of possible access rights supported by the + * current data structure definition. + * + * You probably want RS_ACCESS_COUNT instead, which is the number of actual + * access rights defined. + */ +#define SDK_RS_ACCESS_MAX_COUNT (0x20) /* finn: Evaluated from "(SDK_RS_ACCESS_LIMB_BITS * SDK_RS_ACCESS_MAX_LIMBS)" */ + +/** + * @brief A struct representing a set of access rights. + * + * Note that the values of bit positions larger than RS_ACCESS_COUNT is + * undefined, and should not be assumed to be 0 (see RS_ACCESS_MASK_FILL). + */ +typedef struct RS_ACCESS_MASK { + RsAccessLimb limbs[SDK_RS_ACCESS_MAX_LIMBS]; +} RS_ACCESS_MASK; + +/** + * @brief A struct representing auxiliary information about each access right. + */ +typedef struct RS_ACCESS_INFO { + NvU32 flags; +} RS_ACCESS_INFO; + + +/****************************************************************************/ +/* Access right macros */ +/****************************************************************************/ + +#define SDK_RS_ACCESS_LIMB_INDEX(index) ((index) / SDK_RS_ACCESS_LIMB_BITS) +#define SDK_RS_ACCESS_LIMB_POS(index) ((index) % SDK_RS_ACCESS_LIMB_BITS) + +#define SDK_RS_ACCESS_LIMB_ELT(pAccessMask, index) \ + ((pAccessMask)->limbs[SDK_RS_ACCESS_LIMB_INDEX(index)]) +#define SDK_RS_ACCESS_OFFSET_MASK(index) \ + NVBIT_TYPE(SDK_RS_ACCESS_LIMB_POS(index), RsAccessLimb) + +/*! + * @brief Checks that accessRight represents a valid access right. + * + * The valid range of access rights is [0, RS_ACCESS_COUNT). + * + * @param[in] accessRight The access right value to check + * + * @return true if accessRight is valid + * @return false otherwise + */ +#define RS_ACCESS_BOUNDS_CHECK(accessRight) \ + (accessRight < RS_ACCESS_COUNT) + +/*! + * @brief Test whether an access right is present in a set + * + * @param[in] pAccessMask The set of access rights to read + * @param[in] index The access right to examine + * + * @return NV_TRUE if the access right specified by index was present in the set, + * and NV_FALSE otherwise + */ +#define RS_ACCESS_MASK_TEST(pAccessMask, index) \ + (RS_ACCESS_BOUNDS_CHECK(index) && \ + (SDK_RS_ACCESS_LIMB_ELT(pAccessMask, index) & SDK_RS_ACCESS_OFFSET_MASK(index)) != 0) + +/*! + * @brief Add an access right to a mask + * + * @param[in] pAccessMask The set of access rights to modify + * @param[in] index The access right to set + */ +#define RS_ACCESS_MASK_ADD(pAccessMask, index) \ + do \ + { \ + if (RS_ACCESS_BOUNDS_CHECK(index)) { \ + SDK_RS_ACCESS_LIMB_ELT(pAccessMask, index) |= SDK_RS_ACCESS_OFFSET_MASK(index); \ + } \ + } while (NV_FALSE) + +/*! + * @brief Remove an access right from a mask + * + * @param[in] pAccessMask The set of access rights to modify + * @param[in] index The access right to unset + */ +#define RS_ACCESS_MASK_REMOVE(pAccessMask, index) \ + do \ + { \ + if (RS_ACCESS_BOUNDS_CHECK(index)) { \ + SDK_RS_ACCESS_LIMB_ELT(pAccessMask, index) &= ~SDK_RS_ACCESS_OFFSET_MASK(index); \ + } \ + } while (NV_FALSE) + +/*! + * @brief Performs an in-place union between two access right masks + * + * @param[in,out] pMaskOut The access rights mask to be updated + * @param[in] pMaskIn The set of access rights to be added to pMaskOut + */ +#define RS_ACCESS_MASK_UNION(pMaskOut, pMaskIn) \ + do \ + { \ + NvLength limb; \ + for (limb = 0; limb < SDK_RS_ACCESS_MAX_LIMBS; limb++) \ + { \ + SDK_RS_ACCESS_LIMB_ELT(pMaskOut, limb) |= SDK_RS_ACCESS_LIMB_ELT(pMaskIn, limb); \ + } \ + } while (NV_FALSE) + +/*! + * @brief Performs an in-place subtract of one mask's rights from another + * + * @param[in,out] pMaskOut The access rights mask to be updated + * @param[in] pMaskIn The set of access rights to be removed from pMaskOut + */ +#define RS_ACCESS_MASK_SUBTRACT(pMaskOut, pMaskIn) \ + do \ + { \ + NvLength limb; \ + for (limb = 0; limb < SDK_RS_ACCESS_MAX_LIMBS; limb++) \ + { \ + SDK_RS_ACCESS_LIMB_ELT(pMaskOut, limb) &= ~SDK_RS_ACCESS_LIMB_ELT(pMaskIn, limb); \ + } \ + } while (NV_FALSE) + +/*! + * @brief Removes all rights from an access rights mask + * + * @param[in,out] pAccessMask The access rights mask to be updated + */ +#define RS_ACCESS_MASK_CLEAR(pAccessMask) \ + do \ + { \ + portMemSet(pAccessMask, 0, sizeof(*pAccessMask)); \ + } while (NV_FALSE) + +/*! + * @brief Adds all rights to an access rights mask + * + * @param[in,out] pAccessMask The access rights mask to be updated + */ +#define RS_ACCESS_MASK_FILL(pAccessMask) \ + do \ + { \ + portMemSet(pAccessMask, 0xff, sizeof(*pAccessMask)); \ + } while (NV_FALSE) + + +/****************************************************************************/ +/* Share definitions */ +/****************************************************************************/ + +// +// The usage of Share Policy and the meaning of each share type is documented in +// resman/docs/rmapi/resource_server/rm_capabilities.adoc +// +#define RS_SHARE_TYPE_NONE (0U) +#define RS_SHARE_TYPE_ALL (1U) +#define RS_SHARE_TYPE_OS_SECURITY_TOKEN (2U) +#define RS_SHARE_TYPE_CLIENT (3U) +#define RS_SHARE_TYPE_PID (4U) +#define RS_SHARE_TYPE_SMC_PARTITION (5U) +#define RS_SHARE_TYPE_GPU (6U) +#define RS_SHARE_TYPE_FM_CLIENT (7U) +// Must be last. Update when a new SHARE_TYPE is added +#define RS_SHARE_TYPE_MAX (8U) + + +// +// Use Revoke to remove an existing policy from the list. +// Allow is based on OR logic, Require is based on AND logic. +// To share a right, at least one Allow (non-Require) must match, and all Require must pass. +// If Compose is specified, policies will be added to the list. Otherwise, they will replace the list. +// +#define RS_SHARE_ACTION_FLAG_REVOKE NVBIT(0) +#define RS_SHARE_ACTION_FLAG_REQUIRE NVBIT(1) +#define RS_SHARE_ACTION_FLAG_COMPOSE NVBIT(2) + +/****************************************************************************/ +/* Share flag data structures */ +/****************************************************************************/ + +typedef struct RS_SHARE_POLICY { + NvU32 target; + RS_ACCESS_MASK accessMask; + NvU16 type; ///< RS_SHARE_TYPE_ + NvU8 action; ///< RS_SHARE_ACTION_ +} RS_SHARE_POLICY; diff --git a/userspace/sdks/nv570/nvalloc/common/inc/conf_compute/cc_keyrotation.h b/userspace/sdks/nv570/nvalloc/common/inc/conf_compute/cc_keyrotation.h new file mode 100644 index 0000000..473f294 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/conf_compute/cc_keyrotation.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef CC_KEYROTATION_H +#define CC_KEYROTATION_H + +// +// Default threshold value derived from SECURITY_POLICY_ATTACKER_ADVANTAGE_DEFAULT +// Minimum threshold defined based on minimum in confComputeSetKeyRotation. +// +#define KEY_ROTATION_MINIMUM_INTERNAL_THRESHOLD (134217727u) +#define KEY_ROTATION_DEFAULT_INTERNAL_THRESHOLD (24296003999ull) + +#endif // CC_KEYROTATION_H diff --git a/userspace/sdks/nv570/nvalloc/common/inc/conf_compute/cc_keystore.h b/userspace/sdks/nv570/nvalloc/common/inc/conf_compute/cc_keystore.h new file mode 100644 index 0000000..c629050 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/conf_compute/cc_keystore.h @@ -0,0 +1,487 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef CC_KEYSTORE_H +#define CC_KEYSTORE_H + +// +// Keys are typically grouped in two's so that the first key is used for CPU-to-GPU encryption +// and the second key is used for GPU-to-CPU encryption. +// + +// Keyspace identifiers. +enum +{ + CC_KEYSPACE_GSP, + CC_KEYSPACE_SEC2, + CC_KEYSPACE_LCE0, + CC_KEYSPACE_LCE1, + CC_KEYSPACE_LCE2, + CC_KEYSPACE_LCE3, + CC_KEYSPACE_LCE4, + CC_KEYSPACE_LCE5, + CC_KEYSPACE_LCE6, + CC_KEYSPACE_LCE7, + CC_KEYSPACE_LCE10, + CC_KEYSPACE_LCE11, + CC_KEYSPACE_LCE12, + CC_KEYSPACE_LCE13, + CC_KEYSPACE_LCE14, + CC_KEYSPACE_LCE15, + CC_KEYSPACE_LCE16, + CC_KEYSPACE_LCE17, + CC_KEYSPACE_SIZE // This is always the last element. +}; + +#define CC_KEYSPACE_SIZE_GH100 (CC_KEYSPACE_LCE7 + 1) + +enum +{ + CC_LKEYID_CPU_GSP_LOCKED_RPC, + CC_LKEYID_GSP_CPU_LOCKED_RPC, + CC_LKEYID_CPU_GSP_DMA, + CC_LKEYID_GSP_CPU_DMA, + CC_LKEYID_CPU_GSP_RESERVED1, + CC_LKEYID_GSP_CPU_REPLAYABLE_FAULT, + CC_LKEYID_CPU_GSP_RESERVED2, + CC_LKEYID_GSP_CPU_NON_REPLAYABLE_FAULT, + CC_LKEYID_SEC2_GSP_LOCKED_RPC, + CC_LKEYID_GSP_SEC2_LOCKED_RPC, + CC_LKEYID_CPU_GSP_NVLE_P2P_WRAPPING, + CC_LKEYID_GSP_CPU_RESERVED_1, + CC_KEYSPACE_GSP_SIZE // This is always the last element. +}; +// The fault buffers only support GPU-to-CPU encryption, so the CPU-to-GPU encryption slot +// is left reserved. + +#define CC_LKEYID_GSP_CPU_LOCKED_RPC_STR "gsp_cpu_locked_rpc" +#define CC_LKEYID_CPU_GSP_LOCKED_RPC_STR "cpu_gsp_locked_rpc" +#define CC_LKEYID_GSP_CPU_DMA_STR "gsp_cpu_dma" +#define CC_LKEYID_CPU_GSP_DMA_STR "cpu_gsp_dma" +#define CC_LKEYID_GSP_CPU_REPLAYABLE_FAULT_STR "gsp_cpu_replayable_fault" +#define CC_LKEYID_GSP_CPU_NON_REPLAYABLE_FAULT_STR "gsp_cpu_non_replayable_fault" +#define CC_LKEYID_CPU_GSP_NVLE_P2P_WRAPPING_STR "cpu_gsp_nvle_p2p_wrapping" + +enum +{ + CC_LKEYID_CPU_SEC2_DATA_USER, + CC_LKEYID_CPU_SEC2_HMAC_USER, + CC_LKEYID_CPU_SEC2_DATA_KERN, + CC_LKEYID_CPU_SEC2_HMAC_KERN, + CC_LKEYID_CPU_SEC2_DATA_SCRUBBER, + CC_LKEYID_CPU_SEC2_HMAC_SCRUBBER, + CC_KEYSPACE_SEC2_SIZE // This is always the last element. +}; + +#define CC_LKEYID_CPU_SEC2_DATA_USER_STR "cpu_sec2_data_user" +#define CC_LKEYID_CPU_SEC2_HMAC_USER_STR "cpu_sec2_hmac_user" +#define CC_LKEYID_CPU_SEC2_DATA_KERN_STR "cpu_sec2_data_kernel" +#define CC_LKEYID_CPU_SEC2_HMAC_KERN_STR "cpu_sec2_hmac_kernel" +#define CC_LKEYID_CPU_SEC2_DATA_SCRUBBER_STR "cpu_sec2_data_scrubber" +#define CC_LKEYID_CPU_SEC2_HMAC_SCRUBBER_STR "cpu_sec2_hmac_scrubber" + +enum +{ + CC_LKEYID_LCE_H2D_USER, + CC_LKEYID_LCE_D2H_USER, + CC_LKEYID_LCE_H2D_KERN, + CC_LKEYID_LCE_D2H_KERN, + CC_LKEYID_LCE_H2D_P2P, + CC_LKEYID_LCE_D2H_P2P, + CC_KEYSPACE_LCE_SIZE // This is always the last element. +}; + + +#define CC_KEYSPACE_TOTAL_SIZE (CC_KEYSPACE_GSP_SIZE + CC_KEYSPACE_SEC2_SIZE + (16 * CC_KEYSPACE_LCE_SIZE)) +#define CC_LKEYID_LCE0_H2D_USER_STR "Lce00_h2d_user" +#define CC_LKEYID_LCE0_D2H_USER_STR "Lce00_d2h_user" +#define CC_LKEYID_LCE0_H2D_KERN_STR "Lce00_h2d_kernel" +#define CC_LKEYID_LCE0_D2H_KERN_STR "Lce00_d2h_kernel" +#define CC_LKEYID_LCE0_H2D_P2P_STR "Lce00_h2d_p2p" +#define CC_LKEYID_LCE0_D2H_P2P_STR "Lce00_d2h_p2p" + +#define CC_LKEYID_LCE1_H2D_USER_STR "Lce01_h2d_user" +#define CC_LKEYID_LCE1_D2H_USER_STR "Lce01_d2h_user" +#define CC_LKEYID_LCE1_H2D_KERN_STR "Lce01_h2d_kernel" +#define CC_LKEYID_LCE1_D2H_KERN_STR "Lce01_d2h_kernel" +#define CC_LKEYID_LCE1_H2D_P2P_STR "Lce01_h2d_p2p" +#define CC_LKEYID_LCE1_D2H_P2P_STR "Lce01_d2h_p2p" + +#define CC_LKEYID_LCE2_H2D_USER_STR "Lce02_h2d_user" +#define CC_LKEYID_LCE2_D2H_USER_STR "Lce02_d2h_user" +#define CC_LKEYID_LCE2_H2D_KERN_STR "Lce02_h2d_kernel" +#define CC_LKEYID_LCE2_D2H_KERN_STR "Lce02_d2h_kernel" +#define CC_LKEYID_LCE2_H2D_P2P_STR "Lce02_h2d_p2p" +#define CC_LKEYID_LCE2_D2H_P2P_STR "Lce02_d2h_p2p" + +#define CC_LKEYID_LCE3_H2D_USER_STR "Lce03_h2d_user" +#define CC_LKEYID_LCE3_D2H_USER_STR "Lce03_d2h_user" +#define CC_LKEYID_LCE3_H2D_KERN_STR "Lce03_h2d_kernel" +#define CC_LKEYID_LCE3_D2H_KERN_STR "Lce03_d2h_kernel" +#define CC_LKEYID_LCE3_H2D_P2P_STR "Lce03_h2d_p2p" +#define CC_LKEYID_LCE3_D2H_P2P_STR "Lce03_d2h_p2p" + +#define CC_LKEYID_LCE4_H2D_USER_STR "Lce04_h2d_user" +#define CC_LKEYID_LCE4_D2H_USER_STR "Lce04_d2h_user" +#define CC_LKEYID_LCE4_H2D_KERN_STR "Lce04_h2d_kernel" +#define CC_LKEYID_LCE4_D2H_KERN_STR "Lce04_d2h_kernel" +#define CC_LKEYID_LCE4_H2D_P2P_STR "Lce04_h2d_p2p" +#define CC_LKEYID_LCE4_D2H_P2P_STR "Lce04_d2h_p2p" + +#define CC_LKEYID_LCE5_H2D_USER_STR "Lce05_h2d_user" +#define CC_LKEYID_LCE5_D2H_USER_STR "Lce05_d2h_user" +#define CC_LKEYID_LCE5_H2D_KERN_STR "Lce05_h2d_kernel" +#define CC_LKEYID_LCE5_D2H_KERN_STR "Lce05_d2h_kernel" +#define CC_LKEYID_LCE5_H2D_P2P_STR "Lce05_h2d_p2p" +#define CC_LKEYID_LCE5_D2H_P2P_STR "Lce05_d2h_p2p" + +#define CC_LKEYID_LCE6_H2D_USER_STR "Lce06_h2d_user" +#define CC_LKEYID_LCE6_D2H_USER_STR "Lce06_d2h_user" +#define CC_LKEYID_LCE6_H2D_KERN_STR "Lce06_h2d_kernel" +#define CC_LKEYID_LCE6_D2H_KERN_STR "Lce06_d2h_kernel" +#define CC_LKEYID_LCE6_H2D_P2P_STR "Lce06_h2d_p2p" +#define CC_LKEYID_LCE6_D2H_P2P_STR "Lce06_d2h_p2p" + +#define CC_LKEYID_LCE7_H2D_USER_STR "Lce07_h2d_user" +#define CC_LKEYID_LCE7_D2H_USER_STR "Lce07_d2h_user" +#define CC_LKEYID_LCE7_H2D_KERN_STR "Lce07_h2d_kernel" +#define CC_LKEYID_LCE7_D2H_KERN_STR "Lce07_d2h_kernel" +#define CC_LKEYID_LCE7_H2D_P2P_STR "Lce07_h2d_p2p" +#define CC_LKEYID_LCE7_D2H_P2P_STR "Lce07_d2h_p2p" + +#define CC_LKEYID_LCE10_H2D_USER_STR "Lce10_h2d_user" +#define CC_LKEYID_LCE10_D2H_USER_STR "Lce10_d2h_user" +#define CC_LKEYID_LCE10_H2D_KERN_STR "Lce10_h2d_kernel" +#define CC_LKEYID_LCE10_D2H_KERN_STR "Lce10_d2h_kernel" +#define CC_LKEYID_LCE10_H2D_P2P_STR "Lce10_h2d_p2p" +#define CC_LKEYID_LCE10_D2H_P2P_STR "Lce10_d2h_p2p" + +#define CC_LKEYID_LCE11_H2D_USER_STR "Lce11_h2d_user" +#define CC_LKEYID_LCE11_D2H_USER_STR "Lce11_d2h_user" +#define CC_LKEYID_LCE11_H2D_KERN_STR "Lce11_h2d_kernel" +#define CC_LKEYID_LCE11_D2H_KERN_STR "Lce11_d2h_kernel" +#define CC_LKEYID_LCE11_H2D_P2P_STR "Lce11_h2d_p2p" +#define CC_LKEYID_LCE11_D2H_P2P_STR "Lce11_d2h_p2p" + +#define CC_LKEYID_LCE12_H2D_USER_STR "Lce12_h2d_user" +#define CC_LKEYID_LCE12_D2H_USER_STR "Lce12_d2h_user" +#define CC_LKEYID_LCE12_H2D_KERN_STR "Lce12_h2d_kernel" +#define CC_LKEYID_LCE12_D2H_KERN_STR "Lce12_d2h_kernel" +#define CC_LKEYID_LCE12_H2D_P2P_STR "Lce12_h2d_p2p" +#define CC_LKEYID_LCE12_D2H_P2P_STR "Lce12_d2h_p2p" + +#define CC_LKEYID_LCE13_H2D_USER_STR "Lce13_h2d_user" +#define CC_LKEYID_LCE13_D2H_USER_STR "Lce13_d2h_user" +#define CC_LKEYID_LCE13_H2D_KERN_STR "Lce13_h2d_kernel" +#define CC_LKEYID_LCE13_D2H_KERN_STR "Lce13_d2h_kernel" +#define CC_LKEYID_LCE13_H2D_P2P_STR "Lce13_h2d_p2p" +#define CC_LKEYID_LCE13_D2H_P2P_STR "Lce13_d2h_p2p" + +#define CC_LKEYID_LCE14_H2D_USER_STR "Lce14_h2d_user" +#define CC_LKEYID_LCE14_D2H_USER_STR "Lce14_d2h_user" +#define CC_LKEYID_LCE14_H2D_KERN_STR "Lce14_h2d_kernel" +#define CC_LKEYID_LCE14_D2H_KERN_STR "Lce14_d2h_kernel" +#define CC_LKEYID_LCE14_H2D_P2P_STR "Lce14_h2d_p2p" +#define CC_LKEYID_LCE14_D2H_P2P_STR "Lce14_d2h_p2p" + +#define CC_LKEYID_LCE15_H2D_USER_STR "Lce15_h2d_user" +#define CC_LKEYID_LCE15_D2H_USER_STR "Lce15_d2h_user" +#define CC_LKEYID_LCE15_H2D_KERN_STR "Lce15_h2d_kernel" +#define CC_LKEYID_LCE15_D2H_KERN_STR "Lce15_d2h_kernel" +#define CC_LKEYID_LCE15_H2D_P2P_STR "Lce15_h2d_p2p" +#define CC_LKEYID_LCE15_D2H_P2P_STR "Lce15_d2h_p2p" + +#define CC_LKEYID_LCE16_H2D_USER_STR "Lce16_h2d_user" +#define CC_LKEYID_LCE16_D2H_USER_STR "Lce16_d2h_user" +#define CC_LKEYID_LCE16_H2D_KERN_STR "Lce16_h2d_kernel" +#define CC_LKEYID_LCE16_D2H_KERN_STR "Lce16_d2h_kernel" +#define CC_LKEYID_LCE16_H2D_P2P_STR "Lce16_h2d_p2p" +#define CC_LKEYID_LCE16_D2H_P2P_STR "Lce16_d2h_p2p" + +#define CC_LKEYID_LCE17_H2D_USER_STR "Lce17_h2d_user" +#define CC_LKEYID_LCE17_D2H_USER_STR "Lce17_d2h_user" +#define CC_LKEYID_LCE17_H2D_KERN_STR "Lce17_h2d_kernel" +#define CC_LKEYID_LCE17_D2H_KERN_STR "Lce17_d2h_kernel" +#define CC_LKEYID_LCE17_H2D_P2P_STR "Lce17_h2d_p2p" +#define CC_LKEYID_LCE17_D2H_P2P_STR "Lce17_d2h_p2p" + +// Generate a global key ID from a keyspace (a) and local key ID (b). +#define CC_GKEYID_GEN(a, b) (NvU32)(((a) << 16) | (b)) + +// Get the keyspace component from a global key ID. +#define CC_GKEYID_GET_KEYSPACE(a) (NvU16)((a) >> 16) + +// Get the local key ID from a global key ID. +#define CC_GKEYID_GET_LKEYID(a) (NvU16)((a) & 0xffff) + +// Decrement/increment the local key ID portion of a global key ID. +#define CC_GKEYID_DEC_LKEYID(a) CC_GKEYID_GEN(CC_GKEYID_GET_KEYSPACE((a)), CC_GKEYID_GET_LKEYID((a)) - 1) +#define CC_GKEYID_INC_LKEYID(a) CC_GKEYID_GEN(CC_GKEYID_GET_KEYSPACE((a)), CC_GKEYID_GET_LKEYID((a)) + 1) + +// Get the unqiue string from a global key ID. +#define CC_GKEYID_GET_STR(a) \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_GSP) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_GSP_CPU_LOCKED_RPC) ? \ + CC_LKEYID_GSP_CPU_LOCKED_RPC_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_CPU_GSP_LOCKED_RPC) ? \ + CC_LKEYID_CPU_GSP_LOCKED_RPC_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_GSP_CPU_DMA) ? \ + CC_LKEYID_GSP_CPU_DMA_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_CPU_GSP_DMA) ? \ + CC_LKEYID_CPU_GSP_DMA_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_GSP_CPU_REPLAYABLE_FAULT) ? \ + CC_LKEYID_GSP_CPU_REPLAYABLE_FAULT_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_GSP_CPU_NON_REPLAYABLE_FAULT) ? \ + CC_LKEYID_GSP_CPU_NON_REPLAYABLE_FAULT_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_CPU_GSP_NVLE_P2P_WRAPPING) ? \ + CC_LKEYID_CPU_GSP_NVLE_P2P_WRAPPING_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_SEC2) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_CPU_SEC2_DATA_USER) ? \ + CC_LKEYID_CPU_SEC2_DATA_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_CPU_SEC2_HMAC_USER) ? \ + CC_LKEYID_CPU_SEC2_HMAC_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_CPU_SEC2_DATA_KERN) ? \ + CC_LKEYID_CPU_SEC2_DATA_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_CPU_SEC2_HMAC_KERN) ? \ + CC_LKEYID_CPU_SEC2_HMAC_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_CPU_SEC2_DATA_SCRUBBER) ? \ + CC_LKEYID_CPU_SEC2_DATA_SCRUBBER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_CPU_SEC2_HMAC_SCRUBBER) ? \ + CC_LKEYID_CPU_SEC2_HMAC_SCRUBBER_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE0) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE0_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE0_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE0_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE0_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE0_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE0_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE1) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE1_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE1_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE1_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE1_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE1_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE1_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE2) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE2_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE2_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE2_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE2_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE2_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE2_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE3) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE3_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE3_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE3_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE3_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE3_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE3_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE4) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE4_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE4_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE4_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE4_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE4_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE4_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE5) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE5_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE5_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE5_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE5_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE5_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE5_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE6) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE6_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE6_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE6_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE6_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE6_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE6_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE7) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE7_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE7_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE7_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE7_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE7_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE7_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE10) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE10_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE10_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE10_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE10_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE10_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE10_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE11) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE11_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE11_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE11_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE11_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE11_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE11_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE12) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE12_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE12_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE12_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE12_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE12_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE12_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE13) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE13_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE13_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE13_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE13_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE13_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE13_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE14) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE14_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE14_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE14_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE14_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE14_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE14_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE15) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE15_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE15_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE15_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE15_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE15_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE15_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE16) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE16_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE16_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE16_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE16_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE16_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE16_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE17) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE17_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE17_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE17_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE17_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE17_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE17_D2H_P2P_STR : NULL : NULL + +#define CC_EXPORT_MASTER_KEY_SIZE_BYTES 32 + +#define CC_KEYID_PERCHANNEL_INITIAL_KEYSEED "ce_channel" +#define CC_KEYID_PERCHANNEL_UPDATE_KEYSEED "update_keyseeed" +#define CC_KEYID_PERCHANNEL_CPU_GPU_UPDATE_KEY "update_key1" +#define CC_KEYID_PERCHANNEL_GPU_CPU_UPDATE_KEY "update_key2" + +#endif // CC_KEYSTORE_H diff --git a/userspace/sdks/nv570/nvalloc/common/inc/dev_ctrl_defines.h b/userspace/sdks/nv570/nvalloc/common/inc/dev_ctrl_defines.h new file mode 100644 index 0000000..fa06bcf --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/dev_ctrl_defines.h @@ -0,0 +1,87 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @brief Defines for simplifying SW accesses to the dev_ctrl interrupt tree. + * These are generic defines ued in addition to architecure-specific + * defines in dev_vm_addendum.h + * + */ + +// +// Notes on the terms used below: +// Subtree: The HW tree is a 64-way tree that consists of 2 TOP level interrupt +// registers, 32 bits each. Each of these 64 is referred to as a subtree. +// Leaf: Each of these 64 subtrees are associated with a pair of LEAF registers +// giving us a total of 128 LEAF registers. +// GPU vector: The 128 LEAF registers give us a total of (128*32) GPU vectors +// giving us a total of 4096 GPU vectors +// + +// +// Given a subtree index, the below macros give us the index of the TOP level +// register and the bit within the TOP level register to program for that +// subtree. +// +#define NV_CTRL_INTR_SUBTREE_TO_TOP_IDX(i) (((NvU32)(i)) / 32) +#define NV_CTRL_INTR_SUBTREE_TO_TOP_BIT(i) (((NvU32)(i)) % 32) + +// +// Given a subtree index, the below macros give us the two LEAF register indices +// that correspond to that subtree. +// +#define NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(i) (((NvU32)(i)) * 2) +#define NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(i) ((((NvU32)(i)) * 2) + 1) + +#define NV_CTRL_INTR_LEAF_IDX_TO_SUBTREE(i) (((NvU32)(i)) / 2) + +// +// Given a LEAF register index, the below macros give us the range of GPU +// interrupt vectors that correspond to those leafs. +// +#define NV_CTRL_INTR_LEAF_IDX_TO_GPU_VECTOR_START(i) (((NvU32)(i)) * 32) +#define NV_CTRL_INTR_LEAF_IDX_TO_GPU_VECTOR_END(i) ((((NvU32)(i)) * 32) + 31) + +// +// Given a GPU interrupt vector, the below macros give us the index of the +// LEAF register and the bit within the LEAF register to program for that +// GPU interrupt vector. +// +#define NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(i) (((NvU32)(i)) / 32) +#define NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(i) (((NvU32)(i)) % 32) + +// +// Given a GPU interrupt vector, the below macro gives us the subtree in which +// it belongs. +// +#define NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(i) \ + ((NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(i)) / 2) + +// First index of doorbell which is controlled by VF +#define NV_CTRL_INTR_GPU_DOORBELL_INDEX_VF_START 2048 + +// The max number of leaf registers we expect +#define NV_MAX_INTR_LEAVES 16 + +// In SW, this specifies an invalid interrupt vector +#define NV_INTR_VECTOR_INVALID (NV_U32_MAX) diff --git a/userspace/sdks/nv570/nvalloc/common/inc/flcnifcmn.h b/userspace/sdks/nv570/nvalloc/common/inc/flcnifcmn.h new file mode 100644 index 0000000..df4ba6c --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/flcnifcmn.h @@ -0,0 +1,141 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * flcn Command/Message Interfaces - Common + */ + +#ifndef FLCNIFCMN_H +#define FLCNIFCMN_H + +#include "nvtypes.h" +#include "flcnretval.h" + +/*! + * @ref NvU64_ALIGN32 , NvU64_ALIGN32_PACK, NvU64_ALIGN32_UNPACK + * TODO: Use NV types directly + */ +typedef NvU64_ALIGN32 RM_FLCN_U64; +typedef NvU64_ALIGN32 *PRM_FLCN_U64; + +#define RM_FLCN_U64_IS_ZERO NvU64_ALIGN32_IS_ZERO +#define RM_FLCN_U64_PACK NvU64_ALIGN32_PACK +#define RM_FLCN_U64_UNPACK NvU64_ALIGN32_UNPACK + +/*! + * @brief Header preceding each CMD/MSG exchanged through falcon's queues. + * + * @note Data package sent to falcon are referred as CMDs (commands). + * Data package sent by falcon are referred as MSGs (messages). + */ +typedef struct +{ + /*! + * Unit ID identifies falcon's task/unit receiving/issuing this message. + */ + NvU8 unitId; + /*! + * Total CMD/MSG size (including header). + */ + NvU8 size; + /*! + * Flags identifying state of CMD/MSG. + */ + NvU8 ctrlFlags; + /*! + * Sequence # ID to track each request sent to falcon (where applicable). + */ + NvU8 seqNumId; +} RM_FLCN_QUEUE_HDR, +*PRM_FLCN_QUEUE_HDR; + +/*! + * Convenience macro for determining the size of the falcon's queue header: + */ +#define RM_FLCN_QUEUE_HDR_SIZE sizeof(RM_FLCN_QUEUE_HDR) + +/*! + * Generic Falcon rewind unit ID. + */ +#define RM_FLCN_UNIT_ID_REWIND (0x00U) + +/*! + * Generic CMD structure to hold the header. + */ +typedef struct +{ + RM_FLCN_QUEUE_HDR hdr; + NvU32 cmd; +} RM_FLCN_CMD_GEN; + +/*! + * Generic MSG structure to hold the header. + */ +typedef struct +{ + RM_FLCN_QUEUE_HDR hdr; + NvU32 msg; +} RM_FLCN_MSG_GEN; + +/*! + * Convenience macros for determining the size of body for a command or message: + */ +#define RM_FLCN_CMD_BODY_SIZE(u,t) sizeof(RM_FLCN_##u##_CMD_##t) +#define RM_FLCN_MSG_BODY_SIZE(u,t) sizeof(RM_FLCN_##u##_MSG_##t) + +/*! + * Convenience macros for determining the size of a command or message: + */ +#define RM_FLCN_CMD_SIZE(u,t) \ + (RM_FLCN_QUEUE_HDR_SIZE + RM_FLCN_CMD_BODY_SIZE(u,t)) + +#define RM_FLCN_MSG_SIZE(u,t) \ + (RM_FLCN_QUEUE_HDR_SIZE + RM_FLCN_MSG_BODY_SIZE(u,t)) + +/*! + * Convenience macros for determining the type of a command or message + * (intended to be used symmetrically with the CMD and MSG _SIZE macros): + */ +#define RM_FLCN_CMD_TYPE(u,t) RM_FLCN_##u##_CMD_ID_##t +#define RM_FLCN_MSG_TYPE(u,t) RM_FLCN_##u##_MSG_ID_##t + +/*! + * @brief Falcons' queue header flags (@ref RM_FLCN_QUEUE_HDR::ctrlFlags). + * + * RM_FLCN_QUEUE_FLAGS_STATUS + * Set by command's sender to request back message confirming the completion of + * command's execution. In RM->FLCN communication response is required to free + * command related data tracked within RM (***_SEQ_INFO). + * + * RM_FLCN_QUEUE_HDR_FLAGS_EVENT + * Set by the falcon to distinguish messages sent to RM from command responses. + * + * RM_FLCN_QUEUE_HDR_FLAGS_UNIT_ACK + * Used internally within the falcon to track completed commands when updating + * get (tail) command queue pointers. + */ +#define RM_FLCN_QUEUE_HDR_FLAGS_STATUS NVBIT(0) +#define RM_FLCN_QUEUE_HDR_FLAGS_EVENT NVBIT(2) +#define RM_FLCN_QUEUE_HDR_FLAGS_UNIT_ACK NVBIT(5) + +#endif // FLCNIFCMN_H diff --git a/userspace/sdks/nv570/nvalloc/common/inc/flcnretval.h b/userspace/sdks/nv570/nvalloc/common/inc/flcnretval.h new file mode 100644 index 0000000..0e1efe5 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/flcnretval.h @@ -0,0 +1,305 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2008-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file flcnretval.h + * @brief Defines various status codes that are convenient to relay status + * information in functions. + */ + +#ifndef FLCNRETVAL_H +#define FLCNRETVAL_H + +#include "nvtypes.h" +/*! + * Defines a generic type that may be used to convey status information. This + * is very similar to the RM_STATUS type but smaller in width to save DMEM and + * stack space. + */ +typedef NvU8 FLCN_STATUS; + +#define FLCN_OK (0x00U) +#define FLCN_ERR_BINARY_NOT_STARTED (0xFEU) +#define FLCN_ERROR (0xFFU) + +#define FLCN_ERR_NOT_SUPPORTED (0x01U) +#define FLCN_ERR_INVALID_ARGUMENT (0x02U) +#define FLCN_ERR_ILLEGAL_OPERATION (0x03U) +#define FLCN_ERR_TIMEOUT (0x04U) +#define FLCN_ERR_NO_FREE_MEM (0x05U) +#define FLCN_ERR_HDCP_INVALID_SRM (0x06U) +#define FLCN_ERR_HDCP_RECV_REVOKED (0x07U) +#define FLCN_ERR_RPC_INVALID_INPUT (0x08U) +#define FLCN_ERR_DMA_SUSPENDED (0x09U) +#define FLCN_ERR_MUTEX_ACQUIRED (0x10U) +#define FLCN_ERR_MUTEX_ID_NOT_AVAILABLE (0x11U) +#define FLCN_ERR_OBJECT_NOT_FOUND (0x12U) +#define FLCN_ERR_MSGBOX_TIMEOUT (0x13U) +#define FLCN_ERR_INVALID_INDEX (0x14U) +#define FLCN_ERR_INVALID_FUNCTION (0x15U) +#define FLCN_ERR_INSUFFICIENT_PMB_PLM_PROTECTION (0x16U) +#define FLCN_ERR_DMA_NACK (0x17U) +#define FLCN_ERR_CHIP_NOT_SUPPORTED_FOR_PR (0x18U) +#define FLCN_ERR_BAR0_PRIV_READ_ERROR (0x19U) +#define FLCN_ERR_BAR0_PRIV_WRITE_ERROR (0x1AU) +#define FLCN_ERR_HDCP22_ABORT_AUTHENTICATION (0x1BU) +#define FLCN_ERR_DPU_IS_BUSY (0x1CU) +#define FLCN_ERR_DPU_TIMEOUT_FOR_HDCP_TYPE1_LOCK_REQUEST (0x1DU) +#define FLCN_ERR_HDCP_TYPE1_LOCK_FAILED (0x1EU) +#define FLCN_ERR_HDCP_TYPE1_LOCK_UNKNOWN (0x1FU) +#define FLCN_ERR_WAIT_FOR_BAR0_IDLE_FAILED (0x20U) +#define FLCN_ERR_CSB_PRIV_READ_ERROR (0x21U) +#define FLCN_ERR_CSB_PRIV_WRITE_ERROR (0x22U) +#define FLCN_ERR_DMA_UNEXPECTED_DMAIDX (0x23U) +#define FLCN_ERR_PRIV_SEC_VIOLATION (0x24U) +#define FLCN_ERR_INVALID_VERSION (0x25U) +#define FLCN_ERR_PR_SHARED_STRUCT_INIT_FAILED (0x26U) +#define FLCN_ERR_GPU_IN_DEBUG_MODE (0x27U) +#define FLCN_ERR_HPD_UNPLUG (0x28U) +#define FLCN_ERR_HDCP22_DELAY_ABORT_AUTHENTICATION (0x29U) +#define FLCN_ERR_SECUREBUS_REGISTER_READ_ERROR (0x2AU) +#define FLCN_ERR_SECUREBUS_REGISTER_WRITE_ERROR (0x2BU) +#define FLCN_ERR_HDCP22_FLUSH_TYPE_LOCK_ACTIVE (0x2CU) +#define FLCN_ERR_HDCP22_FLUSH_TYPE_IN_PROGRESS (0x2DU) +#define FLCN_ERR_FEATURE_NOT_ENABLED (0x2EU) +#define FLCN_ERR_OUT_OF_RANGE (0x2FU) + +// I2C Errors +#define FLCN_ERR_I2C_BUSY (0x30U) +#define FLCN_ERR_I2C_NACK_ADDRESS (0x31U) +#define FLCN_ERR_I2C_NACK_BYTE (0x32U) +#define FLCN_ERR_I2C_SIZE (0x33U) +#define FLCN_ERR_I2C_BUS_INVALID (0x34U) + +#define FLCN_ERR_INVALID_STATE (0x35U) +#define FLCN_ERR_RECURSION_LIMIT_EXCEEDED (0x36U) +#define FLCN_ERR_INVALID_CAST (0x37U) + +// AUX Errors +#define FLCN_ERR_AUX_ERROR (0x3AU) +#define FLCN_ERR_AUX_SEMA_ACQUIRED (0x3BU) +#define FLCN_ERR_AUX_SEMA_INVALID_RELEASE (0x3CU) +#define FLCN_ERR_AUX_DEFER_TIMEOUT (0x3DU) +#define FLCN_ERR_MORE_PROCESSING_REQUIRED (0x3EU) +#define FLCN_ERR_DMA_ALIGN (0x3FU) + +// Power-Device Errors +#define FLCN_ERR_PWR_DEVICE_TAMPERED (0x40U) + +#define FLCN_ERR_ITERATION_END (0x41U) + +// Perf change sequence Errors +#define FLCN_ERR_LOCK_NOT_AVAILABLE (0x42U) + +#define FLCN_ERR_STATE_RESET_NEEDED (0x43U) +#define FLCN_ERR_DMA_GENERIC (0x44U) +#define FLCN_ERR_LS_CHK_UCODE_REVOKED (0x45U) +#define FLCN_ERR_ACC_SEQ_MISMATCH (0x46U) +#define FLCN_ERR_SSP_STACK_CHECK_FAILED (0x47U) +#define FLCN_ERR_SE_TRNG_FAILED (0x48U) +#define FLCN_ERR_PROD_MODE_NOT_YET_SUPPORTED (0x49U) + +// SHA HW errors +#define FLCN_ERR_SHA_HW_CHECK_INT_STATUS (0x4AU) +#define FLCN_ERR_SHA_HW_SOFTRESET_REQUIRED (0x4BU) +#define FLCN_ERR_SHA_HW_SOFTRESET_FAILED (0x4CU) +#define FLCN_ERR_SHA_HW_BUSY (0x4DU) + +// +// Add new generic error codes here, do not changes values of exiting error codes, +// because that will affect other binaries and their signatures +// +#define FLCN_ERR_CTXSW_ERROR (0x4EU) +#define FLCN_ERR_SE_SNPKA_HW_CRYPTO_OPERATION_FAILED (0x4FU) + +// VPR SEC2 task errors +#define FLCN_ERR_VPR_APP_INVALID_REQUEST_END_ADDR (0x51U) +#define FLCN_ERR_VPR_APP_INVALID_REQUEST_START_ADDR (0x52U) +#define FLCN_ERR_VPR_APP_SCRUB_VERIF_FAILED (0x53U) +#define FLCN_ERR_VPR_APP_MEMLOCK_ALREADY_SET (0x54U) +#define FLCN_ERR_VPR_APP_INVALID_INDEX (0x55U) +#define FLCN_ERR_VPR_APP_UNEXPECTED_VPR_HANDOFF_FROM_SCRUBBER (0x56U) +#define FLCN_ERR_VPR_APP_CBC_RANGE_CLASH (0x57U) +#define FLCN_ERR_VPR_APP_NOT_SUPPORTED_BY_HW (0x58U) +#define FLCN_ERR_VPR_APP_NOT_SUPPORTED_BY_SW (0x59U) +#define FLCN_ERR_VPR_APP_DISPLAY_VERSION_NOT_SUPPORTED (0x5AU) +#define FLCN_ERR_VPR_APP_VPR_WPR_WRITE_FAILED (0x5BU) +#define FLCN_ERR_VPR_APP_NOTHING_TO_DO (0x5CU) +#define FLCN_ERR_VPR_APP_DISPLAY_NOT_PRESENT (0x5DU) +#define FLCN_ERR_VPR_APP_PREVIOUS_CMD_FAILED_AS_MAX_VPR_IS_0 (0x5EU) +#define FLCN_ERR_VPR_APP_PLM_PROTECTION_NOT_RAISED (0x5FU) +#define FLCN_ERR_VPR_APP_PLM_PROTECTION_ALREADY_RAISED (0x60U) +#define FLCN_ERR_VPR_APP_DISP_FALCON_IS_NOT_IN_LS_MODE (0x61U) +#define FLCN_ERR_VPR_APP_VPR_IS_ALREADY_ENABLED (0x62U) +#define FLCN_ERR_VPR_APP_UNEXPECTEDLY_RUNNING_ON_RISCV (0x63U) +#define FLCN_ERR_INVALID_SR_CONFIGURATION (0x64U) +#define FLCN_ERR_VPR_CMD_NOT_SUPPORTED (0x65U) + +// Clocks Errors +#define FLCN_ERR_CYCLE_DETECTED (0x70U) +#define FLCN_ERR_INVALID_PATH (0x71U) +#define FLCN_ERR_MISMATCHED_TARGET (0x72U) +#define FLCN_ERR_FREQ_NOT_SUPPORTED (0x73U) +#define FLCN_ERR_INVALID_SOURCE (0x74U) +#define FLCN_ERR_NOT_INITIALIZED (0x75U) +#define FLCN_ERR_CLOCK_NOT_SETTLED (0x76U) + +// HDCP2.2 Errors +#define FLCN_ERR_HDCP22_GETDKEY_FAILED (0x80U) +#define FLCN_ERR_HDCP22_H_PRIME (0x81U) +#define FLCN_ERR_HDCP22_CERT_RX (0x82U) +#define FLCN_ERR_HDCP22_PAIRING (0x83U) +#define FLCN_ERR_HDCP22_L_PRIME (0x84U) +#define FLCN_ERR_HDCP22_V_PRIME (0x85U) +#define FLCN_ERR_HDCP22_INVALID_RXIDLIST (0x86U) +#define FLCN_ERR_HDCP22_M_PRIME (0x87U) +#define FLCN_ERR_HDCP22_SEQ_ROLLOVER (0x88U) +#define FLCN_ERR_HDCP22_RSA_HW (0x89U) +#define FLCN_ERR_HDCP22_ECF_TIMESLOT_MISMATCH (0x90U) + +// LibCCC Errors +#define FLCN_ERR_INIT_CRYPTO_DEVICE_FAILED (0x91U) +#define FLCN_ERR_NVPKA_SELECT_ENGINE_FAILED (0x92U) +#define FLCN_ERR_NVPKA_ACQUIRE_MUTEX_FAILED (0x93U) +#define FLCN_ERR_NVPKA_MODULAR_EXP_LOCK_FAILED (0x94U) +#define FLCN_ERR_NVRNG_INIT_CRYPTO_DEVICE_FAILED (0x95U) +#define FLCN_ERR_NVRNG_SELECT_ENGINE_FAILED (0x96U) +#define FLCN_ERR_NVRNG_GENERATE_FAILED (0x97U) +#define FLCN_ERR_NVPKA_ECDSA_INIT_FAILED (0x98U) +#define FLCN_ERR_NVPKA_ECDSA_SIGN_FAILED (0x99U) +#define FLCN_ERR_NVPKA_GET_ECC_KEY_PAIR_FAILED (0x9AU) + +// Heavy Secure Errors +#define FLCN_ERR_HS_CHK_INVALID_INPUT (0xA0U) +#define FLCN_ERR_HS_CHK_CHIP_NOT_SUPPORTED (0xA1U) +#define FLCN_ERR_HS_CHK_UCODE_REVOKED (0xA2U) +#define FLCN_ERR_HS_CHK_NOT_IN_LSMODE (0xA3U) +#define FLCN_ERR_HS_CHK_INVALID_LS_PRIV_LEVEL (0xA4U) +#define FLCN_ERR_HS_CHK_INVALID_REGIONCFG (0xA5U) +#define FLCN_ERR_HS_CHK_PRIV_SEC_DISABLED_ON_PROD (0xA6U) +#define FLCN_ERR_HS_CHK_SW_FUSING_ALLOWED_ON_PROD (0xA7U) +#define FLCN_ERR_HS_CHK_INTERNAL_SKU_ON_PROD (0xA8U) +#define FLCN_ERR_HS_CHK_DEVID_OVERRIDE_ENABLED_ON_PROD (0xA9U) +#define FLCN_ERR_HS_CHK_INCONSISTENT_PROD_MODES (0xAAU) +#define FLCN_ERR_HS_CHK_HUB_ENCRPTION_DISABLED (0xABU) +#define FLCN_ERR_HS_PR_ILLEGAL_LASSAHS_STATE_AT_HS_ENTRY (0xACU) +#define FLCN_ERR_HS_PR_ILLEGAL_LASSAHS_STATE_AT_MPK_DECRYPT (0xADU) +#define FLCN_ERR_HS_PR_ILLEGAL_LASSAHS_STATE_AT_HS_EXIT (0xAEU) +#define FLCN_ERR_HS_PROD_MODE_NOT_YET_SUPPORTED (0xAFU) +#define FLCN_ERR_HS_DEV_VERSION_ON_PROD (0xB0U) +#define FLCN_ERR_HS_PR_LASSAHS_LS_SIG_GRP_MISMATCH (0xB1U) +#define FLCN_ERR_HS_PR_LASSAHS_LS_SIG_GRP_OVERLAYS_CNT (0xB2U) +#define FLCN_ERR_HS_PR_LASSAHS_LS_SIG_GRP_INVALID_VA (0xB3U) +#define FLCN_ERR_HS_MUTEX_ACQUIRE_FAILED (0xB4U) +#define FLCN_ERR_HS_MUTEX_RELEASE_FAILED (0xB5U) +#define FLCN_ERR_HS_PR_MPK_DEC_NEEDS_NEWER_ACR_UDE_SCRUBBER (0xB6U) +#define FLCN_ERR_HS_CHK_ENGID_MISMATCH (0xB7U) +#define FLCN_ERR_HS_OPT_INTERNAL_SKU_CHECK_FAILED (0xB8U) +#define FLCN_ERR_HS_CHK_BOARD_MISMATCH (0xB9U) +#define FLCN_ERR_HS_CHK_DISP_ENG_DISABLED (0xBAU) +#define FLCN_ERR_HS_GEN_RANDOM (0xBBU) +#define FLCN_ERR_HS_CHK_IMPROPERLY_FUSED_BOARD (0xBCU) +#define FLCN_ERR_HS_CHK_HDCP_DISABLED (0xBDU) +#define FLCN_ERR_HS_CHK_HDCP_BLACKLISTED_SKU (0XBEU) +#define FLCN_ERR_HS_SECURE_ACTION_ARG_CHECK_FAILED (0xBFU) +#define FLCN_ERR_HS_CHK_RETURN_PC_AT_HS_ENTRY_IS_OF_HS (0xC0U) +#define FLCN_ERR_HS_CHK_HS_LIB_ENTRY_CALLED_BY_NON_HS (0xC1U) +#define FLCN_ERR_HS_DECODE_TRAP_ALREADY_IN_USE (0xC2U) +#define FLCN_ERR_HS_REGISTER_READ_WRITE_ERROR (0xC3U) +#define FLCN_ERR_HS_CHK_CPUCTL_ALIAS_FALSE (0xC4U) +#define FLCN_ERR_HS_UPDATE_RESET_PLM_ERROR (0xC5U) +#define FLCN_ERR_HS_RNG_CONFIG_ERROR (0xC6U) +#define FLCN_ERR_HS_CHK_NOT_IN_HSMODE (0xC7U) +#define FLCN_ERR_HS_CHK_GFW_CHAIN_OF_TRUST_BROKEN (0xC8U) +#define FLCN_ERR_HS_HDCP22_WRONG_SEQUENCE (0xC9U) +#define FLCN_ERR_HS_HDCP22_INTEGRITY_ERROR (0xCAU) +#define FLCN_ERR_HS_HDCP22_WRONG_TYPE (0xCBU) +#define FLCN_ERR_HS_APM_NOT_ENABLED (0xCCU) +#define FLCN_ERR_HS_APM_SMC_ENABLED (0xCDU) +#define FLCN_ERR_HS_APM_FECS_NOT_HALTED (0xCEU) +#define FLCN_ERR_HS_APM_SCRATCH_PLM_INVALID (0xCFU) +#define FLCN_ERR_HS_APM_SCRATCH_INIT_INVALID (0xD0U) +#define FLCN_ERR_HS_INVALID_KEY (0xD1U) +#define FLCN_ERR_HS_SWKG_INVALID_SIGNATURE (0xD2U) +#define FLCN_ERR_HS_SCP_LIB_DMHASH_FAILED (0xD3U) +#define FLCN_ERR_HS_SCP_LIB_AESKDF_FAILED (0xD4U) +#define FLCN_ERR_INSUFFICIENT_NOPS (0xD5U) + +// +// BAR0/CSB Priv Read/Write Error Handling Defines +// These need to be defined by HW - NV Bug 200198584 +// +#define FLCN_BAR0_PRIV_PRI_ERROR_MASK 0xFFF00000U +#define FLCN_BAR0_PRIV_PRI_ERROR_CODE 0xBAD00000U +#define FLCN_BAR0_PRIV_PRI_RETURN_VAL 0x00BADBADU + +#define FLCN_CSB_PRIV_PRI_ERROR_MASK 0xFFFF0000U +#define FLCN_CSB_PRIV_PRI_ERROR_CODE 0xBADF0000U + +// +// Macro to check FALCON return status +// +#define CHECK_FLCN_STATUS(expr) do { \ + flcnStatus = (expr); \ + if (flcnStatus != FLCN_OK) \ + { \ + goto ErrorExit; \ + } \ + } while (NV_FALSE) + +// Warnings. +#define FLCN_WARN_NOTHING_TO_DO (0xD0U) +#define FLCN_WARN_NOT_QUERIED (0xD1U) +#define FLCN_WARN_DATA_NOT_AVAILABLE (0xD2U) + +// Queue handling Errors +#define FLCN_ERR_QUEUE_MGMT_INVALID_UNIT_ID (0xE0U) +#define FLCN_ERR_QUEUE_MGMT_HEAP_MIRROR_ERR (0xE1U) +#define FLCN_ERR_QUEUE_TASK_INVALID_EVENT_TYPE (0xE2U) +#define FLCN_ERR_QUEUE_TASK_INVALID_UNIT_ID (0xE3U) +#define FLCN_ERR_QUEUE_TASK_INVALID_CMD_TYPE (0xE4U) +#define FLCN_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE (0xE5U) + +// Posted write errors +#define FLCN_ERR_POSTED_WRITE_FAILURE (0xF0U) +#define FLCN_ERR_POSTED_WRITE_INTERRUPTS_ENABLED (0xF1U) +#define FLCN_ERR_POSTED_WRITE_PRI_CLUSTER_COUNT_MISMATCH (0xF2U) +#define FLCN_ERR_POSTED_WRITE_INCORRECT_PARAMS (0xF3U) + +// Lane Margining errors +#define FLCN_ERR_LM_INVALID_RECEIVER_NUMBER (0xF5U) + +// APM errors +#define FLCN_ERR_APM_NOT_FUSED_FOR_EK (0xF6U) +#define FLCN_ERR_APM_BROM_SIGN_FAIL (0xF7U) +// Booter Reload on SEC2-RTOS errors +#define FLCN_ERR_AUTH_GSP_RM_HANDOFF_FAILED (0xF8U) +#define FLCN_ERR_INVALID_WPRMETA_MAGIC_OR_REVISION (0xF9U) + +// Arithmetic errors +#define FLCN_ERR_ARITHMETIC_OVERFLOW (0xFAU) + +// Pri errros +#define FLCN_ERR_OUTSTANDING_PRI_ERROR (0xFBU) + +#endif // FLCNRETVAL_H diff --git a/userspace/sdks/nv570/nvalloc/common/inc/fsp/fsp_caps_query_rpc.h b/userspace/sdks/nv570/nvalloc/common/inc/fsp/fsp_caps_query_rpc.h new file mode 100644 index 0000000..dc4f887 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/fsp/fsp_caps_query_rpc.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef FSP_CAPS_QUERY_RPC_H +#define FSP_CAPS_QUERY_RPC_H + +#include "fsp/nvdm_payload_cmd_response.h" + +#pragma pack(1) + + /*! + * @biief Capability query payload command to FSP + */ +typedef struct +{ + NvU8 subMessageId; +} FSP_CAPS_QUERY_RPC_PAYLOAD_PARAMS; + +/*! + * @brief Capability query response payload for FSP capability query + */ +typedef struct +{ + NvU8 nvdmType; + NVDM_PAYLOAD_COMMAND_RESPONSE cmdResponse; + NvU8 rspPayload[4]; +} FSP_CAPS_QUERY_RESPONSE_PAYLOAD_PARAMS; + +#pragma pack() + +#endif // FSP_CAPS_QUERY_RPC_H diff --git a/userspace/sdks/nv570/nvalloc/common/inc/fsp/fsp_clock_boost_rpc.h b/userspace/sdks/nv570/nvalloc/common/inc/fsp/fsp_clock_boost_rpc.h new file mode 100644 index 0000000..7564fb6 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/fsp/fsp_clock_boost_rpc.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef FSP_CLOCK_BOOST_RPC_H +#define FSP_CLOCK_BOOST_RPC_H + + +#define FSP_CLOCK_BOOST_FEATURE_DISABLE_SUBMESSAGE_ID 0x0 +#define FSP_CLOCK_BOOST_FEATURE_ENABLE_SUBMESSAGE_ID 0x1 +#define FSP_CLOCK_BOOST_TRIGGER_RESTORE_SUBMESSAGE_ID 0x2 + +#pragma pack(1) + + /*! + * @brief Clock Boost payload command to FSP + */ +typedef struct +{ + NvU8 subMessageId; +} FSP_CLOCK_BOOST_RPC_PAYLOAD_PARAMS; + +#pragma pack() + +#endif // FSP_CLOCK_BOOST_RPC_H diff --git a/userspace/sdks/nv570/nvalloc/common/inc/fsp/fsp_emem_channels.h b/userspace/sdks/nv570/nvalloc/common/inc/fsp/fsp_emem_channels.h new file mode 100644 index 0000000..912eeae --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/fsp/fsp_emem_channels.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _FSP_EMEM_CHANNELS_H_ +#define _FSP_EMEM_CHANNELS_H_ + +// +// NVDM (NVIDIA Data Model) overlayed on MCTP (Management Component Transport +// Protocol) and sent over EMEM is the communication mechanism used between FSP +// management partition and CPU-RM/other uprocs. +// + +// RM uses channel 0 for FSP EMEM. +#define FSP_EMEM_CHANNEL_RM 0x0 + +// EMEM channel 0 (RM) is allocated 1K bytes. +#define FSP_EMEM_CHANNEL_RM_SIZE 1024 + +#endif // _FSP_EMEM_CHANNELS_H_ diff --git a/userspace/sdks/nv570/nvalloc/common/inc/fsp/fsp_tnvl_rpc.h b/userspace/sdks/nv570/nvalloc/common/inc/fsp/fsp_tnvl_rpc.h new file mode 100644 index 0000000..73e3034 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/fsp/fsp_tnvl_rpc.h @@ -0,0 +1,137 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _FSP_TNVL_RPC_H_ +#define _FSP_TNVL_RPC_H_ + +#define TNVL_CAPS_SUBMESSAGE_ID 0xFF +#define TNVL_GET_ATT_CERTS_SUBMESSAGE_ID 0x0 +#define TNVL_GET_ATT_REPORT_SUBMESSAGE_ID 0x1 +#define TNVL_LOCK_CONFIG_SUBMESSAGE_ID 0x2 + +#define NVSWITCH_IK_HASH_LENGTH (48) +#define NVSWITCH_ATT_CERT_SIZE_FIELD_LENGTH (2) +#define NVSWITCH_ATT_RSVD1_FIELD_LENGTH (2) + +#pragma pack(1) + + /*! + * @brief TNVL payload to query FSP capabilities + */ +typedef struct +{ + NvU8 subMessageId; +} TNVL_RPC_CAPS_PAYLOAD; + +/*! + * @brief TNVL response payload for FSP capability query + */ +typedef struct +{ + NvU8 nvdmType; + NVDM_PAYLOAD_COMMAND_RESPONSE cmdResponse; + NvU8 rspPayload[40]; +} TNVL_RPC_CAPS_RSP_PAYLOAD; + + /*! + * @brief TNVL payload to query attestation cert chain + */ +typedef struct +{ + NvU8 subMessageId; + NvU8 rsvd; + NvU8 minorVersion; + NvU8 majorVersion; +} TNVL_GET_ATT_CERTS_CMD_PAYLOAD; + +/*! + * @brief TNVL response payload for attestation cert chain + */ +typedef struct +{ + NvU8 nvdmType; + NVDM_PAYLOAD_COMMAND_RESPONSE cmdResponse; + NvU8 subMessageId; + NvU8 rsvd0; + NvU8 minorVersion; + NvU8 majorVersion; + NvU16 certChainLength; + NvU16 rsvd1; + NvU8 devIkHash[NVSWITCH_IK_HASH_LENGTH]; + NvU8 certChain[NVSWITCH_ATTESTATION_CERT_CHAIN_MAX_SIZE]; +} TNVL_GET_ATT_CERTS_RSP_PAYLOAD; + + /*! + * @brief TNVL payload to query attestation report + */ +typedef struct +{ + NvU8 subMessageId; + NvU8 rsvd; + NvU8 minorVersion; + NvU8 majorVersion; + NvU8 nonce[NVSWITCH_NONCE_SIZE]; +} TNVL_GET_ATT_REPORT_CMD_PAYLOAD; + +/*! + * @brief TNVL response payload for attestation report + */ +typedef struct +{ + NvU8 nvdmType; + NVDM_PAYLOAD_COMMAND_RESPONSE cmdResponse; + NvU8 subMessageId; + NvU8 rsvd0; + NvU8 minorVersion; + NvU8 majorVersion; + NvU32 measurementSize; + NvU8 measurementBuffer[NVSWITCH_ATTESTATION_REPORT_MAX_SIZE]; +} TNVL_GET_ATT_REPORT_RSP_PAYLOAD; + +/*! + * @brief TNVL payload to send lock config + */ +typedef struct +{ + NvU8 subMessageId; + NvU8 rsvd; + NvU8 minorVersion; + NvU8 majorVersion; +} TNVL_LOCK_CONFIG_CMD_PAYLOAD; + +/*! + * @brief TNVL response payload for lock config + */ +typedef struct +{ + NvU8 nvdmType; + NVDM_PAYLOAD_COMMAND_RESPONSE cmdResponse; + NvU8 subMessageId; + NvU8 rsvd0; + NvU8 minorVersion; + NvU8 majorVersion; +} TNVL_LOCK_CONFIG_RSP_PAYLOAD; + +#pragma pack() + +#endif // _FSP_TNVL_RPC_H_ diff --git a/userspace/sdks/nv570/nvalloc/common/inc/fsp/nvdm_payload_cmd_response.h b/userspace/sdks/nv570/nvalloc/common/inc/fsp/nvdm_payload_cmd_response.h new file mode 100644 index 0000000..fa117aa --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/fsp/nvdm_payload_cmd_response.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * @file nvdm_payload_cmd_response.h + * @brief Header file containing the definition for the + * NVDM_PAYLOAD_COMMAND_RESPONSE structure, which + * is required for SMBPBI-specific payloads and needs + * to be visible by bothe the PMU and the driver sides. + */ + +#ifndef _NVDM_PAYLOAD_CMD_RESPONSE_H +#define _NVDM_PAYLOAD_CMD_RESPONSE_H + +#pragma pack(1) +typedef struct +{ + NvU32 taskId; + NvU32 commandNvdmType; + NvU32 errorCode; +} NVDM_PAYLOAD_COMMAND_RESPONSE; +#pragma pack() + +#endif // _NVDM_PAYLOAD_CMD_RESPONSE_H diff --git a/userspace/sdks/nv570/nvalloc/common/inc/gsp/gsp_fmc_error_code_formatting.h b/userspace/sdks/nv570/nvalloc/common/inc/gsp/gsp_fmc_error_code_formatting.h new file mode 100644 index 0000000..2f0a51b --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/gsp/gsp_fmc_error_code_formatting.h @@ -0,0 +1,79 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef GSP_FMC_ERROR_CODES_FORMATTING_H +#define GSP_FMC_ERROR_CODES_FORMATTING_H + +//================================================================================ +// DRF Field Definitions for NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR +// These define the bit ranges for the register fields. +//================================================================================ + +// Error code layout +#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR_VARIANT 31:28 +#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR_PARTITION 27:24 +#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR_PAYLOAD 23:0 + +// Fields within the PAYLOAD for Variant 0 (SK) +#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR_SK_ERROR 15:8 +#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR_SK_PHASE 7:0 + +// Fields within the PAYLOAD for Variant 1 (Generic) +#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR_GENERIC_ADDITIONAL_INFO 23:16 +#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR_GENERIC_ERROR_CODE 15:0 + +// Error code layout for safety +#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR_VARIANT_XMSB 31 +#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR_VARIANT_XLSB 28 +#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR_PARTITION_XMSB 27 +#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR_PARTITION_XLSB 24 +#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR_PAYLOAD_XMSB 23 +#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR_PAYLOAD_XLSB 0 + +// Fields within the PAYLOAD for Variant 0 (SK) for safety +#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR_SK_ERROR_XMSB 15 +#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR_SK_ERROR_XLSB 8 + +#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR_SK_PHASE_XMSB 7 +#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR_SK_PHASE_XLSB 0 + +// Fields within the PAYLOAD for Variant 1 (Generic) for safety +#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR_GENERIC_ADDITIONAL_INFO_XMSB 23 +#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR_GENERIC_ADDITIONAL_INFO_XLSB 16 + +#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR_GENERIC_ERROR_CODE_XMSB 15 +#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR_GENERIC_ERROR_CODE_XLSB 0 + +//================================================================================ +// Constant Values +//================================================================================ + +// Partition ID Encoding Logic +#define GSP_FMC_PARTITION_ID_MASK 0xFU +#define GSP_FMC_PARTITION_ID_OFFSET 1U + +// Error Variants / Versions +#define GSP_FMC_ERROR_VARIANT_SK 0U +#define GSP_FMC_ERROR_VARIANT_GENERIC 1U + +#endif /* GSP_FMC_ERROR_CODES_FORMATTING_H */ diff --git a/userspace/sdks/nv570/nvalloc/common/inc/gsp/gsp_fw_sr_meta.h b/userspace/sdks/nv570/nvalloc/common/inc/gsp/gsp_fw_sr_meta.h new file mode 100644 index 0000000..22a0ef7 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/gsp/gsp_fw_sr_meta.h @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#ifndef GSP_FW_SR_META_H_ +#define GSP_FW_SR_META_H_ + +#define GSP_FW_SR_META_MAGIC 0x8a3bb9e6c6c39d93ULL +#define GSP_FW_SR_META_REVISION 2 + +#define GSP_FW_SR_META_INTERNAL_SIZE 128 + +/*! + * GSP firmware SR metadata + * + * Initialized by CPU-RM and kept in Sysmem. + * Consumed by secure ucode (Booter or ACR_RISCV). + */ +typedef struct +{ + // Magic for verification by secure ucode + NvU64 magic; // = GSP_FW_SR_META_MAGIC; + + // + // Revision number + // Bumped up when we change this interface so it is not backward compatible. + // + NvU64 revision; // = GSP_FW_SR_META_MAGIC_REVISION; + + // Members regarding data in SYSMEM + NvU64 sysmemAddrOfSuspendResumeData; + NvU64 sizeOfSuspendResumeData; + + // + // Internal members for use by secure ucode + // Must be exactly GSP_FW_SR_META_INTERNAL_SIZE bytes. + // + NvU32 internal[32]; + + // Same as flags of GspFwWprMeta + NvU32 flags; + + // Subrevision number used by secure ucode + NvU32 subrevision; + + // + // Pad structure to exactly 256 bytes (1 DMA chunk). + // Padding initialized to zero. + // + NvU32 padding[22]; +} GspFwSRMeta; + +#endif // GSP_FW_SR_META_H_ diff --git a/userspace/sdks/nv570/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h b/userspace/sdks/nv570/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h new file mode 100644 index 0000000..35293d1 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h @@ -0,0 +1,242 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#ifndef GSP_FW_WPR_META_H_ +#define GSP_FW_WPR_META_H_ + +/*! + * GSP firmware WPR metadata + * + * Initialized by CPU-RM and DMA'd to FB, at the end of what will be WPR2. + * Verified, and locked in WPR2 by Booter. + * + * Firmware scrubs the last 256mb of FB, no memory outside of this region + * may be used until the FW RM has scrubbed the remainder of memory. + * + * ---------------------------- <- fbSize (end of FB, 1M aligned) + * | VGA WORKSPACE | + * ---------------------------- <- vbiosReservedOffset (64K? aligned) + * | (potential align. gap) | + * ---------------------------- <- gspFwWprEnd + frtsSize + pmuReservedSize + * | PMU mem reservation | + * ---------------------------- <- gspFwWprEnd (128K aligned) + frtsSize + * | FRTS data | (frtsSize is 0 on GA100) + * | ------------------------ | <- frtsOffset + * | BOOT BIN (e.g. SK + BL) | + * ---------------------------- <- bootBinOffset + * | GSP FW ELF | + * ---------------------------- <- gspFwOffset + * | GSP FW (WPR) HEAP | + * ---------------------------- <- gspFwHeapOffset + * | Booter-placed metadata | + * | (struct GspFwWprMeta) | + * ---------------------------- <- gspFwWprStart (128K aligned) + * | GSP FW (non-WPR) HEAP | + * ---------------------------- <- nonWprHeapOffset, gspFwRsvdStart + * (GSP_CARVEOUT_SIZE bytes from end of FB) + */ +typedef struct +{ + // Magic + // BL to use for verification (i.e. Booter locked it in WPR2) + NvU64 magic; // = 0xdc3aae21371a60b3; + + // Revision number of Booter-BL-Sequencer handoff interface + // Bumped up when we change this interface so it is not backward compatible. + // Bumped up when we revoke GSP-RM ucode + NvU64 revision; // = 1; + + // ---- Members regarding data in SYSMEM ---------------------------- + // Consumed by Booter for DMA + + NvU64 sysmemAddrOfRadix3Elf; + NvU64 sizeOfRadix3Elf; + + NvU64 sysmemAddrOfBootloader; + NvU64 sizeOfBootloader; + + // Offsets inside bootloader image needed by Booter + NvU64 bootloaderCodeOffset; + NvU64 bootloaderDataOffset; + NvU64 bootloaderManifestOffset; + + union + { + // Used only at initial boot + struct + { + NvU64 sysmemAddrOfSignature; + NvU64 sizeOfSignature; + }; + + // + // Used at suspend/resume to read GspFwHeapFreeList + // Offset relative to GspFwWprMeta FBMEM PA (gspFwWprStart) + // + struct + { + NvU32 gspFwHeapFreeListWprOffset; + NvU32 unused0; + NvU64 unused1; + }; + }; + + // ---- Members describing FB layout -------------------------------- + NvU64 gspFwRsvdStart; + + NvU64 nonWprHeapOffset; + NvU64 nonWprHeapSize; + + NvU64 gspFwWprStart; + + // GSP-RM to use to setup heap. + NvU64 gspFwHeapOffset; + NvU64 gspFwHeapSize; + + // BL to use to find ELF for jump + NvU64 gspFwOffset; + // Size is sizeOfRadix3Elf above. + + NvU64 bootBinOffset; + // Size is sizeOfBootloader above. + + NvU64 frtsOffset; + NvU64 frtsSize; + + NvU64 gspFwWprEnd; + + // GSP-RM to use for fbRegionInfo? + NvU64 fbSize; + + // ---- Other members ----------------------------------------------- + + // GSP-RM to use for fbRegionInfo? + NvU64 vgaWorkspaceOffset; + NvU64 vgaWorkspaceSize; + + // Boot count. Used to determine whether to load the firmware image. + NvU64 bootCount; + + // This union is organized the way it is to start at an 8-byte boundary and achieve natural + // packing of the internal struct fields. + union + { + struct + { + // TODO: the partitionRpc* fields below do not really belong in this + // structure. The values are patched in by the partition bootstrapper + // when GSP-RM is booted in a partition, and this structure was a + // convenient place for the bootstrapper to access them. These should + // be moved to a different comm. mechanism between the bootstrapper + // and the GSP-RM tasks. + + // Shared partition RPC memory (physical address) + NvU64 partitionRpcAddr; + + // Offsets relative to partitionRpcAddr + NvU16 partitionRpcRequestOffset; + NvU16 partitionRpcReplyOffset; + + // Code section and dataSection offset and size. + NvU32 elfCodeOffset; + NvU32 elfDataOffset; + NvU32 elfCodeSize; + NvU32 elfDataSize; + + // Used during GSP-RM resume to check for revocation + NvU32 lsUcodeVersion; + }; + + struct + { + // Pad for the partitionRpc* fields, plus 4 bytes + NvU32 partitionRpcPadding[4]; + + // CrashCat (contiguous) buffer size/location - occupies same bytes as the + // elf(Code|Data)(Offset|Size) fields above. + // TODO: move to GSP_FMC_INIT_PARAMS + NvU64 sysmemAddrOfCrashReportQueue; + NvU32 sizeOfCrashReportQueue; + + // Pad for the lsUcodeVersion field + NvU32 lsUcodeVersionPadding[1]; + }; + }; + + // Number of VF partitions allocating sub-heaps from the WPR heap + // Used during boot to ensure the heap is adequately sized + NvU8 gspFwHeapVfPartitionCount; + + // Flags to help decide GSP-FW flow. + NvU8 flags; + + // Pad structure to exactly 256 bytes. Can replace padding with additional + // fields without incrementing revision. Padding initialized to 0. + NvU8 padding[2]; + + // + // Starts at gspFwWprEnd+frtsSize b/c FRTS is positioned + // to end where this allocation starts (when RM requests FSP to create + // FRTS). + // + NvU32 pmuReservedSize; + + // BL to use for verification (i.e. Booter says OK to boot) + NvU64 verified; // 0x0 -> unverified, 0xa0a0a0a0a0a0a0a0 -> verified +} GspFwWprMeta; + +#define GSP_FW_WPR_META_VERIFIED 0xa0a0a0a0a0a0a0a0ULL +#define GSP_FW_WPR_META_REVISION 1 +#define GSP_FW_WPR_META_MAGIC 0xdc3aae21371a60b3ULL + +#define GSP_FW_WPR_HEAP_FREE_REGION_COUNT 128 + +typedef struct +{ + // + // offset relative to GspFwWprMeta FBMEM PA + // describes a region at [offs, offs + length) + // + NvU32 offs; // start, inclusive + NvU32 length; +} GspFwHeapFreeRegion; + +typedef struct +{ + NvU64 magic; + NvU32 nregions; + GspFwHeapFreeRegion regions[GSP_FW_WPR_HEAP_FREE_REGION_COUNT]; +} GspFwHeapFreeList; + +#define GSP_FW_HEAP_FREE_LIST_MAGIC 0x4845415046524545ULL + +#define GSP_FW_FLAGS 8:0 +#define GSP_FW_FLAGS_CLOCK_BOOST NVBIT(0) +#define GSP_FW_FLAGS_RECOVERY_MARGIN_PRESENT NVBIT(1) +#define GSP_FW_FLAGS_PPCIE_ENABLED NVBIT(2) +#define GSP_FW_FLAGS_MULTI_GPU_NVLE_ENABLED NVBIT(3) +#define GSP_FW_FLAGS_SCAN_RECOVERY_MARGIN NVBIT(4) + +#endif // GSP_FW_WPR_META_H_ diff --git a/userspace/sdks/nv570/nvalloc/common/inc/gsp/gsp_proxy_reg.h b/userspace/sdks/nv570/nvalloc/common/inc/gsp/gsp_proxy_reg.h new file mode 100644 index 0000000..28aad84 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/gsp/gsp_proxy_reg.h @@ -0,0 +1,83 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGSP_PROXY_REG_H +#define NVGSP_PROXY_REG_H + +#if !defined(NVRISCV_LIBFSP_BUILD) || !NVRISCV_LIBFSP_BUILD + +#define NVGSP_PROXY_REG_CONFIDENTIAL_COMPUTE 0:0 +#define NVGSP_PROXY_REG_CONFIDENTIAL_COMPUTE_DISABLE 0x00000000 +#define NVGSP_PROXY_REG_CONFIDENTIAL_COMPUTE_ENABLE 0x00000001 + +#define NVGSP_PROXY_REG_CONF_COMPUTE_EARLY_INIT 1:1 +#define NVGSP_PROXY_REG_CONF_COMPUTE_EARLY_INIT_DISABLE 0x00000000 +#define NVGSP_PROXY_REG_CONF_COMPUTE_EARLY_INIT_ENABLE 0x00000001 + +#define NVGSP_PROXY_REG_CONF_COMPUTE_DEV_MODE 2:2 +#define NVGSP_PROXY_REG_CONF_COMPUTE_DEV_MODE_DISABLE 0x00000000 +#define NVGSP_PROXY_REG_CONF_COMPUTE_DEV_MODE_ENABLE 0x00000001 + +#define NVGSP_PROXY_REG_CONF_COMPUTE_MULTI_GPU_MODE 5:3 +#define NVGSP_PROXY_REG_CONF_COMPUTE_MULTI_GPU_MODE_NONE 0x00000000 +#define NVGSP_PROXY_REG_CONF_COMPUTE_MULTI_GPU_MODE_PROTECTED_PCIE 0x00000001 +#define NVGSP_PROXY_REG_CONF_COMPUTE_MULTI_GPU_MODE_NVLE 0x00000002 + +#define NVGSP_PROXY_REG_NVLINK_ENCRYPTION 6:6 +#define NVGSP_PROXY_REG_NVLINK_ENCRYPTION_DISABLE 0x00000000 +#define NVGSP_PROXY_REG_NVLINK_ENCRYPTION_ENABLE 0x00000001 + +#else +#define NVGSP_PROXY_REG_CONFIDENTIAL_COMPUTE 0U:0U +#define NVGSP_PROXY_REG_CONFIDENTIAL_COMPUTE_XLSB 0U +#define NVGSP_PROXY_REG_CONFIDENTIAL_COMPUTE_XMSB 0U +#define NVGSP_PROXY_REG_CONFIDENTIAL_COMPUTE_DISABLE 0x00000000U +#define NVGSP_PROXY_REG_CONFIDENTIAL_COMPUTE_ENABLE 0x00000001U + +#define NVGSP_PROXY_REG_CONF_COMPUTE_EARLY_INIT 1U:1U +#define NVGSP_PROXY_REG_CONF_COMPUTE_EARLY_INIT_XLSB 1U +#define NVGSP_PROXY_REG_CONF_COMPUTE_EARLY_INIT_XMSB 1U +#define NVGSP_PROXY_REG_CONF_COMPUTE_EARLY_INIT_DISABLE 0x00000000U +#define NVGSP_PROXY_REG_CONF_COMPUTE_EARLY_INIT_ENABLE 0x00000001U + +#define NVGSP_PROXY_REG_CONF_COMPUTE_DEV_MODE 2U:2U +#define NVGSP_PROXY_REG_CONF_COMPUTE_DEV_MODE_XLSB 2U +#define NVGSP_PROXY_REG_CONF_COMPUTE_DEV_MODE_XMSB 2U +#define NVGSP_PROXY_REG_CONF_COMPUTE_DEV_MODE_DISABLE 0x00000000U +#define NVGSP_PROXY_REG_CONF_COMPUTE_DEV_MODE_ENABLE 0x00000001U + +#define NVGSP_PROXY_REG_CONF_COMPUTE_MULTI_GPU_MODE 5U:3U +#define NVGSP_PROXY_REG_CONF_COMPUTE_MULTI_GPU_MODE_XLSB 3U +#define NVGSP_PROXY_REG_CONF_COMPUTE_MULTI_GPU_MODE_XMSB 5U +#define NVGSP_PROXY_REG_CONF_COMPUTE_MULTI_GPU_MODE_NONE 0x00000000U +#define NVGSP_PROXY_REG_CONF_COMPUTE_MULTI_GPU_MODE_PROTECTED_PCIE 0x00000001U +#define NVGSP_PROXY_REG_CONF_COMPUTE_MULTI_GPU_MODE_NVLE 0x00000002U + +#define NVGSP_PROXY_REG_NVLINK_ENCRYPTION 6U:6U +#define NVGSP_PROXY_REG_NVLINK_ENCRYPTION_XLSB 6U +#define NVGSP_PROXY_REG_NVLINK_ENCRYPTION_XMSB 6U +#define NVGSP_PROXY_REG_NVLINK_ENCRYPTION_DISABLE 0x00000000U +#define NVGSP_PROXY_REG_NVLINK_ENCRYPTION_ENABLE 0x00000001U + +#endif // !defined(NVRISCV_LIBFSP_BUILD) || !NVRISCV_LIBFSP_BUILD +#endif // NVGSP_PROXY_REG_H diff --git a/userspace/sdks/nv570/nvalloc/common/inc/gsp/gspifpub.h b/userspace/sdks/nv570/nvalloc/common/inc/gsp/gspifpub.h new file mode 100644 index 0000000..b366a9d --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/gsp/gspifpub.h @@ -0,0 +1,181 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef GSPIFPUB_H +#define GSPIFPUB_H + +#include + +/*! + * @file gspifpub.h + * @brief GSP Command/Message Interfaces - Published + */ + +/*! + * Target physical memory apertures supported for DMA + */ +typedef enum { + GSP_DMA_TARGET_LOCAL_FB, + GSP_DMA_TARGET_COHERENT_SYSTEM, + GSP_DMA_TARGET_NONCOHERENT_SYSTEM, + GSP_DMA_TARGET_COUNT +} GSP_DMA_TARGET; + +/*! + * @brief GSP-CC Microcode Initialization Parameters + */ +typedef struct GSP_FMC_INIT_PARAMS +{ + // CC initialization "registry keys" + NvU32 regkeys; +} GSP_FMC_INIT_PARAMS; + +/*! + * @brief GSP-ACR BOOT_GSP_RM Command Parameters + * + * The wprCarveout fields have no effect in environments where the WPR can be allocated + * implicitly by ACR. + */ +typedef struct GSP_ACR_BOOT_GSP_RM_PARAMS +{ + // Physical memory aperture through which gspRmDescPa is accessed + GSP_DMA_TARGET target; + // Size in bytes of the GSP-RM descriptor structure + NvU32 gspRmDescSize; + // Physical offset in the target aperture of the GSP-RM descriptor structure + NvU64 gspRmDescOffset; + // Physical offset in FB to set the start of the WPR containing GSP-RM + NvU64 wprCarveoutOffset; + // Size in bytes of the WPR containing GSP-RM + NvU32 wprCarveoutSize; + // Whether to boot GSP-RM or GSP-Proxy through ACR + NvBool bIsGspRmBoot; + // Whether inst-in-sys mode is enabled or not + NvBool bInstInSysMode; +} GSP_ACR_BOOT_GSP_RM_PARAMS; + +/*! + * @brief GSP-RM Parameters + */ +typedef struct GSP_RM_PARAMS +{ + // Physical memory aperture through which bootArgsOffset is accessed + GSP_DMA_TARGET target; + // Physical offset in the memory aperture that will be passed to GSP-RM + NvU64 bootArgsOffset; +} GSP_RM_PARAMS; + +/*! + * @brief GSP-SPDM Parameters + * + * Parameters required to set up a communication mechanism between Kernel-RM + * and SPDM partition inside GSP. + */ +typedef struct GSP_SPDM_PARAMS +{ + // Physical Memory Aperture through which all addresses are accessed + GSP_DMA_TARGET target; + + // Physical offset in the memory aperture where SPDM payload is stored + NvU64 payloadBufferOffset; + + // Size of the above payload buffer + NvU32 payloadBufferSize; +} GSP_SPDM_PARAMS; + +typedef struct GSP_RM_MEM_PARAMS +{ + NvU32 flushSysmemAddrValLo; + NvU32 flushSysmemAddrValHi; +} GSP_RM_MEM_PARAMS; + +/*! + * @brief GSP-CC Microcode Parameters for Boot Partitions + */ +typedef struct GSP_FMC_BOOT_PARAMS +{ + GSP_FMC_INIT_PARAMS initParams; + GSP_ACR_BOOT_GSP_RM_PARAMS bootGspRmParams; + GSP_RM_PARAMS gspRmParams; + GSP_SPDM_PARAMS gspSpdmParams; + GSP_RM_MEM_PARAMS gspRmMemParams; +} GSP_FMC_BOOT_PARAMS; + +/*! + * @brief Inform KeyMgr about which slots needs to be refreshed + */ +typedef enum { + // + // KeyMgr will program the received rotated session key in spare (the once which is not being used for + // current crypto flow) Rx key slot of all ports + // + refreshRxKeySlot, + // + // KeyMgr will program the received rotated session key in Tx key slot of all ports and flip the epoch + // to start using new session key for crypto flow + // + refreshTxKeySlot +} sessionKeyRefreshStage; + +/*! + * @brief Definitions for messages to GSP which will convey NVLE programming keys + */ +#define RM_GSP_NVLE_CMD_ID_UPDATE_SESSION_KEYS (0x80) +#define RM_GSP_NVLE_CMD_ID_REFRESH_SESSION_KEYS (0x81) +#define RM_GSP_NVLE_SESSION_KEY_ENTRY_SET_COUNT (1) +#define RM_GSP_NVLE_AES_256_GCM_KEY_SIZE_BYTES (32) +#define RM_GSP_NVLE_AES_256_GCM_KEY_SIZE_DWORDS (RM_GSP_NVLE_AES_256_GCM_KEY_SIZE_BYTES / sizeof(NvU32)) +#define RM_GSP_NVLE_CMD_TAG_SIZE_BYTES (16) +#define RM_GSP_NVLE_CMD_TAG_SIZE_DWORDS (RM_GSP_NVLE_CMD_TAG_SIZE_BYTES / sizeof(NvU32)) + +typedef struct +{ + NvU32 remoteGpuClid; + NvU32 remoteGpuAlid; + NvU32 key[RM_GSP_NVLE_AES_256_GCM_KEY_SIZE_DWORDS]; + // + // Epoch will inform which keyslot<0,1> is spare in case of refreshRxKeySlot stage and the epoch to which + // the Tx key slot needs to switch to in case of refreshTxKeySlot stage. Epoch is provided only when + // keyslot needs to be refreshed and keymgr will implicitly use epoch = 0 during setup stage + // + NvU8 epoch; + NvBool bValid; +} RM_GSP_NVLE_SESSION_KEY_ENTRY; + +typedef struct +{ + NvU32 cmdId; + NvBool bForKeyRotation; // To be deprecated + RM_GSP_NVLE_SESSION_KEY_ENTRY wrappedKeyEntries[RM_GSP_NVLE_SESSION_KEY_ENTRY_SET_COUNT]; + NvU32 keyEntriesTag[RM_GSP_NVLE_CMD_TAG_SIZE_DWORDS]; +} RM_GSP_NVLE_UPDATE_SESSION_KEYS; + +typedef struct +{ + NvU32 cmdId; + sessionKeyRefreshStage stage; // Inform KeyMgr about which slots needs to be programmmed + RM_GSP_NVLE_SESSION_KEY_ENTRY wrappedKeyEntries[RM_GSP_NVLE_SESSION_KEY_ENTRY_SET_COUNT]; + NvU32 keyEntriesTag[RM_GSP_NVLE_CMD_TAG_SIZE_DWORDS]; +} RM_GSP_NVLE_REFRESH_SESSION_KEYS; + +#endif // GSPIFPUB_H diff --git a/userspace/sdks/nv570/nvalloc/common/inc/inforom/ifrdem.h b/userspace/sdks/nv570/nvalloc/common/inc/inforom/ifrdem.h new file mode 100644 index 0000000..26395e8 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/inforom/ifrdem.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _IFR_DEM_H_ +#define _IFR_DEM_H_ + +#define INFOROM_DEM_OBJECT_V1_00_PACKED_SIZE 4144 +#define INFOROM_DEM_OBJECT_V1_00_FIFO_SIZE 4096 + +struct INFOROM_DEM_OBJECT_V1_00 +{ + INFOROM_OBJECT_HEADER_V1_00 header; + inforom_U032 seqNumber; + inforom_U016 writeOffset; + inforom_U016 readOffset; + inforom_X008 fifoBuffer[INFOROM_DEM_OBJECT_V1_00_FIFO_SIZE]; + inforom_U032 reserved[8]; +}; + +#define INFOROM_DEM_OBJECT_V1_00_FMT INFOROM_OBJECT_HEADER_V1_00_FMT "d2w4096x8d" +typedef struct INFOROM_DEM_OBJECT_V1_00 INFOROM_DEM_OBJECT_V1_00; + +#endif // _IFR_DEM_H_ diff --git a/userspace/sdks/nv570/nvalloc/common/inc/inforom/ifrecc.h b/userspace/sdks/nv570/nvalloc/common/inc/inforom/ifrecc.h new file mode 100644 index 0000000..309b47a --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/inforom/ifrecc.h @@ -0,0 +1,119 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _IFRECC_H_ +#define _IFRECC_H_ + +#include "nvtypes.h" +#include "inforom/types.h" + +// NVSwitch ECC v6 object definition +#define INFOROM_ECC_OBJECT_V6_S0_PACKED_SIZE 3808 + +//Used to determine if the entry is empty or not +#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_VALID 0:0 +#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_VALID_FALSE 0 +#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_VALID_TRUE 1 +#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_CORRUPT_TIMEDATA 1:1 +#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_CORRUPT_TIMEDATA_FALSE 0 +#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_CORRUPT_TIMEDATA_TRUE 1 +#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_ADDR_VALID 2:2 +#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_ADDR_VALID_FALSE 0 +#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_ADDR_VALID_TRUE 1 + +#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_LOCATION_LINK_ID 7:0 + +typedef struct INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER +{ + inforom_U008 header; + inforom_U032 errId; + inforom_U032 lastErrorTimestamp; + inforom_U032 averageEventDelta; + inforom_U016 location; + inforom_U016 sublocation; + inforom_U032 correctedCount; + inforom_U032 uncorrectedCount; + inforom_U032 address; + +} INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER; + +#define INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_MAX_COUNT 128 + +typedef struct INFOROM_ECC_OBJECT_V6_S0 +{ + INFOROM_OBJECT_HEADER_V1_00 header; + + NvU64_ALIGN32 uncorrectedTotal; + NvU64_ALIGN32 correctedTotal; + inforom_U032 lastClearedTimestamp; + + INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER errorEntries[INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_MAX_COUNT]; + + inforom_U008 padding[68]; +} INFOROM_ECC_OBJECT_V6_S0; + +#define INFOROM_ECC_OBJECT_V6_S0_HEADER_FMT INFOROM_OBJECT_HEADER_V1_00_FMT + +#define INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_FMT "b3d2w3d" + +#define INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_ARRAY_FMT \ + INFOROM_FMT_REP128(INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_FMT) + +#define INFOROM_ECC_OBJECT_V6_S0_PADDING_FMT "68b" + +#define INFOROM_ECC_OBJECT_V6_S0_FMT INFOROM_ECC_OBJECT_V6_S0_HEADER_FMT "qqd" \ + INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_ARRAY_FMT \ + INFOROM_ECC_OBJECT_V6_S0_PADDING_FMT + +// Error event structure for NVSwitch ECC errors +typedef struct +{ + NvU32 sxid; + NvU32 linkId; + NvBool bAddressValid; + NvU32 address; + + // The timestamp is filled in by the inforom ECC error logging API + NvU32 timestamp; + + NvBool bUncErr; + NvU32 errorCount; +} INFOROM_NVS_ECC_ERROR_EVENT; + +typedef union +{ + INFOROM_OBJECT_HEADER_V1_00 header; + INFOROM_ECC_OBJECT_V6_S0 v6s; +} INFOROM_ECC_OBJECT; + +typedef struct +{ + const char *pFmt; + NvU8 *pPackedObject; + INFOROM_ECC_OBJECT *pEcc; + + // Signals if there are pending updates to be flushed to InfoROM + NvBool bDirty; +} INFOROM_ECC_STATE, *PINFOROM_ECC_STATE; + +#endif // _IFRECC_H_ diff --git a/userspace/sdks/nv570/nvalloc/common/inc/inforom/ifrnvl.h b/userspace/sdks/nv570/nvalloc/common/inc/inforom/ifrnvl.h new file mode 100644 index 0000000..f09740d --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/inforom/ifrnvl.h @@ -0,0 +1,1561 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _IFRNVL_H_ +#define _IFRNVL_H_ + +// +// NVL - NVLINK Configuration and Error Data +// + +// Link Remote Endpoint Type +typedef enum +{ + INFOROM_NVLINK_REMOTE_TYPE_UNSUPPORTED = -1, + INFOROM_NVLINK_REMOTE_TYPE_NONE = 0, + INFOROM_NVLINK_REMOTE_TYPE_PEER = 1, + INFOROM_NVLINK_REMOTE_TYPE_SYSTEM = 2, + INFOROM_NVLINK_REMOTE_TYPE_SWITCH = 3, + INFOROM_NVLINK_REMOTE_TYPE_MAX = 3, + INFOROM_NVLINK_NUM_REMOTE_TYPES = 4 +} INFOROM_NVLINK_REMOTE_TYPE; + +// Fatal Errors +typedef enum +{ + INFOROM_NVLINK_FATAL_ERR_TYPE_UNSUPPORTED = -1, + + // + // NVLink 1.0 + // + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_DL_DATA_PARITY = 0, + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_DL_CTRL_PARITY = 1, + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_PROTOCOL = 2, + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_OVERFLOW = 3, + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_RAM_DATA_PARITY = 4, + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_RAM_HDR_PARITY = 5, + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_RESP = 6, + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_POISON = 7, + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_TX_RAM_DATA_PARITY = 8, + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_TX_RAM_HDR_PARITY = 9, + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_TX_CREDIT = 10, + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_DL_FLOW_CTRL_PARITY = 11, + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_DL_HDR_PARITY = 12, + INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_RECOVERY_LONG = 13, + INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_FAULT_RAM = 14, + INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_FAULT_INTERFACE = 15, + INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE = 16, + INFOROM_NVLINK_FATAL_ERR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE = 17, + INFOROM_NVLINK_FATAL_ERR_TYPE_DL_RX_FAULT_DL_PROTOCOL = 18, + INFOROM_NVLINK_FATAL_ERR_TYPE_DL_LTSSM_FAULT = 19, + INFOROM_NVLINK_FATAL_ERR_TYPE_MAX_V1 = 19, + INFOROM_NVLINK_NUM_V1_FATAL_ERR_TYPES = 20, + + // + // NVLink 2.0 + // + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DL_DATA_PARITY = 0, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DL_CTRL_PARITY = 1, + // No direct equivalent to: _TL_RX_PROTOCOL = 2, + // No direct equivalent to: _TL_RX_OVERFLOW = 3, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RAM_DATA_PARITY = 4, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RAM_HDR_PARITY = 5, + // No direct equivalent to: _TL_RX_RESP = 6, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DATA_POISONED_PKT_RCVD = 7, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_RAM_DATA_PARITY = 8, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_RAM_HDR_PARITY = 9, + // No direct equivalent to: _TL_TX_CREDIT = 10, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_DL_FLOW_CONTROL_PARITY = 11, + // No direct equivalent to: _TL_DL_HDR_PARITY = 12, + // Identical to NVLink 1.0: _DL_TX_RECOVERY_LONG = 13, + // Identical to NVLink 1.0: _DL_TX_FAULT_RAM = 14, + // Identical to NVLink 1.0: _DL_TX_FAULT_INTERFACE = 15, + // Identical to NVLink 1.0: _DL_TX_FAULT_SUBLINK_CHANGE = 16, + // Identical to NVLink 1.0: _DL_RX_FAULT_SUBLINK_CHANGE = 17, + // Identical to NVLink 1.0: _DL_RX_FAULT_DL_PROTOCOL = 18, + // Identical to NVLink 1.0: _DL_LTSSM_FAULT = 19, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DL_HDR_PARITY = 20, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_AE_FLIT_RCVD = 21, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_BE_FLIT_RCVD = 22, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_ADDR_ALIGN = 23, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_PKT_LEN = 24, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_CMD_ENC = 25, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_DAT_LEN_ENC = 26, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_ADDR_TYPE = 27, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_RSP_STATUS = 28, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_PKT_STATUS = 29, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ = 30, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP = 31, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE = 32, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE = 33, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE = 34, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_PO_FOR_CACHE_ATTR = 35, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_COMPRESSED_RESP = 36, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RESP_STATUS_TARGET = 37, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST = 38, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_HDR_OVERFLOW = 39, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DATA_OVERFLOW = 40, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_STOMPED_PKT_RCVD = 41, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_CORRECTABLE_INTERNAL = 42, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_UNSUPPORTED_VC_OVERFLOW = 43, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE = 44, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE = 45, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_HDR_CREDIT_OVERFLOW = 46, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_DATA_CREDIT_OVERFLOW = 47, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_DL_REPLAY_CREDIT_OVERFLOW = 48, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_UNSUPPORTED_VC_OVERFLOW = 49, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_STOMPED_PKT_SENT = 50, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_DATA_POISONED_PKT_SENT = 51, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_RESP_STATUS_TARGET = 52, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST = 53, + INFOROM_NVLINK_FATAL_ERR_TYPE_MIF_RX_RAM_DATA_PARITY = 54, + INFOROM_NVLINK_FATAL_ERR_TYPE_MIF_RX_RAM_HDR_PARITY = 55, + INFOROM_NVLINK_FATAL_ERR_TYPE_MIF_TX_RAM_DATA_PARITY = 56, + INFOROM_NVLINK_FATAL_ERR_TYPE_MIF_TX_RAM_HDR_PARITY = 57, + INFOROM_NVLINK_FATAL_ERR_TYPE_MAX_V2 = 57, + INFOROM_NVLINK_NUM_V2_FATAL_ERR_TYPES = 58, + + // NVLink 3.0 + + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_COLLAPSED_RESPONSE = 58, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_NCISOC_HDR_ECC_DBE = 59, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_NCISOC_PARITY = 60, + INFOROM_NVLINK_FATAL_ERR_TYPE_DL_LTSSM_FAULT_UP = 61, + INFOROM_NVLINK_FATAL_ERR_TYPE_DL_LTSSM_FAULT_DOWN = 62, + INFOROM_NVLINK_FATAL_ERR_TYPE_MAX_V3 = 62, + INFOROM_NVLINK_NUM_V3_FATAL_ERR_TYPES = 63, + + INFOROM_NVLINK_FATAL_ERR_TYPE_MAX = 62, + INFOROM_NVLINK_NUM_FATAL_ERR_TYPES = 63, +} INFOROM_NVLINK_FATAL_ERR_TYPE; + +typedef enum +{ + // DL RX ----------------------------------------- + // Fatal Counts + INFOROM_NVLINK_DL_RX_FAULT_DL_PROTOCOL_FATAL = 0, + INFOROM_NVLINK_DL_RX_FAULT_SUBLINK_CHANGE_FATAL, + + // Correctable Accumulated Counts + INFOROM_NVLINK_DL_RX_FLIT_CRC_CORR, + INFOROM_NVLINK_DL_RX_LANE0_CRC_CORR, + INFOROM_NVLINK_DL_RX_LANE1_CRC_CORR, + INFOROM_NVLINK_DL_RX_LANE2_CRC_CORR, + INFOROM_NVLINK_DL_RX_LANE3_CRC_CORR, + INFOROM_NVLINK_DL_RX_LINK_REPLAY_EVENTS_CORR, + + // DL TX ----------------------------------------- + // Fatal Counts + INFOROM_NVLINK_DL_TX_FAULT_RAM_FATAL, + INFOROM_NVLINK_DL_TX_FAULT_INTERFACE_FATAL, + INFOROM_NVLINK_DL_TX_FAULT_SUBLINK_CHANGE_FATAL, + + // Correctable Accumulated Counts + INFOROM_NVLINK_DL_TX_LINK_REPLAY_EVENTS_CORR, + + // DL Disassociated ------------------------------ + // Fatal Counts + INFOROM_NVLINK_DL_LTSSM_FAULT_UP_FATAL, + INFOROM_NVLINK_DL_LTSSM_FAULT_DOWN_FATAL, + + // Correctable Accumulated Counts + INFOROM_NVLINK_DL_LINK_RECOVERY_EVENTS_CORR, + + // TLC RX ---------------------------------------- + // Fatal Counts + INFOROM_NVLINK_TLC_RX_DL_HDR_PARITY_ERR_FATAL, + INFOROM_NVLINK_TLC_RX_DL_DATA_PARITY_ERR_FATAL, + INFOROM_NVLINK_TLC_RX_DL_CTRL_PARITY_ERR_FATAL, + INFOROM_NVLINK_TLC_RX_INVALID_AE_FATAL, + INFOROM_NVLINK_TLC_RX_INVALID_BE_FATAL, + INFOROM_NVLINK_TLC_RX_INVALID_ADDR_ALIGN_FATAL, + INFOROM_NVLINK_TLC_RX_PKTLEN_ERR_FATAL, + INFOROM_NVLINK_TLC_RX_RSVD_PACKET_STATUS_ERR_FATAL, + INFOROM_NVLINK_TLC_RX_RSVD_CACHE_ATTR_PROBE_REQ_ERR_FATAL, + INFOROM_NVLINK_TLC_RX_RSVD_CACHE_ATTR_PROBE_RSP_ERR_FATAL, + INFOROM_NVLINK_TLC_RX_DATLEN_GT_RMW_REQ_MAX_ERR_FATAL, + INFOROM_NVLINK_TLC_RX_DATLEN_LT_ATR_RSP_MIN_ERR_FATAL, + INFOROM_NVLINK_TLC_RX_INVALID_CR_FATAL, + INFOROM_NVLINK_TLC_RX_INVALID_COLLAPSED_RESPONSE_FATAL, + INFOROM_NVLINK_TLC_RX_HDR_OVERFLOW_FATAL, + INFOROM_NVLINK_TLC_RX_DATA_OVERFLOW_FATAL, + INFOROM_NVLINK_TLC_RX_STOMP_DETECTED_FATAL, + INFOROM_NVLINK_TLC_RX_RSVD_CMD_ENC_FATAL, + INFOROM_NVLINK_TLC_RX_RSVD_DAT_LEN_ENC_FATAL, + INFOROM_NVLINK_TLC_RX_INVALID_PO_FOR_CACHE_ATTR_FATAL, + // This is only needed for NCISOC support (not used outside SoC?) + // TLC_RX_NCISOC_CREDIT_PARITY_ERR_FATAL_COUNT, + + // Non-Fatal Counts + INFOROM_NVLINK_TLC_RX_RSP_STATUS_HW_ERR_NONFATAL, + INFOROM_NVLINK_TLC_RX_RSP_STATUS_UR_ERR_NONFATAL, + INFOROM_NVLINK_TLC_RX_RSP_STATUS_PRIV_ERR_NONFATAL, + INFOROM_NVLINK_TLC_RX_POISON_NONFATAL, + INFOROM_NVLINK_TLC_RX_AN1_HEARTBEAT_TIMEOUT_NONFATAL, + INFOROM_NVLINK_TLC_RX_ILLEGAL_PRI_WRITE_NONFATAL, + + // Correctable Accumulated Counts + // These should be logged in the ECC object instead + // TLC_RX_HDR_RAM_ECC_SBE_ACCUM, + // TLC_RX_DAT0_RAM_ECC_SBE_ACCUM, + // TLC_RX_DAT1_RAM_ECC_SBE_ACCUM, + + // TLC TX ---------------------------------------- + // Fatal Counts + INFOROM_NVLINK_TLC_TX_DL_CREDIT_PARITY_ERR_FATAL, + // These should be logged in the ECC object instead + // TLC_TX_CREQ_HDR_RAM_ECC_DBE_FATAL_COUNT, + // TLC_TX_RSP_HDR_RAM_ECC_DBE_FATAL_COUNT, + // TLC_TX_RSP1_HDR_RAM_ECC_DBE_FATAL_COUNT, + // TLC_TX_COM_HDR_RAM_ECC_DBE_FATAL_COUNT, + INFOROM_NVLINK_TLC_TX_NCISOC_HDR_ECC_DBE_FATAL, + INFOROM_NVLINK_TLC_TX_NCISOC_PARITY_ERR_FATAL, + + // Non-Fatal Counts + // This is only needed for NCISOC support (not used outside SoC?) + // TLC_TX_NCISOC_DAT_ECC_DBE_NONFATAL_COUNT, + INFOROM_NVLINK_TLC_TX_ILLEGAL_PRI_WRITE_NONFATAL, + INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC0_NONFATAL, + INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC1_NONFATAL, + INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC2_NONFATAL, + INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC3_NONFATAL, + INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC4_NONFATAL, + INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC5_NONFATAL, + INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC6_NONFATAL, + INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC7_NONFATAL, + INFOROM_NVLINK_TLC_TX_POISON_NONFATAL, + INFOROM_NVLINK_TLC_TX_RSP_STATUS_HW_ERR_NONFATAL, + INFOROM_NVLINK_TLC_TX_RSP_STATUS_UR_ERR_NONFATAL, + INFOROM_NVLINK_TLC_TX_RSP_STATUS_PRIV_ERR_NONFATAL, + + // Correctable Counts + // These should be logged in the ECC object instead + // TLC_TX_CREQ_RAMS_ECC_SBE_CORR_ACCUM, + // TLC_TX_RSP_RAMS_ECC_SBE_CORR_ACCUM, + // TLC_TX_RSP1_RAMS_ECC_SBE_CORR_ACCUM, + // TLC_TX_COM_RAMS_ECC_SBE_CORR_ACCUM, + // This is only needed for NCISOC support (not used outside SoC?) + // TLC_TX_NCISOC_ECC_LIMIT_ERR_CORR_ACCUM, + + // NVLIPT Disassociated -------------------------- + // Fatal Counts + INFOROM_NVLINK_NVLIPT_SLEEP_WHILE_ACTIVE_LINK_FATAL, + INFOROM_NVLINK_NVLIPT_RSTSEQ_PHYCTL_TIMEOUT_FATAL, + INFOROM_NVLINK_NVLIPT_RSTSEQ_CLKCTL_TIMEOUT_FATAL, + INFOROM_NVLINK_NVLIPT_CLKCTL_ILLEGAL_REQUEST_FATAL, + INFOROM_NVLINK_NVLIPT_RSTSEQ_PLL_TIMEOUT_FATAL, + INFOROM_NVLINK_NVLIPT_RSTSEQ_PHYARB_TIMEOUT_FATAL, + + // Non-Fatal Counts + INFOROM_NVLINK_NVLIPT_ILLEGAL_LINK_STATE_REQUEST_NONFATAL, + INFOROM_NVLINK_NVLIPT_FAILED_MINION_REQUEST_NONFATAL, + INFOROM_NVLINK_NVLIPT_RESERVED_REQUEST_VALUE_NONFATAL, + INFOROM_NVLINK_NVLIPT_LINK_STATE_WRITE_WHILE_BUSY_NONFATAL, + INFOROM_NVLINK_NVLIPT_WRITE_TO_LOCKED_SYSTEM_REG_NONFATAL, + INFOROM_NVLINK_NVLIPT_LINK_STATE_REQUEST_TIMEOUT_NONFATAL, + + // TODO 3014908 log these in the NVL object until we have ECC object support + INFOROM_NVLINK_TLC_RX_HDR_RAM_ECC_DBE_FATAL, + INFOROM_NVLINK_TLC_RX_DAT0_RAM_ECC_DBE_FATAL, + INFOROM_NVLINK_TLC_RX_DAT1_RAM_ECC_DBE_FATAL, + INFOROM_NVLINK_TLC_TX_CREQ_DAT_RAM_ECC_DBE_NONFATAL, + INFOROM_NVLINK_TLC_TX_RSP_DAT_RAM_ECC_DBE_NONFATAL, + INFOROM_NVLINK_TLC_TX_COM_DAT_RAM_ECC_DBE_NONFATAL, + INFOROM_NVLINK_TLC_TX_RSP1_DAT_RAM_ECC_DBE_FATAL, + + // DL Interrupts ----------------------------------------- + // Fatal Counts + INFOROM_NVLINK_DL_PHY_A_FATAL, + INFOROM_NVLINK_DL_RX_CRC_COUNTER_FATAL, + INFOROM_NVLINK_DL_TX_PL_ERROR_FATAL, + INFOROM_NVLINK_DL_RX_PL_ERROR_FATAL, + + INFOROM_NVLINK_MAX_ERROR_TYPE +} INFOROM_NVLINK_ERROR_TYPES; + +#define INFOROM_NVLINK_V1_FATAL_ERR_TYPES \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_DL_DATA_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_DL_CTRL_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_PROTOCOL) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_OVERFLOW) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_RAM_DATA_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_RAM_HDR_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_RESP) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_POISON) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_TX_RAM_DATA_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_TX_RAM_HDR_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_TX_CREDIT) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_DL_FLOW_CTRL_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_DL_HDR_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_RECOVERY_LONG) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_FAULT_RAM) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_FAULT_INTERFACE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_RX_FAULT_DL_PROTOCOL) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_LTSSM_FAULT) + +#define INFOROM_NVLINK_V2_FATAL_ERR_TYPES \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DL_DATA_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DL_CTRL_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RAM_DATA_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RAM_HDR_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DATA_POISONED_PKT_RCVD) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_RAM_DATA_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_RAM_HDR_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_DL_FLOW_CONTROL_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_RECOVERY_LONG) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_FAULT_RAM) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_FAULT_INTERFACE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_RX_FAULT_DL_PROTOCOL) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_LTSSM_FAULT) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DL_HDR_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_AE_FLIT_RCVD) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_BE_FLIT_RCVD) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_ADDR_ALIGN) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_PKT_LEN) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_CMD_ENC) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_DAT_LEN_ENC) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_ADDR_TYPE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_RSP_STATUS) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_PKT_STATUS) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_PO_FOR_CACHE_ATTR) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_COMPRESSED_RESP) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RESP_STATUS_TARGET) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_HDR_OVERFLOW) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DATA_OVERFLOW) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_STOMPED_PKT_RCVD) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_CORRECTABLE_INTERNAL) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_UNSUPPORTED_VC_OVERFLOW) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_HDR_CREDIT_OVERFLOW) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_DATA_CREDIT_OVERFLOW) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_DL_REPLAY_CREDIT_OVERFLOW) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_UNSUPPORTED_VC_OVERFLOW) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_STOMPED_PKT_SENT) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_DATA_POISONED_PKT_SENT) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_RESP_STATUS_TARGET) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_MIF_RX_RAM_DATA_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_MIF_RX_RAM_HDR_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_MIF_TX_RAM_DATA_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_MIF_TX_RAM_HDR_PARITY) + +#define INFOROM_NVLINK_V3_FATAL_ERR_TYPES \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DL_DATA_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DL_CTRL_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_DL_FLOW_CONTROL_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_FAULT_RAM) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_FAULT_INTERFACE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_RX_FAULT_DL_PROTOCOL) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DL_HDR_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_AE_FLIT_RCVD) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_BE_FLIT_RCVD) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_ADDR_ALIGN) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_PKT_LEN) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_CMD_ENC) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_DAT_LEN_ENC) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_PKT_STATUS) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_PO_FOR_CACHE_ATTR) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_COMPRESSED_RESP) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_HDR_OVERFLOW) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DATA_OVERFLOW) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_STOMPED_PKT_RCVD) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_COLLAPSED_RESPONSE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_NCISOC_HDR_ECC_DBE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_NCISOC_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_LTSSM_FAULT_UP) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_LTSSM_FAULT_DOWN) + +#define INFOROM_NVLINK_V4_FATAL_ERR_TYPES \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_PHY_A) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_RX_CRC_COUNTER) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_PL_ERROR) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_RX_PL_ERROR) + +#define INFOROM_ADD_NVLINK_FATAL_ERR_TYPE(mask, type) \ + mask |= NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_##type) + +typedef struct +{ + NvU32 errorsPerMinute; + NvU32 timestamp; +} INFOROM_NVLINK_ERROR_RATE; + +#define INFOROM_NVLINK_NUM_LINKS 6 + +typedef union INFOROM_NVL_OBJECT INFOROM_NVL_OBJECT, *PINFOROM_NVL_OBJECT; + +// Version 1.0 ---------------------------------------------------------------- + +// Link Remote Endpoint Type +typedef enum +{ + INFOROM_NVL_OBJECT_V1_REMOTE_TYPE_UNSUPPORTED = -1, + INFOROM_NVL_OBJECT_V1_REMOTE_TYPE_NONE = 0, + INFOROM_NVL_OBJECT_V1_REMOTE_TYPE_PEER = 1, + INFOROM_NVL_OBJECT_V1_REMOTE_TYPE_SYSTEM = 2, + INFOROM_NVL_OBJECT_V1_REMOTE_TYPE_SWITCH = 3, + INFOROM_NVL_OBJECT_V1_REMOTE_TYPE_MAX = 3, + INFOROM_NVL_OBJECT_V1_NUM_REMOTE_TYPES = 4, +} INFOROM_NVL_OBJECT_V1_REMOTE_TYPE; + +// Fatal Errors +typedef enum +{ + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_UNSUPPORTED = -1, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_RX_DL_DATA_PARITY = 0, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_RX_DL_CTRL_PARITY = 1, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_RX_PROTOCOL = 2, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_RX_OVERFLOW = 3, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_RX_RAM_DATA_PARITY = 4, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_RX_RAM_HDR_PARITY = 5, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_RX_RESP = 6, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_RX_POISON = 7, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_TX_RAM_DATA_PARITY = 8, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_TX_RAM_HDR_PARITY = 9, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_TX_CREDIT = 10, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_DL_FLOW_CTRL_PARITY = 11, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_DL_HDR_PARITY = 12, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_DL_TX_RECOVERY_LONG = 13, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_DL_TX_FAULT_RAM = 14, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_DL_TX_FAULT_INTERFACE = 15, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_DL_TX_FAULT_SUBLINK_CHANGE = 16, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_DL_RX_FAULT_SUBLINK_CHANGE = 17, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_DL_RX_FAULT_DL_PROTOCOL = 18, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_DL_LTSSM_FAULT = 19, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_MAX = 19, + INFOROM_NVL_OBJECT_V1_NUM_FATAL_ERR_INDICES = 20, +} INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX; + +typedef struct INFOROM_NVL_OBJECT_V1_FATAL_ERR_DATA +{ + inforom_U008 counts[INFOROM_NVL_OBJECT_V1_NUM_FATAL_ERR_INDICES]; + inforom_U008 reserved[25]; +} INFOROM_NVL_OBJECT_V1_FATAL_ERR_DATA; + +#define INFOROM_NVL_OBJECT_V1_FATAL_ERR_DATA_FMT "45b" + +// Non-Fatal Errors +typedef struct INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_ENTRY +{ + inforom_U024 errRate; + inforom_U032 timestamp; +} INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_ENTRY; + +#define INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_FMT "td" + +#define INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_DAY_ENTRIES 5 +#define INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_DAY_INTERVAL (60*60*24) +#define INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_MONTH_ENTRIES 3 +#define INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_MONTH_INTERVAL (60*60*24*30) + +typedef struct INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_DATA +{ + INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_ENTRY maxNDaysAgo[ + INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_DAY_ENTRIES]; + INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_ENTRY maxNMonthsAgo[ + INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_MONTH_ENTRIES]; +} INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_DATA; + +#define INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_DATA_FMT \ + INFOROM_FMT_REP08(INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_FMT) + +typedef struct INFOROM_NVL_OBJECT_V1_ERR_DATA +{ + INFOROM_NVL_OBJECT_V1_FATAL_ERR_DATA fatal; + INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_DATA nonfatal; +} INFOROM_NVL_OBJECT_V1_ERR_DATA; + +#define INFOROM_NVL_OBJECT_V1_ERR_DATA_FMT \ + INFOROM_NVL_OBJECT_V1_FATAL_ERR_DATA_FMT \ + INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_DATA_FMT + +#define INFOROM_NVL_OBJECT_V1_NUM_LINKS 6 + +typedef struct INFOROM_NVL_OBJECT_V1 +{ + INFOROM_OBJECT_HEADER_V1_00 header; + inforom_U004 lastErrorRemoteType[ + INFOROM_NVL_OBJECT_V1_NUM_LINKS]; + inforom_U008 reserved1[1]; + INFOROM_NVL_OBJECT_V1_ERR_DATA errData[INFOROM_NVL_OBJECT_V1_NUM_LINKS]; + inforom_U016 padding[1]; + inforom_U032 reserved2[13]; +} INFOROM_NVL_OBJECT_V1; + +#define INFOROM_NVL_OBJECT_V1_FMT \ + INFOROM_OBJECT_HEADER_V1_00_FMT \ + "6n" /* lastRemoteType */ \ + "b" /* reserved1 */ \ + INFOROM_FMT_REP04(INFOROM_NVL_OBJECT_V1_ERR_DATA_FMT) \ + INFOROM_FMT_REP02(INFOROM_NVL_OBJECT_V1_ERR_DATA_FMT) \ + "w" /* padding */ \ + "13d" /* reserved2 */ + +#define INFOROM_NVL_OBJECT_V1_PACKED_SIZE 672 + +// Version 2.0 ---------------------------------------------------------------- + +// Link Remote Endpoint Type +typedef enum +{ + INFOROM_NVL_OBJECT_V2_REMOTE_TYPE_UNSUPPORTED = -1, + INFOROM_NVL_OBJECT_V2_REMOTE_TYPE_NONE = 0, + INFOROM_NVL_OBJECT_V2_REMOTE_TYPE_PEER = 1, + INFOROM_NVL_OBJECT_V2_REMOTE_TYPE_SYSTEM = 2, + INFOROM_NVL_OBJECT_V2_REMOTE_TYPE_SWITCH = 3, + INFOROM_NVL_OBJECT_V2_REMOTE_TYPE_MAX = 3, + INFOROM_NVL_OBJECT_V2_NUM_REMOTE_TYPES = 4, +} INFOROM_NVL_OBJECT_V2_REMOTE_TYPE; + +// Fatal Errors +typedef enum +{ + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_UNSUPPORTED = -1, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_DL_HDR_PARITY = 0, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_DL_DATA_PARITY = 1, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_DL_CTRL_PARITY = 2, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_RAM_DATA_PARITY = 3, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_RAM_HDR_PARITY = 4, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_INVALID_AE_FLIT_RCVD = 5, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_INVALID_BE_FLIT_RCVD = 6, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_INVALID_ADDR_ALIGN = 7, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_PKT_LEN = 8, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_RSVD_CMD_ENC = 9, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_RSVD_DAT_LEN_ENC = 10, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_RSVD_ADDR_TYPE = 11, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_RSVD_RSP_STATUS = 12, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_RSVD_PKT_STATUS = 13, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ = 14, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP = 15, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE = 16, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE = 17, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE = 18, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_INVALID_PO_FOR_CACHE_ATTR = 19, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_INVALID_COMPRESSED_RESP = 20, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_RESP_STATUS_TARGET = 21, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST = 22, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_HDR_OVERFLOW = 23, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_DATA_OVERFLOW = 24, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_STOMPED_PKT_RCVD = 25, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_DATA_POISONED_PKT_RCVD = 26, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_CORRECTABLE_INTERNAL = 27, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_UNSUPPORTED_VC_OVERFLOW = 28, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE = 29, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE = 30, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_TX_HDR_CREDIT_OVERFLOW = 31, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_TX_DATA_CREDIT_OVERFLOW = 32, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_TX_DL_REPLAY_CREDIT_OVERFLOW = 33, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_TX_DL_FLOW_CONTROL_PARITY = 34, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_TX_RAM_HDR_PARITY = 35, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_TX_RAM_DATA_PARITY = 36, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_TX_UNSUPPORTED_VC_OVERFLOW = 37, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_TX_STOMPED_PKT_SENT = 38, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_TX_DATA_POISONED_PKT_SENT = 39, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_TX_RESP_STATUS_TARGET = 40, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST = 41, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_MIF_RX_RAM_DATA_PARITY = 42, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_MIF_RX_RAM_HDR_PARITY = 43, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_MIF_TX_RAM_DATA_PARITY = 44, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_MIF_TX_RAM_HDR_PARITY = 45, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_DL_TX_RECOVERY_LONG = 46, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_DL_TX_FAULT_RAM = 47, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_DL_TX_FAULT_INTERFACE = 48, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_DL_TX_FAULT_SUBLINK_CHANGE = 49, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_DL_RX_FAULT_SUBLINK_CHANGE = 50, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_DL_RX_FAULT_DL_PROTOCOL = 51, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_DL_LTSSM_FAULT = 52, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_MAX = 52, + INFOROM_NVL_OBJECT_V2_NUM_FATAL_ERR_INDICES = 53, +} INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX; + +typedef struct INFOROM_NVL_OBJECT_V2_FATAL_ERR_DATA +{ + inforom_U008 counts[INFOROM_NVL_OBJECT_V2_NUM_FATAL_ERR_INDICES]; +} INFOROM_NVL_OBJECT_V2_FATAL_ERR_DATA; + +#define INFOROM_NVL_OBJECT_V2_FATAL_ERR_DATA_FMT "53b" + +// Non-Fatal Errors +typedef INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_ENTRY + INFOROM_NVL_OBJECT_V2_NONFATAL_ERR_RATE_ENTRY; + +#define INFOROM_NVL_OBJECT_V2_NONFATAL_ERR_RATE_FMT \ + INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_FMT + +#define INFOROM_NVL_OBJECT_V2_NONFATAL_ERR_RATE_DAY_ENTRIES \ + INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_DAY_ENTRIES +#define INFOROM_NVL_OBJECT_V2_NONFATAL_ERR_RATE_DAY_INTERVAL \ + INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_DAY_INTERVAL +#define INFOROM_NVL_OBJECT_V2_NONFATAL_ERR_RATE_MONTH_ENTRIES \ + INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_MONTH_ENTRIES +#define INFOROM_NVL_OBJECT_V2_NONFATAL_ERR_RATE_MONTH_INTERVAL \ + INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_MONTH_INTERVAL + +typedef INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_DATA + INFOROM_NVL_OBJECT_V2_NONFATAL_ERR_DATA; + +#define INFOROM_NVL_OBJECT_V2_NONFATAL_ERR_DATA_FMT \ + INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_DATA_FMT + +typedef struct INFOROM_NVL_OBJECT_V2_ERR_DATA +{ + INFOROM_NVL_OBJECT_V2_FATAL_ERR_DATA fatal; + INFOROM_NVL_OBJECT_V2_NONFATAL_ERR_DATA nonfatal; +} INFOROM_NVL_OBJECT_V2_ERR_DATA; + +#define INFOROM_NVL_OBJECT_V2_ERR_DATA_FMT \ + INFOROM_NVL_OBJECT_V2_FATAL_ERR_DATA_FMT \ + INFOROM_NVL_OBJECT_V2_NONFATAL_ERR_DATA_FMT + +#define INFOROM_NVL_OBJECT_V2_NUM_LINKS INFOROM_NVL_OBJECT_V1_NUM_LINKS + +typedef struct INFOROM_NVL_OBJECT_V2 +{ + INFOROM_OBJECT_HEADER_V1_00 header; + inforom_U004 lastErrorRemoteType[ + INFOROM_NVL_OBJECT_V2_NUM_LINKS]; + inforom_U008 reserved1[1]; + INFOROM_NVL_OBJECT_V2_ERR_DATA errData[INFOROM_NVL_OBJECT_V2_NUM_LINKS]; + inforom_U016 padding[1]; + inforom_U032 reserved2[1]; +} INFOROM_NVL_OBJECT_V2; + +#define INFOROM_NVL_OBJECT_V2_FMT \ + INFOROM_OBJECT_HEADER_V1_00_FMT \ + "6n" /* lastRemoteType */ \ + "b" /* reserved1 */ \ + INFOROM_FMT_REP04(INFOROM_NVL_OBJECT_V2_ERR_DATA_FMT) \ + INFOROM_FMT_REP02(INFOROM_NVL_OBJECT_V2_ERR_DATA_FMT) \ + "w" /* padding */ \ + "d" /* reserved2 */ + +#define INFOROM_NVL_OBJECT_V2_PACKED_SIZE 672 + +// Version 3.G0 --------------------------------------------------------------- + +#define INFOROM_NVL_OBJECT_V3G_NUM_LINKS 12 +#define INFOROM_NVL_OBJECT_V3G_MAX_SEED_BUFFER_SIZE 7 + +typedef INFOROM_NVL_OBJECT_V2_REMOTE_TYPE INFOROM_NVL_OBJECT_V3_REMOTE_TYPE; + +typedef struct INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO +{ + inforom_U032 lastUpdated; + NvU64_ALIGN32 remoteDeviceSID; + inforom_U008 remoteDeviceType; + inforom_U008 remoteDeviceLink; +} INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO; + +#define INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO_FMT "dq2b" + +typedef struct INFOROM_NVL_OBJECT_V3_MINION_DATA +{ + inforom_U032 lastUpdated; + inforom_U032 data[INFOROM_NVL_OBJECT_V3G_MAX_SEED_BUFFER_SIZE]; +} INFOROM_NVL_OBJECT_V3_MINION_DATA; + +#define INFOROM_NVL_OBJECT_V3_MINION_DATA_FMT "8d" + +typedef struct INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE +{ + inforom_U032 lastUpdated; + inforom_U032 flitCrcErrorsPerMinute; + inforom_U016 laneCrcErrorsPerMinute[4]; +} INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE; + +#define INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE_FMT "2d4w" + +typedef INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE + INFOROM_NVL_OBJECT_V3G_CORRECTABLE_ERROR_RATE_ARRAY[INFOROM_NVL_OBJECT_V3G_NUM_LINKS]; + +#define INFOROM_NVL_OBJECT_V3G_CORRECTABLE_ERROR_RATE_ARRAY_FMT \ + INFOROM_FMT_REP08(INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE_FMT) \ + INFOROM_FMT_REP04(INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE_FMT) + +typedef struct INFOROM_NVL_OBJECT_V3G_MAX_CORRECTABLE_ERROR_RATES +{ + INFOROM_NVL_OBJECT_V3G_CORRECTABLE_ERROR_RATE_ARRAY dailyMaxCorrectableErrorRates[5]; + INFOROM_NVL_OBJECT_V3G_CORRECTABLE_ERROR_RATE_ARRAY monthlyMaxCorrectableErrorRates[3]; +} INFOROM_NVL_OBJECT_V3G_MAX_CORRECTABLE_ERROR_RATES; + +#define INFOROM_NVL_OBJECT_V3G_MAX_CORRECTABLE_ERROR_RATES_FMT \ + INFOROM_FMT_REP08(INFOROM_NVL_OBJECT_V3G_CORRECTABLE_ERROR_RATE_ARRAY_FMT) + +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_NVLIPT_INSTANCE_ID 3:0 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID 7:4 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_DL0 0 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_DL1 1 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_DL2 2 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_DL3 3 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_DL4 4 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_DL5 5 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_DL(n) \ + (NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_DL0+(n)) +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_TLC0 6 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_TLC1 7 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_TLC2 8 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_TLC3 9 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_TLC4 10 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_TLC5 11 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_TLC(n) \ + (NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_TLC0+(n)) +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_MINION 12 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_NVLIPT 13 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_DIRECTION 9:8 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_DIRECTION_NA 1 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_DIRECTION_RX 2 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_DIRECTION_TX 3 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_SEVERITY 11:10 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_SEVERITY_CORRECTABLE 1 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_SEVERITY_UNCORRECTABLE_NONFATAL 2 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_SEVERITY_UNCORRECTABLE_FATAL 3 + +#define INFOROM_NVL_OBJECT_V3_NVLIPT_INSTANCE_MAX 15 +#define INFOROM_NVL_OBJECT_V3_BLOCK_ID_MAX 15 + +#define NV_INFOROM_NVL_OBJECT_V3_NVLIPT_ERROR_SUBTYPE 4:0 +#define NV_INFOROM_NVL_OBJECT_V3_NVLIPT_ERROR_LINK_ID 7:5 +#define NV_INFOROM_NVL_OBJECT_V3_NVLIPT_ERROR_LINK_ID_COMMON 7 + +// Format is ____ +// Each _ has its own subtype space. +typedef enum +{ + // DL RX ----------------------------------------- + // Fatal Counts + DL_RX_FAULT_DL_PROTOCOL_FATAL_COUNT = 0, + DL_RX_FAULT_SUBLINK_CHANGE_FATAL_COUNT, + + // Correctable Accumulated Counts + DL_RX_FLIT_CRC_CORR_ACCUM, + DL_RX_LANE0_CRC_CORR_ACCUM, + DL_RX_LANE1_CRC_CORR_ACCUM, + DL_RX_LANE2_CRC_CORR_ACCUM, + DL_RX_LANE3_CRC_CORR_ACCUM, + DL_RX_LINK_REPLAY_EVENTS_CORR_ACCUM, + + // DL TX ----------------------------------------- + // Fatal Counts + DL_TX_FAULT_RAM_FATAL_COUNT = 0, + DL_TX_FAULT_INTERFACE_FATAL_COUNT, + DL_TX_FAULT_SUBLINK_CHANGE_FATAL_COUNT, + + // Correctable Accumulated Counts + DL_TX_LINK_REPLAY_EVENTS_CORR_ACCUM, + + // DL Disassociated ------------------------------ + // Fatal Counts + DL_NA_LTSSM_FAULT_UP_FATAL_COUNT = 0, + DL_NA_LTSSM_FAULT_DOWN_FATAL_COUNT, + + // Correctable Accumulated Counts + DL_NA_LINK_RECOVERY_EVENTS_CORR_ACCUM, + + DL_NA_PHY_A_FATAL_COUNT, + DL_RX_CRC_COUNTER_FATAL_COUNT, + DL_TX_PL_ERROR_FATAL_COUNT, + DL_RX_PL_ERROR_FATAL_COUNT, + + // TLC RX ---------------------------------------- + // Fatal Counts + TLC_RX_DL_HDR_PARITY_ERR_FATAL_COUNT = 0, + TLC_RX_DL_DATA_PARITY_ERR_FATAL_COUNT, + TLC_RX_DL_CTRL_PARITY_ERR_FATAL_COUNT, + TLC_RX_INVALID_AE_FATAL_COUNT, + TLC_RX_INVALID_BE_FATAL_COUNT, + TLC_RX_INVALID_ADDR_ALIGN_FATAL_COUNT, + TLC_RX_PKTLEN_ERR_FATAL_COUNT, + TLC_RX_RSVD_PACKET_STATUS_ERR_FATAL_COUNT, + TLC_RX_RSVD_CACHE_ATTR_PROBE_REQ_ERR_FATAL_COUNT, + TLC_RX_RSVD_CACHE_ATTR_PROBE_RSP_ERR_FATAL_COUNT, + TLC_RX_DATLEN_GT_RMW_REQ_MAX_ERR_FATAL_COUNT, + TLC_RX_DATLEN_LT_ATR_RSP_MIN_ERR_FATAL_COUNT, + TLC_RX_INVALID_CR_FATAL_COUNT, + TLC_RX_INVALID_COLLAPSED_RESPONSE_FATAL_COUNT, + TLC_RX_HDR_OVERFLOW_FATAL_COUNT, + TLC_RX_DATA_OVERFLOW_FATAL_COUNT, + TLC_RX_STOMP_DETECTED_FATAL_COUNT, + TLC_RX_RSVD_CMD_ENC_FATAL_COUNT, + TLC_RX_RSVD_DAT_LEN_ENC_FATAL_COUNT, + TLC_RX_INVALID_PO_FOR_CACHE_ATTR_FATAL_COUNT, + // This is only needed for NCISOC support (not used outside SoC?) + // TLC_RX_NCISOC_CREDIT_PARITY_ERR_FATAL_COUNT, + + // Non-Fatal Counts + TLC_RX_RSP_STATUS_HW_ERR_NONFATAL_COUNT, + TLC_RX_RSP_STATUS_UR_ERR_NONFATAL_COUNT, + TLC_RX_RSP_STATUS_PRIV_ERR_NONFATAL_COUNT, + TLC_RX_POISON_NONFATAL_COUNT, + TLC_RX_AN1_HEARTBEAT_TIMEOUT_NONFATAL_COUNT, + TLC_RX_ILLEGAL_PRI_WRITE_NONFATAL_COUNT, + + // Fatal Counts addendum + TLC_RX_HDR_RAM_ECC_DBE_FATAL_COUNT, + TLC_RX_DAT0_RAM_ECC_DBE_FATAL_COUNT, + TLC_RX_DAT1_RAM_ECC_DBE_FATAL_COUNT, + + // Correctable Accumulated Counts + // These should be logged in the ECC object instead + // TLC_RX_HDR_RAM_ECC_SBE_ACCUM, + // TLC_RX_DAT0_RAM_ECC_SBE_ACCUM, + // TLC_RX_DAT1_RAM_ECC_SBE_ACCUM, + + // TLC TX ---------------------------------------- + // Fatal Counts + TLC_TX_DL_CREDIT_PARITY_ERR_FATAL_COUNT = 0, + // These should be logged in the ECC object instead + // TLC_TX_CREQ_HDR_RAM_ECC_DBE_FATAL_COUNT, + // TLC_TX_RSP_HDR_RAM_ECC_DBE_FATAL_COUNT, + // TLC_TX_RSP1_HDR_RAM_ECC_DBE_FATAL_COUNT, + // TLC_TX_COM_HDR_RAM_ECC_DBE_FATAL_COUNT, + TLC_TX_NCISOC_HDR_ECC_DBE_FATAL_COUNT, + TLC_TX_NCISOC_PARITY_ERR_FATAL_COUNT, + + // Non-Fatal Counts + // This is only needed for NCISOC support (not used outside SoC?) + // TLC_TX_NCISOC_DAT_ECC_DBE_NONFATAL_COUNT, + TLC_TX_ILLEGAL_PRI_WRITE_NONFATAL_COUNT, + TLC_TX_AN1_TIMEOUT_VC0_NONFATAL_COUNT, + TLC_TX_AN1_TIMEOUT_VC1_NONFATAL_COUNT, + TLC_TX_AN1_TIMEOUT_VC2_NONFATAL_COUNT, + TLC_TX_AN1_TIMEOUT_VC3_NONFATAL_COUNT, + TLC_TX_AN1_TIMEOUT_VC4_NONFATAL_COUNT, + TLC_TX_AN1_TIMEOUT_VC5_NONFATAL_COUNT, + TLC_TX_AN1_TIMEOUT_VC6_NONFATAL_COUNT, + TLC_TX_AN1_TIMEOUT_VC7_NONFATAL_COUNT, + TLC_TX_POISON_NONFATAL_COUNT, + TLC_TX_RSP_STATUS_HW_ERR_NONFATAL_COUNT, + TLC_TX_RSP_STATUS_UR_ERR_NONFATAL_COUNT, + TLC_TX_RSP_STATUS_PRIV_ERR_NONFATAL_COUNT, + TLC_TX_CREQ_DAT_RAM_ECC_DBE_NONFATAL_COUNT, + TLC_TX_RSP_DAT_RAM_ECC_DBE_NONFATAL_COUNT, + TLC_TX_COM_DAT_RAM_ECC_DBE_NONFATAL_COUNT, + + // Correctable Counts + // These should be logged in the ECC object instead + // TLC_TX_CREQ_RAMS_ECC_SBE_CORR_ACCUM, + // TLC_TX_RSP_RAMS_ECC_SBE_CORR_ACCUM, + // TLC_TX_RSP1_RAMS_ECC_SBE_CORR_ACCUM, + // TLC_TX_COM_RAMS_ECC_SBE_CORR_ACCUM, + // This is only needed for NCISOC support (not used outside SoC?) + // TLC_TX_NCISOC_ECC_LIMIT_ERR_CORR_ACCUM, + + // TLC TX Fatal addendum + TLC_TX_RSP1_DAT_RAM_ECC_DBE_FATAL_COUNT, + + // NVLIPT Disassociated -------------------------- + // Fatal Counts + NVLIPT_NA_SLEEP_WHILE_ACTIVE_LINK_FATAL_COUNT = 0, + NVLIPT_NA_RSTSEQ_PHYCTL_TIMEOUT_FATAL_COUNT, + NVLIPT_NA_RSTSEQ_CLKCTL_TIMEOUT_FATAL_COUNT, + NVLIPT_NA_CLKCTL_ILLEGAL_REQUEST_FATAL_COUNT, + NVLIPT_NA_RSTSEQ_PLL_TIMEOUT_FATAL_COUNT, + NVLIPT_NA_RSTSEQ_PHYARB_TIMEOUT_FATAL_COUNT, + + // Non-Fatal Counts + NVLIPT_NA_ILLEGAL_LINK_STATE_REQUEST_NONFATAL_COUNT, + NVLIPT_NA_FAILED_MINION_REQUEST_NONFATAL_COUNT, + NVLIPT_NA_RESERVED_REQUEST_VALUE_NONFATAL_COUNT, + NVLIPT_NA_LINK_STATE_WRITE_WHILE_BUSY_NONFATAL_COUNT, + NVLIPT_NA_WRITE_TO_LOCKED_SYSTEM_REG_NONFATAL_COUNT, + NVLIPT_NA_LINK_STATE_REQUEST_TIMEOUT_NONFATAL_COUNT +} INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_SUBTYPE; + +#define INFOROM_NVL_OBJECT_V3_FATAL_ERR_INDEX_UNSUPPORTED ((NvU8) NV_U8_MAX) + +typedef enum +{ + INFOROM_NVL_ERROR_TYPE_INVALID = 0, + INFOROM_NVL_ERROR_TYPE_COUNT, + INFOROM_NVL_ERROR_TYPE_ACCUM +} INFOROM_NVL_OBJECT_V3_ERROR_TYPE; + +typedef enum +{ + INFOROM_NVL_ERROR_BLOCK_TYPE_DL = 0, + INFOROM_NVL_ERROR_BLOCK_TYPE_TLC, + INFOROM_NVL_ERROR_BLOCK_TYPE_NVLIPT +} INFOROM_NVL_ERROR_BLOCK_TYPE; + +typedef struct +{ + NvU8 nvliptInstance; + NvU8 localLinkIdx; + INFOROM_NVLINK_ERROR_TYPES error; + NvU32 count; // count is used only for correctable errors +} INFOROM_NVLINK_ERROR_EVENT; + +#define INFOROM_NVL_OBJECT_MAX_SUBLINK_WIDTH 8 +typedef struct +{ + NvU16 flitCrc; + NvU8 laneCrc[INFOROM_NVL_OBJECT_MAX_SUBLINK_WIDTH]; + NvU16 rxLinkReplay; + NvU16 txLinkReplay; + NvU16 linkRecovery; +} INFOROM_NVLINK_CORRECTABLE_ERROR_COUNTS; + +typedef struct INFOROM_NVL_OBJECT_V3_ERROR_ENTRY +{ + inforom_U008 header; + inforom_U016 metadata; + inforom_U008 errorSubtype; + union + { + struct + { + inforom_U032 lastError; + inforom_U032 avgEventDelta; + inforom_U032 totalCount; + } event; + struct + { + inforom_U032 lastUpdated; + NvU64_ALIGN32 totalCount; + } accum; + } data; +} INFOROM_NVL_OBJECT_V3_ERROR_ENTRY; + +#define INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT "bwb3d" + +#define INFOROM_NVL_OBJECT_V3G_NUM_ERROR_ENTRIES 240 + +typedef struct INFOROM_NVL_OBJECT_V3G +{ + INFOROM_OBJECT_HEADER_V1_00 header; + INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO remoteDeviceInfo[INFOROM_NVL_OBJECT_V3G_NUM_LINKS]; + INFOROM_NVL_OBJECT_V3_MINION_DATA minionData[INFOROM_NVL_OBJECT_V3G_NUM_LINKS]; + INFOROM_NVL_OBJECT_V3G_MAX_CORRECTABLE_ERROR_RATES maxCorrectableErrorRates; + INFOROM_NVL_OBJECT_V3_ERROR_ENTRY errorLog[INFOROM_NVL_OBJECT_V3G_NUM_ERROR_ENTRIES]; +} INFOROM_NVL_OBJECT_V3G; + +#define INFOROM_NVL_OBJECT_V3G_REMOTE_DEVICE_INFO_ARRAY_FMT \ + INFOROM_FMT_REP08(INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO_FMT) \ + INFOROM_FMT_REP04(INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO_FMT) + +#define INFOROM_NVL_OBJECT_V3G_MINION_DATA_ARRAY_FMT \ + INFOROM_FMT_REP08(INFOROM_NVL_OBJECT_V3_MINION_DATA_FMT) \ + INFOROM_FMT_REP04(INFOROM_NVL_OBJECT_V3_MINION_DATA_FMT) + +#define INFOROM_NVL_OBJECT_V3G_ERROR_LOG_FMT \ + INFOROM_FMT_REP128(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP64(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP32(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP16(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) + +#define INFOROM_NVL_OBJECT_V3G_FMT \ + INFOROM_OBJECT_HEADER_V1_00_FMT \ + INFOROM_NVL_OBJECT_V3G_REMOTE_DEVICE_INFO_ARRAY_FMT \ + INFOROM_NVL_OBJECT_V3G_MINION_DATA_ARRAY_FMT \ + INFOROM_NVL_OBJECT_V3G_MAX_CORRECTABLE_ERROR_RATES_FMT \ + INFOROM_NVL_OBJECT_V3G_ERROR_LOG_FMT + +#define INFOROM_NVL_OBJECT_V3G_PACKED_SIZE 5936 + +// Version 3.S0 --------------------------------------------------------------- +#define INFOROM_NVL_OBJECT_V3S_NUM_LINKS 36 +#define INFOROM_NVL_OBJECT_V3S_NUM_ERROR_ENTRIES 721 + +typedef INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE + INFOROM_NVL_OBJECT_V3S_CORRECTABLE_ERROR_RATE_ARRAY[INFOROM_NVL_OBJECT_V3S_NUM_LINKS]; + +#define INFOROM_NVL_OBJECT_V3S_CORRECTABLE_ERROR_RATE_ARRAY_FMT \ + INFOROM_FMT_REP32(INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE_FMT) \ + INFOROM_FMT_REP04(INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE_FMT) + +typedef struct INFOROM_NVL_OBJECT_V3S_MAX_CORRECTABLE_ERROR_RATES +{ + INFOROM_NVL_OBJECT_V3S_CORRECTABLE_ERROR_RATE_ARRAY dailyMaxCorrectableErrorRates[5]; + INFOROM_NVL_OBJECT_V3S_CORRECTABLE_ERROR_RATE_ARRAY monthlyMaxCorrectableErrorRates[3]; +} INFOROM_NVL_OBJECT_V3S_MAX_CORRECTABLE_ERROR_RATES; + +#define INFOROM_NVL_OBJECT_V3S_MAX_CORRECTABLE_ERROR_RATES_FMT \ + INFOROM_FMT_REP08(INFOROM_NVL_OBJECT_V3S_CORRECTABLE_ERROR_RATE_ARRAY_FMT) + +typedef struct INFOROM_NVL_OBJECT_V3S +{ + INFOROM_OBJECT_HEADER_V1_00 header; + INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO remoteDeviceInfo[INFOROM_NVL_OBJECT_V3S_NUM_LINKS]; + INFOROM_NVL_OBJECT_V3_MINION_DATA minionData[INFOROM_NVL_OBJECT_V3S_NUM_LINKS]; + INFOROM_NVL_OBJECT_V3S_MAX_CORRECTABLE_ERROR_RATES maxCorrectableErrorRates; + INFOROM_NVL_OBJECT_V3_ERROR_ENTRY errorLog[INFOROM_NVL_OBJECT_V3S_NUM_ERROR_ENTRIES]; +} INFOROM_NVL_OBJECT_V3S; + +#define INFOROM_NVL_OBJECT_V3S_REMOTE_DEVICE_INFO_ARRAY_FMT \ + INFOROM_FMT_REP32(INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO_FMT) \ + INFOROM_FMT_REP04(INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO_FMT) + +#define INFOROM_NVL_OBJECT_V3S_MINION_DATA_ARRAY_FMT \ + INFOROM_FMT_REP32(INFOROM_NVL_OBJECT_V3_MINION_DATA_FMT) \ + INFOROM_FMT_REP04(INFOROM_NVL_OBJECT_V3_MINION_DATA_FMT) + +#define INFOROM_NVL_OBJECT_V3S_ERROR_LOG_FMT \ + INFOROM_FMT_REP512(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP128(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP64(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP16(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT + +#define INFOROM_NVL_OBJECT_V3S_FMT \ + INFOROM_OBJECT_HEADER_V1_00_FMT \ + INFOROM_NVL_OBJECT_V3S_REMOTE_DEVICE_INFO_ARRAY_FMT \ + INFOROM_NVL_OBJECT_V3S_MINION_DATA_ARRAY_FMT \ + INFOROM_NVL_OBJECT_V3S_MAX_CORRECTABLE_ERROR_RATES_FMT \ + INFOROM_NVL_OBJECT_V3S_ERROR_LOG_FMT + +#define INFOROM_NVL_OBJECT_V3S_PACKED_SIZE 17808 + +// Version 4.G0 --------------------------------------------------------------- + +#define INFOROM_NVL_OBJECT_V4G_NUM_LINKS 18 + +typedef struct INFOROM_NVL_OBJECT_V4_L1_THRESHOLD_DATA +{ + inforom_U032 word1; + inforom_U032 word2; +} INFOROM_NVL_OBJECT_V4_L1_THRESHOLD_DATA; + +#define INFOROM_NVL_OBJECT_V4_L1_THRESHOLD_DATA_FMT "2d" + +typedef INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE + INFOROM_NVL_OBJECT_V4G_CORRECTABLE_ERROR_RATE_ARRAY[INFOROM_NVL_OBJECT_V4G_NUM_LINKS]; + +#define INFOROM_NVL_OBJECT_V4G_CORRECTABLE_ERROR_RATE_ARRAY_FMT \ + INFOROM_FMT_REP16(INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE_FMT) \ + INFOROM_FMT_REP02(INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE_FMT) + +typedef struct INFOROM_NVL_OBJECT_V4G_MAX_CORRECTABLE_ERROR_RATES +{ + INFOROM_NVL_OBJECT_V4G_CORRECTABLE_ERROR_RATE_ARRAY dailyMaxCorrectableErrorRates[5]; + INFOROM_NVL_OBJECT_V4G_CORRECTABLE_ERROR_RATE_ARRAY monthlyMaxCorrectableErrorRates[3]; +} INFOROM_NVL_OBJECT_V4G_MAX_CORRECTABLE_ERROR_RATES; + +#define INFOROM_NVL_OBJECT_V4G_MAX_CORRECTABLE_ERROR_RATES_FMT \ + INFOROM_FMT_REP08(INFOROM_NVL_OBJECT_V4G_CORRECTABLE_ERROR_RATE_ARRAY_FMT) + +typedef struct INFOROM_NVL_OBJECT_V4G_RESERVED +{ + inforom_U032 reserved; +} INFOROM_NVL_OBJECT_V4G_RESERVED; + +#define INFOROM_NVL_OBJECT_V4G_RESERVED_FMT "d" + +#define INFOROM_NVL_OBJECT_V4G_NUM_ERROR_ENTRIES 364 + +typedef struct INFOROM_NVL_OBJECT_V4G +{ + INFOROM_OBJECT_HEADER_V1_00 header; + INFOROM_NVL_OBJECT_V4_L1_THRESHOLD_DATA l1ThresholdData; + INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO remoteDeviceInfo[INFOROM_NVL_OBJECT_V4G_NUM_LINKS]; + INFOROM_NVL_OBJECT_V4G_MAX_CORRECTABLE_ERROR_RATES maxCorrectableErrorRates; + INFOROM_NVL_OBJECT_V3_ERROR_ENTRY errorLog[INFOROM_NVL_OBJECT_V4G_NUM_ERROR_ENTRIES]; + INFOROM_NVL_OBJECT_V4G_RESERVED reserved; +} INFOROM_NVL_OBJECT_V4G; + +#define INFOROM_NVL_OBJECT_V4G_REMOTE_DEVICE_INFO_ARRAY_FMT \ + INFOROM_FMT_REP16(INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO_FMT) \ + INFOROM_FMT_REP02(INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO_FMT) + +#define INFOROM_NVL_OBJECT_V4G_ERROR_LOG_FMT \ + INFOROM_FMT_REP128(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP128(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP64(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP32(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP08(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP04(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) + +#define INFOROM_NVL_OBJECT_V4G_FMT \ + INFOROM_OBJECT_HEADER_V1_00_FMT \ + INFOROM_NVL_OBJECT_V4G_REMOTE_DEVICE_INFO_ARRAY_FMT \ + INFOROM_NVL_OBJECT_V4_L1_THRESHOLD_DATA_FMT \ + INFOROM_NVL_OBJECT_V4G_MAX_CORRECTABLE_ERROR_RATES_FMT \ + INFOROM_NVL_OBJECT_V4G_ERROR_LOG_FMT \ + INFOROM_NVL_OBJECT_V4G_RESERVED_FMT + +#define INFOROM_NVL_OBJECT_V4G_PACKED_SIZE 8400 + +// Version 4.S0 --------------------------------------------------------------- +#define INFOROM_NVL_OBJECT_V4S_NUM_LINKS 64 +#define INFOROM_NVL_OBJECT_V4S_NUM_ERROR_ENTRIES 1286 + +typedef INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE + INFOROM_NVL_OBJECT_V4S_CORRECTABLE_ERROR_RATE_ARRAY[INFOROM_NVL_OBJECT_V4S_NUM_LINKS]; + +#define INFOROM_NVL_OBJECT_V4S_CORRECTABLE_ERROR_RATE_ARRAY_FMT \ + INFOROM_FMT_REP64(INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE_FMT) + +typedef struct INFOROM_NVL_OBJECT_V4S_MAX_CORRECTABLE_ERROR_RATES +{ + INFOROM_NVL_OBJECT_V4S_CORRECTABLE_ERROR_RATE_ARRAY dailyMaxCorrectableErrorRates[5]; + INFOROM_NVL_OBJECT_V4S_CORRECTABLE_ERROR_RATE_ARRAY monthlyMaxCorrectableErrorRates[3]; +} INFOROM_NVL_OBJECT_V4S_MAX_CORRECTABLE_ERROR_RATES; + +#define INFOROM_NVL_OBJECT_V4S_MAX_CORRECTABLE_ERROR_RATES_FMT \ + INFOROM_FMT_REP08(INFOROM_NVL_OBJECT_V4S_CORRECTABLE_ERROR_RATE_ARRAY_FMT) + +typedef struct INFOROM_NVL_OBJECT_V4S +{ + INFOROM_OBJECT_HEADER_V1_00 header; + INFOROM_NVL_OBJECT_V4_L1_THRESHOLD_DATA l1ThresholdData; + INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO remoteDeviceInfo[INFOROM_NVL_OBJECT_V4S_NUM_LINKS]; + INFOROM_NVL_OBJECT_V4S_MAX_CORRECTABLE_ERROR_RATES maxCorrectableErrorRates; + INFOROM_NVL_OBJECT_V3_ERROR_ENTRY errorLog[INFOROM_NVL_OBJECT_V4S_NUM_ERROR_ENTRIES]; +} INFOROM_NVL_OBJECT_V4S; + +#define INFOROM_NVL_OBJECT_V4S_REMOTE_DEVICE_INFO_ARRAY_FMT \ + INFOROM_FMT_REP64(INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO_FMT) + +#define INFOROM_NVL_OBJECT_V4S_ERROR_LOG_FMT \ + INFOROM_FMT_REP512(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP512(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP256(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP04(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP02(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) + +#define INFOROM_NVL_OBJECT_V4S_FMT \ + INFOROM_OBJECT_HEADER_V1_00_FMT \ + INFOROM_NVL_OBJECT_V4S_REMOTE_DEVICE_INFO_ARRAY_FMT \ + INFOROM_NVL_OBJECT_V4_L1_THRESHOLD_DATA_FMT \ + INFOROM_NVL_OBJECT_V4S_MAX_CORRECTABLE_ERROR_RATES_FMT \ + INFOROM_NVL_OBJECT_V4S_ERROR_LOG_FMT + +#define INFOROM_NVL_OBJECT_V4S_PACKED_SIZE 29680 + +#define INFOROM_NVL_OBJECT_V5_MAX_NUM_LINKS 18 +#define INFOROM_NVL_OBJECT_V5_MAX_NUM_LANES_PER_LINK 2 + +#define INFOROM_NVL_OBJECT_V5_RECORD_METRIC_LINK_DATA_UPTIME_FMT "d" +#define INFOROM_NVL_OBJECT_V5_RECORD_METRIC_LINK_DATA_LOCAL_MAX_RAW_BER_FMT "b" +#define INFOROM_NVL_OBJECT_V5_RECORD_METRIC_LINK_DATA_LOCAL_MAX_EFF_BER_FMT "b" +#define INFOROM_NVL_OBJECT_V5_RECORD_METRIC_LINK_DATA_CURR_EFF_MONITOR_FMT "w" +#define INFOROM_NVL_OBJECT_V5_RECORD_METRIC_LINK_DATA_PLR_XMIT_RETRY_FMT "d" +#define INFOROM_NVL_OBJECT_V5_RECORD_METRIC_LINK_DATA_TOTAL_RECOVERY_FMT "d" + +#define INFOROM_NVL_OBJECT_V5_RECORD_METRIC_LINK_DATA_FMT \ + INFOROM_NVL_OBJECT_V5_RECORD_METRIC_LINK_DATA_UPTIME_FMT \ + INFOROM_NVL_OBJECT_V5_RECORD_METRIC_LINK_DATA_LOCAL_MAX_RAW_BER_FMT \ + INFOROM_NVL_OBJECT_V5_RECORD_METRIC_LINK_DATA_LOCAL_MAX_EFF_BER_FMT \ + INFOROM_NVL_OBJECT_V5_RECORD_METRIC_LINK_DATA_CURR_EFF_MONITOR_FMT \ + INFOROM_NVL_OBJECT_V5_RECORD_METRIC_LINK_DATA_PLR_XMIT_RETRY_FMT \ + INFOROM_NVL_OBJECT_V5_RECORD_METRIC_LINK_DATA_TOTAL_RECOVERY_FMT + +typedef struct INFOROM_NVL_OBJECT_V5_RECORD_METRIC_LINK_DATA // u8[16] +{ + inforom_U032 uptime; // u8[4] + inforom_U008 localMaxRawBERExp; // u8[1] + inforom_U008 localMaxEffBERExp; // u8[1] + inforom_U016 currEffBERMonitor; // u8[2] + inforom_U032 plrXmitRetryWithinTSecMaxLo; // u8[4] + inforom_U032 totalSuccessfulRecoveryEvents; // u8[4] +} INFOROM_NVL_OBJECT_V5_RECORD_METRIC_LINK_DATA; + +#define INFOROM_NVL_OBJECT_V5_RECORD_METRIC_MFDE_FMT "43d" + +typedef struct INFOROM_NVL_OBJECT_V5_RECORD_METRIC_MFDE // u8[172] +{ + inforom_U032 data[43]; // u8[172] +} INFOROM_NVL_OBJECT_V5_RECORD_METRIC_MFDE; + +#define INFOROM_NVL_OBJECT_V5_RECORD_METRIC_DATA_INITIAL_RAW_BER_FMT "18b" +#define INFOROM_NVL_OBJECT_V5_RECORD_METRIC_DATA_INITIAL_EFF_BER_FMT "18b" +#define INFOROM_NVL_OBJECT_V5_RECORD_METRIC_DATA_LAST_DOWN_REASON_FMT "18b" +#define INFOROM_NVL_OBJECT_V5_RECORD_METRIC_DATA_PADDING_FMT "82b" + +#define INFOROM_NVL_OBJECT_V5_RECORD_METRIC_DATA_FMT \ + INFOROM_NVL_OBJECT_V5_RECORD_METRIC_MFDE_FMT \ + INFOROM_FMT_REP16(INFOROM_NVL_OBJECT_V5_RECORD_METRIC_LINK_DATA_FMT) \ + INFOROM_FMT_REP02(INFOROM_NVL_OBJECT_V5_RECORD_METRIC_LINK_DATA_FMT) \ + INFOROM_NVL_OBJECT_V5_RECORD_METRIC_DATA_INITIAL_RAW_BER_FMT \ + INFOROM_NVL_OBJECT_V5_RECORD_METRIC_DATA_INITIAL_EFF_BER_FMT \ + INFOROM_NVL_OBJECT_V5_RECORD_METRIC_DATA_LAST_DOWN_REASON_FMT \ + INFOROM_NVL_OBJECT_V5_RECORD_METRIC_DATA_PADDING_FMT + +typedef struct INFOROM_NVL_OBJECT_V5_RECORD_METRIC_DATA // u8[596] +{ + INFOROM_NVL_OBJECT_V5_RECORD_METRIC_MFDE mfdeEvent; // u8[172] + INFOROM_NVL_OBJECT_V5_RECORD_METRIC_LINK_DATA link[INFOROM_NVL_OBJECT_V5_MAX_NUM_LINKS]; // u8[288] + inforom_U008 initialRawBERExp[INFOROM_NVL_OBJECT_V5_MAX_NUM_LINKS]; // u8[18] + inforom_U008 initialEffBERExp[INFOROM_NVL_OBJECT_V5_MAX_NUM_LINKS]; // u8[18] + inforom_U008 lastDownReason[INFOROM_NVL_OBJECT_V5_MAX_NUM_LINKS]; // u8[18] + inforom_U008 padding[82]; // u8[82] +} INFOROM_NVL_OBJECT_V5_RECORD_METRIC_DATA; + +#define INFOROM_NVL_OBJECT_V5_ACCUMULATIVE_METRIC_HISTOGRAM_FMT "12b" + +typedef struct INFOROM_NVL_OBJECT_V5_ACCUMULATIVE_METRIC_HISTOGRAM // u8[12] +{ + inforom_U008 fixedPoint[12]; // u8[12] +} INFOROM_NVL_OBJECT_V5_ACCUMULATIVE_METRIC_HISTOGRAM; + +#define INFOROM_NVL_OBJECT_V5_ACCUMULATIVE_METRIC_LINK_DATA_LINK_DOWN_COUNT_FMT "d" + +#define INFOROM_NVL_OBJECT_V5_ACCUMULATIVE_METRIC_LINK_DATA_FMT \ + "4b" \ + INFOROM_NVL_OBJECT_V5_ACCUMULATIVE_METRIC_LINK_DATA_LINK_DOWN_COUNT_FMT \ + INFOROM_NVL_OBJECT_V5_ACCUMULATIVE_METRIC_HISTOGRAM_FMT + +typedef struct INFOROM_NVL_OBJECT_V5_ACCUMULATIVE_METRIC_LINK_DATA // u8[20] +{ + inforom_U008 reserved[4]; // u8[4] + inforom_U032 linkDownCount; // u8[4] + INFOROM_NVL_OBJECT_V5_ACCUMULATIVE_METRIC_HISTOGRAM downReasonHistogram; // u8[12] +} INFOROM_NVL_OBJECT_V5_ACCUMULATIVE_METRIC_LINK_DATA; + +#define INFOROM_NVL_OBJECT_V5_ACCUMULATIVE_METRIC_DATA_GLOBAL_MAX_RAW_BER_FMT "18b" +#define INFOROM_NVL_OBJECT_V5_ACCUMULATIVE_METRIC_DATA_GLOBAL_MAX_EFF_BER_FMT "18b" + +#define INFOROM_NVL_OBJECT_V5_ACCUMULATIVE_METRIC_DATA_FMT \ + INFOROM_FMT_REP16(INFOROM_NVL_OBJECT_V5_ACCUMULATIVE_METRIC_LINK_DATA_FMT) \ + INFOROM_FMT_REP02(INFOROM_NVL_OBJECT_V5_ACCUMULATIVE_METRIC_LINK_DATA_FMT) \ + INFOROM_NVL_OBJECT_V5_ACCUMULATIVE_METRIC_DATA_GLOBAL_MAX_RAW_BER_FMT \ + INFOROM_NVL_OBJECT_V5_ACCUMULATIVE_METRIC_DATA_GLOBAL_MAX_EFF_BER_FMT + +typedef struct INFOROM_NVL_OBJECT_V5_ACCUMULATIVE_METRIC_DATA // u8[396] +{ + INFOROM_NVL_OBJECT_V5_ACCUMULATIVE_METRIC_LINK_DATA link[INFOROM_NVL_OBJECT_V5_MAX_NUM_LINKS]; // u8[360] + inforom_U008 globalMaxRawBERExp[INFOROM_NVL_OBJECT_V5_MAX_NUM_LINKS]; // u8[18] + inforom_U008 globalMaxEffBERExp[INFOROM_NVL_OBJECT_V5_MAX_NUM_LINKS]; // u8[18] +} INFOROM_NVL_OBJECT_V5_ACCUMULATIVE_METRIC_DATA; + +#define INFOROM_NVL_OBJECT_V5_RESERVED_FMT "8b" + +#define INFOROM_NVL_OBJECT_V5_FMT \ + INFOROM_OBJECT_HEADER_V1_00_FMT \ + INFOROM_NVL_OBJECT_V5_ACCUMULATIVE_METRIC_DATA_FMT \ + INFOROM_NVL_OBJECT_V5_RECORD_METRIC_DATA_FMT \ + INFOROM_NVL_OBJECT_V5_RESERVED_FMT + +#define INFOROM_NVL_OBJECT_V5_PACKED_SIZE 1008 + +typedef struct INFOROM_NVL_OBJECT_V5 // u8[1008] +{ + INFOROM_OBJECT_HEADER_V1_00 header; // u8[8] + INFOROM_NVL_OBJECT_V5_ACCUMULATIVE_METRIC_DATA accumulative; // u8[396] + INFOROM_NVL_OBJECT_V5_RECORD_METRIC_DATA record; // u8[596] + inforom_U008 reserved[8]; // u8[8] +} INFOROM_NVL_OBJECT_V5; + +#define INFOROM_NVL_OBJECT_FLUSH_INTERVAL (60 * 10) + +typedef struct +{ + struct + { + NvU32 flitCrc; + NvU32 laneCrc[4]; + } errorsPerMinute[INFOROM_NVL_OBJECT_V3G_NUM_LINKS]; + + struct + { + NvU32 flitCrc; + NvU32 laneCrc[4]; + NvU32 rxLinkReplay; + NvU32 txLinkReplay; + NvU32 linkRecovery; + } lastRead[INFOROM_NVL_OBJECT_V3G_NUM_LINKS]; +} INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V3G; + +typedef struct +{ + struct + { + NvU32 flitCrc; + NvU32 laneCrc[4]; + } errorsPerMinute[INFOROM_NVL_OBJECT_V3S_NUM_LINKS]; + + struct + { + NvU32 flitCrc; + NvU32 laneCrc[4]; + NvU32 rxLinkReplay; + NvU32 txLinkReplay; + NvU32 linkRecovery; + } lastRead[INFOROM_NVL_OBJECT_V3S_NUM_LINKS]; +} INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V3S; + +typedef struct +{ + struct + { + NvU32 flitCrc; + NvU32 laneCrc[4]; + } errorsPerMinute[INFOROM_NVL_OBJECT_V4G_NUM_LINKS]; + + struct + { + NvU32 flitCrc; + NvU32 laneCrc[4]; + NvU32 rxLinkReplay; + NvU32 txLinkReplay; + NvU32 linkRecovery; + } lastRead[INFOROM_NVL_OBJECT_V4G_NUM_LINKS]; +} INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V4G; + +typedef struct +{ + struct + { + NvU32 flitCrc; + NvU32 laneCrc[4]; + } errorsPerMinute[INFOROM_NVL_OBJECT_V4S_NUM_LINKS]; + + struct + { + NvU32 flitCrc; + NvU32 laneCrc[4]; + NvU32 rxLinkReplay; + NvU32 txLinkReplay; + NvU32 linkRecovery; + } lastRead[INFOROM_NVL_OBJECT_V4S_NUM_LINKS]; +} INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V4S; + +typedef struct INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V5 +{ + struct + { + void *pParams; + void *pAsyncHandle; + } request[2]; + NvU8 head; +} INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V5, INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V6; + +typedef union +{ + INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V3G v3g; + INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V3S v3s; + INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V4G v4g; + INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V4S v4s; + INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V5 v5; + INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V6 v6; +} INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE; + +typedef struct +{ + const char *pFmt; + NvU8 *pPackedObject; + INFOROM_NVL_OBJECT *pNvl; + + NvBool bDirty; + NvBool bDisableFatalErrorLogging; + NvBool bDisableCorrectableErrorLogging; + NvBool bCallbackPending; + + NvU32 timeSinceLastFlush; + + INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE correctableErrorRateState; +} INFOROM_NVLINK_STATE, *PINFOROM_NVLINK_STATE; + +// Version 6.0 ------------------------------------------------------------- +#define INFOROM_NVL_OBJECT_V6_MAX_NUM_LINKS 36 +#define INFOROM_NVL_OBJECT_V6_MAX_NUM_LANES_PER_LINK 2 + +#define INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA_PLR_TX_BW_LOSS_LOW_FREQUENCY_FMT "6w" +typedef struct INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA_PLR_TX_BW_LOSS_LOW_FREQUENCY // u16[6] +{ + inforom_U016 lastPlrTxBwLossLf; // u16 + inforom_U016 meanPlrTxBwLossLf; // u16 + inforom_U016 maxPlrTxBwLossLf; // u16 + inforom_U016 consBelowPlrTxBwLossLfThreshold; // u16 + inforom_U016 numOfPlrTxBwLossLfWarnings; // u16 + inforom_U016 numOfPlrTxBwLossLfAlarms; // u16 +} INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA_PLR_TX_BW_LOSS_LOW_FREQUENCY; + +#define INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA_RECOVERY_BW_LOSS_LOW_FREQUENCY_FMT "6w" +typedef struct INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA_RECOVERY_BW_LOSS_LOW_FREQUENCY // u16[6] +{ + inforom_U016 lastRecoveryBwLossLf; // u16 + inforom_U016 meanRecoveryBwLossLf; // u16 + inforom_U016 maxRecoveryBwLossLf; // u16 + inforom_U016 consBelowRecoveryBwLossLfThreshold; // u16 + inforom_U016 numOfRecoveryBwLossLfWarnings; // u16 + inforom_U016 numOfRecoveryBwLossLfAlarms; // u16 +} INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA_RECOVERY_BW_LOSS_LOW_FREQUENCY; + +#define INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA_EFFECTIVE_BER_LOW_FREQUENCY_FMT "3w3b6n" +typedef struct INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA_EFFECTIVE_BER_LOW_FREQUENCY // u8[12] +{ + inforom_U016 consBelowEffBerLfThreshold; // u16 + inforom_U016 numOfEffBerLfWarnings; // u16 + inforom_U016 numOfEffBERLfAlarms; // u16 + inforom_U008 meanEffBerLfMagnitue; // u8 + inforom_U008 lastEffBerLfMagnitue; // u8 + inforom_U008 maxEffBerLfMagnitue; // u8 + inforom_U004 lastEffBerLfCoef; // u4 + inforom_U004 meanEffBerLfCoef; // u4 + inforom_U004 maxEffBerLfCoef; // u4 + inforom_U004 padding[3]; // u4[3] +} INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA_EFFECTIVE_BER_LOW_FREQUENCY; + +#define INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA_UPTIME_FMT "d" +#define INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA_TOTAL_RECOVERY_FMT "d" + +#define INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA_FMT \ + INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA_UPTIME_FMT \ + INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA_PLR_TX_BW_LOSS_LOW_FREQUENCY_FMT \ + INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA_RECOVERY_BW_LOSS_LOW_FREQUENCY_FMT \ + INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA_EFFECTIVE_BER_LOW_FREQUENCY_FMT \ + INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA_TOTAL_RECOVERY_FMT + +typedef struct INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA // u8[44] +{ + inforom_U032 uptime; // u8[4] + INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA_PLR_TX_BW_LOSS_LOW_FREQUENCY plrTxBwLossLf; // u16[6] + INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA_RECOVERY_BW_LOSS_LOW_FREQUENCY recoveryBwLossLf; // u16[6] + INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA_EFFECTIVE_BER_LOW_FREQUENCY effBerLf; // u8[12] + inforom_U032 totalSuccessfulRecoveryEvents; // u8[4] +} INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA; + +#define INFOROM_NVL_OBJECT_V6_RECORD_METRIC_MFDE_FMT "43w" + +typedef struct INFOROM_NVL_OBJECT_V6_RECORD_METRIC_MFDE // u8[172] +{ + inforom_U032 data[43]; // u8[172] +} INFOROM_NVL_OBJECT_V6_RECORD_METRIC_MFDE; + +#define INFOROM_NVL_OBJECT_V6_RECORD_METRIC_DATA_INITIAL_RAW_BER_FMT "36b" +#define INFOROM_NVL_OBJECT_V6_RECORD_METRIC_DATA_INITIAL_EFF_BER_FMT "36b" +#define INFOROM_NVL_OBJECT_V6_RECORD_METRIC_DATA_LAST_DOWN_REASON_FMT "36b" +#define INFOROM_NVL_OBJECT_V6_RECORD_METRIC_DATA_LAST_DOWN_ADVANCED_REASON_FMT "36w" + +#define INFOROM_NVL_OBJECT_V6_RECORD_METRIC_DATA_FMT \ + INFOROM_NVL_OBJECT_V6_RECORD_METRIC_MFDE_FMT \ + INFOROM_FMT_REP32(INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA_FMT) \ + INFOROM_FMT_REP04(INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA_FMT) \ + INFOROM_NVL_OBJECT_V6_RECORD_METRIC_DATA_INITIAL_RAW_BER_FMT \ + INFOROM_NVL_OBJECT_V6_RECORD_METRIC_DATA_INITIAL_EFF_BER_FMT \ + INFOROM_NVL_OBJECT_V6_RECORD_METRIC_DATA_LAST_DOWN_REASON_FMT \ + INFOROM_NVL_OBJECT_V6_RECORD_METRIC_DATA_LAST_DOWN_ADVANCED_REASON_FMT + +typedef struct INFOROM_NVL_OBJECT_V6_RECORD_METRIC_DATA // u8[1936] +{ + INFOROM_NVL_OBJECT_V6_RECORD_METRIC_MFDE mfdeEvent; // u8[172] + INFOROM_NVL_OBJECT_V6_RECORD_METRIC_LINK_DATA link[INFOROM_NVL_OBJECT_V6_MAX_NUM_LINKS]; // u8[1584] + inforom_U008 initialRawBERExp[INFOROM_NVL_OBJECT_V6_MAX_NUM_LINKS]; // u8[36] + inforom_U008 initialEffBERExp[INFOROM_NVL_OBJECT_V6_MAX_NUM_LINKS]; // u8[36] + inforom_U008 lastDownReason[INFOROM_NVL_OBJECT_V6_MAX_NUM_LINKS]; // u8[36] + inforom_U016 lastDownAdvancedReason[INFOROM_NVL_OBJECT_V6_MAX_NUM_LINKS]; // u8[72] +} INFOROM_NVL_OBJECT_V6_RECORD_METRIC_DATA; + +#define INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_HISTOGRAM_FMT "16b" + +typedef struct INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_HISTOGRAM // u8[24] +{ + inforom_U008 fixedPoint[24]; // u8[24] +} INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_HISTOGRAM; + +#define INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_HISTOGRAM_XID_LINK_FMT "5b" + +typedef struct INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_HISTOGRAM_XID_LINK // u8[5] +{ + inforom_U008 fixedPoint[5]; +} INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_HISTOGRAM_XID_LINK; + +#define INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_HISTOGRAM_XID_GPU_FMT "d3b" + +typedef struct INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_HISTOGRAM_XID_GPU // u8[7] +{ + inforom_U032 xidCount; // u8[4] + inforom_U008 fixedPoint[3]; // u8[3] 3 per GPU XIDs +} INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_HISTOGRAM_XID_GPU; + +#define INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_LINK_DATA_LINK_DOWN_COUNT_FMT "d" +#define INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_LINK_DATA_PADDING_FMT "3b" + +#define INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_LINK_DATA_FMT \ + INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_LINK_DATA_LINK_DOWN_COUNT_FMT \ + INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_HISTOGRAM_FMT \ + INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_HISTOGRAM_XID_LINK_FMT \ + INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_LINK_DATA_PADDING_FMT + +typedef struct INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_LINK_DATA // u8[36] +{ + inforom_U032 linkDownCount; // u8[4] + INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_HISTOGRAM downReasonHistogram; // u8[24] + INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_HISTOGRAM_XID_LINK xidHistogram; // u8[5] + inforom_U008 padding[3]; // u8[3] +} INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_LINK_DATA; + +#define INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_DATA_PADDING_FMT "b" + +#define INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_DATA_FMT \ + INFOROM_FMT_REP32(INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_LINK_DATA_FMT) \ + INFOROM_FMT_REP04(INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_LINK_DATA_FMT) \ + INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_HISTOGRAM_XID_GPU_FMT \ + INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_DATA_PADDING_FMT + +typedef struct INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_DATA // u8[1304] +{ + INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_LINK_DATA link[INFOROM_NVL_OBJECT_V6_MAX_NUM_LINKS]; // u8[1296] + INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_HISTOGRAM_XID_GPU xidHistogram; // u8[7] + inforom_U008 padding; // u8 +} INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_DATA; + +#define INFOROM_NVL_OBJECT_V6_RESERVED_FMT "784b" + +#define INFOROM_NVL_OBJECT_V6_FMT \ + INFOROM_OBJECT_HEADER_V1_00_FMT \ + INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_DATA_FMT \ + INFOROM_NVL_OBJECT_V6_RECORD_METRIC_DATA_FMT \ + INFOROM_NVL_OBJECT_V6_RESERVED_FMT + +#define INFOROM_NVL_OBJECT_V6_PACKED_SIZE 4032 + +typedef struct INFOROM_NVL_OBJECT_V6 // u8[] +{ + INFOROM_OBJECT_HEADER_V1_00 header; // u8[8] + INFOROM_NVL_OBJECT_V6_ACCUMULATIVE_METRIC_DATA accumulative; // u8[1304] + INFOROM_NVL_OBJECT_V6_RECORD_METRIC_DATA record; // u8[1936] + inforom_U008 reserved[784]; // u8[784] +} INFOROM_NVL_OBJECT_V6; + +union INFOROM_NVL_OBJECT +{ + INFOROM_OBJECT_HEADER_V1_00 header; + INFOROM_NVL_OBJECT_V1 v1; + INFOROM_NVL_OBJECT_V2 v2; + INFOROM_NVL_OBJECT_V3G v3g; + INFOROM_NVL_OBJECT_V3S v3s; + INFOROM_NVL_OBJECT_V4G v4g; + INFOROM_NVL_OBJECT_V4S v4s; + INFOROM_NVL_OBJECT_V5 v5; + INFOROM_NVL_OBJECT_V6 v6; +}; + +#endif /* _IFRNVL_H_ */ diff --git a/userspace/sdks/nv570/nvalloc/common/inc/inforom/ifrstruct.h b/userspace/sdks/nv570/nvalloc/common/inc/inforom/ifrstruct.h new file mode 100644 index 0000000..5c1caed --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/inforom/ifrstruct.h @@ -0,0 +1,110 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _IFRSTRUCT_H_ +#define _IFRSTRUCT_H_ + +#include "inforom/types.h" + +#include "inforom/ifrnvl.h" +#include "inforom/ifrecc.h" +#include "inforom/ifrdem.h" +#include "inforom/omsdef.h" + +#define INFOROM_OBD_OBJECT_V1_XX_PACKED_SIZE 128 + +struct INFOROM_OBD_OBJECT_V1_XX +{ + INFOROM_OBJECT_HEADER_V1_00 header; + inforom_U032 buildDate; + inforom_U008 marketingName[24]; + inforom_U008 serialNumber[16]; + inforom_U008 memoryManufacturer; + inforom_U008 memoryPartID[20]; + inforom_U008 memoryDateCode[6]; + inforom_U008 productPartNumber[20]; + inforom_U008 boardRevision[3]; + inforom_U008 boardType; + inforom_U008 board699PartNumber[20]; + inforom_U008 reserved[5]; +}; +#define INFOROM_OBD_OBJECT_V1_XX_FMT INFOROM_OBJECT_HEADER_V1_00_FMT "d116b" +typedef struct INFOROM_OBD_OBJECT_V1_XX INFOROM_OBD_OBJECT_V1_XX; + +#define INFOROM_OBD_OBJECT_V2_XX_PACKED_SIZE 224 + +struct INFOROM_OBD_OBJECT_V2_XX +{ + INFOROM_OBJECT_HEADER_V1_00 header; + inforom_U032 buildDate; + inforom_U008 marketingName[24]; + inforom_U008 serialNumber[16]; + inforom_U008 memoryManufacturer; + inforom_U008 memoryPartID[20]; + inforom_U008 memoryDateCode[6]; + inforom_U008 productPartNumber[20]; + inforom_U008 boardRevision[3]; + inforom_U008 boardType; + inforom_U008 board699PartNumber[20]; + inforom_U032 productLength; + inforom_U032 productWidth; + inforom_U032 productHeight; + inforom_U008 vbiosFactoryVersion[5]; + inforom_U008 board965PartNumber[20]; + inforom_U008 reserved[64]; +}; +#define INFOROM_OBD_OBJECT_V2_XX_FMT INFOROM_OBJECT_HEADER_V1_00_FMT "d111b3d89b" +typedef struct INFOROM_OBD_OBJECT_V2_XX INFOROM_OBD_OBJECT_V2_XX; + +// +// OEM 1.0 +// + +#define INFOROM_OEM_OBJECT_V1_00_PACKED_SIZE 512 +#define INFOROM_OEM_OBJECT_HEADER_VERSION 1 + +struct INFOROM_OEM_OBJECT_V1_00 +{ + INFOROM_OBJECT_HEADER_V1_00 header; + inforom_U008 oemInfo[504]; +}; +#define INFOROM_OEM_OBJECT_V1_00_FMT INFOROM_OBJECT_HEADER_V1_00_FMT "504b" +typedef struct INFOROM_OEM_OBJECT_V1_00 INFOROM_OEM_OBJECT_V1_00; + +#define INFOROM_IMG_OBJECT_V1_00_PACKED_SIZE 64 +#define INFOROM_IMG_OBJECT_V1_00_VERSION_LENGTH 16 + +struct INFOROM_IMG_OBJECT_V1_00 +{ + INFOROM_OBJECT_HEADER_V1_00 header; + inforom_U008 version[INFOROM_IMG_OBJECT_V1_00_VERSION_LENGTH]; + inforom_U016 pciDeviceId; + inforom_U016 pciVendorId; + inforom_U016 pciSubsystemId; + inforom_U016 pciSubsystemVendorId; + inforom_U008 reserved[32]; +}; +#define INFOROM_IMG_OBJECT_V1_00_FMT INFOROM_OBJECT_HEADER_V1_00_FMT "16b4w32b" +typedef struct INFOROM_IMG_OBJECT_V1_00 INFOROM_IMG_OBJECT_V1_00; + +#endif // _IFRSTRUCT_H_ diff --git a/userspace/sdks/nv570/nvalloc/common/inc/inforom/omsdef.h b/userspace/sdks/nv570/nvalloc/common/inc/inforom/omsdef.h new file mode 100644 index 0000000..9509a7b --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/inforom/omsdef.h @@ -0,0 +1,116 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _INFOROM_OMSDEF_H_ +#define _INFOROM_OMSDEF_H_ + +#include "inforom/types.h" + +#define INFOROM_OMS_OBJECT_V1_PACKED_SIZE 112 + +#define INFOROM_OMS_OBJECT_V1_SETTINGS_ENTRY_DATA_ENTRY_AVAILABLE 0:0 +#define INFOROM_OMS_OBJECT_V1_SETTINGS_ENTRY_DATA_ENTRY_AVAILABLE_NO 0 +#define INFOROM_OMS_OBJECT_V1_SETTINGS_ENTRY_DATA_ENTRY_AVAILABLE_YES 1 +#define INFOROM_OMS_OBJECT_V1_SETTINGS_ENTRY_DATA_FORCE_DEVICE_DISABLE 1:1 +#define INFOROM_OMS_OBJECT_V1_SETTINGS_ENTRY_DATA_FORCE_DEVICE_DISABLE_NO 0 +#define INFOROM_OMS_OBJECT_V1_SETTINGS_ENTRY_DATA_FORCE_DEVICE_DISABLE_YES 1 + +#define INFOROM_OMS_OBJECT_V1G_SETTINGS_ENTRY_DATA_RESERVED 23:2 +#define INFOROM_OMS_OBJECT_V1G_SETTINGS_ENTRY_DATA_ENTRY_CHECKSUM 31:24 + +typedef struct INFOROM_OMS_OBJECT_V1G_SETTINGS_ENTRY +{ + inforom_U032 data; + inforom_U032 clockLimitMin; + inforom_U032 clockLimitMax; +} INFOROM_OMS_OBJECT_V1G_SETTINGS_ENTRY; + +#define INFOROM_OMS_OBJECT_V1G_NUM_SETTINGS_ENTRIES 8 + +typedef struct INFOROM_OMS_OBJECT_V1G +{ + INFOROM_OBJECT_HEADER_V1_00 header; + inforom_U032 lifetimeRefreshCount; + INFOROM_OMS_OBJECT_V1G_SETTINGS_ENTRY settings[ + INFOROM_OMS_OBJECT_V1G_NUM_SETTINGS_ENTRIES]; + inforom_U032 reserved; +} INFOROM_OMS_OBJECT_V1G; + +#define INFOROM_OMS_OBJECT_V1G_FMT INFOROM_OBJECT_HEADER_V1_00_FMT "26d" + +#define INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY_DATA_RESERVED 7:2 +#define INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY_DATA_ENTRY_CHECKSUM 15:8 + +typedef struct INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY +{ + inforom_U016 data; +} INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY; + +#define INFOROM_OMS_OBJECT_V1S_NUM_SETTINGS_ENTRIES 50 + +typedef struct INFOROM_OMS_OBJECT_V1S +{ + INFOROM_OBJECT_HEADER_V1_00 header; + inforom_U032 lifetimeRefreshCount; + INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY settings[ + INFOROM_OMS_OBJECT_V1S_NUM_SETTINGS_ENTRIES]; +} INFOROM_OMS_OBJECT_V1S; + +#define INFOROM_OMS_OBJECT_V1S_FMT INFOROM_OBJECT_HEADER_V1_00_FMT "d50w" + +typedef struct INFOROM_OMS_V1S_DATA +{ + INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY *pIter; + INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY prev; + INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY *pNext; +} INFOROM_OMS_V1S_DATA; + +typedef struct INFOROM_OMS_V1G_DATA +{ + INFOROM_OMS_OBJECT_V1G_SETTINGS_ENTRY *pIter; + INFOROM_OMS_OBJECT_V1G_SETTINGS_ENTRY prev; + INFOROM_OMS_OBJECT_V1G_SETTINGS_ENTRY *pNext; +} INFOROM_OMS_V1G_DATA; + +typedef union +{ + INFOROM_OBJECT_HEADER_V1_00 header; + INFOROM_OMS_OBJECT_V1S v1s; + INFOROM_OMS_OBJECT_V1G v1g; +} INFOROM_OMS_OBJECT; + +typedef union +{ + INFOROM_OMS_V1S_DATA v1s; + INFOROM_OMS_V1G_DATA v1g; +} INFOROM_OMS_DATA; + +typedef struct +{ + const char *pFmt; + NvU8 *pPackedObject; + INFOROM_OMS_OBJECT *pOms; + INFOROM_OMS_DATA omsData; +} INFOROM_OMS_STATE; + +#endif /* _INFOROM_OMSDEF_H_ */ diff --git a/userspace/sdks/nv570/nvalloc/common/inc/inforom/types.h b/userspace/sdks/nv570/nvalloc/common/inc/inforom/types.h new file mode 100644 index 0000000..c062cb0 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/inforom/types.h @@ -0,0 +1,79 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _INFOROM_TYPES_H_ +#define _INFOROM_TYPES_H_ + +/*! + * @file types.h + * @brief Common types and definitions used by InfoROM objects + */ + +typedef NvS32 inforom_S008; +typedef NvU32 inforom_U004; +typedef NvU32 inforom_U008; +typedef NvU32 inforom_U016; +typedef NvU32 inforom_U024; +typedef NvU32 inforom_U032; +typedef NvU64 inforom_U064; +typedef NvU8 inforom_X008; + +#define INFOROM_FMT_S08 's' +#define INFOROM_FMT_U04 'n' +#define INFOROM_FMT_U08 'b' +#define INFOROM_FMT_U16 'w' +#define INFOROM_FMT_U24 't' +#define INFOROM_FMT_U32 'd' +#define INFOROM_FMT_U64 'q' +#define INFOROM_FMT_BINARY 'x' + +// Helper macros for generating repeating format sequences +#define INFOROM_FMT_REP02(fmt) fmt fmt +#define INFOROM_FMT_REP04(fmt) INFOROM_FMT_REP02(fmt) INFOROM_FMT_REP02(fmt) +#define INFOROM_FMT_REP08(fmt) INFOROM_FMT_REP04(fmt) INFOROM_FMT_REP04(fmt) +#define INFOROM_FMT_REP16(fmt) INFOROM_FMT_REP08(fmt) INFOROM_FMT_REP08(fmt) +#define INFOROM_FMT_REP32(fmt) INFOROM_FMT_REP16(fmt) INFOROM_FMT_REP16(fmt) +#define INFOROM_FMT_REP64(fmt) INFOROM_FMT_REP32(fmt) INFOROM_FMT_REP32(fmt) +#define INFOROM_FMT_REP128(fmt) INFOROM_FMT_REP64(fmt) INFOROM_FMT_REP64(fmt) +#define INFOROM_FMT_REP256(fmt) INFOROM_FMT_REP128(fmt) INFOROM_FMT_REP128(fmt) +#define INFOROM_FMT_REP512(fmt) INFOROM_FMT_REP256(fmt) INFOROM_FMT_REP256(fmt) + +#define INFOROM_OBJECT_SUBVERSION_SUPPORTS_NVSWITCH(sv) \ + ((((sv) & 0xF0) == 0) || (((sv) & 0xF0) == 0x20)) + +#define INFOROM_OBJECT_HEADER_V1_00_SIZE_OFFSET 0x05 +#define INFOROM_OBJECT_HEADER_V1_00_CHECKSUM_OFFSET 0x07 +#define INFOROM_OBJECT_HEADER_V1_00_PACKED_SIZE 8 + +typedef struct INFOROM_OBJECT_HEADER_V1_00 +{ + inforom_S008 type[3]; + inforom_U008 version; + inforom_U008 subversion; + inforom_U016 size; + inforom_U008 checksum; +} INFOROM_OBJECT_HEADER_V1_00; + +#define INFOROM_OBJECT_HEADER_V1_00_FMT "3s2bwb" + +#endif // _INFOROM_TYPES_H_ diff --git a/userspace/sdks/nv570/nvalloc/common/inc/mctp_format.h b/userspace/sdks/nv570/nvalloc/common/inc/mctp_format.h new file mode 100644 index 0000000..dd2052a --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/mctp_format.h @@ -0,0 +1,120 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef MCTP_FORMAT_H +#define MCTP_FORMAT_H + +/** + * MCTP (Management Component Transport Protocol) format definitions + * + * Based on DMTF DSP0236 - MCTP Base Specification. + * This is a common header that will be used across multiple RM subsystems + * like FSP, GSP, SEC2, etc. for standardized inter-processor communication. + * + * MCTP provides a transport-agnostic protocol for message exchange between + * platform management components. RM uses MCTP's basic transport header + * with vendor-defined message types (NVDM) for internal communication. + */ + +// MCTP Transport Header Fields (First DWORD) +#define MCTP_HEADER_VERSION 3:0 +#define MCTP_HEADER_RSVD 7:4 +#define MCTP_HEADER_DEID 15:8 +#define MCTP_HEADER_SEID 23:16 +#define MCTP_HEADER_TAG 26:24 +#define MCTP_HEADER_TO 27:27 +#define MCTP_HEADER_SEQ 29:28 +#define MCTP_HEADER_EOM 30:30 +#define MCTP_HEADER_SOM 31:31 + +// MCTP Message Header Fields (Second DWORD) +#define MCTP_MSG_HEADER_TYPE 6:0 +#define MCTP_MSG_HEADER_IC 7:7 +#define MCTP_MSG_HEADER_VENDOR_ID 23:8 +#define MCTP_MSG_HEADER_NVDM_TYPE 31:24 + +// MCTP Constants from specification +#define MCTP_MSG_HEADER_TYPE_VENDOR_PCI 0x7e +#define MCTP_MSG_HEADER_VENDOR_ID_NV 0x10de + +/** + * @brief Create MCTP transport header + * + * Generic helper function to construct the MCTP transport header (first DWORD). + * Can be used by any subsystem (FSP, GSP, SEC2, etc.). + * + * Note: TAG and TO fields are set to 0. These are only needed for complex + * scenarios with concurrent interleaved messages or request/response correlation, + * which are not currently used. Header version is hard-coded to 0x1 (MCTP 1.0). + * + * @param[in] som Start of Message flag (1 for first packet) + * @param[in] eom End of Message flag (1 for last packet) + * @param[in] seid Source Endpoint ID + * @param[in] deid Destination Endpoint ID + * @param[in] seq Packet sequence number (0-3, modulo 4) + * + * @return Constructed MCTP transport header (32-bit DWORD) + */ +static NV_INLINE NvU32 +mctpCreateTransportHeader +( + NvU8 som, + NvU8 eom, + NvU8 seid, + NvU8 deid, + NvU8 seq +) +{ + return REF_NUM(MCTP_HEADER_VERSION, 0x1) | + REF_NUM(MCTP_HEADER_SEID, seid) | + REF_NUM(MCTP_HEADER_DEID, deid) | + REF_NUM(MCTP_HEADER_SEQ, seq) | + REF_NUM(MCTP_HEADER_EOM, eom) | + REF_NUM(MCTP_HEADER_SOM, som); +} + +/** + * @brief Create NVDM over MCTP header + * + * Generic helper function to construct the NVDM message header (second DWORD). + * Sets the MCTP message type to Vendor Defined PCI (0x7E) and includes + * NVIDIA's vendor ID (0x10DE) along with the subsystem-specific NVDM type. + * Can be used by any subsystem (FSP, GSP, SEC2, etc.). + * + * @param[in] nvdmType NVDM message type (subsystem/communication-path specific) + * + * @return Constructed NVDM header (32-bit DWORD) + */ +static NV_INLINE NvU32 +mctpCreateNvdmHeader +( + NvU8 nvdmType +) +{ + return REF_DEF(MCTP_MSG_HEADER_TYPE, _VENDOR_PCI) | + REF_NUM(MCTP_MSG_HEADER_IC, 0) | + REF_DEF(MCTP_MSG_HEADER_VENDOR_ID, _NV) | + REF_NUM(MCTP_MSG_HEADER_NVDM_TYPE, nvdmType); +} + +#endif // MCTP_FORMAT_H diff --git a/userspace/sdks/nv570/nvalloc/common/inc/nv-firmware-chip-family-select.h b/userspace/sdks/nv570/nvalloc/common/inc/nv-firmware-chip-family-select.h new file mode 100644 index 0000000..962776a --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/nv-firmware-chip-family-select.h @@ -0,0 +1,230 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NV_FIRMWARE_CHIP_FAMILY_SELECT_H +#define NV_FIRMWARE_CHIP_FAMILY_SELECT_H + + + +#include +#include +#include + +static inline nv_firmware_chip_family_t nv_firmware_get_chip_family( + NvU32 gpuArch, + NvU32 gpuImpl +) +{ + switch (gpuArch) + { + case GPU_ARCHITECTURE_TURING: + if (gpuImpl <= GPU_IMPLEMENTATION_TU106) + return NV_FIRMWARE_CHIP_FAMILY_TU10X; + else + return NV_FIRMWARE_CHIP_FAMILY_TU11X; + + case GPU_ARCHITECTURE_AMPERE: + if (gpuImpl == GPU_IMPLEMENTATION_GA100) + return NV_FIRMWARE_CHIP_FAMILY_GA100; + else + return NV_FIRMWARE_CHIP_FAMILY_GA10X; + + case GPU_ARCHITECTURE_ADA: + return NV_FIRMWARE_CHIP_FAMILY_AD10X; + + case GPU_ARCHITECTURE_HOPPER: + return NV_FIRMWARE_CHIP_FAMILY_GH100; + + case GPU_ARCHITECTURE_BLACKWELL_GB1XX: + if (gpuImpl == GPU_IMPLEMENTATION_GB10B) + return NV_FIRMWARE_CHIP_FAMILY_GB10Y; + else + return NV_FIRMWARE_CHIP_FAMILY_GB10X; + + case GPU_ARCHITECTURE_BLACKWELL_GB2XX: + if (gpuImpl >= GPU_IMPLEMENTATION_GB20B) + return NV_FIRMWARE_CHIP_FAMILY_GB20Y; + else + return NV_FIRMWARE_CHIP_FAMILY_GB20X; + + case GPU_ARCHITECTURE_RUBIN_GR1XX: + return NV_FIRMWARE_CHIP_FAMILY_GR10X; + } + + return NV_FIRMWARE_CHIP_FAMILY_NULL; +} + +typedef enum +{ + NV_FIRMWARE_TASK_INIT, + NV_FIRMWARE_TASK_RM, + NV_FIRMWARE_TASK_INTR, + NV_FIRMWARE_TASK_VGPU, + NV_FIRMWARE_TASK_MNOC, + NV_FIRMWARE_TASK_DEBUG, + NV_FIRMWARE_TASK_ROOT, + NV_FIRMWARE_TASK_RM_STATE_MONITOR, + + NV_FIRMWARE_TASK_COUNT +} nv_firmware_task_t; + +typedef enum { + NV_FIRMWARE_LIBOS_NONE_SUPPORTED = 0x0, + NV_FIRMWARE_LIBOS2_SUPPORTED = 0x1, + NV_FIRMWARE_LIBOS3_SUPPORTED = 0x2, +} libosMappingType; + +typedef struct +{ + const char *memory_id; + const char *prefix; + const char *elf_section_name; + const NvU8 supported_os; // bitmask +} nv_firmware_task_log_info_t; + +static inline +const nv_firmware_task_log_info_t *nv_firmware_get_task_log_infos(unsigned *num_infos) +{ + const static nv_firmware_task_log_info_t infos[] = + { + {"LOGINIT", "INIT", ".fwlogging_init", NV_FIRMWARE_LIBOS2_SUPPORTED | NV_FIRMWARE_LIBOS3_SUPPORTED}, + {"LOGRM", "RM", ".fwlogging_rm", NV_FIRMWARE_LIBOS2_SUPPORTED | NV_FIRMWARE_LIBOS3_SUPPORTED}, + {"LOGINTR", "INTR", ".fwlogging_rm", NV_FIRMWARE_LIBOS3_SUPPORTED}, + {"LOGVGPU", "VGPU", ".fwlogging_vgpu", NV_FIRMWARE_LIBOS2_SUPPORTED | NV_FIRMWARE_LIBOS3_SUPPORTED}, + {"LOGMNOC", "MNOC", ".fwlogging_mnoc", NV_FIRMWARE_LIBOS3_SUPPORTED}, + {"LOGDBG", "DBG", ".fwlogging_debug", NV_FIRMWARE_LIBOS3_SUPPORTED}, + {"LOGROOT", "ROOT", ".fwlogging_start", NV_FIRMWARE_LIBOS3_SUPPORTED}, + {"LOGRMON", "RMON", ".fwlogging_rm", NV_FIRMWARE_LIBOS3_SUPPORTED}, + }; + + *num_infos = NV_ARRAY_ELEMENTS(infos); + ct_assert(NV_ARRAY_ELEMENTS(infos) == NV_FIRMWARE_TASK_COUNT); + + return infos; +} + +static inline +const nv_firmware_task_log_info_t* nv_firmware_log_info_for_task(nv_firmware_task_t task_id) +{ + unsigned num_infos = 0; + const nv_firmware_task_log_info_t* infos = nv_firmware_get_task_log_infos(&num_infos); + + if ((unsigned)task_id >= num_infos) + { + return NULL; + } + + return &infos[task_id]; +} + +typedef struct +{ + const char *elf_section_name; + + struct + { + NvU32 lo, hi; + } gpuArch; + + struct + { + NvU32 lo, hi; + } gpuImpl; +} nv_firmware_kernel_log_info_t; + +#define NV_FIRMWARE_KERNEL_LOG_MEMORY_ID "LOGKRNL" +#define NV_FIRMWARE_KERNEL_LOG_PREFIX "KRNL" +#define NV_FIRMWARE_GPU_ARCH_SHIFT 0x4 + +// +// HAL for selecting .fwlogging section. Chip ID is checked to fall within {gpuArch, gpuImpl}::{lo, hi} +// ranges. Optional gpuImpl range can be used to specify sub-range of an architecture. +// If `hi` is not set, the range is treated as open. Ranges are checked in order of specification. +// Range overlaps are allowed and resolved by the order. +// +static inline +const nv_firmware_kernel_log_info_t *nv_firmware_get_kernel_log_infos(unsigned *num_infos) +{ + const static nv_firmware_kernel_log_info_t infos[] = + { + {".fwlogging_kernel_gr10x", + {GPU_ARCHITECTURE_RUBIN_GR1XX}, // gr10x... + }, + {".fwlogging_kernel_gb20y", + {GPU_ARCHITECTURE_BLACKWELL_GB2XX, GPU_ARCHITECTURE_BLACKWELL_GB2XX}, // gb20y + {GPU_IMPLEMENTATION_GB20B, 0} + }, + {".fwlogging_kernel_gb20x", + {GPU_ARCHITECTURE_BLACKWELL_GB2XX}, // gb20x... + }, + {".fwlogging_kernel_gb10y", + {GPU_ARCHITECTURE_BLACKWELL_GB1XX, GPU_ARCHITECTURE_BLACKWELL_GB1XX}, // gb10y + {GPU_IMPLEMENTATION_GB10B, 0} + }, + + {".fwlogging_kernel_gb10x", + {GPU_ARCHITECTURE_BLACKWELL_GB1XX}, // gb10x... + }, + + {".fwlogging_kernel_gh100", + {GPU_ARCHITECTURE_HOPPER, GPU_ARCHITECTURE_HOPPER}, // gh100 + }, + + {".fwlogging_kernel_ga10x", + {GPU_ARCHITECTURE_AMPERE, GPU_ARCHITECTURE_ADA}, // ga10x...ad10x + }, + }; + + *num_infos = NV_ARRAY_ELEMENTS(infos); + + return infos; +} + +static inline +const nv_firmware_kernel_log_info_t *nv_firmware_kernel_log_info_for_gpu(NvU32 gpuArch, NvU32 gpuImpl) +{ + unsigned num_infos = 0; + const nv_firmware_kernel_log_info_t* infos = nv_firmware_get_kernel_log_infos(&num_infos); + + for (unsigned i = 0; i < num_infos; i++) + { + const nv_firmware_kernel_log_info_t* info = &infos[i]; + + NvBool bMatchingArch = info->gpuArch.lo <= gpuArch; + if (info->gpuArch.hi != 0) + bMatchingArch &= gpuArch <= info->gpuArch.hi; + + NvBool bMatchingImpl = info->gpuImpl.lo <= gpuImpl; + if (info->gpuImpl.hi != 0) + bMatchingImpl &= gpuImpl <= info->gpuImpl.hi; + + if (bMatchingArch && bMatchingImpl) + { + return info; + } + } + + return NULL; +} + +#endif // NV_FIRMWARE_CHIP_FAMILY_SELECT_H diff --git a/userspace/sdks/nv570/nvalloc/common/inc/nv-firmware.h b/userspace/sdks/nv570/nvalloc/common/inc/nv-firmware.h new file mode 100644 index 0000000..000aa38 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/nv-firmware.h @@ -0,0 +1,145 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NV_FIRMWARE_H +#define NV_FIRMWARE_H + + + +#include +#include + +typedef enum +{ + NV_FIRMWARE_TYPE_GSP, + NV_FIRMWARE_TYPE_GSP_LOG, + NV_FIRMWARE_TYPE_UCODES +} nv_firmware_type_t; + +typedef enum +{ + NV_FIRMWARE_CHIP_FAMILY_NULL = 0, + NV_FIRMWARE_CHIP_FAMILY_TU10X = 1, + NV_FIRMWARE_CHIP_FAMILY_TU11X = 2, + NV_FIRMWARE_CHIP_FAMILY_GA100 = 3, + NV_FIRMWARE_CHIP_FAMILY_GA10X = 4, + NV_FIRMWARE_CHIP_FAMILY_AD10X = 5, + NV_FIRMWARE_CHIP_FAMILY_GH100 = 6, + NV_FIRMWARE_CHIP_FAMILY_GB10X = 8, + NV_FIRMWARE_CHIP_FAMILY_GB20X = 9, + NV_FIRMWARE_CHIP_FAMILY_GR10X = 10, + NV_FIRMWARE_CHIP_FAMILY_GB10Y = 11, + NV_FIRMWARE_CHIP_FAMILY_GB20Y = 12, + NV_FIRMWARE_CHIP_FAMILY_END, +} nv_firmware_chip_family_t; + +static inline const char *nv_firmware_chip_family_to_string( + nv_firmware_chip_family_t fw_chip_family +) +{ + switch (fw_chip_family) { + case NV_FIRMWARE_CHIP_FAMILY_GR10X: return "gr10x"; + case NV_FIRMWARE_CHIP_FAMILY_GB10X: return "gb10x"; + case NV_FIRMWARE_CHIP_FAMILY_GB10Y: return "gb10y"; + case NV_FIRMWARE_CHIP_FAMILY_GB20Y: return "gb20y"; + case NV_FIRMWARE_CHIP_FAMILY_GB20X: return "gb20x"; + case NV_FIRMWARE_CHIP_FAMILY_GH100: return "gh100"; + case NV_FIRMWARE_CHIP_FAMILY_AD10X: return "ad10x"; + case NV_FIRMWARE_CHIP_FAMILY_GA10X: return "ga10x"; + case NV_FIRMWARE_CHIP_FAMILY_GA100: return "ga100"; + case NV_FIRMWARE_CHIP_FAMILY_TU11X: return "tu11x"; + case NV_FIRMWARE_CHIP_FAMILY_TU10X: return "tu10x"; + + case NV_FIRMWARE_CHIP_FAMILY_END: // fall through + case NV_FIRMWARE_CHIP_FAMILY_NULL: + return ""; + } + return ""; +} + +// The includer may optionally define +// NV_FIRMWARE_FOR_NAME(name) +// to return a platform-defined string for a given a firmware base name. +// +// The function nv_firmware_for_chip_family will then be available. +#if defined(NV_FIRMWARE_FOR_NAME) +static inline const char *nv_firmware_for_chip_family( + nv_firmware_type_t fw_type, + nv_firmware_chip_family_t fw_chip_family +) +{ + switch (fw_chip_family) + { + case NV_FIRMWARE_CHIP_FAMILY_GR10X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GB10X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GB10Y: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GB20Y: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GB20X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through + case NV_FIRMWARE_CHIP_FAMILY_AD10X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GA10X: + { + switch (fw_type) + { + case NV_FIRMWARE_TYPE_GSP: return NV_FIRMWARE_FOR_NAME("gsp_ga10x"); + case NV_FIRMWARE_TYPE_GSP_LOG: return NV_FIRMWARE_FOR_NAME("gsp_log_ga10x"); + case NV_FIRMWARE_TYPE_UCODES: return NV_FIRMWARE_FOR_NAME("ucodes_ga10x"); + } + return ""; + } + + case NV_FIRMWARE_CHIP_FAMILY_GA100: // fall through + case NV_FIRMWARE_CHIP_FAMILY_TU11X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_TU10X: + { + switch (fw_type) + { + case NV_FIRMWARE_TYPE_GSP: return NV_FIRMWARE_FOR_NAME("gsp_tu10x"); + case NV_FIRMWARE_TYPE_GSP_LOG: return NV_FIRMWARE_FOR_NAME("gsp_log_tu10x"); + case NV_FIRMWARE_TYPE_UCODES: return NV_FIRMWARE_FOR_NAME("ucodes_tu10x"); + } + return ""; + } + + case NV_FIRMWARE_CHIP_FAMILY_END: // fall through + case NV_FIRMWARE_CHIP_FAMILY_NULL: + return ""; + } + + return ""; +} +#endif // defined(NV_FIRMWARE_FOR_NAME) + +// The includer may optionally define +// NV_FIRMWARE_DECLARE_GSP(name) +// which will then be invoked (at the top-level) for each +// gsp_* and ucodes_* (but not gsp_log_*) +#if defined(NV_FIRMWARE_DECLARE_GSP) +NV_FIRMWARE_DECLARE_GSP("gsp_ga10x") +NV_FIRMWARE_DECLARE_GSP("gsp_tu10x") +NV_FIRMWARE_DECLARE_GSP("ucodes_ga10x") +NV_FIRMWARE_DECLARE_GSP("ucodes_tu10x") +#endif // defined(NV_FIRMWARE_DECLARE_GSP) + +#endif // NV_FIRMWARE_DECLARE_GSP + diff --git a/userspace/sdks/nv570/nvalloc/common/inc/nvcst.h b/userspace/sdks/nv570/nvalloc/common/inc/nvcst.h new file mode 100644 index 0000000..1b7239a --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/nvcst.h @@ -0,0 +1,460 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVCST_H +#define NVCST_H + +#include +#include +#include +#include + +#define CHIPSET_SETUP_FUNC(name) static NV_STATUS name(OBJCL *pCl); + +CHIPSET_SETUP_FUNC(Intel_25XX_setupFunc) +CHIPSET_SETUP_FUNC(Intel_27XX_setupFunc) +CHIPSET_SETUP_FUNC(Intel_2A40_setupFunc) +CHIPSET_SETUP_FUNC(Intel_0040_setupFunc) +CHIPSET_SETUP_FUNC(Intel_2E00_setupFunc) +CHIPSET_SETUP_FUNC(Intel_25E0_setupFunc) +CHIPSET_SETUP_FUNC(Intel_29XX_setupFunc) +CHIPSET_SETUP_FUNC(Intel_29X0_setupFunc) +CHIPSET_SETUP_FUNC(Intel_29E0_setupFunc) +CHIPSET_SETUP_FUNC(Intel_359E_setupFunc) +CHIPSET_SETUP_FUNC(Intel_4000_setupFunc) +CHIPSET_SETUP_FUNC(Intel_4003_setupFunc) +CHIPSET_SETUP_FUNC(Intel_3400_setupFunc) +CHIPSET_SETUP_FUNC(Intel_3B42_setupFunc) +CHIPSET_SETUP_FUNC(Intel_1C46_setupFunc) +CHIPSET_SETUP_FUNC(Intel_1C10_setupFunc) +CHIPSET_SETUP_FUNC(Intel_1C4B_setupFunc) +CHIPSET_SETUP_FUNC(Intel_1C49_setupFunc) +CHIPSET_SETUP_FUNC(Intel_1D40_setupFunc) +CHIPSET_SETUP_FUNC(Intel_8D47_setupFunc) +CHIPSET_SETUP_FUNC(Intel_8D44_setupFunc) +CHIPSET_SETUP_FUNC(Intel_1E10_setupFunc) +CHIPSET_SETUP_FUNC(Intel_8C4B_setupFunc) +CHIPSET_SETUP_FUNC(Intel_8CC4_setupFunc) +CHIPSET_SETUP_FUNC(Intel_A145_setupFunc) +CHIPSET_SETUP_FUNC(Intel_A2C5_setupFunc) +CHIPSET_SETUP_FUNC(Intel_A242_setupFunc) +CHIPSET_SETUP_FUNC(Intel_A2D2_setupFunc) +CHIPSET_SETUP_FUNC(Intel_A2C9_setupFunc) +CHIPSET_SETUP_FUNC(Intel_A301_setupFunc) +CHIPSET_SETUP_FUNC(Intel_0685_setupFunc) +CHIPSET_SETUP_FUNC(Intel_4381_setupFunc) +CHIPSET_SETUP_FUNC(Intel_7A82_setupFunc) +CHIPSET_SETUP_FUNC(Intel_7A04_setupFunc) +CHIPSET_SETUP_FUNC(Intel_7D06_setupFunc) +CHIPSET_SETUP_FUNC(SiS_656_setupFunc) +CHIPSET_SETUP_FUNC(ATI_RS400_setupFunc) +CHIPSET_SETUP_FUNC(ATI_RS480_setupFunc) +CHIPSET_SETUP_FUNC(ATI_RD870_setupFunc) +CHIPSET_SETUP_FUNC(ATI_RD890_setupFunc) +CHIPSET_SETUP_FUNC(ATI_RX780_setupFunc) +CHIPSET_SETUP_FUNC(ATI_FX990_setupFunc) +CHIPSET_SETUP_FUNC(AMD_RS780_setupFunc) +CHIPSET_SETUP_FUNC(AMD_FX790_setupFunc) +CHIPSET_SETUP_FUNC(AMD_FX890_setupFunc) +CHIPSET_SETUP_FUNC(AMD_X370_setupFunc) +CHIPSET_SETUP_FUNC(VIA_VX900_setupFunc) +CHIPSET_SETUP_FUNC(APM_Storm_setupFunc) +CHIPSET_SETUP_FUNC(ARMV8_generic_setupFunc) +CHIPSET_SETUP_FUNC(Marvell_ThunderX2_setupFunc) +CHIPSET_SETUP_FUNC(QEMU_setupFunc) +CHIPSET_SETUP_FUNC(Ampere_eMag_setupFunc) +CHIPSET_SETUP_FUNC(Huawei_Kunpeng920_setupFunc) +CHIPSET_SETUP_FUNC(Mellanox_BlueField_setupFunc) +CHIPSET_SETUP_FUNC(Mellanox_BlueField3_setupFunc) +CHIPSET_SETUP_FUNC(Amazon_Gravitron2_setupFunc) +CHIPSET_SETUP_FUNC(Fujitsu_A64FX_setupFunc) +CHIPSET_SETUP_FUNC(Ampere_Altra_setupFunc) +CHIPSET_SETUP_FUNC(Arm_NeoverseN1_setupFunc) +CHIPSET_SETUP_FUNC(Ampere_AmpereOne_setupFunc) +CHIPSET_SETUP_FUNC(Qualcomm_Snapdragon_setupFunc) +CHIPSET_SETUP_FUNC(Nvidia_T210_setupFunc) +CHIPSET_SETUP_FUNC(Nvidia_T194_setupFunc) +CHIPSET_SETUP_FUNC(Nvidia_TH500_setupFunc) +CHIPSET_SETUP_FUNC(PLDA_XpressRichAXI_setupFunc) +CHIPSET_SETUP_FUNC(Riscv_generic_setupFunc) +CHIPSET_SETUP_FUNC(Intel_A70D_setupFunc) +CHIPSET_SETUP_FUNC(AMD_14D8_setupFunc) +CHIPSET_SETUP_FUNC(Nvidia_TB500_setupFunc) + + +// Keep string length <=32 (including termination) to avoid string copy overflow +CSINFO chipsetInfo[] = +{ + // PCI Express chipset + + {PCI_VENDOR_ID_INTEL, 0x2580, CS_INTEL_2580, "Grantsdale", Intel_25XX_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x2584, CS_INTEL_2584, "Alderwood", Intel_25XX_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x2588, CS_INTEL_2588, "Intel2588", Intel_25XX_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x2590, CS_INTEL_2590, "Alviso", Intel_25XX_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x25C0, CS_INTEL_25E0, "Greencreek", Intel_25E0_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x25E0, CS_INTEL_25E0, "Greencreek", Intel_25E0_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x29B0, CS_INTEL_29X0, "IntelQ35", Intel_29X0_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x29C0, CS_INTEL_29X0, "BearlakeB", Intel_29X0_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x29D0, CS_INTEL_29X0, "IntelQ33", Intel_29X0_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x29E0, CS_INTEL_29E0, "BearlakeX", Intel_29E0_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x359E, CS_INTEL_359E, "Tumwater", Intel_359E_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x4000, CS_INTEL_4000, "Stoakley", Intel_4000_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x4003, CS_INTEL_4003, "SkullTrail", Intel_4003_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x3400, CS_INTEL_3400, "IntelX58", Intel_3400_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x3403, CS_INTEL_3400, "IntelX58", Intel_3400_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x3405, CS_INTEL_3400, "IntelX58", Intel_3400_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x3406, CS_INTEL_3400, "Tylersburg", Intel_3400_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x2770, CS_INTEL_2770, "Lakeport", Intel_25XX_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x2774, CS_INTEL_2774, "Glenwood", Intel_27XX_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x277C, CS_INTEL_277C, "Glenwood", Intel_27XX_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x2A40, CS_INTEL_2A40, "Montevina", Intel_2A40_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x2E00, CS_INTEL_2E00, "Eaglelake", Intel_2E00_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x2E10, CS_INTEL_2E00, "Eaglelake", Intel_2E00_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x2E20, CS_INTEL_2E00, "Eaglelake", Intel_2E00_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x2E30, CS_INTEL_2E00, "Eaglelake", Intel_2E00_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x0044, CS_INTEL_0040, "Arrandale/Auburndale", Intel_0040_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x0062, CS_INTEL_0040, "Arrandale/Auburndale", Intel_0040_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xD130, CS_INTEL_3B42, "Clarksfield", Intel_3B42_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xD132, CS_INTEL_3B42, "Clarksfield", Intel_3B42_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x3B42, CS_INTEL_3B42, "P55/PM55/H57", Intel_3B42_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x1C46, CS_INTEL_1C46, "IntelP67-CougarPoint", Intel_1C46_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x1C4B, CS_INTEL_1C46, "HuronRiver-HM67", Intel_1C4B_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x1C4F, CS_INTEL_1C46, "HuronRiver-QM67", Intel_1C4B_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x1C49, CS_INTEL_1C49, "HuronRiver-HM65", Intel_1C49_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x1C44, CS_INTEL_1C46, "IntelZ68", Intel_1C46_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x1C10, CS_INTEL_1C10, "IntelP67", Intel_1C10_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x1D40, CS_INTEL_1D40, "IntelX79", Intel_1D40_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x1D41, CS_INTEL_1D40, "IntelX79", Intel_1D40_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x1E10, CS_INTEL_1E10, "IntelZ75", Intel_1E10_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x0150, CS_INTEL_1E10, "IntelZ77A-GD55", Intel_1E10_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x0151, CS_INTEL_1E10, "IntelZ77A-GD55", Intel_1E10_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x0100, CS_INTEL_1E10, "IntelZ77A-GD55", Intel_1E10_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x8C4B, CS_INTEL_8C4B, "SharkBay-HM87", Intel_8C4B_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x8C44, CS_INTEL_8C4B, "SharkBay-Z87", Intel_8C4B_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x8C41, CS_INTEL_8C4B, "SharkBay-H8x/P8x", Intel_8C4B_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x8C49, CS_INTEL_8C4B, "SharkBay-HM86", Intel_8C4B_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x8C52, CS_INTEL_8C4B, "SharkBay-E3", Intel_8C4B_setupFunc}, // Does not support SLI + {PCI_VENDOR_ID_INTEL, 0x8CC4, CS_INTEL_8CC4, "IntelZ97", Intel_8CC4_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x8CC3, CS_INTEL_8CC4, "IntelHM97", Intel_8CC4_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA145, CS_INTEL_A145, "IntelZ170", Intel_A145_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA14E, CS_INTEL_A145, "IntelHM170", Intel_A145_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA150, CS_INTEL_A145, "IntelHM170", Intel_A145_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA149, CS_INTEL_A145, "SkyLake C236", Intel_A145_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA14A, CS_INTEL_A145, "SkyLake C232", Intel_A145_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA14D, CS_INTEL_A145, "SkyLake-H", Intel_A145_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA244, CS_INTEL_A145, "SkyLake C620", Intel_A145_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA1C8, CS_INTEL_A145, "SkyLake C620", Intel_A145_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x8D47, CS_INTEL_8D47, "IntelX99", Intel_8D47_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x8D44, CS_INTEL_8D47, "IntelC612", Intel_8D44_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA2C5, CS_INTEL_A2C5, "IntelZ270", Intel_A2C5_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA154, CS_INTEL_A2C5, "IntelZ270", Intel_A2C5_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA152, CS_INTEL_A2C5, "IntelRX9S", Intel_A2C5_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA242, CS_INTEL_A242, "IntelC422", Intel_A242_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA241, CS_INTEL_A242, "IntelC422", Intel_A242_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA243, CS_INTEL_A242, "IntelC422", Intel_A242_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA2D2, CS_INTEL_A2D2, "IntelX299", Intel_A2D2_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA2D3, CS_INTEL_A242, "IntelC422", Intel_A242_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA1C1, CS_INTEL_A242, "IntelC621", Intel_A242_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA1C2, CS_INTEL_A242, "IntelC622", Intel_A242_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA1C3, CS_INTEL_A242, "IntelC624", Intel_A242_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA1C4, CS_INTEL_A242, "IntelC625", Intel_A242_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA1C5, CS_INTEL_A242, "IntelC626", Intel_A242_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA1C6, CS_INTEL_A242, "IntelC627", Intel_A242_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA1C7, CS_INTEL_A242, "IntelC628", Intel_A242_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA2C9, CS_INTEL_A2C9, "IntelZ370", Intel_A2C9_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA310, CS_INTEL_A2C9, "IntelZ370", Intel_A2C9_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA30E, CS_INTEL_A2C9, "IntelZ370", Intel_A2C9_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA305, CS_INTEL_A2C9, "IntelZ390", Intel_A2C9_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA30D, CS_INTEL_A2C9, "IntelH370", Intel_A2C9_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA301, CS_INTEL_A301, "Intel-CannonLake", Intel_A301_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x0685, CS_INTEL_0685, "Intel-CometLake", Intel_0685_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA1CB, CS_INTEL_C620, "Intel-IceLake", NULL}, + {PCI_VENDOR_ID_INTEL, 0x4381, CS_INTEL_4381, "Intel-RocketLake", Intel_4381_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x4385, CS_INTEL_4381, "Intel-RocketLake", Intel_4381_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x7A82, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x7A84, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x1B81, CS_INTEL_1B81, "Intel-SapphireRapids", NULL}, + {PCI_VENDOR_ID_INTEL, 0x7A8A, CS_INTEL_1B81, "Intel-SapphireRapids", NULL}, + {PCI_VENDOR_ID_INTEL, 0x18DC, CS_INTEL_18DC, "Intel-IceLake", NULL}, + {PCI_VENDOR_ID_INTEL, 0x7A04, CS_INTEL_7A04, "Intel-RaptorLake", Intel_7A04_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x5795, CS_INTEL_5795, "Intel-GraniteRapids", NULL}, + {PCI_VENDOR_ID_INTEL, 0xA70D, CS_INTEL_B660, "Intel-B660", Intel_A70D_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x7D06, CS_INTEL_7D06, "Intel-Arrowlake", Intel_7D06_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x7D1A, CS_INTEL_7D06, "Intel-Arrowlake", Intel_7D06_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x7D1B, CS_INTEL_7D06, "Intel-Arrowlake", Intel_7D06_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x7D1C, CS_INTEL_7D06, "Intel-Arrowlake", Intel_7D06_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x7D2A, CS_INTEL_7D06, "Intel-Arrowlake", Intel_7D06_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x7D2D, CS_INTEL_7D06, "Intel-Arrowlake", Intel_7D06_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x7D2E, CS_INTEL_7D06, "Intel-Arrowlake", Intel_7D06_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x7D2F, CS_INTEL_7D06, "Intel-Arrowlake", Intel_7D06_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x7D35, CS_INTEL_7D06, "Intel-Arrowlake", Intel_7D06_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x7D67, CS_INTEL_7D06, "Intel-Arrowlake", Intel_7D06_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x7D30, CS_INTEL_7D06, "Intel-Arrowlake", Intel_7D06_setupFunc}, + + {PCI_VENDOR_ID_NVIDIA, 0x0FAE, CS_NVIDIA_T210, "T210", Nvidia_T210_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x0FAF, CS_NVIDIA_T210, "T210", Nvidia_T210_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x10E5, CS_NVIDIA_T186, "T186", Nvidia_T210_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x10E6, CS_NVIDIA_T186, "T186", Nvidia_T210_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x1AD0, CS_NVIDIA_T194, "T194", Nvidia_T194_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x1AD1, CS_NVIDIA_T194, "T194", Nvidia_T194_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x1AD2, CS_NVIDIA_T194, "T194", Nvidia_T194_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x229A, CS_NVIDIA_T234, "T234", Nvidia_T194_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x229C, CS_NVIDIA_T234, "T234", Nvidia_T194_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x229E, CS_NVIDIA_T234, "T234", Nvidia_T194_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22C2, CS_NVIDIA_T23x, "T23x", Nvidia_T194_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22C3, CS_NVIDIA_T23x, "T23x", Nvidia_T194_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22B1, CS_NVIDIA_TH500, "TH500", Nvidia_TH500_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22B2, CS_NVIDIA_TH500, "TH500", Nvidia_TH500_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22B3, CS_NVIDIA_TH500, "TH500", Nvidia_TH500_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22B4, CS_NVIDIA_TH500, "TH500", Nvidia_TH500_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22B8, CS_NVIDIA_TH500, "TH500", Nvidia_TH500_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22B9, CS_NVIDIA_TH500, "TH500", Nvidia_TH500_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22D6, CS_NVIDIA_T264, "T264", Nvidia_T194_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22D8, CS_NVIDIA_T264, "T264", Nvidia_T194_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22DA, CS_NVIDIA_T264, "T264", Nvidia_T194_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x2B00, CS_NVIDIA_T264, "T264", Nvidia_T194_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x2F95, CS_NVIDIA_TB500, "TB500", Nvidia_TB500_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x2F96, CS_NVIDIA_TB500, "TB500", Nvidia_TB500_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x2F97, CS_NVIDIA_TB500, "TB500", Nvidia_TB500_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x2F98, CS_NVIDIA_TB500, "TB500", Nvidia_TB500_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x2F99, CS_NVIDIA_TB500, "TB500", Nvidia_TB500_setupFunc}, + + {PCI_VENDOR_ID_SIS, 0x0649, CS_SIS_649, "649", SiS_656_setupFunc}, + {PCI_VENDOR_ID_SIS, 0x0656, CS_SIS_656, "656", SiS_656_setupFunc}, + + {PCI_VENDOR_ID_ATI, 0x5A31, CS_ATI_RS400, "RS400", ATI_RS400_setupFunc}, + {PCI_VENDOR_ID_ATI, 0x5A33, CS_ATI_RS400, "RS400", ATI_RS400_setupFunc}, + {PCI_VENDOR_ID_ATI, 0x5950, CS_ATI_RS480, "RS480", ATI_RS480_setupFunc}, + {PCI_VENDOR_ID_ATI, 0x5951, CS_ATI_RS480, "RS480", ATI_RS480_setupFunc}, + {PCI_VENDOR_ID_ATI, 0x5956, CS_ATI_FX790, "FX790" ,AMD_FX790_setupFunc}, + {PCI_VENDOR_ID_ATI, 0x5A11, CS_ATI_FX890, "FX890" ,AMD_FX890_setupFunc}, + {PCI_VENDOR_ID_ATI, 0x5a13, CS_ATI_RD850, "RD850" ,ATI_RD870_setupFunc}, + {PCI_VENDOR_ID_ATI, 0x5a12, CS_ATI_RD870, "RD870" ,ATI_RD870_setupFunc}, + {PCI_VENDOR_ID_ATI, 0x5a10, CS_ATI_RD890, "RD890" ,ATI_RD890_setupFunc}, + {PCI_VENDOR_ID_ATI, 0x5957, CS_ATI_RX780, "RX780" ,ATI_RX780_setupFunc}, + {PCI_VENDOR_ID_ATI, 0x5A14, CS_ATI_FX990, "FX990/X990/970",ATI_FX990_setupFunc}, + + {PCI_VENDOR_ID_AMD, 0x9601, CS_AMD_GX890, "GX890" ,AMD_FX890_setupFunc}, + {PCI_VENDOR_ID_AMD, 0x9600, CS_AMD_RS780, "RS780" ,AMD_RS780_setupFunc}, + {PCI_VENDOR_ID_AMD, 0x790e, CS_AMD_X370, "X370/X399/X470/ TRX40/X570/WRX80", AMD_X370_setupFunc }, + {PCI_VENDOR_ID_AMD, 0x14d8, CS_AMD_RPH, "AMD-Raphael", AMD_14D8_setupFunc}, + + {PCI_VENDOR_ID_VIA, 0x0308, CS_VIA_VT8369B, "VT8369B", NULL}, + {PCI_VENDOR_ID_VIA, 0x0410, CS_VIA_VX900, "VX900", VIA_VX900_setupFunc}, + {PCI_VENDOR_ID_APM, 0xe004, CS_APM_STORM, "X-Gene Storm", APM_Storm_setupFunc}, + {PCI_VENDOR_ID_IBM, 0x03DC, CS_IBM_VENICE, "Venice", NULL}, + {PCI_VENDOR_ID_MARVELL, 0xAF00, CS_MARVELL_THUNDERX2, "Marvell ThunderX2", Marvell_ThunderX2_setupFunc}, + {PCI_VENDOR_ID_REDHAT, 0x0008, CS_REDHAT_QEMU, "QEMU Redhat", QEMU_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE005, CS_AMPERE_EMAG, "AMPERE eMag", Ampere_eMag_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE006, CS_AMPERE_EMAG, "AMPERE eMag", Ampere_eMag_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE007, CS_AMPERE_EMAG, "AMPERE eMag", Ampere_eMag_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE008, CS_AMPERE_EMAG, "AMPERE eMag", Ampere_eMag_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE009, CS_AMPERE_EMAG, "AMPERE eMag", Ampere_eMag_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE00A, CS_AMPERE_EMAG, "AMPERE eMag", Ampere_eMag_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE00B, CS_AMPERE_EMAG, "AMPERE eMag", Ampere_eMag_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE00C, CS_AMPERE_EMAG, "AMPERE eMag", Ampere_eMag_setupFunc}, + {PCI_VENDOR_ID_HUAWEI, 0xA120, CS_HUAWEI_KUNPENG920, "Huawei Kunpeng920", Huawei_Kunpeng920_setupFunc}, + {PCI_VENDOR_ID_MELLANOX, 0xA2D0, CS_MELLANOX_BLUEFIELD, "Mellanox BlueField", Mellanox_BlueField_setupFunc}, + {PCI_VENDOR_ID_MELLANOX, 0xA2D4, CS_MELLANOX_BLUEFIELD2, "Mellanox BlueField 2", NULL}, + {PCI_VENDOR_ID_MELLANOX, 0xA2D5, CS_MELLANOX_BLUEFIELD2, "Mellanox BlueField 2 Crypto disabled", NULL}, + {PCI_VENDOR_ID_MELLANOX, 0xA2DA, CS_MELLANOX_BLUEFIELD3, "Mellanox BlueField 3 Crypto enabled", Mellanox_BlueField3_setupFunc}, + {PCI_VENDOR_ID_MELLANOX, 0xA2DB, CS_MELLANOX_BLUEFIELD3, "Mellanox BlueField 3 Crypto disabled", Mellanox_BlueField3_setupFunc}, + {PCI_VENDOR_ID_AMAZON, 0x0200, CS_AMAZON_GRAVITRON2, "Amazon Gravitron2", Amazon_Gravitron2_setupFunc}, + {PCI_VENDOR_ID_FUJITSU, 0x1952, CS_FUJITSU_A64FX, "Fujitsu A64FX", Fujitsu_A64FX_setupFunc}, + {PCI_VENDOR_ID_CADENCE, 0xDC01, CS_PHYTIUM_S2500, "Phytium S2500", NULL}, + {PCI_VENDOR_ID_CADENCE, 0xDC08, CS_PHYTIUM_S2500, "Phytium S2500", NULL}, + {PCI_VENDOR_ID_CADENCE, 0xDC16, CS_PHYTIUM_S2500, "Phytium S2500", NULL}, + {PCI_VENDOR_ID_CADENCE, 0xFC01, CS_PHYTIUM_S2500, "Phytium S2500", NULL}, + {PCI_VENDOR_ID_CADENCE, 0xFC08, CS_PHYTIUM_S2500, "Phytium S2500", NULL}, + {PCI_VENDOR_ID_CADENCE, 0xFC16, CS_PHYTIUM_S2500, "Phytium S2500", NULL}, + {PCI_VENDOR_ID_AMPERE, 0xE000, CS_AMPERE_ALTRA, "Ampere Altra", Ampere_Altra_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE00D, CS_AMPERE_ALTRA, "Ampere Altra", Ampere_Altra_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE00E, CS_AMPERE_ALTRA, "Ampere Altra", Ampere_Altra_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE010, CS_AMPERE_ALTRA, "Ampere Altra", Ampere_Altra_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE100, CS_AMPERE_ALTRA, "Ampere Altra", Ampere_Altra_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE110, CS_AMPERE_ALTRA, "Ampere Altra", Ampere_Altra_setupFunc}, + {PCI_VENDOR_ID_ARM, 0x0100, CS_ARM_NEOVERSEN1, "Arm Neoverse N1", Arm_NeoverseN1_setupFunc}, + {PCI_VENDOR_ID_HYGON, 0x790E, CS_HYGON_C86, "Hygon-C86-7151", NULL}, + {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN96XX, "Marvell Octeon CN96xx", ARMV8_generic_setupFunc}, + {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN98XX, "Marvell Octeon CN98xx", ARMV8_generic_setupFunc}, + {PCI_VENDOR_ID_QUALCOMM, 0x010E, CS_SNAPDRAGON_8CX, "Qualcomm Snapdragon 8cx Gen3", Qualcomm_Snapdragon_setupFunc}, + {PCI_VENDOR_ID_QUALCOMM, 0x0111, CS_SNAPDRAGON_8CX, "Qualcomm Snapdragon 8cx Gen4", Qualcomm_Snapdragon_setupFunc}, + {PCI_VENDOR_ID_SIFIVE, 0x0000, CS_SIFIVE_FU740_C000, "SiFive FU740-000", Riscv_generic_setupFunc}, + {PCI_VENDOR_ID_PLDA, 0x1111, CS_PLDA_XPRESSRICH_AXI_REF, "XpressRich-AXI Ref Design", PLDA_XpressRichAXI_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE200, CS_AMPERE_AMPEREONE160, "Ampere AmpereOne-160", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE201, CS_AMPERE_AMPEREONE160, "Ampere AmpereOne-160", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE202, CS_AMPERE_AMPEREONE160, "Ampere AmpereOne-160", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE203, CS_AMPERE_AMPEREONE160, "Ampere AmpereOne-160", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE204, CS_AMPERE_AMPEREONE160, "Ampere AmpereOne-160", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE205, CS_AMPERE_AMPEREONE160, "Ampere AmpereOne-160", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE206, CS_AMPERE_AMPEREONE160, "Ampere AmpereOne-160", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE207, CS_AMPERE_AMPEREONE160, "Ampere AmpereOne-160", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_PHYTIUM, 0x5C16, CS_PHYTIUM_S5000, "Phytium S5000", NULL}, + {PCI_VENDOR_ID_AMPERE, 0xE208, CS_AMPERE_AMPEREONE192, "Ampere AmpereOne-192", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE209, CS_AMPERE_AMPEREONE192, "Ampere AmpereOne-192", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE20A, CS_AMPERE_AMPEREONE192, "Ampere AmpereOne-192", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE20B, CS_AMPERE_AMPEREONE192, "Ampere AmpereOne-192", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE20C, CS_AMPERE_AMPEREONE192, "Ampere AmpereOne-192", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE20D, CS_AMPERE_AMPEREONE192, "Ampere AmpereOne-192", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE20E, CS_AMPERE_AMPEREONE192, "Ampere AmpereOne-192", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE20F, CS_AMPERE_AMPEREONE192, "Ampere AmpereOne-192", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22D1, CS_NVIDIA_T254, "T254", Nvidia_T194_setupFunc}, + +/////////////////////////////////////////////////////////////////////////////////////////////////// + + // last element must have chipset CS_UNKNOWN (zero) + {0, 0, CS_UNKNOWN, "Unknown", NULL} +}; + + +VENDORNAME vendorName[] = +{ + {PCI_VENDOR_ID_NVIDIA, "NVIDIA"}, + {PCI_VENDOR_ID_INTEL, "Intel"}, + {PCI_VENDOR_ID_VIA, "VIA"}, + {PCI_VENDOR_ID_RCC, "ServerWorks"}, + {PCI_VENDOR_ID_MICRON_1, "Micron"}, + {PCI_VENDOR_ID_MICRON_2, "Micron"}, + {PCI_VENDOR_ID_APPLE, "Apple"}, + {PCI_VENDOR_ID_SIS, "SiS"}, + {PCI_VENDOR_ID_ATI, "ATI"}, + {PCI_VENDOR_ID_TRANSMETA, "Transmeta"}, + {PCI_VENDOR_ID_HP, "HP"}, + {PCI_VENDOR_ID_AMD, "AMD"}, + {PCI_VENDOR_ID_ALI, "ALi"}, + {PCI_VENDOR_ID_APM, "AppliedMicro"}, + {PCI_VENDOR_ID_IBM, "IBM"}, + {PCI_VENDOR_ID_MARVELL, "MarvellThunderX2"}, + {PCI_VENDOR_ID_REDHAT, "QemuRedhat"}, + {PCI_VENDOR_ID_AMPERE, "AmpereComputing"}, + {PCI_VENDOR_ID_HUAWEI, "Huawei"}, + {PCI_VENDOR_ID_MELLANOX, "Mellanox"}, + {PCI_VENDOR_ID_AMAZON, "Amazon"}, + {PCI_VENDOR_ID_FUJITSU, "Fujitsu"}, + {PCI_VENDOR_ID_CADENCE, "Cadence"}, + {PCI_VENDOR_ID_ARM, "ARM"}, + {PCI_VENDOR_ID_ALIBABA, "Alibaba"}, + {PCI_VENDOR_ID_QUALCOMM, "Qualcomm"}, + {PCI_VENDOR_ID_SIFIVE, "SiFive"}, + {PCI_VENDOR_ID_PLDA, "PLDA"}, + {PCI_VENDOR_ID_PHYTIUM, "Phytium"}, + {0, "Unknown"} // Indicates end of the table +}; + + +// +// Allowlist all chipsets with which dGPU over PCIe is supported on ARM +// (both v7 and v8) platforms. Also include IGPU specific chipsets. +// +ARMCSALLOWLISTINFO armChipsetAllowListInfo[] = +{ + {PCI_VENDOR_ID_NVIDIA, 0x0FAE, CS_NVIDIA_T210}, // NVIDIA Tegra X1 RP0 + {PCI_VENDOR_ID_NVIDIA, 0x0FAF, CS_NVIDIA_T210}, // NVIDIA Tegra X1 RP1 + {PCI_VENDOR_ID_NVIDIA, 0x10E5, CS_NVIDIA_T186}, // NVIDIA Tegra P1 RP0 + {PCI_VENDOR_ID_NVIDIA, 0x10E6, CS_NVIDIA_T186}, // NVIDIA Tegra P1 RP1 + {PCI_VENDOR_ID_NVIDIA, 0x1AD0, CS_NVIDIA_T194}, // NVIDIA Tegra V1 RP0 + {PCI_VENDOR_ID_NVIDIA, 0x1AD1, CS_NVIDIA_T194}, // NVIDIA Tegra V1 RP1 + {PCI_VENDOR_ID_NVIDIA, 0x1AD2, CS_NVIDIA_T194}, // NVIDIA Tegra V1 RP2 + {PCI_VENDOR_ID_NVIDIA, 0x229A, CS_NVIDIA_T234}, // NVIDIA Tegra Orin RP0 + {PCI_VENDOR_ID_NVIDIA, 0x229C, CS_NVIDIA_T234}, // NVIDIA Tegra Orin RP1 + {PCI_VENDOR_ID_NVIDIA, 0x229E, CS_NVIDIA_T234}, // NVIDIA Tegra Orin RP2 + {PCI_VENDOR_ID_NVIDIA, 0x22C2, CS_NVIDIA_T23x}, // NVIDIA Tegra RP0 + {PCI_VENDOR_ID_NVIDIA, 0x22C3, CS_NVIDIA_T23x}, // NVIDIA Tegra RP1 + {PCI_VENDOR_ID_NVIDIA, 0x22B1, CS_NVIDIA_TH500}, // NVIDIA TH500 RP for GH100 GPU in GH180. + {PCI_VENDOR_ID_NVIDIA, 0x22B2, CS_NVIDIA_TH500}, // NVIDIA TH500 RP x16 + {PCI_VENDOR_ID_NVIDIA, 0x22B3, CS_NVIDIA_TH500}, // NVIDIA TH500 RP x4 + {PCI_VENDOR_ID_NVIDIA, 0x22B4, CS_NVIDIA_TH500}, // NVIDIA TH500 RP x1 + {PCI_VENDOR_ID_NVIDIA, 0x22B8, CS_NVIDIA_TH500}, // NVIDIA TH500 RP x8 + {PCI_VENDOR_ID_NVIDIA, 0x22B9, CS_NVIDIA_TH500}, // NVIDIA TH500 RP x2 + {PCI_VENDOR_ID_NVIDIA, 0x22D6, CS_NVIDIA_T264}, // NVIDIA Tegra RP x8 + {PCI_VENDOR_ID_NVIDIA, 0x22D8, CS_NVIDIA_T264}, // NVIDIA Tegra RP x4 + {PCI_VENDOR_ID_NVIDIA, 0x22DA, CS_NVIDIA_T264}, // NVIDIA Tegra RP x2 + {PCI_VENDOR_ID_NVIDIA, 0x22E6, CS_NVIDIA_T264}, // NVIDIA Tegra iGPU RP + {PCI_VENDOR_ID_NVIDIA, 0x2B00, CS_NVIDIA_T264}, // NVIDIA Tegra iGPU + {PCI_VENDOR_ID_NVIDIA, 0x2F95, CS_NVIDIA_TB500}, // NVIDIA TB500 RP x16 + {PCI_VENDOR_ID_NVIDIA, 0x2F96, CS_NVIDIA_TB500}, // NVIDIA TB500 RP x8 + {PCI_VENDOR_ID_NVIDIA, 0x2F97, CS_NVIDIA_TB500}, // NVIDIA TB500 RP x4 + {PCI_VENDOR_ID_NVIDIA, 0x2F98, CS_NVIDIA_TB500}, // NVIDIA TB500 RP x2 + {PCI_VENDOR_ID_NVIDIA, 0x2F99, CS_NVIDIA_TB500}, // NVIDIA TB500 RP x1 + + {PCI_VENDOR_ID_APM, 0xe004, CS_APM_STORM}, // Applied Micro X-Gene "Storm" + {PCI_VENDOR_ID_MARVELL, 0xAF00, CS_MARVELL_THUNDERX2}, // Marvell ThunderX2 + {PCI_VENDOR_ID_REDHAT, 0x0008, CS_REDHAT_QEMU}, // Redhat QEMU + {PCI_VENDOR_ID_AMPERE, 0xE005, CS_AMPERE_EMAG}, // Ampere eMag + {PCI_VENDOR_ID_AMPERE, 0xE006, CS_AMPERE_EMAG}, // Ampere eMag + {PCI_VENDOR_ID_AMPERE, 0xE007, CS_AMPERE_EMAG}, // Ampere eMag + {PCI_VENDOR_ID_AMPERE, 0xE008, CS_AMPERE_EMAG}, // Ampere eMag + {PCI_VENDOR_ID_AMPERE, 0xE009, CS_AMPERE_EMAG}, // Ampere eMag + {PCI_VENDOR_ID_AMPERE, 0xE00A, CS_AMPERE_EMAG}, // Ampere eMag + {PCI_VENDOR_ID_AMPERE, 0xE00B, CS_AMPERE_EMAG}, // Ampere eMag + {PCI_VENDOR_ID_AMPERE, 0xE00C, CS_AMPERE_EMAG}, // Ampere eMag + {PCI_VENDOR_ID_HUAWEI, 0xA120, CS_HUAWEI_KUNPENG920}, // Huawei Kunpeng 920 + {PCI_VENDOR_ID_MELLANOX, 0xA2D0, CS_MELLANOX_BLUEFIELD}, // Mellanox BlueField + {PCI_VENDOR_ID_MELLANOX, 0xA2D4, CS_MELLANOX_BLUEFIELD2},// Mellanox BlueField 2 + {PCI_VENDOR_ID_MELLANOX, 0xA2D5, CS_MELLANOX_BLUEFIELD2},// Mellanox BlueField 2 Crypto disabled + {PCI_VENDOR_ID_MELLANOX, 0xA2DB, CS_MELLANOX_BLUEFIELD3},// Mellanox BlueField 3 Crypto disabled + {PCI_VENDOR_ID_MELLANOX, 0xA2DA, CS_MELLANOX_BLUEFIELD3},// Mellanox BlueField 3 Crypto enabled + {PCI_VENDOR_ID_AMAZON, 0x0200, CS_AMAZON_GRAVITRON2}, // Amazon Gravitron2 + {PCI_VENDOR_ID_FUJITSU, 0x1952, CS_FUJITSU_A64FX}, // Fujitsu A64FX + {PCI_VENDOR_ID_CADENCE, 0xDC01, CS_PHYTIUM_S2500}, // Phytium S2500 + {PCI_VENDOR_ID_CADENCE, 0xDC08, CS_PHYTIUM_S2500}, // Phytium S2500 + {PCI_VENDOR_ID_CADENCE, 0xDC16, CS_PHYTIUM_S2500}, // Phytium S2500 + {PCI_VENDOR_ID_CADENCE, 0xFC01, CS_PHYTIUM_S2500}, // Phytium S2500 + {PCI_VENDOR_ID_CADENCE, 0xFC08, CS_PHYTIUM_S2500}, // Phytium S2500 + {PCI_VENDOR_ID_CADENCE, 0xFC16, CS_PHYTIUM_S2500}, // Phytium S2500 + {PCI_VENDOR_ID_AMPERE, 0xE000, CS_AMPERE_ALTRA}, // Ampere Altra + {PCI_VENDOR_ID_AMPERE, 0xE00D, CS_AMPERE_ALTRA}, // Ampere Altra + {PCI_VENDOR_ID_AMPERE, 0xE00E, CS_AMPERE_ALTRA}, // Ampere Altra + {PCI_VENDOR_ID_AMPERE, 0xE010, CS_AMPERE_ALTRA}, // Ampere Altra + {PCI_VENDOR_ID_AMPERE, 0xE100, CS_AMPERE_ALTRA}, // Ampere Altra + {PCI_VENDOR_ID_AMPERE, 0xE110, CS_AMPERE_ALTRA}, // Ampere Altra + {PCI_VENDOR_ID_ARM, 0x0100, CS_ARM_NEOVERSEN1}, // Arm Neoverse N1 + {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN96XX}, // Marvell OCTEON CN96xx + {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN98XX}, // Marvell OCTEON CN98xx + {PCI_VENDOR_ID_ALIBABA, 0x8000, CS_ALIBABA_YITIAN}, // Alibaba Yitian + {PCI_VENDOR_ID_QUALCOMM, 0x010E, CS_SNAPDRAGON_8CX}, // Qualcomm Snapdragon 8cx Gen3 - 8280 dev platform + {PCI_VENDOR_ID_QUALCOMM, 0x0111, CS_SNAPDRAGON_8CX}, // Qualcomm Snapdragon 8cx Gen4 - 8380 dev(?) platform + {PCI_VENDOR_ID_AMPERE, 0xE200, CS_AMPERE_AMPEREONE160}, // Ampere AmpereOne-160 + {PCI_VENDOR_ID_AMPERE, 0xE201, CS_AMPERE_AMPEREONE160}, // Ampere AmpereOne-160 + {PCI_VENDOR_ID_AMPERE, 0xE202, CS_AMPERE_AMPEREONE160}, // Ampere AmpereOne-160 + {PCI_VENDOR_ID_AMPERE, 0xE203, CS_AMPERE_AMPEREONE160}, // Ampere AmpereOne-160 + {PCI_VENDOR_ID_AMPERE, 0xE204, CS_AMPERE_AMPEREONE160}, // Ampere AmpereOne-160 + {PCI_VENDOR_ID_AMPERE, 0xE205, CS_AMPERE_AMPEREONE160}, // Ampere AmpereOne-160 + {PCI_VENDOR_ID_AMPERE, 0xE206, CS_AMPERE_AMPEREONE160}, // Ampere AmpereOne-160 + {PCI_VENDOR_ID_AMPERE, 0xE207, CS_AMPERE_AMPEREONE160}, // Ampere AmpereOne-160 + {PCI_VENDOR_ID_PHYTIUM, 0x5C16, CS_PHYTIUM_S5000}, // Phytium S5000 + {PCI_VENDOR_ID_AMPERE, 0xE208, CS_AMPERE_AMPEREONE192}, // Ampere AmpereOne-192 + {PCI_VENDOR_ID_AMPERE, 0xE209, CS_AMPERE_AMPEREONE192}, // Ampere AmpereOne-192 + {PCI_VENDOR_ID_AMPERE, 0xE20A, CS_AMPERE_AMPEREONE192}, // Ampere AmpereOne-192 + {PCI_VENDOR_ID_AMPERE, 0xE20B, CS_AMPERE_AMPEREONE192}, // Ampere AmpereOne-192 + {PCI_VENDOR_ID_AMPERE, 0xE20C, CS_AMPERE_AMPEREONE192}, // Ampere AmpereOne-192 + {PCI_VENDOR_ID_AMPERE, 0xE20D, CS_AMPERE_AMPEREONE192}, // Ampere AmpereOne-192 + {PCI_VENDOR_ID_AMPERE, 0xE20E, CS_AMPERE_AMPEREONE192}, // Ampere AmpereOne-192 + {PCI_VENDOR_ID_AMPERE, 0xE20F, CS_AMPERE_AMPEREONE192}, // Ampere AmpereOne-192 + {PCI_VENDOR_ID_NVIDIA, 0x22D1, CS_NVIDIA_T254}, + + // last element must have chipset CS_UNKNOWN (zero) + {0, 0, CS_UNKNOWN} +}; + +#endif /* NVCST_H */ diff --git a/userspace/sdks/nv570/nvalloc/common/inc/nvdm_format.h b/userspace/sdks/nv570/nvalloc/common/inc/nvdm_format.h new file mode 100644 index 0000000..db3baa0 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/nvdm_format.h @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVDM_FORMAT_H +#define NVDM_FORMAT_H + +/** + * NVDM (NVIDIA Data Model) overlaid on MCTP (Management Component Transport + * Protocol) format definitions. + * + * This header consolidates NVDM type definitions from multiple RM subsystems + * including FSP, SEC2, GSP, and others. NVDM is a vendor-defined message layer + * overlaid on MCTP that provides a simple way for different subsystems to + * communicate. + */ + +// +// List of NVDM Message Types +// +// Values are allocated from a shared namespace across all subsystems. +// Add new types here and update the NVDM Message Type allocation page. +// +#define NVDM_TYPE_RESET 0x4 +#define NVDM_TYPE_HULK 0x11 +#define NVDM_TYPE_FIRMWARE_UPDATE 0x12 +#define NVDM_TYPE_PRC 0x13 +#define NVDM_TYPE_COT 0x14 +#define NVDM_TYPE_FSP_RESPONSE 0x15 +#define NVDM_TYPE_SEC2_RESPONSE NVDM_TYPE_FSP_RESPONSE +#define NVDM_TYPE_CAPS_QUERY 0x16 +#define NVDM_TYPE_INFOROM 0x17 +#define NVDM_TYPE_SMBPBI 0x18 +#define NVDM_TYPE_ROMREAD 0x1A +#define NVDM_TYPE_UEFI_RM 0x1C +#define NVDM_TYPE_UEFI_XTL_DEBUG_INTR 0x1D +#define NVDM_TYPE_TNVL 0x1F +#define NVDM_TYPE_CLOCK_BOOST 0x20 +#define NVDM_TYPE_FSP_GSP_COMM 0x21 +#define NVDM_TYPE_SEC2_GSP_COMM NVDM_TYPE_FSP_GSP_COMM + +#define NVDM_TYPE_RM_RPC 0x25 // GSP-RM RPC messages + +#endif // NVDM_FORMAT_H diff --git a/userspace/sdks/nv570/nvalloc/common/inc/nvpcie.h b/userspace/sdks/nv570/nvalloc/common/inc/nvpcie.h new file mode 100644 index 0000000..c4ee983 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/nvpcie.h @@ -0,0 +1,545 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2000-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVPCIE_H +#define NVPCIE_H + + +#include "nvtypes.h" + +/**************** Resource Manager Defines and Structures ******************\ +* * +* Private PCI Express related defines and structures. * +* * +\***************************************************************************/ + +typedef struct NBADDR +{ + NvU32 domain; + NvU8 bus; + NvU8 device; + NvU8 func; + NvU8 valid; + void *handle; +} NBADDR; + +typedef struct PORTDATA +{ + NBADDR addr; + void *vAddr; // virtual address of the port, if it has been mapped . Not used starting with Win10 BuildXXXXX + NvU32 PCIECapPtr; // offset of the PCIE capptr in the NB + // Capability register set in enhanced configuration space + // + NvU32 PCIEErrorCapPtr; // offset of the Advanced Error Reporting Capability register set + NvU32 PCIEVCCapPtr; // offset of the Virtual Channel (VC) Capability register set + NvU32 PCIEL1SsCapPtr; // Offset of the L1 Substates Capabilities + NvU32 PCIEAcsCapPtr; // Offset of the ACS redirect Capabilities + NvU16 DeviceID, VendorID; // device and vendor ID for port +} PORTDATA; + +#define PCI_VENDOR_ID 0x00 +#ifndef PCI_DEVICE_ID +#define PCI_DEVICE_ID 0x02 +#endif +#define PCI_BASE_ADDRESS_1 0x14 /* Aperture Base */ +#define PCI_BASE_ADDRESS_2 0x18 /* Aperture Base */ +#define PCI_CAPABILITY_LIST 0x34 +#define PCI_DEVICE_SPECIFIC 0x40 + +#define NV_PCI_ID 0x0 +#define NV_PCI_ID_VENDOR 15:0 +#define NV_PCI_ID_VENDOR_NVIDIA 0x10DE +#define NV_PCI_ID_DEVICE 31:16 + +#define PCI_MAX_SLOTS 255 +#define PCI_MAX_LANE_WIDTH 32 + +#define PCI_MAX_FUNCTION 8 +#define PCI_INVALID_VENDORID 0xFFFF +#define PCI_INVALID_DEVICEID 0xFFFF +#define PCI_INVALID_SUBVENDORID 0xFFFF +#define PCI_INVALID_SUBDEVICEID 0xFFFF + +#define PCI_IS_VENDORID_VALID(id) (((id) != 0x0000) && ((id) != 0xFFFF)) + +#define PCI_CLASS_BRIDGE_DEV 0x06 +#define PCI_SUBCLASS_BR_HOST 0x00 +#define PCI_MULTIFUNCTION 0x80 + +// From PCI Local Bus Specification, Revision 3.0 +// and PCI Express Base Specification 6.0 +// numbers in comments to right of values indicate +// the referenced section in the PCIE spec + + +#define CAP_ID_MASK 0xFF + +#define CAP_ID_NULL 0x00 // 7.9.28.1 +#define CAP_ID_PMI 0x01 // 7.5.2.1 +#define CAP_ID_AGP 0x02 +#define CAP_ID_VPD 0x03 // 7.9.18.1 +#define CAP_ID_SLOT_ID 0x04 +#define CAP_ID_MSI 0x05 // 7.7.1.1 +#define CAP_ID_HOT_SWAP 0x06 +#define CAP_ID_PCI_X 0x07 +#define CAP_ID_HYPER_TRANSPORT 0x08 +#define CAP_ID_VENDOR_SPECIFIC 0x09 +#define CAP_ID_DEBUG_PORT 0x0A +#define CAP_ID_CRC 0x0B +#define CAP_ID_HOT_PLUG 0x0C +#define CAP_ID_SUBSYSTEM_ID 0x0D // 7.9.23.1 +#define CAP_ID_AGP8X 0x0E +#define CAP_ID_SECURE 0x0F +#define CAP_ID_PCI_EXPRESS 0x10 // 7.5.3.1 +#define CAP_ID_MSI_X 0x11 // 7.7.2.1 +#define CAP_ID_ENHANCED_ALLOCATION 0x14 // 7.8.5.1 +#define CAP_ID_FPB 0x15 // 7.8.11.1 +#define CAP_ID_AF 0x13 // 7.9.21.1 + +// +// sizes for static PCI capabilities structure +// +#define CAP_NULL_SIZE 0x04 // 7.9.28 +#define CAP_PMI_SIZE 0x08 // 7.5.2 +#define CAP_VPD_SIZE 0x08 // 7.9.18 +#define CAP_PCI_X_SIZE 0x3C // 7.5.3 +#define CAP_PCI_EXPRESS_SIZE 0x3C // 7.5.3 +#define CAP_FPB_SIZE 0x08 // 7.8.11.1 +#define CAP_AF_SIZE 0x08 // 7.9.21 +#define CAP_SUBSYSTEM_ID_SIZE 0x08 // 7.9.23 + +// MSI capability size related fields +#define PCI_MSI_CONTROL 0x02 // 7.7.1.2 +#define PCI_MSI_CONTROL_64BIT_CAPABLE 7:7 +#define PCI_MSI_CONTROL_64BIT_CAPABLE_FALSE 0 +#define PCI_MSI_CONTROL_64BIT_CAPABLE_TRUE 1 +#define PCI_MSI_CONTROL_PVM_CAPABLE 8:8 +#define PCI_MSI_CONTROL_PVM_CAPABLE_FALSE 0 +#define PCI_MSI_CONTROL_PVM_CAPABLE_TRUE 1 +#define PCI_MSI_BASE_SIZE 0x0C // 7.7.1 +#define PCI_MSI_64BIT_ADDR_CAPABLE_ADJ_SIZE 0x04 // 7.7.1 +#define PCI_MSI_PVM_CAPABLE_ADJ_SIZE 0x08 // 7.7.1 + +// MSI-X capability size related fields +#define PCI_MSI_X_BASE_SIZE 0x0C // 7.7.2 +#define PCI_MSI_X_CONTROL 0x02 // 7.7.2.2 +#define PCI_MSI_X_CONTROL_TABLE_SIZE 10:0 +#define PCI_MSI_X_TABLE_OFFSET_BIR 0x04 // 7.7.2.3 +#define PCI_MSI_X_TABLE_OFFSET 31:3 +#define PCI_MSI_X_PBR_OFFSET_BIR 0x08 // 7.7.2.4 +#define PCI_MSI_X_PBR_OFFSET 31:3 +#define PCI_MSI_X_TABLE_ENTRY_SIZE 0x10 // 7.7.2 +#define PCI_MSI_X_PBR_ENTRY_SIZE 0x10 // 7.7.2 + +// Enhanced Allocation Capability size related fields +#define PCI_ENHANCED_ALLOCATION_FIRST_DW 0x00 // 7.8.5.1 +#define PCI_ENHANCED_ALLOCATION_FIRST_DW_NUM_ENTRIES 21:16 +#define PCI_ENHANCED_ALLOCATION_TYPE_0_BASE_SIZE 0x04 // 7.8.5.1 +#define PCI_ENHANCED_ALLOCATION_TYPE_1_BASE_SIZE 0x08 // 7.8.5.2 +#define PCI_ENHANCED_ALLOCATION_ENTRY_HEADER 0x00 // 7.8.5.3 +#define PCI_ENHANCED_ALLOCATION_ENTRY_HEADER_ENTRY_SIZE 2:0 + +// PCI Vendor Specific Capability size related fields +#define PCI_VENDOR_SPECIFIC_CAP_HEADER 0x00 // 7.9.4 +#define PCI_VENDOR_SPECIFIC_CAP_HEADER_LENGTH 23:16 + +// +// Extended config space size is 4096 bytes. +// +#define PCI_EXTENDED_CONFIG_SPACE_LENGTH 4096 + +// +// From PCI Local Bus Specification, Revision 3.0 +// HEADER TYPE0 Definitions - Byte offsets +// +#define PCI_HEADER_TYPE0_VENDOR_ID 0x00 +#define PCI_HEADER_TYPE0_DEVICE_ID 0x02 +#define PCI_HEADER_TYPE0_COMMAND 0x04 +#define PCI_HEADER_TYPE0_STATUS 0x06 +#define PCI_HEADER_TYPE0_REVISION_ID 0x08 +#define PCI_HEADER_TYPE0_PROGIF 0x09 +#define PCI_HEADER_TYPE0_SUBCLASS 0x0A +#define PCI_HEADER_TYPE0_BASECLASS 0x0B +#define PCI_HEADER_TYPE0_CACHE_LINE_SIZE 0x0C +#define PCI_HEADER_TYPE0_LATENCY_TIMER 0x0D +#define PCI_HEADER_TYPE0_HEADER_TYPE 0x0E +#define PCI_HEADER_TYPE0_HEADER_TYPE_0 0 +#define PCI_HEADER_TYPE0_HEADER_TYPE_1 1 +#define PCI_HEADER_TYPE0_BIST 0x0F +#define PCI_HEADER_TYPE0_BAR0 0x10 +#define PCI_HEADER_TYPE0_BAR1 0x14 +#define PCI_HEADER_TYPE0_BAR2 0x18 +#define PCI_HEADER_TYPE0_BAR3 0x1C +#define PCI_HEADER_TYPE0_BAR4 0x20 +#define PCI_HEADER_TYPE0_BAR5 0x24 +#define PCI_HEADER_TYPE0_CBCIS_PTR 0x28 +#define PCI_HEADER_TYPE0_SUBSYS_VEN_ID 0x2C +#define PCI_HEADER_TYPE0_SUBSYS_ID 0x2E +#define PCI_HEADER_TYPE0_ROMBAR 0x30 +#define PCI_HEADER_TYPE0_CAP_PTR 0x34 +#define PCI_HEADER_TYPE0_INT_LINE 0x3C +#define PCI_HEADER_TYPE0_INT_PIN 0x3D +#define PCI_HEADER_TYPE0_MIN_GNT 0x3E +#define PCI_HEADER_TYPE0_MAX_LAT 0x3F + +// +// From PCI Express Base Specification Revision 2.0 +// HEADER TYPE1 Definitions +#define PCI_HEADER_TYPE1_BRIDGE_CONTROL 0x3E +#define PCI_HEADER_TYPE1_BRIDGE_CONTROL_VGA_EN 0x08 + +#define PCIE_LINK_CAPABILITIES_2 0x000000A4 /* R--4R */ +#define PCIE_LINK_CAPABILITIES_2_RSVD 0:0 /* C--VF */ +#define PCIE_LINK_CAPABILITIES_2_RSVD_INIT 0x00000000 /* C---V */ +#define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED 7:1 /* R-EVF */ +#define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2_GEN3_GEN4_GEN5 0x0000001F /* R---V */ +#define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_HIDDEN 0x00000000 /* R---V */ +#define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1 0x00000001 /* R---V */ +#define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2 0x00000003 /* R---V */ +#define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2_GEN3 0x00000007 /* R-E-V */ +#define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2_GEN3_GEN4 0x0000000F /* R---V */ +#define PCIE_LINK_CAPABILITIES_2_CROSS_LINK_SUPPORT 8:8 /* C--VF */ +#define PCIE_LINK_CAPABILITIES_2_CROSS_LINK_SUPPORT_DISABLED 0x00000000 /* C---V */ +#define PCIE_LINK_CAPABILITIES_2_RET_PRESENCE_DET_SUPP 23:23 /* R-EVF */ +#define PCIE_LINK_CAPABILITIES_2_RET_PRESENCE_DET_SUPP_UNSET 0x00000000 /* R-E-V */ +#define PCIE_LINK_CAPABILITIES_2_2RET_PRESENCE_DET_SUPP 24:24 /* R-EVF */ +#define PCIE_LINK_CAPABILITIES_2_2RET_PRESENCE_DET_SUPP_UNSET 0x00000000 /* R-E-V */ +#define PCIE_LINK_CAPABILITIES_2_RSVD1 31:25 /* C--VF */ +#define PCIE_LINK_CAPABILITIES_2_RSVD1_INIT 0x00000000 /* C---V */ + +// +// PCI Express Virtual Peer-to-Peer Approval Definition +// +// These offsets are unused in hardware on existing chips and are reserved on +// future chips. Software has defined a virtual PCI capability that may be +// emulated by hypervisors at these offsets, and this capability is not tied +// to any specific hardware. +// +// +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0 0x000000C8 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_ID 7:0 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_NEXT 15:8 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_LENGTH 23:16 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_SIG_LO 31:24 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1 0x000000CC +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_SIG_HI 15:0 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_VERSION 18:16 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_PEER_CLIQUE_ID 22:19 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RSVD 31:23 + +#define NV_PCI_VIRTUAL_P2P_APPROVAL_SIGNATURE 0x00503250 + +#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_0 0x000000D4 +#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_0_ID 7:0 +#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_0_NEXT 15:8 +#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_0_LENGTH 23:16 +#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_0_SIG_LO 31:24 +#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_1 0x000000D8 +#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_1_SIG_HI 15:0 +#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_1_VALUE 31:16 + +#define NV_PCI_VIRTUAL_CONFIG_BITS_SIGNATURE 0x00535442 //"BTS" + +// Allocation of _VALUE bits +#define NV_PCI_VIRTUAL_CONFIG_BITS_PCI_EGRESS_POISON_ENABLE 0:0 + +// Chipset-specific definitions. +// Intel SantaRosa definitions +#define INTEL_2A00_CONFIG_SPACE_BASE 0x60 + +// Intel Montevina definitions +#define INTEL_2A40_CONFIG_SPACE_BASE 0x60 +#define INTEL_2A40_ASLM_CAPABLE_REVID 0x05 + +// Intel EagleLake definitions +#define INTEL_2E00_CONFIG_SPACE_BASE 0x60 + +// Intel Bearlake definitions +#define INTEL_29XX_CONFIG_SPACE_BASE 0x60 + +// Intel BroadWater definitions +#define INTEL_29A0_CONFIG_SPACE_BASE 0x60 + +// Intel Grantsdale definitions +#define INTEL_25XX_CONFIG_SPACE_BASE 0x48 + +// Intel Tumwater definitions +#define INTEL_359E_CONFIG_SPACE_BASE 0xCC + +// Intel Greencreek definitions +#define INTEL_25E0_CONFIG_SPACE_BASE_ADDRESS 0xE0000000 + +// Intel Stoakley definitions +#define INTEL_4000_CONFIG_SPACE_BASE_ADDRESS 0xE0000000 + +// Intel SkullTrail definitions +#define INTEL_4003_CONFIG_SPACE_BASE_ADDRESS_F 0xF0000000 +#define INTEL_4003_CONFIG_SPACE_BASE_ADDRESS_E 0xE0000000 +#define INTEL_4003_CONFIG_SPACE_BASE_ADDRESS INTEL_4003_CONFIG_SPACE_BASE_ADDRESS_F +#define INTEL_4003_CONFIG_SPACE_BASE 0x64 + +// SiS 656 +#define SIS_656_CONFIG_SPACE_BASE 0xE0 +#define SIS_656_CONFIG_SPACE_BASE_ADDRESS 3:0 // mapped to 31:28 + +// PCI/PCIE definitions +#define PCI_MAX_CAPS 20 // max caps to parse +#define PCI_MAX_DEVICES 32 // max devices on bus +#define PCI_MAX_FUNCTIONS 8 // max functions for a device +#define PCI_CAP_HEADER_ID 7:0 // PCI cap header id +#define PCI_CAP_HEADER_NEXT 15:8 // PCI cap header next +#define PCI_COMMON_CLASS_SUBCLASS 0x0a // PCI class/subclass (word) +#define PCI_COMMON_CLASS_SUBBASECLASS_HOST 0x0600 // Host bridge (connect PCI to CPU) [00] + Bridge Device [06] +#define PCI_COMMON_CLASS_SUBBASECLASS_P2P 0x0604 // PCI-to-PCI bridge (connects PCI buses) [04] + Bridge Device [06] +#define PCI_COMMON_CLASS_SUBBASECLASS_VGA 0x0300 +#define PCI_COMMON_CLASS_SUBBASECLASS_3DCTRL 0x0302 +#define PCI_COMMON_CAP_PTR 0x34 // PCI common cap ptr (byte) +#define PCI_TYPE_1_SECONDARY_BUS_NUMBER 0x19 // PCI type 1 sec bus (byte) +#define PCI_TYPE_1_SUBORDINATE_BUS_NUMBER 0x1a // PCI type 1 sub bus (byte) +#define PCIE_CAP_HEADER_ID 15:0 // PCIE cap header id +#define PCIE_CAP_HEADER_ID_INVALID 0xffff +#define PCIE_CAP_HEADER_NEXT 31:20 // PCIE cap header next +#define PCIE_BUS_SHIFT 20 // PCIE cfg space bus shift +#define PCIE_DEVICE_SHIFT 15 // PCIE cfg space dev shift +#define PCIE_FUNC_SHIFT 12 // PCIE cfg space func shift +#define PCIE_CAP_VERSION 19:16 // PCIE cap version +#define PCIE_CAP_VERSION_2P0 2 // PCIE 2.0 version +#define PCIE_LINK_CNTRL_STATUS_2_OFFSET 0x30 // PCIE Link Control/Status 2 offset +#define PCIE_LINK_STATUS_2 31:16 // PCIE Link Status 2 Register +#define PCIE_LINK_STATUS_2_DE_EMPHASIS 0:0 // PCIE De-Emphasis Level +#define PCI_COMMON_SUBSYSTEM_VENDOR_ID 0x2c // PCI subsystem Vendor Id +#define PCI_COMMON_SUBSYSTEM_ID 0x2e // PCI subsystem Id +#define PCIE_CAPABILITY_BASE 0x100 // 1st PCIE capability. + +// PCI Express Capability ID in the enhanced configuration space +#define PCIE_CAP_ID_NULL 0x00 // 7.9.28.1 +#define PCIE_CAP_ID_ERROR 0x01 // 7.8.4.1 +#define PCIE_CAP_ID_VC 0x02 // 7.9.1.1 +#define PCIE_CAP_ID_SERIAL 0x03 // 7.9.3.1 +#define PCIE_CAP_ID_POWER 0x04 // 7.8.1.1 +#define PCIE_CAP_ID_ROOT_COMPLEX 0x05 // 7.9.8.1 +#define PCIE_CAP_ID_ROOT_COMPLEX_INTERNAL_LINK_CTRL 0x06 // 7.9.9.1 +#define PCIE_CAP_ID_ROOT_COMPLEX_EVENT_COLLECTOR_ENDPOINT 0x07 // 7.9.10.1 +#define PCIE_CAP_ID_PCIE_CAP_ID_MFVC 0x08 // 7.9.2.1 +#define PCIE_CAP_ID_RCRB 0x0A // 7.9.7.1 +#define PCIE_CAP_ID_ACS 0x0D // 7.7.11.1 +#define PCIE_CAP_ID_ARI 0x0E // 7.8.8.1 +#define PCIE_CAP_ID_MULTICAST 0x12 // 7.9.11.1 +#define PCIE_CAP_ID_RESIZABLE_BAR 0x15 // 7.8.6.1 +#define PCIE_CAP_ID_DYNAMIC_POWER_ALLOCATION 0x16 // 7.9.12.1 +#define PCIE_CAP_ID_TPH 0x17 // 7.9.13.1 +#define PCIE_CAP_ID_LATENCY_TOLERANCE 0x18 // 7.8.2.1 +#define PCIE_CAP_ID_SECONDARY_PCIE_CAPABILITY 0x19 // 7.7.3.1 +#define PCIE_CAP_ID_PASID 0x1B // 7.8.9.1 +#define PCIE_CAP_ID_DPC 0x1D // 7.9.14.1 +#define PCIE_CAP_ID_L1_PM_SUBSTATES 0x1E // 7.8.3.1 +#define PCIE_CAP_ID_PTM 0x1F // 7.9.15.1 +#define PCIE_CAP_ID_FRS_QUEUING 0x21 // 7.8.10.1 +#define PCIE_CAP_ID_READINESS_TIME_REPORTING 0x22 // 7.9.16.1 +#define PCIE_CAP_ID_VENDOR_SPECIFIC 0x23 // 7.9.6.1 +#define PCIE_CAP_ID_VF_RESIZABLE_BAR 0x24 // 7.8.7.1 +#define PCIE_CAP_ID_DATA_LINK 0x25 // 7.7.4.1 +#define PCIE_CAP_ID_PHYSLAYER_16_GT 0x26 // 7.7.5.1 +#define PCIE_CAP_ID_LANE_MARGINING_AT_RECEVER 0x27 // 7.7.10.1 +#define PCIE_CAP_ID_HIERARCHY_ID 0x28 // 7.9.17.1 +#define PCIE_CAP_ID_NPEM 0x29 // 7.9.19.1 +#define PCIE_CAP_ID_PHYSLAYER_32_GT 0x2A // 7.7.6.1 +#define PCIE_CAP_ID_ALTERNATE_PROTOCOL 0x2B // 7.9.20.1 +#define PCIE_CAP_ID_SFI 0x2C // 7.9.22.1 +#define PCIE_CAP_ID_SHADOW_FUNCTIONS 0x2D // 7.9.25.1 +#define PCIE_CAP_ID_DATA_OBJECT_EXCHANGE 0x2E // 7.9.24.1 +#define PCIE_CAP_ID_DEVICE_3 0x2F // 7.7.9.1 +#define PCIE_CAP_ID_IDE 0x30 // 7.9.26.1 +#define PCIE_CAP_ID_PHYSLAYER_64_GT 0x31 // 7.7.7.1 +#define PCIE_CAP_ID_FLT_LOGGING 0x32 // 7.7.8.1 +#define PCIE_CAP_ID_FLIT_PERF_MEASURMENT 0x33 // 7.8.12.1 +#define PCIE_CAP_ID_FLIT_ERROR_INJECTION 0x34 // 7.8.13.1 + +// static sized structure sizes +#define PCIE_CAP_HEADER_SIZE 0x04 // 7.6.3 +#define PCIE_CAP_NULL_SIZE 0x04 // 7.9.28 +#define PCIE_CAP_ERROR_SIZE 0x48 // 7.8.4 +#define PCIE_CAP_POWER_SIZE 0x10 // 7.8.1 +#define PCIE_CAP_ROOT_COMPLEX_INTERNAL_LINK_CTRL_SIZE 0x0C // 7.9.9 +#define PCIE_CAP_ROOT_COMPLEX_EVENT_COLLECTOR_ENDPOINT_SIZE 0x0C // 7.9.10 +#define PCIE_CAP_SECONDARY_PCIE_SIZE 0x4C // 7.7.3.1 +#define PCIE_CAP_DATA_LINK_SIZE 0x0C // 7.7.4 +#define PCIE_CAP_PHYSLAYER_16_GT_SIZE 0x40 // 7.7.5 +#define PCIE_CAP_PHYSLAYER_32_GT_SIZE 0x40 // 7.7.6 +#define PCIE_CAP_PHYSLAYER_64_GT_SIZE 0x20 // 7.7.7 +#define PCIE_CAP_FLT_LOGGING_SIZE 0x3C // 7.7.8 +#define PCIE_CAP_DEVICE_3_SIZE 0x10 // 7.7.9 +#define PCIE_CAP_LANE_MARGINING_AT_RECEVER_SIZE 0x88 // 7.7.10 +#define PCIE_CAP_ACS_SIZE 0x10 // 7.7.11 +#define PCIE_CAP_LATENCY_TOLERANCE_SIZE 0x08 // 7.8.2 +#define PCIE_CAP_L1_PM_SUBSTATE_SIZE 0x14 // 7.8.3 +#define PCIE_CAP_RESIZABLE_BAR_SIZE 0x34 // 7.8.6 +#define PCIE_CAP_VF_RESIZABLE_BAR_SIZE 0x34 // 7.8.7 +#define PCIE_CAP_ARI_SIZE 0x08 // 7.8.8 +#define PCIE_CAP_PASID_SIZE 0x08 // 7.8.9 +#define PCIE_CAP_FRS_QUEUING_SIZE 0x10 // 7.8.10 +#define PCIE_CAP_FPB_SIZE 0x24 // 7.8.11 +#define PCIE_CAP_FLIT_PERF_MEASURMENT_SIZE 0x24 // 7.8.12 +#define PCIE_CAP_FLIT_ERROR_INJECTION_SIZE 0x24 // 7.8.13 +#define PCIE_CAP_DEV_SERIAL_SIZE 0x0C // 7.9.3 +#define PCIE_CAP_RCRB_SIZE 0x14 // 7.9.7 +#define PCIE_CAP_MULTICAST_SIZE 0x30 // 7.9.11 +#define PCIE_CAP_DYNAMIC_POWER_ALLOCATION_SIZE 0x30 // 7.9.12 +#define PCIE_CAP_DPC_SIZE 0x5C // 7.9.14 +#define PCIE_CAP_PTM_SIZE 0x0C // 7.9.15 +#define PCIE_CAP_READINESS_TIME_REPORTING_SIZE 0x0C // 7.9.16 +#define PCIE_CAP_HIERARCHY_ID_SIZE 0x0C // 7.9.17 +#define PCIE_CAP_NPEM_SIZE 0x10 // 7.9.19 +#define PCIE_CAP_ALTERNATE_PROTOCOL_SIZE 0x14 // 7.9.20 +#define PCIE_CAP_SFI_SIZE 0x14 // 7.9.22 +#define PCIE_CAP_DATA_OBJECT_EXCHANGE_SIZE 0x18 // 7.9.24 +#define PCIE_CAP_SHADOW_FUNCTIONS_SIZE 0x1C // 7.9.25 +#define PCIE_CAP_IDE_SIZE 0x34 // 7.9.26 + +// Virtual Channel Capability size related fields +#define PCIE_VC_REGISTER_1 0x04 // 7.9.1.2 +#define PCIE_VC_REGISTER_1_EXTENDED_VC_COUNT 2:0 +#define PCIE_VIRTUAL_CHANNELS_BASE_SIZE 0x18 // 7.9.1 +#define PCIE_VIRTUAL_CHANNELS_EXTENDED_VC_ENTRY_SIZE 0x10 // 7.9.1 + +// Multi Function Virtual Channel Capability size related fields +#define PCIE_MFVC_REGISTER_1 0x04 // 7.9.2.2 +#define PCIE_MFVC_REGISTER_1_EXTENDED_VC_COUNT 2:0 +#define PCIE_PCIE_CAP_ID_MFVC_BASE_SIZE 0x18 // 7.9.2 +#define PCIE_PCIE_CAP_ID_MFVC_EXTENDED_VC_ENTRY_SIZE 0x10 // 7.9.2 + +// Vendor Specific Capability size related fields +#define PCIE_VENDOR_SPECIFIC_HEADER_1 0x04 // 7.9.6.2 +#define PCIE_VENDOR_SPECIFIC_HEADER_1_LENGTH 31:20 + +// Root Complex Capability size related fields +#define PCIE_ROOT_COMPLEX_SELF_DESC_REGISTER 0x04 // 7.9.8.2 +#define PCIE_ROOT_COMPLEX_SELF_DESC_REGISTER_NUM_LINK_ENTRIES 15:8 +#define PCIE_ROOT_COMPLEX_BASE_SIZE 0x0C // 7.9.8 +#define PCIE_ROOT_COMPLEX_LINK_ENTRY_SIZE 0x10 // 7.9.8.3 + +// TPH capability size related fields +#define PCIE_TPH_REQUESTOR_REGISTER 0x04 // 7.9.13.2 +#define PCIE_TPH_REQUESTOR_REGISTER_ST_TABLE_SIZE 26:16 +#define PCIE_TPH_BASE_SIZE 0x0C // 7.9.13 +#define PCIE_TPH_ST_ENTRY_SIZE 0x02 // 7.9.13.4 + +// Intel CPU family. +#define INTEL_CPU_FAMILY_06 0x06 +#define INTEL_CPU_FAMILY_15 0x0f +#define INTEL_CPU_FAMILY_16 0x10 +#define INTEL_CPU_FAMILY_21 0x15 + +// Intel CPU Model. Calculated as Model += (extModel << 4). +#define INTEL_CPU_MODEL_2A 0x2a +#define INTEL_CPU_MODEL_2D 0x2d +#define INTEL_CPU_MODEL_3A 0x3a +#define INTEL_CPU_MODEL_3F 0x3f + +// Symbolic defines for each possible virtual channel +enum +{ + RM_PCIE_VIRTUAL_CHANNEL_0 = 0, + RM_PCIE_VIRTUAL_CHANNEL_1, + RM_PCIE_VIRTUAL_CHANNEL_2, + RM_PCIE_VIRTUAL_CHANNEL_3, + RM_PCIE_VIRTUAL_CHANNEL_4, + RM_PCIE_VIRTUAL_CHANNEL_5, + RM_PCIE_VIRTUAL_CHANNEL_6, + RM_PCIE_VIRTUAL_CHANNEL_7, + RM_PCIE_VIRTUAL_CHANNEL_INVALID +}; + +// Diagnostic collection actions. +#define RM_PCIE_ACTION_NOP 0 +#define RM_PCIE_ACTION_COLLECT_CONFIG_SPACE 1 +#define RM_PCIE_ACTION_COLLECT_PCI_CAP_STRUCT 2 +#define RM_PCIE_ACTION_COLLECT_PCIE_CAP_STRUCT 3 +#define RM_PCIE_ACTION_COLLECT_ALL_PCI_CAPS 4 +#define RM_PCIE_ACTION_COLLECT_ALL_PCIE_CAPS 5 +#define RM_PCIE_ACTION_REPORT_PCI_CAPS_COUNT 6 +#define RM_PCIE_ACTION_REPORT_PCIE_CAPS_COUNT 7 +#define RM_PCIE_ACTION_EOS 0xff + + +// Diagnostic collection device Type ids +#define RM_PCIE_DEVICE_TYPE_NONE 0xff +#define RM_PCIE_DEVICE_TYPE_GPU 0 +#define RM_PCIE_DEVICE_TYPE_UPSTREAM_BRIDGE 1 +#define RM_PCIE_DEVICE_COUNT 2 + +// Diagnostic collection capability Type ids +#define RM_PCIE_DC_CAP_TYPE_NONE 0xff +#define RM_PCIE_DC_CAP_TYPE_PCI 0 +#define RM_PCIE_DC_CAP_TYPE_PCIE 1 +#define RM_PCIE_DC_CAP_TYPE_COUNT 2 + +typedef struct _def_bif_dc_diagnostic_collection_command +{ + NvU8 action; + NvU8 deviceType; + NvU16 locator; + NvU16 length; +} CL_PCIE_DC_DIAGNOSTIC_COLLECTION_ENTRY; + +typedef struct _def_cl_pcie_dc_capability_map_entry +{ + NvU16 id; + NvU16 blkOffset; +} CL_PCIE_DC_CAPABILITY_MAP_ENTRY; +typedef struct +{ + NvU16 count; + CL_PCIE_DC_CAPABILITY_MAP_ENTRY entries[PCI_MAX_CAPS]; +} CL_PCIE_DC_CAPABILITY_MAP; + +typedef struct OBJCL OBJCL; +typedef struct OBJGPU OBJGPU; +// root port setup functions +NV_STATUS Broadcom_HT2100_setupFunc(OBJGPU *, OBJCL*); + +NV_STATUS Intel_RP25XX_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS Intel_RP81XX_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS Intel_RP3C0X_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS Intel_RP2F0X_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS Intel_RP0C0X_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS Intel_Broadwell_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS Intel_Skylake_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS Intel_Skylake_U_Pch_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS Intel_Skylake_H_Pch_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS Intel_Kabylake_Y_setupFunc(OBJGPU *, OBJCL*); + +NV_STATUS Nvidia_RPC19_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS Nvidia_RPC51_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS Nvidia_RPC55_setupFunc(OBJGPU *, OBJCL*); + +NV_STATUS AMD_RP1480_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS AMD_RP1630_setupFunc(OBJGPU *, OBJCL*); +NV_STATUS AMD_RP1483_setupFunc(OBJGPU *, OBJCL*); + +NV_STATUS Qualcomm_Snapdragon8cx_RP_setupFunc(OBJGPU *, OBJCL*); + +// Determines if the GPU is in a multi-GPU board based on devid checks +NvBool gpuIsMultiGpuBoard(OBJGPU *); + +#endif // NVPCIE_H diff --git a/userspace/sdks/nv570/nvalloc/common/inc/nvrangetypes.h b/userspace/sdks/nv570/nvalloc/common/inc/nvrangetypes.h new file mode 100644 index 0000000..1ff7df6 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/nvrangetypes.h @@ -0,0 +1,162 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file nvrangetypes.h + * @brief Range types and operator macros + * @note #include a header to define NvUxx and NvSxx before sourcing this file. + */ + +#ifndef _NVRANGETYPES_H_ +#define _NVRANGETYPES_H_ + + +// +// Define range types by convention +// +#define __NV_DEFINE_RANGE_TYPE(T) \ +typedef struct NvRange ## T \ +{ \ + Nv ## T min; \ + Nv ## T max; \ +} NvRange ## T; + + +__NV_DEFINE_RANGE_TYPE(U64) // NvRangeU64 +__NV_DEFINE_RANGE_TYPE(S64) // NvRangeS64 +__NV_DEFINE_RANGE_TYPE(U32) // NvRangeU32 +__NV_DEFINE_RANGE_TYPE(S32) // NvRangeS32 +__NV_DEFINE_RANGE_TYPE(U16) // NvRangeU16 +__NV_DEFINE_RANGE_TYPE(S16) // NvRangeS16 +__NV_DEFINE_RANGE_TYPE(U8) // NvRangeU8 +__NV_DEFINE_RANGE_TYPE(S8) // NvRangeS8 + + +// +// Operator macros +// +// Macros are named xxx_RANGE (rather than xxx_RANGEU32, etc.) since they work +// properly on ranges with any number of bits, signed or unsigned. +// + +#define NV_EQUAL_RANGE(r1, r2) ((r1).min == (r2).min && (r1).max == (r2).max) +#define NV_EMPTY_INCLUSIVE_RANGE(r) ((r).min > (r).max) +#define NV_EMPTY_EXCLUSIVE_RANGE(r) ((r).min + 1 > (r).max - 1) +#define NV_WITHIN_INCLUSIVE_RANGE(r, x) ((r).min <= (x) && (x) <= (r).max) +#define NV_WITHIN_EXCLUSIVE_RANGE(r, x) ((r).min < (x) && (x) < (r).max) +#define NV_IS_SUBSET_RANGE(r1, r2) ((r1).min >= (r2).min && (r2).max >= (r1).max) +#define NV_IS_SUPERSET_RANGE(r1, r2) ((r1).min <= (r2).min && (r2).max <= (r1).max) +#define NV_CENTER_OF_RANGE(r) ((r).min / 2 + ((r).max + 1) / 2) // Avoid overflow and rounding anomalies. +#define NV_IS_OVERLAPPING_RANGE(r1, r2) \ + (NV_WITHIN_INCLUSIVE_RANGE((r1), (r2).min) || \ + NV_WITHIN_INCLUSIVE_RANGE((r1), (r2).max)) + +#define NV_DISTANCE_FROM_RANGE(r, x) ((x) < (r).min? (r).min - (x): ((x) > (r).max? (x) - (r).max: 0)) +#define NV_VALUE_WITHIN_INCLUSIVE_RANGE(r, x) ((x) < (r).min? (r).min : ((x) > (r).max? (r).max : (x))) +#define NV_VALUE_WITHIN_EXCLUSIVE_RANGE(r, x) ((x) <= (r).min? (r).min + 1 : ((x) >= (r).max? (r).max - 1 : (x))) + +#define NV_INIT_RANGE(r, x, y) \ +do \ +{ \ + (r).min = (x); \ + (r).max = (y); \ +} while(0) + +#define NV_ASSIGN_DELTA_RANGE(r, x, d) \ +do \ +{ \ + (r).min = (x) - (d); \ + (r).max = (x) + (d); \ +} while(0) + +#define NV_ASSIGN_INTERSECTION_RANGE(r1, r2) \ +do \ +{ \ + if ((r1).min < (r2).min) \ + (r1).min = (r2).min; \ + if ((r1).max > (r2).max) \ + (r1).max = (r2).max; \ +} while(0) + +#define NV_ASSIGN_UNION_RANGE(r1, r2) \ +do \ +{ \ + if ((r1).min > (r2).min) \ + (r1).min = (r2).min; \ + if ((r1).max < (r2).max) \ + (r1).max = (r2).max; \ +} while(0) + +#define NV_MULTIPLY_RANGE(r, x) \ +do \ +{ \ + (r).min *= (x); \ + (r).max *= (x); \ +} while(0) + +#define NV_DIVIDE_FLOOR_RANGE(r, x) \ +do \ +{ \ + (r).min /= (x); \ + (r).max /= (x); \ +} while(0) + +#define NV_DIVIDE_CEILING_RANGE(r, x) \ +do \ +{ \ + (r).min = ((r).min + (x) - 1) / (x); \ + (r).max = ((r).max + (x) - 1) / (x); \ +} while(0) + +#define NV_DIVIDE_ROUND_RANGE(r, x) \ +do \ +{ \ + (r).min = ((r).min + (x) / 2) / (x); \ + (r).max = ((r).max + (x) / 2) / (x); \ +} while(0) + +#define NV_DIVIDE_WIDE_RANGE(r, x) \ +do \ +{ \ + (r).min /= (x); \ + (r).max = ((r).max + (x) - 1) / (x); \ +} while(0) + +#define NV_DIVIDE_NARROW_RANGE(r, x) \ +do \ +{ \ + (r).min = ((r).min + (x) - 1) / (x); \ + (r).max /= (x); \ +} while(0) + +#define NV_VALUE_WITHIN_INCLUSIVE_RANGE(r, x) \ + ((x) < (r).min? (r).min : ((x) > (r).max? (r).max : (x))) + +#define NV_WITHIN_INCLUSIVE_RANGE(r, x) \ + ((r).min <= (x) && (x) <= (r).max) + +#define NV_DISTANCE_FROM_RANGE(r, x) \ + ((x) < (r).min? (r).min - (x): ((x) > (r).max? (x) - (r).max: 0)) + +#endif // _NVRANGETYPES_H_ + diff --git a/userspace/sdks/nv570/nvalloc/common/inc/oob/smbpbi.h b/userspace/sdks/nv570/nvalloc/common/inc/oob/smbpbi.h new file mode 100644 index 0000000..aefad5e --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/oob/smbpbi.h @@ -0,0 +1,2925 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _SMBPBI_H +#define _SMBPBI_H + +#include "oob/smbpbi_impl.h" + +/*! + * This file contains definitions for SMBPBI - SMBUS Out-Of-Band (OOB) interface + */ +/*! + * NV_MSGBOX_CMD() macro below and its derivatives depend on DRF_DEF() and DRF_NUM() + * macros, that are defined in "nvdrf.h" header file, which is a part of + * smbus/msgbox SDK. That file needs to be #included before this (smbpbi.h) + * header file. + */ + +/******************************************************************************** + * * + * GPU COMMANDS * + * * + ********************************************************************************/ + +// +// Encoding: +// 30 29 23 16 15 8 7 0 +// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-. +// |I|C|R| STATUS | ARG2 | ARG1 | OPCODE | COMMAND +// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' +// 31 28 24 +// + +#define NV_MSGBOX_CMD_OPCODE 7:0 +#define NV_MSGBOX_CMD_OPCODE_NULL_CMD 0x00000000 +#define NV_MSGBOX_CMD_OPCODE_GET_CAP_DWORD 0x00000001 +#define NV_MSGBOX_CMD_OPCODE_GET_TEMP 0x00000002 +#define NV_MSGBOX_CMD_OPCODE_GET_EXT_TEMP 0x00000003 /* With 8 fractional bits! */ +#define NV_MSGBOX_CMD_OPCODE_GET_POWER 0x00000004 +#define NV_MSGBOX_CMD_OPCODE_GET_SYS_ID_DATA 0x00000005 +#define NV_MSGBOX_CMD_OPCODE_GET_ECC_V1 0x00000006 +#define NV_MSGBOX_CMD_OPCODE_GET_ECC_V2 0x00000007 +#define NV_MSGBOX_CMD_OPCODE_GPU_PCONTROL 0x00000008 +#define NV_MSGBOX_CMD_OPCODE_GPU_SYSCONTROL 0x00000009 +#define NV_MSGBOX_CMD_OPCODE_SET_MASTER_CAPS 0x0000000a +#define NV_MSGBOX_CMD_OPCODE_SET_PRIMARY_CAPS 0x0000000a // Duplicate value till bug 3190552 is addressed. +#define NV_MSGBOX_CMD_OPCODE_GPU_REQUEST_CPL 0x0000000b +#define NV_MSGBOX_CMD_OPCODE_GET_ECC_V3 0x0000000c +#define NV_MSGBOX_CMD_OPCODE_SCRATCH_READ 0x0000000d +#define NV_MSGBOX_CMD_OPCODE_SCRATCH_WRITE 0x0000000e +#define NV_MSGBOX_CMD_OPCODE_SCRATCH_COPY 0x0000000f +#define NV_MSGBOX_CMD_OPCODE_ASYNC_REQUEST 0x00000010 +#define NV_MSGBOX_CMD_OPCODE_REGISTER_ACCESS 0x00000011 +#define NV_MSGBOX_CMD_OPCODE_GET_POWER_CONNECTOR_STATE 0x00000012 +#define NV_MSGBOX_CMD_OPCODE_GET_PAGE_RETIREMENT_STATS 0x00000013 +#define NV_MSGBOX_CMD_OPCODE_GET_ECC_V4 0x00000014 +#define NV_MSGBOX_CMD_OPCODE_GET_THERM_PARAM 0x00000015 +#define NV_MSGBOX_CMD_OPCODE_GET_ECC_V5 0x00000016 +#define NV_MSGBOX_CMD_OPCODE_ACCESS_WP_MODE 0x00000017 + +// +// TODO: Get rid of MISC_GPU_FLAGS once all SMBPBI implementations have made +// the switch to MISC_DEVICE_FLAGS. +// +#define NV_MSGBOX_CMD_OPCODE_GET_MISC_GPU_FLAGS 0x00000018 +#define NV_MSGBOX_CMD_OPCODE_GET_MISC_DEVICE_FLAGS 0x00000018 +#define NV_MSGBOX_CMD_OPCODE_GPU_UTIL_COUNTERS 0x00000019 +#define NV_MSGBOX_CMD_OPCODE_GET_NVLINK_INFO 0x0000001a +#define NV_MSGBOX_CMD_OPCODE_GET_CLOCK_FREQ_INFO 0x0000001b +#define NV_MSGBOX_CMD_OPCODE_BUNDLE_LAUNCH 0x0000001c +#define NV_MSGBOX_CMD_OPCODE_GET_DRIVER_EVENT_MSG 0x0000001d +#define NV_MSGBOX_CMD_OPCODE_GET_ECC_V6 0x0000001e +#define NV_MSGBOX_CMD_OPCODE_REMAP_ROW_STATS 0x00000020 +#define NV_MSGBOX_CMD_OPCODE_GET_PCIE_LINK_INFO 0x00000021 +#define NV_MSGBOX_CMD_OPCODE_GET_ENERGY_COUNTER 0x00000022 +#define NV_MSGBOX_CMD_OPCODE_RESERVED_0 0x00000024 +#define NV_MSGBOX_CMD_OPCODE_RESERVED_1 0x00000025 +#define NV_MSGBOX_CMD_OPCODE_GET_POWER_HINT_INFO 0x00000026 +#define NV_MSGBOX_CMD_OPCODE_DYNAMIC_SYSTEM_INFORMATION 0x00000027 +#define NV_MSGBOX_CMD_OPCODE_GPU_PERFORMANCE_MONITORING 0x00000028 + +#define NV_MSGBOX_CMD_ARG1 15:8 +#define NV_MSGBOX_CMD_ARG1_NULL 0x00000000 +#define NV_MSGBOX_CMD_ARG1_TEMP_GPU_0 0x00000000 +#define NV_MSGBOX_CMD_ARG1_TEMP_NVSWITCH_0 0x00000000 +#define NV_MSGBOX_CMD_ARG1_TEMP_GPU_1 0x00000001 /* For Gemini boards */ +#define NV_MSGBOX_CMD_ARG1_TEMP_BOARD 0x00000004 +#define NV_MSGBOX_CMD_ARG1_TEMP_MEMORY 0x00000005 +#define NV_MSGBOX_CMD_ARG1_TEMP_PWR_SUPPLY 0x00000006 +#define NV_MSGBOX_CMD_ARG1_TEMP_T_LIMIT 0x00000007 +#define NV_MSGBOX_CMD_ARG1_TEMP_NUM_SENSORS 8 +#define NV_MSGBOX_CMD_ARG1_POWER_TOTAL 0x00000000 +#define NV_MSGBOX_CMD_ARG1_SMBPBI_POWER 0x00000001 +#define NV_MSGBOX_CMD_ARG1_POWER_FB 0x00000002 +#define NV_MSGBOX_CMD_ARG1_POWER_MODULE 0x00000003 +/* SysId info type encodings for opcode NV_MSGBOX_CMD_OPCODE_GET_SYS_ID_DATA (0x05) */ +#define NV_MSGBOX_CMD_ARG1_BOARD_PART_NUM_V1 0x00000000 +#define NV_MSGBOX_CMD_ARG1_OEM_INFO_V1 0x00000001 +#define NV_MSGBOX_CMD_ARG1_SERIAL_NUM_V1 0x00000002 +#define NV_MSGBOX_CMD_ARG1_MARKETING_NAME_V1 0x00000003 +#define NV_MSGBOX_CMD_ARG1_GPU_PART_NUM_V1 0x00000004 +#define NV_MSGBOX_CMD_ARG1_MEMORY_VENDOR_V1 0x00000005 +#define NV_MSGBOX_CMD_ARG1_MEMORY_PART_NUM_V1 0x00000006 +#define NV_MSGBOX_CMD_ARG1_BUILD_DATE_V1 0x00000007 +#define NV_MSGBOX_CMD_ARG1_FIRMWARE_VER_V1 0x00000008 +#define NV_MSGBOX_CMD_ARG1_VENDOR_ID_V1 0x00000009 +#define NV_MSGBOX_CMD_ARG1_DEV_ID_V1 0x0000000a +#define NV_MSGBOX_CMD_ARG1_SUB_VENDOR_ID_V1 0x0000000b +#define NV_MSGBOX_CMD_ARG1_SUB_ID_V1 0x0000000c +#define NV_MSGBOX_CMD_ARG1_GPU_GUID_V1 0x0000000d +#define NV_MSGBOX_CMD_ARG1_INFOROM_VER_V1 0x0000000e +#define NV_MSGBOX_CMD_ARG1_PRODUCT_LENGTH_V1 0x0000000f +#define NV_MSGBOX_CMD_ARG1_PRODUCT_WIDTH_V1 0x00000010 +#define NV_MSGBOX_CMD_ARG1_PRODUCT_HEIGHT_V1 0x00000011 +#define NV_MSGBOX_CMD_ARG1_PCIE_SPEED_V1 0x00000012 +#define NV_MSGBOX_CMD_ARG1_PCIE_WIDTH_V1 0x00000013 +#define NV_MSGBOX_CMD_ARG1_TGP_LIMIT_V1 0x00000014 +#define NV_MSGBOX_CMD_ARG1_FRU_PART_NUMBER_V1 0x00000015 +#define NV_MSGBOX_CMD_ARG1_MODULE_POWER_LIMIT_V1 0x00000016 +#define NV_MSGBOX_CMD_ARG1_MAX_DRAM_CAPACITY_V1 0x00000017 +#define NV_MSGBOX_CMD_ARG1_SYS_ID_DATA_TYPE_MAX 0x00000017 /* Adjust, when adding new types */ +#define NV_MSGBOX_CMD_ARG1_REGISTER_ACCESS_WRITE 0x00000000 +#define NV_MSGBOX_CMD_ARG1_REGISTER_ACCESS_READ 0x00000001 +#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_TARGET 0x00000000 +#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_HW_SLOWDN 0x00000001 +#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_SHUTDN 0x00000002 +#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_HBM_SLOWDN 0x00000003 +#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_SW_SLOWDN 0x00000004 +#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_TARGET_TLIMIT 0x00000005 +#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_HW_SLOWDN_TLIMIT 0x00000006 +#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_SHUTDN_TLIMIT 0x00000007 +#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_HBM_SLOWDN_TLIMIT 0x00000008 +#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_SW_SLOWDN_TLIMIT 0x00000009 +#define NV_MSGBOX_CMD_ARG1_GET_MISC_ECC_ENABLED_STATE 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GET_MISC_GPU_RESET_REQUIRED 0x00000001 +#define NV_MSGBOX_CMD_ARG1_GET_MISC_GPU_FLAGS_PAGE_0 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GET_MISC_GPU_FLAGS_PAGE_1 0x00000001 +#define NV_MSGBOX_CMD_ARG1_GET_MISC_DEVICE_FLAGS_PAGE_0 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GET_MISC_DEVICE_FLAGS_PAGE_1 0x00000001 + +#define NV_MSGBOX_CMD_ARG1_GPU_UTIL_COUNTERS_CONTEXT_TIME 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GPU_UTIL_COUNTERS_SM_TIME 0x00000001 +#define NV_MSGBOX_CMD_ARG1_GPU_UTIL_COUNTERS_RESET_COUNTERS 0x000000FF +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_LINK_COUNT 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_LINK_STATE_V1 0x00000001 +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_LINK_BANDWIDTH 0x00000002 +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_ERR_COUNTER_REPLAY 0x00000003 +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_ERR_COUNTER_RECOVERY 0x00000004 +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_ERR_COUNTER_FLIT_CRC 0x00000005 +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_ERR_COUNTER_DATA_CRC 0x00000006 +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_LINK_STATE_V2 0x00000007 +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_SUBLINK_WIDTH 0x00000008 +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_THROUGHPUT_DATA_TX 0x00000009 +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_THROUGHPUT_DATA_RX 0x0000000a +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_THROUGHPUT_RAW_TX 0x0000000b +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_THROUGHPUT_RAW_RX 0x0000000c +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_TRAINING_ERROR_STATE 0x0000000d +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_RUNTIME_ERROR_STATE 0x0000000e +#define NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_AVAILABILITY 0x0000000f +#define NV_MSGBOX_CMD_ARG1_GET_CLOCK_FREQ_INFO_CURRENT 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GET_CLOCK_FREQ_INFO_MIN 0x00000001 +#define NV_MSGBOX_CMD_ARG1_GET_CLOCK_FREQ_INFO_MAX 0x00000002 +#define NV_MSGBOX_CMD_ARG1_GET_CLOCK_FREQ_INFO_PAGE_3 0x00000003 +#define NV_MSGBOX_CMD_ARG1_GET_SUPPORTED_CLOCK_THROTTLE_REASONS 0x00000004 +#define NV_MSGBOX_CMD_ARG1_GET_CURRENT_CLOCK_THROTTLE_REASONS 0x00000005 +#define NV_MSGBOX_CMD_ARG1_REMAP_ROWS_RAW_COUNTS 0x00000000 +#define NV_MSGBOX_CMD_ARG1_REMAP_ROWS_STATE_FLAGS 0x00000001 +#define NV_MSGBOX_CMD_ARG1_REMAP_ROWS_HISTOGRAM 0x00000002 +#define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_0 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_1 0x00000001 +#define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_2 0x00000002 +#define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_3 0x00000003 +#define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_4 0x00000004 +#define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_6 0x00000006 +#define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_8 0x00000008 +#define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_9 0x00000009 + +/* Async requests */ +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_CONTROL_GET \ + 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_CONTROL_SET \ + 0x00000001 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_INFO_GET \ + 0x00000002 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_THERMAL_FAN_V1_COUNT_GET \ + 0x00000003 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_THERMAL_FAN_V1_INFO_GET \ + 0x00000004 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_THERMAL_FAN_V1_STATUS_GET \ + 0x00000005 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_OVERCLOCKING_LIMIT_CONTROL_GET \ + 0x00000006 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_OVERCLOCKING_LIMIT_CONTROL_SET \ + 0x00000007 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_ENERGY_COUNTER_STATUS_GET \ + 0x00000008 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_VIOLATION_COUNTERS_STATUS_GET \ + 0x00000009 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_UTILIZATION_RATE_GET \ + 0x0000000a +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_OOB_CLOCK_LIMIT_SET \ + 0x0000000b +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_DEVICE_MODE_CONTROL \ + 0x0000000c +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_TEST_MESSAGE_SEND \ + 0x0000000e +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_CLOCK_LIMIT_GET \ + 0x0000000d +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_FAN_CURVE_POINTS_GET_SET \ + 0x0000000f +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_POWER_HINT_GET \ + 0x00000010 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_CONFIGURE_PROGRAMMABLE_EDPP \ + 0x00000011 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_MODULE_LIMIT_CONTROL_GET \ + 0x00000012 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_MODULE_LIMIT_CONTROL_SET \ + 0x00000013 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_MODULE_LIMIT_INFO_GET \ + 0x00000014 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_MEMORY_CAPACITY_UTILIZATION_GET \ + 0x00000015 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_POLL 0x000000ff + + +#define NV_MSGBOX_CMD_ARG1_ECC_V2_SEL 15:14 +#define NV_MSGBOX_CMD_ARG1_ECC_V2_SEL_CNT 0x00000000 /* counters */ +#define NV_MSGBOX_CMD_ARG1_ECC_V2_SEL_FBA 0x00000001 /* FB addresses */ +/* Counters */ +#define NV_MSGBOX_CMD_ARG1_ECC_V2_CNT_DEV 13:12 +#define NV_MSGBOX_CMD_ARG1_ECC_V2_CNT_DEV_FB 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ECC_V2_CNT_DEV_GR 0x00000001 +#define NV_MSGBOX_CMD_ARG1_ECC_V2_CNT_FB_SRC 11:10 +#define NV_MSGBOX_CMD_ARG1_ECC_V2_CNT_FB_SRC_LTC 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ECC_V2_CNT_FB_SRC_FB 0x00000001 +#define NV_MSGBOX_CMD_ARG1_ECC_V2_CNT_GR_SRC 11:10 +#define NV_MSGBOX_CMD_ARG1_ECC_V2_CNT_GR_SRC_L1 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ECC_V2_CNT_GR_SRC_RF 0x00000001 +#define NV_MSGBOX_CMD_ARG1_ECC_V2_CNT_TYPE 9:8 +#define NV_MSGBOX_CMD_ARG1_ECC_V2_CNT_TYPE_SBE 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ECC_V2_CNT_TYPE_DBE 0x00000001 +/* FB addresses */ +#define NV_MSGBOX_CMD_ARG1_ECC_V2_FBA_SC 13:13 /* scope */ +#define NV_MSGBOX_CMD_ARG1_ECC_V2_FBA_SC_IND 0x00000000 /* individual addresses */ +#define NV_MSGBOX_CMD_ARG1_ECC_V2_FBA_SC_CUMUL 0x00000001 /* cumulative counters */ +#define NV_MSGBOX_CMD_ARG1_ECC_V2_FBA_IND_FLD 12:12 /* field */ +#define NV_MSGBOX_CMD_ARG1_ECC_V2_FBA_IND_FLD_CTRS 0x00000000 /* counters: sbe, dbe */ +#define NV_MSGBOX_CMD_ARG1_ECC_V2_FBA_IND_FLD_ADDR 0x00000001 /* address value */ +#define NV_MSGBOX_CMD_ARG1_ECC_V2_FBA_IND_INDEX 11:8 /* address array index: 0-13 */ + +#define NV_MSGBOX_CMD_ARG1_ECC_V3_SEL 15:14 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_SEL_CNT 0x00000000 /* counters */ +#define NV_MSGBOX_CMD_ARG1_ECC_V3_SEL_FBA 0x00000001 /* FB addresses */ +/* Counters */ +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_DEV 13:12 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_DEV_FB 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_DEV_GR 0x00000001 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_FB_SRC 11:10 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_FB_SRC_LTC 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_FB_SRC_FB 0x00000001 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_GR_SRC 11:10 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_GR_SRC_L1 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_GR_SRC_RF 0x00000001 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_GR_SRC_TEX 0x00000002 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_TYPE 9:8 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_TYPE_SBE 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ECC_V3_CNT_TYPE_DBE 0x00000001 +/* FB addresses */ +#define NV_MSGBOX_CMD_ARG1_ECC_V3_FBA_SC 13:13 /* scope */ +#define NV_MSGBOX_CMD_ARG1_ECC_V3_FBA_SC_IND 0x00000000 /* individual addresses */ +// These are not present in V3 +//#define NV_MSGBOX_CMD_ARG1_ECC_V3_FBA_SC_CUMUL 0x00000001 /* cumulative counters */ +#define NV_MSGBOX_CMD_ARG1_ECC_V3_FBA_IND_FLD 12:12 /* field */ +#define NV_MSGBOX_CMD_ARG1_ECC_V3_FBA_IND_FLD_CTRS 0x00000000 /* counters: sbe, dbe */ +#define NV_MSGBOX_CMD_ARG1_ECC_V3_FBA_IND_FLD_ADDR 0x00000001 /* address value */ +#define NV_MSGBOX_CMD_ARG1_ECC_V3_FBA_IND_INDEX 11:8 /* address array index: 0-13 */ + +#define NV_MSGBOX_CMD_ARG1_ECC_V4_SEL 15:14 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_SEL_CNT 0x00000000 /* counters */ +#define NV_MSGBOX_CMD_ARG1_ECC_V4_SEL_FBA 0x00000001 /* FB addresses */ +/* Counters */ +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_DEV 13:12 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_DEV_FB 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_DEV_GR 0x00000001 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_FB_SRC 11:10 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_FB_SRC_LTC 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_FB_SRC_FB 0x00000001 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_GR_SRC 11:10 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_GR_SRC_SHM 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_GR_SRC_RF 0x00000001 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_GR_SRC_TEX 0x00000002 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_TYPE 9:8 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_TYPE_SBE 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ECC_V4_CNT_TYPE_DBE 0x00000001 +/* FB addresses */ +#define NV_MSGBOX_CMD_ARG1_ECC_V4_FBA_SC 13:13 /* scope */ +#define NV_MSGBOX_CMD_ARG1_ECC_V4_FBA_SC_IND 0x00000000 /* individual addresses */ +// These are not present in V4 +//#define NV_MSGBOX_CMD_ARG1_ECC_V4_FBA_SC_CUMUL 0x00000001 /* cumulative counters */ +#define NV_MSGBOX_CMD_ARG1_ECC_V4_FBA_IND_FLD 12:12 /* field */ +#define NV_MSGBOX_CMD_ARG1_ECC_V4_FBA_IND_FLD_CTRS 0x00000000 /* counters: sbe, dbe */ +#define NV_MSGBOX_CMD_ARG1_ECC_V4_FBA_IND_FLD_ADDR 0x00000001 /* address value */ +#define NV_MSGBOX_CMD_ARG1_ECC_V4_FBA_IND_INDEX 11:8 /* address array index: 0-13 */ + +#define NV_MSGBOX_CMD_ARG1_ECC_V5_SEL 15:15 +#define NV_MSGBOX_CMD_ARG1_ECC_V5_SEL_COUNTS 0x00000000 /* address/region counts */ +#define NV_MSGBOX_CMD_ARG1_ECC_V5_SEL_ERR_BUFFER 0x00000001 /* SRAM error buffer */ + +#define NV_MSGBOX_CMD_ARG1_ECC_V5_COUNTS_INDEX_LO 14:8 /* 7 least significant index bits */ + +#define NV_MSGBOX_CMD_ARG1_ECC_V5_ERR_BUF_INDEX 11:8 /* buffer entry index */ + +#define NV_MSGBOX_CMD_ARG1_ACCESS_WP_MODE_ACTION 8:8 +#define NV_MSGBOX_CMD_ARG1_ACCESS_WP_MODE_ACTION_GET 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ACCESS_WP_MODE_ACTION_SET 0x00000001 + +#define NV_MSGBOX_CMD_ARG1_BUNDLE_REQUEST_COUNT 11:8 +#define NV_MSGBOX_CMD_ARG1_BUNDLE_DISP_RULE_COUNT 15:12 + +#define NV_MSGBOX_CMD_ARG1_GET_DEM_OLDEST 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GET_DEM_BY_SEQ_NUMBER 0x00000001 +#define NV_MSGBOX_CMD_ARG1_GET_DEM_BY_TIMESTAMP 0x00000002 + +#define NV_MSGBOX_CMD_ARG1_ECC_V6_ERROR_TYPE 15:8 +#define NV_MSGBOX_CMD_ARG1_ECC_V6_ERROR_TYPE_CORRECTABLE_ERROR 0 +#define NV_MSGBOX_CMD_ARG1_ECC_V6_ERROR_TYPE_UNCORRECTABLE_ERROR 1 +#define NV_MSGBOX_CMD_ARG1_ECC_V6_ERROR_TYPE_ECC_STATE_FLAGS 2 + +#define NV_MSGBOX_CMD_ARG1_ENERGY_COUNTER_GPU 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ENERGY_COUNTER_MODULE 0x00000003 + +// Query type of _GET_POWER_HINT_INFO +#define NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_CLK 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_TEMP 0x00000001 +#define NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_PROFILES 0x00000002 +#define NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_NUM \ + (NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_PROFILES + 1) + +// Arg1 for _GPU_PERFORMANCE_MONITORING +#define NV_MSGBOX_CMD_ARG1_GPM_ACTION 15:14 +#define NV_MSGBOX_CMD_ARG1_GPM_ACTION_GET_INSTANTANEOUS_METRIC 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GPM_ACTION_GET_SNAPSHOT_METRIC 0x00000001 +#define NV_MSGBOX_CMD_ARG1_GPM_ACTION_CAPTURE_SNAPSHOT 0x00000002 +#define NV_MSGBOX_CMD_ARG1_GPM_ACTION_SET_MULTIPLIER 0x00000003 + +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC 13:8 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_GRAPHICS_ENGINE 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_SM_ACTIVITY 0x00000001 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_SM_OCCUPANCY 0x00000002 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_TENSOR_CORE_ACTIVITY 0x00000003 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_DRAM_USAGE 0x00000004 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_FP64_ACTIVITY 0x00000005 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_FP32_ACTIVITY 0x00000006 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_FP16_ACTIVITY 0x00000007 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_PCIE_TX_BANDWIDTH 0x00000008 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_PCIE_RX_BANDWIDTH 0x00000009 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_TX_BANDWIDTH 0x0000000A +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_TX_BANDWIDTH 0x0000000B +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_RX_BANDWIDTH 0x0000000C +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_RX_BANDWIDTH 0x0000000D +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVDEC_UTILIZATION 0x0000000E +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVJPG_UTILIZATION 0x0000000F +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVOFA_UTILIZATION 0x00000010 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_TX_BW_PER_LINK 0x00000011 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_TX_BW_PER_LINK 0x00000012 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_RX_BW_PER_LINK 0x00000013 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_RX_BW_PER_LINK 0x00000014 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVDEC_UTIL_PER_INSTANCE 0x00000015 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVJPG_UTIL_PER_INSTANCE 0x00000016 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_INTEGER_UTILIZATION 0x00000017 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_DMMA_UTILIZATION 0x00000018 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_HMMA_UTILIZATION 0x00000019 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_IMMA_UTILIZATION 0x0000001A + +#define NV_MSGBOX_CMD_ARG1_DYN_SYS_INFO_DRIVER_VERSION_V1 0x00000000 + +#define NV_MSGBOX_CMD_ARG2 23:16 +#define NV_MSGBOX_CMD_ARG2_NULL 0x00000000 + +#define NV_MSGBOX_CMD_ARG2_ECC_V2_FB_PARTITION 23:20 +#define NV_MSGBOX_CMD_ARG2_ECC_V2_FB_SLICE 19:16 +#define NV_MSGBOX_CMD_ARG2_ECC_V2_GR_GPC 23:20 +#define NV_MSGBOX_CMD_ARG2_ECC_V2_GR_TPC 19:16 + +#define NV_MSGBOX_CMD_ARG2_ECC_V3_FB_PARTITION 23:20 +#define NV_MSGBOX_CMD_ARG2_ECC_V3_FB_SLICE 19:16 +#define NV_MSGBOX_CMD_ARG2_ECC_V3_FB_SUBPARTITION 19:16 +#define NV_MSGBOX_CMD_ARG2_ECC_V3_GR_TEX 23:22 +#define NV_MSGBOX_CMD_ARG2_ECC_V3_GR_GPC 21:19 +#define NV_MSGBOX_CMD_ARG2_ECC_V3_GR_TPC 18:16 + +#define NV_MSGBOX_CMD_ARG2_ECC_V4_FB_PARTITION 23:20 +#define NV_MSGBOX_CMD_ARG2_ECC_V4_FB_SLICE 19:16 +#define NV_MSGBOX_CMD_ARG2_ECC_V4_FB_SUBPARTITION 19:16 +#define NV_MSGBOX_CMD_ARG2_ECC_V4_GR_TEX 23:22 +#define NV_MSGBOX_CMD_ARG2_ECC_V4_GR_GPC 21:19 +#define NV_MSGBOX_CMD_ARG2_ECC_V4_GR_TPC 18:16 + +#define NV_MSGBOX_CMD_ARG2_ECC_V5_COUNTS_INDEX_HI 23:21 +#define NV_MSGBOX_CMD_ARG2_ECC_V5_COUNTS_TYPE 18:16 +#define NV_MSGBOX_CMD_ARG2_ECC_V5_COUNTS_TYPE_HDR_META 0x0 /* header and metadata */ + +#define NV_MSGBOX_CMD_ARG2_ECC_V5_COUNTS_TYPE_ADDR_ADDR 0x1 /* addr: address */ +#define NV_MSGBOX_CMD_ARG2_ECC_V5_COUNTS_TYPE_ADDR_UNCORRECTED_COUNTS 0x2 /* addr: uncorrectedCounts */ +#define NV_MSGBOX_CMD_ARG2_ECC_V5_COUNTS_TYPE_ADDR_CORRECTED_TOTAL 0x3 /* addr: correctedTotal */ +#define NV_MSGBOX_CMD_ARG2_ECC_V5_COUNTS_TYPE_ADDR_CORRECTED_UNIQUE 0x4 /* addr: correctedUnique */ + +#define NV_MSGBOX_CMD_ARG2_ECC_V5_COUNTS_TYPE_REGN_CORRECTED_TOTAL 0x1 /* region: correctedTotal */ +#define NV_MSGBOX_CMD_ARG2_ECC_V5_COUNTS_TYPE_REGN_CORRECTED_UNIQUE 0x2 /* region: correctedUnique */ +#define NV_MSGBOX_CMD_ARG2_ECC_V5_COUNTS_TYPE_REGN_UNCORRECTED_TOTAL 0x3 /* region: uncorrectedTotal */ +#define NV_MSGBOX_CMD_ARG2_ECC_V5_COUNTS_TYPE_REGN_UNCORRECTED_UNIQUE 0x4 /* region: uncorrectedUnique */ + +#define NV_MSGBOX_CMD_ARG2_ECC_V5_COUNTS_TYPE_MAX 0x4 + +#define NV_MSGBOX_CMD_ARG2_ECC_V5_ERR_BUF_TYPE 17:16 /* entry element type */ +#define NV_MSGBOX_CMD_ARG2_ECC_V5_ERR_BUF_TYPE_ERR_TYPE_META 0x0 /* errorType and metadata */ +#define NV_MSGBOX_CMD_ARG2_ECC_V5_ERR_BUF_TYPE_TIME_STAMP 0x1 /* time stamp */ +#define NV_MSGBOX_CMD_ARG2_ECC_V5_ERR_BUF_TYPE_ADDR 0x2 /* address */ + +#define NV_MSGBOX_CMD_ARG2_ECC_V5_ERR_BUF_TYPE_MAX 0x2 + +#define NV_MSGBOX_CMD_ARG2_REG_INDEX_SCRATCH_PAGE 0x00000000 +#define NV_MSGBOX_CMD_ARG2_REG_INDEX_EVENTS_PENDING 0x00000001 +#define NV_MSGBOX_CMD_ARG2_REG_INDEX_EVENT_MASK 0x00000002 +#define NV_MSGBOX_CMD_ARG2_REG_INDEX_MAX 0x00000002 /* increase when adding + new registers */ + +#define NV_MSGBOX_CMD_ARG2_NVLINK_INFO_AGGREGATE 0x000000FF + +#define NV_MSGBOX_CMD_ARG2_ACCESS_WP_MODE_SET_STATE 23:16 +#define NV_MSGBOX_CMD_ARG2_ACCESS_WP_MODE_SET_STATE_DISABLED 0x0000005A +#define NV_MSGBOX_CMD_ARG2_ACCESS_WP_MODE_SET_STATE_ENABLED 0x000000A5 + +#define NV_MSGBOX_CMD_ARG2_GET_CLOCK_FREQ_INFO_GPCCLK 0x00000000 +#define NV_MSGBOX_CMD_ARG2_GET_CLOCK_FREQ_INFO_MEMCLK 0x00000001 + +#define NV_MSGBOX_CMD_ARG2_ECC_V6_COUNTER_TYPE 23:16 +#define NV_MSGBOX_CMD_ARG2_ECC_V6_COUNTER_TYPE_SRAM 0 +#define NV_MSGBOX_CMD_ARG2_ECC_V6_COUNTER_TYPE_DRAM 1 + +#define NV_MSGBOX_CMD_ARG2_REMAP_ROW_RAW_CNT_COMBINED 0x00000000 +#define NV_MSGBOX_CMD_ARG2_REMAP_ROW_RAW_CNT_UNCORR 0x00000001 +#define NV_MSGBOX_CMD_ARG2_REMAP_ROW_RAW_CNT_CORR 0x00000002 + +#define NV_MSGBOX_CMD_ARG2_REMAP_ROWS_STATE_FLAGS_PAGE0 0x00000000 + +/*! + * Arg2 for _GET_PCIE_LINK_INFO + * Arg1 == _GET_PCIE_LINK_INFO_PAGE_8 + * Return TX EQ parameters + */ +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_8_LANE_IDX 3:0 +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_8_SPEED_SELECT 5:4 +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_8_SPEED_SELECT_GEN_3 \ + 0x00000000 +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_8_SPEED_SELECT_GEN_4 \ + 0x00000001 +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_8_SPEED_SELECT_GEN_5 \ + 0x00000002 + +/*! + * Arg2 for _GET_PCIE_LINK_INFO + * Arg1 == _GET_PCIE_LINK_INFO_PAGE_9 + * Return RX EQ parameters + */ +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_9_LANE_IDX 3:0 +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_9_SPEED_SELECT 5:4 +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_9_SPEED_SELECT_GEN_3 \ + 0x00000000 +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_9_SPEED_SELECT_GEN_4 \ + 0x00000001 +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_9_SPEED_SELECT_GEN_5 \ + 0x00000002 + +/*! + * Arg2 for _GET_POWER_HINT_INFO + * ARG1 == _GET_POWER_HINT_INFO_CLK + * Return Min/Max frequency in MHz + */ +#define NV_MSGBOX_CMD_ARG2_GET_POWER_HINT_INFO_CLK_GR 0x00000000 +#define NV_MSGBOX_CMD_ARG2_GET_POWER_HINT_INFO_CLK_MEM 0x00000001 + +/*! + * Arg2 for _GET_POWER_HINT_INFO + * ARG1 == _GET_POWER_HINT_INFO_PROFILES + * Return bits represents which profiles are available + */ +#define NV_MSGBOX_CMD_ARG2_GET_POWER_HINT_INFO_PROFILES_PAGE_0 0x00000000 +#define NV_MSGBOX_CMD_ARG2_GET_POWER_HINT_INFO_PROFILES_PAGE_1 0x00000001 +#define NV_MSGBOX_CMD_ARG2_GET_POWER_HINT_INFO_PROFILES_PAGE_2 0x00000002 +#define NV_MSGBOX_CMD_ARG2_GET_POWER_HINT_INFO_PROFILES_PAGE_3 0x00000003 +#define NV_MSGBOX_CMD_ARG2_GET_POWER_HINT_INFO_PROFILES_TOTAL_PAGES \ + (NV_MSGBOX_CMD_ARG2_GET_POWER_HINT_INFO_PROFILES_PAGE_3 + 1) + +// Arg2 for _GPU_PERFORMANCE_MONITORING +#define NV_MSGBOX_CMD_ARG2_GPM_PARTITION_AGGREGATE 0x000000FF +#define NV_MSGBOX_CMD_ARG2_GPM_PARTITION_INDEX 21:16 +#define NV_MSGBOX_CMD_ARG2_GPM_CI_METRICS_REQUESTED 23:23 +#define NV_MSGBOX_CMD_ARG2_GPM_CI_METRICS_REQUESTED_YES 0x00000001 +#define NV_MSGBOX_CMD_ARG2_GPM_CI_METRICS_REQUESTED_NO 0x00000000 + +#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER 23:16 +#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_1X 0x00000001 +#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_2X 0x00000002 +#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_5X 0x00000005 +#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_10X 0x0000000A +#define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_100X 0x00000064 + + +#define NV_MSGBOX_CMD_STATUS 28:24 +#define NV_MSGBOX_CMD_STATUS_NULL 0x00000000 +#define NV_MSGBOX_CMD_STATUS_ERR_REQUEST 0x00000001 +#define NV_MSGBOX_CMD_STATUS_ERR_OPCODE 0x00000002 +#define NV_MSGBOX_CMD_STATUS_ERR_ARG1 0x00000003 +#define NV_MSGBOX_CMD_STATUS_ERR_ARG2 0x00000004 +#define NV_MSGBOX_CMD_STATUS_ERR_DATA 0x00000005 +#define NV_MSGBOX_CMD_STATUS_ERR_MISC 0x00000006 +#define NV_MSGBOX_CMD_STATUS_ERR_I2C_ACCESS 0x00000007 +#define NV_MSGBOX_CMD_STATUS_ERR_NOT_SUPPORTED 0x00000008 +#define NV_MSGBOX_CMD_STATUS_ERR_NOT_AVAILABLE 0x00000009 +#define NV_MSGBOX_CMD_STATUS_ERR_BUSY 0x0000000a +#define NV_MSGBOX_CMD_STATUS_ERR_AGAIN 0x0000000b +#define NV_MSGBOX_CMD_STATUS_ERR_SENSOR_DATA 0x0000000c +#define NV_MSGBOX_CMD_STATUS_ERR_DISPOSITION 0x0000000d +#define NV_MSGBOX_CMD_STATUS_PARTIAL_FAILURE 0x0000001b +#define NV_MSGBOX_CMD_STATUS_ACCEPTED 0x0000001c +#define NV_MSGBOX_CMD_STATUS_INACTIVE 0x0000001d +#define NV_MSGBOX_CMD_STATUS_READY 0x0000001e +#define NV_MSGBOX_CMD_STATUS_SUCCESS 0x0000001f + +#define NV_MSGBOX_CMD_RSVD 29:29 +#define NV_MSGBOX_CMD_RSVD_INIT 0x00000000 + +#define NV_MSGBOX_CMD_COPY_DATA 30:30 +#define NV_MSGBOX_CMD_COPY_DATA_OFF 0x00000000 +#define NV_MSGBOX_CMD_COPY_DATA_ON 0x00000001 + +#define NV_MSGBOX_CMD_EVENT_PENDING 30:30 +#define NV_MSGBOX_CMD_EVENT_PENDING_OFF 0x00000000 +#define NV_MSGBOX_CMD_EVENT_PENDING_ON 0x00000001 + +#define NV_MSGBOX_CMD_INTR 31:31 +#define NV_MSGBOX_CMD_INTR_NOT_PENDING 0x00000000 +#define NV_MSGBOX_CMD_INTR_PENDING 0x00000001 +#define NV_MSGBOX_CMD_INTR_CLEAR 0x00000000 + +/* For individual requests in a bundle */ + +#define NV_MSGBOX_CMD_ON_BUNDLE_FAILURE 31:31 +#define NV_MSGBOX_CMD_ON_BUNDLE_FAILURE_CONTINUE 0x00000000 +#define NV_MSGBOX_CMD_ON_BUNDLE_FAILURE_STOP 0x00000001 + +#define NV_MSGBOX_CMD_DATA_COPY 23:0 +#define NV_MSGBOX_CMD_DATA_COPY_INIT 0x00000000 +#define NV_MSGBOX_CMD_EXT_STATUS 23:0 + +// NV_MSGBOX_CMD_COPY_SIZE_ENCODING used for certain commands to embed size +// indicators in the output when copy-bit is set in request + +#define NV_MSGBOX_CMD_COPY_SIZE_ENCODING_READ_DATA_OUT 0:0 +#define NV_MSGBOX_CMD_COPY_SIZE_ENCODING_READ_DATA_OUT_SET 1 +#define NV_MSGBOX_CMD_COPY_SIZE_ENCODING_READ_DATA_OUT_NOT_SET 0 + +#define NV_MSGBOX_CMD_COPY_SIZE_ENCODING_READ_EXT_DATA_OUT 1:1 +#define NV_MSGBOX_CMD_COPY_SIZE_ENCODING_READ_EXT_DATA_OUT_SET 1 +#define NV_MSGBOX_CMD_COPY_SIZE_ENCODING_READ_EXT_DATA_OUT_NOT_SET 0 + +#define NV_MSGBOX_CMD_COPY_SIZE_ENCODING_DATA 23:2 +#define NV_MSGBOX_CMD_COPY_SIZE_ENCODING_DATA_INIT 0x00000000 + +/* Response to NV_MSGBOX_CMD_ARG1_REMAP_ROWS_HISTOGRAM */ +#define NV_MSGBOX_CMD_REMAP_ROW_HISTOGRAM_NONE_AVAILABILITY 15:0 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_THROUGHPUT_* */ +#define NV_MSGBOX_CMD_NVLINK_INFO_THROUGHPUT_GRANULARITY 1:0 +#define NV_MSGBOX_CMD_NVLINK_INFO_THROUGHPUT_GRANULARITY_KIB 0x00000000 +#define NV_MSGBOX_CMD_NVLINK_INFO_THROUGHPUT_GRANULARITY_MIB 0x00000001 +#define NV_MSGBOX_CMD_NVLINK_INFO_THROUGHPUT_GRANULARITY_GIB 0x00000002 +#define NV_MSGBOX_CMD_NVLINK_INFO_THROUGHPUT_GRANULARITY_TIB 0x00000003 +#define NV_MSGBOX_CMD_NVLINK_INFO_THROUGHPUT_NEW_SAMPLE 2:2 +#define NV_MSGBOX_CMD_NVLINK_INFO_THROUGHPUT_NEW_SAMPLE_FALSE 0x00000000 +#define NV_MSGBOX_CMD_NVLINK_INFO_THROUGHPUT_NEW_SAMPLE_TRUE 0x00000001 +#define NV_MSGBOX_CMD_NVLINK_INFO_THROUGHPUT_INVALID_DELTA 3:3 +#define NV_MSGBOX_CMD_NVLINK_INFO_THROUGHPUT_INVALID_DELTA_FALSE 0x00000000 +#define NV_MSGBOX_CMD_NVLINK_INFO_THROUGHPUT_INVALID_DELTA_TRUE 0x00000001 +#define NV_MSGBOX_CMD_NVLINK_INFO_THROUGHPUT_DELTA 23:4 + +/* + * Response to NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_TRAINING_ERR_STATE + * NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_RUNTIME_ERR_STATE + */ +#define NV_MSGBOX_CMD_NVLINK_INFO_TRAINING_ERROR_COUNT 11:0 +#define NV_MSGBOX_CMD_NVLINK_INFO_RUNTIME_ERROR_COUNT 23:12 +#define NV_MSGBOX_CMD_NVLINK_INFO_ERROR_COUNT_MAX \ + DRF_MASK(NV_MSGBOX_CMD_NVLINK_INFO_TRAINING_ERROR_COUNT) + +/** + * Response to NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_AVAILABILITY + */ +#define NV_MSGBOX_CMD_NVLINK_INFO_GET_NVLINK_INFO_AVAILABILTY_PAGE_0 0x00000000 + +/** + * This field is populated as response to the following metrics: + * - NV_MSGBOX_CMD_ARG1_GPM_METRIC_DRAM_USAGE + * - NV_MSGBOX_CMD_ARG1_GPM_METRIC_PCIE_TX_BANDWIDTH + * - NV_MSGBOX_CMD_ARG1_GPM_METRIC_PCIE_RX_BANDWIDTH + * - NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_TX_BANDWIDTH + * - NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_TX_BANDWIDTH + * - NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_RX_BANDWIDTH + * - NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_RX_BANDWIDTH + */ +#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY 2:0 +#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY_B 0x00000000 +#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY_KIB 0x00000001 +#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY_MIB 0x00000002 +#define NV_MSGBOX_CMD_GPM_DATA_GRANULARITY_GIB 0x00000003 + +/* MSGBOX data, capability dword structure */ + +#define NV_MSGBOX_DATA_REG 31:0 +#define NV_MSGBOX_DATA_CAP_COUNT 6 + +#define NV_MSGBOX_DATA_CAP_0 0 +#define NV_MSGBOX_DATA_CAP_0_TEMP_GPU_0 0:0 +#define NV_MSGBOX_DATA_CAP_0_TEMP_GPU_0_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_TEMP_GPU_0_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_TEMP_NVSWITCH_0 0:0 +#define NV_MSGBOX_DATA_CAP_0_TEMP_NVSWITCH_0_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_TEMP_NVSWITCH_0_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_TEMP_GPU_1 1:1 +#define NV_MSGBOX_DATA_CAP_0_TEMP_GPU_1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_TEMP_GPU_1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_TEMP_BOARD 4:4 +#define NV_MSGBOX_DATA_CAP_0_TEMP_BOARD_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_TEMP_BOARD_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_TEMP_MEMORY 5:5 +#define NV_MSGBOX_DATA_CAP_0_TEMP_MEMORY_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_TEMP_MEMORY_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_TEMP_PWR_SUPPLY 6:6 +#define NV_MSGBOX_DATA_CAP_0_TEMP_PWR_SUPPLY_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_TEMP_PWR_SUPPLY_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_TEMP_T_LIMIT 7:7 +#define NV_MSGBOX_DATA_CAP_0_TEMP_T_LIMIT_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_TEMP_T_LIMIT_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS 11:8 +#define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS_ZERO 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS_ADT7473 0x00000002 +#define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS_SFXP11_5 0x00000005 +#define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS_SFXP24_8 0x00000008 +#define NV_MSGBOX_DATA_CAP_0_GET_ENERGY_COUNTER_MODULE 12:12 +#define NV_MSGBOX_DATA_CAP_0_GET_ENERGY_COUNTER_MODULE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_GET_ENERGY_COUNTER_MODULE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_CONTROL_GET 13:13 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_CONTROL_GET_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_CONTROL_GET_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_CONTROL_SET 14:14 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_CONTROL_SET_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_CONTROL_SET_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_INFO_GET 15:15 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_INFO_GET_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_INFO_GET_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_POWER_TOTAL 16:16 +#define NV_MSGBOX_DATA_CAP_0_POWER_TOTAL_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_POWER_TOTAL_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_GPU_PCONTROL 17:17 +#define NV_MSGBOX_DATA_CAP_0_GPU_PCONTROL_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_GPU_PCONTROL_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_GPU_SYSCONTROL 18:18 +#define NV_MSGBOX_DATA_CAP_0_GPU_SYSCONTROL_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_GPU_SYSCONTROL_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_THERMP_BITS 28:19 // Adjust when adding new bits +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_TLIMIT_BITS 23:19 // Adjust when adding new bits +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_BITS 28:24 // Adjust when adding new bits +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_ACOUSTIC_TLIMIT 19:19 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_ACOUSTIC_TLIMIT_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_ACOUSTIC_TLIMIT_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SLOWDN_TLIMIT 20:20 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SLOWDN_TLIMIT_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SLOWDN_TLIMIT_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SHUTDN_TLIMIT 21:21 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SHUTDN_TLIMIT_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SHUTDN_TLIMIT_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_MEMORY_TLIMIT 22:22 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_MEMORY_TLIMIT_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_MEMORY_TLIMIT_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_GPU_SW_SLOWDOWN_TLIMIT 23:23 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_GPU_SW_SLOWDOWN_TLIMIT_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_GPU_SW_SLOWDOWN_TLIMIT_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_ACOUSTIC 24:24 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_ACOUSTIC_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_ACOUSTIC_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SLOWDN 25:25 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SLOWDN_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SLOWDN_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SHUTDN 26:26 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SHUTDN_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SHUTDN_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_MEMORY 27:27 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_MEMORY_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_MEMORY_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_GPU_SW_SLOWDOWN 28:28 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_GPU_SW_SLOWDOWN_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_GPU_SW_SLOWDOWN_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_GET_FABRIC_STATE_FLAGS 29:29 +#define NV_MSGBOX_DATA_CAP_0_GET_FABRIC_STATE_FLAGS_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_GET_FABRIC_STATE_FLAGS_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_POWER_FB 30:30 +#define NV_MSGBOX_DATA_CAP_0_POWER_FB_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_POWER_FB_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_POWER_MODULE 31:31 +#define NV_MSGBOX_DATA_CAP_0_POWER_MODULE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_POWER_MODULE_AVAILABLE 0x00000001 + +#define NV_MSGBOX_DATA_CAP_1 1 +#define NV_MSGBOX_DATA_CAP_1_BOARD_PART_NUM_V1 0:0 +#define NV_MSGBOX_DATA_CAP_1_BOARD_PART_NUM_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_BOARD_PART_NUM_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_OEM_INFO_V1 1:1 +#define NV_MSGBOX_DATA_CAP_1_OEM_INFO_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_OEM_INFO_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_SERIAL_NUM_V1 2:2 +#define NV_MSGBOX_DATA_CAP_1_SERIAL_NUM_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_SERIAL_NUM_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_MARKETING_NAME_V1 3:3 +#define NV_MSGBOX_DATA_CAP_1_MARKETING_NAME_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_MARKETING_NAME_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_GPU_PART_NUM_V1 4:4 +#define NV_MSGBOX_DATA_CAP_1_GPU_PART_NUM_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_GPU_PART_NUM_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_MEMORY_VENDOR_V1 5:5 +#define NV_MSGBOX_DATA_CAP_1_MEMORY_VENDOR_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_MEMORY_VENDOR_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_MEMORY_PART_NUM_V1 6:6 +#define NV_MSGBOX_DATA_CAP_1_MEMORY_PART_NUM_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_MEMORY_PART_NUM_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_BUILD_DATE_V1 7:7 +#define NV_MSGBOX_DATA_CAP_1_BUILD_DATE_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_BUILD_DATE_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_FIRMWARE_VER_V1 8:8 +#define NV_MSGBOX_DATA_CAP_1_FIRMWARE_VER_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_FIRMWARE_VER_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_VENDOR_ID_V1 9:9 +#define NV_MSGBOX_DATA_CAP_1_VENDOR_ID_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_VENDOR_ID_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_DEV_ID_V1 10:10 +#define NV_MSGBOX_DATA_CAP_1_DEV_ID_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_DEV_ID_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_SUB_VENDOR_ID_V1 11:11 +#define NV_MSGBOX_DATA_CAP_1_SUB_VENDOR_ID_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_SUB_VENDOR_ID_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_SUB_ID_V1 12:12 +#define NV_MSGBOX_DATA_CAP_1_SUB_ID_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_SUB_ID_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_GPU_GUID_V1 13:13 +#define NV_MSGBOX_DATA_CAP_1_GPU_GUID_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_GPU_GUID_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_INFOROM_VER_V1 14:14 +#define NV_MSGBOX_DATA_CAP_1_INFOROM_VER_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_INFOROM_VER_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_MODULE_POWER_LIMIT_V1 15:15 +#define NV_MSGBOX_DATA_CAP_1_MODULE_POWER_LIMIT_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_MODULE_POWER_LIMIT_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_ECC_V1 16:16 +#define NV_MSGBOX_DATA_CAP_1_ECC_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_ECC_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_ECC_V2 17:17 +#define NV_MSGBOX_DATA_CAP_1_ECC_V2_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_ECC_V2_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_ECC_V3 18:18 +#define NV_MSGBOX_DATA_CAP_1_ECC_V3_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_ECC_V3_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_RET_PG_CNT 19:19 +#define NV_MSGBOX_DATA_CAP_1_RET_PG_CNT_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_RET_PG_CNT_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_ECC_V4 20:20 +#define NV_MSGBOX_DATA_CAP_1_ECC_V4_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_ECC_V4_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_ECC_V5 21:21 +#define NV_MSGBOX_DATA_CAP_1_ECC_V5_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_ECC_V5_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_ACCESS_WP_MODE 22:22 +#define NV_MSGBOX_DATA_CAP_1_ACCESS_WP_MODE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_ACCESS_WP_MODE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_GET_ECC_ENABLED_STATE 23:23 +#define NV_MSGBOX_DATA_CAP_1_GET_ECC_ENABLED_STATE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_GET_ECC_ENABLED_STATE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_GET_GPU_RESET_REQUIRED 24:24 +#define NV_MSGBOX_DATA_CAP_1_GET_GPU_RESET_REQUIRED_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_GET_GPU_RESET_REQUIRED_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_GPU_UTIL_COUNTERS 25:25 +#define NV_MSGBOX_DATA_CAP_1_GPU_UTIL_COUNTERS_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_GPU_UTIL_COUNTERS_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_NVLINK_INFO_STATE_V1 26:26 +#define NV_MSGBOX_DATA_CAP_1_NVLINK_INFO_STATE_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_NVLINK_INFO_STATE_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_NVLINK_ERROR_COUNTERS 27:27 +#define NV_MSGBOX_DATA_CAP_1_NVLINK_ERROR_COUNTERS_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_NVLINK_ERROR_COUNTERS_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_CLOCK_FREQ_INFO 28:28 +#define NV_MSGBOX_DATA_CAP_1_CLOCK_FREQ_INFO_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_CLOCK_FREQ_INFO_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_GET_MIG_ENABLED_STATE 29:29 +#define NV_MSGBOX_DATA_CAP_1_GET_MIG_ENABLED_STATE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_GET_MIG_ENABLED_STATE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_ECC_V6 30:30 +#define NV_MSGBOX_DATA_CAP_1_ECC_V6_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_ECC_V6_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_CLOCK_THROTTLE_REASON 31:31 +#define NV_MSGBOX_DATA_CAP_1_CLOCK_THROTTLE_REASON_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_CLOCK_THROTTLE_REASON_AVAILABLE 0x00000001 + +#define NV_MSGBOX_DATA_CAP_2 2 +#define NV_MSGBOX_DATA_CAP_2_GPU_DRIVER 0:0 +#define NV_MSGBOX_DATA_CAP_2_GPU_DRIVER_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_GPU_DRIVER_NOT_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_NVSWITCH_DRIVER 0:0 +#define NV_MSGBOX_DATA_CAP_2_NVSWITCH_DRIVER_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_NVSWITCH_DRIVER_NOT_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_GPU_REQUEST 1:1 +#define NV_MSGBOX_DATA_CAP_2_GPU_REQUEST_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_GPU_REQUEST_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_NUM_SCRATCH_BANKS 4:2 +#define NV_MSGBOX_DATA_CAP_2_NUM_SCRATCH_BANKS_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_FAN_V1_CONTROL 5:5 +#define NV_MSGBOX_DATA_CAP_2_FAN_V1_CONTROL_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_FAN_V1_CONTROL_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_PRODUCT_LENGTH_V1 6:6 +#define NV_MSGBOX_DATA_CAP_2_PRODUCT_LENGTH_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_PRODUCT_LENGTH_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_PRODUCT_WIDTH_V1 7:7 +#define NV_MSGBOX_DATA_CAP_2_PRODUCT_WIDTH_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_PRODUCT_WIDTH_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_PRODUCT_HEIGHT_V1 8:8 +#define NV_MSGBOX_DATA_CAP_2_PRODUCT_HEIGHT_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_PRODUCT_HEIGHT_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_PCIE_SPEED_V1 9:9 +#define NV_MSGBOX_DATA_CAP_2_PCIE_SPEED_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_PCIE_SPEED_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_PCIE_WIDTH_V1 10:10 +#define NV_MSGBOX_DATA_CAP_2_PCIE_WIDTH_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_PCIE_WIDTH_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_TGP_LIMIT_V1 11:11 +#define NV_MSGBOX_DATA_CAP_2_TGP_LIMIT_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_TGP_LIMIT_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_SCRATCH_PAGE_SIZE 12:12 +#define NV_MSGBOX_DATA_CAP_2_SCRATCH_PAGE_SIZE_1024B 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_SCRATCH_PAGE_SIZE_256B 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_REMAP_ROW_STATS 13:13 +#define NV_MSGBOX_DATA_CAP_2_REMAP_ROW_STATS_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_REMAP_ROW_STATS_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_GET_PCIE_LINK_INFO 14:14 +#define NV_MSGBOX_DATA_CAP_2_GET_PCIE_LINK_INFO_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_GET_PCIE_LINK_INFO_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_GET_GPU_DRAIN_AND_RESET_RECOMMENDED 15:15 +#define NV_MSGBOX_DATA_CAP_2_GET_GPU_DRAIN_AND_RESET_RECOMMENDED_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_GET_GPU_DRAIN_AND_RESET_RECOMMENDED_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_THROUGHPUT 16:16 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_THROUGHPUT_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_THROUGHPUT_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_LINK_STATE_V2 17:17 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_LINK_STATE_V2_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_LINK_STATE_V2_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_SUBLINK_WIDTH 18:18 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_SUBLINK_WIDTH_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_SUBLINK_WIDTH_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_GET_ENERGY_COUNTER 19:19 +#define NV_MSGBOX_DATA_CAP_2_GET_ENERGY_COUNTER_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_GET_ENERGY_COUNTER_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_REMAP_ROW_PENDING 20:20 +#define NV_MSGBOX_DATA_CAP_2_REMAP_ROW_PENDING_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_REMAP_ROW_PENDING_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_REMAP_ROW_HISTOGRAM 21:21 +#define NV_MSGBOX_DATA_CAP_2_REMAP_ROW_HISTOGRAM_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_REMAP_ROW_HISTOGRAM_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_TRAINING_ERROR_STATE 22:22 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_TRAINING_ERROR_STATE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_TRAINING_ERROR_STATE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_RUNTIME_ERROR_STATE 23:23 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_RUNTIME_ERROR_STATE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_RUNTIME_ERROR_STATE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_GET_PCIE_LINK_TARGET_SPEED 25:25 +#define NV_MSGBOX_DATA_CAP_2_GET_PCIE_LINK_TARGET_SPEED_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_GET_PCIE_LINK_TARGET_SPEED_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_CURRENT_PSTATE 26:26 +#define NV_MSGBOX_DATA_CAP_2_CURRENT_PSTATE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_CURRENT_PSTATE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_AVAILABILITY 27:27 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_AVAILABILITY_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_AVAILABILITY_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_FRU_PART_NUMBER_V1 31:31 +#define NV_MSGBOX_DATA_CAP_2_FRU_PART_NUMBER_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_FRU_PART_NUMBER_V1_AVAILABLE 0x00000001 + +#define NV_MSGBOX_DATA_CAP_4 4 +#define NV_MSGBOX_DATA_CAP_4_HW_VIOLATION_TIME 0:0 +#define NV_MSGBOX_DATA_CAP_4_HW_VIOLATION_TIME_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_HW_VIOLATION_TIME_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_SW_VIOLATION_TIME 1:1 +#define NV_MSGBOX_DATA_CAP_4_SW_VIOLATION_TIME_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_SW_VIOLATION_TIME_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_SW_POWER_VIOLATION_TIME 2:2 +#define NV_MSGBOX_DATA_CAP_4_SW_POWER_VIOLATION_TIME_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_SW_POWER_VIOLATION_TIME_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_SW_THERMAL_VIOLATION_TIME 3:3 +#define NV_MSGBOX_DATA_CAP_4_SW_THERMAL_VIOLATION_TIME_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_SW_THERMAL_VIOLATION_TIME_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_UTILIZATION_RATE 4:4 +#define NV_MSGBOX_DATA_CAP_4_UTILIZATION_RATE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_UTILIZATION_RATE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_GET_DRIVER_EVENT_MSG 5:5 +#define NV_MSGBOX_DATA_CAP_4_GET_DRIVER_EVENT_MSG_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_GET_DRIVER_EVENT_MSG_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_REQUEST_BUNDLING 6:6 +#define NV_MSGBOX_DATA_CAP_4_REQUEST_BUNDLING_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_REQUEST_BUNDLING_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_SET_DEVICE_DISABLE 7:7 +#define NV_MSGBOX_DATA_CAP_4_SET_DEVICE_DISABLE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_SET_DEVICE_DISABLE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_SET_ECC_MODE 8:8 +#define NV_MSGBOX_DATA_CAP_4_SET_ECC_MODE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_SET_ECC_MODE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_SET_MIG_MODE 10:10 +#define NV_MSGBOX_DATA_CAP_4_SET_MIG_MODE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_SET_MIG_MODE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_FAN_CURVE_POINTS_GET_SET 11:11 +#define NV_MSGBOX_DATA_CAP_4_FAN_CURVE_POINTS_GET_SET_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_FAN_CURVE_POINTS_GET_SET_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_POWER_HINT 22:22 +#define NV_MSGBOX_DATA_CAP_4_POWER_HINT_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_POWER_HINT_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_DRIVER_VERSION_V1 23:23 +#define NV_MSGBOX_DATA_CAP_4_DRIVER_VERSION_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_DRIVER_VERSION_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING 24:24 +#define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_DEM_BY_SEQNUM_TIMESTAMP 26:26 +#define NV_MSGBOX_DATA_CAP_4_DEM_BY_SEQNUM_TIMESTAMP_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_DEM_BY_SEQNUM_TIMESTAMP_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_CONFIGURE_PROGRAMMABLE_EDPP 30:30 +#define NV_MSGBOX_DATA_CAP_4_CONFIGURE_PROGRAMMABLE_EDPP_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_CONFIGURE_PROGRAMMABLE_EDPP_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_MAX_DRAM_CAPACITY_V1 31:31 +#define NV_MSGBOX_DATA_CAP_4_MAX_DRAM_CAPACITY_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_MAX_DRAM_CAPACITY_V1_AVAILABLE 0x00000001 + +#define NV_MSGBOX_DATA_CAP_5 5 +#define NV_MSGBOX_DATA_CAP_5_MEMORY_CAPACITY_UTILIZATION 6:6 +#define NV_MSGBOX_DATA_CAP_5_MEMORY_CAPACITY_UTILIZATION_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_5_MEMORY_CAPACITY_UTILIZATION_AVAILABLE 0x00000001 + +#define NV_MSGBOX_DATA_CAP_5_SRAM_ERROR_THRESHOLD_EXCEEDED 9:9 +#define NV_MSGBOX_DATA_CAP_5_SRAM_ERROR_THRESHOLD_EXCEEDED_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_5_SRAM_ERROR_THRESHOLD_EXCEEDED_AVAILABLE 0x00000001 + +/* ECC counters */ +#define NV_MSGBOX_DATA_ECC_CNT_16BIT_DBE 31:16 +#define NV_MSGBOX_DATA_ECC_CNT_16BIT_SBE 16:0 +#define NV_MSGBOX_DATA_ECC_CNT_8BIT_DBE 23:16 +#define NV_MSGBOX_DATA_ECC_CNT_8BIT_SBE 7:0 + +#define NV_MSGBOX_DATA_ECC_V5_COUNT_HEADER 7:0 + +#define NV_MSGBOX_DATA_ECC_V5_COUNT_HDR_ID 1:0 +#define NV_MSGBOX_DATA_ECC_V5_COUNT_HDR_ID_INVAL 0 +#define NV_MSGBOX_DATA_ECC_V5_COUNT_HDR_ID_ADDR 1 +#define NV_MSGBOX_DATA_ECC_V5_COUNT_HDR_ID_REGN 2 + +#define NV_MSGBOX_DATA_ECC_V5_COUNT_METADATA 31:16 + +#define NV_MSGBOX_DATA_ECC_V5_ERR_BUF_ERR_TYPE 7:0 + +#define NV_MSGBOX_DATA_ECC_V5_ERR_BUF_ERR_TYPE_ID 0:0 +#define NV_MSGBOX_DATA_ECC_V5_ERR_BUF_ERR_TYPE_ID_UNCORR 0 +#define NV_MSGBOX_DATA_ECC_V5_ERR_BUF_ERR_TYPE_ID_CORR 1 + +#define NV_MSGBOX_DATA_ECC_V5_ERR_BUF_METADATA 31:16 + +#define NV_MSGBOX_DATA_ECC_V5_METADATA_STRUCT_ID 21:16 +#define NV_MSGBOX_DATA_ECC_V5_METADATA_STRUCT_ID_LRF 0 +#define NV_MSGBOX_DATA_ECC_V5_METADATA_STRUCT_ID_L1DATA 1 +#define NV_MSGBOX_DATA_ECC_V5_METADATA_STRUCT_ID_L1TAG 2 +#define NV_MSGBOX_DATA_ECC_V5_METADATA_STRUCT_ID_CBU 3 +#define NV_MSGBOX_DATA_ECC_V5_METADATA_STRUCT_ID_LTC 4 +#define NV_MSGBOX_DATA_ECC_V5_METADATA_STRUCT_ID_DRAM 5 + +#define NV_MSGBOX_DATA_ECC_V5_METADATA_LOCATION_ID 26:22 +#define NV_MSGBOX_DATA_ECC_V5_METADATA_SUBLOCATION_ID 31:27 + +/* ECC state flags */ +#define NV_MSGBOX_DATA_ECC_V6_STATE_FLAGS 31:0 + +#define NV_MSGBOX_DATA_ECC_V6_STATE_FLAGS_SRAM_ERROR_THRESHOLD_EXCEEDED 0:0 +#define NV_MSGBOX_DATA_ECC_V6_STATE_FLAGS_SRAM_ERROR_THRESHOLD_EXCEEDED_FALSE 0 +#define NV_MSGBOX_DATA_ECC_V6_STATE_FLAGS_SRAM_ERROR_THRESHOLD_EXCEEDED_TRUE 1 + +/* NV_MSGBOX_CMD_OPCODE_SCRATCH_COPY src offset argument */ +#define NV_MSGBOX_DATA_COPY_SRC_OFFSET 7:0 + +/* NV_MSGBOX_CMD_ARG2_REG_INDEX_SCRATCH_PAGE register layout */ +#define NV_MSGBOX_DATA_SCRATCH_PAGE_DST 7:0 +#define NV_MSGBOX_DATA_SCRATCH_PAGE_SRC 15:8 + +/* Async request status codes returned in the data register */ +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS 7:0 + +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_SUCCESS 0x00000000 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_CARD_NOT_PRESENT 0x00000001 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_DUAL_LINK_INUSE 0x00000002 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_GENERIC 0x00000003 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_GPU_NOT_FULL_POWER 0x00000004 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_IN_USE 0x00000005 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INSUFFICIENT_RESOURCES 0x00000006 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_ACCESS_TYPE 0x00000007 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_ARGUMENT 0x00000008 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_BASE 0x00000009 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_CHANNEL 0x0000000A +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_CLASS 0x0000000B +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_CLIENT 0x0000000C +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_COMMAND 0x0000000D +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_DATA 0x0000000E +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_DEVICE 0x0000000F +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_DMA_SPECIFIER 0x00000010 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_EVENT 0x00000011 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_FLAGS 0x00000012 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_FUNCTION 0x00000013 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_HEAP 0x00000014 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_INDEX 0x00000015 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_LIMIT 0x00000016 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_METHOD 0x00000017 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_OBJECT_BUFFER 0x00000018 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_OBJECT_ERROR 0x00000019 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_OBJECT_HANDLE 0x0000001A +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_OBJECT_NEW 0x0000001B +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_OBJECT_OLD 0x0000001C +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_OBJECT_PARENT 0x0000001D +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_OFFSET 0x0000001E +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_OWNER 0x0000001F +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_PARAM_STRUCT 0x00000020 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_PARAMETER 0x00000021 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_POINTER 0x00000022 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_REGISTRY_KEY 0x00000023 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_STATE 0x00000024 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_STRING_LENGTH 0x00000025 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_XLATE 0x00000026 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_IRQ_NOT_FIRING 0x00000027 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_MULTIPLE_MEMORY_TYPES 0x00000028 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_NOT_SUPPORTED 0x00000029 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_OPERATING_SYSTEM 0x0000002A +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_PROTECTION_FAULT 0x0000002B +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_TIMEOUT 0x0000002C +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_TOO_MANY_PRIMARIES 0x0000002D +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_IRQ_EDGE_TRIGGERED 0x0000002E +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_OPERATION 0x0000002F +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_NOT_COMPATIBLE 0x00000030 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_MORE_PROCESSING_REQUIRED 0x00000031 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INSUFFICIENT_PERMISSIONS 0x00000032 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_TIMEOUT_RETRY 0x00000033 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_NOT_READY 0x00000034 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_GPU_IS_LOST 0x00000035 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_IN_FULLCHIP_RESET 0x00000036 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_LOCK_STATE 0x00000037 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_ADDRESS 0x00000038 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INVALID_IRQ_LEVEL 0x00000039 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_MEMORY_TRAINING_FAILED 0x00000040 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_BUSY_RETRY 0x00000041 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_INSUFFICIENT_POWER 0x00000042 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_OBJECT_NOT_FOUND 0x00000043 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_BUFFER_TOO_SMALL 0x00000044 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_RESET_REQUIRED 0x00000045 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_PRIV_SEC_VIOLATION 0x00000046 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_DEFERRED 0x00000047 +#define NV_MSGBOX_DATA_ASYNC_REQ_STATUS_ERROR_FREQ_NOT_SUPPORTED 0x00000048 + +/* Response to NV_MSGBOX_CMD_OPCODE_GET_POWER_CONNECTOR_STATE */ +#define NV_MSGBOX_DATA_POWER_CONNECTED 0:0 +#define NV_MSGBOX_DATA_POWER_CONNECTED_SUFFICIENT 0x00000000 +#define NV_MSGBOX_DATA_POWER_CONNECTED_INSUFFICIENT 0x00000001 + +/* Response to NV_MSGBOX_CMD_OPCODE_GET_PAGE_RETIREMENT_STATS */ +#define NV_MSGBOX_DATA_RETIRED_PAGES_CNT_SBE 7:0 +#define NV_MSGBOX_DATA_RETIRED_PAGES_CNT_DBE 15:8 + +/* + * Response to + * NV_MSGBOX_CMD_ARG1_GET_MISC_ECC_ENABLED_STATE + * NV_MSGBOX_CMD_ARG1_GET_MISC_GPU_FLAGS_PAGE_0 + */ +#define NV_MSGBOX_DATA_ECC_ENABLED_STATE_SUPPORTED 0:0 +#define NV_MSGBOX_DATA_ECC_ENABLED_STATE_SUPPORTED_OFF 0x00000000 +#define NV_MSGBOX_DATA_ECC_ENABLED_STATE_SUPPORTED_ON 0x00000001 +#define NV_MSGBOX_DATA_ECC_ENABLED_STATE_CURRENT 1:1 +#define NV_MSGBOX_DATA_ECC_ENABLED_STATE_CURRENT_OFF 0x00000000 +#define NV_MSGBOX_DATA_ECC_ENABLED_STATE_CURRENT_ON 0x00000001 +#define NV_MSGBOX_DATA_ECC_ENABLED_STATE_PENDING 2:2 +#define NV_MSGBOX_DATA_ECC_ENABLED_STATE_PENDING_OFF 0x00000000 +#define NV_MSGBOX_DATA_ECC_ENABLED_STATE_PENDING_ON 0x00000001 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_MISC_GPU_FLAGS_PAGE_0 */ +#define NV_MSGBOX_DATA_MIG_ENABLED_STATE_SUPPORTED 3:3 +#define NV_MSGBOX_DATA_MIG_ENABLED_STATE_SUPPORTED_OFF 0x00000000 +#define NV_MSGBOX_DATA_MIG_ENABLED_STATE_SUPPORTED_ON 0x00000001 +#define NV_MSGBOX_DATA_MIG_ENABLED_STATE_CURRENT 4:4 +#define NV_MSGBOX_DATA_MIG_ENABLED_STATE_CURRENT_OFF 0x00000000 +#define NV_MSGBOX_DATA_MIG_ENABLED_STATE_CURRENT_ON 0x00000001 +#define NV_MSGBOX_DATA_MIG_ENABLED_STATE_PENDING 5:5 +#define NV_MSGBOX_DATA_MIG_ENABLED_STATE_PENDING_OFF 0x00000000 +#define NV_MSGBOX_DATA_MIG_ENABLED_STATE_PENDING_ON 0x00000001 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_MISC_DEVICE_FLAGS_PAGE_0 */ +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DRIVER_STATUS 6:6 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DRIVER_STATUS_NOT_RUNNING 0x00000000 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DRIVER_STATUS_RUNNING 0x00000001 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DEVICE_STATUS 7:7 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DEVICE_STATUS_ENABLED 0x00000000 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DEVICE_STATUS_DISABLED 0x00000001 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_FABRIC_MANAGER_STATUS 10:8 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_FABRIC_MANAGER_STATUS_NOT_RUNNING 0x00000000 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_FABRIC_MANAGER_STATUS_RUNNING 0x00000001 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_FABRIC_MANAGER_STATUS_TIMEOUT 0x00000002 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_FABRIC_MANAGER_STATUS_ERROR 0x00000003 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DISABLE_SOURCE 13:11 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DISABLE_SOURCE_NONE 0x00000000 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DISABLE_SOURCE_LOCAL_DEVICE 0x00000001 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DISABLE_SOURCE_PEER_DEVICE 0x00000002 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DISABLE_SOURCE_IN_BAND 0x00000003 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DISABLE_SOURCE_OUT_OF_BAND 0x00000004 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DISABLE_REASON 16:14 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DISABLE_REASON_NONE 0x00000000 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DISABLE_REASON_CLIENT_OVERRIDE 0x00000001 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DISABLE_REASON_TRUNK_LINK_FAILED 0x00000002 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DISABLE_REASON_ACCESS_LINK_FAILED 0x00000003 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DISABLE_REASON_UNSPECIFIED_FAILURE 0x00000004 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DRIVER_RELOAD 17:17 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DRIVER_RELOAD_NOT_PENDING 0x00000000 +#define NV_MSGBOX_DATA_DEVICE_DISABLE_STATE_DRIVER_RELOAD_PENDING 0x00000001 + +/* Response to NV_MSGBOX_CMD_ARG1_ACCESS_WP_MODE_ACTION_GET */ +#define NV_MSGBOX_DATA_ACCESS_WP_MODE_GET_STATE 7:0 +#define NV_MSGBOX_DATA_ACCESS_WP_MODE_GET_STATE_DISABLED 0x0000005A +#define NV_MSGBOX_DATA_ACCESS_WP_MODE_GET_STATE_ENABLED 0x000000A5 + +/* + * Response to + * NV_MSGBOX_CMD_ARG1_GET_MISC_GPU_RESET_REQUIRED + * NV_MSGBOX_CMD_ARG1_GET_MISC_GPU_FLAGS_PAGE_1 + */ +#define NV_MSGBOX_DATA_GPU_RESET_REQUIRED 0:0 +#define NV_MSGBOX_DATA_GPU_RESET_REQUIRED_OFF 0x00000000 +#define NV_MSGBOX_DATA_GPU_RESET_REQUIRED_ON 0x00000001 +#define NV_MSGBOX_DATA_GPU_DRAIN_AND_RESET_RECOMMENDED 1:1 +#define NV_MSGBOX_DATA_GPU_DRAIN_AND_RESET_RECOMMENDED_NO 0x00000000 +#define NV_MSGBOX_DATA_GPU_DRAIN_AND_RESET_RECOMMENDED_YES 0x00000001 + +/** + * Response to + * NV_MSGBOX_CMD_ARG1_GET_CLOCK_FREQ_INFO_PAGE_3 + */ +#define NV_MSGBOX_DATA_GET_CLOCK_FREQ_INFO_PAGE_3_CURRENT_PSTATE 3:0 +#define NV_MSGBOX_DATA_GET_CLOCK_FREQ_INFO_PAGE_3_CURRENT_PSTATE_INVALID 0x0000000F + +/** + * Response to + * NV_MSGBOX_CMD_ARG1_GET_CLOCK_THROTTLE_REASON + */ +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON 31:0 +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_NONE 0x00000000 +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SW_POWER_CAP 0x00000001 +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_HW_SLOWDOWN 0x00000002 +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_HW_THERMAL_SLOWDOWN 0x00000004 +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_HW_POWER_BREAK_SLOWDOWN 0x00000008 +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SYNC_BOOST 0x00000010 +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SW_THERMAL_SLOWDOWN 0x00000020 + +/* + * Number of Nvlink data outputs (dataOut, extData) for + * NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_LINK queries + */ +#define NV_MSGBOX_DATA_NVLINK_INFO_DATA_WIDTH 2 + +/* + * Encoding for Invalid data + */ +#define NV_MSGBOX_DATA_NVLINK_INFO_DATA_INVALID 0xFFFFFFFF + +/* Response to NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_LINK_STATE_V1 */ +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V1__SIZE 32 +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V1_DOWN 0x00000000 +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V1_UP 0x00000001 +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V1_INVALID 0x000000ff + +/* Response to NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_LINK_STATE_V2 */ +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2(i) (3+(i)*4):(0+(i)*4) +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2__SIZE 8 +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2_OFF 0x00000000 +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2_SAFE 0x00000001 +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2_ACTIVE 0x00000002 +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2_ERROR 0x00000003 +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2_L1_LOW_POWER 0x00000004 +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2_NVLINK_DISABLED 0x00000005 +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2_INVALID 0x000000ff + +/* Response to NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_LINK_BANDWIDTH (in Mps) */ +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_BANDWIDTH__SIZE 1 +#define NV_MSGBOX_DATA_NVLINK_LINE_RATE_INVALID 0xFFFFFFFF +#define NV_MSGBOX_DATA_NVLINK_LINE_RATE_00000_MBPS 0 +#define NV_MSGBOX_DATA_NVLINK_LINE_RATE_16000_MBPS 16000 +#define NV_MSGBOX_DATA_NVLINK_LINE_RATE_19200_MBPS 19200 +#define NV_MSGBOX_DATA_NVLINK_LINE_RATE_20000_MBPS 20000 +#define NV_MSGBOX_DATA_NVLINK_LINE_RATE_25000_MBPS 25000 +#define NV_MSGBOX_DATA_NVLINK_LINE_RATE_25781_MBPS 25781 +#define NV_MSGBOX_DATA_NVLINK_LINE_RATE_32000_MBPS 32000 +#define NV_MSGBOX_DATA_NVLINK_LINE_RATE_40000_MBPS 40000 +#define NV_MSGBOX_DATA_NVLINK_LINE_RATE_50000_MBPS 50000 +#define NV_MSGBOX_DATA_NVLINK_LINE_RATE_53125_MBPS 53125 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_SUBLINK_WIDTH */ +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_WIDTH(i) (5+(i)*6):(0+(i)*6) +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_WIDTH__SIZE 5 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_WIDTH_INVALID 0x000000ff +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_TX_WIDTH 2:0 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_TX_WIDTH_0 0x00000000 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_TX_WIDTH_1 0x00000001 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_TX_WIDTH_2 0x00000002 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_TX_WIDTH_4 0x00000003 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_TX_WIDTH_8 0x00000004 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_TX_WIDTH_INVALID 0x00000007 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_RX_WIDTH 5:3 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_RX_WIDTH_0 0x00000000 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_RX_WIDTH_1 0x00000001 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_RX_WIDTH_2 0x00000002 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_RX_WIDTH_4 0x00000003 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_RX_WIDTH_8 0x00000004 +#define NV_MSGBOX_DATA_NVLINK_INFO_SUBLINK_RX_WIDTH_INVALID 0x00000007 + +/* + * Response to NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_TRAINING_ERR_STATE + * NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_RUNTIME_ERR_STATE + */ +#define NV_MSGBOX_DATA_NVLINK_INFO_ERROR_STATE__SIZE 32 +#define NV_MSGBOX_DATA_NVLINK_INFO_ERROR_STATE_INVALID 0x000000ff +#define NV_MSGBOX_DATA_NVLINK_INFO_ERROR_STATE_NO_ERROR 0x00000000 +#define NV_MSGBOX_DATA_NVLINK_INFO_ERROR_STATE_ERROR 0x00000001 + +/* Respones to NV_MSGBOX_CMD_ARG2_REMAP_ROW_RAW_CNT_COMBINED */ +#define NV_MSGBOX_DATA_REMAP_ROW_UNCORR_CNT 10:0 +#define NV_MSGBOX_DATA_REMAP_ROW_UNCORR_CNT_EXCESS 11:11 +#define NV_MSGBOX_DATA_REMAP_ROW_UNCORR_CNT_EXCESS_FALSE 0 +#define NV_MSGBOX_DATA_REMAP_ROW_UNCORR_CNT_EXCESS_TRUE 1 +#define NV_MSGBOX_DATA_REMAP_ROW_CORR_CNT 22:12 +#define NV_MSGBOX_DATA_REMAP_ROW_CORR_CNT_EXCESS 23:23 +#define NV_MSGBOX_DATA_REMAP_ROW_CORR_CNT_EXCESS_FALSE 0 +#define NV_MSGBOX_DATA_REMAP_ROW_CORR_CNT_EXCESS_TRUE 1 + +/* Response to NV_MSGBOX_CMD_ARG1_REMAP_ROWS_STATE_FLAGS */ +#define NV_MSGBOX_DATA_REMAP_ROW_STATE_FLAGS_PAGE0_FAILED_REMAPPING 0:0 +#define NV_MSGBOX_DATA_REMAP_ROW_STATE_FLAGS_PAGE0_FAILED_REMAPPING_FALSE 0 +#define NV_MSGBOX_DATA_REMAP_ROW_STATE_FLAGS_PAGE0_FAILED_REMAPPING_TRUE 1 +#define NV_MSGBOX_DATA_REMAP_ROW_STATE_FLAGS_PAGE0_PENDING_REMAPPING 1:1 +#define NV_MSGBOX_DATA_REMAP_ROW_STATE_FLAGS_PAGE0_PENDING_REMAPPING_FALSE 0 +#define NV_MSGBOX_DATA_REMAP_ROW_STATE_FLAGS_PAGE0_PENDING_REMAPPING_TRUE 1 + +/* Response to NV_MSGBOX_CMD_ARG1_REMAP_ROWS_HISTOGRAM */ +#define NV_MSGBOX_DATA_REMAP_ROW_HISTOGRAM_LOW_AVAILABILITY 15:0 +#define NV_MSGBOX_DATA_REMAP_ROW_HISTOGRAM_PARTIAL_AVAILABILITY 31:16 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_0 */ +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_SPEED 2:0 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_SPEED_UNKNOWN 0x00000000 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_SPEED_2500_MTPS 0x00000001 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_SPEED_5000_MTPS 0x00000002 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_SPEED_8000_MTPS 0x00000003 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_SPEED_16000_MTPS 0x00000004 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_SPEED_32000_MTPS 0x00000005 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_WIDTH 6:4 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_WIDTH_UNKNOWN 0x00000000 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_WIDTH_X1 0x00000001 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_WIDTH_X2 0x00000002 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_WIDTH_X4 0x00000003 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_WIDTH_X8 0x00000004 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_WIDTH_X16 0x00000005 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_WIDTH_X32 0x00000006 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_NONFATAL_ERROR_COUNT 15:8 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_FATAL_ERROR_COUNT 23:16 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_UNSUPP_REQ_COUNT 31:24 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_1 */ +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_1_L0_TO_RECOVERY_COUNT 31:0 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_2 */ +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_2_REPLAY_ROLLOVER_COUNT 15:0 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_2_NAKS_RCVD_COUNT 31:16 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_3 */ +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED 2:0 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_UNKNOWN 0x00000000 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_2500_MTPS 0x00000001 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_5000_MTPS 0x00000002 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_8000_MTPS 0x00000003 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_16000_MTPS 0x00000004 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_32000_MTPS 0x00000005 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_RESERVED 2:0 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_4 */ +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_4_TX_COUNT 31:0 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_6 */ +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE 4:0 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_DETECT 0x00000000 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_POLLING 0x00000001 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_CONFIGURATION 0x00000002 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_RECOVERY 0x00000003 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_RECOVERY_EQZN 0x00000004 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_L0 0x00000005 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_L0S 0x00000006 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_L1 0x00000007 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_L1_PLL_PD 0x00000008 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_L2 0x00000009 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_L1_CPM 0x0000000a +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_L1_1 0x0000000b +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_L1_2 0x0000000c +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_HOT_RESET 0x0000000d +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_LOOPBACK 0x0000000e +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_DISABLED 0x0000000f +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_LINK_DOWN 0x00000010 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_LINK_READY 0x00000011 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_LANES_IN_SLEEP 0x00000012 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_ILLEGAL 0x0000001f + +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_8 */ +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_8_EQ_TX_LOCAL_PRESET 3:0 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_8_EQ_TX_LOCAL_USE_PRESET 4:4 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_8_EQ_TX_LOCAL_FS 10:5 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_8_EQ_TX_LOCAL_LF 16:11 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_9 */ +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_9_EQ_RX_REMOTE_PRESET 3:0 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_9_EQ_RX_REMOTE_USE_PRESET 4:4 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_9_EQ_RX_REMOTE_FS 10:5 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_9_EQ_RX_REMOTE_LF 16:11 + +/* + * Input for NV_MSGBOX_CMD_OPCODE_GPU_PERFORMANCE_MONITORING. Value is valid + * only if Arg2 != GPM_PARTITION_AGGREGATE and Arg2.Bit7 == 1 + */ +#define NV_MSGBOX_DATA_GPM_COMPUTE_INSTANCE_INDEX 15:8 + +/* + * The following three fields correspond to the data which is interpreted + * differently depending on GPM Metric specified in Arg1. + */ +#define NV_MSGBOX_DATA_GPM_NVLINK_INDEX 7:0 +#define NV_MSGBOX_DATA_GPM_NVDEC_INSTANCE 7:0 +#define NV_MSGBOX_DATA_GPM_NVJPG_INSTANCE 7:0 + +/* MSGBOX Extended Data Register */ +#define NV_MSGBOX_EXT_DATA_REG 31:0 + +/* Respones to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_0 */ +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_0_CORRECTABLE_ERROR_COUNT 15:0 + +/* Respones to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_1 */ +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_1_REPLAY_COUNT 31:0 + +/* Respones to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_2 */ +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_2_NAKS_SENT_COUNT 15:0 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_4 */ +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_4_RX_COUNT 31:0 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_8 */ +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_8_EQ_TX_LOCAL_PRECUR 5:0 +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_8_EQ_TX_LOCAL_MAINCUR 11:6 +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_8_EQ_TX_LOCAL_POSTCUR 17:12 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_9 */ +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_9_EQ_RX_REMOTE_PRECUR 5:0 +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_9_EQ_RX_REMOTE_MAINCUR 11:6 +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_9_EQ_RX_REMOTE_POSTCUR 17:12 + +/* Response to NV_MSGBOX_CMD_ARG1_REMAP_ROWS_HISTOGRAM */ +#define NV_MSGBOX_EXT_DATA_REMAP_ROW_HISTOGRAM_MAX_AVAILABILITY 31:16 +#define NV_MSGBOX_EXT_DATA_REMAP_ROW_HISTOGRAM_HIGH_AVAILABILITY 15:0 + +/* SysId info per type sizes */ +#define NV_MSGBOX_SYSID_DATA_SIZE_BOARD_PART_NUM_V1 24 +#define NV_MSGBOX_SYSID_DATA_SIZE_OEM_INFO_V1 24 +#define NV_MSGBOX_SYSID_DATA_SIZE_SERIAL_NUM_V1 16 +#define NV_MSGBOX_SYSID_DATA_SIZE_MARKETING_NAME_V1 24 +#define NV_MSGBOX_SYSID_DATA_SIZE_GPU_PART_NUM_V1 16 +#define NV_MSGBOX_SYSID_DATA_SIZE_MEMORY_VENDOR_V1 1 +#define NV_MSGBOX_SYSID_DATA_SIZE_MEMORY_PART_NUM_V1 20 +#define NV_MSGBOX_SYSID_DATA_SIZE_BUILD_DATE_V1 4 +#define NV_MSGBOX_SYSID_DATA_SIZE_FIRMWARE_VER_V1 14 +#define NV_MSGBOX_SYSID_DATA_SIZE_VENDOR_ID_V1 2 +#define NV_MSGBOX_SYSID_DATA_SIZE_DEV_ID_V1 2 +#define NV_MSGBOX_SYSID_DATA_SIZE_SUB_VENDOR_ID_V1 2 +#define NV_MSGBOX_SYSID_DATA_SIZE_SUB_ID_V1 2 +#define NV_MSGBOX_SYSID_DATA_SIZE_GPU_GUID_V1 16 +#define NV_MSGBOX_SYSID_DATA_SIZE_INFOROM_VER_V1 16 +#define NV_MSGBOX_SYSID_DATA_SIZE_PRODUCT_LENGTH_V1 4 +#define NV_MSGBOX_SYSID_DATA_SIZE_PRODUCT_WIDTH_V1 4 +#define NV_MSGBOX_SYSID_DATA_SIZE_PRODUCT_HEIGHT_V1 4 +#define NV_MSGBOX_SYSID_DATA_SIZE_PCIE_SPEED_V1 1 +#define NV_MSGBOX_SYSID_DATA_SIZE_PCIE_WIDTH_V1 1 +#define NV_MSGBOX_SYSID_DATA_SIZE_TGP_LIMIT_V1 4 +#define NV_MSGBOX_SYSID_DATA_SIZE_FRU_PART_NUMBER_V1 20 +#define NV_MSGBOX_SYSID_DATA_SIZE_MODULE_POWER_LIMIT_V1 4 +#define NV_MSGBOX_SYSID_DATA_SIZE_MAX_DRAM_CAPACITY_V1 4 + +/*! + * Response to NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_CLK + * 16-bit frequency in MHz + */ +#define NV_MSGBOX_DATA_POWER_HINT_INFO_CLK_GR_MIN 15:0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_CLK_GR_MAX 31:16 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_CLK_MEM_MIN 15:0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_CLK_MEM_MAX 31:16 + +/*! + * Response to NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_TEMP + * 16-bit frequency in MHz + */ +#define NV_MSGBOX_DATA_POWER_HINT_INFO_TEMP_MIN 15:0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_TEMP_MAX 31:16 + +/*! + * Response to _ARG1_GET_POWER_HINT_INFO_PROFILES, 1 page consists of data and + * ext data, then we can support up to 256 profiles + * Bit index represents profile ID + */ +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_DMMA_PERF 0:0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_DMMA_PERF_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_DMMA_PERF_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_DMMA_HIGH_K 1:1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_DMMA_HIGH_K_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_DMMA_HIGH_K_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_DMMA_LOW_K 2:2 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_DMMA_LOW_K_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_DMMA_LOW_K_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_HMMA 3:3 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_HMMA_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_HMMA_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_IMMA 4:4 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_IMMA_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_IMMA_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_SGEMM 5:5 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_SGEMM_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_SGEMM_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_TRANSFORMER 6:6 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_TRANSFORMER_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_TRANSFORMER_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_0 7:7 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_0_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_0_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_1 8:8 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_1_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_1_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_2 9:9 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_2_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_2_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_3 10:10 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_3_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_3_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_4 11:11 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_4_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_4_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_5 12:12 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_5_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_5_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_6 13:13 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_6_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_6_AVAILABLE 1 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_7 14:14 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_7_NOT_AVAILABLE 0 +#define NV_MSGBOX_DATA_POWER_HINT_INFO_PROFILES_PAGE_0_CUSTOMER_CUSTOM_7_AVAILABLE 1 + +#define NV_MSGBOX_DATA_DYN_SYS_INFO_SIZE_DRIVER_VERSION 64 + +/* Event types */ +typedef enum +{ + NV_MSGBOX_EVENT_TYPE_SERVER_RESTART_COLD = 0, + NV_MSGBOX_EVENT_TYPE_GPU_RESET_REQUIRED, + NV_MSGBOX_EVENT_TYPE_DRIVER_ERROR_MESSAGE_OLDEST, + NV_MSGBOX_EVENT_TYPE_TGP_LIMIT_SET_SUCCESS, + NV_MSGBOX_EVENT_TYPE_CLOCK_LIMIT_SET_SUCCESS, + NV_MSGBOX_EVENT_TYPE_ECC_TOGGLE_SUCCESS, + NV_MSGBOX_EVENT_TYPE_MIG_TOGGLE_SUCCESS, + NV_MSGBOX_EVENT_TYPE_SERVER_RESTART_WARM, + NV_MSGBOX_EVENT_TYPE_DRIVER_ERROR_MESSAGE_NEW, + NV_MSGBOX_EVENT_TYPE_MODULE_LIMIT_SET_SUCCESS, + NV_MSGBOX_NUM_EVENTS, /* insert new event types before this line */ +} NvMsgboxEventType; + +/* Legacy event names for compatipility */ +#define NV_MSGBOX_EVENT_TYPE_SERVER_RESTART NV_MSGBOX_EVENT_TYPE_SERVER_RESTART_COLD +#define NV_MSGBOX_EVENT_TYPE_DRIVER_ERROR_MESSAGE NV_MSGBOX_EVENT_TYPE_DRIVER_ERROR_MESSAGE_OLDEST + +/* Bit mask of all defined events */ +#define NV_MSGBOX_EVENT_TYPE__ALL (NVBIT(NV_MSGBOX_NUM_EVENTS) - 1) + +/* ----------------------- Set Master Capabilities ---------------------------- */ + +// +// SET_MASTER_CAPS +// +// Descripiton: +// Set/declare SMBPBI Master capabilities. +// +// Common Encoding: +// 7 0 7 0 +// .-+-+-+-+-+-+-+-. .-+-+-+-+-+-+-+-. +// | CLASS | ARG1 | CAP_INDEX | ARG2 +// `-+-+-+-+-+-+-+-' `-+-+-+-+-+-+-+-' +// +// The SMBPBI Master capabilities are logically grouped into classes (specified +// in arg1). Capabilities are sent 32 at a time (dword index stored in arg2) +// per-class (typically once during system-initialization). +// +// Classes: +// _GPU_REQ - Class of capability bits corresponding 1:1 with the GPU- +// Request opcodes the master supports. +// +#define NV_MSGBOX_CMD_SET_MASTER_CAPS_ARG1_CLASS 7:0 +#define NV_MSGBOX_CMD_SET_MASTER_CAPS_ARG1_CLASS_GPU_REQ 0x00000000 + +#define NV_MSGBOX_DATA_MASTER_CAPS_GPU_REQ_COUNT 1 + +#define NV_MSGBOX_DATA_MASTER_CAPS_GPU_REQ_0 31:0 +#define NV_MSGBOX_DATA_MASTER_CAPS_GPU_REQ_0_CPU_PCONTROL 0:0 +#define NV_MSGBOX_DATA_MASTER_CAPS_GPU_REQ_0_CPU_PCONTROL_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_MASTER_CAPS_GPU_REQ_0_CPU_PCONTROL_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_MASTER_CAPS_GPU_REQ_0_SYS_PCONTROL 1:1 +#define NV_MSGBOX_DATA_MASTER_CAPS_GPU_REQ_0_SYS_PCONTROL_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_MASTER_CAPS_GPU_REQ_0_SYS_PCONTROL_AVAILABLE 0x00000001 + +/* ------------------ GPU Performance Control (PCONTROL) ---------------------- */ + +// +// GPU_PCONTROL arg1, arg2, and data encoding (fields are relative to zero, not +// relative to their position in the COMMAND/DATA registers). +// + +// +// ARG1/ARG2 Encoding +// +// 7 3 2 0 7 0 +// .-+-+-+-+-+-+-+-. .-+-+-+-+-+-+-+-. +// | TARGET | ACT | ARG1 |0 0 0 0 0 0 0 0| ARG2 (reserved) +// `-+-+-+-+-+-+-+-' `-+-+-+-+-+-+-+-' +// +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG1_ACTION 2:0 +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG1_ACTION_GET_INFO 0x00000000 +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG1_ACTION_GET_LIMIT 0x00000001 +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG1_ACTION_SET_LIMIT 0x00000002 +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG1_ACTION_GET_STATUS 0x00000003 +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG1_TARGET 7:3 +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG1_TARGET_VPSTATE 0x00000000 +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG1_TARGET_POWER_SMBIDX 0x00000001 +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG2_RSVD 7:0 + +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG1_SET_ACTION(arg1, action) \ + (arg1) = FLD_SET_DRF(_MSGBOX_CMD, _GPU_PCONTROL_ARG1, _ACTION, \ + action, (arg1)) + +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG1_GET_ACTION(arg1) \ + DRF_VAL(_MSGBOX_CMD, _GPU_PCONTROL_ARG1, _ACTION, (arg1)) + +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG1_SET_TARGET(arg1, target) \ + (arg1) = FLD_SET_DRF(_MSGBOX_CMD, _GPU_PCONTROL_ARG1, _TARGET, \ + target, (arg1)) + +#define NV_MSGBOX_CMD_GPU_PCONTROL_ARG1_GET_TARGET(arg1) \ + DRF_VAL(_MSGBOX_CMD, _GPU_PCONTROL_ARG1, _TARGET, (arg1)) + +// +// Getting GPU vPstate Information +// +// Inputs: +// ARG1 - {TARGET=VPSTATE, ACTION=GET_INFO} +// ARG2 - Unused/reserved (must be zero) +// +// Outputs: +// DATA - Current min/max range of externally available vpstates +// (vPmin=fastest, vPmax=slowest) +// +// Encoding: +// 31 16 15 8 7 0 +// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-. +// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| MIN | MAX | DATA +// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' +// +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_INFO_MAX 7:0 +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_INFO_MIN 15:8 +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_INFO_RSVD 31:16 + +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_INFO_SET_MAX(data, max) \ + (data) = FLD_SET_DRF_NUM(_MSGBOX_CMD, _GPU_PCONTROL_DATA, \ + _VPSTATE_GET_INFO_MAX, (max), (data)) + +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_INFO_GET_MAX(data) \ + DRF_VAL(_MSGBOX_CMD, _GPU_PCONTROL_DATA, _VPSTATE_GET_INFO_MAX, (data)) + +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_INFO_SET_MIN(data, min) \ + (data) = FLD_SET_DRF_NUM(_MSGBOX_CMD, _GPU_PCONTROL_DATA, \ + _VPSTATE_GET_INFO_MIN, (min), (data)) + +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_INFO_GET_MIN(data) \ + DRF_VAL(_MSGBOX_CMD, _GPU_PCONTROL_DATA, _VPSTATE_GET_INFO_MIN, (data)) + +// +// Getting GPU vPstate Limits +// +// Inputs: +// ARG1 - {TARGET=VPSTATE, ACTION=GET_LIMIT} +// ARG2 - Unused/reserved (must be zero) +// +// Outputs: +// DATA - Last requested vpstate limit/value, zero when no limit has been set. +// +// Encoding: +// 31 8 7 0 +// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-. +// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| VALUE | DATA +// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' +// +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_LIMIT_VALUE 7:0 +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_LIMIT_RSVD 31:8 + +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_LIMIT_SET_VALUE(data, value) \ + (data) = FLD_SET_DRF_NUM(_MSGBOX_CMD, _GPU_PCONTROL_DATA, \ + _VPSTATE_GET_LIMIT_VALUE, (value), (data)) + +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_LIMIT_GET_VALUE(data) \ + DRF_VAL(_MSGBOX_CMD, _GPU_PCONTROL_DATA, _VPSTATE_GET_LIMIT_VALUE, (data)) + +// +// Setting GPU vPstate Limits: +// +// Inputs: +// ARG1 - {TARGET=VPSTATE, ACTION=SET_LIMIT} +// ARG2 - Unused/reserved (must be zero) +// DATA - Desired vpstate limit/value between vPmin and vPmax (inclusive), +// zero to clear active limits. +// Outputs: +// none +// +// Encoding: +// 31 8 7 0 +// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-. +// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| VALUE | DATA +// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' +// +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_SET_LIMIT_VALUE 7:0 +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_SET_LIMIT_VALUE_CLEAR 0x00000000 +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_SET_LIMIT_VALUE_INIT 0x00000000 +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_SET_LIMIT_RSVD 31:8 + +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_SET_LIMIT_SET_VALUE(data, limit) \ + (data) = FLD_SET_DRF_NUM(_MSGBOX_CMD, _GPU_PCONTROL_DATA, \ + _VPSTATE_SET_LIMIT_VALUE, (limit), (data)) + +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_SET_LIMIT_GET_VALUE(data) \ + DRF_VAL(_MSGBOX_CMD, _GPU_PCONTROL_DATA, _VPSTATE_SET_LIMIT_VALUE, (data)) + +// +// Getting GPU vPstate Status +// +// Inputs: +// ARG1 - {TARGET=VPSTATE, ACTION=GET_STATUS} +// ARG2 - Unused/reserved (must be zero) +// +// Outputs: +// DATA - Current vPstate +// +// Encoding: +// 31 8 7 0 +// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-. +// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CURRENT | DATA +// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' +// +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_STATUS_CURRENT 7:0 +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_STATUS_RSVD 31:8 + +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_STATUS_SET_CURRENT(data, curr) \ + (data) = FLD_SET_DRF_NUM(_MSGBOX_CMD, _GPU_PCONTROL_DATA, \ + _VPSTATE_GET_STATUS_CURRENT, (curr), (data)) + +#define NV_MSGBOX_CMD_GPU_PCONTROL_DATA_VPSTATE_GET_STATUS_GET_CURRENT(data) \ + DRF_VAL(_MSGBOX_CMD, _GPU_PCONTROL_DATA, _VPSTATE_GET_STATUS_CURRENT, (data)) + + +/* ------------------------- GPU System Control ------------------------------- */ + +// +// GPU_SYSCONTROL +// +// Description: +// Command sent to the GPU to set/remove a system-imposed operating limit +// on a specific system-parameter. +// +// Common Encoding: +// 7 2 1 0 7 0 +// .-+-+-+-+-+-+-+-. .-+-+-+-+-+-+-+-. +// | TARGET |ACT| ARG1 |0 0 0 0 0 0 0 0| ARG2 (reserved) +// `-+-+-+-+-+-+-+-' `-+-+-+-+-+-+-+-' +// +// Notes: +// - TARGET accepts NV0000_CTRL_SYSTEM_PARAM_* definitions +// - arg1, arg2, and data encoding (fields are relative to zero, not relative +// to their position in the DATA_OUT register). +// +#define NV_MSGBOX_CMD_GPU_SYSCONTROL_ARG1_ACTION 1:0 +#define NV_MSGBOX_CMD_GPU_SYSCONTROL_ARG1_ACTION_CLEAR_LIMIT 0x00000000 +#define NV_MSGBOX_CMD_GPU_SYSCONTROL_ARG1_ACTION_SET_LIMIT 0x00000001 +#define NV_MSGBOX_CMD_GPU_SYSCONTROL_ARG1_TARGET 7:2 +#define NV_MSGBOX_CMD_GPU_SYSCONTROL_ARG2_RSVD 7:0 + +#define NV_MSGBOX_CMD_GPU_SYSCONTROL_ARG1_SET_ACTION(arg1, action) \ + (arg1) = FLD_SET_DRF(_MSGBOX_CMD, _GPU_SYSCONTROL_ARG1, _ACTION, \ + action, (arg1)) + +#define NV_MSGBOX_CMD_GPU_SYSCONTROL_ARG1_GET_ACTION(arg1) \ + DRF_VAL(_MSGBOX_CMD, _GPU_SYSCONTROL_ARG1, _ACTION, (arg1)) + +#define NV_MSGBOX_CMD_GPU_SYSCONTROL_ARG1_SET_TARGET(arg1, target) \ + (arg1) = FLD_SET_DRF_NUM(_MSGBOX_CMD, _GPU_SYSCONTROL_ARG1, _TARGET, \ + target, (arg1)) + +#define NV_MSGBOX_CMD_GPU_SYSCONTROL_ARG1_GET_TARGET(arg1) \ + DRF_VAL(_MSGBOX_CMD, _GPU_SYSCONTROL_ARG1, _TARGET, (arg1)) + +// +// Setting a System-Parameter Operating-Limit: +// +// Inputs: +// ARG1 - {TARGET=NV_MSGBOX_SYS_PARAM_*, ACTION=SET_LIMIT} +// ARG2 - Unused/reserved (must be zero) +// DATA - Desired limit/value. +// +// Outputs: +// none +// +// Encoding: +// 31 0 +// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-. +// | VALUE | DATA +// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' +// +#define NV_MSGBOX_CMD_GPU_SYSCONTROL_DATA_SET_LIMIT_VALUE 31:0 + +#define NV_MSGBOX_CMD_GPU_SYSCONTROL_DATA_SET_LIMIT_SET_VALUE(data, limit) \ + (data) = FLD_SET_DRF_NUM(_MSGBOX_CMD, _GPU_SYSCONTROL_DATA, \ + _SET_LIMIT_VALUE, (limit), (data)) + +#define NV_MSGBOX_CMD_GPU_SYSCONTROL_DATA_PARAM_SET_LIMIT_GET_VALUE(data) \ + DRF_VAL(_MSGBOX_CMD, _GPU_SYSCONTROL_DATA, _SET_LIMIT_VALUE, (data)) + +// +// Host side scratch memory buffer +// This memory buffer is allocated by the host CPU in its system memory +// and is used for passing additional arguments and results, that don't +// fit in the command/status and data registers due to their size. +// This memory can be accessed by the BMC SMBus master through +// dedicated requests. +// +// Page size is various on different SMBPBI servers. +// Capability dword[2] bit 12 shows size in bytes +// +// _1024 --> 0xFF dwords +// _256 --> 0x40 dowrds +// +#define NV_MSGBOX_SCRATCH_PAGE_SIZE_1024_D 0xFF +#define NV_MSGBOX_SCRATCH_PAGE_SIZE_256_D 0x40 + +// +// TODO Once switch soc/pmu/oobtest remove the reference to this, this will be +// removed. +// +#define NV_MSGBOX_SCRATCH_PAGE_SIZE 1024 +#define NV_MSGBOX_SCRATCH_NUM_PAGES_P 2 // expressed as a power of 2 + // must be >= 2 + +// This cap code plugs into NV_MSGBOX_DATA_CAP_2_NUM_SCRATCH_BANKS +#define NV_MSGBOX_SCRATCH_NUM_PAGES_CAP_CODE \ + (NV_MSGBOX_SCRATCH_NUM_PAGES_P > 0 ? \ + NV_MSGBOX_SCRATCH_NUM_PAGES_P - 1 : 0) + +#define NV_MSGBOX_SCRATCH_NUM_PAGES (1 << NV_MSGBOX_SCRATCH_NUM_PAGES_P) +#define NV_MSGBOX_SCRATCH_BUFFER_SIZE (NV_MSGBOX_SCRATCH_NUM_PAGES \ + * NV_MSGBOX_SCRATCH_PAGE_SIZE) + +// Auxiliary definitions related to NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_STATE_SPEED +#define NV_MSGBOX_NVLINK_STATE_BITS_PER_NVLINK 4 +#define NV_MSGBOX_NVLINK_STATE_NVLINKS_PER_REGISTER (32 / NV_MSGBOX_NVLINK_STATE_BITS_PER_NVLINK) +#define NV_MSGBOX_NVLINK_STATE_NUM_NVLINKS_VOLTA 6 +#define NV_MSGBOX_NVLINK_STATE_NUM_NVLINKS_TURING 2 +#define NV_MSGBOX_NVLINK_STATE_NUM_NVLIPT_GA100 3 +#define NV_MSGBOX_NVLINK_STATE_NUM_LINKS_PER_NVLIPT_NVL30 4 +#define NV_MSGBOX_NVLINK_SUBLINK_WIDTH_MAX_NVL30 4 +#define NV_MSGBOX_NVLINK_STATE_NUM_NVLINKS_GA100 \ + (NV_MSGBOX_NVLINK_STATE_NUM_NVLIPT_GA100 * \ + NV_MSGBOX_NVLINK_STATE_NUM_LINKS_PER_NVLIPT_NVL30) +#define NV_MSGBOX_NVLINK_STATE_NUM_NVLIPT_GA10X 1 +#define NV_MSGBOX_NVLINK_STATE_NUM_NVLINKS_GA10X \ + (NV_MSGBOX_NVLINK_STATE_NUM_NVLIPT_GA10X * \ + NV_MSGBOX_NVLINK_STATE_NUM_LINKS_PER_NVLIPT_NVL30) +#define NV_MSGBOX_NVLINK_STATE_NUM_NVLIPT_LR10 9 +#define NV_MSGBOX_NVLINK_STATE_NUM_NVLINKS_LR10 \ + (NV_MSGBOX_NVLINK_STATE_NUM_NVLIPT_LR10 * \ + NV_MSGBOX_NVLINK_STATE_NUM_LINKS_PER_NVLIPT_NVL30) +#define NV_MSGBOX_NVLINK_STATE_NUM_REGISTERS(arch) \ + ((NV_MSGBOX_NVLINK_STATE_NUM_NVLINKS##arch + NV_MSGBOX_NVLINK_STATE_NVLINKS_PER_REGISTER - 1) \ + / NV_MSGBOX_NVLINK_STATE_NVLINKS_PER_REGISTER) + +// Auxiliary definitions related to NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_THROUGHPUT_* +#define NV_MSGBOX_NVLINK_THROUGHPUT_COUNTER_INDEX_DATA_TX 0x00000000 +#define NV_MSGBOX_NVLINK_THROUGHPUT_COUNTER_INDEX_DATA_RX 0x00000001 +#define NV_MSGBOX_NVLINK_THROUGHPUT_COUNTER_INDEX_RAW_TX 0x00000002 +#define NV_MSGBOX_NVLINK_THROUGHPUT_COUNTER_INDEX_RAW_RX 0x00000003 +#define NV_MSGBOX_NVLINK_THROUGHPUT_COUNTER_INDEX_MAX 0x00000004 + +#if !defined(NV_MSGBOX_NO_PARAM_STRUCTS) +// +// Parameter structures for asynchronous requests +// passed in scratch space +// + +/*! + * This structure is used to hold parameters for + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_CONTROL_GET, + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_CONTROL_SET, + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_MODULE_LIMIT_CONTROL_GET and + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_MODULE_LIMIT_CONTROL_SET + */ +typedef struct +{ + NvU32 flags; + /*! + * If flags:_PERSIST is _ON, make limitCurrInput persistent, + * surviving the driver reload and the system reboot. + * + * If flags:_CLEAR is _ON, it will clear the TGP limit. The + * persistence still depends on persist flag. + */ +#define NV_MSGBOX_PMGR_PWR_POWER_LIMIT_CONTROL_PARAMS_FLAGS_PERSIST 0:0 +#define NV_MSGBOX_PMGR_PWR_POWER_LIMIT_CONTROL_PARAMS_FLAGS_PERSIST_OFF 0x00000000 +#define NV_MSGBOX_PMGR_PWR_POWER_LIMIT_CONTROL_PARAMS_FLAGS_PERSIST_ON 0x00000001 +#define NV_MSGBOX_PMGR_PWR_POWER_LIMIT_CONTROL_PARAMS_FLAGS_CLEAR 1:1 +#define NV_MSGBOX_PMGR_PWR_POWER_LIMIT_CONTROL_PARAMS_FLAGS_CLEAR_OFF 0x00000000 +#define NV_MSGBOX_PMGR_PWR_POWER_LIMIT_CONTROL_PARAMS_FLAGS_CLEAR_ON 0x00000001 + + /*! + * Current total GPU power limit value to enforce, requested by the + * SMBPBI client, expressed in milliwatts. + * Must always be within range imposed by the current policy. + * 0xffffffff is returned, if the limit has not been set by the SMBPBI client. + */ + NvU32 limitCurrInput; + + /*! + * Currently arbitrated total GPU power limit value after taking + * into account limits, requested by all clients, expressed + * in milliwatts. + */ + NvU32 limitCurrOutput; +} NV_MSGBOX_PMGR_PWR_POWER_LIMIT_CONTROL_PARAMS; + +/*! + * This structure is used to hold parameters for + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_INFO_GET and + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_MODULE_LIMIT_INFO_GET + */ +typedef struct +{ + /*! + * Current total GPU power limit lower and upper bounds and the + * default setting, expressed in milliwatts. + * These constraints must be observed, when the limit + * is being set with either + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_CONTROL_SET or + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_MODULE_LIMIT_CONTROL_SET. + */ + NvU32 limitMin; + NvU32 limitMax; + NvU32 limitDefault; +} NV_MSGBOX_PMGR_PWR_POWER_LIMIT_INFO_PARAMS; + +/*! + * This structure is used to hold parameters for + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_THERMAL_FAN_V1_COUNT_GET + */ +typedef struct +{ + NvU32 fanCount; // POLICY - add types below +#define NV_MSGBOX_VIOLATION_COUNTERS_TYPE_ALL_SUPPORTED_POLICIES 0xFFFFFFFF //-1 represents All Supported policies +#define NV_MSGBOX_VIOLATION_COUNTERS_TYPE_HW_VIOLATION 0 +#define NV_MSGBOX_VIOLATION_COUNTERS_TYPE_SW_GLOBAL_VIOLATION 1 +#define NV_MSGBOX_VIOLATION_COUNTERS_TYPE_SW_POWER_VIOLATION 2 +#define NV_MSGBOX_VIOLATION_COUNTERS_TYPE_SW_THERMAL_VIOLATION 3 + + NV_DECLARE_ALIGNED(NvU64 violationTime[32], 8); //. + */ +typedef struct +{ + NvU32 flags; + /*! + * If flags: _CLEAR is _ON, it will clear the limits. Otherwise, + * set the clock limits. + * + * If flags: _PERSIST is _ON, set/clear limits persistently, + * surviving the driver reload and the system reboot. + * + */ +#define NV_MSGBOX_OOB_CLOCK_LIMIT_CTRL_PARAMS_FLAGS_PERSIST 0:0 +#define NV_MSGBOX_OOB_CLOCK_LIMIT_CTRL_PARAMS_FLAGS_PERSIST_OFF 0x00000000 +#define NV_MSGBOX_OOB_CLOCK_LIMIT_CTRL_PARAMS_FLAGS_PERSIST_ON 0x00000001 +#define NV_MSGBOX_OOB_CLOCK_LIMIT_CTRL_PARAMS_FLAGS_CLEAR 1:1 +#define NV_MSGBOX_OOB_CLOCK_LIMIT_CTRL_PARAMS_FLAGS_CLEAR_OFF 0x00000000 +#define NV_MSGBOX_OOB_CLOCK_LIMIT_CTRL_PARAMS_FLAGS_CLEAR_ON 0x00000001 + + /*! + * Graphics clock limit in MHz + */ + NvU32 clkMinFreqMHz; + NvU32 clkMaxFreqMHz; +} NV_MSGBOX_OOB_CLOCK_LIMIT_CTRL_PARAMS; + +/*! + * This structure is used to hold parameters for + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_MEMORY_CAPACITY_UTILIZATION_GET + */ +typedef struct +{ + NvU32 capacityReservedMiB; //. + */ +typedef struct { + /*! + * Graphics clock limit in MHz + * if there is no cap, return + * NV_MSGBOX_CLOCK_LIMIT_GET_PARAMS_CLOCK_LIMIT_NOT_SET + */ + NvU16 oobClientMin; + NvU16 oobClientMax; + NvU16 enforcedMin; + NvU16 enforcedMax; +#define NV_MSGBOX_CLOCK_LIMIT_GET_PARAMS_CLOCK_LIMIT_NOT_SET 0xffff +} NV_MSGBOX_CLOCK_LIMIT_GET_PARAMS; + +/*! + * This structure is used to hold parameters for + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_DEVICE_MODE_CONTROL + */ +typedef struct +{ + NvU16 modeType; //> 7) \ + ) +#define NV_MSGBOX_ECC_V5_COUNTS_NUM_ENTRIES 600 + +#define NV_MSGBOX_CMD_ECC_V5_CNT_HDR_META(index) \ + ( \ + NV_MSGBOX_CMD_ECC_V5_CNT(index) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_COUNTS_TYPE, _HDR_META) \ + ) + +#define NV_MSGBOX_CMD_ECC_V5_CNT_REGN_CORRECTED_TOTAL(index) \ + ( \ + NV_MSGBOX_CMD_ECC_V5_CNT(index) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_COUNTS_TYPE, _REGN_CORRECTED_TOTAL) \ + ) + +#define NV_MSGBOX_CMD_ECC_V5_CNT_REGN_CORRECTED_UNIQUE(index) \ + ( \ + NV_MSGBOX_CMD_ECC_V5_CNT(index) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_COUNTS_TYPE, _REGN_CORRECTED_UNIQUE) \ + ) + +#define NV_MSGBOX_CMD_ECC_V5_CNT_REGN_UNCORRECTED_TOTAL(index) \ + ( \ + NV_MSGBOX_CMD_ECC_V5_CNT(index) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_COUNTS_TYPE, _REGN_UNCORRECTED_TOTAL) \ + ) + +#define NV_MSGBOX_CMD_ECC_V5_CNT_REGN_UNCORRECTED_UNIQUE(index) \ + ( \ + NV_MSGBOX_CMD_ECC_V5_CNT(index) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_COUNTS_TYPE, _REGN_UNCORRECTED_UNIQUE) \ + ) + +#define NV_MSGBOX_CMD_ECC_V5_CNT_ADDR_ADDR(index) \ + ( \ + NV_MSGBOX_CMD_ECC_V5_CNT(index) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_COUNTS_TYPE, _ADDR_ADDR) \ + ) + +#define NV_MSGBOX_CMD_ECC_V5_CNT_ADDR_UNCORRECTED_COUNTS(index) \ + ( \ + NV_MSGBOX_CMD_ECC_V5_CNT(index) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_COUNTS_TYPE, _ADDR_UNCORRECTED_COUNTS) \ + ) + +#define NV_MSGBOX_CMD_ECC_V5_CNT_ADDR_CORRECTED_TOTAL(index) \ + ( \ + NV_MSGBOX_CMD_ECC_V5_CNT(index) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_COUNTS_TYPE, _ADDR_CORRECTED_TOTAL) \ + ) + +#define NV_MSGBOX_CMD_ECC_V5_CNT_ADDR_CORRECTED_UNIQUE(index) \ + ( \ + NV_MSGBOX_CMD_ECC_V5_CNT(index) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_COUNTS_TYPE, _ADDR_CORRECTED_UNIQUE) \ + ) + +#define NV_MSGBOX_CMD_ECC_V5_ERR_BUF(index) \ + ( \ + NV_MSGBOX_CMD(_GET_ECC_V5, 0, 0) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG1_ECC_V5_SEL, _ERR_BUFFER) | \ + DRF_NUM(_MSGBOX, _CMD, _ARG1_ECC_V5_ERR_BUF_INDEX, (index)) \ + ) +#define NV_MSGBOX_ECC_V5_ERR_BUF_NUM_ENTRIES 16 + +#define NV_MSGBOX_CMD_ECC_V5_ERR_BUF_ERR_TYPE_META(index) \ + ( \ + NV_MSGBOX_CMD_ECC_V5_ERR_BUF(index) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_ERR_BUF_TYPE, _ERR_TYPE_META) \ + ) + +#define NV_MSGBOX_CMD_ECC_V5_ERR_BUF_TIME_STAMP(index) \ + ( \ + NV_MSGBOX_CMD_ECC_V5_ERR_BUF(index) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_ERR_BUF_TYPE, _TIME_STAMP) \ + ) + +#define NV_MSGBOX_CMD_ECC_V5_ERR_BUF_ADDR(index) \ + ( \ + NV_MSGBOX_CMD_ECC_V5_ERR_BUF(index) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2_ECC_V5_ERR_BUF_TYPE, _ADDR) \ + ) + +#define NV_MSGBOX_CMD_SET_COPY_DATA(cmd) \ + ( \ + FLD_SET_DRF(_MSGBOX, _CMD, _COPY_DATA, _ON, (cmd)) \ + ) + +#define NV_MSGBOX_CMD_GET_PCIE_LINK_INFO_1(page) \ + ( \ + NV_MSGBOX_CMD(_GET_PCIE_LINK_INFO, \ + (page), \ + 0) \ + ) + +// We use the fact here that for pages ## 8 and 9 Arg2 definitions are similar +#define NV_MSGBOX_CMD_GET_PCIE_LINK_INFO_2(page, lane, speed) \ + ( \ + NV_MSGBOX_CMD(_GET_PCIE_LINK_INFO, \ + (page), \ + DRF_NUM(_MSGBOX, _CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_8, \ + _LANE_IDX, (lane)) | \ + DRF_NUM(_MSGBOX, _CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_8, \ + _SPEED_SELECT, (speed))) \ + ) + +#define NV_MSGBOX_CMD_GPM_GET_METRIC(type, metric, req_ci_metrics, partition) \ + ( \ + NV_MSGBOX_CMD(_GPU_PERFORMANCE_MONITORING, 0, 0) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_ACTION, type) | \ + DRF_NUM(_MSGBOX, _CMD, _ARG1_GPM_METRIC, metric) | \ + DRF_NUM(_MSGBOX, _CMD, _ARG2_GPM_CI_METRICS_REQUESTED, req_ci_metrics) | \ + DRF_NUM(_MSGBOX, _CMD, _ARG2_GPM_PARTITION_INDEX, partition) \ + ) + +#define NV_MSGBOX_CMD_GPM_GET_METRIC_AGGREGATE(type, metric) \ + ( \ + NV_MSGBOX_CMD(_GPU_PERFORMANCE_MONITORING, 0, 0) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_ACTION, type) | \ + DRF_NUM(_MSGBOX, _CMD, _ARG1_GPM_METRIC, metric) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG2, _GPM_PARTITION_AGGREGATE) \ + ) + +#define NV_MSGBOX_DATA_IN_GPM(instance_id, ci_index) \ + ( \ + DRF_NUM(_MSGBOX, _DATA, _GPM_NVDEC_INSTANCE, instance_id) | \ + DRF_NUM(_MSGBOX, _DATA, _GPM_COMPUTE_INSTANCE_INDEX, ci_index) \ + ) + +#define NV_MSGBOX_CMD_GPM_SET_MULTIPLIER(multiplier) \ + ( \ + NV_MSGBOX_CMD(_GPU_PERFORMANCE_MONITORING, 0, 0) | \ + DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_ACTION, _SET_MULTIPLIER) | \ + DRF_NUM(_MSGBOX, _CMD, _ARG2_GPM_MULTIPLIER, (multiplier)) \ + ) + +#define NV_MSGBOX_GET_CMD_OPCODE(cmd) DRF_VAL(_MSGBOX, _CMD, _OPCODE, (cmd)) +#define NV_MSGBOX_GET_CMD_ARG1(cmd) DRF_VAL(_MSGBOX, _CMD, _ARG1 , (cmd)) +#define NV_MSGBOX_GET_CMD_ARG2(cmd) DRF_VAL(_MSGBOX, _CMD, _ARG2 , (cmd)) +#define NV_MSGBOX_GET_CMD_STATUS(cmd) DRF_VAL(_MSGBOX, _CMD, _STATUS, (cmd)) +#define NV_MSGBOX_CMD_IS_COPY_DATA_SET(cmd) \ + FLD_TEST_DRF(_MSGBOX, _CMD, _COPY_DATA, _ON, (cmd)) + +#define NV_MSGBOX_CAP_IS_AVAILABLE(caps, idx, name) \ + !(FLD_TEST_DRF(_MSGBOX, _DATA_CAP_##idx, name, _NOT_AVAILABLE, (caps)[idx])) + +#define NV_MSGBOX_CAP_SET_AVAILABLE(caps, idx, name) \ + (caps)[idx] = FLD_SET_DRF(_MSGBOX, _DATA_CAP_##idx, name, _AVAILABLE, \ + (caps)[idx]) + +/******************************************************************************** + * * + * GPU REQUESTS * + * * + ********************************************************************************/ + +// +// Encoding: +// 31 24 23 16 15 8 7 0 +// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-. +// | REQUEST ID | ARG2 | ARG1 | OPCODE | DATA_OUT +// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' +// +#define NV_MSGBOX_REQ_OPCODE 7:0 +#define NV_MSGBOX_REQ_OPCODE_CPU_PCONTROL 0x00000000 +#define NV_MSGBOX_REQ_OPCODE_SYS_PCONTROL 0x00000001 +#define NV_MSGBOX_REQ_ARG1 15:8 +#define NV_MSGBOX_REQ_ARG2 23:16 +#define NV_MSGBOX_REQ_REQUEST_ID 31:24 +#define NV_MSGBOX_REQ(opcode, arg1, arg2, requestId) \ + ( \ + DRF_NUM(_MSGBOX, _REQ, _OPCODE , (opcode)) | \ + DRF_NUM(_MSGBOX, _REQ, _ARG1 , (arg1)) | \ + DRF_NUM(_MSGBOX, _REQ, _ARG2 , (arg2)) | \ + DRF_NUM(_MSGBOX, _REQ, _REQUEST_ID, (requestId)) \ + ) + +/* ---------------- CPU Performance Control (PCONTROL) ------------------------ */ + +// +// CPU_PCONTROL +// +// Description: +// GPU-Request used to retrieve information and control various aspects of +// CPU performance. +// +// Common Encoding: +// 7 3 2 0 +// .-+-+-+-+-+-+-+-. +// | TARGET | ACT | ARG1 +// `-+-+-+-+-+-+-+-' +// +// Notes: +// arg1, arg2, and data encoding (fields are relative to zero, not relative +// to their position in the DATA_OUT register). +// +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG1_ACTION 2:0 +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG1_ACTION_RSVD1 0x00000000 +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG1_ACTION_RSVD2 0x00000001 +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG1_ACTION_SET_LIMIT 0x00000002 +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG1_TARGET 7:3 +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG1_TARGET_PSTATE 0x00000000 + +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG1_SET_ACTION(arg1, action) \ + (arg1) = FLD_SET_DRF(_MSGBOX_REQ, _CPU_PCONTROL_ARG1, _ACTION, \ + action, (arg1)) + +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG1_GET_ACTION(arg1) \ + DRF_VAL(_MSGBOX_REQ, _CPU_PCONTROL_ARG1, _ACTION, (arg1)) + +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG1_SET_TARGET(arg1, target) \ + (arg1) = FLD_SET_DRF(_MSGBOX_REQ, _CPU_PCONTROL_ARG1, _TARGET, \ + target, (arg1)) + +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG1_GET_TARGET(arg1) \ + DRF_VAL(_MSGBOX_REQ, _CPU_PCONTROL_ARG1, _TARGET, (arg1)) + +// +// Setting CPU Pstate Limits: +// +// Inputs: +// ARG1 - {TARGET=PSTATE, ACTION=SET_LIMIT} +// ARG2 - Stores desired CPU Pstate limit +// +// Outputs: +// none +// +// Encoding: +// 7 3 2 0 7 0 +// .-+-+-+-+-+-+-+-. .-+-+-+-+-+-+-+-. +// | TARGET | ACT | ARG1 | VALUE | ARG2 +// `-+-+-+-+-+-+-+-' `-+-+-+-+-+-+-+-' +// +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG2_PSTATE_SET_LIMIT_VALUE 7:0 + +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG2_PSTATE_SET_LIMIT_SET_VALUE(arg2, limit) \ + (arg2) = FLD_SET_DRF_NUM(_MSGBOX_REQ, _CPU_PCONTROL_ARG2, \ + _PSTATE_SET_LIMIT_VALUE, (limit), (arg2)) + +#define NV_MSGBOX_REQ_CPU_PCONTROL_ARG2_PSTATE_SET_LIMIT_GET_VALUE(arg2) \ + DRF_VAL(_MSGBOX_REQ, _CPU_PCONTROL_ARG2, _PSTATE_SET_LIMIT_VALUE, (arg2)) + +/* ----------------------- System Performance Control ------------------------- */ + +// +// SYS_PCONTROL +// +// Description: +// GPU-Request used to retrieve information and control various aspects of +// system-performance. +// +// Common Encoding: +// 7 3 2 0 7 0 +// .-+-+-+-+-+-+-+-. .-+-+-+-+-+-+-+-. +// | TARGET | ACT | ARG1 |0 0 0 0 0 0 0 0| ARG2 (reserved) +// `-+-+-+-+-+-+-+-' `-+-+-+-+-+-+-+-' +// +// Notes: +// - TARGET accepts NV0000_CTRL_SYSTEM_PARAM_* definitions +// - arg1, arg2, and data encoding (fields are relative to zero, not relative +// to their position in the DATA_OUT register). +// +#define NV_MSGBOX_REQ_SYS_PCONTROL_ARG1_ACTION 2:0 +#define NV_MSGBOX_REQ_SYS_PCONTROL_ARG1_ACTION_GET_STATUS 0x00000000 +#define NV_MSGBOX_REQ_SYS_PCONTROL_ARG1_ACTION_GET_LIMIT 0x00000001 +#define NV_MSGBOX_REQ_SYS_PCONTROL_ARG1_TARGET 7:3 +#define NV_MSGBOX_REQ_SYS_PCONTROL_ARG2_RSVD 7:0 + +#define NV_MSGBOX_REQ_SYS_PCONTROL_ARG1_SET_ACTION(arg1, action) \ + (arg1) = FLD_SET_DRF(_MSGBOX_REQ, _SYS_PCONTROL_ARG1, _ACTION, \ + action, (arg1)) + +#define NV_MSGBOX_REQ_SYS_PCONTROL_ARG1_GET_ACTION(arg1) \ + DRF_VAL(_MSGBOX_REQ, _SYS_PCONTROL_ARG1, _ACTION, (arg1)) + +#define NV_MSGBOX_REQ_SYS_PCONTROL_ARG1_SET_TARGET(arg1, target) \ + (arg1) = FLD_SET_DRF_NUM(_MSGBOX_REQ, _SYS_PCONTROL_ARG1, _TARGET, \ + (target), (arg1)) + +#define NV_MSGBOX_REQ_SYS_PCONTROL_ARG1_GET_TARGET(arg1) \ + DRF_VAL(_MSGBOX_REQ, _SYS_PCONTROL_ARG1, _TARGET, (arg1)) + +#endif /* _SMBPBI_H */ diff --git a/userspace/sdks/nv570/nvalloc/common/inc/oob/smbpbi_impl.h b/userspace/sdks/nv570/nvalloc/common/inc/oob/smbpbi_impl.h new file mode 100644 index 0000000..e7052c8 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/oob/smbpbi_impl.h @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef _SMBPBI_IMPL_H +#define _SMBPBI_IMPL_H +/*! + * This header file stores implementation dependent parameters of the SMBPBI server. + */ + +/*! + * Maximum number of individual requests in a bundle + */ +#define NV_MSGBOX_PARAM_MAX_BUNDLE_SIZE 4 + +/*! + * Maximum number of Result Disposition Rules + */ +#define NV_MSGBOX_PARAM_MAX_DISP_RULES 10 + +/*! + * Maximum length of the Driver Event Message text string is 80, including + * the terminating NUL character. + */ +#define NV_MSGBOX_MAX_DRIVER_EVENT_MSG_TXT_SIZE 80 + +#endif // _SMBPBI_IMPL_H diff --git a/userspace/sdks/nv570/nvalloc/common/inc/oob/smbpbi_priv.h b/userspace/sdks/nv570/nvalloc/common/inc/oob/smbpbi_priv.h new file mode 100644 index 0000000..53b48da --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/oob/smbpbi_priv.h @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _SMBPBI_PRIV_H_ +#define _SMBPBI_PRIV_H_ + +/*! + * This file contains NVIDIA private defines for the SMBPBI + * interface. + */ + +#include "oob/smbpbi.h" + +// MSGBOX command word structure + +// +// Reserving opcodes above 0xC0 for internal/private functionationality. +// +// These opcodes should not be included in any documentation we release outside +// of NVIDIA! +// + +// +// Only for internal use (should not be written to the command register). Used +// for internal tracking when commands are redirected to the RM from the PMU. +// +#define NV_MSGBOX_CMD_ERR_MORE_PROCESSING_REQUIRED 0x000000F0 + +// +// Alternative encodings of the command word. +// These were distinguished by a non-zero value in the 29:29 bit. +// Bit 29 is now reserved and must be 0 i.e. only standard requests will be processed +// and debug requests would fail. +// +#define NV_MSGBOX_CMD_ENCODING 29:29 +#define NV_MSGBOX_CMD_ENCODING_STANDARD 0x00000000 + +#endif // _SMBPBI_PRIV_H_ + diff --git a/userspace/sdks/nv570/nvalloc/common/inc/rmRiscvUcode.h b/userspace/sdks/nv570/nvalloc/common/inc/rmRiscvUcode.h new file mode 100644 index 0000000..d2e4259 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/rmRiscvUcode.h @@ -0,0 +1,95 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * << DO NOT EDIT >> + * + * This file describes the format of generated ucode binary. Please do not change the + * content unless the same change is applied to the target ucode builds. + */ + +#ifndef RM_RISCV_UCODE_H +#define RM_RISCV_UCODE_H + +#include "nvtypes.h" + +typedef struct { + // + // Version 1 + // Version 2 + // Version 3 = for Partition boot + // Version 4 = for eb riscv boot + // Version 5 = Support signing entire RISC-V image as "code" in code section for hopper and later. + // + NvU32 version; // structure version + NvU32 bootloaderOffset; + NvU32 bootloaderSize; + NvU32 bootloaderParamOffset; + NvU32 bootloaderParamSize; + NvU32 riscvElfOffset; + NvU32 riscvElfSize; + NvU32 appVersion; // Changelist number associated with the image + // + // Manifest contains information about Monitor and it is + // input to BR + // + NvU32 manifestOffset; + NvU32 manifestSize; + // + // Monitor Data offset within RISCV image and size + // + NvU32 monitorDataOffset; + NvU32 monitorDataSize; + // + // Monitor Code offset withtin RISCV image and size + // + NvU32 monitorCodeOffset; + NvU32 monitorCodeSize; + NvU32 bIsMonitorEnabled; + // + // Swbrom Code offset within RISCV image and size + // + NvU32 swbromCodeOffset; + NvU32 swbromCodeSize; + // + // Swbrom Data offset within RISCV image and size + // + NvU32 swbromDataOffset; + NvU32 swbromDataSize; + // + // Total size of FB carveout (image and reserved space). + // + NvU32 fbReservedSize; + // + // Indicates whether the entire RISC-V image is signed as "code" in code section. + // + NvU32 bSignedAsCode; + // + // SMP (multihart) and PLIC (split interrupts) + // enablement options + // + NvU32 bIsSmp; + NvU32 bIsPlicEnabled; +} RM_RISCV_UCODE_DESC; + +#endif // RM_RISCV_UCODE_H diff --git a/userspace/sdks/nv570/nvalloc/common/inc/rm_state_monitor.h b/userspace/sdks/nv570/nvalloc/common/inc/rm_state_monitor.h new file mode 100644 index 0000000..e89fd16 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/rm_state_monitor.h @@ -0,0 +1,72 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef RM_STATE_MONITOR_H +#define RM_STATE_MONITOR_H + +// run every 100ms to prevent excessive CPU usage +// as RM dump task runs as a higher priority task +// than RM main task +#define RM_STATE_MONITOR_WAIT_PERIOD (100000000) // 100ms + +typedef enum { + RM_STATE_MONITOR_HEADER_REQUEST_EXIT, + RM_STATE_MONITOR_HEADER_REQUEST_RM_STATE, + RM_STATE_MONITOR_HEADER_RESPONSE +} RM_STATE_MONITOR_HEADER; + +typedef struct { + RM_STATE_MONITOR_HEADER header; +} RM_STATE_MONITOR_REQUEST_MESSAGE; + +typedef struct { + NV_STATUS status; +} RM_STATE_MONITOR_RESPONSE_MESSAGE; + +typedef union { + RM_STATE_MONITOR_REQUEST_MESSAGE request; + RM_STATE_MONITOR_RESPONSE_MESSAGE response; +} RM_STATE_MONITOR_MESSAGE; + +#define RM_STATE_MONITOR_MAX_DPC_QUEUE_ITEMS 16 +#define RM_STATE_MONITOR_MAX_WORK_ITEMS 32 +#define RM_STATE_MONITOR_MAX_INTERRUPTS 32 +#define RM_STATE_MONITOR_MAX_ENINGE_BYTE_ARRAY (4) + +typedef struct { + NvU64 dpcQueue[RM_STATE_MONITOR_MAX_DPC_QUEUE_ITEMS][RM_STATE_MONITOR_MAX_ENINGE_BYTE_ARRAY]; + NvU64 workItemsQueue[RM_STATE_MONITOR_MAX_WORK_ITEMS]; + NvU64 lastDpcExecutionTime; + NvU64 totalDpcExecutionTime; + NvU64 lastWorkItemsExecutionTime; + NvU64 totalWorkItemsExecutionTime; + NvU64 interrupts[RM_STATE_MONITOR_MAX_INTERRUPTS]; //TODO: should this get set? will affect perf +} RM_STATE_MONITOR_DATA; + +typedef struct { + NvU64 requestSequenceNumber; + NvU64 responseSequenceNumber; + RM_STATE_MONITOR_DATA data; +} RM_STATE_MONITOR_BUFFER_LAYOUT; + +#endif diff --git a/userspace/sdks/nv570/nvalloc/common/inc/rmflcnbl.h b/userspace/sdks/nv570/nvalloc/common/inc/rmflcnbl.h new file mode 100644 index 0000000..7a49306 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/rmflcnbl.h @@ -0,0 +1,147 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * Data structures and interfaces used for generic falcon boot-loader. + * + * This generic boot-loader is designed to load both non-secure and + * secure code taking care of signature as well. This bootloader + * should be loaded at the end of the IMEM so that it doesnt overwrite + * itself when it tries to load the code into IMEM starting at blk 0. + * The data will be loaded into DMEM offset 0. + */ + +#ifndef RMFLCNBL_H +#define RMFLCNBL_H + +#include "flcnifcmn.h" + +/*! + * @brief Structure used by the boot-loader to load the rest of the code. + * + * This has to be filled by the GPU driver and copied into DMEM at offset + * provided in the @ref _def_rm_flcn_bl_desc.blDmemDescLoadOff. + */ +typedef struct _def_rm_flcn_bl_dmem_desc +{ + /*! + * reserved should be always first element + */ + NvU32 reserved[4]; + /*! + * signature should follow reserved 16B signature for secure code. + * 0s if no secure code + */ + NvU32 signature[4]; + /*! + * ctxDma is used by the bootloader while loading code/data. + */ + NvU32 ctxDma; + /*! + * 256B aligned physical FB address where code is located. + */ + RM_FLCN_U64 codeDmaBase; + /*! + * Offset from codeDmaBase where the nonSecure code is located. + * The offset must be multiple of 256 to help performance. + */ + NvU32 nonSecureCodeOff; + /*! + * The size of the nonSecure code part. + */ + NvU32 nonSecureCodeSize; + /*! + * Offset from codeDmaBase where the secure code is located. + * The offset must be multiple of 256 to help performance. + */ + NvU32 secureCodeOff; + /*! + * The size of the ecure code part. + */ + NvU32 secureCodeSize; + /*! + * Code entry point which will be invoked by BL after code is loaded. + */ + NvU32 codeEntryPoint; + /*! + * 256B aligned Physical FB Address where data is located. + */ + RM_FLCN_U64 dataDmaBase; + /*! + * Size of data block. Should be multiple of 256B. + */ + NvU32 dataSize; + /*! + * Arguments to be passed to the target firmware being loaded. + */ + NvU32 argc; + /*! + * Number of arguments to be passed to the target firmware being loaded. + */ + NvU32 argv; +} RM_FLCN_BL_DMEM_DESC, *PRM_FLCN_BL_DMEM_DESC; + +/*! + * @brief The header used by the GPU driver to figure out code and data + * sections of bootloader. + */ +typedef struct _def_rm_flcn_bl_img_header +{ + /*! + * Offset of code section in the image. + */ + NvU32 blCodeOffset; + /*! + * Size of code section in the image. + */ + NvU32 blCodeSize; + /*! + * Offset of data section in the image. + */ + NvU32 blDataOffset; + /*! + * Size of data section in the image. + */ + NvU32 blDataSize; +} RM_FLCN_BL_IMG_HEADER, *PRM_FLCN_BL_IMG_HEADER; + +/*! + * @brief The descriptor used by RM to figure out the requirements of boot loader. + */ +typedef struct _def_rm_flcn_bl_desc +{ + /*! + * Starting tag of bootloader + */ + NvU32 blStartTag; + /*! + * Dmem offset where _def_rm_flcn_bl_dmem_desc to be loaded + */ + NvU32 blDmemDescLoadOff; + /*! + * Description of the image + */ + RM_FLCN_BL_IMG_HEADER blImgHeader; +} RM_FLCN_BL_DESC, *PRM_FLCN_BL_DESC; + +#endif // RMFLCNBL_H diff --git a/userspace/sdks/nv570/nvalloc/common/inc/rmgspseq.h b/userspace/sdks/nv570/nvalloc/common/inc/rmgspseq.h new file mode 100644 index 0000000..5d130d6 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/rmgspseq.h @@ -0,0 +1,66 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * Top-level header-file that defines the GSP data structures used to request + * firmware load/execution by the CPU. + */ + +#ifndef _RMGSPSEQ_H_ +#define _RMGSPSEQ_H_ + +#include "rmflcnbl.h" + +/*! + * Structure for loading/executing generic bootloader + */ +typedef struct GspLoadExecGenericBootloaderParams +{ + RM_FLCN_BL_DMEM_DESC dmemDesc; + NvU32 dmemDescSize; + NvU32 addrSpace; + NvU32 cpuCacheAttrib; + NvU32 reserved[4]; +} GspLoadExecGenericBootloaderParams; + +/*! + * Structure for loading/executing HS binary + */ +typedef struct GspLoadExecHsBinaryParams +{ + NvU64 imemPhysAddr; + NvU64 dmemPhysAddr; + NvU64 reserved64[2]; + NvU32 ucodeImemVA; + NvU32 ucodeImemPA; + NvU32 ucodeImemSize; + NvU32 ucodeDmemVA; + NvU32 ucodeDmemPA; + NvU32 ucodeDmemSize; + NvU32 hsSigDmemAddr; + NvU32 engineIdMask; + NvU32 ucodeId; + NvU32 reserved32[3]; +} GspLoadExecHsBinaryParams; + +#endif // _RMGSPSEQ_H_ diff --git a/userspace/sdks/nv570/nvalloc/common/inc/rmifrif.h b/userspace/sdks/nv570/nvalloc/common/inc/rmifrif.h new file mode 100644 index 0000000..b774d02 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/rmifrif.h @@ -0,0 +1,123 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2012 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _RMIFRIF_H_ +#define _RMIFRIF_H_ + +/*! + * @file rmifrif.h + * @brief Defines structures and interfaces common between RM and + * Init-From-Rom (IFR). + * + * For systems supporting GC6 that have on-board VBIOS ROMs, IFR is used + * to expedite several parts of GC6 exit in parallel with PEX init. + * + * After running devinit using a PMU ucode image loaded from the ROM itself, + * parts of RM stateLoad can be done using RM's ucode image. This is + * achieved by loading RM PMU ucode directly from FB. The primary difficulties + * are how to find RM's PMU ucode and how to bootstrap it. + * + * We use the simple approach of allocating a fixed buffer near the + * top of FB that contains the information required to bootstrap RM's PMU + * image. This buffer is called the RM_IFR_GC6_CTX. + * + * The buffer is allocated within RM's reserved memory space, directly before + * the VBIOS workspace (if any is present). Since the VBIOS workspace is + * always a multiple of 64K, RM enforces that the offset between top of memory + * and the end of the buffer is 64K. This way the IFR code can start + * from the top of memory and search downwards in 64K decrements. + * + * A small header is placed at the end of the buffer which contains a + * string signature identifying the buffer and other data needed to find the + * remaining context data. + * + * Top_Of-FB /---------------------\ <- + * | | \ + * | (VBIOS_Workspace) | | END_OFFSET + * | | / + * |---------------------| <- + | | \ + * | GSP FW (if present) | | pFbHalPvtInfo->gspFwSizeBytes + * | | / + * |---------------------| <- + * | RM_IFR_GC6_CTX_HDR | \ + * |---------------------| | + * | (Padding) | | RM_IFR_GC6_CTX_HDR.bufferSize + * |---------------------| | + * | Sequence Data | / + * |---------------------| <- + * | | + * | | + * | | + * | | + * 0x00000000 \---------------------/ + * + * To simplify the RM PMU bootstrap process and decrease IFR maintainence + * cost, the bootstrap process is encoded as a sequence script, leveraging + * a small subset of RM's PMU_SEQ_INST interface (see pmuseqinst.h). + * Register writes are captured during the initial (CPU-driven) RM PMU bootstrap + * and saved into a sequence for replay during GC6 exit. + * + * Only the following opcodes are supported currently: + * NV_PMU_SEQ_WRITE_REG_OPC - (multi-)register write + * NV_PMU_SEQ_EXIT_OPC - sequence done + * + */ + +/*! + * Header structure which identifies the GC6 context buffer. + */ +typedef struct +{ + NvU8 signature[12]; // RM_IFR_GC6_CTX_SIGNATURE + NvU32 bufferSize; // Size of the entire context buffer in bytes + NvU32 seqSizeWords; // Number of 32-bit words of sequence data + NvU32 checksum; // 32-bit chunk checksum of the sequence data +} RM_IFR_GC6_CTX_HDR, *PRM_IFR_GC6_CTX_HDR; + +/*! + * String signature that IFR searches for to find the GC6 context buffer. + */ +#define RM_IFR_GC6_CTX_SIGNATURE "GC6_CTX_HDR" // 12 bytes + +/*! + * Alignment of the offset between top of memory and the end of the + * GC6 context buffer (which is also the end of the header). + */ +#define RM_IFR_GC6_CTX_END_OFFSET_ALIGNMENT 0x10000 // 64KB + +/*! + * Maximum offset between top of memory and the end of the + * GC6 context buffer. This is meant to be a loose upper bound preventing + * scanning of the whole of memory (e.g. when something goes wrong). + */ +#define RM_IFR_GC6_CTX_END_OFFSET_MAX 0x1000000 // 16MB + +/*! + * Maximum size of the context data in bytes. + * This is limited by FECS falcon DMEM size (4K on Kepler). + * The buffer must fit within DMEM together with stack and other global data. + */ +#define RM_IFR_GC6_CTX_DATA_MAX_SIZE 2048 // 2KB + +#endif // _RMIFRIF_H_ diff --git a/userspace/sdks/nv570/nvalloc/common/inc/rmlsfm.h b/userspace/sdks/nv570/nvalloc/common/inc/rmlsfm.h new file mode 100644 index 0000000..ca91911 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/rmlsfm.h @@ -0,0 +1,579 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef RMLSFM_H +#define RMLSFM_H + +/*****************************************************************************/ +/* This file is shared between ACR, SEC2 Binaries */ +/* Do not update this file without updating ACR/SEC2 */ +/*****************************************************************************/ + +/*! + * @file rmlsfm.h + * @brief Top-level header-file that defines Light Secure Falcon Managment + SW shared interfaces. + */ + +/*! + * READ/WRITE masks for WPR region + */ +#define LSF_WPR_REGION_RMASK (0xCU) // Readable only from level 2 and 3 client +#define LSF_WPR_REGION_WMASK (0xCU) // Writable only from level 2 and 3 client +#define LSF_WPR_REGION_RMASK_SUB_WPR_ENABLED (0x8) // Readable only from level 3 client +#define LSF_WPR_REGION_WMASK_SUB_WPR_ENABLED (0x8) // Writable only from level 3 client +#define LSF_WPR_REGION_ALLOW_READ_MISMATCH_NO (0x0) // Disallow read mis-match for all clients +#define LSF_WPR_REGION_ALLOW_WRITE_MISMATCH_NO (0x0) // Disallow write mis-match for all clients + +/*! + * READ mask for WPR region on Tegra + * This is required until we update tegra binaries, Bug 200281517 + * TODO: dgoyal - Remove this once tegra binaries are updated + */ +#define LSF_WPR_REGION_RMASK_FOR_TEGRA (0xFU) + +/*! + * Expected REGION ID to be used for the unprotected FB region (region that + * does not have read or write protections) + */ +#define LSF_UNPROTECTED_REGION_ID (0x0U) + +/*! + * Expected REGION ID to be used for the WPR region for the falcon microcode (includes data). + * ACR allots client requests to each region based on read/write masks and it is supposed + * to provide first priority to requests from LSFM. Providing first priority will naturally assign + * region ID 1 to LSFM and this define will provide a way for different parties to sanity check + * this fact. Also there are other falcons (FECS/video falcons) which depends on this define, so please + * be aware while modifying this. + */ +#define LSF_WPR_EXPECTED_REGION_ID (0x1U) + +/*! + * Expected REGION ID to be used for the unused WPR region. + */ +#define LSF_WPR_UNUSED_REGION_ID (0x2U) + +/*! + * Invalid LS falcon subWpr ID + */ +#define LSF_SUB_WPR_ID_INVALID (0xFFFFFFFFU) + +/*! + * Expected REGION ID to be used for the VPR region. + */ +#define LSF_VPR_REGION_ID (0x3U) + +/*! + * Expected REGION ID to be used for the CPR region with conf compute. + */ +#define LSF_CPR_REGION_ID (0x3U) + +/*! + * Size of the separate bootloader data that could be present in WPR region. + */ +#define LSF_LS_BLDATA_EXPECTED_SIZE (0x100U) + +/*! + * since we dont check signatures in GC6 exit, we need to hardcode the WPR offset + */ +#define LSF_WPR_EXPECTED_OFFSET (0x0U) + +/*! + * CTXDMA to be used while loading code/data in target falcons + */ +#define LSF_BOOTSTRAP_CTX_DMA_FECS (0x0) + +/*! + * Context DMA ID 6 is reserved for Video UCODE + */ +#define LSF_BOOTSTRAP_CTX_DMA_VIDEO (0x6) +#define LSF_BOOTSTRAP_CTX_DMA_BOOTSTRAP_OWNER (0x0) +#define LSF_BOOTSTRAP_CTX_DMA_FBFLCN (0x0) + +/*! + * Falcon Id Defines + * Defines a common Light Secure Falcon identifier. + * Codesigning infra. assumes LSF_FALCON_ID_ prefix for units, + * Changes to the define needs to be reflected in path [1] + * For new Falcon Id adding, we need to append to the end; + * don't insert the new falcon Id in the middle. + * + * @note If a newly added Falcon has multiple instances sharing + * the same Falcon Id, the LSF_FALCON_USES_INSTANCE macro + * need to be updated. + */ +#define LSF_FALCON_ID_PMU (0U) +#define LSF_FALCON_ID_DPU (1U) +#define LSF_FALCON_ID_GSPLITE LSF_FALCON_ID_DPU +#define LSF_FALCON_ID_FECS (2U) +#define LSF_FALCON_ID_GPCCS (3U) +#define LSF_FALCON_ID_NVDEC (4U) +#define LSF_FALCON_ID_NVENC (5U) +#define LSF_FALCON_ID_NVENC0 (5U) +#define LSF_FALCON_ID_NVENC1 (6U) +#define LSF_FALCON_ID_SEC2 (7U) +#define LSF_FALCON_ID_NVENC2 (8U) +#define LSF_FALCON_ID_MINION (9U) +#define LSF_FALCON_ID_FBFALCON (10U) +#define LSF_FALCON_ID_XUSB (11U) +#define LSF_FALCON_ID_GSP_RISCV (12U) +#define LSF_FALCON_ID_PMU_RISCV (13U) +#define LSF_FALCON_ID_SOE (14U) +#define LSF_FALCON_ID_NVDEC1 (15U) +#define LSF_FALCON_ID_OFA (16U) +#define LSF_FALCON_ID_SEC2_RISCV (17U) +#define LSF_FALCON_ID_NVDEC_RISCV (18U) +#define LSF_FALCON_ID_NVDEC_RISCV_EB (19U) +#define LSF_FALCON_ID_NVJPG (20U) +#define LSF_FALCON_ID_FECS_RISCV (21U) +#define LSF_FALCON_ID_GPCCS_RISCV (22U) +#define LSF_FALCON_ID_NVJPG_RISCV_EB (23U) +#define LSF_FALCON_ID_OFA_RISCV_EB (24U) +#define LSF_FALCON_ID_NVENC_RISCV_EB (25U) +#define LSF_FALCON_ID_PMU_RISCV_EB (26U) +#define LSF_FALCON_ID_NVDEC0_RISCV_EB (27U) +#define LSF_FALCON_ID_GSPLITE_RISCV_EB (28U) +#define LSF_FALCON_ID_DISPLAY_RISCV_EB (29U) +#define LSF_FALCON_ID_FBFALCON_RISCV_EB (30U) +#define LSF_FALCON_ID_LPSEC (31U) +#define LSF_FALCON_ID_END (32U) + +#define LSF_FALCON_ID_INVALID (0xFFFFFFFFU) + +// +// TODO: Remove below Alias and add _EB Patching to macro LSF_FALCON_ID_FECS_RISCV, similarly for GPCCS, +// and similar cleanups in RM since RISCV based CTXSW engines are to be booted externally. +// Tracking in Bug 3808599 +// +#define LSF_FALCON_ID_FECS_RISCV_EB (LSF_FALCON_ID_FECS_RISCV) +#define LSF_FALCON_ID_GPCCS_RISCV_EB (LSF_FALCON_ID_GPCCS_RISCV) + +// +// ************************ NOTIFICATION ********************************* +// In case anyone needs to add new LSF falconId, please must calculate +// WPR header size per LSF_FALCON_ID_END. RM needs to call lsfmGetWprHeaderSizeMax_HAL +// to align with acrReadSubWprHeader_HAL in ACR. Otherwise, ACR can't get correct +// address to read sub wpr headers. +// We observer in case LSF_FALCON_ID_END > 32 will cause SEC2 IMEM tag missing error; +// but don't get the root cause yet. +// +#define LSF_FALCON_ID_END_15 (15U) +#define LSF_FALCON_ID_END_17 (17U) +#define LSF_FALCON_ID_END_18 (18U) +#define LSF_FALCON_ID_END_21 (21U) +#define LSF_FALCON_ID_END_30 (30U) + +#define LSF_FALCON_INSTANCE_DEFAULT_0 (0x0U) +#define LSF_FALCON_INSTANCE_DEFAULT_3 (0x3U) +#define LSF_FALCON_INSTANCE_DEFAULT_4 (0x4U) +#define LSF_FALCON_INSTANCE_COUNT_DEFAULT_1 (0x1U) + +// Currently max supported instance is 24 for FECS/GPCCS SMC +#define LSF_FALCON_INSTANCE_FECS_GPCCS_MAX (0x18U) +#define LSF_FALCON_INSTANCE_INVALID (0xFFFFFFFFU) +#define LSF_FALCON_INDEX_MASK_DEFAULT_0 (0x0U) + +/*! + * Checks if the LSF Falcon specified by falconId uses a falconInstance to uniquely identify itself. + * Some Falcons (eg: NVENC) use separate FalconId for each instance while some (eg: NVJPG) + * shares the same falconId across all instances of that engine. Those engines require a falconInstance + * to uniquely identify it. + * @note this macro should be updated as needed whenever LSF_FALCON_ID* defines are added. See Bug: 3833461 + */ +#define LSF_FALCON_USES_INSTANCE(falconId) ((falconId == LSF_FALCON_ID_NVDEC_RISCV_EB) || \ + (falconId == LSF_FALCON_ID_NVJPG) || \ + (falconId == LSF_FALCON_ID_NVJPG_RISCV_EB) || \ + (falconId == LSF_FALCON_ID_NVENC_RISCV_EB) || \ + (falconId == LSF_FALCON_ID_FECS_RISCV_EB) || \ + (falconId == LSF_FALCON_ID_GPCCS_RISCV_EB) || \ + (falconId == LSF_FALCON_ID_GSPLITE_RISCV_EB) || \ + (falconId == LSF_FALCON_ID_OFA_RISCV_EB) || \ + (falconId == LSF_FALCON_ID_LPSEC)) + + +/*! + * Size in entries of the ucode descriptor's dependency map. + * This used to be LSF_FALCON_ID_END, but since that had to grow and we did not want to break any + * existing binaries, they had to be split. + * + * Increasing this number should be done with care. + */ +#define LSF_FALCON_DEPMAP_SIZE (11U) + +/*! + * Falcon Binaries version defines + */ +#define LSF_FALCON_BIN_VERSION_INVALID (0xFFFFFFFFU) + + +/*! + * Light Secure Falcon Ucode Description Defines + * This stucture is prelim and may change as the ucode signing flow evolves. + */ +typedef struct +{ + NvU8 prdKeys[2][16]; + NvU8 dbgKeys[2][16]; + NvU32 bPrdPresent; + NvU32 bDbgPresent; + NvU32 falconId; + NvU32 bSupportsVersioning; + NvU32 version; + NvU32 depMapCount; + NvU8 depMap[LSF_FALCON_DEPMAP_SIZE * 2 * 4]; + NvU8 kdf[16]; +} LSF_UCODE_DESC, *PLSF_UCODE_DESC; + +/*! + * Light Secure WPR Header + * Defines state allowing Light Secure Falcon bootstrapping. + * + * falconId - LS falcon ID + * lsbOffset - Offset into WPR region holding LSB header + * bootstrapOwner - Bootstrap OWNER (either PMU or SEC2) + * bLazyBootstrap - Skip bootstrapping by ACR + * status - Bootstrapping status + */ +typedef struct +{ + NvU32 falconId; + NvU32 lsbOffset; + NvU32 bootstrapOwner; + NvU32 bLazyBootstrap; + NvU32 binVersion; + NvU32 status; +} LSF_WPR_HEADER, *PLSF_WPR_HEADER; + +/*! + * LSF shared SubWpr Header + * + * useCaseId - Shared SubWpr se case ID (updated by RM) + * startAddr - start address of subWpr (updated by RM) + * size4K - size of subWpr in 4K (updated by RM) + */ +typedef struct +{ + NvU32 useCaseId; + NvU32 startAddr; + NvU32 size4K; +} LSF_SHARED_SUB_WPR_HEADER, *PLSF_SHARED_SUB_WPR_HEADER; + +// Shared SubWpr use case IDs +typedef enum +{ + LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_FRTS_VBIOS_TABLES = 1, + LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA = 2, + LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_APM_RTS = 3 +} LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_ENUM; + +#define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_APM_RTS +#define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_INVALID (0xFFFFFFFFU) + +#define MAX_SUPPORTED_SHARED_SUB_WPR_USE_CASES LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX + +// +// Static sizes of shared subWPRs +// Minimum granularity supported is 4K +// +#define LSF_SHARED_DATA_SUB_WPR_FRTS_VBIOS_TABLES_SIZE_IN_4K (0x100) // 1MB in 4K +#define LSF_SHARED_DATA_SUB_WPR_PLAYREADY_SHARED_DATA_SIZE_IN_4K (0x1) // 4K +#define LSF_SHARED_DATA_SUB_WPR_APM_RTS_SIZE_IN_4K (0x1) // 4K + +/*! + * Bootstrap Owner Defines + */ +#define LSF_BOOTSTRAP_OWNER_PMU (LSF_FALCON_ID_PMU) +#define LSF_BOOTSTRAP_OWNER_SEC2 (LSF_FALCON_ID_SEC2) +#define LSF_BOOTSTRAP_OWNER_GSPLITE (LSF_FALCON_ID_GSPLITE) +#define LSF_BOOTSTRAP_OWNER_DEFAULT LSF_BOOTSTRAP_OWNER_PMU + +/*! + * Image Status Defines + */ +#define LSF_IMAGE_STATUS_NONE (0U) +#define LSF_IMAGE_STATUS_COPY (1U) +#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED (2U) +#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED (3U) +#define LSF_IMAGE_STATUS_VALIDATION_DONE (4U) +#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED (5U) +#define LSF_IMAGE_STATUS_BOOTSTRAP_READY (6U) +#define LSF_IMAGE_STATUS_REVOCATION_CHECK_FAILED (7U) + +/*! + * Light Secure Bootstrap Header + * Defines state allowing Light Secure Falcon bootstrapping. + * + * signature - Code/data signature details for this LS falcon + * ucodeOffset - Offset into WPR region where UCODE is located + * ucodeSize - Size of ucode + * dataSize - Size of ucode data + * blCodeSize - Size of bootloader that needs to be loaded by bootstrap owner + * blImemOffset - BL starting virtual address. Need for tagging. + * blDataOffset - Offset into WPR region holding the BL data + * blDataSize - Size of BL data + * appCodeOffset - Offset into WPR region where Application UCODE is located + * appCodeSize - Size of Application UCODE + * appDataOffset - Offset into WPR region where Application DATA is located + * appDataSize - Size of Application DATA + * blLoadCodeAt0 - Load BL at 0th IMEM offset + * bSetVACtx - Make sure to set the code/data loading CTX DMA to be virtual before exiting + * bDmaReqCtx - This falcon requires a ctx before issuing DMAs + * bForcePrivLoad- Use priv loading method instead of bootloader/DMAs + */ + +#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0 0:0 +#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE 0 +#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_TRUE 1 +#define NV_FLCN_ACR_LSF_FLAG_SET_VA_CTX 1:1 +#define NV_FLCN_ACR_LSF_FLAG_SET_VA_CTX_FALSE 0 +#define NV_FLCN_ACR_LSF_FLAG_SET_VA_CTX_TRUE 1 +#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX 2:2 +#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE 0 +#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE 1 +#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD 3:3 +#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE 0 +#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE 1 +typedef struct +{ + LSF_UCODE_DESC signature; + NvU32 ucodeOffset; + NvU32 ucodeSize; + NvU32 dataSize; + NvU32 blCodeSize; + NvU32 blImemOffset; + NvU32 blDataOffset; + NvU32 blDataSize; + NvU32 appCodeOffset; + NvU32 appCodeSize; + NvU32 appDataOffset; + NvU32 appDataSize; + NvU32 flags; + /* + * TODO: Uncomment this once Sanket's changes + * of HALifying is done + NvU32 monitorCodeOffset; + NvU32 monitorDataOffset; + NvU32 manifestOffset; + */ +} LSF_LSB_HEADER, *PLSF_LSB_HEADER; + + +/*! + * Light Secure WPR Content Alignments + */ +#define LSF_WPR_HEADER_ALIGNMENT (256U) +#define LSF_SUB_WPR_HEADER_ALIGNMENT (256U) +#define LSF_LSB_HEADER_ALIGNMENT (256U) +#define LSF_BL_DATA_ALIGNMENT (256U) +#define LSF_BL_DATA_SIZE_ALIGNMENT (256U) +#define LSF_BL_CODE_SIZE_ALIGNMENT (256U) +#define LSF_DATA_SIZE_ALIGNMENT (256U) +#define LSF_CODE_SIZE_ALIGNMENT (256U) + +// MMU excepts subWpr sizes in units of 4K +#define SUB_WPR_SIZE_ALIGNMENT (4096U) + +/*! + * Maximum WPR Header size + */ +#define LSF_WPR_HEADERS_TOTAL_SIZE_MAX (NV_ALIGN_UP((sizeof(LSF_WPR_HEADER) * LSF_FALCON_ID_END), LSF_WPR_HEADER_ALIGNMENT)) +#define LSF_LSB_HEADER_TOTAL_SIZE_MAX (NV_ALIGN_UP(sizeof(LSF_LSB_HEADER), LSF_LSB_HEADER_ALIGNMENT)) + +// +// PMU OBJACR_ALIGNED_256 size will vary with LSF_FALCON_ID_END. +// PMU could run out of DMEM in case we increase LSF_FALCON_ID_END more and more. +// The PMU supports the ACR task on GM20X_thru_VOLTA profiles only. +// In order to prevent LSF_FALCON_ID_END changes to affect older / shipped PMU ucodes (increase of DMEM footprint) +// adding PMU specific ***_END define capturing value covering all PMU profiles that this with the ACR task. +// +#define LSF_FALCON_ID_END_PMU (LSF_FALCON_ID_FBFALCON + 1) +#define LSF_WPR_HEADERS_TOTAL_SIZE_MAX_PMU (NV_ALIGN_UP((sizeof(LSF_WPR_HEADER) * LSF_FALCON_ID_END_PMU), LSF_WPR_HEADER_ALIGNMENT)) + +// +// In order to prevent LSF_FALCON_ID_END changes to affect older / shipped SEC2/ACR ucodes (increase of DMEM footprint) +// adding SEC2/ACR specific ***_END define covering all supported falcons in pre-hopper SEC2-RTOS/ACR ucode. +// +#define LSF_FALCON_ID_END_ACR_ON_SEC2 (LSF_FALCON_ID_NVJPG + 1) +#define LSF_WPR_HEADERS_TOTAL_SIZE_MAX_ACR_ON_SEC2 (NV_ALIGN_UP((sizeof(LSF_WPR_HEADER) * LSF_FALCON_ID_END_ACR_ON_SEC2), LSF_WPR_HEADER_ALIGNMENT)) + +// Maximum SUB WPR header size +#define LSF_SUB_WPR_HEADERS_TOTAL_SIZE_MAX (NV_ALIGN_UP((sizeof(LSF_SHARED_SUB_WPR_HEADER) * LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX), LSF_SUB_WPR_HEADER_ALIGNMENT)) + +/*! + * For the ucode surface alignment, We align to RM_PAGE_SIZE because of + * busMapRmAperture issues, not because of Falcon ucode alignment requirements + * which currently are that it be at least 256. + */ +#define LSF_UCODE_DATA_ALIGNMENT RM_PAGE_SIZE + +/*! + * ACR Descriptors used by ACR UC + */ + +/*! + * Supporting maximum of 2 regions. + * This is needed to pre-allocate space in DMEM + */ +#define RM_FLCN_ACR_MAX_REGIONS (2) +#define LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE (0x200) + +/*! + * startAddress - Starting address of region + * endAddress - Ending address of region + * regionID - Region ID + * readMask - Read Mask + * writeMask - WriteMask + * clientMask - Bit map of all clients currently using this region + * shadowMemStartAddress- FB location from where contents need to be copied to startAddress + */ +typedef struct _def_acr_dmem_region_prop +{ + NvU32 startAddress; + NvU32 endAddress; + NvU32 regionID; + NvU32 readMask; + NvU32 writeMask; + NvU32 clientMask; + NvU32 shadowMemStartAddress; +} RM_FLCN_ACR_REGION_PROP, *PRM_FLCN_ACR_REGION_PROP; + + +/*! + * noOfRegions - Number of regions used by RM. + * regionProps - Region properties + */ +typedef struct _def_acr_regions +{ + NvU32 noOfRegions; + RM_FLCN_ACR_REGION_PROP regionProps[RM_FLCN_ACR_MAX_REGIONS]; +} RM_FLCN_ACR_REGIONS, *PRM_FLCN_ACR_REGIONS; + +/*! + * bVprEnabled : When set, ACR_LOCKDOWN phase programs VPR range. Needs to be + : NvU32 because of alignment + * vprStartAddress : Start address of VPR region. SEC2 binary updates this value + * vprEndAddress : End address of VPR region. SEC2 binary updates this value + * hdcpPolicies : VPR display policies. SEC2 binary updates this value + */ +typedef struct _def_acr_vpr_dmem_desc +{ + NvU32 bVprEnabled; + NvU32 vprStartAddress; + NvU32 vprEndAddress; + NvU32 hdcpPolicies; +} ACR_BSI_VPR_DESC, *PACR_BSI_VPR_DESC; + +/*! + * reservedDmem - When the bootstrap owner has done bootstrapping other falcons, + * and need to switch into LS mode, it needs to have its own actual + * DMEM image copied into DMEM as part of LS setup. If ACR desc is at + * location 0, it will definitely get overwritten causing data corruption. + * Hence we are reserving 0x200 bytes to give room for any loading data. + * NOTE: This has to be the first member always + * signature - Signature of ACR ucode. + * wprRegionID - Region ID holding the WPR header and its details + * wprOffset - Offset from the WPR region holding the wpr header + * regions - Region descriptors + * ucodeBlobBase- Used for Tegra, stores non-WPR start address where kernel stores ucode blob + * ucodeBlobSize- Used for Tegra, stores the size of the ucode blob + */ +typedef struct _def_acr_dmem_desc +{ + NvU32 signatures[4]; + NvU32 wprRegionID; + NvU32 wprOffset; + NvU32 mmuMemoryRange; + RM_FLCN_ACR_REGIONS regions; + NvU32 ucodeBlobSize; + // uCodeBlobBase is moved after ucodeBlobSize to inherently align to qword (8 bytes) + NvU64 NV_DECLARE_ALIGNED(ucodeBlobBase, 8); + + /*! + * Do not change the offset of this descriptor as it shared between + * ACR_REGION_LOCKDOWN HS binary and SEC2. Any change in this structure + * need recompilation of SEC2 and ACR_LOCKDOWN HS binary + */ + ACR_BSI_VPR_DESC vprDesc; +} RM_FLCN_ACR_DESC, *PRM_FLCN_ACR_DESC; + +/*! +* Hub keys/nonce Structure in BSI +*/ +#define MAX_SFBHUB_ENCRYPTION_REGION_KEY_SIZE 4 + +typedef struct _def_acr_hub_scratch_data +{ + NvU32 key[MAX_SFBHUB_ENCRYPTION_REGION_KEY_SIZE]; + NvU32 nonce[MAX_SFBHUB_ENCRYPTION_REGION_KEY_SIZE]; +} ACR_BSI_HUB_DESC, *PACR_BSI_HUB_DESC; + +#define MAX_HUB_ENCRYPTION_REGION_COUNT 3 +typedef struct _def_acr_hub_scratch_array +{ + ACR_BSI_HUB_DESC entries[MAX_HUB_ENCRYPTION_REGION_COUNT]; +} ACR_BSI_HUB_DESC_ARRAY, *PACR_BSI_HUB_DESC_ARRAY; + +typedef struct _def_acr_reserved_dmem +{ + NvU32 reservedDmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; // Always first.. +} ACR_RESERVED_DMEM, *PACR_RESERVED_DMEM; + +typedef struct _def_booter_reserved_dmem +{ + NvU32 reservedDmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; // Always first.. +} BOOTER_RESERVED_DMEM; + +#define NV_FLCN_ACR_DESC_FLAGS_SIG_VERIF 0:0 +#define NV_FLCN_ACR_DESC_FLAGS_SIG_VERIF_DISABLE 0 +#define NV_FLCN_ACR_DESC_FLAGS_SIG_VERIF_ENABLE 1 + +// Macro defines to be consumed by RM to get GH100 GSP Inst_in_sys FMC boot status. +#define GSP_INST_IN_SYS_COMPLETION_STATUS_OK 0x55 +#define GSP_INST_IN_SYS_COMPLETION_STATUS_ERROR 0xAA +#define GSP_INST_IN_SYS_COMPLETION_STATUS_IN_PROGRESS 0x00 + +/*! + * Size of ACR phase in dword + */ +#define ACR_PHASE_SIZE_DWORD sizeof(RM_FLCN_ACR_DESC)/sizeof(NvU32) + +/*! + * Falcon Mode Tokens + * This is the value logged to a mailbox register to indicate that the + * falcon isn't booted in secure mode. + */ +#define LSF_FALCON_MODE_TOKEN_FLCN_INSECURE (0xDEADDEADU) + + +// LS encryption context, to store data to decrypt LS images. +#define LS_ENCRYPTION_AES128_CBC_IV_SIZE_BYTE (16) + +typedef struct +{ + NvU8 bLsEncrypted; + NvU8 rsvd[3]; + NvU8 lsEncIV[LS_ENCRYPTION_AES128_CBC_IV_SIZE_BYTE]; +} LSF_ENCRYPTION_CONTEXT, *PLSF_ENCRYPTION_CONTEXT; + +#endif // RMLSFM_H + diff --git a/userspace/sdks/nv570/nvalloc/common/inc/rmpbicmdif.h b/userspace/sdks/nv570/nvalloc/common/inc/rmpbicmdif.h new file mode 100644 index 0000000..cd4d092 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/rmpbicmdif.h @@ -0,0 +1,140 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * Shared postbox interface defines for RM and PMU. + */ + +#ifndef RMPBICMDIF_H +#define RMPBICMDIF_H + +/* + * Define the status of postbox interface at different instances. + * + * The values should be in accordance to the spec and must not be changed. + * A new PBI command must be submitted with the status NV_PBI_COMMAND_STATUS_UNDEFINED. + */ + +#define NV_PBI_COMMAND_STATUS 7:0 +#define NV_PBI_COMMAND_STATUS_UNDEFINED 0x00 // command submitted to PMU +#define NV_PBI_COMMAND_STATUS_SUCCESS 0x01 // command successfully completed by PMU +#define NV_PBI_COMMAND_STATUS_PENDING 0x02 // command accepted by PMU +#define NV_PBI_COMMAND_STATUS_BUSY 0x03 // command processing in PMU +#define NV_PBI_COMMAND_STATUS_UNSPECIFIED_FAILURE 0x04 // unknown failure or hang +#define NV_PBI_COMMAND_STATUS_INVALID_ADDRESS 0x05 // invalid address submitted to PMU +#define NV_PBI_COMMAND_STATUS_MORE_DATA 0x06 // user needs to send more data to PMU +#define NV_PBI_COMMAND_STATUS_INVALID_COMMAND 0x07 // invalid command submitted + +/* + * This corresponds to reserved bits of command register + */ +#define NV_PBI_COMMAND_RSVD_0 15:8 +#define NV_PBI_COMMAND_RSVD_0_VAL 0x00 + +/* + * This specifies the dword index if client is sending multiple dwords + * for single Dword this should be zero + */ +#define NV_PBI_COMMAND_BUFFER_INDEX 19:16 + +/* + * This specifies the total no. of dwords passed by client + */ +#define NV_PBI_COMMAND_BUFFER_SIZE 23:20 + +/* + * These corresponds the different function ID's supported out of PBI + */ +#define NV_PBI_COMMAND_FUNC_ID 27:24 +#define NV_PBI_COMMAND_FUNC_ID_GET_CAPABILITIES (0) +#define NV_PBI_COMMAND_FUNC_ID_EXECUTE_ROUTINE (11) + +// +// Definitions for common 'Execute Routine' calls that are +// shared across all GPUs. +// +// Common routine IDs must be in the range 0x80 to 0xff. +// +// Get GID: +#define NV_PBI_EXECUTE_ROUTINE_GET_GID 0x80 +// Get Feature: +#define NV_PBI_EXECUTE_ROUTINE_GET_FEATURE 0x81 +#define NV_PBI_EXECUTE_ROUTINE_GET_FEATURE_EXCLUSION 5:0 +#define NV_PBI_EXECUTE_ROUTINE_GET_FEATURE_EXCLUSION_ALLOWED 0x2 + +/* + * This corresponds to reserved field of command register + */ +#define NV_PBI_COMMAND_RSVD_1 28:28 +#define NV_PBI_COMMAND_RSVD_1_VAL 0x00 + +/* + * If this bit is set system will be notified on command completion + */ +#define NV_PBI_COMMAND_SYS_NOTIFY 29:29 +#define NV_PBI_COMMAND_SYS_NOTIFY_TRUE 0x01 +#define NV_PBI_COMMAND_SYS_NOTIFY_FALSE 0x00 + +/* + * If this bit is set driver will be notified of command completion status + */ +#define NV_PBI_COMMAND_DRV_NOTIFY 30:30 +#define NV_PBI_COMMAND_DRV_NOTIFY_TRUE 0x01 +#define NV_PBI_COMMAND_DRV_NOTIFY_FALSE 0x00 + +/* + * Defines the interrupt state of the PBI command + */ +#define NV_PBI_COMMAND_INTERRUPT 31:31 +#define NV_PBI_COMMAND_INTERRUPT_TRUE 0x01 +#define NV_PBI_COMMAND_INTERRUPT_FALSE 0x00 + +/* + * This sets the different fields of command register + */ +#define PBI_SET_COMMAND_PARAMS(status, r0, index, sz, cmd, r1, sys, \ + drv, intr, val) \ +{ \ + val = DRF_NUM(_PBI, _COMMAND, _STATUS, status) | \ + DRF_NUM(_PBI, _COMMAND, _RSVD_0, r0) | \ + DRF_NUM(_PBI, _COMMAND, _BUFFER_INDEX, index) | \ + DRF_NUM(_PBI, _COMMAND, _BUFFER_SIZE, sz) | \ + DRF_NUM(_PBI, _COMMAND, _FUNC_ID, cmd) | \ + DRF_NUM(_PBI, _COMMAND, _RSVD_1, r1) | \ + DRF_NUM(_PBI, _COMMAND, _SYS_NOTIFY, sys) | \ + DRF_NUM(_PBI, _COMMAND, _DRV_NOTIFY, drv) | \ + DRF_NUM(_PBI, _COMMAND, _INTERRUPT, intr); \ +} + +/* + * postbox_clients_mutex_id + * + * Define the Mutex ID for different PBI clients + */ +enum postbox_clients_mutex_id +{ + PBI_CLIENT_NONE = 0x00, + PBI_CLIENT_DRIVER_PCIPBI_SHIM = 0x15 +}; + +#endif /* RMPBICMDIF_H */ diff --git a/userspace/sdks/nv570/nvalloc/common/inc/sec2/nvdm_payload_cmd_response.h b/userspace/sdks/nv570/nvalloc/common/inc/sec2/nvdm_payload_cmd_response.h new file mode 100644 index 0000000..fa117aa --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/sec2/nvdm_payload_cmd_response.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * @file nvdm_payload_cmd_response.h + * @brief Header file containing the definition for the + * NVDM_PAYLOAD_COMMAND_RESPONSE structure, which + * is required for SMBPBI-specific payloads and needs + * to be visible by bothe the PMU and the driver sides. + */ + +#ifndef _NVDM_PAYLOAD_CMD_RESPONSE_H +#define _NVDM_PAYLOAD_CMD_RESPONSE_H + +#pragma pack(1) +typedef struct +{ + NvU32 taskId; + NvU32 commandNvdmType; + NvU32 errorCode; +} NVDM_PAYLOAD_COMMAND_RESPONSE; +#pragma pack() + +#endif // _NVDM_PAYLOAD_CMD_RESPONSE_H diff --git a/userspace/sdks/nv570/nvalloc/common/inc/sec2/sec2_emem_channels.h b/userspace/sdks/nv570/nvalloc/common/inc/sec2/sec2_emem_channels.h new file mode 100644 index 0000000..3681f24 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/sec2/sec2_emem_channels.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _SEC2_EMEM_CHANNELS_H_ +#define _SEC2_EMEM_CHANNELS_H_ + +// +// NVDM (NVIDIA Data Model) overlayed on MCTP (Management Component Transport +// Protocol) and sent over EMEM is the communication mechanism used between SEC2 +// management partition and CPU-RM/other uprocs. +// + +// RM uses channel 0 for SEC2 EMEM. +#define SEC2_EMEM_CHANNEL_RM 0x0 + +// EMEM channel 0 (RM) is allocated 1K bytes. +#define SEC2_EMEM_CHANNEL_RM_SIZE 1024 + +#endif // _SEC2_EMEM_CHANNELS_H_ diff --git a/userspace/sdks/nv570/nvalloc/common/inc/spdm/rmspdmrsakeys.h b/userspace/sdks/nv570/nvalloc/common/inc/spdm/rmspdmrsakeys.h new file mode 100644 index 0000000..882497b --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/spdm/rmspdmrsakeys.h @@ -0,0 +1,160 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file rmspdmrsakeys.h + * @brief SPDM Interfaces - RSA keys + */ + +#ifndef _RM_SPDM_RSA_KEYS_H_ +#define _RM_SPDM_RSA_KEYS_H_ + +// +// Note !! +// All key components order must be big-endian(network order). +// If any change for these key components, need to rebuild GSP/RM code as well. +// +#ifndef USE_MBEDTLS + +const NvU8 g_rsa3k_modulus_mutual_authentication_prod[] = +{ + 0xcd, 0x65, 0xd2, 0xca, 0x74, 0xd1, 0x76, 0x76, 0x9f, 0x18, 0x23, 0x64, 0x55, 0x84, 0x98, 0x60, + 0x71, 0xeb, 0x42, 0x6d, 0xa4, 0x98, 0xf9, 0x92, 0xea, 0x83, 0x5b, 0x9b, 0xe2, 0x66, 0x8b, 0x43, + 0x14, 0x4d, 0x5a, 0xb8, 0xdb, 0x68, 0x2b, 0xfa, 0x5f, 0xdf, 0x7f, 0xf4, 0xfd, 0x5e, 0x42, 0x34, + 0x09, 0x98, 0xa1, 0x21, 0x98, 0x4c, 0x8d, 0xbc, 0x99, 0xdb, 0xea, 0xc1, 0xe3, 0x42, 0xe6, 0x67, + 0x26, 0x86, 0x2c, 0xd0, 0xdb, 0xf3, 0x9c, 0x12, 0xad, 0xb3, 0x82, 0x93, 0x9c, 0xb9, 0xae, 0x98, + 0x82, 0xeb, 0x59, 0xb6, 0x5c, 0x09, 0x9f, 0xa6, 0x15, 0x30, 0xa0, 0xc6, 0x77, 0xd5, 0xae, 0xa2, + 0x91, 0x65, 0x24, 0xc3, 0x7d, 0x9b, 0xa4, 0x2c, 0x31, 0x73, 0x41, 0x26, 0x72, 0xe7, 0x2f, 0xb8, + 0x60, 0xd8, 0xce, 0xb8, 0xd8, 0x4b, 0x90, 0x6c, 0xa3, 0x19, 0x7e, 0x2b, 0xd5, 0xf6, 0x05, 0x8a, + 0x2b, 0xb9, 0x9e, 0x27, 0xba, 0x2e, 0x16, 0x81, 0x9a, 0x9e, 0xf5, 0x6c, 0x38, 0x0a, 0x01, 0xea, + 0xd6, 0xe1, 0xa4, 0x83, 0x76, 0xd0, 0x68, 0xbb, 0x90, 0x63, 0xce, 0x1c, 0x8c, 0x6f, 0x0f, 0x6b, + 0x65, 0x5b, 0x12, 0xe2, 0x92, 0x60, 0x79, 0x88, 0x99, 0x5e, 0x17, 0x89, 0x4d, 0x54, 0xb1, 0x87, + 0x9c, 0xe6, 0x6d, 0x3c, 0x56, 0x1c, 0x3a, 0x3e, 0xb9, 0x16, 0x2c, 0xc8, 0xda, 0x1a, 0xfb, 0x5c, + 0xd7, 0x16, 0x3c, 0x74, 0xda, 0x78, 0xf1, 0x53, 0xd7, 0x66, 0x97, 0x8a, 0x57, 0x0b, 0x86, 0x57, + 0x2c, 0x45, 0xa1, 0x5e, 0xae, 0x39, 0x39, 0xde, 0xe0, 0x40, 0x6f, 0xdb, 0x4c, 0xd8, 0xc1, 0x8c, + 0xdb, 0xce, 0xea, 0x05, 0xc0, 0xbc, 0x89, 0x72, 0x15, 0xfd, 0xbf, 0xb2, 0xb7, 0xf2, 0x5d, 0x05, + 0xdd, 0x2b, 0x53, 0xa4, 0x03, 0x1e, 0x11, 0x67, 0xa7, 0x0f, 0x87, 0xfb, 0x57, 0x48, 0x91, 0xc8, + 0x02, 0xb7, 0x46, 0x3d, 0x82, 0xcd, 0x06, 0x4a, 0x79, 0x0f, 0xa5, 0x8a, 0xac, 0xfb, 0xb7, 0xc2, + 0xf0, 0x95, 0x19, 0x4c, 0x78, 0x7a, 0xc7, 0xd7, 0x70, 0xee, 0x6e, 0x59, 0xaf, 0x51, 0x9b, 0x11, + 0x03, 0xd3, 0x56, 0xb3, 0x05, 0x5a, 0xbb, 0x1f, 0xbd, 0xc2, 0x0e, 0x89, 0x77, 0xb4, 0xc1, 0x02, + 0xf9, 0x97, 0x56, 0x07, 0x2e, 0x4e, 0x2d, 0x01, 0x73, 0x89, 0x7d, 0xf3, 0xc9, 0x8c, 0x88, 0x2c, + 0x79, 0xd9, 0x47, 0x34, 0x9e, 0x32, 0x51, 0xd4, 0xa6, 0x7e, 0xd1, 0x08, 0xda, 0xc0, 0x76, 0x24, + 0x8e, 0x25, 0x73, 0x14, 0x30, 0xd2, 0x17, 0x37, 0xbc, 0xe0, 0x3e, 0xa2, 0x47, 0xff, 0xe2, 0x4e, + 0x9b, 0x31, 0x6c, 0xe6, 0x54, 0xaf, 0x62, 0x3a, 0xcd, 0xfa, 0x2f, 0xaf, 0x73, 0x2e, 0x73, 0x4a, + 0x3a, 0x60, 0xa8, 0xa9, 0xfc, 0x77, 0xb2, 0x57, 0xdd, 0x3a, 0xfa, 0xce, 0x35, 0xc3, 0xea, 0xa9 +}; + +const NvU8 g_rsa3k_public_exponent_mutual_authentication_prod[] = {0x00, 0x01, 0x00, 0x01}; + +const NvU8 g_rsa3k_private_exponent_mutual_authentication_prod[] = +{ + 0x04, 0x85, 0xc0, 0x6d, 0x6a, 0xc3, 0x0d, 0xeb, 0xb0, 0xb7, 0x14, 0x58, 0x6a, 0x35, 0xa0, 0x31, + 0x47, 0x70, 0xd9, 0xa6, 0x96, 0x60, 0x33, 0xe6, 0x93, 0x39, 0x4f, 0x34, 0x10, 0x79, 0x17, 0x89, + 0xe3, 0x91, 0x8c, 0x74, 0xd3, 0x87, 0xe8, 0xa7, 0xfb, 0xa2, 0x6d, 0x2b, 0xd4, 0xc4, 0x55, 0x8a, + 0xd5, 0xc7, 0x41, 0x8c, 0xfe, 0xd0, 0x78, 0xb2, 0x75, 0x64, 0xcd, 0x37, 0x75, 0xac, 0x8c, 0x6c, + 0x2b, 0x01, 0xfb, 0x4c, 0xa1, 0xfb, 0x2c, 0x2d, 0x91, 0x1b, 0x89, 0xbd, 0x7c, 0x4e, 0xee, 0x54, + 0x37, 0x55, 0xbd, 0x44, 0xf1, 0xa3, 0xd8, 0x9b, 0x0c, 0x8e, 0x64, 0x8b, 0xda, 0x29, 0x9f, 0x4d, + 0xbf, 0x0b, 0xce, 0x12, 0x6b, 0xda, 0x98, 0x73, 0xcc, 0xa6, 0xf0, 0x01, 0x4b, 0xb8, 0x61, 0x69, + 0x9a, 0xe0, 0x4b, 0x34, 0xf0, 0xb6, 0x41, 0x38, 0xd3, 0x22, 0x85, 0x8f, 0xab, 0x87, 0x5e, 0x39, + 0xdb, 0x9a, 0x9b, 0xab, 0xde, 0x42, 0x93, 0x86, 0x49, 0x04, 0x44, 0xfd, 0x1c, 0x02, 0xc4, 0x66, + 0x0a, 0x53, 0x2f, 0x8f, 0x21, 0x77, 0x97, 0x46, 0xc1, 0xf8, 0x20, 0x9a, 0xaa, 0x50, 0xeb, 0xb2, + 0xfe, 0xa9, 0x51, 0xb2, 0x21, 0x6c, 0xf4, 0x60, 0x18, 0x98, 0x64, 0xc6, 0x46, 0x28, 0x9e, 0x3c, + 0x11, 0x2d, 0x55, 0xac, 0x65, 0x6c, 0xfb, 0xaf, 0x53, 0xdd, 0xf4, 0x20, 0x7c, 0x04, 0xea, 0x11, + 0xe8, 0x25, 0x65, 0x15, 0x32, 0x8e, 0x08, 0x84, 0xc7, 0x41, 0x13, 0x58, 0x73, 0x61, 0x63, 0x1f, + 0xef, 0x30, 0x1d, 0x3d, 0x36, 0x08, 0x3a, 0xb2, 0xf7, 0x25, 0x56, 0xfc, 0x03, 0x78, 0xb5, 0x45, + 0xf4, 0x60, 0x47, 0x95, 0x1c, 0x6a, 0x2b, 0xfa, 0xe3, 0x1c, 0x2f, 0x0d, 0x2a, 0x90, 0x43, 0x65, + 0x09, 0xbe, 0x63, 0x71, 0x33, 0xd3, 0x29, 0x31, 0xd5, 0x29, 0x26, 0xa3, 0x15, 0xc2, 0x46, 0x70, + 0xb4, 0x3e, 0x23, 0xaf, 0xb6, 0xfb, 0x87, 0x8f, 0x39, 0xf0, 0xd2, 0x3e, 0x35, 0x3c, 0xec, 0x7a, + 0xd2, 0x0f, 0xd8, 0xa4, 0x0c, 0x19, 0xc8, 0xee, 0x47, 0x7c, 0x1e, 0xd6, 0x67, 0x31, 0xe2, 0x9d, + 0xc0, 0x65, 0x64, 0x60, 0xe7, 0xd2, 0xeb, 0xe1, 0x02, 0xd5, 0x92, 0x7c, 0x51, 0xf1, 0x3b, 0x12, + 0x00, 0x65, 0xfd, 0x2b, 0x13, 0x15, 0xfa, 0x6d, 0x99, 0x1d, 0xd3, 0x03, 0x77, 0xb1, 0xb0, 0xf0, + 0x39, 0x7c, 0x27, 0x13, 0x30, 0xba, 0xff, 0x4d, 0x2e, 0xda, 0xe0, 0x37, 0xad, 0xf4, 0x49, 0x0a, + 0xdd, 0x1e, 0x87, 0x8c, 0xc9, 0x6b, 0xf8, 0xc6, 0xb3, 0x05, 0xeb, 0x6c, 0x5f, 0x84, 0x64, 0x62, + 0x1c, 0xf6, 0x04, 0x6f, 0xd7, 0xa9, 0xbc, 0x22, 0x97, 0xdb, 0x8d, 0xa5, 0xe1, 0x3a, 0x5c, 0x0d, + 0x7b, 0x78, 0x25, 0x98, 0x04, 0x7f, 0x2b, 0x59, 0x5b, 0x7c, 0xf7, 0x73, 0x37, 0x7f, 0x92, 0x8d +}; + +#else + +const NvU8 g_rsa3k_modulus_mutual_authentication_prod[] = +{ + 0xa9, 0xea, 0xc3, 0x35, 0xce, 0xfa, 0x3a, 0xdd, 0x57, 0xb2, 0x77, 0xfc, 0xa9, 0xa8, 0x60, 0x3a, + 0x4a, 0x73, 0x2e, 0x73, 0xaf, 0x2f, 0xfa, 0xcd, 0x3a, 0x62, 0xaf, 0x54, 0xe6, 0x6c, 0x31, 0x9b, + 0x4e, 0xe2, 0xff, 0x47, 0xa2, 0x3e, 0xe0, 0xbc, 0x37, 0x17, 0xd2, 0x30, 0x14, 0x73, 0x25, 0x8e, + 0x24, 0x76, 0xc0, 0xda, 0x08, 0xd1, 0x7e, 0xa6, 0xd4, 0x51, 0x32, 0x9e, 0x34, 0x47, 0xd9, 0x79, + 0x2c, 0x88, 0x8c, 0xc9, 0xf3, 0x7d, 0x89, 0x73, 0x01, 0x2d, 0x4e, 0x2e, 0x07, 0x56, 0x97, 0xf9, + 0x02, 0xc1, 0xb4, 0x77, 0x89, 0x0e, 0xc2, 0xbd, 0x1f, 0xbb, 0x5a, 0x05, 0xb3, 0x56, 0xd3, 0x03, + 0x11, 0x9b, 0x51, 0xaf, 0x59, 0x6e, 0xee, 0x70, 0xd7, 0xc7, 0x7a, 0x78, 0x4c, 0x19, 0x95, 0xf0, + 0xc2, 0xb7, 0xfb, 0xac, 0x8a, 0xa5, 0x0f, 0x79, 0x4a, 0x06, 0xcd, 0x82, 0x3d, 0x46, 0xb7, 0x02, + 0xc8, 0x91, 0x48, 0x57, 0xfb, 0x87, 0x0f, 0xa7, 0x67, 0x11, 0x1e, 0x03, 0xa4, 0x53, 0x2b, 0xdd, + 0x05, 0x5d, 0xf2, 0xb7, 0xb2, 0xbf, 0xfd, 0x15, 0x72, 0x89, 0xbc, 0xc0, 0x05, 0xea, 0xce, 0xdb, + 0x8c, 0xc1, 0xd8, 0x4c, 0xdb, 0x6f, 0x40, 0xe0, 0xde, 0x39, 0x39, 0xae, 0x5e, 0xa1, 0x45, 0x2c, + 0x57, 0x86, 0x0b, 0x57, 0x8a, 0x97, 0x66, 0xd7, 0x53, 0xf1, 0x78, 0xda, 0x74, 0x3c, 0x16, 0xd7, + 0x5c, 0xfb, 0x1a, 0xda, 0xc8, 0x2c, 0x16, 0xb9, 0x3e, 0x3a, 0x1c, 0x56, 0x3c, 0x6d, 0xe6, 0x9c, + 0x87, 0xb1, 0x54, 0x4d, 0x89, 0x17, 0x5e, 0x99, 0x88, 0x79, 0x60, 0x92, 0xe2, 0x12, 0x5b, 0x65, + 0x6b, 0x0f, 0x6f, 0x8c, 0x1c, 0xce, 0x63, 0x90, 0xbb, 0x68, 0xd0, 0x76, 0x83, 0xa4, 0xe1, 0xd6, + 0xea, 0x01, 0x0a, 0x38, 0x6c, 0xf5, 0x9e, 0x9a, 0x81, 0x16, 0x2e, 0xba, 0x27, 0x9e, 0xb9, 0x2b, + 0x8a, 0x05, 0xf6, 0xd5, 0x2b, 0x7e, 0x19, 0xa3, 0x6c, 0x90, 0x4b, 0xd8, 0xb8, 0xce, 0xd8, 0x60, + 0xb8, 0x2f, 0xe7, 0x72, 0x26, 0x41, 0x73, 0x31, 0x2c, 0xa4, 0x9b, 0x7d, 0xc3, 0x24, 0x65, 0x91, + 0xa2, 0xae, 0xd5, 0x77, 0xc6, 0xa0, 0x30, 0x15, 0xa6, 0x9f, 0x09, 0x5c, 0xb6, 0x59, 0xeb, 0x82, + 0x98, 0xae, 0xb9, 0x9c, 0x93, 0x82, 0xb3, 0xad, 0x12, 0x9c, 0xf3, 0xdb, 0xd0, 0x2c, 0x86, 0x26, + 0x67, 0xe6, 0x42, 0xe3, 0xc1, 0xea, 0xdb, 0x99, 0xbc, 0x8d, 0x4c, 0x98, 0x21, 0xa1, 0x98, 0x09, + 0x34, 0x42, 0x5e, 0xfd, 0xf4, 0x7f, 0xdf, 0x5f, 0xfa, 0x2b, 0x68, 0xdb, 0xb8, 0x5a, 0x4d, 0x14, + 0x43, 0x8b, 0x66, 0xe2, 0x9b, 0x5b, 0x83, 0xea, 0x92, 0xf9, 0x98, 0xa4, 0x6d, 0x42, 0xeb, 0x71, + 0x60, 0x98, 0x84, 0x55, 0x64, 0x23, 0x18, 0x9f, 0x76, 0x76, 0xd1, 0x74, 0xca, 0xd2, 0x65, 0xcd, + 0x00 +}; + +const NvU8 g_rsa3k_public_exponent_mutual_authentication_prod[] = {0x01, 0x00, 0x01, 0x00}; + +const NvU8 g_rsa3k_private_exponent_mutual_authentication_prod[] = +{ + 0x8d, 0x92, 0x7f, 0x37, 0x73, 0xf7, 0x7c, 0x5b, 0x59, 0x2b, 0x7f, 0x04, 0x98, 0x25, 0x78, 0x7b, + 0x0d, 0x5c, 0x3a, 0xe1, 0xa5, 0x8d, 0xdb, 0x97, 0x22, 0xbc, 0xa9, 0xd7, 0x6f, 0x04, 0xf6, 0x1c, + 0x62, 0x64, 0x84, 0x5f, 0x6c, 0xeb, 0x05, 0xb3, 0xc6, 0xf8, 0x6b, 0xc9, 0x8c, 0x87, 0x1e, 0xdd, + 0x0a, 0x49, 0xf4, 0xad, 0x37, 0xe0, 0xda, 0x2e, 0x4d, 0xff, 0xba, 0x30, 0x13, 0x27, 0x7c, 0x39, + 0xf0, 0xb0, 0xb1, 0x77, 0x03, 0xd3, 0x1d, 0x99, 0x6d, 0xfa, 0x15, 0x13, 0x2b, 0xfd, 0x65, 0x00, + 0x12, 0x3b, 0xf1, 0x51, 0x7c, 0x92, 0xd5, 0x02, 0xe1, 0xeb, 0xd2, 0xe7, 0x60, 0x64, 0x65, 0xc0, + 0x9d, 0xe2, 0x31, 0x67, 0xd6, 0x1e, 0x7c, 0x47, 0xee, 0xc8, 0x19, 0x0c, 0xa4, 0xd8, 0x0f, 0xd2, + 0x7a, 0xec, 0x3c, 0x35, 0x3e, 0xd2, 0xf0, 0x39, 0x8f, 0x87, 0xfb, 0xb6, 0xaf, 0x23, 0x3e, 0xb4, + 0x70, 0x46, 0xc2, 0x15, 0xa3, 0x26, 0x29, 0xd5, 0x31, 0x29, 0xd3, 0x33, 0x71, 0x63, 0xbe, 0x09, + 0x65, 0x43, 0x90, 0x2a, 0x0d, 0x2f, 0x1c, 0xe3, 0xfa, 0x2b, 0x6a, 0x1c, 0x95, 0x47, 0x60, 0xf4, + 0x45, 0xb5, 0x78, 0x03, 0xfc, 0x56, 0x25, 0xf7, 0xb2, 0x3a, 0x08, 0x36, 0x3d, 0x1d, 0x30, 0xef, + 0x1f, 0x63, 0x61, 0x73, 0x58, 0x13, 0x41, 0xc7, 0x84, 0x08, 0x8e, 0x32, 0x15, 0x65, 0x25, 0xe8, + 0x11, 0xea, 0x04, 0x7c, 0x20, 0xf4, 0xdd, 0x53, 0xaf, 0xfb, 0x6c, 0x65, 0xac, 0x55, 0x2d, 0x11, + 0x3c, 0x9e, 0x28, 0x46, 0xc6, 0x64, 0x98, 0x18, 0x60, 0xf4, 0x6c, 0x21, 0xb2, 0x51, 0xa9, 0xfe, + 0xb2, 0xeb, 0x50, 0xaa, 0x9a, 0x20, 0xf8, 0xc1, 0x46, 0x97, 0x77, 0x21, 0x8f, 0x2f, 0x53, 0x0a, + 0x66, 0xc4, 0x02, 0x1c, 0xfd, 0x44, 0x04, 0x49, 0x86, 0x93, 0x42, 0xde, 0xab, 0x9b, 0x9a, 0xdb, + 0x39, 0x5e, 0x87, 0xab, 0x8f, 0x85, 0x22, 0xd3, 0x38, 0x41, 0xb6, 0xf0, 0x34, 0x4b, 0xe0, 0x9a, + 0x69, 0x61, 0xb8, 0x4b, 0x01, 0xf0, 0xa6, 0xcc, 0x73, 0x98, 0xda, 0x6b, 0x12, 0xce, 0x0b, 0xbf, + 0x4d, 0x9f, 0x29, 0xda, 0x8b, 0x64, 0x8e, 0x0c, 0x9b, 0xd8, 0xa3, 0xf1, 0x44, 0xbd, 0x55, 0x37, + 0x54, 0xee, 0x4e, 0x7c, 0xbd, 0x89, 0x1b, 0x91, 0x2d, 0x2c, 0xfb, 0xa1, 0x4c, 0xfb, 0x01, 0x2b, + 0x6c, 0x8c, 0xac, 0x75, 0x37, 0xcd, 0x64, 0x75, 0xb2, 0x78, 0xd0, 0xfe, 0x8c, 0x41, 0xc7, 0xd5, + 0x8a, 0x55, 0xc4, 0xd4, 0x2b, 0x6d, 0xa2, 0xfb, 0xa7, 0xe8, 0x87, 0xd3, 0x74, 0x8c, 0x91, 0xe3, + 0x89, 0x17, 0x79, 0x10, 0x34, 0x4f, 0x39, 0x93, 0xe6, 0x33, 0x60, 0x96, 0xa6, 0xd9, 0x70, 0x47, + 0x31, 0xa0, 0x35, 0x6a, 0x58, 0x14, 0xb7, 0xb0, 0xeb, 0x0d, 0xc3, 0x6a, 0x6d, 0xc0, 0x85, 0x04 +}; + +#endif + +#endif // _RM_SPDM_RSA_KEYS_H_ diff --git a/userspace/sdks/nv570/nvalloc/common/inc/spdm/rmspdmtransport.h b/userspace/sdks/nv570/nvalloc/common/inc/spdm/rmspdmtransport.h new file mode 100644 index 0000000..9440ed8 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/spdm/rmspdmtransport.h @@ -0,0 +1,97 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _RM_SPDM_TRANSPORT_H_ +#define _RM_SPDM_TRANSPORT_H_ + +/* ------------------------- Macros and Defines ----------------------------- */ +// +// The following defines and macros are shared for any message-related constants +// shared between RM and endpoint. +// + +// Defines used for polling-based communication between Kernel-RM and GSP. +#define NV_SPDM_PARTITION_BOOT_SUCCESS (0x59D3B007) +#define NV_SPDM_REQUESTER_SECRETS_DERIVED (0x59D35DED) +#define NV_SPDM_NO_MESSAGE_PENDING_TOKEN (0x00000000) +#define NV_SPDM_REQUESTER_MESSAGE_PENDING_TOKEN (0xAFAFAFAF) +#define NV_SPDM_RESPONDER_MESSAGE_PENDING_TOKEN (0xFAFAFAFA) +#define NV_SPDM_SECRET_TEARDOWN_SUCCESS (0x59D35EDE) +#define NV_SPDM_SECRET_TEARDOWN_FAILURE (0x59D35EFA) +#define NV_SPDM_SECRET_TEARDOWN_ACK (0x59D35EAC) + +// TDISP Defines for polling-based communication between Kernel-RM and GSP. +#define NV_TDISP_PARTITION_BOOT_SUCCESS (0x59D4B001) + +// +// The SPDM communication between Kernel-RM and GSP utilizes a buffer in sysmem accessible +// to both endpoints. The sysmem buffer will contain both a custom NV-defined header +// describing the message type and size, and the SPDM payload itself. +// + +// +// Size of the full transportation buffer (header + SPDM payload) allocated in sysmem. +// We need to align sysmem allocations with page size, but need less space. So we +// over-allocate and tell GSP we only have the size we actually need. +// +#define NV_SPDM_SYSMEM_SURFACE_SIZE_PAGE_ALIGNED (0x2000) +#define NV_SPDM_SYSMEM_SURFACE_SIZE_IN_BYTES (0x1200) +#define NV_SPDM_SYSMEM_SURFACE_ALIGNMENT_IN_BYTES (256) + +// Struct and defines for the header which prepends the SPDM payload. +#pragma pack(1) +typedef struct _NV_SPDM_DESC_HEADER +{ + NvU32 msgType; + NvU32 msgSizeByte; + NvU32 version; +} NV_SPDM_DESC_HEADER, *PNV_SPDM_DESC_HEADER; +#pragma pack() + +#define NV_SPDM_MESSAGE_TYPE_NORMAL (0) +#define NV_SPDM_MESSAGE_TYPE_SECURED (1) +#define NV_SPDM_MESSAGE_TYPE_APPLICATION (2) +#define NV_SPDM_DESC_HEADER_VERSION_1_0 (0x10) +#define NV_SPDM_DESC_HEADER_VERSION_CURRENT (NV_SPDM_DESC_HEADER_VERSION_1_0) +#define NV_SPDM_DESC_HEADER_ALIGNMENT_IN_BYTES (NV_SPDM_SYSMEM_SURFACE_ALIGNMENT_IN_BYTES) + +// Define utilized to determine size available for SPDM payload +#define NV_SPDM_MAX_SPDM_PAYLOAD_SIZE (NV_SPDM_SYSMEM_SURFACE_SIZE_IN_BYTES - sizeof(NV_SPDM_DESC_HEADER)) +#define NV_SPDM_MAX_TRANSCRIPT_BUFFER_SIZE (2 * NV_SPDM_MAX_SPDM_PAYLOAD_SIZE) + +// Limited by the transport size, do not increase without increasing transport buffer. +#define NV_SPDM_MAX_RANDOM_MSG_BYTES (0x0) + +#ifdef NVRM +#include "gpu/mem_mgr/mem_desc.h" +#else +#ifndef ADDR_SYSMEM +// System memory (PCI) +#define ADDR_SYSMEM (1) +#endif // ADDR_SYSMEM +#endif //NVRM + +#define NV_SPDM_DMA_ADDR_SPACE_DEFAULT (ADDR_SYSMEM) +#define NV_SPDM_DMA_REGION_ID_DEFAULT (0) + +#endif // _RM_SPDM_TRANSPORT_H_ diff --git a/userspace/sdks/nv570/nvalloc/common/inc/spdm/rmspdmvendordef.h b/userspace/sdks/nv570/nvalloc/common/inc/spdm/rmspdmvendordef.h new file mode 100644 index 0000000..76eec37 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/common/inc/spdm/rmspdmvendordef.h @@ -0,0 +1,161 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _RMSPDMVENDORDEF_H_ +#define _RMSPDMVENDORDEF_H_ +#include + +/*! + * In NVIDIA's implementation of SPDM, we will support application messages + * which are payloads delivered encrypted in SPDM secured messages, + * sent across the SPDM channel, but do not contain SPDM messages. + * Instead, these messages are for NVIDIA-application purposes. + * These messages and relevant structs are defined here. + */ + +/* ------------------------- Application Payloads ------------------------ */ +/*! + * All application messages will follow a simple header format in order to + * simplify the parsing and forwarding of application messages to the + * relevant recipient endpoint. This format is defined as follows: + * + * +----------------------------------+ + * | RM_SPDM_NV_CMD | + * | Command Type | Command Payload | + * | (4 bytes) (n - 4 - 4 bytes) | + * +----------------------------------+ + * + * The Command Type value defines the expected structure of the payload, + * and how it should be interpreted. + * + * There are two major categories of commands - requests and responses. + * The values of 0x00000000-0x7FFFFFFF are reserved for requests. + * The values of 0x80000000-0xFFFFFFFF are reserved for responses. + */ + +typedef enum +{ + // Request commands. + RM_SPDM_NV_CMD_TYPE_REQ_KEYMGR_NVLE = 0x00000000, + // 0x00000001 - 0x7FFFFFFF reserved. + + // Response commands. + RM_SPDM_NV_CMD_TYPE_RSP_SUCCESS = 0x80000000, + // 0x80000001 - 0xFFFFFFFF reserved. + RM_SPDM_NV_CMD_TYPE_RSP_ERROR = 0xFFFFFFFF, +} RM_SPDM_NV_CMD_TYPE; + +typedef struct +{ + NvU32 cmdType; +} RM_SPDM_NV_CMD_HDR; + +/* ------------------------- NVIDIA Requests -------------------------------- */ +/*! + * Request Command: Key Manager NVLE Command + * Command Type: 0x00000000 + * + * Fields: + * Payload - Variable size opaque data blob containing command meant for Key manager + * + * This command is a generic wrapper around all commands that must be forwarded to Key Manager for NvLink Encryption. + * The command structure itself is opaque, as SPDM need not process any of the message itself. This limits coupling + * between the two command interfaces. + */ +typedef struct +{ + RM_SPDM_NV_CMD_HDR hdr; + + NvU8 payload[]; +} RM_SPDM_NV_CMD_REQ_KEYMGR_NVLE; + +/*! + * Union of all known requests, so responder can allocate enough space for all possible requests. + */ +typedef union { + RM_SPDM_NV_CMD_HDR hdr; + + RM_SPDM_NV_CMD_REQ_KEYMGR_NVLE keyMgrNvle; +} RM_SPDM_NV_CMD_REQ; + +/* ------------------------- NVIDIA Responses ------------------------------- */ +/*! + * Response Command: Success + * Command Type: 0x80000000 + * + * This command is a simple payload for the responding endpoint to + * return success. It has no Command Payload. + */ +typedef struct +{ + RM_SPDM_NV_CMD_HDR hdr; +} RM_SPDM_NV_CMD_RSP_SUCCESS; + +/*! + * Response Command: Error + * Command Type: 0xFFFFFFFF + * + * This command is a generic placeholder error response to return specific + * failure code to application endpoint. This is used to return an error + * back to the original application which sent the message, rather than + * suggesting that there was some SPDM or transport layer error. + */ +typedef struct +{ + RM_SPDM_NV_CMD_HDR hdr; + NV_STATUS status; +} RM_SPDM_NV_CMD_RSP_ERROR; + +/*! + * Union of all known responses, so requester can allocate enough space for all possible responses. + */ +typedef union { + RM_SPDM_NV_CMD_HDR hdr; + + RM_SPDM_NV_CMD_RSP_SUCCESS success; + RM_SPDM_NV_CMD_RSP_ERROR error; +} RM_SPDM_NV_CMD_RSP; + +#pragma pack() + +/* ------------------------- Macros ----------------------------------------- */ +#define SPDM_MAX_MEASUREMENT_BLOCK_COUNT (64) +#define SPDM_CERT_DEFAULT_SLOT_ID (0) +#define SPDM_CAPABILITIES_CT_EXPONENT_MAX (0x1F) +#define SPDM_DEFAULT_HEARTBEAT_PERIOD_IN_SEC (4) + +#define NV_BYTE_TO_BIT_OVERFLOW_MASK_UINT32 (0xE0000000) +#define IS_BYTE_TO_BIT_OVERFLOW_UINT32(a) \ + ((a & NV_BYTE_TO_BIT_OVERFLOW_MASK_UINT32) != 0) + +/* ---------------------- Public defines ------------------------------------- */ +#define NV_KEY_UPDATE_TRIGGER_THRESHOLD (0x10000000) + +#define NV_KEY_UPDATE_TRIGGER_ID_INVALID (0) +#define NV_KEY_UPDATE_TRIGGER_ID_GET_MEASUREMENTS (1) +#define NV_KEY_UPDATE_TRIGGER_ID_HEARTBEAT (2) +#define NV_KEY_UPDATE_TRIGGER_ID_LAST (3) + +#define NV_SPDM_ENCAP_CERT_SIZE_IN_BYTE (578) + +#endif // _RMSPDMVENDORDEF_H_ diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv-caps.h b/userspace/sdks/nv570/nvalloc/unix/include/nv-caps.h new file mode 100644 index 0000000..35bbf7c --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/nv-caps.h @@ -0,0 +1,94 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NV_CAPS_H_ +#define _NV_CAPS_H_ + +#include + +/* + * Opaque OS-specific struct; on Linux, this has member + * 'struct proc_dir_entry'. + */ +typedef struct nv_cap nv_cap_t; + +/* + * Creates directory named "capabilities" under the provided path. + * + * @param[in] path Absolute path + * + * Returns a valid nv_cap_t upon success. Otherwise, returns NULL. + */ +nv_cap_t* NV_API_CALL nv_cap_init(const char *path); + +/* + * Creates capability directory entry + * + * @param[in] parent_cap Parent capability directory + * @param[in] name Capability directory's name + * @param[in] mode Capability directory's access mode + * + * Returns a valid nv_cap_t upon success. Otherwise, returns NULL. + */ +nv_cap_t* NV_API_CALL nv_cap_create_dir_entry(nv_cap_t *parent_cap, const char *name, int mode); + +/* + * Creates capability file entry + * + * @param[in] parent_cap Parent capability directory + * @param[in] name Capability file's name + * @param[in] mode Capability file's access mode + * + * Returns a valid nv_cap_t upon success. Otherwise, returns NULL. + */ +nv_cap_t* NV_API_CALL nv_cap_create_file_entry(nv_cap_t *parent_cap, const char *name, int mode); + +/* + * Destroys capability entry + * + * @param[in] cap Capability entry + */ +void NV_API_CALL nv_cap_destroy_entry(nv_cap_t *cap); + +/* + * Validates and duplicates the provided file descriptor + * + * @param[in] cap Capability entry + * @param[in] fd File descriptor to be validated + * + * Returns duplicate fd upon success. Otherwise, returns -1. + */ +int NV_API_CALL nv_cap_validate_and_dup_fd(const nv_cap_t *cap, int fd); + +/* + * Closes file descriptor + * + * This function should be used to close duplicate file descriptors + * returned by nv_cap_validate_and_dup_fd. + * + * @param[in] fd File descriptor to be validated + * + */ +void NV_API_CALL nv_cap_close_fd(int fd); + +#endif /* _NV_CAPS_H_ */ diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv-chardev-numbers.h b/userspace/sdks/nv570/nvalloc/unix/include/nv-chardev-numbers.h new file mode 100644 index 0000000..54ca547 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/nv-chardev-numbers.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _NV_CHARDEV_NUMBERS_H_ +#define _NV_CHARDEV_NUMBERS_H_ + +// NVIDIA's reserved major character device number (Linux). +#define NV_MAJOR_DEVICE_NUMBER 195 + +// Minor numbers 0 to 247 reserved for regular devices +#define NV_MINOR_DEVICE_NUMBER_REGULAR_MAX 247 + +// Minor numbers 248 to 253 currently unused + +// Minor number 254 reserved for the modeset device (provided by NVKMS) +#define NV_MINOR_DEVICE_NUMBER_MODESET_DEVICE 254 + +// Minor number 255 reserved for the control device +#define NV_MINOR_DEVICE_NUMBER_CONTROL_DEVICE 255 + +#endif // _NV_CHARDEV_NUMBERS_H_ + diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv-gpu-info.h b/userspace/sdks/nv570/nvalloc/unix/include/nv-gpu-info.h new file mode 100644 index 0000000..1b79320 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/nv-gpu-info.h @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NV_GPU_INFO_H_ +#define _NV_GPU_INFO_H_ + +typedef struct { + NvU32 gpu_id; + + struct { + NvU32 domain; + NvU8 bus, slot, function; + } pci_info; + + NvBool needs_numa_setup; + NvBool is_soc_disp; + + /* + * opaque OS-specific pointer; on Linux, this is a pointer to the + * 'struct device' for the GPU. + */ + void *os_device_ptr; +} nv_gpu_info_t; + +#define NV_MAX_GPUS 32 + +#endif /* _NV_GPU_INFO_H_ */ diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv-ioctl-lockless-diag.h b/userspace/sdks/nv570/nvalloc/unix/include/nv-ioctl-lockless-diag.h new file mode 100644 index 0000000..84e3fa7 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/nv-ioctl-lockless-diag.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#if !defined(NV_IOCTL_LOCKLESS_DIAG) +#define NV_IOCTL_LOCKLESS_DIAG + +#include +#include "ctrl/ctrl0000/ctrl0000nvd.h" + +typedef struct +{ + NvU32 cmd; // in + NvU32 status; // out + union // in/out + { + NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS getNvlogInfo; + NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS getNvlogBufferInfo; + NV0000_CTRL_NVD_GET_NVLOG_PARAMS getNvlog; + } params; +} NV_LOCKLESS_DIAGNOSTIC_PARAMS; + +#endif + diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv-ioctl-numa.h b/userspace/sdks/nv570/nvalloc/unix/include/nv-ioctl-numa.h new file mode 100644 index 0000000..0af5267 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/nv-ioctl-numa.h @@ -0,0 +1,81 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef NV_IOCTL_NUMA_H +#define NV_IOCTL_NUMA_H + +#include + +#if defined(NV_KERNEL_INTERFACE_LAYER) && defined(NV_LINUX) +#include +#elif defined (NV_KERNEL_INTERFACE_LAYER) && defined(NV_BSD) +#include +#else + +#include + +#if !defined(__aligned) +#define __aligned(n) __attribute__((aligned(n))) +#endif + +#endif + +#define NV_ESC_NUMA_INFO (NV_IOCTL_BASE + 15) +#define NV_ESC_SET_NUMA_STATUS (NV_IOCTL_BASE + 16) + +#define NV_IOCTL_NUMA_INFO_MAX_OFFLINE_ADDRESSES 64 +typedef struct offline_addresses +{ + uint64_t addresses[NV_IOCTL_NUMA_INFO_MAX_OFFLINE_ADDRESSES] __aligned(8); + uint32_t numEntries; +} nv_offline_addresses_t; + + +/* per-device NUMA memory info as assigned by the system */ +typedef struct nv_ioctl_numa_info +{ + int32_t nid; + int32_t status; + uint64_t memblock_size __aligned(8); + uint64_t numa_mem_addr __aligned(8); + uint64_t numa_mem_size __aligned(8); + uint8_t use_auto_online; + nv_offline_addresses_t offline_addresses __aligned(8); +} nv_ioctl_numa_info_t; + +/* set the status of the device NUMA memory */ +typedef struct nv_ioctl_set_numa_status +{ + int32_t status; +} nv_ioctl_set_numa_status_t; + +#define NV_IOCTL_NUMA_STATUS_DISABLED 0 +#define NV_IOCTL_NUMA_STATUS_OFFLINE 1 +#define NV_IOCTL_NUMA_STATUS_ONLINE_IN_PROGRESS 2 +#define NV_IOCTL_NUMA_STATUS_ONLINE 3 +#define NV_IOCTL_NUMA_STATUS_ONLINE_FAILED 4 +#define NV_IOCTL_NUMA_STATUS_OFFLINE_IN_PROGRESS 5 +#define NV_IOCTL_NUMA_STATUS_OFFLINE_FAILED 6 + +#endif diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv-ioctl-numbers.h b/userspace/sdks/nv570/nvalloc/unix/include/nv-ioctl-numbers.h new file mode 100644 index 0000000..e266368 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/nv-ioctl-numbers.h @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef NV_IOCTL_NUMBERS_H +#define NV_IOCTL_NUMBERS_H + +/* NOTE: using an ioctl() number > 55 will overflow! */ +/* + * NOTE: Any new ioctls added here should also be added to nv_validate_ioctls() in nv.c or + * rm_validate_ioctls() in osapi.c + */ +#define NV_IOCTL_MAGIC 'F' +#define NV_IOCTL_BASE 200 +#define NV_ESC_CARD_INFO (NV_IOCTL_BASE + 0) +#define NV_ESC_REGISTER_FD (NV_IOCTL_BASE + 1) +#define NV_ESC_ALLOC_OS_EVENT (NV_IOCTL_BASE + 6) +#define NV_ESC_FREE_OS_EVENT (NV_IOCTL_BASE + 7) +#define NV_ESC_STATUS_CODE (NV_IOCTL_BASE + 9) +#define NV_ESC_CHECK_VERSION_STR (NV_IOCTL_BASE + 10) +#define NV_ESC_IOCTL_XFER_CMD (NV_IOCTL_BASE + 11) +#define NV_ESC_ATTACH_GPUS_TO_FD (NV_IOCTL_BASE + 12) +#define NV_ESC_QUERY_DEVICE_INTR (NV_IOCTL_BASE + 13) +#define NV_ESC_SYS_PARAMS (NV_IOCTL_BASE + 14) +#define NV_ESC_EXPORT_TO_DMABUF_FD (NV_IOCTL_BASE + 17) +#define NV_ESC_WAIT_OPEN_COMPLETE (NV_IOCTL_BASE + 18) + +#endif diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv-ioctl.h b/userspace/sdks/nv570/nvalloc/unix/include/nv-ioctl.h new file mode 100644 index 0000000..8ca1642 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/nv-ioctl.h @@ -0,0 +1,158 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef NV_IOCTL_H +#define NV_IOCTL_H + +#include +#include +#include + + +typedef struct { + NvU32 domain; /* PCI domain number */ + NvU8 bus; /* PCI bus number */ + NvU8 slot; /* PCI slot number */ + NvU8 function; /* PCI function number */ + NvU16 vendor_id; /* PCI vendor ID */ + NvU16 device_id; /* PCI device ID */ +} nv_pci_info_t; + +/* + * ioctl()'s with parameter structures too large for the + * _IOC cmd layout use the nv_ioctl_xfer_t structure + * and the NV_ESC_IOCTL_XFER_CMD ioctl() to pass the actual + * size and user argument pointer into the RM, which + * will then copy it to/from kernel space in separate steps. + */ +typedef struct nv_ioctl_xfer +{ + NvU32 cmd; + NvU32 size; + NvP64 ptr NV_ALIGN_BYTES(8); +} nv_ioctl_xfer_t; + +typedef struct nv_ioctl_card_info +{ + NvBool valid; + nv_pci_info_t pci_info; /* PCI config information */ + NvU32 gpu_id; + NvU16 interrupt_line; + NvU64 reg_address NV_ALIGN_BYTES(8); + NvU64 reg_size NV_ALIGN_BYTES(8); + NvU64 fb_address NV_ALIGN_BYTES(8); + NvU64 fb_size NV_ALIGN_BYTES(8); + NvU32 minor_number; + NvU8 dev_name[10]; /* device names such as vmgfx[0-32] for vmkernel */ +} nv_ioctl_card_info_t; + +/* alloc event */ +typedef struct nv_ioctl_alloc_os_event +{ + NvHandle hClient; + NvHandle hDevice; + NvU32 fd; + NvU32 Status; +} nv_ioctl_alloc_os_event_t; + +/* free event */ +typedef struct nv_ioctl_free_os_event +{ + NvHandle hClient; + NvHandle hDevice; + NvU32 fd; + NvU32 Status; +} nv_ioctl_free_os_event_t; + +/* status code */ +typedef struct nv_ioctl_status_code +{ + NvU32 domain; + NvU8 bus; + NvU8 slot; + NvU32 status; +} nv_ioctl_status_code_t; + +/* check version string */ +#define NV_RM_API_VERSION_STRING_LENGTH 64 + +typedef struct nv_ioctl_rm_api_version +{ + NvU32 cmd; + NvU32 reply; + char versionString[NV_RM_API_VERSION_STRING_LENGTH]; +} nv_ioctl_rm_api_version_t; + +#define NV_RM_API_VERSION_CMD_STRICT 0 +#define NV_RM_API_VERSION_CMD_RELAXED '1' +#define NV_RM_API_VERSION_CMD_QUERY '2' + +#define NV_RM_API_VERSION_REPLY_UNRECOGNIZED 0 +#define NV_RM_API_VERSION_REPLY_RECOGNIZED 1 + +typedef struct nv_ioctl_query_device_intr +{ + NvU32 intrStatus NV_ALIGN_BYTES(4); + NvU32 status; +} nv_ioctl_query_device_intr_t; + +/* system parameters that the kernel driver may use for configuration */ +typedef struct nv_ioctl_sys_params +{ + NvU64 memblock_size NV_ALIGN_BYTES(8); +} nv_ioctl_sys_params_t; + +typedef struct nv_ioctl_register_fd +{ + int ctl_fd; +} nv_ioctl_register_fd_t; + +#define NV_DMABUF_EXPORT_MAX_HANDLES 128 + +#define NV_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT 0 +#define NV_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE 1 + +typedef struct nv_ioctl_export_to_dma_buf_fd +{ + int fd; + NvHandle hClient; + NvU32 totalObjects; + NvU32 numObjects; + NvU32 index; + NvU64 totalSize NV_ALIGN_BYTES(8); + NvU8 mappingType; + NvBool bAllowMmap; + NvHandle handles[NV_DMABUF_EXPORT_MAX_HANDLES]; + NvU64 offsets[NV_DMABUF_EXPORT_MAX_HANDLES] NV_ALIGN_BYTES(8); + NvU64 sizes[NV_DMABUF_EXPORT_MAX_HANDLES] NV_ALIGN_BYTES(8); + NvU32 status; +} nv_ioctl_export_to_dma_buf_fd_t; + +typedef struct nv_ioctl_wait_open_complete +{ + int rc; + NvU32 adapterStatus; +} nv_ioctl_wait_open_complete_t; + +#endif diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv-kernel-rmapi-ops.h b/userspace/sdks/nv570/nvalloc/unix/include/nv-kernel-rmapi-ops.h new file mode 100644 index 0000000..d50a1e4 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/nv-kernel-rmapi-ops.h @@ -0,0 +1,61 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NV_KERNEL_RMAPI_OPS_H_ +#define _NV_KERNEL_RMAPI_OPS_H_ + +/* + * Define the RMAPI provided to kernel-level RM clients. + * + * Kernel-level RM clients should populate nvidia_kernel_rmapi_ops_t + * by assigning nvidia_kernel_rmapi_ops_t::op and the corresponding + * parameter structure in nvidia_kernel_rmapi_ops_t's params union. + * Then, pass a pointer to the nvidia_kernel_rmapi_ops_t to + * rm_kernel_rmapi_op(). + */ + +#include "nvtypes.h" +#include "nvos.h" + +typedef struct { + NvU32 op; /* One of the NV0[14]_XXXX operations listed below. */ + + union { + NVOS00_PARAMETERS free; /* NV01_FREE */ + NVOS02_PARAMETERS allocMemory64; /* NV01_ALLOC_MEMORY */ + NVOS64_PARAMETERS alloc; /* NV04_ALLOC */ + NVOS32_PARAMETERS *pVidHeapControl; /* NV04_VID_HEAP_CONTROL */ + NVOS33_PARAMETERS mapMemory; /* NV04_MAP_MEMORY */ + NVOS34_PARAMETERS unmapMemory; /* NV04_UNMAP_MEMORY */ + NVOS39_PARAMETERS allocContextDma2; /* NV04_ALLOC_CONTEXT_DMA */ + NVOS46_PARAMETERS mapMemoryDma; /* NV04_MAP_MEMORY_DMA */ + NVOS47_PARAMETERS unmapMemoryDma; /* NV04_UNMAP_MEMORY_DMA */ + NVOS49_PARAMETERS bindContextDma; /* NV04_BIND_CONTEXT_DMA */ + NVOS54_PARAMETERS control; /* NV04_CONTROL*/ + NVOS55_PARAMETERS dupObject; /* NV04_DUP_OBJECT */ + NVOS57_PARAMETERS share; /* NV04_SHARE */ + NVOS61_PARAMETERS addVblankCallback; /* NV04_ADD_VBLANK_CALLBACK */ + } params; +} nvidia_kernel_rmapi_ops_t; + +#endif /* _NV_KERNEL_RMAPI_OPS_H_ */ diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv-nb-regs.h b/userspace/sdks/nv570/nvalloc/unix/include/nv-nb-regs.h new file mode 100644 index 0000000..6282b35 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/nv-nb-regs.h @@ -0,0 +1,65 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NV_NB_REGS_H_ +#define _NV_NB_REGS_H_ + +#include "nvdevid.h" + +typedef struct +{ + NvU32 subsystem_vendor_id; + NvU32 subsystem_device_id; + NvU16 gpu_device_id; +} nv_nb_id_t; + +typedef struct +{ + NvU32 vendor_id; + const char *name; + NvU32 data; +} nv_nb_reg_t; + +/* + * nb_id_table contains the OEM vendor ID, the subsystem ID and the + * GPU device ID of the notebooks for which we need to enable + * vendor specific registry keys. nb_reg_table contains the vendor + * specific registry key values. The initVendorSpecificRegistry() + * function compares the present notebooks OEM subsystem ID and the + * GPU device ID with the values present in id_tables. If a match + * is found, initVendorSpecificRegistry() extracts the vendor + * ID and sets any associated registry key listed in nb_reg_table. + */ + +static nv_nb_id_t nb_id_table[] = { + { PCI_VENDOR_ID_PC_PARTNER, 0x0620, 0x1284 }, // Acer GT 630 + { PCI_VENDOR_ID_PC_PARTNER, 0x0620, 0x124b }, // Acer GT 640 + { 0, 0, 0 } +}; + +static nv_nb_reg_t nb_reg_table[] = { + { PCI_VENDOR_ID_PC_PARTNER, "RmOverrideSupportChipsetAspm", 2 }, + { 0, NULL, 0 } +}; + +#endif //_NV_NB_REGS_H_ diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv-priv.h b/userspace/sdks/nv570/nvalloc/unix/include/nv-priv.h new file mode 100644 index 0000000..a3dcebf --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/nv-priv.h @@ -0,0 +1,357 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NV_PRIV_H_ +#define _NV_PRIV_H_ + +#include +#include +#include +#include +#include + +#define NV_PRIV_REG_WR08(b,o,d) (*((volatile NvV8*)&(b)->Reg008[(o)/1])=(NvV8)(d)) +#define NV_PRIV_REG_WR16(b,o,d) (*((volatile NvV16*)&(b)->Reg016[(o)/2])=(NvV16)(d)) +#define NV_PRIV_REG_WR32(b,o,d) (*((volatile NvV32*)&(b)->Reg032[(o)/4])=(NvV32)(d)) + +#define NV_PRIV_REG_RD08(b,o) ((b)->Reg008[(o)/1]) +#define NV_PRIV_REG_RD16(b,o) ((b)->Reg016[(o)/2]) +#define NV_PRIV_REG_RD32(b,o) ((b)->Reg032[(o)/4]) + +struct OBJGPU; + +typedef struct +{ + NvBool baseValid; + VGAADDRDESC base; + NvBool workspaceBaseValid; + VGAADDRDESC workspaceBase; + NvU32 vesaMode; +} nv_vga_t; + +/* +* device state during Power Management +*/ +typedef struct nv_pm_state_s +{ + NvU32 IntrEn; + NvBool InHibernate; +} nv_pm_state_t; + +/* +* data structure for the UNIX workqueues +*/ +typedef struct nv_work_item_s +{ + OsQueueWorkItemFlags flags; + NvU32 gpuInstance; + union + { + OSWorkItemFunction *pGpuFunction; + OSSystemWorkItemFunction *pSystemFunction; + } func; + void *pData; +} nv_work_item_t; + +#define INVALID_DISP_ID 0xFFFFFFFF +#define MAX_DISP_ID_PER_ADAPTER 0x2 + +typedef struct nv_i2c_adapter_entry_s +{ + void *pOsAdapter; + NvU32 port; + NvU32 displayId[MAX_DISP_ID_PER_ADAPTER]; +} nv_i2c_adapter_entry_t; + +#define NV_INIT_FLAG_HAL 0x0001 +#define NV_INIT_FLAG_HAL_COMPONENTS 0x0002 +#define NV_INIT_FLAG_GPU_STATE 0x0004 +#define NV_INIT_FLAG_GPU_STATE_LOAD 0x0008 +#define NV_INIT_FLAG_FIFO_WATCHDOG 0x0010 +#define NV_INIT_FLAG_CORE_LOGIC 0x0020 +#define NV_INIT_FLAG_GPUMGR_ATTACH 0x0040 +#define NV_INIT_FLAG_PUBLIC_I2C 0x0080 +#define NV_INIT_FLAG_SCALABILITY 0x0100 +#define NV_INIT_FLAG_DMA 0x0200 + +#define MAX_I2C_ADAPTERS NV402C_CTRL_NUM_I2C_PORTS + +/* + * GPU dynamic power state machine. + * + * The GPU is in exactly one of these states at at time. Only certain state + * transitions are valid, as documented by the DAGs below. + * + * When in "instant idle" or COARSE mode: + * + * +----------------------+ + * v | + * +---------+ +----------------+ +--------+ + * | UNKNOWN | --> | IDLE_INDICATED | --> | IN_USE | + * +---------+ +----------------+ +--------+ + * + * The transition from UNKNOWN to IDLE_INDICATED happens in + * rm_init_dynamic_power_management(). + * + * Thereafter, transitions from IDLE_INDICATED to IN_USE happen when + * os_ref_dynamic_power() is called and the refcount transitions from 0 to 1; + * transitions from IN_USE to IDLE_INDICATED happen when + * os_unref_dynamic_power() is called and the refcount transitions from 1 to 0. + * Note that only calls to os_(un)ref_dynamic_power() with the mode == COARSE + * are considered in this mode; calls with mode == FINE are ignored. Since + * COARSE calls are placed only in rm_init_adapter/rm_shutdown_adapter, the GPU + * effectively stays in the IN_USE state any time any client has initialized + * it. + * + * + * When in "deferred idle" or FINE mode: + * + * +----------------------------------------------------------------+ + * | | + * | | + * | +-------------------------------------------+----------------------+ + * | | | v + * | +---------+ +----------------+ +--------------+ +----------------+ +--------+ + * | | UNKNOWN | --> | IDLE_INDICATED | --> | | --> | IDLE_SUSTAINED | --> | IN_USE | -+ + * | +---------+ +----------------+ | | +----------------+ +--------+ | + * | ^ | | | ^ | + * +--------------------+ | IDLE_INSTANT | ------+----------------------+ | + * | | | | + * | | | | + * | | <-----+ | + * +--------------+ | + * ^ | + * +-----------------------------------------------------+ + * + * As before, the transition from UNKNOWN to IDLE_INDICATED happens in + * rm_init_dynamic_power_management(). This is not ideal: it means the GPU may + * be powered down immediately upon loading the RM module, even if + * rm_init_adapter() is going to be called soon thereafter. However, we can't + * rely on deferred idle callbacks yet, since those currently rely on core RM + * being initialized. + * + * At the beginning of rm_init_adapter(), the GPU transitions to the IN_USE + * state; during the rm_init_adapter() sequence, + * RmInitDeferredDynamicPowerManagement() will be called which will schedule + * timer callbacks and set the "deferred_idle_enabled" boolean. + * + * While in "deferred idle" mode, one of the callbacks + * timerCallbackForIdlePreConditions(), timerCallbackToIndicateIdle(), or + * RmIndicateIdle() should be scheduled when in the states: + * - IN_USE + * - IDLE_INSTANT + * - IDLE_SUSTAINED + * Note that since we may transition from IN_USE to IDLE_INSTANT rapidly (e.g., + * for a series of RM calls), we don't attempt to schedule the callbacks and + * cancel them on each of these transitions. The + * timerCallbackForIdlePreConditions() callback will simply exit early if in + * the IN_USE state. + * + * As before, the GPU will remain in the IN_USE state until + * os_unref_dynamic_power() is called and the count transitions from 1 to 0 + * (calls with mode == FINE are honored, in this mode, and these transitions + * can happen frequently). When the refcount reaches 0, rather than going + * directly to the IDLE_INDICATED state, it transitions to the IDLE_INSTANT + * state. + * + * Then, when the next timerCallbackForIdlePreConditions() callback executes, + * if all preconditions are met, the state will transition to IDLE_SUSTAINED. + * + * If, when in the IDLE_SUSTAINED state, os_ref_dynamic_power() is called, the + * GPU will transition back to the IN_USE state and return to the IDLE_INSTANT + * state. This ensures that there is a suitable delay between any activity + * that requires bumping the refcount and indicating idleness. + * + * If the timerCallbackForIdlePreConditions() callback executes again and the + * GPU is still in the IDLE_SUSTAINED state, userspace mappings will be revoked + * and the timerCallbackToIndicateIdle() callback will be scheduled. + * + * If, before the timerCallbackToIndicateIdle() callback executes, either + * os_ref_dynamic_power() is called or a mapping which has been revoked is + * accessed (which triggers the RmForceGpuNotIdle() callback), the GPU will + * transition back to the IN_USE or IDLE_INSTANT state, respectively. + * + * Then, when the timerCallbackToIndicateIdle() callback executes, if all + * mappings are still revoked, and the GPU is still in the IDLE_SUSTAINED + * state, and all GPU idleness preconditions remain satisfied, the + * RmIndicateIdle() work item will be enqueued. (Else, the GPU will transition + * back to the IDLE_INSTANT state and the callback for preconditions is + * scheduled again.) + * + * Finally, once the RmIndicateIdle() work item is called, if all of the same + * conditions still hold, the state will transition to IDLE_INDICATED. No + * callbacks will be scheduled from here; the callbacks for preconditions + * should be re-scheduled when transitioning out of the IDLE_INDICATED state. + * + * Once in the IDLE_INDICATED state, the kernel is free to call the RM to + * perform the GC6 entry sequence then turn off power to the GPU (although it + * may not, if the audio function is being used for example). + * + * There are two paths to exit the IDLE_INDICATED state: + * (a) If os_ref_dynamic_power() is called, in which case it transitions + * directly to the IN_USE state; + * (b) If RmForceGpuNotIdle() is called, in which case it transitions back to + * the IDLE_INSTANT state. + */ +typedef enum +{ + NV_DYNAMIC_POWER_STATE_UNKNOWN = 0, + + NV_DYNAMIC_POWER_STATE_IN_USE, + + NV_DYNAMIC_POWER_STATE_IDLE_INSTANT, + NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED, + NV_DYNAMIC_POWER_STATE_IDLE_INDICATED, +} nv_dynamic_power_state_t; + +typedef struct nv_dynamic_power_s +{ + /* + * mode is read without the mutex -- should be read-only outside of + * rm_init_dynamic_power_management, called during probe only. + */ + nv_dynamic_power_mode_t mode; + /* + * Whether to indicate idle immediately when the refcount reaches 0, or + * only go to the IDLE_INSTANT state, and expect timer callbacks to + * transition through IDLE_SUSTAINED -> IDLE_INDICATED. + */ + NvBool deferred_idle_enabled; + + PORT_ATOMIC nv_dynamic_power_state_t state; + NvS32 refcount; + + /* + * A word on lock ordering. These locks must be taken in the order: + * + * RM API lock > this dynamic_power mutex > RM GPUs lock + * + * Skipping any of those locks is fine (if they aren't required to protect + * whatever state is being accessed or modified), so long as the order is + * not violated. + */ + PORT_MUTEX *mutex; + + /* + * callback handles for deferred dynamic power management. + */ + NvP64 idle_precondition_check_event; + NvP64 indicate_idle_event; + NvBool idle_precondition_check_callback_scheduled; + + /* + * callback handle for kernel initiated gc6 entry/exit. + * these will be protected by the gpu lock. + */ + NvP64 remove_idle_holdoff; + NvBool b_idle_holdoff; + + /* + * flag set if the platform does not support fine grain dynamic power + * management. + */ + NvBool b_fine_not_supported; + + /* + * This flag is used to check if a workitem is queued for + * RmQueueIdleSustainedWorkitem(). + */ + NvBool b_idle_sustained_workitem_queued; + + /* + * Counter to track clients disallowing GCOFF. + */ + NvU32 clients_gcoff_disallow_refcount; + + /* + * Maximum FB allocation size which can be saved in system memory + * while doing GCOFF based dynamic PM. + */ + NvU64 gcoff_max_fb_size; + + /* + * NVreg_DynamicPowerManagement regkey value set by the user + */ + NvU32 dynamic_power_regkey; +} nv_dynamic_power_t; + +typedef struct +{ + OBJGPU *pGpu; + + NvU32 pmc_boot_0; + + nv_vga_t vga; + + NvU32 flags; + NvU32 status; + + nv_i2c_adapter_entry_t i2c_adapters[MAX_I2C_ADAPTERS]; + + void *pVbiosCopy; + NvU32 vbiosSize; + + nv_pm_state_t pm_state; + + nv_reg_entry_t *pRegistry; + + nv_dynamic_power_t dynamic_power; + + /* Flag to check if GPU mobile config is enabled */ + NvBool b_mobile_config_enabled; + + /* Flag to check if S0ix-based power management is enabled. */ + NvBool s0ix_pm_enabled; + + /* Variable to track Dynamic Boost support */ + int db_supported; + + /* + * Maximum FB allocation size which can be saved in system memory + * during system supened with S0ix-based power management. + */ + NvU64 s0ix_gcoff_max_fb_size; + + NvU32 pmc_boot_1; + NvU32 pmc_boot_42; + + /* + * This flag is set if the upstream port has been configured ("D3cold Aux Power Limit" and + * "PERST# Assertion Delay") for GC6. This configuration is needed only for desktops. + */ + NvBool gc6_upstream_port_configured; + + /* This flag is set if _PR3 ACPI method is available to support RTD3. */ + NvBool pr3_acpi_method_present; +} nv_priv_t; + +#define NV_SET_NV_PRIV(nv,p) ((nv)->priv = (p)) +#define NV_GET_NV_PRIV(nv) ((nv) ? (nv)->priv : NULL) + +/* + * Make sure that your stack has taken API Lock before using this macro. + */ +#define NV_GET_NV_PRIV_PGPU(nv) \ + (NV_GET_NV_PRIV(nv) ? ((nv_priv_t *)NV_GET_NV_PRIV(nv))->pGpu : NULL) + +#endif // _NV_PRIV_H_ diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv-reg.h b/userspace/sdks/nv570/nvalloc/unix/include/nv-reg.h new file mode 100644 index 0000000..93999d4 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/nv-reg.h @@ -0,0 +1,1137 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +// +// This file holds Unix-specific NVIDIA driver options +// + +#ifndef _RM_REG_H_ +#define _RM_REG_H_ + +#include "nvtypes.h" +#include "nv-firmware-registry.h" + +/* + * use NV_REG_STRING to stringify a registry key when using that registry key + */ + +#define __NV_REG_STRING(regkey) #regkey +#define NV_REG_STRING(regkey) __NV_REG_STRING(regkey) + +/* + * use NV_DEFINE_REG_ENTRY and NV_DEFINE_PARAMS_TABLE_ENTRY to simplify definition + * of registry keys in the kernel module source code. + */ + +#define __NV_REG_VAR(regkey) NVreg_##regkey + +#if defined(NV_MODULE_PARAMETER) +#define NV_DEFINE_REG_ENTRY(regkey, default_value) \ + static NvU32 __NV_REG_VAR(regkey) = (default_value); \ + NV_MODULE_PARAMETER(__NV_REG_VAR(regkey)) +#define NV_DEFINE_REG_ENTRY_GLOBAL(regkey, default_value) \ + NvU32 __NV_REG_VAR(regkey) = (default_value); \ + NV_MODULE_PARAMETER(__NV_REG_VAR(regkey)) +#else +#define NV_DEFINE_REG_ENTRY(regkey, default_value) \ + static NvU32 __NV_REG_VAR(regkey) = (default_value) +#define NV_DEFINE_REG_ENTRY_GLOBAL(regkey, default_value) \ + NvU32 __NV_REG_VAR(regkey) = (default_value) +#endif + +#if defined(NV_MODULE_STRING_PARAMETER) +#define NV_DEFINE_REG_STRING_ENTRY(regkey, default_value) \ + char *__NV_REG_VAR(regkey) = (default_value); \ + NV_MODULE_STRING_PARAMETER(__NV_REG_VAR(regkey)) +#else +#define NV_DEFINE_REG_STRING_ENTRY(regkey, default_value) \ + char *__NV_REG_VAR(regkey) = (default_value) +#endif + +#define NV_DEFINE_PARAMS_TABLE_ENTRY(regkey) \ + { NV_REG_STRING(regkey), &__NV_REG_VAR(regkey) } + +/* + * Like NV_DEFINE_PARMS_TABLE_ENTRY, but allows a mismatch between the name of + * the regkey and the name of the module parameter. When using this macro, the + * name of the parameter is passed to the extra "parameter" argument, and it is + * this name that must be used in the NV_DEFINE_REG_ENTRY() macro. + */ + +#define NV_DEFINE_PARAMS_TABLE_ENTRY_CUSTOM_NAME(regkey, parameter) \ + { NV_REG_STRING(regkey), &__NV_REG_VAR(parameter)} + +/* + *----------------- registry key definitions-------------------------- + */ + +/* + * Option: ModifyDeviceFiles + * + * Description: + * + * When this option is enabled, the NVIDIA driver will verify the validity + * of the NVIDIA device files in /dev and attempt to dynamically modify + * and/or (re-)create them, if necessary. If you don't wish for the NVIDIA + * driver to touch the device files, you can use this registry key. + * + * This module parameter is only honored by the NVIDIA GPU driver and NVIDIA + * capability driver. Furthermore, the NVIDIA capability driver provides + * modifiable /proc file entry (DeviceFileModify=0/1) to alter the behavior of + * this module parameter per device file. + * + * Possible Values: + * 0 = disable dynamic device file management + * 1 = enable dynamic device file management (default) + */ + +#define __NV_MODIFY_DEVICE_FILES ModifyDeviceFiles +#define NV_REG_MODIFY_DEVICE_FILES NV_REG_STRING(__NV_MODIFY_DEVICE_FILES) + +/* + * Option: DeviceFileUID + * + * Description: + * + * This registry key specifies the UID assigned to the NVIDIA device files + * created and/or modified by the NVIDIA driver when dynamic device file + * management is enabled. + * + * This module parameter is only honored by the NVIDIA GPU driver. + * + * The default UID is 0 ('root'). + */ + +#define __NV_DEVICE_FILE_UID DeviceFileUID +#define NV_REG_DEVICE_FILE_UID NV_REG_STRING(__NV_DEVICE_FILE_UID) + +/* + * Option: DeviceFileGID + * + * Description: + * + * This registry key specifies the GID assigned to the NVIDIA device files + * created and/or modified by the NVIDIA driver when dynamic device file + * management is enabled. + * + * This module parameter is only honored by the NVIDIA GPU driver. + * + * The default GID is 0 ('root'). + */ + +#define __NV_DEVICE_FILE_GID DeviceFileGID +#define NV_REG_DEVICE_FILE_GID NV_REG_STRING(__NV_DEVICE_FILE_GID) + +/* + * Option: DeviceFileMode + * + * Description: + * + * This registry key specifies the device file mode assigned to the NVIDIA + * device files created and/or modified by the NVIDIA driver when dynamic + * device file management is enabled. + * + * This module parameter is only honored by the NVIDIA GPU driver. + * + * The default mode is 0666 (octal, rw-rw-rw-). + */ + +#define __NV_DEVICE_FILE_MODE DeviceFileMode +#define NV_REG_DEVICE_FILE_MODE NV_REG_STRING(__NV_DEVICE_FILE_MODE) + +/* + * Option: ResmanDebugLevel + * + * Default value: ~0 + */ + +#define __NV_RESMAN_DEBUG_LEVEL ResmanDebugLevel +#define NV_REG_RESMAN_DEBUG_LEVEL NV_REG_STRING(__NV_RESMAN_DEBUG_LEVEL) + +/* + * Option: RmLogonRC + * + * Default value: 1 + */ + +#define __NV_RM_LOGON_RC RmLogonRC +#define NV_REG_RM_LOGON_RC NV_REG_STRING(__NV_RM_LOGON_RC) + +/* + * Option: InitializeSystemMemoryAllocations + * + * Description: + * + * The NVIDIA Linux driver normally clears system memory it allocates + * for use with GPUs or within the driver stack. This is to ensure + * that potentially sensitive data is not rendered accessible by + * arbitrary user applications. + * + * Owners of single-user systems or similar trusted configurations may + * choose to disable the aforementioned clears using this option and + * potentially improve performance. + * + * Possible values: + * + * 1 = zero out system memory allocations (default) + * 0 = do not perform memory clears + */ + +#define __NV_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS \ + InitializeSystemMemoryAllocations +#define NV_REG_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS \ + NV_REG_STRING(__NV_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS) + +/* + * Option: RegistryDwords + * + * Description: + * + * This option accepts a semicolon-separated list of key=value pairs. Each + * key name is checked against the table of static options; if a match is + * found, the static option value is overridden, but invalid options remain + * invalid. Pairs that do not match an entry in the static option table + * are passed on to the RM directly. + * + * Format: + * + * NVreg_RegistryDwords=";;..." + */ + +#define __NV_REGISTRY_DWORDS RegistryDwords +#define NV_REG_REGISTRY_DWORDS NV_REG_STRING(__NV_REGISTRY_DWORDS) + +/* + * Option: RegistryDwordsPerDevice + * + * Description: + * + * This option allows to specify registry keys per GPU device. It helps to + * control registry at GPU level of granularity. It accepts a semicolon + * separated list of key=value pairs. The first key value pair MUST be + * "pci=DDDD:BB:DD.F;" where DDDD is Domain, BB is Bus Id, DD is device slot + * number and F is the Function. This PCI BDF is used to identify which GPU to + * assign the registry keys that follows next. + * If a GPU corresponding to the value specified in "pci=DDDD:BB:DD.F;" is NOT + * found, then all the registry keys that follows are skipped, until we find next + * valid pci identified "pci=DDDD:BB:DD.F;". Following are the valid formats for + * the value of the "pci" string: + * 1) bus:slot : Domain and function defaults to 0. + * 2) domain:bus:slot : Function defaults to 0. + * 3) domain:bus:slot.func : Complete PCI dev id string. + * + * For each of the registry keys that follows, key name is checked against the + * table of static options; if a match is found, the static option value is + * overridden, but invalid options remain invalid. Pairs that do not match an + * entry in the static option table are passed on to the RM directly. + * + * Format: + * + * NVreg_RegistryDwordsPerDevice="pci=DDDD:BB:DD.F;;;..; \ + * pci=DDDD:BB:DD.F;;..;" + */ + +#define __NV_REGISTRY_DWORDS_PER_DEVICE RegistryDwordsPerDevice +#define NV_REG_REGISTRY_DWORDS_PER_DEVICE NV_REG_STRING(__NV_REGISTRY_DWORDS_PER_DEVICE) + +#define __NV_RM_MSG RmMsg +#define NV_RM_MSG NV_REG_STRING(__NV_RM_MSG) + +/* + * Option: EnableMSI + * + * Description: + * + * When this option is enabled and the host kernel supports the MSI feature, + * the NVIDIA driver will enable the PCI-E MSI capability of GPUs with the + * support for this feature instead of using PCI-E wired interrupt. + * + * Possible Values: + * + * 0 = disable MSI interrupt + * 1 = enable MSI interrupt (default) + * + */ + +#define __NV_ENABLE_MSI EnableMSI +#define NV_REG_ENABLE_MSI NV_REG_STRING(__NV_ENABLE_MSI) + +/* + * Option: EnablePCIeGen3 + * + * Description: + * + * Due to interoperability problems seen with Kepler PCIe Gen3 capable GPUs + * when configured on SandyBridge E desktop platforms, NVIDIA feels that + * delivering a reliable, high-quality experience is not currently possible in + * PCIe Gen3 mode on all PCIe Gen3 platforms. Therefore, Quadro, Tesla and + * NVS Kepler products operate in PCIe Gen2 mode by default. You may use this + * option to enable PCIe Gen3 support. + * + * This is completely unsupported! + * + * Possible Values: + * + * 0: disable PCIe Gen3 support (default) + * 1: enable PCIe Gen3 support + */ + +#define __NV_ENABLE_PCIE_GEN3 EnablePCIeGen3 +#define NV_REG_ENABLE_PCIE_GEN3 NV_REG_STRING(__NV_ENABLE_PCIE_GEN3) + +/* + * Option: MemoryPoolSize + * + * Description: + * + * When set to a non-zero value, this option specifies the size of the + * memory pool, given as a multiple of 1 GB, created on VMware ESXi to + * satisfy any system memory allocations requested by the NVIDIA kernel + * module. + */ + +#define __NV_MEMORY_POOL_SIZE MemoryPoolSize +#define NV_REG_MEMORY_POOL_SIZE NV_REG_STRING(__NV_MEMORY_POOL_SIZE) + +/* + * Option: KMallocHeapMaxSize + * + * Description: + * + * When set to a non-zero value, this option specifies the maximum size of the + * heap memory space reserved for kmalloc operations. Given as a + * multiple of 1 MB created on VMware ESXi to satisfy any system memory + * allocations requested by the NVIDIA kernel module. + */ + +#define __NV_KMALLOC_HEAP_MAX_SIZE KMallocHeapMaxSize +#define NV_KMALLOC_HEAP_MAX_SIZE NV_REG_STRING(__NV_KMALLOC_HEAP_MAX_SIZE) + +/* + * Option: VMallocHeapMaxSize + * + * Description: + * + * When set to a non-zero value, this option specifies the maximum size of the + * heap memory space reserved for vmalloc operations. Given as a + * multiple of 1 MB created on VMware ESXi to satisfy any system memory + * allocations requested by the NVIDIA kernel module. + */ + +#define __NV_VMALLOC_HEAP_MAX_SIZE VMallocHeapMaxSize +#define NV_VMALLOC_HEAP_MAX_SIZE NV_REG_STRING(__NV_VMALLOC_HEAP_MAX_SIZE) + +/* + * Option: IgnoreMMIOCheck + * + * Description: + * + * When this option is enabled, the NVIDIA kernel module will ignore + * MMIO limit check during device probe on VMWare ESXi kernel. This is + * typically necessary when VMware ESXi MMIO limit differs between any + * base version and its updates. Customer using updates can set regkey + * to avoid probe failure. + */ + +#define __NV_IGNORE_MMIO_CHECK IgnoreMMIOCheck +#define NV_REG_IGNORE_MMIO_CHECK NV_REG_STRING(__NV_IGNORE_MMIO_CHECK) + +/* + * Option: pci + * + * Description: + * + * On Unix platforms, per GPU based registry key can be specified as: + * NVreg_RegistryDwordsPerDevice="pci=DDDD:BB:DD.F,". + * where DDDD:BB:DD.F refers to Domain:Bus:Device.Function. + * We need this key "pci" to identify what follows next is a PCI BDF identifier, + * for which the registry keys are to be applied. + * + * This define is not used on non-UNIX platforms. + * + * Possible Formats for value: + * + * 1) bus:slot : Domain and function defaults to 0. + * 2) domain:bus:slot : Function defaults to 0. + * 3) domain:bus:slot.func : Complete PCI BDF identifier string. + */ +#define __NV_PCI_DEVICE_BDF pci +#define NV_REG_PCI_DEVICE_BDF NV_REG_STRING(__NV_PCI_DEVICE_BDF) + +/* + * Option: EnableStreamMemOPs + * + * Description: + * + * When this option is enabled, the CUDA driver will enable support for + * CUDA Stream Memory Operations in user-mode applications, which are so + * far required to be disabled by default due to limited support in + * devtools. + * + * Note: this is treated as a hint. MemOPs may still be left disabled by CUDA + * driver for other reasons. + * + * Possible Values: + * + * 0 = disable feature (default) + * 1 = enable feature + */ +#define __NV_ENABLE_STREAM_MEMOPS EnableStreamMemOPs +#define NV_REG_ENABLE_STREAM_MEMOPS NV_REG_STRING(__NV_ENABLE_STREAM_MEMOPS) + +/* + * Option: EnableUserNUMAManagement + * + * Description: + * + * When this option is enabled, the NVIDIA kernel module will require the + * user-mode NVIDIA Persistence daemon to manage the onlining and offlining + * of its NUMA device memory. + * + * This option has no effect on platforms that do not support onlining + * device memory to a NUMA node (this feature is only supported on certain + * POWER9 systems). + * + * Possible Values: + * + * 0: disable user-mode NUMA management + * 1: enable user-mode NUMA management (default) + */ +#define __NV_ENABLE_USER_NUMA_MANAGEMENT EnableUserNUMAManagement +#define NV_REG_ENABLE_USER_NUMA_MANAGEMENT NV_REG_STRING(__NV_ENABLE_USER_NUMA_MANAGEMENT) + +/* + * Option: CoherentGPUMemoryMode + * + * Description: + * + * This option can be set to control how GPU Memory is accessed through + * the coherent link. + * + * This option has no effect on platforms that do not support onlining + * device memory to a NUMA node. + * + * Possible string values: + * + * "driver" : disable onlining coherent memory to the OS as a NUMA node. The driver + * will manage it in this case + * "numa" (or unset) : enable onlining coherent memory to the OS as a NUMA node (default) + */ +#define __NV_COHERENT_GPU_MEMORY_MODE CoherentGPUMemoryMode +#define NV_REG_COHERENT_GPU_MEMORY_MODE NV_REG_STRING(__NV_COHERENT_GPU_MEMORY_MODE) + +/* + * Option: GpuBlacklist + * + * Description: + * + * This option accepts a list of blacklisted GPUs, separated by commas, that + * cannot be attached or used. Each blacklisted GPU is identified by a UUID in + * the ASCII format with leading "GPU-". An exact match is required; no partial + * UUIDs. This regkey is deprecated and will be removed in the future. Use + * NV_REG_EXCLUDED_GPUS instead. + */ +#define __NV_GPU_BLACKLIST GpuBlacklist +#define NV_REG_GPU_BLACKLIST NV_REG_STRING(__NV_GPU_BLACKLIST) + +/* + * Option: ExcludedGpus + * + * Description: + * + * This option accepts a list of excluded GPUs, separated by commas, that + * cannot be attached or used. Each excluded GPU is identified by a UUID in + * the ASCII format with leading "GPU-". An exact match is required; no partial + * UUIDs. + */ +#define __NV_EXCLUDED_GPUS ExcludedGpus +#define NV_REG_EXCLUDED_GPUS NV_REG_STRING(__NV_EXCLUDED_GPUS) + +/* + * Option: NVreg_ExcludeAllGpus + * + * Description: + * + * This option allows the user to exclude all GPUs. If used in conjunction with + * UUID based GPU exclusion, all GPUs will be excluded + * + * Possible values: + * 1 - Excludes all GPUs from being attached or used + * 0 - No effect (default) + */ + #define __NV_EXCLUDE_ALL_GPUS ExcludeAllGpus + #define NV_EXCLUDE_ALL_GPUS NV_REG_STRING(__NV_EXCLUDE_ALL_GPUS) + #define NV_EXCLUDE_ALL_GPUS_DEFAULT 0 + +/* + * Option: NvLinkDisable + * + * Description: + * + * When this option is enabled, the NVIDIA kernel module will not attempt to + * initialize or train NVLink connections for any GPUs. System reboot is required + * for changes to take affect. + * + * This option has no effect if no GPUs support NVLink. + * + * Possible Values: + * + * 0: Do not disable NVLink (default) + * 1: Disable NVLink + */ +#define __NV_NVLINK_DISABLE NvLinkDisable +#define NV_REG_NVLINK_DISABLE NV_REG_STRING(__NV_NVLINK_DISABLE) + +/* + * Option: RestrictProfilingToAdminUsers + * + * Description: + * + * When this option is enabled, the NVIDIA kernel module will prevent users + * without administrative access (i.e., the CAP_SYS_ADMIN capability) from + * using GPU performance counters. + * + * Possible Values: + * + * 0: Do not restrict GPU counters (default) + * 1: Restrict GPU counters to system administrators only + */ + +#define __NV_RM_PROFILING_ADMIN_ONLY RmProfilingAdminOnly +#define __NV_RM_PROFILING_ADMIN_ONLY_PARAMETER RestrictProfilingToAdminUsers +#define NV_REG_RM_PROFILING_ADMIN_ONLY NV_REG_STRING(__NV_RM_PROFILING_ADMIN_ONLY) + + +/* +* Option: EnableDebuggerInterface +* +* Description: +* +* When this option is enabled, the NVIDIA kernel module will allow non-administrator users to +* create a non-preemptable debugger session for non-CILP contexts. +* +* Possible Values: +* +* 0: Do not allow non-administrator users to create non-preemptable debugger sessions (default) +* 1: Allow non-administrator users to create non-preemptable debugger sessions +*/ +#define __NV_ENABLE_NON_PREEMTABLE_DEBUGGER_SESSION EnableDebuggerInterface +#define NV_REG_ENABLE_NON_PREEMTABLE_DEBUGGER_SESSION NV_REG_STRING(__NV_ENABLE_NON_PREEMTABLE_DEBUGGER_SESSION) + +/* + * Option: TemporaryFilePath + * + * Description: + * + * When specified, this option changes the location in which the + * NVIDIA kernel module will create unnamed temporary files (e.g. to + * save the contents of video memory in). The indicated file must + * be a directory. By default, temporary files are created in /tmp. + */ +#define __NV_TEMPORARY_FILE_PATH TemporaryFilePath +#define NV_REG_TEMPORARY_FILE_PATH NV_REG_STRING(__NV_TEMPORARY_FILE_PATH) + +/* + * Option: PreserveVideoMemoryAllocations + * + * If enabled, this option prompts the NVIDIA kernel module to save and + * restore all video memory allocations across system power management + * cycles, i.e. suspend/resume and hibernate/restore. Otherwise, + * only select allocations are preserved. + * + * Possible Values: + * + * 0: Preserve only select video memory allocations + * 1: Preserve all video memory allocations + * 2: Automatically enable video memory allocations when + * NVreg_UseKernelSuspendNotifiers is enabled (default) + */ +#define __NV_PRESERVE_VIDEO_MEMORY_ALLOCATIONS PreserveVideoMemoryAllocations +#define NV_REG_PRESERVE_VIDEO_MEMORY_ALLOCATIONS \ + NV_REG_STRING(__NV_PRESERVE_VIDEO_MEMORY_ALLOCATIONS) + +#define NV_REG_PRESERVE_VIDEO_MEMORY_ALLOCATIONS_DISABLED 0 +#define NV_REG_PRESERVE_VIDEO_MEMORY_ALLOCATIONS_ENABLED 1 +#define NV_REG_PRESERVE_VIDEO_MEMORY_ALLOCATIONS_AUTO 2 + +/* + * Option: UseKernelSuspendNotifiers + * + * If enabled, this option prompts the NVIDIA kernel module to register a + * notifier that saves and restores all video memory allocations across system + * power management cycles if PreserveVideoMemoryAllocations is enabled. + * + * Possible Values: + * + * 0: Suspend notifiers are not used (default) + * 1: Suspend notifiers are used when available + */ + +#define __NV_USE_KERNEL_SUSPEND_NOTIFIERS UseKernelSuspendNotifiers +#define NV_REG_USE_KERNEL_SUSPEND_NOTIFIERS \ + NV_REG_STRING(__NV_USE_KERNEL_SUSPEND_NOTIFIERS) + +/* + * Option: EnableS0ixPowerManagement + * + * When this option is enabled, the NVIDIA driver will use S0ix-based + * power management for system suspend/resume, if both the platform and + * the GPU support S0ix. + * + * During system suspend, if S0ix is enabled and + * video memory usage is above the threshold configured by + * 'S0ixPowerManagementVideoMemoryThreshold', video memory will be kept + * in self-refresh mode while the rest of the GPU is powered down. + * + * Otherwise, the driver will copy video memory contents to system memory + * and power off the video memory along with the GPU. + * + * Possible Values: + * + * 0: Disable S0ix based power management (default) + * 1: Enable S0ix based power management + */ + +#define __NV_ENABLE_S0IX_POWER_MANAGEMENT EnableS0ixPowerManagement +#define NV_REG_ENABLE_S0IX_POWER_MANAGEMENT \ + NV_REG_STRING(__NV_ENABLE_S0IX_POWER_MANAGEMENT) + +/* + * Option: S0ixPowerManagementVideoMemoryThreshold + * + * This option controls the threshold that the NVIDIA driver will use during + * S0ix-based system power management. + * + * When S0ix is enabled and the system is suspended, the driver will + * compare the amount of video memory in use with this threshold, + * to decide whether to keep video memory in self-refresh or copy video + * memory content to system memory. + * + * See the 'EnableS0ixPowerManagement' option. + * + * Values are expressed in Megabytes (1048576 bytes). + * + * Default value for this option is 256MB. + * + */ +#define __NV_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD \ + S0ixPowerManagementVideoMemoryThreshold +#define NV_REG_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD \ + NV_REG_STRING(__NV_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD) + +/* + * Option: DynamicPowerManagement + * + * This option controls how aggressively the NVIDIA kernel module will manage + * GPU power through kernel interfaces. + * + * Possible Values: + * + * 0: Never allow the GPU to be powered down (default). + * 1: Power down the GPU when it is not initialized. + * 2: Power down the GPU after it has been inactive for some time. + * 3: (Default) Power down the GPU after a period of inactivity (i.e., + * mode 2) on Ampere or later notebooks. Otherwise, do not power down + * the GPU. + */ +#define __NV_DYNAMIC_POWER_MANAGEMENT DynamicPowerManagement +#define NV_REG_DYNAMIC_POWER_MANAGEMENT \ + NV_REG_STRING(__NV_DYNAMIC_POWER_MANAGEMENT) + +#define NV_REG_DYNAMIC_POWER_MANAGEMENT_NEVER 0 +#define NV_REG_DYNAMIC_POWER_MANAGEMENT_COARSE 1 +#define NV_REG_DYNAMIC_POWER_MANAGEMENT_FINE 2 +#define NV_REG_DYNAMIC_POWER_MANAGEMENT_DEFAULT 3 + +/* + * Option: DynamicPowerManagementVideoMemoryThreshold + * + * This option controls the threshold that the NVIDIA driver will use + * when selecting the dynamic power management scheme. + * + * When the driver detects that the GPU is idle, it will compare the amount + * of video memory in use with this threshold. + * + * If the current video memory usage is less than the threshold, the + * driver may preserve video memory contents in system memory and power off + * the video memory along with the GPU itself, if supported. Otherwise, + * the video memory will be kept in self-refresh mode while powering down + * the rest of the GPU, if supported. + * + * Values are expressed in Megabytes (1048576 bytes). + * + * If the requested value is greater than 200MB (the default), then it + * will be capped to 200MB. + */ +#define __NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD \ + DynamicPowerManagementVideoMemoryThreshold +#define NV_REG_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD \ + NV_REG_STRING(__NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD) + +/* + * Option: TegraGpuPgMask + * + * This option controls the TPC/GPC/FBP power-gating mask for Tegra iGPU. + * + */ +#define __NV_TEGRA_GPU_PG_MASK TegraGpuPgMask +#define NV_REG_TEGRA_GPU_PG_MASK \ + NV_REG_STRING(__NV_TEGRA_GPU_PG_MASK) + +/* + * Option: RegisterPCIDriver + * + * Description: + * + * When this option is enabled, the NVIDIA driver will register with + * PCI subsystem. + * + * Possible values: + * + * 1 - register as PCI driver (default) + * 0 - do not register as PCI driver + */ + +#define __NV_REGISTER_PCI_DRIVER RegisterPCIDriver +#define NV_REG_REGISTER_PCI_DRIVER NV_REG_STRING(__NV_REGISTER_PCI_DRIVER) + +/* + * Option: RegisterPlatformDeviceDriver + * + * Description: + * + * When this option is enabled, the NVIDIA driver will register with + * platform subsystem. + * + * Possible values: + * + * 1 - register as platform driver (default) + * 0 - do not register as platform driver + */ + +#define __NV_REGISTER_PLATFORM_DEVICE_DRIVER RegisterPlatformDeviceDriver +#define NV_REG_REGISTER_PLATFORM_DEVICE_DRIVER NV_REG_STRING(__NV_REGISTER_PLATFORM_DEVICE_DRIVER) + +/* + * Option: EnablePCIERelaxedOrderingMode + * + * Description: + * + * When this option is enabled, the registry key RmSetPCIERelaxedOrdering will + * be set to NV_REG_STR_RM_SET_PCIE_TLP_RELAXED_ORDERING_FORCE_ENABLE, causing + * every device to set the relaxed ordering bit to 1 in all outbound MWr + * transaction-layer packets. This is equivalent to setting the regkey to + * FORCE_ENABLE as a non-per-device registry key. + * + * Possible values: + * 0 - Do not enable PCIe TLP relaxed ordering bit-setting (default) + * 1 - Enable PCIe TLP relaxed ordering bit-setting + */ +#define __NV_ENABLE_PCIE_RELAXED_ORDERING_MODE EnablePCIERelaxedOrderingMode +#define NV_REG_ENABLE_PCIE_RELAXED_ORDERING_MODE \ + NV_REG_STRING(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE) + +/* + * Option: EnableResizableBar + * + * Description: + * + * When this option is enabled, the NVIDIA driver will attempt to resize + * BAR1 to match framebuffer size, or the next largest available size on + * supported machines. This is currently only implemented for Linux. + * + * Possible values: + * 0 - Do not enable PCI BAR resizing + * 1 - Enable PCI BAR resizing + */ +#define __NV_ENABLE_RESIZABLE_BAR EnableResizableBar +#define NV_REG_ENABLE_RESIZABLE_BAR NV_REG_STRING(__NV_ENABLE_RESIZABLE_BAR) + +/* + * Option: EnableGpuFirmware + * + * Description: + * + * When this option is enabled, the NVIDIA driver will enable use of GPU + * firmware. + * + * If this key is set globally to the system, the driver may still attempt + * to apply some policies to maintain uniform firmware modes across all + * GPUS. This may result in the driver failing initialization on some GPUs + * to maintain such a policy. + * + * If this key is set using NVreg_RegistryDwordsPerDevice, then the driver + * will attempt to honor whatever configuration is specified without applying + * additional policies. This may also result in failed GPU initialzations if + * the configuration is not possible (for example if the firmware is missing + * from the filesystem, or the GPU is not capable). + * + * NOTE: More details for this regkey can be found in nv-firmware-registry.h + */ +#define __NV_ENABLE_GPU_FIRMWARE EnableGpuFirmware +#define NV_REG_ENABLE_GPU_FIRMWARE NV_REG_STRING(__NV_ENABLE_GPU_FIRMWARE) + +/* + * Option: EnableGpuFirmwareLogs + * + * When this option is enabled, the NVIDIA driver will send GPU firmware logs + * to the system log, when possible. + * + * NOTE: More details for this regkey can be found in nv-firmware-registry.h + */ +#define __NV_ENABLE_GPU_FIRMWARE_LOGS EnableGpuFirmwareLogs +#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS NV_REG_STRING(__NV_ENABLE_GPU_FIRMWARE_LOGS) + +/* + * Option: EnableDbgBreakpoint + * + * When this option is set to a non-zero value, and the kernel is configured + * appropriately, assertions within resman will trigger a CPU breakpoint (e.g., + * INT3 on x86_64), assumed to be caught by an attached debugger. + * + * When this option is set to the value zero (the default), assertions within + * resman will print to the system log, but no CPU breakpoint will be triggered. + */ +#define __NV_ENABLE_DBG_BREAKPOINT EnableDbgBreakpoint + + +/* + * Option: OpenRmEnableUnsupportedGpus + * + * This option to require opt in for use of Open RM on non-Data Center + * GPUs is deprecated and no longer required. The kernel module parameter + * is left here, though ignored, for backwards compatibility. + */ +#define __NV_OPENRM_ENABLE_UNSUPPORTED_GPUS OpenRmEnableUnsupportedGpus + +/* + * Option: NVreg_DmaRemapPeerMmio + * + * Description: + * + * When this option is enabled, the NVIDIA driver will use device driver + * APIs provided by the Linux kernel for DMA-remapping part of a device's + * MMIO region to another device, creating e.g., IOMMU mappings as necessary. + * When this option is disabled, the NVIDIA driver will instead only apply a + * fixed offset, which may be zero, to CPU physical addresses to produce the + * DMA address for the peer's MMIO region, and no IOMMU mappings will be + * created. + * + * This option only affects peer MMIO DMA mappings, and not system memory + * mappings. + * + * Possible Values: + * 0 = disable dynamic DMA remapping of peer MMIO regions + * 1 = enable dynamic DMA remapping of peer MMIO regions (default) + */ +#define __NV_DMA_REMAP_PEER_MMIO DmaRemapPeerMmio +#define NV_DMA_REMAP_PEER_MMIO NV_REG_STRING(__NV_DMA_REMAP_PEER_MMIO) +#define NV_DMA_REMAP_PEER_MMIO_DISABLE 0x00000000 +#define NV_DMA_REMAP_PEER_MMIO_ENABLE 0x00000001 + +/* + * Option: NVreg_RmNvlinkBandwidthLinkCount + * + * Description: + * + * This option allows user to reduce the GPU nvlink bandwidth to save power. + * + * This option is only for Blackwell+ GPU with NVLINK version 5.0. + */ +#define __NV_RM_NVLINK_BW_LINK_COUNT RmNvlinkBandwidthLinkCount +#define NV_RM_NVLINK_BW_LINK_COUNT NV_REG_STRING(__NV_RM_NVLINK_BW_LINK_COUNT) + +/* + * Option: NVreg_RmNvlinkBandwidth + * + * Description: + * + * This option allows user to reduce the NVLINK P2P bandwidth to save power. + * The option is in the string format. + * + * Possible string values: + * OFF: 0% bandwidth + * MIN: 15%-25% bandwidth depending on the system's NVLink topology + * HALF: 50% bandwidth + * 3QUARTER: 75% bandwidth + * FULL: 100% bandwidth (default) + * + * This option is only for Hopper+ GPU with NVLINK version 4.0. + */ +#define __NV_RM_NVLINK_BW RmNvlinkBandwidth +#define NV_RM_NVLINK_BW NV_REG_STRING(__NV_RM_NVLINK_BW) + +/* + * Option: NVreg_EnableNonblockingOpen + * + * Description: + * + * When this option is enabled, the NVIDIA driver will try to perform any + * required device initialization in the background when /dev/nvidiaN devices + * are opened with the flag O_NONBLOCK. + * + * Possible Values: + * 0 = O_NONBLOCK flag when opening devices is ignored + * 1 = O_NONBLOCK flag when opening devices results in background device + * initialization (default) + */ +#define __NV_ENABLE_NONBLOCKING_OPEN EnableNonblockingOpen +#define NV_ENABLE_NONBLOCKING_OPEN NV_REG_STRING(__NV_ENABLE_NONBLOCKING_OPEN) + +/* + * Option: NVreg_ImexChannelCount + * + * Description: + * + * This option allows users to specify the number of IMEX (import/export) + * channels. Within an IMEX domain, the channels allow sharing memory + * securely in a multi-user environment using the CUDA driver's fabric handle + * based APIs. + * + * An IMEX domain is either an OS instance or a group of securely + * connected OS instances using the NVIDIA IMEX daemon. The option must + * be set to the same value on each OS instance within the IMEX domain. + * + * An IMEX channel is a logical entity that is represented by a /dev node. + * The IMEX channels are global resources within the IMEX domain. When + * exporter and importer CUDA processes have been granted access to the + * same IMEX channel, they can securely share memory. + * + * Note that the NVIDIA driver will not attempt to create the /dev nodes. Thus, + * the related CUDA APIs will fail with an insufficient permission error until + * the /dev nodes are set up. The creation of these /dev nodes, + * /dev/nvidia-caps-imex-channels/channelN, must be handled by the + * administrator, where N is the minor number. The major number can be + * queried from /proc/devices. + * + * nvidia-modprobe CLI support is available to set up the /dev nodes. + * NVreg_ModifyDeviceFiles, NVreg_DeviceFileGID, NVreg_DeviceFileUID + * and NVreg_DeviceFileMode will be honored by nvidia-modprobe. + * + * Also, refer to the NVreg_CreateImexChannel0 option. + * + * Possible values: + * 0 - Disable IMEX using CUDA driver's fabric handles. + * N - N IMEX channels will be enabled in the driver to facilitate N + * concurrent users. Default value is 2048 channels, and the current + * maximum value is 20-bit, same as Linux dev_t's minor number limit. + */ +#define __NV_IMEX_CHANNEL_COUNT ImexChannelCount +#define NV_REG_IMEX_CHANNEL_COUNT NV_REG_STRING(__NV_IMEX_CHANNEL_COUNT) + +/* + * Option: NVreg_CreateImexChannel0 + * + * Description: + * + * This option allows users to specify whether the NVIDIA driver must create + * the IMEX channel 0 by default. The channel will be created automatically + * when the NVIDIA open GPU kernel module is loaded. + * + * Note that users are advised to enable this option only in trusted + * environments where it is acceptable for applications to share the same + * IMEX channel. + * + * For more details on IMEX channels, refer to the NVreg_ImexChannelCount + * option. + * + * Possible values: + * 0 - Do not create IMEX channel 0 (default). + * 1 - Create IMEX channel 0. + */ +#define __NV_CREATE_IMEX_CHANNEL_0 CreateImexChannel0 +#define NV_CREATE_IMEX_CHANNEL_0 NV_REG_STRING(__CREATE_IMEX_CHANNEL_0) + +/* + * Option: NVreg_EnableSystemMemoryPools + * + * Description: + * + * This option controls system memory page pools creation for different page sizes + * Pool for pageSize is enabled by setting bit (pageSize >> NV_ENABLE_SYSTEM_MEMORY_POOLS_SHIFT) + * The pools keep memory cached once freed to speed-up reallocation + * Pools are shared by all adapters + * + * This feature is only supported by OpenRM driver + * + * By default 4K, 64K, 2M page size pools are enabled + */ +#define __NV_ENABLE_SYSTEM_MEMORY_POOLS EnableSystemMemoryPools +#define NV_ENABLE_SYSTEM_MEMORY_POOLS NV_REG_STRING(__NV_ENABLE_SYSTEM_MEMORY_POOLS) +#define NV_ENABLE_SYSTEM_MEMORY_POOLS_DEFAULT 0x00000211 +#define NV_ENABLE_SYSTEM_MEMORY_POOLS_SHIFT 12 + +/* + * Option: NVreg_OsEnableCxlSupport + * + * Description: + * + * When this option is enabled, the driver will enable support for + * CXL at the OS layer. + * + * This option has no effect on platforms that do not support CXL or on + * GPUs without CXL capability. + * + * Possible Values: + * + * 0: disable CXL support + * 1: enable CXL support (default) + */ +#define __NV_OS_ENABLE_CXL_SUPPORT OsEnableCxlSupport +#define NV_REG_OS_ENABLE_CXL_SUPPORT NV_REG_STRING(__NV_OS_ENABLE_CXL_SUPPORT) + +/* + * Option: NVreg_GpuInitOnProbe + * + * Description: + * + * This option allows the user to control initialization of the GPU at PCI probe time + * + * Possible values: + * 0 - Disable initializing the GPUs on PCI probe + * 1 - Initialize GPUs on PCI probe + */ + #define __NV_GPU_INIT_ON_PROBE GpuInitOnProbe + #define NV_GPU_INIT_ON_PROBE NV_REG_STRING(__NV_GPU_INIT_ON_PROBE) + #define NV_GPU_INIT_ON_PROBE_DEFAULT 0 + +#if defined(NV_DEFINE_REGISTRY_KEY_TABLE) + +/* + *---------registry key parameter declarations-------------- + */ + +NV_DEFINE_REG_ENTRY(__NV_RESMAN_DEBUG_LEVEL, ~0); +NV_DEFINE_REG_ENTRY(__NV_RM_LOGON_RC, 1); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_MODIFY_DEVICE_FILES, 1); +NV_DEFINE_REG_ENTRY(__NV_DEVICE_FILE_UID, 0); +NV_DEFINE_REG_ENTRY(__NV_DEVICE_FILE_GID, 0); +NV_DEFINE_REG_ENTRY(__NV_DEVICE_FILE_MODE, 0666); +NV_DEFINE_REG_ENTRY(__NV_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS, 1); +NV_DEFINE_REG_ENTRY(__NV_ENABLE_PCIE_GEN3, 0); +NV_DEFINE_REG_ENTRY(__NV_ENABLE_MSI, 1); +NV_DEFINE_REG_ENTRY(__NV_ENABLE_STREAM_MEMOPS, 0); +NV_DEFINE_REG_ENTRY(__NV_RM_PROFILING_ADMIN_ONLY_PARAMETER, 1); +NV_DEFINE_REG_ENTRY(__NV_PRESERVE_VIDEO_MEMORY_ALLOCATIONS, + NV_REG_PRESERVE_VIDEO_MEMORY_ALLOCATIONS_AUTO); +NV_DEFINE_REG_ENTRY(__NV_ENABLE_S0IX_POWER_MANAGEMENT, 0); +NV_DEFINE_REG_ENTRY(__NV_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD, 256); +NV_DEFINE_REG_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT, 3); +NV_DEFINE_REG_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD, 200); +NV_DEFINE_REG_ENTRY(__NV_ENABLE_GPU_FIRMWARE, NV_REG_ENABLE_GPU_FIRMWARE_DEFAULT_VALUE); +NV_DEFINE_REG_ENTRY(__NV_ENABLE_GPU_FIRMWARE_LOGS, NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG); +NV_DEFINE_REG_ENTRY(__NV_OPENRM_ENABLE_UNSUPPORTED_GPUS, 1); + +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_USER_NUMA_MANAGEMENT, 1); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_MEMORY_POOL_SIZE, 0); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_KMALLOC_HEAP_MAX_SIZE, 0); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_VMALLOC_HEAP_MAX_SIZE, 0); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_IGNORE_MMIO_CHECK, 0); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_NVLINK_DISABLE, 0); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE, 0); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_REGISTER_PCI_DRIVER, 1); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_REGISTER_PLATFORM_DEVICE_DRIVER, 1); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_RESIZABLE_BAR, 0); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_DBG_BREAKPOINT, 0); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_TEGRA_GPU_PG_MASK, 0); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_NONBLOCKING_OPEN, 1); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_EXCLUDE_ALL_GPUS, NV_EXCLUDE_ALL_GPUS_DEFAULT); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_GPU_INIT_ON_PROBE, NV_GPU_INIT_ON_PROBE_DEFAULT); + +NV_DEFINE_REG_STRING_ENTRY(__NV_COHERENT_GPU_MEMORY_MODE, NULL); +NV_DEFINE_REG_STRING_ENTRY(__NV_REGISTRY_DWORDS, NULL); +NV_DEFINE_REG_STRING_ENTRY(__NV_REGISTRY_DWORDS_PER_DEVICE, NULL); +NV_DEFINE_REG_STRING_ENTRY(__NV_RM_MSG, NULL); +NV_DEFINE_REG_STRING_ENTRY(__NV_GPU_BLACKLIST, NULL); +NV_DEFINE_REG_STRING_ENTRY(__NV_TEMPORARY_FILE_PATH, NULL); +NV_DEFINE_REG_STRING_ENTRY(__NV_EXCLUDED_GPUS, NULL); +NV_DEFINE_REG_ENTRY(__NV_DMA_REMAP_PEER_MMIO, NV_DMA_REMAP_PEER_MMIO_ENABLE); +NV_DEFINE_REG_STRING_ENTRY(__NV_RM_NVLINK_BW, NULL); +NV_DEFINE_REG_ENTRY(__NV_RM_NVLINK_BW_LINK_COUNT, 0); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_IMEX_CHANNEL_COUNT, 2048); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_CREATE_IMEX_CHANNEL_0, 0); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_SYSTEM_MEMORY_POOLS, NV_ENABLE_SYSTEM_MEMORY_POOLS_DEFAULT); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_OS_ENABLE_CXL_SUPPORT, 1); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_USE_KERNEL_SUSPEND_NOTIFIERS, 0); +NV_DEFINE_REG_ENTRY(__NV_ENABLE_NON_PREEMTABLE_DEBUGGER_SESSION, 0); +/* + *----------------registry database definition---------------------- + */ + +/* + * You can enable any of the registry options disabled by default by + * editing their respective entries in the table below. The last field + * determines if the option is considered valid - in order for the + * changes to take effect, you need to recompile and reload the NVIDIA + * kernel module. + */ +nv_parm_t nv_parms[] = { + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_RESMAN_DEBUG_LEVEL), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_RM_LOGON_RC), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_MODIFY_DEVICE_FILES), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DEVICE_FILE_UID), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DEVICE_FILE_GID), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DEVICE_FILE_MODE), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_MSI), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_PCIE_GEN3), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_MEMORY_POOL_SIZE), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_KMALLOC_HEAP_MAX_SIZE), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_VMALLOC_HEAP_MAX_SIZE), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_IGNORE_MMIO_CHECK), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_STREAM_MEMOPS), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_USER_NUMA_MANAGEMENT), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_NVLINK_DISABLE), + NV_DEFINE_PARAMS_TABLE_ENTRY_CUSTOM_NAME(__NV_RM_PROFILING_ADMIN_ONLY, + __NV_RM_PROFILING_ADMIN_ONLY_PARAMETER), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_PRESERVE_VIDEO_MEMORY_ALLOCATIONS), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_USE_KERNEL_SUSPEND_NOTIFIERS), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_S0IX_POWER_MANAGEMENT), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_TEGRA_GPU_PG_MASK), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_REGISTER_PCI_DRIVER), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_RESIZABLE_BAR), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_GPU_FIRMWARE), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_GPU_FIRMWARE_LOGS), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_RM_NVLINK_BW_LINK_COUNT), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_DBG_BREAKPOINT), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_OPENRM_ENABLE_UNSUPPORTED_GPUS), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DMA_REMAP_PEER_MMIO), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_IMEX_CHANNEL_COUNT), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_CREATE_IMEX_CHANNEL_0), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_SYSTEM_MEMORY_POOLS), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_OS_ENABLE_CXL_SUPPORT), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_NON_PREEMTABLE_DEBUGGER_SESSION), + {NULL, NULL} +}; + +#elif defined(NVRM) + +extern nv_parm_t nv_parms[]; + +#endif /* NV_DEFINE_REGISTRY_KEY_TABLE */ + +#endif /* _RM_REG_H_ */ diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv-unix-nvos-params-wrappers.h b/userspace/sdks/nv570/nvalloc/unix/include/nv-unix-nvos-params-wrappers.h new file mode 100644 index 0000000..02b0156 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/nv-unix-nvos-params-wrappers.h @@ -0,0 +1,49 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NV_UNIX_NVOS_PARAMS_WRAPPERS_H_ +#define _NV_UNIX_NVOS_PARAMS_WRAPPERS_H_ + +#include + +/* + * This is a wrapper for NVOS02_PARAMETERS with file descriptor + */ + +typedef struct +{ + NVOS02_PARAMETERS params; + int fd; +} nv_ioctl_nvos02_parameters_with_fd; + +/* + * This is a wrapper for NVOS33_PARAMETERS with file descriptor + */ +typedef struct +{ + NVOS33_PARAMETERS params; + int fd; +} nv_ioctl_nvos33_parameters_with_fd; + +#endif // _NV_UNIX_NVOS_PARAMS_WRAPPERS_H_ + diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv.h b/userspace/sdks/nv570/nvalloc/unix/include/nv.h new file mode 100644 index 0000000..d8db166 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/nv.h @@ -0,0 +1,1367 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _NV_H_ +#define _NV_H_ + + + +#include + +#if defined(NV_KERNEL_INTERFACE_LAYER) && defined(__FreeBSD__) + #include // NULL +#elif defined(NV_KERNEL_INTERFACE_LAYER) && defined(NV_LINUX) + #include // NULL +#else + #include // NULL +#endif + +#include +#include "nv_stdarg.h" +#include +#include +#include +#include +#include +#include + +#if !defined(NV_KERNEL_INTERFACE_LAYER) && defined(NVRM) && !defined(NV_DRM_FREEBSD_LKPI) +#include +#else +#define PORT_ATOMIC +#endif + +extern nv_cap_t *nvidia_caps_root; + +extern const NvBool nv_is_rm_firmware_supported_os; + +#include +#include + +#include + +#define GPU_UUID_LEN (16) + +/* + * Buffer size for an ASCII UUID: We need 2 digits per byte, plus space + * for "GPU", 5 dashes, and '\0' termination: + */ +#define GPU_UUID_ASCII_LEN (GPU_UUID_LEN * 2 + 9) + +/* + * #define an absolute maximum used as a sanity check for the + * NV_ESC_IOCTL_XFER_CMD ioctl() size argument. + */ +#define NV_ABSOLUTE_MAX_IOCTL_SIZE 16384 + +/* + * Solaris provides no more than 8 bits for the argument size in + * the ioctl() command encoding; make sure we don't exceed this + * limit. + */ +#define __NV_IOWR_ASSERT(type) ((sizeof(type) <= NV_PLATFORM_MAX_IOCTL_SIZE) ? 1 : -1) +#define __NV_IOWR(nr, type) ({ \ + typedef char __NV_IOWR_TYPE_SIZE_ASSERT[__NV_IOWR_ASSERT(type)]; \ + _IOWR(NV_IOCTL_MAGIC, (nr), type); \ +}) + +#define NV_PCI_DEV_FMT "%04x:%02x:%02x.%x" +#define NV_PCI_DEV_FMT_ARGS(nv) (nv)->pci_info.domain, (nv)->pci_info.bus, \ + (nv)->pci_info.slot, (nv)->pci_info.function + +#define NV_RM_DEVICE_INTR_ADDRESS 0x100 + +#define NV_TEGRA_PCI_IGPU_PG_MASK_DEFAULT 0xFFFFFFFF + +/* + * Clock domain identifier, which is used for fetching the engine + * load backed by the specified clock domain for Tegra platforms + * conforming linux devfreq framework to realize dynamic frequency + * scaling. + */ +typedef enum _TEGRASOC_DEVFREQ_CLK +{ + TEGRASOC_DEVFREQ_CLK_GPC, + TEGRASOC_DEVFREQ_CLK_NVD, +} TEGRASOC_DEVFREQ_CLK; + +/*! + * @brief The order of the display clocks in the below defined enum + * should be synced with below mapping array and macro. + * All four should be updated simultaneously in case + * of removal or addition of clocks in below order. + * Also, TEGRASOC_WHICH_CLK_MAX is used in various places + * in below mentioned files. + * arch/nvalloc/unix/Linux/nv-linux.h + * + * arch/nvalloc/unix/src/os.c + * dispClkMapRmToOsArr[] = {...}; + * + * arch/nvalloc/unix/Linux/nv-clk.c + * osMapClk[] = {...}; + * + */ +typedef enum _TEGRASOC_WHICH_CLK +{ + TEGRASOC_WHICH_CLK_NVDISPLAYHUB, + TEGRASOC_WHICH_CLK_NVDISPLAY_DISP, + TEGRASOC_WHICH_CLK_NVDISPLAY_P0, + TEGRASOC_WHICH_CLK_NVDISPLAY_P1, + TEGRASOC_WHICH_CLK_NVDISPLAY_P2, + TEGRASOC_WHICH_CLK_NVDISPLAY_P3, + TEGRASOC_WHICH_CLK_NVDISPLAY_P4, + TEGRASOC_WHICH_CLK_NVDISPLAY_P5, + TEGRASOC_WHICH_CLK_NVDISPLAY_P6, + TEGRASOC_WHICH_CLK_NVDISPLAY_P7, + TEGRASOC_WHICH_CLK_DPAUX0, + TEGRASOC_WHICH_CLK_FUSE, + TEGRASOC_WHICH_CLK_DSIPLL_VCO, + TEGRASOC_WHICH_CLK_DSIPLL_CLKOUTPN, + TEGRASOC_WHICH_CLK_DSIPLL_CLKOUTA, + TEGRASOC_WHICH_CLK_SPPLL0_VCO, + TEGRASOC_WHICH_CLK_SPPLL0_CLKOUTA, + TEGRASOC_WHICH_CLK_SPPLL0_CLKOUTB, + TEGRASOC_WHICH_CLK_SPPLL0_CLKOUTPN, + TEGRASOC_WHICH_CLK_SPPLL1_CLKOUTPN, + TEGRASOC_WHICH_CLK_SPPLL0_DIV27, + TEGRASOC_WHICH_CLK_SPPLL1_DIV27, + TEGRASOC_WHICH_CLK_SPPLL0_DIV10, + TEGRASOC_WHICH_CLK_SPPLL0_DIV25, + TEGRASOC_WHICH_CLK_SPPLL1_VCO, + TEGRASOC_WHICH_CLK_VPLL0_REF, + TEGRASOC_WHICH_CLK_VPLL0, + TEGRASOC_WHICH_CLK_VPLL1, + TEGRASOC_WHICH_CLK_VPLL2, + TEGRASOC_WHICH_CLK_VPLL3, + TEGRASOC_WHICH_CLK_VPLL4, + TEGRASOC_WHICH_CLK_VPLL5, + TEGRASOC_WHICH_CLK_VPLL6, + TEGRASOC_WHICH_CLK_VPLL7, + TEGRASOC_WHICH_CLK_NVDISPLAY_P0_REF, + TEGRASOC_WHICH_CLK_RG0, + TEGRASOC_WHICH_CLK_RG1, + TEGRASOC_WHICH_CLK_RG2, + TEGRASOC_WHICH_CLK_RG3, + TEGRASOC_WHICH_CLK_RG4, + TEGRASOC_WHICH_CLK_RG5, + TEGRASOC_WHICH_CLK_RG6, + TEGRASOC_WHICH_CLK_RG7, + TEGRASOC_WHICH_CLK_DISPPLL, + TEGRASOC_WHICH_CLK_DISPHUBPLL, + TEGRASOC_WHICH_CLK_DSI_LP, + TEGRASOC_WHICH_CLK_DSI_CORE, + TEGRASOC_WHICH_CLK_DSI_PIXEL, + TEGRASOC_WHICH_CLK_PRE_SOR0, + TEGRASOC_WHICH_CLK_PRE_SOR1, + TEGRASOC_WHICH_CLK_PRE_SOR2, + TEGRASOC_WHICH_CLK_PRE_SOR3, + TEGRASOC_WHICH_CLK_DP_LINKA_REF, + TEGRASOC_WHICH_CLK_DP_LINKB_REF, + TEGRASOC_WHICH_CLK_DP_LINKC_REF, + TEGRASOC_WHICH_CLK_DP_LINKD_REF, + TEGRASOC_WHICH_CLK_SOR_LINKA_INPUT, + TEGRASOC_WHICH_CLK_SOR_LINKB_INPUT, + TEGRASOC_WHICH_CLK_SOR_LINKC_INPUT, + TEGRASOC_WHICH_CLK_SOR_LINKD_INPUT, + TEGRASOC_WHICH_CLK_SOR_LINKA_AFIFO, + TEGRASOC_WHICH_CLK_SOR_LINKB_AFIFO, + TEGRASOC_WHICH_CLK_SOR_LINKC_AFIFO, + TEGRASOC_WHICH_CLK_SOR_LINKD_AFIFO, + TEGRASOC_WHICH_CLK_SOR_LINKA_AFIFO_M, + TEGRASOC_WHICH_CLK_RG0_M, + TEGRASOC_WHICH_CLK_RG1_M, + TEGRASOC_WHICH_CLK_SOR0_M, + TEGRASOC_WHICH_CLK_SOR1_M, + TEGRASOC_WHICH_CLK_PLLHUB, + TEGRASOC_WHICH_CLK_SOR0, + TEGRASOC_WHICH_CLK_SOR1, + TEGRASOC_WHICH_CLK_SOR2, + TEGRASOC_WHICH_CLK_SOR3, + TEGRASOC_WHICH_CLK_SOR_PADA_INPUT, + TEGRASOC_WHICH_CLK_SOR_PADB_INPUT, + TEGRASOC_WHICH_CLK_SOR_PADC_INPUT, + TEGRASOC_WHICH_CLK_SOR_PADD_INPUT, + TEGRASOC_WHICH_CLK_SOR0_PAD, + TEGRASOC_WHICH_CLK_SOR1_PAD, + TEGRASOC_WHICH_CLK_SOR2_PAD, + TEGRASOC_WHICH_CLK_SOR3_PAD, + TEGRASOC_WHICH_CLK_PRE_SF0, + TEGRASOC_WHICH_CLK_SF0, + TEGRASOC_WHICH_CLK_SF1, + TEGRASOC_WHICH_CLK_SF2, + TEGRASOC_WHICH_CLK_SF3, + TEGRASOC_WHICH_CLK_SF4, + TEGRASOC_WHICH_CLK_SF5, + TEGRASOC_WHICH_CLK_SF6, + TEGRASOC_WHICH_CLK_SF7, + TEGRASOC_WHICH_CLK_DSI_PAD_INPUT, + TEGRASOC_WHICH_CLK_PRE_SOR0_REF, + TEGRASOC_WHICH_CLK_PRE_SOR1_REF, + TEGRASOC_WHICH_CLK_SOR0_PLL_REF, + TEGRASOC_WHICH_CLK_SOR1_PLL_REF, + TEGRASOC_WHICH_CLK_SOR2_PLL_REF, + TEGRASOC_WHICH_CLK_SOR3_PLL_REF, + TEGRASOC_WHICH_CLK_SOR0_REF, + TEGRASOC_WHICH_CLK_SOR1_REF, + TEGRASOC_WHICH_CLK_SOR2_REF, + TEGRASOC_WHICH_CLK_SOR3_REF, + TEGRASOC_WHICH_CLK_OSC, + TEGRASOC_WHICH_CLK_DSC, + TEGRASOC_WHICH_CLK_MAUD, + TEGRASOC_WHICH_CLK_AZA_2XBIT, + TEGRASOC_WHICH_CLK_AZA_BIT, + TEGRASOC_WHICH_CLK_MIPI_CAL, + TEGRASOC_WHICH_CLK_UART_FST_MIPI_CAL, + TEGRASOC_WHICH_CLK_SOR0_DIV, + TEGRASOC_WHICH_CLK_DISP_ROOT, + TEGRASOC_WHICH_CLK_HUB_ROOT, + TEGRASOC_WHICH_CLK_PLLA_DISP, + TEGRASOC_WHICH_CLK_PLLA_DISPHUB, + TEGRASOC_WHICH_CLK_PLLA, + TEGRASOC_WHICH_CLK_VPLLX_SOR0_MUXED, + TEGRASOC_WHICH_CLK_VPLLX_SOR1_MUXED, + TEGRASOC_WHICH_CLK_VPLLX_SOR2_MUXED, + TEGRASOC_WHICH_CLK_VPLLX_SOR3_MUXED, + TEGRASOC_WHICH_CLK_SF0_SOR, + TEGRASOC_WHICH_CLK_SF1_SOR, + TEGRASOC_WHICH_CLK_SF2_SOR, + TEGRASOC_WHICH_CLK_SF3_SOR, + TEGRASOC_WHICH_CLK_SF4_SOR, + TEGRASOC_WHICH_CLK_SF5_SOR, + TEGRASOC_WHICH_CLK_SF6_SOR, + TEGRASOC_WHICH_CLK_SF7_SOR, + TEGRASOC_WHICH_CLK_EMC, + TEGRASOC_WHICH_CLK_GPU_FIRST, + TEGRASOC_WHICH_CLK_GPU_SYS = TEGRASOC_WHICH_CLK_GPU_FIRST, + TEGRASOC_WHICH_CLK_GPU_NVD, + TEGRASOC_WHICH_CLK_GPU_UPROC, + TEGRASOC_WHICH_CLK_GPU_GPC0, + TEGRASOC_WHICH_CLK_GPU_GPC1, + TEGRASOC_WHICH_CLK_GPU_GPC2, + TEGRASOC_WHICH_CLK_GPU_LAST = TEGRASOC_WHICH_CLK_GPU_GPC2, + TEGRASOC_WHICH_CLK_MAX, // TEGRASOC_WHICH_CLK_MAX is defined for boundary checks only. +} TEGRASOC_WHICH_CLK; + +#ifdef NVRM + +extern const char *pNVRM_ID; + +/* + * ptr arithmetic convenience + */ + +typedef union +{ + volatile NvV8 Reg008[1]; + volatile NvV16 Reg016[1]; + volatile NvV32 Reg032[1]; +} nv_hwreg_t, * nv_phwreg_t; + + +#define NVRM_PCICFG_NUM_BARS 6 +#define NVRM_PCICFG_BAR_OFFSET(i) (0x10 + (i) * 4) +#define NVRM_PCICFG_BAR_REQTYPE_MASK 0x00000001 +#define NVRM_PCICFG_BAR_REQTYPE_MEMORY 0x00000000 +#define NVRM_PCICFG_BAR_MEMTYPE_MASK 0x00000006 +#define NVRM_PCICFG_BAR_MEMTYPE_64BIT 0x00000004 +#define NVRM_PCICFG_BAR_ADDR_MASK 0xfffffff0 + +#define NVRM_PCICFG_NUM_DWORDS 16 + +#define NV_GPU_NUM_BARS 3 +#define NV_GPU_BAR_INDEX_REGS 0 +#define NV_GPU_BAR_INDEX_FB 1 +#define NV_GPU_BAR_INDEX_IMEM 2 + +typedef struct +{ + NvU64 cpu_address; + NvU64 size; + NvU32 offset; + NvU32 *map; + nv_phwreg_t map_u; +} nv_aperture_t; + +typedef struct +{ + char *name; + NvU32 *data; +} nv_parm_t; + +#define NV_RM_PAGE_SHIFT 12 +#define NV_RM_PAGE_SIZE (1 << NV_RM_PAGE_SHIFT) +#define NV_RM_PAGE_MASK (NV_RM_PAGE_SIZE - 1) + +#define NV_RM_TO_OS_PAGE_SHIFT (os_page_shift - NV_RM_PAGE_SHIFT) +#define NV_RM_PAGES_TO_OS_PAGES(count) \ + ((((NvUPtr)(count)) >> NV_RM_TO_OS_PAGE_SHIFT) + \ + ((((count) & ((1 << NV_RM_TO_OS_PAGE_SHIFT) - 1)) != 0) ? 1 : 0)) + +// for dynamic granularity page array feature. +// Notice: dst_granu should be larger than src_granu. +#define NV_SRC_TO_DST_PAGE_SHIFT(src_granu, dst_granu) (GET_PAGE_SHIFT(dst_granu) - GET_PAGE_SHIFT(src_granu)) +#define NV_SRC_TO_DST_PAGE_COUNT(src_page_count,src_granu, dst_granu) \ + ((((NvUPtr)(src_page_count)) >> NV_SRC_TO_DST_PAGE_SHIFT(src_granu, dst_granu)) + \ + ((((src_page_count) & ((1 << NV_SRC_TO_DST_PAGE_SHIFT(src_granu, dst_granu)) - 1)) != 0) ? 1 : 0)) + +#if defined(NVCPU_X86_64) +#define NV_STACK_SIZE (NV_RM_PAGE_SIZE * 3) +#else +#define NV_STACK_SIZE (NV_RM_PAGE_SIZE * 2) +#endif + +typedef struct nvidia_stack_s +{ + NvU32 size; + void *top; + NvU8 stack[NV_STACK_SIZE-16] __attribute__ ((aligned(16))); +} nvidia_stack_t; + +/* + * TODO: Remove once all UNIX layers have been converted to use nvidia_stack_t + */ +typedef nvidia_stack_t nv_stack_t; + +typedef struct nv_file_private_t nv_file_private_t; + +/* + * this is a wrapper for unix events + * unlike the events that will be returned to clients, this includes + * kernel-specific data, such as file pointer, etc.. + */ +typedef struct nv_event_s +{ + NvHandle hParent; + NvHandle hObject; + NvU32 index; + NvU32 info32; + NvU16 info16; + nv_file_private_t *nvfp; /* per file-descriptor data pointer */ + NvU32 fd; + PORT_ATOMIC NvS32 active; /* whether the event should be signaled */ + NvU32 refcount; /* count of associated RM events */ + struct nv_event_s *next; +} nv_event_t; + +typedef struct nv_kern_mapping_s +{ + void *addr; + NvU64 size; + NvU32 modeFlag; + struct nv_kern_mapping_s *next; +} nv_kern_mapping_t; + +typedef struct nv_usermap_access_params_s +{ + NvU64 addr; + NvU64 size; + NvU64 offset; + NvU64 *page_array; + NvU64 num_pages; + MemoryArea memArea; + NvU64 access_start; + NvU64 access_size; + NvBool contig; + NvU32 caching; +} nv_usermap_access_params_t; + +/* + * It stores mapping context per mapping + */ +typedef struct nv_alloc_mapping_context_s { + void *alloc; + NvU64 page_index; + NvU64 *page_array; + NvU64 num_pages; + MemoryArea memArea; + NvU64 access_start; + NvU64 access_size; + NvU32 prot; + NvBool valid; + NvU32 caching; +} nv_alloc_mapping_context_t; + +struct nv_alloc_mapping_list_node_s; + +typedef struct nv_alloc_mapping_list_node_s { + nv_alloc_mapping_context_t context; + MemoryRange fileRange; + struct nv_alloc_mapping_list_node_s *pNext; + struct nv_alloc_mapping_list_node_s *pPrev; +} nv_alloc_mapping_list_node_t; + +typedef enum +{ + NV_SOC_IRQ_DISPLAY_TYPE = 0x1, + NV_SOC_IRQ_DPAUX_TYPE, + NV_SOC_IRQ_GPIO_TYPE, + NV_SOC_IRQ_HDACODEC_TYPE, + NV_SOC_IRQ_TCPC2DISP_TYPE, + NV_SOC_IRQ_INVALID_TYPE +} nv_soc_irq_type_t; + +/* + * It stores interrupt numbers and interrupt type and private data + */ +typedef struct nv_soc_irq_info_s { + NvU32 irq_num; + nv_soc_irq_type_t irq_type; + NvBool bh_pending; + union { + NvU32 gpio_num; + NvU32 dpaux_instance; + } irq_data; + NvS32 ref_count; +} nv_soc_irq_info_t; + +#define NV_MAX_SOC_IRQS 10 +#define NV_MAX_DPAUX_NUM_DEVICES 4 +#define NV_MAX_DPAUX_DEV_NAME_SIZE 10 + +#define NV_MAX_SOC_DPAUX_NUM_DEVICES 4 + +/* + * per device state + */ + +/* DMA-capable device data, defined by kernel interface layer */ +typedef struct nv_dma_device nv_dma_device_t; + +typedef struct nv_phys_addr_range +{ + NvU64 addr; + NvU64 len; +} nv_phys_addr_range_t; + +typedef struct +{ + char vbios_version[15]; + char firmware_version[64]; +} nv_cached_gpu_info_t; + +typedef struct nv_state_t +{ + void *priv; /* private data */ + void *os_state; /* os-specific device state */ + + int flags; + + /* PCI config info */ + nv_pci_info_t pci_info; + NvU16 subsystem_id; + NvU16 subsystem_vendor; + NvU32 gpu_id; + NvU32 iovaspace_id; + struct + { + NvBool valid; + NvU8 uuid[GPU_UUID_LEN]; + NvBool pci_uuid_read_attempted; + NV_STATUS pci_uuid_status; + } nv_uuid_cache; + void *handle; + + NvU32 pci_cfg_space[NVRM_PCICFG_NUM_DWORDS]; + + /* physical characteristics */ + nv_aperture_t bars[NV_GPU_NUM_BARS]; + nv_aperture_t *regs; + nv_aperture_t *dpaux[NV_MAX_DPAUX_NUM_DEVICES]; + nv_aperture_t *hdacodec_regs; + nv_aperture_t *mipical_regs; + nv_aperture_t *fb, ud; + nv_aperture_t *simregs; + + NvU32 num_dpaux_instance; + NvU32 interrupt_line; + NvU32 dpaux_irqs[NV_MAX_DPAUX_NUM_DEVICES]; + char dpaux_devname[NV_MAX_DPAUX_NUM_DEVICES][NV_MAX_DPAUX_DEV_NAME_SIZE]; + nv_soc_irq_info_t soc_irq_info[NV_MAX_SOC_IRQS]; + NvS32 current_soc_irq; + NvU32 num_soc_irqs; + NvU32 hdacodec_irq; + NvU32 tcpc2disp_irq; + NvU8 *soc_dcb_blob; + NvU32 soc_dcb_size; + NvU32 disp_sw_soc_chip_id; + NvBool soc_is_dpalt_mode_supported; + NvBool soc_is_hfrp_supported; + NvBool soc_is_external_phy_supported; + NvU64 dma_mask; + + NvBool is_tegra_pci_igpu; + NvBool supports_tegra_igpu_rg; + NvBool is_tegra_pci_igpu_rg_enabled; + NvU32 tegra_pci_igpu_pg_mask; + + NvBool primary_vga; + + NvU32 sim_env; + + NvU32 rc_timer_enabled; + + /* list of events allocated for this device */ + nv_event_t *event_list; + + /* lock to protect event_list */ + void *event_spinlock; + + nv_kern_mapping_t *kern_mappings; + + /* Kernel interface DMA device data */ + nv_dma_device_t *dma_dev; + nv_dma_device_t *niso_dma_dev; + + /* + * Per-GPU queue. The actual queue object is usually allocated in the + * arch-specific parent structure (e.g. nv_linux_state_t), and this + * pointer just points to it. + */ + struct os_work_queue *queue; + + /* For loading RM as a firmware (DCE or GSP) client */ + NvBool request_firmware; /* request firmware from the OS */ + NvBool request_fw_client_rm; /* attempt to init RM as FW a client */ + NvBool allow_fallback_to_monolithic_rm; /* allow fallback to monolithic RM if FW client RM doesn't work out */ + NvBool enable_firmware_logs; /* attempt to enable firmware log decoding/printing */ + + /* Variable to track, if nvidia_remove is called */ + NvBool removed; + + NvBool console_device; + + /* Variable to track, if GPU is external GPU */ + NvBool is_external_gpu; + + /* Variable to track, if regkey PreserveVideoMemoryAllocations is set */ + NvBool preserve_vidmem_allocations; + + /* Variable to force allocation of 32-bit addressable memory */ + NvBool force_dma32_alloc; + + /* PCI power state should be D0 during system suspend */ + NvBool d0_state_in_suspend; + + /* Current cyclestats client and context */ + NvU32 profiler_owner; + void *profiler_context; + + /* + * RMAPI objects to use in the OS layer to talk to core RM. + * + * Note that we only need to store one subdevice handle: in SLI, we will + * have a separate nv_state_t per physical GPU. + */ + struct { + NvHandle hClient; + NvHandle hDevice; + NvHandle hSubDevice; + NvHandle hI2C; + NvHandle hDisp; + } rmapi; + + /* Bool to check if dma-buf is supported */ + NvBool dma_buf_supported; + + /* Bool to check if the device received a shutdown notification */ + NvBool is_shutdown; + + /* Bool to check if the GPU has a coherent sysmem link */ + NvBool coherent; + + /* + * Bool to check if GPU memory is backed by struct page. + * False for non-coherent platforms. May also be false + * on coherent platforms if GPU memory is not onlined to the kernel. + */ + NvBool mem_has_struct_page; + + /* + * Coherent GPU Memory Mode, one of: + * NV_COHERENT_GPU_MEM_MODE_NONE + * NV_COHERENT_GPU_MEM_MODE_NUMA + * NV_COHERENT_GPU_MEM_MODE_DRIVER + */ + NvBool coherent_gpu_mem_mode; + + /* OS detected GPU has ATS capability */ + NvBool ats_support; + /* + * NUMA node ID of the CPU to which the GPU is attached. + * Holds NUMA_NO_NODE on platforms that don't support NUMA configuration. + */ + NvS32 cpu_numa_node_id; + + struct { + /* Bool to check if ISO iommu enabled */ + NvBool iso_iommu_present; + /* Bool to check if NISO iommu enabled */ + NvBool niso_iommu_present; + /* Display SMMU Stream IDs */ + NvU32 dispIsoStreamId; + NvU32 dispNisoStreamId; + } iommus; + + struct { + NvU32 max_dispclk_rate_using_disppllkhz; + NvU32 max_dispclk_rate_using_sppll0clkoutakhz; + NvU32 max_hubclk_rate_using_sppll0clkoutbkhz; + } clocks; + + /* Console is managed by drm drivers or NVKMS */ + NvBool client_managed_console; + + /* Console is mapped to sysmem instead of GPU PCIe BAR1 or BAR2 */ + NvBool sysmem_mapped_console; + + /* Struct to cache the gpu info details */ + nv_cached_gpu_info_t cached_gpu_info; + + /* Bool to check if power management is supported */ + NvBool is_pm_unsupported; + + /* Bool to check if the GPU is a CXL device */ + NvBool is_cxl_dev; +} nv_state_t; + +#define NVFP_TYPE_NONE ((NvU32)0x0) +#define NVFP_TYPE_REFCOUNTED ((NvU32)0x1) +#define NVFP_TYPE_REGISTERED ((NvU32)0x2) + +struct nv_file_private_t +{ + NvHandle *handles; + NvU16 maxHandles; + NvU32 deviceInstance; + NvU32 gpuInstanceId; + NvU8 metadata[64]; + + nv_file_private_t * PORT_ATOMIC ctl_nvfp; + void *ctl_nvfp_priv; + PORT_ATOMIC NvU32 register_or_refcount; + // In-flight nv_post_event() calls using this file private. + PORT_ATOMIC NvS32 event_posting_refcount; + + // + // True if a client or an event was ever allocated on this fd. + // If false, RMAPI cleanup is skipped. + // + NvBool bCleanupRmapi; +}; + +static inline NvS32 nv_event_posting_refcount_read(nv_file_private_t *nvfp) +{ + return *((volatile NvS32 *)&nvfp->event_posting_refcount); +} + +// Forward define the gpu ops structures +typedef struct gpuSession *nvgpuSessionHandle_t; +typedef struct gpuDevice *nvgpuDeviceHandle_t; +typedef struct gpuAddressSpace *nvgpuAddressSpaceHandle_t; +typedef struct gpuTsg *nvgpuTsgHandle_t; +typedef struct UvmGpuTsgAllocParams_tag nvgpuTsgAllocParams_t; +typedef struct gpuChannel *nvgpuChannelHandle_t; +typedef struct UvmGpuChannelInfo_tag *nvgpuChannelInfo_t; +typedef struct UvmGpuChannelAllocParams_tag nvgpuChannelAllocParams_t; +typedef struct UvmGpuCaps_tag *nvgpuCaps_t; +typedef struct UvmGpuCopyEnginesCaps_tag *nvgpuCesCaps_t; +typedef struct UvmGpuAddressSpaceInfo_tag *nvgpuAddressSpaceInfo_t; +typedef struct UvmGpuAllocInfo_tag *nvgpuAllocInfo_t; +typedef struct UvmGpuP2PCapsParams_tag *nvgpuP2PCapsParams_t; +typedef struct UvmGpuFbInfo_tag *nvgpuFbInfo_t; +typedef struct UvmGpuNvlinkInfo_tag *nvgpuNvlinkInfo_t; +typedef struct UvmGpuEccInfo_tag *nvgpuEccInfo_t; +typedef struct UvmGpuFaultInfo_tag *nvgpuFaultInfo_t; +typedef struct UvmGpuAccessCntrInfo_tag *nvgpuAccessCntrInfo_t; +typedef struct UvmGpuAccessCntrConfig_tag nvgpuAccessCntrConfig_t; +typedef struct UvmGpuInfo_tag nvgpuInfo_t; +typedef struct UvmGpuClientInfo_tag nvgpuClientInfo_t; +typedef struct UvmPmaAllocationOptions_tag *nvgpuPmaAllocationOptions_t; +typedef struct UvmPmaStatistics_tag *nvgpuPmaStatistics_t; +typedef struct UvmGpuMemoryInfo_tag *nvgpuMemoryInfo_t; +typedef struct UvmGpuExternalMappingInfo_tag *nvgpuExternalMappingInfo_t; +typedef struct UvmGpuExternalPhysAddrInfo_tag *nvgpuExternalPhysAddrInfo_t; +typedef struct UvmGpuChannelResourceInfo_tag *nvgpuChannelResourceInfo_t; +typedef struct UvmGpuChannelInstanceInfo_tag *nvgpuChannelInstanceInfo_t; +typedef struct UvmGpuChannelResourceBindParams_tag *nvgpuChannelResourceBindParams_t; +typedef struct UvmGpuPagingChannelAllocParams_tag nvgpuPagingChannelAllocParams_t; +typedef struct UvmGpuPagingChannel_tag *nvgpuPagingChannelHandle_t; +typedef struct UvmGpuPagingChannelInfo_tag *nvgpuPagingChannelInfo_t; +typedef enum UvmPmaGpuMemoryType_tag nvgpuGpuMemoryType_t; +typedef NV_STATUS (*nvPmaEvictPagesCallback)(void *, NvU64, NvU64 *, NvU32, NvU64, NvU64, nvgpuGpuMemoryType_t); +typedef NV_STATUS (*nvPmaEvictRangeCallback)(void *, NvU64, NvU64, nvgpuGpuMemoryType_t); +typedef struct UvmGpuAccessBitsBufferAlloc_tag *nvgpuAccessBitBufferAlloc_t; +/* + * flags + */ + +#define NV_FLAG_INITIALIZED 0x0001 +#define NV_FLAG_EXCLUDE 0x0002 +#define NV_FLAG_CONTROL 0x0004 +#define NV_FLAG_PCI_P2P_UNSUPPORTED_CHIPSET 0x0008 +#define NV_FLAG_SOC_DISPLAY 0x0010 +#define NV_FLAG_USES_MSI 0x0020 +#define NV_FLAG_USES_MSIX 0x0040 +#define NV_FLAG_PASSTHRU 0x0080 +#define NV_FLAG_SUSPENDED 0x0100 +#define NV_FLAG_HAS_CONSOLE_IN_SYSMEM_CARVEOUT 0x0200 +/* To be set when an FLR needs to be triggered after device shut down. */ +#define NV_FLAG_TRIGGER_FLR 0x0400 +#define NV_FLAG_PERSISTENT_SW_STATE 0x0800 +#define NV_FLAG_IN_RECOVERY 0x1000 +// Unused 0x2000 +#define NV_FLAG_UNBIND_LOCK 0x4000 +/* To be set when GPU is not present on the bus, to help device teardown */ +#define NV_FLAG_IN_SURPRISE_REMOVAL 0x8000 + +typedef enum +{ + NV_PM_ACTION_HIBERNATE, + NV_PM_ACTION_STANDBY, + NV_PM_ACTION_RESUME +} nv_pm_action_t; + +typedef enum +{ + NV_PM_ACTION_DEPTH_DEFAULT, + NV_PM_ACTION_DEPTH_MODESET, + NV_PM_ACTION_DEPTH_UVM +} nv_pm_action_depth_t; + +typedef enum +{ + NV_DYNAMIC_PM_NEVER, + NV_DYNAMIC_PM_COARSE, + NV_DYNAMIC_PM_FINE +} nv_dynamic_power_mode_t; + +typedef enum +{ + NV_POWER_STATE_IN_HIBERNATE, + NV_POWER_STATE_IN_STANDBY, + NV_POWER_STATE_RUNNING +} nv_power_state_t; + +typedef struct +{ + const char *vidmem_power_status; + const char *dynamic_power_status; + const char *gc6_support; + const char *gcoff_support; + const char *s0ix_status; + const char *db_support; +} nv_power_info_t; + +typedef enum +{ + NV_MEMORY_TYPE_SYSTEM, /* Memory mapped for ROM, SBIOS and physical RAM. */ + NV_MEMORY_TYPE_REGISTERS, + NV_MEMORY_TYPE_FRAMEBUFFER, + NV_MEMORY_TYPE_DEVICE_MMIO, /* All kinds of MMIO referred by NVRM e.g. BARs and MCFG of device */ +} nv_memory_type_t; + +#define NV_PRIMARY_VGA(nv) ((nv)->primary_vga) + +#define NV_IS_CTL_DEVICE(nv) ((nv)->flags & NV_FLAG_CONTROL) +#define NV_IS_SOC_DISPLAY_DEVICE(nv) \ + ((nv)->flags & NV_FLAG_SOC_DISPLAY) + +#define NV_IS_DEVICE_IN_SURPRISE_REMOVAL(nv) \ + (((nv)->flags & NV_FLAG_IN_SURPRISE_REMOVAL) != 0) + +#define NV_HAS_CONSOLE_IN_SYSMEM_CARVEOUT(nv) \ + (((nv)->flags & NV_FLAG_HAS_CONSOLE_IN_SYSMEM_CARVEOUT) != 0) + +/* + * For console setup by EFI GOP, the base address is BAR1. + * For console setup by VBIOS, the base address is BAR2 + 16MB. + */ +#define NV_IS_CONSOLE_MAPPED(nv, addr) \ + (((addr) == (nv)->bars[NV_GPU_BAR_INDEX_FB].cpu_address) || \ + ((addr) == ((nv)->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000))) + +#define NV_SOC_IS_ISO_IOMMU_PRESENT(nv) \ + ((nv)->iommus.iso_iommu_present) + +#define NV_SOC_IS_NISO_IOMMU_PRESENT(nv) \ + ((nv)->iommus.niso_iommu_present) +/* + * GPU add/remove events + */ +#define NV_SYSTEM_GPU_ADD_EVENT 0x9001 +#define NV_SYSTEM_GPU_REMOVE_EVENT 0x9002 + +/* + * NVIDIA ACPI sub-event IDs (event types) to be passed into + * to core NVIDIA driver for ACPI events. + */ +#define NV_SYSTEM_ACPI_EVENT_VALUE_DISPLAY_SWITCH_DEFAULT 0 +#define NV_SYSTEM_ACPI_EVENT_VALUE_DOCK_EVENT_UNDOCKED 0 +#define NV_SYSTEM_ACPI_EVENT_VALUE_DOCK_EVENT_DOCKED 1 + +#define NV_ACPI_NVIF_HANDLE_PRESENT 0x01 +#define NV_ACPI_DSM_HANDLE_PRESENT 0x02 +#define NV_ACPI_WMMX_HANDLE_PRESENT 0x04 + +#define NV_EVAL_ACPI_METHOD_NVIF 0x01 +#define NV_EVAL_ACPI_METHOD_WMMX 0x02 + +/* + * Coherent GPU Memory Mode + */ +#define NV_COHERENT_GPU_MEM_MODE_NONE 0 +#define NV_COHERENT_GPU_MEM_MODE_NUMA 1 +#define NV_COHERENT_GPU_MEM_MODE_DRIVER 2 + +typedef enum { + NV_I2C_CMD_READ = 1, + NV_I2C_CMD_WRITE, + NV_I2C_CMD_SMBUS_READ, + NV_I2C_CMD_SMBUS_WRITE, + NV_I2C_CMD_SMBUS_QUICK_WRITE, + NV_I2C_CMD_SMBUS_QUICK_READ, + NV_I2C_CMD_SMBUS_BLOCK_READ, + NV_I2C_CMD_SMBUS_BLOCK_WRITE, + NV_I2C_CMD_BLOCK_READ, + NV_I2C_CMD_BLOCK_WRITE +} nv_i2c_cmd_t; + +// Flags needed by osAllocPagesNode / os_alloc_pages_node +#define NV_ALLOC_PAGES_NODE_NONE 0x0 +#define NV_ALLOC_PAGES_NODE_SKIP_RECLAIM 0x1 + +/* +** where we hide our nv_state_t * ... +*/ +#define NV_SET_NV_STATE(pgpu,p) ((pgpu)->pOsGpuInfo = (p)) +#define NV_GET_NV_STATE(pGpu) \ + (nv_state_t *)((pGpu) ? (pGpu)->pOsGpuInfo : NULL) + +static inline NvBool IS_REG_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) +{ + return ((offset >= nv->regs->cpu_address) && + ((offset + (length - 1)) >= offset) && + ((offset + (length - 1)) <= (nv->regs->cpu_address + (nv->regs->size - 1)))); +} + +static inline NvBool IS_FB_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) +{ + return ((nv->fb) && (nv->fb->size != 0) && + (offset >= nv->fb->cpu_address) && + ((offset + (length - 1)) >= offset) && + ((offset + (length - 1)) <= (nv->fb->cpu_address + (nv->fb->size - 1)))); +} + +static inline NvBool IS_UD_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) +{ + return ((nv->ud.cpu_address != 0) && (nv->ud.size != 0) && + (offset >= nv->ud.cpu_address) && + ((offset + (length - 1)) >= offset) && + ((offset + (length - 1)) <= (nv->ud.cpu_address + (nv->ud.size - 1)))); +} + +static inline NvBool IS_IMEM_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) +{ + return ((nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address != 0) && + (nv->bars[NV_GPU_BAR_INDEX_IMEM].size != 0) && + (offset >= nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address) && + ((offset + (length - 1)) >= offset) && + ((offset + (length - 1)) <= (nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + + (nv->bars[NV_GPU_BAR_INDEX_IMEM].size - 1)))); +} + +#define NV_RM_MAX_MSIX_LINES 8 + +#define NV_MAX_ISR_DELAY_US 20000 +#define NV_MAX_ISR_DELAY_MS (NV_MAX_ISR_DELAY_US / 1000) + +#define NV_TIMERCMP(a, b, CMP) \ + (((a)->tv_sec == (b)->tv_sec) ? \ + ((a)->tv_usec CMP (b)->tv_usec) : ((a)->tv_sec CMP (b)->tv_sec)) + +#define NV_TIMERADD(a, b, result) \ + { \ + (result)->tv_sec = (a)->tv_sec + (b)->tv_sec; \ + (result)->tv_usec = (a)->tv_usec + (b)->tv_usec; \ + if ((result)->tv_usec >= 1000000) \ + { \ + ++(result)->tv_sec; \ + (result)->tv_usec -= 1000000; \ + } \ + } + +#define NV_TIMERSUB(a, b, result) \ + { \ + (result)->tv_sec = (a)->tv_sec - (b)->tv_sec; \ + (result)->tv_usec = (a)->tv_usec - (b)->tv_usec; \ + if ((result)->tv_usec < 0) \ + { \ + --(result)->tv_sec; \ + (result)->tv_usec += 1000000; \ + } \ + } + +#define NV_TIMEVAL_TO_US(tv) ((NvU64)(tv).tv_sec * 1000000 + (tv).tv_usec) + +#ifndef NV_ALIGN_UP +#define NV_ALIGN_UP(v,g) (((v) + ((g) - 1)) & ~((g) - 1)) +#endif +#ifndef NV_ALIGN_DOWN +#define NV_ALIGN_DOWN(v,g) ((v) & ~((g) - 1)) +#endif + + +/* + * driver internal interfaces + */ + +/* + * --------------------------------------------------------------------------- + * + * Function prototypes for UNIX specific OS interface. + * + * --------------------------------------------------------------------------- + */ + +NvU32 NV_API_CALL nv_get_dev_minor (nv_state_t *); +void* NV_API_CALL nv_alloc_kernel_mapping (nv_state_t *, void *, NvU64, NvU32, NvU64, void **); +void NV_API_CALL nv_free_kernel_mapping (nv_state_t *, void *, void *, void *); +NV_STATUS NV_API_CALL nv_alloc_user_mapping (nv_state_t *, void *, NvU64, NvU32, NvU64, NvU32, NvU64 *, void **); +void NV_API_CALL nv_free_user_mapping (nv_state_t *, void *, NvU64, void *); +NV_STATUS NV_API_CALL nv_add_mapping_context_to_file (nv_state_t *, nv_usermap_access_params_t*, NvU32, void *, NvU64, NvU32); + +NvU64 NV_API_CALL nv_get_kern_phys_address (NvU64); +NvU64 NV_API_CALL nv_get_user_phys_address (NvU64); +nv_state_t* NV_API_CALL nv_get_adapter_state (NvU32, NvU8, NvU8); +nv_state_t* NV_API_CALL nv_get_ctl_state (void); + +void NV_API_CALL nv_set_dma_address_size (nv_state_t *, NvU32 ); + +NV_STATUS NV_API_CALL nv_alias_pages (nv_state_t *, NvU32, NvU64, NvU32, NvU32, NvU64, NvU64 *, NvBool, void **); +NV_STATUS NV_API_CALL nv_alloc_pages (nv_state_t *, NvU32, NvU64, NvBool, NvU32, NvBool, NvBool, NvS32, NvU64 *, void **); +NV_STATUS NV_API_CALL nv_free_pages (nv_state_t *, NvU32, NvBool, NvU32, void *); + +NV_STATUS NV_API_CALL nv_register_user_pages (nv_state_t *, NvU64, NvU64 *, void *, void **, NvBool); +void NV_API_CALL nv_unregister_user_pages (nv_state_t *, NvU64, void **, void **); + +NV_STATUS NV_API_CALL nv_register_peer_io_mem (nv_state_t *, NvU64 *, NvU64, void **); +void NV_API_CALL nv_unregister_peer_io_mem(nv_state_t *, void *); + +struct sg_table; + +NV_STATUS NV_API_CALL nv_register_sgt (nv_state_t *, NvU64 *, NvU64, NvU32, void **, + struct sg_table *, void *, NvBool); +void NV_API_CALL nv_unregister_sgt (nv_state_t *, struct sg_table **, void **, void *); +NV_STATUS NV_API_CALL nv_register_phys_pages (nv_state_t *, NvU64 *, NvU64, NvU32, void **); +void NV_API_CALL nv_unregister_phys_pages (nv_state_t *, void *); + +NV_STATUS NV_API_CALL nv_dma_map_sgt (nv_dma_device_t *, NvU64, NvU64 *, NvU32, NvBool, void **); + +NV_STATUS NV_API_CALL nv_dma_map_alloc (nv_dma_device_t *, NvU64, NvU64 *, NvBool, NvBool, void **); +NV_STATUS NV_API_CALL nv_dma_unmap_alloc (nv_dma_device_t *, NvU64, NvU64 *, void **); + +NV_STATUS NV_API_CALL nv_dma_map_peer (nv_dma_device_t *, nv_dma_device_t *, NvU8, NvU64, NvU64 *); +void NV_API_CALL nv_dma_unmap_peer (nv_dma_device_t *, NvU64, NvU64); + +NV_STATUS NV_API_CALL nv_dma_map_mmio (nv_dma_device_t *, NvU64, NvU64 *); +void NV_API_CALL nv_dma_unmap_mmio (nv_dma_device_t *, NvU64, NvU64); + +void NV_API_CALL nv_dma_cache_invalidate (nv_dma_device_t *, void *); +void* NV_API_CALL nv_dma_get_dev_pagemap (NvU64); +void NV_API_CALL nv_dma_put_dev_pagemap (void *); +NvBool NV_API_CALL nv_grdma_pci_topology_supported(nv_state_t *, nv_dma_device_t *); + +NvS32 NV_API_CALL nv_start_rc_timer (nv_state_t *); +NvS32 NV_API_CALL nv_stop_rc_timer (nv_state_t *); + +void NV_API_CALL nv_post_event (nv_event_t *, NvHandle, NvU32, NvU32, NvU16, NvBool); +NvS32 NV_API_CALL nv_get_event (nv_file_private_t *, nv_event_t *, NvU32 *); + +void* NV_API_CALL nv_i2c_add_adapter (nv_state_t *, NvU32); +void NV_API_CALL nv_i2c_del_adapter (nv_state_t *, void *); + +void NV_API_CALL nv_acpi_methods_init (NvU32 *); +void NV_API_CALL nv_acpi_methods_uninit (void); + +NV_STATUS NV_API_CALL nv_acpi_method (NvU32, NvU32, NvU32, void *, NvU16, NvU32 *, void *, NvU16 *); +NV_STATUS NV_API_CALL nv_acpi_d3cold_dsm_for_upstream_port (nv_state_t *, NvU8 *, NvU32, NvU32, NvU32 *); +NV_STATUS NV_API_CALL nv_acpi_dsm_method (nv_state_t *, NvU8 *, NvU32, NvBool, NvU32, void *, NvU16, NvU32 *, void *, NvU16 *); +NV_STATUS NV_API_CALL nv_acpi_ddc_method (nv_state_t *, void *, NvU32 *, NvBool); +NV_STATUS NV_API_CALL nv_acpi_dod_method (nv_state_t *, NvU32 *, NvU32 *); +NV_STATUS NV_API_CALL nv_acpi_rom_method (nv_state_t *, NvU32 *, NvU32 *); +NV_STATUS NV_API_CALL nv_acpi_get_powersource (NvU32 *); +NvBool NV_API_CALL nv_acpi_is_battery_present(void); + +NV_STATUS NV_API_CALL nv_acpi_mux_method (nv_state_t *, NvU32 *, NvU32, const char *); + +NV_STATUS NV_API_CALL nv_log_error (nv_state_t *, NvU32, const char *, va_list); + +NvBool NV_API_CALL nv_requires_dma_remap (nv_state_t *); + +NvBool NV_API_CALL nv_is_rm_firmware_active(nv_state_t *); +const void*NV_API_CALL nv_get_firmware(nv_state_t *, nv_firmware_type_t, nv_firmware_chip_family_t, const void **, NvU32 *); +void NV_API_CALL nv_put_firmware(const void *); + +nv_file_private_t* NV_API_CALL nv_get_file_private(NvS32, NvBool, void **); +void NV_API_CALL nv_put_file_private(void *); + +NV_STATUS NV_API_CALL nv_get_device_memory_config(nv_state_t *, NvU64 *, NvU64 *, NvU64 *, NvU64 *, NvU32 *, NvS32 *); +NV_STATUS NV_API_CALL nv_get_egm_info(nv_state_t *, NvU64 *, NvU64 *, NvS32 *); + +void NV_API_CALL nv_p2p_free_platform_data(void *data); + +NV_STATUS NV_API_CALL nv_revoke_gpu_mappings (nv_state_t *); +void NV_API_CALL nv_acquire_mmap_lock (nv_state_t *); +void NV_API_CALL nv_release_mmap_lock (nv_state_t *); +NvBool NV_API_CALL nv_get_all_mappings_revoked_locked (nv_state_t *); +void NV_API_CALL nv_set_safe_to_mmap_locked (nv_state_t *, NvBool); + +nv_alloc_mapping_list_node_t** NV_API_CALL nv_acquire_file_va(nv_file_private_t *, NvBool); +void NV_API_CALL nv_release_file_va(nv_file_private_t *, NvBool); + +NV_STATUS NV_API_CALL nv_indicate_idle (nv_state_t *); +NV_STATUS NV_API_CALL nv_indicate_not_idle (nv_state_t *); +void NV_API_CALL nv_idle_holdoff (nv_state_t *); + +NvBool NV_API_CALL nv_dynamic_power_available (nv_state_t *); +void NV_API_CALL nv_audio_dynamic_power (nv_state_t *); + +void NV_API_CALL nv_control_soc_irqs (nv_state_t *, NvBool bEnable); +NV_STATUS NV_API_CALL nv_get_current_irq_priv_data(nv_state_t *, NvU32 *); + +NV_STATUS NV_API_CALL nv_acquire_fabric_mgmt_cap (int, int*); +int NV_API_CALL nv_cap_drv_init(void); +void NV_API_CALL nv_cap_drv_exit(void); +NvBool NV_API_CALL nv_is_gpu_accessible(nv_state_t *); +NvBool NV_API_CALL nv_match_gpu_os_info(nv_state_t *, void *); + +void NV_API_CALL nv_get_updated_emu_seg(NvU32 *start, NvU32 *end); +void NV_API_CALL nv_get_screen_info(nv_state_t *, NvU64 *, NvU32 *, NvU32 *, NvU32 *, NvU32 *, NvU64 *); +void NV_API_CALL nv_set_gpu_pg_mask(nv_state_t *); + +struct dma_buf; +typedef struct nv_dma_buf nv_dma_buf_t; +struct drm_gem_object; + +NV_STATUS NV_API_CALL nv_dma_import_sgt (nv_dma_device_t *, struct sg_table *, struct drm_gem_object *); +void NV_API_CALL nv_dma_release_sgt(struct sg_table *, struct drm_gem_object *); +NV_STATUS NV_API_CALL nv_dma_import_dma_buf (nv_dma_device_t *, struct dma_buf *, NvBool, NvU32 *, struct sg_table **, nv_dma_buf_t **); +NV_STATUS NV_API_CALL nv_dma_import_from_fd (nv_dma_device_t *, NvS32, NvBool, NvU32 *, struct sg_table **, nv_dma_buf_t **); +void NV_API_CALL nv_dma_release_dma_buf (nv_dma_buf_t *); + +void NV_API_CALL nv_schedule_uvm_isr (nv_state_t *); + +NV_STATUS NV_API_CALL nv_schedule_uvm_drain_p2p (NvU8 *); +void NV_API_CALL nv_schedule_uvm_resume_p2p (NvU8 *); + +NvBool NV_API_CALL nv_platform_supports_s0ix (void); +NvBool NV_API_CALL nv_s2idle_pm_configured (void); + +NvBool NV_API_CALL nv_pci_tegra_register_power_domain (nv_state_t *, NvBool); +NvBool NV_API_CALL nv_pci_tegra_pm_init (nv_state_t *); +void NV_API_CALL nv_pci_tegra_pm_deinit (nv_state_t *); + +NvBool NV_API_CALL nv_is_chassis_notebook (void); +void NV_API_CALL nv_allow_runtime_suspend (nv_state_t *nv); +void NV_API_CALL nv_disallow_runtime_suspend (nv_state_t *nv); + +typedef void (*nvTegraDceClientIpcCallback)(NvU32, NvU32, NvU32, void *, void *); + +NV_STATUS NV_API_CALL nv_get_num_phys_pages (void *, NvU32 *); +NV_STATUS NV_API_CALL nv_get_phys_pages (void *, void *, NvU32 *); +void NV_API_CALL nv_get_disp_smmu_stream_ids (nv_state_t *, NvU32 *, NvU32 *); + +typedef struct TEGRA_IMP_IMPORT_DATA TEGRA_IMP_IMPORT_DATA; +typedef struct nv_i2c_msg_s nv_i2c_msg_t; + +NV_STATUS NV_API_CALL nv_bpmp_send_mrq (nv_state_t *, NvU32, const void *, NvU32, void *, NvU32, NvS32 *, NvS32 *); +NV_STATUS NV_API_CALL nv_i2c_transfer(nv_state_t *, NvU32, NvU8, nv_i2c_msg_t *, int); +void NV_API_CALL nv_i2c_unregister_clients(nv_state_t *); +NV_STATUS NV_API_CALL nv_i2c_bus_status(nv_state_t *, NvU32, NvS32 *, NvS32 *); +NV_STATUS NV_API_CALL nv_imp_get_import_data (TEGRA_IMP_IMPORT_DATA *); +NV_STATUS NV_API_CALL nv_imp_get_uefi_data (nv_state_t *nv, NvU32 *iso_bw_kbps, NvU32 *floor_bw_kbps); +NV_STATUS NV_API_CALL nv_imp_enable_disable_rfl (nv_state_t *nv, NvBool bEnable); +NV_STATUS NV_API_CALL nv_imp_icc_set_bw (nv_state_t *nv, NvU32 avg_bw_kbps, NvU32 floor_bw_kbps); +NV_STATUS NV_API_CALL nv_get_num_dpaux_instances(nv_state_t *nv, NvU32 *num_instances); +NV_STATUS NV_API_CALL nv_get_tegra_brightness_level(nv_state_t *, NvU32 *); +NV_STATUS NV_API_CALL nv_set_tegra_brightness_level(nv_state_t *, NvU32); + +NV_STATUS NV_API_CALL nv_soc_device_reset (nv_state_t *); +NV_STATUS NV_API_CALL nv_soc_pm_powergate (nv_state_t *); +NV_STATUS NV_API_CALL nv_soc_pm_unpowergate (nv_state_t *); +NV_STATUS NV_API_CALL nv_gpio_get_pin_state(nv_state_t *, NvU32, NvU32 *); +void NV_API_CALL nv_gpio_set_pin_state(nv_state_t *, NvU32, NvU32); +NV_STATUS NV_API_CALL nv_gpio_set_pin_direction(nv_state_t *, NvU32, NvU32); +NV_STATUS NV_API_CALL nv_gpio_get_pin_direction(nv_state_t *, NvU32, NvU32 *); +NV_STATUS NV_API_CALL nv_gpio_get_pin_number(nv_state_t *, NvU32, NvU32 *); +NvBool NV_API_CALL nv_gpio_get_pin_interrupt_status(nv_state_t *, NvU32, NvU32); +NV_STATUS NV_API_CALL nv_gpio_set_pin_interrupt(nv_state_t *, NvU32, NvU32); +NvU32 NV_API_CALL nv_tegra_get_rm_interface_type(NvU32); +NV_STATUS NV_API_CALL nv_tegra_dce_register_ipc_client(NvU32, void *, nvTegraDceClientIpcCallback, NvU32 *); +NV_STATUS NV_API_CALL nv_tegra_dce_client_ipc_send_recv(NvU32, void *, NvU32); +NV_STATUS NV_API_CALL nv_tegra_dce_unregister_ipc_client(NvU32); +NV_STATUS NV_API_CALL nv_dsi_parse_panel_props(nv_state_t *, void *); +NvBool NV_API_CALL nv_dsi_is_panel_connected(nv_state_t *); +NV_STATUS NV_API_CALL nv_dsi_panel_enable(nv_state_t *, void *); +NV_STATUS NV_API_CALL nv_dsi_panel_reset(nv_state_t *, void *); +void NV_API_CALL nv_dsi_panel_disable(nv_state_t *, void *); +void NV_API_CALL nv_dsi_panel_cleanup(nv_state_t *, void *); +NV_STATUS NV_API_CALL nv_soc_mipi_cal_reset(nv_state_t *); +NvU32 NV_API_CALL nv_soc_fuse_register_read (NvU32 addr); +NvBool NV_API_CALL nv_get_hdcp_enabled(nv_state_t *nv); +NV_STATUS NV_API_CALL nv_get_valid_window_head_mask(nv_state_t *nv, NvU64 *); +NV_STATUS NV_API_CALL nv_dp_uphy_pll_init(nv_state_t *, NvU32, NvU32); +NV_STATUS NV_API_CALL nv_dp_uphy_pll_deinit(nv_state_t *); +NV_STATUS NV_API_CALL nv_soc_i2c_hsp_semaphore_acquire(NvU32 ownerId, NvBool bAcquire, NvU64 timeout); +typedef void (*nv_soc_tsec_cb_func_t)(void*, void*); +NvU32 NV_API_CALL nv_soc_tsec_send_cmd(void* cmd, nv_soc_tsec_cb_func_t cb_func, void* cb_context); +NvU32 NV_API_CALL nv_soc_tsec_event_register(nv_soc_tsec_cb_func_t cb_func, void* cb_context, NvBool is_init_event); +NvU32 NV_API_CALL nv_soc_tsec_event_unregister(NvBool is_init_event); +void* NV_API_CALL nv_soc_tsec_alloc_mem_desc(NvU32 num_bytes, NvU32 *flcn_addr); +void NV_API_CALL nv_soc_tsec_free_mem_desc(void *mem_desc); +NvBool NV_API_CALL nv_is_clk_enabled (nv_state_t *, TEGRASOC_WHICH_CLK); +NV_STATUS NV_API_CALL nv_set_parent (nv_state_t *, TEGRASOC_WHICH_CLK, TEGRASOC_WHICH_CLK); +NV_STATUS NV_API_CALL nv_get_parent (nv_state_t *, TEGRASOC_WHICH_CLK, TEGRASOC_WHICH_CLK*); +NV_STATUS NV_API_CALL nv_clk_get_handles (nv_state_t *); +void NV_API_CALL nv_clk_clear_handles (nv_state_t *); +NV_STATUS NV_API_CALL nv_enable_clk (nv_state_t *, TEGRASOC_WHICH_CLK); +void NV_API_CALL nv_disable_clk (nv_state_t *, TEGRASOC_WHICH_CLK); +NV_STATUS NV_API_CALL nv_get_curr_freq (nv_state_t *, TEGRASOC_WHICH_CLK, NvU32 *); +NV_STATUS NV_API_CALL nv_get_max_freq (nv_state_t *, TEGRASOC_WHICH_CLK, NvU32 *); +NV_STATUS NV_API_CALL nv_get_min_freq (nv_state_t *, TEGRASOC_WHICH_CLK, NvU32 *); +NV_STATUS NV_API_CALL nv_set_freq (nv_state_t *, TEGRASOC_WHICH_CLK, NvU32); + +void NV_API_CALL nv_pci_cxl_set_caching(nv_state_t *, NvBool); + +/* + * --------------------------------------------------------------------------- + * + * Function prototypes for Resource Manager interface. + * + * --------------------------------------------------------------------------- + */ + +NvBool NV_API_CALL rm_init_rm (nvidia_stack_t *); +void NV_API_CALL rm_shutdown_rm (nvidia_stack_t *); +NvBool NV_API_CALL rm_init_private_state (nvidia_stack_t *, nv_state_t *); +void NV_API_CALL rm_free_private_state (nvidia_stack_t *, nv_state_t *); +NvBool NV_API_CALL rm_init_adapter (nvidia_stack_t *, nv_state_t *); +void NV_API_CALL rm_disable_adapter (nvidia_stack_t *, nv_state_t *); +void NV_API_CALL rm_shutdown_adapter (nvidia_stack_t *, nv_state_t *); +NV_STATUS NV_API_CALL rm_exclude_adapter (nvidia_stack_t *, nv_state_t *); +NV_STATUS NV_API_CALL rm_acquire_api_lock (nvidia_stack_t *); +NV_STATUS NV_API_CALL rm_release_api_lock (nvidia_stack_t *); +NV_STATUS NV_API_CALL rm_acquire_gpu_lock (nvidia_stack_t *, nv_state_t *); +NV_STATUS NV_API_CALL rm_release_gpu_lock (nvidia_stack_t *, nv_state_t *); +NV_STATUS NV_API_CALL rm_acquire_all_gpus_lock (nvidia_stack_t *); +NV_STATUS NV_API_CALL rm_release_all_gpus_lock (nvidia_stack_t *); +NV_STATUS NV_API_CALL rm_ioctl (nvidia_stack_t *, nv_state_t *, nv_file_private_t *, NvU32, void *, NvU32); +NV_STATUS NV_API_CALL rm_validate_ioctls (NvU32, NvU32); +NvBool NV_API_CALL rm_isr (nvidia_stack_t *, nv_state_t *, NvU32 *); +void NV_API_CALL rm_isr_bh (nvidia_stack_t *, nv_state_t *); +void NV_API_CALL rm_isr_bh_unlocked (nvidia_stack_t *, nv_state_t *); +NvBool NV_API_CALL rm_is_msix_allowed (nvidia_stack_t *, nv_state_t *); +NvBool NV_API_CALL rm_wait_for_bar_firewall (nvidia_stack_t *, NvU32 domain, NvU8 bus, NvU8 device, NvU8 function, NvU16 devId, NvU16 subsystemId); +NV_STATUS NV_API_CALL rm_pmu_perfmon_get_load (nvidia_stack_t *, nv_state_t *, NvU32 *, TEGRASOC_DEVFREQ_CLK); +NV_STATUS NV_API_CALL rm_power_management (nvidia_stack_t *, nv_state_t *, nv_pm_action_t); +NV_STATUS NV_API_CALL rm_stop_user_channels (nvidia_stack_t *, nv_state_t *); +NV_STATUS NV_API_CALL rm_restart_user_channels (nvidia_stack_t *, nv_state_t *); +NV_STATUS NV_API_CALL rm_save_low_res_mode (nvidia_stack_t *, nv_state_t *); +char* NV_API_CALL rm_get_gpu_uuid (nvidia_stack_t *, nv_state_t *); +const NvU8* NV_API_CALL rm_get_gpu_uuid_raw (nvidia_stack_t *, nv_state_t *); +void NV_API_CALL rm_set_rm_firmware_requested(nvidia_stack_t *, nv_state_t *); +void NV_API_CALL rm_cleanup_file_private (nvidia_stack_t *, nv_state_t *, nv_file_private_t *); +void NV_API_CALL rm_unbind_lock (nvidia_stack_t *, nv_state_t *); +NV_STATUS NV_API_CALL rm_read_registry_dword (nvidia_stack_t *, nv_state_t *, const char *, NvU32 *); +NV_STATUS NV_API_CALL rm_write_registry_dword (nvidia_stack_t *, nv_state_t *, const char *, NvU32); +NV_STATUS NV_API_CALL rm_write_registry_binary (nvidia_stack_t *, nv_state_t *, const char *, NvU8 *, NvU32); +NV_STATUS NV_API_CALL rm_write_registry_string (nvidia_stack_t *, nv_state_t *, const char *, const char *, NvU32); +void NV_API_CALL rm_parse_option_string (nvidia_stack_t *, const char *); +char* NV_API_CALL rm_remove_spaces (const char *); +char* NV_API_CALL rm_string_token (char **, const char); +void NV_API_CALL rm_vgpu_vfio_set_driver_vm(nvidia_stack_t *, NvBool); +NV_STATUS NV_API_CALL rm_get_adapter_status_external(nvidia_stack_t *, nv_state_t *); + +NV_STATUS NV_API_CALL rm_run_rc_callback (nvidia_stack_t *, nv_state_t *); +void NV_API_CALL rm_execute_work_item (nvidia_stack_t *, void *); +const char* NV_API_CALL rm_get_device_name (NvU16, NvU16, NvU16); + +NV_STATUS NV_API_CALL rm_is_supported_device (nvidia_stack_t *, nv_state_t *); +NvBool NV_API_CALL rm_is_supported_pci_device(NvU8 pci_class, + NvU8 pci_subclass, + NvU16 vendor, + NvU16 device, + NvU16 subsystem_vendor, + NvU16 subsystem_device, + NvBool print_legacy_warning); + +void NV_API_CALL rm_i2c_remove_adapters (nvidia_stack_t *, nv_state_t *); +NvBool NV_API_CALL rm_i2c_is_smbus_capable (nvidia_stack_t *, nv_state_t *, void *); +NV_STATUS NV_API_CALL rm_i2c_transfer (nvidia_stack_t *, nv_state_t *, void *, nv_i2c_cmd_t, NvU8, NvU8, NvU32, NvU8 *); + +NV_STATUS NV_API_CALL rm_perform_version_check (nvidia_stack_t *, void *, NvU32); + +void NV_API_CALL rm_power_source_change_event (nvidia_stack_t *, NvU32); + +void NV_API_CALL rm_request_dnotifier_state (nvidia_stack_t *, nv_state_t *); + +void NV_API_CALL rm_disable_gpu_state_persistence (nvidia_stack_t *sp, nv_state_t *); +NV_STATUS NV_API_CALL rm_p2p_init_mapping (nvidia_stack_t *, NvU64, NvU64 *, NvU64 *, NvU64 *, NvU64 *, NvU64, NvU64, NvU64, NvU64, void (*)(void *), void *); +NV_STATUS NV_API_CALL rm_p2p_destroy_mapping (nvidia_stack_t *, NvU64); +NV_STATUS NV_API_CALL rm_p2p_get_pages (nvidia_stack_t *, NvU64, NvU32, NvU64, NvU64, NvU64 *, NvU32 *, NvU32 *, NvU32 *, NvU8 **, void *, NvBool *); +NV_STATUS NV_API_CALL rm_p2p_get_gpu_info (nvidia_stack_t *, NvU64, NvU64, NvU8 **, void **); +NV_STATUS NV_API_CALL rm_p2p_get_pages_persistent (nvidia_stack_t *, NvU64, NvU64, void **, NvU64 *, NvU32 *, NvBool, void *, void *, void **, NvBool *); +NV_STATUS NV_API_CALL rm_p2p_register_callback (nvidia_stack_t *, NvU64, NvU64, NvU64, void *, void (*)(void *), void *); +NV_STATUS NV_API_CALL rm_p2p_put_pages (nvidia_stack_t *, NvU64, NvU32, NvU64, void *); +NV_STATUS NV_API_CALL rm_p2p_put_pages_persistent(nvidia_stack_t *, void *, void *, void *); +NV_STATUS NV_API_CALL rm_p2p_dma_map_pages (nvidia_stack_t *, nv_dma_device_t *, NvU8 *, NvU64, NvU32, NvU64 *, void **); +NV_STATUS NV_API_CALL rm_dma_buf_dup_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, + NvHandle, void *, NvHandle, NvU64, NvU64, NvU8, NvHandle *, void **, + NvBool *, NvU32 *, NvBool *, nv_memory_type_t *); +void NV_API_CALL rm_dma_buf_undup_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle); +NV_STATUS NV_API_CALL rm_dma_buf_map_mem_handle (nvidia_stack_t *, nv_state_t *, + NvHandle, NvHandle, MemoryRange, + NvU8, void *, NvBool, MemoryArea *); +void NV_API_CALL rm_dma_buf_unmap_mem_handle(nvidia_stack_t *, nv_state_t *, + NvHandle, NvHandle, NvU8, void *, + NvBool, MemoryArea); +NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device(nvidia_stack_t *, + nv_state_t *, NvHandle, NvHandle, + NvU8, NvHandle *, NvHandle *, + NvHandle *, void **, NvBool *, NvBool *); +void NV_API_CALL rm_dma_buf_put_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, void *); + +void NV_API_CALL rm_kernel_rmapi_op(nvidia_stack_t *sp, void *ops_cmd); +NvBool NV_API_CALL rm_get_device_remove_flag(nvidia_stack_t *sp, NvU32 gpu_id); +NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults(nvidia_stack_t *, nv_state_t *, NvU32 *); +NV_STATUS NV_API_CALL rm_gpu_handle_mmu_faults(nvidia_stack_t *, nv_state_t *, NvU32 *); +NvBool NV_API_CALL rm_is_chipset_io_coherent(nv_stack_t *); +NvBool NV_API_CALL rm_init_event_locks(nvidia_stack_t *, nv_state_t *); +void NV_API_CALL rm_destroy_event_locks(nvidia_stack_t *, nv_state_t *); +NV_STATUS NV_API_CALL rm_get_gpu_numa_info(nvidia_stack_t *, nv_state_t *, nv_ioctl_numa_info_t *); +NV_STATUS NV_API_CALL rm_gpu_numa_online(nvidia_stack_t *, nv_state_t *); +NV_STATUS NV_API_CALL rm_gpu_numa_offline(nvidia_stack_t *, nv_state_t *); +NvBool NV_API_CALL rm_is_device_sequestered(nvidia_stack_t *, nv_state_t *); +void NV_API_CALL rm_check_for_gpu_surprise_removal(nvidia_stack_t *, nv_state_t *); +NV_STATUS NV_API_CALL rm_set_external_kernel_client_count(nvidia_stack_t *, nv_state_t *, NvBool); +NV_STATUS NV_API_CALL rm_schedule_gpu_wakeup(nvidia_stack_t *, nv_state_t *); +NvBool NV_API_CALL rm_disable_iomap_wc(void); + +void NV_API_CALL rm_init_tegra_dynamic_power_management(nvidia_stack_t *, nv_state_t *); +void NV_API_CALL rm_init_dynamic_power_management(nvidia_stack_t *, nv_state_t *, NvBool); +void NV_API_CALL rm_cleanup_dynamic_power_management(nvidia_stack_t *, nv_state_t *); +void NV_API_CALL rm_enable_dynamic_power_management(nvidia_stack_t *, nv_state_t *); +NV_STATUS NV_API_CALL rm_ref_dynamic_power(nvidia_stack_t *, nv_state_t *, nv_dynamic_power_mode_t); +void NV_API_CALL rm_unref_dynamic_power(nvidia_stack_t *, nv_state_t *, nv_dynamic_power_mode_t); +NV_STATUS NV_API_CALL rm_transition_dynamic_power(nvidia_stack_t *, nv_state_t *, NvBool, NvBool *); +void NV_API_CALL rm_get_power_info(nvidia_stack_t *, nv_state_t *, nv_power_info_t *); + +void NV_API_CALL rm_acpi_notify(nvidia_stack_t *, nv_state_t *, NvU32); +void NV_API_CALL rm_acpi_nvpcf_notify(nvidia_stack_t *); + +NvBool NV_API_CALL rm_is_altstack_in_use(void); + +void NV_API_CALL rm_notify_gpu_addition(nvidia_stack_t *, nv_state_t *); +void NV_API_CALL rm_notify_gpu_removal(nvidia_stack_t *, nv_state_t *); + +/* vGPU VFIO specific functions */ +NV_STATUS NV_API_CALL nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU16 *, + NvU32 *, NvU32 *, NvU32); +NV_STATUS NV_API_CALL nv_vgpu_delete(nvidia_stack_t *, const NvU8 *, NvU16); +NV_STATUS NV_API_CALL nv_vgpu_get_type_ids(nvidia_stack_t *, nv_state_t *, NvU32 *, NvU32 *, NvBool, NvU8, NvBool); +NV_STATUS NV_API_CALL nv_vgpu_get_type_info(nvidia_stack_t *, nv_state_t *, NvU32, char *, int, NvU8); +NV_STATUS NV_API_CALL nv_vgpu_get_bar_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *, + NvU64 *, NvU64 *, NvU32 *, NvBool *, NvU8 *); +NV_STATUS NV_API_CALL nv_vgpu_update_sysfs_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU32 *); +NV_STATUS NV_API_CALL nv_vgpu_get_hbm_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *, NvU64 *); +NV_STATUS NV_API_CALL nv_vgpu_process_vf_info(nvidia_stack_t *, nv_state_t *, NvU8, NvU32, NvU8, NvU8, NvU8, NvBool, void *); +NV_STATUS NV_API_CALL nv_gpu_bind_event(nvidia_stack_t *, NvU32, NvBool *); +NV_STATUS NV_API_CALL nv_gpu_unbind_event(nvidia_stack_t *, NvU32, NvBool *); + +nv_soc_irq_type_t NV_API_CALL nv_get_current_irq_type(nv_state_t*); +void NV_API_CALL nv_flush_coherent_cpu_cache_range(nv_state_t *nv, NvU64 cpu_virtual, NvU64 size); + +/* Callbacks should occur roughly every 10ms. */ +#define NV_SNAPSHOT_TIMER_HZ 100 +void NV_API_CALL nv_start_snapshot_timer(void (*snapshot_callback)(void *context)); +void NV_API_CALL nv_flush_snapshot_timer(void); +void NV_API_CALL nv_stop_snapshot_timer(void); + +static inline const NvU8 *nv_get_cached_uuid(nv_state_t *nv) +{ + return nv->nv_uuid_cache.valid ? nv->nv_uuid_cache.uuid : NULL; +} + +/* nano second resolution timer callback structure */ +typedef struct nv_nano_timer nv_nano_timer_t; + +/* nano timer functions */ +void NV_API_CALL nv_create_nano_timer(nv_state_t *, void *pTmrEvent, nv_nano_timer_t **); +void NV_API_CALL nv_start_nano_timer(nv_state_t *nv, nv_nano_timer_t *, NvU64 timens); +NV_STATUS NV_API_CALL rm_run_nano_timer_callback(nvidia_stack_t *, nv_state_t *, void *pTmrEvent); +void NV_API_CALL nv_cancel_nano_timer(nv_state_t *, nv_nano_timer_t *); +void NV_API_CALL nv_destroy_nano_timer(nv_state_t *nv, nv_nano_timer_t *); + +// Host1x specific functions. +NV_STATUS NV_API_CALL nv_get_syncpoint_aperture(NvU32, NvU64 *, NvU64 *, NvU32 *); + +#if defined(NVCPU_X86_64) + +static inline NvU64 nv_rdtsc(void) +{ + NvU64 val; + __asm__ __volatile__ ("rdtsc \t\n" + "shlq $0x20,%%rdx \t\n" + "orq %%rdx,%%rax \t\n" + : "=A" (val)); + return val; +} + +#endif + +static inline NvBool nv_dev_needs_vidmem_preservation(const nv_state_t *nv) +{ + /* + * Tegra iGPUs and SoC display devices don't need vidmem preservation. + */ + return !nv->is_tegra_pci_igpu && !NV_IS_SOC_DISPLAY_DEVICE(nv); +} + +#endif /* NVRM */ + +static inline int nv_count_bits(NvU64 word) +{ + NvU64 bits; + + bits = (word & 0x5555555555555555ULL) + ((word >> 1) & 0x5555555555555555ULL); + bits = (bits & 0x3333333333333333ULL) + ((bits >> 2) & 0x3333333333333333ULL); + bits = (bits & 0x0f0f0f0f0f0f0f0fULL) + ((bits >> 4) & 0x0f0f0f0f0f0f0f0fULL); + bits = (bits & 0x00ff00ff00ff00ffULL) + ((bits >> 8) & 0x00ff00ff00ff00ffULL); + bits = (bits & 0x0000ffff0000ffffULL) + ((bits >> 16) & 0x0000ffff0000ffffULL); + bits = (bits & 0x00000000ffffffffULL) + ((bits >> 32) & 0x00000000ffffffffULL); + + return (int)(bits); +} + +#endif diff --git a/userspace/sdks/nv570/nvalloc/unix/include/nv_escape.h b/userspace/sdks/nv570/nvalloc/unix/include/nv_escape.h new file mode 100644 index 0000000..601d9de --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/nv_escape.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NV_ESCAPE_H_INCLUDED +#define NV_ESCAPE_H_INCLUDED + +/* + * NOTE: Any new ioctls added here should also be added to RmValidateIoctl() in escape.c + * or rm_validate_ioctls() in osapi.c + */ +#define NV_ESC_RM_ALLOC_MEMORY 0x27 +#define NV_ESC_RM_ALLOC_OBJECT 0x28 +#define NV_ESC_RM_FREE 0x29 +#define NV_ESC_RM_CONTROL 0x2A +#define NV_ESC_RM_ALLOC 0x2B +#define NV_ESC_RM_DUP_OBJECT 0x34 +#define NV_ESC_RM_SHARE 0x35 +#define NV_ESC_RM_I2C_ACCESS 0x39 +#define NV_ESC_RM_IDLE_CHANNELS 0x41 +#define NV_ESC_RM_VID_HEAP_CONTROL 0x4A +#define NV_ESC_RM_ACCESS_REGISTRY 0x4D +#define NV_ESC_RM_MAP_MEMORY 0x4E +#define NV_ESC_RM_UNMAP_MEMORY 0x4F +#define NV_ESC_RM_GET_EVENT_DATA 0x52 +#define NV_ESC_RM_ALLOC_CONTEXT_DMA2 0x54 +#define NV_ESC_RM_ADD_VBLANK_CALLBACK 0x56 +#define NV_ESC_RM_MAP_MEMORY_DMA 0x57 +#define NV_ESC_RM_UNMAP_MEMORY_DMA 0x58 +#define NV_ESC_RM_BIND_CONTEXT_DMA 0x59 +#define NV_ESC_RM_EXPORT_OBJECT_TO_FD 0x5C +#define NV_ESC_RM_IMPORT_OBJECT_FROM_FD 0x5D +#define NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO 0x5E +#define NV_ESC_RM_LOCKLESS_DIAGNOSTIC 0x5F + +#endif // NV_ESCAPE_H_INCLUDED diff --git a/userspace/sdks/nv570/nvalloc/unix/include/os-interface.h b/userspace/sdks/nv570/nvalloc/unix/include/os-interface.h new file mode 100644 index 0000000..2a80c50 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/os-interface.h @@ -0,0 +1,298 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/* + * Os interface definitions needed by os-interface.c + */ + +#ifndef OS_INTERFACE_H +#define OS_INTERFACE_H + +/******************* Operating System Interface Routines *******************\ +* * +* Operating system wrapper functions used to abstract the OS. * +* * +\***************************************************************************/ + +#include +#include +#include "nv_stdarg.h" +#include +#include +#include +#include + +#include "rs_access.h" + + + +typedef struct +{ + NvU32 os_major_version; + NvU32 os_minor_version; + NvU32 os_build_number; + const char * os_build_version_str; + const char * os_build_date_plus_str; +}os_version_info; + +/* Each OS defines its own version of this opaque type */ +struct os_work_queue; + +/* Each OS defines its own version of this opaque type */ +typedef struct os_wait_queue os_wait_queue; + +/* Flags needed by os_get_current_proccess_flags */ +#define OS_CURRENT_PROCESS_FLAG_NONE 0x0 +#define OS_CURRENT_PROCESS_FLAG_KERNEL_THREAD 0x1 +#define OS_CURRENT_PROCESS_FLAG_EXITING 0x2 + +/* + * --------------------------------------------------------------------------- + * + * Function prototypes for OS interface. + * + * --------------------------------------------------------------------------- + */ + +NV_STATUS NV_API_CALL os_alloc_mem (void **, NvU64); +void NV_API_CALL os_free_mem (void *); +NV_STATUS NV_API_CALL os_get_system_time (NvU32 *, NvU32 *); +NvU64 NV_API_CALL os_get_monotonic_time_ns (void); +NvU64 NV_API_CALL os_get_monotonic_time_ns_hr (void); +NvU64 NV_API_CALL os_get_monotonic_tick_resolution_ns (void); +NV_STATUS NV_API_CALL os_delay (NvU32); +NV_STATUS NV_API_CALL os_delay_us (NvU32); +NvU64 NV_API_CALL os_get_cpu_frequency (void); +NvU32 NV_API_CALL os_get_current_process (void); +void NV_API_CALL os_get_current_process_name (char *, NvU32); +NV_STATUS NV_API_CALL os_get_current_thread (NvU64 *); +char* NV_API_CALL os_string_copy (char *, const char *); +NvU32 NV_API_CALL os_string_length (const char *); +NvU32 NV_API_CALL os_strtoul (const char *, char **, NvU32); +NvS32 NV_API_CALL os_string_compare (const char *, const char *); +NvS32 NV_API_CALL os_snprintf (char *, NvU32, const char *, ...); +NvS32 NV_API_CALL os_vsnprintf (char *, NvU32, const char *, va_list); +void NV_API_CALL os_log_error (const char *, va_list); +void* NV_API_CALL os_mem_copy (void *, const void *, NvU32); +NV_STATUS NV_API_CALL os_memcpy_from_user (void *, const void *, NvU32); +NV_STATUS NV_API_CALL os_memcpy_to_user (void *, const void *, NvU32); +void* NV_API_CALL os_mem_set (void *, NvU8, NvU32); +NvS32 NV_API_CALL os_mem_cmp (const NvU8 *, const NvU8 *, NvU32); +void* NV_API_CALL os_pci_init_handle (NvU32, NvU8, NvU8, NvU8, NvU16 *, NvU16 *); +NV_STATUS NV_API_CALL os_pci_read_byte (void *, NvU32, NvU8 *); +NV_STATUS NV_API_CALL os_pci_read_word (void *, NvU32, NvU16 *); +NV_STATUS NV_API_CALL os_pci_read_dword (void *, NvU32, NvU32 *); +NV_STATUS NV_API_CALL os_pci_write_byte (void *, NvU32, NvU8); +NV_STATUS NV_API_CALL os_pci_write_word (void *, NvU32, NvU16); +NV_STATUS NV_API_CALL os_pci_write_dword (void *, NvU32, NvU32); +NvBool NV_API_CALL os_pci_remove_supported (void); +void NV_API_CALL os_pci_remove (void *); +void* NV_API_CALL os_map_kernel_space (NvU64, NvU64, NvU32); +void NV_API_CALL os_unmap_kernel_space (void *, NvU64); +NV_STATUS NV_API_CALL os_flush_cpu_cache_all (void); +NV_STATUS NV_API_CALL os_flush_user_cache (void); +void NV_API_CALL os_flush_cpu_write_combine_buffer(void); +NvU8 NV_API_CALL os_io_read_byte (NvU32); +NvU16 NV_API_CALL os_io_read_word (NvU32); +NvU32 NV_API_CALL os_io_read_dword (NvU32); +void NV_API_CALL os_io_write_byte (NvU32, NvU8); +void NV_API_CALL os_io_write_word (NvU32, NvU16); +void NV_API_CALL os_io_write_dword (NvU32, NvU32); +NvBool NV_API_CALL os_is_administrator (void); +NvBool NV_API_CALL os_check_access (RsAccessRight accessRight); +void NV_API_CALL os_dbg_init (void); +void NV_API_CALL os_dbg_breakpoint (void); +void NV_API_CALL os_dbg_set_level (NvU32); +NvU32 NV_API_CALL os_get_cpu_count (void); +NvU32 NV_API_CALL os_get_cpu_number (void); +void NV_API_CALL os_disable_console_access (void); +void NV_API_CALL os_enable_console_access (void); +NV_STATUS NV_API_CALL os_registry_init (void); +NvU64 NV_API_CALL os_get_max_user_va (void); +NV_STATUS NV_API_CALL os_schedule (void); +NV_STATUS NV_API_CALL os_alloc_spinlock (void **); +void NV_API_CALL os_free_spinlock (void *); +NvU64 NV_API_CALL os_acquire_spinlock (void *); +void NV_API_CALL os_release_spinlock (void *, NvU64); +NV_STATUS NV_API_CALL os_queue_work_item (struct os_work_queue *, void *); +NV_STATUS NV_API_CALL os_flush_work_queue (struct os_work_queue *, NvBool); +NvBool NV_API_CALL os_is_queue_flush_ongoing (struct os_work_queue *); +NV_STATUS NV_API_CALL os_alloc_mutex (void **); +void NV_API_CALL os_free_mutex (void *); +NV_STATUS NV_API_CALL os_acquire_mutex (void *); +NV_STATUS NV_API_CALL os_cond_acquire_mutex (void *); +void NV_API_CALL os_release_mutex (void *); +void* NV_API_CALL os_alloc_semaphore (NvU32); +void NV_API_CALL os_free_semaphore (void *); +NV_STATUS NV_API_CALL os_acquire_semaphore (void *); +NV_STATUS NV_API_CALL os_cond_acquire_semaphore (void *); +NV_STATUS NV_API_CALL os_release_semaphore (void *); +void* NV_API_CALL os_alloc_rwlock (void); +void NV_API_CALL os_free_rwlock (void *); +NV_STATUS NV_API_CALL os_acquire_rwlock_read (void *); +NV_STATUS NV_API_CALL os_acquire_rwlock_write (void *); +NV_STATUS NV_API_CALL os_cond_acquire_rwlock_read (void *); +NV_STATUS NV_API_CALL os_cond_acquire_rwlock_write (void *); +void NV_API_CALL os_release_rwlock_read (void *); +void NV_API_CALL os_release_rwlock_write (void *); +NvBool NV_API_CALL os_semaphore_may_sleep (void); +NV_STATUS NV_API_CALL os_get_version_info (os_version_info*); +NV_STATUS NV_API_CALL os_get_is_openrm (NvBool *); +NvBool NV_API_CALL os_is_bif_reset_supported (void *); +NvBool NV_API_CALL os_is_isr (void); +void NV_API_CALL os_dump_stack (void); +NvBool NV_API_CALL os_is_efi_enabled (void); +NvBool NV_API_CALL os_is_xen_dom0 (void); +NvBool NV_API_CALL os_is_vgx_hyper (void); +NV_STATUS NV_API_CALL os_inject_vgx_msi (NvU16, NvU64, NvU32); +NvBool NV_API_CALL os_is_grid_supported (void); +NvU32 NV_API_CALL os_get_grid_csp_support (void); +void NV_API_CALL os_bug_check (NvU32, const char *); +NV_STATUS NV_API_CALL os_lock_user_pages (void *, NvU64, void **, NvU32); +NV_STATUS NV_API_CALL os_lookup_user_io_memory (void *, NvU64, NvU64 **); +NV_STATUS NV_API_CALL os_unlock_user_pages (NvU64, void *, NvU32); +NV_STATUS NV_API_CALL os_match_mmap_offset (void *, NvU64, NvU64 *); +NV_STATUS NV_API_CALL os_get_euid (NvU32 *); +NV_STATUS NV_API_CALL os_get_smbios_header (NvU64 *pSmbsAddr); +NV_STATUS NV_API_CALL os_get_acpi_rsdp_from_uefi (NvU32 *); +void NV_API_CALL os_add_record_for_crashLog (void *, NvU32); +void NV_API_CALL os_delete_record_for_crashLog (void *); +NV_STATUS NV_API_CALL os_call_vgpu_vfio (void *, NvU32); +NV_STATUS NV_API_CALL os_device_vm_present (void); +NV_STATUS NV_API_CALL os_numa_memblock_size (NvU64 *); +NV_STATUS NV_API_CALL os_alloc_pages_node (NvS32, NvU32, NvU32, NvU64 *); +NV_STATUS NV_API_CALL os_get_page (NvU64 address); +NV_STATUS NV_API_CALL os_put_page (NvU64 address); +NvU32 NV_API_CALL os_get_page_refcount (NvU64 address); +NvU32 NV_API_CALL os_count_tail_pages (NvU64 address); +void NV_API_CALL os_free_pages_phys (NvU64, NvU32); +NV_STATUS NV_API_CALL os_open_temporary_file (void **); +void NV_API_CALL os_close_file (void *); +NV_STATUS NV_API_CALL os_write_file (void *, NvU8 *, NvU64, NvU64); +NV_STATUS NV_API_CALL os_read_file (void *, NvU8 *, NvU64, NvU64); +NV_STATUS NV_API_CALL os_open_readonly_file (const char *, void **); +NV_STATUS NV_API_CALL os_open_and_read_file (const char *, NvU8 *, NvU64); +NvBool NV_API_CALL os_is_nvswitch_present (void); +NV_STATUS NV_API_CALL os_get_random_bytes (NvU8 *, NvU16); +NvU32 NV_API_CALL os_get_current_process_flags (void); +NV_STATUS NV_API_CALL os_alloc_wait_queue (os_wait_queue **); +void NV_API_CALL os_free_wait_queue (os_wait_queue *); +void NV_API_CALL os_wait_uninterruptible (os_wait_queue *); +void NV_API_CALL os_wait_interruptible (os_wait_queue *); +void NV_API_CALL os_wake_up (os_wait_queue *); +nv_cap_t* NV_API_CALL os_nv_cap_init (const char *); +nv_cap_t* NV_API_CALL os_nv_cap_create_dir_entry (nv_cap_t *, const char *, int); +nv_cap_t* NV_API_CALL os_nv_cap_create_file_entry (nv_cap_t *, const char *, int); +void NV_API_CALL os_nv_cap_destroy_entry (nv_cap_t *); +int NV_API_CALL os_nv_cap_validate_and_dup_fd (const nv_cap_t *, int); +void NV_API_CALL os_nv_cap_close_fd (int); +NvS32 NV_API_CALL os_imex_channel_get (NvU64); +NvS32 NV_API_CALL os_imex_channel_count (void); +NV_STATUS NV_API_CALL os_tegra_igpu_perf_boost (void *, NvBool, NvU32); + +NV_STATUS NV_API_CALL os_get_tegra_platform (NvU32 *); +enum os_pci_req_atomics_type { + OS_INTF_PCIE_REQ_ATOMICS_32BIT, + OS_INTF_PCIE_REQ_ATOMICS_64BIT, + OS_INTF_PCIE_REQ_ATOMICS_128BIT +}; +NV_STATUS NV_API_CALL os_enable_pci_req_atomics (void *, enum os_pci_req_atomics_type); +void NV_API_CALL os_pci_trigger_flr(void *handle); +NV_STATUS NV_API_CALL os_get_numa_node_memory_usage (NvS32, NvU64 *, NvU64 *); +NV_STATUS NV_API_CALL os_numa_add_gpu_memory (void *, NvU64, NvU64, NvU32 *); +NV_STATUS NV_API_CALL os_numa_remove_gpu_memory (void *, NvU64, NvU64, NvU32); +NV_STATUS NV_API_CALL os_offline_page_at_address(NvU64 address); +void* NV_API_CALL os_get_pid_info(void); +void NV_API_CALL os_put_pid_info(void *pid_info); +NV_STATUS NV_API_CALL os_find_ns_pid(void *pid_info, NvU32 *ns_pid); +NvBool NV_API_CALL os_is_init_ns(void); +NV_STATUS NV_API_CALL os_iommu_sva_bind(void *arg, void **handle, NvU32 *pasid); +void NV_API_CALL os_iommu_sva_unbind(void *handle); +NvBool NV_API_CALL os_supports_kernel_suspend_notifiers(void); + +extern NvU64 os_page_size; +extern NvU64 os_max_page_size; +extern NvU64 os_page_mask; +extern NvU8 os_page_shift; +extern NvBool os_cc_enabled; +extern NvBool os_cc_sev_snp_enabled; +extern NvBool os_cc_sme_enabled; +extern NvBool os_cc_snp_vtom_enabled; +extern NvBool os_cc_tdx_enabled; +extern NvBool os_dma_buf_enabled; +extern NvBool os_imex_channel_is_supported; + +/* + * --------------------------------------------------------------------------- + * + * Debug macros. + * + * --------------------------------------------------------------------------- + */ + +#define NV_DBG_INFO 0x0 +#define NV_DBG_SETUP 0x1 +#define NV_DBG_USERERRORS 0x2 +#define NV_DBG_WARNINGS 0x3 +#define NV_DBG_ERRORS 0x4 + + +void NV_API_CALL out_string(const char *str); +int NV_API_CALL nv_printf(NvU32 debuglevel, const char *printf_format, ...); + +#define NV_DEV_PRINTF(debuglevel, nv, format, ... ) \ + nv_printf(debuglevel, "NVRM: GPU " NV_PCI_DEV_FMT ": " format, NV_PCI_DEV_FMT_ARGS(nv), ## __VA_ARGS__) + +#define NV_DEV_PRINTF_STATUS(debuglevel, nv, status, format, ... ) \ + nv_printf(debuglevel, "NVRM: GPU " NV_PCI_DEV_FMT ": " format " (0x%x)\n", NV_PCI_DEV_FMT_ARGS(nv), ## __VA_ARGS__, status) + +/* + * Fields for os_lock_user_pages flags parameter + */ +#define NV_LOCK_USER_PAGES_FLAGS_WRITE 0:0 +#define NV_LOCK_USER_PAGES_FLAGS_WRITE_NO 0x00000000 +#define NV_LOCK_USER_PAGES_FLAGS_WRITE_YES 0x00000001 + +// NV OS Tegra platform type defines +#define NV_OS_TEGRA_PLATFORM_SIM 0 +#define NV_OS_TEGRA_PLATFORM_FPGA 1 +#define NV_OS_TEGRA_PLATFORM_SILICON 2 + +/* + * Plumbing through cgroup dmem api + */ +#define OS_CGROUP_IMPL_NONE 0 +#define OS_CGROUP_IMPL_MISC 1 +#define OS_CGROUP_IMPL_DMEM 2 +NvU32 NV_API_CALL os_cgroup_implementation(void); +void* NV_API_CALL os_dmem_cgroup_register_region(NvU64 size, const char *name); +void NV_API_CALL os_dmem_cgroup_unregister_region(void *region); +NV_STATUS NV_API_CALL os_dmem_cgroup_try_charge(void *region, NvU64 size, void **ret_pool, void **ret_limit_pool); +void NV_API_CALL os_dmem_cgroup_uncharge(void *pool, NvU64 size); + +void* NV_API_CALL os_cgroup_for_pid(int pid, void *pidInfo); +void* NV_API_CALL os_cgroup_get_from_fd(NvU32 fd); +void NV_API_CALL os_cgroup_put(void *cgroup); + +#endif /* OS_INTERFACE_H */ diff --git a/userspace/sdks/nv570/nvalloc/unix/include/os_custom.h b/userspace/sdks/nv570/nvalloc/unix/include/os_custom.h new file mode 100644 index 0000000..1effaf7 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/os_custom.h @@ -0,0 +1,60 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _OS_CUSTOM_H_ +#define _OS_CUSTOM_H_ + +/*! + * @file os_custom.h + * @brief OS module specific definitions for this OS + */ + +#include + +// File modes, added for NVIDIA capabilities. +#define OS_RUSR 00400 // read permission, owner +#define OS_WUSR 00200 // write permission, owner +#define OS_XUSR 00100 // execute/search permission, owner +#define OS_RWXU (OS_RUSR | OS_WUSR | OS_XUSR) // read, write, execute/search, owner +#define OS_RGRP 00040 // read permission, group +#define OS_WGRP 00020 // write permission, group +#define OS_XGRP 00010 // execute/search permission, group +#define OS_RWXG (OS_RGRP | OS_WGRP | OS_XGRP) // read, write, execute/search, group +#define OS_ROTH 00004 // read permission, other +#define OS_WOTH 00002 // write permission, other +#define OS_XOTH 00001 // execute/search permission, other +#define OS_RWXO (OS_ROTH | OS_WOTH | OS_XOTH) // read, write, execute/search, other +#define OS_RUGO (OS_RUSR | OS_RGRP | OS_ROTH) +#define OS_WUGO (OS_WUSR | OS_WGRP | OS_WOTH) +#define OS_XUGO (OS_XUSR | OS_XGRP | OS_XOTH) + +// Trigger for collecting GPU state for later extraction. +void RmLogGpuCrash(OBJGPU *); + +// This is callback function in the miniport. +// The argument is a device extension, and must be cast as such to be useful. +typedef void (*MINIPORT_CALLBACK)(void*); + +NV_STATUS osPackageRegistry(OBJGPU *pGpu, PACKED_REGISTRY_TABLE *, NvU32 *); + +#endif // _OS_CUSTOM_H_ diff --git a/userspace/sdks/nv570/nvalloc/unix/include/osapi.h b/userspace/sdks/nv570/nvalloc/unix/include/osapi.h new file mode 100644 index 0000000..6402bdb --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/osapi.h @@ -0,0 +1,203 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _OSAPI_H_ +#define _OSAPI_H_ + +#include "core/system.h" +#include "gpu/gpu.h" + +#include // NV_DBG_ERRORS +#include +#include + +#if defined(__use_altstack__) +#if defined(QA_BUILD) +//--------------------------------------------------------------------------- +// +// 32 bit debug marker values. +// +//--------------------------------------------------------------------------- + +#define NV_MARKER1 (NvU32)(('M' << 24) | ('R' << 16) | ('V' << 8) | 'N') +#define NV_MARKER2 (NvU32)(('N' << 24) | ('V' << 16) | ('R' << 8) | 'M') + +// +// The two macros below implement a simple alternate stack usage sanity +// check for QA_BUILD RM builds. NV_ALTSTACK_WRITE_MARKERS() fills +// altstacks with NV_MARKER1, which enables NV_ALTSTACK_CHECK_MARKERS() +// to determine the stack usage fairly reliably by looking for the +// first clobbered marker. If more than 7/8 of the alternate stack were +// used, NV_ALTSTACK_CHECK_MARKERS() prints an error and asserts. +// +#define NV_ALTSTACK_WRITE_MARKERS(sp) \ +{ \ + NvU32 i, *stack = (void *)(sp)->stack; \ + for (i = 0; i < ((sp)->size / sizeof(NvU32)); i++) \ + stack[i] = NV_MARKER1; \ +} + +#define NV_ALTSTACK_CHECK_MARKERS(sp) \ +{ \ + NvU32 i, *stack = (void *)(sp)->stack; \ + for (i = 0; i < ((sp)->size / sizeof(NvU32)); i++) \ + { \ + if (stack[i] != NV_MARKER1) \ + break; \ + } \ + if ((i * sizeof(NvU32)) < ((sp)->size / 8)) \ + { \ + nv_printf(NV_DBG_ERRORS, "NVRM: altstack: used %d of %d bytes!\n", \ + ((sp)->size - (i * (NvU32)sizeof(NvU32))), (sp)->size); \ + NV_ASSERT_PRECOMP((i * sizeof(NvU32)) >= ((sp)->size / 8)); \ + } \ +} +#else +#define NV_ALTSTACK_WRITE_MARKERS(sp) +#define NV_ALTSTACK_CHECK_MARKERS(sp) +#endif +#if defined(NVCPU_X86_64) +#define NV_ENTER_RM_RUNTIME(sp,fp) \ +{ \ + NV_ALTSTACK_WRITE_MARKERS(sp); \ + __asm__ __volatile__ ("movq %%rbp,%0" : "=r" (fp)); /* save %rbp */ \ + __asm__ __volatile__ ("movq %0,%%rbp" :: "r" ((sp)->top)); \ +} + +#define NV_EXIT_RM_RUNTIME(sp,fp) \ +{ \ + register void *__rbp __asm__ ("rbp"); \ + if (__rbp != (sp)->top) \ + { \ + nv_printf(NV_DBG_ERRORS, "NVRM: detected corrupted runtime stack!\n"); \ + NV_ASSERT_PRECOMP(__rbp == (sp)->top); \ + } \ + NV_ALTSTACK_CHECK_MARKERS(sp); \ + __asm__ __volatile__ ("movq %0,%%rbp" :: "r" (fp)); /* restore %rbp */ \ +} +#else +#error "gcc \"altstacks\" support is not implemented on this platform!" +#endif +#else +#define NV_ENTER_RM_RUNTIME(sp,fp) { (void)sp; (void)fp; } +#define NV_EXIT_RM_RUNTIME(sp,fp) +#endif + +void RmShutdownRm (void); + +NvBool RmInitPrivateState (nv_state_t *); +void RmFreePrivateState (nv_state_t *); + +NvBool RmInitAdapter (nv_state_t *); +NvBool RmPartiallyInitAdapter (nv_state_t *); +void RmShutdownAdapter (nv_state_t *); +void RmDisableAdapter (nv_state_t *); +void RmPartiallyDisableAdapter(nv_state_t *); +NV_STATUS RmGetAdapterStatus (nv_state_t *, NvU32 *); +NV_STATUS RmExcludeAdapter (nv_state_t *); + +NvBool RmGpuHasIOSpaceEnabled (nv_state_t *); + +void RmFreeUnusedClients (nv_state_t *, nv_file_private_t *); +NV_STATUS RmIoctl (nv_state_t *, nv_file_private_t *, NvU32, void *, NvU32); +NV_STATUS RmValidateIoctl (NvU32, NvU32); + +void RmI2cAddGpuPorts(nv_state_t *); + +NV_STATUS RmInitX86EmuState(OBJGPU *); +void RmFreeX86EmuState(OBJGPU *); +NV_STATUS RmPowerSourceChangeEvent(nv_state_t *, NvU32); + +void RmRequestDNotifierState(nv_state_t *); + +const NvU8 *RmGetGpuUuidRaw(nv_state_t *); + +NV_STATUS nv_vbios_call(OBJGPU *, NvU32 *, NvU32 *); + +int amd_adv_spec_cache_feature(OBJOS *); +int amd_msr_c0011022_incompatible(OBJOS *); + +NV_STATUS rm_get_adapter_status (nv_state_t *, NvU32 *); + +void rm_client_free_os_events (NvHandle); + +NV_STATUS rm_create_mmap_context (NvHandle, NvHandle, NvHandle, NvP64, NvU64, NvU64, NvU32, NvU32); +NV_STATUS rm_update_device_mapping_info (NvHandle, NvHandle, NvHandle, void *, void *); + +NV_STATUS rm_access_registry (NvHandle, NvHandle, NvU32, NvP64, NvU32, NvP64, NvU32, NvP64, NvU32 *, NvU32 *, NvU32 *); + +// registry management +NV_STATUS RmInitRegistry (void); +NV_STATUS RmDestroyRegistry (nv_state_t *); + +NV_STATUS RmWriteRegistryDword (nv_state_t *, const char *, NvU32 ); +NV_STATUS RmReadRegistryDword (nv_state_t *, const char *, NvU32 *); +NV_STATUS RmWriteRegistryString (nv_state_t *, const char *, const char *, NvU32); +NV_STATUS RmReadRegistryBinary (nv_state_t *, const char *, NvU8 *, NvU32 *); +NV_STATUS RmWriteRegistryBinary (nv_state_t *, const char *, NvU8 *, NvU32); +NV_STATUS RmReadRegistryString (nv_state_t *, const char *, NvU8 *, NvU32 *); + +NV_STATUS RmPackageRegistry (nv_state_t *, PACKED_REGISTRY_TABLE *, NvU32 *); + +NvBool RmIsNvifFunctionSupported(NvU32, NvU32); +void RmInitAcpiMethods (OBJOS *, OBJSYS *, OBJGPU *); +void RmUnInitAcpiMethods (OBJSYS *); + +void RmInflateOsToRmPageArray (RmPhysAddr *, NvU64); +void RmDeflateRmToOsPageArray (RmPhysAddr *, NvU64); + +void convertPageArrayBetweenOsAndRm( + RmPhysAddr *pteArray, + NvU64 pageCountFrom, + NvU64 pageSizeFrom, + NvU64 pageCountTo, + NvU64 pageSizeTo, + NvU64 *newPageCountTo); + +#define IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc) \ + (SYS_GET_INSTANCE()->bEnableDynamicGranularityPageArrays && !memdescGetContiguity(pMemDesc, AT_CPU)) + +void RmInitPowerManagement (nv_state_t *); +void RmDestroyPowerManagement (nv_state_t *); + +NV_STATUS RmPowerManagementTegra (OBJGPU *pGpu, nv_pm_action_t pmAction); + +NV_STATUS os_ref_dynamic_power (nv_state_t *, nv_dynamic_power_mode_t); +void os_unref_dynamic_power (nv_state_t *, nv_dynamic_power_mode_t); +void RmHandleDisplayChange (nvidia_stack_t *, nv_state_t *); +void RmUpdateGc6ConsoleRefCount (nv_state_t *, NvBool); + +NvBool rm_get_uefi_console_status (nv_state_t *); +NvU64 rm_get_uefi_console_size (nv_state_t *, NvU64 *); + +void rm_check_s0ix_regkey_and_platform_support(void); + +RM_API *RmUnixRmApiPrologue (nv_state_t *, THREAD_STATE_NODE *, NvU32 module); +void RmUnixRmApiEpilogue (nv_state_t *, THREAD_STATE_NODE *); + +static inline NvBool rm_is_system_notebook(void) +{ + return (nv_is_chassis_notebook() || nv_acpi_is_battery_present()); +} + +#endif // _OSAPI_H_ diff --git a/userspace/sdks/nv570/nvalloc/unix/include/rmobjexportimport.h b/userspace/sdks/nv570/nvalloc/unix/include/rmobjexportimport.h new file mode 100644 index 0000000..a070c4e --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/rmobjexportimport.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _RMOBJEXPORTIMPORT_H_ +#define _RMOBJEXPORTIMPORT_H_ + +#include "nvstatus.h" + +typedef NvHandle RmObjExportHandle; + +NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject, + RmObjExportHandle *pDstObject, NvU32 *pDeviceInstance); + +void RmFreeObjExportHandle(RmObjExportHandle hObject); + +NV_STATUS RmImportObject(NvHandle hDstClient, NvHandle hDstParent, + NvHandle *phDstObject, RmObjExportHandle hSrcObject, + NvU8 *pObjectType); +#endif // _RMOBJEXPORTIMPORT_H_ + diff --git a/userspace/sdks/nv570/nvalloc/unix/include/x86emu/debug.h b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/debug.h new file mode 100644 index 0000000..6a37dfa --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/debug.h @@ -0,0 +1,211 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for debug definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_DEBUG_H +#define __X86EMU_DEBUG_H + +/*---------------------- Macros and type definitions ----------------------*/ + +/* checks to be enabled for "runtime" */ + +#define CHECK_IP_FETCH_F 0x1 +#define CHECK_SP_ACCESS_F 0x2 +#define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */ +#define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset*/ + +#ifdef X86EMU_DEBUG +# define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F) +# define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F) +# define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F) +# define CHECK_DATA_ACCESS() (M.x86.check & CHECK_DATA_ACCESS_F) +#else +# define CHECK_IP_FETCH() 0 +# define CHECK_SP_ACCESS() 0 +# define CHECK_MEM_ACCESS() 0 +# define CHECK_DATA_ACCESS() 0 +#endif + +#ifdef X86EMU_DEBUG +# define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F) +# define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F) +# define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F) +# define DEBUG_STEP() (M.x86.debug & DEBUG_STEP_F) +# define DEBUG_DISASSEMBLE() (M.x86.debug & DEBUG_DISASSEMBLE_F) +# define DEBUG_BREAK() (M.x86.debug & DEBUG_BREAK_F) +# define DEBUG_SVC() (M.x86.debug & DEBUG_SVC_F) +# define DEBUG_SAVE_IP_CS() (M.x86.debug & DEBUG_SAVE_IP_CS_F) + +# define DEBUG_FS() (M.x86.debug & DEBUG_FS_F) +# define DEBUG_PROC() (M.x86.debug & DEBUG_PROC_F) +# define DEBUG_SYSINT() (M.x86.debug & DEBUG_SYSINT_F) +# define DEBUG_TRACECALL() (M.x86.debug & DEBUG_TRACECALL_F) +# define DEBUG_TRACECALLREGS() (M.x86.debug & DEBUG_TRACECALL_REGS_F) +# define DEBUG_SYS() (M.x86.debug & DEBUG_SYS_F) +# define DEBUG_MEM_TRACE() (M.x86.debug & DEBUG_MEM_TRACE_F) +# define DEBUG_IO_TRACE() (M.x86.debug & DEBUG_IO_TRACE_F) +# define DEBUG_DECODE_NOPRINT() (M.x86.debug & DEBUG_DECODE_NOPRINT_F) +#else +# define DEBUG_INSTRUMENT() 0 +# define DEBUG_DECODE() 0 +# define DEBUG_TRACE() 0 +# define DEBUG_STEP() 0 +# define DEBUG_DISASSEMBLE() 0 +# define DEBUG_BREAK() 0 +# define DEBUG_SVC() 0 +# define DEBUG_SAVE_IP_CS() 0 +# define DEBUG_FS() 0 +# define DEBUG_PROC() 0 +# define DEBUG_SYSINT() 0 +# define DEBUG_TRACECALL() 0 +# define DEBUG_TRACECALLREGS() 0 +# define DEBUG_SYS() 0 +# define DEBUG_MEM_TRACE() 0 +# define DEBUG_IO_TRACE() 0 +# define DEBUG_DECODE_NOPRINT() 0 +#endif + +#ifdef X86EMU_DEBUG + +# define DECODE_PRINTF(x) if (DEBUG_DECODE()) \ + x86emu_decode_printf(x) +# define DECODE_PRINTF2(x,y) if (DEBUG_DECODE()) \ + x86emu_decode_printf2(x,y) + +/* + * The following allow us to look at the bytes of an instruction. The + * first INCR_INSTRN_LEN, is called everytime bytes are consumed in + * the decoding process. The SAVE_IP_CS is called initially when the + * major opcode of the instruction is accessed. + */ +#define INC_DECODED_INST_LEN(x) \ + if (DEBUG_DECODE()) \ + x86emu_inc_decoded_inst_len(x) + +#define SAVE_IP_CS(x,y) \ + if (DEBUG_DECODE() | DEBUG_TRACECALL() | DEBUG_BREAK() \ + | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \ + M.x86.saved_cs = x; \ + M.x86.saved_ip = y; \ + } +#else +# define INC_DECODED_INST_LEN(x) +# define DECODE_PRINTF(x) +# define DECODE_PRINTF2(x,y) +# define SAVE_IP_CS(x,y) +#endif + +#ifdef X86EMU_DEBUG +#define TRACE_REGS() \ + if (DEBUG_DISASSEMBLE()) { \ + x86emu_just_disassemble(); \ + goto EndOfTheInstructionProcedure; \ + } \ + if (DEBUG_TRACE() || DEBUG_DECODE()) X86EMU_trace_regs() +#else +# define TRACE_REGS() +#endif + +#ifdef X86EMU_DEBUG +# define SINGLE_STEP() if (DEBUG_STEP()) x86emu_single_step() +#else +# define SINGLE_STEP() +#endif + +#define TRACE_AND_STEP() \ + TRACE_REGS(); \ + SINGLE_STEP() + +#ifdef X86EMU_DEBUG +# define START_OF_INSTR() +# define END_OF_INSTR() EndOfTheInstructionProcedure: x86emu_end_instr(); +# define END_OF_INSTR_NO_TRACE() x86emu_end_instr(); +#else +# define START_OF_INSTR() +# define END_OF_INSTR() +# define END_OF_INSTR_NO_TRACE() +#endif + +#ifdef X86EMU_DEBUG +#include +# define CALL_TRACE(u,v,w,x,s) \ + if (DEBUG_TRACECALLREGS()) \ + x86emu_dump_regs(); \ + if (DEBUG_TRACECALL()) \ + NV_PRINTF(LEVEL_INFO, "%04x:%04x: CALL %s%04x:%04x\n", u , v, s, w, x); +# define RETURN_TRACE(n,u,v) \ + if (DEBUG_TRACECALLREGS()) \ + x86emu_dump_regs(); \ + if (DEBUG_TRACECALL()) \ + NV_PRINTF(LEVEL_INFO, "%04x:%04x: %s\n",u,v,n); +#else +# define CALL_TRACE(u,v,w,x,s) +# define RETURN_TRACE(n,u,v) +#endif + +#ifdef X86EMU_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +extern void x86emu_inc_decoded_inst_len (int x); +extern void x86emu_decode_printf (const char *x); +extern void x86emu_decode_printf2 (const char *x, int y); +extern void x86emu_just_disassemble (void); +extern void x86emu_single_step (void); +extern void x86emu_end_instr (void); +extern void x86emu_dump_regs (void); +extern void x86emu_dump_xregs (void); +extern void x86emu_print_int_vect (u16 iv); +extern void x86emu_instrument_instruction (void); +extern void x86emu_check_ip_access (void); +extern void x86emu_check_sp_access (void); +extern void x86emu_check_mem_access (u32 p); +extern void x86emu_check_data_access (uint s, uint o); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_DEBUG_H */ diff --git a/userspace/sdks/nv570/nvalloc/unix/include/x86emu/decode.h b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/decode.h new file mode 100644 index 0000000..52eff18 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/decode.h @@ -0,0 +1,88 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for instruction decoding logic. +* +****************************************************************************/ + +#ifndef __X86EMU_DECODE_H +#define __X86EMU_DECODE_H + +/*---------------------- Macros and type definitions ----------------------*/ + +/* Instruction Decoding Stuff */ + +#define FETCH_DECODE_MODRM(mod,rh,rl) fetch_decode_modrm(&mod,&rh,&rl) +#define DECODE_RM_BYTE_REGISTER(r) decode_rm_byte_register(r) +#define DECODE_RM_WORD_REGISTER(r) decode_rm_word_register(r) +#define DECODE_RM_LONG_REGISTER(r) decode_rm_long_register(r) +#define DECODE_CLEAR_SEGOVR() M.x86.mode &= ~SYSMODE_CLRMASK + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +void x86emu_intr_raise (u8 type); +void fetch_decode_modrm (int *mod,int *regh,int *regl); +u8 fetch_byte_imm (void); +u16 fetch_word_imm (void); +u32 fetch_long_imm (void); +u8 fetch_data_byte (uint offset); +u8 fetch_data_byte_abs (uint segment, uint offset); +u16 fetch_data_word (uint offset); +u16 fetch_data_word_abs (uint segment, uint offset); +u32 fetch_data_long (uint offset); +u32 fetch_data_long_abs (uint segment, uint offset); +void store_data_byte (uint offset, u8 val); +void store_data_byte_abs (uint segment, uint offset, u8 val); +void store_data_word (uint offset, u16 val); +void store_data_word_abs (uint segment, uint offset, u16 val); +void store_data_long (uint offset, u32 val); +void store_data_long_abs (uint segment, uint offset, u32 val); +u8* decode_rm_byte_register(int reg); +u16* decode_rm_word_register(int reg); +u32* decode_rm_long_register(int reg); +u16* decode_rm_seg_register(int reg); +u32 decode_rm00_address(int rm); +u32 decode_rm01_address(int rm); +u32 decode_rm10_address(int rm); +u32 decode_sib_address(int sib, int mod); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_DECODE_H */ diff --git a/userspace/sdks/nv570/nvalloc/unix/include/x86emu/fpu.h b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/fpu.h new file mode 100644 index 0000000..7c4f24e --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/fpu.h @@ -0,0 +1,61 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for FPU instruction decoding. +* +****************************************************************************/ + +#ifndef __X86EMU_FPU_H +#define __X86EMU_FPU_H + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* these have to be defined, whether 8087 support compiled in or not. */ + +extern void x86emuOp_esc_coprocess_d8 (u8 op1); +extern void x86emuOp_esc_coprocess_d9 (u8 op1); +extern void x86emuOp_esc_coprocess_da (u8 op1); +extern void x86emuOp_esc_coprocess_db (u8 op1); +extern void x86emuOp_esc_coprocess_dc (u8 op1); +extern void x86emuOp_esc_coprocess_dd (u8 op1); +extern void x86emuOp_esc_coprocess_de (u8 op1); +extern void x86emuOp_esc_coprocess_df (u8 op1); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_FPU_H */ diff --git a/userspace/sdks/nv570/nvalloc/unix/include/x86emu/fpu_regs.h b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/fpu_regs.h new file mode 100644 index 0000000..39ee7fe --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/fpu_regs.h @@ -0,0 +1,119 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for FPU register definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_FPU_REGS_H +#define __X86EMU_FPU_REGS_H + +#ifdef X86_FPU_SUPPORT + +#ifdef PACK +# pragma PACK +#endif + +/* Basic 8087 register can hold any of the following values: */ + +union x86_fpu_reg_u { + s8 tenbytes[10]; + double dval; + float fval; + s16 sval; + s32 lval; + }; + +struct x86_fpu_reg { + union x86_fpu_reg_u reg; + char tag; + }; + +/* + * Since we are not going to worry about the problems of aliasing + * registers, every time a register is modified, its result type is + * set in the tag fields for that register. If some operation + * attempts to access the type in a way inconsistent with its current + * storage format, then we flag the operation. If common, we'll + * attempt the conversion. + */ + +#define X86_FPU_VALID 0x80 +#define X86_FPU_REGTYP(r) ((r) & 0x7F) + +#define X86_FPU_WORD 0x0 +#define X86_FPU_SHORT 0x1 +#define X86_FPU_LONG 0x2 +#define X86_FPU_FLOAT 0x3 +#define X86_FPU_DOUBLE 0x4 +#define X86_FPU_LDBL 0x5 +#define X86_FPU_BSD 0x6 + +#define X86_FPU_STKTOP 0 + +struct x86_fpu_registers { + struct x86_fpu_reg x86_fpu_stack[8]; + int x86_fpu_flags; + int x86_fpu_config; /* rounding modes, etc. */ + short x86_fpu_tos, x86_fpu_bos; + }; + +#ifdef END_PACK +# pragma END_PACK +#endif + +/* + * There are two versions of the following macro. + * + * One version is for opcode D9, for which there are more than 32 + * instructions encoded in the second byte of the opcode. + * + * The other version, deals with all the other 7 i87 opcodes, for + * which there are only 32 strings needed to describe the + * instructions. + */ + +#endif /* X86_FPU_SUPPORT */ + +#ifdef X86EMU_DEBUG +# define DECODE_PRINTINSTR32(t,mod,rh,rl) \ + DECODE_PRINTF(t[(mod<<3)+(rh)]); +# define DECODE_PRINTINSTR256(t,mod,rh,rl) \ + DECODE_PRINTF(t[(mod<<6)+(rh<<3)+(rl)]); +#else +# define DECODE_PRINTINSTR32(t,mod,rh,rl) +# define DECODE_PRINTINSTR256(t,mod,rh,rl) +#endif + +#endif /* __X86EMU_FPU_REGS_H */ diff --git a/userspace/sdks/nv570/nvalloc/unix/include/x86emu/ops.h b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/ops.h new file mode 100644 index 0000000..82d2bbe --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/ops.h @@ -0,0 +1,45 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for operand decoding functions. +* +****************************************************************************/ + +#ifndef __X86EMU_OPS_H +#define __X86EMU_OPS_H + +extern void (*x86emu_optab[0x100])(u8 op1); +extern void (*x86emu_optab2[0x100])(u8 op2); + +#endif /* __X86EMU_OPS_H */ diff --git a/userspace/sdks/nv570/nvalloc/unix/include/x86emu/prim_ops.h b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/prim_ops.h new file mode 100644 index 0000000..8978004 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/prim_ops.h @@ -0,0 +1,141 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for primitive operation functions. +* +****************************************************************************/ + +#ifndef __X86EMU_PRIM_OPS_H +#define __X86EMU_PRIM_OPS_H + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +u16 aaa_word (u16 d); +u16 aas_word (u16 d); +u16 aad_word (u16 d); +u16 aam_word (u8 d); +u8 adc_byte (u8 d, u8 s); +u16 adc_word (u16 d, u16 s); +u32 adc_long (u32 d, u32 s); +u8 add_byte (u8 d, u8 s); +u16 add_word (u16 d, u16 s); +u32 add_long (u32 d, u32 s); +u8 and_byte (u8 d, u8 s); +u16 and_word (u16 d, u16 s); +u32 and_long (u32 d, u32 s); +u8 cmp_byte (u8 d, u8 s); +u16 cmp_word (u16 d, u16 s); +u32 cmp_long (u32 d, u32 s); +u8 daa_byte (u8 d); +u8 das_byte (u8 d); +u8 dec_byte (u8 d); +u16 dec_word (u16 d); +u32 dec_long (u32 d); +u8 inc_byte (u8 d); +u16 inc_word (u16 d); +u32 inc_long (u32 d); +u8 or_byte (u8 d, u8 s); +u16 or_word (u16 d, u16 s); +u32 or_long (u32 d, u32 s); +u8 neg_byte (u8 s); +u16 neg_word (u16 s); +u32 neg_long (u32 s); +u8 not_byte (u8 s); +u16 not_word (u16 s); +u32 not_long (u32 s); +u8 rcl_byte (u8 d, u8 s); +u16 rcl_word (u16 d, u8 s); +u32 rcl_long (u32 d, u8 s); +u8 rcr_byte (u8 d, u8 s); +u16 rcr_word (u16 d, u8 s); +u32 rcr_long (u32 d, u8 s); +u8 rol_byte (u8 d, u8 s); +u16 rol_word (u16 d, u8 s); +u32 rol_long (u32 d, u8 s); +u8 ror_byte (u8 d, u8 s); +u16 ror_word (u16 d, u8 s); +u32 ror_long (u32 d, u8 s); +u8 shl_byte (u8 d, u8 s); +u16 shl_word (u16 d, u8 s); +u32 shl_long (u32 d, u8 s); +u8 shr_byte (u8 d, u8 s); +u16 shr_word (u16 d, u8 s); +u32 shr_long (u32 d, u8 s); +u8 sar_byte (u8 d, u8 s); +u16 sar_word (u16 d, u8 s); +u32 sar_long (u32 d, u8 s); +u16 shld_word (u16 d, u16 fill, u8 s); +u32 shld_long (u32 d, u32 fill, u8 s); +u16 shrd_word (u16 d, u16 fill, u8 s); +u32 shrd_long (u32 d, u32 fill, u8 s); +u8 sbb_byte (u8 d, u8 s); +u16 sbb_word (u16 d, u16 s); +u32 sbb_long (u32 d, u32 s); +u8 sub_byte (u8 d, u8 s); +u16 sub_word (u16 d, u16 s); +u32 sub_long (u32 d, u32 s); +void test_byte (u8 d, u8 s); +void test_word (u16 d, u16 s); +void test_long (u32 d, u32 s); +u8 xor_byte (u8 d, u8 s); +u16 xor_word (u16 d, u16 s); +u32 xor_long (u32 d, u32 s); +void imul_byte (u8 s); +void imul_word (u16 s); +void imul_long (u32 s); +void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s); +void mul_byte (u8 s); +void mul_word (u16 s); +void mul_long (u32 s); +void idiv_byte (u8 s); +void idiv_word (u16 s); +void idiv_long (u32 s); +void div_byte (u8 s); +void div_word (u16 s); +void div_long (u32 s); +void ins (int size); +void outs (int size); +u16 mem_access_word (int addr); +void push_word (u16 w); +void push_long (u32 w); +u16 pop_word (void); +u32 pop_long (void); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_PRIM_OPS_H */ diff --git a/userspace/sdks/nv570/nvalloc/unix/include/x86emu/regs.h b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/regs.h new file mode 100644 index 0000000..4cd0f8b --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/regs.h @@ -0,0 +1,340 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for x86 register definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_REGS_H +#define __X86EMU_REGS_H + +#include "x86emu/debug.h" + +/*---------------------- Macros and type definitions ----------------------*/ + +#ifdef PACK +# pragma PACK +#endif + +/* + * General EAX, EBX, ECX, EDX type registers. Note that for + * portability, and speed, the issue of byte swapping is not addressed + * in the registers. All registers are stored in the default format + * available on the host machine. The only critical issue is that the + * registers should line up EXACTLY in the same manner as they do in + * the 386. That is: + * + * EAX & 0xff === AL + * EAX & 0xffff == AX + * + * etc. The result is that alot of the calculations can then be + * done using the native instruction set fully. + */ + +#ifdef __BIG_ENDIAN__ + +typedef struct { + u32 e_reg; + } I32_reg_t; + +typedef struct { + u16 filler0, x_reg; + } I16_reg_t; + +typedef struct { + u8 filler0, filler1, h_reg, l_reg; + } I8_reg_t; + +#else /* !__BIG_ENDIAN__ */ + +typedef struct { + u32 e_reg; + } I32_reg_t; + +typedef struct { + u16 x_reg; + } I16_reg_t; + +typedef struct { + u8 l_reg, h_reg; + } I8_reg_t; + +#endif /* __BIG_ENDIAN__ */ + +typedef union { + I32_reg_t I32_reg; + I16_reg_t I16_reg; + I8_reg_t I8_reg; + } i386_general_register; + +struct i386_general_regs { + i386_general_register A, B, C, D; + }; + +typedef struct i386_general_regs Gen_reg_t; + +struct i386_special_regs { + i386_general_register SP, BP, SI, DI, IP; + u32 FLAGS; + }; + +/* + * Segment registers here represent the 16 bit quantities + * CS, DS, ES, SS. + */ + +struct i386_segment_regs { + u16 CS, DS, SS, ES, FS, GS; + }; + +/* 8 bit registers */ +#define R_AH gen.A.I8_reg.h_reg +#define R_AL gen.A.I8_reg.l_reg +#define R_BH gen.B.I8_reg.h_reg +#define R_BL gen.B.I8_reg.l_reg +#define R_CH gen.C.I8_reg.h_reg +#define R_CL gen.C.I8_reg.l_reg +#define R_DH gen.D.I8_reg.h_reg +#define R_DL gen.D.I8_reg.l_reg + +/* 16 bit registers */ +#define R_AX gen.A.I16_reg.x_reg +#define R_BX gen.B.I16_reg.x_reg +#define R_CX gen.C.I16_reg.x_reg +#define R_DX gen.D.I16_reg.x_reg + +/* 32 bit extended registers */ +#define R_EAX gen.A.I32_reg.e_reg +#define R_EBX gen.B.I32_reg.e_reg +#define R_ECX gen.C.I32_reg.e_reg +#define R_EDX gen.D.I32_reg.e_reg + +/* special registers */ +#define R_SP spc.SP.I16_reg.x_reg +#define R_BP spc.BP.I16_reg.x_reg +#define R_SI spc.SI.I16_reg.x_reg +#define R_DI spc.DI.I16_reg.x_reg +#define R_IP spc.IP.I16_reg.x_reg +#define R_FLG spc.FLAGS + +/* special registers */ +#define R_SP spc.SP.I16_reg.x_reg +#define R_BP spc.BP.I16_reg.x_reg +#define R_SI spc.SI.I16_reg.x_reg +#define R_DI spc.DI.I16_reg.x_reg +#define R_IP spc.IP.I16_reg.x_reg +#define R_FLG spc.FLAGS + +/* special registers */ +#define R_ESP spc.SP.I32_reg.e_reg +#define R_EBP spc.BP.I32_reg.e_reg +#define R_ESI spc.SI.I32_reg.e_reg +#define R_EDI spc.DI.I32_reg.e_reg +#define R_EIP spc.IP.I32_reg.e_reg +#define R_EFLG spc.FLAGS + +/* segment registers */ +#define R_CS seg.CS +#define R_DS seg.DS +#define R_SS seg.SS +#define R_ES seg.ES +#define R_FS seg.FS +#define R_GS seg.GS + +/* flag conditions */ +#define FB_CF 0x0001 /* CARRY flag */ +#define FB_PF 0x0004 /* PARITY flag */ +#define FB_AF 0x0010 /* AUX flag */ +#define FB_ZF 0x0040 /* ZERO flag */ +#define FB_SF 0x0080 /* SIGN flag */ +#define FB_TF 0x0100 /* TRAP flag */ +#define FB_IF 0x0200 /* INTERRUPT ENABLE flag */ +#define FB_DF 0x0400 /* DIR flag */ +#define FB_OF 0x0800 /* OVERFLOW flag */ + +/* 80286 and above always have bit#1 set */ +#define F_ALWAYS_ON (0x0002) /* flag bits always on */ + +/* + * Define a mask for only those flag bits we will ever pass back + * (via PUSHF) + */ +#define F_MSK (FB_CF|FB_PF|FB_AF|FB_ZF|FB_SF|FB_TF|FB_IF|FB_DF|FB_OF) + +/* following bits masked in to a 16bit quantity */ + +#define F_CF 0x0001 /* CARRY flag */ +#define F_PF 0x0004 /* PARITY flag */ +#define F_AF 0x0010 /* AUX flag */ +#define F_ZF 0x0040 /* ZERO flag */ +#define F_SF 0x0080 /* SIGN flag */ +#define F_TF 0x0100 /* TRAP flag */ +#define F_IF 0x0200 /* INTERRUPT ENABLE flag */ +#define F_DF 0x0400 /* DIR flag */ +#define F_OF 0x0800 /* OVERFLOW flag */ + +#define TOGGLE_FLAG(flag) (M.x86.R_FLG ^= (flag)) +#define SET_FLAG(flag) (M.x86.R_FLG |= (flag)) +#define CLEAR_FLAG(flag) (M.x86.R_FLG &= ~(flag)) +#define ACCESS_FLAG(flag) (M.x86.R_FLG & (flag)) +#define CLEARALL_FLAG(m) (M.x86.R_FLG = 0) + +#define CONDITIONAL_SET_FLAG(COND,FLAG) \ + if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG) + +#define F_PF_CALC 0x010000 /* PARITY flag has been calced */ +#define F_ZF_CALC 0x020000 /* ZERO flag has been calced */ +#define F_SF_CALC 0x040000 /* SIGN flag has been calced */ + +#define F_ALL_CALC 0xff0000 /* All have been calced */ + +/* + * Emulator machine state. + * Segment usage control. + */ +#define SYSMODE_SEG_DS_SS 0x00000001 +#define SYSMODE_SEGOVR_CS 0x00000002 +#define SYSMODE_SEGOVR_DS 0x00000004 +#define SYSMODE_SEGOVR_ES 0x00000008 +#define SYSMODE_SEGOVR_FS 0x00000010 +#define SYSMODE_SEGOVR_GS 0x00000020 +#define SYSMODE_SEGOVR_SS 0x00000040 +#define SYSMODE_PREFIX_REPE 0x00000080 +#define SYSMODE_PREFIX_REPNE 0x00000100 +#define SYSMODE_PREFIX_DATA 0x00000200 +#define SYSMODE_PREFIX_ADDR 0x00000400 +#define SYSMODE_INTR_PENDING 0x10000000 +#define SYSMODE_EXTRN_INTR 0x20000000 +#define SYSMODE_HALTED 0x40000000 + +#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | \ + SYSMODE_SEGOVR_CS | \ + SYSMODE_SEGOVR_DS | \ + SYSMODE_SEGOVR_ES | \ + SYSMODE_SEGOVR_FS | \ + SYSMODE_SEGOVR_GS | \ + SYSMODE_SEGOVR_SS) +#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS | \ + SYSMODE_SEGOVR_CS | \ + SYSMODE_SEGOVR_DS | \ + SYSMODE_SEGOVR_ES | \ + SYSMODE_SEGOVR_FS | \ + SYSMODE_SEGOVR_GS | \ + SYSMODE_SEGOVR_SS | \ + SYSMODE_PREFIX_DATA | \ + SYSMODE_PREFIX_ADDR) + +#define INTR_SYNCH 0x1 +#define INTR_ASYNCH 0x2 +#define INTR_HALTED 0x4 + +typedef struct { + struct i386_general_regs gen; + struct i386_special_regs spc; + struct i386_segment_regs seg; + /* + * MODE contains information on: + * REPE prefix 2 bits repe,repne + * SEGMENT overrides 5 bits normal,DS,SS,CS,ES + * Delayed flag set 3 bits (zero, signed, parity) + * reserved 6 bits + * interrupt # 8 bits instruction raised interrupt + * BIOS video segregs 4 bits + * Interrupt Pending 1 bits + * Extern interrupt 1 bits + * Halted 1 bits + */ + u32 mode; + volatile int intr; /* mask of pending interrupts */ + int debug; +#ifdef X86EMU_DEBUG + int check; + u16 saved_ip; + u16 saved_cs; + int enc_pos; + int enc_str_pos; + char decode_buf[32]; /* encoded byte stream */ + char decoded_buf[256]; /* disassembled strings */ + char debug_cmd[64]; /* input for x86emu_single_step */ +#endif + u8 intno; + u8 __pad[3]; + } X86EMU_regs; + +/**************************************************************************** +REMARKS: +Structure maintaining the emulator machine state. + +MEMBERS: +mem_base - Base real mode memory for the emulator +mem_size - Size of the real mode memory block for the emulator +private - private data pointer +x86 - X86 registers +****************************************************************************/ +typedef struct { + unsigned long mem_base; + unsigned long mem_size; + void* private; + X86EMU_regs x86; + } X86EMU_sysEnv; + +#ifdef END_PACK +# pragma END_PACK +#endif + +/*----------------------------- Global Variables --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* Global emulator machine state. + * + * We keep it global to avoid pointer dereferences in the code for speed. + */ + +extern X86EMU_sysEnv _X86EMU_env; +#define M _X86EMU_env + +/*-------------------------- Function Prototypes --------------------------*/ + +/* Function to log information at runtime */ + +void printk(const char *fmt, ...); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_REGS_H */ diff --git a/userspace/sdks/nv570/nvalloc/unix/include/x86emu/types.h b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/types.h new file mode 100644 index 0000000..53c3e87 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/types.h @@ -0,0 +1,93 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for x86 emulator type definitions. +* +****************************************************************************/ + + +#ifndef __X86EMU_TYPES_H +#define __X86EMU_TYPES_H + +#ifndef NO_SYS_HEADERS +#include +#endif + +/* + * The following kludge is an attempt to work around typedef conflicts with + * . + */ +#define u8 x86emuu8 +#define u16 x86emuu16 +#define u32 x86emuu32 +#define u64 x86emuu64 +#define s8 x86emus8 +#define s16 x86emus16 +#define s32 x86emus32 +#define s64 x86emus64 +#define uint x86emuuint +#define sint x86emusint + +/*---------------------- Macros and type definitions ----------------------*/ + +/* Currently only for Linux/32bit */ +#undef __HAS_LONG_LONG__ +#if defined(__GNUC__) && !defined(NO_LONG_LONG) +#define __HAS_LONG_LONG__ +#endif + +#define NUM32 int + +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned NUM32 u32; +#ifdef __HAS_LONG_LONG__ +typedef unsigned long long u64; +#endif + +typedef char s8; +typedef short s16; +typedef NUM32 s32; +#ifdef __HAS_LONG_LONG__ +typedef long long s64; +#endif + +typedef unsigned int uint; +typedef int sint; + +typedef u16 X86EMU_pioAddr; + +#undef NUM32 + +#endif /* __X86EMU_TYPES_H */ diff --git a/userspace/sdks/nv570/nvalloc/unix/include/x86emu/x86emu.h b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/x86emu.h new file mode 100644 index 0000000..935cc70 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/x86emu.h @@ -0,0 +1,205 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for public specific functions. +* Any application linking against us should only +* include this header +* +****************************************************************************/ + +#ifndef __X86EMU_X86EMU_H +#define __X86EMU_X86EMU_H + +// NV +#ifndef NO_SYS_HEADERS +#define NO_SYS_HEADERS +#endif + +#ifdef SCITECH +#include "scitech.h" +#define X86API _ASMAPI +#define X86APIP _ASMAPIP +typedef int X86EMU_pioAddr; +#else +#include "x86emu/types.h" +#define X86API +#define X86APIP * +#endif +#include "x86emu/regs.h" +#include "x86emu/debug.h" + +/*---------------------- Macros and type definitions ----------------------*/ + +#ifdef PACK +# pragma PACK /* Don't pack structs with function pointers! */ +#endif + +/**************************************************************************** +REMARKS: +Data structure containing ponters to programmed I/O functions used by the +emulator. This is used so that the user program can hook all programmed +I/O for the emulator to handled as necessary by the user program. By +default the emulator contains simple functions that do not do access the +hardware in any way. To allow the emualtor access the hardware, you will +need to override the programmed I/O functions using the X86EMU_setupPioFuncs +function. + +HEADER: +x86emu.h + +MEMBERS: +inb - Function to read a byte from an I/O port +inw - Function to read a word from an I/O port +inl - Function to read a dword from an I/O port +outb - Function to write a byte to an I/O port +outw - Function to write a word to an I/O port +outl - Function to write a dword to an I/O port +****************************************************************************/ +typedef struct { + u8 (X86APIP inb)(X86EMU_pioAddr addr); + u16 (X86APIP inw)(X86EMU_pioAddr addr); + u32 (X86APIP inl)(X86EMU_pioAddr addr); + void (X86APIP outb)(X86EMU_pioAddr addr, u8 val); + void (X86APIP outw)(X86EMU_pioAddr addr, u16 val); + void (X86APIP outl)(X86EMU_pioAddr addr, u32 val); + } X86EMU_pioFuncs; + +/**************************************************************************** +REMARKS: +Data structure containing ponters to memory access functions used by the +emulator. This is used so that the user program can hook all memory +access functions as necessary for the emulator. By default the emulator +contains simple functions that only access the internal memory of the +emulator. If you need specialised functions to handle access to different +types of memory (ie: hardware framebuffer accesses and BIOS memory access +etc), you will need to override this using the X86EMU_setupMemFuncs +function. + +HEADER: +x86emu.h + +MEMBERS: +rdb - Function to read a byte from an address +rdw - Function to read a word from an address +rdl - Function to read a dword from an address +wrb - Function to write a byte to an address +wrw - Function to write a word to an address +wrl - Function to write a dword to an address +****************************************************************************/ +typedef struct { + u8 (X86APIP rdb)(u32 addr); + u16 (X86APIP rdw)(u32 addr); + u32 (X86APIP rdl)(u32 addr); + void (X86APIP wrb)(u32 addr, u8 val); + void (X86APIP wrw)(u32 addr, u16 val); + void (X86APIP wrl)(u32 addr, u32 val); + } X86EMU_memFuncs; + +/**************************************************************************** + Here are the default memory read and write + function in case they are needed as fallbacks. +***************************************************************************/ +extern u8 X86API rdb(u32 addr); +extern u16 X86API rdw(u32 addr); +extern u32 X86API rdl(u32 addr); +extern void X86API wrb(u32 addr, u8 val); +extern void X86API wrw(u32 addr, u16 val); +extern void X86API wrl(u32 addr, u32 val); + +#ifdef END_PACK +# pragma END_PACK +#endif + +/*--------------------- type definitions -----------------------------------*/ + +typedef void (X86APIP X86EMU_intrFuncs)(int num); +extern X86EMU_intrFuncs _X86EMU_intrTab[256]; + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +void X86EMU_setupMemFuncs(X86EMU_memFuncs *funcs); +void X86EMU_setupPioFuncs(X86EMU_pioFuncs *funcs); +void X86EMU_setupIntrFuncs(X86EMU_intrFuncs funcs[]); +void X86EMU_prepareForInt(int num); + +/* decode.c */ + +void X86EMU_exec(void); +void X86EMU_halt_sys(void); + +#ifdef X86EMU_DEBUG +#define HALT_SYS() do { \ + NV_PRINTF(LEVEL_INFO, "halt_sys: file %s, line %d\n", __FILE__, __LINE__); \ + X86EMU_halt_sys(); \ + } while (0) +#else +#define HALT_SYS() X86EMU_halt_sys() +#endif + +/* Debug options */ + +#define DEBUG_DECODE_F 0x000001 /* print decoded instruction */ +#define DEBUG_TRACE_F 0x000002 /* dump regs before/after execution */ +#define DEBUG_STEP_F 0x000004 +#define DEBUG_DISASSEMBLE_F 0x000008 +#define DEBUG_BREAK_F 0x000010 +#define DEBUG_SVC_F 0x000020 +#define DEBUG_SAVE_IP_CS_F 0x000040 +#define DEBUG_FS_F 0x000080 +#define DEBUG_PROC_F 0x000100 +#define DEBUG_SYSINT_F 0x000200 /* bios system interrupts. */ +#define DEBUG_TRACECALL_F 0x000400 +#define DEBUG_INSTRUMENT_F 0x000800 +#define DEBUG_MEM_TRACE_F 0x001000 +#define DEBUG_IO_TRACE_F 0x002000 +#define DEBUG_TRACECALL_REGS_F 0x004000 +#define DEBUG_DECODE_NOPRINT_F 0x008000 +#define DEBUG_EXIT 0x010000 +#define DEBUG_SYS_F (DEBUG_SVC_F|DEBUG_FS_F|DEBUG_PROC_F) + +void X86EMU_trace_regs(void); +void X86EMU_trace_xregs(void); +void X86EMU_dump_memory(u16 seg, u16 off, u32 amt); +int X86EMU_trace_on(void); +int X86EMU_trace_off(void); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_X86EMU_H */ diff --git a/userspace/sdks/nv570/nvalloc/unix/include/x86emu/x86emui.h b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/x86emui.h new file mode 100644 index 0000000..5788558 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/include/x86emu/x86emui.h @@ -0,0 +1,113 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for system specific functions. These functions +* are always compiled and linked in the OS depedent libraries, +* and never in a binary portable driver. +* +****************************************************************************/ + + +#ifndef __X86EMU_X86EMUI_H +#define __X86EMU_X86EMUI_H + +/* If we are compiling in C++ mode, we can compile some functions as + * inline to increase performance (however the code size increases quite + * dramatically in this case). + */ + +// NV +#ifndef NO_SYS_HEADERS +#define NO_SYS_HEADERS +#endif +#include /* NULL */ +#if defined(__cplusplus) && !defined(_NO_INLINE) +#define _INLINE inline +#else +#define _INLINE static +#endif + +/* Get rid of unused parameters in C++ compilation mode */ + +#ifdef __cplusplus +#define X86EMU_UNUSED(v) +#else +#define X86EMU_UNUSED(v) v +#endif + +#include "x86emu.h" +#include "x86emu/regs.h" +#include "x86emu/debug.h" +#include "x86emu/decode.h" +#include "x86emu/ops.h" +#include "x86emu/prim_ops.h" +#include "x86emu/fpu.h" +#include "x86emu/fpu_regs.h" + +#ifndef NO_SYS_HEADERS +#include +#include +#include +#endif + +// On x86_64 abs() is not recognized. I don't understand why. +#ifndef abs +#define abs(i) __builtin_abs(i) +#endif + +/*--------------------------- Inline Functions ----------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +extern u8 (X86APIP sys_rdb)(u32 addr); +extern u16 (X86APIP sys_rdw)(u32 addr); +extern u32 (X86APIP sys_rdl)(u32 addr); +extern void (X86APIP sys_wrb)(u32 addr,u8 val); +extern void (X86APIP sys_wrw)(u32 addr,u16 val); +extern void (X86APIP sys_wrl)(u32 addr,u32 val); + +extern u8 (X86APIP sys_inb)(X86EMU_pioAddr addr); +extern u16 (X86APIP sys_inw)(X86EMU_pioAddr addr); +extern u32 (X86APIP sys_inl)(X86EMU_pioAddr addr); +extern void (X86APIP sys_outb)(X86EMU_pioAddr addr,u8 val); +extern void (X86APIP sys_outw)(X86EMU_pioAddr addr,u16 val); +extern void (X86APIP sys_outl)(X86EMU_pioAddr addr,u32 val); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_X86EMUI_H */ diff --git a/userspace/sdks/nv570/nvalloc/unix/src/asm/x86/nv_cpuid.c b/userspace/sdks/nv570/nvalloc/unix/src/asm/x86/nv_cpuid.c new file mode 100644 index 0000000..fe6dfa9 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/src/asm/x86/nv_cpuid.c @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2013 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +/* inline assembler routines for UNIX platforms */ + +#if defined(NVCPU_X86_64) + +int osNv_cpuid( + int op, + int subop, + NvU32 *eax, + NvU32 *ebx, + NvU32 *ecx, + NvU32 *edx +) +{ + asm volatile (" cpuid \n" + : "=a" (*eax), + "=b" (*ebx), + "=c" (*ecx), + "=d" (*edx) + : "a" (op), + "c" (subop) + : "cc"); + + return 1; +} + +#endif diff --git a/userspace/sdks/nv570/nvalloc/unix/src/asm/x86/nv_rdcr.c b/userspace/sdks/nv570/nvalloc/unix/src/asm/x86/nv_rdcr.c new file mode 100644 index 0000000..6115aa4 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/src/asm/x86/nv_rdcr.c @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2013 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +/* inline assembler routines for UNIX platforms */ + +#if defined(NVCPU_X86_64) + +NvU32 osNv_rdcr4(void) +{ + NvU64 val; + asm volatile ("movq %%cr4,%0" : "=r" (val)); + return (NvU32)val; +} + +#endif diff --git a/userspace/sdks/nv570/nvalloc/unix/src/dynamic-power.c b/userspace/sdks/nv570/nvalloc/unix/src/dynamic-power.c new file mode 100644 index 0000000..fa61d94 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/src/dynamic-power.c @@ -0,0 +1,3185 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +/* + * NOTE: + * The driver disables dynamic power management by effectively setting + * nv_dynamic_power_t::mode to NV_DYNAMIC_PM_NEVER at two places: + * 1) During module probe, when the _PRx methods are not supported + * by the SBIOS or when the kernel does not support runtime PM. + * 2) During RM Init, when the GPU is not Turing+ or when the system is not + * a laptop or when the VBIOS does not support RTD3/GC6. + * + * Thus, after RMInit, if the nv_dynamic_power_t::mode is still + * NV_DYNAMIC_PM_FINE, then we know for sure that the fine grained power + * control is active and running. In this case, the runtime D3 status is + * shown as "Enabled (fine-grained)". + * + * If the nv_dynamic_power_t::mode is NV_DYNAMIC_PM_NEVER, we have to + * distinguish between four cases: + * 1) The driver disabled dynamic power management due to lack of kernel/SBIOS + * support. + * 2) The driver disabled dynamic power management because the GPU does not + * support it or the system is not a laptop. + * 3) The user has explicitly disabled the feature. + * 4) Configuration is not supported by default. + * + * In order to differentiate between these four cases, + * we use the value of regkey NVreg_DynamicPowerManagement. If this value is + * set to 0, then we know that the user has explicitly disabled the + * feature. In this case we show the runtime D3 status as "Disabled". This + * handles case (3) above. + * + * For case (4), we look at the combination of nv_dynamic_power_t::mode and + * NVreg_DynamicPowerManagement value. If mode is never and regkey value is + * default, then status is shown as "Disabled by default". + * + * For remaining cases, (case (1) and (2)) we show status as "Not Supported". + * + * When the regkey is set to 0 and the driver disables the feature due to lack + * of some support, then precedence will be given to regkey value. Thus, when + * both "Not supported" and "Disabled" are possible values, precedence will be + * given to "Disabled" over "Not Supported". + * + * For coarse-grain power control, we show runtime D3 status as + * "Enabled (coarse-grained)". + * + * The runtime D3 status is shown as "?" when RM has not been initialized. + * This is because we do not have full knowledge regarding driver triggered + * disablement until RM is initialized. + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include "kernel/gpu/intr/intr.h" + +#include +#include +#include +#include +#include + + +// mask holding dynamic power supported GPUs +static NvU32 dynamicPowerSupportGpuMask = 0; + +// +// Schedule timer based callback, to check for the complete GPU Idleness. +// Windows has idle time from 70msec to 10sec, we opted for present duration +// considering windows limit. Duration is not much aggressive or slow, hence +// less thrashing. +// +#define GC6_PRECONDITION_CHECK_TIME ((NvU64)5 * 1000 * 1000 * 1000) + +// +// iGPU needs a more aggressive timeout value of precondition +// check to quickly engage the Rail-Gating state on an embedded +// system. +// Considering some basic scenarios like GPU monitoring which could +// poll the GPU every 1 second, Rail-Gating cycle should not be triggered +// in between the pollings. So the timeout value is set to 500 ms. +// and the shortest duration to trigger Deferred-Idle would be +// IGPU_RG_PRECONDITION_CHECK_TIME + IGPU_RG_BLOCKER_CHECK_AND_METHOD_FLUSH_TIME +// +#define IGPU_RG_PRECONDITION_CHECK_TIME ((NvU64)500 * 1000 * 1000) + +// +// Timeout needed for back to back GC6 cycles. +// Timeout is kept same as the timeout selected for GC6 precondition check. +// There are cases where GPU is in GC6 and then kernel wakes GPU out of GC6 +// as part of say accessing pci tree through lspci and then again ask driver +// to put GPU in GC6 state after access to device info is done. +// Below are the reasons for having timeout limit for back to back GC6 cycle. +// 1> Less chip life cycle. +// 2> P-state is not reached to GC6 supported P-state, in some cycles. +// P-state case returns error to kernel, resulting in corrupted sysfs entry +// and then kernel never calls driver to put device in low power state. +// +#define GC6_CYCLE_IDLE_HOLDOFF_CHECK_TIME GC6_PRECONDITION_CHECK_TIME + +// +// Once GPU is found to be idle, driver will schedule another callback of +// smaller duration. Driver needs to be sure that methods that are present +// in host pipeline are flushed to the respective engines and engines become +// idle upon consumption. +// +#define GC6_BAR1_BLOCKER_CHECK_AND_METHOD_FLUSH_TIME (200 * 1000 * 1000) + +// +// The purpose of this timeout value is similar to +// GC6_BAR1_BLOCKER_CHECK_AND_METHOD_FLUSH_TIME. +// The difference between iGPU Rail-Gating and GC6 is that iGPU RG has a more +// aggressive timeout value of precondition check to quickly engage the +// Rail-Gating state on an embedded system. Meanwhile, the overall duration +// of Deferred-Idle should be larger than 1 second considering some polling +// scenarios which happens every 1 second. +// The value here is extended to 700 ms so the overall Deferred-Idle duration. +// could be keep within within the range: +// - Lower Bound: IGPU_RG_PRECONDITION_CHECK_TIME + IGPU_RG_BLOCKER_CHECK_AND_METHOD_FLUSH_TIME +// - Upper Bound: IGPU_RG_PRECONDITION_CHECK_TIME * 2 + IGPU_RG_BLOCKER_CHECK_AND_METHOD_FLUSH_TIME +// +#define IGPU_RG_BLOCKER_CHECK_AND_METHOD_FLUSH_TIME (700 * 1000 * 1000) + +// +// Cap Maximum FB allocation size for GCOFF. If regkey value is greater +// than this value then it will be capped to this value. +// +#define GCOFF_DYNAMIC_PM_MAX_FB_SIZE_MB 1024 + +// +// Safe/Fallback value of PEX reset delay for GCOFF/GPUOFF. +// Used when programming upstream port as per sku specific PEX reset delay from vbios fails +// +#define DEFAULT_GCOFF_PEXRST_DELAY 0 + +static void RmScheduleCallbackForIdlePreConditions(OBJGPU *); +static void RmScheduleCallbackForIdlePreConditionsUnderGpuLock(OBJGPU *); +static void RmScheduleCallbackToIndicateIdle(OBJGPU *); +static NvBool RmCheckForGcxSupportOnCurrentState(OBJGPU *); +static void RmScheduleCallbackToRemoveIdleHoldoff(OBJGPU *); +static void RmQueueIdleSustainedWorkitem(OBJGPU *); + +/*! + * @brief Wrapper that checks lock order for the dynamic power mutex. Locking + * order dictates that the GPU lock must not be taken before taking the dynamic + * power mutex. + * + * The GPU lock must not be held when calling this function. + * + * @param[in] nvp nv_priv_t pointer. + */ +static void acquireDynamicPowerMutex(nv_priv_t *nvp) +{ + /* + * Note that this may be called before nvp->pGpu has been initialized, for + * example at the very beginning of nv_start_device. + */ + NV_ASSERT_CHECKED(!nvp->pGpu || !rmDeviceGpuLockIsOwner(nvp->pGpu->gpuInstance)); + + portSyncMutexAcquire(nvp->dynamic_power.mutex); +} + +/*! + * @brief Wrapper to release the mutex, just for consistency with + * acquireDynamicPowerMutex() above. + * + * @param[in] nvp nv_priv_t pointer. + */ +static void releaseDynamicPowerMutex(nv_priv_t *nvp) +{ + portSyncMutexRelease(nvp->dynamic_power.mutex); +} + +/*! + * @brief: Helper function to get a string for the given state. + * + * @param[in] state Dynamic power state. + * + * @return String for the given state. + */ +const char *nv_dynamic_power_state_string( + nv_dynamic_power_state_t state +) +{ + switch (state) + { +#define DPCASE(_case) \ + case NV_DYNAMIC_POWER_STATE_ ## _case: return # _case; + + DPCASE(IN_USE); + DPCASE(IDLE_INSTANT); + DPCASE(IDLE_SUSTAINED); + DPCASE(IDLE_INDICATED); + DPCASE(UNKNOWN); +#undef DPCASE + } + NV_ASSERT(0); + return "UNEXPECTED"; +} + +/*! + * @brief: Helper function to transition the GPU represented by the 'nv' + * pointer from the power state 'old_state' to the power state 'new_state'. + * + * An atomic compare-and-swap is used; the function returns true if the + * operation was successful. If the function returns false, the state is + * unchanged. + * + * @param[in] nv nv_state_t pointer. + * @param[in] old_state Previous (current) state. + * @param[in] new_state New (requested) state. + * + * @return TRUE if the operation was successful; FALSE otherwise. + */ +NvBool nv_dynamic_power_state_transition( + nv_state_t *nv, + nv_dynamic_power_state_t old_state, + nv_dynamic_power_state_t new_state +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + NV_ASSERT(old_state != new_state); + + ct_assert(sizeof(nv_dynamic_power_state_t) == sizeof(NvS32)); + NvBool ret = portAtomicCompareAndSwapS32((PORT_ATOMIC NvS32*)&nvp->dynamic_power.state, + (NvS32)new_state, (NvS32)old_state); + + if (ret) + { + NV_PRINTF(LEVEL_INFO, "%s: state transition %s -> %s\n", + __FUNCTION__, + nv_dynamic_power_state_string(old_state), + nv_dynamic_power_state_string(new_state)); + } + else + { + NV_PRINTF(LEVEL_INFO, "%s: FAILED state transition %s -> %s\n", + __FUNCTION__, + nv_dynamic_power_state_string(old_state), + nv_dynamic_power_state_string(new_state)); + } + + return ret; + +} + +/*! + * @brief: Check if the GPU hardware appears to be idle. + * + * Assumes the GPU lock is held. + * + * @param[in] pGpu OBJGPU pointer. + * + * @return TRUE if the GPU appears to be currently idle; FALSE otherwise. + */ +static NvBool RmCanEnterGcxUnderGpuLock( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + NV_ASSERT(rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + + /* + * If GC6 cannot be achieved (either GC6 is unsupported or the upstream port is not configured), + * Check for GCOFF prerequisites. Exclude the check for IGPU which has RG support. + */ + if ((!pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_SUPPORTED) || + !nvp->gc6_upstream_port_configured) && + (!pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_RG_SUPPORTED))) + { + NvU64 usedFbSize = 0; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + /* + * In order to enter GCOFF, the FB memory threshold should be less than gcoff_max_fb_size + * and clients of RM should not hold the refcount to prevent GCOFF. + */ + if (!((memmgrGetUsedRamSize(pGpu, pMemoryManager, &usedFbSize) == NV_OK) && + (usedFbSize <= nvp->dynamic_power.gcoff_max_fb_size) && + (nvp->dynamic_power.clients_gcoff_disallow_refcount == 0))) + { + return NV_FALSE; + } + } + + // Check the instantaneous engine level idleness. + return RmCheckForGcxSupportOnCurrentState(pGpu); +} + +/*! + * @brief: Check the feasibility of GPU engaging in a GCx cycle. + * + * Takes the GPU lock. + * + * @param[in] pGpu OBJGPU pointer. + * + * @return TRUE if the GPU appears to be currently idle; FALSE otherwise. + */ +static NvBool RmCanEnterGcx( + OBJGPU *pGpu +) +{ + NvBool result = NV_FALSE; + NV_STATUS status; + GPU_MASK gpuMask; + + // LOCK: acquire per device lock + status = rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER, + &gpuMask); + if (status == NV_OK) + { + result = RmCanEnterGcxUnderGpuLock(pGpu); + // UNLOCK: release per device lock + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + } + + return result; +} + +/*! + * @brief: Force the GPU to be "not idle", if it had previously been indicated + * idle. This is triggered by GPU usage (i.e., writing through a revoked + * mapping), not tracked through the refcount maintained through + * os_{ref,unref}_dynamic_power. So, if we'd previously indicated the GPU was + * idle, we transition to the IDLE_INSTANT state. + * + * @param[in] gpuInstance GPU instance ID. + * @param[in] pArgs Unused callback closure. + */ +static void RmForceGpuNotIdle( + NvU32 gpuInstance, + void *pArgs +) +{ + OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + nv_dynamic_power_state_t old_state; + NvBool ret; + + acquireDynamicPowerMutex(nvp); + + old_state = nvp->dynamic_power.state; + + switch (old_state) + { + case NV_DYNAMIC_POWER_STATE_IDLE_INDICATED: + nv_indicate_not_idle(nv); + NV_ASSERT(nvp->dynamic_power.deferred_idle_enabled); + RmScheduleCallbackForIdlePreConditions(pGpu); + /* fallthrough */ + case NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED: + ret = nv_dynamic_power_state_transition(nv, old_state, NV_DYNAMIC_POWER_STATE_IDLE_INSTANT); + NV_ASSERT(ret); + break; + case NV_DYNAMIC_POWER_STATE_IDLE_INSTANT: + case NV_DYNAMIC_POWER_STATE_IN_USE: + break; + case NV_DYNAMIC_POWER_STATE_UNKNOWN: + NV_ASSERT(0); + break; + } + + /* + * Now that the GPU is guaranteed to not be powered off, we can resume + * servicing mmap requests as usual. + */ + nv_acquire_mmap_lock(nv); + nv_set_safe_to_mmap_locked(nv, NV_TRUE); + nv_release_mmap_lock(nv); + + releaseDynamicPowerMutex(nvp); +} + +/*! + * @brief: Work item to actually indicate the GPU is idle. This rechecks the + * preconditions one last time and verifies nothing has attempted to write + * through any mappings which were revoked. + * + * @param[in] gpuInstance GPU instance ID. + * @param[in] pArgs Unused callback closure. + */ +static void RmIndicateIdle( + NvU32 gpuInstance, + void *pArgs +) +{ + OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + acquireDynamicPowerMutex(nvp); + + nv_acquire_mmap_lock(nv); + + if (nv_get_all_mappings_revoked_locked(nv) && + nvp->dynamic_power.state == NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED && + RmCanEnterGcx(pGpu)) + { + nv_set_safe_to_mmap_locked(nv, NV_FALSE); + nv_dynamic_power_state_transition(nv, NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED, + NV_DYNAMIC_POWER_STATE_IDLE_INDICATED); + nv_indicate_idle(nv); + } + else + { + RmScheduleCallbackForIdlePreConditions(pGpu); + } + + nv_release_mmap_lock(nv); + + releaseDynamicPowerMutex(nvp); +} + +/*! + * @brief: Helper function to trigger the GPU to be forced indicated + * "non-idle", which powers it on if it had been previously powered off, and + * allows mmap processing to continue. + * + * Triggered when a revoked mapping is accessed. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + */ +NV_STATUS NV_API_CALL rm_schedule_gpu_wakeup( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + void *fp; + NV_STATUS ret; + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + + NV_ENTER_RM_RUNTIME(sp, fp); + + ret = osQueueWorkItem(pGpu, + RmForceGpuNotIdle, + NULL, + (OsQueueWorkItemFlags){0}); + + NV_EXIT_RM_RUNTIME(sp, fp); + + return ret; +} + +/*! + * @brief Function to increment/decrement refcount for GPU driving console. + * + * @params[in] nv nv_state_t pointer. + * @params[in] bIncrease If true, increase refcount else decrease. + */ +void +RmUpdateGc6ConsoleRefCount +( + nv_state_t *nv, + NvBool bIncrease +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + if (nv->console_device == NV_FALSE) + { + return; + } + + acquireDynamicPowerMutex(nvp); + + if (bIncrease) + { + /* + * Here refcount value should atleast be 2 due to below: + * 1> Refcount increased by NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT. + * 2> Refcount increased by the Rm entry points for current thread. + */ + if (nvp->dynamic_power.refcount <= 1) + { + NV_PRINTF(LEVEL_INFO, + "%s: Unexpected dynamic power refcount value\n", __FUNCTION__); + } + else + { + nvp->dynamic_power.refcount++; + } + } + else + { + /* + * Here refcount value should atleast be 3 due to below: + * 1> Refcount set by RM at the probe time for console device. + * 2> Refcount increased by NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT. + * 3> Refcount increased by the Rm entry points for current thread. + */ + if (nvp->dynamic_power.refcount <= 2) + { + NV_PRINTF(LEVEL_INFO, + "%s: Unexpected dynamic power refcount value\n", __FUNCTION__); + } + else + { + nvp->dynamic_power.refcount--; + } + } + + releaseDynamicPowerMutex(nvp); +} + +/*! + * @brief Implements the NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT RmControl + * request. + * + * @param[in] pSubdevice + * @param[in,out] pParams + * + * @return + * NV_OK Success + * NV_ERR_INVALID_ARGUMENT Invalid pParams->action + */ +NV_STATUS +subdeviceCtrlCmdOsUnixGc6BlockerRefCnt_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + + /* TODO: keep track of inc/dec on a per-client basis, clean up after + * clients which are unbalanced. */ + if (pParams->action == NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_INC) + { + return osRefGpuAccessNeeded(pGpu->pOsGpuInfo); + } + else if (pParams->action == NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_DEC) + { + osUnrefGpuAccessNeeded(pGpu->pOsGpuInfo); + } + else + { + return NV_ERR_INVALID_ARGUMENT; + } + + return NV_OK; +} + +/*! + * @brief Implements the NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER RmControl + * request. It will perform dynamic power management for GPU + * HDA contoller. + * + * @param[in] pSubdevice + * @param[in,out] pParams + * + * @return + * NV_OK Success + */ +NV_STATUS +subdeviceCtrlCmdOsUnixAudioDynamicPower_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + + /* + * Ideally, we need to honor pParams->bEnter. If it is true, then send the + * request for suspending the HDA controller and if is false, then send the + * request for waking up the HDA controller. Currently, for unix based OS, + * we don't have any proper way to do this and it is implemented with + * workaround. This workaround will wake up the HDA controller for few + * seconds and then bring it back to suspended state. We are using this + * workaround for both the cases (bEnter is true or false). It will help + * in keeping HDA controller active for the duration, when GPU is + * processing HDA controller commands (like writing ELD data). + */ + nv_audio_dynamic_power(NV_GET_NV_STATE(pGpu)); + + return NV_OK; +} + +/*! + * @brief: Function to indicate if GC6/GC-OFF is supported + * or not on the SKU. + * + * @param[in] pGpu OBJGPU pointer. + * @param[in] bGcxTypeGc6 If true, returns string indicating GC6 support + * otherwise returns GC-OFF support. + * + * @return String indicating GC6/GC-OFF support status. + */ +static const char* RmGetGpuGcxSupport( + OBJGPU *pGpu, + NvBool bGcxTypeGC6 +) +{ + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED)) + { + return "Not Supported"; + } + + if (bGcxTypeGC6) + { + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_SUPPORTED)) + { + return "Supported"; + } + } + else + { + if ((pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED)) || + (pGpu->getProperty(pGpu, PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED))) + { + return "Supported"; + } + } + + return "Not Supported"; +} + +/*! + * @brief Function to increment/decrement global Gcoff disallow refcount. + * + * @params[in] pOsGpuInfo OS specific GPU information pointer. + * @params[in] bIsGcoffDisallow If true, increase refcount else decrease. + */ +void osClientGcoffDisallowRefcount( + OS_GPU_INFO *pOsGpuInfo, + NvBool bIsGcoffDisallow +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(pOsGpuInfo); + + if (nvp->dynamic_power.mode == NV_DYNAMIC_PM_NEVER) + { + return; + } + + acquireDynamicPowerMutex(nvp); + + if (bIsGcoffDisallow) + { + nvp->dynamic_power.clients_gcoff_disallow_refcount++; + } + else + { + nvp->dynamic_power.clients_gcoff_disallow_refcount--; + } + + releaseDynamicPowerMutex(nvp); +} + +/*! + * @brief Implements the NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF RmControl + * request. + * + * @param[in] pSubdevice + * @param[in,out] pParams + * + * @return + * NV_OK Success + * NV_ERR_INVALID_ARGUMENT Invalid pParams->action + * NV_ERR_INVALID_OBJECT_HANDLE Invalid Object handle + * NV_ERR_OBJECT_NOT_FOUND Object not found + */ +NV_STATUS +subdeviceCtrlCmdOsUnixAllowDisallowGcoff_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS *pParams +) +{ + NV_STATUS status; + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + + if (pParams->action == NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_ALLOW) + { + if (pSubdevice->bGcoffDisallowed) + { + pSubdevice->bGcoffDisallowed = NV_FALSE; + osClientGcoffDisallowRefcount(pGpu->pOsGpuInfo, NV_FALSE); + status = NV_OK; + } + else + { + NV_ASSERT(0); + status = NV_ERR_INVALID_ARGUMENT; + } + } + else if (pParams->action == NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_DISALLOW) + { + if (!pSubdevice->bGcoffDisallowed) + { + pSubdevice->bGcoffDisallowed = NV_TRUE; + osClientGcoffDisallowRefcount(pGpu->pOsGpuInfo, NV_TRUE); + status = NV_OK; + } + else + { + NV_ASSERT(0); + status = NV_ERR_INVALID_ARGUMENT; + } + } + else + { + status = NV_ERR_INVALID_ARGUMENT; + } + + return status; +} + +/*! + * @brief Read and Parse the Dynamic Power Management regkey. + * This function modifies the default value of regkey to either enable + * or disable RTD3 as per System form factor and GPU architecture. + * + * @param[in] pNv nv_state_t pointer. + * @param[out] pRegkeyValue Original value of regkey. + * @param[out] pOption Modified value of regkey. + * + * @return NV_STATUS code. + */ + +#define NV_PMC_BOOT_42_CHIP_ID_GA102 0x00000172 + +static NV_STATUS +rmReadAndParseDynamicPowerRegkey +( + nv_state_t *pNv, + NvU32 *pRegkeyValue, + NvU32 *pOption +) +{ + NV_STATUS status; + NvU32 chipId; + nv_priv_t *pNvp = NV_GET_NV_PRIV(pNv); + + status = osReadRegistryDword(NULL, NV_REG_DYNAMIC_POWER_MANAGEMENT, pRegkeyValue); + + if (status != NV_OK) + return status; + + // If User has set some value, honor that value + if (*pRegkeyValue != NV_REG_DYNAMIC_POWER_MANAGEMENT_DEFAULT) + { + *pOption = *pRegkeyValue; + return NV_OK; + } + + chipId = decodePmcBoot42ChipId(pNvp->pmc_boot_42); + + // From GA102+, we enable RTD3 only if system is found to be Notebook + if ((chipId >= NV_PMC_BOOT_42_CHIP_ID_GA102) && + (rm_is_system_notebook())) + { + *pOption = NV_REG_DYNAMIC_POWER_MANAGEMENT_FINE; + return NV_OK; + } + + // For Tegra PCI iGPU, support GPU Rail-Gating feature + if (pNv->supports_tegra_igpu_rg) + { + *pOption = NV_REG_DYNAMIC_POWER_MANAGEMENT_FINE; + return NV_OK; + } + + *pOption = NV_REG_DYNAMIC_POWER_MANAGEMENT_NEVER; + return NV_OK; +} +#undef NV_PMC_BOOT_42_CHIP_ID_GA102 + +/*! + * @brief Initialize state related to Tegra iGPU dynamic power management. + * Called once per GPU during driver initialization. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + */ +void NV_API_CALL rm_init_tegra_dynamic_power_management( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + void *fp; + + if (!nv->supports_tegra_igpu_rg) + return; + + NV_ENTER_RM_RUNTIME(sp,fp); + + portMemSet(&nvp->dynamic_power, 0, sizeof(nvp->dynamic_power)); + + nv->is_tegra_pci_igpu_rg_enabled = NV_FALSE; + + NV_PRINTF(LEVEL_INFO, + "NVRM: Tegra PCI iGPU detected, Rail-Gating is supported.\n"); + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +void rm_check_s0ix_regkey_and_platform_support(void) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + NvU32 data; + NvBool status = ((nv_platform_supports_s0ix()) && + ((osReadRegistryDword(NULL, NV_REG_ENABLE_S0IX_POWER_MANAGEMENT, &data) == NV_OK) && (data == 1))); + + pSys->setProperty(pSys, PDB_PROP_SYS_SUPPORTS_S0IX, status); +} + +/*! + * @brief Initialize state related to dynamic power management. + * Called once per GPU during driver initialization. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + */ +void NV_API_CALL rm_init_dynamic_power_management( + nvidia_stack_t *sp, + nv_state_t *nv, + NvBool bPr3AcpiMethodPresent +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvU32 option = NV_REG_DYNAMIC_POWER_MANAGEMENT_NEVER; + NvU32 gcOffMaxFbSizeMb; + void *fp; + NvBool bUefiConsole; + NvU32 status; + NvU32 regkeyValue; + NvBool bIsTegraPciIgpuRgSupported = nv->supports_tegra_igpu_rg; + + NV_ENTER_RM_RUNTIME(sp,fp); + + /* + * Program an impossible value so that we show correct status + * during procfs read of runtime D3 status. + */ + nvp->dynamic_power.dynamic_power_regkey = 0xFFFFFFFFu; + + /* + * Dynamic power management will be disabled in either of + * following 3 cases: + * 1. The driver does not support dynamic PM for this + * distro/kernel version. + * 2. _PR3 ACPI method is not supported by upstream port of GPU. + * 3. This feature is not enabled by regkey. + * Also see NOTE + */ + status = rmReadAndParseDynamicPowerRegkey(nv, ®keyValue, &option); + + if (status == NV_OK) + { + nvp->dynamic_power.dynamic_power_regkey = regkeyValue; + } + + nvp->pr3_acpi_method_present = bPr3AcpiMethodPresent; + if (!nv_dynamic_power_available(nv) || (status != NV_OK) || + (!bPr3AcpiMethodPresent && !bIsTegraPciIgpuRgSupported)) + { + NV_PRINTF(LEVEL_NOTICE, + "%s: Disabling dynamic power management either due to lack" + " of system support or due to error (%d) in reading regkey." + "\n", __FUNCTION__, status); + option = NV_REG_DYNAMIC_POWER_MANAGEMENT_NEVER; + } + + /* + * Read the OS registry for Maximum FB size during GCOFF based dynamic PM. + * This will be capped to GCOFF_DYNAMIC_PM_MAX_FB_SIZE_MB. + */ + if (osReadRegistryDword(NULL, + NV_REG_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD, + &gcOffMaxFbSizeMb) == NV_OK) + { + if (gcOffMaxFbSizeMb > GCOFF_DYNAMIC_PM_MAX_FB_SIZE_MB) + gcOffMaxFbSizeMb = GCOFF_DYNAMIC_PM_MAX_FB_SIZE_MB; + } + else + { + gcOffMaxFbSizeMb = GCOFF_DYNAMIC_PM_MAX_FB_SIZE_MB; + } + + nvp->dynamic_power.gcoff_max_fb_size = + (NvU64)gcOffMaxFbSizeMb * 1024 * 1024; + + nvp->dynamic_power.mutex = portSyncMutexCreate(portMemAllocatorGetGlobalNonPaged()); + if (nvp->dynamic_power.mutex == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "%s: failed to create power mutex\n", __FUNCTION__); + nvp->dynamic_power.mode = NV_DYNAMIC_PM_NEVER; + goto done; + } + + switch (option) + { + case NV_REG_DYNAMIC_POWER_MANAGEMENT_FINE: + nvp->dynamic_power.mode = NV_DYNAMIC_PM_FINE; + break; + case NV_REG_DYNAMIC_POWER_MANAGEMENT_COARSE: + nvp->dynamic_power.mode = NV_DYNAMIC_PM_COARSE; + break; + default: + nv_printf(LEVEL_ERROR, + "NVRM: Unknown DynamicPowerManagement value '%u' specified; " + "disabling dynamic power management.\n", option); + // fallthrough + case NV_REG_DYNAMIC_POWER_MANAGEMENT_NEVER: + nvp->dynamic_power.mode = NV_DYNAMIC_PM_NEVER; + bIsTegraPciIgpuRgSupported = NV_FALSE; + break; + } + + // Enable RTD3 infrastructure from OS side. + if ((nvp->dynamic_power.mode == NV_DYNAMIC_PM_FINE) && + (nvp->dynamic_power.dynamic_power_regkey == NV_REG_DYNAMIC_POWER_MANAGEMENT_DEFAULT)) + { + // Enable Dynamic Rail-Gating for Tegra PCI iGPU + if (bIsTegraPciIgpuRgSupported) + { + if (nv_pci_tegra_pm_init(nv)) + { + nv_printf(NV_DBG_INFO, "NVRM: Tegra PCI iGPU railgating is enabled\n"); + nv->is_tegra_pci_igpu_rg_enabled = NV_TRUE; + + // Allow runtime suspend for Tegra PCI iGPU device with RG successfully enabled. + nv_allow_runtime_suspend(nv); + } + } + else + { + // Allow runtime suspend for the GPU which is not Tegra PCI iGPU device. + nv_allow_runtime_suspend(nv); + } + } + + // UEFI case: where console is driven by GOP driver. + bUefiConsole = rm_get_uefi_console_status(nv); + + nv->console_device = bUefiConsole || nv->primary_vga; + + // + // Initialize refcount as 1 and state as IN_USE. + // rm_enable_dynamic_power_management() will decrease the refcount + // and change state to IDLE_INDICATED, if all prerequisites are met. + // + nvp->dynamic_power.refcount = 1; + nv_dynamic_power_state_transition(nv, NV_DYNAMIC_POWER_STATE_UNKNOWN, + NV_DYNAMIC_POWER_STATE_IN_USE); +done: + NV_EXIT_RM_RUNTIME(sp,fp); +} + +/*! + * @brief Clean up state related to dynamic power management. + * Called during driver removal. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + */ +void NV_API_CALL rm_cleanup_dynamic_power_management( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + void *fp; + NvBool ret; + + NV_ENTER_RM_RUNTIME(sp,fp); + + // Disable RTD3 infrastructure from OS side. + if (((nvp->dynamic_power.mode == NV_DYNAMIC_PM_FINE) && + (nvp->dynamic_power.dynamic_power_regkey == NV_REG_DYNAMIC_POWER_MANAGEMENT_DEFAULT)) || + nv->is_tegra_pci_igpu_rg_enabled) + { + nv_disallow_runtime_suspend(nv); + + // Disable Dynamic Rail-Gating for Tegra PCI iGPU + if (nv->is_tegra_pci_igpu_rg_enabled) + { + nv_pci_tegra_pm_deinit(nv); + nv->is_tegra_pci_igpu_rg_enabled = NV_FALSE; + nv_printf(NV_DBG_INFO, "NVRM: Tegra PCI iGPU railgating is disabled\n"); + } + } + + nv_dynamic_power_state_t old_state = nvp->dynamic_power.state; + + switch (old_state) + { + case NV_DYNAMIC_POWER_STATE_IDLE_INDICATED: + nv_indicate_not_idle(nv); + /* fallthrough */ + case NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED: + case NV_DYNAMIC_POWER_STATE_IDLE_INSTANT: + ret = nv_dynamic_power_state_transition(nv, old_state, + NV_DYNAMIC_POWER_STATE_IN_USE); + /* + * Nothing else should be running asynchronous to teardown that could + * change the state so this should always succeed. + */ + NV_ASSERT(ret); + break; + case NV_DYNAMIC_POWER_STATE_IN_USE: + break; + case NV_DYNAMIC_POWER_STATE_UNKNOWN: + NV_ASSERT(0); + break; + } + + if (nvp->dynamic_power.mutex) + { + portSyncMutexDestroy(nvp->dynamic_power.mutex); + nvp->dynamic_power.mutex = NULL; + } + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +/*! + * @brief Initialize the dynamic power management refcount and enable GPUOFF, + * if all prerequisites are met. + * Called once per GPU during driver initialization. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + */ +void NV_API_CALL rm_enable_dynamic_power_management( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + /* + * If dynamic power management is enabled and device is not driving console, + * then dynamic power management can be engaged (since we're not + * using the GPU yet, so it's okay to power it off). + */ + if ((nvp->dynamic_power.mode != NV_DYNAMIC_PM_NEVER) && !nv->console_device) + { + os_unref_dynamic_power(nv, NV_DYNAMIC_PM_COARSE); + } + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +/* + * @brief Increment the dynamic power refcount to prevent the GPU from being + * powered off until a corresponding os_unref_dynamic_power() call is made. + * These two calls must always be balanced in pairs. + * + * This call may block until the GPU is powered on. + * + * The caller must not be holding the GPU lock, but may be holding the API + * lock. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] mode Dynamic power mode this refcount bump is used for. + */ +NV_STATUS +os_ref_dynamic_power( + nv_state_t *nv, + nv_dynamic_power_mode_t mode +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NV_STATUS status = NV_OK; + NvS32 ref; + + if (nvp == NULL) + { + NV_ASSERT(nv->removed); + return NV_OK; + } + + if (mode > nvp->dynamic_power.mode) + { + return NV_OK; + } + + acquireDynamicPowerMutex(nvp); + + ref = nvp->dynamic_power.refcount++; + + NV_ASSERT(ref >= 0); + + if (ref > 0) + { + NV_ASSERT(nvp->dynamic_power.state == NV_DYNAMIC_POWER_STATE_IN_USE); + } + else + { + /* + * Just transitioned from 0 -> 1. + * The current dynamic power state could be any of: + * + * - IDLE_INDICATED: call nv_indicate_not_idle() to ensure + * the GPU is at full power and ready to be used. + * + * - IDLE_INSTANT/IDLE_SUSTAINED: transition to IN_USE. + * Note that in these states, callbacks may be operating + * asynchronously, so care has to be taken to retry the write if it + * fails. + */ + + nv_dynamic_power_state_t old_state = nvp->dynamic_power.state; + NvBool ret; + + switch (old_state) + { + default: + case NV_DYNAMIC_POWER_STATE_IN_USE: + NV_PRINTF(LEVEL_ERROR, "Unexpected dynamic power state 0x%x\n", + old_state); + /* fallthrough */ + case NV_DYNAMIC_POWER_STATE_IDLE_INDICATED: + status = nv_indicate_not_idle(nv); + if (status != NV_OK) + { + nvp->dynamic_power.refcount--; + break; + } + if (nvp->dynamic_power.deferred_idle_enabled) + { + RmScheduleCallbackForIdlePreConditions(NV_GET_NV_PRIV_PGPU(nv)); + } + /* fallthrough */ + case NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED: + case NV_DYNAMIC_POWER_STATE_IDLE_INSTANT: + do { + ret = nv_dynamic_power_state_transition(nv, old_state, NV_DYNAMIC_POWER_STATE_IN_USE); + if (!ret) + { + old_state = nvp->dynamic_power.state; + NV_ASSERT(old_state == NV_DYNAMIC_POWER_STATE_IDLE_INSTANT || + old_state == NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED); + } + } while (!ret); + break; + } + } + + releaseDynamicPowerMutex(nvp); + + return status; +} + +/* + * @brief This function queries the dynamic boost support. + * This function returns -1 in case it failed to query the + * dynamic boost support. It returns 1 if dynamic boost is + * supported and returns 0 if dynamic boost is not supported. + * + * The caller must hold the API lock before calling this + * function. + * + * @param[in] nv nv_state_t pointer. + */ +static int os_get_dynamic_boost_support( + nv_state_t *nv +) +{ + NV_STATUS status = NV_OK; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS *pNvpcfParams; + OBJGPU *pGpu; + int ret; + + status = os_alloc_mem((void**)&pNvpcfParams, sizeof(*pNvpcfParams)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to allocate memory\n"); + ret = -1; + goto end; + } + + pGpu = NV_GET_NV_PRIV_PGPU(nv); + pNvpcfParams->gpuId = pGpu->gpuId; + pNvpcfParams->subFunc = + NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE; + status = pRmApi->Control(pRmApi, + nv->rmapi.hClient, + nv->rmapi.hClient, + NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO, + (void*)pNvpcfParams, + sizeof(*pNvpcfParams)); + if (status == NV_OK) + { + ret = 1; + } + else if (status == NV_ERR_NOT_SUPPORTED) + { + ret = 0; + } + else + { + ret = -1; + } + + os_free_mem(pNvpcfParams); +end: + return ret; +} + +/*! + * @brief Wrapper around os_ref_dynamic_power() suitable for use from the + * per-OS layers. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + * @param[in] mode Dynamic power mode this refcount bump is used for. + */ +NV_STATUS NV_API_CALL rm_ref_dynamic_power( + nvidia_stack_t *sp, + nv_state_t *nv, + nv_dynamic_power_mode_t mode +) +{ + NV_STATUS status; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + status = os_ref_dynamic_power(nv, mode); + + NV_EXIT_RM_RUNTIME(sp,fp); + + return status; +} + +/*! + * @brief Decrement the dynamic power refcount to release an earlier + * requirement that the GPU be powered on made by calling + * os_ref_dynamic_power(). + * These two calls must always be balanced in pairs. + * + * This call may block until the GPU is powered on. + * + * The caller must not be holding the GPU lock, but may be holding the API + * lock. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] mode Dynamic power mode this refcount bump is used for. + */ +void +os_unref_dynamic_power( + nv_state_t *nv, + nv_dynamic_power_mode_t mode +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvS32 ref; + + if (nvp == NULL) + { + NV_ASSERT(nv->removed); + return; + } + + if (mode > nvp->dynamic_power.mode) + { + return; + } + + acquireDynamicPowerMutex(nvp); + + ref = --nvp->dynamic_power.refcount; + + NV_ASSERT(ref >= 0); + + if (ref == 0) { + NvBool ret; + + /* + * Just transitioned from 1 -> 0. We should have been in the IN_USE + * state previously; now we transition to an idle state: "instant" idle + * if deferred idle is enabled; otherwise indicate idle immediately. + * + * Nothing should be asynchronously changing the state from IN_USE, + * so the state transitions are not expected to fail. + */ + + NV_ASSERT(nvp->dynamic_power.state == NV_DYNAMIC_POWER_STATE_IN_USE); + + if (nvp->dynamic_power.deferred_idle_enabled) + { + ret = nv_dynamic_power_state_transition(nv, NV_DYNAMIC_POWER_STATE_IN_USE, + NV_DYNAMIC_POWER_STATE_IDLE_INSTANT); + NV_ASSERT(ret); + } + else + { + nv_indicate_idle(nv); + ret = nv_dynamic_power_state_transition(nv, NV_DYNAMIC_POWER_STATE_IN_USE, + NV_DYNAMIC_POWER_STATE_IDLE_INDICATED); + NV_ASSERT(ret); + } + } + + releaseDynamicPowerMutex(nvp); +} + +/*! + * @brief Wrapper around os_unref_dynamic_power() suitable for use from the + * per-OS layers. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + * @param[in] mode Dynamic power mode this refcount bump is used for. + */ +void NV_API_CALL rm_unref_dynamic_power( + nvidia_stack_t *sp, + nv_state_t *nv, + nv_dynamic_power_mode_t mode +) +{ + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + os_unref_dynamic_power(nv, mode); + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +/*! + * @brief Wrapper around os_ref_dynamic_power() suitable for use from core RM. + * + * @params[in] pOsGpuInfo OS specific GPU information pointer + */ +NV_STATUS osRefGpuAccessNeeded( + OS_GPU_INFO *pOsGpuInfo +) +{ + return os_ref_dynamic_power(pOsGpuInfo, NV_DYNAMIC_PM_FINE); +} + +/*! + * @brief Wrapper around os_unref_dynamic_power() suitable for use from core RM. + * + * @params[in] pOsGpuInfo OS specific GPU information pointer + */ +void osUnrefGpuAccessNeeded( + OS_GPU_INFO *pOsGpuInfo +) +{ + os_unref_dynamic_power(pOsGpuInfo, NV_DYNAMIC_PM_FINE); +} + +/*! + * @brief Check if GCx is supported on current pstate and if engines are idle. + * + * @param[in] pGpu OBJGPU pointer. + */ +static NvBool RmCheckForGcxSupportOnCurrentState( + OBJGPU *pGpu +) +{ + NV_STATUS status = NV_OK; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS entryPrerequisiteParams; + + portMemSet(&entryPrerequisiteParams, 0, sizeof(entryPrerequisiteParams)); + + status = pRmApi->Control(pRmApi, + nv->rmapi.hClient, + nv->rmapi.hSubDevice, + NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE, + (void*)&entryPrerequisiteParams, + sizeof(entryPrerequisiteParams)); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "NVRM, Failed to get GCx pre-requisite, status=0x%x\n", + status); + return NV_FALSE; + } + + return entryPrerequisiteParams.bIsGC6Satisfied || entryPrerequisiteParams.bIsGCOFFSatisfied; +} + +/*! + * @brief: Work item to actually remove the idle holdoff which was applied + * on GC6 exit. + * This workitem is scheduled after the timeout limit for idle holdoff is + * finished. + * + * Queue with lock flags: + * bLockGpuGroupSubdevice + * + * @param[in] gpuInstance GPU instance ID. + * @param[in] pArgs Unused callback closure. + */ +static void RmRemoveIdleHoldoff( + NvU32 gpuInstance, + void *pArgs +) +{ + OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + if (nvp->dynamic_power.b_idle_holdoff == NV_TRUE) + { + if ((RmCheckForGcxSupportOnCurrentState(pGpu) == NV_TRUE) || + (nvp->dynamic_power.idle_precondition_check_callback_scheduled)) + { + nv_indicate_idle(nv); + nvp->dynamic_power.b_idle_holdoff = NV_FALSE; + } + else + { + RmScheduleCallbackToRemoveIdleHoldoff(pGpu); + } + } +} + +/*! + * @brief Timer callback to schedule a work item to remove idle hold off + * that was applied after GC6 exit. + * + * @param[in] pCallbackData OBJGPU pointer (with void pointer type). + */ +static void timerCallbackToRemoveIdleHoldoff( + void *pCallbackData +) +{ + NV_STATUS status = NV_OK; + OBJGPU *pGpu = reinterpretCast(pCallbackData, OBJGPU *); + + status = osQueueWorkItem(pGpu, + RmRemoveIdleHoldoff, + NULL, + (OsQueueWorkItemFlags){.bLockGpuGroupSubdevice = NV_TRUE}); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Queuing of remove idle holdoff work item failed with status : 0x%x\n", + status); + } +} + +/*! + * @brief Timer callback to check if all idle conditions remain met and + * if so schedule a work item to indicate the GPU is idle. + * + * @param[in] pCallbackData OBJGPU pointer (with void pointer type). + */ +static void timerCallbackToIndicateIdle( + void *pCallbackData +) +{ + OBJGPU *pGpu = reinterpretCast(pCallbackData, OBJGPU *); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + nv_acquire_mmap_lock(nv); + + if (nv_get_all_mappings_revoked_locked(nv) && + nvp->dynamic_power.state == NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED && + RmCanEnterGcxUnderGpuLock(pGpu)) + { + osQueueWorkItem(pGpu, + RmIndicateIdle, + NULL, + (OsQueueWorkItemFlags){0}); + } + else + { + if (nvp->dynamic_power.state == NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED) + { + /* + * Something used the GPU between when we last sampled and now. + * Go back to the "instant" state to start waiting from scratch. + */ + nv_dynamic_power_state_transition(nv, NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED, + NV_DYNAMIC_POWER_STATE_IDLE_INSTANT); + } + + RmScheduleCallbackForIdlePreConditionsUnderGpuLock(pGpu); + } + + nv_release_mmap_lock(nv); +} + +/*! + * @brief Timer callback to periodically check if all idle preconditions are + * met. If so, the dynamic power state is advanced from IDLE_INSTANT to + * IDLE_SUSTAINED, or (if already in the IDLE_SUSTAINED state) mappings are + * revoked and timerCallbackToIndicateIdle() is scheduled. + * + * @param[in] pCallbackData OBJGPU pointer (with void pointer type). + */ +static void timerCallbackForIdlePreConditions( + void *pCallbackData +) +{ + OBJGPU *pGpu = reinterpretCast(pCallbackData, OBJGPU *); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + nvp->dynamic_power.idle_precondition_check_callback_scheduled = NV_FALSE; + + /* + * Note: It is not safe to take the dynamic power mutex here. + * Lock ordering dictates that the dynamic power mutex must be taken before + * the GPU lock, and this function is called with the GPU lock held. + * + * Therefore, this function is careful about *only* triggering specific + * transitions: + * NV_DYNAMIC_POWER_STATE_IDLE_INSTANT -> NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED + * NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED -> NV_DYNAMIC_POWER_STATE_IDLE_INSTANT + * + * Other codepaths are resilient to these state transitions occurring + * asynchronously. The state transition itself is done with an atomic + * compare and swap, so there should be no danger of inadvertently + * triggering a transition from a different state due to a + * read-modify-write or "time of check to time of use" (TOCTTOU) race + * condition. + */ + + if (nvp->dynamic_power.state != NV_DYNAMIC_POWER_STATE_IN_USE) + { + if (RmCanEnterGcxUnderGpuLock(pGpu)) + { + nv_dynamic_power_state_t state = nvp->dynamic_power.state; + switch (state) + { + case NV_DYNAMIC_POWER_STATE_UNKNOWN: + NV_ASSERT(0); + /* fallthrough */ + case NV_DYNAMIC_POWER_STATE_IDLE_INDICATED: + NV_PRINTF(LEVEL_ERROR, "unexpected dynamic power state 0x%x\n", + nvp->dynamic_power.state); + /* fallthrough */ + case NV_DYNAMIC_POWER_STATE_IN_USE: + break; + case NV_DYNAMIC_POWER_STATE_IDLE_INSTANT: + nv_dynamic_power_state_transition(nv, NV_DYNAMIC_POWER_STATE_IDLE_INSTANT, + NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED); + break; + case NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED: + RmQueueIdleSustainedWorkitem(pGpu); + return; + } + + } + else + { + if (nvp->dynamic_power.state == NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED) + { + /* + * Something used the GPU between when we last sampled and now. + * Go back to the "instant" state to start waiting from scratch. + */ + nv_dynamic_power_state_transition(nv, NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED, + NV_DYNAMIC_POWER_STATE_IDLE_INSTANT); + } + } + } + RmScheduleCallbackForIdlePreConditionsUnderGpuLock(pGpu); +} + +/*! + * @brief Cancel any in-flight callback to remove idle holdoff. + * + * @param[in] pGpu OBJGPU pointer. + */ +static void RmCancelCallbackToRemoveIdleHoldoff( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + TMR_EVENT_GENERAL_PARAMS cancelParams; + + if (NvP64_VALUE(nvp->dynamic_power.remove_idle_holdoff) != NULL) + { + portMemSet(&cancelParams, 0, sizeof(cancelParams)); + + cancelParams.pEvent = nvp->dynamic_power.remove_idle_holdoff; + + tmrCtrlCmdEventCancel(pGpu, &cancelParams); + } +} + +/*! + * @brief Cancel any in-flight timer callbacks. + * + * @param[in] pGpu OBJGPU pointer. + */ +static void RmCancelDynamicPowerCallbacks( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + TMR_EVENT_GENERAL_PARAMS cancelParams; + + if (NvP64_VALUE(nvp->dynamic_power.idle_precondition_check_event) != NULL) + { + // Cancel precondition check callback. + portMemSet(&cancelParams, 0, sizeof(cancelParams)); + + cancelParams.pEvent = nvp->dynamic_power.idle_precondition_check_event; + + tmrCtrlCmdEventCancel(pGpu, &cancelParams); + } + + if (NvP64_VALUE(nvp->dynamic_power.indicate_idle_event) != NULL) + { + // Cancel callback to indicate idle + portMemSet(&cancelParams, 0, sizeof(cancelParams)); + + cancelParams.pEvent = nvp->dynamic_power.indicate_idle_event; + + tmrCtrlCmdEventCancel(pGpu, &cancelParams); + } + + RmCancelCallbackToRemoveIdleHoldoff(pGpu); + + nvp->dynamic_power.idle_precondition_check_callback_scheduled = NV_FALSE; +} + +/*! + * @brief Free timer events allocated by CreateDynamicPowerCallbacks() + * + * @param[in] pGpu OBJGPU pointer. + */ +static void RmDestroyDynamicPowerCallbacks( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + TMR_EVENT_GENERAL_PARAMS destroyParams; + + if (NvP64_VALUE(nvp->dynamic_power.idle_precondition_check_event) != NULL) + { + // Destroy precondition check callback. + portMemSet(&destroyParams, 0, sizeof(destroyParams)); + + destroyParams.pEvent = nvp->dynamic_power.idle_precondition_check_event; + + tmrCtrlCmdEventDestroy(pGpu, &destroyParams); + nvp->dynamic_power.idle_precondition_check_event = NvP64_NULL; + } + + if (NvP64_VALUE(nvp->dynamic_power.indicate_idle_event) != NULL) + { + // Destroy callback to indicate idle + portMemSet(&destroyParams, 0, sizeof(destroyParams)); + + destroyParams.pEvent = nvp->dynamic_power.indicate_idle_event; + + tmrCtrlCmdEventDestroy(pGpu, &destroyParams); + nvp->dynamic_power.indicate_idle_event = NvP64_NULL; + } + + if (NvP64_VALUE(nvp->dynamic_power.remove_idle_holdoff) != NULL) + { + // Destroy callback to decrease kernel refcount + portMemSet(&destroyParams, 0, sizeof(destroyParams)); + + destroyParams.pEvent = nvp->dynamic_power.remove_idle_holdoff; + + tmrCtrlCmdEventDestroy(pGpu, &destroyParams); + nvp->dynamic_power.remove_idle_holdoff = NvP64_NULL; + } + + nvp->dynamic_power.deferred_idle_enabled = NV_FALSE; +} + +/* + * @brief Adds a GPU to dynamicPowerSupportGpuMask + * + * @param[in] instance + */ +static void AddGpuDynamicPowerSupported +( + NvU32 instance +) +{ + dynamicPowerSupportGpuMask |= NVBIT(instance); +} + +/* + * @brief Removes a GPU from dynamicPowerSupportGpuMask + * + * @param[in] instance + */ +static void RemoveGpuDynamicPowerSupported +( + NvU32 instance +) +{ + dynamicPowerSupportGpuMask &= ~NVBIT(instance); +} + +/* + * @brief queries dynamicPowerSupportGpuMask + * + * @param[in] void + */ +NvU32 osGetDynamicPowerSupportMask +( + void +) +{ + return dynamicPowerSupportGpuMask; +} + +/*! + * @brief Cancel any outstanding callbacks, and free RM resources allocated by + * RmInitDeferredDynamicPowerManagement(). + * + * @param[in] nv nv_state_t pointer. + */ +void RmDestroyDeferredDynamicPowerManagement( + nv_state_t *nv +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + + // + // Re-instate the dynamic power mode to fine if it was + // disabled due to lack of platform support + // + if (nvp->dynamic_power.b_fine_not_supported == NV_TRUE) + { + nvp->dynamic_power.mode = NV_DYNAMIC_PM_FINE; + nvp->dynamic_power.b_fine_not_supported = NV_FALSE; + } + + // + // Before cancelling and destroying the callbacks, make sure to + // remove the idle holfoff that was applied during gc6 exit. + // + if (nvp->dynamic_power.b_idle_holdoff == NV_TRUE) + { + nv_indicate_idle(nv); + nvp->dynamic_power.b_idle_holdoff = NV_FALSE; + } + + RmCancelDynamicPowerCallbacks(pGpu); + RmDestroyDynamicPowerCallbacks(pGpu); + RemoveGpuDynamicPowerSupported(gpuGetInstance(pGpu)); +} + +/*! + * @brief Allocate timer events to call the functions: + * timerCallbackForIdlePreConditions() + * timerCallbackToIndicateIdle() + * + * The callbacks must be scheduled separately. + * + * @param[in] pGpu OBJGPU pointer. + */ +static NV_STATUS CreateDynamicPowerCallbacks( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + TMR_EVENT_SET_PARAMS createEventParams; + NV_STATUS status; + + // Creating PreCondition check callback. + portMemSet(&createEventParams, 0, sizeof(createEventParams)); + + createEventParams.ppEvent = &(nvp->dynamic_power.idle_precondition_check_event); + createEventParams.pTimeProc = NV_PTR_TO_NvP64(timerCallbackForIdlePreConditions); + createEventParams.pCallbackData = NV_PTR_TO_NvP64(pGpu); + createEventParams.flags = TMR_FLAG_USE_OS_TIMER; + + status = tmrCtrlCmdEventCreate(pGpu, &createEventParams); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Error creating dynamic power precondition check callback\n"); + nvp->dynamic_power.idle_precondition_check_event = NvP64_NULL; + nvp->dynamic_power.indicate_idle_event = NvP64_NULL; + nvp->dynamic_power.remove_idle_holdoff = NvP64_NULL; + return status; + } + + // Create callback to indicate idle.. + portMemSet(&createEventParams, 0, sizeof(createEventParams)); + + createEventParams.ppEvent = &(nvp->dynamic_power.indicate_idle_event); + createEventParams.pTimeProc = NV_PTR_TO_NvP64(timerCallbackToIndicateIdle); + createEventParams.pCallbackData = NV_PTR_TO_NvP64(pGpu); + createEventParams.flags = TMR_FLAG_USE_OS_TIMER; + + status = tmrCtrlCmdEventCreate(pGpu, &createEventParams); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Error creating callback to indicate GPU idle\n"); + nvp->dynamic_power.idle_precondition_check_event = NvP64_NULL; + nvp->dynamic_power.indicate_idle_event = NvP64_NULL; + nvp->dynamic_power.remove_idle_holdoff = NvP64_NULL; + return status; + } + + // Create callback to remove idle holdoff + portMemSet(&createEventParams, 0, sizeof(createEventParams)); + + createEventParams.ppEvent = &(nvp->dynamic_power.remove_idle_holdoff); + createEventParams.pTimeProc = NV_PTR_TO_NvP64(timerCallbackToRemoveIdleHoldoff); + createEventParams.pCallbackData = NV_PTR_TO_NvP64(pGpu); + createEventParams.flags = TMR_FLAG_USE_OS_TIMER; + + status = tmrCtrlCmdEventCreate(pGpu, &createEventParams); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Error creating callback to decrease kernel refcount\n"); + nvp->dynamic_power.idle_precondition_check_event = NvP64_NULL; + nvp->dynamic_power.indicate_idle_event = NvP64_NULL; + nvp->dynamic_power.remove_idle_holdoff = NvP64_NULL; + return status; + } + + return NV_OK; +} + +/*! + * @brief Schedule the timerCallbackForIdlePreConditions() function to be called. + * + * If it is already scheduled, the function is a noop. + * + * The GPU lock must be held when calling this function. + * + * @param[in] pGpu OBJGPU pointer. + */ +static void RmScheduleCallbackForIdlePreConditionsUnderGpuLock( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + TMR_EVENT_SCHEDULE_PARAMS scheduleEventParams; + NV_STATUS status; + + NV_ASSERT(rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + + if (nvp->dynamic_power.idle_precondition_check_callback_scheduled) + { + return; + } + + if (NvP64_VALUE(nvp->dynamic_power.idle_precondition_check_event) != NULL) + { + portMemSet(&scheduleEventParams, 0, sizeof(scheduleEventParams)); + + scheduleEventParams.pEvent = nvp->dynamic_power.idle_precondition_check_event; + scheduleEventParams.bUseTimeAbs = NV_FALSE; + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_RG_SUPPORTED)) + { + /* + * iGPU which supports Rail-Gating may want shorter idleness + * threshold to engage the deferred-idle transition. + * Set the threshold for precondition check to 500 ms. + */ + scheduleEventParams.timeNs = IGPU_RG_PRECONDITION_CHECK_TIME; + } + else + { + scheduleEventParams.timeNs = GC6_PRECONDITION_CHECK_TIME; + } + + status = tmrCtrlCmdEventSchedule(pGpu, &scheduleEventParams); + + if (status == NV_OK) + { + nvp->dynamic_power.idle_precondition_check_callback_scheduled = NV_TRUE; + } + else + { + NV_PRINTF(LEVEL_ERROR, "Error scheduling precondition callback\n"); + } + } +} + +/*! + * @brief Schedule the timerCallbackForIdlePreConditions() function to be called. + * + * If it is already scheduled, the function is a noop. + * + * This function takes the GPU lock. + * + * @param[in] pGpu OBJGPU pointer. + */ +static void RmScheduleCallbackForIdlePreConditions( + OBJGPU *pGpu +) +{ + NV_STATUS status; + GPU_MASK gpuMask; + + // LOCK: acquire per device lock + status = rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER, + &gpuMask); + if (status == NV_OK) + { + RmScheduleCallbackForIdlePreConditionsUnderGpuLock(pGpu); + // UNLOCK: release per device lock + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + } +} + +/*! + * @brief Schedule the timerCallbackToIndicateIdle() function to be called. + * + * The GPU lock must be held when calling this function. + * + * @param[in] pGpu OBJGPU pointer. + */ +static void RmScheduleCallbackToIndicateIdle( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + TMR_EVENT_SCHEDULE_PARAMS scheduleEventParams; + NV_STATUS status; + + NV_ASSERT(rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + + if (NvP64_VALUE(nvp->dynamic_power.indicate_idle_event) != NULL) + { + portMemSet(&scheduleEventParams, 0, sizeof(scheduleEventParams)); + + scheduleEventParams.pEvent = nvp->dynamic_power.indicate_idle_event; + scheduleEventParams.bUseTimeAbs = NV_FALSE; + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_RG_SUPPORTED)) + { + /* + * iGPU which supports Rail-Gating may want shorter idleness + * threshold to engage the deferred-idle transition. + * Set the threshold for idle indicate to 700 ms. + */ + scheduleEventParams.timeNs = IGPU_RG_BLOCKER_CHECK_AND_METHOD_FLUSH_TIME; + } + else + { + scheduleEventParams.timeNs = GC6_BAR1_BLOCKER_CHECK_AND_METHOD_FLUSH_TIME; + } + + status = tmrCtrlCmdEventSchedule(pGpu, &scheduleEventParams); + + if (status != NV_OK) + NV_PRINTF(LEVEL_ERROR, "Error scheduling indicate idle callback\n"); + } +} + +/*! + * @brief Schedule the timerCallbackToRemoveIdleHoldoff() function. + * + * The GPU lock must be held when calling this function. + * + * @param[in] pGpu OBJGPU pointer. + */ +static void RmScheduleCallbackToRemoveIdleHoldoff( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + TMR_EVENT_SCHEDULE_PARAMS scheduleEventParams; + NV_STATUS status; + + NV_ASSERT(rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + + if (NvP64_VALUE(nvp->dynamic_power.remove_idle_holdoff) != NULL) + { + portMemSet(&scheduleEventParams, 0, sizeof(scheduleEventParams)); + + scheduleEventParams.pEvent = nvp->dynamic_power.remove_idle_holdoff; + scheduleEventParams.timeNs = GC6_CYCLE_IDLE_HOLDOFF_CHECK_TIME; + scheduleEventParams.bUseTimeAbs = NV_FALSE; + + status = tmrCtrlCmdEventSchedule(pGpu, &scheduleEventParams); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Error scheduling kernel refcount decrement callback\n"); + } + else + { + nvp->dynamic_power.b_idle_holdoff = NV_TRUE; + } + } +} + +/*! + * @brief Check if the system supports RTD3-GC6. + * + * @param[in] pGpu OBJGPU pointer. + */ +static NvBool RmCheckRtd3GcxSupport( + nv_state_t *pNv, + NvBool *bGC6Support, + NvBool *bGCOFFSupport +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(pNv); + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NV_STATUS status; + NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS virtModeParams = { 0 }; + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED)) + { + NV_PRINTF(LEVEL_NOTICE, "RTD3 is not supported for this arch\n"); + return NV_FALSE; + } + + *bGC6Support = pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_SUPPORTED); + *bGCOFFSupport = pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED) || + pGpu->getProperty(pGpu, PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED); + + if (!(*bGC6Support) && + !(*bGCOFFSupport) && + !(pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_RG_SUPPORTED))) + { + NV_PRINTF(LEVEL_NOTICE, + "Disabling RTD3. [GC6 support=%d GCOFF support=%d RG support=%d]\n", + *bGC6Support, + *bGCOFFSupport, + pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_RG_SUPPORTED)); + return NV_FALSE; + } + + status = pRmApi->Control(pRmApi, pNv->rmapi.hClient, pNv->rmapi.hDevice, + NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE, + &virtModeParams, sizeof(virtModeParams)); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to get Virtualization mode, status=0x%x\n", + status); + return NV_FALSE; + } + + if ((virtModeParams.virtualizationMode != NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE) && + (virtModeParams.virtualizationMode != NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS)) + { + NV_PRINTF(LEVEL_NOTICE, "RTD3 is not supported on VM\n"); + return NV_FALSE; + } + + if (!nvp->pr3_acpi_method_present && + !(pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_RG_SUPPORTED))) + { + NV_PRINTF(LEVEL_NOTICE, "RTD3 ACPI support is not available.\n"); + return NV_FALSE; + } + + return NV_TRUE; +} + +/*! + * @brief Allocate resources needed to track deferred power management, and + * schedule the initial periodic callbacks. + * + * @param[in] nv nv_state_t pointer. + */ +static void RmInitDeferredDynamicPowerManagement( + nv_state_t *nv, + NvBool bRtd3Support +) +{ + NV_STATUS status; + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + if (nvp->dynamic_power.mode == NV_DYNAMIC_PM_FINE) + { + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + + if (!bRtd3Support) + { + nvp->dynamic_power.mode = NV_DYNAMIC_PM_NEVER; + nvp->dynamic_power.b_fine_not_supported = NV_TRUE; + NV_PRINTF(LEVEL_NOTICE, "RTD3 is not supported.\n"); + return; + } + AddGpuDynamicPowerSupported(gpuGetInstance(pGpu)); + nvp->dynamic_power.b_fine_not_supported = NV_FALSE; + status = CreateDynamicPowerCallbacks(pGpu); + + if (status == NV_OK) + { + RmScheduleCallbackForIdlePreConditionsUnderGpuLock(pGpu); + + nvp->dynamic_power.deferred_idle_enabled = NV_TRUE; + // RM's default is GCOFF allow + nvp->dynamic_power.clients_gcoff_disallow_refcount = 0; + } + else + { + NV_PRINTF(LEVEL_ERROR, "Failed to register for dynamic power callbacks\n"); + } + } +} + +/*! + * @brief Check if GCOFF state can be used for Power Management. + * + * @param[in] pGpu OBJGPU pointer. + * @param[in] usedFbSize Used FB Allocation size. + * @param[in] bIsDynamicPM If true, check for dynamic PM; otherwise, check + * for system PM (suspend/resume). + * + * returns NV_TRUE if GCOFF state can be used, otherwise NV_FALSE. + * + */ +static NvBool RmCheckForGcOffPM( + OBJGPU *pGpu, + NvU64 usedFbSize, + NvBool bIsDynamicPM +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvU64 gcoff_max_fb_size; + + if (bIsDynamicPM) + { + /* + * GCOFF won't be enaged for Dynamic PM if X server does not allow. + * The dynamic_power.clients_gcoff_disallow_refcount is being accessed + * without acquiring dynamic power mutex since this value can be + * modified only when GPU is in active state. The os_ref_dynamic_power() + * function will be called to hold a reference to the GPU whenever + * RM is processing osClientGcoffDisallowRefcount() calls. This either + * prevents the GPU from going into a low power state or will wait for + * it to be resumed before proceeding. + */ + if (nvp->dynamic_power.clients_gcoff_disallow_refcount != 0) + return NV_FALSE; + + gcoff_max_fb_size = nvp->dynamic_power.gcoff_max_fb_size; + } + else + { + gcoff_max_fb_size = nvp->s0ix_gcoff_max_fb_size; + } + + /* + * GCOFF will be engaged whenever the following necessary preconditions + * are met: + * + * 1. The GCOFF has not been disabled with regkey by setting it to zero. + * 2. Used FB allocation size are within limits. + */ + return (gcoff_max_fb_size > 0) && + (usedFbSize <= gcoff_max_fb_size); +} + +// +// Function to update fixed fbsr modes to support multiple vairants such as +// GCOFF and cuda S3/resume. +// +static void +RmUpdateFixedFbsrModes(OBJGPU *pGpu) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERING)) + { + pMemoryManager->fixedFbsrModesMask = NVBIT(FBSR_TYPE_DMA); + } + else if (nv->preserve_vidmem_allocations) + { + pMemoryManager->fixedFbsrModesMask = NVBIT(FBSR_TYPE_FILE); + } +} + +static NV_STATUS +RmPowerManagement( + OBJGPU *pGpu, + nv_pm_action_t pmAction +) +{ + // default to NV_OK. there may cases where resman is loaded, but + // no devices are allocated (we're still at the console). in these + // cases, it's fine to let the system do whatever it wants. + NV_STATUS rmStatus = NV_OK; + + if (pGpu) + { + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvBool bcState = gpumgrGetBcEnabledStatus(pGpu); + Intr *pIntr = GPU_GET_INTR(pGpu); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + if ((pmAction == NV_PM_ACTION_HIBERNATE) || (pmAction == NV_PM_ACTION_STANDBY)) + { + // + // pFb object store the FBSR mode through which FB state unload has happened, + // so os layer doesn't need to set FBSR mode on resume. + // + RmUpdateFixedFbsrModes(pGpu); + } + + switch (pmAction) + { + case NV_PM_ACTION_HIBERNATE: + nvp->pm_state.InHibernate = NV_TRUE; + nvp->pm_state.IntrEn = intrGetIntrEn(pIntr); + intrSetIntrEn(pIntr, INTERRUPT_TYPE_DISABLED); + gpumgrSetBcEnabledStatus(pGpu, NV_FALSE); + + rmStatus = gpuEnterHibernate(pGpu); + gpumgrSetBcEnabledStatus(pGpu, bcState); + + break; + + case NV_PM_ACTION_STANDBY: + nvp->pm_state.InHibernate = NV_FALSE; + nvp->pm_state.IntrEn = intrGetIntrEn(pIntr); + intrSetIntrEn(pIntr, INTERRUPT_TYPE_DISABLED); + gpumgrSetBcEnabledStatus(pGpu, NV_FALSE); + + rmStatus = gpuEnterStandby(pGpu); + gpumgrSetBcEnabledStatus(pGpu, bcState); + + break; + + case NV_PM_ACTION_RESUME: + gpumgrSetBcEnabledStatus(pGpu, NV_FALSE); + + if (nvp->pm_state.InHibernate) + { + gpuResumeFromHibernate(pGpu); + } + else + { + gpuResumeFromStandby(pGpu); + } + intrSetIntrEn(pIntr, nvp->pm_state.IntrEn); + gpumgrSetBcEnabledStatus(pGpu, bcState); + NvU32 ac_plugged = 0; + + if (IsMobile(pGpu)) + { + if (nv_acpi_get_powersource(&ac_plugged) == NV_OK) + { + // + // As we have already acquired API and GPU lock here, we are + // directly calling RmPowerSourceChangeEvent. + // + RmPowerSourceChangeEvent(nv, !ac_plugged); + } + RmRequestDNotifierState(nv); + } + break; + + default: + rmStatus = NV_ERR_INVALID_ARGUMENT; + break; + } + + pMemoryManager->fixedFbsrModesMask = 0; + } + + return rmStatus; +} + +/*! + * @brief Call core RM to perform the GCx (GC6/GCOF) entry sequence (before + * powering off the GPU) or exit sequence (after powering the GPU back on). + * + * The GPU lock should be held when calling this function. + * + * @param[in] pGpu OBJGPU pointer. + * @param[in] bEnter If true, perform entry sequence; exit sequence + * otherwise. + * @param[in] bIsDynamicPM If true, it is for dynamic PM; otherwise, it is + * for system PM (suspend/resume). + * + * @return NV_STATUS code indicating if the operation was successful. + */ +NV_STATUS RmGcxPowerManagement( + OBJGPU *pGpu, + NvBool bEnter, + NvBool bIsDynamicPM, + NvBool *bTryAgain +) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NV_STATUS status = NV_OK; + + if (pGpu->acpiMethodData.jtMethodData.bSBIOSCaps && + !pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_MOBILE)) + { + // + // AML override is expected only on NB platforms to support GCOFF-1.0( + // which is legacy GCOFF) and GC6-3.0 + // GC6 3.0 is possible without AML override but due to changes required + // for GCOFF-1.0 in SBIOS & HW, AML override is needed for GC6-3.0 also. + // + NV_PRINTF(LEVEL_INFO,"AML overrides present in Desktop"); + } + + nv->d0_state_in_suspend = NV_FALSE; + + if (bEnter) + { + NvU64 usedFbSize = 0; + NvBool bCanUseGc6 = NV_FALSE; + NV_STATUS fbsrStatus = NV_ERR_GENERIC; + + // + // If the GPU supports GC6, then check if GC6 can be used for + // the current power management request. + // 1. For dynamic PM, GC6 can be used if it is supported by the GPU. + // 2. For system PM with s2idle, GC6 can be used if it is + // supported by the GPU. + // + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_SUPPORTED) && + nvp->gc6_upstream_port_configured) + { + bCanUseGc6 = bIsDynamicPM ? NV_TRUE : nv_s2idle_pm_configured(); + } + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_RG_SUPPORTED)) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_RG_STATE_ENTERING, NV_TRUE); + status = RmPowerManagement(pGpu, NV_PM_ACTION_STANDBY); + pGpu->setProperty(pGpu, PDB_PROP_GPU_RG_STATE_ENTERING, NV_FALSE); + if (status == NV_OK) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_RG_STATE_ENTERED, NV_TRUE); + } + } + // + // If GC6 cannot be used, then no need to compare the used FB size with + // threshold value and select GCOFF irrespective of FB size. + // + else if ((memmgrGetUsedRamSize(pGpu, pMemoryManager, &usedFbSize) == NV_OK) && + (!bCanUseGc6 || RmCheckForGcOffPM(pGpu, usedFbSize, bIsDynamicPM)) && + ((fbsrStatus = fbsrReserveSysMemoryForPowerMgmt(pGpu, pMemoryManager->pFbsr[FBSR_TYPE_DMA], + usedFbSize)) == NV_OK)) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERING, NV_TRUE); + + // + // Set 'bPreserveComptagBackingStoreOnSuspend' so that comptag + // related handling can be done during state unload/load. + // + if (!pMemoryManager->bUseVirtualCopyOnSuspend) + { + pKernelMemorySystem->bPreserveComptagBackingStoreOnSuspend = NV_TRUE; + } + + status = RmPowerManagement(pGpu, NV_PM_ACTION_STANDBY); + pGpu->setProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERING, NV_FALSE); + + if (status == NV_OK) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERED, NV_TRUE); + } + else + { + /* + * Normally the NV_PM_ACTION_RESUME resume should free the + * the reserved memory while doing FB state load. But if the + * failure has happened at very early stage in FB state unload + * while doing NV_PM_ACTION_STANDBY, then reserved system memory + * might not be freed. + */ + fbsrFreeReservedSysMemoryForPowerMgmt(pMemoryManager->pFbsr[FBSR_TYPE_DMA]); + + if (!pMemoryManager->bUseVirtualCopyOnSuspend) + { + pKernelMemorySystem->bPreserveComptagBackingStoreOnSuspend = nv->preserve_vidmem_allocations; + } + } + } + else if (bCanUseGc6) + { + NV2080_CTRL_GC6_ENTRY_PARAMS entryParams; + portMemSet(&entryParams, 0, sizeof(entryParams)); + + entryParams.flavorId = NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID; + entryParams.stepMask = NVBIT(NV2080_CTRL_GC6_STEP_ID_GPU_OFF); + entryParams.params.bIsRTD3Transition = NV_TRUE; + + // + // Currently if the GPU is not in the Lowest P-State, then the + // GC6 entry will fail in its internal sanity check. The system + // suspend can be triggered in any P-State, so sanity check + // for the lowest P-State needs to be skipped. In this case, during + // Perf state unload time, the forceful P-State switch will + // happen which will bring the GPU into lowest P-State. + // + entryParams.params.bSkipPstateSanity = !bIsDynamicPM; + + status = gpuGc6Entry(pGpu, &entryParams); + + // + // The GC6 state requires SW involvement before each transition + // from D0 to D3cold. In case of system suspend with pass-through + // mode, the VM suspend should happen before host suspend. During + // VM suspend, the NVIDIA driver running in the VM side will be + // involved in D3cold transition, but in the host side, it will + // go through D3cold->D0->D3cold transition and will make the + // second D3cold transition without NVIDIA driver. To handle this + // use-case, during VM suspend, use the D0 state and the host linux + // kernel will put the device into D3cold state. + // + if ((status == NV_OK) && ((nv->flags & NV_FLAG_PASSTHRU) != 0)) + { + nv->d0_state_in_suspend = NV_TRUE; + } + } + // + // The else condition below will hit in the following cases: + // Case 1. During system suspend transition: For systems that support s2idle but are configured + // for deep sleep, this "else" condition will be hit when the system memory + // is not sufficient. In this case, we should unset bTryAgain to abort the current suspend entry. + // Case 2. During runtime suspend transition: For systems that do not support GC6 but support + // GCOFF, this "else" condition will be hit when system memory is not sufficent, In this case, we + // should set bTryagain so that the kernel can reschedule the callback later. + // + else + { + if (bIsDynamicPM) + { + if (fbsrStatus == NV_ERR_NO_MEMORY) + { + *bTryAgain = NV_TRUE; + } + status = fbsrStatus; + } + else + { + status = NV_ERR_NOT_SUPPORTED; + NV_PRINTF(LEVEL_ERROR, + "System suspend failed with current system suspend configuration. " + "Please change the system suspend configuration to s2idle in /sys/power/mem_sleep.\n"); + } + } + } + else + { + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERED)) + { + status = RmPowerManagement(pGpu, NV_PM_ACTION_RESUME); + pGpu->setProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERED, NV_FALSE); + if (!pMemoryManager->bUseVirtualCopyOnSuspend) + { + pKernelMemorySystem->bPreserveComptagBackingStoreOnSuspend = nv->preserve_vidmem_allocations; + } + } + else if (pGpu->getProperty(pGpu, PDB_PROP_GPU_RG_STATE_ENTERED)) + { + status = RmPowerManagement(pGpu, NV_PM_ACTION_RESUME); + if (status == NV_OK) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_RG_STATE_ENTERED, NV_FALSE); + } + } + else + { + NV2080_CTRL_GC6_EXIT_PARAMS exitParams; + portMemSet(&exitParams, 0, sizeof(exitParams)); + + exitParams.flavorId = NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID; + exitParams.params.bIsRTD3Transition = NV_TRUE; + + status = gpuGc6Exit(pGpu, &exitParams); + } + } + + return status; +} + +NV_STATUS NV_API_CALL rm_power_management( + nvidia_stack_t *sp, + nv_state_t *pNv, + nv_pm_action_t pmAction +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_OK; + void *fp; + NvBool bTryAgain = NV_FALSE; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_DEVICE_INIT); + + NV_ASSERT_OK(os_flush_work_queue(pNv->queue, pmAction != NV_PM_ACTION_RESUME)); + // + // For GPU driving console, disable console access here, to ensure no console + // writes through BAR1 can interfere with physical RM's setup of BAR1 + // + if (pNv->client_managed_console && !pNv->sysmem_mapped_console) + { + os_disable_console_access(); + } + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER)) == NV_OK) + { + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + + if (pGpu != NULL) + { + if ((rmStatus = os_ref_dynamic_power(pNv, NV_DYNAMIC_PM_FINE)) == NV_OK) + { + // LOCK: acquire GPUs lock + if ((rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER)) == NV_OK) + { + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) + { + rmStatus = RmPowerManagementTegra(pGpu, pmAction); + + // + // RmPowerManagementTegra() is most likely to fail due to + // gpuStateUnload() failures deep in the RM's GPU power + // management paths. However, those paths make no + // attempt to unwind in case of errors. Rather, they + // soldier on and simply report an error at the very end. + // GPU software state meanwhile will indicate the GPU + // has been suspended. + // + // Sadly, in case of an error during suspend/hibernate, + // the only path forward here is to attempt to resume the + // GPU, accepting that the odds of success will vary. + // + if (rmStatus != NV_OK && pmAction != NV_PM_ACTION_RESUME) + { + RmPowerManagementTegra(pGpu, NV_PM_ACTION_RESUME); + } + } + else + { + nv_priv_t *nvp = NV_GET_NV_PRIV(pNv); + + // + // Before going to S3 or S4, remove idle holdoff which was + // applied during gc6 exit. + // + if ((pmAction != NV_PM_ACTION_RESUME) && + (nvp->dynamic_power.b_idle_holdoff == NV_TRUE)) + { + nv_indicate_idle(pNv); + RmCancelCallbackToRemoveIdleHoldoff(pGpu); + nvp->dynamic_power.b_idle_holdoff = NV_FALSE; + } + + // + // Use GCx (GCOFF/GC6) power management if S0ix-based PM is + // enabled and the request is for system suspend/resume. + // Otherwise, use the existing mechanism. + // + if (nvp->s0ix_pm_enabled && + (pmAction == NV_PM_ACTION_STANDBY || + (pmAction == NV_PM_ACTION_RESUME && + !nvp->pm_state.InHibernate))) + { + rmStatus = RmGcxPowerManagement(pGpu, + pmAction == NV_PM_ACTION_STANDBY, + NV_FALSE, &bTryAgain); + + } + else + { + rmStatus = RmPowerManagement(pGpu, pmAction); + } + } + + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + os_unref_dynamic_power(pNv, NV_DYNAMIC_PM_FINE); + } + } + // UNLOCK: release API lock + rmapiLockRelease(); + } + + if (pNv->client_managed_console && !pNv->sysmem_mapped_console) + { + os_enable_console_access(); + } + + NV_ASSERT_OK(os_flush_work_queue(pNv->queue, pmAction != NV_PM_ACTION_RESUME)); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +/*! + * @brief Wrapper around RmGcxPowerManagement() and removes the Idle holdoff + * during exit sequence. + * + * The GPU lock should be held when calling this function. + * + * @param[in] pGpu OBJGPU pointer. + * @param[in] bEnter If true, perform entry sequence; exit sequence + * otherwise. + * + * @return NV_STATUS code indicating if the operation was successful. + */ +static NV_STATUS RmTransitionDynamicPower( + OBJGPU *pGpu, + NvBool bEnter, + NvBool *bTryAgain +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + NV_STATUS status; + + status = RmGcxPowerManagement(pGpu, bEnter, NV_TRUE, bTryAgain); + + if (!bEnter && status == NV_OK) + { + nv_idle_holdoff(nv); + RmScheduleCallbackToRemoveIdleHoldoff(pGpu); + } + + return status; +} + +/*! + * @brief Wrapper around RmTransitionDynamicPower() which sets up the RM + * runtime (thread state and altstack), and takes the GPU lock for the duration + * of the operation. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + * @param[in] bEnter If true, perform entry sequence; exit sequence + * otherwise. + * + * @return NV_STATUS code indicating if the operation was successful. + */ +NV_STATUS NV_API_CALL rm_transition_dynamic_power( + nvidia_stack_t *sp, + nv_state_t *nv, + NvBool bEnter, + NvBool *bTryAgain +) +{ + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + NV_STATUS status = NV_OK; + THREAD_STATE_NODE threadState; + void *fp; + + if (NV_IS_SOC_DISPLAY_DEVICE(nv)) + { + return NV_OK; + } + + NV_ENTER_RM_RUNTIME(sp,fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + if (!bEnter && + !threadState.bValid && + (threadState.threadId == 0) && + pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_RG_SUPPORTED)) + { + /* + * If the thread node is already present in the database, + * reset the thread timeout before the resume operation starts + * for IGPU. + */ + threadStateResetTimeout(pGpu); + } + + if (nv->client_managed_console && !nv->sysmem_mapped_console) + { + os_disable_console_access(); + } + + // LOCK: acquire GPUs lock + status = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER); + if (status == NV_OK) + { + rmapiEnterRtd3PmPath(); + + status = RmTransitionDynamicPower(pGpu, bEnter, bTryAgain); + + rmapiLeaveRtd3PmPath(); + + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + + if (nv->client_managed_console && !nv->sysmem_mapped_console) + { + os_enable_console_access(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp,fp); + + return status; +} + +/*! + * @brief: Notify client about hot-plugged/unplugged displays. + * Called after GPU exits GC6 because of display hot-plug/unplug. + * + * @param[in] nv nv_state_t pointer. + */ +static void RmNotifyClientAboutHotplug( + nv_state_t *nv +) +{ + NV_STATUS status; + GPU_MASK gpuMask; + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + + Nv2080HotplugNotification hotplugNotificationParams; + + portMemSet(&hotplugNotificationParams, 0, sizeof(hotplugNotificationParams)); + + // LOCK: acquire per device lock + status = rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HOTPLUG, + &gpuMask); + if (status == NV_OK) + { + gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_HOTPLUG, + &hotplugNotificationParams, + sizeof(hotplugNotificationParams), 0, 0); + // UNLOCK: release per device lock + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + } +} + +/*! + * @brief If GPU is in GC6, exit GC6 state and + * notify client about display hot-plug/unplug. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + */ +void RmHandleDisplayChange( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + + if (pGpu && + (IS_GPU_GC6_STATE_ENTERED(pGpu) || + pGpu->getProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERED))) + { + if (rm_ref_dynamic_power(sp, nv, NV_DYNAMIC_PM_FINE) == NV_OK) + { + RmNotifyClientAboutHotplug(nv); + rm_unref_dynamic_power(sp, nv, NV_DYNAMIC_PM_FINE); + } + else + NV_PRINTF(LEVEL_ERROR, + "Failed to increment dynamic power refcount\n"); + } +} + +/*! + * @brief RmGetDynamicBoostSupport() gets the notebook DB + * support. DB support is static information for vast majority + * of notebooks and hence we fetch it only once (during the first + * call to this function). This way, the GPU remains in RTD3 state + * when procfs read is done. + * + * @param[in] nv nv_state_t pointer. + */ +static const char* RmGetDynamicBoostSupport( + nv_state_t *pNv +) +{ + nv_priv_t *pNvp = NV_GET_NV_PRIV(pNv); + const char* DbStatus = "?"; + + if (pNvp->db_supported == -1) + { + pNvp->db_supported = os_get_dynamic_boost_support(pNv); + } + + if (pNvp->db_supported == 0) + { + DbStatus = "Not Supported"; + } + else if (pNvp->db_supported == 1) + { + DbStatus = "Supported"; + } + return DbStatus; +} + +/*! + * @brief: Function to query Dynamic Power Management + * + * @param[in] nvp nv_priv_t pointer. + * + * @return String indicating Dynamic Power Management status. + */ +static const char* RmGetDynamicPowerManagementStatus( + nv_priv_t *nvp +) +{ + /* + * If the platform/driver does not support Dynamic Power Management, + * we set mode as NV_DYNAMIC_PM_NEVER. Hence, after RmInit if the + * mode is still NV_DYNAMIC_PM_FINE, we are sure that it is + * supported and enabled. Also see NOTE. + */ + if (nvp->dynamic_power.mode == NV_DYNAMIC_PM_FINE) + { + return "Enabled (fine-grained)"; + } + else if (nvp->dynamic_power.mode == NV_DYNAMIC_PM_COARSE) + { + return "Enabled (coarse-grained)"; + } + else if (nvp->dynamic_power.mode == NV_DYNAMIC_PM_NEVER) + { + + if (nvp->dynamic_power.dynamic_power_regkey == + NV_REG_DYNAMIC_POWER_MANAGEMENT_NEVER) + return "Disabled"; + else if (nvp->dynamic_power.dynamic_power_regkey == + NV_REG_DYNAMIC_POWER_MANAGEMENT_DEFAULT) + return "Disabled by default"; + } + + return "Not supported"; +} + +static void RmHandleIdleSustained( + NvU32 gpuInstance, + void *pArgs +) +{ + OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + nv_revoke_gpu_mappings(NV_GET_NV_STATE(pGpu)); + RmScheduleCallbackToIndicateIdle(pGpu); + nvp->dynamic_power.b_idle_sustained_workitem_queued = NV_FALSE; +} + +/* + * Queue a workitem for revoking GPU mappings, and scheduling a callback to indicate idle. + */ +static void RmQueueIdleSustainedWorkitem( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NV_STATUS status = NV_OK; + + if (!nvp->dynamic_power.b_idle_sustained_workitem_queued) + { + status = osQueueWorkItem(pGpu, + RmHandleIdleSustained, + NULL, + (OsQueueWorkItemFlags){.bLockGpuGroupSubdevice = NV_TRUE}); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_WARNING, + "Failed to queue RmHandleIdleSustained() workitem.\n"); + RmScheduleCallbackForIdlePreConditionsUnderGpuLock(pGpu); + return; + } + nvp->dynamic_power.b_idle_sustained_workitem_queued = NV_TRUE; + } +} + +/* + * Allocate resources needed for S0ix-based system power management. + */ +static void +RmInitS0ixPowerManagement( + nv_state_t *nv, + NvBool bRtd3Support, + NvBool bGC6Support +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvU32 data; + + // S0ix-based S2Idle, on desktops, is not supported yet. Return early for desktop SKUs + if (!nvp->b_mobile_config_enabled) + { + return; + } + + /* + * The GPU S0ix-based system power management will be enabled + * only if all the following necessary requirements are met: + * + * 1. The GPU has RTD3 support. + * 2. The platform has support for s0ix. + * 3. Feature regkey EnableS0ixPowerManagement is enabled. + */ + if (bRtd3Support && bGC6Support && + nv_platform_supports_s0ix() && + (osReadRegistryDword(NULL, NV_REG_ENABLE_S0IX_POWER_MANAGEMENT, + &data) == NV_OK) && (data == 1)) + { + nvp->s0ix_pm_enabled = NV_TRUE; + + /* + * Read the OS registry for Maximum FB size for S0ix-based PM + * which will be expressed in Megabytes (1048576 bytes) and + * convert it into bytes. + */ + if ((osReadRegistryDword(NULL, + NV_REG_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD, + &data) == NV_OK)) + { + nvp->s0ix_gcoff_max_fb_size = (NvU64)data * 1024 * 1024; + } + } +} + +/*! + * @brief: Helper function to abstract the execution and return value verification + * of PEX DSM methods, necessary for GC6 to work in Desktops. + * + * This function is capable to invoke three _DSM methods, as listed below: + * 0x0: _DSM for "Query supported functions" + * (for more details, refer to section 9.1.1 of the ACPI 6.3 Specification). + * 0xA: _DSM for "Requesting D3cold Aux Power Limit" + * (for more details, refer to section 4.6.10 of PCI Firmware Specification v3.3) + * 0xB: _DSM for "Adding PERST# Assertion Delay" + * (for more details, refer to section 4.6.11 of PCI Firmware Specification v3.3) + * + * @param[in] nv nv_state_t pointer. + * @param[in] dsmSubFunc subfunction to invoke. + * @param[in] data input data for dsmSubFunc. + * + * @return TRUE if dsmSubFunc executed successfully and return value is as expected; + * FALSE otherwise. + */ +static NvBool RmAcpiD3ColdDsm +( + nv_state_t *nv, + NvU32 dsmSubFunc, + NvU32 data +) +{ + NvU32 inData = data; + + /* + * Third argument (i.e. acpiDsmRev) is sent as 4 because PEX_FUNC_AUXPOWERLIMIT and + * PEX_FUNC_PEXRST_DELAY sub-functions were introduced in PCI Firmware Specification 3.2 + * and they are supported only for _DSM revision 4 onwards. But, RM still use _DSM + * revision 2 (see drivers/common/inc/pex.h). Hence, the need to hardcode 4 here. + */ + if (nv_acpi_d3cold_dsm_for_upstream_port(nv, (NvU8 *)&PEX_DSM_GUID, 4, dsmSubFunc, &data) != NV_OK) + { + NV_PRINTF(LEVEL_NOTICE, "%s: PEX _DSM subfunction: 0x%X failed.\n", __FUNCTION__, dsmSubFunc); + return NV_FALSE; + } + + switch (dsmSubFunc) + { + case NV_ACPI_ALL_FUNC_SUPPORT: + return ((data & NVBIT(PEX_FUNC_PEXRST_DELAY)) && + (data & NVBIT(PEX_FUNC_AUXPOWERLIMIT))); + + case PEX_FUNC_PEXRST_DELAY: + return (inData == data); + + case PEX_FUNC_AUXPOWERLIMIT: + return ((data == NV_AUX_POWER_REQUEST_STATUS_GRANTED_WITH_12V_POWER) || + (data == NV_AUX_POWER_REQUEST_STATUS_GRANTED_WITHOUT_12V_POWER)); + + default: + return NV_FALSE; + } + + return NV_FALSE; +} + +static NvBool RmConfigureUpstreamPortForRTD3( + nv_state_t *nv, + NvBool bConfigureForGC6 +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + + if (nvp->b_mobile_config_enabled) + return NV_TRUE; + + if (!RmAcpiD3ColdDsm(nv, NV_ACPI_ALL_FUNC_SUPPORT, 0)) + { + return NV_FALSE; + } + + if (!RmAcpiD3ColdDsm(nv, PEX_FUNC_PEXRST_DELAY, + bConfigureForGC6 ? pGpu->gc6State.GC6PerstDelay : DEFAULT_GCOFF_PEXRST_DELAY)) + { + return NV_FALSE; + } + + if (!RmAcpiD3ColdDsm(nv, PEX_FUNC_AUXPOWERLIMIT, + bConfigureForGC6 ? pGpu->gc6State.GC6TotalBoardPower : 0)) + { + if (bConfigureForGC6) + RmAcpiD3ColdDsm(nv, PEX_FUNC_PEXRST_DELAY, DEFAULT_GCOFF_PEXRST_DELAY); + + return NV_FALSE; + } + + NV_PRINTF(LEVEL_NOTICE, + "Aux Power and Pex delay settings %s successfully.\n", + bConfigureForGC6? "applied": "cleared"); + + return NV_TRUE; +} + +void RmInitPowerManagement( + nv_state_t *nv +) +{ + // LOCK: acquire GPUs lock + if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_INIT) == NV_OK) + { + NvBool bGC6Support = NV_FALSE; + NvBool bGCOFFSupport = NV_FALSE; + NvBool bRtd3Support = RmCheckRtd3GcxSupport(nv, &bGC6Support, &bGCOFFSupport); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + + RmInitDeferredDynamicPowerManagement(nv, bRtd3Support); + RmInitS0ixPowerManagement(nv, bRtd3Support, bGC6Support); + + if (bRtd3Support && bGC6Support && + (nvp->s0ix_pm_enabled || (nvp->dynamic_power.mode == NV_DYNAMIC_PM_FINE))) + { + nvp->gc6_upstream_port_configured = RmConfigureUpstreamPortForRTD3(nv, NV_TRUE); + } + + nv->is_pm_unsupported = pGpu->getProperty(pGpu, PDB_PROP_GPU_POWER_MANAGEMENT_UNSUPPORTED); + + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } +} + +void RmDestroyPowerManagement( + nv_state_t *nv +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + if (nvp->gc6_upstream_port_configured) + { + RmConfigureUpstreamPortForRTD3(nv, NV_FALSE); + } + + RmDestroyDeferredDynamicPowerManagement(nv); +} + +void NV_API_CALL rm_get_power_info( + nvidia_stack_t *sp, + nv_state_t *pNv, + nv_power_info_t *powerInfo +) +{ + THREAD_STATE_NODE threadState; + void *fp; + GPU_MASK gpuMask; + const char *pVidmemPowerStatus = "?"; + const char *pGc6Supported = "?"; + const char *pGcoffSupported = "?"; + const char *pDynamicPowerStatus = "?"; + const char *pS0ixStatus = "?"; + const char *pDbStatus = "?"; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER)) == NV_OK) + { + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + + // LOCK: acquire per device lock + if ((pGpu != NULL) && + ((rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER, + &gpuMask)) == NV_OK)) + { + nv_priv_t *pNvp = NV_GET_NV_PRIV(pNv); + + pVidmemPowerStatus = pGpu->getProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERED) ? + "Off" : "Active"; + pDynamicPowerStatus = RmGetDynamicPowerManagementStatus(pNvp); + pGc6Supported = RmGetGpuGcxSupport(pGpu, NV_TRUE); + pGcoffSupported = RmGetGpuGcxSupport(pGpu, NV_FALSE); + pS0ixStatus = pNvp->s0ix_pm_enabled ? "Enabled" : "Disabled"; + pDbStatus = RmGetDynamicBoostSupport(pNv); + // UNLOCK: release per device lock + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + } + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + powerInfo->vidmem_power_status = pVidmemPowerStatus; + powerInfo->dynamic_power_status = pDynamicPowerStatus; + powerInfo->gc6_support = pGc6Supported; + powerInfo->gcoff_support = pGcoffSupported; + powerInfo->s0ix_status = pS0ixStatus; + powerInfo->db_support = pDbStatus; +} + diff --git a/userspace/sdks/nv570/nvalloc/unix/src/escape.c b/userspace/sdks/nv570/nvalloc/unix/src/escape.c new file mode 100644 index 0000000..fae7b8d --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/src/escape.c @@ -0,0 +1,1017 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + + +//***************************** Module Header ********************************** +// +// This code is linked into the resource manager proper. It receives the +// ioctl from the resource manager's customer, unbundles the args and +// calls the correct resman routines. +// +//****************************************************************************** + +#include +#include +#include +#include +#include +#include +#include + +#include +#include // NV01_ROOT +#include // NV01_ROOT_NON_PRIV +#include // NV01_EVENT +#include // NV01_MEMORY_SYSTEM +#include // NV01_MEMORY_SYSTEM_OS_DESCRIPTOR + +#include "rmapi/client_resource.h" +#include "nvlog/nvlog.h" +#include + +#include + +#include + +#define NV_CTL_DEVICE_ONLY(nv) \ +{ \ + if (((nv)->flags & NV_FLAG_CONTROL) == 0) \ + { \ + rmStatus = NV_ERR_INVALID_ARGUMENT; \ + goto done; \ + } \ +} + +#define NV_ACTUAL_DEVICE_ONLY(nv) \ +{ \ + if (((nv)->flags & NV_FLAG_CONTROL) != 0) \ + { \ + rmStatus = NV_ERR_INVALID_ARGUMENT; \ + goto done; \ + } \ +} + +static NV_STATUS RmGetDeviceFd(NVOS54_PARAMETERS *pApi, NvS32 *pFd, + NvBool *pSkipDeviceRef) +{ + RMAPI_PARAM_COPY paramCopy; + void *pKernelParams; + NvU32 paramSize; + NV_STATUS status; + + *pFd = -1; + *pSkipDeviceRef = NV_TRUE; + + switch(pApi->cmd) + { + case NV00FD_CTRL_CMD_ATTACH_GPU: + paramSize = sizeof(NV00FD_CTRL_ATTACH_GPU_PARAMS); + break; + case NV00E0_CTRL_CMD_EXPORT_MEM: + paramSize = sizeof(NV00E0_CTRL_EXPORT_MEM_PARAMS); + break; + default: + return NV_OK; + } + + RMAPI_PARAM_COPY_INIT(paramCopy, pKernelParams, pApi->params, paramSize, 1); + + status = rmapiParamsAcquire(¶mCopy, NV_TRUE); + if (status != NV_OK) + return status; + + switch(pApi->cmd) + { + case NV00FD_CTRL_CMD_ATTACH_GPU: + { + NV00FD_CTRL_ATTACH_GPU_PARAMS *pAttachGpuParams = pKernelParams; + + *pSkipDeviceRef = NV_FALSE; + *pFd = (NvS32)pAttachGpuParams->devDescriptor; + } + break; + case NV00E0_CTRL_CMD_EXPORT_MEM: + { + NV00E0_CTRL_EXPORT_MEM_PARAMS *pExportMemParams = pKernelParams; + + // If hParent is client, no need to reference device. + *pSkipDeviceRef = (pExportMemParams->hParent == pApi->hClient); + *pFd = (NvS32)pExportMemParams->devDescriptor; + } + break; + default: + NV_ASSERT(0); + break; + } + + NV_ASSERT(rmapiParamsRelease(¶mCopy) == NV_OK); + + return status; +} + +// Only return errors through pApi->status +static void RmCreateOsDescriptor(NVOS32_PARAMETERS *pApi, API_SECURITY_INFO secInfo) +{ + NV_STATUS rmStatus; + NvBool writable; + NvU32 flags = 0; + NvU64 allocSize, pageCount, *pPteArray = NULL; + void *pDescriptor, *pPageArray = NULL; + NVOS32_PARAMETERS allocApi = *pApi; + NVOS32_PARAMETERS *pAllocApi = &allocApi; + + pDescriptor = NvP64_VALUE(pApi->data.AllocOsDesc.descriptor); + if (((NvUPtr)pDescriptor & ~os_page_mask) != 0) + { + rmStatus = NV_ERR_NOT_SUPPORTED; + goto done; + } + + // Check to prevent an NvU64 overflow + if ((pApi->data.AllocOsDesc.limit + 1) == 0) + { + rmStatus = NV_ERR_INVALID_LIMIT; + goto done; + } + + allocSize = (pApi->data.AllocOsDesc.limit + 1); + pageCount = (1 + ((allocSize - 1) / os_page_size)); + + writable = FLD_TEST_DRF(OS32, _ATTR2, _PROTECTION_USER, _READ_WRITE, pApi->data.AllocOsDesc.attr2); + + flags = FLD_SET_DRF_NUM(_LOCK_USER_PAGES, _FLAGS, _WRITE, writable, flags); + rmStatus = os_lock_user_pages(pDescriptor, pageCount, &pPageArray, flags); + if (rmStatus == NV_OK) + { + pAllocApi->data.AllocOsDesc.descriptor = (NvP64)(NvUPtr)pPageArray; + pAllocApi->data.AllocOsDesc.descriptorType = NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY; + } + else if (rmStatus == NV_ERR_INVALID_ADDRESS) + { + rmStatus = os_lookup_user_io_memory(pDescriptor, pageCount, &pPteArray); + if (rmStatus == NV_OK) + { + pAllocApi->data.AllocOsDesc.descriptor = (NvP64)(NvUPtr)pPteArray; + pAllocApi->data.AllocOsDesc.descriptorType = NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY; + } + } + if (rmStatus != NV_OK) + goto done; + + Nv04VidHeapControlWithSecInfo(pAllocApi, secInfo); + + pApi->status = pAllocApi->status; + pApi->data.AllocOsDesc.hMemory = pAllocApi->data.AllocOsDesc.hMemory; + + if ((pAllocApi->status != NV_OK) && + (pAllocApi->data.AllocOsDesc.descriptor != NvP64_NULL)) + { + switch (pAllocApi->data.AllocOsDesc.descriptorType) + { + default: + break; + case NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY: + os_unlock_user_pages(pageCount, pPageArray, flags); + break; + } + } + +done: + if (rmStatus != NV_OK) + pApi->status = rmStatus; +} + +// Only return errors through pApi->status +static void RmAllocOsDescriptor(NVOS02_PARAMETERS *pApi, API_SECURITY_INFO secInfo) +{ + NV_STATUS rmStatus = NV_OK; + NvU32 flags, attr, attr2; + NVOS32_PARAMETERS *pVidHeapParams; + + if (!FLD_TEST_DRF(OS02, _FLAGS, _LOCATION, _PCI, pApi->flags) || + !FLD_TEST_DRF(OS02, _FLAGS, _MAPPING, _NO_MAP, pApi->flags)) + { + rmStatus = NV_ERR_INVALID_FLAGS; + goto done; + } + + attr = DRF_DEF(OS32, _ATTR, _LOCATION, _PCI); + + if (FLD_TEST_DRF(OS02, _FLAGS, _COHERENCY, _CACHED, pApi->flags) || + FLD_TEST_DRF(OS02, _FLAGS, _COHERENCY, _WRITE_BACK, pApi->flags)) + { + attr = FLD_SET_DRF(OS32, _ATTR, _COHERENCY, _WRITE_BACK, attr); + } + else if (FLD_TEST_DRF(OS02, _FLAGS, _COHERENCY, _UNCACHED, pApi->flags)) + attr = FLD_SET_DRF(OS32, _ATTR, _COHERENCY, _UNCACHED, attr); + else { + rmStatus = NV_ERR_INVALID_FLAGS; + goto done; + } + + if (FLD_TEST_DRF(OS02, _FLAGS, _PHYSICALITY, _CONTIGUOUS, pApi->flags)) + attr = FLD_SET_DRF(OS32, _ATTR, _PHYSICALITY, _CONTIGUOUS, attr); + else + attr = FLD_SET_DRF(OS32, _ATTR, _PHYSICALITY, _NONCONTIGUOUS, attr); + + if (FLD_TEST_DRF(OS02, _FLAGS, _GPU_CACHEABLE, _YES, pApi->flags)) + attr2 = DRF_DEF(OS32, _ATTR2, _GPU_CACHEABLE, _YES); + else + attr2 = DRF_DEF(OS32, _ATTR2, _GPU_CACHEABLE, _NO); + + if (FLD_TEST_DRF(OS02, _FLAGS, _MEMORY_PROTECTION, _UNPROTECTED, pApi->flags)) + attr2 = FLD_SET_DRF(OS32, _ATTR2, _MEMORY_PROTECTION, _UNPROTECTED, attr2); + + pVidHeapParams = portMemAllocNonPaged(sizeof(NVOS32_PARAMETERS)); + if (pVidHeapParams == NULL) + { + rmStatus = NV_ERR_NO_MEMORY; + goto done; + } + portMemSet(pVidHeapParams, 0, sizeof(NVOS32_PARAMETERS)); + + pVidHeapParams->hRoot = pApi->hRoot; + pVidHeapParams->hObjectParent = pApi->hObjectParent; + pVidHeapParams->function = NVOS32_FUNCTION_ALLOC_OS_DESCRIPTOR; + + flags = (NVOS32_ALLOC_FLAGS_MEMORY_HANDLE_PROVIDED | + NVOS32_ALLOC_FLAGS_MAP_NOT_REQUIRED); + + if (DRF_VAL(OS02, _FLAGS, _ALLOC_USER_READ_ONLY, pApi->flags)) + attr2 = FLD_SET_DRF(OS32, _ATTR2, _PROTECTION_USER, _READ_ONLY, attr2); + + // Currently CPU-RO memory implies GPU-RO as well + if (DRF_VAL(OS02, _FLAGS, _ALLOC_DEVICE_READ_ONLY, pApi->flags) || + DRF_VAL(OS02, _FLAGS, _ALLOC_USER_READ_ONLY, pApi->flags)) + attr2 = FLD_SET_DRF(OS32, _ATTR2, _PROTECTION_DEVICE, _READ_ONLY, attr2); + + pVidHeapParams->data.AllocOsDesc.hMemory = pApi->hObjectNew; + pVidHeapParams->data.AllocOsDesc.flags = flags; + pVidHeapParams->data.AllocOsDesc.attr = attr; + pVidHeapParams->data.AllocOsDesc.attr2 = attr2; + pVidHeapParams->data.AllocOsDesc.descriptor = pApi->pMemory; + pVidHeapParams->data.AllocOsDesc.limit = pApi->limit; + pVidHeapParams->data.AllocOsDesc.descriptorType = NVOS32_DESCRIPTOR_TYPE_VIRTUAL_ADDRESS; + + RmCreateOsDescriptor(pVidHeapParams, secInfo); + + pApi->status = pVidHeapParams->status; + + portMemFree(pVidHeapParams); + +done: + if (rmStatus != NV_OK) + pApi->status = rmStatus; +} + +ct_assert(NV_OFFSETOF(NVOS21_PARAMETERS, hRoot) == NV_OFFSETOF(NVOS64_PARAMETERS, hRoot)); +ct_assert(NV_OFFSETOF(NVOS21_PARAMETERS, hObjectParent) == NV_OFFSETOF(NVOS64_PARAMETERS, hObjectParent)); +ct_assert(NV_OFFSETOF(NVOS21_PARAMETERS, hObjectNew) == NV_OFFSETOF(NVOS64_PARAMETERS, hObjectNew)); +ct_assert(NV_OFFSETOF(NVOS21_PARAMETERS, hClass) == NV_OFFSETOF(NVOS64_PARAMETERS, hClass)); +ct_assert(NV_OFFSETOF(NVOS21_PARAMETERS, pAllocParms) == NV_OFFSETOF(NVOS64_PARAMETERS, pAllocParms)); + + +NV_STATUS RmValidateIoctl(NvU32 cmd, NvU32 size) +{ + int i = 0; + const unsigned int arg_cmd = (cmd & 0xFF); + static const struct { + unsigned int cmdKey; + unsigned int paramSize; + } RmIoctlsTable[] = { + + #define _RM_ESC_IOCTL_ENTRY(_cmd, _type) \ + { .cmdKey = ((_cmd) & 0xFF), .paramSize = sizeof(_type) } + + _RM_ESC_IOCTL_ENTRY(NV_ESC_STATUS_CODE, nv_ioctl_status_code_t), + _RM_ESC_IOCTL_ENTRY(NV_ESC_RM_ALLOC_MEMORY, nv_ioctl_nvos02_parameters_with_fd), + _RM_ESC_IOCTL_ENTRY(NV_ESC_RM_ALLOC_OBJECT, NVOS05_PARAMETERS), + _RM_ESC_IOCTL_ENTRY(NV_ESC_RM_FREE, NVOS00_PARAMETERS), + _RM_ESC_IOCTL_ENTRY(NV_ESC_RM_CONTROL, NVOS54_PARAMETERS), + _RM_ESC_IOCTL_ENTRY(NV_ESC_RM_DUP_OBJECT, NVOS55_PARAMETERS), + _RM_ESC_IOCTL_ENTRY(NV_ESC_RM_SHARE, NVOS57_PARAMETERS), + _RM_ESC_IOCTL_ENTRY(NV_ESC_RM_I2C_ACCESS, NVOS_I2C_ACCESS_PARAMS), + _RM_ESC_IOCTL_ENTRY(NV_ESC_RM_IDLE_CHANNELS, NVOS30_PARAMETERS), + _RM_ESC_IOCTL_ENTRY(NV_ESC_RM_VID_HEAP_CONTROL, NVOS32_PARAMETERS), + _RM_ESC_IOCTL_ENTRY(NV_ESC_RM_ACCESS_REGISTRY, NVOS38_PARAMETERS), + _RM_ESC_IOCTL_ENTRY(NV_ESC_RM_MAP_MEMORY, nv_ioctl_nvos33_parameters_with_fd), + _RM_ESC_IOCTL_ENTRY(NV_ESC_RM_UNMAP_MEMORY, NVOS34_PARAMETERS), + _RM_ESC_IOCTL_ENTRY(NV_ESC_RM_ALLOC_CONTEXT_DMA2, NVOS39_PARAMETERS), + _RM_ESC_IOCTL_ENTRY(NV_ESC_RM_MAP_MEMORY_DMA, NVOS46_PARAMETERS), + _RM_ESC_IOCTL_ENTRY(NV_ESC_RM_UNMAP_MEMORY_DMA, NVOS47_PARAMETERS), + _RM_ESC_IOCTL_ENTRY(NV_ESC_RM_BIND_CONTEXT_DMA, NVOS49_PARAMETERS), + _RM_ESC_IOCTL_ENTRY(NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO, NVOS56_PARAMETERS), + _RM_ESC_IOCTL_ENTRY(NV_ESC_RM_LOCKLESS_DIAGNOSTIC, NV_LOCKLESS_DIAGNOSTIC_PARAMS), + _RM_ESC_IOCTL_ENTRY(NV_ESC_REGISTER_FD, nv_ioctl_register_fd_t), + }; + + if (arg_cmd == NV_ESC_RM_ALLOC) + { + if (size == sizeof(NVOS64_PARAMETERS) || size == sizeof(NVOS21_PARAMETERS)) + { + return NV_OK; + } + else + { + nv_printf(NV_DBG_ERRORS, "NVRM: invalid %d structure size!\n", arg_cmd); + + return NV_ERR_INVALID_ARGUMENT; + } + } + + for (i = 0; i < NV_ARRAY_ELEMENTS(RmIoctlsTable); ++i) + { + if (arg_cmd == RmIoctlsTable[i].cmdKey) + { + if (size != RmIoctlsTable[i].paramSize) + { + nv_printf(NV_DBG_ERRORS, "NVRM: invalid %d structure size, expected %d, got %d!\n", + RmIoctlsTable[i].cmdKey, RmIoctlsTable[i].paramSize, size); + // If IOCTL is found and size is mismatched, return NV_ERR_INVALID_ARGUMENT + return NV_ERR_INVALID_ARGUMENT; + } + // If IOCTL is found and size is valid, return NV_OK + return NV_OK; + } + } + // If IOCTL is not found, return NV_ERR_INVALID_COMMAND + return NV_ERR_INVALID_COMMAND; +} + +NV_STATUS RmIoctl( + nv_state_t *nv, + nv_file_private_t *nvfp, + NvU32 cmd, + void *data, + NvU32 dataSize +) +{ + // nvfp->ctl_nvfp + ct_assert(sizeof(PORT_ATOMIC nv_file_private_t *) == sizeof(nv_file_private_t *)); + ct_assert(_Alignof(PORT_ATOMIC nv_file_private_t *) == _Alignof(nv_file_private_t *)); + + // nvfp->register_or_refcount + ct_assert(sizeof(PORT_ATOMIC NvU32) == sizeof(NvU32)); + ct_assert(_Alignof(PORT_ATOMIC NvU32) == _Alignof(NvU32)); + + NV_STATUS rmStatus = NV_ERR_GENERIC; + API_SECURITY_INFO secInfo = { }; + + secInfo.privLevel = osIsAdministrator() ? RS_PRIV_LEVEL_USER_ROOT : RS_PRIV_LEVEL_USER; + secInfo.paramLocation = PARAM_LOCATION_USER; + secInfo.pProcessToken = NULL; + secInfo.gpuOsInfo = NULL; + secInfo.clientOSInfo = nvfp->ctl_nvfp; + if (secInfo.clientOSInfo == NULL) + secInfo.clientOSInfo = nvfp; + + switch (cmd) + { + case NV_ESC_RM_ALLOC_MEMORY: + { + nv_ioctl_nvos02_parameters_with_fd *pApi; + NVOS02_PARAMETERS *pParms; + + if (dataSize != sizeof(*pApi)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + pApi = data; + pParms = &pApi->params; + + NV_ACTUAL_DEVICE_ONLY(nv); + + if (pParms->hClass == NV01_MEMORY_SYSTEM_OS_DESCRIPTOR) + RmAllocOsDescriptor(pParms, secInfo); + else + { + NvU32 flags = pParms->flags; + + Nv01AllocMemoryWithSecInfo(pParms, secInfo); + + // + // If the system memory is going to be mapped immediately, + // create the mmap context for it now. + // + if ((pParms->hClass == NV01_MEMORY_SYSTEM) && + (!FLD_TEST_DRF(OS02, _FLAGS, _ALLOC, _NONE, flags)) && + (!FLD_TEST_DRF(OS02, _FLAGS, _MAPPING, _NO_MAP, flags)) && + (pParms->status == NV_OK)) + { + if (rm_create_mmap_context(pParms->hRoot, + pParms->hObjectParent, pParms->hObjectNew, + pParms->pMemory, pParms->limit + 1, 0, + NV_MEMORY_DEFAULT, + pApi->fd) != NV_OK) + { + NV_PRINTF(LEVEL_WARNING, + "could not create mmap context for %p\n", + NvP64_VALUE(pParms->pMemory)); + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + } + } + + break; + } + + case NV_ESC_RM_ALLOC_OBJECT: + { + NVOS05_PARAMETERS *pApi = data; + + if (dataSize != sizeof(*pApi)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + NV_CTL_DEVICE_ONLY(nv); + + Nv01AllocObjectWithSecInfo(pApi, secInfo); + break; + } + + case NV_ESC_RM_ALLOC: + { + NVOS21_PARAMETERS *pApi = data; + NVOS64_PARAMETERS *pApiAccess = data; + NvBool bAccessApi = (dataSize == sizeof(NVOS64_PARAMETERS)); + + if ((dataSize != sizeof(*pApi)) && + (dataSize != sizeof(*pApiAccess))) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + switch (pApi->hClass) + { + case NV01_ROOT: + case NV01_ROOT_CLIENT: + case NV01_ROOT_NON_PRIV: + { + NV_CTL_DEVICE_ONLY(nv); + + // Force userspace client allocations to be the _CLIENT class. + pApi->hClass = NV01_ROOT_CLIENT; + break; + } + case NV01_EVENT: + case NV01_EVENT_OS_EVENT: + case NV01_EVENT_KERNEL_CALLBACK: + case NV01_EVENT_KERNEL_CALLBACK_EX: + { + break; + } + default: + { + NV_CTL_DEVICE_ONLY(nv); + break; + } + } + + if (!bAccessApi) + { + Nv04AllocWithSecInfo(pApi, secInfo); + } + else + { + Nv04AllocWithAccessSecInfo(pApiAccess, secInfo); + } + + break; + } + + case NV_ESC_RM_FREE: + { + NVOS00_PARAMETERS *pApi = data; + + if (dataSize != sizeof(*pApi)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + NV_CTL_DEVICE_ONLY(nv); + + Nv01FreeWithSecInfo(pApi, secInfo); + + if (pApi->status == NV_OK && + pApi->hObjectOld == pApi->hRoot) + { + rm_client_free_os_events(pApi->hRoot); + } + + break; + } + + case NV_ESC_RM_VID_HEAP_CONTROL: + { + NVOS32_PARAMETERS *pApi = data; + + if (dataSize != sizeof(*pApi)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + NV_CTL_DEVICE_ONLY(nv); + + if (pApi->function == NVOS32_FUNCTION_ALLOC_OS_DESCRIPTOR) + RmCreateOsDescriptor(pApi, secInfo); + else + Nv04VidHeapControlWithSecInfo(pApi, secInfo); + + break; + } + + case NV_ESC_RM_I2C_ACCESS: + { + NVOS_I2C_ACCESS_PARAMS *pApi = data; + + if (dataSize != sizeof(*pApi)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + NV_ACTUAL_DEVICE_ONLY(nv); + + Nv04I2CAccessWithSecInfo(pApi, secInfo); + break; + } + + case NV_ESC_RM_IDLE_CHANNELS: + { + NVOS30_PARAMETERS *pApi = data; + + if (dataSize != sizeof(*pApi)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + NV_CTL_DEVICE_ONLY(nv); + + Nv04IdleChannelsWithSecInfo(pApi, secInfo); + break; + } + + case NV_ESC_RM_MAP_MEMORY: + { + nv_ioctl_nvos33_parameters_with_fd *pApi; + NVOS33_PARAMETERS *pParms; + + if (dataSize != sizeof(*pApi)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + pApi = data; + pParms = &pApi->params; + + NV_CTL_DEVICE_ONLY(nv); + + // Don't allow userspace to override the caching type + pParms->flags = FLD_SET_DRF(OS33, _FLAGS, _CACHING_TYPE, _DEFAULT, pParms->flags); + Nv04MapMemoryWithSecInfo(pParms, secInfo); + + if (pParms->status == NV_OK) + { + pParms->status = rm_create_mmap_context(pParms->hClient, + pParms->hDevice, pParms->hMemory, + pParms->pLinearAddress, pParms->length, + pParms->offset, + DRF_VAL(OS33, _FLAGS, _CACHING_TYPE, pParms->flags), + pApi->fd); + if (pParms->status != NV_OK) + { + NVOS34_PARAMETERS params; + portMemSet(¶ms, 0, sizeof(params)); + params.hClient = pParms->hClient; + params.hDevice = pParms->hDevice; + params.hMemory = pParms->hMemory; + params.pLinearAddress = pParms->pLinearAddress; + params.flags = pParms->flags; + Nv04UnmapMemoryWithSecInfo(¶ms, secInfo); + } + } + break; + } + + case NV_ESC_RM_UNMAP_MEMORY: + { + NVOS34_PARAMETERS *pApi = data; + + if (dataSize != sizeof(*pApi)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + NV_CTL_DEVICE_ONLY(nv); + + Nv04UnmapMemoryWithSecInfo(pApi, secInfo); + break; + } + + case NV_ESC_RM_ACCESS_REGISTRY: + { + NVOS38_PARAMETERS *pApi = data; + + if (dataSize != sizeof(*pApi)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + NV_CTL_DEVICE_ONLY(nv); + + pApi->status = rm_access_registry(pApi->hClient, + pApi->hObject, + pApi->AccessType, + pApi->pDevNode, + pApi->DevNodeLength, + pApi->pParmStr, + pApi->ParmStrLength, + pApi->pBinaryData, + &pApi->BinaryDataLength, + &pApi->Data, + &pApi->Entry); + break; + } + + case NV_ESC_RM_ALLOC_CONTEXT_DMA2: + { + NVOS39_PARAMETERS *pApi = data; + + if (dataSize != sizeof(*pApi)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + NV_CTL_DEVICE_ONLY(nv); + + Nv04AllocContextDmaWithSecInfo(pApi, secInfo); + break; + } + + case NV_ESC_RM_BIND_CONTEXT_DMA: + { + NVOS49_PARAMETERS *pApi = data; + + if (dataSize != sizeof(*pApi)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + NV_CTL_DEVICE_ONLY(nv); + + Nv04BindContextDmaWithSecInfo(pApi, secInfo); + break; + } + + case NV_ESC_RM_MAP_MEMORY_DMA: + { + NVOS46_PARAMETERS *pApi = data; + + if (dataSize != sizeof(*pApi)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + NV_CTL_DEVICE_ONLY(nv); + + Nv04MapMemoryDmaWithSecInfo(pApi, secInfo); + break; + } + + case NV_ESC_RM_UNMAP_MEMORY_DMA: + { + NVOS47_PARAMETERS *pApi = data; + + if (dataSize != sizeof(*pApi)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + NV_CTL_DEVICE_ONLY(nv); + + Nv04UnmapMemoryDmaWithSecInfo(pApi, secInfo); + break; + } + + case NV_ESC_RM_DUP_OBJECT: + { + NVOS55_PARAMETERS *pApi = data; + + if (dataSize != sizeof(*pApi)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + NV_CTL_DEVICE_ONLY(nv); + + Nv04DupObjectWithSecInfo(pApi, secInfo); + break; + } + + case NV_ESC_RM_SHARE: + { + NVOS57_PARAMETERS *pApi = data; + + if (dataSize != sizeof(*pApi)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + NV_CTL_DEVICE_ONLY(nv); + + Nv04ShareWithSecInfo(pApi, secInfo); + break; + } + + case NV_ESC_STATUS_CODE: + { + nv_state_t *pNv; + nv_ioctl_status_code_t *pApi = data; + + if (dataSize != sizeof(*pApi)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + NV_CTL_DEVICE_ONLY(nv); + + pNv = nv_get_adapter_state(pApi->domain, pApi->bus, pApi->slot); + if (pNv == NULL) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + rmStatus = rm_get_adapter_status(pNv, &pApi->status); + + if (rmStatus != NV_OK) + goto done; + + break; + } + + case NV_ESC_RM_CONTROL: + { + NVOS54_PARAMETERS *pApi = data; + void *priv = NULL; + nv_file_private_t *dev_nvfp = NULL; + NvS32 fd; + NvBool bSkipDeviceRef; + + if (dataSize != sizeof(*pApi)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + NV_CTL_DEVICE_ONLY(nv); + + rmStatus = RmGetDeviceFd(pApi, &fd, &bSkipDeviceRef); + if (rmStatus != NV_OK) + { + goto done; + } + + if (!bSkipDeviceRef) + { + dev_nvfp = nv_get_file_private(fd, NV_FALSE, &priv); + if (dev_nvfp == NULL) + { + rmStatus = NV_ERR_INVALID_DEVICE; + goto done; + } + + // Check to avoid cyclic dependency with NV_ESC_REGISTER_FD + if (!portAtomicCompareAndSwapU32(&dev_nvfp->register_or_refcount, + NVFP_TYPE_REFCOUNTED, + NVFP_TYPE_NONE)) + { + // Is this already refcounted... + if (dev_nvfp->register_or_refcount != NVFP_TYPE_REFCOUNTED) + { + nv_put_file_private(priv); + rmStatus = NV_ERR_IN_USE; + goto done; + } + } + + secInfo.gpuOsInfo = priv; + } + + Nv04ControlWithSecInfo(pApi, secInfo); + + if ((pApi->status != NV_OK) && (priv != NULL)) + { + // + // No need to reset `register_or_refcount` as it might be set + // for previous successful calls. We let it clear with FD close. + // + nv_put_file_private(priv); + + secInfo.gpuOsInfo = NULL; + } + + break; + } + + case NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO: + { + NVOS56_PARAMETERS *pApi = data; + void *pOldCpuAddress; + void *pNewCpuAddress; + + if (dataSize != sizeof(*pApi)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + NV_CTL_DEVICE_ONLY(nv); + + pOldCpuAddress = NvP64_VALUE(pApi->pOldCpuAddress); + pNewCpuAddress = NvP64_VALUE(pApi->pNewCpuAddress); + + pApi->status = rm_update_device_mapping_info(pApi->hClient, + pApi->hDevice, + pApi->hMemory, + pOldCpuAddress, + pNewCpuAddress); + break; + } + + case NV_ESC_RM_LOCKLESS_DIAGNOSTIC: + { + NV_LOCKLESS_DIAGNOSTIC_PARAMS *pParams = data; + + if (dataSize != sizeof(*pParams)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + NV_CTL_DEVICE_ONLY(nv); + + if (!osIsAdministrator()) + { + rmStatus = NV_ERR_INSUFFICIENT_PERMISSIONS; + goto done; + } + + switch (pParams->cmd) + { + // Do not use NVOC _DISPATCH here as it dereferences NULL RmClientResource* + case NV0000_CTRL_CMD_NVD_GET_NVLOG_INFO: + rmStatus = cliresCtrlCmdNvdGetNvlogInfo_IMPL(NULL, &pParams->params.getNvlogInfo); + break; + case NV0000_CTRL_CMD_NVD_GET_NVLOG_BUFFER_INFO: + rmStatus = cliresCtrlCmdNvdGetNvlogBufferInfo_IMPL(NULL, &pParams->params.getNvlogBufferInfo); + break; + case NV0000_CTRL_CMD_NVD_GET_NVLOG: + rmStatus = cliresCtrlCmdNvdGetNvlog_IMPL(NULL, &pParams->params.getNvlog); + break; + default: + rmStatus = NV_ERR_NOT_SUPPORTED; + break; + } + + pParams->status = rmStatus; + goto done; + } + + case NV_ESC_REGISTER_FD: + { + nv_ioctl_register_fd_t *params = data; + void *priv = NULL; + nv_file_private_t *ctl_nvfp; + + if (dataSize != sizeof(*params)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + // LOCK: acquire API lock + rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI); + if (rmStatus != NV_OK) + goto done; + + // If there is already a ctl fd registered on this nvfp, fail. + if (nvfp->ctl_nvfp != NULL) + { + // UNLOCK: release API lock + rmapiLockRelease(); + rmStatus = NV_ERR_INVALID_STATE; + goto done; + } + + // + // Note that this call is valid for both "actual" devices and ctrl + // devices. In particular, NV_ESC_ALLOC_OS_EVENT can be used with + // both types of devices. + // But, the ctl_fd passed in should always correspond to a control FD. + // + ctl_nvfp = nv_get_file_private(params->ctl_fd, + NV_TRUE, /* require ctl fd */ + &priv); + if (ctl_nvfp == NULL) + { + // UNLOCK: release API lock + rmapiLockRelease(); + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + // Disallow self-referential links, and disallow links to FDs that + // themselves have a link. + if ((ctl_nvfp == nvfp) || (ctl_nvfp->ctl_nvfp != NULL)) + { + nv_put_file_private(priv); + // UNLOCK: release API lock + rmapiLockRelease(); + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + // Check to avoid cyclic dependency with device refcounting + if (!portAtomicCompareAndSwapU32(&nvfp->register_or_refcount, + NVFP_TYPE_REGISTERED, + NVFP_TYPE_NONE)) + { + nv_put_file_private(priv); + // UNLOCK: release API lock + rmapiLockRelease(); + rmStatus = NV_ERR_IN_USE; + goto done; + } + + // + // nvfp->ctl_nvfp is read outside the lock, so set it atomically. + // Note that once set, this can never be removed until the fd + // associated with nvfp is closed. We hold on to 'priv' until the + // fd is closed, too, to ensure that the fd associated with + // ctl_nvfp remains valid. + // + portAtomicSetSize(&nvfp->ctl_nvfp, ctl_nvfp); + nvfp->ctl_nvfp_priv = priv; + + // UNLOCK: release API lock + rmapiLockRelease(); + + // NOTE: nv_put_file_private(priv) is not called here. It MUST be + // called during cleanup of this nvfp. + rmStatus = NV_OK; + break; + } + + default: + { + NV_PRINTF(LEVEL_ERROR, "unknown NVRM ioctl command: 0x%x\n", cmd); + goto done; + } + } + + rmStatus = NV_OK; +done: + + return rmStatus; +} diff --git a/userspace/sdks/nv570/nvalloc/unix/src/exports-stubs.c b/userspace/sdks/nv570/nvalloc/unix/src/exports-stubs.c new file mode 100644 index 0000000..ff40300 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/src/exports-stubs.c @@ -0,0 +1,30 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include "os/os.h" +#include +#include +#include +#include + diff --git a/userspace/sdks/nv570/nvalloc/unix/src/gcc_helper.c b/userspace/sdks/nv570/nvalloc/unix/src/gcc_helper.c new file mode 100644 index 0000000..3c1037c --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/src/gcc_helper.c @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +void* memset(void* s, int c, NvUPtr n) +{ + return os_mem_set(s, (NvU8)c, (NvU32)n); +} + +void* memcpy(void* dest, const void* src, NvUPtr n) +{ + return os_mem_copy(dest, src, (NvU32)n); +} diff --git a/userspace/sdks/nv570/nvalloc/unix/src/os-hypervisor.c b/userspace/sdks/nv570/nvalloc/unix/src/os-hypervisor.c new file mode 100644 index 0000000..26c468f --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/src/os-hypervisor.c @@ -0,0 +1,994 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * + * @file os-hypervisor.c + * @brief OS specific Hypervisor interfaces for RM + * + */ + +#include "os/os.h" +#include "nv.h" +#include "nv-priv.h" +#include +#include +#include "core/thread_state.h" +#include "core/locks.h" +#include "virtualization/kernel_vgpu_mgr.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "kernel/gpu/fifo/kernel_fifo.h" +#include "osapi.h" +#include "virtualization/kernel_hostvgpudeviceapi.h" +#include "gpu/timer/objtmr.h" +#include "gpu/bif/kernel_bif.h" +#include "gpu/bus/kern_bus.h" +#include // NV_PMC_BOOT_1_VGPU +#include "nvdevid.h" +#include "ctrl/ctrl0000/ctrl0000vgpu.h" + +#include "g_vgpu_chip_flags.h" // vGPU device names + +#define NV_VFIO_PCI_BAR0_REGION_INDEX 0 +#define NV_VFIO_PCI_BAR1_REGION_INDEX 1 +#define NV_VFIO_PCI_BAR2_REGION_INDEX 2 +#define NV_VFIO_PCI_BAR3_REGION_INDEX 3 + +static NV_STATUS nv_parse_config_params(const char *, const char *, const char, NvU32 *); + + +void hypervisorSetHypervVgpuSupported_IMPL(OBJHYPERVISOR *pHypervisor) +{ + pHypervisor->bIsHypervVgpuSupported = NV_TRUE; +} + +NvBool hypervisorIsVgxHyper_IMPL(void) +{ + return os_is_vgx_hyper(); +} + +NV_STATUS hypervisorInjectInterrupt_IMPL +( + OBJHYPERVISOR *pHypervisor, + VGPU_NS_INTR *pVgpuNsIntr +) +{ + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + + if (osIsVgpuVfioPresent() == NV_OK) + return NV_ERR_NOT_SUPPORTED; + else + { + if (pVgpuNsIntr->guestMSIAddr && pVgpuNsIntr->guestMSIData) + { + status = os_inject_vgx_msi((NvU16)pVgpuNsIntr->guestDomainId, + pVgpuNsIntr->guestMSIAddr, + pVgpuNsIntr->guestMSIData); + } + } + + return status; +} + +HYPERVISOR_TYPE NV_API_CALL nv_get_hypervisor_type(void) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); + return hypervisorGetHypervisorType(pHypervisor); +} + +#define MAX_STR_LEN 256 +NV_STATUS NV_API_CALL nv_vgpu_get_type_info( + nvidia_stack_t *sp, + nv_state_t *pNv, + NvU32 vgpuTypeId, + char *buffer, + int type_info, + NvU8 devfn +) +{ + THREAD_STATE_NODE threadState; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + NV_STATUS rmStatus = NV_OK; + VGPU_TYPE *vgpuTypeInfo; + NvU32 pgpuIndex, i, avail_instances = 0; + OBJGPU *pGpu = NULL; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + if ((rmStatus = kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pNv->gpu_id, &pgpuIndex)) == + NV_OK) + { + for (i = 0; i < MAX_VGPU_TYPES_PER_PGPU; i++) + { + vgpuTypeInfo = pKernelVgpuMgr->pgpuInfo[pgpuIndex].vgpuTypes[i]; + if (vgpuTypeInfo == NULL) + break; + + if (vgpuTypeInfo->vgpuTypeId != vgpuTypeId) + continue; + + switch (type_info) + { + case VGPU_TYPE_INSTANCES: + pGpu = NV_GET_NV_PRIV_PGPU(pNv); + if (pGpu == NULL) + { + NV_PRINTF(LEVEL_ERROR, "%s GPU handle is not valid \n", + __FUNCTION__); + rmStatus = NV_ERR_INVALID_STATE; + goto exit; + } + + rmStatus = kvgpumgrGetAvailableInstances(&avail_instances, pGpu, + vgpuTypeInfo, + pgpuIndex, devfn); + if (rmStatus != NV_OK) + goto exit; + + os_snprintf(buffer, MAX_STR_LEN, "%d\n", avail_instances); + break; + default: + rmStatus = NV_ERR_INVALID_ARGUMENT; + } + break; + } + } + +exit: + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL nv_vgpu_get_type_ids( + nvidia_stack_t *sp, + nv_state_t *pNv, + NvU32 *numVgpuTypes, + NvU32 *vgpuTypeIds, + NvBool isVirtfn, + NvU8 devfn, + NvBool getCreatableTypes +) +{ + THREAD_STATE_NODE threadState; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPU *pGpu = NULL; + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + NV_STATUS rmStatus = NV_OK; + NvU32 pgpuIndex, i, avail_instances = 0; + NvU32 numSupportedVgpuTypes = 0; + VGPU_TYPE *vgpuTypeInfo; + void *fp; + + if (!vgpuTypeIds || !numVgpuTypes) + return NV_ERR_INVALID_ARGUMENT; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + if ((rmStatus = kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pNv->gpu_id, &pgpuIndex)) == + NV_OK) + { + if (pKernelVgpuMgr->pgpuInfo[pgpuIndex].sriovEnabled && !isVirtfn) + { + *numVgpuTypes = 0; + } + else + { + numSupportedVgpuTypes = pKernelVgpuMgr->pgpuInfo[pgpuIndex].numVgpuTypes; + *numVgpuTypes = 0; + + for (i = 0; i < numSupportedVgpuTypes; i++) + { + vgpuTypeInfo = pKernelVgpuMgr->pgpuInfo[pgpuIndex].vgpuTypes[i]; + + if (!getCreatableTypes) + { + // Return all available types + vgpuTypeIds[*numVgpuTypes] = vgpuTypeInfo->vgpuTypeId; + (*numVgpuTypes)++; + continue; + } + + pGpu = NV_GET_NV_PRIV_PGPU(pNv); + if (pGpu == NULL) + { + NV_PRINTF(LEVEL_ERROR, "%s GPU handle is not valid \n", + __FUNCTION__); + goto exit; + } + + rmStatus = kvgpumgrGetAvailableInstances(&avail_instances, pGpu, + vgpuTypeInfo, pgpuIndex, + devfn); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to get available instances for vGPU ID: %d, status: 0x%x\n", + vgpuTypeInfo->vgpuTypeId, rmStatus); + continue; + } + + if (avail_instances == 0) + continue; + + vgpuTypeIds[*numVgpuTypes] = vgpuTypeInfo->vgpuTypeId; + (*numVgpuTypes)++; + } + } + } + +exit: + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL nv_vgpu_delete( + nvidia_stack_t *sp, + const NvU8 *pVgpuDevName, + NvU16 vgpuId +) +{ + THREAD_STATE_NODE threadState; + void *fp = NULL; + NvU32 rmStatus = NV_OK; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + rmStatus = kvgpumgrDeleteRequestVgpu(pVgpuDevName, vgpuId); + // UNLOCK: release API lock + rmapiLockRelease(); + } + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL nv_vgpu_process_vf_info( + nvidia_stack_t *sp, + nv_state_t *pNv, + NvU8 cmd, + NvU32 domain, + NvU8 bus, + NvU8 slot, + NvU8 function, + NvBool isMdevAttached, + void *vf_pci_info +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_OK; + void *fp = NULL; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + rmStatus = kvgpumgrProcessVfInfo(pNv->gpu_id, cmd, domain, bus, slot, function, isMdevAttached, (vgpu_vf_pci_info *) vf_pci_info); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL nv_vgpu_create_request( + nvidia_stack_t *sp, + nv_state_t *pNv, + const NvU8 *pVgpuDevName, + NvU32 vgpuTypeId, + NvU16 *vgpuId, + NvU32 *gpu_instance_id, + NvU32 *placement_id, + NvU32 gpuPciBdf +) +{ + THREAD_STATE_NODE threadState; + void *fp = NULL; + NV_STATUS rmStatus = NV_OK; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + rmStatus = kvgpumgrCreateRequestVgpu(pNv->gpu_id, pVgpuDevName, + vgpuTypeId, vgpuId, gpu_instance_id, placement_id, gpuPciBdf); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +static NV_STATUS is_bar_64bit( + OBJGPU *pGpu, + NvU32 regionIndex, + NvBool *isBar64bit +) +{ + NV_STATUS rmStatus = NV_OK; + + if (pGpu == NULL) + { + NV_PRINTF(LEVEL_ERROR, "%s GPU handle is not valid \n", __FUNCTION__); + rmStatus = NV_ERR_INVALID_STATE; + goto exit; + } + + switch (regionIndex) + { + case NV_VFIO_PCI_BAR0_REGION_INDEX: + *isBar64bit = pGpu->sriovState.b64bitVFBar0; + break; + + case NV_VFIO_PCI_BAR1_REGION_INDEX: + *isBar64bit = pGpu->sriovState.b64bitVFBar1; + break; + + case NV_VFIO_PCI_BAR2_REGION_INDEX: + *isBar64bit = pGpu->sriovState.b64bitVFBar2; + break; + + default: + NV_PRINTF(LEVEL_ERROR, "BAR%d region doesn't exist!\n", regionIndex); + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto exit; + break; + } + + NV_PRINTF(LEVEL_INFO, "BAR%d region is_64bit: %d\n", regionIndex, *isBar64bit);; + +exit: + return rmStatus; +} + +static NV_STATUS +_nv_vgpu_get_bar_size(OBJGPU *pGpu, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, + NvU32 regionIndex, NvU64 *size, NvU8 *configParams) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + NV_STATUS status; + KernelBus *pKernelBus; + NvU32 value = 0; + + pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + *size = kbusGetPciBarSize(pKernelBus, regionIndex); + + if (regionIndex == NV_VFIO_PCI_BAR1_REGION_INDEX) + { + VGPU_TYPE *vgpuTypeInfo; + NvU32 pgpuIndex = 0; + NvBool bOverrideBar1Size = NV_FALSE; + + // Read BAR1 length from vgpuTypeInfo + NV_ASSERT_OK_OR_RETURN(kvgpumgrGetVgpuTypeInfo(pKernelHostVgpuDevice->vgpuType, + &vgpuTypeInfo)); + + *size = vgpuTypeInfo->bar1Length << 20; + NV_ASSERT_OK_OR_RETURN(kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &pgpuIndex)); + + /* + * check for 'override_bar1_size' param in vgpuExtraParams list first, + * if param is missing there then check it in vgpu_params list + */ + status = nv_parse_config_params((const char*)vgpuTypeInfo->vgpuExtraParams, + "override_bar1_size", ';', &value); + if (status == NV_OK && value) + { + bOverrideBar1Size = NV_TRUE; + } + else if (status == NV_ERR_OBJECT_NOT_FOUND) + { + status = nv_parse_config_params((const char *)configParams, + "override_bar1_size", ',', &value); + if (status == NV_OK && value) + bOverrideBar1Size = NV_TRUE; + } + + if (gpuIsVfResizableBAR1Supported(pGpu)) + { + if ((*size > pGpu->sriovState.vfBarSize[1]) || + (!portStringCompare("Compute", (const char *)vgpuTypeInfo->vgpuClass, 7))) + { + *size = pGpu->sriovState.vfBarSize[1]; + } + } + + if (bOverrideBar1Size) + { + NvU64 bar1SizeInBytes, guestBar1; + NvU64 gpuBar1LowerLimit = 256 * 1024 * 1024; // bar1 lower limit for override_bar1_length parameter + bar1SizeInBytes = kbusGetPciBarSize(pKernelBus, NV_VFIO_PCI_BAR1_REGION_INDEX); + + if (pKernelVgpuMgr->pgpuInfo[pgpuIndex].sriovEnabled) + { + *size = pGpu->sriovState.vfBarSize[1]; + } + else if (bar1SizeInBytes > gpuBar1LowerLimit) + { + guestBar1 = bar1SizeInBytes / vgpuTypeInfo->maxInstance; + *size = nvPrevPow2_U64(guestBar1); + } + } + } + else if (regionIndex == NV_VFIO_PCI_BAR2_REGION_INDEX || + regionIndex == NV_VFIO_PCI_BAR3_REGION_INDEX) + { + status = nv_parse_config_params((const char *)configParams, + "address64", ',', &value); + + if ((status != NV_OK) || ((status == NV_OK) && (value != 0))) + { + if (regionIndex == NV_VFIO_PCI_BAR2_REGION_INDEX) + *size = 0; + else if (regionIndex == NV_VFIO_PCI_BAR3_REGION_INDEX) + *size = kbusGetPciBarSize(pKernelBus, NV_VFIO_PCI_BAR2_REGION_INDEX); + } + } + + return NV_OK; +} + +NV_STATUS NV_API_CALL nv_vgpu_get_bar_info +( + nvidia_stack_t *sp, + nv_state_t *pNv, + const NvU8 *pVgpuDevName, + NvU64 *barSizes, + NvU64 *sparseOffsets, + NvU64 *sparseSizes, + NvU32 *sparseCount, + NvBool *isBar064bit, + NvU8 *configParams +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_OK; + OBJGPU *pGpu = NULL; + void *fp = NULL; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_SILENT, + rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR), exit); + + pGpu = NV_GET_NV_PRIV_PGPU(pNv); + if (pGpu == NULL) + { + NV_PRINTF(LEVEL_ERROR, "%s GPU handle is not valid \n", __FUNCTION__); + rmStatus = NV_ERR_INVALID_STATE; + goto release_lock; + } + + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_SILENT, + nv_vgpu_rm_get_bar_info(pGpu, pVgpuDevName, barSizes, + sparseOffsets, sparseSizes, + sparseCount, isBar064bit, + configParams), + release_lock); +release_lock: + // UNLOCK: release API lock + rmapiLockRelease(); + +exit: + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL nv_vgpu_update_sysfs_info +( + nvidia_stack_t *sp, + nv_state_t *pNv, + const NvU8 *pVgpuDevName, + NvU32 mode, + NvU32 *sysfs_val +) +{ + THREAD_STATE_NODE threadState; + void *fp = NULL; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + REQUEST_VGPU_INFO_NODE *pRequestVgpu = NULL; + NV_STATUS rmStatus = NV_OK; + VGPU_SYSFS_OP updateMode = (VGPU_SYSFS_OP)mode; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_SILENT, + rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR), exit); + + // Check the corresponding REQUEST_VGPU_INFO_NODE + for (pRequestVgpu = listHead(&pKernelVgpuMgr->listRequestVgpuHead); + pRequestVgpu != NULL; + pRequestVgpu = listNext(&pKernelVgpuMgr->listRequestVgpuHead, pRequestVgpu)) + { + if (portMemCmp(pRequestVgpu->vgpuDevName, pVgpuDevName, VM_UUID_SIZE) == 0) + break; + } + + if (pRequestVgpu == NULL) + { + rmStatus = NV_ERR_OBJECT_NOT_FOUND; + goto release_lock; + } + + if (updateMode == SET_GPU_INSTANCE_ID) + rmStatus = kvgpumgrSetGpuInstanceId(pRequestVgpu, *sysfs_val); + else if (updateMode == SET_PLACEMENT_ID) + rmStatus = kvgpumgrSetPlacementId(pRequestVgpu, *sysfs_val); + else if (updateMode == GET_PLACEMENT_ID) + *sysfs_val = pRequestVgpu->placementId; + +release_lock: + // UNLOCK: release API lock + rmapiLockRelease(); + +exit: + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL nv_vgpu_get_hbm_info( + nvidia_stack_t *sp, + nv_state_t *pNv, + const NvU8 *pVgpuDevName, + NvU64 *hbmAddr, + NvU64 *size +) +{ + NV_STATUS rmStatus = NV_OK; + THREAD_STATE_NODE threadState; + OBJGPU *pGpu = NULL; + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; + void *fp = NULL; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + if ((size == NULL) || (hbmAddr == NULL)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto exit; + } + + // LOCK: acquire API lock + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_SILENT, rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR), exit); + + pGpu = NV_GET_NV_PRIV_PGPU(pNv); + if (pGpu == NULL) + { + NV_PRINTF(LEVEL_ERROR, "%s GPU handle is not valid \n", __FUNCTION__); + rmStatus = NV_ERR_INVALID_STATE; + goto release_lock; + } + + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_SILENT, + kvgpumgrGetHostVgpuDeviceFromVgpuDevName(pNv->gpu_id, + pVgpuDevName, + &pKernelHostVgpuDevice), release_lock); + if (pKernelHostVgpuDevice->numValidHbmRegions > 1) + { + NV_PRINTF(LEVEL_NOTICE, "non contiguous HBM region is not supported\n"); + NV_ASSERT(0); + } + + if (pKernelHostVgpuDevice->hbmRegionList != NULL) + { + *hbmAddr = pKernelHostVgpuDevice->hbmRegionList[0].hbmBaseAddr; + *size = pKernelHostVgpuDevice->hbmRegionList[0].size; + } + else + { + *hbmAddr = 0; + *size = 0; + } + +release_lock: + // UNLOCK: release API lock + rmapiLockRelease(); +exit: + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +static NV_STATUS nv_parse_config_params( + const char *config_params, + const char *key, + const char delim, + NvU32 *config_value +) +{ + char *ptr, *configParams = rm_remove_spaces(config_params); + char *token, *value, *name; + NvU32 data; + NV_STATUS rmStatus = NV_ERR_OBJECT_NOT_FOUND; + + ptr = configParams; + while ((token = rm_string_token(&ptr, delim)) != NULL) + { + if (!(name = rm_string_token(&token, '=')) || !os_string_length(name)) + continue; + + if (!(value = rm_string_token(&token, '=')) || !os_string_length(value)) + continue; + + data = os_strtoul(value, NULL, 0); + + if (os_string_compare(name, key) == 0) + { + rmStatus = NV_OK; + *config_value = data; + } + } + + // Free the memory allocated by rm_remove_spaces() + os_free_mem(configParams); + + return rmStatus; +} + +static NV_STATUS _nv_vgpu_get_sparse_mmap( + OBJGPU *pGpu, + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, + NvU64 *offsets, + NvU64 *sizes, + NvU32 *numAreas, + NvU8 *configParams +) +{ + NV_STATUS rmStatus = NV_OK, status; + OBJTMR *pTmr = GPU_GET_TIMER(pGpu);; + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu);; + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + NvU32 value = 0; + + *numAreas = 0; + if (pKernelHostVgpuDevice->gfid != 0) + { + rmStatus = kbifGetVFSparseMmapRegions_HAL(pGpu, pKernelBif, pKernelHostVgpuDevice, + os_page_size, numAreas, NULL, NULL); + if (rmStatus == NV_OK) + { + if (*numAreas > NVA081_MAX_SPARSE_REGION_COUNT) + { + NV_PRINTF(LEVEL_ERROR, "Not enough space for sparse mmap region info\n"); + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + + rmStatus = kbifGetVFSparseMmapRegions_HAL(pGpu, pKernelBif, pKernelHostVgpuDevice, os_page_size, + numAreas, offsets, sizes); + if (rmStatus != NV_OK) + return rmStatus; + } + } + else + { + status = nv_parse_config_params((const char *)configParams, + "direct_gpu_timer_access", ',', &value); + if ((status == NV_OK) && (value != 0)) + { + NvU64 offset = 0; + NvU32 size = 0; + + rmStatus = tmrGetTimerBar0MapInfo_HAL(pGpu, pTmr, &offset, &size); + + if (rmStatus == NV_OK) + { + offsets[*numAreas] = offset; + sizes[*numAreas] = size; + (*numAreas)++; + } + } + + value = 0; + { + NvU64 offset = 0; + NvU32 size = 0; + + status = kfifoGetUsermodeMapInfo_HAL(pGpu, pKernelFifo, &offset, &size); + + if (status == NV_OK) + { + offsets[*numAreas] = offset; + sizes[*numAreas] = size; + (*numAreas)++; + } + } + } + + return rmStatus; +} + +NV_STATUS nv_vgpu_rm_get_bar_info +( + OBJGPU *pGpu, + const NvU8 *pVgpuDevName, + NvU64 *barSizes, + NvU64 *sparseOffsets, + NvU64 *sparseSizes, + NvU32 *sparseCount, + NvBool *isBar064bit, + NvU8 *configParams +) +{ + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; + NV_STATUS rmStatus; + NvU32 i = 0; + + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_SILENT, + is_bar_64bit(pGpu, NV_VFIO_PCI_BAR0_REGION_INDEX, isBar064bit), + exit); + + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_SILENT, + kvgpumgrGetHostVgpuDeviceFromVgpuDevName(pGpu->gpuId, + pVgpuDevName, + &pKernelHostVgpuDevice), + exit); + + for (i = 0; i < NVA081_MAX_BAR_REGION_COUNT; i++) + { + /* + * For SRIOV, only VF BAR1 is queried via RM, others BARs are directly + * queried via VF config space in vgpu-vfio + */ + if (gpuIsSriovEnabled(pGpu) && (i != NV_VFIO_PCI_BAR1_REGION_INDEX)) + { + barSizes[i] = 0; + continue; + } + + rmStatus = _nv_vgpu_get_bar_size(pGpu, pKernelHostVgpuDevice, i, + &barSizes[i], configParams); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to query BAR size for index %u 0x%x\n", + i, rmStatus); + goto exit; + } + } + + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_SILENT, + _nv_vgpu_get_sparse_mmap(pGpu, pKernelHostVgpuDevice, + sparseOffsets, sparseSizes, + sparseCount, configParams), + exit); + +exit: + return rmStatus; +} + +NV_STATUS NV_API_CALL nv_gpu_unbind_event +( + nvidia_stack_t *sp, + NvU32 gpuId, + NvBool *isEventNotified +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_OK; + void *fp = NULL; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_UNBIND eventData = { 0 }; + + // Send gpu_id so that nvidia-vgpu-mgr daemon knows which GPU is being unbound + eventData.gpuId = gpuId; + CliAddSystemEvent(NV0000_NOTIFIERS_VGPU_UNBIND_EVENT, &eventData, isEventNotified); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL nv_gpu_bind_event( + nvidia_stack_t *sp, + NvU32 gpuId, + NvBool *isEventNotified +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_OK; + void *fp = NULL; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_BIND eventData = { 0 }; + + eventData.gpuId = gpuId; + CliAddSystemEvent(NV0000_NOTIFIERS_VGPU_BIND_EVENT, &eventData, isEventNotified); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS osIsVgpuVfioPresent(void) +{ + vgpu_vfio_info vgpu_info; + + return os_call_vgpu_vfio((void *) &vgpu_info, CMD_VGPU_VFIO_PRESENT); +} + +NV_STATUS osIsVfioPciCorePresent(void) +{ + vgpu_vfio_info vgpu_info; + + return os_call_vgpu_vfio((void *) &vgpu_info, CMD_VFIO_PCI_CORE_PRESENT); +} + +void osWakeRemoveVgpu(NvU32 gpuId, NvU32 returnStatus) +{ + vgpu_vfio_info vgpu_info; + + vgpu_info.return_status = returnStatus; + vgpu_info.domain = GPU_32_BIT_ID_DECODE_DOMAIN(gpuId); + vgpu_info.bus = GPU_32_BIT_ID_DECODE_BUS(gpuId); + vgpu_info.device = GPU_32_BIT_ID_DECODE_DEVICE(gpuId); + + os_call_vgpu_vfio((void *)&vgpu_info, CMD_VFIO_WAKE_REMOVE_GPU); +} + +NvBool osIsGridSupported(OBJGPU *pGpu) +{ + return (os_is_grid_supported() || os_get_grid_csp_support() || hypervisorIsVgxHyper()); +} + +NvU32 osGetGridCspSupport(void) +{ + return os_get_grid_csp_support(); +} + +void initVGXSpecificRegistry(OBJGPU *pGpu) +{ + NvU32 data32; + osWriteRegistryDword(pGpu, NV_REG_STR_RM_POWER_FEATURES, 0x55455555); + osWriteRegistryDword(pGpu, NV_REG_STR_RM_INFOROM_DISABLE_BBX, + NV_REG_STR_RM_INFOROM_DISABLE_BBX_YES); + if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_DUMP_NVLOG, &data32) != NV_OK)) + { + osWriteRegistryDword(pGpu, NV_REG_STR_RM_DUMP_NVLOG, + NV_REG_STR_RM_DUMP_NVLOG_ENABLE); + } + osWriteRegistryDword(pGpu, NV_REG_STR_RM_RC_WATCHDOG, + NV_REG_STR_RM_RC_WATCHDOG_DISABLE); + osWriteRegistryDword(pGpu, NV_REG_STR_CL_FORCE_P2P, + DRF_DEF(_REG_STR, _CL_FORCE_P2P, _READ, _DISABLE) | + DRF_DEF(_REG_STR, _CL_FORCE_P2P, _WRITE, _DISABLE)); +} + + +NV_STATUS rm_is_vgpu_supported_device( + OS_GPU_INFO *pOsGpuInfo, + NvU32 pmc_boot_1, + NvU32 pmc_boot_42 +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); + NvBool is_sriov_enabled = FLD_TEST_DRF(_PMC, _BOOT_1, _VGPU, _VF, pmc_boot_1); + NvU32 i; + + // if not running in vGPU mode (guest VM) return NV_OK + if (!(pHypervisor && pHypervisor->bIsHVMGuest && + (FLD_TEST_DRF(_PMC, _BOOT_1, _VGPU, _PV, pmc_boot_1) || + is_sriov_enabled))) + { + return NV_OK; + } + + if (!is_sriov_enabled) + { + return NV_OK; + } + + if (os_is_grid_supported() && !gpumgrIsVgxRmFirmwareCapableChip(pmc_boot_42)) + { + return NV_ERR_NOT_SUPPORTED; + } + + if (os_is_grid_supported()) + { + for (i = 0; i < NV_ARRAY_ELEMENTS(sVgpuUsmTypes); i++) + { + if (pOsGpuInfo->pci_info.device_id == sVgpuUsmTypes[i].ulDevID && + pOsGpuInfo->subsystem_id == sVgpuUsmTypes[i].ulSubID) + { + return NV_OK; + } + } + } + + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS osIsVgpuDeviceVmPresent(void) +{ + return os_device_vm_present(); +} diff --git a/userspace/sdks/nv570/nvalloc/unix/src/os.c b/userspace/sdks/nv570/nvalloc/unix/src/os.c new file mode 100644 index 0000000..b441a66 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/src/os.c @@ -0,0 +1,6359 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include // NV device driver interface +#include +#include +#include +#include +#include +#include +#include +#include // NV_EVENT_BUFFER_BIND +#include + +#include +#include + +#include "gpu/gpu.h" +#include +#include + +#include "nverror.h" +#include "kernel/gpu/bif/kernel_bif.h" + +#include "gpu/mig_mgr/kernel_mig_manager.h" + +#include "gpu/mem_sys/kern_mem_sys.h" + +#include "mem_mgr/io_vaspace.h" +#include +#include "kernel/diagnostics/xid_context.h" +#include "gpu/mem_mgr/mem_desc.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "core/thread_state.h" +#include +#include +#include +#include +#include "virtualization/hypervisor/hypervisor.h" +#include "rmobjexportimport.h" +#include +#include "rmapi/rs_utils.h" +#include "rmapi/client_resource.h" +#include "os/dce_rm_client_ipc.h" +#include "mem_mgr/mem.h" +#include "gpu/mem_mgr/virt_mem_allocator_common.h" +#include "nvrm_registry.h" + +#include "vgpu/vgpu_util.h" + +#include "platform/chipset/chipset.h" + +#include +#include +#include "gps.h" +#include "jt.h" + + + + +extern const char *ppOsBugCheckBugcodeStr[]; + + +ct_assert(NV_RM_PAGE_SIZE == RM_PAGE_SIZE); +ct_assert(NV_RM_PAGE_MASK == RM_PAGE_MASK); +ct_assert(NV_RM_PAGE_SHIFT == RM_PAGE_SHIFT); + +typedef struct +{ + NvU32 euid; + NvU32 pid; +} TOKEN_USER, *PTOKEN_USER; + +struct OS_RM_CAPS +{ + NvU32 count; + + // This should be the last element + nv_cap_t **caps; +}; + +NvBool osIsRaisedIRQL(void) +{ + return (!os_semaphore_may_sleep()); +} + +NvBool osIsISR(void) +{ + return os_is_isr(); +} + +NV_STATUS osGetDriverBlock +( + OS_GPU_INFO *pOsGpuInfo, + OS_DRIVER_BLOCK *pBlock +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NvU64 osGetMonotonicTimeNs(void) +{ + return os_get_monotonic_time_ns(); +} + +NV_STATUS osGetPerformanceCounter(NvU64 *pTimeInNs) +{ + *pTimeInNs = os_get_monotonic_time_ns_hr(); + return NV_OK; +} + +NV_STATUS osGetSystemTime( + NvU32 *pSeconds, + NvU32 *pMicroSeconds +) +{ + return os_get_system_time(pSeconds, pMicroSeconds); +} + +/*! + * @brief Get timestamp for logging. + * + * Everything that logs a time stamp should use this routine for consistency. + * + * The returned value is OS dependent. We want the time stamp to use + * KeQueryPerformanceCounter on Windows so it matches the DirectX timestamps. + * Linux uses microseconds since 1970 (osGetSystemTime), since matching DirectX + * is not a priority. + * + * osGetTimestampFreq returns the frequency required to decode the time stamps. + * + * @returns system dependent timestamp. + */ +NvU64 osGetTimestamp(void) +{ + NvU32 sec = 0; + NvU32 usec = 0; + osGetSystemTime(&sec, &usec); + return (NvU64)sec * 1000000 + usec; +} + +/*! + * @brief Get timestamp frequency. + * + * Timestamps are OS dependent. This call returns the frequency + * required to decode them. + * + * @returns Timestamp frequency. For example, 1000000 for MHz. + */ +NvU64 osGetTimestampFreq(void) +{ + return 1000000; +} + +NV_STATUS osDelay(NvU32 milliseconds) +{ + return os_delay(milliseconds); +} + +NV_STATUS osDelayUs(NvU32 microseconds) +{ + return os_delay_us(microseconds); +} + +NV_STATUS osDelayNs(NvU32 nanoseconds) +{ + NvU32 microseconds = NV_MAX(1, (nanoseconds / 1000)); + return os_delay_us(microseconds); +} + +NvU32 osGetCpuFrequency(void) +{ + /* convert os_get_cpu_frequency()'s return value from Hz to MHz */ + return ((NvU32)(os_get_cpu_frequency() / 1000000ULL)); +} + +void* osPciInitHandle( + NvU32 Domain, + NvU8 Bus, + NvU8 Slot, + NvU8 Function, + NvU16 *pVendor, + NvU16 *pDevice +) +{ + // + // Check if the BDF is for a GPU that's already been attached, for which + // we should already have a handle cached. This won't catch devices that + // have been probed but not yet attached, but that shouldn't be a common + // occurrence. + // + // More importantly, having this check here means we don't need to check + // a global list of devices in the kernel interface layer, which could + // have the implication of taking another lock, causing hairy lock + // ordering issues. + // + if (Function == 0) + { + OBJGPU *pGpu = gpumgrGetGpuFromBusInfo(Domain, Bus, Slot); + if (pGpu != NULL) + { + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + if (pVendor) *pVendor = nv->pci_info.vendor_id; + if (pDevice) *pDevice = nv->pci_info.device_id; + return nv->handle; + } + } + + return os_pci_init_handle(Domain, Bus, Slot, Function, pVendor, pDevice); +} + +NvU8 osPciReadByte( + void *pHandle, + NvU32 Offset +) +{ + NvU8 val; + os_pci_read_byte(pHandle, Offset, &val); + return val; +} + +NvU16 osPciReadWord( + void *pHandle, + NvU32 Offset +) +{ + NvU16 val; + os_pci_read_word(pHandle, Offset, &val); + return val; +} + +NvU32 osPciReadDword( + void *pHandle, + NvU32 Offset +) +{ + NvU32 val; + os_pci_read_dword(pHandle, Offset, &val); + return val; +} + +void osPciWriteByte( + void *pHandle, + NvU32 Offset, + NvU8 Value +) +{ + os_pci_write_byte(pHandle, Offset, Value); +} + +void osPciWriteWord( + void *pHandle, + NvU32 Offset, + NvU16 Value +) +{ + os_pci_write_word(pHandle, Offset, Value); +} + +void osPciWriteDword( + void *pHandle, + NvU32 Offset, + NvU32 Value +) +{ + os_pci_write_dword(pHandle, Offset, Value); +} + +void* osMapKernelSpace( + RmPhysAddr Start, + NvU64 Size, + NvU32 Mode, + NvU32 Protect +) +{ + NvU64 offset; + NvU8 *ptr; + + if (0 == Size) + { + NV_ASSERT(Size != 0); + return NULL; + } + + offset = (Start & ~os_page_mask); + Start &= os_page_mask; + + if (!portSafeAddU64(Size, offset, &Size) || + !portSafeAddU64(Size, ~os_page_mask, &Size)) + { + return NULL; + } + Size &= os_page_mask; + + ptr = os_map_kernel_space(Start, Size, Mode); + if (ptr != NULL) + return (ptr + offset); + + return NULL; +} + +void osUnmapKernelSpace( + void *pAddress, + NvU64 Size +) +{ + NvU64 offset; + NvUPtr ptr = (NvUPtr)pAddress; + + if (0 == Size) + { + NV_ASSERT(Size != 0); + return; + } + + offset = (ptr & ~os_page_mask); + ptr &= os_page_mask; + Size = ((Size + offset + ~os_page_mask) & os_page_mask); + os_unmap_kernel_space((void *)ptr, Size); +} + +static NV_STATUS setNumaPrivData +( + KernelMemorySystem *pKernelMemorySystem, + nv_state_t *nv, + MEMORY_DESCRIPTOR *pMemDesc +) +{ + NV_STATUS rmStatus = NV_OK; + void *pAllocPrivate = NULL; + NvU64 *addrArray = NULL; + NvU64 numPages = pMemDesc->PageCount; + NvU64 numOsPages = numPages; + RmPhysAddr *pteArray = memdescGetPteArray(pMemDesc, AT_CPU); + NvU64 i; + + // + // Since this function will also deal with the memory allocated from PMA, + // we have to perform page size inflate/deflate here. + // + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc)) + { + NvU64 size = pMemDesc->ActualSize; + numOsPages = size / NV_MIN(os_page_size, pMemDesc->pageArrayGranularity); + } + + addrArray = portMemAllocNonPaged(numOsPages * sizeof(NvU64)); + if (addrArray == NULL) + { + return NV_ERR_NO_MEMORY; + } + + if (!IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc) && NV_RM_PAGE_SIZE < os_page_size) + { + numOsPages = NV_RM_PAGES_TO_OS_PAGES(numPages); + } + + if (!memdescGetContiguity(pMemDesc, AT_CPU)) + { + NvU64 copyByteSize = 0; + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc)) + { + // pMemDesc->pageArraySize is calculated by 4KB, it should NOT smaller than `numOSPages`. + NV_ASSERT_OR_ELSE(pMemDesc->pageArraySize >= numOsPages, rmStatus = NV_ERR_INVALID_STATE; goto errors); + copyByteSize = numOsPages * sizeof(NvU64); + } + else + { + copyByteSize = numPages * sizeof(NvU64); + } + + portMemCopy((void*)addrArray, + copyByteSize, + (void*)pteArray, + copyByteSize); + + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc)) + { + NvU64 size = pMemDesc->ActualSize; + // + // Because of PMA case, we need to convert page array + // from RM native granularity to OS granularity. + // + convertPageArrayBetweenOsAndRm( + addrArray, + size / pMemDesc->pageArrayGranularity, + pMemDesc->pageArrayGranularity, + size / os_page_size, + os_page_size, + &numOsPages + ); + } + else if (NV_RM_PAGE_SIZE < os_page_size) + { + RmDeflateRmToOsPageArray(addrArray, numPages); + } + + for (i = 0; i < numOsPages; i++) + { + // Update GPA to system physical address + addrArray[i] += pKernelMemorySystem->coherentCpuFbBase; + } + } + else + { + // + // Original PTE array in contiguous memdesc only holds start address. + // We need to fill the OS page array with adjacent page addresses to + // map contiguously. + // + NvU64 offset = pteArray[0] + pKernelMemorySystem->coherentCpuFbBase; + + for (i = 0; i < numOsPages; i++, offset += os_page_size) + { + addrArray[i] = offset; + } + } + + rmStatus = nv_register_phys_pages(nv, addrArray, numOsPages, NV_MEMORY_CACHED, &pAllocPrivate); + if (rmStatus != NV_OK) + { + goto errors; + } + + memdescSetMemData(pMemDesc, pAllocPrivate, NULL); + +errors: + portMemFree(addrArray); + + return rmStatus; +} + +NV_STATUS osGetNumMemoryPages +( + MEMORY_DESCRIPTOR *pMemDesc, + NvU32 *pNumPages +) +{ + void *pAllocPrivate = NULL; + + pAllocPrivate = memdescGetMemData(pMemDesc); + if (pAllocPrivate == NULL) + { + NV_PRINTF(LEVEL_ERROR, "pAllocPrivate is NULL!\n"); + return NV_ERR_INVALID_STATE; + } + + return nv_get_num_phys_pages(pAllocPrivate, pNumPages); +} + +NV_STATUS osGetMemoryPages +( + MEMORY_DESCRIPTOR *pMemDesc, + void *pPages, + NvU32 *pNumPages +) +{ + void *pAllocPrivate = NULL; + + pAllocPrivate = memdescGetMemData(pMemDesc); + if (pAllocPrivate == NULL) + { + NV_PRINTF(LEVEL_ERROR, "pAllocPrivate is NULL!\n"); + return NV_ERR_INVALID_STATE; + } + + return nv_get_phys_pages(pAllocPrivate, pPages, pNumPages); +} + +NV_STATUS osMapSystemMemory +( + MEMORY_DESCRIPTOR *pMemDesc, + NvU64 Offset, + NvU64 Length, + NvBool Kernel, + NvU32 Protect, + NvP64 *ppAddress, + NvP64 *ppPrivate +) +{ + OBJGPU *pGpu = pMemDesc->pGpu; + + NvU64 rootOffset = 0; + pMemDesc = memdescGetRootMemDesc(pMemDesc, &rootOffset); + Offset += rootOffset; + + RmPhysAddr userAddress; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + NV_STATUS rmStatus = NV_OK; + void *pAllocPrivate = NULL; + void *pAddress; + void *pPrivate = NULL; + NvU64 pageIndex; + NvU32 pageOffset = (Offset & ~os_page_mask); + + if (pGpu != NULL && + pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) && + memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM) + { + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + + rmStatus = setNumaPrivData(pKernelMemorySystem, nv, pMemDesc); + if (rmStatus != NV_OK) + return rmStatus; + + pageOffset = memdescGetPhysAddr(pMemDesc, FORCE_VMMU_TRANSLATION(pMemDesc, AT_GPU), Offset) & ~os_page_mask; + } + + *ppAddress = NvP64_NULL; + *ppPrivate = NvP64_NULL; + + if ((Offset + Length) < Length) + return NV_ERR_INVALID_ARGUMENT; + if ((Offset + Length) > pMemDesc->Size) + return NV_ERR_INVALID_ARGUMENT; + + pageIndex = (Offset >> os_page_shift); + + pAllocPrivate = memdescGetMemData(pMemDesc); + if (!pAllocPrivate) + { + NV_PRINTF(LEVEL_ERROR, "pAllocPrivate is NULL!\n"); + return NV_ERR_INVALID_STATE; + } + + if (Kernel) + { + pAddress = nv_alloc_kernel_mapping(nv, pAllocPrivate, + pageIndex, pageOffset, Length, &pPrivate); + if (pAddress == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "failed to create system memory kernel mapping!\n"); + rmStatus = NV_ERR_GENERIC; + } + else + { + *ppAddress = NV_PTR_TO_NvP64(pAddress); + *ppPrivate = NV_PTR_TO_NvP64(pPrivate); + } + } + else + { + rmStatus = nv_alloc_user_mapping(nv, pAllocPrivate, + pageIndex, pageOffset, Length, Protect, &userAddress, + &pPrivate); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "failed to create system memory user mapping!\n"); + } + else + { + *ppAddress = (NvP64)(userAddress); + *ppPrivate = NV_PTR_TO_NvP64(pPrivate); + } + } + + return rmStatus; +} + +void osUnmapSystemMemory +( + MEMORY_DESCRIPTOR *pMemDesc, + NvBool Kernel, + NvP64 pAddress, + NvP64 pPrivate +) +{ + void *pAllocPrivate; + OBJGPU *pGpu = pMemDesc->pGpu; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + pMemDesc = memdescGetRootMemDesc(pMemDesc, NULL); + pAllocPrivate = memdescGetMemData(pMemDesc); + + if (Kernel) + { + nv_free_kernel_mapping(nv, pAllocPrivate, NvP64_VALUE(pAddress), + NvP64_VALUE(pPrivate)); + } + else + { + nv_free_user_mapping(nv, pAllocPrivate, (NvU64)pAddress, + NvP64_VALUE(pPrivate)); + } + + if (pGpu != NULL && + pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) && + memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM && + pAllocPrivate != NULL) + { + nv_unregister_phys_pages(nv, pAllocPrivate); + memdescSetMemData(pMemDesc, NULL, NULL); + } +} + +void osIoWriteByte( + NvU32 Address, + NvU8 Value +) +{ + os_io_write_byte(Address, Value); +} + +NvU16 osIoReadWord( + NvU32 Address +) +{ + return os_io_read_word(Address); +} + +void osIoWriteWord( + NvU32 Address, + NvU16 Value +) +{ + os_io_write_word(Address, Value); +} + +NvU8 osIoReadByte( + NvU32 Address +) +{ + return os_io_read_byte(Address); +} + +NvBool osIsAdministrator(void) +{ + return os_is_administrator(); +} + +NvBool osCheckAccess(RsAccessRight accessRight) +{ + return os_check_access(accessRight); +} + +NvU32 osGetCurrentProcess(void) +{ + return os_get_current_process(); +} + +void osGetCurrentProcessName(char *ProcName, NvU32 Length) +{ + return os_get_current_process_name(ProcName, Length); +} + +NV_STATUS osGetCurrentThread(OS_THREAD_HANDLE *pThreadId) +{ + NV_STATUS rmStatus; + NvU64 threadId = 0; + + if (pThreadId == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + rmStatus = os_get_current_thread(&threadId); + if (rmStatus == NV_OK) + { + *pThreadId = threadId; + } + else + { + *pThreadId = 0; + } + + return rmStatus; +} + +void* osGetPidInfo(void) +{ + return os_get_pid_info(); +} + +void osPutPidInfo(void *pOsPidInfo) +{ + os_put_pid_info(pOsPidInfo); +} + +NV_STATUS osFindNsPid(void *pOsPidInfo, NvU32 *pNsPid) +{ + return os_find_ns_pid(pOsPidInfo, pNsPid); +} + +NvBool osIsInitNs(void) +{ + return os_is_init_ns(); +} + +NV_STATUS osAttachToProcess(void** ppProcessInfo, NvU32 ProcessId) +{ + // + // This function is used by RmUnmapMemory() to attach to the + // process for which a given device memory mapping was + // created, in order to be able to unmap it. On Linux/UNIX + // platforms, we can't "attach" to a random process, but + // since we don't create/destroy user mappings in the RM, we + // don't need to, either. + // + // Report success to the caller to keep RmUnmapMemory() from + // failing, and memory from being leaked as a result. + // + *ppProcessInfo = NULL; + return NV_OK; +} + +void osDetachFromProcess(void* pProcessInfo) +{ + // stub + return; +} + +NV_STATUS osAcquireRmSema(void *pSema) +{ + return NV_OK; +} + +NV_STATUS osCondAcquireRmSema(void *pSema) +{ + return NV_OK; +} + +NvU32 osReleaseRmSema(void *pSema, OBJGPU *pDpcGpu) +{ + return NV_SEMA_RELEASE_SUCCEED; +} + +void osSpinLoop(void) +{ + +} + +NvU64 osGetMaxUserVa(void) +{ + return os_get_max_user_va(); +} + +NV_STATUS osSchedule(void) +{ + return os_schedule(); +} + +NV_STATUS osQueueWorkItem( + OBJGPU *pGpu, + OSWorkItemFunction pFunction, + void *pParams, + OsQueueWorkItemFlags flags +) +{ + nv_work_item_t *pWi; + nv_state_t *nv; + NV_STATUS status; + + pWi = portMemAllocNonPaged(sizeof(nv_work_item_t)); + + if (NULL == pWi) + { + return NV_ERR_NO_MEMORY; + } + + pWi->flags = (OsQueueWorkItemFlags){0}; + pWi->flags.bDontFreeParams = flags.bDontFreeParams; + pWi->flags.bLockSema = flags.bLockSema; + pWi->flags.apiLock = flags.apiLock; + pWi->flags.bLockGpus = flags.bLockGpus; + pWi->flags.bLockGpuGroupDevice = flags.bLockGpuGroupDevice; + pWi->flags.bLockGpuGroupSubdevice = flags.bLockGpuGroupSubdevice; + pWi->flags.bFullGpuSanity = flags.bFullGpuSanity; + pWi->flags.bDropOnUnloadQueueFlush = flags.bDropOnUnloadQueueFlush; + pWi->flags.bSetExpandedGpuVisibility = flags.bSetExpandedGpuVisibility; + + pWi->flags.bRequiresGpu = NV_TRUE; + pWi->gpuInstance = gpuGetInstance(pGpu); + + pWi->func.pGpuFunction = pFunction; + pWi->pData = pParams; + nv = NV_GET_NV_STATE(pGpu); + + status = os_queue_work_item(nv ? nv->queue : NULL, pWi); + + if (NV_OK != status) + { + portMemFree((void *)pWi); + } + + return status; +} + +NV_STATUS osQueueSystemWorkItem( + OSSystemWorkItemFunction pFunction, + void *pParams +) +{ + nv_work_item_t *pWi; + NV_STATUS status; + + pWi = portMemAllocNonPaged(sizeof(nv_work_item_t)); + + if (NULL == pWi) + { + return NV_ERR_NO_MEMORY; + } + + pWi->flags = (OsQueueWorkItemFlags){0}; + pWi->func.pSystemFunction = pFunction; + pWi->pData = pParams; + + status = os_queue_work_item(NULL, pWi); + + if (NV_OK != status) + { + portMemFree((void *)pWi); + } + + return status; +} + +NV_STATUS osQueueSystemWorkItemWithFlags( + OSSystemWorkItemFunction pFunction, + void *pParams, + OsQueueWorkItemFlags flags +) +{ + nv_work_item_t *pWi; + NV_STATUS status; + + pWi = portMemAllocNonPaged(sizeof(nv_work_item_t)); + + if (NULL == pWi) + { + return NV_ERR_NO_MEMORY; + } + + pWi->flags = (OsQueueWorkItemFlags){0}; + pWi->flags.bDontFreeParams = flags.bDontFreeParams; + pWi->flags.bLockSema = flags.bLockSema; + pWi->flags.apiLock = flags.apiLock; + pWi->flags.bLockGpus = flags.bLockGpus; + pWi->flags.bLockGpuGroupDevice = flags.bLockGpuGroupDevice; + pWi->flags.bLockGpuGroupSubdevice = flags.bLockGpuGroupSubdevice; + pWi->flags.bFullGpuSanity = flags.bFullGpuSanity; + pWi->flags.bDropOnUnloadQueueFlush = flags.bDropOnUnloadQueueFlush; + pWi->func.pSystemFunction = pFunction; + pWi->pData = pParams; + + status = os_queue_work_item(NULL, pWi); + + if (NV_OK != status) + { + portMemFree((void *)pWi); + } + + return status; +} + +void osQueueMMUFaultHandler(OBJGPU *pGpu) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + nv_schedule_uvm_isr(nv); +} + +NvBool osGpuSupportsAts(OBJGPU *pGpu) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + // Checks ATS support from both OS side and RM side. + return nv->ats_support && + pGpu->getProperty(pGpu, PDB_PROP_GPU_ATS_SUPPORTED); +} + +NV_STATUS osQueueDrainP2PHandler(NvU8 *pUuid) +{ + return nv_schedule_uvm_drain_p2p(pUuid); +} + +void osQueueResumeP2PHandler(NvU8 *pUuid) +{ + nv_schedule_uvm_resume_p2p(pUuid); +} + +static inline nv_dma_device_t* osGetDmaDeviceForMemDesc( + OS_GPU_INFO *pOsGpuInfo, + MEMORY_DESCRIPTOR *pMemDesc +) +{ + return (pOsGpuInfo->niso_dma_dev != NULL) && + memdescGetFlag(pMemDesc, MEMDESC_FLAGS_MEMORY_TYPE_DISPLAY_NISO) ? + pOsGpuInfo->niso_dma_dev : pOsGpuInfo->dma_dev; +} + +// +// Set the DMA address size for the given GPU +// +// This is a global device setting and care would need to be taken if it was to +// be modified outside of GPU initialization. At least on Linux other drivers, +// like UVM, might be requesting its own DMA mappings for the same GPU after +// the GPU has been initialized. +// +void osDmaSetAddressSize( + OS_GPU_INFO *pOsGpuInfo, + NvU32 bits +) +{ + nv_set_dma_address_size(pOsGpuInfo, bits); +} + +static NV_STATUS osGetPagesInfo( + MEMORY_DESCRIPTOR *pMemDesc, + NvU64 *pageSize, + NvU64 *osPageCount, + NvU64 *rmPageCount +) +{ + NvU64 osPageSize = osGetPageSize(); + NvU64 maxPageSize = NV_MAX(osPageSize, RM_PAGE_SIZE); + NvU64 alignedSize = NV_ALIGN_UP(pMemDesc->Size, maxPageSize); + + *osPageCount = alignedSize >> BIT_IDX_32(osPageSize); + *rmPageCount = alignedSize >> RM_PAGE_SHIFT; + *pageSize = memdescGetAdjustedPageSize(pMemDesc); + + // In the non-contig case need to protect against page array overflows. + if (!memdescGetContiguity(pMemDesc, AT_CPU)) + NV_ASSERT_OR_RETURN(*rmPageCount <= pMemDesc->pageArraySize, NV_ERR_INVALID_ARGUMENT); + + if (*osPageCount > NV_U32_MAX || *rmPageCount > NV_U32_MAX) + return NV_ERR_INVALID_LIMIT; + + return NV_OK; +} + +NV_STATUS osAllocPagesInternal( + MEMORY_DESCRIPTOR *pMemDesc +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPU *pGpu = pMemDesc->pGpu; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + void *pMemData = NULL; + NV_STATUS status; + NvS32 nodeId = memdescGetNumaNode(pMemDesc); + NV_ADDRESS_SPACE addrSpace = memdescGetAddressSpace(pMemDesc); + NvU64 pageSize; + NvU64 osPageCount; + NvU64 rmPageCount; + NvU32 cpuCacheAttrib = memdescGetCpuCacheAttrib(pMemDesc); + + memdescSetMemData(pMemDesc, NULL, NULL); + +#if (defined(NVCPU_AARCH64) && RMCFG_MODULE_CL) + { + OBJCL *pCl = SYS_GET_CL(pSys); + + if ((pCl != NULL) && + pCl->getProperty(pCl, PDB_PROP_CL_IS_CHIPSET_IO_COHERENT) && + !memdescGetFlag(pMemDesc, MEMDESC_FLAGS_NON_IO_COHERENT)) + { + cpuCacheAttrib = NV_MEMORY_CACHED; + } + } +#endif + + // + // For carveout, the memory is already reserved so we don't have + // to allocate memory. + // + if (memdescIsCarveoutMemory(pMemDesc) || + memdescGetFlag(pMemDesc, MEMDESC_FLAGS_GUEST_ALLOCATED)) + { + // We only support carveout with contiguous memory. + if (memdescIsCarveoutMemory(pMemDesc) && + !memdescGetContiguity(pMemDesc, AT_CPU)) + { + status = NV_ERR_NOT_SUPPORTED; + goto done; + } + + status = osGetPagesInfo(pMemDesc, &pageSize, &osPageCount, &rmPageCount); + if (status != NV_OK) + goto done; + + if (!IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc) && + NV_RM_PAGE_SIZE < os_page_size && + !memdescGetContiguity(pMemDesc, AT_CPU)) + { + RmDeflateRmToOsPageArray(memdescGetPteArray(pMemDesc, AT_CPU), + rmPageCount); + } + + status = nv_alias_pages( + NV_GET_NV_STATE(pGpu), + osPageCount, + pageSize, + memdescGetContiguity(pMemDesc, AT_CPU), + cpuCacheAttrib, + memdescGetGuestId(pMemDesc), + memdescGetPteArray(pMemDesc, AT_CPU), + memdescIsCarveoutMemory(pMemDesc), + &pMemData); + } + else + { + NvBool unencrypted = 0; + + if (nv && (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_32BIT_ADDRESSABLE))) + nv->force_dma32_alloc = NV_TRUE; + + // + // If AMD SEV is enabled but APM(Ampere protected) or CC(Confidential + // Compute) mode is not enabled on the GPU, all RM and client + // allocations must be an unprotected sysmem. If APM is enabled and RM + // is allocating sysmem for its internal use, then it has to be + // unprotected as protected sysmem is not accessible to GPU. + // + unencrypted = memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY); + + // + // OBJGPU/nv may be NULL if constructing NV01_MEMORY_DEVICELESS. Assume that + // NV01_MEMORY_DEVICELESS won't be used for display. + // + if (pGpu != NULL && + pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY) && + addrSpace == ADDR_SYSMEM) + { + if (!memdescGetFlag(pMemDesc, MEMDESC_FLAGS_MEMORY_TYPE_DISPLAY_NISO) && + !NV_SOC_IS_ISO_IOMMU_PRESENT(nv)) + { + NV_PRINTF(LEVEL_INFO, "Forcing physically contiguous flags for ISO\n"); + memdescSetContiguity(pMemDesc, AT_CPU, NV_TRUE); + } + + if (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_MEMORY_TYPE_DISPLAY_NISO) && + !NV_SOC_IS_NISO_IOMMU_PRESENT(nv)) + { + NV_PRINTF(LEVEL_INFO, "Forcing physically contiguous flags for NISO\n"); + memdescSetContiguity(pMemDesc, AT_CPU, NV_TRUE); + } + } + + status = osGetPagesInfo(pMemDesc, &pageSize, &osPageCount, &rmPageCount); + if (status != NV_OK) + goto done; + + status = nv_alloc_pages( + NV_GET_NV_STATE(pGpu), + osPageCount, // TODO: This call needs to receive the page count param at the requested page size. + pageSize, + memdescGetContiguity(pMemDesc, AT_CPU), + cpuCacheAttrib, + pSys->getProperty(pSys, + PDB_PROP_SYS_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS), + unencrypted, + nodeId, + memdescGetPteArray(pMemDesc, AT_CPU), + &pMemData); + + if (nv && nv->force_dma32_alloc) + nv->force_dma32_alloc = NV_FALSE; + } + + if (status != NV_OK) + { + goto done; + } + + // Guest allocated memory is already initialized + if (!memdescGetFlag(pMemDesc, MEMDESC_FLAGS_GUEST_ALLOCATED)) + { + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc)) + { + NV_ASSERT_OK_OR_RETURN(memdescSetAllocSizeFields(pMemDesc, osPageCount * os_page_size, os_page_size)); + } + else + { + NV_ASSERT_OK_OR_RETURN(memdescSetAllocSizeFields(pMemDesc, rmPageCount * RM_PAGE_SIZE, RM_PAGE_SIZE)); + } + } + + // + // If the OS layer doesn't think in RM page size, we need to inflate the + // PTE array into RM pages. + // + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc)) + { + NV_ASSERT_OR_RETURN(pMemDesc->pageArrayGranularity == os_page_size, NV_ERR_INVALID_ARGUMENT); + } + else if (NV_RM_PAGE_SIZE < os_page_size && + !memdescGetContiguity(pMemDesc, AT_CPU)) + { + RmInflateOsToRmPageArray(memdescGetPteArray(pMemDesc, AT_CPU), + pMemDesc->PageCount); + } + + memdescSetMemData(pMemDesc, pMemData, NULL); + + if ((pGpu != NULL) && IS_VIRTUAL(pGpu)) + NV_ASSERT_OK_OR_RETURN(vgpuUpdateGuestSysmemPfnBitMap(pGpu, pMemDesc, NV_TRUE)); +done: + return status; +} + +void osFreePagesInternal( + MEMORY_DESCRIPTOR *pMemDesc +) +{ + OBJGPU *pGpu = pMemDesc->pGpu; + NV_STATUS rmStatus; + NvU64 osPageCount; + + if ((pGpu != NULL) && IS_VIRTUAL(pGpu)) + NV_ASSERT_OR_RETURN_VOID(vgpuUpdateGuestSysmemPfnBitMap(pGpu, pMemDesc, NV_FALSE) == NV_OK); + + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc)) + { + NV_ASSERT(pMemDesc->pageArrayGranularity == os_page_size); + osPageCount = pMemDesc->PageCount; + } + else if (NV_RM_PAGE_SIZE < os_page_size && + !memdescGetContiguity(pMemDesc, AT_CPU)) + { + osPageCount = NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount); + RmDeflateRmToOsPageArray(memdescGetPteArray(pMemDesc, AT_CPU), + pMemDesc->PageCount); + } + else + { + osPageCount = NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount); + } + + rmStatus = nv_free_pages(NV_GET_NV_STATE(pGpu), + osPageCount, + memdescGetContiguity(pMemDesc, AT_CPU), + memdescGetCpuCacheAttrib(pMemDesc), + memdescGetMemData(pMemDesc)); + NV_ASSERT(rmStatus == NV_OK); +} + +NV_STATUS osLockMem( + MEMORY_DESCRIPTOR *pMemDesc +) +{ + // Not supported on this OS. + DBG_BREAKPOINT(); + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS osUnlockMem( + MEMORY_DESCRIPTOR *pMemDesc +) +{ + // Not supported on this OS. + DBG_BREAKPOINT(); + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS osMapPciMemoryAreaUser +( + OS_GPU_INFO *pOsGpuInfo, + MemoryArea memArea, + NvU32 protect, + NvU32 mode, + NvP64 *pVirtualAddress, + NvP64 *pPriv +) +{ + NV_STATUS status = NV_OK; + NvU64 origStart; + NvU64 origSize; + NvU64 diffStart; + + if (memArea.numRanges == 0) + { + *pVirtualAddress = (NvP64) NULL; + *pPriv = NULL; + return NV_OK; + } + + // Fix alignment insofar as we can (middle blocks can't be force-aligned this way) + origStart = memArea.pRanges[0].start; + memArea.pRanges[0].start = NV_ALIGN_DOWN64(origStart, os_page_size); + diffStart = origStart - memArea.pRanges[0].start; + memArea.pRanges[0].size += diffStart; + origSize = memArea.pRanges[memArea.numRanges - 1llu].size; + memArea.pRanges[memArea.numRanges - 1llu].size = NV_ALIGN_UP64(origSize, os_page_size); + + { + nv_usermap_access_params_t **ppNvuap, tNvuap; + NvU64 totalRangeSize = sizeof(MemoryRange) * memArea.numRanges; + + portMemSet(&tNvuap, 0, sizeof(nv_usermap_access_params_t)); + + tNvuap.memArea = memArea; + // access_size is only for caching, we can use os_page_size for now until linux has been properly plumbed + tNvuap.access_start = memArea.pRanges[0].start; + tNvuap.access_size = os_page_size; + + tNvuap.caching = mode; + tNvuap.contig = NV_TRUE; + + ppNvuap = (nv_usermap_access_params_t **) tlsEntryAcquire(TLS_ENTRY_ID_MAPPING_CONTEXT); + NV_ASSERT_OR_RETURN(ppNvuap != NULL, NV_ERR_INVALID_STATE); + + NV_ASSERT_OK_OR_GOTO(status, + os_alloc_mem((void**) ppNvuap, sizeof(nv_alloc_mapping_context_t)), + free_tls); + + portMemCopy(*ppNvuap, sizeof(nv_usermap_access_params_t), + &tNvuap, sizeof(nv_usermap_access_params_t)); + + NV_ASSERT_OK_OR_GOTO(status, + os_alloc_mem((void**) &((*ppNvuap)->memArea.pRanges), totalRangeSize), + free_nvuap); + + portMemCopy((*ppNvuap)->memArea.pRanges, totalRangeSize, memArea.pRanges, totalRangeSize); + + *pVirtualAddress = (NvP64) (memArea.pRanges[0].start + diffStart); + goto unalign_and_return; + +free_nvuap: + os_free_mem(*ppNvuap); +free_tls: + tlsEntryRelease(TLS_ENTRY_ID_MAPPING_CONTEXT); + } +unalign_and_return: + memArea.pRanges[memArea.numRanges - 1llu].size = origSize; + memArea.pRanges[0].size -= diffStart; + memArea.pRanges[0].start = origStart; + return status; +} + +NV_STATUS osMapPciMemoryUser( + OS_GPU_INFO *pOsGpuInfo, + RmPhysAddr busAddress, + NvU64 length, + NvU32 Protect, + NvP64 *pVirtualAddress, + NvP64 *pPriv, + NvU32 modeFlag +) +{ + MemoryArea memArea; + MemoryRange memRange; + + memArea.numRanges = 1; + memArea.pRanges = &memRange; + + memRange.start = busAddress; + memRange.size = length; + + return osMapPciMemoryAreaUser(pOsGpuInfo, memArea, Protect, modeFlag, pVirtualAddress, pPriv); +} + +void osUnmapPciMemoryUser( + OS_GPU_INFO *pOsGpuInfo, + NvP64 virtualAddress, + NvU64 length, + NvP64 pPriv +) +{ +} + +NV_STATUS osMapPciMemoryKernelOld +( + OBJGPU *pGpu, + RmPhysAddr busAddress, + NvU64 length, + NvU32 Protect, + void **pVirtualAddress, + NvU32 modeFlag +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_kern_mapping_t *mapping; + + if (pVirtualAddress == NULL) + return NV_ERR_GENERIC; + + *pVirtualAddress = os_map_kernel_space(busAddress, length, modeFlag); + if (*pVirtualAddress == NULL) + return NV_ERR_GENERIC; + + mapping = portMemAllocNonPaged(sizeof(nv_kern_mapping_t)); + if (NULL == mapping) + { + os_unmap_kernel_space(*pVirtualAddress, length); + *pVirtualAddress = 0; + return NV_ERR_GENERIC; + } + + mapping->addr = *pVirtualAddress; + mapping->size = length; + mapping->modeFlag = modeFlag; + + mapping->next = nv->kern_mappings; + nv->kern_mappings = mapping; + + return NV_OK; +} + +NV_STATUS osMapPciMemoryKernel64 +( + OBJGPU *pGpu, + RmPhysAddr busAddress, + NvU64 length, + NvU32 Protect, + NvP64 *pVirtualAddress, + NvU32 modeFlag +) +{ + void *tmppVirtualAddress = NvP64_VALUE(pVirtualAddress); + NV_STATUS rc; + + rc = osMapPciMemoryKernelOld(pGpu, + busAddress, + length, + Protect, + &tmppVirtualAddress, + modeFlag); + + *pVirtualAddress = NV_PTR_TO_NvP64(tmppVirtualAddress); + + return rc; +} + +void osUnmapPciMemoryKernelOld +( + OBJGPU *pGpu, + void* virtualAddress +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_kern_mapping_t *mapping, *tmp; + + // this can happen, for example, during a call to RmShutdownAdapter() + // from a failed RmInitAdapter() + if (virtualAddress == NULL) + { + return; + } + + tmp = mapping = nv->kern_mappings; + while (mapping) + { + if (mapping->addr == virtualAddress) + { + if (mapping == nv->kern_mappings) + { + nv->kern_mappings = mapping->next; + } + else + { + tmp->next = mapping->next; + } + + os_unmap_kernel_space(mapping->addr, mapping->size); + + portMemFree(mapping); + return; + } + tmp = mapping; + mapping = mapping->next; + } + + DBG_BREAKPOINT(); +} + +void osUnmapPciMemoryKernel64 +( + OBJGPU *pGpu, + NvP64 virtualAddress +) +{ + osUnmapPciMemoryKernelOld(pGpu, NvP64_VALUE(virtualAddress)); +} + +NV_STATUS osMapGPU( + OBJGPU *pGpu, + RS_PRIV_LEVEL privLevel, + NvU64 offset, + NvU64 length, + NvU32 Protect, + NvP64 *pAddress, + NvP64 *pPriv +) +{ + NV_STATUS rmStatus = NV_OK; + + if (privLevel >= RS_PRIV_LEVEL_KERNEL) + { + if (!portSafeAddU64((NvUPtr)pGpu->deviceMappings[0].gpuNvAddr, offset, (NvU64*)pAddress)) + { + rmStatus = NV_ERR_INVALID_LIMIT; + } + } + else + { + RmPhysAddr busAddress; + if (!portSafeAddU64(pGpu->busInfo.gpuPhysAddr, offset, &busAddress)) + { + rmStatus = NV_ERR_INVALID_LIMIT; + } + else + { + rmStatus = osMapPciMemoryUser(pGpu->pOsGpuInfo, + busAddress, + length, + Protect, + pAddress, + pPriv, + NV_MEMORY_UNCACHED); + } + } + + return rmStatus; +} + +void osUnmapGPU( + OS_GPU_INFO *pOsGpuInfo, + RS_PRIV_LEVEL privLevel, + NvP64 address, + NvU64 length, + NvP64 priv +) +{ + if (privLevel < RS_PRIV_LEVEL_KERNEL) + { + osUnmapPciMemoryUser(pOsGpuInfo, address, length, priv); + } +} + +static NV_STATUS referenceEventForPost( + nv_event_t *event, + NvBool bDoRefCount, + nv_event_t *eventSnapshot, + nv_file_private_t **ppNvfp +) +{ + nv_state_t *nv = nv_get_ctl_state(); + + portSyncSpinlockAcquire(nv->event_spinlock); + + if (event->active == 0) + { + portSyncSpinlockRelease(nv->event_spinlock); + return NV_ERR_INVALID_EVENT; + } + + if (bDoRefCount) + ++event->refcount; + + // Snapshot while event_spinlock still protects the event lifetime. + *eventSnapshot = *event; + *ppNvfp = eventSnapshot->nvfp; + portAtomicIncrementS32(&(*ppNvfp)->event_posting_refcount); + + portSyncSpinlockRelease(nv->event_spinlock); + return NV_OK; +} + +static void dereferenceEventForPost( + nv_event_t *event, + NvBool bDoRefCount, + nv_file_private_t *nvfp +) +{ + if (bDoRefCount) + { + nv_state_t *nv = nv_get_ctl_state(); + + portSyncSpinlockAcquire(nv->event_spinlock); + + NV_ASSERT(event->refcount > 0); + if (--event->refcount == 0 && !event->active) + portMemFree(event); + + portSyncSpinlockRelease(nv->event_spinlock); + } + + portAtomicDecrementS32(&nvfp->event_posting_refcount); +} + +static void postEvent( + nv_event_t *event, + NvU32 hEvent, + NvU32 notifyIndex, + NvU32 info32, + NvU16 info16, + NvBool dataValid, + NvBool bDoRefCount +) +{ + nv_event_t *eventToPost = event; + + nv_file_private_t *nvfp = NULL; + nv_event_t eventSnapshot; + + if (referenceEventForPost(event, bDoRefCount, &eventSnapshot, &nvfp) != NV_OK) + return; + + eventToPost = &eventSnapshot; + + nv_post_event(eventToPost, hEvent, notifyIndex, + info32, info16, dataValid); + + dereferenceEventForPost(bDoRefCount ? event : NULL, bDoRefCount, nvfp); +} + +NvU32 osSetEvent +( + OBJGPU *pGpu, + NvP64 eventID +) +{ + nv_event_t *event = NvP64_VALUE(eventID); + postEvent(event, 0, 0, 0, 0, NV_FALSE, NV_TRUE); + return 1; +} + +NV_STATUS osNotifyEvent( + OBJGPU *pGpu, + PEVENTNOTIFICATION NotifyEvent, + NvU32 Method, + NvU32 Data, + NV_STATUS Status, + NvBool bDoRefCount +) +{ + NV_STATUS rmStatus = NV_OK; + + // notify the event + switch (NotifyEvent->NotifyType) + { + case NV01_EVENT_OS_EVENT: + { + nv_event_t *event = NvP64_VALUE(NotifyEvent->Data); + postEvent(event, + NotifyEvent->hEvent, + NotifyEvent->NotifyIndex, + 0, 0, + NotifyEvent->bEventDataRequired, + bDoRefCount); + break; + } + + // NOTE: NV01_EVENT_KERNEL_CALLBACK is deprecated. please use NV01_EVENT_KERNEL_CALLBACK_EX. + case NV01_EVENT_KERNEL_CALLBACK: + { + MINIPORT_CALLBACK callBackToMiniport = + (MINIPORT_CALLBACK)NvP64_VALUE(NotifyEvent->Data); + + // perform a direct callback to the miniport + if (callBackToMiniport) + callBackToMiniport(NV_GET_NV_STATE(pGpu)); + break; + } + + case NV01_EVENT_KERNEL_CALLBACK_EX: + { + NVOS10_EVENT_KERNEL_CALLBACK_EX *kc = (NVOS10_EVENT_KERNEL_CALLBACK_EX *)NvP64_VALUE(NotifyEvent->Data); + + // passes two arguments (arg, params) to the kernel callback instead of one (arg). + if (kc && kc->func) + { + kc->func(kc->arg, NULL, NotifyEvent->hEvent, Data, Status); + } + break; + } + + + default: + { + rmStatus = NV_ERR_GENERIC; + break; + } + } + + return rmStatus; + +} // end of osNotifyEvent() + +// Allow CPL Events to be callback or events +NV_STATUS osEventNotification +( + OBJGPU *pGpu, + PEVENTNOTIFICATION pNotifyEvent, + NvU32 notifyIndex, + void * pEventData, + NvU32 eventDataSize +) +{ + return osEventNotificationWithInfo(pGpu, pNotifyEvent, notifyIndex, 0, 0, + pEventData, eventDataSize); +} + +NV_STATUS osEventNotificationWithInfo +( + OBJGPU *pGpu, + PEVENTNOTIFICATION pNotifyEvent, + NvU32 notifyIndex, + NvU32 info32, + NvU16 info16, + void * pEventData, + NvU32 eventDataSize +) +{ + NV_STATUS rmStatus = NV_OK; + NvBool bMatchSubdev = NV_FALSE; + + if ((notifyIndex != OS_EVENT_NOTIFICATION_INDEX_ALL) && + (OS_EVENT_NOTIFICATION_INDEX_MATCH_SUBDEV & notifyIndex)) + { + bMatchSubdev = NV_TRUE; + notifyIndex &= ~OS_EVENT_NOTIFICATION_INDEX_MATCH_SUBDEV; + } + + // walk this object's event list and find any matches for this specific notify + for (; pNotifyEvent; pNotifyEvent = pNotifyEvent->Next) + { + // notifyIndex must match if request isn't for all + if ((notifyIndex != OS_EVENT_NOTIFICATION_INDEX_ALL) && + (pNotifyEvent->NotifyIndex != notifyIndex)) + { + continue; + } + + if (bMatchSubdev && (pGpu->subdeviceInstance != pNotifyEvent->subdeviceInst)) + continue; + + switch (pNotifyEvent->NotifyType) + { + case NV_EVENT_BUFFER_BIND: + case NV01_EVENT_WIN32_EVENT: + { + nv_event_t *event = NvP64_VALUE(pNotifyEvent->Data); + postEvent(event, + pNotifyEvent->hEvent, + pNotifyEvent->NotifyIndex, + info32, info16, + pNotifyEvent->bEventDataRequired, + NV_TRUE); + break; + } + + // NOTE: NV01_EVENT_KERNEL_CALLBACK is deprecated. please use NV01_EVENT_KERNEL_CALLBACK_EX. + case NV01_EVENT_KERNEL_CALLBACK: + { + MINIPORT_CALLBACK callBackToMiniport = + (MINIPORT_CALLBACK)NvP64_VALUE(pNotifyEvent->Data); + + // perform a direct callback to the miniport + if (callBackToMiniport) + callBackToMiniport(NV_GET_NV_STATE(pGpu)); + break; + } + + case NV01_EVENT_KERNEL_CALLBACK_EX: + { + NVOS10_EVENT_KERNEL_CALLBACK_EX *kc = (NVOS10_EVENT_KERNEL_CALLBACK_EX *)NvP64_VALUE(pNotifyEvent->Data); + + if (kc && kc->func) + { + kc->func(kc->arg, pEventData, pNotifyEvent->hEvent, 0, NV_OK); + } + break; + } + + default: + break; + } + } + + return rmStatus; +} + +// Allow CPL Events to be callback or events +NV_STATUS osObjectEventNotification +( + NvHandle hClient, + NvHandle hObject, + NvU32 hClass, + PEVENTNOTIFICATION pNotifyEvent, + NvU32 notifyIndex, + void *pEventData, + NvU32 eventDataSize +) +{ + NV_STATUS rmStatus = NV_OK; + + NV_PRINTF(LEVEL_INFO, "%s()\n", __FUNCTION__); + // walk this object's event list and find any matches for this specific notify + for (; pNotifyEvent; pNotifyEvent = pNotifyEvent->Next) + { + // notifyIndex must match if request isn't for all + if ((notifyIndex != OS_EVENT_NOTIFICATION_INDEX_ALL) && + (pNotifyEvent->NotifyIndex != notifyIndex)) + { + continue; + } + + switch (pNotifyEvent->NotifyType) + { + case NV01_EVENT_OS_EVENT: + { + nv_event_t *event = NvP64_VALUE(pNotifyEvent->Data); + postEvent(event, + pNotifyEvent->hEvent, + pNotifyEvent->NotifyIndex, + 0, 0, + pNotifyEvent->bEventDataRequired, + NV_TRUE); + break; + } + + case NV01_EVENT_KERNEL_CALLBACK_EX: + { + NVOS10_EVENT_KERNEL_CALLBACK_EX *kc = (NVOS10_EVENT_KERNEL_CALLBACK_EX *)NvP64_VALUE(pNotifyEvent->Data); + + if (kc && kc->func) + { + kc->func(kc->arg, pEventData, pNotifyEvent->hEvent, 0, NV_OK); + } + break; + } + + default: + break; + } + } + + return rmStatus; +} + +NV_STATUS osReferenceObjectCount(void *pEvent) +{ + nv_state_t *nv = nv_get_ctl_state(); + nv_event_t *event = pEvent; + + portSyncSpinlockAcquire(nv->event_spinlock); + // If event->active is false, don't allow any more reference + if (event->active == 0) + { + portSyncSpinlockRelease(nv->event_spinlock); + return NV_ERR_INVALID_EVENT; + } + ++event->refcount; + portSyncSpinlockRelease(nv->event_spinlock); + return NV_OK; +} + +NV_STATUS osDereferenceObjectCount(void *pOSEvent) +{ + nv_state_t *nv = nv_get_ctl_state(); + nv_event_t *event = pOSEvent; + + portSyncSpinlockAcquire(nv->event_spinlock); + NV_ASSERT(event->refcount > 0); + // If event->refcount == 0 but event->active is true, the client + // has not yet freed the OS event. free_os_event will free its + // memory when they do, or else when the client itself is freed. + if (--event->refcount == 0 && !event->active) + portMemFree(event); + portSyncSpinlockRelease(nv->event_spinlock); + + return NV_OK; +} + +NV_STATUS osUserHandleToKernelPtr(NvHandle hClient, NvP64 hEvent, NvP64 *pEvent) +{ + nv_state_t *nv = nv_get_ctl_state(); + NvU32 fd = (NvU64)hEvent; + NV_STATUS result; + + portSyncSpinlockAcquire(nv->event_spinlock); + nv_event_t *e = nv->event_list; + while (e != NULL) + { + if (e->fd == fd && e->hParent == hClient) + break; + e = e->next; + } + + if (e != NULL) + { + ++e->refcount; + *pEvent = NV_PTR_TO_NvP64(e); + result = NV_OK; + } + else + result = NV_ERR_OBJECT_NOT_FOUND; + portSyncSpinlockRelease(nv->event_spinlock); + + return result; +} + +NV_STATUS osFlushCpuCache(void) +{ + return os_flush_cpu_cache_all(); +} + +void osFlushCpuWriteCombineBuffer(void) +{ + os_flush_cpu_write_combine_buffer(); +} + + +// +// Evict GPU memory range from the CPU caches. +// +// On some platforms (e.g. P9+V100), the CPU can coherently cache GPU memory +// and RM takes advantage of that. Most everything is handled transparently, +// but there are two exceptions that require explicitly flushing any CPU cache +// lines of GPU memory. These are: +// +// 1) Flushing memory backing ACR regions before they get locked. +// +// Otherwise the cache could get flushed while the regions are locked causing a +// region violation physical fault. See more details in +// acrFlushRegionsFromGpuCoherentCpuCache_IMPL(). +// +// 2) Flushing all of FB before GPU reset (NVLink going down) +// +// Leaving cache entries on the CPU causes fatal errors when the CPU tries +// flushing them later while the link is down. See more details in +// nvlinkStatePostUnload_IMPL(). +// +void osFlushGpuCoherentCpuCacheRange +( + OS_GPU_INFO *pOsGpuInfo, + NvU64 cpuVirtual, + NvU64 size +) +{ + nv_flush_coherent_cpu_cache_range(pOsGpuInfo, cpuVirtual, size); +} + +void osErrorLogV(OBJGPU *pGpu, XidContext context, const char * pFormat, va_list arglist) +{ + NV_STATUS rmStatus; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + if ((pFormat == NULL) || (*pFormat == '\0')) + { + return; + } + + rmStatus = nv_log_error(nv, context.xid, pFormat, arglist); + NV_ASSERT(rmStatus == NV_OK); +} + +void osErrorLog(OBJGPU *pGpu, NvU32 num, const char* pFormat, ...) +{ + va_list arglist; + va_start(arglist, pFormat); + osErrorLogV(pGpu, (XidContext){.xid = num}, pFormat, arglist); + va_end(arglist); +} + +NvU32 +osPollHotkeyState +( + OBJGPU *pGpu +) +{ + return 0; +} + +void osDevWriteReg008( + OBJGPU *pGpu, + DEVICE_MAPPING *pMapping, + NvU32 thisAddress, + NvV8 thisValue +) +{ + if (thisAddress >= pMapping->gpuNvLength) + { + NV_ASSERT(thisAddress < pMapping->gpuNvLength); + return; + } + + NV_PRIV_REG_WR08(pMapping->gpuNvAddr, thisAddress, thisValue); +} + +void osDevWriteReg016( + OBJGPU *pGpu, + DEVICE_MAPPING *pMapping, + NvU32 thisAddress, + NvV16 thisValue +) +{ + if (thisAddress >= pMapping->gpuNvLength) + { + NV_ASSERT(thisAddress < pMapping->gpuNvLength); + return; + } + + NV_PRIV_REG_WR16(pMapping->gpuNvAddr, thisAddress, thisValue); +} + +void osDevWriteReg032( + OBJGPU *pGpu, + DEVICE_MAPPING *pMapping, + NvU32 thisAddress, + NvV32 thisValue +) +{ + NvBool vgpuHandled = NV_FALSE; + + vgpuDevWriteReg032(pGpu, thisAddress, thisValue, &vgpuHandled); + if (vgpuHandled) + { + return; + } + + if (thisAddress >= pMapping->gpuNvLength) + { + NV_ASSERT(thisAddress < pMapping->gpuNvLength); + return; + } + + NV_PRIV_REG_WR32(pMapping->gpuNvAddr, thisAddress, thisValue); +} + +NvU8 osDevReadReg008( + OBJGPU *pGpu, + DEVICE_MAPPING *pMapping, + NvU32 thisAddress +) +{ + NvU8 retval = 0; + + if (thisAddress >= pMapping->gpuNvLength) + { + NV_ASSERT(thisAddress < pMapping->gpuNvLength); + } + else + retval = NV_PRIV_REG_RD08(pMapping->gpuNvAddr, thisAddress); + + return retval; +} + +NvU16 osDevReadReg016( + OBJGPU *pGpu, + DEVICE_MAPPING *pMapping, + NvU32 thisAddress +) +{ + NvU16 retval = 0; + + if (thisAddress >= pMapping->gpuNvLength) + { + NV_ASSERT(thisAddress < pMapping->gpuNvLength); + } + else + retval = NV_PRIV_REG_RD16(pMapping->gpuNvAddr, thisAddress); + + return retval; +} + +NvU32 osDevReadReg032( + OBJGPU *pGpu, + DEVICE_MAPPING *pMapping, + NvU32 thisAddress +) +{ + NvU32 retval = 0; + NvBool vgpuHandled = NV_FALSE; + + retval = vgpuDevReadReg032(pGpu, thisAddress, &vgpuHandled); + if (vgpuHandled) + { + return retval; + } + + if (thisAddress >= pMapping->gpuNvLength) + { + NV_ASSERT(thisAddress < pMapping->gpuNvLength); + } + else + retval = NV_PRIV_REG_RD32(pMapping->gpuNvAddr, thisAddress); + + return retval; +} + +NV_STATUS osReadRegistryDwordBase( + OBJGPU *pGpu, + const char *regParmStr, + NvU32 *Data +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + return RmReadRegistryDword(nv, regParmStr, Data); +} + +NV_STATUS osWriteRegistryDword( + OBJGPU *pGpu, + const char *regParmStr, + NvU32 Data +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + return RmWriteRegistryDword(nv, regParmStr, Data); +} + +NV_STATUS osReadRegistryBinary( + OBJGPU *pGpu, + const char *regParmStr, + NvU8 *Data, + NvU32 *cbLen +) +{ +#if defined(DEBUG) || defined(DEVELOP) + NV_ASSERT_OK_OR_RETURN(osValidateRegistryKeyPrefix(regParmStr)); +#endif + + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + return RmReadRegistryBinary(nv, regParmStr, Data, cbLen); +} + +NV_STATUS osWriteRegistryBinary( + OBJGPU *pGpu, + const char *regParmStr, + NvU8 *Data, + NvU32 cbLen +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + return RmWriteRegistryBinary(nv, regParmStr, Data, cbLen); +} + +NV_STATUS osWriteRegistryVolatile( + OBJGPU *pGpu, + const char *regParmStr, + NvU8 *Data, + NvU32 cbLen +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS osReadRegistryVolatile +( + OBJGPU *pGpu, + const char *regParmStr, + NvU8 *Data, + NvU32 cbLen +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS osReadRegistryVolatileSize +( + OBJGPU *pGpu, + const char *regParmStr, + NvU32 *pSize +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS osReadRegistryStringBase( + OBJGPU *pGpu, + const char *regParmStr, + NvU8 *buffer, + NvU32 *pBufferLength +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + return RmReadRegistryString(nv, regParmStr, buffer, pBufferLength); +} + +NV_STATUS osPackageRegistry( + OBJGPU *pGpu, + PACKED_REGISTRY_TABLE *pRegTable, + NvU32 *pSize +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + return RmPackageRegistry(nv, pRegTable, pSize); +} + +NvU32 osGetCpuCount(void) +{ + return os_get_cpu_count(); // Total number of logical CPUs. +} + +NvU32 osGetCurrentProcessorNumber(void) +{ + return os_get_cpu_number(); +} + +ClientGroupID osClientGroupID(NvU64 process, void *pidInfo) +{ + return os_cgroup_for_pid(process, pidInfo); +} + +NvCgroupImpl osCgroupImplementation(void) +{ + switch (os_cgroup_implementation()) + { + case OS_CGROUP_IMPL_DMEM: return CGROUP_IMPL_OS; + case OS_CGROUP_IMPL_MISC: return CGROUP_IMPL_FALLBACK; + default: return CGROUP_IMPL_NONE; + } +} + +void *osCgroupRegisterRegion(OBJGPU *pGpu, NvU64 size) +{ + char name[32]; + nvDbgSnprintf(name, sizeof name, "nvidia/%04x:%02x:%02x/vidmem", + gpuGetDomain(pGpu), + gpuGetBus(pGpu), + gpuGetDevice(pGpu)); + return os_dmem_cgroup_register_region(size, name); +} + +void osCgroupUnregisterRegion(void *region) +{ + os_dmem_cgroup_unregister_region(region); +} + +NV_STATUS osMemacctTryCharge(void *pRegion, NvLength size, void **ppPool) +{ + return os_dmem_cgroup_try_charge(pRegion, size, ppPool, NULL); +} + +void osMemacctReleaseCharge(void *pool, NvLength size) +{ + os_dmem_cgroup_uncharge(pool, size); +} + +void *osCgroupGetFromFd(NvS32 fd) +{ + return os_cgroup_get_from_fd(fd); +} + +void osCgroupPut(void *cgroup) +{ + os_cgroup_put(cgroup); +} + +void osGetTimeoutParams(OBJGPU *pGpu, NvU32 *pTimeoutUs, NvU32 *pScale, NvU32 *pFlags) +{ + NvU32 gpuMode = gpuGetMode(pGpu); + + NV_ASSERT((NV_GPU_MODE_GRAPHICS_MODE == gpuMode) || + (NV_GPU_MODE_COMPUTE_MODE == gpuMode)); + + if (hypervisorIsVgxHyper()) + { + // + // 1.8 seconds is chosen because it is 90% of the overall hard limit of 2.0 + // seconds, imposed by WDDM driver rules. + // Currently primary use case of VGX is Windows, so setting 1.8 as default + // + *pTimeoutUs = 1.8 * 1000000; + } + else + { + switch (gpuMode) + { + default: + case NV_GPU_MODE_GRAPHICS_MODE: + *pTimeoutUs = 4 * 1000000; + break; + + case NV_GPU_MODE_COMPUTE_MODE: + *pTimeoutUs = 30 * 1000000; + break; + } + } + + *pFlags = GPU_TIMEOUT_FLAGS_OSTIMER; + + *pScale = 1; + if (IS_EMULATION(pGpu) || IS_SIMULATION(pGpu)) + { + *pScale = 60; // 1s -> 1m + } + + return; +} + +void osFlushLog(void) +{ + // Not implemented +} + +static NvU32 _osGetTegraPlatform(void) +{ + NV_STATUS status; + NvU32 mode; + + status = os_get_tegra_platform(&mode); + if (status != NV_ERR_NOT_SUPPORTED) + { + return mode; + } + + return NV_OS_TEGRA_PLATFORM_SILICON; +} + +NvU32 osGetSimulationMode(void) +{ + NvU32 mode; + + switch (_osGetTegraPlatform()) + { + case NV_OS_TEGRA_PLATFORM_SIM: + mode = NV_SIM_MODE_CMODEL; + break; + case NV_OS_TEGRA_PLATFORM_FPGA: + mode = NV_SIM_MODE_TEGRA_FPGA; + break; + case NV_OS_TEGRA_PLATFORM_SILICON: + default: + mode = NV_SIM_MODE_HARDWARE; + break; + } + + return mode; +} + +NV_STATUS +cliresCtrlCmdOsUnixFlushUserCache_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS *pAddressSpaceParams +) +{ + Memory *pMemory; + MEMORY_DESCRIPTOR *pMemDesc; + NvU64 start, end; + NvBool bInvalidateOnly; + + NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, + memGetByHandle(RES_GET_CLIENT(pRmCliRes), + pAddressSpaceParams->hObject, + &pMemory)); + + pMemDesc = pMemory->pMemDesc; + + if (memdescGetAddressSpace(pMemDesc) != ADDR_SYSMEM) + { + NV_PRINTF(LEVEL_ERROR, "%s: wrong address space %d\n", + __FUNCTION__, memdescGetAddressSpace(pMemDesc)); + return NV_ERR_INVALID_COMMAND; + } + + if (memdescGetCpuCacheAttrib(pMemDesc) != NV_MEMORY_CACHED) + { + NV_PRINTF(LEVEL_ERROR, "%s: wrong caching type %d\n", + __FUNCTION__, memdescGetCpuCacheAttrib(pMemDesc)); + return NV_ERR_INVALID_COMMAND; + } + + start = pAddressSpaceParams->offset; + end = start + pAddressSpaceParams->length; + + switch(pAddressSpaceParams->cacheOps) + { + case NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH_INVALIDATE: + case NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH: + bInvalidateOnly = NV_FALSE; + break; + + case NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_INVALIDATE: + bInvalidateOnly = NV_TRUE; + break; + + default: + NV_PRINTF(LEVEL_ERROR, "%s: cacheOps not specified\n", __FUNCTION__); + return NV_ERR_INVALID_COMMAND; + } + + if ((end - start) > pMemory->Length) + { + NV_PRINTF(LEVEL_ERROR, + "%s: end address 0x%llx exceeded buffer length: 0x%llx\n", + __FUNCTION__, end, pMemory->Length); + return NV_ERR_INVALID_LIMIT; + } + + if (bInvalidateOnly) + { + // + // XXX: this seems fishy - I'm not sure if invalidating by the kernel + // VA only as nv_dma_cache_invalidate() does here is sufficient for + // this control call. + // pAddressSpaceParams->internalOnly is expected to be the RM client + // VA for this control call; if we wanted to invalidate the user VA we + // could do so using that. + // + // For I/O coherent platforms this won't actually do anything. + // On non-I/O-coherent platforms, there's no need to do a second + // invalidation after the full flush. + // + nv_state_t *nv = NV_GET_NV_STATE(pMemDesc->pGpu); + if (nv->iovaspace_id != NV_IOVA_DOMAIN_NONE) + { + PIOVAMAPPING pIovaMapping = memdescGetIommuMap(pMemDesc, nv->iovaspace_id); + // + // This should only be called for devices that map memory descriptors + // through the nv-dma library, where the memory descriptor data + // contains all the kernel-specific context we need for the + // invalidation. + // + // (These checks match those in osIovaUnmap() leading up to + // nv_dma_unmap_alloc()). + // + if (pIovaMapping == NULL || + pIovaMapping->pOsData == NULL || + memdescGetFlag(pIovaMapping->pPhysMemDesc, MEMDESC_FLAGS_GUEST_ALLOCATED) || + memdescGetFlag(pIovaMapping->pPhysMemDesc, MEMDESC_FLAGS_PEER_IO_MEM)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + nv_dma_cache_invalidate(nv->dma_dev, pIovaMapping->pOsData); + } + else + { + return NV_ERR_INVALID_ARGUMENT; + } + } + else + { + return os_flush_user_cache(); + } + + return NV_OK; +} + +static NV_STATUS +_initializeExportObjectFd +( + nv_file_private_t *nvfp, + NvHandle hClient, + NvHandle hDevice, + NvU16 maxObjects, + NvU8 *metadata +) +{ + NV_STATUS status; + RsResourceRef *pResourceRef; + Device *pDevice; + NvU32 deviceInstance = NV_MAX_DEVICES; + NvU32 gpuInstanceId = NV_U32_MAX; + + if (nvfp->handles != NULL) + { + return NV_ERR_STATE_IN_USE; + } + + if (hDevice != 0) + { + OBJGPU *pGpu; + MIG_INSTANCE_REF ref; + + status = serverutilGetResourceRef(hClient, hDevice, &pResourceRef); + if (status != NV_OK) + { + return status; + } + + pDevice = dynamicCast(pResourceRef->pResource, Device); + if (pDevice == NULL) + { + return NV_ERR_INVALID_PARAMETER; + } + + deviceInstance = pDevice->deviceInst; + pGpu = GPU_RES_GET_GPU(pDevice); + + if (IS_MIG_IN_USE(pGpu)) + { + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + status = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &ref); + if (status == NV_OK) + { + gpuInstanceId = ref.pKernelMIGGpuInstance->swizzId; + } + } + } + + NV_ASSERT_OK_OR_RETURN(os_alloc_mem((void **)&nvfp->handles, + sizeof(nvfp->handles[0]) * maxObjects)); + + os_mem_set(nvfp->handles, 0, + sizeof(nvfp->handles[0]) * maxObjects); + + nvfp->maxHandles = maxObjects; + nvfp->deviceInstance = deviceInstance; + nvfp->gpuInstanceId = gpuInstanceId; + + if (metadata != NULL) + { + os_mem_copy(nvfp->metadata, metadata, sizeof(nvfp->metadata)); + } + + return NV_OK; +} + +NV_STATUS +cliresCtrlCmdOsUnixExportObjectToFd_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS *pParams +) +{ + NvHandle hClient = RES_GET_CLIENT_HANDLE(pRmCliRes); + RmObjExportHandle hExportHandle = 0; + nv_file_private_t *nvfp = NULL; + void *priv = NULL; + NV_STATUS status = NV_OK; + + /* + * This flag is intended to be implemented entirely in the rmapi library in + * userspace, we should never encounter it here. + */ + if (FLD_TEST_DRF(0000_CTRL, _OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS, + _EMPTY_FD, _TRUE, pParams->flags)) + { + return NV_ERR_INVALID_PARAMETER; + } + + if (pParams->object.type != NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM || + pParams->fd == -1) + { + return NV_ERR_INVALID_PARAMETER; + } + + status = RmExportObject(hClient, + pParams->object.data.rmObject.hObject, + &hExportHandle, NULL); + if (status != NV_OK) + { + goto done; + } + NV_ASSERT(hExportHandle != 0); + + nvfp = nv_get_file_private(pParams->fd, NV_TRUE, &priv); + if (nvfp == NULL) + { + NV_ASSERT(priv == NULL); + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + + status = _initializeExportObjectFd(nvfp, hClient, + pParams->object.data.rmObject.hDevice, + 1, NULL); + if (status != NV_OK) + { + goto done; + } + + nvfp->handles[0] = hExportHandle; + +done: + + if (status != NV_OK && hExportHandle != 0) + { + RmFreeObjExportHandle(hExportHandle); + } + + if (priv != NULL) + { + nv_put_file_private(priv); + } + + return status; +} + +// This control call has been deprecated. It will be deleted soon. +NV_STATUS +cliresCtrlCmdOsUnixCreateExportObjectFd_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS *pParams +) +{ + NV_STATUS status; + NvHandle hClient = RES_GET_CLIENT_HANDLE(pRmCliRes); + nv_file_private_t *nvfp = NULL; + void *priv = NULL; + + ct_assert(sizeof(nvfp->metadata) == sizeof(pParams->metadata)); + + if (pParams->maxObjects == 0) + { + return NV_ERR_INVALID_PARAMETER; + } + + nvfp = nv_get_file_private(pParams->fd, NV_TRUE, &priv); + if (nvfp == NULL) + { + NV_ASSERT(priv == NULL); + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + + status = _initializeExportObjectFd(nvfp, hClient, pParams->hDevice, + pParams->maxObjects, pParams->metadata); + +done: + if (priv != NULL) + { + nv_put_file_private(priv); + } + + return status; +} + +NV_STATUS +cliresCtrlCmdOsUnixExportObjectsToFd_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS *pParams +) +{ + NvHandle hClient = RES_GET_CLIENT_HANDLE(pRmCliRes); + RmObjExportHandle *pExportHandle; + nv_file_private_t *nvfp = NULL; + void *priv = NULL; + NV_STATUS status = NV_OK; + NvU32 i; + NvU32 deviceInstance; + NvU32 result; + NvHandle *exportHandles = NULL; + NvBool bFdSetup = NV_FALSE; + + nvfp = nv_get_file_private(pParams->fd, NV_TRUE, &priv); + if (nvfp == NULL) + { + NV_ASSERT(priv == NULL); + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + + ct_assert(sizeof(nvfp->metadata) == sizeof(pParams->metadata)); + + /* Setup export FD if not done */ + if (nvfp->handles == NULL) + { + if (pParams->maxObjects == 0) + { + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + + status = _initializeExportObjectFd(nvfp, hClient, pParams->hDevice, + pParams->maxObjects, + pParams->metadata); + if (status != NV_OK) + { + goto done; + } + + bFdSetup = NV_TRUE; + } + + if ((nvfp->handles == NULL) || + (pParams->numObjects > + NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_MAX_OBJECTS)) + { + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + + if (!portSafeAddU32(pParams->numObjects, pParams->index, &result) || + (result > nvfp->maxHandles)) + { + status = NV_ERR_OUT_OF_RANGE; + goto done; + } + + status = os_alloc_mem((void **)&exportHandles, + sizeof(exportHandles[0]) * + pParams->numObjects); + if (status != NV_OK) + { + goto done; + } + + for (i = 0; i < pParams->numObjects; i++) + { + exportHandles[i] = 0; + + if (pParams->objects[i] == 0) + { + continue; + } + + status = RmExportObject(hClient, + pParams->objects[i], + &exportHandles[i], + &deviceInstance); + if (status != NV_OK) + { + goto done; + } + + NV_ASSERT(exportHandles[i] != 0); + + if (deviceInstance != nvfp->deviceInstance) + { + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + } + + for (i = 0; i < pParams->numObjects; i++) + { + pExportHandle = &nvfp->handles[i + pParams->index]; + + // If the handle already exists in this position, free it + if (*pExportHandle != 0) + { + RmFreeObjExportHandle(*pExportHandle); + *pExportHandle = 0; + } + + *pExportHandle = exportHandles[i]; + } + +done: + + if ((status != NV_OK) && (exportHandles != NULL)) + { + for (i = 0; i < pParams->numObjects; i++) + { + if (exportHandles[i] != 0) + { + RmFreeObjExportHandle(exportHandles[i]); + } + } + } + + if (exportHandles != NULL) + { + os_free_mem(exportHandles); + } + + if ((status != NV_OK) && bFdSetup) + { + os_free_mem(nvfp->handles); + nvfp->handles = NULL; + nvfp->maxHandles = 0; + } + + if (priv != NULL) + { + nv_put_file_private(priv); + } + + return status; +} + +NV_STATUS +cliresCtrlCmdOsUnixImportObjectFromFd_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS *pParams +) +{ + NvHandle hClient = RES_GET_CLIENT_HANDLE(pRmCliRes); + nv_file_private_t *nvfp = NULL; + void *priv = NULL; + NV_STATUS status = NV_OK; + + if (pParams->object.type != NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM || + pParams->fd == -1) + { + return NV_ERR_INVALID_PARAMETER; + } + + nvfp = nv_get_file_private(pParams->fd, NV_TRUE, &priv); + if (nvfp == NULL) + { + NV_ASSERT(priv == NULL); + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + + if ((nvfp->handles == NULL) || (nvfp->handles[0] == 0) || + (nvfp->maxHandles < 1)) + { + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + + status = RmImportObject(hClient, + pParams->object.data.rmObject.hParent, + &pParams->object.data.rmObject.hObject, + nvfp->handles[0], NULL); + +done: + if (priv != NULL) + { + nv_put_file_private(priv); + } + + return status; +} + +NV_STATUS +cliresCtrlCmdOsUnixImportObjectsFromFd_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS *pParams +) +{ + NvHandle hClient = RES_GET_CLIENT_HANDLE(pRmCliRes); + nv_file_private_t *nvfp = NULL; + void *priv = NULL; + NV_STATUS status = NV_OK; + NvU32 i = 0; + RmObjExportHandle hImportHandle; + NvU32 result; + RM_API *pRmApi; + + nvfp = nv_get_file_private(pParams->fd, NV_TRUE, &priv); + if (nvfp == NULL) + { + NV_ASSERT(priv == NULL); + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + + if ((nvfp->handles == NULL) || + (pParams->numObjects > + NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS)) + { + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + + if (!portSafeAddU32(pParams->numObjects, pParams->index, &result) || + (result > nvfp->maxHandles)) + { + status = NV_ERR_OUT_OF_RANGE; + goto done; + } + + for (i = 0; i < pParams->numObjects; i++) + { + hImportHandle = nvfp->handles[i + pParams->index]; + + /* Nothing to import, just continue */ + if (hImportHandle == 0) + { + pParams->objectTypes[i] = \ + NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_NONE; + continue; + } + + status = RmImportObject(hClient, + pParams->hParent, + &pParams->objects[i], + hImportHandle, + &pParams->objectTypes[i]); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "%s: Unable to import handle (%x, %x, %x)\n", + __FUNCTION__, pParams->hParent, pParams->objects[i], hImportHandle); + goto done; + } + } + +done: + + if (status != NV_OK) + { + pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); + while (i > 0) + { + i--; + + if (pParams->objects[i] != 0) + { + pRmApi->Free(pRmApi, hClient, pParams->objects[i]); + } + } + } + + if (priv != NULL) + { + nv_put_file_private(priv); + } + + return status; +} + +NV_STATUS +cliresCtrlCmdOsUnixGetExportObjectInfo_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS *pParams +) +{ + nv_file_private_t *nvfp = NULL; + void *priv = NULL; + NV_STATUS status = NV_OK; + + if (pParams->fd < 0) + { + return NV_ERR_INVALID_PARAMETER; + } + + nvfp = nv_get_file_private(pParams->fd, NV_TRUE, &priv); + if (nvfp == NULL) + { + NV_ASSERT(priv == NULL); + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + + if (nvfp->handles == NULL) + { + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + + pParams->maxObjects = nvfp->maxHandles; + pParams->deviceInstance = nvfp->deviceInstance; + pParams->gpuInstanceId = nvfp->gpuInstanceId; + + os_mem_copy(pParams->metadata, nvfp->metadata, sizeof(nvfp->metadata)); + +done: + if (priv != NULL) + { + nv_put_file_private(priv); + } + + return status; +} + +NV_STATUS +cliresCtrlCmdOsUnixMemacctSetLimits_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_OS_UNIX_MEMACCT_SET_LIMITS_PARAMS *pParams +) +{ + void *cgroup = osCgroupGetFromFd(pParams->cgroupFd); + if (cgroup == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + NV_STATUS status = memacctSetLimits((ClientGroupID)cgroup, pParams->gpuId, pParams->softLimit, pParams->hardLimit); + osCgroupPut(cgroup); + return status; +} + +NV_STATUS +cliresCtrlCmdOsUnixMemacctGetLimits_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_OS_UNIX_MEMACCT_GET_LIMITS_PARAMS *pParams +) +{ + NvU32 gpuMask = 0; + NvU32 gpuIdx = 0; + OBJGPU *pGpu = NULL; + NV_STATUS status = NV_OK; + + pParams->count = 0; + NV_ASSERT_OK_OR_RETURN(gpumgrGetGpuAttachInfo(NULL, &gpuMask)); + + void *cgroup = osCgroupGetFromFd(pParams->cgroupFd); + if (cgroup == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + NvU32 i = 0; + while ((i < NV0000_CTRL_GPU_MAX_ATTACHED_GPUS) && + ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuIdx)) != NULL)) + { + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + memacctGetLimits((ClientGroupID)cgroup, pGpu->gpuId, + &pParams->limits[i].soft, + &pParams->limits[i].hard, + &pParams->limits[i].current), + out); + pParams->limits[i].gpuId = pGpu->gpuId; + i++; + } + pParams->count = i; +out: + osCgroupPut(cgroup); + return status; +} + +/*! + * osAcpiDsm + * + * @brief Handles os specific _DSM method function calls. + * + * Input parameters: + * @param[in] pGpu : OBJGPU pointer + * @param[in] acpiDsmFunction : ACPI DSM function + * @param[in] acpiDsmSubFunction : ACPI DSM subfunction + * @param[in/out] pInOut : in/out buffer, caller should make sure the buffer is large enough. + * @param[in] pSize : when input, size of data that the caller wants to read, in bytes. + * when output, size of valid data in pInOuta in bytes. + */ +NV_STATUS osCallACPI_DSM +( + OBJGPU *pGpu, + ACPI_DSM_FUNCTION acpiDsmFunction, + NvU32 acpiDsmSubFunction, + NvU32 *pInOut, + NvU16 *pSize +) +{ + NV_STATUS status; + NvU8 *pAcpiDsmGuid = NULL; + NvU32 acpiDsmRev; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvU16 acpiDsmInArgSize = 4; + NvBool acpiNvpcfDsmFunction = NV_FALSE; + + // do any handling/remapping of guid needed. + status = checkDsmCall(pGpu, + (ACPI_DSM_FUNCTION *) &acpiDsmFunction, + &acpiDsmSubFunction, + pInOut, + pSize); + + // return if subfunction is not supported or we're returning cache data + if (status != NV_WARN_MORE_PROCESSING_REQUIRED) + { + return status; + } + + switch ((NvU32) acpiDsmFunction) + { + case ACPI_DSM_FUNCTION_NBSI: + pAcpiDsmGuid = (NvU8 *) &NBSI_DSM_GUID; + acpiDsmRev = NBSI_REVISION_ID; + break; + case ACPI_DSM_FUNCTION_NVHG: + pAcpiDsmGuid = (NvU8 *) &NVHG_DSM_GUID; + acpiDsmRev = NVHG_REVISION_ID; + break; + case ACPI_DSM_FUNCTION_MXM: + pAcpiDsmGuid = (NvU8 *) &DSM_MXM_GUID; + acpiDsmRev = ACPI_MXM_REVISION_ID; + break; + case ACPI_DSM_FUNCTION_NBCI: + pAcpiDsmGuid = (NvU8 *) &NBCI_DSM_GUID; + acpiDsmRev = NBCI_REVISION_ID; + break; + case ACPI_DSM_FUNCTION_NVOP: + pAcpiDsmGuid = (NvU8 *) &NVOP_DSM_GUID; + acpiDsmRev = NVOP_REVISION_ID; + break; + case ACPI_DSM_FUNCTION_PCFG: + pAcpiDsmGuid = (NvU8 *) &PCFG_DSM_GUID; + acpiDsmRev = PCFG_REVISION_ID; + break; + case ACPI_DSM_FUNCTION_GPS_2X: + pAcpiDsmGuid = (NvU8 *) &GPS_DSM_GUID; + acpiDsmRev = GPS_2X_REVISION_ID; + acpiDsmInArgSize = (*pSize); + break; + case ACPI_DSM_FUNCTION_GPS: + if (IsTU10X(pGpu)) + { + pAcpiDsmGuid = (NvU8 *) &GPS_DSM_GUID; + acpiDsmRev = GPS_REVISION_ID; + acpiDsmInArgSize = (*pSize); + } + else + { + return NV_ERR_NOT_SUPPORTED; + } + break; + case ACPI_DSM_FUNCTION_PEX: + pAcpiDsmGuid = (NvU8 *) &PEX_DSM_GUID; + acpiDsmRev = PEX_REVISION_ID; + if (acpiDsmSubFunction == PEX_FUNC_SETLTRLATENCY) + { + acpiDsmInArgSize = (3 + *pSize); + } + break; + case (ACPI_DSM_FUNCTION_JT): + pAcpiDsmGuid = (NvU8 *) &JT_DSM_GUID; + acpiDsmRev = JT_REVISION_ID; + break; + case ACPI_DSM_FUNCTION_NVPCF: + { + pAcpiDsmGuid = (NvU8 *)&NVPCF_ACPI_DSM_GUID; + acpiDsmRev = NVPCF_ACPI_DSM_REVISION_ID; + acpiDsmInArgSize = (*pSize); + acpiNvpcfDsmFunction = NV_TRUE; + break; + } + case ACPI_DSM_FUNCTION_NVPCF_2X: + pAcpiDsmGuid = (NvU8 *)&NVPCF_ACPI_DSM_GUID; + acpiDsmRev = NVPCF_2X_ACPI_DSM_REVISION_ID; + acpiDsmInArgSize = (*pSize); + acpiNvpcfDsmFunction = NV_TRUE; + break; + + default: + return NV_ERR_NOT_SUPPORTED; + break; + } + + status = nv_acpi_dsm_method(nv, + pAcpiDsmGuid, + acpiDsmRev, + acpiNvpcfDsmFunction, + acpiDsmSubFunction, + pInOut, + acpiDsmInArgSize, + NULL, + pInOut, + pSize); + + if (status == NV_OK) + { + if (acpiDsmSubFunction == NV_ACPI_ALL_FUNC_SUPPORT) + { + // if handling get supported functions list... cache it for later calls + cacheDsmSupportedFunction(pGpu, acpiDsmFunction, acpiDsmSubFunction, pInOut, *pSize); + } + } + else if (nvp->b_mobile_config_enabled) + { + NV_PRINTF(LEVEL_ERROR, + "osCallACPI_DSM: Error during 0x%x DSM subfunction 0x%x! status=0x%x\n", + acpiDsmFunction, acpiDsmSubFunction, status); + } + + return status; +} + +NV_STATUS osCallACPI_DOD +( + OBJGPU *pGpu, + NvU32 *pOut, + NvU32 *pSize +) +{ + NV_STATUS rmStatus; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + if ((pOut == NULL) || (pSize == NULL)) + { + return NV_ERR_INVALID_POINTER; + } + + rmStatus = nv_acpi_dod_method(nv, pOut, pSize); + + return rmStatus; +} + +// +// osAcpiDdc +// +// Handles os specific _DDC method function calls. _DDC is to get EDID from SBIOS. +// +NV_STATUS osCallACPI_DDC +( + OBJGPU *pGpu, + NvU32 ulAcpiId, + NvU8 *pOutData, + NvU32 *pOutSize, + NvBool bReadMultiBlock +) +{ + NV_STATUS rmStatus; + + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + if ((pOutData == NULL) || (pOutSize == NULL)) + { + return NV_ERR_INVALID_POINTER; + } + + portMemSet(pOutData, 0, *pOutSize); + + rmStatus = nv_acpi_ddc_method(nv, pOutData, pOutSize, bReadMultiBlock); + + return rmStatus; +} + +// osCallACPI_NVHG_ROM +// Making ACPI Call into SBIOS with ROM method to get display device's ROM data. +// +NV_STATUS osCallACPI_NVHG_ROM +( + OBJGPU *pGpu, + NvU32 *pInData, + NvU32 *pOutData +) +{ + NV_STATUS rmStatus; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + if ((pOutData == NULL) || (pInData == NULL)) + { + return NV_ERR_INVALID_POINTER; + } + + if (pInData[1] > ROM_METHOD_MAX_RETURN_BUFFER_SIZE) + { + return NV_ERR_INVALID_ARGUMENT; + } + + rmStatus = nv_acpi_rom_method(nv, pInData, pOutData); + + return rmStatus; +} + +void osInitSystemStaticConfig(SYS_STATIC_CONFIG *pConfig) +{ + pConfig->bIsNotebook = rm_is_system_notebook(); + pConfig->bOsCCEnabled = os_cc_enabled; + pConfig->bOsCCSevSnpEnabled = os_cc_sev_snp_enabled; + pConfig->bOsCCSmeEnabled = os_cc_sme_enabled; + pConfig->bOsCCSnpVtomEnabled = os_cc_snp_vtom_enabled; + pConfig->bOsCCTdxEnabled = os_cc_tdx_enabled; +} + +NvU32 osApiLockAcquireConfigureFlags(NvU32 flags) +{ + return flags; +} + +NV_STATUS osGpuLocksQueueRelease(OBJGPU *pGpu, NvU32 dpcGpuLocksRelease) +{ + return NV_SEMA_RELEASE_FAILED; +} + +void osSyncWithRmDestroy(void) +{ +} + +void osSyncWithGpuDestroy(NvBool bEntry) +{ +} + +void osModifyGpuSwStatePersistence +( + OS_GPU_INFO *pOsGpuInfo, + NvBool bEnable +) +{ + if (!osIsLegacyPersistenceModeSupported(pOsGpuInfo)) + return; + + if (bEnable) + { + pOsGpuInfo->flags |= NV_FLAG_PERSISTENT_SW_STATE; + } + else + { + pOsGpuInfo->flags &= ~NV_FLAG_PERSISTENT_SW_STATE; + } +} + +// +//osCallACPI_MXDS +// +//Handles OS specific MXDS function call. +// +NV_STATUS osCallACPI_MXDS +( + OBJGPU *pGpu, + NvU32 acpiId, + NvU32 *pInOut +) +{ + NV_STATUS rmStatus; + + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + if (pInOut == NULL) + { + return NV_ERR_INVALID_POINTER; + } + + rmStatus = nv_acpi_mux_method(nv, pInOut, acpiId, "MXDS"); + + return rmStatus; +} + +// +//osCallACPI_MXDM +// +//Handles OS specific MXDM function call. +// +NV_STATUS osCallACPI_MXDM +( + OBJGPU *pGpu, + NvU32 acpiId, + NvU32 *pInOut +) +{ + NV_STATUS rmStatus; + + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + if (pInOut == NULL) + { + return NV_ERR_INVALID_POINTER; + } + + rmStatus = nv_acpi_mux_method(nv, pInOut, acpiId, "MXDM"); + + return rmStatus; +} + +#include "lib/protobuf/prb.h" +#include "lib/protobuf/prb_util.h" +#include "g_nvdebug_pb.h" + +NV_STATUS osGetVersionDump(void * pVoid) +{ + PRB_ENCODER * pPrbEnc = (PRB_ENCODER *)pVoid; + NV_STATUS rmStatus; + os_version_info * pOsVersionInfo = NULL; + const char NV_UNKNOWN_BUILD_VERSION[] = "Unknown build version"; + const char NV_UNKNOWN_BUILD_DATE[] = "Unknown build date"; + + NV_ASSERT_OK_OR_RETURN(os_alloc_mem((void**)&pOsVersionInfo, + sizeof(os_version_info))); + portMemSet(pOsVersionInfo, 0, sizeof(os_version_info)); + + prbEncAddUInt32(pPrbEnc, + NVDEBUG_SYSTEMINFO_OSINFO_FAMILY, + NVDEBUG_OS_UNIX); + + rmStatus = os_get_version_info(pOsVersionInfo); + if (rmStatus != NV_OK) + { + goto cleanup; + } + + prbEncAddUInt32(pPrbEnc, + NVDEBUG_SYSTEMINFO_OSINFO_OSMAJORVERSION, + pOsVersionInfo->os_major_version); + + prbEncAddUInt32(pPrbEnc, + NVDEBUG_SYSTEMINFO_OSINFO_OSMINORVERSION, + pOsVersionInfo->os_minor_version); + + prbEncAddUInt32(pPrbEnc, + NVDEBUG_SYSTEMINFO_OSINFO_OSBLDNUM, + pOsVersionInfo->os_build_number); + + if (NULL == pOsVersionInfo->os_build_version_str) + { + pOsVersionInfo->os_build_version_str = NV_UNKNOWN_BUILD_VERSION; + } + + prbEncAddString(pPrbEnc, + NVDEBUG_SYSTEMINFO_OSINFO_BUILDVERSION, + pOsVersionInfo->os_build_version_str); + + if (NULL == pOsVersionInfo->os_build_date_plus_str) + { + pOsVersionInfo->os_build_date_plus_str = NV_UNKNOWN_BUILD_DATE; + } + + prbEncAddString(pPrbEnc, + NVDEBUG_SYSTEMINFO_OSINFO_BUILDDATEPLUS, + pOsVersionInfo->os_build_date_plus_str); + +cleanup: + os_free_mem(pOsVersionInfo); + return rmStatus; +} + +NV_STATUS osTegraiGpuPerfBoost(OBJGPU *pGpu, NvBool enable, NvU32 duration) +{ + return os_tegra_igpu_perf_boost(pGpu->pOsGpuInfo, enable, duration); +} + +NV_STATUS osGetVersion(NvU32 *majorVer, NvU32 *minorVer, NvU32 *buildNum, NvU16 *unusedPatchVersion, NvU16 *unusedProductType) +{ + os_version_info osVersionInfo; + NV_STATUS rmStatus; + + portMemSet(&osVersionInfo, 0, sizeof(osVersionInfo)); + + rmStatus = os_get_version_info(&osVersionInfo); + if (rmStatus == NV_OK) + { + if (majorVer) + *majorVer = osVersionInfo.os_major_version; + if (minorVer) + *minorVer = osVersionInfo.os_minor_version; + if (buildNum) + *buildNum = osVersionInfo.os_build_number; + } + + return rmStatus; +} + +NV_STATUS osGetIsOpenRM(NvBool *bOpenRm) +{ + return os_get_is_openrm(bOpenRm); +} + +NvBool osIsBifResetSupported(OS_GPU_INFO *pOsGpuInfo) +{ + return os_is_bif_reset_supported((void *)pOsGpuInfo); +} + +NV_STATUS +osGetCarveoutInfo +( + NvU64 *pAddr, + NvU64 *pSize +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +osGetVPRInfo +( + NvU64 *pAddr, + NvU64 *pSize +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +osAllocInVPR +( + MEMORY_DESCRIPTOR *pMemDesc +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +osGetGenCarveout +( + NvU64 *pAddr, + NvU64 *pSize, + NvU32 id, + NvU64 align +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +osI2CClosePorts +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 numPorts +) +{ + nv_i2c_unregister_clients(pOsGpuInfo); + return NV_OK; +} + +static NvU32 +i2cSwPortMapping( + nv_state_t *nv, + NvU32 physicalI2CPort +) +{ + NvU32 linuxI2CSwPort = NV_U32_MAX; + + /** + * For T23X, Linux Tegra I2C controller driver uses logical port(controller) number + * where logical port number of I2C1(Gen1) controller is 0, logical port number for + * I2C2(Gen2) controller is 1 and so on. But RM passes I2C physical port(controller) + * number i.e RM passes "1" for I2C1(Gen1), 2 for I2C2(Gen2), etc. So convert + * physical port number to logical port number(linuxI2CSwPort). + * + * For other chips, the above mentioned logic does not apply and we do not need + * conversion as the physical controller number was updated to 0 and RM passes the + * same. + */ + if ((nv->disp_sw_soc_chip_id == NV_CHIP_ID_T234) + || (nv->disp_sw_soc_chip_id == NV_CHIP_ID_T239) + ) + { + linuxI2CSwPort = physicalI2CPort - 1; + } + else + { + linuxI2CSwPort = physicalI2CPort; + } + + return linuxI2CSwPort; +} + +NV_STATUS +osI2CTransfer +( + OBJGPU *pGpu, + NvU32 Port, + NvU8 Address, + nv_i2c_msg_t *nv_i2c_msgs, + NvU32 count +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + if (NV_IS_SOC_DISPLAY_DEVICE(nv)) + { + Port = i2cSwPortMapping(nv, Port); + return nv_i2c_transfer(nv, Port, Address, + nv_i2c_msgs, count); + } + else + { + return NV_ERR_NOT_SUPPORTED; + } +} + +NV_STATUS +osTegraI2CGetBusState +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 port, + NvS32 *scl, + NvS32 *sda +) +{ + if (NV_IS_SOC_DISPLAY_DEVICE(pOsGpuInfo)) + { + port = i2cSwPortMapping(pOsGpuInfo, port); + return nv_i2c_bus_status(pOsGpuInfo, port, scl, sda); + } + else + { + return NV_ERR_NOT_SUPPORTED; + } +} + +NV_STATUS +osReadI2CBufferDirect +( + OBJGPU *pGpu, + NvU32 Port, + NvU8 Address, + void *pOutputBuffer, + NvU32 OutputSize, + void *pInputBuffer, + NvU32 InputSize +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +osWriteI2CBufferDirect +( + OBJGPU *pGpu, + NvU32 Port, + NvU8 Address, + void *pOutputBuffer0, + NvU32 OutputSize0, + void *pOutputBuffer1, + NvU32 OutputSize1 +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +osGC6PowerControl +( + OBJGPU *pGpu, + NvU32 cmd, + NvU32 *pOut +) +{ + NV_STATUS status; + NvU32 inOut = cmd; + NvU16 rtnSize = sizeof(inOut); + + if (FLD_TEST_DRF(_JT_FUNC, _POWERCONTROL, _GPU_POWER_CONTROL, _GSS, inOut)) + { + if (!pOut) + { + return NV_ERR_INVALID_ARGUMENT; + } + } + + status = osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_JT, + JT_FUNC_POWERCONTROL, + &inOut, + &rtnSize); + + if ((status != NV_OK) || !pOut) + { + return status; + } + + *pOut = inOut; + + return NV_OK; +} + +NvBool osTestPcieExtendedConfigAccess(void *handle, NvU32 offset) +{ + OBJGPU *pGpu; + KernelBif *pKernelBif; + NvU32 nvXveId = 0; + NvU32 nvXveVccapHdr = 0; + NvU32 pciStart = 0; + NvU32 pcieStart = 0; + + static NvBool retryAllowed = NV_TRUE; + static NvBool configAccess = NV_FALSE; + + // + // Return early for offset within PCI space + // and does not requires extended config space access + // + if (offset < 0x100) + { + return NV_TRUE; + } + + if (!retryAllowed) + { + return configAccess; + } + + pGpu = gpumgrGetSomeGpu(); + if (pGpu == NULL) + { + return configAccess; + } + + retryAllowed = NV_FALSE; + + pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + if (pKernelBif == NULL || gpuGetBusIntfType_HAL(pGpu) != + NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS) + { + return configAccess; + } + + // Now verify PCI and PCIe config start registers. + kbifGetPcieConfigAccessTestRegisters_HAL(pGpu, pKernelBif, &pciStart, &pcieStart); + os_pci_read_dword(handle, pciStart, &nvXveId); + os_pci_read_dword(handle, pcieStart, &nvXveVccapHdr); + + if (NV_OK == kbifVerifyPcieConfigAccessTestRegisters_HAL(pGpu, + pKernelBif, + nvXveId, + nvXveVccapHdr)) + { + configAccess = NV_TRUE; + } + + return configAccess; +} + +static NvBool skipIovaMappingForTegra +( + PIOVAMAPPING pIovaMapping, + nv_state_t *nv +) +{ + // + // TODO: When ISO SMMU is not present, dma mapping of imported ISO memory + // causes crash during __clean_dcache_area_poc. dma mapping of ISO + // memory allocated by RM (via __get_free_pages) still works. + // Skip dma mapping of imported ISO memory to unblock Tegra Display in + // AV+L. Bug 200765629 + // + + NV_ASSERT(nv != NULL); + + if (NV_IS_SOC_DISPLAY_DEVICE(nv) && + !NV_SOC_IS_ISO_IOMMU_PRESENT(nv) && + !memdescGetFlag(pIovaMapping->pPhysMemDesc, MEMDESC_FLAGS_MEMORY_TYPE_DISPLAY_NISO) && + memdescGetFlag(pIovaMapping->pPhysMemDesc, MEMDESC_FLAGS_EXT_PAGE_ARRAY_MEM)) + { + NV_PRINTF(LEVEL_INFO, "%s: Skip memdescMapIommu mapping\n", __FUNCTION__); + return NV_TRUE; + } + + return NV_FALSE; +} + +static NvBool osMemDescRequiresReadOnlyDeviceDmaMap +( + MEMORY_DESCRIPTOR *pMemDesc +) +{ + // + // MEMDESC_FLAGS_USER_READ_ONLY is also used by RM-owned buffers that the + // kernel writes and user/GSP reads. Restrict RO DMA direction to external + // OS descriptor mappings. + // + return memdescGetFlag(pMemDesc, MEMDESC_FLAGS_EXT_PAGE_ARRAY_MEM) && + !memdescGetFlag(pMemDesc, MEMDESC_FLAGS_KERNEL_MODE) && + (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_USER_READ_ONLY) || + memdescGetFlag(pMemDesc, MEMDESC_FLAGS_DEVICE_READ_ONLY)); +} + +/*! + * @brief Map memory into an IOVA space according to the given mapping info. + * + * @param[in] pIovaMapping IOVA mapping info + * + * @return NV_ERR_NOT_SUPPORTED + */ +NV_STATUS +osIovaMap +( + PIOVAMAPPING pIovaMapping +) +{ + OBJGPU *pGpu; + nv_state_t *nv, *peer; + NV_STATUS status; + RmPhysAddr base; + NvBool bIsBar0; + PMEMORY_DESCRIPTOR pRootMemDesc; + NvBool bIsFbOffset = NV_FALSE; + NvBool bIsIndirectPeerMapping = NV_FALSE; + NvBool bIsContig; + NV_ADDRESS_SPACE addressSpace; + NvU32 osPageCount; + + if (pIovaMapping == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + pGpu = gpumgrGetGpuFromId(pIovaMapping->iovaspaceId); + if (pGpu == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + pRootMemDesc = memdescGetRootMemDesc(pIovaMapping->pPhysMemDesc, NULL); + addressSpace = memdescGetAddressSpace(pIovaMapping->pPhysMemDesc); + if (gpumgrCheckIndirectPeer(pGpu, pRootMemDesc->pGpu) && + (addressSpace == ADDR_FBMEM)) + { + bIsIndirectPeerMapping = NV_TRUE; + } + + if ((addressSpace != ADDR_SYSMEM) && !bIsIndirectPeerMapping) + { + NV_PRINTF(LEVEL_INFO, + "%s passed memory descriptor in an unsupported address space (%s)\n", + __FUNCTION__, + memdescGetApertureString(memdescGetAddressSpace(pIovaMapping->pPhysMemDesc))); + return NV_ERR_NOT_SUPPORTED; + } + + // + // For guest-allocated memory, we don't actually want to do any remapping, + // since the physical address is already the DMA address to be used by the + // GPU. + // + // For carveout memory, we setup identity mapping, so physical + // address is same as the DMA address. + // + // + if (memdescIsCarveoutMemory(pIovaMapping->pPhysMemDesc) || + memdescGetFlag(pIovaMapping->pPhysMemDesc, MEMDESC_FLAGS_GUEST_ALLOCATED)) + { + return NV_OK; + } + + nv = NV_GET_NV_STATE(pGpu); + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pIovaMapping->pPhysMemDesc)) + { + osPageCount = pIovaMapping->pPhysMemDesc->PageCount; + NV_ASSERT_OR_RETURN(os_page_size == pIovaMapping->pPhysMemDesc->pageArrayGranularity, NV_ERR_INVALID_PARAMETER); + } + else + { + osPageCount = NV_RM_PAGES_TO_OS_PAGES(pIovaMapping->pPhysMemDesc->PageCount); + } + + // + // Intercept peer IO type memory. These are contiguous allocations, so no + // need to adjust pages. + // + if (memdescGetFlag(pIovaMapping->pPhysMemDesc, MEMDESC_FLAGS_PEER_IO_MEM)) + { + NV_ASSERT(memdescGetContiguity(pIovaMapping->pPhysMemDesc, AT_CPU)); + + status = nv_dma_map_mmio(nv->dma_dev, + osPageCount, + &pIovaMapping->iovaArray[0]); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s: failed to map peer IO mem (status = 0x%x)\n", + __FUNCTION__, status); + } + + return status; + } + + // + // We need to check against the "root" GPU, e.g., the GPU that owns this + // allocation. If we're trying to map one of its BARs for a peer, we need + // to handle it differently because it wouldn't have gone through our system + // memory page allocation paths, obviously, and wouldn't have alloc private + // data associated with it. + // + peer = NV_GET_NV_STATE(pRootMemDesc->pGpu); + bIsContig = memdescGetContiguity(pIovaMapping->pPhysMemDesc, AT_CPU); + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pIovaMapping->pPhysMemDesc)) + { + NV_ASSERT_OR_RETURN(pIovaMapping->pPhysMemDesc->pageArrayGranularity == os_page_size, NV_ERR_INVALID_ARGUMENT); + } + else if (NV_RM_PAGE_SIZE < os_page_size && !bIsContig) + { + RmDeflateRmToOsPageArray(&pIovaMapping->iovaArray[0], + pIovaMapping->pPhysMemDesc->PageCount); + } + + base = memdescGetPhysAddr(pIovaMapping->pPhysMemDesc, AT_CPU, 0); + bIsBar0 = IS_REG_OFFSET(peer, base, pIovaMapping->pPhysMemDesc->Size); + + bIsFbOffset = IS_FB_OFFSET(peer, base, pIovaMapping->pPhysMemDesc->Size); + + void *pPriv = memdescGetMemData(pIovaMapping->pPhysMemDesc); + + if (!bIsBar0 && !bIsFbOffset) + { + if (pPriv == NULL) + { + return NV_ERR_INVALID_STATE; + } + } + else if(bIsIndirectPeerMapping) + { + NV_ASSERT(!bIsBar0 && bIsFbOffset); + // + // TODO: Align onlined GPU memory allocation paths with system memory allocation + // That way pMemDesc->pMemData is setup correctly when we try to create mapping + // to onlined memory of indirect peer. After that we can also get rid of some + // extra code in nv_dma_map_alloc. See bug 190324 for details + // + + status = memdescGetNvLinkGpa(pRootMemDesc->pGpu, (bIsContig ? 1 : osPageCount), + &pIovaMapping->iovaArray[0]); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "%s Failed to get SPA\n", __FUNCTION__); + return status; + } + } + + if (skipIovaMappingForTegra(pIovaMapping, nv)) + { + return NV_OK; + } + + if (!bIsBar0 && (!bIsFbOffset || bIsIndirectPeerMapping)) + { + NvBool bReadOnlyDeviceMap = + osMemDescRequiresReadOnlyDeviceDmaMap(pIovaMapping->pPhysMemDesc); + + status = nv_dma_map_alloc( + osGetDmaDeviceForMemDesc(nv, pIovaMapping->pPhysMemDesc), + osPageCount, + &pIovaMapping->iovaArray[0], + bIsContig, bReadOnlyDeviceMap, &pPriv); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s: failed to map allocation (status = 0x%x)\n", + __FUNCTION__, status); + return status; + } + + pIovaMapping->pOsData = pPriv; + } + else if (peer != nv) + { + status = nv_dma_map_peer(nv->dma_dev, peer->dma_dev, bIsBar0 ? 0 : 1, + osPageCount, &pIovaMapping->iovaArray[0]); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_INFO, + "%s: failed to map peer (base = 0x%llx, status = 0x%x)\n", + __FUNCTION__, base, status); + return status; + } + + // + // pOsData must be NULL to distinguish a peer DMA mapping from a + // system memory mapping in osIovaUnmap(), so make sure to set it + // accordingly here. + // + pIovaMapping->pOsData = NULL; + } + else + { + NV_PRINTF(LEVEL_INFO, "cannot map a GPU's BAR to itself\n"); + return NV_ERR_NOT_SUPPORTED; + } + + // + // If the OS layer doesn't think in RM page size, we need to inflate the + // PTE array into RM pages. + // + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pIovaMapping->pPhysMemDesc)) + { + NV_ASSERT_OR_RETURN(pIovaMapping->pPhysMemDesc->pageArrayGranularity == os_page_size, NV_ERR_INVALID_ARGUMENT); + } + else if (NV_RM_PAGE_SIZE < os_page_size && !bIsContig) + { + RmInflateOsToRmPageArray(&pIovaMapping->iovaArray[0], + pIovaMapping->pPhysMemDesc->PageCount); + } + + return NV_OK; +} + +/*! + * @brief Unmap memory from an IOVA space according to the given mapping info. + * + * This mapping info must have been previously mapped by osIovaMap(). + * + * @param[in] pIovaMapping IOVA mapping info + * + */ +void +osIovaUnmap +( + PIOVAMAPPING pIovaMapping +) +{ + OBJGPU *pGpu; + nv_state_t *nv; + void *pPriv; + NV_STATUS status; + NvU64 osPageCount; + + if (pIovaMapping == NULL) + { + return; + } + + pGpu = gpumgrGetGpuFromId(pIovaMapping->iovaspaceId); + if (pGpu == NULL) + { + return; + } + + // + // For guest-allocated or carveout memory, we never actually remapped the + // memory, so we shouldn't try to unmap it here. + // + if (memdescIsCarveoutMemory(pIovaMapping->pPhysMemDesc) || + memdescGetFlag(pIovaMapping->pPhysMemDesc, MEMDESC_FLAGS_GUEST_ALLOCATED)) + { + return; + } + + nv = NV_GET_NV_STATE(pGpu); + + if (skipIovaMappingForTegra(pIovaMapping, nv)) + { + return; + } + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pIovaMapping->pPhysMemDesc)) + { + osPageCount = pIovaMapping->pPhysMemDesc->PageCount; + NV_ASSERT(os_page_size == pIovaMapping->pPhysMemDesc->pageArrayGranularity); + } + else + { + osPageCount = NV_RM_PAGES_TO_OS_PAGES(pIovaMapping->pPhysMemDesc->PageCount); + } + + if (memdescGetFlag(pIovaMapping->pPhysMemDesc, MEMDESC_FLAGS_PEER_IO_MEM)) + { + nv_dma_unmap_mmio(nv->dma_dev, + osPageCount, + pIovaMapping->iovaArray[0]); + + return; + } + + // + // TODO: Formalize the interface with the OS layers so we can use a common + // definition of OS_IOVA_MAPPING_DATA. + // + pPriv = (void *)pIovaMapping->pOsData; + + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pIovaMapping->pPhysMemDesc)) + { + NV_ASSERT(pIovaMapping->pPhysMemDesc->pageArrayGranularity == os_page_size); + } + else if (NV_RM_PAGE_SIZE < os_page_size && + !memdescGetContiguity(pIovaMapping->pPhysMemDesc, AT_CPU)) + { + RmDeflateRmToOsPageArray(&pIovaMapping->iovaArray[0], + pIovaMapping->pPhysMemDesc->PageCount); + } + + if (pPriv != NULL) + { + status = nv_dma_unmap_alloc(nv->dma_dev, + osPageCount, + &pIovaMapping->iovaArray[0], &pPriv); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s: failed to unmap allocation (status = 0x%x)\n", + __FUNCTION__, status); + } + } + else + { + nv_dma_unmap_peer(nv->dma_dev, + osPageCount, + pIovaMapping->iovaArray[0]); + } + + // + // If the OS layer doesn't think in RM page size, we need to fluff out the + // PTE array into RM pages. + // + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pIovaMapping->pPhysMemDesc)) + { + NV_ASSERT(pIovaMapping->pPhysMemDesc->pageArrayGranularity == os_page_size); + } + else if (NV_RM_PAGE_SIZE < os_page_size && + !memdescGetContiguity(pIovaMapping->pPhysMemDesc, AT_CPU)) + { + RmInflateOsToRmPageArray(&pIovaMapping->iovaArray[0], + pIovaMapping->pPhysMemDesc->PageCount); + } + + pIovaMapping->pOsData = NULL; +} + +/*! + * @brief Set the GPU Rail Voltage in Tegra SoC. Currently not supported + * + * @param[in] pGpu GPU object pointer + * @param[in] reqVoltageuV Rail Voltage requested in uV + * @param[out] pSetVoltageuV Rail Voltage set in uV + * + * @return NV_ERR_NOT_SUPPORTED + */ +NV_STATUS +osSetGpuRailVoltage +( + OBJGPU *pGpu, + NvU32 reqVoltageuV, + NvU32 *pSetVoltageuV +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +/*! + * @brief Get the GPU Rail Voltage in Tegra SoC. Currently not supported + * + * @param[in] pGpu GPU object pointer + * @param[out] voltageuV Rail Voltage in uV + * + * @return NV_ERR_NOT_SUPPORTED + */ +NV_STATUS +osGetGpuRailVoltage +( + OBJGPU *pGpu, + NvU32 *pVoltageuV +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +/*! + * @brief Bring down system in a controlled manner on known error conditions. + * + * @bugCode[in] Error code / reason. + */ +void osBugCheck(NvU32 bugCode) +{ + if (bugCode > OS_BUG_CHECK_BUGCODE_LAST) + { + bugCode = OS_BUG_CHECK_BUGCODE_UNKNOWN; + } + + os_bug_check(bugCode, ppOsBugCheckBugcodeStr[bugCode]); +} + +/*! + * @brief Perform an action at assertion failure. + */ +void osAssertFailed(void) +{ + os_dump_stack(); +} + +/*! + * @brief Get the GPU Chip Info - Speedo and IDDQ values + * + * + * @param[in] pGpu GPU object pointer + * @param[out] pGpuSpeedoHv Pointer to GPU Speedo value at high voltage corner. + * @param[out] pGpuSpeedoLv Pointer to GPU Speedo value at low voltage corner. + * @param[out] pGpuIddq Pointer to GPU Iddq Value + * @param[out] pChipSkuId SKU ID for the chip + * + * @return NV_ERR_NOT_SUPPORTED + */ +NV_STATUS +osGetChipInfo +( + OBJGPU *pGpu, + NvU32 *pGpuSpeedoHv, + NvU32 *pGpuSpeedoLv, + NvU32 *pGpuIddq, + NvU32 *pChipSkuId +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +/* + * @brief Get the GPU Rail Voltage Info (i.e. Min, Max and StepSize) in Tegra SoC. + * + * @param[in] pGpu GPU object pointer + * @param[out] pMinVoltageuV Minimum Voltage supported on the Rail in Micro Volts + * @param[out] pMaxVoltageuV Maximum Voltage supported on the Rail in Micro Volts + * @param[out] pStepVoltageuV Voltage Step-size supported on the Rail in Micro Volts + * + * @return NV_ERR_NOT_SUPPORTED + */ +NV_STATUS +osGetGpuRailVoltageInfo +( + OBJGPU *pGpu, + NvU32 *pMinVoltageuV, + NvU32 *pMaxVoltageuV, + NvU32 *pStepVoltageuV +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +/*! + * @brief Get the current opaque security token. + * + * For Linux the security token is the effective UID of a process and process ID + * + * Note: This function allocates memory for the token. The onus is on the calling + * function to free the memory associated with the token once its done with it. + * + * @return pointer to the security token. + */ +PSECURITY_TOKEN +osGetSecurityToken(void) +{ + NV_STATUS rmStatus; + TOKEN_USER *pTokenUser; + + pTokenUser = portMemAllocNonPaged(sizeof(TOKEN_USER)); + if (pTokenUser == NULL) + { + return NULL; + } + rmStatus = os_get_euid(&pTokenUser->euid); + if (rmStatus != NV_OK) + { + portMemFree(pTokenUser); + return NULL; + } + + pTokenUser->pid = os_get_current_process(); + + return (PSECURITY_TOKEN)pTokenUser; +} + +PUID_TOKEN +osGetCurrentUidToken(void) +{ + NV_STATUS rmStatus; + NvU32 *pUidToken; + + pUidToken = portMemAllocNonPaged(sizeof(NvU32)); + if (pUidToken == NULL) + { + return NULL; + } + + rmStatus = os_get_euid(pUidToken); + if (rmStatus != NV_OK) + { + portMemFree(pUidToken); + return NULL; + } + + return (PUID_TOKEN)pUidToken; +} + +/*! + * @brief Interface function to validate the token for the current client + * + * This function takes two tokens as parameters, validates them and checks + * if either the PID or EUID from client database matches the current PID or EUID. + * + * @param[in] pClientSecurityToken security token cached in the client db + * @param[in] pCurrentSecurityToken security token of the current client + * @return NV_OK if the validation is successful + * NV_ERR_INVALID_CLIENT if the tokens do not match + * NV_ERR_INVALID_POINTER if the tokens are invalid + */ +NV_STATUS +osValidateClientTokens +( + PSECURITY_TOKEN pClientSecurityToken, + PSECURITY_TOKEN pCurrentSecurityToken +) +{ + PTOKEN_USER pClientTokenUser = (PTOKEN_USER)pClientSecurityToken; + PTOKEN_USER pCurrentTokenUser = (PTOKEN_USER)pCurrentSecurityToken; + + if (pClientTokenUser == NULL || pCurrentTokenUser == NULL) + return NV_ERR_INVALID_POINTER; + + if ((pClientTokenUser->euid != pCurrentTokenUser->euid) && + (pClientTokenUser->pid != pCurrentTokenUser->pid)) + { + NV_PRINTF(LEVEL_INFO, + "NVRM: %s: Current security token doesn't match the one in the client database. " + "Current EUID: %d, PID: %d; Client DB EUID: %d, PID: %d\n", + __FUNCTION__, pCurrentTokenUser->euid, pCurrentTokenUser->pid, + pClientTokenUser->euid, pClientTokenUser->pid); + return NV_ERR_INVALID_CLIENT; + } + + return NV_OK; +} + +/*! + * @brief Interface function to compare the tokens for two client + * + * This function takes two tokens as parameters, validates them and checks + * if the EUIDs of each token match. + * + * @param[in] pToken1 Token to compare + * @param[in] pToken2 Token to compare + * @return NV_TRUE if the tokens match + * NV_FALSE if the tokens do not match + */ +NvBool +osUidTokensEqual +( + PUID_TOKEN pUidToken1, + PUID_TOKEN pUidToken2 +) +{ + NvU32 * pTokenUser1 = (NvU32*)pUidToken1; + NvU32 * pTokenUser2 = (NvU32*)pUidToken2; + + NV_ASSERT_OR_RETURN((pTokenUser1 != NULL), NV_FALSE); + NV_ASSERT_OR_RETURN((pTokenUser2 != NULL), NV_FALSE); + + if (*pTokenUser1 != *pTokenUser2) + { + return NV_FALSE; + } + + return NV_TRUE; +} + +NvBool +osRemoveGpuSupported +( + void +) +{ + return os_pci_remove_supported(); +} + +/* + * @brief Get the address ranges assigned to local or peer GPUs on a system that + * supports hardware address translation services (ATS) over NVLink/C2C. + * + * @note + * - All address values are in the System Physical Address (SPA) space + * - Targets can either be "Local" (bIsPeer=False) or for a specified "Peer" + * (bIsPeer=True, peerIndex=#) GPU + * - Target address and mask values have a specified bit width, and represent + * the higher order bits above the target address granularity + * + * @param[in] pGpu GPU object pointer + * @param[out] pAddrSysPhys Pointer to hold SPA + * @param[out] pAddrWidth Address range width value pointer + * @param[out] pMask Mask value pointer + * @param[out] pMaskWidth Mask width value pointer + * @param[in] bIsPeer NV_TRUE if this is a peer, local GPU otherwise + * @param[in] peerIndex Peer index + * + * @return NV_OK or NV_ERR_NOT_SUPPORTED + * + * A return value of NV_ERR_NOT_SUPPORTED for the local GPU would + * indicate that the system does not support ATS over NVLink/C2C + */ +NV_STATUS +osGetAtsTargetAddressRange +( + OBJGPU *pGpu, + NvU64 *pAddrSysPhys, + NvU32 *pAddrWidth, + NvU32 *pMask, + NvU32 *pMaskWidth, + NvBool bIsPeer, + NvU32 peerIndex +) +{ +#if RMCFG_MODULE_KERNEL_BIF && RMCFG_MODULE_KERNEL_NVLINK && defined(NVCPU_AARCH64) + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + nv_state_t *nv; + const int addrMaskWidth = 0x10; + + if (!pKernelNvlink && !pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_IS_C2C_LINK_UP)) + return NV_ERR_INVALID_ARGUMENT; + + nv = NV_GET_NV_STATE(pGpu); + + // + // TODO : Bug 1848958 restricts peer device tree parsing. Return early if + // peer values are requested. This should be fixed by passing correct pGpu + // pointer of the peer GPU retrieved using peerIds. + // + if (bIsPeer) + { + const int addrWidth = 0x10; + + *pAddrSysPhys = 0; + *pAddrWidth = addrWidth; + *pMask = 0; + *pMaskWidth = addrMaskWidth; + return NV_OK; + } + else + { + NV_STATUS status = nv_get_device_memory_config(nv, pAddrSysPhys, NULL, NULL, NULL, + pAddrWidth, NULL); + if (status == NV_OK) + { + *pMask = NVBIT(*pAddrWidth) - 1U; + *pMaskWidth = addrMaskWidth; + } + return status; + } + + return NV_OK; +#endif + return NV_ERR_NOT_SUPPORTED; +} + +/* + * @brief Get the physical address in CPU address map and NUMA node id + * of the GPU memory. + * + * @note + * - The physical address is System Physical Address (SPA) in baremetal/host + * and Intermediate Physical Address(IPA) or Guest Physical Address(GPA) + * inside a VM. + * + * @param[in] pGpu GPU object pointer + * @param[out] pAddrPhys Pointer to hold the physical address of FB in + * CPU address map + * @param[out] pSizePhys Pointer to hold the size of FB mapped to CPU + * @param[out] pNodeId NUMA nodeID of respective GPU memory + * + * @return NV_OK or NV_ERR_NOT_SUPPORTED + * + */ +NV_STATUS +osGetFbNumaInfo +( + OBJGPU *pGpu, + NvU64 *pAddrPhys, + NvU64 *pSizePhys, + NvU64 *pAddrRsvdPhys, + NvS32 *pNodeId +) +{ +#if RMCFG_MODULE_KERNEL_BIF && RMCFG_MODULE_KERNEL_NVLINK && defined(NVCPU_AARCH64) + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + nv_state_t *nv; + + *pNodeId = NV0000_CTRL_NO_NUMA_NODE; + + if (!pKernelNvlink && !pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_IS_C2C_LINK_UP)) + return NV_ERR_INVALID_ARGUMENT; + + nv = NV_GET_NV_STATE(pGpu); + + NV_STATUS status = nv_get_device_memory_config(nv, NULL, pAddrPhys, pSizePhys, + pAddrRsvdPhys, NULL, pNodeId); + + return status; +#endif + return NV_ERR_NOT_SUPPORTED; +} + + +/* + * @brief Verif only function to get the chiplib overrides for link connection + * state for all C2C links. + * + * If chiplib overrides exist, each link can either be enabled (1) or disabled (0) + * + * @param[in] pGpu GPU object pointer + * @param[in] maxLinks Size of pLinkConnection array + * @param[out] pLinkConnection array of pLinkConnection values to be populated by MODS + * + * @return NV_OK or NV_ERR_NOT_SUPPORTED (no overrides available) + */ +NV_STATUS +osGetForcedC2CConnection +( + OBJGPU *pGpu, + NvU32 maxLinks, + NvU32 *pLinkConnection +) +{ + int i, ret; + NV_STATUS status; + char path[64]; + + NV_ASSERT_OR_RETURN((pLinkConnection != NULL), NV_ERR_INVALID_POINTER); + NV_ASSERT_OR_RETURN((maxLinks > 0), NV_ERR_NOT_SUPPORTED); + NV_ASSERT_OR_RETURN((pGpu != NULL), NV_ERR_INVALID_ARGUMENT); + + for (i = 0; i < maxLinks; i++) + { + ret = os_snprintf(path, sizeof(path), "CPU_MODEL|CM_ATS_ADDRESS|C2C%u", i); + NV_ASSERT((ret > 0) && (ret < (sizeof(path) - 1))); + + status = gpuSimEscapeRead(pGpu, path, 0, 4, &pLinkConnection[i]); + if (status == NV_OK) + { + NV_PRINTF(LEVEL_INFO, "%s: %s=0x%X\n", __FUNCTION__, + path, pLinkConnection[i]); + } + else + { + NV_PRINTF(LEVEL_INFO, "%s: gpuSimEscapeRead for '%s' failed (%u)\n", + __FUNCTION__, path, status); + return NV_ERR_NOT_SUPPORTED; + } + } + return NV_OK; +} + +static NV_STATUS +osGetSmbiosTableInfo +( + const NvU8 *pMappedAddr, + NvU64 *pBaseAddr, + NvU64 *pLength, + NvU64 *pNumSubTypes, + NvU32 *pVersion +) +{ + *pBaseAddr = 0; + *pLength = 0; + *pNumSubTypes = 0; + *pVersion = 0; + + if (portMemCmp(pMappedAddr, "_SM3_", 5) == 0) + { + *pVersion = (pMappedAddr[7] << 8) | pMappedAddr[8]; + portMemCopy(pLength, 4, pMappedAddr + 12, 4); + portMemCopy(pBaseAddr, 8, pMappedAddr + 16, 8); + + *pNumSubTypes = *pLength / 4; + + return NV_OK; + } + + if (portMemCmp(pMappedAddr, "_SM_", 4) == 0) + { + *pVersion = (pMappedAddr[6] << 8) | pMappedAddr[7]; + + pMappedAddr += 16; + + if (portMemCmp(pMappedAddr, "_DMI_", 5) == 0) + { + portMemCopy(pLength, 2, pMappedAddr + 6, 2); + portMemCopy(pBaseAddr, 4, pMappedAddr + 8, 4); + portMemCopy(pNumSubTypes, 2, pMappedAddr + 12, 2); + + if (!*pVersion) + *pVersion = (pMappedAddr[14] & 0xF0) << 4 | + (pMappedAddr[14] & 0x0F); + + return NV_OK; + } + } + + return NV_ERR_INVALID_ADDRESS; +} + + +/* + * @brief Function to export SMBIOS table. Also, maps table in kernel-space. + * + * @param[out] ppBaseVAddr Base virtual address of SMBIOS table. + * @param[out] pLength Size of SMBIOS table. + * @param[out] pNumSubTypes Count of structures (types) embedded in + * the SMBIOS table. + * @param[out] pVersion SMBIOS version + * + * @return NV_OK, NV_ERR_INSUFFICIENT_RESOURCES or NV_ERR_INVALID_ADDRESS + * or errors from OS layer + */ +NV_STATUS +osGetSmbiosTable +( + void **ppBaseVAddr, + NvU64 *pLength, + NvU64 *pNumSubTypes, + NvU32 *pVersion +) +{ + NV_STATUS status = NV_OK; + NvU64 physSmbiosAddr = ~0ull; + void *pMappedAddr = NULL; + NvU64 basePAddr = 0; + + if (!NVCPU_IS_X86_64 && !NVCPU_IS_AARCH64) + { + return NV_ERR_NOT_SUPPORTED; + } + + status = os_get_smbios_header(&physSmbiosAddr); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_INFO, "%s: Failed query SMBIOS table with error: %x \n", + __FUNCTION__, status); + return status; + } + + NV_ASSERT(physSmbiosAddr != ~0ull); + + pMappedAddr = osMapKernelSpace(physSmbiosAddr, + os_page_size, + NV_MEMORY_CACHED, + NV_PROTECT_READ_WRITE); + if (!pMappedAddr) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + status = osGetSmbiosTableInfo(pMappedAddr, + &basePAddr, + pLength, + pNumSubTypes, + pVersion); + + osUnmapKernelSpace(pMappedAddr, os_page_size); + + if (status != NV_OK) + { + return status; + } + + *ppBaseVAddr = osMapKernelSpace(basePAddr, + *pLength, + NV_MEMORY_CACHED, + NV_PROTECT_READ_WRITE); + if (!*ppBaseVAddr) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + return NV_OK; +} + +/* + * @brief Function to free SMBIOS table mappings + * + * @param[in] pBaseVAddr Base virtual address of SMBIOS table. + * @param[in] length Size of SMBIOS table. + * + */ +void +osPutSmbiosTable +( + void *pBaseVAddr, + NvU64 length +) +{ + osUnmapKernelSpace(pBaseVAddr, length); +} + +NV_STATUS +osGetAcpiRsdpFromUefi +( + NvU32 *pRsdpAddr +) +{ + return os_get_acpi_rsdp_from_uefi(pRsdpAddr); +} + +/* + * @brief Returns NV_TRUE if NvSwitch device is present in the system. + */ +NvBool +osIsNvswitchPresent +( + void +) +{ + return os_is_nvswitch_present(); +} + +/* + * @brief Function to add crashlog buffer entry. + * + * @param[in] pBuffer virt_addr of nvlog buffer + * @param[in] length size of nvlog buffer + */ +void +osAddRecordForCrashLog +( + void *pBuffer, + NvU32 length +) +{ + os_add_record_for_crashLog(pBuffer, length); +} + +/* + * @brief Function to delete crashlog buffer entry. + * + * @param[in] pBuffer virt_addr of nvlog buffer + */ +void +osDeleteRecordForCrashLog +( + void *pBuffer +) +{ + os_delete_record_for_crashLog(pBuffer); +} + +/* + * @brief Queries the sysfs interface to get memblock size + * @param[out] memblock_size Pointer to the memblock_size + */ +NV_STATUS +osNumaMemblockSize +( + NvU64 *memblock_size +) +{ + return os_numa_memblock_size(memblock_size); +} + +NvBool +osNumaOnliningEnabled +( + OS_GPU_INFO *pOsGpuInfo +) +{ + NvS32 numaNodeId = NV0000_CTRL_NO_NUMA_NODE; + + // + // Note that this numaNodeId value fetched from Linux layer might not be + // accurate since it is possible to overwrite it with regkey on some configs + // + if (nv_get_device_memory_config(pOsGpuInfo, NULL, NULL, NULL, NULL, NULL, + &numaNodeId) != NV_OK) + { + return NV_FALSE; + } + + return (numaNodeId != NV0000_CTRL_NO_NUMA_NODE); +} + +/* + * @brief Function to call NUMA allocation entry. + * + * @param[in] nid NUMA node id + * @param[in] size Allocation size + * @param[in] flag Allocation flags + * @param[out] pAddress Ptr to the allocated physical address + */ +NV_STATUS +osAllocPagesNode +( + NvS32 nid, + NvLength size, + NvU32 flag, + NvU64 *pAddress +) +{ + NV_STATUS status = NV_OK; + NvU32 localFlag = NV_ALLOC_PAGES_NODE_NONE; + + if (pAddress == NULL || nid < 0 || size > NV_U32_MAX) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // Translate the flags + if (flag & OS_ALLOC_PAGES_NODE_SKIP_RECLAIM) + { + localFlag |= NV_ALLOC_PAGES_NODE_SKIP_RECLAIM; + } + + status = os_alloc_pages_node(nid, (NvU32)size, localFlag, pAddress); + return status; +} + +void +osAllocAcquirePage +( + NvU64 pAddress, + NvU32 pageCount +) +{ + NvU32 i; + + for (i = 0; i < pageCount; i++) + { + os_get_page(pAddress + (i << os_page_shift)); + } +} + +void +osAllocReleasePage +( + NvU64 pAddress, + NvU32 pageCount +) +{ + NvU32 i; + + for (i = 0; i < pageCount; i++) + { + os_put_page(pAddress + (i << os_page_shift)); + } +} + +/* + * @brief Function to return refcount on a page + * @param[in] address The physical address of the page + */ +NvU32 +osGetPageRefcount +( + NvU64 pAddress +) +{ + return os_get_page_refcount(pAddress); +} + +/* + * @brief Function to return the number of tail pages if the address is + * referring to a compound page; For non-compound pages, 1 is returned. + * @param[in] address The physical address of the page + */ +NvU32 +osCountTailPages +( + NvU64 pAddress +) +{ + return os_count_tail_pages(pAddress); +} + +NvU64 +osGetPageSize(void) +{ + return os_page_size; +} + +NvU64 +osGetSupportedSysmemPageSizeMask(void) +{ + // + // We assume that the kernel can support all power-of-two pagesizes + // between os_page_size and os_max_page_size (inclusive). Return a + // bitmask containing all of those. + // + return (((os_max_page_size << 1) - 1) & (~(os_page_size - 1))); +} + +NvU8 +osGetPageShift(void) +{ + return os_page_shift; +} + + + +/* + * @brief Opens a new temporary file for reading and writing + * + * @param[in] ppFile void double pointer + * + * @returns NV_STATUS, NV_OK if success, + NV_ERR_GENERIC, if error + NV_ERR_NOT_SUPPORTED, for unsupported platforms + */ +NV_STATUS +osOpenTemporaryFile +( + void **ppFile +) +{ + return os_open_temporary_file(ppFile); +} + +/* + * @brief Closes the specified temporary file + * + * @param[in] pFile Pointer to file + * + * @returns void + */ +void +osCloseFile +( + void *pFile +) +{ + os_close_file(pFile); +} + +/* + * @brief Writes the buffer to the specified file at the given offset + * + * @param[in] pFile Pointer to file (void) + * @param[in] pBuffer Pointer to buffer from which to copy + * @param[in] size Size of the copy + * @parma[in] offset offset in the file + * + * @returns NV_STATUS, NV_OK if success, + NV_ERR_GENERIC, if error + NV_ERR_NOT_SUPPORTED, for unsupported platforms + */ +NV_STATUS +osWriteToFile +( + void *pFile, + NvU8 *pBuffer, + NvU64 size, + NvU64 offset +) +{ + return os_write_file(pFile, pBuffer, size, offset); +} + +/* + * @brief Reads from the specified file at the given offset + * + * @param[in] pFile Pointer to file (void *) + * @param[in] pBuffer Pointer to buffer to which the data is copied + * @param[in] size Size of the copy + * @parma[in] offset offset in the file + * + * @returns NV_STATUS, NV_OK if success, + NV_ERR_GENERIC, if error + NV_ERR_NOT_SUPPORTED, for unsupported platforms + */ +NV_STATUS +osReadFromFile +( + void *pFile, + NvU8 *pBuffer, + NvU64 size, + NvU64 offset +) +{ + return os_read_file(pFile, pBuffer, size, offset); +} + +/* + * @brief Unregisters caps from the capability framework. + * The function assumes that the caps are allocated and stored in the + * hierarchical order. If they aren't, OS (Linux kernel) would warn and + * leak the caps. + * + * @param[in] pOsRmCaps caps of interest + */ +void +osRmCapUnregister +( + OS_RM_CAPS **ppOsRmCaps +) +{ + OS_RM_CAPS *pOsRmCaps = *ppOsRmCaps; + NvS32 i; + + if (pOsRmCaps == NULL) + { + return; + } + + for (i = pOsRmCaps->count - 1; i >= 0; i--) + { + if (pOsRmCaps->caps[i] != NULL) + { + os_nv_cap_destroy_entry(pOsRmCaps->caps[i]); + } + } + + os_free_mem(pOsRmCaps->caps); + os_free_mem(pOsRmCaps); + + *ppOsRmCaps = NULL; +} + +static NV_STATUS +_allocOsRmCaps +( + OS_RM_CAPS **ppOsRmCaps, + NvU32 count +) +{ + NV_STATUS status; + OS_RM_CAPS *pOsRmCaps; + + *ppOsRmCaps = NULL; + + status = os_alloc_mem((void**)&pOsRmCaps, sizeof(OS_RM_CAPS)); + if (status != NV_OK) + return status; + + pOsRmCaps->count = count; + + status = os_alloc_mem((void**)&pOsRmCaps->caps, sizeof(pOsRmCaps->caps[0]) * count); + if (status != NV_OK) + { + os_free_mem(pOsRmCaps); + return status; + } + + os_mem_set(pOsRmCaps->caps, 0, sizeof(pOsRmCaps->caps[0]) * count); + + *ppOsRmCaps = pOsRmCaps; + return NV_OK; +} + +#define OS_RM_CAP_GPU_DIR 0 +#define OS_RM_CAP_GPU_MIG_DIR 1 +#define OS_RM_CAP_GPU_COUNT 2 + +/* + * @brief Registers OBJGPU with the capability framework. + * + * @param[in] pOsGpuInfo OS specific GPU information pointer + * @param[out] ppOsRmCaps GPU OS specific capabilities pointer + */ +NV_STATUS +osRmCapRegisterGpu +( + OS_GPU_INFO *pOsGpuInfo, + OS_RM_CAPS **ppOsRmCaps +) +{ + NvU32 minor = nv_get_dev_minor(pOsGpuInfo); + char name[16]; + NV_STATUS status; + OS_RM_CAPS *pOsRmCaps; + nv_cap_t *parent; + nv_cap_t *cap; + + // Return success on the unsupported platforms. + if (nvidia_caps_root == NULL) + { + return NV_OK; + } + + if (*ppOsRmCaps != NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + status = _allocOsRmCaps(&pOsRmCaps, OS_RM_CAP_GPU_COUNT); + if (status != NV_OK) + return status; + + *ppOsRmCaps = pOsRmCaps; + + os_snprintf(name, sizeof(name), "gpu%u", minor); + name[sizeof(name) - 1] = '\0'; + parent = nvidia_caps_root; + + cap = os_nv_cap_create_dir_entry(parent, name, (OS_RUGO | OS_XUGO)); + if (cap == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to setup gpu%u directory\n", minor); + status = NV_ERR_OPERATING_SYSTEM; + goto failed; + } + + pOsRmCaps->caps[OS_RM_CAP_GPU_DIR] = cap; + parent = cap; + + // TODO: Bug 2679591: Add MIG directory only if SMC is enabled. + // For now, always add "mig" directory. + cap = os_nv_cap_create_dir_entry(parent, "mig", (OS_RUGO | OS_XUGO)); + if (cap == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to setup mig directory\n"); + status = NV_ERR_OPERATING_SYSTEM; + goto failed; + } + + pOsRmCaps->caps[OS_RM_CAP_GPU_MIG_DIR] = cap; + + return NV_OK; + +failed: + osRmCapUnregister(ppOsRmCaps); + + return status; +} + +#define OS_RM_CAP_SMC_PART_DIR 0 +#define OS_RM_CAP_SMC_PART_ACCESS_FILE 1 +#define OS_RM_CAP_SMC_PART_COUNT 2 + +/* + * @brief Registers SMC partition (a.k.a. GPU instance) with the capability + * framework + * + * @param[in] pGpuOsRmCaps GPU OS specific capabilities pointer + * @param[out] ppPartitionOsRmCaps OS specific capabilities pointer for SMC partition + * @param[in] swizzId SMC partition swizz ID + */ +NV_STATUS +osRmCapRegisterSmcPartition +( + OS_RM_CAPS *pGpuOsRmCaps, + OS_RM_CAPS **ppPartitionOsRmCaps, + NvU32 swizzId +) +{ + char name[16]; + NV_STATUS status; + nv_cap_t *parent; + nv_cap_t *cap; + OS_RM_CAPS *pOsRmCaps; + + // Return success as there is nothing to do. + if (pGpuOsRmCaps == NULL) + { + return NV_OK; + } + + if (*ppPartitionOsRmCaps != NULL || swizzId >= NV_U32_MAX) + { + return NV_ERR_INVALID_ARGUMENT; + } + + parent = pGpuOsRmCaps->caps[OS_RM_CAP_GPU_MIG_DIR]; + if (parent == NULL) + { + return NV_ERR_INVALID_STATE; + } + + status = _allocOsRmCaps(&pOsRmCaps, OS_RM_CAP_SMC_PART_COUNT); + if (status != NV_OK) + return status; + + *ppPartitionOsRmCaps = pOsRmCaps; + + os_snprintf(name, sizeof(name), "gi%u", swizzId); + name[sizeof(name) - 1] = '\0'; + + cap = os_nv_cap_create_dir_entry(parent, name, OS_RUGO | OS_XUGO); + if (cap == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to setup gi%u directory\n", + swizzId); + status = NV_ERR_OPERATING_SYSTEM; + goto failed; + } + + pOsRmCaps->caps[OS_RM_CAP_SMC_PART_DIR] = cap; + parent = cap; + + cap = os_nv_cap_create_file_entry(parent, "access", OS_RUGO); + if (cap == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to setup access file for ID:%u\n", + swizzId); + status = NV_ERR_OPERATING_SYSTEM; + goto failed; + } + + pOsRmCaps->caps[OS_RM_CAP_SMC_PART_ACCESS_FILE] = cap; + + return NV_OK; + +failed: + osRmCapUnregister(ppPartitionOsRmCaps); + + return status; +} + +#define OS_RM_CAP_SMC_EXEC_PART_DIR 0 +#define OS_RM_CAP_SMC_EXEC_PART_ACCESS_FILE 1 +#define OS_RM_CAP_SMC_EXEC_PART_COUNT 2 + +/* + * @brief Registers SMC execution partition (a.k.a. compute instance) with the + * capability framework + * + * @param[in] pPartitionOsRmCaps OS specific capabilities pointer for SMC partition + * @param[out] ppExecPartitionOsRmCaps OS specific capabilities pointer for SMC execution partition + * @param[in] execPartitionId SMC execution partition ID + */ +NV_STATUS +osRmCapRegisterSmcExecutionPartition +( + OS_RM_CAPS *pPartitionOsRmCaps, + OS_RM_CAPS **ppExecPartitionOsRmCaps, + NvU32 execPartitionId +) +{ + char name[16]; + NV_STATUS status; + nv_cap_t *parent; + nv_cap_t *cap; + OS_RM_CAPS *pOsRmCaps; + + // Return success as there is nothing to do. + if (pPartitionOsRmCaps == NULL) + { + return NV_OK; + } + + if ((*ppExecPartitionOsRmCaps != NULL) || (execPartitionId >= NV_U32_MAX)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + parent = pPartitionOsRmCaps->caps[OS_RM_CAP_SMC_PART_DIR]; + if (parent == NULL) + { + return NV_ERR_INVALID_STATE; + } + + status = _allocOsRmCaps(&pOsRmCaps, OS_RM_CAP_SMC_EXEC_PART_COUNT); + if (status != NV_OK) + { + return status; + } + + *ppExecPartitionOsRmCaps = pOsRmCaps; + + os_snprintf(name, sizeof(name), "ci%u", execPartitionId); + name[sizeof(name) - 1] = '\0'; + + cap = os_nv_cap_create_dir_entry(parent, name, OS_RUGO | OS_XUGO); + if (cap == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to setup ci%u directory\n", + execPartitionId); + status = NV_ERR_OPERATING_SYSTEM; + goto failed; + } + + pOsRmCaps->caps[OS_RM_CAP_SMC_EXEC_PART_DIR] = cap; + parent = cap; + + cap = os_nv_cap_create_file_entry(parent, "access", OS_RUGO); + if (cap == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to setup access file for ID:%u\n", + execPartitionId); + status = NV_ERR_OPERATING_SYSTEM; + goto failed; + } + + pOsRmCaps->caps[OS_RM_CAP_SMC_EXEC_PART_ACCESS_FILE] = cap; + + return NV_OK; + +failed: + osRmCapUnregister(ppExecPartitionOsRmCaps); + + return status; +} + +/* + * @brief Release the acquired capability + * + * @param[in] dupedCapDescriptor descriptor to be released + */ +void +osRmCapRelease +( + NvU64 dupedCapDescriptor +) +{ + if (dupedCapDescriptor == NV_U64_MAX) + { + return; + } + + os_nv_cap_close_fd((int)dupedCapDescriptor); +} + +#define OS_RM_CAP_SYS_MIG_DIR 0 +#define OS_RM_CAP_SYS_SMC_CONFIG_FILE 1 +#define OS_RM_CAP_SYS_SMC_MONITOR_FILE 2 +#define OS_RM_CAP_SYS_FABRIC_IMEX_MGMT_FILE 3 +#define OS_RM_CAP_SYS_PROFILER_DEVICE_FILE 4 +#define OS_RM_CAP_SYS_PROFILER_CONTEXT_FILE 5 +#define OS_RM_CAP_SYS_TRACE_DEVICE_FILE 6 +#define OS_RM_CAP_SYS_COUNT 7 + +NV_STATUS +osRmCapRegisterSys +( + OS_RM_CAPS **ppOsRmCaps +) +{ + nv_cap_t **ppCaps; + nv_cap_t *parent; + nv_cap_t *cap; + NV_STATUS status; + OS_RM_CAPS *pOsRmCaps; + + if (nvidia_caps_root == NULL) + return NV_ERR_NOT_SUPPORTED; + + status = _allocOsRmCaps(&pOsRmCaps, OS_RM_CAP_SYS_COUNT); + if (status != NV_OK) + return status; + + *ppOsRmCaps = pOsRmCaps; + + ppCaps = pOsRmCaps->caps; + + parent = os_nv_cap_create_dir_entry(nvidia_caps_root, "mig", OS_RUGO | OS_XUGO); + if (parent == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to create mig directory\n"); + status = NV_ERR_OPERATING_SYSTEM; + goto failed; + } + ppCaps[OS_RM_CAP_SYS_MIG_DIR] = parent; + + cap = os_nv_cap_create_file_entry(parent, "config", OS_RUSR); + if (cap == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to create mig config file\n"); + status = NV_ERR_OPERATING_SYSTEM; + goto failed; + } + ppCaps[OS_RM_CAP_SYS_SMC_CONFIG_FILE] = cap; + + cap = os_nv_cap_create_file_entry(parent, "monitor", OS_RUGO); + if (cap == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to create mig monitor file\n"); + status = NV_ERR_OPERATING_SYSTEM; + goto failed; + } + ppCaps[OS_RM_CAP_SYS_SMC_MONITOR_FILE] = cap; + + cap = os_nv_cap_create_file_entry(nvidia_caps_root, "fabric-imex-mgmt", OS_RUSR); + if (cap == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to create imex file\n"); + status = NV_ERR_OPERATING_SYSTEM; + goto failed; + } + ppCaps[OS_RM_CAP_SYS_FABRIC_IMEX_MGMT_FILE] = cap; + + cap = os_nv_cap_create_file_entry(nvidia_caps_root, "profiler-device", OS_RUSR); + if (cap == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to create profiler-device file\n"); + status = NV_ERR_OPERATING_SYSTEM; + goto failed; + } + ppCaps[OS_RM_CAP_SYS_PROFILER_DEVICE_FILE] = cap; + + cap = os_nv_cap_create_file_entry(nvidia_caps_root, "profiler-context", OS_RUSR); + if (cap == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to create profiler-context file\n"); + status = NV_ERR_OPERATING_SYSTEM; + goto failed; + } + ppCaps[OS_RM_CAP_SYS_PROFILER_CONTEXT_FILE] = cap; + + cap = os_nv_cap_create_file_entry(nvidia_caps_root, "trace-device", OS_RUSR); + if (cap == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to create trace-device file\n"); + status = NV_ERR_OPERATING_SYSTEM; + goto failed; + } + ppCaps[OS_RM_CAP_SYS_TRACE_DEVICE_FILE] = cap; + + return NV_OK; + +failed: + osRmCapUnregister(ppOsRmCaps); + return status; +} + +/* + * @brief Acquire the requested capability + * + * @param[in] pOsRmCaps opaque pointer to the caps. + * @param[in] rmCap the capability to be acquired. + * @param[in] capDescriptor descriptor to be used for validation + * @param[out] dupedCapDescriptor returns duplicated descriptor if validation + * is successful + * + * Note: On Linux, duplicating fd is helpful to let administrators know about + * the capability users. See https://linux.die.net/man/8/lsof usage. + */ +NV_STATUS +osRmCapAcquire +( + OS_RM_CAPS *pOsRmCaps, + NvU32 rmCap, + NvU64 capDescriptor, + NvU64 *dupedCapDescriptor +) +{ + nv_cap_t *cap; + int fd = (int)capDescriptor; + int duped_fd; + NvU32 index; + NV_STATUS status; + + *dupedCapDescriptor = NV_U64_MAX; + + switch (rmCap) + { + case NV_RM_CAP_SMC_PARTITION_ACCESS: + { + index = OS_RM_CAP_SMC_PART_ACCESS_FILE; + break; + } + case NV_RM_CAP_EXT_FABRIC_MGMT: + { + status = nv_acquire_fabric_mgmt_cap(fd, &duped_fd); + if (status != NV_OK) + { + return status; + } + + goto done; + } + case NV_RM_CAP_SMC_EXEC_PARTITION_ACCESS: + { + index = OS_RM_CAP_SMC_EXEC_PART_ACCESS_FILE; + break; + } + case NV_RM_CAP_SYS_SMC_CONFIG: + { + index = OS_RM_CAP_SYS_SMC_CONFIG_FILE; + break; + } + case NV_RM_CAP_SYS_SMC_MONITOR: + { + index = OS_RM_CAP_SYS_SMC_MONITOR_FILE; + break; + } + case NV_RM_CAP_SYS_FABRIC_IMEX_MGMT: + { + index = OS_RM_CAP_SYS_FABRIC_IMEX_MGMT_FILE; + break; + } + case NV_RM_CAP_SYS_PROFILER_DEVICE: + { + index = OS_RM_CAP_SYS_PROFILER_DEVICE_FILE; + break; + } + case NV_RM_CAP_SYS_PROFILER_CONTEXT: + { + index = OS_RM_CAP_SYS_PROFILER_CONTEXT_FILE; + break; + } + case NV_RM_CAP_SYS_TRACE_DEVICE: + { + index = OS_RM_CAP_SYS_TRACE_DEVICE_FILE; + break; + } + default: + { + return NV_ERR_INVALID_ARGUMENT; + } + } + + if (pOsRmCaps == NULL) + { + return NV_ERR_NOT_SUPPORTED; + } + + if (index >= pOsRmCaps->count) + { + return NV_ERR_INVALID_ARGUMENT; + } + + cap = pOsRmCaps->caps[index]; + + duped_fd = os_nv_cap_validate_and_dup_fd(cap, fd); + if (duped_fd < 0) + { + return NV_ERR_INSUFFICIENT_PERMISSIONS; + } + +done: + *dupedCapDescriptor = duped_fd; + + return NV_OK; +} + +/* + * @brief Initializes capability descriptor + * + * @param[out] pCapDescriptor descriptor to be used + * + */ +void +osRmCapInitDescriptor +( + NvU64 *pCapDescriptor +) +{ + *pCapDescriptor = NV_U64_MAX; +} + +/* + * @brief Checks if IMEX channel support is present. + */ +NvBool +osImexChannelIsSupported(void) +{ + return os_imex_channel_is_supported; +} + +/* + * @brief Returns IMEX channel count. + */ +NvS32 +osImexChannelCount +( + void +) +{ + return os_imex_channel_count(); +} + +/* + * @brief Returns IMEX channel number. + * + * @param[in] descriptor OS specific descriptor to query channel number. + * + */ +NvS32 +osImexChannelGet(NvU64 descriptor) +{ + return os_imex_channel_get(descriptor); +} + +/* + * @brief Generates random bytes which can be used as a universally unique + * identifier. + * + * This function may sleep (interruptible). + * + * @param[out] pBytes Array of random bytes + * @param[in] numBytes Size of the array + */ +NV_STATUS +osGetRandomBytes +( + NvU8 *pBytes, + NvU16 numBytes +) +{ + return os_get_random_bytes(pBytes, numBytes); +} + +/* + * @brief Get current process flags.. + */ +NvU32 +osGetCurrentProcessFlags +( + void +) +{ + return os_get_current_process_flags(); +} + +/* + * @brief Allocate wait queue + * + * @param[out] ppWq Wait queue + */ +NV_STATUS +osAllocWaitQueue +( + OS_WAIT_QUEUE **ppWq +) +{ + return os_alloc_wait_queue(ppWq); +} + +/* + * @brief Free wait queue + * + * @param[in] pWq Wait queue + */ +void +osFreeWaitQueue +( + OS_WAIT_QUEUE *pWq +) +{ + os_free_wait_queue(pWq); +} + +/* + * @brief Put thread to uninterruptible sleep + * + * @param[in] pWq Wait queue + */ +void +osWaitUninterruptible +( + OS_WAIT_QUEUE *pWq +) +{ + os_wait_uninterruptible(pWq); +} + +/* + * @brief Put thread to interruptible sleep + * + * @param[in] pWq Wait queue + */ +void +osWaitInterruptible +( + OS_WAIT_QUEUE *pWq +) +{ + os_wait_interruptible(pWq); +} + +/* + * @brief Wake up thread from uninterruptible sleep + * + * @param[in] pWq Wait queue + */ +void +osWakeUp +( + OS_WAIT_QUEUE *pWq +) +{ + os_wake_up(pWq); +} + +NV_STATUS +osReadPFPciConfigInVF +( + NvU32 addr, + NvU32 *data +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +/*! + * @brief Callback function to notify RM when unix layer receives an event + * + * This function is basically a wrapper to call the Core RM layer and is + * being called from DCE KMD when an event is received from DCE RM. + * + * @param[in] handle handle allocated for corresponding IPC type with DCE + * @param[in] interfaceType RM IPC interface type + * @param[in] length length of the message passed from DCE + * @param[in] data any specific data if present + * @param[in] usrCtx any specific user context if present + * + * @returns void + */ +static void +osTegraDceClientIpcCallback +( + NvU32 handle, + NvU32 interfaceType, + NvU32 length, + void *data, + void *usrCtx +) +{ + THREAD_STATE_NODE threadState; + NvU32 rmInterfaceType = nv_tegra_get_rm_interface_type(interfaceType); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + if (rmLocksAcquireAll(RM_LOCK_MODULES_KERNEL_RM_EVENTS) == NV_OK) + { + dceclientHandleAsyncRpcCallback(handle, rmInterfaceType, length, data, usrCtx); + + rmLocksReleaseAll(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); +} + +/*! + * @brief Performs IPC Client registration with DCE + * + * This function is basically a wrapper to call the unix/linux layer. + * + * @param[in] interfaceType RM IPC interface type + * @param[in] usrCtx any specific user context if present + * @param[out] clientId unique ID registered with DCE for IPC + * + * @returns NV_OK if successful, + * NV_ERR_NOT_SUPPORTED if the functionality is not available, or + * other errors as may be returned by subfunctions. + */ +NV_STATUS +osTegraDceRegisterIpcClient +( + NvU32 interfaceType, + void *usrCtx, + NvU32 *clientId +) +{ + if (interfaceType == DCE_CLIENT_RM_IPC_TYPE_SYNC) + return nv_tegra_dce_register_ipc_client(interfaceType, usrCtx, NULL, clientId); + else if (interfaceType == DCE_CLIENT_RM_IPC_TYPE_EVENT) + return nv_tegra_dce_register_ipc_client(interfaceType, usrCtx, osTegraDceClientIpcCallback, clientId); + else + return NV_ERR_INVALID_ARGUMENT; +} + +/*! + * @brief Performs IPC Client destroy with DCE + * + * This function is basically a wrapper to call the unix/linux layer. + * + * @param[in] clientId unique ID registered with DCE for IPC + * + * @returns NV_OK if successful, + * NV_ERR_NOT_SUPPORTED if the functionality is not available, or + * other errors as may be returned by subfunctions. + */ +NV_STATUS +osTegraDceUnregisterIpcClient +( + NvU32 clientId +) +{ + return nv_tegra_dce_unregister_ipc_client(clientId); +} + +/*! + * @brief Performs IPC Send/Receive to/from DCE + * + * This function is basically a wrapper to call the unix/linux layer. + * + * @param[in] clientId unique ID registered with DCE KMD for corresponding IPC type + * @param[in] msg structure to hold dce ipc message info + * @param[in] msgLength length of the message + * + * @returns NV_OK if successful, + * NV_ERR_NOT_SUPPORTED if the functionality is not available, or + * other errors as may be returned by subfunctions. + */ +NV_STATUS +osTegraDceClientIpcSendRecv +( + NvU32 clientId, + void *msg, + NvU32 msgLength +) +{ + return nv_tegra_dce_client_ipc_send_recv(clientId, msg, msgLength); +} + +/*! + * @brief Sends an MRQ (message-request) to BPMP + * + * The request, response, and ret parameters of this function correspond to the + * components of the tegra_bpmp_message struct, which BPMP uses to receive + * MRQs. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] mrq MRQ_xxx ID specifying what is requested + * @param[in] pRequestData Pointer to request input data + * @param[in] requestDataSize Size of structure pointed to by pRequestData + * @param[out] pResponseData Pointer to response output data + * @param[in] responseDataSize Size of structure pointed to by pResponseData + * @param[out] ret MRQ return code (from "ret" element of + * tegra_bpmp_message struct) + * @param[out] apiRet Return code from tegra_bpmp_transfer call + * + * @returns NV_OK if successful, + * NV_ERR_NOT_SUPPORTED if the functionality is not available, + * NV_ERR_INVALID_POINTER if the tegra_bpmp struct pointer could not + * be obtained from nv, or + * NV_ERR_GENERIC if the tegra_bpmp_transfer call failed (see apiRet + * for Linux error code). + */ +NV_STATUS +osTegraSocBpmpSendMrq +( + OBJGPU *pGpu, + NvU32 mrq, + const void *pRequestData, + NvU32 requestDataSize, + void *pResponseData, + NvU32 responseDataSize, + NvS32 *pRet, + NvS32 *pApiRet +) +{ + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_SOC_SDM)) + { + return NV_ERR_NOT_SUPPORTED; + } + else if (pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) + { + return nv_bpmp_send_mrq(pGpu->pOsGpuInfo, + mrq, + pRequestData, + requestDataSize, + pResponseData, + responseDataSize, + pRet, + pApiRet); + } + else + { + return NV_ERR_NOT_SUPPORTED; + } +} + +/*! + * @brief Returns IMP-relevant data collected from other modules + * + * This function is basically a wrapper to call the unix/linux layer. + * + * @param[out] pTegraImpImportData Structure to receive the data + * + * @returns NV_OK if successful, + * NV_ERR_BUFFER_TOO_SMALL if the array in TEGRA_IMP_IMPORT_DATA is + * too small, + * NV_ERR_NOT_SUPPORTED if the functionality is not available, or + * other errors as may be returned by subfunctions. + */ +NV_STATUS +osTegraSocGetImpImportData +( + OBJGPU *pGpu, + TEGRA_IMP_IMPORT_DATA *pTegraImpImportData +) +{ + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) + { + return nv_imp_get_import_data(pTegraImpImportData); + } + else + { + return NV_ERR_NOT_SUPPORTED; + } +} + +/*! + * @brief Returns IMP-relevant data collected from UEFI + * + * This function is basically a wrapper to call the unix/linux layer. + * + * @param[in] pOsGpuInfo Per GPU Linux state + * @param[out] pIsoBwKbps ISO BW set by UEFI + * @param[out] pFloorBwKbps DRAM Floor BW set by UEFI + * + * @returns NV_OK if successful, + * NV_ERR_NOT_SUPPORTED if the functionality is not available, or + * other errors as may be returned by subfunctions. + */ +NV_STATUS +osTegraSocGetImpUefiData +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 *pIsoBwKbps, + NvU32 *pFloorBwKbps +) +{ + return nv_imp_get_uefi_data(pOsGpuInfo, pIsoBwKbps, pFloorBwKbps); +} + +/*! + * @brief Tells BPMP whether or not RFL is valid + * + * Display HW generates an ok_to_switch signal which asserts when mempool + * occupancy is high enough to be able to turn off memory long enough to + * execute a dramclk frequency switch without underflowing display output. + * ok_to_switch drives the RFL ("request for latency") signal in the memory + * unit, and the switch sequencer waits for this signal to go active before + * starting a dramclk switch. However, if the signal is not valid (e.g., if + * display HW or SW has not been initialized yet), the switch sequencer ignores + * the signal. This API tells BPMP whether or not the signal is valid. + * + * @param[in] pOsGpuInfo Per GPU Linux state + * @param[in] bEnable True if RFL will be valid; false if invalid + * + * @returns NV_OK if successful, + * NV_ERR_NOT_SUPPORTED if the functionality is not available, or + * NV_ERR_GENERIC if some other kind of error occurred. + */ +NV_STATUS +osTegraSocEnableDisableRfl +( + OS_GPU_INFO *pOsGpuInfo, + NvBool bEnable +) +{ + if (NV_IS_SOC_DISPLAY_DEVICE(pOsGpuInfo)) + { + return nv_imp_enable_disable_rfl(pOsGpuInfo, bEnable); + } + else + { + return NV_ERR_NOT_SUPPORTED; + } +} + +/*! + * @brief Returns max rates for display clocks passed by UEFI + * + * @param[in] pOsGpuInfo Per GPU Linux state + * @param[out] pMaxDispClkRateDisppll disp clock maxrate with disppll as parent + * @param[out] pMaxDispClkRateSppllClkouta disp clock maxrate with sppllclkouta as parent + * @param[out] pMaxHubClkRateSppllClkoutb hub clock maxrate with sppllclkoutb as parent + * + * @returns NV_OK if successful, + * NV_ERR_NOT_SUPPORTED if the functionality is not available + */ +NV_STATUS +osTegraSocGetDispClockRates +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 *pMaxDispClkRateDisppll, + NvU32 *pMaxDispClkRateSppllClkouta, + NvU32 *pMaxHubClkRateSppllClkoutb +) +{ + nv_state_t *nv = pOsGpuInfo; + + if (NV_IS_SOC_DISPLAY_DEVICE(nv)) + { + *pMaxDispClkRateDisppll = nv->clocks.max_dispclk_rate_using_disppllkhz; + *pMaxDispClkRateSppllClkouta = nv->clocks.max_dispclk_rate_using_sppll0clkoutakhz; + *pMaxHubClkRateSppllClkoutb = nv->clocks.max_hubclk_rate_using_sppll0clkoutbkhz; + + return NV_OK; + } + else + { + return NV_ERR_NOT_SUPPORTED; + } +} + +/*! + * @brief Allocates a specified amount of ISO memory bandwidth for display + * + * floorBandwidthKBPS is the minimum required (i.e., floor) dramclk frequency + * multiplied by the width of the pipe over which the display data will travel. + * (It is understood that the bandwidth calculated by multiplying the clock + * frequency by the pipe width will not be realistically achievable, due to + * overhead in the memory subsystem. The infrastructure will not actually use + * the bandwidth value, except to reverse the calculation to get the required + * dramclk frequency.) + * + * This function is basically a wrapper to call the unix/linux layer. + * + * @param[in] pOsGpuInfo OS specific GPU information pointer + * @param[in] averageBandwidthKBPS Amount of ISO memory bandwidth requested + * @param[in] floorBandwidhtKBPS Min required dramclk freq * pipe width + * + * @returns NV_OK if successful, + * NV_ERR_INSUFFICIENT_RESOURCES if one of the bandwidth values is too + * high, and bandwidth cannot be allocated, + * NV_ERR_NOT_SUPPORTED if the functionality is not available, or + * NV_ERR_GENERIC if some other kind of error occurred. + */ +NV_STATUS +osTegraAllocateDisplayBandwidth +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 averageBandwidthKBPS, + NvU32 floorBandwidthKBPS +) +{ + if (NV_IS_SOC_DISPLAY_DEVICE(pOsGpuInfo)) + { + return nv_imp_icc_set_bw(pOsGpuInfo, + averageBandwidthKBPS, + floorBandwidthKBPS); + } + else + { + return NV_ERR_NOT_SUPPORTED; + } +} + +/*! + * @brief Creates or sets up platform specific nano second resolution timer + * + * @param[in] pOsGpuInfo OS specific GPU information pointer + * @param[in] pTmrEvent Pointer to timer event information + * @param[in/out] pTimer pointer to hold high resolution timer object + */ +NV_STATUS +osCreateNanoTimer +( + OS_GPU_INFO *pOsGpuInfo, + void *pTmrEvent, + void **pTimer +) +{ + nv_create_nano_timer(pOsGpuInfo, pTmrEvent, (nv_nano_timer_t **)pTimer); + return NV_OK; +} + +/*! + * @brief Starts platform specific nano second resolution timer + * + * @param[in] pOsGpuInfo OS specific GPU information pointer + * @param[in] pTimer pointer to high resolution timer object + * @param[in] timeNs Relative time in nano seconds + */ +NV_STATUS +osStartNanoTimer +( + OS_GPU_INFO *pOsGpuInfo, + void *pTimer, + NvU64 timeNs +) +{ + nv_start_nano_timer(pOsGpuInfo, (nv_nano_timer_t *)pTimer, timeNs); + return NV_OK; +} + +/*! + * @brief Cancels platform specific nano second resolution timer + * + * @param[in] pOsGpuInfo OS specific GPU information pointer + * @param[in] pTimer pointer to timer object + */ +NV_STATUS +osCancelNanoTimer +( + OS_GPU_INFO *pOsGpuInfo, + void *pTimer +) +{ + nv_cancel_nano_timer(pOsGpuInfo, (nv_nano_timer_t *)pTimer); + return NV_OK; +} + +/*! + * @brief Destroys & cancels platform specific nano second resolution timer + * + * + * @param[in] pGpu Device of interest + * @param[in] pTimer pointer to timer object + */ +NV_STATUS +osDestroyNanoTimer +( + OS_GPU_INFO *pOsGpuInfo, + void *pTimer +) +{ + nv_destroy_nano_timer(pOsGpuInfo, (nv_nano_timer_t *)pTimer); + return NV_OK; +} + + +NvBool osIsNonPreemptableDebuggerSessionActive(OBJGPU *pGpu) +{ + NvU32 data = 0; + if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_NON_PREEMTABLE_DEBUGGER_SESSION_ACTIVE, &data) == NV_OK) && (data == NV_REG_STR_RM_NON_PREEMTABLE_DEBUGGER_SESSION_ACTIVE_ENABLE)) + { + return NV_TRUE; + } + + return NV_FALSE; +} + +/*! + * @brief Get number of dpAux instances. + * It is wrapper function to call unix/linux layer. + * + * @param[in] pGpu GPU object pointer + * @param[out] pNumIntances Number of dpAux instances. + * + * @returns NV_STATUS, NV_OK if success, + * NV_ERR_GENERIC, if error + * NV_ERR_NOT_SUPPORTED, for unsupported platforms + */ + +NV_STATUS +osGetTegraNumDpAuxInstances +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 *pNumIntances +) +{ + if (NV_IS_SOC_DISPLAY_DEVICE(pOsGpuInfo)) + { + return nv_get_num_dpaux_instances(pOsGpuInfo, pNumIntances); + } + else + { + return NV_ERR_NOT_SUPPORTED; + } +} + +/* + * @brief Return the priv Data of current IRQ. + * It is wrapper function to call unix/linux layer. + * + * @param[in] pGpu Device of interest + * @param[out] pPrivData privData of current IRQ + * + * @returns NV_STATUS, NV_OK if success, + * NV_ERR_GENERIC, if error + * NV_ERR_NOT_SUPPORTED, for unsupported platforms + */ +NV_STATUS +osGetCurrentIrqPrivData +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 *pPrivData +) +{ + if (NV_IS_SOC_DISPLAY_DEVICE(pOsGpuInfo)) + { + return nv_get_current_irq_priv_data(pOsGpuInfo, pPrivData); + } + else + { + return NV_ERR_NOT_SUPPORTED; + } +} + +/*! + * @brief Get the brightness level + * It is wrapper function to call unix/linux layer. + * + * @param[in] pGpu GPU object pointer + * @param[out] brightness Pointer to brightness level + * + * @returns NV_STATUS, NV_OK if success, + * NV_ERR_GENERIC, if error + * NV_ERR_NOT_SUPPORTED, for unsupported platforms + */ +NV_STATUS +osGetTegraBrightnessLevel +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 *brightness +) +{ + if (NV_IS_SOC_DISPLAY_DEVICE(pOsGpuInfo)) + { + return nv_get_tegra_brightness_level(pOsGpuInfo, brightness); + } + else + { + return NV_ERR_NOT_SUPPORTED; + } +} + +/*! + * @brief Set the brightness level + * It is wrapper function to call unix/linux layer. + * + * @param[in] pGpu GPU object pointer + * @param[out] brightness brightness level + * + * @returns NV_STATUS, NV_OK if success, + * NV_ERR_GENERIC, if error + * NV_ERR_NOT_SUPPORTED, for unsupported platforms + */ +NV_STATUS +osSetTegraBrightnessLevel +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 brightness +) +{ + if (NV_IS_SOC_DISPLAY_DEVICE(pOsGpuInfo)) + { + return nv_set_tegra_brightness_level(pOsGpuInfo, brightness); + } + else + { + return NV_ERR_NOT_SUPPORTED; + } +} + +/* @brief Gets syncpoint aperture information + * + * @param[in] OS_GPU_INFO OS specific GPU information pointer + * @param[in] syncpointId + * @param[out] *physAddr + * @param[out] *limit + * @param[out] *offset + */ +NV_STATUS +osGetSyncpointAperture +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 syncpointId, + NvU64 *physAddr, + NvU64 *limit, + NvU32 *offset +) +{ + return nv_get_syncpoint_aperture(syncpointId, physAddr, limit, offset); +} + +/*! + * @brief Enable PCIe AtomicOp Requester Enable and return + * the completer side capabilities that the requester can send. + * + * @param[in] pOsGpuInfo OS_GPU_INFO OS specific GPU information pointer + * @param[out] pMask mask of supported atomic size, including one or more of: + * OS_PCIE_CAP_MASK_REQ_ATOMICS_32 + * OS_PCIE_CAP_MASK_REQ_ATOMICS_64 + * OS_PCIE_CAP_MASK_REQ_ATOMICS_128 + * + * @returns NV_STATUS, NV_OK if success + * NV_ERR_NOT_SUPPORTED if platform doesn't support this + * feature. + * NV_ERR_GENERIC for any other error + */ + +NV_STATUS +osConfigurePcieReqAtomics +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 *pMask +) +{ + if (pMask) + { + *pMask = 0U; + if (pOsGpuInfo) + { + if (os_enable_pci_req_atomics(pOsGpuInfo->handle, + OS_INTF_PCIE_REQ_ATOMICS_32BIT) == NV_OK) + *pMask |= OS_PCIE_CAP_MASK_REQ_ATOMICS_32; + if (os_enable_pci_req_atomics(pOsGpuInfo->handle, + OS_INTF_PCIE_REQ_ATOMICS_64BIT) == NV_OK) + *pMask |= OS_PCIE_CAP_MASK_REQ_ATOMICS_64; + if (os_enable_pci_req_atomics(pOsGpuInfo->handle, + OS_INTF_PCIE_REQ_ATOMICS_128BIT) == NV_OK) + *pMask |= OS_PCIE_CAP_MASK_REQ_ATOMICS_128; + + if (*pMask != 0) + return NV_OK; + } + } + return NV_ERR_NOT_SUPPORTED; +} + +/*! + * @brief Check GPU is accessible or not + * + * @param[in] pGpu GPU object pointer + * + * @returns NVBool, Returns TRUE if the GPU is accessible, + * FALSE, if error + */ +NvBool +osIsGpuAccessible +( + OBJGPU *pGpu +) +{ + return nv_is_gpu_accessible(NV_GET_NV_STATE(pGpu)); +} + +/*! + * @brief Check whether GPU has received a shutdown notification from the OS + */ +NvBool +osIsGpuShutdown +( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + return nv ? nv->is_shutdown : NV_TRUE; +} + +/*! + * @brief Check GPU OS info matches + * + * @param[in] pGpu GPU object pointer + * + * @returns NVBool, Returns TRUE if matched. + */ +NvBool +osMatchGpuOsInfo +( + OBJGPU *pGpu, + void *pOsInfo +) +{ + return nv_match_gpu_os_info(NV_GET_NV_STATE(pGpu), pOsInfo); +} + +/*! + * @brief Release GPU OS info. + * + * @param[in] pOsInfo GPU OS info pointer + * + * @returns void + */ +void +osReleaseGpuOsInfo +( + void *pOsInfo +) +{ + nv_put_file_private(pOsInfo); +} + +/*! + * @brief Get free, total memory of a NUMA node by NUMA node ID from kernel. + * + * @param[in] numaId NUMA node ID. + * @param[out] free_memory_bytes free memory in bytes. + * @param[out] total_memory_bytes total memory in bytes. + * + */ +void +osGetNumaMemoryUsage +( + NvS32 numaId, + NvU64 *free_memory_bytes, + NvU64 *total_memory_bytes +) +{ + NV_STATUS status = os_get_numa_node_memory_usage(numaId, + free_memory_bytes, + total_memory_bytes); + NV_ASSERT(status == NV_OK); +} + +/*! + * @brief Add GPU memory as a NUMA node. + * + * @param[in/out] pOsGpuInfo OS specific GPU information pointer + * @param[in] offset start offset of the partition within FB + * @param[in] size size of the partition + * @param[out] pNumaNodeId OS NUMA node id for the added memory. + * + * @returns NV_OK if all is okay. Otherwise an error-specific value. + * + */ +NV_STATUS +osNumaAddGpuMemory +( + OS_GPU_INFO *pOsGpuInfo, + NvU64 offset, + NvU64 size, + NvU32 *pNumaNodeId +) +{ + nv_state_t *nv = pOsGpuInfo; + + return os_numa_add_gpu_memory(nv->handle, offset, size, pNumaNodeId); +} + +/*! + * @brief Remove a particular SMC partition's GPU memory from OS kernel. + * + * Remove GPU memory from the OS kernel that is earlier added as a NUMA node + * to the kernel in platforms where GPU is coherently connected to the CPU. + * + * @param[in/out] pOsGpuInfo OS_GPU_INFO OS specific GPU information pointer + * @param[in] offset start offset of the partition within FB + * @param[in] size size of the partition + * @param[in] numaNodeId OS NUMA node id of the memory to be removed. + * + */ +void +osNumaRemoveGpuMemory +( + OS_GPU_INFO *pOsGpuInfo, + NvU64 offset, + NvU64 size, + NvU32 numaNodeId +) +{ + nv_state_t *nv = pOsGpuInfo; + + NV_STATUS status = os_numa_remove_gpu_memory(nv->handle, offset, size, numaNodeId); + NV_ASSERT(status == NV_OK); + + return; +} + +NvBool +osDmabufIsSupported(void) +{ + return os_dma_buf_enabled; +} + +NV_STATUS +osGetEgmInfo +( + OBJGPU *pGpu, + NvU64 *pPhysAddr, + NvU64 *pSize, + NvS32 *pNodeId +) +{ + return nv_get_egm_info(NV_GET_NV_STATE(pGpu), pPhysAddr, pSize, pNodeId); +} + +/*! + * @brief Offline (i.e., blacklist) the page containing a given address from OS kernel. + * + * @param[in] address Address (SPA) of the page to be offlined + * + */ +NV_STATUS +osOfflinePageAtAddress +( + NvU64 address +) +{ + return os_offline_page_at_address(address); +} + +void osAllocatedRmClient(void *pOsInfo) +{ + nv_file_private_t* nvfp = (nv_file_private_t*)pOsInfo; + + if (nvfp != NULL) + nvfp->bCleanupRmapi = NV_TRUE; +} + +/*! + * @brief Update variable to indicate console managed by drm driver. + * + * @param[in] OBJGPU GPU object pointer + * + * @returns void + */ +void +osDisableConsoleManagement +( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + nv->client_managed_console = NV_TRUE; +} + +/* + * @brief Return NV_TRUE if GPU is configured as CXL device. + * + * @param[in] pGpu GPU object pointer + */ +NvBool +osGpuIsCxlDevice +( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + return nv->is_cxl_dev; +} + +/* + * @brief Disabel CXL cache and perform writeback and invalidate for CXL device. + * + * @param[in] pGpu GPU object pointer + * @param[in] bEnableCache Enable/Disable flag + */ +void +osCxlSetCaching +( + OBJGPU *pGpu, + NvBool bEnableCache +) +{ + + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + nv_pci_cxl_set_caching(nv, bEnableCache); +} diff --git a/userspace/sdks/nv570/nvalloc/unix/src/osapi.c b/userspace/sdks/nv570/nvalloc/unix/src/osapi.c new file mode 100644 index 0000000..a3d614d --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/src/osapi.c @@ -0,0 +1,6284 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + + + +#include +#include +#include +#include +#include +#include +#include +#include // Declares RmInitRm(). +#include "gpu/gpu.h" +#include "gps.h" +#include + +#include +#include +#include +#include "kernel/gpu/mem_mgr/mem_mgr.h" + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include "platform/sli/sli.h" + +#include + +#include "rmapi/exports.h" +#include "rmapi/rmapi_utils.h" +#include "rmapi/rs_utils.h" +#include "rmapi/resource_fwd_decls.h" +#include +#include +#include "nv-reg.h" +#include "nv-firmware-registry.h" +#include "core/hal_mgr.h" +#include "gpu/device/device.h" + +#include "resserv/rs_server.h" +#include "resserv/rs_client.h" +#include "resserv/rs_resource.h" +#include "gpu/gpu_uuid.h" + +#include "platform/chipset/pci_pbi.h" + +#include "ctrl/ctrl0000/ctrl0000system.h" +#include "ctrl/ctrl0073/ctrl0073dp.h" +#include "ctrl/ctrl0073/ctrl0073system.h" +#include "ctrl/ctrl0073/ctrl0073specific.h" +#include "ctrl/ctrl2080/ctrl2080bios.h" +#include "ctrl/ctrl2080/ctrl2080fb.h" +#include "ctrl/ctrl2080/ctrl2080perf.h" +#include "ctrl/ctrl2080/ctrl2080gpu.h" +#include "ctrl/ctrl402c.h" + +#include "g_nv_name_released.h" // released chip entries from nvChipAutoFlags.h + +#include + +#include "gpu/bus/kern_bus.h" + +// +// If timer callback comes when PM resume is in progress, then it can't be +// serviced. The timer needs to be rescheduled in this case. This time controls +// the duration of rescheduling. +// +#define TIMER_RESCHED_TIME_DURING_PM_RESUME_NS (100 * 1000 * 1000) + +static void RmInflatePageArray( + RmPhysAddr *pteArray, + NvU64 pageCountFrom, + NvU64 pageSizeFrom, + NvU64 pageCountTo, + NvU64 pageSizeTo); +static void RmDeflatePageArray( + RmPhysAddr *pteArray, + NvU64 pageCountFrom, + NvU64 pageSizeFrom, + NvU64 pageCountTo, + NvU64 pageSizeTo); + +static void RmInflatePageArray( + RmPhysAddr *pteArray, + NvU64 pageCountFrom, + NvU64 pageSizeFrom, + NvU64 pageCountTo, + NvU64 pageSizeTo) +{ + NV_ASSERT(pageCountFrom <= pageCountTo); + NV_ASSERT(pageSizeFrom >= pageSizeTo); + NvUPtr dstPageIdx, dstPageOffset; + NvU64 i; + // convert the idx from pageCount_to to pageCount_from. + NvU64 dstPageShift = NV_SRC_TO_DST_PAGE_SHIFT(pageSizeTo, pageSizeFrom); + + // + // We can do the translation in place by moving backwards, since there + // will always be more RM pages than OS pages + // + for (i = pageCountTo - 1; i != NV_U64_MAX; i--) + { + dstPageIdx = i >> dstPageShift; + dstPageOffset = (i & ((1 << dstPageShift) - 1)) * + pageSizeTo; + pteArray[i] = pteArray[dstPageIdx] + dstPageOffset; + } +} + +static void RmDeflatePageArray( + RmPhysAddr *pteArray, + NvU64 pageCountFrom, + NvU64 pageSizeFrom, + NvU64 pageCountTo, + NvU64 pageSizeTo) +{ + NV_ASSERT(pageCountFrom >= pageCountTo); + NV_ASSERT(pageSizeFrom <= pageSizeTo); + NvU64 i; + + for (i = 0; i < pageCountTo; i++) + { + pteArray[i] = pteArray[(i << NV_SRC_TO_DST_PAGE_SHIFT(pageSizeFrom, pageSizeTo))]; + } + + // Zero out the rest of the addresses, which are now invalid + portMemSet(pteArray + i, 0, sizeof(*pteArray) * (pageCountFrom - i)); +} + +void convertPageArrayBetweenOsAndRm( + RmPhysAddr *pteArray, + NvU64 pageCountFrom, + NvU64 pageSizeFrom, + NvU64 pageCountTo, + NvU64 pageSizeTo, + NvU64 *newPageCountTo) +{ + if (pageSizeFrom < pageSizeTo) + { + RmDeflatePageArray(pteArray, + pageCountFrom, + pageSizeFrom, + pageCountTo, + pageSizeTo + ); + if (newPageCountTo) + { + *newPageCountTo = pageCountTo; + } + } + else if (pageSizeFrom > pageSizeTo) + { + RmInflatePageArray(pteArray, + pageCountFrom, + pageSizeFrom, + pageCountTo, + pageSizeTo + ); + } +} + +// +// Helper function which can be called before doing any RM control +// This function: +// +// a. Performs threadStateInit(). +// b. Acquires API lock. +// c. Checks if RMAPI client handle is valid (i.e. RM is initialized) and +// returns early if RMAPI client handle is invalid. +// d. Increments the dynamic power refcount. If GPU is in RTD3 suspended +// state, then it will wake-up the GPU. +// e. Returns the RMAPI interface handle. +// +// This function should be called only when caller doesn't have acquired API +// lock. Caller needs to use RmUnixRmApiEpilogue() after RM control, if +// RmUnixRmApiPrologue() is successful. +// +RM_API *RmUnixRmApiPrologue(nv_state_t *pNv, THREAD_STATE_NODE *pThreadNode, NvU32 module) +{ + threadStateInit(pThreadNode, THREAD_STATE_FLAGS_NONE); + + if ((rmapiLockAcquire(API_LOCK_FLAGS_NONE, module)) == NV_OK) + { + if ((pNv->rmapi.hClient != 0) && + (os_ref_dynamic_power(pNv, NV_DYNAMIC_PM_FINE) == NV_OK)) + { + return rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); + } + + rmapiLockRelease(); + } + + threadStateFree(pThreadNode, THREAD_STATE_FLAGS_NONE); + + return NULL; +} + +// +// Helper function which can be called after doing RM control, if +// caller has used RmUnixRmApiPrologue() helper function. This function: +// +// a. Decrements the dynamic power refcount. +// b. Release API lock. +// c. Performs threadStateFree(). +// +void RmUnixRmApiEpilogue(nv_state_t *pNv, THREAD_STATE_NODE *pThreadNode) +{ + os_unref_dynamic_power(pNv, NV_DYNAMIC_PM_FINE); + rmapiLockRelease(); + threadStateFree(pThreadNode, THREAD_STATE_FLAGS_NONE); +} + +NvBool RmGpuHasIOSpaceEnabled(nv_state_t * nv) +{ + NvU16 val; + NvBool has_io; + os_pci_read_word(nv->handle, NV_CONFIG_PCI_NV_1, &val); + has_io = FLD_TEST_DRF(_CONFIG, _PCI_NV_1, _IO_SPACE, _ENABLED, val); + return has_io; +} + +// This is a stub function for unix +void osHandleDeferredRecovery( + OBJGPU *pGpu +) +{ + +} + +// This is a stub function for unix +NvBool osIsSwPreInitOnly +( + OS_GPU_INFO *pOsGpuInfo +) +{ + return NV_FALSE; +} + +const NvU8 * RmGetGpuUuidRaw( + nv_state_t *pNv +) +{ + NV_STATUS rmStatus; + OBJGPU *pGpu = NULL; + NvU32 gidFlags; + NvBool isApiLockTaken = NV_FALSE; + + if (pNv->nv_uuid_cache.valid) + return pNv->nv_uuid_cache.uuid; + + if (!rmapiLockIsOwner()) + { + rmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU); + if (rmStatus != NV_OK) + { + return NULL; + } + + isApiLockTaken = NV_TRUE; + } + + pGpu = NV_GET_NV_PRIV_PGPU(pNv); + + // + // PBI is not present in simulation and the loop inside + // pciPbiReadUuid takes up considerable amount of time in + // simulation environment during RM load. + // + if (pGpu && IS_SIMULATION(pGpu)) + { + rmStatus = NV_ERR_NOT_SUPPORTED; + } + else + { + if (!pNv->nv_uuid_cache.pci_uuid_read_attempted) + { + rmStatus = pciPbiReadUuid(pNv->handle, pNv->nv_uuid_cache.uuid); + pNv->nv_uuid_cache.pci_uuid_read_attempted = NV_TRUE; + pNv->nv_uuid_cache.pci_uuid_status = rmStatus; + } + else + { + rmStatus = pNv->nv_uuid_cache.pci_uuid_status; + } + } + + if (rmStatus == NV_OK) + { + rmStatus = gpumgrSetUuid(pNv->gpu_id, pNv->nv_uuid_cache.uuid); + if (rmStatus != NV_OK) + { + goto err; + } + + pNv->nv_uuid_cache.valid = NV_TRUE; + goto done; + } + else if (rmStatus == NV_ERR_NOT_SUPPORTED) + { + nv_printf(NV_DBG_INFO, + "NVRM: PBI is not supported for GPU " NV_PCI_DEV_FMT "\n", + NV_PCI_DEV_FMT_ARGS(pNv)); + } + + gidFlags = DRF_DEF(2080_GPU_CMD,_GPU_GET_GID_FLAGS,_TYPE,_SHA1) + | DRF_DEF(2080_GPU_CMD,_GPU_GET_GID_FLAGS,_FORMAT,_BINARY); + + if (!pGpu) + goto err; + + rmStatus = gpuGetGidInfo(pGpu, NULL, NULL, gidFlags); + if (rmStatus != NV_OK) + goto err; + + if (!pGpu->gpuUuid.isInitialized) + goto err; + + // copy the uuid from the OBJGPU uuid cache + os_mem_copy(pNv->nv_uuid_cache.uuid, pGpu->gpuUuid.uuid, GPU_UUID_LEN); + pNv->nv_uuid_cache.valid = NV_TRUE; + +done: + if (isApiLockTaken) + { + rmapiLockRelease(); + } + + return pNv->nv_uuid_cache.uuid; + +err: + if (isApiLockTaken) + { + rmapiLockRelease(); + } + + return NULL; +} + +static NV_STATUS RmGpuUuidRawToString( + const NvU8 *pGidData, + char *pBuf, + NvU32 bufLen +) +{ + NvU8 *pGidString; + NvU32 GidStrlen; + NV_STATUS rmStatus; + NvU32 gidFlags; + + gidFlags = DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _FORMAT, _ASCII) | + DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, _SHA1); + + rmStatus = transformGidToUserFriendlyString(pGidData, RM_SHA1_GID_SIZE, + &pGidString, &GidStrlen, + gidFlags, + RM_UUID_PREFIX_GPU); + if (rmStatus != NV_OK) + return rmStatus; + + if (bufLen >= GidStrlen) + portMemCopy(pBuf, bufLen, pGidString, GidStrlen); + else + rmStatus = NV_ERR_BUFFER_TOO_SMALL; + + portMemFree((void *)pGidString); + + return rmStatus; +} + +// This function should be called with the API and GPU locks already acquired. +void +RmLogGpuCrash(OBJGPU *pGpu) +{ + NvBool bGpuIsLost, bGpuIsConnected; + + // + // Re-evaluate whether or not the GPU is accessible. This could be called + // from a recovery context where the OS has re-enabled MMIO for the device. + // This happens during EEH processing on IBM Power + Linux, and marking + // the device as connected again will allow rcdbAddRmGpuDump() to collect + // more GPU state. + // + bGpuIsLost = pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_LOST); + bGpuIsConnected = pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_CONNECTED); + if (!bGpuIsConnected || bGpuIsLost) + { + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvU32 pmcBoot0 = NV_PRIV_REG_RD32(nv->regs->map_u, NV_PMC_BOOT_0); + if (pmcBoot0 == nvp->pmc_boot_0) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_CONNECTED, NV_TRUE); + pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_LOST, NV_FALSE); + } + } + + { + // + // Log the engine data to the Journal object, to be pulled out later. This + // will return NV_WARN_MORE_PROCESSING_REQUIRED if the dump needed to be + // deferred to a passive IRQL. We still log the crash dump as being created + // in that case since it (should) be created shortly thereafter, and + // there's currently not a good way to print the below notification + // publicly from the core RM when the DPC completes. + // + NV_STATUS status = rcdbAddRmGpuDump(pGpu); + if (status != NV_OK && status != NV_WARN_MORE_PROCESSING_REQUIRED) + { + NV_PRINTF(LEVEL_ERROR, + "%s: failed to save GPU crash data\n", __FUNCTION__); + } + else + { + nv_printf(NV_DBG_ERRORS, + "NVRM: A GPU crash dump has been created. If possible, please run\n" + "NVRM: nvidia-bug-report.sh as root to collect this data before\n" + "NVRM: the NVIDIA kernel module is unloaded.\n"); + if (!IS_GSP_CLIENT(pGpu) && hypervisorIsVgxHyper()) + { + nv_printf(NV_DBG_ERRORS, "NVRM: Dumping nvlogs buffers\n"); + nvlogDumpToKernelLog(NV_FALSE); + } + } + } + + // Restore the disconnected properties, if they were reset + pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_CONNECTED, bGpuIsConnected); + pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_LOST, bGpuIsLost); + + // Restore persistence mode to the way it was prior to the crash + osModifyGpuSwStatePersistence(pGpu->pOsGpuInfo, + pGpu->getProperty(pGpu, PDB_PROP_GPU_PERSISTENT_SW_STATE)); +} + +static void free_os_event_under_lock(nv_event_t *event) +{ + portAtomicSetS32(&event->active, 0); + + // If refcount > 0, event will be freed by osDereferenceObjectCount + // when the last associated RM event is freed. + if (event->refcount == 0) + portMemFree(event); +} + +static void free_os_events( + nv_file_private_t *nvfp, + NvHandle client +) +{ + nv_state_t *nv = nv_get_ctl_state(); + nv_event_t **pprev; + + portSyncSpinlockAcquire(nv->event_spinlock); + + pprev = &nv->event_list; + while (*pprev != NULL) + { + nv_event_t *cur = *pprev; + // + // XXX We must be called from either rm_client_free_os_events() or + // RmFreeUnusedClients() for this to work. + // + if ((cur->hParent == client) || (cur->nvfp == nvfp)) + { + *pprev = cur->next; + free_os_event_under_lock(cur); + } + else + { + pprev = &cur->next; + } + } + + portSyncSpinlockRelease(nv->event_spinlock); +} + +static NV_STATUS get_os_event_data( + nv_file_private_t *nvfp, + NvP64 pEvent, + NvU32 *MoreEvents +) +{ + nv_event_t nv_event; + NvUnixEvent *nv_unix_event; + NV_STATUS status; + + status = os_alloc_mem((void**)&nv_unix_event, sizeof(NvUnixEvent)); + if (status != NV_OK) + return status; + + status = nv_get_event(nvfp, &nv_event, MoreEvents); + if (status != NV_OK) + { + status = NV_ERR_OPERATING_SYSTEM; + goto done; + } + + os_mem_set(nv_unix_event, 0, sizeof(NvUnixEvent)); + nv_unix_event->hObject = nv_event.hObject; + nv_unix_event->NotifyIndex = nv_event.index; + nv_unix_event->info32 = nv_event.info32; + nv_unix_event->info16 = nv_event.info16; + + status = os_memcpy_to_user(NvP64_VALUE(pEvent), nv_unix_event, sizeof(NvUnixEvent)); +done: + os_free_mem(nv_unix_event); + return status; +} + +void rm_client_free_os_events( + NvHandle client +) +{ + free_os_events(NULL, client); +} + +void RmFreeUnusedClients( + nv_state_t *nv, + nv_file_private_t *nvfp +) +{ + NvU32 *pClientList; + NvU32 numClients, i; + NV_STATUS status; + RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); + + // + // The 'nvfp' pointer uniquely identifies an open instance in kernel space + // and the kernel interface layer guarantees that we are not called before + // the associated nvfp descriptor is closed. We can thus safely free + // abandoned clients with matching 'nvfp' pointers. + // + status = rmapiGetClientHandlesFromOSInfo(nvfp, &pClientList, &numClients); + if (status != NV_OK) + { + numClients = 0; + } + + for (i = 0; i < numClients; ++i) + { + NV_PRINTF(LEVEL_INFO, "freeing abandoned client 0x%x\n", + pClientList[i]); + + } + + if (numClients != 0) + { + pRmApi->DisableClients(pRmApi, pClientList, numClients); + + portMemFree(pClientList); + } + + // Clean up any remaining events using this nvfp. + free_os_events(nvfp, 0); +} + +static void RmUnbindLock( + nv_state_t *nv +) +{ + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + + if ((pGpu == NULL) || (gpuGetUserClientCount(pGpu) == 0)) + { + nv->flags |= NV_FLAG_UNBIND_LOCK; + } +} + +static NV_STATUS allocate_os_event( + NvHandle hParent, + nv_file_private_t *nvfp, + NvU32 fd +) +{ + nv_state_t *nv = nv_get_ctl_state(); + NvU32 status = NV_OK; + nv_event_t *event; + + nv_event_t *new_event = portMemAllocNonPaged(sizeof(nv_event_t)); + if (new_event == NULL) + { + status = NV_ERR_NO_MEMORY; + goto done; + } + + new_event->hParent = hParent; + new_event->nvfp = nvfp; + new_event->fd = fd; + portAtomicSetS32(&new_event->active, 1); + new_event->refcount = 0; + + portSyncSpinlockAcquire(nv->event_spinlock); + for (event = nv->event_list; event; event = event->next) + { + // Only one event may be associated with a given fd. + if (event->hParent == hParent && event->fd == fd) + { + status = NV_ERR_INVALID_ARGUMENT; + portSyncSpinlockRelease(nv->event_spinlock); + goto done; + } + } + + new_event->next = nv->event_list; + nv->event_list = new_event; + nvfp->bCleanupRmapi = NV_TRUE; + portSyncSpinlockRelease(nv->event_spinlock); + +done: + if (status == NV_OK) + { + NV_PRINTF(LEVEL_INFO, "allocated OS event:\n"); + NV_PRINTF(LEVEL_INFO, " hParent: 0x%x\n", hParent); + NV_PRINTF(LEVEL_INFO, " fd: %d\n", fd); + } + else + { + NV_PRINTF(LEVEL_INFO, "failed to allocate OS event: 0x%08x\n", status); + status = NV_ERR_INSUFFICIENT_RESOURCES; + portMemFree(new_event); + } + + return status; +} + +static NV_STATUS free_os_event( + NvHandle hParent, + NvU32 fd +) +{ + nv_state_t *nv = nv_get_ctl_state(); + nv_event_t *event, *tmp; + NV_STATUS result; + + portSyncSpinlockAcquire(nv->event_spinlock); + tmp = event = nv->event_list; + while (event) + { + if ((event->fd == fd) && (event->hParent == hParent)) + { + if (event == nv->event_list) + nv->event_list = event->next; + else + tmp->next = event->next; + break; + } + tmp = event; + event = event->next; + } + + if (event != NULL) + { + free_os_event_under_lock(event); + result = NV_OK; + } + else + result = NV_ERR_INVALID_EVENT; + portSyncSpinlockRelease(nv->event_spinlock); + + if (result == NV_OK) + { + NV_PRINTF(LEVEL_INFO, "freed OS event:\n"); + NV_PRINTF(LEVEL_INFO, " hParent: 0x%x\n", hParent); + NV_PRINTF(LEVEL_INFO, " fd: %d\n", fd); + } + else + { + NV_PRINTF(LEVEL_ERROR, "failed to find OS event:\n"); + NV_PRINTF(LEVEL_ERROR, " hParent: 0x%x\n", hParent); + NV_PRINTF(LEVEL_ERROR, " fd: %d\n", fd); + } + + return result; +} + +static void RmExecuteWorkItem( + void *pWorkItem +) +{ + nv_work_item_t *pWi = (nv_work_item_t *)pWorkItem; + NvU32 gpuMask = 0; + OsQueueWorkItemFlags releaseLocks = {0}; + + if (!(pWi->flags.bRequiresGpu) && + (pWi->flags.bLockGpus || + pWi->flags.bLockGpuGroupDevice || + pWi->flags.bLockGpuGroupSubdevice || + pWi->flags.bFullGpuSanity)) + { + // Requesting one of the GPU locks without providing a GPU instance + NV_ASSERT(0); + goto done; + } + + // Get locks requested by workitem + if (NV_OK != workItemLocksAcquire(pWi->gpuInstance, pWi->flags, + &releaseLocks, &gpuMask)) + { + goto done; + } + + // Some work items may not require a valid GPU instance + if (pWi->flags.bRequiresGpu) + { + // Make sure that pGpu is present + OBJGPU *pGpu = gpumgrGetGpu(pWi->gpuInstance); + if (pGpu != NULL) + { + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + NV_ASSERT_OR_GOTO(nv != NULL, done); + + NvU32 prevGpuInst = gpumgrSetCurrentGpuInstance(pGpu->gpuInstance); + + if (!(pWi->flags.bDropOnUnloadQueueFlush && os_is_queue_flush_ongoing(nv->queue))) + { + pWi->func.pGpuFunction(pWi->gpuInstance, pWi->pData); + } + + gpumgrSetCurrentGpuInstance(prevGpuInst); + } + else + { + NV_PRINTF(LEVEL_ERROR, "Invalid GPU instance for workitem\n"); + } + } + else + { + if (!(pWi->flags.bDropOnUnloadQueueFlush && os_is_queue_flush_ongoing(NULL))) + { + pWi->func.pSystemFunction(pWi->pData); + } + } + +done: + // Release any locks taken + workItemLocksRelease(releaseLocks, gpuMask); + + if ((pWi->pData != NULL) && !(pWi->flags.bDontFreeParams)) + { + portMemFree(pWi->pData); + } + + portMemFree((void *)pWi); +} + +static NV_STATUS RmAccessRegistry( + NvHandle hClient, + NvHandle hObject, + NvU32 AccessType, + NvP64 clientDevNodeAddress, + NvU32 DevNodeLength, + NvP64 clientParmStrAddress, + NvU32 ParmStrLength, + NvP64 clientBinaryDataAddress, + NvU32 *pBinaryDataLength, + NvU32 *Data, + NvU32 *Entry +) +{ + NvU32 gpuMask = 0, gpuInstance = 0; + OBJGPU *pGpu; + NvBool isDevice = NV_FALSE; + NV_STATUS RmStatus = NV_ERR_OPERATING_SYSTEM; + CLIENT_ENTRY *pClientEntry; + Device *pDevice; + Subdevice *pSubdevice; + + RMAPI_PARAM_COPY devNodeParamCopy; + NvU8 *tmpDevNode = NULL; + NvU32 copyOutDevNodeLength = 0; + + RMAPI_PARAM_COPY parmStrParamCopy; + char *tmpParmStr = NULL; + NvU32 copyOutParmStrLength = 0; + + RMAPI_PARAM_COPY binaryDataParamCopy; + NvU8 *tmpBinaryData = NULL; + NvU32 BinaryDataLength = 0; + NvU32 copyOutBinaryDataLength = 0; + + if (NV_OK != serverAcquireClient(&g_resServ, hClient, LOCK_ACCESS_WRITE, + &pClientEntry)) + { + return NV_ERR_INVALID_CLIENT; + } + + if (hClient == hObject) + { + pGpu = NULL; + } + else + { + RsClient *pClient = pClientEntry->pClient; + + RmStatus = deviceGetByHandle(pClient, hObject, &pDevice); + if (RmStatus != NV_OK) + { + RmStatus = subdeviceGetByHandle(pClient, hObject, &pSubdevice); + if (RmStatus != NV_OK) + goto done; + + RmStatus = rmGpuGroupLockAcquire(pSubdevice->subDeviceInst, + GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_GPU, + &gpuMask); + if (RmStatus != NV_OK) + { + gpuMask = 0; + goto done; + } + + GPU_RES_SET_THREAD_BC_STATE(pSubdevice); + pGpu = GPU_RES_GET_GPU(pSubdevice); + } + else + { + RmStatus = rmGpuGroupLockAcquire(pDevice->deviceInst, + GPU_LOCK_GRP_DEVICE, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_GPU, + &gpuMask); + if (RmStatus != NV_OK) + { + gpuMask = 0; + goto done; + } + + GPU_RES_SET_THREAD_BC_STATE(pDevice); + pGpu = GPU_RES_GET_GPU(pDevice); + isDevice = NV_TRUE; + } + } + + if (pBinaryDataLength) + { + BinaryDataLength = *pBinaryDataLength; + } + + // a passed-in devNode + if (DevNodeLength) + { + // the passed-in DevNodeLength does not account for '\0' + DevNodeLength++; + + if (DevNodeLength > NVOS38_MAX_REGISTRY_STRING_LENGTH) + { + RmStatus = NV_ERR_INVALID_STRING_LENGTH; + goto done; + } + + // get access to client's DevNode + RMAPI_PARAM_COPY_INIT(devNodeParamCopy, tmpDevNode, clientDevNodeAddress, DevNodeLength, 1); + devNodeParamCopy.flags |= RMAPI_PARAM_COPY_FLAGS_ZERO_BUFFER; + RmStatus = rmapiParamsAcquire(&devNodeParamCopy, NV_TRUE); + if (RmStatus != NV_OK) + { + RmStatus = NV_ERR_OPERATING_SYSTEM; + goto done; + } + } + + // a passed-in parmStr + if (ParmStrLength) + { + // the passed-in ParmStrLength does not account for '\0' + ParmStrLength++; + + if ((ParmStrLength == 0) || (ParmStrLength > NVOS38_MAX_REGISTRY_STRING_LENGTH)) + { + RmStatus = NV_ERR_INVALID_STRING_LENGTH; + goto done; + } + // get access to client's parmStr + RMAPI_PARAM_COPY_INIT(parmStrParamCopy, tmpParmStr, clientParmStrAddress, ParmStrLength, 1); + RmStatus = rmapiParamsAcquire(&parmStrParamCopy, NV_TRUE); + if (RmStatus != NV_OK) + { + RmStatus = NV_ERR_OPERATING_SYSTEM; + goto done; + } + if (tmpParmStr[ParmStrLength - 1] != '\0') + { + RmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + } + + if ((AccessType == NVOS38_ACCESS_TYPE_READ_BINARY) || + (AccessType == NVOS38_ACCESS_TYPE_WRITE_BINARY)) + { + if ((BinaryDataLength > NVOS38_MAX_REGISTRY_BINARY_LENGTH) || + (BinaryDataLength == 0)) + { + RmStatus = NV_ERR_INVALID_STRING_LENGTH; + goto done; + } + + // get access to client's binaryData + RMAPI_PARAM_COPY_INIT(binaryDataParamCopy, tmpBinaryData, clientBinaryDataAddress, BinaryDataLength, 1); + if (AccessType == NVOS38_ACCESS_TYPE_READ_BINARY) + binaryDataParamCopy.flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYIN; + RmStatus = rmapiParamsAcquire(&binaryDataParamCopy, NV_TRUE); + if (RmStatus != NV_OK) + { + RmStatus = NV_ERR_OPERATING_SYSTEM; + goto done; + } + } + + switch (AccessType) + { + case NVOS38_ACCESS_TYPE_READ_DWORD: + RmStatus = osReadRegistryDword(pGpu, + tmpParmStr, Data); + break; + + case NVOS38_ACCESS_TYPE_WRITE_DWORD: + if (!osIsAdministrator()) + { + RmStatus = NV_ERR_INSUFFICIENT_PERMISSIONS; + break; + } + if (isDevice) + { + while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + RmStatus = osWriteRegistryDword(pGpu, + tmpParmStr, *Data); + + if (RmStatus != NV_OK) + goto done; + } + break; + } + + RmStatus = osWriteRegistryDword(pGpu, + tmpParmStr, *Data); + break; + + case NVOS38_ACCESS_TYPE_READ_BINARY: + RmStatus = osReadRegistryBinary(pGpu, + tmpParmStr, tmpBinaryData, &BinaryDataLength); + + if (RmStatus != NV_OK) + { + goto done; + } + + if (BinaryDataLength) + copyOutBinaryDataLength = BinaryDataLength; + + break; + + case NVOS38_ACCESS_TYPE_WRITE_BINARY: + if (!osIsAdministrator()) + { + RmStatus = NV_ERR_INSUFFICIENT_PERMISSIONS; + break; + } + if (isDevice) + { + while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + RmStatus = osWriteRegistryBinary(pGpu, + tmpParmStr, tmpBinaryData, + BinaryDataLength); + + if (RmStatus != NV_OK) + goto done; + } + break; + } + + RmStatus = osWriteRegistryBinary(pGpu, + tmpParmStr, tmpBinaryData, + BinaryDataLength); + break; + + default: + RmStatus = NV_ERR_INVALID_ACCESS_TYPE; + } + + done: + if (gpuMask != 0) + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + + if (tmpDevNode != NULL) + { + // skip copyout on error + if ((RmStatus != NV_OK) || (copyOutDevNodeLength == 0)) + devNodeParamCopy.flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYOUT; + devNodeParamCopy.paramsSize = copyOutDevNodeLength; + if (NV_OK != rmapiParamsRelease(&devNodeParamCopy)) + if (RmStatus == NV_OK) + RmStatus = NV_ERR_OPERATING_SYSTEM; + } + if (tmpParmStr != NULL) + { + // skip copyout on error + if ((RmStatus != NV_OK) || (copyOutParmStrLength == 0)) + parmStrParamCopy.flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYOUT; + parmStrParamCopy.paramsSize = copyOutParmStrLength; + if (NV_OK != rmapiParamsRelease(&parmStrParamCopy)) + if (RmStatus == NV_OK) + RmStatus = NV_ERR_OPERATING_SYSTEM; + } + if (tmpBinaryData != NULL) + { + // skip copyout on error + if ((RmStatus != NV_OK) || (copyOutBinaryDataLength == 0)) + binaryDataParamCopy.flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYOUT; + binaryDataParamCopy.paramsSize = copyOutBinaryDataLength; + if (NV_OK != rmapiParamsRelease(&binaryDataParamCopy)) + if (RmStatus == NV_OK) + RmStatus = NV_ERR_OPERATING_SYSTEM; + *pBinaryDataLength = copyOutBinaryDataLength; + } + + serverReleaseClient(&g_resServ, LOCK_ACCESS_WRITE, pClientEntry); + return RmStatus; +} + +static NV_STATUS RmUpdateDeviceMappingInfo( + NvHandle hClient, + NvHandle hDevice, + NvHandle hMappable, + void *pOldCpuAddress, + void *pNewCpuAddress +) +{ + NV_STATUS status; + CLIENT_ENTRY *pClientEntry; + RsClient *pClient; + RsResourceRef *pMappableRef; + RsCpuMapping *pCpuMapping; + Device *pDevice; + Subdevice *pSubdevice; + NvU32 gpuMask = 0; + + status = serverAcquireClient(&g_resServ, hClient, LOCK_ACCESS_WRITE, &pClientEntry); + if (status != NV_OK) + return status; + + pClient = pClientEntry->pClient; + + status = deviceGetByHandle(pClient, hDevice, &pDevice); + if (status != NV_OK) + { + status = subdeviceGetByHandle(pClient, hDevice, &pSubdevice); + if (status != NV_OK) + goto done; + + status = rmGpuGroupLockAcquire(pSubdevice->subDeviceInst, + GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_GPU, + &gpuMask); + if (status != NV_OK) + goto done; + + GPU_RES_SET_THREAD_BC_STATE(pSubdevice); + } + else + { + status = rmGpuGroupLockAcquire(pDevice->deviceInst, + GPU_LOCK_GRP_DEVICE, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_GPU, + &gpuMask); + if (status != NV_OK) + goto done; + + GPU_RES_SET_THREAD_BC_STATE(pDevice); + } + + status = clientGetResourceRef(pClient, hMappable, &pMappableRef); + if (status != NV_OK) + goto done; + + if ((objDynamicCastById(pMappableRef->pResource, classId(Memory)) == NULL) && + (objDynamicCastById(pMappableRef->pResource, classId(KernelCcuApi)) == NULL) && + (objDynamicCastById(pMappableRef->pResource, classId(KernelChannel)) == NULL)) + { + status = NV_ERR_INVALID_OBJECT_HANDLE; + goto done; + } + + status = refFindCpuMappingWithFilter(pMappableRef, + NV_PTR_TO_NvP64(pOldCpuAddress), + serverutilMappingFilterCurrentUserProc, + &pCpuMapping); + if (status != NV_OK) + goto done; + + pCpuMapping->pLinearAddress = NV_PTR_TO_NvP64(pNewCpuAddress); + +done: + + if (gpuMask != 0) + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + + serverReleaseClient(&g_resServ, LOCK_ACCESS_WRITE, pClientEntry); + return status; +} + +static void RmSanitizeLogString( + char *pString, + NvU32 stringLength +) +{ + NvU32 i; + + if (pString == NULL) + return; + + for (i = 0; i < stringLength; i++) + { + NvU8 ch = (NvU8)pString[i]; + + if (ch == '\0') + return; + + if ((ch < 0x20) || (ch == 0x7f)) + { + pString[i] = '?'; + } + } +} + +static NV_STATUS RmPerformVersionCheck( + void *pData, + NvU32 dataSize +) +{ + nv_ioctl_rm_api_version_t *pParams; + char clientCh, rmCh; + const char *rmStr = NV_VERSION_STRING; + NvBool relaxed = NV_FALSE; + NvU32 i; + NvU32 procId; + char procName[32]; + + // + // rmStr (i.e., NV_VERSION_STRING) must be null-terminated and fit within + // NV_RM_API_VERSION_STRING_LENGTH, so that: + // + // (1) If the versions don't match, we can return rmStr in + // pParams->versionString. + // (2) The below loop is guaranteed to not overrun rmStr. + // + ct_assert(sizeof(NV_VERSION_STRING) <= NV_RM_API_VERSION_STRING_LENGTH); + + if (dataSize != sizeof(nv_ioctl_rm_api_version_t)) + return NV_ERR_INVALID_ARGUMENT; + + pParams = pData; + + // + // write the reply value, so that the client knows we recognized + // the request + // + pParams->reply = NV_RM_API_VERSION_REPLY_RECOGNIZED; + + // + // the client is just querying the version, not verifying against expected. + // + if (pParams->cmd == NV_RM_API_VERSION_CMD_QUERY) + { + os_string_copy(pParams->versionString, rmStr); + return NV_OK; + } + + // + // the client requested relaxed version checking; we will only + // compare the strings until the first decimal point. + // + if (pParams->cmd == NV_RM_API_VERSION_CMD_RELAXED) + { + relaxed = NV_TRUE; + } + + for (i = 0; i < NV_RM_API_VERSION_STRING_LENGTH; i++) + { + clientCh = pParams->versionString[i]; + rmCh = rmStr[i]; + + // + // fail if the current character is not the same + // + if (clientCh != rmCh) + { + break; + } + + // + // if relaxed matching was requested, succeed when we find the + // first decimal point + // + if ((relaxed) && (clientCh == '.')) + { + return NV_OK; + } + + // + // we found the end of the strings: succeed + // + if (clientCh == '\0') + { + return NV_OK; + } + } + + // + // the version strings did not match: print an error message and + // copy the RM's version string into pParams->versionString, so + // that the client can report the mismatch; explicitly NULL + // terminate the client's string, since we cannot trust it + // + pParams->versionString[NV_RM_API_VERSION_STRING_LENGTH - 1] = '\0'; + + procId = os_get_current_process(); + os_get_current_process_name(procName, sizeof(procName)); + + RmSanitizeLogString(pParams->versionString, NV_RM_API_VERSION_STRING_LENGTH); + RmSanitizeLogString(procName, sizeof(procName)); + + nv_printf(NV_DBG_ERRORS, + "NVRM: API mismatch: the client '%s' (pid %u)\n" + "NVRM: has the version %s, but this kernel module has\n" + "NVRM: the version %s. Please make sure that this\n" + "NVRM: kernel module and all NVIDIA driver components\n" + "NVRM: have the same version.\n", + procName, procId, + pParams->versionString, NV_VERSION_STRING); + + os_string_copy(pParams->versionString, rmStr); + + return NV_ERR_GENERIC; +} + +NV_STATUS RmPowerSourceChangeEvent( + nv_state_t *pNv, + NvU32 event_val +) +{ + NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS params = {0}; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + params.powerStateInfo.powerState = event_val ? NV2080_CTRL_PERF_POWER_SOURCE_BATTERY : + NV2080_CTRL_PERF_POWER_SOURCE_AC; + + return pRmApi->Control(pRmApi, pNv->rmapi.hClient, + pNv->rmapi.hSubDevice, + NV2080_CTRL_CMD_PERF_SET_POWERSTATE, + ¶ms, sizeof(params)); +} + +/*! + * @brief Function to request latest D-Notifier status from SBIOS. + * + * Handle certain scenarios (like a fresh boot or suspend/resume + * of the system) when RM is not available to receive the Dx notifiers. + * This function gets the latest D-Notifier status from SBIOS + * when RM is ready to receive and handle those events. + * Use GPS_FUNC_REQUESTDXSTATE subfunction to invoke current Dx state. + * + * @param[in] pNv nv_state_t pointer. + */ +void RmRequestDNotifierState( + nv_state_t *pNv +) +{ + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + NvU32 supportedFuncs = 0; + NvU16 dsmDataSize = sizeof(supportedFuncs); + NV_STATUS status = NV_OK; + + status = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_GPS_2X, + GPS_FUNC_REQUESTDXSTATE, &supportedFuncs, + &dsmDataSize); + if (status != NV_OK) + { + // + // Call for 'GPS_FUNC_REQUESTDXSTATE' subfunction may fail if the + // SBIOS/EC does not have the corresponding implementation. + // + NV_PRINTF(LEVEL_INFO, + "%s: Failed to request Dx event update, status 0x%x\n", + __FUNCTION__, status); + } +} + +/*! + * @brief Deal with D-notifier events to apply a performance + * level based on the requested auxiliary power-state. + * Read confluence page "D-Notifiers on Linux" for more details. + * + * @param[in] pNv nv_state_t pointer. + * @param[in] event_type NvU32 Event type. + */ +static void RmHandleDNotifierEvent( + nv_state_t *pNv, + NvU32 event_type +) +{ + NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS params = { 0 }; + RM_API *pRmApi; + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_OK; + + switch (event_type) + { + case ACPI_NOTIFY_POWER_LEVEL_D1: + params.powerState = NV2080_CTRL_PERF_AUX_POWER_STATE_P0; + break; + case ACPI_NOTIFY_POWER_LEVEL_D2: + params.powerState = NV2080_CTRL_PERF_AUX_POWER_STATE_P1; + break; + case ACPI_NOTIFY_POWER_LEVEL_D3: + params.powerState = NV2080_CTRL_PERF_AUX_POWER_STATE_P2; + break; + case ACPI_NOTIFY_POWER_LEVEL_D4: + params.powerState = NV2080_CTRL_PERF_AUX_POWER_STATE_P3; + break; + case ACPI_NOTIFY_POWER_LEVEL_D5: + params.powerState = NV2080_CTRL_PERF_AUX_POWER_STATE_P4; + break; + default: + return; + } + + pRmApi = RmUnixRmApiPrologue(pNv, &threadState, RM_LOCK_MODULES_ACPI); + if (pRmApi == NULL) + { + return; + } + + rmStatus = pRmApi->Control(pRmApi, pNv->rmapi.hClient, + pNv->rmapi.hSubDevice, + NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE, + ¶ms, sizeof(params)); + + RmUnixRmApiEpilogue(pNv, &threadState); + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s: Failed to handle ACPI D-Notifier event, status=0x%x\n", + __FUNCTION__, rmStatus); + } +} + +static NvU32 RmDmabufMmapGetCpuCacheType( + OBJGPU *pGpu, + MEMORY_DESCRIPTOR *pMemDesc, + NvU8 mappingType +) +{ + if (pGpu->pGpuArch->bGpuArchIsZeroFb) + { + return memdescGetCpuCacheAttrib(pMemDesc); + } + +#if defined(NVCPU_X86_64) + return NV_MEMORY_WRITECOMBINED; +#elif defined(NVCPU_AARCH64) + if ((pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) && + (mappingType == NV_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT)) + { + return NV_MEMORY_CACHED; + } + else + { + return NV_MEMORY_UNCACHED; + } +#else + // Default to uncached for other platforms for now + return NV_MEMORY_UNCACHED; +#endif +} + +static NV_STATUS +RmDmabufVerifyMemHandle( + OBJGPU *pGpu, + NvHandle hSrcClient, + NvHandle hMemory, + NvU64 offset, + NvU64 size, + void *pGpuInstanceInfo, + MEMORY_DESCRIPTOR **ppMemDesc +) +{ + NV_STATUS status; + RsClient *pClient = NULL; + RsResourceRef *pSrcMemoryRef = NULL; + Memory *pSrcMemory = NULL; + MEMORY_DESCRIPTOR *pMemDesc = NULL; + + NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hSrcClient, &pClient)); + + status = clientGetResourceRef(pClient, hMemory, &pSrcMemoryRef); + if (status != NV_OK) + { + return status; + } + + pSrcMemory = dynamicCast(pSrcMemoryRef->pResource, Memory); + if (pSrcMemory == NULL) + { + return NV_ERR_INVALID_OBJECT; + } + + pMemDesc = pSrcMemory->pMemDesc; + if (pMemDesc == NULL) + { + return NV_ERR_INVALID_STATE; + } + + // + // We skip the partitionable heap check when the source memory is in + // sysmem as there is no valid heap (pHeap will be NULL). + // + if (pGpuInstanceInfo != NULL && memdescGetAddressSpace(pMemDesc) != ADDR_SYSMEM) + { + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance; + pKernelMIGGpuInstance = (KERNEL_MIG_GPU_INSTANCE *) pGpuInstanceInfo; + + if ((pKernelMIGGpuInstance->pMemoryPartitionHeap != pSrcMemory->pHeap)) + { + return NV_ERR_INVALID_OBJECT_PARENT; + } + } + + // Check if hMemory belongs to the same pGpu + if ((pMemDesc->pGpu != pGpu) || + (pSrcMemory->pGpu != pGpu)) + { + return NV_ERR_INVALID_OBJECT_PARENT; + } + + // Offset and size must be aligned to OS page-size + if (!NV_IS_ALIGNED64(offset, os_page_size) || + !NV_IS_ALIGNED64(size, os_page_size)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // Only supported for vidmem and sysmem(only for 0FB) handles + if ((memdescGetAddressSpace(pMemDesc) != ADDR_FBMEM) && + (!pGpu->pGpuArch->bGpuArchIsZeroFb)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if ((size == 0) || + (size > memdescGetSize(pMemDesc)) || + (offset > (memdescGetSize(pMemDesc) - size))) + { + return NV_ERR_INVALID_ARGUMENT; + } + + *ppMemDesc = pMemDesc; + + return NV_OK; +} + +static NV_STATUS +RmDmabufGetClientAndDevice( + OBJGPU *pGpu, + NvHandle hClient, + NvHandle hMemory, + NvU8 mappingType, + NvHandle *phClient, + NvHandle *phDevice, + NvHandle *phSubdevice, + void **ppGpuInstanceInfo +) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + // No dma-buf support for SLI-enabled GPU + if (IsSLIEnabled(pGpu)) + { + return NV_ERR_NOT_SUPPORTED; + } + + // + // MAPPING_TYPE_FORCE_PCIE is to be used only on coherent systems with a + // direct PCIe connection between the exporter and importer. + // MIG is not a supported use-case for dma-buf on these systems. + // + if (mappingType == NV_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE) + { + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) || + pKernelBus->bBar1Disabled || + IS_MIG_ENABLED(pGpu)) + { + return NV_ERR_NOT_SUPPORTED; + } + } + + if (IS_MIG_ENABLED(pGpu)) + { + MIG_INSTANCE_REF ref; + RsClient *pClient; + Memory *pMemory; + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + serverGetClientUnderLock(&g_resServ, hClient, &pClient)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + memGetByHandle(pClient, hMemory, &pMemory)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pMemory->pDevice, &ref)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kmigmgrIncRefCount(ref.pKernelMIGGpuInstance->pShare)); + + *phClient = ref.pKernelMIGGpuInstance->instanceHandles.hClient; + *phDevice = ref.pKernelMIGGpuInstance->instanceHandles.hDevice; + *phSubdevice = ref.pKernelMIGGpuInstance->instanceHandles.hSubdevice; + *ppGpuInstanceInfo = (void *) ref.pKernelMIGGpuInstance; + + return NV_OK; + } + + *phClient = pMemoryManager->hClient; + *phDevice = pMemoryManager->hDevice; + *phSubdevice = pMemoryManager->hSubdevice; + *ppGpuInstanceInfo = NULL; + + return NV_OK; +} + +static void +RmDmabufPutClientAndDevice( + OBJGPU *pGpu, + NvHandle hClient, + NvHandle hDevice, + NvHandle hSubdevice, + void *pGpuInstanceInfo +) +{ + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance; + + if (pGpuInstanceInfo == NULL) + { + return; + } + + pKernelMIGGpuInstance = (KERNEL_MIG_GPU_INSTANCE *) pGpuInstanceInfo; + + NV_ASSERT_OK(kmigmgrDecRefCount(pKernelMIGGpuInstance->pShare)); +} + +static NV_STATUS RmP2PDmaMapPages( + nv_state_t *pNv, + nv_dma_device_t *peer, + NvU64 pageSize, + NvU32 pageCount, + NvU64 *pDmaAddresses, + void **ppPriv +) +{ + NV_STATUS status; + NvU64 *pOsDmaAddresses = NULL; + NvU32 osPagesPerP2PPage, osPageCount, count; + NvBool bDmaMapped = NV_FALSE; + NvU32 i, j, index; + void *pgmap = NULL; + NvBool bPageMapRef = NV_FALSE; + + NV_ASSERT_OR_RETURN((pageSize >= os_page_size), NV_ERR_INVALID_ARGUMENT); + + if (pNv->coherent_gpu_mem_mode == NV_COHERENT_GPU_MEM_MODE_DRIVER) + { + // Take a refcount on the dev_pagemap created for GPU memory by UVM + pgmap = nv_dma_get_dev_pagemap(pDmaAddresses[0]); + if (pgmap == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to get a reference on dev_pagemap in CDMM(driver) mode\n"); + return NV_ERR_NOT_SUPPORTED; + } + + bPageMapRef = NV_TRUE; + } + + if (pageSize == os_page_size) + { + status = nv_dma_map_alloc(peer, pageCount, pDmaAddresses, NV_FALSE, NV_FALSE, ppPriv); + + goto put_pgmap; + } + + // + // If P2P page_size returned from nvidia_p2p_get_pages is bigger than + // OS page size, the page array need to be inflated to correctly do the DMA mapping. + // For example, if page_size = 64K and OS page size = 4K, + // there are 16 OS pages to this 64K P2P page. + // + + osPagesPerP2PPage = pageSize / os_page_size; + osPageCount = osPagesPerP2PPage * pageCount; + + status = os_alloc_mem((void **)&pOsDmaAddresses, + (osPageCount * sizeof(NvU64))); + if (status != NV_OK) + { + goto failed; + } + + index = 0; + for (i = 0; i < pageCount; i++) + { + pOsDmaAddresses[index] = pDmaAddresses[i]; + index++; + + for (j = 1; j < osPagesPerP2PPage; j++) + { + pOsDmaAddresses[index] = pOsDmaAddresses[index - 1] + os_page_size; + index++; + } + } + + status = nv_dma_map_alloc(peer, osPageCount, pOsDmaAddresses, NV_FALSE, NV_FALSE, ppPriv); + if (status != NV_OK) + { + goto failed; + } + bDmaMapped = NV_TRUE; + + // + // The driver breaks down the size into submaps and dma-maps those individually. + // This may result in non-contiguous IOVA segments allocated to each submap. + // We check for OS page contiguity within the bigger pageSize since we need to + // return IOVA chunks at pageSize granularity. + // + count = 0; + for (i = 1; i < osPageCount; i++) + { + count++; + if (count == osPagesPerP2PPage) + { + count = 0; + continue; + } + + if (pOsDmaAddresses[i] != (pOsDmaAddresses[i - 1] + os_page_size)) + { + status = NV_ERR_INVALID_STATE; + goto failed; + } + } + + // + // Fill pDmaAddresses at pageSize granularity + // from expanded pOsDmaAddresses. + // + index = 0; + for (i = 0; i < pageCount; i++) + { + pDmaAddresses[i] = pOsDmaAddresses[index]; + index += osPagesPerP2PPage; + } + + os_free_mem(pOsDmaAddresses); + + if (bPageMapRef) + { + nv_dma_put_dev_pagemap(pgmap); + } + + return NV_OK; + +failed: + if (bDmaMapped) + { + NV_ASSERT_OK(nv_dma_unmap_alloc(peer, osPageCount, + pOsDmaAddresses, ppPriv)); + } + + if (pOsDmaAddresses != NULL) + { + os_free_mem(pOsDmaAddresses); + } + +put_pgmap: + if (bPageMapRef) + { + nv_dma_put_dev_pagemap(pgmap); + } + + return status; +} + +/* + * --------------------------------------------------------------------------- + * + * The routines below are part of the interface between the kernel interface + * layer and the kernel-agnostic portions of the resource manager. + * + * --------------------------------------------------------------------------- + */ + +NvBool NV_API_CALL rm_init_private_state( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + NvBool retval; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + retval = RmInitPrivateState(pNv); + + NV_EXIT_RM_RUNTIME(sp,fp); + + return retval; +} + +void NV_API_CALL rm_free_private_state( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + RmFreePrivateState(pNv); + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NvBool NV_API_CALL rm_init_adapter( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + THREAD_STATE_NODE threadState; + NvBool retval = NV_FALSE; + void *fp; + NvBool bEnabled; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_DEVICE_INIT); + + // + // If GPU is driving any frame buffer console(vesafb, efifb etc) + // mark the console as client driven + // + pNv->client_managed_console = rm_get_uefi_console_status(pNv); + + // + // For GPU driving console, disable console access here, to ensure no console + // writes through BAR1 can interfere with physical RM's setup of BAR1 + // + if (pNv->client_managed_console && !pNv->sysmem_mapped_console) + { + os_disable_console_access(); + } + + // LOCK: acquire API lock + if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_INIT) == NV_OK) + { + if (!((gpumgrQueryGpuDrainState(pNv->gpu_id, &bEnabled, NULL) == NV_OK) + && bEnabled)) + { + if (pNv->flags & NV_FLAG_PERSISTENT_SW_STATE) + { + retval = RmPartiallyInitAdapter(pNv); + } + else + { + retval = RmInitAdapter(pNv); + } + } + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + if (pNv->client_managed_console && !pNv->sysmem_mapped_console) + { + os_enable_console_access(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return retval; +} + +void NV_API_CALL rm_disable_adapter( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + THREAD_STATE_NODE threadState; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_ASSERT_OK(os_flush_work_queue(pNv->queue, NV_TRUE)); + + if (pNv->client_managed_console && !pNv->sysmem_mapped_console) + { + os_disable_console_access(); + } + + // LOCK: acquire API lock + if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DESTROY) == NV_OK) + { + if (pNv->flags & NV_FLAG_PERSISTENT_SW_STATE) + { + RmPartiallyDisableAdapter(pNv); + } + else + { + RmDisableAdapter(pNv); + } + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + if (pNv->client_managed_console && !pNv->sysmem_mapped_console) + { + os_enable_console_access(); + } + + NV_ASSERT_OK(os_flush_work_queue(pNv->queue, NV_TRUE)); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +void NV_API_CALL rm_shutdown_adapter( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + THREAD_STATE_NODE threadState; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + if (pNv->client_managed_console && !pNv->sysmem_mapped_console) + { + os_disable_console_access(); + } + + // LOCK: acquire API lock + if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DESTROY) == NV_OK) + { + RmShutdownAdapter(pNv); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + if (pNv->client_managed_console && !pNv->sysmem_mapped_console) + { + os_enable_console_access(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NV_STATUS NV_API_CALL rm_exclude_adapter( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + NV_STATUS rmStatus; + THREAD_STATE_NODE threadState; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + rmStatus = RmExcludeAdapter(pNv); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_acquire_api_lock( + nvidia_stack_t *sp +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_release_api_lock( + nvidia_stack_t *sp +) +{ + THREAD_STATE_NODE threadState; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // UNLOCK: release API lock + rmapiLockRelease(); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return NV_OK; +} + +NV_STATUS NV_API_CALL rm_acquire_gpu_lock( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire GPU lock + rmStatus = rmDeviceGpuLocksAcquire(NV_GET_NV_PRIV_PGPU(nv), + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_OSAPI); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_release_gpu_lock( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + THREAD_STATE_NODE threadState; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // UNLOCK: release GPU lock + rmDeviceGpuLocksRelease(NV_GET_NV_PRIV_PGPU(nv), GPUS_LOCK_FLAGS_NONE, NULL); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return NV_OK; +} + +NV_STATUS NV_API_CALL rm_acquire_all_gpus_lock( + nvidia_stack_t *sp +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire all GPUs lock + rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_release_all_gpus_lock( + nvidia_stack_t *sp +) +{ + THREAD_STATE_NODE threadState; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // UNLOCK: release all GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return NV_OK; +} + +/*! + * @brief Handle ACPI_NOTIFY_GPS_STATUS_CHANGE event. + * + * This function is called for GPS when SBIOS trigger + * gps STATUS_CHANGE event, which calls rm control call + * NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL to init the GPS + * data from SBIOS. + */ +static void RmHandleGPSStatusChange +( + nv_state_t *pNv +) +{ + NV_STATUS rmStatus; + RM_API *pRmApi; + THREAD_STATE_NODE threadState; + NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS gpsControl = { 0 }; + + pRmApi = RmUnixRmApiPrologue(pNv, &threadState, RM_LOCK_MODULES_ACPI); + if (pRmApi == NULL) + { + return; + } + + gpsControl.command = NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK; + gpsControl.locale = NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_SYSTEM; + + // + // NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL is not a subdevice command. + // But, Inside GPS module, the first GPU, which has GPS + // enabled will be grabbed with GPU manager. The RMAPI_API_LOCK_INTERNAL + // will internally grab the GPU locks and wake-up all the GPUs. Ideally + // this control call should be GPU specific command, if internally + // it uses the GPU. + // + rmStatus = pRmApi->Control(pRmApi, + pNv->rmapi.hClient, + pNv->rmapi.hClient, + NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL, + (void *)&gpsControl, + sizeof(NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS)); + + RmUnixRmApiEpilogue(pNv, &threadState); + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s: Failed to handle ACPI GPS status change event, status=0x%x\n", + __FUNCTION__, rmStatus); + } +} + +/*! + * @brief Function to handle device specific ACPI events. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + * @param[in] event_type NvU32 Event type. + */ +void NV_API_CALL rm_acpi_notify( + nvidia_stack_t *sp, + nv_state_t *nv, + NvU32 event_type +) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + + switch (event_type) + { + case ACPI_VIDEO_NOTIFY_PROBE: + { + THREAD_STATE_NODE threadState; + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + RmHandleDisplayChange(sp, nv); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + break; + } + + case ACPI_NOTIFY_GPS_STATUS_CHANGE: + RmHandleGPSStatusChange(nv); + break; + + case ACPI_NOTIFY_POWER_LEVEL_D1: /* fallthrough */ + case ACPI_NOTIFY_POWER_LEVEL_D2: /* fallthrough */ + case ACPI_NOTIFY_POWER_LEVEL_D3: /* fallthrough */ + case ACPI_NOTIFY_POWER_LEVEL_D4: /* fallthrough */ + case ACPI_NOTIFY_POWER_LEVEL_D5: + RmHandleDNotifierEvent(nv, event_type); + break; + + default: + NV_PRINTF(LEVEL_INFO, "No support for 0x%x event\n", event_type); + NV_ASSERT(0); + break; + } + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +static void nv_align_mmap_offset_length( + nv_usermap_access_params_t *nvuap) +{ + NvU64 page_size = os_page_size; + NvU64 end = nvuap->size + (nvuap->addr & (page_size - 1)); + + nvuap->memArea.numRanges = 1; + nvuap->memArea.pRanges[0].start = NV_ALIGN_DOWN(nvuap->addr, page_size); + nvuap->memArea.pRanges[0].size = NV_ALIGN_UP(end, page_size); + nvuap->offset = NV_ALIGN_DOWN(nvuap->offset, page_size); +} + +static inline NV_STATUS RmGetArrayMinMax( + NvU64 *array, + NvU64 count, + NvU64 *min, + NvU64 *max +) +{ + NvU64 i; + + if (array == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + *min = array[0]; + *max = array[0]; + + if (count == 1) + return NV_OK; + + for (i = 1; i < count; i++) + { + if (array[i] > *max) + *max = array[i]; + + if (array[i] < *min) + *min = array[i]; + } + + return NV_OK; +} + +static NV_STATUS RmGetAllocPrivate(RmClient *, NvU32, NvU64, NvU64, NvU32 *, void **, + NvU64 *); + +static NV_STATUS RmValidateMmapRequest( + nv_state_t *pNv, + NvU64 offset, + NvU64 length, + NvU32 *pProtection +) +{ + NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS params = { 0 }; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NV_STATUS status; + + if (osIsAdministrator()) + { + *pProtection = NV_PROTECT_READ_WRITE; + return NV_OK; + } + + params.addressStart = offset; + params.addressLength = length; + + status = pRmApi->Control(pRmApi, pNv->rmapi.hClient, + pNv->rmapi.hSubDevice, + NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST, + ¶ms, sizeof(params)); + + if (status == NV_OK) + { + *pProtection = params.protection; + } + + return status; +} + +static NV_STATUS RmSetUserMapAccessRange( + nv_usermap_access_params_t *nvuap +) +{ + NV_STATUS status = NV_OK; + + if (nvuap->contig) + { + nvuap->access_start = nvuap->memArea.pRanges[0].start; + nvuap->access_size = nvuap->memArea.pRanges[0].size; + } + else + { + NvU64 highest_address_mapped; + NvU64 lowest_address_mapped; + + status = RmGetArrayMinMax(nvuap->page_array, nvuap->num_pages, + &lowest_address_mapped, + &highest_address_mapped); + if (status != NV_OK) + { + return status; + } + + nvuap->access_start = lowest_address_mapped; + nvuap->access_size = (highest_address_mapped + os_page_size) - lowest_address_mapped; + } + + return status; +} + +static NV_STATUS RmGetMmapPteArray( + KernelMemorySystem *pKernelMemorySystem, + RsClient *pClient, + NvHandle hMemory, + nv_usermap_access_params_t *nvuap +) +{ + NV_STATUS status = NV_OK; + NvU64 pages = 0; + Memory *pMemory = NULL; + PMEMORY_DESCRIPTOR pMemDesc = NULL; + RsResourceRef *pResourceRef; + NvU64 i; + NvU64 *pteArray; + NvU64 index; + + if (nvuap == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // + // If we're mapping a memory handle, we can get the data from the + // descriptor (required if the allocation being mapped is discontiguous). + // + if (clientGetResourceRef(pClient, hMemory, &pResourceRef) == NV_OK) + { + pMemory = dynamicCast(pResourceRef->pResource, Memory); + if (pMemory != NULL) + { + pMemDesc = pMemory->pMemDesc; + nvuap->contig = memdescGetContiguity(pMemDesc, AT_CPU); + } + } + + // + // In the discontiguous case, the page array needs to be large enough to hold + // the 4K-page-sized addresses that we will then deflate to OS page addresses. + // For the contiguous case, we can create the OS-page-sized addresses + // directly in the array. + // + if (nvuap->contig) + { + pages = nvuap->memArea.pRanges[0].size / os_page_size; + } + else + { + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc)) + { + pages = nvuap->memArea.pRanges[0].size / NV_MIN(os_page_size, pMemDesc->pageArrayGranularity); + } + else + { + pages = nvuap->memArea.pRanges[0].size / NV_RM_PAGE_SIZE; + } + } + + NV_ASSERT_OR_RETURN(pages != 0, NV_ERR_INVALID_ARGUMENT); + + status = os_alloc_mem((void **)&nvuap->page_array, (pages * sizeof(NvU64))); + if (status != NV_OK) + { + return status; + } + + if (!nvuap->contig) + { + pteArray = memdescGetPteArray(pMemDesc, AT_CPU); + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc)) + { + index = nvuap->offset / NV_MIN(os_page_size, pMemDesc->pageArrayGranularity); + } + else + { + index = nvuap->offset / NV_RM_PAGE_SIZE; + } + + // + // We're guaranteed to have a MEMORY_DESCRIPTOR in the discontiguous + // case. Copy over the addresses now. + // + NvU64 copyByteSize = NV_MIN(pages, pMemDesc->pageArraySize) * sizeof(NvU64); + portMemCopy((void *)nvuap->page_array, + copyByteSize, (void *)&pteArray[index], + copyByteSize); + + if (!IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc)) + { + if (NV_RM_PAGE_SIZE < os_page_size) + { + RmDeflateRmToOsPageArray(nvuap->page_array, pages); + pages = NV_RM_PAGES_TO_OS_PAGES(pages); + } + } + else + { + // + // Because of PMA case, we need to convert page array + // from RM native granularity to OS granularity. + // + convertPageArrayBetweenOsAndRm( + nvuap->page_array, + nvuap->memArea.pRanges[0].size / pMemDesc->pageArrayGranularity, + pMemDesc->pageArrayGranularity, + nvuap->memArea.pRanges[0].size / os_page_size, + os_page_size, + &pages + ); + } + + // + // Convert the GPU physical addresses to system physical addresses, + // if applicable. + // + for (i = 0; i < pages; i++) + { + nvuap->page_array[i] += pKernelMemorySystem->coherentCpuFbBase; + } + } + else + { + // Offset is accounted in nvuap->memArea.pRanges[0].start. + for (nvuap->page_array[0] = nvuap->memArea.pRanges[0].start, i = 1; + i < pages; i++) + { + nvuap->page_array[i] = nvuap->page_array[i-1] + os_page_size; + } + } + + nvuap->num_pages = pages; + + return status; +} + +/* Must be called with the API lock and the GPU locks */ +static NV_STATUS RmCreateMmapContextLocked( + RmClient *pRmClient, + NvHandle hDevice, + NvHandle hMemory, + NvP64 address, + NvU64 size, + NvU64 offset, + NvU32 cachingType, + NvU32 fd +) +{ + NV_STATUS status = NV_OK; + void *pAllocPriv = NULL; + OBJGPU *pGpu = NULL; + RsClient *pClient = staticCast(pRmClient, RsClient); + KernelMemorySystem *pKernelMemorySystem = NULL; + NvBool bCoherentAtsCpuOffset = NV_FALSE; + NvBool bHostCoherentFbOffset = NV_FALSE; + nv_state_t *pNv = NULL; + NvU64 addr = (NvU64)address; + NvU32 prot = 0; + NvU64 pageIndex = 0; + nv_usermap_access_params_t *nvuap = NULL; + NvBool bClientMap = (pClient->hClient == hDevice); + + if (!bClientMap) + { + if (CliSetGpuContext(pClient->hClient, hDevice, &pGpu, NULL) != NV_OK) + { + Subdevice *pSubdevice; + + status = subdeviceGetByHandle(pClient, hDevice, &pSubdevice); + if (status != NV_OK) + return status; + + pGpu = GPU_RES_GET_GPU(pSubdevice); + + GPU_RES_SET_THREAD_BC_STATE(pSubdevice); + } + } + nvuap = tlsEntryGet(TLS_ENTRY_ID_MAPPING_CONTEXT); + if (nvuap != NULL) + { + NV_ASSERT(tlsEntryRelease(TLS_ENTRY_ID_MAPPING_CONTEXT) == 0); + prot = NV_PROTECT_READ_WRITE; + // + // TODO: Add this to the mapping context so we don't need to do gymnastics + // to figure out what the correct pNv is + // + pNv = NV_GET_NV_STATE(pGpu); + goto add_ctx_to_file; + } + + NV_ASSERT_OK_OR_RETURN(os_alloc_mem((void**)&nvuap, sizeof(nv_usermap_access_params_t))); + portMemSet(nvuap, 0, sizeof(nv_usermap_access_params_t)); + + NV_ASSERT_OK_OR_GOTO(status, os_alloc_mem((void**)&(nvuap->memArea.pRanges), sizeof(MemoryRange)), free_nvuap); + + nvuap->addr = addr; + nvuap->size = size; + nvuap->offset = offset; + nvuap->caching = cachingType; + + // + // Assume the allocation is contiguous until RmGetMmapPteArray + // determines otherwise. + // + nvuap->contig = NV_TRUE; + nv_align_mmap_offset_length(nvuap); + + if (pGpu != NULL) + { + pNv = NV_GET_NV_STATE(pGpu); + pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + bCoherentAtsCpuOffset = IS_COHERENT_CPU_ATS_OFFSET(pGpu, pKernelMemorySystem, addr, size); + bHostCoherentFbOffset = !bCoherentAtsCpuOffset && + IS_COHERENT_FB_OFFSET(pGpu, pKernelMemorySystem, addr, size); + } + // + // If no device is given, or the address isn't in the given device's BARs, + // validate this as a system memory mapping and associate it with the + // control device. + // + if ((pNv == NULL) || + (!IS_REG_OFFSET(pNv, addr, size) && + !IS_FB_OFFSET(pNv, addr, size) && + !(bCoherentAtsCpuOffset || bHostCoherentFbOffset) && + !IS_IMEM_OFFSET(pNv, addr, size))) + { + pNv = nv_get_ctl_state(); + + // + // Validate the mapping request by looking up the underlying sysmem + // allocation. + // + status = RmGetAllocPrivate(pRmClient, hMemory, addr, size, &prot, &pAllocPriv, + &pageIndex); + + if (status != NV_OK) + { + goto done; + } + } + else + { + // + // Validate the mapping request for ATS and get pteArray + // + if (bCoherentAtsCpuOffset) + { + status = RmGetMmapPteArray(pKernelMemorySystem, pClient, hMemory, nvuap); + if (status != NV_OK) + { + goto done; + } + } + else if (bHostCoherentFbOffset) + { + status = RmGetMmapPteArray(pKernelMemorySystem, pClient, hMemory, nvuap); + if (status != NV_OK) + { + goto done; + } + + // + // nvuap->page_array(allocated in RmGetMmapPteArray) is not assigned + // to nvamc->page_array if onlining status is false(which is the case with + // bHostCoherentFbOffset) and so doesn't get freed if not done here. + // The call to RmGetMmapPteArray is for getting the contig and num + // pages of the allocation. + // + os_free_mem(nvuap->page_array); + nvuap->page_array = NULL; + } + + NV_ASSERT_OK_OR_GOTO(status, RmSetUserMapAccessRange(nvuap), done); + + // Validate the mapping request for BAR's. + status = RmValidateMmapRequest(pNv, nvuap->access_start, + nvuap->access_size, &prot); + if (status != NV_OK) + { + goto done; + } + } + +add_ctx_to_file: + status = nv_add_mapping_context_to_file(pNv, nvuap, prot, pAllocPriv, + pageIndex, fd); + +done: + os_free_mem(nvuap->memArea.pRanges); +free_nvuap: + os_free_mem(nvuap); + return status; +} + +// TODO: Bug 1802250: [uvm8] Use an alt stack in all functions in unix/src/osapi.c +NV_STATUS rm_create_mmap_context( + NvHandle hClient, + NvHandle hDevice, + NvHandle hMemory, + NvP64 address, + NvU64 size, + NvU64 offset, + NvU32 cachingType, + NvU32 fd +) +{ + NV_STATUS rmStatus = NV_OK; + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_OSAPI)) == NV_OK) + { + CLIENT_ENTRY *pClientEntry; + RmClient *pRmClient; + + if (NV_OK != serverutilAcquireClient(hClient, LOCK_ACCESS_READ, &pClientEntry, + &pRmClient)) + { + // UNLOCK: release API lock + rmapiLockRelease(); + return NV_ERR_INVALID_CLIENT; + } + + if (pRmClient->ProcID != osGetCurrentProcess()) + { + rmStatus = NV_ERR_INVALID_CLIENT; + } + // LOCK: acquire GPUs lock + else if ((rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI)) == NV_OK) + { + rmStatus = RmCreateMmapContextLocked(pRmClient, hDevice, + hMemory, address, size, offset, + cachingType, fd); + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + + serverutilReleaseClient(LOCK_ACCESS_READ, pClientEntry); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + return rmStatus; +} + +static NV_STATUS RmGetAllocPrivate( + RmClient *pRmClient, + NvU32 hMemory, + NvU64 offset, + NvU64 length, + NvU32 *pProtection, + void **ppPrivate, + NvU64 *pPageIndex +) +{ + NV_STATUS rmStatus; + PMEMORY_DESCRIPTOR pMemDesc; + NvU32 pageOffset; + NvU64 pageCount; + NvU64 endingOffset; + RsResourceRef *pResourceRef; + RmResource *pRmResource; + void *pMemData; + NvBool bPeerIoMem; + NvBool bReadOnlyMem; + *pProtection = NV_PROTECT_READ_WRITE; + *ppPrivate = NULL; + + pageOffset = (offset & ~os_page_mask); + offset &= os_page_mask; + + NV_ASSERT_OR_RETURN(rmapiLockIsOwner(), NV_ERR_INVALID_LOCK_STATE); + + rmStatus = clientGetResourceRef(staticCast(pRmClient, RsClient), + hMemory, &pResourceRef); + if (rmStatus != NV_OK) + goto done; + + pRmResource = dynamicCast(pResourceRef->pResource, RmResource); + if (!pRmResource) + { + rmStatus = NV_ERR_INVALID_OBJECT; + goto done; + } + + rmStatus = rmresGetMemoryMappingDescriptor(pRmResource, &pMemDesc); + if (rmStatus != NV_OK) + goto done; + + bReadOnlyMem = memdescGetFlag(pMemDesc, MEMDESC_FLAGS_USER_READ_ONLY); + bPeerIoMem = memdescGetFlag(pMemDesc, MEMDESC_FLAGS_PEER_IO_MEM); + + if (!(pMemDesc->Allocated || bPeerIoMem || + memdescIsCarveoutMemory(pMemDesc) || + (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOW_EXT_SYSMEM_USER_CPU_MAPPING)))) + { + NV_PRINTF(LEVEL_ERROR, "Mmap is not allowed\n"); + rmStatus = NV_ERR_OBJECT_NOT_FOUND; + goto done; + } + + switch (memdescGetAddressSpace(pMemDesc)) + { + case ADDR_SYSMEM: + break; + default: + rmStatus = NV_ERR_OBJECT_NOT_FOUND; + goto done; + } + + pMemData = memdescGetMemData(pMemDesc); + if (pMemData == NULL) + { + rmStatus = NV_ERR_OBJECT_NOT_FOUND; + goto done; + } + + rmStatus = os_match_mmap_offset(pMemData, offset, pPageIndex); + if (rmStatus != NV_OK) + goto done; + + if (!portSafeAddU64(pageOffset, length, &endingOffset)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + pageCount = (endingOffset / os_page_size); + + if (!portSafeAddU64(*pPageIndex + ((endingOffset % os_page_size) ? 1 : 0), + pageCount, &pageCount)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc)) + { + NV_ASSERT_OR_ELSE(pageCount <= pMemDesc->PageCount, rmStatus = NV_ERR_INVALID_ARGUMENT; goto done); + } + else if (pageCount > NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + if (bReadOnlyMem) + *pProtection = NV_PROTECT_READABLE; + + *ppPrivate = pMemData; + +done: + return rmStatus; +} + +NV_STATUS rm_get_adapter_status( + nv_state_t *pNv, + NvU32 *pStatus +) +{ + NV_STATUS rmStatus = NV_ERR_OPERATING_SYSTEM; + + // LOCK: acquire API lock + if (rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_OSAPI) == NV_OK) + { + rmStatus = RmGetAdapterStatus(pNv, pStatus); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_get_adapter_status_external( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + if (rm_get_adapter_status(pNv, &rmStatus) != NV_OK) + { + rmStatus = NV_ERR_OPERATING_SYSTEM; + } + + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NvBool NV_API_CALL rm_init_rm( + nvidia_stack_t *sp +) +{ + NvBool retval; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + retval = RmInitRm(); + + NV_EXIT_RM_RUNTIME(sp,fp); + + return retval; +} + +void NV_API_CALL rm_shutdown_rm( + nvidia_stack_t *sp +) +{ + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + RmShutdownRm(); + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NvBool NV_API_CALL rm_init_event_locks( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + void *fp; + NvBool ret; + + NV_ENTER_RM_RUNTIME(sp,fp); + + pNv->event_spinlock = portSyncSpinlockCreate(portMemAllocatorGetGlobalNonPaged()); + ret = (pNv->event_spinlock != NULL); + + NV_EXIT_RM_RUNTIME(sp,fp); + return ret; +} + +void NV_API_CALL rm_destroy_event_locks( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + if (pNv && pNv->event_spinlock) + portSyncSpinlockDestroy(pNv->event_spinlock); + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NV_STATUS NV_API_CALL rm_stop_user_channels( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS params = { 0 }; + RM_API *pRmApi; + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_ERR_INVALID_STATE; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + pRmApi = RmUnixRmApiPrologue(pNv, &threadState, RM_LOCK_MODULES_FIFO); + if (pRmApi != NULL) + { + params.bDisable = NV_TRUE; + rmStatus = pRmApi->Control(pRmApi, pNv->rmapi.hClient, + pNv->rmapi.hSubDevice, + NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS, + ¶ms, sizeof(params)); + + RmUnixRmApiEpilogue(pNv, &threadState); + } + + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_restart_user_channels( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS params = { 0 }; + RM_API *pRmApi; + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_ERR_INVALID_STATE; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + pRmApi = RmUnixRmApiPrologue(pNv, &threadState, RM_LOCK_MODULES_FIFO); + if (pRmApi != NULL) + { + params.bDisable = NV_FALSE; + rmStatus = pRmApi->Control(pRmApi, pNv->rmapi.hClient, pNv->rmapi.hSubDevice, + NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS, + ¶ms, sizeof(params)); + + RmUnixRmApiEpilogue(pNv, &threadState); + } + + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +// +// Use this call to check if the chipset is io coherent +// +NvBool NV_API_CALL rm_is_chipset_io_coherent( + nvidia_stack_t *sp) +{ + void *fp; + OBJSYS *pSys; + OBJCL *pCl; + NvBool bIoCoherent = NV_FALSE; + + NV_ENTER_RM_RUNTIME(sp,fp); + + pSys = SYS_GET_INSTANCE(); + pCl = SYS_GET_CL(pSys); + if (pCl == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "%s: no CL object found, setting io coherent by default\n", + __FUNCTION__); + goto done; + } + + bIoCoherent = pCl->getProperty(pCl, PDB_PROP_CL_IS_CHIPSET_IO_COHERENT); + +done: + NV_EXIT_RM_RUNTIME(sp,fp); + + return bIoCoherent; +} + +NV_STATUS NV_API_CALL rm_validate_ioctls( + NvU32 command, + NvU32 dataSize +) +{ + size_t arg_size = dataSize; + int arg_cmd = (command & 0xFF); + int i; + NV_STATUS status; + static const struct { + unsigned int cmdKey; + size_t paramSize; + } rm_ioctls_table[] = { + #define _RM_IOCTL_ENTRY(_cmd, _type) \ + { .cmdKey = ((_cmd) & 0xFF), .paramSize = sizeof(_type),} + /*rm_ioctls */ + _RM_IOCTL_ENTRY(NV_ESC_ALLOC_OS_EVENT, nv_ioctl_alloc_os_event_t), + _RM_IOCTL_ENTRY(NV_ESC_FREE_OS_EVENT, nv_ioctl_free_os_event_t), + _RM_IOCTL_ENTRY(NV_ESC_RM_GET_EVENT_DATA, NVOS41_PARAMETERS), + }; + + status = RmValidateIoctl(command, dataSize); + if (status != NV_ERR_INVALID_COMMAND) + { + return status; + } + + for (i = 0; i < NV_ARRAY_ELEMENTS(rm_ioctls_table); ++i) + { + if (arg_cmd == rm_ioctls_table[i].cmdKey) + { + if (arg_size == rm_ioctls_table[i].paramSize) + { + return NV_OK; + } + nv_printf(NV_DBG_ERRORS, "NVRM: invalid %d structure size, expected %d, got %d!\n", + rm_ioctls_table[i].cmdKey, rm_ioctls_table[i].paramSize, arg_size); + + return NV_ERR_INVALID_ARGUMENT; + } + } + // Unknown IOCTL case. Not found in any rm and RM Tables. + return NV_ERR_INVALID_COMMAND; +} + +NV_STATUS NV_API_CALL rm_ioctl( + nvidia_stack_t *sp, + nv_state_t *pNv, + nv_file_private_t *nvfp, + NvU32 Command, + void *pData, + NvU32 dataSize +) +{ + NV_STATUS rmStatus = NV_OK; + THREAD_STATE_NODE threadState; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + // + // Some ioctls are handled entirely inside the OS layer and don't need to + // suffer the overhead of calling into RM core. + // + switch (Command) + { + case NV_ESC_ALLOC_OS_EVENT: + { + nv_ioctl_alloc_os_event_t *pApi = pData; + + if (dataSize != sizeof(nv_ioctl_alloc_os_event_t)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + break; + } + + pApi->Status = allocate_os_event(pApi->hClient, nvfp, pApi->fd); + break; + } + case NV_ESC_FREE_OS_EVENT: + { + nv_ioctl_free_os_event_t *pApi = pData; + + if (dataSize != sizeof(nv_ioctl_free_os_event_t)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + break; + } + + pApi->Status = free_os_event(pApi->hClient, pApi->fd); + break; + } + case NV_ESC_RM_GET_EVENT_DATA: + { + NVOS41_PARAMETERS *pApi = pData; + + if (dataSize != sizeof(NVOS41_PARAMETERS)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + break; + } + + pApi->status = get_os_event_data(nvfp, + pApi->pEvent, + &pApi->MoreEvents); + break; + } + default: + { + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + rmStatus = RmIoctl(pNv, nvfp, Command, pData, dataSize); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + break; + } + } + + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +static void _deferredClientListFreeCallback(void *unused) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + NV_STATUS status = serverFreeDisabledClients(&g_resServ, 0, pSys->clientListDeferredFreeLimit); + // + // Possible return values: + // NV_WARN_MORE_PROCESSING_REQUIRED - Iteration limit reached, need to call again + // NV_ERR_IN_USE - Already running on another thread, try again later + // In both cases, schedule a worker to clean up anything that remains + // + if (status != NV_OK) + { + status = osQueueSystemWorkItem(_deferredClientListFreeCallback, unused); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_NOTICE, "Failed to schedule deferred free callback. Freeing immediately.\n"); + serverFreeDisabledClients(&g_resServ, 0, 0); + } + } +} + +void NV_API_CALL rm_cleanup_file_private( + nvidia_stack_t *sp, + nv_state_t *pNv, + nv_file_private_t *nvfp +) +{ + THREAD_STATE_NODE threadState; + void *fp; + RM_API *pRmApi; + RM_API_CONTEXT rmApiContext = {0}; + NvU32 i; + OBJSYS *pSys = SYS_GET_INSTANCE(); + + NV_ENTER_RM_RUNTIME(sp,fp); + + // + // Skip cleaning up this fd if: + // - no RMAPI clients and events were ever allocated on this fd + // - no RMAPI object handles were exported on this fd + // Access nvfp->handles without locking as fd cleanup is synchronised by the kernel + // + if (!nvfp->bCleanupRmapi && nvfp->handles == NULL) + goto done; + + pRmApi = rmapiGetInterface(RMAPI_EXTERNAL); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + threadStateSetTimeoutOverride(&threadState, 10 * 1000); + + if (rmapiPrologue(pRmApi, &rmApiContext) != NV_OK) { + NV_EXIT_RM_RUNTIME(sp,fp); + return; + } + + // LOCK: acquire API lock. Low priority so cleanup doesn't block active threads + if (rmapiLockAcquire(RMAPI_LOCK_FLAGS_LOW_PRIORITY, RM_LOCK_MODULES_OSAPI) == NV_OK) + { + // Unref any object which was exported on this file. + if (nvfp->handles != NULL) + { + for (i = 0; i < nvfp->maxHandles; i++) + { + if (nvfp->handles[i] == 0) + { + continue; + } + + RmFreeObjExportHandle(nvfp->handles[i]); + nvfp->handles[i] = 0; + } + + os_free_mem(nvfp->handles); + nvfp->handles = NULL; + nvfp->maxHandles = 0; + } + + // Disable any RM clients associated with this file. + RmFreeUnusedClients(pNv, nvfp); + + // Unless configured otherwise, immediately free all disabled clients + if (!pSys->bUseDeferredClientListFree) + serverFreeDisabledClients(&g_resServ, RM_LOCK_STATES_API_LOCK_ACQUIRED, 0); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + // Start the deferred free callback if necessary + if (pSys->bUseDeferredClientListFree) + _deferredClientListFreeCallback(NULL); + + rmapiEpilogue(pRmApi, &rmApiContext); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + +done: + if (nvfp->ctl_nvfp != NULL) + { + nv_put_file_private(nvfp->ctl_nvfp_priv); + nvfp->ctl_nvfp = NULL; + nvfp->ctl_nvfp_priv = NULL; + } + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +void NV_API_CALL rm_unbind_lock( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + THREAD_STATE_NODE threadState; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI) == NV_OK) + { + RmUnbindLock(pNv); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NV_STATUS NV_API_CALL rm_read_registry_dword( + nvidia_stack_t *sp, + nv_state_t *nv, + const char *regParmStr, + NvU32 *Data +) +{ + OBJGPU *pGpu = NULL; + NV_STATUS RmStatus; + void *fp; + NvBool isApiLockTaken = NV_FALSE; + + NV_ENTER_RM_RUNTIME(sp,fp); + + // + // We can be called from different contexts: + // + // 1) early initialization without device state. + // 2) from outside the RM API (without the lock held) + // + // In context 1)the API lock is not needed and + // in context 2), it needs to be acquired. + // + if (nv != NULL) + { + // LOCK: acquire API lock + if ((RmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_OSAPI)) != NV_OK) + { + NV_EXIT_RM_RUNTIME(sp,fp); + return RmStatus; + } + + isApiLockTaken = NV_TRUE; + } + + pGpu = NV_GET_NV_PRIV_PGPU(nv); + + // Skipping the NULL check as osReadRegistryDword takes care of it. + RmStatus = osReadRegistryDword(pGpu, regParmStr, Data); + + if (isApiLockTaken == NV_TRUE) + { + // UNLOCK: release API lock + rmapiLockRelease(); + } + + NV_EXIT_RM_RUNTIME(sp,fp); + + return RmStatus; +} + +NV_STATUS NV_API_CALL rm_write_registry_dword( + nvidia_stack_t *sp, + nv_state_t *nv, + const char *regParmStr, + NvU32 Data +) +{ + NV_STATUS RmStatus; + void *fp; + NvBool isApiLockTaken = NV_FALSE; + + NV_ENTER_RM_RUNTIME(sp,fp); + + if (nv != NULL) + { + // LOCK: acquire API lock + if ((RmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI)) != NV_OK) + { + NV_EXIT_RM_RUNTIME(sp,fp); + return RmStatus; + } + + isApiLockTaken = NV_TRUE; + } + + RmStatus = RmWriteRegistryDword(nv, regParmStr, Data); + + if (isApiLockTaken == NV_TRUE) + { + // UNLOCK: release API lock + rmapiLockRelease(); + } + + NV_EXIT_RM_RUNTIME(sp,fp); + + return RmStatus; +} + +NV_STATUS NV_API_CALL rm_write_registry_binary( + nvidia_stack_t *sp, + nv_state_t *nv, + const char *regParmStr, + NvU8 *Data, + NvU32 cbLen +) +{ + NV_STATUS RmStatus; + void *fp; + NvBool isApiLockTaken = NV_FALSE; + + NV_ENTER_RM_RUNTIME(sp,fp); + + if (nv != NULL) + { + // LOCK: acquire API lock + if ((RmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI)) != NV_OK) + { + NV_EXIT_RM_RUNTIME(sp,fp); + return RmStatus; + } + + isApiLockTaken = NV_TRUE; + } + + RmStatus = RmWriteRegistryBinary(nv, regParmStr, Data, cbLen); + + if (isApiLockTaken == NV_TRUE) + { + // UNLOCK: release API lock + rmapiLockRelease(); + } + + NV_EXIT_RM_RUNTIME(sp,fp); + + return RmStatus; +} + +NV_STATUS NV_API_CALL rm_write_registry_string( + nvidia_stack_t *sp, + nv_state_t *nv, + const char *regParmStr, + const char *string, + NvU32 stringLength +) +{ + NV_STATUS rmStatus; + void *fp; + NvBool isApiLockTaken = NV_FALSE; + + NV_ENTER_RM_RUNTIME(sp,fp); + + if (nv != NULL) + { + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI)) != NV_OK) + { + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; + } + + isApiLockTaken = NV_TRUE; + } + + rmStatus = RmWriteRegistryString(nv, regParmStr, string, (stringLength + 1)); + + if (isApiLockTaken == NV_TRUE) + { + // UNLOCK: release API lock + rmapiLockRelease(); + } + + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +static NvBool NV_API_CALL rm_is_space(const char ch) +{ + // + // return true if it is a: + // ' ' : (space - decimal 32.) + // '\t' : (TAB - decimal 9) + // 'LF' : (Line feed, new line - decimal 10) + // 'VT' : (Vertical TAB - decimal 11) + // 'FF' : (Form feed, new page - decimal 12) + // '\r' : (carriage return - decimal 13) + // + return ((ch == ' ') || ((ch >= '\t') && (ch <= '\r'))); +} + +char* NV_API_CALL rm_remove_spaces(const char *in) +{ + unsigned int len = os_string_length(in) + 1; + const char *in_ptr; + char *out, *out_ptr; + + if (os_alloc_mem((void **)&out, len) != NV_OK) + return NULL; + + in_ptr = in; + out_ptr = out; + + while (*in_ptr != '\0') + { + if (!rm_is_space(*in_ptr)) + *out_ptr++ = *in_ptr; + in_ptr++; + } + *out_ptr = '\0'; + + return out; +} + +char* NV_API_CALL rm_string_token(char **strp, const char delim) +{ + char *s, *token; + + if ((strp == NULL) || (*strp == NULL)) + return NULL; + + s = token = *strp; + *strp = NULL; + + for (; *s != '\0'; s++) { + if (*s == delim) { + *s = '\0'; + *strp = ++s; + break; + } + } + + return token; +} + +// Parse string passed in NVRM as module parameter. +void NV_API_CALL rm_parse_option_string(nvidia_stack_t *sp, const char *nvRegistryDwords) +{ + unsigned int i; + nv_parm_t *entry; + char *option_string = NULL; + char *ptr, *token; + char *name, *value; + NvU32 data; + + if (nvRegistryDwords != NULL) + { + if ((option_string = rm_remove_spaces(nvRegistryDwords)) == NULL) + { + return; + } + + ptr = option_string; + + while ((token = rm_string_token(&ptr, ';')) != NULL) + { + if (!(name = rm_string_token(&token, '=')) || !os_string_length(name)) + { + continue; + } + + if (!(value = rm_string_token(&token, '=')) || !os_string_length(value)) + { + continue; + } + + if (rm_string_token(&token, '=') != NULL) + { + continue; + } + + data = os_strtoul(value, NULL, 0); + + for (i = 0; (entry = &nv_parms[i])->name != NULL; i++) + { + if (os_string_compare(entry->name, name) == 0) + break; + } + + if (!entry->name) + rm_write_registry_dword(sp, NULL, name, data); + else + *entry->data = data; + } + + // Free the memory allocated by rm_remove_spaces() + os_free_mem(option_string); + } +} + +NV_STATUS NV_API_CALL rm_run_rc_callback( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + OBJGPU *pGpu; + void *fp; + + /* make sure our timer's not still running when it shouldn't be */ + if (nv == NULL) + return NV_ERR_GENERIC; + + pGpu = NV_GET_NV_PRIV_PGPU(nv); + if (pGpu == NULL) + return NV_ERR_GENERIC; + + if (nv->rc_timer_enabled == 0) + return NV_ERR_GENERIC; + + if (!FULL_GPU_SANITY_CHECK(pGpu)) + { + return NV_ERR_GENERIC; + } + + NV_ENTER_RM_RUNTIME(sp,fp); + + osRun1HzCallbacksNow(pGpu); + + NV_EXIT_RM_RUNTIME(sp,fp); + + return NV_OK; +} + +static void _tmrEventServiceTimerWorkItem +( + NvU32 gpuInstance, + void *pArgs +) +{ + OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); + NV_STATUS status = NV_OK; + + status = tmrEventServiceTimer(pGpu, pTmr, (TMR_EVENT *)pArgs); + + if (status != NV_OK) + NV_PRINTF(LEVEL_ERROR, "Timer event failed from OS timer callback workitem with status :0x%x\n", status); +} + +static NV_STATUS RmRunNanoTimerCallback( + OBJGPU *pGpu, + void *pTmrEvent +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS status = NV_OK; + + threadStateInitISRAndDeferredIntHandler(&threadState, pGpu, + THREAD_STATE_FLAGS_IS_DEFERRED_INT_HANDLER); + + // + // OS timers come in ISR context, hence schedule workitem for timer event service. + // GPU timer events are also handled in same mammer allowing us to have same functionality + // for callback functions. + // + status = osQueueWorkItem(pGpu, + _tmrEventServiceTimerWorkItem, + pTmrEvent, + (OsQueueWorkItemFlags){ + .bLockGpuGroupDevice = NV_TRUE, + .bDontFreeParams = NV_TRUE}); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR,"Queuing workitem for timer event failed with status :0x%x\n", status); + } + + // Out of conflicting thread + threadStateFreeISRAndDeferredIntHandler(&threadState, + pGpu, THREAD_STATE_FLAGS_IS_DEFERRED_INT_HANDLER); + + return status; +} + +NV_STATUS NV_API_CALL rm_run_nano_timer_callback +( + nvidia_stack_t *sp, + nv_state_t *nv, + void *pTmrEvent +) +{ + NV_STATUS status; + OBJGPU *pGpu = NULL; + void *fp; + + if (nv == NULL) + return NV_ERR_GENERIC; + + pGpu = NV_GET_NV_PRIV_PGPU(nv); + if (pGpu == NULL) + return NV_ERR_GENERIC; + + if (!FULL_GPU_SANITY_FOR_PM_RESUME(pGpu)) + { + return NV_ERR_GENERIC; + } + + NV_ENTER_RM_RUNTIME(sp,fp); + + status = RmRunNanoTimerCallback(pGpu, pTmrEvent); + + NV_EXIT_RM_RUNTIME(sp,fp); + + return status; +} + +void NV_API_CALL rm_execute_work_item( + nvidia_stack_t *sp, + void *pNvWorkItem +) +{ + void *fp; + THREAD_STATE_NODE threadState; + + NV_ENTER_RM_RUNTIME(sp, fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + RmExecuteWorkItem(pNvWorkItem); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp, fp); +} + +const char* NV_API_CALL rm_get_device_name( + NvU16 device, + NvU16 subsystem_vendor, + NvU16 subsystem_device +) +{ + unsigned int i; + const char *tmpName = NULL; + + for (i = 0; i < NV_ARRAY_ELEMENTS(sChipsReleased); i++) + { + // if the device ID doesn't match, go to the next entry + if (device != sChipsReleased[i].devID) + { + continue; + } + + // if the entry has 0 for the subsystem IDs, then the device + // ID match is sufficient, but continue scanning through + // sChipsReleased[] in case there is a subsystem ID match later + // in the table + if (sChipsReleased[i].subSystemVendorID == 0 && + sChipsReleased[i].subSystemID == 0) + { + tmpName = sChipsReleased[i].name; + continue; + } + + if (subsystem_vendor == sChipsReleased[i].subSystemVendorID && + subsystem_device == sChipsReleased[i].subSystemID) + { + tmpName = sChipsReleased[i].name; + break; + } + } + + return (tmpName != NULL) ? tmpName : "Unknown"; +} + +NV_STATUS rm_access_registry( + NvHandle hClient, + NvHandle hObject, + NvU32 AccessType, + NvP64 clientDevNodeAddress, + NvU32 DevNodeLength, + NvP64 clientParmStrAddress, + NvU32 ParmStrLength, + NvP64 clientBinaryDataAddress, + NvU32 *pBinaryDataLength, + NvU32 *Data, + NvU32 *Entry +) +{ + NV_STATUS RmStatus; + NvBool bReadOnly = (AccessType == NVOS38_ACCESS_TYPE_READ_DWORD) || + (AccessType == NVOS38_ACCESS_TYPE_READ_BINARY); + + // LOCK: acquire API lock + if ((RmStatus = rmapiLockAcquire(bReadOnly ? RMAPI_LOCK_FLAGS_READ : RMAPI_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_OSAPI)) == NV_OK) + { + RmStatus = RmAccessRegistry(hClient, + hObject, + AccessType, + clientDevNodeAddress, + DevNodeLength, + clientParmStrAddress, + ParmStrLength, + clientBinaryDataAddress, + pBinaryDataLength, + Data, + Entry); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + return RmStatus; +} + +NV_STATUS rm_update_device_mapping_info( + NvHandle hClient, + NvHandle hDevice, + NvHandle hMemory, + void *pOldCpuAddress, + void *pNewCpuAddress +) +{ + NV_STATUS RmStatus; + + // LOCK: acquire API lock + if ((RmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU)) == NV_OK) + { + RmStatus = RmUpdateDeviceMappingInfo(hClient, + hDevice, + hMemory, + pOldCpuAddress, + pNewCpuAddress); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + return RmStatus; +} + +static NvBool NV_API_CALL rm_is_legacy_device( + NvU16 device_id, + NvU16 subsystem_vendor, + NvU16 subsystem_device, + NvBool print_warning +) +{ + return NV_FALSE; +} + +static NvBool NV_API_CALL rm_is_legacy_arch( + NvU32 pmc_boot_0, + NvU32 pmc_boot_42 +) +{ + NvBool legacy = NV_FALSE; + + return legacy; +} + +NV_STATUS NV_API_CALL rm_is_supported_device( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + OBJSYS *pSys; + OBJHALMGR *pHalMgr; + GPUHWREG *reg_mapping; + NvU32 myHalPublicID; + void *fp; + NvU32 pmc_boot_0; + NvU32 pmc_boot_42; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + pSys = SYS_GET_INSTANCE(); + pHalMgr = SYS_GET_HALMGR(pSys); + + reg_mapping = osMapKernelSpace(pNv->regs->cpu_address, + os_page_size, + NV_MEMORY_UNCACHED, + NV_PROTECT_READABLE); + + if (reg_mapping == NULL) + { + nv_printf(NV_DBG_ERRORS, "NVRM: failed to map registers!\n"); + rmStatus = NV_ERR_OPERATING_SYSTEM; + goto threadfree; + } + NvU32 pmc_boot_1 = NV_PRIV_REG_RD32(reg_mapping, NV_PMC_BOOT_1); + pmc_boot_0 = NV_PRIV_REG_RD32(reg_mapping, NV_PMC_BOOT_0); + pmc_boot_42 = NV_PRIV_REG_RD32(reg_mapping, NV_PMC_BOOT_42); + + osUnmapKernelSpace(reg_mapping, os_page_size); + + if ((pmc_boot_0 == 0xFFFFFFFF) && (pmc_boot_42 == 0xFFFFFFFF)) + { + nv_printf(NV_DBG_ERRORS, + "NVRM: The NVIDIA GPU %04x:%02x:%02x.%x\n" + "NVRM: (PCI ID: %04x:%04x) installed in this system has\n" + "NVRM: fallen off the bus and is not responding to commands.\n", + pNv->pci_info.domain, pNv->pci_info.bus, pNv->pci_info.slot, + pNv->pci_info.function, pNv->pci_info.vendor_id, + pNv->pci_info.device_id); + rmStatus = NV_ERR_GPU_IS_LOST; + goto threadfree; + } + + /* + * For legacy architectures, rm_is_legacy_arch() prints "legacy" message. + * We do not want to print "unsupported" message for legacy architectures + * to avoid confusion. Also, the probe should not continue for legacy + * architectures. Hence, we set rmStatus to NV_ERR_NOT_SUPPORTED and + * goto threadfree. + */ + if (rm_is_legacy_arch(pmc_boot_0, pmc_boot_42)) + { + rmStatus = NV_ERR_NOT_SUPPORTED; + goto threadfree; + } + + rmStatus = halmgrGetHalForGpu(pHalMgr, pmc_boot_0, pmc_boot_42, &myHalPublicID); + + if (rmStatus != NV_OK) + { + NvBool bIsFirmwareCapable; + + bIsFirmwareCapable = gpumgrIsDeviceRmFirmwareCapable(pmc_boot_42, + FLD_TEST_DRF(_PMC, _BOOT_1, _VGPU, _VF, pmc_boot_1), + NV_IS_SOC_DISPLAY_DEVICE(pNv), + NULL, + NV_FALSE /* bIsTccOrMcdm */); + if (!bIsFirmwareCapable) + { + if (hypervisorIsVgxHyper()) + { + nv_printf(NV_DBG_ERRORS, + "NVRM: The NVIDIA GPU %04x:%02x:%02x.%x (PCI ID: %04x:%04x)\n" + "NVRM: installed in this vGPU host system is not supported by\n" + "NVRM: open nvidia.ko.\n" + "NVRM: Please see the 'Open Linux Kernel Modules' and 'GSP\n" + "NVRM: Firmware' sections in the NVIDIA Virtual GPU (vGPU)\n" + "NVRM: Software documentation, available at docs.nvidia.com.\n", + pNv->pci_info.domain, pNv->pci_info.bus, pNv->pci_info.slot, + pNv->pci_info.function, pNv->pci_info.vendor_id, + pNv->pci_info.device_id); + } + else + { + nv_printf(NV_DBG_ERRORS, + "NVRM: The NVIDIA GPU %04x:%02x:%02x.%x (PCI ID: %04x:%04x)\n" + "NVRM: installed in this system is not supported by open\n" + "NVRM: nvidia.ko because it does not include the required GPU\n" + "NVRM: System Processor (GSP).\n" + "NVRM: Please see the 'Open Linux Kernel Modules' and 'GSP\n" + "NVRM: Firmware' sections in the driver README, available on\n" + "NVRM: the Linux graphics driver download page at\n" + "NVRM: www.nvidia.com.\n", + pNv->pci_info.domain, pNv->pci_info.bus, pNv->pci_info.slot, + pNv->pci_info.function, pNv->pci_info.vendor_id, + pNv->pci_info.device_id); + } + goto threadfree; + } + goto print_unsupported; + } + + rmStatus = rm_is_vgpu_supported_device(pNv, pmc_boot_1, pmc_boot_42); + + if (rmStatus != NV_OK) + { + nv_printf(NV_DBG_ERRORS, + "NVRM: The NVIDIA vGPU %04x:%02x:%02x.%x (PCI ID: %04x:%04x)\n" + "NVRM: installed in this system is not supported by open\n" + "NVRM: nvidia.ko.\n" + "NVRM: Please see the 'Open Linux Kernel Modules' and 'GSP\n" + "NVRM: Firmware' sections in the NVIDIA Virtual GPU (vGPU)\n" + "NVRM: Software documentation, available at docs.nvidia.com.\n", + pNv->pci_info.domain, pNv->pci_info.bus, pNv->pci_info.slot, + pNv->pci_info.function, pNv->pci_info.vendor_id, + pNv->pci_info.device_id); + goto threadfree; + } + goto threadfree; + +print_unsupported: + nv_printf(NV_DBG_ERRORS, + "NVRM: The NVIDIA GPU %04x:%02x:%02x.%x (PCI ID: %04x:%04x)\n" + "NVRM: installed in this system is not supported by the\n" + "NVRM: NVIDIA %s driver release.\n" + "NVRM: Please see 'Appendix A - Supported NVIDIA GPU Products'\n" + "NVRM: in this release's README, available on the operating system\n" + "NVRM: specific graphics driver download page at www.nvidia.com.\n", + pNv->pci_info.domain, pNv->pci_info.bus, pNv->pci_info.slot, + pNv->pci_info.function, pNv->pci_info.vendor_id, + pNv->pci_info.device_id, NV_VERSION_STRING); + +threadfree: + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NvBool NV_API_CALL rm_is_supported_pci_device( + NvU8 pci_class, + NvU8 pci_subclass, + NvU16 vendor, + NvU16 device, + NvU16 subsystem_vendor, + NvU16 subsystem_device, + NvBool print_legacy_warning +) +{ + const NvU16 nv_pci_vendor_id = 0x10DE; + const NvU16 nv_pci_id_riva_tnt = 0x0020; + const NvU8 nv_pci_class_display = 0x03; + const NvU8 nv_pci_subclass_display_vga = 0x00; + const NvU8 nv_pci_subclass_display_3d = 0x02; + + if (pci_class != nv_pci_class_display) + { + return NV_FALSE; + } + + if ((pci_subclass != nv_pci_subclass_display_vga) && + (pci_subclass != nv_pci_subclass_display_3d)) + { + return NV_FALSE; + } + + if (vendor != nv_pci_vendor_id) + { + return NV_FALSE; + } + + if (device < nv_pci_id_riva_tnt) + { + return NV_FALSE; + } + + if (rm_is_legacy_device( + device, + subsystem_vendor, + subsystem_device, + print_legacy_warning)) + { + return NV_FALSE; + } + + return NV_TRUE; +} + +/* + * Performs the I2C transfers which are related with DP AUX channel + */ +static NV_STATUS RmDpAuxI2CTransfer +( + nv_state_t *pNv, + NvU32 displayId, + NvU8 addr, + NvU32 len, + NvU8 *pData, + NvBool bWrite +) +{ + NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_CTRL_PARAMS *pParams; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NV_STATUS status; + + if (len > NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_MAX_DATA_SIZE) + { + NV_PRINTF(LEVEL_ERROR, + "%s: requested I2C transfer length %u is greater than maximum supported length %u\n", + __FUNCTION__, len, NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_MAX_DATA_SIZE); + return NV_ERR_NOT_SUPPORTED; + } + + pParams = portMemAllocNonPaged(sizeof(*pParams)); + if (pParams == NULL) + { + return NV_ERR_NO_MEMORY; + } + + portMemSet(pParams, 0, sizeof(*pParams)); + + pParams->subDeviceInstance = 0; + pParams->displayId = displayId; + pParams->addr = addr; + pParams->size = len; + pParams->bWrite = bWrite; + + if (bWrite) + { + portMemCopy(pParams->data, NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_MAX_DATA_SIZE, + pData, len); + } + + status = pRmApi->Control(pRmApi, pNv->rmapi.hClient, pNv->rmapi.hDisp, + NV0073_CTRL_CMD_DP_AUXCH_I2C_TRANSFER_CTRL, + pParams, sizeof(*pParams)); + + if ((status == NV_OK) && !bWrite) + { + portMemCopy(pData, len, pParams->data, pParams->size); + } + + portMemFree(pParams); + + return status; +} + +/* + * Performs the I2C transfers which are not related with DP AUX channel + */ +static NV_STATUS RmNonDPAuxI2CTransfer +( + nv_state_t *pNv, + NvU8 portId, + nv_i2c_cmd_t type, + NvU8 addr, + NvU8 command, + NvU32 len, + NvU8 *pData +) +{ + NV402C_CTRL_I2C_TRANSACTION_PARAMS *params; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NV_STATUS rmStatus = NV_OK; + + params = portMemAllocNonPaged(sizeof(*params)); + if (params == NULL) + { + return NV_ERR_NO_MEMORY; + } + + portMemSet(params, 0, sizeof(*params)); + + params->portId = portId; + // precondition our address (our stack requires this) + params->deviceAddress = addr << 1; + + switch (type) + { + case NV_I2C_CMD_WRITE: + params->transData.i2cBlockData.bWrite = NV_TRUE; + /* fall through*/ + + case NV_I2C_CMD_READ: + params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW; + params->transData.i2cBlockData.messageLength = len; + params->transData.i2cBlockData.pMessage = pData; + break; + + case NV_I2C_CMD_SMBUS_WRITE: + if (len == 2) + { + params->transData.smbusWordData.bWrite = NV_TRUE; + } + else + { + params->transData.smbusByteData.bWrite = NV_TRUE; + } + /* fall through*/ + + case NV_I2C_CMD_SMBUS_READ: + if (len == 2) + { + params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW; + params->transData.smbusWordData.message = pData[0] | ((NvU16)pData[1] << 8); + params->transData.smbusWordData.registerAddress = command; + } + else + { + params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW; + params->transData.smbusByteData.message = pData[0]; + params->transData.smbusByteData.registerAddress = command; + } + break; + + case NV_I2C_CMD_SMBUS_BLOCK_WRITE: + if (pData[0] >= len) { + portMemFree(params); + return NV_ERR_INVALID_ARGUMENT; + } + params->transData.smbusBlockData.bWrite = NV_TRUE; + params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW; + params->transData.smbusBlockData.registerAddress = command; + params->transData.smbusBlockData.messageLength = pData[0]; + params->transData.smbusBlockData.pMessage = pData + 1; + break; + + case NV_I2C_CMD_SMBUS_BLOCK_READ: + params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW; + params->transData.smbusBlockData.registerAddress = command; + params->transData.smbusBlockData.messageLength = len; + params->transData.smbusBlockData.pMessage = pData; + break; + + case NV_I2C_CMD_SMBUS_QUICK_WRITE: + params->transData.smbusQuickData.bWrite = NV_TRUE; + /* fall through*/ + + case NV_I2C_CMD_SMBUS_QUICK_READ: + params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW; + break; + + case NV_I2C_CMD_BLOCK_WRITE: + params->transData.i2cBufferData.bWrite = NV_TRUE; + /* fall through */ + + case NV_I2C_CMD_BLOCK_READ: + params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW; + params->transData.i2cBufferData.registerAddress = command; + params->transData.i2cBufferData.messageLength = len; + params->transData.i2cBufferData.pMessage = pData; + break; + + default: + portMemFree(params); + return NV_ERR_INVALID_ARGUMENT; + } + + rmStatus = pRmApi->Control(pRmApi, pNv->rmapi.hClient, + pNv->rmapi.hI2C, + NV402C_CTRL_CMD_I2C_TRANSACTION, + params, sizeof(*params)); + + // + // For NV_I2C_CMD_SMBUS_READ, copy the read data to original + // data buffer. + // + if (rmStatus == NV_OK && type == NV_I2C_CMD_SMBUS_READ) + { + if (len == 2) + { + pData[0] = (params->transData.smbusWordData.message & 0xff); + pData[1] = params->transData.smbusWordData.message >> 8; + } + else + { + pData[0] = params->transData.smbusByteData.message; + } + } + + portMemFree(params); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_i2c_transfer( + nvidia_stack_t *sp, + nv_state_t *pNv, + void *pI2cAdapter, + nv_i2c_cmd_t type, + NvU8 addr, + NvU8 command, + NvU32 len, + NvU8 *pData +) +{ + THREAD_STATE_NODE threadState; + nv_priv_t *pNvp = NV_GET_NV_PRIV(pNv); + NV_STATUS rmStatus = NV_OK; + OBJGPU *pGpu = NULL; + NvBool unlockApi = NV_FALSE; + NvBool unlockGpu = NV_FALSE; + NvU32 x; + void *fp; + NvU32 numDispId = 0; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + if (pNvp->flags & NV_INIT_FLAG_PUBLIC_I2C) + { + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_I2C)) != NV_OK) + goto finish; + + unlockApi = NV_TRUE; + + // LOCK: acquire GPUs lock + if ((rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_I2C)) != NV_OK) + goto finish; + + unlockGpu = NV_TRUE; + } + + pGpu = NV_GET_NV_PRIV_PGPU(pNv); + + if (!pGpu) + { + rmStatus = NV_ERR_GENERIC; + goto finish; + } + + for (x = 0; x < MAX_I2C_ADAPTERS; x++) + { + if (pNvp->i2c_adapters[x].pOsAdapter == pI2cAdapter) + { + break; + } + } + + if (x == MAX_I2C_ADAPTERS) + { + rmStatus = NV_ERR_GENERIC; + goto finish; + } + + for (numDispId = 0; numDispId < MAX_DISP_ID_PER_ADAPTER; numDispId++) + { + NvU32 displayId = pNvp->i2c_adapters[x].displayId[numDispId]; + + if (displayId == INVALID_DISP_ID) + { + continue; + } + + // Handle i2c-over-DpAux adapters separately from regular i2c adapters + if (displayId == 0) + { + rmStatus = RmNonDPAuxI2CTransfer(pNv, pNvp->i2c_adapters[x].port, + type, addr, command, len, pData); + } + else + { + if ((type != NV_I2C_CMD_READ) && (type != NV_I2C_CMD_WRITE)) + { + rmStatus = NV_ERR_NOT_SUPPORTED; + goto semafinish; + } + + rmStatus = RmDpAuxI2CTransfer(pNv, displayId, addr, len, pData, + type == NV_I2C_CMD_WRITE); + } +semafinish: + if (rmStatus == NV_OK) + { + break; + } + } + +finish: + if (unlockGpu) + { + // UNLOCK: release GPU lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + + if (unlockApi) + { + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +static void rm_i2c_add_adapter( + nv_state_t *pNv, + NvU32 port, + NvU32 displayId +) +{ + NvU32 y, free; + nv_priv_t *pNvp = NV_GET_NV_PRIV(pNv); + NvU32 numDispId = 0; + + for (y = 0, free = MAX_I2C_ADAPTERS; y < MAX_I2C_ADAPTERS; y++) + { + if (pNvp->i2c_adapters[y].pOsAdapter == NULL) + { + // Only find the first free entry, and ignore the rest + if (free == MAX_I2C_ADAPTERS) + { + free = y; + } + } + else if (pNvp->i2c_adapters[y].port == port) + { + break; + } + } + + if (y < MAX_I2C_ADAPTERS) + { + for (numDispId = 0; numDispId < MAX_DISP_ID_PER_ADAPTER; numDispId++) + { + if (pNvp->i2c_adapters[y].displayId[numDispId] == INVALID_DISP_ID) + { + pNvp->i2c_adapters[y].displayId[numDispId] = displayId; + break; + } + else + { + NV_PRINTF(LEVEL_INFO, + "%s: adapter already exists (port=0x%x, displayId=0x%x)\n", + __FUNCTION__, port, + pNvp->i2c_adapters[y].displayId[numDispId]); + } + } + + if (numDispId == MAX_DISP_ID_PER_ADAPTER) + { + NV_PRINTF(LEVEL_ERROR, + "%s: no more free display Id entries in adapter\n", + __FUNCTION__); + } + + return; + } + + if (free == MAX_I2C_ADAPTERS) + { + NV_PRINTF(LEVEL_ERROR, "%s: no more free adapter entries exist\n", + __FUNCTION__); + return; + } + + pNvp->i2c_adapters[free].pOsAdapter = nv_i2c_add_adapter(pNv, port); + pNvp->i2c_adapters[free].port = port; + // When port is added, numDispId will be 0. + pNvp->i2c_adapters[free].displayId[numDispId] = displayId; +} + +void RmI2cAddGpuPorts(nv_state_t * pNv) +{ + NvU32 x = 0; + nv_priv_t *pNvp = NV_GET_NV_PRIV(pNv); + RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); + NvU32 displayMask; + NV_STATUS status; + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS systemGetSupportedParams = { 0 }; + + if (IS_VIRTUAL(pGpu) || NV_IS_SOC_DISPLAY_DEVICE(pNv)) + return; + + // Make displayId as Invalid. + for (x = 0; x < MAX_I2C_ADAPTERS; x++) + { + NvU32 numDispId; + + for (numDispId = 0; numDispId < MAX_DISP_ID_PER_ADAPTER; numDispId++) + { + pNvp->i2c_adapters[x].displayId[numDispId] = INVALID_DISP_ID; + } + } + + // First, set up the regular i2c adapters - one per i2c port + if (pNv->rmapi.hI2C != 0) + { + NV402C_CTRL_I2C_GET_PORT_INFO_PARAMS i2cPortInfoParams = { 0 }; + + status = pRmApi->Control(pRmApi, pNv->rmapi.hClient, pNv->rmapi.hI2C, + NV402C_CTRL_CMD_I2C_GET_PORT_INFO, + &i2cPortInfoParams, sizeof(i2cPortInfoParams)); + + if (status == NV_OK) + { + for (x = 0; x < NV_ARRAY_ELEMENTS(i2cPortInfoParams.info); x++) + { + // + // Check if this port is implemented and RM I2C framework has + // validated this port. Only limited amount of ports can + // be added to the OS framework. + // + if (FLD_TEST_DRF(402C_CTRL, _I2C_GET_PORT_INFO, _IMPLEMENTED, + _YES, i2cPortInfoParams.info[x]) && + FLD_TEST_DRF(402C_CTRL, _I2C_GET_PORT_INFO, _VALID, + _YES, i2cPortInfoParams.info[x])) + { + rm_i2c_add_adapter(pNv, x, 0); + } + } + } + } + + // + // Now set up the i2c-over-DpAux adapters - one per DP OD + // + // 1. Perform NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS RM control which + // will return the mask for all the display ID's. + // 2. Loop for all the display ID's and do + // NV0073_CTRL_CMD_SPECIFIC_OR_GET_INFO RM control call. For each + // output resource, check for the following requirements: + // a. It must be DisplayPort. + // b. It must be internal to the GPU (ie, not on the board) + // c. It must be directly connected to the physical connector (ie, no DP + // 1.2 multistream ODs). + // 3. Perform NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID RM control for + // getting the I2C port data. + // + // With these restrictions, we should only end up with at most one OD + // per DP connector. + // + + if (pNv->rmapi.hDisp == 0) + { + return; + } + + systemGetSupportedParams.subDeviceInstance = 0; + status = pRmApi->Control(pRmApi, pNv->rmapi.hClient, pNv->rmapi.hDisp, + NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED, + &systemGetSupportedParams, sizeof(systemGetSupportedParams)); + + if (status != NV_OK) + { + return; + } + + for (displayMask = systemGetSupportedParams.displayMask; + displayMask != 0; + displayMask &= ~LOWESTBIT(displayMask)) + { + NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS orInfoParams = { 0 }; + NvU32 displayId = LOWESTBIT(displayMask); + + orInfoParams.subDeviceInstance = 0; + orInfoParams.displayId = displayId; + + status = pRmApi->Control(pRmApi, pNv->rmapi.hClient, pNv->rmapi.hDisp, + NV0073_CTRL_CMD_SPECIFIC_OR_GET_INFO, + &orInfoParams, sizeof(orInfoParams)); + + if ((status == NV_OK) && + (orInfoParams.type == NV0073_CTRL_SPECIFIC_OR_TYPE_SOR) && + ((orInfoParams.protocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_A) || + (orInfoParams.protocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_B)) && + (orInfoParams.location == NV0073_CTRL_SPECIFIC_OR_LOCATION_CHIP) && + (!orInfoParams.bIsDispDynamic)) + { + NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS i2cPortIdParams = { 0 }; + + i2cPortIdParams.subDeviceInstance = 0; + i2cPortIdParams.displayId = displayId; + + status = pRmApi->Control(pRmApi, + pNv->rmapi.hClient, + pNv->rmapi.hDisp, + NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID, + &i2cPortIdParams, + sizeof(i2cPortIdParams)); + + if ((status == NV_OK) && + (i2cPortIdParams.ddcPortId != NV0073_CTRL_SPECIFIC_I2C_PORT_NONE)) + { + rm_i2c_add_adapter(pNv, i2cPortIdParams.ddcPortId - 1, displayId); + } + } + } +} + +void NV_API_CALL rm_i2c_remove_adapters( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + // + // Cycle through all adapter entries, and first remove the adapter + // from the list from the kernel, then remove the i2c adapter + // list once that is completed. This should only be used from exit + // module time. Otherwise it could fail to remove some of the + // kernel adapters and subsequent transfer requests would result + // in crashes. + // + NvU32 x = 0; + nv_priv_t *pNvp = NV_GET_NV_PRIV(pNv); + NvU32 numDispId; + + for (x = 0; x < MAX_I2C_ADAPTERS; x++) + { + if (pNvp->i2c_adapters[x].pOsAdapter != NULL) + { + nv_i2c_del_adapter(pNv, pNvp->i2c_adapters[x].pOsAdapter); + + pNvp->i2c_adapters[x].pOsAdapter = NULL; + pNvp->i2c_adapters[x].port = 0; + for (numDispId = 0; numDispId < MAX_DISP_ID_PER_ADAPTER; numDispId++) + { + pNvp->i2c_adapters[x].displayId[numDispId] = INVALID_DISP_ID; + } + } + } +} + +NvBool NV_API_CALL rm_i2c_is_smbus_capable( + nvidia_stack_t *sp, + nv_state_t *pNv, + void *pI2cAdapter +) +{ + THREAD_STATE_NODE threadState; + nv_priv_t *pNvp = NV_GET_NV_PRIV(pNv); + NV_STATUS rmStatus = NV_OK; + OBJGPU *pGpu = NULL; + NvBool unlock = NV_FALSE; + NvU32 x; + NvBool ret = NV_FALSE; + void *fp; + NvU32 numDispId = 0; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + if (pNvp->flags & NV_INIT_FLAG_PUBLIC_I2C) + { + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_I2C)) != NV_OK) + goto semafinish; + + unlock = NV_TRUE; + } + + pGpu = NV_GET_NV_PRIV_PGPU(pNv); + + if (!pGpu) + { + goto semafinish; + } + + for (x = 0; x < MAX_I2C_ADAPTERS; x++) + { + if (pNvp->i2c_adapters[x].pOsAdapter == pI2cAdapter) + { + break; + } + } + + if (x == MAX_I2C_ADAPTERS) + { + goto semafinish; + } + + // we do not support smbus functions on i2c-over-DPAUX + for (numDispId = 0; numDispId < MAX_DISP_ID_PER_ADAPTER; numDispId++) + { + if (pNvp->i2c_adapters[x].displayId[numDispId] == 0x0) + { + ret = NV_TRUE; + } + } + +semafinish: + if (unlock) + { + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return ret; +} + +NV_STATUS NV_API_CALL rm_perform_version_check( + nvidia_stack_t *sp, + void *pData, + NvU32 dataSize +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + rmStatus = RmPerformVersionCheck(pData, dataSize); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +// +// Handles the Power Source Change event(AC/DC) for Notebooks. +// Notebooks from Maxwell have only one Gpu, so this functions grabs first Gpu +// from GpuMgr and call subdevice RmControl. +// +void NV_API_CALL rm_power_source_change_event( + nvidia_stack_t *sp, + NvU32 event_val +) +{ + THREAD_STATE_NODE threadState; + void *fp; + nv_state_t *nv; + static NvBool first_event_seen = NV_FALSE; + static NvU32 last_event_val = 0; + NV_STATUS rmStatus = NV_OK; + + // Some systems generate spurious power source changed ACPI events. + // Before entering the PM runtime and waking the GPU, see if the power + // state has actually changed. If not, return without waking the GPU. + if ((first_event_seen != NV_FALSE) && (last_event_val == event_val)) + { + return; + } + else + { + first_event_seen = NV_TRUE; + last_event_val = event_val; + } + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_EVENT)) == NV_OK) + { + OBJGPU *pGpu = gpumgrGetGpu(0); + if (pGpu != NULL) + { + nv = NV_GET_NV_STATE(pGpu); + if ((rmStatus = os_ref_dynamic_power(nv, NV_DYNAMIC_PM_FINE)) == + NV_OK) + { + // LOCK: acquire GPU lock + if ((rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_EVENT)) == + NV_OK) + { + rmStatus = RmPowerSourceChangeEvent(nv, event_val); + + // UNLOCK: release GPU lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + os_unref_dynamic_power(nv, NV_DYNAMIC_PM_FINE); + } + // UNLOCK: release API lock + rmapiLockRelease(); + } + } + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s: Failed to handle Power Source change event, status=0x%x\n", + __FUNCTION__, rmStatus); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +void NV_API_CALL rm_request_dnotifier_state( + nv_stack_t *sp, + nv_state_t *pNv +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(pNv); + + if (nvp->b_mobile_config_enabled) + { + THREAD_STATE_NODE threadState; + void *fp; + GPU_MASK gpuMask; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_ACPI)) == NV_OK) + { + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + + // LOCK: acquire per device lock + if ((pGpu != NULL) && + ((rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_ACPI, + &gpuMask)) == NV_OK)) + { + RmRequestDNotifierState(pNv); + + // UNLOCK: release per device lock + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + } + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + } +} + +NV_STATUS NV_API_CALL rm_p2p_dma_map_pages( + nvidia_stack_t *sp, + nv_dma_device_t *peer, + NvU8 *pGpuUuid, + NvU64 pageSize, + NvU32 pageCount, + NvU64 *pDmaAddresses, + void **ppPriv +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + NvU32 i, j; + OBJGPU *pGpu; + nv_state_t *pNv; + + if (ppPriv == NULL) + return NV_ERR_INVALID_ARGUMENT; + + *ppPriv = NULL; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P); + if (rmStatus != NV_OK) + goto done; + + pGpu = gpumgrGetGpuFromUuid(pGpuUuid, + DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, _SHA1) | + DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _FORMAT, _BINARY)); + if (pGpu == NULL) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto unlock; + } + + pNv = NV_GET_NV_STATE(pGpu); + + if (pNv->coherent) + { + rmStatus = RmP2PDmaMapPages(pNv, peer, pageSize, pageCount, + pDmaAddresses, ppPriv); + goto unlock; + } + + // Check if the topology is supported for third party p2p + if (!nv_grdma_pci_topology_supported(pNv, peer)) + { + rmStatus = NV_ERR_NOT_SUPPORTED; + goto unlock; + } + + for (i = 0; i < pageCount; i++) + { + // Map BAR1 PFNs for non-coherent platforms + rmStatus = nv_dma_map_peer(peer, pNv->dma_dev, 0x1, + pageSize / os_page_size, + &pDmaAddresses[i]); + if (rmStatus != NV_OK) + { + for (j = 0; j < i; j++) + { + nv_dma_unmap_peer(peer, pageSize / os_page_size, + pDmaAddresses[j]); + } + goto unlock; + } + } + +unlock: + rmapiLockRelease(); + +done: + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_p2p_get_gpu_info( + nvidia_stack_t *sp, + NvU64 gpuVirtualAddress, + NvU64 length, + NvU8 **ppGpuUuid, + void **ppGpuInfo +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P); + if (rmStatus == NV_OK) + { + OBJGPU *pGpu; + rmStatus = RmP2PGetGpuByAddress(gpuVirtualAddress, + length, + &pGpu); + if (rmStatus == NV_OK) + { + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + const NvU8 *pGid; + + pGid = RmGetGpuUuidRaw(nv); + if (pGid == NULL) + { + rmStatus = NV_ERR_GPU_UUID_NOT_FOUND; + } + else + { + rmStatus = os_alloc_mem((void **)ppGpuUuid, GPU_UUID_LEN); + if (rmStatus == NV_OK) + { + os_mem_copy(*ppGpuUuid, pGid, GPU_UUID_LEN); + } + } + + *ppGpuInfo = (void *) pGpu; + } + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_p2p_get_pages_persistent( + nvidia_stack_t *sp, + NvU64 gpuVirtualAddress, + NvU64 length, + void **p2pObject, + NvU64 *pPhysicalAddresses, + NvU32 *pEntries, + NvBool bForcePcie, + void *pPlatformData, + void *pGpuInfo, + void **ppMigInfo, + NvBool *pMemCpuCacheable +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) + { + rmStatus = RmP2PGetPagesPersistent(gpuVirtualAddress, + length, + p2pObject, + pPhysicalAddresses, + pEntries, + pMemCpuCacheable, + bForcePcie, + pPlatformData, + pGpuInfo, + ppMigInfo); + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_p2p_get_pages( + nvidia_stack_t *sp, + NvU64 p2pToken, + NvU32 vaSpaceToken, + NvU64 gpuVirtualAddress, + NvU64 length, + NvU64 *pPhysicalAddresses, + NvU32 *pWreqMbH, + NvU32 *pRreqMbH, + NvU32 *pEntries, + NvU8 **ppGpuUuid, + void *pPlatformData, + NvBool *pMemCpuCacheable +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) + { + OBJGPU *pGpu; + rmStatus = RmP2PGetPagesWithoutCallbackRegistration(p2pToken, + vaSpaceToken, + gpuVirtualAddress, + length, + pPhysicalAddresses, + pWreqMbH, + pRreqMbH, + pEntries, + pMemCpuCacheable, + &pGpu, + pPlatformData); + if (rmStatus == NV_OK) + { + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + const NvU8 *pGid; + + pGid = RmGetGpuUuidRaw(nv); + if (pGid == NULL) + { + NV_ASSERT_OK(RmP2PPutPages(p2pToken, vaSpaceToken, + gpuVirtualAddress, + pPlatformData)); + rmStatus = NV_ERR_GENERIC; + } + else + { + rmStatus = os_alloc_mem((void **)ppGpuUuid, GPU_UUID_LEN); + if (rmStatus == NV_OK) + os_mem_copy(*ppGpuUuid, pGid, GPU_UUID_LEN); + } + + *pMemCpuCacheable = nv->coherent; + } + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_p2p_register_callback( + nvidia_stack_t *sp, + NvU64 p2pToken, + NvU64 gpuVirtualAddress, + NvU64 length, + void *pPlatformData, + void (*pFreeCallback)(void *pData), + void *pData +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) + { + rmStatus = RmP2PRegisterCallback(p2pToken, gpuVirtualAddress, length, + pPlatformData, pFreeCallback, pData); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_p2p_put_pages_persistent( + nvidia_stack_t *sp, + void *p2pObject, + void *pKey, + void *pMigInfo +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) + { + rmStatus = RmP2PPutPagesPersistent(p2pObject, pKey, pMigInfo); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_p2p_put_pages( + nvidia_stack_t *sp, + NvU64 p2pToken, + NvU32 vaSpaceToken, + NvU64 gpuVirtualAddress, + void *pKey +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) + { + rmStatus = RmP2PPutPages(p2pToken, + vaSpaceToken, + gpuVirtualAddress, + pKey); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +char* NV_API_CALL rm_get_gpu_uuid( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + NV_STATUS rmStatus; + const NvU8 *pGid; + char *pGidString; + + THREAD_STATE_NODE threadState; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // Allocate space for the ASCII string + rmStatus = os_alloc_mem((void **)&pGidString, GPU_UUID_ASCII_LEN); + if (rmStatus != NV_OK) + { + pGidString = NULL; + goto done; + } + + // Get the raw UUID; note the pGid is cached, so we do not need to free it + pGid = RmGetGpuUuidRaw(nv); + + if (pGid != NULL) + { + // Convert the raw UUID to ASCII + rmStatus = RmGpuUuidRawToString(pGid, pGidString, GPU_UUID_ASCII_LEN); + if (rmStatus != NV_OK) + { + os_free_mem(pGidString); + pGidString = NULL; + } + } + else + { + const char *pTmpString = "GPU-???????\?-???\?-???\?-???\?-????????????"; + + portStringCopy(pGidString, GPU_UUID_ASCII_LEN, pTmpString, + portStringLength(pTmpString) + 1); + } + +done: + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return pGidString; +} + +// +// This function will return the UUID in the binary format +// +const NvU8 * NV_API_CALL rm_get_gpu_uuid_raw( + nvidia_stack_t *sp, + nv_state_t *nv) +{ + THREAD_STATE_NODE threadState; + void *fp; + const NvU8 *pGid; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + pGid = RmGetGpuUuidRaw(nv); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return pGid; +} + +static void rm_set_firmware_logs( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + void *fp; + NvU32 enableFirmwareLogsRegVal = NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG; + + NV_ENTER_RM_RUNTIME(sp,fp); + + (void) RmReadRegistryDword(nv, NV_REG_ENABLE_GPU_FIRMWARE_LOGS, + &enableFirmwareLogsRegVal); + nv->enable_firmware_logs = gpumgrGetRmFirmwareLogsEnabled(enableFirmwareLogsRegVal); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +static NvBool rm_get_is_gsp_capable_vgpu( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + void *fp; + THREAD_STATE_NODE threadState; + NvBool isVgpu = NV_FALSE; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + if ((pHypervisor != NULL) && pHypervisor->bIsHVMGuest) + { + GPUHWREG *reg_mapping; + reg_mapping = osMapKernelSpace(nv->regs->cpu_address, + os_page_size, + NV_MEMORY_UNCACHED, + NV_PROTECT_READABLE); + + if (reg_mapping != NULL) + { + NvU32 pmc_boot_1 = NV_PRIV_REG_RD32(reg_mapping, NV_PMC_BOOT_1); + NvU32 pmc_boot_42 = NV_PRIV_REG_RD32(reg_mapping, NV_PMC_BOOT_42); + + osUnmapKernelSpace(reg_mapping, os_page_size); + + if (FLD_TEST_DRF(_PMC, _BOOT_1, _VGPU, _VF, pmc_boot_1) && + gpumgrIsVgxRmFirmwareCapableChip(pmc_boot_42)) + { + isVgpu = NV_TRUE; + } + } + } + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + return isVgpu; +} + +void NV_API_CALL rm_set_rm_firmware_requested( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + nv->request_firmware = NV_TRUE; + nv->allow_fallback_to_monolithic_rm = NV_FALSE; + if (rm_get_is_gsp_capable_vgpu(sp, nv)) + { + nv->request_firmware = NV_FALSE; + } + + // Check if we want firmware logs + if (nv->request_firmware) + rm_set_firmware_logs(sp, nv); +} + +// +// disable GPU SW state persistence +// + +void NV_API_CALL rm_disable_gpu_state_persistence(nvidia_stack_t *sp, nv_state_t *nv) +{ + THREAD_STATE_NODE threadState; + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + pGpu->setProperty(pGpu, PDB_PROP_GPU_PERSISTENT_SW_STATE, NV_FALSE); + osModifyGpuSwStatePersistence(pGpu->pOsGpuInfo, NV_FALSE); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +void NV_API_CALL rm_kernel_rmapi_op(nvidia_stack_t *sp, void *ops_cmd) +{ + nvidia_kernel_rmapi_ops_t *ops = ops_cmd; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + switch (ops->op) + { + case NV01_FREE: + Nv01FreeKernel(&ops->params.free); + break; + + case NV01_ALLOC_MEMORY: + Nv01AllocMemoryKernel(&ops->params.allocMemory64); + break; + + case NV04_ALLOC: + Nv04AllocWithAccessKernel(&ops->params.alloc); + break; + + case NV04_VID_HEAP_CONTROL: + Nv04VidHeapControlKernel(ops->params.pVidHeapControl); + break; + + case NV04_MAP_MEMORY: + { + // + // We need to free NVUAP for MEM_SPACE_USER mappings, + // since we're not going through the regular path + // + nv_usermap_access_params_t *pNvuap = NULL; + Nv04MapMemoryKernel(&ops->params.mapMemory); + pNvuap = (nv_usermap_access_params_t *) tlsEntryGet(TLS_ENTRY_ID_MAPPING_CONTEXT); + if (pNvuap != NULL) + { + NV_ASSERT(tlsEntryRelease(TLS_ENTRY_ID_MAPPING_CONTEXT) == 0); + os_free_mem(pNvuap->memArea.pRanges); + os_free_mem(pNvuap); + } + break; + } + + case NV04_UNMAP_MEMORY: + Nv04UnmapMemoryKernel(&ops->params.unmapMemory); + break; + + case NV04_ALLOC_CONTEXT_DMA: + Nv04AllocContextDmaKernel(&ops->params.allocContextDma2); + break; + + case NV04_MAP_MEMORY_DMA: + Nv04MapMemoryDmaKernel(&ops->params.mapMemoryDma); + break; + + case NV04_UNMAP_MEMORY_DMA: + Nv04UnmapMemoryDmaKernel(&ops->params.unmapMemoryDma); + break; + + case NV04_BIND_CONTEXT_DMA: + Nv04BindContextDmaKernel(&ops->params.bindContextDma); + break; + + case NV04_CONTROL: + Nv04ControlKernel(&ops->params.control); + break; + + case NV04_DUP_OBJECT: + Nv04DupObjectKernel(&ops->params.dupObject); + break; + + case NV04_SHARE: + Nv04ShareKernel(&ops->params.share); + break; + + case NV04_ADD_VBLANK_CALLBACK: + Nv04AddVblankCallbackKernel(&ops->params.addVblankCallback); + break; + } + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +// +// ACPI method (NVIF/_DSM/WMMX/MXM*/etc.) initialization +// +void RmInitAcpiMethods(OBJOS *pOS, OBJSYS *pSys, OBJGPU *pGpu) +{ + NvU32 handlesPresent; + + if (pSys->getProperty(pSys, PDB_PROP_SYS_NVIF_INIT_DONE)) + return; + + nv_acpi_methods_init(&handlesPresent); + + acpiDsmInit(pGpu); +} + +// +// ACPI method (NVIF/_DSM/WMMX/MXM*/etc.) teardown +// +void RmUnInitAcpiMethods(OBJSYS *pSys) +{ + pSys->setProperty(pSys, PDB_PROP_SYS_NVIF_INIT_DONE, NV_FALSE); + + nv_acpi_methods_uninit(); +} + +// +// Converts an array of OS page address to an array of RM page addresses.This +// assumes that: +// (1) The pteArray is at least pageCount entries large, +// (2) The pageCount is given in RM pages, and +// (3) The OS page entries start at index 0. +// +void RmInflateOsToRmPageArray(RmPhysAddr *pteArray, NvU64 pageCount) +{ + RmInflatePageArray( + pteArray, + NV_RM_PAGES_TO_OS_PAGES(pageCount), + os_page_size, + pageCount, + NV_RM_PAGE_SIZE + ); +} + +void RmDeflateRmToOsPageArray(RmPhysAddr *pteArray, NvU64 pageCount) +{ + RmDeflatePageArray( + pteArray, + pageCount, + NV_RM_PAGE_SIZE, + NV_RM_PAGES_TO_OS_PAGES(pageCount), + os_page_size + ); +} + +NvBool NV_API_CALL +rm_get_device_remove_flag +( + nvidia_stack_t * sp, + NvU32 gpu_id +) +{ + THREAD_STATE_NODE threadState; + void *fp; + NvBool bRemove; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + if (gpumgrQueryGpuDrainState(gpu_id, NULL, &bRemove) != NV_OK) + { + bRemove = NV_FALSE; + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + return bRemove; +} + +// +// This API updates only the following fields in nv_ioctl_numa_info_t: +// - nid +// - numa_mem_addr +// - numa_mem_size +// - offline_addresses +// +// Rest of the fields should be updated by caller. +NV_STATUS NV_API_CALL rm_get_gpu_numa_info( + nvidia_stack_t *sp, + nv_state_t *nv, + nv_ioctl_numa_info_t *numa_info +) +{ + NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS *pParams; + RM_API *pRmApi; + THREAD_STATE_NODE threadState; + void *fp; + NV_STATUS status = NV_OK; + + ct_assert(NV_ARRAY_ELEMENTS(numa_info->offline_addresses.addresses) >= + NV_ARRAY_ELEMENTS(pParams->numaOfflineAddresses)); + + if ((numa_info == NULL) || + (numa_info->offline_addresses.numEntries > + NV_ARRAY_ELEMENTS(pParams->numaOfflineAddresses))) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (NV_IS_SOC_DISPLAY_DEVICE(nv)) + { + numa_info->nid = NV0000_CTRL_NO_NUMA_NODE; + numa_info->numa_mem_addr = 0; + numa_info->numa_mem_size = 0; + numa_info->offline_addresses.numEntries = 0; + return NV_OK; + } + + NV_ENTER_RM_RUNTIME(sp,fp); + + pParams = portMemAllocNonPaged(sizeof(*pParams)); + if (pParams == NULL) + { + NV_EXIT_RM_RUNTIME(sp,fp); + return NV_ERR_NO_MEMORY; + } + + portMemSet(pParams, 0, sizeof(*pParams)); + pParams->numaOfflineAddressesCount = + numa_info->offline_addresses.numEntries; + + pRmApi = RmUnixRmApiPrologue(nv, &threadState, RM_LOCK_MODULES_MEM); + if (pRmApi == NULL) + { + status = NV_ERR_INVALID_STATE; + goto finish; + } + + status = pRmApi->Control(pRmApi, nv->rmapi.hClient, nv->rmapi.hSubDevice, + NV2080_CTRL_CMD_FB_GET_NUMA_INFO, + pParams, sizeof(*pParams)); + + RmUnixRmApiEpilogue(nv, &threadState); + + if (status == NV_OK) + { + NvU32 i; + + numa_info->nid = pParams->numaNodeId; + numa_info->numa_mem_addr = pParams->numaMemAddr; + numa_info->numa_mem_size = pParams->numaMemSize; + numa_info->offline_addresses.numEntries = + pParams->numaOfflineAddressesCount; + + for (i = 0; i < pParams->numaOfflineAddressesCount; i++) + { + numa_info->offline_addresses.addresses[i] = + pParams->numaOfflineAddresses[i]; + } + } + +finish: + portMemFree(pParams); + + NV_EXIT_RM_RUNTIME(sp,fp); + + return status; +} + +NV_STATUS NV_API_CALL rm_gpu_numa_online( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS params = { 0 }; + RM_API *pRmApi; + THREAD_STATE_NODE threadState; + void *fp; + NV_STATUS status = NV_OK; + + NV_ENTER_RM_RUNTIME(sp,fp); + + pRmApi = RmUnixRmApiPrologue(nv, &threadState, RM_LOCK_MODULES_MEM); + if (pRmApi == NULL) + { + status = NV_ERR_INVALID_STATE; + goto finish; + } + + params.bOnline = NV_TRUE; + + status = pRmApi->Control(pRmApi, nv->rmapi.hClient, nv->rmapi.hSubDevice, + NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS, + ¶ms, sizeof(params)); + + RmUnixRmApiEpilogue(nv, &threadState); + +finish: + NV_EXIT_RM_RUNTIME(sp,fp); + + return status; +} + + +NV_STATUS NV_API_CALL rm_gpu_numa_offline( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS params = { 0 }; + RM_API *pRmApi; + THREAD_STATE_NODE threadState; + void *fp; + NV_STATUS status = NV_OK; + + NV_ENTER_RM_RUNTIME(sp,fp); + + pRmApi = RmUnixRmApiPrologue(nv, &threadState, RM_LOCK_MODULES_MEM); + if (pRmApi == NULL) + { + status = NV_ERR_INVALID_STATE; + goto finish; + } + + params.bOnline = NV_FALSE; + + status = pRmApi->Control(pRmApi, nv->rmapi.hClient, + nv->rmapi.hSubDevice, + NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS, + ¶ms, sizeof(params)); + + RmUnixRmApiEpilogue(nv, &threadState); + +finish: + NV_EXIT_RM_RUNTIME(sp,fp); + + return status; +} + +// +// A device is considered "sequestered" if it has drain state enabled for it. +// The kernel interface layer can use this to check the drain state of a device +// in paths outside of initialization, e.g., when clients attempt to reference +// count the device. +// +NvBool NV_API_CALL rm_is_device_sequestered( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + THREAD_STATE_NODE threadState; + void *fp; + NvBool bDrain = NV_FALSE; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // + // If gpumgrQueryGpuDrainState succeeds, bDrain will be set as needed. + // If gpumgrQueryGpuDrainState fails, bDrain will stay false; we assume + // that if core RM can't tell us the drain state, it must not be + // attached and the "sequestered" question is not relevant. + // + (void) gpumgrQueryGpuDrainState(pNv->gpu_id, &bDrain, NULL); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + return bDrain; +} + +void NV_API_CALL rm_check_for_gpu_surprise_removal( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + THREAD_STATE_NODE threadState; + void *fp; + NV_STATUS rmStatus; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock. + if ((rmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU)) == NV_OK) + { + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + + if ((rmStatus = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_GPU)) == NV_OK) + { + osHandleGpuLost(pGpu, NV_TRUE); + rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); + } + + // UNLOCK: release api lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NV_STATUS NV_API_CALL rm_set_external_kernel_client_count( + nvidia_stack_t *sp, + nv_state_t *pNv, + NvBool bIncr +) +{ + THREAD_STATE_NODE threadState; + void *fp; + OBJGPU *pGpu; + NV_STATUS rmStatus = NV_OK; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + pGpu = NV_GET_NV_PRIV_PGPU(pNv); + + if (pGpu != NULL) + { + rmStatus = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_GPU); + if (rmStatus == NV_OK) + { + rmStatus = gpuSetExternalKernelClientCount(pGpu, bIncr); + rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); + } + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NvBool rm_get_uefi_console_status( + nv_state_t *nv +) +{ + NvU32 fbWidth, fbHeight, fbDepth, fbPitch; + NvU64 fbSize; + NvU64 fbBaseAddress = 0; + NvBool bConsoleDevice = NV_FALSE; + + // + // nv_get_screen_info() will return dimensions and an address for + // any fbdev driver (e.g., efifb, vesafb, etc). + // + nv_get_screen_info(nv, &fbBaseAddress, &fbWidth, &fbHeight, &fbDepth, &fbPitch, &fbSize); + + bConsoleDevice = (fbSize != 0); + + return bConsoleDevice; +} + +NvU64 rm_get_uefi_console_size( + nv_state_t *nv, + NvU64 *pFbBaseAddress +) +{ + NvU32 fbWidth, fbHeight, fbDepth, fbPitch; + NvU64 fbSize; + + fbSize = fbWidth = fbHeight = fbDepth = fbPitch = 0; + + // + // nv_get_screen_info() will return dimensions and an address for + // any fbdev driver (e.g., efifb, vesafb, etc). + // + nv_get_screen_info(nv, pFbBaseAddress, &fbWidth, &fbHeight, &fbDepth, &fbPitch, &fbSize); + + return fbSize; +} + +NvBool NV_API_CALL rm_disable_iomap_wc(void) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = pSys->pCl; + return pCl->getProperty(pCl, PDB_PROP_CL_DISABLE_IOMAP_WC) == NV_TRUE; +} + +// +// Verifies the handle, offset and size and dups hMemory. +// Must be called with API lock and GPU lock held. +// +NV_STATUS NV_API_CALL rm_dma_buf_dup_mem_handle( + nvidia_stack_t *sp, + nv_state_t *nv, + NvHandle hSrcClient, + NvHandle hDstClient, + NvHandle hDevice, + NvHandle hSubdevice, + void *pGpuInstanceInfo, + NvHandle hMemory, + NvU64 offset, + NvU64 size, + NvU8 mappingType, + NvHandle *phMemoryDuped, + void **ppMemInfo, + NvBool *pbCanMmap, + NvU32 *pCacheType, + NvBool *pbReadOnlyMem, + nv_memory_type_t *pMemoryType +) +{ + MEMORY_DESCRIPTOR *pMemDesc; + THREAD_STATE_NODE *pThreadState; + NV_STATUS rmStatus = NV_ERR_NO_MEMORY; + OBJGPU *pGpu; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + pThreadState = threadStateAlloc(THREAD_STATE_FLAGS_NONE); + NV_ASSERT_OR_GOTO(pThreadState != NULL, Done); + + pGpu = NV_GET_NV_PRIV_PGPU(nv); + + NV_ASSERT(rmapiLockIsOwner()); + + NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); + + rmStatus = RmDmabufVerifyMemHandle(pGpu, hSrcClient, hMemory, + offset, size, pGpuInstanceInfo, + &pMemDesc); + if (rmStatus == NV_OK) + { + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NvHandle hMemoryDuped = 0; + + rmStatus = pRmApi->DupObject(pRmApi, + hDstClient, + hDevice, + &hMemoryDuped, + hSrcClient, + hMemory, + 0); + if (rmStatus == NV_OK) + { + *phMemoryDuped = hMemoryDuped; + } + else if (rmStatus == NV_ERR_INVALID_OBJECT_PARENT) + { + hMemoryDuped = 0; + + // If duping under Device fails, try duping under Subdevice + rmStatus = pRmApi->DupObject(pRmApi, + hDstClient, + hSubdevice, + &hMemoryDuped, + hSrcClient, + hMemory, + 0); + if (rmStatus == NV_OK) + { + *phMemoryDuped = hMemoryDuped; + } + } + *ppMemInfo = (void *) pMemDesc; + + *pCacheType = RmDmabufMmapGetCpuCacheType(pGpu, pMemDesc, mappingType); + *pbReadOnlyMem = memdescGetFlag(pMemDesc, MEMDESC_FLAGS_USER_READ_ONLY); + + if (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_PEER_IO_MEM)) + { + *pMemoryType = NV_MEMORY_TYPE_DEVICE_MMIO; + } + else if (memdescGetAddressSpace(pMemDesc) == ADDR_SYSMEM) + { + *pMemoryType = NV_MEMORY_TYPE_SYSTEM; + } + else + { + // TODO: Assume NV_MEMORY_TYPE_FRAMEBUFFER is for now. + // Add Proper handling for NV_MEMORY_TYPE_REGISTERS. + *pMemoryType = NV_MEMORY_TYPE_FRAMEBUFFER; + } + + // mmap is allowed on 0FB chips(iGPU) for sysmem and on dGPU for vidmem only + *pbCanMmap = (pGpu->pGpuArch->bGpuArchIsZeroFb || + (memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM)); + } + +Done: + if (pThreadState != NULL) + threadStateFree(pThreadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +// +// Frees dup'd hMemory. +// Must be called with API lock and GPU lock held. +// +void NV_API_CALL rm_dma_buf_undup_mem_handle( + nvidia_stack_t *sp, + nv_state_t *nv, + NvHandle hClient, + NvHandle hMemory +) +{ + THREAD_STATE_NODE threadState; + RM_API *pRmApi; + OBJGPU *pGpu; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + pGpu = NV_GET_NV_PRIV_PGPU(nv); + + NV_ASSERT(rmapiLockIsOwner()); + + NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); + + pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + pRmApi->Free(pRmApi, hClient, hMemory); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +// +// Maps a handle to system physical addresses: +// C2C for coherent platforms with DEFAULT mapping type +// BAR1(static & dynamic) for non-coherent platforms and for +// coherent platforms with mapping type FORCE_PCIE +// Must be called with API lock and GPU lock held for dynamic BAR1. +// +NV_STATUS NV_API_CALL rm_dma_buf_map_mem_handle( + nvidia_stack_t *sp, + nv_state_t *nv, + NvHandle hClient, + NvHandle hMemory, + MemoryRange memRange, + NvU8 mappingType, + void *pMemInfo, + NvBool bStaticPhysAddrs, + MemoryArea *pMemArea +) +{ + THREAD_STATE_NODE *pThreadState; + NV_STATUS rmStatus = NV_ERR_INVALID_ARGUMENT; + OBJGPU *pGpu; + MEMORY_DESCRIPTOR *pMemDesc; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + pThreadState = threadStateAlloc(THREAD_STATE_FLAGS_NONE); + if (pThreadState == NULL) + { + NV_ASSERT(0); + rmStatus = NV_ERR_NO_MEMORY; + goto Done; + } + + NV_ASSERT_OR_GOTO(((pMemArea != NULL) && + (pMemInfo != NULL)) && + (memRange.size != 0), Done); + + pGpu = NV_GET_NV_PRIV_PGPU(nv); + pMemDesc = (MEMORY_DESCRIPTOR *) pMemInfo; + + if (((pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) || + (pGpu->pGpuArch->bGpuArchIsZeroFb)) && + (mappingType == NV_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT)) + { + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + NvBool contiguity = memdescCheckContiguity(pMemDesc, AT_CPU); + + // On localized allocations over C2C/nvlink mappings, RDMA is not supported + if (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_AS_LOCALIZED)) + { + NV_PRINTF(LEVEL_ERROR, "RDMA is not supported for localized memory" + " over coherent mappings\n"); + rmStatus = NV_ERR_NOT_SUPPORTED; + goto Done; + } + + if (contiguity) + { + NvU64 physAddr = memdescGetPhysAddr(pMemDesc, AT_CPU, memRange.start); + + NV_ASSERT_OK_OR_GOTO(rmStatus, os_alloc_mem((void **) &pMemArea->pRanges, + sizeof(MemoryRange)), Done); + + pMemArea->pRanges[0].start = pKernelMemorySystem->coherentCpuFbBase + physAddr; + pMemArea->pRanges[0].size = memRange.size; + pMemArea->numRanges = 1; + } + else + { + NvU64 idx = 0; + NvU64 memdescPageSize = memdescGetPageSize(pMemDesc, AT_CPU); + NvU64 origEnd = memRange.start + memRange.size; + NvU64 realStart = NV_ALIGN_DOWN64(memRange.start, memdescPageSize); + NvU64 realEnd = NV_ALIGN_UP64(memRange.start + memRange.size, memdescPageSize); + NvU64 realSize = realEnd - realStart; + NvU64 pageCount = realSize / memdescPageSize; + + NV_ASSERT_OK_OR_GOTO(rmStatus, os_alloc_mem((void **) &pMemArea->pRanges, + pageCount * sizeof(MemoryRange)), Done); + + for(idx = 0; idx < pageCount; idx++) + { + NvU64 physAddr = memdescGetPhysAddr(pMemDesc, AT_CPU, + realStart + (idx * memdescPageSize)); + pMemArea->pRanges[idx].start = pKernelMemorySystem->coherentCpuFbBase + physAddr; + pMemArea->pRanges[idx].size = memdescPageSize; + } + + pMemArea->pRanges[0].start += (memRange.start - realStart); + pMemArea->pRanges[0].size -= (memRange.start - realStart); + pMemArea->pRanges[pageCount - 1llu].size -= (realEnd - origEnd); + + pMemArea->numRanges = pageCount; + } + } + else + { + Device *pDevice = NULL; + RsClient *pClient; + NvU64 idx; + NvU64 barOffset; + KernelBus *pKernelBus; + NvBool bForcePcie; + + pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + + if (!bStaticPhysAddrs) + { + // Dynamic BAR1 requires RMAPI and GPU lock to be held + NV_ASSERT(rmapiLockIsOwner()); + NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); + + NV_ASSERT_OK_OR_GOTO(rmStatus, + serverGetClientUnderLock(&g_resServ, hClient, &pClient), + Done); + + NV_ASSERT_OK_OR_GOTO(rmStatus, + deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice), + Done); + } + + NV_CHECK_OR_GOTO(LEVEL_ERROR, + memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM, + Done); + + // + // We don't take locks for static BAR1. + // Thus, we operate directly on the memdesc passed to + // bypass the client lookup which requires client locks. + // + NV_ASSERT_OK_OR_GOTO(rmStatus, + kbusMapFbAperture_HAL(pGpu, pKernelBus, pMemDesc, memRange, pMemArea, + (BUS_MAP_FB_FLAGS_MAP_UNICAST | BUS_MAP_FB_FLAGS_ALLOW_DISCONTIG), + pDevice), + Done); + + bForcePcie = (mappingType == NV_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE); + + NV_ASSERT_OK_OR_GOTO(rmStatus, + kbusGetGpuFbPhysAddressForRdma(pGpu, pKernelBus, + bForcePcie, &barOffset), + Done); + + for (idx = 0; idx < pMemArea->numRanges; idx++) + { + pMemArea->pRanges[idx].start += barOffset; + } + } + +Done: + if (pThreadState != NULL) + threadStateFree(pThreadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +// +// Unmaps a handle that was mapped to system physical addresses. +// Must be called with API lock and GPU lock held for dynamic BAR1. +// +void NV_API_CALL rm_dma_buf_unmap_mem_handle( + nvidia_stack_t *sp, + nv_state_t *nv, + NvHandle hClient, + NvHandle hMemory, + NvU8 mappingType, + void *pMemInfo, + NvBool bStaticPhysAddrs, + MemoryArea memArea +) +{ + THREAD_STATE_NODE threadState; + OBJGPU *pGpu; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + pGpu = NV_GET_NV_PRIV_PGPU(nv); + + if ((pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) || + pGpu->pGpuArch->bGpuArchIsZeroFb) && + (mappingType == NV_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT)) + { + os_free_mem(memArea.pRanges); + } + else + { + KernelBus *pKernelBus; + NvU64 idx; + NvU64 barOffset; + MEMORY_DESCRIPTOR *pMemDesc = (MEMORY_DESCRIPTOR *) pMemInfo; + NvBool bForcePcie = (mappingType == NV_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE); + + pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + + NV_ASSERT_OK(kbusGetGpuFbPhysAddressForRdma(pGpu, pKernelBus, + bForcePcie, &barOffset)); + + for (idx = 0; idx < memArea.numRanges; idx++) + { + memArea.pRanges[idx].start -= barOffset; + } + + if (!bStaticPhysAddrs) + { + // Dynamic BAR1 requires RMAPI and GPU lock to be held + NV_ASSERT(rmapiLockIsOwner()); + NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); + } + + // + // We don't take locks for static BAR1. + // Thus, we operate directly on the memdesc passed to + // bypass the client lookup which requires client locks. + // + NV_ASSERT_OK(kbusUnmapFbAperture_HAL(pGpu, pKernelBus, pMemDesc, memArea, + BUS_MAP_FB_FLAGS_MAP_UNICAST)); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device( + nvidia_stack_t *sp, + nv_state_t *nv, + NvHandle hClient, + NvHandle hMemory, + NvU8 mappingType, + NvHandle *phClient, + NvHandle *phDevice, + NvHandle *phSubdevice, + void **ppGpuInstanceInfo, + NvBool *pbStaticPhysAddrs, + NvBool *pbAcquireReleaseAllGpuLockOnDup +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI); + if (rmStatus == NV_OK) + { + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + + rmStatus = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI); + if (rmStatus == NV_OK) + { + rmStatus = RmDmabufGetClientAndDevice(pGpu, hClient, hMemory, mappingType, + phClient, phDevice, + phSubdevice, ppGpuInstanceInfo); + if (rmStatus == NV_OK) + { + *pbStaticPhysAddrs = ((pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) || + pGpu->pGpuArch->bGpuArchIsZeroFb) && + (mappingType == NV_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT)) || + kbusIsStaticBar1Enabled(pGpu, GPU_GET_KERNEL_BUS(pGpu)); + } + + *pbAcquireReleaseAllGpuLockOnDup = pGpu->pGpuArch->bGpuArchIsZeroFb; + + rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); + } + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +void NV_API_CALL rm_dma_buf_put_client_and_device( + nvidia_stack_t *sp, + nv_state_t *nv, + NvHandle hClient, + NvHandle hDevice, + NvHandle hSubdevice, + void *pGpuInstanceInfo +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI); + if (rmStatus == NV_OK) + { + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + + rmStatus = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI); + if (rmStatus == NV_OK) + { + RmDmabufPutClientAndDevice(pGpu, hClient, hDevice, hSubdevice, + pGpuInstanceInfo); + + rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); + } + + // UNLOCK: release API lock + rmapiLockRelease(); + } + NV_ASSERT_OK(rmStatus); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +// +// Fetches GSP ucode data for usage during RM Init +// NOTE: Used only on VMWware +// + +void NV_API_CALL rm_vgpu_vfio_set_driver_vm( + nvidia_stack_t *sp, + NvBool is_driver_vm +) +{ + OBJSYS *pSys; + OBJHYPERVISOR *pHypervisor; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + pSys = SYS_GET_INSTANCE(); + pHypervisor = SYS_GET_HYPERVISOR(pSys); + + pHypervisor->setProperty(pHypervisor, PDB_PROP_HYPERVISOR_DRIVERVM_ENABLED, is_driver_vm); + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NvBool NV_API_CALL rm_is_altstack_in_use(void) +{ +#if defined(__use_altstack__) + return NV_TRUE; +#else + return NV_FALSE; +#endif +} + +void NV_API_CALL rm_acpi_nvpcf_notify( + nvidia_stack_t *sp +) +{ + void *fp; + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_OK; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_EVENT)) == NV_OK) + { + OBJGPU *pGpu = gpumgrGetGpu(0); + if (pGpu != NULL) + { + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + if ((rmStatus = os_ref_dynamic_power(nv, NV_DYNAMIC_PM_FINE)) == + NV_OK) + { + gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_NVPCF_EVENTS, + NULL, 0, 0, 0); + } + os_unref_dynamic_power(nv, NV_DYNAMIC_PM_FINE); + } + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +static void rm_notify_gpu_addition_removal_helper( + nv_state_t *nv, + NvBool bBind) +{ + THREAD_STATE_NODE threadState; + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI) == NV_OK) + { + NV0000_CTRL_SYSTEM_EVENT_DATA_GPU_BIND_UNBIND eventData = { 0 }; + + eventData.gpuId = nv->gpu_id; + eventData.bBind = bBind; + + CliAddSystemEvent(NV0000_NOTIFIERS_GPU_BIND_UNBIND_EVENT, &eventData, NULL); + rmapiLockRelease(); + } + else + { + NV_PRINTF(LEVEL_ERROR, "Fail to acquire rmApi lock. Skip notification."); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); +} + +void NV_API_CALL rm_notify_gpu_addition( + nvidia_stack_t *sp, + nv_state_t *nv) +{ + void *fp = NULL; + + NV_ENTER_RM_RUNTIME(sp,fp); + rm_notify_gpu_addition_removal_helper(nv, NV_TRUE); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +void NV_API_CALL rm_notify_gpu_removal( + nvidia_stack_t *sp, + nv_state_t *nv) +{ + void *fp = NULL; + + NV_ENTER_RM_RUNTIME(sp,fp); + rm_notify_gpu_addition_removal_helper(nv, NV_FALSE); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NvBool NV_API_CALL rm_wait_for_bar_firewall( + nvidia_stack_t * sp, + NvU32 domain, + NvU8 bus, + NvU8 device, + NvU8 function, + NvU16 devId, + NvU16 subsystemId +) +{ + NvBool ret; + void *fp = NULL; + + // no state set up yet for threadstate or RM locks + NV_ENTER_RM_RUNTIME(sp,fp); + ret = gpumgrWaitForBarFirewall(domain, bus, device, function, devId, subsystemId); + NV_EXIT_RM_RUNTIME(sp,fp); + + return ret; +} + +static NvU32 devfreq_clk_to_domain( + TEGRASOC_DEVFREQ_CLK devfreqClk +) +{ + NvU32 clkDomain = NV2080_CTRL_CLK_DOMAIN_TEGRA_UNDEFINED; + switch (devfreqClk) + { + case TEGRASOC_DEVFREQ_CLK_GPC: + clkDomain = NV2080_CTRL_CLK_DOMAIN_TEGRA_GPCCLK; + break; + + case TEGRASOC_DEVFREQ_CLK_NVD: + clkDomain = NV2080_CTRL_CLK_DOMAIN_TEGRA_NVDCLK; + break; + + default: + break; + } + + return clkDomain; +} + +NV_STATUS NV_API_CALL rm_pmu_perfmon_get_load( + nvidia_stack_t *sp, + nv_state_t *nv, + NvU32 *load, + TEGRASOC_DEVFREQ_CLK devfreqClk +) +{ + NV2080_CTRL_PERF_GET_TEGRA_PERFMON_SAMPLE_PARAMS params = { 0 }; + NvU32 clkDomain = devfreq_clk_to_domain(devfreqClk); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + RM_API *pRmApi; + NV_STATUS status; + void *fp; + + if (clkDomain == NV2080_CTRL_CLK_DOMAIN_TEGRA_UNDEFINED) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (nvp->dynamic_power.state == NV_DYNAMIC_POWER_STATE_IDLE_INDICATED) + { + *load = 0; + return NV_OK; + } + + NV_ENTER_RM_RUNTIME(sp, fp); + + if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI) == NV_OK) + { + pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); + if (pRmApi == NULL) + { + status = NV_ERR_INVALID_STATE; + rmapiLockRelease(); + goto rm_pmu_perfmon_get_load_exit; + } + + params.clkDomain = clkDomain; + status = pRmApi->Control(pRmApi, nv->rmapi.hClient, nv->rmapi.hSubDevice, + NV2080_CTRL_CMD_PERF_GET_TEGRA_PERFMON_SAMPLE, + ¶ms, sizeof(params)); + if (status == NV_OK) + { + *load = params.clkPercentBusy; + } + + rmapiLockRelease(); + } + else + { + status = NV_ERR_INVALID_STATE; + } + +rm_pmu_perfmon_get_load_exit: + NV_EXIT_RM_RUNTIME(sp, fp); + + return status; +} diff --git a/userspace/sdks/nv570/nvalloc/unix/src/osinit.c b/userspace/sdks/nv570/nvalloc/unix/src/osinit.c new file mode 100644 index 0000000..b3fd343 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/src/osinit.c @@ -0,0 +1,2768 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/************************************************************************************************************** +* +* Description: +* UNIX-general, device-independent initialization code for +* the resource manager. +* +* +**************************************************************************************************************/ + +#include +#include // NV device driver interface +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "gpu/gpu.h" +#include +#include "gpu/bus/kern_bus.h" +#include "nverror.h" +#include +#include +#include +#include +#include "kernel/gpu/intr/intr.h" +#include +#include +#include +#include +#include +#include +#include +#include "liblogdecode.h" + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "platform/nbsi/nbsi_read.h" +#include "gpu_mgr/gpu_db.h" +#include +#include +#include +#include +#include + +#include +// RMCONFIG: need definition of REGISTER_ALL_HALS() +#include "g_hal_register.h" + +typedef enum +{ + RM_INIT_OK, + + /* general os errors */ + RM_INIT_REG_SETUP_FAILED = 0x10, + RM_INIT_SYS_ENVIRONMENT_FAILED, + + /* gpu errors */ + RM_INIT_GPU_GPUMGR_ALLOC_GPU_FAILED = 0x20, + RM_INIT_GPU_GPUMGR_CREATE_DEV_FAILED, + RM_INIT_GPU_GPUMGR_ATTACH_GPU_FAILED, + RM_INIT_GPU_PRE_INIT_FAILED, + RM_INIT_GPU_STATE_INIT_FAILED, + RM_INIT_GPU_LOAD_FAILED, + RM_INIT_GPU_DMA_CONFIGURATION_FAILED, + RM_INIT_GPU_GPUMGR_EXPANDED_VISIBILITY_FAILED, + + /* vbios errors */ + RM_INIT_VBIOS_FAILED = 0x30, + RM_INIT_VBIOS_POST_FAILED, + RM_INIT_VBIOS_X86EMU_FAILED, + + /* scalability errors */ + RM_INIT_SCALABILITY_FAILED = 0x40, + + /* general core rm errors */ + RM_INIT_WATCHDOG_FAILED, + RM_FIFO_GET_UD_BAR1_MAP_INFO_FAILED, + RM_GPUDB_REGISTER_FAILED, + + RM_INIT_ALLOC_RMAPI_FAILED, + RM_INIT_GPUINFO_WITH_RMAPI_FAILED, + + /* rm firmware errors */ + RM_INIT_FIRMWARE_POLICY_FAILED = 0x60, + RM_INIT_FIRMWARE_FETCH_FAILED, + RM_INIT_FIRMWARE_INIT_FAILED, + + RM_INIT_MAX_FAILURES +} rm_init_status; + +typedef rm_init_status RM_INIT_STATUS; + +typedef struct { + RM_INIT_STATUS initStatus; + NV_STATUS rmStatus; + NvU32 line; +} UNIX_STATUS; + +#define INIT_UNIX_STATUS { RM_INIT_OK, NV_OK, 0 } +#define RM_INIT_SUCCESS(init) ((init) == RM_INIT_OK) + +#define RM_SET_ERROR(status, err) { (status).initStatus = (err); \ + (status).line = __LINE__; } + + +static inline NvU64 nv_encode_pci_info(nv_pci_info_t *pci_info) +{ + return gpuEncodeDomainBusDevice(pci_info->domain, pci_info->bus, pci_info->slot); +} + +static inline NvU32 nv_generate_id_from_pci_info(nv_pci_info_t *pci_info) +{ + return gpuGenerate32BitId(pci_info->domain, pci_info->bus, pci_info->slot); +} + +static void nv_set_probed_gpu_flags(nv_state_t *nv) +{ + NvU32 flags = 0; + + if (NV_IS_SOC_DISPLAY_DEVICE(nv)) + { + flags |= DRF_DEF(0000, _CTRL_GPU_PROBED_ID_FLAGS, _SOC_DISPLAY, _TRUE); + } + + gpumgrSetProbedFlags(nv->gpu_id, flags); +} + +static inline void nv_os_map_kernel_space(nv_state_t *nv, nv_aperture_t *aperture) +{ + NV_ASSERT(aperture->map == NULL); + + // let's start off assuming a standard device and map the registers + // normally. It is unfortunate to hard-code the register size here, but we don't + // want to fail trying to map all of a multi-devices' register space + aperture->map = osMapKernelSpace(aperture->cpu_address, + aperture->size, + NV_MEMORY_UNCACHED, + NV_PROTECT_READ_WRITE); + aperture->map_u = (nv_phwreg_t)aperture->map; +} + +// local prototypes +static NV_STATUS initCoreLogic(OBJGPU *); +static void initVendorSpecificRegistry(OBJGPU *, NvU16); +static NV_STATUS teardownCoreLogic(OBJOS *, OBJGPU *); +static void initUnixSpecificRegistry(OBJGPU *); + +NV_STATUS osRmInitRm(void) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + NV_STATUS status; + + if (os_is_efi_enabled()) + { + pSys->setProperty(pSys, PDB_PROP_SYS_IS_UEFI, NV_TRUE); + } + + // have to init this before the debug subsystem, which will + // try to check the value of ResmanDebugLevel + RmInitRegistry(); + + NvU32 data = 0; + if ((osReadRegistryDword(NULL, + NV_REG_ENABLE_PCIE_GEN3, &data) == NV_OK) && + (data != 0)) + { + data = DRF_DEF(_REG_STR, _RM_PCIE, _LINK_SPEED_ALLOW_GEN3, _ENABLE); + + osWriteRegistryDword(NULL, + NV_REG_STR_RM_PCIE_LINK_SPEED, data); + } + + if (!(osReadRegistryDword(NULL, + NV_REG_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS, + &data) == NV_OK) || data) + { + pSys->setProperty(pSys, + PDB_PROP_SYS_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS, + NV_TRUE); + } + + if ((osReadRegistryDword(NULL, + NV_REG_ENABLE_STREAM_MEMOPS, + &data) == NV_OK) && (data != 0)) + { + data = DRF_DEF(_REG_STR, _RM_STREAM_MEMOPS, _ENABLE, _YES); + osWriteRegistryDword(NULL, NV_REG_STR_RM_STREAM_MEMOPS, data); + } + + if ((osReadRegistryDword(NULL, + NV_REG_STR_RM_FORCE_BAR_PATH, + &data) == NV_OK) && (data == 1)) + { + // + // Exposing the GPU memory as NUMA node memory requires coherent CPU + // mappings over NVLink. If those mappings are disabled, also disable + // NUMA-onlining of the device memory. + // + osWriteRegistryDword(NULL, + NV_REG_ENABLE_USER_NUMA_MANAGEMENT, 0); + } + + if ((osReadRegistryDword(NULL, + NV_REG_NVLINK_DISABLE, &data) == NV_OK) && + (data == 1)) + { + osWriteRegistryDword(NULL, NV_REG_STR_RM_NVLINK_CONTROL, 0x1); + } + + if ((osReadRegistryDword(NULL, + NV_REG_ENABLE_PCIE_RELAXED_ORDERING_MODE, &data) == NV_OK) && + (data == 1)) + { + osWriteRegistryDword(NULL, + NV_REG_STR_RM_SET_PCIE_TLP_RELAXED_ORDERING, + NV_REG_STR_RM_SET_PCIE_TLP_RELAXED_ORDERING_ENABLE); + } + + // init the debug subsystem if necessary + os_dbg_init(); + nvDbgInitRmMsg(NULL); + + // Force nvlog reinit since module params are now available + NVLOG_UPDATE(); + + // Register all supported hals + status = REGISTER_ALL_HALS(); + if (status != NV_OK) + { + RmDestroyRegistry(NULL); + return status; + } + + rm_check_s0ix_regkey_and_platform_support(); + + // Setup any ThreadState defaults + threadStateInitSetupFlags(THREAD_STATE_SETUP_FLAGS_ENABLED | + THREAD_STATE_SETUP_FLAGS_TIMEOUT_ENABLED | + THREAD_STATE_SETUP_FLAGS_SLI_LOGIC_ENABLED | + THREAD_STATE_SETUP_FLAGS_DO_NOT_INCLUDE_SLEEP_TIME_ENABLED); + + return NV_OK; +} + +void RmShutdownRm(void) +{ + NV_PRINTF(LEVEL_INFO, "shutdown rm\n"); + + RmDestroyRegistry(NULL); + + // Free objects created with RmInitRm, including the system object + RmDestroyRm(); +} + +// +// osAttachGpu +// +// This routine is used as a callback by the gpumgrAttachGpu +// interface to allow os-dependent code to set up any state +// before engine construction begins. +// +NV_STATUS osAttachGpu( + OBJGPU *pGpu, + void *pOsGpuInfo +) +{ + nv_state_t *nv = (nv_state_t *)pOsGpuInfo; + nv_priv_t *nvp; + + nvp = NV_GET_NV_PRIV(nv); + + nvp->pGpu = pGpu; + + NV_SET_NV_STATE(pGpu, (void *)nv); + + initUnixSpecificRegistry(pGpu); + + // Assign default values to Registry keys for VGX + if (os_is_vgx_hyper()) + { + initVGXSpecificRegistry(pGpu); + } + + return NV_OK; +} + +NV_STATUS osDpcAttachGpu( + OBJGPU *pGpu, + void *pOsGpuInfo +) +{ + return NV_OK; // Nothing to do for unix +} + +void osDpcDetachGpu( + OBJGPU *pGpu +) +{ + return; // Nothing to do for unix +} + +NV_STATUS +osHandleGpuLost +( + OBJGPU *pGpu, + NvBool bEmitXid +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvU32 pmc_boot_0; + + // Determine if we've already run the handler + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_CONNECTED)) + { + return NV_OK; + } + + pmc_boot_0 = NV_PRIV_REG_RD32(nv->regs->map_u, NV_PMC_BOOT_0); + if (pmc_boot_0 != nvp->pmc_boot_0) + { + // + // This doesn't support PEX Reset and Recovery yet. + // This will help to prevent accessing registers of a GPU + // which has fallen off the bus. + // + if (bEmitXid) + { + nvErrorLog_va((void *)pGpu, ROBUST_CHANNEL_GPU_HAS_FALLEN_OFF_THE_BUS, + "GPU has fallen off the bus."); + } + + gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_GPU_UNAVAILABLE, NULL, + 0, ROBUST_CHANNEL_GPU_HAS_FALLEN_OFF_THE_BUS, 0); + + NV_DEV_PRINTF(NV_DBG_ERRORS, nv, "GPU has fallen off the bus.\n"); + + if (pGpu->boardInfo != NULL && pGpu->boardInfo->serialNumber[0] != '\0') + { + NV_DEV_PRINTF(NV_DBG_ERRORS, nv, + "GPU serial number is %s.\n", + pGpu->boardInfo->serialNumber); + } + + gpuSetDisconnectedProperties(pGpu); + + if (IS_GSP_CLIENT(pGpu)) + { + KernelRc *pKernelRc = GPU_GET_KERNEL_RC(pGpu); + + // Notify all channels of the error so that UVM can fail gracefully + if (pKernelRc != NULL) + { + krcRcAndNotifyAllChannels(pGpu, pKernelRc, ROBUST_CHANNEL_GPU_HAS_FALLEN_OFF_THE_BUS, NV_FALSE); + } + } + + // Initiate a crash dump immediately. + RmLogGpuCrash(pGpu); + + // Set SURPRISE_REMOVAL flag for eGPU to help in device removal. + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_EXTERNAL_GPU)) + { + nv->flags |= NV_FLAG_IN_SURPRISE_REMOVAL; + } + + DBG_BREAKPOINT(); + } + + return NV_OK; +} + +/*! + * @brief Traverse bus topology till Gpu's root port. + * If any of the intermediate bridge has TB3 supported vendorId and hotplug + * capability(not necessarily same bridge), mark the Gpu as External Gpu. + * + * @params[in] pGpu OBJGPU pointer + * @params[in] pCl OBJCL pointer + * +* @return NV_OK +* Identified to be eGPU +* @return others + * Not an eGPU / error on identfying + * + */ +NvBool +RmCheckForExternalGpu +( + OBJGPU *pGpu, + OBJCL *pCl +) +{ + NvU8 bus; + NvU32 domain; + void *handleUp; + NvU8 busUp, devUp, funcUp; + NvU16 vendorIdUp, deviceIdUp; + NvU32 portCaps, pciCaps, slotCaps; + NvU32 PCIECapPtr; + RM_API *pRmApi; + NV_STATUS status, rmStatus; + NvBool bTb3Bridge = NV_FALSE, bSlotHotPlugSupport = NV_FALSE; + NvBool iseGPUBridge = NV_FALSE; + + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + domain = gpuGetDomain(pGpu); + bus = gpuGetBus(pGpu); + do + { + // Find the upstream bridge + handleUp = clFindP2PBrdg(pCl, domain, bus, &busUp, &devUp, &funcUp, &vendorIdUp, &deviceIdUp); + if (!handleUp) + { + return iseGPUBridge; + } + + if (vendorIdUp == PCI_VENDOR_ID_INTEL) + { + // Check for the supported TB3(ThunderBolt 3) bridges. + NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS params = { 0 }; + + // LOCK: acquire GPUs lock + rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_INIT); + if (rmStatus != NV_OK) + { + return iseGPUBridge; + } + params.pciDeviceId = deviceIdUp; + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GET_EGPU_BRIDGE_INFO, + ¶ms, + sizeof(params)); + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Error 0x%08x on eGPU Approval for Bridge ID: 0x%08x\n", status, deviceIdUp); + DBG_BREAKPOINT(); + return iseGPUBridge; + } + else + { + // Check for the approved eGPU BUS TB3 + if (params.iseGPUBridge && + params.approvedBusType == NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB3) + { + bTb3Bridge = NV_TRUE; + } + } + } + + if (NV_OK != clSetPortPcieCapOffset(pCl, handleUp, &PCIECapPtr)) + { + // PCIE bridge but no cap pointer. + break; + } + + // Get the PCIE capabilities. + pciCaps = osPciReadDword(handleUp, CL_PCIE_CAP - CL_PCIE_BEGIN + PCIECapPtr); + if (CL_PCIE_CAP_SLOT & pciCaps) + { + // Get the slot capabilities. + slotCaps = osPciReadDword(handleUp, CL_PCIE_SLOT_CAP - CL_PCIE_BEGIN + PCIECapPtr); + + if ((CL_PCIE_SLOT_CAP_HOTPLUG_CAPABLE & slotCaps) && + (CL_PCIE_SLOT_CAP_HOTPLUG_SURPRISE & slotCaps)) + { + bSlotHotPlugSupport = NV_TRUE; + } + } + + if (bTb3Bridge && bSlotHotPlugSupport) + { + iseGPUBridge = NV_TRUE; + break; + } + + bus = busUp; + + // Get port caps to check if PCIE bridge is the root port + portCaps = osPciReadDword(handleUp, CL_PCIE_CAP - CL_PCIE_BEGIN + PCIECapPtr); + + } while (!CL_IS_ROOT_PORT(portCaps)); + return iseGPUBridge; +} + +static NV_STATUS +RmGetFirmwareVersion +( + nv_state_t *pNv, + RM_API *pRmApi +) +{ + NV2080_CTRL_GSP_GET_FEATURES_PARAMS gsp_params; + NV_STATUS rmStatus = NV_OK; + pNv->cached_gpu_info.firmware_version[0] = '\0'; + + rmStatus = pRmApi->Control(pRmApi, pNv->rmapi.hClient, pNv->rmapi.hSubDevice, + NV2080_CTRL_CMD_GSP_GET_FEATURES, &gsp_params, + sizeof(gsp_params)); + + if (rmStatus != NV_OK) + { + if (RMCFG_FEATURE_GSP_CLIENT_RM && pNv->request_firmware) + { + const char *pTmpString = "N/A"; + portStringCopy(pNv->cached_gpu_info.firmware_version, + sizeof(pNv->cached_gpu_info.firmware_version), + pTmpString, portStringLength(pTmpString) + 1); + } + NV_PRINTF(LEVEL_INFO, + "%s: Failed to query gpu firmware version, status=0x%x\n", + __FUNCTION__, rmStatus); + } + else + { + portMemCopy(pNv->cached_gpu_info.firmware_version, + sizeof(pNv->cached_gpu_info.firmware_version), + gsp_params.firmwareVersion, sizeof(gsp_params.firmwareVersion)); + } + + return NV_OK; +} + +static NV_STATUS +RmGetVbiosVersion +( + nv_state_t *pNv, + RM_API *pRmApi +) +{ + NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS *vbios_params; + const size_t vbiosStringLen = 15; // "xx.xx.xx.xx.xx" + NV_STATUS rmStatus = NV_OK; + + vbios_params = portMemAllocNonPaged(sizeof(*vbios_params)); + if (vbios_params == NULL) + { + return NV_ERR_NO_MEMORY;; + } + + portMemSet(vbios_params, 0, sizeof(*vbios_params)); + + vbios_params->biosInfoList[0].index = NV2080_CTRL_BIOS_INFO_INDEX_REVISION; + vbios_params->biosInfoList[1].index = NV2080_CTRL_BIOS_INFO_INDEX_OEM_REVISION; + vbios_params->biosInfoListSize = 2; + + rmStatus = pRmApi->Control(pRmApi, pNv->rmapi.hClient, + pNv->rmapi.hSubDevice, NV2080_CTRL_CMD_BIOS_GET_INFO_V2, + vbios_params, sizeof(*vbios_params)); + + if (rmStatus == NV_OK) + { + const NvU32 biosRevision = vbios_params->biosInfoList[0].data; + const NvU32 biosOEMRevision = vbios_params->biosInfoList[1].data; + + os_snprintf(pNv->cached_gpu_info.vbios_version, vbiosStringLen, + "%02x.%02x.%02x.%02x.%02x", + (biosRevision & 0xff000000) >> 24, + (biosRevision & 0x00ff0000) >> 16, + (biosRevision & 0x0000ff00) >> 8, + (biosRevision & 0x000000ff) >> 0, + biosOEMRevision); + } + else + { + NV_PRINTF(LEVEL_INFO, + "%s: Failed to query vbios version, status=0x%x\n", + __FUNCTION__, rmStatus); + } + portMemFree(vbios_params); + + return NV_OK; +} + +/* + * Initialize the required GPU information by doing RMAPI control calls + * and store the same in the UNIX specific data structures. + */ +static NV_STATUS +RmInitGpuInfoWithRmApi +( + OBJGPU *pGpu +) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pGpuInfoParams = { 0 }; + NV_STATUS status; + const NvU8 *uuid; + + // LOCK: acquire GPUs lock + status = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_INIT); + if (status != NV_OK) + { + return status; + } + + pGpuInfoParams = portMemAllocNonPaged(sizeof(*pGpuInfoParams)); + if (pGpuInfoParams == NULL) + { + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + + return NV_ERR_NO_MEMORY; + } + + + portMemSet(pGpuInfoParams, 0, sizeof(*pGpuInfoParams)); + + pGpuInfoParams->gpuInfoListSize = 3; + pGpuInfoParams->gpuInfoList[0].index = NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED; + pGpuInfoParams->gpuInfoList[1].index = NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY; + pGpuInfoParams->gpuInfoList[2].index = NV2080_CTRL_GPU_INFO_INDEX_COHERENT_GPU_MEMORY_MODE; + + status = pRmApi->Control(pRmApi, nv->rmapi.hClient, + nv->rmapi.hSubDevice, + NV2080_CTRL_CMD_GPU_GET_INFO_V2, + pGpuInfoParams, sizeof(*pGpuInfoParams)); + + if (status == NV_OK) + { + nvp->b_mobile_config_enabled = + (pGpuInfoParams->gpuInfoList[0].data == + NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_YES); + nv->dma_buf_supported = + (pGpuInfoParams->gpuInfoList[1].data == + NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES); + } + + nv->coherent = + (pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) || + pGpu->pGpuArch->bGpuArchIsZeroFb); + + // + // If coherent GPU memory mode is NONE, then GPU memory has struct page + // on coherent platforms and no struct page on non-coherent ones. + // If the mode is enabled and _NUMA, then GPU memory has struct page. + // If the mode is enabled and _DRIVER, then GPU memory doesn't have struct page. + // Tegra iGPU also falls under struct page category, although + // COHERENT_GPU_MEMORY_MODE doesn't apply there. + // + if (pGpuInfoParams->gpuInfoList[2].data == + NV2080_CTRL_GPU_INFO_INDEX_COHERENT_GPU_MEMORY_MODE_NONE) + { + nv->mem_has_struct_page = nv->coherent; + } + else + { + // If mode is not _NONE, we're already on a PDB_PROP_GPU_COHERENT_CPU_MAPPING platform. + nv->mem_has_struct_page = pGpu->pGpuArch->bGpuArchIsZeroFb || + (pGpuInfoParams->gpuInfoList[2].data == + NV2080_CTRL_GPU_INFO_INDEX_COHERENT_GPU_MEMORY_MODE_NUMA); + } + + switch (pGpuInfoParams->gpuInfoList[2].data) + { + case NV2080_CTRL_GPU_INFO_INDEX_COHERENT_GPU_MEMORY_MODE_NONE: + nv->coherent_gpu_mem_mode = NV_COHERENT_GPU_MEM_MODE_NONE; + break; + case NV2080_CTRL_GPU_INFO_INDEX_COHERENT_GPU_MEMORY_MODE_NUMA: + nv->coherent_gpu_mem_mode = NV_COHERENT_GPU_MEM_MODE_NUMA; + break; + case NV2080_CTRL_GPU_INFO_INDEX_COHERENT_GPU_MEMORY_MODE_DRIVER: + nv->coherent_gpu_mem_mode = NV_COHERENT_GPU_MEM_MODE_DRIVER; + break; + } + + portMemFree(pGpuInfoParams); + + if (status != NV_OK) + { + goto finish; + } + + uuid = RmGetGpuUuidRaw(nv); + if (uuid == NULL) + { + status = NV_ERR_GPU_UUID_NOT_FOUND; + goto finish; + } + + status = RmGetFirmwareVersion(nv, pRmApi); + if (status != NV_OK) + { + goto finish; + } + + status = RmGetVbiosVersion(nv, pRmApi); + +finish: + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + + return status; +} + +static void RmSetSocDispDeviceMappings( + GPUATTACHARG *gpuAttachArg, + nv_state_t *nv +) +{ + gpuAttachArg->socDeviceArgs.deviceMapping[SOC_DEV_MAPPING_DISP].gpuNvAddr = (GPUHWREG*) nv->regs->map; + gpuAttachArg->socDeviceArgs.deviceMapping[SOC_DEV_MAPPING_DISP].gpuNvPAddr = nv->regs->cpu_address; + gpuAttachArg->socDeviceArgs.deviceMapping[SOC_DEV_MAPPING_DISP].gpuNvLength = (NvU32) nv->regs->size; +} + +static void RmSetSocDpauxDeviceMappings( + GPUATTACHARG *gpuAttachArg, + nv_state_t *nv +) +{ +} + +static void RmSetSocHdacodecDeviceMappings( + GPUATTACHARG *gpuAttachArg, + nv_state_t *nv +) +{ +} + +static void RmSetSocMipiCalDeviceMappings( + GPUATTACHARG *gpuAttachArg, + nv_state_t *nv +) +{ +} + +static void +osInitNvMapping( + nv_state_t *nv, + NvU32 *pDeviceReference, + UNIX_STATUS *status +) +{ + OBJGPU *pGpu; + OBJSYS *pSys = SYS_GET_INSTANCE(); + GPUATTACHARG *gpuAttachArg; + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvU32 deviceInstance; + NvU32 data = 0; + NvU32 dispIsoStreamId; + NvU32 dispNisoStreamId; + + NV_PRINTF(LEVEL_INFO, "osInitNvMapping:\n"); + + // allocate the next available gpu device number + status->rmStatus = gpumgrAllocGpuInstance(pDeviceReference); + if (status->rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "*** Cannot get valid gpu instance\n"); + RM_SET_ERROR(*status, RM_INIT_GPU_GPUMGR_ALLOC_GPU_FAILED); + return; + } + + // RM_BASIC_LOCK_MODEL: allocate GPU lock + status->rmStatus = rmGpuLockAlloc(*pDeviceReference); + if (status->rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "*** cannot allocate GPU lock\n"); + RM_SET_ERROR(*status, RM_INIT_GPU_GPUMGR_ALLOC_GPU_FAILED); + return; + } + + // attach default single-entry broadcast device for this gpu + status->rmStatus = gpumgrCreateDevice(&deviceInstance, NVBIT(*pDeviceReference), NULL); + if (status->rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "*** Cannot attach bc gpu\n"); + RM_SET_ERROR(*status, RM_INIT_GPU_GPUMGR_CREATE_DEV_FAILED); + // RM_BASIC_LOCK_MODEL: free GPU lock + rmGpuLockFree(*pDeviceReference); + return; + } + + // init attach state + gpuAttachArg = portMemAllocNonPaged(sizeof(GPUATTACHARG)); + if (gpuAttachArg == NULL) + { + NV_PRINTF(LEVEL_ERROR, "*** Cannot allocate gpuAttachArg\n"); + RM_SET_ERROR(*status, RM_INIT_GPU_GPUMGR_ALLOC_GPU_FAILED); + // RM_BASIC_LOCK_MODEL: free GPU lock + rmGpuLockFree(*pDeviceReference); + return; + } + + portMemSet(gpuAttachArg, 0, sizeof(GPUATTACHARG)); + + if (NV_IS_SOC_DISPLAY_DEVICE(nv)) + { + gpuAttachArg->socDeviceArgs.specified = NV_TRUE; + + RmSetSocDispDeviceMappings(gpuAttachArg, nv); + + RmSetSocDpauxDeviceMappings(gpuAttachArg, nv); + + RmSetSocHdacodecDeviceMappings(gpuAttachArg, nv); + + RmSetSocMipiCalDeviceMappings(gpuAttachArg, nv); + + gpuAttachArg->socDeviceArgs.socChipId0 = nv->disp_sw_soc_chip_id; + + gpuAttachArg->socDeviceArgs.iovaspaceId = nv->iovaspace_id; + } + else + { + gpuAttachArg->fbPhysAddr = nv->fb->cpu_address; + gpuAttachArg->fbBaseAddr = (GPUHWREG*) 0; // not mapped + gpuAttachArg->devPhysAddr = nv->regs->cpu_address; + gpuAttachArg->regBaseAddr = (GPUHWREG*) nv->regs->map; + gpuAttachArg->intLine = 0; // don't know yet + gpuAttachArg->instPhysAddr = nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address; + gpuAttachArg->instBaseAddr = (GPUHWREG*) 0; // not mapped + + gpuAttachArg->regLength = nv->regs->size; + gpuAttachArg->fbLength = nv->fb->size; + gpuAttachArg->instLength = nv->bars[NV_GPU_BAR_INDEX_IMEM].size; + + gpuAttachArg->iovaspaceId = nv->iovaspace_id; + gpuAttachArg->cpuNumaNodeId = nv->cpu_numa_node_id; + + if (nv->iovaspace_id != NV_IOVA_DOMAIN_NONE) + { + // Default - PCIe GPUs are connected via NISO IOMMU + nv->iommus.iso_iommu_present = NV_FALSE; + nv->iommus.niso_iommu_present = NV_TRUE; + } + } + + // + // we need this to check if we are running on virtual GPU + // in gpuBindHal function later. + // + if (!NV_IS_SOC_DISPLAY_DEVICE(nv)) + { + gpuAttachArg->nvDomainBusDeviceFunc = nv_encode_pci_info(&nv->pci_info); + } + + gpuAttachArg->bRequestFwClientRm = nv->request_fw_client_rm; + + gpuAttachArg->pOsAttachArg = (void *)nv; + + // use gpu manager to attach gpu + status->rmStatus = gpumgrAttachGpu(*pDeviceReference, gpuAttachArg); + portMemFree(gpuAttachArg); + if (status->rmStatus != NV_OK) + { + gpumgrDestroyDevice(deviceInstance); + RM_SET_ERROR(*status, RM_INIT_GPU_GPUMGR_ATTACH_GPU_FAILED); + NV_PRINTF(LEVEL_ERROR, "*** Cannot attach gpu\n"); + // RM_BASIC_LOCK_MODEL: free GPU lock + rmGpuLockFree(*pDeviceReference); + return; + } + nvp->flags |= NV_INIT_FLAG_GPUMGR_ATTACH; + + pGpu = gpumgrGetGpu(*pDeviceReference); + + sysInitRegistryOverrides(pSys); + + sysApplyLockingPolicy(pSys); + + pGpu->busInfo.IntLine = nv->interrupt_line; + + if (nv->fb != NULL) + { + pGpu->registerAccess.gpuFbAddr = (GPUHWREG*) nv->fb->map; + pGpu->busInfo.gpuPhysFbAddr = nv->fb->cpu_address; + } + + // set default parent gpu + gpumgrSetParentGPU(pGpu, pGpu); + + NV_PRINTF(LEVEL_INFO, "device instance : %d\n", *pDeviceReference); + NV_PRINTF(LEVEL_INFO, "NV regs using linear address : 0x%p\n", + pGpu->deviceMappings[SOC_DEV_MAPPING_DISP].gpuNvAddr); + NV_PRINTF(LEVEL_INFO, + "NV fb using linear address : 0x%p\n", pGpu->registerAccess.gpuFbAddr); + + if (!os_is_vgx_hyper()) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_ALLOW_PAGE_RETIREMENT, NV_TRUE); + } + else + { + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_ALLOW_PAGE_RETIREMENT, NV_TRUE); + } + } + + if ((osReadRegistryDword(NULL, + NV_REG_PRESERVE_VIDEO_MEMORY_ALLOCATIONS, + &data) == NV_OK) && data) + { + if (data == NV_REG_PRESERVE_VIDEO_MEMORY_ALLOCATIONS_ENABLED) + { + nv->preserve_vidmem_allocations = NV_TRUE; + } + else if (data == NV_REG_PRESERVE_VIDEO_MEMORY_ALLOCATIONS_AUTO) + { + /* If the kernel supports suspend notifiers, enable video memory allocations */ + nv->preserve_vidmem_allocations = os_supports_kernel_suspend_notifiers(); + } + + if (nv->preserve_vidmem_allocations && nv_dev_needs_vidmem_preservation(nv)) + { + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + memmgrSetPmaForcePersistence(pMemoryManager, NV_TRUE); + + // Monolithic uses Fifolite channel which doesn't support Virtual mode + if (!pMemoryManager->bUseVirtualCopyOnSuspend) + { + pKernelMemorySystem->bPreserveComptagBackingStoreOnSuspend = NV_TRUE; + } + } + } + + // Check if SMMU can be enabled on PushBuffer Aperture + nv_get_disp_smmu_stream_ids(nv, &dispIsoStreamId, &dispNisoStreamId); + if (dispNisoStreamId != NV_U32_MAX) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_DISP_PB_REQUIRES_SMMU_BYPASS, NV_FALSE); + } + else + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_DISP_PB_REQUIRES_SMMU_BYPASS, NV_TRUE); + } + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_TRIGGER_PCIE_FLR)) + { + nv->flags |= NV_FLAG_TRIGGER_FLR; + } + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_SOC_SDM)) + { + nv->flags |= NV_FLAG_HAS_CONSOLE_IN_SYSMEM_CARVEOUT; + } +} + +static NV_STATUS +osInitScalability( + OBJGPU *pGpu +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + + // We need PCI-E chipset information very early. + if (pCl != NULL) + { + return clInitPcie(pGpu, pCl); + } + else + { + return NV_ERR_NOT_SUPPORTED; + } +} + +static NV_STATUS +osTeardownScalability( + OBJGPU *pGpu +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + + return clTeardownPcie(pGpu, pCl); +} + +static NV_STATUS +RmInitNvHal( + nv_state_t *nv, + NvU32 deviceReference, + UNIX_STATUS *status +) +{ + OBJGPU *pGpu = gpumgrGetGpu(deviceReference); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + PORT_UNREFERENCED_VARIABLE(pGpu); + + nvp->flags |= NV_INIT_FLAG_HAL; + + nvp->flags |= NV_INIT_FLAG_HAL_COMPONENTS; + + return NV_OK; +} + +static void +RmDeterminePrimaryDevice(OBJGPU *pGpu) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + // Skip updating nv->primary_vga while RM is recovering after GPU reset + if (nv->flags & NV_FLAG_IN_RECOVERY) + { + return; + } + + // + // In case of Passthru, GPU will always be secondary + // + if (IS_PASSTHRU(pGpu)) + { + return; + } + + // + // In case of VIRTUAL GPU, there is no display, hence it will be secondary + // + if (IS_VIRTUAL(pGpu)) + { + return; + } + + // + // If GPU is driving any frame buffer console(vesafb, efifb etc) + // mark the console as client driven and GPU as Primary. + // + nv->client_managed_console = rm_get_uefi_console_status(nv); + + pGpu->setProperty(pGpu, PDB_PROP_GPU_PRIMARY_DEVICE, + (nv->client_managed_console || !!nv->primary_vga)); +} + +static void +RmSetConsolePreservationParams(OBJGPU *pGpu) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + NvU64 fbBaseAddress = 0; + NvU64 fbConsoleSize = 0; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + // + // PDB_PROP_GPU_PRIMARY_DEVICE should be NV_FALSE for vGPU configuration so + // return early + // + if (os_is_vgx_hyper() || IS_VIRTUAL(pGpu)) + return; + + if (!gpuFuseSupportsDisplay_HAL(pGpu)) + { + return; + } + + // + // If this is the zero FB SOC GPU with a console in system carveout, then + // the console memory is not mapped onto the BAR. The kernel can directly + // access the console memory, while the GPU accesses system carveout memory + // through the SMMU. + // The carveout is a reserved region of system memory that doesn't get used + // in standard memory allocation. + // + // In this scenario, you don't need to reserve console memory or BAR mapping. + // + if (NV_HAS_CONSOLE_IN_SYSMEM_CARVEOUT(nv)) + { + return; + } + + // + // Check the OS layer for any video memory used by a console + // driver that should be reserved. + // + // If the console driver is using some amount of memory, its + // mapping is presumably either pointing at the start of BAR1 + // (this is the mapping the EFI GOP driver provides for + // efifb), or the upper 16MB of BAR2 (this is the mapping the + // VBIOS provides for, e.g., vesafb). + // + // In the BAR2 case, there is nothing more to do: the upper + // 16MB of BAR2 will remain in physical mode + // (see the documentation for NV_PBUS_BAR2_BLOCK in dev_bus.ref), + // and the console driver can continue to access it. + // + // In the BAR1 case, RM will put all of BAR1 into virtual + // mode, so we need to create a BAR1 mapping for the console + // driver to use. + // + fbConsoleSize = rm_get_uefi_console_size(nv, &fbBaseAddress); + + if ((fbConsoleSize > 0) && (fbBaseAddress != 0) && (pKernelBus != NULL)) + { + pKernelBus->bPreserveBar1ConsoleEnabled = + (fbBaseAddress == nv->fb->cpu_address); + } + + // + // Case for legacy console, where OS will not give console size + // and primary_vga will be set for the device. + // Hence, reserving default size for VGA text modes. + // + if ((fbConsoleSize == 0) && nv->primary_vga) + { + fbConsoleSize = 0x40000; + } + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) + { + pMemoryManager->Ram.ReservedConsoleDispMemSize = fbConsoleSize; + pMemoryManager->Ram.ReservedConsoleDispMemBase = fbBaseAddress; + } + else + { + pMemoryManager->Ram.ReservedConsoleDispMemSize = NV_ALIGN_UP(fbConsoleSize, 0x10000); + } +} + +static NV_STATUS +RmInitDeviceDma( + nv_state_t *nv +) +{ + if (nv->iovaspace_id != NV_IOVA_DOMAIN_NONE) + { + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJVMM *pVmm = SYS_GET_VMM(pSys); + OBJVASPACE *pIOVAS; + NV_STATUS status = vmmCreateVaspace(pVmm, IO_VASPACE_A, + nv->iovaspace_id, 0, 0ULL, ~0ULL, + 0ULL, 0ULL, + NULL, VASPACE_FLAGS_ENABLE_VMM, + &pIOVAS); + if (status != NV_OK) + { + return status; + } + } + + return NV_OK; +} + +static void +RmTeardownDeviceDma( + nv_state_t *nv +) +{ + if (nv->iovaspace_id != NV_IOVA_DOMAIN_NONE) + { + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJVMM *pVmm = SYS_GET_VMM(pSys); + OBJVASPACE *pIOVAS; + + if (NV_OK == vmmGetVaspaceFromId(pVmm, nv->iovaspace_id, IO_VASPACE_A, &pIOVAS)) + { + vmmDestroyVaspace(pVmm, pIOVAS); + } + } +} + +static void +RmEnableDeviceClks(nv_state_t *nv) +{ + NvU32 freqKHz = 0; + NvU32 i; + NV_STATUS ret; + + for (i = TEGRASOC_WHICH_CLK_GPU_FIRST; i <= TEGRASOC_WHICH_CLK_GPU_LAST; i++) + { + ret = nv_get_max_freq(nv, i, &freqKHz); + if (ret != NV_OK) + { + NV_PRINTF(LEVEL_INFO, "NVRM: Max Freq fetch failed for Clk:%d\n", i); + continue; + } + + ret = nv_enable_clk(nv, i); + if (ret != NV_OK) + { + NV_PRINTF(LEVEL_INFO, "NVRM: Clk prepare enable failed for Clk:%d\n", i); + continue; + } + + ret = nv_set_freq(nv, i, freqKHz); + if (ret != NV_OK) + { + NV_PRINTF(LEVEL_INFO, "NVRM: Set Freq failed for Clk:%d\n", i); + } + else + { + NV_PRINTF(LEVEL_INFO, "NVRM: Set Freq:%d for Clk:%d\n", freqKHz, i); + } + } +} + +static void +RmDisableDeviceClks(nv_state_t *nv) +{ + NvU32 i; + + for (i = TEGRASOC_WHICH_CLK_GPU_FIRST; i <= TEGRASOC_WHICH_CLK_GPU_LAST; i++) + { + nv_disable_clk(nv, i); + } +} + +static void +RmInitNvDevice( + NvU32 deviceReference, + UNIX_STATUS *status +) +{ + // set the device context + OBJGPU *pGpu = gpumgrGetGpu(deviceReference); + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + NV_PRINTF(LEVEL_INFO, "RmInitNvDevice:\n"); + + NV_PRINTF(LEVEL_INFO, + "device instance : 0x%08x\n", deviceReference); + + // initialize all engines -- calls back osInitMapping() + status->rmStatus = gpumgrStatePreInitGpu(pGpu); + if (status->rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "*** Cannot pre-initialize the device\n"); + RM_SET_ERROR(*status, RM_INIT_GPU_PRE_INIT_FAILED); + return; + } + + // Configure eGPU setting + if (RmCheckForExternalGpu(pGpu, pCl)) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_EXTERNAL_GPU, NV_TRUE); + nv->is_external_gpu = NV_TRUE; + } + status->rmStatus = gpumgrStateInitGpu(pGpu); + if (status->rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "*** Cannot initialize the device\n"); + RM_SET_ERROR(*status, RM_INIT_GPU_STATE_INIT_FAILED); + return; + } + nvp->flags |= NV_INIT_FLAG_GPU_STATE; + + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + // + // Make sure bifIsMSIEnabled() gets a chance to look up the OS PCI + // handle for this GPU. This must happen after GPU state + // initialization. + // + if (pKernelBif != NULL) + { + kbifCheckAndRearmMSI(pGpu, pKernelBif); + } + + // Set RM's interrupt enable state to zero here so that interrupts + // won't be enabled during loading + Intr *pIntr = GPU_GET_INTR(pGpu); + if (pIntr != NULL) + { + intrSetIntrEn(pIntr, INTERRUPT_TYPE_DISABLED); + } + + status->rmStatus = gpumgrStateLoadGpu(pGpu, GPU_STATE_DEFAULT); + if (status->rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "*** Cannot load state into the device\n"); + RM_SET_ERROR(*status, RM_INIT_GPU_LOAD_FAILED); + return; + } + nvp->flags |= NV_INIT_FLAG_GPU_STATE_LOAD; + + // Setup GPU scalability + (void) RmInitScalability(pGpu); + + return; +} + +NV_STATUS osInitMapping( + OBJGPU *pGpu +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + NV_PRINTF(LEVEL_INFO, "osInitMapping:\n"); + + // Some PCI BIOSs leave the ROM mapped. This causes problems if it overlays system RAM. Just disable it. + GPU_BUS_CFG_WR32(pGpu, NV_CONFIG_PCI_NV_12, 0); + + // make sure our PCI latency timer is sufficient (max it out) + GPU_BUS_CFG_WR32(pGpu, NV_CONFIG_PCI_NV_3, + DRF_DEF(_CONFIG, _PCI_NV_3, _LATENCY_TIMER, _248_CLOCKS)); + + if (pCl != NULL) + { + initCoreLogic(pGpu); + } + nvp->flags |= NV_INIT_FLAG_CORE_LOGIC; + + return NV_OK; + +} // end of osInitMapping() + +static NV_STATUS +initCoreLogic( + OBJGPU *pGpu +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + + return clInit(pGpu, pCl); +} + +static NV_STATUS +teardownCoreLogic( + OBJOS *pOS, + OBJGPU *pGpu +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + + return clTeardown(pGpu, pCl); +} + +static void RmTeardownDpauxRegisters( + nv_state_t *nv +) +{ +} + +static void RmTeardownHdacodecRegisters( + nv_state_t *nv +) +{ +} + +static void RmTeardownMipiCalRegisters( + nv_state_t *nv +) +{ +} + +static NV_STATUS +RmTeardownRegisters( + nv_state_t *nv +) +{ + NV_DEV_PRINTF(NV_DBG_SETUP, nv, "Tearing down registers\n"); + + if (nv->regs && nv->regs->map) + { + osUnmapKernelSpace(nv->regs->map, nv->regs->size); + nv->regs->map = 0; + nv->regs->map_u = NULL; + } + + RmTeardownDpauxRegisters(nv); + + RmTeardownHdacodecRegisters(nv); + + RmTeardownMipiCalRegisters(nv); + + return NV_OK; +} + +static NV_STATUS +RmSetupDpauxRegisters( + nv_state_t *nv, + UNIX_STATUS *status +) +{ + + return NV_OK; +} + +static NV_STATUS +RmSetupHdacodecRegisters( + nv_state_t *nv, + UNIX_STATUS *status +) +{ + + return NV_OK; +} + +static NV_STATUS +RmSetupMipiCalRegisters( + nv_state_t *nv, + UNIX_STATUS *status +) +{ + + return NV_OK; +} + +static void +RmSetupRegisters( + nv_state_t *nv, + UNIX_STATUS *status +) +{ + NV_STATUS ret; + + NV_DEV_PRINTF(NV_DBG_SETUP, nv, "RmSetupRegisters for 0x%x:0x%x\n", + nv->pci_info.vendor_id, nv->pci_info.device_id); + NV_DEV_PRINTF(NV_DBG_SETUP, nv, "pci config info:\n"); + NV_DEV_PRINTF(NV_DBG_SETUP, nv, " registers look like: 0x%" NvU64_fmtx " 0x%" NvU64_fmtx, + nv->regs->cpu_address, nv->regs->size); + + if (nv->fb != NULL) + { + NV_DEV_PRINTF(NV_DBG_SETUP, nv, " fb looks like: 0x%" NvU64_fmtx " 0x%" NvU64_fmtx "\n", + nv->fb->cpu_address, nv->fb->size); + } + + nv_os_map_kernel_space(nv, nv->regs); + + if (nv->regs->map == NULL) + { + NV_DEV_PRINTF(NV_DBG_ERRORS, nv, "Failed to map regs registers!!\n"); + RM_SET_ERROR(*status, RM_INIT_REG_SETUP_FAILED); + status->rmStatus = NV_ERR_OPERATING_SYSTEM; + return; + } + NV_DEV_PRINTF(NV_DBG_SETUP, nv, "Successfully mapped framebuffer and registers\n"); + NV_DEV_PRINTF(NV_DBG_SETUP, nv, "final mappings:\n"); + NV_DEV_PRINTF(NV_DBG_SETUP, nv, " regs: 0x%" NvU64_fmtx " 0x%" NvU64_fmtx " 0x%p\n", + nv->regs->cpu_address, nv->regs->size, nv->regs->map); + + ret = RmSetupDpauxRegisters(nv, status); + if (ret != NV_OK) + goto err_unmap_disp_regs; + + ret = RmSetupHdacodecRegisters(nv, status); + if (ret != NV_OK) + { + RmTeardownDpauxRegisters(nv); + goto err_unmap_disp_regs; + } + + ret = RmSetupMipiCalRegisters(nv, status); + if (ret != NV_OK) + { + RmTeardownHdacodecRegisters(nv); + RmTeardownDpauxRegisters(nv); + goto err_unmap_disp_regs; + } + + return; + +err_unmap_disp_regs: + if (nv->regs && nv->regs->map) + { + osUnmapKernelSpace(nv->regs->map, nv->regs->size); + nv->regs->map = 0; + } + + return; +} + +NvBool RmInitPrivateState( + nv_state_t *pNv +) +{ + nv_priv_t *nvp; + NvU32 gpuId; + NvU32 socChipId0 = 0; + NvU32 pmc_boot_0 = 0; + NvU32 pmc_boot_1 = 0; + NvU32 pmc_boot_42 = 0; + NvU32 dmaAddrWidth = 0; + NvU64 gpuDomainBusDevice = 0; + + NV_SET_NV_PRIV(pNv, NULL); + + if (NV_IS_SOC_DISPLAY_DEVICE(pNv)) + socChipId0 = pNv->disp_sw_soc_chip_id; + else + { + pNv->regs->map_u = os_map_kernel_space(pNv->regs->cpu_address, + os_page_size, + NV_MEMORY_UNCACHED); + if (pNv->regs->map_u == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "failed to map GPU registers (DISABLE_INTERRUPTS).\n"); + return NV_FALSE; + } + + pmc_boot_0 = NV_PRIV_REG_RD32(pNv->regs->map_u, NV_PMC_BOOT_0); + pmc_boot_1 = NV_PRIV_REG_RD32(pNv->regs->map_u, NV_PMC_BOOT_1); + pmc_boot_42 = NV_PRIV_REG_RD32(pNv->regs->map_u, NV_PMC_BOOT_42); + + os_unmap_kernel_space(pNv->regs->map_u, os_page_size); + pNv->regs->map_u = NULL; + } + + if (os_alloc_mem((void **)&nvp, sizeof(*nvp)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "failed to allocate private device state.\n"); + return NV_FALSE; + } + + if (!NV_IS_SOC_DISPLAY_DEVICE(pNv)) + { + gpuId = nv_generate_id_from_pci_info(&pNv->pci_info); + gpuDomainBusDevice = nv_encode_pci_info(&pNv->pci_info); + } + else + { + gpuId = NV0000_CTRL_GPU_INVALID_ID - 1; + gpuDomainBusDevice = 0; + } + + if (gpumgrRegisterGpuId(gpuId, gpuDomainBusDevice) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "failed to register GPU with GPU manager.\n"); + os_free_mem(nvp); + return NV_FALSE; + } + + pNv->gpu_id = gpuId; + + nv_set_probed_gpu_flags(pNv); + + pNv->iovaspace_id = nv_requires_dma_remap(pNv) ? gpuId : + NV_IOVA_DOMAIN_NONE; + pNv->cpu_numa_node_id = NV0000_CTRL_NO_NUMA_NODE; + + // Get the GpuArch instance for this architecture to determine the DMA address width. + GpuArch *pGpuArch = gpumgrGetGpuArch(pmc_boot_42, socChipId0, TEGRA_CHIP_TYPE_DEFAULT); + if (pGpuArch == NULL) + { + NV_PRINTF(LEVEL_ERROR, "failed to get GpuArch for 0x%x/0x%x.\n", + pmc_boot_42, socChipId0); + gpumgrUnregisterGpuId(gpuId); + os_free_mem(nvp); + return NV_FALSE; + } + + dmaAddrWidth = gpuarchGetDmaAddrWidth(pGpuArch); + if (dmaAddrWidth == 0) + { + dmaAddrWidth = gpuarchGetSystemPhysAddrWidth(pGpuArch); + } + nv_set_dma_address_size(pNv, dmaAddrWidth); + + pNv->is_tegra_pci_igpu = !NV_IS_SOC_DISPLAY_DEVICE(pNv) && pGpuArch->bGpuArchIsZeroFb; + // Only certain Tegra PCI iGPUs support Rail-Gating + pNv->supports_tegra_igpu_rg = pNv->is_tegra_pci_igpu && pGpuArch->bGpuarchSupportsIgpuRg; + + pNv->sysmem_mapped_console = pGpuArch->bGpuArchIsZeroFb; + + kvgpumgrAttachGpu(pNv->gpu_id); + + os_mem_set(nvp, 0, sizeof(*nvp)); + nvp->status = NV_ERR_INVALID_STATE; + nvp->pmc_boot_0 = pmc_boot_0; + nvp->pmc_boot_1 = pmc_boot_1; + nvp->pmc_boot_42 = pmc_boot_42; + nvp->db_supported = -1; + NV_SET_NV_PRIV(pNv, nvp); + + return NV_TRUE; +} + +void RmClearPrivateState( + nv_state_t *pNv +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(pNv); + NvU32 status; + void *pVbiosCopy = NULL; + void *pRegistryCopy = NULL; + NvU32 vbiosSize; + nv_i2c_adapter_entry_t i2c_adapters[MAX_I2C_ADAPTERS]; + nv_dynamic_power_t dynamicPowerCopy; + NvU32 x = 0; + NvU32 pmc_boot_0, pmc_boot_1, pmc_boot_42; + NvBool pr3_acpi_method_present = 0; + int db_supported; + + // + // Do not clear private state after GPU resets, it is used while + // recovering the GPU. Only clear the pGpu pointer, which is + // restored during next initialization cycle. + // + if (pNv->flags & NV_FLAG_IN_RECOVERY) + { + nvp->pGpu = NULL; + } + + status = nvp->status; + pVbiosCopy = nvp->pVbiosCopy; + vbiosSize = nvp->vbiosSize; + pRegistryCopy = nvp->pRegistry; + dynamicPowerCopy = nvp->dynamic_power; + pmc_boot_0 = nvp->pmc_boot_0; + pmc_boot_1 = nvp->pmc_boot_1; + pmc_boot_42 = nvp->pmc_boot_42; + pr3_acpi_method_present = nvp->pr3_acpi_method_present; + db_supported = nvp->db_supported; + + for (x = 0; x < MAX_I2C_ADAPTERS; x++) + { + i2c_adapters[x] = nvp->i2c_adapters[x]; + } + + portMemSet(nvp, 0, sizeof(nv_priv_t)); + + nvp->status = status; + nvp->pVbiosCopy = pVbiosCopy; + nvp->vbiosSize = vbiosSize; + nvp->pRegistry = pRegistryCopy; + nvp->dynamic_power = dynamicPowerCopy; + nvp->pmc_boot_0 = pmc_boot_0; + nvp->pmc_boot_1 = pmc_boot_1; + nvp->pmc_boot_42 = pmc_boot_42; + nvp->pr3_acpi_method_present = pr3_acpi_method_present; + nvp->db_supported = db_supported; + + for (x = 0; x < MAX_I2C_ADAPTERS; x++) + { + nvp->i2c_adapters[x] = i2c_adapters[x]; + } + + nvp->flags |= NV_INIT_FLAG_PUBLIC_I2C; +} + +void RmFreePrivateState( + nv_state_t *pNv +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(pNv); + + gpumgrUnregisterGpuId(pNv->gpu_id); + + kvgpumgrDetachGpu(pNv->gpu_id); + + RmDestroyRegistry(pNv); + + if (nvp != NULL) + { + portMemFree(nvp->pVbiosCopy); + os_free_mem(nvp); + } + + NV_SET_NV_PRIV(pNv, NULL); +} + +NvBool RmPartiallyInitAdapter( + nv_state_t *nv +) +{ + NV_PRINTF(LEVEL_INFO, "%s: %04x:%02x:%02x.0\n", __FUNCTION__, + nv->pci_info.domain, nv->pci_info.bus, nv->pci_info.slot); + + nv_start_rc_timer(nv); + + return NV_TRUE; +} + +static NV_STATUS +RmInitX86Emu( + OBJGPU *pGpu +) +{ + NV_STATUS status = NV_OK; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + PORT_UNREFERENCED_VARIABLE(nv); + +#if NVCPU_IS_X86_64 + status = RmInitX86EmuState(pGpu); +#else + // We don't expect a "primary VGA" adapter on non-amd64 platforms + NV_ASSERT(!NV_PRIMARY_VGA(nv)); +#endif + + return status; +} + +static NV_STATUS RmRegisterGpudb( + OBJGPU *pGpu +) +{ + NV_STATUS rmStatus; + const NvU8 *pGid; + nv_state_t *pNv = NV_GET_NV_STATE(pGpu); + + pGid = RmGetGpuUuidRaw(pNv); + if (pGid == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to get UUID\n"); + return NV_ERR_OPERATING_SYSTEM; + } + + rmStatus = gpudbRegisterGpu(pGid, &pGpu->gpuClData.upstreamPort.addr, + pGpu->busInfo.nvDomainBusDeviceFunc); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to register GPU with GPU data base\n"); + } + + return rmStatus; +} + +static void RmUnixFreeRmApi( + nv_state_t *nv +) +{ + if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DESTROY) == NV_OK) + { + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + if (nv->rmapi.hClient != 0) + { + pRmApi->Free(pRmApi, nv->rmapi.hClient, nv->rmapi.hClient); + } + + portMemSet(&nv->rmapi, 0, sizeof(nv->rmapi)); + + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } +} + +static NvBool RmUnixAllocRmApi( + nv_state_t *nv, + NvU32 deviceId +) +{ + NV_STATUS status = NV_OK; + NV0080_ALLOC_PARAMETERS deviceParams = { 0 }; + NV2080_ALLOC_PARAMETERS subDeviceParams = { 0 }; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + portMemSet(&nv->rmapi, 0, sizeof(nv->rmapi)); + + // LOCK: acquire GPUs lock + status = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_INIT); + if (status != NV_OK) + { + return status; + } + + if (pRmApi->AllocWithHandle( + pRmApi, + NV01_NULL_OBJECT, + NV01_NULL_OBJECT, + NV01_NULL_OBJECT, + NV01_ROOT, + &nv->rmapi.hClient, + sizeof(nv->rmapi.hClient)) != NV_OK) + { + goto fail; + } + + deviceParams.deviceId = deviceId; + + if (pRmApi->Alloc( + pRmApi, + nv->rmapi.hClient, + nv->rmapi.hClient, + &nv->rmapi.hDevice, + NV01_DEVICE_0, + &deviceParams, + sizeof(deviceParams)) != NV_OK) + { + goto fail; + } + + subDeviceParams.subDeviceId = 0; + + if (pRmApi->Alloc( + pRmApi, + nv->rmapi.hClient, + nv->rmapi.hDevice, + &nv->rmapi.hSubDevice, + NV20_SUBDEVICE_0, + &subDeviceParams, + sizeof(subDeviceParams)) != NV_OK) + { + goto fail; + } + + // + // The NV40_I2C allocation expected to fail, if it is disabled + // with RM config. + // + if (pRmApi->Alloc( + pRmApi, + nv->rmapi.hClient, + nv->rmapi.hSubDevice, + &nv->rmapi.hI2C, + NV40_I2C, + NULL, + 0) != NV_OK) + { + nv->rmapi.hI2C = 0; + } + + // + // The NV04_DISPLAY_COMMON allocation expected to fail for displayless + // system. nv->rmapi.hDisp value needs to be checked before doing display + // related control calls. + // + if (pRmApi->Alloc( + pRmApi, + nv->rmapi.hClient, + nv->rmapi.hDevice, + &nv->rmapi.hDisp, + NV04_DISPLAY_COMMON, + NULL, + 0) != NV_OK) + { + nv->rmapi.hDisp = 0; + } + + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + + return NV_TRUE; + +fail: + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + + RmUnixFreeRmApi(nv); + return NV_FALSE; +} + +static NV_STATUS RmFetchGspRmImages +( + nv_state_t *nv, + GSP_FIRMWARE *pGspFw, + const void **gspFwHandle, + const void **gspFwLogHandle, + const void **gspUcodesHandle +) +{ + nv_firmware_chip_family_t chipFamily; + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvU32 gpuArch = (decodePmcBoot42Architecture(nvp->pmc_boot_42) << + GPU_ARCH_SHIFT); + NvU32 gpuImpl = DRF_VAL(_PMC, _BOOT_42, _IMPLEMENTATION, nvp->pmc_boot_42); + + chipFamily = nv_firmware_get_chip_family(gpuArch, gpuImpl); + + portMemSet(pGspFw, 0, sizeof(*pGspFw)); + + *gspFwHandle = nv_get_firmware(nv, NV_FIRMWARE_TYPE_GSP, + chipFamily, + &pGspFw->pBuf, + &pGspFw->size); + + NvBool bFirmwareLoadSuccessful = *gspFwHandle != NULL; + + // + // GR-3428 development: Temporarily gated by regkey so this code can be + // decoupled from the build infra changes to package up ucodes.bin. + // + // Because loading the bindata ends up calling request_firmware() on Linux, + // and that function will always print an error to dmesg if the requested + // file is not found, we use this to skip trying to load it. + // + // Check will be removed once ucodes.bin becomes part of the driver package. + // + NvU32 data = 0; + if ((osReadRegistryDword(NULL, "GR3428ReadUcodesBin", &data) == NV_OK) && data) + { + *gspUcodesHandle = nv_get_firmware(nv, NV_FIRMWARE_TYPE_UCODES, + chipFamily, + &pGspFw->pUcodesBin, + &pGspFw->ucodesBinSize); + bFirmwareLoadSuccessful &= *gspUcodesHandle != NULL; + } + + if (!bFirmwareLoadSuccessful && !nv->allow_fallback_to_monolithic_rm) + { + NV_PRINTF(LEVEL_ERROR, "No firmware image found\n"); + return NV_ERR_NOT_SUPPORTED; + } + else if (bFirmwareLoadSuccessful) + { +#if LIBOS_LOG_DECODE_ENABLE + if (nv->enable_firmware_logs) + { + *gspFwLogHandle = nv_get_firmware(nv, NV_FIRMWARE_TYPE_GSP_LOG, + chipFamily, + &pGspFw->pLogElf, + &pGspFw->logElfSize); + if (*gspFwLogHandle == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to load gsp_log_*.bin, no GSP-RM logs will be printed (non-fatal)\n"); + } + } +#endif + nv->request_fw_client_rm = NV_TRUE; + } + else + { + nv->request_fw_client_rm = NV_FALSE; + } + + return NV_OK; +} + +static void _checkP2pChipsetSupport( + nv_state_t *nv +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + + // Check for PCIe P2P chipset support + if (!pCl->bPciePeerWriteCapable || + !pCl->bPciePeerReadCapable) + { + nv->flags |= NV_FLAG_PCI_P2P_UNSUPPORTED_CHIPSET; + } +} + +NvBool RmInitAdapter( + nv_state_t *nv +) +{ + NvU32 devicereference = 0; + UNIX_STATUS status = INIT_UNIX_STATUS; + nv_priv_t *nvp; + NvBool retVal = NV_FALSE; + OBJSYS *pSys; + OBJGPU *pGpu = NULL; + OBJOS *pOS; + KernelDisplay *pKernelDisplay; + const void *gspFwHandle = NULL; + const void *gspFwLogHandle = NULL; + const void *gspUcodesHandle = NULL; + + GSP_FIRMWARE gspFw = {0}; + PORT_UNREFERENCED_VARIABLE(gspFw); + + NV_DEV_PRINTF(NV_DBG_SETUP, nv, "RmInitAdapter\n"); + + nv->flags &= ~NV_FLAG_PASSTHRU; + nv->flags &= ~NV_FLAG_PCI_P2P_UNSUPPORTED_CHIPSET; + + RmSetupRegisters(nv, &status); + if (! RM_INIT_SUCCESS(status.initStatus) ) + goto failed; + + nvp = NV_GET_NV_PRIV(nv); + nvp->status = NV_ERR_OPERATING_SYSTEM; + + status.rmStatus = RmInitDeviceDma(nv); + if (status.rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Cannot configure the device for DMA\n"); + RM_SET_ERROR(status, RM_INIT_GPU_DMA_CONFIGURATION_FAILED); + goto shutdown; + } + + nvp->flags |= NV_INIT_FLAG_DMA; + + pSys = SYS_GET_INSTANCE(); + + // + // Get firmware from the OS, if requested, and decide if RM will run as a + // firmware client. + // + if (nv->request_firmware) + { + if (!NV_IS_SOC_DISPLAY_DEVICE(nv)) + { + status.rmStatus = RmFetchGspRmImages(nv, &gspFw, &gspFwHandle, &gspFwLogHandle, &gspUcodesHandle); + if (status.rmStatus != NV_OK) + { + RM_SET_ERROR(status, RM_INIT_FIRMWARE_FETCH_FAILED); + goto shutdown; + } + } + else + { + nv->request_fw_client_rm = NV_TRUE; + } + } + + // + // Initialization path requires expanded GPU visibility in GPUMGR + // in order to access the GPU undergoing initialization. + // + status.rmStatus = gpumgrThreadEnableExpandedGpuVisibility(); + if (status.rmStatus != NV_OK) + { + RM_SET_ERROR(status, RM_INIT_GPU_GPUMGR_EXPANDED_VISIBILITY_FAILED); + goto shutdown; + } + + + // initialize the RM device register mapping + osInitNvMapping(nv, &devicereference, &status); + if (! RM_INIT_SUCCESS(status.initStatus) ) + { + switch (status.rmStatus) + { + case NV_ERR_NOT_SUPPORTED: + nvp->status = NV_ERR_NOT_SUPPORTED; + break; + } + NV_PRINTF(LEVEL_ERROR, + "osInitNvMapping failed, bailing out of RmInitAdapter\n"); + goto shutdown; + } + + // + // now we can have a pdev for the first time... + // + pGpu = gpumgrGetGpu(devicereference); + + gpumgrSetCurrentGpuInstance(pGpu->gpuInstance); + + pOS = SYS_GET_OS(pSys); + + status.rmStatus = osInitScalability(pGpu); + if (status.rmStatus == NV_OK) + { + nvp->flags |= NV_INIT_FLAG_SCALABILITY; + } + else if (status.rmStatus != NV_ERR_NOT_SUPPORTED) + { + RM_SET_ERROR(status, RM_INIT_SCALABILITY_FAILED); + goto shutdown; + } + + // Boot GSP-RM proxy through COT command either via FSP or SEC2 + if (!IS_GSP_CLIENT(pGpu) && !IS_VIRTUAL(pGpu)) + { + status.rmStatus = gpuBootGspRmProxy(pGpu); + if (status.rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "GSP-RM proxy boot command failed.\n"); + RM_SET_ERROR(status, RM_INIT_FIRMWARE_INIT_FAILED); + goto shutdown; + } + } + + RmDeterminePrimaryDevice(pGpu); + + RmSetConsolePreservationParams(pGpu); + + RmInitAcpiMethods(pOS, pSys, pGpu); + + // This needs to run before GSP-RM is booted, or else it will timeout + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_CLKS_IN_TEGRA_SOC)) + { + NV_PRINTF(LEVEL_INFO, "Enable Clocks to Max\n"); + RmEnableDeviceClks(nv); + } + + // + // If GSP fw RM support is enabled then start the GSP microcode + // (including the task running the full instance of the RM) and + // exchange the necessary initial RPC messages before continuing + // with GPU initialization here. + // + if (IS_GSP_CLIENT(pGpu)) + { + status.rmStatus = kgspInitRm(pGpu, GPU_GET_KERNEL_GSP(pGpu), &gspFw); + if (status.rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Cannot initialize GSP firmware RM\n"); + RM_SET_ERROR(status, RM_INIT_FIRMWARE_INIT_FAILED); + goto shutdown; + } + } + else if (IS_DCE_CLIENT(pGpu)) + { + status.rmStatus = dceclientDceRmInit(pGpu, GPU_GET_DCECLIENTRM(pGpu), NV_TRUE); + if (status.rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Cannot initialize DCE firmware RM\n"); + RM_SET_ERROR(status, RM_INIT_FIRMWARE_INIT_FAILED); + goto shutdown; + } + } + else if (nv->request_fw_client_rm) + { + // We were expecting to enable GSP-RM but something went wrong. + if (!nv->allow_fallback_to_monolithic_rm) + { + RM_SET_ERROR(status, RM_INIT_FIRMWARE_POLICY_FAILED); + goto shutdown; + } + else + { + NV_PRINTF(LEVEL_NOTICE, "Falling back to monolithic RM\n"); + } + } + + pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + if (pKernelDisplay != NULL) + { + kdispSetWarPurgeSatellitesOnCoreFree(pKernelDisplay, NV_TRUE); + } + + if (IS_PASSTHRU(pGpu)) + nv->flags |= NV_FLAG_PASSTHRU; + + RmInitNvHal(nv, devicereference, &status); + if (!RM_INIT_SUCCESS(status.initStatus)) + { + NV_PRINTF(LEVEL_ERROR, + "RmInitNvHal() failed, bailing out of RmInitAdapter!\n"); + goto shutdown; + } + + status.rmStatus = RmInitX86Emu(pGpu); + if (status.rmStatus != NV_OK) + { + RM_SET_ERROR(status, RM_INIT_VBIOS_X86EMU_FAILED); + NV_PRINTF(LEVEL_ERROR, + "RmInitX86Emu failed, bailing out of RmInitAdapter\n"); + goto shutdown; + } + + + initVendorSpecificRegistry(pGpu, nv->pci_info.device_id); + + if (!IS_VIRTUAL(pGpu) && !NV_IS_SOC_DISPLAY_DEVICE(nv)) + { + initNbsiTable(pGpu); + } + + // finally, initialize the device + RmInitNvDevice(devicereference, &status); + if (! RM_INIT_SUCCESS(status.initStatus) ) + { + NV_PRINTF(LEVEL_ERROR, + "RmInitNvDevice failed, bailing out of RmInitAdapter\n"); + switch (status.rmStatus) + { + case NV_ERR_INSUFFICIENT_POWER: + nvp->status = NV_ERR_INSUFFICIENT_POWER; + NV_DEV_PRINTF(NV_DBG_ERRORS, nv, + "GPU does not have the necessary power cables connected.\n"); + break; + } + goto shutdown; + } + + // + // Expanded GPU visibility in GPUMGR is no longer needed once the + // GPU is initialized. + // + gpumgrThreadDisableExpandedGpuVisibility(); + + // LOCK: acquire GPUs lock + status.rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_INIT); + if (status.rmStatus != NV_OK) + { + goto shutdown; + } + + status.rmStatus = osVerifySystemEnvironment(pGpu); + + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + + if (status.rmStatus != NV_OK) + { + RM_SET_ERROR(status, RM_INIT_SYS_ENVIRONMENT_FAILED); + switch (status.rmStatus) + { + case NV_ERR_IRQ_NOT_FIRING: + nvp->status = NV_ERR_IRQ_NOT_FIRING; + break; + } + NV_PRINTF(LEVEL_ERROR, "osVerifySystemEnvironment failed, bailing!\n"); + goto shutdown; + } + + Intr *pIntr = GPU_GET_INTR(pGpu); + if (pIntr != NULL) + { + intrSetIntrEn(pIntr, INTERRUPT_TYPE_HARDWARE); + } + + // LOCK: acquire GPUs lock + status.rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_INIT); + if (status.rmStatus != NV_OK) + { + goto shutdown; + } + + KernelRc *pKernelRc = GPU_GET_KERNEL_RC(pGpu); + // initialize the watchdog (disabled by default) + status.rmStatus = pKernelRc != NULL ? krcWatchdogInit_HAL(pGpu, pKernelRc, NULL) : + NV_ERR_NOT_SUPPORTED; + if (status.rmStatus == NV_OK) + { + krcWatchdogDisable(pKernelRc, NULL); + nvp->flags |= NV_INIT_FLAG_FIFO_WATCHDOG; + } + else if (status.rmStatus == NV_ERR_NOT_SUPPORTED) + { + NV_PRINTF(LEVEL_INFO, + "krcWatchdogInit returned _NOT_SUPPORTED. For Kepler GPUs in PGOB mode, this is normal\n"); + } + else + { + RM_SET_ERROR(status, RM_INIT_WATCHDOG_FAILED); + NV_PRINTF(LEVEL_ERROR, + "krcWatchdogInit failed, bailing out of RmInitAdapter\n"); + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + goto shutdown; + } + + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + nv_start_rc_timer(nv); + + nvp->status = NV_OK; + + if (!RmUnixAllocRmApi(nv, devicereference)) { + RM_SET_ERROR(status, RM_INIT_ALLOC_RMAPI_FAILED); + status.rmStatus = NV_ERR_GENERIC; + goto shutdown; + } + + if (!NV_IS_SOC_DISPLAY_DEVICE(nv)) + { + status.rmStatus = RmInitGpuInfoWithRmApi(pGpu); + if (status.rmStatus != NV_OK) + { + RM_SET_ERROR(status, RM_INIT_GPUINFO_WITH_RMAPI_FAILED); + goto shutdown; + } + } + + // i2c only on master device?? + RmI2cAddGpuPorts(nv); + nvp->flags |= NV_INIT_FLAG_PUBLIC_I2C; + + // This fifo hal call will fail on pre-fermi gpus. In that case, userd + // info will remain 0 and skipped by fb mmap code + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + NvU64 udaddr = 0; + NvU32 udsize = 0; + if (pKernelFifo != NULL) + { + status.rmStatus = kfifoGetUserdBar1MapInfo_HAL(pGpu, pKernelFifo, &udaddr, &udsize); + if (status.rmStatus == NV_OK) + { + nv->ud.cpu_address = (nv->fb->cpu_address + udaddr); + nv->ud.size = udsize; + } + else if (status.rmStatus != NV_ERR_NOT_SUPPORTED) + { + RM_SET_ERROR(status, RM_FIFO_GET_UD_BAR1_MAP_INFO_FAILED); + NV_PRINTF(LEVEL_ERROR, + "kfifoGetUserdBar1MapInfo failed, bailing out of RmInitAdapter\n"); + goto shutdown; + } + } + + nv->flags &= ~NV_FLAG_IN_RECOVERY; + + pSys->setProperty(pSys, PDB_PROP_SYS_SYSTEM_EVENTS_SUPPORTED, NV_TRUE); + + RmInitPowerManagement(nv); + + if (!NV_IS_SOC_DISPLAY_DEVICE(nv)) + { + status.rmStatus = RmRegisterGpudb(pGpu); + if (status.rmStatus != NV_OK) + { + RM_SET_ERROR(status, RM_GPUDB_REGISTER_FAILED); + goto shutdown; + } + } + + if (nvp->b_mobile_config_enabled) + { + NvU32 ac_plugged = 0; + if (nv_acpi_get_powersource(&ac_plugged) == NV_OK) + { + // LOCK: acquire GPU lock + if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_NONE) == NV_OK) + { + // + // As we have already acquired the API Lock here, we are calling + // RmPowerSourceChangeEvent directly instead of rm_power_source_change_event. + // + RmPowerSourceChangeEvent(nv, !ac_plugged); + + // UNLOCK: release GPU lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + } + } + + _checkP2pChipsetSupport(nv); + + NV_DEV_PRINTF(NV_DBG_SETUP, nv, "RmInitAdapter succeeded!\n"); + + retVal = NV_TRUE; + goto done; + + shutdown: + nv->flags &= ~NV_FLAG_IN_RECOVERY; + + gpumgrThreadDisableExpandedGpuVisibility(); + + // call ShutdownAdapter to undo anything we've done above + RmShutdownAdapter(nv); + + failed: + NV_DEV_PRINTF(NV_DBG_ERRORS, nv, "RmInitAdapter failed! (0x%x:0x%x:%d)\n", + status.initStatus, status.rmStatus, status.line); + +done: + nv_put_firmware(gspFwHandle); + nv_put_firmware(gspFwLogHandle); + nv_put_firmware(gspUcodesHandle); + + gpumgrSetCurrentGpuInstance(NV_U32_MAX); + + return retVal; +} + +void RmShutdownAdapter( + nv_state_t *nv +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + NV_STATUS rmStatus; + + if ((pGpu != NULL) && (nvp->flags & NV_INIT_FLAG_GPUMGR_ATTACH)) + { + NvU32 gpuInstance = gpuGetInstance(pGpu); + NvU32 deviceInstance = gpuGetDeviceInstance(pGpu); + OBJSYS *pSys = SYS_GET_INSTANCE(); + + RmUnixFreeRmApi(nv); + + nv->ud.cpu_address = 0; + nv->ud.size = 0; + + // + // LOCK: lock all clients in case of eGPU hot unplug, which + // will not wait for all existing RM clients to stop using the GPU. + // + if (!nv->is_external_gpu || serverLockAllClients(&g_resServ) == NV_OK) + { + // LOCK: acquire GPUs lock + if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DESTROY) == NV_OK) + { + // + // Shutdown path requires expanded GPU visibility in GPUMGR in order + // to access the GPU undergoing shutdown which may not be fully + // initialized, and to continue accessing the GPU undergoing shutdown + // after state destroy. + // + NV_ASSERT_OK(gpumgrThreadEnableExpandedGpuVisibility()); + + RmDestroyPowerManagement(nv); + + freeNbsiTable(pGpu); + + OBJCL *pCl = SYS_GET_CL(pSys); + OBJOS *pOS = GPU_GET_OS(pGpu); + if (pCl != NULL) + { + if (nvp->flags & NV_INIT_FLAG_CORE_LOGIC) + { + teardownCoreLogic(pOS, pGpu); + } + else if (nvp->flags & NV_INIT_FLAG_SCALABILITY) + { + osTeardownScalability(pGpu); + } + } + + if (nvp->flags & NV_INIT_FLAG_FIFO_WATCHDOG) + { + krcWatchdogShutdown(pGpu, GPU_GET_KERNEL_RC(pGpu), NULL); + nvp->flags &= ~NV_INIT_FLAG_FIFO_WATCHDOG; + } + + rmapiSetDelPendingClientResourcesFromGpuMask(NVBIT(gpuInstance)); + rmapiDelPendingDevices(NVBIT(gpuInstance)); + + if (nvp->flags & NV_INIT_FLAG_GPU_STATE_LOAD) + { + rmStatus = gpuStateUnload(pGpu, GPU_STATE_DEFAULT); + NV_ASSERT(rmStatus == NV_OK); + } + + if (nvp->flags & NV_INIT_FLAG_GPU_STATE) + { + rmStatus = gpuStateDestroy(pGpu); + NV_ASSERT(rmStatus == NV_OK); + } + + if (IS_DCE_CLIENT(pGpu)) + { + rmStatus = dceclientDceRmInit(pGpu, GPU_GET_DCECLIENTRM(pGpu), NV_FALSE); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "DCE firmware RM Shutdown failure\n"); + } + } + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_CLKS_IN_TEGRA_SOC)) + { + NV_PRINTF(LEVEL_INFO, "Disable Clocks\n"); + RmDisableDeviceClks(nv); + } + + //if (nvp->flags & NV_INIT_FLAG_HAL) + // destroyHal(pDev); + +#if NVCPU_IS_X86_64 + RmFreeX86EmuState(pGpu); +#endif + + gpumgrDetachGpu(gpuInstance); + gpumgrDestroyDevice(deviceInstance); + + // + // Expanded GPU visibility in GPUMGR is no longer needed once the + // GPU is removed from GPUMGR. + // + gpumgrThreadDisableExpandedGpuVisibility(); + + if (nvp->flags & NV_INIT_FLAG_DMA) + { + RmTeardownDeviceDma(nv); + } + + RmClearPrivateState(nv); + + RmUnInitAcpiMethods(pSys); + + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + + // RM_BASIC_LOCK_MODEL: free GPU lock + rmGpuLockFree(deviceInstance); + } + + // UNLOCK: unlock all clients for eGPU hot unplug path + if (nv->is_external_gpu) + serverUnlockAllClients(&g_resServ); + } + } + else + { + RmClearPrivateState(nv); + } + + RmTeardownRegisters(nv); +} + +void RmPartiallyDisableAdapter( + nv_state_t *nv +) +{ + NV_PRINTF(LEVEL_INFO, "%s: RM is in SW Persistence mode\n", __FUNCTION__); + + nv_stop_rc_timer(nv); +} + +void RmDisableAdapter( + nv_state_t *nv +) +{ + NV_STATUS rmStatus; + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + NvU32 gpuMask; + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + if (pGpu == NULL) + { + return; + } + + gpumgrSetCurrentGpuInstance(pGpu->gpuInstance); + + // + // Normally, we re-enable interrupts when we release the lock + // after RmDisableAdapter(), before disabling the bottom-half ISR. + // If an interrupt came in in that time window, but the bottom half + // wasn't scheduled to run in time, the semaphore acquired by the + // top-half would never be released afterwards (since the bottom-half + // would never run). This call to intrSetIntrEn() ensures that this won't + // happen, by making sure interrupts remain disabled on the GPU in question after + // RmDisableAdapter(). + // + Intr *pIntr = GPU_GET_INTR(pGpu); + if (pIntr != NULL) + { + intrSetIntrEn(pIntr, INTERRUPT_TYPE_DISABLED); + } + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_SECONDARY_BUS_RESET) || + pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_FULLCHIP_RESET)) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_TIMEOUT_RECOVERY, NV_TRUE); + nv->flags |= NV_FLAG_IN_RECOVERY; + } + + // + // LOCK: lock all clients in case of eGPU hot unplug, which + // will not wait for all existing RM clients to stop using the GPU. + // + if (!nv->is_external_gpu || serverLockAllClients(&g_resServ) == NV_OK) + { + + // LOCK: acquire GPUs lock + if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DESTROY) == NV_OK) + { + // + // Free the client allocated resources. + // + // Note this doesn't free RM internal resource allocations. Those are + // freed during gpuStateUnload. + // + gpuMask = gpumgrGetGpuMask(pGpu); + + rmapiSetDelPendingClientResourcesFromGpuMask(gpuMask); + rmapiDelPendingDevices(gpuMask); + + nv_stop_rc_timer(nv); + + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + OBJOS *pOS = SYS_GET_OS(pSys); + if (pCl != NULL) + { + teardownCoreLogic(pOS, pGpu); + nvp->flags &= ~NV_INIT_FLAG_CORE_LOGIC; + } + + if (nvp->flags & NV_INIT_FLAG_FIFO_WATCHDOG) + { + krcWatchdogShutdown(pGpu, GPU_GET_KERNEL_RC(pGpu), NULL); + nvp->flags &= ~NV_INIT_FLAG_FIFO_WATCHDOG; + } + + if (nvp->flags & NV_INIT_FLAG_GPU_STATE_LOAD) + { + rmStatus = gpuStateUnload(pGpu, GPU_STATE_DEFAULT); + NV_ASSERT(rmStatus == NV_OK); + nvp->flags &= ~NV_INIT_FLAG_GPU_STATE_LOAD; + } + + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + + // UNLOCK: unlock all clients for eGPU hot unplug path + if (nv->is_external_gpu) + serverUnlockAllClients(&g_resServ); + } + + gpumgrSetCurrentGpuInstance(NV_U32_MAX); +} + +NV_STATUS RmGetAdapterStatus( + nv_state_t *pNv, + NvU32 *pStatus +) +{ + // + // This status is determined in RmInitAdapter(); the glue layer + // requests it when the adapter failed to initialize to learn + // more about the error condition. This is currently limited to + // osVerifySystemEnvironment() failures. + // + nv_priv_t *nvp; + + nvp = NV_GET_NV_PRIV(pNv); + if (nvp == NULL) + { + return NV_ERR_INVALID_STATE; + } + + *pStatus = nvp->status; + return NV_OK; +} + +static void initVendorSpecificRegistry( + OBJGPU *pGpu, + NvU16 device_id +) +{ + NV_STATUS rmStatus; + NvU32 i; + NvU32 subsystem_id; + NvU32 subsystem_vendor_id; + NvU32 subsystem_device_id; + NvU32 vendor_id = 0; + + if (!pGpu) + return; + + if (pGpu->bIsSOC) + return; + + rmStatus = GPU_BUS_CFG_RD32(pGpu, + NV_CONFIG_PCI_NV_11, &subsystem_id); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s: Cannot read NV_CONFIG_PCI_NV_11\n", __FUNCTION__); + return; + } + + subsystem_vendor_id = (subsystem_id & 0xffff); + subsystem_device_id = (subsystem_id >> 16); + + for (i = 0; (nb_id_table[i].subsystem_vendor_id) != 0; i++) + { + if ((nb_id_table[i].subsystem_vendor_id == subsystem_vendor_id) && + (nb_id_table[i].subsystem_device_id == subsystem_device_id) && + (nb_id_table[i].gpu_device_id == device_id)) + { + vendor_id = subsystem_vendor_id; + break; + } + } + + if (vendor_id != 0) + { + for (i = 0; nb_reg_table[i].vendor_id != 0; i++) + { + if (nb_reg_table[i].vendor_id == vendor_id) + { + osWriteRegistryDword(pGpu, nb_reg_table[i].name, + nb_reg_table[i].data); + } + } + } +} + +static void initUnixSpecificRegistry( + OBJGPU *pGpu +) +{ + // By default, enable GPU reset on Unix + osWriteRegistryDword(pGpu, "RMSecBusResetEnable", 1); + osWriteRegistryDword(pGpu, "RMForcePcieConfigSave", 1); + +} + +void +osRemoveGpu( + NvU32 domain, + NvU8 bus, + NvU8 device +) +{ + void *handle; + + handle = os_pci_init_handle(domain, bus, device, 0, NULL, NULL); + if (handle != NULL) + { + os_pci_remove(handle); + } +} + +/* + * Check to see if this board supports GPU exclusion. + */ +static NvBool RmIsExcludingAllowed( + nv_state_t *pNv +) +{ + NvU32 feature = 0; + NvU32 brand; + + // DGX-2/HGX-2 systems pre-date the PBI call + if (pNv->pci_info.device_id == 0x1db8) + return NV_TRUE; + + if (pciPbiGetFeature(pNv->handle, &feature) != NV_OK) + return NV_FALSE; + + brand = DRF_VAL(_PBI, _EXECUTE_ROUTINE, _GET_FEATURE_EXCLUSION, feature); + + return (brand == NV_PBI_EXECUTE_ROUTINE_GET_FEATURE_EXCLUSION_ALLOWED); +} + +NV_STATUS RmExcludeAdapter( + nv_state_t *nv +) +{ + NV_STATUS rmStatus; + + if (!RmIsExcludingAllowed(nv)) + return NV_ERR_NOT_SUPPORTED; + + rmStatus = gpumgrExcludeGpuId(nv->gpu_id); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to exclude GPU: 0x%x\n", rmStatus); + return rmStatus; + } + + /* + * GPU exclusion only happens during initialization, and therefore there + * is no need to stop activity on the GPU + */ + + return rmStatus; +} diff --git a/userspace/sdks/nv570/nvalloc/unix/src/osmemdesc.c b/userspace/sdks/nv570/nvalloc/unix/src/osmemdesc.c new file mode 100644 index 0000000..84730cb --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/src/osmemdesc.c @@ -0,0 +1,1325 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/******************* OS Memory Descriptor APIS *****************************\ +* * +* This contains routines to create and destroy OS memory descriptor * +* * +****************************************************************************/ + +#include // NV device driver interface +#include +#include +#include +#include +#include +#include + +#include "gpu/bif/kernel_bif.h" + +static NV_STATUS osCreateOsDescriptorFromPageArray(OBJGPU *, NvP64, NvHandle, NvU32, NvU64 *, MEMORY_DESCRIPTOR **, void **); +static void osDestroyOsDescriptorPageArray(PMEMORY_DESCRIPTOR); + +static NV_STATUS osCreateOsDescriptorFromIoMemory(OBJGPU *, NvP64, NvHandle, NvU32, NvU64 *, MEMORY_DESCRIPTOR **, void**); +static void osDestroyOsDescriptorFromIoMemory(PMEMORY_DESCRIPTOR); + +static NV_STATUS osCreateOsDescriptorFromPhysAddr(OBJGPU *, NvP64, NvHandle, NvU32, NvU64 *, MEMORY_DESCRIPTOR **, void**); +static void osDestroyOsDescriptorFromPhysAddr(PMEMORY_DESCRIPTOR); + +static NV_STATUS osCreateOsDescriptorFromFileHandle(OBJGPU *, NvP64, NvHandle, NvU32, NvU64 *, MEMORY_DESCRIPTOR **, void**); +static NV_STATUS osCreateOsDescriptorFromDmaBufPtr(OBJGPU *, NvP64, NvHandle, NvU32, NvU64 *, MEMORY_DESCRIPTOR **, void**); +static void osDestroyOsDescriptorFromDmaBuf(PMEMORY_DESCRIPTOR); +static NV_STATUS osCreateOsDescriptorFromSgtPtr(OBJGPU *, NvP64, NvHandle, NvU32, NvU64 *, MEMORY_DESCRIPTOR **, void**); +static void osDestroyOsDescriptorFromSgt(PMEMORY_DESCRIPTOR); + +static NV_STATUS osCheckGpuBarsOverlapAddrRange(NvRangeU64 addrRange); + +NV_STATUS +osCreateMemFromOsDescriptor +( + OBJGPU *pGpu, + NvP64 pDescriptor, + NvHandle hClient, + NvU32 flags, + NvU64 *pLimit, + MEMORY_DESCRIPTOR **ppMemDesc, + NvU32 descriptorType, + RS_PRIV_LEVEL privilegeLevel +) +{ + RmClient* pClient; + NV_STATUS rmStatus; + void *pPrivate; + + pClient = serverutilGetClientUnderLock(hClient); + if ((pDescriptor == NvP64_NULL) || + (*pLimit == 0) || + (pClient == NULL)) + { + return NV_ERR_INVALID_PARAM_STRUCT; + } + + // + // For the sake of simplicity, unmatched RM and OS page + // sizes are not currently supported in this path, except for + // aarch64. + // + // Also, the nvmap handle is sent which can be any random number so + // the virtual address alignment sanity check can't be done here. + // + if (!NVCPU_IS_AARCH64 && + (NV_RM_PAGE_SIZE != os_page_size)) + { + return NV_ERR_NOT_SUPPORTED; + } + + // + // The two checks below use cached privilege because they + // concern the privilege level of the client, and not the + // privilege level of the calling context which may be + // overridden to KERNEL at some internal callsites. + // + + // + // The RM cannot obtain a table of physical addresses + // for a kernel virtual address range on all of + // the supported UNIX platforms. Since this path is + // not really compelling for kernel allocations on any + // of those platforms, it is not supported. + // For UVM, they could have pre-allocated sysmem to register + // with RM so we put in an exception for that case. + // + if ((rmclientGetCachedPrivilege(pClient) >= RS_PRIV_LEVEL_KERNEL) && + (descriptorType != NVOS32_DESCRIPTOR_TYPE_OS_PHYS_ADDR) && + (descriptorType != NVOS32_DESCRIPTOR_TYPE_OS_FILE_HANDLE) && + (descriptorType != NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR) && + (descriptorType != NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR)) + { + return NV_ERR_NOT_SUPPORTED; + } + + // + // NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR and + // NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR can only be utilized by kernel space + // rm-clients. + // + if ((rmclientGetCachedPrivilege(pClient) < RS_PRIV_LEVEL_KERNEL) && + ((descriptorType == NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR) || + (descriptorType == NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR))) + { + return NV_ERR_NOT_SUPPORTED; + } + + switch (descriptorType) + { + case NVOS32_DESCRIPTOR_TYPE_VIRTUAL_ADDRESS: + rmStatus = NV_ERR_NOT_SUPPORTED; + break; + case NVOS32_DESCRIPTOR_TYPE_OS_PHYS_ADDR: + if (privilegeLevel < RS_PRIV_LEVEL_KERNEL) + { + rmStatus = NV_ERR_NOT_SUPPORTED; + break; + } + rmStatus = osCreateOsDescriptorFromPhysAddr(pGpu, pDescriptor, + hClient, flags, pLimit, ppMemDesc, &pPrivate); + break; + case NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY: + rmStatus = osCreateOsDescriptorFromIoMemory(pGpu, pDescriptor, + hClient, flags, pLimit, ppMemDesc, &pPrivate); + break; + case NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY: + rmStatus = osCreateOsDescriptorFromPageArray(pGpu, pDescriptor, + hClient, flags, pLimit, ppMemDesc, &pPrivate); + break; + case NVOS32_DESCRIPTOR_TYPE_OS_FILE_HANDLE: + rmStatus = osCreateOsDescriptorFromFileHandle(pGpu, pDescriptor, + hClient, flags, pLimit, ppMemDesc, &pPrivate); + break; + case NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR: + rmStatus = osCreateOsDescriptorFromDmaBufPtr(pGpu, pDescriptor, + hClient, flags, pLimit, ppMemDesc, &pPrivate); + break; + case NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR: + rmStatus = osCreateOsDescriptorFromSgtPtr(pGpu, pDescriptor, + hClient, flags, pLimit, ppMemDesc, &pPrivate); + break; + default: + rmStatus = NV_ERR_INVALID_ARGUMENT; + break; + } + + return rmStatus; +} + +static NV_STATUS +osCreateMemdescFromPages +( + OBJGPU *pGpu, + NvU64 size, + NvU32 flags, + NvU32 cacheType, + MEMORY_DESCRIPTOR **ppMemDesc, + void *pImportPriv, + void **ppPrivate +) +{ + NV_STATUS rmStatus = NV_OK; + MEMORY_DESCRIPTOR *pMemDesc; + NvU64 memdescFlags = MEMDESC_FLAGS_NONE; + NvU32 gpuCachedFlags; + NvBool bUnprotected = NV_FALSE; + NvU64 osPageCount; + + // + // Align size up to os page size. This is important in + // order to support submemdesc mappings at native page size. + // Once dynamic tracking is enabled this will not be needed + // as all submemory will get tracked at its native page size. + // + size = NV_ALIGN_UP64(size, os_page_size); + + osPageCount = size >> os_page_shift; + + if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_NISO_DISPLAY, _YES, flags)) + { + memdescFlags |= MEMDESC_FLAGS_MEMORY_TYPE_DISPLAY_NISO; + } + + if (FLD_TEST_DRF(OS02, _FLAGS, _MEMORY_PROTECTION, _UNPROTECTED, flags)) + { + memdescFlags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; + bUnprotected = NV_TRUE; + } + + if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_USER_READ_ONLY, _YES, flags)) + { + memdescFlags |= MEMDESC_FLAGS_USER_READ_ONLY; + memdescFlags |= MEMDESC_FLAGS_DEVICE_READ_ONLY; + } + + if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_DEVICE_READ_ONLY, _YES, flags)) + { + memdescFlags |= MEMDESC_FLAGS_DEVICE_READ_ONLY; + } + + rmStatus = memdescCreate(ppMemDesc, pGpu, size, 0, + NV_MEMORY_NONCONTIGUOUS, ADDR_SYSMEM, + cacheType, memdescFlags); + if (rmStatus != NV_OK) + { + return rmStatus; + } + + if (FLD_TEST_DRF(OS02, _FLAGS, _GPU_CACHEABLE, _YES, flags)) + gpuCachedFlags = NV_MEMORY_CACHED; + else + gpuCachedFlags = NV_MEMORY_UNCACHED; + + pMemDesc = *ppMemDesc; + rmStatus = nv_register_user_pages(NV_GET_NV_STATE(pGpu), + osPageCount, + memdescGetPteArray(pMemDesc, AT_CPU), pImportPriv, + ppPrivate, bUnprotected); + if (rmStatus != NV_OK) + { + memdescDestroy(pMemDesc); + return rmStatus; + } + + memdescSetGpuCacheAttrib(pMemDesc, gpuCachedFlags); + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_KERNEL_MODE, NV_FALSE); + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_EXT_PAGE_ARRAY_MEM, NV_TRUE); + + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc)) + { + NV_ASSERT_OR_GOTO((os_page_size & (pMemDesc->pageArrayGranularity - 1ULL)) == 0, cleanup); + NV_ASSERT_OK_OR_GOTO(rmStatus, memdescSetAllocSizeFields(pMemDesc, size, os_page_size), cleanup); + } + else + { + NV_ASSERT_OK_OR_GOTO(rmStatus, memdescSetAllocSizeFields(pMemDesc, size, NV_RM_PAGE_SIZE), cleanup); + } + + if (!NV_IS_ALIGNED64(memdescGetPhysAddr(pMemDesc, AT_CPU, 0), os_page_size)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + NV_ASSERT_OR_GOTO(0, cleanup); + } + + + // + // If the OS layer doesn't think in RM page size, we need to inflate the + // PTE array into RM pages. + // + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc)) + { + // Because os_page_size == pMemDesc->pageArrayGranularity, we don't need to do any page array conversion. + NV_ASSERT_OR_ELSE(os_page_size == pMemDesc->pageArrayGranularity, rmStatus = NV_ERR_INVALID_ARGUMENT; goto cleanup); + } + else if ((NV_RM_PAGE_SIZE < os_page_size) && + !memdescGetContiguity(pMemDesc, AT_CPU)) + { + RmInflateOsToRmPageArray(memdescGetPteArray(pMemDesc, AT_CPU), pMemDesc->PageCount); + } + + // + // memdescMapIommu() requires the OS-private data to be set on the memory + // descriptor, but we don't want to wire up the teardown callback just yet: + // that callback needs to unpin the pages, but that will already be done + // as part of failure handling further up the stack if memdescMapIommu() + // fails. So we only set up the priv-data cleanup callback once we're sure + // this call will succeed. + // + memdescSetMemData(pMemDesc, *ppPrivate, NULL); + + rmStatus = memdescMapIommu(pMemDesc, pGpu->busInfo.iovaspaceId); +cleanup: + if (rmStatus != NV_OK) + { + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc)) + { + // Because os_page_size == pMemDesc->pageArrayGranularity, we don't need to do any page array conversion. + NV_ASSERT(os_page_size == pMemDesc->pageArrayGranularity); + } + else if ((NV_RM_PAGE_SIZE < os_page_size) && + !memdescGetContiguity(pMemDesc, AT_CPU)) + { + RmDeflateRmToOsPageArray(memdescGetPteArray(pMemDesc, AT_CPU), + pMemDesc->PageCount); + } + + nv_unregister_user_pages(NV_GET_NV_STATE(pGpu), + osPageCount, + NULL /* import_priv */, ppPrivate); + memdescDestroy(pMemDesc); + return rmStatus; + } + + return NV_OK; +} + +static NV_STATUS +osCreateOsDescriptorFromPageArray +( + OBJGPU *pGpu, + NvP64 pDescriptor, + NvHandle hClient, + NvU32 flags, + NvU64 *pLimit, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppPrivate +) +{ + NV_STATUS rmStatus; + + *ppPrivate = NvP64_VALUE(pDescriptor); + + // + // Since the only type of memory permitted in this path + // is anonymous user memory, certain restrictions + // apply for the allocation flags: + // + // 1) anonymous memory is write-back cacheable, hence + // the _COHERENCY flag must match. + // + // 2) the RM has no control over the location of the + // associated pages in memory and thus cannot + // honor requests for contiguous memory. + // + // These restrictions are enforced here to avoid subtle + // bugs later on. + // + if ((!FLD_TEST_DRF(OS02, _FLAGS, _COHERENCY, _CACHED, flags) && + !FLD_TEST_DRF(OS02, _FLAGS, _COHERENCY, _WRITE_BACK, flags)) || + FLD_TEST_DRF(OS02, _FLAGS, _PHYSICALITY, _CONTIGUOUS, flags)) + { + return NV_ERR_INVALID_FLAGS; + } + + rmStatus = osCreateMemdescFromPages(pGpu, (*pLimit + 1), flags, + NV_MEMORY_CACHED, ppMemDesc, + NULL /* pImportPriv */, ppPrivate); + if (rmStatus != NV_OK) + { + return rmStatus; + } + + // All is well - wire up the cleanup callback now + memdescSetMemData(*ppMemDesc, memdescGetMemData(*ppMemDesc), + osDestroyOsDescriptorPageArray); + + return NV_OK; +} + +/*! + * @brief Checks if the given address range overlaps with the BARs for any of + * the GPUs. + */ +static NV_STATUS +osCheckGpuBarsOverlapAddrRange +( + NvRangeU64 addrRange +) +{ + NvRangeU64 gpuPhysAddrRange; + NvRangeU64 gpuPhysFbAddrRange; + NvRangeU64 gpuPhysInstAddrRange; + NvU32 gpuInstance; + OBJGPU *pGpu; + NvU32 gpuMask; + NV_STATUS rmStatus; + + rmStatus = gpumgrGetGpuAttachInfo(NULL, &gpuMask); + NV_ASSERT_OR_RETURN(rmStatus == NV_OK, rmStatus); + + gpuInstance = 0; + while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + NV_INIT_RANGE(gpuPhysAddrRange, pGpu->busInfo.gpuPhysAddr, + pGpu->busInfo.gpuPhysAddr + pGpu->deviceMappings[0].gpuNvLength -1); + + if (NV_IS_OVERLAPPING_RANGE(gpuPhysAddrRange, addrRange)) + { + NV_PRINTF(LEVEL_ERROR, + "%s(): phys range 0x%016llx-0x%016llx overlaps with GPU BAR0\n", + __FUNCTION__, addrRange.min, addrRange.max); + return NV_ERR_INVALID_ADDRESS; + } + + if ((pGpu->pGpuArch->bGpuArchIsZeroFb) || + (pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY))) + { + // No local FB or BAR2 for ZERO_FB and TEGRA_SOC_NVDISPLAY. + continue; + } + + NV_INIT_RANGE(gpuPhysFbAddrRange, gpumgrGetGpuPhysFbAddr(pGpu), + gpumgrGetGpuPhysFbAddr(pGpu) + pGpu->fbLength -1); + + NV_INIT_RANGE(gpuPhysInstAddrRange, pGpu->busInfo.gpuPhysInstAddr, + pGpu->busInfo.gpuPhysInstAddr + pGpu->instLength -1); + + if (NV_IS_OVERLAPPING_RANGE(gpuPhysFbAddrRange, addrRange) || + NV_IS_OVERLAPPING_RANGE(gpuPhysInstAddrRange, addrRange)) + { + NV_PRINTF(LEVEL_ERROR, + "%s(): phys range 0x%016llx-0x%016llx overlaps with FB or GPU BAR2\n", + __FUNCTION__, addrRange.min, addrRange.max); + return NV_ERR_INVALID_ADDRESS; + } + } + + return NV_OK; +} + +static NvU64 +_doWarBug4040336 +( + OBJGPU *pGpu, + NvU64 addr +) +{ + if (gpuIsWarBug4040336Enabled(pGpu)) + { + if ((addr & 0xffffffff00000000ULL) == 0x7fff00000000ULL) + { + addr = addr & 0xffffffffULL; + } + } + return addr; +} + +static NV_STATUS +osCreateOsDescriptorFromIoMemory +( + OBJGPU *pGpu, + NvP64 pDescriptor, + NvHandle hClient, + NvU32 flags, + NvU64 *pLimit, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppPrivate +) +{ + NV_STATUS rmStatus; + NvU32 gpuCachedFlags; + MEMORY_DESCRIPTOR *pMemDesc; + NvU64 *pPteArray; + NvRangeU64 physAddrRange; + NvU64 *base = 0; + NvBool bAllowMmap; + NvU64 size; + + // + // Unlike the page array path, this one deals exclusively + // with I/O memory, which is expected to be contiguous + // physically, and which may only be accessed with uncached + // transactions. + // + if (!FLD_TEST_DRF(OS02, _FLAGS, _COHERENCY, _UNCACHED, flags) || + !FLD_TEST_DRF(OS02, _FLAGS, _PHYSICALITY, _CONTIGUOUS, flags)) + { + return NV_ERR_INVALID_FLAGS; + } + + // + // _PEER_MAP_OVERRIDE flag is controlled by the RM and not the client. + // + // RM will set the _PEER_MAP_OVERRIDE_REQUIRED flag itself for IO memory + // memory imported with RmVidHeapControl. + // + if (FLD_TEST_DRF(OS02, _FLAGS, _PEER_MAP_OVERRIDE, _REQUIRED, flags)) + { + // + // Don't allow MMIO mappings for unprivileged users + // This is a temporary WAR for bug 1630288 "[PeerSync] threat related + // to GPU" + // + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + if (!pKernelBif->peerMappingOverride && !osIsAdministrator()) + { + NV_PRINTF(LEVEL_ERROR, + "%s(): permission denied, allowPeermapping=%d\n", + __FUNCTION__, pKernelBif->peerMappingOverride); + return NV_ERR_INSUFFICIENT_PERMISSIONS; + } + } + + bAllowMmap = !FLD_TEST_DRF(OS02, _FLAGS, _MAPPING, _NEVER_MAP, flags); + + base = (void *)(NvUPtr)pDescriptor; + + // + // There is an architectural deadlock scenario involved when full-duplex P2P + // enabled over BAR1. See #3 in the description of bug 1571948 which explains + // the classic deadlock. So, make sure to error out usermode's memory + // registration if a memory range falls within any of the available GPU's + // BAR window. + // + physAddrRange.min = *base; + physAddrRange.max = *base + *pLimit; + + rmStatus = osCheckGpuBarsOverlapAddrRange(physAddrRange); + if (rmStatus != NV_OK) + { + return rmStatus; + } + + // + // BF3's PCIe MMIO bus address at 0x800000000000(CPU PA 0x7fff00000000) is + // too high for Ampere to address. As a result, BF3's bus address is + // moved to < 4GB. Now, the CPU PA and the bus address are no longer 1:1 + // and needs to be adjusted. + // + *base = _doWarBug4040336(pGpu, *base); + + size = NV_ALIGN_UP64(*pLimit + 1, os_page_size); + + rmStatus = memdescCreate(ppMemDesc, pGpu, size, 0, + NV_MEMORY_CONTIGUOUS, ADDR_SYSMEM, + NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s(): error %d while attempting to create the MMIO mapping\n", + __FUNCTION__, rmStatus); + return rmStatus; + } + + pMemDesc = *ppMemDesc; + + if (FLD_TEST_DRF(OS02, _FLAGS, _GPU_CACHEABLE, _YES, flags)) + gpuCachedFlags = NV_MEMORY_CACHED; + else + gpuCachedFlags = NV_MEMORY_UNCACHED; + + memdescSetGpuCacheAttrib(pMemDesc, gpuCachedFlags); + memdescSetMemData(pMemDesc, NULL, NULL); + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_KERNEL_MODE, NV_FALSE); + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_PEER_IO_MEM, NV_TRUE); + + pPteArray = memdescGetPteArray(pMemDesc, AT_CPU); + pPteArray[0] = *base; + + *ppPrivate = NULL; + + if (!NV_IS_ALIGNED64(pPteArray[0], os_page_size)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + NV_ASSERT_OR_GOTO(0, cleanup); + } + NvU64 osPageCount; + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc)) + { + NV_ASSERT_OK_OR_GOTO(rmStatus, memdescSetAllocSizeFields(pMemDesc, size, os_page_size), cleanup); + osPageCount = pMemDesc->PageCount; + } + else + { + NV_ASSERT_OK_OR_GOTO(rmStatus, memdescSetAllocSizeFields(pMemDesc, size, NV_RM_PAGE_SIZE), cleanup); + osPageCount = NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount); + } + + if (bAllowMmap) + { + rmStatus = nv_register_peer_io_mem(NV_GET_NV_STATE(pGpu), pPteArray, + osPageCount, + ppPrivate); + if (rmStatus != NV_OK) + { + memdescDestroy(pMemDesc); + return rmStatus; + } + } + + memdescSetMemData(pMemDesc, *ppPrivate, NULL); + + // + // memdescMapIommu() requires the OS-private data to be set on the memory + // descriptor, but we don't want to wire up the teardown callback just yet: + // that callback needs to unpin the pages, but that will already be done + // as part of failure handling further up the stack if memdescMapIommu() + // fails. So we only set up the priv-data cleanup callback once we're sure + // this call will succeed. + // + rmStatus = memdescMapIommu(pMemDesc, pGpu->busInfo.iovaspaceId); +cleanup: + if (rmStatus != NV_OK) + { + if (*ppPrivate != NULL) + { + nv_unregister_peer_io_mem(NV_GET_NV_STATE(pGpu), *ppPrivate); + } + memdescDestroy(pMemDesc); + return rmStatus; + } + + // All is well - wire up the cleanup callback now + memdescSetMemData(pMemDesc, memdescGetMemData(pMemDesc), + osDestroyOsDescriptorFromIoMemory); + + return NV_OK; +} + +static NV_STATUS +osCreateOsDescriptorFromPhysAddr +( + OBJGPU *pGpu, + NvP64 pDescriptor, + NvHandle hClient, + NvU32 flags, + NvU64 *pLimit, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppPrivate +) +{ + NV_STATUS rmStatus; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + MEMORY_DESCRIPTOR *pMemDesc; + NvU64 *pPteArray; + NvU64 base = 0; + NvU32 cache_type = NV_MEMORY_CACHED; + NvU64 memdescFlags = MEMDESC_FLAGS_NONE; + NvU64 *pPhys_addrs; + NvU64 num_os_pages; + NvU32 idx; + NvU64 size; + + // Currently only work with contiguous sysmem allocations + if (!FLD_TEST_DRF(OS02, _FLAGS, _PHYSICALITY, _CONTIGUOUS, flags)) + { + return NV_ERR_INVALID_FLAGS; + } + + if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_TYPE_SYNCPOINT, _APERTURE, flags)) + { + // Syncpoint memory is uncached, DMA mapping needs to skip CPU sync. + cache_type = NV_MEMORY_UNCACHED; + + // + // Syncpoint memory is NISO. Don't attempt to IOMMU map if the NISO + // IOMMU isn't enabled. + // + if (!NV_SOC_IS_NISO_IOMMU_PRESENT(nv)) + { + memdescFlags |= MEMDESC_FLAGS_SKIP_IOMMU_MAPPING; + } + } + + if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_NISO_DISPLAY, _YES, flags)) + { + memdescFlags |= MEMDESC_FLAGS_MEMORY_TYPE_DISPLAY_NISO; + } + + base = (NvU64)pDescriptor; + size = NV_ALIGN_UP64((*pLimit + 1), os_page_size); + + NV_ASSERT_OR_RETURN(NV_IS_ALIGNED64(base, os_page_size), NV_ERR_INVALID_ARGUMENT); + + rmStatus = memdescCreate(ppMemDesc, pGpu, size, 0, + NV_MEMORY_CONTIGUOUS, ADDR_SYSMEM, + cache_type, memdescFlags); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s(): error %d while creating memdesc for kernel memory\n", + __FUNCTION__, rmStatus); + return rmStatus; + } + + pMemDesc = *ppMemDesc; + + memdescSetMemData(pMemDesc, NULL, NULL); + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_EXT_PAGE_ARRAY_MEM, NV_TRUE); + + pPteArray = memdescGetPteArray(pMemDesc, AT_CPU); + pPteArray[0] = base; + + num_os_pages = size >> os_page_shift; + pPhys_addrs = portMemAllocNonPaged(sizeof(NvU64) * num_os_pages); + if (pPhys_addrs == NULL) + goto cleanup_memdesc; + + for (idx = 0; idx < num_os_pages; idx++) + { + pPhys_addrs[idx] = base + (idx * os_page_size); + } + + *ppPrivate = NULL; + rmStatus = nv_register_phys_pages(nv, pPhys_addrs, num_os_pages, + memdescGetCpuCacheAttrib(pMemDesc), + ppPrivate); + if (rmStatus != NV_OK) + goto cleanup_memdesc; + + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc)) + { + NV_ASSERT_OK_OR_RETURN(memdescSetAllocSizeFields(pMemDesc, size, os_page_size)); + } + else + { + NV_ASSERT_OK_OR_RETURN(memdescSetAllocSizeFields(pMemDesc, size, NV_RM_PAGE_SIZE)); + } + + // If IOMMU skip flag wasn't set earlier, create IOVA mapping. + if (!memdescGetFlag(pMemDesc, MEMDESC_FLAGS_SKIP_IOMMU_MAPPING)) + { + // + // memdescMapIommu() requires the OS-private data to be set on the memory + // descriptor, but we don't want to wire up the teardown callback just yet: + // that callback needs to unpin the pages, but that will already be done + // as part of failure handling further up the stack if memdescMapIommu() + // fails. So we only set up the priv-data cleanup callback once we're sure + // this call will succeed. + // + memdescSetMemData(pMemDesc, *ppPrivate, NULL); + + rmStatus = memdescMapIommu(pMemDesc, pGpu->busInfo.iovaspaceId); + if (rmStatus != NV_OK) + goto cleanup_pages; + } + + // All is well - wire up the cleanup callback now + memdescSetMemData(pMemDesc, *ppPrivate, + osDestroyOsDescriptorFromPhysAddr); + + portMemFree(pPhys_addrs); + + return NV_OK; + +cleanup_pages: + if (*ppPrivate != NULL) + { + nv_unregister_phys_pages(NV_GET_NV_STATE(pGpu), *ppPrivate); + } + +cleanup_memdesc: + memdescDestroy(pMemDesc); + + portMemFree(pPhys_addrs); + + return rmStatus; +} + +static NV_STATUS +_createMemdescFromDmaBufSgtHelper +( + OBJGPU *pGpu, + NvU32 flags, + void *pImportPriv, + struct sg_table *pImportSgt, + NvU32 size, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppPrivate, + MEM_DATA_RELEASE_CALL_BACK *pMemDataReleaseCallback +) +{ + NV_STATUS rmStatus = NV_OK; + NvU32 cacheType = NV_MEMORY_UNCACHED; + MEMORY_DESCRIPTOR *pMemDesc; + NvU64 memdescFlags = MEMDESC_FLAGS_NONE; + NvU32 gpuCachedFlags; + NvBool isPeerMmio = NV_FALSE; + NvU64 osPageCount; + + // + // Align size up to os page size. This is important in + // order to support submemdesc mappings at native page size. + // Once dynamic tracking is enabled this will not be needed + // as all submemor + // + size = NV_ALIGN_UP64(size, os_page_size); + + osPageCount = size >> os_page_shift; + + NV_ASSERT((pMemDataReleaseCallback == osDestroyOsDescriptorFromDmaBuf) || + (pMemDataReleaseCallback == osDestroyOsDescriptorFromSgt)); + + if (FLD_TEST_DRF(OS02, _FLAGS, _COHERENCY, _WRITE_COMBINE, flags)) + { + cacheType = NV_MEMORY_WRITECOMBINED; + } + else if (!FLD_TEST_DRF(OS02, _FLAGS, _COHERENCY, _UNCACHED, flags)) + { + cacheType = NV_MEMORY_CACHED; + } + + if (FLD_TEST_DRF(OS02, _FLAGS, _GPU_CACHEABLE, _YES, flags)) + { + gpuCachedFlags = NV_MEMORY_CACHED; + } + else + { + gpuCachedFlags = NV_MEMORY_UNCACHED; + } + + if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_TYPE_SYNCPOINT, _APERTURE, flags)) + { + // Syncpoint memory is uncached. + if ((cacheType != NV_MEMORY_UNCACHED) || + (gpuCachedFlags != NV_MEMORY_UNCACHED)) + { + NV_PRINTF(LEVEL_ERROR, + "%s(): Error: Syncpoint memory region should be uncached!!!\n", + __FUNCTION__); + return NV_ERR_INVALID_FLAGS; + } + + isPeerMmio = NV_TRUE; + + NV_PRINTF(LEVEL_INFO, + "%s(): Syncpoint type sgt!\n", __FUNCTION__); + } + + if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_NISO_DISPLAY, _YES, flags)) + { + memdescFlags |= MEMDESC_FLAGS_MEMORY_TYPE_DISPLAY_NISO; + } + + if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_USER_READ_ONLY, _YES, flags)) + { + memdescFlags |= MEMDESC_FLAGS_USER_READ_ONLY; + } + + if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_DEVICE_READ_ONLY, _YES, flags)) + { + memdescFlags |= MEMDESC_FLAGS_DEVICE_READ_ONLY; + } + + rmStatus = memdescCreate(ppMemDesc, pGpu, size, 0, + NV_MEMORY_NONCONTIGUOUS, ADDR_SYSMEM, + cacheType, memdescFlags); + if (rmStatus != NV_OK) + { + return rmStatus; + } + + pMemDesc = *ppMemDesc; + + memdescSetGpuCacheAttrib(pMemDesc, gpuCachedFlags); + memdescSetMemData(pMemDesc, NULL, NULL); + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_KERNEL_MODE, NV_FALSE); + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_EXT_PAGE_ARRAY_MEM, NV_TRUE); + + *ppPrivate = NULL; + rmStatus = nv_register_sgt(NV_GET_NV_STATE(pGpu), + memdescGetPteArray(pMemDesc, AT_CPU), + osPageCount, + memdescGetCpuCacheAttrib(pMemDesc), + ppPrivate, + pImportSgt, + pImportPriv, + isPeerMmio); + if (rmStatus != NV_OK) + { + memdescDestroy(pMemDesc); + return rmStatus; + } + + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc)) + { + NV_ASSERT_OK_OR_GOTO(rmStatus, memdescSetAllocSizeFields(pMemDesc, size, os_page_size), cleanup); + } + else + { + NV_ASSERT_OK_OR_GOTO(rmStatus, memdescSetAllocSizeFields(pMemDesc, size, NV_RM_PAGE_SIZE), cleanup); + } + + if (!NV_IS_ALIGNED64(memdescGetPhysAddr(pMemDesc, AT_CPU, 0), os_page_size)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + NV_ASSERT_OR_GOTO(0, cleanup); + } + + // + // If the OS layer doesn't think in RM page size, we need to inflate the + // PTE array into RM pages. + // + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc)) + { + // Because os_page_size == pMemDesc->pageArrayGranularity, we don't need to do any page array conversion. + NV_ASSERT_OR_ELSE(os_page_size == pMemDesc->pageArrayGranularity, rmStatus = NV_ERR_INVALID_ARGUMENT; goto cleanup); + } + else if ((NV_RM_PAGE_SIZE < os_page_size) && + !memdescGetContiguity(pMemDesc, AT_CPU)) + { + RmInflateOsToRmPageArray(memdescGetPteArray(pMemDesc, AT_CPU), pMemDesc->PageCount); + } + + memdescSetMemData(*ppMemDesc, *ppPrivate, NULL); + + // + // memdescMapIommu() requires the OS-private data to be set on the memory + // descriptor, but we don't want to wire up the teardown callback just yet: + // that callback does teardown that will already be done as part of failure + // handling further up the stack if memdescMapIommu() fails. So we only + // setup the priv-data cleanup callback once we're sure this call will + // succeed. + // + rmStatus = memdescMapIommu(*ppMemDesc, pGpu->busInfo.iovaspaceId); +cleanup: + if (rmStatus != NV_OK) + { + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc)) + { + // Because os_page_size == pMemDesc->pageArrayGranularity, we don't need to do any page array conversion. + NV_ASSERT(os_page_size == pMemDesc->pageArrayGranularity); + } + else if ((NV_RM_PAGE_SIZE < os_page_size) && + !memdescGetContiguity(pMemDesc, AT_CPU)) + { + RmDeflateRmToOsPageArray(memdescGetPteArray(pMemDesc, AT_CPU), + pMemDesc->PageCount); + } + if (*ppPrivate != NULL) + { + nv_unregister_sgt(NV_GET_NV_STATE(pGpu), &pImportSgt, + (void **) &pImportPriv, *ppPrivate); + } + memdescDestroy(pMemDesc); + return rmStatus; + } + + // All is well - wire up the cleanup callback now + memdescSetMemData(*ppMemDesc, *ppPrivate, pMemDataReleaseCallback); + + return rmStatus; +} + +static NV_STATUS +_createMemdescFromDmaBuf +( + OBJGPU *pGpu, + NvU32 flags, + nv_dma_buf_t *pImportPriv, + struct sg_table *pImportSgt, + NvU32 size, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppPrivate +) +{ + NV_STATUS rmStatus = + _createMemdescFromDmaBufSgtHelper(pGpu, flags, pImportPriv, pImportSgt, + size, ppMemDesc, ppPrivate, + osDestroyOsDescriptorFromDmaBuf); + if (rmStatus != NV_OK) + { + nv_dma_release_dma_buf(pImportPriv); + } + + return rmStatus; +} + +static NV_STATUS +_createMemdescFromSgt +( + OBJGPU *pGpu, + NvU32 flags, + struct drm_gem_object *pImportPrivGem, + struct sg_table *pImportSgt, + NvU32 size, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppPrivate +) +{ + NV_STATUS rmStatus = + _createMemdescFromDmaBufSgtHelper(pGpu, flags, pImportPrivGem, + pImportSgt, size, ppMemDesc, + ppPrivate, + osDestroyOsDescriptorFromSgt); + if (rmStatus != NV_OK) + { + nv_dma_release_sgt(pImportSgt, pImportPrivGem); + } + + return rmStatus; +} + +static nv_dma_device_t *GetDmaDeviceForImport +( + nv_state_t *nv, + NvU32 flags +) +{ + if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_NISO_DISPLAY, _YES, flags) && + (nv->niso_dma_dev != NULL)) + { + return nv->niso_dma_dev; + } + else + { + return nv->dma_dev; + } +} + +static NV_STATUS +osCreateOsDescriptorFromFileHandle +( + OBJGPU *pGpu, + NvP64 pDescriptor, + NvHandle hClient, + NvU32 flags, + NvU64 *pLimit, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppPrivate +) +{ + NV_STATUS rmStatus = NV_OK; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_dma_device_t *dma_dev = NULL; + NvU32 size = 0; + nv_dma_buf_t *pImportPriv = NULL; + struct sg_table *pImportSgt = NULL; + NvBool bRoDeviceMap = NV_FALSE; + NvS32 fd; + + fd = (NvS32)((NvU64)pDescriptor); + if ((NvU64)fd != (NvU64)pDescriptor) + { + NV_PRINTF(LEVEL_ERROR, + "%s(): fd must fit within a signed 32-bit integer!\n", + __FUNCTION__); + return NV_ERR_INVALID_ARGUMENT; + } + + dma_dev = GetDmaDeviceForImport(nv, flags); + + if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_DEVICE_READ_ONLY, _YES, flags)) + { + bRoDeviceMap = NV_TRUE; + NV_PRINTF(LEVEL_INFO, + "%s(): RO DMA Mapping - flags [%x]!\n", + __FUNCTION__, flags); + } + + rmStatus = nv_dma_import_from_fd(dma_dev, fd, bRoDeviceMap, &size, + &pImportSgt, &pImportPriv); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s(): Error (%d) while trying to import fd!\n", + __FUNCTION__, rmStatus); + return rmStatus; + } + + return _createMemdescFromDmaBuf(pGpu, flags, pImportPriv, + pImportSgt, + size, ppMemDesc, ppPrivate); +} + +static NV_STATUS +osCreateOsDescriptorFromSgtPtr +( + OBJGPU *pGpu, + NvP64 pDescriptor, + NvHandle hClient, + NvU32 flags, + NvU64 *pLimit, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppPrivate +) +{ + NV_STATUS rmStatus = NV_OK; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS *params = + (NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS*)((NvUPtr) pDescriptor); + + struct sg_table *sgt = params->sgt; + struct drm_gem_object *gem = params->gem; + + rmStatus = nv_dma_import_sgt(nv->dma_dev, sgt, gem); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s(): Error (%d) while trying to import sgt!\n", + __FUNCTION__, rmStatus); + return rmStatus; + } + + return _createMemdescFromSgt(pGpu, flags, gem, sgt, + (*pLimit + 1), ppMemDesc, ppPrivate); +} + +static NV_STATUS +osCreateOsDescriptorFromDmaBufPtr +( + OBJGPU *pGpu, + NvP64 pDescriptor, + NvHandle hClient, + NvU32 flags, + NvU64 *pLimit, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppPrivate +) +{ + NV_STATUS rmStatus = NV_OK; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_dma_device_t *dma_dev = NULL; + NvU32 size = 0; + nv_dma_buf_t *pImportPriv = NULL; + struct sg_table *pImportSgt = NULL; + void *dmaBuf = (void*)((NvUPtr)pDescriptor); + NvBool bRoDeviceMap = NV_FALSE; + + dma_dev = GetDmaDeviceForImport(nv, flags); + + if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_DEVICE_READ_ONLY, _YES, flags)) + { + bRoDeviceMap = NV_TRUE; + NV_PRINTF(LEVEL_INFO, + "%s(): RO DMA Mapping - flags [%x]!\n", + __FUNCTION__, flags); + } + + rmStatus = nv_dma_import_dma_buf(dma_dev, dmaBuf, bRoDeviceMap, &size, + &pImportSgt, &pImportPriv); + if (rmStatus != NV_OK) + { + NV_PRINTF_COND(rmStatus == NV_ERR_NOT_SUPPORTED, LEVEL_INFO, LEVEL_ERROR, + "Error (%d) while trying to import dma_buf!\n", rmStatus); + return rmStatus; + } + + return _createMemdescFromDmaBuf(pGpu, flags, pImportPriv, + pImportSgt, + size, ppMemDesc, ppPrivate); +} + +static void +osDestroyOsDescriptorFromPhysAddr +( + PMEMORY_DESCRIPTOR pMemDesc +) +{ + OBJGPU *pGpu = pMemDesc->pGpu; + void *pPrivate; + + pPrivate = memdescGetMemData(pMemDesc); + NV_ASSERT(pPrivate != NULL); + + if (!memdescGetFlag(pMemDesc, MEMDESC_FLAGS_SKIP_IOMMU_MAPPING)) + memdescUnmapIommu(pMemDesc, pGpu->busInfo.iovaspaceId); + + nv_unregister_phys_pages(NV_GET_NV_STATE(pGpu), pPrivate); +} + +static void +osDestroyOsDescriptorFromIoMemory +( + PMEMORY_DESCRIPTOR pMemDesc +) +{ + OBJGPU *pGpu = pMemDesc->pGpu; + void *pPrivate = memdescGetMemData(pMemDesc); + + if (pPrivate == NULL) + { + return; + } + + nv_unregister_peer_io_mem(NV_GET_NV_STATE(pGpu), pPrivate); +} + +static void +osDestroyOsDescriptorPageArray +( + MEMORY_DESCRIPTOR *pMemDesc +) +{ + OBJGPU *pGpu = pMemDesc->pGpu; + NvU64 osPageCount; + NV_STATUS status; + void *pPrivate; + + pPrivate = memdescGetMemData(pMemDesc); + + NV_ASSERT(pPrivate != NULL); + + // + // TODO: Bug 1811006: Notably skip any IOMMU mapping management as the + // pMemDesc->pGpu might have been torn down already and the pGpu passed in + // doesn't necessarily have IOMMU mappings. For now just allow memdescDestroy() + // to clean up whatever is there (this may not work correctly either if any + // of the IOMMU mappings have outlasted their VASPACEs). This should + // be cleaned up once the fix for bug 1811006 is known. + // + + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc)) + { + // Because os_page_size == pMemDesc->pageArrayGranularity, we don't need to do any page array conversion. + NV_ASSERT_OR_RETURN_VOID(os_page_size == pMemDesc->pageArrayGranularity); + osPageCount = pMemDesc->PageCount; + } + else + { + osPageCount = NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount); + if ((NV_RM_PAGE_SIZE < os_page_size) && + !memdescGetContiguity(pMemDesc, AT_CPU)) + { + RmDeflateRmToOsPageArray(memdescGetPteArray(pMemDesc, AT_CPU), + pMemDesc->PageCount); + } + } + + nv_unregister_user_pages(NV_GET_NV_STATE(pGpu), osPageCount, + NULL /* import_priv */, &pPrivate); + + if (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_FOREIGN_PAGE)) + { + os_free_mem(pPrivate); + } + else + { + // + // We use MEMDESC_FLAGS_USER_READ_ONLY because this reflects the + // NVOS02_FLAGS_ALLOC_USER_READ_ONLY flag value passed into + // os_lock_user_pages(). That flag also results in + // MEMDESC_FLAGS_DEVICE_READ_ONLY being set. + // + NvBool writable = !memdescGetFlag(pMemDesc, MEMDESC_FLAGS_USER_READ_ONLY); + NvU32 flags = DRF_NUM(_LOCK_USER_PAGES, _FLAGS, _WRITE, writable); + status = os_unlock_user_pages(osPageCount, pPrivate, flags); + NV_ASSERT(status == NV_OK); + } +} + +static void +osDestroyOsDescriptorFromDmaBuf +( + PMEMORY_DESCRIPTOR pMemDesc +) +{ + OBJGPU *pGpu = pMemDesc->pGpu; + void *pPrivate = memdescGetMemData(pMemDesc); + + struct sg_table *pImportSgt; + void *pImportPriv; + + /* + * Unmap IOMMU now or we will get a kernel crash when it is unmapped after + * pImportSgt is freed. + */ + memdescUnmapIommu(pMemDesc, pGpu->busInfo.iovaspaceId); + + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc)) + { + // Because os_page_size == pMemDesc->pageArrayGranularity, we don't need to do any page array conversion. + NV_ASSERT_OR_RETURN_VOID(os_page_size == pMemDesc->pageArrayGranularity); + } + else if ((NV_RM_PAGE_SIZE < os_page_size) && + !memdescGetContiguity(pMemDesc, AT_CPU)) + { + RmDeflateRmToOsPageArray(memdescGetPteArray(pMemDesc, AT_CPU), + pMemDesc->PageCount); + } + + nv_unregister_sgt(NV_GET_NV_STATE(pGpu), &pImportSgt, + &pImportPriv, pPrivate); + + /* + * pImportSgt doesn't need to be passed to nv_dma_release_dma_buf() because + * the DMA-BUF associated with pImportPriv already has a reference to the + * SGT. + */ + + nv_dma_release_dma_buf(pImportPriv); +} + +static void +osDestroyOsDescriptorFromSgt +( + PMEMORY_DESCRIPTOR pMemDesc +) +{ + OBJGPU *pGpu = pMemDesc->pGpu; + void *pPrivate = memdescGetMemData(pMemDesc); + + struct sg_table *pImportSgt; + struct drm_gem_object *pImportPrivGem; + + NV_ASSERT(pPrivate != NULL); + + /* + * Unmap IOMMU now or we will get a kernel crash when it is unmapped after + * pImportSgt is freed. + */ + memdescUnmapIommu(pMemDesc, pGpu->busInfo.iovaspaceId); + + if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc)) + { + // Because os_page_size == pMemDesc->pageArrayGranularity, we don't need to do any page array conversion. + NV_ASSERT_OR_RETURN_VOID(os_page_size == pMemDesc->pageArrayGranularity); + } + else if ((NV_RM_PAGE_SIZE < os_page_size) && + !memdescGetContiguity(pMemDesc, AT_CPU)) + { + RmDeflateRmToOsPageArray(memdescGetPteArray(pMemDesc, AT_CPU), + pMemDesc->PageCount); + } + + nv_unregister_sgt(NV_GET_NV_STATE(pGpu), &pImportSgt, + (void **) &pImportPrivGem, pPrivate); + + nv_dma_release_sgt(pImportSgt, pImportPrivGem); +} diff --git a/userspace/sdks/nv570/nvalloc/unix/src/osnvlink.c b/userspace/sdks/nv570/nvalloc/unix/src/osnvlink.c new file mode 100644 index 0000000..af65f9e --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/src/osnvlink.c @@ -0,0 +1,783 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "osapi.h" + +#if defined(INCLUDE_NVLINK_LIB) +#include "nvlink.h" +// +// The functions in this file are a workaround for a significant design flaw +// where RM callbacks for the nvlink library are built with the altstack +// enabled, but the nvlink library is not built with altstack support. Whenever +// the library calls a callback, the stack switching needs to be accounted for +// or else we will observe corruption of data structures in the nvlink library +// as data is pushed onto what the callback thinks is the stack. See bug +// 1710300. +// +// This bug has also exposed other problems, such as the complete lack of +// locking awareness by these callbacks (e.g., assumption that the RMAPI and +// GPU locks are always held on entry, which is not a legitimate assumption). +// For now, we ignore that just to unblock testing. +// +extern NvlStatus knvlinkCoreAddLinkCallback(struct nvlink_link *); +extern NvlStatus knvlinkCoreRemoveLinkCallback(struct nvlink_link *); +extern NvlStatus knvlinkCoreLockLinkCallback(struct nvlink_link *); +extern void knvlinkCoreUnlockLinkCallback(struct nvlink_link *); +extern NvlStatus knvlinkCoreQueueLinkChangeCallback(struct nvlink_link_change *); +extern NvlStatus knvlinkCoreSetDlLinkModeCallback(struct nvlink_link *, NvU64, NvU32); +extern NvlStatus knvlinkCoreGetDlLinkModeCallback(struct nvlink_link *, NvU64 *); +extern NvlStatus knvlinkCoreSetTlLinkModeCallback(struct nvlink_link *, NvU64, NvU32); +extern NvlStatus knvlinkCoreGetTlLinkModeCallback(struct nvlink_link *, NvU64 *); +extern NvlStatus knvlinkCoreGetTxSublinkModeCallback(struct nvlink_link *, NvU64 *, NvU32 *); +extern NvlStatus knvlinkCoreSetTxSublinkModeCallback(struct nvlink_link *, NvU64, NvU32); +extern NvlStatus knvlinkCoreGetRxSublinkModeCallback(struct nvlink_link *, NvU64 *, NvU32 *); +extern NvlStatus knvlinkCoreSetRxSublinkModeCallback(struct nvlink_link *, NvU64, NvU32); +extern NvlStatus knvlinkCoreReadDiscoveryTokenCallback(struct nvlink_link *, NvU64 *); +extern NvlStatus knvlinkCoreWriteDiscoveryTokenCallback(struct nvlink_link *, NvU64); +extern void knvlinkCoreTrainingCompleteCallback(struct nvlink_link *); +extern void knvlinkCoreGetUphyLoadCallback(struct nvlink_link *, NvBool*); +extern NvlStatus knvlinkCoreGetCciLinkModeCallback(struct nvlink_link *, NvU64 *); + +/*! + * @brief Helper to allocate an alternate stack from within core RM. + * + * This needs to be an NV_API_CALL (built to use the original stack instead + * of the altstack) since it is called before we switch to using the altstack. + */ +static NV_STATUS NV_API_CALL osNvlinkAllocAltStack(nvidia_stack_t **pSp) +{ + NV_STATUS status = NV_OK; + nvidia_stack_t *sp = NULL; +#if defined(NVCPU_X86_64) && defined(__use_altstack__) + status = os_alloc_mem((void **)&sp, sizeof(nvidia_stack_t)); + if (status == NV_OK) + { + sp->size = sizeof(sp->stack); + sp->top = sp->stack + sp->size; + } +#endif + *pSp = sp; + return status; +} + +/*! + * @brief Helper to free an alternate stack from within core RM. + * + * This needs to be an NV_API_CALL (built to use the original stack instead + * of the altstack) since it is called after we've switched back to using the + * original stack. + */ +static void NV_API_CALL osNvlinkFreeAltStack(nvidia_stack_t *sp) +{ +#if defined(NVCPU_X86_64) && defined(__use_altstack__) + os_free_mem(sp); +#endif +} + +static NV_STATUS NV_API_CALL osNvlinkGetAltStack(nvidia_stack_t **sp) +{ + return osNvlinkAllocAltStack(sp); +} +static void NV_API_CALL osNvlinkPutAltStack(nvidia_stack_t *sp) +{ + osNvlinkFreeAltStack(sp); +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_add_link +( + struct nvlink_link *link +) +{ + void *fp; + NvlStatus status; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } + + NV_ENTER_RM_RUNTIME(sp, fp); + + status = knvlinkCoreAddLinkCallback(link); + + NV_EXIT_RM_RUNTIME(sp, fp); + + osNvlinkPutAltStack(sp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_remove_link +( + struct nvlink_link *link +) +{ + void *fp; + NvlStatus status; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } + + NV_ENTER_RM_RUNTIME(sp, fp); + + status = knvlinkCoreRemoveLinkCallback(link); + + NV_EXIT_RM_RUNTIME(sp, fp); + + osNvlinkPutAltStack(sp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_lock_link +( + struct nvlink_link *link +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreLockLinkCallback(link); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + osNvlinkPutAltStack(sp); + + return status; +} + +static void NV_API_CALL rm_nvlink_ops_unlock_link +( + struct nvlink_link *link +) +{ + void *fp; + THREAD_STATE_NODE threadState = {0}; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return; + } + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + knvlinkCoreUnlockLinkCallback(link); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + osNvlinkPutAltStack(sp); +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_queue_link_change +( + struct nvlink_link_change *link_change +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreQueueLinkChangeCallback(link_change); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + osNvlinkPutAltStack(sp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_set_dl_link_mode +( + struct nvlink_link *link, + NvU64 mode, + NvU32 flags +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreSetDlLinkModeCallback(link, mode, flags); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + osNvlinkPutAltStack(sp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_get_dl_link_mode +( + struct nvlink_link *link, + NvU64 *mode +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreGetDlLinkModeCallback(link, mode); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + osNvlinkPutAltStack(sp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_set_tl_link_mode +( + struct nvlink_link *link, + NvU64 mode, + NvU32 flags +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreSetTlLinkModeCallback(link, mode, flags); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + osNvlinkPutAltStack(sp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_get_tl_link_mode +( + struct nvlink_link *link, + NvU64 *mode +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreGetTlLinkModeCallback(link, mode); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + osNvlinkPutAltStack(sp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_set_link_tx_mode +( + struct nvlink_link *link, + NvU64 mode, + NvU32 flags +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreSetTxSublinkModeCallback(link, mode, flags); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + osNvlinkPutAltStack(sp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_get_link_tx_mode +( + struct nvlink_link *link, + NvU64 *mode, + NvU32 *subMode +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreGetTxSublinkModeCallback(link, mode, subMode); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + osNvlinkPutAltStack(sp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_set_link_rx_mode +( + struct nvlink_link *link, + NvU64 mode, + NvU32 flags +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreSetRxSublinkModeCallback(link, mode, flags); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + osNvlinkPutAltStack(sp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_get_link_rx_mode +( + struct nvlink_link *link, + NvU64 *mode, + NvU32 *subMode +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreGetRxSublinkModeCallback(link, mode, subMode); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + osNvlinkPutAltStack(sp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_set_link_rx_detect +( + struct nvlink_link *link, + NvU32 flags +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreSetRxSublinkDetectCallback(link, flags); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + osNvlinkPutAltStack(sp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_get_link_rx_detect +( + struct nvlink_link *link +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreGetRxSublinkDetectCallback(link); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + osNvlinkPutAltStack(sp); + + return status; +} + +static void NV_API_CALL rm_nvlink_get_uphy_load +( + struct nvlink_link *link, + NvBool *bUnlocked +) +{ + void *fp; + THREAD_STATE_NODE threadState = {0}; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return; + } + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + knvlinkCoreGetUphyLoadCallback(link, bUnlocked); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + osNvlinkPutAltStack(sp); +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_read_link_discovery_token +( + struct nvlink_link *link, + NvU64 *token +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreReadDiscoveryTokenCallback(link, token); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + osNvlinkPutAltStack(sp); + + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_write_link_discovery_token +( + struct nvlink_link *link, + NvU64 token +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreWriteDiscoveryTokenCallback(link, token); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + osNvlinkPutAltStack(sp); + + return status; +} + +static void NV_API_CALL rm_nvlink_ops_training_complete +( + struct nvlink_link *link +) +{ + void *fp; + THREAD_STATE_NODE threadState = {0}; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return; + } + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + knvlinkCoreTrainingCompleteCallback(link); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + osNvlinkPutAltStack(sp); +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_ali_training +( + struct nvlink_link *link +) +{ + void *fp; + NvlStatus status; + THREAD_STATE_NODE threadState = {0}; + nvidia_stack_t * sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } + + NV_ENTER_RM_RUNTIME(sp, fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + status = knvlinkCoreAliTrainingCallback(link); + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp, fp); + + osNvlinkPutAltStack(sp); + return status; +} + +static NvlStatus NV_API_CALL rm_nvlink_ops_get_cci_link_mode +( + struct nvlink_link *link, + NvU64 *mode +) +{ + return NVL_SUCCESS; +} + +#endif /* defined(INCLUDE_NVLINK_LIB) */ + +const struct nvlink_link_handlers* osGetNvlinkLinkCallbacks(void) +{ +#if defined(INCLUDE_NVLINK_LIB) + static const struct nvlink_link_handlers rm_nvlink_link_ops = + { + .add = rm_nvlink_ops_add_link, + .remove = rm_nvlink_ops_remove_link, + .lock = rm_nvlink_ops_lock_link, + .unlock = rm_nvlink_ops_unlock_link, + .queue_link_change = rm_nvlink_ops_queue_link_change, + .set_dl_link_mode = rm_nvlink_ops_set_dl_link_mode, + .get_dl_link_mode = rm_nvlink_ops_get_dl_link_mode, + .set_tl_link_mode = rm_nvlink_ops_set_tl_link_mode, + .get_tl_link_mode = rm_nvlink_ops_get_tl_link_mode, + .set_tx_mode = rm_nvlink_ops_set_link_tx_mode, + .get_tx_mode = rm_nvlink_ops_get_link_tx_mode, + .set_rx_mode = rm_nvlink_ops_set_link_rx_mode, + .get_rx_mode = rm_nvlink_ops_get_link_rx_mode, + .set_rx_detect = rm_nvlink_ops_set_link_rx_detect, + .get_rx_detect = rm_nvlink_ops_get_link_rx_detect, + .write_discovery_token = rm_nvlink_ops_write_link_discovery_token, + .read_discovery_token = rm_nvlink_ops_read_link_discovery_token, + .training_complete = rm_nvlink_ops_training_complete, + .get_uphy_load = rm_nvlink_get_uphy_load, + .get_cci_link_mode = rm_nvlink_ops_get_cci_link_mode, + .ali_training = rm_nvlink_ops_ali_training, + }; + + return &rm_nvlink_link_ops; +#else + return NULL; +#endif +} + +/* + * @brief Verif only function to get the chiplib overrides for link connection + * state for all NVLINKs. + * + * If chiplib overrides exist, each link can either be enabled (1) or disabled (0) + * + * @param[in] pGpu GPU object pointer + * @param[in] maxLinks Size of pLinkConnection array + * @param[out] pLinkConnection array of pLinkConnection values to be populated by MODS + * + * @return NV_OK or NV_ERR_NOT_SUPPORTED (no overrides available) + */ +NV_STATUS +osGetForcedNVLinkConnection +( + OBJGPU *pGpu, + NvU32 maxLinks, + NvU32 *pLinkConnection +) +{ + int i, ret; + NV_STATUS status; + char path[64]; + + NV_ASSERT_OR_RETURN((pLinkConnection != NULL), NV_ERR_INVALID_POINTER); + NV_ASSERT_OR_RETURN((maxLinks > 0), NV_ERR_NOT_SUPPORTED); + NV_ASSERT_OR_RETURN((pGpu != NULL), NV_ERR_INVALID_ARGUMENT); + + for (i = 0; i < maxLinks; i++) + { + ret = os_snprintf(path, sizeof(path), "CPU_MODEL|CM_ATS_ADDRESS|NVLink%u", i); + NV_ASSERT((ret > 0) && (ret < (sizeof(path) - 1))); + + status = gpuSimEscapeRead(pGpu, path, 0, 4, &pLinkConnection[i]); + if (status == NV_OK) + { + NV_PRINTF(LEVEL_INFO, "%s: %s=0x%X\n", __FUNCTION__, + path, pLinkConnection[i]); + } + else + { + NV_PRINTF(LEVEL_INFO, "%s: gpuSimEscapeRead for '%s' failed (%u)\n", + __FUNCTION__, path, status); + return NV_ERR_NOT_SUPPORTED; + } + } + return NV_OK; +} + +/* + * @brief Get Platform suggested NVLink linerate + * + * NVLink will use this function to get the platform suggested linerate + * if available in FRU or device tree. + * + * @param[in] pGpu GPU object pointer + * @param[out] NvU32 * Suggested datarate + * + * @return NV_OK or NV_ERR_NOT_SUPPORTED (platform linerate data not available) + */ +NV_STATUS +osGetPlatformNvlinkLinerate +( + OBJGPU *pGpu, + NvU32 *lineRate +) +{ + // TODO: Remove this function + return NV_ERR_NOT_SUPPORTED; +} diff --git a/userspace/sdks/nv570/nvalloc/unix/src/osunix.c b/userspace/sdks/nv570/nvalloc/unix/src/osunix.c new file mode 100644 index 0000000..635bf86 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/src/osunix.c @@ -0,0 +1,42 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/***************************** HW State Routines ***************************\ +* * +* Fills in os specific function pointers for the Unix OS object. * +* * +\***************************************************************************/ + +#include +#include + +void +osInitObjOS(OBJOS *pOS) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + + pSys->setProperty(pSys, PDB_PROP_SYS_ONDEMAND_VBLANK_CONTROL_ENABLE_DEFAULT, NV_TRUE); + pOS->setProperty(pOS, PDB_PROP_OS_CACHED_MEMORY_MAPPINGS_FOR_ACPI_TABLE, NV_TRUE); + pOS->setProperty(pOS, PDB_PROP_OS_LIMIT_GPU_RESET, NV_TRUE); +} diff --git a/userspace/sdks/nv570/nvalloc/unix/src/power-management-tegra.c b/userspace/sdks/nv570/nvalloc/unix/src/power-management-tegra.c new file mode 100644 index 0000000..38c91d0 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/src/power-management-tegra.c @@ -0,0 +1,100 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +#include +#include +#include + +NV_STATUS +RmPowerManagementTegra( + OBJGPU *pGpu, + nv_pm_action_t pmAction +) +{ + // + // Default to NV_OK. there may cases where resman is loaded, but + // no devices are allocated (we're still at the console). in these + // cases, it's fine to let the system do whatever it wants. + // + NV_STATUS rmStatus = NV_OK; + + if (pGpu) + { + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + switch (pmAction) + { + case NV_PM_ACTION_HIBERNATE: + nvp->pm_state.InHibernate = NV_TRUE; + pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_PM_CODEPATH, NV_TRUE); + rmStatus = gpuStateUnload(pGpu, GPU_STATE_FLAGS_PM_HIBERNATE | + GPU_STATE_FLAGS_PRESERVING | + GPU_STATE_FLAGS_PM_TRANSITION); + pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_HIBERNATE, NV_TRUE); + break; + + case NV_PM_ACTION_STANDBY: + nvp->pm_state.InHibernate = NV_FALSE; + pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_PM_CODEPATH, NV_TRUE); + rmStatus = gpuStateUnload(pGpu, GPU_STATE_FLAGS_PM_SUSPEND | + GPU_STATE_FLAGS_PRESERVING | + GPU_STATE_FLAGS_PM_TRANSITION);; + pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_STANDBY, NV_TRUE); + pGpu->bInD3Cold = NV_TRUE; + break; + + case NV_PM_ACTION_RESUME: + pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_PM_RESUME_CODEPATH, NV_TRUE); + + if (nvp->pm_state.InHibernate) + { + rmStatus = gpuStateLoad(pGpu, GPU_STATE_FLAGS_PM_HIBERNATE | + GPU_STATE_FLAGS_PRESERVING | + GPU_STATE_FLAGS_PM_TRANSITION);; + pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_HIBERNATE, NV_FALSE); + } + else + { + rmStatus = gpuStateLoad(pGpu, GPU_STATE_FLAGS_PM_SUSPEND | + GPU_STATE_FLAGS_PRESERVING | + GPU_STATE_FLAGS_PM_TRANSITION);; + pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_STANDBY, NV_FALSE); + pGpu->bInD3Cold = NV_FALSE; + } + + pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_PM_CODEPATH, NV_FALSE); + pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_PM_RESUME_CODEPATH, NV_FALSE); + break; + + default: + rmStatus = NV_ERR_INVALID_ARGUMENT; + break; + } + } + + return rmStatus; +} + diff --git a/userspace/sdks/nv570/nvalloc/unix/src/registry.c b/userspace/sdks/nv570/nvalloc/unix/src/registry.c new file mode 100644 index 0000000..70bbcc5 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/src/registry.c @@ -0,0 +1,712 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#if defined(DEBUG_REGISTRY) +#define DBG_REG_PRINTF(a, ...) \ + NV_PRINTF(LEVEL_INFO, a, ##__VA_ARGS__) +#else +#define DBG_REG_PRINTF(a, ...) +#endif + +static NvS32 stringCaseCompare( + const char *string1, + const char *string2 +) +{ + NvU8 c1, c2; + + do + { + c1 = *string1, c2 = *string2; + if (c1 >= 'A' && c1 <= 'Z') + c1 += ('a' - 'A'); + if (c2 >= 'A' && c2 <= 'Z') + c2 += ('a' - 'A'); + string1++, string2++; + } + while ((c1 == c2) && (c1 != '\0')); + + return (c1 - c2); +} + +static nv_reg_entry_t *the_registry = NULL; + +static nv_reg_entry_t* regCreateNewRegistryKey( + nv_state_t *nv, + const char *regParmStr +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + nv_reg_entry_t *new_reg = NULL; + char *new_ParmStr = NULL; + NvU32 parm_size; + + if (regParmStr == NULL) + { + DBG_BREAKPOINT(); + return NULL; + } + + new_reg = portMemAllocNonPaged(sizeof(nv_reg_entry_t)); + if (NULL == new_reg) + { + NV_PRINTF(LEVEL_ERROR, "failed to grow registry\n"); + return NULL; + } + + portMemSet(new_reg, 0, sizeof(nv_reg_entry_t)); + + if (regParmStr != NULL) + { + parm_size = (portStringLength(regParmStr) + 1); + new_ParmStr = portMemAllocNonPaged(parm_size); + if (NULL == new_ParmStr) + { + NV_PRINTF(LEVEL_ERROR, "failed to allocate registry param string\n"); + portMemFree(new_reg); + return NULL; + } + + NV_ASSERT(parm_size <= NVOS38_MAX_REGISTRY_STRING_LENGTH); + + if (portMemCopy(new_ParmStr, parm_size, regParmStr, parm_size) == NULL) + { + NV_PRINTF(LEVEL_ERROR, "failed to copy registry param string\n"); + portMemFree(new_ParmStr); + portMemFree(new_reg); + return NULL; + } + } + + new_reg->regParmStr = new_ParmStr; + new_reg->type = NV_REGISTRY_ENTRY_TYPE_UNKNOWN; + + if (nvp != NULL) + { + new_reg->next = nvp->pRegistry; + nvp->pRegistry = new_reg; + DBG_REG_PRINTF("local registry now at 0x%p\n", nvp->pRegistry); + } + else + { + new_reg->next = the_registry; + the_registry = new_reg; + DBG_REG_PRINTF("global registry now at 0x%p\n", the_registry); + } + + return new_reg; +} + +static NV_STATUS regFreeEntry(nv_reg_entry_t *tmp) +{ + portMemFree(tmp->regParmStr); + tmp->regParmStr = NULL; + { + portMemFree(tmp->pdata); + tmp->pdata = NULL; + tmp->len = 0; + } + portMemFree(tmp); + + return NV_OK; +} + +static nv_reg_entry_t* regFindRegistryEntry( + nv_state_t *nv, + const char *regParmStr, + NvU32 type, + NvBool *bGlobalEntry +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + nv_reg_entry_t *tmp; + + DBG_REG_PRINTF("%s: %s\n", __FUNCTION__, regParmStr); + + if (nvp != NULL) + { + tmp = nvp->pRegistry; + DBG_REG_PRINTF(" local registry at 0x%p\n", tmp); + + while ((tmp != NULL) && (tmp->regParmStr != NULL)) + { + DBG_REG_PRINTF(" Testing against %s\n", + tmp->regParmStr); + if ((stringCaseCompare(tmp->regParmStr, regParmStr) == 0) && + (type == tmp->type)) + { + DBG_REG_PRINTF(" found a match!\n"); + if (bGlobalEntry) + *bGlobalEntry = NV_FALSE; + return tmp; + } + tmp = tmp->next; + } + } + + tmp = the_registry; + DBG_REG_PRINTF(" global registry at 0x%p\n", tmp); + + while ((tmp != NULL) && (tmp->regParmStr != NULL)) + { + DBG_REG_PRINTF(" Testing against %s\n", + tmp->regParmStr); + if ((stringCaseCompare(tmp->regParmStr, regParmStr) == 0) && + (type == tmp->type)) + { + DBG_REG_PRINTF(" found a match!\n"); + if (bGlobalEntry) + *bGlobalEntry = NV_TRUE; + return tmp; + } + tmp = tmp->next; + } + + DBG_REG_PRINTF(" no match\n"); + return NULL; +} + +NV_STATUS RmWriteRegistryDword( + nv_state_t *nv, + const char *regParmStr, + NvU32 Data +) +{ + nv_reg_entry_t *tmp; + NvBool bGlobalEntry; + + if (regParmStr == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + DBG_REG_PRINTF("%s: %s -> 0x%x\n", __FUNCTION__, regParmStr, Data); + + tmp = regFindRegistryEntry(nv, regParmStr, + NV_REGISTRY_ENTRY_TYPE_DWORD, &bGlobalEntry); + + // If we found an entry and we were looking for a global entry and + // found a global, or we were looking for a per-GPU entry and found a + // per-GPU entry + if (tmp != NULL && + ((nv == NULL && bGlobalEntry) || + (nv != NULL && !bGlobalEntry))) + { + tmp->data = Data; + + if (stringCaseCompare(regParmStr, "ResmanDebugLevel") == 0) + { + os_dbg_set_level(Data); + } + + return NV_OK; + } + + tmp = regCreateNewRegistryKey(nv, regParmStr); + if (tmp == NULL) + return NV_ERR_GENERIC; + + tmp->type = NV_REGISTRY_ENTRY_TYPE_DWORD; + tmp->data = Data; + + return NV_OK; +} + +NV_STATUS RmReadRegistryDword( + nv_state_t *nv, + const char *regParmStr, + NvU32 *Data +) +{ + nv_reg_entry_t *tmp; + + if ((regParmStr == NULL) || (Data == NULL)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + DBG_REG_PRINTF("%s: %s\n", __FUNCTION__, regParmStr); + + tmp = regFindRegistryEntry(nv, regParmStr, + NV_REGISTRY_ENTRY_TYPE_DWORD, NULL); + if (tmp == NULL) + { + tmp = regFindRegistryEntry(nv, regParmStr, + NV_REGISTRY_ENTRY_TYPE_BINARY, NULL); + if ((tmp != NULL) && (tmp->len >= sizeof(NvU32))) + { + *Data = *(NvU32 *)tmp->pdata; + } + else + { + DBG_REG_PRINTF(" not found\n"); + return NV_ERR_GENERIC; + } + } + else + { + *Data = tmp->data; + } + + DBG_REG_PRINTF(" found in the_registry: 0x%x\n", *Data); + + return NV_OK; +} + +NV_STATUS RmReadRegistryBinary( + nv_state_t *nv, + const char *regParmStr, + NvU8 *Data, + NvU32 *cbLen +) +{ + nv_reg_entry_t *tmp; + NV_STATUS status; + + if ((regParmStr == NULL) || (Data == NULL) || (cbLen == NULL)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + DBG_REG_PRINTF("%s: %s\n", __FUNCTION__, regParmStr); + + tmp = regFindRegistryEntry(nv, regParmStr, + NV_REGISTRY_ENTRY_TYPE_BINARY, NULL); + if (tmp == NULL) + { + DBG_REG_PRINTF(" not found\n"); + return NV_ERR_GENERIC; + } + + DBG_REG_PRINTF(" found\n"); + + if (*cbLen >= tmp->len) + { + portMemCopy((NvU8 *)Data, *cbLen, (NvU8 *)tmp->pdata, tmp->len); + *cbLen = tmp->len; + status = NV_OK; + } + else + { + NV_PRINTF(LEVEL_ERROR, + "buffer (length: %u) is too small (data length: %u)\n", + *cbLen, tmp->len); + status = NV_ERR_GENERIC; + } + + return status; +} + +NV_STATUS RmWriteRegistryBinary( + nv_state_t *nv, + const char *regParmStr, + NvU8 *Data, + NvU32 cbLen +) +{ + nv_reg_entry_t *tmp; + NvBool bGlobalEntry; + + if ((regParmStr == NULL) || (Data == NULL)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + DBG_REG_PRINTF("%s: %s\n", __FUNCTION__, regParmStr); + + tmp = regFindRegistryEntry(nv, regParmStr, + NV_REGISTRY_ENTRY_TYPE_BINARY, &bGlobalEntry); + + // If we found an entry and we were looking for a global entry and + // found a global, or we were looking for a per-GPU entry and found a + // per-GPU entry + if (tmp != NULL && + ((nv == NULL && bGlobalEntry) || + (nv != NULL && !bGlobalEntry))) + { + if (tmp->pdata != NULL) + { + portMemFree(tmp->pdata); + tmp->pdata = NULL; + tmp->len = 0; + } + } + else + { + tmp = regCreateNewRegistryKey(nv, regParmStr); + if (tmp == NULL) + { + NV_PRINTF(LEVEL_ERROR, "failed to create binary registry entry\n"); + return NV_ERR_GENERIC; + } + } + + tmp->pdata = portMemAllocNonPaged(cbLen); + if (NULL == tmp->pdata) + { + NV_PRINTF(LEVEL_ERROR, "failed to write binary registry entry\n"); + return NV_ERR_GENERIC; + } + + tmp->type = NV_REGISTRY_ENTRY_TYPE_BINARY; + tmp->len = cbLen; + portMemCopy((NvU8 *)tmp->pdata, tmp->len, (NvU8 *)Data, cbLen); + + return NV_OK; +} + +NV_STATUS RmWriteRegistryString( + nv_state_t *nv, + const char *regParmStr, + const char *buffer, + NvU32 bufferLength +) +{ + nv_reg_entry_t *tmp; + NvBool bGlobalEntry; + + if ((regParmStr == NULL) || (buffer == NULL)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + DBG_REG_PRINTF("%s: %s\n", __FUNCTION__, regParmStr); + + tmp = regFindRegistryEntry(nv, regParmStr, + NV_REGISTRY_ENTRY_TYPE_STRING, &bGlobalEntry); + + // If we found an entry and we were looking for a global entry and + // found a global, or we were looking for a per-GPU entry and found a + // per-GPU entry + if (tmp != NULL && + ((nv == NULL && bGlobalEntry) || + (nv != NULL && !bGlobalEntry))) + { + if (tmp->pdata != NULL) + { + portMemFree(tmp->pdata); + tmp->len = 0; + tmp->pdata = NULL; + } + } + else + { + tmp = regCreateNewRegistryKey(nv, regParmStr); + if (tmp == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "failed to allocate a string registry entry!\n"); + return NV_ERR_INSUFFICIENT_RESOURCES; + } + } + + tmp->pdata = portMemAllocNonPaged(bufferLength); + if (tmp->pdata == NULL) + { + NV_PRINTF(LEVEL_ERROR, "failed to write a string registry entry!\n"); + return NV_ERR_NO_MEMORY; + } + + tmp->type = NV_REGISTRY_ENTRY_TYPE_STRING; + tmp->len = bufferLength; + portMemCopy((void *)tmp->pdata, tmp->len, buffer, (bufferLength - 1)); + tmp->pdata[bufferLength-1] = '\0'; + + return NV_OK; +} + +NV_STATUS RmReadRegistryString( + nv_state_t *nv, + const char *regParmStr, + NvU8 *buffer, + NvU32 *pBufferLength +) +{ + NvU32 bufferLength; + nv_reg_entry_t *tmp; + + if ((regParmStr == NULL) || (buffer == NULL) || (pBufferLength == NULL)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + DBG_REG_PRINTF("%s: %s\n", __FUNCTION__, regParmStr); + + bufferLength = *pBufferLength; + *pBufferLength = 0; + *buffer = '\0'; + + tmp = regFindRegistryEntry(nv, regParmStr, + NV_REGISTRY_ENTRY_TYPE_STRING, NULL); + if (tmp == NULL) + { + return NV_ERR_GENERIC; + } + + if (bufferLength >= tmp->len) + { + portMemCopy((void *)buffer, bufferLength, (void *)tmp->pdata, tmp->len); + *pBufferLength = tmp->len; + } + else + { + NV_PRINTF(LEVEL_ERROR, + "buffer (length: %u) is too small (data length: %u)\n", + bufferLength, tmp->len); + return NV_ERR_BUFFER_TOO_SMALL; + } + + return NV_OK; +} + + +NV_STATUS RmInitRegistry(void) +{ + NV_STATUS rmStatus; + + rmStatus = os_registry_init(); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to initialize the OS registry!\n"); + } + + return rmStatus; +} + +NV_STATUS RmDestroyRegistry(nv_state_t *nv) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + nv_reg_entry_t *tmp; + + if (nvp != NULL) + { + tmp = nvp->pRegistry; + nvp->pRegistry = NULL; + } + else + { + tmp = the_registry; + the_registry = NULL; + } + + while (tmp != NULL) + { + nv_reg_entry_t *entry = tmp; + tmp = tmp->next; + regFreeEntry(entry); + } + + return NV_OK; +} + +static void regCountEntriesAndSize( + NvU32 *pNumEntries, // Pointer to number of entries + NvU32 *pSize, // Pointer to total size + nv_reg_entry_t *pRegEntry // Pointer local or global registry +) +{ + // + // Note that *pNumEntries and *pSize are not initialized here. This is so + // we can accumulate totals of both global and local registries. + // + NvU32 numEntries = *pNumEntries; + NvU32 size = *pSize; + + while ((pRegEntry != NULL) && (pRegEntry->regParmStr != NULL)) + { + size += portStringLength(pRegEntry->regParmStr) + 1 + pRegEntry->len; + numEntries++; + pRegEntry = pRegEntry->next; + } + + *pNumEntries = numEntries; + *pSize = size; +} + +static NV_STATUS regCopyEntriesToPackedBuffer( + PACKED_REGISTRY_TABLE *pRegTable, // Pointer to packed record + nv_reg_entry_t *pRegEntry, // Pointer local or global registry + NvU32 *pEntryIndex, // Pointer to next index + NvU32 *pDataOffset // Pointer to offset of next data byte. +) +{ + NvU8 *pByte = (NvU8 *)pRegTable; // Byte version of record pointer. + NV_STATUS nvStatus = NV_OK; + NvU32 entryIndex = *pEntryIndex; + NvU32 dataOffset = *pDataOffset; + + // Walk the records and copy the data. + while ((pRegEntry != NULL) && (pRegEntry->regParmStr != NULL)) + { + PACKED_REGISTRY_ENTRY *pEntry = &pRegTable->entries[entryIndex]; + NvU32 slen = portStringLength(pRegEntry->regParmStr) + 1; + + // Sanity check the data offset and index against counted totals. + if ((dataOffset + slen + pRegEntry->len > pRegTable->size) || + (entryIndex >= pRegTable->numEntries)) + { + // Something has changed since we counted them? + NV_PRINTF(LEVEL_ERROR, "Registry entry record is full\n"); + nvStatus = NV_ERR_INVALID_STATE; + break; + } + + // Copy registry entry name to data blob. + pEntry->nameOffset = dataOffset; + portMemCopy(&pByte[dataOffset], slen, pRegEntry->regParmStr, slen); + dataOffset += slen; + + switch (pRegEntry->type) + { + case NV_REGISTRY_ENTRY_TYPE_DWORD: + pEntry->type = REGISTRY_TABLE_ENTRY_TYPE_DWORD; + pEntry->length = sizeof(NvU32); + pEntry->data = pRegEntry->data; + break; + + case NV_REGISTRY_ENTRY_TYPE_BINARY: + case NV_REGISTRY_ENTRY_TYPE_STRING: + pEntry->type = REGISTRY_TABLE_ENTRY_TYPE_STRING; + if (pRegEntry->type == NV_REGISTRY_ENTRY_TYPE_BINARY) + pEntry->type = REGISTRY_TABLE_ENTRY_TYPE_BINARY; + + if (pRegEntry->len == 0) + { + NV_PRINTF(LEVEL_WARNING, + "Registry Key not sent to GSP-RM because it has 0 DataLength\n"); + break; + } + pEntry->length = pRegEntry->len; + pEntry->data = dataOffset; + portMemCopy(&pByte[dataOffset], pEntry->length, + pRegEntry->pdata, pRegEntry->len); + dataOffset += pRegEntry->len; + break; + + default: + // We should never get here. + pEntry->type = REGISTRY_TABLE_ENTRY_TYPE_UNKNOWN; + pEntry->length = 0; + pEntry->data = 0; + DBG_BREAKPOINT(); + break; + } + + pRegEntry = pRegEntry->next; + entryIndex++; + } + + *pEntryIndex = entryIndex; + *pDataOffset = dataOffset; + return nvStatus; +} + +// Package registry entries +NV_STATUS RmPackageRegistry( + nv_state_t *nv, + PACKED_REGISTRY_TABLE *pRegTable, + NvU32 *pSize +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + nv_reg_entry_t *pLocalRegistry = NULL; + NV_STATUS nvStatus = NV_OK; + NvU32 totalSize; + NvU32 numEntries; + + if (pSize == NULL) + return NV_ERR_INVALID_ARGUMENT; + + // Use the local (per-device) registry if we have one. + if (nvp != NULL) + pLocalRegistry = nvp->pRegistry; + + numEntries = 0; + totalSize = NV_OFFSETOF(PACKED_REGISTRY_TABLE, entries); + + // Count the number of global entries and total size. + regCountEntriesAndSize(&numEntries, &totalSize, the_registry); + + // Count the number of local entries and total size. + regCountEntriesAndSize(&numEntries, &totalSize, pLocalRegistry); + + // Add table record size into total size. + totalSize += sizeof(PACKED_REGISTRY_ENTRY) * numEntries; + + // + // If this function is called to only compute total size of registry table, + // then we are done here. + // + if (pRegTable == NULL) + { + *pSize = totalSize; + return NV_OK; + } + + // Return warning if there are no registry entries. + if (numEntries == 0) + return NV_WARN_NOTHING_TO_DO; + + if (totalSize > *pSize) + { + NV_PRINTF(LEVEL_ERROR, "Registry entries overflow RPC record\n"); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Fill in our new structure with the first pass (counting) values. + pRegTable->size = totalSize; + *pSize = totalSize; + pRegTable->numEntries = numEntries; + + // Offset of first byte after the registry entry table. + totalSize = NV_OFFSETOF(PACKED_REGISTRY_TABLE, entries) + + (sizeof(PACKED_REGISTRY_ENTRY) * numEntries); + + // Starting index in the registry entry table. + numEntries = 0; + + // Walk the global registry and copy the data. + nvStatus = regCopyEntriesToPackedBuffer(pRegTable, + the_registry, &numEntries, &totalSize); + + // Walk the local registry and copy the data. + if (nvStatus == NV_OK) + { + nvStatus = regCopyEntriesToPackedBuffer(pRegTable, + pLocalRegistry, &numEntries, &totalSize); + } + + // Sanity check second pass against first pass. + if ((numEntries != pRegTable->numEntries) || (totalSize != pRegTable->size)) + { + NV_PRINTF(LEVEL_ERROR, "First/second pass mismatch\n"); + nvStatus = NV_ERR_INVALID_STATE; + } + + return nvStatus; +} + diff --git a/userspace/sdks/nv570/nvalloc/unix/src/rm-gpu-ops.c b/userspace/sdks/nv570/nvalloc/unix/src/rm-gpu-ops.c new file mode 100644 index 0000000..688b4c5 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/src/rm-gpu-ops.c @@ -0,0 +1,1079 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include "rmapi/nv_gpu_ops.h" +#include "gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h" + +NV_STATUS NV_API_CALL rm_gpu_ops_create_session( + nvidia_stack_t *sp, + struct gpuSession **session) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCreateSession(session); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_destroy_session ( + nvidia_stack_t *sp, gpuSessionHandle session) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsDestroySession(session); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_device_create ( + nvidia_stack_t *sp, + nvgpuSessionHandle_t session, + const gpuInfo *pGpuInfo, + const NvProcessorUuid *gpuUuid, + nvgpuDeviceHandle_t *device, + NvBool bCreateSmcPartition) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsDeviceCreate(session, pGpuInfo, gpuUuid, device, bCreateSmcPartition); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_device_destroy ( + nvidia_stack_t *sp, + gpuDeviceHandle device) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsDeviceDestroy(device); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_address_space_create ( + nvidia_stack_t *sp, + gpuDeviceHandle device, + NvU64 vaBase, + NvU64 vaSize, + NvU32 enableAts, + gpuAddressSpaceHandle *vaSpace, + gpuAddressSpaceInfo *vaSpaceInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsAddressSpaceCreate(device, vaBase, vaSize, enableAts, + vaSpace, vaSpaceInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_dup_address_space( + nvidia_stack_t *sp, + gpuDeviceHandle device, + NvHandle hUserClient, + NvHandle hUserVASpace, + gpuAddressSpaceHandle *dupedVaspace, + gpuAddressSpaceInfo *vaSpaceInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsDupAddressSpace(device, hUserClient, hUserVASpace, + dupedVaspace, vaSpaceInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_address_space_destroy(nvidia_stack_t *sp, + gpuAddressSpaceHandle vaspace) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + nvGpuOpsAddressSpaceDestroy(vaspace); + NV_EXIT_RM_RUNTIME(sp,fp); + return NV_OK; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_memory_alloc_fb( + nvidia_stack_t *sp, gpuAddressSpaceHandle vaspace, + NvLength size, NvU64 *gpuOffset, gpuAllocInfo *allocInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsMemoryAllocFb(vaspace, size, gpuOffset, allocInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_get_p2p_caps(nvidia_stack_t *sp, + gpuDeviceHandle device1, + gpuDeviceHandle device2, + getP2PCapsParams *pP2pCapsParams) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsGetP2PCaps(device1, device2, pP2pCapsParams); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_memory_alloc_sys( + nvidia_stack_t *sp, gpuAddressSpaceHandle vaspace, + NvLength size, NvU64 *gpuOffset, gpuAllocInfo *allocInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsMemoryAllocSys(vaspace, size, gpuOffset, allocInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_pma_register_callbacks( + nvidia_stack_t *sp, + void *pPma, + pmaEvictPagesCb_t evictPages, + pmaEvictRangeCb_t evictRange, + void *callbackData) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + rmStatus = pmaRegisterEvictionCb(pPma, evictPages, evictRange, callbackData); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +void NV_API_CALL rm_gpu_ops_pma_unregister_callbacks( + nvidia_stack_t *sp, + void *pPma) +{ + THREAD_STATE_NODE threadState; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + pmaUnregisterEvictionCb(pPma); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NV_STATUS NV_API_CALL rm_gpu_ops_get_pma_object( + nvidia_stack_t *sp, + gpuDeviceHandle device, + void **pPma, + const nvgpuPmaStatistics_t *pPmaPubStats) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsGetPmaObject(device, pPma, + (const UvmPmaStatistics **)pPmaPubStats); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_pma_alloc_pages( + nvidia_stack_t *sp, void *pPma, + NvLength pageCount, NvU64 pageSize, + nvgpuPmaAllocationOptions_t pPmaAllocOptions, + NvU64 *pPages) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsPmaAllocPages(pPma, pageCount, pageSize, + pPmaAllocOptions, pPages); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_pma_pin_pages( + nvidia_stack_t *sp, void *pPma, + NvU64 *pPages, NvLength pageCount, NvU64 pageSize, NvU32 flags) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsPmaPinPages(pPma, pPages, pageCount, pageSize, flags); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_memory_cpu_map( + nvidia_stack_t *sp, gpuAddressSpaceHandle vaspace, + NvU64 gpuOffset, NvLength length, void **cpuPtr, NvU64 pageSize) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsMemoryCpuMap(vaspace, gpuOffset, length, cpuPtr, + pageSize); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_memory_cpu_ummap( + nvidia_stack_t *sp, gpuAddressSpaceHandle vaspace, void* cpuPtr) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + nvGpuOpsMemoryCpuUnMap(vaspace, cpuPtr); + NV_EXIT_RM_RUNTIME(sp,fp); + return NV_OK; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_tsg_allocate(nvidia_stack_t *sp, + gpuAddressSpaceHandle vaspace, + const gpuTsgAllocParams *allocParams, + gpuTsgHandle *tsg) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsTsgAllocate(vaspace, allocParams, tsg); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_tsg_destroy(nvidia_stack_t * sp, + nvgpuTsgHandle_t tsg) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + nvGpuOpsTsgDestroy(tsg); + NV_EXIT_RM_RUNTIME(sp,fp); + return NV_OK; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_channel_allocate(nvidia_stack_t *sp, + const gpuTsgHandle tsg, + const gpuChannelAllocParams *allocParams, + gpuChannelHandle *channel, + gpuChannelInfo *channelInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsChannelAllocate(tsg, allocParams, channel, + channelInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_channel_destroy(nvidia_stack_t * sp, + nvgpuChannelHandle_t channel) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + nvGpuOpsChannelDestroy(channel); + NV_EXIT_RM_RUNTIME(sp,fp); + return NV_OK; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_pma_free_pages(nvidia_stack_t *sp, + void *pPma, NvU64 *pPages, NvLength pageCount, NvU64 pageSize, NvU32 flags) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + nvGpuOpsPmaFreePages(pPma, pPages, pageCount, pageSize, flags); + NV_EXIT_RM_RUNTIME(sp,fp); + return NV_OK; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_memory_free( + nvidia_stack_t *sp, gpuAddressSpaceHandle vaspace, NvU64 gpuOffset) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + nvGpuOpsMemoryFree(vaspace, gpuOffset); + NV_EXIT_RM_RUNTIME(sp,fp); + return NV_OK; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_query_caps(nvidia_stack_t *sp, + gpuDeviceHandle device, + gpuCaps * caps) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsQueryCaps(device, caps); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_query_ces_caps(nvidia_stack_t *sp, + gpuDeviceHandle device, + gpuCesCaps *caps) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsQueryCesCaps(device, caps); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_get_gpu_info(nvidia_stack_t *sp, + const NvProcessorUuid *pUuid, + const gpuClientInfo *pGpuClientInfo, + gpuInfo *pGpuInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsGetGpuInfo(pUuid, pGpuClientInfo, pGpuInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_service_device_interrupts_rm(nvidia_stack_t *sp, + gpuDeviceHandle device) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsServiceDeviceInterruptsRM(device); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_set_page_directory (nvidia_stack_t *sp, + gpuAddressSpaceHandle vaSpace, + NvU64 physAddress, unsigned numEntries, + NvBool bVidMemAperture, NvU32 pasid, + NvU64 *dmaAddress) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsSetPageDirectory(vaSpace, physAddress, numEntries, + bVidMemAperture, pasid, dmaAddress); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_unset_page_directory (nvidia_stack_t *sp, + gpuAddressSpaceHandle vaSpace) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsUnsetPageDirectory(vaSpace); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_dup_allocation(nvidia_stack_t *sp, + gpuAddressSpaceHandle srcVaSpace, + NvU64 srcAddress, + gpuAddressSpaceHandle dstVaSpace, + NvU64 dstVaAlignment, + NvU64 *dstAddress) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsDupAllocation(srcVaSpace, srcAddress, dstVaSpace, dstVaAlignment, dstAddress); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_dup_memory (nvidia_stack_t *sp, + gpuDeviceHandle device, + NvHandle hClient, + NvHandle hPhysMemory, + NvHandle *hDupMemory, + nvgpuMemoryInfo_t gpuMemoryInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsDupMemory(device, hClient, hPhysMemory, hDupMemory, gpuMemoryInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_free_duped_handle (nvidia_stack_t *sp, + gpuDeviceHandle device, + NvHandle hPhysHandle) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsFreeDupedHandle(device, hPhysHandle); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_get_fb_info (nvidia_stack_t *sp, + gpuDeviceHandle device, + gpuFbInfo * fbInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsGetFbInfo(device, fbInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_get_ecc_info (nvidia_stack_t *sp, + gpuDeviceHandle device, + gpuEccInfo * eccInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsGetEccInfo(device, eccInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +// +// Please see the comments for nvUvmInterfaceOwnPageFaultIntr(), in +// nv_uvm_interface.h, for the recommended way to use this routine. +// +// How it works: +// +// The rmGpuLocksAcquire call generally saves the current GPU interrupt +// state, then disables interrupt generation for one (or all) GPUs. +// Likewise, the rmGpuLocksRelease call restores (re-enables) those +// interrupts to their previous state. However, the rmGpuLocksRelease +// call does NOT restore interrupts that RM does not own. +// +// This is rather hard to find in the code, so: very approximately, the +// following sequence happens: rmGpuLocksRelease, osEnableInterrupts, +// intrRestoreNonStall_HAL, intrEncodeIntrEn_HAL, and that last one skips +// over any interrupts that RM does not own. +// +// This means that things are a bit asymmetric, because this routine +// actually changes that ownership in between the rmGpuLocksAcquire and +// rmGpuLocksRelease calls. So: +// +// -- If you call this routine with bOwnInterrupts == NV_TRUE (UVM is +// taking ownership from the RM), then rmGpuLocksAcquire disables all +// GPU interrupts. Then the ownership is taken away from RM, so the +// rmGpuLocksRelease call leaves the replayable page fault interrupts +// disabled. It is then up to UVM (the caller) to enable replayable +// page fault interrupts when it is ready. +// +// -- If you call this routine with bOwnInterrupts == NV_FALSE (UVM is +// returning ownership to the RM), then rmGpuLocksAcquire disables +// all GPU interrupts that RM owns. Then the ownership is returned to +// RM, so the rmGpuLocksRelease call re-enables replayable page fault +// interrupts. So, that implies that you need to disable replayable page +// fault interrupts before calling this routine, in order to hand +// over a GPU to RM that is not generating interrupts, until RM is +// ready to handle the interrupts. +// +NV_STATUS NV_API_CALL rm_gpu_ops_own_page_fault_intr(nvidia_stack_t *sp, + struct gpuDevice *device, + NvBool bOwnInterrupts) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsOwnPageFaultIntr(device, bOwnInterrupts); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_init_fault_info (nvidia_stack_t *sp, + gpuDeviceHandle device, + gpuFaultInfo *pFaultInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsInitFaultInfo(device, pFaultInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_destroy_fault_info (nvidia_stack_t *sp, + gpuDeviceHandle device, + gpuFaultInfo *pFaultInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsDestroyFaultInfo(device, pFaultInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +// Functions +// +// - rm_gpu_ops_has_pending_non_replayable_faults +// - rm_gpu_ops_get_non_replayable_faults +// +// Cannot take the GPU/RM lock because it is called during fault servicing. +// This could produce deadlocks if the UVM bottom half gets stuck behind a +// stalling interrupt that cannot be serviced if UVM is holding the lock. +// +// However, these functions can be safely called with no locks because it is +// just accessing the given client shadow fault buffer, which is implemented +// using a lock-free queue. There is a different client shadow fault buffer +// per GPU: RM top-half producer, UVM top/bottom-half consumer. + +NV_STATUS NV_API_CALL rm_gpu_ops_has_pending_non_replayable_faults(nvidia_stack_t *sp, + gpuFaultInfo *pFaultInfo, + NvBool *hasPendingFaults) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsHasPendingNonReplayableFaults(pFaultInfo, hasPendingFaults); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_get_non_replayable_faults(nvidia_stack_t *sp, + gpuFaultInfo *pFaultInfo, + void *faultBuffer, + NvU32 *numFaults) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsGetNonReplayableFaults(pFaultInfo, faultBuffer, numFaults); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_flush_replayable_fault_buffer(nvidia_stack_t *sp, + gpuFaultInfo *pFaultInfo, + NvBool bCopyAndFlush) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsFlushReplayableFaultBuffer(pFaultInfo, bCopyAndFlush); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_toggle_prefetch_faults(nvidia_stack_t *sp, + gpuFaultInfo *pFaultInfo, + NvBool bEnable) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsTogglePrefetchFaults(pFaultInfo, bEnable); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_access_bits_buffer_alloc(nvidia_stack_t *sp, + gpuDeviceHandle device, + gpuAccessBitsBufferAlloc *accessBitsInfo) +{ + NV_STATUS rmStatus; + void* fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsAccessBitsBufAlloc(device, accessBitsInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_access_bits_buffer_free(nvidia_stack_t *sp, + gpuDeviceHandle device, + gpuAccessBitsBufferAlloc *accessBitsInfo) +{ + NV_STATUS rmStatus; + void* fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsAccessBitsBufFree(device, accessBitsInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_access_bits_dump(nvidia_stack_t *sp, + gpuDeviceHandle device, + gpuAccessBitsBufferAlloc *accessBitsInfo, + UVM_ACCESS_BITS_DUMP_MODE mode) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsAccessBitsDump(device, accessBitsInfo, mode); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_init_access_cntr_info(nvidia_stack_t *sp, + gpuDeviceHandle device, + gpuAccessCntrInfo *accessCntrInfo, + NvU32 accessCntrIndex) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsInitAccessCntrInfo(device, accessCntrInfo, accessCntrIndex); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_destroy_access_cntr_info(nvidia_stack_t *sp, + gpuDeviceHandle device, + gpuAccessCntrInfo *accessCntrInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsDestroyAccessCntrInfo(device, accessCntrInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_enable_access_cntr(nvidia_stack_t *sp, + gpuDeviceHandle device, + gpuAccessCntrInfo *accessCntrInfo, + gpuAccessCntrConfig *accessCntrConfig) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsEnableAccessCntr(device, accessCntrInfo, accessCntrConfig); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_disable_access_cntr(nvidia_stack_t *sp, + gpuDeviceHandle device, + gpuAccessCntrInfo *accessCntrInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsDisableAccessCntr(device, accessCntrInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_get_nvlink_info (nvidia_stack_t *sp, + gpuDeviceHandle device, + gpuNvlinkInfo *nvlinkInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsGetNvlinkInfo(device, nvlinkInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL +rm_gpu_ops_p2p_object_create(nvidia_stack_t *sp, + gpuDeviceHandle device1, + gpuDeviceHandle device2, + NvHandle *hP2pObject) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp, fp); + rmStatus = nvGpuOpsP2pObjectCreate(device1, device2, hP2pObject); + NV_EXIT_RM_RUNTIME(sp, fp); + return rmStatus; +} + +void NV_API_CALL +rm_gpu_ops_p2p_object_destroy(nvidia_stack_t *sp, + nvgpuSessionHandle_t session, + NvHandle hP2pObject) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp, fp); + nvGpuOpsP2pObjectDestroy(session, hP2pObject); + NV_EXIT_RM_RUNTIME(sp, fp); +} + +NV_STATUS NV_API_CALL +rm_gpu_ops_get_external_alloc_ptes(nvidia_stack_t* sp, + nvgpuAddressSpaceHandle_t vaSpace, + NvHandle hDupedMemory, + NvU64 offset, + NvU64 size, + nvgpuExternalMappingInfo_t gpuExternalMappingInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp, fp); + rmStatus = nvGpuOpsGetExternalAllocPtes(vaSpace, hDupedMemory, offset, size, + gpuExternalMappingInfo); + NV_EXIT_RM_RUNTIME(sp, fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL +rm_gpu_ops_get_external_alloc_phys_addrs(nvidia_stack_t* sp, + nvgpuAddressSpaceHandle_t vaSpace, + NvHandle hDupedMemory, + NvU64 offset, + NvU64 size, + nvgpuExternalPhysAddrInfo_t gpuExternalPhysAddrsInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp, fp); + rmStatus = nvGpuOpsGetExternalAllocPhysAddrs(vaSpace, hDupedMemory, offset, size, + gpuExternalPhysAddrsInfo); + NV_EXIT_RM_RUNTIME(sp, fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL +rm_gpu_ops_retain_channel(nvidia_stack_t* sp, + nvgpuAddressSpaceHandle_t vaSpace, + NvHandle hClient, + NvHandle hChannel, + void **retainedChannel, + nvgpuChannelInstanceInfo_t channelInstanceInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp, fp); + rmStatus = nvGpuOpsRetainChannel(vaSpace, hClient, hChannel, + (gpuRetainedChannel **)retainedChannel, + channelInstanceInfo); + NV_EXIT_RM_RUNTIME(sp, fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL +rm_gpu_ops_bind_channel_resources(nvidia_stack_t* sp, + void *retainedChannel, + nvgpuChannelResourceBindParams_t channelResourceBindParams) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp, fp); + rmStatus = nvGpuOpsBindChannelResources(retainedChannel, + channelResourceBindParams); + NV_EXIT_RM_RUNTIME(sp, fp); + return rmStatus; +} + +void NV_API_CALL +rm_gpu_ops_release_channel(nvidia_stack_t *sp, void *retainedChannel) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp, fp); + nvGpuOpsReleaseChannel(retainedChannel); + NV_EXIT_RM_RUNTIME(sp, fp); +} + +void NV_API_CALL +rm_gpu_ops_stop_channel(nvidia_stack_t * sp, + void *retainedChannel, + NvBool bImmediate) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + nvGpuOpsStopChannel(retainedChannel, bImmediate); + NV_EXIT_RM_RUNTIME(sp, fp); +} + +NV_STATUS NV_API_CALL +rm_gpu_ops_get_channel_resource_ptes(nvidia_stack_t* sp, + nvgpuAddressSpaceHandle_t vaSpace, + NvP64 resourceDescriptor, + NvU64 offset, + NvU64 size, + nvgpuExternalMappingInfo_t gpuExternalMappingInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp, fp); + rmStatus = nvGpuOpsGetChannelResourcePtes(vaSpace, resourceDescriptor, + offset, size, + gpuExternalMappingInfo); + NV_EXIT_RM_RUNTIME(sp, fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL +rm_gpu_ops_report_non_replayable_fault(nvidia_stack_t *sp, + nvgpuDeviceHandle_t device, + const void *pFaultPacket) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsReportNonReplayableFault(device, pFaultPacket); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL +rm_gpu_ops_paging_channel_allocate(nvidia_stack_t *sp, + gpuDeviceHandle device, + const gpuPagingChannelAllocParams *allocParams, + gpuPagingChannelHandle *channel, + gpuPagingChannelInfo *channelInfo) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsPagingChannelAllocate(device, allocParams, channel, + channelInfo); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +void NV_API_CALL +rm_gpu_ops_paging_channel_destroy(nvidia_stack_t *sp, + gpuPagingChannelHandle channel) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + nvGpuOpsPagingChannelDestroy(channel); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NV_STATUS NV_API_CALL +rm_gpu_ops_paging_channels_map(nvidia_stack_t *sp, + gpuAddressSpaceHandle srcVaSpace, + NvU64 srcAddress, + gpuDeviceHandle device, + NvU64 *dstAddress) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsPagingChannelsMap(srcVaSpace, srcAddress, device, dstAddress); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +void NV_API_CALL +rm_gpu_ops_paging_channels_unmap(nvidia_stack_t *sp, + gpuAddressSpaceHandle srcVaSpace, + NvU64 srcAddress, + gpuDeviceHandle device) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + nvGpuOpsPagingChannelsUnmap(srcVaSpace, srcAddress, device); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NV_STATUS NV_API_CALL +rm_gpu_ops_paging_channel_push_stream(nvidia_stack_t *sp, + gpuPagingChannelHandle channel, + char *methodStream, + NvU32 methodStreamSize) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsPagingChannelPushStream(channel, methodStream, methodStreamSize); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +void NV_API_CALL +rm_gpu_ops_report_fatal_error(nvidia_stack_t *sp, + NV_STATUS error) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + nvGpuOpsReportFatalError(error); + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_context_init(nvidia_stack_t *sp, + struct ccslContext_t **ctx, + gpuChannelHandle channel) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslContextInit(ctx, channel); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_context_clear(nvidia_stack_t *sp, + struct ccslContext_t *ctx) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslContextClear(ctx); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_rotate_key(nvidia_stack_t *sp, + UvmCslContext *contextList[], + NvU32 contextListCount) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslRotateKey(contextList, contextListCount); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_rotate_iv(nvidia_stack_t *sp, + struct ccslContext_t *ctx, + NvU8 direction) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslRotateIv(ctx, direction); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_encrypt_with_iv(nvidia_stack_t *sp, + struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *encryptIv, + NvU8 *outputBuffer, + NvU8 *authTagData) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslEncryptWithIv(ctx, bufferSize, inputBuffer, encryptIv, outputBuffer, authTagData); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_encrypt(nvidia_stack_t *sp, + struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *outputBuffer, + NvU8 *authTagData) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslEncrypt(ctx, bufferSize, inputBuffer, outputBuffer, authTagData); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_decrypt(nvidia_stack_t *sp, + struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 const *decryptIv, + NvU32 keyRotationId, + NvU8 *outputBuffer, + NvU8 const *addAuthData, + NvU32 addAuthDataSize, + NvU8 const *authTagData) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslDecrypt(ctx, bufferSize, inputBuffer, decryptIv, keyRotationId, outputBuffer, + addAuthData, addAuthDataSize, authTagData); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_sign(nvidia_stack_t *sp, + struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *authTagData) + +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslSign(ctx, bufferSize, inputBuffer, authTagData); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_query_message_pool(nvidia_stack_t *sp, + struct ccslContext_t *ctx, + NvU8 direction, + NvU64 *messageNum) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsQueryMessagePool(ctx, direction, messageNum); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_increment_iv(nvidia_stack_t *sp, + struct ccslContext_t *ctx, + NvU8 direction, + NvU64 increment, + NvU8 *iv) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsIncrementIv(ctx, direction, increment, iv); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_log_encryption(nvidia_stack_t *sp, + struct ccslContext_t *ctx, + NvU8 direction, + NvU32 bufferSize) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsLogEncryption(ctx, direction, bufferSize); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} diff --git a/userspace/sdks/nv570/nvalloc/unix/src/rmobjexportimport.c b/userspace/sdks/nv570/nvalloc/unix/src/rmobjexportimport.c new file mode 100644 index 0000000..558f5fd --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/src/rmobjexportimport.c @@ -0,0 +1,650 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file + * + * @brief Provides RmExportObject, RmImportObject, RmFreeObjExportHandle and + * RmGetExportObjectInfo interfaces : + * + * These interfaces allow rm clients to export their objects into + * a unique RmObjExportHandle which another rm client could + * import, even if the source rm client gets destroyed. + * + * RM's device instance may get destroyed asynchronously, in which + * case exported objects residing on that device instance also get + * destroyed. This means it is not possible to import it back, but the + * RmObjExportHandle into which the object had been exported still + * remains valid but no other object could get it. + * + * There are not init/fini routines, it is the responsibility of the + * rest of RM's eco-system to make sure that all RmObjExportHandles get + * freed during driver unload. + * + * The api lock is expected to be held before calling into + * rmobjexportimport.c; do not hold gpu or any other lock. + */ + +#include "rmobjexportimport.h" +#include "nvlimits.h" +#include "gpu/device/device.h" +#include "gpu/mig_mgr/kernel_mig_manager.h" +#include "gpu/mig_mgr/gpu_instance_subscription.h" + +#include "containers/map.h" +#include "rmapi/rmapi.h" +#include "rmapi/rs_utils.h" + +#include "class/cl0080.h" +#include "class/cl2080.h" +#include +#include + +// +// A reference to an RmObjExportHandle +// generated by function RmGenerateObjExportHandle(). +// +MAKE_MAP(RmObjExportHandleMap, NvU8); + +// +// Memory allocator +// +PORT_MEM_ALLOCATOR *pMemAllocator; + +// +// Map RmObjExportHandle -> RmObjExportHandleRef +// +RmObjExportHandleMap objExportHandleMap; + +// +// Rm client to use to dup an object exported to RmObjExportHandle. The minimal +// requirement for duping is to have a device object allocated. This rm client +// is simply like any other external rm client and has no any special handling. +// +// We keep this rm client just like any other external rm client: if +// gpu(s)/device gets powered-down/uninitialized, rm objects allocated by +// external rm clients and located on that gpu(s)/device gets freed (the +// os-layer does that). In that way, code in this file doesn't need to worry +// about freeing exported objects located on that gpu(s)/device. +// +NvHandle hObjExportRmClient; + +// +// Tracker for device and subdevice handles. For now only one subdevice +// (instance 0) is supported per device. +// +typedef struct +{ + NvHandle hRmDevice; + NvHandle hRmSubDevice; + NvHandle hGpuInstSub; +} RmObjExportDevice; +MAKE_MAP(RmObjExportDeviceMap, RmObjExportDevice); + +RmObjExportDeviceMap objExportDeviceMap; + +// +// Usage reference counter for static object in this file like rm client used to +// dup an exported object, memory allocator, map etc. +// +NvU64 objExportImportRefCount; + +// +// Static functions for internal use to code in this file. +// +static NV_STATUS RmRefObjExportImport (void); +static void RmUnrefObjExportImport (void); + +static RmObjExportHandle RmGenerateObjExportHandle (void); +static NV_STATUS RmUnrefObjExportHandle (RmObjExportHandle hObject); + +// +// Free the RmObjExportHandle. +// +static NV_STATUS RmUnrefObjExportHandle(RmObjExportHandle hObject) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); + + void *pHandleRef = mapFind(&objExportHandleMap, hObject); + if (pHandleRef == NULL) + { + return NV_ERR_OBJECT_NOT_FOUND; + } + + if (pRmApi->Free(pRmApi, + hObjExportRmClient, + (NvHandle)mapKey(&objExportHandleMap, pHandleRef)) != NV_OK) + { + NV_PRINTF(LEVEL_WARNING, + "Exported object trying to free was zombie in %s\n", + __FUNCTION__); + } + + mapRemove(&objExportHandleMap, pHandleRef); + + return NV_OK; +} + +// +// Generate unique RmObjExportHandle. +// +static RmObjExportHandle RmGenerateObjExportHandle(void) +{ + // + // The object export handle belongs to range of 0 to + // (MAX_OBJ_EXPORT_HANDLES - 1). + // + // Handle 0 is considered as invalid object handle, this function generates + // handle from range of 1 to (MAX_OBJ_EXPORT_HANDLES - 1). + // + #define MAX_OBJ_EXPORT_HANDLES 0x80000 + + static NvHandle hObjExportHandleNext = 1; + + RmObjExportHandle hStartHandle = hObjExportHandleNext; + RmObjExportHandle hObject = 0; + + do + { + void *pHandleRef; + + hObject = hObjExportHandleNext++; + /* Reset hObjExportHandleNext to next valid handle */ + if (hObjExportHandleNext == MAX_OBJ_EXPORT_HANDLES) { + hObjExportHandleNext = 1; + } + + pHandleRef = mapFind(&objExportHandleMap, hObject); + + if (hObject != hObjExportRmClient && pHandleRef == NULL) + { + break; + } + else + { + hObject = 0; + } + + } while(hObjExportHandleNext != hStartHandle); + + if (hObject != 0) + { + void *pHandleRef = mapInsertNew(&objExportHandleMap, hObject); + + if (pHandleRef == NULL) + { + hObject = 0; + } + } + + return hObject; +} + +// +// Validate that the given hObject is not one of our internally used handles. +// +// Note that mapFind(&objExportHandleMap, hObject) could still fail; that is the +// caller's responsibility. +// +static NvBool RmValidateHandleAgainstInternalHandles(RmObjExportHandle hObject) +{ + RmObjExportDeviceMapIter iter; + + // + // No external RmObjExportHandle could be valid if hObjExportRmClient has + // not been allocated yet, or if it is equal to any of the handles used + // internally by code in this file. + // + if (objExportImportRefCount == 0 || hObjExportRmClient == 0 || + hObject == hObjExportRmClient) + { + return NV_FALSE; + } + + iter = mapIterAll(&objExportDeviceMap); + while (mapIterNext(&iter)) + { + RmObjExportDevice *pRmObjExportDevice = iter.pValue; + + if (pRmObjExportDevice->hRmDevice != 0 && + (hObject == pRmObjExportDevice->hRmDevice || + hObject == pRmObjExportDevice->hRmSubDevice || + hObject == pRmObjExportDevice->hGpuInstSub)) + { + return NV_FALSE; + } + } + + return NV_TRUE; +} + +// +// Increment reference count of static objects internally +// used by code in this file. +// +static NV_STATUS RmRefObjExportImport(void) +{ + NV_STATUS rmStatus = NV_OK; + RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); + + if ((objExportImportRefCount++) != 0) + { + NV_ASSERT(hObjExportRmClient != 0); + NV_ASSERT(pMemAllocator != NULL); + return NV_OK; + } + + rmStatus = pRmApi->AllocWithHandle(pRmApi, + NV01_NULL_OBJECT, + NV01_NULL_OBJECT, + NV01_NULL_OBJECT, + NV01_ROOT, + &hObjExportRmClient, + sizeof(hObjExportRmClient)); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to alloc root in %s\n", __FUNCTION__); + goto failed; + } + + pMemAllocator = portMemAllocatorCreateNonPaged(); + + if (pMemAllocator == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to alloc memory allocator in %s\n", + __FUNCTION__); + goto failed; + } + + mapInit(&objExportHandleMap, pMemAllocator); + mapInit(&objExportDeviceMap, pMemAllocator); + + return NV_OK; + +failed: + + RmUnrefObjExportImport(); + + return rmStatus; +} + +// +// Decrement reference count of static objects internally used by code in this +// file, and free them if reference count reaches to zero. +// +static void RmUnrefObjExportImport(void) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); + + if ((--objExportImportRefCount) != 0) + { + return; + } + + if (pMemAllocator != NULL) + { + mapDestroy(&objExportDeviceMap); + mapDestroy(&objExportHandleMap); + + portMemAllocatorRelease(pMemAllocator); + pMemAllocator = NULL; + } + + if (hObjExportRmClient != 0) + { + NV_STATUS rmStatus = pRmApi->Free(pRmApi, + hObjExportRmClient, + hObjExportRmClient); + + NV_ASSERT(rmStatus == NV_OK); + hObjExportRmClient = 0; + } +} + +NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject, + RmObjExportHandle *pDstObject, NvU32 *pDeviceInstance) +{ + RmObjExportHandle hDstObject; + NvU32 deviceInstance = NV_MAX_DEVICES; + NvBool bClientAsDstParent = NV_FALSE; + NV_STATUS status; + RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); + MIG_INSTANCE_REF ref = kmigmgrMakeNoMIGReference(); + NvU64 deviceMapIdx = 0; + RmObjExportDevice *pObjExportDevice = NULL; + RsResourceRef *pSrcResourceRef; + RsResourceRef *pDeviceRef; + + if (pDstObject == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // + // Find the device instance on which the rm object exists. + // + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + serverutilGetResourceRef(hSrcClient, hSrcObject, &pSrcResourceRef)); + + status = refFindAncestorOfType(pSrcResourceRef, classId(Device), &pDeviceRef); + if (status == NV_OK) + { + Device *pDevice = dynamicCast(pDeviceRef->pResource, Device); + OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); + NvU64 swizzId = KMIGMGR_MAX_GPU_SWIZZID; + + if (IS_MIG_IN_USE(pGpu)) + { + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + + status = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &ref); + if (status == NV_OK) + { + swizzId = ref.pKernelMIGGpuInstance->swizzId; + } + } + + deviceMapIdx = pDevice->deviceInst | (swizzId << 32); + deviceInstance = pDevice->deviceInst; + pObjExportDevice = mapFind(&objExportDeviceMap, deviceMapIdx); + } + else + { + bClientAsDstParent = NV_TRUE; + } + + status = RmRefObjExportImport(); + + if (status != NV_OK) + { + return status; + } + + if (!bClientAsDstParent && + ((pObjExportDevice == NULL) || + serverutilValidateNewResourceHandle(hObjExportRmClient, + pObjExportDevice->hRmDevice))) + { + // + // Device object has not been created or it got destroyed in the + // teardown path of device instance destruction; allocate a fresh device + // object. + // + NV0080_ALLOC_PARAMETERS params; + NV2080_ALLOC_PARAMETERS subdevParams; + + if (pObjExportDevice == NULL) + { + pObjExportDevice = mapInsertNew(&objExportDeviceMap, deviceMapIdx); + + pObjExportDevice->hRmDevice = RmGenerateObjExportHandle(); + pObjExportDevice->hRmSubDevice = RmGenerateObjExportHandle(); + pObjExportDevice->hGpuInstSub = NV01_NULL_OBJECT; + + if (pObjExportDevice->hRmDevice == 0 || + pObjExportDevice->hRmSubDevice == 0) + { + NV_PRINTF(LEVEL_ERROR, "Failed to allocate object handles in %s\n", + __FUNCTION__); + + mapRemove(&objExportDeviceMap, pObjExportDevice); + + status = NV_ERR_NO_MEMORY; + goto done; + } + } + + portMemSet(¶ms, 0, sizeof(NV0080_ALLOC_PARAMETERS)); + + params.deviceId = deviceInstance; + params.hClientShare = hObjExportRmClient; + + status = pRmApi->AllocWithHandle(pRmApi, + hObjExportRmClient, + hObjExportRmClient, + pObjExportDevice->hRmDevice, + NV01_DEVICE_0, + ¶ms, + sizeof(params)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to alloc device in %s\n", + __FUNCTION__); + goto done; + } + + portMemSet(&subdevParams, 0, sizeof(NV2080_ALLOC_PARAMETERS)); + + subdevParams.subDeviceId = 0; + + status = pRmApi->AllocWithHandle(pRmApi, + hObjExportRmClient, + pObjExportDevice->hRmDevice, + pObjExportDevice->hRmSubDevice, + NV20_SUBDEVICE_0, + &subdevParams, + sizeof(subdevParams)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to alloc subdevice in %s\n", + __FUNCTION__); + + (void) pRmApi->Free(pRmApi, hObjExportRmClient, + pObjExportDevice->hRmDevice); + goto done; + } + + // Allocate MIG subscription, if needed + if ((ref.pKernelMIGGpuInstance != NULL) && + (ref.pKernelMIGGpuInstance->swizzId < KMIGMGR_MAX_GPU_SWIZZID)) + { + NVC637_ALLOCATION_PARAMETERS giSubAllocParams; + + portMemSet(&giSubAllocParams, 0, sizeof(giSubAllocParams)); + giSubAllocParams.swizzId = ref.pKernelMIGGpuInstance->swizzId; + + pObjExportDevice->hGpuInstSub = RmGenerateObjExportHandle(); + + status = pRmApi->AllocWithHandle(pRmApi, + hObjExportRmClient, + pObjExportDevice->hRmSubDevice, + pObjExportDevice->hGpuInstSub, + AMPERE_SMC_PARTITION_REF, + &giSubAllocParams, + sizeof(giSubAllocParams)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to alloc gpu instance subscription in %s\n", + __FUNCTION__); + + (void) pRmApi->Free(pRmApi, hObjExportRmClient, + pObjExportDevice->hRmDevice); + goto done; + } + } + } + + hDstObject = RmGenerateObjExportHandle(); + + if (hDstObject == 0) + { + NV_PRINTF(LEVEL_ERROR, "Failed to allocate object handle in %s\n", + __FUNCTION__); + status = NV_ERR_NO_MEMORY; + goto done; + } + + // If duping under device handle fails, try subdevice handle. + status = pRmApi->DupObject(pRmApi, + hObjExportRmClient, + bClientAsDstParent ? hObjExportRmClient : + pObjExportDevice->hRmDevice, + &hDstObject, + hSrcClient, + hSrcObject, + 0 /* flags */); + if (status != NV_OK) + { + if (!bClientAsDstParent && (status == NV_ERR_INVALID_OBJECT_PARENT)) + { + NV_PRINTF(LEVEL_INFO, + "pRmApi->DupObject(Dev, failed due to invalid parent in %s." + " Now attempting DupObject with Subdev handle.\n", + __FUNCTION__); + + status = pRmApi->DupObject(pRmApi, + hObjExportRmClient, + pObjExportDevice->hRmSubDevice, + &hDstObject, + hSrcClient, + hSrcObject, + 0 /* flags */); + if (status != NV_OK) + { + RmUnrefObjExportHandle(hDstObject); + + NV_PRINTF(LEVEL_ERROR, + "pRmApi->DupObject(Subdev, failed with error code 0x%x in %s\n", + status, __FUNCTION__); + goto done; + } + } + else + { + RmUnrefObjExportHandle(hDstObject); + + NV_PRINTF(LEVEL_ERROR, + "pRmApi->DupObject(Dev, failed with error code 0x%x in %s\n", + status, __FUNCTION__); + goto done; + } + } + + if (pDeviceInstance != NULL) + { + *pDeviceInstance = deviceInstance; + } + + *pDstObject = hDstObject; + +done: + if (status != NV_OK) + { + RmUnrefObjExportImport(); + } + + return status; +} + +void RmFreeObjExportHandle(RmObjExportHandle hObject) +{ + if (!RmValidateHandleAgainstInternalHandles(hObject)) + { + NV_PRINTF(LEVEL_ERROR, "Invalid handle to exported object in %s\n", + __FUNCTION__); + return; + } + + RmUnrefObjExportHandle(hObject); + + RmUnrefObjExportImport(); +} + +NV_STATUS RmImportObject(NvHandle hDstClient, NvHandle hDstParent, + NvHandle *phDstObject, RmObjExportHandle hSrcObject, + NvU8 *pObjectType) +{ + NV_STATUS status; + NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS params; + RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); + + if (!RmValidateHandleAgainstInternalHandles(hSrcObject)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (mapFind(&objExportHandleMap, hSrcObject) == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (pObjectType != NULL) + { + params.hObject = hSrcObject; + // + // rmApiGetEffectiveAddrSpace expect mapping flags to be set as DIRECT for + // GPU cacheable Sysmem for Pre-Ampere chips. We are not doing any mapping + // here, so passing this as workaround to get the expected address space. + // + params.mapFlags = FLD_SET_DRF(OS33, _FLAGS, _MAPPING, _DIRECT, 0); + params.addrSpaceType = \ + NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_INVALID; + + status = pRmApi->Control(pRmApi, hObjExportRmClient, hObjExportRmClient, + NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE, + ¶ms, sizeof(params)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "GET_ADDR_SPACE_TYPE failed with error code 0x%x in %s\n", + status, __FUNCTION__); + return status; + } + + switch (params.addrSpaceType) + { + case NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_SYSMEM: + *pObjectType = NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_SYSMEM; + break; + case NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM: + *pObjectType = NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_VIDMEM; + break; + case NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC: + *pObjectType = NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC; + break; +#if defined(NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC_MC) && \ + defined(NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC_MC) + case NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC_MC: + *pObjectType = NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC_MC; + break; +#endif + default: + NV_ASSERT_OK_OR_RETURN(NV_ERR_INVALID_ARGUMENT); + } + } + + status = pRmApi->DupObject(pRmApi, hDstClient, hDstParent, phDstObject, + hObjExportRmClient, hSrcObject, + 0 /* flags */); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "pRmApi->DupObject(pRmApi, failed with error code 0x%x in %s\n", + status, __FUNCTION__); + return status; + } + + return NV_OK; +} diff --git a/userspace/sdks/nv570/nvalloc/unix/src/subdevice_ctrl_os_unix.c b/userspace/sdks/nv570/nvalloc/unix/src/subdevice_ctrl_os_unix.c new file mode 100644 index 0000000..fdbdb6b --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/src/subdevice_ctrl_os_unix.c @@ -0,0 +1,97 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include // NV device driver interface +#include +#include +#include +#include +#include "gpu/gpu.h" +#include "gpu/gpu_resource.h" +#include "gpu/subdevice/subdevice.h" +#include +#include "gpu/mem_mgr/mem_desc.h" +#include "mem_mgr/mem.h" +#include +#include +#include "rmapi/rs_utils.h" +#include "rmapi/client_resource.h" +#include +#include +#include // NV01_EVENT +#include // NV01_MEMORY_SYSTEM +#include // G84_PERFBUFFER +#include +#include +#include +#include + +/*! + * @brief Implements the NV2080_CTRL_CMD_OS_UNIX_VIDMEM_PERSISTENCE_STATUS + * RmControl request. It will check if the GPU video memory will be + * persistent during system suspend/resume cycle. + * + * @param[in] pSubdevice + * @param[in,out] pParams + * + * @return + * NV_OK Success + */ +NV_STATUS +subdeviceCtrlCmdOsUnixVidmemPersistenceStatus_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + pParams->bVidmemPersistent = (nv->preserve_vidmem_allocations || nvp->s0ix_pm_enabled); + + return NV_OK; +} + +/*! + * @brief Implements the NV2080_CTRL_CMD_OS_UNIX_UPDATE_TGP_STATUS + * RmControl request. It sets restore TGP flag which is used + * to restore TGP limits when client is killed. + * + * @param[in] pSubdevice + * @param[in] pParams + * + * @return + * NV_OK Success + */ +NV_STATUS +subdeviceCtrlCmdOsUnixUpdateTgpStatus_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS *pParams +) +{ + pSubdevice->bUpdateTGP = pParams->bUpdateTGP; + + return NV_OK; +} diff --git a/userspace/sdks/nv570/nvalloc/unix/src/unix_console.c b/userspace/sdks/nv570/nvalloc/unix/src/unix_console.c new file mode 100644 index 0000000..28b597b --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/src/unix_console.c @@ -0,0 +1,412 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "vgpu/vgpu_events.h" + +static NV_STATUS +unixCallVideoBIOS +( + OBJGPU *pGpu, + NvU32 *eax, + NvU32 *ebx +) +{ + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + + if (NVCPU_IS_X86_64) + { + NvU32 eax_in = *eax; + NvU32 ebx_in = *ebx; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_UEFI)) + { + return NV_ERR_NOT_SUPPORTED; + } + + NV_PRINTF(LEVEL_INFO, "unixCallVideoBIOS: 0x%x 0x%x, vga_satus = %d\n", *eax, *ebx, NV_PRIMARY_VGA(NV_GET_NV_STATE(pGpu))); + + status = nv_vbios_call(pGpu, eax, ebx); + + // this was originally changed for nt in changelist 644223 + if (*eax != 0x4f) + { + NV_PRINTF(LEVEL_ERROR, + "int10h(%04x, %04x) vesa call failed! (%04x, %04x)\n", + eax_in, ebx_in, *eax, *ebx); + status = NV_ERR_GENERIC; + } + } + + return status; +} + +static void +RmSaveDisplayState +( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + NvBool use_vbios = NV_PRIMARY_VGA(nv) && RmGpuHasIOSpaceEnabled(nv); + NvU32 eax, ebx; + NV_STATUS status; + NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS preUnixConsoleParams = {0}; + NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS postUnixConsoleParams = {0}; + + if (IS_VIRTUAL(pGpu) || (pKernelDisplay == NULL) || nv->client_managed_console) + { + return; + } + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_UEFI)) + { + NV_PRINTF(LEVEL_INFO, "RM fallback doesn't support saving of efifb console\n"); + return; + } + + preUnixConsoleParams.bSave = NV_TRUE; + preUnixConsoleParams.bUseVbios = use_vbios; + + NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, pRmApi->Control(pRmApi, nv->rmapi.hClient, nv->rmapi.hSubDevice, + NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE, + &preUnixConsoleParams, sizeof(preUnixConsoleParams)), return); + + if (preUnixConsoleParams.bReturnEarly) + { + return; + } + + if (use_vbios) + { + // + // Attempt to identify the currently set VESA mode; assume + // vanilla VGA text if the VBIOS call fails. + // + eax = 0x4f03; + ebx = 0; + if (NV_OK == unixCallVideoBIOS(pGpu, &eax, &ebx)) + { + nvp->vga.vesaMode = (ebx & 0x3fff); + } + else + { + nvp->vga.vesaMode = 3; + } + } + + postUnixConsoleParams.bSave = NV_TRUE; + postUnixConsoleParams.bUseVbios = use_vbios; + + NV_CHECK_OK(status, LEVEL_ERROR, + pRmApi->Control(pRmApi, nv->rmapi.hClient,nv->rmapi.hSubDevice, + NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE, + &postUnixConsoleParams, sizeof(postUnixConsoleParams))); +} + +static void RmRestoreDisplayState +( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NvBool use_vbios = NV_PRIMARY_VGA(nv) && RmGpuHasIOSpaceEnabled(nv);; + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + NV_STATUS status; + NvU32 eax, ebx; + NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS preUnixConsoleParams = {0}; + NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS postUnixConsoleParams = {0}; + + // + // Since vGPU does all real hardware management in the host, + // there is nothing to do at this point in the guest OS. + // + if (IS_VIRTUAL(pGpu) || (pKernelDisplay == NULL) || nv->client_managed_console) + { + return; + } + + // + // Fix up DCB index VBIOS scratch registers. + // The strategies employed are: + // + // SBIOS/VBIOS: + // Clear the DCB index, and set the previous DCB index to the original + // value. This allows the VBIOS (during the int10h mode-set) to + // determine which display to enable, and to set the head-enabled bit + // as needed (see bugs #264873 and #944398). + // + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_UEFI)) + { + NV_PRINTF(LEVEL_INFO, "RM fallback doesn't support efifb console restore\n"); + return; + } + + preUnixConsoleParams.bUseVbios = use_vbios; + preUnixConsoleParams.bSave = NV_FALSE; + + NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, pRmApi->Control(pRmApi, nv->rmapi.hClient, + nv->rmapi.hSubDevice, + NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE, + &preUnixConsoleParams, sizeof(preUnixConsoleParams)), return); + + if (preUnixConsoleParams.bReturnEarly) + { + return; + } + + if (use_vbios) + { + eax = 0x4f02; + ebx = nvp->vga.vesaMode; + + if (NV_OK == unixCallVideoBIOS(pGpu, &eax, &ebx)) + { + postUnixConsoleParams.bVbiosCallSuccessful = NV_TRUE; + } + } + + postUnixConsoleParams.bSave = NV_FALSE; + postUnixConsoleParams.bUseVbios = use_vbios; + + NV_CHECK_OK(status, LEVEL_ERROR, + pRmApi->Control(pRmApi, nv->rmapi.hClient, nv->rmapi.hSubDevice, + NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE, + &postUnixConsoleParams, sizeof(postUnixConsoleParams))); +} + +static void +RmChangeResMode +( + OBJGPU *pGpu, + NvBool hires +) +{ + if (hires) + { + SLI_LOOP_START(SLI_LOOP_FLAGS_NONE) + + RmSaveDisplayState(pGpu); + + SLI_LOOP_END + } + else + { + SLI_LOOP_START(SLI_LOOP_FLAGS_NONE) + + RmRestoreDisplayState(pGpu); + // + // vGPU: + // + // Since vGPU does all real hardware management in the host, if we + // are in guest OS (where IS_VIRTUAL(pGpu) is true), do an RPC to + // the host to trigger switch from HIRES to (LORES)VGA. + // + if (IS_VIRTUAL(pGpu)) + { + NV_STATUS status = NV_OK; + NV_RM_RPC_SWITCH_TO_VGA(pGpu, status); + } + + SLI_LOOP_END + } +} + +NV_STATUS NV_API_CALL +rm_save_low_res_mode +( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + THREAD_STATE_NODE threadState; + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + RmSaveDisplayState(pGpu); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return NV_OK; +} + +NV_STATUS +deviceCtrlCmdOsUnixVTSwitch_IMPL +( + Device *pDevice, + NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + NvBool hires; + NvBool bChangeResMode = NV_TRUE; + + switch (pParams->cmd) + { + case NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_SAVE_VT_STATE: + hires = NV_TRUE; + break; + + case NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_RESTORE_VT_STATE: + hires = NV_FALSE; + break; + + case NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_CONSOLE_RESTORED: + bChangeResMode = NV_FALSE; + break; + + default: + return NV_ERR_INVALID_ARGUMENT; + } + + RmUpdateGc6ConsoleRefCount(nv, + pParams->cmd != NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_SAVE_VT_STATE); + + if (!bChangeResMode) + { + return NV_OK; + } + + if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_FB) == NV_OK) + { + RmChangeResMode(pGpu, hires); + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + else + { + NV_PRINTF(LEVEL_INFO,"%s: Failed to acquire GPU lock", __FUNCTION__); + } + return NV_OK; +} + +NV_STATUS deviceCtrlCmdOsUnixVTGetFBInfo_IMPL +( + Device *pDevice, + NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); + NvBool bContinue = NV_TRUE; + + if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_FB) == NV_OK) + { + // See if the console is on one of the subdevices of this device. + portMemSet(pParams, 0, sizeof(*pParams)); + + SLI_LOOP_START(SLI_LOOP_FLAGS_NONE) + + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + if ((memmgrGetReservedConsoleMemDesc(pGpu, pMemoryManager) != NULL) && bContinue) + { + NvU64 baseAddr, size; + NvU32 width, height, depth, pitch; + + // There should only be one. + NV_ASSERT(pParams->width == 0); + + pParams->subDeviceInstance = gpumgrGetSubDeviceInstanceFromGpu(pGpu); + + // Console is either mapped to BAR1 or BAR2 + 16 MB + nv_get_screen_info(nv, &baseAddr, &width, &height, &depth, + &pitch, &size); + + pParams->baseAddress = baseAddr; + pParams->size = size; + pParams->width = (NvU16)width; + pParams->height = (NvU16)height; + pParams->depth = (NvU16)depth; + pParams->pitch = (NvU16)pitch; + + if (baseAddr != 0) + { + bContinue = NV_FALSE; + } + } + + SLI_LOOP_END + + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + else + { + NV_PRINTF(LEVEL_INFO,"%s: Failed to acquire GPU lock", __FUNCTION__); + } + + return NV_OK; +} + + +void +dispdeviceFillVgaSavedDisplayState +( + OBJGPU *pGpu, + NvU64 vgaAddr, + NvU8 vgaMemType, + NvBool vgaValid, + NvU64 workspaceAddr, + NvU8 workspaceMemType, + NvBool workspaceValid, + NvBool baseValid, + NvBool workspaceBaseValid +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvBool use_vbios = NV_PRIMARY_VGA(nv) && RmGpuHasIOSpaceEnabled(nv); + + if (use_vbios) + { + nvp->vga.base.addr = vgaAddr; + nvp->vga.base.memTarget = vgaMemType; + nvp->vga.base.valid = vgaValid; + nvp->vga.baseValid = baseValid; + + nvp->vga.workspaceBase.addr = workspaceAddr; + nvp->vga.workspaceBase.memTarget = workspaceMemType; + nvp->vga.workspaceBase.valid = workspaceValid; + nvp->vga.workspaceBaseValid = workspaceBaseValid; + } +} + diff --git a/userspace/sdks/nv570/nvalloc/unix/src/unix_intr.c b/userspace/sdks/nv570/nvalloc/unix/src/unix_intr.c new file mode 100644 index 0000000..aef36ab --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/src/unix_intr.c @@ -0,0 +1,1050 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "kernel/gpu/intr/intr.h" +#include "gpu/bif/kernel_bif.h" +#include "gpu/mmu/kern_gmmu.h" +#include "gpu/disp/kern_disp.h" +#include "gpu/disp/head/kernel_head.h" +#include + +#include "platform/sli/sli.h" + +// +// Service Interrupts that are not Masked when using +// INTR_USE_INTR_MASK_FOR_LOCKING +// Note that everything done here is without holding the GPUs Lock. +// Returning NV_OK means an interrupt has been serviced +// +static NV_STATUS _osIsrIntrMask_GpusUnlocked(OBJGPU *pGpu, THREAD_STATE_NODE *pThreadState) +{ + NV_STATUS rmStatus = NV_ERR_NO_INTR_PENDING; + Intr *pIntr = GPU_GET_INTR(pGpu); + MC_ENGINE_BITVECTOR intrPending, intrEngMask; + NvU32 vblankIntrServicedHeadMask = 0; + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + NvBool bFailedLockAcquire = NV_FALSE; + + if (gpuIsGpuFullPower(pGpu) == NV_FALSE) + { + return rmStatus; + } + + intrGetPendingLowLatencyHwDisplayIntr_HAL(pGpu, pIntr, &intrPending, pThreadState); + + // Only disp interrupt remains in INTR_MASK + if ((pKernelDisplay != NULL) && + (( pKernelDisplay->getProperty(pKernelDisplay, PDB_PROP_KDISP_HAS_SEPARATE_LOW_LATENCY_LINE) && bitVectorTest(&intrPending, MC_ENGINE_IDX_DISP_LOW)) || + (!pKernelDisplay->getProperty(pKernelDisplay, PDB_PROP_KDISP_HAS_SEPARATE_LOW_LATENCY_LINE) && bitVectorTest(&intrPending, MC_ENGINE_IDX_DISP)))) + { + if (kdispAcquireLowLatencyLockConditional(&pKernelDisplay->lowLatencyLock)) + { + + if (pKernelDisplay->getProperty(pKernelDisplay, PDB_PROP_KDISP_AGGRESSIVE_VBLANK_HANDLING)) + { + NV_ASSERT_OK( + kdispOptimizePerFrameOsCallbacks(pGpu, pKernelDisplay, NV_TRUE, + pThreadState, + &vblankIntrServicedHeadMask, + &intrPending)); + + // + // Need to setup deferred vblank handling for once the + // GPUs Lock is released since we cleared vblank intrs. + // + if (vblankIntrServicedHeadMask) + { + vblankIntrServicedHeadMask |= kdispGetDeferredVblankHeadMask(pKernelDisplay); + kdispSetDeferredVblankHeadMask(pKernelDisplay, vblankIntrServicedHeadMask); + } + } + else + { + kdispServiceLowLatencyIntrs_HAL(pGpu, pKernelDisplay, 0, + (VBLANK_STATE_PROCESS_LOW_LATENCY | + VBLANK_STATE_PROCESS_CALLED_FROM_ISR), + pThreadState, + &vblankIntrServicedHeadMask, + &intrPending); + } + + kdispReleaseLowLatencyLock(&pKernelDisplay->lowLatencyLock); + } + else + { + // + // If we lose this, then another thread is already servicing the low latency interrupts. + // Claim the interrupt, but go through the below disable code so that we don't immediately + // cause another interrupt indefinitely which could starve the other thread that already + // has the lock + // + rmStatus = NV_OK; + bFailedLockAcquire = NV_TRUE; + } + + // + // Bug 4512542: The check for INTR_MASK is currently redundant since it's + // already checked outside this function, but we would like to unconditionally + // call this function if we can service the vblank first. + // + if (pIntr->getProperty(pIntr, PDB_PROP_INTR_USE_INTR_MASK_FOR_LOCKING)) + { + // + // If an unmasked intr is still pending after the above, that means a + // intr other than the vblank, so we'll MSK this off + // for now and handle once the GPUs Lock is released. + // + intrGetPendingLowLatencyHwDisplayIntr_HAL(pGpu, pIntr, &intrPending, pThreadState); + + // + // Only disp interrupt remains in INTR_MASK + // Don't re-mask it if we have an entirely separate interrupt line, unless we have lost the race above. + // + if (( pKernelDisplay->getProperty(pKernelDisplay, PDB_PROP_KDISP_HAS_SEPARATE_LOW_LATENCY_LINE) && bitVectorTest(&intrPending, MC_ENGINE_IDX_DISP_LOW) && bFailedLockAcquire) || + (!pKernelDisplay->getProperty(pKernelDisplay, PDB_PROP_KDISP_HAS_SEPARATE_LOW_LATENCY_LINE) && bitVectorTest(&intrPending, MC_ENGINE_IDX_DISP))) + { + NvU32 intrMaskFlags; + NvU64 oldIrql; + + oldIrql = rmIntrMaskLockAcquire(pGpu); + + // Skip the IntrMask update if told to by another thread. + intrMaskFlags = intrGetIntrMaskFlags(pIntr); + if ((intrMaskFlags & INTR_MASK_FLAGS_ISR_SKIP_MASK_UPDATE) == 0) + { + if (pIntr->getProperty(pIntr, PDB_PROP_INTR_USE_INTR_MASK_FOR_LOCKING)) + { + intrGetIntrMask_HAL(pGpu, pIntr, &intrEngMask, pThreadState); + + // Only disp interrupt remains in INTR_MASK + bitVectorClr(&intrEngMask, MC_ENGINE_IDX_DISP); + + if (pIntr->getProperty(pIntr, PDB_PROP_INTR_USE_TOP_EN_FOR_VBLANK_HANDLING)) + { + intrSetDisplayInterruptEnable_HAL(pGpu, pIntr, NV_FALSE, pThreadState); + } + else + { + intrSetIntrMask_HAL(pGpu, pIntr, &intrEngMask, pThreadState); + } + } + } + + rmIntrMaskLockRelease(pGpu, oldIrql); + } + } + + if (vblankIntrServicedHeadMask) + { + rmStatus = NV_OK; + } + } + + return rmStatus; +} + +static NvBool osInterruptPending( + OBJGPU *pGpu, + NvBool *serviced, + THREAD_STATE_NODE *pThreadState +) +{ + KernelDisplay *pKernelDisplay; + NvBool pending, sema_release; + THREAD_STATE_NODE threadState; + Intr *pIntr = NULL; + MC_ENGINE_BITVECTOR intr0Pending; + MC_ENGINE_BITVECTOR intr1Pending; + + *serviced = NV_FALSE; + pending = NV_FALSE; + sema_release = NV_TRUE; + NvU8 stackAllocator[TLS_ISR_ALLOCATOR_SIZE]; // ISR allocations come from this buffer + PORT_MEM_ALLOCATOR *pIsrAllocator; + + // + // GPU interrupt servicing ("top half") + // + // Top-level processing of GPU interrupts is performed using the + // steps below; although the code is straight forward, there + // are a few points to be aware of: + // + // 1) The GPUs lock is acquired for two reasons: to allow + // looping over GPUs atomically in SLI and to sanity + // check the PCI configuration space of any initialized + // GPUs. If the acquisition fails, the early return + // is acceptable since GPU interrupts are disabled while + // the lock is held; note that returning success + // in this case could interfere with the processing + // of third-party device interrupts if the IRQ is shared. + // Due to the above, some interrupts may be reported as + // unhandled if invocations of the ISR registered with + // the kernel are not serialized. This is bad, but + // ignored by currently supported kernels, provided most + // interrupts are handled. + // + // 2) Since acquisition of the lock disables interrupts + // on all initialized GPUs, NV_PMC_INTR_EN_0 can not be + // relied up on to determine whether interrupts are + // expected from a given GPU. The code below is therefore + // forced to rely on software state. NV_PMC_INTR_EN_0 + // is read only as a sanity check to guard against + // invalid GPU state (lack of PCI memory access, etc.). + // + // 3) High priority interrupts (VBLANK, etc.), are serviced in + // this function, service of all other interrupts is + // deferred until a bottom half. If a bottom half needs + // to be scheduled, release of the GPUs lock is + // likewise deferred until completion of the bottom half. + // + // 4) To reduce the risk of starvation, an effort is made to + // consolidate processing of interrupts pending on + // all GPUs sharing a given IRQ. + // + // 5) Care is taken to ensure that the consolidated interrupt + // processing is performed in the context of a GPU + // that has interrupts pending. Else if additional ISR + // processing via a bottom-half is required, this + // bottom-half ISR might race against the GPU's shut-down + // path. + // + + pIsrAllocator = portMemAllocatorCreateOnExistingBlock(stackAllocator, sizeof(stackAllocator)); + tlsIsrInit(pIsrAllocator); + + // + // Also check if we need to acquire the GPU lock at all and get critical interrupts + // This should not violate (1) from above since we are not servicing the GPUs in SLI, + // only checking their state. + // + // To do so, two steps are required: + // Step 1: Check if we can service nonstall interrupts outside the GPUs lock. Otherwise + // we have to acquire the GPUs lock to service the nonstall interrupts anyway, and we + // can't get around acquiring the GPUs lock. + // + // Step 2 is inline below + // + NvBool bIsAnyStallIntrPending = NV_TRUE; + NvBool bIsAnyBottomHalfStallPending = NV_FALSE; + NvU32 isDispPendingPerGpu = 0, isDispLowLatencyPendingPerGpu = 0; + NvU32 isTmrPendingPerGpu = 0; + + { + threadStateInitISRLockless(&threadState, pGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS); + bIsAnyStallIntrPending = NV_FALSE; + + { + pIntr = GPU_GET_INTR(pGpu); + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) + { + bIsAnyStallIntrPending = NV_TRUE; + } + else + if ((pIntr != NULL) && (INTERRUPT_TYPE_HARDWARE == intrGetIntrEn(pIntr))) + { + NvBool bCtxswLog = NV_FALSE; + intrGetPendingNonStall_HAL(pGpu, pIntr, &intr1Pending, &threadState); + intrCheckFecsEventbufferPending(pGpu, pIntr, &intr1Pending, &bCtxswLog); + if (!bitVectorTestAllCleared(&intr1Pending)) + { + intrServiceNonStall_HAL(pGpu, pIntr, &intr1Pending, &threadState); + *serviced = NV_TRUE; + } + + // + // Step 2: Service nonstall interrupts and check if there are any stall interrupts + // pending on any GPUs. If there are, then we will take the GPU lock. + // + // Bug 4223192: calling intrGetPendingStall_HAL is rather expensive, + // so save off the critical interrupts to be handled in the top half. + // + + // vblank read leaf 4 + read the rest + + NvU32 intrStaticReg; + intrGetPendingDispLowLatencyAndStaticReg_HAL(pGpu, pIntr, &intrStaticReg, &intr0Pending, &threadState); + intrGetRemainingPendingStall_HAL(pGpu, pIntr, intrStaticReg, &intr0Pending, &threadState); + + if (!bitVectorTestAllCleared(&intr0Pending)) + { + if ((pKernelDisplay != NULL) && pKernelDisplay->getProperty(pKernelDisplay, PDB_PROP_KDISP_HAS_SEPARATE_LOW_LATENCY_LINE)) + { + if (bitVectorTest(&intr0Pending, MC_ENGINE_IDX_DISP_LOW)) + { + isDispLowLatencyPendingPerGpu |= NVBIT32(gpuGetInstance(pGpu)); + + // We will attempt to handle this separately from the other stall interrupts + bitVectorClr(&intr0Pending, MC_ENGINE_IDX_DISP_LOW); + } + } + else + { + if (bitVectorTest(&intr0Pending, MC_ENGINE_IDX_DISP)) + { + isDispPendingPerGpu |= NVBIT32(gpuGetInstance(pGpu)); + + // We will attempt to handle this separately from the other stall interrupts + bitVectorClr(&intr0Pending, MC_ENGINE_IDX_DISP); + } + } + + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && + !IS_VIRTUAL(pGpu) && bitVectorTest(&intr0Pending, MC_ENGINE_IDX_TMR)) + { + isTmrPendingPerGpu |= NVBIT32(gpuGetInstance(pGpu)); + + // We will clear this in the top half + bitVectorClr(&intr0Pending, MC_ENGINE_IDX_TMR); + } + + if (!bitVectorTestAllCleared(&intr0Pending)) + { + // + // If any other stall interrupts are pending, + // they will be handled in the bottom half. + // + bIsAnyBottomHalfStallPending = NV_TRUE; + } + + bIsAnyStallIntrPending = NV_TRUE; + } + } + } + threadStateFreeISRLockless(&threadState, pGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS); + } + + // LOCK: try to acquire GPUs lock + if (bIsAnyStallIntrPending && + (rmDeviceGpuLocksAcquire(pGpu, GPU_LOCK_FLAGS_COND_ACQUIRE, RM_LOCK_MODULES_ISR) == NV_OK)) + { + threadStateInitISRAndDeferredIntHandler(&threadState, + pGpu, THREAD_STATE_FLAGS_IS_ISR); + + { + pIntr = GPU_GET_INTR(pGpu); + pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) + { + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_soc_irq_type_t irq_type; + + irq_type = nv_get_current_irq_type(nv); + + if (irq_type == NV_SOC_IRQ_DISPLAY_TYPE) + { + NvU32 dispIntr0Pending = 0; + + if (kdispAcquireLowLatencyLockConditional(&pKernelDisplay->lowLatencyLock)) + { + kdispServiceLowLatencyIntrs_HAL(pGpu, pKernelDisplay, 0, + (VBLANK_STATE_PROCESS_LOW_LATENCY | + VBLANK_STATE_PROCESS_CALLED_FROM_ISR), + &threadState, + NULL, + NULL); + + kdispReleaseLowLatencyLock(&pKernelDisplay->lowLatencyLock); + + *serviced = NV_TRUE; + } + + kdispGetPendingInterrupts_HAL(pGpu, pKernelDisplay, &dispIntr0Pending); + + if (dispIntr0Pending != 0) + { + pending = NV_TRUE; + sema_release = NV_FALSE; + } + } + } + else if ((pIntr != NULL) && INTERRUPT_TYPE_HARDWARE == intrGetIntrEn(pIntr)) + { + // If interrupt enable is garbage the GPU is probably in a bad state + if (!(intrGetIntrEnFromHw_HAL(pGpu, pIntr, &threadState) > INTERRUPT_TYPE_MAX)) + { + // + // If lockless interrupt handling was enabled, we have already cached which critical + // interrupts are pending. We only set the appropriate bits in the intr0Pending bitvector + // for the subsequent code to service them in the same manner as the lockless nonstall + // interrupt handling disabled case. But we also clear them from intr0Pending and + // for disp, check if they're still pending afterwards. We already checked whether any + // other bottom half stall interrupts are pending in bIsAnyBottomHalfStallPending above. + // + // After all this, the combination of bIsAnyBottomHalfStallPending and intr0Pending + // contains whether any stall interrupts are still pending, so check both to determine if + // we need a bottom half. + // + bitVectorClrAll(&intr0Pending); + + if ((pKernelDisplay != NULL) && pKernelDisplay->getProperty(pKernelDisplay, PDB_PROP_KDISP_HAS_SEPARATE_LOW_LATENCY_LINE)) + { + if ((isDispLowLatencyPendingPerGpu & NVBIT32(gpuGetInstance(pGpu))) != 0) + { + bitVectorSet(&intr0Pending, MC_ENGINE_IDX_DISP_LOW); + } + } + else + { + if ((isDispPendingPerGpu & NVBIT32(gpuGetInstance(pGpu))) != 0) + { + bitVectorSet(&intr0Pending, MC_ENGINE_IDX_DISP); + } + + } + + if ((isTmrPendingPerGpu & NVBIT32(gpuGetInstance(pGpu))) != 0) + { + bitVectorSet(&intr0Pending, MC_ENGINE_IDX_TMR); + } + } + + if ((pKernelDisplay != NULL) && + (( pKernelDisplay->getProperty(pKernelDisplay, PDB_PROP_KDISP_HAS_SEPARATE_LOW_LATENCY_LINE) && bitVectorTest(&intr0Pending, MC_ENGINE_IDX_DISP_LOW)) || + (!pKernelDisplay->getProperty(pKernelDisplay, PDB_PROP_KDISP_HAS_SEPARATE_LOW_LATENCY_LINE) && bitVectorTest(&intr0Pending, MC_ENGINE_IDX_DISP)))) + { + MC_ENGINE_BITVECTOR intrDispPending; + NvBool bIsLowLatencyIntrPending; + + // If this is true, then we're here because it is true + bIsLowLatencyIntrPending = pKernelDisplay->getProperty(pKernelDisplay, PDB_PROP_KDISP_HAS_SEPARATE_LOW_LATENCY_LINE); + + if (kdispAcquireLowLatencyLockConditional(&pKernelDisplay->lowLatencyLock)) + { + if (pKernelDisplay->getProperty(pKernelDisplay, PDB_PROP_KDISP_AGGRESSIVE_VBLANK_HANDLING)) + { + // Need to queue a bottom half to service the interrupts since unix otherwise won't + kdispHandleAggressiveVblank(pGpu, pKernelDisplay, pThreadState, &intr0Pending); + } + else + { + kdispServiceLowLatencyIntrs_HAL(pGpu, pKernelDisplay, 0, + (VBLANK_STATE_PROCESS_LOW_LATENCY | + VBLANK_STATE_PROCESS_CALLED_FROM_ISR), + &threadState, + NULL, + &intr0Pending); + + } + + *serviced = NV_TRUE; + + kdispReleaseLowLatencyLock(&pKernelDisplay->lowLatencyLock); + } + + if (bIsLowLatencyIntrPending) + { + bitVectorClr(&intr0Pending, MC_ENGINE_IDX_DISP_LOW); + } + else + { + bitVectorClr(&intr0Pending, MC_ENGINE_IDX_DISP); + } + + intrGetPendingLowLatencyHwDisplayIntr_HAL(pGpu, pIntr, &intrDispPending, &threadState); + + // + // If deferred vblank is used (depends on PDB_PROP_KDISP_AGGRESSIVE_VBLANK_HANDLING) + // and pending, we need to queue a bottom half to service the rest of the interrupts, + // so signal that an interrupt is still pending + // + if (kdispGetDeferredVblankHeadMask(pKernelDisplay) != 0) + { + bitVectorSet(&intrDispPending, MC_ENGINE_IDX_DISP); + } + + bitVectorOr(&intr0Pending, &intr0Pending, &intrDispPending); + } + + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && + !IS_VIRTUAL(pGpu) && bitVectorTest(&intr0Pending, MC_ENGINE_IDX_TMR)) + { + // We have to clear the top level interrupt bit here since otherwise + // the bottom half will attempt to service the interrupt on the CPU + // side before GSP receives the notification and services it + intrClearLeafVector_HAL(pGpu, pIntr, intrGetVectorFromEngineId(pGpu, pIntr, MC_ENGINE_IDX_TMR, NV_FALSE), &threadState); + bitVectorClr(&intr0Pending, MC_ENGINE_IDX_TMR); + + NV_ASSERT_OK(intrTriggerPrivDoorbell_HAL(pGpu, pIntr, NV_DOORBELL_NOTIFY_LEAF_SERVICE_TMR_HANDLE)); + } + + { + bitVectorClrAll(&intr1Pending); + } + + if (bIsAnyBottomHalfStallPending || + !bitVectorTestAllCleared(&intr0Pending) || + !bitVectorTestAllCleared(&intr1Pending)) + { + pending = NV_TRUE; + sema_release = NV_FALSE; + } + } + } + + if (sema_release) + { + NV_ASSERT(!pending); + + // UNLOCK: release GPUs lock + rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); + } + else + { + rmDeviceGpuLockSetOwner(pGpu, GPUS_LOCK_OWNER_PENDING_DPC_REFRESH); + } + + threadStateFreeISRAndDeferredIntHandler(&threadState, + pGpu, THREAD_STATE_FLAGS_IS_ISR); + } + else if (bIsAnyStallIntrPending) + { + threadStateInitISRLockless(&threadState, pGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS); + + { + pIntr = GPU_GET_INTR(pGpu); + + if ((pIntr != NULL) && (pIntr->getProperty(pIntr, PDB_PROP_INTR_USE_INTR_MASK_FOR_LOCKING))) + { + if (_osIsrIntrMask_GpusUnlocked(pGpu, &threadState) == NV_OK) + { + *serviced = NV_TRUE; + } + } + } + + threadStateFreeISRLockless(&threadState, pGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS); + } + + tlsIsrDestroy(pIsrAllocator); + portMemAllocatorRelease(pIsrAllocator); + + return pending; +} + +NV_STATUS osIsr( + OBJGPU *pGpu +) +{ + NV_STATUS status = NV_OK; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvBool pending = NV_FALSE; + NvBool serviced = NV_FALSE; + Intr *pIntr; + + if (nvp->flags & NV_INIT_FLAG_GPU_STATE_LOAD) + { + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) + { + pending = osInterruptPending(pGpu, &serviced, NULL /* threadstate */); + } + else + { + pIntr = GPU_GET_INTR(pGpu); + if (INTERRUPT_TYPE_HARDWARE == intrGetIntrEn(pIntr)) + { + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + pending = osInterruptPending(pGpu, &serviced, NULL /* threadstate */); + kbifCheckAndRearmMSI(pGpu, pKernelBif); + } + } + } + + if (!pending && (IS_VIRTUAL(pGpu) || !serviced)) + status = NV_ERR_NO_INTR_PENDING; + else if (pending) + status = NV_WARN_MORE_PROCESSING_REQUIRED; + + return status; +} + +/* + * Helper function to determine when the RM SEMA/GPUS LOCK should toggle + * interrupts. Based on the state of the GPU - we must add cases here as we + * discover them. + * + * Noteworthy special cases: + * + * - Suspend/resume: the GPU could still be suspended and not accessible + * on the bus, while passive-level threads need to grab the GPUs + * lock, or other GPUs are being resumed and triggering interrupts. + * + * @param[in] pGpu OBJGPU pointer + * + * @return NV_TRUE if the RM SEMA/GPUS LOCK should toggle interrupts, NV_FALSE + * otherwise. + */ +NvBool osLockShouldToggleInterrupts(OBJGPU *pGpu) +{ + if (IS_DCE_CLIENT(pGpu)) + { + return NV_TRUE; + } + + return (!pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_PM_CODEPATH) && + gpuIsStateLoaded(pGpu)); +} + +void osEnableInterrupts(OBJGPU *pGpu) +{ + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) + { + // enable irq through os call + nv_control_soc_irqs(NV_GET_NV_STATE(pGpu), NV_TRUE); + return; + } + else + { + Intr *pIntr = GPU_GET_INTR(pGpu); + NvU32 intrEn; + + if (!pIntr->getProperty(pIntr, PDB_PROP_INTR_USE_INTR_MASK_FOR_LOCKING)) + NV_ASSERT(intrGetIntrEnFromHw_HAL(pGpu, pIntr, NULL) == INTERRUPT_TYPE_DISABLED); + + intrEn = intrGetIntrEn(pIntr); + intrSetIntrEnInHw_HAL(pGpu, pIntr, intrEn, NULL); + intrSetStall_HAL(pGpu, pIntr, intrEn, NULL); + + intrRestoreNonStall_HAL(pGpu, pIntr, intrGetIntrEn(pIntr), NULL); + } +} + +void osDisableInterrupts( + OBJGPU *pGpu, + NvBool bIsr +) +{ + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) + { + // disable irq through os call + nv_control_soc_irqs(NV_GET_NV_STATE(pGpu), NV_FALSE); + return; + } + else + { + Intr *pIntr = GPU_GET_INTR(pGpu); + NvU32 new_intr_en_0 = INTERRUPT_TYPE_DISABLED; + + intrSetIntrEnInHw_HAL(pGpu, pIntr, new_intr_en_0, NULL); + intrSetStall_HAL(pGpu, pIntr, new_intr_en_0, NULL); + + intrRestoreNonStall_HAL(pGpu, pIntr, intrGetIntrEn(pIntr), NULL); + } +} + +static void RmIsrBottomHalf( + nv_state_t *pNv +) +{ + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + OS_THREAD_HANDLE threadId; + Intr *pIntr = NULL; + NvU8 stackAllocator[TLS_ISR_ALLOCATOR_SIZE]; // ISR allocations come from this buffer + PORT_MEM_ALLOCATOR *pIsrAllocator; + + pIsrAllocator = portMemAllocatorCreateOnExistingBlock(stackAllocator, sizeof(stackAllocator)); + tlsIsrInit(pIsrAllocator); + + // + // The owning thread changes as the ISR acquires the GPUs lock, + // but the bottom half releases it. Refresh the ThreadId owner to be + // correct here for the bottom half context. + // + osGetCurrentThread(&threadId); + rmDeviceGpuLockSetOwner(pGpu, threadId); + + { + threadStateInitISRAndDeferredIntHandler(pGpu->pDpcThreadState, pGpu, + THREAD_STATE_FLAGS_IS_ISR_DEFERRED_INT_HANDLER); + } + + { + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + gpumgrSetCurrentGpuInstance(pGpu->gpuInstance); + + pIntr = GPU_GET_INTR(pGpu); + + // + // Call disp service incase of SOC Display, + // TODO : with multi interrupt handling based on irq aux interrupts are serviced by dpAuxService + // See JIRA task TDS-4253. + // + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) + { + if (nv_get_current_irq_type(nv) == NV_SOC_IRQ_DISPLAY_TYPE) + { + if (IS_DCE_CLIENT(pGpu)) + { + kdispAcquireLowLatencyLock(&pKernelDisplay->lowLatencyLock); + + kdispServiceLowLatencyIntrs_HAL(pGpu, pKernelDisplay, 0, + VBLANK_STATE_PROCESS_LOW_LATENCY, + pGpu->pDpcThreadState, + NULL, + NULL); + + kdispReleaseLowLatencyLock(&pKernelDisplay->lowLatencyLock); + } + else + { + } + } + } + else if ((pIntr != NULL) && (INTERRUPT_TYPE_HARDWARE == intrGetIntrEn(pIntr))) + { + intrServiceStall_HAL(pGpu, pIntr); + } + + gpumgrSetCurrentGpuInstance(NV_U32_MAX); + } + + // UNLOCK: release GPUs lock + rmDeviceGpuLocksReleaseAndThreadStateFreeDeferredIntHandlerOptimized(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); + + tlsIsrDestroy(pIsrAllocator); + portMemAllocatorRelease(pIsrAllocator); +} + +static void RmIsrBottomHalfUnlocked( + nv_state_t *pNv +) +{ + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + Intr *pIntr; + THREAD_STATE_NODE threadState; + + // In the GSP client scenario, the fatal fault interrupt is not shared + // by UVM and CPU-RM. Instead, it is handled entirely by GSP-RM. We + // therefore do not expect this function to be called. But if it is, bail + // without attempting to service interrupts. + if (IS_GSP_CLIENT(pGpu)) + { + return; + } + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // Grab GPU lock here as this kthread-item was enqueued without grabbing GPU lock + if (rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DPC) == NV_OK) + { + if (FULL_GPU_SANITY_CHECK(pGpu)) + { + pIntr = GPU_GET_INTR(pGpu); + + if (intrGetIntrEn(pIntr) != INTERRUPT_TYPE_DISABLED) + { + MC_ENGINE_BITVECTOR intrPending; + intrGetPendingStall_HAL(pGpu, pIntr, &intrPending, &threadState); + intrServiceNonStallBottomHalf(pGpu, pIntr, &intrPending, &threadState); + } + } + + rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); +} + +NvBool NV_API_CALL rm_isr( + nvidia_stack_t *sp, + nv_state_t *nv, + NvU32 *NeedBottomHalf +) +{ + NV_STATUS status; + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + OBJGPU *pGpu; + NvBool retval; + void *fp; + + if ((nvp->flags & NV_INIT_FLAG_GPU_STATE_LOAD) == 0) + { + return NV_FALSE; + } + + pGpu = NV_GET_NV_PRIV_PGPU(nv); + if (pGpu == NULL) + { + return NV_FALSE; + } + + NV_ENTER_RM_RUNTIME(sp,fp); + + // call actual isr function here + status = isrWrapper(pGpu->testIntr, pGpu); + + switch (status) + { + case NV_OK: + *NeedBottomHalf = NV_FALSE; + retval = NV_TRUE; + break; + case NV_WARN_MORE_PROCESSING_REQUIRED: + *NeedBottomHalf = NV_TRUE; + retval = NV_TRUE; + break; + case NV_ERR_NO_INTR_PENDING: + default: + *NeedBottomHalf = NV_FALSE; + retval = NV_FALSE; + break; + } + + NV_EXIT_RM_RUNTIME(sp,fp); + + return retval; +} + +void NV_API_CALL rm_isr_bh( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + RmIsrBottomHalf(pNv); + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +void NV_API_CALL rm_isr_bh_unlocked( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + RmIsrBottomHalfUnlocked(pNv); + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults( + nvidia_stack_t *sp, + nv_state_t *nv, + NvU32 *faultsCopied +) +{ + NV_STATUS status = NV_OK; + OBJGPU *pGpu; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + pGpu = NV_GET_NV_PRIV_PGPU(nv); + if (pGpu == NULL || faultsCopied == NULL) + { + status = NV_ERR_OBJECT_NOT_FOUND; + goto done; + } + + if (IS_GSP_CLIENT(pGpu)) + { + // Non-replayable faults are copied to the client shadow buffer by GSP-RM. + status = NV_OK; + goto done; + } + else + { + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + PORT_MEM_ALLOCATOR *pIsrAllocator; + THREAD_STATE_NODE threadState; + NvU8 stackAllocator[TLS_ISR_ALLOCATOR_SIZE]; // ISR allocations come from this buffer + + if (pKernelGmmu == NULL) + { + status = NV_ERR_OBJECT_NOT_FOUND; + goto done; + } + + // If MMU fault buffer is not enabled, return early + if (!gpuIsVoltaHubIntrSupported(pGpu)) + goto done; + + pIsrAllocator = portMemAllocatorCreateOnExistingBlock(stackAllocator, sizeof(stackAllocator)); + tlsIsrInit(pIsrAllocator); + threadStateInitISRAndDeferredIntHandler(&threadState, pGpu, THREAD_STATE_FLAGS_IS_ISR); + + // Copies all valid packets in RM's and client's shadow buffer + status = kgmmuCopyMmuFaults_HAL(pGpu, pKernelGmmu, &threadState, faultsCopied, + NON_REPLAYABLE_FAULT_BUFFER, NV_FALSE); + + threadStateFreeISRAndDeferredIntHandler(&threadState, pGpu, THREAD_STATE_FLAGS_IS_ISR); + tlsIsrDestroy(pIsrAllocator); + portMemAllocatorRelease(pIsrAllocator); + + } + +done: + NV_EXIT_RM_RUNTIME(sp,fp); + + return status; +} + +// +// Use this call when MMU faults needs to be copied +// outisde of RM lock. +// +static NV_STATUS _rm_gpu_copy_mmu_faults_unlocked( + OBJGPU *pGpu, + NvU32 *pFaultsCopied, + THREAD_STATE_NODE *pThreadState +) +{ + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + + if (pKernelGmmu == NULL) + { + return NV_ERR_OBJECT_NOT_FOUND; + } + + // If MMU fault buffer is not enabled, return early + if (!gpuIsVoltaHubIntrSupported(pGpu)) + return NV_OK; + + // Copies all valid packets in RM's and client's shadow buffer + return kgmmuCopyMmuFaults_HAL(pGpu, pKernelGmmu, pThreadState, pFaultsCopied, + NON_REPLAYABLE_FAULT_BUFFER, NV_FALSE); + + return NV_OK; +} + +// +// Wrapper to handle calls to copy mmu faults +// +NV_STATUS rm_gpu_handle_mmu_faults( + nvidia_stack_t *sp, + nv_state_t *nv, + NvU32 *faultsCopied +) +{ + NvU32 status = NV_OK; + OBJGPU *pGpu; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + *faultsCopied = 0; + pGpu = NV_GET_NV_PRIV_PGPU(nv); + + if (pGpu == NULL) + { + NV_EXIT_RM_RUNTIME(sp,fp); + return NV_ERR_OBJECT_NOT_FOUND; + } + + { + KernelGmmu *pKernelGmmu; + PORT_MEM_ALLOCATOR *pIsrAllocator; + THREAD_STATE_NODE threadState; + NvU8 stackAllocator[TLS_ISR_ALLOCATOR_SIZE]; // ISR allocations come from this buffer + + pIsrAllocator = portMemAllocatorCreateOnExistingBlock(stackAllocator, sizeof(stackAllocator)); + tlsIsrInit(pIsrAllocator); + threadStateInitISRLockless(&threadState, pGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS); + + pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && !IS_VIRTUAL(pGpu)) + { + Intr *pIntr = GPU_GET_INTR(pGpu); + + if (kgmmuIsNonReplayableFaultPending_HAL(pGpu, pKernelGmmu, &threadState)) + { + // We have to clear the top level interrupt bit here since otherwise + // the bottom half will attempt to service the interrupt on the CPU + // side before GSP receives the notification and services it + kgmmuClearNonReplayableFaultIntr_HAL(pGpu, pKernelGmmu, &threadState); + status = intrTriggerPrivDoorbell_HAL(pGpu, pIntr, NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_HANDLE); + + } + } + else if (IS_VIRTUAL_WITH_SRIOV(pGpu)) + { + if (kgmmuIsNonReplayableFaultPending_HAL(pGpu, pKernelGmmu, &threadState)) + { + status = _rm_gpu_copy_mmu_faults_unlocked(pGpu, faultsCopied, &threadState); + } + } + else + { + if (IS_GSP_CLIENT(pGpu)) + { + // Non-replayable faults are copied to the client shadow buffer by GSP-RM. + status = NV_OK; + } + else + { + status = _rm_gpu_copy_mmu_faults_unlocked(pGpu, faultsCopied, &threadState); + } + } + + threadStateFreeISRLockless(&threadState, pGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS); + tlsIsrDestroy(pIsrAllocator); + portMemAllocatorRelease(pIsrAllocator); + } + + NV_EXIT_RM_RUNTIME(sp,fp); + return status; +} + +NvBool NV_API_CALL rm_is_msix_allowed( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + nv_priv_t *pNvp = NV_GET_NV_PRIV(nv); + THREAD_STATE_NODE threadState; + void *fp; + NvBool ret = NV_FALSE; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_INIT) == NV_OK) + { + ret = gpumgrIsDeviceMsixAllowed(nv->regs->cpu_address, + pNvp->pmc_boot_1, pNvp->pmc_boot_42); + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + return ret; +} diff --git a/userspace/sdks/nv570/nvalloc/unix/src/vbioscall.c b/userspace/sdks/nv570/nvalloc/unix/src/vbioscall.c new file mode 100644 index 0000000..8eeb85e --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/src/vbioscall.c @@ -0,0 +1,457 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/****************************************************************************** +* +* Description: +* This file provides the glue layer between the RM's OS object +* unixCallVideoBIOS() method and the x86 real mode emulator +* +******************************************************************************/ + + +#include +#include +#include +#include + +#include + +#include + +#define IO_LOG(port, val) + +#define NV_ROMLEY_VGA_PHYS_ADDR 0x9d000 +#define NV_VGA_PHYS_ADDR 0xa0000 +#define NV_VIDEO_ROM_PHYS_ADDR 0xc0000 +#define NV_EXPANSION_VIDEO_ROM_PHYS_ADDR 0xc8000 +#define NV_SYSTEM_ROM_PHYS_ADDR 0xf0000 + +#define X86EMU_LOWMEM 0x600 // Interrupt vectors, BIOS data size +#define X86EMU_STACK_ADDR 0x10000 +#define X86EMU_STACK_SIZE 0x1000 +#define X86EMU_BUF_ADDR 0x20000 // EDID buffer for VESA int10 0x4f15 +#define X86EMU_BUF_SIZE 128 + +#define OP_HLT 0xf4 // HLT instruction - causes the emulator to return + +// This is where IRET from int10 will take us +#define X86EMU_IRET_SEG (X86EMU_STACK_ADDR >> 4) +#define X86EMU_IRET_OFF 0 + +#define X86EMU_DFLT_FLAGS (F_IF) + +static NvBool x86emuReady; +static void *x86emuStack; + +static struct x86emu_mem_seg { + NvU32 start; + NvU32 end; + void *vaddr; +} x86emu_mem_map[] = { + {NV_ROMLEY_VGA_PHYS_ADDR, NV_VGA_PHYS_ADDR - 1}, + {NV_VGA_PHYS_ADDR, NV_VIDEO_ROM_PHYS_ADDR - 1}, // vga + {NV_VIDEO_ROM_PHYS_ADDR, NV_EXPANSION_VIDEO_ROM_PHYS_ADDR -1}, // vbios, sbios + {NV_EXPANSION_VIDEO_ROM_PHYS_ADDR, NV_SYSTEM_ROM_PHYS_ADDR -1}, // vbios, sbios + {NV_SYSTEM_ROM_PHYS_ADDR, 0xFFFFF}, // Motherboard BIOS + {X86EMU_STACK_ADDR, X86EMU_STACK_ADDR + X86EMU_STACK_SIZE - 1}, // emulator stack + {0, X86EMU_LOWMEM - 1}, // Interrupt vectors, BIOS data + {X86EMU_BUF_ADDR, X86EMU_BUF_ADDR + X86EMU_BUF_SIZE - 1}, +}; + +enum { + X86EMU_SEG_ROMLEY_VGA = 0, + X86EMU_SEG_VGA, + X86EMU_SEG_ROM, + X86EMU_SEG_ROM_EXPANSION, + X86EMU_SEG_ROM_MOTHERBOARD_BIOS, + X86EMU_SEG_EMULATOR_STACK, + X86EMU_SEG_BIOS_DATA, + X86EMU_SEG_EDID_BUFFER, + X86EMU_NUM_SEGS +}; + +ct_assert(X86EMU_NUM_SEGS == NV_ARRAY_ELEMENTS(x86emu_mem_map)); + +static NvU8 +x_inb(NvU16 port) +{ + NvU8 val; + + val = os_io_read_byte(port); + IO_LOG(port, val); + return val; +} + +static void +x_outb(NvU16 port, NvU8 val) +{ + IO_LOG(port, val); + os_io_write_byte(port, val); +} + +static NvU16 +x_inw(NvU16 port) +{ + NvU16 val; + + val = os_io_read_word(port); + IO_LOG(port, val); + return val; +} + +static void +x_outw(NvU16 port, NvU16 val) +{ + IO_LOG(port, val); + os_io_write_word(port, val); +} + +static u32 +x_inl(X86EMU_pioAddr port) +{ + NvU32 val; + + val = os_io_read_dword(port); + IO_LOG(port, val); + return val; +} + +static void +x_outl(X86EMU_pioAddr port, u32 val) +{ + IO_LOG(port, val); + os_io_write_dword(port, val); +} + +static void * +Mem_addr_xlat(NvU32 addr, NvU32 sz) +{ + int i; + struct x86emu_mem_seg *pseg; + + for (i = 0; i < X86EMU_NUM_SEGS; ++i) + { + pseg = x86emu_mem_map + i; + if (pseg->vaddr != 0 && addr >= pseg->start && addr + sz - 1 <= pseg->end) + return (void *)((char *)pseg->vaddr + addr - pseg->start); + } + + X86EMU_halt_sys(); + + return 0; +} + +static NvU8 +Mem_rb(u32 addr) +{ + NvU8 *va = Mem_addr_xlat(addr, 1); + + return va != 0 ? *va : 0; +} + +static NvU16 +Mem_rw(u32 addr) +{ + NvU16 *va = Mem_addr_xlat(addr, 2); + + return va != 0 ? *va : 0; +} + +static u32 +Mem_rl(u32 addr) +{ + NvU32 *va = Mem_addr_xlat(addr, 4); + + return va != 0 ? *va : 0; +} + +static void +Mem_wb(u32 addr, NvU8 val) +{ + NvU8 *va = Mem_addr_xlat(addr, 1); + + if (va != 0) + *va = val; +} + +static void +Mem_ww(u32 addr, NvU16 val) +{ + NvU16 *va = Mem_addr_xlat(addr, 2); + + if (va != 0) + *va = val; +} + +static void +Mem_wl(u32 addr, u32 val) +{ + NvU32 *va = Mem_addr_xlat(addr, 4); + + if (va != 0) + *va = val; +} + +static NvU16 +get_int_seg(int i) +{ + return Mem_rw(i * 4 + 2); +} + + +static NvU16 +get_int_off(int i) +{ + return Mem_rw(i * 4); +} + + +static void +pushw(NvU16 i) +{ + M.x86.R_ESP -= 2; + Mem_ww((M.x86.R_SS << 4) + M.x86.R_ESP, i); +} + +static void +x86emu_do_int(int num) +{ +#if 0 + Int10Current->num = num; + + if (!int_handler(Int10Current)) { + X86EMU_halt_sys(); + } +#else + if ((num == 0x15) && (M.x86.R_AX == 0x5f80)) + { + // + // Handle the MXM_SYS_INFO_CALLBACK_NUM int 15h SBIOS + // callback: disclaim support by returning a value + // other than 005fh (MXM_SYS_INFO_CALLBACK_FUNC_SUPPORTED) + // to the caller. + // + M.x86.R_AX = 0; + } + else + { + NV_PRINTF(LEVEL_ERROR, "x86emu: int $%d (eax = %08x)\n", + num, M.x86.R_EAX); + DBG_BREAKPOINT(); + X86EMU_halt_sys(); + } +#endif +} + +NV_STATUS +RmInitX86EmuState(OBJGPU *pGpu) { + int i; + struct x86emu_mem_seg *pseg; + X86EMU_intrFuncs *intFuncs; + X86EMU_pioFuncs pioFuncs = { + (&x_inb), + (&x_inw), + (&x_inl), + (&x_outb), + (&x_outw), + (&x_outl) + }; + + X86EMU_memFuncs memFuncs = { + (&Mem_rb), + (&Mem_rw), + (&Mem_rl), + (&Mem_wb), + (&Mem_ww), + (&Mem_wl) + }; + + if (!NV_PRIMARY_VGA(NV_GET_NV_STATE(pGpu))) // not the primary GPU + return NV_OK; + + NV_ASSERT(!x86emuReady); + + x86emuStack = portMemAllocNonPaged( + X86EMU_STACK_SIZE + sizeof(X86EMU_intrFuncs*) * 256); + if (x86emuStack == NULL) + return NV_ERR_NO_MEMORY; + + // Interrupt dispatch table + intFuncs = (void *)((NvU8 *)x86emuStack + X86EMU_STACK_SIZE); + + // Fill virtual addresses in the memory map + for (i = 0; i < X86EMU_NUM_SEGS; ++i) + { + pseg = x86emu_mem_map + i; + switch (i) + { + case X86EMU_SEG_ROM: + case X86EMU_SEG_ROM_EXPANSION: + case X86EMU_SEG_ROM_MOTHERBOARD_BIOS: + nv_get_updated_emu_seg(&pseg->start, &pseg->end); + /* fallthrough */ + case X86EMU_SEG_VGA: + case X86EMU_SEG_BIOS_DATA: + pseg->vaddr = os_map_kernel_space(pseg->start, + pseg->end - pseg->start + 1, + NV_MEMORY_CACHED); + if (pseg->vaddr == 0) + { + NV_PRINTF(LEVEL_ERROR, "x86emu can't map phys addr 0x%05x\n", + pseg->start); + return NV_ERR_GENERIC; + } + break; + case X86EMU_SEG_EMULATOR_STACK: + pseg->vaddr = x86emuStack; + break; + default: + pseg->vaddr = 0; + break; + } + } + X86EMU_setupMemFuncs(&memFuncs); + + M.mem_base = 0; + M.mem_size = 1024*1024; + X86EMU_setupPioFuncs(&pioFuncs); + + for (i=0;i<256;i++) + intFuncs[i] = x86emu_do_int; + X86EMU_setupIntrFuncs(intFuncs); + + x86emuReady = NV_TRUE; + + return NV_OK; +} + +void +RmFreeX86EmuState(OBJGPU *pGpu) +{ + int i; + struct x86emu_mem_seg *pseg; + + if (! x86emuReady || !NV_PRIMARY_VGA(NV_GET_NV_STATE(pGpu))) // not the primary GPU + return; + + portMemFree(x86emuStack); + x86emuStack = 0; + + for (i = 0; i < X86EMU_NUM_SEGS; ++i) + { + pseg = x86emu_mem_map + i; + switch (i) + { + case X86EMU_SEG_ROMLEY_VGA: + case X86EMU_SEG_VGA: + case X86EMU_SEG_ROM: + case X86EMU_SEG_ROM_EXPANSION: + case X86EMU_SEG_ROM_MOTHERBOARD_BIOS: + case X86EMU_SEG_BIOS_DATA: + if (pseg->vaddr != 0) + os_unmap_kernel_space(pseg->vaddr, pseg->end - pseg->start + 1); + } + pseg->vaddr = 0; + } + + x86emuReady = NV_FALSE; +} + +NV_STATUS +nv_vbios_call( + OBJGPU *pGpu, + NvU32 *eax, + NvU32 *ebx) +{ + NvU16 seg; + NvU16 off; + struct x86emu_mem_seg *pseg; + + if (!NV_PRIMARY_VGA(NV_GET_NV_STATE(pGpu))) + return NV_ERR_GENERIC; + + seg = get_int_seg(0x10); + off = get_int_off(0x10); + + pseg = &x86emu_mem_map[X86EMU_SEG_VGA]; + if (seg < (pseg->start >> 4)) + { + pseg = &x86emu_mem_map[X86EMU_SEG_ROMLEY_VGA]; + if (seg < (pseg->start >> 4)) + { + NV_PRINTF(LEVEL_ERROR, + "cannot call the VBIOS. INT10 vector not in ROM: %04x:%04x\n", + seg, off); + return NV_ERR_GENERIC; + } + else if (pseg->vaddr == NULL) + { + pseg->vaddr = os_map_kernel_space(pseg->start, + (pseg->end - pseg->start + 1), + NV_MEMORY_CACHED); + if (pseg->vaddr == NULL) + { + NV_PRINTF(LEVEL_ERROR, "x86emu can't map phys addr 0x%05x\n", + pseg->start); + return NV_ERR_GENERIC; + } + } + } + + // Reset the CPU + portMemSet(&M, 0, sizeof(M)); + + M.x86.R_SS = X86EMU_STACK_ADDR >> 4; + M.x86.R_ESP = X86EMU_STACK_SIZE; + M.x86.R_CS = seg; + M.x86.R_EIP = off; + M.x86.R_EFLG = X86EMU_DFLT_FLAGS; + M.x86.R_EAX = *eax; + M.x86.R_EBX = *ebx; + M.x86.R_ECX = 0; + M.x86.R_EDX = 0; + M.x86.R_ES = X86EMU_BUF_ADDR >> 4; + + X86EMU_trace_on(); + + // Map ES:EDI to buffer. Used by vesa intr 4f15 - read EDID + pseg = &x86emu_mem_map[X86EMU_SEG_EDID_BUFFER]; + pseg->vaddr = NULL; + + // Prepare the code for IRET to jump to + Mem_wb((X86EMU_IRET_SEG << 4) + X86EMU_IRET_OFF, OP_HLT); + + pushw(X86EMU_DFLT_FLAGS); + pushw(X86EMU_IRET_SEG); + pushw(X86EMU_IRET_OFF); + + // Run the emulator + X86EMU_exec(); + + *eax = M.x86.R_EAX; + *ebx = M.x86.R_EBX; + + return NV_OK; +} diff --git a/userspace/sdks/nv570/nvalloc/unix/x86emu/debug.c b/userspace/sdks/nv570/nvalloc/unix/x86emu/debug.c new file mode 100644 index 0000000..ccf8be7 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/x86emu/debug.c @@ -0,0 +1,547 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file contains the code to handle debugging of the +* emulator. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" +#ifndef NO_SYS_HEADERS +#include +#include +#endif + +/*----------------------------- Implementation ----------------------------*/ + +#ifdef X86EMU_DEBUG + +static void print_encoded_bytes (u16 s, u16 o); +static void print_decoded_instruction (void); +static int parse_line (char *s, int *ps, int *n); + +/* should look something like debug's output. */ +void X86EMU_trace_regs (void) +{ + if (DEBUG_TRACE()) { + x86emu_dump_regs(); + } + if (DEBUG_DECODE() && ! DEBUG_DECODE_NOPRINT()) { + NV_PRINTF(LEVEL_INFO, "%04x:%04x ", M.x86.saved_cs, + M.x86.saved_ip); + print_encoded_bytes( M.x86.saved_cs, M.x86.saved_ip); + print_decoded_instruction(); + } +} + +void X86EMU_trace_xregs (void) +{ + if (DEBUG_TRACE()) { + x86emu_dump_xregs(); + } +} + +void x86emu_just_disassemble (void) +{ + /* + * This routine called if the flag DEBUG_DISASSEMBLE is set kind + * of a hack! + */ + NV_PRINTF(LEVEL_INFO, "%04x:%04x ", M.x86.saved_cs, + M.x86.saved_ip); + print_encoded_bytes( M.x86.saved_cs, M.x86.saved_ip); + print_decoded_instruction(); +} + +static void disassemble_forward (u16 seg, u16 off, int n) +{ + X86EMU_sysEnv tregs; + int i; + u8 op1; + /* + * hack, hack, hack. What we do is use the exact machinery set up + * for execution, except that now there is an additional state + * flag associated with the "execution", and we are using a copy + * of the register struct. All the major opcodes, once fully + * decoded, have the following two steps: TRACE_REGS(r,m); + * SINGLE_STEP(r,m); which disappear if DEBUG is not defined to + * the preprocessor. The TRACE_REGS macro expands to: + * + * if (debug&DEBUG_DISASSEMBLE) + * {just_disassemble(); goto EndOfInstruction;} + * if (debug&DEBUG_TRACE) trace_regs(r,m); + * + * ...... and at the last line of the routine. + * + * EndOfInstruction: end_instr(); + * + * Up to the point where TRACE_REG is expanded, NO modifications + * are done to any register EXCEPT the IP register, for fetch and + * decoding purposes. + * + * This was done for an entirely different reason, but makes a + * nice way to get the system to help debug codes. + */ + tregs = M; + tregs.x86.R_IP = off; + tregs.x86.R_CS = seg; + + /* reset the decoding buffers */ + tregs.x86.enc_str_pos = 0; + tregs.x86.enc_pos = 0; + + /* turn on the "disassemble only, no execute" flag */ + tregs.x86.debug |= DEBUG_DISASSEMBLE_F; + + /* DUMP NEXT n instructions to screen in straight_line fashion */ + /* + * This looks like the regular instruction fetch stream, except + * that when this occurs, each fetched opcode, upon seeing the + * DEBUG_DISASSEMBLE flag set, exits immediately after decoding + * the instruction. XXX --- CHECK THAT MEM IS NOT AFFECTED!!! + * Note the use of a copy of the register structure... + */ + for (i=0; i 256) return; + seg = fetch_data_word_abs(0,iv*4); + off = fetch_data_word_abs(0,iv*4+2); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "%04x:%04x ", seg, off); +} + +void X86EMU_dump_memory (u16 seg, u16 off, u32 amt) +{ + u32 start = off & 0xfffffff0; + u32 end = (off+16) & 0xfffffff0; + u32 i; + + while (end <= off + amt) { + NV_PRINTF(LEVEL_INFO, "%04x:%04x ", seg, start); + for (i=start; i< off; i++) + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, " "); + for ( ; i< end; i++) + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "%02x ", fetch_data_byte_abs(seg, i)); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "\n"); + start = end; + end = start + 16; + } +} + +void x86emu_single_step (void) +{ + int ps[10]; + int ntok; + int cmd; + int done; + int segment; + int offset; + static int breakpoint; + static int noDecode = 1; + + if (DEBUG_BREAK()) { + if (M.x86.saved_ip != breakpoint) { + return; + } else { + M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; + M.x86.debug |= DEBUG_TRACE_F; + M.x86.debug &= ~DEBUG_BREAK_F; + print_decoded_instruction (); + X86EMU_trace_regs(); + } + } + done=0; + offset = M.x86.saved_ip; + while (!done) { + NV_PRINTF(LEVEL_INFO, "-"); + + /* + * Set _X86EMU_env.x86.debug_cmd from a kernel debugger to a command to + * control the emulator debugger + */ + if (M.x86.debug_cmd[0] == '\0') + { + DBG_BREAKPOINT(); + } + + cmd = parse_line(M.x86.debug_cmd, ps, &ntok); + switch(cmd) { + case 'u': + disassemble_forward(M.x86.saved_cs,(u16)offset,10); + break; + case 'd': + if (ntok == 2) { + segment = M.x86.saved_cs; + offset = ps[1]; + X86EMU_dump_memory(segment,(u16)offset,16); + offset += 16; + } else if (ntok == 3) { + segment = ps[1]; + offset = ps[2]; + X86EMU_dump_memory(segment,(u16)offset,16); + offset += 16; + } else { + segment = M.x86.saved_cs; + X86EMU_dump_memory(segment,(u16)offset,16); + offset += 16; + } + break; + case 'c': + M.x86.debug ^= DEBUG_TRACECALL_F; + break; + case 's': + M.x86.debug ^= DEBUG_SVC_F | DEBUG_SYS_F | DEBUG_SYSINT_F; + break; + case 'r': + X86EMU_trace_regs(); + break; + case 'x': + X86EMU_trace_xregs(); + break; + case 'g': + if (ntok == 2) { + breakpoint = ps[1]; + if (noDecode) { + M.x86.debug |= DEBUG_DECODE_NOPRINT_F; + } else { + M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; + } + M.x86.debug &= ~DEBUG_TRACE_F; + M.x86.debug |= DEBUG_BREAK_F; + done = 1; + } + break; + case 'q': + M.x86.debug |= DEBUG_EXIT; + return; + case 'P': + noDecode = (noDecode)?0:1; + NV_PRINTF(LEVEL_INFO, "Toggled decoding to %s\n", + (noDecode) ? "FALSE" : "TRUE"); + break; + case 'a': + X86EMU_trace_off(); + /* fall thru */ + case 't': + case 0: + done = 1; + break; + } + portMemSet(&M.x86.debug_cmd, 0, sizeof(M.x86.debug_cmd)); + } +} + +int X86EMU_trace_on(void) +{ + return M.x86.debug |= DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F; +} + +int X86EMU_trace_off(void) +{ + return M.x86.debug &= ~(DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F); +} + +static void parse_hex (char *s, int *pval) +{ + unsigned int val = 0; + unsigned char c; + + if (s[0] == '0' && s[1] == 'x') + s += 2; + + while ((c = *(s++))) + { + if (c >= '0' && c <= '9') + { + val <<= 4; + val |= c - '0'; + continue; + } + else if (c >= 'a' && c <= 'f') + { + val <<= 4; + val |= c - 'a'; + continue; + } + else if (c >= 'A' && c <= 'F') + { + val <<= 4; + val |= c - 'A'; + continue; + } + break; + } + + *pval = val; +} + +static int parse_line (char *s, int *ps, int *n) +{ + int cmd; + + *n = 0; + while(*s == ' ' || *s == '\t') s++; + ps[*n] = *s; + switch (*s) { + case '\n': + *n += 1; + return 0; + default: + cmd = *s; + *n += 1; + } + + while (1) + { + while (*s != ' ' && *s != '\t' && *s != '\n' && *s != '\0') + s++; + + if (*s == '\n' || *s == '\0') + return cmd; + + while(*s == ' ' || *s == '\t') + s++; + + parse_hex(s, &ps[*n]); + *n += 1; + } +} + +void x86emu_dump_regs (void) +{ + NV_PRINTF(LEVEL_INFO, "\tAX=%04x ", M.x86.R_AX); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "BX=%04x ", M.x86.R_BX); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "CX=%04x ", M.x86.R_CX); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "DX=%04x ", M.x86.R_DX); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "SP=%04x ", M.x86.R_SP); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "BP=%04x ", M.x86.R_BP); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "SI=%04x ", M.x86.R_SI); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "DI=%04x\n", M.x86.R_DI); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "\tDS=%04x ", M.x86.R_DS); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "ES=%04x ", M.x86.R_ES); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "SS=%04x ", M.x86.R_SS); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "CS=%04x ", M.x86.R_CS); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "IP=%04x ", M.x86.R_IP); + if (ACCESS_FLAG(F_OF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "OV "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NV "); + } + if (ACCESS_FLAG(F_DF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "DN "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "UP "); + } + if (ACCESS_FLAG(F_IF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "EI "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "DI "); + } + if (ACCESS_FLAG(F_SF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NG "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "PL "); + } + if (ACCESS_FLAG(F_ZF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "ZR "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NZ "); + } + if (ACCESS_FLAG(F_AF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "AC "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NA "); + } + if (ACCESS_FLAG(F_PF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "PE "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "PO "); + } + if (ACCESS_FLAG(F_CF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "CY "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NC "); + } + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "\n"); +} + +void x86emu_dump_xregs (void) +{ + NV_PRINTF(LEVEL_INFO, "\tEAX=%08x ", M.x86.R_EAX); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "EBX=%08x ", M.x86.R_EBX); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "ECX=%08x ", M.x86.R_ECX); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "EDX=%08x \n", M.x86.R_EDX); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "\tESP=%08x ", M.x86.R_ESP); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "EBP=%08x ", M.x86.R_EBP); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "ESI=%08x ", M.x86.R_ESI); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "EDI=%08x\n", M.x86.R_EDI); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "\tDS=%04x ", M.x86.R_DS); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "ES=%04x ", M.x86.R_ES); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "SS=%04x ", M.x86.R_SS); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "CS=%04x ", M.x86.R_CS); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "EIP=%08x\n\t", M.x86.R_EIP); + if (ACCESS_FLAG(F_OF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "OV "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NV "); + } + if (ACCESS_FLAG(F_DF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "DN "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "UP "); + } + if (ACCESS_FLAG(F_IF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "EI "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "DI "); + } + if (ACCESS_FLAG(F_SF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NG "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "PL "); + } + if (ACCESS_FLAG(F_ZF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "ZR "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NZ "); + } + if (ACCESS_FLAG(F_AF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "AC "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NA "); + } + if (ACCESS_FLAG(F_PF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "PE "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "PO "); + } + if (ACCESS_FLAG(F_CF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "CY "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NC "); + } + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "\n"); +} + +#else + +void x86emu_dump_regs (void) +{ +} + +void x86emu_dump_xregs (void) +{ +} + +int X86EMU_trace_on(void) +{ + return 0; +} + +int X86EMU_trace_off(void) +{ + return 0; +} + +#endif /* X86EMU_DEBUG */ + diff --git a/userspace/sdks/nv570/nvalloc/unix/x86emu/decode.c b/userspace/sdks/nv570/nvalloc/unix/x86emu/decode.c new file mode 100644 index 0000000..a683ce4 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/x86emu/decode.c @@ -0,0 +1,1094 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes subroutines which are related to +* instruction decoding and accessess of immediate data via IP. etc. +* +****************************************************************************/ + + +#include "x86emu/x86emui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Handles any pending asychronous interrupts. +****************************************************************************/ +static void x86emu_intr_handle(void) +{ + u8 intno; + + if (M.x86.intr & INTR_SYNCH) { + intno = M.x86.intno; + if (_X86EMU_intrTab[intno]) { + (*_X86EMU_intrTab[intno])(intno); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(intno * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(intno * 4); + M.x86.intr = 0; + } + } +} + +/**************************************************************************** +PARAMETERS: +intrnum - Interrupt number to raise + +REMARKS: +Raise the specified interrupt to be handled before the execution of the +next instruction. +****************************************************************************/ +void x86emu_intr_raise( + u8 intrnum) +{ + M.x86.intno = intrnum; + M.x86.intr |= INTR_SYNCH; +} + +/**************************************************************************** +REMARKS: +Main execution loop for the emulator. We return from here when the system +halts, which is normally caused by a stack fault when we return from the +original real mode call. +****************************************************************************/ +void X86EMU_exec(void) +{ + u8 op1; + + M.x86.intr = 0; + DB(x86emu_end_instr();) + + for (;;) { +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + /* If debugging, save the IP and CS values. */ + SAVE_IP_CS(M.x86.R_CS, M.x86.R_IP); + INC_DECODED_INST_LEN(1); + if (M.x86.intr) { + if (M.x86.intr & INTR_HALTED) { +DB( if (M.x86.R_SP != 0) { + NV_PRINTF(LEVEL_INFO, "halted\n"); + X86EMU_trace_regs(); + } + else { + if (M.x86.debug) + NV_PRINTF(LEVEL_INFO, + "Service completed successfully\n"); + }) + return; + } + if (((M.x86.intr & INTR_SYNCH) && (M.x86.intno == 0 || M.x86.intno == 2)) || + !ACCESS_FLAG(F_IF)) { + x86emu_intr_handle(); + } + } + op1 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + (*x86emu_optab[op1])(op1); + if (M.x86.debug & DEBUG_EXIT) { + M.x86.debug &= ~DEBUG_EXIT; + return; + } + } +} + +/**************************************************************************** +REMARKS: +Halts the system by setting the halted system flag. +****************************************************************************/ +void X86EMU_halt_sys(void) +{ + M.x86.intr |= INTR_HALTED; +} + +/**************************************************************************** +PARAMETERS: +mod - Mod value from decoded byte +regh - Reg h value from decoded byte +regl - Reg l value from decoded byte + +REMARKS: +Raise the specified interrupt to be handled before the execution of the +next instruction. + +NOTE: Do not inline this function, as (*sys_rdb) is already inline! +****************************************************************************/ +void fetch_decode_modrm( + int *mod, + int *regh, + int *regl) +{ + int fetched; + +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + INC_DECODED_INST_LEN(1); + *mod = (fetched >> 6) & 0x03; + *regh = (fetched >> 3) & 0x07; + *regl = (fetched >> 0) & 0x07; +} + +/**************************************************************************** +RETURNS: +Immediate byte value read from instruction queue + +REMARKS: +This function returns the immediate byte from the instruction queue, and +moves the instruction pointer to the next value. + +NOTE: Do not inline this function, as (*sys_rdb) is already inline! +****************************************************************************/ +u8 fetch_byte_imm(void) +{ + u8 fetched; + +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + INC_DECODED_INST_LEN(1); + return fetched; +} + +/**************************************************************************** +RETURNS: +Immediate word value read from instruction queue + +REMARKS: +This function returns the immediate byte from the instruction queue, and +moves the instruction pointer to the next value. + +NOTE: Do not inline this function, as (*sys_rdw) is already inline! +****************************************************************************/ +u16 fetch_word_imm(void) +{ + u16 fetched; + +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + fetched = (*sys_rdw)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP)); + M.x86.R_IP += 2; + INC_DECODED_INST_LEN(2); + return fetched; +} + +/**************************************************************************** +RETURNS: +Immediate lone value read from instruction queue + +REMARKS: +This function returns the immediate byte from the instruction queue, and +moves the instruction pointer to the next value. + +NOTE: Do not inline this function, as (*sys_rdw) is already inline! +****************************************************************************/ +u32 fetch_long_imm(void) +{ + u32 fetched; + +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + fetched = (*sys_rdl)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP)); + M.x86.R_IP += 4; + INC_DECODED_INST_LEN(4); + return fetched; +} + +/**************************************************************************** +RETURNS: +Value of the default data segment + +REMARKS: +Inline function that returns the default data segment for the current +instruction. + +On the x86 processor, the default segment is not always DS if there is +no segment override. Address modes such as -3[BP] or 10[BP+SI] all refer to +addresses relative to SS (ie: on the stack). So, at the minimum, all +decodings of addressing modes would have to set/clear a bit describing +whether the access is relative to DS or SS. That is the function of the +cpu-state-varible M.x86.mode. There are several potential states: + + repe prefix seen (handled elsewhere) + repne prefix seen (ditto) + + cs segment override + ds segment override + es segment override + fs segment override + gs segment override + ss segment override + + ds/ss select (in absense of override) + +Each of the above 7 items are handled with a bit in the mode field. +****************************************************************************/ +_INLINE u32 get_data_segment(void) +{ +#define GET_SEGMENT(segment) + switch (M.x86.mode & SYSMODE_SEGMASK) { + case 0: /* default case: use ds register */ + case SYSMODE_SEGOVR_DS: + case SYSMODE_SEGOVR_DS | SYSMODE_SEG_DS_SS: + return M.x86.R_DS; + case SYSMODE_SEG_DS_SS: /* non-overridden, use ss register */ + return M.x86.R_SS; + case SYSMODE_SEGOVR_CS: + case SYSMODE_SEGOVR_CS | SYSMODE_SEG_DS_SS: + return M.x86.R_CS; + case SYSMODE_SEGOVR_ES: + case SYSMODE_SEGOVR_ES | SYSMODE_SEG_DS_SS: + return M.x86.R_ES; + case SYSMODE_SEGOVR_FS: + case SYSMODE_SEGOVR_FS | SYSMODE_SEG_DS_SS: + return M.x86.R_FS; + case SYSMODE_SEGOVR_GS: + case SYSMODE_SEGOVR_GS | SYSMODE_SEG_DS_SS: + return M.x86.R_GS; + case SYSMODE_SEGOVR_SS: + case SYSMODE_SEGOVR_SS | SYSMODE_SEG_DS_SS: + return M.x86.R_SS; + default: +#ifdef X86EMU_DEBUG + NV_PRINTF(LEVEL_INFO, + "error: should not happen: multiple overrides.\n"); +#endif + HALT_SYS(); + return 0; + } +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to load data from + +RETURNS: +Byte value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u8 fetch_data_byte( + uint offset) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + return (*sys_rdb)((get_data_segment() << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to load data from + +RETURNS: +Word value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u16 fetch_data_word( + uint offset) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + return (*sys_rdw)((get_data_segment() << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to load data from + +RETURNS: +Long value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u32 fetch_data_long( + uint offset) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + return (*sys_rdl)((get_data_segment() << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to load data from +offset - Offset to load data from + +RETURNS: +Byte value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u8 fetch_data_byte_abs( + uint segment, + uint offset) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + return (*sys_rdb)(((u32)segment << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to load data from +offset - Offset to load data from + +RETURNS: +Word value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u16 fetch_data_word_abs( + uint segment, + uint offset) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + return (*sys_rdw)(((u32)segment << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to load data from +offset - Offset to load data from + +RETURNS: +Long value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u32 fetch_data_long_abs( + uint segment, + uint offset) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + return (*sys_rdl)(((u32)segment << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a word value to an segmented memory location. The segment used is +the current 'default' segment, which may have been overridden. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_byte( + uint offset, + u8 val) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + (*sys_wrb)((get_data_segment() << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a word value to an segmented memory location. The segment used is +the current 'default' segment, which may have been overridden. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_word( + uint offset, + u16 val) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + (*sys_wrw)((get_data_segment() << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a long value to an segmented memory location. The segment used is +the current 'default' segment, which may have been overridden. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_long( + uint offset, + u32 val) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + (*sys_wrl)((get_data_segment() << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to store data at +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a byte value to an absolute memory location. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_byte_abs( + uint segment, + uint offset, + u8 val) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + (*sys_wrb)(((u32)segment << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to store data at +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a word value to an absolute memory location. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_word_abs( + uint segment, + uint offset, + u16 val) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + (*sys_wrw)(((u32)segment << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to store data at +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a long value to an absolute memory location. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_long_abs( + uint segment, + uint offset, + u32 val) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + (*sys_wrl)(((u32)segment << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for byte operands. Also enables the decoding of instructions. +****************************************************************************/ +u8* decode_rm_byte_register( + int reg) +{ + switch (reg) { + case 0: + DECODE_PRINTF("AL"); + return &M.x86.R_AL; + case 1: + DECODE_PRINTF("CL"); + return &M.x86.R_CL; + case 2: + DECODE_PRINTF("DL"); + return &M.x86.R_DL; + case 3: + DECODE_PRINTF("BL"); + return &M.x86.R_BL; + case 4: + DECODE_PRINTF("AH"); + return &M.x86.R_AH; + case 5: + DECODE_PRINTF("CH"); + return &M.x86.R_CH; + case 6: + DECODE_PRINTF("DH"); + return &M.x86.R_DH; + case 7: + DECODE_PRINTF("BH"); + return &M.x86.R_BH; + } + HALT_SYS(); + return NULL; /* NOT REACHED OR REACHED ON ERROR */ +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for word operands. Also enables the decoding of instructions. +****************************************************************************/ +u16* decode_rm_word_register( + int reg) +{ + switch (reg) { + case 0: + DECODE_PRINTF("AX"); + return &M.x86.R_AX; + case 1: + DECODE_PRINTF("CX"); + return &M.x86.R_CX; + case 2: + DECODE_PRINTF("DX"); + return &M.x86.R_DX; + case 3: + DECODE_PRINTF("BX"); + return &M.x86.R_BX; + case 4: + DECODE_PRINTF("SP"); + return &M.x86.R_SP; + case 5: + DECODE_PRINTF("BP"); + return &M.x86.R_BP; + case 6: + DECODE_PRINTF("SI"); + return &M.x86.R_SI; + case 7: + DECODE_PRINTF("DI"); + return &M.x86.R_DI; + } + HALT_SYS(); + return NULL; /* NOTREACHED OR REACHED ON ERROR */ +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for dword operands. Also enables the decoding of instructions. +****************************************************************************/ +u32* decode_rm_long_register( + int reg) +{ + switch (reg) { + case 0: + DECODE_PRINTF("EAX"); + return &M.x86.R_EAX; + case 1: + DECODE_PRINTF("ECX"); + return &M.x86.R_ECX; + case 2: + DECODE_PRINTF("EDX"); + return &M.x86.R_EDX; + case 3: + DECODE_PRINTF("EBX"); + return &M.x86.R_EBX; + case 4: + DECODE_PRINTF("ESP"); + return &M.x86.R_ESP; + case 5: + DECODE_PRINTF("EBP"); + return &M.x86.R_EBP; + case 6: + DECODE_PRINTF("ESI"); + return &M.x86.R_ESI; + case 7: + DECODE_PRINTF("EDI"); + return &M.x86.R_EDI; + } + HALT_SYS(); + return NULL; /* NOTREACHED OR REACHED ON ERROR */ +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for word operands, modified from above for the weirdo +special case of segreg operands. Also enables the decoding of instructions. +****************************************************************************/ +u16* decode_rm_seg_register( + int reg) +{ + switch (reg) { + case 0: + DECODE_PRINTF("ES"); + return &M.x86.R_ES; + case 1: + DECODE_PRINTF("CS"); + return &M.x86.R_CS; + case 2: + DECODE_PRINTF("SS"); + return &M.x86.R_SS; + case 3: + DECODE_PRINTF("DS"); + return &M.x86.R_DS; + case 4: + DECODE_PRINTF("FS"); + return &M.x86.R_FS; + case 5: + DECODE_PRINTF("GS"); + return &M.x86.R_GS; + case 6: + case 7: + DECODE_PRINTF("ILLEGAL SEGREG"); + break; + } + HALT_SYS(); + return NULL; /* NOT REACHED OR REACHED ON ERROR */ +} + +/* + * + * return offset from the SIB Byte + */ +u32 decode_sib_address(int sib, int mod) +{ + u32 base = 0, i = 0, scale = 1; + + switch(sib & 0x07) { + case 0: + DECODE_PRINTF("[EAX]"); + base = M.x86.R_EAX; + break; + case 1: + DECODE_PRINTF("[ECX]"); + base = M.x86.R_ECX; + break; + case 2: + DECODE_PRINTF("[EDX]"); + base = M.x86.R_EDX; + break; + case 3: + DECODE_PRINTF("[EBX]"); + base = M.x86.R_EBX; + break; + case 4: + DECODE_PRINTF("[ESP]"); + base = M.x86.R_ESP; + M.x86.mode |= SYSMODE_SEG_DS_SS; + break; + case 5: + if (mod == 0) { + base = fetch_long_imm(); + DECODE_PRINTF2("%08x", base); + } else { + DECODE_PRINTF("[EBP]"); + base = M.x86.R_ESP; + M.x86.mode |= SYSMODE_SEG_DS_SS; + } + break; + case 6: + DECODE_PRINTF("[ESI]"); + base = M.x86.R_ESI; + break; + case 7: + DECODE_PRINTF("[EDI]"); + base = M.x86.R_EDI; + break; + } + switch ((sib >> 3) & 0x07) { + case 0: + DECODE_PRINTF("[EAX"); + i = M.x86.R_EAX; + break; + case 1: + DECODE_PRINTF("[ECX"); + i = M.x86.R_ECX; + break; + case 2: + DECODE_PRINTF("[EDX"); + i = M.x86.R_EDX; + break; + case 3: + DECODE_PRINTF("[EBX"); + i = M.x86.R_EBX; + break; + case 4: + i = 0; + break; + case 5: + DECODE_PRINTF("[EBP"); + i = M.x86.R_EBP; + break; + case 6: + DECODE_PRINTF("[ESI"); + i = M.x86.R_ESI; + break; + case 7: + DECODE_PRINTF("[EDI"); + i = M.x86.R_EDI; + break; + } + scale = 1 << ((sib >> 6) & 0x03); + if (((sib >> 3) & 0x07) != 4) { + if (scale == 1) { + DECODE_PRINTF("]"); + } else { + DECODE_PRINTF2("*%d]", scale); + } + } + return base + (i * scale); +} + +/**************************************************************************** +PARAMETERS: +rm - RM value to decode + +RETURNS: +Offset in memory for the address decoding + +REMARKS: +Return the offset given by mod=00 addressing. Also enables the +decoding of instructions. + +NOTE: The code which specifies the corresponding segment (ds vs ss) + below in the case of [BP+..]. The assumption here is that at the + point that this subroutine is called, the bit corresponding to + SYSMODE_SEG_DS_SS will be zero. After every instruction + except the segment override instructions, this bit (as well + as any bits indicating segment overrides) will be clear. So + if a SS access is needed, set this bit. Otherwise, DS access + occurs (unless any of the segment override bits are set). +****************************************************************************/ +u32 decode_rm00_address( + int rm) +{ + u32 offset; + int sib; + + if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + /* 32-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF("[EAX]"); + return M.x86.R_EAX; + case 1: + DECODE_PRINTF("[ECX]"); + return M.x86.R_ECX; + case 2: + DECODE_PRINTF("[EDX]"); + return M.x86.R_EDX; + case 3: + DECODE_PRINTF("[EBX]"); + return M.x86.R_EBX; + case 4: + sib = fetch_byte_imm(); + return decode_sib_address(sib, 0); + case 5: + offset = fetch_long_imm(); + DECODE_PRINTF2("[%08x]", offset); + return offset; + case 6: + DECODE_PRINTF("[ESI]"); + return M.x86.R_ESI; + case 7: + DECODE_PRINTF("[EDI]"); + return M.x86.R_EDI; + } + HALT_SYS(); + } else { + /* 16-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF("[BX+SI]"); + return (M.x86.R_BX + M.x86.R_SI) & 0xffff; + case 1: + DECODE_PRINTF("[BX+DI]"); + return (M.x86.R_BX + M.x86.R_DI) & 0xffff; + case 2: + DECODE_PRINTF("[BP+SI]"); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI) & 0xffff; + case 3: + DECODE_PRINTF("[BP+DI]"); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI) & 0xffff; + case 4: + DECODE_PRINTF("[SI]"); + return M.x86.R_SI; + case 5: + DECODE_PRINTF("[DI]"); + return M.x86.R_DI; + case 6: + offset = fetch_word_imm(); + DECODE_PRINTF2("[%04x]", offset); + return offset; + case 7: + DECODE_PRINTF("[BX]"); + return M.x86.R_BX; + } + HALT_SYS(); + } + return 0; +} + +/**************************************************************************** +PARAMETERS: +rm - RM value to decode + +RETURNS: +Offset in memory for the address decoding + +REMARKS: +Return the offset given by mod=01 addressing. Also enables the +decoding of instructions. +****************************************************************************/ +u32 decode_rm01_address( + int rm) +{ + int displacement = 0; + int sib; + + /* Fetch disp8 if no SIB byte */ + if (!((M.x86.mode & SYSMODE_PREFIX_ADDR) && (rm == 4))) + displacement = (s8)fetch_byte_imm(); + + if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + /* 32-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF2("%d[EAX]", displacement); + return M.x86.R_EAX + displacement; + case 1: + DECODE_PRINTF2("%d[ECX]", displacement); + return M.x86.R_ECX + displacement; + case 2: + DECODE_PRINTF2("%d[EDX]", displacement); + return M.x86.R_EDX + displacement; + case 3: + DECODE_PRINTF2("%d[EBX]", displacement); + return M.x86.R_EBX + displacement; + case 4: + sib = fetch_byte_imm(); + displacement = (s8)fetch_byte_imm(); + DECODE_PRINTF2("%d", displacement); + return decode_sib_address(sib, 1) + displacement; + case 5: + DECODE_PRINTF2("%d[EBP]", displacement); + return M.x86.R_EBP + displacement; + case 6: + DECODE_PRINTF2("%d[ESI]", displacement); + return M.x86.R_ESI + displacement; + case 7: + DECODE_PRINTF2("%d[EDI]", displacement); + return M.x86.R_EDI + displacement; + } + HALT_SYS(); + } else { + /* 16-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF2("%d[BX+SI]", displacement); + return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; + case 1: + DECODE_PRINTF2("%d[BX+DI]", displacement); + return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; + case 2: + DECODE_PRINTF2("%d[BP+SI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; + case 3: + DECODE_PRINTF2("%d[BP+DI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; + case 4: + DECODE_PRINTF2("%d[SI]", displacement); + return (M.x86.R_SI + displacement) & 0xffff; + case 5: + DECODE_PRINTF2("%d[DI]", displacement); + return (M.x86.R_DI + displacement) & 0xffff; + case 6: + DECODE_PRINTF2("%d[BP]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + displacement) & 0xffff; + case 7: + DECODE_PRINTF2("%d[BX]", displacement); + return (M.x86.R_BX + displacement) & 0xffff; + } + HALT_SYS(); + } + return 0; /* SHOULD NOT HAPPEN */ +} + +/**************************************************************************** +PARAMETERS: +rm - RM value to decode + +RETURNS: +Offset in memory for the address decoding + +REMARKS: +Return the offset given by mod=10 addressing. Also enables the +decoding of instructions. +****************************************************************************/ +u32 decode_rm10_address( + int rm) +{ + u32 displacement = 0; + int sib; + + /* Fetch disp16 if 16-bit addr mode */ + if (!(M.x86.mode & SYSMODE_PREFIX_ADDR)) + displacement = (u16)fetch_word_imm(); + else { + /* Fetch disp32 if no SIB byte */ + if (rm != 4) + displacement = (u32)fetch_long_imm(); + } + + if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + /* 32-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF2("%08x[EAX]", displacement); + return M.x86.R_EAX + displacement; + case 1: + DECODE_PRINTF2("%08x[ECX]", displacement); + return M.x86.R_ECX + displacement; + case 2: + DECODE_PRINTF2("%08x[EDX]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return M.x86.R_EDX + displacement; + case 3: + DECODE_PRINTF2("%08x[EBX]", displacement); + return M.x86.R_EBX + displacement; + case 4: + sib = fetch_byte_imm(); + displacement = (u32)fetch_long_imm(); + DECODE_PRINTF2("%08x", displacement); + return decode_sib_address(sib, 2) + displacement; + break; + case 5: + DECODE_PRINTF2("%08x[EBP]", displacement); + return M.x86.R_EBP + displacement; + case 6: + DECODE_PRINTF2("%08x[ESI]", displacement); + return M.x86.R_ESI + displacement; + case 7: + DECODE_PRINTF2("%08x[EDI]", displacement); + return M.x86.R_EDI + displacement; + } + HALT_SYS(); + } else { + /* 16-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF2("%04x[BX+SI]", displacement); + return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; + case 1: + DECODE_PRINTF2("%04x[BX+DI]", displacement); + return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; + case 2: + DECODE_PRINTF2("%04x[BP+SI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; + case 3: + DECODE_PRINTF2("%04x[BP+DI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; + case 4: + DECODE_PRINTF2("%04x[SI]", displacement); + return (M.x86.R_SI + displacement) & 0xffff; + case 5: + DECODE_PRINTF2("%04x[DI]", displacement); + return (M.x86.R_DI + displacement) & 0xffff; + case 6: + DECODE_PRINTF2("%04x[BP]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + displacement) & 0xffff; + case 7: + DECODE_PRINTF2("%04x[BX]", displacement); + return (M.x86.R_BX + displacement) & 0xffff; + } + HALT_SYS(); + } + return 0; + /*NOTREACHED */ +} diff --git a/userspace/sdks/nv570/nvalloc/unix/x86emu/fpu.c b/userspace/sdks/nv570/nvalloc/unix/x86emu/fpu.c new file mode 100644 index 0000000..0a21c99 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/x86emu/fpu.c @@ -0,0 +1,965 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file contains the code to implement the decoding and +* emulation of the FPU instructions. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/* opcode=0xd8 */ +void x86emuOp_esc_coprocess_d8(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("ESC D8\n"); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef X86EMU_DEBUG + +static char *x86emu_fpu_op_d9_tab[] = { + "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ", + "FLDENV\t", "FLDCW\t", "FSTENV\t", "FSTCW\t", + + "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ", + "FLDENV\t", "FLDCW\t", "FSTENV\t", "FSTCW\t", + + "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ", + "FLDENV\t", "FLDCW\t", "FSTENV\t", "FSTCW\t", +}; + +static char *x86emu_fpu_op_d9_tab1[] = { + "FLD\t", "FLD\t", "FLD\t", "FLD\t", + "FLD\t", "FLD\t", "FLD\t", "FLD\t", + + "FXCH\t", "FXCH\t", "FXCH\t", "FXCH\t", + "FXCH\t", "FXCH\t", "FXCH\t", "FXCH\t", + + "FNOP", "ESC_D9", "ESC_D9", "ESC_D9", + "ESC_D9", "ESC_D9", "ESC_D9", "ESC_D9", + + "FSTP\t", "FSTP\t", "FSTP\t", "FSTP\t", + "FSTP\t", "FSTP\t", "FSTP\t", "FSTP\t", + + "FCHS", "FABS", "ESC_D9", "ESC_D9", + "FTST", "FXAM", "ESC_D9", "ESC_D9", + + "FLD1", "FLDL2T", "FLDL2E", "FLDPI", + "FLDLG2", "FLDLN2", "FLDZ", "ESC_D9", + + "F2XM1", "FYL2X", "FPTAN", "FPATAN", + "FXTRACT", "ESC_D9", "FDECSTP", "FINCSTP", + + "FPREM", "FYL2XP1", "FSQRT", "ESC_D9", + "FRNDINT", "FSCALE", "ESC_D9", "ESC_D9", +}; + +#endif /* X86EMU_DEBUG */ + +/* opcode=0xd9 */ +void x86emuOp_esc_coprocess_d9(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset = 0; + u8 stkelem = 0; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (mod != 3) { + DECODE_PRINTINSTR32(x86emu_fpu_op_d9_tab, mod, rh, rl); + } else { + DECODE_PRINTF(x86emu_fpu_op_d9_tab1[(rh << 3) + rl]); + } +#endif + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + if (rh < 4) { + DECODE_PRINTF2("ST(%d)\n", stkelem); + } else { + DECODE_PRINTF("\n"); + } + break; + } +#ifdef X86EMU_FPU_PRESENT + /* execute */ + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_fld(X86EMU_FPU_STKTOP, stkelem); + break; + case 1: + x86emu_fpu_R_fxch(X86EMU_FPU_STKTOP, stkelem); + break; + case 2: + switch (rl) { + case 0: + x86emu_fpu_R_nop(); + break; + default: + x86emu_fpu_illegal(); + break; + } + case 3: + x86emu_fpu_R_fstp(X86EMU_FPU_STKTOP, stkelem); + break; + case 4: + switch (rl) { + case 0: + x86emu_fpu_R_fchs(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fabs(X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_ftst(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fxam(X86EMU_FPU_STKTOP); + break; + default: + /* 2,3,6,7 */ + x86emu_fpu_illegal(); + break; + } + break; + + case 5: + switch (rl) { + case 0: + x86emu_fpu_R_fld1(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fldl2t(X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fldl2e(X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_R_fldpi(X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_fldlg2(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fldln2(X86EMU_FPU_STKTOP); + break; + case 6: + x86emu_fpu_R_fldz(X86EMU_FPU_STKTOP); + break; + default: + /* 7 */ + x86emu_fpu_illegal(); + break; + } + break; + + case 6: + switch (rl) { + case 0: + x86emu_fpu_R_f2xm1(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fyl2x(X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fptan(X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_R_fpatan(X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_fxtract(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_illegal(); + break; + case 6: + x86emu_fpu_R_decstp(); + break; + case 7: + x86emu_fpu_R_incstp(); + break; + } + break; + + case 7: + switch (rl) { + case 0: + x86emu_fpu_R_fprem(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fyl2xp1(X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fsqrt(X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_illegal(); + break; + case 4: + x86emu_fpu_R_frndint(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fscale(X86EMU_FPU_STKTOP); + break; + case 6: + case 7: + default: + x86emu_fpu_illegal(); + break; + } + break; + + default: + switch (rh) { + case 0: + x86emu_fpu_M_fld(X86EMU_FPU_FLOAT, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fst(X86EMU_FPU_FLOAT, destoffset); + break; + case 3: + x86emu_fpu_M_fstp(X86EMU_FPU_FLOAT, destoffset); + break; + case 4: + x86emu_fpu_M_fldenv(X86EMU_FPU_WORD, destoffset); + break; + case 5: + x86emu_fpu_M_fldcw(X86EMU_FPU_WORD, destoffset); + break; + case 6: + x86emu_fpu_M_fstenv(X86EMU_FPU_WORD, destoffset); + break; + case 7: + x86emu_fpu_M_fstcw(X86EMU_FPU_WORD, destoffset); + break; + } + } + } +#else + (void)destoffset; + (void)stkelem; +#endif /* X86EMU_FPU_PRESENT */ + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef X86EMU_DEBUG + +char *x86emu_fpu_op_da_tab[] = { + "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ", + "FICOMP\tDWORD PTR ", + "FISUB\tDWORD PTR ", "FISUBR\tDWORD PTR ", "FIDIV\tDWORD PTR ", + "FIDIVR\tDWORD PTR ", + + "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ", + "FICOMP\tDWORD PTR ", + "FISUB\tDWORD PTR ", "FISUBR\tDWORD PTR ", "FIDIV\tDWORD PTR ", + "FIDIVR\tDWORD PTR ", + + "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ", + "FICOMP\tDWORD PTR ", + "FISUB\tDWORD PTR ", "FISUBR\tDWORD PTR ", "FIDIV\tDWORD PTR ", + "FIDIVR\tDWORD PTR ", + + "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", + "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", +}; + +#endif /* X86EMU_DEBUG */ + +/* opcode=0xda */ +void x86emuOp_esc_coprocess_da(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset = 0; + u8 stkelem = 0; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_da_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + switch (mod) { + case 3: + x86emu_fpu_illegal(); + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_iadd(X86EMU_FPU_SHORT, destoffset); + break; + case 1: + x86emu_fpu_M_imul(X86EMU_FPU_SHORT, destoffset); + break; + case 2: + x86emu_fpu_M_icom(X86EMU_FPU_SHORT, destoffset); + break; + case 3: + x86emu_fpu_M_icomp(X86EMU_FPU_SHORT, destoffset); + break; + case 4: + x86emu_fpu_M_isub(X86EMU_FPU_SHORT, destoffset); + break; + case 5: + x86emu_fpu_M_isubr(X86EMU_FPU_SHORT, destoffset); + break; + case 6: + x86emu_fpu_M_idiv(X86EMU_FPU_SHORT, destoffset); + break; + case 7: + x86emu_fpu_M_idivr(X86EMU_FPU_SHORT, destoffset); + break; + } + } +#else + (void)destoffset; + (void)stkelem; +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef X86EMU_DEBUG + +char *x86emu_fpu_op_db_tab[] = { + "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ", + "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ", + + "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ", + "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ", + + "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ", + "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ", +}; + +#endif /* X86EMU_DEBUG */ + +/* opcode=0xdb */ +void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset = 0; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (mod != 3) { + DECODE_PRINTINSTR32(x86emu_fpu_op_db_tab, mod, rh, rl); + } else if (rh == 4) { /* === 11 10 0 nnn */ + switch (rl) { + case 0: + DECODE_PRINTF("FENI\n"); + break; + case 1: + DECODE_PRINTF("FDISI\n"); + break; + case 2: + DECODE_PRINTF("FCLEX\n"); + break; + case 3: + DECODE_PRINTF("FINIT\n"); + break; + } + } else { + DECODE_PRINTF2("ESC_DB %0x\n", (mod << 6) + (rh << 3) + (rl)); + } +#endif /* X86EMU_DEBUG */ + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + break; + case 1: + destoffset = decode_rm01_address(rl); + break; + case 2: + destoffset = decode_rm10_address(rl); + break; + case 3: /* register to register */ + break; + } +#ifdef X86EMU_FPU_PRESENT + /* execute */ + switch (mod) { + case 3: + switch (rh) { + case 4: + switch (rl) { + case 0: + x86emu_fpu_R_feni(); + break; + case 1: + x86emu_fpu_R_fdisi(); + break; + case 2: + x86emu_fpu_R_fclex(); + break; + case 3: + x86emu_fpu_R_finit(); + break; + default: + x86emu_fpu_illegal(); + break; + } + break; + default: + x86emu_fpu_illegal(); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fild(X86EMU_FPU_SHORT, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fist(X86EMU_FPU_SHORT, destoffset); + break; + case 3: + x86emu_fpu_M_fistp(X86EMU_FPU_SHORT, destoffset); + break; + case 4: + x86emu_fpu_illegal(); + break; + case 5: + x86emu_fpu_M_fld(X86EMU_FPU_LDBL, destoffset); + break; + case 6: + x86emu_fpu_illegal(); + break; + case 7: + x86emu_fpu_M_fstp(X86EMU_FPU_LDBL, destoffset); + break; + } + } +#else + (void)destoffset; +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef X86EMU_DEBUG +char *x86emu_fpu_op_dc_tab[] = { + "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ", + "FCOMP\tQWORD PTR ", + "FSUB\tQWORD PTR ", "FSUBR\tQWORD PTR ", "FDIV\tQWORD PTR ", + "FDIVR\tQWORD PTR ", + + "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ", + "FCOMP\tQWORD PTR ", + "FSUB\tQWORD PTR ", "FSUBR\tQWORD PTR ", "FDIV\tQWORD PTR ", + "FDIVR\tQWORD PTR ", + + "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ", + "FCOMP\tQWORD PTR ", + "FSUB\tQWORD PTR ", "FSUBR\tQWORD PTR ", "FDIV\tQWORD PTR ", + "FDIVR\tQWORD PTR ", + + "FADD\t", "FMUL\t", "FCOM\t", "FCOMP\t", + "FSUBR\t", "FSUB\t", "FDIVR\t", "FDIV\t", +}; +#endif /* X86EMU_DEBUG */ + +/* opcode=0xdc */ +void x86emuOp_esc_coprocess_dc(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset = 0; + u8 stkelem = 0; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_dc_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + /* execute */ + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_fadd(stkelem, X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fmul(stkelem, X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fcom(stkelem, X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_R_fcomp(stkelem, X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_fsubr(stkelem, X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fsub(stkelem, X86EMU_FPU_STKTOP); + break; + case 6: + x86emu_fpu_R_fdivr(stkelem, X86EMU_FPU_STKTOP); + break; + case 7: + x86emu_fpu_R_fdiv(stkelem, X86EMU_FPU_STKTOP); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fadd(X86EMU_FPU_DOUBLE, destoffset); + break; + case 1: + x86emu_fpu_M_fmul(X86EMU_FPU_DOUBLE, destoffset); + break; + case 2: + x86emu_fpu_M_fcom(X86EMU_FPU_DOUBLE, destoffset); + break; + case 3: + x86emu_fpu_M_fcomp(X86EMU_FPU_DOUBLE, destoffset); + break; + case 4: + x86emu_fpu_M_fsub(X86EMU_FPU_DOUBLE, destoffset); + break; + case 5: + x86emu_fpu_M_fsubr(X86EMU_FPU_DOUBLE, destoffset); + break; + case 6: + x86emu_fpu_M_fdiv(X86EMU_FPU_DOUBLE, destoffset); + break; + case 7: + x86emu_fpu_M_fdivr(X86EMU_FPU_DOUBLE, destoffset); + break; + } + } +#else + (void)destoffset; + (void)stkelem; +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef X86EMU_DEBUG + +static char *x86emu_fpu_op_dd_tab[] = { + "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ", + "FRSTOR\t", "ESC_DD\t2D,", "FSAVE\t", "FSTSW\t", + + "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ", + "FRSTOR\t", "ESC_DD\t2D,", "FSAVE\t", "FSTSW\t", + + "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ", + "FRSTOR\t", "ESC_DD\t2D,", "FSAVE\t", "FSTSW\t", + + "FFREE\t", "FXCH\t", "FST\t", "FSTP\t", + "ESC_DD\t2C,", "ESC_DD\t2D,", "ESC_DD\t2E,", "ESC_DD\t2F,", +}; + +#endif /* X86EMU_DEBUG */ + +/* opcode=0xdd */ +void x86emuOp_esc_coprocess_dd(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset = 0; + u8 stkelem = 0; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_dd_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_ffree(stkelem); + break; + case 1: + x86emu_fpu_R_fxch(stkelem); + break; + case 2: + x86emu_fpu_R_fst(stkelem); /* register version */ + break; + case 3: + x86emu_fpu_R_fstp(stkelem); /* register version */ + break; + default: + x86emu_fpu_illegal(); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fld(X86EMU_FPU_DOUBLE, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fst(X86EMU_FPU_DOUBLE, destoffset); + break; + case 3: + x86emu_fpu_M_fstp(X86EMU_FPU_DOUBLE, destoffset); + break; + case 4: + x86emu_fpu_M_frstor(X86EMU_FPU_WORD, destoffset); + break; + case 5: + x86emu_fpu_illegal(); + break; + case 6: + x86emu_fpu_M_fsave(X86EMU_FPU_WORD, destoffset); + break; + case 7: + x86emu_fpu_M_fstsw(X86EMU_FPU_WORD, destoffset); + break; + } + } +#else + (void)destoffset; + (void)stkelem; +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef X86EMU_DEBUG + +static char *x86emu_fpu_op_de_tab[] = +{ + "FIADD\tWORD PTR ", "FIMUL\tWORD PTR ", "FICOM\tWORD PTR ", + "FICOMP\tWORD PTR ", + "FISUB\tWORD PTR ", "FISUBR\tWORD PTR ", "FIDIV\tWORD PTR ", + "FIDIVR\tWORD PTR ", + + "FIADD\tWORD PTR ", "FIMUL\tWORD PTR ", "FICOM\tWORD PTR ", + "FICOMP\tWORD PTR ", + "FISUB\tWORD PTR ", "FISUBR\tWORD PTR ", "FIDIV\tWORD PTR ", + "FIDIVR\tWORD PTR ", + + "FIADD\tWORD PTR ", "FIMUL\tWORD PTR ", "FICOM\tWORD PTR ", + "FICOMP\tWORD PTR ", + "FISUB\tWORD PTR ", "FISUBR\tWORD PTR ", "FIDIV\tWORD PTR ", + "FIDIVR\tWORD PTR ", + + "FADDP\t", "FMULP\t", "FCOMP\t", "FCOMPP\t", + "FSUBRP\t", "FSUBP\t", "FDIVRP\t", "FDIVP\t", +}; + +#endif /* X86EMU_DEBUG */ + +/* opcode=0xde */ +void x86emuOp_esc_coprocess_de(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset = 0; + u8 stkelem = 0; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_de_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_faddp(stkelem, X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fmulp(stkelem, X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fcomp(stkelem, X86EMU_FPU_STKTOP); + break; + case 3: + if (stkelem == 1) + x86emu_fpu_R_fcompp(stkelem, X86EMU_FPU_STKTOP); + else + x86emu_fpu_illegal(); + break; + case 4: + x86emu_fpu_R_fsubrp(stkelem, X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fsubp(stkelem, X86EMU_FPU_STKTOP); + break; + case 6: + x86emu_fpu_R_fdivrp(stkelem, X86EMU_FPU_STKTOP); + break; + case 7: + x86emu_fpu_R_fdivp(stkelem, X86EMU_FPU_STKTOP); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fiadd(X86EMU_FPU_WORD, destoffset); + break; + case 1: + x86emu_fpu_M_fimul(X86EMU_FPU_WORD, destoffset); + break; + case 2: + x86emu_fpu_M_ficom(X86EMU_FPU_WORD, destoffset); + break; + case 3: + x86emu_fpu_M_ficomp(X86EMU_FPU_WORD, destoffset); + break; + case 4: + x86emu_fpu_M_fisub(X86EMU_FPU_WORD, destoffset); + break; + case 5: + x86emu_fpu_M_fisubr(X86EMU_FPU_WORD, destoffset); + break; + case 6: + x86emu_fpu_M_fidiv(X86EMU_FPU_WORD, destoffset); + break; + case 7: + x86emu_fpu_M_fidivr(X86EMU_FPU_WORD, destoffset); + break; + } + } +#else + (void)destoffset; + (void)stkelem; +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef X86EMU_DEBUG + +static char *x86emu_fpu_op_df_tab[] = { + /* mod == 00 */ + "FILD\tWORD PTR ", "ESC_DF\t39\n", "FIST\tWORD PTR ", "FISTP\tWORD PTR ", + "FBLD\tTBYTE PTR ", "FILD\tQWORD PTR ", "FBSTP\tTBYTE PTR ", + "FISTP\tQWORD PTR ", + + /* mod == 01 */ + "FILD\tWORD PTR ", "ESC_DF\t39 ", "FIST\tWORD PTR ", "FISTP\tWORD PTR ", + "FBLD\tTBYTE PTR ", "FILD\tQWORD PTR ", "FBSTP\tTBYTE PTR ", + "FISTP\tQWORD PTR ", + + /* mod == 10 */ + "FILD\tWORD PTR ", "ESC_DF\t39 ", "FIST\tWORD PTR ", "FISTP\tWORD PTR ", + "FBLD\tTBYTE PTR ", "FILD\tQWORD PTR ", "FBSTP\tTBYTE PTR ", + "FISTP\tQWORD PTR ", + + /* mod == 11 */ + "FFREE\t", "FXCH\t", "FST\t", "FSTP\t", + "ESC_DF\t3C,", "ESC_DF\t3D,", "ESC_DF\t3E,", "ESC_DF\t3F," +}; + +#endif /* X86EMU_DEBUG */ + +/* opcode=0xdf */ +void x86emuOp_esc_coprocess_df(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset = 0; + u8 stkelem = 0; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_df_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d)\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_ffree(stkelem); + break; + case 1: + x86emu_fpu_R_fxch(stkelem); + break; + case 2: + x86emu_fpu_R_fst(stkelem); /* register version */ + break; + case 3: + x86emu_fpu_R_fstp(stkelem); /* register version */ + break; + default: + x86emu_fpu_illegal(); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fild(X86EMU_FPU_WORD, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fist(X86EMU_FPU_WORD, destoffset); + break; + case 3: + x86emu_fpu_M_fistp(X86EMU_FPU_WORD, destoffset); + break; + case 4: + x86emu_fpu_M_fbld(X86EMU_FPU_BSD, destoffset); + break; + case 5: + x86emu_fpu_M_fild(X86EMU_FPU_LONG, destoffset); + break; + case 6: + x86emu_fpu_M_fbstp(X86EMU_FPU_BSD, destoffset); + break; + case 7: + x86emu_fpu_M_fistp(X86EMU_FPU_LONG, destoffset); + break; + } + } +#else + (void)destoffset; + (void)stkelem; +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} diff --git a/userspace/sdks/nv570/nvalloc/unix/x86emu/ops.c b/userspace/sdks/nv570/nvalloc/unix/x86emu/ops.c new file mode 100644 index 0000000..52b97b4 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/x86emu/ops.c @@ -0,0 +1,11761 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes subroutines to implement the decoding +* and emulation of all the x86 processor instructions. +* +* There are approximately 250 subroutines in here, which correspond +* to the 256 byte-"opcodes" found on the 8086. The table which +* dispatches this is found in the files optab.[ch]. +* +* Each opcode proc has a comment preceeding it which gives it's table +* address. Several opcodes are missing (undefined) in the table. +* +* Each proc includes information for decoding (DECODE_PRINTF and +* DECODE_PRINTF2), debugging (TRACE_REGS, SINGLE_STEP), and misc +* functions (START_OF_INSTR, END_OF_INSTR). +* +* Many of the procedures are *VERY* similar in coding. This has +* allowed for a very large amount of code to be generated in a fairly +* short amount of time (i.e. cut, paste, and modify). The result is +* that much of the code below could have been folded into subroutines +* for a large reduction in size of this file. The downside would be +* that there would be a penalty in execution speed. The file could +* also have been *MUCH* larger by inlining certain functions which +* were called. This could have resulted even faster execution. The +* prime directive I used to decide whether to inline the code or to +* modularize it, was basically: 1) no unnecessary subroutine calls, +* 2) no routines more than about 200 lines in size, and 3) modularize +* any code that I might not get right the first time. The fetch_* +* subroutines fall into the latter category. The The decode_* fall +* into the second category. The coding of the "switch(mod){ .... }" +* in many of the subroutines below falls into the first category. +* Especially, the coding of {add,and,or,sub,...}_{byte,word} +* subroutines are an especially glaring case of the third guideline. +* Since so much of the code is cloned from other modules (compare +* opcode #00 to opcode #01), making the basic operations subroutine +* calls is especially important; otherwise mistakes in coding an +* "add" would represent a nightmare in maintenance. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +PARAMETERS: +op1 - Instruction op code + +REMARKS: +Handles illegal opcodes. +****************************************************************************/ +static void x86emuOp_illegal_op( + u8 op1) +{ + START_OF_INSTR(); + if (M.x86.R_SP != 0) { + DECODE_PRINTF("ILLEGAL X86 OPCODE\n"); + TRACE_REGS(); + DB( NV_PRINTF(LEVEL_INFO, "%04x:%04x: %02X ILLEGAL X86 OPCODE!\n", + M.x86.R_CS, M.x86.R_IP - 1, op1);) + HALT_SYS(); + } + else { + /* If we get here, it means the stack pointer is back to zero + * so we are just returning from an emulator service call + * so therte is no need to display an error message. We trap + * the emulator with an 0xF1 opcode to finish the service + * call. + */ + X86EMU_halt_sys(); + } + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x00 +****************************************************************************/ +static void x86emuOp_add_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 *destreg, *srcreg; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x01 +****************************************************************************/ +static void x86emuOp_add_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x02 +****************************************************************************/ +static void x86emuOp_add_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x03 +****************************************************************************/ +static void x86emuOp_add_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x04 +****************************************************************************/ +static void x86emuOp_add_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = add_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x05 +****************************************************************************/ +static void x86emuOp_add_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("ADD\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("ADD\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = add_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = add_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x06 +****************************************************************************/ +static void x86emuOp_push_ES(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tES\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_ES); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x07 +****************************************************************************/ +static void x86emuOp_pop_ES(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tES\n"); + TRACE_AND_STEP(); + M.x86.R_ES = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x08 +****************************************************************************/ +static void x86emuOp_or_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("OR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x09 +****************************************************************************/ +static void x86emuOp_or_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("OR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0a +****************************************************************************/ +static void x86emuOp_or_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("OR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0b +****************************************************************************/ +static void x86emuOp_or_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("OR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0c +****************************************************************************/ +static void x86emuOp_or_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("OR\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = or_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0d +****************************************************************************/ +static void x86emuOp_or_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("OR\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("OR\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = or_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = or_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0e +****************************************************************************/ +static void x86emuOp_push_CS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tCS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f. Escape for two-byte opcode (286 or better) +****************************************************************************/ +static void x86emuOp_two_byte(u8 X86EMU_UNUSED(op1)) +{ + u8 op2 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + INC_DECODED_INST_LEN(1); + (*x86emu_optab2[op2])(op2); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x10 +****************************************************************************/ +static void x86emuOp_adc_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x11 +****************************************************************************/ +static void x86emuOp_adc_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x12 +****************************************************************************/ +static void x86emuOp_adc_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x13 +****************************************************************************/ +static void x86emuOp_adc_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x14 +****************************************************************************/ +static void x86emuOp_adc_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = adc_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x15 +****************************************************************************/ +static void x86emuOp_adc_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("ADC\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("ADC\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = adc_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = adc_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x16 +****************************************************************************/ +static void x86emuOp_push_SS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tSS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_SS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x17 +****************************************************************************/ +static void x86emuOp_pop_SS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tSS\n"); + TRACE_AND_STEP(); + M.x86.R_SS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x18 +****************************************************************************/ +static void x86emuOp_sbb_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x19 +****************************************************************************/ +static void x86emuOp_sbb_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1a +****************************************************************************/ +static void x86emuOp_sbb_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1b +****************************************************************************/ +static void x86emuOp_sbb_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1c +****************************************************************************/ +static void x86emuOp_sbb_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = sbb_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1d +****************************************************************************/ +static void x86emuOp_sbb_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("SBB\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("SBB\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = sbb_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = sbb_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1e +****************************************************************************/ +static void x86emuOp_push_DS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tDS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_DS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1f +****************************************************************************/ +static void x86emuOp_pop_DS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tDS\n"); + TRACE_AND_STEP(); + M.x86.R_DS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x20 +****************************************************************************/ +static void x86emuOp_and_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("AND\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x21 +****************************************************************************/ +static void x86emuOp_and_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("AND\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x22 +****************************************************************************/ +static void x86emuOp_and_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("AND\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x23 +****************************************************************************/ +static void x86emuOp_and_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("AND\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, srcval); + break; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, srcval); + break; + } + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x24 +****************************************************************************/ +static void x86emuOp_and_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("AND\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = and_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x25 +****************************************************************************/ +static void x86emuOp_and_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("AND\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("AND\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = and_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = and_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x26 +****************************************************************************/ +static void x86emuOp_segovr_ES(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("ES:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_ES; + /* + * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4 + * opcode subroutines we do not want to do this. + */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x27 +****************************************************************************/ +static void x86emuOp_daa(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("DAA\n"); + TRACE_AND_STEP(); + M.x86.R_AL = daa_byte(M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x28 +****************************************************************************/ +static void x86emuOp_sub_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x29 +****************************************************************************/ +static void x86emuOp_sub_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2a +****************************************************************************/ +static void x86emuOp_sub_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2b +****************************************************************************/ +static void x86emuOp_sub_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2c +****************************************************************************/ +static void x86emuOp_sub_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = sub_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2d +****************************************************************************/ +static void x86emuOp_sub_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("SUB\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("SUB\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = sub_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = sub_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2e +****************************************************************************/ +static void x86emuOp_segovr_CS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("CS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_CS; + /* note no DECODE_CLEAR_SEGOVR here. */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2f +****************************************************************************/ +static void x86emuOp_das(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("DAS\n"); + TRACE_AND_STEP(); + M.x86.R_AL = das_byte(M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x30 +****************************************************************************/ +static void x86emuOp_xor_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x31 +****************************************************************************/ +static void x86emuOp_xor_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x32 +****************************************************************************/ +static void x86emuOp_xor_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x33 +****************************************************************************/ +static void x86emuOp_xor_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x34 +****************************************************************************/ +static void x86emuOp_xor_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = xor_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x35 +****************************************************************************/ +static void x86emuOp_xor_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XOR\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("XOR\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = xor_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = xor_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x36 +****************************************************************************/ +static void x86emuOp_segovr_SS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("SS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_SS; + /* no DECODE_CLEAR_SEGOVR ! */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x37 +****************************************************************************/ +static void x86emuOp_aaa(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("AAA\n"); + TRACE_AND_STEP(); + M.x86.R_AX = aaa_word(M.x86.R_AX); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x38 +****************************************************************************/ +static void x86emuOp_cmp_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 *destreg, *srcreg; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(destval, *srcreg); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(destval, *srcreg); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(destval, *srcreg); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x39 +****************************************************************************/ +static void x86emuOp_cmp_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(destval, *srcreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(destval, *srcreg); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(destval, *srcreg); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3a +****************************************************************************/ +static void x86emuOp_cmp_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3b +****************************************************************************/ +static void x86emuOp_cmp_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3c +****************************************************************************/ +static void x86emuOp_cmp_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + cmp_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3d +****************************************************************************/ +static void x86emuOp_cmp_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("CMP\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("CMP\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + cmp_long(M.x86.R_EAX, srcval); + } else { + cmp_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3e +****************************************************************************/ +static void x86emuOp_segovr_DS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("DS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_DS; + /* NO DECODE_CLEAR_SEGOVR! */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3f +****************************************************************************/ +static void x86emuOp_aas(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("AAS\n"); + TRACE_AND_STEP(); + M.x86.R_AX = aas_word(M.x86.R_AX); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x40 +****************************************************************************/ +static void x86emuOp_inc_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEAX\n"); + } else { + DECODE_PRINTF("INC\tAX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = inc_long(M.x86.R_EAX); + } else { + M.x86.R_AX = inc_word(M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x41 +****************************************************************************/ +static void x86emuOp_inc_CX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tECX\n"); + } else { + DECODE_PRINTF("INC\tCX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = inc_long(M.x86.R_ECX); + } else { + M.x86.R_CX = inc_word(M.x86.R_CX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x42 +****************************************************************************/ +static void x86emuOp_inc_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEDX\n"); + } else { + DECODE_PRINTF("INC\tDX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDX = inc_long(M.x86.R_EDX); + } else { + M.x86.R_DX = inc_word(M.x86.R_DX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x43 +****************************************************************************/ +static void x86emuOp_inc_BX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEBX\n"); + } else { + DECODE_PRINTF("INC\tBX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBX = inc_long(M.x86.R_EBX); + } else { + M.x86.R_BX = inc_word(M.x86.R_BX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x44 +****************************************************************************/ +static void x86emuOp_inc_SP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tESP\n"); + } else { + DECODE_PRINTF("INC\tSP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESP = inc_long(M.x86.R_ESP); + } else { + M.x86.R_SP = inc_word(M.x86.R_SP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x45 +****************************************************************************/ +static void x86emuOp_inc_BP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEBP\n"); + } else { + DECODE_PRINTF("INC\tBP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBP = inc_long(M.x86.R_EBP); + } else { + M.x86.R_BP = inc_word(M.x86.R_BP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x46 +****************************************************************************/ +static void x86emuOp_inc_SI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tESI\n"); + } else { + DECODE_PRINTF("INC\tSI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESI = inc_long(M.x86.R_ESI); + } else { + M.x86.R_SI = inc_word(M.x86.R_SI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x47 +****************************************************************************/ +static void x86emuOp_inc_DI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEDI\n"); + } else { + DECODE_PRINTF("INC\tDI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = inc_long(M.x86.R_EDI); + } else { + M.x86.R_DI = inc_word(M.x86.R_DI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x48 +****************************************************************************/ +static void x86emuOp_dec_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEAX\n"); + } else { + DECODE_PRINTF("DEC\tAX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = dec_long(M.x86.R_EAX); + } else { + M.x86.R_AX = dec_word(M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x49 +****************************************************************************/ +static void x86emuOp_dec_CX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tECX\n"); + } else { + DECODE_PRINTF("DEC\tCX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = dec_long(M.x86.R_ECX); + } else { + M.x86.R_CX = dec_word(M.x86.R_CX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4a +****************************************************************************/ +static void x86emuOp_dec_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEDX\n"); + } else { + DECODE_PRINTF("DEC\tDX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDX = dec_long(M.x86.R_EDX); + } else { + M.x86.R_DX = dec_word(M.x86.R_DX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4b +****************************************************************************/ +static void x86emuOp_dec_BX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEBX\n"); + } else { + DECODE_PRINTF("DEC\tBX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBX = dec_long(M.x86.R_EBX); + } else { + M.x86.R_BX = dec_word(M.x86.R_BX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4c +****************************************************************************/ +static void x86emuOp_dec_SP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tESP\n"); + } else { + DECODE_PRINTF("DEC\tSP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESP = dec_long(M.x86.R_ESP); + } else { + M.x86.R_SP = dec_word(M.x86.R_SP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4d +****************************************************************************/ +static void x86emuOp_dec_BP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEBP\n"); + } else { + DECODE_PRINTF("DEC\tBP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBP = dec_long(M.x86.R_EBP); + } else { + M.x86.R_BP = dec_word(M.x86.R_BP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4e +****************************************************************************/ +static void x86emuOp_dec_SI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tESI\n"); + } else { + DECODE_PRINTF("DEC\tSI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESI = dec_long(M.x86.R_ESI); + } else { + M.x86.R_SI = dec_word(M.x86.R_SI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4f +****************************************************************************/ +static void x86emuOp_dec_DI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEDI\n"); + } else { + DECODE_PRINTF("DEC\tDI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = dec_long(M.x86.R_EDI); + } else { + M.x86.R_DI = dec_word(M.x86.R_DI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x50 +****************************************************************************/ +static void x86emuOp_push_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEAX\n"); + } else { + DECODE_PRINTF("PUSH\tAX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EAX); + } else { + push_word(M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x51 +****************************************************************************/ +static void x86emuOp_push_CX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tECX\n"); + } else { + DECODE_PRINTF("PUSH\tCX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_ECX); + } else { + push_word(M.x86.R_CX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x52 +****************************************************************************/ +static void x86emuOp_push_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEDX\n"); + } else { + DECODE_PRINTF("PUSH\tDX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EDX); + } else { + push_word(M.x86.R_DX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x53 +****************************************************************************/ +static void x86emuOp_push_BX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEBX\n"); + } else { + DECODE_PRINTF("PUSH\tBX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EBX); + } else { + push_word(M.x86.R_BX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x54 +****************************************************************************/ +static void x86emuOp_push_SP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tESP\n"); + } else { + DECODE_PRINTF("PUSH\tSP\n"); + } + TRACE_AND_STEP(); + /* Always push (E)SP, since we are emulating an i386 and above + * processor. This is necessary as some BIOS'es use this to check + * what type of processor is in the system. + */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_ESP); + } else { + push_word((u16)(M.x86.R_SP)); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x55 +****************************************************************************/ +static void x86emuOp_push_BP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEBP\n"); + } else { + DECODE_PRINTF("PUSH\tBP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EBP); + } else { + push_word(M.x86.R_BP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x56 +****************************************************************************/ +static void x86emuOp_push_SI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tESI\n"); + } else { + DECODE_PRINTF("PUSH\tSI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_ESI); + } else { + push_word(M.x86.R_SI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x57 +****************************************************************************/ +static void x86emuOp_push_DI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEDI\n"); + } else { + DECODE_PRINTF("PUSH\tDI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EDI); + } else { + push_word(M.x86.R_DI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x58 +****************************************************************************/ +static void x86emuOp_pop_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEAX\n"); + } else { + DECODE_PRINTF("POP\tAX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = pop_long(); + } else { + M.x86.R_AX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x59 +****************************************************************************/ +static void x86emuOp_pop_CX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tECX\n"); + } else { + DECODE_PRINTF("POP\tCX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = pop_long(); + } else { + M.x86.R_CX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5a +****************************************************************************/ +static void x86emuOp_pop_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEDX\n"); + } else { + DECODE_PRINTF("POP\tDX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDX = pop_long(); + } else { + M.x86.R_DX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5b +****************************************************************************/ +static void x86emuOp_pop_BX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEBX\n"); + } else { + DECODE_PRINTF("POP\tBX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBX = pop_long(); + } else { + M.x86.R_BX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5c +****************************************************************************/ +static void x86emuOp_pop_SP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tESP\n"); + } else { + DECODE_PRINTF("POP\tSP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESP = pop_long(); + } else { + M.x86.R_SP = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5d +****************************************************************************/ +static void x86emuOp_pop_BP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEBP\n"); + } else { + DECODE_PRINTF("POP\tBP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBP = pop_long(); + } else { + M.x86.R_BP = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5e +****************************************************************************/ +static void x86emuOp_pop_SI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tESI\n"); + } else { + DECODE_PRINTF("POP\tSI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESI = pop_long(); + } else { + M.x86.R_SI = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5f +****************************************************************************/ +static void x86emuOp_pop_DI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEDI\n"); + } else { + DECODE_PRINTF("POP\tDI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = pop_long(); + } else { + M.x86.R_DI = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x60 +****************************************************************************/ +static void x86emuOp_push_all(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSHAD\n"); + } else { + DECODE_PRINTF("PUSHA\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 old_sp = M.x86.R_ESP; + + push_long(M.x86.R_EAX); + push_long(M.x86.R_ECX); + push_long(M.x86.R_EDX); + push_long(M.x86.R_EBX); + push_long(old_sp); + push_long(M.x86.R_EBP); + push_long(M.x86.R_ESI); + push_long(M.x86.R_EDI); + } else { + u16 old_sp = M.x86.R_SP; + + push_word(M.x86.R_AX); + push_word(M.x86.R_CX); + push_word(M.x86.R_DX); + push_word(M.x86.R_BX); + push_word(old_sp); + push_word(M.x86.R_BP); + push_word(M.x86.R_SI); + push_word(M.x86.R_DI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x61 +****************************************************************************/ +static void x86emuOp_pop_all(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POPAD\n"); + } else { + DECODE_PRINTF("POPA\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = pop_long(); + M.x86.R_ESI = pop_long(); + M.x86.R_EBP = pop_long(); + M.x86.R_ESP += 4; /* skip ESP */ + M.x86.R_EBX = pop_long(); + M.x86.R_EDX = pop_long(); + M.x86.R_ECX = pop_long(); + M.x86.R_EAX = pop_long(); + } else { + M.x86.R_DI = pop_word(); + M.x86.R_SI = pop_word(); + M.x86.R_BP = pop_word(); + M.x86.R_SP += 2; /* skip SP */ + M.x86.R_BX = pop_word(); + M.x86.R_DX = pop_word(); + M.x86.R_CX = pop_word(); + M.x86.R_AX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/*opcode 0x62 ILLEGAL OP, calls x86emuOp_illegal_op() */ +/*opcode 0x63 ILLEGAL OP, calls x86emuOp_illegal_op() */ + +/**************************************************************************** +REMARKS: +Handles opcode 0x64 +****************************************************************************/ +static void x86emuOp_segovr_FS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("FS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_FS; + /* + * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4 + * opcode subroutines we do not want to do this. + */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x65 +****************************************************************************/ +static void x86emuOp_segovr_GS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("GS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_GS; + /* + * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4 + * opcode subroutines we do not want to do this. + */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x66 - prefix for 32-bit register +****************************************************************************/ +static void x86emuOp_prefix_data(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("DATA:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_PREFIX_DATA; + /* note no DECODE_CLEAR_SEGOVR here. */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x67 - prefix for 32-bit address +****************************************************************************/ +static void x86emuOp_prefix_addr(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("ADDR:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_PREFIX_ADDR; + /* note no DECODE_CLEAR_SEGOVR here. */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x68 +****************************************************************************/ +static void x86emuOp_push_word_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 imm; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + imm = fetch_long_imm(); + } else { + imm = fetch_word_imm(); + } + DECODE_PRINTF2("PUSH\t%x\n", imm); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(imm); + } else { + push_word((u16)imm); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x69 +****************************************************************************/ +static void x86emuOp_imul_word_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("IMUL\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + res = (s16)*srcreg * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6a +****************************************************************************/ +static void x86emuOp_push_byte_IMM(u8 X86EMU_UNUSED(op1)) +{ + s16 imm; + + START_OF_INSTR(); + imm = (s8)fetch_byte_imm(); + DECODE_PRINTF2("PUSH\t%d\n", imm); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long((s32)imm); + } else { + push_word(imm); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6b +****************************************************************************/ +static void x86emuOp_imul_byte_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + s8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("IMUL\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + res = (s16)*srcreg * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6c +****************************************************************************/ +static void x86emuOp_ins_byte(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("INSB\n"); + ins(1); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6d +****************************************************************************/ +static void x86emuOp_ins_word(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INSD\n"); + ins(4); + } else { + DECODE_PRINTF("INSW\n"); + ins(2); + } + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6e +****************************************************************************/ +static void x86emuOp_outs_byte(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("OUTSB\n"); + outs(1); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6f +****************************************************************************/ +static void x86emuOp_outs_word(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("OUTSD\n"); + outs(4); + } else { + DECODE_PRINTF("OUTSW\n"); + outs(2); + } + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x70 +****************************************************************************/ +static void x86emuOp_jump_near_O(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if overflow flag is set */ + START_OF_INSTR(); + DECODE_PRINTF("JO\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_OF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x71 +****************************************************************************/ +static void x86emuOp_jump_near_NO(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if overflow is not set */ + START_OF_INSTR(); + DECODE_PRINTF("JNO\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_OF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x72 +****************************************************************************/ +static void x86emuOp_jump_near_B(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if carry flag is set. */ + START_OF_INSTR(); + DECODE_PRINTF("JB\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_CF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x73 +****************************************************************************/ +static void x86emuOp_jump_near_NB(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if carry flag is clear. */ + START_OF_INSTR(); + DECODE_PRINTF("JNB\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_CF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x74 +****************************************************************************/ +static void x86emuOp_jump_near_Z(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if zero flag is set. */ + START_OF_INSTR(); + DECODE_PRINTF("JZ\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x75 +****************************************************************************/ +static void x86emuOp_jump_near_NZ(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if zero flag is clear. */ + START_OF_INSTR(); + DECODE_PRINTF("JNZ\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x76 +****************************************************************************/ +static void x86emuOp_jump_near_BE(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if carry flag is set or if the zero + flag is set. */ + START_OF_INSTR(); + DECODE_PRINTF("JBE\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x77 +****************************************************************************/ +static void x86emuOp_jump_near_NBE(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if carry flag is clear and if the zero + flag is clear */ + START_OF_INSTR(); + DECODE_PRINTF("JNBE\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF))) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x78 +****************************************************************************/ +static void x86emuOp_jump_near_S(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if sign flag is set */ + START_OF_INSTR(); + DECODE_PRINTF("JS\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_SF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x79 +****************************************************************************/ +static void x86emuOp_jump_near_NS(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if sign flag is clear */ + START_OF_INSTR(); + DECODE_PRINTF("JNS\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_SF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7a +****************************************************************************/ +static void x86emuOp_jump_near_P(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if parity flag is set (even parity) */ + START_OF_INSTR(); + DECODE_PRINTF("JP\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_PF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7b +****************************************************************************/ +static void x86emuOp_jump_near_NP(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if parity flag is clear (odd parity) */ + START_OF_INSTR(); + DECODE_PRINTF("JNP\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_PF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7c +****************************************************************************/ +static void x86emuOp_jump_near_L(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + int sf, of; + + /* jump to byte offset if sign flag not equal to overflow flag. */ + START_OF_INSTR(); + DECODE_PRINTF("JL\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + sf = ACCESS_FLAG(F_SF) != 0; + of = ACCESS_FLAG(F_OF) != 0; + if (sf ^ of) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7d +****************************************************************************/ +static void x86emuOp_jump_near_NL(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + int sf, of; + + /* jump to byte offset if sign flag not equal to overflow flag. */ + START_OF_INSTR(); + DECODE_PRINTF("JNL\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + sf = ACCESS_FLAG(F_SF) != 0; + of = ACCESS_FLAG(F_OF) != 0; + /* note: inverse of above, but using == instead of xor. */ + if (sf == of) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7e +****************************************************************************/ +static void x86emuOp_jump_near_LE(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + int sf, of; + + /* jump to byte offset if sign flag not equal to overflow flag + or the zero flag is set */ + START_OF_INSTR(); + DECODE_PRINTF("JLE\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + sf = ACCESS_FLAG(F_SF) != 0; + of = ACCESS_FLAG(F_OF) != 0; + if ((sf ^ of) || ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7f +****************************************************************************/ +static void x86emuOp_jump_near_NLE(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + int sf, of; + + /* jump to byte offset if sign flag equal to overflow flag. + and the zero flag is clear */ + START_OF_INSTR(); + DECODE_PRINTF("JNLE\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + sf = ACCESS_FLAG(F_SF) != 0; + of = ACCESS_FLAG(F_OF) != 0; + if ((sf == of) && !ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +static u8 (*opc80_byte_operation[])(u8 d, u8 s) = +{ + add_byte, /* 00 */ + or_byte, /* 01 */ + adc_byte, /* 02 */ + sbb_byte, /* 03 */ + and_byte, /* 04 */ + sub_byte, /* 05 */ + xor_byte, /* 06 */ + cmp_byte, /* 07 */ +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0x80 +****************************************************************************/ +static void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 imm; + u8 destval; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc80_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc80_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc80_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc80_byte_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +static u16 (*opc81_word_operation[])(u16 d, u16 s) = +{ + add_word, /*00 */ + or_word, /*01 */ + adc_word, /*02 */ + sbb_word, /*03 */ + and_word, /*04 */ + sub_word, /*05 */ + xor_word, /*06 */ + cmp_word, /*07 */ +}; + +static u32 (*opc81_long_operation[])(u32 d, u32 s) = +{ + add_long, /*00 */ + or_long, /*01 */ + adc_long, /*02 */ + sbb_long, /*03 */ + and_long, /*04 */ + sub_long, /*05 */ + xor_long, /*06 */ + cmp_long, /*07 */ +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0x81 +****************************************************************************/ +static void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } + } +#endif + /* + * Know operation, decode the mod byte to find the addressing + * mode. + */ + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 destval,imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_long_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } else { + u16 *destreg; + u16 destval,imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_word_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +static u8 (*opc82_byte_operation[])(u8 s, u8 d) = +{ + add_byte, /*00 */ + or_byte, /*01 *//*YYY UNUSED ???? */ + adc_byte, /*02 */ + sbb_byte, /*03 */ + and_byte, /*04 *//*YYY UNUSED ???? */ + sub_byte, /*05 */ + xor_byte, /*06 *//*YYY UNUSED ???? */ + cmp_byte, /*07 */ +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0x82 +****************************************************************************/ +static void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 imm; + u8 destval; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction Similar to opcode 81, except that + * the immediate byte is sign extended to a word length. + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc82_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc82_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc82_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc82_byte_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +static u16 (*opc83_word_operation[])(u16 s, u16 d) = +{ + add_word, /*00 */ + or_word, /*01 *//*YYY UNUSED ???? */ + adc_word, /*02 */ + sbb_word, /*03 */ + and_word, /*04 *//*YYY UNUSED ???? */ + sub_word, /*05 */ + xor_word, /*06 *//*YYY UNUSED ???? */ + cmp_word, /*07 */ +}; + +static u32 (*opc83_long_operation[])(u32 s, u32 d) = +{ + add_long, /*00 */ + or_long, /*01 *//*YYY UNUSED ???? */ + adc_long, /*02 */ + sbb_long, /*03 */ + and_long, /*04 *//*YYY UNUSED ???? */ + sub_long, /*05 */ + xor_long, /*06 *//*YYY UNUSED ???? */ + cmp_long, /*07 */ +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0x83 +****************************************************************************/ +static void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction Similar to opcode 81, except that + * the immediate byte is sign extended to a word length. + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + destval = fetch_data_long(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + destval = fetch_data_word(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + destval = fetch_data_long(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + destval = fetch_data_word(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + destval = fetch_data_long(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + destval = fetch_data_word(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 destval,imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_long_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } else { + u16 *destreg; + u16 destval,imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_word_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x84 +****************************************************************************/ +static void x86emuOp_test_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("TEST\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(destval, *srcreg); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(destval, *srcreg); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(destval, *srcreg); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x85 +****************************************************************************/ +static void x86emuOp_test_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("TEST\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(destval, *srcreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(destval, *srcreg); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(destval, *srcreg); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x86 +****************************************************************************/ +static void x86emuOp_xchg_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + u8 tmp; + + START_OF_INSTR(); + DECODE_PRINTF("XCHG\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x87 +****************************************************************************/ +static void x86emuOp_xchg_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("XCHG\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 destval,tmp; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_long(destoffset, destval); + } else { + u16 *srcreg; + u16 destval,tmp; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 destval,tmp; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_long(destoffset, destval); + } else { + u16 *srcreg; + u16 destval,tmp; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 destval,tmp; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_long(destoffset, destval); + } else { + u16 *srcreg; + u16 destval,tmp; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 tmp; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + } else { + u16 *destreg,*srcreg; + u16 tmp; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x88 +****************************************************************************/ +static void x86emuOp_mov_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, *srcreg); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, *srcreg); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, *srcreg); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x89 +****************************************************************************/ +static void x86emuOp_mov_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u32 destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_long(destoffset, *srcreg); + } else { + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_word(destoffset, *srcreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_long(destoffset, *srcreg); + } else { + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_word(destoffset, *srcreg); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_long(destoffset, *srcreg); + } else { + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_word(destoffset, *srcreg); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8a +****************************************************************************/ +static void x86emuOp_mov_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8b +****************************************************************************/ +static void x86emuOp_mov_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg, *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg, *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8c +****************************************************************************/ +static void x86emuOp_mov_word_RM_SR(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u16 *destreg, *srcreg; + uint destoffset; + u16 destval; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = *srcreg; + store_data_word(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = *srcreg; + store_data_word(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = *srcreg; + store_data_word(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8d +****************************************************************************/ +static void x86emuOp_lea_word_R_M(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LEA\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + u32 *srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u32)destoffset; + } else { + u16 *srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u16)destoffset; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + u32 *srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u32)destoffset; + } else { + u16 *srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u16)destoffset; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + u32 *srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u32)destoffset; + } else { + u16 *srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u16)destoffset; + } + break; + case 3: /* register to register */ + /* undefined. Do nothing. */ + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8e +****************************************************************************/ +static void x86emuOp_mov_word_SR_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u16 *destreg, *srcreg; + uint srcoffset; + u16 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 1: + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 2: + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 3: /* register to register */ + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + /* + * Clean up, and reset all the R_xSP pointers to the correct + * locations. This is about 3x too much overhead (doing all the + * segreg ptrs when only one is needed, but this instruction + * *cannot* be that common, and this isn't too much work anyway. + */ + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8f +****************************************************************************/ +static void x86emuOp_pop_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("POP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (rh != 0) { + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); + HALT_SYS(); + } + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_long(); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_word(); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_long(); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_word(); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_long(); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_word(); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = pop_long(); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = pop_word(); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x90 +****************************************************************************/ +static void x86emuOp_nop(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("NOP\n"); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x91 +****************************************************************************/ +static void x86emuOp_xchg_word_AX_CX(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,ECX\n"); + } else { + DECODE_PRINTF("XCHG\tAX,CX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_ECX; + M.x86.R_ECX = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_CX; + M.x86.R_CX = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x92 +****************************************************************************/ +static void x86emuOp_xchg_word_AX_DX(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,EDX\n"); + } else { + DECODE_PRINTF("XCHG\tAX,DX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_EDX; + M.x86.R_EDX = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_DX; + M.x86.R_DX = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x93 +****************************************************************************/ +static void x86emuOp_xchg_word_AX_BX(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,EBX\n"); + } else { + DECODE_PRINTF("XCHG\tAX,BX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_EBX; + M.x86.R_EBX = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_BX; + M.x86.R_BX = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x94 +****************************************************************************/ +static void x86emuOp_xchg_word_AX_SP(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,ESP\n"); + } else { + DECODE_PRINTF("XCHG\tAX,SP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_ESP; + M.x86.R_ESP = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_SP; + M.x86.R_SP = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x95 +****************************************************************************/ +static void x86emuOp_xchg_word_AX_BP(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,EBP\n"); + } else { + DECODE_PRINTF("XCHG\tAX,BP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_EBP; + M.x86.R_EBP = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_BP; + M.x86.R_BP = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x96 +****************************************************************************/ +static void x86emuOp_xchg_word_AX_SI(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,ESI\n"); + } else { + DECODE_PRINTF("XCHG\tAX,SI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_ESI; + M.x86.R_ESI = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_SI; + M.x86.R_SI = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x97 +****************************************************************************/ +static void x86emuOp_xchg_word_AX_DI(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,EDI\n"); + } else { + DECODE_PRINTF("XCHG\tAX,DI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_EDI; + M.x86.R_EDI = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_DI; + M.x86.R_DI = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x98 +****************************************************************************/ +static void x86emuOp_cbw(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("CWDE\n"); + } else { + DECODE_PRINTF("CBW\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + if (M.x86.R_AX & 0x8000) { + M.x86.R_EAX |= 0xffff0000; + } else { + M.x86.R_EAX &= 0x0000ffff; + } + } else { + if (M.x86.R_AL & 0x80) { + M.x86.R_AH = 0xff; + } else { + M.x86.R_AH = 0x0; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x99 +****************************************************************************/ +static void x86emuOp_cwd(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("CDQ\n"); + } else { + DECODE_PRINTF("CWD\n"); + } + DECODE_PRINTF("CWD\n"); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + if (M.x86.R_EAX & 0x80000000) { + M.x86.R_EDX = 0xffffffff; + } else { + M.x86.R_EDX = 0x0; + } + } else { + if (M.x86.R_AX & 0x8000) { + M.x86.R_DX = 0xffff; + } else { + M.x86.R_DX = 0x0; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9a +****************************************************************************/ +static void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 farseg, faroff; + + START_OF_INSTR(); + DECODE_PRINTF("CALL\t"); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + faroff = fetch_long_imm(); + farseg = fetch_word_imm(); + } else { + faroff = fetch_word_imm(); + farseg = fetch_word_imm(); + } + DECODE_PRINTF2("%04x:", farseg); + DECODE_PRINTF2("%04x\n", faroff); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, farseg, faroff, "FAR "); + + /* XXX + * + * Hooked interrupt vectors calling into our "BIOS" will cause + * problems unless all intersegment stuff is checked for BIOS + * access. Check needed here. For moment, let it alone. + */ + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = farseg; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EIP); + } else { + push_word(M.x86.R_IP); + } + M.x86.R_EIP = faroff & 0xffff; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9b +****************************************************************************/ +static void x86emuOp_wait(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("WAIT"); + TRACE_AND_STEP(); + /* NADA. */ + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9c +****************************************************************************/ +static void x86emuOp_pushf_word(u8 X86EMU_UNUSED(op1)) +{ + u32 flags; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSHFD\n"); + } else { + DECODE_PRINTF("PUSHF\n"); + } + TRACE_AND_STEP(); + + /* clear out *all* bits not representing flags, and turn on real bits */ + flags = (M.x86.R_EFLG & F_MSK) | F_ALWAYS_ON; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(flags); + } else { + push_word((u16)flags); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9d +****************************************************************************/ +static void x86emuOp_popf_word(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POPFD\n"); + } else { + DECODE_PRINTF("POPF\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EFLG = pop_long(); + } else { + M.x86.R_FLG = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9e +****************************************************************************/ +static void x86emuOp_sahf(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("SAHF\n"); + TRACE_AND_STEP(); + /* clear the lower bits of the flag register */ + M.x86.R_FLG &= 0xffffff00; + /* or in the AH register into the flags register */ + M.x86.R_FLG |= M.x86.R_AH; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9f +****************************************************************************/ +static void x86emuOp_lahf(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("LAHF\n"); + TRACE_AND_STEP(); + M.x86.R_AH = (u8)(M.x86.R_FLG & 0xff); + /*undocumented TC++ behavior??? Nope. It's documented, but + you have too look real hard to notice it. */ + M.x86.R_AH |= 0x2; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa0 +****************************************************************************/ +static void x86emuOp_mov_AL_M_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 offset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tAL,"); + offset = fetch_word_imm(); + DECODE_PRINTF2("[%04x]\n", offset); + TRACE_AND_STEP(); + M.x86.R_AL = fetch_data_byte(offset); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa1 +****************************************************************************/ +static void x86emuOp_mov_AX_M_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 offset; + + START_OF_INSTR(); + offset = fetch_word_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("MOV\tEAX,[%04x]\n", offset); + } else { + DECODE_PRINTF2("MOV\tAX,[%04x]\n", offset); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = fetch_data_long(offset); + } else { + M.x86.R_AX = fetch_data_word(offset); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa2 +****************************************************************************/ +static void x86emuOp_mov_M_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 offset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + offset = fetch_word_imm(); + DECODE_PRINTF2("[%04x],AL\n", offset); + TRACE_AND_STEP(); + store_data_byte(offset, M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa3 +****************************************************************************/ +static void x86emuOp_mov_M_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 offset; + + START_OF_INSTR(); + offset = fetch_word_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("MOV\t[%04x],EAX\n", offset); + } else { + DECODE_PRINTF2("MOV\t[%04x],AX\n", offset); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + store_data_long(offset, M.x86.R_EAX); + } else { + store_data_word(offset, M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa4 +****************************************************************************/ +static void x86emuOp_movs_byte(u8 X86EMU_UNUSED(op1)) +{ + u8 val; + u32 count; + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("MOVS\tBYTE\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + TRACE_AND_STEP(); + count = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + val = fetch_data_byte(M.x86.R_SI); + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, val); + M.x86.R_SI += inc; + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa5 +****************************************************************************/ +static void x86emuOp_movs_word(u8 X86EMU_UNUSED(op1)) +{ + u32 val; + int inc; + u32 count; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOVS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("MOVS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + count = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long(M.x86.R_SI); + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, val); + } else { + val = fetch_data_word(M.x86.R_SI); + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, (u16)val); + } + M.x86.R_SI += inc; + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa6 +****************************************************************************/ +static void x86emuOp_cmps_byte(u8 X86EMU_UNUSED(op1)) +{ + s8 val1, val2; + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("CMPS\tBYTE\n"); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + + if (M.x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + M.x86.R_SI += inc; + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa7 +****************************************************************************/ +static void x86emuOp_cmps_word(u8 X86EMU_UNUSED(op1)) +{ + u32 val1,val2; + int inc; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("CMPS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("CMPS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + M.x86.R_SI += inc; + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa8 +****************************************************************************/ +static void x86emuOp_test_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + int imm; + + START_OF_INSTR(); + DECODE_PRINTF("TEST\tAL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%04x\n", imm); + TRACE_AND_STEP(); + test_byte(M.x86.R_AL, (u8)imm); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa9 +****************************************************************************/ +static void x86emuOp_test_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("TEST\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("TEST\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + test_long(M.x86.R_EAX, srcval); + } else { + test_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xaa +****************************************************************************/ +static void x86emuOp_stos_byte(u8 X86EMU_UNUSED(op1)) +{ + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("STOS\tBYTE\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + TRACE_AND_STEP(); + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xab +****************************************************************************/ +static void x86emuOp_stos_word(u8 X86EMU_UNUSED(op1)) +{ + int inc; + u32 count; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("STOS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("STOS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + count = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_EAX); + } else { + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AX); + } + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xac +****************************************************************************/ +static void x86emuOp_lods_byte(u8 X86EMU_UNUSED(op1)) +{ + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("LODS\tBYTE\n"); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + M.x86.R_AL = fetch_data_byte(M.x86.R_SI); + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + M.x86.R_AL = fetch_data_byte(M.x86.R_SI); + M.x86.R_SI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xad +****************************************************************************/ +static void x86emuOp_lods_word(u8 X86EMU_UNUSED(op1)) +{ + int inc; + u32 count; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("LODS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("LODS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + count = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = fetch_data_long(M.x86.R_SI); + } else { + M.x86.R_AX = fetch_data_word(M.x86.R_SI); + } + M.x86.R_SI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xae +****************************************************************************/ +static void x86emuOp_scas_byte(u8 X86EMU_UNUSED(op1)) +{ + s8 val2; + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("SCAS\tBYTE\n"); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + if (M.x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xaf +****************************************************************************/ +static void x86emuOp_scas_word(u8 X86EMU_UNUSED(op1)) +{ + int inc; + u32 val; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("SCAS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("SCAS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb0 +****************************************************************************/ +static void x86emuOp_mov_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tAL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_AL = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb1 +****************************************************************************/ +static void x86emuOp_mov_byte_CL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tCL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_CL = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb2 +****************************************************************************/ +static void x86emuOp_mov_byte_DL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tDL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_DL = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb3 +****************************************************************************/ +static void x86emuOp_mov_byte_BL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tBL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_BL = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb4 +****************************************************************************/ +static void x86emuOp_mov_byte_AH_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tAH,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_AH = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb5 +****************************************************************************/ +static void x86emuOp_mov_byte_CH_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tCH,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_CH = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb6 +****************************************************************************/ +static void x86emuOp_mov_byte_DH_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tDH,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_DH = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb7 +****************************************************************************/ +static void x86emuOp_mov_byte_BH_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tBH,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_BH = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb8 +****************************************************************************/ +static void x86emuOp_mov_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = srcval; + } else { + M.x86.R_AX = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb9 +****************************************************************************/ +static void x86emuOp_mov_word_CX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tECX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tCX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = srcval; + } else { + M.x86.R_CX = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xba +****************************************************************************/ +static void x86emuOp_mov_word_DX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEDX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tDX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDX = srcval; + } else { + M.x86.R_DX = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbb +****************************************************************************/ +static void x86emuOp_mov_word_BX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEBX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tBX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBX = srcval; + } else { + M.x86.R_BX = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbc +****************************************************************************/ +static void x86emuOp_mov_word_SP_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tESP,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tSP,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESP = srcval; + } else { + M.x86.R_SP = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbd +****************************************************************************/ +static void x86emuOp_mov_word_BP_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEBP,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tBP,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBP = srcval; + } else { + M.x86.R_BP = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbe +****************************************************************************/ +static void x86emuOp_mov_word_SI_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tESI,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tSI,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESI = srcval; + } else { + M.x86.R_SI = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbf +****************************************************************************/ +static void x86emuOp_mov_word_DI_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEDI,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tDI,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = srcval; + } else { + M.x86.R_DI = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/* used by opcodes c0, d0, and d2. */ +static u8(*opcD0_byte_operation[])(u8 d, u8 s) = +{ + rol_byte, + ror_byte, + rcl_byte, + rcr_byte, + shl_byte, + shr_byte, + shl_byte, /* sal_byte === shl_byte by definition */ + sar_byte, +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0xc0 +****************************************************************************/ +static void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 destval; + u8 amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, amt); + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/* used by opcodes c1, d1, and d3. */ +static u16(*opcD1_word_operation[])(u16 s, u8 d) = +{ + rol_word, + ror_word, + rcl_word, + rcr_word, + shl_word, + shr_word, + shl_word, /* sal_byte === shl_byte by definition */ + sar_word, +}; + +/* used by opcodes c1, d1, and d3. */ +static u32 (*opcD1_long_operation[])(u32 s, u8 d) = +{ + rol_long, + ror_long, + rcl_long, + rcr_long, + shl_long, + shr_long, + shl_long, /* sal_byte === shl_byte by definition */ + sar_long, +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0xc1 +****************************************************************************/ +static void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc2 +****************************************************************************/ +static void x86emuOp_ret_near_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 imm; + + START_OF_INSTR(); + DECODE_PRINTF("RET\t"); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + RETURN_TRACE("RET",M.x86.saved_cs,M.x86.saved_ip); + TRACE_AND_STEP(); + M.x86.R_IP = pop_word(); + M.x86.R_SP += imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc3 +****************************************************************************/ +static void x86emuOp_ret_near(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("RET\n"); + RETURN_TRACE("RET",M.x86.saved_cs,M.x86.saved_ip); + TRACE_AND_STEP(); + M.x86.R_IP = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc4 +****************************************************************************/ +static void x86emuOp_les_R_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LES\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_ES = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_ES = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_ES = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc5 +****************************************************************************/ +static void x86emuOp_lds_R_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LDS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_DS = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_DS = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_DS = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc6 +****************************************************************************/ +static void x86emuOp_mov_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (rh != 0) { + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n"); + HALT_SYS(); + } + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + store_data_byte(destoffset, imm); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + store_data_byte(destoffset, imm); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + store_data_byte(destoffset, imm); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc7 +****************************************************************************/ +static void x86emuOp_mov_word_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (rh != 0) { + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); + HALT_SYS(); + } + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_long(destoffset, imm); + } else { + u16 imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_word(destoffset, imm); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_long(destoffset, imm); + } else { + u16 imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_word(destoffset, imm); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_long(destoffset, imm); + } else { + u16 imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_word(destoffset, imm); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + } else { + u16 *destreg; + u16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc8 +****************************************************************************/ +static void x86emuOp_enter(u8 X86EMU_UNUSED(op1)) +{ + u16 local,frame_pointer; + u8 nesting; + int i; + + START_OF_INSTR(); + local = fetch_word_imm(); + nesting = fetch_byte_imm(); + DECODE_PRINTF2("ENTER %x\n", local); + DECODE_PRINTF2(",%x\n", nesting); + TRACE_AND_STEP(); + push_word(M.x86.R_BP); + frame_pointer = M.x86.R_SP; + if (nesting > 0) { + for (i = 1; i < nesting; i++) { + M.x86.R_BP -= 2; + push_word(fetch_data_word_abs(M.x86.R_SS, M.x86.R_BP)); + } + push_word(frame_pointer); + } + M.x86.R_BP = frame_pointer; + M.x86.R_SP = (u16)(M.x86.R_SP - local); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc9 +****************************************************************************/ +static void x86emuOp_leave(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("LEAVE\n"); + TRACE_AND_STEP(); + M.x86.R_SP = M.x86.R_BP; + M.x86.R_BP = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xca +****************************************************************************/ +static void x86emuOp_ret_far_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 imm; + + START_OF_INSTR(); + DECODE_PRINTF("RETF\t"); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + RETURN_TRACE("RETF",M.x86.saved_cs,M.x86.saved_ip); + TRACE_AND_STEP(); + M.x86.R_IP = pop_word(); + M.x86.R_CS = pop_word(); + M.x86.R_SP += imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xcb +****************************************************************************/ +static void x86emuOp_ret_far(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("RETF\n"); + RETURN_TRACE("RETF",M.x86.saved_cs,M.x86.saved_ip); + TRACE_AND_STEP(); + M.x86.R_IP = pop_word(); + M.x86.R_CS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xcc +****************************************************************************/ +static void x86emuOp_int3(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("INT 3\n"); + TRACE_AND_STEP(); + if (_X86EMU_intrTab[3]) { + (*_X86EMU_intrTab[3])(3); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(3 * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(3 * 4); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xcd +****************************************************************************/ +static void x86emuOp_int_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 intnum; + + START_OF_INSTR(); + DECODE_PRINTF("INT\t"); + intnum = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", intnum); + TRACE_AND_STEP(); + if (_X86EMU_intrTab[intnum]) { + (*_X86EMU_intrTab[intnum])(intnum); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(intnum * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(intnum * 4); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xce +****************************************************************************/ +static void x86emuOp_into(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("INTO\n"); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_OF)) { + if (_X86EMU_intrTab[4]) { + (*_X86EMU_intrTab[4])(4); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(4 * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(4 * 4); + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xcf +****************************************************************************/ +static void x86emuOp_iret(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("IRET\n"); + + TRACE_AND_STEP(); + + M.x86.R_IP = pop_word(); + M.x86.R_CS = pop_word(); + M.x86.R_FLG = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd0 +****************************************************************************/ +static void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 destval; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, 1); + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, 1); + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, 1); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, 1); + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd1 +****************************************************************************/ +static void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, 1); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, 1); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, 1); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, 1); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, 1); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, 1); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (*destreg, 1); + *destreg = destval; + } else { + u16 destval; + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (*destreg, 1); + *destreg = destval; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd2 +****************************************************************************/ +static void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 destval; + u8 amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + amt = M.x86.R_CL; + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, amt); + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd3 +****************************************************************************/ +static void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + amt = M.x86.R_CL; + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd4 +****************************************************************************/ +static void x86emuOp_aam(u8 X86EMU_UNUSED(op1)) +{ + u8 a; + + START_OF_INSTR(); + DECODE_PRINTF("AAM\n"); + a = fetch_byte_imm(); /* this is a stupid encoding. */ + if (a != 10) { + /* fix: add base decoding + aam_word(u8 val, int base a) */ + DECODE_PRINTF("ERROR DECODING AAM\n"); + TRACE_REGS(); + HALT_SYS(); + } + TRACE_AND_STEP(); + /* note the type change here --- returning AL and AH in AX. */ + M.x86.R_AX = aam_word(M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd5 +****************************************************************************/ +static void x86emuOp_aad(u8 X86EMU_UNUSED(op1)) +{ + u8 a; + + START_OF_INSTR(); + DECODE_PRINTF("AAD\n"); + a = fetch_byte_imm(); + if (a != 10) { + /* fix: add base decoding + aad_word(u16 val, int base a) */ + DECODE_PRINTF("ERROR DECODING AAM\n"); + TRACE_REGS(); + HALT_SYS(); + } + TRACE_AND_STEP(); + M.x86.R_AX = aad_word(M.x86.R_AX); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/* opcode 0xd6 ILLEGAL OPCODE */ + +/**************************************************************************** +REMARKS: +Handles opcode 0xd7 +****************************************************************************/ +static void x86emuOp_xlat(u8 X86EMU_UNUSED(op1)) +{ + u16 addr; + + START_OF_INSTR(); + DECODE_PRINTF("XLAT\n"); + TRACE_AND_STEP(); + addr = (u16)(M.x86.R_BX + (u8)M.x86.R_AL); + M.x86.R_AL = fetch_data_byte(addr); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/* instuctions D8 .. DF are in i87_ops.c */ + +/**************************************************************************** +REMARKS: +Handles opcode 0xe0 +****************************************************************************/ +static void x86emuOp_loopne(u8 X86EMU_UNUSED(op1)) +{ + s16 ip; + + START_OF_INSTR(); + DECODE_PRINTF("LOOPNE\t"); + ip = (s8) fetch_byte_imm(); + ip += (s16) M.x86.R_IP; + DECODE_PRINTF2("%04x\n", ip); + TRACE_AND_STEP(); + M.x86.R_CX -= 1; + if (M.x86.R_CX != 0 && !ACCESS_FLAG(F_ZF)) /* CX != 0 and !ZF */ + M.x86.R_IP = ip; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe1 +****************************************************************************/ +static void x86emuOp_loope(u8 X86EMU_UNUSED(op1)) +{ + s16 ip; + + START_OF_INSTR(); + DECODE_PRINTF("LOOPE\t"); + ip = (s8) fetch_byte_imm(); + ip += (s16) M.x86.R_IP; + DECODE_PRINTF2("%04x\n", ip); + TRACE_AND_STEP(); + M.x86.R_CX -= 1; + if (M.x86.R_CX != 0 && ACCESS_FLAG(F_ZF)) /* CX != 0 and ZF */ + M.x86.R_IP = ip; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe2 +****************************************************************************/ +static void x86emuOp_loop(u8 X86EMU_UNUSED(op1)) +{ + s16 ip; + + START_OF_INSTR(); + DECODE_PRINTF("LOOP\t"); + ip = (s8) fetch_byte_imm(); + ip += (s16) M.x86.R_IP; + DECODE_PRINTF2("%04x\n", ip); + TRACE_AND_STEP(); + M.x86.R_CX -= 1; + if (M.x86.R_CX != 0) + M.x86.R_IP = ip; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe3 +****************************************************************************/ +static void x86emuOp_jcxz(u8 X86EMU_UNUSED(op1)) +{ + u16 target; + s8 offset; + + /* jump to byte offset if overflow flag is set */ + START_OF_INSTR(); + DECODE_PRINTF("JCXZ\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (M.x86.R_CX == 0) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe4 +****************************************************************************/ +static void x86emuOp_in_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 port; + + START_OF_INSTR(); + DECODE_PRINTF("IN\t"); + port = (u8) fetch_byte_imm(); + DECODE_PRINTF2("%x,AL\n", port); + TRACE_AND_STEP(); + M.x86.R_AL = (*sys_inb)(port); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe5 +****************************************************************************/ +static void x86emuOp_in_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 port; + + START_OF_INSTR(); + DECODE_PRINTF("IN\t"); + port = (u8) fetch_byte_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("EAX,%x\n", port); + } else { + DECODE_PRINTF2("AX,%x\n", port); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = (*sys_inl)(port); + } else { + M.x86.R_AX = (*sys_inw)(port); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe6 +****************************************************************************/ +static void x86emuOp_out_byte_IMM_AL(u8 X86EMU_UNUSED(op1)) +{ + u8 port; + + START_OF_INSTR(); + DECODE_PRINTF("OUT\t"); + port = (u8) fetch_byte_imm(); + DECODE_PRINTF2("%x,AL\n", port); + TRACE_AND_STEP(); + (*sys_outb)(port, M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe7 +****************************************************************************/ +static void x86emuOp_out_word_IMM_AX(u8 X86EMU_UNUSED(op1)) +{ + u8 port; + + START_OF_INSTR(); + DECODE_PRINTF("OUT\t"); + port = (u8) fetch_byte_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("%x,EAX\n", port); + } else { + DECODE_PRINTF2("%x,AX\n", port); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + (*sys_outl)(port, M.x86.R_EAX); + } else { + (*sys_outw)(port, M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe8 +****************************************************************************/ +static void x86emuOp_call_near_IMM(u8 X86EMU_UNUSED(op1)) +{ + s16 ip16 = 0; + s32 ip32 = 0; + + START_OF_INSTR(); + DECODE_PRINTF("CALL\t"); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + ip32 = (s32) fetch_long_imm(); + ip32 += (s16) M.x86.R_IP; /* CHECK SIGN */ + DECODE_PRINTF2("%04x\n", (u16)ip32); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip32, ""); + } else { + ip16 = (s16) fetch_word_imm(); + ip16 += (s16) M.x86.R_IP; /* CHECK SIGN */ + DECODE_PRINTF2("%04x\n", (u16)ip16); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip16, ""); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EIP); + M.x86.R_EIP = ip32 & 0xffff; + } else { + push_word(M.x86.R_IP); + M.x86.R_EIP = ip16; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe9 +****************************************************************************/ +static void x86emuOp_jump_near_IMM(u8 X86EMU_UNUSED(op1)) +{ + s32 ip; + + START_OF_INSTR(); + DECODE_PRINTF("JMP\t"); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + ip = (s32)fetch_long_imm(); + ip += (s32)M.x86.R_EIP; + DECODE_PRINTF2("%08x\n", (u32)ip); + TRACE_AND_STEP(); + M.x86.R_EIP = (u32)ip; + } else { + ip = (s16)fetch_word_imm(); + ip += (s16)M.x86.R_IP; + DECODE_PRINTF2("%04x\n", (u16)ip); + TRACE_AND_STEP(); + M.x86.R_IP = (u16)ip; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xea +****************************************************************************/ +static void x86emuOp_jump_far_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 cs; + u32 ip; + + START_OF_INSTR(); + DECODE_PRINTF("JMP\tFAR "); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + ip = fetch_long_imm(); + } else { + ip = fetch_word_imm(); + } + cs = fetch_word_imm(); + DECODE_PRINTF2("%04x:", cs); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("%08x\n", ip); + } else { + DECODE_PRINTF2("%04x\n", (u16)ip); + } + TRACE_AND_STEP(); + M.x86.R_EIP = ip & 0xffff; + M.x86.R_CS = cs; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xeb +****************************************************************************/ +static void x86emuOp_jump_byte_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 target; + s8 offset; + + START_OF_INSTR(); + DECODE_PRINTF("JMP\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xec +****************************************************************************/ +static void x86emuOp_in_byte_AL_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("IN\tAL,DX\n"); + TRACE_AND_STEP(); + M.x86.R_AL = (*sys_inb)(M.x86.R_DX); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xed +****************************************************************************/ +static void x86emuOp_in_word_AX_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("IN\tEAX,DX\n"); + } else { + DECODE_PRINTF("IN\tAX,DX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = (*sys_inl)(M.x86.R_DX); + } else { + M.x86.R_AX = (*sys_inw)(M.x86.R_DX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xee +****************************************************************************/ +static void x86emuOp_out_byte_DX_AL(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("OUT\tDX,AL\n"); + TRACE_AND_STEP(); + (*sys_outb)(M.x86.R_DX, M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xef +****************************************************************************/ +static void x86emuOp_out_word_DX_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("OUT\tDX,EAX\n"); + } else { + DECODE_PRINTF("OUT\tDX,AX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + (*sys_outl)(M.x86.R_DX, M.x86.R_EAX); + } else { + (*sys_outw)(M.x86.R_DX, M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf0 +****************************************************************************/ +static void x86emuOp_lock(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("LOCK:\n"); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/*opcode 0xf1 ILLEGAL OPERATION */ + +/**************************************************************************** +REMARKS: +Handles opcode 0xf2 +****************************************************************************/ +static void x86emuOp_repne(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("REPNE\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_PREFIX_REPNE; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf3 +****************************************************************************/ +static void x86emuOp_repe(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("REPE\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_PREFIX_REPE; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf4 +****************************************************************************/ +static void x86emuOp_halt(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("HALT\n"); + TRACE_AND_STEP(); + HALT_SYS(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf5 +****************************************************************************/ +static void x86emuOp_cmc(u8 X86EMU_UNUSED(op1)) +{ + /* complement the carry flag. */ + START_OF_INSTR(); + DECODE_PRINTF("CMC\n"); + TRACE_AND_STEP(); + TOGGLE_FLAG(F_CF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf6 +****************************************************************************/ +static void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 destval, srcval; + + /* long, drawn out code follows. Double switch for a total + of 32 cases. */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: /* mod=00 */ + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF("TEST\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + test_byte(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("NOT\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = not_byte(destval); + store_data_byte(destoffset, destval); + break; + case 3: + DECODE_PRINTF("NEG\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = neg_byte(destval); + store_data_byte(destoffset, destval); + break; + case 4: + DECODE_PRINTF("MUL\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + mul_byte(destval); + break; + case 5: + DECODE_PRINTF("IMUL\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + imul_byte(destval); + break; + case 6: + DECODE_PRINTF("DIV\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + div_byte(destval); + break; + case 7: + DECODE_PRINTF("IDIV\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + idiv_byte(destval); + break; + } + break; /* end mod==00 */ + case 1: /* mod=01 */ + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF("TEST\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + test_byte(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=01 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("NOT\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = not_byte(destval); + store_data_byte(destoffset, destval); + break; + case 3: + DECODE_PRINTF("NEG\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = neg_byte(destval); + store_data_byte(destoffset, destval); + break; + case 4: + DECODE_PRINTF("MUL\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + mul_byte(destval); + break; + case 5: + DECODE_PRINTF("IMUL\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + imul_byte(destval); + break; + case 6: + DECODE_PRINTF("DIV\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + div_byte(destval); + break; + case 7: + DECODE_PRINTF("IDIV\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + idiv_byte(destval); + break; + } + break; /* end mod==01 */ + case 2: /* mod=10 */ + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF("TEST\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + test_byte(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=10 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("NOT\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = not_byte(destval); + store_data_byte(destoffset, destval); + break; + case 3: + DECODE_PRINTF("NEG\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = neg_byte(destval); + store_data_byte(destoffset, destval); + break; + case 4: + DECODE_PRINTF("MUL\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + mul_byte(destval); + break; + case 5: + DECODE_PRINTF("IMUL\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + imul_byte(destval); + break; + case 6: + DECODE_PRINTF("DIV\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + div_byte(destval); + break; + case 7: + DECODE_PRINTF("IDIV\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + idiv_byte(destval); + break; + } + break; /* end mod==10 */ + case 3: /* mod=11 */ + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF("TEST\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + TRACE_AND_STEP(); + test_byte(*destreg, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("NOT\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_byte(*destreg); + break; + case 3: + DECODE_PRINTF("NEG\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_byte(*destreg); + break; + case 4: + DECODE_PRINTF("MUL\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_byte(*destreg); /*!!! */ + break; + case 5: + DECODE_PRINTF("IMUL\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_byte(*destreg); + break; + case 6: + DECODE_PRINTF("DIV\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_byte(*destreg); + break; + case 7: + DECODE_PRINTF("IDIV\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_byte(*destreg); + break; + } + break; /* end mod==11 */ + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf7 +****************************************************************************/ +static void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + /* long, drawn out code follows. Double switch for a total + of 32 cases. */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: /* mod=00 */ + switch (rh) { + case 0: /* test word imm */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,srcval; + + DECODE_PRINTF("TEST\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + test_long(destval, srcval); + } else { + u16 destval,srcval; + + DECODE_PRINTF("TEST\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + test_word(destval, srcval); + } + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); + HALT_SYS(); + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NOT\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = not_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NOT\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = not_word(destval); + store_data_word(destoffset, destval); + } + break; + case 3: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NEG\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = neg_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NEG\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = neg_word(destval); + store_data_word(destoffset, destval); + } + break; + case 4: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("MUL\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + mul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("MUL\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + mul_word(destval); + } + break; + case 5: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IMUL\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + imul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IMUL\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + imul_word(destval); + } + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DIV\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + div_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("DIV\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + div_word(destval); + } + break; + case 7: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IDIV\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + idiv_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IDIV\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + idiv_word(destval); + } + break; + } + break; /* end mod==00 */ + case 1: /* mod=01 */ + switch (rh) { + case 0: /* test word imm */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,srcval; + + DECODE_PRINTF("TEST\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + test_long(destval, srcval); + } else { + u16 destval,srcval; + + DECODE_PRINTF("TEST\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + test_word(destval, srcval); + } + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=01 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NOT\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = not_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NOT\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = not_word(destval); + store_data_word(destoffset, destval); + } + break; + case 3: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NEG\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = neg_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NEG\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = neg_word(destval); + store_data_word(destoffset, destval); + } + break; + case 4: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("MUL\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + mul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("MUL\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + mul_word(destval); + } + break; + case 5: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IMUL\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + imul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IMUL\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + imul_word(destval); + } + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DIV\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + div_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("DIV\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + div_word(destval); + } + break; + case 7: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IDIV\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + idiv_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IDIV\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + idiv_word(destval); + } + break; + } + break; /* end mod==01 */ + case 2: /* mod=10 */ + switch (rh) { + case 0: /* test word imm */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,srcval; + + DECODE_PRINTF("TEST\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + test_long(destval, srcval); + } else { + u16 destval,srcval; + + DECODE_PRINTF("TEST\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + test_word(destval, srcval); + } + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=10 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NOT\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = not_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NOT\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = not_word(destval); + store_data_word(destoffset, destval); + } + break; + case 3: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NEG\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = neg_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NEG\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = neg_word(destval); + store_data_word(destoffset, destval); + } + break; + case 4: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("MUL\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + mul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("MUL\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + mul_word(destval); + } + break; + case 5: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IMUL\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + imul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IMUL\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + imul_word(destval); + } + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DIV\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + div_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("DIV\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + div_word(destval); + } + break; + case 7: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IDIV\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + idiv_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IDIV\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + idiv_word(destval); + } + break; + } + break; /* end mod==10 */ + case 3: /* mod=11 */ + switch (rh) { + case 0: /* test word imm */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + DECODE_PRINTF("TEST\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + DECODE_PRINTF("TEST\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_word(*destreg, srcval); + } + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("NOT\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("NOT\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_word(*destreg); + } + break; + case 3: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("NEG\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("NEG\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_word(*destreg); + } + break; + case 4: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("MUL\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_long(*destreg); /*!!! */ + } else { + u16 *destreg; + + DECODE_PRINTF("MUL\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_word(*destreg); /*!!! */ + } + break; + case 5: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("IMUL\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("IMUL\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_word(*destreg); + } + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("DIV\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("DIV\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_word(*destreg); + } + break; + case 7: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("IDIV\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("IDIV\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_word(*destreg); + } + break; + } + break; /* end mod==11 */ + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf8 +****************************************************************************/ +static void x86emuOp_clc(u8 X86EMU_UNUSED(op1)) +{ + /* clear the carry flag. */ + START_OF_INSTR(); + DECODE_PRINTF("CLC\n"); + TRACE_AND_STEP(); + CLEAR_FLAG(F_CF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf9 +****************************************************************************/ +static void x86emuOp_stc(u8 X86EMU_UNUSED(op1)) +{ + /* set the carry flag. */ + START_OF_INSTR(); + DECODE_PRINTF("STC\n"); + TRACE_AND_STEP(); + SET_FLAG(F_CF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfa +****************************************************************************/ +static void x86emuOp_cli(u8 X86EMU_UNUSED(op1)) +{ + /* clear interrupts. */ + START_OF_INSTR(); + DECODE_PRINTF("CLI\n"); + TRACE_AND_STEP(); + CLEAR_FLAG(F_IF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfb +****************************************************************************/ +static void x86emuOp_sti(u8 X86EMU_UNUSED(op1)) +{ + /* enable interrupts. */ + START_OF_INSTR(); + DECODE_PRINTF("STI\n"); + TRACE_AND_STEP(); + SET_FLAG(F_IF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfc +****************************************************************************/ +static void x86emuOp_cld(u8 X86EMU_UNUSED(op1)) +{ + /* clear interrupts. */ + START_OF_INSTR(); + DECODE_PRINTF("CLD\n"); + TRACE_AND_STEP(); + CLEAR_FLAG(F_DF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfd +****************************************************************************/ +static void x86emuOp_std(u8 X86EMU_UNUSED(op1)) +{ + /* clear interrupts. */ + START_OF_INSTR(); + DECODE_PRINTF("STD\n"); + TRACE_AND_STEP(); + SET_FLAG(F_DF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfe +****************************************************************************/ +static void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rh, rl; + u8 destval; + uint destoffset; + u8 *destreg; + + /* Yet another special case instruction. */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("INC\t"); + break; + case 1: + DECODE_PRINTF("DEC\t"); + break; + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod); + HALT_SYS(); + break; + } + } +#endif + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: /* inc word ptr ... */ + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = inc_byte(destval); + store_data_byte(destoffset, destval); + break; + case 1: /* dec word ptr ... */ + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = dec_byte(destval); + store_data_byte(destoffset, destval); + break; + } + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = inc_byte(destval); + store_data_byte(destoffset, destval); + break; + case 1: + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = dec_byte(destval); + store_data_byte(destoffset, destval); + break; + } + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = inc_byte(destval); + store_data_byte(destoffset, destval); + break; + case 1: + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = dec_byte(destval); + store_data_byte(destoffset, destval); + break; + } + break; + case 3: + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + TRACE_AND_STEP(); + *destreg = inc_byte(*destreg); + break; + case 1: + TRACE_AND_STEP(); + *destreg = dec_byte(*destreg); + break; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xff +****************************************************************************/ +static void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rh, rl; + uint destoffset = 0; + u16 *destreg; + u16 destval,destval2; + + /* Yet another special case instruction. */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tDWORD PTR "); + } else { + DECODE_PRINTF("INC\tWORD PTR "); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tDWORD PTR "); + } else { + DECODE_PRINTF("DEC\tWORD PTR "); + } + break; + case 2: + DECODE_PRINTF("CALL\t"); + break; + case 3: + DECODE_PRINTF("CALL\tFAR "); + break; + case 4: + DECODE_PRINTF("JMP\t"); + break; + case 5: + DECODE_PRINTF("JMP\tFAR "); + break; + case 6: + DECODE_PRINTF("PUSH\t"); + break; + case 7: + DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t"); + HALT_SYS(); + break; + } + } +#endif + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: /* inc word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = inc_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = inc_word(destval); + store_data_word(destoffset, destval); + } + break; + case 1: /* dec word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = dec_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = dec_word(destval); + store_data_word(destoffset, destval); + } + break; + case 2: /* call word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 3: /* call far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = destval2; + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 4: /* jmp word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + break; + case 5: /* jmp far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + M.x86.R_CS = destval2; + break; + case 6: /* push word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + push_long(destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(destval); + } + break; + } + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = inc_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = inc_word(destval); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = dec_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = dec_word(destval); + store_data_word(destoffset, destval); + } + break; + case 2: /* call word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 3: /* call far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = destval2; + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 4: /* jmp word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + break; + case 5: /* jmp far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + M.x86.R_CS = destval2; + break; + case 6: /* push word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + push_long(destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(destval); + } + break; + } + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = inc_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = inc_word(destval); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = dec_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = dec_word(destval); + store_data_word(destoffset, destval); + } + break; + case 2: /* call word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 3: /* call far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = destval2; + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 4: /* jmp word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + break; + case 5: /* jmp far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + M.x86.R_CS = destval2; + break; + case 6: /* push word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + push_long(destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(destval); + } + break; + } + break; + case 3: + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = inc_long(*destreg); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = inc_word(*destreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = dec_long(*destreg); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = dec_word(*destreg); + } + break; + case 2: /* call word ptr ... */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = *destreg; + break; + case 3: /* jmp far ptr ... */ + DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + TRACE_AND_STEP(); + HALT_SYS(); + break; + + case 4: /* jmp ... */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + M.x86.R_IP = (u16) (*destreg); + break; + case 5: /* jmp far ptr ... */ + DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + TRACE_AND_STEP(); + HALT_SYS(); + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_long(*destreg); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(*destreg); + } + break; + case 7: + DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + TRACE_AND_STEP(); + HALT_SYS(); + break; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/*************************************************************************** + * Single byte operation code table: + **************************************************************************/ +void (*x86emu_optab[256])(u8) = +{ +/* 0x00 */ x86emuOp_add_byte_RM_R, +/* 0x01 */ x86emuOp_add_word_RM_R, +/* 0x02 */ x86emuOp_add_byte_R_RM, +/* 0x03 */ x86emuOp_add_word_R_RM, +/* 0x04 */ x86emuOp_add_byte_AL_IMM, +/* 0x05 */ x86emuOp_add_word_AX_IMM, +/* 0x06 */ x86emuOp_push_ES, +/* 0x07 */ x86emuOp_pop_ES, + +/* 0x08 */ x86emuOp_or_byte_RM_R, +/* 0x09 */ x86emuOp_or_word_RM_R, +/* 0x0a */ x86emuOp_or_byte_R_RM, +/* 0x0b */ x86emuOp_or_word_R_RM, +/* 0x0c */ x86emuOp_or_byte_AL_IMM, +/* 0x0d */ x86emuOp_or_word_AX_IMM, +/* 0x0e */ x86emuOp_push_CS, +/* 0x0f */ x86emuOp_two_byte, + +/* 0x10 */ x86emuOp_adc_byte_RM_R, +/* 0x11 */ x86emuOp_adc_word_RM_R, +/* 0x12 */ x86emuOp_adc_byte_R_RM, +/* 0x13 */ x86emuOp_adc_word_R_RM, +/* 0x14 */ x86emuOp_adc_byte_AL_IMM, +/* 0x15 */ x86emuOp_adc_word_AX_IMM, +/* 0x16 */ x86emuOp_push_SS, +/* 0x17 */ x86emuOp_pop_SS, + +/* 0x18 */ x86emuOp_sbb_byte_RM_R, +/* 0x19 */ x86emuOp_sbb_word_RM_R, +/* 0x1a */ x86emuOp_sbb_byte_R_RM, +/* 0x1b */ x86emuOp_sbb_word_R_RM, +/* 0x1c */ x86emuOp_sbb_byte_AL_IMM, +/* 0x1d */ x86emuOp_sbb_word_AX_IMM, +/* 0x1e */ x86emuOp_push_DS, +/* 0x1f */ x86emuOp_pop_DS, + +/* 0x20 */ x86emuOp_and_byte_RM_R, +/* 0x21 */ x86emuOp_and_word_RM_R, +/* 0x22 */ x86emuOp_and_byte_R_RM, +/* 0x23 */ x86emuOp_and_word_R_RM, +/* 0x24 */ x86emuOp_and_byte_AL_IMM, +/* 0x25 */ x86emuOp_and_word_AX_IMM, +/* 0x26 */ x86emuOp_segovr_ES, +/* 0x27 */ x86emuOp_daa, + +/* 0x28 */ x86emuOp_sub_byte_RM_R, +/* 0x29 */ x86emuOp_sub_word_RM_R, +/* 0x2a */ x86emuOp_sub_byte_R_RM, +/* 0x2b */ x86emuOp_sub_word_R_RM, +/* 0x2c */ x86emuOp_sub_byte_AL_IMM, +/* 0x2d */ x86emuOp_sub_word_AX_IMM, +/* 0x2e */ x86emuOp_segovr_CS, +/* 0x2f */ x86emuOp_das, + +/* 0x30 */ x86emuOp_xor_byte_RM_R, +/* 0x31 */ x86emuOp_xor_word_RM_R, +/* 0x32 */ x86emuOp_xor_byte_R_RM, +/* 0x33 */ x86emuOp_xor_word_R_RM, +/* 0x34 */ x86emuOp_xor_byte_AL_IMM, +/* 0x35 */ x86emuOp_xor_word_AX_IMM, +/* 0x36 */ x86emuOp_segovr_SS, +/* 0x37 */ x86emuOp_aaa, + +/* 0x38 */ x86emuOp_cmp_byte_RM_R, +/* 0x39 */ x86emuOp_cmp_word_RM_R, +/* 0x3a */ x86emuOp_cmp_byte_R_RM, +/* 0x3b */ x86emuOp_cmp_word_R_RM, +/* 0x3c */ x86emuOp_cmp_byte_AL_IMM, +/* 0x3d */ x86emuOp_cmp_word_AX_IMM, +/* 0x3e */ x86emuOp_segovr_DS, +/* 0x3f */ x86emuOp_aas, + +/* 0x40 */ x86emuOp_inc_AX, +/* 0x41 */ x86emuOp_inc_CX, +/* 0x42 */ x86emuOp_inc_DX, +/* 0x43 */ x86emuOp_inc_BX, +/* 0x44 */ x86emuOp_inc_SP, +/* 0x45 */ x86emuOp_inc_BP, +/* 0x46 */ x86emuOp_inc_SI, +/* 0x47 */ x86emuOp_inc_DI, + +/* 0x48 */ x86emuOp_dec_AX, +/* 0x49 */ x86emuOp_dec_CX, +/* 0x4a */ x86emuOp_dec_DX, +/* 0x4b */ x86emuOp_dec_BX, +/* 0x4c */ x86emuOp_dec_SP, +/* 0x4d */ x86emuOp_dec_BP, +/* 0x4e */ x86emuOp_dec_SI, +/* 0x4f */ x86emuOp_dec_DI, + +/* 0x50 */ x86emuOp_push_AX, +/* 0x51 */ x86emuOp_push_CX, +/* 0x52 */ x86emuOp_push_DX, +/* 0x53 */ x86emuOp_push_BX, +/* 0x54 */ x86emuOp_push_SP, +/* 0x55 */ x86emuOp_push_BP, +/* 0x56 */ x86emuOp_push_SI, +/* 0x57 */ x86emuOp_push_DI, + +/* 0x58 */ x86emuOp_pop_AX, +/* 0x59 */ x86emuOp_pop_CX, +/* 0x5a */ x86emuOp_pop_DX, +/* 0x5b */ x86emuOp_pop_BX, +/* 0x5c */ x86emuOp_pop_SP, +/* 0x5d */ x86emuOp_pop_BP, +/* 0x5e */ x86emuOp_pop_SI, +/* 0x5f */ x86emuOp_pop_DI, + +/* 0x60 */ x86emuOp_push_all, +/* 0x61 */ x86emuOp_pop_all, +/* 0x62 */ x86emuOp_illegal_op, /* bound */ +/* 0x63 */ x86emuOp_illegal_op, /* arpl */ +/* 0x64 */ x86emuOp_segovr_FS, +/* 0x65 */ x86emuOp_segovr_GS, +/* 0x66 */ x86emuOp_prefix_data, +/* 0x67 */ x86emuOp_prefix_addr, + +/* 0x68 */ x86emuOp_push_word_IMM, +/* 0x69 */ x86emuOp_imul_word_IMM, +/* 0x6a */ x86emuOp_push_byte_IMM, +/* 0x6b */ x86emuOp_imul_byte_IMM, +/* 0x6c */ x86emuOp_ins_byte, +/* 0x6d */ x86emuOp_ins_word, +/* 0x6e */ x86emuOp_outs_byte, +/* 0x6f */ x86emuOp_outs_word, + +/* 0x70 */ x86emuOp_jump_near_O, +/* 0x71 */ x86emuOp_jump_near_NO, +/* 0x72 */ x86emuOp_jump_near_B, +/* 0x73 */ x86emuOp_jump_near_NB, +/* 0x74 */ x86emuOp_jump_near_Z, +/* 0x75 */ x86emuOp_jump_near_NZ, +/* 0x76 */ x86emuOp_jump_near_BE, +/* 0x77 */ x86emuOp_jump_near_NBE, + +/* 0x78 */ x86emuOp_jump_near_S, +/* 0x79 */ x86emuOp_jump_near_NS, +/* 0x7a */ x86emuOp_jump_near_P, +/* 0x7b */ x86emuOp_jump_near_NP, +/* 0x7c */ x86emuOp_jump_near_L, +/* 0x7d */ x86emuOp_jump_near_NL, +/* 0x7e */ x86emuOp_jump_near_LE, +/* 0x7f */ x86emuOp_jump_near_NLE, + +/* 0x80 */ x86emuOp_opc80_byte_RM_IMM, +/* 0x81 */ x86emuOp_opc81_word_RM_IMM, +/* 0x82 */ x86emuOp_opc82_byte_RM_IMM, +/* 0x83 */ x86emuOp_opc83_word_RM_IMM, +/* 0x84 */ x86emuOp_test_byte_RM_R, +/* 0x85 */ x86emuOp_test_word_RM_R, +/* 0x86 */ x86emuOp_xchg_byte_RM_R, +/* 0x87 */ x86emuOp_xchg_word_RM_R, + +/* 0x88 */ x86emuOp_mov_byte_RM_R, +/* 0x89 */ x86emuOp_mov_word_RM_R, +/* 0x8a */ x86emuOp_mov_byte_R_RM, +/* 0x8b */ x86emuOp_mov_word_R_RM, +/* 0x8c */ x86emuOp_mov_word_RM_SR, +/* 0x8d */ x86emuOp_lea_word_R_M, +/* 0x8e */ x86emuOp_mov_word_SR_RM, +/* 0x8f */ x86emuOp_pop_RM, + +/* 0x90 */ x86emuOp_nop, +/* 0x91 */ x86emuOp_xchg_word_AX_CX, +/* 0x92 */ x86emuOp_xchg_word_AX_DX, +/* 0x93 */ x86emuOp_xchg_word_AX_BX, +/* 0x94 */ x86emuOp_xchg_word_AX_SP, +/* 0x95 */ x86emuOp_xchg_word_AX_BP, +/* 0x96 */ x86emuOp_xchg_word_AX_SI, +/* 0x97 */ x86emuOp_xchg_word_AX_DI, + +/* 0x98 */ x86emuOp_cbw, +/* 0x99 */ x86emuOp_cwd, +/* 0x9a */ x86emuOp_call_far_IMM, +/* 0x9b */ x86emuOp_wait, +/* 0x9c */ x86emuOp_pushf_word, +/* 0x9d */ x86emuOp_popf_word, +/* 0x9e */ x86emuOp_sahf, +/* 0x9f */ x86emuOp_lahf, + +/* 0xa0 */ x86emuOp_mov_AL_M_IMM, +/* 0xa1 */ x86emuOp_mov_AX_M_IMM, +/* 0xa2 */ x86emuOp_mov_M_AL_IMM, +/* 0xa3 */ x86emuOp_mov_M_AX_IMM, +/* 0xa4 */ x86emuOp_movs_byte, +/* 0xa5 */ x86emuOp_movs_word, +/* 0xa6 */ x86emuOp_cmps_byte, +/* 0xa7 */ x86emuOp_cmps_word, +/* 0xa8 */ x86emuOp_test_AL_IMM, +/* 0xa9 */ x86emuOp_test_AX_IMM, +/* 0xaa */ x86emuOp_stos_byte, +/* 0xab */ x86emuOp_stos_word, +/* 0xac */ x86emuOp_lods_byte, +/* 0xad */ x86emuOp_lods_word, +/* 0xac */ x86emuOp_scas_byte, +/* 0xad */ x86emuOp_scas_word, + + +/* 0xb0 */ x86emuOp_mov_byte_AL_IMM, +/* 0xb1 */ x86emuOp_mov_byte_CL_IMM, +/* 0xb2 */ x86emuOp_mov_byte_DL_IMM, +/* 0xb3 */ x86emuOp_mov_byte_BL_IMM, +/* 0xb4 */ x86emuOp_mov_byte_AH_IMM, +/* 0xb5 */ x86emuOp_mov_byte_CH_IMM, +/* 0xb6 */ x86emuOp_mov_byte_DH_IMM, +/* 0xb7 */ x86emuOp_mov_byte_BH_IMM, + +/* 0xb8 */ x86emuOp_mov_word_AX_IMM, +/* 0xb9 */ x86emuOp_mov_word_CX_IMM, +/* 0xba */ x86emuOp_mov_word_DX_IMM, +/* 0xbb */ x86emuOp_mov_word_BX_IMM, +/* 0xbc */ x86emuOp_mov_word_SP_IMM, +/* 0xbd */ x86emuOp_mov_word_BP_IMM, +/* 0xbe */ x86emuOp_mov_word_SI_IMM, +/* 0xbf */ x86emuOp_mov_word_DI_IMM, + +/* 0xc0 */ x86emuOp_opcC0_byte_RM_MEM, +/* 0xc1 */ x86emuOp_opcC1_word_RM_MEM, +/* 0xc2 */ x86emuOp_ret_near_IMM, +/* 0xc3 */ x86emuOp_ret_near, +/* 0xc4 */ x86emuOp_les_R_IMM, +/* 0xc5 */ x86emuOp_lds_R_IMM, +/* 0xc6 */ x86emuOp_mov_byte_RM_IMM, +/* 0xc7 */ x86emuOp_mov_word_RM_IMM, +/* 0xc8 */ x86emuOp_enter, +/* 0xc9 */ x86emuOp_leave, +/* 0xca */ x86emuOp_ret_far_IMM, +/* 0xcb */ x86emuOp_ret_far, +/* 0xcc */ x86emuOp_int3, +/* 0xcd */ x86emuOp_int_IMM, +/* 0xce */ x86emuOp_into, +/* 0xcf */ x86emuOp_iret, + +/* 0xd0 */ x86emuOp_opcD0_byte_RM_1, +/* 0xd1 */ x86emuOp_opcD1_word_RM_1, +/* 0xd2 */ x86emuOp_opcD2_byte_RM_CL, +/* 0xd3 */ x86emuOp_opcD3_word_RM_CL, +/* 0xd4 */ x86emuOp_aam, +/* 0xd5 */ x86emuOp_aad, +/* 0xd6 */ x86emuOp_illegal_op, /* Undocumented SETALC instruction */ +/* 0xd7 */ x86emuOp_xlat, +/* 0xd8 */ x86emuOp_esc_coprocess_d8, +/* 0xd9 */ x86emuOp_esc_coprocess_d9, +/* 0xda */ x86emuOp_esc_coprocess_da, +/* 0xdb */ x86emuOp_esc_coprocess_db, +/* 0xdc */ x86emuOp_esc_coprocess_dc, +/* 0xdd */ x86emuOp_esc_coprocess_dd, +/* 0xde */ x86emuOp_esc_coprocess_de, +/* 0xdf */ x86emuOp_esc_coprocess_df, + +/* 0xe0 */ x86emuOp_loopne, +/* 0xe1 */ x86emuOp_loope, +/* 0xe2 */ x86emuOp_loop, +/* 0xe3 */ x86emuOp_jcxz, +/* 0xe4 */ x86emuOp_in_byte_AL_IMM, +/* 0xe5 */ x86emuOp_in_word_AX_IMM, +/* 0xe6 */ x86emuOp_out_byte_IMM_AL, +/* 0xe7 */ x86emuOp_out_word_IMM_AX, + +/* 0xe8 */ x86emuOp_call_near_IMM, +/* 0xe9 */ x86emuOp_jump_near_IMM, +/* 0xea */ x86emuOp_jump_far_IMM, +/* 0xeb */ x86emuOp_jump_byte_IMM, +/* 0xec */ x86emuOp_in_byte_AL_DX, +/* 0xed */ x86emuOp_in_word_AX_DX, +/* 0xee */ x86emuOp_out_byte_DX_AL, +/* 0xef */ x86emuOp_out_word_DX_AX, + +/* 0xf0 */ x86emuOp_lock, +/* 0xf1 */ x86emuOp_illegal_op, +/* 0xf2 */ x86emuOp_repne, +/* 0xf3 */ x86emuOp_repe, +/* 0xf4 */ x86emuOp_halt, +/* 0xf5 */ x86emuOp_cmc, +/* 0xf6 */ x86emuOp_opcF6_byte_RM, +/* 0xf7 */ x86emuOp_opcF7_word_RM, + +/* 0xf8 */ x86emuOp_clc, +/* 0xf9 */ x86emuOp_stc, +/* 0xfa */ x86emuOp_cli, +/* 0xfb */ x86emuOp_sti, +/* 0xfc */ x86emuOp_cld, +/* 0xfd */ x86emuOp_std, +/* 0xfe */ x86emuOp_opcFE_byte_RM, +/* 0xff */ x86emuOp_opcFF_word_RM, +}; diff --git a/userspace/sdks/nv570/nvalloc/unix/x86emu/ops2.c b/userspace/sdks/nv570/nvalloc/unix/x86emu/ops2.c new file mode 100644 index 0000000..6053b48 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/x86emu/ops2.c @@ -0,0 +1,2877 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes subroutines to implement the decoding +* and emulation of all the x86 extended two-byte processor +* instructions. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +PARAMETERS: +op1 - Instruction op code + +REMARKS: +Handles illegal opcodes. +****************************************************************************/ +static void x86emuOp2_illegal_op( + u8 op2) +{ + START_OF_INSTR(); + DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); + TRACE_REGS(); +DB( NV_PRINTF(LEVEL_INFO, + "%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n", + M.x86.R_CS, M.x86.R_IP - 2, op2);) + HALT_SYS(); + END_OF_INSTR(); +} + +#define xorl(a,b) ((a) && !(b)) || (!(a) && (b)) + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0x80-0x8F +****************************************************************************/ +static void x86emuOp2_long_jump(u8 op2) +{ + s32 target; + const char *name = 0; + int cond = 0; + + /* conditional jump to word offset. */ + START_OF_INSTR(); + switch (op2) { + case 0x80: + name = "JO\t"; + cond = ACCESS_FLAG(F_OF); + break; + case 0x81: + name = "JNO\t"; + cond = !ACCESS_FLAG(F_OF); + break; + case 0x82: + name = "JB\t"; + cond = ACCESS_FLAG(F_CF); + break; + case 0x83: + name = "JNB\t"; + cond = !ACCESS_FLAG(F_CF); + break; + case 0x84: + name = "JZ\t"; + cond = ACCESS_FLAG(F_ZF); + break; + case 0x85: + name = "JNZ\t"; + cond = !ACCESS_FLAG(F_ZF); + break; + case 0x86: + name = "JBE\t"; + cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); + break; + case 0x87: + name = "JNBE\t"; + cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); + break; + case 0x88: + name = "JS\t"; + cond = ACCESS_FLAG(F_SF); + break; + case 0x89: + name = "JNS\t"; + cond = !ACCESS_FLAG(F_SF); + break; + case 0x8a: + name = "JP\t"; + cond = ACCESS_FLAG(F_PF); + break; + case 0x8b: + name = "JNP\t"; + cond = !ACCESS_FLAG(F_PF); + break; + case 0x8c: + name = "JL\t"; + cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; + case 0x8d: + name = "JNL\t"; + cond = !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; + case 0x8e: + name = "JLE\t"; + cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; + case 0x8f: + name = "JNLE\t"; + cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; + } + DECODE_PRINTF(name); + (void)name; + target = (s16) fetch_word_imm(); + target += (s16) M.x86.R_IP; + DECODE_PRINTF2("%04x\n", target); + TRACE_AND_STEP(); + if (cond) + M.x86.R_IP = (u16)target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0x90-0x9F +****************************************************************************/ +static void x86emuOp2_set_byte(u8 op2) +{ + int mod, rl, rh; + uint destoffset; + u8 *destreg; + const char *name = 0; + int cond = 0; + + START_OF_INSTR(); + switch (op2) { + case 0x90: + name = "SETO\t"; + cond = ACCESS_FLAG(F_OF); + break; + case 0x91: + name = "SETNO\t"; + cond = !ACCESS_FLAG(F_OF); + break; + case 0x92: + name = "SETB\t"; + cond = ACCESS_FLAG(F_CF); + break; + case 0x93: + name = "SETNB\t"; + cond = !ACCESS_FLAG(F_CF); + break; + case 0x94: + name = "SETZ\t"; + cond = ACCESS_FLAG(F_ZF); + break; + case 0x95: + name = "SETNZ\t"; + cond = !ACCESS_FLAG(F_ZF); + break; + case 0x96: + name = "SETBE\t"; + cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); + break; + case 0x97: + name = "SETNBE\t"; + cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); + break; + case 0x98: + name = "SETS\t"; + cond = ACCESS_FLAG(F_SF); + break; + case 0x99: + name = "SETNS\t"; + cond = !ACCESS_FLAG(F_SF); + break; + case 0x9a: + name = "SETP\t"; + cond = ACCESS_FLAG(F_PF); + break; + case 0x9b: + name = "SETNP\t"; + cond = !ACCESS_FLAG(F_PF); + break; + case 0x9c: + name = "SETL\t"; + cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; + case 0x9d: + name = "SETNL\t"; + cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; + case 0x9e: + name = "SETLE\t"; + cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; + case 0x9f: + name = "SETNLE\t"; + cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; + } + DECODE_PRINTF(name); + (void)name; + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, cond ? 0x01 : 0x00); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, cond ? 0x01 : 0x00); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, cond ? 0x01 : 0x00); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = cond ? 0x01 : 0x00; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa0 +****************************************************************************/ +static void x86emuOp2_push_FS(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tFS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_FS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa1 +****************************************************************************/ +static void x86emuOp2_pop_FS(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tFS\n"); + TRACE_AND_STEP(); + M.x86.R_FS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa3 +****************************************************************************/ +static void x86emuOp2_bt_R(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit,disp; + + START_OF_INSTR(); + DECODE_PRINTF("BT\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval; + u32 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } else { + u16 srcval; + u16 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval; + u32 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } else { + u16 srcval; + u16 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval; + u32 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } else { + u16 srcval; + u16 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); + } else { + u16 *srcreg,*shiftreg; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa4 +****************************************************************************/ +static void x86emuOp2_shld_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint destoffset; + u8 shift; + + START_OF_INSTR(); + DECODE_PRINTF("SHLD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shld_long(*destreg,*shiftreg,shift); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shld_word(*destreg,*shiftreg,shift); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa5 +****************************************************************************/ +static void x86emuOp2_shld_CL(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SHLD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shld_long(*destreg,*shiftreg,M.x86.R_CL); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shld_word(*destreg,*shiftreg,M.x86.R_CL); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa8 +****************************************************************************/ +static void x86emuOp2_push_GS(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tGS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_GS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa9 +****************************************************************************/ +static void x86emuOp2_pop_GS(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tGS\n"); + TRACE_AND_STEP(); + M.x86.R_GS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +#if 1 +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xab +****************************************************************************/ +static void x86emuOp2_bts_R(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit,disp; + + START_OF_INSTR(); + DECODE_PRINTF("BTS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval | mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, srcval | mask); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval | mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, srcval | mask); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval | mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, srcval | mask); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg |= mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg |= mask; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} +#endif + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xac +****************************************************************************/ +static void x86emuOp2_shrd_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint destoffset; + u8 shift; + + START_OF_INSTR(); + DECODE_PRINTF("SHLD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shrd_long(*destreg,*shiftreg,shift); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shrd_word(*destreg,*shiftreg,shift); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xad +****************************************************************************/ +static void x86emuOp2_shrd_CL(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SHLD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shrd_long(*destreg,*shiftreg,M.x86.R_CL); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shrd_word(*destreg,*shiftreg,M.x86.R_CL); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xaf +****************************************************************************/ +static void x86emuOp2_imul_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("IMUL\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + res = (s16)*destreg * (s16)srcval; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + res = (s16)*destreg * (s16)srcval; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + res = (s16)*destreg * (s16)srcval; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)*srcreg); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + res = (s16)*destreg * (s16)*srcreg; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb2 +****************************************************************************/ +static void x86emuOp2_lss_R_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LSS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_SS = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_SS = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_SS = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb3 +****************************************************************************/ +static void x86emuOp2_btr_R(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit,disp; + + START_OF_INSTR(); + DECODE_PRINTF("BTR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval & ~mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval & ~mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval & ~mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg &= ~mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg &= ~mask; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb4 +****************************************************************************/ +static void x86emuOp2_lfs_R_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LFS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_FS = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_FS = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_FS = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb5 +****************************************************************************/ +static void x86emuOp2_lgs_R_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LGS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_GS = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_GS = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_GS = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb6 +****************************************************************************/ +static void x86emuOp2_movzx_byte_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOVZX\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb7 +****************************************************************************/ +static void x86emuOp2_movzx_word_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + u32 *destreg; + u32 srcval; + u16 *srcreg; + + START_OF_INSTR(); + DECODE_PRINTF("MOVZX\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 1: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 2: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 3: /* register to register */ + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xba +****************************************************************************/ +static void x86emuOp2_btX_I(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (rh) { + case 4: + DECODE_PRINTF("BT\t"); + break; + case 5: + DECODE_PRINTF("BTS\t"); + break; + case 6: + DECODE_PRINTF("BTR\t"); + break; + case 7: + DECODE_PRINTF("BTC\t"); + break; + default: + DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); + TRACE_REGS(); +DB( NV_PRINTF(LEVEL_INFO, + "%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n", + M.x86.R_CS, M.x86.R_IP - 3, op2, + (mod << 6) | (rh << 3) | rl);) + HALT_SYS(); + } + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, mask; + u8 shift; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = shift & 0x1F; + srcval = fetch_data_long(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_long(srcoffset, srcval | mask); + break; + case 6: + store_data_long(srcoffset, srcval & ~mask); + break; + case 7: + store_data_long(srcoffset, srcval ^ mask); + break; + default: + break; + } + } else { + u16 srcval, mask; + u8 shift; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = shift & 0xF; + srcval = fetch_data_word(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_word(srcoffset, srcval | mask); + break; + case 6: + store_data_word(srcoffset, srcval & ~mask); + break; + case 7: + store_data_word(srcoffset, srcval ^ mask); + break; + default: + break; + } + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, mask; + u8 shift; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = shift & 0x1F; + srcval = fetch_data_long(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_long(srcoffset, srcval | mask); + break; + case 6: + store_data_long(srcoffset, srcval & ~mask); + break; + case 7: + store_data_long(srcoffset, srcval ^ mask); + break; + default: + break; + } + } else { + u16 srcval, mask; + u8 shift; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = shift & 0xF; + srcval = fetch_data_word(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_word(srcoffset, srcval | mask); + break; + case 6: + store_data_word(srcoffset, srcval & ~mask); + break; + case 7: + store_data_word(srcoffset, srcval ^ mask); + break; + default: + break; + } + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, mask; + u8 shift; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = shift & 0x1F; + srcval = fetch_data_long(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_long(srcoffset, srcval | mask); + break; + case 6: + store_data_long(srcoffset, srcval & ~mask); + break; + case 7: + store_data_long(srcoffset, srcval ^ mask); + break; + default: + break; + } + } else { + u16 srcval, mask; + u8 shift; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = shift & 0xF; + srcval = fetch_data_word(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_word(srcoffset, srcval | mask); + break; + case 6: + store_data_word(srcoffset, srcval & ~mask); + break; + case 7: + store_data_word(srcoffset, srcval ^ mask); + break; + default: + break; + } + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 mask; + u8 shift; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = shift & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + switch (rh) { + case 5: + *srcreg |= mask; + break; + case 6: + *srcreg &= ~mask; + break; + case 7: + *srcreg ^= mask; + break; + default: + break; + } + } else { + u16 *srcreg; + u16 mask; + u8 shift; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = shift & 0xF; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + switch (rh) { + case 5: + *srcreg |= mask; + break; + case 6: + *srcreg &= ~mask; + break; + case 7: + *srcreg ^= mask; + break; + default: + break; + } + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbb +****************************************************************************/ +static void x86emuOp2_btc_R(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit,disp; + + START_OF_INSTR(); + DECODE_PRINTF("BTC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval ^ mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval ^ mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval ^ mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg ^= mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg ^= mask; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbc +****************************************************************************/ +static void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("BSF\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch(mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcval = *DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcval = *DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbd +****************************************************************************/ +static void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("BSR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch(mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcval = *DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcval = *DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbe +****************************************************************************/ +static void x86emuOp2_movsx_byte_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOVSX\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = (s32)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = (s16)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = (s32)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = (s16)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = (s32)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = (s16)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s32)((s8)*srcreg); + } else { + u16 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s16)((s8)*srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbf +****************************************************************************/ +static void x86emuOp2_movsx_word_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + u32 *destreg; + u32 srcval; + u16 *srcreg; + + START_OF_INSTR(); + DECODE_PRINTF("MOVSX\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = (s32)((s16)fetch_data_word(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 1: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = (s32)((s16)fetch_data_word(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 2: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = (s32)((s16)fetch_data_word(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 3: /* register to register */ + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s32)((s16)*srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/*************************************************************************** + * Double byte operation code table: + **************************************************************************/ +void (*x86emu_optab2[256])(u8) = +{ +/* 0x00 */ x86emuOp2_illegal_op, /* Group F (ring 0 PM) */ +/* 0x01 */ x86emuOp2_illegal_op, /* Group G (ring 0 PM) */ +/* 0x02 */ x86emuOp2_illegal_op, /* lar (ring 0 PM) */ +/* 0x03 */ x86emuOp2_illegal_op, /* lsl (ring 0 PM) */ +/* 0x04 */ x86emuOp2_illegal_op, +/* 0x05 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ +/* 0x06 */ x86emuOp2_illegal_op, /* clts (ring 0 PM) */ +/* 0x07 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ +/* 0x08 */ x86emuOp2_illegal_op, /* invd (ring 0 PM) */ +/* 0x09 */ x86emuOp2_illegal_op, /* wbinvd (ring 0 PM) */ +/* 0x0a */ x86emuOp2_illegal_op, +/* 0x0b */ x86emuOp2_illegal_op, +/* 0x0c */ x86emuOp2_illegal_op, +/* 0x0d */ x86emuOp2_illegal_op, +/* 0x0e */ x86emuOp2_illegal_op, +/* 0x0f */ x86emuOp2_illegal_op, + +/* 0x10 */ x86emuOp2_illegal_op, +/* 0x11 */ x86emuOp2_illegal_op, +/* 0x12 */ x86emuOp2_illegal_op, +/* 0x13 */ x86emuOp2_illegal_op, +/* 0x14 */ x86emuOp2_illegal_op, +/* 0x15 */ x86emuOp2_illegal_op, +/* 0x16 */ x86emuOp2_illegal_op, +/* 0x17 */ x86emuOp2_illegal_op, +/* 0x18 */ x86emuOp2_illegal_op, +/* 0x19 */ x86emuOp2_illegal_op, +/* 0x1a */ x86emuOp2_illegal_op, +/* 0x1b */ x86emuOp2_illegal_op, +/* 0x1c */ x86emuOp2_illegal_op, +/* 0x1d */ x86emuOp2_illegal_op, +/* 0x1e */ x86emuOp2_illegal_op, +/* 0x1f */ x86emuOp2_illegal_op, + +/* 0x20 */ x86emuOp2_illegal_op, /* mov reg32,creg (ring 0 PM) */ +/* 0x21 */ x86emuOp2_illegal_op, /* mov reg32,dreg (ring 0 PM) */ +/* 0x22 */ x86emuOp2_illegal_op, /* mov creg,reg32 (ring 0 PM) */ +/* 0x23 */ x86emuOp2_illegal_op, /* mov dreg,reg32 (ring 0 PM) */ +/* 0x24 */ x86emuOp2_illegal_op, /* mov reg32,treg (ring 0 PM) */ +/* 0x25 */ x86emuOp2_illegal_op, +/* 0x26 */ x86emuOp2_illegal_op, /* mov treg,reg32 (ring 0 PM) */ +/* 0x27 */ x86emuOp2_illegal_op, +/* 0x28 */ x86emuOp2_illegal_op, +/* 0x29 */ x86emuOp2_illegal_op, +/* 0x2a */ x86emuOp2_illegal_op, +/* 0x2b */ x86emuOp2_illegal_op, +/* 0x2c */ x86emuOp2_illegal_op, +/* 0x2d */ x86emuOp2_illegal_op, +/* 0x2e */ x86emuOp2_illegal_op, +/* 0x2f */ x86emuOp2_illegal_op, + +/* 0x30 */ x86emuOp2_illegal_op, +/* 0x31 */ x86emuOp2_illegal_op, +/* 0x32 */ x86emuOp2_illegal_op, +/* 0x33 */ x86emuOp2_illegal_op, +/* 0x34 */ x86emuOp2_illegal_op, +/* 0x35 */ x86emuOp2_illegal_op, +/* 0x36 */ x86emuOp2_illegal_op, +/* 0x37 */ x86emuOp2_illegal_op, +/* 0x38 */ x86emuOp2_illegal_op, +/* 0x39 */ x86emuOp2_illegal_op, +/* 0x3a */ x86emuOp2_illegal_op, +/* 0x3b */ x86emuOp2_illegal_op, +/* 0x3c */ x86emuOp2_illegal_op, +/* 0x3d */ x86emuOp2_illegal_op, +/* 0x3e */ x86emuOp2_illegal_op, +/* 0x3f */ x86emuOp2_illegal_op, + +/* 0x40 */ x86emuOp2_illegal_op, +/* 0x41 */ x86emuOp2_illegal_op, +/* 0x42 */ x86emuOp2_illegal_op, +/* 0x43 */ x86emuOp2_illegal_op, +/* 0x44 */ x86emuOp2_illegal_op, +/* 0x45 */ x86emuOp2_illegal_op, +/* 0x46 */ x86emuOp2_illegal_op, +/* 0x47 */ x86emuOp2_illegal_op, +/* 0x48 */ x86emuOp2_illegal_op, +/* 0x49 */ x86emuOp2_illegal_op, +/* 0x4a */ x86emuOp2_illegal_op, +/* 0x4b */ x86emuOp2_illegal_op, +/* 0x4c */ x86emuOp2_illegal_op, +/* 0x4d */ x86emuOp2_illegal_op, +/* 0x4e */ x86emuOp2_illegal_op, +/* 0x4f */ x86emuOp2_illegal_op, + +/* 0x50 */ x86emuOp2_illegal_op, +/* 0x51 */ x86emuOp2_illegal_op, +/* 0x52 */ x86emuOp2_illegal_op, +/* 0x53 */ x86emuOp2_illegal_op, +/* 0x54 */ x86emuOp2_illegal_op, +/* 0x55 */ x86emuOp2_illegal_op, +/* 0x56 */ x86emuOp2_illegal_op, +/* 0x57 */ x86emuOp2_illegal_op, +/* 0x58 */ x86emuOp2_illegal_op, +/* 0x59 */ x86emuOp2_illegal_op, +/* 0x5a */ x86emuOp2_illegal_op, +/* 0x5b */ x86emuOp2_illegal_op, +/* 0x5c */ x86emuOp2_illegal_op, +/* 0x5d */ x86emuOp2_illegal_op, +/* 0x5e */ x86emuOp2_illegal_op, +/* 0x5f */ x86emuOp2_illegal_op, + +/* 0x60 */ x86emuOp2_illegal_op, +/* 0x61 */ x86emuOp2_illegal_op, +/* 0x62 */ x86emuOp2_illegal_op, +/* 0x63 */ x86emuOp2_illegal_op, +/* 0x64 */ x86emuOp2_illegal_op, +/* 0x65 */ x86emuOp2_illegal_op, +/* 0x66 */ x86emuOp2_illegal_op, +/* 0x67 */ x86emuOp2_illegal_op, +/* 0x68 */ x86emuOp2_illegal_op, +/* 0x69 */ x86emuOp2_illegal_op, +/* 0x6a */ x86emuOp2_illegal_op, +/* 0x6b */ x86emuOp2_illegal_op, +/* 0x6c */ x86emuOp2_illegal_op, +/* 0x6d */ x86emuOp2_illegal_op, +/* 0x6e */ x86emuOp2_illegal_op, +/* 0x6f */ x86emuOp2_illegal_op, + +/* 0x70 */ x86emuOp2_illegal_op, +/* 0x71 */ x86emuOp2_illegal_op, +/* 0x72 */ x86emuOp2_illegal_op, +/* 0x73 */ x86emuOp2_illegal_op, +/* 0x74 */ x86emuOp2_illegal_op, +/* 0x75 */ x86emuOp2_illegal_op, +/* 0x76 */ x86emuOp2_illegal_op, +/* 0x77 */ x86emuOp2_illegal_op, +/* 0x78 */ x86emuOp2_illegal_op, +/* 0x79 */ x86emuOp2_illegal_op, +/* 0x7a */ x86emuOp2_illegal_op, +/* 0x7b */ x86emuOp2_illegal_op, +/* 0x7c */ x86emuOp2_illegal_op, +/* 0x7d */ x86emuOp2_illegal_op, +/* 0x7e */ x86emuOp2_illegal_op, +/* 0x7f */ x86emuOp2_illegal_op, + +/* 0x80 */ x86emuOp2_long_jump, +/* 0x81 */ x86emuOp2_long_jump, +/* 0x82 */ x86emuOp2_long_jump, +/* 0x83 */ x86emuOp2_long_jump, +/* 0x84 */ x86emuOp2_long_jump, +/* 0x85 */ x86emuOp2_long_jump, +/* 0x86 */ x86emuOp2_long_jump, +/* 0x87 */ x86emuOp2_long_jump, +/* 0x88 */ x86emuOp2_long_jump, +/* 0x89 */ x86emuOp2_long_jump, +/* 0x8a */ x86emuOp2_long_jump, +/* 0x8b */ x86emuOp2_long_jump, +/* 0x8c */ x86emuOp2_long_jump, +/* 0x8d */ x86emuOp2_long_jump, +/* 0x8e */ x86emuOp2_long_jump, +/* 0x8f */ x86emuOp2_long_jump, + +/* 0x90 */ x86emuOp2_set_byte, +/* 0x91 */ x86emuOp2_set_byte, +/* 0x92 */ x86emuOp2_set_byte, +/* 0x93 */ x86emuOp2_set_byte, +/* 0x94 */ x86emuOp2_set_byte, +/* 0x95 */ x86emuOp2_set_byte, +/* 0x96 */ x86emuOp2_set_byte, +/* 0x97 */ x86emuOp2_set_byte, +/* 0x98 */ x86emuOp2_set_byte, +/* 0x99 */ x86emuOp2_set_byte, +/* 0x9a */ x86emuOp2_set_byte, +/* 0x9b */ x86emuOp2_set_byte, +/* 0x9c */ x86emuOp2_set_byte, +/* 0x9d */ x86emuOp2_set_byte, +/* 0x9e */ x86emuOp2_set_byte, +/* 0x9f */ x86emuOp2_set_byte, + +/* 0xa0 */ x86emuOp2_push_FS, +/* 0xa1 */ x86emuOp2_pop_FS, +/* 0xa2 */ x86emuOp2_illegal_op, +/* 0xa3 */ x86emuOp2_bt_R, +/* 0xa4 */ x86emuOp2_shld_IMM, +/* 0xa5 */ x86emuOp2_shld_CL, +/* 0xa6 */ x86emuOp2_illegal_op, +/* 0xa7 */ x86emuOp2_illegal_op, +/* 0xa8 */ x86emuOp2_push_GS, +/* 0xa9 */ x86emuOp2_pop_GS, +/* 0xaa */ x86emuOp2_illegal_op, +/* 0xab */ x86emuOp2_bts_R, +/* 0xac */ x86emuOp2_shrd_IMM, +/* 0xad */ x86emuOp2_shrd_CL, +/* 0xae */ x86emuOp2_illegal_op, +/* 0xaf */ x86emuOp2_imul_R_RM, + +/* 0xb0 */ x86emuOp2_illegal_op, /* TODO: cmpxchg */ +/* 0xb1 */ x86emuOp2_illegal_op, /* TODO: cmpxchg */ +/* 0xb2 */ x86emuOp2_lss_R_IMM, +/* 0xb3 */ x86emuOp2_btr_R, +/* 0xb4 */ x86emuOp2_lfs_R_IMM, +/* 0xb5 */ x86emuOp2_lgs_R_IMM, +/* 0xb6 */ x86emuOp2_movzx_byte_R_RM, +/* 0xb7 */ x86emuOp2_movzx_word_R_RM, +/* 0xb8 */ x86emuOp2_illegal_op, +/* 0xb9 */ x86emuOp2_illegal_op, +/* 0xba */ x86emuOp2_btX_I, +/* 0xbb */ x86emuOp2_btc_R, +/* 0xbc */ x86emuOp2_bsf, +/* 0xbd */ x86emuOp2_bsr, +/* 0xbe */ x86emuOp2_movsx_byte_R_RM, +/* 0xbf */ x86emuOp2_movsx_word_R_RM, + +/* 0xc0 */ x86emuOp2_illegal_op, /* TODO: xadd */ +/* 0xc1 */ x86emuOp2_illegal_op, /* TODO: xadd */ +/* 0xc2 */ x86emuOp2_illegal_op, +/* 0xc3 */ x86emuOp2_illegal_op, +/* 0xc4 */ x86emuOp2_illegal_op, +/* 0xc5 */ x86emuOp2_illegal_op, +/* 0xc6 */ x86emuOp2_illegal_op, +/* 0xc7 */ x86emuOp2_illegal_op, +/* 0xc8 */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xc9 */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xca */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xcb */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xcc */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xcd */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xce */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xcf */ x86emuOp2_illegal_op, /* TODO: bswap */ + +/* 0xd0 */ x86emuOp2_illegal_op, +/* 0xd1 */ x86emuOp2_illegal_op, +/* 0xd2 */ x86emuOp2_illegal_op, +/* 0xd3 */ x86emuOp2_illegal_op, +/* 0xd4 */ x86emuOp2_illegal_op, +/* 0xd5 */ x86emuOp2_illegal_op, +/* 0xd6 */ x86emuOp2_illegal_op, +/* 0xd7 */ x86emuOp2_illegal_op, +/* 0xd8 */ x86emuOp2_illegal_op, +/* 0xd9 */ x86emuOp2_illegal_op, +/* 0xda */ x86emuOp2_illegal_op, +/* 0xdb */ x86emuOp2_illegal_op, +/* 0xdc */ x86emuOp2_illegal_op, +/* 0xdd */ x86emuOp2_illegal_op, +/* 0xde */ x86emuOp2_illegal_op, +/* 0xdf */ x86emuOp2_illegal_op, + +/* 0xe0 */ x86emuOp2_illegal_op, +/* 0xe1 */ x86emuOp2_illegal_op, +/* 0xe2 */ x86emuOp2_illegal_op, +/* 0xe3 */ x86emuOp2_illegal_op, +/* 0xe4 */ x86emuOp2_illegal_op, +/* 0xe5 */ x86emuOp2_illegal_op, +/* 0xe6 */ x86emuOp2_illegal_op, +/* 0xe7 */ x86emuOp2_illegal_op, +/* 0xe8 */ x86emuOp2_illegal_op, +/* 0xe9 */ x86emuOp2_illegal_op, +/* 0xea */ x86emuOp2_illegal_op, +/* 0xeb */ x86emuOp2_illegal_op, +/* 0xec */ x86emuOp2_illegal_op, +/* 0xed */ x86emuOp2_illegal_op, +/* 0xee */ x86emuOp2_illegal_op, +/* 0xef */ x86emuOp2_illegal_op, + +/* 0xf0 */ x86emuOp2_illegal_op, +/* 0xf1 */ x86emuOp2_illegal_op, +/* 0xf2 */ x86emuOp2_illegal_op, +/* 0xf3 */ x86emuOp2_illegal_op, +/* 0xf4 */ x86emuOp2_illegal_op, +/* 0xf5 */ x86emuOp2_illegal_op, +/* 0xf6 */ x86emuOp2_illegal_op, +/* 0xf7 */ x86emuOp2_illegal_op, +/* 0xf8 */ x86emuOp2_illegal_op, +/* 0xf9 */ x86emuOp2_illegal_op, +/* 0xfa */ x86emuOp2_illegal_op, +/* 0xfb */ x86emuOp2_illegal_op, +/* 0xfc */ x86emuOp2_illegal_op, +/* 0xfd */ x86emuOp2_illegal_op, +/* 0xfe */ x86emuOp2_illegal_op, +/* 0xff */ x86emuOp2_illegal_op, +}; diff --git a/userspace/sdks/nv570/nvalloc/unix/x86emu/prim_ops.c b/userspace/sdks/nv570/nvalloc/unix/x86emu/prim_ops.c new file mode 100644 index 0000000..27c1948 --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/x86emu/prim_ops.c @@ -0,0 +1,2655 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file contains the code to implement the primitive +* machine operations used by the emulation code in ops.c +* +* Carry Chain Calculation +* +* This represents a somewhat expensive calculation which is +* apparently required to emulate the setting of the OF and AF flag. +* The latter is not so important, but the former is. The overflow +* flag is the XOR of the top two bits of the carry chain for an +* addition (similar for subtraction). Since we do not want to +* simulate the addition in a bitwise manner, we try to calculate the +* carry chain given the two operands and the result. +* +* So, given the following table, which represents the addition of two +* bits, we can derive a formula for the carry chain. +* +* a b cin r cout +* 0 0 0 0 0 +* 0 0 1 1 0 +* 0 1 0 1 0 +* 0 1 1 0 1 +* 1 0 0 1 0 +* 1 0 1 0 1 +* 1 1 0 0 1 +* 1 1 1 1 1 +* +* Construction of table for cout: +* +* ab +* r \ 00 01 11 10 +* |------------------ +* 0 | 0 1 1 1 +* 1 | 0 0 1 0 +* +* By inspection, one gets: cc = ab + r'(a + b) +* +* That represents alot of operations, but NO CHOICE.... +* +* Borrow Chain Calculation. +* +* The following table represents the subtraction of two bits, from +* which we can derive a formula for the borrow chain. +* +* a b bin r bout +* 0 0 0 0 0 +* 0 0 1 1 1 +* 0 1 0 1 1 +* 0 1 1 0 1 +* 1 0 0 1 0 +* 1 0 1 0 0 +* 1 1 0 0 0 +* 1 1 1 1 1 +* +* Construction of table for cout: +* +* ab +* r \ 00 01 11 10 +* |------------------ +* 0 | 0 1 0 0 +* 1 | 1 1 1 0 +* +* By inspection, one gets: bc = a'b + r(a' + b) +* +****************************************************************************/ + +#define PRIM_OPS_NO_REDEFINE_ASM +#include "x86emu/x86emui.h" + +/*------------------------- Global Variables ------------------------------*/ + +static u32 x86emu_parity_tab[8] = +{ + 0x96696996, + 0x69969669, + 0x69969669, + 0x96696996, + 0x69969669, + 0x96696996, + 0x96696996, + 0x69969669, +}; + +#define PARITY(x) (((x86emu_parity_tab[(x) / 32] >> ((x) % 32)) & 1) == 0) +#define XOR2(x) (((x) ^ ((x)>>1)) & 0x1) + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Implements the AAA instruction and side effects. +****************************************************************************/ +u16 aaa_word(u16 d) +{ + u16 res; + if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) { + d += 0x6; + d += 0x100; + SET_FLAG(F_AF); + SET_FLAG(F_CF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + } + res = (u16)(d & 0xFF0F); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AAA instruction and side effects. +****************************************************************************/ +u16 aas_word(u16 d) +{ + u16 res; + if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) { + d -= 0x6; + d -= 0x100; + SET_FLAG(F_AF); + SET_FLAG(F_CF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + } + res = (u16)(d & 0xFF0F); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AAD instruction and side effects. +****************************************************************************/ +u16 aad_word(u16 d) +{ + u16 l; + u8 hb, lb; + + hb = (u8)((d >> 8) & 0xff); + lb = (u8)((d & 0xff)); + l = (u16)((lb + 10 * hb) & 0xFF); + + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(l & 0x80, F_SF); + CONDITIONAL_SET_FLAG(l == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(l & 0xff), F_PF); + return l; +} + +/**************************************************************************** +REMARKS: +Implements the AAM instruction and side effects. +****************************************************************************/ +u16 aam_word(u8 d) +{ + u16 h, l; + + h = (u16)(d / 10); + l = (u16)(d % 10); + l |= (u16)(h << 8); + + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(l & 0x80, F_SF); + CONDITIONAL_SET_FLAG(l == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(l & 0xff), F_PF); + return l; +} + +/**************************************************************************** +REMARKS: +Implements the ADC instruction and side effects. +****************************************************************************/ +u8 adc_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + if (ACCESS_FLAG(F_CF)) + res = 1 + d + s; + else + res = d + s; + + CONDITIONAL_SET_FLAG(res & 0x100, F_CF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the ADC instruction and side effects. +****************************************************************************/ +u16 adc_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + if (ACCESS_FLAG(F_CF)) + res = 1 + d + s; + else + res = d + s; + + CONDITIONAL_SET_FLAG(res & 0x10000, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the ADC instruction and side effects. +****************************************************************************/ +u32 adc_long(u32 d, u32 s) +{ + register u32 lo; /* all operands in native machine order */ + register u32 hi; + register u32 res; + register u32 cc; + + if (ACCESS_FLAG(F_CF)) { + lo = 1 + (d & 0xFFFF) + (s & 0xFFFF); + res = 1 + d + s; + } + else { + lo = (d & 0xFFFF) + (s & 0xFFFF); + res = d + s; + } + hi = (lo >> 16) + (d >> 16) + (s >> 16); + + CONDITIONAL_SET_FLAG(hi & 0x10000, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the ADD instruction and side effects. +****************************************************************************/ +u8 add_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + s; + CONDITIONAL_SET_FLAG(res & 0x100, F_CF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the ADD instruction and side effects. +****************************************************************************/ +u16 add_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + s; + CONDITIONAL_SET_FLAG(res & 0x10000, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the ADD instruction and side effects. +****************************************************************************/ +u32 add_long(u32 d, u32 s) +{ + register u32 lo; /* all operands in native machine order */ + register u32 hi; + register u32 res; + register u32 cc; + + lo = (d & 0xFFFF) + (s & 0xFFFF); + res = d + s; + hi = (lo >> 16) + (d >> 16) + (s >> 16); + + CONDITIONAL_SET_FLAG(hi & 0x10000, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AND instruction and side effects. +****************************************************************************/ +u8 and_byte(u8 d, u8 s) +{ + register u8 res; /* all operands in native machine order */ + + res = d & s; + + /* set the flags */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AND instruction and side effects. +****************************************************************************/ +u16 and_word(u16 d, u16 s) +{ + register u16 res; /* all operands in native machine order */ + + res = d & s; + + /* set the flags */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AND instruction and side effects. +****************************************************************************/ +u32 and_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d & s; + + /* set the flags */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the CMP instruction and side effects. +****************************************************************************/ +u8 cmp_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CLEAR_FLAG(F_CF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return d; +} + +/**************************************************************************** +REMARKS: +Implements the CMP instruction and side effects. +****************************************************************************/ +u16 cmp_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return d; +} + +/**************************************************************************** +REMARKS: +Implements the CMP instruction and side effects. +****************************************************************************/ +u32 cmp_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return d; +} + +/**************************************************************************** +REMARKS: +Implements the DAA instruction and side effects. +****************************************************************************/ +u8 daa_byte(u8 d) +{ + u32 res = d; + if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) { + res += 6; + SET_FLAG(F_AF); + } + if (res > 0x9F || ACCESS_FLAG(F_CF)) { + res += 0x60; + SET_FLAG(F_CF); + } + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xFF) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the DAS instruction and side effects. +****************************************************************************/ +u8 das_byte(u8 d) +{ + if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) { + d -= 6; + SET_FLAG(F_AF); + } + if (d > 0x9F || ACCESS_FLAG(F_CF)) { + d -= 0x60; + SET_FLAG(F_CF); + } + CONDITIONAL_SET_FLAG(d & 0x80, F_SF); + CONDITIONAL_SET_FLAG(d == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(d & 0xff), F_PF); + return d; +} + +/**************************************************************************** +REMARKS: +Implements the DEC instruction and side effects. +****************************************************************************/ +u8 dec_byte(u8 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - 1; + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + /* based on sub_byte, uses s==1. */ + bc = (res & (~d | 1)) | (~d & 1); + /* carry flag unchanged */ + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the DEC instruction and side effects. +****************************************************************************/ +u16 dec_word(u16 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - 1; + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + /* based on the sub_byte routine, with s==1 */ + bc = (res & (~d | 1)) | (~d & 1); + /* carry flag unchanged */ + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the DEC instruction and side effects. +****************************************************************************/ +u32 dec_long(u32 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - 1; + + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | 1)) | (~d & 1); + /* carry flag unchanged */ + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the INC instruction and side effects. +****************************************************************************/ +u8 inc_byte(u8 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + 1; + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = ((1 & d) | (~res)) & (1 | d); + CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the INC instruction and side effects. +****************************************************************************/ +u16 inc_word(u16 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + 1; + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (1 & d) | ((~res) & (1 | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the INC instruction and side effects. +****************************************************************************/ +u32 inc_long(u32 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + 1; + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (1 & d) | ((~res) & (1 | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u8 or_byte(u8 d, u8 s) +{ + register u8 res; /* all operands in native machine order */ + + res = d | s; + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u16 or_word(u16 d, u16 s) +{ + register u16 res; /* all operands in native machine order */ + + res = d | s; + /* set the carry flag to be bit 8 */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u32 or_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d | s; + + /* set the carry flag to be bit 8 */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u8 neg_byte(u8 s) +{ + register u8 res; + register u8 bc; + + CONDITIONAL_SET_FLAG(s != 0, F_CF); + res = (u8)-s; + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res), F_PF); + /* calculate the borrow chain --- modified such that d=0. + substitutiing d=0 into bc= res&(~d|s)|(~d&s); + (the one used for sub) and simplifying, since ~d=0xff..., + ~d|s == 0xffff..., and res&0xfff... == res. Similarly + ~d&s == s. So the simplified result is: */ + bc = res | s; + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u16 neg_word(u16 s) +{ + register u16 res; + register u16 bc; + + CONDITIONAL_SET_FLAG(s != 0, F_CF); + res = (u16)-s; + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain --- modified such that d=0. + substitutiing d=0 into bc= res&(~d|s)|(~d&s); + (the one used for sub) and simplifying, since ~d=0xff..., + ~d|s == 0xffff..., and res&0xfff... == res. Similarly + ~d&s == s. So the simplified result is: */ + bc = res | s; + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u32 neg_long(u32 s) +{ + register u32 res; + register u32 bc; + + CONDITIONAL_SET_FLAG(s != 0, F_CF); + res = (u32)-s; + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain --- modified such that d=0. + substitutiing d=0 into bc= res&(~d|s)|(~d&s); + (the one used for sub) and simplifying, since ~d=0xff..., + ~d|s == 0xffff..., and res&0xfff... == res. Similarly + ~d&s == s. So the simplified result is: */ + bc = res | s; + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the NOT instruction and side effects. +****************************************************************************/ +u8 not_byte(u8 s) +{ + return ~s; +} + +/**************************************************************************** +REMARKS: +Implements the NOT instruction and side effects. +****************************************************************************/ +u16 not_word(u16 s) +{ + return ~s; +} + +/**************************************************************************** +REMARKS: +Implements the NOT instruction and side effects. +****************************************************************************/ +u32 not_long(u32 s) +{ + return ~s; +} + +/**************************************************************************** +REMARKS: +Implements the RCL instruction and side effects. +****************************************************************************/ +u8 rcl_byte(u8 d, u8 s) +{ + register unsigned int res, cnt, mask, cf; + + /* s is the rotate distance. It varies from 0 - 8. */ + /* have + + CF B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 + + want to rotate through the carry by "s" bits. We could + loop, but that's inefficient. So the width is 9, + and we split into three parts: + + The new carry flag (was B_n) + the stuff in B_n-1 .. B_0 + the stuff in B_7 .. B_n+1 + + The new rotate is done mod 9, and given this, + for a rotation of n bits (mod 9) the new carry flag is + then located n bits from the MSB. The low part is + then shifted up cnt bits, and the high part is or'd + in. Using CAPS for new values, and lowercase for the + original values, this can be expressed as: + + IF n > 0 + 1) CF <- b_(8-n) + 2) B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 + 3) B_(n-1) <- cf + 4) B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) + */ + res = d; + if ((cnt = s % 9) != 0) { + /* extract the new CARRY FLAG. */ + /* CF <- b_(8-n) */ + cf = (d >> (8 - cnt)) & 0x1; + + /* get the low stuff which rotated + into the range B_7 .. B_cnt */ + /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 */ + /* note that the right hand side done by the mask */ + res = (d << cnt) & 0xff; + + /* now the high stuff which rotated around + into the positions B_cnt-2 .. B_0 */ + /* B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) */ + /* shift it downward, 7-(n-2) = 9-n positions. + and mask off the result before or'ing in. + */ + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (9 - cnt)) & mask; + + /* if the carry flag was set, or it in. */ + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + /* B_(n-1) <- cf */ + res |= 1 << (cnt - 1); + } + /* set the new carry flag, based on the variable "cf" */ + CONDITIONAL_SET_FLAG(cf, F_CF); + /* OVERFLOW is set *IFF* cnt==1, then it is the + xor of CF and the most significant bit. Blecck. */ + /* parenthesized this expression since it appears to + be causing OF to be misset */ + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 6) & 0x2)), + F_OF); + + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the RCL instruction and side effects. +****************************************************************************/ +u16 rcl_word(u16 d, u8 s) +{ + register unsigned int res, cnt, mask, cf; + + res = d; + if ((cnt = s % 17) != 0) { + cf = (d >> (16 - cnt)) & 0x1; + res = (d << cnt) & 0xffff; + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (17 - cnt)) & mask; + if (ACCESS_FLAG(F_CF)) { + res |= 1 << (cnt - 1); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 14) & 0x2)), + F_OF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the RCL instruction and side effects. +****************************************************************************/ +u32 rcl_long(u32 d, u8 s) +{ + register u32 res, cnt, mask, cf; + + res = d; + if ((cnt = s % 33) != 0) { + cf = (d >> (32 - cnt)) & 0x1; + res = (d << cnt) & 0xffffffff; + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (33 - cnt)) & mask; + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + res |= 1 << (cnt - 1); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 30) & 0x2)), + F_OF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the RCR instruction and side effects. +****************************************************************************/ +u8 rcr_byte(u8 d, u8 s) +{ + u32 res, cnt; + u32 mask, cf, ocf = 0; + + /* rotate right through carry */ + /* + s is the rotate distance. It varies from 0 - 8. + d is the byte object rotated. + + have + + CF B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 + + The new rotate is done mod 9, and given this, + for a rotation of n bits (mod 9) the new carry flag is + then located n bits from the LSB. The low part is + then shifted up cnt bits, and the high part is or'd + in. Using CAPS for new values, and lowercase for the + original values, this can be expressed as: + + IF n > 0 + 1) CF <- b_(n-1) + 2) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) + 3) B_(8-n) <- cf + 4) B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) + */ + res = d; + if ((cnt = s % 9) != 0) { + /* extract the new CARRY FLAG. */ + /* CF <- b_(n-1) */ + if (cnt == 1) { + cf = d & 0x1; + /* note hackery here. Access_flag(..) evaluates to either + 0 if flag not set + non-zero if flag is set. + doing access_flag(..) != 0 casts that into either + 0..1 in any representation of the flags register + (i.e. packed bit array or unpacked.) + */ + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + + /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_n */ + /* note that the right hand side done by the mask + This is effectively done by shifting the + object to the right. The result must be masked, + in case the object came in and was treated + as a negative number. Needed??? */ + + mask = (1 << (8 - cnt)) - 1; + res = (d >> cnt) & mask; + + /* now the high stuff which rotated around + into the positions B_cnt-2 .. B_0 */ + /* B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) */ + /* shift it downward, 7-(n-2) = 9-n positions. + and mask off the result before or'ing in. + */ + res |= (d << (9 - cnt)); + + /* if the carry flag was set, or it in. */ + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + /* B_(8-n) <- cf */ + res |= 1 << (8 - cnt); + } + /* set the new carry flag, based on the variable "cf" */ + CONDITIONAL_SET_FLAG(cf, F_CF); + /* OVERFLOW is set *IFF* cnt==1, then it is the + xor of CF and the most significant bit. Blecck. */ + /* parenthesized... */ + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 6) & 0x2)), + F_OF); + } + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the RCR instruction and side effects. +****************************************************************************/ +u16 rcr_word(u16 d, u8 s) +{ + u32 res, cnt; + u32 mask, cf, ocf = 0; + + /* rotate right through carry */ + res = d; + if ((cnt = s % 17) != 0) { + if (cnt == 1) { + cf = d & 0x1; + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + mask = (1 << (16 - cnt)) - 1; + res = (d >> cnt) & mask; + res |= (d << (17 - cnt)); + if (ACCESS_FLAG(F_CF)) { + res |= 1 << (16 - cnt); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 14) & 0x2)), + F_OF); + } + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the RCR instruction and side effects. +****************************************************************************/ +u32 rcr_long(u32 d, u8 s) +{ + u32 res, cnt; + u32 mask, cf, ocf = 0; + + /* rotate right through carry */ + res = d; + if ((cnt = s % 33) != 0) { + if (cnt == 1) { + cf = d & 0x1; + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + mask = (1 << (32 - cnt)) - 1; + res = (d >> cnt) & mask; + if (cnt != 1) + res |= (d << (33 - cnt)); + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + res |= 1 << (32 - cnt); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 30) & 0x2)), + F_OF); + } + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the ROL instruction and side effects. +****************************************************************************/ +u8 rol_byte(u8 d, u8 s) +{ + register unsigned int res, cnt, mask; + + /* rotate left */ + /* + s is the rotate distance. It varies from 0 - 8. + d is the byte object rotated. + + have + + CF B_7 ... B_0 + + The new rotate is done mod 8. + Much simpler than the "rcl" or "rcr" operations. + + IF n > 0 + 1) B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) + 2) B_(n-1) .. B_(0) <- b_(7) .. b_(8-n) + */ + res = d; + if ((cnt = s % 8) != 0) { + /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) */ + res = (d << cnt); + + /* B_(n-1) .. B_(0) <- b_(7) .. b_(8-n) */ + mask = (1 << cnt) - 1; + res |= (d >> (8 - cnt)) & mask; + + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + /* OVERFLOW is set *IFF* s==1, then it is the + xor of CF and the most significant bit. Blecck. */ + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 6) & 0x2)), + F_OF); + } if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the ROL instruction and side effects. +****************************************************************************/ +u16 rol_word(u16 d, u8 s) +{ + register unsigned int res, cnt, mask; + + res = d; + if ((cnt = s % 16) != 0) { + res = (d << cnt); + mask = (1 << cnt) - 1; + res |= (d >> (16 - cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 14) & 0x2)), + F_OF); + } if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the ROL instruction and side effects. +****************************************************************************/ +u32 rol_long(u32 d, u8 s) +{ + register u32 res, cnt, mask; + + res = d; + if ((cnt = s % 32) != 0) { + res = (d << cnt); + mask = (1 << cnt) - 1; + res |= (d >> (32 - cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 30) & 0x2)), + F_OF); + } if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the ROR instruction and side effects. +****************************************************************************/ +u8 ror_byte(u8 d, u8 s) +{ + register unsigned int res, cnt, mask; + + /* rotate right */ + /* + s is the rotate distance. It varies from 0 - 8. + d is the byte object rotated. + + have + + B_7 ... B_0 + + The rotate is done mod 8. + + IF n > 0 + 1) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) + 2) B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) + */ + res = d; + if ((cnt = s % 8) != 0) { /* not a typo, do nada if cnt==0 */ + /* B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) */ + res = (d << (8 - cnt)); + + /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) */ + mask = (1 << (8 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80, F_CF); + /* OVERFLOW is set *IFF* s==1, then it is the + xor of the two most significant bits. Blecck. */ + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 6), F_OF); + } else if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80, F_CF); + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the ROR instruction and side effects. +****************************************************************************/ +u16 ror_word(u16 d, u8 s) +{ + register unsigned int res, cnt, mask; + + res = d; + if ((cnt = s % 16) != 0) { + res = (d << (16 - cnt)); + mask = (1 << (16 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 14), F_OF); + } else if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the ROR instruction and side effects. +****************************************************************************/ +u32 ror_long(u32 d, u8 s) +{ + register u32 res, cnt, mask; + + res = d; + if ((cnt = s % 32) != 0) { + res = (d << (32 - cnt)); + mask = (1 << (32 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 30), F_OF); + } else if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SHL instruction and side effects. +****************************************************************************/ +u8 shl_byte(u8 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 8) { + cnt = s % 8; + + /* last bit shifted out goes into carry flag */ + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (8 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = (u8) d; + } + + if (cnt == 1) { + /* Needs simplification. */ + CONDITIONAL_SET_FLAG( + (((res & 0x80) == 0x80) ^ + (ACCESS_FLAG(F_CF) != 0)), + /* was (M.x86.R_FLG&F_CF)==F_CF)), */ + F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHL instruction and side effects. +****************************************************************************/ +u16 shl_word(u16 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = (u16) d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG( + (((res & 0x8000) == 0x8000) ^ + (ACCESS_FLAG(F_CF) != 0)), + F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHL instruction and side effects. +****************************************************************************/ +u32 shl_long(u32 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SHR instruction and side effects. +****************************************************************************/ +u8 shr_byte(u8 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 8) { + cnt = s % 8; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = (u8) d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 6), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d >> (s-1)) & 0x1, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHR instruction and side effects. +****************************************************************************/ +u16 shr_word(u16 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHR instruction and side effects. +****************************************************************************/ +u32 shr_long(u32 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SAR instruction and side effects. +****************************************************************************/ +u8 sar_byte(u8 d, u8 s) +{ + unsigned int cnt, res, cf, mask, sf; + + res = d; + sf = d & 0x80; + cnt = s % 8; + if (cnt > 0 && cnt < 8) { + mask = (1 << (8 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + } else if (cnt >= 8) { + if (sf) { + res = 0xff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SAR instruction and side effects. +****************************************************************************/ +u16 sar_word(u16 d, u8 s) +{ + unsigned int cnt, res, cf, mask, sf; + + sf = d & 0x8000; + cnt = s % 16; + res = d; + if (cnt > 0 && cnt < 16) { + mask = (1 << (16 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else if (cnt >= 16) { + if (sf) { + res = 0xffff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SAR instruction and side effects. +****************************************************************************/ +u32 sar_long(u32 d, u8 s) +{ + u32 cnt, res, cf, mask, sf; + + sf = d & 0x80000000; + cnt = s % 32; + res = d; + if (cnt > 0 && cnt < 32) { + mask = (1 << (32 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else if (cnt >= 32) { + if (sf) { + res = 0xffffffff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SHLD instruction and side effects. +****************************************************************************/ +u16 shld_word (u16 d, u16 fill, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + res = (d << cnt) | (fill >> (16-cnt)); + cf = d & (1 << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x8000) == 0x8000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHLD instruction and side effects. +****************************************************************************/ +u32 shld_long (u32 d, u32 fill, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + res = (d << cnt) | (fill >> (32-cnt)); + cf = d & (1 << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SHRD instruction and side effects. +****************************************************************************/ +u16 shrd_word (u16 d, u16 fill, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) | (fill << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHRD instruction and side effects. +****************************************************************************/ +u32 shrd_long (u32 d, u32 fill, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) | (fill << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SBB instruction and side effects. +****************************************************************************/ +u8 sbb_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + if (ACCESS_FLAG(F_CF)) + res = d - s - 1; + else + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SBB instruction and side effects. +****************************************************************************/ +u16 sbb_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + if (ACCESS_FLAG(F_CF)) + res = d - s - 1; + else + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SBB instruction and side effects. +****************************************************************************/ +u32 sbb_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + if (ACCESS_FLAG(F_CF)) + res = d - s - 1; + else + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SUB instruction and side effects. +****************************************************************************/ +u8 sub_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SUB instruction and side effects. +****************************************************************************/ +u16 sub_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SUB instruction and side effects. +****************************************************************************/ +u32 sub_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the TEST instruction and side effects. +****************************************************************************/ +void test_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d & s; + + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + /* AF == dont care */ + CLEAR_FLAG(F_CF); +} + +/**************************************************************************** +REMARKS: +Implements the TEST instruction and side effects. +****************************************************************************/ +void test_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d & s; + + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + /* AF == dont care */ + CLEAR_FLAG(F_CF); +} + +/**************************************************************************** +REMARKS: +Implements the TEST instruction and side effects. +****************************************************************************/ +void test_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d & s; + + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + /* AF == dont care */ + CLEAR_FLAG(F_CF); +} + +/**************************************************************************** +REMARKS: +Implements the XOR instruction and side effects. +****************************************************************************/ +u8 xor_byte(u8 d, u8 s) +{ + register u8 res; /* all operands in native machine order */ + + res = d ^ s; + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res), F_PF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the XOR instruction and side effects. +****************************************************************************/ +u16 xor_word(u16 d, u16 s) +{ + register u16 res; /* all operands in native machine order */ + + res = d ^ s; + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the XOR instruction and side effects. +****************************************************************************/ +u32 xor_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d ^ s; + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +void imul_byte(u8 s) +{ + s16 res = (s16)((s8)M.x86.R_AL * (s8)s); + + M.x86.R_AX = res; + if (((M.x86.R_AL & 0x80) == 0 && M.x86.R_AH == 0x00) || + ((M.x86.R_AL & 0x80) != 0 && M.x86.R_AH == 0xFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +void imul_word(u16 s) +{ + s32 res = (s16)M.x86.R_AX * (s16)s; + + M.x86.R_AX = (u16)res; + M.x86.R_DX = (u16)(res >> 16); + if (((M.x86.R_AX & 0x8000) == 0 && M.x86.R_DX == 0x00) || + ((M.x86.R_AX & 0x8000) != 0 && M.x86.R_DX == 0xFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s) +{ +#ifdef __HAS_LONG_LONG__ + s64 res = (s64)(s32)d * (s32)s; + + *res_lo = (u32)res; + *res_hi = (u32)(res >> 32); +#else + u32 d_lo,d_hi,d_sign; + u32 s_lo,s_hi,s_sign; + u32 rlo_lo,rlo_hi,rhi_lo; + + if ((d_sign = d & 0x80000000) != 0) + d = -d; + d_lo = d & 0xFFFF; + d_hi = d >> 16; + if ((s_sign = s & 0x80000000) != 0) + s = -s; + s_lo = s & 0xFFFF; + s_hi = s >> 16; + rlo_lo = d_lo * s_lo; + rlo_hi = (d_hi * s_lo + d_lo * s_hi) + (rlo_lo >> 16); + rhi_lo = d_hi * s_hi + (rlo_hi >> 16); + *res_lo = (rlo_hi << 16) | (rlo_lo & 0xFFFF); + *res_hi = rhi_lo; + if (d_sign != s_sign) { + d = ~*res_lo; + s = (((d & 0xFFFF) + 1) >> 16) + (d >> 16); + *res_lo = ~*res_lo+1; + *res_hi = ~*res_hi+(s >> 16); + } +#endif +} + +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +void imul_long(u32 s) +{ + imul_long_direct(&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s); + if (((M.x86.R_EAX & 0x80000000) == 0 && M.x86.R_EDX == 0x00) || + ((M.x86.R_EAX & 0x80000000) != 0 && M.x86.R_EDX == 0xFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the MUL instruction and side effects. +****************************************************************************/ +void mul_byte(u8 s) +{ + u16 res = (u16)(M.x86.R_AL * s); + + M.x86.R_AX = res; + if (M.x86.R_AH == 0) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the MUL instruction and side effects. +****************************************************************************/ +void mul_word(u16 s) +{ + u32 res = M.x86.R_AX * s; + + M.x86.R_AX = (u16)res; + M.x86.R_DX = (u16)(res >> 16); + if (M.x86.R_DX == 0) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the MUL instruction and side effects. +****************************************************************************/ +void mul_long(u32 s) +{ +#ifdef __HAS_LONG_LONG__ + u64 res = (u64)M.x86.R_EAX * s; + + M.x86.R_EAX = (u32)res; + M.x86.R_EDX = (u32)(res >> 32); +#else + u32 a,a_lo,a_hi; + u32 s_lo,s_hi; + u32 rlo_lo,rlo_hi,rhi_lo; + + a = M.x86.R_EAX; + a_lo = a & 0xFFFF; + a_hi = a >> 16; + s_lo = s & 0xFFFF; + s_hi = s >> 16; + rlo_lo = a_lo * s_lo; + rlo_hi = (a_hi * s_lo + a_lo * s_hi) + (rlo_lo >> 16); + rhi_lo = a_hi * s_hi + (rlo_hi >> 16); + M.x86.R_EAX = (rlo_hi << 16) | (rlo_lo & 0xFFFF); + M.x86.R_EDX = rhi_lo; +#endif + + if (M.x86.R_EDX == 0) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the IDIV instruction and side effects. +****************************************************************************/ +void idiv_byte(u8 s) +{ + s32 dvd, div, mod; + + dvd = (s16)M.x86.R_AX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (s8)s; + mod = dvd % (s8)s; + if (abs(div) > 0x7f) { + x86emu_intr_raise(0); + return; + } + M.x86.R_AL = (s8) div; + M.x86.R_AH = (s8) mod; +} + +/**************************************************************************** +REMARKS: +Implements the IDIV instruction and side effects. +****************************************************************************/ +void idiv_word(u16 s) +{ + s32 dvd, div, mod; + + dvd = (((s32)M.x86.R_DX) << 16) | M.x86.R_AX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (s16)s; + mod = dvd % (s16)s; + if (abs(div) > 0x7fff) { + x86emu_intr_raise(0); + return; + } + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(div == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); + + M.x86.R_AX = (u16)div; + M.x86.R_DX = (u16)mod; +} + +/**************************************************************************** +REMARKS: +Implements the IDIV instruction and side effects. +****************************************************************************/ +void idiv_long(u32 s) +{ +#ifdef __HAS_LONG_LONG__ + s64 dvd, div, mod; + + dvd = (((s64)M.x86.R_EDX) << 32) | M.x86.R_EAX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (s32)s; + mod = dvd % (s32)s; + if (((u64)div >> 32) != 0 && + ((u64)div >> 32) != 0xFFFFFFFFUL) { + x86emu_intr_raise(0); + return; + } +#else + s32 div = 0, mod; + s32 h_dvd = M.x86.R_EDX; + u32 l_dvd = M.x86.R_EAX; + u32 abs_s = s & 0x7FFFFFFF; + u32 abs_h_dvd = h_dvd & 0x7FFFFFFF; + u32 h_s = abs_s >> 1; + u32 l_s = abs_s << 31; + int counter = 31; + int carry; + + if (s == 0) { + x86emu_intr_raise(0); + return; + } + do { + div <<= 1; + carry = (l_dvd >= l_s) ? 0 : 1; + + if (abs_h_dvd < (h_s + carry)) { + h_s >>= 1; + l_s = abs_s << (--counter); + continue; + } else { + abs_h_dvd -= (h_s + carry); + l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) + : (l_dvd - l_s); + h_s >>= 1; + l_s = abs_s << (--counter); + div |= 1; + continue; + } + + } while (counter > -1); + /* overflow */ + if (abs_h_dvd || (l_dvd > abs_s)) { + x86emu_intr_raise(0); + return; + } + /* sign */ + div |= ((h_dvd & 0x10000000) ^ (s & 0x10000000)); + mod = l_dvd; + +#endif + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_ZF); + CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); + + M.x86.R_EAX = (u32)div; + M.x86.R_EDX = (u32)mod; +} + +/**************************************************************************** +REMARKS: +Implements the DIV instruction and side effects. +****************************************************************************/ +void div_byte(u8 s) +{ + u32 dvd, div, mod; + + dvd = M.x86.R_AX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (u8)s; + mod = dvd % (u8)s; + if (div > 0xff) { + x86emu_intr_raise(0); + return; + } + M.x86.R_AL = (u8)div; + M.x86.R_AH = (u8)mod; +} + +/**************************************************************************** +REMARKS: +Implements the DIV instruction and side effects. +****************************************************************************/ +void div_word(u16 s) +{ + u32 dvd, div, mod; + + dvd = (((u32)M.x86.R_DX) << 16) | M.x86.R_AX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (u16)s; + mod = dvd % (u16)s; + if (div > 0xffff) { + x86emu_intr_raise(0); + return; + } + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(div == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); + + M.x86.R_AX = (u16)div; + M.x86.R_DX = (u16)mod; +} + +/**************************************************************************** +REMARKS: +Implements the DIV instruction and side effects. +****************************************************************************/ +void div_long(u32 s) +{ +#ifdef __HAS_LONG_LONG__ + u64 dvd, div, mod; + + dvd = (((u64)M.x86.R_EDX) << 32) | M.x86.R_EAX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (u32)s; + mod = dvd % (u32)s; + if (div > 0xffffffffULL) { + x86emu_intr_raise(0); + return; + } +#else + s32 div = 0, mod; + s32 h_dvd = M.x86.R_EDX; + u32 l_dvd = M.x86.R_EAX; + + u32 h_s = s; + u32 l_s = 0; + int counter = 32; + int carry; + + if (s == 0) { + x86emu_intr_raise(0); + return; + } + do { + div <<= 1; + carry = (l_dvd >= l_s) ? 0 : 1; + + if (h_dvd < (h_s + carry)) { + h_s >>= 1; + l_s = s << (--counter); + continue; + } else { + h_dvd -= (h_s + carry); + l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) + : (l_dvd - l_s); + h_s >>= 1; + l_s = s << (--counter); + div |= 1; + continue; + } + + } while (counter > -1); + /* overflow */ + if (h_dvd || (l_dvd > s)) { + x86emu_intr_raise(0); + return; + } + mod = l_dvd; +#endif + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_ZF); + CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); + + M.x86.R_EAX = (u32)div; + M.x86.R_EDX = (u32)mod; +} + +/**************************************************************************** +REMARKS: +Implements the IN string instruction and side effects. +****************************************************************************/ +void ins(int size) +{ + int inc = size; + + if (ACCESS_FLAG(F_DF)) { + inc = -size; + } + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* in until CX is ZERO. */ + u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ? + M.x86.R_ECX : M.x86.R_CX); + switch (size) { + case 1: + while (count--) { + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inb)(M.x86.R_DX)); + M.x86.R_DI += inc; + } + break; + + case 2: + while (count--) { + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inw)(M.x86.R_DX)); + M.x86.R_DI += inc; + } + break; + case 4: + while (count--) { + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inl)(M.x86.R_DX)); + M.x86.R_DI += inc; + break; + } + } + M.x86.R_CX = 0; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = 0; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + switch (size) { + case 1: + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inb)(M.x86.R_DX)); + break; + case 2: + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inw)(M.x86.R_DX)); + break; + case 4: + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inl)(M.x86.R_DX)); + break; + } + M.x86.R_DI += inc; + } +} + +/**************************************************************************** +REMARKS: +Implements the OUT string instruction and side effects. +****************************************************************************/ +void outs(int size) +{ + int inc = size; + + if (ACCESS_FLAG(F_DF)) { + inc = -size; + } + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* out until CX is ZERO. */ + u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ? + M.x86.R_ECX : M.x86.R_CX); + switch (size) { + case 1: + while (count--) { + (*sys_outb)(M.x86.R_DX, + fetch_data_byte_abs(M.x86.R_ES, M.x86.R_SI)); + M.x86.R_SI += inc; + } + break; + + case 2: + while (count--) { + (*sys_outw)(M.x86.R_DX, + fetch_data_word_abs(M.x86.R_ES, M.x86.R_SI)); + M.x86.R_SI += inc; + } + break; + case 4: + while (count--) { + (*sys_outl)(M.x86.R_DX, + fetch_data_long_abs(M.x86.R_ES, M.x86.R_SI)); + M.x86.R_SI += inc; + break; + } + } + M.x86.R_CX = 0; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = 0; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + switch (size) { + case 1: + (*sys_outb)(M.x86.R_DX, + fetch_data_byte_abs(M.x86.R_ES, M.x86.R_SI)); + break; + case 2: + (*sys_outw)(M.x86.R_DX, + fetch_data_word_abs(M.x86.R_ES, M.x86.R_SI)); + break; + case 4: + (*sys_outl)(M.x86.R_DX, + fetch_data_long_abs(M.x86.R_ES, M.x86.R_SI)); + break; + } + M.x86.R_SI += inc; + } +} + +/**************************************************************************** +PARAMETERS: +addr - Address to fetch word from + +REMARKS: +Fetches a word from emulator memory using an absolute address. +****************************************************************************/ +u16 mem_access_word(int addr) +{ +DB( if (CHECK_MEM_ACCESS()) + x86emu_check_mem_access(addr);) + return (*sys_rdw)(addr); +} + +/**************************************************************************** +REMARKS: +Pushes a word onto the stack. + +NOTE: Do not inline this, as (*sys_wrX) is already inline! +****************************************************************************/ +void push_word(u16 w) +{ +DB( if (CHECK_SP_ACCESS()) + x86emu_check_sp_access();) + M.x86.R_SP -= 2; + (*sys_wrw)(((u32)M.x86.R_SS << 4) + M.x86.R_SP, w); +} + +/**************************************************************************** +REMARKS: +Pushes a long onto the stack. + +NOTE: Do not inline this, as (*sys_wrX) is already inline! +****************************************************************************/ +void push_long(u32 w) +{ +DB( if (CHECK_SP_ACCESS()) + x86emu_check_sp_access();) + M.x86.R_SP -= 4; + (*sys_wrl)(((u32)M.x86.R_SS << 4) + M.x86.R_SP, w); +} + +/**************************************************************************** +REMARKS: +Pops a word from the stack. + +NOTE: Do not inline this, as (*sys_rdX) is already inline! +****************************************************************************/ +u16 pop_word(void) +{ + register u16 res; + +DB( if (CHECK_SP_ACCESS()) + x86emu_check_sp_access();) + res = (*sys_rdw)(((u32)M.x86.R_SS << 4) + M.x86.R_SP); + M.x86.R_SP += 2; + return res; +} + +/**************************************************************************** +REMARKS: +Pops a long from the stack. + +NOTE: Do not inline this, as (*sys_rdX) is already inline! +****************************************************************************/ +u32 pop_long(void) +{ + register u32 res; + +DB( if (CHECK_SP_ACCESS()) + x86emu_check_sp_access();) + res = (*sys_rdl)(((u32)M.x86.R_SS << 4) + M.x86.R_SP); + M.x86.R_SP += 4; + return res; +} + diff --git a/userspace/sdks/nv570/nvalloc/unix/x86emu/sys.c b/userspace/sdks/nv570/nvalloc/unix/x86emu/sys.c new file mode 100644 index 0000000..9a5527f --- /dev/null +++ b/userspace/sdks/nv570/nvalloc/unix/x86emu/sys.c @@ -0,0 +1,663 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes subroutines which are related to +* programmed I/O and memory access. Included in this module +* are default functions with limited usefulness. For real +* uses these functions will most likely be overriden by the +* user library. +* +****************************************************************************/ + +#include "x86emu/x86emu.h" +#include "x86emu/x86emui.h" +#include "x86emu/regs.h" +#include "x86emu/debug.h" +#include "x86emu/prim_ops.h" +#ifndef NO_SYS_HEADERS +#include +#endif +/*------------------------- Global Variables ------------------------------*/ + +X86EMU_sysEnv _X86EMU_env; /* Global emulator machine state */ +X86EMU_intrFuncs _X86EMU_intrTab[256]; + +/*----------------------------- Implementation ----------------------------*/ +#if defined(__alpha__) || defined(__alpha) +/* to cope with broken egcs-1.1.2 :-(((( */ + +#define ALPHA_UALOADS +/* + * inline functions to do unaligned accesses + * from linux/include/asm-alpha/unaligned.h + */ + +/* + * EGCS 1.1 knows about arbitrary unaligned loads. Define some + * packed structures to talk about such things with. + */ + +#if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) +struct __una_u64 { unsigned long x __attribute__((packed)); }; +struct __una_u32 { unsigned int x __attribute__((packed)); }; +struct __una_u16 { unsigned short x __attribute__((packed)); }; +#endif + +static __inline__ unsigned long ldq_u(unsigned long * r11) +{ +#if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + const struct __una_u64 *ptr = (const struct __una_u64 *) r11; + return ptr->x; +#else + unsigned long r1,r2; + __asm__("ldq_u %0,%3\n\t" + "ldq_u %1,%4\n\t" + "extql %0,%2,%0\n\t" + "extqh %1,%2,%1" + :"=&r" (r1), "=&r" (r2) + :"r" (r11), + "m" (*r11), + "m" (*(const unsigned long *)(7+(char *) r11))); + return r1 | r2; +#endif +} + +static __inline__ unsigned long ldl_u(unsigned int * r11) +{ +#if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + const struct __una_u32 *ptr = (const struct __una_u32 *) r11; + return ptr->x; +#else + unsigned long r1,r2; + __asm__("ldq_u %0,%3\n\t" + "ldq_u %1,%4\n\t" + "extll %0,%2,%0\n\t" + "extlh %1,%2,%1" + :"=&r" (r1), "=&r" (r2) + :"r" (r11), + "m" (*r11), + "m" (*(const unsigned long *)(3+(char *) r11))); + return r1 | r2; +#endif +} + +static __inline__ unsigned long ldw_u(unsigned short * r11) +{ +#if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + const struct __una_u16 *ptr = (const struct __una_u16 *) r11; + return ptr->x; +#else + unsigned long r1,r2; + __asm__("ldq_u %0,%3\n\t" + "ldq_u %1,%4\n\t" + "extwl %0,%2,%0\n\t" + "extwh %1,%2,%1" + :"=&r" (r1), "=&r" (r2) + :"r" (r11), + "m" (*r11), + "m" (*(const unsigned long *)(1+(char *) r11))); + return r1 | r2; +#endif +} + +/* + * Elemental unaligned stores + */ + +static __inline__ void stq_u(unsigned long r5, unsigned long * r11) +{ +#if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + struct __una_u64 *ptr = (struct __una_u64 *) r11; + ptr->x = r5; +#else + unsigned long r1,r2,r3,r4; + + __asm__("ldq_u %3,%1\n\t" + "ldq_u %2,%0\n\t" + "insqh %6,%7,%5\n\t" + "insql %6,%7,%4\n\t" + "mskqh %3,%7,%3\n\t" + "mskql %2,%7,%2\n\t" + "bis %3,%5,%3\n\t" + "bis %2,%4,%2\n\t" + "stq_u %3,%1\n\t" + "stq_u %2,%0" + :"=m" (*r11), + "=m" (*(unsigned long *)(7+(char *) r11)), + "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) + :"r" (r5), "r" (r11)); +#endif +} + +static __inline__ void stl_u(unsigned long r5, unsigned int * r11) +{ +#if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + struct __una_u32 *ptr = (struct __una_u32 *) r11; + ptr->x = r5; +#else + unsigned long r1,r2,r3,r4; + + __asm__("ldq_u %3,%1\n\t" + "ldq_u %2,%0\n\t" + "inslh %6,%7,%5\n\t" + "insll %6,%7,%4\n\t" + "msklh %3,%7,%3\n\t" + "mskll %2,%7,%2\n\t" + "bis %3,%5,%3\n\t" + "bis %2,%4,%2\n\t" + "stq_u %3,%1\n\t" + "stq_u %2,%0" + :"=m" (*r11), + "=m" (*(unsigned long *)(3+(char *) r11)), + "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) + :"r" (r5), "r" (r11)); +#endif +} + +static __inline__ void stw_u(unsigned long r5, unsigned short * r11) +{ +#if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + struct __una_u16 *ptr = (struct __una_u16 *) r11; + ptr->x = r5; +#else + unsigned long r1,r2,r3,r4; + + __asm__("ldq_u %3,%1\n\t" + "ldq_u %2,%0\n\t" + "inswh %6,%7,%5\n\t" + "inswl %6,%7,%4\n\t" + "mskwh %3,%7,%3\n\t" + "mskwl %2,%7,%2\n\t" + "bis %3,%5,%3\n\t" + "bis %2,%4,%2\n\t" + "stq_u %3,%1\n\t" + "stq_u %2,%0" + :"=m" (*r11), + "=m" (*(unsigned long *)(1+(char *) r11)), + "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) + :"r" (r5), "r" (r11)); +#endif +} + +#elif defined(__GNUC__) && ((__GNUC__ < 3)) && \ + (defined (__ia64__) || defined (ia64__)) +#define IA64_UALOADS +/* + * EGCS 1.1 knows about arbitrary unaligned loads. Define some + * packed structures to talk about such things with. + */ +struct __una_u64 { unsigned long x __attribute__((packed)); }; +struct __una_u32 { unsigned int x __attribute__((packed)); }; +struct __una_u16 { unsigned short x __attribute__((packed)); }; + +static __inline__ unsigned long +__uldq (const unsigned long * r11) +{ + const struct __una_u64 *ptr = (const struct __una_u64 *) r11; + return ptr->x; +} + +static __inline__ unsigned long +uldl (const unsigned int * r11) +{ + const struct __una_u32 *ptr = (const struct __una_u32 *) r11; + return ptr->x; +} + +static __inline__ unsigned long +uldw (const unsigned short * r11) +{ + const struct __una_u16 *ptr = (const struct __una_u16 *) r11; + return ptr->x; +} + +static __inline__ void +ustq (unsigned long r5, unsigned long * r11) +{ + struct __una_u64 *ptr = (struct __una_u64 *) r11; + ptr->x = r5; +} + +static __inline__ void +ustl (unsigned long r5, unsigned int * r11) +{ + struct __una_u32 *ptr = (struct __una_u32 *) r11; + ptr->x = r5; +} + +static __inline__ void +ustw (unsigned long r5, unsigned short * r11) +{ + struct __una_u16 *ptr = (struct __una_u16 *) r11; + ptr->x = r5; +} + +#endif + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Byte value read from emulator memory. + +REMARKS: +Reads a byte value from the emulator memory. +****************************************************************************/ +u8 X86API rdb( + u32 addr) +{ + u8 val; + + if (addr > M.mem_size - 1) { + DB(NV_PRINTF(LEVEL_INFO, "mem_read: address %#x out of range!\n", addr);) + HALT_SYS(); + } + val = *(u8*)(M.mem_base + addr); +DB( if (DEBUG_MEM_TRACE()) + NV_PRINTF(LEVEL_INFO, "%#08x 1 -> %#x\n", addr, val);) + return val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Word value read from emulator memory. + +REMARKS: +Reads a word value from the emulator memory. +****************************************************************************/ +u16 X86API rdw( + u32 addr) +{ + u16 val = 0; + + if (addr > M.mem_size - 2) { + DB(NV_PRINTF(LEVEL_INFO, "mem_read: address %#x out of range!\n", addr);) + HALT_SYS(); + } +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + val = (*(u8*)(M.mem_base + addr) | + (*(u8*)(M.mem_base + addr + 1) << 8)); + } + else +#endif +#if defined(ALPHA_UALOADS) + val = ldw_u((u16*)(M.mem_base + addr)); +#elif defined(IA64_UALOADS) + val = uldw((u16*)(M.mem_base + addr)); +#else + val = *(u16*)(M.mem_base + addr); +#endif +DB( if (DEBUG_MEM_TRACE()) + NV_PRINTF(LEVEL_INFO, "%#08x 2 -> %#x\n", addr, val);) + return val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Long value read from emulator memory. +REMARKS: +Reads a long value from the emulator memory. +****************************************************************************/ +u32 X86API rdl( + u32 addr) +{ + u32 val = 0; + + if (addr > M.mem_size - 4) { + DB(NV_PRINTF(LEVEL_INFO, "mem_read: address %#x out of range!\n", addr);) + HALT_SYS(); + } +#ifdef __BIG_ENDIAN__ + if (addr & 0x3) { + val = (*(u8*)(M.mem_base + addr + 0) | + (*(u8*)(M.mem_base + addr + 1) << 8) | + (*(u8*)(M.mem_base + addr + 2) << 16) | + (*(u8*)(M.mem_base + addr + 3) << 24)); + } + else +#endif +#if defined(ALPHA_UALOADS) + val = ldl_u((u32*)(M.mem_base + addr)); +#elif defined(IA64_UALOADS) + val = uldl((u32*)(M.mem_base + addr)); +#else + val = *(u32*)(M.mem_base + addr); +#endif +DB( if (DEBUG_MEM_TRACE()) + NV_PRINTF(LEVEL_INFO, "%#08x 4 -> %#x\n", addr, val);) + return val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a byte value to emulator memory. +****************************************************************************/ +void X86API wrb( + u32 addr, + u8 val) +{ +DB( if (DEBUG_MEM_TRACE()) + NV_PRINTF(LEVEL_INFO, "%#08x 1 <- %#x\n", addr, val);) + if (addr > M.mem_size - 1) { + DB(NV_PRINTF(LEVEL_INFO, "mem_write: address %#x out of range!\n", addr);) + HALT_SYS(); + } + *(u8*)(M.mem_base + addr) = val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a word value to emulator memory. +****************************************************************************/ +void X86API wrw( + u32 addr, + u16 val) +{ +DB( if (DEBUG_MEM_TRACE()) + NV_PRINTF(LEVEL_INFO, "%#08x 2 <- %#x\n", addr, val);) + if (addr > M.mem_size - 2) { + DB(NV_PRINTF(LEVEL_INFO, "mem_write: address %#x out of range!\n", addr);) + HALT_SYS(); + } +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; + *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; + } + else +#endif +#if defined(ALPHA_UALOADS) + stw_u(val,(u16*)(M.mem_base + addr)); +#elif defined(IA64_UALOADS) + ustw(val,(u16*)(M.mem_base + addr)); +#else + *(u16*)(M.mem_base + addr) = val; +#endif +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a long value to emulator memory. +****************************************************************************/ +void X86API wrl( + u32 addr, + u32 val) +{ +DB( if (DEBUG_MEM_TRACE()) + NV_PRINTF(LEVEL_INFO, "%#08x 4 <- %#x\n", addr, val);) + if (addr > M.mem_size - 4) { + DB(NV_PRINTF(LEVEL_INFO, "mem_write: address %#x out of range!\n", addr);) + HALT_SYS(); + } +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; + *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; + *(u8*)(M.mem_base + addr + 2) = (val >> 16) & 0xff; + *(u8*)(M.mem_base + addr + 3) = (val >> 24) & 0xff; + } + else +#endif +#if defined(ALPHA_UALOADS) + stl_u(val,(u32*)(M.mem_base + addr)); +#elif defined(IA64_UALOADS) + ustl(val,(u32*)(M.mem_base + addr)); +#else + *(u32*)(M.mem_base + addr) = val; +#endif +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to read +RETURN: +0 +REMARKS: +Default PIO byte read function. Doesn't perform real inb. +****************************************************************************/ +static u8 X86API p_inb( + X86EMU_pioAddr addr) +{ +DB( if (DEBUG_IO_TRACE()) + NV_PRINTF(LEVEL_INFO, "inb %#04x \n", addr);) + return 0; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to read +RETURN: +0 +REMARKS: +Default PIO word read function. Doesn't perform real inw. +****************************************************************************/ +static u16 X86API p_inw( + X86EMU_pioAddr addr) +{ +DB( if (DEBUG_IO_TRACE()) + NV_PRINTF(LEVEL_INFO, "inw %#04x \n", addr);) + return 0; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to read +RETURN: +0 +REMARKS: +Default PIO long read function. Doesn't perform real inl. +****************************************************************************/ +static u32 X86API p_inl( + X86EMU_pioAddr addr) +{ +DB( if (DEBUG_IO_TRACE()) + NV_PRINTF(LEVEL_INFO, "inl %#04x \n", addr);) + return 0; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to write +val - Value to store +REMARKS: +Default PIO byte write function. Doesn't perform real outb. +****************************************************************************/ +static void X86API p_outb( + X86EMU_pioAddr addr, + u8 val) +{ +DB( if (DEBUG_IO_TRACE()) + NV_PRINTF(LEVEL_INFO, "outb %#02x -> %#04x \n", val, addr);) + return; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to write +val - Value to store +REMARKS: +Default PIO word write function. Doesn't perform real outw. +****************************************************************************/ +static void X86API p_outw( + X86EMU_pioAddr addr, + u16 val) +{ +DB( if (DEBUG_IO_TRACE()) + NV_PRINTF(LEVEL_INFO, "outw %#04x -> %#04x \n", val, addr);) + return; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to write +val - Value to store +REMARKS: +Default PIO ;ong write function. Doesn't perform real outl. +****************************************************************************/ +static void X86API p_outl( + X86EMU_pioAddr addr, + u32 val) +{ +DB( if (DEBUG_IO_TRACE()) + NV_PRINTF(LEVEL_INFO, "outl %#08x -> %#04x \n", val, addr);) + return; +} + +/*------------------------- Global Variables ------------------------------*/ + +u8 (X86APIP sys_rdb)(u32 addr) = rdb; +u16 (X86APIP sys_rdw)(u32 addr) = rdw; +u32 (X86APIP sys_rdl)(u32 addr) = rdl; +void (X86APIP sys_wrb)(u32 addr,u8 val) = wrb; +void (X86APIP sys_wrw)(u32 addr,u16 val) = wrw; +void (X86APIP sys_wrl)(u32 addr,u32 val) = wrl; +u8 (X86APIP sys_inb)(X86EMU_pioAddr addr) = p_inb; +u16 (X86APIP sys_inw)(X86EMU_pioAddr addr) = p_inw; +u32 (X86APIP sys_inl)(X86EMU_pioAddr addr) = p_inl; +void (X86APIP sys_outb)(X86EMU_pioAddr addr, u8 val) = p_outb; +void (X86APIP sys_outw)(X86EMU_pioAddr addr, u16 val) = p_outw; +void (X86APIP sys_outl)(X86EMU_pioAddr addr, u32 val) = p_outl; + +/*----------------------------- Setup -------------------------------------*/ + +/**************************************************************************** +PARAMETERS: +funcs - New memory function pointers to make active + +REMARKS: +This function is used to set the pointers to functions which access +memory space, allowing the user application to override these functions +and hook them out as necessary for their application. +****************************************************************************/ +void X86EMU_setupMemFuncs( + X86EMU_memFuncs *funcs) +{ + sys_rdb = funcs->rdb; + sys_rdw = funcs->rdw; + sys_rdl = funcs->rdl; + sys_wrb = funcs->wrb; + sys_wrw = funcs->wrw; + sys_wrl = funcs->wrl; +} + +/**************************************************************************** +PARAMETERS: +funcs - New programmed I/O function pointers to make active + +REMARKS: +This function is used to set the pointers to functions which access +I/O space, allowing the user application to override these functions +and hook them out as necessary for their application. +****************************************************************************/ +void X86EMU_setupPioFuncs( + X86EMU_pioFuncs *funcs) +{ + sys_inb = funcs->inb; + sys_inw = funcs->inw; + sys_inl = funcs->inl; + sys_outb = funcs->outb; + sys_outw = funcs->outw; + sys_outl = funcs->outl; +} + +/**************************************************************************** +PARAMETERS: +funcs - New interrupt vector table to make active + +REMARKS: +This function is used to set the pointers to functions which handle +interrupt processing in the emulator, allowing the user application to +hook interrupts as necessary for their application. Any interrupts that +are not hooked by the user application, and reflected and handled internally +in the emulator via the interrupt vector table. This allows the application +to get control when the code being emulated executes specific software +interrupts. +****************************************************************************/ +void X86EMU_setupIntrFuncs( + X86EMU_intrFuncs funcs[]) +{ + int i; + + for (i=0; i < 256; i++) + _X86EMU_intrTab[i] = NULL; + if (funcs) { + for (i = 0; i < 256; i++) + _X86EMU_intrTab[i] = funcs[i]; + } +} + +/**************************************************************************** +PARAMETERS: +int - New software interrupt to prepare for + +REMARKS: +This function is used to set up the emulator state to exceute a software +interrupt. This can be used by the user application code to allow an +interrupt to be hooked, examined and then reflected back to the emulator +so that the code in the emulator will continue processing the software +interrupt as per normal. This essentially allows system code to actively +hook and handle certain software interrupts as necessary. +****************************************************************************/ +void X86EMU_prepareForInt( + int num) +{ + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(num * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(num * 4); + M.x86.intr = 0; +} diff --git a/userspace/sdks/nv570/nvidia/inc/Nvcm.h b/userspace/sdks/nv570/nvidia/inc/Nvcm.h new file mode 100644 index 0000000..71dc880 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/Nvcm.h @@ -0,0 +1,71 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/******************* Operating System Interface Routines *******************\ +* * +* Module: NVCM.H * +* Windows Configuration Manager defines and prototypes. * +* * +* ***IMPORTANT*** The interfaces defined in this file are *deprecated* * +* ***IMPORTANT*** in favor of RmControl. * +* ***IMPORTANT*** Try hard to not use this file at all and definitely * +* ***IMPORTANT*** do not add or modify interfaces here. * +* Ref: bug 488474: delete CFG and CFG_EX * +* * +\***************************************************************************/ + +#ifndef _NVCM_H_ +#define _NVCM_H_ + +#include "nvdeprecated.h" + +#if NV_DEPRECATED_COMPAT(RM_CONFIG_GET_SET) + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvgputypes.h" +#ifndef _H2INC +#include "rmcd.h" +#endif + +#include "nverror.h" + +#define NV_ROBUST_CHANNEL_ALLOCFAIL_CLIENT 0x00000001 +#define NV_ROBUST_CHANNEL_ALLOCFAIL_DEVICE 0x00000002 +#define NV_ROBUST_CHANNEL_ALLOCFAIL_SUBDEVICE 0x00000004 +#define NV_ROBUST_CHANNEL_ALLOCFAIL_CHANNEL 0x00000008 +#define NV_ROBUST_CHANNEL_ALLOCFAIL_CTXDMA 0x00000010 +#define NV_ROBUST_CHANNEL_ALLOCFAIL_EVENT 0x00000020 +#define NV_ROBUST_CHANNEL_ALLOCFAIL_MEMORY 0x00000040 +#define NV_ROBUST_CHANNEL_ALLOCFAIL_OBJECT 0x00000080 +#define NV_ROBUST_CHANNEL_ALLOCFAIL_HEAP 0x00000100 + +#define NV_ROBUST_CHANNEL_BREAKONERROR_DEFAULT 0x00000000 +#define NV_ROBUST_CHANNEL_BREAKONERROR_DISABLE 0x00000001 +#define NV_ROBUST_CHANNEL_BREAKONERROR_ENABLE 0x00000002 + +#endif // NV_DEPRECATED_RM_CONFIG_GET_SET + +#endif // _NVCM_H_ diff --git a/userspace/sdks/nv570/nvidia/inc/alloc/alloc_channel.h b/userspace/sdks/nv570/nvidia/inc/alloc/alloc_channel.h new file mode 100644 index 0000000..4e96204 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/alloc/alloc_channel.h @@ -0,0 +1,319 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: alloc/alloc_channel.finn +// + +#include "nvlimits.h" +#include "nvcfg_sdk.h" + +typedef struct NV_MEMORY_DESC_PARAMS { + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 addressSpace; + NvU32 cacheAttrib; +} NV_MEMORY_DESC_PARAMS; + + +/* + * NV_CHANNEL_ALLOC_PARAMS.flags values. + * + * These flags may apply to all channel types: PIO, DMA, and GPFIFO. + * They are also designed so that zero is always the correct default. + * + * NVOS04_FLAGS_CHANNEL_TYPE: + * This flag specifies the type of channel to allocate. Legal values + * for this flag include: + * + * NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL: + * This flag specifies that a physical channel is to be allocated. + * + * NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL: + * OBSOLETE - NOT SUPPORTED + * + * NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL: + * OBSOLETE - NOT SUPPORTED + */ + +/* valid NVOS04_FLAGS_CHANNEL_TYPE values */ +#define NVOS04_FLAGS_CHANNEL_TYPE 1:0 +#define NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL 0x00000000 +#define NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL 0x00000001 // OBSOLETE +#define NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL 0x00000002 // OBSOLETE + +/* + * NVOS04_FLAGS_VPR: + * This flag specifies if channel is intended for work with + * Video Protected Regions (VPR) + * + * NVOS04_FLAGS_VPR_TRUE: + * The channel will only write to protected memory regions. + * + * NVOS04_FLAGS_VPR_FALSE: + * The channel will never read from protected memory regions. + */ +#define NVOS04_FLAGS_VPR 2:2 +#define NVOS04_FLAGS_VPR_FALSE 0x00000000 +#define NVOS04_FLAGS_VPR_TRUE 0x00000001 + + + +/* + * NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING: + * This flag specifies if the channel can skip refcounting of potentially + * accessed mappings on job kickoff. This flag is only meaningful for + * kernel drivers which perform refcounting of memory mappings. + * + * NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE: + * The channel cannot not skip refcounting of memory mappings + * + * NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE: + * The channel can skip refcounting of memory mappings + */ +#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING 3:3 +#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE: + * This flag specifies which "runqueue" the allocated channel will be + * executed on in a TSG. Channels on different runqueues within a TSG + * may be able to feed methods into the engine simultaneously. + * Non-default values are only supported on GP10x and later and only for + * channels within a TSG. + */ +#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE 4:4 +#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_DEFAULT 0x00000000 +#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_ONE 0x00000001 + +/* + * NVOS04_FLAGS_PRIVILEGED_CHANNEL: + * This flag tells RM whether to give the channel admin privilege. This + * flag will only take effect if the client is GSP-vGPU plugin. It is + * needed so that guest can update page tables in physical mode and do + * scrubbing. + */ +#define NVOS04_FLAGS_PRIVILEGED_CHANNEL 5:5 +#define NVOS04_FLAGS_PRIVILEGED_CHANNEL_FALSE 0x00000000 +#define NVOS04_FLAGS_PRIVILEGED_CHANNEL_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING: + * This flags tells RM not to schedule a newly created channel within a + * channel group immediately even if channel group is currently scheduled. + * Channel will not be scheduled until NVA06F_CTRL_GPFIFO_SCHEDULE is + * invoked. This is used eg. for CUDA which needs to do additional + * initialization before starting up a channel. + * Default is FALSE. + */ +#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING 6:6 +#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_FALSE 0x00000000 +#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_DENY_PHYSICAL_MODE_CE: + * This flag specifies whether or not to deny access to the physical + * mode of CopyEngine regardless of whether or not the client handle + * is admin. If set to true, this channel allocation will always result + * in an unprivileged channel. If set to false, the privilege of the channel + * will depend on the privilege level of the client handle. + * This is primarily meant for vGPU since all client handles + * granted to guests are admin. + */ +#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE 7:7 +#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_CHANNEL_USERD_INDEX_VALUE + * + * This flag specifies the channel offset in terms of within a page of + * USERD. For example, value 3 means the 4th channel within a USERD page. + * Given the USERD size is 512B, we will have 8 channels total, so 3 bits + * are reserved. + * + * When _USERD_INDEX_FIXED_TRUE is set but INDEX_PAGE_FIXED_FALSE is set, + * it will ask for a new USERD page. + * + */ +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_VALUE 10:8 + +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED 11:11 +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_VALUE + * + * This flag specifies the channel offset in terms of USERD page. When + * this PAGE_FIXED_TRUE is set, the INDEX_FIXED_FALSE bit should also + * be set, otherwise INVALID_STATE will be returned. + * + * And the field _USERD_INDEX_VALUE will be used to request the specific + * offset within a USERD page. + */ + +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_VALUE 20:12 + +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED 21:21 +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_DENY_AUTH_LEVEL_PRIV + * This flag specifies whether or not to deny access to the privileged + * host methods TLB_INVALIDATE and ACCESS_COUNTER_CLR + */ +#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV 22:22 +#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER + * + * This flag specifies scrubbing should be skipped for any internal + * allocations made for this channel from PMA using ctx buf pools. + * Only kernel clients are allowed to use this setting. + */ +#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER 23:23 +#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO + * + * This flag specifies that the client is expected to map USERD themselves + * and RM need not do so. + */ +#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO 24:24 +#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL + */ +#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL 25:25 +#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_FALSE 0x00000000 +#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT + * + * This flag specifies whether the channel calling context is from CPU + * VGPU plugin. + */ +#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT 26:26 +#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_TRUE 0x00000001 + + /* + * NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT + * + * This flag specifies the channel PBDMA ACQUIRE timeout option. + * _FALSE to disable it, _TRUE to enable it. + * When this flag is enabled, if a host semaphore acquire does not + * complete in about 2 sec, it will time out and trigger a RC error. + */ +#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT 27:27 +#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_GROUP_CHANNEL_THREAD: + * This flags specifies the thread id in which an allocated channel + * will be executed in a TSG. The relationship between the thread id + * in A TSG and respective definitions are implementation specific. + * Also, not all classes will be supported at thread > 0. + * This field cannot be used on non-TSG channels and must be set to + * the default value (0) in that case. If thread > 0 on a non-TSG + * channel, the allocation will fail + */ +#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD 29:28 +#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_DEFAULT 0x00000000 +#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_ONE 0x00000001 +#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_TWO 0x00000002 + +#define NVOS04_FLAGS_MAP_CHANNEL 30:30 +#define NVOS04_FLAGS_MAP_CHANNEL_FALSE 0x00000000 +#define NVOS04_FLAGS_MAP_CHANNEL_TRUE 0x00000001 + +#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC 31:31 +#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_FALSE 0x00000000 +#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_TRUE 0x00000001 + + + + +#define NV_CHANNEL_ALLOC_PARAMS_MESSAGE_ID (0x906fU) + +typedef struct NV_CHANNEL_ALLOC_PARAMS { + + NvHandle hObjectError; // error context DMA + NvHandle hObjectBuffer; // no longer used + NV_DECLARE_ALIGNED(NvU64 gpFifoOffset, 8); // offset to beginning of GP FIFO + NvU32 gpFifoEntries; // number of GP FIFO entries + + NvU32 flags; + + + NvHandle hContextShare; // context share handle + NvHandle hVASpace; // VASpace for the channel + + // handle to UserD memory object for channel, ignored if hUserdMemory[0]=0 + NvHandle hUserdMemory[NV_MAX_SUBDEVICES]; + + // offset to beginning of UserD within hUserdMemory[x] + NV_DECLARE_ALIGNED(NvU64 userdOffset[NV_MAX_SUBDEVICES], 8); + + // engine type(NV2080_ENGINE_TYPE_*) with which this channel is associated + NvU32 engineType; + // Channel identifier that is unique for the duration of a RM session + NvU32 cid; + // One-hot encoded bitmask to match SET_SUBDEVICE_MASK methods + NvU32 subDeviceId; + NvHandle hObjectEccError; // ECC error context DMA + + + + NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS instanceMem, 8); + NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS userdMem, 8); + NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS ramfcMem, 8); + NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS mthdbufMem, 8); + + NvHandle hPhysChannelGroup; // reserved + NvU32 internalFlags; // reserved + NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS errorNotifierMem, 8); // reserved + NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS eccErrorNotifierMem, 8); // reserved + NvU32 ProcessID; // reserved + NvU32 SubProcessID; // reserved +} NV_CHANNEL_ALLOC_PARAMS; + +typedef NV_CHANNEL_ALLOC_PARAMS NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl0000.h b/userspace/sdks/nv570/nvidia/inc/class/cl0000.h new file mode 100644 index 0000000..e7fefba --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl0000.h @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0000.finn +// + +#include "nvlimits.h" +#include "cl0000_notification.h" + +/* object NV01_NULL_OBJECT */ +#define NV01_NULL_OBJECT (0x0) /* finn: Evaluated from "NV0000_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* obsolete alises */ +#define NV1_NULL_OBJECT NV01_NULL_OBJECT + +#define NV01_ROOT (0x0U) /* finn: Evaluated from "NV0000_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* NvAlloc parameteters */ +#define NV0000_ALLOC_PARAMETERS_MESSAGE_ID (0x0000U) + +typedef struct NV0000_ALLOC_PARAMETERS { + NvHandle hClient; /* CORERM-2934: hClient must remain the first member until all allocations use these params */ + NvU32 processID; + char processName[NV_PROC_NAME_MAX_LENGTH]; +} NV0000_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl0000_notification.h b/userspace/sdks/nv570/nvidia/inc/class/cl0000_notification.h new file mode 100644 index 0000000..79b51d9 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl0000_notification.h @@ -0,0 +1,68 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0000_notification_h_ +#define _cl0000_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/*event values*/ +#define NV0000_NOTIFIERS_DISPLAY_CHANGE (0) +#define NV0000_NOTIFIERS_EVENT_NONE_PENDING (1) +#define NV0000_NOTIFIERS_VM_START (2) +#define NV0000_NOTIFIERS_GPU_BIND_EVENT (3) +#define NV0000_NOTIFIERS_NVTELEMETRY_REPORT_EVENT (4) +#define NV0000_NOTIFIERS_MAXCOUNT (5) + +/*Status definitions for NV0000_NOTIFIERS_DISPLAY_CHANGE event*/ + +#define NV0000_NOTIFIERS_STATUS_ACPI_DISPLAY_DEVICE_CYCLE (0) + +//--------------------------------------------------------------------------- + +/* NvNotification[] fields and values */ +#define NV000_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + + +/* pio method data structure */ +typedef volatile struct _cl0000_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv000Typedef, Nv01Root; + +/* obsolete aliases */ +#define NV000_TYPEDEF Nv01Root +#define Nv1Root Nv01Root +#define nv1Root Nv01Root +#define nv01Root Nv01Root + +/*event values*/ +#define NV0000_NOTIFIERS_ENABLE_CPU_UTIL_CTRL (1) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0000_notification_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl0001.h b/userspace/sdks/nv570/nvidia/inc/class/cl0001.h new file mode 100644 index 0000000..10a8af4 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl0001.h @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2013 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0001_h_ +#define _cl0001_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV01_ROOT_NON_PRIV (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0001_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl0002.h b/userspace/sdks/nv570/nvidia/inc/class/cl0002.h new file mode 100644 index 0000000..dd1d6c6 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl0002.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2001-2001, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0002_h_ +#define _cl0002_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV01_CONTEXT_DMA_FROM_MEMORY (0x00000002) +/* NvNotification[] fields and values */ +#define NV002_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +typedef volatile struct _cl0002_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv002Typedef, Nv01ContextDmaFromMemory; +#define NV002_TYPEDEF Nv01ContextDmaFromMemory +/* obsolete stuff */ +#define NV1_CONTEXT_DMA_FROM_MEMORY (0x00000002) +#define NV01_CONTEXT_DMA (0x00000002) +#define Nv1ContextDmaFromMemory Nv01ContextDmaFromMemory +#define nv1ContextDmaFromMemory Nv01ContextDmaFromMemory +#define nv01ContextDmaFromMemory Nv01ContextDmaFromMemory + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0002_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl0004.h b/userspace/sdks/nv570/nvidia/inc/class/cl0004.h new file mode 100644 index 0000000..32e25e7 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl0004.h @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0004_h_ +#define _cl0004_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV01_TIMER (0x00000004) +/* NvNotification[] elements */ +#define NV004_NOTIFIERS_SET_ALARM_NOTIFY (0) +#define NV004_NOTIFIERS_MAXCOUNT (1) + +/* mapped timer registers */ +typedef volatile struct _Nv01TimerMapTypedef { + NvU32 Reserved00[0x100]; + NvU32 PTimerTime0; /* 0x00009400 */ + NvU32 Reserved01[0x3]; + NvU32 PTimerTime1; /* 0x00009410 */ +} Nv01TimerMap; + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0004_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl0005.h b/userspace/sdks/nv570/nvidia/inc/class/cl0005.h new file mode 100644 index 0000000..2d04c34 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl0005.h @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0005.finn +// + +#include "cl0005_notification.h" + +#define NV01_EVENT (0x5U) /* finn: Evaluated from "NV0005_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* NvRmAlloc() parameters */ +#define NV0005_ALLOC_PARAMETERS_MESSAGE_ID (0x0005U) + +typedef struct NV0005_ALLOC_PARAMETERS { + NvHandle hParentClient; + NvHandle hSrcResource; + + NvV32 hClass; + NvV32 notifyIndex; + NV_DECLARE_ALIGNED(NvP64 data, 8); +} NV0005_ALLOC_PARAMETERS; + + +/* NV0005_ALLOC_PARAMETERS's notifyIndex field is overloaded to contain the + * notifyIndex value itself, plus flags, and optionally a subdevice field if + * flags contains NV01_EVENT_SUBDEVICE_SPECIFIC. Note that NV01_EVENT_* + * contain the full 32-bit flag value that is OR'd into notifyIndex, not the + * contents of the FLAGS field (i.e. NV01_EVENT_* are pre-shifted into place). + */ +#define NV0005_NOTIFY_INDEX_INDEX 15:0 +#define NV0005_NOTIFY_INDEX_SUBDEVICE 23:16 +#define NV0005_NOTIFY_INDEX_FLAGS 31:24 diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl0005_notification.h b/userspace/sdks/nv570/nvidia/inc/class/cl0005_notification.h new file mode 100644 index 0000000..5e6b32e --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl0005_notification.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0005_notification_h_ +#define _cl0005_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* NvNotification[] fields and values */ +#define NV003_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +/* pio method data structure */ +typedef volatile struct _cl0005_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv005Typedef, Nv01Event; + +#define NV005_TYPEDEF Nv01Event + +/* obsolete stuff */ +#define NV1_TIMER (0x00000004) +#define Nv1Event Nv01Event +#define nv1Event Nv01Event +#define nv01Event Nv01Event + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0005_notification_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl000f.h b/userspace/sdks/nv570/nvidia/inc/class/cl000f.h new file mode 100644 index 0000000..7c0d96b --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl000f.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl000f.finn +// + +#define FABRIC_MANAGER_SESSION (0xfU) /* finn: Evaluated from "NV000F_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV000F_NOTIFIERS_FABRIC_EVENT (0) + +#define NV000F_FLAGS_CHANNEL_RECOVERY 0:0 +#define NV000F_FLAGS_CHANNEL_RECOVERY_ENABLED 0x0 +#define NV000F_FLAGS_CHANNEL_RECOVERY_DISABLED 0x1 + +#define NV000F_ALLOCATION_PARAMETERS_MESSAGE_ID (0x000fU) + +typedef struct NV000F_ALLOCATION_PARAMETERS { + // + // capDescriptor is a file descriptor for unix RM clients, but a void + // pointer for windows RM clients. + // + // capDescriptor is transparent to RM clients i.e. RM's user-mode shim + // populates this field on behalf of clients. + // + NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8); + + NvU32 flags; +} NV000F_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl0020.h b/userspace/sdks/nv570/nvidia/inc/class/cl0020.h new file mode 100644 index 0000000..87154a9 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl0020.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0020_h_ +#define _cl0020_h_ + +#include "nvtypes.h" + +#define NV0020_GPU_MANAGEMENT (0x00000020) + +#endif /* _cl0020_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl0030.h b/userspace/sdks/nv570/nvidia/inc/class/cl0030.h new file mode 100644 index 0000000..9a0000e --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl0030.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0030_h_ +#define _cl0030_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV01_NULL (0x00000030) +/* NvNotification[] fields and values */ +#define NV030_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +typedef volatile struct _cl0030_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv030Typedef, Nv01Null; +#define NV030_TYPEDEF Nv01Null +/* obsolete stuff */ +#define NV1_NULL (0x00000030) +#define Nv1Null Nv01Null +#define nv1Null Nv01Null +#define nv01Null Nv01Null + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0030_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl003e.h b/userspace/sdks/nv570/nvidia/inc/class/cl003e.h new file mode 100644 index 0000000..d23e642 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl003e.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2001-2001, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl003e_h_ +#define _cl003e_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV01_CONTEXT_ERROR_TO_MEMORY (0x0000003E) +#define NV01_MEMORY_SYSTEM (0x0000003E) +/* NvNotification[] fields and values */ +#define NV03E_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +typedef volatile struct _cl003e_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv03eTypedef, Nv01ContextErrorToMemory; +#define NV03E_TYPEDEF Nv01ContextErrorToMemory +/* obsolete stuff */ +#define NV1_CONTEXT_ERROR_TO_MEMORY (0x0000003E) +#define Nv1ContextErrorToMemory Nv01ContextErrorToMemory +#define nv1ContextErrorToMemory Nv01ContextErrorToMemory +#define nv01ContextErrorToMemory Nv01ContextErrorToMemory + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl003e_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl003f.h b/userspace/sdks/nv570/nvidia/inc/class/cl003f.h new file mode 100644 index 0000000..b124538 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl003f.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2001-2001, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl003f_h_ +#define _cl003f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV01_MEMORY_LOCAL_PRIVILEGED (0x0000003F) +/* NvNotification[] fields and values */ +#define NV03F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +#ifndef AMD64 +typedef volatile struct _cl003f_tag0 { +#else +typedef struct { +#endif + NvV32 Reserved00[0x7c0]; +} Nv01MemoryLocalPrivileged; +#define NV03F_TYPEDEF Nv01MemoryLocalPrivileged +typedef Nv01MemoryLocalPrivileged Nv03fTypedef; +/* obsolete stuff */ +#define NV01_MEMORY_PRIVILEGED (0x0000003F) +#define NV1_MEMORY_PRIVILEGED (0x0000003F) +#define Nv01MemoryPrivileged Nv01MemoryLocalPrivileged +#define nv01MemoryPrivileged Nv01MemoryLocalPrivileged +#define Nv1MemoryPrivileged Nv01MemoryLocalPrivileged +#define nv1MemoryPrivileged Nv01MemoryLocalPrivileged +#define nv01MemoryLocalPrivileged Nv01MemoryLocalPrivileged + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl003f_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl0040.h b/userspace/sdks/nv570/nvidia/inc/class/cl0040.h new file mode 100644 index 0000000..103ec3a --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl0040.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2001 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl0040_h_ +#define _cl0040_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV01_MEMORY_LOCAL_USER (0x00000040) +/* NvNotification[] fields and values */ +#define NV040_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +typedef volatile struct _cl0040_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv040Typedef, Nv01MemoryLocalUser; +#define NV040_TYPEDEF Nv01MemoryLocalUser +/* obsolete stuff */ +#define NV01_MEMORY_USER (0x00000040) +#define NV1_MEMORY_USER (0x00000040) +#define Nv01MemoryUser Nv01MemoryLocalUser +#define nv01MemoryUser Nv01MemoryLocalUser +#define Nv1MemoryUser Nv01MemoryLocalUser +#define nv1MemoryUser Nv01MemoryLocalUser +#define nv01MemoryLocalUser Nv01MemoryLocalUser + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0040_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl0041.h b/userspace/sdks/nv570/nvidia/inc/class/cl0041.h new file mode 100644 index 0000000..fa8707a --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl0041.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2001-2005, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0041_h_ +#define _cl0041_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV04_MEMORY (0x00000041) +/* NvNotification[] fields and values */ +#define NV041_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +typedef volatile struct _cl0041_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv041Typedef, Nv04Memory; +#define NV041_TYPEDEF Nv04Memory; + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0041_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl0060.h b/userspace/sdks/nv570/nvidia/inc/class/cl0060.h new file mode 100644 index 0000000..80e3778 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl0060.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0060.finn +// + +#define NV0060_SYNC_GPU_BOOST (0x60U) /* finn: Evaluated from "NV0060_ALLOC_PARAMETERS_MESSAGE_ID" */ + +#define NV0060_ALLOC_PARAMETERS_MESSAGE_ID (0x0060U) + +typedef struct NV0060_ALLOC_PARAMETERS { + NvU32 gpuBoostGroupId; +} NV0060_ALLOC_PARAMETERS; diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl0070.h b/userspace/sdks/nv570/nvidia/inc/class/cl0070.h new file mode 100644 index 0000000..c2a8f4b --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl0070.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2001-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0070.finn +// + +#define NV01_MEMORY_VIRTUAL (0x70U) /* finn: Evaluated from "NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_MESSAGE_ID" */ +#define NV01_MEMORY_SYSTEM_DYNAMIC (0x70U) /* finn: Evaluated from "NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_MESSAGE_ID" */ + +/* + * NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS + * + * Allocation params for NV01_MEMORY_VIRTUAL. + * + * NV01_MEMORY_SYSTEM_DYNAMIC is an alias for NV01_MEMORY_VIRTUAL. This + * was traditionally allocated with RmAllocMemory64(). The default GPU + * virtual address space is used, and the limit of this address space is + * returned in limit. The NV01_MEMORY_SYSTEM_DYNAMIC handle can be + * passed to RmAllocContextDma2() with an offset/limit. The context dma + * handle can then be used as the hDma handle for RmMapMemoryDma. + * + * This behavior is maintained in the RM compatibility shim. + * + * NV01_MEMORY_VIRTUAL replaces this behavior with a single object. + * + * hVASpace - if hVASpace is NV01_NULL_OBJECT the default GPU VA space is + * selected. Alternatively a FERMI_VASPACE_A handle may be specified. + * + * The NV_MEMORY_VIRTUAL_SYSMEM_DYNAMIC_HVASPACE is used for by the + * compatibility layer to emulate NV01_MEMORY_SYSTEM_DYNAMIC semantics. + * + * offset - An offset into the virtual address space may be specified. This + * will limit range of the GPU VA returned by RmMapMemoryDma to be + * above offset. + * + * limit - When limit is zero the maximum limit used. If a non-zero limit + * is specified then it will be used. The final limit is returned. + */ +#define NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_MESSAGE_ID (0x0070U) + +typedef struct NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offset, 8); // [IN] - offset into address space + NV_DECLARE_ALIGNED(NvU64 limit, 8); // [IN/OUT] - limit of address space + NvHandle hVASpace; // [IN] - Address space handle +} NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS; + +#define NV_MEMORY_VIRTUAL_SYSMEM_DYNAMIC_HVASPACE 0xffffffffU + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl0071.h b/userspace/sdks/nv570/nvidia/inc/class/cl0071.h new file mode 100644 index 0000000..be106d3 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl0071.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2001-2001, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0071_h_ +#define _cl0071_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV01_MEMORY_SYSTEM_OS_DESCRIPTOR (0x00000071) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0071_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl0073.h b/userspace/sdks/nv570/nvidia/inc/class/cl0073.h new file mode 100644 index 0000000..3775287 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl0073.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2001-2021, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0073_h_ +#define _cl0073_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV04_DISPLAY_COMMON (0x00000073) + +/* event values */ +#define NV0073_NOTIFIERS_SW (0) +#define NV0073_NOTIFIERS_MAXCOUNT (5) + + +#define NV0073_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NV0073_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000) +#define NV0073_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000) +#define NV0073_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000) +#define NV0073_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) + +/* pio method data structure */ +typedef volatile struct _cl0073_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv073Typedef, Nv04DisplayCommon; +#define NV073_TYPEDEF Nv04DisplayCommon + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0073_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl0076.h b/userspace/sdks/nv570/nvidia/inc/class/cl0076.h new file mode 100644 index 0000000..50bd0a9 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl0076.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0076_h_ +#define _cl0076_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV01_MEMORY_FRAMEBUFFER_CONSOLE (0x00000076) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0076_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl007d.h b/userspace/sdks/nv570/nvidia/inc/class/cl007d.h new file mode 100644 index 0000000..f9d25d9 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl007d.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl007d_h_ +#define _cl007d_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV04_SOFTWARE_TEST (0x0000007D) +#define NV07D 0x00001fff:0x00000000 +/* NvNotification[] elements */ +#define NV07D_NOTIFIERS_NOTIFY (0) +#define NV07D_NOTIFIERS_MAXCOUNT (1) +/* NvNotification[] fields and values */ +#define NV07D_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NV07D_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +#define NV07D_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NV07D_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x1000) +#define NV07D_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x0800) +#define NV07D_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) + +/* pio method data structures */ +typedef volatile struct _cl007d_tag0 { + NvV32 NoOperation; /* ignored 0100-0103*/ + NvV32 Notify; /* NV07D_NOTIFY_* 0104-0107*/ + NvV32 Reserved0104[0x78/4]; + NvV32 SetContextDmaNotifies; /* NV01_CONTEXT_DMA 0180-0183*/ + NvV32 Reserved0184[0x1f7c/4]; +} Nv07dTypedef, Nv04SoftwareTest; + +#define NV07D_TYPEDEF Nv04SoftwareTest +/* dma method offsets, fields, and values */ +#define NV07D_SET_OBJECT (0x00000000) +#define NV07D_NO_OPERATION (0x00000100) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl007d_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl0080.h b/userspace/sdks/nv570/nvidia/inc/class/cl0080.h new file mode 100644 index 0000000..7f4bd59 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl0080.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0080.finn +// + +#include "nvlimits.h" +#include "cl0080_notification.h" + +#define NV01_DEVICE_0 (0x80U) /* finn: Evaluated from "NV0080_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* NvAlloc parameteters */ +#define NV0080_MAX_DEVICES NV_MAX_DEVICES + +/** + * @brief Alloc param + * + * @param vaMode mode for virtual address space allocation + * Three modes: + * NV_DEVICE_ALLOCATION_VAMODE_OPTIONAL_MULTIPLE_VASPACES + * NV_DEVICE_ALLOCATION_VAMODE_SINGLE_VASPACE + * NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES + * Detailed description of these modes is in nvos.h + **/ + +#define NV0080_ALLOC_PARAMETERS_MESSAGE_ID (0x0080U) + +typedef struct NV0080_ALLOC_PARAMETERS { + NvU32 deviceId; + NvHandle hClientShare; + NvHandle hTargetClient; + NvHandle hTargetDevice; + NvV32 flags; + NV_DECLARE_ALIGNED(NvU64 vaSpaceSize, 8); + NV_DECLARE_ALIGNED(NvU64 vaStartInternal, 8); + NV_DECLARE_ALIGNED(NvU64 vaLimitInternal, 8); + NvV32 vaMode; +} NV0080_ALLOC_PARAMETERS; diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl0080_notification.h b/userspace/sdks/nv570/nvidia/inc/class/cl0080_notification.h new file mode 100644 index 0000000..a976d3f --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl0080_notification.h @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0080_notification_h_ +#define _cl0080_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* NvNotification[] fields and values */ +#define NV080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +/* pio method data structure */ +typedef volatile struct _cl0080_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv080Typedef, Nv01Device0; + +#define NV080_TYPEDEF Nv01Device0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0080_notification_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl0090.h b/userspace/sdks/nv570/nvidia/inc/class/cl0090.h new file mode 100644 index 0000000..1ed7835 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl0090.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl0090_h_ +#define _cl0090_h_ + +#include "nvtypes.h" + +#define KERNEL_GRAPHICS_CONTEXT (0x00000090) + +#endif /* _cl0090_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl0092.h b/userspace/sdks/nv570/nvidia/inc/class/cl0092.h new file mode 100644 index 0000000..327e0e4 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl0092.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0092.finn +// + +#include "class/cl0092_callback.h" + +/* + * This RgLineCallback class allows RM clients to register/unregister the RG line callback functions. + * + * Must be allocated with kernel access rights. + * + * Allocation params: + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the NV04_DISPLAY_COMMON parent device to which the + * operation should be directed. + * head + * This parameter specifies the head for which the callback is to be egistered/unregistered. This value must be + * less than the maximum number of heads supported by the GPU subdevice. + * rgLineNum + * This indicates the RG scanout line number on which the callback will be executed. + * 1/ Client should set the proper RG line number based on mode in which the display head is running and + * subsequent possible modeset that may affect the line number. + * 2/ Client is expected to clear/set the interrupts around modesets or power-transitions (like s3/hibernation). + * 3/ Client should make sure that this param does not exceed the raster settings. + * pCallbkFn + * Pointer to callback function. Cannot be NULL. + * pCallbkParams + * Pointer to the ctrl call param struct. + */ + +#define NV0092_RG_LINE_CALLBACK (0x92U) /* finn: Evaluated from "NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS_MESSAGE_ID (0x0092U) + +typedef struct NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS { + NvU32 subDeviceInstance; + NvU32 head; + NvU32 rgLineNum; + + NV_DECLARE_ALIGNED(NvP64 pCallbkFn, 8); /* A function pointer of NV0092_REGISTER_RG_LINE_CALLBACK_FN */ + + NV_DECLARE_ALIGNED(NvP64 pCallbkParams, 8); /* The param1 in NV0092_REGISTER_RG_LINE_CALLBACK_FN */ +} NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl0092_callback.h b/userspace/sdks/nv570/nvidia/inc/class/cl0092_callback.h new file mode 100644 index 0000000..4cd86ad --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl0092_callback.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef SDK_CL0092_CALLBACK_H +#define SDK_CL0092_CALLBACK_H + +typedef void (*NV0092_REGISTER_RG_LINE_CALLBACK_FN)(NvU32 rgIntrLine, NvP64 param1, NvBool bIsIrqlIsr); + +#endif // SDK_CL0092_CALLBACK_H diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl00b1.h b/userspace/sdks/nv570/nvidia/inc/class/cl00b1.h new file mode 100644 index 0000000..bc6e69f --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl00b1.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _CL00B1_H_ +#define _CL00B1_H_ + +#define NV01_MEMORY_HW_RESOURCES 0x00b1 + +#endif // _CL00B1_H_ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl00c1.h b/userspace/sdks/nv570/nvidia/inc/class/cl00c1.h new file mode 100644 index 0000000..73fea05 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl00c1.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00c1.finn +// + +#include "nvlimits.h" +#define NV_FB_SEGMENT (0xc1U) /* finn: Evaluated from "NV_FB_SEGMENT_ALLOCATION_PARAMS_MESSAGE_ID" */ + +/* + * NV_FB_SEGMENT_ALLOCATION_PARAMS - Allocation params to create FB segment through + * NvRmAlloc. + */ +#define NV_FB_SEGMENT_ALLOCATION_PARAMS_MESSAGE_ID (0x00C1U) + +typedef struct NV_FB_SEGMENT_ALLOCATION_PARAMS { + NvHandle hCtxDma; // unused + NvU32 subDeviceIDMask; + NV_DECLARE_ALIGNED(NvU64 dmaOffset, 8); // unused + NV_DECLARE_ALIGNED(NvU64 VidOffset, 8); + NV_DECLARE_ALIGNED(NvU64 Offset, 8); // To be deprecated + NV_DECLARE_ALIGNED(NvU64 pOffset[NV_MAX_SUBDEVICES], 8); + NV_DECLARE_ALIGNED(NvU64 Length, 8); + NV_DECLARE_ALIGNED(NvU64 ValidLength, 8); + NV_DECLARE_ALIGNED(NvP64 pPageArray, 8); + NvU32 startPageIndex; + NvHandle AllocHintHandle; + NvU32 Flags; + NvHandle hMemory; // Not used in NvRmAlloc path; only used in CTRL path + NvHandle hClient; // Not used in NvRmAlloc path; only used in CTRL path + NvHandle hDevice; // Not used in NvRmAlloc path; only used in CTRL path + NV_DECLARE_ALIGNED(NvP64 pCpuAddress, 8); // To be deprecated + NV_DECLARE_ALIGNED(NvP64 ppCpuAddress[NV_MAX_SUBDEVICES], 8); + NV_DECLARE_ALIGNED(NvU64 GpuAddress, 8); // To be deprecated + NV_DECLARE_ALIGNED(NvU64 pGpuAddress[NV_MAX_SUBDEVICES], 8); + NvHandle hAllocHintClient; + NvU32 kind; + NvU32 compTag; +} NV_FB_SEGMENT_ALLOCATION_PARAMS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl00c2.h b/userspace/sdks/nv570/nvidia/inc/class/cl00c2.h new file mode 100644 index 0000000..ef2d168 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl00c2.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00c2.finn +// + +#define NV01_MEMORY_LOCAL_PHYSICAL (0xc2U) /* finn: Evaluated from "NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID" */ + +#define NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID (0x00c2U) + +typedef struct NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS { + NV_DECLARE_ALIGNED(NvU64 memSize, 8); // [OUT] + NvU32 format; // [IN] - PTE format to use + NvU32 pageSize; // [IN] - Page size to use +} NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl00c3.h b/userspace/sdks/nv570/nvidia/inc/class/cl00c3.h new file mode 100644 index 0000000..298e582 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl00c3.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00c3.finn +// + +#define NV01_MEMORY_SYNCPOINT (0xc3U) /* finn: Evaluated from "NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS_MESSAGE_ID" */ + +/* + * NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS - Allocation params to create syncpoint + * through NvRmAlloc. + */ +#define NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS_MESSAGE_ID (0x00c3U) + +typedef struct NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS { + NvU32 syncpointId; +} NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl00db.h b/userspace/sdks/nv570/nvidia/inc/class/cl00db.h new file mode 100644 index 0000000..91791bd --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl00db.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00db.finn +// + +#define NV40_DEBUG_BUFFER (0xdbU) /* finn: Evaluated from "NV00DB_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* NvRmAlloc() parameters */ +#define NV00DB_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00dbU) + +typedef struct NV00DB_ALLOCATION_PARAMETERS { + NvU32 size; /* Desired message size / actual size returned */ + NvU32 tag; /* Protobuf tag for message location in dump message */ +} NV00DB_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl00de.h b/userspace/sdks/nv570/nvidia/inc/class/cl00de.h new file mode 100644 index 0000000..8c772ef --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl00de.h @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl00de_h_ +#define _cl00de_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define RM_USER_SHARED_DATA (0x000000de) + +typedef struct NV00DE_SHARED_DATA { + volatile NvU32 seq; + + NvU32 bar1Size; + NvU32 bar1AvailSize; + // New data members always add to bottom +} NV00DE_SHARED_DATA; + +typedef struct NV00DE_ALLOC_PARAMETERS { + // initialize to 0 + NvU32 reserved; +} NV00DE_ALLOC_PARAMETERS; + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl00de_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl00f2.h b/userspace/sdks/nv570/nvidia/inc/class/cl00f2.h new file mode 100644 index 0000000..13b0624 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl00f2.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _cl00f2_h_ +#define _cl00f2_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define IO_VASPACE_A (0x000000f2) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl00f2_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl00f3.h b/userspace/sdks/nv570/nvidia/inc/class/cl00f3.h new file mode 100644 index 0000000..09647c3 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl00f3.h @@ -0,0 +1,75 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00f3.finn +// + + + +/* + * Class definition for creating a memory descriptor from a FLA range in RmAllocMemory. + * No memory is allocated, only a memory descriptor and memory object is created + * for later use in other calls. These classes are used by clients who tries to + * import the memory exported by other GPU(s)/FAM/process. The range, size and + * other parameters are passed as Nv01MemoryFla structure. + */ + +#define NV01_MEMORY_FLA (0xf3U) /* finn: Evaluated from "NV_FLA_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID" */ + +/* + * Structure of NV_FLA_MEMORY_ALLOCATION_PARAMS + * + * + */ +#define NV_FLA_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID (0x00f3U) + +typedef struct NV_FLA_MEMORY_ALLOCATION_PARAMS { + NvU32 type; /* FBMEM: NVOS32_TYPE_* */ + NvU32 flags; /* FBMEM: NVOS32_ALLOC_FLAGS_* */ + NvU32 attr; /* FBMEM: NVOS32_ATTR_* */ + NvU32 attr2; /* FBMEM: NVOS32_ATTR2_* */ + NV_DECLARE_ALIGNED(NvU64 base, 8); /* base of FLA range */ + NV_DECLARE_ALIGNED(NvU64 align, 8); /* alignment for FLA range*/ + NV_DECLARE_ALIGNED(NvU64 limit, 8); + // + // For Direct connected systems, clients need to program this hSubDevice with + // the exporting GPU, for RM to route the traffic to the destination GPU + // Clients need not program this for NvSwitch connected systems + // + NvHandle hExportSubdevice; /* hSubdevice of the exporting GPU */ + // + // Instead of base and limit, clients can also pass the FLA handle (or hExportHandle) + // being exported from destination side to import on the access side + // + NvHandle hExportHandle; /* FLA handle being exported or Export handle */ + // The RM client used to export memory + NvHandle hExportClient; + NvU32 flagsOs02; +} NV_FLA_MEMORY_ALLOCATION_PARAMS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl00f8.h b/userspace/sdks/nv570/nvidia/inc/class/cl00f8.h new file mode 100644 index 0000000..096c46c --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl00f8.h @@ -0,0 +1,119 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00f8.finn +// + + + +/* + * Class definition for allocating a contiguous or discontiguous FLA. + */ + +#define NV_MEMORY_FABRIC (0xf8U) /* finn: Evaluated from "NV00F8_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* + * alignment [IN] + * Alignment for the allocation. + * Should be at least the requested page size. + * + * allocSize [IN] + * Size of the FLA VA. + * + * pageSize [IN] + * Requested page size. Can be any of the NV_MEMORY_FABRIC_PAGE_SIZE_* + * + * allocFlags [IN] + * Can be any of the NV00F8_ALLOC_FLAGS_* + * DEFAULT (sticky) + * The FLA -> PA mappings will be stuck to the object, i.e, once the mapping is created + * there is no way to unmap it explicitly. + * The FLA object must be destroyed to release the mappings. + * The FLA object can't be duped or exported until it has a mapping associated with it. + * Partial FLA->PA mappings will NOT be allowed. + * FLEXIBLE_FLA + * The FLA -> PA mappings can be modified anytime irrespective of the FLA object is duped + * or exported. + * Partial FLA mappings are allowed. + * FORCE_NONCONTIGUOUS + * The allocator may pick contiguous memory whenever possible. This flag forces the + * allocator to always allocate noncontiguous memory. This flag is mainly used for + * testing purpose. So, use with caution. + * FORCE_CONTIGUOUS + * This flag forces the allocator to always allocate contiguous memory. + * READ_ONLY + * The FLA -> PA mappings will be created read-only. This option is only available on + * debug/develop builds due to security concerns. The security concerns are due to the + * fact that FLA access errors (a.k.a PRIV errors) are not aways context attributable. + * + * map.offset [IN] + * Offset into the physical memory descriptor. + * Must be physical memory page size aligned. + * + * map.hVidMem [IN] + * - Handle to the physical memory. + * - Must be passed so that the FLA -> GPA mapping can happen during object creation. + * - For sticky allocations, physical memory being mapped should be large enough + * (accounting map.offset) to cover the whole fabric object allocation size. + * - For flexible allocations, physical memory handle should be zero. + * - Phys memory with 2MB and 512MB pages is supported. + * - hVidMem should belong the same device and client which is allocating FLA. + * + * map.flags [IN] + * Reserved for future use. + * Clients should pass 0 as of now. + */ + +#define NV_MEMORY_FABRIC_PAGE_SIZE_2M 0x200000 +#define NV_MEMORY_FABRIC_PAGE_SIZE_512M 0x20000000 + +#define NV00F8_ALLOC_FLAGS_DEFAULT 0 +#define NV00F8_ALLOC_FLAGS_FLEXIBLE_FLA NVBIT(0) +#define NV00F8_ALLOC_FLAGS_FORCE_NONCONTIGUOUS NVBIT(1) +#define NV00F8_ALLOC_FLAGS_FORCE_CONTIGUOUS NVBIT(2) +#define NV00F8_ALLOC_FLAGS_READ_ONLY NVBIT(3) + +#define NV00F8_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00f8U) + +typedef struct NV00F8_ALLOCATION_PARAMETERS { + + NV_DECLARE_ALIGNED(NvU64 alignment, 8); + NV_DECLARE_ALIGNED(NvU64 allocSize, 8); + + NvU32 pageSize; + NvU32 allocFlags; + + struct { + NV_DECLARE_ALIGNED(NvU64 offset, 8); + + NvHandle hVidMem; + NvU32 flags; + } map; +} NV00F8_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl00fc.h b/userspace/sdks/nv570/nvidia/inc/class/cl00fc.h new file mode 100644 index 0000000..aa50ead --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl00fc.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _cl00fc_h_ +#define _cl00fc_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define FABRIC_VASPACE_A (0x000000fc) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl00fc_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl00fd.h b/userspace/sdks/nv570/nvidia/inc/class/cl00fd.h new file mode 100644 index 0000000..5e80d46 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl00fd.h @@ -0,0 +1,73 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * Class definition for allocating a contiguous or discontiguous Multicast FLA. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00fd.finn +// + +#define NV_MEMORY_MULTICAST_FABRIC (0xfdU) /* finn: Evaluated from "NV00FD_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* + * alignment [IN] + * Alignment for the allocation. + * Should be at least the requested page size. + * + * allocSize [IN] + * Size of the Multicast FLA VA. + * + * pageSize [IN] + * Requested page size. Can be any of the NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_* + * + * allocFlags [IN] + * Reserved for future use + * Clients should pass 0 as of now. + * + * numGpus [IN] + * Number of unique GPUs to be attached. + * + * pOsEvent [IN] + * Optional OS event handle created with NvRmAllocOsEvent(). + */ + +#define NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_512M 0x20000000 + +#define NV00FD_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00fdU) + +typedef struct NV00FD_ALLOCATION_PARAMETERS { + NV_DECLARE_ALIGNED(NvU64 alignment, 8); + NV_DECLARE_ALIGNED(NvU64 allocSize, 8); + NvU32 pageSize; + NvU32 allocFlags; + NvU32 numGpus; + NV_DECLARE_ALIGNED(NvP64 pOsEvent, 8); +} NV00FD_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl00fe.h b/userspace/sdks/nv570/nvidia/inc/class/cl00fe.h new file mode 100644 index 0000000..464c1ec --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl00fe.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00fe.finn +// + +#define NV_MEMORY_MAPPER (0xfeU) /* finn: Evaluated from "NV_MEMORY_MAPPER_ALLOCATION_PARAMS_MESSAGE_ID" */ + +/* + * NV_MEMORY_MAPPER_ALLOCATION_PARAMS + * + * Allocation params for NV_MEMORY_MAPPER. + * This class provides paging operations channel interface to userspace clients. + */ +#define NV_MEMORY_MAPPER_ALLOCATION_PARAMS_MESSAGE_ID (0x00FEU) + +typedef struct NV_MEMORY_MAPPER_ALLOCATION_PARAMS { + NvBool unused; +} NV_MEMORY_MAPPER_ALLOCATION_PARAMS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl2080.h b/userspace/sdks/nv570/nvidia/inc/class/cl2080.h new file mode 100644 index 0000000..32b616f --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl2080.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2002-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl2080.finn +// + +#include "nvlimits.h" +#include "cl2080_notification.h" + +#define NV20_SUBDEVICE_0 (0x2080U) /* finn: Evaluated from "NV2080_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* NvAlloc parameteters */ +#define NV2080_MAX_SUBDEVICES NV_MAX_SUBDEVICES + +#define NV2080_ALLOC_PARAMETERS_MESSAGE_ID (0x2080U) + +typedef struct NV2080_ALLOC_PARAMETERS { + NvU32 subDeviceId; +} NV2080_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl2080_notification.h b/userspace/sdks/nv570/nvidia/inc/class/cl2080_notification.h new file mode 100644 index 0000000..1879905 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl2080_notification.h @@ -0,0 +1,497 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl2080_notification_h_ +#define _cl2080_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* event values */ +#define NV2080_NOTIFIERS_SW (0) +#define NV2080_NOTIFIERS_HOTPLUG (1) +#define NV2080_NOTIFIERS_POWER_CONNECTOR (2) +#define NV2080_NOTIFIERS_THERMAL_SW (3) +#define NV2080_NOTIFIERS_THERMAL_HW (4) +#define NV2080_NOTIFIERS_FULL_SCREEN_CHANGE (5) +#define NV2080_NOTIFIERS_EVENTBUFFER (6) +#define NV2080_NOTIFIERS_DP_IRQ (7) +#define NV2080_NOTIFIERS_GR_DEBUG_INTR (8) +#define NV2080_NOTIFIERS_PMU_EVENT (9) +#define NV2080_NOTIFIERS_PMU_COMMAND (10) +#define NV2080_NOTIFIERS_TIMER (11) +#define NV2080_NOTIFIERS_GRAPHICS (12) +#define NV2080_NOTIFIERS_PPP (13) +#define NV2080_NOTIFIERS_VLD (14) // also known as BSP +#define NV2080_NOTIFIERS_NVDEC0 NV2080_NOTIFIERS_VLD +#define NV2080_NOTIFIERS_NVDEC1 (15) +#define NV2080_NOTIFIERS_NVDEC2 (16) +#define NV2080_NOTIFIERS_NVDEC3 (17) +#define NV2080_NOTIFIERS_NVDEC4 (18) +#define NV2080_NOTIFIERS_NVDEC5 (19) +#define NV2080_NOTIFIERS_NVDEC6 (20) +#define NV2080_NOTIFIERS_NVDEC7 (21) +#define NV2080_NOTIFIERS_PDEC (22) // also known as VP +#define NV2080_NOTIFIERS_CE0 (23) +#define NV2080_NOTIFIERS_CE1 (24) +#define NV2080_NOTIFIERS_CE2 (25) +#define NV2080_NOTIFIERS_CE3 (26) +#define NV2080_NOTIFIERS_CE4 (27) +#define NV2080_NOTIFIERS_CE5 (28) +#define NV2080_NOTIFIERS_CE6 (29) +#define NV2080_NOTIFIERS_CE7 (30) +#define NV2080_NOTIFIERS_CE8 (31) +#define NV2080_NOTIFIERS_CE9 (32) +#define NV2080_NOTIFIERS_PSTATE_CHANGE (33) +#define NV2080_NOTIFIERS_HDCP_STATUS_CHANGE (34) +#define NV2080_NOTIFIERS_FIFO_EVENT_MTHD (35) +#define NV2080_NOTIFIERS_PRIV_RING_HANG (36) +#define NV2080_NOTIFIERS_RC_ERROR (37) +#define NV2080_NOTIFIERS_MSENC (38) +#define NV2080_NOTIFIERS_NVENC0 NV2080_NOTIFIERS_MSENC +#define NV2080_NOTIFIERS_NVENC1 (39) +#define NV2080_NOTIFIERS_NVENC2 (40) +#define NV2080_NOTIFIERS_UNUSED_0 (41) // Unused +#define NV2080_NOTIFIERS_ACPI_NOTIFY (42) +#define NV2080_NOTIFIERS_COOLER_DIAG_ZONE (43) +#define NV2080_NOTIFIERS_THERMAL_DIAG_ZONE (44) +#define NV2080_NOTIFIERS_AUDIO_HDCP_REQUEST (45) +#define NV2080_NOTIFIERS_WORKLOAD_MODULATION_CHANGE (46) +#define NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT (47) +#define NV2080_NOTIFIERS_GPIO_1_RISING_INTERRUPT (48) +#define NV2080_NOTIFIERS_GPIO_2_RISING_INTERRUPT (49) +#define NV2080_NOTIFIERS_GPIO_3_RISING_INTERRUPT (50) +#define NV2080_NOTIFIERS_GPIO_4_RISING_INTERRUPT (51) +#define NV2080_NOTIFIERS_GPIO_5_RISING_INTERRUPT (52) +#define NV2080_NOTIFIERS_GPIO_6_RISING_INTERRUPT (53) +#define NV2080_NOTIFIERS_GPIO_7_RISING_INTERRUPT (54) +#define NV2080_NOTIFIERS_GPIO_8_RISING_INTERRUPT (55) +#define NV2080_NOTIFIERS_GPIO_9_RISING_INTERRUPT (56) +#define NV2080_NOTIFIERS_GPIO_10_RISING_INTERRUPT (57) +#define NV2080_NOTIFIERS_GPIO_11_RISING_INTERRUPT (58) +#define NV2080_NOTIFIERS_GPIO_12_RISING_INTERRUPT (59) +#define NV2080_NOTIFIERS_GPIO_13_RISING_INTERRUPT (60) +#define NV2080_NOTIFIERS_GPIO_14_RISING_INTERRUPT (61) +#define NV2080_NOTIFIERS_GPIO_15_RISING_INTERRUPT (62) +#define NV2080_NOTIFIERS_GPIO_16_RISING_INTERRUPT (63) +#define NV2080_NOTIFIERS_GPIO_17_RISING_INTERRUPT (64) +#define NV2080_NOTIFIERS_GPIO_18_RISING_INTERRUPT (65) +#define NV2080_NOTIFIERS_GPIO_19_RISING_INTERRUPT (66) +#define NV2080_NOTIFIERS_GPIO_20_RISING_INTERRUPT (67) +#define NV2080_NOTIFIERS_GPIO_21_RISING_INTERRUPT (68) +#define NV2080_NOTIFIERS_GPIO_22_RISING_INTERRUPT (69) +#define NV2080_NOTIFIERS_GPIO_23_RISING_INTERRUPT (70) +#define NV2080_NOTIFIERS_GPIO_24_RISING_INTERRUPT (71) +#define NV2080_NOTIFIERS_GPIO_25_RISING_INTERRUPT (72) +#define NV2080_NOTIFIERS_GPIO_26_RISING_INTERRUPT (73) +#define NV2080_NOTIFIERS_GPIO_27_RISING_INTERRUPT (74) +#define NV2080_NOTIFIERS_GPIO_28_RISING_INTERRUPT (75) +#define NV2080_NOTIFIERS_GPIO_29_RISING_INTERRUPT (76) +#define NV2080_NOTIFIERS_GPIO_30_RISING_INTERRUPT (77) +#define NV2080_NOTIFIERS_GPIO_31_RISING_INTERRUPT (78) +#define NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT (79) +#define NV2080_NOTIFIERS_GPIO_1_FALLING_INTERRUPT (80) +#define NV2080_NOTIFIERS_GPIO_2_FALLING_INTERRUPT (81) +#define NV2080_NOTIFIERS_GPIO_3_FALLING_INTERRUPT (82) +#define NV2080_NOTIFIERS_GPIO_4_FALLING_INTERRUPT (83) +#define NV2080_NOTIFIERS_GPIO_5_FALLING_INTERRUPT (84) +#define NV2080_NOTIFIERS_GPIO_6_FALLING_INTERRUPT (85) +#define NV2080_NOTIFIERS_GPIO_7_FALLING_INTERRUPT (86) +#define NV2080_NOTIFIERS_GPIO_8_FALLING_INTERRUPT (87) +#define NV2080_NOTIFIERS_GPIO_9_FALLING_INTERRUPT (88) +#define NV2080_NOTIFIERS_GPIO_10_FALLING_INTERRUPT (89) +#define NV2080_NOTIFIERS_GPIO_11_FALLING_INTERRUPT (90) +#define NV2080_NOTIFIERS_GPIO_12_FALLING_INTERRUPT (91) +#define NV2080_NOTIFIERS_GPIO_13_FALLING_INTERRUPT (92) +#define NV2080_NOTIFIERS_GPIO_14_FALLING_INTERRUPT (93) +#define NV2080_NOTIFIERS_GPIO_15_FALLING_INTERRUPT (94) +#define NV2080_NOTIFIERS_GPIO_16_FALLING_INTERRUPT (95) +#define NV2080_NOTIFIERS_GPIO_17_FALLING_INTERRUPT (96) +#define NV2080_NOTIFIERS_GPIO_18_FALLING_INTERRUPT (97) +#define NV2080_NOTIFIERS_GPIO_19_FALLING_INTERRUPT (98) +#define NV2080_NOTIFIERS_GPIO_20_FALLING_INTERRUPT (99) +#define NV2080_NOTIFIERS_GPIO_21_FALLING_INTERRUPT (100) +#define NV2080_NOTIFIERS_GPIO_22_FALLING_INTERRUPT (101) +#define NV2080_NOTIFIERS_GPIO_23_FALLING_INTERRUPT (102) +#define NV2080_NOTIFIERS_GPIO_24_FALLING_INTERRUPT (103) +#define NV2080_NOTIFIERS_GPIO_25_FALLING_INTERRUPT (104) +#define NV2080_NOTIFIERS_GPIO_26_FALLING_INTERRUPT (105) +#define NV2080_NOTIFIERS_GPIO_27_FALLING_INTERRUPT (106) +#define NV2080_NOTIFIERS_GPIO_28_FALLING_INTERRUPT (107) +#define NV2080_NOTIFIERS_GPIO_29_FALLING_INTERRUPT (108) +#define NV2080_NOTIFIERS_GPIO_30_FALLING_INTERRUPT (109) +#define NV2080_NOTIFIERS_GPIO_31_FALLING_INTERRUPT (110) +#define NV2080_NOTIFIERS_ECC_SBE (111) +#define NV2080_NOTIFIERS_ECC_DBE (112) +#define NV2080_NOTIFIERS_STEREO_EMITTER_DETECTION (113) +#define NV2080_NOTIFIERS_GC5_GPU_READY (114) +#define NV2080_NOTIFIERS_SEC2 (115) +#define NV2080_NOTIFIERS_GC6_REFCOUNT_INC (116) +#define NV2080_NOTIFIERS_GC6_REFCOUNT_DEC (117) +#define NV2080_NOTIFIERS_POWER_EVENT (118) +#define NV2080_NOTIFIERS_CLOCKS_CHANGE (119) +#define NV2080_NOTIFIERS_HOTPLUG_PROCESSING_COMPLETE (120) +#define NV2080_NOTIFIERS_PHYSICAL_PAGE_FAULT (121) +#define NV2080_NOTIFIERS_RESERVED122 (122) +#define NV2080_NOTIFIERS_NVLINK_ERROR_FATAL (123) +#define NV2080_NOTIFIERS_PRIV_REG_ACCESS_FAULT (124) +#define NV2080_NOTIFIERS_NVLINK_ERROR_RECOVERY_REQUIRED (125) +#define NV2080_NOTIFIERS_NVJPG (126) +#define NV2080_NOTIFIERS_NVJPEG0 NV2080_NOTIFIERS_NVJPG +#define NV2080_NOTIFIERS_NVJPEG1 (127) +#define NV2080_NOTIFIERS_NVJPEG2 (128) +#define NV2080_NOTIFIERS_NVJPEG3 (129) +#define NV2080_NOTIFIERS_NVJPEG4 (130) +#define NV2080_NOTIFIERS_NVJPEG5 (131) +#define NV2080_NOTIFIERS_NVJPEG6 (132) +#define NV2080_NOTIFIERS_NVJPEG7 (133) +#define NV2080_NOTIFIERS_RUNLIST_AND_ENG_IDLE (134) +#define NV2080_NOTIFIERS_RUNLIST_ACQUIRE (135) +#define NV2080_NOTIFIERS_RUNLIST_ACQUIRE_AND_ENG_IDLE (136) +#define NV2080_NOTIFIERS_RUNLIST_IDLE (137) +#define NV2080_NOTIFIERS_TSG_PREEMPT_COMPLETE (138) +#define NV2080_NOTIFIERS_RUNLIST_PREEMPT_COMPLETE (139) +#define NV2080_NOTIFIERS_CTXSW_TIMEOUT (140) +#define NV2080_NOTIFIERS_INFOROM_ECC_OBJECT_UPDATED (141) +#define NV2080_NOTIFIERS_NVTELEMETRY_REPORT_EVENT (142) +#define NV2080_NOTIFIERS_DSTATE_XUSB_PPC (143) +#define NV2080_NOTIFIERS_FECS_CTX_SWITCH (144) +#define NV2080_NOTIFIERS_XUSB_PPC_CONNECTED (145) +#define NV2080_NOTIFIERS_GR0 NV2080_NOTIFIERS_GRAPHICS +#define NV2080_NOTIFIERS_GR1 (146) +#define NV2080_NOTIFIERS_GR2 (147) +#define NV2080_NOTIFIERS_GR3 (148) +#define NV2080_NOTIFIERS_GR4 (149) +#define NV2080_NOTIFIERS_GR5 (150) +#define NV2080_NOTIFIERS_GR6 (151) +#define NV2080_NOTIFIERS_GR7 (152) +#define NV2080_NOTIFIERS_OFA (153) +#define NV2080_NOTIFIERS_DSTATE_HDA (154) +#define NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL (155) +#define NV2080_NOTIFIERS_POISON_ERROR_FATAL (156) +#define NV2080_NOTIFIERS_UCODE_RESET (157) +#define NV2080_NOTIFIERS_PLATFORM_POWER_MODE_CHANGE (158) +#define NV2080_NOTIFIERS_SMC_CONFIG_UPDATE (159) +#define NV2080_NOTIFIERS_INFOROM_RRL_OBJECT_UPDATED (160) +#define NV2080_NOTIFIERS_INFOROM_PBL_OBJECT_UPDATED (161) +#define NV2080_NOTIFIERS_LPWR_DIFR_PREFETCH_REQUEST (162) +#define NV2080_NOTIFIERS_SEC_FAULT_ERROR (163) +#define NV2080_NOTIFIERS_POSSIBLE_ERROR (164) +#define NV2080_NOTIFIERS_NVLINK_INFO_LINK_UP (165) +#define NV2080_NOTIFIERS_NVLINK_INFO_LINK_DOWN (176) +#define NV2080_NOTIFIERS_MAXCOUNT (177) + +// Indexed GR notifier reference +#define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x - 1))) +#define NV2080_NOTIFIERS_GR_IDX(x) ((x) - NV2080_NOTIFIERS_GR0) +#define NV2080_NOTIFIER_TYPE_IS_GR(x) (((x) == NV2080_NOTIFIERS_GR0) || (((x) >= NV2080_NOTIFIERS_GR1) && ((x) <= NV2080_NOTIFIERS_GR7))) + +#define NV2080_NOTIFIERS_CE(x) (NV2080_NOTIFIERS_CE0 + (x)) +#define NV2080_NOTIFIERS_CE_IDX(x) ((x) - NV2080_NOTIFIERS_CE0) +#define NV2080_NOTIFIER_TYPE_IS_CE(x) (((x) >= NV2080_NOTIFIERS_CE0) && ((x) <= NV2080_NOTIFIERS_CE9)) + +// Indexed MSENC notifier reference +#define NV2080_NOTIFIERS_NVENC(x) (NV2080_NOTIFIERS_NVENC0 + (x)) +#define NV2080_NOTIFIERS_NVENC_IDX(x) ((x) - NV2080_NOTIFIERS_NVENC0) +#define NV2080_NOTIFIER_TYPE_IS_NVENC(x) (((x) >= NV2080_NOTIFIERS_NVENC0) && ((x) <= NV2080_NOTIFIERS_NVENC2)) +// Indexed NVDEC notifier reference +#define NV2080_NOTIFIERS_NVDEC(x) (NV2080_NOTIFIERS_NVDEC0 + (x)) +#define NV2080_NOTIFIERS_NVDEC_IDX(x) ((x) - NV2080_NOTIFIERS_NVDEC0) +#define NV2080_NOTIFIER_TYPE_IS_NVDEC(x) (((x) >= NV2080_NOTIFIERS_NVDEC0) && ((x) <= NV2080_NOTIFIERS_NVDEC7)) +// Indexed NVJPEG notifier reference +#define NV2080_NOTIFIERS_NVJPEG(x) (NV2080_NOTIFIERS_NVJPEG0 + (x)) +#define NV2080_NOTIFIERS_NVJPEG_IDX(x) ((x) - NV2080_NOTIFIERS_NVJPEG0) +#define NV2080_NOTIFIER_TYPE_IS_NVJPEG(x) (((x) >= NV2080_NOTIFIERS_NVJPEG0) && ((x) <= NV2080_NOTIFIERS_NVJPEG7)) + +#define NV2080_NOTIFIERS_GPIO_RISING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT + (pin)) +#define NV2080_NOTIFIERS_GPIO_FALLING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT + (pin)) + +#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000) +#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000) +#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000) +#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) + +/* exported engine defines */ +#define NV2080_ENGINE_TYPE_NULL (0x00000000) +#define NV2080_ENGINE_TYPE_GRAPHICS (0x00000001) +#define NV2080_ENGINE_TYPE_GR0 NV2080_ENGINE_TYPE_GRAPHICS +#define NV2080_ENGINE_TYPE_GR1 (0x00000002) +#define NV2080_ENGINE_TYPE_GR2 (0x00000003) +#define NV2080_ENGINE_TYPE_GR3 (0x00000004) +#define NV2080_ENGINE_TYPE_GR4 (0x00000005) +#define NV2080_ENGINE_TYPE_GR5 (0x00000006) +#define NV2080_ENGINE_TYPE_GR6 (0x00000007) +#define NV2080_ENGINE_TYPE_GR7 (0x00000008) +#define NV2080_ENGINE_TYPE_COPY0 (0x00000009) +#define NV2080_ENGINE_TYPE_COPY1 (0x0000000a) +#define NV2080_ENGINE_TYPE_COPY2 (0x0000000b) +#define NV2080_ENGINE_TYPE_COPY3 (0x0000000c) +#define NV2080_ENGINE_TYPE_COPY4 (0x0000000d) +#define NV2080_ENGINE_TYPE_COPY5 (0x0000000e) +#define NV2080_ENGINE_TYPE_COPY6 (0x0000000f) +#define NV2080_ENGINE_TYPE_COPY7 (0x00000010) +#define NV2080_ENGINE_TYPE_COPY8 (0x00000011) +#define NV2080_ENGINE_TYPE_COPY9 (0x00000012) +#define NV2080_ENGINE_TYPE_BSP (0x00000013) +#define NV2080_ENGINE_TYPE_NVDEC0 NV2080_ENGINE_TYPE_BSP +#define NV2080_ENGINE_TYPE_NVDEC1 (0x00000014) +#define NV2080_ENGINE_TYPE_NVDEC2 (0x00000015) +#define NV2080_ENGINE_TYPE_NVDEC3 (0x00000016) +#define NV2080_ENGINE_TYPE_NVDEC4 (0x00000017) +#define NV2080_ENGINE_TYPE_NVDEC5 (0x00000018) +#define NV2080_ENGINE_TYPE_NVDEC6 (0x00000019) +#define NV2080_ENGINE_TYPE_NVDEC7 (0x0000001a) +#define NV2080_ENGINE_TYPE_MSENC (0x0000001b) +#define NV2080_ENGINE_TYPE_NVENC0 NV2080_ENGINE_TYPE_MSENC /* Mutually exclusive alias */ +#define NV2080_ENGINE_TYPE_NVENC1 (0x0000001c) +#define NV2080_ENGINE_TYPE_NVENC2 (0x0000001d) +#define NV2080_ENGINE_TYPE_VP (0x0000001e) +#define NV2080_ENGINE_TYPE_ME (0x0000001f) +#define NV2080_ENGINE_TYPE_PPP (0x00000020) +#define NV2080_ENGINE_TYPE_MPEG (0x00000021) +#define NV2080_ENGINE_TYPE_SW (0x00000022) +#define NV2080_ENGINE_TYPE_CIPHER (0x00000023) +#define NV2080_ENGINE_TYPE_TSEC NV2080_ENGINE_TYPE_CIPHER +#define NV2080_ENGINE_TYPE_VIC (0x00000024) +#define NV2080_ENGINE_TYPE_MP (0x00000025) +#define NV2080_ENGINE_TYPE_SEC2 (0x00000026) +#define NV2080_ENGINE_TYPE_HOST (0x00000027) +#define NV2080_ENGINE_TYPE_DPU (0x00000028) +#define NV2080_ENGINE_TYPE_PMU (0x00000029) +#define NV2080_ENGINE_TYPE_FBFLCN (0x0000002a) +#define NV2080_ENGINE_TYPE_NVJPG (0x0000002b) +#define NV2080_ENGINE_TYPE_NVJPEG0 NV2080_ENGINE_TYPE_NVJPG +#define NV2080_ENGINE_TYPE_NVJPEG1 (0x0000002c) +#define NV2080_ENGINE_TYPE_NVJPEG2 (0x0000002d) +#define NV2080_ENGINE_TYPE_NVJPEG3 (0x0000002e) +#define NV2080_ENGINE_TYPE_NVJPEG4 (0x0000002f) +#define NV2080_ENGINE_TYPE_NVJPEG5 (0x00000030) +#define NV2080_ENGINE_TYPE_NVJPEG6 (0x00000031) +#define NV2080_ENGINE_TYPE_NVJPEG7 (0x00000032) +#define NV2080_ENGINE_TYPE_OFA (0x00000033) +#define NV2080_ENGINE_TYPE_LAST (0x0000003e) +#define NV2080_ENGINE_TYPE_ALLENGINES (0xffffffff) + +#define NV2080_ENGINE_TYPE_COPY_SIZE 10 +#define NV2080_ENGINE_TYPE_NVENC_SIZE 3 +#define NV2080_ENGINE_TYPE_NVJPEG_SIZE 8 +#define NV2080_ENGINE_TYPE_NVDEC_SIZE 8 +#define NV2080_ENGINE_TYPE_GR_SIZE 8 + +// Indexed engines +#define NV2080_ENGINE_TYPE_COPY(i) (NV2080_ENGINE_TYPE_COPY0+(i)) +#define NV2080_ENGINE_TYPE_IS_COPY(i) (((i) >= NV2080_ENGINE_TYPE_COPY0) && ((i) <= NV2080_ENGINE_TYPE_COPY9)) +#define NV2080_ENGINE_TYPE_COPY_IDX(i) ((i) - NV2080_ENGINE_TYPE_COPY0) + +#define NV2080_ENGINE_TYPE_NVENC(i) (NV2080_ENGINE_TYPE_NVENC0+(i)) +#define NV2080_ENGINE_TYPE_IS_NVENC(i) (((i) >= NV2080_ENGINE_TYPE_NVENC0) && ((i) < NV2080_ENGINE_TYPE_NVENC(NV2080_ENGINE_TYPE_NVENC_SIZE))) +#define NV2080_ENGINE_TYPE_NVENC_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVENC0) + +#define NV2080_ENGINE_TYPE_NVDEC(i) (NV2080_ENGINE_TYPE_NVDEC0+(i)) +#define NV2080_ENGINE_TYPE_IS_NVDEC(i) (((i) >= NV2080_ENGINE_TYPE_NVDEC0) && ((i) < NV2080_ENGINE_TYPE_NVDEC(NV2080_ENGINE_TYPE_NVDEC_SIZE))) +#define NV2080_ENGINE_TYPE_NVDEC_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVDEC0) + +#define NV2080_ENGINE_TYPE_NVJPEG(i) (NV2080_ENGINE_TYPE_NVJPEG0+(i)) +#define NV2080_ENGINE_TYPE_IS_NVJPEG(i) (((i) >= NV2080_ENGINE_TYPE_NVJPEG0) && ((i) < NV2080_ENGINE_TYPE_NVJPEG(NV2080_ENGINE_TYPE_NVJPEG_SIZE))) +#define NV2080_ENGINE_TYPE_NVJPEG_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVJPEG0) + +#define NV2080_ENGINE_TYPE_GR(i) (NV2080_ENGINE_TYPE_GR0 + (i)) +#define NV2080_ENGINE_TYPE_IS_GR(i) (((i) >= NV2080_ENGINE_TYPE_GR0) && ((i) < NV2080_ENGINE_TYPE_GR(NV2080_ENGINE_TYPE_GR_SIZE))) +#define NV2080_ENGINE_TYPE_GR_IDX(i) ((i) - NV2080_ENGINE_TYPE_GR0) + +#define NV2080_ENGINE_TYPE_IS_VALID(i) (((i) > (NV2080_ENGINE_TYPE_NULL)) && ((i) < (NV2080_ENGINE_TYPE_LAST))) + +/* exported client defines */ +#define NV2080_CLIENT_TYPE_TEX (0x00000001) +#define NV2080_CLIENT_TYPE_COLOR (0x00000002) +#define NV2080_CLIENT_TYPE_DEPTH (0x00000003) +#define NV2080_CLIENT_TYPE_DA (0x00000004) +#define NV2080_CLIENT_TYPE_FE (0x00000005) +#define NV2080_CLIENT_TYPE_SCC (0x00000006) +#define NV2080_CLIENT_TYPE_WID (0x00000007) +#define NV2080_CLIENT_TYPE_MSVLD (0x00000008) +#define NV2080_CLIENT_TYPE_MSPDEC (0x00000009) +#define NV2080_CLIENT_TYPE_MSPPP (0x0000000a) +#define NV2080_CLIENT_TYPE_VIC (0x0000000b) +#define NV2080_CLIENT_TYPE_ALLCLIENTS (0xffffffff) + +/* GC5 Gpu Ready event defines */ +#define NV2080_GC5_EXIT_COMPLETE (0x00000001) +#define NV2080_GC5_ENTRY_ABORTED (0x00000002) + +/* Platform Power Mode event defines */ +#define NV2080_PLATFORM_POWER_MODE_CHANGE_COMPLETION (0x00000000) +#define NV2080_PLATFORM_POWER_MODE_CHANGE_ACPI_NOTIFICATION (0x00000001) + +/* NvNotification[] fields and values */ +#define NV2080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +typedef volatile struct _cl2080_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv2080Typedef, Nv20Subdevice0; +#define NV2080_TYPEDEF Nv20Subdevice0 + +/* HDCP Status change notification information */ +typedef struct Nv2080HdcpStatusChangeNotificationRec { + NvU32 displayId; + NvU32 hdcpStatusChangeNotif; +} Nv2080HdcpStatusChangeNotification; + +/* Pstate change notification information */ +typedef struct Nv2080PStateChangeNotificationRec { + struct { + NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/ + } timeStamp; /* -0007*/ + NvU32 NewPstate; +} Nv2080PStateChangeNotification; + +/* Clocks change notification information */ +typedef struct Nv2080ClocksChangeNotificationRec { + struct { + NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/ + } timeStamp; /* -0007*/ +} Nv2080ClocksChangeNotification; + +/* WorkLoad Modulation state change notification information*/ +typedef struct Nv2080WorkloadModulationChangeNotificationRec { + struct { + NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/ + } timeStamp; /* -0007*/ + NvBool WorkloadModulationEnabled; +} Nv2080WorkloadModulationChangeNotification; + +/* Hotplug notification information */ +typedef struct { + NvU32 plugDisplayMask; + NvU32 unplugDisplayMask; +} Nv2080HotplugNotification; + +/* Power state changing notification information */ +typedef struct { + NvBool bSwitchToAC; + NvBool bGPUCapabilityChanged; + NvU32 displayMaskAffected; +} Nv2080PowerEventNotification; + +/* DP IRQ notification information */ +typedef struct Nv2080DpIrqNotificationRec { + NvU32 displayId; +} Nv2080DpIrqNotification; + +/* XUSB/PPC D-State change notification information */ +typedef struct Nv2080DstateXusbPpcNotificationRec { + NvU32 dstateXusb; + NvU32 dstatePpc; +} Nv2080DstateXusbPpcNotification; + +/* XUSB/PPC Connection status notification information */ +typedef struct Nv2080XusbPpcConnectStateNotificationRec { + NvBool bConnected; +} Nv2080XusbPpcConnectStateNotification; + +/* ACPI event notification information */ +typedef struct Nv2080ACPIEvent { + NvU32 event; +} Nv2080ACPIEvent; + +/* Cooler Zone notification information */ +typedef struct _NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC { + NvU32 currentZone; +} NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC; + +/* Thermal Zone notification information */ +typedef struct _NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC { + NvU32 currentZone; +} NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC; + +/* HDCP ref count change notification information */ +typedef struct Nv2080AudioHdcpRequestRec { + NvU32 displayId; + NvU32 requestedState; +} Nv2080AudioHdcpRequest; + +/* Gpu ready event information */ +typedef struct Nv2080GC5GpuReadyParams { + NvU32 event; + NvU32 sciIntr0; + NvU32 sciIntr1; +} Nv2080GC5GpuReadyParams; + +/* Priv reg access fault notification information */ +typedef struct { + NvU32 errAddr; +} Nv2080PrivRegAccessFaultNotification; + +/* HDA D-State change notification information + * See @HDACODEC_DSTATE for definitions + */ +typedef struct Nv2080DstateHdaCodecNotificationRec { + NvU32 dstateHdaCodec; +} Nv2080DstateHdaCodecNotification; + +/* + * Platform Power Mode event information + */ +typedef struct _NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS { + NvU8 platformPowerModeIndex; + NvU8 platformPowerModeMask; + NvU8 eventReason; +} NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS; + +#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_INDEX 7:0 +#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_MASK 15:8 +#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_REASON 23:16 + +/* + * ENGINE_INFO_TYPE_NV2080 of the engine for which the QOS interrupt has been raised + */ +typedef struct { + NvU32 engineType; +} Nv2080QosIntrNotification; + +typedef struct { + NvU64 physAddress NV_ALIGN_BYTES(8); +} Nv2080EccDbeNotification; + +/* + * LPWR DIFR Prefetch Request - Size of L2 Cache + */ +typedef struct { + NvU32 l2CacheSize; +} Nv2080LpwrDifrPrefetchNotification; + +/* + * Nvlink Link status change Notification + */ +typedef struct { + NvU32 GpuId; + NvU32 linkId; +} Nv2080NvlinkLnkChangeNotification; + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl2080_notification_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl2081.h b/userspace/sdks/nv570/nvidia/inc/class/cl2081.h new file mode 100644 index 0000000..05341ca --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl2081.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl2081.finn +// + +#define NV2081_BINAPI (0x2081U) /* finn: Evaluated from "NV2081_ALLOC_PARAMETERS_MESSAGE_ID" */ + +#define NV2081_ALLOC_PARAMETERS_MESSAGE_ID (0x2081U) + +typedef struct NV2081_ALLOC_PARAMETERS { + NvU32 reserved; +} NV2081_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl2082.h b/userspace/sdks/nv570/nvidia/inc/class/cl2082.h new file mode 100644 index 0000000..0a721f5 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl2082.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl2082.finn +// + +#define NV2082_BINAPI_PRIVILEGED (0x2082U) /* finn: Evaluated from "NV2082_ALLOC_PARAMETERS_MESSAGE_ID" */ + +#define NV2082_ALLOC_PARAMETERS_MESSAGE_ID (0x2082U) + +typedef struct NV2082_ALLOC_PARAMETERS { + NvU32 reserved; +} NV2082_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl208f.h b/userspace/sdks/nv570/nvidia/inc/class/cl208f.h new file mode 100644 index 0000000..c9d7f01 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl208f.h @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2006 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl208f_h_ +#define _cl208f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* Class within the subdevice used for diagnostic purpose*/ +#define NV20_SUBDEVICE_DIAG (0x0000208f) + +/* event values */ +#define NV208F_NOTIFIERS_SW (0) +#define NV208F_NOTIFIERS_MAXCOUNT (1) + +/* NvNotification[] fields and values */ +#define NV208f_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +typedef volatile struct _cl208f_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv208fTypedef, Nv20SubdeviceDiag; +#define NV208f_TYPEDEF Nv20SubdeviceDiag + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl208f_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl30f1.h b/userspace/sdks/nv570/nvidia/inc/class/cl30f1.h new file mode 100644 index 0000000..b7edbd2 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl30f1.h @@ -0,0 +1,56 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl30f1.finn +// + +#include "cl30f1_notification.h" + +/* class NV30_GSYNC */ +#define NV30_GSYNC (0x30f1U) /* finn: Evaluated from "NV30F1_ALLOC_PARAMETERS_MESSAGE_ID" */ + +#define NV30F1_GSYNC_CONNECTOR_ONE (0) +#define NV30F1_GSYNC_CONNECTOR_TWO (1) +#define NV30F1_GSYNC_CONNECTOR_THREE (2) +#define NV30F1_GSYNC_CONNECTOR_FOUR (3) + +#define NV30F1_GSYNC_CONNECTOR_PRIMARY NV30F1_GSYNC_CONNECTOR_ONE +#define NV30F1_GSYNC_CONNECTOR_SECONDARY NV30F1_GSYNC_CONNECTOR_TWO + +#define NV30F1_GSYNC_CONNECTOR_COUNT (4) + +/* NvRmAlloc parameters */ +#define NV30F1_MAX_GSYNCS (0x0000004) + +#define NV30F1_ALLOC_PARAMETERS_MESSAGE_ID (0x30f1U) + +typedef struct NV30F1_ALLOC_PARAMETERS { + NvU32 gsyncInstance; +} NV30F1_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl30f1_notification.h b/userspace/sdks/nv570/nvidia/inc/class/cl30f1_notification.h new file mode 100644 index 0000000..290eb5c --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl30f1_notification.h @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl30f1_notification_h_ +#define _cl30f1_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * A client should use NV01_EVENT_OS_EVENT as hClass and NV30F1_GSYNC_NOTIFIERS_* as + * notify index when allocating event, if separate event notifications are needed for + * separate event types. + * + * A client should use NV01_EVENT_KERNEL_CALLBACK as hClass and + * NV30F1_GSYNC_NOTIFIERS_ALL as notify index, if a single event is required. + * In this case RM would set event data equal to a pointer to NvNotification structure. + * The info32 field of NvNotification structure would be equal a bitmask of + * NV30F1_GSYNC_NOTIFIERS_* values. + */ + +/* NvNotification[] fields and values */ + +/* Framelock sync gain and loss events. These are connector specific events. */ +#define NV30F1_GSYNC_NOTIFIERS_SYNC_LOSS(c) (0x00+(c)) +#define NV30F1_GSYNC_NOTIFIERS_SYNC_GAIN(c) (0x04+(c)) + +/* Framelock stereo gain and loss events. These are connector specific events. */ +#define NV30F1_GSYNC_NOTIFIERS_STEREO_LOSS(c) (0x08+(c)) +#define NV30F1_GSYNC_NOTIFIERS_STEREO_GAIN(c) (0x0C+(c)) + +/* House cable gain(plug in) and loss(plug out) events. */ +#define NV30F1_GSYNC_NOTIFIERS_HOUSE_GAIN (0x10) +#define NV30F1_GSYNC_NOTIFIERS_HOUSE_LOSS (0x11) + +/* RJ45 cable gain(plug in) and loss(plug out) events. */ +#define NV30F1_GSYNC_NOTIFIERS_RJ45_GAIN (0x12) +#define NV30F1_GSYNC_NOTIFIERS_RJ45_LOSS (0x13) + +#define NV30F1_GSYNC_NOTIFIERS_MAXCOUNT (0x14) + +/* + * For handling all event types. + * Note for Windows, it only handles NV01_EVENT_KERNEL_CALLBACK_EX; as for NV01_EVENT_OS_EVENT, it can only + * signal an event but not handle over any information. + */ +#define NV30F1_GSYNC_NOTIFIERS_ALL NV30F1_GSYNC_NOTIFIERS_MAXCOUNT + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl30f1_notification_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl402c.h b/userspace/sdks/nv570/nvidia/inc/class/cl402c.h new file mode 100644 index 0000000..9ba7c3b --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl402c.h @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2010 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl402c_h_ +#define _cl402c_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* I2C operations */ +#define NV40_I2C (0x0000402c) + +typedef volatile struct _cl402c_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv402cTypedef, Nv40I2c; +#define NV402C_TYPEDEF Nv40I2c + + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl402c_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl503b.h b/userspace/sdks/nv570/nvidia/inc/class/cl503b.h new file mode 100644 index 0000000..b372f78 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl503b.h @@ -0,0 +1,57 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl503b.finn +// + +#define NV50_P2P (0x503bU) /* finn: Evaluated from "NV503B_ALLOC_PARAMETERS_MESSAGE_ID" */ + +#define NV503B_FLAGS_P2P_TYPE 0:0 +#define NV503B_FLAGS_P2P_TYPE_GPA 0 +#define NV503B_FLAGS_P2P_TYPE_SPA 1 + +/* NvRmAlloc parameters */ +#define NV503B_ALLOC_PARAMETERS_MESSAGE_ID (0x503bU) + +typedef struct NV503B_ALLOC_PARAMETERS { + NvHandle hSubDevice; /* subDevice handle of local GPU */ + NvHandle hPeerSubDevice; /* subDevice handle of peer GPU */ + NvU32 subDevicePeerIdMask; /* Bit mask of peer ID for SubDevice + * A value of 0 defaults to RM selected + * PeerIdMasks must match in loopback */ + NvU32 peerSubDevicePeerIdMask; /* Bit mask of peer ID for PeerSubDevice + * A value of 0 defaults to RM selected + * PeerIdMasks must match in loopback */ + NV_DECLARE_ALIGNED(NvU64 mailboxBar1Addr, 8); /* P2P Mailbox area base offset in BAR1 + * Must have the same value across the GPUs */ + NvU32 mailboxTotalSize; /* Size of the P2P Mailbox area + * Must have the same value across the GPUs */ + NvU32 flags; /* Flag to indicate types/attib of p2p */ +} NV503B_ALLOC_PARAMETERS; diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl503c.h b/userspace/sdks/nv570/nvidia/inc/class/cl503c.h new file mode 100644 index 0000000..7f28960 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl503c.h @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl503c.finn +// + +#define NV50_THIRD_PARTY_P2P (0x503cU) /* finn: Evaluated from "NV503C_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* NvRmAlloc parameters */ +#define NV503C_ALLOC_PARAMETERS_MESSAGE_ID (0x503cU) + +typedef struct NV503C_ALLOC_PARAMETERS { + NvU32 flags; +} NV503C_ALLOC_PARAMETERS; + +#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE 1:0 +#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_PROPRIETARY (0x00000000) +#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_BAR1 (0x00000001) +#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_NVLINK (0x00000002) + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl506f.h b/userspace/sdks/nv570/nvidia/inc/class/cl506f.h new file mode 100644 index 0000000..b086c43 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl506f.h @@ -0,0 +1,157 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl506f_h_ +#define _cl506f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class NV50_CHANNEL_GPFIFO */ +#define NV50_CHANNEL_GPFIFO (0x0000506F) + +/* NvNotification[] elements */ +#define NV506F_NOTIFIERS_RC (0) +#define NV506F_NOTIFIERS_SW (1) +#define NV506F_NOTIFIERS_GR_DEBUG_INTR (2) +#define NV506F_NOTIFIERS_MAXCOUNT (3) + +/* NvNotification[] fields and values */ +#define NV506f_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NV506f_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +typedef volatile struct _cl506f_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv506fTypedef, Nv50ChannelGPFifo; +#define NV506F_TYPEDEF Nv50ChannelGPFifo +/* pio flow control data structure */ +typedef volatile struct _cl506f_tag1 { + NvU32 Ignored00[0x010]; /* 0000-0039*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 SetReference; /* set reference value 0050-0053*/ + NvU32 Ignored02[0x001]; /* 0054-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored03[0x007]; /* 0064-007f*/ + NvU32 Yield; /* engine yield, write only 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x3dc]; +} Nv506fControl, Nv50ControlGPFifo; +/* fields and values */ +#define NV506F_NUMBER_OF_SUBCHANNELS (8) +#define NV506F_SET_OBJECT (0x00000000) +#define NV506F_SET_REFERENCE (0x00000050) +#define NV506F_SET_CONTEXT_DMA_SEMAPHORE (0x00000060) +#define NV506F_SEMAPHORE_OFFSET (0x00000064) +#define NV506F_SEMAPHORE_ACQUIRE (0x00000068) +#define NV506F_SEMAPHORE_RELEASE (0x0000006c) +#define NV506F_YIELD (0x00000080) + +// +// GPFIFO entry format +// +#define NV506F_GP_ENTRY__SIZE 8 +#define NV506F_GP_ENTRY0_DISABLE 0:0 +#define NV506F_GP_ENTRY0_DISABLE_NOT 0x00000000 +#define NV506F_GP_ENTRY0_DISABLE_SKIP 0x00000001 +#define NV506F_GP_ENTRY0_NO_CONTEXT_SWITCH 1:1 +#define NV506F_GP_ENTRY0_NO_CONTEXT_SWITCH_FALSE 0x00000000 +#define NV506F_GP_ENTRY0_NO_CONTEXT_SWITCH_TRUE 0x00000001 +#define NV506F_GP_ENTRY0_GET 31:2 +#define NV506F_GP_ENTRY1_GET_HI 7:0 +#define NV506F_GP_ENTRY1_PRIV 8:8 +#define NV506F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NV506F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NV506F_GP_ENTRY1_LEVEL 9:9 +#define NV506F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NV506F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NV506F_GP_ENTRY1_LENGTH 31:10 + +/* dma method descriptor formats */ +#define NV506F_DMA_PRIMARY_OPCODE 1:0 +#define NV506F_DMA_PRIMARY_OPCODE_USES_SECONDARY (0x00000000) +#define NV506F_DMA_PRIMARY_OPCODE_RESERVED (0x00000003) +#define NV506F_DMA_METHOD_ADDRESS 12:2 +#define NV506F_DMA_METHOD_SUBCHANNEL 15:13 +#define NV506F_DMA_TERT_OP 17:16 +#define NV506F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NV506F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NV506F_DMA_TERT_OP_GRP0_DOUBLE_HEADER (0x00000003) +#define NV506F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NV506F_DMA_TERT_OP_GRP2_RESERVED01 (0x00000001) +#define NV506F_DMA_TERT_OP_GRP2_RESERVED10 (0x00000002) +#define NV506F_DMA_TERT_OP_GRP2_RESERVED11 (0x00000003) +#define NV506F_DMA_METHOD_COUNT 28:18 +#define NV506F_DMA_SEC_OP 31:29 +#define NV506F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NV506F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NV506F_DMA_SEC_OP_GRP3_RESERVED (0x00000003) +#define NV506F_DMA_SEC_OP_GRP4_RESERVED (0x00000004) +#define NV506F_DMA_SEC_OP_GRP5_RESERVED (0x00000005) +#define NV506F_DMA_SEC_OP_GRP6_RESERVED (0x00000006) +#define NV506F_DMA_SEC_OP_GRP7_RESERVED (0x00000007) +#define NV506F_DMA_LONG_COUNT 31:0 +/* dma legacy method descriptor format */ +#define NV506F_DMA_OPCODE2 1:0 +#define NV506F_DMA_OPCODE2_NONE (0x00000000) +#define NV506F_DMA_OPCODE 31:29 +#define NV506F_DMA_OPCODE_METHOD (0x00000000) +#define NV506F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NV506F_DMA_OPCODE3_NONE (0x00000000) +/* dma data format */ +#define NV506F_DMA_DATA 31:0 +/* dma double header descriptor format */ +#define NV506F_DMA_DH_OPCODE2 1:0 +#define NV506F_DMA_DH_OPCODE2_NONE (0x00000000) +#define NV506F_DMA_DH_METHOD_ADDRESS 12:2 +#define NV506F_DMA_DH_METHOD_SUBCHANNEL 15:13 +#define NV506F_DMA_DH_OPCODE3 17:16 +#define NV506F_DMA_DH_OPCODE3_DOUBLE_HEADER (0x00000003) +#define NV506F_DMA_DH_OPCODE 31:29 +#define NV506F_DMA_DH_OPCODE_METHOD (0x00000000) +/* dma double header method count format */ +#define NV506F_DMA_DH_METHOD_COUNT 23:0 +/* dma double header data format */ +#define NV506F_DMA_DH_DATA 31:0 +/* dma nop format */ +#define NV506F_DMA_NOP (0x00000000) +/* dma set subdevice mask format */ +#define NV506F_DMA_SET_SUBDEVICE_MASK (0x00010000) +#define NV506F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NV506F_DMA_OPCODE3 17:16 +#define NV506F_DMA_OPCODE3_SET_SUBDEVICE_MASK (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl506f_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl5070.h b/userspace/sdks/nv570/nvidia/inc/class/cl5070.h new file mode 100644 index 0000000..6a26551 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl5070.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl5070.finn +// + +#include "cl5070_notification.h" + +#define NV50_DISPLAY (0x5070U) /* finn: Evaluated from "NV5070_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV5070_ALLOCATION_PARAMETERS_MESSAGE_ID (0x5070U) + +typedef struct NV5070_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numDacs; // Number of DACs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NV5070_ALLOCATION_PARAMETERS; diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl5070_notification.h b/userspace/sdks/nv570/nvidia/inc/class/cl5070_notification.h new file mode 100644 index 0000000..a23107d --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl5070_notification.h @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl5070_notification_h_ +#define _cl5070_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* event values */ +#define NV5070_NOTIFIERS_SW (0) +#define NV5070_NOTIFIERS_MAXCOUNT (1) + +#define NV5070_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NV5070_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000) +#define NV5070_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000) +#define NV5070_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000) +#define NV5070_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl5070_notification_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl5080.h b/userspace/sdks/nv570/nvidia/inc/class/cl5080.h new file mode 100644 index 0000000..cf05945 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl5080.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2002-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl5080.finn +// + +#include "cl5080_notification.h" + +#define NV50_DEFERRED_API_CLASS (0x5080U) /* finn: Evaluated from "NV5080_ALLOC_PARAMS_MESSAGE_ID" */ + +/* NvRmAlloc parameters */ +#define NV5080_ALLOC_PARAMS_MESSAGE_ID (0x5080U) + +typedef struct NV5080_ALLOC_PARAMS { + // Should the deferred api completion trigger an event + NvBool notifyCompletion; +} NV5080_ALLOC_PARAMS; + +// Class-specific allocation capabilities + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl5080_notification.h b/userspace/sdks/nv570/nvidia/inc/class/cl5080_notification.h new file mode 100644 index 0000000..170c8fb --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl5080_notification.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl5080_notification_h_ +#define _cl5080_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* dma method offsets, fields, and values */ +#define NV5080_SET_OBJECT (0x00000000) +#define NV5080_NO_OPERATION (0x00000100) +#define NV5080_DEFERRED_API (0x00000200) +#define NV5080_DEFERRED_API_HANDLE 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl5080_notification_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl50a0.h b/userspace/sdks/nv570/nvidia/inc/class/cl50a0.h new file mode 100644 index 0000000..5fec57e --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl50a0.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2005, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl50a0_h_ +#define _cl50a0_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV50_MEMORY_VIRTUAL (0x000050a0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl50a0_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl83de.h b/userspace/sdks/nv570/nvidia/inc/class/cl83de.h new file mode 100644 index 0000000..df67deb --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl83de.h @@ -0,0 +1,56 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl83de.finn +// + +#define GT200_DEBUGGER (0x83deU) /* finn: Evaluated from "NV83DE_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* + * Creating the GT200_DEBUGGER object: + * - The debug object is instantiated as a child of either the compute or the + * 3D-class object. + * - The Cuda/GR debugger uses the NV83DE_ALLOC_PARAMETERS to fill in the Client + * and 3D-Class handles of the debuggee and passes this to the NvRmAlloc. + * e.g: + NV83DE_ALLOC_PARAMETERS params; + * memset (¶ms, 0, sizeof (NV83DE_ALLOC_PARAMETERS)); + * params.hAppClient = DebuggeeClient; + * params.hClass3dObject = 3DClassHandle; + * NvRmAlloc(hDebuggerClient, hDebuggerClient, hDebugger, GT200_DEBUGGER, ¶ms); + */ + +#define NV83DE_ALLOC_PARAMETERS_MESSAGE_ID (0x83deU) + +typedef struct NV83DE_ALLOC_PARAMETERS { + NvHandle hDebuggerClient_Obsolete; // No longer supported (must be zero) + NvHandle hAppClient; + NvHandle hClass3dObject; +} NV83DE_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl844c.h b/userspace/sdks/nv570/nvidia/inc/class/cl844c.h new file mode 100644 index 0000000..c4afe5f --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl844c.h @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl844c_h_ +#define _cl844c_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define G84_PERFBUFFER (0x0000844C) + +/* pio method data structure */ +typedef volatile struct _cl844c_tag0 { + NvV32 Reserved00[0x7c0]; +} G844cTypedef, G84PerfBuffer; +#define G844C_TYPEDEF G84PerfBuffer + +#define G844C_PERFBUFFER_MEMORY_HANDLE (0x844C0001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl844c_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl84a0.h b/userspace/sdks/nv570/nvidia/inc/class/cl84a0.h new file mode 100644 index 0000000..1ee51ad --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl84a0.h @@ -0,0 +1,110 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl84a0.finn +// + +#include "cl84a0_deprecated.h" + +/* + * Class definitions for creating a memory descriptor from a list of page numbers + * in RmAllocMemory. No memory is allocated: only a memory descriptor and + * memory object are created for later use in other calls. These classes + * are used by vGPU to create references to memory assigned to a guest VM. + * In all cases, the list is passed as reference, in the pAddress argument + * of RmAllocMemory, to a Nv01MemoryList structure (cast to a void **). + */ + +/* List of system memory physical page numbers */ +#define NV01_MEMORY_LIST_SYSTEM (0x00000081) +/* List of frame buffer physical page numbers */ +#define NV01_MEMORY_LIST_FBMEM (0x00000082) +/* List of page numbers relative to the start of the specified object */ +#define NV01_MEMORY_LIST_OBJECT (0x00000083) + +/* + * List structure of NV01_MEMORY_LIST_* classes + * + * The pageNumber array is variable in length, with pageCount elements, + * so the allocated size of the structure must reflect that. + * + * FBMEM items apply only to NV01_MEMORY_LIST_FBMEM and to + * NV01_MEMORY_LIST_OBJECT when the underlying object is + * FBMEM (must be zero for other cases) + * + * NV_MEMORY_LIST_ALLOCATION_PARAMS - Allocation params to create memory list + * through NvRmAlloc. + */ +#define NV_MEMORY_LIST_ALLOCATION_PARAMS_MESSAGE_ID (0x84a0U) + +typedef struct NV_MEMORY_LIST_ALLOCATION_PARAMS { + NvHandle hClient; /* client to which object belongs + * (may differ from client creating the mapping). + * May be NV01_NULL_OBJECT, in which case client + * handle is used */ + NvHandle hParent; /* device with which object is associated. + * Must be NV01_NULL_OBJECT if hClient is NV01_NULL_OBJECT. + * Must not be NV01_NULL_OBJECT if hClient is + * not NV01_NULL_OBJECT. */ + NvHandle hObject; /* object to which pages are relative + * (NV01_NULL_OBJECT for NV01_MEMORY_LIST_SYSTEM + * and NV01_MEMORY_LIST_FBMEM) */ + NvHandle hHwResClient; /* client associated with the backdoor vnc surface*/ + NvHandle hHwResDevice; /* device associated to the bacdoor vnc surface*/ + NvHandle hHwResHandle; /* handle to hardware resources allocated to + * backdoor vnc surface*/ + NvU32 pteAdjust; /* offset of data in first page */ + NvU32 reserved_0; /* reserved: must be 0 */ + NvU32 type; /* FBMEM: NVOS32_TYPE_* */ + NvU32 flags; /* FBMEM: NVOS32_ALLOC_FLAGS_* */ + NvU32 attr; /* FBMEM: NVOS32_ATTR_* */ + NvU32 attr2; /* FBMEM: NVOS32_ATTR2_* */ + NvU32 height; /* FBMEM: height in pixels */ + NvU32 width; /* FBMEM: width in pixels */ + NvU32 format; /* FBMEM: memory kind */ + NvU32 comprcovg; /* FBMEM: compression coverage */ + NvU32 zcullcovg; /* FBMEM: Z-cull coverage */ + NvU32 pageCount; /* count of elements in pageNumber array */ + NvU32 heapOwner; /* heap owner information from client */ + + NV_DECLARE_ALIGNED(NvU64 guestId, 8); + /* ID of the guest VM. e.g., domain ID in case of Xen */ + NV_DECLARE_ALIGNED(NvU64 rangeBegin, 8); + /* preferred VA range start address */ + NV_DECLARE_ALIGNED(NvU64 rangeEnd, 8); + /* preferred VA range end address */ + NvU32 pitch; + NvU32 ctagOffset; + NV_DECLARE_ALIGNED(NvU64 size, 8); + NV_DECLARE_ALIGNED(NvU64 align, 8); + NV_DECLARE_ALIGNED(NvP64 pageNumberList, 8); + NV_DECLARE_ALIGNED(NvU64 limit, 8); + NvU32 flagsOs02; +} NV_MEMORY_LIST_ALLOCATION_PARAMS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl84a0_deprecated.h b/userspace/sdks/nv570/nvidia/inc/class/cl84a0_deprecated.h new file mode 100644 index 0000000..f1e7f0c --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl84a0_deprecated.h @@ -0,0 +1,90 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl84a0_deprecated_h_ +#define _cl84a0_deprecated_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * List structure of NV01_MEMORY_LIST_* classes + * + * The pageNumber array is variable in length, with pageCount elements, + * so the allocated size of the structure must reflect that. + * + * FBMEM items apply only to NV01_MEMORY_LIST_FBMEM and to + * NV01_MEMORY_LIST_OBJECT when the underlying object is + * FBMEM (must be zero for other cases) + * + * Nv01MemoryList is deprecated. NV_MEMORY_LIST_ALLOCATION_PARAMS should be used + * instead. + */ +typedef struct Nv01MemoryListRec { + NvHandle hClient; /* client to which object belongs + * (may differ from client creating the mapping). + * May be NV01_NULL_OBJECT, in which case client + * handle is used */ + NvHandle hParent; /* device with which object is associated. + * Must be NV01_NULL_OBJECT if hClient is NV01_NULL_OBJECT. + * Must not be NV01_NULL_OBJECT if hClient is + * not NV01_NULL_OBJECT. */ + NvHandle hObject; /* object to which pages are relative + * (NV01_NULL_OBJECT for NV01_MEMORY_LIST_SYSTEM + * and NV01_MEMORY_LIST_FBMEM) */ + NvHandle hHwResClient;/* client associated with the backdoor vnc surface*/ + NvHandle hHwResDevice;/* device associated to the bacdoor vnc surface*/ + NvHandle hHwResHandle;/* handle to hardware resources allocated to + * backdoor vnc surface*/ + NvU32 pteAdjust; /* offset of data in first page */ + NvU32 type; /* FBMEM: NVOS32_TYPE_* */ + NvU32 flags; /* FBMEM: NVOS32_ALLOC_FLAGS_* */ + NvU32 attr; /* FBMEM: NVOS32_ATTR_* */ + NvU32 attr2; /* FBMEM: NVOS32_ATTR2_* */ + NvU32 height; /* FBMEM: height in pixels */ + NvU32 width; /* FBMEM: width in pixels */ + NvU32 format; /* FBMEM: memory kind */ + NvU32 comprcovg; /* FBMEM: compression coverage */ + NvU32 zcullcovg; /* FBMEM: Z-cull coverage */ + NvU32 pageCount; /* count of elements in pageNumber array */ + NvU32 heapOwner; /* heap owner information from client */ + NvU32 reserved_1; /* reserved: must be 0 */ + NvU64 NV_DECLARE_ALIGNED(guestId,8); + /* ID of the guest VM. e.g., domain ID in case of Xen */ + NvU64 NV_DECLARE_ALIGNED(rangeBegin,8); + /* preferred VA range start address */ + NvU64 NV_DECLARE_ALIGNED(rangeEnd,8); + /* preferred VA range end address */ + NvU32 pitch; + NvU32 ctagOffset; + NvU64 size; + NvU64 align; + NvU64 pageNumber[1]; /* variable length array of page numbers */ +} Nv01MemoryList; + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl84a0_deprecated_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl85b5sw.h b/userspace/sdks/nv570/nvidia/inc/class/cl85b5sw.h new file mode 100644 index 0000000..63e1160 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl85b5sw.h @@ -0,0 +1,38 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl85b5sw.finn +// + +#define NV85B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0x85b5U) + +typedef struct NV85B5_ALLOCATION_PARAMETERS { + NvU32 version; // set to 0 + NvU32 engineInstance; // CE instance +} NV85B5_ALLOCATION_PARAMETERS; diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl900e.h b/userspace/sdks/nv570/nvidia/inc/class/cl900e.h new file mode 100644 index 0000000..6684889 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl900e.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl900e_h_ +#define _cl900e_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define MPS_COMPUTE (0x0000900E) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl900e_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl9010.h b/userspace/sdks/nv570/nvidia/inc/class/cl9010.h new file mode 100644 index 0000000..722277b --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl9010.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9010.finn +// + +#include "class/cl9010_callback.h" + +#define NV9010_VBLANK_CALLBACK (0x9010U) /* finn: Evaluated from "NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9010U) + +typedef struct NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS { + NV_DECLARE_ALIGNED(NvP64 pProc, 8); // Routine to call at vblank time + // A function pointer of OSVBLANKCALLBACKPROC + NvV32 LogicalHead; // Logical Head + NV_DECLARE_ALIGNED(NvP64 pParm1, 8); // pParm1 + NV_DECLARE_ALIGNED(NvP64 pParm2, 8); // pParm2 +} NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl9010_callback.h b/userspace/sdks/nv570/nvidia/inc/class/cl9010_callback.h new file mode 100644 index 0000000..1945b68 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl9010_callback.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef SDK_CL9010_CALLBACK_H +#define SDK_CL9010_CALLBACK_H + +typedef void (*OSVBLANKCALLBACKPROC)(NvP64 pParm1, NvP64 pParm2); + +#endif // SDK_CL9010_CALLBACK_H diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl902d.h b/userspace/sdks/nv570/nvidia/inc/class/cl902d.h new file mode 100644 index 0000000..38bd5cf --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl902d.h @@ -0,0 +1,1092 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_fermi_twod_a_h_ +#define _cl_fermi_twod_a_h_ + +#define FERMI_TWOD_A 0x902D + +typedef volatile struct fermi_twod_a_struct { + NvU32 SetObject; + NvU32 Reserved_0x04[0x3F]; + NvU32 NoOperation; + NvU32 SetNotifyA; + NvU32 SetNotifyB; + NvU32 Notify; + NvU32 WaitForIdle; + NvU32 LoadMmeInstructionRamPointer; + NvU32 LoadMmeInstructionRam; + NvU32 LoadMmeStartAddressRamPointer; + NvU32 LoadMmeStartAddressRam; + NvU32 SetMmeShadowRamControl; + NvU32 Reserved_0x128[0x2]; + NvU32 SetGlobalRenderEnableA; + NvU32 SetGlobalRenderEnableB; + NvU32 SetGlobalRenderEnableC; + NvU32 SendGoIdle; + NvU32 PmTrigger; + NvU32 Reserved_0x144[0x3]; + NvU32 SetInstrumentationMethodHeader; + NvU32 SetInstrumentationMethodData; + NvU32 Reserved_0x158[0x25]; + NvU32 SetMmeSwitchState; + NvU32 Reserved_0x1F0[0x4]; + NvU32 SetDstFormat; + NvU32 SetDstMemoryLayout; + NvU32 SetDstBlockSize; + NvU32 SetDstDepth; + NvU32 SetDstLayer; + NvU32 SetDstPitch; + NvU32 SetDstWidth; + NvU32 SetDstHeight; + NvU32 SetDstOffsetUpper; + NvU32 SetDstOffsetLower; + NvU32 FlushAndInvalidateRopMiniCache; + NvU32 SetSpareNoop06; + NvU32 SetSrcFormat; + NvU32 SetSrcMemoryLayout; + NvU32 SetSrcBlockSize; + NvU32 SetSrcDepth; + NvU32 TwodInvalidateTextureDataCache; + NvU32 SetSrcPitch; + NvU32 SetSrcWidth; + NvU32 SetSrcHeight; + NvU32 SetSrcOffsetUpper; + NvU32 SetSrcOffsetLower; + NvU32 SetPixelsFromMemorySectorPromotion; + NvU32 SetSpareNoop12; + NvU32 SetNumProcessingClusters; + NvU32 SetRenderEnableA; + NvU32 SetRenderEnableB; + NvU32 SetRenderEnableC; + NvU32 SetSpareNoop08; + NvU32 SetSpareNoop01; + NvU32 SetSpareNoop11; + NvU32 SetSpareNoop07; + NvU32 SetClipX0; + NvU32 SetClipY0; + NvU32 SetClipWidth; + NvU32 SetClipHeight; + NvU32 SetClipEnable; + NvU32 SetColorKeyFormat; + NvU32 SetColorKey; + NvU32 SetColorKeyEnable; + NvU32 SetRop; + NvU32 SetBeta1; + NvU32 SetBeta4; + NvU32 SetOperation; + NvU32 SetPatternOffset; + NvU32 SetPatternSelect; + NvU32 SetDstColorRenderToZetaSurface; + NvU32 SetSpareNoop04; + NvU32 SetSpareNoop15; + NvU32 SetSpareNoop13; + NvU32 SetSpareNoop03; + NvU32 SetSpareNoop14; + NvU32 SetSpareNoop02; + NvU32 SetCompression; + NvU32 SetSpareNoop09; + NvU32 SetRenderEnableOverride; + NvU32 SetPixelsFromMemoryDirection; + NvU32 SetSpareNoop10; + NvU32 SetMonochromePatternColorFormat; + NvU32 SetMonochromePatternFormat; + NvU32 SetMonochromePatternColor0; + NvU32 SetMonochromePatternColor1; + NvU32 SetMonochromePattern0; + NvU32 SetMonochromePattern1; + NvU32 ColorPatternX8R8G8B8[0x40]; + NvU32 ColorPatternR5G6B5[0x20]; + NvU32 ColorPatternX1R5G5B5[0x20]; + NvU32 ColorPatternY8[0x10]; + NvU32 SetRenderSolidPrimColor0; + NvU32 SetRenderSolidPrimColor1; + NvU32 SetRenderSolidPrimColor2; + NvU32 SetRenderSolidPrimColor3; + NvU32 SetMmeMemAddressA; + NvU32 SetMmeMemAddressB; + NvU32 SetMmeDataRamAddress; + NvU32 MmeDmaRead; + NvU32 MmeDmaReadFifoed; + NvU32 MmeDmaWrite; + NvU32 MmeDmaReduction; + NvU32 MmeDmaSysmembar; + NvU32 MmeDmaSync; + NvU32 SetMmeDataFifoConfig; + NvU32 Reserved_0x578[0x2]; + NvU32 RenderSolidPrimMode; + NvU32 SetRenderSolidPrimColorFormat; + NvU32 SetRenderSolidPrimColor; + NvU32 SetRenderSolidLineTieBreakBits; + NvU32 Reserved_0x590[0x14]; + NvU32 RenderSolidPrimPointXY; + NvU32 Reserved_0x5E4[0x7]; + struct { + NvU32 SetX; + NvU32 Y; + } RenderSolidPrimPoint[0x40]; + NvU32 SetPixelsFromCpuDataType; + NvU32 SetPixelsFromCpuColorFormat; + NvU32 SetPixelsFromCpuIndexFormat; + NvU32 SetPixelsFromCpuMonoFormat; + NvU32 SetPixelsFromCpuWrap; + NvU32 SetPixelsFromCpuColor0; + NvU32 SetPixelsFromCpuColor1; + NvU32 SetPixelsFromCpuMonoOpacity; + NvU32 Reserved_0x820[0x6]; + NvU32 SetPixelsFromCpuSrcWidth; + NvU32 SetPixelsFromCpuSrcHeight; + NvU32 SetPixelsFromCpuDxDuFrac; + NvU32 SetPixelsFromCpuDxDuInt; + NvU32 SetPixelsFromCpuDyDvFrac; + NvU32 SetPixelsFromCpuDyDvInt; + NvU32 SetPixelsFromCpuDstX0Frac; + NvU32 SetPixelsFromCpuDstX0Int; + NvU32 SetPixelsFromCpuDstY0Frac; + NvU32 SetPixelsFromCpuDstY0Int; + NvU32 PixelsFromCpuData; + NvU32 Reserved_0x864[0x3]; + NvU32 SetBigEndianControl; + NvU32 Reserved_0x874[0x3]; + NvU32 SetPixelsFromMemoryBlockShape; + NvU32 SetPixelsFromMemoryCorralSize; + NvU32 SetPixelsFromMemorySafeOverlap; + NvU32 SetPixelsFromMemorySampleMode; + NvU32 Reserved_0x890[0x8]; + NvU32 SetPixelsFromMemoryDstX0; + NvU32 SetPixelsFromMemoryDstY0; + NvU32 SetPixelsFromMemoryDstWidth; + NvU32 SetPixelsFromMemoryDstHeight; + NvU32 SetPixelsFromMemoryDuDxFrac; + NvU32 SetPixelsFromMemoryDuDxInt; + NvU32 SetPixelsFromMemoryDvDyFrac; + NvU32 SetPixelsFromMemoryDvDyInt; + NvU32 SetPixelsFromMemorySrcX0Frac; + NvU32 SetPixelsFromMemorySrcX0Int; + NvU32 SetPixelsFromMemorySrcY0Frac; + NvU32 PixelsFromMemorySrcY0Int; + NvU32 SetFalcon00; + NvU32 SetFalcon01; + NvU32 SetFalcon02; + NvU32 SetFalcon03; + NvU32 SetFalcon04; + NvU32 SetFalcon05; + NvU32 SetFalcon06; + NvU32 SetFalcon07; + NvU32 SetFalcon08; + NvU32 SetFalcon09; + NvU32 SetFalcon10; + NvU32 SetFalcon11; + NvU32 SetFalcon12; + NvU32 SetFalcon13; + NvU32 SetFalcon14; + NvU32 SetFalcon15; + NvU32 SetFalcon16; + NvU32 SetFalcon17; + NvU32 SetFalcon18; + NvU32 SetFalcon19; + NvU32 SetFalcon20; + NvU32 SetFalcon21; + NvU32 SetFalcon22; + NvU32 SetFalcon23; + NvU32 SetFalcon24; + NvU32 SetFalcon25; + NvU32 SetFalcon26; + NvU32 SetFalcon27; + NvU32 SetFalcon28; + NvU32 SetFalcon29; + NvU32 SetFalcon30; + NvU32 SetFalcon31; + NvU32 Reserved_0x960[0x123]; + NvU32 MmeDmaWriteMethodBarrier; + NvU32 Reserved_0xDF0[0x984]; + NvU32 SetMmeShadowScratch[0x100]; + struct { + NvU32 Macro; + NvU32 Data; + } CallMme[0xE0]; +} fermi_twod_a_t; + + +#define NV902D_SET_OBJECT 0x0000 +#define NV902D_SET_OBJECT_CLASS_ID 15:0 +#define NV902D_SET_OBJECT_ENGINE_ID 20:16 + +#define NV902D_NO_OPERATION 0x0100 +#define NV902D_NO_OPERATION_V 31:0 + +#define NV902D_SET_NOTIFY_A 0x0104 +#define NV902D_SET_NOTIFY_A_ADDRESS_UPPER 24:0 + +#define NV902D_SET_NOTIFY_B 0x0108 +#define NV902D_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NV902D_NOTIFY 0x010c +#define NV902D_NOTIFY_TYPE 31:0 +#define NV902D_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NV902D_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NV902D_WAIT_FOR_IDLE 0x0110 +#define NV902D_WAIT_FOR_IDLE_V 31:0 + +#define NV902D_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NV902D_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NV902D_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NV902D_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NV902D_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NV902D_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NV902D_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NV902D_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NV902D_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NV902D_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NV902D_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NV902D_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NV902D_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NV902D_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NV902D_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV902D_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV902D_SEND_GO_IDLE 0x013c +#define NV902D_SEND_GO_IDLE_V 31:0 + +#define NV902D_PM_TRIGGER 0x0140 +#define NV902D_PM_TRIGGER_V 31:0 + +#define NV902D_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NV902D_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NV902D_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NV902D_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NV902D_SET_MME_SWITCH_STATE 0x01ec +#define NV902D_SET_MME_SWITCH_STATE_VALID 0:0 +#define NV902D_SET_MME_SWITCH_STATE_VALID_FALSE 0x00000000 +#define NV902D_SET_MME_SWITCH_STATE_VALID_TRUE 0x00000001 +#define NV902D_SET_MME_SWITCH_STATE_SAVE_MACRO 11:4 +#define NV902D_SET_MME_SWITCH_STATE_RESTORE_MACRO 19:12 + +#define NV902D_SET_DST_FORMAT 0x0200 +#define NV902D_SET_DST_FORMAT_V 7:0 +#define NV902D_SET_DST_FORMAT_V_A8R8G8B8 0x000000CF +#define NV902D_SET_DST_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NV902D_SET_DST_FORMAT_V_A2R10G10B10 0x000000DF +#define NV902D_SET_DST_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV902D_SET_DST_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NV902D_SET_DST_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV902D_SET_DST_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV902D_SET_DST_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NV902D_SET_DST_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV902D_SET_DST_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NV902D_SET_DST_FORMAT_V_R5G6B5 0x000000E8 +#define NV902D_SET_DST_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV902D_SET_DST_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV902D_SET_DST_FORMAT_V_Y8 0x000000F3 +#define NV902D_SET_DST_FORMAT_V_Y16 0x000000EE +#define NV902D_SET_DST_FORMAT_V_Y32 0x000000FF +#define NV902D_SET_DST_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV902D_SET_DST_FORMAT_V_O1R5G5B5 0x000000FC +#define NV902D_SET_DST_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV902D_SET_DST_FORMAT_V_O8R8G8B8 0x000000FE +#define NV902D_SET_DST_FORMAT_V_Y1_8X8 0x0000001C +#define NV902D_SET_DST_FORMAT_V_RF16 0x000000F2 +#define NV902D_SET_DST_FORMAT_V_RF32 0x000000E5 +#define NV902D_SET_DST_FORMAT_V_RF32_GF32 0x000000CB +#define NV902D_SET_DST_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NV902D_SET_DST_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NV902D_SET_DST_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NV902D_SET_DST_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NV902D_SET_DST_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NV902D_SET_DST_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NV902D_SET_DST_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NV902D_SET_DST_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NV902D_SET_DST_FORMAT_V_RF16_GF16 0x000000DE +#define NV902D_SET_DST_FORMAT_V_R16_G16 0x000000DA +#define NV902D_SET_DST_FORMAT_V_RN16_GN16 0x000000DB +#define NV902D_SET_DST_FORMAT_V_G8R8 0x000000EA +#define NV902D_SET_DST_FORMAT_V_GN8RN8 0x000000EB +#define NV902D_SET_DST_FORMAT_V_RN16 0x000000EF +#define NV902D_SET_DST_FORMAT_V_RN8 0x000000F4 +#define NV902D_SET_DST_FORMAT_V_A8 0x000000F7 + +#define NV902D_SET_DST_MEMORY_LAYOUT 0x0204 +#define NV902D_SET_DST_MEMORY_LAYOUT_V 0:0 +#define NV902D_SET_DST_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000 +#define NV902D_SET_DST_MEMORY_LAYOUT_V_PITCH 0x00000001 + +#define NV902D_SET_DST_BLOCK_SIZE 0x0208 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT 6:4 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH 10:8 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NV902D_SET_DST_DEPTH 0x020c +#define NV902D_SET_DST_DEPTH_V 31:0 + +#define NV902D_SET_DST_LAYER 0x0210 +#define NV902D_SET_DST_LAYER_V 31:0 + +#define NV902D_SET_DST_PITCH 0x0214 +#define NV902D_SET_DST_PITCH_V 31:0 + +#define NV902D_SET_DST_WIDTH 0x0218 +#define NV902D_SET_DST_WIDTH_V 31:0 + +#define NV902D_SET_DST_HEIGHT 0x021c +#define NV902D_SET_DST_HEIGHT_V 31:0 + +#define NV902D_SET_DST_OFFSET_UPPER 0x0220 +#define NV902D_SET_DST_OFFSET_UPPER_V 7:0 + +#define NV902D_SET_DST_OFFSET_LOWER 0x0224 +#define NV902D_SET_DST_OFFSET_LOWER_V 31:0 + +#define NV902D_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x0228 +#define NV902D_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NV902D_SET_SPARE_NOOP06 0x022c +#define NV902D_SET_SPARE_NOOP06_V 31:0 + +#define NV902D_SET_SRC_FORMAT 0x0230 +#define NV902D_SET_SRC_FORMAT_V 7:0 +#define NV902D_SET_SRC_FORMAT_V_A8R8G8B8 0x000000CF +#define NV902D_SET_SRC_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NV902D_SET_SRC_FORMAT_V_A2R10G10B10 0x000000DF +#define NV902D_SET_SRC_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV902D_SET_SRC_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NV902D_SET_SRC_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV902D_SET_SRC_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV902D_SET_SRC_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NV902D_SET_SRC_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV902D_SET_SRC_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NV902D_SET_SRC_FORMAT_V_R5G6B5 0x000000E8 +#define NV902D_SET_SRC_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV902D_SET_SRC_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV902D_SET_SRC_FORMAT_V_Y8 0x000000F3 +#define NV902D_SET_SRC_FORMAT_V_AY8 0x0000001D +#define NV902D_SET_SRC_FORMAT_V_Y16 0x000000EE +#define NV902D_SET_SRC_FORMAT_V_Y32 0x000000FF +#define NV902D_SET_SRC_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV902D_SET_SRC_FORMAT_V_O1R5G5B5 0x000000FC +#define NV902D_SET_SRC_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV902D_SET_SRC_FORMAT_V_O8R8G8B8 0x000000FE +#define NV902D_SET_SRC_FORMAT_V_Y1_8X8 0x0000001C +#define NV902D_SET_SRC_FORMAT_V_RF16 0x000000F2 +#define NV902D_SET_SRC_FORMAT_V_RF32 0x000000E5 +#define NV902D_SET_SRC_FORMAT_V_RF32_GF32 0x000000CB +#define NV902D_SET_SRC_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NV902D_SET_SRC_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NV902D_SET_SRC_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NV902D_SET_SRC_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NV902D_SET_SRC_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NV902D_SET_SRC_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NV902D_SET_SRC_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NV902D_SET_SRC_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NV902D_SET_SRC_FORMAT_V_RF16_GF16 0x000000DE +#define NV902D_SET_SRC_FORMAT_V_R16_G16 0x000000DA +#define NV902D_SET_SRC_FORMAT_V_RN16_GN16 0x000000DB +#define NV902D_SET_SRC_FORMAT_V_G8R8 0x000000EA +#define NV902D_SET_SRC_FORMAT_V_GN8RN8 0x000000EB +#define NV902D_SET_SRC_FORMAT_V_RN16 0x000000EF +#define NV902D_SET_SRC_FORMAT_V_RN8 0x000000F4 +#define NV902D_SET_SRC_FORMAT_V_A8 0x000000F7 + +#define NV902D_SET_SRC_MEMORY_LAYOUT 0x0234 +#define NV902D_SET_SRC_MEMORY_LAYOUT_V 0:0 +#define NV902D_SET_SRC_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000 +#define NV902D_SET_SRC_MEMORY_LAYOUT_V_PITCH 0x00000001 + +#define NV902D_SET_SRC_BLOCK_SIZE 0x0238 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT 6:4 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH 10:8 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NV902D_SET_SRC_DEPTH 0x023c +#define NV902D_SET_SRC_DEPTH_V 31:0 + +#define NV902D_TWOD_INVALIDATE_TEXTURE_DATA_CACHE 0x0240 +#define NV902D_TWOD_INVALIDATE_TEXTURE_DATA_CACHE_V 1:0 +#define NV902D_TWOD_INVALIDATE_TEXTURE_DATA_CACHE_V_L1_ONLY 0x00000000 +#define NV902D_TWOD_INVALIDATE_TEXTURE_DATA_CACHE_V_L2_ONLY 0x00000001 +#define NV902D_TWOD_INVALIDATE_TEXTURE_DATA_CACHE_V_L1_AND_L2 0x00000002 + +#define NV902D_SET_SRC_PITCH 0x0244 +#define NV902D_SET_SRC_PITCH_V 31:0 + +#define NV902D_SET_SRC_WIDTH 0x0248 +#define NV902D_SET_SRC_WIDTH_V 31:0 + +#define NV902D_SET_SRC_HEIGHT 0x024c +#define NV902D_SET_SRC_HEIGHT_V 31:0 + +#define NV902D_SET_SRC_OFFSET_UPPER 0x0250 +#define NV902D_SET_SRC_OFFSET_UPPER_V 7:0 + +#define NV902D_SET_SRC_OFFSET_LOWER 0x0254 +#define NV902D_SET_SRC_OFFSET_LOWER_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION 0x0258 +#define NV902D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V 1:0 +#define NV902D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V_NO_PROMOTION 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V_PROMOTE_TO_2_V 0x00000001 +#define NV902D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V_PROMOTE_TO_2_H 0x00000002 +#define NV902D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V_PROMOTE_TO_4 0x00000003 + +#define NV902D_SET_SPARE_NOOP12 0x025c +#define NV902D_SET_SPARE_NOOP12_V 31:0 + +#define NV902D_SET_NUM_PROCESSING_CLUSTERS 0x0260 +#define NV902D_SET_NUM_PROCESSING_CLUSTERS_V 0:0 +#define NV902D_SET_NUM_PROCESSING_CLUSTERS_V_ALL 0x00000000 +#define NV902D_SET_NUM_PROCESSING_CLUSTERS_V_ONE 0x00000001 + +#define NV902D_SET_RENDER_ENABLE_A 0x0264 +#define NV902D_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV902D_SET_RENDER_ENABLE_B 0x0268 +#define NV902D_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV902D_SET_RENDER_ENABLE_C 0x026c +#define NV902D_SET_RENDER_ENABLE_C_MODE 2:0 +#define NV902D_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV902D_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV902D_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV902D_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV902D_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV902D_SET_SPARE_NOOP08 0x0270 +#define NV902D_SET_SPARE_NOOP08_V 31:0 + +#define NV902D_SET_SPARE_NOOP01 0x0274 +#define NV902D_SET_SPARE_NOOP01_V 31:0 + +#define NV902D_SET_SPARE_NOOP11 0x0278 +#define NV902D_SET_SPARE_NOOP11_V 31:0 + +#define NV902D_SET_SPARE_NOOP07 0x027c +#define NV902D_SET_SPARE_NOOP07_V 31:0 + +#define NV902D_SET_CLIP_X0 0x0280 +#define NV902D_SET_CLIP_X0_V 31:0 + +#define NV902D_SET_CLIP_Y0 0x0284 +#define NV902D_SET_CLIP_Y0_V 31:0 + +#define NV902D_SET_CLIP_WIDTH 0x0288 +#define NV902D_SET_CLIP_WIDTH_V 31:0 + +#define NV902D_SET_CLIP_HEIGHT 0x028c +#define NV902D_SET_CLIP_HEIGHT_V 31:0 + +#define NV902D_SET_CLIP_ENABLE 0x0290 +#define NV902D_SET_CLIP_ENABLE_V 0:0 +#define NV902D_SET_CLIP_ENABLE_V_FALSE 0x00000000 +#define NV902D_SET_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NV902D_SET_COLOR_KEY_FORMAT 0x0294 +#define NV902D_SET_COLOR_KEY_FORMAT_V 2:0 +#define NV902D_SET_COLOR_KEY_FORMAT_V_A16R5G6B5 0x00000000 +#define NV902D_SET_COLOR_KEY_FORMAT_V_A1R5G5B5 0x00000001 +#define NV902D_SET_COLOR_KEY_FORMAT_V_A8R8G8B8 0x00000002 +#define NV902D_SET_COLOR_KEY_FORMAT_V_A2R10G10B10 0x00000003 +#define NV902D_SET_COLOR_KEY_FORMAT_V_Y8 0x00000004 +#define NV902D_SET_COLOR_KEY_FORMAT_V_Y16 0x00000005 +#define NV902D_SET_COLOR_KEY_FORMAT_V_Y32 0x00000006 + +#define NV902D_SET_COLOR_KEY 0x0298 +#define NV902D_SET_COLOR_KEY_V 31:0 + +#define NV902D_SET_COLOR_KEY_ENABLE 0x029c +#define NV902D_SET_COLOR_KEY_ENABLE_V 0:0 +#define NV902D_SET_COLOR_KEY_ENABLE_V_FALSE 0x00000000 +#define NV902D_SET_COLOR_KEY_ENABLE_V_TRUE 0x00000001 + +#define NV902D_SET_ROP 0x02a0 +#define NV902D_SET_ROP_V 7:0 + +#define NV902D_SET_BETA1 0x02a4 +#define NV902D_SET_BETA1_V 31:0 + +#define NV902D_SET_BETA4 0x02a8 +#define NV902D_SET_BETA4_B 7:0 +#define NV902D_SET_BETA4_G 15:8 +#define NV902D_SET_BETA4_R 23:16 +#define NV902D_SET_BETA4_A 31:24 + +#define NV902D_SET_OPERATION 0x02ac +#define NV902D_SET_OPERATION_V 2:0 +#define NV902D_SET_OPERATION_V_SRCCOPY_AND 0x00000000 +#define NV902D_SET_OPERATION_V_ROP_AND 0x00000001 +#define NV902D_SET_OPERATION_V_BLEND_AND 0x00000002 +#define NV902D_SET_OPERATION_V_SRCCOPY 0x00000003 +#define NV902D_SET_OPERATION_V_ROP 0x00000004 +#define NV902D_SET_OPERATION_V_SRCCOPY_PREMULT 0x00000005 +#define NV902D_SET_OPERATION_V_BLEND_PREMULT 0x00000006 + +#define NV902D_SET_PATTERN_OFFSET 0x02b0 +#define NV902D_SET_PATTERN_OFFSET_X 5:0 +#define NV902D_SET_PATTERN_OFFSET_Y 13:8 + +#define NV902D_SET_PATTERN_SELECT 0x02b4 +#define NV902D_SET_PATTERN_SELECT_V 1:0 +#define NV902D_SET_PATTERN_SELECT_V_MONOCHROME_8x8 0x00000000 +#define NV902D_SET_PATTERN_SELECT_V_MONOCHROME_64x1 0x00000001 +#define NV902D_SET_PATTERN_SELECT_V_MONOCHROME_1x64 0x00000002 +#define NV902D_SET_PATTERN_SELECT_V_COLOR 0x00000003 + +#define NV902D_SET_DST_COLOR_RENDER_TO_ZETA_SURFACE 0x02b8 +#define NV902D_SET_DST_COLOR_RENDER_TO_ZETA_SURFACE_V 0:0 +#define NV902D_SET_DST_COLOR_RENDER_TO_ZETA_SURFACE_V_FALSE 0x00000000 +#define NV902D_SET_DST_COLOR_RENDER_TO_ZETA_SURFACE_V_TRUE 0x00000001 + +#define NV902D_SET_SPARE_NOOP04 0x02bc +#define NV902D_SET_SPARE_NOOP04_V 31:0 + +#define NV902D_SET_SPARE_NOOP15 0x02c0 +#define NV902D_SET_SPARE_NOOP15_V 31:0 + +#define NV902D_SET_SPARE_NOOP13 0x02c4 +#define NV902D_SET_SPARE_NOOP13_V 31:0 + +#define NV902D_SET_SPARE_NOOP03 0x02c8 +#define NV902D_SET_SPARE_NOOP03_V 31:0 + +#define NV902D_SET_SPARE_NOOP14 0x02cc +#define NV902D_SET_SPARE_NOOP14_V 31:0 + +#define NV902D_SET_SPARE_NOOP02 0x02d0 +#define NV902D_SET_SPARE_NOOP02_V 31:0 + +#define NV902D_SET_COMPRESSION 0x02d4 +#define NV902D_SET_COMPRESSION_ENABLE 0:0 +#define NV902D_SET_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NV902D_SET_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NV902D_SET_SPARE_NOOP09 0x02d8 +#define NV902D_SET_SPARE_NOOP09_V 31:0 + +#define NV902D_SET_RENDER_ENABLE_OVERRIDE 0x02dc +#define NV902D_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NV902D_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NV902D_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NV902D_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION 0x02e0 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_HORIZONTAL 1:0 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_HORIZONTAL_HW_DECIDES 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_HORIZONTAL_LEFT_TO_RIGHT 0x00000001 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_HORIZONTAL_RIGHT_TO_LEFT 0x00000002 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_VERTICAL 5:4 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_VERTICAL_HW_DECIDES 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_VERTICAL_TOP_TO_BOTTOM 0x00000001 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_VERTICAL_BOTTOM_TO_TOP 0x00000002 + +#define NV902D_SET_SPARE_NOOP10 0x02e4 +#define NV902D_SET_SPARE_NOOP10_V 31:0 + +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT 0x02e8 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V 2:0 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8X8R5G6B5 0x00000000 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A1R5G5B5 0x00000001 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8R8G8B8 0x00000002 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8Y8 0x00000003 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8X8Y16 0x00000004 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_Y32 0x00000005 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_BYTE_EXPAND 0x00000006 + +#define NV902D_SET_MONOCHROME_PATTERN_FORMAT 0x02ec +#define NV902D_SET_MONOCHROME_PATTERN_FORMAT_V 0:0 +#define NV902D_SET_MONOCHROME_PATTERN_FORMAT_V_CGA6_M1 0x00000000 +#define NV902D_SET_MONOCHROME_PATTERN_FORMAT_V_LE_M1 0x00000001 + +#define NV902D_SET_MONOCHROME_PATTERN_COLOR0 0x02f0 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR0_V 31:0 + +#define NV902D_SET_MONOCHROME_PATTERN_COLOR1 0x02f4 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR1_V 31:0 + +#define NV902D_SET_MONOCHROME_PATTERN0 0x02f8 +#define NV902D_SET_MONOCHROME_PATTERN0_V 31:0 + +#define NV902D_SET_MONOCHROME_PATTERN1 0x02fc +#define NV902D_SET_MONOCHROME_PATTERN1_V 31:0 + +#define NV902D_COLOR_PATTERN_X8R8G8B8(i) (0x0300+(i)*4) +#define NV902D_COLOR_PATTERN_X8R8G8B8_B0 7:0 +#define NV902D_COLOR_PATTERN_X8R8G8B8_G0 15:8 +#define NV902D_COLOR_PATTERN_X8R8G8B8_R0 23:16 +#define NV902D_COLOR_PATTERN_X8R8G8B8_IGNORE0 31:24 + +#define NV902D_COLOR_PATTERN_R5G6B5(i) (0x0400+(i)*4) +#define NV902D_COLOR_PATTERN_R5G6B5_B0 4:0 +#define NV902D_COLOR_PATTERN_R5G6B5_G0 10:5 +#define NV902D_COLOR_PATTERN_R5G6B5_R0 15:11 +#define NV902D_COLOR_PATTERN_R5G6B5_B1 20:16 +#define NV902D_COLOR_PATTERN_R5G6B5_G1 26:21 +#define NV902D_COLOR_PATTERN_R5G6B5_R1 31:27 + +#define NV902D_COLOR_PATTERN_X1R5G5B5(i) (0x0480+(i)*4) +#define NV902D_COLOR_PATTERN_X1R5G5B5_B0 4:0 +#define NV902D_COLOR_PATTERN_X1R5G5B5_G0 9:5 +#define NV902D_COLOR_PATTERN_X1R5G5B5_R0 14:10 +#define NV902D_COLOR_PATTERN_X1R5G5B5_IGNORE0 15:15 +#define NV902D_COLOR_PATTERN_X1R5G5B5_B1 20:16 +#define NV902D_COLOR_PATTERN_X1R5G5B5_G1 25:21 +#define NV902D_COLOR_PATTERN_X1R5G5B5_R1 30:26 +#define NV902D_COLOR_PATTERN_X1R5G5B5_IGNORE1 31:31 + +#define NV902D_COLOR_PATTERN_Y8(i) (0x0500+(i)*4) +#define NV902D_COLOR_PATTERN_Y8_Y0 7:0 +#define NV902D_COLOR_PATTERN_Y8_Y1 15:8 +#define NV902D_COLOR_PATTERN_Y8_Y2 23:16 +#define NV902D_COLOR_PATTERN_Y8_Y3 31:24 + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR0 0x0540 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR0_V 31:0 + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR1 0x0544 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR1_V 31:0 + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR2 0x0548 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR2_V 31:0 + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR3 0x054c +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR3_V 31:0 + +#define NV902D_SET_MME_MEM_ADDRESS_A 0x0550 +#define NV902D_SET_MME_MEM_ADDRESS_A_UPPER 24:0 + +#define NV902D_SET_MME_MEM_ADDRESS_B 0x0554 +#define NV902D_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NV902D_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NV902D_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NV902D_MME_DMA_READ 0x055c +#define NV902D_MME_DMA_READ_LENGTH 31:0 + +#define NV902D_MME_DMA_READ_FIFOED 0x0560 +#define NV902D_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NV902D_MME_DMA_WRITE 0x0564 +#define NV902D_MME_DMA_WRITE_LENGTH 31:0 + +#define NV902D_MME_DMA_REDUCTION 0x0568 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NV902D_MME_DMA_SYSMEMBAR 0x056c +#define NV902D_MME_DMA_SYSMEMBAR_V 0:0 + +#define NV902D_MME_DMA_SYNC 0x0570 +#define NV902D_MME_DMA_SYNC_VALUE 31:0 + +#define NV902D_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NV902D_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NV902D_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NV902D_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NV902D_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NV902D_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NV902D_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NV902D_RENDER_SOLID_PRIM_MODE 0x0580 +#define NV902D_RENDER_SOLID_PRIM_MODE_V 2:0 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_POINTS 0x00000000 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_LINES 0x00000001 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_POLYLINE 0x00000002 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_TRIANGLES 0x00000003 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_RECTS 0x00000004 + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT 0x0584 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V 7:0 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_RF32_GF32 0x000000CB +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A8R8G8B8 0x000000CF +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A2R10G10B10 0x000000DF +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_R5G6B5 0x000000E8 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y8 0x000000F3 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y16 0x000000EE +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y32 0x000000FF +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_O1R5G5B5 0x000000FC +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_O8R8G8B8 0x000000FE + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR 0x0588 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_V 31:0 + +#define NV902D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS 0x058c +#define NV902D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS_XMAJ__XINC__YINC 0:0 +#define NV902D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS_XMAJ__XDEC__YINC 4:4 +#define NV902D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS_YMAJ__XINC__YINC 8:8 +#define NV902D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS_YMAJ__XDEC__YINC 12:12 + +#define NV902D_RENDER_SOLID_PRIM_POINT_X_Y 0x05e0 +#define NV902D_RENDER_SOLID_PRIM_POINT_X_Y_X 15:0 +#define NV902D_RENDER_SOLID_PRIM_POINT_X_Y_Y 31:16 + +#define NV902D_RENDER_SOLID_PRIM_POINT_SET_X(j) (0x0600+(j)*8) +#define NV902D_RENDER_SOLID_PRIM_POINT_SET_X_V 31:0 + +#define NV902D_RENDER_SOLID_PRIM_POINT_Y(j) (0x0604+(j)*8) +#define NV902D_RENDER_SOLID_PRIM_POINT_Y_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE 0x0800 +#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE_V 0:0 +#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE_V_COLOR 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE_V_INDEX 0x00000001 + +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT 0x0804 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V 7:0 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A8R8G8B8 0x000000CF +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A2R10G10B10 0x000000DF +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_R5G6B5 0x000000E8 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y8 0x000000F3 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y16 0x000000EE +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y32 0x000000FF +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_O1R5G5B5 0x000000FC +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_O8R8G8B8 0x000000FE + +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT 0x0808 +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V 1:0 +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I1 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I4 0x00000001 +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I8 0x00000002 + +#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT 0x080c +#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V 0:0 +#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V_CGA6_M1 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V_LE_M1 0x00000001 + +#define NV902D_SET_PIXELS_FROM_CPU_WRAP 0x0810 +#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V 1:0 +#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_PIXEL 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_BYTE 0x00000001 +#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_DWORD 0x00000002 + +#define NV902D_SET_PIXELS_FROM_CPU_COLOR0 0x0814 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR0_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_COLOR1 0x0818 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR1_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY 0x081c +#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V 0:0 +#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V_TRANSPARENT 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V_OPAQUE 0x00000001 + +#define NV902D_SET_PIXELS_FROM_CPU_SRC_WIDTH 0x0838 +#define NV902D_SET_PIXELS_FROM_CPU_SRC_WIDTH_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_SRC_HEIGHT 0x083c +#define NV902D_SET_PIXELS_FROM_CPU_SRC_HEIGHT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_FRAC 0x0840 +#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_INT 0x0844 +#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_FRAC 0x0848 +#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_INT 0x084c +#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_FRAC 0x0850 +#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_INT 0x0854 +#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_FRAC 0x0858 +#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_INT 0x085c +#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_INT_V 31:0 + +#define NV902D_PIXELS_FROM_CPU_DATA 0x0860 +#define NV902D_PIXELS_FROM_CPU_DATA_V 31:0 + +#define NV902D_SET_BIG_ENDIAN_CONTROL 0x0870 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X32_SWAP_1 0:0 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X32_SWAP_4 1:1 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X32_SWAP_8 2:2 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X32_SWAP_16 3:3 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X16_SWAP_1 4:4 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X16_SWAP_4 5:5 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X16_SWAP_8 6:6 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X16_SWAP_16 7:7 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X8_SWAP_1 8:8 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X8_SWAP_4 9:9 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X8_SWAP_8 10:10 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X8_SWAP_16 11:11 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_CGA6_SWAP_1 12:12 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_CGA6_SWAP_4 13:13 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_CGA6_SWAP_8 14:14 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_CGA6_SWAP_16 15:15 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_LE_SWAP_1 16:16 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_LE_SWAP_4 17:17 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_LE_SWAP_8 18:18 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_LE_SWAP_16 19:19 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I4_SWAP_1 20:20 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I4_SWAP_4 21:21 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I4_SWAP_8 22:22 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I4_SWAP_16 23:23 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I8_SWAP_1 24:24 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I8_SWAP_4 25:25 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I8_SWAP_8 26:26 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I8_SWAP_16 27:27 +#define NV902D_SET_BIG_ENDIAN_CONTROL_OVERRIDE 28:28 + +#define NV902D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE 0x0880 +#define NV902D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE_V 2:0 +#define NV902D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE_V_AUTO 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE_V_SHAPE_8X8 0x00000001 +#define NV902D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE_V_SHAPE_16X4 0x00000002 + +#define NV902D_SET_PIXELS_FROM_MEMORY_CORRAL_SIZE 0x0884 +#define NV902D_SET_PIXELS_FROM_MEMORY_CORRAL_SIZE_V 9:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP 0x0888 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V 0:0 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V_FALSE 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V_TRUE 0x00000001 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE 0x088c +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_ORIGIN 0:0 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_ORIGIN_CENTER 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_ORIGIN_CORNER 0x00000001 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_FILTER 4:4 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_FILTER_POINT 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_FILTER_BILINEAR 0x00000001 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_X0 0x08b0 +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_X0_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_Y0 0x08b4 +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_Y0_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_WIDTH 0x08b8 +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_WIDTH_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_HEIGHT 0x08bc +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_HEIGHT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_FRAC 0x08c0 +#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_INT 0x08c4 +#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_FRAC 0x08c8 +#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_INT 0x08cc +#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC 0x08d0 +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_INT 0x08d4 +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC 0x08d8 +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC_V 31:0 + +#define NV902D_PIXELS_FROM_MEMORY_SRC_Y0_INT 0x08dc +#define NV902D_PIXELS_FROM_MEMORY_SRC_Y0_INT_V 31:0 + +#define NV902D_SET_FALCON00 0x08e0 +#define NV902D_SET_FALCON00_V 31:0 + +#define NV902D_SET_FALCON01 0x08e4 +#define NV902D_SET_FALCON01_V 31:0 + +#define NV902D_SET_FALCON02 0x08e8 +#define NV902D_SET_FALCON02_V 31:0 + +#define NV902D_SET_FALCON03 0x08ec +#define NV902D_SET_FALCON03_V 31:0 + +#define NV902D_SET_FALCON04 0x08f0 +#define NV902D_SET_FALCON04_V 31:0 + +#define NV902D_SET_FALCON05 0x08f4 +#define NV902D_SET_FALCON05_V 31:0 + +#define NV902D_SET_FALCON06 0x08f8 +#define NV902D_SET_FALCON06_V 31:0 + +#define NV902D_SET_FALCON07 0x08fc +#define NV902D_SET_FALCON07_V 31:0 + +#define NV902D_SET_FALCON08 0x0900 +#define NV902D_SET_FALCON08_V 31:0 + +#define NV902D_SET_FALCON09 0x0904 +#define NV902D_SET_FALCON09_V 31:0 + +#define NV902D_SET_FALCON10 0x0908 +#define NV902D_SET_FALCON10_V 31:0 + +#define NV902D_SET_FALCON11 0x090c +#define NV902D_SET_FALCON11_V 31:0 + +#define NV902D_SET_FALCON12 0x0910 +#define NV902D_SET_FALCON12_V 31:0 + +#define NV902D_SET_FALCON13 0x0914 +#define NV902D_SET_FALCON13_V 31:0 + +#define NV902D_SET_FALCON14 0x0918 +#define NV902D_SET_FALCON14_V 31:0 + +#define NV902D_SET_FALCON15 0x091c +#define NV902D_SET_FALCON15_V 31:0 + +#define NV902D_SET_FALCON16 0x0920 +#define NV902D_SET_FALCON16_V 31:0 + +#define NV902D_SET_FALCON17 0x0924 +#define NV902D_SET_FALCON17_V 31:0 + +#define NV902D_SET_FALCON18 0x0928 +#define NV902D_SET_FALCON18_V 31:0 + +#define NV902D_SET_FALCON19 0x092c +#define NV902D_SET_FALCON19_V 31:0 + +#define NV902D_SET_FALCON20 0x0930 +#define NV902D_SET_FALCON20_V 31:0 + +#define NV902D_SET_FALCON21 0x0934 +#define NV902D_SET_FALCON21_V 31:0 + +#define NV902D_SET_FALCON22 0x0938 +#define NV902D_SET_FALCON22_V 31:0 + +#define NV902D_SET_FALCON23 0x093c +#define NV902D_SET_FALCON23_V 31:0 + +#define NV902D_SET_FALCON24 0x0940 +#define NV902D_SET_FALCON24_V 31:0 + +#define NV902D_SET_FALCON25 0x0944 +#define NV902D_SET_FALCON25_V 31:0 + +#define NV902D_SET_FALCON26 0x0948 +#define NV902D_SET_FALCON26_V 31:0 + +#define NV902D_SET_FALCON27 0x094c +#define NV902D_SET_FALCON27_V 31:0 + +#define NV902D_SET_FALCON28 0x0950 +#define NV902D_SET_FALCON28_V 31:0 + +#define NV902D_SET_FALCON29 0x0954 +#define NV902D_SET_FALCON29_V 31:0 + +#define NV902D_SET_FALCON30 0x0958 +#define NV902D_SET_FALCON30_V 31:0 + +#define NV902D_SET_FALCON31 0x095c +#define NV902D_SET_FALCON31_V 31:0 + +#define NV902D_MME_DMA_WRITE_METHOD_BARRIER 0x0dec +#define NV902D_MME_DMA_WRITE_METHOD_BARRIER_V 0:0 + +#define NV902D_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NV902D_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NV902D_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NV902D_CALL_MME_MACRO_V 31:0 + +#define NV902D_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NV902D_CALL_MME_DATA_V 31:0 + +#endif /* _cl_fermi_twod_a_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl9067.h b/userspace/sdks/nv570/nvidia/inc/class/cl9067.h new file mode 100644 index 0000000..5355f18 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl9067.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _cl9067_h_ +#define _cl9067_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define FERMI_CONTEXT_SHARE_A (0x00009067) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl9067_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl906f.h b/userspace/sdks/nv570/nvidia/inc/class/cl906f.h new file mode 100644 index 0000000..b20d8ff --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl906f.h @@ -0,0 +1,242 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl906f_h_ +#define _cl906f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class GF100_CHANNEL_GPFIFO */ +/* + * Documentation for GF100_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + */ +#define GF100_CHANNEL_GPFIFO (0x0000906F) + +/* pio method data structure */ +typedef volatile struct _cl906f_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv906fTypedef, GF100ChannelGPFifo; +#define NV906F_TYPEDEF GF100ChannelGPFifo +/* dma flow control data structure */ +typedef volatile struct _cl906f_tag1 { + NvU32 Ignored00[0x010]; /* 0000-0043*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 SetReferenceThreshold; /* set reference value threshold 0050-0053*/ + NvU32 Ignored01[0x001]; /* 0054-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x3dc]; +} Nv906fControl, GF100ControlGPFifo; +/* fields and values */ +#define NV906F_NUMBER_OF_SUBCHANNELS (8) +#define NV906F_SET_OBJECT (0x00000000) +#define NV906F_SET_OBJECT_NVCLASS 15:0 +#define NV906F_SET_OBJECT_ENGINE 20:16 +#define NV906F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NV906F_ILLEGAL (0x00000004) +#define NV906F_ILLEGAL_HANDLE 31:0 +#define NV906F_NOP (0x00000008) +#define NV906F_NOP_HANDLE 31:0 +#define NV906F_SEMAPHOREA (0x00000010) +#define NV906F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NV906F_SEMAPHOREB (0x00000014) +#define NV906F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NV906F_SEMAPHOREC (0x00000018) +#define NV906F_SEMAPHOREC_PAYLOAD 31:0 +#define NV906F_SEMAPHORED (0x0000001C) +#define NV906F_SEMAPHORED_OPERATION 3:0 +#define NV906F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NV906F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NV906F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NV906F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NV906F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NV906F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NV906F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NV906F_SEMAPHORED_RELEASE_WFI 20:20 +#define NV906F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NV906F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NV906F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NV906F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NV906F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NV906F_NON_STALL_INTERRUPT (0x00000020) +#define NV906F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NV906F_FB_FLUSH (0x00000024) +#define NV906F_FB_FLUSH_HANDLE 31:0 +#define NV906F_MEM_OP_A (0x00000028) +#define NV906F_MEM_OP_A_OPERAND_LOW 31:2 +#define NV906F_MEM_OP_A_TLB_INVALIDATE_ADDR 29:2 +#define NV906F_MEM_OP_A_TLB_INVALIDATE_TARGET 31:30 +#define NV906F_MEM_OP_A_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000 +#define NV906F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002 +#define NV906F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 +#define NV906F_MEM_OP_B (0x0000002c) +#define NV906F_MEM_OP_B_OPERAND_HIGH 7:0 +#define NV906F_MEM_OP_B_OPERATION 31:27 +#define NV906F_MEM_OP_B_OPERATION_SYSMEMBAR_FLUSH 0x00000005 +#define NV906F_MEM_OP_B_OPERATION_SOFT_FLUSH 0x00000006 +#define NV906F_MEM_OP_B_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NV906F_MEM_OP_B_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NV906F_MEM_OP_B_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +#define NV906F_MEM_OP_B_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NV906F_MEM_OP_B_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB 0:0 +#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ALL 0x00000001 +#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC 1:1 +#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NV906F_SET_REFERENCE (0x00000050) +#define NV906F_SET_REFERENCE_COUNT 31:0 +#define NV906F_CRC_CHECK (0x0000007c) +#define NV906F_CRC_CHECK_VALUE 31:0 +#define NV906F_YIELD (0x00000080) +#define NV906F_YIELD_OP 1:0 +#define NV906F_YIELD_OP_NOP 0x00000000 + +/* GPFIFO entry format */ +#define NV906F_GP_ENTRY__SIZE 8 +#define NV906F_GP_ENTRY0_FETCH 0:0 +#define NV906F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NV906F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NV906F_GP_ENTRY0_NO_CONTEXT_SWITCH 1:1 +#define NV906F_GP_ENTRY0_NO_CONTEXT_SWITCH_FALSE 0x00000000 +#define NV906F_GP_ENTRY0_NO_CONTEXT_SWITCH_TRUE 0x00000001 +#define NV906F_GP_ENTRY0_GET 31:2 +#define NV906F_GP_ENTRY0_OPERAND 31:0 +#define NV906F_GP_ENTRY1_GET_HI 7:0 +#define NV906F_GP_ENTRY1_PRIV 8:8 +#define NV906F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NV906F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NV906F_GP_ENTRY1_LEVEL 9:9 +#define NV906F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NV906F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NV906F_GP_ENTRY1_LENGTH 30:10 +#define NV906F_GP_ENTRY1_SYNC 31:31 +#define NV906F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NV906F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NV906F_GP_ENTRY1_OPCODE 7:0 +#define NV906F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NV906F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NV906F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NV906F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NV906F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NV906F_DMA_METHOD_ADDRESS 11:0 +#define NV906F_DMA_SUBDEVICE_MASK 15:4 +#define NV906F_DMA_METHOD_SUBCHANNEL 15:13 +#define NV906F_DMA_TERT_OP 17:16 +#define NV906F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NV906F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NV906F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NV906F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NV906F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NV906F_DMA_METHOD_COUNT_OLD 28:18 +#define NV906F_DMA_METHOD_COUNT 28:16 +#define NV906F_DMA_IMMD_DATA 28:16 +#define NV906F_DMA_SEC_OP 31:29 +#define NV906F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NV906F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NV906F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NV906F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NV906F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NV906F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NV906F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NV906F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NV906F_DMA_INCR_ADDRESS 11:0 +#define NV906F_DMA_INCR_SUBCHANNEL 15:13 +#define NV906F_DMA_INCR_COUNT 28:16 +#define NV906F_DMA_INCR_OPCODE 31:29 +#define NV906F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NV906F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NV906F_DMA_NONINCR_ADDRESS 11:0 +#define NV906F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NV906F_DMA_NONINCR_COUNT 28:16 +#define NV906F_DMA_NONINCR_OPCODE 31:29 +#define NV906F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NV906F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NV906F_DMA_ONEINCR_ADDRESS 11:0 +#define NV906F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NV906F_DMA_ONEINCR_COUNT 28:16 +#define NV906F_DMA_ONEINCR_OPCODE 31:29 +#define NV906F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NV906F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NV906F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NV906F_DMA_IMMD_ADDRESS 11:0 +#define NV906F_DMA_IMMD_SUBCHANNEL 15:13 +#define NV906F_DMA_IMMD_DATA 28:16 +#define NV906F_DMA_IMMD_OPCODE 31:29 +#define NV906F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NV906F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NV906F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NV906F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NV906F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NV906F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NV906F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NV906F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NV906F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NV906F_DMA_ENDSEG_OPCODE 31:29 +#define NV906F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NV906F_DMA_ADDRESS 12:2 +#define NV906F_DMA_SUBCH 15:13 +#define NV906F_DMA_OPCODE3 17:16 +#define NV906F_DMA_OPCODE3_NONE (0x00000000) +#define NV906F_DMA_COUNT 28:18 +#define NV906F_DMA_OPCODE 31:29 +#define NV906F_DMA_OPCODE_METHOD (0x00000000) +#define NV906F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NV906F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl906f_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl906fsw.h b/userspace/sdks/nv570/nvidia/inc/class/cl906fsw.h new file mode 100644 index 0000000..465a91a --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl906fsw.h @@ -0,0 +1,42 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl906f_sw_h_ +#define _cl906f_sw_h_ + +/* NvNotification[] elements */ +#define NV906F_NOTIFIERS_RC (0) +#define NV906F_NOTIFIERS_REFCNT (1) +#define NV906F_NOTIFIERS_NONSTALL (2) +#define NV906F_NOTIFIERS_EVENTBUFFER (3) +#define NV906F_NOTIFIERS_IDLECHANNEL (4) +#define NV906F_NOTIFIERS_ENDCTX (5) +#define NV906F_NOTIFIERS_SW (6) +#define NV906F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NV906F_NOTIFIERS_MAXCOUNT (8) + +/* NvNotification[] fields and values */ +#define NV906f_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NV906f_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _cl906f_sw_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl9072.h b/userspace/sdks/nv570/nvidia/inc/class/cl9072.h new file mode 100644 index 0000000..61e134a --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl9072.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9072.finn +// + +#include "cl9072_notification.h" + +#define GF100_DISP_SW (0x9072U) /* finn: Evaluated from "NV9072_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV9072_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9072U) + +typedef struct NV9072_ALLOCATION_PARAMETERS { + NvU32 logicalHeadId; + /* + * 0 implies use Head argument only (i.e. whatever is currently setup on this head) + */ + NvU32 displayMask; + NvU32 caps; +} NV9072_ALLOCATION_PARAMETERS; diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl9072_notification.h b/userspace/sdks/nv570/nvidia/inc/class/cl9072_notification.h new file mode 100644 index 0000000..21b48f8 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl9072_notification.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl9072_notification_h_ +#define _cl9072_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV9072_NOTIFIERS_NOTIFY_ON_VBLANK (9) +#define NV9072_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl9072_notification_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl9074.h b/userspace/sdks/nv570/nvidia/inc/class/cl9074.h new file mode 100644 index 0000000..60436ba --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl9074.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl9074_h_ +#define _cl9074_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define GF100_TIMED_SEMAPHORE_SW (0x00009074) + +/* NvNotification[] fields and values */ +#define NV9074_NOTIFICATION_STATUS_PENDING (0x8000) +#define NV9074_NOTIFICATION_STATUS_DONE_FLUSHED (0x0001) +#define NV9074_NOTIFICATION_STATUS_DONE (0x0000) + +#define NV9074_SET_NOTIFIER_HI_V 7:0 + +#define NV9074_SET_SEMAPHORE_HI_V 7:0 + +#define NV9074_SCHEDULE_SEMAPHORE_RELEASE_NOTIFY 1:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl9074_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl907dswspare.h b/userspace/sdks/nv570/nvidia/inc/class/cl907dswspare.h new file mode 100644 index 0000000..ee9ddaa --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl907dswspare.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl907d_sw_spare_h_ +#define _cl907d_sw_spare_h_ + +/* This file is *not* auto-generated. */ + +#define NV907D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF 1:0 +#define NV907D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF_NO_PREF (0x00000000) +#define NV907D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF_GSYNC (0x00000001) + +#define NV907D_PIOR_SET_SW_SPARE_A_CODE_FOR_LOCK_SIGNAL_PROPAGATION_ONLY 1:0 +#define NV907D_PIOR_SET_SW_SPARE_A_CODE_FOR_LOCK_SIGNAL_PROPAGATION_ONLY_FALSE (0x00000000) +#define NV907D_PIOR_SET_SW_SPARE_A_CODE_FOR_LOCK_SIGNAL_PROPAGATION_ONLY_TRUE (0x00000001) + +#endif // _cl907d_sw_spare_h_ + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl9096.h b/userspace/sdks/nv570/nvidia/inc/class/cl9096.h new file mode 100644 index 0000000..559216d --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl9096.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl9096_h_ +#define _cl9096_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define GF100_ZBC_CLEAR (0x00009096) +#define NV9096_TYPEDEF GF100ZBCClear + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl9096_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl9097.h b/userspace/sdks/nv570/nvidia/inc/class/cl9097.h new file mode 100644 index 0000000..8bc7792 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl9097.h @@ -0,0 +1,3815 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_fermi_a_h_ +#define _cl_fermi_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl fermi_a */ + +#include "nvtypes.h" + +#define FERMI_A 0x9097 + +#define NV9097_SET_OBJECT 0x0000 +#define NV9097_SET_OBJECT_CLASS_ID 15:0 +#define NV9097_SET_OBJECT_ENGINE_ID 20:16 + +#define NV9097_NO_OPERATION 0x0100 +#define NV9097_NO_OPERATION_V 31:0 + +#define NV9097_SET_NOTIFY_A 0x0104 +#define NV9097_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NV9097_SET_NOTIFY_B 0x0108 +#define NV9097_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NV9097_NOTIFY 0x010c +#define NV9097_NOTIFY_TYPE 31:0 +#define NV9097_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NV9097_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NV9097_WAIT_FOR_IDLE 0x0110 +#define NV9097_WAIT_FOR_IDLE_V 31:0 + +#define NV9097_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NV9097_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NV9097_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NV9097_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NV9097_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NV9097_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NV9097_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NV9097_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NV9097_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NV9097_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NV9097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NV9097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NV9097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NV9097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NV9097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NV9097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NV9097_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NV9097_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NV9097_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV9097_SEND_GO_IDLE 0x013c +#define NV9097_SEND_GO_IDLE_V 31:0 + +#define NV9097_PM_TRIGGER 0x0140 +#define NV9097_PM_TRIGGER_V 31:0 + +#define NV9097_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NV9097_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NV9097_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NV9097_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NV9097_RUN_DS_NOW 0x0200 +#define NV9097_RUN_DS_NOW_V 31:0 + +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NV9097_SET_RASTER_PIPE_SYNC_CONTROL 0x0208 +#define NV9097_SET_RASTER_PIPE_SYNC_CONTROL_PRIM_AREA_THRESHOLD 21:0 +#define NV9097_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE 24:24 +#define NV9097_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE_FALSE 0x00000000 +#define NV9097_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NV9097_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NV9097_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_API_MANDATED_EARLY_Z 0x0210 +#define NV9097_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NV9097_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NV9097_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_GS_DM_FIFO 0x0214 +#define NV9097_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NV9097_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NV9097_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NV9097_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NV9097_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NV9097_INVALIDATE_SHADER_CACHES 0x021c +#define NV9097_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NV9097_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NV9097_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NV9097_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NV9097_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NV9097_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NV9097_INVALIDATE_SHADER_CACHES_UNIFORM 8:8 +#define NV9097_INVALIDATE_SHADER_CACHES_UNIFORM_FALSE 0x00000000 +#define NV9097_INVALIDATE_SHADER_CACHES_UNIFORM_TRUE 0x00000001 +#define NV9097_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NV9097_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NV9097_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NV9097_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NV9097_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NV9097_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NV9097_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NV9097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NV9097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NV9097_SET_VAB_VERTEX3F(i) (0x0220+(i)*4) +#define NV9097_SET_VAB_VERTEX3F_V 31:0 + +#define NV9097_SET_VAB_VERTEX4F(i) (0x0230+(i)*4) +#define NV9097_SET_VAB_VERTEX4F_V 31:0 + +#define NV9097_SET_VAB_NORMAL3F(i) (0x0240+(i)*4) +#define NV9097_SET_VAB_NORMAL3F_V 31:0 + +#define NV9097_SET_VAB_COLOR3F(i) (0x0250+(i)*4) +#define NV9097_SET_VAB_COLOR3F_V 31:0 + +#define NV9097_SET_VAB_COLOR4F(i) (0x0260+(i)*4) +#define NV9097_SET_VAB_COLOR4F_V 31:0 + +#define NV9097_SET_VAB_COLOR4UB(i) (0x0270+(i)*4) +#define NV9097_SET_VAB_COLOR4UB_V 31:0 + +#define NV9097_SET_VAB_TEX_COORD1F(i) (0x0280+(i)*4) +#define NV9097_SET_VAB_TEX_COORD1F_V 31:0 + +#define NV9097_SET_VAB_TEX_COORD2F(i) (0x0290+(i)*4) +#define NV9097_SET_VAB_TEX_COORD2F_V 31:0 + +#define NV9097_SET_VAB_TEX_COORD3F(i) (0x02a0+(i)*4) +#define NV9097_SET_VAB_TEX_COORD3F_V 31:0 + +#define NV9097_SET_VAB_TEX_COORD4F(i) (0x02b0+(i)*4) +#define NV9097_SET_VAB_TEX_COORD4F_V 31:0 + +#define NV9097_SET_GA_TO_VA_MAPPING_MODE 0x02c4 +#define NV9097_SET_GA_TO_VA_MAPPING_MODE_V 0:0 +#define NV9097_SET_GA_TO_VA_MAPPING_MODE_V_DISABLE 0x00000000 +#define NV9097_SET_GA_TO_VA_MAPPING_MODE_V_ENABLE 0x00000001 + +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY 0x02c8 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_VIRTUAL_ADDRESS_UPPER 7:0 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_GENERIC_ADDRESS_UPPER 23:16 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE 30:30 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_FALSE 0x00000000 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_TRUE 0x00000001 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE 31:31 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_FALSE 0x00000000 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_TASK_CIRCULAR_BUFFER_THROTTLE 0x02cc +#define NV9097_SET_TASK_CIRCULAR_BUFFER_THROTTLE_TASK_COUNT 21:0 + +#define NV9097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NV9097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NV9097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NV9097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NV9097_SET_RASTER_BOUNDING_BOX 0x02ec +#define NV9097_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NV9097_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NV9097_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NV9097_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NV9097_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NV9097_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NV9097_DRAW_ZERO_INDEX 0x0304 +#define NV9097_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NV9097_SET_L1_CONFIGURATION 0x0308 +#define NV9097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NV9097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NV9097_SET_RENDER_ENABLE_CONTROL 0x030c +#define NV9097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NV9097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NV9097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NV9097_X_X_X_SET_CT_ENABLE 0x0310 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET0 0:0 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET0_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET0_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET1 1:1 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET1_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET1_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET2 2:2 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET2_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET2_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET3 3:3 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET3_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET3_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET4 4:4 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET4_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET4_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET5 5:5 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET5_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET5_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET6 6:6 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET6_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET6_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET7 7:7 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET7_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET7_TRUE 0x00000001 + +#define NV9097_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NV9097_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NV9097_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SNAP_GRID_LINE 0x0318 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NV9097_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NV9097_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NV9097_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NV9097_SET_SNAP_GRID_NON_LINE 0x031c +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NV9097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NV9097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NV9097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NV9097_SET_TESSELLATION_PARAMETERS 0x0320 +#define NV9097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NV9097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NV9097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NV9097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NV9097_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NV9097_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NV9097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NV9097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NV9097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NV9097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NV9097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NV9097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NV9097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NV9097_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NV9097_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NV9097_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NV9097_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NV9097_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NV9097_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NV9097_SET_TESSELLATION_LOD_V1 0x0330 +#define NV9097_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NV9097_SET_TG_LOD_INTERIOR_U 0x0334 +#define NV9097_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NV9097_SET_TG_LOD_INTERIOR_V 0x0338 +#define NV9097_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NV9097_RESERVED_TG07 0x033c +#define NV9097_RESERVED_TG07_V 0:0 + +#define NV9097_RESERVED_TG08 0x0340 +#define NV9097_RESERVED_TG08_V 0:0 + +#define NV9097_RESERVED_TG09 0x0344 +#define NV9097_RESERVED_TG09_V 0:0 + +#define NV9097_RESERVED_TG10 0x0348 +#define NV9097_RESERVED_TG10_V 0:0 + +#define NV9097_RESERVED_TG11 0x034c +#define NV9097_RESERVED_TG11_V 0:0 + +#define NV9097_RESERVED_TG12 0x0350 +#define NV9097_RESERVED_TG12_V 0:0 + +#define NV9097_RESERVED_TG13 0x0354 +#define NV9097_RESERVED_TG13_V 0:0 + +#define NV9097_RESERVED_TG14 0x0358 +#define NV9097_RESERVED_TG14_V 0:0 + +#define NV9097_RESERVED_TG15 0x035c +#define NV9097_RESERVED_TG15_V 0:0 + +#define NV9097_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NV9097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NV9097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NV9097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NV9097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NV9097_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NV9097_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NV9097_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NV9097_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NV9097_SET_RASTER_ENABLE 0x037c +#define NV9097_SET_RASTER_ENABLE_V 0:0 +#define NV9097_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NV9097_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NV9097_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NV9097_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NV9097_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NV9097_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NV9097_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NV9097_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NV9097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NV9097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NV9097_SET_VAB_DATA_TYPELESS(i) (0x0400+(i)*4) +#define NV9097_SET_VAB_DATA_TYPELESS_V 31:0 + +#define NV9097_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NV9097_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NV9097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NV9097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NV9097_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NV9097_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NV9097_SET_RASTER_INPUT 0x0740 +#define NV9097_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NV9097_SET_STREAM_OUTPUT 0x0744 +#define NV9097_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NV9097_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NV9097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NV9097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_ALPHA_FRACTION 0x074c +#define NV9097_SET_ALPHA_FRACTION_V 7:0 + +#define NV9097_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NV9097_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NV9097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NV9097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NV9097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 + +#define NV9097_SET_MAX_TI_WARPS_PER_BATCH 0x075c +#define NV9097_SET_MAX_TI_WARPS_PER_BATCH_V 5:0 + +#define NV9097_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NV9097_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NV9097_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NV9097_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NV9097_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NV9097_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NV9097_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NV9097_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NV9097_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NV9097_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NV9097_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NV9097_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NV9097_SET_VAB_VERTEX2F(i) (0x07b0+(i)*4) +#define NV9097_SET_VAB_VERTEX2F_V 31:0 + +#define NV9097_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NV9097_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NV9097_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NV9097_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NV9097_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NV9097_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NV9097_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NV9097_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NV9097_SET_CULL_BEFORE_FETCH 0x07dc +#define NV9097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NV9097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NV9097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NV9097_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NV9097_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NV9097_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NV9097_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NV9097_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NV9097_SET_ZCULL_STORAGE_A 0x07e8 +#define NV9097_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NV9097_SET_ZCULL_STORAGE_B 0x07ec +#define NV9097_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NV9097_SET_ZCULL_STORAGE_C 0x07f0 +#define NV9097_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NV9097_SET_ZCULL_STORAGE_D 0x07f4 +#define NV9097_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NV9097_SET_ZT_READ_ONLY 0x07f8 +#define NV9097_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NV9097_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NV9097_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NV9097_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NV9097_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NV9097_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NV9097_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NV9097_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NV9097_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NV9097_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NV9097_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NV9097_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NV9097_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NV9097_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NV9097_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NV9097_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NV9097_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NV9097_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NV9097_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV9097_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NV9097_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV9097_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 + +#define NV9097_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NV9097_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NV9097_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NV9097_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NV9097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NV9097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NV9097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NV9097_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NV9097_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NV9097_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NV9097_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NV9097_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NV9097_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NV9097_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NV9097_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NV9097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NV9097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NV9097_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NV9097_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NV9097_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NV9097_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NV9097_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NV9097_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NV9097_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NV9097_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NV9097_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NV9097_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NV9097_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NV9097_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NV9097_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NV9097_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NV9097_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NV9097_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NV9097_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NV9097_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NV9097_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NV9097_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NV9097_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NV9097_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NV9097_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NV9097_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NV9097_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NV9097_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NV9097_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NV9097_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NV9097_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NV9097_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NV9097_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NV9097_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NV9097_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NV9097_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NV9097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NV9097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NV9097_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NV9097_SET_STATISTICS_COUNTER 0x0d68 +#define NV9097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NV9097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NV9097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NV9097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NV9097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NV9097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NV9097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NV9097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NV9097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NV9097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NV9097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NV9097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NV9097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NV9097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NV9097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NV9097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NV9097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NV9097_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NV9097_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NV9097_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NV9097_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NV9097_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NV9097_SET_VERTEX_ARRAY_START 0x0d74 +#define NV9097_SET_VERTEX_ARRAY_START_V 31:0 + +#define NV9097_DRAW_VERTEX_ARRAY 0x0d78 +#define NV9097_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NV9097_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NV9097_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NV9097_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NV9097_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NV9097_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NV9097_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NV9097_SET_Z_CLEAR_VALUE 0x0d90 +#define NV9097_SET_Z_CLEAR_VALUE_V 31:0 + +#define NV9097_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NV9097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NV9097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NV9097_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NV9097_SET_FRONT_POLYGON_MODE 0x0dac +#define NV9097_SET_FRONT_POLYGON_MODE_V 31:0 +#define NV9097_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NV9097_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NV9097_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NV9097_SET_BACK_POLYGON_MODE 0x0db0 +#define NV9097_SET_BACK_POLYGON_MODE_V 31:0 +#define NV9097_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NV9097_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NV9097_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NV9097_SET_POLY_SMOOTH 0x0db4 +#define NV9097_SET_POLY_SMOOTH_ENABLE 0:0 +#define NV9097_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NV9097_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_ZT_MARK 0x0db8 +#define NV9097_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NV9097_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NV9097_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NV9097_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NV9097_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NV9097_SET_POLY_OFFSET_POINT 0x0dc0 +#define NV9097_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NV9097_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_POLY_OFFSET_LINE 0x0dc4 +#define NV9097_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NV9097_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_POLY_OFFSET_FILL 0x0dc8 +#define NV9097_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NV9097_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NV9097_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_PATCH 0x0dcc +#define NV9097_SET_PATCH_SIZE 7:0 + +#define NV9097_SET_ZCULL_CRITERION 0x0dd8 +#define NV9097_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NV9097_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NV9097_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NV9097_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NV9097_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NV9097_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NV9097_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NV9097_SET_ZCULL_CRITERION_SREF 23:16 +#define NV9097_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NV9097_X_X_X_SET_DA_ATTRIBUTE_CACHE_LINE 0x0ddc +#define NV9097_X_X_X_SET_DA_ATTRIBUTE_CACHE_LINE_V 1:0 +#define NV9097_X_X_X_SET_DA_ATTRIBUTE_CACHE_LINE_V_SIZE128 0x00000000 +#define NV9097_X_X_X_SET_DA_ATTRIBUTE_CACHE_LINE_V_SIZE64 0x00000001 +#define NV9097_X_X_X_SET_DA_ATTRIBUTE_CACHE_LINE_V_SIZE32 0x00000002 + +#define NV9097_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NV9097_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NV9097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NV9097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NV9097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE 0x0dec +#define NV9097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE 0:0 +#define NV9097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE_TRUE 0x00000001 + +#define NV9097_X_X_X_SET_REDUCE_COLOR 0x0df4 +#define NV9097_X_X_X_SET_REDUCE_COLOR_U8_THRESHOLD 7:0 +#define NV9097_X_X_X_SET_REDUCE_COLOR_FP16_THRESHOLD 23:8 + +#define NV9097_SET_WINDOW_OFFSET_X 0x0df8 +#define NV9097_SET_WINDOW_OFFSET_X_V 16:0 + +#define NV9097_SET_WINDOW_OFFSET_Y 0x0dfc +#define NV9097_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NV9097_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NV9097_SET_SCISSOR_ENABLE_V 0:0 +#define NV9097_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NV9097_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NV9097_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NV9097_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NV9097_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NV9097_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NV9097_SET_VAB_NORMAL3S(i) (0x0f00+(i)*4) +#define NV9097_SET_VAB_NORMAL3S_V 31:0 + +#define NV9097_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NV9097_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NV9097_SET_BACK_STENCIL_MASK 0x0f58 +#define NV9097_SET_BACK_STENCIL_MASK_V 7:0 + +#define NV9097_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NV9097_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NV9097_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NV9097_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NV9097_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NV9097_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NV9097_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NV9097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NV9097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NV9097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NV9097_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NV9097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NV9097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NV9097_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NV9097_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NV9097_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NV9097_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NV9097_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NV9097_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NV9097_SET_CT_MRT_ENABLE 0x0fac +#define NV9097_SET_CT_MRT_ENABLE_V 0:0 +#define NV9097_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NV9097_SET_NONMULTISAMPLED_Z_V 0:0 +#define NV9097_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NV9097_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NV9097_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NV9097_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NV9097_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NV9097_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NV9097_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NV9097_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NV9097_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NV9097_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NV9097_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NV9097_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NV9097_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_BLEND_OPT_CONTROL 0x0fdc +#define NV9097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NV9097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NV9097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NV9097_SET_ZT_A 0x0fe0 +#define NV9097_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_ZT_B 0x0fe4 +#define NV9097_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_ZT_FORMAT 0x0fe8 +#define NV9097_SET_ZT_FORMAT_V 4:0 +#define NV9097_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NV9097_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NV9097_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NV9097_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NV9097_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NV9097_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NV9097_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NV9097_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NV9097_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NV9097_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NV9097_SET_ZT_BLOCK_SIZE 0x0fec +#define NV9097_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NV9097_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV9097_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NV9097_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NV9097_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NV9097_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NV9097_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NV9097_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NV9097_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NV9097_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NV9097_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NV9097_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NV9097_SET_FORCE_ONE_TEXTURE_UNIT 0x1004 +#define NV9097_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE 0:0 +#define NV9097_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NV9097_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NV9097_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NV9097_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NV9097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NV9097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NV9097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NV9097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NV9097_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NV9097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NV9097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NV9097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NV9097_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NV9097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NV9097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SPARE_NOOP00 0x1040 +#define NV9097_SET_SPARE_NOOP00_V 31:0 + +#define NV9097_SET_SPARE_NOOP01 0x1044 +#define NV9097_SET_SPARE_NOOP01_V 31:0 + +#define NV9097_SET_SPARE_NOOP02 0x1048 +#define NV9097_SET_SPARE_NOOP02_V 31:0 + +#define NV9097_SET_SPARE_NOOP03 0x104c +#define NV9097_SET_SPARE_NOOP03_V 31:0 + +#define NV9097_SET_SPARE_NOOP04 0x1050 +#define NV9097_SET_SPARE_NOOP04_V 31:0 + +#define NV9097_SET_SPARE_NOOP05 0x1054 +#define NV9097_SET_SPARE_NOOP05_V 31:0 + +#define NV9097_SET_SPARE_NOOP06 0x1058 +#define NV9097_SET_SPARE_NOOP06_V 31:0 + +#define NV9097_SET_SPARE_NOOP07 0x105c +#define NV9097_SET_SPARE_NOOP07_V 31:0 + +#define NV9097_SET_SPARE_NOOP08 0x1060 +#define NV9097_SET_SPARE_NOOP08_V 31:0 + +#define NV9097_SET_SPARE_NOOP09 0x1064 +#define NV9097_SET_SPARE_NOOP09_V 31:0 + +#define NV9097_SET_SPARE_NOOP10 0x1068 +#define NV9097_SET_SPARE_NOOP10_V 31:0 + +#define NV9097_SET_SPARE_NOOP11 0x106c +#define NV9097_SET_SPARE_NOOP11_V 31:0 + +#define NV9097_SET_SPARE_NOOP12 0x1070 +#define NV9097_SET_SPARE_NOOP12_V 31:0 + +#define NV9097_SET_SPARE_NOOP13 0x1074 +#define NV9097_SET_SPARE_NOOP13_V 31:0 + +#define NV9097_SET_SPARE_NOOP14 0x1078 +#define NV9097_SET_SPARE_NOOP14_V 31:0 + +#define NV9097_SET_SPARE_NOOP15 0x107c +#define NV9097_SET_SPARE_NOOP15_V 31:0 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NV9097_UNBIND_ALL 0x10f4 +#define NV9097_UNBIND_ALL_TEXTURE_HEADERS 0:0 +#define NV9097_UNBIND_ALL_TEXTURE_HEADERS_FALSE 0x00000000 +#define NV9097_UNBIND_ALL_TEXTURE_HEADERS_TRUE 0x00000001 +#define NV9097_UNBIND_ALL_TEXTURE_SAMPLERS 4:4 +#define NV9097_UNBIND_ALL_TEXTURE_SAMPLERS_FALSE 0x00000000 +#define NV9097_UNBIND_ALL_TEXTURE_SAMPLERS_TRUE 0x00000001 +#define NV9097_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NV9097_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NV9097_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NV9097_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NV9097_NO_OPERATION_DATA_HI 0x110c +#define NV9097_NO_OPERATION_DATA_HI_V 31:0 + +#define NV9097_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NV9097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NV9097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NV9097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NV9097_PM_TRIGGER_END 0x1114 +#define NV9097_PM_TRIGGER_END_V 31:0 + +#define NV9097_SET_VERTEX_ID_BASE 0x1118 +#define NV9097_SET_VERTEX_ID_BASE_V 31:0 + +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NV9097_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NV9097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NV9097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NV9097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NV9097_FLUSH_PENDING_WRITES 0x1144 +#define NV9097_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NV9097_SET_VAB_DATA_CONTROL 0x114c +#define NV9097_SET_VAB_DATA_CONTROL_VAB_INDEX 7:0 +#define NV9097_SET_VAB_DATA_CONTROL_COMPONENT_COUNT 10:8 +#define NV9097_SET_VAB_DATA_CONTROL_COMPONENT_BYTE_WIDTH 14:12 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT 18:16 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_SNORM 0x00000001 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_UNORM 0x00000002 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_SINT 0x00000003 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_UINT 0x00000004 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_USCALED 0x00000005 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_SSCALED 0x00000006 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_FLOAT 0x00000007 + +#define NV9097_SET_VAB_DATA(i) (0x1150+(i)*4) +#define NV9097_SET_VAB_DATA_V 31:0 + +#define NV9097_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NV9097_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NV9097_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NV9097_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_SET_CT_SELECT 0x121c +#define NV9097_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NV9097_SET_CT_SELECT_TARGET0 6:4 +#define NV9097_SET_CT_SELECT_TARGET1 9:7 +#define NV9097_SET_CT_SELECT_TARGET2 12:10 +#define NV9097_SET_CT_SELECT_TARGET3 15:13 +#define NV9097_SET_CT_SELECT_TARGET4 18:16 +#define NV9097_SET_CT_SELECT_TARGET5 21:19 +#define NV9097_SET_CT_SELECT_TARGET6 24:22 +#define NV9097_SET_CT_SELECT_TARGET7 27:25 + +#define NV9097_SET_COMPRESSION_THRESHOLD 0x1220 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NV9097_SET_ZT_SIZE_A 0x1228 +#define NV9097_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NV9097_SET_ZT_SIZE_B 0x122c +#define NV9097_SET_ZT_SIZE_B_HEIGHT 16:0 + +#define NV9097_SET_ZT_SIZE_C 0x1230 +#define NV9097_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NV9097_SET_ZT_SIZE_C_CONTROL 16:16 +#define NV9097_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NV9097_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NV9097_SET_SAMPLER_BINDING 0x1234 +#define NV9097_SET_SAMPLER_BINDING_V 0:0 +#define NV9097_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NV9097_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NV9097_DRAW_AUTO 0x123c +#define NV9097_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NV9097_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NV9097_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 9:0 + +#define NV9097_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NV9097_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NV9097_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NV9097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NV9097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NV9097_SET_SHADER_SCHEDULING 0x12ac +#define NV9097_SET_SHADER_SCHEDULING_MODE 0:0 +#define NV9097_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 +#define NV9097_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 + +#define NV9097_CLEAR_ZCULL_REGION 0x12c8 +#define NV9097_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NV9097_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NV9097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NV9097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NV9097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NV9097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NV9097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NV9097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NV9097_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NV9097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NV9097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NV9097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NV9097_SET_DEPTH_TEST 0x12cc +#define NV9097_SET_DEPTH_TEST_ENABLE 0:0 +#define NV9097_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_FILL_MODE 0x12d0 +#define NV9097_SET_FILL_MODE_V 31:0 +#define NV9097_SET_FILL_MODE_V_POINT 0x00000001 +#define NV9097_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NV9097_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NV9097_SET_SHADE_MODE 0x12d4 +#define NV9097_SET_SHADE_MODE_V 31:0 +#define NV9097_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NV9097_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NV9097_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NV9097_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NV9097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NV9097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NV9097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NV9097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NV9097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NV9097_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NV9097_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NV9097_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NV9097_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_DEPTH_WRITE 0x12e8 +#define NV9097_SET_DEPTH_WRITE_ENABLE 0:0 +#define NV9097_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_ALPHA_TEST 0x12ec +#define NV9097_SET_ALPHA_TEST_ENABLE 0:0 +#define NV9097_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NV9097_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NV9097_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NV9097_DRAW_INLINE_INDEX4X8 0x1304 +#define NV9097_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NV9097_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NV9097_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NV9097_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NV9097_D3D_SET_CULL_MODE 0x1308 +#define NV9097_D3D_SET_CULL_MODE_V 31:0 +#define NV9097_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NV9097_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NV9097_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NV9097_SET_DEPTH_FUNC 0x130c +#define NV9097_SET_DEPTH_FUNC_V 31:0 +#define NV9097_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NV9097_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NV9097_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NV9097_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NV9097_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NV9097_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NV9097_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NV9097_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NV9097_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NV9097_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NV9097_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NV9097_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NV9097_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NV9097_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NV9097_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NV9097_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NV9097_SET_ALPHA_REF 0x1310 +#define NV9097_SET_ALPHA_REF_V 31:0 + +#define NV9097_SET_ALPHA_FUNC 0x1314 +#define NV9097_SET_ALPHA_FUNC_V 31:0 +#define NV9097_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NV9097_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NV9097_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NV9097_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NV9097_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NV9097_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NV9097_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NV9097_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NV9097_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NV9097_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NV9097_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NV9097_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NV9097_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NV9097_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NV9097_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NV9097_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NV9097_SET_DRAW_AUTO_STRIDE 0x1318 +#define NV9097_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NV9097_SET_BLEND_CONST_RED 0x131c +#define NV9097_SET_BLEND_CONST_RED_V 31:0 + +#define NV9097_SET_BLEND_CONST_GREEN 0x1320 +#define NV9097_SET_BLEND_CONST_GREEN_V 31:0 + +#define NV9097_SET_BLEND_CONST_BLUE 0x1324 +#define NV9097_SET_BLEND_CONST_BLUE_V 31:0 + +#define NV9097_SET_BLEND_CONST_ALPHA 0x1328 +#define NV9097_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NV9097_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NV9097_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NV9097_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NV9097_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NV9097_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS 2:1 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY 0x00000000 + +#define NV9097_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NV9097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NV9097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NV9097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_BLEND_COLOR_OP 0x1340 +#define NV9097_SET_BLEND_COLOR_OP_V 31:0 +#define NV9097_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NV9097_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NV9097_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NV9097_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NV9097_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NV9097_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NV9097_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NV9097_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NV9097_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NV9097_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_BLEND_ALPHA_OP 0x134c +#define NV9097_SET_BLEND_ALPHA_OP_V 31:0 +#define NV9097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NV9097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NV9097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NV9097_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NV9097_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NV9097_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NV9097_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NV9097_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NV9097_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NV9097_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_GLOBAL_COLOR_KEY 0x1354 +#define NV9097_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NV9097_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NV9097_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_SINGLE_ROP_CONTROL 0x135c +#define NV9097_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NV9097_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_BLEND(i) (0x1360+(i)*4) +#define NV9097_SET_BLEND_ENABLE 0:0 +#define NV9097_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NV9097_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_STENCIL_TEST 0x1380 +#define NV9097_SET_STENCIL_TEST_ENABLE 0:0 +#define NV9097_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_STENCIL_OP_FAIL 0x1384 +#define NV9097_SET_STENCIL_OP_FAIL_V 31:0 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NV9097_SET_STENCIL_OP_ZFAIL 0x1388 +#define NV9097_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NV9097_SET_STENCIL_OP_ZPASS 0x138c +#define NV9097_SET_STENCIL_OP_ZPASS_V 31:0 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NV9097_SET_STENCIL_FUNC 0x1390 +#define NV9097_SET_STENCIL_FUNC_V 31:0 +#define NV9097_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NV9097_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NV9097_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NV9097_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NV9097_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NV9097_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NV9097_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NV9097_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NV9097_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NV9097_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NV9097_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NV9097_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NV9097_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NV9097_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NV9097_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NV9097_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NV9097_SET_STENCIL_FUNC_REF 0x1394 +#define NV9097_SET_STENCIL_FUNC_REF_V 7:0 + +#define NV9097_SET_STENCIL_FUNC_MASK 0x1398 +#define NV9097_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NV9097_SET_STENCIL_MASK 0x139c +#define NV9097_SET_STENCIL_MASK_V 7:0 + +#define NV9097_SET_DRAW_AUTO_START 0x13a4 +#define NV9097_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NV9097_SET_PS_SATURATE 0x13a8 +#define NV9097_SET_PS_SATURATE_OUTPUT0 0:0 +#define NV9097_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT1 4:4 +#define NV9097_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT2 8:8 +#define NV9097_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT3 12:12 +#define NV9097_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT4 16:16 +#define NV9097_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT5 20:20 +#define NV9097_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT6 24:24 +#define NV9097_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT7 28:28 +#define NV9097_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 + +#define NV9097_SET_WINDOW_ORIGIN 0x13ac +#define NV9097_SET_WINDOW_ORIGIN_MODE 0:0 +#define NV9097_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NV9097_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NV9097_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NV9097_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NV9097_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NV9097_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NV9097_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NV9097_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NV9097_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NV9097_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NV9097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NV9097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_ALPHA_HYSTERESIS 0x1420 +#define NV9097_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NV9097_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NV9097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NV9097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NV9097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NV9097_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NV9097_INVALIDATE_DA_DMA_CACHE 0x142c +#define NV9097_INVALIDATE_DA_DMA_CACHE_V 0:0 + +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR 0x1430 +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR_UNORM_ENABLE 4:4 +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR_UNORM_ENABLE_FALSE 0x00000000 +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR_UNORM_ENABLE_TRUE 0x00000001 +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR_SRGB_ENABLE 8:8 +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR_SRGB_ENABLE_FALSE 0x00000000 +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR_SRGB_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NV9097_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NV9097_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NV9097_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NV9097_X_X_X_SET_CLEAR_CONTROL 0x143c +#define NV9097_X_X_X_SET_CLEAR_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NV9097_X_X_X_SET_CLEAR_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CLEAR_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CLEAR_CONTROL_USE_CLEAR_RECT 4:4 +#define NV9097_X_X_X_SET_CLEAR_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CLEAR_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 + +#define NV9097_SET_PS_WARP_WATERMARKS 0x1450 +#define NV9097_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NV9097_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NV9097_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NV9097_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NV9097_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NV9097_STORE_ZCULL 0x1464 +#define NV9097_STORE_ZCULL_V 0:0 + +#define NV9097_LOAD_ZCULL 0x1500 +#define NV9097_LOAD_ZCULL_V 0:0 + +#define NV9097_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NV9097_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NV9097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NV9097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NV9097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NV9097_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NV9097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NV9097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NV9097_SET_USER_CLIP_ENABLE 0x1510 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NV9097_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NV9097_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NV9097_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_POINT_SIZE 0x1518 +#define NV9097_SET_POINT_SIZE_V 31:0 + +#define NV9097_SET_ZCULL_STATS 0x151c +#define NV9097_SET_ZCULL_STATS_ENABLE 0:0 +#define NV9097_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_POINT_SPRITE 0x1520 +#define NV9097_SET_POINT_SPRITE_ENABLE 0:0 +#define NV9097_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SHADER_EXCEPTIONS 0x1528 +#define NV9097_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NV9097_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NV9097_CLEAR_REPORT_VALUE 0x1530 +#define NV9097_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NV9097_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NV9097_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NV9097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NV9097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NV9097_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NV9097_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 + +#define NV9097_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NV9097_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NV9097_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_ZT_SELECT 0x1538 +#define NV9097_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NV9097_SET_RENDER_ENABLE_A 0x1550 +#define NV9097_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_RENDER_ENABLE_B 0x1554 +#define NV9097_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_RENDER_ENABLE_C 0x1558 +#define NV9097_SET_RENDER_ENABLE_C_MODE 2:0 +#define NV9097_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV9097_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV9097_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV9097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV9097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV9097_SET_TEX_SAMPLER_POOL_A 0x155c +#define NV9097_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NV9097_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NV9097_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NV9097_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NV9097_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NV9097_SET_ANTI_ALIASED_LINE 0x1570 +#define NV9097_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NV9097_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_TEX_HEADER_POOL_A 0x1574 +#define NV9097_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_TEX_HEADER_POOL_B 0x1578 +#define NV9097_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_TEX_HEADER_POOL_C 0x157c +#define NV9097_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NV9097_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NV9097_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NV9097_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NV9097_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NV9097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NV9097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NV9097_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NV9097_SET_BACK_STENCIL_FUNC 0x15a4 +#define NV9097_SET_BACK_STENCIL_FUNC_V 31:0 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NV9097_SET_SRGB_WRITE 0x15b8 +#define NV9097_SET_SRGB_WRITE_ENABLE 0:0 +#define NV9097_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_DEPTH_BIAS 0x15bc +#define NV9097_SET_DEPTH_BIAS_V 31:0 + +#define NV9097_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NV9097_SET_ZCULL_REGION_FORMAT_TYPE 1:0 +#define NV9097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NV9097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NV9097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NV9097_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 + +#define NV9097_SET_RT_LAYER 0x15cc +#define NV9097_SET_RT_LAYER_V 15:0 +#define NV9097_SET_RT_LAYER_CONTROL 16:16 +#define NV9097_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NV9097_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NV9097_SET_ANTI_ALIAS 0x15d0 +#define NV9097_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NV9097_SET_EDGE_FLAG 0x15e4 +#define NV9097_SET_EDGE_FLAG_V 0:0 +#define NV9097_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NV9097_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NV9097_DRAW_INLINE_INDEX 0x15e8 +#define NV9097_DRAW_INLINE_INDEX_V 31:0 + +#define NV9097_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NV9097_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NV9097_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NV9097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NV9097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NV9097_DRAW_INLINE_INDEX2X16 0x15f0 +#define NV9097_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NV9097_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NV9097_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NV9097_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NV9097_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NV9097_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NV9097_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NV9097_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NV9097_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NV9097_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NV9097_SET_POINT_SPRITE_SELECT 0x1604 +#define NV9097_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NV9097_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NV9097_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NV9097_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NV9097_SET_PROGRAM_REGION_A 0x1608 +#define NV9097_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NV9097_SET_PROGRAM_REGION_B 0x160c +#define NV9097_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NV9097_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NV9097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NV9097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NV9097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NV9097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NV9097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NV9097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NV9097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NV9097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NV9097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NV9097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NV9097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NV9097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NV9097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NV9097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NV9097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NV9097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NV9097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NV9097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NV9097_END 0x1614 +#define NV9097_END_V 0:0 + +#define NV9097_BEGIN 0x1618 +#define NV9097_BEGIN_OP 15:0 +#define NV9097_BEGIN_OP_POINTS 0x00000000 +#define NV9097_BEGIN_OP_LINES 0x00000001 +#define NV9097_BEGIN_OP_LINE_LOOP 0x00000002 +#define NV9097_BEGIN_OP_LINE_STRIP 0x00000003 +#define NV9097_BEGIN_OP_TRIANGLES 0x00000004 +#define NV9097_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NV9097_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NV9097_BEGIN_OP_QUADS 0x00000007 +#define NV9097_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NV9097_BEGIN_OP_POLYGON 0x00000009 +#define NV9097_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NV9097_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NV9097_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_BEGIN_OP_PATCH 0x0000000E +#define NV9097_BEGIN_PRIMITIVE_ID 24:24 +#define NV9097_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NV9097_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NV9097_BEGIN_INSTANCE_ID 27:26 +#define NV9097_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NV9097_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NV9097_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NV9097_BEGIN_SPLIT_MODE 30:29 +#define NV9097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NV9097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NV9097_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NV9097_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 + +#define NV9097_SET_VERTEX_ID_COPY 0x161c +#define NV9097_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NV9097_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NV9097_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NV9097_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NV9097_ADD_TO_PRIMITIVE_ID 0x1620 +#define NV9097_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NV9097_LOAD_PRIMITIVE_ID 0x1624 +#define NV9097_LOAD_PRIMITIVE_ID_V 31:0 + +#define NV9097_SET_SHADER_BASED_CULL 0x162c +#define NV9097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NV9097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NV9097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NV9097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SHADER_ISA_VERSION 0x1634 +#define NV9097_SET_SHADER_ISA_VERSION_MINOR_SUB 7:0 +#define NV9097_SET_SHADER_ISA_VERSION_MINOR 15:8 +#define NV9097_SET_SHADER_ISA_VERSION_MAJOR 23:16 + +#define NV9097_SET_FERMI_CLASS_VERSION 0x1638 +#define NV9097_SET_FERMI_CLASS_VERSION_CURRENT 15:0 +#define NV9097_SET_FERMI_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NV9097_SET_VAB_PAGE 0x163c +#define NV9097_SET_VAB_PAGE_READ_SELECT 0:0 +#define NV9097_SET_VAB_PAGE_READ_SELECT_PAGES_0_AND_1 0x00000000 +#define NV9097_SET_VAB_PAGE_READ_SELECT_PAGES_0_AND_2 0x00000001 + +#define NV9097_DRAW_INLINE_VERTEX 0x1640 +#define NV9097_DRAW_INLINE_VERTEX_V 31:0 + +#define NV9097_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NV9097_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NV9097_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NV9097_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NV9097_SET_DA_OUTPUT 0x164c +#define NV9097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NV9097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NV9097_SET_ANTI_ALIASED_POINT 0x1658 +#define NV9097_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NV9097_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_POINT_CENTER_MODE 0x165c +#define NV9097_SET_POINT_CENTER_MODE_V 31:0 +#define NV9097_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NV9097_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NV9097_SET_CUBEMAP_INTER_FACE_FILTERING 0x1664 +#define NV9097_SET_CUBEMAP_INTER_FACE_FILTERING_MODE 2:1 +#define NV9097_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_USE_WRAP 0x00000000 +#define NV9097_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_OVERRIDE_WRAP 0x00000001 +#define NV9097_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_SPAN_SEAM 0x00000002 +#define NV9097_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_CROSS_SEAM 0x00000003 + +#define NV9097_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NV9097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NV9097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NV9097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NV9097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NV9097_SET_LINE_STIPPLE 0x166c +#define NV9097_SET_LINE_STIPPLE_ENABLE 0:0 +#define NV9097_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NV9097_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NV9097_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NV9097_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NV9097_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NV9097_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NV9097_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NV9097_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NV9097_SET_PROVOKING_VERTEX 0x1684 +#define NV9097_SET_PROVOKING_VERTEX_V 0:0 +#define NV9097_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NV9097_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NV9097_SET_TWO_SIDED_LIGHT 0x1688 +#define NV9097_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NV9097_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_POLYGON_STIPPLE 0x168c +#define NV9097_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NV9097_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SHADER_CONTROL 0x1690 +#define NV9097_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NV9097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NV9097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NV9097_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO 16:16 +#define NV9097_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NV9097_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NV9097_LAUNCH_VERTEX 0x169c +#define NV9097_LAUNCH_VERTEX_V 0:0 + +#define NV9097_CHECK_FERMI_CLASS_VERSION 0x16a0 +#define NV9097_CHECK_FERMI_CLASS_VERSION_CURRENT 15:0 +#define NV9097_CHECK_FERMI_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NV9097_SET_SPH_VERSION 0x16a4 +#define NV9097_SET_SPH_VERSION_CURRENT 15:0 +#define NV9097_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NV9097_CHECK_SPH_VERSION 0x16a8 +#define NV9097_CHECK_SPH_VERSION_CURRENT 15:0 +#define NV9097_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NV9097_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NV9097_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NV9097_SET_AAM_VERSION 0x1790 +#define NV9097_SET_AAM_VERSION_CURRENT 15:0 +#define NV9097_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NV9097_CHECK_AAM_VERSION 0x1794 +#define NV9097_CHECK_AAM_VERSION_CURRENT 15:0 +#define NV9097_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NV9097_SET_ZT_LAYER 0x179c +#define NV9097_SET_ZT_LAYER_OFFSET 15:0 + +#define NV9097_SET_VAB_MEMORY_AREA_A 0x17bc +#define NV9097_SET_VAB_MEMORY_AREA_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_VAB_MEMORY_AREA_B 0x17c0 +#define NV9097_SET_VAB_MEMORY_AREA_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_VAB_MEMORY_AREA_C 0x17c4 +#define NV9097_SET_VAB_MEMORY_AREA_C_SIZE 1:0 +#define NV9097_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_64K 0x00000001 +#define NV9097_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_128K 0x00000002 +#define NV9097_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_256K 0x00000003 + +#define NV9097_SET_INDEX_BUFFER_A 0x17c8 +#define NV9097_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NV9097_SET_INDEX_BUFFER_B 0x17cc +#define NV9097_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NV9097_SET_INDEX_BUFFER_C 0x17d0 +#define NV9097_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NV9097_SET_INDEX_BUFFER_D 0x17d4 +#define NV9097_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NV9097_SET_INDEX_BUFFER_E 0x17d8 +#define NV9097_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NV9097_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NV9097_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NV9097_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NV9097_SET_INDEX_BUFFER_F 0x17dc +#define NV9097_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NV9097_DRAW_INDEX_BUFFER 0x17e0 +#define NV9097_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_SET_DEPTH_BIAS_CLAMP 0x187c +#define NV9097_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NV9097_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NV9097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NV9097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NV9097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NV9097_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NV9097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NV9097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NV9097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NV9097_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NV9097_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NV9097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NV9097_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NV9097_OGL_SET_CULL 0x1918 +#define NV9097_OGL_SET_CULL_ENABLE 0:0 +#define NV9097_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NV9097_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NV9097_OGL_SET_FRONT_FACE 0x191c +#define NV9097_OGL_SET_FRONT_FACE_V 31:0 +#define NV9097_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NV9097_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NV9097_OGL_SET_CULL_FACE 0x1920 +#define NV9097_OGL_SET_CULL_FACE_V 31:0 +#define NV9097_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NV9097_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NV9097_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NV9097_SET_VIEWPORT_PIXEL 0x1924 +#define NV9097_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NV9097_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NV9097_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NV9097_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NV9097_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NV9097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NV9097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NV9097_INVALIDATE_CONSTANT_BUFFER_CACHE 0x1930 +#define NV9097_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2 0:0 +#define NV9097_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_FALSE 0x00000000 +#define NV9097_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_TRUE 0x00000001 + +#define NV9097_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NV9097_SET_USER_CLIP_OP 0x1940 +#define NV9097_SET_USER_CLIP_OP_PLANE0 0:0 +#define NV9097_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE1 4:4 +#define NV9097_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE2 8:8 +#define NV9097_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE3 12:12 +#define NV9097_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE4 16:16 +#define NV9097_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE5 20:20 +#define NV9097_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE6 24:24 +#define NV9097_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE7 28:28 +#define NV9097_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NV9097_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NV9097_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NV9097_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NV9097_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NV9097_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NV9097_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NV9097_SET_WINDOW_CLIP_ENABLE 0x194c +#define NV9097_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NV9097_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_WINDOW_CLIP_TYPE 0x1950 +#define NV9097_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NV9097_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NV9097_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NV9097_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NV9097_INVALIDATE_ZCULL 0x1958 +#define NV9097_INVALIDATE_ZCULL_V 31:0 +#define NV9097_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NV9097_SET_ZCULL 0x1968 +#define NV9097_SET_ZCULL_Z_ENABLE 0:0 +#define NV9097_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NV9097_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NV9097_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_ZCULL_BOUNDS 0x196c +#define NV9097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NV9097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NV9097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NV9097_ZCULL_SYNC 0x1978 +#define NV9097_ZCULL_SYNC_V 31:0 + +#define NV9097_SET_CLIP_ID_TEST 0x197c +#define NV9097_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NV9097_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NV9097_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NV9097_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NV9097_SET_CLIP_ID 0x1984 +#define NV9097_SET_CLIP_ID_V 31:0 + +#define NV9097_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NV9097_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NV9097_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NV9097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NV9097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NV9097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NV9097_SET_LOGIC_OP 0x19c4 +#define NV9097_SET_LOGIC_OP_ENABLE 0:0 +#define NV9097_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NV9097_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_LOGIC_OP_FUNC 0x19c8 +#define NV9097_SET_LOGIC_OP_FUNC_V 31:0 +#define NV9097_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NV9097_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NV9097_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NV9097_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NV9097_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NV9097_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NV9097_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NV9097_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NV9097_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NV9097_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NV9097_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NV9097_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NV9097_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NV9097_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NV9097_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NV9097_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NV9097_SET_Z_COMPRESSION 0x19cc +#define NV9097_SET_Z_COMPRESSION_ENABLE 0:0 +#define NV9097_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NV9097_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NV9097_CLEAR_SURFACE 0x19d0 +#define NV9097_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NV9097_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NV9097_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_SURFACE_R_ENABLE 2:2 +#define NV9097_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_SURFACE_G_ENABLE 3:3 +#define NV9097_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_SURFACE_B_ENABLE 4:4 +#define NV9097_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_SURFACE_A_ENABLE 5:5 +#define NV9097_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NV9097_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NV9097_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NV9097_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NV9097_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NV9097_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NV9097_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NV9097_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NV9097_SET_CT_WRITE_R_ENABLE 0:0 +#define NV9097_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NV9097_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NV9097_SET_CT_WRITE_G_ENABLE 4:4 +#define NV9097_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NV9097_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NV9097_SET_CT_WRITE_B_ENABLE 8:8 +#define NV9097_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NV9097_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NV9097_SET_CT_WRITE_A_ENABLE 12:12 +#define NV9097_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NV9097_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NV9097_PIPE_NOP 0x1a2c +#define NV9097_PIPE_NOP_V 31:0 + +#define NV9097_SET_SPARE00 0x1a30 +#define NV9097_SET_SPARE00_V 31:0 + +#define NV9097_SET_SPARE01 0x1a34 +#define NV9097_SET_SPARE01_V 31:0 + +#define NV9097_SET_SPARE02 0x1a38 +#define NV9097_SET_SPARE02_V 31:0 + +#define NV9097_SET_SPARE03 0x1a3c +#define NV9097_SET_SPARE03_V 31:0 + +#define NV9097_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NV9097_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NV9097_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NV9097_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NV9097_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NV9097_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NV9097_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NV9097_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NV9097_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NV9097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NV9097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NV9097_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NV9097_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NV9097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NV9097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NV9097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NV9097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NV9097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 + +#define NV9097_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NV9097_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NV9097_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NV9097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NV9097_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NV9097_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NV9097_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NV9097_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NV9097_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NV9097_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NV9097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NV9097_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NV9097_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NV9097_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NV9097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NV9097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NV9097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NV9097_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NV9097_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NV9097_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NV9097_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NV9097_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NV9097_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NV9097_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NV9097_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NV9097_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NV9097_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NV9097_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NV9097_SET_PIPELINE_SHADER_TYPE 7:4 +#define NV9097_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NV9097_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NV9097_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NV9097_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NV9097_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NV9097_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NV9097_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NV9097_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NV9097_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NV9097_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NV9097_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NV9097_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NV9097_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NV9097_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NV9097_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NV9097_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NV9097_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NV9097_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NV9097_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NV9097_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NV9097_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NV9097_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NV9097_SET_BINDING_CONTROL_TEXTURE(j) (0x2200+(j)*16) +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS 3:0 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__1 0x00000000 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__2 0x00000001 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__4 0x00000002 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__8 0x00000003 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__16 0x00000004 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS 7:4 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__1 0x00000000 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__2 0x00000001 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__4 0x00000002 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__8 0x00000003 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__16 0x00000004 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__32 0x00000005 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__64 0x00000006 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__128 0x00000007 + +#define NV9097_SET_BINDING_CONTROL_RESERVED_A(j) (0x2204+(j)*16) +#define NV9097_SET_BINDING_CONTROL_RESERVED_A_V 0:0 + +#define NV9097_SET_BINDING_CONTROL_RESERVED_B(j) (0x2208+(j)*16) +#define NV9097_SET_BINDING_CONTROL_RESERVED_B_V 0:0 + +#define NV9097_SET_FALCON00 0x2300 +#define NV9097_SET_FALCON00_V 31:0 + +#define NV9097_SET_FALCON01 0x2304 +#define NV9097_SET_FALCON01_V 31:0 + +#define NV9097_SET_FALCON02 0x2308 +#define NV9097_SET_FALCON02_V 31:0 + +#define NV9097_SET_FALCON03 0x230c +#define NV9097_SET_FALCON03_V 31:0 + +#define NV9097_SET_FALCON04 0x2310 +#define NV9097_SET_FALCON04_V 31:0 + +#define NV9097_SET_FALCON05 0x2314 +#define NV9097_SET_FALCON05_V 31:0 + +#define NV9097_SET_FALCON06 0x2318 +#define NV9097_SET_FALCON06_V 31:0 + +#define NV9097_SET_FALCON07 0x231c +#define NV9097_SET_FALCON07_V 31:0 + +#define NV9097_SET_FALCON08 0x2320 +#define NV9097_SET_FALCON08_V 31:0 + +#define NV9097_SET_FALCON09 0x2324 +#define NV9097_SET_FALCON09_V 31:0 + +#define NV9097_SET_FALCON10 0x2328 +#define NV9097_SET_FALCON10_V 31:0 + +#define NV9097_SET_FALCON11 0x232c +#define NV9097_SET_FALCON11_V 31:0 + +#define NV9097_SET_FALCON12 0x2330 +#define NV9097_SET_FALCON12_V 31:0 + +#define NV9097_SET_FALCON13 0x2334 +#define NV9097_SET_FALCON13_V 31:0 + +#define NV9097_SET_FALCON14 0x2338 +#define NV9097_SET_FALCON14_V 31:0 + +#define NV9097_SET_FALCON15 0x233c +#define NV9097_SET_FALCON15_V 31:0 + +#define NV9097_SET_FALCON16 0x2340 +#define NV9097_SET_FALCON16_V 31:0 + +#define NV9097_SET_FALCON17 0x2344 +#define NV9097_SET_FALCON17_V 31:0 + +#define NV9097_SET_FALCON18 0x2348 +#define NV9097_SET_FALCON18_V 31:0 + +#define NV9097_SET_FALCON19 0x234c +#define NV9097_SET_FALCON19_V 31:0 + +#define NV9097_SET_FALCON20 0x2350 +#define NV9097_SET_FALCON20_V 31:0 + +#define NV9097_SET_FALCON21 0x2354 +#define NV9097_SET_FALCON21_V 31:0 + +#define NV9097_SET_FALCON22 0x2358 +#define NV9097_SET_FALCON22_V 31:0 + +#define NV9097_SET_FALCON23 0x235c +#define NV9097_SET_FALCON23_V 31:0 + +#define NV9097_SET_FALCON24 0x2360 +#define NV9097_SET_FALCON24_V 31:0 + +#define NV9097_SET_FALCON25 0x2364 +#define NV9097_SET_FALCON25_V 31:0 + +#define NV9097_SET_FALCON26 0x2368 +#define NV9097_SET_FALCON26_V 31:0 + +#define NV9097_SET_FALCON27 0x236c +#define NV9097_SET_FALCON27_V 31:0 + +#define NV9097_SET_FALCON28 0x2370 +#define NV9097_SET_FALCON28_V 31:0 + +#define NV9097_SET_FALCON29 0x2374 +#define NV9097_SET_FALCON29_V 31:0 + +#define NV9097_SET_FALCON30 0x2378 +#define NV9097_SET_FALCON30_V 31:0 + +#define NV9097_SET_FALCON31 0x237c +#define NV9097_SET_FALCON31_V 31:0 + +#define NV9097_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NV9097_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NV9097_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NV9097_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NV9097_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NV9097_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NV9097_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NV9097_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NV9097_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NV9097_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NV9097_BIND_GROUP_TEXTURE_SAMPLER(j) (0x2400+(j)*32) +#define NV9097_BIND_GROUP_TEXTURE_SAMPLER_VALID 0:0 +#define NV9097_BIND_GROUP_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 +#define NV9097_BIND_GROUP_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 +#define NV9097_BIND_GROUP_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 +#define NV9097_BIND_GROUP_TEXTURE_SAMPLER_INDEX 24:12 + +#define NV9097_BIND_GROUP_TEXTURE_HEADER(j) (0x2404+(j)*32) +#define NV9097_BIND_GROUP_TEXTURE_HEADER_VALID 0:0 +#define NV9097_BIND_GROUP_TEXTURE_HEADER_VALID_FALSE 0x00000000 +#define NV9097_BIND_GROUP_TEXTURE_HEADER_VALID_TRUE 0x00000001 +#define NV9097_BIND_GROUP_TEXTURE_HEADER_TEXTURE_SLOT 8:1 +#define NV9097_BIND_GROUP_TEXTURE_HEADER_INDEX 30:9 + +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_SAMPLER(j) (0x2408+(j)*32) +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_SAMPLER_VALID 0:0 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_SAMPLER_INDEX 24:12 + +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_HEADER(j) (0x240c+(j)*32) +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_HEADER_VALID 0:0 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_HEADER_VALID_FALSE 0x00000000 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_HEADER_VALID_TRUE 0x00000001 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_HEADER_TEXTURE_SLOT 8:1 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_HEADER_INDEX 30:9 + +#define NV9097_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NV9097_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NV9097_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NV9097_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NV9097_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NV9097_RESERVED_GROUP_B_RESERVED_A(j) (0x2500+(j)*32) +#define NV9097_RESERVED_GROUP_B_RESERVED_A_V 0:0 + +#define NV9097_RESERVED_GROUP_B_RESERVED_B(j) (0x2504+(j)*32) +#define NV9097_RESERVED_GROUP_B_RESERVED_B_V 0:0 + +#define NV9097_RESERVED_GROUP_B_RESERVED_C(j) (0x2508+(j)*32) +#define NV9097_RESERVED_GROUP_B_RESERVED_C_V 0:0 + +#define NV9097_RESERVED_GROUP_B_RESERVED_D(j) (0x250c+(j)*32) +#define NV9097_RESERVED_GROUP_B_RESERVED_D_V 0:0 + +#define NV9097_RESERVED_GROUP_B_RESERVED_E(j) (0x2510+(j)*32) +#define NV9097_RESERVED_GROUP_B_RESERVED_E_V 0:0 + +#define NV9097_SET_COLOR_CLAMP 0x2600 +#define NV9097_SET_COLOR_CLAMP_ENABLE 0:0 +#define NV9097_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NV9097_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SU_LD_ST_TARGET_A(j) (0x2700+(j)*32) +#define NV9097_SET_SU_LD_ST_TARGET_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_SU_LD_ST_TARGET_B(j) (0x2704+(j)*32) +#define NV9097_SET_SU_LD_ST_TARGET_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_SU_LD_ST_TARGET_C(j) (0x2708+(j)*32) +#define NV9097_SET_SU_LD_ST_TARGET_C_WIDTH 31:0 + +#define NV9097_SET_SU_LD_ST_TARGET_D(j) (0x270c+(j)*32) +#define NV9097_SET_SU_LD_ST_TARGET_D_HEIGHT 16:0 +#define NV9097_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY 20:20 +#define NV9097_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_BLOCKLINEAR 0x00000000 +#define NV9097_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_PITCH 0x00000001 + +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT(j) (0x2710+(j)*32) +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_TYPE 0:0 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_TYPE_COLOR 0x00000000 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_TYPE_ZETA 0x00000001 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR 11:4 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_DISABLED 0x00000000 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_AF32 0x000000C0 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_AS32 0x000000C1 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_AU32 0x000000C2 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_X32 0x000000C3 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_X32 0x000000C4 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_X32 0x000000C5 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16_B16_A16 0x000000C6 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16_BN16_AN16 0x000000C7 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16_BS16_AS16 0x000000C8 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16_BU16_AU16 0x000000C9 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_AF16 0x000000CA +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32 0x000000CB +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32 0x000000CC +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32 0x000000CD +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_X16 0x000000CE +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8G8B8 0x000000CF +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8RL8GL8BL8 0x000000D0 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2B10G10R10 0x000000D1 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU2BU10GU10RU10 0x000000D2 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8B8G8R8 0x000000D5 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8BL8GL8RL8 0x000000D6 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AN8BN8GN8RN8 0x000000D7 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AS8BS8GS8RS8 0x000000D8 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU8BU8GU8RU8 0x000000D9 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16 0x000000DA +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16 0x000000DB +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16 0x000000DC +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16 0x000000DD +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16 0x000000DE +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2R10G10B10 0x000000DF +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_BF10GF11RF11 0x000000E0 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32 0x000000E3 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32 0x000000E4 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32 0x000000E5 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8R8G8B8 0x000000E6 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8RL8GL8BL8 0x000000E7 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R5G6B5 0x000000E8 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A1R5G5B5 0x000000E9 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_G8R8 0x000000EA +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GN8RN8 0x000000EB +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GS8RS8 0x000000EC +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GU8RU8 0x000000ED +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16 0x000000EE +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16 0x000000EF +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16 0x000000F0 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16 0x000000F1 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16 0x000000F2 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R8 0x000000F3 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN8 0x000000F4 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS8 0x000000F5 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU8 0x000000F6 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8 0x000000F7 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X1R5G5B5 0x000000F8 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8B8G8R8 0x000000F9 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8BL8GL8RL8 0x000000FA +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z1R5G5B5 0x000000FB +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O1R5G5B5 0x000000FC +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z8R8G8B8 0x000000FD +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O8R8G8B8 0x000000FE +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R32 0x000000FF +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A16 0x00000040 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF16 0x00000041 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF32 0x00000042 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8 0x00000043 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_A16 0x00000044 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_AF16 0x00000045 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_AF32 0x00000046 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA 16:12 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z16 0x00000013 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z24S8 0x00000014 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24 0x00000015 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_S8Z24 0x00000016 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_V8Z24 0x00000018 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32 0x0000000A +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X24S8 0x00000019 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24_X16V8S8 0x0000001D +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8X8 0x0000001E +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8S8 0x0000001F + +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE(j) (0x2714+(j)*32) +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH 3:0 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT 7:4 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 + +#define NV9097_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NV9097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NV9097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NV9097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NV9097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 2:0 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 6:4 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 10:8 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 14:12 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 18:16 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 22:20 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 26:24 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 30:28 + +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NV9097_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NV9097_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NV9097_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NV9097_CALL_MME_MACRO_V 31:0 + +#define NV9097_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NV9097_CALL_MME_DATA_V 31:0 + +#endif /* _cl_fermi_a_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl90cc.h b/userspace/sdks/nv570/nvidia/inc/class/cl90cc.h new file mode 100644 index 0000000..25d8570 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl90cc.h @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl90cc_h_ +#define _cl90cc_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define GF100_PROFILER (0x000090CC) + +/* + * Creating the GF100_PROFILER object: + * - The profiler object is instantiated as a child of either the subdevice or + * a channel group or channel, depending on whether reservations + * should be global to the subdevice or per-context. When the profiler + * requests a reservation or information about outstanding reservations, the + * scope of the request is determined by the profiler object's parent class. + */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl90cc_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl90cd.h b/userspace/sdks/nv570/nvidia/inc/class/cl90cd.h new file mode 100644 index 0000000..6c626a6 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl90cd.h @@ -0,0 +1,237 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * NV_EVENT_BUFFER + * An event buffer is shared between user (RO) and kernel(RW). + * It holds debug/profile event data provided by the kernel. + * + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl90cd.finn +// + +#define NV_EVENT_BUFFER (0x90cdU) /* finn: Evaluated from "NV_EVENT_BUFFER_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* + * NV_EVENT_BUFFER_HEADER + * This structure holds the get and put values used to index/consume event buffer. + * Along with other RO data shared with the user. + * + * recordGet/Put: These "pointers" work in the traditional sense: + * - when GET==PUT, the fifo is empty + * - when GET==PUT+1, the fifo is full + * This implies a full fifo always has one "wasted" element. + * + * recordCount: This is the total number of records added to the buffer by the kernel + * This information is filled out when the buffer is setup to keep newest records. + * recordCount = number of records currently in the buffer + overflow count. + * + * recordDropcount: This is the number of event records that are dropped because the + * buffer is full. + * This information is filled out when event buffer is setup to keep oldest records. + * + * vardataDropcount: Event buffer provides a dual stream of data, where the record can contain + * an optional offset to a variable length data buffer. + * This is the number of variable data records that are dropped because the + * buffer is full. + * This information is filled out when event buffer is setup to keep oldest records. + */ +typedef struct NV_EVENT_BUFFER_HEADER { + NvU32 recordGet; + NvU32 recordPut; + NV_DECLARE_ALIGNED(NvU64 recordCount, 8); + NV_DECLARE_ALIGNED(NvU64 recordDropcount, 8); + NV_DECLARE_ALIGNED(NvU64 vardataDropcount, 8); +} NV_EVENT_BUFFER_HEADER; + +/* + * NV_EVENT_BUFFER_RECORD_HEADER + * This is the header added to each event record. + * This helps identify the event type and variable length data is associated with it. + */ +typedef struct NV_EVENT_BUFFER_RECORD_HEADER { + NvU16 type; + NvU16 subtype; + NvU32 varData; // [31: 5] = (varDataOffset >> 5); 0 < vardataOffset <= vardataBufferSize + // [ 4: 1] = reserved for future use + // [ 0: 0] = isVardataStartOffsetZero +} NV_EVENT_BUFFER_RECORD_HEADER; + +/* + * NV_EVENT_BUFFER_RECORD + * This structure defines a generic event record. + * The size of this record is fixed for a given event buffer. + * It is configured by the user during allocation. + */ +typedef struct NV_EVENT_BUFFER_RECORD { + NV_EVENT_BUFFER_RECORD_HEADER recordHeader; + NV_DECLARE_ALIGNED(NvU64 inlinePayload[1], 8); // 1st element of the payload/data + // Do not add more elements here, inlinePayload can contain more than one elements +} NV_EVENT_BUFFER_RECORD; + +#define NV_EVENT_VARDATA_GRANULARITY 32 +#define NV_EVENT_VARDATA_OFFSET_MASK (~(NV_EVENT_VARDATA_GRANULARITY - 1)) +#define NV_EVENT_VARDATA_START_OFFSET_ZERO 0x01 + +/* + * NV_EVENT_BUFFER_ALLOC_PARAMETERS + * + * bufferHeader [OUT] + * This is the user VA offset pointing to the base of NV_EVENT_BUFFER_HEADER. + * + * recordBuffer [OUT] + * This is the user VA offset pointing to the base of the event record buffer. + * This buffer will contain NV_EVENT_BUFFER_RECORDs added by the kernel. + * + * recordSize [IN] + * This is the size of NV_EVENT_BUFFER_RECORD used by this buffer + * + * recordCount [IN] + * This is the number of records that recordBuffer can hold. + * + * vardataBuffer [OUT] + * This is the user VA offset pointing to the base of the variable data buffer. + * + * vardataBufferSize [IN] + * Size of the variable data buffer in bytes. + * + * recordsFreeThreshold [IN] + * This is the notification threshold for the event record buffer. + * This felid specifies the number of records that the buffer can + * still hold before it gets full. + * + * vardataFreeThreshold [IN] + * This is the notification threshold for the vardata buffer. + * This felid specifies the number of bytes that the buffer can + * still hold before it gets full. + * + * notificationHandle [IN] + * When recordsFreeThreshold or vardataFreeThreshold is met, kernel will notify + * user on this handle. If notificationHandle = NULL, event notification + * is disabled. This is an OS specific notification handle. + * It is a Windows event handle or a fd pointer on Linux. + * + * hSubDevice [IN] + * An event buffer can either hold sub-device related events or system events. + * This handle specifies the sub-device to associate this buffer with. + * If this parameter is NULL, then the buffer is tied to the client instead. + * + * flags [IN] + * Set to 0 by default. + * This field can hold any future flags to configure the buffer if needed. + * + * hBufferHeader [IN] + * The backing memory object for the buffer header. Must be a NV01_MEMORY_DEVICELESS object. + * On Windows platforms, a buffer will be internally generated if hBufferHeader is 0. + * + * hRecordBuffer [IN] + * The backing memory object for the record buffer. Must be a NV01_MEMORY_DEVICELESS object. + * On Windows platforms, a buffer will be internally generated if hRecordBuffer is 0. + * + * hVardataBuffer [IN] + * The backing memory object for the vardata buffer. Must be a NV01_MEMORY_DEVICELESS object. + * On Windows platforms, a buffer will be internally generated if hVardataBuffer is 0. + * + */ +#define NV_EVENT_BUFFER_ALLOC_PARAMETERS_MESSAGE_ID (0x90cdU) + +typedef struct NV_EVENT_BUFFER_ALLOC_PARAMETERS { + NV_DECLARE_ALIGNED(NvP64 bufferHeader, 8); + NV_DECLARE_ALIGNED(NvP64 recordBuffer, 8); + NvU32 recordSize; + NvU32 recordCount; + NV_DECLARE_ALIGNED(NvP64 vardataBuffer, 8); + NvU32 vardataBufferSize; + NvU32 recordsFreeThreshold; + NV_DECLARE_ALIGNED(NvU64 notificationHandle, 8); + NvU32 vardataFreeThreshold; + NvHandle hSubDevice; + NvU32 flags; + + NvHandle hBufferHeader; + NvHandle hRecordBuffer; + NvHandle hVardataBuffer; +} NV_EVENT_BUFFER_ALLOC_PARAMETERS; + +/* + * NV_EVENT_BUFFER_BIND + * This class is used to allocate an Event Type object bound to a given event buffer. + * This allocation call associates an event type with an event buffer. + * Multiple event types can be associated with the same buffer as long as they belong to + * the same category i.e. either sub-device or system. + * When event buffer is enabled, if an event bound to this buffer occurs, + * some relevant data gets added to it. + * cl2080.h has a list of sub-device events that can be associated with a buffer + * cl0000.h has a list of system events that can be associated with a buffer + * These defines are also used in class NV01_EVENT_OS_EVENT (0x79) to get event notification + * and class NV01_EVENT_KERNEL_CALLBACK_EX (0x7E) to get kernel callbacks. + * This class extends that support to additionally get relevant data in an event buffer + * + */ +#define NV_EVENT_BUFFER_BIND (0x0000007F) + +/* + * NV_EVENT_BUFFER_BIND_PARAMETERS + * + * bufferHandle [IN] + * Event buffer handle used to bind the given event type + * + * eventType [IN] + * This is one of the eventTypeIDs from cl2080.h/cl000.h + * e.g. NV2080_NOTIFIERS_PSTATE_CHANGE + * + * eventSubtype [IN] + * Event subtype for a given type of event. + * This field is optional depending on if an eventtype has a subtype. + * + * hClientTarget [IN] + * Handle of the target client whose events are to be bound to the given buffer + * e.g. context switch events can be tracked for a given client. + * This field is optional depending on the event type. + * e.g. pstate change events are per gpu but do not depend on a client. + * + * hSrcResource [IN] + * source resource handle for the event type + * e.g. channel handle: RC/context switch can be tracked for a given channel + * This field is optional depending on the event type. + * e.g. pstate change events are per gpu and cannot be sub-categorized + * + * KernelCallbackdata [IN] + * This field is reserved for KERNEL ONLY clients. + * + */ +typedef struct NV_EVENT_BUFFER_BIND_PARAMETERS { + NvHandle bufferHandle; + NvU16 eventType; + NvU16 eventSubtype; + NvHandle hClientTarget; + NvHandle hSrcResource; + NV_DECLARE_ALIGNED(NvP64 KernelCallbackdata, 8); +} NV_EVENT_BUFFER_BIND_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl90cdfecs.h b/userspace/sdks/nv570/nvidia/inc/class/cl90cdfecs.h new file mode 100644 index 0000000..5118249 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl90cdfecs.h @@ -0,0 +1,112 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl90cdFecs_h_ +#define _cl90cdFecs_h_ + +/* This file defines parameters for FECS context switch events*/ + +#define NV_EVENT_BUFFER_FECS_VERSION 2 + +/* + * These are the types of context switch events + * This field gets added to NV_EVENT_BUFFER_FECS_RECORD to specify the sub type of fecs event + * Do *not* edit these as they are defined to maintain consistency with Tegra tools + */ +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_SO 0x00 +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_CTXSW_REQ_BY_HOST 0x01 +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_FE_ACK 0x02 +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_FE_ACK_WFI 0x0a +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_FE_ACK_GFXP 0x0b +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_FE_ACK_CTAP 0x0c +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_FE_ACK_CILP 0x0d +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_SAVE_END 0x03 +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_RESTORE_START 0x04 +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_CONTEXT_START 0x05 +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_SIMPLE_START 0x06 +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_SIMPLE_END 0x07 +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_ENGINE_RESET 0xfe +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_INVALID_TIMESTAMP 0xff +#define NV_EVENT_BUFFER_FECS_CTXSWTAG_LAST NV_EVENT_BUFFER_FECS_EVENTS_CTXSWTAG_INVALID_TIMESTAMP + +/* + * Bit fields used to enable a particular sub type of event + */ +#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_SO NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_SO) +#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_CTXSW_REQ_BY_HOST NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_CTXSW_REQ_BY_HOST) +#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_FE_ACK NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_FE_ACK) +#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_SAVE_END NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_SAVE_END) +#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_RESTORE_START NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_RESTORE_START) +#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_CONTEXT_START NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_CONTEXT_START) +#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_SIMPLE_START NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_SIMPLE_START) +#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_SIMPLE_END NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_SIMPLE_END) + +/* context_id is set to this value if fecs info doesn't match a known channel/tsg handle*/ +#define NV_EVENT_BUFFER_INVALID_CONTEXT 0xFFFFFFFF + +/* + * PID/context_id are set to these values if the data is from another user's + * client and the current user is not an administrator + */ +#define NV_EVENT_BUFFER_HIDDEN_PID 0x0 +#define NV_EVENT_BUFFER_HIDDEN_CONTEXT 0x0 + +/* + * PID/context_id are set to these values if the data is from a kernel client + * and the data is being read by a user client + */ +#define NV_EVENT_BUFFER_KERNEL_PID 0xFFFFFFFF +#define NV_EVENT_BUFFER_KERNEL_CONTEXT 0xFFFFFFFF + +// V1 ------------------------------------------------------------------------ +typedef struct +{ + NvU8 tag; ///< NV_EVENT_BUFFER_FECS_CTXSWTAG_* + NvU8 vmid; + NvU16 seqno; ///< used to detect drop + NvU32 context_id; ///< channel/tsg handle + NvU64 pid NV_ALIGN_BYTES(8); ///< process id + NvU64 timestamp NV_ALIGN_BYTES(8); + /* Do *not* edit items above this to maintain consistency with tegra tools + Always add to the end of this structure to retain backward compatibility */ +} NV_EVENT_BUFFER_FECS_RECORD_V1; + +// V2 ------------------------------------------------------------------------ +typedef struct +{ + NvU8 tag; ///< NV_EVENT_BUFFER_FECS_CTXSWTAG_* + NvU8 vmid; + NvU16 seqno; ///< used to detect drop + NvU32 context_id; ///< channel/tsg handle + NvU32 pid; ///< process id + NvU16 reserved0; + NvU8 migGpuInstanceId; + NvU8 migComputeInstanceId; + NvU64 timestamp NV_ALIGN_BYTES(8); + /* Do *not* edit items above this to maintain consistency with tegra tools + Always add to the end of this structure to retain backward compatibility */ +} NV_EVENT_BUFFER_FECS_RECORD_V2; + +typedef NV_EVENT_BUFFER_FECS_RECORD_V1 NV_EVENT_BUFFER_FECS_RECORD_V0; +typedef NV_EVENT_BUFFER_FECS_RECORD_V1 NV_EVENT_BUFFER_FECS_RECORD; +#endif /* _cl90cdFecs_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl90cdtypes.h b/userspace/sdks/nv570/nvidia/inc/class/cl90cdtypes.h new file mode 100644 index 0000000..f2a40cf --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl90cdtypes.h @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl90cdtypes_h_ +#define _cl90cdtypes_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Legacy values record type values have been kept for backward +// compatibility. New values should be added sequentially. +// +#define NV_EVENT_BUFFER_RECORD_TYPE_INVALID (0) +#define NV_EVENT_BUFFER_RECORD_TYPE_VIDEO_TRACE (1) +#define NV_EVENT_BUFFER_RECORD_TYPE_FECS_CTX_SWITCH_V2 (2) +#define NV_EVENT_BUFFER_RECORD_TYPE_NVTELEMETRY_REPORT_EVENT_SYSTEM (4) +#define NV_EVENT_BUFFER_RECORD_TYPE_NVTELEMETRY_REPORT_EVENT_SUBDEVICE (132) +#define NV_EVENT_BUFFER_RECORD_TYPE_FECS_CTX_SWITCH (134) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _cl90cdtypes_h_ + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl90ce.h b/userspace/sdks/nv570/nvidia/inc/class/cl90ce.h new file mode 100644 index 0000000..b4506df --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl90ce.h @@ -0,0 +1,42 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl90ce_h_ +#define _cl90ce_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* +* NV_MEMORY_DEVICELESS +* Memory that is not associated with a device +*/ +#define NV01_MEMORY_DEVICELESS (0x000090CE) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _cl90ce_h_ + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl90e6.h b/userspace/sdks/nv570/nvidia/inc/class/cl90e6.h new file mode 100644 index 0000000..63348ea --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl90e6.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl90e6_h_ +#define _cl90e6_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define GF100_SUBDEVICE_MASTER (0x000090e6) + +typedef struct { + NvU32 Reserved00[0x400]; /* NV_PMC 0x00000FFF:0x00000000 */ +} Nv90e6MapTypedef, GF100MASTERMap; + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl90e6_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl90ec.h b/userspace/sdks/nv570/nvidia/inc/class/cl90ec.h new file mode 100644 index 0000000..182640a --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl90ec.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl90ec_h_ +#define _cl90ec_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* Class within the subdevice used for communicating with HDACODEC*/ +#define GF100_HDACODEC (0x000090EC) + + /* pio method data structure */ +typedef volatile struct _cl90ec_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv90ECTypedef, GF100Hdacodec; +#define NV90EC_TYPEDEF GF100Hdacodec + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl9071_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl90f1.h b/userspace/sdks/nv570/nvidia/inc/class/cl90f1.h new file mode 100644 index 0000000..7523ef1 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl90f1.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _cl90f1_h_ +#define _cl90f1_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define FERMI_VASPACE_A (0x000090f1) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl90f1_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl9170.h b/userspace/sdks/nv570/nvidia/inc/class/cl9170.h new file mode 100644 index 0000000..478125f --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl9170.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9170.finn +// + +#define NV9170_DISPLAY (0x9170U) /* finn: Evaluated from "NV9170_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV9170_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9170U) + +typedef struct NV9170_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numDacs; // Number of DACs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NV9170_ALLOCATION_PARAMETERS; diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl9171.h b/userspace/sdks/nv570/nvidia/inc/class/cl9171.h new file mode 100644 index 0000000..dcbd90b --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl9171.h @@ -0,0 +1,295 @@ +/* + * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl9171_h_ +#define _cl9171_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV9171_DISP_SF_USER 0x9171 + +typedef volatile struct _cl9171_tag0 { + NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x00690FFF:0x00690000 */ +} _Nv9171DispSfUser, Nv9171DispSfUserMap; + +#define NV9171_SF_HDMI_INFO_IDX_AVI_INFOFRAME 0x00000000 /* */ +#define NV9171_SF_HDMI_INFO_IDX_GENERIC_INFOFRAME 0x00000001 /* */ +#define NV9171_SF_HDMI_INFO_IDX_GCP 0x00000003 /* */ +#define NV9171_SF_HDMI_INFO_IDX_VSI 0x00000004 /* */ +#define NV9171_SF_HDMI_INFO_CTRL(i,j) (0x00690000-0x00690000+(i)*1024+(j)*64) /* RWX4A */ +#define NV9171_SF_HDMI_INFO_CTRL__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_INFO_CTRL__SIZE_2 5 /* */ +#define NV9171_SF_HDMI_INFO_CTRL_ENABLE 0:0 /* RWIVF */ +#define NV9171_SF_HDMI_INFO_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_INFO_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_OTHER 4:4 /* RWIVF */ +#define NV9171_SF_HDMI_INFO_CTRL_OTHER_DIS 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_INFO_CTRL_OTHER_EN 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_SINGLE 8:8 /* RWIVF */ +#define NV9171_SF_HDMI_INFO_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_INFO_CTRL_SINGLE_EN 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_CHKSUM_HW 9:9 /* RWIVF */ +#define NV9171_SF_HDMI_INFO_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_CHKSUM_HW_EN 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_CHKSUM_HW_DIS 0x00000000 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */ +#define NV9171_SF_HDMI_INFO_CTRL_HBLANK 12:12 /* RWIVF */ +#define NV9171_SF_HDMI_INFO_CTRL_HBLANK_DIS 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_INFO_CTRL_HBLANK_EN 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_VIDEO_FMT 16:16 /* RWIVF */ +#define NV9171_SF_HDMI_INFO_CTRL_VIDEO_FMT_SW_CONTROLLED 0x00000000 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_VIDEO_FMT_HW_CONTROLLED 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_INFO_CTRL_VIDEO_FMT_INIT 0x00000001 /* RWI-V */ +#define NV9171_SF_HDMI_INFO_STATUS(i,j) (0x00690004-0x00690000+(i)*1024+(j)*64) /* R--4A */ +#define NV9171_SF_HDMI_INFO_STATUS__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_INFO_STATUS__SIZE_2 5 /* */ +#define NV9171_SF_HDMI_INFO_STATUS_SENT 0:0 /* R--VF */ +#define NV9171_SF_HDMI_INFO_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NV9171_SF_HDMI_INFO_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NV9171_SF_HDMI_INFO_STATUS_SENT_INIT 0x00000000 /* R-I-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x00690000-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x00690008-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x0069000C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x00690010-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x00690014-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x00690018-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_HEADER(i) (0x00690048-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_HEADER__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_HEADER_HB0 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_HEADER_HB1 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_HEADER_HB2 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW(i) (0x0069004C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH(i) (0x00690050-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW(i) (0x00690054-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH(i) (0x00690058-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW(i) (0x0069005C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH(i) (0x00690060-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW(i) (0x00690064-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH(i) (0x00690068-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GCP_SUBPACK(i) (0x006900CC-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_GCP_SUBPACK__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_GCP_SUBPACK_SB0 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_GCP_SUBPACK_SB0_INIT 0x00000001 /* RWI-V */ +#define NV9171_SF_HDMI_GCP_SUBPACK_SB0_SET_AVMUTE 0x00000001 /* RW--V */ +#define NV9171_SF_HDMI_GCP_SUBPACK_SB0_CLR_AVMUTE 0x00000010 /* RW--V */ +#define NV9171_SF_HDMI_GCP_SUBPACK_SB1 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_GCP_SUBPACK_SB1_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_GCP_SUBPACK_SB2 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_GCP_SUBPACK_SB2_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_HEADER(i) (0x00690108-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_HEADER__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_HEADER_HB0 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_HEADER_HB1 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_HEADER_HB2 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW(i) (0x0069010C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH(i) (0x00690110-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW(i) (0x00690114-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH(i) (0x00690118-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW(i) (0x0069011C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH(i) (0x00690120-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW(i) (0x00690124-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB21 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB22 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB23 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB24 31:24 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH(i) (0x00690128-0x00690000+(i)*1024) /* RWX4A */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH__SIZE_1 4 /* */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */ +#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _cl9171_h_ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl917a.h b/userspace/sdks/nv570/nvidia/inc/class/cl917a.h new file mode 100644 index 0000000..b6d6239 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl917a.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl917a_h_ +#define _cl917a_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV917A_CURSOR_CHANNEL_PIO (0x0000917A) + +typedef volatile struct { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x1D]; + NvV32 Update; // 0x00000080 - 0x00000083 + NvV32 SetCursorHotSpotPointsOut[2]; // 0x00000084 - 0x0000008B + NvV32 Reserved02[0x3DD]; +} GK104DispCursorControlPio; + +#define NV917A_FREE (0x00000008) +#define NV917A_FREE_COUNT 5:0 +#define NV917A_UPDATE (0x00000080) +#define NV917A_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV917A_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV917A_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV917A_SET_CURSOR_HOT_SPOT_POINTS_OUT(b) (0x00000084 + (b)*0x00000004) +#define NV917A_SET_CURSOR_HOT_SPOT_POINTS_OUT_X 15:0 +#define NV917A_SET_CURSOR_HOT_SPOT_POINTS_OUT_Y 31:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl917a_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl917b.h b/userspace/sdks/nv570/nvidia/inc/class/cl917b.h new file mode 100644 index 0000000..05270e2 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl917b.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl917b_h_ +#define _cl917b_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV917B_OVERLAY_IMM_CHANNEL_PIO (0x0000917B) + +typedef volatile struct { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x1D]; + NvV32 Update; // 0x00000080 - 0x00000083 + NvV32 SetPointsOut[2]; // 0x00000084 - 0x0000008B + NvV32 Reserved02[0x1]; + NvV32 AwakenOnceFlippedTo; // 0x00000090 - 0x00000093 + NvV32 Reserved03[0x3DB]; +} GK104DispOverlayImmControlPio; + +#define NV917B_FREE (0x00000008) +#define NV917B_FREE_COUNT 5:0 +#define NV917B_UPDATE (0x00000080) +#define NV917B_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV917B_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV917B_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV917B_SET_POINTS_OUT(b) (0x00000084 + (b)*0x00000004) +#define NV917B_SET_POINTS_OUT_X 15:0 +#define NV917B_SET_POINTS_OUT_Y 31:16 +#define NV917B_AWAKEN_ONCE_FLIPPED_TO (0x00000090) +#define NV917B_AWAKEN_ONCE_FLIPPED_TO_AWAKEN_COUNT 11:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl917b_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl917c.h b/userspace/sdks/nv570/nvidia/inc/class/cl917c.h new file mode 100644 index 0000000..2b7c6a2 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl917c.h @@ -0,0 +1,298 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl917c_h_ +#define _cl917c_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV917C_BASE_CHANNEL_DMA (0x0000917C) + +#define NV_DISP_BASE_NOTIFIER_1 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1_SIZEOF 0x00000004 +#define NV_DISP_BASE_NOTIFIER_1__0 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT 15:0 +#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP 29:16 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS 31:30 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED 0x00000002 + + +#define NV_DISP_NOTIFICATION_2 0x00000000 +#define NV_DISP_NOTIFICATION_2_SIZEOF 0x00000010 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0 0x00000000 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0_NANOSECONDS0 31:0 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1 0x00000001 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1_NANOSECONDS1 31:0 +#define NV_DISP_NOTIFICATION_2_INFO32_2 0x00000002 +#define NV_DISP_NOTIFICATION_2_INFO32_2_R0 31:0 +#define NV_DISP_NOTIFICATION_2_INFO16_3 0x00000003 +#define NV_DISP_NOTIFICATION_2_INFO16_3_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_2_INFO16_3_FIELD 8:8 +#define NV_DISP_NOTIFICATION_2_INFO16_3_R1 15:9 +#define NV_DISP_NOTIFICATION_2__3_STATUS 31:16 +#define NV_DISP_NOTIFICATION_2__3_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_2__3_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_2__3_STATUS_FINISHED 0x00000000 + + +#define NV_DISP_NOTIFICATION_INFO16 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_INFO16__0 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_INFO16__0_FIELD 8:8 +#define NV_DISP_NOTIFICATION_INFO16__0_R1 15:9 + + +#define NV_DISP_NOTIFICATION_STATUS 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_STATUS__0 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS 15:0 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED 0x00000000 + + +// dma opcode instructions +#define NV917C_DMA 0x00000000 +#define NV917C_DMA_OPCODE 31:29 +#define NV917C_DMA_OPCODE_METHOD 0x00000000 +#define NV917C_DMA_OPCODE_JUMP 0x00000001 +#define NV917C_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV917C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV917C_DMA_OPCODE 31:29 +#define NV917C_DMA_OPCODE_METHOD 0x00000000 +#define NV917C_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV917C_DMA_METHOD_COUNT 27:18 +#define NV917C_DMA_METHOD_OFFSET 11:2 +#define NV917C_DMA_DATA 31:0 +#define NV917C_DMA_DATA_NOP 0x00000000 +#define NV917C_DMA_OPCODE 31:29 +#define NV917C_DMA_OPCODE_JUMP 0x00000001 +#define NV917C_DMA_JUMP_OFFSET 11:2 +#define NV917C_DMA_OPCODE 31:29 +#define NV917C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV917C_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV917C_PUT (0x00000000) +#define NV917C_PUT_PTR 11:2 +#define NV917C_GET (0x00000004) +#define NV917C_GET_PTR 11:2 +#define NV917C_GET_SCANLINE (0x00000010) +#define NV917C_GET_SCANLINE_LINE 15:0 +#define NV917C_UPDATE (0x00000080) +#define NV917C_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV917C_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV917C_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV917C_UPDATE_SPECIAL_HANDLING 25:24 +#define NV917C_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV917C_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV917C_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV917C_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV917C_SET_PRESENT_CONTROL (0x00000084) +#define NV917C_SET_PRESENT_CONTROL_BEGIN_MODE 9:8 +#define NV917C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NV917C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NV917C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE (0x00000002) +#define NV917C_SET_PRESENT_CONTROL_STEREO_FLIP_MODE 3:3 +#define NV917C_SET_PRESENT_CONTROL_STEREO_FLIP_MODE_PAIR_FLIP (0x00000000) +#define NV917C_SET_PRESENT_CONTROL_STEREO_FLIP_MODE_AT_ANY_FRAME (0x00000001) +#define NV917C_SET_PRESENT_CONTROL_TIMESTAMP_MODE 2:2 +#define NV917C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000) +#define NV917C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001) +#define NV917C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV917C_SET_PRESENT_CONTROL_BEGIN_LINE 30:16 +#define NV917C_SET_PRESENT_CONTROL_ON_LINE_MARGIN 15:10 +#define NV917C_SET_PRESENT_CONTROL_MODE 1:0 +#define NV917C_SET_PRESENT_CONTROL_MODE_MONO (0x00000000) +#define NV917C_SET_PRESENT_CONTROL_MODE_STEREO (0x00000001) +#define NV917C_SET_PRESENT_CONTROL_MODE_SPEC_FLIP (0x00000002) +#define NV917C_SET_SEMAPHORE_CONTROL (0x00000088) +#define NV917C_SET_SEMAPHORE_CONTROL_OFFSET 11:2 +#define NV917C_SET_SEMAPHORE_CONTROL_DELAY 26:26 +#define NV917C_SET_SEMAPHORE_CONTROL_DELAY_DISABLE (0x00000000) +#define NV917C_SET_SEMAPHORE_CONTROL_DELAY_ENABLE (0x00000001) +#define NV917C_SET_SEMAPHORE_CONTROL_FORMAT 28:28 +#define NV917C_SET_SEMAPHORE_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV917C_SET_SEMAPHORE_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV917C_SET_SEMAPHORE_ACQUIRE (0x0000008C) +#define NV917C_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NV917C_SET_SEMAPHORE_RELEASE (0x00000090) +#define NV917C_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NV917C_SET_CONTEXT_DMA_SEMAPHORE (0x00000094) +#define NV917C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NV917C_SET_NOTIFIER_CONTROL (0x000000A0) +#define NV917C_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV917C_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV917C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV917C_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV917C_SET_NOTIFIER_CONTROL_DELAY 26:26 +#define NV917C_SET_NOTIFIER_CONTROL_DELAY_DISABLE (0x00000000) +#define NV917C_SET_NOTIFIER_CONTROL_DELAY_ENABLE (0x00000001) +#define NV917C_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV917C_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV917C_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV917C_SET_CONTEXT_DMA_NOTIFIER (0x000000A4) +#define NV917C_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV917C_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0x00000004) +#define NV917C_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV917C_SET_BASE_LUT_LO (0x000000E0) +#define NV917C_SET_BASE_LUT_LO_ENABLE 31:30 +#define NV917C_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV917C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001) +#define NV917C_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000002) +#define NV917C_SET_BASE_LUT_LO_MODE 27:24 +#define NV917C_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV917C_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV917C_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV917C_SET_BASE_LUT_HI (0x000000E4) +#define NV917C_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV917C_SET_OUTPUT_LUT_LO (0x000000E8) +#define NV917C_SET_OUTPUT_LUT_LO_ENABLE 31:30 +#define NV917C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV917C_SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001) +#define NV917C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000002) +#define NV917C_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV917C_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV917C_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV917C_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV917C_SET_OUTPUT_LUT_HI (0x000000EC) +#define NV917C_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV917C_SET_CONTEXT_DMA_LUT (0x000000FC) +#define NV917C_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV917C_SET_PROCESSING (0x00000110) +#define NV917C_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV917C_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV917C_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV917C_SET_CONVERSION_RED (0x00000114) +#define NV917C_SET_CONVERSION_RED_GAIN 15:0 +#define NV917C_SET_CONVERSION_RED_OFS 31:16 +#define NV917C_SET_CONVERSION_GRN (0x00000118) +#define NV917C_SET_CONVERSION_GRN_GAIN 15:0 +#define NV917C_SET_CONVERSION_GRN_OFS 31:16 +#define NV917C_SET_CONVERSION_BLU (0x0000011C) +#define NV917C_SET_CONVERSION_BLU_GAIN 15:0 +#define NV917C_SET_CONVERSION_BLU_OFS 31:16 +#define NV917C_SET_TIMESTAMP_ORIGIN_LO (0x00000130) +#define NV917C_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NV917C_SET_TIMESTAMP_ORIGIN_HI (0x00000134) +#define NV917C_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NV917C_SET_UPDATE_TIMESTAMP_LO (0x00000138) +#define NV917C_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NV917C_SET_UPDATE_TIMESTAMP_HI (0x0000013C) +#define NV917C_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NV917C_SET_CSC_RED2RED (0x00000140) +#define NV917C_SET_CSC_RED2RED_OWNER 31:31 +#define NV917C_SET_CSC_RED2RED_OWNER_CORE (0x00000000) +#define NV917C_SET_CSC_RED2RED_OWNER_BASE (0x00000001) +#define NV917C_SET_CSC_RED2RED_COEFF 18:0 +#define NV917C_SET_CSC_GRN2RED (0x00000144) +#define NV917C_SET_CSC_GRN2RED_COEFF 18:0 +#define NV917C_SET_CSC_BLU2RED (0x00000148) +#define NV917C_SET_CSC_BLU2RED_COEFF 18:0 +#define NV917C_SET_CSC_CONSTANT2RED (0x0000014C) +#define NV917C_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV917C_SET_CSC_RED2GRN (0x00000150) +#define NV917C_SET_CSC_RED2GRN_COEFF 18:0 +#define NV917C_SET_CSC_GRN2GRN (0x00000154) +#define NV917C_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV917C_SET_CSC_BLU2GRN (0x00000158) +#define NV917C_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV917C_SET_CSC_CONSTANT2GRN (0x0000015C) +#define NV917C_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV917C_SET_CSC_RED2BLU (0x00000160) +#define NV917C_SET_CSC_RED2BLU_COEFF 18:0 +#define NV917C_SET_CSC_GRN2BLU (0x00000164) +#define NV917C_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV917C_SET_CSC_BLU2BLU (0x00000168) +#define NV917C_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV917C_SET_CSC_CONSTANT2BLU (0x0000016C) +#define NV917C_SET_CSC_CONSTANT2BLU_COEFF 18:0 +#define NV917C_SET_SPARE (0x000003BC) +#define NV917C_SET_SPARE_UNUSED 31:0 +#define NV917C_SET_SPARE_NOOP(b) (0x000003C0 + (b)*0x00000004) +#define NV917C_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV917C_SURFACE_SET_OFFSET(a,b) (0x00000400 + (a)*0x00000020 + (b)*0x00000004) +#define NV917C_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV917C_SURFACE_SET_SIZE(a) (0x00000408 + (a)*0x00000020) +#define NV917C_SURFACE_SET_SIZE_WIDTH 15:0 +#define NV917C_SURFACE_SET_SIZE_HEIGHT 31:16 +#define NV917C_SURFACE_SET_STORAGE(a) (0x0000040C + (a)*0x00000020) +#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV917C_SURFACE_SET_STORAGE_PITCH 20:8 +#define NV917C_SURFACE_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV917C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV917C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV917C_SURFACE_SET_PARAMS(a) (0x00000410 + (a)*0x00000020) +#define NV917C_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV917C_SURFACE_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV917C_SURFACE_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV917C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV917C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV917C_SURFACE_SET_PARAMS_GAMMA 2:2 +#define NV917C_SURFACE_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV917C_SURFACE_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV917C_SURFACE_SET_PARAMS_LAYOUT 5:4 +#define NV917C_SURFACE_SET_PARAMS_LAYOUT_FRM (0x00000000) +#define NV917C_SURFACE_SET_PARAMS_LAYOUT_FLD1 (0x00000001) +#define NV917C_SURFACE_SET_PARAMS_LAYOUT_FLD2 (0x00000002) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl917c_h diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl917cswspare.h b/userspace/sdks/nv570/nvidia/inc/class/cl917cswspare.h new file mode 100644 index 0000000..39e88c0 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl917cswspare.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl917c_sw_spare_h_ +#define _cl917c_sw_spare_h_ + +/* This file is *not* auto-generated. */ + +/* NV917C_SET_SPARE_PRE_UPDATE_TRAP is an alias of NV917C_SET_SPARE_NOOP(0) */ +#define NV917C_SET_SPARE_PRE_UPDATE_TRAP (0x000003C0) +#define NV917C_SET_SPARE_PRE_UPDATE_TRAP_UNUSED 31:0 + +/* NV917C_SET_SPARE_POST_UPDATE_TRAP is an alias of NV917C_SET_SPARE_NOOP(1) */ +#define NV917C_SET_SPARE_POST_UPDATE_TRAP (0x000003C4) +#define NV917C_SET_SPARE_POST_UPDATE_TRAP_UNUSED 31:0 + + +#endif /* _cl917c_sw_spare_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl917d.h b/userspace/sdks/nv570/nvidia/inc/class/cl917d.h new file mode 100644 index 0000000..4f70d81 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl917d.h @@ -0,0 +1,1551 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl917d_h_ +#define _cl917d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV917D_CORE_CHANNEL_DMA (0x0000917D) + +#define NV917D_CORE_NOTIFIER_3 0x00000000 +#define NV917D_CORE_NOTIFIER_3_SIZEOF 0x00000150 +#define NV917D_CORE_NOTIFIER_3_COMPLETION_0 0x00000000 +#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_DONE 0:0 +#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_R0 15:1 +#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP 29:16 +#define NV917D_CORE_NOTIFIER_3__1 0x00000001 +#define NV917D_CORE_NOTIFIER_3__1_R1 31:0 +#define NV917D_CORE_NOTIFIER_3__2 0x00000002 +#define NV917D_CORE_NOTIFIER_3__2_R2 31:0 +#define NV917D_CORE_NOTIFIER_3__3 0x00000003 +#define NV917D_CORE_NOTIFIER_3__3_R3 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_R0 19:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA 20:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_R1 29:21 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE 30:30 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5 0x00000005 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE 3:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE 11:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE 15:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE 19:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE 27:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE 31:28 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6 0x00000006 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE 3:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE 11:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE 15:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE 19:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE 27:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE 31:28 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_UNAVAILABLE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_SCAN_LOCK 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_FLIP_LOCK 0x00000002 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_STEREO 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_7 0x00000007 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_7_R4 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_8 0x00000008 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_8_R5 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_9 0x00000009 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_9_R6 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_10 0x0000000A +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_10_R7 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_11 0x0000000B +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_11_R8 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12 0x0000000C +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0 31:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13 0x0000000D +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14 0x0000000E +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0 31:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15 0x0000000F +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16 0x00000010 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0 31:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17 0x00000011 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18 0x00000012 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0 31:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19 0x00000013 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21 0x00000015 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22 0x00000016 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23 0x00000017 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24 0x00000018 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25 0x00000019 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26 0x0000001A +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27 0x0000001B +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28 0x0000001C +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29 0x0000001D +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30 0x0000001E +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31 0x0000001F +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32 0x00000020 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33 0x00000021 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34 0x00000022 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35 0x00000023 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36 0x00000024 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0 31:7 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37 0x00000025 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38 0x00000026 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0 31:7 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39 0x00000027 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40 0x00000028 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0 31:7 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41 0x00000029 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42 0x0000002A +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0 31:7 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43 0x0000002B +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44 0x0000002C +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45 0x0000002D +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45_R1 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46 0x0000002E +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47 0x0000002F +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47_R1 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48 0x00000030 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49 0x00000031 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49_R1 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50 0x00000032 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51 0x00000033 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51_R1 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52 0x00000034 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53 0x00000035 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54 0x00000036 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55 0x00000037 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56 0x00000038 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57 0x00000039 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58 0x0000003A +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59 0x0000003B +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60 0x0000003C +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61 0x0000003D +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62 0x0000003E +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63 0x0000003F +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64 0x00000040 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65 0x00000041 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66 0x00000042 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67 0x00000043 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68 0x00000044 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69 0x00000045 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70 0x00000046 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71 0x00000047 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72 0x00000048 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73 0x00000049 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74 0x0000004A +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75 0x0000004B +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76 0x0000004C +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77 0x0000004D +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78 0x0000004E +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79 0x0000004F +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80 0x00000050 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81 0x00000051 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82 0x00000052 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83 0x00000053 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10 31:0 + + +// dma opcode instructions +#define NV917D_DMA 0x00000000 +#define NV917D_DMA_OPCODE 31:29 +#define NV917D_DMA_OPCODE_METHOD 0x00000000 +#define NV917D_DMA_OPCODE_JUMP 0x00000001 +#define NV917D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV917D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV917D_DMA_OPCODE 31:29 +#define NV917D_DMA_OPCODE_METHOD 0x00000000 +#define NV917D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV917D_DMA_METHOD_COUNT 27:18 +#define NV917D_DMA_METHOD_OFFSET 11:2 +#define NV917D_DMA_DATA 31:0 +#define NV917D_DMA_DATA_NOP 0x00000000 +#define NV917D_DMA_OPCODE 31:29 +#define NV917D_DMA_OPCODE_JUMP 0x00000001 +#define NV917D_DMA_JUMP_OFFSET 11:2 +#define NV917D_DMA_OPCODE 31:29 +#define NV917D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV917D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV917D_PUT (0x00000000) +#define NV917D_PUT_PTR 11:2 +#define NV917D_GET (0x00000004) +#define NV917D_GET_PTR 11:2 +#define NV917D_UPDATE (0x00000080) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR(i) (0 +(i)*4):(0 +(i)*4) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1 4 +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0 +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR1 4:4 +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR2 8:8 +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR3 12:12 +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE(i) (1 +(i)*4):(1 +(i)*4) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1 4 +#define NV917D_UPDATE_INTERLOCK_WITH_BASE_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE0 1:1 +#define NV917D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE1 5:5 +#define NV917D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE2 9:9 +#define NV917D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE3 13:13 +#define NV917D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY(i) (2 +(i)*4):(2 +(i)*4) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1 4 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY1 6:6 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY2 10:10 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY3 14:14 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i) (3 +(i)*4):(3 +(i)*4) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1 4 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 7:7 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2 11:11 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3 15:15 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE (0x00000001) +#define NV917D_UPDATE_SPECIAL_HANDLING 25:24 +#define NV917D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV917D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV917D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV917D_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV917D_UPDATE_NOT_DRIVER_FRIENDLY 31:31 +#define NV917D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000) +#define NV917D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001) +#define NV917D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30 +#define NV917D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000) +#define NV917D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001) +#define NV917D_UPDATE_INHIBIT_INTERRUPTS 29:29 +#define NV917D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NV917D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NV917D_SET_NOTIFIER_CONTROL (0x00000084) +#define NV917D_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV917D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV917D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV917D_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV917D_SET_NOTIFIER_CONTROL_NOTIFY 31:31 +#define NV917D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NV917D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NV917D_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV917D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV917D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV917D_SET_CONTEXT_DMA_NOTIFIER (0x00000088) +#define NV917D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV917D_GET_CAPABILITIES (0x0000008C) +#define NV917D_GET_CAPABILITIES_DUMMY 31:0 +#define NV917D_SET_SPARE (0x0000016C) +#define NV917D_SET_SPARE_UNUSED 31:0 +#define NV917D_SET_SPARE_NOOP(b) (0x00000170 + (b)*0x00000004) +#define NV917D_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV917D_DAC_SET_CONTROL(a) (0x00000180 + (a)*0x00000020) +#define NV917D_DAC_SET_CONTROL_OWNER_MASK 3:0 +#define NV917D_DAC_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV917D_DAC_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV917D_DAC_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV917D_DAC_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV917D_DAC_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV917D_DAC_SET_CONTROL_PROTOCOL 12:8 +#define NV917D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV917D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT (0x00000013) +#define NV917D_DAC_SET_SW_SPARE_A(a) (0x00000184 + (a)*0x00000020) +#define NV917D_DAC_SET_SW_SPARE_A_CODE 31:0 +#define NV917D_DAC_SET_SW_SPARE_B(a) (0x00000188 + (a)*0x00000020) +#define NV917D_DAC_SET_SW_SPARE_B_CODE 31:0 +#define NV917D_DAC_SET_CUSTOM_REASON(a) (0x00000190 + (a)*0x00000020) +#define NV917D_DAC_SET_CUSTOM_REASON_CODE 31:0 + +#define NV917D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV917D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV917D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NV917D_SOR_SET_SW_SPARE_A(a) (0x00000204 + (a)*0x00000020) +#define NV917D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NV917D_SOR_SET_SW_SPARE_B(a) (0x00000208 + (a)*0x00000020) +#define NV917D_SOR_SET_SW_SPARE_B_CODE 31:0 +#define NV917D_SOR_SET_CUSTOM_REASON(a) (0x00000210 + (a)*0x00000020) +#define NV917D_SOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV917D_PIOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NV917D_PIOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV917D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV917D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV917D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV917D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV917D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV917D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV917D_PIOR_SET_SW_SPARE_A(a) (0x00000304 + (a)*0x00000020) +#define NV917D_PIOR_SET_SW_SPARE_A_CODE 31:0 +#define NV917D_PIOR_SET_SW_SPARE_B(a) (0x00000308 + (a)*0x00000020) +#define NV917D_PIOR_SET_SW_SPARE_B_CODE 31:0 +#define NV917D_PIOR_SET_CUSTOM_REASON(a) (0x00000310 + (a)*0x00000020) +#define NV917D_PIOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV917D_HEAD_SET_PRESENT_CONTROL(a) (0x00000400 + (a)*0x00000300) +#define NV917D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NV917D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 8:8 +#define NV917D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NV917D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NV917D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00000404 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 3:3 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 4:4 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 9:6 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000009) +#define NV917D_HEAD_SET_CONTROL(a) (0x00000408 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTROL_STRUCTURE 0:0 +#define NV917D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 3:2 +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 19:15 +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV917D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 7:4 +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 9:8 +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 14:10 +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV917D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK 1:1 +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_ENABLE (0x00000001) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN 24:20 +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV917D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN 29:25 +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000003) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000004) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000005) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000006) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000007) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000008) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x00000009) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000A) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000B) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000C) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000D) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000E) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x0000000F) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_UNSPECIFIED (0x00000010) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV917D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV917D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NV917D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NV917D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000410 + (a)*0x00000300) +#define NV917D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV917D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV917D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV917D_HEAD_SET_RASTER_SIZE(a) (0x00000414 + (a)*0x00000300) +#define NV917D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV917D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV917D_HEAD_SET_RASTER_SYNC_END(a) (0x00000418 + (a)*0x00000300) +#define NV917D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV917D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV917D_HEAD_SET_RASTER_BLANK_END(a) (0x0000041C + (a)*0x00000300) +#define NV917D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV917D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV917D_HEAD_SET_RASTER_BLANK_START(a) (0x00000420 + (a)*0x00000300) +#define NV917D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV917D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV917D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000424 + (a)*0x00000300) +#define NV917D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV917D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV917D_HEAD_SET_LOCK_CHAIN(a) (0x00000428 + (a)*0x00000300) +#define NV917D_HEAD_SET_LOCK_CHAIN_POSITION 27:24 +#define NV917D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000042C + (a)*0x00000300) +#define NV917D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV917D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV917D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV917D_HEAD_SET_CRC_CONTROL(a) (0x00000430 + (a)*0x00000300) +#define NV917D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 1:0 +#define NV917D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000000) +#define NV917D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_BASE (0x00000001) +#define NV917D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_OVERLAY (0x00000002) +#define NV917D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 2:2 +#define NV917D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NV917D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NV917D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE 3:3 +#define NV917D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_FALSE (0x00000000) +#define NV917D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_TRUE (0x00000001) +#define NV917D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE 4:4 +#define NV917D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_FALSE (0x00000000) +#define NV917D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_TRUE (0x00000001) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT 19:8 +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC__SIZE_1 4 +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC0 (0x00000FF0) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC1 (0x00000FF1) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC2 (0x00000FF2) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC3 (0x00000FF3) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG__SIZE_1 4 +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG0 (0x00000FF8) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG1 (0x00000FF9) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG2 (0x00000FFA) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG3 (0x00000FFB) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR__SIZE_1 8 +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR0 (0x00000F0F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR1 (0x00000F1F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR2 (0x00000F2F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR3 (0x00000F3F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR4 (0x00000F4F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR5 (0x00000F5F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR6 (0x00000F6F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR7 (0x00000F7F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF__SIZE_1 4 +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF0 (0x00000F8F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF1 (0x00000F9F) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF2 (0x00000FAF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF3 (0x00000FBF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR__SIZE_1 8 +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR0 (0x000000FF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR1 (0x000001FF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR2 (0x000002FF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR3 (0x000003FF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR4 (0x000004FF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR5 (0x000005FF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR6 (0x000006FF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR7 (0x000007FF) +#define NV917D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_NONE (0x00000FFF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT 31:20 +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC__SIZE_1 4 +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC0 (0x00000FF0) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC1 (0x00000FF1) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC2 (0x00000FF2) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC3 (0x00000FF3) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG__SIZE_1 4 +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG0 (0x00000FF8) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG1 (0x00000FF9) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG2 (0x00000FFA) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG3 (0x00000FFB) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR__SIZE_1 8 +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR0 (0x00000F0F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR1 (0x00000F1F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR2 (0x00000F2F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR3 (0x00000F3F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR4 (0x00000F4F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR5 (0x00000F5F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR6 (0x00000F6F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR7 (0x00000F7F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF__SIZE_1 4 +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF0 (0x00000F8F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF1 (0x00000F9F) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF2 (0x00000FAF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF3 (0x00000FBF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR__SIZE_1 8 +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR0 (0x000000FF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR1 (0x000001FF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR2 (0x000002FF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR3 (0x000003FF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR4 (0x000004FF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR5 (0x000005FF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR6 (0x000006FF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR7 (0x000007FF) +#define NV917D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_NONE (0x00000FFF) +#define NV917D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 5:5 +#define NV917D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC 6:6 +#define NV917D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_ENABLE (0x00000001) +#define NV917D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00000438 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NV917D_HEAD_SET_BASE_LUT_LO(a) (0x00000440 + (a)*0x00000300) +#define NV917D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV917D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE 27:24 +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV917D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV917D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_BASE_LUT_HI(a) (0x00000444 + (a)*0x00000300) +#define NV917D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV917D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000448 + (a)*0x00000300) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000044C + (a)*0x00000300) +#define NV917D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x00000450 + (a)*0x00000300) +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x00000454 + (a)*0x00000300) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE 21:20 +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25 (0x00000000) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28 (0x00000001) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM (0x00000002) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 24:24 +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING 25:25 +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE (0x00000000) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE (0x00000001) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 26:26 +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00000458 + (a)*0x00000300) +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NV917D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000045C + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV917D_HEAD_SET_OFFSET(a) (0x00000460 + (a)*0x00000300) +#define NV917D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV917D_HEAD_SET_SIZE(a) (0x00000468 + (a)*0x00000300) +#define NV917D_HEAD_SET_SIZE_WIDTH 15:0 +#define NV917D_HEAD_SET_SIZE_HEIGHT 31:16 +#define NV917D_HEAD_SET_STORAGE(a) (0x0000046C + (a)*0x00000300) +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV917D_HEAD_SET_STORAGE_PITCH 20:8 +#define NV917D_HEAD_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV917D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV917D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV917D_HEAD_SET_PARAMS(a) (0x00000470 + (a)*0x00000300) +#define NV917D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV917D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV917D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV917D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV917D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV917D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV917D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV917D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV917D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV917D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV917D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV917D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV917D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV917D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV917D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV917D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV917D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV917D_HEAD_SET_PARAMS_GAMMA 2:2 +#define NV917D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV917D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV917D_HEAD_SET_CONTEXT_DMAS_ISO(a) (0x00000474 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV917D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x0000047C + (a)*0x00000300) +#define NV917D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 1:0 +#define NV917D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NV917D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NV917D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_SPEC_FLIP (0x00000002) +#define NV917D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE 27:26 +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NV917D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 15:8 +#define NV917D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 23:16 +#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV917D_HEAD_SET_OFFSETS_CURSOR(a,b) (0x00000484 + (a)*0x00000300 + (b)*0x00000004) +#define NV917D_HEAD_SET_OFFSETS_CURSOR_ORIGIN 31:0 +#define NV917D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b) (0x0000048C + (a)*0x00000300 + (b)*0x00000004) +#define NV917D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE 31:0 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00000494 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422 8:8 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE (0x00000001) +#define NV917D_HEAD_SET_PROCAMP(a) (0x00000498 + (a)*0x00000300) +#define NV917D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV917D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV917D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV917D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV917D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV917D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV917D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV917D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV917D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV917D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 5:5 +#define NV917D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NV917D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NV917D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 6:6 +#define NV917D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) +#define NV917D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) +#define NV917D_HEAD_SET_DITHER_CONTROL(a) (0x000004A0 + (a)*0x00000300) +#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NV917D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV917D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x000004B0 + (a)*0x00000300) +#define NV917D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV917D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000004B8 + (a)*0x00000300) +#define NV917D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV917D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x000004BC + (a)*0x00000300) +#define NV917D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NV917D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000004C0 + (a)*0x00000300) +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000004C4 + (a)*0x00000300) +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a) (0x000004C8 + (a)*0x00000300) +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH 14:0 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT 30:16 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT 17:16 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257 (0x00000001) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025 (0x00000002) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT 21:20 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x000004D4 + (a)*0x00000300) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT 13:12 +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE (0x00000000) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257 (0x00000001) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025 (0x00000002) +#define NV917D_HEAD_SET_PROCESSING(a) (0x000004E0 + (a)*0x00000300) +#define NV917D_HEAD_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV917D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV917D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV917D_HEAD_SET_CONVERSION_RED(a) (0x000004E4 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONVERSION_RED_GAIN 15:0 +#define NV917D_HEAD_SET_CONVERSION_RED_OFS 31:16 +#define NV917D_HEAD_SET_CONVERSION_GRN(a) (0x000004E8 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONVERSION_GRN_GAIN 15:0 +#define NV917D_HEAD_SET_CONVERSION_GRN_OFS 31:16 +#define NV917D_HEAD_SET_CONVERSION_BLU(a) (0x000004EC + (a)*0x00000300) +#define NV917D_HEAD_SET_CONVERSION_BLU_GAIN 15:0 +#define NV917D_HEAD_SET_CONVERSION_BLU_OFS 31:16 +#define NV917D_HEAD_SET_CSC_RED2RED(a) (0x000004F0 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE 31:31 +#define NV917D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_CSC_RED2RED_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_GRN2RED(a) (0x000004F4 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_GRN2RED_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_BLU2RED(a) (0x000004F8 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_BLU2RED_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_CONSTANT2RED(a) (0x000004FC + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_RED2GRN(a) (0x00000500 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_RED2GRN_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_GRN2GRN(a) (0x00000504 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_BLU2GRN(a) (0x00000508 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_CONSTANT2GRN(a) (0x0000050C + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_RED2BLU(a) (0x00000510 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_RED2BLU_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_GRN2BLU(a) (0x00000514 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_BLU2BLU(a) (0x00000518 + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV917D_HEAD_SET_CSC_CONSTANT2BLU(a) (0x0000051C + (a)*0x00000300) +#define NV917D_HEAD_SET_CSC_CONSTANT2BLU_COEFF 18:0 +#define NV917D_HEAD_SET_HDMI_CTRL(a) (0x00000520 + (a)*0x00000300) +#define NV917D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NV917D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NV917D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NV917D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NV917D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE 15:12 +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000000) +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FIELD_ALTERNATIVE (0x00000001) +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_LINE_ALTERNATIVE (0x00000002) +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_FULL (0x00000003) +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH (0x00000004) +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH_GRAPHICS (0x00000005) +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_TOP_AND_BOTTOM (0x00000006) +#define NV917D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_HALF (0x00000008) +#define NV917D_HEAD_SET_VACTIVE_SPACE_COLOR(a) (0x00000524 + (a)*0x00000300) +#define NV917D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR 9:0 +#define NV917D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y 19:10 +#define NV917D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB 29:20 +#define NV917D_HEAD_SET_DISPLAY_ID(a,b) (0x0000052C + (a)*0x00000300 + (b)*0x00000004) +#define NV917D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NV917D_HEAD_SET_SW_SPARE_A(a) (0x0000054C + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NV917D_HEAD_SET_SW_SPARE_B(a) (0x00000550 + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NV917D_HEAD_SET_SW_SPARE_C(a) (0x00000554 + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NV917D_HEAD_SET_SW_SPARE_D(a) (0x00000558 + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NV917D_HEAD_SET_GET_BLANKING_CTRL(a) (0x0000055C + (a)*0x00000300) +#define NV917D_HEAD_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NV917D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NV917D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NV917D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NV917D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NV917D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a) (0x000006D0 + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED 31:0 +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a) (0x000006D4 + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED 31:0 +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a) (0x000006D8 + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED 31:0 +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a) (0x000006DC + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED 31:0 +#define NV917D_HEAD_SET_SPARE(a) (0x000006EC + (a)*0x00000300) +#define NV917D_HEAD_SET_SPARE_UNUSED 31:0 +#define NV917D_HEAD_SET_SPARE_NOOP(a,b) (0x000006F0 + (a)*0x00000300 + (b)*0x00000004) +#define NV917D_HEAD_SET_SPARE_NOOP_UNUSED 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl917d_h diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl917dcrcnotif.h b/userspace/sdks/nv570/nvidia/inc/class/cl917dcrcnotif.h new file mode 100644 index 0000000..9abc605 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl917dcrcnotif.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2003-2010, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __cl917dcrcnotif_h__ +#define __cl917dcrcnotif_h__ +/* This file is autogenerated. Do not edit */ + +#define NV917D_NOTIFIER_CRC_1_STATUS_0 0x00000000 +#define NV917D_NOTIFIER_CRC_1_STATUS_0_DONE 0:0 +#define NV917D_NOTIFIER_CRC_1_STATUS_0_DONE_FALSE 0x00000000 +#define NV917D_NOTIFIER_CRC_1_STATUS_0_DONE_TRUE 0x00000001 +#define NV917D_NOTIFIER_CRC_1_STATUS_0_COMPOSITOR_OVERFLOW 3:3 +#define NV917D_NOTIFIER_CRC_1_STATUS_0_COMPOSITOR_OVERFLOW_FALSE 0x00000000 +#define NV917D_NOTIFIER_CRC_1_STATUS_0_COMPOSITOR_OVERFLOW_TRUE 0x00000001 +#define NV917D_NOTIFIER_CRC_1_STATUS_0_PRIMARY_OUTPUT_OVERFLOW 4:4 +#define NV917D_NOTIFIER_CRC_1_STATUS_0_PRIMARY_OUTPUT_OVERFLOW_FALSE 0x00000000 +#define NV917D_NOTIFIER_CRC_1_STATUS_0_PRIMARY_OUTPUT_OVERFLOW_TRUE 0x00000001 +#define NV917D_NOTIFIER_CRC_1_STATUS_0_COUNT 31:24 +#define NV917D_NOTIFIER_CRC_1_CRC_ENTRY0_3 0x00000003 +#define NV917D_NOTIFIER_CRC_1_CRC_ENTRY0_3_COMPOSITOR_CRC 31:0 +#define NV917D_NOTIFIER_CRC_1_CRC_ENTRY0_4 0x00000004 +#define NV917D_NOTIFIER_CRC_1_CRC_ENTRY0_4_PRIMARY_OUTPUT_CRC 31:0 +#define NV917D_NOTIFIER_CRC_1_CRC_ENTRY1_8 0x00000008 + +#endif // __cl917dcrcnotif_h__ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl917e.h b/userspace/sdks/nv570/nvidia/inc/class/cl917e.h new file mode 100644 index 0000000..6586bda --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl917e.h @@ -0,0 +1,265 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl917e_h_ +#define _cl917e_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV917E_OVERLAY_CHANNEL_DMA (0x0000917E) + +#define NV_DISP_NOTIFICATION_2 0x00000000 +#define NV_DISP_NOTIFICATION_2_SIZEOF 0x00000010 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0 0x00000000 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0_NANOSECONDS0 31:0 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1 0x00000001 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1_NANOSECONDS1 31:0 +#define NV_DISP_NOTIFICATION_2_INFO32_2 0x00000002 +#define NV_DISP_NOTIFICATION_2_INFO32_2_R0 31:0 +#define NV_DISP_NOTIFICATION_2_INFO16_3 0x00000003 +#define NV_DISP_NOTIFICATION_2_INFO16_3_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_2_INFO16_3_FIELD 8:8 +#define NV_DISP_NOTIFICATION_2_INFO16_3_R1 15:9 +#define NV_DISP_NOTIFICATION_2__3_STATUS 31:16 +#define NV_DISP_NOTIFICATION_2__3_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_2__3_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_2__3_STATUS_FINISHED 0x00000000 + + +#define NV_DISP_NOTIFICATION_INFO16 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_INFO16__0 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_INFO16__0_FIELD 8:8 +#define NV_DISP_NOTIFICATION_INFO16__0_R1 15:9 + + +#define NV_DISP_NOTIFICATION_STATUS 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_STATUS__0 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS 15:0 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED 0x00000000 + + +// dma opcode instructions +#define NV917E_DMA 0x00000000 +#define NV917E_DMA_OPCODE 31:29 +#define NV917E_DMA_OPCODE_METHOD 0x00000000 +#define NV917E_DMA_OPCODE_JUMP 0x00000001 +#define NV917E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV917E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV917E_DMA_OPCODE 31:29 +#define NV917E_DMA_OPCODE_METHOD 0x00000000 +#define NV917E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV917E_DMA_METHOD_COUNT 27:18 +#define NV917E_DMA_METHOD_OFFSET 11:2 +#define NV917E_DMA_DATA 31:0 +#define NV917E_DMA_DATA_NOP 0x00000000 +#define NV917E_DMA_OPCODE 31:29 +#define NV917E_DMA_OPCODE_JUMP 0x00000001 +#define NV917E_DMA_JUMP_OFFSET 11:2 +#define NV917E_DMA_OPCODE 31:29 +#define NV917E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV917E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV917E_PUT (0x00000000) +#define NV917E_PUT_PTR 11:2 +#define NV917E_GET (0x00000004) +#define NV917E_GET_PTR 11:2 +#define NV917E_UPDATE (0x00000080) +#define NV917E_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV917E_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV917E_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV917E_UPDATE_SPECIAL_HANDLING 25:24 +#define NV917E_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV917E_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV917E_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV917E_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV917E_SET_PRESENT_CONTROL (0x00000084) +#define NV917E_SET_PRESENT_CONTROL_BEGIN_MODE 1:0 +#define NV917E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP (0x00000000) +#define NV917E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP (0x00000003) +#define NV917E_SET_PRESENT_CONTROL_STEREO_FLIP_MODE 3:3 +#define NV917E_SET_PRESENT_CONTROL_STEREO_FLIP_MODE_PAIR_FLIP (0x00000000) +#define NV917E_SET_PRESENT_CONTROL_STEREO_FLIP_MODE_AT_ANY_FRAME (0x00000001) +#define NV917E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV917E_SET_PRESENT_CONTROL_MODE 11:10 +#define NV917E_SET_PRESENT_CONTROL_MODE_MONO (0x00000000) +#define NV917E_SET_PRESENT_CONTROL_MODE_STEREO (0x00000001) +#define NV917E_SET_PRESENT_CONTROL_MODE_SPEC_FLIP (0x00000002) +#define NV917E_SET_SEMAPHORE_ACQUIRE (0x00000088) +#define NV917E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NV917E_SET_SEMAPHORE_RELEASE (0x0000008C) +#define NV917E_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NV917E_SET_SEMAPHORE_CONTROL (0x00000090) +#define NV917E_SET_SEMAPHORE_CONTROL_OFFSET 11:2 +#define NV917E_SET_SEMAPHORE_CONTROL_FORMAT 28:28 +#define NV917E_SET_SEMAPHORE_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV917E_SET_SEMAPHORE_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV917E_SET_CONTEXT_DMA_SEMAPHORE (0x00000094) +#define NV917E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NV917E_SET_NOTIFIER_CONTROL (0x000000A0) +#define NV917E_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV917E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV917E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV917E_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV917E_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV917E_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV917E_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV917E_SET_CONTEXT_DMA_NOTIFIER (0x000000A4) +#define NV917E_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV917E_SET_CONTEXT_DMA_LUT (0x000000B0) +#define NV917E_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV917E_SET_OVERLAY_LUT_LO (0x000000B4) +#define NV917E_SET_OVERLAY_LUT_LO_ENABLE 31:31 +#define NV917E_SET_OVERLAY_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV917E_SET_OVERLAY_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV917E_SET_OVERLAY_LUT_LO_MODE 27:24 +#define NV917E_SET_OVERLAY_LUT_LO_MODE_LORES (0x00000000) +#define NV917E_SET_OVERLAY_LUT_LO_MODE_HIRES (0x00000001) +#define NV917E_SET_OVERLAY_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV917E_SET_OVERLAY_LUT_HI (0x000000B8) +#define NV917E_SET_OVERLAY_LUT_HI_ORIGIN 31:0 +#define NV917E_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0x00000004) +#define NV917E_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV917E_SET_POINT_IN (0x000000E0) +#define NV917E_SET_POINT_IN_X 14:0 +#define NV917E_SET_POINT_IN_Y 30:16 +#define NV917E_SET_SIZE_IN (0x000000E4) +#define NV917E_SET_SIZE_IN_WIDTH 14:0 +#define NV917E_SET_SIZE_IN_HEIGHT 30:16 +#define NV917E_SET_SIZE_OUT (0x000000E8) +#define NV917E_SET_SIZE_OUT_WIDTH 14:0 +#define NV917E_SET_COMPOSITION_CONTROL (0x00000100) +#define NV917E_SET_COMPOSITION_CONTROL_MODE 3:0 +#define NV917E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING (0x00000000) +#define NV917E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING (0x00000001) +#define NV917E_SET_COMPOSITION_CONTROL_MODE_OPAQUE (0x00000002) +#define NV917E_SET_KEY_COLOR_LO (0x00000104) +#define NV917E_SET_KEY_COLOR_LO_COLOR 31:0 +#define NV917E_SET_KEY_COLOR_HI (0x00000108) +#define NV917E_SET_KEY_COLOR_HI_COLOR 31:0 +#define NV917E_SET_KEY_MASK_LO (0x0000010C) +#define NV917E_SET_KEY_MASK_LO_MASK 31:0 +#define NV917E_SET_KEY_MASK_HI (0x00000110) +#define NV917E_SET_KEY_MASK_HI_MASK 31:0 +#define NV917E_SET_PROCESSING (0x00000118) +#define NV917E_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV917E_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV917E_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV917E_SET_CONVERSION_RED (0x0000011C) +#define NV917E_SET_CONVERSION_RED_GAIN 15:0 +#define NV917E_SET_CONVERSION_RED_OFS 31:16 +#define NV917E_SET_CONVERSION_GRN (0x00000120) +#define NV917E_SET_CONVERSION_GRN_GAIN 15:0 +#define NV917E_SET_CONVERSION_GRN_OFS 31:16 +#define NV917E_SET_CONVERSION_BLU (0x00000124) +#define NV917E_SET_CONVERSION_BLU_GAIN 15:0 +#define NV917E_SET_CONVERSION_BLU_OFS 31:16 +#define NV917E_SET_TIMESTAMP_ORIGIN_LO (0x00000130) +#define NV917E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NV917E_SET_TIMESTAMP_ORIGIN_HI (0x00000134) +#define NV917E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NV917E_SET_UPDATE_TIMESTAMP_LO (0x00000138) +#define NV917E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NV917E_SET_UPDATE_TIMESTAMP_HI (0x0000013C) +#define NV917E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NV917E_SET_CSC_RED2RED (0x00000140) +#define NV917E_SET_CSC_RED2RED_COEFF 18:0 +#define NV917E_SET_CSC_GRN2RED (0x00000144) +#define NV917E_SET_CSC_GRN2RED_COEFF 18:0 +#define NV917E_SET_CSC_BLU2RED (0x00000148) +#define NV917E_SET_CSC_BLU2RED_COEFF 18:0 +#define NV917E_SET_CSC_CONSTANT2RED (0x0000014C) +#define NV917E_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV917E_SET_CSC_RED2GRN (0x00000150) +#define NV917E_SET_CSC_RED2GRN_COEFF 18:0 +#define NV917E_SET_CSC_GRN2GRN (0x00000154) +#define NV917E_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV917E_SET_CSC_BLU2GRN (0x00000158) +#define NV917E_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV917E_SET_CSC_CONSTANT2GRN (0x0000015C) +#define NV917E_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV917E_SET_CSC_RED2BLU (0x00000160) +#define NV917E_SET_CSC_RED2BLU_COEFF 18:0 +#define NV917E_SET_CSC_GRN2BLU (0x00000164) +#define NV917E_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV917E_SET_CSC_BLU2BLU (0x00000168) +#define NV917E_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV917E_SET_CSC_CONSTANT2BLU (0x0000016C) +#define NV917E_SET_CSC_CONSTANT2BLU_COEFF 18:0 +#define NV917E_SET_SPARE (0x000003BC) +#define NV917E_SET_SPARE_UNUSED 31:0 +#define NV917E_SET_SPARE_NOOP(b) (0x000003C0 + (b)*0x00000004) +#define NV917E_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV917E_SURFACE_SET_OFFSET(b) (0x00000400 + (b)*0x00000004) +#define NV917E_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV917E_SURFACE_SET_SIZE (0x00000408) +#define NV917E_SURFACE_SET_SIZE_WIDTH 15:0 +#define NV917E_SURFACE_SET_SIZE_HEIGHT 31:16 +#define NV917E_SURFACE_SET_STORAGE (0x0000040C) +#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV917E_SURFACE_SET_STORAGE_PITCH 20:8 +#define NV917E_SURFACE_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV917E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV917E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV917E_SURFACE_SET_PARAMS (0x00000410) +#define NV917E_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV917E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8 (0x00000028) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8 (0x00000029) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV917E_SURFACE_SET_PARAMS_COLOR_SPACE 1:0 +#define NV917E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB (0x00000000) +#define NV917E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601 (0x00000001) +#define NV917E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709 (0x00000002) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl917e_h diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl9270.h b/userspace/sdks/nv570/nvidia/inc/class/cl9270.h new file mode 100644 index 0000000..de3f498 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl9270.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9270.finn +// + +#define NV9270_DISPLAY (0x9270U) /* finn: Evaluated from "NV9270_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV9270_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9270U) + +typedef struct NV9270_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numDacs; // Number of DACs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NV9270_ALLOCATION_PARAMETERS; diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl9271.h b/userspace/sdks/nv570/nvidia/inc/class/cl9271.h new file mode 100644 index 0000000..397cdc2 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl9271.h @@ -0,0 +1,295 @@ +/* + * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl9271_h_ +#define _cl9271_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV9271_DISP_SF_USER 0x9271 + +typedef volatile struct _cl9271_tag0 { + NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x00690FFF:0x00690000 */ +} _Nv9271DispSfUser, Nv9271DispSfUserMap; + +#define NV9271_SF_HDMI_INFO_IDX_AVI_INFOFRAME 0x00000000 /* */ +#define NV9271_SF_HDMI_INFO_IDX_GENERIC_INFOFRAME 0x00000001 /* */ +#define NV9271_SF_HDMI_INFO_IDX_GCP 0x00000003 /* */ +#define NV9271_SF_HDMI_INFO_IDX_VSI 0x00000004 /* */ +#define NV9271_SF_HDMI_INFO_CTRL(i,j) (0x00690000-0x00690000+(i)*1024+(j)*64) /* RWX4A */ +#define NV9271_SF_HDMI_INFO_CTRL__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_INFO_CTRL__SIZE_2 5 /* */ +#define NV9271_SF_HDMI_INFO_CTRL_ENABLE 0:0 /* RWIVF */ +#define NV9271_SF_HDMI_INFO_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_INFO_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NV9271_SF_HDMI_INFO_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NV9271_SF_HDMI_INFO_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NV9271_SF_HDMI_INFO_CTRL_OTHER 4:4 /* RWIVF */ +#define NV9271_SF_HDMI_INFO_CTRL_OTHER_DIS 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_INFO_CTRL_OTHER_EN 0x00000001 /* RW--V */ +#define NV9271_SF_HDMI_INFO_CTRL_SINGLE 8:8 /* RWIVF */ +#define NV9271_SF_HDMI_INFO_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_INFO_CTRL_SINGLE_EN 0x00000001 /* RW--V */ +#define NV9271_SF_HDMI_INFO_CTRL_CHKSUM_HW 9:9 /* RWIVF */ +#define NV9271_SF_HDMI_INFO_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */ +#define NV9271_SF_HDMI_INFO_CTRL_CHKSUM_HW_EN 0x00000001 /* RW--V */ +#define NV9271_SF_HDMI_INFO_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */ +#define NV9271_SF_HDMI_INFO_CTRL_CHKSUM_HW_DIS 0x00000000 /* RW--V */ +#define NV9271_SF_HDMI_INFO_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */ +#define NV9271_SF_HDMI_INFO_CTRL_HBLANK 12:12 /* RWIVF */ +#define NV9271_SF_HDMI_INFO_CTRL_HBLANK_DIS 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_INFO_CTRL_HBLANK_EN 0x00000001 /* RW--V */ +#define NV9271_SF_HDMI_INFO_CTRL_VIDEO_FMT 16:16 /* RWIVF */ +#define NV9271_SF_HDMI_INFO_CTRL_VIDEO_FMT_SW_CONTROLLED 0x00000000 /* RW--V */ +#define NV9271_SF_HDMI_INFO_CTRL_VIDEO_FMT_HW_CONTROLLED 0x00000001 /* RW--V */ +#define NV9271_SF_HDMI_INFO_CTRL_VIDEO_FMT_INIT 0x00000001 /* RWI-V */ +#define NV9271_SF_HDMI_INFO_STATUS(i,j) (0x00690004-0x00690000+(i)*1024+(j)*64) /* R--4A */ +#define NV9271_SF_HDMI_INFO_STATUS__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_INFO_STATUS__SIZE_2 5 /* */ +#define NV9271_SF_HDMI_INFO_STATUS_SENT 0:0 /* R--VF */ +#define NV9271_SF_HDMI_INFO_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NV9271_SF_HDMI_INFO_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NV9271_SF_HDMI_INFO_STATUS_SENT_INIT 0x00000000 /* R-I-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x00690000-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x00690008-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x0069000C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x00690010-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x00690014-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x00690018-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_HEADER(i) (0x00690048-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_GENERIC_HEADER__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_GENERIC_HEADER_HB0 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_HEADER_HB1 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_HEADER_HB2 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW(i) (0x0069004C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_HIGH(i) (0x00690050-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW(i) (0x00690054-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_HIGH(i) (0x00690058-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW(i) (0x0069005C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_HIGH(i) (0x00690060-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_HIGH__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW(i) (0x00690064-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24 31:24 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_HIGH(i) (0x00690068-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_HIGH__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GCP_SUBPACK(i) (0x006900CC-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_GCP_SUBPACK__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_GCP_SUBPACK_SB0 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_GCP_SUBPACK_SB0_INIT 0x00000001 /* RWI-V */ +#define NV9271_SF_HDMI_GCP_SUBPACK_SB0_SET_AVMUTE 0x00000001 /* RW--V */ +#define NV9271_SF_HDMI_GCP_SUBPACK_SB0_CLR_AVMUTE 0x00000010 /* RW--V */ +#define NV9271_SF_HDMI_GCP_SUBPACK_SB1 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_GCP_SUBPACK_SB1_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_GCP_SUBPACK_SB2 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_GCP_SUBPACK_SB2_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_HEADER(i) (0x00690108-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_VSI_HEADER__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_VSI_HEADER_HB0 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_HEADER_HB1 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_HEADER_HB2 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW(i) (0x0069010C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_HIGH(i) (0x00690110-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW(i) (0x00690114-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_HIGH(i) (0x00690118-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW(i) (0x0069011C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_HIGH(i) (0x00690120-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_HIGH__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW(i) (0x00690124-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW_PB21 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW_PB22 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW_PB23 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW_PB24 31:24 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_HIGH(i) (0x00690128-0x00690000+(i)*1024) /* RWX4A */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_HIGH__SIZE_1 4 /* */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */ +#define NV9271_SF_HDMI_VSI_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _cl9271_h_ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl927c.h b/userspace/sdks/nv570/nvidia/inc/class/cl927c.h new file mode 100644 index 0000000..1b78305 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl927c.h @@ -0,0 +1,299 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl927c_h_ +#define _cl927c_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV927C_BASE_CHANNEL_DMA (0x0000927C) + +#define NV_DISP_BASE_NOTIFIER_1 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1_SIZEOF 0x00000004 +#define NV_DISP_BASE_NOTIFIER_1__0 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT 15:0 +#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP 29:16 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS 31:30 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED 0x00000002 + + +#define NV_DISP_NOTIFICATION_2 0x00000000 +#define NV_DISP_NOTIFICATION_2_SIZEOF 0x00000010 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0 0x00000000 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0_NANOSECONDS0 31:0 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1 0x00000001 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1_NANOSECONDS1 31:0 +#define NV_DISP_NOTIFICATION_2_INFO32_2 0x00000002 +#define NV_DISP_NOTIFICATION_2_INFO32_2_R0 31:0 +#define NV_DISP_NOTIFICATION_2_INFO16_3 0x00000003 +#define NV_DISP_NOTIFICATION_2_INFO16_3_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_2_INFO16_3_FIELD 8:8 +#define NV_DISP_NOTIFICATION_2_INFO16_3_R1 15:9 +#define NV_DISP_NOTIFICATION_2__3_STATUS 31:16 +#define NV_DISP_NOTIFICATION_2__3_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_2__3_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_2__3_STATUS_FINISHED 0x00000000 + + +#define NV_DISP_NOTIFICATION_INFO16 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_INFO16__0 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_INFO16__0_FIELD 8:8 +#define NV_DISP_NOTIFICATION_INFO16__0_R1 15:9 + + +#define NV_DISP_NOTIFICATION_STATUS 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_STATUS__0 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS 15:0 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED 0x00000000 + + +// dma opcode instructions +#define NV927C_DMA 0x00000000 +#define NV927C_DMA_OPCODE 31:29 +#define NV927C_DMA_OPCODE_METHOD 0x00000000 +#define NV927C_DMA_OPCODE_JUMP 0x00000001 +#define NV927C_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV927C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV927C_DMA_OPCODE 31:29 +#define NV927C_DMA_OPCODE_METHOD 0x00000000 +#define NV927C_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV927C_DMA_METHOD_COUNT 27:18 +#define NV927C_DMA_METHOD_OFFSET 11:2 +#define NV927C_DMA_DATA 31:0 +#define NV927C_DMA_DATA_NOP 0x00000000 +#define NV927C_DMA_OPCODE 31:29 +#define NV927C_DMA_OPCODE_JUMP 0x00000001 +#define NV927C_DMA_JUMP_OFFSET 11:2 +#define NV927C_DMA_OPCODE 31:29 +#define NV927C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV927C_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV927C_PUT (0x00000000) +#define NV927C_PUT_PTR 11:2 +#define NV927C_GET (0x00000004) +#define NV927C_GET_PTR 11:2 +#define NV927C_GET_SCANLINE (0x00000010) +#define NV927C_GET_SCANLINE_LINE 15:0 +#define NV927C_UPDATE (0x00000080) +#define NV927C_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV927C_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV927C_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV927C_UPDATE_SPECIAL_HANDLING 25:24 +#define NV927C_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV927C_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV927C_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV927C_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV927C_SET_PRESENT_CONTROL (0x00000084) +#define NV927C_SET_PRESENT_CONTROL_BEGIN_MODE 9:8 +#define NV927C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NV927C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NV927C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE (0x00000002) +#define NV927C_SET_PRESENT_CONTROL_STEREO_FLIP_MODE 3:3 +#define NV927C_SET_PRESENT_CONTROL_STEREO_FLIP_MODE_PAIR_FLIP (0x00000000) +#define NV927C_SET_PRESENT_CONTROL_STEREO_FLIP_MODE_AT_ANY_FRAME (0x00000001) +#define NV927C_SET_PRESENT_CONTROL_TIMESTAMP_MODE 2:2 +#define NV927C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000) +#define NV927C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001) +#define NV927C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV927C_SET_PRESENT_CONTROL_BEGIN_LINE 30:16 +#define NV927C_SET_PRESENT_CONTROL_ON_LINE_MARGIN 15:10 +#define NV927C_SET_PRESENT_CONTROL_MODE 1:0 +#define NV927C_SET_PRESENT_CONTROL_MODE_MONO (0x00000000) +#define NV927C_SET_PRESENT_CONTROL_MODE_STEREO (0x00000001) +#define NV927C_SET_PRESENT_CONTROL_MODE_SPEC_FLIP (0x00000002) +#define NV927C_SET_SEMAPHORE_CONTROL (0x00000088) +#define NV927C_SET_SEMAPHORE_CONTROL_OFFSET 11:2 +#define NV927C_SET_SEMAPHORE_CONTROL_DELAY 26:26 +#define NV927C_SET_SEMAPHORE_CONTROL_DELAY_DISABLE (0x00000000) +#define NV927C_SET_SEMAPHORE_CONTROL_DELAY_ENABLE (0x00000001) +#define NV927C_SET_SEMAPHORE_CONTROL_FORMAT 28:28 +#define NV927C_SET_SEMAPHORE_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV927C_SET_SEMAPHORE_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV927C_SET_SEMAPHORE_ACQUIRE (0x0000008C) +#define NV927C_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NV927C_SET_SEMAPHORE_RELEASE (0x00000090) +#define NV927C_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NV927C_SET_CONTEXT_DMA_SEMAPHORE (0x00000094) +#define NV927C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NV927C_SET_NOTIFIER_CONTROL (0x000000A0) +#define NV927C_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV927C_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV927C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV927C_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV927C_SET_NOTIFIER_CONTROL_DELAY 26:26 +#define NV927C_SET_NOTIFIER_CONTROL_DELAY_DISABLE (0x00000000) +#define NV927C_SET_NOTIFIER_CONTROL_DELAY_ENABLE (0x00000001) +#define NV927C_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV927C_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV927C_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV927C_SET_CONTEXT_DMA_NOTIFIER (0x000000A4) +#define NV927C_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV927C_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0x00000004) +#define NV927C_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV927C_SET_BASE_LUT_LO (0x000000E0) +#define NV927C_SET_BASE_LUT_LO_ENABLE 31:30 +#define NV927C_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV927C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001) +#define NV927C_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000002) +#define NV927C_SET_BASE_LUT_LO_MODE 27:24 +#define NV927C_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV927C_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV927C_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV927C_SET_BASE_LUT_HI (0x000000E4) +#define NV927C_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV927C_SET_OUTPUT_LUT_LO (0x000000E8) +#define NV927C_SET_OUTPUT_LUT_LO_ENABLE 31:30 +#define NV927C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV927C_SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001) +#define NV927C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000002) +#define NV927C_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV927C_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV927C_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV927C_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV927C_SET_OUTPUT_LUT_HI (0x000000EC) +#define NV927C_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV927C_SET_CONTEXT_DMA_LUT (0x000000FC) +#define NV927C_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV927C_SET_PROCESSING (0x00000110) +#define NV927C_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV927C_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV927C_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV927C_SET_CONVERSION_RED (0x00000114) +#define NV927C_SET_CONVERSION_RED_GAIN 15:0 +#define NV927C_SET_CONVERSION_RED_OFS 31:16 +#define NV927C_SET_CONVERSION_GRN (0x00000118) +#define NV927C_SET_CONVERSION_GRN_GAIN 15:0 +#define NV927C_SET_CONVERSION_GRN_OFS 31:16 +#define NV927C_SET_CONVERSION_BLU (0x0000011C) +#define NV927C_SET_CONVERSION_BLU_GAIN 15:0 +#define NV927C_SET_CONVERSION_BLU_OFS 31:16 +#define NV927C_SET_TIMESTAMP_ORIGIN_LO (0x00000130) +#define NV927C_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NV927C_SET_TIMESTAMP_ORIGIN_HI (0x00000134) +#define NV927C_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NV927C_SET_UPDATE_TIMESTAMP_LO (0x00000138) +#define NV927C_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NV927C_SET_UPDATE_TIMESTAMP_HI (0x0000013C) +#define NV927C_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NV927C_SET_CSC_RED2RED (0x00000140) +#define NV927C_SET_CSC_RED2RED_OWNER 31:31 +#define NV927C_SET_CSC_RED2RED_OWNER_CORE (0x00000000) +#define NV927C_SET_CSC_RED2RED_OWNER_BASE (0x00000001) +#define NV927C_SET_CSC_RED2RED_COEFF 18:0 +#define NV927C_SET_CSC_GRN2RED (0x00000144) +#define NV927C_SET_CSC_GRN2RED_COEFF 18:0 +#define NV927C_SET_CSC_BLU2RED (0x00000148) +#define NV927C_SET_CSC_BLU2RED_COEFF 18:0 +#define NV927C_SET_CSC_CONSTANT2RED (0x0000014C) +#define NV927C_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV927C_SET_CSC_RED2GRN (0x00000150) +#define NV927C_SET_CSC_RED2GRN_COEFF 18:0 +#define NV927C_SET_CSC_GRN2GRN (0x00000154) +#define NV927C_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV927C_SET_CSC_BLU2GRN (0x00000158) +#define NV927C_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV927C_SET_CSC_CONSTANT2GRN (0x0000015C) +#define NV927C_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV927C_SET_CSC_RED2BLU (0x00000160) +#define NV927C_SET_CSC_RED2BLU_COEFF 18:0 +#define NV927C_SET_CSC_GRN2BLU (0x00000164) +#define NV927C_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV927C_SET_CSC_BLU2BLU (0x00000168) +#define NV927C_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV927C_SET_CSC_CONSTANT2BLU (0x0000016C) +#define NV927C_SET_CSC_CONSTANT2BLU_COEFF 18:0 +#define NV927C_SET_SPARE (0x000003BC) +#define NV927C_SET_SPARE_UNUSED 31:0 +#define NV927C_SET_SPARE_NOOP(b) (0x000003C0 + (b)*0x00000004) +#define NV927C_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV927C_SURFACE_SET_OFFSET(a,b) (0x00000400 + (a)*0x00000020 + (b)*0x00000004) +#define NV927C_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV927C_SURFACE_SET_SIZE(a) (0x00000408 + (a)*0x00000020) +#define NV927C_SURFACE_SET_SIZE_WIDTH 15:0 +#define NV927C_SURFACE_SET_SIZE_HEIGHT 31:16 +#define NV927C_SURFACE_SET_STORAGE(a) (0x0000040C + (a)*0x00000020) +#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV927C_SURFACE_SET_STORAGE_PITCH 20:8 +#define NV927C_SURFACE_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV927C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV927C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV927C_SURFACE_SET_PARAMS(a) (0x00000410 + (a)*0x00000020) +#define NV927C_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV927C_SURFACE_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV927C_SURFACE_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV927C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV927C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV927C_SURFACE_SET_PARAMS_GAMMA 2:2 +#define NV927C_SURFACE_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV927C_SURFACE_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV927C_SURFACE_SET_PARAMS_LAYOUT 5:4 +#define NV927C_SURFACE_SET_PARAMS_LAYOUT_FRM (0x00000000) +#define NV927C_SURFACE_SET_PARAMS_LAYOUT_FLD1 (0x00000001) +#define NV927C_SURFACE_SET_PARAMS_LAYOUT_FLD2 (0x00000002) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl927c_h diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl927d.h b/userspace/sdks/nv570/nvidia/inc/class/cl927d.h new file mode 100644 index 0000000..df45fec --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl927d.h @@ -0,0 +1,1556 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl927d_h_ +#define _cl927d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV927D_CORE_CHANNEL_DMA (0x0000927D) + +#define NV927D_CORE_NOTIFIER_3 0x00000000 +#define NV927D_CORE_NOTIFIER_3_SIZEOF 0x00000150 +#define NV927D_CORE_NOTIFIER_3_COMPLETION_0 0x00000000 +#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_DONE 0:0 +#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_R0 15:1 +#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP 29:16 +#define NV927D_CORE_NOTIFIER_3__1 0x00000001 +#define NV927D_CORE_NOTIFIER_3__1_R1 31:0 +#define NV927D_CORE_NOTIFIER_3__2 0x00000002 +#define NV927D_CORE_NOTIFIER_3__2_R2 31:0 +#define NV927D_CORE_NOTIFIER_3__3 0x00000003 +#define NV927D_CORE_NOTIFIER_3__3_R3 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_R0 19:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA 20:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_R1 29:21 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE 30:30 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5 0x00000005 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE 3:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE 11:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE 15:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE 19:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE 27:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE 31:28 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6 0x00000006 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE 3:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE 11:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE 15:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE 19:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE 27:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE 31:28 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_UNAVAILABLE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_SCAN_LOCK 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_FLIP_LOCK 0x00000002 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_STEREO 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_7 0x00000007 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_7_R4 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_8 0x00000008 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_8_R5 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_9 0x00000009 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_9_R6 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_10 0x0000000A +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_10_R7 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_11 0x0000000B +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_11_R8 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12 0x0000000C +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0 31:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13 0x0000000D +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14 0x0000000E +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0 31:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15 0x0000000F +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16 0x00000010 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0 31:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17 0x00000011 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18 0x00000012 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0 31:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19 0x00000013 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A 8:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B 9:9 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1 10:10 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS 11:11 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2 12:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3 15:14 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4 19:17 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A 24:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B 25:25 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE 26:26 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6 31:27 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21 0x00000015 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_LVDS_CLK_MAX 23:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R8 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22 0x00000016 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A 8:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B 9:9 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1 10:10 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS 11:11 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2 12:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3 15:14 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4 19:17 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A 24:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B 25:25 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE 26:26 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6 31:27 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23 0x00000017 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_LVDS_CLK_MAX 23:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R8 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24 0x00000018 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A 8:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B 9:9 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1 10:10 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS 11:11 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2 12:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3 15:14 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4 19:17 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A 24:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B 25:25 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE 26:26 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6 31:27 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25 0x00000019 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_LVDS_CLK_MAX 23:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R8 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26 0x0000001A +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A 8:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B 9:9 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1 10:10 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS 11:11 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2 12:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3 15:14 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4 19:17 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A 24:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B 25:25 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE 26:26 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6 31:27 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27 0x0000001B +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_LVDS_CLK_MAX 23:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R8 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28 0x0000001C +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A 8:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B 9:9 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1 10:10 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS 11:11 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2 12:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3 15:14 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4 19:17 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A 24:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B 25:25 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE 26:26 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6 31:27 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29 0x0000001D +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_LVDS_CLK_MAX 23:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R8 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30 0x0000001E +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A 8:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B 9:9 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1 10:10 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS 11:11 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2 12:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3 15:14 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4 19:17 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A 24:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B 25:25 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE 26:26 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6 31:27 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31 0x0000001F +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_LVDS_CLK_MAX 23:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R8 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32 0x00000020 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A 8:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B 9:9 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1 10:10 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS 11:11 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2 12:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3 15:14 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4 19:17 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A 24:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B 25:25 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE 26:26 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6 31:27 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33 0x00000021 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_LVDS_CLK_MAX 23:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R8 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34 0x00000022 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A 8:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B 9:9 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1 10:10 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS 11:11 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2 12:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3 15:14 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4 19:17 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A 24:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B 25:25 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE 26:26 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6 31:27 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35 0x00000023 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_LVDS_CLK_MAX 23:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R8 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36 0x00000024 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0 31:7 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37 0x00000025 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38 0x00000026 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0 31:7 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39 0x00000027 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40 0x00000028 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0 31:7 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41 0x00000029 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42 0x0000002A +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0 31:7 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43 0x0000002B +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44 0x0000002C +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44_R0 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45 0x0000002D +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45_R1 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46 0x0000002E +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46_R0 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47 0x0000002F +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47_R1 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48 0x00000030 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48_R0 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49 0x00000031 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49_R1 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50 0x00000032 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50_R0 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51 0x00000033 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51_R1 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52 0x00000034 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53 0x00000035 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54 0x00000036 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55 0x00000037 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56 0x00000038 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57 0x00000039 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58 0x0000003A +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59 0x0000003B +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60 0x0000003C +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61 0x0000003D +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62 0x0000003E +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63 0x0000003F +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64 0x00000040 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65 0x00000041 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66 0x00000042 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67 0x00000043 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68 0x00000044 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69 0x00000045 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70 0x00000046 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71 0x00000047 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72 0x00000048 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73 0x00000049 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74 0x0000004A +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75 0x0000004B +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76 0x0000004C +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77 0x0000004D +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78 0x0000004E +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79 0x0000004F +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80 0x00000050 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81 0x00000051 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82 0x00000052 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83 0x00000053 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10 31:0 + + +// dma opcode instructions +#define NV927D_DMA 0x00000000 +#define NV927D_DMA_OPCODE 31:29 +#define NV927D_DMA_OPCODE_METHOD 0x00000000 +#define NV927D_DMA_OPCODE_JUMP 0x00000001 +#define NV927D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV927D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV927D_DMA_OPCODE 31:29 +#define NV927D_DMA_OPCODE_METHOD 0x00000000 +#define NV927D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV927D_DMA_METHOD_COUNT 27:18 +#define NV927D_DMA_METHOD_OFFSET 11:2 +#define NV927D_DMA_DATA 31:0 +#define NV927D_DMA_DATA_NOP 0x00000000 +#define NV927D_DMA_OPCODE 31:29 +#define NV927D_DMA_OPCODE_JUMP 0x00000001 +#define NV927D_DMA_JUMP_OFFSET 11:2 +#define NV927D_DMA_OPCODE 31:29 +#define NV927D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV927D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV927D_PUT (0x00000000) +#define NV927D_PUT_PTR 11:2 +#define NV927D_GET (0x00000004) +#define NV927D_GET_PTR 11:2 +#define NV927D_UPDATE (0x00000080) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR(i) (0 +(i)*4):(0 +(i)*4) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1 4 +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0 +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR1 4:4 +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR2 8:8 +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR3 12:12 +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE(i) (1 +(i)*4):(1 +(i)*4) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1 4 +#define NV927D_UPDATE_INTERLOCK_WITH_BASE_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE0 1:1 +#define NV927D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE1 5:5 +#define NV927D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE2 9:9 +#define NV927D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE3 13:13 +#define NV927D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY(i) (2 +(i)*4):(2 +(i)*4) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1 4 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY1 6:6 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY2 10:10 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY3 14:14 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i) (3 +(i)*4):(3 +(i)*4) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1 4 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 7:7 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2 11:11 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3 15:15 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE (0x00000001) +#define NV927D_UPDATE_SPECIAL_HANDLING 25:24 +#define NV927D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV927D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV927D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV927D_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV927D_UPDATE_NOT_DRIVER_FRIENDLY 31:31 +#define NV927D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000) +#define NV927D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001) +#define NV927D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30 +#define NV927D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000) +#define NV927D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001) +#define NV927D_UPDATE_INHIBIT_INTERRUPTS 29:29 +#define NV927D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NV927D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NV927D_SET_NOTIFIER_CONTROL (0x00000084) +#define NV927D_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV927D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV927D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV927D_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV927D_SET_NOTIFIER_CONTROL_NOTIFY 31:31 +#define NV927D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NV927D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NV927D_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV927D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV927D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV927D_SET_CONTEXT_DMA_NOTIFIER (0x00000088) +#define NV927D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV927D_GET_CAPABILITIES (0x0000008C) +#define NV927D_GET_CAPABILITIES_DUMMY 31:0 +#define NV927D_SET_SPARE (0x0000016C) +#define NV927D_SET_SPARE_UNUSED 31:0 +#define NV927D_SET_SPARE_NOOP(b) (0x00000170 + (b)*0x00000004) +#define NV927D_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV927D_DAC_SET_CONTROL(a) (0x00000180 + (a)*0x00000020) +#define NV927D_DAC_SET_CONTROL_OWNER_MASK 3:0 +#define NV927D_DAC_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV927D_DAC_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV927D_DAC_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV927D_DAC_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV927D_DAC_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV927D_DAC_SET_CONTROL_PROTOCOL 12:8 +#define NV927D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV927D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT (0x00000013) +#define NV927D_DAC_SET_SW_SPARE_A(a) (0x00000184 + (a)*0x00000020) +#define NV927D_DAC_SET_SW_SPARE_A_CODE 31:0 +#define NV927D_DAC_SET_SW_SPARE_B(a) (0x00000188 + (a)*0x00000020) +#define NV927D_DAC_SET_SW_SPARE_B_CODE 31:0 +#define NV927D_DAC_SET_CUSTOM_REASON(a) (0x00000190 + (a)*0x00000020) +#define NV927D_DAC_SET_CUSTOM_REASON_CODE 31:0 + +#define NV927D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020) +#define NV927D_SOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV927D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV927D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV927D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV927D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV927D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV927D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV927D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV927D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV927D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV927D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV927D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NV927D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NV927D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV927D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV927D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV927D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV927D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NV927D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NV927D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NV927D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NV927D_SOR_SET_SW_SPARE_A(a) (0x00000204 + (a)*0x00000020) +#define NV927D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NV927D_SOR_SET_SW_SPARE_B(a) (0x00000208 + (a)*0x00000020) +#define NV927D_SOR_SET_SW_SPARE_B_CODE 31:0 +#define NV927D_SOR_SET_CUSTOM_REASON(a) (0x00000210 + (a)*0x00000020) +#define NV927D_SOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV927D_PIOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NV927D_PIOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV927D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV927D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV927D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV927D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV927D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV927D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV927D_PIOR_SET_SW_SPARE_A(a) (0x00000304 + (a)*0x00000020) +#define NV927D_PIOR_SET_SW_SPARE_A_CODE 31:0 +#define NV927D_PIOR_SET_SW_SPARE_B(a) (0x00000308 + (a)*0x00000020) +#define NV927D_PIOR_SET_SW_SPARE_B_CODE 31:0 +#define NV927D_PIOR_SET_CUSTOM_REASON(a) (0x00000310 + (a)*0x00000020) +#define NV927D_PIOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV927D_HEAD_SET_PRESENT_CONTROL(a) (0x00000400 + (a)*0x00000300) +#define NV927D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NV927D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 8:8 +#define NV927D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NV927D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NV927D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00000404 + (a)*0x00000300) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 3:3 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 4:4 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 9:6 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000009) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 12:12 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 20:13 +#define NV927D_HEAD_SET_CONTROL(a) (0x00000408 + (a)*0x00000300) +#define NV927D_HEAD_SET_CONTROL_STRUCTURE 0:0 +#define NV927D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV927D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 3:2 +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 19:15 +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV927D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 7:4 +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 9:8 +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 14:10 +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV927D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK 1:1 +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_DISABLE (0x00000000) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_ENABLE (0x00000001) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN 24:20 +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV927D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN 29:25 +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000000) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000001) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000002) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000003) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000004) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000005) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000006) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000007) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000008) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x00000009) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000A) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000B) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000C) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000D) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000E) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x0000000F) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_UNSPECIFIED (0x00000010) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV927D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV927D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NV927D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NV927D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000410 + (a)*0x00000300) +#define NV927D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV927D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV927D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV927D_HEAD_SET_RASTER_SIZE(a) (0x00000414 + (a)*0x00000300) +#define NV927D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV927D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV927D_HEAD_SET_RASTER_SYNC_END(a) (0x00000418 + (a)*0x00000300) +#define NV927D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV927D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV927D_HEAD_SET_RASTER_BLANK_END(a) (0x0000041C + (a)*0x00000300) +#define NV927D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV927D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV927D_HEAD_SET_RASTER_BLANK_START(a) (0x00000420 + (a)*0x00000300) +#define NV927D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV927D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV927D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000424 + (a)*0x00000300) +#define NV927D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV927D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV927D_HEAD_SET_LOCK_CHAIN(a) (0x00000428 + (a)*0x00000300) +#define NV927D_HEAD_SET_LOCK_CHAIN_POSITION 27:24 +#define NV927D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000042C + (a)*0x00000300) +#define NV927D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV927D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV927D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV927D_HEAD_SET_CRC_CONTROL(a) (0x00000430 + (a)*0x00000300) +#define NV927D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 1:0 +#define NV927D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000000) +#define NV927D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_BASE (0x00000001) +#define NV927D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_OVERLAY (0x00000002) +#define NV927D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 2:2 +#define NV927D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NV927D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NV927D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE 3:3 +#define NV927D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_FALSE (0x00000000) +#define NV927D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_TRUE (0x00000001) +#define NV927D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE 4:4 +#define NV927D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_FALSE (0x00000000) +#define NV927D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_TRUE (0x00000001) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT 19:8 +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC__SIZE_1 4 +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC0 (0x00000FF0) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC1 (0x00000FF1) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC2 (0x00000FF2) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC3 (0x00000FF3) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG__SIZE_1 4 +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG0 (0x00000FF8) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG1 (0x00000FF9) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG2 (0x00000FFA) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG3 (0x00000FFB) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR__SIZE_1 8 +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR0 (0x00000F0F) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR1 (0x00000F1F) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR2 (0x00000F2F) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR3 (0x00000F3F) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR4 (0x00000F4F) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR5 (0x00000F5F) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR6 (0x00000F6F) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR7 (0x00000F7F) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF__SIZE_1 4 +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF0 (0x00000F8F) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF1 (0x00000F9F) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF2 (0x00000FAF) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF3 (0x00000FBF) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR__SIZE_1 8 +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR0 (0x000000FF) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR1 (0x000001FF) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR2 (0x000002FF) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR3 (0x000003FF) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR4 (0x000004FF) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR5 (0x000005FF) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR6 (0x000006FF) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR7 (0x000007FF) +#define NV927D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_NONE (0x00000FFF) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT 31:20 +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC__SIZE_1 4 +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC0 (0x00000FF0) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC1 (0x00000FF1) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC2 (0x00000FF2) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC3 (0x00000FF3) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG__SIZE_1 4 +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG0 (0x00000FF8) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG1 (0x00000FF9) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG2 (0x00000FFA) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG3 (0x00000FFB) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR__SIZE_1 8 +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR0 (0x00000F0F) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR1 (0x00000F1F) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR2 (0x00000F2F) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR3 (0x00000F3F) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR4 (0x00000F4F) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR5 (0x00000F5F) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR6 (0x00000F6F) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR7 (0x00000F7F) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF__SIZE_1 4 +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF0 (0x00000F8F) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF1 (0x00000F9F) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF2 (0x00000FAF) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF3 (0x00000FBF) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR__SIZE_1 8 +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR0 (0x000000FF) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR1 (0x000001FF) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR2 (0x000002FF) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR3 (0x000003FF) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR4 (0x000004FF) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR5 (0x000005FF) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR6 (0x000006FF) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR7 (0x000007FF) +#define NV927D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_NONE (0x00000FFF) +#define NV927D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 5:5 +#define NV927D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC 6:6 +#define NV927D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_DISABLE (0x00000000) +#define NV927D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_ENABLE (0x00000001) +#define NV927D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00000438 + (a)*0x00000300) +#define NV927D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NV927D_HEAD_SET_BASE_LUT_LO(a) (0x00000440 + (a)*0x00000300) +#define NV927D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV927D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE 27:24 +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV927D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV927D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_BASE_LUT_HI(a) (0x00000444 + (a)*0x00000300) +#define NV927D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV927D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000448 + (a)*0x00000300) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000044C + (a)*0x00000300) +#define NV927D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x00000450 + (a)*0x00000300) +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x00000454 + (a)*0x00000300) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE 21:20 +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25 (0x00000000) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28 (0x00000001) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM (0x00000002) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 24:24 +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING 25:25 +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE (0x00000000) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE (0x00000001) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 26:26 +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00000458 + (a)*0x00000300) +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NV927D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000045C + (a)*0x00000300) +#define NV927D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV927D_HEAD_SET_OFFSET(a) (0x00000460 + (a)*0x00000300) +#define NV927D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV927D_HEAD_SET_SIZE(a) (0x00000468 + (a)*0x00000300) +#define NV927D_HEAD_SET_SIZE_WIDTH 15:0 +#define NV927D_HEAD_SET_SIZE_HEIGHT 31:16 +#define NV927D_HEAD_SET_STORAGE(a) (0x0000046C + (a)*0x00000300) +#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV927D_HEAD_SET_STORAGE_PITCH 20:8 +#define NV927D_HEAD_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV927D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV927D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV927D_HEAD_SET_PARAMS(a) (0x00000470 + (a)*0x00000300) +#define NV927D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV927D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV927D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV927D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV927D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV927D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV927D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV927D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV927D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024) +#define NV927D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV927D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV927D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV927D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV927D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV927D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV927D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV927D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV927D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV927D_HEAD_SET_PARAMS_GAMMA 2:2 +#define NV927D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV927D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV927D_HEAD_SET_CONTEXT_DMAS_ISO(a) (0x00000474 + (a)*0x00000300) +#define NV927D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV927D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x0000047C + (a)*0x00000300) +#define NV927D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 1:0 +#define NV927D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NV927D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NV927D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_SPEC_FLIP (0x00000002) +#define NV927D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300) +#define NV927D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV927D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV927D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV927D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE 27:26 +#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NV927D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 15:8 +#define NV927D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 23:16 +#define NV927D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV927D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV927D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV927D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV927D_HEAD_SET_OFFSETS_CURSOR(a,b) (0x00000484 + (a)*0x00000300 + (b)*0x00000004) +#define NV927D_HEAD_SET_OFFSETS_CURSOR_ORIGIN 31:0 +#define NV927D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b) (0x0000048C + (a)*0x00000300 + (b)*0x00000004) +#define NV927D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE 31:0 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00000494 + (a)*0x00000300) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422 8:8 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE (0x00000000) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE (0x00000001) +#define NV927D_HEAD_SET_PROCAMP(a) (0x00000498 + (a)*0x00000300) +#define NV927D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV927D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV927D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV927D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV927D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV927D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV927D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV927D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV927D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV927D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 5:5 +#define NV927D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NV927D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NV927D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 6:6 +#define NV927D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) +#define NV927D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) +#define NV927D_HEAD_SET_DITHER_CONTROL(a) (0x000004A0 + (a)*0x00000300) +#define NV927D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV927D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV927D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV927D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV927D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002) +#define NV927D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NV927D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV927D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x000004B0 + (a)*0x00000300) +#define NV927D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV927D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV927D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000004B8 + (a)*0x00000300) +#define NV927D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV927D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV927D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x000004BC + (a)*0x00000300) +#define NV927D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NV927D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000004C0 + (a)*0x00000300) +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000004C4 + (a)*0x00000300) +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a) (0x000004C8 + (a)*0x00000300) +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH 14:0 +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT 30:16 +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT 17:16 +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE (0x00000000) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257 (0x00000001) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025 (0x00000002) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT 21:20 +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x000004D4 + (a)*0x00000300) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT 13:12 +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE (0x00000000) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257 (0x00000001) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025 (0x00000002) +#define NV927D_HEAD_SET_PROCESSING(a) (0x000004E0 + (a)*0x00000300) +#define NV927D_HEAD_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV927D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV927D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV927D_HEAD_SET_CONVERSION_RED(a) (0x000004E4 + (a)*0x00000300) +#define NV927D_HEAD_SET_CONVERSION_RED_GAIN 15:0 +#define NV927D_HEAD_SET_CONVERSION_RED_OFS 31:16 +#define NV927D_HEAD_SET_CONVERSION_GRN(a) (0x000004E8 + (a)*0x00000300) +#define NV927D_HEAD_SET_CONVERSION_GRN_GAIN 15:0 +#define NV927D_HEAD_SET_CONVERSION_GRN_OFS 31:16 +#define NV927D_HEAD_SET_CONVERSION_BLU(a) (0x000004EC + (a)*0x00000300) +#define NV927D_HEAD_SET_CONVERSION_BLU_GAIN 15:0 +#define NV927D_HEAD_SET_CONVERSION_BLU_OFS 31:16 +#define NV927D_HEAD_SET_CSC_RED2RED(a) (0x000004F0 + (a)*0x00000300) +#define NV927D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE 31:31 +#define NV927D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_CSC_RED2RED_COEFF 18:0 +#define NV927D_HEAD_SET_CSC_GRN2RED(a) (0x000004F4 + (a)*0x00000300) +#define NV927D_HEAD_SET_CSC_GRN2RED_COEFF 18:0 +#define NV927D_HEAD_SET_CSC_BLU2RED(a) (0x000004F8 + (a)*0x00000300) +#define NV927D_HEAD_SET_CSC_BLU2RED_COEFF 18:0 +#define NV927D_HEAD_SET_CSC_CONSTANT2RED(a) (0x000004FC + (a)*0x00000300) +#define NV927D_HEAD_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV927D_HEAD_SET_CSC_RED2GRN(a) (0x00000500 + (a)*0x00000300) +#define NV927D_HEAD_SET_CSC_RED2GRN_COEFF 18:0 +#define NV927D_HEAD_SET_CSC_GRN2GRN(a) (0x00000504 + (a)*0x00000300) +#define NV927D_HEAD_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV927D_HEAD_SET_CSC_BLU2GRN(a) (0x00000508 + (a)*0x00000300) +#define NV927D_HEAD_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV927D_HEAD_SET_CSC_CONSTANT2GRN(a) (0x0000050C + (a)*0x00000300) +#define NV927D_HEAD_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV927D_HEAD_SET_CSC_RED2BLU(a) (0x00000510 + (a)*0x00000300) +#define NV927D_HEAD_SET_CSC_RED2BLU_COEFF 18:0 +#define NV927D_HEAD_SET_CSC_GRN2BLU(a) (0x00000514 + (a)*0x00000300) +#define NV927D_HEAD_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV927D_HEAD_SET_CSC_BLU2BLU(a) (0x00000518 + (a)*0x00000300) +#define NV927D_HEAD_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV927D_HEAD_SET_CSC_CONSTANT2BLU(a) (0x0000051C + (a)*0x00000300) +#define NV927D_HEAD_SET_CSC_CONSTANT2BLU_COEFF 18:0 +#define NV927D_HEAD_SET_HDMI_CTRL(a) (0x00000520 + (a)*0x00000300) +#define NV927D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NV927D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NV927D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NV927D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NV927D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NV927D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE 15:12 +#define NV927D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000000) +#define NV927D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FIELD_ALTERNATIVE (0x00000001) +#define NV927D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_LINE_ALTERNATIVE (0x00000002) +#define NV927D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_FULL (0x00000003) +#define NV927D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH (0x00000004) +#define NV927D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH_GRAPHICS (0x00000005) +#define NV927D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_TOP_AND_BOTTOM (0x00000006) +#define NV927D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_HALF (0x00000008) +#define NV927D_HEAD_SET_VACTIVE_SPACE_COLOR(a) (0x00000524 + (a)*0x00000300) +#define NV927D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR 9:0 +#define NV927D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y 19:10 +#define NV927D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB 29:20 +#define NV927D_HEAD_SET_DISPLAY_ID(a,b) (0x0000052C + (a)*0x00000300 + (b)*0x00000004) +#define NV927D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NV927D_HEAD_SET_SW_SPARE_A(a) (0x0000054C + (a)*0x00000300) +#define NV927D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NV927D_HEAD_SET_SW_SPARE_B(a) (0x00000550 + (a)*0x00000300) +#define NV927D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NV927D_HEAD_SET_SW_SPARE_C(a) (0x00000554 + (a)*0x00000300) +#define NV927D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NV927D_HEAD_SET_SW_SPARE_D(a) (0x00000558 + (a)*0x00000300) +#define NV927D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NV927D_HEAD_SET_GET_BLANKING_CTRL(a) (0x0000055C + (a)*0x00000300) +#define NV927D_HEAD_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NV927D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NV927D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NV927D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NV927D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NV927D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) +#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a) (0x000006D0 + (a)*0x00000300) +#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED 31:0 +#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a) (0x000006D4 + (a)*0x00000300) +#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED 31:0 +#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a) (0x000006D8 + (a)*0x00000300) +#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED 31:0 +#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a) (0x000006DC + (a)*0x00000300) +#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED 31:0 +#define NV927D_HEAD_SET_SPARE(a) (0x000006EC + (a)*0x00000300) +#define NV927D_HEAD_SET_SPARE_UNUSED 31:0 +#define NV927D_HEAD_SET_SPARE_NOOP(a,b) (0x000006F0 + (a)*0x00000300 + (b)*0x00000004) +#define NV927D_HEAD_SET_SPARE_NOOP_UNUSED 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl927d_h diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl9470.h b/userspace/sdks/nv570/nvidia/inc/class/cl9470.h new file mode 100644 index 0000000..faacb95 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl9470.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9470.finn +// + +#define NV9470_DISPLAY (0x9470U) /* finn: Evaluated from "NV9470_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV9470_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9470U) + +typedef struct NV9470_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numDacs; // Number of DACs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NV9470_ALLOCATION_PARAMETERS; diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl9471.h b/userspace/sdks/nv570/nvidia/inc/class/cl9471.h new file mode 100644 index 0000000..c5f557f --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl9471.h @@ -0,0 +1,295 @@ +/* + * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl9471_h_ +#define _cl9471_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV9471_DISP_SF_USER 0x9471 + +typedef volatile struct _cl9471_tag0 { + NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x00690FFF:0x00690000 */ +} _Nv9471DispSfUser, Nv9471DispSfUserMap; + +#define NV9471_SF_HDMI_INFO_IDX_AVI_INFOFRAME 0x00000000 /* */ +#define NV9471_SF_HDMI_INFO_IDX_GENERIC_INFOFRAME 0x00000001 /* */ +#define NV9471_SF_HDMI_INFO_IDX_GCP 0x00000003 /* */ +#define NV9471_SF_HDMI_INFO_IDX_VSI 0x00000004 /* */ +#define NV9471_SF_HDMI_INFO_CTRL(i,j) (0x00690000-0x00690000+(i)*1024+(j)*64) /* RWX4A */ +#define NV9471_SF_HDMI_INFO_CTRL__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_INFO_CTRL__SIZE_2 5 /* */ +#define NV9471_SF_HDMI_INFO_CTRL_ENABLE 0:0 /* RWIVF */ +#define NV9471_SF_HDMI_INFO_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_INFO_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NV9471_SF_HDMI_INFO_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NV9471_SF_HDMI_INFO_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NV9471_SF_HDMI_INFO_CTRL_OTHER 4:4 /* RWIVF */ +#define NV9471_SF_HDMI_INFO_CTRL_OTHER_DIS 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_INFO_CTRL_OTHER_EN 0x00000001 /* RW--V */ +#define NV9471_SF_HDMI_INFO_CTRL_SINGLE 8:8 /* RWIVF */ +#define NV9471_SF_HDMI_INFO_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_INFO_CTRL_SINGLE_EN 0x00000001 /* RW--V */ +#define NV9471_SF_HDMI_INFO_CTRL_CHKSUM_HW 9:9 /* RWIVF */ +#define NV9471_SF_HDMI_INFO_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */ +#define NV9471_SF_HDMI_INFO_CTRL_CHKSUM_HW_EN 0x00000001 /* RW--V */ +#define NV9471_SF_HDMI_INFO_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */ +#define NV9471_SF_HDMI_INFO_CTRL_CHKSUM_HW_DIS 0x00000000 /* RW--V */ +#define NV9471_SF_HDMI_INFO_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */ +#define NV9471_SF_HDMI_INFO_CTRL_HBLANK 12:12 /* RWIVF */ +#define NV9471_SF_HDMI_INFO_CTRL_HBLANK_DIS 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_INFO_CTRL_HBLANK_EN 0x00000001 /* RW--V */ +#define NV9471_SF_HDMI_INFO_CTRL_VIDEO_FMT 16:16 /* RWIVF */ +#define NV9471_SF_HDMI_INFO_CTRL_VIDEO_FMT_SW_CONTROLLED 0x00000000 /* RW--V */ +#define NV9471_SF_HDMI_INFO_CTRL_VIDEO_FMT_HW_CONTROLLED 0x00000001 /* RW--V */ +#define NV9471_SF_HDMI_INFO_CTRL_VIDEO_FMT_INIT 0x00000001 /* RWI-V */ +#define NV9471_SF_HDMI_INFO_STATUS(i,j) (0x00690004-0x00690000+(i)*1024+(j)*64) /* R--4A */ +#define NV9471_SF_HDMI_INFO_STATUS__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_INFO_STATUS__SIZE_2 5 /* */ +#define NV9471_SF_HDMI_INFO_STATUS_SENT 0:0 /* R--VF */ +#define NV9471_SF_HDMI_INFO_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NV9471_SF_HDMI_INFO_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NV9471_SF_HDMI_INFO_STATUS_SENT_INIT 0x00000000 /* R-I-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x00690000-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x00690008-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x0069000C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x00690010-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x00690014-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x00690018-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_HEADER(i) (0x00690048-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_GENERIC_HEADER__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_GENERIC_HEADER_HB0 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_HEADER_HB1 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_HEADER_HB2 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW(i) (0x0069004C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_HIGH(i) (0x00690050-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW(i) (0x00690054-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_HIGH(i) (0x00690058-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW(i) (0x0069005C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_HIGH(i) (0x00690060-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_HIGH__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW(i) (0x00690064-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24 31:24 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_HIGH(i) (0x00690068-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_HIGH__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GCP_SUBPACK(i) (0x006900CC-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_GCP_SUBPACK__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_GCP_SUBPACK_SB0 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_GCP_SUBPACK_SB0_INIT 0x00000001 /* RWI-V */ +#define NV9471_SF_HDMI_GCP_SUBPACK_SB0_SET_AVMUTE 0x00000001 /* RW--V */ +#define NV9471_SF_HDMI_GCP_SUBPACK_SB0_CLR_AVMUTE 0x00000010 /* RW--V */ +#define NV9471_SF_HDMI_GCP_SUBPACK_SB1 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_GCP_SUBPACK_SB1_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_GCP_SUBPACK_SB2 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_GCP_SUBPACK_SB2_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_HEADER(i) (0x00690108-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_VSI_HEADER__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_VSI_HEADER_HB0 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_HEADER_HB1 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_HEADER_HB2 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW(i) (0x0069010C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_HIGH(i) (0x00690110-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW(i) (0x00690114-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_HIGH(i) (0x00690118-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW(i) (0x0069011C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_HIGH(i) (0x00690120-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_HIGH__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW(i) (0x00690124-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW_PB21 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW_PB22 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW_PB23 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW_PB24 31:24 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_HIGH(i) (0x00690128-0x00690000+(i)*1024) /* RWX4A */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_HIGH__SIZE_1 4 /* */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */ +#define NV9471_SF_HDMI_VSI_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _cl9471_h_ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl947d.h b/userspace/sdks/nv570/nvidia/inc/class/cl947d.h new file mode 100644 index 0000000..6842406 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl947d.h @@ -0,0 +1,1606 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl947d_h_ +#define _cl947d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV947D_CORE_CHANNEL_DMA (0x0000947D) + +#define NV947D_CORE_NOTIFIER_3 0x00000000 +#define NV947D_CORE_NOTIFIER_3_SIZEOF 0x00000150 +#define NV947D_CORE_NOTIFIER_3_COMPLETION_0 0x00000000 +#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_DONE 0:0 +#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_R0 15:1 +#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP 29:16 +#define NV947D_CORE_NOTIFIER_3__1 0x00000001 +#define NV947D_CORE_NOTIFIER_3__1_R1 31:0 +#define NV947D_CORE_NOTIFIER_3__2 0x00000002 +#define NV947D_CORE_NOTIFIER_3__2_R2 31:0 +#define NV947D_CORE_NOTIFIER_3__3 0x00000003 +#define NV947D_CORE_NOTIFIER_3__3_R3 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_R0 19:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA 20:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_R1 29:21 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE 30:30 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5 0x00000005 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE 3:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE 11:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE 15:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE 19:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE 27:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6 0x00000006 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE 3:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE 11:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE 15:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE 19:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE 27:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_UNAVAILABLE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_SCAN_LOCK 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_FLIP_LOCK 0x00000002 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_STEREO 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_7 0x00000007 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_7_R4 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_8 0x00000008 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_8_R5 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_9 0x00000009 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_9_R6 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_10 0x0000000A +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_10_R7 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_11 0x0000000B +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_11_R8 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12 0x0000000C +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0 31:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13 0x0000000D +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14 0x0000000E +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0 31:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15 0x0000000F +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16 0x00000010 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0 31:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17 0x00000011 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18 0x00000012 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0 31:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19 0x00000013 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A 8:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B 9:9 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1 10:10 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS 11:11 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2 12:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3 15:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4 19:17 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A 24:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B 25:25 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE 26:26 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21 0x00000015 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_LVDS_CLK_MAX 23:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R8 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22 0x00000016 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A 8:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B 9:9 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1 10:10 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS 11:11 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2 12:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3 15:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4 19:17 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A 24:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B 25:25 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE 26:26 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23 0x00000017 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_LVDS_CLK_MAX 23:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R8 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24 0x00000018 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A 8:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B 9:9 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1 10:10 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS 11:11 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2 12:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3 15:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4 19:17 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A 24:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B 25:25 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE 26:26 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25 0x00000019 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_LVDS_CLK_MAX 23:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R8 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26 0x0000001A +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A 8:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B 9:9 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1 10:10 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS 11:11 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2 12:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3 15:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4 19:17 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A 24:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B 25:25 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE 26:26 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27 0x0000001B +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_LVDS_CLK_MAX 23:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R8 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28 0x0000001C +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A 8:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B 9:9 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1 10:10 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS 11:11 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2 12:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3 15:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4 19:17 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A 24:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B 25:25 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE 26:26 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29 0x0000001D +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_LVDS_CLK_MAX 23:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R8 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30 0x0000001E +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A 8:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B 9:9 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1 10:10 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS 11:11 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2 12:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3 15:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4 19:17 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A 24:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B 25:25 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE 26:26 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31 0x0000001F +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_LVDS_CLK_MAX 23:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R8 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32 0x00000020 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A 8:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B 9:9 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1 10:10 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS 11:11 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2 12:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3 15:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4 19:17 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A 24:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B 25:25 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE 26:26 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33 0x00000021 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_LVDS_CLK_MAX 23:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R8 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34 0x00000022 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A 8:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B 9:9 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1 10:10 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS 11:11 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2 12:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3 15:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4 19:17 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A 24:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B 25:25 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE 26:26 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35 0x00000023 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_LVDS_CLK_MAX 23:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R8 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36 0x00000024 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0 31:7 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37 0x00000025 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38 0x00000026 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0 31:7 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39 0x00000027 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40 0x00000028 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0 31:7 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41 0x00000029 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42 0x0000002A +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0 31:7 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43 0x0000002B +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44 0x0000002C +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44_R0 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45 0x0000002D +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45_R1 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46 0x0000002E +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46_R0 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47 0x0000002F +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47_R1 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48 0x00000030 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48_R0 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49 0x00000031 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49_R1 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50 0x00000032 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50_R0 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51 0x00000033 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51_R1 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52 0x00000034 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_REORDER_BANK_WIDTH_SIZE_MAX 13:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0 31:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53 0x00000035 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54 0x00000036 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55 0x00000037 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56 0x00000038 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57 0x00000039 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58 0x0000003A +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59 0x0000003B +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60 0x0000003C +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_REORDER_BANK_WIDTH_SIZE_MAX 13:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0 31:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61 0x0000003D +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62 0x0000003E +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63 0x0000003F +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64 0x00000040 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65 0x00000041 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66 0x00000042 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67 0x00000043 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68 0x00000044 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_REORDER_BANK_WIDTH_SIZE_MAX 13:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0 31:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69 0x00000045 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70 0x00000046 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71 0x00000047 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72 0x00000048 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73 0x00000049 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74 0x0000004A +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75 0x0000004B +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76 0x0000004C +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_REORDER_BANK_WIDTH_SIZE_MAX 13:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0 31:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77 0x0000004D +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78 0x0000004E +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79 0x0000004F +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80 0x00000050 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81 0x00000051 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82 0x00000052 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83 0x00000053 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10 31:0 + + +// dma opcode instructions +#define NV947D_DMA 0x00000000 +#define NV947D_DMA_OPCODE 31:29 +#define NV947D_DMA_OPCODE_METHOD 0x00000000 +#define NV947D_DMA_OPCODE_JUMP 0x00000001 +#define NV947D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV947D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV947D_DMA_METHOD_COUNT 27:18 +#define NV947D_DMA_METHOD_OFFSET 11:2 +#define NV947D_DMA_DATA 31:0 +#define NV947D_DMA_DATA_NOP 0x00000000 +#define NV947D_DMA_JUMP_OFFSET 11:2 +#define NV947D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV947D_PUT (0x00000000) +#define NV947D_PUT_PTR 11:2 +#define NV947D_GET (0x00000004) +#define NV947D_GET_PTR 11:2 +#define NV947D_UPDATE (0x00000080) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR(i) (0 +(i)*4):(0 +(i)*4) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1 4 +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0 +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR1 4:4 +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR2 8:8 +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR3 12:12 +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE(i) (1 +(i)*4):(1 +(i)*4) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1 4 +#define NV947D_UPDATE_INTERLOCK_WITH_BASE_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE0 1:1 +#define NV947D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE1 5:5 +#define NV947D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE2 9:9 +#define NV947D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE3 13:13 +#define NV947D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY(i) (2 +(i)*4):(2 +(i)*4) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1 4 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY1 6:6 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY2 10:10 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY3 14:14 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i) (3 +(i)*4):(3 +(i)*4) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1 4 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 7:7 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2 11:11 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3 15:15 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE (0x00000001) +#define NV947D_UPDATE_SPECIAL_HANDLING 25:24 +#define NV947D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV947D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV947D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV947D_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV947D_UPDATE_NOT_DRIVER_FRIENDLY 31:31 +#define NV947D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000) +#define NV947D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001) +#define NV947D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30 +#define NV947D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000) +#define NV947D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001) +#define NV947D_UPDATE_INHIBIT_INTERRUPTS 29:29 +#define NV947D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NV947D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NV947D_SET_NOTIFIER_CONTROL (0x00000084) +#define NV947D_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV947D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV947D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV947D_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV947D_SET_NOTIFIER_CONTROL_NOTIFY 31:31 +#define NV947D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NV947D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NV947D_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV947D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV947D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV947D_SET_CONTEXT_DMA_NOTIFIER (0x00000088) +#define NV947D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV947D_GET_CAPABILITIES (0x0000008C) +#define NV947D_GET_CAPABILITIES_DUMMY 31:0 +#define NV947D_SET_SPARE (0x0000016C) +#define NV947D_SET_SPARE_UNUSED 31:0 +#define NV947D_SET_SPARE_NOOP(b) (0x00000170 + (b)*0x00000004) +#define NV947D_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV947D_DAC_SET_CONTROL(a) (0x00000180 + (a)*0x00000020) +#define NV947D_DAC_SET_CONTROL_OWNER_MASK 3:0 +#define NV947D_DAC_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV947D_DAC_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV947D_DAC_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV947D_DAC_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV947D_DAC_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV947D_DAC_SET_CONTROL_PROTOCOL 12:8 +#define NV947D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV947D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT (0x00000013) +#define NV947D_DAC_SET_SW_SPARE_A(a) (0x00000184 + (a)*0x00000020) +#define NV947D_DAC_SET_SW_SPARE_A_CODE 31:0 +#define NV947D_DAC_SET_SW_SPARE_B(a) (0x00000188 + (a)*0x00000020) +#define NV947D_DAC_SET_SW_SPARE_B_CODE 31:0 +#define NV947D_DAC_SET_CUSTOM_REASON(a) (0x00000190 + (a)*0x00000020) +#define NV947D_DAC_SET_CUSTOM_REASON_CODE 31:0 + +#define NV947D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020) +#define NV947D_SOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV947D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV947D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV947D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV947D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV947D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV947D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV947D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV947D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV947D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV947D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV947D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NV947D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NV947D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV947D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV947D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV947D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV947D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NV947D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NV947D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NV947D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NV947D_SOR_SET_SW_SPARE_A(a) (0x00000204 + (a)*0x00000020) +#define NV947D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NV947D_SOR_SET_SW_SPARE_B(a) (0x00000208 + (a)*0x00000020) +#define NV947D_SOR_SET_SW_SPARE_B_CODE 31:0 +#define NV947D_SOR_SET_CUSTOM_REASON(a) (0x00000210 + (a)*0x00000020) +#define NV947D_SOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV947D_PIOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NV947D_PIOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV947D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV947D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV947D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV947D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV947D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV947D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV947D_PIOR_SET_SW_SPARE_A(a) (0x00000304 + (a)*0x00000020) +#define NV947D_PIOR_SET_SW_SPARE_A_CODE 31:0 +#define NV947D_PIOR_SET_SW_SPARE_B(a) (0x00000308 + (a)*0x00000020) +#define NV947D_PIOR_SET_SW_SPARE_B_CODE 31:0 +#define NV947D_PIOR_SET_CUSTOM_REASON(a) (0x00000310 + (a)*0x00000020) +#define NV947D_PIOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV947D_HEAD_SET_PRESENT_CONTROL(a) (0x00000400 + (a)*0x00000300) +#define NV947D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NV947D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 8:8 +#define NV947D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NV947D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NV947D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00000404 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 3:3 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 4:4 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 9:6 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000009) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 12:12 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 20:13 +#define NV947D_HEAD_SET_CONTROL(a) (0x00000408 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTROL_STRUCTURE 0:0 +#define NV947D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 3:2 +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 19:15 +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV947D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 7:4 +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 9:8 +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 14:10 +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV947D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK 1:1 +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_DISABLE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN 24:20 +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV947D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN 29:25 +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000000) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000001) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000002) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000003) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000004) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000005) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000006) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000007) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000008) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x00000009) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000A) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000B) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000C) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000D) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000E) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x0000000F) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_UNSPECIFIED (0x00000010) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV947D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV947D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NV947D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NV947D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000410 + (a)*0x00000300) +#define NV947D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV947D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV947D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV947D_HEAD_SET_RASTER_SIZE(a) (0x00000414 + (a)*0x00000300) +#define NV947D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV947D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV947D_HEAD_SET_RASTER_SYNC_END(a) (0x00000418 + (a)*0x00000300) +#define NV947D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV947D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV947D_HEAD_SET_RASTER_BLANK_END(a) (0x0000041C + (a)*0x00000300) +#define NV947D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV947D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV947D_HEAD_SET_RASTER_BLANK_START(a) (0x00000420 + (a)*0x00000300) +#define NV947D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV947D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV947D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000424 + (a)*0x00000300) +#define NV947D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV947D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV947D_HEAD_SET_LOCK_CHAIN(a) (0x00000428 + (a)*0x00000300) +#define NV947D_HEAD_SET_LOCK_CHAIN_POSITION 27:24 +#define NV947D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000042C + (a)*0x00000300) +#define NV947D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV947D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV947D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV947D_HEAD_SET_CRC_CONTROL(a) (0x00000430 + (a)*0x00000300) +#define NV947D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 1:0 +#define NV947D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000000) +#define NV947D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_BASE (0x00000001) +#define NV947D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_OVERLAY (0x00000002) +#define NV947D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 2:2 +#define NV947D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NV947D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NV947D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE 3:3 +#define NV947D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_FALSE (0x00000000) +#define NV947D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_TRUE (0x00000001) +#define NV947D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE 4:4 +#define NV947D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_FALSE (0x00000000) +#define NV947D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_TRUE (0x00000001) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT 19:8 +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC__SIZE_1 4 +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC0 (0x00000FF0) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC1 (0x00000FF1) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC2 (0x00000FF2) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC3 (0x00000FF3) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG__SIZE_1 4 +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG0 (0x00000FF8) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG1 (0x00000FF9) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG2 (0x00000FFA) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG3 (0x00000FFB) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR__SIZE_1 8 +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR0 (0x00000F0F) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR1 (0x00000F1F) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR2 (0x00000F2F) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR3 (0x00000F3F) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR4 (0x00000F4F) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR5 (0x00000F5F) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR6 (0x00000F6F) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR7 (0x00000F7F) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF__SIZE_1 4 +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF0 (0x00000F8F) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF1 (0x00000F9F) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF2 (0x00000FAF) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF3 (0x00000FBF) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR__SIZE_1 8 +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR0 (0x000000FF) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR1 (0x000001FF) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR2 (0x000002FF) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR3 (0x000003FF) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR4 (0x000004FF) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR5 (0x000005FF) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR6 (0x000006FF) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR7 (0x000007FF) +#define NV947D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_NONE (0x00000FFF) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT 31:20 +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC__SIZE_1 4 +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC0 (0x00000FF0) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC1 (0x00000FF1) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC2 (0x00000FF2) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC3 (0x00000FF3) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG__SIZE_1 4 +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG0 (0x00000FF8) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG1 (0x00000FF9) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG2 (0x00000FFA) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG3 (0x00000FFB) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR__SIZE_1 8 +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR0 (0x00000F0F) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR1 (0x00000F1F) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR2 (0x00000F2F) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR3 (0x00000F3F) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR4 (0x00000F4F) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR5 (0x00000F5F) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR6 (0x00000F6F) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR7 (0x00000F7F) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF__SIZE_1 4 +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF0 (0x00000F8F) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF1 (0x00000F9F) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF2 (0x00000FAF) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF3 (0x00000FBF) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR__SIZE_1 8 +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR0 (0x000000FF) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR1 (0x000001FF) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR2 (0x000002FF) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR3 (0x000003FF) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR4 (0x000004FF) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR5 (0x000005FF) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR6 (0x000006FF) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR7 (0x000007FF) +#define NV947D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_NONE (0x00000FFF) +#define NV947D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 5:5 +#define NV947D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC 6:6 +#define NV947D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_DISABLE (0x00000000) +#define NV947D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00000438 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NV947D_HEAD_SET_BASE_LUT_LO(a) (0x00000440 + (a)*0x00000300) +#define NV947D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV947D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE 27:24 +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV947D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV947D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_BASE_LUT_HI(a) (0x00000444 + (a)*0x00000300) +#define NV947D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV947D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000448 + (a)*0x00000300) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000044C + (a)*0x00000300) +#define NV947D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x00000450 + (a)*0x00000300) +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x00000454 + (a)*0x00000300) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE 21:20 +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25 (0x00000000) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28 (0x00000001) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM (0x00000002) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 24:24 +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING 25:25 +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE (0x00000000) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE (0x00000001) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 26:26 +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00000458 + (a)*0x00000300) +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NV947D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000045C + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV947D_HEAD_SET_OFFSET(a) (0x00000460 + (a)*0x00000300) +#define NV947D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV947D_HEAD_SET_SIZE(a) (0x00000468 + (a)*0x00000300) +#define NV947D_HEAD_SET_SIZE_WIDTH 15:0 +#define NV947D_HEAD_SET_SIZE_HEIGHT 31:16 +#define NV947D_HEAD_SET_STORAGE(a) (0x0000046C + (a)*0x00000300) +#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV947D_HEAD_SET_STORAGE_PITCH 20:8 +#define NV947D_HEAD_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV947D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV947D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV947D_HEAD_SET_PARAMS(a) (0x00000470 + (a)*0x00000300) +#define NV947D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV947D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV947D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV947D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV947D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV947D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV947D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV947D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV947D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024) +#define NV947D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV947D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV947D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV947D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV947D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV947D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV947D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV947D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV947D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV947D_HEAD_SET_PARAMS_GAMMA 2:2 +#define NV947D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV947D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV947D_HEAD_SET_CONTEXT_DMAS_ISO(a) (0x00000474 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV947D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x0000047C + (a)*0x00000300) +#define NV947D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 1:0 +#define NV947D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NV947D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NV947D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_SPEC_FLIP (0x00000002) +#define NV947D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV947D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV947D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV947D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE 27:26 +#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NV947D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 15:8 +#define NV947D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 23:16 +#define NV947D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV947D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV947D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV947D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV947D_HEAD_SET_OFFSETS_CURSOR(a,b) (0x00000484 + (a)*0x00000300 + (b)*0x00000004) +#define NV947D_HEAD_SET_OFFSETS_CURSOR_ORIGIN 31:0 +#define NV947D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b) (0x0000048C + (a)*0x00000300 + (b)*0x00000004) +#define NV947D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE 31:0 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00000494 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422 8:8 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE (0x00000001) +#define NV947D_HEAD_SET_PROCAMP(a) (0x00000498 + (a)*0x00000300) +#define NV947D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV947D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV947D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV947D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV947D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV947D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV947D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV947D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV947D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV947D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 5:5 +#define NV947D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NV947D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NV947D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 6:6 +#define NV947D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) +#define NV947D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) +#define NV947D_HEAD_SET_DITHER_CONTROL(a) (0x000004A0 + (a)*0x00000300) +#define NV947D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV947D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV947D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV947D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV947D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002) +#define NV947D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NV947D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV947D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x000004B0 + (a)*0x00000300) +#define NV947D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV947D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV947D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000004B8 + (a)*0x00000300) +#define NV947D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV947D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV947D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x000004BC + (a)*0x00000300) +#define NV947D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NV947D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000004C0 + (a)*0x00000300) +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000004C4 + (a)*0x00000300) +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a) (0x000004C8 + (a)*0x00000300) +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH 14:0 +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT 30:16 +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT 17:16 +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE (0x00000000) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257 (0x00000001) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025 (0x00000002) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT 21:20 +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x000004D4 + (a)*0x00000300) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT 13:12 +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE (0x00000000) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257 (0x00000001) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025 (0x00000002) +#define NV947D_HEAD_SET_PROCESSING(a) (0x000004E0 + (a)*0x00000300) +#define NV947D_HEAD_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV947D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV947D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CONVERSION_RED(a) (0x000004E4 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONVERSION_RED_GAIN 15:0 +#define NV947D_HEAD_SET_CONVERSION_RED_OFS 31:16 +#define NV947D_HEAD_SET_CONVERSION_GRN(a) (0x000004E8 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONVERSION_GRN_GAIN 15:0 +#define NV947D_HEAD_SET_CONVERSION_GRN_OFS 31:16 +#define NV947D_HEAD_SET_CONVERSION_BLU(a) (0x000004EC + (a)*0x00000300) +#define NV947D_HEAD_SET_CONVERSION_BLU_GAIN 15:0 +#define NV947D_HEAD_SET_CONVERSION_BLU_OFS 31:16 +#define NV947D_HEAD_SET_CSC_RED2RED(a) (0x000004F0 + (a)*0x00000300) +#define NV947D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE 31:31 +#define NV947D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CSC_RED2RED_COEFF 18:0 +#define NV947D_HEAD_SET_CSC_GRN2RED(a) (0x000004F4 + (a)*0x00000300) +#define NV947D_HEAD_SET_CSC_GRN2RED_COEFF 18:0 +#define NV947D_HEAD_SET_CSC_BLU2RED(a) (0x000004F8 + (a)*0x00000300) +#define NV947D_HEAD_SET_CSC_BLU2RED_COEFF 18:0 +#define NV947D_HEAD_SET_CSC_CONSTANT2RED(a) (0x000004FC + (a)*0x00000300) +#define NV947D_HEAD_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV947D_HEAD_SET_CSC_RED2GRN(a) (0x00000500 + (a)*0x00000300) +#define NV947D_HEAD_SET_CSC_RED2GRN_COEFF 18:0 +#define NV947D_HEAD_SET_CSC_GRN2GRN(a) (0x00000504 + (a)*0x00000300) +#define NV947D_HEAD_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV947D_HEAD_SET_CSC_BLU2GRN(a) (0x00000508 + (a)*0x00000300) +#define NV947D_HEAD_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV947D_HEAD_SET_CSC_CONSTANT2GRN(a) (0x0000050C + (a)*0x00000300) +#define NV947D_HEAD_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV947D_HEAD_SET_CSC_RED2BLU(a) (0x00000510 + (a)*0x00000300) +#define NV947D_HEAD_SET_CSC_RED2BLU_COEFF 18:0 +#define NV947D_HEAD_SET_CSC_GRN2BLU(a) (0x00000514 + (a)*0x00000300) +#define NV947D_HEAD_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV947D_HEAD_SET_CSC_BLU2BLU(a) (0x00000518 + (a)*0x00000300) +#define NV947D_HEAD_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV947D_HEAD_SET_CSC_CONSTANT2BLU(a) (0x0000051C + (a)*0x00000300) +#define NV947D_HEAD_SET_CSC_CONSTANT2BLU_COEFF 18:0 +#define NV947D_HEAD_SET_HDMI_CTRL(a) (0x00000520 + (a)*0x00000300) +#define NV947D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NV947D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NV947D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NV947D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NV947D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NV947D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE 15:12 +#define NV947D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000000) +#define NV947D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FIELD_ALTERNATIVE (0x00000001) +#define NV947D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_LINE_ALTERNATIVE (0x00000002) +#define NV947D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_FULL (0x00000003) +#define NV947D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH (0x00000004) +#define NV947D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH_GRAPHICS (0x00000005) +#define NV947D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_TOP_AND_BOTTOM (0x00000006) +#define NV947D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_HALF (0x00000008) +#define NV947D_HEAD_SET_VACTIVE_SPACE_COLOR(a) (0x00000524 + (a)*0x00000300) +#define NV947D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR 9:0 +#define NV947D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y 19:10 +#define NV947D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB 29:20 +#define NV947D_HEAD_SET_PIXEL_REORDER_CONTROL(a) (0x00000528 + (a)*0x00000300) +#define NV947D_HEAD_SET_PIXEL_REORDER_CONTROL_BANK_WIDTH 13:0 +#define NV947D_HEAD_SET_DISPLAY_ID(a,b) (0x0000052C + (a)*0x00000300 + (b)*0x00000004) +#define NV947D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NV947D_HEAD_SET_SW_SPARE_A(a) (0x0000054C + (a)*0x00000300) +#define NV947D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NV947D_HEAD_SET_SW_SPARE_B(a) (0x00000550 + (a)*0x00000300) +#define NV947D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NV947D_HEAD_SET_SW_SPARE_C(a) (0x00000554 + (a)*0x00000300) +#define NV947D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NV947D_HEAD_SET_SW_SPARE_D(a) (0x00000558 + (a)*0x00000300) +#define NV947D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NV947D_HEAD_SET_GET_BLANKING_CTRL(a) (0x0000055C + (a)*0x00000300) +#define NV947D_HEAD_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NV947D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NV947D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NV947D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NV947D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NV947D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CONTROL_COMPRESSION(a) (0x00000560 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_ENABLE 0:0 +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_CHUNK_BANDWIDTH 12:1 +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LAST_BANDWIDTH 24:13 +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA(a) (0x00000564 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY1 7:4 +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY2 11:8 +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY3 15:12 +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA_CHUNK_SIZE 23:16 +#define NV947D_HEAD_SET_STALL_LOCK(a) (0x00000568 + (a)*0x00000300) +#define NV947D_HEAD_SET_STALL_LOCK_ENABLE 0:0 +#define NV947D_HEAD_SET_STALL_LOCK_ENABLE_FALSE (0x00000000) +#define NV947D_HEAD_SET_STALL_LOCK_ENABLE_TRUE (0x00000001) +#define NV947D_HEAD_SET_STALL_LOCK_MODE 1:1 +#define NV947D_HEAD_SET_STALL_LOCK_MODE_CONTINUOUS (0x00000000) +#define NV947D_HEAD_SET_STALL_LOCK_MODE_ONE_SHOT (0x00000001) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN 6:2 +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV947D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV947D_HEAD_SET_STALL_LOCK_UNSTALL_MODE 7:7 +#define NV947D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_CRASH_LOCK (0x00000000) +#define NV947D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_LINE_LOCK (0x00000001) +#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a) (0x000006D0 + (a)*0x00000300) +#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED 31:0 +#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a) (0x000006D4 + (a)*0x00000300) +#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED 31:0 +#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a) (0x000006D8 + (a)*0x00000300) +#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED 31:0 +#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a) (0x000006DC + (a)*0x00000300) +#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED 31:0 +#define NV947D_HEAD_SET_SPARE(a) (0x000006EC + (a)*0x00000300) +#define NV947D_HEAD_SET_SPARE_UNUSED 31:0 +#define NV947D_HEAD_SET_SPARE_NOOP(a,b) (0x000006F0 + (a)*0x00000300 + (b)*0x00000004) +#define NV947D_HEAD_SET_SPARE_NOOP_UNUSED 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl947d_h diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl9570.h b/userspace/sdks/nv570/nvidia/inc/class/cl9570.h new file mode 100644 index 0000000..00e6d7f --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl9570.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9570.finn +// + +#define NV9570_DISPLAY (0x9570U) /* finn: Evaluated from "NV9570_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV9570_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9570U) + +typedef struct NV9570_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numDacs; // Number of DACs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NV9570_ALLOCATION_PARAMETERS; diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl9571.h b/userspace/sdks/nv570/nvidia/inc/class/cl9571.h new file mode 100644 index 0000000..be40b1f --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl9571.h @@ -0,0 +1,295 @@ +/* + * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl9571_h_ +#define _cl9571_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV9571_DISP_SF_USER 0x9571 + +typedef volatile struct _cl9571_tag0 { + NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x00690FFF:0x00690000 */ +} _Nv9571DispSfUser, Nv9571DispSfUserMap; + +#define NV9571_SF_HDMI_INFO_IDX_AVI_INFOFRAME 0x00000000 /* */ +#define NV9571_SF_HDMI_INFO_IDX_GENERIC_INFOFRAME 0x00000001 /* */ +#define NV9571_SF_HDMI_INFO_IDX_GCP 0x00000003 /* */ +#define NV9571_SF_HDMI_INFO_IDX_VSI 0x00000004 /* */ +#define NV9571_SF_HDMI_INFO_CTRL(i,j) (0x00690000-0x00690000+(i)*1024+(j)*64) /* RWX4A */ +#define NV9571_SF_HDMI_INFO_CTRL__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_INFO_CTRL__SIZE_2 5 /* */ +#define NV9571_SF_HDMI_INFO_CTRL_ENABLE 0:0 /* RWIVF */ +#define NV9571_SF_HDMI_INFO_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_INFO_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NV9571_SF_HDMI_INFO_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NV9571_SF_HDMI_INFO_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NV9571_SF_HDMI_INFO_CTRL_OTHER 4:4 /* RWIVF */ +#define NV9571_SF_HDMI_INFO_CTRL_OTHER_DIS 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_INFO_CTRL_OTHER_EN 0x00000001 /* RW--V */ +#define NV9571_SF_HDMI_INFO_CTRL_SINGLE 8:8 /* RWIVF */ +#define NV9571_SF_HDMI_INFO_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_INFO_CTRL_SINGLE_EN 0x00000001 /* RW--V */ +#define NV9571_SF_HDMI_INFO_CTRL_CHKSUM_HW 9:9 /* RWIVF */ +#define NV9571_SF_HDMI_INFO_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */ +#define NV9571_SF_HDMI_INFO_CTRL_CHKSUM_HW_EN 0x00000001 /* RW--V */ +#define NV9571_SF_HDMI_INFO_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */ +#define NV9571_SF_HDMI_INFO_CTRL_CHKSUM_HW_DIS 0x00000000 /* RW--V */ +#define NV9571_SF_HDMI_INFO_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */ +#define NV9571_SF_HDMI_INFO_CTRL_HBLANK 12:12 /* RWIVF */ +#define NV9571_SF_HDMI_INFO_CTRL_HBLANK_DIS 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_INFO_CTRL_HBLANK_EN 0x00000001 /* RW--V */ +#define NV9571_SF_HDMI_INFO_CTRL_VIDEO_FMT 16:16 /* RWIVF */ +#define NV9571_SF_HDMI_INFO_CTRL_VIDEO_FMT_SW_CONTROLLED 0x00000000 /* RW--V */ +#define NV9571_SF_HDMI_INFO_CTRL_VIDEO_FMT_HW_CONTROLLED 0x00000001 /* RW--V */ +#define NV9571_SF_HDMI_INFO_CTRL_VIDEO_FMT_INIT 0x00000001 /* RWI-V */ +#define NV9571_SF_HDMI_INFO_STATUS(i,j) (0x00690004-0x00690000+(i)*1024+(j)*64) /* R--4A */ +#define NV9571_SF_HDMI_INFO_STATUS__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_INFO_STATUS__SIZE_2 5 /* */ +#define NV9571_SF_HDMI_INFO_STATUS_SENT 0:0 /* R--VF */ +#define NV9571_SF_HDMI_INFO_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NV9571_SF_HDMI_INFO_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NV9571_SF_HDMI_INFO_STATUS_SENT_INIT 0x00000000 /* R-I-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x00690000-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x00690008-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x0069000C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x00690010-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x00690014-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x00690018-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_HEADER(i) (0x00690048-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_GENERIC_HEADER__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_GENERIC_HEADER_HB0 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_HEADER_HB1 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_HEADER_HB2 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW(i) (0x0069004C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_HIGH(i) (0x00690050-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW(i) (0x00690054-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_HIGH(i) (0x00690058-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW(i) (0x0069005C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_HIGH(i) (0x00690060-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_HIGH__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW(i) (0x00690064-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24 31:24 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_HIGH(i) (0x00690068-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_HIGH__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GCP_SUBPACK(i) (0x006900CC-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_GCP_SUBPACK__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_GCP_SUBPACK_SB0 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_GCP_SUBPACK_SB0_INIT 0x00000001 /* RWI-V */ +#define NV9571_SF_HDMI_GCP_SUBPACK_SB0_SET_AVMUTE 0x00000001 /* RW--V */ +#define NV9571_SF_HDMI_GCP_SUBPACK_SB0_CLR_AVMUTE 0x00000010 /* RW--V */ +#define NV9571_SF_HDMI_GCP_SUBPACK_SB1 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_GCP_SUBPACK_SB1_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_GCP_SUBPACK_SB2 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_GCP_SUBPACK_SB2_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_HEADER(i) (0x00690108-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_VSI_HEADER__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_VSI_HEADER_HB0 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_HEADER_HB1 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_HEADER_HB2 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW(i) (0x0069010C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_HIGH(i) (0x00690110-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_HIGH__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW(i) (0x00690114-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_HIGH(i) (0x00690118-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_HIGH__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW(i) (0x0069011C-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_HIGH(i) (0x00690120-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_HIGH__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW(i) (0x00690124-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW_PB21 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW_PB22 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW_PB23 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW_PB24 31:24 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_HIGH(i) (0x00690128-0x00690000+(i)*1024) /* RWX4A */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_HIGH__SIZE_1 4 /* */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */ +#define NV9571_SF_HDMI_VSI_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _cl9571_h_ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl957d.h b/userspace/sdks/nv570/nvidia/inc/class/cl957d.h new file mode 100644 index 0000000..ea10694 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl957d.h @@ -0,0 +1,1602 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl957d_h_ +#define _cl957d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV957D_CORE_CHANNEL_DMA (0x0000957D) + +#define NV957D_CORE_NOTIFIER_3 0x00000000 +#define NV957D_CORE_NOTIFIER_3_SIZEOF 0x00000150 +#define NV957D_CORE_NOTIFIER_3_COMPLETION_0 0x00000000 +#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_DONE 0:0 +#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_R0 15:1 +#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP 29:16 +#define NV957D_CORE_NOTIFIER_3__1 0x00000001 +#define NV957D_CORE_NOTIFIER_3__1_R1 31:0 +#define NV957D_CORE_NOTIFIER_3__2 0x00000002 +#define NV957D_CORE_NOTIFIER_3__2_R2 31:0 +#define NV957D_CORE_NOTIFIER_3__3 0x00000003 +#define NV957D_CORE_NOTIFIER_3__3_R3 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_R0 19:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA 20:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_R1 29:21 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE 30:30 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5 0x00000005 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE 3:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE 11:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE 15:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE 19:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE 27:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6 0x00000006 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE 3:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE 11:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE 15:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE 19:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE 27:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_UNAVAILABLE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_SCAN_LOCK 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_FLIP_LOCK 0x00000002 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_STEREO 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_7 0x00000007 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_7_R4 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_8 0x00000008 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_8_R5 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_9 0x00000009 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_9_R6 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_10 0x0000000A +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_10_R7 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_11 0x0000000B +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_11_R8 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12 0x0000000C +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0 31:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13 0x0000000D +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14 0x0000000E +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0 31:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15 0x0000000F +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16 0x00000010 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0 31:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17 0x00000011 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18 0x00000012 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0 31:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19 0x00000013 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A 8:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B 9:9 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1 10:10 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS 11:11 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2 13:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3 16:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4 19:17 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A 24:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B 25:25 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE 26:26 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21 0x00000015 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_CLK_MAX 23:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_LVDS_CLK_MAX 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22 0x00000016 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A 8:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B 9:9 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1 10:10 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS 11:11 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2 13:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3 16:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4 19:17 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A 24:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B 25:25 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE 26:26 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23 0x00000017 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_CLK_MAX 23:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_LVDS_CLK_MAX 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24 0x00000018 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A 8:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B 9:9 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1 10:10 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS 11:11 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2 13:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3 16:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4 19:17 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A 24:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B 25:25 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE 26:26 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25 0x00000019 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_CLK_MAX 23:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_LVDS_CLK_MAX 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26 0x0000001A +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A 8:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B 9:9 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1 10:10 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS 11:11 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2 13:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3 16:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4 19:17 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A 24:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B 25:25 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE 26:26 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27 0x0000001B +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_CLK_MAX 23:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_LVDS_CLK_MAX 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28 0x0000001C +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A 8:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B 9:9 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1 10:10 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS 11:11 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2 13:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3 16:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4 19:17 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A 24:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B 25:25 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE 26:26 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29 0x0000001D +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_CLK_MAX 23:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_LVDS_CLK_MAX 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30 0x0000001E +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A 8:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B 9:9 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1 10:10 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS 11:11 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2 13:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3 16:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4 19:17 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A 24:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B 25:25 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE 26:26 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31 0x0000001F +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_CLK_MAX 23:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_LVDS_CLK_MAX 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32 0x00000020 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A 8:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B 9:9 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1 10:10 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS 11:11 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2 13:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3 16:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4 19:17 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A 24:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B 25:25 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE 26:26 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33 0x00000021 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_CLK_MAX 23:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_LVDS_CLK_MAX 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34 0x00000022 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A 8:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B 9:9 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1 10:10 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS 11:11 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2 13:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3 16:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4 19:17 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A 24:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B 25:25 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE 26:26 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35 0x00000023 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_CLK_MAX 23:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_LVDS_CLK_MAX 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36 0x00000024 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0 31:7 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37 0x00000025 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38 0x00000026 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0 31:7 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39 0x00000027 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40 0x00000028 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0 31:7 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41 0x00000029 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42 0x0000002A +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0 31:7 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43 0x0000002B +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44 0x0000002C +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44_R0 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45 0x0000002D +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45_R1 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46 0x0000002E +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46_R0 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47 0x0000002F +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47_R1 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48 0x00000030 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48_R0 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49 0x00000031 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49_R1 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50 0x00000032 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50_R0 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51 0x00000033 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51_R1 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52 0x00000034 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0 31:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53 0x00000035 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54 0x00000036 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55 0x00000037 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56 0x00000038 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57 0x00000039 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58 0x0000003A +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59 0x0000003B +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60 0x0000003C +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0 31:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61 0x0000003D +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62 0x0000003E +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63 0x0000003F +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64 0x00000040 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65 0x00000041 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66 0x00000042 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67 0x00000043 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68 0x00000044 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0 31:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69 0x00000045 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70 0x00000046 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71 0x00000047 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72 0x00000048 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73 0x00000049 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74 0x0000004A +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75 0x0000004B +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76 0x0000004C +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0 31:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77 0x0000004D +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78 0x0000004E +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79 0x0000004F +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80 0x00000050 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81 0x00000051 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82 0x00000052 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83 0x00000053 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10 31:0 + + +// dma opcode instructions +#define NV957D_DMA 0x00000000 +#define NV957D_DMA_OPCODE 31:29 +#define NV957D_DMA_OPCODE_METHOD 0x00000000 +#define NV957D_DMA_OPCODE_JUMP 0x00000001 +#define NV957D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV957D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV957D_DMA_METHOD_COUNT 27:18 +#define NV957D_DMA_METHOD_OFFSET 11:2 +#define NV957D_DMA_DATA 31:0 +#define NV957D_DMA_DATA_NOP 0x00000000 +#define NV957D_DMA_JUMP_OFFSET 11:2 +#define NV957D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV957D_PUT (0x00000000) +#define NV957D_PUT_PTR 11:2 +#define NV957D_GET (0x00000004) +#define NV957D_GET_PTR 11:2 +#define NV957D_UPDATE (0x00000080) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR(i) (0 +(i)*4):(0 +(i)*4) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1 4 +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0 +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR1 4:4 +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR2 8:8 +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR3 12:12 +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE(i) (1 +(i)*4):(1 +(i)*4) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1 4 +#define NV957D_UPDATE_INTERLOCK_WITH_BASE_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE0 1:1 +#define NV957D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE1 5:5 +#define NV957D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE2 9:9 +#define NV957D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE3 13:13 +#define NV957D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY(i) (2 +(i)*4):(2 +(i)*4) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1 4 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY1 6:6 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY2 10:10 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY3 14:14 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i) (3 +(i)*4):(3 +(i)*4) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1 4 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 7:7 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2 11:11 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3 15:15 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE (0x00000001) +#define NV957D_UPDATE_SPECIAL_HANDLING 25:24 +#define NV957D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV957D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV957D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV957D_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV957D_UPDATE_NOT_DRIVER_FRIENDLY 31:31 +#define NV957D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000) +#define NV957D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001) +#define NV957D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30 +#define NV957D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000) +#define NV957D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001) +#define NV957D_UPDATE_INHIBIT_INTERRUPTS 29:29 +#define NV957D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NV957D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NV957D_SET_NOTIFIER_CONTROL (0x00000084) +#define NV957D_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV957D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV957D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV957D_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV957D_SET_NOTIFIER_CONTROL_NOTIFY 31:31 +#define NV957D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NV957D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NV957D_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV957D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV957D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV957D_SET_CONTEXT_DMA_NOTIFIER (0x00000088) +#define NV957D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV957D_GET_CAPABILITIES (0x0000008C) +#define NV957D_GET_CAPABILITIES_DUMMY 31:0 +#define NV957D_SET_SPARE (0x0000016C) +#define NV957D_SET_SPARE_UNUSED 31:0 +#define NV957D_SET_SPARE_NOOP(b) (0x00000170 + (b)*0x00000004) +#define NV957D_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV957D_DAC_SET_CONTROL(a) (0x00000180 + (a)*0x00000020) +#define NV957D_DAC_SET_CONTROL_OWNER_MASK 3:0 +#define NV957D_DAC_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV957D_DAC_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV957D_DAC_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV957D_DAC_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV957D_DAC_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV957D_DAC_SET_CONTROL_PROTOCOL 12:8 +#define NV957D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV957D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT (0x00000013) +#define NV957D_DAC_SET_SW_SPARE_A(a) (0x00000184 + (a)*0x00000020) +#define NV957D_DAC_SET_SW_SPARE_A_CODE 31:0 +#define NV957D_DAC_SET_SW_SPARE_B(a) (0x00000188 + (a)*0x00000020) +#define NV957D_DAC_SET_SW_SPARE_B_CODE 31:0 +#define NV957D_DAC_SET_CUSTOM_REASON(a) (0x00000190 + (a)*0x00000020) +#define NV957D_DAC_SET_CUSTOM_REASON_CODE 31:0 + +#define NV957D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020) +#define NV957D_SOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV957D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV957D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV957D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV957D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV957D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV957D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV957D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV957D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV957D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV957D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV957D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NV957D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NV957D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV957D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV957D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV957D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV957D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NV957D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NV957D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NV957D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NV957D_SOR_SET_SW_SPARE_A(a) (0x00000204 + (a)*0x00000020) +#define NV957D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NV957D_SOR_SET_SW_SPARE_B(a) (0x00000208 + (a)*0x00000020) +#define NV957D_SOR_SET_SW_SPARE_B_CODE 31:0 +#define NV957D_SOR_SET_CUSTOM_REASON(a) (0x00000210 + (a)*0x00000020) +#define NV957D_SOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV957D_PIOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NV957D_PIOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV957D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV957D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV957D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV957D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV957D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV957D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV957D_PIOR_SET_SW_SPARE_A(a) (0x00000304 + (a)*0x00000020) +#define NV957D_PIOR_SET_SW_SPARE_A_CODE 31:0 +#define NV957D_PIOR_SET_SW_SPARE_B(a) (0x00000308 + (a)*0x00000020) +#define NV957D_PIOR_SET_SW_SPARE_B_CODE 31:0 +#define NV957D_PIOR_SET_CUSTOM_REASON(a) (0x00000310 + (a)*0x00000020) +#define NV957D_PIOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV957D_HEAD_SET_PRESENT_CONTROL(a) (0x00000400 + (a)*0x00000300) +#define NV957D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NV957D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 8:8 +#define NV957D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NV957D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NV957D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00000404 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 3:3 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 4:4 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 9:6 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000009) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 12:12 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 20:13 +#define NV957D_HEAD_SET_CONTROL(a) (0x00000408 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTROL_STRUCTURE 0:0 +#define NV957D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 3:2 +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 19:15 +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV957D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 7:4 +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 9:8 +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 14:10 +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV957D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK 1:1 +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_DISABLE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN 24:20 +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV957D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN 29:25 +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000000) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000001) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000002) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000003) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000004) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000005) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000006) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000007) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000008) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x00000009) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000A) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000B) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000C) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000D) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000E) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x0000000F) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_UNSPECIFIED (0x00000010) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV957D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV957D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NV957D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NV957D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000410 + (a)*0x00000300) +#define NV957D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV957D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV957D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV957D_HEAD_SET_RASTER_SIZE(a) (0x00000414 + (a)*0x00000300) +#define NV957D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV957D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV957D_HEAD_SET_RASTER_SYNC_END(a) (0x00000418 + (a)*0x00000300) +#define NV957D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV957D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV957D_HEAD_SET_RASTER_BLANK_END(a) (0x0000041C + (a)*0x00000300) +#define NV957D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV957D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV957D_HEAD_SET_RASTER_BLANK_START(a) (0x00000420 + (a)*0x00000300) +#define NV957D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV957D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV957D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000424 + (a)*0x00000300) +#define NV957D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV957D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV957D_HEAD_SET_LOCK_CHAIN(a) (0x00000428 + (a)*0x00000300) +#define NV957D_HEAD_SET_LOCK_CHAIN_POSITION 27:24 +#define NV957D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000042C + (a)*0x00000300) +#define NV957D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV957D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV957D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV957D_HEAD_SET_CRC_CONTROL(a) (0x00000430 + (a)*0x00000300) +#define NV957D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 1:0 +#define NV957D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000000) +#define NV957D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_BASE (0x00000001) +#define NV957D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_OVERLAY (0x00000002) +#define NV957D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 2:2 +#define NV957D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NV957D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NV957D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE 3:3 +#define NV957D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_FALSE (0x00000000) +#define NV957D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_TRUE (0x00000001) +#define NV957D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE 4:4 +#define NV957D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_FALSE (0x00000000) +#define NV957D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_TRUE (0x00000001) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT 19:8 +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC__SIZE_1 4 +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC0 (0x00000FF0) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC1 (0x00000FF1) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC2 (0x00000FF2) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC3 (0x00000FF3) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG__SIZE_1 4 +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG0 (0x00000FF8) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG1 (0x00000FF9) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG2 (0x00000FFA) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG3 (0x00000FFB) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR__SIZE_1 8 +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR0 (0x00000F0F) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR1 (0x00000F1F) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR2 (0x00000F2F) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR3 (0x00000F3F) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR4 (0x00000F4F) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR5 (0x00000F5F) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR6 (0x00000F6F) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR7 (0x00000F7F) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF__SIZE_1 4 +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF0 (0x00000F8F) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF1 (0x00000F9F) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF2 (0x00000FAF) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF3 (0x00000FBF) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR__SIZE_1 8 +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR0 (0x000000FF) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR1 (0x000001FF) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR2 (0x000002FF) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR3 (0x000003FF) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR4 (0x000004FF) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR5 (0x000005FF) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR6 (0x000006FF) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR7 (0x000007FF) +#define NV957D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_NONE (0x00000FFF) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT 31:20 +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC__SIZE_1 4 +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC0 (0x00000FF0) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC1 (0x00000FF1) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC2 (0x00000FF2) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC3 (0x00000FF3) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG__SIZE_1 4 +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG0 (0x00000FF8) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG1 (0x00000FF9) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG2 (0x00000FFA) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG3 (0x00000FFB) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR__SIZE_1 8 +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR0 (0x00000F0F) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR1 (0x00000F1F) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR2 (0x00000F2F) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR3 (0x00000F3F) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR4 (0x00000F4F) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR5 (0x00000F5F) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR6 (0x00000F6F) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR7 (0x00000F7F) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF__SIZE_1 4 +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF0 (0x00000F8F) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF1 (0x00000F9F) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF2 (0x00000FAF) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF3 (0x00000FBF) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR__SIZE_1 8 +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR0 (0x000000FF) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR1 (0x000001FF) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR2 (0x000002FF) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR3 (0x000003FF) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR4 (0x000004FF) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR5 (0x000005FF) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR6 (0x000006FF) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR7 (0x000007FF) +#define NV957D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_NONE (0x00000FFF) +#define NV957D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 5:5 +#define NV957D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC 6:6 +#define NV957D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_DISABLE (0x00000000) +#define NV957D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00000438 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NV957D_HEAD_SET_BASE_LUT_LO(a) (0x00000440 + (a)*0x00000300) +#define NV957D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV957D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE 27:24 +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV957D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV957D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_BASE_LUT_HI(a) (0x00000444 + (a)*0x00000300) +#define NV957D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV957D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000448 + (a)*0x00000300) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000044C + (a)*0x00000300) +#define NV957D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x00000450 + (a)*0x00000300) +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x00000454 + (a)*0x00000300) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE 21:20 +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25 (0x00000000) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28 (0x00000001) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM (0x00000002) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 24:24 +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING 25:25 +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE (0x00000000) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE (0x00000001) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 26:26 +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00000458 + (a)*0x00000300) +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NV957D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000045C + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV957D_HEAD_SET_OFFSET(a) (0x00000460 + (a)*0x00000300) +#define NV957D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV957D_HEAD_SET_SIZE(a) (0x00000468 + (a)*0x00000300) +#define NV957D_HEAD_SET_SIZE_WIDTH 15:0 +#define NV957D_HEAD_SET_SIZE_HEIGHT 31:16 +#define NV957D_HEAD_SET_STORAGE(a) (0x0000046C + (a)*0x00000300) +#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV957D_HEAD_SET_STORAGE_PITCH 20:8 +#define NV957D_HEAD_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV957D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV957D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV957D_HEAD_SET_PARAMS(a) (0x00000470 + (a)*0x00000300) +#define NV957D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV957D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV957D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV957D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV957D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV957D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV957D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV957D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV957D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024) +#define NV957D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV957D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV957D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV957D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV957D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV957D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV957D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV957D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV957D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV957D_HEAD_SET_PARAMS_GAMMA 2:2 +#define NV957D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV957D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV957D_HEAD_SET_CONTEXT_DMAS_ISO(a) (0x00000474 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV957D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x0000047C + (a)*0x00000300) +#define NV957D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 1:0 +#define NV957D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NV957D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NV957D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_SPEC_FLIP (0x00000002) +#define NV957D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV957D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV957D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV957D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE 27:26 +#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NV957D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 15:8 +#define NV957D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 23:16 +#define NV957D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV957D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV957D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV957D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV957D_HEAD_SET_OFFSETS_CURSOR(a,b) (0x00000484 + (a)*0x00000300 + (b)*0x00000004) +#define NV957D_HEAD_SET_OFFSETS_CURSOR_ORIGIN 31:0 +#define NV957D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b) (0x0000048C + (a)*0x00000300 + (b)*0x00000004) +#define NV957D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE 31:0 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00000494 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422 8:8 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE (0x00000001) +#define NV957D_HEAD_SET_PROCAMP(a) (0x00000498 + (a)*0x00000300) +#define NV957D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV957D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV957D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV957D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV957D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV957D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV957D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV957D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV957D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV957D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 5:5 +#define NV957D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NV957D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NV957D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 6:6 +#define NV957D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) +#define NV957D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) +#define NV957D_HEAD_SET_DITHER_CONTROL(a) (0x000004A0 + (a)*0x00000300) +#define NV957D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV957D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV957D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV957D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV957D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002) +#define NV957D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NV957D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV957D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x000004B0 + (a)*0x00000300) +#define NV957D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV957D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV957D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000004B8 + (a)*0x00000300) +#define NV957D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV957D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV957D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x000004BC + (a)*0x00000300) +#define NV957D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NV957D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000004C0 + (a)*0x00000300) +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000004C4 + (a)*0x00000300) +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a) (0x000004C8 + (a)*0x00000300) +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH 14:0 +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT 30:16 +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT 17:16 +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE (0x00000000) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257 (0x00000001) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025 (0x00000002) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT 21:20 +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x000004D4 + (a)*0x00000300) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT 13:12 +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE (0x00000000) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257 (0x00000001) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025 (0x00000002) +#define NV957D_HEAD_SET_PROCESSING(a) (0x000004E0 + (a)*0x00000300) +#define NV957D_HEAD_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV957D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV957D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CONVERSION_RED(a) (0x000004E4 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONVERSION_RED_GAIN 15:0 +#define NV957D_HEAD_SET_CONVERSION_RED_OFS 31:16 +#define NV957D_HEAD_SET_CONVERSION_GRN(a) (0x000004E8 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONVERSION_GRN_GAIN 15:0 +#define NV957D_HEAD_SET_CONVERSION_GRN_OFS 31:16 +#define NV957D_HEAD_SET_CONVERSION_BLU(a) (0x000004EC + (a)*0x00000300) +#define NV957D_HEAD_SET_CONVERSION_BLU_GAIN 15:0 +#define NV957D_HEAD_SET_CONVERSION_BLU_OFS 31:16 +#define NV957D_HEAD_SET_CSC_RED2RED(a) (0x000004F0 + (a)*0x00000300) +#define NV957D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE 31:31 +#define NV957D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CSC_RED2RED_COEFF 18:0 +#define NV957D_HEAD_SET_CSC_GRN2RED(a) (0x000004F4 + (a)*0x00000300) +#define NV957D_HEAD_SET_CSC_GRN2RED_COEFF 18:0 +#define NV957D_HEAD_SET_CSC_BLU2RED(a) (0x000004F8 + (a)*0x00000300) +#define NV957D_HEAD_SET_CSC_BLU2RED_COEFF 18:0 +#define NV957D_HEAD_SET_CSC_CONSTANT2RED(a) (0x000004FC + (a)*0x00000300) +#define NV957D_HEAD_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV957D_HEAD_SET_CSC_RED2GRN(a) (0x00000500 + (a)*0x00000300) +#define NV957D_HEAD_SET_CSC_RED2GRN_COEFF 18:0 +#define NV957D_HEAD_SET_CSC_GRN2GRN(a) (0x00000504 + (a)*0x00000300) +#define NV957D_HEAD_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV957D_HEAD_SET_CSC_BLU2GRN(a) (0x00000508 + (a)*0x00000300) +#define NV957D_HEAD_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV957D_HEAD_SET_CSC_CONSTANT2GRN(a) (0x0000050C + (a)*0x00000300) +#define NV957D_HEAD_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV957D_HEAD_SET_CSC_RED2BLU(a) (0x00000510 + (a)*0x00000300) +#define NV957D_HEAD_SET_CSC_RED2BLU_COEFF 18:0 +#define NV957D_HEAD_SET_CSC_GRN2BLU(a) (0x00000514 + (a)*0x00000300) +#define NV957D_HEAD_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV957D_HEAD_SET_CSC_BLU2BLU(a) (0x00000518 + (a)*0x00000300) +#define NV957D_HEAD_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV957D_HEAD_SET_CSC_CONSTANT2BLU(a) (0x0000051C + (a)*0x00000300) +#define NV957D_HEAD_SET_CSC_CONSTANT2BLU_COEFF 18:0 +#define NV957D_HEAD_SET_HDMI_CTRL(a) (0x00000520 + (a)*0x00000300) +#define NV957D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NV957D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NV957D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NV957D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NV957D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NV957D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE 15:12 +#define NV957D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000000) +#define NV957D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FIELD_ALTERNATIVE (0x00000001) +#define NV957D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_LINE_ALTERNATIVE (0x00000002) +#define NV957D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_FULL (0x00000003) +#define NV957D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH (0x00000004) +#define NV957D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH_GRAPHICS (0x00000005) +#define NV957D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_TOP_AND_BOTTOM (0x00000006) +#define NV957D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_HALF (0x00000008) +#define NV957D_HEAD_SET_VACTIVE_SPACE_COLOR(a) (0x00000524 + (a)*0x00000300) +#define NV957D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR 9:0 +#define NV957D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y 19:10 +#define NV957D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB 29:20 +#define NV957D_HEAD_SET_PIXEL_REORDER_CONTROL(a) (0x00000528 + (a)*0x00000300) +#define NV957D_HEAD_SET_PIXEL_REORDER_CONTROL_BANK_WIDTH 13:0 +#define NV957D_HEAD_SET_DISPLAY_ID(a,b) (0x0000052C + (a)*0x00000300 + (b)*0x00000004) +#define NV957D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NV957D_HEAD_SET_SW_SPARE_A(a) (0x0000054C + (a)*0x00000300) +#define NV957D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NV957D_HEAD_SET_SW_SPARE_B(a) (0x00000550 + (a)*0x00000300) +#define NV957D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NV957D_HEAD_SET_SW_SPARE_C(a) (0x00000554 + (a)*0x00000300) +#define NV957D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NV957D_HEAD_SET_SW_SPARE_D(a) (0x00000558 + (a)*0x00000300) +#define NV957D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NV957D_HEAD_SET_GET_BLANKING_CTRL(a) (0x0000055C + (a)*0x00000300) +#define NV957D_HEAD_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NV957D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NV957D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NV957D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NV957D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NV957D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CONTROL_COMPRESSION(a) (0x00000560 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_ENABLE 0:0 +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_CHUNK_BANDWIDTH 12:1 +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LAST_BANDWIDTH 24:13 +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA(a) (0x00000564 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY1 7:4 +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY2 11:8 +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY3 15:12 +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA_CHUNK_SIZE 23:16 +#define NV957D_HEAD_SET_STALL_LOCK(a) (0x00000568 + (a)*0x00000300) +#define NV957D_HEAD_SET_STALL_LOCK_ENABLE 0:0 +#define NV957D_HEAD_SET_STALL_LOCK_ENABLE_FALSE (0x00000000) +#define NV957D_HEAD_SET_STALL_LOCK_ENABLE_TRUE (0x00000001) +#define NV957D_HEAD_SET_STALL_LOCK_MODE 1:1 +#define NV957D_HEAD_SET_STALL_LOCK_MODE_CONTINUOUS (0x00000000) +#define NV957D_HEAD_SET_STALL_LOCK_MODE_ONE_SHOT (0x00000001) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN 6:2 +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV957D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV957D_HEAD_SET_STALL_LOCK_UNSTALL_MODE 7:7 +#define NV957D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_CRASH_LOCK (0x00000000) +#define NV957D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_LINE_LOCK (0x00000001) +#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a) (0x000006D0 + (a)*0x00000300) +#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED 31:0 +#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a) (0x000006D4 + (a)*0x00000300) +#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED 31:0 +#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a) (0x000006D8 + (a)*0x00000300) +#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED 31:0 +#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a) (0x000006DC + (a)*0x00000300) +#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED 31:0 +#define NV957D_HEAD_SET_SPARE(a) (0x000006EC + (a)*0x00000300) +#define NV957D_HEAD_SET_SPARE_UNUSED 31:0 +#define NV957D_HEAD_SET_SPARE_NOOP(a,b) (0x000006F0 + (a)*0x00000300 + (b)*0x00000004) +#define NV957D_HEAD_SET_SPARE_NOOP_UNUSED 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl957d_h diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl9770.h b/userspace/sdks/nv570/nvidia/inc/class/cl9770.h new file mode 100644 index 0000000..914838f --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl9770.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9770.finn +// + +#define NV9770_DISPLAY (0x9770U) /* finn: Evaluated from "NV9770_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV9770_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9770U) + +typedef struct NV9770_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numDacs; // Number of DACs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NV9770_ALLOCATION_PARAMETERS; diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl977d.h b/userspace/sdks/nv570/nvidia/inc/class/cl977d.h new file mode 100644 index 0000000..adf59a2 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl977d.h @@ -0,0 +1,1587 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl977d_h_ +#define _cl977d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV977D_CORE_CHANNEL_DMA (0x0000977D) + +#define NV977D_CORE_NOTIFIER_3 0x00000000 +#define NV977D_CORE_NOTIFIER_3_SIZEOF 0x00000150 +#define NV977D_CORE_NOTIFIER_3_COMPLETION_0 0x00000000 +#define NV977D_CORE_NOTIFIER_3_COMPLETION_0_DONE 0:0 +#define NV977D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_COMPLETION_0_R0 15:1 +#define NV977D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP 29:16 +#define NV977D_CORE_NOTIFIER_3__1 0x00000001 +#define NV977D_CORE_NOTIFIER_3__1_R1 31:0 +#define NV977D_CORE_NOTIFIER_3__2 0x00000002 +#define NV977D_CORE_NOTIFIER_3__2_R2 31:0 +#define NV977D_CORE_NOTIFIER_3__3 0x00000003 +#define NV977D_CORE_NOTIFIER_3__3_R3 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO 2:2 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_R0 19:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA 20:20 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_R1 29:21 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE 30:30 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5 0x00000005 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE 3:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE 7:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE 11:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE 15:12 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE 19:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE 23:20 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE 27:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE 31:28 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6 0x00000006 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE 3:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE 7:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE 11:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE 15:12 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE 19:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE 23:20 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE 27:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE 31:28 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_UNAVAILABLE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_SCAN_LOCK 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_FLIP_LOCK 0x00000002 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_STEREO 0x00000004 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_7 0x00000007 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_7_R4 31:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_8 0x00000008 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_8_R5 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_9 0x00000009 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_9_R6 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_10 0x0000000A +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_10_R7 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_11 0x0000000B +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_11_R8 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12 0x0000000C +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE 3:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0 31:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13 0x0000000D +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1 31:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14 0x0000000E +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE 3:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0 31:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15 0x0000000F +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1 31:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16 0x00000010 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE 3:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0 31:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17 0x00000011 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1 31:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18 0x00000012 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE 3:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0 31:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19 0x00000013 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1 31:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18 2:2 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24 3:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0 7:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A 8:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B 9:9 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1 10:10 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS 11:11 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2 13:12 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3 16:14 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4 19:17 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5 23:20 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A 24:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B 25:25 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE 26:26 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6 31:28 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21 0x00000015 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7 15:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_CLK_MAX 23:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_LVDS_CLK_MAX 31:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22 0x00000016 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18 2:2 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24 3:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0 7:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A 8:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B 9:9 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1 10:10 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS 11:11 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2 13:12 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3 16:14 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4 19:17 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5 23:20 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A 24:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B 25:25 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE 26:26 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6 31:28 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23 0x00000017 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7 15:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_CLK_MAX 23:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_LVDS_CLK_MAX 31:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24 0x00000018 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18 2:2 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24 3:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0 7:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A 8:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B 9:9 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1 10:10 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS 11:11 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2 13:12 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3 16:14 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4 19:17 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5 23:20 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A 24:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B 25:25 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE 26:26 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6 31:28 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25 0x00000019 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7 15:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_CLK_MAX 23:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_LVDS_CLK_MAX 31:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26 0x0000001A +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18 2:2 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24 3:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0 7:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A 8:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B 9:9 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1 10:10 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS 11:11 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2 13:12 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3 16:14 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4 19:17 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5 23:20 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A 24:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B 25:25 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE 26:26 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6 31:28 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27 0x0000001B +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7 15:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_CLK_MAX 23:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_LVDS_CLK_MAX 31:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28 0x0000001C +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18 2:2 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24 3:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0 7:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A 8:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B 9:9 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1 10:10 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS 11:11 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2 13:12 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3 16:14 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4 19:17 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5 23:20 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A 24:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B 25:25 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE 26:26 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6 31:28 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29 0x0000001D +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7 15:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_CLK_MAX 23:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_LVDS_CLK_MAX 31:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30 0x0000001E +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18 2:2 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24 3:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0 7:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A 8:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B 9:9 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1 10:10 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS 11:11 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2 13:12 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3 16:14 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4 19:17 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5 23:20 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A 24:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B 25:25 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE 26:26 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6 31:28 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31 0x0000001F +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7 15:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_CLK_MAX 23:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_LVDS_CLK_MAX 31:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32 0x00000020 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18 2:2 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24 3:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0 7:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A 8:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B 9:9 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1 10:10 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS 11:11 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2 13:12 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3 16:14 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4 19:17 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5 23:20 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A 24:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B 25:25 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE 26:26 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6 31:28 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33 0x00000021 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7 15:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_CLK_MAX 23:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_LVDS_CLK_MAX 31:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34 0x00000022 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18 2:2 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24 3:3 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0 7:4 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A 8:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B 9:9 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1 10:10 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS 11:11 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2 13:12 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3 16:14 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4 19:17 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5 23:20 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A 24:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B 25:25 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE 26:26 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6 31:28 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35 0x00000023 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7 15:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_CLK_MAX 23:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_LVDS_CLK_MAX 31:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36 0x00000024 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0 31:7 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37 0x00000025 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1 15:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2 31:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38 0x00000026 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0 31:7 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39 0x00000027 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1 15:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2 31:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40 0x00000028 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0 31:7 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41 0x00000029 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1 15:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2 31:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42 0x0000002A +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC 0:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC 1:1 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0 31:7 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43 0x0000002B +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1 15:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2 31:24 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52 0x00000034 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0 31:14 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53 0x00000035 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444 14:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1 15:15 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422 30:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54 0x00000036 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444 14:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3 15:15 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422 30:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55 0x00000037 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444 14:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5 15:15 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422 30:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56 0x00000038 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7 31:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57 0x00000039 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58 0x0000003A +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59 0x0000003B +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60 0x0000003C +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0 31:14 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61 0x0000003D +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444 14:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1 15:15 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422 30:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62 0x0000003E +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444 14:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3 15:15 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422 30:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63 0x0000003F +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444 14:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5 15:15 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422 30:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64 0x00000040 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7 31:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65 0x00000041 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66 0x00000042 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67 0x00000043 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68 0x00000044 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0 31:14 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69 0x00000045 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444 14:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1 15:15 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422 30:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70 0x00000046 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444 14:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3 15:15 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422 30:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71 0x00000047 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444 14:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5 15:15 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422 30:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72 0x00000048 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7 31:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73 0x00000049 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74 0x0000004A +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75 0x0000004B +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76 0x0000004C +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0 31:14 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77 0x0000004D +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444 14:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1 15:15 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422 30:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78 0x0000004E +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444 14:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3 15:15 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422 30:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79 0x0000004F +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444 14:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5 15:15 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422 30:16 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6 31:31 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80 0x00000050 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX 7:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7 31:8 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81 0x00000051 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82 0x00000052 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9 31:0 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83 0x00000053 +#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10 31:0 + + +// dma opcode instructions +#define NV977D_DMA 0x00000000 +#define NV977D_DMA_OPCODE 31:29 +#define NV977D_DMA_OPCODE_METHOD 0x00000000 +#define NV977D_DMA_OPCODE_JUMP 0x00000001 +#define NV977D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV977D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV977D_DMA_METHOD_COUNT 27:18 +#define NV977D_DMA_METHOD_OFFSET 11:2 +#define NV977D_DMA_DATA 31:0 +#define NV977D_DMA_DATA_NOP 0x00000000 +#define NV977D_DMA_JUMP_OFFSET 11:2 +#define NV977D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV977D_PUT (0x00000000) +#define NV977D_PUT_PTR 11:2 +#define NV977D_GET (0x00000004) +#define NV977D_GET_PTR 11:2 +#define NV977D_UPDATE (0x00000080) +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR(i) (0 +(i)*4):(0 +(i)*4) +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1 4 +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0 +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR1 4:4 +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR2 8:8 +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR3 12:12 +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_BASE(i) (1 +(i)*4):(1 +(i)*4) +#define NV977D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1 4 +#define NV977D_UPDATE_INTERLOCK_WITH_BASE_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_BASE_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_BASE0 1:1 +#define NV977D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_BASE1 5:5 +#define NV977D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_BASE2 9:9 +#define NV977D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_BASE3 13:13 +#define NV977D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY(i) (2 +(i)*4):(2 +(i)*4) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1 4 +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2 +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY1 6:6 +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY2 10:10 +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY3 14:14 +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i) (3 +(i)*4):(3 +(i)*4) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1 4 +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3 +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 7:7 +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2 11:11 +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE (0x00000001) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3 15:15 +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE (0x00000000) +#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE (0x00000001) +#define NV977D_UPDATE_SPECIAL_HANDLING 25:24 +#define NV977D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV977D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV977D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV977D_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV977D_UPDATE_NOT_DRIVER_FRIENDLY 31:31 +#define NV977D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000) +#define NV977D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001) +#define NV977D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30 +#define NV977D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000) +#define NV977D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001) +#define NV977D_UPDATE_INHIBIT_INTERRUPTS 29:29 +#define NV977D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NV977D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NV977D_SET_NOTIFIER_CONTROL (0x00000084) +#define NV977D_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV977D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV977D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV977D_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV977D_SET_NOTIFIER_CONTROL_NOTIFY 31:31 +#define NV977D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NV977D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NV977D_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV977D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV977D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV977D_SET_CONTEXT_DMA_NOTIFIER (0x00000088) +#define NV977D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV977D_GET_CAPABILITIES (0x0000008C) +#define NV977D_GET_CAPABILITIES_DUMMY 31:0 +#define NV977D_SET_SPARE (0x0000016C) +#define NV977D_SET_SPARE_UNUSED 31:0 +#define NV977D_SET_SPARE_NOOP(b) (0x00000170 + (b)*0x00000004) +#define NV977D_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV977D_DAC_SET_CONTROL(a) (0x00000180 + (a)*0x00000020) +#define NV977D_DAC_SET_CONTROL_OWNER_MASK 3:0 +#define NV977D_DAC_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV977D_DAC_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV977D_DAC_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV977D_DAC_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV977D_DAC_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV977D_DAC_SET_CONTROL_PROTOCOL 12:8 +#define NV977D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV977D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT (0x00000013) +#define NV977D_DAC_SET_SW_SPARE_A(a) (0x00000184 + (a)*0x00000020) +#define NV977D_DAC_SET_SW_SPARE_A_CODE 31:0 +#define NV977D_DAC_SET_SW_SPARE_B(a) (0x00000188 + (a)*0x00000020) +#define NV977D_DAC_SET_SW_SPARE_B_CODE 31:0 +#define NV977D_DAC_SET_CUSTOM_REASON(a) (0x00000190 + (a)*0x00000020) +#define NV977D_DAC_SET_CUSTOM_REASON_CODE 31:0 + +#define NV977D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020) +#define NV977D_SOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV977D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV977D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV977D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV977D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV977D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV977D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV977D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV977D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV977D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV977D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV977D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NV977D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NV977D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV977D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV977D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV977D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV977D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NV977D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NV977D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NV977D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NV977D_SOR_SET_SW_SPARE_A(a) (0x00000204 + (a)*0x00000020) +#define NV977D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NV977D_SOR_SET_SW_SPARE_B(a) (0x00000208 + (a)*0x00000020) +#define NV977D_SOR_SET_SW_SPARE_B_CODE 31:0 +#define NV977D_SOR_SET_CUSTOM_REASON(a) (0x00000210 + (a)*0x00000020) +#define NV977D_SOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV977D_PIOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NV977D_PIOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV977D_PIOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV977D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV977D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV977D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV977D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV977D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV977D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV977D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV977D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV977D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV977D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV977D_PIOR_SET_SW_SPARE_A(a) (0x00000304 + (a)*0x00000020) +#define NV977D_PIOR_SET_SW_SPARE_A_CODE 31:0 +#define NV977D_PIOR_SET_SW_SPARE_B(a) (0x00000308 + (a)*0x00000020) +#define NV977D_PIOR_SET_SW_SPARE_B_CODE 31:0 +#define NV977D_PIOR_SET_CUSTOM_REASON(a) (0x00000310 + (a)*0x00000020) +#define NV977D_PIOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV977D_HEAD_SET_PRESENT_CONTROL(a) (0x00000400 + (a)*0x00000300) +#define NV977D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NV977D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 8:8 +#define NV977D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NV977D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NV977D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00000404 + (a)*0x00000300) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 3:3 +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 4:4 +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 9:6 +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000009) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 12:12 +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 24:13 +#define NV977D_HEAD_SET_CONTROL(a) (0x00000408 + (a)*0x00000300) +#define NV977D_HEAD_SET_CONTROL_STRUCTURE 0:0 +#define NV977D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV977D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 3:2 +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 19:15 +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV977D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 7:4 +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 9:8 +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 14:10 +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV977D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK 1:1 +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_DISABLE (0x00000000) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_ENABLE (0x00000001) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN 24:20 +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV977D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN 29:25 +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000000) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000001) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000002) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000003) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000004) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000005) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000006) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000007) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000008) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x00000009) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000A) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000B) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000C) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000D) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000E) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x0000000F) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_UNSPECIFIED (0x00000010) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV977D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV977D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NV977D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV977D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV977D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NV977D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV977D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV977D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000410 + (a)*0x00000300) +#define NV977D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV977D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV977D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV977D_HEAD_SET_RASTER_SIZE(a) (0x00000414 + (a)*0x00000300) +#define NV977D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV977D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV977D_HEAD_SET_RASTER_SYNC_END(a) (0x00000418 + (a)*0x00000300) +#define NV977D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV977D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV977D_HEAD_SET_RASTER_BLANK_END(a) (0x0000041C + (a)*0x00000300) +#define NV977D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV977D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV977D_HEAD_SET_RASTER_BLANK_START(a) (0x00000420 + (a)*0x00000300) +#define NV977D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV977D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV977D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000424 + (a)*0x00000300) +#define NV977D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV977D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV977D_HEAD_SET_LOCK_CHAIN(a) (0x00000428 + (a)*0x00000300) +#define NV977D_HEAD_SET_LOCK_CHAIN_POSITION 27:24 +#define NV977D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000042C + (a)*0x00000300) +#define NV977D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV977D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV977D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV977D_HEAD_SET_CRC_CONTROL(a) (0x00000430 + (a)*0x00000300) +#define NV977D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 1:0 +#define NV977D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000000) +#define NV977D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_BASE (0x00000001) +#define NV977D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_OVERLAY (0x00000002) +#define NV977D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 2:2 +#define NV977D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NV977D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NV977D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE 3:3 +#define NV977D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_FALSE (0x00000000) +#define NV977D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_TRUE (0x00000001) +#define NV977D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE 4:4 +#define NV977D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_FALSE (0x00000000) +#define NV977D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_TRUE (0x00000001) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT 19:8 +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC__SIZE_1 4 +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC0 (0x00000FF0) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC1 (0x00000FF1) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC2 (0x00000FF2) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC3 (0x00000FF3) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG__SIZE_1 4 +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG0 (0x00000FF8) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG1 (0x00000FF9) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG2 (0x00000FFA) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG3 (0x00000FFB) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR__SIZE_1 8 +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR0 (0x00000F0F) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR1 (0x00000F1F) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR2 (0x00000F2F) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR3 (0x00000F3F) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR4 (0x00000F4F) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR5 (0x00000F5F) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR6 (0x00000F6F) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR7 (0x00000F7F) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF__SIZE_1 4 +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF0 (0x00000F8F) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF1 (0x00000F9F) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF2 (0x00000FAF) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF3 (0x00000FBF) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR__SIZE_1 8 +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR0 (0x000000FF) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR1 (0x000001FF) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR2 (0x000002FF) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR3 (0x000003FF) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR4 (0x000004FF) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR5 (0x000005FF) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR6 (0x000006FF) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR7 (0x000007FF) +#define NV977D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_NONE (0x00000FFF) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT 31:20 +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC__SIZE_1 4 +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC0 (0x00000FF0) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC1 (0x00000FF1) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC2 (0x00000FF2) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC3 (0x00000FF3) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG__SIZE_1 4 +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG0 (0x00000FF8) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG1 (0x00000FF9) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG2 (0x00000FFA) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG3 (0x00000FFB) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR__SIZE_1 8 +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR0 (0x00000F0F) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR1 (0x00000F1F) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR2 (0x00000F2F) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR3 (0x00000F3F) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR4 (0x00000F4F) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR5 (0x00000F5F) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR6 (0x00000F6F) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR7 (0x00000F7F) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF__SIZE_1 4 +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF0 (0x00000F8F) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF1 (0x00000F9F) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF2 (0x00000FAF) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF3 (0x00000FBF) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR__SIZE_1 8 +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR0 (0x000000FF) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR1 (0x000001FF) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR2 (0x000002FF) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR3 (0x000003FF) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR4 (0x000004FF) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR5 (0x000005FF) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR6 (0x000006FF) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR7 (0x000007FF) +#define NV977D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_NONE (0x00000FFF) +#define NV977D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 5:5 +#define NV977D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NV977D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NV977D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC 6:6 +#define NV977D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_DISABLE (0x00000000) +#define NV977D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_ENABLE (0x00000001) +#define NV977D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00000438 + (a)*0x00000300) +#define NV977D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NV977D_HEAD_SET_BASE_LUT_LO(a) (0x00000440 + (a)*0x00000300) +#define NV977D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV977D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV977D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV977D_HEAD_SET_BASE_LUT_LO_MODE 27:24 +#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV977D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV977D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV977D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV977D_HEAD_SET_BASE_LUT_HI(a) (0x00000444 + (a)*0x00000300) +#define NV977D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV977D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000448 + (a)*0x00000300) +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV977D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV977D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000044C + (a)*0x00000300) +#define NV977D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x00000450 + (a)*0x00000300) +#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x00000454 + (a)*0x00000300) +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE 21:20 +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25 (0x00000000) +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28 (0x00000001) +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM (0x00000002) +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 24:24 +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING 25:25 +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE (0x00000000) +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE (0x00000001) +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 26:26 +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00000458 + (a)*0x00000300) +#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NV977D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000045C + (a)*0x00000300) +#define NV977D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV977D_HEAD_SET_OFFSET(a) (0x00000460 + (a)*0x00000300) +#define NV977D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV977D_HEAD_SET_SIZE(a) (0x00000468 + (a)*0x00000300) +#define NV977D_HEAD_SET_SIZE_WIDTH 15:0 +#define NV977D_HEAD_SET_SIZE_HEIGHT 31:16 +#define NV977D_HEAD_SET_STORAGE(a) (0x0000046C + (a)*0x00000300) +#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV977D_HEAD_SET_STORAGE_PITCH 20:8 +#define NV977D_HEAD_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV977D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV977D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV977D_HEAD_SET_PARAMS(a) (0x00000470 + (a)*0x00000300) +#define NV977D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV977D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV977D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV977D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV977D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV977D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV977D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV977D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV977D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024) +#define NV977D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV977D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV977D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV977D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV977D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV977D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV977D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV977D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV977D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV977D_HEAD_SET_PARAMS_GAMMA 2:2 +#define NV977D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV977D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV977D_HEAD_SET_CONTEXT_DMAS_ISO(a) (0x00000474 + (a)*0x00000300) +#define NV977D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV977D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x0000047C + (a)*0x00000300) +#define NV977D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 1:0 +#define NV977D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NV977D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NV977D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_SPEC_FLIP (0x00000002) +#define NV977D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300) +#define NV977D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV977D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV977D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV977D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV977D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV977D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV977D_HEAD_SET_CONTROL_CURSOR_SIZE 27:26 +#define NV977D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV977D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV977D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NV977D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NV977D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 15:8 +#define NV977D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 23:16 +#define NV977D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV977D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV977D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV977D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV977D_HEAD_SET_OFFSETS_CURSOR(a,b) (0x00000484 + (a)*0x00000300 + (b)*0x00000004) +#define NV977D_HEAD_SET_OFFSETS_CURSOR_ORIGIN 31:0 +#define NV977D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b) (0x0000048C + (a)*0x00000300 + (b)*0x00000004) +#define NV977D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE 31:0 +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00000494 + (a)*0x00000300) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422 8:8 +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE (0x00000000) +#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE (0x00000001) +#define NV977D_HEAD_SET_PROCAMP(a) (0x00000498 + (a)*0x00000300) +#define NV977D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV977D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV977D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV977D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV977D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003) +#define NV977D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV977D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV977D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV977D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV977D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV977D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 5:5 +#define NV977D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NV977D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NV977D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 6:6 +#define NV977D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) +#define NV977D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) +#define NV977D_HEAD_SET_DITHER_CONTROL(a) (0x000004A0 + (a)*0x00000300) +#define NV977D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV977D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV977D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV977D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV977D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV977D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV977D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002) +#define NV977D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV977D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV977D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV977D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV977D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV977D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NV977D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV977D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x000004B0 + (a)*0x00000300) +#define NV977D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV977D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV977D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000004B8 + (a)*0x00000300) +#define NV977D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV977D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV977D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x000004BC + (a)*0x00000300) +#define NV977D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NV977D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000004C0 + (a)*0x00000300) +#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000004C4 + (a)*0x00000300) +#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a) (0x000004C8 + (a)*0x00000300) +#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH 14:0 +#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT 30:16 +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT 17:16 +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE (0x00000000) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257 (0x00000001) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025 (0x00000002) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT 21:20 +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) +#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x000004D4 + (a)*0x00000300) +#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT 13:12 +#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE (0x00000000) +#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257 (0x00000001) +#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025 (0x00000002) +#define NV977D_HEAD_SET_PROCESSING(a) (0x000004E0 + (a)*0x00000300) +#define NV977D_HEAD_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV977D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV977D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV977D_HEAD_SET_CONVERSION_RED(a) (0x000004E4 + (a)*0x00000300) +#define NV977D_HEAD_SET_CONVERSION_RED_GAIN 15:0 +#define NV977D_HEAD_SET_CONVERSION_RED_OFS 31:16 +#define NV977D_HEAD_SET_CONVERSION_GRN(a) (0x000004E8 + (a)*0x00000300) +#define NV977D_HEAD_SET_CONVERSION_GRN_GAIN 15:0 +#define NV977D_HEAD_SET_CONVERSION_GRN_OFS 31:16 +#define NV977D_HEAD_SET_CONVERSION_BLU(a) (0x000004EC + (a)*0x00000300) +#define NV977D_HEAD_SET_CONVERSION_BLU_GAIN 15:0 +#define NV977D_HEAD_SET_CONVERSION_BLU_OFS 31:16 +#define NV977D_HEAD_SET_CSC_RED2RED(a) (0x000004F0 + (a)*0x00000300) +#define NV977D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE 31:31 +#define NV977D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV977D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV977D_HEAD_SET_CSC_RED2RED_COEFF 18:0 +#define NV977D_HEAD_SET_CSC_GRN2RED(a) (0x000004F4 + (a)*0x00000300) +#define NV977D_HEAD_SET_CSC_GRN2RED_COEFF 18:0 +#define NV977D_HEAD_SET_CSC_BLU2RED(a) (0x000004F8 + (a)*0x00000300) +#define NV977D_HEAD_SET_CSC_BLU2RED_COEFF 18:0 +#define NV977D_HEAD_SET_CSC_CONSTANT2RED(a) (0x000004FC + (a)*0x00000300) +#define NV977D_HEAD_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV977D_HEAD_SET_CSC_RED2GRN(a) (0x00000500 + (a)*0x00000300) +#define NV977D_HEAD_SET_CSC_RED2GRN_COEFF 18:0 +#define NV977D_HEAD_SET_CSC_GRN2GRN(a) (0x00000504 + (a)*0x00000300) +#define NV977D_HEAD_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV977D_HEAD_SET_CSC_BLU2GRN(a) (0x00000508 + (a)*0x00000300) +#define NV977D_HEAD_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV977D_HEAD_SET_CSC_CONSTANT2GRN(a) (0x0000050C + (a)*0x00000300) +#define NV977D_HEAD_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV977D_HEAD_SET_CSC_RED2BLU(a) (0x00000510 + (a)*0x00000300) +#define NV977D_HEAD_SET_CSC_RED2BLU_COEFF 18:0 +#define NV977D_HEAD_SET_CSC_GRN2BLU(a) (0x00000514 + (a)*0x00000300) +#define NV977D_HEAD_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV977D_HEAD_SET_CSC_BLU2BLU(a) (0x00000518 + (a)*0x00000300) +#define NV977D_HEAD_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV977D_HEAD_SET_CSC_CONSTANT2BLU(a) (0x0000051C + (a)*0x00000300) +#define NV977D_HEAD_SET_CSC_CONSTANT2BLU_COEFF 18:0 +#define NV977D_HEAD_SET_HDMI_CTRL(a) (0x00000520 + (a)*0x00000300) +#define NV977D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NV977D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NV977D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NV977D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NV977D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NV977D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE 15:12 +#define NV977D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000000) +#define NV977D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FIELD_ALTERNATIVE (0x00000001) +#define NV977D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_LINE_ALTERNATIVE (0x00000002) +#define NV977D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_FULL (0x00000003) +#define NV977D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH (0x00000004) +#define NV977D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH_GRAPHICS (0x00000005) +#define NV977D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_TOP_AND_BOTTOM (0x00000006) +#define NV977D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_HALF (0x00000008) +#define NV977D_HEAD_SET_VACTIVE_SPACE_COLOR(a) (0x00000524 + (a)*0x00000300) +#define NV977D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR 9:0 +#define NV977D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y 19:10 +#define NV977D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB 29:20 +#define NV977D_HEAD_SET_PIXEL_REORDER_CONTROL(a) (0x00000528 + (a)*0x00000300) +#define NV977D_HEAD_SET_PIXEL_REORDER_CONTROL_BANK_WIDTH 13:0 +#define NV977D_HEAD_SET_DISPLAY_ID(a,b) (0x0000052C + (a)*0x00000300 + (b)*0x00000004) +#define NV977D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NV977D_HEAD_SET_SW_SPARE_A(a) (0x0000054C + (a)*0x00000300) +#define NV977D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NV977D_HEAD_SET_SW_SPARE_B(a) (0x00000550 + (a)*0x00000300) +#define NV977D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NV977D_HEAD_SET_SW_SPARE_C(a) (0x00000554 + (a)*0x00000300) +#define NV977D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NV977D_HEAD_SET_SW_SPARE_D(a) (0x00000558 + (a)*0x00000300) +#define NV977D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NV977D_HEAD_SET_GET_BLANKING_CTRL(a) (0x0000055C + (a)*0x00000300) +#define NV977D_HEAD_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NV977D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NV977D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NV977D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NV977D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NV977D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) +#define NV977D_HEAD_SET_CONTROL_COMPRESSION(a) (0x00000560 + (a)*0x00000300) +#define NV977D_HEAD_SET_CONTROL_COMPRESSION_ENABLE 0:0 +#define NV977D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_DISABLE (0x00000000) +#define NV977D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_ENABLE (0x00000001) +#define NV977D_HEAD_SET_CONTROL_COMPRESSION_CHUNK_BANDWIDTH 12:1 +#define NV977D_HEAD_SET_CONTROL_COMPRESSION_LAST_BANDWIDTH 24:13 +#define NV977D_HEAD_SET_CONTROL_COMPRESSION_LA(a) (0x00000564 + (a)*0x00000300) +#define NV977D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY1 7:4 +#define NV977D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY2 11:8 +#define NV977D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY3 15:12 +#define NV977D_HEAD_SET_CONTROL_COMPRESSION_LA_CHUNK_SIZE 23:16 +#define NV977D_HEAD_SET_STALL_LOCK(a) (0x00000568 + (a)*0x00000300) +#define NV977D_HEAD_SET_STALL_LOCK_ENABLE 0:0 +#define NV977D_HEAD_SET_STALL_LOCK_ENABLE_FALSE (0x00000000) +#define NV977D_HEAD_SET_STALL_LOCK_ENABLE_TRUE (0x00000001) +#define NV977D_HEAD_SET_STALL_LOCK_MODE 1:1 +#define NV977D_HEAD_SET_STALL_LOCK_MODE_CONTINUOUS (0x00000000) +#define NV977D_HEAD_SET_STALL_LOCK_MODE_ONE_SHOT (0x00000001) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN 6:2 +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV977D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV977D_HEAD_SET_STALL_LOCK_UNSTALL_MODE 7:7 +#define NV977D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_CRASH_LOCK (0x00000000) +#define NV977D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_LINE_LOCK (0x00000001) +#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a) (0x000006D0 + (a)*0x00000300) +#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED 31:0 +#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a) (0x000006D4 + (a)*0x00000300) +#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED 31:0 +#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a) (0x000006D8 + (a)*0x00000300) +#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED 31:0 +#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a) (0x000006DC + (a)*0x00000300) +#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED 31:0 +#define NV977D_HEAD_SET_SPARE(a) (0x000006EC + (a)*0x00000300) +#define NV977D_HEAD_SET_SPARE_UNUSED 31:0 +#define NV977D_HEAD_SET_SPARE_NOOP(a,b) (0x000006F0 + (a)*0x00000300 + (b)*0x00000004) +#define NV977D_HEAD_SET_SPARE_NOOP_UNUSED 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl977d_h diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl9870.h b/userspace/sdks/nv570/nvidia/inc/class/cl9870.h new file mode 100644 index 0000000..44b7659 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl9870.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9870.finn +// + +#define NV9870_DISPLAY (0x9870U) /* finn: Evaluated from "NV9870_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV9870_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9870U) + +typedef struct NV9870_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numDacs; // Number of DACs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NV9870_ALLOCATION_PARAMETERS; diff --git a/userspace/sdks/nv570/nvidia/inc/class/cl987d.h b/userspace/sdks/nv570/nvidia/inc/class/cl987d.h new file mode 100644 index 0000000..ab01f62 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cl987d.h @@ -0,0 +1,1590 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl987d_h_ +#define _cl987d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV987D_CORE_CHANNEL_DMA (0x0000987D) + +#define NV987D_CORE_NOTIFIER_3 0x00000000 +#define NV987D_CORE_NOTIFIER_3_SIZEOF 0x00000150 +#define NV987D_CORE_NOTIFIER_3_COMPLETION_0 0x00000000 +#define NV987D_CORE_NOTIFIER_3_COMPLETION_0_DONE 0:0 +#define NV987D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_COMPLETION_0_R0 15:1 +#define NV987D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP 29:16 +#define NV987D_CORE_NOTIFIER_3__1 0x00000001 +#define NV987D_CORE_NOTIFIER_3__1_R1 31:0 +#define NV987D_CORE_NOTIFIER_3__2 0x00000002 +#define NV987D_CORE_NOTIFIER_3__2_R2 31:0 +#define NV987D_CORE_NOTIFIER_3__3 0x00000003 +#define NV987D_CORE_NOTIFIER_3__3_R3 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO 2:2 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_R0 19:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA 20:20 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_R1 29:21 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE 30:30 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN0USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_INTERNAL_FLIP_LOCK_PIN1USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5 0x00000005 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE 3:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN0USAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE 7:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN1USAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE 11:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN2USAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE 15:12 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN3USAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE 19:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN4USAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE 23:20 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN5USAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE 27:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN6USAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE 31:28 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5_LOCK_PIN7USAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6 0x00000006 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE 3:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN8USAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE 7:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN9USAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE 11:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_AUSAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE 15:12 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_BUSAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE 19:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_CUSAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE 23:20 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_DUSAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE 27:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_EUSAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE 31:28 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_UNAVAILABLE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_SCAN_LOCK 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_FLIP_LOCK 0x00000002 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6_LOCK_PIN_FUSAGE_STEREO 0x00000004 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_7 0x00000007 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_7_R4 31:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_8 0x00000008 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_8_R5 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_9 0x00000009 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_9_R6 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_10 0x0000000A +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_10_R7 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_11 0x0000000B +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_11_R8 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12 0x0000000C +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE 3:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0 31:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13 0x0000000D +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1 31:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14 0x0000000E +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE 3:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0 31:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15 0x0000000F +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1 31:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16 0x00000010 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE 3:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0 31:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17 0x00000011 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1 31:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18 0x00000012 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE 3:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0 31:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19 0x00000013 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1 31:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18 2:2 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24 3:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0 7:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A 8:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B 9:9 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1 10:10 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS 11:11 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2 13:12 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3 16:14 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4 19:17 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5 23:20 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A 24:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B 25:25 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE 26:26 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6 31:28 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21 0x00000015 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7 15:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_CLK_MAX 23:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_LVDS_CLK_MAX 31:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22 0x00000016 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18 2:2 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24 3:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0 7:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A 8:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B 9:9 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1 10:10 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS 11:11 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2 13:12 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3 16:14 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4 19:17 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5 23:20 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A 24:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B 25:25 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE 26:26 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6 31:28 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23 0x00000017 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7 15:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_CLK_MAX 23:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_LVDS_CLK_MAX 31:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24 0x00000018 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18 2:2 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24 3:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0 7:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A 8:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B 9:9 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1 10:10 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS 11:11 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2 13:12 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3 16:14 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4 19:17 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5 23:20 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A 24:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B 25:25 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE 26:26 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6 31:28 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25 0x00000019 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7 15:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_CLK_MAX 23:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_LVDS_CLK_MAX 31:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26 0x0000001A +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18 2:2 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24 3:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0 7:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A 8:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B 9:9 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1 10:10 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS 11:11 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2 13:12 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3 16:14 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4 19:17 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5 23:20 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A 24:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B 25:25 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE 26:26 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6 31:28 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27 0x0000001B +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7 15:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_CLK_MAX 23:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_LVDS_CLK_MAX 31:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28 0x0000001C +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18 2:2 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24 3:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0 7:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A 8:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B 9:9 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1 10:10 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS 11:11 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2 13:12 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3 16:14 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4 19:17 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5 23:20 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A 24:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B 25:25 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE 26:26 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6 31:28 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29 0x0000001D +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7 15:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_CLK_MAX 23:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_LVDS_CLK_MAX 31:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30 0x0000001E +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18 2:2 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24 3:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0 7:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A 8:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B 9:9 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1 10:10 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS 11:11 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2 13:12 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3 16:14 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4 19:17 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5 23:20 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A 24:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B 25:25 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE 26:26 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6 31:28 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31 0x0000001F +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7 15:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_CLK_MAX 23:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_LVDS_CLK_MAX 31:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32 0x00000020 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18 2:2 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24 3:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0 7:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A 8:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B 9:9 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1 10:10 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS 11:11 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2 13:12 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3 16:14 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4 19:17 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5 23:20 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A 24:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B 25:25 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE 26:26 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6 31:28 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33 0x00000021 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7 15:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_CLK_MAX 23:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_LVDS_CLK_MAX 31:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34 0x00000022 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18 2:2 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24 3:3 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0 7:4 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A 8:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B 9:9 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1 10:10 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS 11:11 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2 13:12 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3 16:14 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4 19:17 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5 23:20 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A 24:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B 25:25 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE 26:26 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6 31:28 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35 0x00000023 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7 15:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_CLK_MAX 23:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_LVDS_CLK_MAX 31:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36 0x00000024 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0 31:10 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37 0x00000025 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1 15:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2 31:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38 0x00000026 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0 31:10 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39 0x00000027 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1 15:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2 31:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40 0x00000028 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0 31:10 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41 0x00000029 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1 15:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2 31:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42 0x0000002A +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC 0:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC 1:1 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0 31:10 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43 0x0000002B +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1 15:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2 31:24 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52 0x00000034 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0 31:14 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53 0x00000035 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444 14:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1 15:15 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422 30:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54 0x00000036 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444 14:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3 15:15 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422 30:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55 0x00000037 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444 14:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5 15:15 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422 30:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56 0x00000038 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7 31:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57 0x00000039 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58 0x0000003A +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59 0x0000003B +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60 0x0000003C +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0 31:14 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61 0x0000003D +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444 14:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1 15:15 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422 30:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62 0x0000003E +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444 14:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3 15:15 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422 30:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63 0x0000003F +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444 14:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5 15:15 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422 30:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64 0x00000040 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7 31:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65 0x00000041 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66 0x00000042 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67 0x00000043 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68 0x00000044 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0 31:14 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69 0x00000045 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444 14:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1 15:15 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422 30:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70 0x00000046 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444 14:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3 15:15 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422 30:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71 0x00000047 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444 14:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5 15:15 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422 30:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72 0x00000048 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7 31:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73 0x00000049 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74 0x0000004A +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75 0x0000004B +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76 0x0000004C +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0 31:14 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77 0x0000004D +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444 14:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1 15:15 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422 30:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78 0x0000004E +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444 14:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3 15:15 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422 30:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79 0x0000004F +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444 14:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5 15:15 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422 30:16 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6 31:31 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80 0x00000050 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX 7:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7 31:8 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81 0x00000051 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82 0x00000052 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9 31:0 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83 0x00000053 +#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10 31:0 + + +// dma opcode instructions +#define NV987D_DMA 0x00000000 +#define NV987D_DMA_OPCODE 31:29 +#define NV987D_DMA_OPCODE_METHOD 0x00000000 +#define NV987D_DMA_OPCODE_JUMP 0x00000001 +#define NV987D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV987D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV987D_DMA_METHOD_COUNT 27:18 +#define NV987D_DMA_METHOD_OFFSET 11:2 +#define NV987D_DMA_DATA 31:0 +#define NV987D_DMA_DATA_NOP 0x00000000 +#define NV987D_DMA_JUMP_OFFSET 11:2 +#define NV987D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV987D_PUT (0x00000000) +#define NV987D_PUT_PTR 11:2 +#define NV987D_GET (0x00000004) +#define NV987D_GET_PTR 11:2 +#define NV987D_UPDATE (0x00000080) +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR(i) (0 +(i)*4):(0 +(i)*4) +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1 4 +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0 +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR1 4:4 +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR2 8:8 +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR3 12:12 +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_BASE(i) (1 +(i)*4):(1 +(i)*4) +#define NV987D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1 4 +#define NV987D_UPDATE_INTERLOCK_WITH_BASE_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_BASE_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_BASE0 1:1 +#define NV987D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_BASE1 5:5 +#define NV987D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_BASE2 9:9 +#define NV987D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_BASE3 13:13 +#define NV987D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY(i) (2 +(i)*4):(2 +(i)*4) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1 4 +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2 +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY1 6:6 +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY2 10:10 +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY3 14:14 +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i) (3 +(i)*4):(3 +(i)*4) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1 4 +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3 +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 7:7 +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2 11:11 +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE (0x00000001) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3 15:15 +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE (0x00000000) +#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE (0x00000001) +#define NV987D_UPDATE_SPECIAL_HANDLING 25:24 +#define NV987D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV987D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV987D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV987D_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV987D_UPDATE_NOT_DRIVER_FRIENDLY 31:31 +#define NV987D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000) +#define NV987D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001) +#define NV987D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30 +#define NV987D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000) +#define NV987D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001) +#define NV987D_UPDATE_INHIBIT_INTERRUPTS 29:29 +#define NV987D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NV987D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NV987D_SET_NOTIFIER_CONTROL (0x00000084) +#define NV987D_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV987D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV987D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV987D_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV987D_SET_NOTIFIER_CONTROL_NOTIFY 31:31 +#define NV987D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NV987D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NV987D_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV987D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV987D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV987D_SET_NOTIFIER_CONTROL_NO_WAIT_ACTIVE 0:0 +#define NV987D_SET_NOTIFIER_CONTROL_NO_WAIT_ACTIVE_FALSE (0x00000000) +#define NV987D_SET_NOTIFIER_CONTROL_NO_WAIT_ACTIVE_TRUE (0x00000001) +#define NV987D_SET_CONTEXT_DMA_NOTIFIER (0x00000088) +#define NV987D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV987D_GET_CAPABILITIES (0x0000008C) +#define NV987D_GET_CAPABILITIES_DUMMY 31:0 +#define NV987D_SET_SPARE (0x0000016C) +#define NV987D_SET_SPARE_UNUSED 31:0 +#define NV987D_SET_SPARE_NOOP(b) (0x00000170 + (b)*0x00000004) +#define NV987D_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV987D_DAC_SET_CONTROL(a) (0x00000180 + (a)*0x00000020) +#define NV987D_DAC_SET_CONTROL_OWNER_MASK 3:0 +#define NV987D_DAC_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV987D_DAC_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV987D_DAC_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV987D_DAC_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV987D_DAC_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV987D_DAC_SET_CONTROL_PROTOCOL 12:8 +#define NV987D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV987D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT (0x00000013) +#define NV987D_DAC_SET_SW_SPARE_A(a) (0x00000184 + (a)*0x00000020) +#define NV987D_DAC_SET_SW_SPARE_A_CODE 31:0 +#define NV987D_DAC_SET_SW_SPARE_B(a) (0x00000188 + (a)*0x00000020) +#define NV987D_DAC_SET_SW_SPARE_B_CODE 31:0 +#define NV987D_DAC_SET_CUSTOM_REASON(a) (0x00000190 + (a)*0x00000020) +#define NV987D_DAC_SET_CUSTOM_REASON_CODE 31:0 + +#define NV987D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020) +#define NV987D_SOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV987D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV987D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV987D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV987D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV987D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV987D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV987D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV987D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV987D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV987D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV987D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NV987D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NV987D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV987D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV987D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV987D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV987D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NV987D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NV987D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NV987D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NV987D_SOR_SET_SW_SPARE_A(a) (0x00000204 + (a)*0x00000020) +#define NV987D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NV987D_SOR_SET_SW_SPARE_B(a) (0x00000208 + (a)*0x00000020) +#define NV987D_SOR_SET_SW_SPARE_B_CODE 31:0 +#define NV987D_SOR_SET_CUSTOM_REASON(a) (0x00000210 + (a)*0x00000020) +#define NV987D_SOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV987D_PIOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NV987D_PIOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV987D_PIOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV987D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV987D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV987D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV987D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV987D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV987D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV987D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV987D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV987D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV987D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV987D_PIOR_SET_SW_SPARE_A(a) (0x00000304 + (a)*0x00000020) +#define NV987D_PIOR_SET_SW_SPARE_A_CODE 31:0 +#define NV987D_PIOR_SET_SW_SPARE_B(a) (0x00000308 + (a)*0x00000020) +#define NV987D_PIOR_SET_SW_SPARE_B_CODE 31:0 +#define NV987D_PIOR_SET_CUSTOM_REASON(a) (0x00000310 + (a)*0x00000020) +#define NV987D_PIOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV987D_HEAD_SET_PRESENT_CONTROL(a) (0x00000400 + (a)*0x00000300) +#define NV987D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NV987D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 8:8 +#define NV987D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NV987D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NV987D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00000404 + (a)*0x00000300) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 3:3 +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 4:4 +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 9:6 +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000009) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 12:12 +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 24:13 +#define NV987D_HEAD_SET_CONTROL(a) (0x00000408 + (a)*0x00000300) +#define NV987D_HEAD_SET_CONTROL_STRUCTURE 0:0 +#define NV987D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV987D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 3:2 +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 19:15 +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV987D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 7:4 +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 9:8 +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 14:10 +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV987D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK 1:1 +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_DISABLE (0x00000000) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_ENABLE (0x00000001) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN 24:20 +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV987D_HEAD_SET_CONTROL_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN 29:25 +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000000) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000001) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000002) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000003) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000004) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000005) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000006) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000007) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000008) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x00000009) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000A) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000B) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000C) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000D) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000E) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x0000000F) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_UNSPECIFIED (0x00000010) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV987D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV987D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NV987D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV987D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV987D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NV987D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NV987D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NV987D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000410 + (a)*0x00000300) +#define NV987D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV987D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV987D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV987D_HEAD_SET_RASTER_SIZE(a) (0x00000414 + (a)*0x00000300) +#define NV987D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV987D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV987D_HEAD_SET_RASTER_SYNC_END(a) (0x00000418 + (a)*0x00000300) +#define NV987D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV987D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV987D_HEAD_SET_RASTER_BLANK_END(a) (0x0000041C + (a)*0x00000300) +#define NV987D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV987D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV987D_HEAD_SET_RASTER_BLANK_START(a) (0x00000420 + (a)*0x00000300) +#define NV987D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV987D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV987D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000424 + (a)*0x00000300) +#define NV987D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV987D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV987D_HEAD_SET_LOCK_CHAIN(a) (0x00000428 + (a)*0x00000300) +#define NV987D_HEAD_SET_LOCK_CHAIN_POSITION 27:24 +#define NV987D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000042C + (a)*0x00000300) +#define NV987D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV987D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV987D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV987D_HEAD_SET_CRC_CONTROL(a) (0x00000430 + (a)*0x00000300) +#define NV987D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 1:0 +#define NV987D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000000) +#define NV987D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_BASE (0x00000001) +#define NV987D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_OVERLAY (0x00000002) +#define NV987D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 2:2 +#define NV987D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NV987D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NV987D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE 3:3 +#define NV987D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_FALSE (0x00000000) +#define NV987D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_TRUE (0x00000001) +#define NV987D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE 4:4 +#define NV987D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_FALSE (0x00000000) +#define NV987D_HEAD_SET_CRC_CONTROL_FLIPLOCK_MODE_TRUE (0x00000001) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT 19:8 +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC__SIZE_1 4 +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC0 (0x00000FF0) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC1 (0x00000FF1) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC2 (0x00000FF2) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC3 (0x00000FF3) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG__SIZE_1 4 +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG0 (0x00000FF8) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG1 (0x00000FF9) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG2 (0x00000FFA) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG3 (0x00000FFB) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR__SIZE_1 8 +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR0 (0x00000F0F) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR1 (0x00000F1F) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR2 (0x00000F2F) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR3 (0x00000F3F) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR4 (0x00000F4F) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR5 (0x00000F5F) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR6 (0x00000F6F) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR7 (0x00000F7F) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF__SIZE_1 4 +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF0 (0x00000F8F) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF1 (0x00000F9F) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF2 (0x00000FAF) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF3 (0x00000FBF) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR__SIZE_1 8 +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR0 (0x000000FF) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR1 (0x000001FF) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR2 (0x000002FF) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR3 (0x000003FF) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR4 (0x000004FF) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR5 (0x000005FF) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR6 (0x000006FF) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR7 (0x000007FF) +#define NV987D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_NONE (0x00000FFF) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT 31:20 +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC__SIZE_1 4 +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC0 (0x00000FF0) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC1 (0x00000FF1) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC2 (0x00000FF2) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC3 (0x00000FF3) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG__SIZE_1 4 +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG0 (0x00000FF8) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG1 (0x00000FF9) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG2 (0x00000FFA) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG3 (0x00000FFB) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR__SIZE_1 8 +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR0 (0x00000F0F) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR1 (0x00000F1F) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR2 (0x00000F2F) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR3 (0x00000F3F) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR4 (0x00000F4F) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR5 (0x00000F5F) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR6 (0x00000F6F) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR7 (0x00000F7F) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF__SIZE_1 4 +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF0 (0x00000F8F) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF1 (0x00000F9F) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF2 (0x00000FAF) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF3 (0x00000FBF) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR__SIZE_1 8 +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR0 (0x000000FF) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR1 (0x000001FF) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR2 (0x000002FF) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR3 (0x000003FF) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR4 (0x000004FF) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR5 (0x000005FF) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR6 (0x000006FF) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR7 (0x000007FF) +#define NV987D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_NONE (0x00000FFF) +#define NV987D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 5:5 +#define NV987D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NV987D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NV987D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC 6:6 +#define NV987D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_DISABLE (0x00000000) +#define NV987D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_ENABLE (0x00000001) +#define NV987D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00000438 + (a)*0x00000300) +#define NV987D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NV987D_HEAD_SET_BASE_LUT_LO(a) (0x00000440 + (a)*0x00000300) +#define NV987D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV987D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV987D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV987D_HEAD_SET_BASE_LUT_LO_MODE 27:24 +#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV987D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV987D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV987D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV987D_HEAD_SET_BASE_LUT_HI(a) (0x00000444 + (a)*0x00000300) +#define NV987D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV987D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000448 + (a)*0x00000300) +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV987D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV987D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000044C + (a)*0x00000300) +#define NV987D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x00000450 + (a)*0x00000300) +#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x00000454 + (a)*0x00000300) +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE 21:20 +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25 (0x00000000) +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28 (0x00000001) +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM (0x00000002) +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 24:24 +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING 25:25 +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE (0x00000000) +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE (0x00000001) +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 26:26 +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00000458 + (a)*0x00000300) +#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NV987D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000045C + (a)*0x00000300) +#define NV987D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV987D_HEAD_SET_OFFSET(a) (0x00000460 + (a)*0x00000300) +#define NV987D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV987D_HEAD_SET_SIZE(a) (0x00000468 + (a)*0x00000300) +#define NV987D_HEAD_SET_SIZE_WIDTH 15:0 +#define NV987D_HEAD_SET_SIZE_HEIGHT 31:16 +#define NV987D_HEAD_SET_STORAGE(a) (0x0000046C + (a)*0x00000300) +#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV987D_HEAD_SET_STORAGE_PITCH 20:8 +#define NV987D_HEAD_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV987D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV987D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV987D_HEAD_SET_PARAMS(a) (0x00000470 + (a)*0x00000300) +#define NV987D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV987D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV987D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV987D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV987D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV987D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV987D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV987D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV987D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024) +#define NV987D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV987D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV987D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV987D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV987D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV987D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV987D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV987D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV987D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV987D_HEAD_SET_PARAMS_GAMMA 2:2 +#define NV987D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV987D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV987D_HEAD_SET_CONTEXT_DMAS_ISO(a) (0x00000474 + (a)*0x00000300) +#define NV987D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV987D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x0000047C + (a)*0x00000300) +#define NV987D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 1:0 +#define NV987D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NV987D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NV987D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_SPEC_FLIP (0x00000002) +#define NV987D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300) +#define NV987D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV987D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV987D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV987D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV987D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV987D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV987D_HEAD_SET_CONTROL_CURSOR_SIZE 27:26 +#define NV987D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV987D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV987D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NV987D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NV987D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 15:8 +#define NV987D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 23:16 +#define NV987D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV987D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV987D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV987D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV987D_HEAD_SET_OFFSETS_CURSOR(a,b) (0x00000484 + (a)*0x00000300 + (b)*0x00000004) +#define NV987D_HEAD_SET_OFFSETS_CURSOR_ORIGIN 31:0 +#define NV987D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b) (0x0000048C + (a)*0x00000300 + (b)*0x00000004) +#define NV987D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE 31:0 +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00000494 + (a)*0x00000300) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422 8:8 +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE (0x00000000) +#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE (0x00000001) +#define NV987D_HEAD_SET_PROCAMP(a) (0x00000498 + (a)*0x00000300) +#define NV987D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV987D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV987D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV987D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV987D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003) +#define NV987D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV987D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV987D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV987D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV987D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV987D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 5:5 +#define NV987D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NV987D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NV987D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 6:6 +#define NV987D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) +#define NV987D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) +#define NV987D_HEAD_SET_DITHER_CONTROL(a) (0x000004A0 + (a)*0x00000300) +#define NV987D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV987D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV987D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV987D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV987D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV987D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV987D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002) +#define NV987D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV987D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV987D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV987D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV987D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV987D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NV987D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV987D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x000004B0 + (a)*0x00000300) +#define NV987D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV987D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV987D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000004B8 + (a)*0x00000300) +#define NV987D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV987D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV987D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x000004BC + (a)*0x00000300) +#define NV987D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NV987D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000004C0 + (a)*0x00000300) +#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000004C4 + (a)*0x00000300) +#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a) (0x000004C8 + (a)*0x00000300) +#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH 14:0 +#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT 30:16 +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT 17:16 +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE (0x00000000) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257 (0x00000001) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025 (0x00000002) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT 21:20 +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) +#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x000004D4 + (a)*0x00000300) +#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT 13:12 +#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE (0x00000000) +#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257 (0x00000001) +#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025 (0x00000002) +#define NV987D_HEAD_SET_PROCESSING(a) (0x000004E0 + (a)*0x00000300) +#define NV987D_HEAD_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV987D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV987D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV987D_HEAD_SET_CONVERSION_RED(a) (0x000004E4 + (a)*0x00000300) +#define NV987D_HEAD_SET_CONVERSION_RED_GAIN 15:0 +#define NV987D_HEAD_SET_CONVERSION_RED_OFS 31:16 +#define NV987D_HEAD_SET_CONVERSION_GRN(a) (0x000004E8 + (a)*0x00000300) +#define NV987D_HEAD_SET_CONVERSION_GRN_GAIN 15:0 +#define NV987D_HEAD_SET_CONVERSION_GRN_OFS 31:16 +#define NV987D_HEAD_SET_CONVERSION_BLU(a) (0x000004EC + (a)*0x00000300) +#define NV987D_HEAD_SET_CONVERSION_BLU_GAIN 15:0 +#define NV987D_HEAD_SET_CONVERSION_BLU_OFS 31:16 +#define NV987D_HEAD_SET_CSC_RED2RED(a) (0x000004F0 + (a)*0x00000300) +#define NV987D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE 31:31 +#define NV987D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV987D_HEAD_SET_CSC_RED2RED_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV987D_HEAD_SET_CSC_RED2RED_COEFF 18:0 +#define NV987D_HEAD_SET_CSC_GRN2RED(a) (0x000004F4 + (a)*0x00000300) +#define NV987D_HEAD_SET_CSC_GRN2RED_COEFF 18:0 +#define NV987D_HEAD_SET_CSC_BLU2RED(a) (0x000004F8 + (a)*0x00000300) +#define NV987D_HEAD_SET_CSC_BLU2RED_COEFF 18:0 +#define NV987D_HEAD_SET_CSC_CONSTANT2RED(a) (0x000004FC + (a)*0x00000300) +#define NV987D_HEAD_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV987D_HEAD_SET_CSC_RED2GRN(a) (0x00000500 + (a)*0x00000300) +#define NV987D_HEAD_SET_CSC_RED2GRN_COEFF 18:0 +#define NV987D_HEAD_SET_CSC_GRN2GRN(a) (0x00000504 + (a)*0x00000300) +#define NV987D_HEAD_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV987D_HEAD_SET_CSC_BLU2GRN(a) (0x00000508 + (a)*0x00000300) +#define NV987D_HEAD_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV987D_HEAD_SET_CSC_CONSTANT2GRN(a) (0x0000050C + (a)*0x00000300) +#define NV987D_HEAD_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV987D_HEAD_SET_CSC_RED2BLU(a) (0x00000510 + (a)*0x00000300) +#define NV987D_HEAD_SET_CSC_RED2BLU_COEFF 18:0 +#define NV987D_HEAD_SET_CSC_GRN2BLU(a) (0x00000514 + (a)*0x00000300) +#define NV987D_HEAD_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV987D_HEAD_SET_CSC_BLU2BLU(a) (0x00000518 + (a)*0x00000300) +#define NV987D_HEAD_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV987D_HEAD_SET_CSC_CONSTANT2BLU(a) (0x0000051C + (a)*0x00000300) +#define NV987D_HEAD_SET_CSC_CONSTANT2BLU_COEFF 18:0 +#define NV987D_HEAD_SET_HDMI_CTRL(a) (0x00000520 + (a)*0x00000300) +#define NV987D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NV987D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NV987D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NV987D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NV987D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NV987D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE 15:12 +#define NV987D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000000) +#define NV987D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_FIELD_ALTERNATIVE (0x00000001) +#define NV987D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_LINE_ALTERNATIVE (0x00000002) +#define NV987D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_FULL (0x00000003) +#define NV987D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH (0x00000004) +#define NV987D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_L_DEPTH_GRAPHICS (0x00000005) +#define NV987D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_TOP_AND_BOTTOM (0x00000006) +#define NV987D_HEAD_SET_HDMI_CTRL_STEREO3D_STRUCTURE_SIDE_BY_SIDE_HALF (0x00000008) +#define NV987D_HEAD_SET_VACTIVE_SPACE_COLOR(a) (0x00000524 + (a)*0x00000300) +#define NV987D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR 9:0 +#define NV987D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y 19:10 +#define NV987D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB 29:20 +#define NV987D_HEAD_SET_PIXEL_REORDER_CONTROL(a) (0x00000528 + (a)*0x00000300) +#define NV987D_HEAD_SET_PIXEL_REORDER_CONTROL_BANK_WIDTH 13:0 +#define NV987D_HEAD_SET_DISPLAY_ID(a,b) (0x0000052C + (a)*0x00000300 + (b)*0x00000004) +#define NV987D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NV987D_HEAD_SET_SW_SPARE_A(a) (0x0000054C + (a)*0x00000300) +#define NV987D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NV987D_HEAD_SET_SW_SPARE_B(a) (0x00000550 + (a)*0x00000300) +#define NV987D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NV987D_HEAD_SET_SW_SPARE_C(a) (0x00000554 + (a)*0x00000300) +#define NV987D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NV987D_HEAD_SET_SW_SPARE_D(a) (0x00000558 + (a)*0x00000300) +#define NV987D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NV987D_HEAD_SET_GET_BLANKING_CTRL(a) (0x0000055C + (a)*0x00000300) +#define NV987D_HEAD_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NV987D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NV987D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NV987D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NV987D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NV987D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) +#define NV987D_HEAD_SET_CONTROL_COMPRESSION(a) (0x00000560 + (a)*0x00000300) +#define NV987D_HEAD_SET_CONTROL_COMPRESSION_ENABLE 0:0 +#define NV987D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_DISABLE (0x00000000) +#define NV987D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_ENABLE (0x00000001) +#define NV987D_HEAD_SET_CONTROL_COMPRESSION_CHUNK_BANDWIDTH 12:1 +#define NV987D_HEAD_SET_CONTROL_COMPRESSION_LAST_BANDWIDTH 24:13 +#define NV987D_HEAD_SET_CONTROL_COMPRESSION_LA(a) (0x00000564 + (a)*0x00000300) +#define NV987D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY1 7:4 +#define NV987D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY2 11:8 +#define NV987D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY3 15:12 +#define NV987D_HEAD_SET_CONTROL_COMPRESSION_LA_CHUNK_SIZE 23:16 +#define NV987D_HEAD_SET_STALL_LOCK(a) (0x00000568 + (a)*0x00000300) +#define NV987D_HEAD_SET_STALL_LOCK_ENABLE 0:0 +#define NV987D_HEAD_SET_STALL_LOCK_ENABLE_FALSE (0x00000000) +#define NV987D_HEAD_SET_STALL_LOCK_ENABLE_TRUE (0x00000001) +#define NV987D_HEAD_SET_STALL_LOCK_MODE 1:1 +#define NV987D_HEAD_SET_STALL_LOCK_MODE_CONTINUOUS (0x00000000) +#define NV987D_HEAD_SET_STALL_LOCK_MODE_ONE_SHOT (0x00000001) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN 6:2 +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(i) (0x00000000 +(i)) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_0 (0x00000000) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_1 (0x00000001) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_2 (0x00000002) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_3 (0x00000003) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_4 (0x00000004) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_5 (0x00000005) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_6 (0x00000006) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_7 (0x00000007) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_8 (0x00000008) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_9 (0x00000009) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_A (0x0000000A) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_B (0x0000000B) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_C (0x0000000C) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_D (0x0000000D) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_E (0x0000000E) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_F (0x0000000F) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_UNSPECIFIED (0x00000010) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 4 +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK(i) (0x0000001E +(i)) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK__SIZE_1 2 +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x0000001E) +#define NV987D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x0000001F) +#define NV987D_HEAD_SET_STALL_LOCK_UNSTALL_MODE 7:7 +#define NV987D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_CRASH_LOCK (0x00000000) +#define NV987D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_LINE_LOCK (0x00000001) +#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a) (0x000006D0 + (a)*0x00000300) +#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED 31:0 +#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a) (0x000006D4 + (a)*0x00000300) +#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED 31:0 +#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a) (0x000006D8 + (a)*0x00000300) +#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED 31:0 +#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a) (0x000006DC + (a)*0x00000300) +#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED 31:0 +#define NV987D_HEAD_SET_SPARE(a) (0x000006EC + (a)*0x00000300) +#define NV987D_HEAD_SET_SPARE_UNUSED 31:0 +#define NV987D_HEAD_SET_SPARE_NOOP(a,b) (0x000006F0 + (a)*0x00000300 + (b)*0x00000004) +#define NV987D_HEAD_SET_SPARE_NOOP_UNUSED 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl987d_h diff --git a/userspace/sdks/nv570/nvidia/inc/class/cla06c.h b/userspace/sdks/nv570/nvidia/inc/class/cla06c.h new file mode 100644 index 0000000..0b4f5c9 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cla06c.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _cla06c_h_ +#define _cla06c_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define KEPLER_CHANNEL_GROUP_A (0x0000A06C) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cla06c_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cla06f.h b/userspace/sdks/nv570/nvidia/inc/class/cla06f.h new file mode 100644 index 0000000..336cab5 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cla06f.h @@ -0,0 +1,240 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clA06f_h_ +#define _clA06f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class KEPLER_CHANNEL_GPFIFO */ +/* + * Documentation for KEPLER_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + */ +#define KEPLER_CHANNEL_GPFIFO_A (0x0000A06F) + + +/* pio method data structure */ +typedef volatile struct _cla06f_tag0 { + NvV32 Reserved00[0x7c0]; +} NvA06FTypedef, KEPLER_ChannelGPFifo; +#define NVA06F_TYPEDEF KEPLER_CHANNELChannelGPFifo +/* dma flow control data structure */ +typedef volatile struct _cla06f_tag1 { + NvU32 Ignored00[0x010]; /* 0000-0043*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} NvA06FControl, KeplerAControlGPFifo; +/* fields and values */ +#define NVA06F_NUMBER_OF_SUBCHANNELS (8) +#define NVA06F_SET_OBJECT (0x00000000) +#define NVA06F_SET_OBJECT_NVCLASS 15:0 +#define NVA06F_SET_OBJECT_ENGINE 20:16 +#define NVA06F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVA06F_ILLEGAL (0x00000004) +#define NVA06F_ILLEGAL_HANDLE 31:0 +#define NVA06F_NOP (0x00000008) +#define NVA06F_NOP_HANDLE 31:0 +#define NVA06F_SEMAPHOREA (0x00000010) +#define NVA06F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVA06F_SEMAPHOREB (0x00000014) +#define NVA06F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVA06F_SEMAPHOREC (0x00000018) +#define NVA06F_SEMAPHOREC_PAYLOAD 31:0 +#define NVA06F_SEMAPHORED (0x0000001C) +#define NVA06F_SEMAPHORED_OPERATION 3:0 +#define NVA06F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVA06F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVA06F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVA06F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVA06F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVA06F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVA06F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVA06F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVA06F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVA06F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVA06F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVA06F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVA06F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVA06F_NON_STALL_INTERRUPT (0x00000020) +#define NVA06F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVA06F_FB_FLUSH (0x00000024) +#define NVA06F_FB_FLUSH_HANDLE 31:0 +#define NVA06F_MEM_OP_A (0x00000028) +#define NVA06F_MEM_OP_A_OPERAND_LOW 31:2 +#define NVA06F_MEM_OP_A_TLB_INVALIDATE_ADDR 29:2 +#define NVA06F_MEM_OP_A_TLB_INVALIDATE_TARGET 31:30 +#define NVA06F_MEM_OP_A_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000 +#define NVA06F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002 +#define NVA06F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 +#define NVA06F_MEM_OP_B (0x0000002c) +#define NVA06F_MEM_OP_B_OPERAND_HIGH 7:0 +#define NVA06F_MEM_OP_B_OPERATION 31:27 +#define NVA06F_MEM_OP_B_OPERATION_SYSMEMBAR_FLUSH 0x00000005 +#define NVA06F_MEM_OP_B_OPERATION_SOFT_FLUSH 0x00000006 +#define NVA06F_MEM_OP_B_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVA06F_MEM_OP_B_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NVA06F_MEM_OP_B_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +#define NVA06F_MEM_OP_B_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVA06F_MEM_OP_B_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB 0:0 +#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ALL 0x00000001 +#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC 1:1 +#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVA06F_SET_REFERENCE (0x00000050) +#define NVA06F_SET_REFERENCE_COUNT 31:0 +#define NVA06F_CRC_CHECK (0x0000007c) +#define NVA06F_CRC_CHECK_VALUE 31:0 +#define NVA06F_YIELD (0x00000080) +#define NVA06F_YIELD_OP 1:0 +#define NVA06F_YIELD_OP_NOP 0x00000000 + + +/* GPFIFO entry format */ +#define NVA06F_GP_ENTRY__SIZE 8 +#define NVA06F_GP_ENTRY0_FETCH 0:0 +#define NVA06F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVA06F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVA06F_GP_ENTRY0_GET 31:2 +#define NVA06F_GP_ENTRY0_OPERAND 31:0 +#define NVA06F_GP_ENTRY1_GET_HI 7:0 +#define NVA06F_GP_ENTRY1_PRIV 8:8 +#define NVA06F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NVA06F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NVA06F_GP_ENTRY1_LEVEL 9:9 +#define NVA06F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVA06F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVA06F_GP_ENTRY1_LENGTH 30:10 +#define NVA06F_GP_ENTRY1_SYNC 31:31 +#define NVA06F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVA06F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVA06F_GP_ENTRY1_OPCODE 7:0 +#define NVA06F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVA06F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVA06F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVA06F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVA06F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVA06F_DMA_METHOD_ADDRESS 11:0 +#define NVA06F_DMA_SUBDEVICE_MASK 15:4 +#define NVA06F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVA06F_DMA_TERT_OP 17:16 +#define NVA06F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVA06F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVA06F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVA06F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVA06F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVA06F_DMA_METHOD_COUNT_OLD 28:18 +#define NVA06F_DMA_METHOD_COUNT 28:16 +#define NVA06F_DMA_IMMD_DATA 28:16 +#define NVA06F_DMA_SEC_OP 31:29 +#define NVA06F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVA06F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVA06F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVA06F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVA06F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVA06F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVA06F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVA06F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVA06F_DMA_INCR_ADDRESS 11:0 +#define NVA06F_DMA_INCR_SUBCHANNEL 15:13 +#define NVA06F_DMA_INCR_COUNT 28:16 +#define NVA06F_DMA_INCR_OPCODE 31:29 +#define NVA06F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVA06F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVA06F_DMA_NONINCR_ADDRESS 11:0 +#define NVA06F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVA06F_DMA_NONINCR_COUNT 28:16 +#define NVA06F_DMA_NONINCR_OPCODE 31:29 +#define NVA06F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVA06F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVA06F_DMA_ONEINCR_ADDRESS 11:0 +#define NVA06F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVA06F_DMA_ONEINCR_COUNT 28:16 +#define NVA06F_DMA_ONEINCR_OPCODE 31:29 +#define NVA06F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVA06F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVA06F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVA06F_DMA_IMMD_ADDRESS 11:0 +#define NVA06F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVA06F_DMA_IMMD_DATA 28:16 +#define NVA06F_DMA_IMMD_OPCODE 31:29 +#define NVA06F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVA06F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVA06F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA06F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVA06F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVA06F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA06F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVA06F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA06F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVA06F_DMA_ENDSEG_OPCODE 31:29 +#define NVA06F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVA06F_DMA_ADDRESS 12:2 +#define NVA06F_DMA_SUBCH 15:13 +#define NVA06F_DMA_OPCODE3 17:16 +#define NVA06F_DMA_OPCODE3_NONE (0x00000000) +#define NVA06F_DMA_COUNT 28:18 +#define NVA06F_DMA_OPCODE 31:29 +#define NVA06F_DMA_OPCODE_METHOD (0x00000000) +#define NVA06F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVA06F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clA06F_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cla06fsubch.h b/userspace/sdks/nv570/nvidia/inc/class/cla06fsubch.h new file mode 100644 index 0000000..330a681 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cla06fsubch.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cla06fsubch_h_ +#define _cla06fsubch_h_ + +#define NVA06F_SUBCHANNEL_2D 3 +#define NVA06F_SUBCHANNEL_3D 0 +#define NVA06F_SUBCHANNEL_COMPUTE 1 +#define NVA06F_SUBCHANNEL_COPY_ENGINE 4 +#define NVA06F_SUBCHANNEL_I2M 2 + +#endif // _cla06fsubch_h_ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cla06fsw.h b/userspace/sdks/nv570/nvidia/inc/class/cla06fsw.h new file mode 100644 index 0000000..99c3b8a --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cla06fsw.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cla06f_sw_h_ +#define _cla06f_sw_h_ + +#define NVA06F_NOTIFIERS_RC (0) +#define NVA06F_NOTIFIERS_REFCNT (1) +#define NVA06F_NOTIFIERS_NONSTALL (2) +#define NVA06F_NOTIFIERS_EVENTBUFFER (3) +#define NVA06F_NOTIFIERS_IDLECHANNEL (4) +#define NVA06F_NOTIFIERS_ENDCTX (5) +#define NVA06F_NOTIFIERS_SW (6) +#define NVA06F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVA06F_NOTIFIERS_MAXCOUNT (8) + +/* NvNotification[] fields and values */ +#define NVA06F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVA06F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _cla06f_sw_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cla081.h b/userspace/sdks/nv570/nvidia/inc/class/cla081.h new file mode 100644 index 0000000..d17271a --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cla081.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cla081_h_ +#define _cla081_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVA081_VGPU_CONFIG (0x0000a081) + +/*event values*/ +#define NVA081_NOTIFIERS_EVENT_VGPU_GUEST_CREATED (0) +#define NVA081_NOTIFIERS_EVENT_VGPU_GUEST_INITIALISING (1) +#define NVA081_NOTIFIERS_EVENT_VGPU_GUEST_DESTROYED (2) +#define NVA081_NOTIFIERS_MAXCOUNT (5) + + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cla081_h diff --git a/userspace/sdks/nv570/nvidia/inc/class/cla084.h b/userspace/sdks/nv570/nvidia/inc/class/cla084.h new file mode 100644 index 0000000..a224c6d --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cla084.h @@ -0,0 +1,77 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cla084.finn +// + +#include "nv_vgpu_types.h" +#include "cla084_notification.h" + +#define NVA084_KERNEL_HOST_VGPU_DEVICE (0xa084U) /* finn: Evaluated from "NVA084_ALLOC_PARAMETERS_MESSAGE_ID" */ + +#define NVA084_MAX_VMMU_SEGMENTS 384 + +/* + * NVA084_ALLOC_PARAMETERS + * + * This structure represents vGPU host device KERNEL object allocation parameters. + * dbdf -> domain (31:16), bus (15:8), device (7:3), function (2:0) + * gfid -> Used only when SRIOV is enabled otherwise set to 0. + * swizzId [IN/OUT] -> Used only when MIG mode is enabled otherwise set + * to NV2080_CTRL_GPU_PARTITION_ID_INVALID. + * numChannels -> Used only when SRIOV is enabled. Must be a power of 2. + * bDisableDefaultSmcExecPartRestore - If set to true, SMC default execution partition + * save/restore will not be done in host-RM + * vgpuDeviceInstanceId -> Specifies the vGPU device instance per VM to be used + * for supporting multiple vGPUs per VM. + * numGuestFbHandles -> number of guest memory handles + * guestFbHandleList -> handle list to guest memory + * hPluginHeapMemory -> plugin heap memory handle + * bDeviceProfilingEnabled -> If set to true, profiling is allowed + */ +#define NVA084_ALLOC_PARAMETERS_MESSAGE_ID (0xa084U) + +typedef struct NVA084_ALLOC_PARAMETERS { + NvU32 dbdf; + NvU32 gfid; + NvU32 swizzId; + NvU32 vgpuType; + NvU32 vmPid; + NvU32 numChannels; + NvU32 numPluginChannels; + VM_ID_TYPE vmIdType; + NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); + NvBool bDisableDefaultSmcExecPartRestore; + NvU32 vgpuDeviceInstanceId; + NvU32 numGuestFbHandles; + NvHandle guestFbHandleList[NVA084_MAX_VMMU_SEGMENTS]; + NvHandle hPluginHeapMemory; + NV_DECLARE_ALIGNED(NvU64 ctrlBuffOffset, 8); + NvBool bDeviceProfilingEnabled; +} NVA084_ALLOC_PARAMETERS; diff --git a/userspace/sdks/nv570/nvidia/inc/class/cla084_notification.h b/userspace/sdks/nv570/nvidia/inc/class/cla084_notification.h new file mode 100644 index 0000000..da2ec5b --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cla084_notification.h @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cla084_notification_h_ +#define _cla084_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +// +// @todo: We will define the actual event values later based on the use case. +// These event values are only for Test purpose. +// +/* event values */ +#define NVA084_NOTIFIERS_EVENT_VGPU_PLUGIN_TASK_BOOTLOADED (0) +#define NVA084_NOTIFIERS_EVENT_VGPU_PLUGIN_TASK_UNLOADED (1) +#define NVA084_NOTIFIERS_EVENT_VGPU_PLUGIN_TASK_CRASHED (2) +#define NVA084_NOTIFIERS_EVENT_GUEST_DRIVER_LOADED (3) +#define NVA084_NOTIFIERS_EVENT_GUEST_DRIVER_UNLOADED (4) +#define NVA084_NOTIFIERS_MAXCOUNT (5) + +#define NVA084_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NVA084_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000) +#define NVA084_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000) +#define NVA084_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000) +#define NVA084_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cla084_notification_h_ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cla097.h b/userspace/sdks/nv570/nvidia/inc/class/cla097.h new file mode 100644 index 0000000..9ebbcfd --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cla097.h @@ -0,0 +1,3817 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_kepler_a_h_ +#define _cl_kepler_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl kepler_a */ + +#include "nvtypes.h" + +#define KEPLER_A 0xA097 + +#define NVA097_SET_OBJECT 0x0000 +#define NVA097_SET_OBJECT_CLASS_ID 15:0 +#define NVA097_SET_OBJECT_ENGINE_ID 20:16 + +#define NVA097_NO_OPERATION 0x0100 +#define NVA097_NO_OPERATION_V 31:0 + +#define NVA097_SET_NOTIFY_A 0x0104 +#define NVA097_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVA097_SET_NOTIFY_B 0x0108 +#define NVA097_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVA097_NOTIFY 0x010c +#define NVA097_NOTIFY_TYPE 31:0 +#define NVA097_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVA097_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVA097_WAIT_FOR_IDLE 0x0110 +#define NVA097_WAIT_FOR_IDLE_V 31:0 + +#define NVA097_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVA097_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVA097_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVA097_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVA097_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVA097_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVA097_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVA097_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVA097_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVA097_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVA097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVA097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVA097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVA097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVA097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVA097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVA097_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVA097_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVA097_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA097_SEND_GO_IDLE 0x013c +#define NVA097_SEND_GO_IDLE_V 31:0 + +#define NVA097_PM_TRIGGER 0x0140 +#define NVA097_PM_TRIGGER_V 31:0 + +#define NVA097_PM_TRIGGER_WFI 0x0144 +#define NVA097_PM_TRIGGER_WFI_V 31:0 + +#define NVA097_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVA097_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVA097_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVA097_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVA097_LINE_LENGTH_IN 0x0180 +#define NVA097_LINE_LENGTH_IN_VALUE 31:0 + +#define NVA097_LINE_COUNT 0x0184 +#define NVA097_LINE_COUNT_VALUE 31:0 + +#define NVA097_OFFSET_OUT_UPPER 0x0188 +#define NVA097_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVA097_OFFSET_OUT 0x018c +#define NVA097_OFFSET_OUT_VALUE 31:0 + +#define NVA097_PITCH_OUT 0x0190 +#define NVA097_PITCH_OUT_VALUE 31:0 + +#define NVA097_SET_DST_BLOCK_SIZE 0x0194 +#define NVA097_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVA097_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVA097_SET_DST_WIDTH 0x0198 +#define NVA097_SET_DST_WIDTH_V 31:0 + +#define NVA097_SET_DST_HEIGHT 0x019c +#define NVA097_SET_DST_HEIGHT_V 31:0 + +#define NVA097_SET_DST_DEPTH 0x01a0 +#define NVA097_SET_DST_DEPTH_V 31:0 + +#define NVA097_SET_DST_LAYER 0x01a4 +#define NVA097_SET_DST_LAYER_V 31:0 + +#define NVA097_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVA097_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVA097_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVA097_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVA097_LAUNCH_DMA 0x01b0 +#define NVA097_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVA097_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA097_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA097_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVA097_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVA097_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVA097_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVA097_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVA097_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVA097_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVA097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVA097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVA097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVA097_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVA097_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA097_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA097_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA097_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVA097_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA097_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA097_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVA097_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVA097_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVA097_LOAD_INLINE_DATA 0x01b4 +#define NVA097_LOAD_INLINE_DATA_V 31:0 + +#define NVA097_SET_I2M_SEMAPHORE_A 0x01dc +#define NVA097_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVA097_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVA097_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA097_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVA097_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVA097_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVA097_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVA097_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVA097_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVA097_SET_I2M_SPARE_NOOP03 0x01fc +#define NVA097_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVA097_RUN_DS_NOW 0x0200 +#define NVA097_RUN_DS_NOW_V 31:0 + +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVA097_SET_RASTER_PIPE_SYNC_CONTROL 0x0208 +#define NVA097_SET_RASTER_PIPE_SYNC_CONTROL_PRIM_AREA_THRESHOLD 21:0 +#define NVA097_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE 24:24 +#define NVA097_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE_FALSE 0x00000000 +#define NVA097_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVA097_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVA097_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVA097_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVA097_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVA097_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_GS_DM_FIFO 0x0214 +#define NVA097_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVA097_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVA097_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVA097_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVA097_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA097_INVALIDATE_SHADER_CACHES 0x021c +#define NVA097_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVA097_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVA097_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVA097_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVA097_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVA097_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVA097_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVA097_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVA097_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVA097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVA097_SET_VAB_VERTEX3F(i) (0x0220+(i)*4) +#define NVA097_SET_VAB_VERTEX3F_V 31:0 + +#define NVA097_SET_VAB_VERTEX4F(i) (0x0230+(i)*4) +#define NVA097_SET_VAB_VERTEX4F_V 31:0 + +#define NVA097_SET_VAB_NORMAL3F(i) (0x0240+(i)*4) +#define NVA097_SET_VAB_NORMAL3F_V 31:0 + +#define NVA097_SET_VAB_COLOR3F(i) (0x0250+(i)*4) +#define NVA097_SET_VAB_COLOR3F_V 31:0 + +#define NVA097_SET_VAB_COLOR4F(i) (0x0260+(i)*4) +#define NVA097_SET_VAB_COLOR4F_V 31:0 + +#define NVA097_SET_VAB_COLOR4UB(i) (0x0270+(i)*4) +#define NVA097_SET_VAB_COLOR4UB_V 31:0 + +#define NVA097_SET_VAB_TEX_COORD1F(i) (0x0280+(i)*4) +#define NVA097_SET_VAB_TEX_COORD1F_V 31:0 + +#define NVA097_SET_VAB_TEX_COORD2F(i) (0x0290+(i)*4) +#define NVA097_SET_VAB_TEX_COORD2F_V 31:0 + +#define NVA097_SET_VAB_TEX_COORD3F(i) (0x02a0+(i)*4) +#define NVA097_SET_VAB_TEX_COORD3F_V 31:0 + +#define NVA097_SET_VAB_TEX_COORD4F(i) (0x02b0+(i)*4) +#define NVA097_SET_VAB_TEX_COORD4F_V 31:0 + +#define NVA097_SET_TASK_CIRCULAR_BUFFER_THROTTLE 0x02cc +#define NVA097_SET_TASK_CIRCULAR_BUFFER_THROTTLE_TASK_COUNT 21:0 + +#define NVA097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NVA097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NVA097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVA097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVA097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVA097_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 9:0 + +#define NVA097_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVA097_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVA097_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVA097_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVA097_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVA097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVA097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVA097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVA097_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVA097_SET_ZCULL_SUBREGION 0x02e8 +#define NVA097_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVA097_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVA097_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVA097_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVA097_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVA097_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVA097_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVA097_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVA097_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVA097_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVA097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVA097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVA097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVA097_DRAW_ZERO_INDEX 0x0304 +#define NVA097_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVA097_SET_L1_CONFIGURATION 0x0308 +#define NVA097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVA097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVA097_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVA097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVA097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVA097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVA097_SET_SPA_VERSION 0x0310 +#define NVA097_SET_SPA_VERSION_MINOR 7:0 +#define NVA097_SET_SPA_VERSION_MAJOR 15:8 + +#define NVA097_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NVA097_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NVA097_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_SNAP_GRID_LINE 0x0318 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVA097_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVA097_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVA097_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVA097_SET_SNAP_GRID_NON_LINE 0x031c +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVA097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVA097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVA097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVA097_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVA097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVA097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVA097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVA097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVA097_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVA097_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVA097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVA097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVA097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVA097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVA097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVA097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVA097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVA097_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVA097_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVA097_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVA097_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVA097_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVA097_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVA097_SET_TESSELLATION_LOD_V1 0x0330 +#define NVA097_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVA097_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVA097_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVA097_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVA097_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVA097_RESERVED_TG07 0x033c +#define NVA097_RESERVED_TG07_V 0:0 + +#define NVA097_RESERVED_TG08 0x0340 +#define NVA097_RESERVED_TG08_V 0:0 + +#define NVA097_RESERVED_TG09 0x0344 +#define NVA097_RESERVED_TG09_V 0:0 + +#define NVA097_RESERVED_TG10 0x0348 +#define NVA097_RESERVED_TG10_V 0:0 + +#define NVA097_RESERVED_TG11 0x034c +#define NVA097_RESERVED_TG11_V 0:0 + +#define NVA097_RESERVED_TG12 0x0350 +#define NVA097_RESERVED_TG12_V 0:0 + +#define NVA097_RESERVED_TG13 0x0354 +#define NVA097_RESERVED_TG13_V 0:0 + +#define NVA097_RESERVED_TG14 0x0358 +#define NVA097_RESERVED_TG14_V 0:0 + +#define NVA097_RESERVED_TG15 0x035c +#define NVA097_RESERVED_TG15_V 0:0 + +#define NVA097_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVA097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVA097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVA097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVA097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVA097_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVA097_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVA097_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVA097_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVA097_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVA097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVA097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVA097_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVA097_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVA097_SET_RASTER_ENABLE 0x037c +#define NVA097_SET_RASTER_ENABLE_V 0:0 +#define NVA097_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVA097_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVA097_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVA097_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVA097_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVA097_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVA097_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVA097_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVA097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVA097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVA097_SET_VAB_DATA_TYPELESS(i) (0x0400+(i)*4) +#define NVA097_SET_VAB_DATA_TYPELESS_V 31:0 + +#define NVA097_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVA097_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVA097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVA097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVA097_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVA097_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVA097_SET_RASTER_INPUT 0x0740 +#define NVA097_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVA097_SET_STREAM_OUTPUT 0x0744 +#define NVA097_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVA097_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVA097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVA097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_ALPHA_FRACTION 0x074c +#define NVA097_SET_ALPHA_FRACTION_V 7:0 + +#define NVA097_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVA097_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVA097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVA097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVA097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 + +#define NVA097_SET_MAX_TI_WARPS_PER_BATCH 0x075c +#define NVA097_SET_MAX_TI_WARPS_PER_BATCH_V 5:0 + +#define NVA097_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVA097_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA097_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVA097_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVA097_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVA097_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVA097_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVA097_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVA097_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVA097_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVA097_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVA097_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVA097_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVA097_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVA097_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVA097_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVA097_SET_ISBE_SAVE_RESTORE_PROGRAM 0x07ac +#define NVA097_SET_ISBE_SAVE_RESTORE_PROGRAM_OFFSET 31:0 + +#define NVA097_SET_VAB_VERTEX2F(i) (0x07b0+(i)*4) +#define NVA097_SET_VAB_VERTEX2F_V 31:0 + +#define NVA097_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVA097_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVA097_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVA097_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVA097_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVA097_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVA097_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVA097_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVA097_SET_CULL_BEFORE_FETCH 0x07dc +#define NVA097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVA097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVA097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVA097_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVA097_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVA097_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVA097_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVA097_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVA097_SET_ZCULL_STORAGE_A 0x07e8 +#define NVA097_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVA097_SET_ZCULL_STORAGE_B 0x07ec +#define NVA097_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVA097_SET_ZCULL_STORAGE_C 0x07f0 +#define NVA097_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVA097_SET_ZCULL_STORAGE_D 0x07f4 +#define NVA097_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVA097_SET_ZT_READ_ONLY 0x07f8 +#define NVA097_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVA097_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVA097_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVA097_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVA097_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVA097_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVA097_SET_TEXTURE_INSTRUCTION_OPERAND 0x07fc +#define NVA097_SET_TEXTURE_INSTRUCTION_OPERAND_ORDERING 0:0 +#define NVA097_SET_TEXTURE_INSTRUCTION_OPERAND_ORDERING_FERMI_ORDER 0x00000000 +#define NVA097_SET_TEXTURE_INSTRUCTION_OPERAND_ORDERING_KEPLER_ORDER 0x00000001 + +#define NVA097_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVA097_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVA097_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVA097_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVA097_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVA097_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVA097_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVA097_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVA097_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVA097_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVA097_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVA097_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVA097_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVA097_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVA097_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVA097_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVA097_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVA097_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVA097_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA097_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVA097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVA097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVA097_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVA097_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVA097_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVA097_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVA097_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVA097_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVA097_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NVA097_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NVA097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVA097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVA097_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVA097_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVA097_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVA097_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVA097_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVA097_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVA097_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVA097_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVA097_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVA097_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVA097_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVA097_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVA097_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVA097_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVA097_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVA097_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVA097_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVA097_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVA097_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVA097_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVA097_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVA097_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVA097_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVA097_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVA097_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVA097_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVA097_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVA097_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVA097_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVA097_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVA097_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVA097_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVA097_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVA097_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVA097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVA097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVA097_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVA097_SET_STATISTICS_COUNTER 0x0d68 +#define NVA097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVA097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVA097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVA097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVA097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVA097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVA097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVA097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVA097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVA097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVA097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVA097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVA097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVA097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVA097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVA097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVA097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVA097_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVA097_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVA097_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVA097_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVA097_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVA097_SET_VERTEX_ARRAY_START 0x0d74 +#define NVA097_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVA097_DRAW_VERTEX_ARRAY 0x0d78 +#define NVA097_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVA097_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVA097_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVA097_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVA097_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVA097_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVA097_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVA097_SET_Z_CLEAR_VALUE 0x0d90 +#define NVA097_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVA097_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVA097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVA097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVA097_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVA097_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVA097_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVA097_SET_FRONT_POLYGON_MODE 0x0dac +#define NVA097_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVA097_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVA097_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVA097_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVA097_SET_BACK_POLYGON_MODE 0x0db0 +#define NVA097_SET_BACK_POLYGON_MODE_V 31:0 +#define NVA097_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVA097_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVA097_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVA097_SET_POLY_SMOOTH 0x0db4 +#define NVA097_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVA097_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVA097_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_ZT_MARK 0x0db8 +#define NVA097_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NVA097_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVA097_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVA097_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVA097_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVA097_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVA097_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVA097_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVA097_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVA097_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVA097_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVA097_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVA097_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_PATCH 0x0dcc +#define NVA097_SET_PATCH_SIZE 7:0 + +#define NVA097_SET_ZCULL_CRITERION 0x0dd8 +#define NVA097_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVA097_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVA097_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVA097_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVA097_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVA097_SET_ZCULL_CRITERION_SREF 23:16 +#define NVA097_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVA097_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVA097_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVA097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVA097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVA097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE 0x0dec +#define NVA097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE 0:0 +#define NVA097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_WINDOW_OFFSET_X 0x0df8 +#define NVA097_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVA097_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVA097_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVA097_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVA097_SET_SCISSOR_ENABLE_V 0:0 +#define NVA097_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVA097_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVA097_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVA097_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVA097_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVA097_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVA097_SET_VAB_NORMAL3S(i) (0x0f00+(i)*4) +#define NVA097_SET_VAB_NORMAL3S_V 31:0 + +#define NVA097_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVA097_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVA097_SET_BACK_STENCIL_MASK 0x0f58 +#define NVA097_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVA097_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVA097_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVA097_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVA097_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVA097_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVA097_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVA097_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVA097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVA097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVA097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVA097_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVA097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVA097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVA097_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVA097_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVA097_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVA097_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVA097_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVA097_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVA097_SET_CT_MRT_ENABLE 0x0fac +#define NVA097_SET_CT_MRT_ENABLE_V 0:0 +#define NVA097_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVA097_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVA097_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVA097_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVA097_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVA097_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVA097_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVA097_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVA097_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVA097_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVA097_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVA097_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVA097_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVA097_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVA097_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVA097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVA097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVA097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVA097_SET_ZT_A 0x0fe0 +#define NVA097_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_ZT_B 0x0fe4 +#define NVA097_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_ZT_FORMAT 0x0fe8 +#define NVA097_SET_ZT_FORMAT_V 4:0 +#define NVA097_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVA097_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVA097_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVA097_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVA097_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVA097_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVA097_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVA097_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVA097_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVA097_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVA097_SET_ZT_BLOCK_SIZE 0x0fec +#define NVA097_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVA097_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA097_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVA097_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVA097_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVA097_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVA097_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVA097_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVA097_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVA097_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVA097_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVA097_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA097_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVA097_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVA097_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVA097_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVA097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVA097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVA097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVA097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVA097_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVA097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVA097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVA097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVA097_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVA097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVA097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_SPARE_NOOP00 0x1040 +#define NVA097_SET_SPARE_NOOP00_V 31:0 + +#define NVA097_SET_SPARE_NOOP01 0x1044 +#define NVA097_SET_SPARE_NOOP01_V 31:0 + +#define NVA097_SET_SPARE_NOOP02 0x1048 +#define NVA097_SET_SPARE_NOOP02_V 31:0 + +#define NVA097_SET_SPARE_NOOP03 0x104c +#define NVA097_SET_SPARE_NOOP03_V 31:0 + +#define NVA097_SET_SPARE_NOOP04 0x1050 +#define NVA097_SET_SPARE_NOOP04_V 31:0 + +#define NVA097_SET_SPARE_NOOP05 0x1054 +#define NVA097_SET_SPARE_NOOP05_V 31:0 + +#define NVA097_SET_SPARE_NOOP06 0x1058 +#define NVA097_SET_SPARE_NOOP06_V 31:0 + +#define NVA097_SET_SPARE_NOOP07 0x105c +#define NVA097_SET_SPARE_NOOP07_V 31:0 + +#define NVA097_SET_SPARE_NOOP08 0x1060 +#define NVA097_SET_SPARE_NOOP08_V 31:0 + +#define NVA097_SET_SPARE_NOOP09 0x1064 +#define NVA097_SET_SPARE_NOOP09_V 31:0 + +#define NVA097_SET_SPARE_NOOP10 0x1068 +#define NVA097_SET_SPARE_NOOP10_V 31:0 + +#define NVA097_SET_SPARE_NOOP11 0x106c +#define NVA097_SET_SPARE_NOOP11_V 31:0 + +#define NVA097_SET_SPARE_NOOP12 0x1070 +#define NVA097_SET_SPARE_NOOP12_V 31:0 + +#define NVA097_SET_SPARE_NOOP13 0x1074 +#define NVA097_SET_SPARE_NOOP13_V 31:0 + +#define NVA097_SET_SPARE_NOOP14 0x1078 +#define NVA097_SET_SPARE_NOOP14_V 31:0 + +#define NVA097_SET_SPARE_NOOP15 0x107c +#define NVA097_SET_SPARE_NOOP15_V 31:0 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVA097_UNBIND_ALL 0x10f4 +#define NVA097_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVA097_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVA097_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVA097_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA097_NO_OPERATION_DATA_HI 0x110c +#define NVA097_NO_OPERATION_DATA_HI_V 31:0 + +#define NVA097_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVA097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVA097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVA097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVA097_PM_TRIGGER_END 0x1114 +#define NVA097_PM_TRIGGER_END_V 31:0 + +#define NVA097_SET_VERTEX_ID_BASE 0x1118 +#define NVA097_SET_VERTEX_ID_BASE_V 31:0 + +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVA097_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVA097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVA097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVA097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVA097_FLUSH_PENDING_WRITES 0x1144 +#define NVA097_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVA097_SET_VAB_DATA_CONTROL 0x114c +#define NVA097_SET_VAB_DATA_CONTROL_VAB_INDEX 7:0 +#define NVA097_SET_VAB_DATA_CONTROL_COMPONENT_COUNT 10:8 +#define NVA097_SET_VAB_DATA_CONTROL_COMPONENT_BYTE_WIDTH 14:12 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT 18:16 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_SNORM 0x00000001 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_UNORM 0x00000002 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_SINT 0x00000003 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_UINT 0x00000004 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_USCALED 0x00000005 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_SSCALED 0x00000006 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_FLOAT 0x00000007 + +#define NVA097_SET_VAB_DATA(i) (0x1150+(i)*4) +#define NVA097_SET_VAB_DATA_V 31:0 + +#define NVA097_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVA097_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVA097_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVA097_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_SET_CT_SELECT 0x121c +#define NVA097_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVA097_SET_CT_SELECT_TARGET0 6:4 +#define NVA097_SET_CT_SELECT_TARGET1 9:7 +#define NVA097_SET_CT_SELECT_TARGET2 12:10 +#define NVA097_SET_CT_SELECT_TARGET3 15:13 +#define NVA097_SET_CT_SELECT_TARGET4 18:16 +#define NVA097_SET_CT_SELECT_TARGET5 21:19 +#define NVA097_SET_CT_SELECT_TARGET6 24:22 +#define NVA097_SET_CT_SELECT_TARGET7 27:25 + +#define NVA097_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVA097_SET_ZT_SIZE_A 0x1228 +#define NVA097_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVA097_SET_ZT_SIZE_B 0x122c +#define NVA097_SET_ZT_SIZE_B_HEIGHT 16:0 + +#define NVA097_SET_ZT_SIZE_C 0x1230 +#define NVA097_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVA097_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVA097_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVA097_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVA097_SET_SAMPLER_BINDING 0x1234 +#define NVA097_SET_SAMPLER_BINDING_V 0:0 +#define NVA097_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVA097_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVA097_DRAW_AUTO 0x123c +#define NVA097_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVA097_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVA097_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 9:0 + +#define NVA097_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVA097_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVA097_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVA097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVA097_SET_SHADER_SCHEDULING 0x12ac +#define NVA097_SET_SHADER_SCHEDULING_MODE 0:0 +#define NVA097_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 +#define NVA097_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 + +#define NVA097_CLEAR_ZCULL_REGION 0x12c8 +#define NVA097_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVA097_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVA097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVA097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVA097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVA097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVA097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVA097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVA097_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVA097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVA097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVA097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVA097_SET_DEPTH_TEST 0x12cc +#define NVA097_SET_DEPTH_TEST_ENABLE 0:0 +#define NVA097_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_FILL_MODE 0x12d0 +#define NVA097_SET_FILL_MODE_V 31:0 +#define NVA097_SET_FILL_MODE_V_POINT 0x00000001 +#define NVA097_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVA097_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVA097_SET_SHADE_MODE 0x12d4 +#define NVA097_SET_SHADE_MODE_V 31:0 +#define NVA097_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVA097_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVA097_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVA097_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVA097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVA097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVA097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVA097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVA097_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVA097_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVA097_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVA097_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_DEPTH_WRITE 0x12e8 +#define NVA097_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVA097_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_ALPHA_TEST 0x12ec +#define NVA097_SET_ALPHA_TEST_ENABLE 0:0 +#define NVA097_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVA097_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVA097_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVA097_DRAW_INLINE_INDEX4X8 0x1304 +#define NVA097_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVA097_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVA097_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVA097_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVA097_D3D_SET_CULL_MODE 0x1308 +#define NVA097_D3D_SET_CULL_MODE_V 31:0 +#define NVA097_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVA097_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVA097_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVA097_SET_DEPTH_FUNC 0x130c +#define NVA097_SET_DEPTH_FUNC_V 31:0 +#define NVA097_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVA097_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVA097_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA097_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA097_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVA097_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA097_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA097_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA097_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVA097_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVA097_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA097_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA097_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVA097_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA097_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA097_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA097_SET_ALPHA_REF 0x1310 +#define NVA097_SET_ALPHA_REF_V 31:0 + +#define NVA097_SET_ALPHA_FUNC 0x1314 +#define NVA097_SET_ALPHA_FUNC_V 31:0 +#define NVA097_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVA097_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVA097_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA097_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA097_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVA097_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA097_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA097_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA097_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVA097_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVA097_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA097_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA097_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVA097_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA097_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA097_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA097_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVA097_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVA097_SET_BLEND_CONST_RED 0x131c +#define NVA097_SET_BLEND_CONST_RED_V 31:0 + +#define NVA097_SET_BLEND_CONST_GREEN 0x1320 +#define NVA097_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVA097_SET_BLEND_CONST_BLUE 0x1324 +#define NVA097_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVA097_SET_BLEND_CONST_ALPHA 0x1328 +#define NVA097_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVA097_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVA097_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVA097_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVA097_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVA097_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVA097_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVA097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVA097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVA097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_BLEND_COLOR_OP 0x1340 +#define NVA097_SET_BLEND_COLOR_OP_V 31:0 +#define NVA097_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA097_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA097_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA097_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVA097_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVA097_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVA097_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA097_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA097_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVA097_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_BLEND_ALPHA_OP 0x134c +#define NVA097_SET_BLEND_ALPHA_OP_V 31:0 +#define NVA097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA097_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVA097_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVA097_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVA097_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA097_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA097_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVA097_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVA097_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVA097_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVA097_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_SINGLE_ROP_CONTROL 0x135c +#define NVA097_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVA097_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_BLEND(i) (0x1360+(i)*4) +#define NVA097_SET_BLEND_ENABLE 0:0 +#define NVA097_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVA097_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_STENCIL_TEST 0x1380 +#define NVA097_SET_STENCIL_TEST_ENABLE 0:0 +#define NVA097_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_STENCIL_OP_FAIL 0x1384 +#define NVA097_SET_STENCIL_OP_FAIL_V 31:0 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVA097_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVA097_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVA097_SET_STENCIL_OP_ZPASS 0x138c +#define NVA097_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVA097_SET_STENCIL_FUNC 0x1390 +#define NVA097_SET_STENCIL_FUNC_V 31:0 +#define NVA097_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVA097_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVA097_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA097_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA097_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVA097_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA097_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA097_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA097_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVA097_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVA097_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA097_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA097_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVA097_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA097_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA097_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA097_SET_STENCIL_FUNC_REF 0x1394 +#define NVA097_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVA097_SET_STENCIL_FUNC_MASK 0x1398 +#define NVA097_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVA097_SET_STENCIL_MASK 0x139c +#define NVA097_SET_STENCIL_MASK_V 7:0 + +#define NVA097_SET_DRAW_AUTO_START 0x13a4 +#define NVA097_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVA097_SET_PS_SATURATE 0x13a8 +#define NVA097_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVA097_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVA097_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVA097_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVA097_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVA097_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVA097_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVA097_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVA097_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 + +#define NVA097_SET_WINDOW_ORIGIN 0x13ac +#define NVA097_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVA097_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVA097_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVA097_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVA097_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVA097_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVA097_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVA097_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVA097_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVA097_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVA097_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVA097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVA097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_ALPHA_HYSTERESIS 0x1420 +#define NVA097_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NVA097_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVA097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVA097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA097_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVA097_INVALIDATE_DA_DMA_CACHE 0x142c +#define NVA097_INVALIDATE_DA_DMA_CACHE_V 0:0 + +#define NVA097_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVA097_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVA097_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVA097_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVA097_SET_PS_WARP_WATERMARKS 0x1450 +#define NVA097_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVA097_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVA097_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVA097_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVA097_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVA097_STORE_ZCULL 0x1464 +#define NVA097_STORE_ZCULL_V 0:0 + +#define NVA097_LOAD_ZCULL 0x1500 +#define NVA097_LOAD_ZCULL_V 0:0 + +#define NVA097_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVA097_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVA097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVA097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVA097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVA097_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVA097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVA097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVA097_SET_USER_CLIP_ENABLE 0x1510 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVA097_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVA097_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVA097_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_POINT_SIZE 0x1518 +#define NVA097_SET_POINT_SIZE_V 31:0 + +#define NVA097_SET_ZCULL_STATS 0x151c +#define NVA097_SET_ZCULL_STATS_ENABLE 0:0 +#define NVA097_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_POINT_SPRITE 0x1520 +#define NVA097_SET_POINT_SPRITE_ENABLE 0:0 +#define NVA097_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_SHADER_EXCEPTIONS 0x1528 +#define NVA097_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVA097_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVA097_CLEAR_REPORT_VALUE 0x1530 +#define NVA097_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVA097_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVA097_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVA097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVA097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVA097_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVA097_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 + +#define NVA097_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVA097_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVA097_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_ZT_SELECT 0x1538 +#define NVA097_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVA097_SET_RENDER_ENABLE_A 0x1550 +#define NVA097_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_RENDER_ENABLE_B 0x1554 +#define NVA097_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_RENDER_ENABLE_C 0x1558 +#define NVA097_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVA097_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA097_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA097_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA097_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVA097_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVA097_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVA097_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVA097_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVA097_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVA097_SET_ANTI_ALIASED_LINE 0x1570 +#define NVA097_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVA097_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_TEX_HEADER_POOL_A 0x1574 +#define NVA097_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_TEX_HEADER_POOL_B 0x1578 +#define NVA097_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_TEX_HEADER_POOL_C 0x157c +#define NVA097_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVA097_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVA097_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVA097_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVA097_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVA097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVA097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVA097_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVA097_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVA097_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA097_SET_SRGB_WRITE 0x15b8 +#define NVA097_SET_SRGB_WRITE_ENABLE 0:0 +#define NVA097_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_DEPTH_BIAS 0x15bc +#define NVA097_SET_DEPTH_BIAS_V 31:0 + +#define NVA097_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVA097_SET_RT_LAYER 0x15cc +#define NVA097_SET_RT_LAYER_V 15:0 +#define NVA097_SET_RT_LAYER_CONTROL 16:16 +#define NVA097_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVA097_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVA097_SET_ANTI_ALIAS 0x15d0 +#define NVA097_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVA097_SET_EDGE_FLAG 0x15e4 +#define NVA097_SET_EDGE_FLAG_V 0:0 +#define NVA097_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVA097_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVA097_DRAW_INLINE_INDEX 0x15e8 +#define NVA097_DRAW_INLINE_INDEX_V 31:0 + +#define NVA097_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVA097_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVA097_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVA097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVA097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVA097_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVA097_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVA097_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVA097_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVA097_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVA097_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVA097_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVA097_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVA097_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVA097_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVA097_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVA097_SET_POINT_SPRITE_SELECT 0x1604 +#define NVA097_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVA097_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVA097_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVA097_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVA097_SET_PROGRAM_REGION_A 0x1608 +#define NVA097_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVA097_SET_PROGRAM_REGION_B 0x160c +#define NVA097_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVA097_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVA097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVA097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVA097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVA097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVA097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVA097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVA097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVA097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVA097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVA097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVA097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVA097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVA097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVA097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVA097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVA097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVA097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVA097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVA097_END 0x1614 +#define NVA097_END_V 0:0 + +#define NVA097_BEGIN 0x1618 +#define NVA097_BEGIN_OP 15:0 +#define NVA097_BEGIN_OP_POINTS 0x00000000 +#define NVA097_BEGIN_OP_LINES 0x00000001 +#define NVA097_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVA097_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVA097_BEGIN_OP_TRIANGLES 0x00000004 +#define NVA097_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVA097_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVA097_BEGIN_OP_QUADS 0x00000007 +#define NVA097_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVA097_BEGIN_OP_POLYGON 0x00000009 +#define NVA097_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVA097_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVA097_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_BEGIN_OP_PATCH 0x0000000E +#define NVA097_BEGIN_PRIMITIVE_ID 24:24 +#define NVA097_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVA097_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVA097_BEGIN_INSTANCE_ID 27:26 +#define NVA097_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVA097_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVA097_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVA097_BEGIN_SPLIT_MODE 30:29 +#define NVA097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVA097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVA097_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVA097_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 + +#define NVA097_SET_VERTEX_ID_COPY 0x161c +#define NVA097_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVA097_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVA097_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVA097_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVA097_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVA097_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVA097_LOAD_PRIMITIVE_ID 0x1624 +#define NVA097_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVA097_SET_SHADER_BASED_CULL 0x162c +#define NVA097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVA097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVA097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVA097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_CLASS_VERSION 0x1638 +#define NVA097_SET_CLASS_VERSION_CURRENT 15:0 +#define NVA097_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA097_SET_VAB_PAGE 0x163c +#define NVA097_SET_VAB_PAGE_READ_SELECT 0:0 +#define NVA097_SET_VAB_PAGE_READ_SELECT_PAGES_0_AND_1 0x00000000 +#define NVA097_SET_VAB_PAGE_READ_SELECT_PAGES_0_AND_2 0x00000001 + +#define NVA097_DRAW_INLINE_VERTEX 0x1640 +#define NVA097_DRAW_INLINE_VERTEX_V 31:0 + +#define NVA097_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVA097_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVA097_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVA097_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVA097_SET_DA_OUTPUT 0x164c +#define NVA097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVA097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVA097_SET_ANTI_ALIASED_POINT 0x1658 +#define NVA097_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVA097_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_POINT_CENTER_MODE 0x165c +#define NVA097_SET_POINT_CENTER_MODE_V 31:0 +#define NVA097_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVA097_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVA097_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVA097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVA097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVA097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVA097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVA097_SET_LINE_STIPPLE 0x166c +#define NVA097_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVA097_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVA097_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVA097_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVA097_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVA097_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVA097_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVA097_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVA097_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVA097_SET_PROVOKING_VERTEX 0x1684 +#define NVA097_SET_PROVOKING_VERTEX_V 0:0 +#define NVA097_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVA097_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVA097_SET_TWO_SIDED_LIGHT 0x1688 +#define NVA097_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVA097_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_POLYGON_STIPPLE 0x168c +#define NVA097_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVA097_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_SHADER_CONTROL 0x1690 +#define NVA097_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVA097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVA097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVA097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVA097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVA097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVA097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVA097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVA097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVA097_LAUNCH_VERTEX 0x169c +#define NVA097_LAUNCH_VERTEX_V 0:0 + +#define NVA097_CHECK_CLASS_VERSION 0x16a0 +#define NVA097_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVA097_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA097_SET_SPH_VERSION 0x16a4 +#define NVA097_SET_SPH_VERSION_CURRENT 15:0 +#define NVA097_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA097_CHECK_SPH_VERSION 0x16a8 +#define NVA097_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVA097_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVA097_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVA097_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVA097_SET_AAM_VERSION 0x1790 +#define NVA097_SET_AAM_VERSION_CURRENT 15:0 +#define NVA097_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA097_CHECK_AAM_VERSION 0x1794 +#define NVA097_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVA097_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA097_SET_ZT_LAYER 0x179c +#define NVA097_SET_ZT_LAYER_OFFSET 15:0 + +#define NVA097_SET_VAB_MEMORY_AREA_A 0x17bc +#define NVA097_SET_VAB_MEMORY_AREA_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_VAB_MEMORY_AREA_B 0x17c0 +#define NVA097_SET_VAB_MEMORY_AREA_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_VAB_MEMORY_AREA_C 0x17c4 +#define NVA097_SET_VAB_MEMORY_AREA_C_SIZE 1:0 +#define NVA097_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_64K 0x00000001 +#define NVA097_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_128K 0x00000002 +#define NVA097_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_256K 0x00000003 + +#define NVA097_SET_INDEX_BUFFER_A 0x17c8 +#define NVA097_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVA097_SET_INDEX_BUFFER_B 0x17cc +#define NVA097_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVA097_SET_INDEX_BUFFER_C 0x17d0 +#define NVA097_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVA097_SET_INDEX_BUFFER_D 0x17d4 +#define NVA097_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVA097_SET_INDEX_BUFFER_E 0x17d8 +#define NVA097_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVA097_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVA097_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVA097_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVA097_SET_INDEX_BUFFER_F 0x17dc +#define NVA097_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVA097_DRAW_INDEX_BUFFER 0x17e0 +#define NVA097_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVA097_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVA097_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVA097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVA097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVA097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVA097_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVA097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVA097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVA097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVA097_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVA097_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVA097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVA097_OGL_SET_CULL 0x1918 +#define NVA097_OGL_SET_CULL_ENABLE 0:0 +#define NVA097_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVA097_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVA097_OGL_SET_FRONT_FACE 0x191c +#define NVA097_OGL_SET_FRONT_FACE_V 31:0 +#define NVA097_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVA097_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVA097_OGL_SET_CULL_FACE 0x1920 +#define NVA097_OGL_SET_CULL_FACE_V 31:0 +#define NVA097_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVA097_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVA097_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVA097_SET_VIEWPORT_PIXEL 0x1924 +#define NVA097_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVA097_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVA097_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVA097_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVA097_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVA097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVA097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVA097_INVALIDATE_CONSTANT_BUFFER_CACHE 0x1930 +#define NVA097_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2 0:0 +#define NVA097_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_FALSE 0x00000000 +#define NVA097_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_TRUE 0x00000001 + +#define NVA097_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVA097_SET_USER_CLIP_OP 0x1940 +#define NVA097_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVA097_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVA097_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVA097_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVA097_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVA097_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVA097_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVA097_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVA097_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVA097_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVA097_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVA097_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVA097_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVA097_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVA097_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVA097_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVA097_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVA097_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVA097_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVA097_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVA097_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVA097_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVA097_INVALIDATE_ZCULL 0x1958 +#define NVA097_INVALIDATE_ZCULL_V 31:0 +#define NVA097_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVA097_SET_ZCULL 0x1968 +#define NVA097_SET_ZCULL_Z_ENABLE 0:0 +#define NVA097_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVA097_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_ZCULL_BOUNDS 0x196c +#define NVA097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVA097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVA097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVA097_ZCULL_SYNC 0x1978 +#define NVA097_ZCULL_SYNC_V 31:0 + +#define NVA097_SET_CLIP_ID_TEST 0x197c +#define NVA097_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVA097_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVA097_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVA097_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVA097_SET_CLIP_ID 0x1984 +#define NVA097_SET_CLIP_ID_V 31:0 + +#define NVA097_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVA097_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVA097_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVA097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVA097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVA097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVA097_SET_LOGIC_OP 0x19c4 +#define NVA097_SET_LOGIC_OP_ENABLE 0:0 +#define NVA097_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVA097_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_LOGIC_OP_FUNC 0x19c8 +#define NVA097_SET_LOGIC_OP_FUNC_V 31:0 +#define NVA097_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVA097_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVA097_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVA097_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVA097_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVA097_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVA097_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVA097_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVA097_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVA097_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVA097_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVA097_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVA097_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVA097_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVA097_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVA097_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVA097_SET_Z_COMPRESSION 0x19cc +#define NVA097_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVA097_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVA097_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVA097_CLEAR_SURFACE 0x19d0 +#define NVA097_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVA097_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVA097_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVA097_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVA097_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVA097_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVA097_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVA097_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVA097_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVA097_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVA097_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVA097_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVA097_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVA097_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVA097_SET_CT_WRITE_R_ENABLE 0:0 +#define NVA097_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVA097_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVA097_SET_CT_WRITE_G_ENABLE 4:4 +#define NVA097_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVA097_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVA097_SET_CT_WRITE_B_ENABLE 8:8 +#define NVA097_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVA097_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVA097_SET_CT_WRITE_A_ENABLE 12:12 +#define NVA097_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVA097_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVA097_PIPE_NOP 0x1a2c +#define NVA097_PIPE_NOP_V 31:0 + +#define NVA097_SET_SPARE00 0x1a30 +#define NVA097_SET_SPARE00_V 31:0 + +#define NVA097_SET_SPARE01 0x1a34 +#define NVA097_SET_SPARE01_V 31:0 + +#define NVA097_SET_SPARE02 0x1a38 +#define NVA097_SET_SPARE02_V 31:0 + +#define NVA097_SET_SPARE03 0x1a3c +#define NVA097_SET_SPARE03_V 31:0 + +#define NVA097_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVA097_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVA097_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVA097_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA097_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVA097_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVA097_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVA097_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVA097_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVA097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVA097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVA097_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVA097_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVA097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVA097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVA097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVA097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVA097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVA097_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVA097_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVA097_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVA097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVA097_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVA097_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVA097_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVA097_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVA097_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVA097_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVA097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVA097_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVA097_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVA097_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVA097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVA097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVA097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVA097_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVA097_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVA097_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVA097_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVA097_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVA097_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVA097_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVA097_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVA097_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVA097_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVA097_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVA097_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVA097_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVA097_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVA097_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVA097_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVA097_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVA097_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVA097_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NVA097_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NVA097_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVA097_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVA097_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVA097_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NVA097_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVA097_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVA097_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NVA097_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVA097_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NVA097_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NVA097_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVA097_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVA097_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVA097_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVA097_SET_FALCON00 0x2300 +#define NVA097_SET_FALCON00_V 31:0 + +#define NVA097_SET_FALCON01 0x2304 +#define NVA097_SET_FALCON01_V 31:0 + +#define NVA097_SET_FALCON02 0x2308 +#define NVA097_SET_FALCON02_V 31:0 + +#define NVA097_SET_FALCON03 0x230c +#define NVA097_SET_FALCON03_V 31:0 + +#define NVA097_SET_FALCON04 0x2310 +#define NVA097_SET_FALCON04_V 31:0 + +#define NVA097_SET_FALCON05 0x2314 +#define NVA097_SET_FALCON05_V 31:0 + +#define NVA097_SET_FALCON06 0x2318 +#define NVA097_SET_FALCON06_V 31:0 + +#define NVA097_SET_FALCON07 0x231c +#define NVA097_SET_FALCON07_V 31:0 + +#define NVA097_SET_FALCON08 0x2320 +#define NVA097_SET_FALCON08_V 31:0 + +#define NVA097_SET_FALCON09 0x2324 +#define NVA097_SET_FALCON09_V 31:0 + +#define NVA097_SET_FALCON10 0x2328 +#define NVA097_SET_FALCON10_V 31:0 + +#define NVA097_SET_FALCON11 0x232c +#define NVA097_SET_FALCON11_V 31:0 + +#define NVA097_SET_FALCON12 0x2330 +#define NVA097_SET_FALCON12_V 31:0 + +#define NVA097_SET_FALCON13 0x2334 +#define NVA097_SET_FALCON13_V 31:0 + +#define NVA097_SET_FALCON14 0x2338 +#define NVA097_SET_FALCON14_V 31:0 + +#define NVA097_SET_FALCON15 0x233c +#define NVA097_SET_FALCON15_V 31:0 + +#define NVA097_SET_FALCON16 0x2340 +#define NVA097_SET_FALCON16_V 31:0 + +#define NVA097_SET_FALCON17 0x2344 +#define NVA097_SET_FALCON17_V 31:0 + +#define NVA097_SET_FALCON18 0x2348 +#define NVA097_SET_FALCON18_V 31:0 + +#define NVA097_SET_FALCON19 0x234c +#define NVA097_SET_FALCON19_V 31:0 + +#define NVA097_SET_FALCON20 0x2350 +#define NVA097_SET_FALCON20_V 31:0 + +#define NVA097_SET_FALCON21 0x2354 +#define NVA097_SET_FALCON21_V 31:0 + +#define NVA097_SET_FALCON22 0x2358 +#define NVA097_SET_FALCON22_V 31:0 + +#define NVA097_SET_FALCON23 0x235c +#define NVA097_SET_FALCON23_V 31:0 + +#define NVA097_SET_FALCON24 0x2360 +#define NVA097_SET_FALCON24_V 31:0 + +#define NVA097_SET_FALCON25 0x2364 +#define NVA097_SET_FALCON25_V 31:0 + +#define NVA097_SET_FALCON26 0x2368 +#define NVA097_SET_FALCON26_V 31:0 + +#define NVA097_SET_FALCON27 0x236c +#define NVA097_SET_FALCON27_V 31:0 + +#define NVA097_SET_FALCON28 0x2370 +#define NVA097_SET_FALCON28_V 31:0 + +#define NVA097_SET_FALCON29 0x2374 +#define NVA097_SET_FALCON29_V 31:0 + +#define NVA097_SET_FALCON30 0x2378 +#define NVA097_SET_FALCON30_V 31:0 + +#define NVA097_SET_FALCON31 0x237c +#define NVA097_SET_FALCON31_V 31:0 + +#define NVA097_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVA097_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVA097_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVA097_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVA097_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVA097_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVA097_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVA097_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVA097_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVA097_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVA097_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVA097_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVA097_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVA097_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVA097_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVA097_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVA097_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVA097_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVA097_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVA097_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVA097_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA097_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA097_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVA097_SET_COLOR_CLAMP 0x2600 +#define NVA097_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVA097_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVA097_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVA097_NOOP_X_X_X_SET_VALVE 0x2604 +#define NVA097_NOOP_X_X_X_SET_VALVE_HIGHER_PRIORITY 0:0 +#define NVA097_NOOP_X_X_X_SET_VALVE_HIGHER_PRIORITY_COMPUTE 0x00000000 +#define NVA097_NOOP_X_X_X_SET_VALVE_HIGHER_PRIORITY_GRAPHICS 0x00000001 + +#define NVA097_SET_BINDLESS_TEXTURE 0x2608 +#define NVA097_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVA097_SET_TRAP_HANDLER 0x260c +#define NVA097_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVA097_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVA097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVA097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVA097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVA097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVA097_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVA097_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVA097_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVA097_CALL_MME_MACRO_V 31:0 + +#define NVA097_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVA097_CALL_MME_DATA_V 31:0 + +#endif /* _cl_kepler_a_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cla0b0.h b/userspace/sdks/nv570/nvidia/inc/class/cla0b0.h new file mode 100644 index 0000000..ef4faa8 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cla0b0.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "nvtypes.h" + +#ifndef _cla0b0_h_ +#define _cla0b0_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVA0B0_VIDEO_DECODER (0x0000A0B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cla0b0_h diff --git a/userspace/sdks/nv570/nvidia/inc/class/cla0b5.h b/userspace/sdks/nv570/nvidia/inc/class/cla0b5.h new file mode 100644 index 0000000..92076c6 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cla0b5.h @@ -0,0 +1,262 @@ +/******************************************************************************* + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _cla0b5_h_ +#define _cla0b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define KEPLER_DMA_COPY_A (0x0000A0B5) + +#define NVA0B5_NOP (0x00000100) +#define NVA0B5_NOP_PARAMETER 31:0 +#define NVA0B5_PM_TRIGGER (0x00000140) +#define NVA0B5_PM_TRIGGER_V 31:0 +#define NVA0B5_SET_SEMAPHORE_A (0x00000240) +#define NVA0B5_SET_SEMAPHORE_A_UPPER 7:0 +#define NVA0B5_SET_SEMAPHORE_B (0x00000244) +#define NVA0B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVA0B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVA0B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVA0B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVA0B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVA0B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVA0B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVA0B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVA0B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVA0B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVA0B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVA0B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVA0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVA0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVA0B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVA0B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVA0B5_SET_DST_PHYS_MODE (0x00000264) +#define NVA0B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVA0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVA0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVA0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVA0B5_LAUNCH_DMA (0x00000300) +#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVA0B5_LAUNCH_DMA_BYPASS_L2 11:11 +#define NVA0B5_LAUNCH_DMA_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVA0B5_LAUNCH_DMA_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVA0B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVA0B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVA0B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVA0B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVA0B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVA0B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN (0x0000000B) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX (0x0000000C) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMUL (0x0000000D) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMUL (0x0000000E) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVA0B5_OFFSET_IN_UPPER (0x00000400) +#define NVA0B5_OFFSET_IN_UPPER_UPPER 7:0 +#define NVA0B5_OFFSET_IN_LOWER (0x00000404) +#define NVA0B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVA0B5_OFFSET_OUT_UPPER (0x00000408) +#define NVA0B5_OFFSET_OUT_UPPER_UPPER 7:0 +#define NVA0B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVA0B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVA0B5_PITCH_IN (0x00000410) +#define NVA0B5_PITCH_IN_VALUE 31:0 +#define NVA0B5_PITCH_OUT (0x00000414) +#define NVA0B5_PITCH_OUT_VALUE 31:0 +#define NVA0B5_LINE_LENGTH_IN (0x00000418) +#define NVA0B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVA0B5_LINE_COUNT (0x0000041C) +#define NVA0B5_LINE_COUNT_VALUE 31:0 +#define NVA0B5_SET_REMAP_CONST_A (0x00000700) +#define NVA0B5_SET_REMAP_CONST_A_V 31:0 +#define NVA0B5_SET_REMAP_CONST_B (0x00000704) +#define NVA0B5_SET_REMAP_CONST_B_V 31:0 +#define NVA0B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVA0B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVA0B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVA0B5_SET_DST_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) +#define NVA0B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVA0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVA0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) +#define NVA0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVA0B5_SET_DST_WIDTH (0x00000710) +#define NVA0B5_SET_DST_WIDTH_V 31:0 +#define NVA0B5_SET_DST_HEIGHT (0x00000714) +#define NVA0B5_SET_DST_HEIGHT_V 31:0 +#define NVA0B5_SET_DST_DEPTH (0x00000718) +#define NVA0B5_SET_DST_DEPTH_V 31:0 +#define NVA0B5_SET_DST_LAYER (0x0000071C) +#define NVA0B5_SET_DST_LAYER_V 31:0 +#define NVA0B5_SET_DST_ORIGIN (0x00000720) +#define NVA0B5_SET_DST_ORIGIN_X 15:0 +#define NVA0B5_SET_DST_ORIGIN_Y 31:16 +#define NVA0B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVA0B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVA0B5_SET_SRC_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) +#define NVA0B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVA0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVA0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) +#define NVA0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVA0B5_SET_SRC_WIDTH (0x0000072C) +#define NVA0B5_SET_SRC_WIDTH_V 31:0 +#define NVA0B5_SET_SRC_HEIGHT (0x00000730) +#define NVA0B5_SET_SRC_HEIGHT_V 31:0 +#define NVA0B5_SET_SRC_DEPTH (0x00000734) +#define NVA0B5_SET_SRC_DEPTH_V 31:0 +#define NVA0B5_SET_SRC_LAYER (0x00000738) +#define NVA0B5_SET_SRC_LAYER_V 31:0 +#define NVA0B5_SET_SRC_ORIGIN (0x0000073C) +#define NVA0B5_SET_SRC_ORIGIN_X 15:0 +#define NVA0B5_SET_SRC_ORIGIN_Y 31:16 +#define NVA0B5_PM_TRIGGER_END (0x00001114) +#define NVA0B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cla0b5_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/cla0c0.h b/userspace/sdks/nv570/nvidia/inc/class/cla0c0.h new file mode 100644 index 0000000..bc73e40 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cla0c0.h @@ -0,0 +1,646 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_kepler_compute_a_h_ +#define _cl_kepler_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl kepler_compute_a */ + +#include "nvtypes.h" + +#define KEPLER_COMPUTE_A 0xA0C0 + +#define NVA0C0_SET_OBJECT 0x0000 +#define NVA0C0_SET_OBJECT_CLASS_ID 15:0 +#define NVA0C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVA0C0_NO_OPERATION 0x0100 +#define NVA0C0_NO_OPERATION_V 31:0 + +#define NVA0C0_SET_NOTIFY_A 0x0104 +#define NVA0C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVA0C0_SET_NOTIFY_B 0x0108 +#define NVA0C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVA0C0_NOTIFY 0x010c +#define NVA0C0_NOTIFY_TYPE 31:0 +#define NVA0C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVA0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVA0C0_WAIT_FOR_IDLE 0x0110 +#define NVA0C0_WAIT_FOR_IDLE_V 31:0 + +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA0C0_SEND_GO_IDLE 0x013c +#define NVA0C0_SEND_GO_IDLE_V 31:0 + +#define NVA0C0_PM_TRIGGER 0x0140 +#define NVA0C0_PM_TRIGGER_V 31:0 + +#define NVA0C0_PM_TRIGGER_WFI 0x0144 +#define NVA0C0_PM_TRIGGER_WFI_V 31:0 + +#define NVA0C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVA0C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVA0C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVA0C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVA0C0_LINE_LENGTH_IN 0x0180 +#define NVA0C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVA0C0_LINE_COUNT 0x0184 +#define NVA0C0_LINE_COUNT_VALUE 31:0 + +#define NVA0C0_OFFSET_OUT_UPPER 0x0188 +#define NVA0C0_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVA0C0_OFFSET_OUT 0x018c +#define NVA0C0_OFFSET_OUT_VALUE 31:0 + +#define NVA0C0_PITCH_OUT 0x0190 +#define NVA0C0_PITCH_OUT_VALUE 31:0 + +#define NVA0C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVA0C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVA0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVA0C0_SET_DST_WIDTH 0x0198 +#define NVA0C0_SET_DST_WIDTH_V 31:0 + +#define NVA0C0_SET_DST_HEIGHT 0x019c +#define NVA0C0_SET_DST_HEIGHT_V 31:0 + +#define NVA0C0_SET_DST_DEPTH 0x01a0 +#define NVA0C0_SET_DST_DEPTH_V 31:0 + +#define NVA0C0_SET_DST_LAYER 0x01a4 +#define NVA0C0_SET_DST_LAYER_V 31:0 + +#define NVA0C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVA0C0_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVA0C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVA0C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVA0C0_LAUNCH_DMA 0x01b0 +#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVA0C0_LOAD_INLINE_DATA 0x01b4 +#define NVA0C0_LOAD_INLINE_DATA_V 31:0 + +#define NVA0C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVA0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVA0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVA0C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA0C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVA0C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVA0C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVA0C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVA0C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVA0C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVA0C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVA0C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVA0C0_PERFMON_TRANSFER 0x0210 +#define NVA0C0_PERFMON_TRANSFER_V 31:0 + +#define NVA0C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVA0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA0C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVA0C0_SET_CWD_CONTROL 0x0240 +#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVA0C0_SET_CWD_REF_COUNTER 0x0248 +#define NVA0C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVA0C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0 + +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVA0C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVA0C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVA0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA0C0_SET_QMD_VERSION 0x0288 +#define NVA0C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVA0C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA0C0_CHECK_QMD_VERSION 0x0290 +#define NVA0C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVA0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA0C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVA0C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVA0C0_SEND_PCAS_A 0x02b4 +#define NVA0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVA0C0_SEND_PCAS_B 0x02b8 +#define NVA0C0_SEND_PCAS_B_FROM 23:0 +#define NVA0C0_SEND_PCAS_B_DELTA 31:24 + +#define NVA0C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVA0C0_SET_SPA_VERSION 0x0310 +#define NVA0C0_SET_SPA_VERSION_MINOR 7:0 +#define NVA0C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVA0C0_SET_FALCON00 0x0500 +#define NVA0C0_SET_FALCON00_V 31:0 + +#define NVA0C0_SET_FALCON01 0x0504 +#define NVA0C0_SET_FALCON01_V 31:0 + +#define NVA0C0_SET_FALCON02 0x0508 +#define NVA0C0_SET_FALCON02_V 31:0 + +#define NVA0C0_SET_FALCON03 0x050c +#define NVA0C0_SET_FALCON03_V 31:0 + +#define NVA0C0_SET_FALCON04 0x0510 +#define NVA0C0_SET_FALCON04_V 31:0 + +#define NVA0C0_SET_FALCON05 0x0514 +#define NVA0C0_SET_FALCON05_V 31:0 + +#define NVA0C0_SET_FALCON06 0x0518 +#define NVA0C0_SET_FALCON06_V 31:0 + +#define NVA0C0_SET_FALCON07 0x051c +#define NVA0C0_SET_FALCON07_V 31:0 + +#define NVA0C0_SET_FALCON08 0x0520 +#define NVA0C0_SET_FALCON08_V 31:0 + +#define NVA0C0_SET_FALCON09 0x0524 +#define NVA0C0_SET_FALCON09_V 31:0 + +#define NVA0C0_SET_FALCON10 0x0528 +#define NVA0C0_SET_FALCON10_V 31:0 + +#define NVA0C0_SET_FALCON11 0x052c +#define NVA0C0_SET_FALCON11_V 31:0 + +#define NVA0C0_SET_FALCON12 0x0530 +#define NVA0C0_SET_FALCON12_V 31:0 + +#define NVA0C0_SET_FALCON13 0x0534 +#define NVA0C0_SET_FALCON13_V 31:0 + +#define NVA0C0_SET_FALCON14 0x0538 +#define NVA0C0_SET_FALCON14_V 31:0 + +#define NVA0C0_SET_FALCON15 0x053c +#define NVA0C0_SET_FALCON15_V 31:0 + +#define NVA0C0_SET_FALCON16 0x0540 +#define NVA0C0_SET_FALCON16_V 31:0 + +#define NVA0C0_SET_FALCON17 0x0544 +#define NVA0C0_SET_FALCON17_V 31:0 + +#define NVA0C0_SET_FALCON18 0x0548 +#define NVA0C0_SET_FALCON18_V 31:0 + +#define NVA0C0_SET_FALCON19 0x054c +#define NVA0C0_SET_FALCON19_V 31:0 + +#define NVA0C0_SET_FALCON20 0x0550 +#define NVA0C0_SET_FALCON20_V 31:0 + +#define NVA0C0_SET_FALCON21 0x0554 +#define NVA0C0_SET_FALCON21_V 31:0 + +#define NVA0C0_SET_FALCON22 0x0558 +#define NVA0C0_SET_FALCON22_V 31:0 + +#define NVA0C0_SET_FALCON23 0x055c +#define NVA0C0_SET_FALCON23_V 31:0 + +#define NVA0C0_SET_FALCON24 0x0560 +#define NVA0C0_SET_FALCON24_V 31:0 + +#define NVA0C0_SET_FALCON25 0x0564 +#define NVA0C0_SET_FALCON25_V 31:0 + +#define NVA0C0_SET_FALCON26 0x0568 +#define NVA0C0_SET_FALCON26_V 31:0 + +#define NVA0C0_SET_FALCON27 0x056c +#define NVA0C0_SET_FALCON27_V 31:0 + +#define NVA0C0_SET_FALCON28 0x0570 +#define NVA0C0_SET_FALCON28_V 31:0 + +#define NVA0C0_SET_FALCON29 0x0574 +#define NVA0C0_SET_FALCON29_V 31:0 + +#define NVA0C0_SET_FALCON30 0x0578 +#define NVA0C0_SET_FALCON30_V 31:0 + +#define NVA0C0_SET_FALCON31 0x057c +#define NVA0C0_SET_FALCON31_V 31:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVA0C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVA0C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVA0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVA0C0_SET_SPARE_NOOP12 0x0f44 +#define NVA0C0_SET_SPARE_NOOP12_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP13 0x0f48 +#define NVA0C0_SET_SPARE_NOOP13_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP14 0x0f4c +#define NVA0C0_SET_SPARE_NOOP14_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP15 0x0f50 +#define NVA0C0_SET_SPARE_NOOP15_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP00 0x1040 +#define NVA0C0_SET_SPARE_NOOP00_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP01 0x1044 +#define NVA0C0_SET_SPARE_NOOP01_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP02 0x1048 +#define NVA0C0_SET_SPARE_NOOP02_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP03 0x104c +#define NVA0C0_SET_SPARE_NOOP03_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP04 0x1050 +#define NVA0C0_SET_SPARE_NOOP04_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP05 0x1054 +#define NVA0C0_SET_SPARE_NOOP05_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP06 0x1058 +#define NVA0C0_SET_SPARE_NOOP06_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP07 0x105c +#define NVA0C0_SET_SPARE_NOOP07_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP08 0x1060 +#define NVA0C0_SET_SPARE_NOOP08_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP09 0x1064 +#define NVA0C0_SET_SPARE_NOOP09_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP10 0x1068 +#define NVA0C0_SET_SPARE_NOOP10_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP11 0x106c +#define NVA0C0_SET_SPARE_NOOP11_V 31:0 + +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVA0C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVA0C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVA0C0_SET_RENDER_ENABLE_A 0x1550 +#define NVA0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_RENDER_ENABLE_B 0x1554 +#define NVA0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_RENDER_ENABLE_C 0x1558 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA0C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVA0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVA0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVA0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVA0C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVA0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVA0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVA0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVA0C0_SET_PROGRAM_REGION_A 0x1608 +#define NVA0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVA0C0_SET_PROGRAM_REGION_B 0x160c +#define NVA0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVA0C0_SET_SHADER_CONTROL 0x1690 +#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 + +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVA0C0_PIPE_NOP 0x1a2c +#define NVA0C0_PIPE_NOP_V 31:0 + +#define NVA0C0_SET_SPARE00 0x1a30 +#define NVA0C0_SET_SPARE00_V 31:0 + +#define NVA0C0_SET_SPARE01 0x1a34 +#define NVA0C0_SET_SPARE01_V 31:0 + +#define NVA0C0_SET_SPARE02 0x1a38 +#define NVA0C0_SET_SPARE02_V 31:0 + +#define NVA0C0_SET_SPARE03 0x1a3c +#define NVA0C0_SET_SPARE03_V 31:0 + +#define NVA0C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVA0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVA0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVA0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA0C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVA0C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVA0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVA0C0_SET_TRAP_HANDLER 0x260c +#define NVA0C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVA0C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVA0C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_kepler_compute_a_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cla0c0qmd.h b/userspace/sdks/nv570/nvidia/inc/class/cla0c0qmd.h new file mode 100644 index 0000000..b04ce5b --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cla0c0qmd.h @@ -0,0 +1,658 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __CLA0C0QMD_H__ +#define __CLA0C0QMD_H__ + +/* +** Queue Meta Data, Version 00_06 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_A MW(30:0) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_B MW(31:31) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_C MW(62:32) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_D MW(63:63) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_E MW(94:64) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_F MW(95:95) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_G MW(126:96) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_H MW(127:127) +#define NVA0C0_QMDV00_06_QMD_RESERVED_A_A MW(159:128) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_I MW(191:160) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_J MW(196:192) +#define NVA0C0_QMDV00_06_QMD_RESERVED_A MW(199:197) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K MW(200:200) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L MW(201:201) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_B MW(207:204) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_M MW(222:208) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N MW(223:223) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_O MW(248:224) +#define NVA0C0_QMDV00_06_QMD_RESERVED_C MW(249:249) +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_PROGRAM_OFFSET MW(287:256) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_P MW(319:288) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_Q MW(327:320) +#define NVA0C0_QMDV00_06_QMD_RESERVED_D MW(335:328) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_R MW(351:336) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_S MW(357:352) +#define NVA0C0_QMDV00_06_QMD_RESERVED_E MW(365:358) +#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE MW(369:368) +#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T MW(370:370) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U MW(371:371) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_THROTTLED MW(372:372) +#define NVA0C0_QMDV00_06_THROTTLED_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_THROTTLED_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_E2_A MW(376:376) +#define NVA0C0_QMDV00_06_QMD_RESERVED_E2_B MW(377:377) +#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVA0C0_QMDV00_06_SAMPLER_INDEX MW(382:382) +#define NVA0C0_QMDV00_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVA0C0_QMDV00_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_E3_A MW(383:383) +#define NVA0C0_QMDV00_06_CTA_RASTER_WIDTH MW(415:384) +#define NVA0C0_QMDV00_06_CTA_RASTER_HEIGHT MW(431:416) +#define NVA0C0_QMDV00_06_CTA_RASTER_DEPTH MW(447:432) +#define NVA0C0_QMDV00_06_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVA0C0_QMDV00_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVA0C0_QMDV00_06_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_V MW(535:512) +#define NVA0C0_QMDV00_06_QMD_RESERVED_F MW(542:536) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W MW(543:543) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_SHARED_MEMORY_SIZE MW(561:544) +#define NVA0C0_QMDV00_06_QMD_RESERVED_G MW(575:562) +#define NVA0C0_QMDV00_06_QMD_VERSION MW(579:576) +#define NVA0C0_QMDV00_06_QMD_MAJOR_VERSION MW(583:580) +#define NVA0C0_QMDV00_06_QMD_RESERVED_H MW(591:584) +#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_I MW(668:648) +#define NVA0C0_QMDV00_06_L1_CONFIGURATION MW(671:669) +#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_X MW(703:672) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_Y MW(735:704) +#define NVA0C0_QMDV00_06_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVA0C0_QMDV00_06_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVA0C0_QMDV00_06_QMD_RESERVED_J MW(783:776) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP MW(790:788) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV00_06_QMD_RESERVED_K MW(791:791) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE0_PAYLOAD MW(831:800) +#define NVA0C0_QMDV00_06_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVA0C0_QMDV00_06_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVA0C0_QMDV00_06_QMD_RESERVED_L MW(879:872) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP MW(886:884) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV00_06_QMD_RESERVED_M MW(887:887) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE1_PAYLOAD MW(927:896) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVA0C0_QMDV00_06_QMD_RESERVED_N MW(1466:1464) +#define NVA0C0_QMDV00_06_BARRIER_COUNT MW(1471:1467) +#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVA0C0_QMDV00_06_REGISTER_COUNT MW(1503:1496) +#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVA0C0_QMDV00_06_SASS_VERSION MW(1535:1528) +#define NVA0C0_QMDV00_06_QMD_SPARE_A MW(1567:1536) +#define NVA0C0_QMDV00_06_QMD_SPARE_B MW(1599:1568) +#define NVA0C0_QMDV00_06_QMD_SPARE_C MW(1631:1600) +#define NVA0C0_QMDV00_06_QMD_SPARE_D MW(1663:1632) +#define NVA0C0_QMDV00_06_QMD_SPARE_E MW(1695:1664) +#define NVA0C0_QMDV00_06_QMD_SPARE_F MW(1727:1696) +#define NVA0C0_QMDV00_06_QMD_SPARE_G MW(1759:1728) +#define NVA0C0_QMDV00_06_QMD_SPARE_H MW(1791:1760) +#define NVA0C0_QMDV00_06_QMD_SPARE_I MW(1823:1792) +#define NVA0C0_QMDV00_06_QMD_SPARE_J MW(1855:1824) +#define NVA0C0_QMDV00_06_QMD_SPARE_K MW(1887:1856) +#define NVA0C0_QMDV00_06_QMD_SPARE_L MW(1919:1888) +#define NVA0C0_QMDV00_06_QMD_SPARE_M MW(1951:1920) +#define NVA0C0_QMDV00_06_QMD_SPARE_N MW(1983:1952) +#define NVA0C0_QMDV00_06_DEBUG_ID_UPPER MW(2015:1984) +#define NVA0C0_QMDV00_06_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 01_06 + */ + +#define NVA0C0_QMDV01_06_OUTER_PUT MW(30:0) +#define NVA0C0_QMDV01_06_OUTER_OVERFLOW MW(31:31) +#define NVA0C0_QMDV01_06_OUTER_GET MW(62:32) +#define NVA0C0_QMDV01_06_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVA0C0_QMDV01_06_INNER_GET MW(94:64) +#define NVA0C0_QMDV01_06_INNER_OVERFLOW MW(95:95) +#define NVA0C0_QMDV01_06_INNER_PUT MW(126:96) +#define NVA0C0_QMDV01_06_INNER_STICKY_OVERFLOW MW(127:127) +#define NVA0C0_QMDV01_06_QMD_RESERVED_A_A MW(159:128) +#define NVA0C0_QMDV01_06_SCHEDULER_NEXT_QMD_POINTER MW(191:160) +#define NVA0C0_QMDV01_06_QMD_GROUP_ID MW(197:192) +#define NVA0C0_QMDV01_06_QMD_RESERVED_A MW(199:198) +#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE MW(200:200) +#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_QMD_RESERVED_B MW(207:205) +#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_ADDR MW(222:208) +#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID MW(223:223) +#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVA0C0_QMDV01_06_QMD_RESERVED_C MW(249:249) +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_PROGRAM_OFFSET MW(287:256) +#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVA0C0_QMDV01_06_QMD_RESERVED_D MW(335:328) +#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE MW(369:368) +#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_THROTTLED MW(372:372) +#define NVA0C0_QMDV01_06_THROTTLED_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_THROTTLED_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR MW(376:376) +#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVA0C0_QMDV01_06_SAMPLER_INDEX MW(382:382) +#define NVA0C0_QMDV01_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVA0C0_QMDV01_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVA0C0_QMDV01_06_CTA_RASTER_WIDTH MW(415:384) +#define NVA0C0_QMDV01_06_CTA_RASTER_HEIGHT MW(431:416) +#define NVA0C0_QMDV01_06_CTA_RASTER_DEPTH MW(447:432) +#define NVA0C0_QMDV01_06_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVA0C0_QMDV01_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVA0C0_QMDV01_06_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVA0C0_QMDV01_06_LAUNCH_QUOTA MW(535:512) +#define NVA0C0_QMDV01_06_QMD_RESERVED_F MW(542:536) +#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE MW(543:543) +#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_SHARED_MEMORY_SIZE MW(561:544) +#define NVA0C0_QMDV01_06_QMD_RESERVED_G MW(575:562) +#define NVA0C0_QMDV01_06_QMD_VERSION MW(579:576) +#define NVA0C0_QMDV01_06_QMD_MAJOR_VERSION MW(583:580) +#define NVA0C0_QMDV01_06_QMD_RESERVED_H MW(591:584) +#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_QMD_RESERVED_I MW(668:648) +#define NVA0C0_QMDV01_06_L1_CONFIGURATION MW(671:669) +#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVA0C0_QMDV01_06_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVA0C0_QMDV01_06_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVA0C0_QMDV01_06_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVA0C0_QMDV01_06_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVA0C0_QMDV01_06_QMD_RESERVED_J MW(783:776) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP MW(790:788) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV01_06_QMD_RESERVED_K MW(791:791) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE0_PAYLOAD MW(831:800) +#define NVA0C0_QMDV01_06_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVA0C0_QMDV01_06_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVA0C0_QMDV01_06_QMD_RESERVED_L MW(879:872) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP MW(886:884) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV01_06_QMD_RESERVED_M MW(887:887) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE1_PAYLOAD MW(927:896) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVA0C0_QMDV01_06_QMD_RESERVED_N MW(1466:1464) +#define NVA0C0_QMDV01_06_BARRIER_COUNT MW(1471:1467) +#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVA0C0_QMDV01_06_REGISTER_COUNT MW(1503:1496) +#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVA0C0_QMDV01_06_SASS_VERSION MW(1535:1528) +#define NVA0C0_QMDV01_06_HW_ONLY_INNER_GET MW(1566:1536) +#define NVA0C0_QMDV01_06_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVA0C0_QMDV01_06_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVA0C0_QMDV01_06_HW_ONLY_SCHEDULE_ON_PUT_UPDATE_ENABLE MW(1599:1599) +#define NVA0C0_QMDV01_06_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(1606:1600) +#define NVA0C0_QMDV01_06_QMD_RESERVED_Q MW(1609:1607) +#define NVA0C0_QMDV01_06_COALESCE_WAITING_PERIOD MW(1617:1610) +#define NVA0C0_QMDV01_06_QMD_RESERVED_R MW(1631:1618) +#define NVA0C0_QMDV01_06_QMD_SPARE_D MW(1663:1632) +#define NVA0C0_QMDV01_06_QMD_SPARE_E MW(1695:1664) +#define NVA0C0_QMDV01_06_QMD_SPARE_F MW(1727:1696) +#define NVA0C0_QMDV01_06_QMD_SPARE_G MW(1759:1728) +#define NVA0C0_QMDV01_06_QMD_SPARE_H MW(1791:1760) +#define NVA0C0_QMDV01_06_QMD_SPARE_I MW(1823:1792) +#define NVA0C0_QMDV01_06_QMD_SPARE_J MW(1855:1824) +#define NVA0C0_QMDV01_06_QMD_SPARE_K MW(1887:1856) +#define NVA0C0_QMDV01_06_QMD_SPARE_L MW(1919:1888) +#define NVA0C0_QMDV01_06_QMD_SPARE_M MW(1951:1920) +#define NVA0C0_QMDV01_06_QMD_SPARE_N MW(1983:1952) +#define NVA0C0_QMDV01_06_DEBUG_ID_UPPER MW(2015:1984) +#define NVA0C0_QMDV01_06_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 01_07 + */ + +#define NVA0C0_QMDV01_07_OUTER_PUT MW(30:0) +#define NVA0C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) +#define NVA0C0_QMDV01_07_OUTER_GET MW(62:32) +#define NVA0C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVA0C0_QMDV01_07_INNER_GET MW(94:64) +#define NVA0C0_QMDV01_07_INNER_OVERFLOW MW(95:95) +#define NVA0C0_QMDV01_07_INNER_PUT MW(126:96) +#define NVA0C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) +#define NVA0C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) +#define NVA0C0_QMDV01_07_QMD_GROUP_ID MW(197:192) +#define NVA0C0_QMDV01_07_QMD_RESERVED_A MW(200:198) +#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_QMD_RESERVED_B MW(223:208) +#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVA0C0_QMDV01_07_QMD_RESERVED_C MW(249:249) +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) +#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVA0C0_QMDV01_07_QMD_RESERVED_D MW(335:328) +#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) +#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_THROTTLED MW(372:372) +#define NVA0C0_QMDV01_07_THROTTLED_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_THROTTLED_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) +#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVA0C0_QMDV01_07_SAMPLER_INDEX MW(382:382) +#define NVA0C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVA0C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVA0C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) +#define NVA0C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) +#define NVA0C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) +#define NVA0C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVA0C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVA0C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVA0C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVA0C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) +#define NVA0C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) +#define NVA0C0_QMDV01_07_QMD_RESERVED_G MW(575:562) +#define NVA0C0_QMDV01_07_QMD_VERSION MW(579:576) +#define NVA0C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) +#define NVA0C0_QMDV01_07_QMD_RESERVED_H MW(591:584) +#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_QMD_RESERVED_I MW(668:648) +#define NVA0C0_QMDV01_07_L1_CONFIGURATION MW(671:669) +#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVA0C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVA0C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVA0C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVA0C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVA0C0_QMDV01_07_QMD_RESERVED_J MW(783:776) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV01_07_QMD_RESERVED_K MW(791:791) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) +#define NVA0C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVA0C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVA0C0_QMDV01_07_QMD_RESERVED_L MW(879:872) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV01_07_QMD_RESERVED_M MW(887:887) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVA0C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) +#define NVA0C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) +#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVA0C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) +#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVA0C0_QMDV01_07_SASS_VERSION MW(1535:1528) +#define NVA0C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) +#define NVA0C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVA0C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVA0C0_QMDV01_07_QMD_RESERVED_P MW(1599:1599) +#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVA0C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) +#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVA0C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) +#define NVA0C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) +#define NVA0C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) +#define NVA0C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) +#define NVA0C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) +#define NVA0C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) +#define NVA0C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) +#define NVA0C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) +#define NVA0C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) +#define NVA0C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) +#define NVA0C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) +#define NVA0C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLA0C0QMD_H__ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cla140.h b/userspace/sdks/nv570/nvidia/inc/class/cla140.h new file mode 100644 index 0000000..08b8fc1 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cla140.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cla140_h_ +#define _cla140_h_ + +#define KEPLER_INLINE_TO_MEMORY_B 0xA140 + +#endif // _cla140_h_ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cla16f.h b/userspace/sdks/nv570/nvidia/inc/class/cla16f.h new file mode 100644 index 0000000..66e7594 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cla16f.h @@ -0,0 +1,254 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cla16f_h_ +#define _cla16f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class KEPLER_CHANNEL_GPFIFO */ +/* + * Documentation for KEPLER_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + */ +#define KEPLER_CHANNEL_GPFIFO_B (0x0000A16F) + +/* pio method data structure */ +typedef volatile struct _cla16f_tag0 { + NvV32 Reserved00[0x7c0]; +} NvA16FTypedef, KEPLER_ChannelGPFifoB; +#define NVA16F_TYPEDEF KEPLER_CHANNELChannelGPFifo +/* dma flow control data structure */ +typedef volatile struct _cla16f_tag1 { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} NvA16FControl, KeplerBControlGPFifo; +/* fields and values */ +#define NVA16F_NUMBER_OF_SUBCHANNELS (8) +#define NVA16F_SET_OBJECT (0x00000000) +#define NVA16F_SET_OBJECT_NVCLASS 15:0 +#define NVA16F_SET_OBJECT_ENGINE 20:16 +#define NVA16F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVA16F_ILLEGAL (0x00000004) +#define NVA16F_ILLEGAL_HANDLE 31:0 +#define NVA16F_NOP (0x00000008) +#define NVA16F_NOP_HANDLE 31:0 +#define NVA16F_SEMAPHOREA (0x00000010) +#define NVA16F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVA16F_SEMAPHOREB (0x00000014) +#define NVA16F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVA16F_SEMAPHOREC (0x00000018) +#define NVA16F_SEMAPHOREC_PAYLOAD 31:0 +#define NVA16F_SEMAPHORED (0x0000001C) +#define NVA16F_SEMAPHORED_OPERATION 4:0 +#define NVA16F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVA16F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVA16F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVA16F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVA16F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 +#define NVA16F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVA16F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVA16F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVA16F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVA16F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVA16F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVA16F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVA16F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVA16F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVA16F_SEMAPHORED_REDUCTION 30:27 +#define NVA16F_SEMAPHORED_REDUCTION_MIN 0x00000000 +#define NVA16F_SEMAPHORED_REDUCTION_MAX 0x00000001 +#define NVA16F_SEMAPHORED_REDUCTION_XOR 0x00000002 +#define NVA16F_SEMAPHORED_REDUCTION_AND 0x00000003 +#define NVA16F_SEMAPHORED_REDUCTION_OR 0x00000004 +#define NVA16F_SEMAPHORED_REDUCTION_ADD 0x00000005 +#define NVA16F_SEMAPHORED_REDUCTION_INC 0x00000006 +#define NVA16F_SEMAPHORED_REDUCTION_DEC 0x00000007 +#define NVA16F_SEMAPHORED_FORMAT 31:31 +#define NVA16F_SEMAPHORED_FORMAT_SIGNED 0x00000000 +#define NVA16F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 +#define NVA16F_NON_STALL_INTERRUPT (0x00000020) +#define NVA16F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVA16F_FB_FLUSH (0x00000024) +#define NVA16F_FB_FLUSH_HANDLE 31:0 +#define NVA16F_MEM_OP_A (0x00000028) +#define NVA16F_MEM_OP_A_OPERAND_LOW 31:2 +#define NVA16F_MEM_OP_A_TLB_INVALIDATE_ADDR 29:2 +#define NVA16F_MEM_OP_A_TLB_INVALIDATE_TARGET 31:30 +#define NVA16F_MEM_OP_A_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000 +#define NVA16F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002 +#define NVA16F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 +#define NVA16F_MEM_OP_B (0x0000002c) +#define NVA16F_MEM_OP_B_OPERAND_HIGH 7:0 +#define NVA16F_MEM_OP_B_OPERATION 31:27 +#define NVA16F_MEM_OP_B_OPERATION_SYSMEMBAR_FLUSH 0x00000005 +#define NVA16F_MEM_OP_B_OPERATION_SOFT_FLUSH 0x00000006 +#define NVA16F_MEM_OP_B_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVA16F_MEM_OP_B_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NVA16F_MEM_OP_B_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +#define NVA16F_MEM_OP_B_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVA16F_MEM_OP_B_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB 0:0 +#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ALL 0x00000001 +#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC 1:1 +#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVA16F_SET_REFERENCE (0x00000050) +#define NVA16F_SET_REFERENCE_COUNT 31:0 +#define NVA16F_WFI (0x00000078) +#define NVA16F_WFI_HANDLE 31:0 +#define NVA16F_CRC_CHECK (0x0000007c) +#define NVA16F_CRC_CHECK_VALUE 31:0 +#define NVA16F_YIELD (0x00000080) +#define NVA16F_YIELD_OP 1:0 +#define NVA16F_YIELD_OP_NOP 0x00000000 + + +/* GPFIFO entry format */ +#define NVA16F_GP_ENTRY__SIZE 8 +#define NVA16F_GP_ENTRY0_FETCH 0:0 +#define NVA16F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVA16F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVA16F_GP_ENTRY0_GET 31:2 +#define NVA16F_GP_ENTRY0_OPERAND 31:0 +#define NVA16F_GP_ENTRY1_GET_HI 7:0 +#define NVA16F_GP_ENTRY1_PRIV 8:8 +#define NVA16F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NVA16F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NVA16F_GP_ENTRY1_LEVEL 9:9 +#define NVA16F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVA16F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVA16F_GP_ENTRY1_LENGTH 30:10 +#define NVA16F_GP_ENTRY1_SYNC 31:31 +#define NVA16F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVA16F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVA16F_GP_ENTRY1_OPCODE 7:0 +#define NVA16F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVA16F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVA16F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVA16F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVA16F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVA16F_DMA_METHOD_ADDRESS 11:0 +#define NVA16F_DMA_SUBDEVICE_MASK 15:4 +#define NVA16F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVA16F_DMA_TERT_OP 17:16 +#define NVA16F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVA16F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVA16F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVA16F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVA16F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVA16F_DMA_METHOD_COUNT_OLD 28:18 +#define NVA16F_DMA_METHOD_COUNT 28:16 +#define NVA16F_DMA_IMMD_DATA 28:16 +#define NVA16F_DMA_SEC_OP 31:29 +#define NVA16F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVA16F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVA16F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVA16F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVA16F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVA16F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVA16F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVA16F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVA16F_DMA_INCR_ADDRESS 11:0 +#define NVA16F_DMA_INCR_SUBCHANNEL 15:13 +#define NVA16F_DMA_INCR_COUNT 28:16 +#define NVA16F_DMA_INCR_OPCODE 31:29 +#define NVA16F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVA16F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVA16F_DMA_NONINCR_ADDRESS 11:0 +#define NVA16F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVA16F_DMA_NONINCR_COUNT 28:16 +#define NVA16F_DMA_NONINCR_OPCODE 31:29 +#define NVA16F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVA16F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVA16F_DMA_ONEINCR_ADDRESS 11:0 +#define NVA16F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVA16F_DMA_ONEINCR_COUNT 28:16 +#define NVA16F_DMA_ONEINCR_OPCODE 31:29 +#define NVA16F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVA16F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVA16F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVA16F_DMA_IMMD_ADDRESS 11:0 +#define NVA16F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVA16F_DMA_IMMD_DATA 28:16 +#define NVA16F_DMA_IMMD_OPCODE 31:29 +#define NVA16F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVA16F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVA16F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA16F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVA16F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVA16F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA16F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVA16F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA16F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVA16F_DMA_ENDSEG_OPCODE 31:29 +#define NVA16F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVA16F_DMA_ADDRESS 12:2 +#define NVA16F_DMA_SUBCH 15:13 +#define NVA16F_DMA_OPCODE3 17:16 +#define NVA16F_DMA_OPCODE3_NONE (0x00000000) +#define NVA16F_DMA_COUNT 28:18 +#define NVA16F_DMA_OPCODE 31:29 +#define NVA16F_DMA_OPCODE_METHOD (0x00000000) +#define NVA16F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVA16F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cla16F_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cla16fsw.h b/userspace/sdks/nv570/nvidia/inc/class/cla16fsw.h new file mode 100644 index 0000000..cea256f --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cla16fsw.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cla16f_sw_h_ +#define _cla16f_sw_h_ + +#define NVA16F_NOTIFIERS_RC (0) +#define NVA16F_NOTIFIERS_REFCNT (1) +#define NVA16F_NOTIFIERS_NONSTALL (2) +#define NVA16F_NOTIFIERS_EVENTBUFFER (3) +#define NVA16F_NOTIFIERS_IDLECHANNEL (4) +#define NVA16F_NOTIFIERS_ENDCTX (5) +#define NVA16F_NOTIFIERS_SW (6) +#define NVA16F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVA16F_NOTIFIERS_MAXCOUNT (8) + +/* NvNotification[] fields and values */ +#define NVA16F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVA16F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _cla16f_sw_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cla197.h b/userspace/sdks/nv570/nvidia/inc/class/cla197.h new file mode 100644 index 0000000..deae603 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cla197.h @@ -0,0 +1,3826 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_kepler_b_h_ +#define _cl_kepler_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl kepler_b */ + +#include "nvtypes.h" + +#define KEPLER_B 0xA197 + +#define NVA197_SET_OBJECT 0x0000 +#define NVA197_SET_OBJECT_CLASS_ID 15:0 +#define NVA197_SET_OBJECT_ENGINE_ID 20:16 + +#define NVA197_NO_OPERATION 0x0100 +#define NVA197_NO_OPERATION_V 31:0 + +#define NVA197_SET_NOTIFY_A 0x0104 +#define NVA197_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVA197_SET_NOTIFY_B 0x0108 +#define NVA197_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVA197_NOTIFY 0x010c +#define NVA197_NOTIFY_TYPE 31:0 +#define NVA197_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVA197_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVA197_WAIT_FOR_IDLE 0x0110 +#define NVA197_WAIT_FOR_IDLE_V 31:0 + +#define NVA197_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVA197_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVA197_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVA197_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVA197_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVA197_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVA197_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVA197_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVA197_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVA197_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVA197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVA197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVA197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVA197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVA197_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVA197_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVA197_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVA197_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVA197_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA197_SEND_GO_IDLE 0x013c +#define NVA197_SEND_GO_IDLE_V 31:0 + +#define NVA197_PM_TRIGGER 0x0140 +#define NVA197_PM_TRIGGER_V 31:0 + +#define NVA197_PM_TRIGGER_WFI 0x0144 +#define NVA197_PM_TRIGGER_WFI_V 31:0 + +#define NVA197_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVA197_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVA197_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVA197_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVA197_LINE_LENGTH_IN 0x0180 +#define NVA197_LINE_LENGTH_IN_VALUE 31:0 + +#define NVA197_LINE_COUNT 0x0184 +#define NVA197_LINE_COUNT_VALUE 31:0 + +#define NVA197_OFFSET_OUT_UPPER 0x0188 +#define NVA197_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVA197_OFFSET_OUT 0x018c +#define NVA197_OFFSET_OUT_VALUE 31:0 + +#define NVA197_PITCH_OUT 0x0190 +#define NVA197_PITCH_OUT_VALUE 31:0 + +#define NVA197_SET_DST_BLOCK_SIZE 0x0194 +#define NVA197_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVA197_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVA197_SET_DST_WIDTH 0x0198 +#define NVA197_SET_DST_WIDTH_V 31:0 + +#define NVA197_SET_DST_HEIGHT 0x019c +#define NVA197_SET_DST_HEIGHT_V 31:0 + +#define NVA197_SET_DST_DEPTH 0x01a0 +#define NVA197_SET_DST_DEPTH_V 31:0 + +#define NVA197_SET_DST_LAYER 0x01a4 +#define NVA197_SET_DST_LAYER_V 31:0 + +#define NVA197_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVA197_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVA197_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVA197_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVA197_LAUNCH_DMA 0x01b0 +#define NVA197_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVA197_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA197_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA197_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVA197_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVA197_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVA197_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVA197_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVA197_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVA197_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVA197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVA197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVA197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVA197_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVA197_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA197_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA197_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA197_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVA197_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA197_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA197_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVA197_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVA197_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVA197_LOAD_INLINE_DATA 0x01b4 +#define NVA197_LOAD_INLINE_DATA_V 31:0 + +#define NVA197_SET_I2M_SEMAPHORE_A 0x01dc +#define NVA197_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVA197_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVA197_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA197_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVA197_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVA197_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVA197_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVA197_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVA197_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVA197_SET_I2M_SPARE_NOOP03 0x01fc +#define NVA197_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVA197_RUN_DS_NOW 0x0200 +#define NVA197_RUN_DS_NOW_V 31:0 + +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVA197_SET_RASTER_PIPE_SYNC_CONTROL 0x0208 +#define NVA197_SET_RASTER_PIPE_SYNC_CONTROL_PRIM_AREA_THRESHOLD 21:0 +#define NVA197_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE 24:24 +#define NVA197_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE_FALSE 0x00000000 +#define NVA197_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVA197_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVA197_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVA197_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVA197_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVA197_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_GS_DM_FIFO 0x0214 +#define NVA197_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVA197_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVA197_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVA197_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVA197_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA197_INVALIDATE_SHADER_CACHES 0x021c +#define NVA197_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVA197_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVA197_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVA197_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVA197_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVA197_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVA197_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVA197_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVA197_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVA197_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVA197_SET_VAB_VERTEX3F(i) (0x0220+(i)*4) +#define NVA197_SET_VAB_VERTEX3F_V 31:0 + +#define NVA197_SET_VAB_VERTEX4F(i) (0x0230+(i)*4) +#define NVA197_SET_VAB_VERTEX4F_V 31:0 + +#define NVA197_SET_VAB_NORMAL3F(i) (0x0240+(i)*4) +#define NVA197_SET_VAB_NORMAL3F_V 31:0 + +#define NVA197_SET_VAB_COLOR3F(i) (0x0250+(i)*4) +#define NVA197_SET_VAB_COLOR3F_V 31:0 + +#define NVA197_SET_VAB_COLOR4F(i) (0x0260+(i)*4) +#define NVA197_SET_VAB_COLOR4F_V 31:0 + +#define NVA197_SET_VAB_COLOR4UB(i) (0x0270+(i)*4) +#define NVA197_SET_VAB_COLOR4UB_V 31:0 + +#define NVA197_SET_VAB_TEX_COORD1F(i) (0x0280+(i)*4) +#define NVA197_SET_VAB_TEX_COORD1F_V 31:0 + +#define NVA197_SET_VAB_TEX_COORD2F(i) (0x0290+(i)*4) +#define NVA197_SET_VAB_TEX_COORD2F_V 31:0 + +#define NVA197_SET_VAB_TEX_COORD3F(i) (0x02a0+(i)*4) +#define NVA197_SET_VAB_TEX_COORD3F_V 31:0 + +#define NVA197_SET_VAB_TEX_COORD4F(i) (0x02b0+(i)*4) +#define NVA197_SET_VAB_TEX_COORD4F_V 31:0 + +#define NVA197_SET_GLOBAL_LOAD_VIA_TEXTURE 0x02c4 +#define NVA197_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE 0:0 +#define NVA197_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE_TRUE 0x00000001 +#define NVA197_SET_GLOBAL_LOAD_VIA_TEXTURE_HEADER_INDEX 23:4 + +#define NVA197_SET_TASK_CIRCULAR_BUFFER_THROTTLE 0x02cc +#define NVA197_SET_TASK_CIRCULAR_BUFFER_THROTTLE_TASK_COUNT 21:0 + +#define NVA197_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NVA197_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NVA197_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVA197_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVA197_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVA197_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 9:0 + +#define NVA197_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVA197_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVA197_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVA197_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVA197_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVA197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVA197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVA197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVA197_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVA197_SET_ZCULL_SUBREGION 0x02e8 +#define NVA197_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVA197_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVA197_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVA197_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVA197_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVA197_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVA197_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVA197_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVA197_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVA197_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVA197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVA197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVA197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVA197_DRAW_ZERO_INDEX 0x0304 +#define NVA197_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVA197_SET_L1_CONFIGURATION 0x0308 +#define NVA197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVA197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVA197_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVA197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVA197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVA197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVA197_SET_SPA_VERSION 0x0310 +#define NVA197_SET_SPA_VERSION_MINOR 7:0 +#define NVA197_SET_SPA_VERSION_MAJOR 15:8 + +#define NVA197_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NVA197_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NVA197_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_SNAP_GRID_LINE 0x0318 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVA197_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVA197_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVA197_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVA197_SET_SNAP_GRID_NON_LINE 0x031c +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVA197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVA197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVA197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVA197_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVA197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVA197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVA197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVA197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVA197_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVA197_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVA197_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVA197_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVA197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVA197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVA197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVA197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVA197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVA197_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVA197_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVA197_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVA197_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVA197_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVA197_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVA197_SET_TESSELLATION_LOD_V1 0x0330 +#define NVA197_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVA197_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVA197_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVA197_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVA197_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVA197_RESERVED_TG07 0x033c +#define NVA197_RESERVED_TG07_V 0:0 + +#define NVA197_RESERVED_TG08 0x0340 +#define NVA197_RESERVED_TG08_V 0:0 + +#define NVA197_RESERVED_TG09 0x0344 +#define NVA197_RESERVED_TG09_V 0:0 + +#define NVA197_RESERVED_TG10 0x0348 +#define NVA197_RESERVED_TG10_V 0:0 + +#define NVA197_RESERVED_TG11 0x034c +#define NVA197_RESERVED_TG11_V 0:0 + +#define NVA197_RESERVED_TG12 0x0350 +#define NVA197_RESERVED_TG12_V 0:0 + +#define NVA197_RESERVED_TG13 0x0354 +#define NVA197_RESERVED_TG13_V 0:0 + +#define NVA197_RESERVED_TG14 0x0358 +#define NVA197_RESERVED_TG14_V 0:0 + +#define NVA197_RESERVED_TG15 0x035c +#define NVA197_RESERVED_TG15_V 0:0 + +#define NVA197_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVA197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVA197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVA197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVA197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVA197_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVA197_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVA197_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVA197_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVA197_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVA197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVA197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVA197_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVA197_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVA197_SET_RASTER_ENABLE 0x037c +#define NVA197_SET_RASTER_ENABLE_V 0:0 +#define NVA197_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVA197_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVA197_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVA197_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVA197_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVA197_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVA197_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVA197_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVA197_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVA197_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVA197_SET_VAB_DATA_TYPELESS(i) (0x0400+(i)*4) +#define NVA197_SET_VAB_DATA_TYPELESS_V 31:0 + +#define NVA197_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVA197_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVA197_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVA197_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVA197_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVA197_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVA197_SET_RASTER_INPUT 0x0740 +#define NVA197_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVA197_SET_STREAM_OUTPUT 0x0744 +#define NVA197_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVA197_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVA197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVA197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_ALPHA_FRACTION 0x074c +#define NVA197_SET_ALPHA_FRACTION_V 7:0 + +#define NVA197_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVA197_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVA197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVA197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVA197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 + +#define NVA197_SET_MAX_TI_WARPS_PER_BATCH 0x075c +#define NVA197_SET_MAX_TI_WARPS_PER_BATCH_V 5:0 + +#define NVA197_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVA197_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA197_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVA197_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVA197_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVA197_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVA197_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVA197_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVA197_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVA197_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVA197_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVA197_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVA197_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVA197_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVA197_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVA197_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVA197_SET_ISBE_SAVE_RESTORE_PROGRAM 0x07ac +#define NVA197_SET_ISBE_SAVE_RESTORE_PROGRAM_OFFSET 31:0 + +#define NVA197_SET_VAB_VERTEX2F(i) (0x07b0+(i)*4) +#define NVA197_SET_VAB_VERTEX2F_V 31:0 + +#define NVA197_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVA197_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVA197_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVA197_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVA197_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVA197_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVA197_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVA197_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVA197_SET_CULL_BEFORE_FETCH 0x07dc +#define NVA197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVA197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVA197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVA197_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVA197_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVA197_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVA197_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVA197_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVA197_SET_ZCULL_STORAGE_A 0x07e8 +#define NVA197_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVA197_SET_ZCULL_STORAGE_B 0x07ec +#define NVA197_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVA197_SET_ZCULL_STORAGE_C 0x07f0 +#define NVA197_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVA197_SET_ZCULL_STORAGE_D 0x07f4 +#define NVA197_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVA197_SET_ZT_READ_ONLY 0x07f8 +#define NVA197_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVA197_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVA197_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVA197_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVA197_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVA197_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVA197_SET_TEXTURE_INSTRUCTION_OPERAND 0x07fc +#define NVA197_SET_TEXTURE_INSTRUCTION_OPERAND_ORDERING 0:0 +#define NVA197_SET_TEXTURE_INSTRUCTION_OPERAND_ORDERING_FERMI_ORDER 0x00000000 +#define NVA197_SET_TEXTURE_INSTRUCTION_OPERAND_ORDERING_KEPLER_ORDER 0x00000001 + +#define NVA197_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVA197_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVA197_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVA197_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVA197_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVA197_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVA197_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVA197_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVA197_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVA197_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVA197_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVA197_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVA197_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVA197_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVA197_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVA197_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVA197_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVA197_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVA197_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA197_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVA197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVA197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVA197_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVA197_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVA197_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVA197_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVA197_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVA197_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVA197_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NVA197_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NVA197_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVA197_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVA197_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVA197_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVA197_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVA197_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVA197_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVA197_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVA197_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVA197_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVA197_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVA197_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVA197_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVA197_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVA197_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVA197_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVA197_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVA197_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVA197_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVA197_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVA197_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVA197_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVA197_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVA197_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVA197_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVA197_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVA197_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVA197_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVA197_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVA197_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVA197_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVA197_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVA197_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVA197_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVA197_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVA197_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVA197_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVA197_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVA197_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVA197_SET_STATISTICS_COUNTER 0x0d68 +#define NVA197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVA197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVA197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVA197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVA197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVA197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVA197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVA197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVA197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVA197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVA197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVA197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVA197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVA197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVA197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVA197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVA197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVA197_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVA197_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVA197_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVA197_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVA197_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVA197_SET_VERTEX_ARRAY_START 0x0d74 +#define NVA197_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVA197_DRAW_VERTEX_ARRAY 0x0d78 +#define NVA197_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVA197_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVA197_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVA197_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVA197_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVA197_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVA197_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVA197_SET_Z_CLEAR_VALUE 0x0d90 +#define NVA197_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVA197_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVA197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVA197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVA197_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVA197_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVA197_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVA197_SET_FRONT_POLYGON_MODE 0x0dac +#define NVA197_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVA197_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVA197_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVA197_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVA197_SET_BACK_POLYGON_MODE 0x0db0 +#define NVA197_SET_BACK_POLYGON_MODE_V 31:0 +#define NVA197_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVA197_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVA197_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVA197_SET_POLY_SMOOTH 0x0db4 +#define NVA197_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVA197_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVA197_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_ZT_MARK 0x0db8 +#define NVA197_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NVA197_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVA197_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVA197_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVA197_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVA197_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVA197_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVA197_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVA197_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVA197_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVA197_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVA197_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVA197_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_PATCH 0x0dcc +#define NVA197_SET_PATCH_SIZE 7:0 + +#define NVA197_SET_ZCULL_CRITERION 0x0dd8 +#define NVA197_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVA197_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVA197_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVA197_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVA197_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVA197_SET_ZCULL_CRITERION_SREF 23:16 +#define NVA197_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVA197_SET_SM_QUADRANT_SELECTION_CONTROL 0x0ddc +#define NVA197_SET_SM_QUADRANT_SELECTION_CONTROL_MAX_PIXEL_WARPS 7:0 + +#define NVA197_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVA197_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVA197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVA197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVA197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_DRAW_INLINE_VERTEX_VAB_UPDATE 0x0dec +#define NVA197_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE 0:0 +#define NVA197_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_WINDOW_OFFSET_X 0x0df8 +#define NVA197_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVA197_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVA197_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVA197_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVA197_SET_SCISSOR_ENABLE_V 0:0 +#define NVA197_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVA197_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVA197_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVA197_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVA197_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVA197_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVA197_SET_VAB_NORMAL3S(i) (0x0f00+(i)*4) +#define NVA197_SET_VAB_NORMAL3S_V 31:0 + +#define NVA197_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVA197_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVA197_SET_BACK_STENCIL_MASK 0x0f58 +#define NVA197_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVA197_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVA197_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVA197_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVA197_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVA197_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVA197_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVA197_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVA197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVA197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVA197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVA197_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVA197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVA197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVA197_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVA197_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVA197_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVA197_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVA197_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVA197_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVA197_SET_CT_MRT_ENABLE 0x0fac +#define NVA197_SET_CT_MRT_ENABLE_V 0:0 +#define NVA197_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVA197_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVA197_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVA197_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVA197_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVA197_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVA197_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVA197_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVA197_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVA197_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVA197_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVA197_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVA197_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVA197_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVA197_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVA197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVA197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVA197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVA197_SET_ZT_A 0x0fe0 +#define NVA197_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_ZT_B 0x0fe4 +#define NVA197_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_ZT_FORMAT 0x0fe8 +#define NVA197_SET_ZT_FORMAT_V 4:0 +#define NVA197_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVA197_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVA197_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVA197_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVA197_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVA197_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVA197_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVA197_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVA197_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVA197_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVA197_SET_ZT_BLOCK_SIZE 0x0fec +#define NVA197_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVA197_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA197_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVA197_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVA197_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVA197_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVA197_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVA197_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVA197_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVA197_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVA197_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVA197_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA197_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVA197_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVA197_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVA197_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVA197_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVA197_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVA197_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVA197_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVA197_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVA197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVA197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVA197_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVA197_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVA197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVA197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_SPARE_NOOP00 0x1040 +#define NVA197_SET_SPARE_NOOP00_V 31:0 + +#define NVA197_SET_SPARE_NOOP01 0x1044 +#define NVA197_SET_SPARE_NOOP01_V 31:0 + +#define NVA197_SET_SPARE_NOOP02 0x1048 +#define NVA197_SET_SPARE_NOOP02_V 31:0 + +#define NVA197_SET_SPARE_NOOP03 0x104c +#define NVA197_SET_SPARE_NOOP03_V 31:0 + +#define NVA197_SET_SPARE_NOOP04 0x1050 +#define NVA197_SET_SPARE_NOOP04_V 31:0 + +#define NVA197_SET_SPARE_NOOP05 0x1054 +#define NVA197_SET_SPARE_NOOP05_V 31:0 + +#define NVA197_SET_SPARE_NOOP06 0x1058 +#define NVA197_SET_SPARE_NOOP06_V 31:0 + +#define NVA197_SET_SPARE_NOOP07 0x105c +#define NVA197_SET_SPARE_NOOP07_V 31:0 + +#define NVA197_SET_SPARE_NOOP08 0x1060 +#define NVA197_SET_SPARE_NOOP08_V 31:0 + +#define NVA197_SET_SPARE_NOOP09 0x1064 +#define NVA197_SET_SPARE_NOOP09_V 31:0 + +#define NVA197_SET_SPARE_NOOP10 0x1068 +#define NVA197_SET_SPARE_NOOP10_V 31:0 + +#define NVA197_SET_SPARE_NOOP11 0x106c +#define NVA197_SET_SPARE_NOOP11_V 31:0 + +#define NVA197_SET_SPARE_NOOP12 0x1070 +#define NVA197_SET_SPARE_NOOP12_V 31:0 + +#define NVA197_SET_SPARE_NOOP13 0x1074 +#define NVA197_SET_SPARE_NOOP13_V 31:0 + +#define NVA197_SET_SPARE_NOOP14 0x1078 +#define NVA197_SET_SPARE_NOOP14_V 31:0 + +#define NVA197_SET_SPARE_NOOP15 0x107c +#define NVA197_SET_SPARE_NOOP15_V 31:0 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVA197_UNBIND_ALL 0x10f4 +#define NVA197_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVA197_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVA197_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVA197_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA197_NO_OPERATION_DATA_HI 0x110c +#define NVA197_NO_OPERATION_DATA_HI_V 31:0 + +#define NVA197_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVA197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVA197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVA197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVA197_PM_TRIGGER_END 0x1114 +#define NVA197_PM_TRIGGER_END_V 31:0 + +#define NVA197_SET_VERTEX_ID_BASE 0x1118 +#define NVA197_SET_VERTEX_ID_BASE_V 31:0 + +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVA197_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVA197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVA197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVA197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVA197_FLUSH_PENDING_WRITES 0x1144 +#define NVA197_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVA197_SET_VAB_DATA_CONTROL 0x114c +#define NVA197_SET_VAB_DATA_CONTROL_VAB_INDEX 7:0 +#define NVA197_SET_VAB_DATA_CONTROL_COMPONENT_COUNT 10:8 +#define NVA197_SET_VAB_DATA_CONTROL_COMPONENT_BYTE_WIDTH 14:12 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT 18:16 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_SNORM 0x00000001 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_UNORM 0x00000002 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_SINT 0x00000003 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_UINT 0x00000004 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_USCALED 0x00000005 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_SSCALED 0x00000006 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_FLOAT 0x00000007 + +#define NVA197_SET_VAB_DATA(i) (0x1150+(i)*4) +#define NVA197_SET_VAB_DATA_V 31:0 + +#define NVA197_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVA197_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVA197_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVA197_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_SET_CT_SELECT 0x121c +#define NVA197_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVA197_SET_CT_SELECT_TARGET0 6:4 +#define NVA197_SET_CT_SELECT_TARGET1 9:7 +#define NVA197_SET_CT_SELECT_TARGET2 12:10 +#define NVA197_SET_CT_SELECT_TARGET3 15:13 +#define NVA197_SET_CT_SELECT_TARGET4 18:16 +#define NVA197_SET_CT_SELECT_TARGET5 21:19 +#define NVA197_SET_CT_SELECT_TARGET6 24:22 +#define NVA197_SET_CT_SELECT_TARGET7 27:25 + +#define NVA197_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVA197_SET_ZT_SIZE_A 0x1228 +#define NVA197_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVA197_SET_ZT_SIZE_B 0x122c +#define NVA197_SET_ZT_SIZE_B_HEIGHT 16:0 + +#define NVA197_SET_ZT_SIZE_C 0x1230 +#define NVA197_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVA197_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVA197_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVA197_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVA197_SET_SAMPLER_BINDING 0x1234 +#define NVA197_SET_SAMPLER_BINDING_V 0:0 +#define NVA197_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVA197_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVA197_DRAW_AUTO 0x123c +#define NVA197_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVA197_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVA197_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 9:0 + +#define NVA197_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVA197_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVA197_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA197_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVA197_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVA197_SET_SHADER_SCHEDULING 0x12ac +#define NVA197_SET_SHADER_SCHEDULING_MODE 0:0 +#define NVA197_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 +#define NVA197_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 + +#define NVA197_CLEAR_ZCULL_REGION 0x12c8 +#define NVA197_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVA197_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVA197_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVA197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVA197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVA197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVA197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVA197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVA197_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVA197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVA197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVA197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVA197_SET_DEPTH_TEST 0x12cc +#define NVA197_SET_DEPTH_TEST_ENABLE 0:0 +#define NVA197_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_FILL_MODE 0x12d0 +#define NVA197_SET_FILL_MODE_V 31:0 +#define NVA197_SET_FILL_MODE_V_POINT 0x00000001 +#define NVA197_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVA197_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVA197_SET_SHADE_MODE 0x12d4 +#define NVA197_SET_SHADE_MODE_V 31:0 +#define NVA197_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVA197_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVA197_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVA197_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVA197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVA197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVA197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVA197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVA197_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVA197_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVA197_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVA197_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_DEPTH_WRITE 0x12e8 +#define NVA197_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVA197_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_ALPHA_TEST 0x12ec +#define NVA197_SET_ALPHA_TEST_ENABLE 0:0 +#define NVA197_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVA197_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVA197_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVA197_DRAW_INLINE_INDEX4X8 0x1304 +#define NVA197_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVA197_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVA197_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVA197_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVA197_D3D_SET_CULL_MODE 0x1308 +#define NVA197_D3D_SET_CULL_MODE_V 31:0 +#define NVA197_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVA197_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVA197_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVA197_SET_DEPTH_FUNC 0x130c +#define NVA197_SET_DEPTH_FUNC_V 31:0 +#define NVA197_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVA197_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVA197_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA197_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA197_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVA197_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA197_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA197_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA197_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVA197_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVA197_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA197_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA197_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVA197_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA197_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA197_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA197_SET_ALPHA_REF 0x1310 +#define NVA197_SET_ALPHA_REF_V 31:0 + +#define NVA197_SET_ALPHA_FUNC 0x1314 +#define NVA197_SET_ALPHA_FUNC_V 31:0 +#define NVA197_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVA197_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVA197_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA197_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA197_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVA197_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA197_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA197_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA197_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVA197_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVA197_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA197_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA197_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVA197_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA197_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA197_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA197_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVA197_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVA197_SET_BLEND_CONST_RED 0x131c +#define NVA197_SET_BLEND_CONST_RED_V 31:0 + +#define NVA197_SET_BLEND_CONST_GREEN 0x1320 +#define NVA197_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVA197_SET_BLEND_CONST_BLUE 0x1324 +#define NVA197_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVA197_SET_BLEND_CONST_ALPHA 0x1328 +#define NVA197_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVA197_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVA197_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVA197_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVA197_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVA197_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVA197_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVA197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVA197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVA197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_BLEND_COLOR_OP 0x1340 +#define NVA197_SET_BLEND_COLOR_OP_V 31:0 +#define NVA197_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA197_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA197_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA197_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVA197_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVA197_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVA197_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA197_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA197_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVA197_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_BLEND_ALPHA_OP 0x134c +#define NVA197_SET_BLEND_ALPHA_OP_V 31:0 +#define NVA197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA197_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVA197_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVA197_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVA197_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA197_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA197_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVA197_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVA197_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVA197_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVA197_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_SINGLE_ROP_CONTROL 0x135c +#define NVA197_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVA197_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_BLEND(i) (0x1360+(i)*4) +#define NVA197_SET_BLEND_ENABLE 0:0 +#define NVA197_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVA197_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_STENCIL_TEST 0x1380 +#define NVA197_SET_STENCIL_TEST_ENABLE 0:0 +#define NVA197_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_STENCIL_OP_FAIL 0x1384 +#define NVA197_SET_STENCIL_OP_FAIL_V 31:0 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVA197_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVA197_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVA197_SET_STENCIL_OP_ZPASS 0x138c +#define NVA197_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVA197_SET_STENCIL_FUNC 0x1390 +#define NVA197_SET_STENCIL_FUNC_V 31:0 +#define NVA197_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVA197_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVA197_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA197_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA197_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVA197_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA197_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA197_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA197_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVA197_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVA197_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA197_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA197_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVA197_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA197_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA197_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA197_SET_STENCIL_FUNC_REF 0x1394 +#define NVA197_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVA197_SET_STENCIL_FUNC_MASK 0x1398 +#define NVA197_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVA197_SET_STENCIL_MASK 0x139c +#define NVA197_SET_STENCIL_MASK_V 7:0 + +#define NVA197_SET_DRAW_AUTO_START 0x13a4 +#define NVA197_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVA197_SET_PS_SATURATE 0x13a8 +#define NVA197_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVA197_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVA197_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVA197_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVA197_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVA197_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVA197_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVA197_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVA197_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 + +#define NVA197_SET_WINDOW_ORIGIN 0x13ac +#define NVA197_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVA197_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVA197_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVA197_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVA197_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVA197_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVA197_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVA197_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVA197_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVA197_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVA197_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVA197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVA197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_ALPHA_HYSTERESIS 0x1420 +#define NVA197_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NVA197_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVA197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVA197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA197_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVA197_INVALIDATE_DA_DMA_CACHE 0x142c +#define NVA197_INVALIDATE_DA_DMA_CACHE_V 0:0 + +#define NVA197_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVA197_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVA197_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVA197_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVA197_SET_PS_WARP_WATERMARKS 0x1450 +#define NVA197_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVA197_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVA197_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVA197_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVA197_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVA197_STORE_ZCULL 0x1464 +#define NVA197_STORE_ZCULL_V 0:0 + +#define NVA197_LOAD_ZCULL 0x1500 +#define NVA197_LOAD_ZCULL_V 0:0 + +#define NVA197_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVA197_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVA197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVA197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVA197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVA197_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVA197_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVA197_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVA197_SET_USER_CLIP_ENABLE 0x1510 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVA197_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVA197_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVA197_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_POINT_SIZE 0x1518 +#define NVA197_SET_POINT_SIZE_V 31:0 + +#define NVA197_SET_ZCULL_STATS 0x151c +#define NVA197_SET_ZCULL_STATS_ENABLE 0:0 +#define NVA197_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_POINT_SPRITE 0x1520 +#define NVA197_SET_POINT_SPRITE_ENABLE 0:0 +#define NVA197_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_SHADER_EXCEPTIONS 0x1528 +#define NVA197_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVA197_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVA197_CLEAR_REPORT_VALUE 0x1530 +#define NVA197_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVA197_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVA197_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVA197_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVA197_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVA197_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVA197_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 + +#define NVA197_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVA197_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVA197_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_ZT_SELECT 0x1538 +#define NVA197_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVA197_SET_RENDER_ENABLE_A 0x1550 +#define NVA197_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_RENDER_ENABLE_B 0x1554 +#define NVA197_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_RENDER_ENABLE_C 0x1558 +#define NVA197_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVA197_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA197_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA197_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA197_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA197_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA197_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVA197_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVA197_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVA197_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVA197_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVA197_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVA197_SET_ANTI_ALIASED_LINE 0x1570 +#define NVA197_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVA197_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_TEX_HEADER_POOL_A 0x1574 +#define NVA197_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_TEX_HEADER_POOL_B 0x1578 +#define NVA197_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_TEX_HEADER_POOL_C 0x157c +#define NVA197_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVA197_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVA197_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVA197_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVA197_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVA197_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVA197_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVA197_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVA197_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVA197_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA197_SET_SRGB_WRITE 0x15b8 +#define NVA197_SET_SRGB_WRITE_ENABLE 0:0 +#define NVA197_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_DEPTH_BIAS 0x15bc +#define NVA197_SET_DEPTH_BIAS_V 31:0 + +#define NVA197_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVA197_SET_RT_LAYER 0x15cc +#define NVA197_SET_RT_LAYER_V 15:0 +#define NVA197_SET_RT_LAYER_CONTROL 16:16 +#define NVA197_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVA197_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVA197_SET_ANTI_ALIAS 0x15d0 +#define NVA197_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVA197_SET_EDGE_FLAG 0x15e4 +#define NVA197_SET_EDGE_FLAG_V 0:0 +#define NVA197_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVA197_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVA197_DRAW_INLINE_INDEX 0x15e8 +#define NVA197_DRAW_INLINE_INDEX_V 31:0 + +#define NVA197_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVA197_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVA197_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVA197_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVA197_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVA197_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVA197_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVA197_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVA197_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVA197_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVA197_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVA197_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVA197_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVA197_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVA197_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVA197_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVA197_SET_POINT_SPRITE_SELECT 0x1604 +#define NVA197_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVA197_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVA197_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVA197_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVA197_SET_PROGRAM_REGION_A 0x1608 +#define NVA197_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVA197_SET_PROGRAM_REGION_B 0x160c +#define NVA197_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVA197_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVA197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVA197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVA197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVA197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVA197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVA197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVA197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVA197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVA197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVA197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVA197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVA197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVA197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVA197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVA197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVA197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVA197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVA197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVA197_END 0x1614 +#define NVA197_END_V 0:0 + +#define NVA197_BEGIN 0x1618 +#define NVA197_BEGIN_OP 15:0 +#define NVA197_BEGIN_OP_POINTS 0x00000000 +#define NVA197_BEGIN_OP_LINES 0x00000001 +#define NVA197_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVA197_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVA197_BEGIN_OP_TRIANGLES 0x00000004 +#define NVA197_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVA197_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVA197_BEGIN_OP_QUADS 0x00000007 +#define NVA197_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVA197_BEGIN_OP_POLYGON 0x00000009 +#define NVA197_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVA197_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVA197_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_BEGIN_OP_PATCH 0x0000000E +#define NVA197_BEGIN_PRIMITIVE_ID 24:24 +#define NVA197_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVA197_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVA197_BEGIN_INSTANCE_ID 27:26 +#define NVA197_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVA197_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVA197_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVA197_BEGIN_SPLIT_MODE 30:29 +#define NVA197_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVA197_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVA197_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVA197_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 + +#define NVA197_SET_VERTEX_ID_COPY 0x161c +#define NVA197_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVA197_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVA197_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVA197_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVA197_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVA197_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVA197_LOAD_PRIMITIVE_ID 0x1624 +#define NVA197_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVA197_SET_SHADER_BASED_CULL 0x162c +#define NVA197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVA197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVA197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVA197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_CLASS_VERSION 0x1638 +#define NVA197_SET_CLASS_VERSION_CURRENT 15:0 +#define NVA197_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA197_SET_VAB_PAGE 0x163c +#define NVA197_SET_VAB_PAGE_READ_SELECT 0:0 +#define NVA197_SET_VAB_PAGE_READ_SELECT_PAGES_0_AND_1 0x00000000 +#define NVA197_SET_VAB_PAGE_READ_SELECT_PAGES_0_AND_2 0x00000001 + +#define NVA197_DRAW_INLINE_VERTEX 0x1640 +#define NVA197_DRAW_INLINE_VERTEX_V 31:0 + +#define NVA197_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVA197_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVA197_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVA197_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVA197_SET_DA_OUTPUT 0x164c +#define NVA197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVA197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVA197_SET_ANTI_ALIASED_POINT 0x1658 +#define NVA197_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVA197_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_POINT_CENTER_MODE 0x165c +#define NVA197_SET_POINT_CENTER_MODE_V 31:0 +#define NVA197_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVA197_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVA197_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVA197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVA197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVA197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVA197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVA197_SET_LINE_STIPPLE 0x166c +#define NVA197_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVA197_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVA197_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVA197_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVA197_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVA197_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVA197_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVA197_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVA197_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVA197_SET_PROVOKING_VERTEX 0x1684 +#define NVA197_SET_PROVOKING_VERTEX_V 0:0 +#define NVA197_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVA197_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVA197_SET_TWO_SIDED_LIGHT 0x1688 +#define NVA197_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVA197_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_POLYGON_STIPPLE 0x168c +#define NVA197_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVA197_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_SHADER_CONTROL 0x1690 +#define NVA197_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVA197_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVA197_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVA197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVA197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVA197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVA197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVA197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVA197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVA197_LAUNCH_VERTEX 0x169c +#define NVA197_LAUNCH_VERTEX_V 0:0 + +#define NVA197_CHECK_CLASS_VERSION 0x16a0 +#define NVA197_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVA197_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA197_SET_SPH_VERSION 0x16a4 +#define NVA197_SET_SPH_VERSION_CURRENT 15:0 +#define NVA197_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA197_CHECK_SPH_VERSION 0x16a8 +#define NVA197_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVA197_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVA197_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVA197_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVA197_SET_AAM_VERSION 0x1790 +#define NVA197_SET_AAM_VERSION_CURRENT 15:0 +#define NVA197_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA197_CHECK_AAM_VERSION 0x1794 +#define NVA197_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVA197_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA197_SET_ZT_LAYER 0x179c +#define NVA197_SET_ZT_LAYER_OFFSET 15:0 + +#define NVA197_SET_VAB_MEMORY_AREA_A 0x17bc +#define NVA197_SET_VAB_MEMORY_AREA_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_VAB_MEMORY_AREA_B 0x17c0 +#define NVA197_SET_VAB_MEMORY_AREA_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_VAB_MEMORY_AREA_C 0x17c4 +#define NVA197_SET_VAB_MEMORY_AREA_C_SIZE 1:0 +#define NVA197_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_64K 0x00000001 +#define NVA197_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_128K 0x00000002 +#define NVA197_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_256K 0x00000003 + +#define NVA197_SET_INDEX_BUFFER_A 0x17c8 +#define NVA197_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVA197_SET_INDEX_BUFFER_B 0x17cc +#define NVA197_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVA197_SET_INDEX_BUFFER_C 0x17d0 +#define NVA197_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVA197_SET_INDEX_BUFFER_D 0x17d4 +#define NVA197_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVA197_SET_INDEX_BUFFER_E 0x17d8 +#define NVA197_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVA197_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVA197_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVA197_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVA197_SET_INDEX_BUFFER_F 0x17dc +#define NVA197_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVA197_DRAW_INDEX_BUFFER 0x17e0 +#define NVA197_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVA197_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVA197_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVA197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVA197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVA197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVA197_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVA197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVA197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVA197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVA197_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVA197_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVA197_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVA197_OGL_SET_CULL 0x1918 +#define NVA197_OGL_SET_CULL_ENABLE 0:0 +#define NVA197_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVA197_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVA197_OGL_SET_FRONT_FACE 0x191c +#define NVA197_OGL_SET_FRONT_FACE_V 31:0 +#define NVA197_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVA197_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVA197_OGL_SET_CULL_FACE 0x1920 +#define NVA197_OGL_SET_CULL_FACE_V 31:0 +#define NVA197_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVA197_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVA197_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVA197_SET_VIEWPORT_PIXEL 0x1924 +#define NVA197_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVA197_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVA197_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVA197_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVA197_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVA197_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVA197_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVA197_INVALIDATE_CONSTANT_BUFFER_CACHE 0x1930 +#define NVA197_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2 0:0 +#define NVA197_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_FALSE 0x00000000 +#define NVA197_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_TRUE 0x00000001 + +#define NVA197_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVA197_SET_USER_CLIP_OP 0x1940 +#define NVA197_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVA197_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVA197_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVA197_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVA197_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVA197_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVA197_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVA197_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVA197_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVA197_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVA197_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVA197_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVA197_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVA197_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVA197_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVA197_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVA197_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVA197_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVA197_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVA197_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVA197_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVA197_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVA197_INVALIDATE_ZCULL 0x1958 +#define NVA197_INVALIDATE_ZCULL_V 31:0 +#define NVA197_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVA197_SET_ZCULL 0x1968 +#define NVA197_SET_ZCULL_Z_ENABLE 0:0 +#define NVA197_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVA197_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_ZCULL_BOUNDS 0x196c +#define NVA197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVA197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVA197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVA197_ZCULL_SYNC 0x1978 +#define NVA197_ZCULL_SYNC_V 31:0 + +#define NVA197_SET_CLIP_ID_TEST 0x197c +#define NVA197_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVA197_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVA197_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVA197_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVA197_SET_CLIP_ID 0x1984 +#define NVA197_SET_CLIP_ID_V 31:0 + +#define NVA197_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVA197_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVA197_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVA197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVA197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVA197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVA197_SET_LOGIC_OP 0x19c4 +#define NVA197_SET_LOGIC_OP_ENABLE 0:0 +#define NVA197_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVA197_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_LOGIC_OP_FUNC 0x19c8 +#define NVA197_SET_LOGIC_OP_FUNC_V 31:0 +#define NVA197_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVA197_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVA197_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVA197_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVA197_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVA197_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVA197_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVA197_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVA197_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVA197_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVA197_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVA197_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVA197_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVA197_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVA197_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVA197_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVA197_SET_Z_COMPRESSION 0x19cc +#define NVA197_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVA197_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVA197_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVA197_CLEAR_SURFACE 0x19d0 +#define NVA197_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVA197_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVA197_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVA197_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVA197_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVA197_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVA197_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVA197_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVA197_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVA197_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVA197_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVA197_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVA197_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVA197_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVA197_SET_CT_WRITE_R_ENABLE 0:0 +#define NVA197_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVA197_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVA197_SET_CT_WRITE_G_ENABLE 4:4 +#define NVA197_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVA197_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVA197_SET_CT_WRITE_B_ENABLE 8:8 +#define NVA197_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVA197_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVA197_SET_CT_WRITE_A_ENABLE 12:12 +#define NVA197_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVA197_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVA197_PIPE_NOP 0x1a2c +#define NVA197_PIPE_NOP_V 31:0 + +#define NVA197_SET_SPARE00 0x1a30 +#define NVA197_SET_SPARE00_V 31:0 + +#define NVA197_SET_SPARE01 0x1a34 +#define NVA197_SET_SPARE01_V 31:0 + +#define NVA197_SET_SPARE02 0x1a38 +#define NVA197_SET_SPARE02_V 31:0 + +#define NVA197_SET_SPARE03 0x1a3c +#define NVA197_SET_SPARE03_V 31:0 + +#define NVA197_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVA197_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVA197_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVA197_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA197_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVA197_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVA197_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVA197_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVA197_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVA197_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVA197_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVA197_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVA197_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVA197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVA197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVA197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVA197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVA197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVA197_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVA197_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVA197_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVA197_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVA197_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVA197_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVA197_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVA197_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVA197_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVA197_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVA197_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVA197_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVA197_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVA197_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVA197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVA197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVA197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVA197_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVA197_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVA197_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVA197_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVA197_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVA197_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVA197_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVA197_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVA197_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVA197_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVA197_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVA197_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVA197_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVA197_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVA197_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVA197_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVA197_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVA197_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVA197_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NVA197_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NVA197_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVA197_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVA197_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVA197_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NVA197_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVA197_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVA197_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NVA197_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVA197_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NVA197_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NVA197_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVA197_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVA197_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVA197_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVA197_SET_FALCON00 0x2300 +#define NVA197_SET_FALCON00_V 31:0 + +#define NVA197_SET_FALCON01 0x2304 +#define NVA197_SET_FALCON01_V 31:0 + +#define NVA197_SET_FALCON02 0x2308 +#define NVA197_SET_FALCON02_V 31:0 + +#define NVA197_SET_FALCON03 0x230c +#define NVA197_SET_FALCON03_V 31:0 + +#define NVA197_SET_FALCON04 0x2310 +#define NVA197_SET_FALCON04_V 31:0 + +#define NVA197_SET_FALCON05 0x2314 +#define NVA197_SET_FALCON05_V 31:0 + +#define NVA197_SET_FALCON06 0x2318 +#define NVA197_SET_FALCON06_V 31:0 + +#define NVA197_SET_FALCON07 0x231c +#define NVA197_SET_FALCON07_V 31:0 + +#define NVA197_SET_FALCON08 0x2320 +#define NVA197_SET_FALCON08_V 31:0 + +#define NVA197_SET_FALCON09 0x2324 +#define NVA197_SET_FALCON09_V 31:0 + +#define NVA197_SET_FALCON10 0x2328 +#define NVA197_SET_FALCON10_V 31:0 + +#define NVA197_SET_FALCON11 0x232c +#define NVA197_SET_FALCON11_V 31:0 + +#define NVA197_SET_FALCON12 0x2330 +#define NVA197_SET_FALCON12_V 31:0 + +#define NVA197_SET_FALCON13 0x2334 +#define NVA197_SET_FALCON13_V 31:0 + +#define NVA197_SET_FALCON14 0x2338 +#define NVA197_SET_FALCON14_V 31:0 + +#define NVA197_SET_FALCON15 0x233c +#define NVA197_SET_FALCON15_V 31:0 + +#define NVA197_SET_FALCON16 0x2340 +#define NVA197_SET_FALCON16_V 31:0 + +#define NVA197_SET_FALCON17 0x2344 +#define NVA197_SET_FALCON17_V 31:0 + +#define NVA197_SET_FALCON18 0x2348 +#define NVA197_SET_FALCON18_V 31:0 + +#define NVA197_SET_FALCON19 0x234c +#define NVA197_SET_FALCON19_V 31:0 + +#define NVA197_SET_FALCON20 0x2350 +#define NVA197_SET_FALCON20_V 31:0 + +#define NVA197_SET_FALCON21 0x2354 +#define NVA197_SET_FALCON21_V 31:0 + +#define NVA197_SET_FALCON22 0x2358 +#define NVA197_SET_FALCON22_V 31:0 + +#define NVA197_SET_FALCON23 0x235c +#define NVA197_SET_FALCON23_V 31:0 + +#define NVA197_SET_FALCON24 0x2360 +#define NVA197_SET_FALCON24_V 31:0 + +#define NVA197_SET_FALCON25 0x2364 +#define NVA197_SET_FALCON25_V 31:0 + +#define NVA197_SET_FALCON26 0x2368 +#define NVA197_SET_FALCON26_V 31:0 + +#define NVA197_SET_FALCON27 0x236c +#define NVA197_SET_FALCON27_V 31:0 + +#define NVA197_SET_FALCON28 0x2370 +#define NVA197_SET_FALCON28_V 31:0 + +#define NVA197_SET_FALCON29 0x2374 +#define NVA197_SET_FALCON29_V 31:0 + +#define NVA197_SET_FALCON30 0x2378 +#define NVA197_SET_FALCON30_V 31:0 + +#define NVA197_SET_FALCON31 0x237c +#define NVA197_SET_FALCON31_V 31:0 + +#define NVA197_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVA197_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVA197_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVA197_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVA197_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVA197_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVA197_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVA197_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVA197_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVA197_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVA197_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVA197_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVA197_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVA197_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVA197_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVA197_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVA197_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVA197_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVA197_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVA197_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVA197_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA197_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA197_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVA197_SET_COLOR_CLAMP 0x2600 +#define NVA197_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVA197_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVA197_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVA197_NOOP_X_X_X_SET_VALVE 0x2604 +#define NVA197_NOOP_X_X_X_SET_VALVE_HIGHER_PRIORITY 0:0 +#define NVA197_NOOP_X_X_X_SET_VALVE_HIGHER_PRIORITY_COMPUTE 0x00000000 +#define NVA197_NOOP_X_X_X_SET_VALVE_HIGHER_PRIORITY_GRAPHICS 0x00000001 + +#define NVA197_SET_BINDLESS_TEXTURE 0x2608 +#define NVA197_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVA197_SET_TRAP_HANDLER 0x260c +#define NVA197_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVA197_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVA197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVA197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVA197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVA197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVA197_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVA197_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVA197_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVA197_CALL_MME_MACRO_V 31:0 + +#define NVA197_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVA197_CALL_MME_DATA_V 31:0 + +#endif /* _cl_kepler_b_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cla1c0.h b/userspace/sdks/nv570/nvidia/inc/class/cla1c0.h new file mode 100644 index 0000000..2b904c0 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cla1c0.h @@ -0,0 +1,669 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_kepler_compute_b_h_ +#define _cl_kepler_compute_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl kepler_compute_b */ + +#include "nvtypes.h" + +#define KEPLER_COMPUTE_B 0xA1C0 + +#define NVA1C0_SET_OBJECT 0x0000 +#define NVA1C0_SET_OBJECT_CLASS_ID 15:0 +#define NVA1C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVA1C0_NO_OPERATION 0x0100 +#define NVA1C0_NO_OPERATION_V 31:0 + +#define NVA1C0_SET_NOTIFY_A 0x0104 +#define NVA1C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_SET_NOTIFY_B 0x0108 +#define NVA1C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_NOTIFY 0x010c +#define NVA1C0_NOTIFY_TYPE 31:0 +#define NVA1C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVA1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVA1C0_WAIT_FOR_IDLE 0x0110 +#define NVA1C0_WAIT_FOR_IDLE_V 31:0 + +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA1C0_SEND_GO_IDLE 0x013c +#define NVA1C0_SEND_GO_IDLE_V 31:0 + +#define NVA1C0_PM_TRIGGER 0x0140 +#define NVA1C0_PM_TRIGGER_V 31:0 + +#define NVA1C0_PM_TRIGGER_WFI 0x0144 +#define NVA1C0_PM_TRIGGER_WFI_V 31:0 + +#define NVA1C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVA1C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVA1C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVA1C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVA1C0_LINE_LENGTH_IN 0x0180 +#define NVA1C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVA1C0_LINE_COUNT 0x0184 +#define NVA1C0_LINE_COUNT_VALUE 31:0 + +#define NVA1C0_OFFSET_OUT_UPPER 0x0188 +#define NVA1C0_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVA1C0_OFFSET_OUT 0x018c +#define NVA1C0_OFFSET_OUT_VALUE 31:0 + +#define NVA1C0_PITCH_OUT 0x0190 +#define NVA1C0_PITCH_OUT_VALUE 31:0 + +#define NVA1C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVA1C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVA1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVA1C0_SET_DST_WIDTH 0x0198 +#define NVA1C0_SET_DST_WIDTH_V 31:0 + +#define NVA1C0_SET_DST_HEIGHT 0x019c +#define NVA1C0_SET_DST_HEIGHT_V 31:0 + +#define NVA1C0_SET_DST_DEPTH 0x01a0 +#define NVA1C0_SET_DST_DEPTH_V 31:0 + +#define NVA1C0_SET_DST_LAYER 0x01a4 +#define NVA1C0_SET_DST_LAYER_V 31:0 + +#define NVA1C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVA1C0_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVA1C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVA1C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVA1C0_LAUNCH_DMA 0x01b0 +#define NVA1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVA1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVA1C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVA1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVA1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVA1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVA1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVA1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVA1C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVA1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA1C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVA1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVA1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVA1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVA1C0_LOAD_INLINE_DATA 0x01b4 +#define NVA1C0_LOAD_INLINE_DATA_V 31:0 + +#define NVA1C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVA1C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVA1C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVA1C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA1C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVA1C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVA1C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVA1C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVA1C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVA1C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVA1C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVA1C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVA1C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVA1C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVA1C0_PERFMON_TRANSFER 0x0210 +#define NVA1C0_PERFMON_TRANSFER_V 31:0 + +#define NVA1C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVA1C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA1C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVA1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVA1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVA1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVA1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVA1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVA1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVA1C0_SET_CWD_CONTROL 0x0240 +#define NVA1C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVA1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVA1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVA1C0_SET_CWD_REF_COUNTER 0x0248 +#define NVA1C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVA1C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVA1C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVA1C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVA1C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA1C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVA1C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVA1C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA1C0_SET_QMD_VERSION 0x0288 +#define NVA1C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVA1C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA1C0_CHECK_QMD_VERSION 0x0290 +#define NVA1C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVA1C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA1C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVA1C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVA1C0_SEND_PCAS_A 0x02b4 +#define NVA1C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVA1C0_SEND_PCAS_B 0x02b8 +#define NVA1C0_SEND_PCAS_B_FROM 23:0 +#define NVA1C0_SEND_PCAS_B_DELTA 31:24 + +#define NVA1C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVA1C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVA1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVA1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVA1C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVA1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVA1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE 0x02c4 +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE 0:0 +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE_TRUE 0x00000001 +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_HEADER_INDEX 23:4 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVA1C0_SET_SPA_VERSION 0x0310 +#define NVA1C0_SET_SPA_VERSION_MINOR 7:0 +#define NVA1C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVA1C0_SET_FALCON00 0x0500 +#define NVA1C0_SET_FALCON00_V 31:0 + +#define NVA1C0_SET_FALCON01 0x0504 +#define NVA1C0_SET_FALCON01_V 31:0 + +#define NVA1C0_SET_FALCON02 0x0508 +#define NVA1C0_SET_FALCON02_V 31:0 + +#define NVA1C0_SET_FALCON03 0x050c +#define NVA1C0_SET_FALCON03_V 31:0 + +#define NVA1C0_SET_FALCON04 0x0510 +#define NVA1C0_SET_FALCON04_V 31:0 + +#define NVA1C0_SET_FALCON05 0x0514 +#define NVA1C0_SET_FALCON05_V 31:0 + +#define NVA1C0_SET_FALCON06 0x0518 +#define NVA1C0_SET_FALCON06_V 31:0 + +#define NVA1C0_SET_FALCON07 0x051c +#define NVA1C0_SET_FALCON07_V 31:0 + +#define NVA1C0_SET_FALCON08 0x0520 +#define NVA1C0_SET_FALCON08_V 31:0 + +#define NVA1C0_SET_FALCON09 0x0524 +#define NVA1C0_SET_FALCON09_V 31:0 + +#define NVA1C0_SET_FALCON10 0x0528 +#define NVA1C0_SET_FALCON10_V 31:0 + +#define NVA1C0_SET_FALCON11 0x052c +#define NVA1C0_SET_FALCON11_V 31:0 + +#define NVA1C0_SET_FALCON12 0x0530 +#define NVA1C0_SET_FALCON12_V 31:0 + +#define NVA1C0_SET_FALCON13 0x0534 +#define NVA1C0_SET_FALCON13_V 31:0 + +#define NVA1C0_SET_FALCON14 0x0538 +#define NVA1C0_SET_FALCON14_V 31:0 + +#define NVA1C0_SET_FALCON15 0x053c +#define NVA1C0_SET_FALCON15_V 31:0 + +#define NVA1C0_SET_FALCON16 0x0540 +#define NVA1C0_SET_FALCON16_V 31:0 + +#define NVA1C0_SET_FALCON17 0x0544 +#define NVA1C0_SET_FALCON17_V 31:0 + +#define NVA1C0_SET_FALCON18 0x0548 +#define NVA1C0_SET_FALCON18_V 31:0 + +#define NVA1C0_SET_FALCON19 0x054c +#define NVA1C0_SET_FALCON19_V 31:0 + +#define NVA1C0_SET_FALCON20 0x0550 +#define NVA1C0_SET_FALCON20_V 31:0 + +#define NVA1C0_SET_FALCON21 0x0554 +#define NVA1C0_SET_FALCON21_V 31:0 + +#define NVA1C0_SET_FALCON22 0x0558 +#define NVA1C0_SET_FALCON22_V 31:0 + +#define NVA1C0_SET_FALCON23 0x055c +#define NVA1C0_SET_FALCON23_V 31:0 + +#define NVA1C0_SET_FALCON24 0x0560 +#define NVA1C0_SET_FALCON24_V 31:0 + +#define NVA1C0_SET_FALCON25 0x0564 +#define NVA1C0_SET_FALCON25_V 31:0 + +#define NVA1C0_SET_FALCON26 0x0568 +#define NVA1C0_SET_FALCON26_V 31:0 + +#define NVA1C0_SET_FALCON27 0x056c +#define NVA1C0_SET_FALCON27_V 31:0 + +#define NVA1C0_SET_FALCON28 0x0570 +#define NVA1C0_SET_FALCON28_V 31:0 + +#define NVA1C0_SET_FALCON29 0x0574 +#define NVA1C0_SET_FALCON29_V 31:0 + +#define NVA1C0_SET_FALCON30 0x0578 +#define NVA1C0_SET_FALCON30_V 31:0 + +#define NVA1C0_SET_FALCON31 0x057c +#define NVA1C0_SET_FALCON31_V 31:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVA1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVA1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVA1C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVA1C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVA1C0_SET_SPARE_NOOP12 0x0f44 +#define NVA1C0_SET_SPARE_NOOP12_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP13 0x0f48 +#define NVA1C0_SET_SPARE_NOOP13_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP14 0x0f4c +#define NVA1C0_SET_SPARE_NOOP14_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP15 0x0f50 +#define NVA1C0_SET_SPARE_NOOP15_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP00 0x1040 +#define NVA1C0_SET_SPARE_NOOP00_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP01 0x1044 +#define NVA1C0_SET_SPARE_NOOP01_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP02 0x1048 +#define NVA1C0_SET_SPARE_NOOP02_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP03 0x104c +#define NVA1C0_SET_SPARE_NOOP03_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP04 0x1050 +#define NVA1C0_SET_SPARE_NOOP04_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP05 0x1054 +#define NVA1C0_SET_SPARE_NOOP05_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP06 0x1058 +#define NVA1C0_SET_SPARE_NOOP06_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP07 0x105c +#define NVA1C0_SET_SPARE_NOOP07_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP08 0x1060 +#define NVA1C0_SET_SPARE_NOOP08_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP09 0x1064 +#define NVA1C0_SET_SPARE_NOOP09_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP10 0x1068 +#define NVA1C0_SET_SPARE_NOOP10_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP11 0x106c +#define NVA1C0_SET_SPARE_NOOP11_V 31:0 + +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVA1C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVA1C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVA1C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVA1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVA1C0_SET_RENDER_ENABLE_A 0x1550 +#define NVA1C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_RENDER_ENABLE_B 0x1554 +#define NVA1C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_RENDER_ENABLE_C 0x1558 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA1C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVA1C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVA1C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVA1C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVA1C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVA1C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVA1C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVA1C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVA1C0_SET_PROGRAM_REGION_A 0x1608 +#define NVA1C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_SET_PROGRAM_REGION_B 0x160c +#define NVA1C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_SET_SHADER_CONTROL 0x1690 +#define NVA1C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVA1C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVA1C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 + +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVA1C0_PIPE_NOP 0x1a2c +#define NVA1C0_PIPE_NOP_V 31:0 + +#define NVA1C0_SET_SPARE00 0x1a30 +#define NVA1C0_SET_SPARE00_V 31:0 + +#define NVA1C0_SET_SPARE01 0x1a34 +#define NVA1C0_SET_SPARE01_V 31:0 + +#define NVA1C0_SET_SPARE02 0x1a38 +#define NVA1C0_SET_SPARE02_V 31:0 + +#define NVA1C0_SET_SPARE03 0x1a3c +#define NVA1C0_SET_SPARE03_V 31:0 + +#define NVA1C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVA1C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVA1C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVA1C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA1C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVA1C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVA1C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVA1C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVA1C0_SET_TRAP_HANDLER 0x260c +#define NVA1C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVA1C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVA1C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_kepler_compute_b_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cla26f.h b/userspace/sdks/nv570/nvidia/inc/class/cla26f.h new file mode 100644 index 0000000..807c5cf --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cla26f.h @@ -0,0 +1,254 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cla26f_h_ +#define _cla26f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class KEPLER_CHANNEL_GPFIFO */ +/* + * Documentation for KEPLER_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + */ +#define KEPLER_CHANNEL_GPFIFO_C (0x0000A26F) + +/* pio method data structure */ +typedef volatile struct _cla26f_tag0 { + NvV32 Reserved00[0x7c0]; +} NvA26FTypedef, KEPLER_ChannelGPFifoC; +#define NVA26F_TYPEDEF KEPLER_CHANNELChannelGPFifo +/* dma flow control data structure */ +typedef volatile struct _cla26f_tag1 { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} NvA26FControl, KeplerCControlGPFifo; +/* fields and values */ +#define NVA26F_NUMBER_OF_SUBCHANNELS (8) +#define NVA26F_SET_OBJECT (0x00000000) +#define NVA26F_SET_OBJECT_NVCLASS 15:0 +#define NVA26F_SET_OBJECT_ENGINE 20:16 +#define NVA26F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVA26F_ILLEGAL (0x00000004) +#define NVA26F_ILLEGAL_HANDLE 31:0 +#define NVA26F_NOP (0x00000008) +#define NVA26F_NOP_HANDLE 31:0 +#define NVA26F_SEMAPHOREA (0x00000010) +#define NVA26F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVA26F_SEMAPHOREB (0x00000014) +#define NVA26F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVA26F_SEMAPHOREC (0x00000018) +#define NVA26F_SEMAPHOREC_PAYLOAD 31:0 +#define NVA26F_SEMAPHORED (0x0000001C) +#define NVA26F_SEMAPHORED_OPERATION 3:0 +#define NVA26F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVA26F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVA26F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVA26F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVA26F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVA26F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVA26F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVA26F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVA26F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVA26F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVA26F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVA26F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVA26F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVA26F_NON_STALL_INTERRUPT (0x00000020) +#define NVA26F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVA26F_FB_FLUSH (0x00000024) +#define NVA26F_FB_FLUSH_HANDLE 31:0 +#define NVA26F_MEM_OP_A (0x00000028) +#define NVA26F_MEM_OP_A_OPERAND_LOW 31:2 +#define NVA26F_MEM_OP_A_TLB_INVALIDATE_ADDR 29:2 +#define NVA26F_MEM_OP_A_TLB_INVALIDATE_TARGET 31:30 +#define NVA26F_MEM_OP_A_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000 +#define NVA26F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002 +#define NVA26F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 +#define NVA26F_MEM_OP_B (0x0000002c) +#define NVA26F_MEM_OP_B_OPERAND_HIGH 7:0 +#define NVA26F_MEM_OP_B_OPERATION 31:27 +#define NVA26F_MEM_OP_B_OPERATION_SYSMEMBAR_FLUSH 0x00000005 +#define NVA26F_MEM_OP_B_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVA26F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e +#define NVA26F_MEM_OP_B_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVA26F_MEM_OP_B_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB 0:0 +#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ALL 0x00000001 +#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC 1:1 +#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVA26F_SET_REFERENCE (0x00000050) +#define NVA26F_SET_REFERENCE_COUNT 31:0 +#define NVA26F_SYNCPOINTA (0x00000070) +#define NVA26F_SYNCPOINTA_PAYLOAD 31:0 +#define NVA26F_SYNCPOINTB (0x00000074) +#define NVA26F_SYNCPOINTB_OPERATION 1:0 +#define NVA26F_SYNCPOINTB_OPERATION_WAIT 0x00000000 +#define NVA26F_SYNCPOINTB_OPERATION_INCR 0x00000001 +#define NVA26F_SYNCPOINTB_OPERATION_BASE_ADD 0x00000002 +#define NVA26F_SYNCPOINTB_OPERATION_BASE_WRITE 0x00000003 +#define NVA26F_SYNCPOINTB_WAIT_SWITCH 4:4 +#define NVA26F_SYNCPOINTB_WAIT_SWITCH_DIS 0x00000000 +#define NVA26F_SYNCPOINTB_WAIT_SWITCH_EN 0x00000001 +#define NVA26F_SYNCPOINTB_BASE 5:5 +#define NVA26F_SYNCPOINTB_BASE_DIS 0x00000000 +#define NVA26F_SYNCPOINTB_BASE_EN 0x00000001 +#define NVA26F_SYNCPOINTB_SYNCPT_INDEX 15:8 +#define NVA26F_SYNCPOINTB_BASE_INDEX 25:20 +#define NVA26F_WFI (0x00000078) +#define NVA26F_WFI_HANDLE 31:0 +#define NVA26F_CRC_CHECK (0x0000007c) +#define NVA26F_CRC_CHECK_VALUE 31:0 +#define NVA26F_YIELD (0x00000080) +#define NVA26F_YIELD_OP 1:0 +#define NVA26F_YIELD_OP_NOP 0x00000000 + +/* GPFIFO entry format */ +#define NVA26F_GP_ENTRY__SIZE 8 +#define NVA26F_GP_ENTRY0_FETCH 0:0 +#define NVA26F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVA26F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVA26F_GP_ENTRY0_GET 31:2 +#define NVA26F_GP_ENTRY0_OPERAND 31:0 +#define NVA26F_GP_ENTRY1_GET_HI 7:0 +#define NVA26F_GP_ENTRY1_PRIV 8:8 +#define NVA26F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NVA26F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NVA26F_GP_ENTRY1_LEVEL 9:9 +#define NVA26F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVA26F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVA26F_GP_ENTRY1_LENGTH 30:10 +#define NVA26F_GP_ENTRY1_SYNC 31:31 +#define NVA26F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVA26F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVA26F_GP_ENTRY1_OPCODE 7:0 +#define NVA26F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVA26F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVA26F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVA26F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVA26F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVA26F_DMA_METHOD_ADDRESS 11:0 +#define NVA26F_DMA_SUBDEVICE_MASK 15:4 +#define NVA26F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVA26F_DMA_TERT_OP 17:16 +#define NVA26F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVA26F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVA26F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVA26F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVA26F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVA26F_DMA_METHOD_COUNT_OLD 28:18 +#define NVA26F_DMA_METHOD_COUNT 28:16 +#define NVA26F_DMA_IMMD_DATA 28:16 +#define NVA26F_DMA_SEC_OP 31:29 +#define NVA26F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVA26F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVA26F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVA26F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVA26F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVA26F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVA26F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVA26F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVA26F_DMA_INCR_ADDRESS 11:0 +#define NVA26F_DMA_INCR_SUBCHANNEL 15:13 +#define NVA26F_DMA_INCR_COUNT 28:16 +#define NVA26F_DMA_INCR_OPCODE 31:29 +#define NVA26F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVA26F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVA26F_DMA_NONINCR_ADDRESS 11:0 +#define NVA26F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVA26F_DMA_NONINCR_COUNT 28:16 +#define NVA26F_DMA_NONINCR_OPCODE 31:29 +#define NVA26F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVA26F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVA26F_DMA_ONEINCR_ADDRESS 11:0 +#define NVA26F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVA26F_DMA_ONEINCR_COUNT 28:16 +#define NVA26F_DMA_ONEINCR_OPCODE 31:29 +#define NVA26F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVA26F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVA26F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVA26F_DMA_IMMD_ADDRESS 11:0 +#define NVA26F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVA26F_DMA_IMMD_DATA 28:16 +#define NVA26F_DMA_IMMD_OPCODE 31:29 +#define NVA26F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVA26F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVA26F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA26F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVA26F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVA26F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA26F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVA26F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA26F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVA26F_DMA_ENDSEG_OPCODE 31:29 +#define NVA26F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVA26F_DMA_ADDRESS 12:2 +#define NVA26F_DMA_SUBCH 15:13 +#define NVA26F_DMA_OPCODE3 17:16 +#define NVA26F_DMA_OPCODE3_NONE (0x00000000) +#define NVA26F_DMA_COUNT 28:18 +#define NVA26F_DMA_OPCODE 31:29 +#define NVA26F_DMA_OPCODE_METHOD (0x00000000) +#define NVA26F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVA26F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cla26f_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clb069.h b/userspace/sdks/nv570/nvidia/inc/class/clb069.h new file mode 100644 index 0000000..94140dd --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clb069.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clb069_h_ +#define _clb069_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define MAXWELL_FAULT_BUFFER_A (0xb069) + +#define NVB069_FAULT_BUF_ENTRY 0x0000001f:0x00000000 +#define NVB069_FAULT_BUF_SIZE 32 +#define NVB069_FAULT_BUF_ENTRY_INST_APERTURE MW((9+0*32):(0*32+8)) +#define NVB069_FAULT_BUF_ENTRY_INST_APERTURE_VID_MEM 0x00000000 +#define NVB069_FAULT_BUF_ENTRY_INST_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVB069_FAULT_BUF_ENTRY_INST_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVB069_FAULT_BUF_ENTRY_INST_LO MW((31+0*32):(0*32+12)) +#define NVB069_FAULT_BUF_ENTRY_INST_HI MW((31+1*32):(1*32+0)) +#define NVB069_FAULT_BUF_ENTRY_INST MW((31+1*32):(0*32+12)) +#define NVB069_FAULT_BUF_ENTRY_ADDR_LO MW((31+2*32):(2*32+0)) +#define NVB069_FAULT_BUF_ENTRY_ADDR_HI MW((31+3*32):(3*32+0)) +#define NVB069_FAULT_BUF_ENTRY_ADDR MW((31+3*32):(2*32+0)) +#define NVB069_FAULT_BUF_ENTRY_TIMESTAMP_LO MW((31+4*32):(4*32+0)) +#define NVB069_FAULT_BUF_ENTRY_TIMESTAMP_HI MW((31+5*32):(5*32+0)) +#define NVB069_FAULT_BUF_ENTRY_TIMESTAMP MW((31+5*32):(4*32+0)) +#define NVB069_FAULT_BUF_ENTRY_RESERVED MW((31+6*32):(6*32+0)) +#define NVB069_FAULT_BUF_ENTRY_FAULT_TYPE MW((4+7*32):(7*32+0)) +#define NVB069_FAULT_BUF_ENTRY_CLIENT MW((14+7*32):(7*32+8)) +#define NVB069_FAULT_BUF_ENTRY_ACCESS_TYPE MW((18+7*32):(7*32+16)) +#define NVB069_FAULT_BUF_ENTRY_MMU_CLIENT_TYPE MW((20+7*32):(7*32+20)) +#define NVB069_FAULT_BUF_ENTRY_GPC_ID MW((28+7*32):(7*32+24)) +#define NVB069_FAULT_BUF_ENTRY_VALID MW((31+7*32):(7*32+31)) +#define NVB069_FAULT_BUF_ENTRY_VALID_FALSE 0x00000000 +#define NVB069_FAULT_BUF_ENTRY_VALID_TRUE 0x00000001 +#define NVB069_NOTIFIERS_REPLAYABLE_FAULT (0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clb069_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clb069sw.h b/userspace/sdks/nv570/nvidia/inc/class/clb069sw.h new file mode 100644 index 0000000..840ac79 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clb069sw.h @@ -0,0 +1,38 @@ +/******************************************************************************* + Copyright (c) 2008-2022 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clb069sw.finn +// + +#define NVB069_ALLOCATION_PARAMETERS_MESSAGE_ID (0xb069U) + +typedef struct NVB069_ALLOCATION_PARAMETERS { + NvU32 flags; // set to 0 +} NVB069_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clb06f.h b/userspace/sdks/nv570/nvidia/inc/class/clb06f.h new file mode 100644 index 0000000..b2b51e0 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clb06f.h @@ -0,0 +1,260 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clb06f_h_ +#define _clb06f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class MAXWELL_CHANNEL_GPFIFO */ +/* + * Documentation for MAXWELL_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + */ +#define MAXWELL_CHANNEL_GPFIFO_A (0x0000B06F) + +#define NVB06F_TYPEDEF MAXWELL_CHANNELChannelGPFifoA + +/* dma flow control data structure */ +typedef volatile struct _clb06f_tag0 { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} Nvb06FControl, MaxwellAControlGPFifo; + +/* fields and values */ +#define NVB06F_NUMBER_OF_SUBCHANNELS (8) +#define NVB06F_SET_OBJECT (0x00000000) +#define NVB06F_SET_OBJECT_NVCLASS 15:0 +#define NVB06F_SET_OBJECT_ENGINE 20:16 +#define NVB06F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVB06F_ILLEGAL (0x00000004) +#define NVB06F_ILLEGAL_HANDLE 31:0 +#define NVB06F_NOP (0x00000008) +#define NVB06F_NOP_HANDLE 31:0 +#define NVB06F_SEMAPHOREA (0x00000010) +#define NVB06F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVB06F_SEMAPHOREB (0x00000014) +#define NVB06F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVB06F_SEMAPHOREC (0x00000018) +#define NVB06F_SEMAPHOREC_PAYLOAD 31:0 +#define NVB06F_SEMAPHORED (0x0000001C) +#define NVB06F_SEMAPHORED_OPERATION 4:0 +#define NVB06F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVB06F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVB06F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVB06F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVB06F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 +#define NVB06F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVB06F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVB06F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVB06F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVB06F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVB06F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVB06F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVB06F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVB06F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVB06F_SEMAPHORED_REDUCTION 30:27 +#define NVB06F_SEMAPHORED_REDUCTION_MIN 0x00000000 +#define NVB06F_SEMAPHORED_REDUCTION_MAX 0x00000001 +#define NVB06F_SEMAPHORED_REDUCTION_XOR 0x00000002 +#define NVB06F_SEMAPHORED_REDUCTION_AND 0x00000003 +#define NVB06F_SEMAPHORED_REDUCTION_OR 0x00000004 +#define NVB06F_SEMAPHORED_REDUCTION_ADD 0x00000005 +#define NVB06F_SEMAPHORED_REDUCTION_INC 0x00000006 +#define NVB06F_SEMAPHORED_REDUCTION_DEC 0x00000007 +#define NVB06F_SEMAPHORED_FORMAT 31:31 +#define NVB06F_SEMAPHORED_FORMAT_SIGNED 0x00000000 +#define NVB06F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 +#define NVB06F_NON_STALL_INTERRUPT (0x00000020) +#define NVB06F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVB06F_FB_FLUSH (0x00000024) +#define NVB06F_FB_FLUSH_HANDLE 31:0 +// NOTE - MEM_OP_A and MEM_OP_B have been removed for gm20x to make room for +// possible future MEM_OP features. MEM_OP_C/D have identical functionality +// to the previous MEM_OP_A/B methods. +#define NVB06F_MEM_OP_C (0x00000030) +#define NVB06F_MEM_OP_C_OPERAND_LOW 31:2 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_TARGET 11:10 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 +#define NVB06F_MEM_OP_C_TLB_INVALIDATE_ADDR_LO 31:12 +#define NVB06F_MEM_OP_D (0x00000034) +#define NVB06F_MEM_OP_D_OPERAND_HIGH 7:0 +#define NVB06F_MEM_OP_D_OPERATION 31:27 +#define NVB06F_MEM_OP_D_OPERATION_MEMBAR 0x00000005 +#define NVB06F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVB06F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NVB06F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +#define NVB06F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVB06F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVB06F_MEM_OP_D_TLB_INVALIDATE_ADDR_HI 7:0 +#define NVB06F_SET_REFERENCE (0x00000050) +#define NVB06F_SET_REFERENCE_COUNT 31:0 +#define NVB06F_WFI (0x00000078) +#define NVB06F_WFI_SCOPE 0:0 +#define NVB06F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000 +#define NVB06F_WFI_SCOPE_ALL 0x00000001 +#define NVB06F_CRC_CHECK (0x0000007c) +#define NVB06F_CRC_CHECK_VALUE 31:0 +#define NVB06F_YIELD (0x00000080) +#define NVB06F_YIELD_OP 1:0 +#define NVB06F_YIELD_OP_NOP 0x00000000 +#define NVB06F_YIELD_OP_PBDMA_TIMESLICE 0x00000001 +#define NVB06F_YIELD_OP_RUNLIST_TIMESLICE 0x00000002 +#define NVB06F_YIELD_OP_TSG 0x00000003 + + +/* GPFIFO entry format */ +#define NVB06F_GP_ENTRY__SIZE 8 +#define NVB06F_GP_ENTRY0_FETCH 0:0 +#define NVB06F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVB06F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVB06F_GP_ENTRY0_GET 31:2 +#define NVB06F_GP_ENTRY0_OPERAND 31:0 +#define NVB06F_GP_ENTRY1_GET_HI 7:0 +#define NVB06F_GP_ENTRY1_PRIV 8:8 +#define NVB06F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NVB06F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NVB06F_GP_ENTRY1_LEVEL 9:9 +#define NVB06F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVB06F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVB06F_GP_ENTRY1_LENGTH 30:10 +#define NVB06F_GP_ENTRY1_SYNC 31:31 +#define NVB06F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVB06F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVB06F_GP_ENTRY1_OPCODE 7:0 +#define NVB06F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVB06F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVB06F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVB06F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVB06F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVB06F_DMA_METHOD_ADDRESS 11:0 +#define NVB06F_DMA_SUBDEVICE_MASK 15:4 +#define NVB06F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVB06F_DMA_TERT_OP 17:16 +#define NVB06F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVB06F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVB06F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVB06F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVB06F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVB06F_DMA_METHOD_COUNT_OLD 28:18 +#define NVB06F_DMA_METHOD_COUNT 28:16 +#define NVB06F_DMA_IMMD_DATA 28:16 +#define NVB06F_DMA_SEC_OP 31:29 +#define NVB06F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVB06F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVB06F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVB06F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVB06F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVB06F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVB06F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVB06F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVB06F_DMA_INCR_ADDRESS 11:0 +#define NVB06F_DMA_INCR_SUBCHANNEL 15:13 +#define NVB06F_DMA_INCR_COUNT 28:16 +#define NVB06F_DMA_INCR_OPCODE 31:29 +#define NVB06F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVB06F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVB06F_DMA_NONINCR_ADDRESS 11:0 +#define NVB06F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVB06F_DMA_NONINCR_COUNT 28:16 +#define NVB06F_DMA_NONINCR_OPCODE 31:29 +#define NVB06F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVB06F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVB06F_DMA_ONEINCR_ADDRESS 11:0 +#define NVB06F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVB06F_DMA_ONEINCR_COUNT 28:16 +#define NVB06F_DMA_ONEINCR_OPCODE 31:29 +#define NVB06F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVB06F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVB06F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVB06F_DMA_IMMD_ADDRESS 11:0 +#define NVB06F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVB06F_DMA_IMMD_DATA 28:16 +#define NVB06F_DMA_IMMD_OPCODE 31:29 +#define NVB06F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVB06F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVB06F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVB06F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVB06F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVB06F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVB06F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVB06F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVB06F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVB06F_DMA_ENDSEG_OPCODE 31:29 +#define NVB06F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVB06F_DMA_ADDRESS 12:2 +#define NVB06F_DMA_SUBCH 15:13 +#define NVB06F_DMA_OPCODE3 17:16 +#define NVB06F_DMA_OPCODE3_NONE (0x00000000) +#define NVB06F_DMA_COUNT 28:18 +#define NVB06F_DMA_OPCODE 31:29 +#define NVB06F_DMA_OPCODE_METHOD (0x00000000) +#define NVB06F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVB06F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clb06f_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clb06fsw.h b/userspace/sdks/nv570/nvidia/inc/class/clb06fsw.h new file mode 100644 index 0000000..3e1c74b --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clb06fsw.h @@ -0,0 +1,42 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clb06f_sw_h_ +#define _clb06f_sw_h_ + +#define NVB06F_NOTIFIERS_RC (0) +#define NVB06F_NOTIFIERS_REFCNT (1) +#define NVB06F_NOTIFIERS_NONSTALL (2) +#define NVB06F_NOTIFIERS_EVENTBUFFER (3) +#define NVB06F_NOTIFIERS_IDLECHANNEL (4) +#define NVB06F_NOTIFIERS_ENDCTX (5) +#define NVB06F_NOTIFIERS_SW (6) +#define NVB06F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVB06F_NOTIFIERS_REPLAYABLE_FAULT (8) +#define NVB06F_NOTIFIERS_MAXCOUNT (9) + +/* NvNotification[] fields and values */ +#define NVB06F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVB06F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _clb06f_sw_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clb097.h b/userspace/sdks/nv570/nvidia/inc/class/clb097.h new file mode 100644 index 0000000..52ee310 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clb097.h @@ -0,0 +1,3966 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_maxwell_a_h_ +#define _cl_maxwell_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl maxwell_a */ + +#include "nvtypes.h" + +#define MAXWELL_A 0xB097 + +#define NVB097_SET_OBJECT 0x0000 +#define NVB097_SET_OBJECT_CLASS_ID 15:0 +#define NVB097_SET_OBJECT_ENGINE_ID 20:16 + +#define NVB097_NO_OPERATION 0x0100 +#define NVB097_NO_OPERATION_V 31:0 + +#define NVB097_SET_NOTIFY_A 0x0104 +#define NVB097_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVB097_SET_NOTIFY_B 0x0108 +#define NVB097_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVB097_NOTIFY 0x010c +#define NVB097_NOTIFY_TYPE 31:0 +#define NVB097_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVB097_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVB097_WAIT_FOR_IDLE 0x0110 +#define NVB097_WAIT_FOR_IDLE_V 31:0 + +#define NVB097_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVB097_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVB097_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVB097_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVB097_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVB097_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVB097_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVB097_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVB097_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVB097_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVB097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVB097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVB097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVB097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVB097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVB097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVB097_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVB097_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVB097_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB097_SEND_GO_IDLE 0x013c +#define NVB097_SEND_GO_IDLE_V 31:0 + +#define NVB097_PM_TRIGGER 0x0140 +#define NVB097_PM_TRIGGER_V 31:0 + +#define NVB097_PM_TRIGGER_WFI 0x0144 +#define NVB097_PM_TRIGGER_WFI_V 31:0 + +#define NVB097_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVB097_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVB097_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVB097_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVB097_LINE_LENGTH_IN 0x0180 +#define NVB097_LINE_LENGTH_IN_VALUE 31:0 + +#define NVB097_LINE_COUNT 0x0184 +#define NVB097_LINE_COUNT_VALUE 31:0 + +#define NVB097_OFFSET_OUT_UPPER 0x0188 +#define NVB097_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVB097_OFFSET_OUT 0x018c +#define NVB097_OFFSET_OUT_VALUE 31:0 + +#define NVB097_PITCH_OUT 0x0190 +#define NVB097_PITCH_OUT_VALUE 31:0 + +#define NVB097_SET_DST_BLOCK_SIZE 0x0194 +#define NVB097_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVB097_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVB097_SET_DST_WIDTH 0x0198 +#define NVB097_SET_DST_WIDTH_V 31:0 + +#define NVB097_SET_DST_HEIGHT 0x019c +#define NVB097_SET_DST_HEIGHT_V 31:0 + +#define NVB097_SET_DST_DEPTH 0x01a0 +#define NVB097_SET_DST_DEPTH_V 31:0 + +#define NVB097_SET_DST_LAYER 0x01a4 +#define NVB097_SET_DST_LAYER_V 31:0 + +#define NVB097_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVB097_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVB097_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVB097_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVB097_LAUNCH_DMA 0x01b0 +#define NVB097_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVB097_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB097_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB097_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVB097_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVB097_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVB097_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVB097_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVB097_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVB097_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVB097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVB097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVB097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVB097_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVB097_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB097_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB097_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB097_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVB097_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB097_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB097_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVB097_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVB097_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVB097_LOAD_INLINE_DATA 0x01b4 +#define NVB097_LOAD_INLINE_DATA_V 31:0 + +#define NVB097_SET_I2M_SEMAPHORE_A 0x01dc +#define NVB097_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVB097_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVB097_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB097_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVB097_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVB097_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVB097_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVB097_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVB097_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVB097_SET_I2M_SPARE_NOOP03 0x01fc +#define NVB097_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVB097_RUN_DS_NOW 0x0200 +#define NVB097_RUN_DS_NOW_V 31:0 + +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVB097_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVB097_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVB097_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVB097_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVB097_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVB097_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_GS_DM_FIFO 0x0214 +#define NVB097_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVB097_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVB097_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVB097_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVB097_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB097_INVALIDATE_SHADER_CACHES 0x021c +#define NVB097_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVB097_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVB097_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVB097_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVB097_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVB097_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVB097_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVB097_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVB097_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVB097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVB097_INCREMENT_SYNC_POINT 0x02c8 +#define NVB097_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVB097_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVB097_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVB097_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVB097_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVB097_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVB097_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVB097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NVB097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NVB097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVB097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVB097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVB097_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVB097_DECOMPRESS_SURFACE 0x02e0 +#define NVB097_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVB097_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVB097_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVB097_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVB097_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVB097_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVB097_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVB097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVB097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVB097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVB097_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVB097_SET_ZCULL_SUBREGION 0x02e8 +#define NVB097_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVB097_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVB097_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVB097_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVB097_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVB097_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVB097_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVB097_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVB097_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVB097_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVB097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVB097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVB097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVB097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVB097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVB097_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVB097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVB097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVB097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVB097_DRAW_ZERO_INDEX 0x0304 +#define NVB097_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVB097_SET_L1_CONFIGURATION 0x0308 +#define NVB097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVB097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVB097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVB097_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVB097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVB097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVB097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVB097_SET_SPA_VERSION 0x0310 +#define NVB097_SET_SPA_VERSION_MINOR 7:0 +#define NVB097_SET_SPA_VERSION_MAJOR 15:8 + +#define NVB097_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NVB097_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NVB097_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_SNAP_GRID_LINE 0x0318 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVB097_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVB097_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVB097_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVB097_SET_SNAP_GRID_NON_LINE 0x031c +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVB097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVB097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVB097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVB097_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVB097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVB097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVB097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVB097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVB097_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVB097_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVB097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVB097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVB097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVB097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVB097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVB097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVB097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVB097_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVB097_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVB097_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVB097_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVB097_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVB097_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVB097_SET_TESSELLATION_LOD_V1 0x0330 +#define NVB097_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVB097_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVB097_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVB097_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVB097_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVB097_RESERVED_TG07 0x033c +#define NVB097_RESERVED_TG07_V 0:0 + +#define NVB097_RESERVED_TG08 0x0340 +#define NVB097_RESERVED_TG08_V 0:0 + +#define NVB097_RESERVED_TG09 0x0344 +#define NVB097_RESERVED_TG09_V 0:0 + +#define NVB097_RESERVED_TG10 0x0348 +#define NVB097_RESERVED_TG10_V 0:0 + +#define NVB097_RESERVED_TG11 0x034c +#define NVB097_RESERVED_TG11_V 0:0 + +#define NVB097_RESERVED_TG12 0x0350 +#define NVB097_RESERVED_TG12_V 0:0 + +#define NVB097_RESERVED_TG13 0x0354 +#define NVB097_RESERVED_TG13_V 0:0 + +#define NVB097_RESERVED_TG14 0x0358 +#define NVB097_RESERVED_TG14_V 0:0 + +#define NVB097_RESERVED_TG15 0x035c +#define NVB097_RESERVED_TG15_V 0:0 + +#define NVB097_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVB097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVB097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVB097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVB097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVB097_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVB097_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVB097_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVB097_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVB097_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVB097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVB097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVB097_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVB097_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVB097_SET_RASTER_ENABLE 0x037c +#define NVB097_SET_RASTER_ENABLE_V 0:0 +#define NVB097_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVB097_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVB097_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVB097_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVB097_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVB097_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVB097_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVB097_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVB097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVB097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVB097_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVB097_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVB097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVB097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVB097_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVB097_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVB097_SET_RASTER_INPUT 0x0740 +#define NVB097_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVB097_SET_STREAM_OUTPUT 0x0744 +#define NVB097_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVB097_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVB097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVB097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_ALPHA_FRACTION 0x074c +#define NVB097_SET_ALPHA_FRACTION_V 7:0 + +#define NVB097_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVB097_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVB097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVB097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVB097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 + +#define NVB097_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVB097_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB097_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVB097_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVB097_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVB097_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVB097_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVB097_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVB097_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVB097_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVB097_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVB097_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVB097_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVB097_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVB097_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVB097_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVB097_SET_ISBE_SAVE_RESTORE_PROGRAM 0x07ac +#define NVB097_SET_ISBE_SAVE_RESTORE_PROGRAM_OFFSET 31:0 + +#define NVB097_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVB097_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVB097_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVB097_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVB097_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVB097_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVB097_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVB097_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVB097_SET_CULL_BEFORE_FETCH 0x07dc +#define NVB097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVB097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVB097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVB097_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVB097_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVB097_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVB097_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVB097_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVB097_SET_ZCULL_STORAGE_A 0x07e8 +#define NVB097_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVB097_SET_ZCULL_STORAGE_B 0x07ec +#define NVB097_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVB097_SET_ZCULL_STORAGE_C 0x07f0 +#define NVB097_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVB097_SET_ZCULL_STORAGE_D 0x07f4 +#define NVB097_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVB097_SET_ZT_READ_ONLY 0x07f8 +#define NVB097_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVB097_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVB097_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVB097_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVB097_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVB097_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVB097_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVB097_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVB097_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVB097_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVB097_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVB097_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVB097_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVB097_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVB097_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVB097_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVB097_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVB097_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVB097_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVB097_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVB097_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVB097_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVB097_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVB097_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVB097_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB097_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVB097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVB097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVB097_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVB097_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVB097_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVB097_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVB097_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVB097_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVB097_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NVB097_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NVB097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVB097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVB097_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVB097_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVB097_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVB097_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVB097_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVB097_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVB097_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVB097_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVB097_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVB097_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVB097_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVB097_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVB097_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVB097_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVB097_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVB097_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVB097_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVB097_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVB097_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVB097_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVB097_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVB097_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVB097_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVB097_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVB097_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVB097_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVB097_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVB097_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVB097_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVB097_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVB097_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVB097_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVB097_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVB097_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVB097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVB097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVB097_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVB097_SET_STATISTICS_COUNTER 0x0d68 +#define NVB097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVB097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVB097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVB097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVB097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVB097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVB097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVB097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVB097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVB097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVB097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVB097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVB097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVB097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVB097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVB097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVB097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVB097_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVB097_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVB097_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVB097_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVB097_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVB097_SET_VERTEX_ARRAY_START 0x0d74 +#define NVB097_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVB097_DRAW_VERTEX_ARRAY 0x0d78 +#define NVB097_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVB097_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVB097_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVB097_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVB097_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVB097_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVB097_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVB097_SET_Z_CLEAR_VALUE 0x0d90 +#define NVB097_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVB097_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVB097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVB097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVB097_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVB097_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVB097_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVB097_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVB097_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVB097_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVB097_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVB097_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVB097_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVB097_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVB097_SET_FRONT_POLYGON_MODE 0x0dac +#define NVB097_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVB097_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVB097_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVB097_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVB097_SET_BACK_POLYGON_MODE 0x0db0 +#define NVB097_SET_BACK_POLYGON_MODE_V 31:0 +#define NVB097_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVB097_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVB097_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVB097_SET_POLY_SMOOTH 0x0db4 +#define NVB097_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVB097_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVB097_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_ZT_MARK 0x0db8 +#define NVB097_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NVB097_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVB097_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVB097_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVB097_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVB097_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVB097_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVB097_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVB097_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVB097_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVB097_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVB097_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVB097_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_PATCH 0x0dcc +#define NVB097_SET_PATCH_SIZE 7:0 + +#define NVB097_SET_ITERATED_BLEND 0x0dd0 +#define NVB097_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVB097_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVB097_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVB097_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVB097_SET_ZCULL_CRITERION 0x0dd8 +#define NVB097_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVB097_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVB097_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVB097_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVB097_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVB097_SET_ZCULL_CRITERION_SREF 23:16 +#define NVB097_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVB097_PIXEL_SHADER_BARRIER 0x0de0 +#define NVB097_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVB097_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVB097_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVB097_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVB097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVB097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVB097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVB097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVB097_SET_WINDOW_OFFSET_X 0x0df8 +#define NVB097_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVB097_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVB097_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVB097_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVB097_SET_SCISSOR_ENABLE_V 0:0 +#define NVB097_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVB097_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVB097_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVB097_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVB097_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVB097_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVB097_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0f10 +#define NVB097_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVB097_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVB097_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVB097_SET_VPC_PERF_KNOB 0x0f14 +#define NVB097_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVB097_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVB097_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVB097_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVB097_PM_LOCAL_TRIGGER 0x0f18 +#define NVB097_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVB097_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVB097_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVB097_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVB097_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVB097_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVB097_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVB097_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVB097_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVB097_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVB097_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVB097_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVB097_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVB097_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVB097_SET_BACK_STENCIL_MASK 0x0f58 +#define NVB097_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVB097_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVB097_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVB097_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVB097_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVB097_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVB097_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVB097_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVB097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVB097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVB097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVB097_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVB097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVB097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVB097_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVB097_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVB097_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVB097_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVB097_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVB097_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVB097_SET_CT_MRT_ENABLE 0x0fac +#define NVB097_SET_CT_MRT_ENABLE_V 0:0 +#define NVB097_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVB097_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVB097_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVB097_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVB097_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVB097_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVB097_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVB097_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVB097_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVB097_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVB097_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVB097_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVB097_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVB097_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVB097_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVB097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVB097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVB097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVB097_SET_ZT_A 0x0fe0 +#define NVB097_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_ZT_B 0x0fe4 +#define NVB097_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_ZT_FORMAT 0x0fe8 +#define NVB097_SET_ZT_FORMAT_V 4:0 +#define NVB097_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVB097_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVB097_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVB097_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVB097_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVB097_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVB097_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVB097_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVB097_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVB097_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVB097_SET_ZT_BLOCK_SIZE 0x0fec +#define NVB097_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVB097_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVB097_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVB097_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVB097_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVB097_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVB097_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVB097_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVB097_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVB097_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVB097_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVB097_SET_TILED_CACHE_BUNDLE_CONTROL 0x0ffc +#define NVB097_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT 0:0 +#define NVB097_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_FALSE 0x00000000 +#define NVB097_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_TRUE 0x00000001 + +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB097_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVB097_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVB097_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVB097_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVB097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVB097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVB097_SET_RESERVED_SW_METHOD00 0x1014 +#define NVB097_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVB097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVB097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVB097_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVB097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVB097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVB097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVB097_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVB097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVB097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_RESERVED_SW_METHOD01 0x1028 +#define NVB097_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD02 0x102c +#define NVB097_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVB097_SET_SPARE_NOOP01 0x1044 +#define NVB097_SET_SPARE_NOOP01_V 31:0 + +#define NVB097_SET_SPARE_NOOP02 0x1048 +#define NVB097_SET_SPARE_NOOP02_V 31:0 + +#define NVB097_SET_SPARE_NOOP03 0x104c +#define NVB097_SET_SPARE_NOOP03_V 31:0 + +#define NVB097_SET_SPARE_NOOP04 0x1050 +#define NVB097_SET_SPARE_NOOP04_V 31:0 + +#define NVB097_SET_SPARE_NOOP05 0x1054 +#define NVB097_SET_SPARE_NOOP05_V 31:0 + +#define NVB097_SET_SPARE_NOOP06 0x1058 +#define NVB097_SET_SPARE_NOOP06_V 31:0 + +#define NVB097_SET_SPARE_NOOP07 0x105c +#define NVB097_SET_SPARE_NOOP07_V 31:0 + +#define NVB097_SET_SPARE_NOOP08 0x1060 +#define NVB097_SET_SPARE_NOOP08_V 31:0 + +#define NVB097_SET_SPARE_NOOP09 0x1064 +#define NVB097_SET_SPARE_NOOP09_V 31:0 + +#define NVB097_SET_SPARE_NOOP10 0x1068 +#define NVB097_SET_SPARE_NOOP10_V 31:0 + +#define NVB097_SET_SPARE_NOOP11 0x106c +#define NVB097_SET_SPARE_NOOP11_V 31:0 + +#define NVB097_SET_SPARE_NOOP12 0x1070 +#define NVB097_SET_SPARE_NOOP12_V 31:0 + +#define NVB097_SET_SPARE_NOOP13 0x1074 +#define NVB097_SET_SPARE_NOOP13_V 31:0 + +#define NVB097_SET_SPARE_NOOP14 0x1078 +#define NVB097_SET_SPARE_NOOP14_V 31:0 + +#define NVB097_SET_SPARE_NOOP15 0x107c +#define NVB097_SET_SPARE_NOOP15_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVB097_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVB097_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVB097_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD06 0x10bc +#define NVB097_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVB097_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVB097_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVB097_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVB097_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVB097_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVB097_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVB097_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD13 0x10dc +#define NVB097_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVB097_UNBIND_ALL 0x10f4 +#define NVB097_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVB097_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVB097_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVB097_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB097_SET_RESERVED_SW_METHOD14 0x1100 +#define NVB097_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD15 0x1104 +#define NVB097_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVB097_NO_OPERATION_DATA_HI 0x110c +#define NVB097_NO_OPERATION_DATA_HI_V 31:0 + +#define NVB097_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVB097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVB097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVB097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVB097_PM_TRIGGER_END 0x1114 +#define NVB097_PM_TRIGGER_END_V 31:0 + +#define NVB097_SET_VERTEX_ID_BASE 0x1118 +#define NVB097_SET_VERTEX_ID_BASE_V 31:0 + +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVB097_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVB097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVB097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVB097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVB097_FLUSH_PENDING_WRITES 0x1144 +#define NVB097_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVB097_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVB097_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVB097_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVB097_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_SET_CT_SELECT 0x121c +#define NVB097_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVB097_SET_CT_SELECT_TARGET0 6:4 +#define NVB097_SET_CT_SELECT_TARGET1 9:7 +#define NVB097_SET_CT_SELECT_TARGET2 12:10 +#define NVB097_SET_CT_SELECT_TARGET3 15:13 +#define NVB097_SET_CT_SELECT_TARGET4 18:16 +#define NVB097_SET_CT_SELECT_TARGET5 21:19 +#define NVB097_SET_CT_SELECT_TARGET6 24:22 +#define NVB097_SET_CT_SELECT_TARGET7 27:25 + +#define NVB097_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVB097_SET_ZT_SIZE_A 0x1228 +#define NVB097_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVB097_SET_ZT_SIZE_B 0x122c +#define NVB097_SET_ZT_SIZE_B_HEIGHT 16:0 + +#define NVB097_SET_ZT_SIZE_C 0x1230 +#define NVB097_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVB097_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVB097_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVB097_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVB097_SET_SAMPLER_BINDING 0x1234 +#define NVB097_SET_SAMPLER_BINDING_V 0:0 +#define NVB097_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVB097_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVB097_DRAW_AUTO 0x123c +#define NVB097_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVB097_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVB097_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVB097_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVB097_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVB097_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVB097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVB097_CLEAR_ZCULL_REGION 0x12c8 +#define NVB097_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVB097_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVB097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVB097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVB097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVB097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVB097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVB097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVB097_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVB097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVB097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVB097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVB097_SET_DEPTH_TEST 0x12cc +#define NVB097_SET_DEPTH_TEST_ENABLE 0:0 +#define NVB097_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVB097_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_FILL_MODE 0x12d0 +#define NVB097_SET_FILL_MODE_V 31:0 +#define NVB097_SET_FILL_MODE_V_POINT 0x00000001 +#define NVB097_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVB097_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVB097_SET_SHADE_MODE 0x12d4 +#define NVB097_SET_SHADE_MODE_V 31:0 +#define NVB097_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVB097_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVB097_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVB097_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVB097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVB097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVB097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVB097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVB097_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVB097_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVB097_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVB097_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_DEPTH_WRITE 0x12e8 +#define NVB097_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVB097_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_ALPHA_TEST 0x12ec +#define NVB097_SET_ALPHA_TEST_ENABLE 0:0 +#define NVB097_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVB097_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVB097_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVB097_DRAW_INLINE_INDEX4X8 0x1304 +#define NVB097_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVB097_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVB097_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVB097_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVB097_D3D_SET_CULL_MODE 0x1308 +#define NVB097_D3D_SET_CULL_MODE_V 31:0 +#define NVB097_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVB097_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVB097_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVB097_SET_DEPTH_FUNC 0x130c +#define NVB097_SET_DEPTH_FUNC_V 31:0 +#define NVB097_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVB097_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVB097_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB097_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB097_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVB097_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB097_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB097_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB097_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVB097_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVB097_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB097_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB097_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVB097_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB097_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB097_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB097_SET_ALPHA_REF 0x1310 +#define NVB097_SET_ALPHA_REF_V 31:0 + +#define NVB097_SET_ALPHA_FUNC 0x1314 +#define NVB097_SET_ALPHA_FUNC_V 31:0 +#define NVB097_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVB097_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVB097_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB097_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB097_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVB097_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB097_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB097_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB097_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVB097_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVB097_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB097_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB097_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVB097_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB097_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB097_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB097_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVB097_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVB097_SET_BLEND_CONST_RED 0x131c +#define NVB097_SET_BLEND_CONST_RED_V 31:0 + +#define NVB097_SET_BLEND_CONST_GREEN 0x1320 +#define NVB097_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVB097_SET_BLEND_CONST_BLUE 0x1324 +#define NVB097_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVB097_SET_BLEND_CONST_ALPHA 0x1328 +#define NVB097_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVB097_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVB097_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVB097_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVB097_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVB097_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVB097_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVB097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVB097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVB097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BLEND_COLOR_OP 0x1340 +#define NVB097_SET_BLEND_COLOR_OP_V 31:0 +#define NVB097_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB097_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB097_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB097_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVB097_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVB097_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVB097_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB097_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB097_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVB097_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_BLEND_ALPHA_OP 0x134c +#define NVB097_SET_BLEND_ALPHA_OP_V 31:0 +#define NVB097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB097_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVB097_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVB097_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVB097_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB097_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB097_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVB097_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVB097_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVB097_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVB097_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_SINGLE_ROP_CONTROL 0x135c +#define NVB097_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVB097_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BLEND(i) (0x1360+(i)*4) +#define NVB097_SET_BLEND_ENABLE 0:0 +#define NVB097_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVB097_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_STENCIL_TEST 0x1380 +#define NVB097_SET_STENCIL_TEST_ENABLE 0:0 +#define NVB097_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_STENCIL_OP_FAIL 0x1384 +#define NVB097_SET_STENCIL_OP_FAIL_V 31:0 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVB097_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVB097_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVB097_SET_STENCIL_OP_ZPASS 0x138c +#define NVB097_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVB097_SET_STENCIL_FUNC 0x1390 +#define NVB097_SET_STENCIL_FUNC_V 31:0 +#define NVB097_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVB097_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVB097_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB097_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB097_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVB097_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB097_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB097_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB097_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVB097_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVB097_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB097_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB097_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVB097_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB097_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB097_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB097_SET_STENCIL_FUNC_REF 0x1394 +#define NVB097_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVB097_SET_STENCIL_FUNC_MASK 0x1398 +#define NVB097_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVB097_SET_STENCIL_MASK 0x139c +#define NVB097_SET_STENCIL_MASK_V 7:0 + +#define NVB097_SET_DRAW_AUTO_START 0x13a4 +#define NVB097_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVB097_SET_PS_SATURATE 0x13a8 +#define NVB097_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVB097_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVB097_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVB097_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVB097_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVB097_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVB097_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVB097_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVB097_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVB097_SET_WINDOW_ORIGIN 0x13ac +#define NVB097_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVB097_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVB097_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVB097_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVB097_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVB097_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVB097_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVB097_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVB097_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVB097_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVB097_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVB097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVB097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_ALPHA_HYSTERESIS 0x1420 +#define NVB097_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NVB097_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVB097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVB097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB097_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVB097_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVB097_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVB097_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVB097_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVB097_SET_PS_WARP_WATERMARKS 0x1450 +#define NVB097_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVB097_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVB097_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVB097_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVB097_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVB097_STORE_ZCULL 0x1464 +#define NVB097_STORE_ZCULL_V 0:0 + +#define NVB097_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVB097_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVB097_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVB097_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVB097_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVB097_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVB097_LOAD_ZCULL 0x1500 +#define NVB097_LOAD_ZCULL_V 0:0 + +#define NVB097_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVB097_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVB097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVB097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVB097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVB097_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVB097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVB097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVB097_SET_USER_CLIP_ENABLE 0x1510 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVB097_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVB097_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVB097_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_POINT_SIZE 0x1518 +#define NVB097_SET_POINT_SIZE_V 31:0 + +#define NVB097_SET_ZCULL_STATS 0x151c +#define NVB097_SET_ZCULL_STATS_ENABLE 0:0 +#define NVB097_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_POINT_SPRITE 0x1520 +#define NVB097_SET_POINT_SPRITE_ENABLE 0:0 +#define NVB097_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_SHADER_EXCEPTIONS 0x1528 +#define NVB097_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVB097_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVB097_CLEAR_REPORT_VALUE 0x1530 +#define NVB097_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVB097_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVB097_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVB097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVB097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVB097_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVB097_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 + +#define NVB097_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVB097_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVB097_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_ZT_SELECT 0x1538 +#define NVB097_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVB097_SET_RENDER_ENABLE_A 0x1550 +#define NVB097_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_RENDER_ENABLE_B 0x1554 +#define NVB097_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_RENDER_ENABLE_C 0x1558 +#define NVB097_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVB097_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB097_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB097_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB097_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVB097_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVB097_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVB097_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVB097_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVB097_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVB097_SET_ANTI_ALIASED_LINE 0x1570 +#define NVB097_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVB097_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_TEX_HEADER_POOL_A 0x1574 +#define NVB097_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_TEX_HEADER_POOL_B 0x1578 +#define NVB097_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_TEX_HEADER_POOL_C 0x157c +#define NVB097_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVB097_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVB097_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVB097_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVB097_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVB097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVB097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVB097_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVB097_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVB097_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB097_SET_SRGB_WRITE 0x15b8 +#define NVB097_SET_SRGB_WRITE_ENABLE 0:0 +#define NVB097_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_DEPTH_BIAS 0x15bc +#define NVB097_SET_DEPTH_BIAS_V 31:0 + +#define NVB097_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVB097_SET_RT_LAYER 0x15cc +#define NVB097_SET_RT_LAYER_V 15:0 +#define NVB097_SET_RT_LAYER_CONTROL 16:16 +#define NVB097_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVB097_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVB097_SET_ANTI_ALIAS 0x15d0 +#define NVB097_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVB097_SET_EDGE_FLAG 0x15e4 +#define NVB097_SET_EDGE_FLAG_V 0:0 +#define NVB097_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVB097_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVB097_DRAW_INLINE_INDEX 0x15e8 +#define NVB097_DRAW_INLINE_INDEX_V 31:0 + +#define NVB097_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVB097_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVB097_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVB097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVB097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVB097_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVB097_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVB097_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVB097_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVB097_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVB097_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVB097_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVB097_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVB097_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVB097_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVB097_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVB097_SET_POINT_SPRITE_SELECT 0x1604 +#define NVB097_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVB097_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVB097_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVB097_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVB097_SET_PROGRAM_REGION_A 0x1608 +#define NVB097_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVB097_SET_PROGRAM_REGION_B 0x160c +#define NVB097_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVB097_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVB097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVB097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVB097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVB097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVB097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVB097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVB097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVB097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVB097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVB097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVB097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVB097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVB097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVB097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVB097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVB097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVB097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVB097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVB097_END 0x1614 +#define NVB097_END_V 0:0 + +#define NVB097_BEGIN 0x1618 +#define NVB097_BEGIN_OP 15:0 +#define NVB097_BEGIN_OP_POINTS 0x00000000 +#define NVB097_BEGIN_OP_LINES 0x00000001 +#define NVB097_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVB097_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVB097_BEGIN_OP_TRIANGLES 0x00000004 +#define NVB097_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVB097_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVB097_BEGIN_OP_QUADS 0x00000007 +#define NVB097_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVB097_BEGIN_OP_POLYGON 0x00000009 +#define NVB097_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVB097_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVB097_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_BEGIN_OP_PATCH 0x0000000E +#define NVB097_BEGIN_PRIMITIVE_ID 24:24 +#define NVB097_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVB097_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVB097_BEGIN_INSTANCE_ID 27:26 +#define NVB097_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVB097_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVB097_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVB097_BEGIN_SPLIT_MODE 30:29 +#define NVB097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVB097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVB097_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVB097_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 + +#define NVB097_SET_VERTEX_ID_COPY 0x161c +#define NVB097_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVB097_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVB097_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVB097_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVB097_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVB097_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVB097_LOAD_PRIMITIVE_ID 0x1624 +#define NVB097_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVB097_SET_SHADER_BASED_CULL 0x162c +#define NVB097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVB097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVB097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVB097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_CLASS_VERSION 0x1638 +#define NVB097_SET_CLASS_VERSION_CURRENT 15:0 +#define NVB097_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB097_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVB097_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVB097_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVB097_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVB097_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVB097_SET_DA_OUTPUT 0x164c +#define NVB097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVB097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVB097_SET_ANTI_ALIASED_POINT 0x1658 +#define NVB097_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVB097_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_POINT_CENTER_MODE 0x165c +#define NVB097_SET_POINT_CENTER_MODE_V 31:0 +#define NVB097_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVB097_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVB097_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVB097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVB097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVB097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVB097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVB097_SET_LINE_STIPPLE 0x166c +#define NVB097_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVB097_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVB097_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVB097_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVB097_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVB097_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVB097_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVB097_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVB097_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVB097_SET_PROVOKING_VERTEX 0x1684 +#define NVB097_SET_PROVOKING_VERTEX_V 0:0 +#define NVB097_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVB097_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVB097_SET_TWO_SIDED_LIGHT 0x1688 +#define NVB097_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVB097_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_POLYGON_STIPPLE 0x168c +#define NVB097_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVB097_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_SHADER_CONTROL 0x1690 +#define NVB097_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVB097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVB097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVB097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVB097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVB097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVB097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVB097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVB097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVB097_CHECK_CLASS_VERSION 0x16a0 +#define NVB097_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVB097_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB097_SET_SPH_VERSION 0x16a4 +#define NVB097_SET_SPH_VERSION_CURRENT 15:0 +#define NVB097_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB097_CHECK_SPH_VERSION 0x16a8 +#define NVB097_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVB097_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVB097_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVB097_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVB097_SET_AAM_VERSION 0x1790 +#define NVB097_SET_AAM_VERSION_CURRENT 15:0 +#define NVB097_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB097_CHECK_AAM_VERSION 0x1794 +#define NVB097_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVB097_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB097_SET_ZT_LAYER 0x179c +#define NVB097_SET_ZT_LAYER_OFFSET 15:0 + +#define NVB097_SET_INDEX_BUFFER_A 0x17c8 +#define NVB097_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVB097_SET_INDEX_BUFFER_B 0x17cc +#define NVB097_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVB097_SET_INDEX_BUFFER_C 0x17d0 +#define NVB097_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVB097_SET_INDEX_BUFFER_D 0x17d4 +#define NVB097_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVB097_SET_INDEX_BUFFER_E 0x17d8 +#define NVB097_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVB097_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVB097_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVB097_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVB097_SET_INDEX_BUFFER_F 0x17dc +#define NVB097_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVB097_DRAW_INDEX_BUFFER 0x17e0 +#define NVB097_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVB097_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVB097_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVB097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVB097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVB097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVB097_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVB097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVB097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVB097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVB097_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVB097_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVB097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVB097_OGL_SET_CULL 0x1918 +#define NVB097_OGL_SET_CULL_ENABLE 0:0 +#define NVB097_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVB097_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVB097_OGL_SET_FRONT_FACE 0x191c +#define NVB097_OGL_SET_FRONT_FACE_V 31:0 +#define NVB097_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVB097_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVB097_OGL_SET_CULL_FACE 0x1920 +#define NVB097_OGL_SET_CULL_FACE_V 31:0 +#define NVB097_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVB097_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVB097_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVB097_SET_VIEWPORT_PIXEL 0x1924 +#define NVB097_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVB097_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVB097_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVB097_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVB097_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVB097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVB097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVB097_SET_USER_CLIP_OP 0x1940 +#define NVB097_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVB097_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVB097_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVB097_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVB097_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVB097_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVB097_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVB097_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVB097_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVB097_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVB097_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVB097_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVB097_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVB097_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVB097_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVB097_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVB097_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVB097_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVB097_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVB097_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVB097_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVB097_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVB097_INVALIDATE_ZCULL 0x1958 +#define NVB097_INVALIDATE_ZCULL_V 31:0 +#define NVB097_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVB097_SET_ZCULL 0x1968 +#define NVB097_SET_ZCULL_Z_ENABLE 0:0 +#define NVB097_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVB097_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_ZCULL_BOUNDS 0x196c +#define NVB097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVB097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVB097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVB097_ZCULL_SYNC 0x1978 +#define NVB097_ZCULL_SYNC_V 31:0 + +#define NVB097_SET_CLIP_ID_TEST 0x197c +#define NVB097_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVB097_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVB097_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVB097_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVB097_SET_CLIP_ID 0x1984 +#define NVB097_SET_CLIP_ID_V 31:0 + +#define NVB097_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVB097_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVB097_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVB097_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVB097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVB097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVB097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVB097_SET_LOGIC_OP 0x19c4 +#define NVB097_SET_LOGIC_OP_ENABLE 0:0 +#define NVB097_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVB097_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_LOGIC_OP_FUNC 0x19c8 +#define NVB097_SET_LOGIC_OP_FUNC_V 31:0 +#define NVB097_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVB097_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVB097_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVB097_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVB097_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVB097_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVB097_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVB097_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVB097_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVB097_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVB097_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVB097_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVB097_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVB097_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVB097_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVB097_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVB097_SET_Z_COMPRESSION 0x19cc +#define NVB097_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVB097_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVB097_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVB097_CLEAR_SURFACE 0x19d0 +#define NVB097_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVB097_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVB097_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVB097_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVB097_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVB097_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVB097_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVB097_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVB097_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVB097_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVB097_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVB097_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVB097_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVB097_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVB097_SET_CT_WRITE_R_ENABLE 0:0 +#define NVB097_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVB097_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVB097_SET_CT_WRITE_G_ENABLE 4:4 +#define NVB097_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVB097_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVB097_SET_CT_WRITE_B_ENABLE 8:8 +#define NVB097_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVB097_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVB097_SET_CT_WRITE_A_ENABLE 12:12 +#define NVB097_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVB097_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVB097_PIPE_NOP 0x1a2c +#define NVB097_PIPE_NOP_V 31:0 + +#define NVB097_SET_SPARE00 0x1a30 +#define NVB097_SET_SPARE00_V 31:0 + +#define NVB097_SET_SPARE01 0x1a34 +#define NVB097_SET_SPARE01_V 31:0 + +#define NVB097_SET_SPARE02 0x1a38 +#define NVB097_SET_SPARE02_V 31:0 + +#define NVB097_SET_SPARE03 0x1a3c +#define NVB097_SET_SPARE03_V 31:0 + +#define NVB097_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVB097_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVB097_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVB097_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB097_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVB097_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVB097_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVB097_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVB097_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVB097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVB097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVB097_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVB097_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVB097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVB097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVB097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVB097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVB097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVB097_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVB097_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVB097_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVB097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVB097_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVB097_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVB097_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVB097_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVB097_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVB097_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVB097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVB097_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVB097_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVB097_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVB097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVB097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVB097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVB097_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVB097_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVB097_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVB097_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVB097_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVB097_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVB097_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVB097_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVB097_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVB097_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVB097_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVB097_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVB097_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVB097_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVB097_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVB097_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVB097_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVB097_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVB097_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NVB097_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NVB097_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVB097_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVB097_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVB097_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NVB097_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVB097_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVB097_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NVB097_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVB097_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NVB097_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NVB097_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVB097_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVB097_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVB097_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVB097_SET_FALCON00 0x2300 +#define NVB097_SET_FALCON00_V 31:0 + +#define NVB097_SET_FALCON01 0x2304 +#define NVB097_SET_FALCON01_V 31:0 + +#define NVB097_SET_FALCON02 0x2308 +#define NVB097_SET_FALCON02_V 31:0 + +#define NVB097_SET_FALCON03 0x230c +#define NVB097_SET_FALCON03_V 31:0 + +#define NVB097_SET_FALCON04 0x2310 +#define NVB097_SET_FALCON04_V 31:0 + +#define NVB097_SET_FALCON05 0x2314 +#define NVB097_SET_FALCON05_V 31:0 + +#define NVB097_SET_FALCON06 0x2318 +#define NVB097_SET_FALCON06_V 31:0 + +#define NVB097_SET_FALCON07 0x231c +#define NVB097_SET_FALCON07_V 31:0 + +#define NVB097_SET_FALCON08 0x2320 +#define NVB097_SET_FALCON08_V 31:0 + +#define NVB097_SET_FALCON09 0x2324 +#define NVB097_SET_FALCON09_V 31:0 + +#define NVB097_SET_FALCON10 0x2328 +#define NVB097_SET_FALCON10_V 31:0 + +#define NVB097_SET_FALCON11 0x232c +#define NVB097_SET_FALCON11_V 31:0 + +#define NVB097_SET_FALCON12 0x2330 +#define NVB097_SET_FALCON12_V 31:0 + +#define NVB097_SET_FALCON13 0x2334 +#define NVB097_SET_FALCON13_V 31:0 + +#define NVB097_SET_FALCON14 0x2338 +#define NVB097_SET_FALCON14_V 31:0 + +#define NVB097_SET_FALCON15 0x233c +#define NVB097_SET_FALCON15_V 31:0 + +#define NVB097_SET_FALCON16 0x2340 +#define NVB097_SET_FALCON16_V 31:0 + +#define NVB097_SET_FALCON17 0x2344 +#define NVB097_SET_FALCON17_V 31:0 + +#define NVB097_SET_FALCON18 0x2348 +#define NVB097_SET_FALCON18_V 31:0 + +#define NVB097_SET_FALCON19 0x234c +#define NVB097_SET_FALCON19_V 31:0 + +#define NVB097_SET_FALCON20 0x2350 +#define NVB097_SET_FALCON20_V 31:0 + +#define NVB097_SET_FALCON21 0x2354 +#define NVB097_SET_FALCON21_V 31:0 + +#define NVB097_SET_FALCON22 0x2358 +#define NVB097_SET_FALCON22_V 31:0 + +#define NVB097_SET_FALCON23 0x235c +#define NVB097_SET_FALCON23_V 31:0 + +#define NVB097_SET_FALCON24 0x2360 +#define NVB097_SET_FALCON24_V 31:0 + +#define NVB097_SET_FALCON25 0x2364 +#define NVB097_SET_FALCON25_V 31:0 + +#define NVB097_SET_FALCON26 0x2368 +#define NVB097_SET_FALCON26_V 31:0 + +#define NVB097_SET_FALCON27 0x236c +#define NVB097_SET_FALCON27_V 31:0 + +#define NVB097_SET_FALCON28 0x2370 +#define NVB097_SET_FALCON28_V 31:0 + +#define NVB097_SET_FALCON29 0x2374 +#define NVB097_SET_FALCON29_V 31:0 + +#define NVB097_SET_FALCON30 0x2378 +#define NVB097_SET_FALCON30_V 31:0 + +#define NVB097_SET_FALCON31 0x237c +#define NVB097_SET_FALCON31_V 31:0 + +#define NVB097_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVB097_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVB097_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVB097_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVB097_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVB097_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVB097_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVB097_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVB097_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVB097_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVB097_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVB097_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVB097_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVB097_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVB097_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVB097_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVB097_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVB097_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVB097_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVB097_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVB097_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVB097_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVB097_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVB097_SET_COLOR_CLAMP 0x2600 +#define NVB097_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVB097_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVB097_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BINDLESS_TEXTURE 0x2608 +#define NVB097_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVB097_SET_TRAP_HANDLER 0x260c +#define NVB097_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVB097_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVB097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVB097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVB097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVB097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVB097_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVB097_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB097_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVB097_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB097_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVB097_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVB097_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVB097_CALL_MME_MACRO_V 31:0 + +#define NVB097_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVB097_CALL_MME_DATA_V 31:0 + +#endif /* _cl_maxwell_a_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clb097tex.h b/userspace/sdks/nv570/nvidia/inc/class/clb097tex.h new file mode 100644 index 0000000..e5543e3 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clb097tex.h @@ -0,0 +1,2050 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2010 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLB097TEX_H__ +#define __CLB097TEX_H__ + +/* +** Texture Header State + */ + +#define NVB097_TEXHEAD0_COMPONENT_SIZES 5:0 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R32_G32_B32_A32 0x00000001 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R32_G32_B32 0x00000002 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R16_G16_B16_A16 0x00000003 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R32_G32 0x00000004 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R32_B24G8 0x00000005 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_X8B8G8R8 0x00000007 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_A8B8G8R8 0x00000008 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_A2B10G10R10 0x00000009 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R16_G16 0x0000000c +#define NVB097_TEXHEAD0_COMPONENT_SIZES_G8R24 0x0000000d +#define NVB097_TEXHEAD0_COMPONENT_SIZES_G24R8 0x0000000e +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R32 0x0000000f +#define NVB097_TEXHEAD0_COMPONENT_SIZES_A4B4G4R4 0x00000012 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_A5B5G5R1 0x00000013 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_A1B5G5R5 0x00000014 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_B5G6R5 0x00000015 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_B6G5R5 0x00000016 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_G8R8 0x00000018 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R16 0x0000001b +#define NVB097_TEXHEAD0_COMPONENT_SIZES_Y8_VIDEO 0x0000001c +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R8 0x0000001d +#define NVB097_TEXHEAD0_COMPONENT_SIZES_G4R4 0x0000001e +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R1 0x0000001f +#define NVB097_TEXHEAD0_COMPONENT_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_BF10GF11RF11 0x00000021 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_G8B8G8R8 0x00000022 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_B8G8R8G8 0x00000023 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_DXT1 0x00000024 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_DXT23 0x00000025 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_DXT45 0x00000026 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_DXN1 0x00000027 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_DXN2 0x00000028 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_BC6H_SF16 0x00000010 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_BC6H_UF16 0x00000011 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_BC7U 0x00000017 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ETC2_RGB 0x00000006 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ETC2_RGBA 0x0000000b +#define NVB097_TEXHEAD0_COMPONENT_SIZES_EAC 0x00000019 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_EACX2 0x0000001a +#define NVB097_TEXHEAD0_COMPONENT_SIZES_Z24S8 0x00000029 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_X8Z24 0x0000002a +#define NVB097_TEXHEAD0_COMPONENT_SIZES_S8Z24 0x0000002b +#define NVB097_TEXHEAD0_COMPONENT_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVB097_TEXHEAD0_COMPONENT_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVB097_TEXHEAD0_COMPONENT_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32 0x0000002f +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X24S8 0x00000030 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_Z16 0x0000003a +#define NVB097_TEXHEAD0_COMPONENT_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVB097_TEXHEAD0_COMPONENT_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVB097_TEXHEAD0_COMPONENT_SIZES_CS_BITFIELD_SIZE 0x0000003f +#define NVB097_TEXHEAD0_R_DATA_TYPE 8:6 +#define NVB097_TEXHEAD0_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD0_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD0_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD0_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD0_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD0_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD0_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD0_G_DATA_TYPE 11:9 +#define NVB097_TEXHEAD0_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD0_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD0_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD0_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD0_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD0_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD0_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD0_B_DATA_TYPE 14:12 +#define NVB097_TEXHEAD0_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD0_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD0_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD0_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD0_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD0_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD0_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD0_A_DATA_TYPE 17:15 +#define NVB097_TEXHEAD0_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD0_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD0_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD0_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD0_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD0_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD0_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD0_X_SOURCE 20:18 +#define NVB097_TEXHEAD0_X_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD0_X_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD0_X_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD0_X_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD0_X_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD0_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD0_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD0_Y_SOURCE 23:21 +#define NVB097_TEXHEAD0_Y_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD0_Y_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD0_Y_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD0_Y_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD0_Y_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD0_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD0_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD0_Z_SOURCE 26:24 +#define NVB097_TEXHEAD0_Z_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD0_Z_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD0_Z_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD0_Z_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD0_Z_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD0_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD0_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD0_W_SOURCE 29:27 +#define NVB097_TEXHEAD0_W_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD0_W_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD0_W_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD0_W_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD0_W_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD0_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD0_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD0_PACK_COMPONENTS 30:30 +#define NVB097_TEXHEAD0_USE_COMPONENT_SIZES_EXTENDED 31:31 +#define NVB097_TEXHEAD1_OFFSET_LOWER 31:0 +#define NVB097_TEXHEAD2_OFFSET_UPPER 7:0 +#define NVB097_TEXHEAD2_ANISO_SPREAD_MAX_LOG2_L_S_B 9:8 +#define NVB097_TEXHEAD2_S_R_G_B_CONVERSION 10:10 +#define NVB097_TEXHEAD2_ANISO_SPREAD_MAX_LOG2_M_S_B 11:11 +#define NVB097_TEXHEAD2_LOD_ANISO_QUALITY2 12:12 +#define NVB097_TEXHEAD2_COLOR_KEY_OP 13:13 +#define NVB097_TEXHEAD2_TEXTURE_TYPE 17:14 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVB097_TEXHEAD2_MEMORY_LAYOUT 18:18 +#define NVB097_TEXHEAD2_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB097_TEXHEAD2_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_WIDTH 21:19 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_HEIGHT 24:22 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_DEPTH 27:25 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEAD2_SECTOR_PROMOTION 29:28 +#define NVB097_TEXHEAD2_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVB097_TEXHEAD2_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVB097_TEXHEAD2_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVB097_TEXHEAD2_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVB097_TEXHEAD2_BORDER_SOURCE 30:30 +#define NVB097_TEXHEAD2_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVB097_TEXHEAD2_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVB097_TEXHEAD2_NORMALIZED_COORDS 31:31 +#define NVB097_TEXHEAD3_PITCH 19:0 +#define NVB097_TEXHEAD3_LOD_ANISO_QUALITY 20:20 +#define NVB097_TEXHEAD3_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD3_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD3_LOD_ISO_QUALITY 21:21 +#define NVB097_TEXHEAD3_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD3_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD3_ANISO_COARSE_SPREAD_MODIFIER 23:22 +#define NVB097_TEXHEAD3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD3_ANISO_SPREAD_SCALE 28:24 +#define NVB097_TEXHEAD3_USE_HEADER_OPT_CONTROL 29:29 +#define NVB097_TEXHEAD3_RESERVED3A 30:30 +#define NVB097_TEXHEAD3_RESERVED3B 31:31 +#define NVB097_TEXHEAD4_WIDTH 29:0 +#define NVB097_TEXHEAD4_DEPTH_TEXTURE 30:30 +#define NVB097_TEXHEAD4_USE_TEXTURE_HEADER_VERSION2 31:31 +#define NVB097_TEXHEAD5_HEIGHT 15:0 +#define NVB097_TEXHEAD5_DEPTH 27:16 +#define NVB097_TEXHEAD5_MAX_MIP_LEVEL 31:28 +#define NVB097_TEXHEAD6_TRILIN_OPT 4:0 +#define NVB097_TEXHEAD6_MIP_LOD_BIAS 17:5 +#define NVB097_TEXHEAD6_RESERVED6A 18:18 +#define NVB097_TEXHEAD6_ANISO_BIAS 22:19 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_FUNC 24:23 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD6_ANISO_COARSE_SPREAD_FUNC 26:25 +#define NVB097_TEXHEAD6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY 29:27 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_MODIFIER 31:30 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD7_COLOR_KEY_VALUE 31:0 + + +/* +** Texture Header State Blocklinear + */ + +#define NVB097_TEXHEAD_BL_COMPONENTS MW(6:0) +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R32 0x0000000f +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R16 0x0000001b +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R8 0x0000001d +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R1 0x0000001f +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_EAC 0x00000019 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_Z16 0x0000003a +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVB097_TEXHEAD_BL_R_DATA_TYPE MW(9:7) +#define NVB097_TEXHEAD_BL_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_BL_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_BL_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_BL_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_BL_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_BL_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_BL_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BL_G_DATA_TYPE MW(12:10) +#define NVB097_TEXHEAD_BL_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_BL_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_BL_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_BL_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_BL_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_BL_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_BL_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BL_B_DATA_TYPE MW(15:13) +#define NVB097_TEXHEAD_BL_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_BL_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_BL_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_BL_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_BL_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_BL_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_BL_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BL_A_DATA_TYPE MW(18:16) +#define NVB097_TEXHEAD_BL_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_BL_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_BL_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_BL_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_BL_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_BL_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_BL_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BL_X_SOURCE MW(21:19) +#define NVB097_TEXHEAD_BL_X_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_BL_X_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_BL_X_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_BL_X_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_BL_X_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_BL_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_BL_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BL_Y_SOURCE MW(24:22) +#define NVB097_TEXHEAD_BL_Y_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_BL_Y_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_BL_Y_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_BL_Y_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_BL_Y_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_BL_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_BL_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BL_Z_SOURCE MW(27:25) +#define NVB097_TEXHEAD_BL_Z_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_BL_Z_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_BL_Z_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_BL_Z_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_BL_Z_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_BL_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_BL_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BL_W_SOURCE MW(30:28) +#define NVB097_TEXHEAD_BL_W_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_BL_W_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_BL_W_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_BL_W_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_BL_W_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_BL_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_BL_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BL_PACK_COMPONENTS MW(31:31) +#define NVB097_TEXHEAD_BL_RESERVED1Y MW(36:32) +#define NVB097_TEXHEAD_BL_GOB_DEPTH_OFFSET MW(38:37) +#define NVB097_TEXHEAD_BL_RESERVED1X MW(40:39) +#define NVB097_TEXHEAD_BL_ADDRESS_BITS31TO9 MW(63:41) +#define NVB097_TEXHEAD_BL_ADDRESS_BITS47TO32 MW(79:64) +#define NVB097_TEXHEAD_BL_RESERVED_ADDRESS MW(84:80) +#define NVB097_TEXHEAD_BL_HEADER_VERSION MW(87:85) +#define NVB097_TEXHEAD_BL_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVB097_TEXHEAD_BL_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVB097_TEXHEAD_BL_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVB097_TEXHEAD_BL_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVB097_TEXHEAD_BL_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVB097_TEXHEAD_BL_RESERVED_HEADER_VERSION MW(88:88) +#define NVB097_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVB097_TEXHEAD_BL_RESERVED2A MW(95:93) +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_WIDTH MW(98:96) +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT MW(101:99) +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH MW(104:102) +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEAD_BL_SPARSE_ENABLE MW(105:105) +#define NVB097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS MW(108:106) +#define NVB097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVB097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEAD_BL_GOB3D MW(109:109) +#define NVB097_TEXHEAD_BL_USE_ARRAY_TILE_ALIGNMENT MW(110:110) +#define NVB097_TEXHEAD_BL_RESERVED3Z MW(111:111) +#define NVB097_TEXHEAD_BL_LOD_ANISO_QUALITY2 MW(112:112) +#define NVB097_TEXHEAD_BL_LOD_ANISO_QUALITY MW(113:113) +#define NVB097_TEXHEAD_BL_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD_BL_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD_BL_LOD_ISO_QUALITY MW(114:114) +#define NVB097_TEXHEAD_BL_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD_BL_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD_BL_ANISO_SPREAD_SCALE MW(121:117) +#define NVB097_TEXHEAD_BL_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVB097_TEXHEAD_BL_DEPTH_TEXTURE MW(123:123) +#define NVB097_TEXHEAD_BL_MAX_MIP_LEVEL MW(127:124) +#define NVB097_TEXHEAD_BL_WIDTH_MINUS_ONE MW(143:128) +#define NVB097_TEXHEAD_BL_RESERVED4A MW(146:144) +#define NVB097_TEXHEAD_BL_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVB097_TEXHEAD_BL_S_R_G_B_CONVERSION MW(150:150) +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE MW(154:151) +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVB097_TEXHEAD_BL_SECTOR_PROMOTION MW(156:155) +#define NVB097_TEXHEAD_BL_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVB097_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVB097_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVB097_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVB097_TEXHEAD_BL_BORDER_SIZE MW(159:157) +#define NVB097_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVB097_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVB097_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVB097_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVB097_TEXHEAD_BL_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVB097_TEXHEAD_BL_HEIGHT_MINUS_ONE MW(175:160) +#define NVB097_TEXHEAD_BL_DEPTH_MINUS_ONE MW(189:176) +#define NVB097_TEXHEAD_BL_RESERVED5A MW(190:190) +#define NVB097_TEXHEAD_BL_NORMALIZED_COORDS MW(191:191) +#define NVB097_TEXHEAD_BL_RESERVED6Y MW(192:192) +#define NVB097_TEXHEAD_BL_TRILIN_OPT MW(197:193) +#define NVB097_TEXHEAD_BL_MIP_LOD_BIAS MW(210:198) +#define NVB097_TEXHEAD_BL_ANISO_BIAS MW(214:211) +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY MW(221:219) +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD_BL_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVB097_TEXHEAD_BL_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT MW(235:232) +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1_CENTER 0x0000000c +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_CENTER 0x0000000d +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_CENTER 0x0000000e +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X4_REGULAR 0x0000000f +#define NVB097_TEXHEAD_BL_MIN_LOD_CLAMP MW(247:236) +#define NVB097_TEXHEAD_BL_RESERVED7Y MW(255:248) + + +/* +** Texture Header State Blocklinear Color Key + */ + +#define NVB097_TEXHEAD_BLCK_COMPONENTS MW(6:0) +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVB097_TEXHEAD_BLCK_R_DATA_TYPE MW(9:7) +#define NVB097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BLCK_G_DATA_TYPE MW(12:10) +#define NVB097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BLCK_B_DATA_TYPE MW(15:13) +#define NVB097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BLCK_A_DATA_TYPE MW(18:16) +#define NVB097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BLCK_X_SOURCE MW(21:19) +#define NVB097_TEXHEAD_BLCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_BLCK_X_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_BLCK_X_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_BLCK_X_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_BLCK_X_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_BLCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_BLCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BLCK_Y_SOURCE MW(24:22) +#define NVB097_TEXHEAD_BLCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_BLCK_Y_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_BLCK_Y_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_BLCK_Y_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_BLCK_Y_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_BLCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_BLCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BLCK_Z_SOURCE MW(27:25) +#define NVB097_TEXHEAD_BLCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_BLCK_Z_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_BLCK_Z_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_BLCK_Z_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_BLCK_Z_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_BLCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_BLCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BLCK_W_SOURCE MW(30:28) +#define NVB097_TEXHEAD_BLCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_BLCK_W_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_BLCK_W_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_BLCK_W_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_BLCK_W_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_BLCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_BLCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BLCK_PACK_COMPONENTS MW(31:31) +#define NVB097_TEXHEAD_BLCK_RESERVED1Y MW(36:32) +#define NVB097_TEXHEAD_BLCK_GOB_DEPTH_OFFSET MW(38:37) +#define NVB097_TEXHEAD_BLCK_RESERVED1X MW(40:39) +#define NVB097_TEXHEAD_BLCK_ADDRESS_BITS31TO9 MW(63:41) +#define NVB097_TEXHEAD_BLCK_ADDRESS_BITS47TO32 MW(79:64) +#define NVB097_TEXHEAD_BLCK_RESERVED_ADDRESS MW(84:80) +#define NVB097_TEXHEAD_BLCK_HEADER_VERSION MW(87:85) +#define NVB097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVB097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVB097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVB097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVB097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVB097_TEXHEAD_BLCK_RESERVED_HEADER_VERSION MW(88:88) +#define NVB097_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVB097_TEXHEAD_BLCK_RESERVED2A MW(95:93) +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_WIDTH MW(98:96) +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT MW(101:99) +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH MW(104:102) +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEAD_BLCK_SPARSE_ENABLE MW(105:105) +#define NVB097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS MW(108:106) +#define NVB097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVB097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEAD_BLCK_GOB3D MW(109:109) +#define NVB097_TEXHEAD_BLCK_USE_ARRAY_TILE_ALIGNMENT MW(110:110) +#define NVB097_TEXHEAD_BLCK_RESERVED3Z MW(111:111) +#define NVB097_TEXHEAD_BLCK_LOD_ANISO_QUALITY2 MW(112:112) +#define NVB097_TEXHEAD_BLCK_LOD_ANISO_QUALITY MW(113:113) +#define NVB097_TEXHEAD_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD_BLCK_LOD_ISO_QUALITY MW(114:114) +#define NVB097_TEXHEAD_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD_BLCK_ANISO_SPREAD_SCALE MW(121:117) +#define NVB097_TEXHEAD_BLCK_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVB097_TEXHEAD_BLCK_DEPTH_TEXTURE MW(123:123) +#define NVB097_TEXHEAD_BLCK_MAX_MIP_LEVEL MW(127:124) +#define NVB097_TEXHEAD_BLCK_WIDTH_MINUS_ONE MW(143:128) +#define NVB097_TEXHEAD_BLCK_RESERVED4A MW(146:144) +#define NVB097_TEXHEAD_BLCK_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVB097_TEXHEAD_BLCK_S_R_G_B_CONVERSION MW(150:150) +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE MW(154:151) +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVB097_TEXHEAD_BLCK_SECTOR_PROMOTION MW(156:155) +#define NVB097_TEXHEAD_BLCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVB097_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVB097_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVB097_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVB097_TEXHEAD_BLCK_BORDER_SIZE MW(159:157) +#define NVB097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVB097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVB097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVB097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVB097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVB097_TEXHEAD_BLCK_HEIGHT_MINUS_ONE MW(175:160) +#define NVB097_TEXHEAD_BLCK_DEPTH_MINUS_ONE MW(189:176) +#define NVB097_TEXHEAD_BLCK_RESERVED5A MW(190:190) +#define NVB097_TEXHEAD_BLCK_NORMALIZED_COORDS MW(191:191) +#define NVB097_TEXHEAD_BLCK_COLOR_KEY_OP MW(192:192) +#define NVB097_TEXHEAD_BLCK_TRILIN_OPT MW(197:193) +#define NVB097_TEXHEAD_BLCK_MIP_LOD_BIAS MW(210:198) +#define NVB097_TEXHEAD_BLCK_ANISO_BIAS MW(214:211) +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY MW(221:219) +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD_BLCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Header State One-D Buffer + */ + +#define NVB097_TEXHEAD_1D_COMPONENTS MW(6:0) +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R32 0x0000000f +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R16 0x0000001b +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R8 0x0000001d +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R1 0x0000001f +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_EAC 0x00000019 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_Z16 0x0000003a +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVB097_TEXHEAD_1D_R_DATA_TYPE MW(9:7) +#define NVB097_TEXHEAD_1D_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_1D_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_1D_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_1D_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_1D_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_1D_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_1D_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_1D_G_DATA_TYPE MW(12:10) +#define NVB097_TEXHEAD_1D_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_1D_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_1D_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_1D_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_1D_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_1D_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_1D_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_1D_B_DATA_TYPE MW(15:13) +#define NVB097_TEXHEAD_1D_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_1D_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_1D_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_1D_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_1D_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_1D_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_1D_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_1D_A_DATA_TYPE MW(18:16) +#define NVB097_TEXHEAD_1D_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_1D_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_1D_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_1D_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_1D_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_1D_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_1D_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_1D_X_SOURCE MW(21:19) +#define NVB097_TEXHEAD_1D_X_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_1D_X_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_1D_X_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_1D_X_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_1D_X_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_1D_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_1D_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_1D_Y_SOURCE MW(24:22) +#define NVB097_TEXHEAD_1D_Y_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_1D_Y_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_1D_Y_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_1D_Y_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_1D_Y_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_1D_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_1D_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_1D_Z_SOURCE MW(27:25) +#define NVB097_TEXHEAD_1D_Z_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_1D_Z_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_1D_Z_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_1D_Z_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_1D_Z_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_1D_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_1D_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_1D_W_SOURCE MW(30:28) +#define NVB097_TEXHEAD_1D_W_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_1D_W_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_1D_W_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_1D_W_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_1D_W_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_1D_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_1D_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_1D_PACK_COMPONENTS MW(31:31) +#define NVB097_TEXHEAD_1D_ADDRESS_BITS31TO0 MW(63:32) +#define NVB097_TEXHEAD_1D_ADDRESS_BITS47TO32 MW(79:64) +#define NVB097_TEXHEAD_1D_RESERVED_ADDRESS MW(84:80) +#define NVB097_TEXHEAD_1D_HEADER_VERSION MW(87:85) +#define NVB097_TEXHEAD_1D_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVB097_TEXHEAD_1D_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVB097_TEXHEAD_1D_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVB097_TEXHEAD_1D_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVB097_TEXHEAD_1D_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVB097_TEXHEAD_1D_RESERVED_HEADER_VERSION MW(88:88) +#define NVB097_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVB097_TEXHEAD_1D_RESERVED2A MW(95:93) +#define NVB097_TEXHEAD_1D_WIDTH_MINUS_ONE_BITS31TO16 MW(111:96) +#define NVB097_TEXHEAD_1D_RESERVED3X MW(127:112) +#define NVB097_TEXHEAD_1D_WIDTH_MINUS_ONE_BITS15TO0 MW(143:128) +#define NVB097_TEXHEAD_1D_RESERVED4A MW(146:144) +#define NVB097_TEXHEAD_1D_RESERVED4X MW(149:147) +#define NVB097_TEXHEAD_1D_S_R_G_B_CONVERSION MW(150:150) +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE MW(154:151) +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVB097_TEXHEAD_1D_SECTOR_PROMOTION MW(156:155) +#define NVB097_TEXHEAD_1D_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVB097_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVB097_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVB097_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVB097_TEXHEAD_1D_RESERVED4Y MW(159:157) +#define NVB097_TEXHEAD_1D_RESERVED5X MW(189:160) +#define NVB097_TEXHEAD_1D_RESERVED5A MW(190:190) +#define NVB097_TEXHEAD_1D_RESERVED5Y MW(191:191) +#define NVB097_TEXHEAD_1D_RESERVED6X MW(223:192) +#define NVB097_TEXHEAD_1D_RESERVED7X MW(255:224) + + +/* +** Texture Header State Pitch + */ + +#define NVB097_TEXHEAD_PITCH_COMPONENTS MW(6:0) +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32 0x0000000f +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R16 0x0000001b +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R8 0x0000001d +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R1 0x0000001f +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_EAC 0x00000019 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_Z16 0x0000003a +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVB097_TEXHEAD_PITCH_R_DATA_TYPE MW(9:7) +#define NVB097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCH_G_DATA_TYPE MW(12:10) +#define NVB097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCH_B_DATA_TYPE MW(15:13) +#define NVB097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCH_A_DATA_TYPE MW(18:16) +#define NVB097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCH_X_SOURCE MW(21:19) +#define NVB097_TEXHEAD_PITCH_X_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_PITCH_X_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_PITCH_X_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_PITCH_X_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_PITCH_X_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_PITCH_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_PITCH_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCH_Y_SOURCE MW(24:22) +#define NVB097_TEXHEAD_PITCH_Y_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_PITCH_Y_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_PITCH_Y_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_PITCH_Y_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_PITCH_Y_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_PITCH_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_PITCH_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCH_Z_SOURCE MW(27:25) +#define NVB097_TEXHEAD_PITCH_Z_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_PITCH_Z_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_PITCH_Z_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_PITCH_Z_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_PITCH_Z_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_PITCH_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_PITCH_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCH_W_SOURCE MW(30:28) +#define NVB097_TEXHEAD_PITCH_W_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_PITCH_W_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_PITCH_W_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_PITCH_W_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_PITCH_W_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_PITCH_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_PITCH_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCH_PACK_COMPONENTS MW(31:31) +#define NVB097_TEXHEAD_PITCH_RESERVED1A MW(36:32) +#define NVB097_TEXHEAD_PITCH_ADDRESS_BITS31TO5 MW(63:37) +#define NVB097_TEXHEAD_PITCH_ADDRESS_BITS47TO32 MW(79:64) +#define NVB097_TEXHEAD_PITCH_RESERVED_ADDRESS MW(84:80) +#define NVB097_TEXHEAD_PITCH_HEADER_VERSION MW(87:85) +#define NVB097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVB097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVB097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVB097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVB097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVB097_TEXHEAD_PITCH_RESERVED_HEADER_VERSION MW(88:88) +#define NVB097_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVB097_TEXHEAD_PITCH_RESERVED2A MW(95:93) +#define NVB097_TEXHEAD_PITCH_PITCH_BITS20TO5 MW(111:96) +#define NVB097_TEXHEAD_PITCH_LOD_ANISO_QUALITY2 MW(112:112) +#define NVB097_TEXHEAD_PITCH_LOD_ANISO_QUALITY MW(113:113) +#define NVB097_TEXHEAD_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD_PITCH_LOD_ISO_QUALITY MW(114:114) +#define NVB097_TEXHEAD_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD_PITCH_ANISO_SPREAD_SCALE MW(121:117) +#define NVB097_TEXHEAD_PITCH_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVB097_TEXHEAD_PITCH_DEPTH_TEXTURE MW(123:123) +#define NVB097_TEXHEAD_PITCH_MAX_MIP_LEVEL MW(127:124) +#define NVB097_TEXHEAD_PITCH_WIDTH_MINUS_ONE MW(143:128) +#define NVB097_TEXHEAD_PITCH_RESERVED4A MW(146:144) +#define NVB097_TEXHEAD_PITCH_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVB097_TEXHEAD_PITCH_S_R_G_B_CONVERSION MW(150:150) +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE MW(154:151) +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVB097_TEXHEAD_PITCH_SECTOR_PROMOTION MW(156:155) +#define NVB097_TEXHEAD_PITCH_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVB097_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVB097_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVB097_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVB097_TEXHEAD_PITCH_BORDER_SIZE MW(159:157) +#define NVB097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVB097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVB097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVB097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVB097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVB097_TEXHEAD_PITCH_HEIGHT_MINUS_ONE MW(175:160) +#define NVB097_TEXHEAD_PITCH_DEPTH_MINUS_ONE MW(189:176) +#define NVB097_TEXHEAD_PITCH_RESERVED5A MW(190:190) +#define NVB097_TEXHEAD_PITCH_NORMALIZED_COORDS MW(191:191) +#define NVB097_TEXHEAD_PITCH_RESERVED6Y MW(192:192) +#define NVB097_TEXHEAD_PITCH_TRILIN_OPT MW(197:193) +#define NVB097_TEXHEAD_PITCH_MIP_LOD_BIAS MW(210:198) +#define NVB097_TEXHEAD_PITCH_ANISO_BIAS MW(214:211) +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY MW(221:219) +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD_PITCH_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVB097_TEXHEAD_PITCH_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT MW(235:232) +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1_CENTER 0x0000000c +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_CENTER 0x0000000d +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_CENTER 0x0000000e +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X4_REGULAR 0x0000000f +#define NVB097_TEXHEAD_PITCH_MIN_LOD_CLAMP MW(247:236) +#define NVB097_TEXHEAD_PITCH_RESERVED7Y MW(255:248) + + +/* +** Texture Header State Pitch Color Key + */ + +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS MW(6:0) +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVB097_TEXHEAD_PITCHCK_R_DATA_TYPE MW(9:7) +#define NVB097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_G_DATA_TYPE MW(12:10) +#define NVB097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_B_DATA_TYPE MW(15:13) +#define NVB097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_A_DATA_TYPE MW(18:16) +#define NVB097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_X_SOURCE MW(21:19) +#define NVB097_TEXHEAD_PITCHCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_X_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_X_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_X_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_X_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_Y_SOURCE MW(24:22) +#define NVB097_TEXHEAD_PITCHCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_Y_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_Y_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_Y_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_Y_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_Z_SOURCE MW(27:25) +#define NVB097_TEXHEAD_PITCHCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_Z_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_Z_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_Z_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_Z_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_W_SOURCE MW(30:28) +#define NVB097_TEXHEAD_PITCHCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_W_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_W_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_W_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_W_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_PACK_COMPONENTS MW(31:31) +#define NVB097_TEXHEAD_PITCHCK_RESERVED1A MW(36:32) +#define NVB097_TEXHEAD_PITCHCK_ADDRESS_BITS31TO5 MW(63:37) +#define NVB097_TEXHEAD_PITCHCK_ADDRESS_BITS47TO32 MW(79:64) +#define NVB097_TEXHEAD_PITCHCK_RESERVED_ADDRESS MW(84:80) +#define NVB097_TEXHEAD_PITCHCK_HEADER_VERSION MW(87:85) +#define NVB097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_RESERVED_HEADER_VERSION MW(88:88) +#define NVB097_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVB097_TEXHEAD_PITCHCK_RESERVED2A MW(95:93) +#define NVB097_TEXHEAD_PITCHCK_PITCH_BITS20TO5 MW(111:96) +#define NVB097_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY2 MW(112:112) +#define NVB097_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY MW(113:113) +#define NVB097_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_LOD_ISO_QUALITY MW(114:114) +#define NVB097_TEXHEAD_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_ANISO_SPREAD_SCALE MW(121:117) +#define NVB097_TEXHEAD_PITCHCK_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVB097_TEXHEAD_PITCHCK_DEPTH_TEXTURE MW(123:123) +#define NVB097_TEXHEAD_PITCHCK_MAX_MIP_LEVEL MW(127:124) +#define NVB097_TEXHEAD_PITCHCK_WIDTH_MINUS_ONE MW(143:128) +#define NVB097_TEXHEAD_PITCHCK_RESERVED4A MW(146:144) +#define NVB097_TEXHEAD_PITCHCK_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVB097_TEXHEAD_PITCHCK_S_R_G_B_CONVERSION MW(150:150) +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE MW(154:151) +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVB097_TEXHEAD_PITCHCK_SECTOR_PROMOTION MW(156:155) +#define NVB097_TEXHEAD_PITCHCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_BORDER_SIZE MW(159:157) +#define NVB097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_HEIGHT_MINUS_ONE MW(175:160) +#define NVB097_TEXHEAD_PITCHCK_DEPTH_MINUS_ONE MW(189:176) +#define NVB097_TEXHEAD_PITCHCK_RESERVED5A MW(190:190) +#define NVB097_TEXHEAD_PITCHCK_NORMALIZED_COORDS MW(191:191) +#define NVB097_TEXHEAD_PITCHCK_COLOR_KEY_OP MW(192:192) +#define NVB097_TEXHEAD_PITCHCK_TRILIN_OPT MW(197:193) +#define NVB097_TEXHEAD_PITCHCK_MIP_LOD_BIAS MW(210:198) +#define NVB097_TEXHEAD_PITCHCK_ANISO_BIAS MW(214:211) +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY MW(221:219) +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Header State, Version 2 + */ + +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES 5:0 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R32_G32_B32_A32 0x00000001 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R32_G32_B32 0x00000002 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R16_G16_B16_A16 0x00000003 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R32_G32 0x00000004 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R32_B24G8 0x00000005 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_X8B8G8R8 0x00000007 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_A8B8G8R8 0x00000008 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_A2B10G10R10 0x00000009 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R16_G16 0x0000000c +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_G8R24 0x0000000d +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_G24R8 0x0000000e +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R32 0x0000000f +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_A4B4G4R4 0x00000012 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_A5B5G5R1 0x00000013 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_A1B5G5R5 0x00000014 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_B5G6R5 0x00000015 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_B6G5R5 0x00000016 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_G8R8 0x00000018 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R16 0x0000001b +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_Y8_VIDEO 0x0000001c +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R8 0x0000001d +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_G4R4 0x0000001e +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R1 0x0000001f +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_BF10GF11RF11 0x00000021 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_G8B8G8R8 0x00000022 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_B8G8R8G8 0x00000023 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_DXT1 0x00000024 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_DXT23 0x00000025 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_DXT45 0x00000026 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_DXN1 0x00000027 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_DXN2 0x00000028 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_BC6H_SF16 0x00000010 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_BC6H_UF16 0x00000011 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_BC7U 0x00000017 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ETC2_RGB 0x00000006 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ETC2_RGBA 0x0000000b +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_EAC 0x00000019 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_EACX2 0x0000001a +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_Z24S8 0x00000029 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_X8Z24 0x0000002a +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_S8Z24 0x0000002b +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32 0x0000002f +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X24S8 0x00000030 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_Z16 0x0000003a +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_CS_BITFIELD_SIZE 0x0000003f +#define NVB097_TEXHEADV2_0_R_DATA_TYPE 8:6 +#define NVB097_TEXHEADV2_0_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEADV2_0_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEADV2_0_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEADV2_0_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEADV2_0_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEADV2_0_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEADV2_0_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEADV2_0_G_DATA_TYPE 11:9 +#define NVB097_TEXHEADV2_0_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEADV2_0_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEADV2_0_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEADV2_0_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEADV2_0_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEADV2_0_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEADV2_0_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEADV2_0_B_DATA_TYPE 14:12 +#define NVB097_TEXHEADV2_0_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEADV2_0_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEADV2_0_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEADV2_0_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEADV2_0_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEADV2_0_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEADV2_0_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEADV2_0_A_DATA_TYPE 17:15 +#define NVB097_TEXHEADV2_0_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEADV2_0_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEADV2_0_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEADV2_0_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEADV2_0_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEADV2_0_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEADV2_0_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEADV2_0_X_SOURCE 20:18 +#define NVB097_TEXHEADV2_0_X_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEADV2_0_X_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEADV2_0_X_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEADV2_0_X_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEADV2_0_X_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEADV2_0_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEADV2_0_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEADV2_0_Y_SOURCE 23:21 +#define NVB097_TEXHEADV2_0_Y_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEADV2_0_Y_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEADV2_0_Y_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEADV2_0_Y_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEADV2_0_Y_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEADV2_0_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEADV2_0_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEADV2_0_Z_SOURCE 26:24 +#define NVB097_TEXHEADV2_0_Z_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEADV2_0_Z_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEADV2_0_Z_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEADV2_0_Z_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEADV2_0_Z_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEADV2_0_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEADV2_0_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEADV2_0_W_SOURCE 29:27 +#define NVB097_TEXHEADV2_0_W_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEADV2_0_W_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEADV2_0_W_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEADV2_0_W_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEADV2_0_W_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEADV2_0_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEADV2_0_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEADV2_0_PACK_COMPONENTS 30:30 +#define NVB097_TEXHEADV2_0_USE_COMPONENT_SIZES_EXTENDED 31:31 +#define NVB097_TEXHEADV2_1_OFFSET_LOWER 31:0 +#define NVB097_TEXHEADV2_2_OFFSET_UPPER 7:0 +#define NVB097_TEXHEADV2_2_ANISO_SPREAD_MAX_LOG2_L_S_B 9:8 +#define NVB097_TEXHEADV2_2_S_R_G_B_CONVERSION 10:10 +#define NVB097_TEXHEADV2_2_ANISO_SPREAD_MAX_LOG2_M_S_B 11:11 +#define NVB097_TEXHEADV2_2_LOD_ANISO_QUALITY2 12:12 +#define NVB097_TEXHEADV2_2_COLOR_KEY_OP 13:13 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE 17:14 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVB097_TEXHEADV2_2_MEMORY_LAYOUT 18:18 +#define NVB097_TEXHEADV2_2_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB097_TEXHEADV2_2_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_WIDTH 21:19 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_HEIGHT 24:22 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_DEPTH 27:25 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEADV2_2_SECTOR_PROMOTION 29:28 +#define NVB097_TEXHEADV2_2_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVB097_TEXHEADV2_2_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVB097_TEXHEADV2_2_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVB097_TEXHEADV2_2_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVB097_TEXHEADV2_2_BORDER_SOURCE 30:30 +#define NVB097_TEXHEADV2_2_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVB097_TEXHEADV2_2_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVB097_TEXHEADV2_2_NORMALIZED_COORDS 31:31 +#define NVB097_TEXHEADV2_3_PITCH 19:0 +#define NVB097_TEXHEADV2_3_LOD_ANISO_QUALITY 20:20 +#define NVB097_TEXHEADV2_3_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEADV2_3_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEADV2_3_LOD_ISO_QUALITY 21:21 +#define NVB097_TEXHEADV2_3_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEADV2_3_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEADV2_3_ANISO_COARSE_SPREAD_MODIFIER 23:22 +#define NVB097_TEXHEADV2_3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEADV2_3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEADV2_3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEADV2_3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEADV2_3_ANISO_SPREAD_SCALE 28:24 +#define NVB097_TEXHEADV2_3_USE_HEADER_OPT_CONTROL 29:29 +#define NVB097_TEXHEADV2_3_RESERVED3A 30:30 +#define NVB097_TEXHEADV2_3_RESERVED3B 31:31 +#define NVB097_TEXHEADV2_4_WIDTH 29:0 +#define NVB097_TEXHEADV2_4_DEPTH_TEXTURE 30:30 +#define NVB097_TEXHEADV2_4_USE_TEXTURE_HEADER_VERSION2 31:31 +#define NVB097_TEXHEADV2_5_HEIGHT 15:0 +#define NVB097_TEXHEADV2_5_DEPTH 27:16 +#define NVB097_TEXHEADV2_5_MAX_MIP_LEVEL 31:28 +#define NVB097_TEXHEADV2_6_TRILIN_OPT 4:0 +#define NVB097_TEXHEADV2_6_MIP_LOD_BIAS 17:5 +#define NVB097_TEXHEADV2_6_RESERVED6A 18:18 +#define NVB097_TEXHEADV2_6_ANISO_BIAS 22:19 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_FUNC 24:23 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEADV2_6_ANISO_COARSE_SPREAD_FUNC 26:25 +#define NVB097_TEXHEADV2_6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEADV2_6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEADV2_6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEADV2_6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY 29:27 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_MODIFIER 31:30 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEADV2_7_RES_VIEW_MIN_MIP_LEVEL 3:0 +#define NVB097_TEXHEADV2_7_RES_VIEW_MAX_MIP_LEVEL 7:4 +#define NVB097_TEXHEADV2_7_HEIGHT_MSB 8:8 +#define NVB097_TEXHEADV2_7_HEIGHT_MSB_RESERVED 11:9 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT 15:12 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_2X1_CENTER 0x0000000c +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_2X2_CENTER 0x0000000d +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_4X2_CENTER 0x0000000e +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_4X4_REGULAR 0x0000000f +#define NVB097_TEXHEADV2_7_MIN_LOD_CLAMP 27:16 +#define NVB097_TEXHEADV2_7_DEPTH_MSB 30:28 +#define NVB097_TEXHEADV2_7_RESERVED7A 31:31 + + +/* +** Texture Header State, Version 3 + */ + +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES 5:0 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_4X4 0x00000000 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_5X4 0x00000010 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_5X5 0x00000001 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_6X5 0x00000011 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_6X6 0x00000002 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_8X5 0x00000015 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_8X6 0x00000012 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_8X8 0x00000004 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_10X5 0x00000016 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_10X6 0x00000017 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_10X8 0x00000013 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_10X10 0x00000005 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_12X10 0x00000014 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_12X12 0x00000006 +#define NVB097_TEXHEADV3_0_R_DATA_TYPE 8:6 +#define NVB097_TEXHEADV3_0_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEADV3_0_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEADV3_0_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEADV3_0_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEADV3_0_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEADV3_0_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEADV3_0_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEADV3_0_G_DATA_TYPE 11:9 +#define NVB097_TEXHEADV3_0_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEADV3_0_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEADV3_0_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEADV3_0_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEADV3_0_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEADV3_0_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEADV3_0_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEADV3_0_B_DATA_TYPE 14:12 +#define NVB097_TEXHEADV3_0_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEADV3_0_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEADV3_0_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEADV3_0_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEADV3_0_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEADV3_0_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEADV3_0_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEADV3_0_A_DATA_TYPE 17:15 +#define NVB097_TEXHEADV3_0_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEADV3_0_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEADV3_0_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEADV3_0_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEADV3_0_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEADV3_0_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEADV3_0_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEADV3_0_X_SOURCE 20:18 +#define NVB097_TEXHEADV3_0_X_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEADV3_0_X_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEADV3_0_X_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEADV3_0_X_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEADV3_0_X_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEADV3_0_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEADV3_0_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEADV3_0_Y_SOURCE 23:21 +#define NVB097_TEXHEADV3_0_Y_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEADV3_0_Y_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEADV3_0_Y_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEADV3_0_Y_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEADV3_0_Y_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEADV3_0_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEADV3_0_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEADV3_0_Z_SOURCE 26:24 +#define NVB097_TEXHEADV3_0_Z_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEADV3_0_Z_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEADV3_0_Z_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEADV3_0_Z_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEADV3_0_Z_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEADV3_0_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEADV3_0_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEADV3_0_W_SOURCE 29:27 +#define NVB097_TEXHEADV3_0_W_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEADV3_0_W_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEADV3_0_W_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEADV3_0_W_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEADV3_0_W_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEADV3_0_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEADV3_0_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEADV3_0_PACK_COMPONENTS 30:30 +#define NVB097_TEXHEADV3_0_USE_COMPONENT_SIZES_EXTENDED 31:31 +#define NVB097_TEXHEADV3_1_OFFSET_LOWER 31:0 +#define NVB097_TEXHEADV3_2_OFFSET_UPPER 7:0 +#define NVB097_TEXHEADV3_2_ANISO_SPREAD_MAX_LOG2_L_S_B 9:8 +#define NVB097_TEXHEADV3_2_S_R_G_B_CONVERSION 10:10 +#define NVB097_TEXHEADV3_2_ANISO_SPREAD_MAX_LOG2_M_S_B 11:11 +#define NVB097_TEXHEADV3_2_LOD_ANISO_QUALITY2 12:12 +#define NVB097_TEXHEADV3_2_COLOR_KEY_OP 13:13 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE 17:14 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVB097_TEXHEADV3_2_MEMORY_LAYOUT 18:18 +#define NVB097_TEXHEADV3_2_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB097_TEXHEADV3_2_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_WIDTH 21:19 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_HEIGHT 24:22 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_DEPTH 27:25 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEADV3_2_SECTOR_PROMOTION 29:28 +#define NVB097_TEXHEADV3_2_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVB097_TEXHEADV3_2_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVB097_TEXHEADV3_2_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVB097_TEXHEADV3_2_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVB097_TEXHEADV3_2_BORDER_SOURCE 30:30 +#define NVB097_TEXHEADV3_2_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVB097_TEXHEADV3_2_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVB097_TEXHEADV3_2_NORMALIZED_COORDS 31:31 +#define NVB097_TEXHEADV3_3_PITCH 19:0 +#define NVB097_TEXHEADV3_3_LOD_ANISO_QUALITY 20:20 +#define NVB097_TEXHEADV3_3_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEADV3_3_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEADV3_3_LOD_ISO_QUALITY 21:21 +#define NVB097_TEXHEADV3_3_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEADV3_3_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEADV3_3_ANISO_COARSE_SPREAD_MODIFIER 23:22 +#define NVB097_TEXHEADV3_3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEADV3_3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEADV3_3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEADV3_3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEADV3_3_ANISO_SPREAD_SCALE 28:24 +#define NVB097_TEXHEADV3_3_USE_HEADER_OPT_CONTROL 29:29 +#define NVB097_TEXHEADV3_3_RESERVED3A 30:30 +#define NVB097_TEXHEADV3_3_RESERVED3B 31:31 +#define NVB097_TEXHEADV3_4_WIDTH 29:0 +#define NVB097_TEXHEADV3_4_DEPTH_TEXTURE 30:30 +#define NVB097_TEXHEADV3_4_USE_TEXTURE_HEADER_VERSION2 31:31 +#define NVB097_TEXHEADV3_5_HEIGHT 15:0 +#define NVB097_TEXHEADV3_5_DEPTH 27:16 +#define NVB097_TEXHEADV3_5_MAX_MIP_LEVEL 31:28 +#define NVB097_TEXHEADV3_6_TRILIN_OPT 4:0 +#define NVB097_TEXHEADV3_6_MIP_LOD_BIAS 17:5 +#define NVB097_TEXHEADV3_6_RESERVED6A 18:18 +#define NVB097_TEXHEADV3_6_ANISO_BIAS 22:19 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_FUNC 24:23 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEADV3_6_ANISO_COARSE_SPREAD_FUNC 26:25 +#define NVB097_TEXHEADV3_6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEADV3_6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEADV3_6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEADV3_6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY 29:27 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_MODIFIER 31:30 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEADV3_7_RES_VIEW_MIN_MIP_LEVEL 3:0 +#define NVB097_TEXHEADV3_7_RES_VIEW_MAX_MIP_LEVEL 7:4 +#define NVB097_TEXHEADV3_7_HEIGHT_MSB 8:8 +#define NVB097_TEXHEADV3_7_HEIGHT_MSB_RESERVED 11:9 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT 15:12 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_2X1_CENTER 0x0000000c +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_2X2_CENTER 0x0000000d +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_4X2_CENTER 0x0000000e +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_4X4_REGULAR 0x0000000f +#define NVB097_TEXHEADV3_7_MIN_LOD_CLAMP 27:16 +#define NVB097_TEXHEADV3_7_DEPTH_MSB 30:28 +#define NVB097_TEXHEADV3_7_RESERVED7A 31:31 + + +/* +** Texture Sampler State + */ + +#define NVB097_TEXSAMP0_ADDRESS_U 2:0 +#define NVB097_TEXSAMP0_ADDRESS_U_WRAP 0x00000000 +#define NVB097_TEXSAMP0_ADDRESS_U_MIRROR 0x00000001 +#define NVB097_TEXSAMP0_ADDRESS_U_CLAMP_TO_EDGE 0x00000002 +#define NVB097_TEXSAMP0_ADDRESS_U_BORDER 0x00000003 +#define NVB097_TEXSAMP0_ADDRESS_U_CLAMP_OGL 0x00000004 +#define NVB097_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVB097_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_BORDER 0x00000006 +#define NVB097_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVB097_TEXSAMP0_ADDRESS_V 5:3 +#define NVB097_TEXSAMP0_ADDRESS_V_WRAP 0x00000000 +#define NVB097_TEXSAMP0_ADDRESS_V_MIRROR 0x00000001 +#define NVB097_TEXSAMP0_ADDRESS_V_CLAMP_TO_EDGE 0x00000002 +#define NVB097_TEXSAMP0_ADDRESS_V_BORDER 0x00000003 +#define NVB097_TEXSAMP0_ADDRESS_V_CLAMP_OGL 0x00000004 +#define NVB097_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVB097_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_BORDER 0x00000006 +#define NVB097_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVB097_TEXSAMP0_ADDRESS_P 8:6 +#define NVB097_TEXSAMP0_ADDRESS_P_WRAP 0x00000000 +#define NVB097_TEXSAMP0_ADDRESS_P_MIRROR 0x00000001 +#define NVB097_TEXSAMP0_ADDRESS_P_CLAMP_TO_EDGE 0x00000002 +#define NVB097_TEXSAMP0_ADDRESS_P_BORDER 0x00000003 +#define NVB097_TEXSAMP0_ADDRESS_P_CLAMP_OGL 0x00000004 +#define NVB097_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVB097_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_BORDER 0x00000006 +#define NVB097_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVB097_TEXSAMP0_DEPTH_COMPARE 9:9 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC 12:10 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_NEVER 0x00000000 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_LESS 0x00000001 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_EQUAL 0x00000002 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_LEQUAL 0x00000003 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_GREATER 0x00000004 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_NOTEQUAL 0x00000005 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_GEQUAL 0x00000006 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_ALWAYS 0x00000007 +#define NVB097_TEXSAMP0_S_R_G_B_CONVERSION 13:13 +#define NVB097_TEXSAMP0_RESERVED0A 16:14 +#define NVB097_TEXSAMP0_RESERVED0B 19:17 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY 22:20 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVB097_TEXSAMP1_MAG_FILTER 2:0 +#define NVB097_TEXSAMP1_MAG_FILTER_MAG_POINT 0x00000001 +#define NVB097_TEXSAMP1_MAG_FILTER_MAG_LINEAR 0x00000002 +#define NVB097_TEXSAMP1_MAG_FILTER_VCAA_4_TAP 0x00000003 +#define NVB097_TEXSAMP1_MAG_FILTER_VCAA_8_TAP 0x00000004 +#define NVB097_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP 3:3 +#define NVB097_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP_INTEGER_AND_FRACTION 0x00000000 +#define NVB097_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP_INTEGER_ONLY 0x00000001 +#define NVB097_TEXSAMP1_MIN_FILTER 5:4 +#define NVB097_TEXSAMP1_MIN_FILTER_MIN_POINT 0x00000001 +#define NVB097_TEXSAMP1_MIN_FILTER_MIN_LINEAR 0x00000002 +#define NVB097_TEXSAMP1_MIN_FILTER_MIN_ANISO 0x00000003 +#define NVB097_TEXSAMP1_MIP_FILTER 7:6 +#define NVB097_TEXSAMP1_MIP_FILTER_MIP_NONE 0x00000001 +#define NVB097_TEXSAMP1_MIP_FILTER_MIP_POINT 0x00000002 +#define NVB097_TEXSAMP1_MIP_FILTER_MIP_LINEAR 0x00000003 +#define NVB097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING 9:8 +#define NVB097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_USE_WRAP 0x00000000 +#define NVB097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_OVERRIDE_WRAP 0x00000001 +#define NVB097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_AUTO_SPAN_SEAM 0x00000002 +#define NVB097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_AUTO_CROSS_SEAM 0x00000003 +#define NVB097_TEXSAMP1_MIP_LOD_BIAS 24:12 +#define NVB097_TEXSAMP1_FLOAT_COORD_NORMALIZATION 25:25 +#define NVB097_TEXSAMP1_FLOAT_COORD_NORMALIZATION_USE_HEADER_SETTING 0x00000000 +#define NVB097_TEXSAMP1_FLOAT_COORD_NORMALIZATION_FORCE_UNNORMALIZED_COORDS 0x00000001 +#define NVB097_TEXSAMP1_TRILIN_OPT 30:26 +#define NVB097_TEXSAMP2_MIN_LOD_CLAMP 11:0 +#define NVB097_TEXSAMP2_MAX_LOD_CLAMP 23:12 +#define NVB097_TEXSAMP2_S_R_G_B_BORDER_COLOR_R 31:24 +#define NVB097_TEXSAMP3_RESERVED12 11:0 +#define NVB097_TEXSAMP3_S_R_G_B_BORDER_COLOR_G 19:12 +#define NVB097_TEXSAMP3_S_R_G_B_BORDER_COLOR_B 27:20 +#define NVB097_TEXSAMP4_BORDER_COLOR_R 31:0 +#define NVB097_TEXSAMP5_BORDER_COLOR_G 31:0 +#define NVB097_TEXSAMP6_BORDER_COLOR_B 31:0 +#define NVB097_TEXSAMP7_BORDER_COLOR_A 31:0 + + + +#endif // #ifndef __CLB097TEX_H__ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clb0b0.h b/userspace/sdks/nv570/nvidia/inc/class/clb0b0.h new file mode 100644 index 0000000..030040c --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clb0b0.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "nvtypes.h" + +#ifndef _clb0b0_h_ +#define _clb0b0_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVB0B0_VIDEO_DECODER (0x0000B0B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clb0b0_h diff --git a/userspace/sdks/nv570/nvidia/inc/class/clb0b5.h b/userspace/sdks/nv570/nvidia/inc/class/clb0b5.h new file mode 100644 index 0000000..63fe695 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clb0b5.h @@ -0,0 +1,261 @@ +/******************************************************************************* + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clb0b5_h_ +#define _clb0b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define MAXWELL_DMA_COPY_A (0x0000B0B5) + +#define NVB0B5_NOP (0x00000100) +#define NVB0B5_NOP_PARAMETER 31:0 +#define NVB0B5_PM_TRIGGER (0x00000140) +#define NVB0B5_PM_TRIGGER_V 31:0 +#define NVB0B5_SET_SEMAPHORE_A (0x00000240) +#define NVB0B5_SET_SEMAPHORE_A_UPPER 7:0 +#define NVB0B5_SET_SEMAPHORE_B (0x00000244) +#define NVB0B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVB0B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVB0B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVB0B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVB0B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVB0B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVB0B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVB0B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVB0B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVB0B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVB0B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVB0B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVB0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVB0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVB0B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVB0B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVB0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVB0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVB0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVB0B5_SET_DST_PHYS_MODE (0x00000264) +#define NVB0B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVB0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVB0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVB0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVB0B5_LAUNCH_DMA (0x00000300) +#define NVB0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVB0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVB0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVB0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVB0B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVB0B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVB0B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVB0B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVB0B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVB0B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVB0B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVB0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVB0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVB0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVB0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVB0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVB0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVB0B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVB0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVB0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVB0B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVB0B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVB0B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVB0B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVB0B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVB0B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVB0B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVB0B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVB0B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVB0B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVB0B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVB0B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVB0B5_LAUNCH_DMA_BYPASS_L2 20:20 +#define NVB0B5_LAUNCH_DMA_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVB0B5_LAUNCH_DMA_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVB0B5_OFFSET_IN_UPPER (0x00000400) +#define NVB0B5_OFFSET_IN_UPPER_UPPER 7:0 +#define NVB0B5_OFFSET_IN_LOWER (0x00000404) +#define NVB0B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVB0B5_OFFSET_OUT_UPPER (0x00000408) +#define NVB0B5_OFFSET_OUT_UPPER_UPPER 7:0 +#define NVB0B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVB0B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVB0B5_PITCH_IN (0x00000410) +#define NVB0B5_PITCH_IN_VALUE 31:0 +#define NVB0B5_PITCH_OUT (0x00000414) +#define NVB0B5_PITCH_OUT_VALUE 31:0 +#define NVB0B5_LINE_LENGTH_IN (0x00000418) +#define NVB0B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVB0B5_LINE_COUNT (0x0000041C) +#define NVB0B5_LINE_COUNT_VALUE 31:0 +#define NVB0B5_SET_REMAP_CONST_A (0x00000700) +#define NVB0B5_SET_REMAP_CONST_A_V 31:0 +#define NVB0B5_SET_REMAP_CONST_B (0x00000704) +#define NVB0B5_SET_REMAP_CONST_B_V 31:0 +#define NVB0B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVB0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVB0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVB0B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVB0B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVB0B5_SET_DST_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) +#define NVB0B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVB0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVB0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) +#define NVB0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVB0B5_SET_DST_WIDTH (0x00000710) +#define NVB0B5_SET_DST_WIDTH_V 31:0 +#define NVB0B5_SET_DST_HEIGHT (0x00000714) +#define NVB0B5_SET_DST_HEIGHT_V 31:0 +#define NVB0B5_SET_DST_DEPTH (0x00000718) +#define NVB0B5_SET_DST_DEPTH_V 31:0 +#define NVB0B5_SET_DST_LAYER (0x0000071C) +#define NVB0B5_SET_DST_LAYER_V 31:0 +#define NVB0B5_SET_DST_ORIGIN (0x00000720) +#define NVB0B5_SET_DST_ORIGIN_X 15:0 +#define NVB0B5_SET_DST_ORIGIN_Y 31:16 +#define NVB0B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVB0B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVB0B5_SET_SRC_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) +#define NVB0B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVB0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVB0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) +#define NVB0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVB0B5_SET_SRC_WIDTH (0x0000072C) +#define NVB0B5_SET_SRC_WIDTH_V 31:0 +#define NVB0B5_SET_SRC_HEIGHT (0x00000730) +#define NVB0B5_SET_SRC_HEIGHT_V 31:0 +#define NVB0B5_SET_SRC_DEPTH (0x00000734) +#define NVB0B5_SET_SRC_DEPTH_V 31:0 +#define NVB0B5_SET_SRC_LAYER (0x00000738) +#define NVB0B5_SET_SRC_LAYER_V 31:0 +#define NVB0B5_SET_SRC_ORIGIN (0x0000073C) +#define NVB0B5_SET_SRC_ORIGIN_X 15:0 +#define NVB0B5_SET_SRC_ORIGIN_Y 31:16 +#define NVB0B5_PM_TRIGGER_END (0x00001114) +#define NVB0B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clb0b5_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clb0b5sw.h b/userspace/sdks/nv570/nvidia/inc/class/clb0b5sw.h new file mode 100644 index 0000000..ff18931 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clb0b5sw.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clb0b5sw.finn +// + + + +// +// Using VERSION_0 will cause the API to interpret +// engineType as a CE engine instance. This allows +// for backward compatibility with 85B5sw and 90B5sw. +// +#define NVB0B5_ALLOCATION_PARAMETERS_VERSION_0 0 + +// +// Using VERSION_1 will cause the API to interpret +// engineType as an NV2080_ENGINE_TYPE ordinal. +// +#define NVB0B5_ALLOCATION_PARAMETERS_VERSION_1 1 + +#define NVB0B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xb0b5U) + +typedef struct NVB0B5_ALLOCATION_PARAMETERS { + NvU32 version; + NvU32 engineType; +} NVB0B5_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clb0c0.h b/userspace/sdks/nv570/nvidia/inc/class/clb0c0.h new file mode 100644 index 0000000..c343c51 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clb0c0.h @@ -0,0 +1,720 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_maxwell_compute_a_h_ +#define _cl_maxwell_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl maxwell_compute_a */ + +#include "nvtypes.h" + +#define MAXWELL_COMPUTE_A 0xB0C0 + +#define NVB0C0_SET_OBJECT 0x0000 +#define NVB0C0_SET_OBJECT_CLASS_ID 15:0 +#define NVB0C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVB0C0_NO_OPERATION 0x0100 +#define NVB0C0_NO_OPERATION_V 31:0 + +#define NVB0C0_SET_NOTIFY_A 0x0104 +#define NVB0C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_SET_NOTIFY_B 0x0108 +#define NVB0C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_NOTIFY 0x010c +#define NVB0C0_NOTIFY_TYPE 31:0 +#define NVB0C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVB0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVB0C0_WAIT_FOR_IDLE 0x0110 +#define NVB0C0_WAIT_FOR_IDLE_V 31:0 + +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB0C0_SEND_GO_IDLE 0x013c +#define NVB0C0_SEND_GO_IDLE_V 31:0 + +#define NVB0C0_PM_TRIGGER 0x0140 +#define NVB0C0_PM_TRIGGER_V 31:0 + +#define NVB0C0_PM_TRIGGER_WFI 0x0144 +#define NVB0C0_PM_TRIGGER_WFI_V 31:0 + +#define NVB0C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVB0C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVB0C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVB0C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVB0C0_LINE_LENGTH_IN 0x0180 +#define NVB0C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVB0C0_LINE_COUNT 0x0184 +#define NVB0C0_LINE_COUNT_VALUE 31:0 + +#define NVB0C0_OFFSET_OUT_UPPER 0x0188 +#define NVB0C0_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVB0C0_OFFSET_OUT 0x018c +#define NVB0C0_OFFSET_OUT_VALUE 31:0 + +#define NVB0C0_PITCH_OUT 0x0190 +#define NVB0C0_PITCH_OUT_VALUE 31:0 + +#define NVB0C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVB0C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVB0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVB0C0_SET_DST_WIDTH 0x0198 +#define NVB0C0_SET_DST_WIDTH_V 31:0 + +#define NVB0C0_SET_DST_HEIGHT 0x019c +#define NVB0C0_SET_DST_HEIGHT_V 31:0 + +#define NVB0C0_SET_DST_DEPTH 0x01a0 +#define NVB0C0_SET_DST_DEPTH_V 31:0 + +#define NVB0C0_SET_DST_LAYER 0x01a4 +#define NVB0C0_SET_DST_LAYER_V 31:0 + +#define NVB0C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVB0C0_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVB0C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVB0C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVB0C0_LAUNCH_DMA 0x01b0 +#define NVB0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVB0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVB0C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVB0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVB0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVB0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVB0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVB0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVB0C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVB0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB0C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVB0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVB0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVB0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVB0C0_LOAD_INLINE_DATA 0x01b4 +#define NVB0C0_LOAD_INLINE_DATA_V 31:0 + +#define NVB0C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVB0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVB0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVB0C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB0C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVB0C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVB0C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVB0C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVB0C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVB0C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVB0C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVB0C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVB0C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVB0C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVB0C0_PERFMON_TRANSFER 0x0210 +#define NVB0C0_PERFMON_TRANSFER_V 31:0 + +#define NVB0C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVB0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0218 +#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVB0C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVB0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVB0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVB0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVB0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVB0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVB0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVB0C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVB0C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVB0C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVB0C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVB0C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVB0C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVB0C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVB0C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVB0C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVB0C0_SET_CWD_CONTROL 0x0240 +#define NVB0C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVB0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVB0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVB0C0_SET_CWD_REF_COUNTER 0x0248 +#define NVB0C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVB0C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVB0C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVB0C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVB0C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVB0C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVB0C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVB0C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVB0C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVB0C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVB0C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVB0C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVB0C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVB0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB0C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVB0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVB0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB0C0_SET_QMD_VERSION 0x0288 +#define NVB0C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVB0C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB0C0_CHECK_QMD_VERSION 0x0290 +#define NVB0C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVB0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB0C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVB0C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVB0C0_SEND_PCAS_A 0x02b4 +#define NVB0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVB0C0_SEND_PCAS_B 0x02b8 +#define NVB0C0_SEND_PCAS_B_FROM 23:0 +#define NVB0C0_SEND_PCAS_B_DELTA 31:24 + +#define NVB0C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVB0C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVB0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVB0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVB0C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVB0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVB0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVB0C0_SET_SPA_VERSION 0x0310 +#define NVB0C0_SET_SPA_VERSION_MINOR 7:0 +#define NVB0C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVB0C0_SET_FALCON00 0x0500 +#define NVB0C0_SET_FALCON00_V 31:0 + +#define NVB0C0_SET_FALCON01 0x0504 +#define NVB0C0_SET_FALCON01_V 31:0 + +#define NVB0C0_SET_FALCON02 0x0508 +#define NVB0C0_SET_FALCON02_V 31:0 + +#define NVB0C0_SET_FALCON03 0x050c +#define NVB0C0_SET_FALCON03_V 31:0 + +#define NVB0C0_SET_FALCON04 0x0510 +#define NVB0C0_SET_FALCON04_V 31:0 + +#define NVB0C0_SET_FALCON05 0x0514 +#define NVB0C0_SET_FALCON05_V 31:0 + +#define NVB0C0_SET_FALCON06 0x0518 +#define NVB0C0_SET_FALCON06_V 31:0 + +#define NVB0C0_SET_FALCON07 0x051c +#define NVB0C0_SET_FALCON07_V 31:0 + +#define NVB0C0_SET_FALCON08 0x0520 +#define NVB0C0_SET_FALCON08_V 31:0 + +#define NVB0C0_SET_FALCON09 0x0524 +#define NVB0C0_SET_FALCON09_V 31:0 + +#define NVB0C0_SET_FALCON10 0x0528 +#define NVB0C0_SET_FALCON10_V 31:0 + +#define NVB0C0_SET_FALCON11 0x052c +#define NVB0C0_SET_FALCON11_V 31:0 + +#define NVB0C0_SET_FALCON12 0x0530 +#define NVB0C0_SET_FALCON12_V 31:0 + +#define NVB0C0_SET_FALCON13 0x0534 +#define NVB0C0_SET_FALCON13_V 31:0 + +#define NVB0C0_SET_FALCON14 0x0538 +#define NVB0C0_SET_FALCON14_V 31:0 + +#define NVB0C0_SET_FALCON15 0x053c +#define NVB0C0_SET_FALCON15_V 31:0 + +#define NVB0C0_SET_FALCON16 0x0540 +#define NVB0C0_SET_FALCON16_V 31:0 + +#define NVB0C0_SET_FALCON17 0x0544 +#define NVB0C0_SET_FALCON17_V 31:0 + +#define NVB0C0_SET_FALCON18 0x0548 +#define NVB0C0_SET_FALCON18_V 31:0 + +#define NVB0C0_SET_FALCON19 0x054c +#define NVB0C0_SET_FALCON19_V 31:0 + +#define NVB0C0_SET_FALCON20 0x0550 +#define NVB0C0_SET_FALCON20_V 31:0 + +#define NVB0C0_SET_FALCON21 0x0554 +#define NVB0C0_SET_FALCON21_V 31:0 + +#define NVB0C0_SET_FALCON22 0x0558 +#define NVB0C0_SET_FALCON22_V 31:0 + +#define NVB0C0_SET_FALCON23 0x055c +#define NVB0C0_SET_FALCON23_V 31:0 + +#define NVB0C0_SET_FALCON24 0x0560 +#define NVB0C0_SET_FALCON24_V 31:0 + +#define NVB0C0_SET_FALCON25 0x0564 +#define NVB0C0_SET_FALCON25_V 31:0 + +#define NVB0C0_SET_FALCON26 0x0568 +#define NVB0C0_SET_FALCON26_V 31:0 + +#define NVB0C0_SET_FALCON27 0x056c +#define NVB0C0_SET_FALCON27_V 31:0 + +#define NVB0C0_SET_FALCON28 0x0570 +#define NVB0C0_SET_FALCON28_V 31:0 + +#define NVB0C0_SET_FALCON29 0x0574 +#define NVB0C0_SET_FALCON29_V 31:0 + +#define NVB0C0_SET_FALCON30 0x0578 +#define NVB0C0_SET_FALCON30_V 31:0 + +#define NVB0C0_SET_FALCON31 0x057c +#define NVB0C0_SET_FALCON31_V 31:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVB0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVB0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVB0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVB0C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVB0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVB0C0_SET_SPARE_NOOP12 0x0f44 +#define NVB0C0_SET_SPARE_NOOP12_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP13 0x0f48 +#define NVB0C0_SET_SPARE_NOOP13_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP14 0x0f4c +#define NVB0C0_SET_SPARE_NOOP14_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP15 0x0f50 +#define NVB0C0_SET_SPARE_NOOP15_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP00 0x1040 +#define NVB0C0_SET_SPARE_NOOP00_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP01 0x1044 +#define NVB0C0_SET_SPARE_NOOP01_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP02 0x1048 +#define NVB0C0_SET_SPARE_NOOP02_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP03 0x104c +#define NVB0C0_SET_SPARE_NOOP03_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP04 0x1050 +#define NVB0C0_SET_SPARE_NOOP04_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP05 0x1054 +#define NVB0C0_SET_SPARE_NOOP05_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP06 0x1058 +#define NVB0C0_SET_SPARE_NOOP06_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP07 0x105c +#define NVB0C0_SET_SPARE_NOOP07_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP08 0x1060 +#define NVB0C0_SET_SPARE_NOOP08_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP09 0x1064 +#define NVB0C0_SET_SPARE_NOOP09_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP10 0x1068 +#define NVB0C0_SET_SPARE_NOOP10_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP11 0x106c +#define NVB0C0_SET_SPARE_NOOP11_V 31:0 + +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVB0C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVB0C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVB0C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVB0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVB0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVB0C0_SET_RENDER_ENABLE_A 0x1550 +#define NVB0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_RENDER_ENABLE_B 0x1554 +#define NVB0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_RENDER_ENABLE_C 0x1558 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB0C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVB0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVB0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVB0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVB0C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVB0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVB0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVB0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVB0C0_SET_PROGRAM_REGION_A 0x1608 +#define NVB0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_SET_PROGRAM_REGION_B 0x160c +#define NVB0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVB0C0_PIPE_NOP 0x1a2c +#define NVB0C0_PIPE_NOP_V 31:0 + +#define NVB0C0_SET_SPARE00 0x1a30 +#define NVB0C0_SET_SPARE00_V 31:0 + +#define NVB0C0_SET_SPARE01 0x1a34 +#define NVB0C0_SET_SPARE01_V 31:0 + +#define NVB0C0_SET_SPARE02 0x1a38 +#define NVB0C0_SET_SPARE02_V 31:0 + +#define NVB0C0_SET_SPARE03 0x1a3c +#define NVB0C0_SET_SPARE03_V 31:0 + +#define NVB0C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVB0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVB0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVB0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB0C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVB0C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVB0C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVB0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVB0C0_SET_TRAP_HANDLER 0x260c +#define NVB0C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVB0C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVB0C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB0C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVB0C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB0C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVB0C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_maxwell_compute_a_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clb0cc.h b/userspace/sdks/nv570/nvidia/inc/class/clb0cc.h new file mode 100644 index 0000000..61ee79f --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clb0cc.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clb0cc_h_ +#define _clb0cc_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define MAXWELL_PROFILER (0x0000B0CC) + +/* + * This is an interface definition for MAXWELL_PROFILER class and cannot + * be instantiated by clients. + * MAXWELL_PROFILER_DEVICE extends this interface to define interface for + * device level profiling + */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clb0cc_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clb197.h b/userspace/sdks/nv570/nvidia/inc/class/clb197.h new file mode 100644 index 0000000..f8c976c --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clb197.h @@ -0,0 +1,4160 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_maxwell_b_h_ +#define _cl_maxwell_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl maxwell_b */ + +#include "nvtypes.h" + +#define MAXWELL_B 0xB197 + +#define NVB197_SET_OBJECT 0x0000 +#define NVB197_SET_OBJECT_CLASS_ID 15:0 +#define NVB197_SET_OBJECT_ENGINE_ID 20:16 + +#define NVB197_NO_OPERATION 0x0100 +#define NVB197_NO_OPERATION_V 31:0 + +#define NVB197_SET_NOTIFY_A 0x0104 +#define NVB197_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVB197_SET_NOTIFY_B 0x0108 +#define NVB197_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVB197_NOTIFY 0x010c +#define NVB197_NOTIFY_TYPE 31:0 +#define NVB197_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVB197_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVB197_WAIT_FOR_IDLE 0x0110 +#define NVB197_WAIT_FOR_IDLE_V 31:0 + +#define NVB197_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVB197_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVB197_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVB197_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVB197_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVB197_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVB197_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVB197_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVB197_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVB197_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVB197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVB197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVB197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVB197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVB197_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVB197_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVB197_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVB197_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVB197_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB197_SEND_GO_IDLE 0x013c +#define NVB197_SEND_GO_IDLE_V 31:0 + +#define NVB197_PM_TRIGGER 0x0140 +#define NVB197_PM_TRIGGER_V 31:0 + +#define NVB197_PM_TRIGGER_WFI 0x0144 +#define NVB197_PM_TRIGGER_WFI_V 31:0 + +#define NVB197_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVB197_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVB197_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVB197_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVB197_LINE_LENGTH_IN 0x0180 +#define NVB197_LINE_LENGTH_IN_VALUE 31:0 + +#define NVB197_LINE_COUNT 0x0184 +#define NVB197_LINE_COUNT_VALUE 31:0 + +#define NVB197_OFFSET_OUT_UPPER 0x0188 +#define NVB197_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVB197_OFFSET_OUT 0x018c +#define NVB197_OFFSET_OUT_VALUE 31:0 + +#define NVB197_PITCH_OUT 0x0190 +#define NVB197_PITCH_OUT_VALUE 31:0 + +#define NVB197_SET_DST_BLOCK_SIZE 0x0194 +#define NVB197_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVB197_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVB197_SET_DST_WIDTH 0x0198 +#define NVB197_SET_DST_WIDTH_V 31:0 + +#define NVB197_SET_DST_HEIGHT 0x019c +#define NVB197_SET_DST_HEIGHT_V 31:0 + +#define NVB197_SET_DST_DEPTH 0x01a0 +#define NVB197_SET_DST_DEPTH_V 31:0 + +#define NVB197_SET_DST_LAYER 0x01a4 +#define NVB197_SET_DST_LAYER_V 31:0 + +#define NVB197_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVB197_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVB197_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVB197_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVB197_LAUNCH_DMA 0x01b0 +#define NVB197_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVB197_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB197_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB197_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVB197_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVB197_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVB197_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVB197_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVB197_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVB197_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVB197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVB197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVB197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVB197_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVB197_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB197_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB197_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB197_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVB197_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB197_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB197_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVB197_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVB197_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVB197_LOAD_INLINE_DATA 0x01b4 +#define NVB197_LOAD_INLINE_DATA_V 31:0 + +#define NVB197_SET_I2M_SEMAPHORE_A 0x01dc +#define NVB197_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVB197_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVB197_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB197_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVB197_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVB197_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVB197_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVB197_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVB197_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVB197_SET_I2M_SPARE_NOOP03 0x01fc +#define NVB197_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVB197_RUN_DS_NOW 0x0200 +#define NVB197_RUN_DS_NOW_V 31:0 + +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVB197_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVB197_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVB197_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVB197_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVB197_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVB197_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_GS_DM_FIFO 0x0214 +#define NVB197_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVB197_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVB197_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVB197_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVB197_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB197_INVALIDATE_SHADER_CACHES 0x021c +#define NVB197_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVB197_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVB197_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVB197_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVB197_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVB197_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVB197_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVB197_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVB197_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVB197_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVB197_INCREMENT_SYNC_POINT 0x02c8 +#define NVB197_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVB197_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVB197_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVB197_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVB197_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVB197_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVB197_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVB197_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NVB197_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NVB197_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVB197_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVB197_DECOMPRESS_SURFACE 0x02e0 +#define NVB197_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVB197_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVB197_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVB197_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVB197_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVB197_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVB197_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVB197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVB197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVB197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVB197_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVB197_SET_ZCULL_SUBREGION 0x02e8 +#define NVB197_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVB197_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVB197_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVB197_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVB197_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVB197_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVB197_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVB197_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVB197_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVB197_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVB197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVB197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVB197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVB197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVB197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVB197_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVB197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVB197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVB197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVB197_DRAW_ZERO_INDEX 0x0304 +#define NVB197_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVB197_SET_L1_CONFIGURATION 0x0308 +#define NVB197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVB197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVB197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVB197_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVB197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVB197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVB197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVB197_SET_SPA_VERSION 0x0310 +#define NVB197_SET_SPA_VERSION_MINOR 7:0 +#define NVB197_SET_SPA_VERSION_MAJOR 15:8 + +#define NVB197_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NVB197_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NVB197_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_SNAP_GRID_LINE 0x0318 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVB197_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVB197_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVB197_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVB197_SET_SNAP_GRID_NON_LINE 0x031c +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVB197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVB197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVB197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVB197_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVB197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVB197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVB197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVB197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVB197_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVB197_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVB197_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVB197_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVB197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVB197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVB197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVB197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVB197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVB197_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVB197_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVB197_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVB197_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVB197_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVB197_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVB197_SET_TESSELLATION_LOD_V1 0x0330 +#define NVB197_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVB197_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVB197_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVB197_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVB197_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVB197_RESERVED_TG07 0x033c +#define NVB197_RESERVED_TG07_V 0:0 + +#define NVB197_RESERVED_TG08 0x0340 +#define NVB197_RESERVED_TG08_V 0:0 + +#define NVB197_RESERVED_TG09 0x0344 +#define NVB197_RESERVED_TG09_V 0:0 + +#define NVB197_RESERVED_TG10 0x0348 +#define NVB197_RESERVED_TG10_V 0:0 + +#define NVB197_RESERVED_TG11 0x034c +#define NVB197_RESERVED_TG11_V 0:0 + +#define NVB197_RESERVED_TG12 0x0350 +#define NVB197_RESERVED_TG12_V 0:0 + +#define NVB197_RESERVED_TG13 0x0354 +#define NVB197_RESERVED_TG13_V 0:0 + +#define NVB197_RESERVED_TG14 0x0358 +#define NVB197_RESERVED_TG14_V 0:0 + +#define NVB197_RESERVED_TG15 0x035c +#define NVB197_RESERVED_TG15_V 0:0 + +#define NVB197_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVB197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVB197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVB197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVB197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVB197_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVB197_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVB197_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVB197_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVB197_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVB197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVB197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVB197_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVB197_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVB197_SET_RASTER_ENABLE 0x037c +#define NVB197_SET_RASTER_ENABLE_V 0:0 +#define NVB197_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVB197_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVB197_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVB197_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVB197_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVB197_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVB197_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVB197_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVB197_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVB197_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVB197_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVB197_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVB197_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVB197_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVB197_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVB197_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVB197_SET_RASTER_INPUT 0x0740 +#define NVB197_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVB197_SET_STREAM_OUTPUT 0x0744 +#define NVB197_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVB197_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVB197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVB197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ALPHA_FRACTION 0x074c +#define NVB197_SET_ALPHA_FRACTION_V 7:0 + +#define NVB197_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVB197_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVB197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVB197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVB197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVB197_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVB197_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVB197_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB197_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVB197_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVB197_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVB197_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVB197_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVB197_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVB197_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVB197_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVB197_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVB197_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVB197_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVB197_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVB197_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVB197_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVB197_SET_ISBE_SAVE_RESTORE_PROGRAM 0x07ac +#define NVB197_SET_ISBE_SAVE_RESTORE_PROGRAM_OFFSET 31:0 + +#define NVB197_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVB197_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVB197_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVB197_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVB197_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVB197_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVB197_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVB197_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVB197_SET_CULL_BEFORE_FETCH 0x07dc +#define NVB197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVB197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVB197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVB197_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVB197_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVB197_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVB197_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVB197_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVB197_SET_ZCULL_STORAGE_A 0x07e8 +#define NVB197_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVB197_SET_ZCULL_STORAGE_B 0x07ec +#define NVB197_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVB197_SET_ZCULL_STORAGE_C 0x07f0 +#define NVB197_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVB197_SET_ZCULL_STORAGE_D 0x07f4 +#define NVB197_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVB197_SET_ZT_READ_ONLY 0x07f8 +#define NVB197_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVB197_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVB197_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVB197_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVB197_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVB197_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVB197_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVB197_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVB197_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVB197_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVB197_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVB197_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVB197_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVB197_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVB197_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVB197_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVB197_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVB197_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVB197_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVB197_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVB197_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVB197_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVB197_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVB197_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVB197_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB197_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVB197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVB197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVB197_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVB197_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVB197_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVB197_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVB197_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVB197_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVB197_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NVB197_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NVB197_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVB197_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVB197_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVB197_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVB197_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVB197_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVB197_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVB197_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVB197_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVB197_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVB197_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVB197_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVB197_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVB197_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVB197_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVB197_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVB197_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVB197_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVB197_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVB197_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVB197_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVB197_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVB197_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVB197_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVB197_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVB197_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVB197_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVB197_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVB197_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVB197_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVB197_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVB197_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVB197_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVB197_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVB197_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVB197_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVB197_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVB197_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVB197_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVB197_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVB197_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVB197_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVB197_SET_STATISTICS_COUNTER 0x0d68 +#define NVB197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVB197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVB197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVB197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVB197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVB197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVB197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVB197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVB197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVB197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVB197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVB197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVB197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVB197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVB197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVB197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVB197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVB197_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVB197_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVB197_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVB197_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVB197_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVB197_SET_VERTEX_ARRAY_START 0x0d74 +#define NVB197_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVB197_DRAW_VERTEX_ARRAY 0x0d78 +#define NVB197_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVB197_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVB197_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVB197_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVB197_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVB197_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVB197_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVB197_SET_Z_CLEAR_VALUE 0x0d90 +#define NVB197_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVB197_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVB197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVB197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVB197_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVB197_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVB197_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVB197_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVB197_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVB197_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVB197_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVB197_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVB197_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVB197_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVB197_SET_FRONT_POLYGON_MODE 0x0dac +#define NVB197_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVB197_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVB197_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVB197_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVB197_SET_BACK_POLYGON_MODE 0x0db0 +#define NVB197_SET_BACK_POLYGON_MODE_V 31:0 +#define NVB197_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVB197_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVB197_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVB197_SET_POLY_SMOOTH 0x0db4 +#define NVB197_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVB197_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ZT_MARK 0x0db8 +#define NVB197_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NVB197_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVB197_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVB197_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVB197_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVB197_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVB197_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVB197_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVB197_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVB197_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVB197_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVB197_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_PATCH 0x0dcc +#define NVB197_SET_PATCH_SIZE 7:0 + +#define NVB197_SET_ITERATED_BLEND 0x0dd0 +#define NVB197_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVB197_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVB197_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVB197_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVB197_SET_ZCULL_CRITERION 0x0dd8 +#define NVB197_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVB197_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVB197_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVB197_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVB197_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVB197_SET_ZCULL_CRITERION_SREF 23:16 +#define NVB197_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVB197_PIXEL_SHADER_BARRIER 0x0de0 +#define NVB197_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVB197_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVB197_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVB197_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVB197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVB197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVB197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVB197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVB197_SET_WINDOW_OFFSET_X 0x0df8 +#define NVB197_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVB197_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVB197_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVB197_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVB197_SET_SCISSOR_ENABLE_V 0:0 +#define NVB197_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVB197_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVB197_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVB197_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVB197_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVB197_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVB197_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0f10 +#define NVB197_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVB197_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVB197_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVB197_SET_VPC_PERF_KNOB 0x0f14 +#define NVB197_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVB197_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVB197_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVB197_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVB197_PM_LOCAL_TRIGGER 0x0f18 +#define NVB197_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVB197_SET_POST_Z_PS_IMASK 0x0f1c +#define NVB197_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVB197_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVB197_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVB197_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVB197_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVB197_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVB197_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVB197_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVB197_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVB197_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVB197_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVB197_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVB197_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVB197_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVB197_SET_BACK_STENCIL_MASK 0x0f58 +#define NVB197_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVB197_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVB197_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVB197_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVB197_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVB197_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVB197_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVB197_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVB197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVB197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVB197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVB197_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVB197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVB197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVB197_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVB197_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVB197_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVB197_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVB197_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVB197_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVB197_SET_SAMPLE_MASK 0x0fa4 +#define NVB197_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVB197_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVB197_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVB197_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVB197_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVB197_SET_CT_MRT_ENABLE 0x0fac +#define NVB197_SET_CT_MRT_ENABLE_V 0:0 +#define NVB197_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVB197_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVB197_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVB197_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVB197_SET_TIR 0x0fb4 +#define NVB197_SET_TIR_MODE 1:0 +#define NVB197_SET_TIR_MODE_DISABLED 0x00000000 +#define NVB197_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVB197_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVB197_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVB197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVB197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVB197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVB197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVB197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVB197_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVB197_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVB197_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVB197_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVB197_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVB197_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVB197_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVB197_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVB197_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVB197_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVB197_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_TIR_MODULATION 0x0fd4 +#define NVB197_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVB197_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVB197_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVB197_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVB197_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVB197_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVB197_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVB197_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVB197_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVB197_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVB197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVB197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVB197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVB197_SET_ZT_A 0x0fe0 +#define NVB197_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_ZT_B 0x0fe4 +#define NVB197_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_ZT_FORMAT 0x0fe8 +#define NVB197_SET_ZT_FORMAT_V 4:0 +#define NVB197_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVB197_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVB197_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVB197_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVB197_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVB197_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVB197_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVB197_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVB197_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVB197_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVB197_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVB197_SET_ZT_BLOCK_SIZE 0x0fec +#define NVB197_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVB197_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB197_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVB197_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVB197_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVB197_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVB197_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVB197_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVB197_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVB197_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVB197_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVB197_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVB197_SET_TILED_CACHE_BUNDLE_CONTROL 0x0ffc +#define NVB197_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT 0:0 +#define NVB197_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_FALSE 0x00000000 +#define NVB197_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_TRUE 0x00000001 + +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB197_SET_VIEWPORT_MULTICAST 0x1004 +#define NVB197_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVB197_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVB197_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVB197_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVB197_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVB197_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVB197_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVB197_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVB197_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVB197_SET_RESERVED_SW_METHOD00 0x1014 +#define NVB197_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVB197_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVB197_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVB197_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVB197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVB197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVB197_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVB197_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVB197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVB197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_RESERVED_SW_METHOD01 0x1028 +#define NVB197_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD02 0x102c +#define NVB197_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVB197_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVB197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVB197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVB197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVB197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVB197_SET_SPARE_NOOP01 0x1044 +#define NVB197_SET_SPARE_NOOP01_V 31:0 + +#define NVB197_SET_SPARE_NOOP02 0x1048 +#define NVB197_SET_SPARE_NOOP02_V 31:0 + +#define NVB197_SET_SPARE_NOOP03 0x104c +#define NVB197_SET_SPARE_NOOP03_V 31:0 + +#define NVB197_SET_SPARE_NOOP04 0x1050 +#define NVB197_SET_SPARE_NOOP04_V 31:0 + +#define NVB197_SET_SPARE_NOOP05 0x1054 +#define NVB197_SET_SPARE_NOOP05_V 31:0 + +#define NVB197_SET_SPARE_NOOP06 0x1058 +#define NVB197_SET_SPARE_NOOP06_V 31:0 + +#define NVB197_SET_SPARE_NOOP07 0x105c +#define NVB197_SET_SPARE_NOOP07_V 31:0 + +#define NVB197_SET_SPARE_NOOP08 0x1060 +#define NVB197_SET_SPARE_NOOP08_V 31:0 + +#define NVB197_SET_SPARE_NOOP09 0x1064 +#define NVB197_SET_SPARE_NOOP09_V 31:0 + +#define NVB197_SET_SPARE_NOOP10 0x1068 +#define NVB197_SET_SPARE_NOOP10_V 31:0 + +#define NVB197_SET_SPARE_NOOP11 0x106c +#define NVB197_SET_SPARE_NOOP11_V 31:0 + +#define NVB197_SET_SPARE_NOOP12 0x1070 +#define NVB197_SET_SPARE_NOOP12_V 31:0 + +#define NVB197_SET_SPARE_NOOP13 0x1074 +#define NVB197_SET_SPARE_NOOP13_V 31:0 + +#define NVB197_SET_SPARE_NOOP14 0x1078 +#define NVB197_SET_SPARE_NOOP14_V 31:0 + +#define NVB197_SET_SPARE_NOOP15 0x107c +#define NVB197_SET_SPARE_NOOP15_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVB197_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVB197_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVB197_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD06 0x10bc +#define NVB197_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVB197_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVB197_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVB197_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVB197_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVB197_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVB197_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVB197_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD13 0x10dc +#define NVB197_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVB197_UNBIND_ALL 0x10f4 +#define NVB197_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVB197_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVB197_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVB197_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB197_SET_RESERVED_SW_METHOD14 0x1100 +#define NVB197_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD15 0x1104 +#define NVB197_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVB197_NO_OPERATION_DATA_HI 0x110c +#define NVB197_NO_OPERATION_DATA_HI_V 31:0 + +#define NVB197_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVB197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVB197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVB197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVB197_PM_TRIGGER_END 0x1114 +#define NVB197_PM_TRIGGER_END_V 31:0 + +#define NVB197_SET_VERTEX_ID_BASE 0x1118 +#define NVB197_SET_VERTEX_ID_BASE_V 31:0 + +#define NVB197_SET_STENCIL_COMPRESSION 0x111c +#define NVB197_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVB197_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVB197_SET_TIR_CONTROL 0x1130 +#define NVB197_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVB197_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVB197_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVB197_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVB197_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVB197_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVB197_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVB197_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVB197_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 + +#define NVB197_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVB197_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVB197_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVB197_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVB197_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVB197_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVB197_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVB197_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVB197_SET_FILL_VIA_TRIANGLE 0x113c +#define NVB197_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVB197_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVB197_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVB197_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVB197_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVB197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVB197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVB197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVB197_FLUSH_PENDING_WRITES 0x1144 +#define NVB197_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVB197_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVB197_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVB197_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVB197_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVB197_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVB197_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVB197_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVB197_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVB197_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVB197_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVB197_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVB197_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVB197_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVB197_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVB197_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVB197_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVB197_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVB197_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVB197_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVB197_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVB197_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB197_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ZT_SPARSE 0x1208 +#define NVB197_SET_ZT_SPARSE_ENABLE 0:0 +#define NVB197_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVB197_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVB197_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVB197_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVB197_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_SET_CT_SELECT 0x121c +#define NVB197_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVB197_SET_CT_SELECT_TARGET0 6:4 +#define NVB197_SET_CT_SELECT_TARGET1 9:7 +#define NVB197_SET_CT_SELECT_TARGET2 12:10 +#define NVB197_SET_CT_SELECT_TARGET3 15:13 +#define NVB197_SET_CT_SELECT_TARGET4 18:16 +#define NVB197_SET_CT_SELECT_TARGET5 21:19 +#define NVB197_SET_CT_SELECT_TARGET6 24:22 +#define NVB197_SET_CT_SELECT_TARGET7 27:25 + +#define NVB197_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVB197_SET_ZT_SIZE_A 0x1228 +#define NVB197_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVB197_SET_ZT_SIZE_B 0x122c +#define NVB197_SET_ZT_SIZE_B_HEIGHT 16:0 + +#define NVB197_SET_ZT_SIZE_C 0x1230 +#define NVB197_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVB197_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVB197_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVB197_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVB197_SET_SAMPLER_BINDING 0x1234 +#define NVB197_SET_SAMPLER_BINDING_V 0:0 +#define NVB197_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVB197_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVB197_DRAW_AUTO 0x123c +#define NVB197_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVB197_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVB197_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVB197_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVB197_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVB197_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVB197_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVB197_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVB197_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVB197_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVB197_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB197_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVB197_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVB197_CLEAR_ZCULL_REGION 0x12c8 +#define NVB197_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVB197_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVB197_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVB197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVB197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVB197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVB197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVB197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVB197_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVB197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVB197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVB197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVB197_SET_DEPTH_TEST 0x12cc +#define NVB197_SET_DEPTH_TEST_ENABLE 0:0 +#define NVB197_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVB197_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_FILL_MODE 0x12d0 +#define NVB197_SET_FILL_MODE_V 31:0 +#define NVB197_SET_FILL_MODE_V_POINT 0x00000001 +#define NVB197_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVB197_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVB197_SET_SHADE_MODE 0x12d4 +#define NVB197_SET_SHADE_MODE_V 31:0 +#define NVB197_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVB197_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVB197_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVB197_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVB197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVB197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVB197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVB197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVB197_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVB197_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVB197_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVB197_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_DEPTH_WRITE 0x12e8 +#define NVB197_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVB197_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ALPHA_TEST 0x12ec +#define NVB197_SET_ALPHA_TEST_ENABLE 0:0 +#define NVB197_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVB197_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVB197_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVB197_DRAW_INLINE_INDEX4X8 0x1304 +#define NVB197_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVB197_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVB197_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVB197_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVB197_D3D_SET_CULL_MODE 0x1308 +#define NVB197_D3D_SET_CULL_MODE_V 31:0 +#define NVB197_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVB197_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVB197_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVB197_SET_DEPTH_FUNC 0x130c +#define NVB197_SET_DEPTH_FUNC_V 31:0 +#define NVB197_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVB197_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVB197_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB197_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB197_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVB197_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB197_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB197_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB197_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVB197_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVB197_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB197_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB197_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVB197_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB197_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB197_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB197_SET_ALPHA_REF 0x1310 +#define NVB197_SET_ALPHA_REF_V 31:0 + +#define NVB197_SET_ALPHA_FUNC 0x1314 +#define NVB197_SET_ALPHA_FUNC_V 31:0 +#define NVB197_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVB197_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVB197_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB197_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB197_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVB197_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB197_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB197_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB197_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVB197_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVB197_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB197_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB197_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVB197_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB197_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB197_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB197_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVB197_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVB197_SET_BLEND_CONST_RED 0x131c +#define NVB197_SET_BLEND_CONST_RED_V 31:0 + +#define NVB197_SET_BLEND_CONST_GREEN 0x1320 +#define NVB197_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVB197_SET_BLEND_CONST_BLUE 0x1324 +#define NVB197_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVB197_SET_BLEND_CONST_ALPHA 0x1328 +#define NVB197_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVB197_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVB197_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVB197_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVB197_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVB197_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVB197_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVB197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVB197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVB197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BLEND_COLOR_OP 0x1340 +#define NVB197_SET_BLEND_COLOR_OP_V 31:0 +#define NVB197_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB197_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB197_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB197_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVB197_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVB197_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVB197_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB197_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB197_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVB197_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_BLEND_ALPHA_OP 0x134c +#define NVB197_SET_BLEND_ALPHA_OP_V 31:0 +#define NVB197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB197_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVB197_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVB197_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVB197_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB197_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB197_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVB197_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVB197_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVB197_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVB197_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_SINGLE_ROP_CONTROL 0x135c +#define NVB197_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVB197_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BLEND(i) (0x1360+(i)*4) +#define NVB197_SET_BLEND_ENABLE 0:0 +#define NVB197_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVB197_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_STENCIL_TEST 0x1380 +#define NVB197_SET_STENCIL_TEST_ENABLE 0:0 +#define NVB197_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_STENCIL_OP_FAIL 0x1384 +#define NVB197_SET_STENCIL_OP_FAIL_V 31:0 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVB197_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVB197_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVB197_SET_STENCIL_OP_ZPASS 0x138c +#define NVB197_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVB197_SET_STENCIL_FUNC 0x1390 +#define NVB197_SET_STENCIL_FUNC_V 31:0 +#define NVB197_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVB197_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVB197_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB197_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB197_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVB197_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB197_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB197_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB197_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVB197_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVB197_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB197_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB197_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVB197_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB197_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB197_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB197_SET_STENCIL_FUNC_REF 0x1394 +#define NVB197_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVB197_SET_STENCIL_FUNC_MASK 0x1398 +#define NVB197_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVB197_SET_STENCIL_MASK 0x139c +#define NVB197_SET_STENCIL_MASK_V 7:0 + +#define NVB197_SET_DRAW_AUTO_START 0x13a4 +#define NVB197_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVB197_SET_PS_SATURATE 0x13a8 +#define NVB197_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVB197_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVB197_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVB197_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVB197_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVB197_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVB197_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVB197_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVB197_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVB197_SET_WINDOW_ORIGIN 0x13ac +#define NVB197_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVB197_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVB197_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVB197_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVB197_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVB197_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVB197_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVB197_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVB197_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVB197_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVB197_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVB197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVB197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ALPHA_HYSTERESIS 0x1420 +#define NVB197_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NVB197_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVB197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVB197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB197_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVB197_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVB197_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVB197_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVB197_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVB197_SET_PS_WARP_WATERMARKS 0x1450 +#define NVB197_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVB197_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVB197_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVB197_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVB197_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVB197_STORE_ZCULL 0x1464 +#define NVB197_STORE_ZCULL_V 0:0 + +#define NVB197_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVB197_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVB197_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVB197_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVB197_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVB197_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVB197_LOAD_ZCULL 0x1500 +#define NVB197_LOAD_ZCULL_V 0:0 + +#define NVB197_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVB197_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVB197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVB197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVB197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVB197_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVB197_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVB197_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVB197_SET_USER_CLIP_ENABLE 0x1510 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVB197_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVB197_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVB197_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_POINT_SIZE 0x1518 +#define NVB197_SET_POINT_SIZE_V 31:0 + +#define NVB197_SET_ZCULL_STATS 0x151c +#define NVB197_SET_ZCULL_STATS_ENABLE 0:0 +#define NVB197_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_POINT_SPRITE 0x1520 +#define NVB197_SET_POINT_SPRITE_ENABLE 0:0 +#define NVB197_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_SHADER_EXCEPTIONS 0x1528 +#define NVB197_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVB197_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVB197_CLEAR_REPORT_VALUE 0x1530 +#define NVB197_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVB197_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVB197_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVB197_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVB197_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVB197_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVB197_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 + +#define NVB197_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVB197_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVB197_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_ZT_SELECT 0x1538 +#define NVB197_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVB197_SET_RENDER_ENABLE_A 0x1550 +#define NVB197_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_RENDER_ENABLE_B 0x1554 +#define NVB197_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_RENDER_ENABLE_C 0x1558 +#define NVB197_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVB197_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB197_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB197_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB197_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB197_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB197_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVB197_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVB197_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVB197_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVB197_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVB197_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVB197_SET_ANTI_ALIASED_LINE 0x1570 +#define NVB197_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVB197_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_TEX_HEADER_POOL_A 0x1574 +#define NVB197_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_TEX_HEADER_POOL_B 0x1578 +#define NVB197_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_TEX_HEADER_POOL_C 0x157c +#define NVB197_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVB197_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVB197_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVB197_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVB197_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVB197_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVB197_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVB197_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVB197_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVB197_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB197_SET_SRGB_WRITE 0x15b8 +#define NVB197_SET_SRGB_WRITE_ENABLE 0:0 +#define NVB197_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_DEPTH_BIAS 0x15bc +#define NVB197_SET_DEPTH_BIAS_V 31:0 + +#define NVB197_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVB197_SET_RT_LAYER 0x15cc +#define NVB197_SET_RT_LAYER_V 15:0 +#define NVB197_SET_RT_LAYER_CONTROL 16:16 +#define NVB197_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVB197_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVB197_SET_ANTI_ALIAS 0x15d0 +#define NVB197_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVB197_SET_EDGE_FLAG 0x15e4 +#define NVB197_SET_EDGE_FLAG_V 0:0 +#define NVB197_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVB197_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVB197_DRAW_INLINE_INDEX 0x15e8 +#define NVB197_DRAW_INLINE_INDEX_V 31:0 + +#define NVB197_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVB197_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVB197_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVB197_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVB197_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVB197_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVB197_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVB197_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVB197_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVB197_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVB197_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVB197_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVB197_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVB197_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVB197_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVB197_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVB197_SET_POINT_SPRITE_SELECT 0x1604 +#define NVB197_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVB197_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVB197_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVB197_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVB197_SET_PROGRAM_REGION_A 0x1608 +#define NVB197_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVB197_SET_PROGRAM_REGION_B 0x160c +#define NVB197_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVB197_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVB197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVB197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVB197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVB197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVB197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVB197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVB197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVB197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVB197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVB197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVB197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVB197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVB197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVB197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVB197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVB197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVB197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVB197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVB197_END 0x1614 +#define NVB197_END_V 0:0 + +#define NVB197_BEGIN 0x1618 +#define NVB197_BEGIN_OP 15:0 +#define NVB197_BEGIN_OP_POINTS 0x00000000 +#define NVB197_BEGIN_OP_LINES 0x00000001 +#define NVB197_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVB197_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVB197_BEGIN_OP_TRIANGLES 0x00000004 +#define NVB197_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVB197_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVB197_BEGIN_OP_QUADS 0x00000007 +#define NVB197_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVB197_BEGIN_OP_POLYGON 0x00000009 +#define NVB197_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVB197_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVB197_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_BEGIN_OP_PATCH 0x0000000E +#define NVB197_BEGIN_PRIMITIVE_ID 24:24 +#define NVB197_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVB197_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVB197_BEGIN_INSTANCE_ID 27:26 +#define NVB197_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVB197_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVB197_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVB197_BEGIN_SPLIT_MODE 30:29 +#define NVB197_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVB197_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVB197_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVB197_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 + +#define NVB197_SET_VERTEX_ID_COPY 0x161c +#define NVB197_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVB197_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVB197_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVB197_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVB197_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVB197_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVB197_LOAD_PRIMITIVE_ID 0x1624 +#define NVB197_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVB197_SET_SHADER_BASED_CULL 0x162c +#define NVB197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVB197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVB197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVB197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_CLASS_VERSION 0x1638 +#define NVB197_SET_CLASS_VERSION_CURRENT 15:0 +#define NVB197_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB197_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVB197_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVB197_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVB197_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVB197_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVB197_SET_DA_OUTPUT 0x164c +#define NVB197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVB197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVB197_SET_ANTI_ALIASED_POINT 0x1658 +#define NVB197_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVB197_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_POINT_CENTER_MODE 0x165c +#define NVB197_SET_POINT_CENTER_MODE_V 31:0 +#define NVB197_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVB197_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVB197_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVB197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVB197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVB197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVB197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVB197_SET_LINE_STIPPLE 0x166c +#define NVB197_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVB197_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVB197_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVB197_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVB197_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVB197_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVB197_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVB197_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVB197_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVB197_SET_PROVOKING_VERTEX 0x1684 +#define NVB197_SET_PROVOKING_VERTEX_V 0:0 +#define NVB197_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVB197_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVB197_SET_TWO_SIDED_LIGHT 0x1688 +#define NVB197_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVB197_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_POLYGON_STIPPLE 0x168c +#define NVB197_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVB197_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_SHADER_CONTROL 0x1690 +#define NVB197_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVB197_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVB197_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVB197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVB197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVB197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVB197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVB197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVB197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVB197_CHECK_CLASS_VERSION 0x16a0 +#define NVB197_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVB197_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB197_SET_SPH_VERSION 0x16a4 +#define NVB197_SET_SPH_VERSION_CURRENT 15:0 +#define NVB197_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB197_CHECK_SPH_VERSION 0x16a8 +#define NVB197_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVB197_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVB197_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVB197_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVB197_SET_AAM_VERSION 0x1790 +#define NVB197_SET_AAM_VERSION_CURRENT 15:0 +#define NVB197_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB197_CHECK_AAM_VERSION 0x1794 +#define NVB197_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVB197_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB197_SET_ZT_LAYER 0x179c +#define NVB197_SET_ZT_LAYER_OFFSET 15:0 + +#define NVB197_SET_INDEX_BUFFER_A 0x17c8 +#define NVB197_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVB197_SET_INDEX_BUFFER_B 0x17cc +#define NVB197_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVB197_SET_INDEX_BUFFER_C 0x17d0 +#define NVB197_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVB197_SET_INDEX_BUFFER_D 0x17d4 +#define NVB197_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVB197_SET_INDEX_BUFFER_E 0x17d8 +#define NVB197_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVB197_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVB197_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVB197_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVB197_SET_INDEX_BUFFER_F 0x17dc +#define NVB197_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVB197_DRAW_INDEX_BUFFER 0x17e0 +#define NVB197_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVB197_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVB197_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVB197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVB197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVB197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVB197_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVB197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVB197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVB197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVB197_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVB197_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVB197_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVB197_OGL_SET_CULL 0x1918 +#define NVB197_OGL_SET_CULL_ENABLE 0:0 +#define NVB197_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVB197_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVB197_OGL_SET_FRONT_FACE 0x191c +#define NVB197_OGL_SET_FRONT_FACE_V 31:0 +#define NVB197_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVB197_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVB197_OGL_SET_CULL_FACE 0x1920 +#define NVB197_OGL_SET_CULL_FACE_V 31:0 +#define NVB197_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVB197_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVB197_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVB197_SET_VIEWPORT_PIXEL 0x1924 +#define NVB197_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVB197_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVB197_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVB197_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVB197_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVB197_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVB197_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVB197_SET_USER_CLIP_OP 0x1940 +#define NVB197_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVB197_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVB197_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVB197_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVB197_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVB197_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVB197_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVB197_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVB197_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVB197_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVB197_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVB197_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVB197_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVB197_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVB197_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVB197_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVB197_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVB197_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVB197_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVB197_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVB197_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVB197_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVB197_INVALIDATE_ZCULL 0x1958 +#define NVB197_INVALIDATE_ZCULL_V 31:0 +#define NVB197_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVB197_SET_ZCULL 0x1968 +#define NVB197_SET_ZCULL_Z_ENABLE 0:0 +#define NVB197_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVB197_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ZCULL_BOUNDS 0x196c +#define NVB197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVB197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVB197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVB197_ZCULL_SYNC 0x1978 +#define NVB197_ZCULL_SYNC_V 31:0 + +#define NVB197_SET_CLIP_ID_TEST 0x197c +#define NVB197_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVB197_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVB197_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVB197_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVB197_SET_CLIP_ID 0x1984 +#define NVB197_SET_CLIP_ID_V 31:0 + +#define NVB197_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVB197_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVB197_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVB197_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVB197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVB197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVB197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVB197_SET_LOGIC_OP 0x19c4 +#define NVB197_SET_LOGIC_OP_ENABLE 0:0 +#define NVB197_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVB197_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_LOGIC_OP_FUNC 0x19c8 +#define NVB197_SET_LOGIC_OP_FUNC_V 31:0 +#define NVB197_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVB197_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVB197_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVB197_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVB197_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVB197_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVB197_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVB197_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVB197_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVB197_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVB197_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVB197_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVB197_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVB197_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVB197_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVB197_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVB197_SET_Z_COMPRESSION 0x19cc +#define NVB197_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVB197_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVB197_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVB197_CLEAR_SURFACE 0x19d0 +#define NVB197_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVB197_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVB197_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVB197_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVB197_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVB197_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVB197_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVB197_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVB197_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVB197_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVB197_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVB197_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVB197_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVB197_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVB197_SET_CT_WRITE_R_ENABLE 0:0 +#define NVB197_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVB197_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVB197_SET_CT_WRITE_G_ENABLE 4:4 +#define NVB197_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVB197_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVB197_SET_CT_WRITE_B_ENABLE 8:8 +#define NVB197_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVB197_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVB197_SET_CT_WRITE_A_ENABLE 12:12 +#define NVB197_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVB197_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVB197_PIPE_NOP 0x1a2c +#define NVB197_PIPE_NOP_V 31:0 + +#define NVB197_SET_SPARE00 0x1a30 +#define NVB197_SET_SPARE00_V 31:0 + +#define NVB197_SET_SPARE01 0x1a34 +#define NVB197_SET_SPARE01_V 31:0 + +#define NVB197_SET_SPARE02 0x1a38 +#define NVB197_SET_SPARE02_V 31:0 + +#define NVB197_SET_SPARE03 0x1a3c +#define NVB197_SET_SPARE03_V 31:0 + +#define NVB197_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVB197_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVB197_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVB197_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB197_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVB197_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVB197_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVB197_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVB197_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVB197_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVB197_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVB197_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVB197_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVB197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVB197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVB197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVB197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVB197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVB197_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVB197_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVB197_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVB197_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVB197_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVB197_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVB197_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVB197_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVB197_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVB197_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVB197_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVB197_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVB197_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVB197_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVB197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVB197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVB197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVB197_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVB197_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVB197_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVB197_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVB197_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVB197_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVB197_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVB197_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVB197_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVB197_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVB197_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVB197_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVB197_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVB197_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVB197_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVB197_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVB197_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVB197_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVB197_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NVB197_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NVB197_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVB197_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVB197_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVB197_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NVB197_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVB197_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVB197_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NVB197_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVB197_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NVB197_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NVB197_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVB197_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVB197_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVB197_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVB197_SET_FALCON00 0x2300 +#define NVB197_SET_FALCON00_V 31:0 + +#define NVB197_SET_FALCON01 0x2304 +#define NVB197_SET_FALCON01_V 31:0 + +#define NVB197_SET_FALCON02 0x2308 +#define NVB197_SET_FALCON02_V 31:0 + +#define NVB197_SET_FALCON03 0x230c +#define NVB197_SET_FALCON03_V 31:0 + +#define NVB197_SET_FALCON04 0x2310 +#define NVB197_SET_FALCON04_V 31:0 + +#define NVB197_SET_FALCON05 0x2314 +#define NVB197_SET_FALCON05_V 31:0 + +#define NVB197_SET_FALCON06 0x2318 +#define NVB197_SET_FALCON06_V 31:0 + +#define NVB197_SET_FALCON07 0x231c +#define NVB197_SET_FALCON07_V 31:0 + +#define NVB197_SET_FALCON08 0x2320 +#define NVB197_SET_FALCON08_V 31:0 + +#define NVB197_SET_FALCON09 0x2324 +#define NVB197_SET_FALCON09_V 31:0 + +#define NVB197_SET_FALCON10 0x2328 +#define NVB197_SET_FALCON10_V 31:0 + +#define NVB197_SET_FALCON11 0x232c +#define NVB197_SET_FALCON11_V 31:0 + +#define NVB197_SET_FALCON12 0x2330 +#define NVB197_SET_FALCON12_V 31:0 + +#define NVB197_SET_FALCON13 0x2334 +#define NVB197_SET_FALCON13_V 31:0 + +#define NVB197_SET_FALCON14 0x2338 +#define NVB197_SET_FALCON14_V 31:0 + +#define NVB197_SET_FALCON15 0x233c +#define NVB197_SET_FALCON15_V 31:0 + +#define NVB197_SET_FALCON16 0x2340 +#define NVB197_SET_FALCON16_V 31:0 + +#define NVB197_SET_FALCON17 0x2344 +#define NVB197_SET_FALCON17_V 31:0 + +#define NVB197_SET_FALCON18 0x2348 +#define NVB197_SET_FALCON18_V 31:0 + +#define NVB197_SET_FALCON19 0x234c +#define NVB197_SET_FALCON19_V 31:0 + +#define NVB197_SET_FALCON20 0x2350 +#define NVB197_SET_FALCON20_V 31:0 + +#define NVB197_SET_FALCON21 0x2354 +#define NVB197_SET_FALCON21_V 31:0 + +#define NVB197_SET_FALCON22 0x2358 +#define NVB197_SET_FALCON22_V 31:0 + +#define NVB197_SET_FALCON23 0x235c +#define NVB197_SET_FALCON23_V 31:0 + +#define NVB197_SET_FALCON24 0x2360 +#define NVB197_SET_FALCON24_V 31:0 + +#define NVB197_SET_FALCON25 0x2364 +#define NVB197_SET_FALCON25_V 31:0 + +#define NVB197_SET_FALCON26 0x2368 +#define NVB197_SET_FALCON26_V 31:0 + +#define NVB197_SET_FALCON27 0x236c +#define NVB197_SET_FALCON27_V 31:0 + +#define NVB197_SET_FALCON28 0x2370 +#define NVB197_SET_FALCON28_V 31:0 + +#define NVB197_SET_FALCON29 0x2374 +#define NVB197_SET_FALCON29_V 31:0 + +#define NVB197_SET_FALCON30 0x2378 +#define NVB197_SET_FALCON30_V 31:0 + +#define NVB197_SET_FALCON31 0x237c +#define NVB197_SET_FALCON31_V 31:0 + +#define NVB197_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVB197_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVB197_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVB197_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVB197_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVB197_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVB197_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVB197_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVB197_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVB197_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVB197_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVB197_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVB197_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVB197_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVB197_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVB197_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVB197_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVB197_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVB197_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVB197_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVB197_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVB197_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVB197_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVB197_SET_COLOR_CLAMP 0x2600 +#define NVB197_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVB197_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVB197_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BINDLESS_TEXTURE 0x2608 +#define NVB197_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVB197_SET_TRAP_HANDLER 0x260c +#define NVB197_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVB197_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVB197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVB197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVB197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVB197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVB197_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVB197_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB197_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVB197_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB197_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVB197_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVB197_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVB197_CALL_MME_MACRO_V 31:0 + +#define NVB197_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVB197_CALL_MME_DATA_V 31:0 + +#endif /* _cl_maxwell_b_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clb1c0.h b/userspace/sdks/nv570/nvidia/inc/class/clb1c0.h new file mode 100644 index 0000000..8d7aaac --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clb1c0.h @@ -0,0 +1,750 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_maxwell_compute_b_h_ +#define _cl_maxwell_compute_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl maxwell_compute_b */ + +#include "nvtypes.h" + +#define MAXWELL_COMPUTE_B 0xB1C0 + +#define NVB1C0_SET_OBJECT 0x0000 +#define NVB1C0_SET_OBJECT_CLASS_ID 15:0 +#define NVB1C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVB1C0_NO_OPERATION 0x0100 +#define NVB1C0_NO_OPERATION_V 31:0 + +#define NVB1C0_SET_NOTIFY_A 0x0104 +#define NVB1C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_SET_NOTIFY_B 0x0108 +#define NVB1C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_NOTIFY 0x010c +#define NVB1C0_NOTIFY_TYPE 31:0 +#define NVB1C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVB1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVB1C0_WAIT_FOR_IDLE 0x0110 +#define NVB1C0_WAIT_FOR_IDLE_V 31:0 + +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB1C0_SEND_GO_IDLE 0x013c +#define NVB1C0_SEND_GO_IDLE_V 31:0 + +#define NVB1C0_PM_TRIGGER 0x0140 +#define NVB1C0_PM_TRIGGER_V 31:0 + +#define NVB1C0_PM_TRIGGER_WFI 0x0144 +#define NVB1C0_PM_TRIGGER_WFI_V 31:0 + +#define NVB1C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVB1C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVB1C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVB1C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVB1C0_LINE_LENGTH_IN 0x0180 +#define NVB1C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVB1C0_LINE_COUNT 0x0184 +#define NVB1C0_LINE_COUNT_VALUE 31:0 + +#define NVB1C0_OFFSET_OUT_UPPER 0x0188 +#define NVB1C0_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVB1C0_OFFSET_OUT 0x018c +#define NVB1C0_OFFSET_OUT_VALUE 31:0 + +#define NVB1C0_PITCH_OUT 0x0190 +#define NVB1C0_PITCH_OUT_VALUE 31:0 + +#define NVB1C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVB1C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVB1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVB1C0_SET_DST_WIDTH 0x0198 +#define NVB1C0_SET_DST_WIDTH_V 31:0 + +#define NVB1C0_SET_DST_HEIGHT 0x019c +#define NVB1C0_SET_DST_HEIGHT_V 31:0 + +#define NVB1C0_SET_DST_DEPTH 0x01a0 +#define NVB1C0_SET_DST_DEPTH_V 31:0 + +#define NVB1C0_SET_DST_LAYER 0x01a4 +#define NVB1C0_SET_DST_LAYER_V 31:0 + +#define NVB1C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVB1C0_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVB1C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVB1C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVB1C0_LAUNCH_DMA 0x01b0 +#define NVB1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVB1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVB1C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVB1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVB1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVB1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVB1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVB1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVB1C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVB1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB1C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVB1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVB1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVB1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVB1C0_LOAD_INLINE_DATA 0x01b4 +#define NVB1C0_LOAD_INLINE_DATA_V 31:0 + +#define NVB1C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVB1C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVB1C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVB1C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB1C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVB1C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVB1C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVB1C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVB1C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVB1C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVB1C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVB1C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVB1C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVB1C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVB1C0_PERFMON_TRANSFER 0x0210 +#define NVB1C0_PERFMON_TRANSFER_V 31:0 + +#define NVB1C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVB1C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0218 +#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVB1C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVB1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVB1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVB1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVB1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVB1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVB1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVB1C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVB1C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVB1C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVB1C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVB1C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVB1C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVB1C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVB1C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVB1C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVB1C0_SET_CWD_CONTROL 0x0240 +#define NVB1C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVB1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVB1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVB1C0_SET_CWD_REF_COUNTER 0x0248 +#define NVB1C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVB1C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVB1C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVB1C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVB1C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVB1C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVB1C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVB1C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVB1C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVB1C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVB1C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVB1C0_SET_GWC_SCG_TYPE 0x026c +#define NVB1C0_SET_GWC_SCG_TYPE_SCG_TYPE 0:0 +#define NVB1C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0 0x00000000 +#define NVB1C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1 0x00000001 + +#define NVB1C0_SET_SCG_CONTROL 0x0270 +#define NVB1C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 + +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVB1C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVB1C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVB1C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB1C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVB1C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVB1C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB1C0_SET_QMD_VERSION 0x0288 +#define NVB1C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVB1C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB1C0_SET_WFI_CONFIG 0x028c +#define NVB1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI 0:0 +#define NVB1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE 0x00000000 +#define NVB1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE 0x00000001 + +#define NVB1C0_CHECK_QMD_VERSION 0x0290 +#define NVB1C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVB1C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB1C0_WAIT_FOR_IDLE_SCG_TYPE 0x0294 +#define NVB1C0_WAIT_FOR_IDLE_SCG_TYPE_V 31:0 + +#define NVB1C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVB1C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL 0x029c +#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE 0:0 +#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE 0x00000001 + +#define NVB1C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVB1C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVB1C0_SEND_PCAS_A 0x02b4 +#define NVB1C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVB1C0_SEND_PCAS_B 0x02b8 +#define NVB1C0_SEND_PCAS_B_FROM 23:0 +#define NVB1C0_SEND_PCAS_B_DELTA 31:24 + +#define NVB1C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVB1C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVB1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVB1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVB1C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVB1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVB1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVB1C0_SET_SPA_VERSION 0x0310 +#define NVB1C0_SET_SPA_VERSION_MINOR 7:0 +#define NVB1C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVB1C0_SET_FALCON00 0x0500 +#define NVB1C0_SET_FALCON00_V 31:0 + +#define NVB1C0_SET_FALCON01 0x0504 +#define NVB1C0_SET_FALCON01_V 31:0 + +#define NVB1C0_SET_FALCON02 0x0508 +#define NVB1C0_SET_FALCON02_V 31:0 + +#define NVB1C0_SET_FALCON03 0x050c +#define NVB1C0_SET_FALCON03_V 31:0 + +#define NVB1C0_SET_FALCON04 0x0510 +#define NVB1C0_SET_FALCON04_V 31:0 + +#define NVB1C0_SET_FALCON05 0x0514 +#define NVB1C0_SET_FALCON05_V 31:0 + +#define NVB1C0_SET_FALCON06 0x0518 +#define NVB1C0_SET_FALCON06_V 31:0 + +#define NVB1C0_SET_FALCON07 0x051c +#define NVB1C0_SET_FALCON07_V 31:0 + +#define NVB1C0_SET_FALCON08 0x0520 +#define NVB1C0_SET_FALCON08_V 31:0 + +#define NVB1C0_SET_FALCON09 0x0524 +#define NVB1C0_SET_FALCON09_V 31:0 + +#define NVB1C0_SET_FALCON10 0x0528 +#define NVB1C0_SET_FALCON10_V 31:0 + +#define NVB1C0_SET_FALCON11 0x052c +#define NVB1C0_SET_FALCON11_V 31:0 + +#define NVB1C0_SET_FALCON12 0x0530 +#define NVB1C0_SET_FALCON12_V 31:0 + +#define NVB1C0_SET_FALCON13 0x0534 +#define NVB1C0_SET_FALCON13_V 31:0 + +#define NVB1C0_SET_FALCON14 0x0538 +#define NVB1C0_SET_FALCON14_V 31:0 + +#define NVB1C0_SET_FALCON15 0x053c +#define NVB1C0_SET_FALCON15_V 31:0 + +#define NVB1C0_SET_FALCON16 0x0540 +#define NVB1C0_SET_FALCON16_V 31:0 + +#define NVB1C0_SET_FALCON17 0x0544 +#define NVB1C0_SET_FALCON17_V 31:0 + +#define NVB1C0_SET_FALCON18 0x0548 +#define NVB1C0_SET_FALCON18_V 31:0 + +#define NVB1C0_SET_FALCON19 0x054c +#define NVB1C0_SET_FALCON19_V 31:0 + +#define NVB1C0_SET_FALCON20 0x0550 +#define NVB1C0_SET_FALCON20_V 31:0 + +#define NVB1C0_SET_FALCON21 0x0554 +#define NVB1C0_SET_FALCON21_V 31:0 + +#define NVB1C0_SET_FALCON22 0x0558 +#define NVB1C0_SET_FALCON22_V 31:0 + +#define NVB1C0_SET_FALCON23 0x055c +#define NVB1C0_SET_FALCON23_V 31:0 + +#define NVB1C0_SET_FALCON24 0x0560 +#define NVB1C0_SET_FALCON24_V 31:0 + +#define NVB1C0_SET_FALCON25 0x0564 +#define NVB1C0_SET_FALCON25_V 31:0 + +#define NVB1C0_SET_FALCON26 0x0568 +#define NVB1C0_SET_FALCON26_V 31:0 + +#define NVB1C0_SET_FALCON27 0x056c +#define NVB1C0_SET_FALCON27_V 31:0 + +#define NVB1C0_SET_FALCON28 0x0570 +#define NVB1C0_SET_FALCON28_V 31:0 + +#define NVB1C0_SET_FALCON29 0x0574 +#define NVB1C0_SET_FALCON29_V 31:0 + +#define NVB1C0_SET_FALCON30 0x0578 +#define NVB1C0_SET_FALCON30_V 31:0 + +#define NVB1C0_SET_FALCON31 0x057c +#define NVB1C0_SET_FALCON31_V 31:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVB1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVB1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVB1C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVB1C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVB1C0_SET_SPARE_NOOP12 0x0f44 +#define NVB1C0_SET_SPARE_NOOP12_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP13 0x0f48 +#define NVB1C0_SET_SPARE_NOOP13_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP14 0x0f4c +#define NVB1C0_SET_SPARE_NOOP14_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP15 0x0f50 +#define NVB1C0_SET_SPARE_NOOP15_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP00 0x1040 +#define NVB1C0_SET_SPARE_NOOP00_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP01 0x1044 +#define NVB1C0_SET_SPARE_NOOP01_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP02 0x1048 +#define NVB1C0_SET_SPARE_NOOP02_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP03 0x104c +#define NVB1C0_SET_SPARE_NOOP03_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP04 0x1050 +#define NVB1C0_SET_SPARE_NOOP04_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP05 0x1054 +#define NVB1C0_SET_SPARE_NOOP05_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP06 0x1058 +#define NVB1C0_SET_SPARE_NOOP06_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP07 0x105c +#define NVB1C0_SET_SPARE_NOOP07_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP08 0x1060 +#define NVB1C0_SET_SPARE_NOOP08_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP09 0x1064 +#define NVB1C0_SET_SPARE_NOOP09_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP10 0x1068 +#define NVB1C0_SET_SPARE_NOOP10_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP11 0x106c +#define NVB1C0_SET_SPARE_NOOP11_V 31:0 + +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVB1C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVB1C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVB1C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVB1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVB1C0_SET_RENDER_ENABLE_A 0x1550 +#define NVB1C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_RENDER_ENABLE_B 0x1554 +#define NVB1C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_RENDER_ENABLE_C 0x1558 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB1C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVB1C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVB1C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVB1C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVB1C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVB1C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVB1C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVB1C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVB1C0_SET_PROGRAM_REGION_A 0x1608 +#define NVB1C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_SET_PROGRAM_REGION_B 0x160c +#define NVB1C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVB1C0_PIPE_NOP 0x1a2c +#define NVB1C0_PIPE_NOP_V 31:0 + +#define NVB1C0_SET_SPARE00 0x1a30 +#define NVB1C0_SET_SPARE00_V 31:0 + +#define NVB1C0_SET_SPARE01 0x1a34 +#define NVB1C0_SET_SPARE01_V 31:0 + +#define NVB1C0_SET_SPARE02 0x1a38 +#define NVB1C0_SET_SPARE02_V 31:0 + +#define NVB1C0_SET_SPARE03 0x1a3c +#define NVB1C0_SET_SPARE03_V 31:0 + +#define NVB1C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVB1C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVB1C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVB1C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB1C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVB1C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVB1C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVB1C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVB1C0_SET_TRAP_HANDLER 0x260c +#define NVB1C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVB1C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVB1C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB1C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVB1C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB1C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVB1C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_maxwell_compute_b_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clb2cc.h b/userspace/sdks/nv570/nvidia/inc/class/clb2cc.h new file mode 100644 index 0000000..e539404 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clb2cc.h @@ -0,0 +1,60 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clb2cc.finn +// + +#include "clb0cc.h" + +#define MAXWELL_PROFILER_DEVICE (0xb2ccU) /* finn: Evaluated from "NVB2CC_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* + * Creating the MAXWELL_PROFILER_DEVICE object: + * - The profiler object is instantiated as a child of subdevice. + */ +#define NVB2CC_ALLOC_PARAMETERS_MESSAGE_ID (0xb2ccU) + +typedef struct NVB2CC_ALLOC_PARAMETERS { + /* + * This parameter specifies the handle of the client that owns the context + * specified by hContextTarget. This can set it to 0 where a context + * specific operation is not needed. For context level operations see: + * @ref NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY, @ref NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC, + * @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM. + */ + NvHandle hClientTarget; + + /* + * This parameter specifies the handle of the BC channel (or BC channel + * group) object instance to which context-specific operations are to be + * directed. If hClientTarget is set to 0 then this parameter is ignored. + */ + NvHandle hContextTarget; +} NVB2CC_ALLOC_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clb4b7.h b/userspace/sdks/nv570/nvidia/inc/class/clb4b7.h new file mode 100644 index 0000000..e015151 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clb4b7.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clb4b7_h_ +#define clb4b7_h_ + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVB4B7_VIDEO_ENCODER (0x0000B4B7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clb4b7_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clb6b0.h b/userspace/sdks/nv570/nvidia/inc/class/clb6b0.h new file mode 100644 index 0000000..d79dcb4 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clb6b0.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "nvtypes.h" + +#ifndef _clb6b0_h_ +#define _clb6b0_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVB6B0_VIDEO_DECODER (0x0000B6B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clb6b0_h diff --git a/userspace/sdks/nv570/nvidia/inc/class/clb8b0.h b/userspace/sdks/nv570/nvidia/inc/class/clb8b0.h new file mode 100644 index 0000000..b2d0e09 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clb8b0.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clb8b0_h__ +#define __gh100_clb8b0_h__ +#define NVB8B0_VIDEO_DECODER (0x0000B8B0) +#endif // __gh100_clb8b0_h__ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clb8d1.h b/userspace/sdks/nv570/nvidia/inc/class/clb8d1.h new file mode 100644 index 0000000..e6c8e4c --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clb8d1.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clb8d1_h__ +#define __gh100_clb8d1_h__ +#define NVB8D1_VIDEO_NVJPG (0x0000B8D1) +#endif // __gh100_clb8d1_h__ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clb8fa.h b/userspace/sdks/nv570/nvidia/inc/class/clb8fa.h new file mode 100644 index 0000000..19edb23 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clb8fa.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clb8fa_h_ +#define _clb8fa_h_ + +#define NVB8FA_VIDEO_OFA (0x0000B8FA) + +#endif /* _clb8fa_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc06f.h b/userspace/sdks/nv570/nvidia/inc/class/clc06f.h new file mode 100644 index 0000000..d8b8607 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc06f.h @@ -0,0 +1,312 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc06f_h_ +#define _clc06f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class PASCAL_CHANNEL_GPFIFO */ +/* + * Documentation for PASCAL_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + * Note there is no .mfs file for this class. + */ +#define PASCAL_CHANNEL_GPFIFO_A (0x0000C06F) + +#define NVC06F_TYPEDEF PASCAL_CHANNELChannelGPFifoA + +/* dma flow control data structure */ +typedef volatile struct Nvc06fControl_struct { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} Nvc06fControl, PascalAControlGPFifo; + +/* fields and values */ +#define NVC06F_NUMBER_OF_SUBCHANNELS (8) +#define NVC06F_SET_OBJECT (0x00000000) +#define NVC06F_SET_OBJECT_NVCLASS 15:0 +#define NVC06F_SET_OBJECT_ENGINE 20:16 +#define NVC06F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVC06F_ILLEGAL (0x00000004) +#define NVC06F_ILLEGAL_HANDLE 31:0 +#define NVC06F_NOP (0x00000008) +#define NVC06F_NOP_HANDLE 31:0 +#define NVC06F_SEMAPHOREA (0x00000010) +#define NVC06F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVC06F_SEMAPHOREB (0x00000014) +#define NVC06F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVC06F_SEMAPHOREC (0x00000018) +#define NVC06F_SEMAPHOREC_PAYLOAD 31:0 +#define NVC06F_SEMAPHORED (0x0000001C) +#define NVC06F_SEMAPHORED_OPERATION 4:0 +#define NVC06F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVC06F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVC06F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVC06F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVC06F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 +#define NVC06F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVC06F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVC06F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVC06F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVC06F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVC06F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVC06F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVC06F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVC06F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVC06F_SEMAPHORED_REDUCTION 30:27 +#define NVC06F_SEMAPHORED_REDUCTION_MIN 0x00000000 +#define NVC06F_SEMAPHORED_REDUCTION_MAX 0x00000001 +#define NVC06F_SEMAPHORED_REDUCTION_XOR 0x00000002 +#define NVC06F_SEMAPHORED_REDUCTION_AND 0x00000003 +#define NVC06F_SEMAPHORED_REDUCTION_OR 0x00000004 +#define NVC06F_SEMAPHORED_REDUCTION_ADD 0x00000005 +#define NVC06F_SEMAPHORED_REDUCTION_INC 0x00000006 +#define NVC06F_SEMAPHORED_REDUCTION_DEC 0x00000007 +#define NVC06F_SEMAPHORED_FORMAT 31:31 +#define NVC06F_SEMAPHORED_FORMAT_SIGNED 0x00000000 +#define NVC06F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 +#define NVC06F_NON_STALL_INTERRUPT (0x00000020) +#define NVC06F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVC06F_FB_FLUSH (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR +#define NVC06F_FB_FLUSH_HANDLE 31:0 +// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for +// specifying the page address for a targeted TLB invalidate and the uTLB for +// a targeted REPLAY_CANCEL for UVM. +// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly +// rearranged fields. +#define NVC06F_MEM_OP_A (0x00000028) +#define NVC06F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC06F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC06F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11 +#define NVC06F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001 +#define NVC06F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000 +#define NVC06F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12 +#define NVC06F_MEM_OP_B (0x0000002c) +#define NVC06F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0 +#define NVC06F_MEM_OP_C (0x00000030) +#define NVC06F_MEM_OP_C_MEMBAR_TYPE 2:0 +#define NVC06F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000 +#define NVC06F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE +// MEM_OP_D MUST be preceded by MEM_OPs A-C. +#define NVC06F_MEM_OP_D (0x00000034) +#define NVC06F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE +#define NVC06F_MEM_OP_D_OPERATION 31:27 +#define NVC06F_MEM_OP_D_OPERATION_MEMBAR 0x00000005 +#define NVC06F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVC06F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a +#define NVC06F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NVC06F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +// CLEAN_LINES is an alias for Tegra/GPU IP usage +#define NVC06F_MEM_OP_D_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e +// This B alias is confusing but it was missed as part of the update. Left here +// for compatibility. +#define NVC06F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e +#define NVC06F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVC06F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVC06F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015 +#define NVC06F_SET_REFERENCE (0x00000050) +#define NVC06F_SET_REFERENCE_COUNT 31:0 +// Syncpoint methods are only available on Tegra parts. Attempting to use +// them on discrete GPUs will result in Host raising NV_PPBDMA_INTR_0_METHOD. +#define NVC06F_SYNCPOINTA (0x00000070) +#define NVC06F_SYNCPOINTA_PAYLOAD 31:0 +#define NVC06F_SYNCPOINTB (0x00000074) +#define NVC06F_SYNCPOINTB_OPERATION 0:0 +#define NVC06F_SYNCPOINTB_OPERATION_WAIT 0x00000000 +#define NVC06F_SYNCPOINTB_OPERATION_INCR 0x00000001 +#define NVC06F_SYNCPOINTB_WAIT_SWITCH 4:4 +#define NVC06F_SYNCPOINTB_WAIT_SWITCH_DIS 0x00000000 +#define NVC06F_SYNCPOINTB_WAIT_SWITCH_EN 0x00000001 +#define NVC06F_SYNCPOINTB_SYNCPT_INDEX 19:8 +#define NVC06F_WFI (0x00000078) +#define NVC06F_WFI_SCOPE 0:0 +#define NVC06F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000 +#define NVC06F_WFI_SCOPE_ALL 0x00000001 +#define NVC06F_CRC_CHECK (0x0000007c) +#define NVC06F_CRC_CHECK_VALUE 31:0 +#define NVC06F_YIELD (0x00000080) +#define NVC06F_YIELD_OP 1:0 +#define NVC06F_YIELD_OP_NOP 0x00000000 +#define NVC06F_YIELD_OP_PBDMA_TIMESLICE 0x00000001 +#define NVC06F_YIELD_OP_RUNLIST_TIMESLICE 0x00000002 +#define NVC06F_YIELD_OP_TSG 0x00000003 + + +/* GPFIFO entry format */ +#define NVC06F_GP_ENTRY__SIZE 8 +#define NVC06F_GP_ENTRY0_FETCH 0:0 +#define NVC06F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVC06F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVC06F_GP_ENTRY0_GET 31:2 +#define NVC06F_GP_ENTRY0_OPERAND 31:0 +#define NVC06F_GP_ENTRY1_GET_HI 7:0 +#define NVC06F_GP_ENTRY1_PRIV 8:8 +#define NVC06F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NVC06F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NVC06F_GP_ENTRY1_LEVEL 9:9 +#define NVC06F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVC06F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVC06F_GP_ENTRY1_LENGTH 30:10 +#define NVC06F_GP_ENTRY1_SYNC 31:31 +#define NVC06F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVC06F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVC06F_GP_ENTRY1_OPCODE 7:0 +#define NVC06F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVC06F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVC06F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVC06F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVC06F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVC06F_DMA_METHOD_ADDRESS 11:0 +#define NVC06F_DMA_SUBDEVICE_MASK 15:4 +#define NVC06F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVC06F_DMA_TERT_OP 17:16 +#define NVC06F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVC06F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVC06F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVC06F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVC06F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVC06F_DMA_METHOD_COUNT_OLD 28:18 +#define NVC06F_DMA_METHOD_COUNT 28:16 +#define NVC06F_DMA_IMMD_DATA 28:16 +#define NVC06F_DMA_SEC_OP 31:29 +#define NVC06F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVC06F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVC06F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVC06F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVC06F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVC06F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVC06F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVC06F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVC06F_DMA_INCR_ADDRESS 11:0 +#define NVC06F_DMA_INCR_SUBCHANNEL 15:13 +#define NVC06F_DMA_INCR_COUNT 28:16 +#define NVC06F_DMA_INCR_OPCODE 31:29 +#define NVC06F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVC06F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVC06F_DMA_NONINCR_ADDRESS 11:0 +#define NVC06F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVC06F_DMA_NONINCR_COUNT 28:16 +#define NVC06F_DMA_NONINCR_OPCODE 31:29 +#define NVC06F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVC06F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVC06F_DMA_ONEINCR_ADDRESS 11:0 +#define NVC06F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVC06F_DMA_ONEINCR_COUNT 28:16 +#define NVC06F_DMA_ONEINCR_OPCODE 31:29 +#define NVC06F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVC06F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVC06F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVC06F_DMA_IMMD_ADDRESS 11:0 +#define NVC06F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVC06F_DMA_IMMD_DATA 28:16 +#define NVC06F_DMA_IMMD_OPCODE 31:29 +#define NVC06F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVC06F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVC06F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC06F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVC06F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVC06F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC06F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVC06F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC06F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVC06F_DMA_ENDSEG_OPCODE 31:29 +#define NVC06F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVC06F_DMA_ADDRESS 12:2 +#define NVC06F_DMA_SUBCH 15:13 +#define NVC06F_DMA_OPCODE3 17:16 +#define NVC06F_DMA_OPCODE3_NONE (0x00000000) +#define NVC06F_DMA_COUNT 28:18 +#define NVC06F_DMA_OPCODE 31:29 +#define NVC06F_DMA_OPCODE_METHOD (0x00000000) +#define NVC06F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVC06F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc06f_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc06fsw.h b/userspace/sdks/nv570/nvidia/inc/class/clc06fsw.h new file mode 100644 index 0000000..4e000c6 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc06fsw.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* This file is *not* auto-generated. */ + +#ifndef _clc06f_sw_h_ +#define _clc06f_sw_h_ + +#define NVC06F_NOTIFIERS_RC (0) +#define NVC06F_NOTIFIERS_REFCNT (1) +#define NVC06F_NOTIFIERS_NONSTALL (2) +#define NVC06F_NOTIFIERS_EVENTBUFFER (3) +#define NVC06F_NOTIFIERS_IDLECHANNEL (4) +#define NVC06F_NOTIFIERS_ENDCTX (5) +#define NVC06F_NOTIFIERS_SW (6) +#define NVC06F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVC06F_NOTIFIERS_REPLAYABLE_FAULT (8) +#define NVC06F_NOTIFIERS_MAXCOUNT (9) + +/* NvNotification[] fields and values */ +#define NVC06F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVC06F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _clc06f_sw_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc076.h b/userspace/sdks/nv570/nvidia/inc/class/clc076.h new file mode 100644 index 0000000..284c57a --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc076.h @@ -0,0 +1,82 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc076_h_ +#define _clc076_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define GP100_UVM_SW (0x0000c076) + +#define NVC076_SET_OBJECT (0x00000000) +#define NVC076_NO_OPERATION (0x00000100) + +/* Method data fields to support gpu fault cancel. These are pushed in order by UVM */ + +#define NVC076_FAULT_CANCEL_A (0x00000104) +#define NVC076_FAULT_CANCEL_A_INST_APERTURE 1:0 +#define NVC076_FAULT_CANCEL_A_INST_APERTURE_VID_MEM 0x00000000 +#define NVC076_FAULT_CANCEL_A_INST_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC076_FAULT_CANCEL_A_INST_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 + +/* instance pointer is 4k aligned so those bits are reused to store the aperture */ +#define NVC076_FAULT_CANCEL_A_INST_LOW 31:12 + +#define NVC076_FAULT_CANCEL_B (0x00000108) +#define NVC076_FAULT_CANCEL_B_INST_HI 31:0 + +#define NVC076_FAULT_CANCEL_C (0x0000010c) +#define NVC076_FAULT_CANCEL_C_CLIENT_ID 5:0 +#define NVC076_FAULT_CANCEL_C_GPC_ID 10:6 +#define NVC076_FAULT_CANCEL_C_MODE 31:30 +#define NVC076_FAULT_CANCEL_C_MODE_TARGETED 0x00000000 +#define NVC076_FAULT_CANCEL_C_MODE_GLOBAL 0x00000001 + +/* Method data fields to support clearing faulted bit. These are pushed in order by UVM */ + +#define NVC076_CLEAR_FAULTED_A (0x00000110) + +#define NVC076_CLEAR_FAULTED_A_INST_APERTURE 1:0 +#define NVC076_CLEAR_FAULTED_A_INST_APERTURE_VID_MEM 0x00000000 +#define NVC076_CLEAR_FAULTED_A_INST_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC076_CLEAR_FAULTED_A_INST_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 + +#define NVC076_CLEAR_FAULTED_A_TYPE 2:2 +#define NVC076_CLEAR_FAULTED_A_TYPE_PBDMA_FAULTED 0x00000000 +#define NVC076_CLEAR_FAULTED_A_TYPE_ENG_FAULTED 0x00000001 + +/* instance pointer is 4k aligned */ +#define NVC076_CLEAR_FAULTED_A_INST_LOW 31:12 + +#define NVC076_CLEAR_FAULTED_B (0x00000114) +#define NVC076_CLEAR_FAULTED_B_INST_HI 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc076_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc097.h b/userspace/sdks/nv570/nvidia/inc/class/clc097.h new file mode 100644 index 0000000..129056b --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc097.h @@ -0,0 +1,4191 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_pascal_a_h_ +#define _cl_pascal_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl pascal_a */ + +#include "nvtypes.h" + +#define PASCAL_A 0xC097 + +#define NVC097_SET_OBJECT 0x0000 +#define NVC097_SET_OBJECT_CLASS_ID 15:0 +#define NVC097_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC097_NO_OPERATION 0x0100 +#define NVC097_NO_OPERATION_V 31:0 + +#define NVC097_SET_NOTIFY_A 0x0104 +#define NVC097_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC097_SET_NOTIFY_B 0x0108 +#define NVC097_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC097_NOTIFY 0x010c +#define NVC097_NOTIFY_TYPE 31:0 +#define NVC097_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC097_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC097_WAIT_FOR_IDLE 0x0110 +#define NVC097_WAIT_FOR_IDLE_V 31:0 + +#define NVC097_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC097_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC097_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC097_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC097_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC097_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC097_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC097_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC097_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC097_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC097_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC097_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC097_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC097_SEND_GO_IDLE 0x013c +#define NVC097_SEND_GO_IDLE_V 31:0 + +#define NVC097_PM_TRIGGER 0x0140 +#define NVC097_PM_TRIGGER_V 31:0 + +#define NVC097_PM_TRIGGER_WFI 0x0144 +#define NVC097_PM_TRIGGER_WFI_V 31:0 + +#define NVC097_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC097_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC097_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC097_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC097_LINE_LENGTH_IN 0x0180 +#define NVC097_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC097_LINE_COUNT 0x0184 +#define NVC097_LINE_COUNT_VALUE 31:0 + +#define NVC097_OFFSET_OUT_UPPER 0x0188 +#define NVC097_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC097_OFFSET_OUT 0x018c +#define NVC097_OFFSET_OUT_VALUE 31:0 + +#define NVC097_PITCH_OUT 0x0190 +#define NVC097_PITCH_OUT_VALUE 31:0 + +#define NVC097_SET_DST_BLOCK_SIZE 0x0194 +#define NVC097_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC097_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC097_SET_DST_WIDTH 0x0198 +#define NVC097_SET_DST_WIDTH_V 31:0 + +#define NVC097_SET_DST_HEIGHT 0x019c +#define NVC097_SET_DST_HEIGHT_V 31:0 + +#define NVC097_SET_DST_DEPTH 0x01a0 +#define NVC097_SET_DST_DEPTH_V 31:0 + +#define NVC097_SET_DST_LAYER 0x01a4 +#define NVC097_SET_DST_LAYER_V 31:0 + +#define NVC097_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC097_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC097_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC097_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC097_LAUNCH_DMA 0x01b0 +#define NVC097_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC097_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC097_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC097_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC097_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC097_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC097_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC097_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC097_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC097_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC097_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC097_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC097_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC097_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC097_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC097_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC097_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC097_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC097_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC097_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC097_LOAD_INLINE_DATA 0x01b4 +#define NVC097_LOAD_INLINE_DATA_V 31:0 + +#define NVC097_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC097_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC097_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC097_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC097_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC097_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC097_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC097_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC097_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC097_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC097_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC097_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC097_RUN_DS_NOW 0x0200 +#define NVC097_RUN_DS_NOW_V 31:0 + +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC097_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC097_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC097_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC097_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC097_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC097_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_GS_DM_FIFO 0x0214 +#define NVC097_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC097_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC097_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC097_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC097_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC097_INVALIDATE_SHADER_CACHES 0x021c +#define NVC097_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC097_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC097_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC097_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC097_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC097_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC097_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC097_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC097_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC097_INCREMENT_SYNC_POINT 0x02c8 +#define NVC097_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC097_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC097_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC097_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC097_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC097_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC097_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NVC097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NVC097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 21:0 + +#define NVC097_DECOMPRESS_SURFACE 0x02e0 +#define NVC097_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC097_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC097_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC097_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC097_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC097_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC097_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC097_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC097_SET_ZCULL_SUBREGION 0x02e8 +#define NVC097_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC097_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC097_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC097_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC097_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC097_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC097_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC097_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC097_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC097_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC097_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC097_DRAW_ZERO_INDEX 0x0304 +#define NVC097_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC097_SET_L1_CONFIGURATION 0x0308 +#define NVC097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC097_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC097_SET_SPA_VERSION 0x0310 +#define NVC097_SET_SPA_VERSION_MINOR 7:0 +#define NVC097_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC097_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NVC097_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NVC097_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_SNAP_GRID_LINE 0x0318 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC097_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC097_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC097_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC097_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC097_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC097_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC097_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC097_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC097_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC097_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC097_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC097_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC097_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC097_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC097_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC097_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC097_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC097_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC097_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC097_RESERVED_TG07 0x033c +#define NVC097_RESERVED_TG07_V 0:0 + +#define NVC097_RESERVED_TG08 0x0340 +#define NVC097_RESERVED_TG08_V 0:0 + +#define NVC097_RESERVED_TG09 0x0344 +#define NVC097_RESERVED_TG09_V 0:0 + +#define NVC097_RESERVED_TG10 0x0348 +#define NVC097_RESERVED_TG10_V 0:0 + +#define NVC097_RESERVED_TG11 0x034c +#define NVC097_RESERVED_TG11_V 0:0 + +#define NVC097_RESERVED_TG12 0x0350 +#define NVC097_RESERVED_TG12_V 0:0 + +#define NVC097_RESERVED_TG13 0x0354 +#define NVC097_RESERVED_TG13_V 0:0 + +#define NVC097_RESERVED_TG14 0x0358 +#define NVC097_RESERVED_TG14_V 0:0 + +#define NVC097_RESERVED_TG15 0x035c +#define NVC097_RESERVED_TG15_V 0:0 + +#define NVC097_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC097_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC097_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC097_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC097_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC097_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC097_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC097_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC097_SET_RASTER_ENABLE 0x037c +#define NVC097_SET_RASTER_ENABLE_V 0:0 +#define NVC097_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC097_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC097_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC097_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC097_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC097_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC097_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC097_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC097_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC097_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC097_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC097_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC097_SET_RASTER_INPUT 0x0740 +#define NVC097_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC097_SET_STREAM_OUTPUT 0x0744 +#define NVC097_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC097_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_ALPHA_FRACTION 0x074c +#define NVC097_SET_ALPHA_FRACTION_V 7:0 + +#define NVC097_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC097_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC097_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC097_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC097_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC097_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC097_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC097_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC097_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC097_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC097_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC097_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC097_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC097_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC097_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC097_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC097_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC097_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC097_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC097_SET_ISBE_SAVE_RESTORE_PROGRAM 0x07ac +#define NVC097_SET_ISBE_SAVE_RESTORE_PROGRAM_OFFSET 31:0 + +#define NVC097_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC097_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC097_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC097_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC097_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC097_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC097_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC097_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC097_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC097_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC097_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC097_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC097_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC097_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC097_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC097_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC097_SET_ZCULL_STORAGE_B 0x07ec +#define NVC097_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC097_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC097_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC097_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC097_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC097_SET_ZT_READ_ONLY 0x07f8 +#define NVC097_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC097_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC097_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC097_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC097_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC097_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC097_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC097_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC097_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC097_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC097_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC097_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC097_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC097_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC097_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC097_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC097_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC097_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC097_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC097_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC097_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC097_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC097_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC097_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC097_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC097_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC097_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC097_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC097_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC097_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC097_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC097_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC097_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NVC097_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NVC097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVC097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVC097_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC097_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC097_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC097_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC097_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC097_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC097_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC097_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC097_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC097_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC097_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC097_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC097_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC097_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC097_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC097_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC097_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC097_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC097_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC097_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC097_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC097_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC097_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC097_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC097_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC097_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC097_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC097_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC097_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC097_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC097_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC097_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC097_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC097_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC097_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC097_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC097_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC097_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC097_SET_STATISTICS_COUNTER 0x0d68 +#define NVC097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC097_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC097_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC097_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC097_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC097_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC097_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC097_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC097_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC097_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC097_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC097_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC097_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC097_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC097_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC097_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC097_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC097_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC097_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC097_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC097_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC097_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC097_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC097_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC097_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC097_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC097_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC097_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC097_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC097_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC097_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC097_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC097_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC097_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC097_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC097_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC097_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC097_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC097_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC097_SET_POLY_SMOOTH 0x0db4 +#define NVC097_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC097_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_ZT_MARK 0x0db8 +#define NVC097_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NVC097_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVC097_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVC097_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC097_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC097_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC097_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC097_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC097_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC097_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC097_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC097_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_PATCH 0x0dcc +#define NVC097_SET_PATCH_SIZE 7:0 + +#define NVC097_SET_ITERATED_BLEND 0x0dd0 +#define NVC097_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC097_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC097_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC097_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC097_SET_ZCULL_CRITERION 0x0dd8 +#define NVC097_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC097_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC097_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC097_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC097_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC097_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC097_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC097_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC097_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC097_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC097_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC097_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC097_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC097_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC097_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC097_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC097_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC097_SET_SCISSOR_ENABLE_V 0:0 +#define NVC097_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC097_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC097_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC097_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC097_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC097_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC097_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0f10 +#define NVC097_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVC097_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVC097_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVC097_SET_VPC_PERF_KNOB 0x0f14 +#define NVC097_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC097_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC097_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC097_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC097_PM_LOCAL_TRIGGER 0x0f18 +#define NVC097_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC097_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC097_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC097_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC097_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC097_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC097_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC097_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC097_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC097_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC097_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC097_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC097_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC097_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC097_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC097_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC097_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC097_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC097_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC097_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC097_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC097_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC097_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC097_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC097_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC097_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC097_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC097_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC097_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC097_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC097_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC097_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC097_SET_SAMPLE_MASK 0x0fa4 +#define NVC097_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC097_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC097_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC097_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC097_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC097_SET_CT_MRT_ENABLE 0x0fac +#define NVC097_SET_CT_MRT_ENABLE_V 0:0 +#define NVC097_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC097_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC097_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC097_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC097_SET_TIR 0x0fb4 +#define NVC097_SET_TIR_MODE 1:0 +#define NVC097_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC097_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC097_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC097_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC097_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC097_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC097_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC097_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC097_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC097_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC097_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC097_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC097_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC097_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC097_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC097_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC097_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC097_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC097_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC097_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_TIR_MODULATION 0x0fd4 +#define NVC097_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC097_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC097_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC097_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC097_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC097_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC097_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC097_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC097_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC097_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC097_SET_ZT_A 0x0fe0 +#define NVC097_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_ZT_B 0x0fe4 +#define NVC097_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_ZT_FORMAT 0x0fe8 +#define NVC097_SET_ZT_FORMAT_V 4:0 +#define NVC097_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC097_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC097_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC097_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC097_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC097_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC097_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC097_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC097_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC097_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC097_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC097_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC097_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC097_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC097_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC097_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC097_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC097_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC097_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC097_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC097_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC097_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC097_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC097_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC097_SET_TILED_CACHE_BUNDLE_CONTROL 0x0ffc +#define NVC097_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT 0:0 +#define NVC097_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_FALSE 0x00000000 +#define NVC097_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_TRUE 0x00000001 + +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC097_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC097_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC097_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC097_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC097_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC097_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC097_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC097_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC097_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC097_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC097_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC097_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC097_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD02 0x102c +#define NVC097_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC097_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC097_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC097_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC097_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC097_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC097_SET_SPARE_NOOP01 0x1044 +#define NVC097_SET_SPARE_NOOP01_V 31:0 + +#define NVC097_SET_SPARE_NOOP02 0x1048 +#define NVC097_SET_SPARE_NOOP02_V 31:0 + +#define NVC097_SET_SPARE_NOOP03 0x104c +#define NVC097_SET_SPARE_NOOP03_V 31:0 + +#define NVC097_SET_SPARE_NOOP04 0x1050 +#define NVC097_SET_SPARE_NOOP04_V 31:0 + +#define NVC097_SET_SPARE_NOOP05 0x1054 +#define NVC097_SET_SPARE_NOOP05_V 31:0 + +#define NVC097_SET_SPARE_NOOP06 0x1058 +#define NVC097_SET_SPARE_NOOP06_V 31:0 + +#define NVC097_SET_SPARE_NOOP07 0x105c +#define NVC097_SET_SPARE_NOOP07_V 31:0 + +#define NVC097_SET_SPARE_NOOP08 0x1060 +#define NVC097_SET_SPARE_NOOP08_V 31:0 + +#define NVC097_SET_SPARE_NOOP09 0x1064 +#define NVC097_SET_SPARE_NOOP09_V 31:0 + +#define NVC097_SET_SPARE_NOOP10 0x1068 +#define NVC097_SET_SPARE_NOOP10_V 31:0 + +#define NVC097_SET_SPARE_NOOP11 0x106c +#define NVC097_SET_SPARE_NOOP11_V 31:0 + +#define NVC097_SET_SPARE_NOOP12 0x1070 +#define NVC097_SET_SPARE_NOOP12_V 31:0 + +#define NVC097_SET_SPARE_NOOP13 0x1074 +#define NVC097_SET_SPARE_NOOP13_V 31:0 + +#define NVC097_SET_SPARE_NOOP14 0x1078 +#define NVC097_SET_SPARE_NOOP14_V 31:0 + +#define NVC097_SET_SPARE_NOOP15 0x107c +#define NVC097_SET_SPARE_NOOP15_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC097_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC097_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC097_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC097_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC097_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC097_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC097_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC097_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC097_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC097_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC097_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC097_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC097_UNBIND_ALL 0x10f4 +#define NVC097_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC097_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC097_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC097_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC097_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC097_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC097_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC097_NO_OPERATION_DATA_HI 0x110c +#define NVC097_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC097_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC097_PM_TRIGGER_END 0x1114 +#define NVC097_PM_TRIGGER_END_V 31:0 + +#define NVC097_SET_VERTEX_ID_BASE 0x1118 +#define NVC097_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC097_SET_STENCIL_COMPRESSION 0x111c +#define NVC097_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC097_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC097_SET_TIR_CONTROL 0x1130 +#define NVC097_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC097_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC097_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC097_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC097_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC097_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC097_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC097_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC097_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 + +#define NVC097_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC097_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC097_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC097_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC097_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC097_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC097_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC097_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC097_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC097_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC097_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC097_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC097_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC097_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC097_FLUSH_PENDING_WRITES 0x1144 +#define NVC097_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC097_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC097_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC097_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC097_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC097_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC097_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC097_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC097_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC097_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC097_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC097_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC097_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC097_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC097_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC097_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC097_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC097_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC097_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC097_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC097_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC097_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC097_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_SCREEN_STATE_MASK 0x1204 +#define NVC097_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC097_SET_ZT_SPARSE 0x1208 +#define NVC097_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC097_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC097_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC097_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC097_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC097_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_SET_CT_SELECT 0x121c +#define NVC097_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC097_SET_CT_SELECT_TARGET0 6:4 +#define NVC097_SET_CT_SELECT_TARGET1 9:7 +#define NVC097_SET_CT_SELECT_TARGET2 12:10 +#define NVC097_SET_CT_SELECT_TARGET3 15:13 +#define NVC097_SET_CT_SELECT_TARGET4 18:16 +#define NVC097_SET_CT_SELECT_TARGET5 21:19 +#define NVC097_SET_CT_SELECT_TARGET6 24:22 +#define NVC097_SET_CT_SELECT_TARGET7 27:25 + +#define NVC097_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC097_SET_ZT_SIZE_A 0x1228 +#define NVC097_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC097_SET_ZT_SIZE_B 0x122c +#define NVC097_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC097_SET_ZT_SIZE_C 0x1230 +#define NVC097_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC097_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC097_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC097_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC097_SET_SAMPLER_BINDING 0x1234 +#define NVC097_SET_SAMPLER_BINDING_V 0:0 +#define NVC097_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC097_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC097_DRAW_AUTO 0x123c +#define NVC097_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC097_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC097_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC097_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC097_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC097_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC097_SET_BACK_END_COPY_A 0x1264 +#define NVC097_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC097_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC097_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC097_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC097_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BACK_END_COPY_B 0x1268 +#define NVC097_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC097_SET_BACK_END_COPY_C 0x126c +#define NVC097_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC097_SET_BACK_END_COPY_D 0x1270 +#define NVC097_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC097_SET_BACK_END_COPY_E 0x1274 +#define NVC097_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC097_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC097_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 21:0 + +#define NVC097_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC097_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC097_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC097_CLEAR_ZCULL_REGION 0x12c8 +#define NVC097_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC097_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC097_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC097_SET_DEPTH_TEST 0x12cc +#define NVC097_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC097_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC097_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_FILL_MODE 0x12d0 +#define NVC097_SET_FILL_MODE_V 31:0 +#define NVC097_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC097_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC097_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC097_SET_SHADE_MODE 0x12d4 +#define NVC097_SET_SHADE_MODE_V 31:0 +#define NVC097_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC097_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC097_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC097_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC097_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC097_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC097_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_DEPTH_WRITE 0x12e8 +#define NVC097_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC097_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_ALPHA_TEST 0x12ec +#define NVC097_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC097_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC097_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC097_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC097_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC097_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC097_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC097_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC097_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC097_D3D_SET_CULL_MODE 0x1308 +#define NVC097_D3D_SET_CULL_MODE_V 31:0 +#define NVC097_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC097_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC097_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC097_SET_DEPTH_FUNC 0x130c +#define NVC097_SET_DEPTH_FUNC_V 31:0 +#define NVC097_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC097_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC097_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC097_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC097_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC097_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC097_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC097_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC097_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC097_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC097_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC097_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC097_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC097_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC097_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC097_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC097_SET_ALPHA_REF 0x1310 +#define NVC097_SET_ALPHA_REF_V 31:0 + +#define NVC097_SET_ALPHA_FUNC 0x1314 +#define NVC097_SET_ALPHA_FUNC_V 31:0 +#define NVC097_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC097_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC097_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC097_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC097_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC097_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC097_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC097_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC097_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC097_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC097_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC097_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC097_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC097_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC097_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC097_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC097_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC097_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC097_SET_BLEND_CONST_RED 0x131c +#define NVC097_SET_BLEND_CONST_RED_V 31:0 + +#define NVC097_SET_BLEND_CONST_GREEN 0x1320 +#define NVC097_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC097_SET_BLEND_CONST_BLUE 0x1324 +#define NVC097_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC097_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC097_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC097_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC097_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC097_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC097_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC097_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC097_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BLEND_COLOR_OP 0x1340 +#define NVC097_SET_BLEND_COLOR_OP_V 31:0 +#define NVC097_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC097_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC097_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC097_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC097_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC097_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC097_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC097_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC097_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC097_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_BLEND_ALPHA_OP 0x134c +#define NVC097_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC097_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC097_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC097_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC097_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC097_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC097_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC097_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC097_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC097_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC097_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC097_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC097_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BLEND(i) (0x1360+(i)*4) +#define NVC097_SET_BLEND_ENABLE 0:0 +#define NVC097_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_STENCIL_TEST 0x1380 +#define NVC097_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC097_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_STENCIL_OP_FAIL 0x1384 +#define NVC097_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC097_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC097_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC097_SET_STENCIL_OP_ZPASS 0x138c +#define NVC097_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC097_SET_STENCIL_FUNC 0x1390 +#define NVC097_SET_STENCIL_FUNC_V 31:0 +#define NVC097_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC097_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC097_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC097_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC097_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC097_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC097_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC097_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC097_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC097_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC097_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC097_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC097_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC097_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC097_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC097_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC097_SET_STENCIL_FUNC_REF 0x1394 +#define NVC097_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC097_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC097_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC097_SET_STENCIL_MASK 0x139c +#define NVC097_SET_STENCIL_MASK_V 7:0 + +#define NVC097_SET_DRAW_AUTO_START 0x13a4 +#define NVC097_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC097_SET_PS_SATURATE 0x13a8 +#define NVC097_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC097_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC097_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC097_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC097_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC097_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC097_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC097_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC097_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC097_SET_WINDOW_ORIGIN 0x13ac +#define NVC097_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC097_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC097_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC097_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC097_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC097_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC097_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC097_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC097_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC097_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC097_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_ALPHA_HYSTERESIS 0x1420 +#define NVC097_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NVC097_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC097_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC097_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC097_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC097_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC097_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC097_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC097_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC097_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC097_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC097_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC097_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC097_STORE_ZCULL 0x1464 +#define NVC097_STORE_ZCULL_V 0:0 + +#define NVC097_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC097_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC097_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC097_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC097_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC097_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC097_LOAD_ZCULL 0x1500 +#define NVC097_LOAD_ZCULL_V 0:0 + +#define NVC097_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC097_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC097_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC097_SET_USER_CLIP_ENABLE 0x1510 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC097_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC097_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC097_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_POINT_SIZE 0x1518 +#define NVC097_SET_POINT_SIZE_V 31:0 + +#define NVC097_SET_ZCULL_STATS 0x151c +#define NVC097_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC097_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_POINT_SPRITE 0x1520 +#define NVC097_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC097_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC097_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC097_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC097_CLEAR_REPORT_VALUE 0x1530 +#define NVC097_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC097_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC097_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC097_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC097_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 + +#define NVC097_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC097_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC097_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_ZT_SELECT 0x1538 +#define NVC097_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC097_SET_RENDER_ENABLE_A 0x1550 +#define NVC097_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_RENDER_ENABLE_B 0x1554 +#define NVC097_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_RENDER_ENABLE_C 0x1558 +#define NVC097_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC097_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC097_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC097_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC097_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC097_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC097_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC097_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC097_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC097_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC097_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC097_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC097_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC097_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC097_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_TEX_HEADER_POOL_C 0x157c +#define NVC097_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC097_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC097_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC097_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC097_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC097_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC097_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC097_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC097_SET_SRGB_WRITE 0x15b8 +#define NVC097_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC097_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_DEPTH_BIAS 0x15bc +#define NVC097_SET_DEPTH_BIAS_V 31:0 + +#define NVC097_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC097_SET_RT_LAYER 0x15cc +#define NVC097_SET_RT_LAYER_V 15:0 +#define NVC097_SET_RT_LAYER_CONTROL 16:16 +#define NVC097_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC097_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC097_SET_ANTI_ALIAS 0x15d0 +#define NVC097_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC097_SET_EDGE_FLAG 0x15e4 +#define NVC097_SET_EDGE_FLAG_V 0:0 +#define NVC097_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC097_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC097_DRAW_INLINE_INDEX 0x15e8 +#define NVC097_DRAW_INLINE_INDEX_V 31:0 + +#define NVC097_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC097_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC097_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC097_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC097_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC097_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC097_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC097_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC097_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC097_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC097_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC097_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC097_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC097_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC097_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC097_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC097_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC097_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC097_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC097_SET_PROGRAM_REGION_A 0x1608 +#define NVC097_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVC097_SET_PROGRAM_REGION_B 0x160c +#define NVC097_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVC097_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC097_END 0x1614 +#define NVC097_END_V 0:0 + +#define NVC097_BEGIN 0x1618 +#define NVC097_BEGIN_OP 15:0 +#define NVC097_BEGIN_OP_POINTS 0x00000000 +#define NVC097_BEGIN_OP_LINES 0x00000001 +#define NVC097_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC097_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC097_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC097_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC097_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC097_BEGIN_OP_QUADS 0x00000007 +#define NVC097_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC097_BEGIN_OP_POLYGON 0x00000009 +#define NVC097_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC097_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC097_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_BEGIN_OP_PATCH 0x0000000E +#define NVC097_BEGIN_PRIMITIVE_ID 24:24 +#define NVC097_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC097_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC097_BEGIN_INSTANCE_ID 27:26 +#define NVC097_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC097_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC097_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC097_BEGIN_SPLIT_MODE 30:29 +#define NVC097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC097_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC097_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 + +#define NVC097_SET_VERTEX_ID_COPY 0x161c +#define NVC097_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC097_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC097_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC097_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC097_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC097_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC097_LOAD_PRIMITIVE_ID 0x1624 +#define NVC097_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC097_SET_SHADER_BASED_CULL 0x162c +#define NVC097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_CLASS_VERSION 0x1638 +#define NVC097_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC097_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC097_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC097_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC097_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC097_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC097_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC097_SET_DA_OUTPUT 0x164c +#define NVC097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC097_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC097_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC097_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_POINT_CENTER_MODE 0x165c +#define NVC097_SET_POINT_CENTER_MODE_V 31:0 +#define NVC097_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC097_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC097_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC097_SET_LINE_STIPPLE 0x166c +#define NVC097_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC097_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC097_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC097_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC097_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC097_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC097_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC097_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC097_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC097_SET_PROVOKING_VERTEX 0x1684 +#define NVC097_SET_PROVOKING_VERTEX_V 0:0 +#define NVC097_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC097_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC097_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC097_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC097_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_POLYGON_STIPPLE 0x168c +#define NVC097_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC097_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_SHADER_CONTROL 0x1690 +#define NVC097_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC097_CHECK_CLASS_VERSION 0x16a0 +#define NVC097_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC097_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC097_SET_SPH_VERSION 0x16a4 +#define NVC097_SET_SPH_VERSION_CURRENT 15:0 +#define NVC097_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC097_CHECK_SPH_VERSION 0x16a8 +#define NVC097_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC097_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC097_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC097_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC097_SET_AAM_VERSION 0x1790 +#define NVC097_SET_AAM_VERSION_CURRENT 15:0 +#define NVC097_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC097_CHECK_AAM_VERSION 0x1794 +#define NVC097_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC097_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC097_SET_ZT_LAYER 0x179c +#define NVC097_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC097_SET_INDEX_BUFFER_A 0x17c8 +#define NVC097_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC097_SET_INDEX_BUFFER_B 0x17cc +#define NVC097_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC097_SET_INDEX_BUFFER_C 0x17d0 +#define NVC097_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC097_SET_INDEX_BUFFER_D 0x17d4 +#define NVC097_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC097_SET_INDEX_BUFFER_E 0x17d8 +#define NVC097_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC097_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC097_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC097_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC097_SET_INDEX_BUFFER_F 0x17dc +#define NVC097_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC097_DRAW_INDEX_BUFFER 0x17e0 +#define NVC097_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC097_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC097_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC097_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC097_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC097_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC097_OGL_SET_CULL 0x1918 +#define NVC097_OGL_SET_CULL_ENABLE 0:0 +#define NVC097_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC097_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC097_OGL_SET_FRONT_FACE 0x191c +#define NVC097_OGL_SET_FRONT_FACE_V 31:0 +#define NVC097_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC097_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC097_OGL_SET_CULL_FACE 0x1920 +#define NVC097_OGL_SET_CULL_FACE_V 31:0 +#define NVC097_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC097_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC097_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC097_SET_VIEWPORT_PIXEL 0x1924 +#define NVC097_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC097_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC097_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC097_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC097_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC097_SET_USER_CLIP_OP 0x1940 +#define NVC097_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC097_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC097_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC097_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC097_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC097_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC097_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC097_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC097_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC097_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC097_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC097_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC097_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC097_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC097_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC097_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC097_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC097_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC097_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC097_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC097_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC097_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC097_INVALIDATE_ZCULL 0x1958 +#define NVC097_INVALIDATE_ZCULL_V 31:0 +#define NVC097_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC097_SET_ZCULL 0x1968 +#define NVC097_SET_ZCULL_Z_ENABLE 0:0 +#define NVC097_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC097_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_ZCULL_BOUNDS 0x196c +#define NVC097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC097_ZCULL_SYNC 0x1978 +#define NVC097_ZCULL_SYNC_V 31:0 + +#define NVC097_SET_CLIP_ID_TEST 0x197c +#define NVC097_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC097_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC097_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC097_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC097_SET_CLIP_ID 0x1984 +#define NVC097_SET_CLIP_ID_V 31:0 + +#define NVC097_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC097_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC097_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC097_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC097_SET_LOGIC_OP 0x19c4 +#define NVC097_SET_LOGIC_OP_ENABLE 0:0 +#define NVC097_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC097_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC097_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC097_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC097_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC097_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC097_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC097_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC097_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC097_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC097_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC097_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC097_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC097_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC097_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC097_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC097_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC097_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC097_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC097_SET_Z_COMPRESSION 0x19cc +#define NVC097_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC097_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC097_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC097_CLEAR_SURFACE 0x19d0 +#define NVC097_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC097_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC097_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC097_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC097_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC097_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC097_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC097_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC097_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC097_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC097_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC097_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC097_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC097_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC097_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC097_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC097_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC097_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC097_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC097_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC097_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC097_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC097_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC097_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC097_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC097_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC097_PIPE_NOP 0x1a2c +#define NVC097_PIPE_NOP_V 31:0 + +#define NVC097_SET_SPARE00 0x1a30 +#define NVC097_SET_SPARE00_V 31:0 + +#define NVC097_SET_SPARE01 0x1a34 +#define NVC097_SET_SPARE01_V 31:0 + +#define NVC097_SET_SPARE02 0x1a38 +#define NVC097_SET_SPARE02_V 31:0 + +#define NVC097_SET_SPARE03 0x1a3c +#define NVC097_SET_SPARE03_V 31:0 + +#define NVC097_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC097_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC097_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC097_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC097_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC097_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC097_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC097_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC097_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC097_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC097_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC097_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC097_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC097_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC097_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC097_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC097_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC097_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC097_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC097_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC097_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC097_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC097_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVC097_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVC097_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVC097_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVC097_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVC097_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVC097_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVC097_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVC097_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC097_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC097_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC097_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC097_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC097_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC097_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC097_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC097_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC097_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC097_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC097_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NVC097_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NVC097_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC097_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC097_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC097_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NVC097_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC097_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC097_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NVC097_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVC097_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NVC097_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NVC097_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVC097_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVC097_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC097_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC097_SET_FALCON00 0x2300 +#define NVC097_SET_FALCON00_V 31:0 + +#define NVC097_SET_FALCON01 0x2304 +#define NVC097_SET_FALCON01_V 31:0 + +#define NVC097_SET_FALCON02 0x2308 +#define NVC097_SET_FALCON02_V 31:0 + +#define NVC097_SET_FALCON03 0x230c +#define NVC097_SET_FALCON03_V 31:0 + +#define NVC097_SET_FALCON04 0x2310 +#define NVC097_SET_FALCON04_V 31:0 + +#define NVC097_SET_FALCON05 0x2314 +#define NVC097_SET_FALCON05_V 31:0 + +#define NVC097_SET_FALCON06 0x2318 +#define NVC097_SET_FALCON06_V 31:0 + +#define NVC097_SET_FALCON07 0x231c +#define NVC097_SET_FALCON07_V 31:0 + +#define NVC097_SET_FALCON08 0x2320 +#define NVC097_SET_FALCON08_V 31:0 + +#define NVC097_SET_FALCON09 0x2324 +#define NVC097_SET_FALCON09_V 31:0 + +#define NVC097_SET_FALCON10 0x2328 +#define NVC097_SET_FALCON10_V 31:0 + +#define NVC097_SET_FALCON11 0x232c +#define NVC097_SET_FALCON11_V 31:0 + +#define NVC097_SET_FALCON12 0x2330 +#define NVC097_SET_FALCON12_V 31:0 + +#define NVC097_SET_FALCON13 0x2334 +#define NVC097_SET_FALCON13_V 31:0 + +#define NVC097_SET_FALCON14 0x2338 +#define NVC097_SET_FALCON14_V 31:0 + +#define NVC097_SET_FALCON15 0x233c +#define NVC097_SET_FALCON15_V 31:0 + +#define NVC097_SET_FALCON16 0x2340 +#define NVC097_SET_FALCON16_V 31:0 + +#define NVC097_SET_FALCON17 0x2344 +#define NVC097_SET_FALCON17_V 31:0 + +#define NVC097_SET_FALCON18 0x2348 +#define NVC097_SET_FALCON18_V 31:0 + +#define NVC097_SET_FALCON19 0x234c +#define NVC097_SET_FALCON19_V 31:0 + +#define NVC097_SET_FALCON20 0x2350 +#define NVC097_SET_FALCON20_V 31:0 + +#define NVC097_SET_FALCON21 0x2354 +#define NVC097_SET_FALCON21_V 31:0 + +#define NVC097_SET_FALCON22 0x2358 +#define NVC097_SET_FALCON22_V 31:0 + +#define NVC097_SET_FALCON23 0x235c +#define NVC097_SET_FALCON23_V 31:0 + +#define NVC097_SET_FALCON24 0x2360 +#define NVC097_SET_FALCON24_V 31:0 + +#define NVC097_SET_FALCON25 0x2364 +#define NVC097_SET_FALCON25_V 31:0 + +#define NVC097_SET_FALCON26 0x2368 +#define NVC097_SET_FALCON26_V 31:0 + +#define NVC097_SET_FALCON27 0x236c +#define NVC097_SET_FALCON27_V 31:0 + +#define NVC097_SET_FALCON28 0x2370 +#define NVC097_SET_FALCON28_V 31:0 + +#define NVC097_SET_FALCON29 0x2374 +#define NVC097_SET_FALCON29_V 31:0 + +#define NVC097_SET_FALCON30 0x2378 +#define NVC097_SET_FALCON30_V 31:0 + +#define NVC097_SET_FALCON31 0x237c +#define NVC097_SET_FALCON31_V 31:0 + +#define NVC097_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC097_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC097_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC097_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC097_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC097_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC097_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC097_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC097_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC097_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC097_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC097_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC097_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC097_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC097_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC097_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC097_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC097_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC097_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC097_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC097_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC097_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC097_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC097_SET_COLOR_CLAMP 0x2600 +#define NVC097_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC097_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC097_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BINDLESS_TEXTURE 0x2608 +#define NVC097_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVC097_SET_TRAP_HANDLER 0x260c +#define NVC097_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVC097_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC097_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC097_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC097_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC097_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC097_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC097_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC097_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC097_CALL_MME_MACRO_V 31:0 + +#define NVC097_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC097_CALL_MME_DATA_V 31:0 + +#endif /* _cl_pascal_a_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc097tex.h b/userspace/sdks/nv570/nvidia/inc/class/clc097tex.h new file mode 100644 index 0000000..7c5a822 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc097tex.h @@ -0,0 +1,1353 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2010 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLC097TEX_H__ +#define __CLC097TEX_H__ + +/* +** Texture Header State Blocklinear + */ + +#define NVC097_TEXHEAD_BL_COMPONENTS MW(6:0) +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R32 0x0000000f +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R16 0x0000001b +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R8 0x0000001d +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R1 0x0000001f +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_EAC 0x00000019 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_Z16 0x0000003a +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVC097_TEXHEAD_BL_R_DATA_TYPE MW(9:7) +#define NVC097_TEXHEAD_BL_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_BL_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_BL_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_BL_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_BL_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_BL_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_BL_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BL_G_DATA_TYPE MW(12:10) +#define NVC097_TEXHEAD_BL_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_BL_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_BL_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_BL_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_BL_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_BL_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_BL_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BL_B_DATA_TYPE MW(15:13) +#define NVC097_TEXHEAD_BL_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_BL_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_BL_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_BL_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_BL_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_BL_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_BL_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BL_A_DATA_TYPE MW(18:16) +#define NVC097_TEXHEAD_BL_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_BL_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_BL_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_BL_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_BL_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_BL_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_BL_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BL_X_SOURCE MW(21:19) +#define NVC097_TEXHEAD_BL_X_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_BL_X_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_BL_X_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_BL_X_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_BL_X_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_BL_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_BL_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BL_Y_SOURCE MW(24:22) +#define NVC097_TEXHEAD_BL_Y_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_BL_Y_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_BL_Y_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_BL_Y_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_BL_Y_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_BL_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_BL_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BL_Z_SOURCE MW(27:25) +#define NVC097_TEXHEAD_BL_Z_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_BL_Z_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_BL_Z_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_BL_Z_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_BL_Z_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_BL_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_BL_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BL_W_SOURCE MW(30:28) +#define NVC097_TEXHEAD_BL_W_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_BL_W_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_BL_W_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_BL_W_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_BL_W_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_BL_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_BL_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BL_PACK_COMPONENTS MW(31:31) +#define NVC097_TEXHEAD_BL_RESERVED1Y MW(36:32) +#define NVC097_TEXHEAD_BL_GOB_DEPTH_OFFSET MW(38:37) +#define NVC097_TEXHEAD_BL_RESERVED1X MW(40:39) +#define NVC097_TEXHEAD_BL_ADDRESS_BITS31TO9 MW(63:41) +#define NVC097_TEXHEAD_BL_ADDRESS_BITS48TO32 MW(80:64) +#define NVC097_TEXHEAD_BL_RESERVED_ADDRESS MW(84:81) +#define NVC097_TEXHEAD_BL_HEADER_VERSION MW(87:85) +#define NVC097_TEXHEAD_BL_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVC097_TEXHEAD_BL_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVC097_TEXHEAD_BL_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVC097_TEXHEAD_BL_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVC097_TEXHEAD_BL_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVC097_TEXHEAD_BL_RESERVED_HEADER_VERSION MW(88:88) +#define NVC097_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVC097_TEXHEAD_BL_RESERVED2A MW(95:93) +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_WIDTH MW(98:96) +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT MW(101:99) +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH MW(104:102) +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC097_TEXHEAD_BL_RESERVED3Y MW(105:105) +#define NVC097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS MW(108:106) +#define NVC097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVC097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVC097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVC097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVC097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVC097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVC097_TEXHEAD_BL_GOB3D MW(109:109) +#define NVC097_TEXHEAD_BL_RESERVED3Z MW(111:110) +#define NVC097_TEXHEAD_BL_LOD_ANISO_QUALITY2 MW(112:112) +#define NVC097_TEXHEAD_BL_LOD_ANISO_QUALITY MW(113:113) +#define NVC097_TEXHEAD_BL_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC097_TEXHEAD_BL_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC097_TEXHEAD_BL_LOD_ISO_QUALITY MW(114:114) +#define NVC097_TEXHEAD_BL_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC097_TEXHEAD_BL_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC097_TEXHEAD_BL_ANISO_SPREAD_SCALE MW(121:117) +#define NVC097_TEXHEAD_BL_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVC097_TEXHEAD_BL_DEPTH_TEXTURE MW(123:123) +#define NVC097_TEXHEAD_BL_MAX_MIP_LEVEL MW(127:124) +#define NVC097_TEXHEAD_BL_WIDTH_MINUS_ONE MW(144:128) +#define NVC097_TEXHEAD_BL_DEPTH_MINUS_ONE_BIT14 MW(145:145) +#define NVC097_TEXHEAD_BL_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVC097_TEXHEAD_BL_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVC097_TEXHEAD_BL_S_R_G_B_CONVERSION MW(150:150) +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE MW(154:151) +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVC097_TEXHEAD_BL_SECTOR_PROMOTION MW(156:155) +#define NVC097_TEXHEAD_BL_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVC097_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVC097_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVC097_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVC097_TEXHEAD_BL_BORDER_SIZE MW(159:157) +#define NVC097_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVC097_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVC097_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVC097_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVC097_TEXHEAD_BL_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVC097_TEXHEAD_BL_HEIGHT_MINUS_ONE MW(175:160) +#define NVC097_TEXHEAD_BL_DEPTH_MINUS_ONE MW(189:176) +#define NVC097_TEXHEAD_BL_RESERVED5A MW(190:190) +#define NVC097_TEXHEAD_BL_NORMALIZED_COORDS MW(191:191) +#define NVC097_TEXHEAD_BL_RESERVED6Y MW(192:192) +#define NVC097_TEXHEAD_BL_TRILIN_OPT MW(197:193) +#define NVC097_TEXHEAD_BL_MIP_LOD_BIAS MW(210:198) +#define NVC097_TEXHEAD_BL_ANISO_BIAS MW(214:211) +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY MW(221:219) +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC097_TEXHEAD_BL_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVC097_TEXHEAD_BL_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT MW(235:232) +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVC097_TEXHEAD_BL_MIN_LOD_CLAMP MW(247:236) +#define NVC097_TEXHEAD_BL_RESERVED7Y MW(255:248) + + +/* +** Texture Header State Blocklinear Color Key + */ + +#define NVC097_TEXHEAD_BLCK_COMPONENTS MW(6:0) +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVC097_TEXHEAD_BLCK_R_DATA_TYPE MW(9:7) +#define NVC097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BLCK_G_DATA_TYPE MW(12:10) +#define NVC097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BLCK_B_DATA_TYPE MW(15:13) +#define NVC097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BLCK_A_DATA_TYPE MW(18:16) +#define NVC097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BLCK_X_SOURCE MW(21:19) +#define NVC097_TEXHEAD_BLCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_BLCK_X_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_BLCK_X_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_BLCK_X_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_BLCK_X_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_BLCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_BLCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BLCK_Y_SOURCE MW(24:22) +#define NVC097_TEXHEAD_BLCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_BLCK_Y_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_BLCK_Y_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_BLCK_Y_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_BLCK_Y_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_BLCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_BLCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BLCK_Z_SOURCE MW(27:25) +#define NVC097_TEXHEAD_BLCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_BLCK_Z_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_BLCK_Z_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_BLCK_Z_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_BLCK_Z_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_BLCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_BLCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BLCK_W_SOURCE MW(30:28) +#define NVC097_TEXHEAD_BLCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_BLCK_W_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_BLCK_W_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_BLCK_W_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_BLCK_W_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_BLCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_BLCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BLCK_PACK_COMPONENTS MW(31:31) +#define NVC097_TEXHEAD_BLCK_RESERVED1Y MW(36:32) +#define NVC097_TEXHEAD_BLCK_GOB_DEPTH_OFFSET MW(38:37) +#define NVC097_TEXHEAD_BLCK_RESERVED1X MW(40:39) +#define NVC097_TEXHEAD_BLCK_ADDRESS_BITS31TO9 MW(63:41) +#define NVC097_TEXHEAD_BLCK_ADDRESS_BITS48TO32 MW(80:64) +#define NVC097_TEXHEAD_BLCK_RESERVED_ADDRESS MW(84:81) +#define NVC097_TEXHEAD_BLCK_HEADER_VERSION MW(87:85) +#define NVC097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVC097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVC097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVC097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVC097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVC097_TEXHEAD_BLCK_RESERVED_HEADER_VERSION MW(88:88) +#define NVC097_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVC097_TEXHEAD_BLCK_RESERVED2A MW(95:93) +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_WIDTH MW(98:96) +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT MW(101:99) +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH MW(104:102) +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC097_TEXHEAD_BLCK_RESERVED3Y MW(105:105) +#define NVC097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS MW(108:106) +#define NVC097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVC097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVC097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVC097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVC097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVC097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVC097_TEXHEAD_BLCK_GOB3D MW(109:109) +#define NVC097_TEXHEAD_BLCK_RESERVED3Z MW(111:110) +#define NVC097_TEXHEAD_BLCK_LOD_ANISO_QUALITY2 MW(112:112) +#define NVC097_TEXHEAD_BLCK_LOD_ANISO_QUALITY MW(113:113) +#define NVC097_TEXHEAD_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC097_TEXHEAD_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC097_TEXHEAD_BLCK_LOD_ISO_QUALITY MW(114:114) +#define NVC097_TEXHEAD_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC097_TEXHEAD_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC097_TEXHEAD_BLCK_ANISO_SPREAD_SCALE MW(121:117) +#define NVC097_TEXHEAD_BLCK_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVC097_TEXHEAD_BLCK_DEPTH_TEXTURE MW(123:123) +#define NVC097_TEXHEAD_BLCK_MAX_MIP_LEVEL MW(127:124) +#define NVC097_TEXHEAD_BLCK_WIDTH_MINUS_ONE MW(144:128) +#define NVC097_TEXHEAD_BLCK_DEPTH_MINUS_ONE_BIT14 MW(145:145) +#define NVC097_TEXHEAD_BLCK_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVC097_TEXHEAD_BLCK_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVC097_TEXHEAD_BLCK_S_R_G_B_CONVERSION MW(150:150) +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE MW(154:151) +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVC097_TEXHEAD_BLCK_SECTOR_PROMOTION MW(156:155) +#define NVC097_TEXHEAD_BLCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVC097_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVC097_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVC097_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVC097_TEXHEAD_BLCK_BORDER_SIZE MW(159:157) +#define NVC097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVC097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVC097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVC097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVC097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVC097_TEXHEAD_BLCK_HEIGHT_MINUS_ONE MW(175:160) +#define NVC097_TEXHEAD_BLCK_DEPTH_MINUS_ONE MW(189:176) +#define NVC097_TEXHEAD_BLCK_RESERVED5A MW(190:190) +#define NVC097_TEXHEAD_BLCK_NORMALIZED_COORDS MW(191:191) +#define NVC097_TEXHEAD_BLCK_COLOR_KEY_OP MW(192:192) +#define NVC097_TEXHEAD_BLCK_TRILIN_OPT MW(197:193) +#define NVC097_TEXHEAD_BLCK_MIP_LOD_BIAS MW(210:198) +#define NVC097_TEXHEAD_BLCK_ANISO_BIAS MW(214:211) +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY MW(221:219) +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC097_TEXHEAD_BLCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Header State One-D Buffer + */ + +#define NVC097_TEXHEAD_1D_COMPONENTS MW(6:0) +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R32 0x0000000f +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R16 0x0000001b +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R8 0x0000001d +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R1 0x0000001f +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_EAC 0x00000019 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_Z16 0x0000003a +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVC097_TEXHEAD_1D_R_DATA_TYPE MW(9:7) +#define NVC097_TEXHEAD_1D_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_1D_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_1D_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_1D_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_1D_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_1D_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_1D_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_1D_G_DATA_TYPE MW(12:10) +#define NVC097_TEXHEAD_1D_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_1D_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_1D_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_1D_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_1D_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_1D_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_1D_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_1D_B_DATA_TYPE MW(15:13) +#define NVC097_TEXHEAD_1D_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_1D_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_1D_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_1D_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_1D_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_1D_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_1D_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_1D_A_DATA_TYPE MW(18:16) +#define NVC097_TEXHEAD_1D_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_1D_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_1D_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_1D_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_1D_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_1D_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_1D_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_1D_X_SOURCE MW(21:19) +#define NVC097_TEXHEAD_1D_X_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_1D_X_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_1D_X_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_1D_X_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_1D_X_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_1D_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_1D_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_1D_Y_SOURCE MW(24:22) +#define NVC097_TEXHEAD_1D_Y_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_1D_Y_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_1D_Y_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_1D_Y_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_1D_Y_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_1D_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_1D_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_1D_Z_SOURCE MW(27:25) +#define NVC097_TEXHEAD_1D_Z_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_1D_Z_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_1D_Z_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_1D_Z_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_1D_Z_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_1D_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_1D_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_1D_W_SOURCE MW(30:28) +#define NVC097_TEXHEAD_1D_W_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_1D_W_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_1D_W_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_1D_W_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_1D_W_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_1D_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_1D_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_1D_PACK_COMPONENTS MW(31:31) +#define NVC097_TEXHEAD_1D_ADDRESS_BITS31TO0 MW(63:32) +#define NVC097_TEXHEAD_1D_ADDRESS_BITS48TO32 MW(80:64) +#define NVC097_TEXHEAD_1D_RESERVED_ADDRESS MW(84:81) +#define NVC097_TEXHEAD_1D_HEADER_VERSION MW(87:85) +#define NVC097_TEXHEAD_1D_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVC097_TEXHEAD_1D_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVC097_TEXHEAD_1D_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVC097_TEXHEAD_1D_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVC097_TEXHEAD_1D_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVC097_TEXHEAD_1D_RESERVED_HEADER_VERSION MW(88:88) +#define NVC097_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVC097_TEXHEAD_1D_RESERVED2A MW(95:93) +#define NVC097_TEXHEAD_1D_WIDTH_MINUS_ONE_BITS31TO16 MW(111:96) +#define NVC097_TEXHEAD_1D_RESERVED3X MW(127:112) +#define NVC097_TEXHEAD_1D_WIDTH_MINUS_ONE_BITS15TO0 MW(143:128) +#define NVC097_TEXHEAD_1D_RESERVED4X MW(149:144) +#define NVC097_TEXHEAD_1D_S_R_G_B_CONVERSION MW(150:150) +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE MW(154:151) +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVC097_TEXHEAD_1D_SECTOR_PROMOTION MW(156:155) +#define NVC097_TEXHEAD_1D_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVC097_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVC097_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVC097_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVC097_TEXHEAD_1D_RESERVED4Y MW(159:157) +#define NVC097_TEXHEAD_1D_RESERVED5X MW(189:160) +#define NVC097_TEXHEAD_1D_RESERVED5A MW(190:190) +#define NVC097_TEXHEAD_1D_RESERVED5Y MW(191:191) +#define NVC097_TEXHEAD_1D_RESERVED6X MW(223:192) +#define NVC097_TEXHEAD_1D_RESERVED7X MW(255:224) + + +/* +** Texture Header State Pitch + */ + +#define NVC097_TEXHEAD_PITCH_COMPONENTS MW(6:0) +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32 0x0000000f +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R16 0x0000001b +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R8 0x0000001d +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R1 0x0000001f +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_EAC 0x00000019 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_Z16 0x0000003a +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVC097_TEXHEAD_PITCH_R_DATA_TYPE MW(9:7) +#define NVC097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCH_G_DATA_TYPE MW(12:10) +#define NVC097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCH_B_DATA_TYPE MW(15:13) +#define NVC097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCH_A_DATA_TYPE MW(18:16) +#define NVC097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCH_X_SOURCE MW(21:19) +#define NVC097_TEXHEAD_PITCH_X_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_PITCH_X_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_PITCH_X_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_PITCH_X_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_PITCH_X_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_PITCH_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_PITCH_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCH_Y_SOURCE MW(24:22) +#define NVC097_TEXHEAD_PITCH_Y_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_PITCH_Y_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_PITCH_Y_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_PITCH_Y_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_PITCH_Y_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_PITCH_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_PITCH_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCH_Z_SOURCE MW(27:25) +#define NVC097_TEXHEAD_PITCH_Z_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_PITCH_Z_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_PITCH_Z_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_PITCH_Z_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_PITCH_Z_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_PITCH_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_PITCH_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCH_W_SOURCE MW(30:28) +#define NVC097_TEXHEAD_PITCH_W_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_PITCH_W_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_PITCH_W_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_PITCH_W_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_PITCH_W_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_PITCH_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_PITCH_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCH_PACK_COMPONENTS MW(31:31) +#define NVC097_TEXHEAD_PITCH_RESERVED1A MW(36:32) +#define NVC097_TEXHEAD_PITCH_ADDRESS_BITS31TO5 MW(63:37) +#define NVC097_TEXHEAD_PITCH_ADDRESS_BITS48TO32 MW(80:64) +#define NVC097_TEXHEAD_PITCH_RESERVED_ADDRESS MW(84:81) +#define NVC097_TEXHEAD_PITCH_HEADER_VERSION MW(87:85) +#define NVC097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVC097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVC097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVC097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVC097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVC097_TEXHEAD_PITCH_RESERVED_HEADER_VERSION MW(88:88) +#define NVC097_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVC097_TEXHEAD_PITCH_RESERVED2A MW(95:93) +#define NVC097_TEXHEAD_PITCH_PITCH_BITS20TO5 MW(111:96) +#define NVC097_TEXHEAD_PITCH_LOD_ANISO_QUALITY2 MW(112:112) +#define NVC097_TEXHEAD_PITCH_LOD_ANISO_QUALITY MW(113:113) +#define NVC097_TEXHEAD_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC097_TEXHEAD_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC097_TEXHEAD_PITCH_LOD_ISO_QUALITY MW(114:114) +#define NVC097_TEXHEAD_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC097_TEXHEAD_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC097_TEXHEAD_PITCH_ANISO_SPREAD_SCALE MW(121:117) +#define NVC097_TEXHEAD_PITCH_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVC097_TEXHEAD_PITCH_DEPTH_TEXTURE MW(123:123) +#define NVC097_TEXHEAD_PITCH_MAX_MIP_LEVEL MW(127:124) +#define NVC097_TEXHEAD_PITCH_WIDTH_MINUS_ONE MW(144:128) +#define NVC097_TEXHEAD_PITCH_PITCH_BIT21 MW(145:145) +#define NVC097_TEXHEAD_PITCH_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVC097_TEXHEAD_PITCH_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVC097_TEXHEAD_PITCH_S_R_G_B_CONVERSION MW(150:150) +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE MW(154:151) +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVC097_TEXHEAD_PITCH_SECTOR_PROMOTION MW(156:155) +#define NVC097_TEXHEAD_PITCH_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVC097_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVC097_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVC097_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVC097_TEXHEAD_PITCH_BORDER_SIZE MW(159:157) +#define NVC097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVC097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVC097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVC097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVC097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVC097_TEXHEAD_PITCH_HEIGHT_MINUS_ONE MW(175:160) +#define NVC097_TEXHEAD_PITCH_DEPTH_MINUS_ONE MW(189:176) +#define NVC097_TEXHEAD_PITCH_RESERVED5A MW(190:190) +#define NVC097_TEXHEAD_PITCH_NORMALIZED_COORDS MW(191:191) +#define NVC097_TEXHEAD_PITCH_RESERVED6Y MW(192:192) +#define NVC097_TEXHEAD_PITCH_TRILIN_OPT MW(197:193) +#define NVC097_TEXHEAD_PITCH_MIP_LOD_BIAS MW(210:198) +#define NVC097_TEXHEAD_PITCH_ANISO_BIAS MW(214:211) +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY MW(221:219) +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC097_TEXHEAD_PITCH_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVC097_TEXHEAD_PITCH_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT MW(235:232) +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVC097_TEXHEAD_PITCH_MIN_LOD_CLAMP MW(247:236) +#define NVC097_TEXHEAD_PITCH_RESERVED7Y MW(255:248) + + +/* +** Texture Header State Pitch Color Key + */ + +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS MW(6:0) +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVC097_TEXHEAD_PITCHCK_R_DATA_TYPE MW(9:7) +#define NVC097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_G_DATA_TYPE MW(12:10) +#define NVC097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_B_DATA_TYPE MW(15:13) +#define NVC097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_A_DATA_TYPE MW(18:16) +#define NVC097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_X_SOURCE MW(21:19) +#define NVC097_TEXHEAD_PITCHCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_X_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_X_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_X_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_X_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_Y_SOURCE MW(24:22) +#define NVC097_TEXHEAD_PITCHCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_Y_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_Y_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_Y_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_Y_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_Z_SOURCE MW(27:25) +#define NVC097_TEXHEAD_PITCHCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_Z_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_Z_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_Z_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_Z_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_W_SOURCE MW(30:28) +#define NVC097_TEXHEAD_PITCHCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_W_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_W_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_W_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_W_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_PACK_COMPONENTS MW(31:31) +#define NVC097_TEXHEAD_PITCHCK_RESERVED1A MW(36:32) +#define NVC097_TEXHEAD_PITCHCK_ADDRESS_BITS31TO5 MW(63:37) +#define NVC097_TEXHEAD_PITCHCK_ADDRESS_BITS48TO32 MW(80:64) +#define NVC097_TEXHEAD_PITCHCK_RESERVED_ADDRESS MW(84:81) +#define NVC097_TEXHEAD_PITCHCK_HEADER_VERSION MW(87:85) +#define NVC097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_RESERVED_HEADER_VERSION MW(88:88) +#define NVC097_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVC097_TEXHEAD_PITCHCK_RESERVED2A MW(95:93) +#define NVC097_TEXHEAD_PITCHCK_PITCH_BITS20TO5 MW(111:96) +#define NVC097_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY2 MW(112:112) +#define NVC097_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY MW(113:113) +#define NVC097_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_LOD_ISO_QUALITY MW(114:114) +#define NVC097_TEXHEAD_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_ANISO_SPREAD_SCALE MW(121:117) +#define NVC097_TEXHEAD_PITCHCK_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVC097_TEXHEAD_PITCHCK_DEPTH_TEXTURE MW(123:123) +#define NVC097_TEXHEAD_PITCHCK_MAX_MIP_LEVEL MW(127:124) +#define NVC097_TEXHEAD_PITCHCK_WIDTH_MINUS_ONE MW(144:128) +#define NVC097_TEXHEAD_PITCHCK_PITCH_BIT21 MW(145:145) +#define NVC097_TEXHEAD_PITCHCK_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVC097_TEXHEAD_PITCHCK_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVC097_TEXHEAD_PITCHCK_S_R_G_B_CONVERSION MW(150:150) +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE MW(154:151) +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVC097_TEXHEAD_PITCHCK_SECTOR_PROMOTION MW(156:155) +#define NVC097_TEXHEAD_PITCHCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_BORDER_SIZE MW(159:157) +#define NVC097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_HEIGHT_MINUS_ONE MW(175:160) +#define NVC097_TEXHEAD_PITCHCK_DEPTH_MINUS_ONE MW(189:176) +#define NVC097_TEXHEAD_PITCHCK_RESERVED5A MW(190:190) +#define NVC097_TEXHEAD_PITCHCK_NORMALIZED_COORDS MW(191:191) +#define NVC097_TEXHEAD_PITCHCK_COLOR_KEY_OP MW(192:192) +#define NVC097_TEXHEAD_PITCHCK_TRILIN_OPT MW(197:193) +#define NVC097_TEXHEAD_PITCHCK_MIP_LOD_BIAS MW(210:198) +#define NVC097_TEXHEAD_PITCHCK_ANISO_BIAS MW(214:211) +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY MW(221:219) +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Sampler State + */ + +#define NVC097_TEXSAMP0_ADDRESS_U 2:0 +#define NVC097_TEXSAMP0_ADDRESS_U_WRAP 0x00000000 +#define NVC097_TEXSAMP0_ADDRESS_U_MIRROR 0x00000001 +#define NVC097_TEXSAMP0_ADDRESS_U_CLAMP_TO_EDGE 0x00000002 +#define NVC097_TEXSAMP0_ADDRESS_U_BORDER 0x00000003 +#define NVC097_TEXSAMP0_ADDRESS_U_CLAMP_OGL 0x00000004 +#define NVC097_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVC097_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_BORDER 0x00000006 +#define NVC097_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVC097_TEXSAMP0_ADDRESS_V 5:3 +#define NVC097_TEXSAMP0_ADDRESS_V_WRAP 0x00000000 +#define NVC097_TEXSAMP0_ADDRESS_V_MIRROR 0x00000001 +#define NVC097_TEXSAMP0_ADDRESS_V_CLAMP_TO_EDGE 0x00000002 +#define NVC097_TEXSAMP0_ADDRESS_V_BORDER 0x00000003 +#define NVC097_TEXSAMP0_ADDRESS_V_CLAMP_OGL 0x00000004 +#define NVC097_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVC097_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_BORDER 0x00000006 +#define NVC097_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVC097_TEXSAMP0_ADDRESS_P 8:6 +#define NVC097_TEXSAMP0_ADDRESS_P_WRAP 0x00000000 +#define NVC097_TEXSAMP0_ADDRESS_P_MIRROR 0x00000001 +#define NVC097_TEXSAMP0_ADDRESS_P_CLAMP_TO_EDGE 0x00000002 +#define NVC097_TEXSAMP0_ADDRESS_P_BORDER 0x00000003 +#define NVC097_TEXSAMP0_ADDRESS_P_CLAMP_OGL 0x00000004 +#define NVC097_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVC097_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_BORDER 0x00000006 +#define NVC097_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVC097_TEXSAMP0_DEPTH_COMPARE 9:9 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC 12:10 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_NEVER 0x00000000 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_LESS 0x00000001 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_EQUAL 0x00000002 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_LEQUAL 0x00000003 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_GREATER 0x00000004 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_NOTEQUAL 0x00000005 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_GEQUAL 0x00000006 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_ALWAYS 0x00000007 +#define NVC097_TEXSAMP0_S_R_G_B_CONVERSION 13:13 +#define NVC097_TEXSAMP0_RESERVED0A 16:14 +#define NVC097_TEXSAMP0_RESERVED0B 19:17 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY 22:20 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVC097_TEXSAMP1_MAG_FILTER 2:0 +#define NVC097_TEXSAMP1_MAG_FILTER_MAG_POINT 0x00000001 +#define NVC097_TEXSAMP1_MAG_FILTER_MAG_LINEAR 0x00000002 +#define NVC097_TEXSAMP1_MAG_FILTER_VCAA_4_TAP 0x00000003 +#define NVC097_TEXSAMP1_MAG_FILTER_VCAA_8_TAP 0x00000004 +#define NVC097_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP 3:3 +#define NVC097_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP_INTEGER_AND_FRACTION 0x00000000 +#define NVC097_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP_INTEGER_ONLY 0x00000001 +#define NVC097_TEXSAMP1_MIN_FILTER 5:4 +#define NVC097_TEXSAMP1_MIN_FILTER_MIN_POINT 0x00000001 +#define NVC097_TEXSAMP1_MIN_FILTER_MIN_LINEAR 0x00000002 +#define NVC097_TEXSAMP1_MIN_FILTER_MIN_ANISO 0x00000003 +#define NVC097_TEXSAMP1_MIP_FILTER 7:6 +#define NVC097_TEXSAMP1_MIP_FILTER_MIP_NONE 0x00000001 +#define NVC097_TEXSAMP1_MIP_FILTER_MIP_POINT 0x00000002 +#define NVC097_TEXSAMP1_MIP_FILTER_MIP_LINEAR 0x00000003 +#define NVC097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING 9:8 +#define NVC097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_USE_WRAP 0x00000000 +#define NVC097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_OVERRIDE_WRAP 0x00000001 +#define NVC097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_AUTO_SPAN_SEAM 0x00000002 +#define NVC097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_AUTO_CROSS_SEAM 0x00000003 +#define NVC097_TEXSAMP1_REDUCTION_FILTER 11:10 +#define NVC097_TEXSAMP1_REDUCTION_FILTER_RED_NONE 0x00000000 +#define NVC097_TEXSAMP1_REDUCTION_FILTER_RED_MINIMUM 0x00000001 +#define NVC097_TEXSAMP1_REDUCTION_FILTER_RED_MAXIMUM 0x00000002 +#define NVC097_TEXSAMP1_MIP_LOD_BIAS 24:12 +#define NVC097_TEXSAMP1_FLOAT_COORD_NORMALIZATION 25:25 +#define NVC097_TEXSAMP1_FLOAT_COORD_NORMALIZATION_USE_HEADER_SETTING 0x00000000 +#define NVC097_TEXSAMP1_FLOAT_COORD_NORMALIZATION_FORCE_UNNORMALIZED_COORDS 0x00000001 +#define NVC097_TEXSAMP1_TRILIN_OPT 30:26 +#define NVC097_TEXSAMP2_MIN_LOD_CLAMP 11:0 +#define NVC097_TEXSAMP2_MAX_LOD_CLAMP 23:12 +#define NVC097_TEXSAMP2_S_R_G_B_BORDER_COLOR_R 31:24 +#define NVC097_TEXSAMP3_RESERVED12 11:0 +#define NVC097_TEXSAMP3_S_R_G_B_BORDER_COLOR_G 19:12 +#define NVC097_TEXSAMP3_S_R_G_B_BORDER_COLOR_B 27:20 +#define NVC097_TEXSAMP4_BORDER_COLOR_R 31:0 +#define NVC097_TEXSAMP5_BORDER_COLOR_G 31:0 +#define NVC097_TEXSAMP6_BORDER_COLOR_B 31:0 +#define NVC097_TEXSAMP7_BORDER_COLOR_A 31:0 + + + +#endif // #ifndef __CLC097TEX_H__ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc0b5.h b/userspace/sdks/nv570/nvidia/inc/class/clc0b5.h new file mode 100644 index 0000000..d1fa85a --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc0b5.h @@ -0,0 +1,261 @@ +/******************************************************************************* + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clc0b5_h_ +#define _clc0b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define PASCAL_DMA_COPY_A (0x0000C0B5) + +#define NVC0B5_NOP (0x00000100) +#define NVC0B5_NOP_PARAMETER 31:0 +#define NVC0B5_PM_TRIGGER (0x00000140) +#define NVC0B5_PM_TRIGGER_V 31:0 +#define NVC0B5_SET_SEMAPHORE_A (0x00000240) +#define NVC0B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC0B5_SET_SEMAPHORE_B (0x00000244) +#define NVC0B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC0B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC0B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC0B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC0B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC0B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC0B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC0B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC0B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC0B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC0B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC0B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC0B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC0B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC0B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC0B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC0B5_LAUNCH_DMA (0x00000300) +#define NVC0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC0B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC0B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC0B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC0B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC0B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC0B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC0B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC0B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC0B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC0B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC0B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC0B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC0B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC0B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC0B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC0B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC0B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC0B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC0B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC0B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC0B5_LAUNCH_DMA_SRC_BYPASS_L2 20:20 +#define NVC0B5_LAUNCH_DMA_SRC_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC0B5_LAUNCH_DMA_SRC_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC0B5_LAUNCH_DMA_DST_BYPASS_L2 21:21 +#define NVC0B5_LAUNCH_DMA_DST_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC0B5_LAUNCH_DMA_DST_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC0B5_LAUNCH_DMA_RESERVED 31:28 +#define NVC0B5_OFFSET_IN_UPPER (0x00000400) +#define NVC0B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC0B5_OFFSET_IN_LOWER (0x00000404) +#define NVC0B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC0B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC0B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC0B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC0B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC0B5_PITCH_IN (0x00000410) +#define NVC0B5_PITCH_IN_VALUE 31:0 +#define NVC0B5_PITCH_OUT (0x00000414) +#define NVC0B5_PITCH_OUT_VALUE 31:0 +#define NVC0B5_LINE_LENGTH_IN (0x00000418) +#define NVC0B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC0B5_LINE_COUNT (0x0000041C) +#define NVC0B5_LINE_COUNT_VALUE 31:0 +#define NVC0B5_SET_REMAP_CONST_A (0x00000700) +#define NVC0B5_SET_REMAP_CONST_A_V 31:0 +#define NVC0B5_SET_REMAP_CONST_B (0x00000704) +#define NVC0B5_SET_REMAP_CONST_B_V 31:0 +#define NVC0B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC0B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC0B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC0B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC0B5_SET_DST_WIDTH (0x00000710) +#define NVC0B5_SET_DST_WIDTH_V 31:0 +#define NVC0B5_SET_DST_HEIGHT (0x00000714) +#define NVC0B5_SET_DST_HEIGHT_V 31:0 +#define NVC0B5_SET_DST_DEPTH (0x00000718) +#define NVC0B5_SET_DST_DEPTH_V 31:0 +#define NVC0B5_SET_DST_LAYER (0x0000071C) +#define NVC0B5_SET_DST_LAYER_V 31:0 +#define NVC0B5_SET_DST_ORIGIN (0x00000720) +#define NVC0B5_SET_DST_ORIGIN_X 15:0 +#define NVC0B5_SET_DST_ORIGIN_Y 31:16 +#define NVC0B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC0B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC0B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC0B5_SET_SRC_WIDTH (0x0000072C) +#define NVC0B5_SET_SRC_WIDTH_V 31:0 +#define NVC0B5_SET_SRC_HEIGHT (0x00000730) +#define NVC0B5_SET_SRC_HEIGHT_V 31:0 +#define NVC0B5_SET_SRC_DEPTH (0x00000734) +#define NVC0B5_SET_SRC_DEPTH_V 31:0 +#define NVC0B5_SET_SRC_LAYER (0x00000738) +#define NVC0B5_SET_SRC_LAYER_V 31:0 +#define NVC0B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC0B5_SET_SRC_ORIGIN_X 15:0 +#define NVC0B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC0B5_PM_TRIGGER_END (0x00001114) +#define NVC0B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc0b5_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc0b5sw.h b/userspace/sdks/nv570/nvidia/inc/class/clc0b5sw.h new file mode 100644 index 0000000..dc5bc41 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc0b5sw.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc0b5sw.finn +// + + + +// +// Using VERSION_0 will cause the API to interpret +// engineType as a CE engine instance. This allows +// for backward compatibility with 85B5sw and 90B5sw. +// +#define NVC0B5_ALLOCATION_PARAMETERS_VERSION_0 0 + +// +// Using VERSION_1 will cause the API to interpret +// engineType as an NV2080_ENGINE_TYPE ordinal. +// +#define NVC0B5_ALLOCATION_PARAMETERS_VERSION_1 1 + +#define NVC0B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc0b5U) + +typedef struct NVC0B5_ALLOCATION_PARAMETERS { + NvU32 version; + NvU32 engineType; +} NVC0B5_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc0b7.h b/userspace/sdks/nv570/nvidia/inc/class/clc0b7.h new file mode 100644 index 0000000..bdb9bba --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc0b7.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clc0b7_h +#define clc0b7_h + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC0B7_VIDEO_ENCODER (0x0000C0B7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc0b7_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc0c0.h b/userspace/sdks/nv570/nvidia/inc/class/clc0c0.h new file mode 100644 index 0000000..fde8702 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc0c0.h @@ -0,0 +1,777 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_pascal_compute_a_h_ +#define _cl_pascal_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl pascal_compute_a */ + +#include "nvtypes.h" + +#define PASCAL_COMPUTE_A 0xC0C0 + +#define NVC0C0_SET_OBJECT 0x0000 +#define NVC0C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC0C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC0C0_NO_OPERATION 0x0100 +#define NVC0C0_NO_OPERATION_V 31:0 + +#define NVC0C0_SET_NOTIFY_A 0x0104 +#define NVC0C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC0C0_SET_NOTIFY_B 0x0108 +#define NVC0C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_NOTIFY 0x010c +#define NVC0C0_NOTIFY_TYPE 31:0 +#define NVC0C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC0C0_WAIT_FOR_IDLE 0x0110 +#define NVC0C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC0C0_SEND_GO_IDLE 0x013c +#define NVC0C0_SEND_GO_IDLE_V 31:0 + +#define NVC0C0_PM_TRIGGER 0x0140 +#define NVC0C0_PM_TRIGGER_V 31:0 + +#define NVC0C0_PM_TRIGGER_WFI 0x0144 +#define NVC0C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC0C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC0C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC0C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC0C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC0C0_LINE_LENGTH_IN 0x0180 +#define NVC0C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC0C0_LINE_COUNT 0x0184 +#define NVC0C0_LINE_COUNT_VALUE 31:0 + +#define NVC0C0_OFFSET_OUT_UPPER 0x0188 +#define NVC0C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC0C0_OFFSET_OUT 0x018c +#define NVC0C0_OFFSET_OUT_VALUE 31:0 + +#define NVC0C0_PITCH_OUT 0x0190 +#define NVC0C0_PITCH_OUT_VALUE 31:0 + +#define NVC0C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC0C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC0C0_SET_DST_WIDTH 0x0198 +#define NVC0C0_SET_DST_WIDTH_V 31:0 + +#define NVC0C0_SET_DST_HEIGHT 0x019c +#define NVC0C0_SET_DST_HEIGHT_V 31:0 + +#define NVC0C0_SET_DST_DEPTH 0x01a0 +#define NVC0C0_SET_DST_DEPTH_V 31:0 + +#define NVC0C0_SET_DST_LAYER 0x01a4 +#define NVC0C0_SET_DST_LAYER_V 31:0 + +#define NVC0C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC0C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC0C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC0C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC0C0_LAUNCH_DMA 0x01b0 +#define NVC0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC0C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC0C0_LOAD_INLINE_DATA 0x01b4 +#define NVC0C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC0C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC0C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC0C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC0C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC0C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC0C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC0C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC0C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC0C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC0C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC0C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC0C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVC0C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVC0C0_PERFMON_TRANSFER 0x0210 +#define NVC0C0_PERFMON_TRANSFER_V 31:0 + +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0218 +#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVC0C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC0C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC0C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC0C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC0C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC0C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC0C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC0C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC0C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC0C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC0C0_SET_CWD_CONTROL 0x0240 +#define NVC0C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVC0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVC0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC0C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC0C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC0C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC0C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC0C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC0C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC0C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC0C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC0C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC0C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC0C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC0C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC0C0_SET_GWC_SCG_TYPE 0x026c +#define NVC0C0_SET_GWC_SCG_TYPE_SCG_TYPE 0:0 +#define NVC0C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0 0x00000000 +#define NVC0C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1 0x00000001 + +#define NVC0C0_SET_SCG_CONTROL 0x0270 +#define NVC0C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 + +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 16:0 + +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVC0C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC0C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC0C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC0C0_SET_QMD_VERSION 0x0288 +#define NVC0C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC0C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC0C0_SET_WFI_CONFIG 0x028c +#define NVC0C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI 0:0 +#define NVC0C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE 0x00000000 +#define NVC0C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE 0x00000001 + +#define NVC0C0_CHECK_QMD_VERSION 0x0290 +#define NVC0C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC0C0_WAIT_FOR_IDLE_SCG_TYPE 0x0294 +#define NVC0C0_WAIT_FOR_IDLE_SCG_TYPE_V 31:0 + +#define NVC0C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC0C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL 0x029c +#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE 0:0 +#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE 0x00000001 + +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC0C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC0C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC0C0_SEND_PCAS_A 0x02b4 +#define NVC0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC0C0_SEND_PCAS_B 0x02b8 +#define NVC0C0_SEND_PCAS_B_FROM 23:0 +#define NVC0C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC0C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC0C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC0C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC0C0_SET_SPA_VERSION 0x0310 +#define NVC0C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC0C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC0C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC0C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC0C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC0C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC0C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC0C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC0C0_SET_FALCON00 0x0500 +#define NVC0C0_SET_FALCON00_V 31:0 + +#define NVC0C0_SET_FALCON01 0x0504 +#define NVC0C0_SET_FALCON01_V 31:0 + +#define NVC0C0_SET_FALCON02 0x0508 +#define NVC0C0_SET_FALCON02_V 31:0 + +#define NVC0C0_SET_FALCON03 0x050c +#define NVC0C0_SET_FALCON03_V 31:0 + +#define NVC0C0_SET_FALCON04 0x0510 +#define NVC0C0_SET_FALCON04_V 31:0 + +#define NVC0C0_SET_FALCON05 0x0514 +#define NVC0C0_SET_FALCON05_V 31:0 + +#define NVC0C0_SET_FALCON06 0x0518 +#define NVC0C0_SET_FALCON06_V 31:0 + +#define NVC0C0_SET_FALCON07 0x051c +#define NVC0C0_SET_FALCON07_V 31:0 + +#define NVC0C0_SET_FALCON08 0x0520 +#define NVC0C0_SET_FALCON08_V 31:0 + +#define NVC0C0_SET_FALCON09 0x0524 +#define NVC0C0_SET_FALCON09_V 31:0 + +#define NVC0C0_SET_FALCON10 0x0528 +#define NVC0C0_SET_FALCON10_V 31:0 + +#define NVC0C0_SET_FALCON11 0x052c +#define NVC0C0_SET_FALCON11_V 31:0 + +#define NVC0C0_SET_FALCON12 0x0530 +#define NVC0C0_SET_FALCON12_V 31:0 + +#define NVC0C0_SET_FALCON13 0x0534 +#define NVC0C0_SET_FALCON13_V 31:0 + +#define NVC0C0_SET_FALCON14 0x0538 +#define NVC0C0_SET_FALCON14_V 31:0 + +#define NVC0C0_SET_FALCON15 0x053c +#define NVC0C0_SET_FALCON15_V 31:0 + +#define NVC0C0_SET_FALCON16 0x0540 +#define NVC0C0_SET_FALCON16_V 31:0 + +#define NVC0C0_SET_FALCON17 0x0544 +#define NVC0C0_SET_FALCON17_V 31:0 + +#define NVC0C0_SET_FALCON18 0x0548 +#define NVC0C0_SET_FALCON18_V 31:0 + +#define NVC0C0_SET_FALCON19 0x054c +#define NVC0C0_SET_FALCON19_V 31:0 + +#define NVC0C0_SET_FALCON20 0x0550 +#define NVC0C0_SET_FALCON20_V 31:0 + +#define NVC0C0_SET_FALCON21 0x0554 +#define NVC0C0_SET_FALCON21_V 31:0 + +#define NVC0C0_SET_FALCON22 0x0558 +#define NVC0C0_SET_FALCON22_V 31:0 + +#define NVC0C0_SET_FALCON23 0x055c +#define NVC0C0_SET_FALCON23_V 31:0 + +#define NVC0C0_SET_FALCON24 0x0560 +#define NVC0C0_SET_FALCON24_V 31:0 + +#define NVC0C0_SET_FALCON25 0x0564 +#define NVC0C0_SET_FALCON25_V 31:0 + +#define NVC0C0_SET_FALCON26 0x0568 +#define NVC0C0_SET_FALCON26_V 31:0 + +#define NVC0C0_SET_FALCON27 0x056c +#define NVC0C0_SET_FALCON27_V 31:0 + +#define NVC0C0_SET_FALCON28 0x0570 +#define NVC0C0_SET_FALCON28_V 31:0 + +#define NVC0C0_SET_FALCON29 0x0574 +#define NVC0C0_SET_FALCON29_V 31:0 + +#define NVC0C0_SET_FALCON30 0x0578 +#define NVC0C0_SET_FALCON30_V 31:0 + +#define NVC0C0_SET_FALCON31 0x057c +#define NVC0C0_SET_FALCON31_V 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC0C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC0C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC0C0_SET_SPARE_NOOP12 0x0f44 +#define NVC0C0_SET_SPARE_NOOP12_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP13 0x0f48 +#define NVC0C0_SET_SPARE_NOOP13_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP14 0x0f4c +#define NVC0C0_SET_SPARE_NOOP14_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP15 0x0f50 +#define NVC0C0_SET_SPARE_NOOP15_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP00 0x1040 +#define NVC0C0_SET_SPARE_NOOP00_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP01 0x1044 +#define NVC0C0_SET_SPARE_NOOP01_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP02 0x1048 +#define NVC0C0_SET_SPARE_NOOP02_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP03 0x104c +#define NVC0C0_SET_SPARE_NOOP03_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP04 0x1050 +#define NVC0C0_SET_SPARE_NOOP04_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP05 0x1054 +#define NVC0C0_SET_SPARE_NOOP05_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP06 0x1058 +#define NVC0C0_SET_SPARE_NOOP06_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP07 0x105c +#define NVC0C0_SET_SPARE_NOOP07_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP08 0x1060 +#define NVC0C0_SET_SPARE_NOOP08_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP09 0x1064 +#define NVC0C0_SET_SPARE_NOOP09_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP10 0x1068 +#define NVC0C0_SET_SPARE_NOOP10_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP11 0x106c +#define NVC0C0_SET_SPARE_NOOP11_V 31:0 + +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC0C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC0C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC0C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC0C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC0C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC0C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC0C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC0C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC0C0_SET_PROGRAM_REGION_A 0x1608 +#define NVC0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 16:0 + +#define NVC0C0_SET_PROGRAM_REGION_B 0x160c +#define NVC0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC0C0_PIPE_NOP 0x1a2c +#define NVC0C0_PIPE_NOP_V 31:0 + +#define NVC0C0_SET_SPARE00 0x1a30 +#define NVC0C0_SET_SPARE00_V 31:0 + +#define NVC0C0_SET_SPARE01 0x1a34 +#define NVC0C0_SET_SPARE01_V 31:0 + +#define NVC0C0_SET_SPARE02 0x1a38 +#define NVC0C0_SET_SPARE02_V 31:0 + +#define NVC0C0_SET_SPARE03 0x1a3c +#define NVC0C0_SET_SPARE03_V 31:0 + +#define NVC0C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC0C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC0C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC0C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC0C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC0C0_SET_TRAP_HANDLER 0x260c +#define NVC0C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC0C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC0C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC0C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC0C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC0C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC0C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_pascal_compute_a_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc197.h b/userspace/sdks/nv570/nvidia/inc/class/clc197.h new file mode 100644 index 0000000..b03d735 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc197.h @@ -0,0 +1,4242 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_pascal_b_h_ +#define _cl_pascal_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl pascal_b */ + +#include "nvtypes.h" + +#define PASCAL_B 0xC197 + +#define NVC197_SET_OBJECT 0x0000 +#define NVC197_SET_OBJECT_CLASS_ID 15:0 +#define NVC197_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC197_NO_OPERATION 0x0100 +#define NVC197_NO_OPERATION_V 31:0 + +#define NVC197_SET_NOTIFY_A 0x0104 +#define NVC197_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC197_SET_NOTIFY_B 0x0108 +#define NVC197_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC197_NOTIFY 0x010c +#define NVC197_NOTIFY_TYPE 31:0 +#define NVC197_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC197_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC197_WAIT_FOR_IDLE 0x0110 +#define NVC197_WAIT_FOR_IDLE_V 31:0 + +#define NVC197_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC197_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC197_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC197_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC197_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC197_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC197_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC197_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC197_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC197_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC197_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC197_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC197_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC197_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC197_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC197_SEND_GO_IDLE 0x013c +#define NVC197_SEND_GO_IDLE_V 31:0 + +#define NVC197_PM_TRIGGER 0x0140 +#define NVC197_PM_TRIGGER_V 31:0 + +#define NVC197_PM_TRIGGER_WFI 0x0144 +#define NVC197_PM_TRIGGER_WFI_V 31:0 + +#define NVC197_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC197_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC197_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC197_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC197_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC197_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC197_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC197_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC197_LINE_LENGTH_IN 0x0180 +#define NVC197_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC197_LINE_COUNT 0x0184 +#define NVC197_LINE_COUNT_VALUE 31:0 + +#define NVC197_OFFSET_OUT_UPPER 0x0188 +#define NVC197_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC197_OFFSET_OUT 0x018c +#define NVC197_OFFSET_OUT_VALUE 31:0 + +#define NVC197_PITCH_OUT 0x0190 +#define NVC197_PITCH_OUT_VALUE 31:0 + +#define NVC197_SET_DST_BLOCK_SIZE 0x0194 +#define NVC197_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC197_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC197_SET_DST_WIDTH 0x0198 +#define NVC197_SET_DST_WIDTH_V 31:0 + +#define NVC197_SET_DST_HEIGHT 0x019c +#define NVC197_SET_DST_HEIGHT_V 31:0 + +#define NVC197_SET_DST_DEPTH 0x01a0 +#define NVC197_SET_DST_DEPTH_V 31:0 + +#define NVC197_SET_DST_LAYER 0x01a4 +#define NVC197_SET_DST_LAYER_V 31:0 + +#define NVC197_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC197_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC197_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC197_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC197_LAUNCH_DMA 0x01b0 +#define NVC197_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC197_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC197_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC197_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC197_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC197_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC197_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC197_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC197_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC197_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC197_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC197_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC197_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC197_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC197_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC197_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC197_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC197_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC197_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC197_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC197_LOAD_INLINE_DATA 0x01b4 +#define NVC197_LOAD_INLINE_DATA_V 31:0 + +#define NVC197_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC197_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC197_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC197_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC197_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC197_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC197_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC197_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC197_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC197_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC197_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC197_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC197_RUN_DS_NOW 0x0200 +#define NVC197_RUN_DS_NOW_V 31:0 + +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC197_SET_GS_MODE 0x0208 +#define NVC197_SET_GS_MODE_TYPE 0:0 +#define NVC197_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVC197_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVC197_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC197_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC197_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC197_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC197_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC197_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_GS_DM_FIFO 0x0214 +#define NVC197_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC197_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC197_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC197_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC197_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC197_INVALIDATE_SHADER_CACHES 0x021c +#define NVC197_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC197_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC197_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC197_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC197_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC197_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC197_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC197_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC197_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC197_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC197_SET_INSTANCE_COUNT 0x0220 +#define NVC197_SET_INSTANCE_COUNT_V 31:0 + +#define NVC197_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVC197_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVC197_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC197_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVC197_INCREMENT_SYNC_POINT 0x02c8 +#define NVC197_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC197_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC197_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC197_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC197_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC197_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC197_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC197_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NVC197_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NVC197_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC197_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC197_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC197_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVC197_DECOMPRESS_SURFACE 0x02e0 +#define NVC197_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC197_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC197_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC197_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC197_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC197_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC197_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC197_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC197_SET_ZCULL_SUBREGION 0x02e8 +#define NVC197_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC197_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC197_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC197_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC197_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC197_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC197_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC197_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC197_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC197_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC197_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC197_DRAW_ZERO_INDEX 0x0304 +#define NVC197_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC197_SET_L1_CONFIGURATION 0x0308 +#define NVC197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC197_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC197_SET_SPA_VERSION 0x0310 +#define NVC197_SET_SPA_VERSION_MINOR 7:0 +#define NVC197_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC197_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NVC197_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NVC197_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_SNAP_GRID_LINE 0x0318 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC197_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC197_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC197_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC197_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC197_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC197_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC197_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC197_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC197_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC197_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC197_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC197_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC197_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC197_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC197_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC197_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC197_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC197_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC197_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC197_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC197_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC197_RESERVED_TG07 0x033c +#define NVC197_RESERVED_TG07_V 0:0 + +#define NVC197_RESERVED_TG08 0x0340 +#define NVC197_RESERVED_TG08_V 0:0 + +#define NVC197_RESERVED_TG09 0x0344 +#define NVC197_RESERVED_TG09_V 0:0 + +#define NVC197_RESERVED_TG10 0x0348 +#define NVC197_RESERVED_TG10_V 0:0 + +#define NVC197_RESERVED_TG11 0x034c +#define NVC197_RESERVED_TG11_V 0:0 + +#define NVC197_RESERVED_TG12 0x0350 +#define NVC197_RESERVED_TG12_V 0:0 + +#define NVC197_RESERVED_TG13 0x0354 +#define NVC197_RESERVED_TG13_V 0:0 + +#define NVC197_RESERVED_TG14 0x0358 +#define NVC197_RESERVED_TG14_V 0:0 + +#define NVC197_RESERVED_TG15 0x035c +#define NVC197_RESERVED_TG15_V 0:0 + +#define NVC197_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC197_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC197_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC197_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC197_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC197_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC197_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC197_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC197_SET_RASTER_ENABLE 0x037c +#define NVC197_SET_RASTER_ENABLE_V 0:0 +#define NVC197_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC197_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC197_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC197_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC197_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC197_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC197_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC197_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC197_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC197_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC197_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVC197_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVC197_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVC197_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVC197_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVC197_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVC197_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVC197_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVC197_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC197_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC197_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC197_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC197_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC197_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC197_SET_RASTER_INPUT 0x0740 +#define NVC197_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC197_SET_STREAM_OUTPUT 0x0744 +#define NVC197_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC197_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_ALPHA_FRACTION 0x074c +#define NVC197_SET_ALPHA_FRACTION_V 7:0 + +#define NVC197_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC197_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC197_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC197_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC197_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC197_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC197_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC197_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC197_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC197_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC197_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC197_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC197_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC197_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC197_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC197_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC197_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC197_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC197_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC197_SET_ISBE_SAVE_RESTORE_PROGRAM 0x07ac +#define NVC197_SET_ISBE_SAVE_RESTORE_PROGRAM_OFFSET 31:0 + +#define NVC197_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVC197_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC197_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC197_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC197_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC197_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC197_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC197_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC197_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC197_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC197_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC197_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC197_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC197_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC197_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC197_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC197_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC197_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC197_SET_ZCULL_STORAGE_B 0x07ec +#define NVC197_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC197_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC197_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC197_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC197_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC197_SET_ZT_READ_ONLY 0x07f8 +#define NVC197_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC197_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC197_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC197_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC197_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC197_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC197_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC197_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC197_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC197_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC197_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC197_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC197_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC197_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC197_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC197_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC197_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC197_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC197_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC197_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC197_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC197_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC197_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC197_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC197_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC197_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC197_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC197_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC197_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC197_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC197_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC197_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC197_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NVC197_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NVC197_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVC197_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVC197_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC197_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC197_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC197_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC197_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC197_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC197_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC197_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC197_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC197_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC197_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC197_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC197_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC197_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC197_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC197_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC197_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC197_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC197_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC197_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC197_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC197_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC197_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC197_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC197_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC197_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC197_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC197_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC197_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC197_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC197_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC197_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC197_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC197_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC197_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC197_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC197_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC197_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC197_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC197_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC197_SET_STATISTICS_COUNTER 0x0d68 +#define NVC197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVC197_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC197_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC197_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC197_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC197_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC197_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC197_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC197_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC197_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC197_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC197_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC197_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC197_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC197_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC197_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC197_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC197_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC197_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC197_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC197_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC197_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC197_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC197_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC197_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC197_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC197_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC197_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC197_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC197_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC197_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC197_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC197_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC197_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC197_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC197_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC197_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC197_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC197_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC197_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC197_SET_POLY_SMOOTH 0x0db4 +#define NVC197_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC197_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_ZT_MARK 0x0db8 +#define NVC197_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NVC197_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVC197_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVC197_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC197_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC197_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC197_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC197_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC197_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC197_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC197_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC197_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_PATCH 0x0dcc +#define NVC197_SET_PATCH_SIZE 7:0 + +#define NVC197_SET_ITERATED_BLEND 0x0dd0 +#define NVC197_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC197_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC197_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC197_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC197_SET_ZCULL_CRITERION 0x0dd8 +#define NVC197_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC197_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC197_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC197_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC197_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC197_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC197_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC197_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC197_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC197_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC197_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC197_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC197_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC197_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC197_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC197_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC197_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC197_SET_SCISSOR_ENABLE_V 0:0 +#define NVC197_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC197_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC197_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC197_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC197_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC197_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC197_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0f10 +#define NVC197_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVC197_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVC197_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVC197_SET_VPC_PERF_KNOB 0x0f14 +#define NVC197_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC197_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC197_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC197_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC197_PM_LOCAL_TRIGGER 0x0f18 +#define NVC197_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC197_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC197_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC197_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC197_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC197_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC197_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC197_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC197_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC197_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC197_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC197_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC197_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC197_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC197_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC197_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC197_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC197_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC197_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC197_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC197_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC197_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC197_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC197_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC197_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC197_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC197_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC197_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC197_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC197_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC197_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC197_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC197_SET_SAMPLE_MASK 0x0fa4 +#define NVC197_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC197_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC197_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC197_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC197_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC197_SET_CT_MRT_ENABLE 0x0fac +#define NVC197_SET_CT_MRT_ENABLE_V 0:0 +#define NVC197_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC197_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC197_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC197_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC197_SET_TIR 0x0fb4 +#define NVC197_SET_TIR_MODE 1:0 +#define NVC197_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC197_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC197_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC197_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC197_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC197_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC197_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC197_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC197_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC197_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC197_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC197_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC197_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC197_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC197_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_TIR_MODULATION 0x0fd4 +#define NVC197_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC197_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC197_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC197_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC197_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC197_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC197_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC197_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC197_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC197_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC197_SET_ZT_A 0x0fe0 +#define NVC197_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_ZT_B 0x0fe4 +#define NVC197_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_ZT_FORMAT 0x0fe8 +#define NVC197_SET_ZT_FORMAT_V 4:0 +#define NVC197_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC197_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC197_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC197_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC197_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC197_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC197_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC197_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC197_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC197_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC197_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC197_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC197_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC197_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC197_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC197_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC197_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC197_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC197_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC197_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC197_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC197_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC197_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC197_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC197_SET_TILED_CACHE_BUNDLE_CONTROL 0x0ffc +#define NVC197_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT 0:0 +#define NVC197_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_FALSE 0x00000000 +#define NVC197_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_TRUE 0x00000001 + +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC197_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC197_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC197_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC197_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC197_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC197_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC197_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC197_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC197_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC197_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC197_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC197_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC197_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC197_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC197_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC197_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC197_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC197_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD02 0x102c +#define NVC197_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC197_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC197_SET_SPARE_NOOP01 0x1044 +#define NVC197_SET_SPARE_NOOP01_V 31:0 + +#define NVC197_SET_SPARE_NOOP02 0x1048 +#define NVC197_SET_SPARE_NOOP02_V 31:0 + +#define NVC197_SET_SPARE_NOOP03 0x104c +#define NVC197_SET_SPARE_NOOP03_V 31:0 + +#define NVC197_SET_SPARE_NOOP04 0x1050 +#define NVC197_SET_SPARE_NOOP04_V 31:0 + +#define NVC197_SET_SPARE_NOOP05 0x1054 +#define NVC197_SET_SPARE_NOOP05_V 31:0 + +#define NVC197_SET_SPARE_NOOP06 0x1058 +#define NVC197_SET_SPARE_NOOP06_V 31:0 + +#define NVC197_SET_SPARE_NOOP07 0x105c +#define NVC197_SET_SPARE_NOOP07_V 31:0 + +#define NVC197_SET_SPARE_NOOP08 0x1060 +#define NVC197_SET_SPARE_NOOP08_V 31:0 + +#define NVC197_SET_SPARE_NOOP09 0x1064 +#define NVC197_SET_SPARE_NOOP09_V 31:0 + +#define NVC197_SET_SPARE_NOOP10 0x1068 +#define NVC197_SET_SPARE_NOOP10_V 31:0 + +#define NVC197_SET_SPARE_NOOP11 0x106c +#define NVC197_SET_SPARE_NOOP11_V 31:0 + +#define NVC197_SET_SPARE_NOOP12 0x1070 +#define NVC197_SET_SPARE_NOOP12_V 31:0 + +#define NVC197_SET_SPARE_NOOP13 0x1074 +#define NVC197_SET_SPARE_NOOP13_V 31:0 + +#define NVC197_SET_SPARE_NOOP14 0x1078 +#define NVC197_SET_SPARE_NOOP14_V 31:0 + +#define NVC197_SET_SPARE_NOOP15 0x107c +#define NVC197_SET_SPARE_NOOP15_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC197_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC197_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC197_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC197_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC197_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC197_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC197_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC197_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC197_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC197_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC197_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC197_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC197_UNBIND_ALL 0x10f4 +#define NVC197_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC197_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC197_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC197_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC197_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC197_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC197_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC197_NO_OPERATION_DATA_HI 0x110c +#define NVC197_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC197_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC197_PM_TRIGGER_END 0x1114 +#define NVC197_PM_TRIGGER_END_V 31:0 + +#define NVC197_SET_VERTEX_ID_BASE 0x1118 +#define NVC197_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC197_SET_STENCIL_COMPRESSION 0x111c +#define NVC197_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC197_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC197_SET_TIR_CONTROL 0x1130 +#define NVC197_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC197_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC197_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC197_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC197_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC197_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC197_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC197_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC197_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 + +#define NVC197_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC197_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC197_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC197_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC197_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC197_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC197_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC197_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC197_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC197_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC197_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC197_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC197_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC197_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC197_FLUSH_PENDING_WRITES 0x1144 +#define NVC197_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC197_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC197_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC197_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC197_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC197_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC197_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC197_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC197_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC197_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC197_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC197_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC197_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC197_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC197_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC197_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC197_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC197_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC197_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC197_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC197_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC197_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC197_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_SCREEN_STATE_MASK 0x1204 +#define NVC197_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC197_SET_ZT_SPARSE 0x1208 +#define NVC197_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC197_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC197_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC197_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC197_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC197_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_SET_CT_SELECT 0x121c +#define NVC197_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC197_SET_CT_SELECT_TARGET0 6:4 +#define NVC197_SET_CT_SELECT_TARGET1 9:7 +#define NVC197_SET_CT_SELECT_TARGET2 12:10 +#define NVC197_SET_CT_SELECT_TARGET3 15:13 +#define NVC197_SET_CT_SELECT_TARGET4 18:16 +#define NVC197_SET_CT_SELECT_TARGET5 21:19 +#define NVC197_SET_CT_SELECT_TARGET6 24:22 +#define NVC197_SET_CT_SELECT_TARGET7 27:25 + +#define NVC197_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC197_SET_ZT_SIZE_A 0x1228 +#define NVC197_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC197_SET_ZT_SIZE_B 0x122c +#define NVC197_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC197_SET_ZT_SIZE_C 0x1230 +#define NVC197_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC197_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC197_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC197_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC197_SET_SAMPLER_BINDING 0x1234 +#define NVC197_SET_SAMPLER_BINDING_V 0:0 +#define NVC197_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC197_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC197_DRAW_AUTO 0x123c +#define NVC197_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC197_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC197_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC197_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC197_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC197_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC197_SET_BACK_END_COPY_A 0x1264 +#define NVC197_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC197_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC197_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC197_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC197_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BACK_END_COPY_B 0x1268 +#define NVC197_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC197_SET_BACK_END_COPY_C 0x126c +#define NVC197_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC197_SET_BACK_END_COPY_D 0x1270 +#define NVC197_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC197_SET_BACK_END_COPY_E 0x1274 +#define NVC197_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC197_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC197_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVC197_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC197_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC197_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC197_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC197_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC197_CLEAR_ZCULL_REGION 0x12c8 +#define NVC197_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC197_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC197_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC197_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC197_SET_DEPTH_TEST 0x12cc +#define NVC197_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC197_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC197_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_FILL_MODE 0x12d0 +#define NVC197_SET_FILL_MODE_V 31:0 +#define NVC197_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC197_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC197_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC197_SET_SHADE_MODE 0x12d4 +#define NVC197_SET_SHADE_MODE_V 31:0 +#define NVC197_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC197_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC197_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC197_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC197_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC197_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC197_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_DEPTH_WRITE 0x12e8 +#define NVC197_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC197_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_ALPHA_TEST 0x12ec +#define NVC197_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC197_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC197_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC197_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC197_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC197_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC197_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC197_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC197_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC197_D3D_SET_CULL_MODE 0x1308 +#define NVC197_D3D_SET_CULL_MODE_V 31:0 +#define NVC197_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC197_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC197_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC197_SET_DEPTH_FUNC 0x130c +#define NVC197_SET_DEPTH_FUNC_V 31:0 +#define NVC197_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC197_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC197_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC197_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC197_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC197_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC197_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC197_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC197_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC197_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC197_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC197_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC197_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC197_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC197_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC197_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC197_SET_ALPHA_REF 0x1310 +#define NVC197_SET_ALPHA_REF_V 31:0 + +#define NVC197_SET_ALPHA_FUNC 0x1314 +#define NVC197_SET_ALPHA_FUNC_V 31:0 +#define NVC197_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC197_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC197_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC197_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC197_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC197_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC197_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC197_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC197_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC197_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC197_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC197_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC197_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC197_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC197_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC197_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC197_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC197_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC197_SET_BLEND_CONST_RED 0x131c +#define NVC197_SET_BLEND_CONST_RED_V 31:0 + +#define NVC197_SET_BLEND_CONST_GREEN 0x1320 +#define NVC197_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC197_SET_BLEND_CONST_BLUE 0x1324 +#define NVC197_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC197_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC197_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC197_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC197_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC197_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC197_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC197_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC197_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BLEND_COLOR_OP 0x1340 +#define NVC197_SET_BLEND_COLOR_OP_V 31:0 +#define NVC197_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC197_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC197_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC197_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC197_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC197_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC197_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC197_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC197_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC197_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_BLEND_ALPHA_OP 0x134c +#define NVC197_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC197_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC197_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC197_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC197_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC197_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC197_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC197_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC197_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC197_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC197_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC197_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC197_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BLEND(i) (0x1360+(i)*4) +#define NVC197_SET_BLEND_ENABLE 0:0 +#define NVC197_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_STENCIL_TEST 0x1380 +#define NVC197_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC197_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_STENCIL_OP_FAIL 0x1384 +#define NVC197_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC197_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC197_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC197_SET_STENCIL_OP_ZPASS 0x138c +#define NVC197_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC197_SET_STENCIL_FUNC 0x1390 +#define NVC197_SET_STENCIL_FUNC_V 31:0 +#define NVC197_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC197_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC197_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC197_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC197_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC197_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC197_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC197_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC197_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC197_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC197_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC197_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC197_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC197_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC197_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC197_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC197_SET_STENCIL_FUNC_REF 0x1394 +#define NVC197_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC197_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC197_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC197_SET_STENCIL_MASK 0x139c +#define NVC197_SET_STENCIL_MASK_V 7:0 + +#define NVC197_SET_DRAW_AUTO_START 0x13a4 +#define NVC197_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC197_SET_PS_SATURATE 0x13a8 +#define NVC197_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC197_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC197_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC197_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC197_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC197_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC197_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC197_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC197_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC197_SET_WINDOW_ORIGIN 0x13ac +#define NVC197_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC197_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC197_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC197_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC197_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC197_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC197_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC197_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC197_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC197_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC197_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_ALPHA_HYSTERESIS 0x1420 +#define NVC197_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NVC197_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC197_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC197_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC197_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC197_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC197_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC197_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC197_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC197_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC197_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC197_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC197_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC197_STORE_ZCULL 0x1464 +#define NVC197_STORE_ZCULL_V 0:0 + +#define NVC197_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC197_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC197_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC197_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC197_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC197_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC197_LOAD_ZCULL 0x1500 +#define NVC197_LOAD_ZCULL_V 0:0 + +#define NVC197_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC197_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC197_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC197_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC197_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC197_SET_USER_CLIP_ENABLE 0x1510 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC197_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC197_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC197_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_POINT_SIZE 0x1518 +#define NVC197_SET_POINT_SIZE_V 31:0 + +#define NVC197_SET_ZCULL_STATS 0x151c +#define NVC197_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC197_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_POINT_SPRITE 0x1520 +#define NVC197_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC197_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC197_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC197_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC197_CLEAR_REPORT_VALUE 0x1530 +#define NVC197_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC197_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC197_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC197_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC197_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC197_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC197_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVC197_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC197_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC197_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_ZT_SELECT 0x1538 +#define NVC197_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC197_SET_RENDER_ENABLE_A 0x1550 +#define NVC197_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_RENDER_ENABLE_B 0x1554 +#define NVC197_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_RENDER_ENABLE_C 0x1558 +#define NVC197_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC197_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC197_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC197_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC197_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC197_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC197_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC197_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC197_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC197_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC197_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC197_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC197_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC197_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC197_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC197_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC197_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_TEX_HEADER_POOL_C 0x157c +#define NVC197_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC197_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC197_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC197_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC197_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC197_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC197_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC197_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC197_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC197_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC197_SET_SRGB_WRITE 0x15b8 +#define NVC197_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC197_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_DEPTH_BIAS 0x15bc +#define NVC197_SET_DEPTH_BIAS_V 31:0 + +#define NVC197_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC197_SET_RT_LAYER 0x15cc +#define NVC197_SET_RT_LAYER_V 15:0 +#define NVC197_SET_RT_LAYER_CONTROL 16:16 +#define NVC197_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC197_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC197_SET_ANTI_ALIAS 0x15d0 +#define NVC197_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC197_SET_EDGE_FLAG 0x15e4 +#define NVC197_SET_EDGE_FLAG_V 0:0 +#define NVC197_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC197_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC197_DRAW_INLINE_INDEX 0x15e8 +#define NVC197_DRAW_INLINE_INDEX_V 31:0 + +#define NVC197_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC197_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC197_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC197_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC197_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC197_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC197_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC197_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC197_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC197_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC197_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC197_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC197_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC197_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC197_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC197_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC197_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC197_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC197_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC197_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC197_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC197_SET_PROGRAM_REGION_A 0x1608 +#define NVC197_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVC197_SET_PROGRAM_REGION_B 0x160c +#define NVC197_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVC197_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC197_END 0x1614 +#define NVC197_END_V 0:0 + +#define NVC197_BEGIN 0x1618 +#define NVC197_BEGIN_OP 15:0 +#define NVC197_BEGIN_OP_POINTS 0x00000000 +#define NVC197_BEGIN_OP_LINES 0x00000001 +#define NVC197_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC197_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC197_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC197_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC197_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC197_BEGIN_OP_QUADS 0x00000007 +#define NVC197_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC197_BEGIN_OP_POLYGON 0x00000009 +#define NVC197_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC197_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC197_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_BEGIN_OP_PATCH 0x0000000E +#define NVC197_BEGIN_PRIMITIVE_ID 24:24 +#define NVC197_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC197_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC197_BEGIN_INSTANCE_ID 27:26 +#define NVC197_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC197_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC197_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC197_BEGIN_SPLIT_MODE 30:29 +#define NVC197_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC197_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC197_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC197_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC197_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVC197_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC197_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_VERTEX_ID_COPY 0x161c +#define NVC197_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC197_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC197_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC197_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC197_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC197_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC197_LOAD_PRIMITIVE_ID 0x1624 +#define NVC197_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC197_SET_SHADER_BASED_CULL 0x162c +#define NVC197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_CLASS_VERSION 0x1638 +#define NVC197_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC197_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC197_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC197_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC197_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC197_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC197_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC197_SET_DA_OUTPUT 0x164c +#define NVC197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC197_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC197_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC197_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_POINT_CENTER_MODE 0x165c +#define NVC197_SET_POINT_CENTER_MODE_V 31:0 +#define NVC197_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC197_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC197_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC197_SET_LINE_STIPPLE 0x166c +#define NVC197_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC197_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC197_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC197_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC197_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC197_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC197_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC197_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC197_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC197_SET_PROVOKING_VERTEX 0x1684 +#define NVC197_SET_PROVOKING_VERTEX_V 0:0 +#define NVC197_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC197_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC197_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC197_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC197_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_POLYGON_STIPPLE 0x168c +#define NVC197_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC197_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_SHADER_CONTROL 0x1690 +#define NVC197_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC197_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC197_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC197_CHECK_CLASS_VERSION 0x16a0 +#define NVC197_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC197_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC197_SET_SPH_VERSION 0x16a4 +#define NVC197_SET_SPH_VERSION_CURRENT 15:0 +#define NVC197_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC197_CHECK_SPH_VERSION 0x16a8 +#define NVC197_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC197_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC197_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC197_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC197_SET_AAM_VERSION 0x1790 +#define NVC197_SET_AAM_VERSION_CURRENT 15:0 +#define NVC197_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC197_CHECK_AAM_VERSION 0x1794 +#define NVC197_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC197_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC197_SET_ZT_LAYER 0x179c +#define NVC197_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC197_SET_INDEX_BUFFER_A 0x17c8 +#define NVC197_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC197_SET_INDEX_BUFFER_B 0x17cc +#define NVC197_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC197_SET_INDEX_BUFFER_C 0x17d0 +#define NVC197_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC197_SET_INDEX_BUFFER_D 0x17d4 +#define NVC197_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC197_SET_INDEX_BUFFER_E 0x17d8 +#define NVC197_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC197_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC197_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC197_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC197_SET_INDEX_BUFFER_F 0x17dc +#define NVC197_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC197_DRAW_INDEX_BUFFER 0x17e0 +#define NVC197_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC197_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC197_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC197_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC197_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC197_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC197_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC197_OGL_SET_CULL 0x1918 +#define NVC197_OGL_SET_CULL_ENABLE 0:0 +#define NVC197_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC197_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC197_OGL_SET_FRONT_FACE 0x191c +#define NVC197_OGL_SET_FRONT_FACE_V 31:0 +#define NVC197_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC197_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC197_OGL_SET_CULL_FACE 0x1920 +#define NVC197_OGL_SET_CULL_FACE_V 31:0 +#define NVC197_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC197_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC197_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC197_SET_VIEWPORT_PIXEL 0x1924 +#define NVC197_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC197_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC197_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC197_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC197_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC197_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC197_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC197_SET_USER_CLIP_OP 0x1940 +#define NVC197_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC197_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC197_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC197_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC197_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC197_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC197_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC197_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC197_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC197_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC197_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC197_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC197_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC197_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC197_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC197_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC197_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC197_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC197_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC197_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC197_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC197_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC197_INVALIDATE_ZCULL 0x1958 +#define NVC197_INVALIDATE_ZCULL_V 31:0 +#define NVC197_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC197_SET_ZCULL 0x1968 +#define NVC197_SET_ZCULL_Z_ENABLE 0:0 +#define NVC197_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC197_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_ZCULL_BOUNDS 0x196c +#define NVC197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC197_ZCULL_SYNC 0x1978 +#define NVC197_ZCULL_SYNC_V 31:0 + +#define NVC197_SET_CLIP_ID_TEST 0x197c +#define NVC197_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC197_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC197_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC197_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC197_SET_CLIP_ID 0x1984 +#define NVC197_SET_CLIP_ID_V 31:0 + +#define NVC197_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC197_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC197_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC197_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC197_SET_LOGIC_OP 0x19c4 +#define NVC197_SET_LOGIC_OP_ENABLE 0:0 +#define NVC197_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC197_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC197_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC197_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC197_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC197_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC197_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC197_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC197_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC197_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC197_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC197_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC197_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC197_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC197_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC197_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC197_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC197_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC197_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC197_SET_Z_COMPRESSION 0x19cc +#define NVC197_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC197_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC197_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC197_CLEAR_SURFACE 0x19d0 +#define NVC197_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC197_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC197_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC197_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC197_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC197_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC197_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC197_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC197_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC197_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC197_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC197_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC197_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC197_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC197_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC197_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC197_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC197_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC197_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC197_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC197_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC197_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC197_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC197_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC197_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC197_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC197_PIPE_NOP 0x1a2c +#define NVC197_PIPE_NOP_V 31:0 + +#define NVC197_SET_SPARE00 0x1a30 +#define NVC197_SET_SPARE00_V 31:0 + +#define NVC197_SET_SPARE01 0x1a34 +#define NVC197_SET_SPARE01_V 31:0 + +#define NVC197_SET_SPARE02 0x1a38 +#define NVC197_SET_SPARE02_V 31:0 + +#define NVC197_SET_SPARE03 0x1a3c +#define NVC197_SET_SPARE03_V 31:0 + +#define NVC197_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC197_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC197_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC197_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC197_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC197_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC197_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC197_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC197_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC197_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC197_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC197_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC197_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC197_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC197_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC197_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC197_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC197_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC197_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC197_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC197_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC197_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC197_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC197_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC197_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC197_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC197_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVC197_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVC197_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVC197_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVC197_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVC197_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVC197_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVC197_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVC197_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC197_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC197_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC197_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC197_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC197_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC197_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC197_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC197_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC197_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC197_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC197_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NVC197_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NVC197_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC197_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC197_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC197_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NVC197_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC197_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC197_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NVC197_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVC197_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NVC197_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NVC197_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVC197_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVC197_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC197_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC197_SET_FALCON00 0x2300 +#define NVC197_SET_FALCON00_V 31:0 + +#define NVC197_SET_FALCON01 0x2304 +#define NVC197_SET_FALCON01_V 31:0 + +#define NVC197_SET_FALCON02 0x2308 +#define NVC197_SET_FALCON02_V 31:0 + +#define NVC197_SET_FALCON03 0x230c +#define NVC197_SET_FALCON03_V 31:0 + +#define NVC197_SET_FALCON04 0x2310 +#define NVC197_SET_FALCON04_V 31:0 + +#define NVC197_SET_FALCON05 0x2314 +#define NVC197_SET_FALCON05_V 31:0 + +#define NVC197_SET_FALCON06 0x2318 +#define NVC197_SET_FALCON06_V 31:0 + +#define NVC197_SET_FALCON07 0x231c +#define NVC197_SET_FALCON07_V 31:0 + +#define NVC197_SET_FALCON08 0x2320 +#define NVC197_SET_FALCON08_V 31:0 + +#define NVC197_SET_FALCON09 0x2324 +#define NVC197_SET_FALCON09_V 31:0 + +#define NVC197_SET_FALCON10 0x2328 +#define NVC197_SET_FALCON10_V 31:0 + +#define NVC197_SET_FALCON11 0x232c +#define NVC197_SET_FALCON11_V 31:0 + +#define NVC197_SET_FALCON12 0x2330 +#define NVC197_SET_FALCON12_V 31:0 + +#define NVC197_SET_FALCON13 0x2334 +#define NVC197_SET_FALCON13_V 31:0 + +#define NVC197_SET_FALCON14 0x2338 +#define NVC197_SET_FALCON14_V 31:0 + +#define NVC197_SET_FALCON15 0x233c +#define NVC197_SET_FALCON15_V 31:0 + +#define NVC197_SET_FALCON16 0x2340 +#define NVC197_SET_FALCON16_V 31:0 + +#define NVC197_SET_FALCON17 0x2344 +#define NVC197_SET_FALCON17_V 31:0 + +#define NVC197_SET_FALCON18 0x2348 +#define NVC197_SET_FALCON18_V 31:0 + +#define NVC197_SET_FALCON19 0x234c +#define NVC197_SET_FALCON19_V 31:0 + +#define NVC197_SET_FALCON20 0x2350 +#define NVC197_SET_FALCON20_V 31:0 + +#define NVC197_SET_FALCON21 0x2354 +#define NVC197_SET_FALCON21_V 31:0 + +#define NVC197_SET_FALCON22 0x2358 +#define NVC197_SET_FALCON22_V 31:0 + +#define NVC197_SET_FALCON23 0x235c +#define NVC197_SET_FALCON23_V 31:0 + +#define NVC197_SET_FALCON24 0x2360 +#define NVC197_SET_FALCON24_V 31:0 + +#define NVC197_SET_FALCON25 0x2364 +#define NVC197_SET_FALCON25_V 31:0 + +#define NVC197_SET_FALCON26 0x2368 +#define NVC197_SET_FALCON26_V 31:0 + +#define NVC197_SET_FALCON27 0x236c +#define NVC197_SET_FALCON27_V 31:0 + +#define NVC197_SET_FALCON28 0x2370 +#define NVC197_SET_FALCON28_V 31:0 + +#define NVC197_SET_FALCON29 0x2374 +#define NVC197_SET_FALCON29_V 31:0 + +#define NVC197_SET_FALCON30 0x2378 +#define NVC197_SET_FALCON30_V 31:0 + +#define NVC197_SET_FALCON31 0x237c +#define NVC197_SET_FALCON31_V 31:0 + +#define NVC197_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC197_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC197_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC197_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC197_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC197_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC197_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC197_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC197_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC197_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC197_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC197_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC197_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC197_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC197_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC197_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC197_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC197_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC197_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC197_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC197_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC197_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC197_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC197_SET_COLOR_CLAMP 0x2600 +#define NVC197_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC197_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC197_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BINDLESS_TEXTURE 0x2608 +#define NVC197_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVC197_SET_TRAP_HANDLER 0x260c +#define NVC197_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVC197_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC197_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC197_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC197_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC197_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC197_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC197_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC197_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC197_CALL_MME_MACRO_V 31:0 + +#define NVC197_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC197_CALL_MME_DATA_V 31:0 + +#endif /* _cl_pascal_b_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc1b0.h b/userspace/sdks/nv570/nvidia/inc/class/clc1b0.h new file mode 100644 index 0000000..ec139e9 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc1b0.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "nvtypes.h" + +#ifndef _clc1b0_h_ +#define _clc1b0_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC1B0_VIDEO_DECODER (0x0000C1B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc1b0_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc1b5.h b/userspace/sdks/nv570/nvidia/inc/class/clc1b5.h new file mode 100644 index 0000000..fff8467 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc1b5.h @@ -0,0 +1,273 @@ +/******************************************************************************* + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clc1b5_h_ +#define _clc1b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define PASCAL_DMA_COPY_B (0x0000C1B5) + +#define NVC1B5_NOP (0x00000100) +#define NVC1B5_NOP_PARAMETER 31:0 +#define NVC1B5_PM_TRIGGER (0x00000140) +#define NVC1B5_PM_TRIGGER_V 31:0 +#define NVC1B5_SET_SEMAPHORE_A (0x00000240) +#define NVC1B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC1B5_SET_SEMAPHORE_B (0x00000244) +#define NVC1B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC1B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC1B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC1B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC1B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC1B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC1B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC1B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC1B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC1B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC1B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC1B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC1B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC1B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC1B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC1B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC1B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC1B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC1B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC1B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC1B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC1B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC1B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC1B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC1B5_LAUNCH_DMA (0x00000300) +#define NVC1B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC1B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC1B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC1B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC1B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC1B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC1B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC1B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC1B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC1B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC1B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC1B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC1B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC1B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC1B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC1B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC1B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC1B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC1B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC1B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC1B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC1B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC1B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC1B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC1B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC1B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC1B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC1B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC1B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC1B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC1B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC1B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC1B5_LAUNCH_DMA_SRC_BYPASS_L2 20:20 +#define NVC1B5_LAUNCH_DMA_SRC_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC1B5_LAUNCH_DMA_SRC_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC1B5_LAUNCH_DMA_DST_BYPASS_L2 21:21 +#define NVC1B5_LAUNCH_DMA_DST_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC1B5_LAUNCH_DMA_DST_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC1B5_LAUNCH_DMA_VPRMODE 23:22 +#define NVC1B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVC1B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC1B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC1B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 +#define NVC1B5_OFFSET_IN_UPPER (0x00000400) +#define NVC1B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC1B5_OFFSET_IN_LOWER (0x00000404) +#define NVC1B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC1B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC1B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC1B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC1B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC1B5_PITCH_IN (0x00000410) +#define NVC1B5_PITCH_IN_VALUE 31:0 +#define NVC1B5_PITCH_OUT (0x00000414) +#define NVC1B5_PITCH_OUT_VALUE 31:0 +#define NVC1B5_LINE_LENGTH_IN (0x00000418) +#define NVC1B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC1B5_LINE_COUNT (0x0000041C) +#define NVC1B5_LINE_COUNT_VALUE 31:0 +#define NVC1B5_SET_REMAP_CONST_A (0x00000700) +#define NVC1B5_SET_REMAP_CONST_A_V 31:0 +#define NVC1B5_SET_REMAP_CONST_B (0x00000704) +#define NVC1B5_SET_REMAP_CONST_B_V 31:0 +#define NVC1B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC1B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC1B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC1B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC1B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC1B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC1B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC1B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC1B5_SET_DST_WIDTH (0x00000710) +#define NVC1B5_SET_DST_WIDTH_V 31:0 +#define NVC1B5_SET_DST_HEIGHT (0x00000714) +#define NVC1B5_SET_DST_HEIGHT_V 31:0 +#define NVC1B5_SET_DST_DEPTH (0x00000718) +#define NVC1B5_SET_DST_DEPTH_V 31:0 +#define NVC1B5_SET_DST_LAYER (0x0000071C) +#define NVC1B5_SET_DST_LAYER_V 31:0 +#define NVC1B5_SET_DST_ORIGIN (0x00000720) +#define NVC1B5_SET_DST_ORIGIN_X 15:0 +#define NVC1B5_SET_DST_ORIGIN_Y 31:16 +#define NVC1B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC1B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC1B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC1B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC1B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC1B5_SET_SRC_WIDTH (0x0000072C) +#define NVC1B5_SET_SRC_WIDTH_V 31:0 +#define NVC1B5_SET_SRC_HEIGHT (0x00000730) +#define NVC1B5_SET_SRC_HEIGHT_V 31:0 +#define NVC1B5_SET_SRC_DEPTH (0x00000734) +#define NVC1B5_SET_SRC_DEPTH_V 31:0 +#define NVC1B5_SET_SRC_LAYER (0x00000738) +#define NVC1B5_SET_SRC_LAYER_V 31:0 +#define NVC1B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC1B5_SET_SRC_ORIGIN_X 15:0 +#define NVC1B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC1B5_SRC_ORIGIN_X (0x00000744) +#define NVC1B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC1B5_SRC_ORIGIN_Y (0x00000748) +#define NVC1B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC1B5_DST_ORIGIN_X (0x0000074C) +#define NVC1B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC1B5_DST_ORIGIN_Y (0x00000750) +#define NVC1B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC1B5_PM_TRIGGER_END (0x00001114) +#define NVC1B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc1b5_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc1b5sw.h b/userspace/sdks/nv570/nvidia/inc/class/clc1b5sw.h new file mode 100644 index 0000000..27af6f2 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc1b5sw.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc1b5sw.finn +// + + + +// +// Using VERSION_0 will cause the API to interpret +// engineType as a CE engine instance. This allows +// for backward compatibility with 85B5sw and 90B5sw. +// +#define NVC1B5_ALLOCATION_PARAMETERS_VERSION_0 0 + +// +// Using VERSION_1 will cause the API to interpret +// engineType as an NV2080_ENGINE_TYPE ordinal. +// +#define NVC1B5_ALLOCATION_PARAMETERS_VERSION_1 1 + +#define NVC1B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc1b5U) + +typedef struct NVC1B5_ALLOCATION_PARAMETERS { + NvU32 version; + NvU32 engineType; +} NVC1B5_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc1b7.h b/userspace/sdks/nv570/nvidia/inc/class/clc1b7.h new file mode 100644 index 0000000..14d94ed --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc1b7.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clc1b7_h +#define clc1b7_h + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC1B7_VIDEO_ENCODER (0x0000C1B7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc1b7_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc1c0.h b/userspace/sdks/nv570/nvidia/inc/class/clc1c0.h new file mode 100644 index 0000000..f2569bf --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc1c0.h @@ -0,0 +1,795 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_pascal_compute_b_h_ +#define _cl_pascal_compute_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl pascal_compute_b */ + +#include "nvtypes.h" + +#define PASCAL_COMPUTE_B 0xC1C0 + +#define NVC1C0_SET_OBJECT 0x0000 +#define NVC1C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC1C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC1C0_NO_OPERATION 0x0100 +#define NVC1C0_NO_OPERATION_V 31:0 + +#define NVC1C0_SET_NOTIFY_A 0x0104 +#define NVC1C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC1C0_SET_NOTIFY_B 0x0108 +#define NVC1C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_NOTIFY 0x010c +#define NVC1C0_NOTIFY_TYPE 31:0 +#define NVC1C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC1C0_WAIT_FOR_IDLE 0x0110 +#define NVC1C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC1C0_SEND_GO_IDLE 0x013c +#define NVC1C0_SEND_GO_IDLE_V 31:0 + +#define NVC1C0_PM_TRIGGER 0x0140 +#define NVC1C0_PM_TRIGGER_V 31:0 + +#define NVC1C0_PM_TRIGGER_WFI 0x0144 +#define NVC1C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC1C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC1C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC1C0_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC1C0_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC1C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC1C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC1C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC1C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC1C0_LINE_LENGTH_IN 0x0180 +#define NVC1C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC1C0_LINE_COUNT 0x0184 +#define NVC1C0_LINE_COUNT_VALUE 31:0 + +#define NVC1C0_OFFSET_OUT_UPPER 0x0188 +#define NVC1C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC1C0_OFFSET_OUT 0x018c +#define NVC1C0_OFFSET_OUT_VALUE 31:0 + +#define NVC1C0_PITCH_OUT 0x0190 +#define NVC1C0_PITCH_OUT_VALUE 31:0 + +#define NVC1C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC1C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC1C0_SET_DST_WIDTH 0x0198 +#define NVC1C0_SET_DST_WIDTH_V 31:0 + +#define NVC1C0_SET_DST_HEIGHT 0x019c +#define NVC1C0_SET_DST_HEIGHT_V 31:0 + +#define NVC1C0_SET_DST_DEPTH 0x01a0 +#define NVC1C0_SET_DST_DEPTH_V 31:0 + +#define NVC1C0_SET_DST_LAYER 0x01a4 +#define NVC1C0_SET_DST_LAYER_V 31:0 + +#define NVC1C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC1C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC1C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC1C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC1C0_LAUNCH_DMA 0x01b0 +#define NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC1C0_LOAD_INLINE_DATA 0x01b4 +#define NVC1C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC1C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC1C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC1C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC1C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC1C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC1C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC1C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC1C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC1C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC1C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC1C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC1C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC1C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC1C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVC1C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVC1C0_PERFMON_TRANSFER 0x0210 +#define NVC1C0_PERFMON_TRANSFER_V 31:0 + +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0218 +#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVC1C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC1C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC1C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC1C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC1C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC1C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC1C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC1C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC1C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC1C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC1C0_SET_CWD_CONTROL 0x0240 +#define NVC1C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVC1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVC1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC1C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC1C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC1C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC1C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC1C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC1C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC1C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC1C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC1C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC1C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC1C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC1C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC1C0_SET_GWC_SCG_TYPE 0x026c +#define NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE 0:0 +#define NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0 0x00000000 +#define NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1 0x00000001 + +#define NVC1C0_SET_SCG_CONTROL 0x0270 +#define NVC1C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 +#define NVC1C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 +#define NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 +#define NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 +#define NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 + +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 16:0 + +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVC1C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC1C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC1C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC1C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC1C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC1C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC1C0_SET_QMD_VERSION 0x0288 +#define NVC1C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC1C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC1C0_SET_WFI_CONFIG 0x028c +#define NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI 0:0 +#define NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE 0x00000000 +#define NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE 0x00000001 + +#define NVC1C0_CHECK_QMD_VERSION 0x0290 +#define NVC1C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC1C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC1C0_WAIT_FOR_IDLE_SCG_TYPE 0x0294 +#define NVC1C0_WAIT_FOR_IDLE_SCG_TYPE_V 31:0 + +#define NVC1C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC1C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL 0x029c +#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE 0:0 +#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE 0x00000001 + +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC1C0_SCG_HYSTERESIS_CONTROL 0x02a8 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 + +#define NVC1C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC1C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC1C0_SEND_PCAS_A 0x02b4 +#define NVC1C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC1C0_SEND_PCAS_B 0x02b8 +#define NVC1C0_SEND_PCAS_B_FROM 23:0 +#define NVC1C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC1C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC1C0_SET_SPA_VERSION 0x0310 +#define NVC1C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC1C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC1C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC1C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC1C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC1C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC1C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC1C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC1C0_SET_FALCON00 0x0500 +#define NVC1C0_SET_FALCON00_V 31:0 + +#define NVC1C0_SET_FALCON01 0x0504 +#define NVC1C0_SET_FALCON01_V 31:0 + +#define NVC1C0_SET_FALCON02 0x0508 +#define NVC1C0_SET_FALCON02_V 31:0 + +#define NVC1C0_SET_FALCON03 0x050c +#define NVC1C0_SET_FALCON03_V 31:0 + +#define NVC1C0_SET_FALCON04 0x0510 +#define NVC1C0_SET_FALCON04_V 31:0 + +#define NVC1C0_SET_FALCON05 0x0514 +#define NVC1C0_SET_FALCON05_V 31:0 + +#define NVC1C0_SET_FALCON06 0x0518 +#define NVC1C0_SET_FALCON06_V 31:0 + +#define NVC1C0_SET_FALCON07 0x051c +#define NVC1C0_SET_FALCON07_V 31:0 + +#define NVC1C0_SET_FALCON08 0x0520 +#define NVC1C0_SET_FALCON08_V 31:0 + +#define NVC1C0_SET_FALCON09 0x0524 +#define NVC1C0_SET_FALCON09_V 31:0 + +#define NVC1C0_SET_FALCON10 0x0528 +#define NVC1C0_SET_FALCON10_V 31:0 + +#define NVC1C0_SET_FALCON11 0x052c +#define NVC1C0_SET_FALCON11_V 31:0 + +#define NVC1C0_SET_FALCON12 0x0530 +#define NVC1C0_SET_FALCON12_V 31:0 + +#define NVC1C0_SET_FALCON13 0x0534 +#define NVC1C0_SET_FALCON13_V 31:0 + +#define NVC1C0_SET_FALCON14 0x0538 +#define NVC1C0_SET_FALCON14_V 31:0 + +#define NVC1C0_SET_FALCON15 0x053c +#define NVC1C0_SET_FALCON15_V 31:0 + +#define NVC1C0_SET_FALCON16 0x0540 +#define NVC1C0_SET_FALCON16_V 31:0 + +#define NVC1C0_SET_FALCON17 0x0544 +#define NVC1C0_SET_FALCON17_V 31:0 + +#define NVC1C0_SET_FALCON18 0x0548 +#define NVC1C0_SET_FALCON18_V 31:0 + +#define NVC1C0_SET_FALCON19 0x054c +#define NVC1C0_SET_FALCON19_V 31:0 + +#define NVC1C0_SET_FALCON20 0x0550 +#define NVC1C0_SET_FALCON20_V 31:0 + +#define NVC1C0_SET_FALCON21 0x0554 +#define NVC1C0_SET_FALCON21_V 31:0 + +#define NVC1C0_SET_FALCON22 0x0558 +#define NVC1C0_SET_FALCON22_V 31:0 + +#define NVC1C0_SET_FALCON23 0x055c +#define NVC1C0_SET_FALCON23_V 31:0 + +#define NVC1C0_SET_FALCON24 0x0560 +#define NVC1C0_SET_FALCON24_V 31:0 + +#define NVC1C0_SET_FALCON25 0x0564 +#define NVC1C0_SET_FALCON25_V 31:0 + +#define NVC1C0_SET_FALCON26 0x0568 +#define NVC1C0_SET_FALCON26_V 31:0 + +#define NVC1C0_SET_FALCON27 0x056c +#define NVC1C0_SET_FALCON27_V 31:0 + +#define NVC1C0_SET_FALCON28 0x0570 +#define NVC1C0_SET_FALCON28_V 31:0 + +#define NVC1C0_SET_FALCON29 0x0574 +#define NVC1C0_SET_FALCON29_V 31:0 + +#define NVC1C0_SET_FALCON30 0x0578 +#define NVC1C0_SET_FALCON30_V 31:0 + +#define NVC1C0_SET_FALCON31 0x057c +#define NVC1C0_SET_FALCON31_V 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC1C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC1C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC1C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC1C0_SET_SPARE_NOOP12 0x0f44 +#define NVC1C0_SET_SPARE_NOOP12_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP13 0x0f48 +#define NVC1C0_SET_SPARE_NOOP13_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP14 0x0f4c +#define NVC1C0_SET_SPARE_NOOP14_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP15 0x0f50 +#define NVC1C0_SET_SPARE_NOOP15_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP00 0x1040 +#define NVC1C0_SET_SPARE_NOOP00_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP01 0x1044 +#define NVC1C0_SET_SPARE_NOOP01_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP02 0x1048 +#define NVC1C0_SET_SPARE_NOOP02_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP03 0x104c +#define NVC1C0_SET_SPARE_NOOP03_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP04 0x1050 +#define NVC1C0_SET_SPARE_NOOP04_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP05 0x1054 +#define NVC1C0_SET_SPARE_NOOP05_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP06 0x1058 +#define NVC1C0_SET_SPARE_NOOP06_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP07 0x105c +#define NVC1C0_SET_SPARE_NOOP07_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP08 0x1060 +#define NVC1C0_SET_SPARE_NOOP08_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP09 0x1064 +#define NVC1C0_SET_SPARE_NOOP09_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP10 0x1068 +#define NVC1C0_SET_SPARE_NOOP10_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP11 0x106c +#define NVC1C0_SET_SPARE_NOOP11_V 31:0 + +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC1C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC1C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC1C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC1C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC1C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC1C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC1C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC1C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC1C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC1C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC1C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC1C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC1C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC1C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC1C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC1C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC1C0_SET_PROGRAM_REGION_A 0x1608 +#define NVC1C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 16:0 + +#define NVC1C0_SET_PROGRAM_REGION_B 0x160c +#define NVC1C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC1C0_PIPE_NOP 0x1a2c +#define NVC1C0_PIPE_NOP_V 31:0 + +#define NVC1C0_SET_SPARE00 0x1a30 +#define NVC1C0_SET_SPARE00_V 31:0 + +#define NVC1C0_SET_SPARE01 0x1a34 +#define NVC1C0_SET_SPARE01_V 31:0 + +#define NVC1C0_SET_SPARE02 0x1a38 +#define NVC1C0_SET_SPARE02_V 31:0 + +#define NVC1C0_SET_SPARE03 0x1a3c +#define NVC1C0_SET_SPARE03_V 31:0 + +#define NVC1C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC1C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC1C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC1C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC1C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC1C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC1C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC1C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC1C0_SET_TRAP_HANDLER 0x260c +#define NVC1C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC1C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC1C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC1C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC1C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC1C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC1C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_pascal_compute_b_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc2b0.h b/userspace/sdks/nv570/nvidia/inc/class/clc2b0.h new file mode 100644 index 0000000..9961f82 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc2b0.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _clc2b0_h_ +#define _clc2b0_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC2B0_VIDEO_DECODER (0x0000C2B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc2b0_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc2b7.h b/userspace/sdks/nv570/nvidia/inc/class/clc2b7.h new file mode 100644 index 0000000..4c4e37d --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc2b7.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clc2b7_h +#define clc2b7_h + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC2B7_VIDEO_ENCODER (0x0000C2B7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc2b7_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc361.h b/userspace/sdks/nv570/nvidia/inc/class/clc361.h new file mode 100644 index 0000000..daa8841 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc361.h @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc361_h_ +#define _clc361_h_ + +#define VOLTA_USERMODE_A (0xc361) + +#define NVC361 0x0081ffff:0x00810000 +#define NVC361_NV_USERMODE__SIZE 65536 +#define NVC361_TIME_0 0x00000080 +#define NVC361_TIME_1 0x00000084 +#define NVC361_NOTIFY_CHANNEL_PENDING 0x00000090 + +#endif // _clc361_h_ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc365.h b/userspace/sdks/nv570/nvidia/inc/class/clc365.h new file mode 100644 index 0000000..2bbd766 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc365.h @@ -0,0 +1,88 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc365_h_ +#define _clc365_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define ACCESS_COUNTER_NOTIFY_BUFFER (0xc365) + +#define NVC365_NOTIFY_BUF +#define NVC365_NOTIFY_BUF_ENTRY 0x0000001f:0x00000000 +#define NVC365_NOTIFY_BUF_SIZE 32 +#define NVC365_NOTIFY_BUF_ENTRY_TYPE MW((0+0*32):(0*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_TYPE_CPU 0x00000000 +#define NVC365_NOTIFY_BUF_ENTRY_TYPE_GPU 0x00000001 +#define NVC365_NOTIFY_BUF_ENTRY_ADDR_TYPE MW((1+0*32):(0*32+1)) +#define NVC365_NOTIFY_BUF_ENTRY_ADDR_TYPE_GVA 0x00000000 +#define NVC365_NOTIFY_BUF_ENTRY_ADDR_TYPE_GPA 0x00000001 +#define NVC365_NOTIFY_BUF_ENTRY_BANK MW((5+0*32):(0*32+2)) +#define NVC365_NOTIFY_BUF_ENTRY_BANK_0 0x00000000 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_1 0x00000001 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_2 0x00000002 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_3 0x00000003 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_4 0x00000004 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_5 0x00000005 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_6 0x00000006 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_7 0x00000007 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_8 0x00000008 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_9 0x00000009 +#define NVC365_NOTIFY_BUF_ENTRY_BANK_10 0x0000000a +#define NVC365_NOTIFY_BUF_ENTRY_BANK_11 0x0000000b +#define NVC365_NOTIFY_BUF_ENTRY_BANK_12 0x0000000c +#define NVC365_NOTIFY_BUF_ENTRY_BANK_13 0x0000000d +#define NVC365_NOTIFY_BUF_ENTRY_BANK_14 0x0000000e +#define NVC365_NOTIFY_BUF_ENTRY_BANK_15 0x0000000f +#define NVC365_NOTIFY_BUF_ENTRY_APERTURE MW((9+0*32):(0*32+8)) +#define NVC365_NOTIFY_BUF_ENTRY_APERTURE_VID_MEM 0x00000000 +#define NVC365_NOTIFY_BUF_ENTRY_APERTURE_PEER_MEM 0x00000001 +#define NVC365_NOTIFY_BUF_ENTRY_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC365_NOTIFY_BUF_ENTRY_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVC365_NOTIFY_BUF_ENTRY_INST_APERTURE MW((11+0*32):(0*32+10)) +#define NVC365_NOTIFY_BUF_ENTRY_INST_APERTURE_VID_MEM 0x00000000 +#define NVC365_NOTIFY_BUF_ENTRY_INST_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC365_NOTIFY_BUF_ENTRY_INST_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVC365_NOTIFY_BUF_ENTRY_INST_LO MW((31+0*32):(0*32+12)) +#define NVC365_NOTIFY_BUF_ENTRY_INST_HI MW((31+1*32):(1*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_INST MW((31+1*32):(0*32+12)) +#define NVC365_NOTIFY_BUF_ENTRY_ADDR_LO MW((31+2*32):(2*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_ADDR_HI MW((31+3*32):(3*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_ADDR MW((31+3*32):(2*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_SUB_GRANULARITY MW((31+4*32):(4*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_NOTIFY_TAG MW((19+5*32):(5*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_COUNTER_VAL MW((15+6*32):(6*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_PEER_ID MW((2+7*32):(7*32+0)) +#define NVC365_NOTIFY_BUF_ENTRY_MMU_ENGINE_ID MW((28+7*32):(7*32+20)) +#define NVC365_NOTIFY_BUF_ENTRY_VALID MW((31+7*32):(7*32+31)) +#define NVC365_NOTIFY_BUF_ENTRY_VALID_FALSE 0x00000000 +#define NVC365_NOTIFY_BUF_ENTRY_VALID_TRUE 0x00000001 +#define NVC365_NOTIFIERS_ACCESS_COUNTER (0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc365_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc369.h b/userspace/sdks/nv570/nvidia/inc/class/clc369.h new file mode 100644 index 0000000..a73e182 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc369.h @@ -0,0 +1,77 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc369_h_ +#define _clc369_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define MMU_FAULT_BUFFER (0xc369) + +#define NVC369_BUF +#define NVC369_BUF_ENTRY 0x0000001f:0x00000000 +#define NVC369_BUF_SIZE 32 +#define NVC369_BUF_ENTRY_INST_APERTURE MW((9+0*32):(0*32+8)) +#define NVC369_BUF_ENTRY_INST_APERTURE_VID_MEM 0x00000000 +#define NVC369_BUF_ENTRY_INST_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC369_BUF_ENTRY_INST_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVC369_BUF_ENTRY_INST_LO MW((31+0*32):(0*32+12)) +#define NVC369_BUF_ENTRY_INST_HI MW((31+1*32):(1*32+0)) +#define NVC369_BUF_ENTRY_INST MW((31+1*32):(0*32+12)) +#define NVC369_BUF_ENTRY_ADDR_PHYS_APERTURE MW((1+2*32):(2*32+0)) +#define NVC369_BUF_ENTRY_ADDR_LO MW((31+2*32):(2*32+12)) +#define NVC369_BUF_ENTRY_ADDR_HI MW((31+3*32):(3*32+0)) +#define NVC369_BUF_ENTRY_ADDR MW((31+3*32):(2*32+12)) +#define NVC369_BUF_ENTRY_TIMESTAMP_LO MW((31+4*32):(4*32+0)) +#define NVC369_BUF_ENTRY_TIMESTAMP_HI MW((31+5*32):(5*32+0)) +#define NVC369_BUF_ENTRY_TIMESTAMP MW((31+5*32):(4*32+0)) +#define NVC369_BUF_ENTRY_ENGINE_ID MW((8+6*32):(6*32+0)) +#define NVC369_BUF_ENTRY_FAULT_TYPE MW((4+7*32):(7*32+0)) +#define NVC369_BUF_ENTRY_REPLAYABLE_FAULT MW((7+7*32):(7*32+7)) +#define NVC369_BUF_ENTRY_REPLAYABLE_FAULT_FALSE 0x00000000 +#define NVC369_BUF_ENTRY_REPLAYABLE_FAULT_TRUE 0x00000001 +#define NVC369_BUF_ENTRY_CLIENT MW((14+7*32):(7*32+8)) +#define NVC369_BUF_ENTRY_ACCESS_TYPE MW((19+7*32):(7*32+16)) +#define NVC369_BUF_ENTRY_MMU_CLIENT_TYPE MW((20+7*32):(7*32+20)) +#define NVC369_BUF_ENTRY_GPC_ID MW((28+7*32):(7*32+24)) +#define NVC369_BUF_ENTRY_PROTECTED_MODE MW((29+7*32):(7*32+29)) +#define NVC369_BUF_ENTRY_PROTECTED_MODE_FALSE 0x00000000 +#define NVC369_BUF_ENTRY_PROTECTED_MODE_TRUE 0x00000001 +#define NVC369_BUF_ENTRY_REPLAYABLE_FAULT_EN MW((30+7*32):(7*32+30)) +#define NVC369_BUF_ENTRY_REPLAYABLE_FAULT_EN_FALSE 0x00000000 +#define NVC369_BUF_ENTRY_REPLAYABLE_FAULT_EN_TRUE 0x00000001 +#define NVC369_BUF_ENTRY_VALID MW((31+7*32):(7*32+31)) +#define NVC369_BUF_ENTRY_VALID_FALSE 0x00000000 +#define NVC369_BUF_ENTRY_VALID_TRUE 0x00000001 +#define NVC369_NOTIFIER_MMU_FAULT_NON_REPLAYABLE 0 +#define NVC369_NOTIFIER_MMU_FAULT_REPLAYABLE 1 +#define NVC369_NOTIFIER_MMU_FAULT_ERROR 2 +#define NVC369_NOTIFIER_MMU_FAULT_NON_REPLAYABLE_IN_PRIV 3 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc369_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc36f.h b/userspace/sdks/nv570/nvidia/inc/class/clc36f.h new file mode 100644 index 0000000..cae1c68 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc36f.h @@ -0,0 +1,366 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc36f_h_ +#define _clc36f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class VOLTA_CHANNEL_GPFIFO */ +/* + * Documentation for VOLTA_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + * Note there is no .mfs file for this class. + */ +#define VOLTA_CHANNEL_GPFIFO_A (0x0000C36F) + +#define NVC36F_TYPEDEF VOLTA_CHANNELChannelGPFifoA + +/* dma flow control data structure */ +typedef volatile struct Nvc36fControl_struct { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} Nvc36fControl, VoltaAControlGPFifo; + +/* fields and values */ +#define NVC36F_NUMBER_OF_SUBCHANNELS (8) +#define NVC36F_SET_OBJECT (0x00000000) +#define NVC36F_SET_OBJECT_NVCLASS 15:0 +#define NVC36F_SET_OBJECT_ENGINE 20:16 +#define NVC36F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVC36F_ILLEGAL (0x00000004) +#define NVC36F_ILLEGAL_HANDLE 31:0 +#define NVC36F_NOP (0x00000008) +#define NVC36F_NOP_HANDLE 31:0 +#define NVC36F_SEMAPHOREA (0x00000010) +#define NVC36F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVC36F_SEMAPHOREB (0x00000014) +#define NVC36F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVC36F_SEMAPHOREC (0x00000018) +#define NVC36F_SEMAPHOREC_PAYLOAD 31:0 +#define NVC36F_SEMAPHORED (0x0000001C) +#define NVC36F_SEMAPHORED_OPERATION 4:0 +#define NVC36F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVC36F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVC36F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVC36F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVC36F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 +#define NVC36F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVC36F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVC36F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVC36F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVC36F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVC36F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVC36F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVC36F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVC36F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVC36F_SEMAPHORED_REDUCTION 30:27 +#define NVC36F_SEMAPHORED_REDUCTION_MIN 0x00000000 +#define NVC36F_SEMAPHORED_REDUCTION_MAX 0x00000001 +#define NVC36F_SEMAPHORED_REDUCTION_XOR 0x00000002 +#define NVC36F_SEMAPHORED_REDUCTION_AND 0x00000003 +#define NVC36F_SEMAPHORED_REDUCTION_OR 0x00000004 +#define NVC36F_SEMAPHORED_REDUCTION_ADD 0x00000005 +#define NVC36F_SEMAPHORED_REDUCTION_INC 0x00000006 +#define NVC36F_SEMAPHORED_REDUCTION_DEC 0x00000007 +#define NVC36F_SEMAPHORED_FORMAT 31:31 +#define NVC36F_SEMAPHORED_FORMAT_SIGNED 0x00000000 +#define NVC36F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 +#define NVC36F_NON_STALL_INTERRUPT (0x00000020) +#define NVC36F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVC36F_FB_FLUSH (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR +#define NVC36F_FB_FLUSH_HANDLE 31:0 +// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for +// specifying the page address for a targeted TLB invalidate and the uTLB for +// a targeted REPLAY_CANCEL for UVM. +// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly +// rearranged fields. +#define NVC36F_MEM_OP_A (0x00000028) +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID 6:0 // only relevant for REPLAY_CANCEL_VA_GLOBAL +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11 +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001 +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000 +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12 +#define NVC36F_MEM_OP_B (0x0000002c) +#define NVC36F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0 +#define NVC36F_MEM_OP_C (0x00000030) +#define NVC36F_MEM_OP_C_MEMBAR_TYPE 2:0 +#define NVC36F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000 +#define NVC36F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE 9:7 //only relevant for REPLAY_CANCEL_VA_GLOBAL +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ 0 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE 1 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG 2 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD 3 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK 4 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL 5 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC 6 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL 7 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE +#define NVC36F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG 19:0 +// MEM_OP_D MUST be preceded by MEM_OPs A-C. +#define NVC36F_MEM_OP_D (0x00000034) +#define NVC36F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE +#define NVC36F_MEM_OP_D_OPERATION 31:27 +#define NVC36F_MEM_OP_D_OPERATION_MEMBAR 0x00000005 +#define NVC36F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVC36F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a +#define NVC36F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NVC36F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +// CLEAN_LINES is an alias for Tegra/GPU IP usage +#define NVC36F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e +#define NVC36F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVC36F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVC36F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015 +#define NVC36F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR 0x00000016 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE 1:0 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC 0x00000000 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC 0x00000001 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL 0x00000002 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED 0x00000003 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE 2:2 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC 0x00000000 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC 0x00000001 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK 6:3 +#define NVC36F_SET_REFERENCE (0x00000050) +#define NVC36F_SET_REFERENCE_COUNT 31:0 +#define NVC36F_SEM_ADDR_LO (0x0000005c) +#define NVC36F_SEM_ADDR_LO_OFFSET 31:2 +#define NVC36F_SEM_ADDR_HI (0x00000060) +#define NVC36F_SEM_ADDR_HI_OFFSET 7:0 +#define NVC36F_SEM_PAYLOAD_LO (0x00000064) +#define NVC36F_SEM_PAYLOAD_LO_PAYLOAD 31:0 +#define NVC36F_SEM_PAYLOAD_HI (0x00000068) +#define NVC36F_SEM_PAYLOAD_HI_PAYLOAD 31:0 +#define NVC36F_SEM_EXECUTE (0x0000006c) +#define NVC36F_SEM_EXECUTE_OPERATION 2:0 +#define NVC36F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000 +#define NVC36F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001 +#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ 0x00000002 +#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003 +#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_AND 0x00000004 +#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_NOR 0x00000005 +#define NVC36F_SEM_EXECUTE_OPERATION_REDUCTION 0x00000006 +#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12 +#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS 0x00000000 +#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001 +#define NVC36F_SEM_EXECUTE_RELEASE_WFI 20:20 +#define NVC36F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000 +#define NVC36F_SEM_EXECUTE_RELEASE_WFI_EN 0x00000001 +#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE 24:24 +#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000 +#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT 0x00000001 +#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25 +#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000 +#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001 +#define NVC36F_SEM_EXECUTE_REDUCTION 30:27 +#define NVC36F_SEM_EXECUTE_REDUCTION_IMIN 0x00000000 +#define NVC36F_SEM_EXECUTE_REDUCTION_IMAX 0x00000001 +#define NVC36F_SEM_EXECUTE_REDUCTION_IXOR 0x00000002 +#define NVC36F_SEM_EXECUTE_REDUCTION_IAND 0x00000003 +#define NVC36F_SEM_EXECUTE_REDUCTION_IOR 0x00000004 +#define NVC36F_SEM_EXECUTE_REDUCTION_IADD 0x00000005 +#define NVC36F_SEM_EXECUTE_REDUCTION_INC 0x00000006 +#define NVC36F_SEM_EXECUTE_REDUCTION_DEC 0x00000007 +#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT 31:31 +#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000000 +#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000001 +#define NVC36F_WFI (0x00000078) +#define NVC36F_WFI_SCOPE 0:0 +#define NVC36F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000 +#define NVC36F_WFI_SCOPE_CURRENT_VEID 0x00000000 +#define NVC36F_WFI_SCOPE_ALL 0x00000001 +#define NVC36F_CRC_CHECK (0x0000007c) +#define NVC36F_CRC_CHECK_VALUE 31:0 +#define NVC36F_YIELD (0x00000080) +#define NVC36F_YIELD_OP 1:0 +#define NVC36F_YIELD_OP_NOP 0x00000000 +#define NVC36F_YIELD_OP_RUNLIST_TIMESLICE 0x00000002 +#define NVC36F_YIELD_OP_TSG 0x00000003 +#define NVC36F_CLEAR_FAULTED (0x00000084) +#define NVC36F_CLEAR_FAULTED_CHID 11:0 +#define NVC36F_CLEAR_FAULTED_TYPE 31:31 +#define NVC36F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED 0x00000000 +#define NVC36F_CLEAR_FAULTED_TYPE_ENG_FAULTED 0x00000001 + + +/* GPFIFO entry format */ +#define NVC36F_GP_ENTRY__SIZE 8 +#define NVC36F_GP_ENTRY0_FETCH 0:0 +#define NVC36F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVC36F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVC36F_GP_ENTRY0_GET 31:2 +#define NVC36F_GP_ENTRY0_OPERAND 31:0 +#define NVC36F_GP_ENTRY1_GET_HI 7:0 +#define NVC36F_GP_ENTRY1_PRIV 8:8 +#define NVC36F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NVC36F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NVC36F_GP_ENTRY1_LEVEL 9:9 +#define NVC36F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVC36F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVC36F_GP_ENTRY1_LENGTH 30:10 +#define NVC36F_GP_ENTRY1_SYNC 31:31 +#define NVC36F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVC36F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVC36F_GP_ENTRY1_OPCODE 7:0 +#define NVC36F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVC36F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVC36F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVC36F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVC36F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVC36F_DMA_METHOD_ADDRESS 11:0 +#define NVC36F_DMA_SUBDEVICE_MASK 15:4 +#define NVC36F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVC36F_DMA_TERT_OP 17:16 +#define NVC36F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVC36F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVC36F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVC36F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVC36F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVC36F_DMA_METHOD_COUNT_OLD 28:18 +#define NVC36F_DMA_METHOD_COUNT 28:16 +#define NVC36F_DMA_IMMD_DATA 28:16 +#define NVC36F_DMA_SEC_OP 31:29 +#define NVC36F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVC36F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVC36F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVC36F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVC36F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVC36F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVC36F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVC36F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVC36F_DMA_INCR_ADDRESS 11:0 +#define NVC36F_DMA_INCR_SUBCHANNEL 15:13 +#define NVC36F_DMA_INCR_COUNT 28:16 +#define NVC36F_DMA_INCR_OPCODE 31:29 +#define NVC36F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVC36F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVC36F_DMA_NONINCR_ADDRESS 11:0 +#define NVC36F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVC36F_DMA_NONINCR_COUNT 28:16 +#define NVC36F_DMA_NONINCR_OPCODE 31:29 +#define NVC36F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVC36F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVC36F_DMA_ONEINCR_ADDRESS 11:0 +#define NVC36F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVC36F_DMA_ONEINCR_COUNT 28:16 +#define NVC36F_DMA_ONEINCR_OPCODE 31:29 +#define NVC36F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVC36F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVC36F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVC36F_DMA_IMMD_ADDRESS 11:0 +#define NVC36F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVC36F_DMA_IMMD_DATA 28:16 +#define NVC36F_DMA_IMMD_OPCODE 31:29 +#define NVC36F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVC36F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVC36F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC36F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVC36F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVC36F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC36F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVC36F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC36F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVC36F_DMA_ENDSEG_OPCODE 31:29 +#define NVC36F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVC36F_DMA_ADDRESS 12:2 +#define NVC36F_DMA_SUBCH 15:13 +#define NVC36F_DMA_OPCODE3 17:16 +#define NVC36F_DMA_OPCODE3_NONE (0x00000000) +#define NVC36F_DMA_COUNT 28:18 +#define NVC36F_DMA_OPCODE 31:29 +#define NVC36F_DMA_OPCODE_METHOD (0x00000000) +#define NVC36F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVC36F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc36f_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc36fsw.h b/userspace/sdks/nv570/nvidia/inc/class/clc36fsw.h new file mode 100644 index 0000000..b54c505 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc36fsw.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* This file is *not* auto-generated. */ + +#ifndef _clc36f_sw_h_ +#define _clc36f_sw_h_ + +#define NVC36F_NOTIFIERS_RC (0) +#define NVC36F_NOTIFIERS_REFCNT (1) +#define NVC36F_NOTIFIERS_NONSTALL (2) +#define NVC36F_NOTIFIERS_EVENTBUFFER (3) +#define NVC36F_NOTIFIERS_IDLECHANNEL (4) +#define NVC36F_NOTIFIERS_ENDCTX (5) +#define NVC36F_NOTIFIERS_SW (6) +#define NVC36F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVC36F_NOTIFIERS_REPLAYABLE_FAULT (8) +#define NVC36F_NOTIFIERS_MAXCOUNT (9) + +/* NvNotification[] fields and values */ +#define NVC36F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVC36F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _clc36f_sw_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc370.h b/userspace/sdks/nv570/nvidia/inc/class/clc370.h new file mode 100644 index 0000000..4f6bf4b --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc370.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc370.finn +// + +#include "clc370_notification.h" + +#define NVC370_DISPLAY (0xc370U) /* finn: Evaluated from "NVC370_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NVC370_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc370U) + +typedef struct NVC370_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NVC370_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc370_notification.h b/userspace/sdks/nv570/nvidia/inc/class/clc370_notification.h new file mode 100644 index 0000000..e0c8867 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc370_notification.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc370_notification_h_ +#define _clc370_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "class/cl5070.h" + +/* event values */ +#define NVC370_NOTIFIERS_SW NV5070_NOTIFIERS_SW +#define NVC370_NOTIFIERS_BEGIN NV5070_NOTIFIERS_MAXCOUNT +#define NVC370_NOTIFIERS_VPR NVC370_NOTIFIERS_BEGIN + (0) +#define NVC370_NOTIFIERS_RG_SEM_NOTIFICATION NVC370_NOTIFIERS_VPR + (1) +#define NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION NVC370_NOTIFIERS_RG_SEM_NOTIFICATION + (1) +#define NVC370_NOTIFIERS_MAXCOUNT NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION + (1) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc370_notification_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc371.h b/userspace/sdks/nv570/nvidia/inc/class/clc371.h new file mode 100644 index 0000000..a8398cc --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc371.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc371_h_ +#define _clc371_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC371_DISP_SF_USER (0x000C371) + +typedef volatile struct _clc371_tag0 { + NvU32 dispSfUserOffset[0x400]; +} _NvC371DispSfUser, NvC371DispSfUserMap; + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _clc371_h_ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc372sw.h b/userspace/sdks/nv570/nvidia/inc/class/clc372sw.h new file mode 100644 index 0000000..552ea08 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc372sw.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc372sw_h_ +#define _clc372sw_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC372_DISPLAY_SW (0x0000C372) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc372sw_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc373.h b/userspace/sdks/nv570/nvidia/inc/class/clc373.h new file mode 100644 index 0000000..c707022 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc373.h @@ -0,0 +1,350 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc373_h_ +#define _clc373_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC373_DISP_CAPABILITIES 0xC373 + +typedef volatile struct _clc373_tag0 { + NvU32 dispCapabilities[0x400]; +} _NvC373DispCapabilities,NvC373DispCapabilities_Map ; + + +#define NVC373_SYS_CAP 0x0 /* RW-4R */ +#define NVC373_SYS_CAP_HEAD0_EXISTS 0:0 /* RWIVF */ +#define NVC373_SYS_CAP_HEAD0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_HEAD1_EXISTS 1:1 /* RWIVF */ +#define NVC373_SYS_CAP_HEAD1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_HEAD2_EXISTS 2:2 /* RWIVF */ +#define NVC373_SYS_CAP_HEAD2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_HEAD3_EXISTS 3:3 /* RWIVF */ +#define NVC373_SYS_CAP_HEAD3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_HEAD4_EXISTS 4:4 /* RWIVF */ +#define NVC373_SYS_CAP_HEAD4_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_HEAD5_EXISTS 5:5 /* RWIVF */ +#define NVC373_SYS_CAP_HEAD5_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_HEAD6_EXISTS 6:6 /* RWIVF */ +#define NVC373_SYS_CAP_HEAD6_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_HEAD7_EXISTS 7:7 /* RWIVF */ +#define NVC373_SYS_CAP_HEAD7_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVC373_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */ +#define NVC373_SYS_CAP_HEAD_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR0_EXISTS 8:8 /* RWIVF */ +#define NVC373_SYS_CAP_SOR0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR1_EXISTS 9:9 /* RWIVF */ +#define NVC373_SYS_CAP_SOR1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR2_EXISTS 10:10 /* RWIVF */ +#define NVC373_SYS_CAP_SOR2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR3_EXISTS 11:11 /* RWIVF */ +#define NVC373_SYS_CAP_SOR3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR4_EXISTS 12:12 /* RWIVF */ +#define NVC373_SYS_CAP_SOR4_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR5_EXISTS 13:13 /* RWIVF */ +#define NVC373_SYS_CAP_SOR5_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR6_EXISTS 14:14 /* RWIVF */ +#define NVC373_SYS_CAP_SOR6_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR7_EXISTS 15:15 /* RWIVF */ +#define NVC373_SYS_CAP_SOR7_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* RWIVF */ +#define NVC373_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */ +#define NVC373_SYS_CAP_SOR_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB 0x4 /* RW-4R */ +#define NVC373_SYS_CAPB_WINDOW0_EXISTS 0:0 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW1_EXISTS 1:1 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW2_EXISTS 2:2 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW3_EXISTS 3:3 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW4_EXISTS 4:4 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW4_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW5_EXISTS 5:5 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW5_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW6_EXISTS 6:6 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW6_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW7_EXISTS 7:7 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW7_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW8_EXISTS 8:8 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW8_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW8_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW8_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW9_EXISTS 9:9 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW9_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW9_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW9_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW10_EXISTS 10:10 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW10_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW10_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW10_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW11_EXISTS 11:11 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW11_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW11_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW11_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW12_EXISTS 12:12 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW12_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW12_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW12_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW13_EXISTS 13:13 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW13_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW13_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW13_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW14_EXISTS 14:14 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW14_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW14_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW14_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW15_EXISTS 15:15 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW15_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW15_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW15_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW16_EXISTS 16:16 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW16_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW16_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW16_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW17_EXISTS 17:17 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW17_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW17_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW17_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW18_EXISTS 18:18 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW18_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW18_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW18_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW19_EXISTS 19:19 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW19_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW19_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW19_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW20_EXISTS 20:20 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW20_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW20_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW20_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW21_EXISTS 21:21 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW21_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW21_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW21_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW22_EXISTS 22:22 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW22_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW22_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW22_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW23_EXISTS 23:23 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW23_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW23_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW23_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW24_EXISTS 24:24 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW24_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW24_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW24_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW25_EXISTS 25:25 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW25_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW25_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW25_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW26_EXISTS 26:26 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW26_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW26_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW26_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW27_EXISTS 27:27 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW27_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW27_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW27_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW28_EXISTS 28:28 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW28_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW28_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW28_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW29_EXISTS 29:29 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW29_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW29_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW29_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW30_EXISTS 30:30 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW30_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW30_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW30_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW31_EXISTS 31:31 /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW31_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW31_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW31_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVC373_SYS_CAPB_WINDOW_EXISTS__SIZE_1 32 /* */ +#define NVC373_SYS_CAPB_WINDOW_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SYS_CAPB_WINDOW_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC373_SYS_CAPB_WINDOW_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC373_HEAD_CAPA(i) (0x30+(i)*32) /* RW-4A */ +#define NVC373_HEAD_CAPA__SIZE_1 8 /* */ +#define NVC373_HEAD_CAPA_SCALER 0:0 /* RWIVF */ +#define NVC373_HEAD_CAPA_SCALER_TRUE 0x00000001 /* RW--V */ +#define NVC373_HEAD_CAPA_SCALER_FALSE 0x00000000 /* RW--V */ +#define NVC373_HEAD_CAPA_SCALER_INIT 0x00000000 /* RWI-V */ +#define NVC373_HEAD_CAPA_SCALER_HAS_YUV422 1:1 /* RWIVF */ +#define NVC373_HEAD_CAPA_SCALER_HAS_YUV422_TRUE 0x00000001 /* RW--V */ +#define NVC373_HEAD_CAPA_SCALER_HAS_YUV422_FALSE 0x00000000 /* RW--V */ +#define NVC373_HEAD_CAPA_SCALER_HAS_YUV422_INIT 0x00000000 /* RWI-V */ +#define NVC373_HEAD_CAPA_HSAT 2:2 /* RWIVF */ +#define NVC373_HEAD_CAPA_HSAT_TRUE 0x00000001 /* RW--V */ +#define NVC373_HEAD_CAPA_HSAT_FALSE 0x00000000 /* RW--V */ +#define NVC373_HEAD_CAPA_HSAT_INIT 0x00000000 /* RWI-V */ +#define NVC373_HEAD_CAPA_OCSC 3:3 /* RWIVF */ +#define NVC373_HEAD_CAPA_OCSC_TRUE 0x00000001 /* RW--V */ +#define NVC373_HEAD_CAPA_OCSC_FALSE 0x00000000 /* RW--V */ +#define NVC373_HEAD_CAPA_OCSC_INIT 0x00000000 /* RWI-V */ +#define NVC373_HEAD_CAPA_YUV422 4:4 /* RWIVF */ +#define NVC373_HEAD_CAPA_YUV422_TRUE 0x00000001 /* RW--V */ +#define NVC373_HEAD_CAPA_YUV422_FALSE 0x00000000 /* RW--V */ +#define NVC373_HEAD_CAPA_YUV422_INIT 0x00000000 /* RWI-V */ +#define NVC373_HEAD_CAPA_LUT_TYPE 6:5 /* RWIVF */ +#define NVC373_HEAD_CAPA_LUT_TYPE_NONE 0x00000000 /* RW--V */ +#define NVC373_HEAD_CAPA_LUT_TYPE_257 0x00000001 /* RW--V */ +#define NVC373_HEAD_CAPA_LUT_TYPE_1025 0x00000002 /* RW--V */ +#define NVC373_HEAD_CAPA_LUT_TYPE_INIT 0x00000000 /* RWI-V */ +#define NVC373_HEAD_CAPA_LUT_LOCATION 7:7 /* RWIVF */ +#define NVC373_HEAD_CAPA_LUT_LOCATION_EARLY 0x00000000 /* RW--V */ +#define NVC373_HEAD_CAPA_LUT_LOCATION_LATE 0x00000001 /* RW--V */ +#define NVC373_HEAD_CAPA_LUT_LOCATION_INIT 0x00000000 /* RWI-V */ +#define NVC373_HEAD_CAPD(i) (0x3c+(i)*32) /* RW-4A */ +#define NVC373_HEAD_CAPD__SIZE_1 8 /* */ +#define NVC373_HEAD_CAPD_MAX_PIXELS_2TAP422 15:0 /* RWIUF */ +#define NVC373_HEAD_CAPD_MAX_PIXELS_2TAP422_INIT 0x00000000 /* RWI-V */ +#define NVC373_HEAD_CAPD_MAX_PIXELS_2TAP444 31:16 /* RWIUF */ +#define NVC373_HEAD_CAPD_MAX_PIXELS_2TAP444_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP(i) (0x144+(i)*8) /* RW-4A */ +#define NVC373_SOR_CAP__SIZE_1 8 /* */ +#define NVC373_SOR_CAP_SINGLE_LVDS_18 0:0 /* RWIVF */ +#define NVC373_SOR_CAP_SINGLE_LVDS_18_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_SINGLE_LVDS_24 1:1 /* RWIVF */ +#define NVC373_SOR_CAP_SINGLE_LVDS_24_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_DUAL_LVDS_18 2:2 /* RWIVF */ +#define NVC373_SOR_CAP_DUAL_LVDS_18_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_DUAL_LVDS_24 3:3 /* RWIVF */ +#define NVC373_SOR_CAP_DUAL_LVDS_24_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_SINGLE_TMDS_A 8:8 /* RWIVF */ +#define NVC373_SOR_CAP_SINGLE_TMDS_A_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_SINGLE_TMDS_B 9:9 /* RWIVF */ +#define NVC373_SOR_CAP_SINGLE_TMDS_B_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_DUAL_TMDS 11:11 /* RWIVF */ +#define NVC373_SOR_CAP_DUAL_TMDS_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* RWIVF */ +#define NVC373_SOR_CAP_DISPLAY_OVER_PCIE_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_SDI 16:16 /* RWIVF */ +#define NVC373_SOR_CAP_SDI_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_SDI_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_SDI_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_DP_A 24:24 /* RWIVF */ +#define NVC373_SOR_CAP_DP_A_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_DP_A_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_DP_A_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_DP_B 25:25 /* RWIVF */ +#define NVC373_SOR_CAP_DP_B_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_DP_B_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_DP_B_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_DP_INTERLACE 26:26 /* RWIVF */ +#define NVC373_SOR_CAP_DP_INTERLACE_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CAP_DP_8_LANES 27:27 /* RWIVF */ +#define NVC373_SOR_CAP_DP_8_LANES_INIT 0x00000000 /* RWI-V */ +#define NVC373_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* RW--V */ +#define NVC373_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* RW--V */ +#define NVC373_SOR_CLK_CAP(i) (0x608+(i)*4) /* RW-4A */ +#define NVC373_SOR_CLK_CAP__SIZE_1 8 /* */ +#define NVC373_SOR_CLK_CAP_DP_MAX 7:0 /* RWIUF */ +#define NVC373_SOR_CLK_CAP_DP_MAX_INIT 0x00000036 /* RWI-V */ +#define NVC373_SOR_CLK_CAP_TMDS_MAX 23:16 /* RWIUF */ +#define NVC373_SOR_CLK_CAP_TMDS_MAX_INIT 0x0000003C /* RWI-V */ +#define NVC373_SOR_CLK_CAP_LVDS_MAX 31:24 /* RWIUF */ +#define NVC373_SOR_CLK_CAP_LVDS_MAX_INIT 0x00000000 /* RWI-V */ + +#ifdef __cplusplus +}; +#endif /* extern C */ +#endif //_clc373_h_ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc37a.h b/userspace/sdks/nv570/nvidia/inc/class/clc37a.h new file mode 100644 index 0000000..4a096b6 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc37a.h @@ -0,0 +1,213 @@ +/* + * Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _clc37a__h_ +#define _clc37a__h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC37A_CURSOR_IMM_CHANNEL_PIO (0x0000C37A) + +typedef volatile struct _clc37a_tag0 { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x7D]; + NvV32 Update; // 0x00000200 - 0x00000203 + NvV32 SetInterlockFlags; // 0x00000204 - 0x00000207 + NvV32 SetCursorHotSpotPointOut[2]; // 0x00000208 - 0x0000020F + NvV32 SetWindowInterlockFlags; // 0x00000210 - 0x00000213 + NvV32 Reserved02[0x37B]; +} NVC37ADispCursorImmControlPio; + +#define NVC37A_FREE (0x00000008) +#define NVC37A_FREE_COUNT 5:0 +#define NVC37A_UPDATE (0x00000200) +#define NVC37A_UPDATE_RELEASE_ELV 0:0 +#define NVC37A_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC37A_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC37A_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC37A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC37A_SET_INTERLOCK_FLAGS (0x00000204) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC37A_SET_CURSOR_HOT_SPOT_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVC37A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0 +#define NVC37A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS (0x00000210) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc37a_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc37b.h b/userspace/sdks/nv570/nvidia/inc/class/clc37b.h new file mode 100644 index 0000000..b61700e --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc37b.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _clC37b_h_ +#define _clC37b_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC37B_WINDOW_IMM_CHANNEL_DMA (0x0000C37B) + +// dma opcode instructions +#define NVC37B_DMA +#define NVC37B_DMA_OPCODE 31:29 +#define NVC37B_DMA_OPCODE_METHOD 0x00000000 +#define NVC37B_DMA_OPCODE_JUMP 0x00000001 +#define NVC37B_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC37B_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC37B_DMA_METHOD_COUNT 27:18 +#define NVC37B_DMA_METHOD_OFFSET 13:2 +#define NVC37B_DMA_DATA 31:0 +#define NVC37B_DMA_DATA_NOP 0x00000000 +#define NVC37B_DMA_JUMP_OFFSET 11:2 +#define NVC37B_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVC37B_PUT (0x00000000) +#define NVC37B_PUT_PTR 9:0 +#define NVC37B_GET (0x00000004) +#define NVC37B_GET_PTR 9:0 +#define NVC37B_UPDATE (0x00000200) +#define NVC37B_UPDATE_RELEASE_ELV 0:0 +#define NVC37B_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC37B_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC37B_UPDATE_INTERLOCK_WITH_WINDOW 1:1 +#define NVC37B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC37B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC37B_SET_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVC37B_SET_POINT_OUT_X 15:0 +#define NVC37B_SET_POINT_OUT_Y 31:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC37b_h diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc37d.h b/userspace/sdks/nv570/nvidia/inc/class/clc37d.h new file mode 100644 index 0000000..9ac7050 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc37d.h @@ -0,0 +1,953 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _clC37d_h_ +#define _clC37d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC37D_CORE_CHANNEL_DMA (0x0000C37D) + +#define NV_DISP_NOTIFIER 0x00000000 +#define NV_DISP_NOTIFIER_SIZEOF 0x00000010 +#define NV_DISP_NOTIFIER__0 0x00000000 +#define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFIER__0_FIELD 8:8 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE 9:9 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001 +#define NV_DISP_NOTIFIER__0_R1 15:10 +#define NV_DISP_NOTIFIER__0_R2 23:16 +#define NV_DISP_NOTIFIER__0_R3 29:24 +#define NV_DISP_NOTIFIER__0_STATUS 31:30 +#define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002 +#define NV_DISP_NOTIFIER__1 0x00000001 +#define NV_DISP_NOTIFIER__1_R4 31:0 +#define NV_DISP_NOTIFIER__2 0x00000002 +#define NV_DISP_NOTIFIER__2_TIMESTAMP_LO 31:0 +#define NV_DISP_NOTIFIER__3 0x00000003 +#define NV_DISP_NOTIFIER__3_TIMESTAMP_HI 31:0 + + +// dma opcode instructions +#define NVC37D_DMA +#define NVC37D_DMA_OPCODE 31:29 +#define NVC37D_DMA_OPCODE_METHOD 0x00000000 +#define NVC37D_DMA_OPCODE_JUMP 0x00000001 +#define NVC37D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC37D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC37D_DMA_METHOD_COUNT 27:18 +#define NVC37D_DMA_METHOD_OFFSET 13:2 +#define NVC37D_DMA_DATA 31:0 +#define NVC37D_DMA_DATA_NOP 0x00000000 +#define NVC37D_DMA_JUMP_OFFSET 11:2 +#define NVC37D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// if cap SUPPORT_FLEXIBLE_WIN_MAPPING is FALSE, this define can be used to obtain which head a window is mapped to +#define NVC37D_WINDOW_MAPPED_TO_HEAD(w) ((w)>>1) +#define NVC37D_GET_VALID_WINDOWMASK_FOR_HEAD(h) ((1<<((h)*2)) | (1<<((h)*2+1))) + +// class methods +#define NVC37D_PUT (0x00000000) +#define NVC37D_PUT_PTR 9:0 +#define NVC37D_GET (0x00000004) +#define NVC37D_GET_PTR 9:0 +#define NVC37D_UPDATE (0x00000200) +#define NVC37D_UPDATE_SPECIAL_HANDLING 21:20 +#define NVC37D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NVC37D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NVC37D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NVC37D_UPDATE_SPECIAL_HANDLING_REASON 19:12 +#define NVC37D_UPDATE_INHIBIT_INTERRUPTS 24:24 +#define NVC37D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NVC37D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NVC37D_UPDATE_RELEASE_ELV 0:0 +#define NVC37D_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC37D_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC37D_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC37D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC37D_SET_CONTEXT_DMA_NOTIFIER (0x00000208) +#define NVC37D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NVC37D_SET_NOTIFIER_CONTROL (0x0000020C) +#define NVC37D_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC37D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC37D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC37D_SET_NOTIFIER_CONTROL_OFFSET 11:4 +#define NVC37D_SET_NOTIFIER_CONTROL_NOTIFY 12:12 +#define NVC37D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NVC37D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NVC37D_SET_CONTROL (0x00000210) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN(i) ((i)+0):((i)+0) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN__SIZE_1 4 +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN_DISABLE (0x00000000) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN_ENABLE (0x00000001) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN0 0:0 +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN0_DISABLE (0x00000000) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN0_ENABLE (0x00000001) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN1 1:1 +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN1_DISABLE (0x00000000) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN1_ENABLE (0x00000001) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN2 2:2 +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN2_DISABLE (0x00000000) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN2_ENABLE (0x00000001) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN3 3:3 +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN3_DISABLE (0x00000000) +#define NVC37D_SET_CONTROL_FLIP_LOCK_PIN3_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS (0x00000218) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+0):((i)+0) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS (0x0000021C) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVC37D_GET_RG_SCAN_LINE(b) (0x00000220 + (b)*0x00000004) +#define NVC37D_GET_RG_SCAN_LINE_LINE 15:0 +#define NVC37D_GET_RG_SCAN_LINE_VBLANK 16:16 +#define NVC37D_GET_RG_SCAN_LINE_VBLANK_FALSE (0x00000000) +#define NVC37D_GET_RG_SCAN_LINE_VBLANK_TRUE (0x00000001) +#define NVC37D_SET_GET_BLANKING_CTRL(b) (0x00000240 + (b)*0x00000004) +#define NVC37D_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NVC37D_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NVC37D_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NVC37D_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NVC37D_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NVC37D_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) + +#define NVC37D_PIOR_SET_CONTROL(a) (0x00000280 + (a)*0x00000020) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK 7:0 +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVC37D_PIOR_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVC37D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NVC37D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NVC37D_PIOR_SET_CONTROL_PROTOCOL_EXT_SDI_SD_ENC (0x00000001) +#define NVC37D_PIOR_SET_CONTROL_PROTOCOL_EXT_SDI_HD_ENC (0x00000002) +#define NVC37D_PIOR_SET_CONTROL_PROTOCOL_DIST_RENDER_OUT (0x00000004) +#define NVC37D_PIOR_SET_CONTROL_PROTOCOL_DIST_RENDER_IN (0x00000005) +#define NVC37D_PIOR_SET_CONTROL_PROTOCOL_DIST_RENDER_INOUT (0x00000006) +#define NVC37D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 16:16 +#define NVC37D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC37D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC37D_PIOR_SET_CUSTOM_REASON(a) (0x00000284 + (a)*0x00000020) +#define NVC37D_PIOR_SET_CUSTOM_REASON_CODE 31:0 +#define NVC37D_PIOR_SET_SW_SPARE_A(a) (0x00000288 + (a)*0x00000020) +#define NVC37D_PIOR_SET_SW_SPARE_A_CODE 31:0 +#define NVC37D_PIOR_SET_SW_SPARE_B(a) (0x0000028C + (a)*0x00000020) +#define NVC37D_PIOR_SET_SW_SPARE_B_CODE 31:0 + +#define NVC37D_SOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK 7:0 +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DSI (0x0000000A) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NVC37D_SOR_SET_CONTROL_DE_SYNC_POLARITY 16:16 +#define NVC37D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC37D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NVC37D_SOR_SET_CUSTOM_REASON(a) (0x00000304 + (a)*0x00000020) +#define NVC37D_SOR_SET_CUSTOM_REASON_CODE 31:0 +#define NVC37D_SOR_SET_SW_SPARE_A(a) (0x00000308 + (a)*0x00000020) +#define NVC37D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NVC37D_SOR_SET_SW_SPARE_B(a) (0x0000030C + (a)*0x00000020) +#define NVC37D_SOR_SET_SW_SPARE_B_CODE 31:0 + +#define NVC37D_WINDOW_SET_CONTROL(a) (0x00001000 + (a)*0x00000080) +#define NVC37D_WINDOW_SET_CONTROL_OWNER 3:0 +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD(i) (0x00000000 +(i)) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD__SIZE_1 8 +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD0 (0x00000000) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD1 (0x00000001) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD2 (0x00000002) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD3 (0x00000003) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD4 (0x00000004) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD5 (0x00000005) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD6 (0x00000006) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD7 (0x00000007) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_NONE (0x0000000F) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0x00000080) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a) (0x00001008 + (a)*0x00000080) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR(a) (0x0000100C + (a)*0x00000080) +#define NVC37D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVC37D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a) (0x00001010 + (a)*0x00000080) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_MAX_PIXELS_FETCHED_PER_LINE 14:0 +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT 17:16 +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT_USAGE_NONE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT_USAGE_257 (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT_USAGE_1025 (0x00000002) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS 22:20 +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED 24:24 +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) + +#define NVC37D_HEAD_SET_PROCAMP(a) (0x00002000 + (a)*0x00000400) +#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003) +#define NVC37D_HEAD_SET_PROCAMP_CHROMA_LPF 3:3 +#define NVC37D_HEAD_SET_PROCAMP_CHROMA_LPF_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_PROCAMP_CHROMA_LPF_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_PROCAMP_SAT_COS 15:4 +#define NVC37D_HEAD_SET_PROCAMP_SAT_SINE 27:16 +#define NVC37D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 28:28 +#define NVC37D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NVC37D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NVC37D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 29:29 +#define NVC37D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL 31:30 +#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL_AUTO (0x00000000) +#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL_VIDEO (0x00000001) +#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL_GRAPHICS (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00002004 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 2:2 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 3:3 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 7:4 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000004) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000005) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000006) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000007) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000008) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 24:24 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 23:12 +#define NVC37D_HEAD_SET_CONTROL(a) (0x00002008 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTROL_STRUCTURE 1:0 +#define NVC37D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE 2:2 +#define NVC37D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_NORMAL (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 11:10 +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 8:4 +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 15:12 +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 23:22 +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 20:16 +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN 28:24 +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000004) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000005) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000006) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000007) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000008) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000009) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000B) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000C) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000D) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000E) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000F) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x00000010) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC37D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NVC37D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NVC37D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x0000200C + (a)*0x00000400) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC37D_HEAD_SET_PIXEL_REORDER_CONTROL(a) (0x00002010 + (a)*0x00000400) +#define NVC37D_HEAD_SET_PIXEL_REORDER_CONTROL_BANK_WIDTH 13:0 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00002014 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVC37D_HEAD_SET_DITHER_CONTROL(a) (0x00002018 + (a)*0x00000400) +#define NVC37D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NVC37D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS 5:4 +#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_6_BITS (0x00000000) +#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_8_BITS (0x00000001) +#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_10_BITS (0x00000002) +#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_12_BITS (0x00000003) +#define NVC37D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE 2:2 +#define NVC37D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE 10:8 +#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NVC37D_HEAD_SET_DITHER_CONTROL_PHASE 13:12 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x0000201C + (a)*0x00000400) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 0:0 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING 4:4 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 9:8 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NVC37D_HEAD_SET_DISPLAY_ID(a,b) (0x00002020 + (a)*0x00000400 + (b)*0x00000004) +#define NVC37D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00002028 + (a)*0x00000400) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC37D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR(a) (0x0000202C + (a)*0x00000400) +#define NVC37D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVC37D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS(a) (0x00002030 + (a)*0x00000400) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR 2:0 +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_NONE (0x00000000) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W32_H32 (0x00000001) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W64_H64 (0x00000002) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W128_H128 (0x00000003) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W256_H256 (0x00000004) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT 5:4 +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED 8:8 +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVC37D_HEAD_SET_STALL_LOCK(a) (0x00002034 + (a)*0x00000400) +#define NVC37D_HEAD_SET_STALL_LOCK_ENABLE 0:0 +#define NVC37D_HEAD_SET_STALL_LOCK_ENABLE_FALSE (0x00000000) +#define NVC37D_HEAD_SET_STALL_LOCK_ENABLE_TRUE (0x00000001) +#define NVC37D_HEAD_SET_STALL_LOCK_MODE 2:2 +#define NVC37D_HEAD_SET_STALL_LOCK_MODE_CONTINUOUS (0x00000000) +#define NVC37D_HEAD_SET_STALL_LOCK_MODE_ONE_SHOT (0x00000001) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN 8:4 +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC37D_HEAD_SET_STALL_LOCK_UNSTALL_MODE 12:12 +#define NVC37D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_CRASH_LOCK (0x00000000) +#define NVC37D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_LINE_LOCK (0x00000001) +#define NVC37D_HEAD_SET_STALL_LOCK_TEPOLARITY 14:14 +#define NVC37D_HEAD_SET_STALL_LOCK_TEPOLARITY_POSITIVE_TRUE (0x00000000) +#define NVC37D_HEAD_SET_STALL_LOCK_TEPOLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC37D_HEAD_SET_LOCK_CHAIN(a) (0x00002044 + (a)*0x00000400) +#define NVC37D_HEAD_SET_LOCK_CHAIN_POSITION 3:0 +#define NVC37D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x00002048 + (a)*0x00000400) +#define NVC37D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NVC37D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NVC37D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x0000204C + (a)*0x00000400) +#define NVC37D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NVC37D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NVC37D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x00002058 + (a)*0x00000400) +#define NVC37D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NVC37D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NVC37D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x0000205C + (a)*0x00000400) +#define NVC37D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NVC37D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NVC37D_HEAD_SET_DESKTOP_COLOR(a) (0x00002060 + (a)*0x00000400) +#define NVC37D_HEAD_SET_DESKTOP_COLOR_ALPHA 7:0 +#define NVC37D_HEAD_SET_DESKTOP_COLOR_RED 15:8 +#define NVC37D_HEAD_SET_DESKTOP_COLOR_GREEN 23:16 +#define NVC37D_HEAD_SET_DESKTOP_COLOR_BLUE 31:24 +#define NVC37D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000400) +#define NVC37D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NVC37D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NVC37D_HEAD_SET_RASTER_SYNC_END(a) (0x00002068 + (a)*0x00000400) +#define NVC37D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NVC37D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NVC37D_HEAD_SET_RASTER_BLANK_END(a) (0x0000206C + (a)*0x00000400) +#define NVC37D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NVC37D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NVC37D_HEAD_SET_RASTER_BLANK_START(a) (0x00002070 + (a)*0x00000400) +#define NVC37D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NVC37D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NVC37D_HEAD_SET_OVERSCAN_COLOR(a) (0x00002078 + (a)*0x00000400) +#define NVC37D_HEAD_SET_OVERSCAN_COLOR_RED_CR 9:0 +#define NVC37D_HEAD_SET_OVERSCAN_COLOR_GREEN_Y 19:10 +#define NVC37D_HEAD_SET_OVERSCAN_COLOR_BLUE_CB 29:20 +#define NVC37D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR(a) (0x0000207C + (a)*0x00000400) +#define NVC37D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_RED_CR 9:0 +#define NVC37D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_GREEN_Y 19:10 +#define NVC37D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_BLUE_CB 29:20 +#define NVC37D_HEAD_SET_HDMI_CTRL(a) (0x00002080 + (a)*0x00000400) +#define NVC37D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NVC37D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NVC37D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NVC37D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NVC37D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NVC37D_HEAD_SET_CONTEXT_DMA_CURSOR(a,b) (0x00002088 + (a)*0x00000400 + (b)*0x00000004) +#define NVC37D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0 +#define NVC37D_HEAD_SET_OFFSET_CURSOR(a,b) (0x00002090 + (a)*0x00000400 + (b)*0x00000004) +#define NVC37D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0 +#define NVC37D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x00002098 + (a)*0x00000400) +#define NVC37D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 0:0 +#define NVC37D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NVC37D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_CURSOR(a) (0x0000209C + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_FORMAT 7:0 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE 9:8 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 19:12 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 27:20 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA 29:28 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_NONE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_SRGB (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_YUV8_10 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_YUV12 (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION(a) (0x000020A0 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_K1 7:0 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT 11:8 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT 15:12 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_ZERO (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE 16:16 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_BLEND (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_XOR (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT(a) (0x000020A4 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE 1:0 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_257 (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_1025 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE 5:4 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_UNITY (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_XRBIAS (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_XVYCC (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE 9:8 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE_INDEX (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE_INTERPOLATE (0x00000001) +#define NVC37D_HEAD_SET_OFFSET_OUTPUT_LUT(a) (0x000020A8 + (a)*0x00000400) +#define NVC37D_HEAD_SET_OFFSET_OUTPUT_LUT_ORIGIN 31:0 +#define NVC37D_HEAD_SET_CONTEXT_DMA_OUTPUT_LUT(a) (0x000020AC + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTEXT_DMA_OUTPUT_LUT_HANDLE 31:0 +#define NVC37D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00002180 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NVC37D_HEAD_SET_CRC_CONTROL(a) (0x00002184 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 4:0 +#define NVC37D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 8:8 +#define NVC37D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NVC37D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC 19:12 +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_NONE (0x00000000) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SF (0x00000030) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR__SIZE_1 8 +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR0 (0x00000050) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR1 (0x00000051) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR2 (0x00000052) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR3 (0x00000053) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR4 (0x00000054) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR5 (0x00000055) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR6 (0x00000056) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR7 (0x00000057) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR(i) (0x00000060 +(i)) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR__SIZE_1 4 +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR0 (0x00000060) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR1 (0x00000061) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR2 (0x00000062) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR3 (0x00000063) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC 27:20 +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_NONE (0x00000000) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SF (0x00000030) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR__SIZE_1 8 +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR0 (0x00000050) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR1 (0x00000051) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR2 (0x00000052) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR3 (0x00000053) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR4 (0x00000054) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR5 (0x00000055) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR6 (0x00000056) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR7 (0x00000057) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR(i) (0x00000060 +(i)) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR__SIZE_1 4 +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR0 (0x00000060) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR1 (0x00000061) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR2 (0x00000062) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR3 (0x00000063) +#define NVC37D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 9:9 +#define NVC37D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_PRESENT_CONTROL(a) (0x0000218C + (a)*0x00000400) +#define NVC37D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 0:0 +#define NVC37D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NVC37D_HEAD_SET_SW_SPARE_A(a) (0x00002194 + (a)*0x00000400) +#define NVC37D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NVC37D_HEAD_SET_SW_SPARE_B(a) (0x00002198 + (a)*0x00000400) +#define NVC37D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NVC37D_HEAD_SET_SW_SPARE_C(a) (0x0000219C + (a)*0x00000400) +#define NVC37D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NVC37D_HEAD_SET_SW_SPARE_D(a) (0x000021A0 + (a)*0x00000400) +#define NVC37D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NVC37D_HEAD_SET_DISPLAY_RATE(a) (0x000021A8 + (a)*0x00000400) +#define NVC37D_HEAD_SET_DISPLAY_RATE_RUN_MODE 0:0 +#define NVC37D_HEAD_SET_DISPLAY_RATE_RUN_MODE_CONTINUOUS (0x00000000) +#define NVC37D_HEAD_SET_DISPLAY_RATE_RUN_MODE_ONE_SHOT (0x00000001) +#define NVC37D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_INTERVAL 25:4 +#define NVC37D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH 2:2 +#define NVC37D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_MIN_FRAME_IDLE(a) (0x00002218 + (a)*0x00000400) +#define NVC37D_HEAD_SET_MIN_FRAME_IDLE_LEADING_RASTER_LINES 14:0 +#define NVC37D_HEAD_SET_MIN_FRAME_IDLE_TRAILING_RASTER_LINES 30:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC37d_h diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc37dcrcnotif.h b/userspace/sdks/nv570/nvidia/inc/class/clc37dcrcnotif.h new file mode 100644 index 0000000..88b5b77 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc37dcrcnotif.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2003-2016, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __clc37dcrcnotif_h__ +#define __clc37dcrcnotif_h__ +/* This file is autogenerated. Do not edit */ + +#define NVC37D_NOTIFIER_CRC_STATUS_0 0x00000000 +#define NVC37D_NOTIFIER_CRC_STATUS_0_DONE 0:0 +#define NVC37D_NOTIFIER_CRC_STATUS_0_DONE_FALSE 0x00000000 +#define NVC37D_NOTIFIER_CRC_STATUS_0_DONE_TRUE 0x00000001 +#define NVC37D_NOTIFIER_CRC_STATUS_0_COMPOSITOR_OVERFLOW 3:3 +#define NVC37D_NOTIFIER_CRC_STATUS_0_COMPOSITOR_OVERFLOW_FALSE 0x00000000 +#define NVC37D_NOTIFIER_CRC_STATUS_0_COMPOSITOR_OVERFLOW_TRUE 0x00000001 +#define NVC37D_NOTIFIER_CRC_STATUS_0_RG_OVERFLOW 4:4 +#define NVC37D_NOTIFIER_CRC_STATUS_0_RG_OVERFLOW_FALSE 0x00000000 +#define NVC37D_NOTIFIER_CRC_STATUS_0_RG_OVERFLOW_TRUE 0x00000001 +#define NVC37D_NOTIFIER_CRC_STATUS_0_PRIMARY_OUTPUT_OVERFLOW 5:5 +#define NVC37D_NOTIFIER_CRC_STATUS_0_PRIMARY_OUTPUT_OVERFLOW_FALSE 0x00000000 +#define NVC37D_NOTIFIER_CRC_STATUS_0_PRIMARY_OUTPUT_OVERFLOW_TRUE 0x00000001 +#define NVC37D_NOTIFIER_CRC_STATUS_0_COUNT 27:16 +#define NVC37D_NOTIFIER_CRC_CRC_ENTRY0_11 0x0000000B +#define NVC37D_NOTIFIER_CRC_CRC_ENTRY0_11_COMPOSITOR_CRC 31:0 +#define NVC37D_NOTIFIER_CRC_CRC_ENTRY0_12 0x0000000C +#define NVC37D_NOTIFIER_CRC_CRC_ENTRY0_12_RG_CRC 31:0 +#define NVC37D_NOTIFIER_CRC_CRC_ENTRY0_13 0x0000000D +#define NVC37D_NOTIFIER_CRC_CRC_ENTRY0_13_PRIMARY_OUTPUT_CRC 31:0 +#define NVC37D_NOTIFIER_CRC_CRC_ENTRY1_21 0x00000015 + +#endif // __clc37dcrcnotif_h__ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc37dswspare.h b/userspace/sdks/nv570/nvidia/inc/class/clc37dswspare.h new file mode 100644 index 0000000..44b21a8 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc37dswspare.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc37d_sw_spare_h_ +#define _clc37d_sw_spare_h_ + +/* This file is *not* auto-generated. */ + +#define NVC37D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF 1:0 +#define NVC37D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF_NO_PREF (0x00000000) +#define NVC37D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF_QSYNC (0x00000001) + +#define NVC37D_HEAD_SET_SW_SPARE_A_DISABLE_MID_FRAME_AND_DWCF_WATERMARK 2:2 +#define NVC37D_HEAD_SET_SW_SPARE_A_DISABLE_MID_FRAME_AND_DWCF_WATERMARK_FALSE (0x00000000) +#define NVC37D_HEAD_SET_SW_SPARE_A_DISABLE_MID_FRAME_AND_DWCF_WATERMARK_TRUE (0x00000001) + +#endif // _clc37d_sw_spare_h_ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc37e.h b/userspace/sdks/nv570/nvidia/inc/class/clc37e.h new file mode 100644 index 0000000..f46929a --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc37e.h @@ -0,0 +1,498 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _clC37e_h_ +#define _clC37e_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC37E_WINDOW_CHANNEL_DMA (0x0000C37E) + +// dma opcode instructions +#define NVC37E_DMA +#define NVC37E_DMA_OPCODE 31:29 +#define NVC37E_DMA_OPCODE_METHOD 0x00000000 +#define NVC37E_DMA_OPCODE_JUMP 0x00000001 +#define NVC37E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC37E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC37E_DMA_METHOD_COUNT 27:18 +#define NVC37E_DMA_METHOD_OFFSET 13:2 +#define NVC37E_DMA_DATA 31:0 +#define NVC37E_DMA_DATA_NOP 0x00000000 +#define NVC37E_DMA_JUMP_OFFSET 11:2 +#define NVC37E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVC37E_PUT (0x00000000) +#define NVC37E_PUT_PTR 9:0 +#define NVC37E_GET (0x00000004) +#define NVC37E_GET_PTR 9:0 +#define NVC37E_UPDATE (0x00000200) +#define NVC37E_UPDATE_RELEASE_ELV 0:0 +#define NVC37E_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC37E_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC37E_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC37E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM 12:12 +#define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE (0x00000000) +#define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE (0x00000001) +#define NVC37E_GET_LINE (0x00000208) +#define NVC37E_GET_LINE_LINE 15:0 +#define NVC37E_SET_SEMAPHORE_CONTROL (0x0000020C) +#define NVC37E_SET_SEMAPHORE_CONTROL_OFFSET 7:0 +#define NVC37E_SET_SEMAPHORE_ACQUIRE (0x00000210) +#define NVC37E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NVC37E_SET_SEMAPHORE_RELEASE (0x00000214) +#define NVC37E_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NVC37E_SET_CONTEXT_DMA_SEMAPHORE (0x00000218) +#define NVC37E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NVC37E_SET_CONTEXT_DMA_NOTIFIER (0x0000021C) +#define NVC37E_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NVC37E_SET_NOTIFIER_CONTROL (0x00000220) +#define NVC37E_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC37E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC37E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC37E_SET_NOTIFIER_CONTROL_OFFSET 11:4 +#define NVC37E_SET_SIZE (0x00000224) +#define NVC37E_SET_SIZE_WIDTH 15:0 +#define NVC37E_SET_SIZE_HEIGHT 31:16 +#define NVC37E_SET_STORAGE (0x00000228) +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC37E_SET_STORAGE_MEMORY_LAYOUT 4:4 +#define NVC37E_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC37E_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC37E_SET_PARAMS (0x0000022C) +#define NVC37E_SET_PARAMS_FORMAT 7:0 +#define NVC37E_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NVC37E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F) +#define NVC37E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NVC37E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC37E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E) +#define NVC37E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC37E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6) +#define NVC37E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NVC37E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9) +#define NVC37E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NVC37E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NVC37E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NVC37E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024) +#define NVC37E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NVC37E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NVC37E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NVC37E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028) +#define NVC37E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029) +#define NVC37E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035) +#define NVC37E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036) +#define NVC37E_SET_PARAMS_FORMAT_Y8___U8V8_N422R (0x00000037) +#define NVC37E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038) +#define NVC37E_SET_PARAMS_FORMAT_Y8___U8___V8_N444 (0x0000003A) +#define NVC37E_SET_PARAMS_FORMAT_Y8___U8___V8_N420 (0x0000003B) +#define NVC37E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055) +#define NVC37E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056) +#define NVC37E_SET_PARAMS_FORMAT_Y10___U10V10_N422R (0x00000057) +#define NVC37E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058) +#define NVC37E_SET_PARAMS_FORMAT_Y10___U10___V10_N444 (0x0000005A) +#define NVC37E_SET_PARAMS_FORMAT_Y10___U10___V10_N420 (0x0000005B) +#define NVC37E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075) +#define NVC37E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076) +#define NVC37E_SET_PARAMS_FORMAT_Y12___U12V12_N422R (0x00000077) +#define NVC37E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078) +#define NVC37E_SET_PARAMS_FORMAT_Y12___U12___V12_N444 (0x0000007A) +#define NVC37E_SET_PARAMS_FORMAT_Y12___U12___V12_N420 (0x0000007B) +#define NVC37E_SET_PARAMS_COLOR_SPACE 9:8 +#define NVC37E_SET_PARAMS_COLOR_SPACE_RGB (0x00000000) +#define NVC37E_SET_PARAMS_COLOR_SPACE_YUV_601 (0x00000001) +#define NVC37E_SET_PARAMS_COLOR_SPACE_YUV_709 (0x00000002) +#define NVC37E_SET_PARAMS_COLOR_SPACE_YUV_2020 (0x00000003) +#define NVC37E_SET_PARAMS_INPUT_RANGE 13:12 +#define NVC37E_SET_PARAMS_INPUT_RANGE_BYPASS (0x00000000) +#define NVC37E_SET_PARAMS_INPUT_RANGE_LIMITED (0x00000001) +#define NVC37E_SET_PARAMS_INPUT_RANGE_FULL (0x00000002) +#define NVC37E_SET_PARAMS_UNDERREPLICATE 16:16 +#define NVC37E_SET_PARAMS_UNDERREPLICATE_DISABLE (0x00000000) +#define NVC37E_SET_PARAMS_UNDERREPLICATE_ENABLE (0x00000001) +#define NVC37E_SET_PARAMS_DE_GAMMA 21:20 +#define NVC37E_SET_PARAMS_DE_GAMMA_NONE (0x00000000) +#define NVC37E_SET_PARAMS_DE_GAMMA_SRGB (0x00000001) +#define NVC37E_SET_PARAMS_DE_GAMMA_YUV8_10 (0x00000002) +#define NVC37E_SET_PARAMS_DE_GAMMA_YUV12 (0x00000003) +#define NVC37E_SET_PARAMS_CSC 17:17 +#define NVC37E_SET_PARAMS_CSC_DISABLE (0x00000000) +#define NVC37E_SET_PARAMS_CSC_ENABLE (0x00000001) +#define NVC37E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18 +#define NVC37E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000) +#define NVC37E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001) +#define NVC37E_SET_PARAMS_SWAP_UV 19:19 +#define NVC37E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000) +#define NVC37E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001) +#define NVC37E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004) +#define NVC37E_SET_PLANAR_STORAGE_PITCH 12:0 +#define NVC37E_SET_CONTEXT_DMA_ISO(b) (0x00000240 + (b)*0x00000004) +#define NVC37E_SET_CONTEXT_DMA_ISO_HANDLE 31:0 +#define NVC37E_SET_OFFSET(b) (0x00000260 + (b)*0x00000004) +#define NVC37E_SET_OFFSET_ORIGIN 31:0 +#define NVC37E_SET_PROCESSING (0x00000280) +#define NVC37E_SET_PROCESSING_USE_GAIN_OFFSETS 0:0 +#define NVC37E_SET_PROCESSING_USE_GAIN_OFFSETS_DISABLE (0x00000000) +#define NVC37E_SET_PROCESSING_USE_GAIN_OFFSETS_ENABLE (0x00000001) +#define NVC37E_SET_CONVERSION_RED (0x00000284) +#define NVC37E_SET_CONVERSION_RED_GAIN 15:0 +#define NVC37E_SET_CONVERSION_RED_OFFSET 31:16 +#define NVC37E_SET_CONVERSION_GREEN (0x00000288) +#define NVC37E_SET_CONVERSION_GREEN_GAIN 15:0 +#define NVC37E_SET_CONVERSION_GREEN_OFFSET 31:16 +#define NVC37E_SET_CONVERSION_BLUE (0x0000028C) +#define NVC37E_SET_CONVERSION_BLUE_GAIN 15:0 +#define NVC37E_SET_CONVERSION_BLUE_OFFSET 31:16 +#define NVC37E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004) +#define NVC37E_SET_POINT_IN_X 15:0 +#define NVC37E_SET_POINT_IN_Y 31:16 +#define NVC37E_SET_SIZE_IN (0x00000298) +#define NVC37E_SET_SIZE_IN_WIDTH 14:0 +#define NVC37E_SET_SIZE_IN_HEIGHT 30:16 +#define NVC37E_SET_SIZE_OUT (0x000002A4) +#define NVC37E_SET_SIZE_OUT_WIDTH 14:0 +#define NVC37E_SET_SIZE_OUT_HEIGHT 30:16 +#define NVC37E_SET_CONTROL_INPUT_SCALER (0x000002A8) +#define NVC37E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVC37E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVC37E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVC37E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVC37E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVC37E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVC37E_SET_INPUT_SCALER_COEFF_VALUE (0x000002AC) +#define NVC37E_SET_INPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVC37E_SET_INPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVC37E_SET_CONTROL_INPUT_LUT (0x000002B0) +#define NVC37E_SET_CONTROL_INPUT_LUT_SIZE 1:0 +#define NVC37E_SET_CONTROL_INPUT_LUT_SIZE_SIZE_257 (0x00000000) +#define NVC37E_SET_CONTROL_INPUT_LUT_SIZE_SIZE_1025 (0x00000002) +#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE 5:4 +#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE_UNITY (0x00000000) +#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE_XRBIAS (0x00000001) +#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE_XVYCC (0x00000002) +#define NVC37E_SET_CONTROL_INPUT_LUT_OUTPUT_MODE 9:8 +#define NVC37E_SET_CONTROL_INPUT_LUT_OUTPUT_MODE_INDEX (0x00000000) +#define NVC37E_SET_CONTROL_INPUT_LUT_OUTPUT_MODE_INTERPOLATE (0x00000001) +#define NVC37E_SET_OFFSET_INPUT_LUT (0x000002B4) +#define NVC37E_SET_OFFSET_INPUT_LUT_ORIGIN 31:0 +#define NVC37E_SET_CONTEXT_DMA_INPUT_LUT (0x000002B8) +#define NVC37E_SET_CONTEXT_DMA_INPUT_LUT_HANDLE 31:0 +#define NVC37E_SET_CSC_RED2RED (0x000002BC) +#define NVC37E_SET_CSC_RED2RED_COEFF 18:0 +#define NVC37E_SET_CSC_GREEN2RED (0x000002C0) +#define NVC37E_SET_CSC_GREEN2RED_COEFF 18:0 +#define NVC37E_SET_CSC_BLUE2RED (0x000002C4) +#define NVC37E_SET_CSC_BLUE2RED_COEFF 18:0 +#define NVC37E_SET_CSC_CONSTANT2RED (0x000002C8) +#define NVC37E_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NVC37E_SET_CSC_RED2GREEN (0x000002CC) +#define NVC37E_SET_CSC_RED2GREEN_COEFF 18:0 +#define NVC37E_SET_CSC_GREEN2GREEN (0x000002D0) +#define NVC37E_SET_CSC_GREEN2GREEN_COEFF 18:0 +#define NVC37E_SET_CSC_BLUE2GREEN (0x000002D4) +#define NVC37E_SET_CSC_BLUE2GREEN_COEFF 18:0 +#define NVC37E_SET_CSC_CONSTANT2GREEN (0x000002D8) +#define NVC37E_SET_CSC_CONSTANT2GREEN_COEFF 18:0 +#define NVC37E_SET_CSC_RED2BLUE (0x000002DC) +#define NVC37E_SET_CSC_RED2BLUE_COEFF 18:0 +#define NVC37E_SET_CSC_GREEN2BLUE (0x000002E0) +#define NVC37E_SET_CSC_GREEN2BLUE_COEFF 18:0 +#define NVC37E_SET_CSC_BLUE2BLUE (0x000002E4) +#define NVC37E_SET_CSC_BLUE2BLUE_COEFF 18:0 +#define NVC37E_SET_CSC_CONSTANT2BLUE (0x000002E8) +#define NVC37E_SET_CSC_CONSTANT2BLUE_COEFF 18:0 +#define NVC37E_SET_COMPOSITION_CONTROL (0x000002EC) +#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0 +#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000) +#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001) +#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002) +#define NVC37E_SET_COMPOSITION_CONTROL_DEPTH 11:4 +#define NVC37E_SET_COMPOSITION_CONSTANT_ALPHA (0x000002F0) +#define NVC37E_SET_COMPOSITION_CONSTANT_ALPHA_K1 7:0 +#define NVC37E_SET_COMPOSITION_CONSTANT_ALPHA_K2 15:8 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT (0x000002F4) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC37E_SET_KEY_ALPHA (0x000002F8) +#define NVC37E_SET_KEY_ALPHA_MIN 15:0 +#define NVC37E_SET_KEY_ALPHA_MAX 31:16 +#define NVC37E_SET_KEY_RED_CR (0x000002FC) +#define NVC37E_SET_KEY_RED_CR_MIN 15:0 +#define NVC37E_SET_KEY_RED_CR_MAX 31:16 +#define NVC37E_SET_KEY_GREEN_Y (0x00000300) +#define NVC37E_SET_KEY_GREEN_Y_MIN 15:0 +#define NVC37E_SET_KEY_GREEN_Y_MAX 31:16 +#define NVC37E_SET_KEY_BLUE_CB (0x00000304) +#define NVC37E_SET_KEY_BLUE_CB_MIN 15:0 +#define NVC37E_SET_KEY_BLUE_CB_MAX 31:16 +#define NVC37E_SET_PRESENT_CONTROL (0x00000308) +#define NVC37E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NVC37E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4 +#define NVC37E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NVC37E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NVC37E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8 +#define NVC37E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000) +#define NVC37E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001) +#define NVC37E_SET_PRESENT_CONTROL_STEREO_MODE 13:12 +#define NVC37E_SET_PRESENT_CONTROL_STEREO_MODE_MONO (0x00000000) +#define NVC37E_SET_PRESENT_CONTROL_STEREO_MODE_PAIR_FLIP (0x00000001) +#define NVC37E_SET_PRESENT_CONTROL_STEREO_MODE_AT_ANY_FRAME (0x00000002) +#define NVC37E_SET_TIMESTAMP_ORIGIN_LO (0x00000340) +#define NVC37E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NVC37E_SET_TIMESTAMP_ORIGIN_HI (0x00000344) +#define NVC37E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NVC37E_SET_UPDATE_TIMESTAMP_LO (0x00000348) +#define NVC37E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NVC37E_SET_UPDATE_TIMESTAMP_HI (0x0000034C) +#define NVC37E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NVC37E_SET_INTERLOCK_FLAGS (0x00000370) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 0:0 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+1):((i)+1) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 1:1 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 2:2 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 3:3 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 4:4 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 5:5 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 6:6 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 7:7 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 8:8 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS (0x00000374) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC37e_h diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc397.h b/userspace/sdks/nv570/nvidia/inc/class/clc397.h new file mode 100644 index 0000000..2122c75 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc397.h @@ -0,0 +1,4219 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_volta_a_h_ +#define _cl_volta_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl volta_a */ + +#include "nvtypes.h" + +#define VOLTA_A 0xC397 + +#define NVC397_SET_OBJECT 0x0000 +#define NVC397_SET_OBJECT_CLASS_ID 15:0 +#define NVC397_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC397_NO_OPERATION 0x0100 +#define NVC397_NO_OPERATION_V 31:0 + +#define NVC397_SET_NOTIFY_A 0x0104 +#define NVC397_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC397_SET_NOTIFY_B 0x0108 +#define NVC397_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC397_NOTIFY 0x010c +#define NVC397_NOTIFY_TYPE 31:0 +#define NVC397_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC397_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC397_WAIT_FOR_IDLE 0x0110 +#define NVC397_WAIT_FOR_IDLE_V 31:0 + +#define NVC397_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC397_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC397_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC397_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC397_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC397_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC397_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC397_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC397_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC397_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC397_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC397_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC397_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC397_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC397_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC397_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC397_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC397_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC397_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC397_SEND_GO_IDLE 0x013c +#define NVC397_SEND_GO_IDLE_V 31:0 + +#define NVC397_PM_TRIGGER 0x0140 +#define NVC397_PM_TRIGGER_V 31:0 + +#define NVC397_PM_TRIGGER_WFI 0x0144 +#define NVC397_PM_TRIGGER_WFI_V 31:0 + +#define NVC397_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC397_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC397_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC397_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC397_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC397_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC397_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC397_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC397_LINE_LENGTH_IN 0x0180 +#define NVC397_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC397_LINE_COUNT 0x0184 +#define NVC397_LINE_COUNT_VALUE 31:0 + +#define NVC397_OFFSET_OUT_UPPER 0x0188 +#define NVC397_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC397_OFFSET_OUT 0x018c +#define NVC397_OFFSET_OUT_VALUE 31:0 + +#define NVC397_PITCH_OUT 0x0190 +#define NVC397_PITCH_OUT_VALUE 31:0 + +#define NVC397_SET_DST_BLOCK_SIZE 0x0194 +#define NVC397_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC397_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC397_SET_DST_WIDTH 0x0198 +#define NVC397_SET_DST_WIDTH_V 31:0 + +#define NVC397_SET_DST_HEIGHT 0x019c +#define NVC397_SET_DST_HEIGHT_V 31:0 + +#define NVC397_SET_DST_DEPTH 0x01a0 +#define NVC397_SET_DST_DEPTH_V 31:0 + +#define NVC397_SET_DST_LAYER 0x01a4 +#define NVC397_SET_DST_LAYER_V 31:0 + +#define NVC397_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC397_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC397_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC397_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC397_LAUNCH_DMA 0x01b0 +#define NVC397_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC397_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC397_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC397_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC397_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC397_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC397_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC397_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC397_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC397_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC397_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC397_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC397_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC397_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC397_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC397_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC397_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC397_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC397_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC397_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC397_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC397_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC397_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC397_LOAD_INLINE_DATA 0x01b4 +#define NVC397_LOAD_INLINE_DATA_V 31:0 + +#define NVC397_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC397_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC397_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC397_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC397_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC397_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC397_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC397_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC397_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC397_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC397_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC397_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC397_RUN_DS_NOW 0x0200 +#define NVC397_RUN_DS_NOW_V 31:0 + +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC397_SET_GS_MODE 0x0208 +#define NVC397_SET_GS_MODE_TYPE 0:0 +#define NVC397_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVC397_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVC397_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC397_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC397_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC397_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC397_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC397_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_GS_DM_FIFO 0x0214 +#define NVC397_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC397_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC397_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC397_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC397_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC397_INVALIDATE_SHADER_CACHES 0x021c +#define NVC397_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC397_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC397_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC397_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC397_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC397_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC397_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC397_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC397_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC397_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC397_SET_INSTANCE_COUNT 0x0220 +#define NVC397_SET_INSTANCE_COUNT_V 31:0 + +#define NVC397_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVC397_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVC397_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC397_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVC397_SET_MME_VERSION 0x0234 +#define NVC397_SET_MME_VERSION_MAJOR 7:0 + +#define NVC397_INCREMENT_SYNC_POINT 0x02c8 +#define NVC397_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC397_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC397_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC397_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC397_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC397_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC397_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC397_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC397_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVC397_DECOMPRESS_SURFACE 0x02e0 +#define NVC397_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC397_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC397_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC397_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC397_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC397_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC397_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC397_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC397_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC397_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC397_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC397_SET_ZCULL_SUBREGION 0x02e8 +#define NVC397_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC397_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC397_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC397_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC397_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC397_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC397_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC397_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC397_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC397_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC397_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC397_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC397_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC397_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC397_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC397_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC397_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC397_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC397_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC397_DRAW_ZERO_INDEX 0x0304 +#define NVC397_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC397_SET_L1_CONFIGURATION 0x0308 +#define NVC397_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC397_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC397_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC397_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC397_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC397_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC397_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC397_SET_SPA_VERSION 0x0310 +#define NVC397_SET_SPA_VERSION_MINOR 7:0 +#define NVC397_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC397_SET_SNAP_GRID_LINE 0x0318 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC397_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC397_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC397_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC397_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC397_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC397_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC397_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC397_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC397_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC397_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC397_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC397_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC397_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC397_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC397_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC397_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC397_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC397_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC397_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC397_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC397_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC397_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC397_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC397_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC397_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC397_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC397_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC397_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC397_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC397_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC397_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC397_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC397_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC397_RESERVED_TG07 0x033c +#define NVC397_RESERVED_TG07_V 0:0 + +#define NVC397_RESERVED_TG08 0x0340 +#define NVC397_RESERVED_TG08_V 0:0 + +#define NVC397_RESERVED_TG09 0x0344 +#define NVC397_RESERVED_TG09_V 0:0 + +#define NVC397_RESERVED_TG10 0x0348 +#define NVC397_RESERVED_TG10_V 0:0 + +#define NVC397_RESERVED_TG11 0x034c +#define NVC397_RESERVED_TG11_V 0:0 + +#define NVC397_RESERVED_TG12 0x0350 +#define NVC397_RESERVED_TG12_V 0:0 + +#define NVC397_RESERVED_TG13 0x0354 +#define NVC397_RESERVED_TG13_V 0:0 + +#define NVC397_RESERVED_TG14 0x0358 +#define NVC397_RESERVED_TG14_V 0:0 + +#define NVC397_RESERVED_TG15 0x035c +#define NVC397_RESERVED_TG15_V 0:0 + +#define NVC397_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC397_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC397_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC397_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC397_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC397_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC397_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC397_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC397_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC397_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC397_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC397_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC397_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC397_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC397_SET_RASTER_ENABLE 0x037c +#define NVC397_SET_RASTER_ENABLE_V 0:0 +#define NVC397_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC397_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC397_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC397_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC397_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC397_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC397_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC397_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC397_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC397_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC397_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVC397_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVC397_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVC397_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVC397_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVC397_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVC397_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVC397_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVC397_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC397_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC397_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC397_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC397_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC397_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC397_SET_RASTER_INPUT 0x0740 +#define NVC397_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC397_SET_STREAM_OUTPUT 0x0744 +#define NVC397_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC397_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC397_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC397_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC397_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC397_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC397_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC397_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC397_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC397_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC397_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC397_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC397_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC397_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC397_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC397_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC397_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC397_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC397_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC397_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC397_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC397_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC397_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC397_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC397_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC397_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVC397_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC397_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC397_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC397_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC397_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC397_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC397_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC397_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC397_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC397_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC397_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC397_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC397_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC397_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC397_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC397_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC397_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC397_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC397_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC397_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC397_SET_ZCULL_STORAGE_B 0x07ec +#define NVC397_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC397_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC397_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC397_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC397_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC397_SET_ZT_READ_ONLY 0x07f8 +#define NVC397_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC397_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC397_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC397_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC397_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC397_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC397_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC397_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC397_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC397_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC397_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC397_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC397_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC397_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC397_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC397_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC397_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC397_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC397_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC397_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC397_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC397_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC397_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC397_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC397_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC397_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC397_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC397_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC397_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC397_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC397_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC397_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC397_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC397_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC397_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC397_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC397_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC397_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC397_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC397_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC397_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC397_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC397_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC397_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC397_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC397_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC397_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC397_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC397_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC397_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC397_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC397_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC397_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC397_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC397_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC397_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC397_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC397_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC397_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC397_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC397_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC397_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC397_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC397_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC397_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC397_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC397_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC397_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC397_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC397_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC397_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC397_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC397_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC397_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC397_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC397_SET_STATISTICS_COUNTER 0x0d68 +#define NVC397_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC397_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC397_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC397_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC397_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC397_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC397_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC397_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC397_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC397_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC397_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC397_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC397_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC397_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC397_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC397_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC397_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVC397_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC397_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC397_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC397_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC397_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC397_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC397_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC397_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC397_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC397_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC397_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC397_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC397_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC397_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC397_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC397_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC397_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC397_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC397_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC397_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC397_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC397_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC397_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC397_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC397_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC397_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC397_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC397_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC397_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC397_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC397_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC397_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC397_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC397_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC397_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC397_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC397_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC397_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC397_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC397_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC397_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC397_SET_POLY_SMOOTH 0x0db4 +#define NVC397_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC397_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC397_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC397_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC397_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC397_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC397_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC397_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC397_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC397_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_PATCH 0x0dcc +#define NVC397_SET_PATCH_SIZE 7:0 + +#define NVC397_SET_ITERATED_BLEND 0x0dd0 +#define NVC397_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC397_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC397_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC397_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC397_SET_ZCULL_CRITERION 0x0dd8 +#define NVC397_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC397_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC397_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC397_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC397_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC397_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC397_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC397_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC397_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC397_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC397_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC397_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC397_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC397_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC397_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC397_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC397_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC397_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC397_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC397_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC397_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC397_SET_SCISSOR_ENABLE_V 0:0 +#define NVC397_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC397_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC397_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC397_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC397_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC397_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC397_SET_VPC_PERF_KNOB 0x0f14 +#define NVC397_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC397_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC397_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC397_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC397_PM_LOCAL_TRIGGER 0x0f18 +#define NVC397_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC397_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC397_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC397_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC397_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC397_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC397_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC397_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC397_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC397_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC397_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC397_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC397_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC397_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC397_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC397_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC397_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC397_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC397_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC397_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC397_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC397_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC397_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC397_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC397_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC397_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC397_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC397_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC397_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC397_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC397_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC397_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC397_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC397_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC397_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC397_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC397_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC397_SET_SAMPLE_MASK 0x0fa4 +#define NVC397_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC397_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC397_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC397_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC397_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC397_SET_CT_MRT_ENABLE 0x0fac +#define NVC397_SET_CT_MRT_ENABLE_V 0:0 +#define NVC397_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC397_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC397_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC397_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC397_SET_TIR 0x0fb4 +#define NVC397_SET_TIR_MODE 1:0 +#define NVC397_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC397_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC397_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC397_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC397_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC397_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC397_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC397_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC397_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC397_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC397_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC397_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC397_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC397_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC397_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC397_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC397_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC397_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC397_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC397_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_TIR_MODULATION 0x0fd4 +#define NVC397_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC397_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC397_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC397_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC397_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC397_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC397_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC397_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC397_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC397_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC397_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC397_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC397_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC397_SET_ZT_A 0x0fe0 +#define NVC397_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_ZT_B 0x0fe4 +#define NVC397_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_ZT_FORMAT 0x0fe8 +#define NVC397_SET_ZT_FORMAT_V 4:0 +#define NVC397_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC397_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC397_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC397_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC397_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC397_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC397_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC397_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC397_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC397_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC397_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC397_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC397_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC397_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC397_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC397_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC397_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC397_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC397_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC397_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC397_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC397_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC397_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC397_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC397_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC397_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC397_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC397_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC397_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC397_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC397_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC397_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC397_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC397_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC397_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC397_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC397_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC397_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC397_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC397_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC397_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC397_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC397_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC397_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC397_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC397_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD02 0x102c +#define NVC397_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC397_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC397_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC397_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC397_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC397_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC397_SET_SPARE_NOOP01 0x1044 +#define NVC397_SET_SPARE_NOOP01_V 31:0 + +#define NVC397_SET_SPARE_NOOP02 0x1048 +#define NVC397_SET_SPARE_NOOP02_V 31:0 + +#define NVC397_SET_SPARE_NOOP03 0x104c +#define NVC397_SET_SPARE_NOOP03_V 31:0 + +#define NVC397_SET_SPARE_NOOP04 0x1050 +#define NVC397_SET_SPARE_NOOP04_V 31:0 + +#define NVC397_SET_SPARE_NOOP05 0x1054 +#define NVC397_SET_SPARE_NOOP05_V 31:0 + +#define NVC397_SET_SPARE_NOOP06 0x1058 +#define NVC397_SET_SPARE_NOOP06_V 31:0 + +#define NVC397_SET_SPARE_NOOP07 0x105c +#define NVC397_SET_SPARE_NOOP07_V 31:0 + +#define NVC397_SET_SPARE_NOOP08 0x1060 +#define NVC397_SET_SPARE_NOOP08_V 31:0 + +#define NVC397_SET_SPARE_NOOP09 0x1064 +#define NVC397_SET_SPARE_NOOP09_V 31:0 + +#define NVC397_SET_SPARE_NOOP10 0x1068 +#define NVC397_SET_SPARE_NOOP10_V 31:0 + +#define NVC397_SET_SPARE_NOOP11 0x106c +#define NVC397_SET_SPARE_NOOP11_V 31:0 + +#define NVC397_SET_SPARE_NOOP12 0x1070 +#define NVC397_SET_SPARE_NOOP12_V 31:0 + +#define NVC397_SET_SPARE_NOOP13 0x1074 +#define NVC397_SET_SPARE_NOOP13_V 31:0 + +#define NVC397_SET_SPARE_NOOP14 0x1078 +#define NVC397_SET_SPARE_NOOP14_V 31:0 + +#define NVC397_SET_SPARE_NOOP15 0x107c +#define NVC397_SET_SPARE_NOOP15_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC397_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC397_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC397_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC397_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC397_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC397_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC397_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC397_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC397_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC397_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC397_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC397_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC397_UNBIND_ALL 0x10f4 +#define NVC397_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC397_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC397_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC397_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC397_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC397_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC397_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC397_NO_OPERATION_DATA_HI 0x110c +#define NVC397_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC397_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC397_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC397_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC397_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC397_PM_TRIGGER_END 0x1114 +#define NVC397_PM_TRIGGER_END_V 31:0 + +#define NVC397_SET_VERTEX_ID_BASE 0x1118 +#define NVC397_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC397_SET_STENCIL_COMPRESSION 0x111c +#define NVC397_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC397_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC397_SET_TIR_CONTROL 0x1130 +#define NVC397_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC397_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC397_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC397_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC397_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC397_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC397_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC397_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC397_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 + +#define NVC397_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC397_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC397_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC397_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC397_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC397_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC397_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC397_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC397_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC397_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC397_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC397_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC397_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC397_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC397_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC397_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC397_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC397_FLUSH_PENDING_WRITES 0x1144 +#define NVC397_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC397_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC397_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC397_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC397_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC397_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC397_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC397_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC397_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC397_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC397_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC397_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC397_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC397_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC397_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC397_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC397_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC397_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC397_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC397_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC397_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC397_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC397_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_SCREEN_STATE_MASK 0x1204 +#define NVC397_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC397_SET_ZT_SPARSE 0x1208 +#define NVC397_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC397_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC397_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC397_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC397_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC397_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_SET_CT_SELECT 0x121c +#define NVC397_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC397_SET_CT_SELECT_TARGET0 6:4 +#define NVC397_SET_CT_SELECT_TARGET1 9:7 +#define NVC397_SET_CT_SELECT_TARGET2 12:10 +#define NVC397_SET_CT_SELECT_TARGET3 15:13 +#define NVC397_SET_CT_SELECT_TARGET4 18:16 +#define NVC397_SET_CT_SELECT_TARGET5 21:19 +#define NVC397_SET_CT_SELECT_TARGET6 24:22 +#define NVC397_SET_CT_SELECT_TARGET7 27:25 + +#define NVC397_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC397_SET_ZT_SIZE_A 0x1228 +#define NVC397_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC397_SET_ZT_SIZE_B 0x122c +#define NVC397_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC397_SET_ZT_SIZE_C 0x1230 +#define NVC397_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC397_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC397_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC397_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC397_SET_SAMPLER_BINDING 0x1234 +#define NVC397_SET_SAMPLER_BINDING_V 0:0 +#define NVC397_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC397_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC397_DRAW_AUTO 0x123c +#define NVC397_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC397_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC397_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC397_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC397_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC397_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC397_SET_BACK_END_COPY_A 0x1264 +#define NVC397_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC397_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC397_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC397_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC397_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BACK_END_COPY_B 0x1268 +#define NVC397_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC397_SET_BACK_END_COPY_C 0x126c +#define NVC397_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC397_SET_BACK_END_COPY_D 0x1270 +#define NVC397_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC397_SET_BACK_END_COPY_E 0x1274 +#define NVC397_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC397_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC397_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVC397_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC397_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC397_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC397_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC397_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC397_CLEAR_ZCULL_REGION 0x12c8 +#define NVC397_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC397_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC397_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC397_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC397_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC397_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC397_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC397_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC397_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC397_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC397_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC397_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC397_SET_DEPTH_TEST 0x12cc +#define NVC397_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC397_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC397_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_FILL_MODE 0x12d0 +#define NVC397_SET_FILL_MODE_V 31:0 +#define NVC397_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC397_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC397_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC397_SET_SHADE_MODE 0x12d4 +#define NVC397_SET_SHADE_MODE_V 31:0 +#define NVC397_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC397_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC397_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC397_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC397_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC397_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC397_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC397_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC397_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC397_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC397_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC397_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_DEPTH_WRITE 0x12e8 +#define NVC397_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC397_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_ALPHA_TEST 0x12ec +#define NVC397_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC397_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC397_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC397_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC397_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC397_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC397_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC397_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC397_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC397_D3D_SET_CULL_MODE 0x1308 +#define NVC397_D3D_SET_CULL_MODE_V 31:0 +#define NVC397_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC397_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC397_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC397_SET_DEPTH_FUNC 0x130c +#define NVC397_SET_DEPTH_FUNC_V 31:0 +#define NVC397_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC397_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC397_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC397_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC397_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC397_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC397_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC397_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC397_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC397_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC397_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC397_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC397_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC397_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC397_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC397_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC397_SET_ALPHA_REF 0x1310 +#define NVC397_SET_ALPHA_REF_V 31:0 + +#define NVC397_SET_ALPHA_FUNC 0x1314 +#define NVC397_SET_ALPHA_FUNC_V 31:0 +#define NVC397_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC397_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC397_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC397_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC397_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC397_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC397_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC397_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC397_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC397_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC397_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC397_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC397_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC397_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC397_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC397_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC397_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC397_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC397_SET_BLEND_CONST_RED 0x131c +#define NVC397_SET_BLEND_CONST_RED_V 31:0 + +#define NVC397_SET_BLEND_CONST_GREEN 0x1320 +#define NVC397_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC397_SET_BLEND_CONST_BLUE 0x1324 +#define NVC397_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC397_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC397_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC397_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC397_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC397_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC397_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC397_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC397_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC397_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC397_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BLEND_COLOR_OP 0x1340 +#define NVC397_SET_BLEND_COLOR_OP_V 31:0 +#define NVC397_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC397_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC397_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC397_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC397_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC397_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC397_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC397_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC397_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC397_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_BLEND_ALPHA_OP 0x134c +#define NVC397_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC397_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC397_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC397_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC397_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC397_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC397_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC397_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC397_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC397_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC397_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC397_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC397_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC397_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC397_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC397_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BLEND(i) (0x1360+(i)*4) +#define NVC397_SET_BLEND_ENABLE 0:0 +#define NVC397_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_STENCIL_TEST 0x1380 +#define NVC397_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC397_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_STENCIL_OP_FAIL 0x1384 +#define NVC397_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC397_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC397_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC397_SET_STENCIL_OP_ZPASS 0x138c +#define NVC397_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC397_SET_STENCIL_FUNC 0x1390 +#define NVC397_SET_STENCIL_FUNC_V 31:0 +#define NVC397_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC397_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC397_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC397_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC397_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC397_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC397_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC397_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC397_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC397_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC397_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC397_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC397_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC397_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC397_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC397_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC397_SET_STENCIL_FUNC_REF 0x1394 +#define NVC397_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC397_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC397_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC397_SET_STENCIL_MASK 0x139c +#define NVC397_SET_STENCIL_MASK_V 7:0 + +#define NVC397_SET_DRAW_AUTO_START 0x13a4 +#define NVC397_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC397_SET_PS_SATURATE 0x13a8 +#define NVC397_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC397_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC397_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC397_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC397_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC397_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC397_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC397_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC397_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC397_SET_WINDOW_ORIGIN 0x13ac +#define NVC397_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC397_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC397_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC397_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC397_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC397_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC397_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC397_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC397_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC397_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC397_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC397_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC397_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC397_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC397_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC397_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC397_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC397_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC397_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC397_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC397_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC397_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC397_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC397_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC397_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC397_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC397_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC397_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC397_STORE_ZCULL 0x1464 +#define NVC397_STORE_ZCULL_V 0:0 + +#define NVC397_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC397_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC397_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC397_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC397_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC397_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC397_LOAD_ZCULL 0x1500 +#define NVC397_LOAD_ZCULL_V 0:0 + +#define NVC397_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC397_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC397_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC397_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC397_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC397_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC397_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC397_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC397_SET_USER_CLIP_ENABLE 0x1510 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC397_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC397_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC397_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_POINT_SIZE 0x1518 +#define NVC397_SET_POINT_SIZE_V 31:0 + +#define NVC397_SET_ZCULL_STATS 0x151c +#define NVC397_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC397_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_POINT_SPRITE 0x1520 +#define NVC397_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC397_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC397_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC397_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC397_CLEAR_REPORT_VALUE 0x1530 +#define NVC397_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC397_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC397_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC397_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC397_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC397_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC397_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVC397_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC397_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC397_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_ZT_SELECT 0x1538 +#define NVC397_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC397_SET_RENDER_ENABLE_A 0x1550 +#define NVC397_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_RENDER_ENABLE_B 0x1554 +#define NVC397_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_RENDER_ENABLE_C 0x1558 +#define NVC397_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC397_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC397_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC397_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC397_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC397_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC397_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC397_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC397_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC397_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC397_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC397_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC397_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC397_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC397_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC397_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC397_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_TEX_HEADER_POOL_C 0x157c +#define NVC397_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC397_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC397_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC397_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC397_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC397_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC397_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC397_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC397_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC397_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC397_SET_SRGB_WRITE 0x15b8 +#define NVC397_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC397_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_DEPTH_BIAS 0x15bc +#define NVC397_SET_DEPTH_BIAS_V 31:0 + +#define NVC397_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC397_SET_RT_LAYER 0x15cc +#define NVC397_SET_RT_LAYER_V 15:0 +#define NVC397_SET_RT_LAYER_CONTROL 16:16 +#define NVC397_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC397_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC397_SET_ANTI_ALIAS 0x15d0 +#define NVC397_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC397_SET_EDGE_FLAG 0x15e4 +#define NVC397_SET_EDGE_FLAG_V 0:0 +#define NVC397_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC397_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC397_DRAW_INLINE_INDEX 0x15e8 +#define NVC397_DRAW_INLINE_INDEX_V 31:0 + +#define NVC397_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC397_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC397_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC397_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC397_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC397_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC397_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC397_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC397_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC397_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC397_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC397_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC397_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC397_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC397_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC397_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC397_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC397_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC397_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC397_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC397_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC397_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC397_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC397_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC397_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC397_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC397_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC397_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC397_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC397_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC397_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC397_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC397_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC397_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC397_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC397_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC397_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC397_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC397_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC397_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC397_END 0x1614 +#define NVC397_END_V 0:0 + +#define NVC397_BEGIN 0x1618 +#define NVC397_BEGIN_OP 15:0 +#define NVC397_BEGIN_OP_POINTS 0x00000000 +#define NVC397_BEGIN_OP_LINES 0x00000001 +#define NVC397_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC397_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC397_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC397_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC397_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC397_BEGIN_OP_QUADS 0x00000007 +#define NVC397_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC397_BEGIN_OP_POLYGON 0x00000009 +#define NVC397_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC397_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC397_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_BEGIN_OP_PATCH 0x0000000E +#define NVC397_BEGIN_PRIMITIVE_ID 24:24 +#define NVC397_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC397_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC397_BEGIN_INSTANCE_ID 27:26 +#define NVC397_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC397_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC397_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC397_BEGIN_SPLIT_MODE 30:29 +#define NVC397_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC397_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC397_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC397_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC397_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVC397_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC397_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_VERTEX_ID_COPY 0x161c +#define NVC397_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC397_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC397_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC397_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC397_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC397_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC397_LOAD_PRIMITIVE_ID 0x1624 +#define NVC397_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC397_SET_SHADER_BASED_CULL 0x162c +#define NVC397_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC397_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC397_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC397_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_CLASS_VERSION 0x1638 +#define NVC397_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC397_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC397_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC397_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC397_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC397_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC397_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC397_SET_DA_OUTPUT 0x164c +#define NVC397_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC397_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC397_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC397_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC397_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_POINT_CENTER_MODE 0x165c +#define NVC397_SET_POINT_CENTER_MODE_V 31:0 +#define NVC397_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC397_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC397_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC397_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC397_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC397_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC397_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC397_SET_LINE_STIPPLE 0x166c +#define NVC397_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC397_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC397_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC397_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC397_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC397_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC397_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC397_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC397_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC397_SET_PROVOKING_VERTEX 0x1684 +#define NVC397_SET_PROVOKING_VERTEX_V 0:0 +#define NVC397_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC397_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC397_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC397_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC397_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_POLYGON_STIPPLE 0x168c +#define NVC397_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC397_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_SHADER_CONTROL 0x1690 +#define NVC397_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC397_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC397_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC397_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC397_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC397_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC397_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC397_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC397_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC397_CHECK_CLASS_VERSION 0x16a0 +#define NVC397_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC397_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC397_SET_SPH_VERSION 0x16a4 +#define NVC397_SET_SPH_VERSION_CURRENT 15:0 +#define NVC397_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC397_CHECK_SPH_VERSION 0x16a8 +#define NVC397_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC397_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC397_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC397_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC397_SET_AAM_VERSION 0x1790 +#define NVC397_SET_AAM_VERSION_CURRENT 15:0 +#define NVC397_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC397_CHECK_AAM_VERSION 0x1794 +#define NVC397_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC397_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC397_SET_ZT_LAYER 0x179c +#define NVC397_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC397_SET_INDEX_BUFFER_A 0x17c8 +#define NVC397_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC397_SET_INDEX_BUFFER_B 0x17cc +#define NVC397_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC397_SET_INDEX_BUFFER_C 0x17d0 +#define NVC397_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC397_SET_INDEX_BUFFER_D 0x17d4 +#define NVC397_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC397_SET_INDEX_BUFFER_E 0x17d8 +#define NVC397_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC397_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC397_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC397_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC397_SET_INDEX_BUFFER_F 0x17dc +#define NVC397_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC397_DRAW_INDEX_BUFFER 0x17e0 +#define NVC397_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC397_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC397_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC397_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC397_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC397_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC397_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC397_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC397_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC397_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC397_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC397_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC397_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC397_OGL_SET_CULL 0x1918 +#define NVC397_OGL_SET_CULL_ENABLE 0:0 +#define NVC397_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC397_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC397_OGL_SET_FRONT_FACE 0x191c +#define NVC397_OGL_SET_FRONT_FACE_V 31:0 +#define NVC397_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC397_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC397_OGL_SET_CULL_FACE 0x1920 +#define NVC397_OGL_SET_CULL_FACE_V 31:0 +#define NVC397_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC397_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC397_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC397_SET_VIEWPORT_PIXEL 0x1924 +#define NVC397_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC397_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC397_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC397_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC397_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC397_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC397_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE 17:16 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_USE_FIELD_MIN_Z_ZERO_MAX_Z_ONE 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MIN_Z_MAX_Z 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_ZERO_ONE 0x00000002 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MINUS_INF_PLUS_INF 0x00000003 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC397_SET_USER_CLIP_OP 0x1940 +#define NVC397_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC397_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC397_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC397_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC397_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC397_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC397_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC397_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC397_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC397_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC397_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC397_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC397_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC397_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC397_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC397_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC397_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC397_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC397_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC397_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC397_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC397_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC397_INVALIDATE_ZCULL 0x1958 +#define NVC397_INVALIDATE_ZCULL_V 31:0 +#define NVC397_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC397_SET_ZCULL 0x1968 +#define NVC397_SET_ZCULL_Z_ENABLE 0:0 +#define NVC397_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC397_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_ZCULL_BOUNDS 0x196c +#define NVC397_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC397_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC397_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC397_ZCULL_SYNC 0x1978 +#define NVC397_ZCULL_SYNC_V 31:0 + +#define NVC397_SET_CLIP_ID_TEST 0x197c +#define NVC397_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC397_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC397_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC397_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC397_SET_CLIP_ID 0x1984 +#define NVC397_SET_CLIP_ID_V 31:0 + +#define NVC397_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC397_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC397_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC397_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC397_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC397_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC397_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC397_SET_LOGIC_OP 0x19c4 +#define NVC397_SET_LOGIC_OP_ENABLE 0:0 +#define NVC397_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC397_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC397_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC397_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC397_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC397_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC397_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC397_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC397_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC397_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC397_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC397_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC397_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC397_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC397_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC397_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC397_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC397_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC397_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC397_SET_Z_COMPRESSION 0x19cc +#define NVC397_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC397_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC397_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC397_CLEAR_SURFACE 0x19d0 +#define NVC397_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC397_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC397_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC397_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC397_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC397_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC397_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC397_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC397_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC397_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC397_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC397_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC397_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC397_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC397_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC397_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC397_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC397_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC397_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC397_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC397_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC397_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC397_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC397_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC397_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC397_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC397_PIPE_NOP 0x1a2c +#define NVC397_PIPE_NOP_V 31:0 + +#define NVC397_SET_SPARE00 0x1a30 +#define NVC397_SET_SPARE00_V 31:0 + +#define NVC397_SET_SPARE01 0x1a34 +#define NVC397_SET_SPARE01_V 31:0 + +#define NVC397_SET_SPARE02 0x1a38 +#define NVC397_SET_SPARE02_V 31:0 + +#define NVC397_SET_SPARE03 0x1a3c +#define NVC397_SET_SPARE03_V 31:0 + +#define NVC397_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC397_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC397_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC397_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC397_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC397_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC397_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC397_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC397_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC397_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC397_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC397_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC397_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC397_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC397_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC397_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC397_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC397_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC397_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC397_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC397_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC397_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC397_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC397_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC397_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC397_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC397_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC397_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC397_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC397_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC397_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC397_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC397_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC397_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVC397_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVC397_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVC397_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVC397_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVC397_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVC397_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVC397_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVC397_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC397_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC397_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC397_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC397_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC397_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC397_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC397_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC397_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC397_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC397_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC397_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC397_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC397_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC397_SET_PIPELINE_REGISTER_COUNT_V 8:0 + +#define NVC397_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC397_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC397_SET_PIPELINE_PROGRAM_ADDRESS_A(j) (0x2014+(j)*64) +#define NVC397_SET_PIPELINE_PROGRAM_ADDRESS_A_UPPER 7:0 + +#define NVC397_SET_PIPELINE_PROGRAM_ADDRESS_B(j) (0x2018+(j)*64) +#define NVC397_SET_PIPELINE_PROGRAM_ADDRESS_B_LOWER 31:0 + +#define NVC397_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVC397_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVC397_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC397_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC397_SET_FALCON00 0x2300 +#define NVC397_SET_FALCON00_V 31:0 + +#define NVC397_SET_FALCON01 0x2304 +#define NVC397_SET_FALCON01_V 31:0 + +#define NVC397_SET_FALCON02 0x2308 +#define NVC397_SET_FALCON02_V 31:0 + +#define NVC397_SET_FALCON03 0x230c +#define NVC397_SET_FALCON03_V 31:0 + +#define NVC397_SET_FALCON04 0x2310 +#define NVC397_SET_FALCON04_V 31:0 + +#define NVC397_SET_FALCON05 0x2314 +#define NVC397_SET_FALCON05_V 31:0 + +#define NVC397_SET_FALCON06 0x2318 +#define NVC397_SET_FALCON06_V 31:0 + +#define NVC397_SET_FALCON07 0x231c +#define NVC397_SET_FALCON07_V 31:0 + +#define NVC397_SET_FALCON08 0x2320 +#define NVC397_SET_FALCON08_V 31:0 + +#define NVC397_SET_FALCON09 0x2324 +#define NVC397_SET_FALCON09_V 31:0 + +#define NVC397_SET_FALCON10 0x2328 +#define NVC397_SET_FALCON10_V 31:0 + +#define NVC397_SET_FALCON11 0x232c +#define NVC397_SET_FALCON11_V 31:0 + +#define NVC397_SET_FALCON12 0x2330 +#define NVC397_SET_FALCON12_V 31:0 + +#define NVC397_SET_FALCON13 0x2334 +#define NVC397_SET_FALCON13_V 31:0 + +#define NVC397_SET_FALCON14 0x2338 +#define NVC397_SET_FALCON14_V 31:0 + +#define NVC397_SET_FALCON15 0x233c +#define NVC397_SET_FALCON15_V 31:0 + +#define NVC397_SET_FALCON16 0x2340 +#define NVC397_SET_FALCON16_V 31:0 + +#define NVC397_SET_FALCON17 0x2344 +#define NVC397_SET_FALCON17_V 31:0 + +#define NVC397_SET_FALCON18 0x2348 +#define NVC397_SET_FALCON18_V 31:0 + +#define NVC397_SET_FALCON19 0x234c +#define NVC397_SET_FALCON19_V 31:0 + +#define NVC397_SET_FALCON20 0x2350 +#define NVC397_SET_FALCON20_V 31:0 + +#define NVC397_SET_FALCON21 0x2354 +#define NVC397_SET_FALCON21_V 31:0 + +#define NVC397_SET_FALCON22 0x2358 +#define NVC397_SET_FALCON22_V 31:0 + +#define NVC397_SET_FALCON23 0x235c +#define NVC397_SET_FALCON23_V 31:0 + +#define NVC397_SET_FALCON24 0x2360 +#define NVC397_SET_FALCON24_V 31:0 + +#define NVC397_SET_FALCON25 0x2364 +#define NVC397_SET_FALCON25_V 31:0 + +#define NVC397_SET_FALCON26 0x2368 +#define NVC397_SET_FALCON26_V 31:0 + +#define NVC397_SET_FALCON27 0x236c +#define NVC397_SET_FALCON27_V 31:0 + +#define NVC397_SET_FALCON28 0x2370 +#define NVC397_SET_FALCON28_V 31:0 + +#define NVC397_SET_FALCON29 0x2374 +#define NVC397_SET_FALCON29_V 31:0 + +#define NVC397_SET_FALCON30 0x2378 +#define NVC397_SET_FALCON30_V 31:0 + +#define NVC397_SET_FALCON31 0x237c +#define NVC397_SET_FALCON31_V 31:0 + +#define NVC397_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC397_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC397_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC397_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC397_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC397_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC397_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC397_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC397_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC397_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC397_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC397_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC397_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC397_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC397_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC397_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC397_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC397_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC397_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC397_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC397_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC397_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC397_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC397_SET_TRAP_HANDLER_A 0x25f8 +#define NVC397_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC397_SET_TRAP_HANDLER_B 0x25fc +#define NVC397_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC397_SET_COLOR_CLAMP 0x2600 +#define NVC397_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC397_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC397_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BINDLESS_TEXTURE 0x2608 +#define NVC397_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVC397_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC397_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC397_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC397_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC397_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC397_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC397_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC397_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC397_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC397_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC397_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC397_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC397_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC397_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC397_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC397_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC397_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC397_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC397_CALL_MME_MACRO_V 31:0 + +#define NVC397_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC397_CALL_MME_DATA_V 31:0 + +#endif /* _cl_volta_a_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc3b0.h b/userspace/sdks/nv570/nvidia/inc/class/clc3b0.h new file mode 100644 index 0000000..5ccaedd --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc3b0.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _clc3b0_h_ +#define _clc3b0_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC3B0_VIDEO_DECODER (0x0000C3B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc3b0_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc3b5.h b/userspace/sdks/nv570/nvidia/inc/class/clc3b5.h new file mode 100644 index 0000000..74ee1b7 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc3b5.h @@ -0,0 +1,278 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clc3b5_h_ +#define _clc3b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define VOLTA_DMA_COPY_A (0x0000C3B5) + +#define NVC3B5_NOP (0x00000100) +#define NVC3B5_NOP_PARAMETER 31:0 +#define NVC3B5_PM_TRIGGER (0x00000140) +#define NVC3B5_PM_TRIGGER_V 31:0 +#define NVC3B5_SET_SEMAPHORE_A (0x00000240) +#define NVC3B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC3B5_SET_SEMAPHORE_B (0x00000244) +#define NVC3B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC3B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC3B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC3B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC3B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC3B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC3B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC3B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC3B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC3B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC3B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC3B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC3B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC3B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC3B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC3B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC3B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC3B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC3B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC3B5_SET_SRC_PHYS_MODE_BASIC_KIND 5:2 +#define NVC3B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC3B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC3B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC3B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC3B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC3B5_SET_DST_PHYS_MODE_BASIC_KIND 5:2 +#define NVC3B5_LAUNCH_DMA (0x00000300) +#define NVC3B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC3B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC3B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC3B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC3B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC3B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC3B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC3B5_LAUNCH_DMA_FLUSH_TYPE 25:25 +#define NVC3B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000) +#define NVC3B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC3B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC3B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC3B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC3B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC3B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC3B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC3B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC3B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC3B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC3B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC3B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC3B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC3B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC3B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC3B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC3B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC3B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC3B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC3B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC3B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC3B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC3B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC3B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC3B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC3B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC3B5_LAUNCH_DMA_SRC_BYPASS_L2 20:20 +#define NVC3B5_LAUNCH_DMA_SRC_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC3B5_LAUNCH_DMA_SRC_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC3B5_LAUNCH_DMA_DST_BYPASS_L2 21:21 +#define NVC3B5_LAUNCH_DMA_DST_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC3B5_LAUNCH_DMA_DST_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC3B5_LAUNCH_DMA_VPRMODE 23:22 +#define NVC3B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVC3B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC3B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC3B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 +#define NVC3B5_OFFSET_IN_UPPER (0x00000400) +#define NVC3B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC3B5_OFFSET_IN_LOWER (0x00000404) +#define NVC3B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC3B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC3B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC3B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC3B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC3B5_PITCH_IN (0x00000410) +#define NVC3B5_PITCH_IN_VALUE 31:0 +#define NVC3B5_PITCH_OUT (0x00000414) +#define NVC3B5_PITCH_OUT_VALUE 31:0 +#define NVC3B5_LINE_LENGTH_IN (0x00000418) +#define NVC3B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC3B5_LINE_COUNT (0x0000041C) +#define NVC3B5_LINE_COUNT_VALUE 31:0 +#define NVC3B5_SET_REMAP_CONST_A (0x00000700) +#define NVC3B5_SET_REMAP_CONST_A_V 31:0 +#define NVC3B5_SET_REMAP_CONST_B (0x00000704) +#define NVC3B5_SET_REMAP_CONST_B_V 31:0 +#define NVC3B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC3B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC3B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC3B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC3B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC3B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC3B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC3B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC3B5_SET_DST_WIDTH (0x00000710) +#define NVC3B5_SET_DST_WIDTH_V 31:0 +#define NVC3B5_SET_DST_HEIGHT (0x00000714) +#define NVC3B5_SET_DST_HEIGHT_V 31:0 +#define NVC3B5_SET_DST_DEPTH (0x00000718) +#define NVC3B5_SET_DST_DEPTH_V 31:0 +#define NVC3B5_SET_DST_LAYER (0x0000071C) +#define NVC3B5_SET_DST_LAYER_V 31:0 +#define NVC3B5_SET_DST_ORIGIN (0x00000720) +#define NVC3B5_SET_DST_ORIGIN_X 15:0 +#define NVC3B5_SET_DST_ORIGIN_Y 31:16 +#define NVC3B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC3B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC3B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC3B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC3B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC3B5_SET_SRC_WIDTH (0x0000072C) +#define NVC3B5_SET_SRC_WIDTH_V 31:0 +#define NVC3B5_SET_SRC_HEIGHT (0x00000730) +#define NVC3B5_SET_SRC_HEIGHT_V 31:0 +#define NVC3B5_SET_SRC_DEPTH (0x00000734) +#define NVC3B5_SET_SRC_DEPTH_V 31:0 +#define NVC3B5_SET_SRC_LAYER (0x00000738) +#define NVC3B5_SET_SRC_LAYER_V 31:0 +#define NVC3B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC3B5_SET_SRC_ORIGIN_X 15:0 +#define NVC3B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC3B5_SRC_ORIGIN_X (0x00000744) +#define NVC3B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC3B5_SRC_ORIGIN_Y (0x00000748) +#define NVC3B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC3B5_DST_ORIGIN_X (0x0000074C) +#define NVC3B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC3B5_DST_ORIGIN_Y (0x00000750) +#define NVC3B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC3B5_PM_TRIGGER_END (0x00001114) +#define NVC3B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc3b5_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc3b5sw.h b/userspace/sdks/nv570/nvidia/inc/class/clc3b5sw.h new file mode 100644 index 0000000..b913984 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc3b5sw.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc3b5sw.finn +// + + + +// +// Using VERSION_0 will cause the API to interpret +// engineType as a CE engine instance. This allows +// for backward compatibility with 85B5sw and 90B5sw. +// +#define NVC3B5_ALLOCATION_PARAMETERS_VERSION_0 0 + +// +// Using VERSION_1 will cause the API to interpret +// engineType as an NV2080_ENGINE_TYPE ordinal. +// +#define NVC3B5_ALLOCATION_PARAMETERS_VERSION_1 1 + +#define NVC3B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc3b5U) + +typedef struct NVC3B5_ALLOCATION_PARAMETERS { + NvU32 version; + NvU32 engineType; +} NVC3B5_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc3b7.h b/userspace/sdks/nv570/nvidia/inc/class/clc3b7.h new file mode 100644 index 0000000..0a313b8 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc3b7.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clc3b7_h +#define clc3b7_h + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC3B7_VIDEO_ENCODER (0x0000C3B7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc3b7_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc3c0.h b/userspace/sdks/nv570/nvidia/inc/class/clc3c0.h new file mode 100644 index 0000000..76b4566 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc3c0.h @@ -0,0 +1,703 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_volta_compute_a_h_ +#define _cl_volta_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl volta_compute_a */ + +#include "nvtypes.h" + +#define VOLTA_COMPUTE_A 0xC3C0 + +#define NVC3C0_SET_OBJECT 0x0000 +#define NVC3C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC3C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC3C0_NO_OPERATION 0x0100 +#define NVC3C0_NO_OPERATION_V 31:0 + +#define NVC3C0_SET_NOTIFY_A 0x0104 +#define NVC3C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC3C0_SET_NOTIFY_B 0x0108 +#define NVC3C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC3C0_NOTIFY 0x010c +#define NVC3C0_NOTIFY_TYPE 31:0 +#define NVC3C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC3C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC3C0_WAIT_FOR_IDLE 0x0110 +#define NVC3C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC3C0_SEND_GO_IDLE 0x013c +#define NVC3C0_SEND_GO_IDLE_V 31:0 + +#define NVC3C0_PM_TRIGGER 0x0140 +#define NVC3C0_PM_TRIGGER_V 31:0 + +#define NVC3C0_PM_TRIGGER_WFI 0x0144 +#define NVC3C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC3C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC3C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC3C0_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC3C0_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC3C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC3C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC3C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC3C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC3C0_LINE_LENGTH_IN 0x0180 +#define NVC3C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC3C0_LINE_COUNT 0x0184 +#define NVC3C0_LINE_COUNT_VALUE 31:0 + +#define NVC3C0_OFFSET_OUT_UPPER 0x0188 +#define NVC3C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC3C0_OFFSET_OUT 0x018c +#define NVC3C0_OFFSET_OUT_VALUE 31:0 + +#define NVC3C0_PITCH_OUT 0x0190 +#define NVC3C0_PITCH_OUT_VALUE 31:0 + +#define NVC3C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC3C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC3C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC3C0_SET_DST_WIDTH 0x0198 +#define NVC3C0_SET_DST_WIDTH_V 31:0 + +#define NVC3C0_SET_DST_HEIGHT 0x019c +#define NVC3C0_SET_DST_HEIGHT_V 31:0 + +#define NVC3C0_SET_DST_DEPTH 0x01a0 +#define NVC3C0_SET_DST_DEPTH_V 31:0 + +#define NVC3C0_SET_DST_LAYER 0x01a4 +#define NVC3C0_SET_DST_LAYER_V 31:0 + +#define NVC3C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC3C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC3C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC3C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC3C0_LAUNCH_DMA 0x01b0 +#define NVC3C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC3C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC3C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC3C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC3C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC3C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC3C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC3C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC3C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC3C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC3C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC3C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC3C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC3C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC3C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC3C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC3C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC3C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC3C0_LOAD_INLINE_DATA 0x01b4 +#define NVC3C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC3C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC3C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC3C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC3C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC3C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC3C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC3C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC3C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC3C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC3C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC3C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC3C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC3C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC3C0_PERFMON_TRANSFER 0x0210 +#define NVC3C0_PERFMON_TRANSFER_V 31:0 + +#define NVC3C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC3C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC3C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC3C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC3C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC3C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC3C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC3C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC3C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC3C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC3C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC3C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC3C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC3C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC3C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC3C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC3C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC3C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC3C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC3C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC3C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC3C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC3C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC3C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC3C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC3C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC3C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC3C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC3C0_SET_SCG_CONTROL 0x0270 +#define NVC3C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 +#define NVC3C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 +#define NVC3C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 +#define NVC3C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 +#define NVC3C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 + +#define NVC3C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC3C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC3C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC3C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC3C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC3C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC3C0_SET_QMD_VERSION 0x0288 +#define NVC3C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC3C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC3C0_CHECK_QMD_VERSION 0x0290 +#define NVC3C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC3C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC3C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC3C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC3C0_SCG_HYSTERESIS_CONTROL 0x02a8 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 + +#define NVC3C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC3C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC3C0_SEND_PCAS_A 0x02b4 +#define NVC3C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC3C0_SEND_PCAS_B 0x02b8 +#define NVC3C0_SEND_PCAS_B_FROM 23:0 +#define NVC3C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC3C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC3C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC3C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC3C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC3C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC3C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC3C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC3C0_SET_SKED_CACHE_CONTROL 0x02cc +#define NVC3C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID 0:0 +#define NVC3C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE 0x00000000 +#define NVC3C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE 0x00000001 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC3C0_SET_SPA_VERSION 0x0310 +#define NVC3C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC3C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC3C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC3C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC3C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC3C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC3C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC3C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC3C0_SET_FALCON00 0x0500 +#define NVC3C0_SET_FALCON00_V 31:0 + +#define NVC3C0_SET_FALCON01 0x0504 +#define NVC3C0_SET_FALCON01_V 31:0 + +#define NVC3C0_SET_FALCON02 0x0508 +#define NVC3C0_SET_FALCON02_V 31:0 + +#define NVC3C0_SET_FALCON03 0x050c +#define NVC3C0_SET_FALCON03_V 31:0 + +#define NVC3C0_SET_FALCON04 0x0510 +#define NVC3C0_SET_FALCON04_V 31:0 + +#define NVC3C0_SET_FALCON05 0x0514 +#define NVC3C0_SET_FALCON05_V 31:0 + +#define NVC3C0_SET_FALCON06 0x0518 +#define NVC3C0_SET_FALCON06_V 31:0 + +#define NVC3C0_SET_FALCON07 0x051c +#define NVC3C0_SET_FALCON07_V 31:0 + +#define NVC3C0_SET_FALCON08 0x0520 +#define NVC3C0_SET_FALCON08_V 31:0 + +#define NVC3C0_SET_FALCON09 0x0524 +#define NVC3C0_SET_FALCON09_V 31:0 + +#define NVC3C0_SET_FALCON10 0x0528 +#define NVC3C0_SET_FALCON10_V 31:0 + +#define NVC3C0_SET_FALCON11 0x052c +#define NVC3C0_SET_FALCON11_V 31:0 + +#define NVC3C0_SET_FALCON12 0x0530 +#define NVC3C0_SET_FALCON12_V 31:0 + +#define NVC3C0_SET_FALCON13 0x0534 +#define NVC3C0_SET_FALCON13_V 31:0 + +#define NVC3C0_SET_FALCON14 0x0538 +#define NVC3C0_SET_FALCON14_V 31:0 + +#define NVC3C0_SET_FALCON15 0x053c +#define NVC3C0_SET_FALCON15_V 31:0 + +#define NVC3C0_SET_FALCON16 0x0540 +#define NVC3C0_SET_FALCON16_V 31:0 + +#define NVC3C0_SET_FALCON17 0x0544 +#define NVC3C0_SET_FALCON17_V 31:0 + +#define NVC3C0_SET_FALCON18 0x0548 +#define NVC3C0_SET_FALCON18_V 31:0 + +#define NVC3C0_SET_FALCON19 0x054c +#define NVC3C0_SET_FALCON19_V 31:0 + +#define NVC3C0_SET_FALCON20 0x0550 +#define NVC3C0_SET_FALCON20_V 31:0 + +#define NVC3C0_SET_FALCON21 0x0554 +#define NVC3C0_SET_FALCON21_V 31:0 + +#define NVC3C0_SET_FALCON22 0x0558 +#define NVC3C0_SET_FALCON22_V 31:0 + +#define NVC3C0_SET_FALCON23 0x055c +#define NVC3C0_SET_FALCON23_V 31:0 + +#define NVC3C0_SET_FALCON24 0x0560 +#define NVC3C0_SET_FALCON24_V 31:0 + +#define NVC3C0_SET_FALCON25 0x0564 +#define NVC3C0_SET_FALCON25_V 31:0 + +#define NVC3C0_SET_FALCON26 0x0568 +#define NVC3C0_SET_FALCON26_V 31:0 + +#define NVC3C0_SET_FALCON27 0x056c +#define NVC3C0_SET_FALCON27_V 31:0 + +#define NVC3C0_SET_FALCON28 0x0570 +#define NVC3C0_SET_FALCON28_V 31:0 + +#define NVC3C0_SET_FALCON29 0x0574 +#define NVC3C0_SET_FALCON29_V 31:0 + +#define NVC3C0_SET_FALCON30 0x0578 +#define NVC3C0_SET_FALCON30_V 31:0 + +#define NVC3C0_SET_FALCON31 0x057c +#define NVC3C0_SET_FALCON31_V 31:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC3C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC3C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC3C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC3C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC3C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC3C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC3C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC3C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC3C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC3C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC3C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC3C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC3C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC3C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC3C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC3C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC3C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC3C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC3C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC3C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC3C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC3C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC3C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC3C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC3C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC3C0_PIPE_NOP 0x1a2c +#define NVC3C0_PIPE_NOP_V 31:0 + +#define NVC3C0_SET_SPARE00 0x1a30 +#define NVC3C0_SET_SPARE00_V 31:0 + +#define NVC3C0_SET_SPARE01 0x1a34 +#define NVC3C0_SET_SPARE01_V 31:0 + +#define NVC3C0_SET_SPARE02 0x1a38 +#define NVC3C0_SET_SPARE02_V 31:0 + +#define NVC3C0_SET_SPARE03 0x1a3c +#define NVC3C0_SET_SPARE03_V 31:0 + +#define NVC3C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC3C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC3C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC3C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC3C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC3C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC3C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC3C0_SET_TRAP_HANDLER_A 0x25f8 +#define NVC3C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC3C0_SET_TRAP_HANDLER_B 0x25fc +#define NVC3C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC3C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC3C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC3C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC3C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC3C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC3C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC3C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC3C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC3C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC3C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC3C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC3C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_volta_compute_a_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc461.h b/userspace/sdks/nv570/nvidia/inc/class/clc461.h new file mode 100644 index 0000000..0c0378f --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc461.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc461_h_ +#define _clc461_h_ + +#define TURING_USERMODE_A (0xc461) + +#endif // _clc461_h_ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc46f.h b/userspace/sdks/nv570/nvidia/inc/class/clc46f.h new file mode 100644 index 0000000..fb1c594 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc46f.h @@ -0,0 +1,365 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc46f_h_ +#define _clc46f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class TURING_CHANNEL_GPFIFO */ +/* + * Documentation for TURING_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + * Note there is no .mfs file for this class. + */ +#define TURING_CHANNEL_GPFIFO_A (0x0000C46F) + +#define NVC46F_TYPEDEF TURING_CHANNELChannelGPFifoA + +/* dma flow control data structure */ +typedef volatile struct Nvc46fControl_struct { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} Nvc46fControl, TuringAControlGPFifo; + +/* fields and values */ +#define NVC46F_NUMBER_OF_SUBCHANNELS (8) +#define NVC46F_SET_OBJECT (0x00000000) +#define NVC46F_SET_OBJECT_NVCLASS 15:0 +#define NVC46F_SET_OBJECT_ENGINE 20:16 +#define NVC46F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVC46F_ILLEGAL (0x00000004) +#define NVC46F_ILLEGAL_HANDLE 31:0 +#define NVC46F_NOP (0x00000008) +#define NVC46F_NOP_HANDLE 31:0 +#define NVC46F_SEMAPHOREA (0x00000010) +#define NVC46F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVC46F_SEMAPHOREB (0x00000014) +#define NVC46F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVC46F_SEMAPHOREC (0x00000018) +#define NVC46F_SEMAPHOREC_PAYLOAD 31:0 +#define NVC46F_SEMAPHORED (0x0000001C) +#define NVC46F_SEMAPHORED_OPERATION 4:0 +#define NVC46F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVC46F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVC46F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVC46F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVC46F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 +#define NVC46F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVC46F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVC46F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVC46F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVC46F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVC46F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVC46F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVC46F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVC46F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVC46F_SEMAPHORED_REDUCTION 30:27 +#define NVC46F_SEMAPHORED_REDUCTION_MIN 0x00000000 +#define NVC46F_SEMAPHORED_REDUCTION_MAX 0x00000001 +#define NVC46F_SEMAPHORED_REDUCTION_XOR 0x00000002 +#define NVC46F_SEMAPHORED_REDUCTION_AND 0x00000003 +#define NVC46F_SEMAPHORED_REDUCTION_OR 0x00000004 +#define NVC46F_SEMAPHORED_REDUCTION_ADD 0x00000005 +#define NVC46F_SEMAPHORED_REDUCTION_INC 0x00000006 +#define NVC46F_SEMAPHORED_REDUCTION_DEC 0x00000007 +#define NVC46F_SEMAPHORED_FORMAT 31:31 +#define NVC46F_SEMAPHORED_FORMAT_SIGNED 0x00000000 +#define NVC46F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 +#define NVC46F_NON_STALL_INTERRUPT (0x00000020) +#define NVC46F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVC46F_FB_FLUSH (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR +#define NVC46F_FB_FLUSH_HANDLE 31:0 +// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for +// specifying the page address for a targeted TLB invalidate and the uTLB for +// a targeted REPLAY_CANCEL for UVM. +// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly +// rearranged fields. +#define NVC46F_MEM_OP_A (0x00000028) +#define NVC46F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC46F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type +#define NVC46F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC46F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID 6:0 // only relevant for REPLAY_CANCEL_VA_GLOBAL +#define NVC46F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11 +#define NVC46F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001 +#define NVC46F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000 +#define NVC46F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12 +#define NVC46F_MEM_OP_B (0x0000002c) +#define NVC46F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0 +#define NVC46F_MEM_OP_C (0x00000030) +#define NVC46F_MEM_OP_C_MEMBAR_TYPE 2:0 +#define NVC46F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000 +#define NVC46F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE 9:7 //only relevant for REPLAY_CANCEL_VA_GLOBAL +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ 0 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE 1 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG 2 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD 3 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK 4 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL 5 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC 6 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL 7 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE +#define NVC46F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG 19:0 +// MEM_OP_D MUST be preceded by MEM_OPs A-C. +#define NVC46F_MEM_OP_D (0x00000034) +#define NVC46F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE +#define NVC46F_MEM_OP_D_OPERATION 31:27 +#define NVC46F_MEM_OP_D_OPERATION_MEMBAR 0x00000005 +#define NVC46F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVC46F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a +#define NVC46F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NVC46F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +// CLEAN_LINES is an alias for Tegra/GPU IP usage +#define NVC46F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e +#define NVC46F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVC46F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVC46F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015 +#define NVC46F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR 0x00000016 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE 1:0 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC 0x00000000 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC 0x00000001 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL 0x00000002 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED 0x00000003 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE 2:2 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC 0x00000000 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC 0x00000001 +#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK 6:3 +#define NVC46F_SET_REFERENCE (0x00000050) +#define NVC46F_SET_REFERENCE_COUNT 31:0 +#define NVC46F_SEM_ADDR_LO (0x0000005c) +#define NVC46F_SEM_ADDR_LO_OFFSET 31:2 +#define NVC46F_SEM_ADDR_HI (0x00000060) +#define NVC46F_SEM_ADDR_HI_OFFSET 7:0 +#define NVC46F_SEM_PAYLOAD_LO (0x00000064) +#define NVC46F_SEM_PAYLOAD_LO_PAYLOAD 31:0 +#define NVC46F_SEM_PAYLOAD_HI (0x00000068) +#define NVC46F_SEM_PAYLOAD_HI_PAYLOAD 31:0 +#define NVC46F_SEM_EXECUTE (0x0000006c) +#define NVC46F_SEM_EXECUTE_OPERATION 2:0 +#define NVC46F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000 +#define NVC46F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001 +#define NVC46F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ 0x00000002 +#define NVC46F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003 +#define NVC46F_SEM_EXECUTE_OPERATION_ACQ_AND 0x00000004 +#define NVC46F_SEM_EXECUTE_OPERATION_ACQ_NOR 0x00000005 +#define NVC46F_SEM_EXECUTE_OPERATION_REDUCTION 0x00000006 +#define NVC46F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12 +#define NVC46F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS 0x00000000 +#define NVC46F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001 +#define NVC46F_SEM_EXECUTE_RELEASE_WFI 20:20 +#define NVC46F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000 +#define NVC46F_SEM_EXECUTE_RELEASE_WFI_EN 0x00000001 +#define NVC46F_SEM_EXECUTE_PAYLOAD_SIZE 24:24 +#define NVC46F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000 +#define NVC46F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT 0x00000001 +#define NVC46F_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25 +#define NVC46F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000 +#define NVC46F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001 +#define NVC46F_SEM_EXECUTE_REDUCTION 30:27 +#define NVC46F_SEM_EXECUTE_REDUCTION_IMIN 0x00000000 +#define NVC46F_SEM_EXECUTE_REDUCTION_IMAX 0x00000001 +#define NVC46F_SEM_EXECUTE_REDUCTION_IXOR 0x00000002 +#define NVC46F_SEM_EXECUTE_REDUCTION_IAND 0x00000003 +#define NVC46F_SEM_EXECUTE_REDUCTION_IOR 0x00000004 +#define NVC46F_SEM_EXECUTE_REDUCTION_IADD 0x00000005 +#define NVC46F_SEM_EXECUTE_REDUCTION_INC 0x00000006 +#define NVC46F_SEM_EXECUTE_REDUCTION_DEC 0x00000007 +#define NVC46F_SEM_EXECUTE_REDUCTION_FORMAT 31:31 +#define NVC46F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000000 +#define NVC46F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000001 +#define NVC46F_WFI (0x00000078) +#define NVC46F_WFI_SCOPE 0:0 +#define NVC46F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000 +#define NVC46F_WFI_SCOPE_CURRENT_VEID 0x00000000 +#define NVC46F_WFI_SCOPE_ALL 0x00000001 +#define NVC46F_CRC_CHECK (0x0000007c) +#define NVC46F_CRC_CHECK_VALUE 31:0 +#define NVC46F_YIELD (0x00000080) +#define NVC46F_YIELD_OP 1:0 +#define NVC46F_YIELD_OP_NOP 0x00000000 +#define NVC46F_YIELD_OP_RUNLIST_TIMESLICE 0x00000002 +#define NVC46F_YIELD_OP_TSG 0x00000003 +#define NVC46F_CLEAR_FAULTED (0x00000084) +// Note: RM provides the HANDLE as an opaque value; the internal detail fields +// are intentionally not exposed to the driver through these defines. +#define NVC46F_CLEAR_FAULTED_HANDLE 30:0 +#define NVC46F_CLEAR_FAULTED_TYPE 31:31 +#define NVC46F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED 0x00000000 +#define NVC46F_CLEAR_FAULTED_TYPE_ENG_FAULTED 0x00000001 + + +/* GPFIFO entry format */ +#define NVC46F_GP_ENTRY__SIZE 8 +#define NVC46F_GP_ENTRY0_FETCH 0:0 +#define NVC46F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVC46F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVC46F_GP_ENTRY0_GET 31:2 +#define NVC46F_GP_ENTRY0_OPERAND 31:0 +#define NVC46F_GP_ENTRY1_GET_HI 7:0 +#define NVC46F_GP_ENTRY1_LEVEL 9:9 +#define NVC46F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVC46F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVC46F_GP_ENTRY1_LENGTH 30:10 +#define NVC46F_GP_ENTRY1_SYNC 31:31 +#define NVC46F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVC46F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVC46F_GP_ENTRY1_OPCODE 7:0 +#define NVC46F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVC46F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVC46F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVC46F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVC46F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVC46F_DMA_METHOD_ADDRESS 11:0 +#define NVC46F_DMA_SUBDEVICE_MASK 15:4 +#define NVC46F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVC46F_DMA_TERT_OP 17:16 +#define NVC46F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVC46F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVC46F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVC46F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVC46F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVC46F_DMA_METHOD_COUNT_OLD 28:18 +#define NVC46F_DMA_METHOD_COUNT 28:16 +#define NVC46F_DMA_IMMD_DATA 28:16 +#define NVC46F_DMA_SEC_OP 31:29 +#define NVC46F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVC46F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVC46F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVC46F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVC46F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVC46F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVC46F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVC46F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVC46F_DMA_INCR_ADDRESS 11:0 +#define NVC46F_DMA_INCR_SUBCHANNEL 15:13 +#define NVC46F_DMA_INCR_COUNT 28:16 +#define NVC46F_DMA_INCR_OPCODE 31:29 +#define NVC46F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVC46F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVC46F_DMA_NONINCR_ADDRESS 11:0 +#define NVC46F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVC46F_DMA_NONINCR_COUNT 28:16 +#define NVC46F_DMA_NONINCR_OPCODE 31:29 +#define NVC46F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVC46F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVC46F_DMA_ONEINCR_ADDRESS 11:0 +#define NVC46F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVC46F_DMA_ONEINCR_COUNT 28:16 +#define NVC46F_DMA_ONEINCR_OPCODE 31:29 +#define NVC46F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVC46F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVC46F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVC46F_DMA_IMMD_ADDRESS 11:0 +#define NVC46F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVC46F_DMA_IMMD_DATA 28:16 +#define NVC46F_DMA_IMMD_OPCODE 31:29 +#define NVC46F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVC46F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVC46F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC46F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVC46F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVC46F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC46F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVC46F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC46F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVC46F_DMA_ENDSEG_OPCODE 31:29 +#define NVC46F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVC46F_DMA_ADDRESS 12:2 +#define NVC46F_DMA_SUBCH 15:13 +#define NVC46F_DMA_OPCODE3 17:16 +#define NVC46F_DMA_OPCODE3_NONE (0x00000000) +#define NVC46F_DMA_COUNT 28:18 +#define NVC46F_DMA_OPCODE 31:29 +#define NVC46F_DMA_OPCODE_METHOD (0x00000000) +#define NVC46F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVC46F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc46f_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc46fsw.h b/userspace/sdks/nv570/nvidia/inc/class/clc46fsw.h new file mode 100644 index 0000000..7438195 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc46fsw.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* This file is *not* auto-generated. */ + +#ifndef _clc46f_sw_h_ +#define _clc46f_sw_h_ + +#define NVC46F_NOTIFIERS_RC (0) +#define NVC46F_NOTIFIERS_REFCNT (1) +#define NVC46F_NOTIFIERS_NONSTALL (2) +#define NVC46F_NOTIFIERS_EVENTBUFFER (3) +#define NVC46F_NOTIFIERS_IDLECHANNEL (4) +#define NVC46F_NOTIFIERS_ENDCTX (5) +#define NVC46F_NOTIFIERS_SW (6) +#define NVC46F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVC46F_NOTIFIERS_REPLAYABLE_FAULT (8) +#define NVC46F_NOTIFIERS_MAXCOUNT (9) + +/* NvNotification[] fields and values */ +#define NVC46F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVC46F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _clc46f_sw_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc4b0.h b/userspace/sdks/nv570/nvidia/inc/class/clc4b0.h new file mode 100644 index 0000000..4b7d335 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc4b0.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clc4b0_h_ +#define clc4b0_h_ + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC4B0_VIDEO_DECODER (0x0000C4B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc4b0_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc4b7.h b/userspace/sdks/nv570/nvidia/inc/class/clc4b7.h new file mode 100644 index 0000000..27f3983 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc4b7.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clc4b7_h_ +#define clc4b7_h_ + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC4B7_VIDEO_ENCODER (0x0000C4B7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc4b7_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc4c0.h b/userspace/sdks/nv570/nvidia/inc/class/clc4c0.h new file mode 100644 index 0000000..f96026c --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc4c0.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_volta_compute_b_h_ +#define _cl_volta_compute_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl volta_compute_b */ + +#include "nvtypes.h" + +#define VOLTA_COMPUTE_B 0xC4C0 + +#endif /* _cl_volta_compute_b_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc4d1.h b/userspace/sdks/nv570/nvidia/inc/class/clc4d1.h new file mode 100644 index 0000000..196b034 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc4d1.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "nvtypes.h" + +#ifndef _clc4d1_h_ +#define _clc4d1_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC4D1_VIDEO_NVJPG (0x0000C4D1) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc4d1_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc561.h b/userspace/sdks/nv570/nvidia/inc/class/clc561.h new file mode 100644 index 0000000..83a9339 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc561.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc561_h_ +#define _clc561_h_ + +#define AMPERE_USERMODE_A (0xc561) + +#endif // _clc561_h_ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc56f.h b/userspace/sdks/nv570/nvidia/inc/class/clc56f.h new file mode 100644 index 0000000..bc8b675 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc56f.h @@ -0,0 +1,367 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc56f_h_ +#define _clc56f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class AMPERE_CHANNEL_GPFIFO */ +/* + * Documentation for AMPERE_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + * Note there is no .mfs file for this class. + */ +#define AMPERE_CHANNEL_GPFIFO_A (0x0000C56F) + +#define NVC56F_TYPEDEF AMPERE_CHANNELChannelGPFifoA + +/* dma flow control data structure */ +typedef volatile struct Nvc56fControl_struct { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} Nvc56fControl, AmpereAControlGPFifo; + +/* fields and values */ +#define NVC56F_NUMBER_OF_SUBCHANNELS (8) +#define NVC56F_SET_OBJECT (0x00000000) +#define NVC56F_SET_OBJECT_NVCLASS 15:0 +#define NVC56F_SET_OBJECT_ENGINE 20:16 +#define NVC56F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVC56F_ILLEGAL (0x00000004) +#define NVC56F_ILLEGAL_HANDLE 31:0 +#define NVC56F_NOP (0x00000008) +#define NVC56F_NOP_HANDLE 31:0 +#define NVC56F_SEMAPHOREA (0x00000010) +#define NVC56F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVC56F_SEMAPHOREB (0x00000014) +#define NVC56F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVC56F_SEMAPHOREC (0x00000018) +#define NVC56F_SEMAPHOREC_PAYLOAD 31:0 +#define NVC56F_SEMAPHORED (0x0000001C) +#define NVC56F_SEMAPHORED_OPERATION 4:0 +#define NVC56F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVC56F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVC56F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVC56F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVC56F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 +#define NVC56F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVC56F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVC56F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVC56F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVC56F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVC56F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVC56F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVC56F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVC56F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVC56F_SEMAPHORED_REDUCTION 30:27 +#define NVC56F_SEMAPHORED_REDUCTION_MIN 0x00000000 +#define NVC56F_SEMAPHORED_REDUCTION_MAX 0x00000001 +#define NVC56F_SEMAPHORED_REDUCTION_XOR 0x00000002 +#define NVC56F_SEMAPHORED_REDUCTION_AND 0x00000003 +#define NVC56F_SEMAPHORED_REDUCTION_OR 0x00000004 +#define NVC56F_SEMAPHORED_REDUCTION_ADD 0x00000005 +#define NVC56F_SEMAPHORED_REDUCTION_INC 0x00000006 +#define NVC56F_SEMAPHORED_REDUCTION_DEC 0x00000007 +#define NVC56F_SEMAPHORED_FORMAT 31:31 +#define NVC56F_SEMAPHORED_FORMAT_SIGNED 0x00000000 +#define NVC56F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 +#define NVC56F_NON_STALL_INTERRUPT (0x00000020) +#define NVC56F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVC56F_FB_FLUSH (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR +#define NVC56F_FB_FLUSH_HANDLE 31:0 +// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for +// specifying the page address for a targeted TLB invalidate and the uTLB for +// a targeted REPLAY_CANCEL for UVM. +// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly +// rearranged fields. +#define NVC56F_MEM_OP_A (0x00000028) +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE 7:6 // only relevant for invalidates with NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE for invalidating link TLB only, or non-link TLB only or all TLBs +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS 0 +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS 1 +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS 2 +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD 3 +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID 6:0 // only relevant for REPLAY_CANCEL_VA_GLOBAL +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11 +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001 +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000 +#define NVC56F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12 +#define NVC56F_MEM_OP_B (0x0000002c) +#define NVC56F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0 +#define NVC56F_MEM_OP_C (0x00000030) +#define NVC56F_MEM_OP_C_MEMBAR_TYPE 2:0 +#define NVC56F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000 +#define NVC56F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE 9:7 //only relevant for REPLAY_CANCEL_VA_GLOBAL +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ 0 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE 1 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG 2 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD 3 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK 4 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL 5 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC 6 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL 7 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE +#define NVC56F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG 19:0 +// MEM_OP_D MUST be preceded by MEM_OPs A-C. +#define NVC56F_MEM_OP_D (0x00000034) +#define NVC56F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE +#define NVC56F_MEM_OP_D_OPERATION 31:27 +#define NVC56F_MEM_OP_D_OPERATION_MEMBAR 0x00000005 +#define NVC56F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVC56F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a +#define NVC56F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NVC56F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +// CLEAN_LINES is an alias for Tegra/GPU IP usage +#define NVC56F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e +#define NVC56F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVC56F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVC56F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015 +#define NVC56F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR 0x00000016 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE 1:0 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC 0x00000000 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC 0x00000001 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL 0x00000002 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED 0x00000003 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE 2:2 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC 0x00000000 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC 0x00000001 +#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK 6:3 +#define NVC56F_SET_REFERENCE (0x00000050) +#define NVC56F_SET_REFERENCE_COUNT 31:0 +#define NVC56F_SEM_ADDR_LO (0x0000005c) +#define NVC56F_SEM_ADDR_LO_OFFSET 31:2 +#define NVC56F_SEM_ADDR_HI (0x00000060) +#define NVC56F_SEM_ADDR_HI_OFFSET 7:0 +#define NVC56F_SEM_PAYLOAD_LO (0x00000064) +#define NVC56F_SEM_PAYLOAD_LO_PAYLOAD 31:0 +#define NVC56F_SEM_PAYLOAD_HI (0x00000068) +#define NVC56F_SEM_PAYLOAD_HI_PAYLOAD 31:0 +#define NVC56F_SEM_EXECUTE (0x0000006c) +#define NVC56F_SEM_EXECUTE_OPERATION 2:0 +#define NVC56F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000 +#define NVC56F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001 +#define NVC56F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ 0x00000002 +#define NVC56F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003 +#define NVC56F_SEM_EXECUTE_OPERATION_ACQ_AND 0x00000004 +#define NVC56F_SEM_EXECUTE_OPERATION_ACQ_NOR 0x00000005 +#define NVC56F_SEM_EXECUTE_OPERATION_REDUCTION 0x00000006 +#define NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12 +#define NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS 0x00000000 +#define NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001 +#define NVC56F_SEM_EXECUTE_RELEASE_WFI 20:20 +#define NVC56F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000 +#define NVC56F_SEM_EXECUTE_RELEASE_WFI_EN 0x00000001 +#define NVC56F_SEM_EXECUTE_PAYLOAD_SIZE 24:24 +#define NVC56F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000 +#define NVC56F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT 0x00000001 +#define NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25 +#define NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000 +#define NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001 +#define NVC56F_SEM_EXECUTE_REDUCTION 30:27 +#define NVC56F_SEM_EXECUTE_REDUCTION_IMIN 0x00000000 +#define NVC56F_SEM_EXECUTE_REDUCTION_IMAX 0x00000001 +#define NVC56F_SEM_EXECUTE_REDUCTION_IXOR 0x00000002 +#define NVC56F_SEM_EXECUTE_REDUCTION_IAND 0x00000003 +#define NVC56F_SEM_EXECUTE_REDUCTION_IOR 0x00000004 +#define NVC56F_SEM_EXECUTE_REDUCTION_IADD 0x00000005 +#define NVC56F_SEM_EXECUTE_REDUCTION_INC 0x00000006 +#define NVC56F_SEM_EXECUTE_REDUCTION_DEC 0x00000007 +#define NVC56F_SEM_EXECUTE_REDUCTION_FORMAT 31:31 +#define NVC56F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000000 +#define NVC56F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000001 +#define NVC56F_WFI (0x00000078) +#define NVC56F_WFI_SCOPE 0:0 +#define NVC56F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000 +#define NVC56F_WFI_SCOPE_CURRENT_VEID 0x00000000 +#define NVC56F_WFI_SCOPE_ALL 0x00000001 +#define NVC56F_YIELD (0x00000080) +#define NVC56F_YIELD_OP 1:0 +#define NVC56F_YIELD_OP_NOP 0x00000000 +#define NVC56F_YIELD_OP_TSG 0x00000003 +#define NVC56F_CLEAR_FAULTED (0x00000084) +// Note: RM provides the HANDLE as an opaque value; the internal detail fields +// are intentionally not exposed to the driver through these defines. +#define NVC56F_CLEAR_FAULTED_HANDLE 30:0 +#define NVC56F_CLEAR_FAULTED_TYPE 31:31 +#define NVC56F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED 0x00000000 +#define NVC56F_CLEAR_FAULTED_TYPE_ENG_FAULTED 0x00000001 + + +/* GPFIFO entry format */ +#define NVC56F_GP_ENTRY__SIZE 8 +#define NVC56F_GP_ENTRY0_FETCH 0:0 +#define NVC56F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVC56F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVC56F_GP_ENTRY0_GET 31:2 +#define NVC56F_GP_ENTRY0_OPERAND 31:0 +#define NVC56F_GP_ENTRY1_GET_HI 7:0 +#define NVC56F_GP_ENTRY1_LEVEL 9:9 +#define NVC56F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVC56F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVC56F_GP_ENTRY1_LENGTH 30:10 +#define NVC56F_GP_ENTRY1_SYNC 31:31 +#define NVC56F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVC56F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVC56F_GP_ENTRY1_OPCODE 7:0 +#define NVC56F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVC56F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVC56F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVC56F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVC56F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVC56F_DMA_METHOD_ADDRESS 11:0 +#define NVC56F_DMA_SUBDEVICE_MASK 15:4 +#define NVC56F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVC56F_DMA_TERT_OP 17:16 +#define NVC56F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVC56F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVC56F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVC56F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVC56F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVC56F_DMA_METHOD_COUNT_OLD 28:18 +#define NVC56F_DMA_METHOD_COUNT 28:16 +#define NVC56F_DMA_IMMD_DATA 28:16 +#define NVC56F_DMA_SEC_OP 31:29 +#define NVC56F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVC56F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVC56F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVC56F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVC56F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVC56F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVC56F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVC56F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVC56F_DMA_INCR_ADDRESS 11:0 +#define NVC56F_DMA_INCR_SUBCHANNEL 15:13 +#define NVC56F_DMA_INCR_COUNT 28:16 +#define NVC56F_DMA_INCR_OPCODE 31:29 +#define NVC56F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVC56F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVC56F_DMA_NONINCR_ADDRESS 11:0 +#define NVC56F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVC56F_DMA_NONINCR_COUNT 28:16 +#define NVC56F_DMA_NONINCR_OPCODE 31:29 +#define NVC56F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVC56F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVC56F_DMA_ONEINCR_ADDRESS 11:0 +#define NVC56F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVC56F_DMA_ONEINCR_COUNT 28:16 +#define NVC56F_DMA_ONEINCR_OPCODE 31:29 +#define NVC56F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVC56F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVC56F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVC56F_DMA_IMMD_ADDRESS 11:0 +#define NVC56F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVC56F_DMA_IMMD_DATA 28:16 +#define NVC56F_DMA_IMMD_OPCODE 31:29 +#define NVC56F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVC56F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVC56F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC56F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVC56F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVC56F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC56F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVC56F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC56F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVC56F_DMA_ENDSEG_OPCODE 31:29 +#define NVC56F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVC56F_DMA_ADDRESS 12:2 +#define NVC56F_DMA_SUBCH 15:13 +#define NVC56F_DMA_OPCODE3 17:16 +#define NVC56F_DMA_OPCODE3_NONE (0x00000000) +#define NVC56F_DMA_COUNT 28:18 +#define NVC56F_DMA_OPCODE 31:29 +#define NVC56F_DMA_OPCODE_METHOD (0x00000000) +#define NVC56F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVC56F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc56f_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc56fsw.h b/userspace/sdks/nv570/nvidia/inc/class/clc56fsw.h new file mode 100644 index 0000000..13496be --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc56fsw.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* This file is *not* auto-generated. */ + +#ifndef _clc56f_sw_h_ +#define _clc56f_sw_h_ + +#define NVC56F_NOTIFIERS_RC (0) +#define NVC56F_NOTIFIERS_REFCNT (1) +#define NVC56F_NOTIFIERS_NONSTALL (2) +#define NVC56F_NOTIFIERS_EVENTBUFFER (3) +#define NVC56F_NOTIFIERS_IDLECHANNEL (4) +#define NVC56F_NOTIFIERS_ENDCTX (5) +#define NVC56F_NOTIFIERS_SW (6) +#define NVC56F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVC56F_NOTIFIERS_REPLAYABLE_FAULT (8) +#define NVC56F_NOTIFIERS_MAXCOUNT (9) + +/* NvNotification[] fields and values */ +#define NVC56F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVC56F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _clc56f_sw_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc570.h b/userspace/sdks/nv570/nvidia/inc/class/clc570.h new file mode 100644 index 0000000..0e562ab --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc570.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc570.finn +// + +#define NVC570_DISPLAY (0xc570U) /* finn: Evaluated from "NVC570_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NVC570_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc570U) + +typedef struct NVC570_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display +} NVC570_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc572.h b/userspace/sdks/nv570/nvidia/inc/class/clc572.h new file mode 100644 index 0000000..79dd9b3 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc572.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc572_h_ +#define _clc572_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define PHYSICAL_CHANNEL_GPFIFO (0x0000C572) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc572_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc573.h b/userspace/sdks/nv570/nvidia/inc/class/clc573.h new file mode 100644 index 0000000..a7bb1f4 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc573.h @@ -0,0 +1,598 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc573_h_ +#define _clc573_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC573_DISP_CAPABILITIES 0xC573 + +typedef volatile struct _clc573_tag0 { + NvU32 dispCapabilities[0x400]; +} _NvC573DispCapabilities,NvC573DispCapabilities_Map ; + + +#define NVC573_SYS_CAP 0x0 /* RW-4R */ +#define NVC573_SYS_CAP_HEAD0_EXISTS 0:0 /* RWIVF */ +#define NVC573_SYS_CAP_HEAD0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_HEAD1_EXISTS 1:1 /* RWIVF */ +#define NVC573_SYS_CAP_HEAD1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_HEAD2_EXISTS 2:2 /* RWIVF */ +#define NVC573_SYS_CAP_HEAD2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_HEAD3_EXISTS 3:3 /* RWIVF */ +#define NVC573_SYS_CAP_HEAD3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_HEAD4_EXISTS 4:4 /* RWIVF */ +#define NVC573_SYS_CAP_HEAD4_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_HEAD5_EXISTS 5:5 /* RWIVF */ +#define NVC573_SYS_CAP_HEAD5_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_HEAD6_EXISTS 6:6 /* RWIVF */ +#define NVC573_SYS_CAP_HEAD6_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_HEAD7_EXISTS 7:7 /* RWIVF */ +#define NVC573_SYS_CAP_HEAD7_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVC573_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */ +#define NVC573_SYS_CAP_HEAD_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR0_EXISTS 8:8 /* RWIVF */ +#define NVC573_SYS_CAP_SOR0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR1_EXISTS 9:9 /* RWIVF */ +#define NVC573_SYS_CAP_SOR1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR2_EXISTS 10:10 /* RWIVF */ +#define NVC573_SYS_CAP_SOR2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR3_EXISTS 11:11 /* RWIVF */ +#define NVC573_SYS_CAP_SOR3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR4_EXISTS 12:12 /* RWIVF */ +#define NVC573_SYS_CAP_SOR4_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR5_EXISTS 13:13 /* RWIVF */ +#define NVC573_SYS_CAP_SOR5_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR6_EXISTS 14:14 /* RWIVF */ +#define NVC573_SYS_CAP_SOR6_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR7_EXISTS 15:15 /* RWIVF */ +#define NVC573_SYS_CAP_SOR7_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* RWIVF */ +#define NVC573_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */ +#define NVC573_SYS_CAP_SOR_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB 0x4 /* RW-4R */ +#define NVC573_SYS_CAPB_WINDOW0_EXISTS 0:0 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW1_EXISTS 1:1 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW2_EXISTS 2:2 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW3_EXISTS 3:3 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW4_EXISTS 4:4 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW4_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW5_EXISTS 5:5 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW5_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW6_EXISTS 6:6 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW6_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW7_EXISTS 7:7 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW7_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW8_EXISTS 8:8 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW8_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW8_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW8_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW9_EXISTS 9:9 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW9_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW9_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW9_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW10_EXISTS 10:10 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW10_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW10_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW10_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW11_EXISTS 11:11 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW11_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW11_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW11_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW12_EXISTS 12:12 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW12_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW12_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW12_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW13_EXISTS 13:13 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW13_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW13_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW13_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW14_EXISTS 14:14 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW14_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW14_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW14_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW15_EXISTS 15:15 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW15_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW15_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW15_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW16_EXISTS 16:16 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW16_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW16_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW16_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW17_EXISTS 17:17 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW17_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW17_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW17_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW18_EXISTS 18:18 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW18_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW18_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW18_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW19_EXISTS 19:19 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW19_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW19_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW19_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW20_EXISTS 20:20 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW20_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW20_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW20_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW21_EXISTS 21:21 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW21_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW21_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW21_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW22_EXISTS 22:22 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW22_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW22_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW22_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW23_EXISTS 23:23 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW23_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW23_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW23_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW24_EXISTS 24:24 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW24_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW24_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW24_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW25_EXISTS 25:25 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW25_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW25_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW25_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW26_EXISTS 26:26 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW26_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW26_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW26_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW27_EXISTS 27:27 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW27_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW27_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW27_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW28_EXISTS 28:28 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW28_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW28_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW28_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW29_EXISTS 29:29 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW29_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW29_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW29_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW30_EXISTS 30:30 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW30_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW30_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW30_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW31_EXISTS 31:31 /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW31_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW31_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW31_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVC573_SYS_CAPB_WINDOW_EXISTS__SIZE_1 32 /* */ +#define NVC573_SYS_CAPB_WINDOW_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SYS_CAPB_WINDOW_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC573_SYS_CAPB_WINDOW_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA 0x10 /* RW-4R */ +#define NVC573_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES 15:0 /* RWIUF */ +#define NVC573_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH 17:16 /* RWIVF */ +#define NVC573_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B 0x00000000 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B 0x00000002 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B 0x00000003 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_PLANAR 19:19 /* RWIVF */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_PLANAR_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_PLANAR_FALSE 0x00000000 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_PLANAR_TRUE 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_VGA 20:20 /* RWIVF */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_VGA_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE 0x00000000 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION 21:21 /* RWIVF */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_FALSE 0x00000000 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_TRUE 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MSCG 22:22 /* RWIVF */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MSCG_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MSCG_FALSE 0x00000000 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MSCG_TRUE 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH 23:23 /* RWIVF */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_FALSE 0x00000000 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_TRUE 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT 26:26 /* RWIVF */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION 31:30 /* RWIVF */ +#define NVC573_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_INIT 0x00000000 /* RWI-V */ +#define NVC573_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B 0x00000000 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B 0x00000001 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B 0x00000002 /* RW--V */ +#define NVC573_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B 0x00000003 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA(i) (0x680+(i)*32) /* RW-4A */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA__SIZE_1 8 /* */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_FULL_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_UNIT_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT 16:16 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT 17:17 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT 18:18 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OLPF_PRESENT 19:19 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OLPF_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OLPF_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OLPF_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT 20:20 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT 21:21 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT 22:22 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB(i) (0x684+(i)*32) /* RW-4A */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB__SIZE_1 8 /* */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_VGA 0:0 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_VGA_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_VGA_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_VGA_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGSZ 9:6 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGSZ_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGNR 12:10 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGNR_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT 15:15 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC(i) (0x688+(i)*32) /* RW-4A */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC__SIZE_1 8 /* */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC0_PRECISION 4:0 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC0_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC1_PRECISION 12:8 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC1_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP 13:13 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_SF_PRECISION 20:16 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_SF_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_CI_PRECISION 24:21 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_CI_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB 25:25 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPD(i) (0x68c+(i)*32) /* RW-4A */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPD__SIZE_1 8 /* */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE(i) (0x690+(i)*32) /* RW-4A */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE__SIZE_1 8 /* */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_RATEBUFSIZE 3:0 /* RWIUF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_RATEBUFSIZE_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_LINEBUFSIZE 13:8 /* RWIUF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_LINEBUFSIZE_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422 16:16 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_INIT 0x00000000 /* RWI-V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420 17:17 /* RWIVF */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_TRUE 0x00000001 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_FALSE 0x00000000 /* RW--V */ +#define NVC573_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP(i) (0x144+(i)*8) /* RW-4A */ +#define NVC573_SOR_CAP__SIZE_1 8 /* */ +#define NVC573_SOR_CAP_SINGLE_LVDS_18 0:0 /* RWIVF */ +#define NVC573_SOR_CAP_SINGLE_LVDS_18_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_SINGLE_LVDS_24 1:1 /* RWIVF */ +#define NVC573_SOR_CAP_SINGLE_LVDS_24_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_DUAL_LVDS_18 2:2 /* RWIVF */ +#define NVC573_SOR_CAP_DUAL_LVDS_18_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_DUAL_LVDS_24 3:3 /* RWIVF */ +#define NVC573_SOR_CAP_DUAL_LVDS_24_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_SINGLE_TMDS_A 8:8 /* RWIVF */ +#define NVC573_SOR_CAP_SINGLE_TMDS_A_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_SINGLE_TMDS_B 9:9 /* RWIVF */ +#define NVC573_SOR_CAP_SINGLE_TMDS_B_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_DUAL_TMDS 11:11 /* RWIVF */ +#define NVC573_SOR_CAP_DUAL_TMDS_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* RWIVF */ +#define NVC573_SOR_CAP_DISPLAY_OVER_PCIE_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_SDI 16:16 /* RWIVF */ +#define NVC573_SOR_CAP_SDI_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_SDI_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_SDI_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_DP_A 24:24 /* RWIVF */ +#define NVC573_SOR_CAP_DP_A_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_DP_A_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_DP_A_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_DP_B 25:25 /* RWIVF */ +#define NVC573_SOR_CAP_DP_B_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_DP_B_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_DP_B_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_DP_INTERLACE 26:26 /* RWIVF */ +#define NVC573_SOR_CAP_DP_INTERLACE_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* RW--V */ +#define NVC573_SOR_CAP_DP_8_LANES 27:27 /* RWIVF */ +#define NVC573_SOR_CAP_DP_8_LANES_INIT 0x00000000 /* RWI-V */ +#define NVC573_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* RW--V */ +#define NVC573_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA(i) (0x780+(i)*32) /* RW-4A */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA__SIZE_1 32 /* */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH 13:10 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT 16:16 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT 17:17 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT 18:18 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT 19:19 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT 20:20 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT 21:21 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT 22:22 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT 23:23 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT 24:24 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB(i) (0x784+(i)*32) /* RW-4A */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB__SIZE_1 32 /* */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION 4:0 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ 9:6 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR 12:10 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT 15:15 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC(i) (0x788+(i)*32) /* RW-4A */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC__SIZE_1 32 /* */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION 4:0 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGSZ 9:6 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGSZ_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGNR 12:10 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGNR_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT 15:15 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION 20:16 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP 21:21 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD(i) (0x78c+(i)*32) /* RW-4A */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD__SIZE_1 32 /* */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ 3:0 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR 6:4 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD 8:8 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT 9:9 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION 16:12 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION 20:17 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB 21:21 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA 22:22 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE(i) (0x790+(i)*32) /* RW-4A */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE__SIZE_1 32 /* */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION 4:0 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGSZ 9:6 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGSZ_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGNR 12:10 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGNR_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT 15:15 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION 20:16 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP 21:21 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPF(i) (0x794+(i)*32) /* RW-4A */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPF__SIZE_1 32 /* */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP_INIT 0x00000000 /* RWI-V */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */ +#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP_INIT 0x00000000 /* RWI-V */ + +#ifdef __cplusplus +}; +#endif /* extern C */ +#endif //_clc573_h_ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc574.h b/userspace/sdks/nv570/nvidia/inc/class/clc574.h new file mode 100644 index 0000000..4587c7a --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc574.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc574.finn +// + +#define UVM_CHANNEL_RETAINER (0xc574U) /* finn: Evaluated from "NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_MESSAGE_ID" */ + +#define NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_MESSAGE_ID (0xc574U) + +typedef struct NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS { + NvHandle hClient; + NvHandle hChannel; +} NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc57a.h b/userspace/sdks/nv570/nvidia/inc/class/clc57a.h new file mode 100644 index 0000000..54eb741 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc57a.h @@ -0,0 +1,179 @@ +/* + * Copyright (c) 1993-2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc57a__h_ +#define _clc57a__h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC57A_CURSOR_IMM_CHANNEL_PIO (0x0000C57A) + +typedef volatile struct _clc57a_tag0 { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x7D]; + NvV32 Update; // 0x00000200 - 0x00000203 + NvV32 SetInterlockFlags; // 0x00000204 - 0x00000207 + NvV32 SetCursorHotSpotPointOut[2]; // 0x00000208 - 0x0000020F + NvV32 SetWindowInterlockFlags; // 0x00000210 - 0x00000213 + NvV32 Reserved02[0x37B]; +} NVC57ADispCursorImmControlPio; + +#define NVC57A_FREE (0x00000008) +#define NVC57A_FREE_COUNT 5:0 +#define NVC57A_UPDATE (0x00000200) +#define NVC57A_SET_INTERLOCK_FLAGS (0x00000204) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC57A_SET_CURSOR_HOT_SPOT_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVC57A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0 +#define NVC57A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS (0x00000210) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC57A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc57a_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc57b.h b/userspace/sdks/nv570/nvidia/inc/class/clc57b.h new file mode 100644 index 0000000..545ccc5 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc57b.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clC57b_h_ +#define _clC57b_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC57B_WINDOW_IMM_CHANNEL_DMA (0x0000C57B) + +// dma opcode instructions +#define NVC57B_DMA +#define NVC57B_DMA_OPCODE 31:29 +#define NVC57B_DMA_OPCODE_METHOD 0x00000000 +#define NVC57B_DMA_OPCODE_JUMP 0x00000001 +#define NVC57B_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC57B_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC57B_DMA_METHOD_COUNT 27:18 +#define NVC57B_DMA_METHOD_OFFSET 13:2 +#define NVC57B_DMA_DATA 31:0 +#define NVC57B_DMA_DATA_NOP 0x00000000 +#define NVC57B_DMA_JUMP_OFFSET 11:2 +#define NVC57B_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVC57B_PUT (0x00000000) +#define NVC57B_PUT_PTR 9:0 +#define NVC57B_GET (0x00000004) +#define NVC57B_GET_PTR 9:0 +#define NVC57B_UPDATE (0x00000200) +#define NVC57B_UPDATE_INTERLOCK_WITH_WINDOW 1:1 +#define NVC57B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC57B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC57B_SET_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVC57B_SET_POINT_OUT_X 15:0 +#define NVC57B_SET_POINT_OUT_Y 31:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC57b_h diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc57d.h b/userspace/sdks/nv570/nvidia/inc/class/clc57d.h new file mode 100644 index 0000000..4f415d0 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc57d.h @@ -0,0 +1,1277 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clC57d_h_ +#define _clC57d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC57D_CORE_CHANNEL_DMA (0x0000C57D) + +#define NV_DISP_NOTIFIER 0x00000000 +#define NV_DISP_NOTIFIER_SIZEOF 0x00000010 +#define NV_DISP_NOTIFIER__0 0x00000000 +#define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFIER__0_FIELD 8:8 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE 9:9 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001 +#define NV_DISP_NOTIFIER__0_R1 15:10 +#define NV_DISP_NOTIFIER__0_R2 23:16 +#define NV_DISP_NOTIFIER__0_R3 29:24 +#define NV_DISP_NOTIFIER__0_STATUS 31:30 +#define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002 +#define NV_DISP_NOTIFIER__1 0x00000001 +#define NV_DISP_NOTIFIER__1_R4 31:0 +#define NV_DISP_NOTIFIER__2 0x00000002 +#define NV_DISP_NOTIFIER__2_TIMESTAMP_LO 31:0 +#define NV_DISP_NOTIFIER__3 0x00000003 +#define NV_DISP_NOTIFIER__3_TIMESTAMP_HI 31:0 + + +// dma opcode instructions +#define NVC57D_DMA +#define NVC57D_DMA_OPCODE 31:29 +#define NVC57D_DMA_OPCODE_METHOD 0x00000000 +#define NVC57D_DMA_OPCODE_JUMP 0x00000001 +#define NVC57D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC57D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC57D_DMA_METHOD_COUNT 27:18 +#define NVC57D_DMA_METHOD_OFFSET 13:2 +#define NVC57D_DMA_DATA 31:0 +#define NVC57D_DMA_DATA_NOP 0x00000000 +#define NVC57D_DMA_JUMP_OFFSET 11:2 +#define NVC57D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// if cap SUPPORT_FLEXIBLE_WIN_MAPPING is FALSE, this define can be used to obtain which head a window is mapped to +#define NVC37D_WINDOW_MAPPED_TO_HEAD(w) ((w)>>1) +#define NVC37D_GET_VALID_WINDOWMASK_FOR_HEAD(h) ((1<<((h)*2)) | (1<<((h)*2+1))) + +// class methods +#define NVC57D_PUT (0x00000000) +#define NVC57D_PUT_PTR 9:0 +#define NVC57D_GET (0x00000004) +#define NVC57D_GET_PTR 9:0 +#define NVC57D_UPDATE (0x00000200) +#define NVC57D_UPDATE_SPECIAL_HANDLING 21:20 +#define NVC57D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NVC57D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NVC57D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NVC57D_UPDATE_SPECIAL_HANDLING_REASON 19:12 +#define NVC57D_UPDATE_INHIBIT_INTERRUPTS 24:24 +#define NVC57D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NVC57D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NVC57D_UPDATE_RELEASE_ELV 0:0 +#define NVC57D_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC57D_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC57D_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC57D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC57D_SET_CONTEXT_DMA_NOTIFIER (0x00000208) +#define NVC57D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NVC57D_SET_NOTIFIER_CONTROL (0x0000020C) +#define NVC57D_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC57D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC57D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC57D_SET_NOTIFIER_CONTROL_OFFSET 11:4 +#define NVC57D_SET_NOTIFIER_CONTROL_NOTIFY 12:12 +#define NVC57D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NVC57D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NVC57D_SET_CONTROL (0x00000210) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN(i) ((i)+0):((i)+0) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN__SIZE_1 4 +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN_DISABLE (0x00000000) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN_ENABLE (0x00000001) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN0 0:0 +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN0_DISABLE (0x00000000) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN0_ENABLE (0x00000001) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN1 1:1 +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN1_DISABLE (0x00000000) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN1_ENABLE (0x00000001) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN2 2:2 +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN2_DISABLE (0x00000000) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN2_ENABLE (0x00000001) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN3 3:3 +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN3_DISABLE (0x00000000) +#define NVC57D_SET_CONTROL_FLIP_LOCK_PIN3_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS (0x00000218) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+0):((i)+0) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC57D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS (0x0000021C) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC57D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVC57D_GET_RG_SCAN_LINE(b) (0x00000220 + (b)*0x00000004) +#define NVC57D_GET_RG_SCAN_LINE_LINE 15:0 +#define NVC57D_GET_RG_SCAN_LINE_VBLANK 16:16 +#define NVC57D_GET_RG_SCAN_LINE_VBLANK_FALSE (0x00000000) +#define NVC57D_GET_RG_SCAN_LINE_VBLANK_TRUE (0x00000001) +#define NVC57D_SET_GET_BLANKING_CTRL(b) (0x00000240 + (b)*0x00000004) +#define NVC57D_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NVC57D_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NVC57D_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NVC57D_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NVC57D_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NVC57D_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) + +#define NVC57D_SOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK 7:0 +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVC57D_SOR_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVC57D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NVC57D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NVC57D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NVC57D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NVC57D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NVC57D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NVC57D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NVC57D_SOR_SET_CONTROL_PROTOCOL_DSI (0x0000000A) +#define NVC57D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NVC57D_SOR_SET_CONTROL_DE_SYNC_POLARITY 16:16 +#define NVC57D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC57D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC57D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NVC57D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NVC57D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NVC57D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NVC57D_SOR_SET_CUSTOM_REASON(a) (0x00000304 + (a)*0x00000020) +#define NVC57D_SOR_SET_CUSTOM_REASON_CODE 31:0 +#define NVC57D_SOR_SET_SW_SPARE_A(a) (0x00000308 + (a)*0x00000020) +#define NVC57D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NVC57D_SOR_SET_SW_SPARE_B(a) (0x0000030C + (a)*0x00000020) +#define NVC57D_SOR_SET_SW_SPARE_B_CODE 31:0 + +#define NVC57D_WINDOW_SET_CONTROL(a) (0x00001000 + (a)*0x00000080) +#define NVC57D_WINDOW_SET_CONTROL_OWNER 3:0 +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD(i) (0x00000000 +(i)) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD__SIZE_1 8 +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD0 (0x00000000) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD1 (0x00000001) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD2 (0x00000002) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD3 (0x00000003) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD4 (0x00000004) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD5 (0x00000005) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD6 (0x00000006) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_HEAD7 (0x00000007) +#define NVC57D_WINDOW_SET_CONTROL_OWNER_NONE (0x0000000F) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0x00000080) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a) (0x00001008 + (a)*0x00000080) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR(a) (0x0000100C + (a)*0x00000080) +#define NVC57D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVC57D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a) (0x00001010 + (a)*0x00000080) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_MAX_PIXELS_FETCHED_PER_LINE 14:0 +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED 16:16 +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED 28:28 +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS 22:20 +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED 24:24 +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) + +#define NVC57D_HEAD_SET_PROCAMP(a) (0x00002000 + (a)*0x00000400) +#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003) +#define NVC57D_HEAD_SET_PROCAMP_CHROMA_LPF 3:3 +#define NVC57D_HEAD_SET_PROCAMP_CHROMA_LPF_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_PROCAMP_CHROMA_LPF_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 28:28 +#define NVC57D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NVC57D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00002004 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 2:2 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 3:3 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 7:4 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000004) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000005) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000006) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000007) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000008) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 24:24 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 23:12 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN 31:26 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN0 (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN1 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN2 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN3 (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN4 (0x00000004) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN5 (0x00000005) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN6 (0x00000006) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN7 (0x00000007) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN8 (0x00000008) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN9 (0x00000009) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN10 (0x0000000A) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN11 (0x0000000B) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN12 (0x0000000C) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN13 (0x0000000D) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN14 (0x0000000E) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN15 (0x0000000F) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN16 (0x00000010) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN17 (0x00000011) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN18 (0x00000012) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN19 (0x00000013) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN20 (0x00000014) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN21 (0x00000015) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN22 (0x00000016) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN23 (0x00000017) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN24 (0x00000018) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN25 (0x00000019) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN26 (0x0000001A) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN27 (0x0000001B) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN28 (0x0000001C) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN29 (0x0000001D) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN30 (0x0000001E) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN31 (0x0000001F) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_NONE (0x0000003F) +#define NVC57D_HEAD_SET_CONTROL(a) (0x00002008 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CONTROL_STRUCTURE 1:0 +#define NVC57D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE 2:2 +#define NVC57D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_NORMAL (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 11:10 +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 8:4 +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 15:12 +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 23:22 +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 20:16 +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC57D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN 28:24 +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000004) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000005) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000006) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000007) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000008) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000009) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000B) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000C) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000D) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000E) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000F) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x00000010) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC57D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NVC57D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NVC57D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x0000200C + (a)*0x00000400) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC57D_HEAD_SET_PIXEL_REORDER_CONTROL(a) (0x00002010 + (a)*0x00000400) +#define NVC57D_HEAD_SET_PIXEL_REORDER_CONTROL_BANK_WIDTH 13:0 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00002014 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVC57D_HEAD_SET_DITHER_CONTROL(a) (0x00002018 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NVC57D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_DITHER_CONTROL_BITS 5:4 +#define NVC57D_HEAD_SET_DITHER_CONTROL_BITS_TO_6_BITS (0x00000000) +#define NVC57D_HEAD_SET_DITHER_CONTROL_BITS_TO_8_BITS (0x00000001) +#define NVC57D_HEAD_SET_DITHER_CONTROL_BITS_TO_10_BITS (0x00000002) +#define NVC57D_HEAD_SET_DITHER_CONTROL_BITS_TO_12_BITS (0x00000003) +#define NVC57D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE 2:2 +#define NVC57D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_DITHER_CONTROL_MODE 10:8 +#define NVC57D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NVC57D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NVC57D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NVC57D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NVC57D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NVC57D_HEAD_SET_DITHER_CONTROL_MODE_ROUND (0x00000005) +#define NVC57D_HEAD_SET_DITHER_CONTROL_PHASE 13:12 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x0000201C + (a)*0x00000400) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 0:0 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING 4:4 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 9:8 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NVC57D_HEAD_SET_DISPLAY_ID(a,b) (0x00002020 + (a)*0x00000400 + (b)*0x00000004) +#define NVC57D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00002028 + (a)*0x00000400) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC57D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR(a) (0x0000202C + (a)*0x00000400) +#define NVC57D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVC57D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS(a) (0x00002030 + (a)*0x00000400) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR 2:0 +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_NONE (0x00000000) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W32_H32 (0x00000001) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W64_H64 (0x00000002) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W128_H128 (0x00000003) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W256_H256 (0x00000004) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED 4:4 +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_FALSE (0x00000000) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_TRUE (0x00000001) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS 14:12 +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED 8:8 +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVC57D_HEAD_SET_STALL_LOCK(a) (0x00002034 + (a)*0x00000400) +#define NVC57D_HEAD_SET_STALL_LOCK_ENABLE 0:0 +#define NVC57D_HEAD_SET_STALL_LOCK_ENABLE_FALSE (0x00000000) +#define NVC57D_HEAD_SET_STALL_LOCK_ENABLE_TRUE (0x00000001) +#define NVC57D_HEAD_SET_STALL_LOCK_MODE 2:2 +#define NVC57D_HEAD_SET_STALL_LOCK_MODE_CONTINUOUS (0x00000000) +#define NVC57D_HEAD_SET_STALL_LOCK_MODE_ONE_SHOT (0x00000001) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN 8:4 +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC57D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC57D_HEAD_SET_STALL_LOCK_UNSTALL_MODE 12:12 +#define NVC57D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_CRASH_LOCK (0x00000000) +#define NVC57D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_LINE_LOCK (0x00000001) +#define NVC57D_HEAD_SET_STALL_LOCK_TEPOLARITY 14:14 +#define NVC57D_HEAD_SET_STALL_LOCK_TEPOLARITY_POSITIVE_TRUE (0x00000000) +#define NVC57D_HEAD_SET_STALL_LOCK_TEPOLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC57D_HEAD_SET_LOCK_CHAIN(a) (0x00002044 + (a)*0x00000400) +#define NVC57D_HEAD_SET_LOCK_CHAIN_POSITION 3:0 +#define NVC57D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x00002048 + (a)*0x00000400) +#define NVC57D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NVC57D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NVC57D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x0000204C + (a)*0x00000400) +#define NVC57D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NVC57D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NVC57D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x00002058 + (a)*0x00000400) +#define NVC57D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NVC57D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NVC57D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x0000205C + (a)*0x00000400) +#define NVC57D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NVC57D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NVC57D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000400) +#define NVC57D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NVC57D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NVC57D_HEAD_SET_RASTER_SYNC_END(a) (0x00002068 + (a)*0x00000400) +#define NVC57D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NVC57D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NVC57D_HEAD_SET_RASTER_BLANK_END(a) (0x0000206C + (a)*0x00000400) +#define NVC57D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NVC57D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NVC57D_HEAD_SET_RASTER_BLANK_START(a) (0x00002070 + (a)*0x00000400) +#define NVC57D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NVC57D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NVC57D_HEAD_SET_OVERSCAN_COLOR(a) (0x00002078 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OVERSCAN_COLOR_RED_CR 9:0 +#define NVC57D_HEAD_SET_OVERSCAN_COLOR_GREEN_Y 19:10 +#define NVC57D_HEAD_SET_OVERSCAN_COLOR_BLUE_CB 29:20 +#define NVC57D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR(a) (0x0000207C + (a)*0x00000400) +#define NVC57D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_RED_CR 9:0 +#define NVC57D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_GREEN_Y 19:10 +#define NVC57D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_BLUE_CB 29:20 +#define NVC57D_HEAD_SET_HDMI_CTRL(a) (0x00002080 + (a)*0x00000400) +#define NVC57D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NVC57D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NVC57D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NVC57D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NVC57D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NVC57D_HEAD_SET_CONTEXT_DMA_CURSOR(a,b) (0x00002088 + (a)*0x00000400 + (b)*0x00000004) +#define NVC57D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0 +#define NVC57D_HEAD_SET_OFFSET_CURSOR(a,b) (0x00002090 + (a)*0x00000400 + (b)*0x00000004) +#define NVC57D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0 +#define NVC57D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x00002098 + (a)*0x00000400) +#define NVC57D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 0:0 +#define NVC57D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NVC57D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_CURSOR(a) (0x0000209C + (a)*0x00000400) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_FORMAT 7:0 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_SIZE 9:8 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 19:12 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 27:20 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION(a) (0x000020A0 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_K1 7:0 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT 11:8 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT 15:12 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_ZERO (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE 16:16 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_BLEND (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_XOR (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS 20:20 +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00002180 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NVC57D_HEAD_SET_CRC_CONTROL(a) (0x00002184 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 5:0 +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_0 (0x00000000) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_1 (0x00000001) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_2 (0x00000002) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_3 (0x00000003) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_4 (0x00000004) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_5 (0x00000005) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_6 (0x00000006) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_7 (0x00000007) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_8 (0x00000008) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_9 (0x00000009) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_10 (0x0000000A) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_11 (0x0000000B) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_12 (0x0000000C) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_13 (0x0000000D) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_14 (0x0000000E) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_15 (0x0000000F) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_16 (0x00000010) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_17 (0x00000011) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_18 (0x00000012) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_19 (0x00000013) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_20 (0x00000014) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_21 (0x00000015) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_22 (0x00000016) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_23 (0x00000017) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_24 (0x00000018) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_25 (0x00000019) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_26 (0x0000001A) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_27 (0x0000001B) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_28 (0x0000001C) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_29 (0x0000001D) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_30 (0x0000001E) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_31 (0x0000001F) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000020) +#define NVC57D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 8:8 +#define NVC57D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NVC57D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC 19:12 +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_NONE (0x00000000) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SF (0x00000030) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR__SIZE_1 8 +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR0 (0x00000050) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR1 (0x00000051) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR2 (0x00000052) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR3 (0x00000053) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR4 (0x00000054) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR5 (0x00000055) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR6 (0x00000056) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR7 (0x00000057) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC 27:20 +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_NONE (0x00000000) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SF (0x00000030) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR__SIZE_1 8 +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR0 (0x00000050) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR1 (0x00000051) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR2 (0x00000052) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR3 (0x00000053) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR4 (0x00000054) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR5 (0x00000055) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR6 (0x00000056) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR7 (0x00000057) +#define NVC57D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 9:9 +#define NVC57D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_PRESENT_CONTROL(a) (0x0000218C + (a)*0x00000400) +#define NVC57D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 0:0 +#define NVC57D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NVC57D_HEAD_SET_SW_SPARE_A(a) (0x00002194 + (a)*0x00000400) +#define NVC57D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NVC57D_HEAD_SET_SW_SPARE_B(a) (0x00002198 + (a)*0x00000400) +#define NVC57D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NVC57D_HEAD_SET_SW_SPARE_C(a) (0x0000219C + (a)*0x00000400) +#define NVC57D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NVC57D_HEAD_SET_SW_SPARE_D(a) (0x000021A0 + (a)*0x00000400) +#define NVC57D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NVC57D_HEAD_SET_DISPLAY_RATE(a) (0x000021A8 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DISPLAY_RATE_RUN_MODE 0:0 +#define NVC57D_HEAD_SET_DISPLAY_RATE_RUN_MODE_CONTINUOUS (0x00000000) +#define NVC57D_HEAD_SET_DISPLAY_RATE_RUN_MODE_ONE_SHOT (0x00000001) +#define NVC57D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_INTERVAL 25:4 +#define NVC57D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH 2:2 +#define NVC57D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE(a) (0x00002214 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVC57D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVC57D_HEAD_SET_MIN_FRAME_IDLE(a) (0x00002218 + (a)*0x00000400) +#define NVC57D_HEAD_SET_MIN_FRAME_IDLE_LEADING_RASTER_LINES 14:0 +#define NVC57D_HEAD_SET_MIN_FRAME_IDLE_TRAILING_RASTER_LINES 30:16 +#define NVC57D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED(a) (0x00002220 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED_ALPHA 7:0 +#define NVC57D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED_RED 31:16 +#define NVC57D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE(a) (0x00002224 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE_GREEN 15:0 +#define NVC57D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE_BLUE 31:16 +#define NVC57D_HEAD_SET_CURSOR_COLOR_NORM_SCALE(a) (0x00002228 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CURSOR_COLOR_NORM_SCALE_VALUE 15:0 +#define NVC57D_HEAD_SET_XOR_BLEND_FACTOR(a) (0x0000222C + (a)*0x00000400) +#define NVC57D_HEAD_SET_XOR_BLEND_FACTOR_LOG2PEAK_LUMINANCE 3:0 +#define NVC57D_HEAD_SET_XOR_BLEND_FACTOR_S1 16:4 +#define NVC57D_HEAD_SET_XOR_BLEND_FACTOR_S2 30:18 +#define NVC57D_HEAD_SET_CLAMP_RANGE_GREEN(a) (0x00002238 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CLAMP_RANGE_GREEN_LOW 11:0 +#define NVC57D_HEAD_SET_CLAMP_RANGE_GREEN_HIGH 27:16 +#define NVC57D_HEAD_SET_CLAMP_RANGE_RED_BLUE(a) (0x0000223C + (a)*0x00000400) +#define NVC57D_HEAD_SET_CLAMP_RANGE_RED_BLUE_LOW 11:0 +#define NVC57D_HEAD_SET_CLAMP_RANGE_RED_BLUE_HIGH 27:16 +#define NVC57D_HEAD_SET_OCSC0CONTROL(a) (0x00002240 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0CONTROL_ENABLE 0:0 +#define NVC57D_HEAD_SET_OCSC0CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_OCSC0CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C00(a) (0x00002244 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C00_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C01(a) (0x00002248 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C01_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C02(a) (0x0000224C + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C02_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C03(a) (0x00002250 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C03_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C10(a) (0x00002254 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C10_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C11(a) (0x00002258 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C11_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C12(a) (0x0000225C + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C12_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C13(a) (0x00002260 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C13_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C20(a) (0x00002264 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C20_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C21(a) (0x00002268 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C21_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C22(a) (0x0000226C + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C22_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C23(a) (0x00002270 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC0COEFFICIENT_C23_VALUE 20:0 +#define NVC57D_HEAD_SET_OLUT_CONTROL(a) (0x00002280 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OLUT_CONTROL_INTERPOLATE 0:0 +#define NVC57D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_OLUT_CONTROL_MIRROR 1:1 +#define NVC57D_HEAD_SET_OLUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_OLUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_OLUT_CONTROL_MODE 3:2 +#define NVC57D_HEAD_SET_OLUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVC57D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVC57D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVC57D_HEAD_SET_OLUT_CONTROL_SIZE 18:8 +#define NVC57D_HEAD_SET_OLUT_FP_NORM_SCALE(a) (0x00002284 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OLUT_FP_NORM_SCALE_VALUE 31:0 +#define NVC57D_HEAD_SET_CONTEXT_DMA_OLUT(a) (0x00002288 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CONTEXT_DMA_OLUT_HANDLE 31:0 +#define NVC57D_HEAD_SET_OFFSET_OLUT(a) (0x0000228C + (a)*0x00000400) +#define NVC57D_HEAD_SET_OFFSET_OLUT_ORIGIN 31:0 +#define NVC57D_HEAD_SET_OCSC1CONTROL(a) (0x0000229C + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1CONTROL_ENABLE 0:0 +#define NVC57D_HEAD_SET_OCSC1CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_OCSC1CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C00(a) (0x000022A0 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C00_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C01(a) (0x000022A4 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C01_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C02(a) (0x000022A8 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C02_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C03(a) (0x000022AC + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C03_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C10(a) (0x000022B0 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C10_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C11(a) (0x000022B4 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C11_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C12(a) (0x000022B8 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C12_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C13(a) (0x000022BC + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C13_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C20(a) (0x000022C0 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C20_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C21(a) (0x000022C4 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C21_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C22(a) (0x000022C8 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C22_VALUE 20:0 +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C23(a) (0x000022CC + (a)*0x00000400) +#define NVC57D_HEAD_SET_OCSC1COEFFICIENT_C23_VALUE 20:0 +#define NVC57D_HEAD_SET_TILE_POSITION(a) (0x000022D0 + (a)*0x00000400) +#define NVC57D_HEAD_SET_TILE_POSITION_X 2:0 +#define NVC57D_HEAD_SET_TILE_POSITION_Y 6:4 +#define NVC57D_HEAD_SET_DSC_CONTROL(a) (0x000022D4 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_CONTROL_ENABLE 0:0 +#define NVC57D_HEAD_SET_DSC_CONTROL_ENABLE_FALSE (0x00000000) +#define NVC57D_HEAD_SET_DSC_CONTROL_ENABLE_TRUE (0x00000001) +#define NVC57D_HEAD_SET_DSC_CONTROL_MODE 2:1 +#define NVC57D_HEAD_SET_DSC_CONTROL_MODE_SINGLE (0x00000000) +#define NVC57D_HEAD_SET_DSC_CONTROL_MODE_DUAL (0x00000001) +#define NVC57D_HEAD_SET_DSC_CONTROL_MODE_QUAD (0x00000002) +#define NVC57D_HEAD_SET_DSC_CONTROL_MODE_DROP (0x00000003) +#define NVC57D_HEAD_SET_DSC_CONTROL_AUTO_RESET 3:3 +#define NVC57D_HEAD_SET_DSC_CONTROL_AUTO_RESET_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_DSC_CONTROL_AUTO_RESET_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION 4:4 +#define NVC57D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET 5:5 +#define NVC57D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET_FALSE (0x00000000) +#define NVC57D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET_TRUE (0x00000001) +#define NVC57D_HEAD_SET_DSC_CONTROL_FLATNESS_DET_THRESH 15:6 +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL(a) (0x000022D8 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_ENABLE 0:0 +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_ENABLE_FALSE (0x00000000) +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_ENABLE_TRUE (0x00000001) +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_LOCATION 1:1 +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_VSYNC (0x00000000) +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_VBLANK (0x00000001) +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_SIZE 9:2 +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY 10:10 +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVC57D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY_ONCE (0x00000001) +#define NVC57D_HEAD_SET_DSC_PPS_HEAD(a) (0x000022DC + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_HEAD_BYTE0 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_HEAD_BYTE1 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_HEAD_BYTE2 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_HEAD_BYTE3 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA0(a) (0x000022E0 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA0_DSC_VERSION_MINOR 3:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA0_DSC_VERSION_MAJOR 7:4 +#define NVC57D_HEAD_SET_DSC_PPS_DATA0_PPS_IDENTIFIER 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA0_RESERVED 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA0_LINEBUF_DEPTH 27:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA0_BITS_PER_COMPONENT 31:28 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1(a) (0x000022E4 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_BITS_PER_PIXEL_HIGH 1:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_VBR_ENABLE 2:2 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_SIMPLE422 3:3 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_CONVERT_RGB 4:4 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_BLOCK_PRED_ENABLE 5:5 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_RESERVED 7:6 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_BITS_PER_PIXEL_LOW 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_PIC_HEIGHT_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA1_PIC_HEIGHT_LOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA2(a) (0x000022E8 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA2_PIC_WIDTH_HIGH 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA2_PIC_WIDTH_LOW 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA2_SLICE_HEIGHT_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA2_SLICE_HEIGHT_LOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA3(a) (0x000022EC + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA3_SLICE_WIDTH_HIGH 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA3_SLICE_WIDTH_LOW 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA3_CHUNK_SIZE_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA3_CHUNK_SIZE_LOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA4(a) (0x000022F0 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA4_INITIAL_XMIT_DELAY_HIGH 1:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA4_RESERVED 7:2 +#define NVC57D_HEAD_SET_DSC_PPS_DATA4_INITIAL_XMIT_DELAY_LOW 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA4_INITIAL_DEC_DELAY_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA4_INITIAL_DEC_DELAY_LOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA5(a) (0x000022F4 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA5_RESERVED0 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA5_INITIAL_SCALE_VALUE 13:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA5_RESERVED1 15:14 +#define NVC57D_HEAD_SET_DSC_PPS_DATA5_SCALE_INCREMENT_INTERVAL_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA5_SCALE_INCREMENT_INTERVAL_LOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA6(a) (0x000022F8 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA6_SCALE_DECREMENT_INTERVAL_HIGH 3:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA6_RESERVED0 7:4 +#define NVC57D_HEAD_SET_DSC_PPS_DATA6_SCALE_DECREMENT_INTERVAL_LOW 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA6_RESERVED1 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA6_FIRST_LINE_BPG_OFFSET 28:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA6_RESERVED2 31:29 +#define NVC57D_HEAD_SET_DSC_PPS_DATA7(a) (0x000022FC + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA7_NFL_BPG_OFFSET_HIGH 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA7_NFL_BPG_OFFSET_LOW 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA7_SLICE_BPG_OFFSET_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA7_SLICE_BPG_OFFSET_LOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA8(a) (0x00002300 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA8_INITIAL_OFFSET_HIGH 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA8_INITIAL_OFFSET_LOW 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA8_FINAL_OFFSET_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA8_FINAL_OFFSET_LOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA9(a) (0x00002304 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA9_FLATNESS_MIN_QP 4:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA9_RESERVED0 7:5 +#define NVC57D_HEAD_SET_DSC_PPS_DATA9_FLATNESS_MAX_QP 12:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA9_RESERVED1 15:13 +#define NVC57D_HEAD_SET_DSC_PPS_DATA9_RC_MODEL_SIZE_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA9_RC_MODEL_SIZE_LOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA10(a) (0x00002308 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA10_RC_EDGE_FACTOR 3:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA10_RESERVED0 7:4 +#define NVC57D_HEAD_SET_DSC_PPS_DATA10_RC_QUANT_INCR_LIMIT0 12:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA10_RESERVED1 15:13 +#define NVC57D_HEAD_SET_DSC_PPS_DATA10_RC_QUANT_INCR_LIMIT1 20:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA10_RESERVED2 23:21 +#define NVC57D_HEAD_SET_DSC_PPS_DATA10_RC_TGT_OFFSET_LO 27:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA10_RC_TGT_OFFSET_HI 31:28 +#define NVC57D_HEAD_SET_DSC_PPS_DATA11(a) (0x0000230C + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH0 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH1 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH2 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH3 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA12(a) (0x00002310 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH4 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH5 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH6 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH7 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA13(a) (0x00002314 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH8 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH9 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH10 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH11 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA14(a) (0x00002318 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA14_RC_BUF_THRESH12 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA14_RC_BUF_THRESH13 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MAX_QP_HIGH0 18:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MIN_QP0 23:19 +#define NVC57D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_BPG_OFFSET0 29:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MAX_QP_LOW0 31:30 +#define NVC57D_HEAD_SET_DSC_PPS_DATA15(a) (0x0000231C + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_HIGH1 2:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MIN_QP1 7:3 +#define NVC57D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_BPG_OFFSET1 13:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_LOW1 15:14 +#define NVC57D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_HIGH2 18:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MIN_QP2 23:19 +#define NVC57D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_BPG_OFFSET2 29:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_LOW2 31:30 +#define NVC57D_HEAD_SET_DSC_PPS_DATA16(a) (0x00002320 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_HIGH3 2:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MIN_QP3 7:3 +#define NVC57D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_BPG_OFFSET3 13:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_LOW3 15:14 +#define NVC57D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_HIGH4 18:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MIN_QP4 23:19 +#define NVC57D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_BPG_OFFSET4 29:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_LOW4 31:30 +#define NVC57D_HEAD_SET_DSC_PPS_DATA17(a) (0x00002324 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_HIGH5 2:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MIN_QP5 7:3 +#define NVC57D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_BPG_OFFSET5 13:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_LOW5 15:14 +#define NVC57D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_HIGH6 18:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MIN_QP6 23:19 +#define NVC57D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_BPG_OFFSET6 29:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_LOW6 31:30 +#define NVC57D_HEAD_SET_DSC_PPS_DATA18(a) (0x00002328 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_HIGH7 2:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MIN_QP7 7:3 +#define NVC57D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_BPG_OFFSET7 13:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_LOW7 15:14 +#define NVC57D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_HIGH8 18:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MIN_QP8 23:19 +#define NVC57D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_BPG_OFFSET8 29:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_LOW8 31:30 +#define NVC57D_HEAD_SET_DSC_PPS_DATA19(a) (0x0000232C + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_HIGH9 2:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MIN_QP9 7:3 +#define NVC57D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_BPG_OFFSET9 13:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_LOW9 15:14 +#define NVC57D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_HIGH10 18:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MIN_QP10 23:19 +#define NVC57D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_BPG_OFFSET10 29:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_LOW10 31:30 +#define NVC57D_HEAD_SET_DSC_PPS_DATA20(a) (0x00002330 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_HIGH11 2:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MIN_QP11 7:3 +#define NVC57D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_BPG_OFFSET11 13:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_LOW11 15:14 +#define NVC57D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_HIGH12 18:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MIN_QP12 23:19 +#define NVC57D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_BPG_OFFSET12 29:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_LOW12 31:30 +#define NVC57D_HEAD_SET_DSC_PPS_DATA21(a) (0x00002334 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_HIGH13 2:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MIN_QP13 7:3 +#define NVC57D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_BPG_OFFSET13 13:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_LOW13 15:14 +#define NVC57D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_HIGH14 18:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MIN_QP14 23:19 +#define NVC57D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_BPG_OFFSET14 29:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_LOW14 31:30 +#define NVC57D_HEAD_SET_DSC_PPS_DATA22(a) (0x00002338 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA22_NATIVE422 0:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA22_NATIVE420 1:1 +#define NVC57D_HEAD_SET_DSC_PPS_DATA22_RESERVED0 7:2 +#define NVC57D_HEAD_SET_DSC_PPS_DATA22_SECOND_LINE_BPG_OFFSET 12:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA22_RESERVED1 15:13 +#define NVC57D_HEAD_SET_DSC_PPS_DATA22_NSL_BPG_OFFSET_HIGH 23:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA22_NSL_BPG_OFFSETLOW 31:24 +#define NVC57D_HEAD_SET_DSC_PPS_DATA23(a) (0x0000233C + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA23_SECOND_LINE_OFFSET_ADJ_HIGH 7:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA23_SECOND_LINE_OFFSET_ADJ_LOW 15:8 +#define NVC57D_HEAD_SET_DSC_PPS_DATA23_RESERVED 31:16 +#define NVC57D_HEAD_SET_DSC_PPS_DATA24(a) (0x00002340 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA24_RESERVED 31:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA25(a) (0x00002344 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA25_RESERVED 31:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA26(a) (0x00002348 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA26_RESERVED 31:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA27(a) (0x0000234C + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA27_RESERVED 31:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA28(a) (0x00002350 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA28_RESERVED 31:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA29(a) (0x00002354 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA29_RESERVED 31:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA30(a) (0x00002358 + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA30_RESERVED 31:0 +#define NVC57D_HEAD_SET_DSC_PPS_DATA31(a) (0x0000235C + (a)*0x00000400) +#define NVC57D_HEAD_SET_DSC_PPS_DATA31_RESERVED 31:0 +#define NVC57D_HEAD_SET_RG_MERGE(a) (0x00002360 + (a)*0x00000400) +#define NVC57D_HEAD_SET_RG_MERGE_MODE 1:0 +#define NVC57D_HEAD_SET_RG_MERGE_MODE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_RG_MERGE_MODE_SETUP (0x00000001) +#define NVC57D_HEAD_SET_RG_MERGE_MODE_MASTER (0x00000002) +#define NVC57D_HEAD_SET_RG_MERGE_MODE_SLAVE (0x00000003) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC57d_h diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc57e.h b/userspace/sdks/nv570/nvidia/inc/class/clc57e.h new file mode 100644 index 0000000..d613410 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc57e.h @@ -0,0 +1,657 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clC57e_h_ +#define _clC57e_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC57E_WINDOW_CHANNEL_DMA (0x0000C57E) + +// dma opcode instructions +#define NVC57E_DMA +#define NVC57E_DMA_OPCODE 31:29 +#define NVC57E_DMA_OPCODE_METHOD 0x00000000 +#define NVC57E_DMA_OPCODE_JUMP 0x00000001 +#define NVC57E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC57E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC57E_DMA_METHOD_COUNT 27:18 +#define NVC57E_DMA_METHOD_OFFSET 13:2 +#define NVC57E_DMA_DATA 31:0 +#define NVC57E_DMA_DATA_NOP 0x00000000 +#define NVC57E_DMA_JUMP_OFFSET 11:2 +#define NVC57E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVC57E_PUT (0x00000000) +#define NVC57E_PUT_PTR 9:0 +#define NVC57E_GET (0x00000004) +#define NVC57E_GET_PTR 9:0 +#define NVC57E_UPDATE (0x00000200) +#define NVC57E_UPDATE_RELEASE_ELV 0:0 +#define NVC57E_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC57E_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC57E_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC57E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC57E_UPDATE_INTERLOCK_WITH_WIN_IMM 12:12 +#define NVC57E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE (0x00000000) +#define NVC57E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE (0x00000001) +#define NVC57E_GET_LINE (0x00000208) +#define NVC57E_GET_LINE_LINE 15:0 +#define NVC57E_SET_SEMAPHORE_CONTROL (0x0000020C) +#define NVC57E_SET_SEMAPHORE_CONTROL_OFFSET 7:0 +#define NVC57E_SET_SEMAPHORE_ACQUIRE (0x00000210) +#define NVC57E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NVC57E_SET_SEMAPHORE_RELEASE (0x00000214) +#define NVC57E_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NVC57E_SET_CONTEXT_DMA_SEMAPHORE (0x00000218) +#define NVC57E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NVC57E_SET_CONTEXT_DMA_NOTIFIER (0x0000021C) +#define NVC57E_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NVC57E_SET_NOTIFIER_CONTROL (0x00000220) +#define NVC57E_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC57E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC57E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC57E_SET_NOTIFIER_CONTROL_OFFSET 11:4 +#define NVC57E_SET_SIZE (0x00000224) +#define NVC57E_SET_SIZE_WIDTH 15:0 +#define NVC57E_SET_SIZE_HEIGHT 31:16 +#define NVC57E_SET_STORAGE (0x00000228) +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC57E_SET_STORAGE_MEMORY_LAYOUT 4:4 +#define NVC57E_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC57E_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC57E_SET_PARAMS (0x0000022C) +#define NVC57E_SET_PARAMS_FORMAT 7:0 +#define NVC57E_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NVC57E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F) +#define NVC57E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NVC57E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC57E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E) +#define NVC57E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC57E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6) +#define NVC57E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NVC57E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9) +#define NVC57E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NVC57E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NVC57E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NVC57E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024) +#define NVC57E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NVC57E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NVC57E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NVC57E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028) +#define NVC57E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029) +#define NVC57E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035) +#define NVC57E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036) +#define NVC57E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038) +#define NVC57E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055) +#define NVC57E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056) +#define NVC57E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058) +#define NVC57E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075) +#define NVC57E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076) +#define NVC57E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078) +#define NVC57E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18 +#define NVC57E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000) +#define NVC57E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001) +#define NVC57E_SET_PARAMS_SWAP_UV 19:19 +#define NVC57E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000) +#define NVC57E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001) +#define NVC57E_SET_PARAMS_FMT_ROUNDING_MODE 22:22 +#define NVC57E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_TO_NEAREST (0x00000000) +#define NVC57E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_DOWN (0x00000001) +#define NVC57E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004) +#define NVC57E_SET_PLANAR_STORAGE_PITCH 12:0 +#define NVC57E_SET_CONTEXT_DMA_ISO(b) (0x00000240 + (b)*0x00000004) +#define NVC57E_SET_CONTEXT_DMA_ISO_HANDLE 31:0 +#define NVC57E_SET_OFFSET(b) (0x00000260 + (b)*0x00000004) +#define NVC57E_SET_OFFSET_ORIGIN 31:0 +#define NVC57E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004) +#define NVC57E_SET_POINT_IN_X 15:0 +#define NVC57E_SET_POINT_IN_Y 31:16 +#define NVC57E_SET_SIZE_IN (0x00000298) +#define NVC57E_SET_SIZE_IN_WIDTH 15:0 +#define NVC57E_SET_SIZE_IN_HEIGHT 31:16 +#define NVC57E_SET_SIZE_OUT (0x000002A4) +#define NVC57E_SET_SIZE_OUT_WIDTH 15:0 +#define NVC57E_SET_SIZE_OUT_HEIGHT 31:16 +#define NVC57E_SET_CONTROL_INPUT_SCALER (0x000002A8) +#define NVC57E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVC57E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVC57E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVC57E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVC57E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVC57E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVC57E_SET_INPUT_SCALER_COEFF_VALUE (0x000002AC) +#define NVC57E_SET_INPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVC57E_SET_INPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVC57E_SET_COMPOSITION_CONTROL (0x000002EC) +#define NVC57E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0 +#define NVC57E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000) +#define NVC57E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001) +#define NVC57E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002) +#define NVC57E_SET_COMPOSITION_CONTROL_DEPTH 11:4 +#define NVC57E_SET_COMPOSITION_CONTROL_BYPASS 16:16 +#define NVC57E_SET_COMPOSITION_CONTROL_BYPASS_DISABLE (0x00000000) +#define NVC57E_SET_COMPOSITION_CONTROL_BYPASS_ENABLE (0x00000001) +#define NVC57E_SET_COMPOSITION_CONSTANT_ALPHA (0x000002F0) +#define NVC57E_SET_COMPOSITION_CONSTANT_ALPHA_K1 7:0 +#define NVC57E_SET_COMPOSITION_CONSTANT_ALPHA_K2 15:8 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT (0x000002F4) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28 +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC57E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC57E_SET_KEY_ALPHA (0x000002F8) +#define NVC57E_SET_KEY_ALPHA_MIN 15:0 +#define NVC57E_SET_KEY_ALPHA_MAX 31:16 +#define NVC57E_SET_KEY_RED_CR (0x000002FC) +#define NVC57E_SET_KEY_RED_CR_MIN 15:0 +#define NVC57E_SET_KEY_RED_CR_MAX 31:16 +#define NVC57E_SET_KEY_GREEN_Y (0x00000300) +#define NVC57E_SET_KEY_GREEN_Y_MIN 15:0 +#define NVC57E_SET_KEY_GREEN_Y_MAX 31:16 +#define NVC57E_SET_KEY_BLUE_CB (0x00000304) +#define NVC57E_SET_KEY_BLUE_CB_MIN 15:0 +#define NVC57E_SET_KEY_BLUE_CB_MAX 31:16 +#define NVC57E_SET_PRESENT_CONTROL (0x00000308) +#define NVC57E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NVC57E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4 +#define NVC57E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NVC57E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NVC57E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8 +#define NVC57E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000) +#define NVC57E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001) +#define NVC57E_SET_PRESENT_CONTROL_STEREO_MODE 13:12 +#define NVC57E_SET_PRESENT_CONTROL_STEREO_MODE_MONO (0x00000000) +#define NVC57E_SET_PRESENT_CONTROL_STEREO_MODE_PAIR_FLIP (0x00000001) +#define NVC57E_SET_PRESENT_CONTROL_STEREO_MODE_AT_ANY_FRAME (0x00000002) +#define NVC57E_SET_TIMESTAMP_ORIGIN_LO (0x00000340) +#define NVC57E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NVC57E_SET_TIMESTAMP_ORIGIN_HI (0x00000344) +#define NVC57E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NVC57E_SET_UPDATE_TIMESTAMP_LO (0x00000348) +#define NVC57E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NVC57E_SET_UPDATE_TIMESTAMP_HI (0x0000034C) +#define NVC57E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NVC57E_SET_INTERLOCK_FLAGS (0x00000370) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 0:0 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+1):((i)+1) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 1:1 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 2:2 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 3:3 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 4:4 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 5:5 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 6:6 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 7:7 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 8:8 +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC57E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS (0x00000374) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC57E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVC57E_SET_EXT_PACKET_CONTROL (0x00000398) +#define NVC57E_SET_EXT_PACKET_CONTROL_ENABLE 0:0 +#define NVC57E_SET_EXT_PACKET_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57E_SET_EXT_PACKET_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57E_SET_EXT_PACKET_CONTROL_LOCATION 4:4 +#define NVC57E_SET_EXT_PACKET_CONTROL_LOCATION_VSYNC (0x00000000) +#define NVC57E_SET_EXT_PACKET_CONTROL_LOCATION_VBLANK (0x00000001) +#define NVC57E_SET_EXT_PACKET_CONTROL_FREQUENCY 8:8 +#define NVC57E_SET_EXT_PACKET_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVC57E_SET_EXT_PACKET_CONTROL_FREQUENCY_ONCE (0x00000001) +#define NVC57E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE 12:12 +#define NVC57E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_DISABLE (0x00000000) +#define NVC57E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_ENABLE (0x00000001) +#define NVC57E_SET_EXT_PACKET_CONTROL_SIZE 27:16 +#define NVC57E_SET_EXT_PACKET_DATA (0x0000039C) +#define NVC57E_SET_EXT_PACKET_DATA_DB0 7:0 +#define NVC57E_SET_EXT_PACKET_DATA_DB1 15:8 +#define NVC57E_SET_EXT_PACKET_DATA_DB2 23:16 +#define NVC57E_SET_EXT_PACKET_DATA_DB3 31:24 +#define NVC57E_SET_FMT_COEFFICIENT_C00 (0x00000400) +#define NVC57E_SET_FMT_COEFFICIENT_C00_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C01 (0x00000404) +#define NVC57E_SET_FMT_COEFFICIENT_C01_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C02 (0x00000408) +#define NVC57E_SET_FMT_COEFFICIENT_C02_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C03 (0x0000040C) +#define NVC57E_SET_FMT_COEFFICIENT_C03_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C10 (0x00000410) +#define NVC57E_SET_FMT_COEFFICIENT_C10_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C11 (0x00000414) +#define NVC57E_SET_FMT_COEFFICIENT_C11_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C12 (0x00000418) +#define NVC57E_SET_FMT_COEFFICIENT_C12_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C13 (0x0000041C) +#define NVC57E_SET_FMT_COEFFICIENT_C13_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C20 (0x00000420) +#define NVC57E_SET_FMT_COEFFICIENT_C20_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C21 (0x00000424) +#define NVC57E_SET_FMT_COEFFICIENT_C21_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C22 (0x00000428) +#define NVC57E_SET_FMT_COEFFICIENT_C22_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C23 (0x0000042C) +#define NVC57E_SET_FMT_COEFFICIENT_C23_VALUE 20:0 +#define NVC57E_SET_ILUT_CONTROL (0x00000440) +#define NVC57E_SET_ILUT_CONTROL_INTERPOLATE 0:0 +#define NVC57E_SET_ILUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC57E_SET_ILUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC57E_SET_ILUT_CONTROL_MIRROR 1:1 +#define NVC57E_SET_ILUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC57E_SET_ILUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC57E_SET_ILUT_CONTROL_MODE 3:2 +#define NVC57E_SET_ILUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVC57E_SET_ILUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVC57E_SET_ILUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVC57E_SET_ILUT_CONTROL_SIZE 18:8 +#define NVC57E_SET_CONTEXT_DMA_ILUT (0x00000444) +#define NVC57E_SET_CONTEXT_DMA_ILUT_HANDLE 31:0 +#define NVC57E_SET_OFFSET_ILUT (0x00000448) +#define NVC57E_SET_OFFSET_ILUT_ORIGIN 31:0 +#define NVC57E_SET_CSC00CONTROL (0x0000045C) +#define NVC57E_SET_CSC00CONTROL_ENABLE 0:0 +#define NVC57E_SET_CSC00CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57E_SET_CSC00CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57E_SET_CSC00COEFFICIENT_C00 (0x00000460) +#define NVC57E_SET_CSC00COEFFICIENT_C00_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C01 (0x00000464) +#define NVC57E_SET_CSC00COEFFICIENT_C01_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C02 (0x00000468) +#define NVC57E_SET_CSC00COEFFICIENT_C02_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C03 (0x0000046C) +#define NVC57E_SET_CSC00COEFFICIENT_C03_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C10 (0x00000470) +#define NVC57E_SET_CSC00COEFFICIENT_C10_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C11 (0x00000474) +#define NVC57E_SET_CSC00COEFFICIENT_C11_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C12 (0x00000478) +#define NVC57E_SET_CSC00COEFFICIENT_C12_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C13 (0x0000047C) +#define NVC57E_SET_CSC00COEFFICIENT_C13_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C20 (0x00000480) +#define NVC57E_SET_CSC00COEFFICIENT_C20_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C21 (0x00000484) +#define NVC57E_SET_CSC00COEFFICIENT_C21_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C22 (0x00000488) +#define NVC57E_SET_CSC00COEFFICIENT_C22_VALUE 20:0 +#define NVC57E_SET_CSC00COEFFICIENT_C23 (0x0000048C) +#define NVC57E_SET_CSC00COEFFICIENT_C23_VALUE 20:0 +#define NVC57E_SET_CSC0LUT_CONTROL (0x000004A0) +#define NVC57E_SET_CSC0LUT_CONTROL_INTERPOLATE 0:0 +#define NVC57E_SET_CSC0LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC57E_SET_CSC0LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC57E_SET_CSC0LUT_CONTROL_MIRROR 1:1 +#define NVC57E_SET_CSC0LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC57E_SET_CSC0LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC57E_SET_CSC0LUT_CONTROL_ENABLE 4:4 +#define NVC57E_SET_CSC0LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57E_SET_CSC0LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57E_SET_CSC0LUT_SEGMENT_SIZE (0x000004A4) +#define NVC57E_SET_CSC0LUT_SEGMENT_SIZE_IDX 5:0 +#define NVC57E_SET_CSC0LUT_SEGMENT_SIZE_VALUE 18:16 +#define NVC57E_SET_CSC0LUT_ENTRY (0x000004A8) +#define NVC57E_SET_CSC0LUT_ENTRY_IDX 10:0 +#define NVC57E_SET_CSC0LUT_ENTRY_VALUE 31:16 +#define NVC57E_SET_CSC01CONTROL (0x000004BC) +#define NVC57E_SET_CSC01CONTROL_ENABLE 0:0 +#define NVC57E_SET_CSC01CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57E_SET_CSC01CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57E_SET_CSC01COEFFICIENT_C00 (0x000004C0) +#define NVC57E_SET_CSC01COEFFICIENT_C00_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C01 (0x000004C4) +#define NVC57E_SET_CSC01COEFFICIENT_C01_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C02 (0x000004C8) +#define NVC57E_SET_CSC01COEFFICIENT_C02_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C03 (0x000004CC) +#define NVC57E_SET_CSC01COEFFICIENT_C03_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C10 (0x000004D0) +#define NVC57E_SET_CSC01COEFFICIENT_C10_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C11 (0x000004D4) +#define NVC57E_SET_CSC01COEFFICIENT_C11_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C12 (0x000004D8) +#define NVC57E_SET_CSC01COEFFICIENT_C12_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C13 (0x000004DC) +#define NVC57E_SET_CSC01COEFFICIENT_C13_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C20 (0x000004E0) +#define NVC57E_SET_CSC01COEFFICIENT_C20_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C21 (0x000004E4) +#define NVC57E_SET_CSC01COEFFICIENT_C21_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C22 (0x000004E8) +#define NVC57E_SET_CSC01COEFFICIENT_C22_VALUE 20:0 +#define NVC57E_SET_CSC01COEFFICIENT_C23 (0x000004EC) +#define NVC57E_SET_CSC01COEFFICIENT_C23_VALUE 20:0 +#define NVC57E_SET_TMO_CONTROL (0x00000500) +#define NVC57E_SET_TMO_CONTROL_INTERPOLATE 0:0 +#define NVC57E_SET_TMO_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC57E_SET_TMO_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC57E_SET_TMO_CONTROL_SAT_MODE 3:2 +#define NVC57E_SET_TMO_CONTROL_SIZE 18:8 +#define NVC57E_SET_TMO_LOW_INTENSITY_ZONE (0x00000508) +#define NVC57E_SET_TMO_LOW_INTENSITY_ZONE_END 29:16 +#define NVC57E_SET_TMO_LOW_INTENSITY_VALUE (0x0000050C) +#define NVC57E_SET_TMO_LOW_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVC57E_SET_TMO_LOW_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVC57E_SET_TMO_LOW_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVC57E_SET_TMO_MEDIUM_INTENSITY_ZONE (0x00000510) +#define NVC57E_SET_TMO_MEDIUM_INTENSITY_ZONE_START 13:0 +#define NVC57E_SET_TMO_MEDIUM_INTENSITY_ZONE_END 29:16 +#define NVC57E_SET_TMO_MEDIUM_INTENSITY_VALUE (0x00000514) +#define NVC57E_SET_TMO_MEDIUM_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVC57E_SET_TMO_MEDIUM_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVC57E_SET_TMO_MEDIUM_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVC57E_SET_TMO_HIGH_INTENSITY_ZONE (0x00000518) +#define NVC57E_SET_TMO_HIGH_INTENSITY_ZONE_START 13:0 +#define NVC57E_SET_TMO_HIGH_INTENSITY_VALUE (0x0000051C) +#define NVC57E_SET_TMO_HIGH_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVC57E_SET_TMO_HIGH_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVC57E_SET_TMO_HIGH_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVC57E_SET_CONTEXT_DMA_TMO_LUT (0x00000528) +#define NVC57E_SET_CONTEXT_DMA_TMO_LUT_HANDLE 31:0 +#define NVC57E_SET_OFFSET_TMO_LUT (0x0000052C) +#define NVC57E_SET_OFFSET_TMO_LUT_ORIGIN 31:0 +#define NVC57E_SET_CSC10CONTROL (0x0000053C) +#define NVC57E_SET_CSC10CONTROL_ENABLE 0:0 +#define NVC57E_SET_CSC10CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57E_SET_CSC10CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57E_SET_CSC10COEFFICIENT_C00 (0x00000540) +#define NVC57E_SET_CSC10COEFFICIENT_C00_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C01 (0x00000544) +#define NVC57E_SET_CSC10COEFFICIENT_C01_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C02 (0x00000548) +#define NVC57E_SET_CSC10COEFFICIENT_C02_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C03 (0x0000054C) +#define NVC57E_SET_CSC10COEFFICIENT_C03_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C10 (0x00000550) +#define NVC57E_SET_CSC10COEFFICIENT_C10_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C11 (0x00000554) +#define NVC57E_SET_CSC10COEFFICIENT_C11_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C12 (0x00000558) +#define NVC57E_SET_CSC10COEFFICIENT_C12_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C13 (0x0000055C) +#define NVC57E_SET_CSC10COEFFICIENT_C13_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C20 (0x00000560) +#define NVC57E_SET_CSC10COEFFICIENT_C20_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C21 (0x00000564) +#define NVC57E_SET_CSC10COEFFICIENT_C21_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C22 (0x00000568) +#define NVC57E_SET_CSC10COEFFICIENT_C22_VALUE 20:0 +#define NVC57E_SET_CSC10COEFFICIENT_C23 (0x0000056C) +#define NVC57E_SET_CSC10COEFFICIENT_C23_VALUE 20:0 +#define NVC57E_SET_CSC1LUT_CONTROL (0x00000580) +#define NVC57E_SET_CSC1LUT_CONTROL_INTERPOLATE 0:0 +#define NVC57E_SET_CSC1LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC57E_SET_CSC1LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC57E_SET_CSC1LUT_CONTROL_MIRROR 1:1 +#define NVC57E_SET_CSC1LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC57E_SET_CSC1LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC57E_SET_CSC1LUT_CONTROL_ENABLE 4:4 +#define NVC57E_SET_CSC1LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57E_SET_CSC1LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57E_SET_CSC1LUT_SEGMENT_SIZE (0x00000584) +#define NVC57E_SET_CSC1LUT_SEGMENT_SIZE_IDX 5:0 +#define NVC57E_SET_CSC1LUT_SEGMENT_SIZE_VALUE 18:16 +#define NVC57E_SET_CSC1LUT_ENTRY (0x00000588) +#define NVC57E_SET_CSC1LUT_ENTRY_IDX 10:0 +#define NVC57E_SET_CSC1LUT_ENTRY_VALUE 31:16 +#define NVC57E_SET_CSC11CONTROL (0x0000059C) +#define NVC57E_SET_CSC11CONTROL_ENABLE 0:0 +#define NVC57E_SET_CSC11CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC57E_SET_CSC11CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC57E_SET_CSC11COEFFICIENT_C00 (0x000005A0) +#define NVC57E_SET_CSC11COEFFICIENT_C00_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C01 (0x000005A4) +#define NVC57E_SET_CSC11COEFFICIENT_C01_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C02 (0x000005A8) +#define NVC57E_SET_CSC11COEFFICIENT_C02_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C03 (0x000005AC) +#define NVC57E_SET_CSC11COEFFICIENT_C03_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C10 (0x000005B0) +#define NVC57E_SET_CSC11COEFFICIENT_C10_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C11 (0x000005B4) +#define NVC57E_SET_CSC11COEFFICIENT_C11_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C12 (0x000005B8) +#define NVC57E_SET_CSC11COEFFICIENT_C12_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C13 (0x000005BC) +#define NVC57E_SET_CSC11COEFFICIENT_C13_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C20 (0x000005C0) +#define NVC57E_SET_CSC11COEFFICIENT_C20_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C21 (0x000005C4) +#define NVC57E_SET_CSC11COEFFICIENT_C21_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C22 (0x000005C8) +#define NVC57E_SET_CSC11COEFFICIENT_C22_VALUE 20:0 +#define NVC57E_SET_CSC11COEFFICIENT_C23 (0x000005CC) +#define NVC57E_SET_CSC11COEFFICIENT_C23_VALUE 20:0 +#define NVC57E_SET_CLAMP_RANGE (0x000005D0) +#define NVC57E_SET_CLAMP_RANGE_LOW 15:0 +#define NVC57E_SET_CLAMP_RANGE_HIGH 31:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC57e_h diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc57esw.h b/userspace/sdks/nv570/nvidia/inc/class/clc57esw.h new file mode 100644 index 0000000..8c106b4 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc57esw.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2009-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc57e_sw_h_ +#define _clc57e_sw_h_ + +/* This file is *not* auto-generated. */ + +#define NVC57E_WINDOWS_NOTIFY_RM (0x0000058C) +#define NVC57E_WINDOWS_NOTIFY_RM_VSYNC_STATE_CHANGE 0:0 +#define NVC57E_WINDOWS_NOTIFY_RM_VSYNC_STATE_CHANGE_FALSE (0x00000000) +#define NVC57E_WINDOWS_NOTIFY_RM_VSYNC_STATE_CHANGE_TRUE (0x00000001) +#define NVC57E_WINDOWS_NOTIFY_RM_VSYNC_STATE 1:1 +#define NVC57E_WINDOWS_NOTIFY_RM_VSYNC_STATE_OFF (0x00000000) +#define NVC57E_WINDOWS_NOTIFY_RM_VSYNC_STATE_ON (0x00000001) +#define NVC57E_WINDOWS_NOTIFY_RM_ASSOCIATED_HEAD 7:4 + +#define SwSetMClkSwitch Reserved05[1] + +#define NVC57E_SW_SET_MCLK_SWITCH (0x000002B4) +#define NVC57E_SW_SET_MCLK_SWITCH_ENABLE 0:0 +#define NVC57E_SW_SET_MCLK_SWITCH_ENABLE_FALSE (0x00000000) +#define NVC57E_SW_SET_MCLK_SWITCH_ENABLE_TRUE (0x00000001) + +#endif // _clc57e_sw_h_ + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc58b.h b/userspace/sdks/nv570/nvidia/inc/class/clc58b.h new file mode 100644 index 0000000..7dba2c6 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc58b.h @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc58b.finn +// + +#define TURING_VMMU_A (0xc58bU) /* finn: Evaluated from "TURING_VMMU_A_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* + * @brief NvAlloc parameters for TuringVmmuA class + * + * This class represents mapping between guest physical and system physical. + * Will also be used to represent VF specific state for a given guest. + * + * gfid [in] + * GFID of VF + */ + +#define TURING_VMMU_A_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc58bU) + +typedef struct TURING_VMMU_A_ALLOCATION_PARAMETERS { + NvHandle hHostVgpuDevice; +} TURING_VMMU_A_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc597.h b/userspace/sdks/nv570/nvidia/inc/class/clc597.h new file mode 100644 index 0000000..711dae1 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc597.h @@ -0,0 +1,4352 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_turing_a_h_ +#define _cl_turing_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl turing_a */ + +#include "nvtypes.h" + +#define TURING_A 0xC597 + +#define NVC597_SET_OBJECT 0x0000 +#define NVC597_SET_OBJECT_CLASS_ID 15:0 +#define NVC597_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC597_NO_OPERATION 0x0100 +#define NVC597_NO_OPERATION_V 31:0 + +#define NVC597_SET_NOTIFY_A 0x0104 +#define NVC597_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC597_SET_NOTIFY_B 0x0108 +#define NVC597_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC597_NOTIFY 0x010c +#define NVC597_NOTIFY_TYPE 31:0 +#define NVC597_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC597_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC597_WAIT_FOR_IDLE 0x0110 +#define NVC597_WAIT_FOR_IDLE_V 31:0 + +#define NVC597_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC597_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC597_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC597_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC597_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC597_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC597_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC597_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC597_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC597_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC597_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC597_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC597_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC597_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC597_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC597_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC597_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC597_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC597_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC597_SEND_GO_IDLE 0x013c +#define NVC597_SEND_GO_IDLE_V 31:0 + +#define NVC597_PM_TRIGGER 0x0140 +#define NVC597_PM_TRIGGER_V 31:0 + +#define NVC597_PM_TRIGGER_WFI 0x0144 +#define NVC597_PM_TRIGGER_WFI_V 31:0 + +#define NVC597_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC597_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC597_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC597_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC597_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC597_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC597_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC597_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC597_LINE_LENGTH_IN 0x0180 +#define NVC597_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC597_LINE_COUNT 0x0184 +#define NVC597_LINE_COUNT_VALUE 31:0 + +#define NVC597_OFFSET_OUT_UPPER 0x0188 +#define NVC597_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC597_OFFSET_OUT 0x018c +#define NVC597_OFFSET_OUT_VALUE 31:0 + +#define NVC597_PITCH_OUT 0x0190 +#define NVC597_PITCH_OUT_VALUE 31:0 + +#define NVC597_SET_DST_BLOCK_SIZE 0x0194 +#define NVC597_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC597_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC597_SET_DST_WIDTH 0x0198 +#define NVC597_SET_DST_WIDTH_V 31:0 + +#define NVC597_SET_DST_HEIGHT 0x019c +#define NVC597_SET_DST_HEIGHT_V 31:0 + +#define NVC597_SET_DST_DEPTH 0x01a0 +#define NVC597_SET_DST_DEPTH_V 31:0 + +#define NVC597_SET_DST_LAYER 0x01a4 +#define NVC597_SET_DST_LAYER_V 31:0 + +#define NVC597_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC597_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC597_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC597_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC597_LAUNCH_DMA 0x01b0 +#define NVC597_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC597_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC597_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC597_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC597_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC597_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC597_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC597_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC597_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC597_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC597_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC597_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC597_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC597_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC597_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC597_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC597_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC597_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC597_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC597_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC597_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC597_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC597_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC597_LOAD_INLINE_DATA 0x01b4 +#define NVC597_LOAD_INLINE_DATA_V 31:0 + +#define NVC597_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC597_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC597_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC597_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC597_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC597_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC597_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC597_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC597_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC597_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC597_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC597_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC597_RUN_DS_NOW 0x0200 +#define NVC597_RUN_DS_NOW_V 31:0 + +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC597_SET_GS_MODE 0x0208 +#define NVC597_SET_GS_MODE_TYPE 0:0 +#define NVC597_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVC597_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVC597_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC597_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC597_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC597_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC597_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC597_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_GS_DM_FIFO 0x0214 +#define NVC597_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC597_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC597_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC597_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC597_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC597_INVALIDATE_SHADER_CACHES 0x021c +#define NVC597_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC597_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC597_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC597_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC597_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC597_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC597_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC597_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC597_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC597_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC597_SET_INSTANCE_COUNT 0x0220 +#define NVC597_SET_INSTANCE_COUNT_V 31:0 + +#define NVC597_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVC597_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVC597_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC597_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVC597_SET_MME_VERSION 0x0234 +#define NVC597_SET_MME_VERSION_MAJOR 7:0 + +#define NVC597_SET_INDEX_BUFFER_SIZE_A 0x0238 +#define NVC597_SET_INDEX_BUFFER_SIZE_A_UPPER 7:0 + +#define NVC597_SET_INDEX_BUFFER_SIZE_B 0x023c +#define NVC597_SET_INDEX_BUFFER_SIZE_B_LOWER 31:0 + +#define NVC597_SET_ROOT_TABLE_VISIBILITY(i) (0x0240+(i)*4) +#define NVC597_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP0_ENABLE 1:0 +#define NVC597_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP1_ENABLE 5:4 +#define NVC597_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP2_ENABLE 9:8 +#define NVC597_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP3_ENABLE 13:12 +#define NVC597_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP4_ENABLE 17:16 + +#define NVC597_SET_DRAW_CONTROL_A 0x0260 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY 3:0 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_POINTS 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_LINES 0x00000001 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_QUADS 0x00000007 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_PATCH 0x0000000E +#define NVC597_SET_DRAW_CONTROL_A_PRIMITIVE_ID 4:4 +#define NVC597_SET_DRAW_CONTROL_A_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ID 6:5 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ID_FIRST 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC597_SET_DRAW_CONTROL_A_SPLIT_MODE 8:7 +#define NVC597_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC597_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC597_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE 9:9 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 +#define NVC597_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX 10:10 +#define NVC597_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_FALSE 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_TRUE 0x00000001 +#define NVC597_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX 11:11 +#define NVC597_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_FALSE 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_TRUE 0x00000001 + +#define NVC597_SET_DRAW_CONTROL_B 0x0264 +#define NVC597_SET_DRAW_CONTROL_B_INSTANCE_COUNT 31:0 + +#define NVC597_DRAW_INDEX_BUFFER_BEGIN_END_A 0x0268 +#define NVC597_DRAW_INDEX_BUFFER_BEGIN_END_A_FIRST 31:0 + +#define NVC597_DRAW_INDEX_BUFFER_BEGIN_END_B 0x026c +#define NVC597_DRAW_INDEX_BUFFER_BEGIN_END_B_COUNT 31:0 + +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_A 0x0270 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_A_START 31:0 + +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_B 0x0274 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_B_COUNT 31:0 + +#define NVC597_INVALIDATE_RASTER_CACHE_NO_WFI 0x027c +#define NVC597_INVALIDATE_RASTER_CACHE_NO_WFI_V 0:0 + +#define NVC597_SET_COLOR_RENDER_TO_ZETA_SURFACE 0x02b8 +#define NVC597_SET_COLOR_RENDER_TO_ZETA_SURFACE_V 0:0 +#define NVC597_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_FALSE 0x00000000 +#define NVC597_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_TRUE 0x00000001 + +#define NVC597_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION 0x02bc +#define NVC597_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V 0:0 +#define NVC597_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_FALSE 0x00000000 +#define NVC597_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_TRUE 0x00000001 + +#define NVC597_INCREMENT_SYNC_POINT 0x02c8 +#define NVC597_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC597_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC597_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC597_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC597_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC597_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC597_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC597_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC597_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC597_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC597_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVC597_DECOMPRESS_SURFACE 0x02e0 +#define NVC597_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC597_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC597_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC597_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC597_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC597_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC597_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC597_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC597_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC597_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC597_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC597_SET_ZCULL_SUBREGION 0x02e8 +#define NVC597_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC597_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC597_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC597_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC597_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC597_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC597_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC597_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC597_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC597_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC597_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC597_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC597_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC597_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC597_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC597_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC597_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC597_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC597_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC597_DRAW_ZERO_INDEX 0x0304 +#define NVC597_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC597_SET_L1_CONFIGURATION 0x0308 +#define NVC597_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC597_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC597_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC597_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC597_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC597_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC597_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC597_SET_SPA_VERSION 0x0310 +#define NVC597_SET_SPA_VERSION_MINOR 7:0 +#define NVC597_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC597_SET_TIMESLICE_BATCH_LIMIT 0x0314 +#define NVC597_SET_TIMESLICE_BATCH_LIMIT_BATCH_LIMIT 15:0 + +#define NVC597_SET_SNAP_GRID_LINE 0x0318 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC597_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC597_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC597_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC597_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC597_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC597_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC597_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC597_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC597_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC597_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC597_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC597_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC597_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC597_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC597_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC597_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC597_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC597_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC597_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC597_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC597_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC597_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC597_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC597_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC597_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC597_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC597_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC597_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC597_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC597_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC597_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC597_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC597_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC597_RESERVED_TG07 0x033c +#define NVC597_RESERVED_TG07_V 0:0 + +#define NVC597_RESERVED_TG08 0x0340 +#define NVC597_RESERVED_TG08_V 0:0 + +#define NVC597_RESERVED_TG09 0x0344 +#define NVC597_RESERVED_TG09_V 0:0 + +#define NVC597_RESERVED_TG10 0x0348 +#define NVC597_RESERVED_TG10_V 0:0 + +#define NVC597_RESERVED_TG11 0x034c +#define NVC597_RESERVED_TG11_V 0:0 + +#define NVC597_RESERVED_TG12 0x0350 +#define NVC597_RESERVED_TG12_V 0:0 + +#define NVC597_RESERVED_TG13 0x0354 +#define NVC597_RESERVED_TG13_V 0:0 + +#define NVC597_RESERVED_TG14 0x0358 +#define NVC597_RESERVED_TG14_V 0:0 + +#define NVC597_RESERVED_TG15 0x035c +#define NVC597_RESERVED_TG15_V 0:0 + +#define NVC597_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC597_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC597_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC597_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC597_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC597_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC597_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC597_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC597_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC597_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC597_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC597_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC597_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC597_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC597_SET_RASTER_ENABLE 0x037c +#define NVC597_SET_RASTER_ENABLE_V 0:0 +#define NVC597_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC597_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC597_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC597_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC597_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC597_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC597_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC597_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC597_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC597_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC597_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVC597_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVC597_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVC597_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVC597_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVC597_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVC597_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVC597_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVC597_SET_ROOT_TABLE_SELECTOR 0x0504 +#define NVC597_SET_ROOT_TABLE_SELECTOR_ROOT_TABLE 2:0 +#define NVC597_SET_ROOT_TABLE_SELECTOR_OFFSET 15:8 + +#define NVC597_LOAD_ROOT_TABLE 0x0508 +#define NVC597_LOAD_ROOT_TABLE_V 31:0 + +#define NVC597_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVC597_SET_MME_MEM_ADDRESS_A_UPPER 7:0 + +#define NVC597_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVC597_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVC597_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVC597_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVC597_MME_DMA_READ 0x055c +#define NVC597_MME_DMA_READ_LENGTH 31:0 + +#define NVC597_MME_DMA_READ_FIFOED 0x0560 +#define NVC597_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVC597_MME_DMA_WRITE 0x0564 +#define NVC597_MME_DMA_WRITE_LENGTH 31:0 + +#define NVC597_MME_DMA_REDUCTION 0x0568 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVC597_MME_DMA_SYSMEMBAR 0x056c +#define NVC597_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVC597_MME_DMA_SYNC 0x0570 +#define NVC597_MME_DMA_SYNC_VALUE 31:0 + +#define NVC597_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NVC597_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NVC597_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NVC597_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NVC597_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NVC597_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NVC597_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NVC597_SET_VERTEX_STREAM_SIZE_A(j) (0x0600+(j)*8) +#define NVC597_SET_VERTEX_STREAM_SIZE_A_UPPER 7:0 + +#define NVC597_SET_VERTEX_STREAM_SIZE_B(j) (0x0604+(j)*8) +#define NVC597_SET_VERTEX_STREAM_SIZE_B_LOWER 31:0 + +#define NVC597_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC597_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC597_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC597_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC597_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC597_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC597_SET_RASTER_INPUT 0x0740 +#define NVC597_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC597_SET_STREAM_OUTPUT 0x0744 +#define NVC597_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC597_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC597_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC597_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC597_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC597_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC597_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC597_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC597_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC597_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC597_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC597_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC597_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC597_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC597_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC597_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC597_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC597_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC597_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC597_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC597_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC597_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC597_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC597_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC597_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC597_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVC597_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC597_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC597_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC597_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC597_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC597_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC597_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC597_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC597_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC597_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC597_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC597_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC597_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC597_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC597_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC597_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC597_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC597_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC597_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC597_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC597_SET_ZCULL_STORAGE_B 0x07ec +#define NVC597_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC597_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC597_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC597_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC597_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC597_SET_ZT_READ_ONLY 0x07f8 +#define NVC597_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC597_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC597_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC597_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC597_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC597_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC597_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC597_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC597_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC597_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC597_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC597_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC597_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC597_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC597_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC597_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC597_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC597_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC597_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC597_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC597_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC597_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC597_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC597_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC597_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC597_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC597_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC597_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC597_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC597_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC597_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC597_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC597_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC597_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC597_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC597_SET_COLOR_TARGET_RESERVED_A(j) (0x0824+(j)*64) +#define NVC597_SET_COLOR_TARGET_RESERVED_A_V 0:0 + +#define NVC597_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC597_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC597_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC597_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC597_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC597_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC597_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC597_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC597_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC597_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC597_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC597_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC597_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC597_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC597_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC597_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC597_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC597_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC597_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC597_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC597_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC597_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC597_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC597_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC597_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC597_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC597_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC597_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC597_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC597_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC597_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC597_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC597_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC597_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC597_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC597_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC597_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC597_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC597_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC597_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC597_SET_STATISTICS_COUNTER 0x0d68 +#define NVC597_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC597_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC597_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC597_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC597_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC597_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC597_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC597_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC597_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC597_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC597_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC597_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC597_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC597_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC597_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC597_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC597_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVC597_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC597_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC597_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC597_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC597_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC597_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC597_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC597_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC597_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC597_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC597_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC597_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC597_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC597_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC597_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC597_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC597_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC597_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC597_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC597_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC597_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC597_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC597_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC597_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC597_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC597_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC597_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC597_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC597_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC597_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC597_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC597_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC597_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC597_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC597_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC597_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC597_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC597_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC597_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC597_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC597_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC597_SET_POLY_SMOOTH 0x0db4 +#define NVC597_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC597_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC597_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC597_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC597_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC597_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC597_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC597_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC597_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC597_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_PATCH 0x0dcc +#define NVC597_SET_PATCH_SIZE 7:0 + +#define NVC597_SET_ITERATED_BLEND 0x0dd0 +#define NVC597_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC597_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC597_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC597_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC597_SET_ZCULL_CRITERION 0x0dd8 +#define NVC597_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC597_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC597_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC597_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC597_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC597_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC597_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC597_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC597_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC597_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC597_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC597_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC597_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC597_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC597_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC597_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC597_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC597_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC597_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC597_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC597_SET_SCISSOR_ENABLE_V 0:0 +#define NVC597_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC597_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC597_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC597_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC597_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC597_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC597_SET_VPC_PERF_KNOB 0x0f14 +#define NVC597_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC597_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC597_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC597_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC597_PM_LOCAL_TRIGGER 0x0f18 +#define NVC597_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC597_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC597_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC597_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC597_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC597_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC597_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC597_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC597_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC597_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC597_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC597_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC597_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC597_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC597_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC597_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC597_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC597_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC597_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC597_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC597_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC597_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC597_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC597_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC597_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC597_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC597_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC597_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC597_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC597_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC597_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC597_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC597_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC597_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC597_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC597_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC597_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC597_SET_SAMPLE_MASK 0x0fa4 +#define NVC597_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC597_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC597_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC597_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC597_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC597_SET_CT_MRT_ENABLE 0x0fac +#define NVC597_SET_CT_MRT_ENABLE_V 0:0 +#define NVC597_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC597_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC597_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC597_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC597_SET_TIR 0x0fb4 +#define NVC597_SET_TIR_MODE 1:0 +#define NVC597_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC597_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC597_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC597_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC597_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC597_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC597_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC597_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC597_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC597_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC597_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC597_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC597_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC597_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC597_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC597_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC597_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC597_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC597_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC597_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_TIR_MODULATION 0x0fd4 +#define NVC597_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC597_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC597_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC597_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC597_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC597_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC597_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC597_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC597_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC597_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC597_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC597_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC597_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC597_SET_ZT_A 0x0fe0 +#define NVC597_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_ZT_B 0x0fe4 +#define NVC597_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_ZT_FORMAT 0x0fe8 +#define NVC597_SET_ZT_FORMAT_V 4:0 +#define NVC597_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC597_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC597_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC597_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC597_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC597_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC597_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC597_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC597_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC597_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC597_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC597_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC597_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC597_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC597_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC597_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC597_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC597_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC597_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC597_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC597_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC597_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC597_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC597_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC597_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC597_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC597_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC597_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC597_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC597_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC597_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC597_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC597_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC597_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC597_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC597_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC597_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC597_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC597_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC597_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC597_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC597_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC597_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC597_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC597_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC597_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD02 0x102c +#define NVC597_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC597_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC597_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC597_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC597_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC597_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC597_SET_SPARE_NOOP01 0x1044 +#define NVC597_SET_SPARE_NOOP01_V 31:0 + +#define NVC597_SET_SPARE_NOOP02 0x1048 +#define NVC597_SET_SPARE_NOOP02_V 31:0 + +#define NVC597_SET_SPARE_NOOP03 0x104c +#define NVC597_SET_SPARE_NOOP03_V 31:0 + +#define NVC597_SET_SPARE_NOOP04 0x1050 +#define NVC597_SET_SPARE_NOOP04_V 31:0 + +#define NVC597_SET_SPARE_NOOP05 0x1054 +#define NVC597_SET_SPARE_NOOP05_V 31:0 + +#define NVC597_SET_SPARE_NOOP06 0x1058 +#define NVC597_SET_SPARE_NOOP06_V 31:0 + +#define NVC597_SET_SPARE_NOOP07 0x105c +#define NVC597_SET_SPARE_NOOP07_V 31:0 + +#define NVC597_SET_SPARE_NOOP08 0x1060 +#define NVC597_SET_SPARE_NOOP08_V 31:0 + +#define NVC597_SET_SPARE_NOOP09 0x1064 +#define NVC597_SET_SPARE_NOOP09_V 31:0 + +#define NVC597_SET_SPARE_NOOP10 0x1068 +#define NVC597_SET_SPARE_NOOP10_V 31:0 + +#define NVC597_SET_SPARE_NOOP11 0x106c +#define NVC597_SET_SPARE_NOOP11_V 31:0 + +#define NVC597_SET_SPARE_NOOP12 0x1070 +#define NVC597_SET_SPARE_NOOP12_V 31:0 + +#define NVC597_SET_SPARE_NOOP13 0x1074 +#define NVC597_SET_SPARE_NOOP13_V 31:0 + +#define NVC597_SET_SPARE_NOOP14 0x1078 +#define NVC597_SET_SPARE_NOOP14_V 31:0 + +#define NVC597_SET_SPARE_NOOP15 0x107c +#define NVC597_SET_SPARE_NOOP15_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC597_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC597_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC597_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC597_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC597_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC597_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC597_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC597_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC597_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC597_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC597_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC597_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC597_UNBIND_ALL 0x10f4 +#define NVC597_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC597_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC597_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC597_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC597_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC597_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC597_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC597_NO_OPERATION_DATA_HI 0x110c +#define NVC597_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC597_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC597_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC597_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC597_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC597_PM_TRIGGER_END 0x1114 +#define NVC597_PM_TRIGGER_END_V 31:0 + +#define NVC597_SET_VERTEX_ID_BASE 0x1118 +#define NVC597_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC597_SET_STENCIL_COMPRESSION 0x111c +#define NVC597_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC597_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC597_SET_TIR_CONTROL 0x1130 +#define NVC597_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC597_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC597_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC597_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC597_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC597_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC597_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC597_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC597_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 + +#define NVC597_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC597_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC597_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC597_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC597_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC597_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC597_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC597_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC597_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC597_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC597_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC597_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC597_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC597_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC597_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC597_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC597_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC597_FLUSH_PENDING_WRITES 0x1144 +#define NVC597_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC597_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC597_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC597_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC597_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC597_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC597_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC597_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC597_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC597_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC597_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC597_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC597_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC597_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC597_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC597_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC597_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC597_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC597_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC597_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC597_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC597_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC597_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_SCREEN_STATE_MASK 0x1204 +#define NVC597_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC597_SET_ZT_SPARSE 0x1208 +#define NVC597_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC597_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC597_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC597_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_SET_CT_SELECT 0x121c +#define NVC597_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC597_SET_CT_SELECT_TARGET0 6:4 +#define NVC597_SET_CT_SELECT_TARGET1 9:7 +#define NVC597_SET_CT_SELECT_TARGET2 12:10 +#define NVC597_SET_CT_SELECT_TARGET3 15:13 +#define NVC597_SET_CT_SELECT_TARGET4 18:16 +#define NVC597_SET_CT_SELECT_TARGET5 21:19 +#define NVC597_SET_CT_SELECT_TARGET6 24:22 +#define NVC597_SET_CT_SELECT_TARGET7 27:25 + +#define NVC597_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC597_SET_ZT_SIZE_A 0x1228 +#define NVC597_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC597_SET_ZT_SIZE_B 0x122c +#define NVC597_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC597_SET_ZT_SIZE_C 0x1230 +#define NVC597_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC597_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC597_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC597_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC597_SET_SAMPLER_BINDING 0x1234 +#define NVC597_SET_SAMPLER_BINDING_V 0:0 +#define NVC597_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC597_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC597_DRAW_AUTO 0x123c +#define NVC597_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC597_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC597_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC597_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC597_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC597_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC597_SET_BACK_END_COPY_A 0x1264 +#define NVC597_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC597_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC597_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC597_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC597_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BACK_END_COPY_B 0x1268 +#define NVC597_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC597_SET_BACK_END_COPY_C 0x126c +#define NVC597_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC597_SET_BACK_END_COPY_D 0x1270 +#define NVC597_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC597_SET_BACK_END_COPY_E 0x1274 +#define NVC597_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC597_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC597_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVC597_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC597_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC597_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC597_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC597_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC597_CLEAR_ZCULL_REGION 0x12c8 +#define NVC597_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC597_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC597_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC597_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC597_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC597_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC597_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC597_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC597_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC597_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC597_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC597_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC597_SET_DEPTH_TEST 0x12cc +#define NVC597_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC597_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_FILL_MODE 0x12d0 +#define NVC597_SET_FILL_MODE_V 31:0 +#define NVC597_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC597_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC597_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC597_SET_SHADE_MODE 0x12d4 +#define NVC597_SET_SHADE_MODE_V 31:0 +#define NVC597_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC597_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC597_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC597_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC597_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC597_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC597_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC597_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC597_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC597_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC597_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC597_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_DEPTH_WRITE 0x12e8 +#define NVC597_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC597_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_ALPHA_TEST 0x12ec +#define NVC597_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC597_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC597_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC597_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC597_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC597_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC597_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC597_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC597_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC597_D3D_SET_CULL_MODE 0x1308 +#define NVC597_D3D_SET_CULL_MODE_V 31:0 +#define NVC597_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC597_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC597_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC597_SET_DEPTH_FUNC 0x130c +#define NVC597_SET_DEPTH_FUNC_V 31:0 +#define NVC597_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC597_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC597_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC597_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC597_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC597_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC597_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC597_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC597_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC597_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC597_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC597_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC597_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC597_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC597_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC597_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC597_SET_ALPHA_REF 0x1310 +#define NVC597_SET_ALPHA_REF_V 31:0 + +#define NVC597_SET_ALPHA_FUNC 0x1314 +#define NVC597_SET_ALPHA_FUNC_V 31:0 +#define NVC597_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC597_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC597_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC597_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC597_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC597_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC597_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC597_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC597_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC597_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC597_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC597_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC597_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC597_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC597_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC597_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC597_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC597_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC597_SET_BLEND_CONST_RED 0x131c +#define NVC597_SET_BLEND_CONST_RED_V 31:0 + +#define NVC597_SET_BLEND_CONST_GREEN 0x1320 +#define NVC597_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC597_SET_BLEND_CONST_BLUE 0x1324 +#define NVC597_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC597_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC597_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC597_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC597_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC597_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC597_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC597_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC597_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC597_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC597_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BLEND_COLOR_OP 0x1340 +#define NVC597_SET_BLEND_COLOR_OP_V 31:0 +#define NVC597_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC597_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC597_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC597_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC597_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC597_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC597_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC597_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC597_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC597_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_BLEND_ALPHA_OP 0x134c +#define NVC597_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC597_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC597_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC597_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC597_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC597_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC597_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC597_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC597_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC597_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC597_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC597_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC597_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC597_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC597_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC597_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BLEND(i) (0x1360+(i)*4) +#define NVC597_SET_BLEND_ENABLE 0:0 +#define NVC597_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_STENCIL_TEST 0x1380 +#define NVC597_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC597_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_STENCIL_OP_FAIL 0x1384 +#define NVC597_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC597_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC597_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC597_SET_STENCIL_OP_ZPASS 0x138c +#define NVC597_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC597_SET_STENCIL_FUNC 0x1390 +#define NVC597_SET_STENCIL_FUNC_V 31:0 +#define NVC597_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC597_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC597_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC597_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC597_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC597_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC597_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC597_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC597_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC597_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC597_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC597_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC597_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC597_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC597_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC597_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC597_SET_STENCIL_FUNC_REF 0x1394 +#define NVC597_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC597_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC597_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC597_SET_STENCIL_MASK 0x139c +#define NVC597_SET_STENCIL_MASK_V 7:0 + +#define NVC597_SET_DRAW_AUTO_START 0x13a4 +#define NVC597_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC597_SET_PS_SATURATE 0x13a8 +#define NVC597_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC597_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC597_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC597_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC597_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC597_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC597_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC597_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC597_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC597_SET_WINDOW_ORIGIN 0x13ac +#define NVC597_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC597_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC597_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC597_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC597_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC597_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC597_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC597_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC597_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC597_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC597_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC597_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC597_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC597_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC597_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC597_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC597_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC597_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC597_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC597_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC597_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC597_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC597_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC597_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC597_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC597_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC597_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC597_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC597_STORE_ZCULL 0x1464 +#define NVC597_STORE_ZCULL_V 0:0 + +#define NVC597_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC597_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC597_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC597_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC597_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC597_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC597_LOAD_ZCULL 0x1500 +#define NVC597_LOAD_ZCULL_V 0:0 + +#define NVC597_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC597_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC597_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC597_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC597_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC597_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC597_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC597_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC597_SET_USER_CLIP_ENABLE 0x1510 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC597_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC597_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC597_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_POINT_SIZE 0x1518 +#define NVC597_SET_POINT_SIZE_V 31:0 + +#define NVC597_SET_ZCULL_STATS 0x151c +#define NVC597_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC597_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_POINT_SPRITE 0x1520 +#define NVC597_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC597_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC597_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC597_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC597_CLEAR_REPORT_VALUE 0x1530 +#define NVC597_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC597_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC597_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC597_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC597_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC597_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC597_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVC597_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC597_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC597_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_ZT_SELECT 0x1538 +#define NVC597_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC597_SET_RENDER_ENABLE_A 0x1550 +#define NVC597_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_RENDER_ENABLE_B 0x1554 +#define NVC597_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_RENDER_ENABLE_C 0x1558 +#define NVC597_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC597_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC597_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC597_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC597_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC597_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC597_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC597_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC597_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC597_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC597_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC597_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC597_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC597_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC597_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC597_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC597_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_TEX_HEADER_POOL_C 0x157c +#define NVC597_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC597_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC597_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC597_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC597_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC597_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC597_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC597_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC597_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC597_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC597_SET_SRGB_WRITE 0x15b8 +#define NVC597_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC597_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_DEPTH_BIAS 0x15bc +#define NVC597_SET_DEPTH_BIAS_V 31:0 + +#define NVC597_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC597_SET_RT_LAYER 0x15cc +#define NVC597_SET_RT_LAYER_V 15:0 +#define NVC597_SET_RT_LAYER_CONTROL 16:16 +#define NVC597_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC597_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC597_SET_ANTI_ALIAS 0x15d0 +#define NVC597_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC597_SET_EDGE_FLAG 0x15e4 +#define NVC597_SET_EDGE_FLAG_V 0:0 +#define NVC597_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC597_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC597_DRAW_INLINE_INDEX 0x15e8 +#define NVC597_DRAW_INLINE_INDEX_V 31:0 + +#define NVC597_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC597_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC597_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC597_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC597_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC597_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC597_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC597_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC597_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC597_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC597_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC597_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC597_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC597_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC597_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC597_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC597_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC597_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC597_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC597_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC597_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC597_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC597_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC597_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC597_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC597_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC597_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC597_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC597_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC597_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC597_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC597_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC597_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC597_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC597_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC597_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC597_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC597_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC597_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC597_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC597_END 0x1614 +#define NVC597_END_V 0:0 + +#define NVC597_BEGIN 0x1618 +#define NVC597_BEGIN_OP 15:0 +#define NVC597_BEGIN_OP_POINTS 0x00000000 +#define NVC597_BEGIN_OP_LINES 0x00000001 +#define NVC597_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC597_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC597_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC597_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC597_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC597_BEGIN_OP_QUADS 0x00000007 +#define NVC597_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC597_BEGIN_OP_POLYGON 0x00000009 +#define NVC597_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC597_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC597_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_BEGIN_OP_PATCH 0x0000000E +#define NVC597_BEGIN_PRIMITIVE_ID 24:24 +#define NVC597_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC597_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC597_BEGIN_INSTANCE_ID 27:26 +#define NVC597_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC597_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC597_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC597_BEGIN_SPLIT_MODE 30:29 +#define NVC597_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC597_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC597_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC597_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC597_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVC597_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC597_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_VERTEX_ID_COPY 0x161c +#define NVC597_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC597_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC597_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC597_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC597_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC597_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC597_LOAD_PRIMITIVE_ID 0x1624 +#define NVC597_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC597_SET_SHADER_BASED_CULL 0x162c +#define NVC597_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC597_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC597_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC597_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_CLASS_VERSION 0x1638 +#define NVC597_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC597_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC597_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC597_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC597_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC597_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC597_SET_DA_OUTPUT 0x164c +#define NVC597_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC597_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC597_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC597_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC597_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_POINT_CENTER_MODE 0x165c +#define NVC597_SET_POINT_CENTER_MODE_V 31:0 +#define NVC597_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC597_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC597_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC597_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC597_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC597_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC597_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC597_SET_LINE_STIPPLE 0x166c +#define NVC597_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC597_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC597_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC597_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC597_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC597_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC597_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC597_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC597_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC597_SET_PROVOKING_VERTEX 0x1684 +#define NVC597_SET_PROVOKING_VERTEX_V 0:0 +#define NVC597_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC597_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC597_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC597_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC597_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_POLYGON_STIPPLE 0x168c +#define NVC597_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC597_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_SHADER_CONTROL 0x1690 +#define NVC597_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC597_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC597_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC597_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC597_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC597_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC597_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC597_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC597_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC597_CHECK_CLASS_VERSION 0x16a0 +#define NVC597_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC597_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC597_SET_SPH_VERSION 0x16a4 +#define NVC597_SET_SPH_VERSION_CURRENT 15:0 +#define NVC597_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC597_CHECK_SPH_VERSION 0x16a8 +#define NVC597_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC597_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC597_SET_SCG_GRAPHICS_PRIORITY 0x16bc +#define NVC597_SET_SCG_GRAPHICS_PRIORITY_PRIORITY 5:0 + +#define NVC597_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS(i) (0x16c0+(i)*4) +#define NVC597_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC597_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC597_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC597_SET_AAM_VERSION 0x1790 +#define NVC597_SET_AAM_VERSION_CURRENT 15:0 +#define NVC597_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC597_CHECK_AAM_VERSION 0x1794 +#define NVC597_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC597_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC597_SET_ZT_LAYER 0x179c +#define NVC597_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC597_SET_INDEX_BUFFER_A 0x17c8 +#define NVC597_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC597_SET_INDEX_BUFFER_B 0x17cc +#define NVC597_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC597_SET_INDEX_BUFFER_E 0x17d8 +#define NVC597_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC597_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC597_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC597_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC597_SET_INDEX_BUFFER_F 0x17dc +#define NVC597_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC597_DRAW_INDEX_BUFFER 0x17e0 +#define NVC597_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC597_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC597_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC597_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC597_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC597_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC597_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC597_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC597_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC597_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC597_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC597_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC597_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC597_OGL_SET_CULL 0x1918 +#define NVC597_OGL_SET_CULL_ENABLE 0:0 +#define NVC597_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC597_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC597_OGL_SET_FRONT_FACE 0x191c +#define NVC597_OGL_SET_FRONT_FACE_V 31:0 +#define NVC597_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC597_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC597_OGL_SET_CULL_FACE 0x1920 +#define NVC597_OGL_SET_CULL_FACE_V 31:0 +#define NVC597_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC597_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC597_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC597_SET_VIEWPORT_PIXEL 0x1924 +#define NVC597_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC597_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC597_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC597_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC597_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC597_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC597_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE 17:16 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_USE_FIELD_MIN_Z_ZERO_MAX_Z_ONE 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MIN_Z_MAX_Z 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_ZERO_ONE 0x00000002 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MINUS_INF_PLUS_INF 0x00000003 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC597_SET_USER_CLIP_OP 0x1940 +#define NVC597_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC597_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC597_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC597_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC597_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC597_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC597_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC597_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC597_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC597_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC597_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC597_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC597_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC597_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC597_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC597_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC597_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC597_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC597_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC597_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC597_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC597_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC597_INVALIDATE_ZCULL 0x1958 +#define NVC597_INVALIDATE_ZCULL_V 31:0 +#define NVC597_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC597_SET_ZCULL 0x1968 +#define NVC597_SET_ZCULL_Z_ENABLE 0:0 +#define NVC597_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC597_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_ZCULL_BOUNDS 0x196c +#define NVC597_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC597_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC597_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC597_ZCULL_SYNC 0x1978 +#define NVC597_ZCULL_SYNC_V 31:0 + +#define NVC597_SET_CLIP_ID_TEST 0x197c +#define NVC597_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC597_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC597_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC597_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC597_SET_CLIP_ID 0x1984 +#define NVC597_SET_CLIP_ID_V 31:0 + +#define NVC597_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC597_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC597_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC597_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC597_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC597_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC597_SET_LOGIC_OP 0x19c4 +#define NVC597_SET_LOGIC_OP_ENABLE 0:0 +#define NVC597_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC597_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC597_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC597_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC597_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC597_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC597_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC597_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC597_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC597_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC597_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC597_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC597_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC597_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC597_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC597_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC597_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC597_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC597_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC597_SET_Z_COMPRESSION 0x19cc +#define NVC597_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC597_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC597_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC597_CLEAR_SURFACE 0x19d0 +#define NVC597_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC597_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC597_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC597_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC597_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC597_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC597_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC597_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC597_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC597_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC597_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC597_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC597_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC597_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC597_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC597_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC597_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC597_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC597_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC597_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC597_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC597_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC597_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC597_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC597_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC597_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC597_PIPE_NOP 0x1a2c +#define NVC597_PIPE_NOP_V 31:0 + +#define NVC597_SET_SPARE00 0x1a30 +#define NVC597_SET_SPARE00_V 31:0 + +#define NVC597_SET_SPARE01 0x1a34 +#define NVC597_SET_SPARE01_V 31:0 + +#define NVC597_SET_SPARE02 0x1a38 +#define NVC597_SET_SPARE02_V 31:0 + +#define NVC597_SET_SPARE03 0x1a3c +#define NVC597_SET_SPARE03_V 31:0 + +#define NVC597_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC597_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC597_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC597_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC597_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC597_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC597_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC597_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC597_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC597_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC597_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC597_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC597_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC597_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC597_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC597_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC597_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC597_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC597_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC597_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC597_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC597_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC597_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC597_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC597_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC597_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC597_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC597_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC597_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC597_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC597_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC597_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC597_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC597_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC597_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC597_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC597_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC597_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC597_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC597_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC597_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC597_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC597_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC597_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC597_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC597_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC597_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC597_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC597_SET_PIPELINE_REGISTER_COUNT_V 8:0 + +#define NVC597_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC597_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC597_SET_PIPELINE_PROGRAM_ADDRESS_A(j) (0x2014+(j)*64) +#define NVC597_SET_PIPELINE_PROGRAM_ADDRESS_A_UPPER 7:0 + +#define NVC597_SET_PIPELINE_PROGRAM_ADDRESS_B(j) (0x2018+(j)*64) +#define NVC597_SET_PIPELINE_PROGRAM_ADDRESS_B_LOWER 31:0 + +#define NVC597_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVC597_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVC597_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC597_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC597_SET_FALCON00 0x2300 +#define NVC597_SET_FALCON00_V 31:0 + +#define NVC597_SET_FALCON01 0x2304 +#define NVC597_SET_FALCON01_V 31:0 + +#define NVC597_SET_FALCON02 0x2308 +#define NVC597_SET_FALCON02_V 31:0 + +#define NVC597_SET_FALCON03 0x230c +#define NVC597_SET_FALCON03_V 31:0 + +#define NVC597_SET_FALCON04 0x2310 +#define NVC597_SET_FALCON04_V 31:0 + +#define NVC597_SET_FALCON05 0x2314 +#define NVC597_SET_FALCON05_V 31:0 + +#define NVC597_SET_FALCON06 0x2318 +#define NVC597_SET_FALCON06_V 31:0 + +#define NVC597_SET_FALCON07 0x231c +#define NVC597_SET_FALCON07_V 31:0 + +#define NVC597_SET_FALCON08 0x2320 +#define NVC597_SET_FALCON08_V 31:0 + +#define NVC597_SET_FALCON09 0x2324 +#define NVC597_SET_FALCON09_V 31:0 + +#define NVC597_SET_FALCON10 0x2328 +#define NVC597_SET_FALCON10_V 31:0 + +#define NVC597_SET_FALCON11 0x232c +#define NVC597_SET_FALCON11_V 31:0 + +#define NVC597_SET_FALCON12 0x2330 +#define NVC597_SET_FALCON12_V 31:0 + +#define NVC597_SET_FALCON13 0x2334 +#define NVC597_SET_FALCON13_V 31:0 + +#define NVC597_SET_FALCON14 0x2338 +#define NVC597_SET_FALCON14_V 31:0 + +#define NVC597_SET_FALCON15 0x233c +#define NVC597_SET_FALCON15_V 31:0 + +#define NVC597_SET_FALCON16 0x2340 +#define NVC597_SET_FALCON16_V 31:0 + +#define NVC597_SET_FALCON17 0x2344 +#define NVC597_SET_FALCON17_V 31:0 + +#define NVC597_SET_FALCON18 0x2348 +#define NVC597_SET_FALCON18_V 31:0 + +#define NVC597_SET_FALCON19 0x234c +#define NVC597_SET_FALCON19_V 31:0 + +#define NVC597_SET_FALCON20 0x2350 +#define NVC597_SET_FALCON20_V 31:0 + +#define NVC597_SET_FALCON21 0x2354 +#define NVC597_SET_FALCON21_V 31:0 + +#define NVC597_SET_FALCON22 0x2358 +#define NVC597_SET_FALCON22_V 31:0 + +#define NVC597_SET_FALCON23 0x235c +#define NVC597_SET_FALCON23_V 31:0 + +#define NVC597_SET_FALCON24 0x2360 +#define NVC597_SET_FALCON24_V 31:0 + +#define NVC597_SET_FALCON25 0x2364 +#define NVC597_SET_FALCON25_V 31:0 + +#define NVC597_SET_FALCON26 0x2368 +#define NVC597_SET_FALCON26_V 31:0 + +#define NVC597_SET_FALCON27 0x236c +#define NVC597_SET_FALCON27_V 31:0 + +#define NVC597_SET_FALCON28 0x2370 +#define NVC597_SET_FALCON28_V 31:0 + +#define NVC597_SET_FALCON29 0x2374 +#define NVC597_SET_FALCON29_V 31:0 + +#define NVC597_SET_FALCON30 0x2378 +#define NVC597_SET_FALCON30_V 31:0 + +#define NVC597_SET_FALCON31 0x237c +#define NVC597_SET_FALCON31_V 31:0 + +#define NVC597_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC597_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC597_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC597_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC597_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC597_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC597_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC597_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC597_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC597_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC597_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC597_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC597_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC597_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC597_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC597_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC597_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC597_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC597_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC597_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC597_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC597_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC597_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC597_SET_TRAP_HANDLER_A 0x25f8 +#define NVC597_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC597_SET_TRAP_HANDLER_B 0x25fc +#define NVC597_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC597_SET_COLOR_CLAMP 0x2600 +#define NVC597_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC597_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC597_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BINDLESS_TEXTURE 0x2608 +#define NVC597_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVC597_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC597_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC597_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC597_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC597_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC597_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC597_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC597_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC597_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC597_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC597_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC597_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC597_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC597_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC597_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC597_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC597_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC597_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC597_CALL_MME_MACRO_V 31:0 + +#define NVC597_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC597_CALL_MME_DATA_V 31:0 + +#endif /* _cl_turing_a_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc5b5.h b/userspace/sdks/nv570/nvidia/inc/class/clc5b5.h new file mode 100644 index 0000000..cc3633e --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc5b5.h @@ -0,0 +1,282 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clc5b5_h_ +#define _clc5b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define TURING_DMA_COPY_A (0x0000C5B5) + +#define NVC5B5_NOP (0x00000100) +#define NVC5B5_NOP_PARAMETER 31:0 +#define NVC5B5_PM_TRIGGER (0x00000140) +#define NVC5B5_PM_TRIGGER_V 31:0 +#define NVC5B5_SET_SEMAPHORE_A (0x00000240) +#define NVC5B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC5B5_SET_SEMAPHORE_B (0x00000244) +#define NVC5B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC5B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC5B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC5B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC5B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC5B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC5B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC5B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC5B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC5B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC5B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC5B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC5B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC5B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC5B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC5B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC5B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC5B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC5B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC5B5_SET_SRC_PHYS_MODE_BASIC_KIND 5:2 +#define NVC5B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC5B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC5B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC5B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC5B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC5B5_SET_DST_PHYS_MODE_BASIC_KIND 5:2 +#define NVC5B5_LAUNCH_DMA (0x00000300) +#define NVC5B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC5B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC5B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC5B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC5B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC5B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC5B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC5B5_LAUNCH_DMA_FLUSH_TYPE 25:25 +#define NVC5B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000) +#define NVC5B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE (0x00000003) +#define NVC5B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC5B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC5B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC5B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC5B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC5B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC5B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC5B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC5B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC5B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC5B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC5B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC5B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC5B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC5B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC5B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC5B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC5B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC5B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC5B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC5B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC5B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC5B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC5B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC5B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC5B5_LAUNCH_DMA_SRC_BYPASS_L2 20:20 +#define NVC5B5_LAUNCH_DMA_SRC_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC5B5_LAUNCH_DMA_SRC_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC5B5_LAUNCH_DMA_DST_BYPASS_L2 21:21 +#define NVC5B5_LAUNCH_DMA_DST_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC5B5_LAUNCH_DMA_DST_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC5B5_LAUNCH_DMA_VPRMODE 23:22 +#define NVC5B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVC5B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC5B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC5B5_LAUNCH_DMA_DISABLE_PLC 26:26 +#define NVC5B5_LAUNCH_DMA_DISABLE_PLC_FALSE (0x00000000) +#define NVC5B5_LAUNCH_DMA_DISABLE_PLC_TRUE (0x00000001) +#define NVC5B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 +#define NVC5B5_OFFSET_IN_UPPER (0x00000400) +#define NVC5B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC5B5_OFFSET_IN_LOWER (0x00000404) +#define NVC5B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC5B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC5B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC5B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC5B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC5B5_PITCH_IN (0x00000410) +#define NVC5B5_PITCH_IN_VALUE 31:0 +#define NVC5B5_PITCH_OUT (0x00000414) +#define NVC5B5_PITCH_OUT_VALUE 31:0 +#define NVC5B5_LINE_LENGTH_IN (0x00000418) +#define NVC5B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC5B5_LINE_COUNT (0x0000041C) +#define NVC5B5_LINE_COUNT_VALUE 31:0 +#define NVC5B5_SET_REMAP_CONST_A (0x00000700) +#define NVC5B5_SET_REMAP_CONST_A_V 31:0 +#define NVC5B5_SET_REMAP_CONST_B (0x00000704) +#define NVC5B5_SET_REMAP_CONST_B_V 31:0 +#define NVC5B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC5B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC5B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC5B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC5B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC5B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC5B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC5B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC5B5_SET_DST_WIDTH (0x00000710) +#define NVC5B5_SET_DST_WIDTH_V 31:0 +#define NVC5B5_SET_DST_HEIGHT (0x00000714) +#define NVC5B5_SET_DST_HEIGHT_V 31:0 +#define NVC5B5_SET_DST_DEPTH (0x00000718) +#define NVC5B5_SET_DST_DEPTH_V 31:0 +#define NVC5B5_SET_DST_LAYER (0x0000071C) +#define NVC5B5_SET_DST_LAYER_V 31:0 +#define NVC5B5_SET_DST_ORIGIN (0x00000720) +#define NVC5B5_SET_DST_ORIGIN_X 15:0 +#define NVC5B5_SET_DST_ORIGIN_Y 31:16 +#define NVC5B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC5B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC5B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC5B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC5B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC5B5_SET_SRC_WIDTH (0x0000072C) +#define NVC5B5_SET_SRC_WIDTH_V 31:0 +#define NVC5B5_SET_SRC_HEIGHT (0x00000730) +#define NVC5B5_SET_SRC_HEIGHT_V 31:0 +#define NVC5B5_SET_SRC_DEPTH (0x00000734) +#define NVC5B5_SET_SRC_DEPTH_V 31:0 +#define NVC5B5_SET_SRC_LAYER (0x00000738) +#define NVC5B5_SET_SRC_LAYER_V 31:0 +#define NVC5B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC5B5_SET_SRC_ORIGIN_X 15:0 +#define NVC5B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC5B5_SRC_ORIGIN_X (0x00000744) +#define NVC5B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC5B5_SRC_ORIGIN_Y (0x00000748) +#define NVC5B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC5B5_DST_ORIGIN_X (0x0000074C) +#define NVC5B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC5B5_DST_ORIGIN_Y (0x00000750) +#define NVC5B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC5B5_PM_TRIGGER_END (0x00001114) +#define NVC5B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc5b5_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc5b5sw.h b/userspace/sdks/nv570/nvidia/inc/class/clc5b5sw.h new file mode 100644 index 0000000..0295824 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc5b5sw.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc5b5sw.finn +// + + + +// +// Using VERSION_0 will cause the API to interpret +// engineType as a CE engine instance. This allows +// for backward compatibility with 85B5sw and 90B5sw. +// +#define NVC5B5_ALLOCATION_PARAMETERS_VERSION_0 0 + +// +// Using VERSION_1 will cause the API to interpret +// engineType as an NV2080_ENGINE_TYPE ordinal. +// +#define NVC5B5_ALLOCATION_PARAMETERS_VERSION_1 1 + +#define NVC5B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc5b5U) + +typedef struct NVC5B5_ALLOCATION_PARAMETERS { + NvU32 version; + NvU32 engineType; +} NVC5B5_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc5c0.h b/userspace/sdks/nv570/nvidia/inc/class/clc5c0.h new file mode 100644 index 0000000..51e0837 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc5c0.h @@ -0,0 +1,732 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_turing_compute_a_h_ +#define _cl_turing_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl turing_compute_a */ + +#include "nvtypes.h" + +#define TURING_COMPUTE_A 0xC5C0 + +#define NVC5C0_SET_OBJECT 0x0000 +#define NVC5C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC5C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC5C0_NO_OPERATION 0x0100 +#define NVC5C0_NO_OPERATION_V 31:0 + +#define NVC5C0_SET_NOTIFY_A 0x0104 +#define NVC5C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC5C0_SET_NOTIFY_B 0x0108 +#define NVC5C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_NOTIFY 0x010c +#define NVC5C0_NOTIFY_TYPE 31:0 +#define NVC5C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC5C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC5C0_WAIT_FOR_IDLE 0x0110 +#define NVC5C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC5C0_SEND_GO_IDLE 0x013c +#define NVC5C0_SEND_GO_IDLE_V 31:0 + +#define NVC5C0_PM_TRIGGER 0x0140 +#define NVC5C0_PM_TRIGGER_V 31:0 + +#define NVC5C0_PM_TRIGGER_WFI 0x0144 +#define NVC5C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC5C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC5C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC5C0_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC5C0_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC5C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC5C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC5C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC5C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC5C0_LINE_LENGTH_IN 0x0180 +#define NVC5C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC5C0_LINE_COUNT 0x0184 +#define NVC5C0_LINE_COUNT_VALUE 31:0 + +#define NVC5C0_OFFSET_OUT_UPPER 0x0188 +#define NVC5C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC5C0_OFFSET_OUT 0x018c +#define NVC5C0_OFFSET_OUT_VALUE 31:0 + +#define NVC5C0_PITCH_OUT 0x0190 +#define NVC5C0_PITCH_OUT_VALUE 31:0 + +#define NVC5C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC5C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC5C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC5C0_SET_DST_WIDTH 0x0198 +#define NVC5C0_SET_DST_WIDTH_V 31:0 + +#define NVC5C0_SET_DST_HEIGHT 0x019c +#define NVC5C0_SET_DST_HEIGHT_V 31:0 + +#define NVC5C0_SET_DST_DEPTH 0x01a0 +#define NVC5C0_SET_DST_DEPTH_V 31:0 + +#define NVC5C0_SET_DST_LAYER 0x01a4 +#define NVC5C0_SET_DST_LAYER_V 31:0 + +#define NVC5C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC5C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC5C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC5C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC5C0_LAUNCH_DMA 0x01b0 +#define NVC5C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC5C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC5C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC5C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC5C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC5C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC5C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC5C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC5C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC5C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC5C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC5C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC5C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC5C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC5C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC5C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC5C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC5C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC5C0_LOAD_INLINE_DATA 0x01b4 +#define NVC5C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC5C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC5C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC5C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC5C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC5C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC5C0_SET_SM_SCG_CONTROL 0x01e8 +#define NVC5C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS 0:0 +#define NVC5C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE 0x00000000 +#define NVC5C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE 0x00000001 + +#define NVC5C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC5C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC5C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC5C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC5C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC5C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC5C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC5C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC5C0_PERFMON_TRANSFER 0x0210 +#define NVC5C0_PERFMON_TRANSFER_V 31:0 + +#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_A 0x0214 +#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_A_ADDRESS_UPPER 7:0 + +#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_B 0x0218 +#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC5C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC5C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC5C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC5C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC5C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC5C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC5C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC5C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC5C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC5C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC5C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC5C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC5C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC5C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC5C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC5C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC5C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC5C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC5C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC5C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC5C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC5C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC5C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC5C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC5C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC5C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC5C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC5C0_SET_SCG_CONTROL 0x0270 +#define NVC5C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 +#define NVC5C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 +#define NVC5C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 +#define NVC5C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 +#define NVC5C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 + +#define NVC5C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC5C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC5C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC5C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC5C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC5C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC5C0_SET_QMD_VERSION 0x0288 +#define NVC5C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC5C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC5C0_CHECK_QMD_VERSION 0x0290 +#define NVC5C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC5C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC5C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC5C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL 0x029c +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_CONSTANT_BUFFER_MASK 7:0 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE 8:8 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE 12:12 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE 16:16 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE 20:20 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE 24:24 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_TRUE 0x00000001 + +#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC5C0_SCG_HYSTERESIS_CONTROL 0x02a8 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 + +#define NVC5C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC5C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC5C0_SEND_PCAS_A 0x02b4 +#define NVC5C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC5C0_SEND_PCAS_B 0x02b8 +#define NVC5C0_SEND_PCAS_B_FROM 23:0 +#define NVC5C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC5C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC5C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC5C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC5C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC5C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC5C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC5C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC5C0_SET_SKED_CACHE_CONTROL 0x02cc +#define NVC5C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID 0:0 +#define NVC5C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE 0x00000000 +#define NVC5C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE 0x00000001 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC5C0_SET_SPA_VERSION 0x0310 +#define NVC5C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC5C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC5C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC5C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC5C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC5C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC5C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC5C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC5C0_SET_FALCON00 0x0500 +#define NVC5C0_SET_FALCON00_V 31:0 + +#define NVC5C0_SET_FALCON01 0x0504 +#define NVC5C0_SET_FALCON01_V 31:0 + +#define NVC5C0_SET_FALCON02 0x0508 +#define NVC5C0_SET_FALCON02_V 31:0 + +#define NVC5C0_SET_FALCON03 0x050c +#define NVC5C0_SET_FALCON03_V 31:0 + +#define NVC5C0_SET_FALCON04 0x0510 +#define NVC5C0_SET_FALCON04_V 31:0 + +#define NVC5C0_SET_FALCON05 0x0514 +#define NVC5C0_SET_FALCON05_V 31:0 + +#define NVC5C0_SET_FALCON06 0x0518 +#define NVC5C0_SET_FALCON06_V 31:0 + +#define NVC5C0_SET_FALCON07 0x051c +#define NVC5C0_SET_FALCON07_V 31:0 + +#define NVC5C0_SET_FALCON08 0x0520 +#define NVC5C0_SET_FALCON08_V 31:0 + +#define NVC5C0_SET_FALCON09 0x0524 +#define NVC5C0_SET_FALCON09_V 31:0 + +#define NVC5C0_SET_FALCON10 0x0528 +#define NVC5C0_SET_FALCON10_V 31:0 + +#define NVC5C0_SET_FALCON11 0x052c +#define NVC5C0_SET_FALCON11_V 31:0 + +#define NVC5C0_SET_FALCON12 0x0530 +#define NVC5C0_SET_FALCON12_V 31:0 + +#define NVC5C0_SET_FALCON13 0x0534 +#define NVC5C0_SET_FALCON13_V 31:0 + +#define NVC5C0_SET_FALCON14 0x0538 +#define NVC5C0_SET_FALCON14_V 31:0 + +#define NVC5C0_SET_FALCON15 0x053c +#define NVC5C0_SET_FALCON15_V 31:0 + +#define NVC5C0_SET_FALCON16 0x0540 +#define NVC5C0_SET_FALCON16_V 31:0 + +#define NVC5C0_SET_FALCON17 0x0544 +#define NVC5C0_SET_FALCON17_V 31:0 + +#define NVC5C0_SET_FALCON18 0x0548 +#define NVC5C0_SET_FALCON18_V 31:0 + +#define NVC5C0_SET_FALCON19 0x054c +#define NVC5C0_SET_FALCON19_V 31:0 + +#define NVC5C0_SET_FALCON20 0x0550 +#define NVC5C0_SET_FALCON20_V 31:0 + +#define NVC5C0_SET_FALCON21 0x0554 +#define NVC5C0_SET_FALCON21_V 31:0 + +#define NVC5C0_SET_FALCON22 0x0558 +#define NVC5C0_SET_FALCON22_V 31:0 + +#define NVC5C0_SET_FALCON23 0x055c +#define NVC5C0_SET_FALCON23_V 31:0 + +#define NVC5C0_SET_FALCON24 0x0560 +#define NVC5C0_SET_FALCON24_V 31:0 + +#define NVC5C0_SET_FALCON25 0x0564 +#define NVC5C0_SET_FALCON25_V 31:0 + +#define NVC5C0_SET_FALCON26 0x0568 +#define NVC5C0_SET_FALCON26_V 31:0 + +#define NVC5C0_SET_FALCON27 0x056c +#define NVC5C0_SET_FALCON27_V 31:0 + +#define NVC5C0_SET_FALCON28 0x0570 +#define NVC5C0_SET_FALCON28_V 31:0 + +#define NVC5C0_SET_FALCON29 0x0574 +#define NVC5C0_SET_FALCON29_V 31:0 + +#define NVC5C0_SET_FALCON30 0x0578 +#define NVC5C0_SET_FALCON30_V 31:0 + +#define NVC5C0_SET_FALCON31 0x057c +#define NVC5C0_SET_FALCON31_V 31:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC5C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC5C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC5C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC5C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS(i) (0x0da0+(i)*4) +#define NVC5C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC5C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC5C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC5C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC5C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC5C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC5C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC5C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC5C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC5C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC5C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC5C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC5C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC5C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC5C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC5C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC5C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC5C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC5C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC5C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC5C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC5C0_PIPE_NOP 0x1a2c +#define NVC5C0_PIPE_NOP_V 31:0 + +#define NVC5C0_SET_SPARE00 0x1a30 +#define NVC5C0_SET_SPARE00_V 31:0 + +#define NVC5C0_SET_SPARE01 0x1a34 +#define NVC5C0_SET_SPARE01_V 31:0 + +#define NVC5C0_SET_SPARE02 0x1a38 +#define NVC5C0_SET_SPARE02_V 31:0 + +#define NVC5C0_SET_SPARE03 0x1a3c +#define NVC5C0_SET_SPARE03_V 31:0 + +#define NVC5C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC5C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC5C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC5C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC5C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC5C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC5C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC5C0_SET_TRAP_HANDLER_A 0x25f8 +#define NVC5C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC5C0_SET_TRAP_HANDLER_B 0x25fc +#define NVC5C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC5C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC5C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC5C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC5C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC5C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC5C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC5C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC5C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC5C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC5C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC5C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_turing_compute_a_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc637.h b/userspace/sdks/nv570/nvidia/inc/class/clc637.h new file mode 100644 index 0000000..65bed26 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc637.h @@ -0,0 +1,62 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc637.finn +// + +#define AMPERE_SMC_PARTITION_REF (0xc637U) /* finn: Evaluated from "NVC637_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +// +// This swizzId can be used by root clients like tools for device level +// profiling +// +#define NVC637_DEVICE_PROFILING_SWIZZID (0xFFFFFFFE) + +// +// TODO: Deprecate NVC637_DEVICE_LEVEL_SWIZZID once all the clients are moved to +// NVC637_DEVICE_PROFILING_SWIZZID +// +#define NVC637_DEVICE_LEVEL_SWIZZID NVC637_DEVICE_PROFILING_SWIZZID + +/* NvRmAlloc parameters */ +#define NVC637_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc637U) + +typedef struct NVC637_ALLOCATION_PARAMETERS { + // + // capDescriptor is a file descriptor for unix RM clients, but a void + // pointer for windows RM clients. + // + // capDescriptor is transparent to RM clients i.e. RM's user-mode shim + // populates this field on behalf of clients. + // + NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8); + + NvU32 swizzId; +} NVC637_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc638.h b/userspace/sdks/nv570/nvidia/inc/class/clc638.h new file mode 100644 index 0000000..73b3fda --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc638.h @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc638.finn +// + +#define AMPERE_SMC_EXEC_PARTITION_REF (0xc638U) /* finn: Evaluated from "NVC638_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* NvRmAlloc parameters */ +#define NVC638_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc638U) + +typedef struct NVC638_ALLOCATION_PARAMETERS { + // + // capDescriptor is a file descriptor for unix RM clients, but a void + // pointer for windows RM clients. + // + // capDescriptor is transparent to RM clients i.e. RM's user-mode shim + // populates this field on behalf of clients. + // + NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8); + + NvU32 execPartitionId; +} NVC638_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc639.h b/userspace/sdks/nv570/nvidia/inc/class/clc639.h new file mode 100644 index 0000000..d589de7 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc639.h @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc639.finn +// + +#define AMPERE_SMC_CONFIG_SESSION (0xc639U) /* finn: Evaluated from "NVC639_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* NvRmAlloc parameters */ +#define NVC639_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc639U) + +typedef struct NVC639_ALLOCATION_PARAMETERS { + // + // capDescriptor is a file descriptor for unix RM clients, but a void + // pointer for windows RM clients. + // + // capDescriptor is transparent to RM clients i.e. RM's user-mode shim + // populates this field on behalf of clients. + // + NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8); +} NVC639_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc640.h b/userspace/sdks/nv570/nvidia/inc/class/clc640.h new file mode 100644 index 0000000..214a45c --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc640.h @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc640.finn +// + +#define AMPERE_SMC_MONITOR_SESSION (0xc640U) /* finn: Evaluated from "NVC640_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* NvRmAlloc parameters */ +#define NVC640_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc640U) + +typedef struct NVC640_ALLOCATION_PARAMETERS { + // + // capDescriptor is a file descriptor for unix RM clients, but a void + // pointer for windows RM clients. + // + // capDescriptor is transparent to RM clients i.e. RM's user-mode shim + // populates this field on behalf of clients. + // + NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8); +} NVC640_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc661.h b/userspace/sdks/nv570/nvidia/inc/class/clc661.h new file mode 100644 index 0000000..d9f8a48 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc661.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clc661_h__ +#define __gh100_clc661_h__ +#define HOPPER_USERMODE_A (0xc661) +#endif // __gh100_clc661_h__ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc670.h b/userspace/sdks/nv570/nvidia/inc/class/clc670.h new file mode 100644 index 0000000..e46194d --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc670.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc670.finn +// + +#define NVC670_DISPLAY (0xc670U) /* finn: Evaluated from "NVC670_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NVC670_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc670U) + +typedef struct NVC670_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numDsis; // Number of DSIs in this chip/display +} NVC670_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc671.h b/userspace/sdks/nv570/nvidia/inc/class/clc671.h new file mode 100644 index 0000000..11f77d7 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc671.h @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc671_h_ +#define _clc671_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC671_DISP_SF_USER (0x000C671) + +typedef volatile struct _clc671_tag0 { + NvU32 dispSfUserOffset[0x400]; +} _NvC671DispSfUser, NvC671DispSfUserMap; + +#define NVC671_SF_HDMI_INFO_IDX_GENERIC_INFOFRAME 0x00000001 /* */ +#define NVC671_SF_HDMI_INFO_IDX_VSI 0x00000004 /* */ +#define NVC671_SF_HDMI_INFO_CTRL(i,j) (0x000E0000-0x000E0000+(i)*1024+(j)*64) /* RW-4A */ +#define NVC671_SF_HDMI_INFO_CTRL__SIZE_1 4 /* */ +#define NVC671_SF_HDMI_INFO_CTRL__SIZE_2 5 /* */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _clc671_h_ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc673.h b/userspace/sdks/nv570/nvidia/inc/class/clc673.h new file mode 100644 index 0000000..7ae1334 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc673.h @@ -0,0 +1,399 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc673_h_ +#define _clc673_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC673_DISP_CAPABILITIES 0xC673 + +typedef volatile struct _clc673_tag0 { + NvU32 dispCapabilities[0x400]; +} _NvC673DispCapabilities,NvC673DispCapabilities_Map ; + + +#define NVC673_SYS_CAP 0x0 /* RW-4R */ +#define NVC673_SYS_CAP_HEAD0_EXISTS 0:0 /* RWIVF */ +#define NVC673_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_HEAD1_EXISTS 1:1 /* RWIVF */ +#define NVC673_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_HEAD2_EXISTS 2:2 /* RWIVF */ +#define NVC673_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_HEAD3_EXISTS 3:3 /* RWIVF */ +#define NVC673_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_HEAD4_EXISTS 4:4 /* RWIVF */ +#define NVC673_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_HEAD5_EXISTS 5:5 /* RWIVF */ +#define NVC673_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_HEAD6_EXISTS 6:6 /* RWIVF */ +#define NVC673_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_HEAD7_EXISTS 7:7 /* RWIVF */ +#define NVC673_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NVC673_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */ +#define NVC673_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR0_EXISTS 8:8 /* RWIVF */ +#define NVC673_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR1_EXISTS 9:9 /* RWIVF */ +#define NVC673_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR2_EXISTS 10:10 /* RWIVF */ +#define NVC673_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR3_EXISTS 11:11 /* RWIVF */ +#define NVC673_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR4_EXISTS 12:12 /* RWIVF */ +#define NVC673_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR5_EXISTS 13:13 /* RWIVF */ +#define NVC673_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR6_EXISTS 14:14 /* RWIVF */ +#define NVC673_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR7_EXISTS 15:15 /* RWIVF */ +#define NVC673_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* RWIVF */ +#define NVC673_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */ +#define NVC673_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_DSI0_EXISTS 20:20 /* RWIVF */ +#define NVC673_SYS_CAP_DSI0_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_DSI0_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_DSI1_EXISTS 21:21 /* RWIVF */ +#define NVC673_SYS_CAP_DSI1_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_DSI1_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_DSI2_EXISTS 22:22 /* RWIVF */ +#define NVC673_SYS_CAP_DSI2_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_DSI2_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_DSI3_EXISTS 23:23 /* RWIVF */ +#define NVC673_SYS_CAP_DSI3_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_DSI3_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_SYS_CAP_DSI_EXISTS(i) (20+(i)):(20+(i)) /* RWIVF */ +#define NVC673_SYS_CAP_DSI_EXISTS__SIZE_1 4 /* */ +#define NVC673_SYS_CAP_DSI_EXISTS_NO 0x00000000 /* RW--V */ +#define NVC673_SYS_CAP_DSI_EXISTS_YES 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA 0x10 /* RW-4R */ +#define NVC673_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES 15:0 /* RWIUF */ +#define NVC673_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH 17:16 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B 0x00000002 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B 0x00000003 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_ROTATION 18:18 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_ROTATION_FALSE 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_ROTATION_TRUE 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_PLANAR 19:19 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_PLANAR_FALSE 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_PLANAR_TRUE 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_VGA 20:20 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION 21:21 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_FALSE 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_TRUE 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MSCG 22:22 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MSCG_FALSE 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MSCG_TRUE 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH 23:23 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_FALSE 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_TRUE 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT 26:26 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION 31:30 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B 0x00000002 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B 0x00000003 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC 0x18 /* RW-4R */ +#define NVC673_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE 1:0 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_32B 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_64B 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_128B 0x00000002 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_256B 0x00000003 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED 6:4 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_NONE 0x00000000 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_TWO 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_FOUR 0x00000002 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_EIGHT 0x00000003 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_SIXTEEN 0x00000004 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR 11:11 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_FALSE 0x00000000 /* RWI-V */ +#define NVC673_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_TRUE 0x00000001 /* RW--V */ +#define NVC673_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP 12:12 /* RWIVF */ +#define NVC673_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_FALSE 0x00000000 /* RWI-V */ +#define NVC673_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA(i) (0x680+(i)*32) /* RW-4A */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA__SIZE_1 8 /* */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT 16:16 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT 17:17 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT 18:18 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT 19:19 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT 20:20 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT 21:21 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT 22:22 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT 23:23 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT 24:24 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB(i) (0x684+(i)*32) /* RW-4A */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB__SIZE_1 8 /* */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_VGA 0:0 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_VGA_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_VGA_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGSZ 9:6 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGNR 12:10 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT 15:15 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC(i) (0x688+(i)*32) /* RW-4A */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC__SIZE_1 8 /* */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_OCSC0_PRECISION 4:0 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_OCSC1_PRECISION 12:8 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP 13:13 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_SF_PRECISION 20:16 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_CI_PRECISION 24:21 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB 25:25 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPD(i) (0x68c+(i)*32) /* RW-4A */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPD__SIZE_1 8 /* */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE(i) (0x690+(i)*32) /* RW-4A */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE__SIZE_1 8 /* */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE_DSC_RATEBUFSIZE 3:0 /* RWIUF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE_DSC_LINEBUFSIZE 13:8 /* RWIUF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422 16:16 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420 17:17 /* RWIVF */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_TRUE 0x00000001 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_FALSE 0x00000000 /* RW--V */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPF(i) (0x694+(i)*32) /* RW-4A */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPF__SIZE_1 8 /* */ +#define NVC673_POSTCOMP_HEAD_HDR_CAPF_VFILTER_MAX_PIXELS 15:0 /* RWIVF */ +#define NVC673_SOR_CAP(i) (0x144+(i)*8) /* RW-4A */ +#define NVC673_SOR_CAP__SIZE_1 8 /* */ +#define NVC673_SOR_CAP_SINGLE_LVDS_18 0:0 /* RWIVF */ +#define NVC673_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_SINGLE_LVDS_24 1:1 /* RWIVF */ +#define NVC673_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_DUAL_LVDS_18 2:2 /* RWIVF */ +#define NVC673_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_DUAL_LVDS_24 3:3 /* RWIVF */ +#define NVC673_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_SINGLE_TMDS_A 8:8 /* RWIVF */ +#define NVC673_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_SINGLE_TMDS_B 9:9 /* RWIVF */ +#define NVC673_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_DUAL_TMDS 11:11 /* RWIVF */ +#define NVC673_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* RWIVF */ +#define NVC673_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_SDI 16:16 /* RWIVF */ +#define NVC673_SOR_CAP_SDI_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_SDI_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_DP_A 24:24 /* RWIVF */ +#define NVC673_SOR_CAP_DP_A_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_DP_A_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_DP_B 25:25 /* RWIVF */ +#define NVC673_SOR_CAP_DP_B_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_DP_B_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_DP_INTERLACE 26:26 /* RWIVF */ +#define NVC673_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_DP_8_LANES 27:27 /* RWIVF */ +#define NVC673_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* RW--V */ +#define NVC673_SOR_CAP_HDMI_FRL 28:28 /* RWIVF */ +#define NVC673_SOR_CAP_HDMI_FRL_FALSE 0x00000000 /* RW--V */ +#define NVC673_SOR_CAP_HDMI_FRL_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA(i) (0x780+(i)*32) /* RW-4A */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA__SIZE_1 32 /* */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH 13:10 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT 16:16 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT 17:17 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT 18:18 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT 19:19 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT 20:20 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT 21:21 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT 22:22 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT 23:23 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT 24:24 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB(i) (0x784+(i)*32) /* RW-4A */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB__SIZE_1 32 /* */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION 4:0 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ 9:6 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR 12:10 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT 15:15 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC(i) (0x788+(i)*32) /* RW-4A */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC__SIZE_1 32 /* */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION 4:0 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGSZ 9:6 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGNR 12:10 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT 15:15 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION 20:16 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP 21:21 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD(i) (0x78c+(i)*32) /* RW-4A */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD__SIZE_1 32 /* */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ 3:0 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR 6:4 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD 8:8 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT 9:9 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION 16:12 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION 20:17 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB 21:21 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA 22:22 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE(i) (0x790+(i)*32) /* RW-4A */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE__SIZE_1 32 /* */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION 4:0 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP 5:5 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGSZ 9:6 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGNR 12:10 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD 14:14 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT 15:15 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION 20:16 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP 21:21 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPF(i) (0x794+(i)*32) /* RW-4A */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPF__SIZE_1 32 /* */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */ +#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */ + +#ifdef __cplusplus +}; +#endif /* extern C */ +#endif //_clc673_h_ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc67a.h b/userspace/sdks/nv570/nvidia/inc/class/clc67a.h new file mode 100644 index 0000000..ab6f1d4 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc67a.h @@ -0,0 +1,181 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + + +#ifndef _clc67a__h_ +#define _clc67a__h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC67A_CURSOR_IMM_CHANNEL_PIO (0x0000C67A) + +typedef volatile struct _clc67a_tag0 { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x7D]; + NvV32 Update; // 0x00000200 - 0x00000203 + NvV32 SetInterlockFlags; // 0x00000204 - 0x00000207 + NvV32 SetCursorHotSpotPointOut[2]; // 0x00000208 - 0x0000020F + NvV32 SetWindowInterlockFlags; // 0x00000210 - 0x00000213 + NvV32 Reserved02[0x37B]; +} NVC67ADispCursorImmControlPio; + +#define NVC67A_FREE (0x00000008) +#define NVC67A_FREE_COUNT 5:0 +#define NVC67A_UPDATE (0x00000200) +#define NVC67A_SET_INTERLOCK_FLAGS (0x00000204) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC67A_SET_CURSOR_HOT_SPOT_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVC67A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0 +#define NVC67A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS (0x00000210) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC67A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc67a_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc67b.h b/userspace/sdks/nv570/nvidia/inc/class/clc67b.h new file mode 100644 index 0000000..c9779a0 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc67b.h @@ -0,0 +1,66 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + + + +#ifndef _clC67b_h_ +#define _clC67b_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC67B_WINDOW_IMM_CHANNEL_DMA (0x0000C67B) + +// dma opcode instructions +#define NVC67B_DMA +#define NVC67B_DMA_OPCODE 31:29 +#define NVC67B_DMA_OPCODE_METHOD 0x00000000 +#define NVC67B_DMA_OPCODE_JUMP 0x00000001 +#define NVC67B_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC67B_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC67B_DMA_METHOD_COUNT 27:18 +#define NVC67B_DMA_METHOD_OFFSET 13:2 +#define NVC67B_DMA_DATA 31:0 +#define NVC67B_DMA_DATA_NOP 0x00000000 +#define NVC67B_DMA_JUMP_OFFSET 11:2 +#define NVC67B_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVC67B_PUT (0x00000000) +#define NVC67B_PUT_PTR 9:0 +#define NVC67B_GET (0x00000004) +#define NVC67B_GET_PTR 9:0 +#define NVC67B_UPDATE (0x00000200) +#define NVC67B_UPDATE_INTERLOCK_WITH_WINDOW 1:1 +#define NVC67B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC67B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC67B_SET_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVC67B_SET_POINT_OUT_X 15:0 +#define NVC67B_SET_POINT_OUT_Y 31:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC67b_h diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc67d.h b/userspace/sdks/nv570/nvidia/inc/class/clc67d.h new file mode 100644 index 0000000..dd2a4f6 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc67d.h @@ -0,0 +1,1339 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + + + +#ifndef _clC67d_h_ +#define _clC67d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC67D_CORE_CHANNEL_DMA (0x0000C67D) + +#define NV_DISP_NOTIFIER 0x00000000 +#define NV_DISP_NOTIFIER_SIZEOF 0x00000010 +#define NV_DISP_NOTIFIER__0 0x00000000 +#define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFIER__0_FIELD 8:8 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE 9:9 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001 +#define NV_DISP_NOTIFIER__0_R1 15:10 +#define NV_DISP_NOTIFIER__0_R2 23:16 +#define NV_DISP_NOTIFIER__0_R3 29:24 +#define NV_DISP_NOTIFIER__0_STATUS 31:30 +#define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002 +#define NV_DISP_NOTIFIER__1 0x00000001 +#define NV_DISP_NOTIFIER__1_R4 31:0 +#define NV_DISP_NOTIFIER__2 0x00000002 +#define NV_DISP_NOTIFIER__2_TIMESTAMP_LO 31:0 +#define NV_DISP_NOTIFIER__3 0x00000003 +#define NV_DISP_NOTIFIER__3_TIMESTAMP_HI 31:0 + + +// dma opcode instructions +#define NVC67D_DMA +#define NVC67D_DMA_OPCODE 31:29 +#define NVC67D_DMA_OPCODE_METHOD 0x00000000 +#define NVC67D_DMA_OPCODE_JUMP 0x00000001 +#define NVC67D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC67D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC67D_DMA_METHOD_COUNT 27:18 +#define NVC67D_DMA_METHOD_OFFSET 13:2 +#define NVC67D_DMA_DATA 31:0 +#define NVC67D_DMA_DATA_NOP 0x00000000 +#define NVC67D_DMA_JUMP_OFFSET 11:2 +#define NVC67D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// if cap SUPPORT_FLEXIBLE_WIN_MAPPING is FALSE, this define can be used to obtain which head a window is mapped to +#define NVC37D_WINDOW_MAPPED_TO_HEAD(w) ((w)>>1) +#define NVC37D_GET_VALID_WINDOWMASK_FOR_HEAD(h) ((1<<((h)*2)) | (1<<((h)*2+1))) + +// class methods +#define NVC67D_PUT (0x00000000) +#define NVC67D_PUT_PTR 9:0 +#define NVC67D_GET (0x00000004) +#define NVC67D_GET_PTR 9:0 +#define NVC67D_UPDATE (0x00000200) +#define NVC67D_UPDATE_SPECIAL_HANDLING 21:20 +#define NVC67D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NVC67D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NVC67D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NVC67D_UPDATE_SPECIAL_HANDLING_REASON 19:12 +#define NVC67D_UPDATE_INHIBIT_INTERRUPTS 24:24 +#define NVC67D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NVC67D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NVC67D_UPDATE_RELEASE_ELV 0:0 +#define NVC67D_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC67D_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC67D_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC67D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC67D_SET_CONTEXT_DMA_NOTIFIER (0x00000208) +#define NVC67D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NVC67D_SET_NOTIFIER_CONTROL (0x0000020C) +#define NVC67D_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC67D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC67D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC67D_SET_NOTIFIER_CONTROL_OFFSET 11:4 +#define NVC67D_SET_NOTIFIER_CONTROL_NOTIFY 12:12 +#define NVC67D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NVC67D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NVC67D_SET_CONTROL (0x00000210) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN(i) ((i)+0):((i)+0) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN__SIZE_1 4 +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN_DISABLE (0x00000000) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN_ENABLE (0x00000001) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN0 0:0 +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN0_DISABLE (0x00000000) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN0_ENABLE (0x00000001) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN1 1:1 +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN1_DISABLE (0x00000000) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN1_ENABLE (0x00000001) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN2 2:2 +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN2_DISABLE (0x00000000) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN2_ENABLE (0x00000001) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN3 3:3 +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN3_DISABLE (0x00000000) +#define NVC67D_SET_CONTROL_FLIP_LOCK_PIN3_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS (0x00000218) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+0):((i)+0) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC67D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS (0x0000021C) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC67D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVC67D_GET_RG_SCAN_LINE(b) (0x00000220 + (b)*0x00000004) +#define NVC67D_GET_RG_SCAN_LINE_LINE 15:0 +#define NVC67D_GET_RG_SCAN_LINE_VBLANK 16:16 +#define NVC67D_GET_RG_SCAN_LINE_VBLANK_FALSE (0x00000000) +#define NVC67D_GET_RG_SCAN_LINE_VBLANK_TRUE (0x00000001) +#define NVC67D_SET_GET_BLANKING_CTRL(b) (0x00000240 + (b)*0x00000004) +#define NVC67D_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NVC67D_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NVC67D_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NVC67D_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NVC67D_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NVC67D_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) + +#define NVC67D_SOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK 7:0 +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVC67D_SOR_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVC67D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NVC67D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NVC67D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NVC67D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NVC67D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NVC67D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NVC67D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NVC67D_SOR_SET_CONTROL_PROTOCOL_HDMI_FRL (0x0000000C) +#define NVC67D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NVC67D_SOR_SET_CONTROL_DE_SYNC_POLARITY 16:16 +#define NVC67D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC67D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC67D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NVC67D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NVC67D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NVC67D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NVC67D_SOR_SET_CUSTOM_REASON(a) (0x00000304 + (a)*0x00000020) +#define NVC67D_SOR_SET_CUSTOM_REASON_CODE 31:0 +#define NVC67D_SOR_SET_SW_SPARE_A(a) (0x00000308 + (a)*0x00000020) +#define NVC67D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NVC67D_SOR_SET_SW_SPARE_B(a) (0x0000030C + (a)*0x00000020) +#define NVC67D_SOR_SET_SW_SPARE_B_CODE 31:0 + +#define NVC67D_DSI_SET_CONTROL(a) (0x00000500 + (a)*0x00000020) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK 7:0 +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVC67D_DSI_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVC67D_DSI_SET_CUSTOM_REASON(a) (0x00000504 + (a)*0x00000020) +#define NVC67D_DSI_SET_CUSTOM_REASON_CODE 31:0 +#define NVC67D_DSI_SET_SW_SPARE_A(a) (0x00000508 + (a)*0x00000020) +#define NVC67D_DSI_SET_SW_SPARE_A_CODE 31:0 +#define NVC67D_DSI_SET_SW_SPARE_B(a) (0x0000050C + (a)*0x00000020) +#define NVC67D_DSI_SET_SW_SPARE_B_CODE 31:0 + +#define NVC67D_WINDOW_SET_CONTROL(a) (0x00001000 + (a)*0x00000080) +#define NVC67D_WINDOW_SET_CONTROL_OWNER 3:0 +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD(i) (0x00000000 +(i)) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD__SIZE_1 8 +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD0 (0x00000000) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD1 (0x00000001) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD2 (0x00000002) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD3 (0x00000003) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD4 (0x00000004) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD5 (0x00000005) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD6 (0x00000006) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_HEAD7 (0x00000007) +#define NVC67D_WINDOW_SET_CONTROL_OWNER_NONE (0x0000000F) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0x00000080) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a) (0x00001008 + (a)*0x00000080) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR(a) (0x0000100C + (a)*0x00000080) +#define NVC67D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVC67D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a) (0x00001010 + (a)*0x00000080) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_MAX_PIXELS_FETCHED_PER_LINE 14:0 +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED 16:16 +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED 28:28 +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS 22:20 +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED 24:24 +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED 30:30 +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED_FALSE (0x00000000) +#define NVC67D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED_TRUE (0x00000001) + +#define NVC67D_HEAD_SET_PROCAMP(a) (0x00002000 + (a)*0x00000400) +#define NVC67D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NVC67D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NVC67D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NVC67D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NVC67D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003) +#define NVC67D_HEAD_SET_PROCAMP_CHROMA_LPF 3:3 +#define NVC67D_HEAD_SET_PROCAMP_CHROMA_LPF_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_PROCAMP_CHROMA_LPF_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_PROCAMP_CHROMA_DOWN_V 4:4 +#define NVC67D_HEAD_SET_PROCAMP_CHROMA_DOWN_V_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_PROCAMP_CHROMA_DOWN_V_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 28:28 +#define NVC67D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NVC67D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00002004 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 2:2 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 3:3 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 7:4 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000003) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000004) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000005) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000006) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000007) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000008) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_444 (0x00000009) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444NP (0x0000000A) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 24:24 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 23:12 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN 31:26 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN0 (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN1 (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN2 (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN3 (0x00000003) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN4 (0x00000004) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN5 (0x00000005) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN6 (0x00000006) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN7 (0x00000007) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN8 (0x00000008) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN9 (0x00000009) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN10 (0x0000000A) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN11 (0x0000000B) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN12 (0x0000000C) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN13 (0x0000000D) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN14 (0x0000000E) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN15 (0x0000000F) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN16 (0x00000010) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN17 (0x00000011) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN18 (0x00000012) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN19 (0x00000013) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN20 (0x00000014) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN21 (0x00000015) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN22 (0x00000016) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN23 (0x00000017) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN24 (0x00000018) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN25 (0x00000019) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN26 (0x0000001A) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN27 (0x0000001B) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN28 (0x0000001C) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN29 (0x0000001D) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN30 (0x0000001E) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN31 (0x0000001F) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_NONE (0x0000003F) +#define NVC67D_HEAD_SET_CONTROL(a) (0x00002008 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CONTROL_STRUCTURE 1:0 +#define NVC67D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE 2:2 +#define NVC67D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_NORMAL (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_YUV420PACKER 3:3 +#define NVC67D_HEAD_SET_CONTROL_YUV420PACKER_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_YUV420PACKER_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE 11:10 +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_NO_LOCK (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN 8:4 +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_LOCKOUT_WINDOW 15:12 +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_MODE 23:22 +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_NO_LOCK (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_FRAME_LOCK (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_MODE_RASTER_LOCK (0x00000003) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN 20:16 +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC67D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN 28:24 +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16 +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000003) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000004) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000005) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000006) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000007) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000008) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000009) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000B) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000C) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000D) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000E) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000F) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x00000010) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC67D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE 30:30 +#define NVC67D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_SLAVE_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE 31:31 +#define NVC67D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_MASTER_STEREO_LOCK_MODE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x0000200C + (a)*0x00000400) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC67D_HEAD_SET_PIXEL_REORDER_CONTROL(a) (0x00002010 + (a)*0x00000400) +#define NVC67D_HEAD_SET_PIXEL_REORDER_CONTROL_BANK_WIDTH 13:0 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00002014 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVC67D_HEAD_SET_DITHER_CONTROL(a) (0x00002018 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NVC67D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_DITHER_CONTROL_BITS 5:4 +#define NVC67D_HEAD_SET_DITHER_CONTROL_BITS_TO_6_BITS (0x00000000) +#define NVC67D_HEAD_SET_DITHER_CONTROL_BITS_TO_8_BITS (0x00000001) +#define NVC67D_HEAD_SET_DITHER_CONTROL_BITS_TO_10_BITS (0x00000002) +#define NVC67D_HEAD_SET_DITHER_CONTROL_BITS_TO_12_BITS (0x00000003) +#define NVC67D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE 2:2 +#define NVC67D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_DITHER_CONTROL_MODE 10:8 +#define NVC67D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NVC67D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NVC67D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NVC67D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NVC67D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NVC67D_HEAD_SET_DITHER_CONTROL_MODE_ROUND (0x00000005) +#define NVC67D_HEAD_SET_DITHER_CONTROL_PHASE 13:12 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x0000201C + (a)*0x00000400) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 0:0 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING 4:4 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 9:8 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NVC67D_HEAD_SET_DISPLAY_ID(a,b) (0x00002020 + (a)*0x00000400 + (b)*0x00000004) +#define NVC67D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00002028 + (a)*0x00000400) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC67D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC67D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR(a) (0x0000202C + (a)*0x00000400) +#define NVC67D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_HORIZONTAL 15:0 +#define NVC67D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_VERTICAL 31:16 +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS(a) (0x00002030 + (a)*0x00000400) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR 2:0 +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_NONE (0x00000000) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W32_H32 (0x00000001) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W64_H64 (0x00000002) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W128_H128 (0x00000003) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W256_H256 (0x00000004) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED 4:4 +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_FALSE (0x00000000) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_TRUE (0x00000001) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS 14:12 +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED 8:8 +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED 16:16 +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED_FALSE (0x00000000) +#define NVC67D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED_TRUE (0x00000001) +#define NVC67D_HEAD_SET_STALL_LOCK(a) (0x00002034 + (a)*0x00000400) +#define NVC67D_HEAD_SET_STALL_LOCK_ENABLE 0:0 +#define NVC67D_HEAD_SET_STALL_LOCK_ENABLE_FALSE (0x00000000) +#define NVC67D_HEAD_SET_STALL_LOCK_ENABLE_TRUE (0x00000001) +#define NVC67D_HEAD_SET_STALL_LOCK_MODE 2:2 +#define NVC67D_HEAD_SET_STALL_LOCK_MODE_CONTINUOUS (0x00000000) +#define NVC67D_HEAD_SET_STALL_LOCK_MODE_ONE_SHOT (0x00000001) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN 8:4 +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC67D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC67D_HEAD_SET_STALL_LOCK_UNSTALL_MODE 12:12 +#define NVC67D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_CRASH_LOCK (0x00000000) +#define NVC67D_HEAD_SET_STALL_LOCK_UNSTALL_MODE_LINE_LOCK (0x00000001) +#define NVC67D_HEAD_SET_STALL_LOCK_TEPOLARITY 14:14 +#define NVC67D_HEAD_SET_STALL_LOCK_TEPOLARITY_POSITIVE_TRUE (0x00000000) +#define NVC67D_HEAD_SET_STALL_LOCK_TEPOLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC67D_HEAD_SET_STALL_LOCK_UNSTALL_SYNC_ADVANCE 25:16 +#define NVC67D_HEAD_SET_LOCK_CHAIN(a) (0x00002044 + (a)*0x00000400) +#define NVC67D_HEAD_SET_LOCK_CHAIN_POSITION 3:0 +#define NVC67D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x00002048 + (a)*0x00000400) +#define NVC67D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NVC67D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NVC67D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x0000204C + (a)*0x00000400) +#define NVC67D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NVC67D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NVC67D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x00002058 + (a)*0x00000400) +#define NVC67D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NVC67D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NVC67D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x0000205C + (a)*0x00000400) +#define NVC67D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NVC67D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NVC67D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000400) +#define NVC67D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NVC67D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NVC67D_HEAD_SET_RASTER_SYNC_END(a) (0x00002068 + (a)*0x00000400) +#define NVC67D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NVC67D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NVC67D_HEAD_SET_RASTER_BLANK_END(a) (0x0000206C + (a)*0x00000400) +#define NVC67D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NVC67D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NVC67D_HEAD_SET_RASTER_BLANK_START(a) (0x00002070 + (a)*0x00000400) +#define NVC67D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NVC67D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NVC67D_HEAD_SET_OVERSCAN_COLOR(a) (0x00002078 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OVERSCAN_COLOR_RED_CR 9:0 +#define NVC67D_HEAD_SET_OVERSCAN_COLOR_GREEN_Y 19:10 +#define NVC67D_HEAD_SET_OVERSCAN_COLOR_BLUE_CB 29:20 +#define NVC67D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR(a) (0x0000207C + (a)*0x00000400) +#define NVC67D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_RED_CR 9:0 +#define NVC67D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_GREEN_Y 19:10 +#define NVC67D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_BLUE_CB 29:20 +#define NVC67D_HEAD_SET_HDMI_CTRL(a) (0x00002080 + (a)*0x00000400) +#define NVC67D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NVC67D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NVC67D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NVC67D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_STEREO3D (0x00000002) +#define NVC67D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NVC67D_HEAD_SET_CONTEXT_DMA_CURSOR(a,b) (0x00002088 + (a)*0x00000400 + (b)*0x00000004) +#define NVC67D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0 +#define NVC67D_HEAD_SET_OFFSET_CURSOR(a,b) (0x00002090 + (a)*0x00000400 + (b)*0x00000004) +#define NVC67D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0 +#define NVC67D_HEAD_SET_PRESENT_CONTROL_CURSOR(a) (0x00002098 + (a)*0x00000400) +#define NVC67D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE 0:0 +#define NVC67D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_MONO (0x00000000) +#define NVC67D_HEAD_SET_PRESENT_CONTROL_CURSOR_MODE_STEREO (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_CURSOR(a) (0x0000209C + (a)*0x00000400) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_FORMAT 7:0 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_SIZE 9:8 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 19:12 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 27:20 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION(a) (0x000020A0 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_K1 7:0 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT 11:8 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT 15:12 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_ZERO (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE 16:16 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_BLEND (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_XOR (0x00000001) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS 20:20 +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00002180 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NVC67D_HEAD_SET_CRC_CONTROL(a) (0x00002184 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 5:0 +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_0 (0x00000000) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_1 (0x00000001) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_2 (0x00000002) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_3 (0x00000003) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_4 (0x00000004) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_5 (0x00000005) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_6 (0x00000006) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_7 (0x00000007) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_8 (0x00000008) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_9 (0x00000009) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_10 (0x0000000A) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_11 (0x0000000B) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_12 (0x0000000C) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_13 (0x0000000D) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_14 (0x0000000E) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_15 (0x0000000F) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_16 (0x00000010) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_17 (0x00000011) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_18 (0x00000012) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_19 (0x00000013) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_20 (0x00000014) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_21 (0x00000015) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_22 (0x00000016) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_23 (0x00000017) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_24 (0x00000018) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_25 (0x00000019) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_26 (0x0000001A) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_27 (0x0000001B) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_28 (0x0000001C) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_29 (0x0000001D) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_30 (0x0000001E) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_31 (0x0000001F) +#define NVC67D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000020) +#define NVC67D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 8:8 +#define NVC67D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NVC67D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC 19:12 +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_NONE (0x00000000) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SF (0x00000030) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR__SIZE_1 8 +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR0 (0x00000050) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR1 (0x00000051) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR2 (0x00000052) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR3 (0x00000053) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR4 (0x00000054) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR5 (0x00000055) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR6 (0x00000056) +#define NVC67D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR7 (0x00000057) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC 27:20 +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_NONE (0x00000000) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SF (0x00000030) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR__SIZE_1 8 +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR0 (0x00000050) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR1 (0x00000051) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR2 (0x00000052) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR3 (0x00000053) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR4 (0x00000054) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR5 (0x00000055) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR6 (0x00000056) +#define NVC67D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR7 (0x00000057) +#define NVC67D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 9:9 +#define NVC67D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_PRESENT_CONTROL(a) (0x0000218C + (a)*0x00000400) +#define NVC67D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 0:0 +#define NVC67D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NVC67D_HEAD_SET_SW_SPARE_A(a) (0x00002194 + (a)*0x00000400) +#define NVC67D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NVC67D_HEAD_SET_SW_SPARE_B(a) (0x00002198 + (a)*0x00000400) +#define NVC67D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NVC67D_HEAD_SET_SW_SPARE_C(a) (0x0000219C + (a)*0x00000400) +#define NVC67D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NVC67D_HEAD_SET_SW_SPARE_D(a) (0x000021A0 + (a)*0x00000400) +#define NVC67D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NVC67D_HEAD_SET_DISPLAY_RATE(a) (0x000021A8 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DISPLAY_RATE_RUN_MODE 0:0 +#define NVC67D_HEAD_SET_DISPLAY_RATE_RUN_MODE_CONTINUOUS (0x00000000) +#define NVC67D_HEAD_SET_DISPLAY_RATE_RUN_MODE_ONE_SHOT (0x00000001) +#define NVC67D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_INTERVAL 25:4 +#define NVC67D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH 2:2 +#define NVC67D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_DISPLAY_RATE_MIN_REFRESH_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_CONTEXT_DMA_RG_REL_SEMAPHORE(a,b) (0x000021AC + (a)*0x00000400 + (b)*0x00000004) +#define NVC67D_HEAD_SET_CONTEXT_DMA_RG_REL_SEMAPHORE_HANDLE 31:0 +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL(a,b) (0x000021CC + (a)*0x00000400 + (b)*0x00000004) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_OFFSET 7:0 +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE 14:14 +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE_WRITE (0x00000000) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_REL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE 10:10 +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE_ONE_TIME (0x00000000) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RUN_MODE_CONTINUOUS (0x00000001) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_CONTROL_RASTER_LINE 30:16 +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_VALUE(a,b) (0x000021EC + (a)*0x00000400 + (b)*0x00000004) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_VALUE 31:0 +#define NVC67D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE(a) (0x00002214 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVC67D_HEAD_SET_OUTPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVC67D_HEAD_SET_MIN_FRAME_IDLE(a) (0x00002218 + (a)*0x00000400) +#define NVC67D_HEAD_SET_MIN_FRAME_IDLE_LEADING_RASTER_LINES 14:0 +#define NVC67D_HEAD_SET_MIN_FRAME_IDLE_TRAILING_RASTER_LINES 30:16 +#define NVC67D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED(a) (0x00002220 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED_ALPHA 7:0 +#define NVC67D_HEAD_SET_DESKTOP_COLOR_ALPHA_RED_RED 31:16 +#define NVC67D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE(a) (0x00002224 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE_GREEN 15:0 +#define NVC67D_HEAD_SET_DESKTOP_COLOR_GREEN_BLUE_BLUE 31:16 +#define NVC67D_HEAD_SET_CURSOR_COLOR_NORM_SCALE(a) (0x00002228 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CURSOR_COLOR_NORM_SCALE_VALUE 15:0 +#define NVC67D_HEAD_SET_XOR_BLEND_FACTOR(a) (0x0000222C + (a)*0x00000400) +#define NVC67D_HEAD_SET_XOR_BLEND_FACTOR_LOG2PEAK_LUMINANCE 3:0 +#define NVC67D_HEAD_SET_XOR_BLEND_FACTOR_S1 16:4 +#define NVC67D_HEAD_SET_XOR_BLEND_FACTOR_S2 30:18 +#define NVC67D_HEAD_SET_CLAMP_RANGE_GREEN(a) (0x00002238 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CLAMP_RANGE_GREEN_LOW 11:0 +#define NVC67D_HEAD_SET_CLAMP_RANGE_GREEN_HIGH 27:16 +#define NVC67D_HEAD_SET_CLAMP_RANGE_RED_BLUE(a) (0x0000223C + (a)*0x00000400) +#define NVC67D_HEAD_SET_CLAMP_RANGE_RED_BLUE_LOW 11:0 +#define NVC67D_HEAD_SET_CLAMP_RANGE_RED_BLUE_HIGH 27:16 +#define NVC67D_HEAD_SET_OCSC0CONTROL(a) (0x00002240 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0CONTROL_ENABLE 0:0 +#define NVC67D_HEAD_SET_OCSC0CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_OCSC0CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C00(a) (0x00002244 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C00_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C01(a) (0x00002248 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C01_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C02(a) (0x0000224C + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C02_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C03(a) (0x00002250 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C03_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C10(a) (0x00002254 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C10_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C11(a) (0x00002258 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C11_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C12(a) (0x0000225C + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C12_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C13(a) (0x00002260 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C13_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C20(a) (0x00002264 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C20_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C21(a) (0x00002268 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C21_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C22(a) (0x0000226C + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C22_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C23(a) (0x00002270 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC0COEFFICIENT_C23_VALUE 20:0 +#define NVC67D_HEAD_SET_OLUT_CONTROL(a) (0x00002280 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OLUT_CONTROL_INTERPOLATE 0:0 +#define NVC67D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_OLUT_CONTROL_MIRROR 1:1 +#define NVC67D_HEAD_SET_OLUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_OLUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_OLUT_CONTROL_MODE 3:2 +#define NVC67D_HEAD_SET_OLUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVC67D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVC67D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVC67D_HEAD_SET_OLUT_CONTROL_SIZE 18:8 +#define NVC67D_HEAD_SET_OLUT_FP_NORM_SCALE(a) (0x00002284 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OLUT_FP_NORM_SCALE_VALUE 31:0 +#define NVC67D_HEAD_SET_CONTEXT_DMA_OLUT(a) (0x00002288 + (a)*0x00000400) +#define NVC67D_HEAD_SET_CONTEXT_DMA_OLUT_HANDLE 31:0 +#define NVC67D_HEAD_SET_OFFSET_OLUT(a) (0x0000228C + (a)*0x00000400) +#define NVC67D_HEAD_SET_OFFSET_OLUT_ORIGIN 31:0 +#define NVC67D_HEAD_SET_OCSC1CONTROL(a) (0x0000229C + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1CONTROL_ENABLE 0:0 +#define NVC67D_HEAD_SET_OCSC1CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_OCSC1CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C00(a) (0x000022A0 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C00_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C01(a) (0x000022A4 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C01_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C02(a) (0x000022A8 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C02_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C03(a) (0x000022AC + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C03_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C10(a) (0x000022B0 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C10_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C11(a) (0x000022B4 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C11_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C12(a) (0x000022B8 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C12_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C13(a) (0x000022BC + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C13_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C20(a) (0x000022C0 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C20_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C21(a) (0x000022C4 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C21_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C22(a) (0x000022C8 + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C22_VALUE 20:0 +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C23(a) (0x000022CC + (a)*0x00000400) +#define NVC67D_HEAD_SET_OCSC1COEFFICIENT_C23_VALUE 20:0 +#define NVC67D_HEAD_SET_TILE_POSITION(a) (0x000022D0 + (a)*0x00000400) +#define NVC67D_HEAD_SET_TILE_POSITION_X 2:0 +#define NVC67D_HEAD_SET_TILE_POSITION_Y 6:4 +#define NVC67D_HEAD_SET_DSC_CONTROL(a) (0x000022D4 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_CONTROL_ENABLE 0:0 +#define NVC67D_HEAD_SET_DSC_CONTROL_ENABLE_FALSE (0x00000000) +#define NVC67D_HEAD_SET_DSC_CONTROL_ENABLE_TRUE (0x00000001) +#define NVC67D_HEAD_SET_DSC_CONTROL_MODE 2:1 +#define NVC67D_HEAD_SET_DSC_CONTROL_MODE_SINGLE (0x00000000) +#define NVC67D_HEAD_SET_DSC_CONTROL_MODE_DUAL (0x00000001) +#define NVC67D_HEAD_SET_DSC_CONTROL_MODE_QUAD (0x00000002) +#define NVC67D_HEAD_SET_DSC_CONTROL_AUTO_RESET 3:3 +#define NVC67D_HEAD_SET_DSC_CONTROL_AUTO_RESET_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_DSC_CONTROL_AUTO_RESET_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION 4:4 +#define NVC67D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_DSC_CONTROL_FULL_ICH_ERR_PRECISION_ENABLE (0x00000001) +#define NVC67D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET 5:5 +#define NVC67D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET_FALSE (0x00000000) +#define NVC67D_HEAD_SET_DSC_CONTROL_FORCE_ICH_RESET_TRUE (0x00000001) +#define NVC67D_HEAD_SET_DSC_CONTROL_FLATNESS_DET_THRESH 15:6 +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL(a) (0x000022D8 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_ENABLE 0:0 +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_ENABLE_FALSE (0x00000000) +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_ENABLE_TRUE (0x00000001) +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_LOCATION 1:1 +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_VSYNC (0x00000000) +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_LOCATION_VBLANK (0x00000001) +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_SIZE 9:2 +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY 10:10 +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVC67D_HEAD_SET_DSC_PPS_CONTROL_FREQUENCY_ONCE (0x00000001) +#define NVC67D_HEAD_SET_DSC_PPS_HEAD(a) (0x000022DC + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_HEAD_BYTE0 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_HEAD_BYTE1 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_HEAD_BYTE2 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_HEAD_BYTE3 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA0(a) (0x000022E0 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA0_DSC_VERSION_MINOR 3:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA0_DSC_VERSION_MAJOR 7:4 +#define NVC67D_HEAD_SET_DSC_PPS_DATA0_PPS_IDENTIFIER 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA0_RESERVED 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA0_LINEBUF_DEPTH 27:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA0_BITS_PER_COMPONENT 31:28 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1(a) (0x000022E4 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_BITS_PER_PIXEL_HIGH 1:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_VBR_ENABLE 2:2 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_SIMPLE422 3:3 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_CONVERT_RGB 4:4 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_BLOCK_PRED_ENABLE 5:5 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_RESERVED 7:6 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_BITS_PER_PIXEL_LOW 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_PIC_HEIGHT_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA1_PIC_HEIGHT_LOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA2(a) (0x000022E8 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA2_PIC_WIDTH_HIGH 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA2_PIC_WIDTH_LOW 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA2_SLICE_HEIGHT_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA2_SLICE_HEIGHT_LOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA3(a) (0x000022EC + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA3_SLICE_WIDTH_HIGH 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA3_SLICE_WIDTH_LOW 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA3_CHUNK_SIZE_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA3_CHUNK_SIZE_LOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA4(a) (0x000022F0 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA4_INITIAL_XMIT_DELAY_HIGH 1:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA4_RESERVED 7:2 +#define NVC67D_HEAD_SET_DSC_PPS_DATA4_INITIAL_XMIT_DELAY_LOW 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA4_INITIAL_DEC_DELAY_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA4_INITIAL_DEC_DELAY_LOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA5(a) (0x000022F4 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA5_RESERVED0 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA5_INITIAL_SCALE_VALUE 13:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA5_RESERVED1 15:14 +#define NVC67D_HEAD_SET_DSC_PPS_DATA5_SCALE_INCREMENT_INTERVAL_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA5_SCALE_INCREMENT_INTERVAL_LOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA6(a) (0x000022F8 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA6_SCALE_DECREMENT_INTERVAL_HIGH 3:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA6_RESERVED0 7:4 +#define NVC67D_HEAD_SET_DSC_PPS_DATA6_SCALE_DECREMENT_INTERVAL_LOW 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA6_RESERVED1 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA6_FIRST_LINE_BPG_OFFSET 28:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA6_RESERVED2 31:29 +#define NVC67D_HEAD_SET_DSC_PPS_DATA7(a) (0x000022FC + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA7_NFL_BPG_OFFSET_HIGH 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA7_NFL_BPG_OFFSET_LOW 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA7_SLICE_BPG_OFFSET_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA7_SLICE_BPG_OFFSET_LOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA8(a) (0x00002300 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA8_INITIAL_OFFSET_HIGH 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA8_INITIAL_OFFSET_LOW 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA8_FINAL_OFFSET_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA8_FINAL_OFFSET_LOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA9(a) (0x00002304 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA9_FLATNESS_MIN_QP 4:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA9_RESERVED0 7:5 +#define NVC67D_HEAD_SET_DSC_PPS_DATA9_FLATNESS_MAX_QP 12:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA9_RESERVED1 15:13 +#define NVC67D_HEAD_SET_DSC_PPS_DATA9_RC_MODEL_SIZE_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA9_RC_MODEL_SIZE_LOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA10(a) (0x00002308 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA10_RC_EDGE_FACTOR 3:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA10_RESERVED0 7:4 +#define NVC67D_HEAD_SET_DSC_PPS_DATA10_RC_QUANT_INCR_LIMIT0 12:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA10_RESERVED1 15:13 +#define NVC67D_HEAD_SET_DSC_PPS_DATA10_RC_QUANT_INCR_LIMIT1 20:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA10_RESERVED2 23:21 +#define NVC67D_HEAD_SET_DSC_PPS_DATA10_RC_TGT_OFFSET_LO 27:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA10_RC_TGT_OFFSET_HI 31:28 +#define NVC67D_HEAD_SET_DSC_PPS_DATA11(a) (0x0000230C + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH0 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH1 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH2 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA11_RC_BUF_THRESH3 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA12(a) (0x00002310 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH4 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH5 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH6 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA12_RC_BUF_THRESH7 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA13(a) (0x00002314 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH8 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH9 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH10 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA13_RC_BUF_THRESH11 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA14(a) (0x00002318 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA14_RC_BUF_THRESH12 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA14_RC_BUF_THRESH13 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MAX_QP_HIGH0 18:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MIN_QP0 23:19 +#define NVC67D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_BPG_OFFSET0 29:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA14_RC_RANGE_MAX_QP_LOW0 31:30 +#define NVC67D_HEAD_SET_DSC_PPS_DATA15(a) (0x0000231C + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_HIGH1 2:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MIN_QP1 7:3 +#define NVC67D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_BPG_OFFSET1 13:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_LOW1 15:14 +#define NVC67D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_HIGH2 18:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MIN_QP2 23:19 +#define NVC67D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_BPG_OFFSET2 29:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA15_RC_RANGE_MAX_QP_LOW2 31:30 +#define NVC67D_HEAD_SET_DSC_PPS_DATA16(a) (0x00002320 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_HIGH3 2:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MIN_QP3 7:3 +#define NVC67D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_BPG_OFFSET3 13:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_LOW3 15:14 +#define NVC67D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_HIGH4 18:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MIN_QP4 23:19 +#define NVC67D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_BPG_OFFSET4 29:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA16_RC_RANGE_MAX_QP_LOW4 31:30 +#define NVC67D_HEAD_SET_DSC_PPS_DATA17(a) (0x00002324 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_HIGH5 2:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MIN_QP5 7:3 +#define NVC67D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_BPG_OFFSET5 13:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_LOW5 15:14 +#define NVC67D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_HIGH6 18:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MIN_QP6 23:19 +#define NVC67D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_BPG_OFFSET6 29:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA17_RC_RANGE_MAX_QP_LOW6 31:30 +#define NVC67D_HEAD_SET_DSC_PPS_DATA18(a) (0x00002328 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_HIGH7 2:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MIN_QP7 7:3 +#define NVC67D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_BPG_OFFSET7 13:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_LOW7 15:14 +#define NVC67D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_HIGH8 18:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MIN_QP8 23:19 +#define NVC67D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_BPG_OFFSET8 29:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA18_RC_RANGE_MAX_QP_LOW8 31:30 +#define NVC67D_HEAD_SET_DSC_PPS_DATA19(a) (0x0000232C + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_HIGH9 2:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MIN_QP9 7:3 +#define NVC67D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_BPG_OFFSET9 13:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_LOW9 15:14 +#define NVC67D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_HIGH10 18:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MIN_QP10 23:19 +#define NVC67D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_BPG_OFFSET10 29:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA19_RC_RANGE_MAX_QP_LOW10 31:30 +#define NVC67D_HEAD_SET_DSC_PPS_DATA20(a) (0x00002330 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_HIGH11 2:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MIN_QP11 7:3 +#define NVC67D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_BPG_OFFSET11 13:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_LOW11 15:14 +#define NVC67D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_HIGH12 18:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MIN_QP12 23:19 +#define NVC67D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_BPG_OFFSET12 29:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA20_RC_RANGE_MAX_QP_LOW12 31:30 +#define NVC67D_HEAD_SET_DSC_PPS_DATA21(a) (0x00002334 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_HIGH13 2:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MIN_QP13 7:3 +#define NVC67D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_BPG_OFFSET13 13:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_LOW13 15:14 +#define NVC67D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_HIGH14 18:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MIN_QP14 23:19 +#define NVC67D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_BPG_OFFSET14 29:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA21_RC_RANGE_MAX_QP_LOW14 31:30 +#define NVC67D_HEAD_SET_DSC_PPS_DATA22(a) (0x00002338 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA22_NATIVE422 0:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA22_NATIVE420 1:1 +#define NVC67D_HEAD_SET_DSC_PPS_DATA22_RESERVED0 7:2 +#define NVC67D_HEAD_SET_DSC_PPS_DATA22_SECOND_LINE_BPG_OFFSET 12:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA22_RESERVED1 15:13 +#define NVC67D_HEAD_SET_DSC_PPS_DATA22_NSL_BPG_OFFSET_HIGH 23:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA22_NSL_BPG_OFFSETLOW 31:24 +#define NVC67D_HEAD_SET_DSC_PPS_DATA23(a) (0x0000233C + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA23_SECOND_LINE_OFFSET_ADJ_HIGH 7:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA23_SECOND_LINE_OFFSET_ADJ_LOW 15:8 +#define NVC67D_HEAD_SET_DSC_PPS_DATA23_RESERVED 31:16 +#define NVC67D_HEAD_SET_DSC_PPS_DATA24(a) (0x00002340 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA24_RESERVED 31:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA25(a) (0x00002344 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA25_RESERVED 31:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA26(a) (0x00002348 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA26_RESERVED 31:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA27(a) (0x0000234C + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA27_RESERVED 31:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA28(a) (0x00002350 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA28_RESERVED 31:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA29(a) (0x00002354 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA29_RESERVED 31:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA30(a) (0x00002358 + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA30_RESERVED 31:0 +#define NVC67D_HEAD_SET_DSC_PPS_DATA31(a) (0x0000235C + (a)*0x00000400) +#define NVC67D_HEAD_SET_DSC_PPS_DATA31_RESERVED 31:0 +#define NVC67D_HEAD_SET_RG_MERGE(a) (0x00002360 + (a)*0x00000400) +#define NVC67D_HEAD_SET_RG_MERGE_MODE 1:0 +#define NVC67D_HEAD_SET_RG_MERGE_MODE_DISABLE (0x00000000) +#define NVC67D_HEAD_SET_RG_MERGE_MODE_SETUP (0x00000001) +#define NVC67D_HEAD_SET_RG_MERGE_MODE_MASTER (0x00000002) +#define NVC67D_HEAD_SET_RG_MERGE_MODE_SLAVE (0x00000003) +#define NVC67D_HEAD_SET_RASTER_HBLANK_DELAY(a) (0x00002364 + (a)*0x00000400) +#define NVC67D_HEAD_SET_RASTER_HBLANK_DELAY_BLANK_START 15:0 +#define NVC67D_HEAD_SET_RASTER_HBLANK_DELAY_BLANK_END 31:16 +#define NVC67D_HEAD_SET_HDMI_DSC_HCACTIVE(a) (0x00002368 + (a)*0x00000400) +#define NVC67D_HEAD_SET_HDMI_DSC_HCACTIVE_BYTES 15:0 +#define NVC67D_HEAD_SET_HDMI_DSC_HCACTIVE_TRI_BYTES 31:16 +#define NVC67D_HEAD_SET_HDMI_DSC_HCBLANK(a) (0x0000236C + (a)*0x00000400) +#define NVC67D_HEAD_SET_HDMI_DSC_HCBLANK_WIDTH 15:0 +#define NVC67D_HEAD_SW_RESERVED(a,b) (0x00002370 + (a)*0x00000400 + (b)*0x00000004) +#define NVC67D_HEAD_SW_RESERVED_VALUE 31:0 +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_HI(a,b) (0x00002380 + (a)*0x00000400 + (b)*0x00000004) +#define NVC67D_HEAD_SET_RG_REL_SEMAPHORE_VALUE_HI_VALUE 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC67d_h diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc67e.h b/userspace/sdks/nv570/nvidia/inc/class/clc67e.h new file mode 100644 index 0000000..516e6ea --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc67e.h @@ -0,0 +1,700 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + + + +#ifndef _clC67e_h_ +#define _clC67e_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC67E_WINDOW_CHANNEL_DMA (0x0000C67E) + +// dma opcode instructions +#define NVC67E_DMA +#define NVC67E_DMA_OPCODE 31:29 +#define NVC67E_DMA_OPCODE_METHOD 0x00000000 +#define NVC67E_DMA_OPCODE_JUMP 0x00000001 +#define NVC67E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC67E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC67E_DMA_METHOD_COUNT 27:18 +#define NVC67E_DMA_METHOD_OFFSET 13:2 +#define NVC67E_DMA_DATA 31:0 +#define NVC67E_DMA_DATA_NOP 0x00000000 +#define NVC67E_DMA_JUMP_OFFSET 11:2 +#define NVC67E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVC67E_PUT (0x00000000) +#define NVC67E_PUT_PTR 9:0 +#define NVC67E_GET (0x00000004) +#define NVC67E_GET_PTR 9:0 +#define NVC67E_UPDATE (0x00000200) +#define NVC67E_UPDATE_RELEASE_ELV 0:0 +#define NVC67E_UPDATE_RELEASE_ELV_FALSE (0x00000000) +#define NVC67E_UPDATE_RELEASE_ELV_TRUE (0x00000001) +#define NVC67E_UPDATE_FLIP_LOCK_PIN 8:4 +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i)) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16 +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i)) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8 +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E) +#define NVC67E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F) +#define NVC67E_UPDATE_INTERLOCK_WITH_WIN_IMM 12:12 +#define NVC67E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE (0x00000000) +#define NVC67E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE (0x00000001) +#define NVC67E_SET_SEMAPHORE_ACQUIRE_HI (0x00000204) +#define NVC67E_SET_SEMAPHORE_ACQUIRE_HI_VALUE 31:0 +#define NVC67E_GET_LINE (0x00000208) +#define NVC67E_GET_LINE_LINE 15:0 +#define NVC67E_SET_SEMAPHORE_CONTROL (0x0000020C) +#define NVC67E_SET_SEMAPHORE_CONTROL_OFFSET 7:0 +#define NVC67E_SET_SEMAPHORE_CONTROL_SKIP_ACQ 11:11 +#define NVC67E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_FALSE (0x00000000) +#define NVC67E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_TRUE (0x00000001) +#define NVC67E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVC67E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVC67E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVC67E_SET_SEMAPHORE_CONTROL_ACQ_MODE 13:12 +#define NVC67E_SET_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000) +#define NVC67E_SET_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001) +#define NVC67E_SET_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002) +#define NVC67E_SET_SEMAPHORE_CONTROL_REL_MODE 14:14 +#define NVC67E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE (0x00000000) +#define NVC67E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC67E_SET_SEMAPHORE_ACQUIRE (0x00000210) +#define NVC67E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NVC67E_SET_SEMAPHORE_RELEASE (0x00000214) +#define NVC67E_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NVC67E_SET_CONTEXT_DMA_SEMAPHORE (0x00000218) +#define NVC67E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NVC67E_SET_CONTEXT_DMA_NOTIFIER (0x0000021C) +#define NVC67E_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NVC67E_SET_NOTIFIER_CONTROL (0x00000220) +#define NVC67E_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC67E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC67E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC67E_SET_NOTIFIER_CONTROL_OFFSET 11:4 +#define NVC67E_SET_SIZE (0x00000224) +#define NVC67E_SET_SIZE_WIDTH 15:0 +#define NVC67E_SET_SIZE_HEIGHT 31:16 +#define NVC67E_SET_STORAGE (0x00000228) +#define NVC67E_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NVC67E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NVC67E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NVC67E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC67E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC67E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC67E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC67E_SET_PARAMS (0x0000022C) +#define NVC67E_SET_PARAMS_FORMAT 7:0 +#define NVC67E_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NVC67E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F) +#define NVC67E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NVC67E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC67E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E) +#define NVC67E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC67E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6) +#define NVC67E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NVC67E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9) +#define NVC67E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NVC67E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NVC67E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NVC67E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NVC67E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NVC67E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028) +#define NVC67E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029) +#define NVC67E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035) +#define NVC67E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036) +#define NVC67E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038) +#define NVC67E_SET_PARAMS_FORMAT_Y8___U8___V8_N444 (0x0000003A) +#define NVC67E_SET_PARAMS_FORMAT_Y8___U8___V8_N420 (0x0000003B) +#define NVC67E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055) +#define NVC67E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056) +#define NVC67E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058) +#define NVC67E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075) +#define NVC67E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076) +#define NVC67E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078) +#define NVC67E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18 +#define NVC67E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000) +#define NVC67E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001) +#define NVC67E_SET_PARAMS_SWAP_UV 19:19 +#define NVC67E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000) +#define NVC67E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001) +#define NVC67E_SET_PARAMS_FMT_ROUNDING_MODE 22:22 +#define NVC67E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_TO_NEAREST (0x00000000) +#define NVC67E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_DOWN (0x00000001) +#define NVC67E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004) +#define NVC67E_SET_PLANAR_STORAGE_PITCH 12:0 +#define NVC67E_SET_SEMAPHORE_RELEASE_HI (0x0000023C) +#define NVC67E_SET_SEMAPHORE_RELEASE_HI_VALUE 31:0 +#define NVC67E_SET_CONTEXT_DMA_ISO(b) (0x00000240 + (b)*0x00000004) +#define NVC67E_SET_CONTEXT_DMA_ISO_HANDLE 31:0 +#define NVC67E_SET_OFFSET(b) (0x00000260 + (b)*0x00000004) +#define NVC67E_SET_OFFSET_ORIGIN 31:0 +#define NVC67E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004) +#define NVC67E_SET_POINT_IN_X 15:0 +#define NVC67E_SET_POINT_IN_Y 31:16 +#define NVC67E_SET_SIZE_IN (0x00000298) +#define NVC67E_SET_SIZE_IN_WIDTH 15:0 +#define NVC67E_SET_SIZE_IN_HEIGHT 31:16 +#define NVC67E_SET_SIZE_OUT (0x000002A4) +#define NVC67E_SET_SIZE_OUT_WIDTH 15:0 +#define NVC67E_SET_SIZE_OUT_HEIGHT 31:16 +#define NVC67E_SET_CONTROL_INPUT_SCALER (0x000002A8) +#define NVC67E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS 2:0 +#define NVC67E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NVC67E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NVC67E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS 6:4 +#define NVC67E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NVC67E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004) +#define NVC67E_SET_INPUT_SCALER_COEFF_VALUE (0x000002AC) +#define NVC67E_SET_INPUT_SCALER_COEFF_VALUE_DATA 9:0 +#define NVC67E_SET_INPUT_SCALER_COEFF_VALUE_INDEX 19:12 +#define NVC67E_SET_COMPOSITION_CONTROL (0x000002EC) +#define NVC67E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0 +#define NVC67E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000) +#define NVC67E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001) +#define NVC67E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002) +#define NVC67E_SET_COMPOSITION_CONTROL_DEPTH 11:4 +#define NVC67E_SET_COMPOSITION_CONTROL_BYPASS 16:16 +#define NVC67E_SET_COMPOSITION_CONTROL_BYPASS_DISABLE (0x00000000) +#define NVC67E_SET_COMPOSITION_CONTROL_BYPASS_ENABLE (0x00000001) +#define NVC67E_SET_COMPOSITION_CONSTANT_ALPHA (0x000002F0) +#define NVC67E_SET_COMPOSITION_CONSTANT_ALPHA_K1 7:0 +#define NVC67E_SET_COMPOSITION_CONSTANT_ALPHA_K2 15:8 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT (0x000002F4) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28 +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC67E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC67E_SET_KEY_ALPHA (0x000002F8) +#define NVC67E_SET_KEY_ALPHA_MIN 15:0 +#define NVC67E_SET_KEY_ALPHA_MAX 31:16 +#define NVC67E_SET_KEY_RED_CR (0x000002FC) +#define NVC67E_SET_KEY_RED_CR_MIN 15:0 +#define NVC67E_SET_KEY_RED_CR_MAX 31:16 +#define NVC67E_SET_KEY_GREEN_Y (0x00000300) +#define NVC67E_SET_KEY_GREEN_Y_MIN 15:0 +#define NVC67E_SET_KEY_GREEN_Y_MAX 31:16 +#define NVC67E_SET_KEY_BLUE_CB (0x00000304) +#define NVC67E_SET_KEY_BLUE_CB_MIN 15:0 +#define NVC67E_SET_KEY_BLUE_CB_MAX 31:16 +#define NVC67E_SET_PRESENT_CONTROL (0x00000308) +#define NVC67E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NVC67E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4 +#define NVC67E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NVC67E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NVC67E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8 +#define NVC67E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000) +#define NVC67E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001) +#define NVC67E_SET_PRESENT_CONTROL_STEREO_MODE 13:12 +#define NVC67E_SET_PRESENT_CONTROL_STEREO_MODE_MONO (0x00000000) +#define NVC67E_SET_PRESENT_CONTROL_STEREO_MODE_PAIR_FLIP (0x00000001) +#define NVC67E_SET_PRESENT_CONTROL_STEREO_MODE_AT_ANY_FRAME (0x00000002) +#define NVC67E_SET_ACQ_SEMAPHORE_VALUE_HI (0x0000030C) +#define NVC67E_SET_ACQ_SEMAPHORE_VALUE_HI_VALUE 31:0 +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL (0x00000330) +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL_OFFSET 7:0 +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15 +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000) +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001) +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE 13:12 +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000) +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001) +#define NVC67E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002) +#define NVC67E_SET_ACQ_SEMAPHORE_VALUE (0x00000334) +#define NVC67E_SET_ACQ_SEMAPHORE_VALUE_VALUE 31:0 +#define NVC67E_SET_CONTEXT_DMA_ACQ_SEMAPHORE (0x00000338) +#define NVC67E_SET_CONTEXT_DMA_ACQ_SEMAPHORE_HANDLE 31:0 +#define NVC67E_SET_SCAN_DIRECTION (0x0000033C) +#define NVC67E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION 0:0 +#define NVC67E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_LEFT (0x00000000) +#define NVC67E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_RIGHT (0x00000001) +#define NVC67E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION 1:1 +#define NVC67E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_TOP (0x00000000) +#define NVC67E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_BOTTOM (0x00000001) +#define NVC67E_SET_SCAN_DIRECTION_COLUMN_ORDER 2:2 +#define NVC67E_SET_SCAN_DIRECTION_COLUMN_ORDER_FALSE (0x00000000) +#define NVC67E_SET_SCAN_DIRECTION_COLUMN_ORDER_TRUE (0x00000001) +#define NVC67E_SET_TIMESTAMP_ORIGIN_LO (0x00000340) +#define NVC67E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NVC67E_SET_TIMESTAMP_ORIGIN_HI (0x00000344) +#define NVC67E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NVC67E_SET_UPDATE_TIMESTAMP_LO (0x00000348) +#define NVC67E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NVC67E_SET_UPDATE_TIMESTAMP_HI (0x0000034C) +#define NVC67E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NVC67E_SET_INTERLOCK_FLAGS (0x00000370) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 0:0 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+1):((i)+1) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 1:1 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 2:2 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 3:3 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 4:4 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 5:5 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 6:6 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 7:7 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 8:8 +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC67E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS (0x00000374) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC67E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#define NVC67E_SET_EXT_PACKET_CONTROL (0x00000398) +#define NVC67E_SET_EXT_PACKET_CONTROL_ENABLE 0:0 +#define NVC67E_SET_EXT_PACKET_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67E_SET_EXT_PACKET_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67E_SET_EXT_PACKET_CONTROL_LOCATION 4:4 +#define NVC67E_SET_EXT_PACKET_CONTROL_LOCATION_VSYNC (0x00000000) +#define NVC67E_SET_EXT_PACKET_CONTROL_LOCATION_VBLANK (0x00000001) +#define NVC67E_SET_EXT_PACKET_CONTROL_FREQUENCY 8:8 +#define NVC67E_SET_EXT_PACKET_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000) +#define NVC67E_SET_EXT_PACKET_CONTROL_FREQUENCY_ONCE (0x00000001) +#define NVC67E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE 12:12 +#define NVC67E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_DISABLE (0x00000000) +#define NVC67E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_ENABLE (0x00000001) +#define NVC67E_SET_EXT_PACKET_CONTROL_SIZE 27:16 +#define NVC67E_SET_EXT_PACKET_DATA (0x0000039C) +#define NVC67E_SET_EXT_PACKET_DATA_DB0 7:0 +#define NVC67E_SET_EXT_PACKET_DATA_DB1 15:8 +#define NVC67E_SET_EXT_PACKET_DATA_DB2 23:16 +#define NVC67E_SET_EXT_PACKET_DATA_DB3 31:24 +#define NVC67E_SET_FMT_COEFFICIENT_C00 (0x00000400) +#define NVC67E_SET_FMT_COEFFICIENT_C00_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C01 (0x00000404) +#define NVC67E_SET_FMT_COEFFICIENT_C01_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C02 (0x00000408) +#define NVC67E_SET_FMT_COEFFICIENT_C02_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C03 (0x0000040C) +#define NVC67E_SET_FMT_COEFFICIENT_C03_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C10 (0x00000410) +#define NVC67E_SET_FMT_COEFFICIENT_C10_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C11 (0x00000414) +#define NVC67E_SET_FMT_COEFFICIENT_C11_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C12 (0x00000418) +#define NVC67E_SET_FMT_COEFFICIENT_C12_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C13 (0x0000041C) +#define NVC67E_SET_FMT_COEFFICIENT_C13_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C20 (0x00000420) +#define NVC67E_SET_FMT_COEFFICIENT_C20_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C21 (0x00000424) +#define NVC67E_SET_FMT_COEFFICIENT_C21_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C22 (0x00000428) +#define NVC67E_SET_FMT_COEFFICIENT_C22_VALUE 20:0 +#define NVC67E_SET_FMT_COEFFICIENT_C23 (0x0000042C) +#define NVC67E_SET_FMT_COEFFICIENT_C23_VALUE 20:0 +#define NVC67E_SET_ILUT_CONTROL (0x00000440) +#define NVC67E_SET_ILUT_CONTROL_INTERPOLATE 0:0 +#define NVC67E_SET_ILUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC67E_SET_ILUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC67E_SET_ILUT_CONTROL_MIRROR 1:1 +#define NVC67E_SET_ILUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC67E_SET_ILUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC67E_SET_ILUT_CONTROL_MODE 3:2 +#define NVC67E_SET_ILUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVC67E_SET_ILUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVC67E_SET_ILUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVC67E_SET_ILUT_CONTROL_SIZE 18:8 +#define NVC67E_SET_CONTEXT_DMA_ILUT (0x00000444) +#define NVC67E_SET_CONTEXT_DMA_ILUT_HANDLE 31:0 +#define NVC67E_SET_OFFSET_ILUT (0x00000448) +#define NVC67E_SET_OFFSET_ILUT_ORIGIN 31:0 +#define NVC67E_SET_CSC00CONTROL (0x0000045C) +#define NVC67E_SET_CSC00CONTROL_ENABLE 0:0 +#define NVC67E_SET_CSC00CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67E_SET_CSC00CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67E_SET_CSC00COEFFICIENT_C00 (0x00000460) +#define NVC67E_SET_CSC00COEFFICIENT_C00_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C01 (0x00000464) +#define NVC67E_SET_CSC00COEFFICIENT_C01_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C02 (0x00000468) +#define NVC67E_SET_CSC00COEFFICIENT_C02_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C03 (0x0000046C) +#define NVC67E_SET_CSC00COEFFICIENT_C03_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C10 (0x00000470) +#define NVC67E_SET_CSC00COEFFICIENT_C10_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C11 (0x00000474) +#define NVC67E_SET_CSC00COEFFICIENT_C11_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C12 (0x00000478) +#define NVC67E_SET_CSC00COEFFICIENT_C12_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C13 (0x0000047C) +#define NVC67E_SET_CSC00COEFFICIENT_C13_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C20 (0x00000480) +#define NVC67E_SET_CSC00COEFFICIENT_C20_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C21 (0x00000484) +#define NVC67E_SET_CSC00COEFFICIENT_C21_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C22 (0x00000488) +#define NVC67E_SET_CSC00COEFFICIENT_C22_VALUE 20:0 +#define NVC67E_SET_CSC00COEFFICIENT_C23 (0x0000048C) +#define NVC67E_SET_CSC00COEFFICIENT_C23_VALUE 20:0 +#define NVC67E_SET_CSC0LUT_CONTROL (0x000004A0) +#define NVC67E_SET_CSC0LUT_CONTROL_INTERPOLATE 0:0 +#define NVC67E_SET_CSC0LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC67E_SET_CSC0LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC67E_SET_CSC0LUT_CONTROL_MIRROR 1:1 +#define NVC67E_SET_CSC0LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC67E_SET_CSC0LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC67E_SET_CSC0LUT_CONTROL_ENABLE 4:4 +#define NVC67E_SET_CSC0LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67E_SET_CSC0LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67E_SET_CSC0LUT_SEGMENT_SIZE (0x000004A4) +#define NVC67E_SET_CSC0LUT_SEGMENT_SIZE_IDX 5:0 +#define NVC67E_SET_CSC0LUT_SEGMENT_SIZE_VALUE 18:16 +#define NVC67E_SET_CSC0LUT_ENTRY (0x000004A8) +#define NVC67E_SET_CSC0LUT_ENTRY_IDX 10:0 +#define NVC67E_SET_CSC0LUT_ENTRY_VALUE 31:16 +#define NVC67E_SET_CSC01CONTROL (0x000004BC) +#define NVC67E_SET_CSC01CONTROL_ENABLE 0:0 +#define NVC67E_SET_CSC01CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67E_SET_CSC01CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67E_SET_CSC01COEFFICIENT_C00 (0x000004C0) +#define NVC67E_SET_CSC01COEFFICIENT_C00_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C01 (0x000004C4) +#define NVC67E_SET_CSC01COEFFICIENT_C01_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C02 (0x000004C8) +#define NVC67E_SET_CSC01COEFFICIENT_C02_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C03 (0x000004CC) +#define NVC67E_SET_CSC01COEFFICIENT_C03_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C10 (0x000004D0) +#define NVC67E_SET_CSC01COEFFICIENT_C10_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C11 (0x000004D4) +#define NVC67E_SET_CSC01COEFFICIENT_C11_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C12 (0x000004D8) +#define NVC67E_SET_CSC01COEFFICIENT_C12_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C13 (0x000004DC) +#define NVC67E_SET_CSC01COEFFICIENT_C13_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C20 (0x000004E0) +#define NVC67E_SET_CSC01COEFFICIENT_C20_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C21 (0x000004E4) +#define NVC67E_SET_CSC01COEFFICIENT_C21_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C22 (0x000004E8) +#define NVC67E_SET_CSC01COEFFICIENT_C22_VALUE 20:0 +#define NVC67E_SET_CSC01COEFFICIENT_C23 (0x000004EC) +#define NVC67E_SET_CSC01COEFFICIENT_C23_VALUE 20:0 +#define NVC67E_SET_TMO_CONTROL (0x00000500) +#define NVC67E_SET_TMO_CONTROL_INTERPOLATE 0:0 +#define NVC67E_SET_TMO_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC67E_SET_TMO_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC67E_SET_TMO_CONTROL_SAT_MODE 3:2 +#define NVC67E_SET_TMO_CONTROL_SIZE 18:8 +#define NVC67E_SET_TMO_LOW_INTENSITY_ZONE (0x00000508) +#define NVC67E_SET_TMO_LOW_INTENSITY_ZONE_END 29:16 +#define NVC67E_SET_TMO_LOW_INTENSITY_VALUE (0x0000050C) +#define NVC67E_SET_TMO_LOW_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVC67E_SET_TMO_LOW_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVC67E_SET_TMO_LOW_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVC67E_SET_TMO_MEDIUM_INTENSITY_ZONE (0x00000510) +#define NVC67E_SET_TMO_MEDIUM_INTENSITY_ZONE_START 13:0 +#define NVC67E_SET_TMO_MEDIUM_INTENSITY_ZONE_END 29:16 +#define NVC67E_SET_TMO_MEDIUM_INTENSITY_VALUE (0x00000514) +#define NVC67E_SET_TMO_MEDIUM_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVC67E_SET_TMO_MEDIUM_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVC67E_SET_TMO_MEDIUM_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVC67E_SET_TMO_HIGH_INTENSITY_ZONE (0x00000518) +#define NVC67E_SET_TMO_HIGH_INTENSITY_ZONE_START 13:0 +#define NVC67E_SET_TMO_HIGH_INTENSITY_VALUE (0x0000051C) +#define NVC67E_SET_TMO_HIGH_INTENSITY_VALUE_LIN_WEIGHT 8:0 +#define NVC67E_SET_TMO_HIGH_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12 +#define NVC67E_SET_TMO_HIGH_INTENSITY_VALUE_THRESHOLD 31:24 +#define NVC67E_SET_CONTEXT_DMA_TMO_LUT (0x00000528) +#define NVC67E_SET_CONTEXT_DMA_TMO_LUT_HANDLE 31:0 +#define NVC67E_SET_OFFSET_TMO_LUT (0x0000052C) +#define NVC67E_SET_OFFSET_TMO_LUT_ORIGIN 31:0 +#define NVC67E_SET_CSC10CONTROL (0x0000053C) +#define NVC67E_SET_CSC10CONTROL_ENABLE 0:0 +#define NVC67E_SET_CSC10CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67E_SET_CSC10CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67E_SET_CSC10COEFFICIENT_C00 (0x00000540) +#define NVC67E_SET_CSC10COEFFICIENT_C00_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C01 (0x00000544) +#define NVC67E_SET_CSC10COEFFICIENT_C01_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C02 (0x00000548) +#define NVC67E_SET_CSC10COEFFICIENT_C02_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C03 (0x0000054C) +#define NVC67E_SET_CSC10COEFFICIENT_C03_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C10 (0x00000550) +#define NVC67E_SET_CSC10COEFFICIENT_C10_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C11 (0x00000554) +#define NVC67E_SET_CSC10COEFFICIENT_C11_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C12 (0x00000558) +#define NVC67E_SET_CSC10COEFFICIENT_C12_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C13 (0x0000055C) +#define NVC67E_SET_CSC10COEFFICIENT_C13_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C20 (0x00000560) +#define NVC67E_SET_CSC10COEFFICIENT_C20_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C21 (0x00000564) +#define NVC67E_SET_CSC10COEFFICIENT_C21_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C22 (0x00000568) +#define NVC67E_SET_CSC10COEFFICIENT_C22_VALUE 20:0 +#define NVC67E_SET_CSC10COEFFICIENT_C23 (0x0000056C) +#define NVC67E_SET_CSC10COEFFICIENT_C23_VALUE 20:0 +#define NVC67E_SET_CSC1LUT_CONTROL (0x00000580) +#define NVC67E_SET_CSC1LUT_CONTROL_INTERPOLATE 0:0 +#define NVC67E_SET_CSC1LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC67E_SET_CSC1LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC67E_SET_CSC1LUT_CONTROL_MIRROR 1:1 +#define NVC67E_SET_CSC1LUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC67E_SET_CSC1LUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC67E_SET_CSC1LUT_CONTROL_ENABLE 4:4 +#define NVC67E_SET_CSC1LUT_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67E_SET_CSC1LUT_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67E_SET_CSC1LUT_SEGMENT_SIZE (0x00000584) +#define NVC67E_SET_CSC1LUT_SEGMENT_SIZE_IDX 5:0 +#define NVC67E_SET_CSC1LUT_SEGMENT_SIZE_VALUE 18:16 +#define NVC67E_SET_CSC1LUT_ENTRY (0x00000588) +#define NVC67E_SET_CSC1LUT_ENTRY_IDX 10:0 +#define NVC67E_SET_CSC1LUT_ENTRY_VALUE 31:16 +#define NVC67E_SET_CSC11CONTROL (0x0000059C) +#define NVC67E_SET_CSC11CONTROL_ENABLE 0:0 +#define NVC67E_SET_CSC11CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC67E_SET_CSC11CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC67E_SET_CSC11COEFFICIENT_C00 (0x000005A0) +#define NVC67E_SET_CSC11COEFFICIENT_C00_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C01 (0x000005A4) +#define NVC67E_SET_CSC11COEFFICIENT_C01_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C02 (0x000005A8) +#define NVC67E_SET_CSC11COEFFICIENT_C02_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C03 (0x000005AC) +#define NVC67E_SET_CSC11COEFFICIENT_C03_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C10 (0x000005B0) +#define NVC67E_SET_CSC11COEFFICIENT_C10_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C11 (0x000005B4) +#define NVC67E_SET_CSC11COEFFICIENT_C11_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C12 (0x000005B8) +#define NVC67E_SET_CSC11COEFFICIENT_C12_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C13 (0x000005BC) +#define NVC67E_SET_CSC11COEFFICIENT_C13_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C20 (0x000005C0) +#define NVC67E_SET_CSC11COEFFICIENT_C20_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C21 (0x000005C4) +#define NVC67E_SET_CSC11COEFFICIENT_C21_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C22 (0x000005C8) +#define NVC67E_SET_CSC11COEFFICIENT_C22_VALUE 20:0 +#define NVC67E_SET_CSC11COEFFICIENT_C23 (0x000005CC) +#define NVC67E_SET_CSC11COEFFICIENT_C23_VALUE 20:0 +#define NVC67E_SET_CLAMP_RANGE (0x000005D0) +#define NVC67E_SET_CLAMP_RANGE_LOW 15:0 +#define NVC67E_SET_CLAMP_RANGE_HIGH 31:16 +#define NVC67E_SW_RESERVED(b) (0x000005D4 + (b)*0x00000004) +#define NVC67E_SW_RESERVED_VALUE 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clC67e_h diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc697.h b/userspace/sdks/nv570/nvidia/inc/class/clc697.h new file mode 100644 index 0000000..a8b447e --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc697.h @@ -0,0 +1,4352 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_ampere_a_h_ +#define _cl_ampere_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl ampere_a */ + +#include "nvtypes.h" + +#define AMPERE_A 0xC697 + +#define NVC697_SET_OBJECT 0x0000 +#define NVC697_SET_OBJECT_CLASS_ID 15:0 +#define NVC697_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC697_NO_OPERATION 0x0100 +#define NVC697_NO_OPERATION_V 31:0 + +#define NVC697_SET_NOTIFY_A 0x0104 +#define NVC697_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC697_SET_NOTIFY_B 0x0108 +#define NVC697_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC697_NOTIFY 0x010c +#define NVC697_NOTIFY_TYPE 31:0 +#define NVC697_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC697_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC697_WAIT_FOR_IDLE 0x0110 +#define NVC697_WAIT_FOR_IDLE_V 31:0 + +#define NVC697_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC697_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC697_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC697_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC697_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC697_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC697_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC697_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC697_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC697_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC697_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC697_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC697_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC697_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC697_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC697_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC697_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC697_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC697_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC697_SEND_GO_IDLE 0x013c +#define NVC697_SEND_GO_IDLE_V 31:0 + +#define NVC697_PM_TRIGGER 0x0140 +#define NVC697_PM_TRIGGER_V 31:0 + +#define NVC697_PM_TRIGGER_WFI 0x0144 +#define NVC697_PM_TRIGGER_WFI_V 31:0 + +#define NVC697_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC697_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC697_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC697_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC697_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC697_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC697_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC697_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC697_LINE_LENGTH_IN 0x0180 +#define NVC697_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC697_LINE_COUNT 0x0184 +#define NVC697_LINE_COUNT_VALUE 31:0 + +#define NVC697_OFFSET_OUT_UPPER 0x0188 +#define NVC697_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC697_OFFSET_OUT 0x018c +#define NVC697_OFFSET_OUT_VALUE 31:0 + +#define NVC697_PITCH_OUT 0x0190 +#define NVC697_PITCH_OUT_VALUE 31:0 + +#define NVC697_SET_DST_BLOCK_SIZE 0x0194 +#define NVC697_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC697_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC697_SET_DST_WIDTH 0x0198 +#define NVC697_SET_DST_WIDTH_V 31:0 + +#define NVC697_SET_DST_HEIGHT 0x019c +#define NVC697_SET_DST_HEIGHT_V 31:0 + +#define NVC697_SET_DST_DEPTH 0x01a0 +#define NVC697_SET_DST_DEPTH_V 31:0 + +#define NVC697_SET_DST_LAYER 0x01a4 +#define NVC697_SET_DST_LAYER_V 31:0 + +#define NVC697_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC697_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC697_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC697_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC697_LAUNCH_DMA 0x01b0 +#define NVC697_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC697_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC697_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC697_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC697_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC697_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC697_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC697_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC697_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC697_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC697_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC697_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC697_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC697_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC697_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC697_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC697_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC697_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC697_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC697_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC697_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC697_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC697_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC697_LOAD_INLINE_DATA 0x01b4 +#define NVC697_LOAD_INLINE_DATA_V 31:0 + +#define NVC697_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC697_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC697_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC697_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC697_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC697_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC697_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC697_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC697_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC697_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC697_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC697_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC697_RUN_DS_NOW 0x0200 +#define NVC697_RUN_DS_NOW_V 31:0 + +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC697_SET_GS_MODE 0x0208 +#define NVC697_SET_GS_MODE_TYPE 0:0 +#define NVC697_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVC697_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVC697_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC697_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC697_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC697_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC697_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC697_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_GS_DM_FIFO 0x0214 +#define NVC697_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC697_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC697_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC697_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC697_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC697_INVALIDATE_SHADER_CACHES 0x021c +#define NVC697_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC697_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC697_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC697_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC697_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC697_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC697_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC697_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC697_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC697_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC697_SET_INSTANCE_COUNT 0x0220 +#define NVC697_SET_INSTANCE_COUNT_V 31:0 + +#define NVC697_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVC697_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVC697_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC697_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVC697_SET_MME_VERSION 0x0234 +#define NVC697_SET_MME_VERSION_MAJOR 7:0 + +#define NVC697_SET_INDEX_BUFFER_SIZE_A 0x0238 +#define NVC697_SET_INDEX_BUFFER_SIZE_A_UPPER 7:0 + +#define NVC697_SET_INDEX_BUFFER_SIZE_B 0x023c +#define NVC697_SET_INDEX_BUFFER_SIZE_B_LOWER 31:0 + +#define NVC697_SET_ROOT_TABLE_VISIBILITY(i) (0x0240+(i)*4) +#define NVC697_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP0_ENABLE 1:0 +#define NVC697_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP1_ENABLE 5:4 +#define NVC697_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP2_ENABLE 9:8 +#define NVC697_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP3_ENABLE 13:12 +#define NVC697_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP4_ENABLE 17:16 + +#define NVC697_SET_DRAW_CONTROL_A 0x0260 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY 3:0 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_POINTS 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_LINES 0x00000001 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_QUADS 0x00000007 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_PATCH 0x0000000E +#define NVC697_SET_DRAW_CONTROL_A_PRIMITIVE_ID 4:4 +#define NVC697_SET_DRAW_CONTROL_A_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ID 6:5 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ID_FIRST 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC697_SET_DRAW_CONTROL_A_SPLIT_MODE 8:7 +#define NVC697_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC697_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC697_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE 9:9 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 +#define NVC697_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX 10:10 +#define NVC697_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_FALSE 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_TRUE 0x00000001 +#define NVC697_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX 11:11 +#define NVC697_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_FALSE 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_TRUE 0x00000001 + +#define NVC697_SET_DRAW_CONTROL_B 0x0264 +#define NVC697_SET_DRAW_CONTROL_B_INSTANCE_COUNT 31:0 + +#define NVC697_DRAW_INDEX_BUFFER_BEGIN_END_A 0x0268 +#define NVC697_DRAW_INDEX_BUFFER_BEGIN_END_A_FIRST 31:0 + +#define NVC697_DRAW_INDEX_BUFFER_BEGIN_END_B 0x026c +#define NVC697_DRAW_INDEX_BUFFER_BEGIN_END_B_COUNT 31:0 + +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_A 0x0270 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_A_START 31:0 + +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_B 0x0274 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_B_COUNT 31:0 + +#define NVC697_INVALIDATE_RASTER_CACHE_NO_WFI 0x027c +#define NVC697_INVALIDATE_RASTER_CACHE_NO_WFI_V 0:0 + +#define NVC697_SET_COLOR_RENDER_TO_ZETA_SURFACE 0x02b8 +#define NVC697_SET_COLOR_RENDER_TO_ZETA_SURFACE_V 0:0 +#define NVC697_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_FALSE 0x00000000 +#define NVC697_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_TRUE 0x00000001 + +#define NVC697_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION 0x02bc +#define NVC697_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V 0:0 +#define NVC697_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_FALSE 0x00000000 +#define NVC697_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_TRUE 0x00000001 + +#define NVC697_INCREMENT_SYNC_POINT 0x02c8 +#define NVC697_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC697_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC697_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC697_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC697_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC697_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC697_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC697_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC697_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC697_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC697_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVC697_DECOMPRESS_SURFACE 0x02e0 +#define NVC697_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC697_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC697_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC697_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC697_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC697_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC697_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC697_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC697_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC697_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC697_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC697_SET_ZCULL_SUBREGION 0x02e8 +#define NVC697_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC697_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC697_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC697_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC697_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC697_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC697_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC697_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC697_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC697_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC697_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC697_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC697_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC697_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC697_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC697_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC697_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC697_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC697_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC697_DRAW_ZERO_INDEX 0x0304 +#define NVC697_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC697_SET_L1_CONFIGURATION 0x0308 +#define NVC697_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC697_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC697_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC697_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC697_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC697_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC697_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC697_SET_SPA_VERSION 0x0310 +#define NVC697_SET_SPA_VERSION_MINOR 7:0 +#define NVC697_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC697_SET_TIMESLICE_BATCH_LIMIT 0x0314 +#define NVC697_SET_TIMESLICE_BATCH_LIMIT_BATCH_LIMIT 15:0 + +#define NVC697_SET_SNAP_GRID_LINE 0x0318 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC697_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC697_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC697_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC697_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC697_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC697_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC697_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC697_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC697_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC697_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC697_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC697_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC697_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC697_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC697_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC697_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC697_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC697_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC697_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC697_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC697_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC697_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC697_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC697_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC697_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC697_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC697_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC697_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC697_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC697_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC697_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC697_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC697_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC697_RESERVED_TG07 0x033c +#define NVC697_RESERVED_TG07_V 0:0 + +#define NVC697_RESERVED_TG08 0x0340 +#define NVC697_RESERVED_TG08_V 0:0 + +#define NVC697_RESERVED_TG09 0x0344 +#define NVC697_RESERVED_TG09_V 0:0 + +#define NVC697_RESERVED_TG10 0x0348 +#define NVC697_RESERVED_TG10_V 0:0 + +#define NVC697_RESERVED_TG11 0x034c +#define NVC697_RESERVED_TG11_V 0:0 + +#define NVC697_RESERVED_TG12 0x0350 +#define NVC697_RESERVED_TG12_V 0:0 + +#define NVC697_RESERVED_TG13 0x0354 +#define NVC697_RESERVED_TG13_V 0:0 + +#define NVC697_RESERVED_TG14 0x0358 +#define NVC697_RESERVED_TG14_V 0:0 + +#define NVC697_RESERVED_TG15 0x035c +#define NVC697_RESERVED_TG15_V 0:0 + +#define NVC697_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC697_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC697_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC697_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC697_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC697_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC697_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC697_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC697_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC697_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC697_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC697_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC697_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC697_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC697_SET_RASTER_ENABLE 0x037c +#define NVC697_SET_RASTER_ENABLE_V 0:0 +#define NVC697_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC697_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC697_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC697_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC697_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC697_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC697_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC697_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC697_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC697_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC697_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVC697_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVC697_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVC697_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVC697_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVC697_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVC697_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVC697_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVC697_SET_ROOT_TABLE_SELECTOR 0x0504 +#define NVC697_SET_ROOT_TABLE_SELECTOR_ROOT_TABLE 2:0 +#define NVC697_SET_ROOT_TABLE_SELECTOR_OFFSET 15:8 + +#define NVC697_LOAD_ROOT_TABLE 0x0508 +#define NVC697_LOAD_ROOT_TABLE_V 31:0 + +#define NVC697_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVC697_SET_MME_MEM_ADDRESS_A_UPPER 7:0 + +#define NVC697_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVC697_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVC697_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVC697_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVC697_MME_DMA_READ 0x055c +#define NVC697_MME_DMA_READ_LENGTH 31:0 + +#define NVC697_MME_DMA_READ_FIFOED 0x0560 +#define NVC697_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVC697_MME_DMA_WRITE 0x0564 +#define NVC697_MME_DMA_WRITE_LENGTH 31:0 + +#define NVC697_MME_DMA_REDUCTION 0x0568 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVC697_MME_DMA_SYSMEMBAR 0x056c +#define NVC697_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVC697_MME_DMA_SYNC 0x0570 +#define NVC697_MME_DMA_SYNC_VALUE 31:0 + +#define NVC697_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NVC697_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NVC697_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NVC697_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NVC697_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NVC697_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NVC697_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NVC697_SET_VERTEX_STREAM_SIZE_A(j) (0x0600+(j)*8) +#define NVC697_SET_VERTEX_STREAM_SIZE_A_UPPER 7:0 + +#define NVC697_SET_VERTEX_STREAM_SIZE_B(j) (0x0604+(j)*8) +#define NVC697_SET_VERTEX_STREAM_SIZE_B_LOWER 31:0 + +#define NVC697_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC697_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC697_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC697_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC697_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC697_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC697_SET_RASTER_INPUT 0x0740 +#define NVC697_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC697_SET_STREAM_OUTPUT 0x0744 +#define NVC697_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC697_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC697_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC697_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC697_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC697_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC697_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC697_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC697_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC697_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC697_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC697_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC697_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC697_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC697_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC697_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC697_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC697_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC697_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC697_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC697_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC697_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC697_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC697_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC697_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC697_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVC697_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC697_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC697_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC697_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC697_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC697_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC697_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC697_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC697_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC697_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC697_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC697_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC697_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC697_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC697_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC697_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC697_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC697_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC697_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC697_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC697_SET_ZCULL_STORAGE_B 0x07ec +#define NVC697_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC697_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC697_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC697_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC697_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC697_SET_ZT_READ_ONLY 0x07f8 +#define NVC697_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC697_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC697_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC697_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC697_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC697_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC697_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC697_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC697_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC697_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC697_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC697_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC697_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC697_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC697_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC697_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC697_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC697_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC697_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC697_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC697_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC697_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC697_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC697_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC697_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC697_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC697_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC697_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC697_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC697_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC697_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC697_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC697_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC697_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC697_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC697_SET_COLOR_TARGET_RESERVED_A(j) (0x0824+(j)*64) +#define NVC697_SET_COLOR_TARGET_RESERVED_A_V 0:0 + +#define NVC697_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC697_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC697_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC697_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC697_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC697_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC697_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC697_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC697_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC697_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC697_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC697_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC697_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC697_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC697_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC697_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC697_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC697_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC697_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC697_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC697_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC697_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC697_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC697_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC697_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC697_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC697_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC697_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC697_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC697_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC697_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC697_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC697_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC697_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC697_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC697_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC697_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC697_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC697_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC697_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC697_SET_STATISTICS_COUNTER 0x0d68 +#define NVC697_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC697_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC697_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC697_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC697_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC697_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC697_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC697_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC697_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC697_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC697_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC697_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC697_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC697_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC697_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC697_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC697_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVC697_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC697_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC697_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC697_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC697_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC697_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC697_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC697_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC697_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC697_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC697_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC697_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC697_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC697_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC697_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC697_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC697_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC697_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC697_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC697_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC697_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC697_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC697_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC697_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC697_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC697_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC697_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC697_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC697_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC697_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC697_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC697_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC697_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC697_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC697_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC697_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC697_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC697_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC697_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC697_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC697_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC697_SET_POLY_SMOOTH 0x0db4 +#define NVC697_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC697_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC697_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC697_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC697_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC697_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC697_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC697_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC697_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC697_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_PATCH 0x0dcc +#define NVC697_SET_PATCH_SIZE 7:0 + +#define NVC697_SET_ITERATED_BLEND 0x0dd0 +#define NVC697_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC697_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC697_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC697_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC697_SET_ZCULL_CRITERION 0x0dd8 +#define NVC697_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC697_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC697_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC697_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC697_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC697_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC697_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC697_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC697_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC697_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC697_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC697_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC697_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC697_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC697_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC697_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC697_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC697_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC697_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC697_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC697_SET_SCISSOR_ENABLE_V 0:0 +#define NVC697_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC697_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC697_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC697_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC697_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC697_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC697_SET_VPC_PERF_KNOB 0x0f14 +#define NVC697_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC697_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC697_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC697_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC697_PM_LOCAL_TRIGGER 0x0f18 +#define NVC697_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC697_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC697_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC697_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC697_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC697_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC697_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC697_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC697_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC697_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC697_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC697_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC697_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC697_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC697_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC697_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC697_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC697_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC697_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC697_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC697_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC697_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC697_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC697_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC697_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC697_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC697_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC697_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC697_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC697_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC697_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC697_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC697_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC697_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC697_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC697_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC697_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC697_SET_SAMPLE_MASK 0x0fa4 +#define NVC697_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC697_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC697_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC697_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC697_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC697_SET_CT_MRT_ENABLE 0x0fac +#define NVC697_SET_CT_MRT_ENABLE_V 0:0 +#define NVC697_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC697_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC697_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC697_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC697_SET_TIR 0x0fb4 +#define NVC697_SET_TIR_MODE 1:0 +#define NVC697_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC697_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC697_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC697_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC697_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC697_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC697_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC697_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC697_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC697_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC697_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC697_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC697_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC697_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC697_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC697_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC697_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC697_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC697_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC697_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_TIR_MODULATION 0x0fd4 +#define NVC697_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC697_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC697_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC697_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC697_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC697_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC697_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC697_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC697_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC697_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC697_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC697_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC697_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC697_SET_ZT_A 0x0fe0 +#define NVC697_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_ZT_B 0x0fe4 +#define NVC697_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_ZT_FORMAT 0x0fe8 +#define NVC697_SET_ZT_FORMAT_V 4:0 +#define NVC697_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC697_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC697_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC697_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC697_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC697_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC697_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC697_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC697_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC697_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC697_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC697_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC697_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC697_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC697_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC697_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC697_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC697_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC697_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC697_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC697_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC697_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC697_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC697_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC697_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC697_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC697_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC697_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC697_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC697_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC697_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC697_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC697_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC697_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC697_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC697_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC697_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC697_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC697_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC697_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC697_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC697_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC697_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC697_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC697_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC697_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD02 0x102c +#define NVC697_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC697_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC697_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC697_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC697_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC697_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC697_SET_SPARE_NOOP01 0x1044 +#define NVC697_SET_SPARE_NOOP01_V 31:0 + +#define NVC697_SET_SPARE_NOOP02 0x1048 +#define NVC697_SET_SPARE_NOOP02_V 31:0 + +#define NVC697_SET_SPARE_NOOP03 0x104c +#define NVC697_SET_SPARE_NOOP03_V 31:0 + +#define NVC697_SET_SPARE_NOOP04 0x1050 +#define NVC697_SET_SPARE_NOOP04_V 31:0 + +#define NVC697_SET_SPARE_NOOP05 0x1054 +#define NVC697_SET_SPARE_NOOP05_V 31:0 + +#define NVC697_SET_SPARE_NOOP06 0x1058 +#define NVC697_SET_SPARE_NOOP06_V 31:0 + +#define NVC697_SET_SPARE_NOOP07 0x105c +#define NVC697_SET_SPARE_NOOP07_V 31:0 + +#define NVC697_SET_SPARE_NOOP08 0x1060 +#define NVC697_SET_SPARE_NOOP08_V 31:0 + +#define NVC697_SET_SPARE_NOOP09 0x1064 +#define NVC697_SET_SPARE_NOOP09_V 31:0 + +#define NVC697_SET_SPARE_NOOP10 0x1068 +#define NVC697_SET_SPARE_NOOP10_V 31:0 + +#define NVC697_SET_SPARE_NOOP11 0x106c +#define NVC697_SET_SPARE_NOOP11_V 31:0 + +#define NVC697_SET_SPARE_NOOP12 0x1070 +#define NVC697_SET_SPARE_NOOP12_V 31:0 + +#define NVC697_SET_SPARE_NOOP13 0x1074 +#define NVC697_SET_SPARE_NOOP13_V 31:0 + +#define NVC697_SET_SPARE_NOOP14 0x1078 +#define NVC697_SET_SPARE_NOOP14_V 31:0 + +#define NVC697_SET_SPARE_NOOP15 0x107c +#define NVC697_SET_SPARE_NOOP15_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC697_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC697_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC697_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC697_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC697_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC697_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC697_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC697_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC697_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC697_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC697_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC697_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC697_UNBIND_ALL 0x10f4 +#define NVC697_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC697_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC697_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC697_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC697_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC697_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC697_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC697_NO_OPERATION_DATA_HI 0x110c +#define NVC697_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC697_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC697_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC697_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC697_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC697_PM_TRIGGER_END 0x1114 +#define NVC697_PM_TRIGGER_END_V 31:0 + +#define NVC697_SET_VERTEX_ID_BASE 0x1118 +#define NVC697_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC697_SET_STENCIL_COMPRESSION 0x111c +#define NVC697_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC697_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC697_SET_TIR_CONTROL 0x1130 +#define NVC697_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC697_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC697_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC697_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC697_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC697_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC697_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC697_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC697_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 + +#define NVC697_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC697_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC697_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC697_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC697_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC697_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC697_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC697_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC697_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC697_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC697_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC697_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC697_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC697_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC697_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC697_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC697_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC697_FLUSH_PENDING_WRITES 0x1144 +#define NVC697_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC697_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC697_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC697_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC697_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC697_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC697_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC697_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC697_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC697_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC697_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC697_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC697_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC697_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC697_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC697_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC697_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC697_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC697_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC697_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC697_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC697_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC697_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_SCREEN_STATE_MASK 0x1204 +#define NVC697_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC697_SET_ZT_SPARSE 0x1208 +#define NVC697_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC697_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC697_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC697_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_SET_CT_SELECT 0x121c +#define NVC697_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC697_SET_CT_SELECT_TARGET0 6:4 +#define NVC697_SET_CT_SELECT_TARGET1 9:7 +#define NVC697_SET_CT_SELECT_TARGET2 12:10 +#define NVC697_SET_CT_SELECT_TARGET3 15:13 +#define NVC697_SET_CT_SELECT_TARGET4 18:16 +#define NVC697_SET_CT_SELECT_TARGET5 21:19 +#define NVC697_SET_CT_SELECT_TARGET6 24:22 +#define NVC697_SET_CT_SELECT_TARGET7 27:25 + +#define NVC697_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC697_SET_ZT_SIZE_A 0x1228 +#define NVC697_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC697_SET_ZT_SIZE_B 0x122c +#define NVC697_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC697_SET_ZT_SIZE_C 0x1230 +#define NVC697_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC697_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC697_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC697_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC697_SET_SAMPLER_BINDING 0x1234 +#define NVC697_SET_SAMPLER_BINDING_V 0:0 +#define NVC697_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC697_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC697_DRAW_AUTO 0x123c +#define NVC697_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC697_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC697_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC697_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC697_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC697_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC697_SET_BACK_END_COPY_A 0x1264 +#define NVC697_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC697_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC697_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC697_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC697_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BACK_END_COPY_B 0x1268 +#define NVC697_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC697_SET_BACK_END_COPY_C 0x126c +#define NVC697_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC697_SET_BACK_END_COPY_D 0x1270 +#define NVC697_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC697_SET_BACK_END_COPY_E 0x1274 +#define NVC697_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC697_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC697_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVC697_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC697_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC697_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC697_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC697_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC697_CLEAR_ZCULL_REGION 0x12c8 +#define NVC697_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC697_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC697_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC697_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC697_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC697_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC697_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC697_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC697_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC697_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC697_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC697_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC697_SET_DEPTH_TEST 0x12cc +#define NVC697_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC697_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_FILL_MODE 0x12d0 +#define NVC697_SET_FILL_MODE_V 31:0 +#define NVC697_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC697_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC697_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC697_SET_SHADE_MODE 0x12d4 +#define NVC697_SET_SHADE_MODE_V 31:0 +#define NVC697_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC697_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC697_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC697_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC697_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC697_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC697_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC697_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC697_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC697_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC697_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC697_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_DEPTH_WRITE 0x12e8 +#define NVC697_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC697_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_ALPHA_TEST 0x12ec +#define NVC697_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC697_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC697_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC697_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC697_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC697_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC697_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC697_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC697_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC697_D3D_SET_CULL_MODE 0x1308 +#define NVC697_D3D_SET_CULL_MODE_V 31:0 +#define NVC697_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC697_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC697_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC697_SET_DEPTH_FUNC 0x130c +#define NVC697_SET_DEPTH_FUNC_V 31:0 +#define NVC697_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC697_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC697_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC697_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC697_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC697_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC697_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC697_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC697_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC697_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC697_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC697_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC697_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC697_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC697_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC697_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC697_SET_ALPHA_REF 0x1310 +#define NVC697_SET_ALPHA_REF_V 31:0 + +#define NVC697_SET_ALPHA_FUNC 0x1314 +#define NVC697_SET_ALPHA_FUNC_V 31:0 +#define NVC697_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC697_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC697_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC697_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC697_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC697_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC697_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC697_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC697_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC697_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC697_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC697_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC697_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC697_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC697_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC697_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC697_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC697_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC697_SET_BLEND_CONST_RED 0x131c +#define NVC697_SET_BLEND_CONST_RED_V 31:0 + +#define NVC697_SET_BLEND_CONST_GREEN 0x1320 +#define NVC697_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC697_SET_BLEND_CONST_BLUE 0x1324 +#define NVC697_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC697_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC697_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC697_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC697_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC697_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC697_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC697_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC697_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC697_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC697_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BLEND_COLOR_OP 0x1340 +#define NVC697_SET_BLEND_COLOR_OP_V 31:0 +#define NVC697_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC697_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC697_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC697_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC697_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC697_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC697_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC697_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC697_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC697_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_BLEND_ALPHA_OP 0x134c +#define NVC697_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC697_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC697_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC697_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC697_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC697_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC697_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC697_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC697_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC697_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC697_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC697_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC697_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC697_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC697_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC697_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BLEND(i) (0x1360+(i)*4) +#define NVC697_SET_BLEND_ENABLE 0:0 +#define NVC697_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_STENCIL_TEST 0x1380 +#define NVC697_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC697_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_STENCIL_OP_FAIL 0x1384 +#define NVC697_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC697_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC697_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC697_SET_STENCIL_OP_ZPASS 0x138c +#define NVC697_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC697_SET_STENCIL_FUNC 0x1390 +#define NVC697_SET_STENCIL_FUNC_V 31:0 +#define NVC697_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC697_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC697_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC697_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC697_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC697_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC697_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC697_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC697_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC697_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC697_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC697_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC697_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC697_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC697_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC697_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC697_SET_STENCIL_FUNC_REF 0x1394 +#define NVC697_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC697_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC697_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC697_SET_STENCIL_MASK 0x139c +#define NVC697_SET_STENCIL_MASK_V 7:0 + +#define NVC697_SET_DRAW_AUTO_START 0x13a4 +#define NVC697_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC697_SET_PS_SATURATE 0x13a8 +#define NVC697_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC697_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC697_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC697_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC697_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC697_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC697_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC697_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC697_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC697_SET_WINDOW_ORIGIN 0x13ac +#define NVC697_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC697_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC697_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC697_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC697_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC697_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC697_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC697_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC697_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC697_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC697_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC697_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC697_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC697_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC697_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC697_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC697_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC697_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC697_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC697_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC697_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC697_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC697_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC697_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC697_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC697_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC697_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC697_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC697_STORE_ZCULL 0x1464 +#define NVC697_STORE_ZCULL_V 0:0 + +#define NVC697_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC697_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC697_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC697_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC697_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC697_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC697_LOAD_ZCULL 0x1500 +#define NVC697_LOAD_ZCULL_V 0:0 + +#define NVC697_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC697_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC697_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC697_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC697_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC697_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC697_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC697_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC697_SET_USER_CLIP_ENABLE 0x1510 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC697_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC697_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC697_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_POINT_SIZE 0x1518 +#define NVC697_SET_POINT_SIZE_V 31:0 + +#define NVC697_SET_ZCULL_STATS 0x151c +#define NVC697_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC697_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_POINT_SPRITE 0x1520 +#define NVC697_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC697_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC697_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC697_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC697_CLEAR_REPORT_VALUE 0x1530 +#define NVC697_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC697_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC697_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC697_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC697_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC697_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC697_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVC697_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC697_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC697_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_ZT_SELECT 0x1538 +#define NVC697_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC697_SET_RENDER_ENABLE_A 0x1550 +#define NVC697_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_RENDER_ENABLE_B 0x1554 +#define NVC697_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_RENDER_ENABLE_C 0x1558 +#define NVC697_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC697_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC697_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC697_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC697_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC697_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC697_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC697_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC697_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC697_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC697_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC697_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC697_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC697_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC697_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC697_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC697_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_TEX_HEADER_POOL_C 0x157c +#define NVC697_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC697_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC697_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC697_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC697_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC697_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC697_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC697_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC697_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC697_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC697_SET_SRGB_WRITE 0x15b8 +#define NVC697_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC697_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_DEPTH_BIAS 0x15bc +#define NVC697_SET_DEPTH_BIAS_V 31:0 + +#define NVC697_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC697_SET_RT_LAYER 0x15cc +#define NVC697_SET_RT_LAYER_V 15:0 +#define NVC697_SET_RT_LAYER_CONTROL 16:16 +#define NVC697_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC697_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC697_SET_ANTI_ALIAS 0x15d0 +#define NVC697_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC697_SET_EDGE_FLAG 0x15e4 +#define NVC697_SET_EDGE_FLAG_V 0:0 +#define NVC697_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC697_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC697_DRAW_INLINE_INDEX 0x15e8 +#define NVC697_DRAW_INLINE_INDEX_V 31:0 + +#define NVC697_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC697_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC697_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC697_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC697_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC697_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC697_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC697_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC697_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC697_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC697_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC697_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC697_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC697_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC697_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC697_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC697_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC697_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC697_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC697_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC697_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC697_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC697_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC697_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC697_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC697_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC697_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC697_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC697_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC697_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC697_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC697_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC697_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC697_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC697_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC697_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC697_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC697_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC697_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC697_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC697_END 0x1614 +#define NVC697_END_V 0:0 + +#define NVC697_BEGIN 0x1618 +#define NVC697_BEGIN_OP 15:0 +#define NVC697_BEGIN_OP_POINTS 0x00000000 +#define NVC697_BEGIN_OP_LINES 0x00000001 +#define NVC697_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC697_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC697_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC697_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC697_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC697_BEGIN_OP_QUADS 0x00000007 +#define NVC697_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC697_BEGIN_OP_POLYGON 0x00000009 +#define NVC697_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC697_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC697_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_BEGIN_OP_PATCH 0x0000000E +#define NVC697_BEGIN_PRIMITIVE_ID 24:24 +#define NVC697_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC697_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC697_BEGIN_INSTANCE_ID 27:26 +#define NVC697_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC697_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC697_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC697_BEGIN_SPLIT_MODE 30:29 +#define NVC697_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC697_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC697_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC697_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC697_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVC697_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC697_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_VERTEX_ID_COPY 0x161c +#define NVC697_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC697_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC697_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC697_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC697_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC697_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC697_LOAD_PRIMITIVE_ID 0x1624 +#define NVC697_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC697_SET_SHADER_BASED_CULL 0x162c +#define NVC697_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC697_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC697_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC697_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_CLASS_VERSION 0x1638 +#define NVC697_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC697_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC697_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC697_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC697_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC697_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC697_SET_DA_OUTPUT 0x164c +#define NVC697_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC697_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC697_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC697_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC697_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_POINT_CENTER_MODE 0x165c +#define NVC697_SET_POINT_CENTER_MODE_V 31:0 +#define NVC697_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC697_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC697_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC697_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC697_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC697_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC697_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC697_SET_LINE_STIPPLE 0x166c +#define NVC697_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC697_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC697_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC697_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC697_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC697_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC697_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC697_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC697_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC697_SET_PROVOKING_VERTEX 0x1684 +#define NVC697_SET_PROVOKING_VERTEX_V 0:0 +#define NVC697_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC697_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC697_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC697_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC697_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_POLYGON_STIPPLE 0x168c +#define NVC697_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC697_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_SHADER_CONTROL 0x1690 +#define NVC697_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC697_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC697_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC697_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC697_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC697_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC697_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC697_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC697_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC697_CHECK_CLASS_VERSION 0x16a0 +#define NVC697_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC697_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC697_SET_SPH_VERSION 0x16a4 +#define NVC697_SET_SPH_VERSION_CURRENT 15:0 +#define NVC697_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC697_CHECK_SPH_VERSION 0x16a8 +#define NVC697_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC697_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC697_SET_SCG_GRAPHICS_PRIORITY 0x16bc +#define NVC697_SET_SCG_GRAPHICS_PRIORITY_PRIORITY 5:0 + +#define NVC697_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS(i) (0x16c0+(i)*4) +#define NVC697_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC697_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC697_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC697_SET_AAM_VERSION 0x1790 +#define NVC697_SET_AAM_VERSION_CURRENT 15:0 +#define NVC697_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC697_CHECK_AAM_VERSION 0x1794 +#define NVC697_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC697_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC697_SET_ZT_LAYER 0x179c +#define NVC697_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC697_SET_INDEX_BUFFER_A 0x17c8 +#define NVC697_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC697_SET_INDEX_BUFFER_B 0x17cc +#define NVC697_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC697_SET_INDEX_BUFFER_E 0x17d8 +#define NVC697_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC697_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC697_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC697_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC697_SET_INDEX_BUFFER_F 0x17dc +#define NVC697_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC697_DRAW_INDEX_BUFFER 0x17e0 +#define NVC697_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC697_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC697_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC697_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC697_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC697_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC697_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC697_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC697_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC697_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC697_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC697_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC697_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC697_OGL_SET_CULL 0x1918 +#define NVC697_OGL_SET_CULL_ENABLE 0:0 +#define NVC697_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC697_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC697_OGL_SET_FRONT_FACE 0x191c +#define NVC697_OGL_SET_FRONT_FACE_V 31:0 +#define NVC697_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC697_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC697_OGL_SET_CULL_FACE 0x1920 +#define NVC697_OGL_SET_CULL_FACE_V 31:0 +#define NVC697_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC697_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC697_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC697_SET_VIEWPORT_PIXEL 0x1924 +#define NVC697_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC697_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC697_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC697_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC697_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC697_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC697_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE 17:16 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_USE_FIELD_MIN_Z_ZERO_MAX_Z_ONE 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MIN_Z_MAX_Z 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_ZERO_ONE 0x00000002 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MINUS_INF_PLUS_INF 0x00000003 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC697_SET_USER_CLIP_OP 0x1940 +#define NVC697_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC697_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC697_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC697_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC697_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC697_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC697_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC697_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC697_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC697_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC697_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC697_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC697_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC697_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC697_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC697_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC697_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC697_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC697_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC697_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC697_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC697_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC697_INVALIDATE_ZCULL 0x1958 +#define NVC697_INVALIDATE_ZCULL_V 31:0 +#define NVC697_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC697_SET_ZCULL 0x1968 +#define NVC697_SET_ZCULL_Z_ENABLE 0:0 +#define NVC697_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC697_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_ZCULL_BOUNDS 0x196c +#define NVC697_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC697_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC697_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC697_ZCULL_SYNC 0x1978 +#define NVC697_ZCULL_SYNC_V 31:0 + +#define NVC697_SET_CLIP_ID_TEST 0x197c +#define NVC697_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC697_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC697_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC697_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC697_SET_CLIP_ID 0x1984 +#define NVC697_SET_CLIP_ID_V 31:0 + +#define NVC697_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC697_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC697_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC697_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC697_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC697_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC697_SET_LOGIC_OP 0x19c4 +#define NVC697_SET_LOGIC_OP_ENABLE 0:0 +#define NVC697_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC697_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC697_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC697_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC697_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC697_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC697_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC697_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC697_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC697_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC697_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC697_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC697_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC697_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC697_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC697_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC697_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC697_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC697_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC697_SET_Z_COMPRESSION 0x19cc +#define NVC697_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC697_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC697_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC697_CLEAR_SURFACE 0x19d0 +#define NVC697_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC697_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC697_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC697_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC697_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC697_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC697_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC697_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC697_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC697_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC697_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC697_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC697_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC697_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC697_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC697_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC697_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC697_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC697_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC697_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC697_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC697_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC697_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC697_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC697_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC697_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC697_PIPE_NOP 0x1a2c +#define NVC697_PIPE_NOP_V 31:0 + +#define NVC697_SET_SPARE00 0x1a30 +#define NVC697_SET_SPARE00_V 31:0 + +#define NVC697_SET_SPARE01 0x1a34 +#define NVC697_SET_SPARE01_V 31:0 + +#define NVC697_SET_SPARE02 0x1a38 +#define NVC697_SET_SPARE02_V 31:0 + +#define NVC697_SET_SPARE03 0x1a3c +#define NVC697_SET_SPARE03_V 31:0 + +#define NVC697_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC697_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC697_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC697_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC697_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC697_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC697_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC697_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC697_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC697_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC697_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC697_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC697_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC697_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC697_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC697_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC697_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC697_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC697_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC697_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC697_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC697_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC697_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC697_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC697_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC697_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC697_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC697_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC697_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC697_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC697_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC697_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC697_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC697_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC697_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC697_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC697_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC697_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC697_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC697_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC697_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC697_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC697_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC697_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC697_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC697_SET_PIPELINE_RESERVED_B(j) (0x2004+(j)*64) +#define NVC697_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVC697_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC697_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC697_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC697_SET_PIPELINE_REGISTER_COUNT_V 8:0 + +#define NVC697_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC697_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC697_SET_PIPELINE_PROGRAM_ADDRESS_A(j) (0x2014+(j)*64) +#define NVC697_SET_PIPELINE_PROGRAM_ADDRESS_A_UPPER 7:0 + +#define NVC697_SET_PIPELINE_PROGRAM_ADDRESS_B(j) (0x2018+(j)*64) +#define NVC697_SET_PIPELINE_PROGRAM_ADDRESS_B_LOWER 31:0 + +#define NVC697_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVC697_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVC697_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC697_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC697_SET_FALCON00 0x2300 +#define NVC697_SET_FALCON00_V 31:0 + +#define NVC697_SET_FALCON01 0x2304 +#define NVC697_SET_FALCON01_V 31:0 + +#define NVC697_SET_FALCON02 0x2308 +#define NVC697_SET_FALCON02_V 31:0 + +#define NVC697_SET_FALCON03 0x230c +#define NVC697_SET_FALCON03_V 31:0 + +#define NVC697_SET_FALCON04 0x2310 +#define NVC697_SET_FALCON04_V 31:0 + +#define NVC697_SET_FALCON05 0x2314 +#define NVC697_SET_FALCON05_V 31:0 + +#define NVC697_SET_FALCON06 0x2318 +#define NVC697_SET_FALCON06_V 31:0 + +#define NVC697_SET_FALCON07 0x231c +#define NVC697_SET_FALCON07_V 31:0 + +#define NVC697_SET_FALCON08 0x2320 +#define NVC697_SET_FALCON08_V 31:0 + +#define NVC697_SET_FALCON09 0x2324 +#define NVC697_SET_FALCON09_V 31:0 + +#define NVC697_SET_FALCON10 0x2328 +#define NVC697_SET_FALCON10_V 31:0 + +#define NVC697_SET_FALCON11 0x232c +#define NVC697_SET_FALCON11_V 31:0 + +#define NVC697_SET_FALCON12 0x2330 +#define NVC697_SET_FALCON12_V 31:0 + +#define NVC697_SET_FALCON13 0x2334 +#define NVC697_SET_FALCON13_V 31:0 + +#define NVC697_SET_FALCON14 0x2338 +#define NVC697_SET_FALCON14_V 31:0 + +#define NVC697_SET_FALCON15 0x233c +#define NVC697_SET_FALCON15_V 31:0 + +#define NVC697_SET_FALCON16 0x2340 +#define NVC697_SET_FALCON16_V 31:0 + +#define NVC697_SET_FALCON17 0x2344 +#define NVC697_SET_FALCON17_V 31:0 + +#define NVC697_SET_FALCON18 0x2348 +#define NVC697_SET_FALCON18_V 31:0 + +#define NVC697_SET_FALCON19 0x234c +#define NVC697_SET_FALCON19_V 31:0 + +#define NVC697_SET_FALCON20 0x2350 +#define NVC697_SET_FALCON20_V 31:0 + +#define NVC697_SET_FALCON21 0x2354 +#define NVC697_SET_FALCON21_V 31:0 + +#define NVC697_SET_FALCON22 0x2358 +#define NVC697_SET_FALCON22_V 31:0 + +#define NVC697_SET_FALCON23 0x235c +#define NVC697_SET_FALCON23_V 31:0 + +#define NVC697_SET_FALCON24 0x2360 +#define NVC697_SET_FALCON24_V 31:0 + +#define NVC697_SET_FALCON25 0x2364 +#define NVC697_SET_FALCON25_V 31:0 + +#define NVC697_SET_FALCON26 0x2368 +#define NVC697_SET_FALCON26_V 31:0 + +#define NVC697_SET_FALCON27 0x236c +#define NVC697_SET_FALCON27_V 31:0 + +#define NVC697_SET_FALCON28 0x2370 +#define NVC697_SET_FALCON28_V 31:0 + +#define NVC697_SET_FALCON29 0x2374 +#define NVC697_SET_FALCON29_V 31:0 + +#define NVC697_SET_FALCON30 0x2378 +#define NVC697_SET_FALCON30_V 31:0 + +#define NVC697_SET_FALCON31 0x237c +#define NVC697_SET_FALCON31_V 31:0 + +#define NVC697_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC697_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC697_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC697_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC697_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC697_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC697_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC697_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC697_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC697_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC697_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC697_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC697_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC697_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC697_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC697_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC697_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC697_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC697_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC697_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC697_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC697_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC697_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC697_SET_TRAP_HANDLER_A 0x25f8 +#define NVC697_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC697_SET_TRAP_HANDLER_B 0x25fc +#define NVC697_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC697_SET_COLOR_CLAMP 0x2600 +#define NVC697_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC697_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC697_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC697_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC697_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC697_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC697_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC697_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC697_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC697_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC697_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC697_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC697_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC697_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC697_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC697_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC697_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC697_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC697_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC697_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC697_CALL_MME_MACRO_V 31:0 + +#define NVC697_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC697_CALL_MME_DATA_V 31:0 + +#endif /* _cl_ampere_a_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc6b0.h b/userspace/sdks/nv570/nvidia/inc/class/clc6b0.h new file mode 100644 index 0000000..d36f053 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc6b0.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clc6b0_h_ +#define clc6b0_h_ + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC6B0_VIDEO_DECODER (0x0000C6B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc6b0_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc6b5.h b/userspace/sdks/nv570/nvidia/inc/class/clc6b5.h new file mode 100644 index 0000000..873ca74 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc6b5.h @@ -0,0 +1,282 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clc6b5_h_ +#define _clc6b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define AMPERE_DMA_COPY_A (0x0000C6B5) + +#define NVC6B5_NOP (0x00000100) +#define NVC6B5_NOP_PARAMETER 31:0 +#define NVC6B5_PM_TRIGGER (0x00000140) +#define NVC6B5_PM_TRIGGER_V 31:0 +#define NVC6B5_SET_SEMAPHORE_A (0x00000240) +#define NVC6B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC6B5_SET_SEMAPHORE_B (0x00000244) +#define NVC6B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC6B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC6B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC6B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC6B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC6B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC6B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC6B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC6B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC6B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC6B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC6B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC6B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC6B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC6B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC6B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC6B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC6B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC6B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC6B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVC6B5_SET_SRC_PHYS_MODE_BASIC_KIND 5:2 +#define NVC6B5_SET_SRC_PHYS_MODE_PEER_ID 8:6 +#define NVC6B5_SET_SRC_PHYS_MODE_FLA 9:9 +#define NVC6B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC6B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC6B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC6B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC6B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC6B5_SET_DST_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVC6B5_SET_DST_PHYS_MODE_BASIC_KIND 5:2 +#define NVC6B5_SET_DST_PHYS_MODE_PEER_ID 8:6 +#define NVC6B5_SET_DST_PHYS_MODE_FLA 9:9 +#define NVC6B5_LAUNCH_DMA (0x00000300) +#define NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC6B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC6B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC6B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC6B5_LAUNCH_DMA_FLUSH_TYPE 25:25 +#define NVC6B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000) +#define NVC6B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE (0x00000003) +#define NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC6B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC6B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC6B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC6B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC6B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC6B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC6B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC6B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC6B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC6B5_LAUNCH_DMA_VPRMODE 23:22 +#define NVC6B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVC6B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC6B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC6B5_LAUNCH_DMA_DISABLE_PLC 26:26 +#define NVC6B5_LAUNCH_DMA_DISABLE_PLC_FALSE (0x00000000) +#define NVC6B5_LAUNCH_DMA_DISABLE_PLC_TRUE (0x00000001) +#define NVC6B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 +#define NVC6B5_OFFSET_IN_UPPER (0x00000400) +#define NVC6B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC6B5_OFFSET_IN_LOWER (0x00000404) +#define NVC6B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC6B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC6B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC6B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC6B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC6B5_PITCH_IN (0x00000410) +#define NVC6B5_PITCH_IN_VALUE 31:0 +#define NVC6B5_PITCH_OUT (0x00000414) +#define NVC6B5_PITCH_OUT_VALUE 31:0 +#define NVC6B5_LINE_LENGTH_IN (0x00000418) +#define NVC6B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC6B5_LINE_COUNT (0x0000041C) +#define NVC6B5_LINE_COUNT_VALUE 31:0 +#define NVC6B5_SET_REMAP_CONST_A (0x00000700) +#define NVC6B5_SET_REMAP_CONST_A_V 31:0 +#define NVC6B5_SET_REMAP_CONST_B (0x00000704) +#define NVC6B5_SET_REMAP_CONST_B_V 31:0 +#define NVC6B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC6B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC6B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC6B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC6B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC6B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC6B5_SET_DST_WIDTH (0x00000710) +#define NVC6B5_SET_DST_WIDTH_V 31:0 +#define NVC6B5_SET_DST_HEIGHT (0x00000714) +#define NVC6B5_SET_DST_HEIGHT_V 31:0 +#define NVC6B5_SET_DST_DEPTH (0x00000718) +#define NVC6B5_SET_DST_DEPTH_V 31:0 +#define NVC6B5_SET_DST_LAYER (0x0000071C) +#define NVC6B5_SET_DST_LAYER_V 31:0 +#define NVC6B5_SET_DST_ORIGIN (0x00000720) +#define NVC6B5_SET_DST_ORIGIN_X 15:0 +#define NVC6B5_SET_DST_ORIGIN_Y 31:16 +#define NVC6B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC6B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC6B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC6B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC6B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC6B5_SET_SRC_WIDTH (0x0000072C) +#define NVC6B5_SET_SRC_WIDTH_V 31:0 +#define NVC6B5_SET_SRC_HEIGHT (0x00000730) +#define NVC6B5_SET_SRC_HEIGHT_V 31:0 +#define NVC6B5_SET_SRC_DEPTH (0x00000734) +#define NVC6B5_SET_SRC_DEPTH_V 31:0 +#define NVC6B5_SET_SRC_LAYER (0x00000738) +#define NVC6B5_SET_SRC_LAYER_V 31:0 +#define NVC6B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC6B5_SET_SRC_ORIGIN_X 15:0 +#define NVC6B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC6B5_SRC_ORIGIN_X (0x00000744) +#define NVC6B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC6B5_SRC_ORIGIN_Y (0x00000748) +#define NVC6B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC6B5_DST_ORIGIN_X (0x0000074C) +#define NVC6B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC6B5_DST_ORIGIN_Y (0x00000750) +#define NVC6B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC6B5_PM_TRIGGER_END (0x00001114) +#define NVC6B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc6b5_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc6b5sw.h b/userspace/sdks/nv570/nvidia/inc/class/clc6b5sw.h new file mode 100644 index 0000000..7a928aa --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc6b5sw.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc6b5sw.finn +// + + + +// +// Using VERSION_0 will cause the API to interpret +// engineType as a CE engine instance. This allows +// for backward compatibility with 85B5sw and 90B5sw. +// +#define NVC6B5_ALLOCATION_PARAMETERS_VERSION_0 0 + +// +// Using VERSION_1 will cause the API to interpret +// engineType as an NV2080_ENGINE_TYPE ordinal. +// +#define NVC6B5_ALLOCATION_PARAMETERS_VERSION_1 1 + +#define NVC6B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc6b5U) + +typedef struct NVC6B5_ALLOCATION_PARAMETERS { + NvU32 version; + NvU32 engineType; +} NVC6B5_ALLOCATION_PARAMETERS; + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc6c0.h b/userspace/sdks/nv570/nvidia/inc/class/clc6c0.h new file mode 100644 index 0000000..48aa385 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc6c0.h @@ -0,0 +1,697 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_ampere_compute_a_h_ +#define _cl_ampere_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl ampere_compute_a */ + +#include "nvtypes.h" + +#define AMPERE_COMPUTE_A 0xC6C0 + +#define NVC6C0_SET_OBJECT 0x0000 +#define NVC6C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC6C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC6C0_NO_OPERATION 0x0100 +#define NVC6C0_NO_OPERATION_V 31:0 + +#define NVC6C0_SET_NOTIFY_A 0x0104 +#define NVC6C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC6C0_SET_NOTIFY_B 0x0108 +#define NVC6C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC6C0_NOTIFY 0x010c +#define NVC6C0_NOTIFY_TYPE 31:0 +#define NVC6C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC6C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC6C0_WAIT_FOR_IDLE 0x0110 +#define NVC6C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC6C0_SEND_GO_IDLE 0x013c +#define NVC6C0_SEND_GO_IDLE_V 31:0 + +#define NVC6C0_PM_TRIGGER 0x0140 +#define NVC6C0_PM_TRIGGER_V 31:0 + +#define NVC6C0_PM_TRIGGER_WFI 0x0144 +#define NVC6C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC6C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC6C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC6C0_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC6C0_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC6C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC6C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC6C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC6C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC6C0_LINE_LENGTH_IN 0x0180 +#define NVC6C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC6C0_LINE_COUNT 0x0184 +#define NVC6C0_LINE_COUNT_VALUE 31:0 + +#define NVC6C0_OFFSET_OUT_UPPER 0x0188 +#define NVC6C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC6C0_OFFSET_OUT 0x018c +#define NVC6C0_OFFSET_OUT_VALUE 31:0 + +#define NVC6C0_PITCH_OUT 0x0190 +#define NVC6C0_PITCH_OUT_VALUE 31:0 + +#define NVC6C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC6C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC6C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC6C0_SET_DST_WIDTH 0x0198 +#define NVC6C0_SET_DST_WIDTH_V 31:0 + +#define NVC6C0_SET_DST_HEIGHT 0x019c +#define NVC6C0_SET_DST_HEIGHT_V 31:0 + +#define NVC6C0_SET_DST_DEPTH 0x01a0 +#define NVC6C0_SET_DST_DEPTH_V 31:0 + +#define NVC6C0_SET_DST_LAYER 0x01a4 +#define NVC6C0_SET_DST_LAYER_V 31:0 + +#define NVC6C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC6C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC6C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC6C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC6C0_LAUNCH_DMA 0x01b0 +#define NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC6C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC6C0_LOAD_INLINE_DATA 0x01b4 +#define NVC6C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC6C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC6C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC6C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC6C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC6C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC6C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC6C0_SET_SM_SCG_CONTROL 0x01e8 +#define NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS 0:0 +#define NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE 0x00000000 +#define NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE 0x00000001 + +#define NVC6C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC6C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC6C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC6C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC6C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC6C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC6C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC6C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC6C0_PERFMON_TRANSFER 0x0210 +#define NVC6C0_PERFMON_TRANSFER_V 31:0 + +#define NVC6C0_SET_QMD_VIRTUALIZATION_BASE_A 0x0214 +#define NVC6C0_SET_QMD_VIRTUALIZATION_BASE_A_ADDRESS_UPPER 7:0 + +#define NVC6C0_SET_QMD_VIRTUALIZATION_BASE_B 0x0218 +#define NVC6C0_SET_QMD_VIRTUALIZATION_BASE_B_ADDRESS_LOWER 31:0 + +#define NVC6C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC6C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC6C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC6C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC6C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC6C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC6C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC6C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC6C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC6C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC6C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC6C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC6C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC6C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC6C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC6C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC6C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC6C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC6C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC6C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC6C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC6C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC6C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC6C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC6C0_SET_SCG_CONTROL 0x0270 +#define NVC6C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 +#define NVC6C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 +#define NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 +#define NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 +#define NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 + +#define NVC6C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC6C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC6C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC6C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC6C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC6C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC6C0_SET_QMD_VERSION 0x0288 +#define NVC6C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC6C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC6C0_CHECK_QMD_VERSION 0x0290 +#define NVC6C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC6C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC6C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC6C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL 0x029c +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_CONSTANT_BUFFER_MASK 7:0 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE 8:8 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE 12:12 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE 16:16 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE 20:20 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE 24:24 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_TRUE 0x00000001 + +#define NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC6C0_SCG_HYSTERESIS_CONTROL 0x02a8 +#define NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 +#define NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 +#define NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 +#define NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 + +#define NVC6C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC6C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC6C0_SEND_PCAS_A 0x02b4 +#define NVC6C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC6C0_SEND_PCAS_B 0x02b8 +#define NVC6C0_SEND_PCAS_B_FROM 23:0 +#define NVC6C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC6C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC6C0_SEND_SIGNALING_PCAS2_B 0x02c0 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION 3:0 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_NOP 0x00000000 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE 0x00000001 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_SCHEDULE 0x00000002 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_COPY_SCHEDULE 0x00000003 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_PUT 0x00000006 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_DECREMENT_DEPENDENCE 0x00000007 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH 0x00000008 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH_SCHEDULE 0x00000009 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_SCHEDULE 0x0000000A +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_FORCE_REQUIRE_SCHEDULING 0x0000000B + +#define NVC6C0_SET_SKED_CACHE_CONTROL 0x02cc +#define NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID 0:0 +#define NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE 0x00000000 +#define NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE 0x00000001 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC6C0_SET_SPA_VERSION 0x0310 +#define NVC6C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC6C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC6C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC6C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC6C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC6C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC6C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC6C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC6C0_SET_FALCON00 0x0500 +#define NVC6C0_SET_FALCON00_V 31:0 + +#define NVC6C0_SET_FALCON01 0x0504 +#define NVC6C0_SET_FALCON01_V 31:0 + +#define NVC6C0_SET_FALCON02 0x0508 +#define NVC6C0_SET_FALCON02_V 31:0 + +#define NVC6C0_SET_FALCON03 0x050c +#define NVC6C0_SET_FALCON03_V 31:0 + +#define NVC6C0_SET_FALCON04 0x0510 +#define NVC6C0_SET_FALCON04_V 31:0 + +#define NVC6C0_SET_FALCON05 0x0514 +#define NVC6C0_SET_FALCON05_V 31:0 + +#define NVC6C0_SET_FALCON06 0x0518 +#define NVC6C0_SET_FALCON06_V 31:0 + +#define NVC6C0_SET_FALCON07 0x051c +#define NVC6C0_SET_FALCON07_V 31:0 + +#define NVC6C0_SET_FALCON08 0x0520 +#define NVC6C0_SET_FALCON08_V 31:0 + +#define NVC6C0_SET_FALCON09 0x0524 +#define NVC6C0_SET_FALCON09_V 31:0 + +#define NVC6C0_SET_FALCON10 0x0528 +#define NVC6C0_SET_FALCON10_V 31:0 + +#define NVC6C0_SET_FALCON11 0x052c +#define NVC6C0_SET_FALCON11_V 31:0 + +#define NVC6C0_SET_FALCON12 0x0530 +#define NVC6C0_SET_FALCON12_V 31:0 + +#define NVC6C0_SET_FALCON13 0x0534 +#define NVC6C0_SET_FALCON13_V 31:0 + +#define NVC6C0_SET_FALCON14 0x0538 +#define NVC6C0_SET_FALCON14_V 31:0 + +#define NVC6C0_SET_FALCON15 0x053c +#define NVC6C0_SET_FALCON15_V 31:0 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC6C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC6C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS(i) (0x0da0+(i)*4) +#define NVC6C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC6C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC6C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC6C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC6C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC6C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC6C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC6C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC6C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC6C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC6C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC6C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC6C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC6C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC6C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC6C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC6C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC6C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC6C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC6C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC6C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC6C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC6C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC6C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC6C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC6C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC6C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC6C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC6C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC6C0_PIPE_NOP 0x1a2c +#define NVC6C0_PIPE_NOP_V 31:0 + +#define NVC6C0_SET_SPARE00 0x1a30 +#define NVC6C0_SET_SPARE00_V 31:0 + +#define NVC6C0_SET_SPARE01 0x1a34 +#define NVC6C0_SET_SPARE01_V 31:0 + +#define NVC6C0_SET_SPARE02 0x1a38 +#define NVC6C0_SET_SPARE02_V 31:0 + +#define NVC6C0_SET_SPARE03 0x1a3c +#define NVC6C0_SET_SPARE03_V 31:0 + +#define NVC6C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC6C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC6C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC6C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC6C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC6C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC6C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC6C0_SET_TRAP_HANDLER_A 0x25f8 +#define NVC6C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC6C0_SET_TRAP_HANDLER_B 0x25fc +#define NVC6C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC6C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC6C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC6C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC6C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC6C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC6C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC6C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC6C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC6C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC6C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC6C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC6C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_ampere_compute_a_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc6fa.h b/userspace/sdks/nv570/nvidia/inc/class/clc6fa.h new file mode 100644 index 0000000..92d06ea --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc6fa.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc6fa_h_ +#define _clc6fa_h_ + +#define NVC6FA_VIDEO_OFA (0x0000C6FA) + +#endif // _clc6fa_h_ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc770.h b/userspace/sdks/nv570/nvidia/inc/class/clc770.h new file mode 100644 index 0000000..4f66916 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc770.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc770.finn +// + +#define NVC770_DISPLAY (0xc770U) /* finn: Evaluated from "NVC770_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + + + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc771.h b/userspace/sdks/nv570/nvidia/inc/class/clc771.h new file mode 100644 index 0000000..b2b1976 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc771.h @@ -0,0 +1,155 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef _clc771_h_ +#define _clc771_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC771_DISP_SF_USER (0x000C771) + +typedef volatile struct _clc771_tag0 { + NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x000D0FFF:0x000D0000 */ +} _NvC771DispSfUser, NvC771DispSfUserMap; + +#define NVC771_SF_SHARED_GENERIC_CTRL(i,j) (0x000E0200-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_CTRL_ENABLE 0:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_SINGLE 4:4 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_CTRL_SINGLE_NO 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_SINGLE_YES 0x00000001 /* RW--V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_CHECKSUM_HW 16:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_CTRL_CHECKSUM_HW_NO 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_CHECKSUM_HW_YES 0x00000001 /* RW--V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_LOC 9:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_CTRL_LOC_VBLANK 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_LOC_VSYNC 0x00000001 /* RW--V */ +#define NVC771_SF_SHARED_GENERIC_CTRL_LOC_LOADV 0x00000002 /* RW--V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER(i,j) (0x000E0204-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ + +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB3 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB3_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0(i,j) (0x000E0208-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB0 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB0_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB1 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB1_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB2 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB2_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB3 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB3_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1(i,j) (0x000E020C-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB4 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB4_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB5 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB5_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB6 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB6_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB7 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB7_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2(i,j) (0x000E0210-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB8 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB8_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB9 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB9_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB10 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB10_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB11 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB11_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3(i,j) (0x000E0214-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB12 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB12_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB13 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB13_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB14 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB14_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB15 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB15_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4(i,j) (0x000E0218-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB16 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB16_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB17 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB17_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB18 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB18_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB19 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB19_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5(i,j) (0x000E021C-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB20 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB20_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB21 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB21_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB22 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB22_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB23 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB23_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6(i,j) (0x000E0220-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB24 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB24_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB25 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB25_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB26 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB26_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB27 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB27_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7(i,j) (0x000E0224-0x000E0000+(i)*1024+(j)*40) /* RW-4A */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7__SIZE_1 8 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7__SIZE_2 6 /* */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB28 7:0 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB28_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB29 15:8 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB29_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB30 23:16 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB30_INIT 0x00000000 /* RWI-V */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB31 31:24 /* RWIVF */ +#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB31_INIT 0x00000000 /* RWI-V */ + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc773.h b/userspace/sdks/nv570/nvidia/inc/class/clc773.h new file mode 100644 index 0000000..db5505a --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc773.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc773_h_ +#define _clc773_h_ + +#define NVC773_DISP_CAPABILITIES 0xC773 + +#endif diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc77d.h b/userspace/sdks/nv570/nvidia/inc/class/clc77d.h new file mode 100644 index 0000000..f46235a --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc77d.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc77d_h_ +#define _clc77d_h_ + +#define NVC77D_CORE_CHANNEL_DMA (0x0000C77D) + +#define NVC77D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000400) +#define NVC77D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NVC77D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 + +#endif diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc77f.h b/userspace/sdks/nv570/nvidia/inc/class/clc77f.h new file mode 100644 index 0000000..3651a58 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc77f.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clC77F_h_ +#define _clC77F_h_ + +// +// This class provides functional support of Display ANYChannel, Display Contextdmas bound to +// ANYChannel can be used on any other display window channels. +// +#define NVC77F_ANY_CHANNEL_DMA (0x0000C77F) + +#endif // _clC77F_h_ + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc797.h b/userspace/sdks/nv570/nvidia/inc/class/clc797.h new file mode 100644 index 0000000..dc4b600 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc797.h @@ -0,0 +1,4481 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_ampere_b_h_ +#define _cl_ampere_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl ampere_b */ + +#include "nvtypes.h" + +#define AMPERE_B 0xC797 + +#define NVC797_SET_OBJECT 0x0000 +#define NVC797_SET_OBJECT_CLASS_ID 15:0 +#define NVC797_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC797_NO_OPERATION 0x0100 +#define NVC797_NO_OPERATION_V 31:0 + +#define NVC797_SET_NOTIFY_A 0x0104 +#define NVC797_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC797_SET_NOTIFY_B 0x0108 +#define NVC797_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC797_NOTIFY 0x010c +#define NVC797_NOTIFY_TYPE 31:0 +#define NVC797_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC797_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC797_WAIT_FOR_IDLE 0x0110 +#define NVC797_WAIT_FOR_IDLE_V 31:0 + +#define NVC797_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC797_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC797_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC797_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC797_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC797_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC797_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC797_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC797_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC797_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC797_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC797_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC797_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC797_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC797_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC797_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC797_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC797_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC797_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC797_SEND_GO_IDLE 0x013c +#define NVC797_SEND_GO_IDLE_V 31:0 + +#define NVC797_PM_TRIGGER 0x0140 +#define NVC797_PM_TRIGGER_V 31:0 + +#define NVC797_PM_TRIGGER_WFI 0x0144 +#define NVC797_PM_TRIGGER_WFI_V 31:0 + +#define NVC797_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC797_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC797_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC797_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC797_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC797_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC797_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC797_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER 0x0158 +#define NVC797_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER_PAYLOAD_LOWER 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER 0x015c +#define NVC797_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD_UPPER 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_ADDRESS_LOWER 0x0160 +#define NVC797_SET_REPORT_SEMAPHORE_ADDRESS_LOWER_LOWER 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_ADDRESS_UPPER 0x0164 +#define NVC797_SET_REPORT_SEMAPHORE_ADDRESS_UPPER_UPPER 7:0 + +#define NVC797_REPORT_SEMAPHORE_EXECUTE 0x0168 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_OPERATION 1:0 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_OPERATION_RELEASE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_OPERATION_ACQUIRE 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_OPERATION_REPORT_ONLY 0x00000002 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_OPERATION_TRAP 0x00000003 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION 5:2 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC797_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE 6:6 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT 11:7 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_NONE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_SCG_CLOCKS 0x00000008 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS0 0x0000000A +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS1 0x0000000C +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS2 0x0000000E +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS3 0x00000010 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_TIMESTAMP 0x00000014 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE 14:13 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_SUB_REPORT 17:15 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE 19:19 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE 18:18 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE 20:20 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP 23:21 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_INC 0x00000003 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_AND 0x00000005 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_OR 0x00000006 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT 25:24 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64 27:27 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_FALSE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_TRUE 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE 29:28 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_NONE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 + +#define NVC797_LINE_LENGTH_IN 0x0180 +#define NVC797_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC797_LINE_COUNT 0x0184 +#define NVC797_LINE_COUNT_VALUE 31:0 + +#define NVC797_OFFSET_OUT_UPPER 0x0188 +#define NVC797_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC797_OFFSET_OUT 0x018c +#define NVC797_OFFSET_OUT_VALUE 31:0 + +#define NVC797_PITCH_OUT 0x0190 +#define NVC797_PITCH_OUT_VALUE 31:0 + +#define NVC797_SET_DST_BLOCK_SIZE 0x0194 +#define NVC797_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC797_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC797_SET_DST_WIDTH 0x0198 +#define NVC797_SET_DST_WIDTH_V 31:0 + +#define NVC797_SET_DST_HEIGHT 0x019c +#define NVC797_SET_DST_HEIGHT_V 31:0 + +#define NVC797_SET_DST_DEPTH 0x01a0 +#define NVC797_SET_DST_DEPTH_V 31:0 + +#define NVC797_SET_DST_LAYER 0x01a4 +#define NVC797_SET_DST_LAYER_V 31:0 + +#define NVC797_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC797_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC797_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC797_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC797_LAUNCH_DMA 0x01b0 +#define NVC797_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC797_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC797_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC797_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC797_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC797_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC797_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC797_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC797_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC797_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC797_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC797_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC797_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC797_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC797_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC797_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC797_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC797_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC797_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC797_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC797_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC797_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC797_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC797_LOAD_INLINE_DATA 0x01b4 +#define NVC797_LOAD_INLINE_DATA_V 31:0 + +#define NVC797_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC797_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC797_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC797_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC797_SET_MME_SWITCH_STATE 0x01ec +#define NVC797_SET_MME_SWITCH_STATE_VALID 0:0 +#define NVC797_SET_MME_SWITCH_STATE_VALID_FALSE 0x00000000 +#define NVC797_SET_MME_SWITCH_STATE_VALID_TRUE 0x00000001 +#define NVC797_SET_MME_SWITCH_STATE_SAVE_MACRO 11:4 +#define NVC797_SET_MME_SWITCH_STATE_RESTORE_MACRO 19:12 + +#define NVC797_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC797_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC797_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC797_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC797_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC797_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC797_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC797_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC797_RUN_DS_NOW 0x0200 +#define NVC797_RUN_DS_NOW_V 31:0 + +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC797_SET_GS_MODE 0x0208 +#define NVC797_SET_GS_MODE_TYPE 0:0 +#define NVC797_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVC797_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVC797_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC797_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC797_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC797_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC797_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC797_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_GS_DM_FIFO 0x0214 +#define NVC797_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC797_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC797_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC797_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC797_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC797_INVALIDATE_SHADER_CACHES 0x021c +#define NVC797_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC797_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC797_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC797_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC797_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC797_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC797_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC797_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC797_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC797_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC797_SET_INSTANCE_COUNT 0x0220 +#define NVC797_SET_INSTANCE_COUNT_V 31:0 + +#define NVC797_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVC797_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVC797_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC797_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVC797_SET_MME_VERSION 0x0234 +#define NVC797_SET_MME_VERSION_MAJOR 7:0 + +#define NVC797_SET_INDEX_BUFFER_SIZE_A 0x0238 +#define NVC797_SET_INDEX_BUFFER_SIZE_A_UPPER 7:0 + +#define NVC797_SET_INDEX_BUFFER_SIZE_B 0x023c +#define NVC797_SET_INDEX_BUFFER_SIZE_B_LOWER 31:0 + +#define NVC797_SET_ROOT_TABLE_VISIBILITY(i) (0x0240+(i)*4) +#define NVC797_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP0_ENABLE 1:0 +#define NVC797_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP1_ENABLE 5:4 +#define NVC797_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP2_ENABLE 9:8 +#define NVC797_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP3_ENABLE 13:12 +#define NVC797_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP4_ENABLE 17:16 + +#define NVC797_SET_DRAW_CONTROL_A 0x0260 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY 3:0 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_POINTS 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_LINES 0x00000001 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_QUADS 0x00000007 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_PATCH 0x0000000E +#define NVC797_SET_DRAW_CONTROL_A_PRIMITIVE_ID 4:4 +#define NVC797_SET_DRAW_CONTROL_A_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ID 6:5 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ID_FIRST 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC797_SET_DRAW_CONTROL_A_SPLIT_MODE 8:7 +#define NVC797_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC797_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC797_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE 9:9 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 +#define NVC797_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX 10:10 +#define NVC797_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_FALSE 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_TRUE 0x00000001 +#define NVC797_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX 11:11 +#define NVC797_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_FALSE 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_TRUE 0x00000001 + +#define NVC797_SET_DRAW_CONTROL_B 0x0264 +#define NVC797_SET_DRAW_CONTROL_B_INSTANCE_COUNT 31:0 + +#define NVC797_DRAW_INDEX_BUFFER_BEGIN_END_A 0x0268 +#define NVC797_DRAW_INDEX_BUFFER_BEGIN_END_A_FIRST 31:0 + +#define NVC797_DRAW_INDEX_BUFFER_BEGIN_END_B 0x026c +#define NVC797_DRAW_INDEX_BUFFER_BEGIN_END_B_COUNT 31:0 + +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_A 0x0270 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_A_START 31:0 + +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_B 0x0274 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_B_COUNT 31:0 + +#define NVC797_INVALIDATE_RASTER_CACHE_NO_WFI 0x027c +#define NVC797_INVALIDATE_RASTER_CACHE_NO_WFI_V 0:0 + +#define NVC797_SET_COLOR_RENDER_TO_ZETA_SURFACE 0x02b8 +#define NVC797_SET_COLOR_RENDER_TO_ZETA_SURFACE_V 0:0 +#define NVC797_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_FALSE 0x00000000 +#define NVC797_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_TRUE 0x00000001 + +#define NVC797_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION 0x02bc +#define NVC797_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V 0:0 +#define NVC797_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_FALSE 0x00000000 +#define NVC797_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_TRUE 0x00000001 + +#define NVC797_INCREMENT_SYNC_POINT 0x02c8 +#define NVC797_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC797_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC797_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC797_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC797_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC797_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC797_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC797_SET_ROOT_TABLE_PREFETCH 0x02d0 +#define NVC797_SET_ROOT_TABLE_PREFETCH_STAGE_ENABLES 5:0 + +#define NVC797_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC797_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC797_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC797_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVC797_DECOMPRESS_SURFACE 0x02e0 +#define NVC797_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC797_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC797_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC797_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC797_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC797_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC797_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC797_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC797_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC797_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC797_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC797_SET_ZCULL_SUBREGION 0x02e8 +#define NVC797_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC797_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC797_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC797_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC797_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC797_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC797_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC797_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC797_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC797_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC797_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC797_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC797_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC797_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC797_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC797_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC797_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC797_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC797_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC797_DRAW_ZERO_INDEX 0x0304 +#define NVC797_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC797_SET_L1_CONFIGURATION 0x0308 +#define NVC797_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC797_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC797_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC797_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC797_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC797_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC797_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC797_SET_SPA_VERSION 0x0310 +#define NVC797_SET_SPA_VERSION_MINOR 7:0 +#define NVC797_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC797_SET_TIMESLICE_BATCH_LIMIT 0x0314 +#define NVC797_SET_TIMESLICE_BATCH_LIMIT_BATCH_LIMIT 15:0 + +#define NVC797_SET_SNAP_GRID_LINE 0x0318 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC797_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC797_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC797_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC797_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC797_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC797_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC797_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC797_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC797_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC797_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC797_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC797_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC797_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC797_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC797_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC797_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC797_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC797_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC797_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC797_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC797_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC797_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC797_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC797_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC797_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC797_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC797_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC797_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC797_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC797_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC797_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC797_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC797_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC797_RESERVED_TG07 0x033c +#define NVC797_RESERVED_TG07_V 0:0 + +#define NVC797_RESERVED_TG08 0x0340 +#define NVC797_RESERVED_TG08_V 0:0 + +#define NVC797_RESERVED_TG09 0x0344 +#define NVC797_RESERVED_TG09_V 0:0 + +#define NVC797_RESERVED_TG10 0x0348 +#define NVC797_RESERVED_TG10_V 0:0 + +#define NVC797_RESERVED_TG11 0x034c +#define NVC797_RESERVED_TG11_V 0:0 + +#define NVC797_RESERVED_TG12 0x0350 +#define NVC797_RESERVED_TG12_V 0:0 + +#define NVC797_RESERVED_TG13 0x0354 +#define NVC797_RESERVED_TG13_V 0:0 + +#define NVC797_RESERVED_TG14 0x0358 +#define NVC797_RESERVED_TG14_V 0:0 + +#define NVC797_RESERVED_TG15 0x035c +#define NVC797_RESERVED_TG15_V 0:0 + +#define NVC797_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC797_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC797_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC797_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC797_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC797_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC797_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC797_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC797_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC797_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC797_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC797_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC797_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC797_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC797_SET_RASTER_ENABLE 0x037c +#define NVC797_SET_RASTER_ENABLE_V 0:0 +#define NVC797_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC797_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC797_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC797_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC797_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC797_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC797_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC797_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC797_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC797_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC797_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVC797_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVC797_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVC797_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVC797_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVC797_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVC797_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVC797_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVC797_SET_Z_ROP_SLICE_MAP 0x0500 +#define NVC797_SET_Z_ROP_SLICE_MAP_VIRTUAL_ADDRESS_MASK 31:0 + +#define NVC797_SET_ROOT_TABLE_SELECTOR 0x0504 +#define NVC797_SET_ROOT_TABLE_SELECTOR_ROOT_TABLE 2:0 +#define NVC797_SET_ROOT_TABLE_SELECTOR_OFFSET 15:8 + +#define NVC797_LOAD_ROOT_TABLE 0x0508 +#define NVC797_LOAD_ROOT_TABLE_V 31:0 + +#define NVC797_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVC797_SET_MME_MEM_ADDRESS_A_UPPER 16:0 + +#define NVC797_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVC797_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVC797_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVC797_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVC797_MME_DMA_READ 0x055c +#define NVC797_MME_DMA_READ_LENGTH 31:0 + +#define NVC797_MME_DMA_READ_FIFOED 0x0560 +#define NVC797_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVC797_MME_DMA_WRITE 0x0564 +#define NVC797_MME_DMA_WRITE_LENGTH 31:0 + +#define NVC797_MME_DMA_REDUCTION 0x0568 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVC797_MME_DMA_SYSMEMBAR 0x056c +#define NVC797_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVC797_MME_DMA_SYNC 0x0570 +#define NVC797_MME_DMA_SYNC_VALUE 31:0 + +#define NVC797_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NVC797_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NVC797_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NVC797_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NVC797_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NVC797_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NVC797_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NVC797_SET_VERTEX_STREAM_SIZE_A(j) (0x0600+(j)*8) +#define NVC797_SET_VERTEX_STREAM_SIZE_A_UPPER 7:0 + +#define NVC797_SET_VERTEX_STREAM_SIZE_B(j) (0x0604+(j)*8) +#define NVC797_SET_VERTEX_STREAM_SIZE_B_LOWER 31:0 + +#define NVC797_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC797_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC797_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC797_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC797_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC797_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC797_SET_RASTER_INPUT 0x0740 +#define NVC797_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC797_SET_STREAM_OUTPUT 0x0744 +#define NVC797_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC797_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC797_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC797_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC797_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC797_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC797_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC797_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC797_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC797_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC797_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC797_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC797_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC797_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC797_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC797_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC797_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC797_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC797_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC797_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC797_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC797_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC797_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC797_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC797_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC797_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVC797_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC797_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC797_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC797_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC797_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC797_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC797_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC797_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC797_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC797_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC797_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC797_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC797_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC797_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC797_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC797_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC797_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC797_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC797_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC797_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC797_SET_ZCULL_STORAGE_B 0x07ec +#define NVC797_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC797_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC797_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC797_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC797_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC797_SET_ZT_READ_ONLY 0x07f8 +#define NVC797_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC797_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC797_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC797_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC797_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC797_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC797_THROTTLE_SM 0x07fc +#define NVC797_THROTTLE_SM_MULTIPLY_ADD 0:0 +#define NVC797_THROTTLE_SM_MULTIPLY_ADD_FALSE 0x00000000 +#define NVC797_THROTTLE_SM_MULTIPLY_ADD_TRUE 0x00000001 + +#define NVC797_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC797_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC797_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC797_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC797_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC797_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC797_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC797_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC797_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC797_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC797_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC797_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC797_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC797_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC797_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC797_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC797_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC797_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC797_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC797_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC797_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC797_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC797_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC797_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC797_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC797_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC797_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC797_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC797_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC797_SET_COLOR_TARGET_C_ROP_SLICE_MAP(j) (0x0824+(j)*64) +#define NVC797_SET_COLOR_TARGET_C_ROP_SLICE_MAP_VIRTUAL_ADDRESS_MASK 31:0 + +#define NVC797_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC797_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC797_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC797_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC797_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC797_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC797_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC797_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC797_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC797_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC797_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC797_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC797_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC797_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC797_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC797_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC797_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC797_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC797_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC797_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC797_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC797_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC797_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC797_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC797_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC797_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC797_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC797_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC797_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC797_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC797_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC797_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC797_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC797_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC797_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC797_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC797_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC797_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC797_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC797_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC797_SET_STATISTICS_COUNTER 0x0d68 +#define NVC797_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC797_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC797_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC797_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC797_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC797_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC797_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC797_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC797_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC797_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC797_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC797_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC797_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC797_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC797_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC797_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC797_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVC797_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC797_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC797_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC797_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC797_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC797_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC797_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC797_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC797_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC797_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC797_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC797_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC797_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC797_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC797_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC797_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC797_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC797_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC797_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC797_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC797_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC797_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC797_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC797_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC797_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC797_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC797_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC797_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC797_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC797_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC797_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC797_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC797_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC797_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC797_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC797_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC797_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC797_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC797_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC797_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC797_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC797_SET_POLY_SMOOTH 0x0db4 +#define NVC797_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC797_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC797_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC797_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC797_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC797_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC797_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC797_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC797_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC797_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_PATCH 0x0dcc +#define NVC797_SET_PATCH_SIZE 7:0 + +#define NVC797_SET_ITERATED_BLEND 0x0dd0 +#define NVC797_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC797_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC797_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC797_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC797_SET_ZCULL_CRITERION 0x0dd8 +#define NVC797_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC797_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC797_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC797_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC797_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC797_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC797_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC797_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC797_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC797_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC797_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 +#define NVC797_PIXEL_SHADER_BARRIER_BARRIER_LOCATION 1:1 +#define NVC797_PIXEL_SHADER_BARRIER_BARRIER_LOCATION_BLOCK_BEFORE_PS 0x00000000 +#define NVC797_PIXEL_SHADER_BARRIER_BARRIER_LOCATION_BLOCK_BEFORE_PS_AND_ZTEST 0x00000001 + +#define NVC797_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC797_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC797_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC797_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC797_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC797_MME_DMA_WRITE_METHOD_BARRIER 0x0dec +#define NVC797_MME_DMA_WRITE_METHOD_BARRIER_V 0:0 + +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC797_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC797_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC797_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC797_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC797_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC797_SET_SCISSOR_ENABLE_V 0:0 +#define NVC797_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC797_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC797_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC797_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC797_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC797_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC797_SET_VPC_PERF_KNOB 0x0f14 +#define NVC797_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC797_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC797_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC797_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC797_PM_LOCAL_TRIGGER 0x0f18 +#define NVC797_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC797_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC797_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC797_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC797_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC797_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC797_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC797_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC797_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC797_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC797_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC797_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC797_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC797_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC797_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC797_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC797_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC797_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC797_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC797_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC797_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC797_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC797_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC797_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC797_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC797_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC797_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC797_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC797_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC797_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC797_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC797_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC797_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC797_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC797_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC797_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC797_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC797_SET_SAMPLE_MASK 0x0fa4 +#define NVC797_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC797_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC797_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC797_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC797_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC797_SET_CT_MRT_ENABLE 0x0fac +#define NVC797_SET_CT_MRT_ENABLE_V 0:0 +#define NVC797_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC797_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC797_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC797_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC797_SET_TIR 0x0fb4 +#define NVC797_SET_TIR_MODE 1:0 +#define NVC797_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC797_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC797_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC797_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC797_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC797_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC797_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC797_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC797_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC797_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC797_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC797_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC797_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC797_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC797_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC797_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC797_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC797_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC797_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC797_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_TIR_MODULATION 0x0fd4 +#define NVC797_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC797_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC797_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC797_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC797_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC797_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC797_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC797_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC797_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC797_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC797_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC797_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC797_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC797_SET_ZT_A 0x0fe0 +#define NVC797_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_ZT_B 0x0fe4 +#define NVC797_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_ZT_FORMAT 0x0fe8 +#define NVC797_SET_ZT_FORMAT_V 4:0 +#define NVC797_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC797_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC797_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC797_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC797_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC797_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC797_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC797_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC797_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC797_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC797_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC797_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC797_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC797_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC797_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC797_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC797_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC797_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC797_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC797_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC797_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC797_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC797_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC797_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC797_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC797_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC797_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC797_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC797_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC797_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC797_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC797_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC797_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC797_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC797_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC797_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC797_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC797_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC797_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC797_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC797_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC797_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC797_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC797_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC797_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC797_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD02 0x102c +#define NVC797_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC797_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC797_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC797_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC797_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC797_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC797_SET_SPARE_NOOP01 0x1044 +#define NVC797_SET_SPARE_NOOP01_V 31:0 + +#define NVC797_SET_SPARE_NOOP02 0x1048 +#define NVC797_SET_SPARE_NOOP02_V 31:0 + +#define NVC797_SET_SPARE_NOOP03 0x104c +#define NVC797_SET_SPARE_NOOP03_V 31:0 + +#define NVC797_SET_SPARE_NOOP04 0x1050 +#define NVC797_SET_SPARE_NOOP04_V 31:0 + +#define NVC797_SET_SPARE_NOOP05 0x1054 +#define NVC797_SET_SPARE_NOOP05_V 31:0 + +#define NVC797_SET_SPARE_NOOP06 0x1058 +#define NVC797_SET_SPARE_NOOP06_V 31:0 + +#define NVC797_SET_SPARE_NOOP07 0x105c +#define NVC797_SET_SPARE_NOOP07_V 31:0 + +#define NVC797_SET_SPARE_NOOP08 0x1060 +#define NVC797_SET_SPARE_NOOP08_V 31:0 + +#define NVC797_SET_SPARE_NOOP09 0x1064 +#define NVC797_SET_SPARE_NOOP09_V 31:0 + +#define NVC797_SET_SPARE_NOOP10 0x1068 +#define NVC797_SET_SPARE_NOOP10_V 31:0 + +#define NVC797_SET_SPARE_NOOP11 0x106c +#define NVC797_SET_SPARE_NOOP11_V 31:0 + +#define NVC797_SET_SPARE_NOOP12 0x1070 +#define NVC797_SET_SPARE_NOOP12_V 31:0 + +#define NVC797_SET_SPARE_NOOP13 0x1074 +#define NVC797_SET_SPARE_NOOP13_V 31:0 + +#define NVC797_SET_SPARE_NOOP14 0x1078 +#define NVC797_SET_SPARE_NOOP14_V 31:0 + +#define NVC797_SET_SPARE_NOOP15 0x107c +#define NVC797_SET_SPARE_NOOP15_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC797_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC797_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC797_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC797_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC797_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC797_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC797_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC797_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC797_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC797_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC797_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC797_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC797_UNBIND_ALL 0x10f4 +#define NVC797_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC797_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC797_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC797_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC797_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC797_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC797_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC797_NO_OPERATION_DATA_HI 0x110c +#define NVC797_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC797_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC797_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC797_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC797_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC797_PM_TRIGGER_END 0x1114 +#define NVC797_PM_TRIGGER_END_V 31:0 + +#define NVC797_SET_VERTEX_ID_BASE 0x1118 +#define NVC797_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC797_SET_STENCIL_COMPRESSION 0x111c +#define NVC797_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC797_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC797_SET_TIR_CONTROL 0x1130 +#define NVC797_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC797_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC797_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC797_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC797_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC797_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC797_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC797_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC797_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 +#define NVC797_SET_TIR_CONTROL_REDUCTION_MODE 2:2 +#define NVC797_SET_TIR_CONTROL_REDUCTION_MODE_AFFINITY_MAP 0x00000000 +#define NVC797_SET_TIR_CONTROL_REDUCTION_MODE_TRUNCATION 0x00000001 + +#define NVC797_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC797_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC797_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC797_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC797_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC797_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC797_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC797_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC797_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC797_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC797_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC797_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC797_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC797_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC797_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC797_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC797_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC797_FLUSH_PENDING_WRITES 0x1144 +#define NVC797_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC797_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC797_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC797_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC797_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC797_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC797_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC797_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC797_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC797_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC797_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC797_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC797_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC797_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC797_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC797_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC797_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC797_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC797_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC797_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC797_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC797_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC797_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_SCREEN_STATE_MASK 0x1204 +#define NVC797_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC797_SET_ZT_SPARSE 0x1208 +#define NVC797_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC797_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC797_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC797_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_SET_CT_SELECT 0x121c +#define NVC797_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC797_SET_CT_SELECT_TARGET0 6:4 +#define NVC797_SET_CT_SELECT_TARGET1 9:7 +#define NVC797_SET_CT_SELECT_TARGET2 12:10 +#define NVC797_SET_CT_SELECT_TARGET3 15:13 +#define NVC797_SET_CT_SELECT_TARGET4 18:16 +#define NVC797_SET_CT_SELECT_TARGET5 21:19 +#define NVC797_SET_CT_SELECT_TARGET6 24:22 +#define NVC797_SET_CT_SELECT_TARGET7 27:25 + +#define NVC797_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC797_SET_ZT_SIZE_A 0x1228 +#define NVC797_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC797_SET_ZT_SIZE_B 0x122c +#define NVC797_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC797_SET_ZT_SIZE_C 0x1230 +#define NVC797_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC797_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC797_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC797_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC797_SET_SAMPLER_BINDING 0x1234 +#define NVC797_SET_SAMPLER_BINDING_V 0:0 +#define NVC797_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC797_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC797_DRAW_AUTO 0x123c +#define NVC797_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC797_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC797_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC797_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC797_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC797_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC797_SET_BACK_END_COPY_A 0x1264 +#define NVC797_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC797_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC797_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC797_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC797_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BACK_END_COPY_B 0x1268 +#define NVC797_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC797_SET_BACK_END_COPY_C 0x126c +#define NVC797_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC797_SET_BACK_END_COPY_D 0x1270 +#define NVC797_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC797_SET_BACK_END_COPY_E 0x1274 +#define NVC797_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC797_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC797_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVC797_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC797_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC797_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC797_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC797_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC797_CLEAR_ZCULL_REGION 0x12c8 +#define NVC797_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC797_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC797_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC797_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC797_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC797_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC797_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC797_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC797_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC797_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC797_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC797_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC797_SET_DEPTH_TEST 0x12cc +#define NVC797_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC797_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_FILL_MODE 0x12d0 +#define NVC797_SET_FILL_MODE_V 31:0 +#define NVC797_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC797_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC797_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC797_SET_SHADE_MODE 0x12d4 +#define NVC797_SET_SHADE_MODE_V 31:0 +#define NVC797_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC797_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC797_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC797_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC797_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC797_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC797_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC797_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC797_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC797_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC797_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC797_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_DEPTH_WRITE 0x12e8 +#define NVC797_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC797_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_ALPHA_TEST 0x12ec +#define NVC797_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC797_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC797_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC797_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC797_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC797_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC797_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC797_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC797_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC797_D3D_SET_CULL_MODE 0x1308 +#define NVC797_D3D_SET_CULL_MODE_V 31:0 +#define NVC797_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC797_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC797_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC797_SET_DEPTH_FUNC 0x130c +#define NVC797_SET_DEPTH_FUNC_V 31:0 +#define NVC797_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC797_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC797_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC797_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC797_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC797_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC797_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC797_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC797_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC797_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC797_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC797_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC797_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC797_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC797_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC797_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC797_SET_ALPHA_REF 0x1310 +#define NVC797_SET_ALPHA_REF_V 31:0 + +#define NVC797_SET_ALPHA_FUNC 0x1314 +#define NVC797_SET_ALPHA_FUNC_V 31:0 +#define NVC797_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC797_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC797_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC797_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC797_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC797_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC797_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC797_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC797_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC797_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC797_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC797_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC797_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC797_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC797_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC797_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC797_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC797_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC797_SET_BLEND_CONST_RED 0x131c +#define NVC797_SET_BLEND_CONST_RED_V 31:0 + +#define NVC797_SET_BLEND_CONST_GREEN 0x1320 +#define NVC797_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC797_SET_BLEND_CONST_BLUE 0x1324 +#define NVC797_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC797_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC797_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC797_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC797_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC797_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC797_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC797_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC797_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC797_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC797_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BLEND_COLOR_OP 0x1340 +#define NVC797_SET_BLEND_COLOR_OP_V 31:0 +#define NVC797_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC797_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC797_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC797_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC797_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC797_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC797_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC797_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC797_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC797_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_BLEND_ALPHA_OP 0x134c +#define NVC797_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC797_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC797_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC797_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC797_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC797_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC797_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC797_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC797_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC797_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC797_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC797_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC797_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC797_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC797_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC797_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BLEND(i) (0x1360+(i)*4) +#define NVC797_SET_BLEND_ENABLE 0:0 +#define NVC797_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_STENCIL_TEST 0x1380 +#define NVC797_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC797_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_STENCIL_OP_FAIL 0x1384 +#define NVC797_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC797_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC797_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC797_SET_STENCIL_OP_ZPASS 0x138c +#define NVC797_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC797_SET_STENCIL_FUNC 0x1390 +#define NVC797_SET_STENCIL_FUNC_V 31:0 +#define NVC797_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC797_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC797_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC797_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC797_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC797_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC797_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC797_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC797_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC797_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC797_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC797_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC797_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC797_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC797_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC797_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC797_SET_STENCIL_FUNC_REF 0x1394 +#define NVC797_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC797_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC797_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC797_SET_STENCIL_MASK 0x139c +#define NVC797_SET_STENCIL_MASK_V 7:0 + +#define NVC797_SET_DRAW_AUTO_START 0x13a4 +#define NVC797_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC797_SET_PS_SATURATE 0x13a8 +#define NVC797_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC797_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC797_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC797_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC797_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC797_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC797_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC797_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC797_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC797_SET_WINDOW_ORIGIN 0x13ac +#define NVC797_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC797_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC797_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC797_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC797_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC797_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC797_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC797_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC797_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC797_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC797_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC797_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC797_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC797_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC797_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC797_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC797_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC797_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC797_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC797_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC797_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC797_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC797_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC797_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC797_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC797_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC797_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC797_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC797_STORE_ZCULL 0x1464 +#define NVC797_STORE_ZCULL_V 0:0 + +#define NVC797_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC797_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC797_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC797_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC797_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC797_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC797_LOAD_ZCULL 0x1500 +#define NVC797_LOAD_ZCULL_V 0:0 + +#define NVC797_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC797_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC797_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC797_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC797_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC797_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC797_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC797_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC797_SET_USER_CLIP_ENABLE 0x1510 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC797_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC797_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC797_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_POINT_SIZE 0x1518 +#define NVC797_SET_POINT_SIZE_V 31:0 + +#define NVC797_SET_ZCULL_STATS 0x151c +#define NVC797_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC797_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_POINT_SPRITE 0x1520 +#define NVC797_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC797_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC797_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC797_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC797_CLEAR_REPORT_VALUE 0x1530 +#define NVC797_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC797_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC797_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC797_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC797_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC797_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC797_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVC797_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC797_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC797_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_ZT_SELECT 0x1538 +#define NVC797_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC797_SET_RENDER_ENABLE_A 0x1550 +#define NVC797_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_RENDER_ENABLE_B 0x1554 +#define NVC797_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_RENDER_ENABLE_C 0x1558 +#define NVC797_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC797_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC797_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC797_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC797_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC797_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC797_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC797_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC797_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC797_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC797_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC797_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC797_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC797_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC797_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC797_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC797_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_TEX_HEADER_POOL_C 0x157c +#define NVC797_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC797_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC797_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC797_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC797_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC797_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC797_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC797_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC797_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC797_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC797_SET_SRGB_WRITE 0x15b8 +#define NVC797_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC797_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_DEPTH_BIAS 0x15bc +#define NVC797_SET_DEPTH_BIAS_V 31:0 + +#define NVC797_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC797_SET_RT_LAYER 0x15cc +#define NVC797_SET_RT_LAYER_V 15:0 +#define NVC797_SET_RT_LAYER_CONTROL 16:16 +#define NVC797_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC797_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC797_SET_ANTI_ALIAS 0x15d0 +#define NVC797_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC797_SET_EDGE_FLAG 0x15e4 +#define NVC797_SET_EDGE_FLAG_V 0:0 +#define NVC797_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC797_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC797_DRAW_INLINE_INDEX 0x15e8 +#define NVC797_DRAW_INLINE_INDEX_V 31:0 + +#define NVC797_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC797_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC797_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC797_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC797_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC797_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC797_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC797_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC797_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC797_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC797_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC797_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC797_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC797_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC797_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC797_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC797_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC797_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC797_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC797_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC797_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC797_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC797_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC797_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC797_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC797_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC797_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC797_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC797_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC797_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC797_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC797_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC797_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC797_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC797_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC797_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC797_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC797_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC797_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC797_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC797_END 0x1614 +#define NVC797_END_V 0:0 + +#define NVC797_BEGIN 0x1618 +#define NVC797_BEGIN_OP 15:0 +#define NVC797_BEGIN_OP_POINTS 0x00000000 +#define NVC797_BEGIN_OP_LINES 0x00000001 +#define NVC797_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC797_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC797_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC797_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC797_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC797_BEGIN_OP_QUADS 0x00000007 +#define NVC797_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC797_BEGIN_OP_POLYGON 0x00000009 +#define NVC797_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC797_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC797_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_BEGIN_OP_PATCH 0x0000000E +#define NVC797_BEGIN_PRIMITIVE_ID 24:24 +#define NVC797_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC797_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC797_BEGIN_INSTANCE_ID 27:26 +#define NVC797_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC797_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC797_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC797_BEGIN_SPLIT_MODE 30:29 +#define NVC797_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC797_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC797_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC797_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC797_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVC797_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC797_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_VERTEX_ID_COPY 0x161c +#define NVC797_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC797_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC797_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC797_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC797_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC797_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC797_LOAD_PRIMITIVE_ID 0x1624 +#define NVC797_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC797_SET_SHADER_BASED_CULL 0x162c +#define NVC797_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC797_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC797_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC797_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_CLASS_VERSION 0x1638 +#define NVC797_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC797_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC797_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC797_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC797_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC797_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC797_SET_DA_OUTPUT 0x164c +#define NVC797_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC797_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC797_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC797_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC797_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_POINT_CENTER_MODE 0x165c +#define NVC797_SET_POINT_CENTER_MODE_V 31:0 +#define NVC797_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC797_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC797_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC797_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC797_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC797_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC797_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC797_SET_LINE_STIPPLE 0x166c +#define NVC797_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC797_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC797_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC797_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC797_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC797_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC797_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC797_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC797_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC797_SET_PROVOKING_VERTEX 0x1684 +#define NVC797_SET_PROVOKING_VERTEX_V 0:0 +#define NVC797_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC797_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC797_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC797_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC797_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_POLYGON_STIPPLE 0x168c +#define NVC797_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC797_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_SHADER_CONTROL 0x1690 +#define NVC797_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC797_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC797_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC797_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC797_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC797_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC797_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC797_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC797_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC797_CHECK_CLASS_VERSION 0x16a0 +#define NVC797_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC797_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC797_SET_SPH_VERSION 0x16a4 +#define NVC797_SET_SPH_VERSION_CURRENT 15:0 +#define NVC797_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC797_CHECK_SPH_VERSION 0x16a8 +#define NVC797_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC797_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC797_SET_SCG_GRAPHICS_PRIORITY 0x16bc +#define NVC797_SET_SCG_GRAPHICS_PRIORITY_PRIORITY 5:0 + +#define NVC797_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS(i) (0x16c0+(i)*4) +#define NVC797_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC797_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC797_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC797_SET_AAM_VERSION 0x1790 +#define NVC797_SET_AAM_VERSION_CURRENT 15:0 +#define NVC797_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC797_CHECK_AAM_VERSION 0x1794 +#define NVC797_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC797_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC797_SET_ZT_LAYER 0x179c +#define NVC797_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC797_SET_INDEX_BUFFER_A 0x17c8 +#define NVC797_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC797_SET_INDEX_BUFFER_B 0x17cc +#define NVC797_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC797_SET_INDEX_BUFFER_E 0x17d8 +#define NVC797_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC797_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC797_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC797_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC797_SET_INDEX_BUFFER_F 0x17dc +#define NVC797_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC797_DRAW_INDEX_BUFFER 0x17e0 +#define NVC797_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC797_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC797_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC797_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC797_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC797_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC797_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC797_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC797_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC797_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC797_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC797_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC797_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC797_OGL_SET_CULL 0x1918 +#define NVC797_OGL_SET_CULL_ENABLE 0:0 +#define NVC797_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC797_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC797_OGL_SET_FRONT_FACE 0x191c +#define NVC797_OGL_SET_FRONT_FACE_V 31:0 +#define NVC797_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC797_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC797_OGL_SET_CULL_FACE 0x1920 +#define NVC797_OGL_SET_CULL_FACE_V 31:0 +#define NVC797_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC797_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC797_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC797_SET_VIEWPORT_PIXEL 0x1924 +#define NVC797_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC797_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC797_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC797_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC797_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC797_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC797_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE 17:16 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_USE_FIELD_MIN_Z_ZERO_MAX_Z_ONE 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MIN_Z_MAX_Z 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_ZERO_ONE 0x00000002 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MINUS_INF_PLUS_INF 0x00000003 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC797_SET_USER_CLIP_OP 0x1940 +#define NVC797_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC797_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC797_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC797_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC797_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC797_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC797_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC797_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC797_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC797_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC797_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC797_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC797_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC797_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC797_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC797_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC797_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC797_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC797_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC797_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC797_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC797_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC797_INVALIDATE_ZCULL 0x1958 +#define NVC797_INVALIDATE_ZCULL_V 31:0 +#define NVC797_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC797_SET_ZCULL 0x1968 +#define NVC797_SET_ZCULL_Z_ENABLE 0:0 +#define NVC797_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC797_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_ZCULL_BOUNDS 0x196c +#define NVC797_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC797_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC797_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC797_ZCULL_SYNC 0x1978 +#define NVC797_ZCULL_SYNC_V 31:0 + +#define NVC797_SET_CLIP_ID_TEST 0x197c +#define NVC797_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC797_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC797_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC797_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC797_SET_CLIP_ID 0x1984 +#define NVC797_SET_CLIP_ID_V 31:0 + +#define NVC797_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC797_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC797_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC797_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC797_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC797_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC797_SET_LOGIC_OP 0x19c4 +#define NVC797_SET_LOGIC_OP_ENABLE 0:0 +#define NVC797_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC797_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC797_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC797_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC797_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC797_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC797_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC797_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC797_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC797_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC797_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC797_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC797_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC797_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC797_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC797_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC797_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC797_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC797_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC797_SET_Z_COMPRESSION 0x19cc +#define NVC797_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC797_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC797_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC797_CLEAR_SURFACE 0x19d0 +#define NVC797_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC797_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC797_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC797_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC797_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC797_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC797_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC797_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC797_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC797_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC797_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC797_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC797_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC797_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC797_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC797_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC797_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC797_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC797_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC797_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC797_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC797_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC797_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC797_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC797_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC797_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC797_PIPE_NOP 0x1a2c +#define NVC797_PIPE_NOP_V 31:0 + +#define NVC797_SET_SPARE00 0x1a30 +#define NVC797_SET_SPARE00_V 31:0 + +#define NVC797_SET_SPARE01 0x1a34 +#define NVC797_SET_SPARE01_V 31:0 + +#define NVC797_SET_SPARE02 0x1a38 +#define NVC797_SET_SPARE02_V 31:0 + +#define NVC797_SET_SPARE03 0x1a3c +#define NVC797_SET_SPARE03_V 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC797_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC797_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC797_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC797_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC797_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC797_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC797_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC797_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC797_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC797_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC797_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC797_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_TIMESTAMP 0x00000014 +#define NVC797_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC797_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC797_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC797_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC797_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC797_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC797_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC797_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC797_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC797_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC797_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC797_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC797_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC797_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC797_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC797_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC797_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC797_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC797_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC797_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC797_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC797_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC797_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC797_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC797_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC797_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC797_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC797_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC797_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC797_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC797_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC797_SET_PIPELINE_RESERVED_B(j) (0x2004+(j)*64) +#define NVC797_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVC797_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC797_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC797_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC797_SET_PIPELINE_REGISTER_COUNT_V 8:0 + +#define NVC797_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC797_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC797_SET_PIPELINE_PROGRAM_ADDRESS_A(j) (0x2014+(j)*64) +#define NVC797_SET_PIPELINE_PROGRAM_ADDRESS_A_UPPER 7:0 + +#define NVC797_SET_PIPELINE_PROGRAM_ADDRESS_B(j) (0x2018+(j)*64) +#define NVC797_SET_PIPELINE_PROGRAM_ADDRESS_B_LOWER 31:0 + +#define NVC797_SET_PIPELINE_PROGRAM_PREFETCH(j) (0x201c+(j)*64) +#define NVC797_SET_PIPELINE_PROGRAM_PREFETCH_SIZE_IN_BLOCKS 6:0 + +#define NVC797_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC797_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC797_SET_FALCON00 0x2300 +#define NVC797_SET_FALCON00_V 31:0 + +#define NVC797_SET_FALCON01 0x2304 +#define NVC797_SET_FALCON01_V 31:0 + +#define NVC797_SET_FALCON02 0x2308 +#define NVC797_SET_FALCON02_V 31:0 + +#define NVC797_SET_FALCON03 0x230c +#define NVC797_SET_FALCON03_V 31:0 + +#define NVC797_SET_FALCON04 0x2310 +#define NVC797_SET_FALCON04_V 31:0 + +#define NVC797_SET_FALCON05 0x2314 +#define NVC797_SET_FALCON05_V 31:0 + +#define NVC797_SET_FALCON06 0x2318 +#define NVC797_SET_FALCON06_V 31:0 + +#define NVC797_SET_FALCON07 0x231c +#define NVC797_SET_FALCON07_V 31:0 + +#define NVC797_SET_FALCON08 0x2320 +#define NVC797_SET_FALCON08_V 31:0 + +#define NVC797_SET_FALCON09 0x2324 +#define NVC797_SET_FALCON09_V 31:0 + +#define NVC797_SET_FALCON10 0x2328 +#define NVC797_SET_FALCON10_V 31:0 + +#define NVC797_SET_FALCON11 0x232c +#define NVC797_SET_FALCON11_V 31:0 + +#define NVC797_SET_FALCON12 0x2330 +#define NVC797_SET_FALCON12_V 31:0 + +#define NVC797_SET_FALCON13 0x2334 +#define NVC797_SET_FALCON13_V 31:0 + +#define NVC797_SET_FALCON14 0x2338 +#define NVC797_SET_FALCON14_V 31:0 + +#define NVC797_SET_FALCON15 0x233c +#define NVC797_SET_FALCON15_V 31:0 + +#define NVC797_SET_FALCON16 0x2340 +#define NVC797_SET_FALCON16_V 31:0 + +#define NVC797_SET_FALCON17 0x2344 +#define NVC797_SET_FALCON17_V 31:0 + +#define NVC797_SET_FALCON18 0x2348 +#define NVC797_SET_FALCON18_V 31:0 + +#define NVC797_SET_FALCON19 0x234c +#define NVC797_SET_FALCON19_V 31:0 + +#define NVC797_SET_FALCON20 0x2350 +#define NVC797_SET_FALCON20_V 31:0 + +#define NVC797_SET_FALCON21 0x2354 +#define NVC797_SET_FALCON21_V 31:0 + +#define NVC797_SET_FALCON22 0x2358 +#define NVC797_SET_FALCON22_V 31:0 + +#define NVC797_SET_FALCON23 0x235c +#define NVC797_SET_FALCON23_V 31:0 + +#define NVC797_SET_FALCON24 0x2360 +#define NVC797_SET_FALCON24_V 31:0 + +#define NVC797_SET_FALCON25 0x2364 +#define NVC797_SET_FALCON25_V 31:0 + +#define NVC797_SET_FALCON26 0x2368 +#define NVC797_SET_FALCON26_V 31:0 + +#define NVC797_SET_FALCON27 0x236c +#define NVC797_SET_FALCON27_V 31:0 + +#define NVC797_SET_FALCON28 0x2370 +#define NVC797_SET_FALCON28_V 31:0 + +#define NVC797_SET_FALCON29 0x2374 +#define NVC797_SET_FALCON29_V 31:0 + +#define NVC797_SET_FALCON30 0x2378 +#define NVC797_SET_FALCON30_V 31:0 + +#define NVC797_SET_FALCON31 0x237c +#define NVC797_SET_FALCON31_V 31:0 + +#define NVC797_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC797_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC797_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC797_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC797_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC797_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC797_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC797_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC797_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC797_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC797_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC797_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC797_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC797_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC797_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC797_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC797_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC797_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC797_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC797_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC797_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC797_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC797_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC797_SET_TRAP_HANDLER_A 0x25f8 +#define NVC797_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC797_SET_TRAP_HANDLER_B 0x25fc +#define NVC797_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC797_SET_COLOR_CLAMP 0x2600 +#define NVC797_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC797_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC797_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC797_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC797_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC797_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC797_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC797_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC797_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC797_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC797_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC797_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC797_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC797_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC797_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC797_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC797_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC797_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC797_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC797_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC797_CALL_MME_MACRO_V 31:0 + +#define NVC797_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC797_CALL_MME_DATA_V 31:0 + +#endif /* _cl_ampere_b_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc7b0.h b/userspace/sdks/nv570/nvidia/inc/class/clc7b0.h new file mode 100644 index 0000000..8c98771 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc7b0.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef clc7b0_h_ +#define clc7b0_h_ + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC7B0_VIDEO_DECODER (0x0000C7B0) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc7b0_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc7b5.h b/userspace/sdks/nv570/nvidia/inc/class/clc7b5.h new file mode 100644 index 0000000..df331e8 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc7b5.h @@ -0,0 +1,304 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clc7b5_h_ +#define _clc7b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define AMPERE_DMA_COPY_B (0x0000C7B5) + +#define NVC7B5_NOP (0x00000100) +#define NVC7B5_NOP_PARAMETER 31:0 +#define NVC7B5_PM_TRIGGER (0x00000140) +#define NVC7B5_PM_TRIGGER_V 31:0 +#define NVC7B5_SET_MONITORED_FENCE_TYPE (0x0000021C) +#define NVC7B5_SET_MONITORED_FENCE_TYPE_TYPE 0:0 +#define NVC7B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE (0x00000000) +#define NVC7B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE_EXT (0x00000001) +#define NVC7B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER (0x00000220) +#define NVC7B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER_UPPER 16:0 +#define NVC7B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER (0x00000224) +#define NVC7B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER_LOWER 31:0 +#define NVC7B5_SET_SEMAPHORE_A (0x00000240) +#define NVC7B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC7B5_SET_SEMAPHORE_B (0x00000244) +#define NVC7B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC7B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC7B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC7B5_SET_SEMAPHORE_PAYLOAD_UPPER (0x0000024C) +#define NVC7B5_SET_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD 31:0 +#define NVC7B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC7B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC7B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC7B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC7B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC7B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC7B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC7B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC7B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC7B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC7B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC7B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC7B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC7B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC7B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC7B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC7B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVC7B5_SET_SRC_PHYS_MODE_BASIC_KIND 5:2 +#define NVC7B5_SET_SRC_PHYS_MODE_PEER_ID 8:6 +#define NVC7B5_SET_SRC_PHYS_MODE_FLA 9:9 +#define NVC7B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC7B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC7B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC7B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC7B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC7B5_SET_DST_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVC7B5_SET_DST_PHYS_MODE_BASIC_KIND 5:2 +#define NVC7B5_SET_DST_PHYS_MODE_PEER_ID 8:6 +#define NVC7B5_SET_DST_PHYS_MODE_FLA 9:9 +#define NVC7B5_LAUNCH_DMA (0x00000300) +#define NVC7B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC7B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC7B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC7B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC7B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC7B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC7B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC7B5_LAUNCH_DMA_FLUSH_TYPE 25:25 +#define NVC7B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000) +#define NVC7B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_NO_TIMESTAMP (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_WITH_TIMESTAMP (0x00000002) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE (0x00000003) +#define NVC7B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC7B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC7B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC7B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC7B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC7B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC7B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC7B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC7B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC7B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC7B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC7B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC7B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC7B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC7B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC7B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC7B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC7B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC7B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC7B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC7B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC7B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC7B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC7B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC7B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDA (0x00000008) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDB (0x00000009) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN (0x0000000B) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX (0x0000000C) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDC (0x0000000D) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDD (0x0000000E) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDE (0x0000000F) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC7B5_LAUNCH_DMA_VPRMODE 23:22 +#define NVC7B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVC7B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC7B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC7B5_LAUNCH_DMA_DISABLE_PLC 26:26 +#define NVC7B5_LAUNCH_DMA_DISABLE_PLC_FALSE (0x00000000) +#define NVC7B5_LAUNCH_DMA_DISABLE_PLC_TRUE (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE 27:27 +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_ONE_WORD (0x00000000) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_TWO_WORD (0x00000001) +#define NVC7B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 +#define NVC7B5_OFFSET_IN_UPPER (0x00000400) +#define NVC7B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC7B5_OFFSET_IN_LOWER (0x00000404) +#define NVC7B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC7B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC7B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC7B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC7B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC7B5_PITCH_IN (0x00000410) +#define NVC7B5_PITCH_IN_VALUE 31:0 +#define NVC7B5_PITCH_OUT (0x00000414) +#define NVC7B5_PITCH_OUT_VALUE 31:0 +#define NVC7B5_LINE_LENGTH_IN (0x00000418) +#define NVC7B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC7B5_LINE_COUNT (0x0000041C) +#define NVC7B5_LINE_COUNT_VALUE 31:0 +#define NVC7B5_SET_REMAP_CONST_A (0x00000700) +#define NVC7B5_SET_REMAP_CONST_A_V 31:0 +#define NVC7B5_SET_REMAP_CONST_B (0x00000704) +#define NVC7B5_SET_REMAP_CONST_B_V 31:0 +#define NVC7B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC7B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC7B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC7B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC7B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC7B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC7B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC7B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC7B5_SET_DST_WIDTH (0x00000710) +#define NVC7B5_SET_DST_WIDTH_V 31:0 +#define NVC7B5_SET_DST_HEIGHT (0x00000714) +#define NVC7B5_SET_DST_HEIGHT_V 31:0 +#define NVC7B5_SET_DST_DEPTH (0x00000718) +#define NVC7B5_SET_DST_DEPTH_V 31:0 +#define NVC7B5_SET_DST_LAYER (0x0000071C) +#define NVC7B5_SET_DST_LAYER_V 31:0 +#define NVC7B5_SET_DST_ORIGIN (0x00000720) +#define NVC7B5_SET_DST_ORIGIN_X 15:0 +#define NVC7B5_SET_DST_ORIGIN_Y 31:16 +#define NVC7B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC7B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC7B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC7B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC7B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC7B5_SET_SRC_WIDTH (0x0000072C) +#define NVC7B5_SET_SRC_WIDTH_V 31:0 +#define NVC7B5_SET_SRC_HEIGHT (0x00000730) +#define NVC7B5_SET_SRC_HEIGHT_V 31:0 +#define NVC7B5_SET_SRC_DEPTH (0x00000734) +#define NVC7B5_SET_SRC_DEPTH_V 31:0 +#define NVC7B5_SET_SRC_LAYER (0x00000738) +#define NVC7B5_SET_SRC_LAYER_V 31:0 +#define NVC7B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC7B5_SET_SRC_ORIGIN_X 15:0 +#define NVC7B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC7B5_SRC_ORIGIN_X (0x00000744) +#define NVC7B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC7B5_SRC_ORIGIN_Y (0x00000748) +#define NVC7B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC7B5_DST_ORIGIN_X (0x0000074C) +#define NVC7B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC7B5_DST_ORIGIN_Y (0x00000750) +#define NVC7B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC7B5_PM_TRIGGER_END (0x00001114) +#define NVC7B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc7b5_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc7b7.h b/userspace/sdks/nv570/nvidia/inc/class/clc7b7.h new file mode 100644 index 0000000..909195b --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc7b7.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef clc7b7_h_ +#define clc7b7_h_ + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC7B7_VIDEO_ENCODER (0x0000C7B7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // clc7b7_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc7c0.h b/userspace/sdks/nv570/nvidia/inc/class/clc7c0.h new file mode 100644 index 0000000..6eb2889 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc7c0.h @@ -0,0 +1,848 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_ampere_compute_b_h_ +#define _cl_ampere_compute_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl ampere_compute_b */ + +#include "nvtypes.h" + +#define AMPERE_COMPUTE_B 0xC7C0 + +#define NVC7C0_SET_OBJECT 0x0000 +#define NVC7C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC7C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC7C0_NO_OPERATION 0x0100 +#define NVC7C0_NO_OPERATION_V 31:0 + +#define NVC7C0_SET_NOTIFY_A 0x0104 +#define NVC7C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC7C0_SET_NOTIFY_B 0x0108 +#define NVC7C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC7C0_NOTIFY 0x010c +#define NVC7C0_NOTIFY_TYPE 31:0 +#define NVC7C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC7C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC7C0_WAIT_FOR_IDLE 0x0110 +#define NVC7C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC7C0_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC7C0_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC7C0_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC7C0_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC7C0_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC7C0_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC7C0_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC7C0_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC7C0_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC7C0_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC7C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC7C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC7C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC7C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC7C0_SEND_GO_IDLE 0x013c +#define NVC7C0_SEND_GO_IDLE_V 31:0 + +#define NVC7C0_PM_TRIGGER 0x0140 +#define NVC7C0_PM_TRIGGER_V 31:0 + +#define NVC7C0_PM_TRIGGER_WFI 0x0144 +#define NVC7C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC7C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC7C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC7C0_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC7C0_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC7C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC7C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC7C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC7C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER 0x0158 +#define NVC7C0_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER_PAYLOAD_LOWER 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER 0x015c +#define NVC7C0_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD_UPPER 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_ADDRESS_LOWER 0x0160 +#define NVC7C0_SET_REPORT_SEMAPHORE_ADDRESS_LOWER_LOWER 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_ADDRESS_UPPER 0x0164 +#define NVC7C0_SET_REPORT_SEMAPHORE_ADDRESS_UPPER_UPPER 7:0 + +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE 0x0168 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_OPERATION 1:0 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_OPERATION_RELEASE 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_OPERATION_ACQUIRE 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_OPERATION_REPORT_ONLY 0x00000002 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_OPERATION_TRAP 0x00000003 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE 2:2 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE 4:3 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE 5:5 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE 6:6 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP 9:7 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_INC 0x00000003 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_AND 0x00000005 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_OR 0x00000006 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT 11:10 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64 12:12 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_FALSE 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_TRUE 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE 14:13 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_NONE 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 + +#define NVC7C0_LINE_LENGTH_IN 0x0180 +#define NVC7C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC7C0_LINE_COUNT 0x0184 +#define NVC7C0_LINE_COUNT_VALUE 31:0 + +#define NVC7C0_OFFSET_OUT_UPPER 0x0188 +#define NVC7C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC7C0_OFFSET_OUT 0x018c +#define NVC7C0_OFFSET_OUT_VALUE 31:0 + +#define NVC7C0_PITCH_OUT 0x0190 +#define NVC7C0_PITCH_OUT_VALUE 31:0 + +#define NVC7C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC7C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC7C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC7C0_SET_DST_WIDTH 0x0198 +#define NVC7C0_SET_DST_WIDTH_V 31:0 + +#define NVC7C0_SET_DST_HEIGHT 0x019c +#define NVC7C0_SET_DST_HEIGHT_V 31:0 + +#define NVC7C0_SET_DST_DEPTH 0x01a0 +#define NVC7C0_SET_DST_DEPTH_V 31:0 + +#define NVC7C0_SET_DST_LAYER 0x01a4 +#define NVC7C0_SET_DST_LAYER_V 31:0 + +#define NVC7C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC7C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC7C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC7C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC7C0_LAUNCH_DMA 0x01b0 +#define NVC7C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC7C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC7C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC7C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC7C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC7C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC7C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC7C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC7C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC7C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC7C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC7C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC7C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC7C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC7C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC7C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC7C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC7C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC7C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC7C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC7C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC7C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC7C0_LOAD_INLINE_DATA 0x01b4 +#define NVC7C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC7C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC7C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC7C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC7C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC7C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC7C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC7C0_SET_SM_SCG_CONTROL 0x01e8 +#define NVC7C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS 0:0 +#define NVC7C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE 0x00000000 +#define NVC7C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE 0x00000001 + +#define NVC7C0_SET_MME_SWITCH_STATE 0x01ec +#define NVC7C0_SET_MME_SWITCH_STATE_VALID 0:0 +#define NVC7C0_SET_MME_SWITCH_STATE_VALID_FALSE 0x00000000 +#define NVC7C0_SET_MME_SWITCH_STATE_VALID_TRUE 0x00000001 +#define NVC7C0_SET_MME_SWITCH_STATE_SAVE_MACRO 11:4 +#define NVC7C0_SET_MME_SWITCH_STATE_RESTORE_MACRO 19:12 + +#define NVC7C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC7C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC7C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC7C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC7C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC7C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC7C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC7C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC7C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC7C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC7C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC7C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC7C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC7C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC7C0_PERFMON_TRANSFER 0x0210 +#define NVC7C0_PERFMON_TRANSFER_V 31:0 + +#define NVC7C0_SET_QMD_VIRTUALIZATION_BASE_A 0x0214 +#define NVC7C0_SET_QMD_VIRTUALIZATION_BASE_A_ADDRESS_UPPER 7:0 + +#define NVC7C0_SET_QMD_VIRTUALIZATION_BASE_B 0x0218 +#define NVC7C0_SET_QMD_VIRTUALIZATION_BASE_B_ADDRESS_LOWER 31:0 + +#define NVC7C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC7C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC7C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC7C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC7C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC7C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC7C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC7C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC7C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC7C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC7C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC7C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC7C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC7C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC7C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC7C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC7C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC7C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC7C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC7C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC7C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC7C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC7C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC7C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC7C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC7C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC7C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC7C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC7C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC7C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC7C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC7C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC7C0_SET_SCG_CONTROL 0x0270 +#define NVC7C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 +#define NVC7C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 +#define NVC7C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 +#define NVC7C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 +#define NVC7C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 + +#define NVC7C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC7C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC7C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC7C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC7C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC7C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC7C0_SET_QMD_VERSION 0x0288 +#define NVC7C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC7C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC7C0_CHECK_QMD_VERSION 0x0290 +#define NVC7C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC7C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC7C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC7C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL 0x029c +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_CONSTANT_BUFFER_MASK 7:0 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE 8:8 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE 12:12 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_DEPENDENT_ENABLE 9:9 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_DEPENDENT_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_DEPENDENT_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE 16:16 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE 20:20 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_DEPENDENT_ENABLE 10:10 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_DEPENDENT_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_DEPENDENT_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE 24:24 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_TRUE 0x00000001 + +#define NVC7C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC7C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC7C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC7C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC7C0_SCG_HYSTERESIS_CONTROL 0x02a8 +#define NVC7C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 +#define NVC7C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC7C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 +#define NVC7C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 +#define NVC7C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC7C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 + +#define NVC7C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC7C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC7C0_SEND_PCAS_A 0x02b4 +#define NVC7C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC7C0_SEND_PCAS_B 0x02b8 +#define NVC7C0_SEND_PCAS_B_FROM 23:0 +#define NVC7C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC7C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC7C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC7C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC7C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC7C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC7C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC7C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC7C0_SEND_SIGNALING_PCAS2_B 0x02c0 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION 3:0 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_NOP 0x00000000 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE 0x00000001 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_SCHEDULE 0x00000002 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_COPY_SCHEDULE 0x00000003 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_PUT 0x00000006 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_DECREMENT_DEPENDENCE 0x00000007 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH 0x00000008 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH_SCHEDULE 0x00000009 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_SCHEDULE 0x0000000A +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_FORCE_REQUIRE_SCHEDULING 0x0000000B +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_DEPENDENCE 0x0000000C +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_CWD_REF_COUNTER 0x0000000D +#define NVC7C0_SEND_SIGNALING_PCAS2_B_SELECT 13:8 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_OFFSET_MINUS_ONE 23:14 + +#define NVC7C0_SET_SKED_CACHE_CONTROL 0x02cc +#define NVC7C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID 0:0 +#define NVC7C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE 0x00000000 +#define NVC7C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE 0x00000001 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC7C0_SET_SPA_VERSION 0x0310 +#define NVC7C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC7C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC7C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC7C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC7C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC7C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC7C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC7C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC7C0_SET_FALCON00 0x0500 +#define NVC7C0_SET_FALCON00_V 31:0 + +#define NVC7C0_SET_FALCON01 0x0504 +#define NVC7C0_SET_FALCON01_V 31:0 + +#define NVC7C0_SET_FALCON02 0x0508 +#define NVC7C0_SET_FALCON02_V 31:0 + +#define NVC7C0_SET_FALCON03 0x050c +#define NVC7C0_SET_FALCON03_V 31:0 + +#define NVC7C0_SET_FALCON04 0x0510 +#define NVC7C0_SET_FALCON04_V 31:0 + +#define NVC7C0_SET_FALCON05 0x0514 +#define NVC7C0_SET_FALCON05_V 31:0 + +#define NVC7C0_SET_FALCON06 0x0518 +#define NVC7C0_SET_FALCON06_V 31:0 + +#define NVC7C0_SET_FALCON07 0x051c +#define NVC7C0_SET_FALCON07_V 31:0 + +#define NVC7C0_SET_FALCON08 0x0520 +#define NVC7C0_SET_FALCON08_V 31:0 + +#define NVC7C0_SET_FALCON09 0x0524 +#define NVC7C0_SET_FALCON09_V 31:0 + +#define NVC7C0_SET_FALCON10 0x0528 +#define NVC7C0_SET_FALCON10_V 31:0 + +#define NVC7C0_SET_FALCON11 0x052c +#define NVC7C0_SET_FALCON11_V 31:0 + +#define NVC7C0_SET_FALCON12 0x0530 +#define NVC7C0_SET_FALCON12_V 31:0 + +#define NVC7C0_SET_FALCON13 0x0534 +#define NVC7C0_SET_FALCON13_V 31:0 + +#define NVC7C0_SET_FALCON14 0x0538 +#define NVC7C0_SET_FALCON14_V 31:0 + +#define NVC7C0_SET_FALCON15 0x053c +#define NVC7C0_SET_FALCON15_V 31:0 + +#define NVC7C0_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVC7C0_SET_MME_MEM_ADDRESS_A_UPPER 16:0 + +#define NVC7C0_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVC7C0_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVC7C0_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVC7C0_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVC7C0_MME_DMA_READ 0x055c +#define NVC7C0_MME_DMA_READ_LENGTH 31:0 + +#define NVC7C0_MME_DMA_READ_FIFOED 0x0560 +#define NVC7C0_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVC7C0_MME_DMA_WRITE 0x0564 +#define NVC7C0_MME_DMA_WRITE_LENGTH 31:0 + +#define NVC7C0_MME_DMA_REDUCTION 0x0568 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVC7C0_MME_DMA_SYSMEMBAR 0x056c +#define NVC7C0_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVC7C0_MME_DMA_SYNC 0x0570 +#define NVC7C0_MME_DMA_SYNC_VALUE 31:0 + +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC7C0_THROTTLE_SM 0x07fc +#define NVC7C0_THROTTLE_SM_MULTIPLY_ADD 0:0 +#define NVC7C0_THROTTLE_SM_MULTIPLY_ADD_FALSE 0x00000000 +#define NVC7C0_THROTTLE_SM_MULTIPLY_ADD_TRUE 0x00000001 + +#define NVC7C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC7C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC7C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC7C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS(i) (0x0da0+(i)*4) +#define NVC7C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC7C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC7C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC7C0_MME_DMA_WRITE_METHOD_BARRIER 0x0dec +#define NVC7C0_MME_DMA_WRITE_METHOD_BARRIER_V 0:0 + +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC7C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC7C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC7C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC7C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC7C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC7C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC7C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC7C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC7C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC7C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC7C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC7C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC7C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC7C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC7C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC7C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC7C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC7C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC7C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC7C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC7C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC7C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC7C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC7C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC7C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC7C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC7C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC7C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC7C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC7C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC7C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC7C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC7C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC7C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC7C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC7C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC7C0_PIPE_NOP 0x1a2c +#define NVC7C0_PIPE_NOP_V 31:0 + +#define NVC7C0_SET_SPARE00 0x1a30 +#define NVC7C0_SET_SPARE00_V 31:0 + +#define NVC7C0_SET_SPARE01 0x1a34 +#define NVC7C0_SET_SPARE01_V 31:0 + +#define NVC7C0_SET_SPARE02 0x1a38 +#define NVC7C0_SET_SPARE02_V 31:0 + +#define NVC7C0_SET_SPARE03 0x1a3c +#define NVC7C0_SET_SPARE03_V 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC7C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC7C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC7C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC7C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC7C0_SET_TRAP_HANDLER_A 0x25f8 +#define NVC7C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC7C0_SET_TRAP_HANDLER_B 0x25fc +#define NVC7C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC7C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC7C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC7C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC7C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC7C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC7C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC7C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC7C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC7C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC7C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC7C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC7C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC7C0_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC7C0_CALL_MME_MACRO_V 31:0 + +#define NVC7C0_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC7C0_CALL_MME_DATA_V 31:0 + +#endif /* _cl_ampere_compute_b_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc7fa.h b/userspace/sdks/nv570/nvidia/inc/class/clc7fa.h new file mode 100644 index 0000000..50892c5 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc7fa.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "nvtypes.h" + +#ifndef _clc7fa_h_ +#define _clc7fa_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC7FA_VIDEO_OFA (0x0000C7FA) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc7fa_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc86f.h b/userspace/sdks/nv570/nvidia/inc/class/clc86f.h new file mode 100644 index 0000000..48154a3 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc86f.h @@ -0,0 +1,84 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clc86f_h__ +#define __gh100_clc86f_h__ + +typedef volatile struct Nvc86fControl_struct { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} Nvc86fControl, HopperAControlGPFifo; + +#define HOPPER_CHANNEL_GPFIFO_A (0x0000C86F) +#define NVC86F_SET_OBJECT (0x00000000) +#define NVC86F_SEM_ADDR_LO (0x0000005c) +#define NVC86F_SEM_ADDR_LO_OFFSET 31:2 +#define NVC86F_SEM_ADDR_HI (0x00000060) +#define NVC86F_SEM_ADDR_HI_OFFSET 24:0 +#define NVC86F_SEM_PAYLOAD_LO (0x00000064) +#define NVC86F_SEM_PAYLOAD_HI (0x00000068) +#define NVC86F_SEM_EXECUTE (0x0000006c) +#define NVC86F_SEM_EXECUTE_OPERATION 2:0 +#define NVC86F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001 +#define NVC86F_SEM_EXECUTE_RELEASE_WFI 20:20 +#define NVC86F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000 +#define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE 24:24 +#define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000 + +/* GPFIFO entry format */ +#define NVC86F_GP_ENTRY__SIZE 8 +#define NVC86F_GP_ENTRY0_FETCH 0:0 +#define NVC86F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVC86F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVC86F_GP_ENTRY0_GET 31:2 +#define NVC86F_GP_ENTRY0_OPERAND 31:0 +#define NVC86F_GP_ENTRY0_PB_EXTENDED_BASE_OPERAND 24:8 +#define NVC86F_GP_ENTRY1_GET_HI 7:0 +#define NVC86F_GP_ENTRY1_LEVEL 9:9 +#define NVC86F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVC86F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVC86F_GP_ENTRY1_LENGTH 30:10 +#define NVC86F_GP_ENTRY1_SYNC 31:31 +#define NVC86F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVC86F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVC86F_GP_ENTRY1_OPCODE 7:0 +#define NVC86F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVC86F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVC86F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVC86F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 +#define NVC86F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE 0x00000004 + +#endif // __gh100_clc86f_h__ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc86fsw.h b/userspace/sdks/nv570/nvidia/inc/class/clc86fsw.h new file mode 100644 index 0000000..dce4dfd --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc86fsw.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* This file is *not* auto-generated. */ + +#ifndef _clc86f_sw_h_ +#define _clc86f_sw_h_ + +#define NVC86F_NOTIFIERS_RC (0) +#define NVC86F_NOTIFIERS_REFCNT (1) +#define NVC86F_NOTIFIERS_NONSTALL (2) +#define NVC86F_NOTIFIERS_EVENTBUFFER (3) +#define NVC86F_NOTIFIERS_IDLECHANNEL (4) +#define NVC86F_NOTIFIERS_ENDCTX (5) +#define NVC86F_NOTIFIERS_SW (6) +#define NVC86F_NOTIFIERS_GR_DEBUG_INTR (7) +#define NVC86F_NOTIFIERS_REPLAYABLE_FAULT (8) +#define NVC86F_NOTIFIERS_MAXCOUNT (9) + +/* NvNotification[] fields and values */ +#define NVC86F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NVC86F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) + +#endif /* _clc56f_sw_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc8b5.h b/userspace/sdks/nv570/nvidia/inc/class/clc8b5.h new file mode 100644 index 0000000..38fd8be --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc8b5.h @@ -0,0 +1,77 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clc8b5_h__ +#define __gh100_clc8b5_h__ +#define HOPPER_DMA_COPY_A (0x0000C8B5) +#define NVC8B5_SET_SEMAPHORE_A (0x00000240) +#define NVC8B5_SET_SEMAPHORE_A_UPPER 24:0 +#define NVC8B5_SET_SEMAPHORE_B (0x00000244) +#define NVC8B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC8B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC8B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC8B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC8B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC8B5_LAUNCH_DMA (0x00000300) +#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC8B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC8B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC8B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC8B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC8B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC8B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC8B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC8B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE 23:23 +#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_TRUE (0x00000001) +#define NVC8B5_LAUNCH_DMA_DISABLE_PLC 26:26 +#define NVC8B5_LAUNCH_DMA_DISABLE_PLC_TRUE (0x00000001) +#define NVC8B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC8B5_OFFSET_OUT_UPPER_UPPER 24:0 +#define NVC8B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC8B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC8B5_LINE_LENGTH_IN (0x00000418) +#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS (0x000006FC) +#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE 0:0 +#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_FALSE (0x00000000) +#define NVC8B5_SET_REMAP_CONST_A (0x00000700) +#define NVC8B5_SET_REMAP_CONST_B (0x00000704) +#define NVC8B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#endif // __gh100_clc8b5_h__ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc997.h b/userspace/sdks/nv570/nvidia/inc/class/clc997.h new file mode 100644 index 0000000..81607be --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc997.h @@ -0,0 +1,4481 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_ada_a_h_ +#define _cl_ada_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl ada_a */ + +#include "nvtypes.h" + +#define ADA_A 0xC997 + +#define NVC997_SET_OBJECT 0x0000 +#define NVC997_SET_OBJECT_CLASS_ID 15:0 +#define NVC997_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC997_NO_OPERATION 0x0100 +#define NVC997_NO_OPERATION_V 31:0 + +#define NVC997_SET_NOTIFY_A 0x0104 +#define NVC997_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC997_SET_NOTIFY_B 0x0108 +#define NVC997_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC997_NOTIFY 0x010c +#define NVC997_NOTIFY_TYPE 31:0 +#define NVC997_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC997_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC997_WAIT_FOR_IDLE 0x0110 +#define NVC997_WAIT_FOR_IDLE_V 31:0 + +#define NVC997_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC997_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC997_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC997_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC997_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC997_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC997_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC997_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC997_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC997_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC997_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC997_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC997_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC997_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC997_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC997_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC997_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC997_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC997_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC997_SEND_GO_IDLE 0x013c +#define NVC997_SEND_GO_IDLE_V 31:0 + +#define NVC997_PM_TRIGGER 0x0140 +#define NVC997_PM_TRIGGER_V 31:0 + +#define NVC997_PM_TRIGGER_WFI 0x0144 +#define NVC997_PM_TRIGGER_WFI_V 31:0 + +#define NVC997_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC997_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC997_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC997_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC997_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC997_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC997_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC997_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER 0x0158 +#define NVC997_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER_PAYLOAD_LOWER 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER 0x015c +#define NVC997_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD_UPPER 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_ADDRESS_LOWER 0x0160 +#define NVC997_SET_REPORT_SEMAPHORE_ADDRESS_LOWER_LOWER 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_ADDRESS_UPPER 0x0164 +#define NVC997_SET_REPORT_SEMAPHORE_ADDRESS_UPPER_UPPER 7:0 + +#define NVC997_REPORT_SEMAPHORE_EXECUTE 0x0168 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_OPERATION 1:0 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_OPERATION_RELEASE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_OPERATION_ACQUIRE 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_OPERATION_REPORT_ONLY 0x00000002 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_OPERATION_TRAP 0x00000003 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION 5:2 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC997_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE 6:6 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT 11:7 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_NONE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_SCG_CLOCKS 0x00000008 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS0 0x0000000A +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS1 0x0000000C +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS2 0x0000000E +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS3 0x00000010 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_TIMESTAMP 0x00000014 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE 14:13 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_SUB_REPORT 17:15 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE 19:19 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE 18:18 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE 20:20 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP 23:21 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_INC 0x00000003 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_AND 0x00000005 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_OR 0x00000006 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT 25:24 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64 27:27 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_FALSE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_TRUE 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE 29:28 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_NONE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 + +#define NVC997_LINE_LENGTH_IN 0x0180 +#define NVC997_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC997_LINE_COUNT 0x0184 +#define NVC997_LINE_COUNT_VALUE 31:0 + +#define NVC997_OFFSET_OUT_UPPER 0x0188 +#define NVC997_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC997_OFFSET_OUT 0x018c +#define NVC997_OFFSET_OUT_VALUE 31:0 + +#define NVC997_PITCH_OUT 0x0190 +#define NVC997_PITCH_OUT_VALUE 31:0 + +#define NVC997_SET_DST_BLOCK_SIZE 0x0194 +#define NVC997_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC997_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC997_SET_DST_WIDTH 0x0198 +#define NVC997_SET_DST_WIDTH_V 31:0 + +#define NVC997_SET_DST_HEIGHT 0x019c +#define NVC997_SET_DST_HEIGHT_V 31:0 + +#define NVC997_SET_DST_DEPTH 0x01a0 +#define NVC997_SET_DST_DEPTH_V 31:0 + +#define NVC997_SET_DST_LAYER 0x01a4 +#define NVC997_SET_DST_LAYER_V 31:0 + +#define NVC997_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC997_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC997_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC997_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC997_LAUNCH_DMA 0x01b0 +#define NVC997_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC997_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC997_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC997_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC997_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC997_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC997_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC997_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC997_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC997_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC997_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC997_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC997_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC997_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC997_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC997_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC997_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC997_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC997_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC997_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC997_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC997_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC997_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC997_LOAD_INLINE_DATA 0x01b4 +#define NVC997_LOAD_INLINE_DATA_V 31:0 + +#define NVC997_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC997_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC997_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC997_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC997_SET_MME_SWITCH_STATE 0x01ec +#define NVC997_SET_MME_SWITCH_STATE_VALID 0:0 +#define NVC997_SET_MME_SWITCH_STATE_VALID_FALSE 0x00000000 +#define NVC997_SET_MME_SWITCH_STATE_VALID_TRUE 0x00000001 +#define NVC997_SET_MME_SWITCH_STATE_SAVE_MACRO 11:4 +#define NVC997_SET_MME_SWITCH_STATE_RESTORE_MACRO 19:12 + +#define NVC997_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC997_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC997_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC997_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC997_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC997_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC997_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC997_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC997_RUN_DS_NOW 0x0200 +#define NVC997_RUN_DS_NOW_V 31:0 + +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC997_SET_GS_MODE 0x0208 +#define NVC997_SET_GS_MODE_TYPE 0:0 +#define NVC997_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVC997_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVC997_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC997_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC997_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC997_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC997_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC997_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_GS_DM_FIFO 0x0214 +#define NVC997_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC997_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC997_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC997_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC997_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC997_INVALIDATE_SHADER_CACHES 0x021c +#define NVC997_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC997_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC997_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC997_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC997_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC997_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC997_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC997_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC997_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC997_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC997_SET_INSTANCE_COUNT 0x0220 +#define NVC997_SET_INSTANCE_COUNT_V 31:0 + +#define NVC997_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVC997_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVC997_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC997_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVC997_SET_MME_VERSION 0x0234 +#define NVC997_SET_MME_VERSION_MAJOR 7:0 + +#define NVC997_SET_INDEX_BUFFER_SIZE_A 0x0238 +#define NVC997_SET_INDEX_BUFFER_SIZE_A_UPPER 7:0 + +#define NVC997_SET_INDEX_BUFFER_SIZE_B 0x023c +#define NVC997_SET_INDEX_BUFFER_SIZE_B_LOWER 31:0 + +#define NVC997_SET_ROOT_TABLE_VISIBILITY(i) (0x0240+(i)*4) +#define NVC997_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP0_ENABLE 1:0 +#define NVC997_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP1_ENABLE 5:4 +#define NVC997_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP2_ENABLE 9:8 +#define NVC997_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP3_ENABLE 13:12 +#define NVC997_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP4_ENABLE 17:16 + +#define NVC997_SET_DRAW_CONTROL_A 0x0260 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY 3:0 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_POINTS 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_LINES 0x00000001 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_QUADS 0x00000007 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_PATCH 0x0000000E +#define NVC997_SET_DRAW_CONTROL_A_PRIMITIVE_ID 4:4 +#define NVC997_SET_DRAW_CONTROL_A_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ID 6:5 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ID_FIRST 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC997_SET_DRAW_CONTROL_A_SPLIT_MODE 8:7 +#define NVC997_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC997_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC997_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE 9:9 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 +#define NVC997_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX 10:10 +#define NVC997_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_FALSE 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_TRUE 0x00000001 +#define NVC997_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX 11:11 +#define NVC997_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_FALSE 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_TRUE 0x00000001 + +#define NVC997_SET_DRAW_CONTROL_B 0x0264 +#define NVC997_SET_DRAW_CONTROL_B_INSTANCE_COUNT 31:0 + +#define NVC997_DRAW_INDEX_BUFFER_BEGIN_END_A 0x0268 +#define NVC997_DRAW_INDEX_BUFFER_BEGIN_END_A_FIRST 31:0 + +#define NVC997_DRAW_INDEX_BUFFER_BEGIN_END_B 0x026c +#define NVC997_DRAW_INDEX_BUFFER_BEGIN_END_B_COUNT 31:0 + +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_A 0x0270 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_A_START 31:0 + +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_B 0x0274 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_B_COUNT 31:0 + +#define NVC997_INVALIDATE_RASTER_CACHE_NO_WFI 0x027c +#define NVC997_INVALIDATE_RASTER_CACHE_NO_WFI_V 0:0 + +#define NVC997_SET_COLOR_RENDER_TO_ZETA_SURFACE 0x02b8 +#define NVC997_SET_COLOR_RENDER_TO_ZETA_SURFACE_V 0:0 +#define NVC997_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_FALSE 0x00000000 +#define NVC997_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_TRUE 0x00000001 + +#define NVC997_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION 0x02bc +#define NVC997_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V 0:0 +#define NVC997_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_FALSE 0x00000000 +#define NVC997_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_TRUE 0x00000001 + +#define NVC997_INCREMENT_SYNC_POINT 0x02c8 +#define NVC997_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC997_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC997_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC997_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC997_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC997_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC997_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC997_SET_ROOT_TABLE_PREFETCH 0x02d0 +#define NVC997_SET_ROOT_TABLE_PREFETCH_STAGE_ENABLES 5:0 + +#define NVC997_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC997_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC997_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC997_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVC997_DECOMPRESS_SURFACE 0x02e0 +#define NVC997_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC997_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC997_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC997_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC997_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC997_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC997_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC997_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC997_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC997_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC997_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC997_SET_ZCULL_SUBREGION 0x02e8 +#define NVC997_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC997_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC997_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC997_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC997_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC997_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC997_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC997_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC997_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC997_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC997_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC997_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC997_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC997_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC997_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC997_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC997_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC997_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC997_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC997_DRAW_ZERO_INDEX 0x0304 +#define NVC997_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC997_SET_L1_CONFIGURATION 0x0308 +#define NVC997_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC997_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC997_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC997_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC997_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC997_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC997_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC997_SET_SPA_VERSION 0x0310 +#define NVC997_SET_SPA_VERSION_MINOR 7:0 +#define NVC997_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC997_SET_TIMESLICE_BATCH_LIMIT 0x0314 +#define NVC997_SET_TIMESLICE_BATCH_LIMIT_BATCH_LIMIT 15:0 + +#define NVC997_SET_SNAP_GRID_LINE 0x0318 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC997_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC997_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC997_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC997_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC997_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC997_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC997_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC997_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC997_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC997_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC997_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC997_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC997_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC997_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC997_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC997_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC997_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC997_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC997_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC997_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC997_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC997_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC997_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC997_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC997_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC997_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC997_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC997_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC997_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC997_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC997_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC997_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC997_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC997_RESERVED_TG07 0x033c +#define NVC997_RESERVED_TG07_V 0:0 + +#define NVC997_RESERVED_TG08 0x0340 +#define NVC997_RESERVED_TG08_V 0:0 + +#define NVC997_RESERVED_TG09 0x0344 +#define NVC997_RESERVED_TG09_V 0:0 + +#define NVC997_RESERVED_TG10 0x0348 +#define NVC997_RESERVED_TG10_V 0:0 + +#define NVC997_RESERVED_TG11 0x034c +#define NVC997_RESERVED_TG11_V 0:0 + +#define NVC997_RESERVED_TG12 0x0350 +#define NVC997_RESERVED_TG12_V 0:0 + +#define NVC997_RESERVED_TG13 0x0354 +#define NVC997_RESERVED_TG13_V 0:0 + +#define NVC997_RESERVED_TG14 0x0358 +#define NVC997_RESERVED_TG14_V 0:0 + +#define NVC997_RESERVED_TG15 0x035c +#define NVC997_RESERVED_TG15_V 0:0 + +#define NVC997_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC997_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC997_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC997_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC997_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC997_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC997_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC997_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC997_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC997_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC997_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC997_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC997_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC997_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC997_SET_RASTER_ENABLE 0x037c +#define NVC997_SET_RASTER_ENABLE_V 0:0 +#define NVC997_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC997_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC997_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC997_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC997_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC997_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC997_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC997_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC997_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC997_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC997_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVC997_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVC997_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVC997_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVC997_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVC997_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVC997_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVC997_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVC997_SET_Z_ROP_SLICE_MAP 0x0500 +#define NVC997_SET_Z_ROP_SLICE_MAP_VIRTUAL_ADDRESS_MASK 31:0 + +#define NVC997_SET_ROOT_TABLE_SELECTOR 0x0504 +#define NVC997_SET_ROOT_TABLE_SELECTOR_ROOT_TABLE 2:0 +#define NVC997_SET_ROOT_TABLE_SELECTOR_OFFSET 15:8 + +#define NVC997_LOAD_ROOT_TABLE 0x0508 +#define NVC997_LOAD_ROOT_TABLE_V 31:0 + +#define NVC997_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVC997_SET_MME_MEM_ADDRESS_A_UPPER 16:0 + +#define NVC997_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVC997_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVC997_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVC997_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVC997_MME_DMA_READ 0x055c +#define NVC997_MME_DMA_READ_LENGTH 31:0 + +#define NVC997_MME_DMA_READ_FIFOED 0x0560 +#define NVC997_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVC997_MME_DMA_WRITE 0x0564 +#define NVC997_MME_DMA_WRITE_LENGTH 31:0 + +#define NVC997_MME_DMA_REDUCTION 0x0568 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVC997_MME_DMA_SYSMEMBAR 0x056c +#define NVC997_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVC997_MME_DMA_SYNC 0x0570 +#define NVC997_MME_DMA_SYNC_VALUE 31:0 + +#define NVC997_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NVC997_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NVC997_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NVC997_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NVC997_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NVC997_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NVC997_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NVC997_SET_VERTEX_STREAM_SIZE_A(j) (0x0600+(j)*8) +#define NVC997_SET_VERTEX_STREAM_SIZE_A_UPPER 7:0 + +#define NVC997_SET_VERTEX_STREAM_SIZE_B(j) (0x0604+(j)*8) +#define NVC997_SET_VERTEX_STREAM_SIZE_B_LOWER 31:0 + +#define NVC997_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC997_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC997_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC997_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC997_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC997_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC997_SET_RASTER_INPUT 0x0740 +#define NVC997_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC997_SET_STREAM_OUTPUT 0x0744 +#define NVC997_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC997_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC997_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC997_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC997_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC997_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC997_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC997_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC997_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC997_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC997_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC997_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC997_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC997_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC997_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC997_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC997_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC997_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC997_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC997_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC997_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC997_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC997_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC997_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC997_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC997_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVC997_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC997_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC997_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC997_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC997_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC997_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC997_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC997_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC997_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC997_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC997_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC997_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC997_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC997_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC997_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC997_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC997_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC997_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC997_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC997_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC997_SET_ZCULL_STORAGE_B 0x07ec +#define NVC997_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC997_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC997_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC997_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC997_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC997_SET_ZT_READ_ONLY 0x07f8 +#define NVC997_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC997_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC997_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC997_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC997_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC997_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC997_THROTTLE_SM 0x07fc +#define NVC997_THROTTLE_SM_MULTIPLY_ADD 0:0 +#define NVC997_THROTTLE_SM_MULTIPLY_ADD_FALSE 0x00000000 +#define NVC997_THROTTLE_SM_MULTIPLY_ADD_TRUE 0x00000001 + +#define NVC997_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC997_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC997_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC997_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC997_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC997_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC997_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC997_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC997_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC997_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC997_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC997_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC997_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC997_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC997_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC997_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC997_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC997_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC997_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC997_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC997_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC997_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC997_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC997_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC997_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC997_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC997_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC997_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC997_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC997_SET_COLOR_TARGET_C_ROP_SLICE_MAP(j) (0x0824+(j)*64) +#define NVC997_SET_COLOR_TARGET_C_ROP_SLICE_MAP_VIRTUAL_ADDRESS_MASK 31:0 + +#define NVC997_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC997_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC997_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC997_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC997_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC997_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC997_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC997_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC997_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC997_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC997_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC997_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC997_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC997_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC997_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC997_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC997_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC997_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC997_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC997_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC997_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC997_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC997_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC997_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC997_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC997_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC997_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC997_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC997_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC997_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC997_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC997_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC997_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC997_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC997_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC997_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC997_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC997_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC997_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC997_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC997_SET_STATISTICS_COUNTER 0x0d68 +#define NVC997_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC997_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC997_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC997_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC997_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC997_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC997_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC997_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC997_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC997_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC997_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC997_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC997_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC997_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC997_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC997_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC997_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVC997_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC997_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC997_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC997_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC997_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC997_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC997_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC997_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC997_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC997_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC997_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC997_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC997_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC997_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC997_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC997_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC997_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC997_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC997_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC997_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC997_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC997_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC997_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC997_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC997_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC997_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC997_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC997_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC997_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC997_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC997_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC997_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC997_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC997_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC997_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC997_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC997_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC997_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC997_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC997_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC997_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC997_SET_POLY_SMOOTH 0x0db4 +#define NVC997_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC997_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC997_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC997_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC997_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC997_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC997_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC997_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC997_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC997_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_PATCH 0x0dcc +#define NVC997_SET_PATCH_SIZE 7:0 + +#define NVC997_SET_ITERATED_BLEND 0x0dd0 +#define NVC997_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC997_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC997_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC997_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC997_SET_ZCULL_CRITERION 0x0dd8 +#define NVC997_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC997_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC997_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC997_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC997_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC997_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC997_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC997_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC997_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC997_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC997_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 +#define NVC997_PIXEL_SHADER_BARRIER_BARRIER_LOCATION 1:1 +#define NVC997_PIXEL_SHADER_BARRIER_BARRIER_LOCATION_BLOCK_BEFORE_PS 0x00000000 +#define NVC997_PIXEL_SHADER_BARRIER_BARRIER_LOCATION_BLOCK_BEFORE_PS_AND_ZTEST 0x00000001 + +#define NVC997_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC997_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC997_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC997_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC997_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC997_MME_DMA_WRITE_METHOD_BARRIER 0x0dec +#define NVC997_MME_DMA_WRITE_METHOD_BARRIER_V 0:0 + +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC997_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC997_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC997_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC997_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC997_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC997_SET_SCISSOR_ENABLE_V 0:0 +#define NVC997_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC997_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC997_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC997_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC997_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC997_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC997_SET_VPC_PERF_KNOB 0x0f14 +#define NVC997_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC997_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC997_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC997_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC997_PM_LOCAL_TRIGGER 0x0f18 +#define NVC997_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC997_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC997_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC997_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC997_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC997_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC997_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC997_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC997_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC997_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC997_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC997_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC997_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC997_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC997_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC997_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC997_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC997_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC997_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC997_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC997_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC997_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC997_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC997_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC997_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC997_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC997_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC997_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC997_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC997_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC997_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC997_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC997_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC997_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC997_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC997_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC997_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC997_SET_SAMPLE_MASK 0x0fa4 +#define NVC997_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC997_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC997_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC997_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC997_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC997_SET_CT_MRT_ENABLE 0x0fac +#define NVC997_SET_CT_MRT_ENABLE_V 0:0 +#define NVC997_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC997_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC997_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC997_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC997_SET_TIR 0x0fb4 +#define NVC997_SET_TIR_MODE 1:0 +#define NVC997_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC997_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC997_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC997_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC997_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC997_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC997_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC997_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC997_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC997_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC997_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC997_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC997_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC997_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC997_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC997_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC997_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC997_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC997_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC997_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_TIR_MODULATION 0x0fd4 +#define NVC997_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC997_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC997_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC997_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC997_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC997_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC997_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC997_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC997_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC997_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC997_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC997_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC997_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC997_SET_ZT_A 0x0fe0 +#define NVC997_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_ZT_B 0x0fe4 +#define NVC997_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_ZT_FORMAT 0x0fe8 +#define NVC997_SET_ZT_FORMAT_V 4:0 +#define NVC997_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC997_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC997_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC997_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC997_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC997_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC997_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC997_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC997_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC997_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC997_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC997_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC997_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC997_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC997_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC997_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC997_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC997_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC997_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC997_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC997_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC997_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC997_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC997_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC997_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC997_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC997_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC997_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC997_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC997_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC997_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC997_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC997_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC997_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC997_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC997_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC997_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC997_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC997_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC997_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC997_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC997_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC997_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC997_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC997_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC997_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD02 0x102c +#define NVC997_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC997_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC997_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC997_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC997_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC997_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC997_SET_SPARE_NOOP01 0x1044 +#define NVC997_SET_SPARE_NOOP01_V 31:0 + +#define NVC997_SET_SPARE_NOOP02 0x1048 +#define NVC997_SET_SPARE_NOOP02_V 31:0 + +#define NVC997_SET_SPARE_NOOP03 0x104c +#define NVC997_SET_SPARE_NOOP03_V 31:0 + +#define NVC997_SET_SPARE_NOOP04 0x1050 +#define NVC997_SET_SPARE_NOOP04_V 31:0 + +#define NVC997_SET_SPARE_NOOP05 0x1054 +#define NVC997_SET_SPARE_NOOP05_V 31:0 + +#define NVC997_SET_SPARE_NOOP06 0x1058 +#define NVC997_SET_SPARE_NOOP06_V 31:0 + +#define NVC997_SET_SPARE_NOOP07 0x105c +#define NVC997_SET_SPARE_NOOP07_V 31:0 + +#define NVC997_SET_SPARE_NOOP08 0x1060 +#define NVC997_SET_SPARE_NOOP08_V 31:0 + +#define NVC997_SET_SPARE_NOOP09 0x1064 +#define NVC997_SET_SPARE_NOOP09_V 31:0 + +#define NVC997_SET_SPARE_NOOP10 0x1068 +#define NVC997_SET_SPARE_NOOP10_V 31:0 + +#define NVC997_SET_SPARE_NOOP11 0x106c +#define NVC997_SET_SPARE_NOOP11_V 31:0 + +#define NVC997_SET_SPARE_NOOP12 0x1070 +#define NVC997_SET_SPARE_NOOP12_V 31:0 + +#define NVC997_SET_SPARE_NOOP13 0x1074 +#define NVC997_SET_SPARE_NOOP13_V 31:0 + +#define NVC997_SET_SPARE_NOOP14 0x1078 +#define NVC997_SET_SPARE_NOOP14_V 31:0 + +#define NVC997_SET_SPARE_NOOP15 0x107c +#define NVC997_SET_SPARE_NOOP15_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC997_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC997_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC997_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC997_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC997_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC997_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC997_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC997_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC997_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC997_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC997_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC997_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC997_UNBIND_ALL 0x10f4 +#define NVC997_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC997_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC997_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC997_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC997_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC997_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC997_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC997_NO_OPERATION_DATA_HI 0x110c +#define NVC997_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC997_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC997_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC997_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC997_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC997_PM_TRIGGER_END 0x1114 +#define NVC997_PM_TRIGGER_END_V 31:0 + +#define NVC997_SET_VERTEX_ID_BASE 0x1118 +#define NVC997_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC997_SET_STENCIL_COMPRESSION 0x111c +#define NVC997_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC997_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC997_SET_TIR_CONTROL 0x1130 +#define NVC997_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC997_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC997_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC997_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC997_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC997_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC997_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC997_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC997_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 +#define NVC997_SET_TIR_CONTROL_REDUCTION_MODE 2:2 +#define NVC997_SET_TIR_CONTROL_REDUCTION_MODE_AFFINITY_MAP 0x00000000 +#define NVC997_SET_TIR_CONTROL_REDUCTION_MODE_TRUNCATION 0x00000001 + +#define NVC997_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC997_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC997_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC997_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC997_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC997_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC997_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC997_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC997_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC997_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC997_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC997_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC997_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC997_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC997_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC997_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC997_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC997_FLUSH_PENDING_WRITES 0x1144 +#define NVC997_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC997_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC997_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC997_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC997_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC997_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC997_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC997_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC997_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC997_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC997_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC997_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC997_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC997_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC997_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC997_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC997_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC997_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC997_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC997_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC997_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC997_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC997_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_SCREEN_STATE_MASK 0x1204 +#define NVC997_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC997_SET_ZT_SPARSE 0x1208 +#define NVC997_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC997_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC997_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC997_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_SET_CT_SELECT 0x121c +#define NVC997_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC997_SET_CT_SELECT_TARGET0 6:4 +#define NVC997_SET_CT_SELECT_TARGET1 9:7 +#define NVC997_SET_CT_SELECT_TARGET2 12:10 +#define NVC997_SET_CT_SELECT_TARGET3 15:13 +#define NVC997_SET_CT_SELECT_TARGET4 18:16 +#define NVC997_SET_CT_SELECT_TARGET5 21:19 +#define NVC997_SET_CT_SELECT_TARGET6 24:22 +#define NVC997_SET_CT_SELECT_TARGET7 27:25 + +#define NVC997_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC997_SET_ZT_SIZE_A 0x1228 +#define NVC997_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC997_SET_ZT_SIZE_B 0x122c +#define NVC997_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC997_SET_ZT_SIZE_C 0x1230 +#define NVC997_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC997_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC997_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC997_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC997_SET_SAMPLER_BINDING 0x1234 +#define NVC997_SET_SAMPLER_BINDING_V 0:0 +#define NVC997_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC997_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC997_DRAW_AUTO 0x123c +#define NVC997_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC997_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC997_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC997_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC997_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC997_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC997_SET_BACK_END_COPY_A 0x1264 +#define NVC997_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC997_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC997_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC997_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC997_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BACK_END_COPY_B 0x1268 +#define NVC997_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC997_SET_BACK_END_COPY_C 0x126c +#define NVC997_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC997_SET_BACK_END_COPY_D 0x1270 +#define NVC997_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC997_SET_BACK_END_COPY_E 0x1274 +#define NVC997_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC997_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC997_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVC997_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC997_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC997_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC997_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC997_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC997_CLEAR_ZCULL_REGION 0x12c8 +#define NVC997_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC997_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC997_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC997_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC997_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC997_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC997_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC997_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC997_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC997_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC997_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC997_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC997_SET_DEPTH_TEST 0x12cc +#define NVC997_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC997_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_FILL_MODE 0x12d0 +#define NVC997_SET_FILL_MODE_V 31:0 +#define NVC997_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC997_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC997_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC997_SET_SHADE_MODE 0x12d4 +#define NVC997_SET_SHADE_MODE_V 31:0 +#define NVC997_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC997_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC997_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC997_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC997_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC997_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC997_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC997_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC997_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC997_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC997_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC997_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_DEPTH_WRITE 0x12e8 +#define NVC997_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC997_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_ALPHA_TEST 0x12ec +#define NVC997_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC997_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC997_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC997_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC997_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC997_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC997_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC997_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC997_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC997_D3D_SET_CULL_MODE 0x1308 +#define NVC997_D3D_SET_CULL_MODE_V 31:0 +#define NVC997_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC997_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC997_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC997_SET_DEPTH_FUNC 0x130c +#define NVC997_SET_DEPTH_FUNC_V 31:0 +#define NVC997_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC997_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC997_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC997_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC997_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC997_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC997_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC997_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC997_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC997_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC997_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC997_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC997_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC997_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC997_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC997_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC997_SET_ALPHA_REF 0x1310 +#define NVC997_SET_ALPHA_REF_V 31:0 + +#define NVC997_SET_ALPHA_FUNC 0x1314 +#define NVC997_SET_ALPHA_FUNC_V 31:0 +#define NVC997_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC997_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC997_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC997_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC997_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC997_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC997_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC997_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC997_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC997_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC997_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC997_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC997_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC997_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC997_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC997_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC997_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC997_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC997_SET_BLEND_CONST_RED 0x131c +#define NVC997_SET_BLEND_CONST_RED_V 31:0 + +#define NVC997_SET_BLEND_CONST_GREEN 0x1320 +#define NVC997_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC997_SET_BLEND_CONST_BLUE 0x1324 +#define NVC997_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC997_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC997_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC997_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC997_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC997_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC997_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC997_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC997_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC997_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC997_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BLEND_COLOR_OP 0x1340 +#define NVC997_SET_BLEND_COLOR_OP_V 31:0 +#define NVC997_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC997_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC997_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC997_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC997_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC997_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC997_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC997_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC997_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC997_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_BLEND_ALPHA_OP 0x134c +#define NVC997_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC997_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC997_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC997_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC997_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC997_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC997_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC997_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC997_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC997_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC997_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC997_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC997_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC997_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC997_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC997_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BLEND(i) (0x1360+(i)*4) +#define NVC997_SET_BLEND_ENABLE 0:0 +#define NVC997_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_STENCIL_TEST 0x1380 +#define NVC997_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC997_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_STENCIL_OP_FAIL 0x1384 +#define NVC997_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC997_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC997_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC997_SET_STENCIL_OP_ZPASS 0x138c +#define NVC997_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC997_SET_STENCIL_FUNC 0x1390 +#define NVC997_SET_STENCIL_FUNC_V 31:0 +#define NVC997_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC997_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC997_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC997_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC997_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC997_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC997_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC997_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC997_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC997_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC997_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC997_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC997_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC997_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC997_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC997_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC997_SET_STENCIL_FUNC_REF 0x1394 +#define NVC997_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC997_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC997_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC997_SET_STENCIL_MASK 0x139c +#define NVC997_SET_STENCIL_MASK_V 7:0 + +#define NVC997_SET_DRAW_AUTO_START 0x13a4 +#define NVC997_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC997_SET_PS_SATURATE 0x13a8 +#define NVC997_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC997_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC997_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC997_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC997_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC997_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC997_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC997_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC997_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC997_SET_WINDOW_ORIGIN 0x13ac +#define NVC997_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC997_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC997_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC997_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC997_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC997_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC997_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC997_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC997_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC997_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC997_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC997_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC997_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC997_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC997_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC997_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC997_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC997_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC997_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC997_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC997_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC997_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC997_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC997_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC997_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC997_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC997_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC997_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC997_STORE_ZCULL 0x1464 +#define NVC997_STORE_ZCULL_V 0:0 + +#define NVC997_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC997_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC997_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC997_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC997_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC997_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC997_LOAD_ZCULL 0x1500 +#define NVC997_LOAD_ZCULL_V 0:0 + +#define NVC997_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC997_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC997_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC997_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC997_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC997_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC997_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC997_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC997_SET_USER_CLIP_ENABLE 0x1510 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC997_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC997_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC997_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_POINT_SIZE 0x1518 +#define NVC997_SET_POINT_SIZE_V 31:0 + +#define NVC997_SET_ZCULL_STATS 0x151c +#define NVC997_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC997_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_POINT_SPRITE 0x1520 +#define NVC997_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC997_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC997_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC997_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC997_CLEAR_REPORT_VALUE 0x1530 +#define NVC997_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC997_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC997_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC997_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC997_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC997_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC997_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVC997_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC997_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC997_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_ZT_SELECT 0x1538 +#define NVC997_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC997_SET_RENDER_ENABLE_A 0x1550 +#define NVC997_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_RENDER_ENABLE_B 0x1554 +#define NVC997_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_RENDER_ENABLE_C 0x1558 +#define NVC997_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC997_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC997_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC997_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC997_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC997_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC997_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC997_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC997_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC997_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC997_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC997_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC997_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC997_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC997_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC997_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC997_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_TEX_HEADER_POOL_C 0x157c +#define NVC997_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC997_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC997_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC997_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC997_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC997_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC997_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC997_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC997_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC997_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC997_SET_SRGB_WRITE 0x15b8 +#define NVC997_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC997_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_DEPTH_BIAS 0x15bc +#define NVC997_SET_DEPTH_BIAS_V 31:0 + +#define NVC997_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC997_SET_RT_LAYER 0x15cc +#define NVC997_SET_RT_LAYER_V 15:0 +#define NVC997_SET_RT_LAYER_CONTROL 16:16 +#define NVC997_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC997_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC997_SET_ANTI_ALIAS 0x15d0 +#define NVC997_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC997_SET_EDGE_FLAG 0x15e4 +#define NVC997_SET_EDGE_FLAG_V 0:0 +#define NVC997_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC997_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC997_DRAW_INLINE_INDEX 0x15e8 +#define NVC997_DRAW_INLINE_INDEX_V 31:0 + +#define NVC997_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC997_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC997_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC997_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC997_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC997_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC997_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC997_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC997_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC997_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC997_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC997_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC997_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC997_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC997_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC997_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC997_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC997_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC997_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC997_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC997_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC997_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC997_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC997_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC997_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC997_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC997_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC997_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC997_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC997_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC997_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC997_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC997_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC997_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC997_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC997_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC997_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC997_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC997_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC997_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC997_END 0x1614 +#define NVC997_END_V 0:0 + +#define NVC997_BEGIN 0x1618 +#define NVC997_BEGIN_OP 15:0 +#define NVC997_BEGIN_OP_POINTS 0x00000000 +#define NVC997_BEGIN_OP_LINES 0x00000001 +#define NVC997_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC997_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC997_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC997_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC997_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC997_BEGIN_OP_QUADS 0x00000007 +#define NVC997_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC997_BEGIN_OP_POLYGON 0x00000009 +#define NVC997_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC997_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC997_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_BEGIN_OP_PATCH 0x0000000E +#define NVC997_BEGIN_PRIMITIVE_ID 24:24 +#define NVC997_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC997_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC997_BEGIN_INSTANCE_ID 27:26 +#define NVC997_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC997_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC997_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC997_BEGIN_SPLIT_MODE 30:29 +#define NVC997_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC997_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC997_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC997_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC997_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVC997_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC997_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_VERTEX_ID_COPY 0x161c +#define NVC997_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC997_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC997_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC997_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC997_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC997_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC997_LOAD_PRIMITIVE_ID 0x1624 +#define NVC997_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC997_SET_SHADER_BASED_CULL 0x162c +#define NVC997_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC997_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC997_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC997_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_CLASS_VERSION 0x1638 +#define NVC997_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC997_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC997_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC997_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC997_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC997_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC997_SET_DA_OUTPUT 0x164c +#define NVC997_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC997_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC997_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC997_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC997_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_POINT_CENTER_MODE 0x165c +#define NVC997_SET_POINT_CENTER_MODE_V 31:0 +#define NVC997_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC997_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC997_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC997_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC997_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC997_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC997_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC997_SET_LINE_STIPPLE 0x166c +#define NVC997_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC997_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC997_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC997_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC997_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC997_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC997_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC997_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC997_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC997_SET_PROVOKING_VERTEX 0x1684 +#define NVC997_SET_PROVOKING_VERTEX_V 0:0 +#define NVC997_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC997_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC997_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC997_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC997_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_POLYGON_STIPPLE 0x168c +#define NVC997_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC997_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_SHADER_CONTROL 0x1690 +#define NVC997_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC997_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC997_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC997_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC997_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC997_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC997_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC997_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC997_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC997_CHECK_CLASS_VERSION 0x16a0 +#define NVC997_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC997_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC997_SET_SPH_VERSION 0x16a4 +#define NVC997_SET_SPH_VERSION_CURRENT 15:0 +#define NVC997_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC997_CHECK_SPH_VERSION 0x16a8 +#define NVC997_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC997_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC997_SET_SCG_GRAPHICS_PRIORITY 0x16bc +#define NVC997_SET_SCG_GRAPHICS_PRIORITY_PRIORITY 5:0 + +#define NVC997_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS(i) (0x16c0+(i)*4) +#define NVC997_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC997_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC997_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC997_SET_AAM_VERSION 0x1790 +#define NVC997_SET_AAM_VERSION_CURRENT 15:0 +#define NVC997_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC997_CHECK_AAM_VERSION 0x1794 +#define NVC997_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC997_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC997_SET_ZT_LAYER 0x179c +#define NVC997_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC997_SET_INDEX_BUFFER_A 0x17c8 +#define NVC997_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC997_SET_INDEX_BUFFER_B 0x17cc +#define NVC997_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC997_SET_INDEX_BUFFER_E 0x17d8 +#define NVC997_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC997_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC997_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC997_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC997_SET_INDEX_BUFFER_F 0x17dc +#define NVC997_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC997_DRAW_INDEX_BUFFER 0x17e0 +#define NVC997_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC997_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC997_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC997_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC997_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC997_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC997_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC997_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC997_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC997_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC997_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC997_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC997_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC997_OGL_SET_CULL 0x1918 +#define NVC997_OGL_SET_CULL_ENABLE 0:0 +#define NVC997_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC997_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC997_OGL_SET_FRONT_FACE 0x191c +#define NVC997_OGL_SET_FRONT_FACE_V 31:0 +#define NVC997_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC997_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC997_OGL_SET_CULL_FACE 0x1920 +#define NVC997_OGL_SET_CULL_FACE_V 31:0 +#define NVC997_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC997_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC997_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC997_SET_VIEWPORT_PIXEL 0x1924 +#define NVC997_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC997_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC997_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC997_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC997_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC997_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC997_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE 17:16 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_USE_FIELD_MIN_Z_ZERO_MAX_Z_ONE 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MIN_Z_MAX_Z 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_ZERO_ONE 0x00000002 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MINUS_INF_PLUS_INF 0x00000003 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC997_SET_USER_CLIP_OP 0x1940 +#define NVC997_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC997_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC997_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC997_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC997_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC997_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC997_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC997_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC997_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC997_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC997_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC997_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC997_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC997_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC997_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC997_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC997_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC997_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC997_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC997_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC997_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC997_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC997_INVALIDATE_ZCULL 0x1958 +#define NVC997_INVALIDATE_ZCULL_V 31:0 +#define NVC997_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC997_SET_ZCULL 0x1968 +#define NVC997_SET_ZCULL_Z_ENABLE 0:0 +#define NVC997_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC997_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_ZCULL_BOUNDS 0x196c +#define NVC997_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC997_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC997_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC997_ZCULL_SYNC 0x1978 +#define NVC997_ZCULL_SYNC_V 31:0 + +#define NVC997_SET_CLIP_ID_TEST 0x197c +#define NVC997_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC997_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC997_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC997_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC997_SET_CLIP_ID 0x1984 +#define NVC997_SET_CLIP_ID_V 31:0 + +#define NVC997_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC997_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC997_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC997_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC997_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC997_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC997_SET_LOGIC_OP 0x19c4 +#define NVC997_SET_LOGIC_OP_ENABLE 0:0 +#define NVC997_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC997_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC997_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC997_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC997_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC997_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC997_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC997_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC997_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC997_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC997_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC997_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC997_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC997_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC997_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC997_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC997_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC997_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC997_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC997_SET_Z_COMPRESSION 0x19cc +#define NVC997_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC997_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC997_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC997_CLEAR_SURFACE 0x19d0 +#define NVC997_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC997_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC997_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC997_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC997_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC997_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC997_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC997_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC997_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC997_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC997_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC997_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC997_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC997_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC997_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC997_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC997_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC997_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC997_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC997_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC997_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC997_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC997_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC997_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC997_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC997_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC997_PIPE_NOP 0x1a2c +#define NVC997_PIPE_NOP_V 31:0 + +#define NVC997_SET_SPARE00 0x1a30 +#define NVC997_SET_SPARE00_V 31:0 + +#define NVC997_SET_SPARE01 0x1a34 +#define NVC997_SET_SPARE01_V 31:0 + +#define NVC997_SET_SPARE02 0x1a38 +#define NVC997_SET_SPARE02_V 31:0 + +#define NVC997_SET_SPARE03 0x1a3c +#define NVC997_SET_SPARE03_V 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC997_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC997_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC997_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC997_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC997_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC997_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC997_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC997_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC997_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC997_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC997_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC997_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_TIMESTAMP 0x00000014 +#define NVC997_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC997_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC997_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC997_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC997_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC997_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC997_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC997_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC997_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC997_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC997_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC997_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC997_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC997_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC997_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC997_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC997_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC997_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC997_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC997_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC997_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC997_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC997_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC997_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC997_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC997_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC997_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC997_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC997_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC997_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC997_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC997_SET_PIPELINE_RESERVED_B(j) (0x2004+(j)*64) +#define NVC997_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVC997_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC997_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC997_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC997_SET_PIPELINE_REGISTER_COUNT_V 8:0 + +#define NVC997_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC997_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC997_SET_PIPELINE_PROGRAM_ADDRESS_A(j) (0x2014+(j)*64) +#define NVC997_SET_PIPELINE_PROGRAM_ADDRESS_A_UPPER 7:0 + +#define NVC997_SET_PIPELINE_PROGRAM_ADDRESS_B(j) (0x2018+(j)*64) +#define NVC997_SET_PIPELINE_PROGRAM_ADDRESS_B_LOWER 31:0 + +#define NVC997_SET_PIPELINE_PROGRAM_PREFETCH(j) (0x201c+(j)*64) +#define NVC997_SET_PIPELINE_PROGRAM_PREFETCH_SIZE_IN_BLOCKS 6:0 + +#define NVC997_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC997_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC997_SET_FALCON00 0x2300 +#define NVC997_SET_FALCON00_V 31:0 + +#define NVC997_SET_FALCON01 0x2304 +#define NVC997_SET_FALCON01_V 31:0 + +#define NVC997_SET_FALCON02 0x2308 +#define NVC997_SET_FALCON02_V 31:0 + +#define NVC997_SET_FALCON03 0x230c +#define NVC997_SET_FALCON03_V 31:0 + +#define NVC997_SET_FALCON04 0x2310 +#define NVC997_SET_FALCON04_V 31:0 + +#define NVC997_SET_FALCON05 0x2314 +#define NVC997_SET_FALCON05_V 31:0 + +#define NVC997_SET_FALCON06 0x2318 +#define NVC997_SET_FALCON06_V 31:0 + +#define NVC997_SET_FALCON07 0x231c +#define NVC997_SET_FALCON07_V 31:0 + +#define NVC997_SET_FALCON08 0x2320 +#define NVC997_SET_FALCON08_V 31:0 + +#define NVC997_SET_FALCON09 0x2324 +#define NVC997_SET_FALCON09_V 31:0 + +#define NVC997_SET_FALCON10 0x2328 +#define NVC997_SET_FALCON10_V 31:0 + +#define NVC997_SET_FALCON11 0x232c +#define NVC997_SET_FALCON11_V 31:0 + +#define NVC997_SET_FALCON12 0x2330 +#define NVC997_SET_FALCON12_V 31:0 + +#define NVC997_SET_FALCON13 0x2334 +#define NVC997_SET_FALCON13_V 31:0 + +#define NVC997_SET_FALCON14 0x2338 +#define NVC997_SET_FALCON14_V 31:0 + +#define NVC997_SET_FALCON15 0x233c +#define NVC997_SET_FALCON15_V 31:0 + +#define NVC997_SET_FALCON16 0x2340 +#define NVC997_SET_FALCON16_V 31:0 + +#define NVC997_SET_FALCON17 0x2344 +#define NVC997_SET_FALCON17_V 31:0 + +#define NVC997_SET_FALCON18 0x2348 +#define NVC997_SET_FALCON18_V 31:0 + +#define NVC997_SET_FALCON19 0x234c +#define NVC997_SET_FALCON19_V 31:0 + +#define NVC997_SET_FALCON20 0x2350 +#define NVC997_SET_FALCON20_V 31:0 + +#define NVC997_SET_FALCON21 0x2354 +#define NVC997_SET_FALCON21_V 31:0 + +#define NVC997_SET_FALCON22 0x2358 +#define NVC997_SET_FALCON22_V 31:0 + +#define NVC997_SET_FALCON23 0x235c +#define NVC997_SET_FALCON23_V 31:0 + +#define NVC997_SET_FALCON24 0x2360 +#define NVC997_SET_FALCON24_V 31:0 + +#define NVC997_SET_FALCON25 0x2364 +#define NVC997_SET_FALCON25_V 31:0 + +#define NVC997_SET_FALCON26 0x2368 +#define NVC997_SET_FALCON26_V 31:0 + +#define NVC997_SET_FALCON27 0x236c +#define NVC997_SET_FALCON27_V 31:0 + +#define NVC997_SET_FALCON28 0x2370 +#define NVC997_SET_FALCON28_V 31:0 + +#define NVC997_SET_FALCON29 0x2374 +#define NVC997_SET_FALCON29_V 31:0 + +#define NVC997_SET_FALCON30 0x2378 +#define NVC997_SET_FALCON30_V 31:0 + +#define NVC997_SET_FALCON31 0x237c +#define NVC997_SET_FALCON31_V 31:0 + +#define NVC997_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC997_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC997_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC997_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC997_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC997_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC997_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC997_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC997_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC997_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC997_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC997_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC997_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC997_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC997_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC997_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC997_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC997_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC997_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC997_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC997_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC997_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC997_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC997_SET_TRAP_HANDLER_A 0x25f8 +#define NVC997_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC997_SET_TRAP_HANDLER_B 0x25fc +#define NVC997_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC997_SET_COLOR_CLAMP 0x2600 +#define NVC997_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC997_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC997_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC997_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC997_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC997_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC997_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC997_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC997_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC997_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC997_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC997_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC997_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC997_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC997_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC997_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC997_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC997_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC997_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC997_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC997_CALL_MME_MACRO_V 31:0 + +#define NVC997_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC997_CALL_MME_DATA_V 31:0 + +#endif /* _cl_ada_a_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc9b0.h b/userspace/sdks/nv570/nvidia/inc/class/clc9b0.h new file mode 100644 index 0000000..604fe53 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc9b0.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc9b0_h_ +#define _clc9b0_h_ + +#define NVC9B0_VIDEO_DECODER (0x0000C9B0) + +#endif diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc9b7.h b/userspace/sdks/nv570/nvidia/inc/class/clc9b7.h new file mode 100644 index 0000000..6a0caef --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc9b7.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc9b7_h_ +#define _clc9b7_h_ + +#define NVC9B7_VIDEO_ENCODER (0x0000C9B7) + +#endif diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc9c0.h b/userspace/sdks/nv570/nvidia/inc/class/clc9c0.h new file mode 100644 index 0000000..35da97f --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc9c0.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc9c0_h_ +#define _clc9c0_h_ + +#define ADA_COMPUTE_A 0xC9C0 + +#endif diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc9d1.h b/userspace/sdks/nv570/nvidia/inc/class/clc9d1.h new file mode 100644 index 0000000..6849f96 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc9d1.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _clc9d1_h_ +#define _clc9d1_h_ + +#define NVC9D1_VIDEO_NVJPG (0x0000C9D1) + +#endif // _clc9d1_h diff --git a/userspace/sdks/nv570/nvidia/inc/class/clc9fa.h b/userspace/sdks/nv570/nvidia/inc/class/clc9fa.h new file mode 100644 index 0000000..6b4a20a --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clc9fa.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _clc9fa_h_ +#define _clc9fa_h_ + +#define NVC9FA_VIDEO_OFA (0x0000C9FA) + +#endif // _clc9fa_h + diff --git a/userspace/sdks/nv570/nvidia/inc/class/clcb97.h b/userspace/sdks/nv570/nvidia/inc/class/clcb97.h new file mode 100644 index 0000000..7528a2d --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clcb97.h @@ -0,0 +1,4480 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_hopper_a_h_ +#define _cl_hopper_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl hopper_a */ + +#include "nvtypes.h" + +#define HOPPER_A 0xCB97 + +#define NVCB97_SET_OBJECT 0x0000 +#define NVCB97_SET_OBJECT_CLASS_ID 15:0 +#define NVCB97_SET_OBJECT_ENGINE_ID 20:16 + +#define NVCB97_NO_OPERATION 0x0100 +#define NVCB97_NO_OPERATION_V 31:0 + +#define NVCB97_SET_NOTIFY_A 0x0104 +#define NVCB97_SET_NOTIFY_A_ADDRESS_UPPER 24:0 + +#define NVCB97_SET_NOTIFY_B 0x0108 +#define NVCB97_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVCB97_NOTIFY 0x010c +#define NVCB97_NOTIFY_TYPE 31:0 +#define NVCB97_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVCB97_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVCB97_WAIT_FOR_IDLE 0x0110 +#define NVCB97_WAIT_FOR_IDLE_V 31:0 + +#define NVCB97_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVCB97_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVCB97_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVCB97_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVCB97_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVCB97_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVCB97_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVCB97_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVCB97_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVCB97_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVCB97_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVCB97_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVCB97_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVCB97_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVCB97_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVCB97_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVCB97_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVCB97_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVCB97_SEND_GO_IDLE 0x013c +#define NVCB97_SEND_GO_IDLE_V 31:0 + +#define NVCB97_PM_TRIGGER 0x0140 +#define NVCB97_PM_TRIGGER_V 31:0 + +#define NVCB97_PM_TRIGGER_WFI 0x0144 +#define NVCB97_PM_TRIGGER_WFI_V 31:0 + +#define NVCB97_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVCB97_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVCB97_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVCB97_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVCB97_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVCB97_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVCB97_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVCB97_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER 0x0158 +#define NVCB97_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER_PAYLOAD_LOWER 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER 0x015c +#define NVCB97_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD_UPPER 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_ADDRESS_LOWER 0x0160 +#define NVCB97_SET_REPORT_SEMAPHORE_ADDRESS_LOWER_LOWER 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_ADDRESS_UPPER 0x0164 +#define NVCB97_SET_REPORT_SEMAPHORE_ADDRESS_UPPER_UPPER 24:0 + +#define NVCB97_REPORT_SEMAPHORE_EXECUTE 0x0168 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_OPERATION 1:0 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_OPERATION_RELEASE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_OPERATION_ACQUIRE 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_OPERATION_REPORT_ONLY 0x00000002 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_OPERATION_TRAP 0x00000003 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION 5:2 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_NONE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_VPC 0x00000004 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_ALL 0x0000000F +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE 6:6 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT 11:7 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_NONE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_VS_INVOCATIONS 0x00000005 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_TI_INVOCATIONS 0x0000001B +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_TS_INVOCATIONS 0x0000001D +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_GS_INVOCATIONS 0x00000007 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_SCG_CLOCKS 0x00000008 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS0 0x0000000A +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS1 0x0000000C +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS2 0x0000000E +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS3 0x00000010 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_PS_INVOCATIONS 0x00000013 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_TIMESTAMP 0x00000014 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE 14:13 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_SUB_REPORT 17:15 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE 19:19 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_FALSE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_TRUE 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE 18:18 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE_FALSE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE_TRUE 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE 20:20 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP 23:21 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_ADD 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MIN 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MAX 0x00000002 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_INC 0x00000003 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_DEC 0x00000004 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_AND 0x00000005 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_OR 0x00000006 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_XOR 0x00000007 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT 25:24 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64 27:27 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_FALSE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_TRUE 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE 29:28 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_NONE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 + +#define NVCB97_LINE_LENGTH_IN 0x0180 +#define NVCB97_LINE_LENGTH_IN_VALUE 31:0 + +#define NVCB97_LINE_COUNT 0x0184 +#define NVCB97_LINE_COUNT_VALUE 31:0 + +#define NVCB97_OFFSET_OUT_UPPER 0x0188 +#define NVCB97_OFFSET_OUT_UPPER_VALUE 24:0 + +#define NVCB97_OFFSET_OUT 0x018c +#define NVCB97_OFFSET_OUT_VALUE 31:0 + +#define NVCB97_PITCH_OUT 0x0190 +#define NVCB97_PITCH_OUT_VALUE 31:0 + +#define NVCB97_SET_DST_BLOCK_SIZE 0x0194 +#define NVCB97_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVCB97_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVCB97_SET_DST_WIDTH 0x0198 +#define NVCB97_SET_DST_WIDTH_V 31:0 + +#define NVCB97_SET_DST_HEIGHT 0x019c +#define NVCB97_SET_DST_HEIGHT_V 31:0 + +#define NVCB97_SET_DST_DEPTH 0x01a0 +#define NVCB97_SET_DST_DEPTH_V 31:0 + +#define NVCB97_SET_DST_LAYER 0x01a4 +#define NVCB97_SET_DST_LAYER_V 31:0 + +#define NVCB97_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVCB97_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVCB97_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVCB97_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVCB97_LAUNCH_DMA 0x01b0 +#define NVCB97_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVCB97_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVCB97_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVCB97_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVCB97_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVCB97_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVCB97_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVCB97_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVCB97_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVCB97_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVCB97_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVCB97_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVCB97_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVCB97_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVCB97_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVCB97_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVCB97_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVCB97_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVCB97_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVCB97_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVCB97_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVCB97_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVCB97_LOAD_INLINE_DATA 0x01b4 +#define NVCB97_LOAD_INLINE_DATA_V 31:0 + +#define NVCB97_SET_I2M_SEMAPHORE_A 0x01dc +#define NVCB97_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 24:0 + +#define NVCB97_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVCB97_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVCB97_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVCB97_SET_MME_SWITCH_STATE 0x01ec +#define NVCB97_SET_MME_SWITCH_STATE_VALID 0:0 +#define NVCB97_SET_MME_SWITCH_STATE_VALID_FALSE 0x00000000 +#define NVCB97_SET_MME_SWITCH_STATE_VALID_TRUE 0x00000001 +#define NVCB97_SET_MME_SWITCH_STATE_SAVE_MACRO 11:4 +#define NVCB97_SET_MME_SWITCH_STATE_RESTORE_MACRO 19:12 + +#define NVCB97_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVCB97_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVCB97_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVCB97_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVCB97_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVCB97_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVCB97_SET_I2M_SPARE_NOOP03 0x01fc +#define NVCB97_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVCB97_RUN_DS_NOW 0x0200 +#define NVCB97_RUN_DS_NOW_V 31:0 + +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVCB97_SET_GS_MODE 0x0208 +#define NVCB97_SET_GS_MODE_TYPE 0:0 +#define NVCB97_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVCB97_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVCB97_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVCB97_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVCB97_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVCB97_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVCB97_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_GS_DM_FIFO 0x0214 +#define NVCB97_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVCB97_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVCB97_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVCB97_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVCB97_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVCB97_INVALIDATE_SHADER_CACHES 0x021c +#define NVCB97_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVCB97_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVCB97_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVCB97_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVCB97_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVCB97_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVCB97_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVCB97_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVCB97_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVCB97_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVCB97_SET_INSTANCE_COUNT 0x0220 +#define NVCB97_SET_INSTANCE_COUNT_V 31:0 + +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_GO_IDLE_TIMEOUT 0x022c +#define NVCB97_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVCB97_SET_MME_VERSION 0x0234 +#define NVCB97_SET_MME_VERSION_MAJOR 7:0 + +#define NVCB97_SET_INDEX_BUFFER_SIZE_A 0x0238 +#define NVCB97_SET_INDEX_BUFFER_SIZE_A_UPPER 7:0 + +#define NVCB97_SET_INDEX_BUFFER_SIZE_B 0x023c +#define NVCB97_SET_INDEX_BUFFER_SIZE_B_LOWER 31:0 + +#define NVCB97_SET_ROOT_TABLE_VISIBILITY(i) (0x0240+(i)*4) +#define NVCB97_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP0_ENABLE 1:0 +#define NVCB97_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP1_ENABLE 5:4 +#define NVCB97_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP2_ENABLE 9:8 +#define NVCB97_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP3_ENABLE 13:12 +#define NVCB97_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP4_ENABLE 17:16 + +#define NVCB97_SET_DRAW_CONTROL_A 0x0260 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY 3:0 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_LINES 0x00000001 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_PATCH 0x0000000E +#define NVCB97_SET_DRAW_CONTROL_A_PRIMITIVE_ID 4:4 +#define NVCB97_SET_DRAW_CONTROL_A_PRIMITIVE_ID_FIRST 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ID 6:5 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ID_FIRST 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVCB97_SET_DRAW_CONTROL_A_SPLIT_MODE 8:7 +#define NVCB97_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVCB97_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVCB97_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE 9:9 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX 10:10 +#define NVCB97_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_FALSE 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_TRUE 0x00000001 +#define NVCB97_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX 11:11 +#define NVCB97_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_FALSE 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_TRUE 0x00000001 + +#define NVCB97_SET_DRAW_CONTROL_B 0x0264 +#define NVCB97_SET_DRAW_CONTROL_B_INSTANCE_COUNT 31:0 + +#define NVCB97_DRAW_INDEX_BUFFER_BEGIN_END_A 0x0268 +#define NVCB97_DRAW_INDEX_BUFFER_BEGIN_END_A_FIRST 31:0 + +#define NVCB97_DRAW_INDEX_BUFFER_BEGIN_END_B 0x026c +#define NVCB97_DRAW_INDEX_BUFFER_BEGIN_END_B_COUNT 31:0 + +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_A 0x0270 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_A_START 31:0 + +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_B 0x0274 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_B_COUNT 31:0 + +#define NVCB97_INVALIDATE_RASTER_CACHE_NO_WFI 0x027c +#define NVCB97_INVALIDATE_RASTER_CACHE_NO_WFI_V 0:0 + +#define NVCB97_SET_COLOR_RENDER_TO_ZETA_SURFACE 0x02b8 +#define NVCB97_SET_COLOR_RENDER_TO_ZETA_SURFACE_V 0:0 +#define NVCB97_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_FALSE 0x00000000 +#define NVCB97_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_TRUE 0x00000001 + +#define NVCB97_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION 0x02bc +#define NVCB97_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V 0:0 +#define NVCB97_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_TRUE 0x00000001 + +#define NVCB97_INCREMENT_SYNC_POINT 0x02c8 +#define NVCB97_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVCB97_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVCB97_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVCB97_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVCB97_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVCB97_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVCB97_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVCB97_SET_ROOT_TABLE_PREFETCH 0x02d0 +#define NVCB97_SET_ROOT_TABLE_PREFETCH_STAGE_ENABLES 5:0 + +#define NVCB97_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVCB97_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVCB97_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVCB97_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVCB97_DECOMPRESS_SURFACE 0x02e0 +#define NVCB97_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVCB97_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVCB97_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVCB97_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVCB97_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVCB97_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVCB97_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVCB97_SET_ZCULL_SUBREGION 0x02e8 +#define NVCB97_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVCB97_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVCB97_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVCB97_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVCB97_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVCB97_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVCB97_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVCB97_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVCB97_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVCB97_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVCB97_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVCB97_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVCB97_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVCB97_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVCB97_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVCB97_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVCB97_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVCB97_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVCB97_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVCB97_DRAW_ZERO_INDEX 0x0304 +#define NVCB97_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVCB97_SET_L1_CONFIGURATION 0x0308 +#define NVCB97_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVCB97_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVCB97_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVCB97_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVCB97_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVCB97_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVCB97_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVCB97_SET_SPA_VERSION 0x0310 +#define NVCB97_SET_SPA_VERSION_MINOR 7:0 +#define NVCB97_SET_SPA_VERSION_MAJOR 15:8 + +#define NVCB97_SET_TIMESLICE_BATCH_LIMIT 0x0314 +#define NVCB97_SET_TIMESLICE_BATCH_LIMIT_BATCH_LIMIT 15:0 + +#define NVCB97_SET_SNAP_GRID_LINE 0x0318 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVCB97_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVCB97_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVCB97_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVCB97_SET_SNAP_GRID_NON_LINE 0x031c +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVCB97_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVCB97_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVCB97_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVCB97_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVCB97_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVCB97_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVCB97_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVCB97_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVCB97_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVCB97_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVCB97_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVCB97_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVCB97_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVCB97_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVCB97_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVCB97_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVCB97_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVCB97_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVCB97_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVCB97_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVCB97_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVCB97_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVCB97_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVCB97_SET_TESSELLATION_LOD_V1 0x0330 +#define NVCB97_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVCB97_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVCB97_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVCB97_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVCB97_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVCB97_RESERVED_TG07 0x033c +#define NVCB97_RESERVED_TG07_V 0:0 + +#define NVCB97_RESERVED_TG08 0x0340 +#define NVCB97_RESERVED_TG08_V 0:0 + +#define NVCB97_RESERVED_TG09 0x0344 +#define NVCB97_RESERVED_TG09_V 0:0 + +#define NVCB97_RESERVED_TG10 0x0348 +#define NVCB97_RESERVED_TG10_V 0:0 + +#define NVCB97_RESERVED_TG11 0x034c +#define NVCB97_RESERVED_TG11_V 0:0 + +#define NVCB97_RESERVED_TG12 0x0350 +#define NVCB97_RESERVED_TG12_V 0:0 + +#define NVCB97_RESERVED_TG13 0x0354 +#define NVCB97_RESERVED_TG13_V 0:0 + +#define NVCB97_RESERVED_TG14 0x0358 +#define NVCB97_RESERVED_TG14_V 0:0 + +#define NVCB97_RESERVED_TG15 0x035c +#define NVCB97_RESERVED_TG15_V 0:0 + +#define NVCB97_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVCB97_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVCB97_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVCB97_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVCB97_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVCB97_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVCB97_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVCB97_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVCB97_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVCB97_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVCB97_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVCB97_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVCB97_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVCB97_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVCB97_SET_RASTER_ENABLE 0x037c +#define NVCB97_SET_RASTER_ENABLE_V 0:0 +#define NVCB97_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVCB97_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVCB97_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVCB97_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVCB97_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVCB97_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVCB97_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVCB97_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVCB97_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVCB97_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVCB97_SET_Z_ROP_SLICE_MAP 0x0500 +#define NVCB97_SET_Z_ROP_SLICE_MAP_VIRTUAL_ADDRESS_MASK 31:0 + +#define NVCB97_SET_ROOT_TABLE_SELECTOR 0x0504 +#define NVCB97_SET_ROOT_TABLE_SELECTOR_ROOT_TABLE 2:0 +#define NVCB97_SET_ROOT_TABLE_SELECTOR_OFFSET 15:8 + +#define NVCB97_LOAD_ROOT_TABLE 0x0508 +#define NVCB97_LOAD_ROOT_TABLE_V 31:0 + +#define NVCB97_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVCB97_SET_MME_MEM_ADDRESS_A_UPPER 24:0 + +#define NVCB97_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVCB97_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVCB97_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVCB97_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVCB97_MME_DMA_READ 0x055c +#define NVCB97_MME_DMA_READ_LENGTH 31:0 + +#define NVCB97_MME_DMA_READ_FIFOED 0x0560 +#define NVCB97_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVCB97_MME_DMA_WRITE 0x0564 +#define NVCB97_MME_DMA_WRITE_LENGTH 31:0 + +#define NVCB97_MME_DMA_REDUCTION 0x0568 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVCB97_MME_DMA_SYSMEMBAR 0x056c +#define NVCB97_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVCB97_MME_DMA_SYNC 0x0570 +#define NVCB97_MME_DMA_SYNC_VALUE 31:0 + +#define NVCB97_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NVCB97_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NVCB97_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NVCB97_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NVCB97_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NVCB97_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NVCB97_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NVCB97_SET_VERTEX_STREAM_SIZE_A(j) (0x0600+(j)*8) +#define NVCB97_SET_VERTEX_STREAM_SIZE_A_UPPER 7:0 + +#define NVCB97_SET_VERTEX_STREAM_SIZE_B(j) (0x0604+(j)*8) +#define NVCB97_SET_VERTEX_STREAM_SIZE_B_LOWER 31:0 + +#define NVCB97_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVCB97_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVCB97_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVCB97_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVCB97_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVCB97_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVCB97_SET_RASTER_INPUT 0x0740 +#define NVCB97_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVCB97_SET_STREAM_OUTPUT 0x0744 +#define NVCB97_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVCB97_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVCB97_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVCB97_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVCB97_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVCB97_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVCB97_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVCB97_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVCB97_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVCB97_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVCB97_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVCB97_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVCB97_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 6:0 + +#define NVCB97_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVCB97_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVCB97_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVCB97_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVCB97_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVCB97_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVCB97_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVCB97_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVCB97_SET_TEXTURE_HEADER_VERSION 0x07ac +#define NVCB97_SET_TEXTURE_HEADER_VERSION_MAJOR 7:0 + +#define NVCB97_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVCB97_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVCB97_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVCB97_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVCB97_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVCB97_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVCB97_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVCB97_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVCB97_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVCB97_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVCB97_SET_CULL_BEFORE_FETCH 0x07dc +#define NVCB97_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVCB97_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVCB97_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVCB97_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVCB97_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVCB97_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVCB97_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVCB97_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVCB97_SET_ZCULL_STORAGE_A 0x07e8 +#define NVCB97_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_ZCULL_STORAGE_B 0x07ec +#define NVCB97_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_ZCULL_STORAGE_C 0x07f0 +#define NVCB97_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_ZCULL_STORAGE_D 0x07f4 +#define NVCB97_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_ZT_READ_ONLY 0x07f8 +#define NVCB97_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVCB97_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVCB97_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVCB97_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVCB97_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVCB97_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVCB97_THROTTLE_SM 0x07fc +#define NVCB97_THROTTLE_SM_MULTIPLY_ADD 0:0 +#define NVCB97_THROTTLE_SM_MULTIPLY_ADD_FALSE 0x00000000 +#define NVCB97_THROTTLE_SM_MULTIPLY_ADD_TRUE 0x00000001 + +#define NVCB97_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVCB97_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVCB97_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVCB97_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVCB97_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVCB97_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVCB97_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVCB97_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVCB97_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVCB97_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVCB97_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVCB97_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVCB97_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVCB97_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVCB97_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVCB97_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVCB97_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVCB97_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVCB97_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVCB97_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVCB97_SET_COLOR_TARGET_C_ROP_SLICE_MAP(j) (0x0824+(j)*64) +#define NVCB97_SET_COLOR_TARGET_C_ROP_SLICE_MAP_VIRTUAL_ADDRESS_MASK 31:0 + +#define NVCB97_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVCB97_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVCB97_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVCB97_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVCB97_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVCB97_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVCB97_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVCB97_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVCB97_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVCB97_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVCB97_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVCB97_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVCB97_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVCB97_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVCB97_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVCB97_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVCB97_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVCB97_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVCB97_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVCB97_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVCB97_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVCB97_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVCB97_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVCB97_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVCB97_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVCB97_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVCB97_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVCB97_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVCB97_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVCB97_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVCB97_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVCB97_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVCB97_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVCB97_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVCB97_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVCB97_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVCB97_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVCB97_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVCB97_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVCB97_SET_STATISTICS_COUNTER 0x0d68 +#define NVCB97_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVCB97_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVCB97_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVCB97_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVCB97_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVCB97_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVCB97_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVCB97_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVCB97_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVCB97_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVCB97_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVCB97_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVCB97_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVCB97_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVCB97_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVCB97_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVCB97_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVCB97_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVCB97_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVCB97_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVCB97_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVCB97_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVCB97_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVCB97_SET_VERTEX_ARRAY_START 0x0d74 +#define NVCB97_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVCB97_DRAW_VERTEX_ARRAY 0x0d78 +#define NVCB97_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVCB97_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVCB97_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVCB97_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVCB97_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVCB97_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVCB97_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVCB97_SET_Z_CLEAR_VALUE 0x0d90 +#define NVCB97_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVCB97_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVCB97_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVCB97_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVCB97_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVCB97_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVCB97_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVCB97_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVCB97_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVCB97_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVCB97_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVCB97_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVCB97_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVCB97_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVCB97_SET_FRONT_POLYGON_MODE 0x0dac +#define NVCB97_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVCB97_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVCB97_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVCB97_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVCB97_SET_BACK_POLYGON_MODE 0x0db0 +#define NVCB97_SET_BACK_POLYGON_MODE_V 31:0 +#define NVCB97_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVCB97_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVCB97_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVCB97_SET_POLY_SMOOTH 0x0db4 +#define NVCB97_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVCB97_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVCB97_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVCB97_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVCB97_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVCB97_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVCB97_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVCB97_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVCB97_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_PATCH 0x0dcc +#define NVCB97_SET_PATCH_SIZE 7:0 + +#define NVCB97_SET_ITERATED_BLEND 0x0dd0 +#define NVCB97_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVCB97_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVCB97_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVCB97_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVCB97_SET_ZCULL_CRITERION 0x0dd8 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVCB97_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVCB97_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVCB97_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_CRITERION_SREF 23:16 +#define NVCB97_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVCB97_PIXEL_SHADER_BARRIER 0x0de0 +#define NVCB97_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVCB97_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVCB97_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 +#define NVCB97_PIXEL_SHADER_BARRIER_BARRIER_LOCATION 1:1 +#define NVCB97_PIXEL_SHADER_BARRIER_BARRIER_LOCATION_BLOCK_BEFORE_PS 0x00000000 +#define NVCB97_PIXEL_SHADER_BARRIER_BARRIER_LOCATION_BLOCK_BEFORE_PS_AND_ZTEST 0x00000001 + +#define NVCB97_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVCB97_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVCB97_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVCB97_MME_DMA_WRITE_METHOD_BARRIER 0x0dec +#define NVCB97_MME_DMA_WRITE_METHOD_BARRIER_V 0:0 + +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVCB97_SET_WINDOW_OFFSET_X 0x0df8 +#define NVCB97_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVCB97_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVCB97_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVCB97_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVCB97_SET_SCISSOR_ENABLE_V 0:0 +#define NVCB97_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVCB97_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVCB97_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVCB97_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVCB97_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVCB97_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVCB97_SET_VPC_PERF_KNOB 0x0f14 +#define NVCB97_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVCB97_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVCB97_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVCB97_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVCB97_PM_LOCAL_TRIGGER 0x0f18 +#define NVCB97_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVCB97_SET_POST_Z_PS_IMASK 0x0f1c +#define NVCB97_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVCB97_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVCB97_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVCB97_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVCB97_SET_BACK_STENCIL_MASK 0x0f58 +#define NVCB97_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVCB97_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVCB97_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVCB97_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVCB97_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVCB97_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVCB97_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVCB97_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVCB97_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVCB97_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVCB97_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVCB97_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVCB97_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVCB97_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVCB97_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVCB97_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVCB97_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVCB97_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVCB97_SET_SAMPLE_MASK 0x0fa4 +#define NVCB97_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVCB97_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVCB97_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVCB97_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVCB97_SET_CT_MRT_ENABLE 0x0fac +#define NVCB97_SET_CT_MRT_ENABLE_V 0:0 +#define NVCB97_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVCB97_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVCB97_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVCB97_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVCB97_SET_TIR 0x0fb4 +#define NVCB97_SET_TIR_MODE 1:0 +#define NVCB97_SET_TIR_MODE_DISABLED 0x00000000 +#define NVCB97_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVCB97_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVCB97_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVCB97_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVCB97_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVCB97_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVCB97_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVCB97_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVCB97_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVCB97_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVCB97_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVCB97_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVCB97_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVCB97_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVCB97_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVCB97_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVCB97_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVCB97_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVCB97_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_TIR_MODULATION 0x0fd4 +#define NVCB97_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVCB97_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVCB97_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVCB97_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVCB97_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVCB97_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVCB97_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVCB97_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVCB97_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVCB97_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVCB97_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVCB97_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVCB97_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVCB97_SET_ZT_A 0x0fe0 +#define NVCB97_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_ZT_B 0x0fe4 +#define NVCB97_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_ZT_FORMAT 0x0fe8 +#define NVCB97_SET_ZT_FORMAT_V 4:0 +#define NVCB97_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVCB97_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVCB97_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVCB97_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVCB97_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVCB97_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVCB97_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 + +#define NVCB97_SET_ZT_BLOCK_SIZE 0x0fec +#define NVCB97_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVCB97_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVCB97_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVCB97_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVCB97_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVCB97_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVCB97_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVCB97_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVCB97_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVCB97_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVCB97_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVCB97_SET_VIEWPORT_MULTICAST 0x1004 +#define NVCB97_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVCB97_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVCB97_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVCB97_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVCB97_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVCB97_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVCB97_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVCB97_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVCB97_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVCB97_SET_RESERVED_SW_METHOD00 0x1014 +#define NVCB97_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVCB97_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVCB97_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVCB97_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVCB97_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVCB97_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVCB97_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVCB97_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVCB97_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVCB97_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_RESERVED_SW_METHOD01 0x1028 +#define NVCB97_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD02 0x102c +#define NVCB97_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVCB97_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVCB97_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVCB97_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVCB97_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVCB97_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVCB97_SET_SPARE_NOOP01 0x1044 +#define NVCB97_SET_SPARE_NOOP01_V 31:0 + +#define NVCB97_SET_SPARE_NOOP02 0x1048 +#define NVCB97_SET_SPARE_NOOP02_V 31:0 + +#define NVCB97_SET_SPARE_NOOP03 0x104c +#define NVCB97_SET_SPARE_NOOP03_V 31:0 + +#define NVCB97_SET_SPARE_NOOP04 0x1050 +#define NVCB97_SET_SPARE_NOOP04_V 31:0 + +#define NVCB97_SET_SPARE_NOOP05 0x1054 +#define NVCB97_SET_SPARE_NOOP05_V 31:0 + +#define NVCB97_SET_SPARE_NOOP06 0x1058 +#define NVCB97_SET_SPARE_NOOP06_V 31:0 + +#define NVCB97_SET_SPARE_NOOP07 0x105c +#define NVCB97_SET_SPARE_NOOP07_V 31:0 + +#define NVCB97_SET_SPARE_NOOP08 0x1060 +#define NVCB97_SET_SPARE_NOOP08_V 31:0 + +#define NVCB97_SET_SPARE_NOOP09 0x1064 +#define NVCB97_SET_SPARE_NOOP09_V 31:0 + +#define NVCB97_SET_SPARE_NOOP10 0x1068 +#define NVCB97_SET_SPARE_NOOP10_V 31:0 + +#define NVCB97_SET_SPARE_NOOP11 0x106c +#define NVCB97_SET_SPARE_NOOP11_V 31:0 + +#define NVCB97_SET_SPARE_NOOP12 0x1070 +#define NVCB97_SET_SPARE_NOOP12_V 31:0 + +#define NVCB97_SET_SPARE_NOOP13 0x1074 +#define NVCB97_SET_SPARE_NOOP13_V 31:0 + +#define NVCB97_SET_SPARE_NOOP14 0x1078 +#define NVCB97_SET_SPARE_NOOP14_V 31:0 + +#define NVCB97_SET_SPARE_NOOP15 0x107c +#define NVCB97_SET_SPARE_NOOP15_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVCB97_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVCB97_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVCB97_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD06 0x10bc +#define NVCB97_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVCB97_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVCB97_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVCB97_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVCB97_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVCB97_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVCB97_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVCB97_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD13 0x10dc +#define NVCB97_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVCB97_UNBIND_ALL 0x10f4 +#define NVCB97_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVCB97_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVCB97_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVCB97_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVCB97_SET_RESERVED_SW_METHOD14 0x1100 +#define NVCB97_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD15 0x1104 +#define NVCB97_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVCB97_NO_OPERATION_DATA_HI 0x110c +#define NVCB97_NO_OPERATION_DATA_HI_V 31:0 + +#define NVCB97_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVCB97_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVCB97_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVCB97_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVCB97_PM_TRIGGER_END 0x1114 +#define NVCB97_PM_TRIGGER_END_V 31:0 + +#define NVCB97_SET_VERTEX_ID_BASE 0x1118 +#define NVCB97_SET_VERTEX_ID_BASE_V 31:0 + +#define NVCB97_SET_STENCIL_COMPRESSION 0x111c +#define NVCB97_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVCB97_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVCB97_SET_TIR_CONTROL 0x1130 +#define NVCB97_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVCB97_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVCB97_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVCB97_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVCB97_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVCB97_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVCB97_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVCB97_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVCB97_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 +#define NVCB97_SET_TIR_CONTROL_REDUCTION_MODE 2:2 +#define NVCB97_SET_TIR_CONTROL_REDUCTION_MODE_AFFINITY_MAP 0x00000000 +#define NVCB97_SET_TIR_CONTROL_REDUCTION_MODE_TRUNCATION 0x00000001 + +#define NVCB97_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVCB97_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVCB97_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVCB97_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVCB97_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVCB97_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVCB97_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVCB97_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVCB97_SET_FILL_VIA_TRIANGLE 0x113c +#define NVCB97_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVCB97_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVCB97_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVCB97_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVCB97_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVCB97_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVCB97_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVCB97_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVCB97_FLUSH_PENDING_WRITES 0x1144 +#define NVCB97_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVCB97_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVCB97_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVCB97_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVCB97_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVCB97_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVCB97_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVCB97_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVCB97_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVCB97_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVCB97_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVCB97_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVCB97_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVCB97_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVCB97_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVCB97_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVCB97_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVCB97_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVCB97_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_SCREEN_STATE_MASK 0x1204 +#define NVCB97_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVCB97_SET_ZT_SPARSE 0x1208 +#define NVCB97_SET_ZT_SPARSE_ENABLE 0:0 +#define NVCB97_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVCB97_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVCB97_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_SET_CT_SELECT 0x121c +#define NVCB97_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVCB97_SET_CT_SELECT_TARGET0 6:4 +#define NVCB97_SET_CT_SELECT_TARGET1 9:7 +#define NVCB97_SET_CT_SELECT_TARGET2 12:10 +#define NVCB97_SET_CT_SELECT_TARGET3 15:13 +#define NVCB97_SET_CT_SELECT_TARGET4 18:16 +#define NVCB97_SET_CT_SELECT_TARGET5 21:19 +#define NVCB97_SET_CT_SELECT_TARGET6 24:22 +#define NVCB97_SET_CT_SELECT_TARGET7 27:25 + +#define NVCB97_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVCB97_SET_ZT_SIZE_A 0x1228 +#define NVCB97_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVCB97_SET_ZT_SIZE_B 0x122c +#define NVCB97_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVCB97_SET_ZT_SIZE_C 0x1230 +#define NVCB97_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVCB97_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVCB97_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVCB97_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVCB97_SET_SAMPLER_BINDING 0x1234 +#define NVCB97_SET_SAMPLER_BINDING_V 0:0 +#define NVCB97_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVCB97_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVCB97_DRAW_AUTO 0x123c +#define NVCB97_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVCB97_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVCB97_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVCB97_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVCB97_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVCB97_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVCB97_SET_BACK_END_COPY_A 0x1264 +#define NVCB97_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVCB97_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVCB97_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVCB97_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BACK_END_COPY_B 0x1268 +#define NVCB97_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_BACK_END_COPY_C 0x126c +#define NVCB97_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_BACK_END_COPY_D 0x1270 +#define NVCB97_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_BACK_END_COPY_E 0x1274 +#define NVCB97_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVCB97_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVCB97_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVCB97_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVCB97_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVCB97_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVCB97_CLEAR_ZCULL_REGION 0x12c8 +#define NVCB97_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVCB97_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVCB97_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVCB97_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVCB97_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVCB97_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVCB97_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVCB97_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVCB97_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVCB97_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVCB97_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVCB97_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVCB97_SET_DEPTH_TEST 0x12cc +#define NVCB97_SET_DEPTH_TEST_ENABLE 0:0 +#define NVCB97_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_FILL_MODE 0x12d0 +#define NVCB97_SET_FILL_MODE_V 31:0 +#define NVCB97_SET_FILL_MODE_V_POINT 0x00000001 +#define NVCB97_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVCB97_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVCB97_SET_SHADE_MODE 0x12d4 +#define NVCB97_SET_SHADE_MODE_V 31:0 +#define NVCB97_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVCB97_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVCB97_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVCB97_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVCB97_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVCB97_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVCB97_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVCB97_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVCB97_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVCB97_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVCB97_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVCB97_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_DEPTH_WRITE 0x12e8 +#define NVCB97_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVCB97_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_ALPHA_TEST 0x12ec +#define NVCB97_SET_ALPHA_TEST_ENABLE 0:0 +#define NVCB97_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVCB97_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVCB97_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVCB97_DRAW_INLINE_INDEX4X8 0x1304 +#define NVCB97_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVCB97_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVCB97_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVCB97_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVCB97_D3D_SET_CULL_MODE 0x1308 +#define NVCB97_D3D_SET_CULL_MODE_V 31:0 +#define NVCB97_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVCB97_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVCB97_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVCB97_SET_DEPTH_FUNC 0x130c +#define NVCB97_SET_DEPTH_FUNC_V 31:0 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVCB97_SET_ALPHA_REF 0x1310 +#define NVCB97_SET_ALPHA_REF_V 31:0 + +#define NVCB97_SET_ALPHA_FUNC 0x1314 +#define NVCB97_SET_ALPHA_FUNC_V 31:0 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVCB97_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVCB97_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVCB97_SET_BLEND_CONST_RED 0x131c +#define NVCB97_SET_BLEND_CONST_RED_V 31:0 + +#define NVCB97_SET_BLEND_CONST_GREEN 0x1320 +#define NVCB97_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVCB97_SET_BLEND_CONST_BLUE 0x1324 +#define NVCB97_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVCB97_SET_BLEND_CONST_ALPHA 0x1328 +#define NVCB97_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVCB97_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVCB97_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVCB97_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVCB97_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BLEND_COLOR_OP 0x1340 +#define NVCB97_SET_BLEND_COLOR_OP_V 31:0 +#define NVCB97_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVCB97_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVCB97_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVCB97_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVCB97_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVCB97_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVCB97_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVCB97_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVCB97_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVCB97_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_BLEND_ALPHA_OP 0x134c +#define NVCB97_SET_BLEND_ALPHA_OP_V 31:0 +#define NVCB97_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVCB97_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVCB97_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVCB97_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVCB97_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVCB97_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVCB97_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVCB97_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVCB97_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVCB97_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVCB97_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVCB97_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_SINGLE_ROP_CONTROL 0x135c +#define NVCB97_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVCB97_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BLEND(i) (0x1360+(i)*4) +#define NVCB97_SET_BLEND_ENABLE 0:0 +#define NVCB97_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_STENCIL_TEST 0x1380 +#define NVCB97_SET_STENCIL_TEST_ENABLE 0:0 +#define NVCB97_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_STENCIL_OP_FAIL 0x1384 +#define NVCB97_SET_STENCIL_OP_FAIL_V 31:0 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVCB97_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVCB97_SET_STENCIL_OP_ZPASS 0x138c +#define NVCB97_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVCB97_SET_STENCIL_FUNC 0x1390 +#define NVCB97_SET_STENCIL_FUNC_V 31:0 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVCB97_SET_STENCIL_FUNC_REF 0x1394 +#define NVCB97_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVCB97_SET_STENCIL_FUNC_MASK 0x1398 +#define NVCB97_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVCB97_SET_STENCIL_MASK 0x139c +#define NVCB97_SET_STENCIL_MASK_V 7:0 + +#define NVCB97_SET_DRAW_AUTO_START 0x13a4 +#define NVCB97_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVCB97_SET_PS_SATURATE 0x13a8 +#define NVCB97_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVCB97_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVCB97_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVCB97_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVCB97_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVCB97_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVCB97_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVCB97_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVCB97_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVCB97_SET_WINDOW_ORIGIN 0x13ac +#define NVCB97_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVCB97_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVCB97_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVCB97_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVCB97_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVCB97_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVCB97_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVCB97_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVCB97_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVCB97_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVCB97_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVCB97_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVCB97_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVCB97_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVCB97_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVCB97_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVCB97_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVCB97_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVCB97_SET_PS_WARP_WATERMARKS 0x1450 +#define NVCB97_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVCB97_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVCB97_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVCB97_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVCB97_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVCB97_STORE_ZCULL 0x1464 +#define NVCB97_STORE_ZCULL_V 0:0 + +#define NVCB97_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVCB97_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVCB97_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVCB97_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVCB97_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVCB97_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVCB97_LOAD_ZCULL 0x1500 +#define NVCB97_LOAD_ZCULL_V 0:0 + +#define NVCB97_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVCB97_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVCB97_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVCB97_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVCB97_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVCB97_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVCB97_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVCB97_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVCB97_SET_USER_CLIP_ENABLE 0x1510 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVCB97_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVCB97_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVCB97_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_POINT_SIZE 0x1518 +#define NVCB97_SET_POINT_SIZE_V 31:0 + +#define NVCB97_SET_ZCULL_STATS 0x151c +#define NVCB97_SET_ZCULL_STATS_ENABLE 0:0 +#define NVCB97_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_POINT_SPRITE 0x1520 +#define NVCB97_SET_POINT_SPRITE_ENABLE 0:0 +#define NVCB97_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_SHADER_EXCEPTIONS 0x1528 +#define NVCB97_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVCB97_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVCB97_CLEAR_REPORT_VALUE 0x1530 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVCB97_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVCB97_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVCB97_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_ZT_SELECT 0x1538 +#define NVCB97_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVCB97_SET_RENDER_ENABLE_A 0x1550 +#define NVCB97_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_RENDER_ENABLE_B 0x1554 +#define NVCB97_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_RENDER_ENABLE_C 0x1558 +#define NVCB97_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVCB97_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVCB97_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVCB97_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVCB97_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVCB97_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVCB97_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVCB97_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVCB97_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVCB97_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVCB97_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVCB97_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVCB97_SET_ANTI_ALIASED_LINE 0x1570 +#define NVCB97_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVCB97_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_TEX_HEADER_POOL_A 0x1574 +#define NVCB97_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_TEX_HEADER_POOL_B 0x1578 +#define NVCB97_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_TEX_HEADER_POOL_C 0x157c +#define NVCB97_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVCB97_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVCB97_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVCB97_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVCB97_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVCB97_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVCB97_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVCB97_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVCB97_SET_SRGB_WRITE 0x15b8 +#define NVCB97_SET_SRGB_WRITE_ENABLE 0:0 +#define NVCB97_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_DEPTH_BIAS 0x15bc +#define NVCB97_SET_DEPTH_BIAS_V 31:0 + +#define NVCB97_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVCB97_SET_RT_LAYER 0x15cc +#define NVCB97_SET_RT_LAYER_V 15:0 +#define NVCB97_SET_RT_LAYER_CONTROL 16:16 +#define NVCB97_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVCB97_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVCB97_SET_ANTI_ALIAS 0x15d0 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVCB97_SET_EDGE_FLAG 0x15e4 +#define NVCB97_SET_EDGE_FLAG_V 0:0 +#define NVCB97_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVCB97_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVCB97_DRAW_INLINE_INDEX 0x15e8 +#define NVCB97_DRAW_INLINE_INDEX_V 31:0 + +#define NVCB97_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVCB97_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVCB97_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVCB97_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVCB97_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVCB97_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVCB97_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVCB97_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVCB97_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVCB97_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVCB97_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVCB97_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVCB97_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVCB97_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVCB97_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVCB97_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVCB97_SET_POINT_SPRITE_SELECT 0x1604 +#define NVCB97_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVCB97_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVCB97_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVCB97_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVCB97_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVCB97_END 0x1614 +#define NVCB97_END_V 0:0 + +#define NVCB97_BEGIN 0x1618 +#define NVCB97_BEGIN_OP 15:0 +#define NVCB97_BEGIN_OP_POINTS 0x00000000 +#define NVCB97_BEGIN_OP_LINES 0x00000001 +#define NVCB97_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVCB97_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVCB97_BEGIN_OP_TRIANGLES 0x00000004 +#define NVCB97_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVCB97_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVCB97_BEGIN_OP_QUADS 0x00000007 +#define NVCB97_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVCB97_BEGIN_OP_POLYGON 0x00000009 +#define NVCB97_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVCB97_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_BEGIN_OP_PATCH 0x0000000E +#define NVCB97_BEGIN_PRIMITIVE_ID 24:24 +#define NVCB97_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVCB97_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVCB97_BEGIN_INSTANCE_ID 27:26 +#define NVCB97_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVCB97_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVCB97_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVCB97_BEGIN_SPLIT_MODE 30:29 +#define NVCB97_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVCB97_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVCB97_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVCB97_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVCB97_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVCB97_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVCB97_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_VERTEX_ID_COPY 0x161c +#define NVCB97_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVCB97_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVCB97_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVCB97_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVCB97_LOAD_PRIMITIVE_ID 0x1624 +#define NVCB97_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVCB97_SET_SHADER_BASED_CULL 0x162c +#define NVCB97_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVCB97_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVCB97_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_CLASS_VERSION 0x1638 +#define NVCB97_SET_CLASS_VERSION_CURRENT 15:0 +#define NVCB97_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCB97_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVCB97_SET_DA_OUTPUT 0x164c +#define NVCB97_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVCB97_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVCB97_SET_ANTI_ALIASED_POINT 0x1658 +#define NVCB97_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVCB97_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_POINT_CENTER_MODE 0x165c +#define NVCB97_SET_POINT_CENTER_MODE_V 31:0 +#define NVCB97_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVCB97_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVCB97_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVCB97_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVCB97_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVCB97_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVCB97_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVCB97_SET_LINE_STIPPLE 0x166c +#define NVCB97_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVCB97_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVCB97_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVCB97_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVCB97_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVCB97_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVCB97_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVCB97_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVCB97_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVCB97_SET_PROVOKING_VERTEX 0x1684 +#define NVCB97_SET_PROVOKING_VERTEX_V 0:0 +#define NVCB97_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVCB97_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVCB97_SET_TWO_SIDED_LIGHT 0x1688 +#define NVCB97_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVCB97_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_POLYGON_STIPPLE 0x168c +#define NVCB97_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVCB97_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_SHADER_CONTROL 0x1690 +#define NVCB97_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVCB97_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVCB97_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVCB97_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVCB97_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVCB97_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVCB97_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVCB97_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVCB97_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVCB97_CHECK_CLASS_VERSION 0x16a0 +#define NVCB97_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVCB97_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCB97_SET_SPH_VERSION 0x16a4 +#define NVCB97_SET_SPH_VERSION_CURRENT 15:0 +#define NVCB97_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCB97_CHECK_SPH_VERSION 0x16a8 +#define NVCB97_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVCB97_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVCB97_SET_SCG_GRAPHICS_PRIORITY 0x16bc +#define NVCB97_SET_SCG_GRAPHICS_PRIORITY_PRIORITY 5:0 + +#define NVCB97_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS(i) (0x16c0+(i)*4) +#define NVCB97_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS_V 31:0 + +#define NVCB97_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVCB97_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVCB97_SET_AAM_VERSION 0x1790 +#define NVCB97_SET_AAM_VERSION_CURRENT 15:0 +#define NVCB97_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCB97_CHECK_AAM_VERSION 0x1794 +#define NVCB97_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVCB97_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCB97_SET_ZT_LAYER 0x179c +#define NVCB97_SET_ZT_LAYER_OFFSET 15:0 + +#define NVCB97_SET_INDEX_BUFFER_A 0x17c8 +#define NVCB97_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_INDEX_BUFFER_B 0x17cc +#define NVCB97_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_INDEX_BUFFER_E 0x17d8 +#define NVCB97_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVCB97_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVCB97_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVCB97_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVCB97_SET_INDEX_BUFFER_F 0x17dc +#define NVCB97_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVCB97_DRAW_INDEX_BUFFER 0x17e0 +#define NVCB97_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVCB97_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVCB97_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVCB97_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVCB97_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVCB97_OGL_SET_CULL 0x1918 +#define NVCB97_OGL_SET_CULL_ENABLE 0:0 +#define NVCB97_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVCB97_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVCB97_OGL_SET_FRONT_FACE 0x191c +#define NVCB97_OGL_SET_FRONT_FACE_V 31:0 +#define NVCB97_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVCB97_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVCB97_OGL_SET_CULL_FACE 0x1920 +#define NVCB97_OGL_SET_CULL_FACE_V 31:0 +#define NVCB97_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVCB97_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVCB97_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVCB97_SET_VIEWPORT_PIXEL 0x1924 +#define NVCB97_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVCB97_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVCB97_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVCB97_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVCB97_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVCB97_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE 17:16 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_USE_FIELD_MIN_Z_ZERO_MAX_Z_ONE 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MIN_Z_MAX_Z 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_ZERO_ONE 0x00000002 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MINUS_INF_PLUS_INF 0x00000003 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVCB97_SET_USER_CLIP_OP 0x1940 +#define NVCB97_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVCB97_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVCB97_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVCB97_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVCB97_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVCB97_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVCB97_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVCB97_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVCB97_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVCB97_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVCB97_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVCB97_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVCB97_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVCB97_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVCB97_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVCB97_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVCB97_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVCB97_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVCB97_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVCB97_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVCB97_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVCB97_INVALIDATE_ZCULL 0x1958 +#define NVCB97_INVALIDATE_ZCULL_V 31:0 +#define NVCB97_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVCB97_SET_ZCULL 0x1968 +#define NVCB97_SET_ZCULL_Z_ENABLE 0:0 +#define NVCB97_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVCB97_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_ZCULL_BOUNDS 0x196c +#define NVCB97_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVCB97_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVCB97_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVCB97_ZCULL_SYNC 0x1978 +#define NVCB97_ZCULL_SYNC_V 31:0 + +#define NVCB97_SET_CLIP_ID_TEST 0x197c +#define NVCB97_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVCB97_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVCB97_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVCB97_SET_CLIP_ID 0x1984 +#define NVCB97_SET_CLIP_ID_V 31:0 + +#define NVCB97_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVCB97_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVCB97_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVCB97_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVCB97_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVCB97_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVCB97_SET_LOGIC_OP 0x19c4 +#define NVCB97_SET_LOGIC_OP_ENABLE 0:0 +#define NVCB97_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_LOGIC_OP_FUNC 0x19c8 +#define NVCB97_SET_LOGIC_OP_FUNC_V 31:0 +#define NVCB97_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVCB97_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVCB97_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVCB97_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVCB97_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVCB97_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVCB97_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVCB97_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVCB97_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVCB97_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVCB97_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVCB97_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVCB97_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVCB97_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVCB97_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVCB97_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVCB97_SET_Z_COMPRESSION 0x19cc +#define NVCB97_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVCB97_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVCB97_CLEAR_SURFACE 0x19d0 +#define NVCB97_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVCB97_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVCB97_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVCB97_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVCB97_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVCB97_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVCB97_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVCB97_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVCB97_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVCB97_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVCB97_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVCB97_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVCB97_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVCB97_SET_CT_WRITE_R_ENABLE 0:0 +#define NVCB97_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_CT_WRITE_G_ENABLE 4:4 +#define NVCB97_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_CT_WRITE_B_ENABLE 8:8 +#define NVCB97_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_CT_WRITE_A_ENABLE 12:12 +#define NVCB97_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVCB97_PIPE_NOP 0x1a2c +#define NVCB97_PIPE_NOP_V 31:0 + +#define NVCB97_SET_SPARE00 0x1a30 +#define NVCB97_SET_SPARE00_V 31:0 + +#define NVCB97_SET_SPARE01 0x1a34 +#define NVCB97_SET_SPARE01_V 31:0 + +#define NVCB97_SET_SPARE02 0x1a38 +#define NVCB97_SET_SPARE02_V 31:0 + +#define NVCB97_SET_SPARE03 0x1a3c +#define NVCB97_SET_SPARE03_V 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVCB97_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 24:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVCB97_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVCB97_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVCB97_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVCB97_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVCB97_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVCB97_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVCB97_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVCB97_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVCB97_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVCB97_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVCB97_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_TIMESTAMP 0x00000014 +#define NVCB97_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVCB97_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVCB97_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVCB97_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVCB97_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVCB97_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVCB97_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVCB97_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVCB97_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVCB97_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVCB97_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVCB97_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVCB97_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVCB97_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVCB97_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVCB97_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVCB97_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVCB97_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVCB97_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVCB97_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVCB97_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVCB97_SET_PIPELINE_RESERVED_B(j) (0x2004+(j)*64) +#define NVCB97_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVCB97_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVCB97_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVCB97_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVCB97_SET_PIPELINE_REGISTER_COUNT_V 8:0 + +#define NVCB97_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVCB97_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVCB97_SET_PIPELINE_PROGRAM_ADDRESS_A(j) (0x2014+(j)*64) +#define NVCB97_SET_PIPELINE_PROGRAM_ADDRESS_A_UPPER 7:0 + +#define NVCB97_SET_PIPELINE_PROGRAM_ADDRESS_B(j) (0x2018+(j)*64) +#define NVCB97_SET_PIPELINE_PROGRAM_ADDRESS_B_LOWER 31:0 + +#define NVCB97_SET_PIPELINE_PROGRAM_PREFETCH(j) (0x201c+(j)*64) +#define NVCB97_SET_PIPELINE_PROGRAM_PREFETCH_SIZE_IN_BLOCKS 6:0 + +#define NVCB97_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVCB97_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVCB97_SET_FALCON00 0x2300 +#define NVCB97_SET_FALCON00_V 31:0 + +#define NVCB97_SET_FALCON01 0x2304 +#define NVCB97_SET_FALCON01_V 31:0 + +#define NVCB97_SET_FALCON02 0x2308 +#define NVCB97_SET_FALCON02_V 31:0 + +#define NVCB97_SET_FALCON03 0x230c +#define NVCB97_SET_FALCON03_V 31:0 + +#define NVCB97_SET_FALCON04 0x2310 +#define NVCB97_SET_FALCON04_V 31:0 + +#define NVCB97_SET_FALCON05 0x2314 +#define NVCB97_SET_FALCON05_V 31:0 + +#define NVCB97_SET_FALCON06 0x2318 +#define NVCB97_SET_FALCON06_V 31:0 + +#define NVCB97_SET_FALCON07 0x231c +#define NVCB97_SET_FALCON07_V 31:0 + +#define NVCB97_SET_FALCON08 0x2320 +#define NVCB97_SET_FALCON08_V 31:0 + +#define NVCB97_SET_FALCON09 0x2324 +#define NVCB97_SET_FALCON09_V 31:0 + +#define NVCB97_SET_FALCON10 0x2328 +#define NVCB97_SET_FALCON10_V 31:0 + +#define NVCB97_SET_FALCON11 0x232c +#define NVCB97_SET_FALCON11_V 31:0 + +#define NVCB97_SET_FALCON12 0x2330 +#define NVCB97_SET_FALCON12_V 31:0 + +#define NVCB97_SET_FALCON13 0x2334 +#define NVCB97_SET_FALCON13_V 31:0 + +#define NVCB97_SET_FALCON14 0x2338 +#define NVCB97_SET_FALCON14_V 31:0 + +#define NVCB97_SET_FALCON15 0x233c +#define NVCB97_SET_FALCON15_V 31:0 + +#define NVCB97_SET_FALCON16 0x2340 +#define NVCB97_SET_FALCON16_V 31:0 + +#define NVCB97_SET_FALCON17 0x2344 +#define NVCB97_SET_FALCON17_V 31:0 + +#define NVCB97_SET_FALCON18 0x2348 +#define NVCB97_SET_FALCON18_V 31:0 + +#define NVCB97_SET_FALCON19 0x234c +#define NVCB97_SET_FALCON19_V 31:0 + +#define NVCB97_SET_FALCON20 0x2350 +#define NVCB97_SET_FALCON20_V 31:0 + +#define NVCB97_SET_FALCON21 0x2354 +#define NVCB97_SET_FALCON21_V 31:0 + +#define NVCB97_SET_FALCON22 0x2358 +#define NVCB97_SET_FALCON22_V 31:0 + +#define NVCB97_SET_FALCON23 0x235c +#define NVCB97_SET_FALCON23_V 31:0 + +#define NVCB97_SET_FALCON24 0x2360 +#define NVCB97_SET_FALCON24_V 31:0 + +#define NVCB97_SET_FALCON25 0x2364 +#define NVCB97_SET_FALCON25_V 31:0 + +#define NVCB97_SET_FALCON26 0x2368 +#define NVCB97_SET_FALCON26_V 31:0 + +#define NVCB97_SET_FALCON27 0x236c +#define NVCB97_SET_FALCON27_V 31:0 + +#define NVCB97_SET_FALCON28 0x2370 +#define NVCB97_SET_FALCON28_V 31:0 + +#define NVCB97_SET_FALCON29 0x2374 +#define NVCB97_SET_FALCON29_V 31:0 + +#define NVCB97_SET_FALCON30 0x2378 +#define NVCB97_SET_FALCON30_V 31:0 + +#define NVCB97_SET_FALCON31 0x237c +#define NVCB97_SET_FALCON31_V 31:0 + +#define NVCB97_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVCB97_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVCB97_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVCB97_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVCB97_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVCB97_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVCB97_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVCB97_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVCB97_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVCB97_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVCB97_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVCB97_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVCB97_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVCB97_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVCB97_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVCB97_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVCB97_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVCB97_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVCB97_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVCB97_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVCB97_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVCB97_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVCB97_SET_TRAP_HANDLER_A 0x25f8 +#define NVCB97_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVCB97_SET_TRAP_HANDLER_B 0x25fc +#define NVCB97_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_COLOR_CLAMP 0x2600 +#define NVCB97_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVCB97_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVCB97_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVCB97_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVCB97_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVCB97_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVCB97_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVCB97_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVCB97_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVCB97_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVCB97_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVCB97_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVCB97_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVCB97_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVCB97_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVCB97_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVCB97_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVCB97_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVCB97_CALL_MME_MACRO_V 31:0 + +#define NVCB97_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVCB97_CALL_MME_DATA_V 31:0 + +#endif /* _cl_hopper_a_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clcb97tex.h b/userspace/sdks/nv570/nvidia/inc/class/clcb97tex.h new file mode 100644 index 0000000..f9871b7 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clcb97tex.h @@ -0,0 +1,2437 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLCB97TEX_H__ +#define __CLCB97TEX_H__ + +/* +** Texture Header State Blocklinear + */ + +#define NVCB97_TEXHEAD_BL_COMPONENTS MW(6:0) +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE MW(9:7) +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE MW(12:10) +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE MW(15:13) +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE MW(18:16) +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_X_SOURCE MW(21:19) +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_Y_SOURCE MW(24:22) +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_Z_SOURCE MW(27:25) +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_W_SOURCE MW(30:28) +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_PACK_COMPONENTS MW(31:31) +#define NVCB97_TEXHEAD_BL_RESERVED1Y MW(36:32) +#define NVCB97_TEXHEAD_BL_GOB_DEPTH_OFFSET MW(38:37) +#define NVCB97_TEXHEAD_BL_RESERVED1X MW(40:39) +#define NVCB97_TEXHEAD_BL_ADDRESS_BITS31TO9 MW(63:41) +#define NVCB97_TEXHEAD_BL_ADDRESS_BITS48TO32 MW(80:64) +#define NVCB97_TEXHEAD_BL_RESERVED_ADDRESS MW(84:81) +#define NVCB97_TEXHEAD_BL_HEADER_VERSION MW(87:85) +#define NVCB97_TEXHEAD_BL_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVCB97_TEXHEAD_BL_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVCB97_TEXHEAD_BL_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVCB97_TEXHEAD_BL_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVCB97_TEXHEAD_BL_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVCB97_TEXHEAD_BL_RESERVED_HEADER_VERSION MW(88:88) +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVCB97_TEXHEAD_BL_RESERVED2A MW(95:93) +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_WIDTH MW(98:96) +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT MW(101:99) +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH MW(104:102) +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_BL_RESERVED3Y MW(105:105) +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS MW(108:106) +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_BL_GOB3D MW(109:109) +#define NVCB97_TEXHEAD_BL_RESERVED3Z MW(111:110) +#define NVCB97_TEXHEAD_BL_LOD_ANISO_QUALITY2 MW(112:112) +#define NVCB97_TEXHEAD_BL_LOD_ANISO_QUALITY MW(113:113) +#define NVCB97_TEXHEAD_BL_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_BL_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_BL_LOD_ISO_QUALITY MW(114:114) +#define NVCB97_TEXHEAD_BL_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_BL_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_BL_ANISO_SPREAD_SCALE MW(121:117) +#define NVCB97_TEXHEAD_BL_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVCB97_TEXHEAD_BL_DEPTH_TEXTURE MW(123:123) +#define NVCB97_TEXHEAD_BL_MAX_MIP_LEVEL MW(127:124) +#define NVCB97_TEXHEAD_BL_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_BL_DEPTH_MINUS_ONE_BIT14 MW(145:145) +#define NVCB97_TEXHEAD_BL_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVCB97_TEXHEAD_BL_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVCB97_TEXHEAD_BL_S_R_G_B_CONVERSION MW(150:150) +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE MW(154:151) +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_BL_SECTOR_PROMOTION MW(156:155) +#define NVCB97_TEXHEAD_BL_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_BL_BORDER_SIZE MW(159:157) +#define NVCB97_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVCB97_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVCB97_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVCB97_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVCB97_TEXHEAD_BL_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVCB97_TEXHEAD_BL_HEIGHT_MINUS_ONE MW(175:160) +#define NVCB97_TEXHEAD_BL_DEPTH_MINUS_ONE MW(189:176) +#define NVCB97_TEXHEAD_BL_RESERVED5A MW(190:190) +#define NVCB97_TEXHEAD_BL_NORMALIZED_COORDS MW(191:191) +#define NVCB97_TEXHEAD_BL_RESERVED6Y MW(192:192) +#define NVCB97_TEXHEAD_BL_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_BL_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_BL_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_BL_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVCB97_TEXHEAD_BL_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT MW(235:232) +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVCB97_TEXHEAD_BL_MIN_LOD_CLAMP MW(247:236) +#define NVCB97_TEXHEAD_BL_RESERVED7Y MW(255:248) + + +/* +** Texture Header State Blocklinear Color Key + */ + +#define NVCB97_TEXHEAD_BLCK_COMPONENTS MW(6:0) +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE MW(9:7) +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE MW(12:10) +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE MW(15:13) +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE MW(18:16) +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE MW(21:19) +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE MW(24:22) +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE MW(27:25) +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE MW(30:28) +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_PACK_COMPONENTS MW(31:31) +#define NVCB97_TEXHEAD_BLCK_RESERVED1Y MW(36:32) +#define NVCB97_TEXHEAD_BLCK_GOB_DEPTH_OFFSET MW(38:37) +#define NVCB97_TEXHEAD_BLCK_RESERVED1X MW(40:39) +#define NVCB97_TEXHEAD_BLCK_ADDRESS_BITS31TO9 MW(63:41) +#define NVCB97_TEXHEAD_BLCK_ADDRESS_BITS48TO32 MW(80:64) +#define NVCB97_TEXHEAD_BLCK_RESERVED_ADDRESS MW(84:81) +#define NVCB97_TEXHEAD_BLCK_HEADER_VERSION MW(87:85) +#define NVCB97_TEXHEAD_BLCK_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVCB97_TEXHEAD_BLCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVCB97_TEXHEAD_BLCK_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVCB97_TEXHEAD_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVCB97_TEXHEAD_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVCB97_TEXHEAD_BLCK_RESERVED_HEADER_VERSION MW(88:88) +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVCB97_TEXHEAD_BLCK_RESERVED2A MW(95:93) +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_WIDTH MW(98:96) +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT MW(101:99) +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH MW(104:102) +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_BLCK_RESERVED3Y MW(105:105) +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS MW(108:106) +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_BLCK_GOB3D MW(109:109) +#define NVCB97_TEXHEAD_BLCK_RESERVED3Z MW(111:110) +#define NVCB97_TEXHEAD_BLCK_LOD_ANISO_QUALITY2 MW(112:112) +#define NVCB97_TEXHEAD_BLCK_LOD_ANISO_QUALITY MW(113:113) +#define NVCB97_TEXHEAD_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_BLCK_LOD_ISO_QUALITY MW(114:114) +#define NVCB97_TEXHEAD_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_ANISO_SPREAD_SCALE MW(121:117) +#define NVCB97_TEXHEAD_BLCK_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVCB97_TEXHEAD_BLCK_DEPTH_TEXTURE MW(123:123) +#define NVCB97_TEXHEAD_BLCK_MAX_MIP_LEVEL MW(127:124) +#define NVCB97_TEXHEAD_BLCK_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_BLCK_DEPTH_MINUS_ONE_BIT14 MW(145:145) +#define NVCB97_TEXHEAD_BLCK_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVCB97_TEXHEAD_BLCK_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVCB97_TEXHEAD_BLCK_S_R_G_B_CONVERSION MW(150:150) +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE MW(154:151) +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_BLCK_SECTOR_PROMOTION MW(156:155) +#define NVCB97_TEXHEAD_BLCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_BLCK_BORDER_SIZE MW(159:157) +#define NVCB97_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVCB97_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVCB97_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVCB97_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVCB97_TEXHEAD_BLCK_HEIGHT_MINUS_ONE MW(175:160) +#define NVCB97_TEXHEAD_BLCK_DEPTH_MINUS_ONE MW(189:176) +#define NVCB97_TEXHEAD_BLCK_RESERVED5A MW(190:190) +#define NVCB97_TEXHEAD_BLCK_NORMALIZED_COORDS MW(191:191) +#define NVCB97_TEXHEAD_BLCK_COLOR_KEY_OP MW(192:192) +#define NVCB97_TEXHEAD_BLCK_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_BLCK_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_BLCK_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Header State One-D Buffer + */ + +#define NVCB97_TEXHEAD_1D_COMPONENTS MW(6:0) +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE MW(9:7) +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE MW(12:10) +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE MW(15:13) +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE MW(18:16) +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_X_SOURCE MW(21:19) +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_Y_SOURCE MW(24:22) +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_Z_SOURCE MW(27:25) +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_W_SOURCE MW(30:28) +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_PACK_COMPONENTS MW(31:31) +#define NVCB97_TEXHEAD_1D_ADDRESS_BITS31TO0 MW(63:32) +#define NVCB97_TEXHEAD_1D_ADDRESS_BITS48TO32 MW(80:64) +#define NVCB97_TEXHEAD_1D_RESERVED_ADDRESS MW(84:81) +#define NVCB97_TEXHEAD_1D_HEADER_VERSION MW(87:85) +#define NVCB97_TEXHEAD_1D_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVCB97_TEXHEAD_1D_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVCB97_TEXHEAD_1D_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVCB97_TEXHEAD_1D_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVCB97_TEXHEAD_1D_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVCB97_TEXHEAD_1D_RESERVED_HEADER_VERSION MW(88:88) +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVCB97_TEXHEAD_1D_RESERVED2A MW(95:93) +#define NVCB97_TEXHEAD_1D_WIDTH_MINUS_ONE_BITS31TO16 MW(111:96) +#define NVCB97_TEXHEAD_1D_RESERVED3X MW(127:112) +#define NVCB97_TEXHEAD_1D_WIDTH_MINUS_ONE_BITS15TO0 MW(143:128) +#define NVCB97_TEXHEAD_1D_RESERVED4X MW(149:144) +#define NVCB97_TEXHEAD_1D_S_R_G_B_CONVERSION MW(150:150) +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE MW(154:151) +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_1D_SECTOR_PROMOTION MW(156:155) +#define NVCB97_TEXHEAD_1D_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_1D_RESERVED4Y MW(159:157) +#define NVCB97_TEXHEAD_1D_RESERVED5X MW(189:160) +#define NVCB97_TEXHEAD_1D_RESERVED5A MW(190:190) +#define NVCB97_TEXHEAD_1D_RESERVED5Y MW(191:191) +#define NVCB97_TEXHEAD_1D_RESERVED6X MW(223:192) +#define NVCB97_TEXHEAD_1D_RESERVED7X MW(255:224) + + +/* +** Texture Header State Pitch + */ + +#define NVCB97_TEXHEAD_PITCH_COMPONENTS MW(6:0) +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE MW(9:7) +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE MW(12:10) +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE MW(15:13) +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE MW(18:16) +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE MW(21:19) +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE MW(24:22) +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE MW(27:25) +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE MW(30:28) +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_PACK_COMPONENTS MW(31:31) +#define NVCB97_TEXHEAD_PITCH_RESERVED1A MW(36:32) +#define NVCB97_TEXHEAD_PITCH_ADDRESS_BITS31TO5 MW(63:37) +#define NVCB97_TEXHEAD_PITCH_ADDRESS_BITS48TO32 MW(80:64) +#define NVCB97_TEXHEAD_PITCH_RESERVED_ADDRESS MW(84:81) +#define NVCB97_TEXHEAD_PITCH_HEADER_VERSION MW(87:85) +#define NVCB97_TEXHEAD_PITCH_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVCB97_TEXHEAD_PITCH_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVCB97_TEXHEAD_PITCH_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVCB97_TEXHEAD_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVCB97_TEXHEAD_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVCB97_TEXHEAD_PITCH_RESERVED_HEADER_VERSION MW(88:88) +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVCB97_TEXHEAD_PITCH_RESERVED2A MW(95:93) +#define NVCB97_TEXHEAD_PITCH_PITCH_BITS20TO5 MW(111:96) +#define NVCB97_TEXHEAD_PITCH_LOD_ANISO_QUALITY2 MW(112:112) +#define NVCB97_TEXHEAD_PITCH_LOD_ANISO_QUALITY MW(113:113) +#define NVCB97_TEXHEAD_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_PITCH_LOD_ISO_QUALITY MW(114:114) +#define NVCB97_TEXHEAD_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_ANISO_SPREAD_SCALE MW(121:117) +#define NVCB97_TEXHEAD_PITCH_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVCB97_TEXHEAD_PITCH_DEPTH_TEXTURE MW(123:123) +#define NVCB97_TEXHEAD_PITCH_MAX_MIP_LEVEL MW(127:124) +#define NVCB97_TEXHEAD_PITCH_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_PITCH_PITCH_BIT21 MW(145:145) +#define NVCB97_TEXHEAD_PITCH_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVCB97_TEXHEAD_PITCH_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVCB97_TEXHEAD_PITCH_S_R_G_B_CONVERSION MW(150:150) +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE MW(154:151) +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_PITCH_SECTOR_PROMOTION MW(156:155) +#define NVCB97_TEXHEAD_PITCH_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_PITCH_BORDER_SIZE MW(159:157) +#define NVCB97_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVCB97_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVCB97_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVCB97_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVCB97_TEXHEAD_PITCH_HEIGHT_MINUS_ONE MW(175:160) +#define NVCB97_TEXHEAD_PITCH_DEPTH_MINUS_ONE MW(189:176) +#define NVCB97_TEXHEAD_PITCH_RESERVED5A MW(190:190) +#define NVCB97_TEXHEAD_PITCH_NORMALIZED_COORDS MW(191:191) +#define NVCB97_TEXHEAD_PITCH_RESERVED6Y MW(192:192) +#define NVCB97_TEXHEAD_PITCH_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_PITCH_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_PITCH_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVCB97_TEXHEAD_PITCH_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT MW(235:232) +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVCB97_TEXHEAD_PITCH_MIN_LOD_CLAMP MW(247:236) +#define NVCB97_TEXHEAD_PITCH_RESERVED7Y MW(255:248) + + +/* +** Texture Header State Pitch Color Key + */ + +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS MW(6:0) +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE MW(9:7) +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE MW(12:10) +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE MW(15:13) +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE MW(18:16) +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE MW(21:19) +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE MW(24:22) +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE MW(27:25) +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE MW(30:28) +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_PACK_COMPONENTS MW(31:31) +#define NVCB97_TEXHEAD_PITCHCK_RESERVED1A MW(36:32) +#define NVCB97_TEXHEAD_PITCHCK_ADDRESS_BITS31TO5 MW(63:37) +#define NVCB97_TEXHEAD_PITCHCK_ADDRESS_BITS48TO32 MW(80:64) +#define NVCB97_TEXHEAD_PITCHCK_RESERVED_ADDRESS MW(84:81) +#define NVCB97_TEXHEAD_PITCHCK_HEADER_VERSION MW(87:85) +#define NVCB97_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_RESERVED_HEADER_VERSION MW(88:88) +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVCB97_TEXHEAD_PITCHCK_RESERVED2A MW(95:93) +#define NVCB97_TEXHEAD_PITCHCK_PITCH_BITS20TO5 MW(111:96) +#define NVCB97_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY2 MW(112:112) +#define NVCB97_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY MW(113:113) +#define NVCB97_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_LOD_ISO_QUALITY MW(114:114) +#define NVCB97_TEXHEAD_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_SPREAD_SCALE MW(121:117) +#define NVCB97_TEXHEAD_PITCHCK_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVCB97_TEXHEAD_PITCHCK_DEPTH_TEXTURE MW(123:123) +#define NVCB97_TEXHEAD_PITCHCK_MAX_MIP_LEVEL MW(127:124) +#define NVCB97_TEXHEAD_PITCHCK_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_PITCHCK_PITCH_BIT21 MW(145:145) +#define NVCB97_TEXHEAD_PITCHCK_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVCB97_TEXHEAD_PITCHCK_S_R_G_B_CONVERSION MW(150:150) +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE MW(154:151) +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_PITCHCK_SECTOR_PROMOTION MW(156:155) +#define NVCB97_TEXHEAD_PITCHCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_BORDER_SIZE MW(159:157) +#define NVCB97_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_HEIGHT_MINUS_ONE MW(175:160) +#define NVCB97_TEXHEAD_PITCHCK_DEPTH_MINUS_ONE MW(189:176) +#define NVCB97_TEXHEAD_PITCHCK_RESERVED5A MW(190:190) +#define NVCB97_TEXHEAD_PITCHCK_NORMALIZED_COORDS MW(191:191) +#define NVCB97_TEXHEAD_PITCHCK_COLOR_KEY_OP MW(192:192) +#define NVCB97_TEXHEAD_PITCHCK_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_PITCHCK_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Header V2 Blocklinear + */ + +#define NVCB97_TEXHEAD_V2_BL_RESERVED0A MW(3:0) +#define NVCB97_TEXHEAD_V2_BL_GOB_DEPTH_OFFSET MW(8:4) +#define NVCB97_TEXHEAD_V2_BL_ADDRESS_BITS31TO9 MW(31:9) +#define NVCB97_TEXHEAD_V2_BL_ADDRESS_BITS56TO32 MW(56:32) +#define NVCB97_TEXHEAD_V2_BL_RESERVED1A MW(63:57) +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_WIDTH MW(66:64) +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT MW(69:67) +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH MW(72:70) +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_RESERVED3Y MW(73:73) +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS MW(76:74) +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_GOB3D MW(77:77) +#define NVCB97_TEXHEAD_V2_BL_RESERVED2Z MW(79:78) +#define NVCB97_TEXHEAD_V2_BL_LOD_ANISO_QUALITY2 MW(80:80) +#define NVCB97_TEXHEAD_V2_BL_LOD_ANISO_QUALITY MW(81:81) +#define NVCB97_TEXHEAD_V2_BL_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_LOD_ISO_QUALITY MW(82:82) +#define NVCB97_TEXHEAD_V2_BL_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_MODIFIER MW(84:83) +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_ANISO_SPREAD_SCALE MW(89:85) +#define NVCB97_TEXHEAD_V2_BL_USE_HEADER_OPT_CONTROL MW(90:90) +#define NVCB97_TEXHEAD_V2_BL_DEPTH_TEXTURE MW(91:91) +#define NVCB97_TEXHEAD_V2_BL_MAX_MIP_LEVEL MW(95:92) +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE MW(98:96) +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE MW(101:99) +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE MW(104:102) +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE MW(107:105) +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE MW(111:108) +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_UNORM 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_SNORM 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_FLOAT 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_SGNRGB 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_SGNA 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_DSDT 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_UINT 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_SINT 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_ZS 0x00000008 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_SZ 0x00000009 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_ZFS 0x0000000a +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS MW(118:112) +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_V2_BL_PACK_COMPONENTS MW(119:119) +#define NVCB97_TEXHEAD_V2_BL_RESERVED3A MW(123:120) +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION MW(127:124) +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION_SELECT_PITCH_COLOR_KEY_V2 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION_SELECT_PITCH_V2 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION_SELECT_BLOCKLINEAR_V2 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY_V2 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION_SELECT_ONE_D_RAW_TYPED 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION_SELECT_ONE_D_STRUCT_BUF 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_V2_BL_NORMALIZED_COORDS MW(145:145) +#define NVCB97_TEXHEAD_V2_BL_ANISO_SPREAD_MAX_LOG2 MW(148:146) +#define NVCB97_TEXHEAD_V2_BL_S_R_G_B_CONVERSION MW(149:149) +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE MW(153:150) +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_V2_BL_SECTOR_PROMOTION MW(155:154) +#define NVCB97_TEXHEAD_V2_BL_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_BORDER_SOURCE MW(156:156) +#define NVCB97_TEXHEAD_V2_BL_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_RESERVED4A MW(159:157) +#define NVCB97_TEXHEAD_V2_BL_HEIGHT_MINUS_ONE MW(176:160) +#define NVCB97_TEXHEAD_V2_BL_DEPTH_MINUS_ONE MW(191:177) +#define NVCB97_TEXHEAD_V2_BL_RESERVED6Y MW(192:192) +#define NVCB97_TEXHEAD_V2_BL_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_V2_BL_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_V2_BL_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVCB97_TEXHEAD_V2_BL_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT MW(235:232) +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVCB97_TEXHEAD_V2_BL_MIN_LOD_CLAMP MW(247:236) +#define NVCB97_TEXHEAD_V2_BL_RESERVED7Y MW(255:248) + + +/* +** Texture Header V2 Blocklinear Color Key + */ + +#define NVCB97_TEXHEAD_V2_BLCK_RESERVED0A MW(3:0) +#define NVCB97_TEXHEAD_V2_BLCK_GOB_DEPTH_OFFSET MW(8:4) +#define NVCB97_TEXHEAD_V2_BLCK_ADDRESS_BITS31TO9 MW(31:9) +#define NVCB97_TEXHEAD_V2_BLCK_ADDRESS_BITS56TO32 MW(56:32) +#define NVCB97_TEXHEAD_V2_BLCK_RESERVED1A MW(63:57) +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_WIDTH MW(66:64) +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT MW(69:67) +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH MW(72:70) +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_RESERVED3Y MW(73:73) +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS MW(76:74) +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_GOB3D MW(77:77) +#define NVCB97_TEXHEAD_V2_BLCK_RESERVED2Z MW(79:78) +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ANISO_QUALITY2 MW(80:80) +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ANISO_QUALITY MW(81:81) +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ISO_QUALITY MW(82:82) +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_MODIFIER MW(84:83) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_SPREAD_SCALE MW(89:85) +#define NVCB97_TEXHEAD_V2_BLCK_USE_HEADER_OPT_CONTROL MW(90:90) +#define NVCB97_TEXHEAD_V2_BLCK_DEPTH_TEXTURE MW(91:91) +#define NVCB97_TEXHEAD_V2_BLCK_MAX_MIP_LEVEL MW(95:92) +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE MW(98:96) +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE MW(101:99) +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE MW(104:102) +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE MW(107:105) +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE MW(111:108) +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_UNORM 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_SNORM 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_FLOAT 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_SGNRGB 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_SGNA 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_DSDT 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_UINT 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_SINT 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_ZS 0x00000008 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_SZ 0x00000009 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_ZFS 0x0000000a +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS MW(118:112) +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_V2_BLCK_PACK_COMPONENTS MW(119:119) +#define NVCB97_TEXHEAD_V2_BLCK_RESERVED3A MW(123:120) +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION MW(127:124) +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY_V2 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION_SELECT_PITCH_V2 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR_V2 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY_V2 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION_SELECT_ONE_D_RAW_TYPED 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION_SELECT_ONE_D_STRUCT_BUF 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_V2_BLCK_NORMALIZED_COORDS MW(145:145) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_SPREAD_MAX_LOG2 MW(148:146) +#define NVCB97_TEXHEAD_V2_BLCK_S_R_G_B_CONVERSION MW(149:149) +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE MW(153:150) +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_V2_BLCK_SECTOR_PROMOTION MW(155:154) +#define NVCB97_TEXHEAD_V2_BLCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_BORDER_SOURCE MW(156:156) +#define NVCB97_TEXHEAD_V2_BLCK_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_RESERVED4A MW(159:157) +#define NVCB97_TEXHEAD_V2_BLCK_HEIGHT_MINUS_ONE MW(176:160) +#define NVCB97_TEXHEAD_V2_BLCK_DEPTH_MINUS_ONE MW(191:177) +#define NVCB97_TEXHEAD_V2_BLCK_COLOR_KEY_OP MW(192:192) +#define NVCB97_TEXHEAD_V2_BLCK_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_V2_BLCK_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Header V2 One-D Raw Typed + */ + +#define NVCB97_TEXHEAD_V2_1DRT_ADDRESS_BITS31TO0 MW(31:0) +#define NVCB97_TEXHEAD_V2_1DRT_ADDRESS_BITS63TO32 MW(63:32) +#define NVCB97_TEXHEAD_V2_1DRT_WIDTH_MINUS_ONE MW(95:64) +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE MW(98:96) +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE MW(101:99) +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE MW(104:102) +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE MW(107:105) +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE MW(111:108) +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_UNORM 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_SNORM 0x00000001 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_FLOAT 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_SGNRGB 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_SGNA 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_DSDT 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_UINT 0x00000006 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_SINT 0x00000007 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_ZS 0x00000008 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_SZ 0x00000009 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_ZFS 0x0000000a +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS MW(117:112) +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_INVALID 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_G8R24 0x0000000d +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_G24R8 0x0000000e +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R32 0x0000000f +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_G8R8 0x00000018 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R16 0x0000001b +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R8 0x0000001d +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_G4R4 0x0000001e +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_X8B8G8R8_SRGB 0x00000031 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_A8B8G8R8_SRGB 0x00000032 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_G8R8_SRGB 0x00000033 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R8_SRGB 0x00000034 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZESV2_CS_BITFIELD_SIZE 0x0000003f +#define NVCB97_TEXHEAD_V2_1DRT_SECTOR_PROMOTION MW(119:118) +#define NVCB97_TEXHEAD_V2_1DRT_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_V2_1DRT_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_RESERVED3A MW(123:120) +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION MW(127:124) +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION_SELECT_PITCH_COLOR_KEY_V2 0x00000001 +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION_SELECT_PITCH_V2 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION_SELECT_BLOCKLINEAR_V2 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY_V2 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION_SELECT_ONE_D_RAW_TYPED 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION_SELECT_ONE_D_STRUCT_BUF 0x00000006 +#define NVCB97_TEXHEAD_V2_1DRT_RESERVED4X MW(156:128) +#define NVCB97_TEXHEAD_V2_1DRT_RESERVED4A MW(159:157) +#define NVCB97_TEXHEAD_V2_1DRT_RESERVED5X MW(191:160) +#define NVCB97_TEXHEAD_V2_1DRT_RESERVED6X MW(223:192) +#define NVCB97_TEXHEAD_V2_1DRT_RESERVED7X MW(255:224) + + +/* +** Texture Header V2 One-D Structured Buffer + */ + +#define NVCB97_TEXHEAD_V2_1DSB_ADDRESS_BITS31TO0 MW(31:0) +#define NVCB97_TEXHEAD_V2_1DSB_ADDRESS_BITS63TO32 MW(63:32) +#define NVCB97_TEXHEAD_V2_1DSB_WIDTH_MINUS_ONE MW(95:64) +#define NVCB97_TEXHEAD_V2_1DSB_STRIDE MW(107:96) +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE MW(111:108) +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_UNORM 0x00000000 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_SNORM 0x00000001 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_FLOAT 0x00000002 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_SGNRGB 0x00000003 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_SGNA 0x00000004 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_DSDT 0x00000005 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_UINT 0x00000006 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_SINT 0x00000007 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_ZS 0x00000008 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_SZ 0x00000009 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_ZFS 0x0000000a +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS MW(117:112) +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_INVALID 0x00000000 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_G8R24 0x0000000d +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_G24R8 0x0000000e +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R32 0x0000000f +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_G8R8 0x00000018 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R16 0x0000001b +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R8 0x0000001d +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_G4R4 0x0000001e +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_X8B8G8R8_SRGB 0x00000031 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_A8B8G8R8_SRGB 0x00000032 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_G8R8_SRGB 0x00000033 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R8_SRGB 0x00000034 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZESV2_CS_BITFIELD_SIZE 0x0000003f +#define NVCB97_TEXHEAD_V2_1DSB_SECTOR_PROMOTION MW(119:118) +#define NVCB97_TEXHEAD_V2_1DSB_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_V2_1DSB_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_V2_1DSB_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_V2_1DSB_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_V2_1DSB_RESERVED3A MW(123:120) +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION MW(127:124) +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION_SELECT_PITCH_COLOR_KEY_V2 0x00000001 +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION_SELECT_PITCH_V2 0x00000002 +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION_SELECT_BLOCKLINEAR_V2 0x00000003 +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY_V2 0x00000004 +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION_SELECT_ONE_D_RAW_TYPED 0x00000005 +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION_SELECT_ONE_D_STRUCT_BUF 0x00000006 +#define NVCB97_TEXHEAD_V2_1DSB_RESERVED4X MW(156:128) +#define NVCB97_TEXHEAD_V2_1DSB_RESERVED4A MW(159:157) +#define NVCB97_TEXHEAD_V2_1DSB_RESERVED5X MW(191:160) +#define NVCB97_TEXHEAD_V2_1DSB_RESERVED6X MW(223:192) +#define NVCB97_TEXHEAD_V2_1DSB_RESERVED7X MW(255:224) + + +/* +** Texture Header V2 Pitch + */ + +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED0A MW(3:0) +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED0X MW(4:4) +#define NVCB97_TEXHEAD_V2_PITCH_ADDRESS_BITS31TO5 MW(31:5) +#define NVCB97_TEXHEAD_V2_PITCH_ADDRESS_BITS56TO32 MW(56:32) +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED1A MW(63:57) +#define NVCB97_TEXHEAD_V2_PITCH_PITCH_BITS21TO5 MW(80:64) +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ANISO_QUALITY2 MW(81:81) +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ANISO_QUALITY MW(82:82) +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ISO_QUALITY MW(83:83) +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_MODIFIER MW(85:84) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_SPREAD_SCALE MW(90:86) +#define NVCB97_TEXHEAD_V2_PITCH_DEPTH_TEXTURE MW(91:91) +#define NVCB97_TEXHEAD_V2_PITCH_MAX_MIP_LEVEL MW(95:92) +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE MW(98:96) +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE MW(101:99) +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE MW(104:102) +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE MW(107:105) +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE MW(111:108) +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_UNORM 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_SNORM 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_FLOAT 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_SGNRGB 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_SGNA 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_DSDT 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_UINT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_SINT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_ZS 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_SZ 0x00000009 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_ZFS 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS MW(118:112) +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_V2_PITCH_PACK_COMPONENTS MW(119:119) +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED3A MW(123:120) +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION MW(127:124) +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION_SELECT_PITCH_COLOR_KEY_V2 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION_SELECT_PITCH_V2 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR_V2 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY_V2 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION_SELECT_ONE_D_RAW_TYPED 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION_SELECT_ONE_D_STRUCT_BUF 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_V2_PITCH_NORMALIZED_COORDS MW(145:145) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_SPREAD_MAX_LOG2 MW(148:146) +#define NVCB97_TEXHEAD_V2_PITCH_S_R_G_B_CONVERSION MW(149:149) +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE MW(153:150) +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_V2_PITCH_SECTOR_PROMOTION MW(155:154) +#define NVCB97_TEXHEAD_V2_PITCH_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_BORDER_SOURCE MW(156:156) +#define NVCB97_TEXHEAD_V2_PITCH_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED4A MW(159:157) +#define NVCB97_TEXHEAD_V2_PITCH_HEIGHT_MINUS_ONE MW(176:160) +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED5Y MW(191:177) +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED6Y MW(192:192) +#define NVCB97_TEXHEAD_V2_PITCH_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_V2_PITCH_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVCB97_TEXHEAD_V2_PITCH_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT MW(235:232) +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVCB97_TEXHEAD_V2_PITCH_MIN_LOD_CLAMP MW(247:236) +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED7Y MW(255:248) + + +/* +** Texture Header V2 Pitch Color Key + */ + +#define NVCB97_TEXHEAD_V2_PITCHCK_RESERVED0A MW(3:0) +#define NVCB97_TEXHEAD_V2_PITCHCK_RESERVED0X MW(4:4) +#define NVCB97_TEXHEAD_V2_PITCHCK_ADDRESS_BITS31TO5 MW(31:5) +#define NVCB97_TEXHEAD_V2_PITCHCK_ADDRESS_BITS56TO32 MW(56:32) +#define NVCB97_TEXHEAD_V2_PITCHCK_RESERVED1A MW(63:57) +#define NVCB97_TEXHEAD_V2_PITCHCK_PITCH_BITS21TO5 MW(80:64) +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ANISO_QUALITY2 MW(81:81) +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ANISO_QUALITY MW(82:82) +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ISO_QUALITY MW(83:83) +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER MW(85:84) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_SPREAD_SCALE MW(90:86) +#define NVCB97_TEXHEAD_V2_PITCHCK_DEPTH_TEXTURE MW(91:91) +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_MIP_LEVEL MW(95:92) +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE MW(98:96) +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE MW(101:99) +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE MW(104:102) +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE MW(107:105) +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE MW(111:108) +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_UNORM 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_SNORM 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_FLOAT 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_SGNRGB 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_SGNA 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_DSDT 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_UINT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_SINT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_ZS 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_SZ 0x00000009 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_ZFS 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS MW(118:112) +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_V2_PITCHCK_PACK_COMPONENTS MW(119:119) +#define NVCB97_TEXHEAD_V2_PITCHCK_RESERVED3A MW(123:120) +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION MW(127:124) +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY_V2 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION_SELECT_PITCH_V2 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR_V2 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY_V2 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION_SELECT_ONE_D_RAW_TYPED 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION_SELECT_ONE_D_STRUCT_BUF 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_V2_PITCHCK_NORMALIZED_COORDS MW(145:145) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_SPREAD_MAX_LOG2 MW(148:146) +#define NVCB97_TEXHEAD_V2_PITCHCK_S_R_G_B_CONVERSION MW(149:149) +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE MW(153:150) +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_V2_PITCHCK_SECTOR_PROMOTION MW(155:154) +#define NVCB97_TEXHEAD_V2_PITCHCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_BORDER_SOURCE MW(156:156) +#define NVCB97_TEXHEAD_V2_PITCHCK_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_RESERVED4A MW(159:157) +#define NVCB97_TEXHEAD_V2_PITCHCK_HEIGHT_MINUS_ONE MW(176:160) +#define NVCB97_TEXHEAD_V2_PITCHCK_RESERVED5Y MW(191:177) +#define NVCB97_TEXHEAD_V2_PITCHCK_COLOR_KEY_OP MW(192:192) +#define NVCB97_TEXHEAD_V2_PITCHCK_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_V2_PITCHCK_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Sampler State + */ + +#define NVCB97_TEXSAMP0_ADDRESS_U 2:0 +#define NVCB97_TEXSAMP0_ADDRESS_U_WRAP 0x00000000 +#define NVCB97_TEXSAMP0_ADDRESS_U_MIRROR 0x00000001 +#define NVCB97_TEXSAMP0_ADDRESS_U_CLAMP_TO_EDGE 0x00000002 +#define NVCB97_TEXSAMP0_ADDRESS_U_BORDER 0x00000003 +#define NVCB97_TEXSAMP0_ADDRESS_U_CLAMP_OGL 0x00000004 +#define NVCB97_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVCB97_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_BORDER 0x00000006 +#define NVCB97_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVCB97_TEXSAMP0_ADDRESS_V 5:3 +#define NVCB97_TEXSAMP0_ADDRESS_V_WRAP 0x00000000 +#define NVCB97_TEXSAMP0_ADDRESS_V_MIRROR 0x00000001 +#define NVCB97_TEXSAMP0_ADDRESS_V_CLAMP_TO_EDGE 0x00000002 +#define NVCB97_TEXSAMP0_ADDRESS_V_BORDER 0x00000003 +#define NVCB97_TEXSAMP0_ADDRESS_V_CLAMP_OGL 0x00000004 +#define NVCB97_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVCB97_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_BORDER 0x00000006 +#define NVCB97_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVCB97_TEXSAMP0_ADDRESS_P 8:6 +#define NVCB97_TEXSAMP0_ADDRESS_P_WRAP 0x00000000 +#define NVCB97_TEXSAMP0_ADDRESS_P_MIRROR 0x00000001 +#define NVCB97_TEXSAMP0_ADDRESS_P_CLAMP_TO_EDGE 0x00000002 +#define NVCB97_TEXSAMP0_ADDRESS_P_BORDER 0x00000003 +#define NVCB97_TEXSAMP0_ADDRESS_P_CLAMP_OGL 0x00000004 +#define NVCB97_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVCB97_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_BORDER 0x00000006 +#define NVCB97_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE 9:9 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC 12:10 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_NEVER 0x00000000 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_LESS 0x00000001 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_EQUAL 0x00000002 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_LEQUAL 0x00000003 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_GREATER 0x00000004 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_NOTEQUAL 0x00000005 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_GEQUAL 0x00000006 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_ALWAYS 0x00000007 +#define NVCB97_TEXSAMP0_S_R_G_B_CONVERSION 13:13 +#define NVCB97_TEXSAMP0_RESERVED0A 16:14 +#define NVCB97_TEXSAMP0_RESERVED0B 19:17 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY 22:20 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXSAMP0_FORCED_INVALID 31:31 +#define NVCB97_TEXSAMP1_MAG_FILTER 2:0 +#define NVCB97_TEXSAMP1_MAG_FILTER_MAG_POINT 0x00000001 +#define NVCB97_TEXSAMP1_MAG_FILTER_MAG_LINEAR 0x00000002 +#define NVCB97_TEXSAMP1_MAG_FILTER_VCAA_4_TAP 0x00000003 +#define NVCB97_TEXSAMP1_MAG_FILTER_VCAA_8_TAP 0x00000004 +#define NVCB97_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP 3:3 +#define NVCB97_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP_INTEGER_AND_FRACTION 0x00000000 +#define NVCB97_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP_INTEGER_ONLY 0x00000001 +#define NVCB97_TEXSAMP1_MIN_FILTER 5:4 +#define NVCB97_TEXSAMP1_MIN_FILTER_MIN_POINT 0x00000001 +#define NVCB97_TEXSAMP1_MIN_FILTER_MIN_LINEAR 0x00000002 +#define NVCB97_TEXSAMP1_MIN_FILTER_MIN_ANISO 0x00000003 +#define NVCB97_TEXSAMP1_MIP_FILTER 7:6 +#define NVCB97_TEXSAMP1_MIP_FILTER_MIP_NONE 0x00000001 +#define NVCB97_TEXSAMP1_MIP_FILTER_MIP_POINT 0x00000002 +#define NVCB97_TEXSAMP1_MIP_FILTER_MIP_LINEAR 0x00000003 +#define NVCB97_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING 9:8 +#define NVCB97_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_USE_WRAP 0x00000000 +#define NVCB97_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_OVERRIDE_WRAP 0x00000001 +#define NVCB97_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_AUTO_SPAN_SEAM 0x00000002 +#define NVCB97_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_AUTO_CROSS_SEAM 0x00000003 +#define NVCB97_TEXSAMP1_REDUCTION_FILTER 11:10 +#define NVCB97_TEXSAMP1_REDUCTION_FILTER_RED_NONE 0x00000000 +#define NVCB97_TEXSAMP1_REDUCTION_FILTER_RED_MINIMUM 0x00000001 +#define NVCB97_TEXSAMP1_REDUCTION_FILTER_RED_MAXIMUM 0x00000002 +#define NVCB97_TEXSAMP1_MIP_LOD_BIAS 24:12 +#define NVCB97_TEXSAMP1_FLOAT_COORD_NORMALIZATION 25:25 +#define NVCB97_TEXSAMP1_FLOAT_COORD_NORMALIZATION_USE_HEADER_SETTING 0x00000000 +#define NVCB97_TEXSAMP1_FLOAT_COORD_NORMALIZATION_FORCE_UNNORMALIZED_COORDS 0x00000001 +#define NVCB97_TEXSAMP1_TRILIN_OPT 30:26 +#define NVCB97_TEXSAMP2_MIN_LOD_CLAMP 11:0 +#define NVCB97_TEXSAMP2_MAX_LOD_CLAMP 23:12 +#define NVCB97_TEXSAMP2_S_R_G_B_BORDER_COLOR_R 31:24 +#define NVCB97_TEXSAMP3_RESERVED12 11:0 +#define NVCB97_TEXSAMP3_S_R_G_B_BORDER_COLOR_G 19:12 +#define NVCB97_TEXSAMP3_S_R_G_B_BORDER_COLOR_B 27:20 +#define NVCB97_TEXSAMP4_BORDER_COLOR_R 31:0 +#define NVCB97_TEXSAMP5_BORDER_COLOR_G 31:0 +#define NVCB97_TEXSAMP6_BORDER_COLOR_B 31:0 +#define NVCB97_TEXSAMP7_BORDER_COLOR_A 31:0 + + + +#endif // #ifndef __CLCB97TEX_H__ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clcbc0.h b/userspace/sdks/nv570/nvidia/inc/class/clcbc0.h new file mode 100644 index 0000000..bed5e94 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clcbc0.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_clcbc0_h__ +#define __gh100_clcbc0_h__ +#define HOPPER_COMPUTE_A 0xCBC0 +#endif // __gh100_clcbc0_h__ diff --git a/userspace/sdks/nv570/nvidia/inc/class/clcbca.h b/userspace/sdks/nv570/nvidia/inc/class/clcbca.h new file mode 100644 index 0000000..4570cc9 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/clcbca.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _CLCBCA_H_ +#define _CLCBCA_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV_COUNTER_COLLECTION_UNIT (0x0000CBCA) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _CLCBCA_H_ diff --git a/userspace/sdks/nv570/nvidia/inc/class/cld0b7.h b/userspace/sdks/nv570/nvidia/inc/class/cld0b7.h new file mode 100644 index 0000000..d7c044d --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/class/cld0b7.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef cld0b7_h +#define cld0b7_h + +#include "nvtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVD0B7_VIDEO_ENCODER (0x0000D0B7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // cld0b7_h + diff --git a/userspace/sdks/nv570/nvidia/inc/cpuopsys.h b/userspace/sdks/nv570/nvidia/inc/cpuopsys.h new file mode 100644 index 0000000..230c7b5 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/cpuopsys.h @@ -0,0 +1,422 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! \brief + * Define compile time symbols for CPU type and operating system type. + * This file should only contain preprocessor commands so that + * there are no dependencies on other files. + * + * cpuopsys.h + * + * Copyright (c) 2001, Nvidia Corporation. All rights reserved. + */ + +/*! + * Uniform names are defined for compile time options to distinguish + * CPU types and Operating systems. + * Distinctions between CPU and OpSys should be orthogonal. + * + * These uniform names have initially been defined by keying off the + * makefile/build names defined for builds in the OpenGL group. + * Getting the uniform names defined for other builds may require + * different qualifications. + * + * The file is placed here to allow for the possibility of all driver + * components using the same naming convention for conditional compilation. + */ + +#ifndef CPUOPSYS_H +#define CPUOPSYS_H + +/*****************************************************************************/ +/* Define all OS/CPU-Chip related symbols */ + +/* ***** WINDOWS variations */ +#if defined(_WIN32) || defined(_WIN16) +# define NV_WINDOWS + +# if defined(_WIN32_WINNT) +# define NV_WINDOWS_NT +# elif defined(_WIN32_WCE) +# define NV_WINDOWS_CE +# else +# define NV_WINDOWS_9X +# endif +#endif /* _WIN32 || defined(_WIN16) */ + +/* ***** Unix variations */ +#if defined(__linux__) && !defined(NV_LINUX) && !defined(NV_VMWARE) +# define NV_LINUX +#endif /* defined(__linux__) */ + +#if defined(__VMWARE__) && !defined(NV_VMWARE) +# define NV_VMWARE +#endif /* defined(__VMWARE__) */ + +/* SunOS + gcc */ +#if defined(__sun__) && defined(__svr4__) && !defined(NV_SUNOS) +# define NV_SUNOS +#endif /* defined(__sun__) && defined(__svr4__) */ + +/* SunOS + Sun Compiler (named SunPro, Studio or Forte) */ +#if defined(__SUNPRO_C) || defined(__SUNPRO_CC) +# define NV_SUNPRO_C +# define NV_SUNOS +#endif /* defined(_SUNPRO_C) || defined(__SUNPRO_CC) */ + +#if defined(__FreeBSD__) && !defined(NV_BSD) +# define NV_BSD +#endif /* defined(__FreeBSD__) */ + +/* XXXar don't define NV_UNIX on MacOSX or vxworks or QNX */ +#if (defined(__unix__) || defined(__unix) || defined(__INTEGRITY) ) && !defined(nvmacosx) && !defined(vxworks) && !defined(NV_UNIX) && !defined(__QNX__) && !defined(__QNXNTO__)/* XXX until removed from Makefiles */ +# define NV_UNIX +#endif /* defined(__unix__) */ + +#if (defined(__QNX__) || defined(__QNXNTO__)) && !defined(NV_QNX) +# define NV_QNX +#endif + +#if (defined(__ANDROID__) || defined(ANDROID)) && !defined(NV_ANDROID) +# define NV_ANDROID +#endif + +#if defined(DceCore) && !defined(NV_DCECORE) +# define NV_DCECORE +#endif + +/* ***** Apple variations */ +#if defined(macintosh) || defined(__APPLE__) +# define NV_MACINTOSH +# if defined(__MACH__) +# define NV_MACINTOSH_OSX +# else +# define NV_MACINTOSH_OS9 +# endif +# if defined(__LP64__) +# define NV_MACINTOSH_64 +# endif +#endif /* defined(macintosh) */ + +/* ***** VxWorks */ +/* Tornado 2.21 is gcc 2.96 and #defines __vxworks. */ +/* Tornado 2.02 is gcc 2.7.2 and doesn't define any OS symbol, so we rely on */ +/* the build system #defining vxworks. */ +#if defined(__vxworks) || defined(vxworks) +# define NV_VXWORKS +#endif + +/* ***** Integrity OS */ +#if defined(__INTEGRITY) +# if !defined(NV_INTEGRITY) +# define NV_INTEGRITY +# endif +#endif + +/* ***** Processor type variations */ +/* Note: The prefix NV_CPU_* is taken by Nvcm.h */ + +#if ((defined(_M_IX86) || defined(__i386__) || defined(__i386)) && !defined(NVCPU_X86)) /* XXX until removed from Makefiles */ +/* _M_IX86 for windows, __i386__ for Linux (or any x86 using gcc) */ +/* __i386 for Studio compiler on Solaris x86 */ +# define NVCPU_X86 /* any IA32 machine (not x86-64) */ +# define NVCPU_MIN_PAGE_SHIFT 12 +#endif + +#if defined(NV_LINUX) && defined(__ia64__) +# define NVCPU_IA64_LINUX /* any IA64 for Linux opsys */ +#endif +#if defined(NVCPU_IA64_WINDOWS) || defined(NVCPU_IA64_LINUX) || defined(IA64) +# define NVCPU_IA64 /* any IA64 for any opsys */ +#endif + +#if (defined(NV_MACINTOSH) && !(defined(__i386__) || defined(__x86_64__))) || defined(__PPC__) || defined(__ppc) +# if defined(__powerpc64__) && defined(__LITTLE_ENDIAN__) +# ifndef NVCPU_PPC64LE +# define NVCPU_PPC64LE /* PPC 64-bit little endian */ +# endif +# else +# ifndef NVCPU_PPC +# define NVCPU_PPC /* any non-PPC64LE PowerPC architecture */ +# endif +# ifndef NV_BIG_ENDIAN +# define NV_BIG_ENDIAN +# endif +# endif +# define NVCPU_FAMILY_PPC +#endif + +#if defined(__x86_64) || defined(AMD64) || defined(_M_AMD64) +# define NVCPU_X86_64 /* any x86-64 for any opsys */ +#endif + +#if defined(NVCPU_X86) || defined(NVCPU_X86_64) +# define NVCPU_FAMILY_X86 +#endif + +#if defined(__riscv) && (__riscv_xlen==64) +# define NVCPU_RISCV64 +# if defined(__nvriscv) +# define NVCPU_NVRISCV64 +# endif +#endif + +#if defined(__arm__) || defined(_M_ARM) +/* + * 32-bit instruction set on, e.g., ARMv7 or AArch32 execution state + * on ARMv8 + */ +# define NVCPU_ARM +# define NVCPU_MIN_PAGE_SHIFT 12 +#endif + +#if defined(__aarch64__) || defined(__ARM64__) || defined(_M_ARM64) +# define NVCPU_AARCH64 /* 64-bit A64 instruction set on ARMv8 */ +# define NVCPU_MIN_PAGE_SHIFT 12 +#endif + +#if defined(NVCPU_ARM) || defined(NVCPU_AARCH64) +# define NVCPU_FAMILY_ARM +#endif + +#if defined(__SH4__) +# ifndef NVCPU_SH4 +# define NVCPU_SH4 /* Renesas (formerly Hitachi) SH4 */ +# endif +# if defined NV_WINDOWS_CE +# define NVCPU_MIN_PAGE_SHIFT 12 +# endif +#endif + +/* For Xtensa processors */ +#if defined(__XTENSA__) +# define NVCPU_XTENSA +# if defined(__XTENSA_EB__) +# define NV_BIG_ENDIAN +# endif +#endif + + +/* + * Other flavors of CPU type should be determined at run-time. + * For example, an x86 architecture with/without SSE. + * If it can compile, then there's no need for a compile time option. + * For some current GCC limitations, these may be fixed by using the Intel + * compiler for certain files in a Linux build. + */ + +/* The minimum page size can be determined from the minimum page shift */ +#if defined(NVCPU_MIN_PAGE_SHIFT) +#define NVCPU_MIN_PAGE_SIZE (1 << NVCPU_MIN_PAGE_SHIFT) +#endif + +#if defined(NVCPU_IA64) || defined(NVCPU_X86_64) || \ + defined(NV_MACINTOSH_64) || defined(NVCPU_AARCH64) || \ + defined(NVCPU_PPC64LE) || defined(NVCPU_RISCV64) +# define NV_64_BITS /* all architectures where pointers are 64 bits */ +#else +/* we assume 32 bits. I don't see a need for NV_16_BITS. */ +#endif + +/* For verification-only features not intended to be included in normal drivers */ +#if defined(ENABLE_VERIF_FEATURES) +#define NV_VERIF_FEATURES +#endif + +/* + * New, safer family of #define's -- these ones use 0 vs. 1 rather than + * defined/!defined. This is advantageous because if you make a typo, + * say misspelled ENDIAN: + * + * #if NVCPU_IS_BIG_ENDAIN + * + * ...some compilers can give you a warning telling you that you screwed up. + * The compiler can also give you a warning if you forget to #include + * "cpuopsys.h" in your code before the point where you try to use these + * conditionals. + * + * Also, the names have been prefixed in more cases with "CPU" or "OS" for + * increased clarity. You can tell the names apart from the old ones because + * they all use "_IS_" in the name. + * + * Finally, these can be used in "if" statements and not just in #if's. For + * example: + * + * if (NVCPU_IS_BIG_ENDIAN) x = Swap32(x); + * + * Maybe some day in the far-off future these can replace the old #define's. + */ + +#define NV_IS_MODS 0 + +#define NVOS_IS_WINDOWS 0 +#if defined(NV_WINDOWS_CE) +#define NVOS_IS_WINDOWS_CE 1 +#else +#define NVOS_IS_WINDOWS_CE 0 +#endif +#if defined(NV_LINUX) +#define NVOS_IS_LINUX 1 +#else +#define NVOS_IS_LINUX 0 +#endif +#if defined(NV_UNIX) +#define NVOS_IS_UNIX 1 +#else +#define NVOS_IS_UNIX 0 +#endif +#if defined(NV_BSD) +#define NVOS_IS_FREEBSD 1 +#else +#define NVOS_IS_FREEBSD 0 +#endif +#if defined(NV_SUNOS) +#define NVOS_IS_SOLARIS 1 +#else +#define NVOS_IS_SOLARIS 0 +#endif +#define NVOS_IS_VMWARE 0 +#if defined(NV_QNX) +#define NVOS_IS_QNX 1 +#else +#define NVOS_IS_QNX 0 +#endif +#if defined(NV_ANDROID) +#define NVOS_IS_ANDROID 1 +#else +#define NVOS_IS_ANDROID 0 +#endif +#if defined(NV_MACINTOSH) +#define NVOS_IS_MACINTOSH 1 +#else +#define NVOS_IS_MACINTOSH 0 +#endif +#if defined(NV_VXWORKS) +#define NVOS_IS_VXWORKS 1 +#else +#define NVOS_IS_VXWORKS 0 +#endif +#if defined(NV_LIBOS) +#define NVOS_IS_LIBOS 1 +#else +#define NVOS_IS_LIBOS 0 +#endif +#if defined(NV_INTEGRITY) +#define NVOS_IS_INTEGRITY 1 +#else +#define NVOS_IS_INTEGRITY 0 +#endif + +#if defined(NVCPU_X86) +#define NVCPU_IS_X86 1 +#else +#define NVCPU_IS_X86 0 +#endif +#if defined(NVCPU_RISCV64) +#define NVCPU_IS_RISCV64 1 +#else +#define NVCPU_IS_RISCV64 0 +#endif +#if defined(NVCPU_NVRISCV64) +#define NVCPU_IS_NVRISCV64 1 +#else +#define NVCPU_IS_NVRISCV64 0 +#endif +#if defined(NVCPU_IA64) +#define NVCPU_IS_IA64 1 +#else +#define NVCPU_IS_IA64 0 +#endif +#if defined(NVCPU_X86_64) +#define NVCPU_IS_X86_64 1 +#else +#define NVCPU_IS_X86_64 0 +#endif +#if defined(NVCPU_FAMILY_X86) +#define NVCPU_IS_FAMILY_X86 1 +#else +#define NVCPU_IS_FAMILY_X86 0 +#endif +#if defined(NVCPU_PPC) +#define NVCPU_IS_PPC 1 +#else +#define NVCPU_IS_PPC 0 +#endif +#if defined(NVCPU_PPC64LE) +#define NVCPU_IS_PPC64LE 1 +#else +#define NVCPU_IS_PPC64LE 0 +#endif +#if defined(NVCPU_FAMILY_PPC) +#define NVCPU_IS_FAMILY_PPC 1 +#else +#define NVCPU_IS_FAMILY_PPC 0 +#endif +#if defined(NVCPU_ARM) +#define NVCPU_IS_ARM 1 +#else +#define NVCPU_IS_ARM 0 +#endif +#if defined(NVCPU_AARCH64) +#define NVCPU_IS_AARCH64 1 +#else +#define NVCPU_IS_AARCH64 0 +#endif +#if defined(NVCPU_FAMILY_ARM) +#define NVCPU_IS_FAMILY_ARM 1 +#else +#define NVCPU_IS_FAMILY_ARM 0 +#endif +#if defined(NVCPU_SH4) +#define NVCPU_IS_SH4 1 +#else +#define NVCPU_IS_SH4 0 +#endif +#if defined(NVCPU_XTENSA) +#define NVCPU_IS_XTENSA 1 +#else +#define NVCPU_IS_XTENSA 0 +#endif +#if defined(NV_BIG_ENDIAN) +#define NVCPU_IS_BIG_ENDIAN 1 +#else +#define NVCPU_IS_BIG_ENDIAN 0 +#endif +#if defined(NV_64_BITS) +#define NVCPU_IS_64_BITS 1 +#else +#define NVCPU_IS_64_BITS 0 +#endif +#if defined(NVCPU_FAMILY_ARM) +#define NVCPU_IS_PCIE_CACHE_COHERENT 0 +#else +#define NVCPU_IS_PCIE_CACHE_COHERENT 1 +#endif +#if defined(NV_DCECORE) +#define NVOS_IS_DCECORE 1 +#else +#define NVOS_IS_DCECORE 0 +#endif +/*****************************************************************************/ + +#endif /* CPUOPSYS_H */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h new file mode 100644 index 0000000..89e2219 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h @@ -0,0 +1,68 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000base.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV01_ROOT (client) control commands and parameters */ + +#define NV0000_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0000,NV0000_CTRL_##cat,idx) + +/* Client command categories (6bits) */ +#define NV0000_CTRL_RESERVED (0x00) +#define NV0000_CTRL_SYSTEM (0x01) +#define NV0000_CTRL_GPU (0x02) +#define NV0000_CTRL_GSYNC (0x03) +#define NV0000_CTRL_DIAG (0x04) +#define NV0000_CTRL_EVENT (0x05) +#define NV0000_CTRL_NVD (0x06) +#define NV0000_CTRL_SWINSTR (0x07) +#define NV0000_CTRL_PROC (0x09) +#define NV0000_CTRL_SYNC_GPU_BOOST (0x0A) +#define NV0000_CTRL_GPUACCT (0x0B) +#define NV0000_CTRL_VGPU (0x0C) +#define NV0000_CTRL_CLIENT (0x0D) + +// per-OS categories start at highest category and work backwards +#define NV0000_CTRL_OS_WINDOWS (0x3F) +#define NV0000_CTRL_OS_MACOS (0x3E) +#define NV0000_CTRL_OS_UNIX (0x3D) + + +/* + * NV0000_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0000_CTRL_CMD_NULL (0x0) /* finn: Evaluated from "(FINN_NV01_ROOT_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrl0000_base_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h new file mode 100644 index 0000000..a05add6 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h @@ -0,0 +1,183 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000client.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +#include "class/cl0000.h" +#include "rs_access.h" + +/* + * NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE + * + * This command may be used to query memory address space type associated with an object + * + * Parameters: + * hObject[IN] + * handle of the object to look up + * addrSpaceType[OUT] + * addrSpaceType with associated memory descriptor + * + * Possible status values are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_OBJECT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE (0xd01) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS { + NvHandle hObject; /* [in] - Handle of object to look up */ + NvU32 mapFlags; /* [in] - Flags that will be used when mapping the object */ + NvU32 addrSpaceType; /* [out] - Memory Address Space Type */ +} NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS; + +#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_INVALID 0x00000000 +#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_SYSMEM 0x00000001 +#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM 0x00000002 +#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_REGMEM 0x00000003 +#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC 0x00000004 + + + +/* + * NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO + * + * This command may be used to query information on a handle + */ +#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO (0xd02) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS { + NvHandle hObject; /* [in] - Handle of object to look up */ + NvU32 index; /* [in] - Type of lookup */ + + union { + NvHandle hResult; /* [out] - Result of lookup when result is a handle type */ + NV_DECLARE_ALIGNED(NvU64 iResult, 8); /* [out] - Result of lookup when result is a integer */ + } data; +} NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS; + +#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_INVALID 0x00000000 +#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_PARENT 0x00000001 +#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_CLASSID 0x00000002 + +/* + * NV0000_CTRL_CMD_CLIENT_GET_ACCESS_RIGHTS + * + * This command may be used to get this client's access rights for an object + * The object to which access rights are checked does not have to be owned by + * the client calling the command, it is owned by the hClient parameter + */ +#define NV0000_CTRL_CMD_CLIENT_GET_ACCESS_RIGHTS (0xd03) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS { + NvHandle hObject; /* [in] - Handle of object to look up */ + NvHandle hClient; /* [in] - Handle of client which owns hObject */ + RS_ACCESS_MASK maskResult; /* [out] - Result of lookup */ +} NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS; + +/* + * NV0000_CTRL_CMD_CLIENT_SET_INHERITED_SHARE_POLICY + * + * DEPRECATED: Calls NV0000_CTRL_CMD_CLIENT_SHARE_OBJECT with hObject=hClient + * + * This command will modify a client's inherited share policy list + * The policy is applied in the same way that NvRmShare applies policies, + * except to the client's inherited policy list instead of an object's policy list + */ +#define NV0000_CTRL_CMD_CLIENT_SET_INHERITED_SHARE_POLICY (0xd04) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS { + RS_SHARE_POLICY sharePolicy; /* [in] - Share Policy to apply */ +} NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS; + +/* + * NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE + * + * This command may be used to get a handle of a child of a given type + */ +#define NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE (0xd05) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS { + NvHandle hParent; /* [in] - Handle of parent object */ + NvU32 classId; /* [in] - Class ID of the child object */ + NvHandle hObject; /* [out] - Handle of the child object (0 if not found) */ +} NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS; + +/* + * NV0000_CTRL_CMD_CLIENT_SHARE_OBJECT + * + * This command is meant to imitate the NvRmShare API. + * Applies a share policy to an object, which should be owned by the caller's client. + * The policy is applied in the same way that NvRmShare applies policies. + * + * This ctrl command is only meant to be used in older branches. For releases after R450, + * use NvRmShare directly instead. + */ +#define NV0000_CTRL_CMD_CLIENT_SHARE_OBJECT (0xd06) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS { + NvHandle hObject; /* [in] - Handle of object to share */ + RS_SHARE_POLICY sharePolicy; /* [in] - Share Policy to apply */ +} NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS; + +/* + * NV0000_CTRL_CMD_CLIENT_OBJECTS_ARE_DUPLICATES + * + * This command returns true if the objects are duplicates. + * + * Currently supported only for memory objects. + */ +#define NV0000_CTRL_CMD_CLIENT_OBJECTS_ARE_DUPLICATES (0xd07) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS { + NvHandle hObject1; /* [in] - Handle of object to be checked */ + NvHandle hObject2; /* [in] - Handle of object to be checked */ + NvBool bDuplicates; /* [out] - Returns true if duplicates */ +} NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS; + +/* _ctrl0000client_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h new file mode 100644 index 0000000..9b72f20 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h @@ -0,0 +1,326 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000diag.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +/* NV01_ROOT (client) system control commands and parameters */ + +/* + * NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_STATE + * + * This command returns the current lock meter logging state. + * + * state + * This parameter returns the current lock meter logging state. + * NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_DISABLED + * This value indicates lock metering is disabled. + * NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_ENABLED + * This value indicates lock metering is enabled. + * count + * This parameter returns the total number of lock metering entries + * (NV0000_CTRL_DIAG_LOCK_METER_ENTRY) available. This value will + * not exceed NV0000_CTRL_DIAG_LOCK_METER_MAX_ENTRIES. When lock metering + * is enabled this parameter will return zero. + * missedCount + * This parameter returns the number of lock metering entries that had + * to be discarded due to a full lock metering table. This value will + * not exceed NV0000_CTRL_DIAG_LOCK_METER_MAX_TABLE_ENTRIES. When lock + * metering is enabled this parameter will return zero. + * bCircularBuffer + * This parameter returns type of buffer. + * TRUE + * Buffer is circular + * FALSE + * Buffer is sequential + * + * Possible status values returned are: + * NV_OK + */ +#define NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_STATE (0x480) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS_MESSAGE_ID (0x80U) + +typedef struct NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS { + NvU32 state; + NvU32 count; + NvU32 missedCount; + NvBool bCircularBuffer; +} NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS; + +/* valid lock metering state values */ +#define NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_DISABLED (0x00000000) +#define NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_ENABLED (0x00000001) + +/* maximum possible number of lock metering entries stored internally */ +#define NV0000_CTRL_DIAG_LOCK_METER_MAX_TABLE_ENTRIES (0x20000) + +/* + * NV0000_CTRL_CMD_DIAG_SET_LOCK_METER_STATE + * + * This command sets the current lock meter logging state. + * + * state + * This parameter specifies the new state of the lock metering mechanism. + * Legal state values are: + * NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_DISABLE + * This value disables lock metering. + * NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_ENABLE + * This value enables lock metering. + * NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_RESET + * This value resets, or clears, all lock metering state. Lock + * metering must be disabled prior to attempting a reset. + * bCircularBuffer + * This parameter specifies type of buffer. + * Possible values are: + * TRUE + * For circular buffer. + * FALSE + * For sequential buffer. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV0000_CTRL_CMD_DIAG_SET_LOCK_METER_STATE (0x481) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS { + NvU32 state; + NvBool bCircularBuffer; +} NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS; + +/* valid lock metering state values */ +#define NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_DISABLE (0x00000000) +#define NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_ENABLE (0x00000001) +#define NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_RESET (0x00000002) + +/* + * NV0000_CTRL_DIAG_LOCK_METER_ENTRY + * + * This structure represents a single lock meter entry. + * + * counter + * This field contains the number of nanonseconds elapsed since the + * the last system boot when the lock meter entry was generated. + * freq + * This field contains the CPU performance counter frequency in units + * of ticks per second. + * line + * This field contains the relevant line number. + * filename + * This field contains the relevant file name. + * tag + * This field contains a tag uniquely identifying the user of the metered + * lock operations. + * cpuNum + * This field contains the CPU number from which the metered operation + * was initiated. + * irql + * This field contains the IRQL at which the metered operation was + * initiated. + * data0 + * data1 + * data2 + * These fields contain tag-specific data. + */ +#define NV0000_CTRL_DIAG_LOCK_METER_ENTRY_FILENAME_LENGTH (0xc) + +typedef struct NV0000_CTRL_DIAG_LOCK_METER_ENTRY { + NV_DECLARE_ALIGNED(NvU64 counter, 8); + + NvU32 line; + NvU8 filename[NV0000_CTRL_DIAG_LOCK_METER_ENTRY_FILENAME_LENGTH]; + + NvU16 tag; + NvU8 cpuNum; + NvU8 irql; + + NV_DECLARE_ALIGNED(NvU64 threadId, 8); + + NvU32 data0; + NvU32 data1; + NvU32 data2; +} NV0000_CTRL_DIAG_LOCK_METER_ENTRY; + +/* valid lock meter entry tag values */ +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA (0x00000001) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_FORCED (0x00000002) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_COND (0x00000003) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_SEMA (0x00000004) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_API (0x00000010) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_API (0x00000011) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_GPUS (0x00000020) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_GPUS (0x00000021) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_DATA (0x00000100) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RMCTRL (0x00001000) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GET (0x00002000) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SET (0x00002001) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GETEX (0x00002002) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SETEX (0x00002003) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_VIDHEAP (0x00003000) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM (0x00003001) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM (0x00003002) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM_DMA (0x00003003) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM_DMA (0x00003004) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC (0x00004000) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_MEM (0x00004001) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_DUP_OBJECT (0x00004010) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CLIENT (0x00005000) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DEVICE (0x00005001) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE (0x00005002) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE_DIAG (0x00005003) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP (0x00005004) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP_CMN (0x00005005) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL (0x00005006) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_MPEG (0x00005007) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_DISP (0x00005008) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_MEMORY (0x00005009) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_FBMEM (0x0000500A) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_OBJECT (0x0000500B) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_EVENT (0x0000500C) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_IDLE_CHANNELS (0x00006000) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_BIND_CTXDMA (0x00007000) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_CTXDMA (0x00007001) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ISR (0x0000F000) +#define NV0000_CTRL_DIAG_LOCK_METER_TAG_DPC (0x0000F00F) + +/* + * NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_ENTRIES + * + * This command returns lock metering data in a fixed-sized array of entries. + * Each request will return up NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_MAX_ENTRIES + * entries. + * + * It is up to the caller to repeat these requests to retrieve the total number + * of entries reported by NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_STATE. + * + * entryCount + * This parameter returns the total number of valid entries returned + * in the entries array. This value will not exceed + * NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_MAX but may be less. + * A value of zero indicates there are no more valid entries. + * entries + * This parameter contains the storage into which lock metering entry + * data is returned. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_ENTRIES (0x485) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS_MESSAGE_ID" */ + +/* total number of entries returned */ +#define NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_MAX (0x40) + +#define NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS_MESSAGE_ID (0x85U) + +typedef struct NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS { + NvU32 entryCount; + NV_DECLARE_ALIGNED(NV0000_CTRL_DIAG_LOCK_METER_ENTRY entries[NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_MAX], 8); +} NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS; + +/* + * NV0000_CTRL_CMD_DIAG_PROFILE_RPC + * + * This command returns the RPC runtime information, and + * will only return valid when it is running inside VGX mode. + * + * rpcProfileCmd: + * RPC profiler command issued by rpc profiler utility + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_DIAG_PROFILE_RPC (0x488) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS_MESSAGE_ID" */ + +typedef struct RPC_METER_ENTRY { + NV_DECLARE_ALIGNED(NvU64 startTimeInNs, 8); + NV_DECLARE_ALIGNED(NvU64 endTimeInNs, 8); + NV_DECLARE_ALIGNED(NvU64 rpcDataTag, 8); + NV_DECLARE_ALIGNED(NvU64 rpcExtraData, 8); +} RPC_METER_ENTRY; + +#define NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS_MESSAGE_ID (0x88U) + +typedef struct NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS { + NvU32 rpcProfileCmd; +} NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS; + +#define NV0000_CTRL_PROFILE_RPC_CMD_DISABLE (0x00000000) +#define NV0000_CTRL_PROFILE_RPC_CMD_ENABLE (0x00000001) +#define NV0000_CTRL_PROFILE_RPC_CMD_RESET (0x00000002) + +/* + * NV0000_CTRL_CMD_DIAG_DUMP_RPC + * + * This command returns the RPC runtime information, which + * will be logged by NV0000_CTRL_CMD_DIAG_PROFILE_RPC command + * when running inside VGX mode. + * + * When issuing this command, the RPC profiler has to be disabled. + * + * firstEntryOffset: + * [IN] offset for first entry. + * + * outputEntryCout: + * [OUT] number of entries returned in rpcProfilerBuffer. + * + * remainingEntryCount: + * [OUT] number of entries remaining. + * + * elapsedTimeInNs: + * [OUT] runtime for the RPC profiler tool. + * + * rpcProfilerBuffer: + * [OUT] buffer to store the RPC entries + */ + +#define NV0000_CTRL_CMD_DIAG_DUMP_RPC (0x489) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_DUMP_RPC_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_DIAG_RPC_MAX_ENTRIES (100) + +#define NV0000_CTRL_DIAG_DUMP_RPC_PARAMS_MESSAGE_ID (0x89U) + +typedef struct NV0000_CTRL_DIAG_DUMP_RPC_PARAMS { + NvU32 firstEntryOffset; + NvU32 outputEntryCount; + NvU32 remainingEntryCount; + NV_DECLARE_ALIGNED(NvU64 elapsedTimeInNs, 8); + NV_DECLARE_ALIGNED(RPC_METER_ENTRY rpcProfilerBuffer[NV0000_CTRL_DIAG_RPC_MAX_ENTRIES], 8); +} NV0000_CTRL_DIAG_DUMP_RPC_PARAMS; + +/* _ctrl0000diag_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h new file mode 100644 index 0000000..1679f84 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h @@ -0,0 +1,113 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000event.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +#include "class/cl0000.h" +/* + * NV0000_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * This command sets event notification for the system events. + * + * event + * This parameter specifies the type of event to which the specified + * action is to be applied. The valid event values can be found in + * cl0000.h. + * + * action + * This parameter specifies the desired event notification action. + * Valid notification actions include: + * NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE + * This action disables event notification for the specified + * event. + * NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE + * This action enables single-shot event notification for the + * specified event. + * NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT + * This action enables repeated event notification for the + * specified event. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_CLIENT + * + */ + +#define NV0000_CTRL_CMD_EVENT_SET_NOTIFICATION (0x501) /* finn: Evaluated from "(FINN_NV01_ROOT_EVENT_INTERFACE_ID << 8) | NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS { + NvU32 event; + NvU32 action; +} NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001) +#define NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002) + +/* + * NV0000_CTRL_CMD_GET_SYSTEM_EVENT_STATUS + * + * This command returns the status of the specified system event type. + * See the description of NV01_EVENT for details on registering events. + * + * event + * This parameter specifies the event type. Valid event type values + * can be found in cl0000.h. + * status + * This parameter returns the status for a given event type. Valid + * status values can be found in cl0000.h. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_CLIENT + * + */ + +#define NV0000_CTRL_CMD_GET_SYSTEM_EVENT_STATUS (0x502) /* finn: Evaluated from "(FINN_NV01_ROOT_EVENT_INTERFACE_ID << 8) | NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS { + NvU32 event; + NvU32 status; +} NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS; + +/* _ctrl0000event_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h new file mode 100644 index 0000000..3ce0f06 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h @@ -0,0 +1,873 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000gpu.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" +#include "ctrl/ctrl0000/ctrl0000system.h" +#include "ctrl/ctrlxxxx.h" +#include "nvlimits.h" + +/* NV01_ROOT (client) GPU control commands and parameters */ + +/* + * NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS + * + * This command returns a table of attached gpuId values. + * The table is NV0000_CTRL_GPU_MAX_ATTACHED_GPUS entries in size. + * + * gpuIds[] + * This parameter returns the table of attached GPU IDs. + * The GPU ID is an opaque platform-dependent value that can be used + * with the NV0000_CTRL_CMD_GPU_GET_ID_INFO command to retrieve + * additional information about the GPU. The valid entries in gpuIds[] + * are contiguous, with a value of NV0000_CTRL_GPU_INVALID_ID indicating + * the invalid entries. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS (0x201U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_MAX_ATTACHED_GPUS 32U +#define NV0000_CTRL_GPU_INVALID_ID (0xffffffffU) + +#define NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS { + NvU32 gpuIds[NV0000_CTRL_GPU_MAX_ATTACHED_GPUS]; +} NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS; + +/* + * Deprecated. Please use NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 instead. + */ +#define NV0000_CTRL_CMD_GPU_GET_ID_INFO (0x202U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_MAX_SZNAME 128U + +#define NV0000_CTRL_NO_NUMA_NODE (-1) + +#define NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_GPU_GET_ID_INFO_PARAMS { + NvU32 gpuId; + NvU32 gpuFlags; + NvU32 deviceInstance; + NvU32 subDeviceInstance; + NV_DECLARE_ALIGNED(NvP64 szName, 8); + NvU32 sliStatus; + NvU32 boardId; + NvU32 gpuInstance; + NvS32 numaId; +} NV0000_CTRL_GPU_GET_ID_INFO_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 + * This command returns GPU instance information for the specified GPU. + * + * [in] gpuId + * This parameter should specify a valid GPU ID value. If there + * is no GPU present with the specified ID, a status of + * NV_ERR_INVALID_ARGUMENT is returned. + * [out] gpuFlags + * This parameter returns various flags values for the specified GPU. + * Valid flag values include: + * NV0000_CTRL_GPU_ID_INFO_IN_USE + * When true this flag indicates there are client references + * to the GPU in the form of device class instantiations (see + * NV01_DEVICE or NV03_DEVICE descriptions for details). + * NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE + * When true this flag indicates the GPU is linked into an + * active SLI device. + * NV0000_CTRL_GPU_ID_INFO_MOBILE + * When true this flag indicates the GPU is a mobile GPU. + * NV0000_CTRL_GPU_ID_BOOT_MASTER + * When true this flag indicates the GPU is the boot master GPU. + * NV0000_CTRL_GPU_ID_INFO_SOC + * When true this flag indicates the GPU is part of a + * System-on-Chip (SOC). + * NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED + * When ATS is enabled on the system. + * [out] deviceInstance + * This parameter returns the broadcast device instance number associated + * with the specified GPU. This value can be used to instantiate + * a broadcast reference to the GPU using the NV01_DEVICE classes. + * [out] subDeviceInstance + * This parameter returns the unicast subdevice instance number + * associated with the specified GPU. This value can be used to + * instantiate a unicast reference to the GPU using the NV20_SUBDEVICE + * classes. + * [out] sliStatus + * This parameters returns the SLI status for the specified GPU. + * Legal values for this member are described by NV0000_CTRL_SLI_STATUS. + * [out] boardId + * This parameter returns the board ID value with which the + * specified GPU is associated. Multiple GPUs can share the + * same board ID in multi-GPU configurations. + * [out] gpuInstance + * This parameter returns the GPU instance number for the specified GPU. + * GPU instance numbers are assigned in bus-probe order beginning with + * zero and are limited to one less the number of GPUs in the system. + * [out] numaId + * This parameter returns the ID of NUMA node for the specified GPU. + * In case there is no NUMA node, NV0000_CTRL_NO_NUMA_NODE is returned. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + + + +#define NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 (0x205U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS { + NvU32 gpuId; + NvU32 gpuFlags; + NvU32 deviceInstance; + NvU32 subDeviceInstance; + NvU32 sliStatus; + NvU32 boardId; + NvU32 gpuInstance; + NvS32 numaId; +} NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS; + + +/* valid flags values */ +#define NV0000_CTRL_GPU_ID_INFO_IN_USE 0:0 +#define NV0000_CTRL_GPU_ID_INFO_IN_USE_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_IN_USE_TRUE (0x00000001U) +#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE 1:1 +#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_TRUE (0x00000001U) +#define NV0000_CTRL_GPU_ID_INFO_MOBILE 2:2 +#define NV0000_CTRL_GPU_ID_INFO_MOBILE_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_MOBILE_TRUE (0x00000001U) +#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER 3:3 +#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_TRUE (0x00000001U) + + +#define NV0000_CTRL_GPU_ID_INFO_SOC 5:5 +#define NV0000_CTRL_GPU_ID_INFO_SOC_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_SOC_TRUE (0x00000001U) +#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED 6:6 +#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE (0x00000001U) + +/* + * NV0000_CTRL_CMD_GPU_GET_INIT_STATUS + * + * This command returns the initialization status for the specified GPU, and + * will return NV_ERR_INVALID_STATE if called prior to GPU + * initialization. + * + * gpuId + * This parameter should specify a valid GPU ID value. If there + * is no GPU present with the specified ID, a status of + * NV_ERR_INVALID_ARGUMENT is returned. + * status + * This parameter returns the status code identifying the initialization + * state of the GPU. If this parameter has the value NV_OK, + * then no errors were detected during GPU initialization. Otherwise, this + * parameter specifies the top-level error that was detected during GPU + * initialization. Note that a value of NV_OK only means that + * no errors were detected during the actual GPU initialization, and other + * errors may have occurred that prevent the GPU from being attached or + * accessible via the NV01_DEVICE or NV20_SUBDEVICE classes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV0000_CTRL_CMD_GPU_GET_INIT_STATUS (0x203U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS { + NvU32 gpuId; + NvU32 status; +} NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS + * + * This command returns a mask of valid device IDs. These device IDs + * can be used to instantiate the NV01_DEVICE_0 class (see NV01_DEVICE_0 + * for more information). + * + * deviceIds + * This parameter returns the mask of valid device IDs. Each enabled bit + * in the mask corresponds to a valid device instance. Valid device + * instances can be used to initialize the NV0080_ALLOC_PARAMETERS + * structure when using NvRmAlloc to instantiate device handles. The + * number of device IDs will not exceed NV_MAX_DEVICES in number. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS (0x204U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS { + NvU32 deviceIds; +} NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS; + + + +/* + * NV0000_CTRL_CMD_GPU_GET_PROBED_IDS + * + * This command returns a table of probed gpuId values. + * The table is NV0000_CTRL_GPU_MAX_PROBED_GPUS entries in size. + * + * gpuIds[] + * This parameter returns the table of probed GPU IDs. + * The GPU ID is an opaque platform-dependent value that can + * be used with the NV0000_CTRL_CMD_GPU_ATTACH_IDS and + * NV0000_CTRL_CMD_GPU_DETACH_ID commands to attach and detach + * the GPU. + * The valid entries in gpuIds[] are contiguous, with a value + * of NV0000_CTRL_GPU_INVALID_ID indicating the invalid entries. + * excludedGpuIds[] + * This parameter returns the table of excluded GPU IDs. + * An excluded GPU ID is an opaque platform-dependent value that + * can be used with NV0000_CTRL_CMD_GPU_GET_PCI_INFO and + * NV0000_CTRL_CMD_GPU_GET_UUID_INFO. + * The valid entries in excludedGpuIds[] are contiguous, with a value + * of NV0000_CTRL_GPU_INVALID_ID indicating the invalid entries. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0000_CTRL_CMD_GPU_GET_PROBED_IDS (0x214U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_MAX_PROBED_GPUS NV_MAX_DEVICES + +#define NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS { + NvU32 gpuIds[NV0000_CTRL_GPU_MAX_PROBED_GPUS]; + NvU32 excludedGpuIds[NV0000_CTRL_GPU_MAX_PROBED_GPUS]; +} NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_GET_PCI_INFO + * + * This command takes a gpuId and returns PCI bus information about + * the device. If the OS does not support returning PCI bus + * information, this call will return NV_ERR_NOT_SUPPORTED + * + * gpuId + * This parameter should specify a valid GPU ID value. If there + * is no GPU present with the specified ID, a status of + * NV_ERR_INVALID_ARGUMENT is returned. + * + * domain + * This parameter returns the PCI domain of the GPU. + * + * bus + * This parameter returns the PCI bus of the GPU. + * + * slot + * This parameter returns the PCI slot of the GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_GPU_GET_PCI_INFO (0x21bU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID (0x1BU) + +typedef struct NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS { + NvU32 gpuId; + NvU32 domain; + NvU16 bus; + NvU16 slot; +} NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_ATTACH_IDS + * + * This command attaches the GPUs with the gpuIds matching those in + * the table provided by the client. + * The table is NV0000_CTRL_GPU_MAX_PROBED_GPUS entries in size. + * + * gpuIds[] + * This parameter holds the table of gpuIds to attach. At least + * one gpuId must be specified; clients may use the special + * gpuId value NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS to indicate + * that all probed GPUs are to be attached. + * The entries in gpuIds[] must be contiguous, with a value of + * NV0000_CTRL_GPU_INVALID_ID to indicate the first invalid + * entry. + * If one or more of the gpuId values do not specify a GPU found + * in the system, the NV_ERR_INVALID_ARGUMENT error + * status is returned. + * + * failedId + * If NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS is specified and + * a GPU cannot be attached, the NV0000_CTRL_CMD_GPU_ATTACH_IDS + * command returns an error code and saves the failing GPU's + * gpuId in this field. + * + * If a table of gpuIds is provided, these gpuIds will be validated + * against the RM's table of probed gpuIds and attached in turn, + * if valid; if NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS is used, all + * probed gpuIds will be attached, in the order the associated GPUs + * were probed in by the RM. + * + * If a gpuId fails to attach, this gpuId is stored in the failedId + * field. Any GPUs attached by the command prior the failure are + * detached. + * + * If multiple clients use NV0000_CTRL_CMD_GPU_ATTACH_IDS to attach + * a gpuId, the RM ensures that the gpuId won't be detached until + * all clients have issued a call to NV0000_CTRL_CMD_GPU_DETACH_IDS + * to detach the gpuId (or have terminated). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OPERATING_SYSTEM + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_IRQ_EDGE_TRIGGERED + * NV_ERR_IRQ_NOT_FIRING + */ +#define NV0000_CTRL_CMD_GPU_ATTACH_IDS (0x215U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS (0x0000ffffU) + +#define NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV0000_CTRL_GPU_ATTACH_IDS_PARAMS { + NvU32 gpuIds[NV0000_CTRL_GPU_MAX_PROBED_GPUS]; + NvU32 failedId; +} NV0000_CTRL_GPU_ATTACH_IDS_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_DETACH_IDS + * + * This command detaches the GPUs with the gpuIds matching those in + * the table provided by the client. + * The table is NV0000_CTRL_GPU_MAX_ATTACHED_GPUS entries in size. + * + * gpuIds[] + * This parameter holds the table of gpuIds to detach. At least + * one gpuId must be specified; clients may use the special + * gpuId NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS to indicate that + * all attached GPUs are to be detached. + * The entries in gpuIds[] must be contiguous, with a value of + * NV0000_CTRL_GPU_INVALID_ID to indicate the first invalid + * entry. + * If one or more of the gpuId values do not specify a GPU found + * in the system, the NV_ERR_INVALID_ARGUMENT error + * status is returned. + * + * If a table of gpuIds is provided, these gpuIds will be validated + * against the RM's list of attached gpuIds; each valid gpuId is + * detached immediately if it's no longer in use (i.e. if there are + * no client references to the associated GPU in the form of + * device class instantiations (see the NV01_DEVICE or NV03_DEVICE + * descriptions for details)) and if no other client still requires + * the associated GPU to be attached. + * + * If a given gpuId can't be detached immediately, it will instead + * be detached when the last client reference is freed or when + * the last client that issued NV0000_CTRL_CMD_GPU_ATTACH_IDS for + * this gpuId either issues NV0000_CTRL_CMD_GPU_DETACH_IDS or exits + * without detaching the gpuId explicitly. + * + * Clients may use the NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS command + * to obtain a table of the attached gpuIds. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OPERATING_SYSTEM + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_GPU_DETACH_IDS (0x216U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS (0x0000ffffU) + +#define NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV0000_CTRL_GPU_DETACH_IDS_PARAMS { + NvU32 gpuIds[NV0000_CTRL_GPU_MAX_ATTACHED_GPUS]; +} NV0000_CTRL_GPU_DETACH_IDS_PARAMS; + + + +/* + * NV0000_CTRL_CMD_GPU_GET_SVM_SIZE + * + * This command is used to get the SVM size. + * + * gpuId + * This parameter uniquely identifies the GPU whose associated + * SVM size is to be returned. The value of this field must + * match one of those in the table returned by + * NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS + * + * SvmSize + * SVM size is returned in this. + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + * + */ +#define NV0000_CTRL_CMD_GPU_GET_SVM_SIZE (0x240U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID (0x40U) + +typedef struct NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS { + NvU32 gpuId; + NvU32 svmSize; +} NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS; + + + +/* + * NV0000_CTRL_CMD_GPU_GET_UUID_INFO + * + * This command returns requested information pertaining to the GPU + * specified by the GPU UUID passed in. + * + * Generally only GPUs that have been attached are visible to this call. Therefore + * queries on unattached GPUs will fail with NV_ERR_OBJECT_NOT_FOUND. However, + * a query for a SHA1 UUID may succeed for an unattached GPU in cases where the GID + * is cached, such as an excluded GPU. + * + * gpuGuid (INPUT) + * The GPU UUID of the gpu whose parameters are to be returned. Refer to + * NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information. + * + * flags (INPUT) + * The _FORMAT* flags designate ascii string format or a binary format. + * + * The _TYPE* flags designate either SHA-1-based (32-hex-character) or + * SHA-256-based (64-hex-character). + * + * gpuId (OUTPUT) + * The GPU ID of the GPU identified by gpuGuid. Refer to + * NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information. + * + * deviceInstance (OUTPUT) + * The device instance of the GPU identified by gpuGuid. Refer to + * NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information. + * + * subdeviceInstance (OUTPUT) + * The subdevice instance of the GPU identified by gpuGuid. Refer to + * NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * + */ +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO (0x274U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID" */ + +/* maximum possible number of bytes of GID information */ +#define NV0000_GPU_MAX_GID_LENGTH (0x00000100U) + +#define NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID (0x74U) + +typedef struct NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS { + NvU8 gpuUuid[NV0000_GPU_MAX_GID_LENGTH]; + NvU32 flags; + NvU32 gpuId; + NvU32 deviceInstance; + NvU32 subdeviceInstance; +} NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS; + +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT 1:0 +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_ASCII (0x00000000U) +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_BINARY (0x00000002U) + +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE 2:2 +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA1 (0x00000000U) +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA256 (0x00000001U) + +/* + * NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID + * + * This command returns the GPU UUID for the provided GPU ID. + * Note that only GPUs that have been attached are visible to this call. + * Therefore queries on unattached GPUs will fail + * with NV_ERR_OBJECT_NOT_FOUND. + * + * gpuId (INPUT) + * The GPU ID whose parameters are to be returned. Refer to + * NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information. + * + * flags (INPUT) + * + * NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII + * This value is used to request the GPU UUID in ASCII format. + * NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY + * This value is used to request the GPU UUID in binary format. + * + * NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1 + * This value is used to request that the GPU UUID value + * be SHA1-based (32-hex-character). + * NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256 + * This value is used to request that the GPU UUID value + * be SHA256-based (64-hex-character). + * + * gpuUuid[NV0000_GPU_MAX_GID_LENGTH] (OUTPUT) + * The GPU UUID of the GPU identified by GPU ID. Refer to + * NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information. + * + * uuidStrLen (OUTPUT) + * The length of the UUID returned which is related to the format that + * was requested using flags. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_OPERATING_SYSTEM + */ +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID (0x275U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID (0x75U) + +typedef struct NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS { + NvU32 gpuId; + NvU32 flags; + NvU8 gpuUuid[NV0000_GPU_MAX_GID_LENGTH]; + NvU32 uuidStrLen; +} NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS; + +/* valid format values */ +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT 1:0 +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII (0x00000000U) +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY (0x00000002U) + +/*valid type values*/ +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE 2:2 +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1 (0x00000000U) +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256 (0x00000001U) + + + +/* + * NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE + * + * This command is used to enter or exit the so called "drain" state. + * When this state is enabled, the existing clients continue executing + * as usual, however no new client connections are allowed. + * This is done in order to "drain" the system of the running clients + * in preparation to selectively powering down the GPU. + * No GPU can enter a bleed state if that GPU is in an SLI group. + * In that case, NV_ERR_IN_USE is returned. + * Requires administrator privileges. + * + * It is expected, that the "drain" state will be eventually deprecated + * and replaced with another mechanism to quiesce a GPU (Bug 1718113). + * + * gpuId (INPUT) + * This parameter should specify a valid GPU ID value. If there + * is no GPU present with the specified ID, a status of + * NV_ERR_INVALID_ARGUMENT is returned. + * newState (INPUT) + * This input parameter is used to enter or exit the "drain" + * software state of the GPU specified by the gpuId parameter. + * Possible values are: + * NV0000_CTRL_GPU_DRAIN_STATE_ENABLED + * NV0000_CTRL_GPU_DRAIN_STATE_DISABLED + * flags (INPUT) + * NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE + * if set, upon reaching quiescence, a request will be made to + * the OS to "forget" the PCI device associated with the + * GPU specified by the gpuId parameter, in case such a request + * is supported by the OS. Otherwise, NV_ERR_NOT_SUPPORTED + * will be returned. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_IN_USE + */ + +#define NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE (0x278U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID" */ + +/* Possible values of newState */ +#define NV0000_CTRL_GPU_DRAIN_STATE_DISABLED (0x00000000U) +#define NV0000_CTRL_GPU_DRAIN_STATE_ENABLED (0x00000001U) + +/* Defined bits for the "flags" argument */ +#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE (0x00000001U) +#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE (0x00000002U) + +#define NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID (0x78U) + +typedef struct NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS { + NvU32 gpuId; + NvU32 newState; + NvU32 flags; +} NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE + * + * gpuId (INPUT) + * This parameter should specify a valid GPU ID value. If there + * is no GPU present with the specified ID, a status of + * NVOS_STATUS_ERROR_INVALID_ARGUMENT is returned. + * drainState (OUTPUT) + * This parameter returns a value indicating if the "drain" + * state is currently enabled or not for the specified GPU. See the + * description of NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE. + * Possible values are: + * NV0000_CTRL_GPU_DRAIN_STATE_ENABLED + * NV0000_CTRL_GPU_DRAIN_STATE_DISABLED + * flags (OUTPUT) + * NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE + * if set, upon reaching quiesence, the GPU device will be + * removed automatically from the kernel space, similar + * to what writing "1" to the sysfs "remove" node does. + * NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE + * after removing the GPU, also disable the parent bridge's + * PCIe link. This flag can only be set in conjunction with + * NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE, and then + * only when the GPU is already idle (not attached). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE (0x279U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID (0x79U) + +typedef struct NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS { + NvU32 gpuId; + NvU32 drainState; + NvU32 flags; +} NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_DISCOVER + * + * This request asks the OS to scan the PCI tree or a sub-tree for GPUs, + * that are not yet known to the OS, and to make them available for use. + * If all of domain:bus:slot.function are zeros, the entire tree is scanned, + * otherwise the parameters identify the bridge device, that roots the + * subtree to be scanned. + * Requires administrator privileges. + * + * domain (INPUT) + * PCI domain of the bridge + * bus (INPUT) + * PCI bus of the bridge + * slot (INPUT) + * PCI slot of the bridge + * function (INPUT) + * PCI function of the bridge + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_DEVICE + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_OPERATING_SYSTEM + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_GPU_DISCOVER (0x27aU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | 0x7A" */ + +typedef struct NV0000_CTRL_GPU_DISCOVER_PARAMS { + NvU32 domain; + NvU8 bus; + NvU8 slot; + NvU8 function; +} NV0000_CTRL_GPU_DISCOVER_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE + * + * This command is used to get the content of the MemOp (CUDA Memory Operation) + * enablement mask, which can be overridden by using the MemOpOverride RegKey. + * + * The enableMask member must be treated as a bitmask, where each bit controls + * the enablement of a feature. + * + * So far, the only feature which is defined controls to whole MemOp APIs. + * + * Possible status values returned are: + * NV_OK + * + */ +#define NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE (0x27bU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID (0x7BU) + +typedef struct NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS { + NvU32 enableMask; +} NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS; + +#define NV0000_CTRL_GPU_FLAGS_MEMOP_ENABLE (0x00000001U) + + + +/* + * NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT + * + * This privileged command is used to disable initialization for the NVLinks + * provided in the mask. + * + * The mask must be applied before the GPU is attached. DISABLE_NVLINK_INIT + * is an NOP for non-NVLink GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_DEVICE + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_INVALID_STATE + * NV_ERR_IN_USE + * + */ +#define NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT (0x281U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS { + NvU32 gpuId; + NvU32 mask; + NvBool bSkipHwNvlinkDisable; +} NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS; + + +#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA 0x00000175U +#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN 6U +#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT 5U + +/* + * NV0000_CTRL_CMD_GPU_LEGACY_CONFIG + * + * Path to use legacy RM GetConfig/Set API. This API is being phased out. + */ +#define NV0000_CTRL_CMD_GPU_LEGACY_CONFIG (0x282U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID (0x82U) + +typedef struct NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS { + NvHandle hContext; /* [in] - Handle of object to perform operation on (Device, Subdevice, etc) */ + NvU32 opType; /* [in] - Type of API */ + NvV32 index; /* [in] - command type */ + NvU32 dataType; /* [out] - data union type */ + + union { + struct { + NvU32 newValue; + NvU32 oldValue; + } configSet; + struct { + NvU8 paramData[NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA]; + NvU32 paramSize; + } configEx; + struct { + NvU32 propertyId; + NvU32 propertyIn[NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN]; + NvU32 propertyOut[NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT]; + } reservedProperty; + } data; +} NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS; + +#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET (0x00000001U) +#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET_EX (0x00000002U) +#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET_EX (0x00000003U) +#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_RESERVED (0x00000004U) + +/* + * NV0000_CTRL_CMD_IDLE_CHANNELS + */ +#define NV0000_CTRL_CMD_IDLE_CHANNELS (0x283U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID (0x83U) + +typedef struct NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS { + NvHandle hDevice; + NvHandle hChannel; + NvV32 numChannels; + /* C form: NvP64 phClients NV_ALIGN_BYTES(8); */ + NV_DECLARE_ALIGNED(NvP64 phClients, 8); + /* C form: NvP64 phDevices NV_ALIGN_BYTES(8); */ + NV_DECLARE_ALIGNED(NvP64 phDevices, 8); + /* C form: NvP64 phChannels NV_ALIGN_BYTES(8); */ + NV_DECLARE_ALIGNED(NvP64 phChannels, 8); + NvV32 flags; + NvV32 timeout; +} NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS; + +#define NV0000_CTRL_GPU_IMAGE_TYPE_GSP (0x00000001U) +#define NV0000_CTRL_GPU_IMAGE_TYPE_GSP_LOG (0x00000002U) + +/* + * NV0000_CTRL_CMD_PUSH_GSP_UCODE + * + * This command is used to push the GSP ucode into RM. + * This function is used only on VMware + * + * Possible status values returned are: + * NV_OK The sent data is stored successfully + * NV_ERR_INVALID_ARGUMENT if the arguments are not proper + * NV_ERR_NO_MEMORY if memory allocation failed + * NV_ERR_NOT_SUPPORTED if function is invoked on non-GSP setup or any + * setup other than VMware host + * + */ +#define NV0000_CTRL_CMD_PUSH_GSP_UCODE (0x285) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS_MESSAGE_ID (0x85U) + +typedef struct NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS { + NvU8 image; + NV_DECLARE_ALIGNED(NvU64 totalSize, 8); + NV_DECLARE_ALIGNED(NvP64 pData, 8); +} NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS; +/* _ctrl0000gpu_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h new file mode 100644 index 0000000..6f8ff13 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h @@ -0,0 +1,255 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000gpuacct.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +/* + * NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE + * + * This command is used to enable or disable the per process GPU accounting. + * This is part of GPU's software state and will persist if persistent + * software state is enabled. Refer to the description of + * NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE for more information. + * + * gpuId + * This parameter should specify a valid GPU ID value. Refer to the + * description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more + * information. If there is no GPU present with the specified ID, + * a status of NV_ERR_INVALID_ARGUMENT is returned. + * pid + * This input parameter specifies the process id of the process for which + * the accounting state needs to be set. + * In case of VGX host, this parameter specifies VGPU plugin(VM) pid. This + * parameter is set only when this RM control is called from VGPU plugin, + * otherwise it is zero meaning set/reset the accounting state for the + * specified GPU. + * newState + * This input parameter is used to enable or disable the GPU accounting. + * Possible values are: + * NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED + * NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE (0xb01) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID" */ + +/* Possible values of persistentSwState */ +#define NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED (0x00000000) +#define NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED (0x00000001) + +#define NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS { + NvU32 gpuId; + NvU32 pid; + NvU32 newState; +} NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS; + +/* + * NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_STATE + * + * This command is used to get the current state of GPU accounting. + * + * gpuId + * This parameter should specify a valid GPU ID value. Refer to the + * description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more + * information. If there is no GPU present with the specified ID, + * a status of NV_ERR_INVALID_ARGUMENT is returned. + * pid + * This input parameter specifies the process id of the process of which the + * accounting state needs to be queried. + * In case of VGX host, this parameter specifies VGPU plugin(VM) pid. This + * parameter is set only when this RM control is called from VGPU plugin, + * otherwise it is zero meaning the accounting state needs to be queried for + * the specified GPU. + * state + * This parameter returns a value indicating if per process GPU accounting + * is currently enabled or not for the specified GPU. See the + * description of NV0000_CTRL_CMD_GPU_SET_ACCOUNTING_STATE. + * Possible values are: + * NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED + * NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_STATE (0xb02) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS { + NvU32 gpuId; + NvU32 pid; + NvU32 state; +} NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS; + +/* + * NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS + * + * This command returns GPU accounting data for the process. + * + * gpuId + * This parameter should specify a valid GPU ID value. Refer to the + * description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more + * information. If there is no GPU present with the specified ID, + * a status of NV_ERR_INVALID_ARGUMENT is returned. + * pid + * This parameter specifies the PID of the process for which information is + * to be queried. + * In case of VGX host, this parameter specifies VGPU plugin(VM) pid inside + * which the subPid is running. This parameter is set to VGPU plugin pid + * when this RM control is called from VGPU plugin. + * subPid + * In case of VGX host, this parameter specifies the PID of the process for + * which information is to be queried. In other cases, it is zero. + * gpuUtil + * This parameter returns the average GR utilization during the process's + * lifetime. + * fbUtil + * This parameter returns the average FB bandwidth utilization during the + * process's lifetime. + * maxFbUsage + * This parameter returns the maximum FB allocated (in bytes) by the process. + * startTime + * This parameter returns the time stamp value in micro seconds at the time + * process started utilizing GPU. + * stopTime + * This parameter returns the time stamp value in micro seconds at the time + * process stopped utilizing GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_GPUACCT_GET_PROC_ACCOUNTING_INFO (0xb03) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS { + NvU32 gpuId; + NvU32 pid; + NvU32 subPid; + NvU32 gpuUtil; + NvU32 fbUtil; + NV_DECLARE_ALIGNED(NvU64 maxFbUsage, 8); + NV_DECLARE_ALIGNED(NvU64 startTime, 8); + NV_DECLARE_ALIGNED(NvU64 endTime, 8); +} NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS; + +/* + * NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_PIDS + * + * This command is used to get the PIDS of processes with accounting + * information in the driver. + * + * gpuId + * This parameter should specify a valid GPU ID value. Refer to the + * description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more + * information. If there is no GPU present with the specified ID, + * a status of NV_ERR_INVALID_ARGUMENT is returned. + * pid + * This input parameter specifies the process id of the process of which the + * information needs to be queried. + * In case of VGX host, this parameter specifies VGPU plugin(VM) pid. This + * parameter is set only when this RM control is called from VGPU plugin, + * otherwise it is zero meaning get the pid list of the all the processes + * running on the specified GPU. + * pidTbl + * This parameter returns the table of all PIDs for which driver has + * accounting info. + * pidCount + * This parameter returns the number of entries in the PID table. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_PIDS (0xb04) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_MESSAGE_ID" */ + +/* max size of pidTable */ +#define NV0000_GPUACCT_PID_MAX_COUNT 4000 + +#define NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS { + NvU32 gpuId; + NvU32 pid; + NvU32 pidTbl[NV0000_GPUACCT_PID_MAX_COUNT]; + NvU32 pidCount; +} NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS; + +/* + * NV0000_CTRL_CMD_GPUACCT_CLEAR_ACCOUNTING_DATA + * + * This command is used to clear previously collected GPU accounting data. This + * will have no affect on data for the running processes, accounting data for + * these processes will not be cleared and will still be logged for these + * processes. In order to clear ALL accounting data, accounting needs to be + * disabled using NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE before executing + * this command. + * + * gpuId + * This parameter should specify a valid GPU ID value. Refer to the + * description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more + * information. If there is no GPU present with the specified ID, + * a status of NV_ERR_INVALID_ARGUMENT is returned. + * pid + * This input parameter specifies the process id of the process for which + * the accounting data needs to be cleared. + * In case of VGX host, this parameter specifies VGPU plugin(VM) pid for + * which the accounting data needs to be cleared. This parameter is set only + * when this RM control is called from VGPU plugin, otherwise it is zero + * meaning clear the accounting data of processes running on baremetal + * system. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ + +#define NV0000_CTRL_CMD_GPUACCT_CLEAR_ACCOUNTING_DATA (0xb05) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS { + NvU32 gpuId; + NvU32 pid; +} NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS; + + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h new file mode 100644 index 0000000..2df6c42 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h @@ -0,0 +1,101 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000gsync.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +#include "class/cl30f1.h" +/* NV01_ROOT (client) system controller control commands and parameters */ + +/* + * NV0000_CTRL_CMD_GSYNC_GET_ATTACHED_IDS + * + * This command returns a table of attached gsyncId values. + * The table is NV0000_CTRL_GSYNC_MAX_ATTACHED_GSYNCS entries in size. + * + * gsyncIds[] + * This parameter returns the table of attached gsync IDs. + * The gsync ID is an opaque platform-dependent value that + * can be used with the NV0000_CTRL_CMD_GSYNC_GET_ID_INFO command to + * retrieve additional information about the gsync device. + * The valid entries in gsyncIds[] are contiguous, with a value + * of NV0000_CTRL_GSYNC_INVALID_ID indicating the invalid entries. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV0000_CTRL_CMD_GSYNC_GET_ATTACHED_IDS (0x301) /* finn: Evaluated from "(FINN_NV01_ROOT_GSYNC_INTERFACE_ID << 8) | NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS { + NvU32 gsyncIds[NV30F1_MAX_GSYNCS]; +} NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS; + +/* this value marks entries in gsyncIds[] as invalid */ +#define NV0000_CTRL_GSYNC_INVALID_ID (0xffffffff) + +/* + * NV0000_CTRL_CMD_GSYNC_GET_ID_INFO + * + * This command returns gsync instance information for the + * specified gsync device. + * + * gsyncId + * This parameter should specify a valid gsync ID value. + * If there is no gsync present with the specified ID, a + * status of NV_ERR_INVALID_ARGUMENT is returned. + * gsyncFlags + * This parameter returns the current state of the gsync device. + * gsyncInstance + * This parameter returns the instance number associated with the + * specified gsync. This value can be used to instantiate + * a reference to the gsync using one of the NV30_GSYNC + * classes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_GSYNC_GET_ID_INFO (0x302) /* finn: Evaluated from "(FINN_NV01_ROOT_GSYNC_INTERFACE_ID << 8) | NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS { + NvU32 gsyncId; + NvU32 gsyncFlags; + NvU32 gsyncInstance; +} NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS; + +/* _ctrl0000gsync_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h new file mode 100644 index 0000000..41a4954 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h @@ -0,0 +1,636 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000nvd.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +/* NV01_ROOT (client) nvd control commands and parameters */ + +/* + * NV0080_CTRL_NVD_DUMP_COMPONENT + * + * The following dump components are used to describe legal ranges in + * commands below: + * + * NV0080_CTRL_CMD_NVD_DUMP_COMPONENT_SYS + * This is the system dump component. + * NV0080_CTRL_CMD_NVD_DUMP_COMPONENT_NVLOG + * This is the nvlog dump component. + * NV0080_CTRL_CMD_NVD_DUMP_COMPONENT_RESERVED + * This component is reserved. + * + * See nvdump.h for more information on dump component values. + */ +#define NV0000_CTRL_NVD_DUMP_COMPONENT_SYS (0x400) +#define NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG (0x800) +#define NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED (0xB00) + +/* + * NV0000_CTRL_CMD_NVD_GET_DUMP_SIZE + * + * This command gets the expected dump size of a particular system + * dump component. Note that events that occur between this command + * and a later NV0000_CTRL_CMD_NVD_GET_DUMP command could alter the size of + * the buffer required. + * + * component + * This parameter specifies the system dump component for which the + * dump size is desired. Legal values for this parameter must + * be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_SYS and + * less than NV0000_CTRL_NVD_GET_DUMP_COMPONENT_NVLOG. + * size + * This parameter returns the expected size in bytes. The maximum + * value of this call is NV0000_CTRL_NVD_MAX_DUMP_SIZE. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT if components are invalid. + */ + +#define NV0000_CTRL_CMD_NVD_GET_DUMP_SIZE (0x601) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS { + NvU32 component; + NvU32 size; +} NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS; + +/* Max size that a GET_DUMP_SIZE_PARAMS call can return */ +#define NV0000_CTRL_NVD_MAX_DUMP_SIZE (1000000) + +/* + * NV0000_CTRL_CMD_NVD_GET_DUMP + * + * This command gets a dump of a particular system dump component. If triggers + * is non-zero, the command waits for the trigger to occur before it returns. + * + * pBuffer + * This parameter points to the buffer for the data. + * component + * This parameter specifies the system dump component for which the + * dump is to be retrieved. Legal values for this parameter must + * be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_SYS and + * less than NV0000_CTRL_NVD_GET_DUMP_COMPONENT_NVLOG. + * size + * On entry, this parameter specifies the maximum length for + * the returned data. On exit, it specifies the number of bytes + * returned. + * + * Possible status values returned are: + * NV_OK + * NVOS_ERROR_INVALID_ARGUMENT if components are invalid. + * NVOS_ERROR_INVALID_ADDRESS if pBuffer is invalid + * NVOS_ERROR_INVALID_???? if the buffer was too small + */ +#define NV0000_CTRL_CMD_NVD_GET_DUMP (0x602) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_NVD_GET_DUMP_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pBuffer, 8); + NvU32 component; + NvU32 size; +} NV0000_CTRL_NVD_GET_DUMP_PARAMS; + +/* + * NV0000_CTRL_CMD_NVD_GET_TIMESTAMP + * + * This command returns the current value of the timestamp used + * by the RM in NvDebug dumps. It is provided to keep the RM and NvDebug + * clients on the same time base. + * + * cpuClkId + * See also NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO + * This parameter specifies the source of the CPU clock. Legal values for + * this parameter include: + * NV0000_NVD_CPU_TIME_CLK_ID_DEFAULT and NV0000_NVD_CPU_TIME_CLK_ID_OSTIME + * This clock id will provide real time in microseconds since 00:00:00 UTC on January 1, 1970. + * It is calculated as follows: + * (seconds * 1000000) + uSeconds + * NV0000_NVD_CPU_TIME_CLK_ID_PLATFORM_API + * This clock id will provide time stamp that is constant-rate, high + * precision using platform API that is also available in the user mode. + * NV0000_NVD_CPU_TIME_CLK_ID_TSC + * This clock id will provide time stamp using CPU's time stamp counter. + * + * timestamp + * Retrieved timestamp + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_NVD_CPU_TIME_CLK_ID_DEFAULT (0x00000000) +#define NV0000_NVD_CPU_TIME_CLK_ID_OSTIME (0x00000001) +#define NV0000_NVD_CPU_TIME_CLK_ID_TSC (0x00000002) +#define NV0000_NVD_CPU_TIME_CLK_ID_PLATFORM_API (0x00000003) + +#define NV0000_CTRL_CMD_NVD_GET_TIMESTAMP (0x603) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS { + NV_DECLARE_ALIGNED(NvU64 timestamp, 8); + NvU8 cpuClkId; +} NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS; + +/* + * NV0000_CTRL_CMD_NVD_GET_NVLOG_INFO + * + * This command gets the current state of the NvLog buffer system. + * + * component (in) + * This parameter specifies the system dump component for which the + * NvLog info is desired. Legal values for this parameter must + * be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG and + * less than NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED. + * version (out) + * This parameter returns the version of the Nvlog subsystem. + * runtimeSizes (out) + * This parameter returns the array of sizes for all supported printf + * specifiers. This information is necessary to know how many bytes + * to decode when given a certain specifier (such as %d). + * The following describes the contents of each array entry: + * NV0000_CTRL_NVD_RUNTIME_SIZE_UNUSED + * This array entry has special meaning and is unused in the + * runtimeSizes array. + * NV0000_CTRL_NVD_RUNTIME_SIZE_INT + * This array entry returns the size of integer types for use in + * interpreting the %d, %u, %x, %X, %i, %o specifiers. + * NV0000_CTRL_NVD_RUNTIME_SIZE_LONG_LONG + * This array entry returns the size of long long integer types for + * using in interpreting the %lld, %llu, %llx, %llX, %lli, %llo + * specifiers. + * NV0000_CTRL_NVD_RUNTIME_SIZE_STRING + * This array entry returns zero as strings are not allowed. + * NV0000_CTRL_NVD_RUNTIME_SIZE_PTR + * This array entry returns the size of the pointer type for use + * in interpreting the %p specifier. + * NV0000_CTRL_NVD_RUNTIME_SIZE_CHAR + * This array entry returns the size of the char type for use in + * intpreting the %c specifier. + * NV0000_CTRL_NVD_RUNTIME_SIZE_FLOAT + * This array entry returns the size of the float types for use in + * in interpreting the %f, %g, %e, %F, %G, %E specifiers. + * All remaining entries are reserved and return 0. + * printFlags (out) + * This parameter returns the flags of the NvLog system. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_BUFFER_FLAGS + * See NV0000_CTRL_CMD_NVD_GET_NVLOG_BUF_INFO for more details. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_BUFFER_SIZE + * This field returns the buffer size in KBytes. A value of zero + * is returned when logging is disabled. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP + * This field returns the format of the timestamp. Legal values + * for this parameter include: + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP_NONE + * This value indicates no timestamp. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP_32BIT + * This value indicates a 32-bit timestamp. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP_64BIT + * This value indicates a 64-bit timestamp. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP_32BIT_DIFF + * This value indicates a 32-bit differential timestamp. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_RESERVED + * This field is reserved. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_RUNTIME_LEVEL + * This field returns the lowest debug level for which logging + * is enabled by default. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_INIT + * This field indicates if logging for the specified component has + * been initialized. Legal values for this parameter include: + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_INIT_NO + * This value indicates NvLog is uninitialized. + * NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_INIT_YES + * This value indicates NvLog has been initialized. + * signature (out) + * This parameter is the signature of the database + * required to decode these logs, autogenerated at buildtime. + * bufferTags (out) + * This parameter identifies the buffer tag used during allocation + * or a value of '0' if buffer is unallocated for each possible + * buffer. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT if components are invalid. + */ +#define NV0000_CTRL_CMD_NVD_GET_NVLOG_INFO (0x604) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS_MESSAGE_ID" */ + +/* maximum size of the runtimeSizes array */ +#define NV0000_CTRL_NVD_MAX_RUNTIME_SIZES (16) + +/* size of signature parameter */ +#define NV0000_CTRL_NVD_SIGNATURE_SIZE (4) + +/* Maximum number of buffers */ +#define NV0000_CTRL_NVD_MAX_BUFFERS (256) + +#define NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS { + NvU32 component; + NvU32 version; + NvU8 runtimeSizes[NV0000_CTRL_NVD_MAX_RUNTIME_SIZES]; + NvU32 printFlags; + NvU32 signature[NV0000_CTRL_NVD_SIGNATURE_SIZE]; + NvU32 bufferTags[NV0000_CTRL_NVD_MAX_BUFFERS]; +} NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS; + +/* runtimeSize array indices */ +#define NV0000_CTRL_NVD_RUNTIME_SIZE_UNUSED (0) +#define NV0000_CTRL_NVD_RUNTIME_SIZE_INT (1) +#define NV0000_CTRL_NVD_RUNTIME_SIZE_LONG_LONG (2) +#define NV0000_CTRL_NVD_RUNTIME_SIZE_STRING (3) +#define NV0000_CTRL_NVD_RUNTIME_SIZE_PTR (4) +#define NV0000_CTRL_NVD_RUNTIME_SIZE_CHAR (5) +#define NV0000_CTRL_NVD_RUNTIME_SIZE_FLOAT (6) + +/* printFlags fields and values */ +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_INFO 7:0 +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE 23:8 +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DISABLE (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DEFAULT (0x00000004) +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_RUNTIME_LEVEL 28:25 +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP 30:29 +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_NONE (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32 (0x00000001) +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_64 (0x00000002) +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32_DIFF (0x00000003) +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED 31:31 +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_NO (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_YES (0x00000001) + +/* + * NV0000_CTRL_CMD_NVD_GET_NVLOG_BUFFER_INFO + * + * This command gets the current state of a specific buffer in the NvLog + * buffer system. + * + * component (in) + * This parameter specifies the system dump component for which the + * NvLog info is desired. Legal values for this parameter must + * be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG and + * less than NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED. + * buffer (in/out) + * This parameter specifies the buffer number from which to retrieve the + * buffer information. Valid values are 0 to (NV0000_CTRL_NVD_MAX_BUFFERS - 1). + * If the buffer is specified using the 'tag' parameter, the buffer + * number is returned through this one. + * tag (in/out) + * If this parameter is non-zero, it will be used to specify the buffer, + * instead of 'buffer' parameter. It returns the tag of the specified buffer + * size (out) + * This parameter returns the size of the specified buffer. + * flags (in/out) + * On input, this parameter sets the following behavior: + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE + * This flag controls if the nvlog system should pause output + * to this buffer. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_YES + * The buffer should be paused until another command + * unpauses this buffer. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_NO + * The buffer should not be paused. + * On output, this parameter returns the flags of a specified buffer: + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED + * This flag indicates if logging to the specified buffer is + * disabled or not. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE + * This flag indicates the buffer logging type: + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_RING + * This type value indicates logging to the buffer wraps. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_NOWRAP + * This type value indicates logging to the buffer does not wrap. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE + * This flag indicates if the buffer size is expandable. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_NO + * The buffer is not expandable. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_YES + * The buffer is expandable. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NON_PAGED + * This flag indicates if the buffer occupies non-paged or pageable + * memory. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NON_PAGED_NO + * The buffer is in pageable memory. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NON_PAGES_YES + * The buffer is in non-paged memory. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING + * This flag indicates the locking mode for the specified buffer. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_NONE + * This locking value indicates that no locking is performed. This + * locking mode is typically used for inherently single-threaded + * buffers. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_STATE + * This locking value indicates that the buffer is locked only + * during state changes and that memory copying is unlocked. This + * mode should not be used tiny buffers that overflow every write + * or two. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_FULL + * This locking value indicates the buffer is locked for the full + * duration of the write. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA + * This flag indicates if the buffer is stored in OCA dumps. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_NO + * The buffer is not included in OCA dumps. + * NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_YES + * The buffer is included in OCA dumps. + * pos (out) + * This parameter is the current position of the tracker/cursor in the + * buffer. + * overflow (out) + * This parameter is the number of times the buffer has overflowed. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT if components are invalid. + */ + +#define NV0000_CTRL_CMD_NVD_GET_NVLOG_BUFFER_INFO (0x605) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS { + NvU32 component; + NvU32 buffer; + NvU32 tag; + NvU32 size; + NvU32 flags; + NvU32 pos; + NvU32 overflow; +} NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS; + +/* flags fields and values */ +/* input */ +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE 0:0 +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_NO (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_YES (0x00000001) + +/* output */ +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED 0:0 +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_NO (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_YES (0x00000001) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE 1:1 +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_RING (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_NOWRAP (0x00000001) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE 2:2 +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_NO (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_YES (0x00000001) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED 3:3 +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_NO (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_YES (0x00000001) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING 5:4 +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_NONE (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_STATE (0x00000001) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_FULL (0x00000002) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA 6:6 +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_NO (0x00000000) +#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_YES (0x00000001) + +/* + * NV0000_CTRL_CMD_NVD_GET_NVLOG + * + * This command retrieves the specified dump block from the specified + * NvLog buffer. To retrieve the entire buffer, the caller should start + * with blockNum set to 0 and continue issuing calls with an incremented + * blockNum until the returned size value is less than + * NV0000_CTRL_NVD_NVLOG_MAX_BLOCK_SIZE. + * + * component (in) + * This parameter specifies the system dump component for which the NvLog + * dump operation is to be directed. Legal values for this parameter + * must be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG + * and less than NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED. + * buffer (in) + * This parameter specifies the NvLog buffer to dump. + * blockNum (in) + * This parameter specifies the block number for which data is to be + * dumped. + * size (in/out) + * On entry, this parameter specifies the maximum length in bytes for + * the returned data (should be set to NV0000_CTRL_NVLOG_MAX_BLOCK_SIZE). + * On exit, it specifies the number of bytes returned. + * data (out) + * This parameter returns the data for the specified block. The size + * patameter values indicates the number of valid bytes returned. + * + * Possible status values returned are: + * NV_OK + * NVOS_ERROR_INVALID_ARGUMENT if components are invalid. + */ +#define NV0000_CTRL_CMD_NVD_GET_NVLOG (0x606) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_NVLOG_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_NVLOG_MAX_BLOCK_SIZE (4000) + +#define NV0000_CTRL_NVD_GET_NVLOG_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV0000_CTRL_NVD_GET_NVLOG_PARAMS { + NvU32 component; + NvU32 buffer; + NvU32 blockNum; + NvU32 size; + NvU8 data[NV0000_CTRL_NVLOG_MAX_BLOCK_SIZE]; +} NV0000_CTRL_NVD_GET_NVLOG_PARAMS; + +/* + * NV0000_CTRL_CMD_NVD_GET_RCERR_RPT + * + * This command returns block of registers that were recorded at the time + * of an RC error for the current process. + * + * reqIdx: + * [IN] the index of the report being requested. + * index rolls over to 0. + * if the requested index is not in the circular buffer, then no data is + * transferred & either NV_ERR_INVALID_INDEX (indicating the specified + * index is not in the table) is returned. + * + * rptIdx: + * [OUT] the index of the report being returned. + * if the requested index is not in the circular buffer, then the value is + * undefined, no data istransferred & NV_ERR_INVALID_INDEX is returned. + * if the the specified index is present, but does not meet the requested + * criteria (refer to the owner & processId fields). the rptIdx will be + * set to a value that does not match the reqIdx, and no data will be + * transferred. NV_ERR_INSUFFICIENT_PERMISSIONS is still returned. + * + * gpuTag: + * [OUT] id of the GPU whose data was collected. + * + * rptTimeInNs: + * [OUT] the timestamp for when the report was created. + * + * startIdx: + * [OUT] the index of the oldest start record for the first report that + * matches the specified criteria (refer to the owner & processId + * fields). If no records match the specified criteria, this value is + * undefined, the failure code NV_ERR_MISSING_TABLE_ENTRY will + * be returned, and no data will be transferred. + * + * endIdx: + * [OUT] the index of the newest end record for the most recent report that + * matches the specified criteria (refer to the owner & processId + * fields). If no records match the specified criteria, this value is + * undefined, the failure code NV_ERR_MISSING_TABLE_ENTRY will + * be returned, and no data will be transferred. + * + * rptType: + * [OUT] indicator of what data is in the report. + * + * flags + * [OUT] a set odf flags indicating attributes of the record + * NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_FIRST -- indicates this is the first record of a report. + * NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_LAST -- indicates this is the last record of the report. + * NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_RANGE_VALID -- indicates this is the response contains a valid +* index range. + * Note, this may be set when an error is returned indicating a valid range was found, but event of + * the requested index was not. + * NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_DATA_VALID -- indicates this is the response contains valid data. + * + * rptCount: + * [OUT] number of entries returned in report. + * + * owner: + * [IN] Entries are only returned if they have the same owner as the specified owner or the specified + * owner Id is NV0000_CTRL_CMD_NVD_RPT_ANY_OWNER_ID. + * if the requested index is not owned by the specified owner, the rptIdx + * will be set to a value that does not match the reqIdx, and no data will + * be transferred. NV_ERR_INSUFFICIENT_PERMISSIONS is returned. + * + * processId: + * [IN] Deprecated + * report: + * [OUT] array of rptCount enum/value pair entries containing the data from the report. + * entries beyond rptCount are undefined. + * + * + * Possible status values returned are: + * NV_OK -- we found & transferred the requested record. + * NV_ERR_MISSING_TABLE_ENTRY -- we don't find any records that meet the criteria. + * NV_ERR_INVALID_INDEX -- the requested index was not found in the buffer. + * NV_ERR_INSUFFICIENT_PERMISSIONS -- the requested record was found, but it did not meet the criteria. + * NV_ERR_BUSY_RETRY -- We could not access the circular buffer. + * + */ + +#define NV0000_CTRL_CMD_NVD_GET_RCERR_RPT (0x607) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_MAX_ENTRIES 200 + +// report types +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_TEST 0 +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GRSTATUS 1 +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GPCSTATUS 2 +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_MMU_FAULT_STATUS 3 + +// pseudo register enums attribute content +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_EMPTY 0x00000000 +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_OVERFLOWED 0x00000001 // number of missed entries. +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_MAX_PSEDO_REG 0x0000000f + + + +// Flags Definitions +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_FIRST 0x00000001 // indicates this is the first record of a report. +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_LAST 0x00000002 // indicates this is the last record of the report. +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_RANGE_VALID 0x00000004 // indicates this is the response contains a valid range +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_DATA_VALID 0x00000008 // indicates this is the response contains valid data + + +// Attribute Definitions +#define TPC_REG_ATTR(gpcId, tpcId) ((gpcId << 8) | (tpcId)) +#define ROP_REG_ATTR(gpcId, ropId) ((gpcId << 8) | (ropId)) +#define SM_REG_ATTR(gpcId, tpcId, smId) ((((gpcId) << 16) | ((tpcId) << 8)) | (smId)) + +// Process Id Pseudo values +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_PROCESS_ID 0x00000000 // get report for any process ID + +#define NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_OWNER_ID 0xFFFFFFFF // get report for any owner ID + + +typedef struct NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY { + NvU32 tag; + NvU32 value; + NvU32 attribute; +} NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY; + +#define NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS { + NvU16 reqIdx; + NvU16 rptIdx; + NvU32 GPUTag; + NvU32 rptTime; // time in seconds since 1/1/1970 + NvU16 startIdx; + NvU16 endIdx; + NvU16 rptType; + NvU32 flags; + NvU16 rptCount; + NvU32 owner; // indicating whose reports to get + NvU32 processId; // deprecated field + + NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY report[NV0000_CTRL_CMD_NVD_RCERR_RPT_MAX_ENTRIES]; +} NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS; + +/* + * NV0000_CTRL_CMD_NVD_GET_DPC_ISR_TS + * + * This command returns the time stamp information that are collected from + * the execution of various DPCs/ISRs. This time stamp information is for + * debugging purposes only and would help with analyzing regressions and + * latencies for DPC/ISR execution times. + * + * tsBufferSize + * This field specifies the size of the buffer that the caller allocates. + * tsBuffer + * THis field specifies a pointer in the callers address space to the + * buffer into which the timestamp info on DPC/ISR is to be returned. + * This buffer must at least be as big as tsBufferSize. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV0000_CTRL_CMD_NVD_GET_DPC_ISR_TS (0x608) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS { + NvU32 tsBufferSize; + NV_DECLARE_ALIGNED(NvP64 pTSBuffer, 8); +} NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS; + +/* _ctrl0000nvd_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h new file mode 100644 index 0000000..9a48202 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h @@ -0,0 +1,98 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000proc.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" +#include "nvlimits.h" + +/* + * NV0000_CTRL_CMD_SET_SUB_PROCESS_ID + * + * Save the sub process ID and sub process name in client database + * subProcID + * Sub process ID + * subProcessName + * Sub process name + * + * In vGPU environment, sub process means the guest user/kernel process running + * within a single VM. It also refers to any sub process (or sub-sub process) + * within a parent process. + * + * Please refer to the wiki for more details about sub process concept: Resource_Server + * + * Possible return values are: + * NV_OK + */ +#define NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS { + NvU32 subProcessID; + char subProcessName[NV_PROC_NAME_MAX_LENGTH]; +} NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS; + +/* + * NV0000_CTRL_CMD_DISABLE_SUB_PROCESS_USERD_ISOLATION + * + * Disable sub process USERD isolation. + * bIsSubProcIsolated + * NV_TRUE to disable sub process USERD isolation + * + * USERD allocated by different domains should not be put into the same physical page. + * This provides the basic security isolation because a physical page is the unit of + * granularity at which OS can provide isolation between processes. + * + * GUEST_USER: USERD allocated by guest user process + * GUEST_KERNEL: USERD allocated by guest kernel process + * GUEST_INSECURE: USERD allocated by guest/kernel process, + * INSECURE means there is no isolation between guest user and guest kernel + * HOST_USER: USERD allocated by host user process + * HOST_KERNEL: USERD allocated by host kernel process + * + * When sub process USERD isolation is disabled, we won't distinguish USERD allocated by guest + * user and guest kernel. They all belong to the GUEST_INSECURE domain. + * + * Please refer to wiki for more details: RM_USERD_Isolation + * + * Possible return values are: + * NV_OK + */ +#define NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS { + NvBool bIsSubProcessDisabled; +} NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS; + +#define NV0000_CTRL_CMD_SET_SUB_PROCESS_ID (0x901) /* finn: Evaluated from "(FINN_NV01_ROOT_PROC_INTERFACE_ID << 8) | NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_DISABLE_SUB_PROCESS_USERD_ISOLATION (0x902) /* finn: Evaluated from "(FINN_NV01_ROOT_PROC_INTERFACE_ID << 8) | NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS_MESSAGE_ID" */ + +/* _ctrl0000proc_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h new file mode 100644 index 0000000..b8e921e --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h @@ -0,0 +1,112 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000syncgpuboost.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +#include "nvtypes.h" +#include "nvlimits.h" + +/* --------------------------- Macros ----------------------------------------*/ +// There are at least 2 GPUs in a sync group. Hence max is half of max devices. +#define NV0000_SYNC_GPU_BOOST_MAX_GROUPS (0x10) /* finn: Evaluated from "((NV_MAX_DEVICES) >> 1)" */ +#define NV0000_SYNC_GPU_BOOST_INVALID_GROUP_ID 0xFFFFFFFF + +/*-------------------------Command Prototypes---------------------------------*/ + +/*! + * Query whether SYNC GPU BOOST MANAGER is enabled or disabled. + */ +#define NV0000_CTRL_CMD_SYNC_GPU_BOOST_INFO (0xa01) /* finn: Evaluated from "(FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID << 8) | NV0000_SYNC_GPU_BOOST_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_SYNC_GPU_BOOST_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_SYNC_GPU_BOOST_INFO_PARAMS { + // [out] Specifies if Sync Gpu Boost Manager is enabled or not. + NvBool bEnabled; +} NV0000_SYNC_GPU_BOOST_INFO_PARAMS; + +/*! + * Creates a Synchronized GPU-Boost Group (SGBG) + */ +#define NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_CREATE (0xa02) /* finn: Evaluated from "(FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID << 8) | NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS_MESSAGE_ID" */ + +/*! + * Describes a Synchronized GPU-Boost Group configuration + */ +typedef struct NV0000_SYNC_GPU_BOOST_GROUP_CONFIG { + // [in] Number of elements in @ref gpuIds + NvU32 gpuCount; + + // [in] IDs of GPUs to be put in the Sync Boost Group + NvU32 gpuIds[NV_MAX_DEVICES]; + + // [out] Unique ID of the SGBG, if created + NvU32 boostGroupId; + + // [in] If this group represents bridgeless SLI + NvBool bBridgeless; +} NV0000_SYNC_GPU_BOOST_GROUP_CONFIG; + +#define NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS { + NV0000_SYNC_GPU_BOOST_GROUP_CONFIG boostConfig; +} NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS; + +/*! + * Destroys a previously created Synchronized GPU-Boost Group(SGBG) + */ +#define NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_DESTROY (0xa03) /* finn: Evaluated from "(FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID << 8) | NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS_MESSAGE_ID" */ + +#define NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS { + // [[in] Unique ID of the SGBG to be destroyed + NvU32 boostGroupId; +} NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS; + +/*! + * Get configuration information for all Synchronized Boost Groups in the system. + */ +#define NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_INFO (0xa04) /* finn: Evaluated from "(FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID << 8) | NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS { + // [out] Number of groups retrieved. @ref NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS::boostGroups + NvU32 groupCount; + + // [out] @ref NV0000_SYNC_GPU_BOOST_GROUP_CONFIG + NV0000_SYNC_GPU_BOOST_GROUP_CONFIG pBoostGroups[NV0000_SYNC_GPU_BOOST_MAX_GROUPS]; +} NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS; + +/* _ctrl0000syncgpuboost_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h new file mode 100644 index 0000000..74b65c7 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h @@ -0,0 +1,2915 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000system.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl0000/ctrl0000base.h" + +/* NV01_ROOT (client) system control commands and parameters */ + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_FEATURES + * + * This command returns a mask of supported features for the SYSTEM category + * of the 0000 class. + * + * Valid features include: + * + * NV0000_CTRL_GET_FEATURES_SLI + * When this bit is set, SLI is supported. + * NV0000_CTRL_GET_FEATURES_UEFI + * When this bit is set, it is a UEFI system. + * NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT + * When this bit is set, EFI has initialized core channel + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_FEATURES (0x1f0U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID (0xF0U) + +typedef struct NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS { + NvU32 featuresMask; +} NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS; + + + +/* Valid feature values */ +#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI 0:0 +#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI 1:1 +#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT 2:2 +#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE (0x00000001U) +/* + * NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION + * + * This command returns the current driver information. + * The first time this is called the size of strings is + * set with the greater of NV_BUILD_BRANCH_VERSION and + * NV_DISPLAY_DRIVER_TITLE. The client then allocates memory + * of size sizeOfStrings for pVersionBuffer and pTitleBuffer + * and calls the command again to receive driver info. + * + * sizeOfStrings + * This field returns the size in bytes of the pVersionBuffer and + * pTitleBuffer strings. + * pDriverVersionBuffer + * This field returns the version (NV_VERSION_STRING). + * pVersionBuffer + * This field returns the version (NV_BUILD_BRANCH_VERSION). + * pTitleBuffer + * This field returns the title (NV_DISPLAY_DRIVER_TITLE). + * changelistNumber + * This field returns the changelist value (NV_BUILD_CHANGELIST_NUM). + * officialChangelistNumber + * This field returns the last official changelist value + * (NV_LAST_OFFICIAL_CHANGELIST_NUM). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION (0x101U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS { + NvU32 sizeOfStrings; + NV_DECLARE_ALIGNED(NvP64 pDriverVersionBuffer, 8); + NV_DECLARE_ALIGNED(NvP64 pVersionBuffer, 8); + NV_DECLARE_ALIGNED(NvP64 pTitleBuffer, 8); + NvU32 changelistNumber; + NvU32 officialChangelistNumber; +} NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO + * + * This command returns system CPU information. + * + * type + * This field returns the processor type. + * Legal processor types include: + * Intel processors: + * P55 : P55C - MMX + * P6 : PPro + * P2 : PentiumII + * P2XC : Xeon & Celeron + * CELA : Celeron-A + * P3 : Pentium-III + * P3_INTL2 : Pentium-III w/integrated L2 (fullspeed, on die, 256K) + * P4 : Pentium 4 + * CORE2 : Core2 Duo Conroe + * AMD processors + * K62 : K6-2 w/ 3DNow + * IDT/Centaur processors + * C6 : WinChip C6 + * C62 : WinChip 2 w/ 3DNow + * Cyrix processors + * GX : MediaGX + * M1 : 6x86 + * M2 : M2 + * MGX : MediaGX w/ MMX + * Transmeta processors + * TM_CRUSOE : Transmeta Crusoe(tm) + * PowerPC processors + * PPC603 : PowerPC 603 + * PPC604 : PowerPC 604 + * PPC750 : PowerPC 750 + * + * capabilities + * This field returns the capabilities of the processor. + * Legal processor capabilities include: + * MMX : supports MMX + * SSE : supports SSE + * 3DNOW : supports 3DNow + * SSE2 : supports SSE2 + * SFENCE : supports SFENCE + * WRITE_COMBINING : supports write-combining + * ALTIVEC : supports ALTIVEC + * PUT_NEEDS_IO : requires OUT inst w/PUT updates + * NEEDS_WC_WORKAROUND : requires workaround for P4 write-combining bug + * 3DNOW_EXT : supports 3DNow Extensions + * MMX_EXT : supports MMX Extensions + * CMOV : supports CMOV + * CLFLUSH : supports CLFLUSH + * SSE3 : supports SSE3 + * NEEDS_WAR_124888 : requires write to GPU while spinning on + * : GPU value + * HT : support hyper-threading + * clock + * This field returns the processor speed in MHz. + * L1DataCacheSize + * This field returns the level 1 data (or unified) cache size + * in kilobytes. + * L2DataCacheSize + * This field returns the level 2 data (or unified) cache size + * in kilobytes. + * dataCacheLineSize + * This field returns the bytes per line in the level 1 data cache. + * numLogicalCpus + * This field returns the number of logical processors. On Intel x86 + * systems that support it, this value will incorporate the current state + * of HyperThreading. + * numPhysicalCpus + * This field returns the number of physical processors. + * name + * This field returns the CPU name in ASCII string format. + * family + * Vendor defined Family and Extended Family combined + * model + * Vendor defined Model and Extended Model combined + * stepping + * Silicon stepping + * bSEVEnabled + * Secure Encrypted Virtualization enabled/disabled state + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO (0x102U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS { + NvU32 type; /* processor type */ + NvU32 capabilities; /* processor caps */ + NvU32 clock; /* processor speed (MHz) */ + NvU32 L1DataCacheSize; /* L1 dcache size (KB) */ + NvU32 L2DataCacheSize; /* L2 dcache size (KB) */ + NvU32 dataCacheLineSize; /* L1 dcache bytes/line */ + NvU32 numLogicalCpus; /* logial processor cnt */ + NvU32 numPhysicalCpus; /* physical processor cnt*/ + NvU8 name[52]; /* embedded cpu name */ + NvU32 family; /* Vendor defined Family and Extended Family combined */ + NvU32 model; /* Vendor defined Model and Extended Model combined */ + NvU8 stepping; /* Silicon stepping */ + NvU32 coresOnDie; /* cpu cores per die */ + NvBool bSEVEnabled; /* SEV enabled on cpu */ +} NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS; + +// Macros for CPU family information +#define NV0000_CTRL_SYSTEM_CPU_FAMILY 3:0 +#define NV0000_CTRL_SYSTEM_CPU_EXTENDED_FAMILY 11:4 + +// Macros for CPU model information +#define NV0000_CTRL_SYSTEM_CPU_MODEL 3:0 +#define NV0000_CTRL_SYSTEM_CPU_EXTENDED_MODEL 7:4 + +// Macros for AMD CPU information +#define NV0000_CTRL_SYSTEM_CPU_ID_AMD_FAMILY 0xF +#define NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_FAMILY 0xA +#define NV0000_CTRL_SYSTEM_CPU_ID_AMD_MODEL 0x0 +#define NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_MODEL 0x4 + +// Macros for Intel CPU information +#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_FAMILY 0x6 +#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_FAMILY 0x0 +#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_S_MODEL 0x7 +#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_P_MODEL 0xA +#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_MODEL 0x9 + +/* processor type values */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_UNKNOWN (0x00000000U) +/* Intel types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P5 (0x00000001U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P55 (0x00000002U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P6 (0x00000003U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P2 (0x00000004U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P2XC (0x00000005U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_CELA (0x00000006U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P3 (0x00000007U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P3_INTL2 (0x00000008U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P4 (0x00000009U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2 (0x00000010U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_CELN_M16H (0x00000011U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2_EXTRM (0x00000012U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_ATOM (0x00000013U) +/* AMD types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K5 (0x00000030U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K6 (0x00000031U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K62 (0x00000032U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K63 (0x00000033U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K7 (0x00000034U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K8 (0x00000035U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K10 (0x00000036U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K11 (0x00000037U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_RYZEN (0x00000038U) +/* IDT/Centaur types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_C6 (0x00000060U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_C62 (0x00000061U) +/* Cyrix types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_GX (0x00000070U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_M1 (0x00000071U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_M2 (0x00000072U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_MGX (0x00000073U) +/* Transmeta types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_TM_CRUSOE (0x00000080U) +/* IBM types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC603 (0x00000090U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC604 (0x00000091U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC750 (0x00000092U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_POWERN (0x00000093U) +/* Unknown ARM architecture CPU type */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_UNKNOWN (0xA0000000U) +/* ARM Ltd types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A9 (0xA0000009U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A15 (0xA000000FU) +/* NVIDIA types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_1_0 (0xA0001000U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_2_0 (0xA0002000U) + +/* Generic types */ +#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC (0xA00FF000U) + + + +/* processor capabilities */ +#define NV0000_CTRL_SYSTEM_CPU_CAP_MMX (0x00000001U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE (0x00000002U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW (0x00000004U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 (0x00000008U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE (0x00000010U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING (0x00000020U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC (0x00000040U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_PUT_NEEDS_IO (0x00000080U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WC_WORKAROUND (0x00000100U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT (0x00000200U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT (0x00000400U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_CMOV (0x00000800U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH (0x00001000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_190854 (0x00002000U) /* deprecated */ +#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 (0x00004000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_124888 (0x00008000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE (0x00010000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 (0x00020000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 (0x00040000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_AVX (0x00080000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_ERMS (0x00100000U) + +/* feature mask (as opposed to bugs, requirements, etc.) */ +#define NV0000_CTRL_SYSTEM_CPU_CAP_FEATURE_MASK (0x1f5e7fU) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_CPU_CAP_MMX | NV0000_CTRL_SYSTEM_CPU_CAP_SSE | NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW | NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 | NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE | NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING | NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC | NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT | NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT | NV0000_CTRL_SYSTEM_CPU_CAP_CMOV | NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH | NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 | NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE | NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 | NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 | NV0000_CTRL_SYSTEM_CPU_CAP_AVX | NV0000_CTRL_SYSTEM_CPU_CAP_ERMS)" */ + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_CAPS + * + * This command returns the set of system capabilities in the + * form of an array of unsigned bytes. System capabilities include + * supported features and required workarounds for the system, + * each represented by a byte offset into the table and a bit + * position within that byte. + * + * capsTblSize + * This parameter specifies the size in bytes of the caps table. + * This value should be set to NV0000_CTRL_SYSTEM_CAPS_TBL_SIZE. + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the system caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_CAPS (0x103U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x3" */ + +typedef struct NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS { + NvU32 capsTblSize; + NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); +} NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS; + +/* extract cap bit setting from tbl */ +#define NV0000_CTRL_SYSTEM_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* caps format is byte_index:bit_mask */ +#define NV0000_CTRL_SYSTEM_CAPS_POWER_SLI_SUPPORTED 0:0x01 + +/* size in bytes of system caps table */ +#define NV0000_CTRL_SYSTEM_CAPS_TBL_SIZE 1U + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO + * + * This command returns system chipset information. + * + * vendorId + * This parameter returns the vendor identification for the chipset. + * A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the chipset + * cannot be identified. + * deviceId + * This parameter returns the device identification for the chipset. + * A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the chipset + * cannot be identified. + * subSysVendorId + * This parameter returns the subsystem vendor identification for the + * chipset. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the + * chipset cannot be identified. + * subSysDeviceId + * This parameter returns the subsystem device identification for the + * chipset. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the + * chipset cannot be identified. + * HBvendorId + * This parameter returns the vendor identification for the chipset's + * host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates + * the chipset's host bridge cannot be identified. + * HBdeviceId + * This parameter returns the device identification for the chipset's + * host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates + * the chipset's host bridge cannot be identified. + * HBsubSysVendorId + * This parameter returns the subsystem vendor identification for the + * chipset's host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID + * indicates the chipset's host bridge cannot be identified. + * HBsubSysDeviceId + * This parameter returns the subsystem device identification for the + * chipset's host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID + * indicates the chipset's host bridge cannot be identified. + * sliBondId + * This parameter returns the SLI bond identification for the chipset. + * vendorNameString + * This parameter returns the vendor name string. + * chipsetNameString + * This parameter returns the vendor name string. + * sliBondNameString + * This parameter returns the SLI bond name string. + * flag + * This parameter specifies NV0000_CTRL_SYSTEM_CHIPSET_FLAG_XXX flags: + * _HAS_RESIZABLE_BAR_ISSUE_YES: Chipset where the use of resizable BAR1 + * should be disabled - bug 3440153 + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO (0x104U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID" */ + +/* maximum name string length */ +#define NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH (0x0000020U) + +/* invalid id */ +#define NV0000_SYSTEM_CHIPSET_INVALID_ID (0xffffU) + +#define NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS { + NvU16 vendorId; + NvU16 deviceId; + NvU16 subSysVendorId; + NvU16 subSysDeviceId; + NvU16 HBvendorId; + NvU16 HBdeviceId; + NvU16 HBsubSysVendorId; + NvU16 HBsubSysDeviceId; + NvU32 sliBondId; + NvU8 vendorNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; + NvU8 subSysVendorNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; + NvU8 chipsetNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; + NvU8 sliBondNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; + NvU32 flags; +} NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS; + +#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE 0:0 +#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_NO (0x00000000U) +#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_YES (0x00000001U) + + + +/* + * NV0000_CTRL_CMD_SYSTEM_SET_MEMORY_SIZE + * + * This command is used to set the system memory size in pages. + * + * memorySize + * This parameter specifies the system memory size in pages. All values + * are considered legal. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0000_CTRL_CMD_SYSTEM_SET_MEMORY_SIZE (0x107U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS { + NvU32 memorySize; +} NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST + * + * This command is used to retrieve the set of system-level classes + * supported by the platform. + * + * numClasses + * This parameter returns the number of valid entries in the returned + * classes[] list. This parameter will not exceed + * Nv0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE. + * classes + * This parameter returns the list of supported classes + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST (0x108U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID" */ + +/* maximum number of classes returned in classes[] array */ +#define NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE (32U) + +#define NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS { + NvU32 numClasses; + NvU32 classes[NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE]; +} NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT + * + * This command is used to send triggered mobile related system events + * to the RM. + * + * eventType + * This parameter indicates the triggered event type. This parameter + * should specify a valid NV0000_CTRL_SYSTEM_EVENT_TYPE value. + * eventData + * This parameter specifies the type-dependent event data associated + * with EventType. This parameter should specify a valid + * NV0000_CTRL_SYSTEM_EVENT_DATA value. + * bEventDataForced + * This parameter specifies what we have to do, Whether trust current + * Lid/Dock state or not. This parameter should specify a valid + * NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED value. + + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * Sync this up (#defines) with one in nvapi.spec! + * (NV_ACPI_EVENT_TYPE & NV_ACPI_EVENT_DATA) + */ +#define NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT (0x110U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS { + NvU32 eventType; + NvU32 eventData; + NvBool bEventDataForced; +} NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS; + +/* valid eventType values */ +#define NV0000_CTRL_SYSTEM_EVENT_TYPE_LID_STATE (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_TYPE_POWER_SOURCE (0x00000001U) +#define NV0000_CTRL_SYSTEM_EVENT_TYPE_DOCK_STATE (0x00000002U) +#define NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_LID (0x00000003U) +#define NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_DOCK (0x00000004U) + +/* valid eventData values */ +#define NV0000_CTRL_SYSTEM_EVENT_DATA_LID_OPEN (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_LID_CLOSED (0x00000001U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_BATTERY (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_AC (0x00000001U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_UNDOCKED (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_DOCKED (0x00000001U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DSM (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DCS (0x00000001U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_NVIF (0x00000002U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_ACPI (0x00000003U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL (0x00000004U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_COUNT (0x5U) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL + 1)" */ +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DSM (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DCS (0x00000001U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_NVIF (0x00000002U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_ACPI (0x00000003U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL (0x00000004U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_COUNT (0x5U) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL + 1)" */ + +/* valid bEventDataForced values */ +#define NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_TRUE (0x00000001U) + +/* + * NV000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE + * + * This command is used to query the platform type. + * + * systemType + * This parameter returns the type of the system. + * Legal values for this parameter include: + * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP + * The system is a desktop platform. + * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC + * The system is a mobile (non-Toshiba) platform. + * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP + * The system is a mobile Toshiba platform. + * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC + * The system is a system-on-a-chip (SOC) platform. + * + + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE (0x111U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS { + NvU32 systemType; +} NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS; + +/* valid systemType values */ +#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP (0x000000U) +#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC (0x000001U) +#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_TOSHIBA (0x000002U) +#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC (0x000003U) + + + + +/* + * NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL + * + * This command controls the current RmMsg filters. + * + * It is only supported if RmMsg is enabled (e.g. debug builds). + * + * cmd + * GET - Gets the current RmMsg filter string. + * SET - Sets the current RmMsg filter string. + * + * count + * The length of the RmMsg filter string. + * + * data + * The RmMsg filter string. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL (0x121U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE 512U + +#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_GET (0x00000000U) +#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_SET (0x00000001U) + +#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID (0x21U) + +typedef struct NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS { + NvU32 cmd; + NvU32 count; + NvU8 data[NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE]; +} NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS; + +/* + * NV0000_CTRL_SYSTEM_HWBC_INFO + * + * This structure contains information about the HWBC (BR04) specified by + * hwbcId. + * + * hwbcId + * This field specifies the HWBC ID. + * firmwareVersion + * This field returns the version of the firmware on the HWBC (BR04), if + * present. This is a packed binary number of the form 0x12345678, which + * corresponds to a firmware version of 12.34.56.78. + * subordinateBus + * This field returns the subordinate bus number of the HWBC (BR04). + * secondaryBus + * This field returns the secondary bus number of the HWBC (BR04). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +typedef struct NV0000_CTRL_SYSTEM_HWBC_INFO { + NvU32 hwbcId; + NvU32 firmwareVersion; + NvU32 subordinateBus; + NvU32 secondaryBus; +} NV0000_CTRL_SYSTEM_HWBC_INFO; + +#define NV0000_CTRL_SYSTEM_HWBC_INVALID_ID (0xFFFFFFFFU) + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO + * + * This command returns information about all Hardware Broadcast (HWBC) + * devices present in the system that are BR04s. To get the complete + * list of HWBCs in the system, all GPUs present in the system must be + * initialized. See the description of NV0000_CTRL_CMD_GPU_ATTACH_IDS to + * accomplish this. + * + * hwbcInfo + * This field is an array of NV0000_CTRL_SYSTEM_HWBC_INFO structures into + * which HWBC information is placed. There is one entry for each HWBC + * present in the system. Valid entries are contiguous, invalid entries + * have the hwbcId equal to NV0000_CTRL_SYSTEM_HWBC_INVALID_ID. If no HWBC + * is present in the system, all the entries would be marked invalid, but + * the return value would still be SUCCESS. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO (0x124U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_MAX_HWBCS (0x00000080U) + +#define NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID (0x24U) + +typedef struct NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS { + NV0000_CTRL_SYSTEM_HWBC_INFO hwbcInfo[NV0000_CTRL_SYSTEM_MAX_HWBCS]; +} NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL + * + * This command is used to control GPS functionality. It allows control of + * GPU Performance Scaling (GPS), changing its operational parameters and read + * most GPS dynamic parameters. + * + * command + * This parameter specifies the command to execute. Invalid commands + * result in the return of an NV_ERR_INVALID_ARGUMENT status. + * locale + * This parameter indicates the specific locale to which the command + * 'command' is to be applied. + * Supported range of CPU/GPU {i = 0, ..., 255} + * data + * This parameter contains a command-specific data payload. It can + * be used to input data as well as output data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_COMMAND + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_DATA + * NV_ERR_INVALID_REQUEST + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL (0x122U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS { + NvU16 command; + NvU16 locale; + NvU32 data; +} NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS; + +/* + * Valid command values : + * + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT + * Is used to check if GPS was correctly initialized. + * Possible return (OUT) values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC + * Are used to stop/start GPS functionality and to get current status. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS + * Are used to control execution of GPS actions and to get current status. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC + * Are used to switch current GPS logic and to retrieve current logic. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF + * Will cause that all GPS actions will be NULL. + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY + * Fuzzy logic will determine GPS actions based on current ruleset. + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC + * Deterministic logic will define GPS actions based on current ruleset. + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE + * Are used to set/retrieve system control preference. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT + * Are used to set/retrieve GPU2CPU pstate limits. + * IN/OUT values are four bytes packed into a 32-bit data field. + * The CPU cap index for GPU pstate 0 is in the lowest byte, the CPU cap + * index for the GPU pstate 3 is in the highest byte, etc. One + * special value is to disable the override to the GPU2CPU map: + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE + * Is used to stop/start GPS PMU functionality. + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE + * Is used to get the current status of PMU GPS. + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER + * Are used to set/retrieve max power [mW] that system can provide. + * This is hardcoded GPS safety feature and logic/rules does not apply + * to this threshold. + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET + * Are used to set/retrieve current system cooling budget [mW]. + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD + * Are used to set/retrieve integration interval [sec]. + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT + * Are used to set/retrieve used ruleset [#]. Value is checked + * against MAX number of rules for currently used GPS logic. Also COUNT + * provides a way to find out how many rules exist for the current control + * system. + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST + * Is used to set/get a delay relative to now during which to allow unbound + * CPU performance. Units are seconds. + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE + * Is used to override/get the actual power supply mode (AC/Battery). + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO + * Is used to get the Ventura system information for VCT tool + * Returned 32bit value should be treated as bitmask and decoded in + * following way: + * Encoding details are defined in objgps.h refer to + * NV_GPS_SYS_SUPPORT_INFO and corresponding bit defines. + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTION + * Is used to get the supported sub-functions defined in SBIOS. Returned + * value is a bitmask where each bit corresponds to different function: + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE + * Are used to retrieve appropriate power measurements and their derivatives + * in [mW] for required locale. _BURDEN is defined only for _LOCALE_SYSTEM. + * _INTERMEDIATE is not defined for _LOCALE_SYSTEM, and takes an In value as + * index. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS + * Is used to retrieve parameters when adjusting raw sensor power reading. + * The values may come from SBIOS, VBIOS, registry or driver default. + * Possible IN value is the index of interested parameter. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE + * Are used to retrieve appropriate temperature measurements and their + * derivatives in [1/1000 Celsius]. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX + * Are used to retrieve CPU(x)/GPU(x) p-state or it's limits. + * Not applicable to _LOCALE_SYSTEM. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION + * Is used to retrieve last GPS action for given domain. + * Not applicable to _LOCALE_SYSTEM. + * Possible return (OUT) values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0 + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1 + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1 + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2 + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE + * Is used to set the power sensor simulator state. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE + * Is used to get the power simulator sensor simulator state. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA + * Is used to set power sensor simulator data + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA + * Is used to get power sensor simulator data + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK + * Is used to respond to the ACPI event triggered by SBIOS. RM will + * request value for budget and status, validate them, apply them + * and send ACK back to SBIOS. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT + * Is a test cmd that should notify SBIOS to send ACPI event requesting + * budget and status change. + */ +#define NV0000_CTRL_CMD_SYSTEM_GPS_INVALID (0xFFFFU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT (0x0000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC (0x0001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC (0x0002U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS (0x0003U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS (0x0004U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC (0x0005U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC (0x0006U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE (0x0007U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE (0x0008U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT (0x0009U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT (0x000AU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE (0x000BU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE (0x000CU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER (0x0100U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER (0x0101U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET (0x0102U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET (0x0103U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD (0x0104U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD (0x0105U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET (0x0106U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET (0x0107U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT (0x0108U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST (0x0109U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST (0x010AU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE (0x010BU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE (0x010CU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO (0x010DU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTIONS (0x010EU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER (0x0200U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA (0x0201U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE (0x0202U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG (0x0203U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL (0x0204U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN (0x0205U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE (0x0206U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS (0x0210U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP (0x0220U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA (0x0221U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE (0x0222U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE (0x0240U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP (0x0241U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN (0x0242U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX (0x0243U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION (0x0244U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_SLFM_PRESENT (0x0245U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE (0x0250U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE (0x0251U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA (0x0252U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA (0x0253U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK (0x0320U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT (0x0321U) + +/* valid LOCALE values */ +#define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_INVALID (0xFFFFU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_SYSTEM (0x0000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_CPU(i) (0x0100+((i)%0x100)) +#define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_GPU(i) (0x0200+((i)%0x100)) + +/* valid data values for enums */ +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID (0x80000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE (0xFFFFFFFFU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_ON (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS (0x00000004U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC (0x00000008U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC (0x00000010U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB (0x00000020U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS (0x00000040U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0 (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1 (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT (0x00000003U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1 (0x00000004U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2 (0x00000005U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM (0x00000006U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM (0x00000007U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_NO (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_YES (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_ON (0x00000001U) + +/* + * NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL + * + * This command allows execution of multiple GpsControl commands within one + * RmControl call. For practical reasons # of commands is limited to 16. + * This command shares defines with NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL. + * + * cmdCount + * Number of commands that should be executed. + * Less or equal to NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX. + * + * succeeded + * Number of commands that were succesully executed. + * Less or equal to NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX. + * Failing commands return NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID + * in their data field. + * + * cmdData + * Array of commands with following structure: + * command + * This parameter specifies the command to execute. + * Invalid commands result in the return of an + * NV_ERR_INVALID_ARGUMENT status. + * locale + * This parameter indicates the specific locale to which + * the command 'command' is to be applied. + * Supported range of CPU/GPU {i = 0, ..., 255} + * data + * This parameter contains a command-specific data payload. + * It is used both to input data as well as to output data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL (0x123U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX (16U) +#define NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID (0x23U) + +typedef struct NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS { + NvU32 cmdCount; + NvU32 succeeded; + + struct { + NvU16 command; + NvU16 locale; + NvU32 data; + } cmdData[NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX]; +} NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS; + + +/* + * Deprecated. Please use NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 instead. + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS (0x127U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID" */ + +/* + * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED must remain equal to the square of + * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS due to Check RM parsing issues. + * NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS is the maximum size of GPU groups + * allowed for batched P2P caps queries provided by the RM control + * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX. + */ +#define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS 32U +#define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED 1024U +#define NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS 8U +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER 0xffffffffU + +/* P2P capabilities status index values */ +#define NV0000_CTRL_P2P_CAPS_INDEX_READ 0U +#define NV0000_CTRL_P2P_CAPS_INDEX_WRITE 1U +#define NV0000_CTRL_P2P_CAPS_INDEX_NVLINK 2U +#define NV0000_CTRL_P2P_CAPS_INDEX_ATOMICS 3U +#define NV0000_CTRL_P2P_CAPS_INDEX_PROP 4U +#define NV0000_CTRL_P2P_CAPS_INDEX_LOOPBACK 5U +#define NV0000_CTRL_P2P_CAPS_INDEX_PCI 6U +#define NV0000_CTRL_P2P_CAPS_INDEX_C2C 7U +#define NV0000_CTRL_P2P_CAPS_INDEX_PCI_BAR1 8U + +#define NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE 9U + + +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID (0x27U) + +typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS { + NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; + NvU32 gpuCount; + NvU32 p2pCaps; + NvU32 p2pOptimalReadCEs; + NvU32 p2pOptimalWriteCEs; + NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; + NV_DECLARE_ALIGNED(NvP64 busPeerIds, 8); +} NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS; + +/* valid p2pCaps values */ +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED 0:0 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED 1:1 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED 2:2 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED 3:3 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED 4:4 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED 5:5 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED 6:6 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED 7:7 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED 8:8 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED 9:9 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED 10:10 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_TRUE (0x00000001U) + + +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED 12:12 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED 13:13 +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_TRUE (0x00000001U) + +/* P2P status codes */ +#define NV0000_P2P_CAPS_STATUS_OK (0x00U) +#define NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED (0x01U) +#define NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED (0x02U) +#define NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED (0x03U) +#define NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY (0x04U) +#define NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED (0x05U) + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 + * + * This command returns peer to peer capabilities present between GPUs. + * Valid requests must present a list of GPU Ids. + * + * [in] gpuIds + * This member contains the array of GPU IDs for which we query the P2P + * capabilities. Valid entries are contiguous, beginning with the first + * entry in the list. + * [in] gpuCount + * This member contains the number of GPU IDs stored in the gpuIds[] array. + * [out] p2pCaps + * This member returns the peer to peer capabilities discovered between the + * GPUs. Valid p2pCaps values include: + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED + * When this bit is set, peer to peer writes between subdevices owned + * by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED + * When this bit is set, peer to peer reads between subdevices owned + * by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED + * When this bit is set, peer to peer PROP between subdevices owned + * by this device are supported. This is enabled by default + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED + * When this bit is set, PCI is supported for all P2P between subdevices + * owned by this device. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED + * When this bit is set, NVLINK is supported for all P2P between subdevices + * owned by this device. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED + * When this bit is set, peer to peer atomics between subdevices owned + * by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED + * When this bit is set, peer to peer loopback is supported for subdevices + * owned by this device. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED + * When this bit is set, indirect peer to peer writes between subdevices + * owned by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED + * When this bit is set, indirect peer to peer reads between subdevices + * owned by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED + * When this bit is set, indirect peer to peer atomics between + * subdevices owned by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED + * When this bit is set, indirect NVLINK is supported for subdevices + * owned by this device. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED + * When this bit is set, C2C P2P is supported between the GPUs + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_BAR1_SUPPORTED + * When this bit is set, BAR1 P2P is supported between the GPUs + * mentioned in @ref gpuIds + * [out] p2pOptimalReadCEs + * For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink + * [out] p2pOptimalWriteCEs + * For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink + * [out] p2pCapsStatus + * This member returns status of all supported p2p capabilities. Valid + * status values include: + * NV0000_P2P_CAPS_STATUS_OK + * P2P capability is supported. + * NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED + * Chipset doesn't support p2p capability. + * NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED + * GPU doesn't support p2p capability. + * NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED + * IOH topology isn't supported. For e.g. root ports are on different + * IOH. + * NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY + * P2P Capability is disabled by a regkey. + * NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED + * P2P Capability is not supported. + * NV0000_P2P_CAPS_STATUS_NVLINK_SETUP_FAILED + * Indicates that NvLink P2P link setup failed. + * [out] busPeerIds + * Peer ID matrix. It is a one-dimentional array. + * busPeerIds[X * gpuCount + Y] maps from index X to index Y in + * the gpuIds[] table. For invalid or non-existent peer busPeerIds[] + * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ + + + +#define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 (0x12bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID (0x2BU) + +typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS { + NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; + NvU32 gpuCount; + NvU32 p2pCaps; + NvU32 p2pOptimalReadCEs; + NvU32 p2pOptimalWriteCEs; + NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; + NvU32 busPeerIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED]; +} NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX + * + * This command returns peer to peer capabilities present between all pairs of + * GPU IDs {(a, b) : a in gpuIdGrpA and b in gpuIdGrpB}. This can be used to + * collect all P2P capabilities in the system - see the SRT: + * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX_TEST + * for a demonstration. + * + * The call will query for all pairs between set A and set B, and returns + * results in both link directions. The results are two-dimensional arrays where + * the first dimension is the index within the set-A array of one GPU ID under + * consideration, and the second dimension is the index within the set-B array + * of the other GPU ID under consideration. + * + * That is, the result arrays are *ALWAYS* to be indexed first with the set-A + * index, then with the set-B index. The B-to-A direction of results are put in + * the b2aOptimal(Read|Write)CEs. This makes it unnecessary to call the query + * twice, since the usual use case requires both directions. + * + * If a set is being compared against itself (by setting grpBCount to 0), then + * the result matrices are symmetric - it doesn't matter which index is first. + * However, the choice of indices is effectively a choice of which ID is "B" and + * which is "A" for the "a2b" and "b2a" directional results. + * + * [in] grpACount + * This member contains the number of GPU IDs stored in the gpuIdGrpA[] + * array. Must be >= 0. + * [in] grpBCount + * This member contains the number of GPU IDs stored in the gpuIdGrpB[] + * array. Can be == 0 to specify a check of group A against itself. + * [in] gpuIdGrpA + * This member contains the array of GPU IDs in "group A", each of which + * will have its P2P capabilities returned with respect to each GPU ID in + * "group B". Valid entries are contiguous, beginning with the first entry + * in the list. + * [in] gpuIdGrpB + * This member contains the array of GPU IDs in "group B", each of which + * will have its P2P capabilities returned with respect to each GPU ID in + * "group A". Valid entries are contiguous, beginning with the first entry + * in the list. May be equal to gpuIdGrpA, but best performance requires + * that the caller specifies grpBCount = 0 in this case, and ignores this. + * [out] p2pCaps + * This member returns the peer to peer capabilities discovered between the + * pairs of input GPUs between the groups, indexed by [A_index][B_index]. + * Valid p2pCaps values include: + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED + * When this bit is set, peer to peer writes between subdevices owned + * by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED + * When this bit is set, peer to peer reads between subdevices owned + * by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED + * When this bit is set, peer to peer PROP between subdevices owned + * by this device are supported. This is enabled by default + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED + * When this bit is set, PCI is supported for all P2P between subdevices + * owned by this device. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED + * When this bit is set, NVLINK is supported for all P2P between subdevices + * owned by this device. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED + * When this bit is set, peer to peer atomics between subdevices owned + * by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED + * When this bit is set, peer to peer loopback is supported for subdevices + * owned by this device. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED + * When this bit is set, indirect peer to peer writes between subdevices + * owned by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED + * When this bit is set, indirect peer to peer reads between subdevices + * owned by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED + * When this bit is set, indirect peer to peer atomics between + * subdevices owned by this device are supported. + * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED + * When this bit is set, indirect NVLINK is supported for subdevices + * owned by this device. + * [out] a2bOptimalReadCes + * For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink + * in the A-to-B direction. + * [out] a2bOptimalWriteCes + * For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink + * in the A-to-B direction. + * [out] b2aOptimalReadCes + * For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink + * in the B-to-A direction. + * [out] b2aOptimalWriteCes + * For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink + * in the B-to-A direction. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ + + + +#define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX (0x13aU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID" */ + +typedef NvU32 NV0000_CTRL_P2P_CAPS_MATRIX_ROW[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID (0x3AU) + +typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS { + NvU32 grpACount; + NvU32 grpBCount; + NvU32 gpuIdGrpA[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; + NvU32 gpuIdGrpB[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; + NV0000_CTRL_P2P_CAPS_MATRIX_ROW p2pCaps[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; + NV0000_CTRL_P2P_CAPS_MATRIX_ROW a2bOptimalReadCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; + NV0000_CTRL_P2P_CAPS_MATRIX_ROW a2bOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; + NV0000_CTRL_P2P_CAPS_MATRIX_ROW b2aOptimalReadCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; + NV0000_CTRL_P2P_CAPS_MATRIX_ROW b2aOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; +} NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GPS_CTRL + * + * This command is used to execute general GPS Functions, most dealing with + * calling SBIOS, or retrieving cached sensor and GPS state data. + * + * version + * This parameter specifies the version of the interface. Legal values + * for this parameter are 1. + * cmd + * This parameter specifies the GPS API to be invoked. + * Valid values for this parameter are: + * NV0000_CTRL_GPS_CMD_GET_THERM_LIMIT + * This command gets the temperature limit for thermal controller. When + * this command is specified the input parameter contains ???. + * NV0000_CTRL_GPS_CMD_SET_THERM_LIMIT + * This command set the temperature limit for thermal controller. When + * this command is specified the input parameter contains ???. + * input + * This parameter specifies the cmd-specific input value. + * result + * This parameter returns the cmd-specific output value. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_SYSTEM_GPS_CTRL (0x12aU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID (0x2AU) + +typedef struct NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS { + NvU32 cmd; + NvS32 input[2]; + NvS32 result[4]; +} NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS; + +/* valid version values */ +#define NV0000_CTRL_GPS_PSHARE_PARAMS_PSP_CURRENT_VERSION (0x00010000U) + +/* valid cmd values */ +#define NV0000_CTRL_GPS_CMD_TYPE_GET_THERM_LIMIT (0x00000002U) +#define NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000U) +#define NV0000_CTRL_GPS_RESULT_THERMAL_LIMIT (0x00000000U) +#define NV0000_CTRL_GPS_RESULT_MIN_LIMIT (0x00000001U) +#define NV0000_CTRL_GPS_RESULT_MAX_LIMIT (0x00000002U) +#define NV0000_CTRL_GPS_RESULT_LIMIT_SOURCE (0x00000003U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_THERM_LIMIT (0x00000003U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_THERMAL_LIMIT (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA (0x00000004U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DOWN_N_DELTA (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA (0x00000005U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DOWN_N_DELTA (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA (0x00000006U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_HOLD_DELTA (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA (0x00000007U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_HOLD_DELTA (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA (0x00000008U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_UP_DELTA (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA (0x00000009U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_UP_DELTA (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA (0x0000000AU) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_ENGAGE_DELTA (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA (0x0000000BU) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_ENGAGE_DELTA (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000CU) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000DU) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_STATUS (0x00000016U) +#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_STATUS (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_STATUS (0x00000017U) +#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_STATUS (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM (0x00000018U) +#define NV0000_CTRL_GPS_RESULT_CPU_SET_UTIL_AVG_NUM (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM (0x00000019U) +#define NV0000_CTRL_GPS_INPUT_CPU_GET_UTIL_AVG_NUM (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_PERF_SENSOR (0x0000001AU) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_NEXT_EXPECTED_POLL (0x00000001U) +#define NV0000_CTRL_GPS_RESULT_PERF_SENSOR_VALUE (0x00000000U) +#define NV0000_CTRL_GPS_RESULT_PERF_SENSOR_AVAILABLE (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_CALL_ACPI (0x0000001BU) +#define NV0000_CTRL_GPS_INPUT_ACPI_CMD (0x00000000U) +#define NV0000_CTRL_GPS_INPUT_ACPI_PARAM_IN (0x00000001U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_1 (0x00000000U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_2 (0x00000001U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_STATUS (0x00000000U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_VERSION (0x00000001U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_SZ (0x00000002U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_SZ (0x00000000U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_COUNT (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_IGPU_TURBO (0x0000001CU) +#define NV0000_CTRL_GPS_INPUT_SET_IGPU_TURBO (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERIOD (0x00000026U) +#define NV0000_CTRL_GPS_INPUT_TEMP_PERIOD (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERIOD (0x00000027U) +#define NV0000_CTRL_GPS_RESULT_TEMP_PERIOD (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_NUDGE_FACTOR (0x00000028U) +#define NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_UP (0x00000000U) +#define NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_DOWN (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_NUDGE_FACTOR (0x00000029U) +#define NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_UP (0x00000000U) +#define NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_DOWN (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES (0x0000002AU) +#define NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) +#define NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES (0x0000002BU) +#define NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) +#define NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERF_LIMITS (0x0000002CU) +#define NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_UPPER (0x00000000U) +#define NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_LOWER (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERF_LIMITS (0x0000002DU) +#define NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_UPPER (0x00000000U) +#define NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_LOWER (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_PM1_AVAILABLE (0x0000002EU) +#define NV0000_CTRL_GPS_INPUT_PM1_AVAILABLE (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_PM1_AVAILABLE (0x0000002FU) +#define NV0000_CTRL_GPS_OUTPUT_PM1_AVAILABLE (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS (0x00000044U) +#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) +#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS (0x00000045U) +#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT (0x00000046U) +#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ (0000000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT (0x00000047U) +#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ (0000000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM (0x00000048U) +#define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_INDEX (0000000000U) +#define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_AVAILABLE_MASK (0000000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM (0x00000049U) +#define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX (0000000000U) +#define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX_MAX (2U) + +#define NV0000_CTRL_GPS_PPM_INDEX 7:0 +#define NV0000_CTRL_GPS_PPM_INDEX_MAXPERF (0U) +#define NV0000_CTRL_GPS_PPM_INDEX_BALANCED (1U) +#define NV0000_CTRL_GPS_PPM_INDEX_QUIET (2U) +#define NV0000_CTRL_GPS_PPM_INDEX_INVALID (0xFFU) +#define NV0000_CTRL_GPS_PPM_MASK 15:8 +#define NV0000_CTRL_GPS_PPM_MASK_INVALID (0U) + +/* valid PS_STATUS result values */ +#define NV0000_CTRL_GPS_CMD_PS_STATUS_OFF (0U) +#define NV0000_CTRL_GPS_CMD_PS_STATUS_ON (1U) + + +/* + * NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS + * + * This command allows privileged users to update the values of + * security settings governing RM behavior. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT, + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_PERMISSIONS + * + * Please note: as implied above, administrator privileges are + * required to modify security settings. + */ +#define NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS (0x129U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x29" */ + +#define GPS_MAX_COUNTERS_PER_BLOCK 32U +typedef struct NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS { + NvU32 objHndl; + NvU32 blockId; + NvU32 nextExpectedSampleTimems; + NvU32 countersReq; + NvU32 countersReturned; + NvU32 counterBlock[GPS_MAX_COUNTERS_PER_BLOCK]; +} NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS; + +#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS (0x12cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x2C" */ + +#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS (0x12eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x2E" */ + +/* + * NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI + * + * This command allows users to call GPS ACPI commands for testing purposes. + * + * cmd + * This parameter specifies the GPS ACPI command to execute. + * + * input + * This parameter specified the cmd-dependent input value. + * + * resultSz + * This parameter returns the size (in bytes) of the valid data + * returned in the result parameter. + * + * result + * This parameter returns the results of the specified cmd. + * The maximum size (in bytes) of this returned data will + * not exceed GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE + * + * GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE + * The size of buffer (result) in unit of NvU32. + * The smallest value is sizeof(PSS_ENTRY)*ACPI_PSS_ENTRY_MAX. + * Since the prior one is 24 bytes, and the later one is 48, + * this value cannot be smaller than 288. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT, + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_PERMISSIONS + * + */ +#define GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U +#define NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID (0x2DU) + +typedef struct NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS { + NvU32 cmd; + NvU32 input; + NvU32 resultSz; + NvU32 result[GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE]; +} NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS; + +#define NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI (0x12dU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID" */ + +/* + * NV0000_CTRL_SYSTEM_PARAM_* + * + * The following is a list of system-level parameters (often sensors) that the + * driver can be made aware of. They are primarily intended to be used by system + * power-balancing algorithms that require system-wide visibility in order to + * function. The names and values used here are established and specified in + * several different NVIDIA documents that are made externally available. Thus, + * updates to this list must be made with great caution. The only permissible + * change is to append new parameters. Reordering is strictly prohibited. + * + * Brief Parameter Summary: + * TGPU - GPU temperature (NvTemp) + * PDTS - CPU package temperature (NvTemp) + * SFAN - System fan speed (% of maximum fan speed) + * SKNT - Skin temperature (NvTemp) + * CPUE - CPU energy counter (NvU32) + * TMP1 - Additional temperature sensor 1 (NvTemp) + * TMP2 - Additional temperature sensor 2 (NvTemp) + * CTGP - Mode 2 power limit offset (NvU32) + * PPMD - Power mode data (NvU32) + */ +#define NV0000_CTRL_SYSTEM_PARAM_TGPU (0x00000000U) +#define NV0000_CTRL_SYSTEM_PARAM_PDTS (0x00000001U) +#define NV0000_CTRL_SYSTEM_PARAM_SFAN (0x00000002U) +#define NV0000_CTRL_SYSTEM_PARAM_SKNT (0x00000003U) +#define NV0000_CTRL_SYSTEM_PARAM_CPUE (0x00000004U) +#define NV0000_CTRL_SYSTEM_PARAM_TMP1 (0x00000005U) +#define NV0000_CTRL_SYSTEM_PARAM_TMP2 (0x00000006U) +#define NV0000_CTRL_SYSTEM_PARAM_CTGP (0x00000007U) +#define NV0000_CTRL_SYSTEM_PARAM_PPMD (0x00000008U) +#define NV0000_CTRL_SYSTEM_PARAM_COUNT (0x00000009U) + +/* + * NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD + * + * This command is used to execute general ACPI methods. + * + * method + * This parameter identifies the MXM ACPI API to be invoked. + * Valid values for this parameter are: + * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS + * This value specifies that the DSM NVOP subfunction OPTIMUSCAPS + * API is to be invoked. + * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG + * This value specifies that the DSM NVOP subfunction OPTIMUSFLAG + * API is to be invoked. This API will set a Flag in sbios to Indicate + * that HD Audio Controller is disable/Enabled from GPU Config space. + * This flag will be used by sbios to restore Audio state after resuming + * from s3/s4. + * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS + * This value specifies that the DSM JT subfunction FUNC_CAPS is to + * to be invoked to get the SBIOS capabilities + * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY + * This value specifies that the DSM JT subfunction FUNC_PLATPOLICY is + * to be invoked to set and get the various platform policies for JT. + * Refer to the JT spec in more detail on various policies. + * inData + * This parameter specifies the method-specific input buffer. Data is + * passed to the specified API using this buffer. + * inDataSize + * This parameter specifies the size of the inData buffer in bytes. + * outStatus + * This parameter returns the status code from the associated ACPI call. + * outData + * This parameter specifies the method-specific output buffer. Data + * is returned by the specified API using this buffer. + * outDataSize + * This parameter specifies the size of the outData buffer in bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD (0x130U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID (0x30U) + +typedef struct NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS { + NvU32 method; + NV_DECLARE_ALIGNED(NvP64 inData, 8); + NvU16 inDataSize; + NvU32 outStatus; + NV_DECLARE_ALIGNED(NvP64 outData, 8); + NvU16 outDataSize; +} NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS; + +/* valid method parameter values */ +#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS (0x00000000U) +#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG (0x00000001U) +#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS (0x00000002U) +#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY (0x00000003U) +/* + * NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS + * + * This command can be used to instruct the RM to enable/disable specific module + * of ETW events. + * + * moduleMask + * This parameter specifies the module of events we would like to + * enable/disable. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS (0x131U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID (0x31U) + +typedef struct NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS { + NvU32 moduleMask; +} NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS; + +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ALL (0x00000001U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NOFREQ (0x00000002U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_FLUSH (0x00000004U) + +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PERF (0x00000010U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ELPG (0x00000020U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVDPS (0x00000040U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_POWER (0x00000080U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_DISP (0x00000100U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RMAPI (0x00000200U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_INTR (0x00000400U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_LOCK (0x00000800U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RCJOURNAL (0x00001000U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GENERIC (0x00002000U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_THERM (0x00004000U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GPS (0x00008000U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PCIE (0x00010000U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVTELEMETRY (0x00020000U) + +/* + * NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA + * + * This command is used to read FRL data based on need. + * + * nextSampleNumber + * This parameter returns the counter of next sample which is being filled. + * samples + * This parameter returns the frame time, render time, target time, client ID + * with one reserve bit for future use. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA (0x12fU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE 64U + +typedef struct NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE { + NvU16 frameTime; + NvU16 renderTime; + NvU16 targetTime; + NvU8 sleepTime; + NvU8 sampleNumber; +} NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE; + +#define NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID (0x2FU) + +typedef struct NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS { + NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE samples[NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE]; + NvU8 nextSampleNumber; +} NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA + * + * This command is used to write FRM data based on need. + * + * frameTime + * This parameter contains the frame time of current frame. + * renderTime + * This parameter contains the render time of current frame. + * targetTime + * This parameter contains the target time of current frame. + * sleepTime + * This parameter contains the sleep duration inserted by FRL for the latest frame. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA (0x132U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID (0x32U) + +typedef struct NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS { + NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE sampleData; +} NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO + * + * This command returns the current host driver, host OS and + * plugin information. It is only valid when VGX is setup. + * szHostDriverVersionBuffer + * This field returns the host driver version (NV_VERSION_STRING). + * szHostVersionBuffer + * This field returns the host driver version (NV_BUILD_BRANCH_VERSION). + * szHostTitleBuffer + * This field returns the host driver title (NV_DISPLAY_DRIVER_TITLE). + * szPluginTitleBuffer + * This field returns the plugin build title (NV_DISPLAY_DRIVER_TITLE). + * szHostUnameBuffer + * This field returns the call of 'uname' on the host OS. + * iHostChangelistNumber + * This field returns the changelist value of the host driver (NV_BUILD_CHANGELIST_NUM). + * iPluginChangelistNumber + * This field returns the changelist value of the plugin (NV_BUILD_CHANGELIST_NUM). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE 256U +#define NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO (0x133U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID (0x33U) + +typedef struct NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS { + char szHostDriverVersionBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; + char szHostVersionBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; + char szHostTitleBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; + char szPluginTitleBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; + char szHostUnameBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; + NvU32 iHostChangelistNumber; + NvU32 iPluginChangelistNumber; +} NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS + * + * This command returns the power status of the GPUs in the system, successfully attached or not because of + * insufficient power. It is supported on Kepler and up only. + * gpuCount + * This field returns the count into the following arrays. + * busNumber + * This field returns the busNumber of a GPU. + * gpuExternalPowerStatus + * This field returns the corresponding external power status: + * NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED + * NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS (0x134U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID (0x34U) + +typedef struct NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS { + NvU8 gpuCount; + NvU8 gpuBus[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; + NvU8 gpuExternalPowerStatus[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; +} NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS; + +/* Valid gpuExternalPowerStatus values */ +#define NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED 0U +#define NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED 1U + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS + * + * This command returns the caller's API access privileges using + * this client handle. + * + * privStatus + * This parameter returns a mask of possible access privileges: + * NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_PRIV_USER_FLAG + * The caller is running with elevated privileges + * NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_ROOT_HANDLE_FLAG + * Client is of NV01_ROOT class. + * NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG + * Client has PRIV bit set. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ + + +#define NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS (0x135U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID (0x35U) + +typedef struct NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS { + NvU8 privStatusFlags; +} NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS; + + +/* Valid privStatus values */ +#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_USER_FLAG (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_KERNEL_HANDLE_FLAG (0x00000002U) +#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG (0x00000004U) + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS + * + * The fabric manager (FM) notifies RM that fabric (system) is ready for peer to + * peer (P2P) use or still initializing the fabric. This command allows clients + * to query fabric status to allow P2P operations. + * + * Note, on systems where FM isn't used, RM just returns _SKIP. + * + * fabricStatus + * This parameter returns current fabric status: + * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP + * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED + * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS + * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_INVALID_PARAM_STRUCT + */ + +typedef enum NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS { + NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP = 1, + NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED = 2, + NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS = 3, + NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED = 4, +} NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS; + +#define NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS (0x136U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID (0x36U) + +typedef struct NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS { + NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS fabricStatus; +} NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS; + +/* + * NV0000_CTRL_VGPU_GET_VGPU_VERSION_INFO + * + * This command is used to query the range of VGX version supported. + * + * host_min_supported_version + * The minimum vGPU version supported by host driver + * host_max_supported_version + * The maximum vGPU version supported by host driver + * user_min_supported_version + * The minimum vGPU version set by user for vGPU support + * user_max_supported_version + * The maximum vGPU version set by user for vGPU support + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + */ +#define NV0000_CTRL_VGPU_GET_VGPU_VERSION (0x137U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID" */ + +/* + * NV0000_CTRL_VGPU_GET_VGPU_VERSION + */ +#define NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID (0x37U) + +typedef struct NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS { + NvU32 host_min_supported_version; + NvU32 host_max_supported_version; + NvU32 user_min_supported_version; + NvU32 user_max_supported_version; +} NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS; + +/* + * NV0000_CTRL_VGPU_SET_VGPU_VERSION + * + * This command is used to query whether pGPU is live migration capable or not. + * + * min_version + * The minimum vGPU version to be supported being set + * max_version + * The maximum vGPU version to be supported being set + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + */ +#define NV0000_CTRL_VGPU_SET_VGPU_VERSION (0x138U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID" */ + +/* + * NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS + */ +#define NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID (0x38U) + +typedef struct NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS { + NvU32 min_version; + NvU32 max_version; +} NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS; + +/* + * NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID + * + * This command is used to get a unique identifier for the instance of RM. + * The returned value will only change when the driver is reloaded. A previous + * value will never be reused on a given machine. + * + * rm_instance_id; + * The instance ID of the current RM instance + * + * Possible status values returned are: + * NV_OK + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_RM_INSTANCE_ID (0x139U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID" */ + +/* + * NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS + */ +#define NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID (0x39U) + +typedef struct NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS { + NV_DECLARE_ALIGNED(NvU64 rm_instance_id, 8); +} NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO + * + * This API is used to get the TPP(total processing power) and + * the rated TGP(total GPU power) from SBIOS. + * + * NVPCF is an acronym for Nvidia Platform Controllers and Framework + * which implements platform level policies. NVPCF is implemented in + * a kernel driver on windows. It is implemented in a user mode app + * called nvidia-powerd on Linux. + * + * gpuId + * GPU ID + * tpp + * Total processing power including CPU and GPU + * ratedTgp + * Rated total GPU Power + * subFunc + * NVPCF subfunction id + * ctgpOffsetmW + * Configurable TGP offset, in mW + * targetTppOffsetmW + * TPP, as offset in mW. + * maxOutputOffsetmW + * Maximum allowed output, as offset in mW. + * minOutputOffsetmW; + * Minimum allowed output, as offset in mW. + * + * Valid subFunc ids for NVPCF 1x include : + * NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED + * NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO (0x13bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID (0x3BU) + +typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS { + NvU32 gpuId; + NvU32 tpp; + NvU32 ratedTgp; + NvU32 subFunc; + NvU32 ctgpOffsetmW; + NvU32 targetTppOffsetmW; + NvU32 maxOutputOffsetmW; + NvU32 minOutputOffsetmW; +} NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS; + +/* Valid NVPCF subfunction case */ +#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED_CASE 0U +#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_CASE 1U +#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE 2U +#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_CASE 3U + +/* Valid NVPCF subfunction ids */ +#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED (0x00000000) +#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS (0x00000002) + +/* + * Defines for get supported sub functions bit fields + */ +#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED 0:0 +#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_YES 1 +#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_NO 0 + +/*! + * Config DSM 2x version specific defines + */ +#define NVPCF0100_CTRL_CONFIG_DSM_2X_VERSION (0x00000200) +#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED (0x00000000) +#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS (0x00000002) + +/* + * NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT + * + * This API is used to sync the external fabric management status with + * GSP-RM + * + * bExternalFabricMgmt + * Whether fabric is externally managed + * + * Possible status values returned are: + * NV_OK + */ +#define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT (0x13cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID (0x3CU) + +typedef struct NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS { + NvBool bExternalFabricMgmt; +} NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS; + +/* + * NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO + * + * This API is used to get information about the RM client + * database. + * + * clientCount [OUT] + * This field indicates the number of clients currently allocated. + * + * resourceCount [OUT] + * This field indicates the number of resources currently allocated + * across all clients. + * + */ +#define NV0000_CTRL_CMD_SYSTEM_GET_CLIENT_DATABASE_INFO (0x13dU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID (0x3DU) + +typedef struct NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS { + NvU32 clientCount; + NV_DECLARE_ALIGNED(NvU64 resourceCount, 8); +} NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 + * + * This command returns the current driver information in + * statically sized character arrays. + * + * driverVersionBuffer + * This field returns the version (NV_VERSION_STRING). + * versionBuffer + * This field returns the version (NV_BUILD_BRANCH_VERSION). + * titleBuffer + * This field returns the title (NV_DISPLAY_DRIVER_TITLE). + * changelistNumber + * This field returns the changelist value (NV_BUILD_CHANGELIST_NUM). + * officialChangelistNumber + * This field returns the last official changelist value + * (NV_LAST_OFFICIAL_CHANGELIST_NUM). + * + * Possible status values returned are: + * NV_OK + */ + +#define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE 256U +#define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 (0x13eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID (0x3EU) + +typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS { + char driverVersionBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; + char versionBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; + char titleBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; + NvU32 changelistNumber; + NvU32 officialChangelistNumber; +} NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL + * + * This API is used to get/set RMCTRL cache mode + * + * cmd [IN] + * GET - Gets RMCTRL cache mode + * SET - Sets RMCTRL cache mode + * + * mode [IN/OUT] + * On GET, this field is the output of current RMCTRL cache mode + * On SET, this field indicates the mode to set RMCTRL cache to + * Valid values for this parameter are: + * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE + * No get/set action to cache. + * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE + * Try to get from cache at the beginning of the control. + * Set cache after control finished if the control has not been cached. + * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY + * Do not get from cache. Set cache when control call finished. + * When setting the cache, verify the value in the cache is the same + * with the current control value if the control is already cached. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL (0x13fU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID (0x3FU) + +typedef struct NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS { + NvU32 cmd; + NvU32 mode; +} NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS; + +#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_GET (0x00000000U) +#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_SET (0x00000001U) + +#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE (0x00000000U) +#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE (0x00000001U) +#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY (0x00000002U) + +/* + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL + * + * This command is used to control PFM_REQ_HNDLR functionality. It allows control of + * GPU Performance Scaling (PFM_REQ_HNDLR), changing its operational parameters and read + * most PFM_REQ_HNDLR dynamic parameters. + * + * command + * This parameter specifies the command to execute. Invalid commands + * result in the return of an NV_ERR_INVALID_ARGUMENT status. + * locale + * This parameter indicates the specific locale to which the command + * 'command' is to be applied. +* Supported range of CPU/GPU {i = 0, ..., 255} + * data + * This parameter contains a command-specific data payload. It can + * be used to input data as well as output data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_COMMAND + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_DATA + * NV_ERR_INVALID_REQUEST + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL (0x140U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID (0x40U) + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS { + NvU16 command; + NvU16 locale; + NvU32 data; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS; + +/* + * Valid command values : + * + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT + * Is used to check if PFM_REQ_HNDLR was correctly initialized. + * Possible return (OUT) values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC + * Are used to stop/start PFM_REQ_HNDLR functionality and to get current status. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS + * Are used to control execution of PFM_REQ_HNDLR actions and to get current status. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC + * Are used to switch current PFM_REQ_HNDLR logic and to retrieve current logic. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF + * Will cause that all PFM_REQ_HNDLR actions will be NULL. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY + * Fuzzy logic will determine PFM_REQ_HNDLR actions based on current ruleset. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC + * Deterministic logic will define PFM_REQ_HNDLR actions based on current ruleset. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE + * Are used to set/retrieve system control preference. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT + * Are used to set/retrieve GPU2CPU pstate limits. + * IN/OUT values are four bytes packed into a 32-bit data field. + * The CPU cap index for GPU pstate 0 is in the lowest byte, the CPU cap + * index for the GPU pstate 3 is in the highest byte, etc. One + * special value is to disable the override to the GPU2CPU map: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE + * Is used to stop/start PFM_REQ_HNDLR PMU functionality. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE + * Is used to get the current status of PMU PFM_REQ_HNDLR. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER + * Are used to set/retrieve max power [mW] that system can provide. + * This is hardcoded PFM_REQ_HNDLR safety feature and logic/rules does not apply + * to this threshold. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET + * Are used to set/retrieve current system cooling budget [mW]. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD + * Are used to set/retrieve integration interval [sec]. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT + * Are used to set/retrieve used ruleset [#]. Value is checked + * against MAX number of rules for currently used PFM_REQ_HNDLR logic. Also COUNT + * provides a way to find out how many rules exist for the current control + * system. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST + * Is used to set/get a delay relative to now during which to allow unbound + * CPU performance. Units are seconds. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE + * Is used to override/get the actual power supply mode (AC/Battery). + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO + * Is used to get the Ventura system information for VCT tool + * Returned 32bit value should be treated as bitmask and decoded in + * following way: + * Encoding details are defined in objPFM_REQ_HNDLR.h refer to + * NV_PFM_REQ_HNDLR_SYS_SUPPORT_INFO and corresponding bit defines. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTION + * Is used to get the supported sub-functions defined in SBIOS. Returned + * value is a bitmask where each bit corresponds to different function: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE + * Are used to retrieve appropriate power measurements and their derivatives + * in [mW] for required locale. _BURDEN is defined only for _LOCALE_SYSTEM. + * _INTERMEDIATE is not defined for _LOCALE_SYSTEM, and takes an In value as + * index. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS + * Is used to retrieve parameters when adjusting raw sensor power reading. + * The values may come from SBIOS, VBIOS, registry or driver default. + * Possible IN value is the index of interested parameter. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE + * Are used to retrieve appropriate temperature measurements and their + * derivatives in [1/1000 Celsius]. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX + * Are used to retrieve CPU(x)/GPU(x) p-state or it's limits. + * Not applicable to _LOCALE_SYSTEM. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION + * Is used to retrieve last PFM_REQ_HNDLR action for given domain. + * Not applicable to _LOCALE_SYSTEM. + * Possible return (OUT) values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0 + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1 + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1 + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2 + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE + * Is used to set the power sensor simulator state. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE + * Is used to get the power simulator sensor simulator state. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA + * Is used to set power sensor simulator data + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA + * Is used to get power sensor simulator data + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK + * Is used to respond to the ACPI event triggered by SBIOS. RM will + * request value for budget and status, validate them, apply them + * and send ACK back to SBIOS. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT + * Is a test cmd that should notify SBIOS to send ACPI event requesting + * budget and status change. + */ +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_INVALID (0xFFFFU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT (0x0000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC (0x0001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC (0x0002U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS (0x0003U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS (0x0004U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC (0x0005U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC (0x0006U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE (0x0007U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE (0x0008U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT (0x0009U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT (0x000AU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE (0x000BU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE (0x000CU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER (0x0100U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER (0x0101U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET (0x0102U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET (0x0103U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD (0x0104U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD (0x0105U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET (0x0106U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET (0x0107U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT (0x0108U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST (0x0109U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST (0x010AU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE (0x010BU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE (0x010CU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO (0x010DU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTIONS (0x010EU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER (0x0200U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA (0x0201U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE (0x0202U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG (0x0203U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL (0x0204U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN (0x0205U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE (0x0206U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS (0x0210U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP (0x0220U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA (0x0221U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE (0x0222U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE (0x0240U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP (0x0241U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN (0x0242U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX (0x0243U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION (0x0244U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_SLFM_PRESENT (0x0245U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE (0x0250U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE (0x0251U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA (0x0252U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA (0x0253U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK (0x0320U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT (0x0321U) + +/* valid LOCALE values */ +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_INVALID (0xFFFFU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_SYSTEM (0x0000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_CPU(i) (0x0100+((i)%0x100)) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_GPU(i) (0x0200+((i)%0x100)) + +/* valid data values for enums */ +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID (0x80000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE (0xFFFFFFFFU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_ON (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS (0x00000004U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC (0x00000008U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC (0x00000010U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB (0x00000020U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS (0x00000040U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0 (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1 (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT (0x00000003U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1 (0x00000004U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2 (0x00000005U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM (0x00000006U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM (0x00000007U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_NO (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_YES (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_ON (0x00000001U) + +/* + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL + * + * This command allows execution of multiple PFM_REQ_HNDLRControl commands within one + * RmControl call. For practical reasons # of commands is limited to 16. + * This command shares defines with NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL. + * + * cmdCount + * Number of commands that should be executed. + * Less or equal to NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX. + * + * succeeded + * Number of commands that were succesully executed. + * Less or equal to NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX. + * Failing commands return NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID + * in their data field. + * + * cmdData + * Array of commands with following structure: + * command + * This parameter specifies the command to execute. + * Invalid commands result in the return of an + * NV_ERR_INVALID_ARGUMENT status. + * locale + * This parameter indicates the specific locale to which + * the command 'command' is to be applied. + * Supported range of CPU/GPU {i = 0, ..., 255} + * data + * This parameter contains a command-specific data payload. + * It is used both to input data as well as to output data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL (0x141U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX (16U) +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID (0x41U) + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS { + NvU32 cmdCount; + NvU32 succeeded; + + struct { + NvU16 command; + NvU16 locale; + NvU32 data; + } cmdData[NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX]; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL + * + * This command is used to execute general PFM_REQ_HNDLR Functions, most dealing with + * calling SBIOS, or retrieving cached sensor and PFM_REQ_HNDLR state data. + * + * version + * This parameter specifies the version of the interface. Legal values + * for this parameter are 1. + * cmd + * This parameter specifies the PFM_REQ_HNDLR API to be invoked. + * Valid values for this parameter are: + * NV0000_CTRL_PFM_REQ_HNDLR_CMD_GET_THERM_LIMIT + * This command gets the temperature limit for thermal controller. When + * this command is specified the input parameter contains ???. + * NV0000_CTRL_PFM_REQ_HNDLR_CMD_SET_THERM_LIMIT + * This command set the temperature limit for thermal controller. When + * this command is specified the input parameter contains ???. + * input + * This parameter specifies the cmd-specific input value. + * result + * This parameter returns the cmd-specific output value. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL (0x142U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID (0x42U) + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS { + NvU32 cmd; + NvS32 input[2]; + NvS32 result[4]; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS; + +/* valid version values */ +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_PSP_CURRENT_VERSION (0x00010000U) + +/* valid cmd values */ +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_THERM_LIMIT (0x00000002U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_THERMAL_LIMIT (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MIN_LIMIT (0x00000001U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MAX_LIMIT (0x00000002U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE (0x00000003U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_THERM_LIMIT (0x00000003U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_THERMAL_LIMIT (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA (0x00000004U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DOWN_N_DELTA (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA (0x00000005U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DOWN_N_DELTA (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA (0x00000006U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_HOLD_DELTA (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA (0x00000007U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_HOLD_DELTA (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA (0x00000008U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_UP_DELTA (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA (0x00000009U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_UP_DELTA (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA (0x0000000AU) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_ENGAGE_DELTA (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA (0x0000000BU) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_ENGAGE_DELTA (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000CU) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000DU) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_STATUS (0x00000016U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_STATUS (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_STATUS (0x00000017U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_STATUS (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM (0x00000018U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_CPU_SET_UTIL_AVG_NUM (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM (0x00000019U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_CPU_GET_UTIL_AVG_NUM (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PERF_SENSOR (0x0000001AU) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_NEXT_EXPECTED_POLL (0x00000001U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_VALUE (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_AVAILABLE (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_CALL_ACPI (0x0000001BU) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_CMD (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_PARAM_IN (0x00000001U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_1 (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_2 (0x00000001U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_STATUS (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_VERSION (0x00000001U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_SZ (0x00000002U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_SZ (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_COUNT (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_IGPU_TURBO (0x0000001CU) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SET_IGPU_TURBO (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERIOD (0x00000026U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERIOD (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERIOD (0x00000027U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERIOD (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_NUDGE_FACTOR (0x00000028U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_UP (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_DOWN (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_NUDGE_FACTOR (0x00000029U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_UP (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_DOWN (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES (0x0000002AU) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES (0x0000002BU) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERF_LIMITS (0x0000002CU) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_UPPER (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_LOWER (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERF_LIMITS (0x0000002DU) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_UPPER (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_LOWER (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PM1_AVAILABLE (0x0000002EU) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_PM1_AVAILABLE (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PM1_AVAILABLE (0x0000002FU) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_PM1_AVAILABLE (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS (0x00000044U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS (0x00000045U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT (0x00000046U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ (0000000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT (0x00000047U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ (0000000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM (0x00000048U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_INDEX (0000000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_AVAILABLE_MASK (0000000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM (0x00000049U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX (0000000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX_MAX (2U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX 7:0 +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_MAXPERF (0U) +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_BALANCED (1U) +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_QUIET (2U) +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID (0xFFU) +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK 15:8 +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK_INVALID (0U) + +/* valid PS_STATUS result values */ +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_OFF (0U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_ON (1U) + +#define PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK 32U +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS { + NvU32 objHndl; + NvU32 blockId; + NvU32 nextExpectedSampleTimems; + NvU32 countersReq; + NvU32 countersReturned; + NvU32 counterBlock[PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK]; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS; + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS (0x146U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x46" */ + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS (0x147U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x47" */ + +/* + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI + * + * This command allows users to call PFM_REQ_HNDLR ACPI commands for testing purposes. + * + * cmd + * This parameter specifies the PFM_REQ_HNDLR ACPI command to execute. + * + * input + * This parameter specified the cmd-dependent input value. + * + * resultSz + * This parameter returns the size (in bytes) of the valid data + * returned in the result parameter. + * + * result + * This parameter returns the results of the specified cmd. + * The maximum size (in bytes) of this returned data will + * not exceed PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE + * + * PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE + * The size of buffer (result) in unit of NvU32. + * The smallest value is sizeof(PSS_ENTRY)*ACPI_PSS_ENTRY_MAX. + * Since the prior one is 24 bytes, and the later one is 48, + * this value cannot be smaller than 288. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT, + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_PERMISSIONS + * + */ +#define PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID (0x43U) + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS { + NvU32 cmd; + NvU32 input; + NvU32 resultSz; + NvU32 result[PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE]; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS; + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI (0x143U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PFM_REQ_HNDLR (0x00008000U) + +/* + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA + * + * This command is used to read FRL data based on need. + * + * nextSampleNumber + * This parameter returns the counter of next sample which is being filled. + * samples + * This parameter returns the frame time, render time, target time, client ID + * with one reserve bit for future use. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA (0x144U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE 64U + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE { + NvU16 frameTime; + NvU16 renderTime; + NvU16 targetTime; + NvU8 sleepTime; + NvU8 sampleNumber; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE; + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID (0x44U) + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS { + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE samples[NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE]; + NvU8 nextSampleNumber; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA + * + * This command is used to write FRM data based on need. + * + * frameTime + * This parameter contains the frame time of current frame. + * renderTime + * This parameter contains the render time of current frame. + * targetTime + * This parameter contains the target time of current frame. + * sleepTime + * This parameter contains the sleep duration inserted by FRL for the latest frame. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA (0x145U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID (0x45U) + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS { + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE sampleData; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS; + +/* _ctrl0000system_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h new file mode 100644 index 0000000..d55703d --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h @@ -0,0 +1,435 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000unix.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +/* NV01_ROOT (client) Linux control commands and parameters */ + +/* + * NV0000_CTRL_CMD_OS_UNIX_FLUSH_USER_CACHE + * + * This command may be used to force a cache flush for a range of virtual addresses in + * memory. Can be used for either user or kernel addresses. + * + * offset, length + * These parameters specify the offset within the memory block + * and the number of bytes to flush/invalidate + * cacheOps + * This parameter flags whether to flush, invalidate or do both. + * Possible values are: + * NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH + * NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_INVALIDATE + * NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH_INVALIDATE + * hDevice + * This parameter is the handle to the device + * hObject + * This parameter is the handle to the memory structure being operated on. + * internalOnly + * Intended for internal use unless client is running in MODS UNIX environment, + * in which case this parameter specify the virtual address of the memory block + * to flush. + * + * Possible status values are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_COMMAND + * NV_ERR_INVALID_LIMIT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_OS_UNIX_FLUSH_USER_CACHE (0x3d02) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 length, 8); + NvU32 cacheOps; + NvHandle hDevice; + NvHandle hObject; + NV_DECLARE_ALIGNED(NvU64 internalOnly, 8); +} NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS; + +#define NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH (0x00000001) +#define NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_INVALIDATE (0x00000002) +#define NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH_INVALIDATE (0x00000003) + + +/* + * NV0000_CTRL_CMD_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR + * + * This command is used to get the control file descriptor. + * + * Possible status values returned are: + * NV_OK + * + */ +#define NV0000_CTRL_CMD_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR (0x3d04) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | 0x4" */ + +typedef struct NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS { + NvS32 fd; +} NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS; + +typedef enum NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE { + NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_NONE = 0, + NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM = 1, +} NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE; + +typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECT { + NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE type; + + union { + struct { + NvHandle hDevice; + NvHandle hParent; + NvHandle hObject; + } rmObject; + } data; +} NV0000_CTRL_OS_UNIX_EXPORT_OBJECT; + +/* + * NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD + * + * This command may be used to export NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE + * object to file descriptor. + * + * Note that the 'fd' parameter is an input parameter at the kernel level, but + * an output parameter for usermode RMAPI clients -- the RMAPI library will + * open a new FD automatically if a usermode RMAPI client exports an object. + * + * Kernel-mode RM clients can export an object to an FD in two steps: + * 1. User client calls this RMControl with the flag 'EMPTY_FD_TRUE' to create + * an empty FD to receive the object, then passes that FD to the kernel-mode + * RM client. + * 2. Kernel-mode RM client fills in the rest of the + * NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS as usual and calls RM to + * associate its desired RM object with the empty FD from its usermode + * client. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_PARAMETER + */ +#define NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD (0x3d05) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS { + NV0000_CTRL_OS_UNIX_EXPORT_OBJECT object; /* IN */ + NvS32 fd; /* IN/OUT */ + NvU32 flags; /* IN */ +} NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS; + +/* + * If EMPTY_FD is TRUE, the 'fd' will be created but no object will be + * associated with it. The hDevice parameter is still required, to determine + * the correct device node on which to create the file descriptor. + * (An empty FD can then be passed to a kernel-mode driver to associate it with + * an actual object.) + */ +#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD 0:0 +#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_FALSE (0x00000000) +#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_TRUE (0x00000001) + +/* + * NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD + * + * This command may be used to import back + * NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE object from file descriptor. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_PARAMETER + */ +#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD (0x3d06) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS { + NvS32 fd; /* IN */ + NV0000_CTRL_OS_UNIX_EXPORT_OBJECT object; /* IN */ +} NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS; + +/* + * NV0000_CTRL_CMD_OS_GET_GPU_INFO + * + * This command will query the OS specific info for the specified GPU. + * + * gpuId + * This parameter should specify a valid GPU ID value. If there + * is no GPU present with the specified ID, a status of + * NV_ERR_INVALID_ARGUMENT is returned. + * minorNum + * This parameter returns minor number of device node. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_OS_GET_GPU_INFO (0x3d07) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | 0x7" */ + +typedef struct NV0000_CTRL_OS_GET_GPU_INFO_PARAMS { + NvU32 gpuId; /* IN */ + NvU32 minorNum; /* OUT */ +} NV0000_CTRL_OS_GET_GPU_INFO_PARAMS; + +/* + * NV0000_CTRL_CMD_OS_UNIX_GET_EXPORT_OBJECT_INFO + * + * This command will query the deviceInstance for the specified FD + * which is referencing an exported object. + * + * fd + * File descriptor parameter is referencing an exported object on a Unix system. + * + * deviceInstatnce + * This parameter returns a deviceInstance on which the object is located. + * + * NV_MAX_DEVICES is returned if the object is parented by a client instead + * of a device. + * + * maxObjects + * This parameter returns the maximum number of object handles that may be + * contained in the file descriptor. + * + * metadata + * This parameter returns the user metadata passed into the + * _EXPORT_OBJECTS_TO_FD control call. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OBJECT_NOT_FOUND + */ + +#define NV0000_CTRL_CMD_OS_UNIX_GET_EXPORT_OBJECT_INFO (0x3d08) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE 64 + +#define NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS { + NvS32 fd; /* IN */ + NvU32 deviceInstance; /* OUT */ + NvU16 maxObjects; /* OUT */ + NvU8 metadata[NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE]; /* OUT */ +} NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS; + +/* + * NV0000_CTRL_CMD_OS_UNIX_REFRESH_RMAPI_DEVICE_LIST + * + * This command will re-fetch probed GPUs information and update RMAPI library's + * internal detected GPU context information accordingly. Without this, GPUs + * attached to RM after RMAPI client initialization will not be accessible and + * all RMAPI library calls will fail on them. + * Currently this is used by NVSwitch Fabric Manager in conjunction with NVSwitch + * Shared Virtualization feature where GPUs are hot-plugged to OS/RM (by Hypervisor) + * and Fabric Manager is signaled externally by the Hypervisor to initialize those GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_OPERATING_SYSTEM + */ + +#define NV0000_CTRL_CMD_OS_UNIX_REFRESH_RMAPI_DEVICE_LIST (0x3d09) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | 0x9" */ + +/* + * This control call has been deprecated. It will be deleted soon. + * Use NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD (singular) or + * NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD (plural) instead. + */ +#define NV0000_CTRL_CMD_OS_UNIX_CREATE_EXPORT_OBJECT_FD (0x3d0a) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_BUFFER_SIZE NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE + +#define NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS { + NvHandle hDevice; /* IN */ + NvU16 maxObjects; /* IN */ + NvU8 metadata[NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_BUFFER_SIZE]; /* IN */ + NvS32 fd; /* IN/OUT */ +} NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS; + +/* + * NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD + * + * Exports RM handles to an fd that was provided, also creates an FD if + * requested. + * + * The objects in the 'handles' array are exported into the fd + * as the range [index, index + numObjects). + * + * If index + numObjects is greater than the maxObjects value used + * to create the file descriptor, NV_ERR_INVALID_PARAMETER is returned. + * + * If 'numObjects and 'index' overlap with a prior call, the newer call's RM object + * handles will overwrite the previously exported handles from the previous call. + * This overlapping behavior can also be used to unexport a handle by setting + * the appropriate object in 'objects' to 0. + * + * fd + * A file descriptor. If -1, a new FD will be created. + * + * hDevice + * The owning device of the objects to be exported (must be the same for + * all objects). + * + * maxObjects + * The total number of objects that the client wishes to export to the FD. + * This parameter will be honored only when the FD is getting created. + * + * metadata + * A buffer for clients to write some metadata to and pass to the importing + * client. This parameter will be honored only when the FD is getting + * created. + * + * objects + * Array of RM object handles to export to the fd. + * + * numObjects + * The number of handles the user wishes to export in this call. + * + * index + * The index into the export fd at which to start exporting the handles in + * 'objects' (for use in iterative calls). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OUT_OF_RANGE + * NV_ERR_NOT_SUPPORTED + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_OBJECT_HANDLE + */ +#define NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD (0x3d0b) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_MAX_OBJECTS 512 + +#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS { + NvS32 fd; /* IN/OUT */ + NvHandle hDevice; /* IN */ + NvU16 maxObjects; /* IN */ + NvU8 metadata[NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE]; /* IN */ + NvHandle objects[NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_MAX_OBJECTS]; /* IN */ + NvU16 numObjects; /* IN */ + NvU16 index; /* IN */ +} NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS; + +/* + * NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECTS_FROM_FD + * + * This command can be used to import back RM handles + * that were exported to an fd using the + * NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD control call. + * + * If index + numObjects is greater than the maxObjects value used + * to create the file descriptor, NV_ERR_INVALID_PARAMETER is returned + * and no objects are imported. + * + * For each valid handle in the 'objects' array parameter at index 'i', + * the corresponding object handle at index ('i' + 'index') contained by + * the fd will be imported. If the object at index ('i' + 'index') has + * not been exported into the fd, no object will be imported. + * + * If any of handles contained in the 'objects' array parameter are invalid + * and the corresponding export object handle is valid, + * NV_ERR_INVALID_PARAMETER will be returned and no handles will be imported. + * + * fd + * The export fd on which to import handles out of. + * + * hParent + * The parent RM handle of which all of the exported objects will + * be duped under. + * + * objects + * An array of RM handles. The exported objects will be duped under + * these handles during the import process. + * + * objectTypes + * An array of RM handle types. The type _NONE will be returned if + * the object was not imported. Other possible object types are + * mentioned below. + * + * numObjects + * The number of valid object handles in the 'objects' array. This should + * be set to the number of objects that the client wishes to import. + * + * index + * The index into the fd in which to start importing from. For + * use in iterative calls. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OUT_OF_RANGE + * NV_ERR_NOT_SUPPORTED + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_PARAMETER + */ +#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECTS_FROM_FD (0x3d0c) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID" */ + +// +// TODO Bump this back up to 512 after the FLA revamp is complete +// +#define NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS 128 + +#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_NONE 0 +#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_VIDMEM 1 +#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_SYSMEM 2 +#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC 3 + + + +#define NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS { + NvS32 fd; /* IN */ + NvHandle hParent; /* IN */ + NvHandle objects[NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS]; /* IN */ + NvU8 objectTypes[NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS]; /* OUT */ + NvU16 numObjects; /* IN */ + NvU16 index; /* IN */ +} NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS; + +/* _ctrl0000unix_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h new file mode 100644 index 0000000..671c1a3 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h @@ -0,0 +1,78 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0000/ctrl0000vgpu.finn +// + +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrla081.h" +#include "class/cl0000.h" +#include "nv_vgpu_types.h" +/* + * NV0000_CTRL_CMD_VGPU_GET_START_DATA + * + * This command gets data associated with NV0000_NOTIFIERS_VGPU_MGR_START to + * start VGPU process. + * + * mdevUuid + * This parameter gives mdev device UUID for which nvidia-vgpu-mgr should + * init process. + * + * qemuPid + * This parameter specifies the QEMU process ID of the VM. + * + * gpuPciId + * This parameter provides gpuId of GPU on which vgpu device is created. + * + * configParams + * This parameter specifies the configuration parameters for vGPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_EVENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_CLIENT + * + */ +#define NV0000_CTRL_CMD_VGPU_GET_START_DATA (0xc01) /* finn: Evaluated from "(FINN_NV01_ROOT_VGPU_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_GET_START_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_VGPU_GET_START_DATA_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_VGPU_GET_START_DATA_PARAMS { + NvU8 mdevUuid[VM_UUID_SIZE]; + NvU8 configParams[1024]; + NvU32 qemuPid; + NvU32 gpuPciId; + NvU16 vgpuId; + NvU32 gpuPciBdf; +} NV0000_CTRL_VGPU_GET_START_DATA_PARAMS; + +/* _ctrl0000vgpu_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0002.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0002.h new file mode 100644 index 0000000..046c931 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0002.h @@ -0,0 +1,178 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0002.finn +// + +#include "ctrl/ctrlxxxx.h" +#define NV0002_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0002, NV0002_CTRL_##cat, idx) + +/* Client command categories (6bits) */ +#define NV0002_CTRL_RESERVED (0x00) +#define NV0002_CTRL_DMA (0x01) + + +/* + * NV0002_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ + +#define NV0002_CTRL_CMD_NULL (0x20000) /* finn: Evaluated from "(FINN_NV01_CONTEXT_DMA_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV0002_CTRL_CMD_UPDATE_CONTEXTDMA + * + * This command will update the parameters of the specified context dma. The + * context dma must be bound to a display channel. The update is limited + * to the display view of the context dma. Other use cases will continue to + * use the original allocation parameters. + * + * This is used on platforms where memory may be moved by the operating + * system after allocation. + * + * This control call supports the NVOS54_FLAGS_LOCK_BYPASS flag. + * + * baseAddress + * This parameter, if selected by flags, indicates the new baseAddress for + * the ctxdma + * limit + * This parameter, if selected by flags, indicates the new limit of the + * ctxdma. + * hCtxDma + * ContextDma handle on which to operate. Must match the handle given to the control + * call. + * hChannel + * Display channel handle. This field is ignored. + * hintHandle + * Hint value returned from HeapAllocHint which encodes information about + * the surface. This is used by chips without generic kind. Newer chips + * use the COMPR_INFO flag and the hintHandle must be zero. + * flags + * This parameter specifies flags which indicate which other parameters are + * valid. + * FLAGS_PAGESIZE updates the context DMA pagesize field, if not _DEFAULT + * FLAGS_USE_COMPR_INFO uses the surface format specified in the params, instead of hintHandle. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_NOT_SUPPORTED + */ +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA (0x20101) /* finn: Evaluated from "(FINN_NV01_CONTEXT_DMA_DMA_INTERFACE_ID << 8) | NV0002_CTRL_UPDATE_CONTEXTDMA_PARAMS_MESSAGE_ID" */ + +#define NV0002_CTRL_UPDATE_CONTEXTDMA_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0002_CTRL_UPDATE_CONTEXTDMA_PARAMS { + NV_DECLARE_ALIGNED(NvU64 baseAddress, 8); + NV_DECLARE_ALIGNED(NvU64 limit, 8); + NvHandle hSubDevice; + NvHandle hCtxDma; + NvHandle hChannel; + NvHandle hintHandle; + NvU32 flags; +} NV0002_CTRL_UPDATE_CONTEXTDMA_PARAMS; + +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_BASEADDRESS 0:0 +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_BASEADDRESS_INVALID (0x00000000) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_BASEADDRESS_VALID (0x00000001) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_LIMIT 1:1 +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_LIMIT_INVALID (0x00000000) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_LIMIT_VALID (0x00000001) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_HINT 2:2 +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_HINT_INVALID (0x00000000) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_HINT_VALID (0x00000001) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_PAGESIZE 4:3 +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_PAGESIZE_DEFAULT (0x00000000) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_PAGESIZE_4K (0x00000001) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_PAGESIZE_BIG (0x00000002) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_USE_COMPR_INFO 6:5 +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_USE_COMPR_INFO_NONE (0x00000000) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_USE_COMPR_INFO_FORMAT_PITCH (0x00000001) +#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_USE_COMPR_INFO_FORMAT_BLOCK_LINEAR (0x00000002) + +/* + * NV0002_CTRL_CMD_BIND_CONTEXTDMA + * + * Bind a context dma to a display channel. Binding is no longer required for + * Host channels, but does silently succeed. + * + * This control call supports the NVOS54_FLAGS_LOCK_BYPASS flag. + * + * This control replaces the obsolete RmBindContextDma() API. + * + * hChannel + * The channel for ctxdma bind + * + * Possible error codes include + * NV_OK + * NV_ERR_TOO_MANY_PRIMARIES hash table is full + * NV_ERR_NO_MEMORY instance memory is full + * NV_ERR_INVALID_OFFSET surface is not correctly aligned + * NV_ERR_STATE_IN_USE context dma was already bound given channel + */ +#define NV0002_CTRL_CMD_BIND_CONTEXTDMA (0x20102) /* finn: Evaluated from "(FINN_NV01_CONTEXT_DMA_DMA_INTERFACE_ID << 8) | NV0002_CTRL_BIND_CONTEXTDMA_PARAMS_MESSAGE_ID" */ + +#define NV0002_CTRL_BIND_CONTEXTDMA_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0002_CTRL_BIND_CONTEXTDMA_PARAMS { + NvHandle hChannel; +} NV0002_CTRL_BIND_CONTEXTDMA_PARAMS; + +/* + * NV0002_CTRL_CMD_UNBIND_CONTEXTDMA + * + * Unbind a context dma from a display channel. + * + * This control call supports the NVOS54_FLAGS_LOCK_BYPASS flag. + * + * hChannel + * The display channel to unbind from + * + * Possible error codes include + * NV_OK + * NV_ERR_INVALID_STATE channel was not bound + */ +#define NV0002_CTRL_CMD_UNBIND_CONTEXTDMA (0x20103) /* finn: Evaluated from "(FINN_NV01_CONTEXT_DMA_DMA_INTERFACE_ID << 8) | NV0002_CTRL_UNBIND_CONTEXTDMA_PARAMS_MESSAGE_ID" */ + +#define NV0002_CTRL_UNBIND_CONTEXTDMA_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0002_CTRL_UNBIND_CONTEXTDMA_PARAMS { + NvHandle hChannel; +} NV0002_CTRL_UNBIND_CONTEXTDMA_PARAMS; + +/* _ctrl0002.h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0004.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0004.h new file mode 100644 index 0000000..91431ce --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0004.h @@ -0,0 +1,93 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0004.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV01_TIMER control commands and parameters */ + +#define NV0004_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0004, NV0004_CTRL_##cat, idx) + +/* NV01_TIMER command categories (8bits) */ +#define NV0004_CTRL_RESERVED (0x00) +#define NV0004_CTRL_TMR (0x01) + +/* + * NV0004_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0004_CTRL_CMD_NULL (0x40000) /* finn: Evaluated from "(FINN_NV01_TIMER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV0004_CTRL_CMD_TMR_SET_ALARM_NOTIFY + * + * This command can be used to set a PTIMER alarm to trigger at the + * specified time in the future on the subdevice associated with this + * NV01_TIMER object instance. + * + * hEvent + * This parameter specifies the handle of an NV01_EVENT object instance + * that is to be signaled when the alarm triggers. This NV01_EVENT + * object instance must have been allocated with this NV01_TIMER object + * instance as its parent. If this parameter is set to NV01_NULL_OBJECT + * then all NV01_EVENT object instances associated with this NV01_TIMER + * object instance are signaled. + * alarmTimeUsecs + * This parameter specifies the relative time in nanoseconds at which + * the alarm should trigger. Note that the accuracy between the alarm + * trigger and the subsequent notification to the caller can vary + * depending on system conditions. + * + * Possible status values returned include: + * NVOS_STATUS_SUCCES + * NVOS_STATUS_INVALID_PARAM_STRUCT + * NVOS_STATUS_INVALID_OBJECT_HANDLE + */ + +#define NV0004_CTRL_CMD_TMR_SET_ALARM_NOTIFY (0x40110) /* finn: Evaluated from "(FINN_NV01_TIMER_TMR_INTERFACE_ID << 8) | NV0004_CTRL_TMR_SET_ALARM_NOTIFY_PARAMS_MESSAGE_ID" */ + +#define NV0004_CTRL_TMR_SET_ALARM_NOTIFY_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV0004_CTRL_TMR_SET_ALARM_NOTIFY_PARAMS { + NvHandle hEvent; + NV_DECLARE_ALIGNED(NvU64 alarmTimeNsecs, 8); +} NV0004_CTRL_TMR_SET_ALARM_NOTIFY_PARAMS; + +/* _ctrl0004_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl000f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl000f.h new file mode 100644 index 0000000..ecabf33 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl000f.h @@ -0,0 +1,85 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl000f.finn +// + +#include "ctrl/ctrlxxxx.h" + +#define NV000F_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x000f, NV000F_CTRL_##cat, idx) + +/* Client command categories (6bits) */ +#define NV000F_CTRL_RESERVED (0x00U) +#define NV000F_CTRL_FM (0x01U) +#define NV000F_CTRL_RESERVED2 (0x02U) + +/* + * NV000f_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV000F_CTRL_CMD_NULL (0xf0000U) /* finn: Evaluated from "(FINN_FABRIC_MANAGER_SESSION_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV000F_CTRL_CMD_SET_FM_STATE + * + * This command will notify RM that the fabric manager is initialized. + * + * RM would block P2P operations such as P2P capability reporting, NV50_P2P object + * allocation etc. until the notification received. + * + * Possible status values returned are: + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + * NV_OK + */ +#define NV000F_CTRL_CMD_SET_FM_STATE (0xf0101U) /* finn: Evaluated from "(FINN_FABRIC_MANAGER_SESSION_FM_INTERFACE_ID << 8) | 0x1" */ + +/* + * NV000F_CTRL_CMD_CLEAR_FM_STATE + * + * This command will notify RM that the fabric manager is uninitialized. + * + * RM would block P2P operations such as P2P capability reporting, NV50_P2P object + * allocation etc. as soon as the notification received. + * + * Possible status values returned are: + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + * NV_OK + */ +#define NV000F_CTRL_CMD_CLEAR_FM_STATE (0xf0102U) /* finn: Evaluated from "(FINN_FABRIC_MANAGER_SESSION_FM_INTERFACE_ID << 8) | 0x2" */ + +/* _ctrl000f.h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0020.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0020.h new file mode 100644 index 0000000..60f6684 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0020.h @@ -0,0 +1,80 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0020.finn +// + +#include "ctrl/ctrlxxxx.h" +#define NV0020_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0x0020, NV0020_CTRL_##cat, idx) + +/* NV0020_GPU_MANAGEMENT command categories (6bits) */ +#define NV0020_CTRL_RESERVED (0x00) +#define NV0020_CTRL_GPU_MGMT (0x01) + +/* + * NV0020_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0020_CTRL_CMD_NULL (0x200000) /* finn: Evaluated from "(FINN_NV0020_GPU_MANAGEMENT_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* Maximum possible number of bytes of GID information */ +#define NV0020_GPU_MAX_GID_LENGTH (0x00000100) + +/* + * NV0020_CTRL_CMD_GPU_MGMT_SET_SHUTDOWN_STATE + * + * This command modifies GPU zero power state for the desired GPU in the + * database. This state is set by a privileged client, after the GPU is + * completely unregistered from RM as well as PCI subsystem. On Linux, + * clients perform this operation through pci-sysfs. + * This control call requires admin privileges. + * + * uuid (INPUT) + * The UUID of the gpu. + * Supports binary format and SHA-1 type. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0020_CTRL_CMD_GPU_MGMT_SET_SHUTDOWN_STATE (0x200101) /* finn: Evaluated from "(FINN_NV0020_GPU_MANAGEMENT_GPU_MGMT_INTERFACE_ID << 8) | NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS { + NvU8 uuid[NV0020_GPU_MAX_GID_LENGTH]; +} NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS; + +/* _ctrl0020_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl003e.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl003e.h new file mode 100644 index 0000000..880fcc8 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl003e.h @@ -0,0 +1,191 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl003e.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV01_MEMORY_SYSTEM control commands and parameters */ + +#define NV003E_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x003E, NV003E_CTRL_##cat, idx) + +/* NV01_MEMORY_SYSTEM command categories (6bits) */ +#define NV003E_CTRL_RESERVED (0x00) +#define NV003E_CTRL_MEMORY (0x01) + +/* + * NV003E_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV003E_CTRL_CMD_NULL (0x3e0000) /* finn: Evaluated from "(FINN_NV01_MEMORY_SYSTEM_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV003E_CTRL_CMD_GET_SURFACE_PHYS_ATTR + * + * This command returns attributes associated with the memory object + * at the given offset. The architecture dependent return parameter + * comprFormat determines the meaningfulness (or not) of comprOffset. + * + * This call is currently only supported in the MODS environment. + * + * memOffset + * This parameter is both an input and an output. As input, this + * parameter holds an offset into the memory surface. The return + * value is the physical address of the surface at the given offset. + * memFormat + * This parameter returns the memory kind of the surface. + * comprOffset + * This parameter returns the compression offset of the surface. + * comprFormat + * This parameter returns the type of compression of the surface. + * gpuCacheAttr + * gpuCacheAttr returns the gpu cache attribute of the surface. + * Legal return values for this field are + * NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN + * NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED + * NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED + * gpuP2PCacheAttr + * gpuP2PCacheAttr returns the gpu peer-to-peer cache attribute of the surface. + * Legal return values for this field are + * NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN + * NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED + * NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED + * mmuContext + * mmuContext returns the requested type of physical address + * Legal return values for this field are + * TEGRA_VASPACE_A -- return the non-GPU device physical address ( the system physical address itself) for Tegra engines. + * returns the system physical address, may change to use a class value in future. + * FERMI_VASPACE_A -- return the GPU device physical address( the system physical address, or the SMMU VA) for Big GPU engines. + * 0 -- return the GPU device physical address( the system physical address, or the SMMU VA) for Big GPU engines. + * use of zero may be deprecated in future. + * contigSegmentSize + * If the underlying surface is physically contiguous, this parameter + * returns the size in bytes of the piece of memory starting from + * the offset specified in the memOffset parameter extending to the last + * byte of the surface. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_BAD_OBJECT_HANDLE + * NVOS_STATUS_BAD_OBJECT_PARENT + * NVOS_STATUS_NOT_SUPPORTED + * + */ +#define NV003E_CTRL_CMD_GET_SURFACE_PHYS_ATTR (0x3e0101) /* finn: Evaluated from "(FINN_NV01_MEMORY_SYSTEM_MEMORY_INTERFACE_ID << 8) | NV003E_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS_MESSAGE_ID" */ + +#define NV003E_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV003E_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS { + NV_DECLARE_ALIGNED(NvU64 memOffset, 8); + NvU32 memFormat; + NvU32 comprOffset; + NvU32 comprFormat; + NvU32 gpuCacheAttr; + NvU32 gpuP2PCacheAttr; + NvU32 mmuContext; + NV_DECLARE_ALIGNED(NvU64 contigSegmentSize, 8); +} NV003E_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS; + +/* valid gpuCacheAttr return values */ +#define NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN (0x00000000) +#define NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED (0x00000001) +#define NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED (0x00000002) + +/* NV003E_CTRL_CMD_GET_SURFACE_NUM_PHYS_PAGES + * + * This command returns the number of physical pages associated with the + * memory object. + * + * This call is currently only implemented on Linux and assumes that linux + * kernel in which RM module will be loaded has same page size as defined + * in linux kernel source with which RM module was built. + * + * numPages + * This parameter returns total number of physical pages associated with + * the memory object. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV003E_CTRL_CMD_GET_SURFACE_NUM_PHYS_PAGES (0x3e0102) /* finn: Evaluated from "(FINN_NV01_MEMORY_SYSTEM_MEMORY_INTERFACE_ID << 8) | NV003E_CTRL_GET_SURFACE_NUM_PHYS_PAGES_PARAMS_MESSAGE_ID" */ + +#define NV003E_CTRL_GET_SURFACE_NUM_PHYS_PAGES_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV003E_CTRL_GET_SURFACE_NUM_PHYS_PAGES_PARAMS { + NvU32 numPages; +} NV003E_CTRL_GET_SURFACE_NUM_PHYS_PAGES_PARAMS; + + +/* NV003E_CTRL_CMD_GET_SURFACE_PHYS_PAGES + * + * This command returns physical pages associated with the memory object. + * + * This call is currently only implemented on Linux and assumes that linux + * kernel in which RM module will be loaded has same page size as defined + * in linux kernel source with which RM module was built. + * + * pPages + * This parameter returns physical pages associated with the memory object. + * + * numPages + * This parameter is both an input and an output. As an input parameter, + * it's value indicates maximum number of physical pages to be copied to + * pPages. As an output parameter, it's value indicates number of physical + * pages copied to pPages. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV003E_CTRL_CMD_GET_SURFACE_PHYS_PAGES (0x3e0103) /* finn: Evaluated from "(FINN_NV01_MEMORY_SYSTEM_MEMORY_INTERFACE_ID << 8) | NV003E_CTRL_GET_SURFACE_PHYS_PAGES_PARAMS_MESSAGE_ID" */ + +#define NV003E_CTRL_GET_SURFACE_PHYS_PAGES_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV003E_CTRL_GET_SURFACE_PHYS_PAGES_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pPages, 8); + NvU32 numPages; +} NV003E_CTRL_GET_SURFACE_PHYS_PAGES_PARAMS; + +/* _ctrl003e_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0041.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0041.h new file mode 100644 index 0000000..322393d --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0041.h @@ -0,0 +1,450 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0041.finn +// + +#include "nvos.h" +#include "ctrl/ctrlxxxx.h" +/* NV04_MEMORY control commands and parameters */ + +#define NV0041_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0041, NV0041_CTRL_##cat, idx) + +/* NV04_MEMORY command categories (6bits) */ +#define NV0041_CTRL_RESERVED (0x00) +#define NV0041_CTRL_MEMORY (0x01) + +/* + * NV0041_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0041_CTRL_CMD_NULL (0x410000) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR + * + * This command returns attributes associated with the memory object + * at the given offset. The architecture dependent return parameter + * comprFormat determines the meaningfulness (or not) of comprOffset. + * + * This call is only currently supported in the MODS environment. + * + * memOffset + * This parameter is both an input and an output. As input, this + * parameter holds an offset into the memory surface. The return + * value is the physical address of the surface at the given offset. + * memFormat + * This parameter returns the memory kind of the surface. + * comprOffset + * This parameter returns the compression offset of the surface. + * comprFormat + * This parameter returns the type of compression of the surface. + * memAperture + * The aperture of the surface is returned in this field. + * Legal return values for this parameter are + * NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_VIDMEM + * NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_SYSMEM + * gpuCacheAttr + * gpuCacheAttr returns the gpu cache attribute of the surface. + * Legal return values for this field are + * NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN + * NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED + * NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED + * gpuP2PCacheAttr + * gpuP2PCacheAttr returns the gpu peer-to-peer cache attribute of the surface. + * Legal return values for this field are + * NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN + * NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED + * NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED + * mmuContext + * mmuContext indicates the type of physical address to be returned (input parameter). + * Legal return values for this field are + * TEGRA_VASPACE_A -- return the device physical address for Tegra (non-GPU) engines. This is the system physical address itself. + * returns the system physical address. This may change to use a class value in future. + * FERMI_VASPACE_A -- return the device physical address for GPU engines. This can be a system physical address or a GPU SMMU virtual address. + * 0 -- return the device physical address for GPU engines. This can be a system physical address or a GPU SMMU virtual address. + * use of zero may be deprecated in future. + * contigSegmentSize + * If the underlying surface is physically contiguous, this parameter + * returns the size in bytes of the piece of memory starting from + * the offset specified in the memOffset parameter extending to the last + * byte of the surface. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_BAD_OBJECT_HANDLE + * NVOS_STATUS_BAD_OBJECT_PARENT + * NVOS_STATUS_NOT_SUPPORTED + * + */ +#define NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR (0x410103) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS { + NV_DECLARE_ALIGNED(NvU64 memOffset, 8); + NvU32 memFormat; + NvU32 comprOffset; + NvU32 comprFormat; + NvU32 memAperture; + NvU32 gpuCacheAttr; + NvU32 gpuP2PCacheAttr; + NvU32 mmuContext; + NV_DECLARE_ALIGNED(NvU64 contigSegmentSize, 8); +} NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS; + +/* valid memAperture return values */ +#define NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_VIDMEM (0x00000000) +#define NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_SYSMEM (0x00000001) + +/* valid gpuCacheAttr return values */ +#define NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN (0x00000000) +#define NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED (0x00000001) +#define NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED (0x00000002) + +/* + * NV0041_CTRL_CMD_GET_SURFACE_ZCULL_ID + * + * This command returns the Z-cull identifier for a surface. + * The value of ~0 is returned if there is none associated. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_BAD_OBJECT_HANDLE + * NVOS_STATUS_BAD_OBJECT_PARENT + * NVOS_STATUS_NOT_SUPPORTED + * + */ +#define NV0041_CTRL_CMD_GET_SURFACE_ZCULL_ID (0x410104) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS { + NvU32 zcullId; +} NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS; + + +// return values for 'tilingFormat' +// XXX - the names for these are misleading +#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_INVALID (0x00000000) +#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_FB (0x00000001) +#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_FB_1HIGH (0x00000002) +#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_FB_4HIGH (0x00000003) +#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_UMA_1HIGH (0x00000004) +#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_UMA_4HIGH (0x00000005) + +/* + * NV0041_CTRL_SURFACE_INFO + * + * This structure represents a single 32bit surface value. Clients + * request a particular surface value by specifying a unique surface + * information index. + * + * Legal surface information index values are: + * NV0041_CTRL_SURFACE_INFO_INDEX_ATTRS + * This index is used to request the set of hw attributes associated + * with the surface. Each distinct attribute is represented by a + * single bit flag in the returned value. + * Legal flags values for this index are: + * NV0041_CTRL_SURFACE_INFO_ATTRS_COMPR + * This surface has compression resources bound to it. + * NV0041_CTRL_SURFACE_INFO_ATTRS_ZCULL + * This surface has zcull resources bound to it. + * NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE + * This index is used to request the compression coverage (if any) + * in units of 64K for the associated surface. A value of zero indicates + * there are no compression resources associated with the surface. + * Legal return values range from zero to a maximum number of 64K units + * that is GPU implementation dependent. + * NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_SIZE + * This index is used to request the physically allocated size in units + * of 4K(NV0041_CTRL_SURFACE_INFO_PHYS_SIZE_SCALE_FACTOR) for the associated + * surface. + * NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_ATTR + * This index is used to request the surface attribute field. The returned + * field value can be decoded using the NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_* + * DRF-style macros provided below. + * NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE + * This index is used to request the surface address space type. + * Returned values are described by NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE. + */ +typedef struct NV0041_CTRL_SURFACE_INFO { + NvU32 index; + NvU32 data; +} NV0041_CTRL_SURFACE_INFO; + +/* valid surface info index values */ +#define NV0041_CTRL_SURFACE_INFO_INDEX_ATTRS (0x00000001) +#define NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE (0x00000005) +#define NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_SIZE (0x00000007) +#define NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_ATTR (0x00000008) +#define NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE (0x00000009) + +/* + * This define indicates the scale factor of the reported physical size to the + * actual size in bytes. We use the scale factor to save space from the + * interface and account for large surfaces. To get the actual size, + * use `(NvU64)reported_size * NV0041_CTRL_SURFACE_INFO_PHYS_SIZE_SCALE_FACTOR`. + */ +#define NV0041_CTRL_SURFACE_INFO_PHYS_SIZE_SCALE_FACTOR (0x1000) + +/* valid surface info attr flags */ +#define NV0041_CTRL_SURFACE_INFO_ATTRS_COMPR (0x00000002) +#define NV0041_CTRL_SURFACE_INFO_ATTRS_ZCULL (0x00000004) + +/* Valid surface info page size */ +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE NVOS32_ATTR_PAGE_SIZE +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE_DEFAULT NVOS32_ATTR_PAGE_SIZE_DEFAULT +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE_4KB NVOS32_ATTR_PAGE_SIZE_4KB +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE_BIG NVOS32_ATTR_PAGE_SIZE_BIG +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE_HUGE NVOS32_ATTR_PAGE_SIZE_HUGE + +/* Valid surface info CPU coherency */ +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY NVOS32_ATTR_COHERENCY +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_UNCACHED NVOS32_ATTR_COHERENCY_UNCACHED +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_CACHED NVOS32_ATTR_COHERENCY_CACHED +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_COMBINE NVOS32_ATTR_COHERENCY_WRITE_COMBINE +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_THROUGH NVOS32_ATTR_COHERENCY_WRITE_THROUGH +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_PROTECT NVOS32_ATTR_COHERENCY_WRITE_PROTECT +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_BACK NVOS32_ATTR_COHERENCY_WRITE_BACK + +/* + * NV0041_CTRL_CMD_GET_SURFACE_INFO + * + * This command returns surface information for the associated memory object. + * Requests to retrieve surface information use a list of one or more + * NV0041_CTRL_SURFACE_INFO structures. + * + * surfaceInfoListSize + * This field specifies the number of entries on the caller's + * surfaceInfoList. + * surfaceInfoList + * This field specifies a pointer in the caller's address space + * to the buffer into which the surface information is to be returned. + * This buffer must be at least as big as surfaceInfoListSize multiplied + * by the size of the NV0041_CTRL_SURFACE_INFO structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV0041_CTRL_CMD_GET_SURFACE_INFO (0x410110) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_GET_SURFACE_INFO_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV0041_CTRL_GET_SURFACE_INFO_PARAMS { + NvU32 surfaceInfoListSize; + NV_DECLARE_ALIGNED(NvP64 surfaceInfoList, 8); +} NV0041_CTRL_GET_SURFACE_INFO_PARAMS; + +/* + * NV0041_CTRL_CMD_GET_SURFACE_COMPRESSION_COVERAGE + * + * This command returns the percentage of surface compression tag coverage. + * The value of 0 is returned if there are no tags associated. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_BAD_OBJECT_HANDLE + * NVOS_STATUS_BAD_OBJECT_PARENT + * NVOS_STATUS_NOT_SUPPORTED + * + */ +#define NV0041_CTRL_CMD_GET_SURFACE_COMPRESSION_COVERAGE (0x410112) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS { + NvHandle hSubDevice; /* if non zero subDevice handle of local GPU */ + NvU32 lineMin; + NvU32 lineMax; + NvU32 format; +} NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS; + +/* + * NV0041_CTRL_CMD_GET_FBMEM_BUS_ADDR + * + * This command returns the BAR1 physical address of a + * Memory mapping made using NvRmMapMemory() + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INVALID_DATA + * NV_ERR_INVALID_CLIENT + * NV_ERR_INVALID_OBJECT_HANDLE + * + */ +#define NV0041_CTRL_CMD_GET_FBMEM_BUS_ADDR (0x410114) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_FBMEM_BUS_ADDR_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_GET_FBMEM_BUS_ADDR_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV0041_CTRL_GET_FBMEM_BUS_ADDR_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pLinearAddress, 8); /* [in] Linear address of CPU mapping */ + NV_DECLARE_ALIGNED(NvU64 busAddress, 8); /* [out] BAR1 address */ +} NV0041_CTRL_GET_FBMEM_BUS_ADDR_PARAMS; + +/* + * NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE + * + * This command flushes a cache on the GPU which all memory accesses go + * through. The types of flushes supported by this API may not be supported by + * all hardware. Attempting an unsupported flush type will result in an error. + * + * flags + * Contains flags to control various aspects of the flush. Valid values + * are defined in NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS*. Not all + * flags are valid for all GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NVOS_STATUS_INVALID_ARGUMENT + * NVOS_STATUS_INVALID_STATE + * + * See Also: + * NV0080_CTRL_CMD_DMA_FLUSH + * Performs flush operations in broadcast for the GPU cache and other hardware + * engines. Use this call if you want to flush all GPU caches in a + * broadcast device. + * NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE + * Flushes the entire GPU cache or a set of physical addresses (if the + * hardware supports it). Use this call if you want to flush a set of + * addresses or the entire GPU cache in unicast mode. + * + */ +#define NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE (0x410116) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS { + NvU32 flags; +} NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS; + +#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK 0:0 +#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_NO (0x00000000) +#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_YES (0x00000001) +#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_INVALIDATE 1:1 +#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_NO (0x00000000) +#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_YES (0x00000001) + +/* + * NV0041_CTRL_CMD_GET_EME_PAGE_SIZE + * + * This command may be used to get the memory page size + * + * Parameters: + * pageSize [OUT] + * pageSize with associated memory descriptor + * + * Possible status values are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_NOT_SUPPORTED + */ +#define NV0041_CTRL_CMD_GET_MEM_PAGE_SIZE (0x410118) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS { + NvU32 pageSize; /* [out] - page size */ +} NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS; + +/* + * NV0041_CTRL_CMD_UPDATE_SURFACE_COMPRESSION + * + * Acquire/release compression for surface + * + * Parameters: + * bRelease [IN] + * true = release compression; false = acquire compression + */ +#define NV0041_CTRL_CMD_UPDATE_SURFACE_COMPRESSION (0x410119) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_UPDATE_SURFACE_COMPRESSION_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_UPDATE_SURFACE_COMPRESSION_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV0041_CTRL_UPDATE_SURFACE_COMPRESSION_PARAMS { + NvBool bRelease; /* [in] - acquire/release setting */ +} NV0041_CTRL_UPDATE_SURFACE_COMPRESSION_PARAMS; + +#define NV0041_CTRL_CMD_PRINT_LABELS_PARAMS_MESSAGE_ID (0x50U) + +typedef struct NV0041_CTRL_CMD_PRINT_LABELS_PARAMS { + NvU32 tag; /* [in] */ +} NV0041_CTRL_CMD_PRINT_LABELS_PARAMS; +#define NV0041_CTRL_CMD_SET_LABEL_PARAMS_MESSAGE_ID (0x51U) + +typedef struct NV0041_CTRL_CMD_SET_LABEL_PARAMS { + NvU32 tag; /* [in] */ +} NV0041_CTRL_CMD_SET_LABEL_PARAMS; +#define NV0041_CTRL_CMD_SET_LABEL (0x410151) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_CMD_SET_LABEL_PARAMS_MESSAGE_ID" */ +#define NV0041_CTRL_CMD_GET_LABEL (0x410152) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_CMD_GET_LABEL_PARAMS_MESSAGE_ID" */ +#define NV0041_CTRL_CMD_GET_LABEL_PARAMS_MESSAGE_ID (0x52U) + +typedef struct NV0041_CTRL_CMD_GET_LABEL_PARAMS { + NvU32 tag; /* [in] */ +} NV0041_CTRL_CMD_GET_LABEL_PARAMS; + +/* + * NV0041_CTRL_CMD_SET_TAG + * + * This command sets memory allocation tag used for debugging. +* Every client has it's own memory allocation tag and tag is copying when object is duping. + * This control can be used for shared allocations to change it's tag. + */ +#define NV0041_CTRL_CMD_SET_TAG (0x410120) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_CMD_SET_TAG_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_CMD_SET_TAG_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV0041_CTRL_CMD_SET_TAG_PARAMS { + NvU32 tag; /* [in] */ +} NV0041_CTRL_CMD_SET_TAG_PARAMS; + +/* + * NV0041_CTRL_CMD_GET_TAG + * + * This command returns memory allocation tag used for debugging. + */ +#define NV0041_CTRL_CMD_GET_TAG (0x410121) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_CMD_GET_TAG_PARAMS_MESSAGE_ID" */ + +#define NV0041_CTRL_CMD_GET_TAG_PARAMS_MESSAGE_ID (0x21U) + +typedef struct NV0041_CTRL_CMD_GET_TAG_PARAMS { + NvU32 tag; /* [out] */ +} NV0041_CTRL_CMD_GET_TAG_PARAMS; + +/* _ctrl0041_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073.h new file mode 100644 index 0000000..fa7d8f7 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073.h @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2015,2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073.finn +// + + + + +#include "ctrl/ctrlxxxx.h" +/* category-specific includes */ +#include "ctrl0073/ctrl0073system.h" +#include "ctrl0073/ctrl0073specific.h" +#include "ctrl0073/ctrl0073stereo.h" +#include "ctrl0073/ctrl0073event.h" +#include "ctrl0073/ctrl0073internal.h" +#include "ctrl0073/ctrl0073dfp.h" +#include "ctrl0073/ctrl0073dp.h" +#include "ctrl0073/ctrl0073svp.h" +#include "ctrl0073/ctrl0073dpu.h" +#include "ctrl0073/ctrl0073psr.h" diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h new file mode 100644 index 0000000..970ea3b --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h @@ -0,0 +1,60 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073base.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV04_DISPLAY_COMMON control commands and parameters */ + +#define NV0073_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0073, NV0073_CTRL_##cat, idx) + +/* NV04_DISPLAY_COMMON command categories (6bits) */ +#define NV0073_CTRL_RESERVED (0x00U) +#define NV0073_CTRL_SYSTEM (0x01U) +#define NV0073_CTRL_SPECIFIC (0x02U) +#define NV0073_CTRL_EVENT (0x03U) +#define NV0073_CTRL_INTERNAL (0x04U) +#define NV0073_CTRL_DFP (0x11U) +#define NV0073_CTRL_DP (0x13U) +#define NV0073_CTRL_SVP (0x14U) +#define NV0073_CTRL_DPU (0x15U) +#define NV0073_CTRL_PSR (0x16U) +#define NV0073_CTRL_STEREO (0x17U) + +/* + * NV0073_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0073_CTRL_CMD_NULL (0x730000U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrl0073base_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h new file mode 100644 index 0000000..347b478 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h @@ -0,0 +1,1269 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073dfp.finn +// + +#include "ctrl/ctrl0073/ctrl0073base.h" + +/* NV04_DISPLAY_COMMON dfp-display-specific control commands and parameters */ + +/* + * NV0073_CTRL_CMD_DFP_GET_INFO + * + * This command can be used to determine the associated display type for + * the specified displayId. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must be a dfp display + * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * flags + * This parameter returns the information specific to this dfp. Here are + * the possible fields: + * NV0073_CTRL_DFP_FLAGS_SIGNAL + * This specifies the type of signal used for this dfp. + * NV0073_CTRL_DFP_FLAGS_LANES + * This specifies whether the board supports 1, 2, or 4 lanes + * for DISPLAYPORT signals. + * NV0073_CTRL_DFP_FLAGS_LIMIT + * Some GPUs were not qualified to run internal TMDS except at 60 HZ + * refresh rates. So, if LIMIT_60HZ_RR is set, then the client must + * make sure to only allow 60 HZ refresh rate modes to the OS/User. + * NV0073_CTRL_DFP_FLAGS_SLI_SCALER + * While running in SLI, if SLI_SCALER_DISABLE is set, the GPU cannot + * scale any resolutions. So, the output timing must match the + * memory footprint. + * NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE + * This specifies whether the DFP displayId is capable of + * transmitting HDMI. + * NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE + * This specifies whether the displayId is capable of sending a + * limited color range out from the board. + * NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE + * This specifies whether the displayId is capable of auto-configuring + * the color range. + * NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE + * This specifies whether the displayId is capable of sending the + * YCBCR422 color format out from the board. + * NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE + * This specifies whether the displayId is capable of sending + * YCBCR444 color format out from the board. + * NV0073_CTRL_DFP_FLAGS_DP_LINK_BANDWIDTH + * This specifies whether the displayId is capable of doing high + * bit-rate (2.7Gbps) or low bit-rate (1.62Gbps) if the DFP is + * display port. + * NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED + * This specifies whether the DFP displayId is allowed to transmit HDMI + * based on the VBIOS settings. + * NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT + * This specifies whether the DFP displayId is actually an embedded display + * port based on VBIOS connector information AND ASSR cap. + * NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT + * This specifies whether the DFP displayId must be trained to RBR mode + * (if it is using DP protocol) whenever possible. + * NV0073_CTRL_DFP_FLAGS_LINK + * This specifies whether the board supports single or dual links + * for TMDS, LVDS, and SDI signals. + * NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED + * This specifies if PostCursor2 is disabled in the VBIOS + * NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID + * This indicates whether this SOR uses DSI-A, DSI-B or both (ganged mode). + * NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE + * This indicates whether this DFP supports Dynamic MUX + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_DFP_GET_INFO (0x731140U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_GET_INFO_PARAMS_MESSAGE_ID (0x40U) + +typedef struct NV0073_CTRL_DFP_GET_INFO_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 flags; +} NV0073_CTRL_DFP_GET_INFO_PARAMS; + +/* valid display types */ +#define NV0073_CTRL_DFP_FLAGS_SIGNAL 2:0 +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_TMDS (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_LVDS (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_SDI (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DISPLAYPORT (0x00000003U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DSI (0x00000004U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_WRBK (0x00000005U) +#define NV0073_CTRL_DFP_FLAGS_LANE 5:3 +#define NV0073_CTRL_DFP_FLAGS_LANE_NONE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_LANE_SINGLE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_LANE_DUAL (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_LANE_QUAD (0x00000003U) +#define NV0073_CTRL_DFP_FLAGS_LANE_OCT (0x00000004U) +#define NV0073_CTRL_DFP_FLAGS_LIMIT 6:6 +#define NV0073_CTRL_DFP_FLAGS_LIMIT_DISABLE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_LIMIT_60HZ_RR (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER 7:7 +#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_NORMAL (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_DISABLE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE 8:8 +#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE 9:9 +#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE 10:10 +#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE 11:11 +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE 12:12 +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED 14:14 +#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT 15:15 +#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT 16:16 +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_NONE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_PREFER_RBR (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW 19:17 +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_1_62GBPS (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_2_70GBPS (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_5_40GBPS (0x00000003U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_8_10GBPS (0x00000004U) +#define NV0073_CTRL_DFP_FLAGS_LINK 21:20 +#define NV0073_CTRL_DFP_FLAGS_LINK_NONE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_LINK_SINGLE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_LINK_DUAL (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID 22:22 +#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID 24:23 +#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_NONE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_A (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_B (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_GANGED (0x00000003U) +#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED 25:25 +#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DP_PHY_REPEATER_COUNT 29:26 +#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE 30:30 +#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_TRUE (0x00000001U) + + + +/* + * NV0073_CTRL_CMD_DFP_GET_DP2TMDS_DONGLE_INFO + * + * This command can be used to determine information about dongles attached + * to a displayport connection. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the dfp display which owns the + * panel power to adjust. The display ID must be a dfp display + * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * flags + * This parameter provide state information about the dongle attachments. + * NV0073_CTRL_DFP_GET_DP2TMDS_DONGLE_INFO_FLAGS_CAPABLE + * Specifies if the connection is capable of a dongle. This field + * returns false in all cases of signal types except for those capable + * of outputting TMDS. Even then the if a gpio is not defined, the + * the a statement of false will also be returned. + * NV0073_CTRL_DFP_GET_DP2TMDS_DONGLE_INFO_FLAGS_ATTACHED + * When attached, this value specifies that a dongle is detected and + * attached. The client should read the _TYPE field to determine + * if it is a dp2hdmi or dp2dvi dongle. + * NV0073_CTRL_DFP_GET_DP2TMDS_DONGLE_INFO_FLAGS_TYPE + * _DP2DVI: no response to i2cAddr 0x80 per DP interop guidelines. + * clients MUST avoid outputting HDMI even if capable. + * _DP2HDMI: dongle responds to i2cAddr 0x80 per DP interop guidelines. + * client is allowed to output HDMI when possible. + * _LFH_DVI: DMS59-DVI breakout dongle is in use. + * _LFH_VGA: DMS59-VGA breakout dongle is in use. + * NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE + * _1: Max TMDS Clock rate is 165 MHz for both DVI and HDMI. + * _2: Max TMDS Clock rate will be specified in the dongle + * address space at device address 0x80. + * DVI is up to 165 MHz + * HDMI is up to 300 MHz + * There are type 2 devices that support beyond 600 MHz + * though not defined in the spec. + * maxTmdsClkRateHz + * This defines the max TMDS clock rate for dual mode adaptor in Hz. + */ +#define NV0073_CTRL_CMD_DFP_GET_DISPLAYPORT_DONGLE_INFO (0x731142U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS_MESSAGE_ID (0x42U) + +typedef struct NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 flags; + NvU32 maxTmdsClkRateHz; +} NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS; + +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_CAPABLE 0:0 +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_ATTACHED 1:1 +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_ATTACHED_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_ATTACHED_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE 7:4 +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE_DP2DVI (0x00000000U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE_DP2HDMI (0x00000001U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE_LFH_DVI (0x00000002U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE_LFH_VGA (0x00000003U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE 8:8 +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE_1 (0x00000000U) +#define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE_2 (0x00000001U) + + + +/* + * NV0073_CTRL_CMD_DFP_SET_ELD_AUDIO_CAPS + * + * This command is used to inform hardware the receiver's audio capabilities + * using the new EDID Like Data (ELD) memory structure. The ELD memory + * structure is read by the audio driver by issuing the ELD Data command verb. + * This mechanism is used for passing sink device' audio EDID information + * from graphics software to audio software. ELD contents will contain a + * subset of the sink device's EDID information. + * The client should inform hardware at initial boot, a modeset, and whenever + * a hotplug event occurs. + * + * displayId + * This parameter indicates the digital display device's + * mask. This comes as input to this command. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * numELDSize + * This parameter specifies how many bytes of data RM should write to the + * ELD buffer. Section 7.3.3.36 of the ECN specifies that the ELD buffer + * size of zero based. HDAudio driver will then use this information to + * determine how many bytes of the ELD buffer the HDAudio should read. + * The maximum size of the buffer is 96 bytes. + * bufferELD + * This buffer contains data as defined in the ECR HDMI ELD memory structure. + * Refer to the ELD Memory Structure Specification for more details. + * The format should be: + * - Header block is fixed at 4 bytes + * The header block contains the ELD version and baseline ELD len as + * well as some reserved fields. + * - Baseline block for audio descriptors is 76 bytes + * (15 SAD; each SAD=3 bytes requiring 45 bytes with 31 bytes to spare) + * As well as some other bits used to denote the CEA version, + * the speaker allocation data, monitor name, connector type, and + * hdcp capabilities. + * - Vendor specific block of 16 bytes + * maxFreqSupported + * Supply the maximum frequency supported for the overall audio caps. + * This value should match CEA861-X defines for sample freq. + * ctrl: + * NV0073_CTRL_DFP_SET_ELD_AUDIO_CAPS_CTRL_PD: + * Specifies the presence detect of the receiver. On a hotplug + * or modeset client should set this bit to TRUE. + * NV0073_CTRL_DFP_SET_ELD_AUDIO_CAPS_CTRL_ELDV: + * Specifies whether the ELD buffer contents are valid. + * An intrinsic unsolicited response (UR) is generated whenever + * the ELDV bit changes in value and the PD=1. When _PD=1(hotplug), + * RM will set the ELDV bit after ELD buffer contents are written. + * If _ELDV bit is set to false such as during a unplug, then the + * contents of the ELD buffer will be cleared. + * deviceEntry: + * The deviceEntry number from which the SF should accept packets. + * _NONE if disabling audio. + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_DFP_SET_ELD_AUDIO_CAPS (0x731144U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER 96U + +#define NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS_MESSAGE_ID (0x44U) + +typedef struct NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 numELDSize; + NvU8 bufferELD[NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER]; + NvU32 maxFreqSupported; + NvU32 ctrl; + NvU32 deviceEntry; +} NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS; + +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0320KHZ (0x00000001U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0441KHZ (0x00000002U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0480KHZ (0x00000003U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0882KHZ (0x00000004U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0960KHZ (0x00000005U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_1764KHZ (0x00000006U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_1920KHZ (0x00000007U) + +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD 0:0 +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV 1:1 +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV_TRUE (0x00000001U) + +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_0 (0x00000000U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_1 (0x00000001U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_2 (0x00000002U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_3 (0x00000003U) +#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_NONE (0x00000007U) + + + +/* + * NV0073_CTRL_CMD_DFP_GET_SPREAD_SPECTRUM_STATUS + * + * This command is used to get spread spectrum status for a display device. + * + * displayId + * Display ID for which the spread spectrum status is needed. + * checkRMSsState + * Default is to check in Vbios. This flag lets this control call to check in register. + * status + * Return status value. + */ + +#define NV0073_CTRL_CMD_DFP_GET_SPREAD_SPECTRUM (0x73114cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS_MESSAGE_ID (0x4CU) + +typedef struct NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS { + NvU32 displayId; + NvBool enabled; +} NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS; + +/* + * NV0073_CTRL_CMD_DFP_UPDATE_DYNAMIC_DFP_CACHE + * + * Update the Dynamic DFP with Bcaps read from remote display. + * Also updates hdcpFlags, gpu hdcp capable flags in DFP. + * If bResetDfp is true, all the flags are reset before making changes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_DFP_UPDATE_DYNAMIC_DFP_CACHE (0x73114eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS_MESSAGE_ID (0x4EU) + +typedef struct NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS { + NvU32 subDeviceInstance; + NvU32 headIndex; + NvU8 bcaps; + NvU8 bksv[5]; + NvU32 hdcpFlags; + NvBool bHdcpCapable; + NvBool bResetDfp; + NvU8 updateMask; +} NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS; + +#define NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_MASK_BCAPS 0x01U +#define NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_MASK_BKSV 0x02U +#define NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_MASK_FLAGS 0x03U + +/* + * NV0073_CTRL_CMD_DFP_SET_AUDIO_ENABLE + * + * This command sets the audio enable state of the DFP. When disabled, + * no audio stream packets or audio timestamp packets will be sent. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the dfp + * audio should be enabled or disabled. The display ID must be a dfp display. + * If the displayId is not a dfp, this call will return + * NV_ERR_INVALID_ARGUMENT. + * enable + * This parameter specifies whether to enable (NV_TRUE) or disable (NV_FALSE) + * audio to the display. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * + */ +#define NV0073_CTRL_CMD_DFP_SET_AUDIO_ENABLE (0x731150U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS_MESSAGE_ID (0x50U) + +typedef struct NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool enable; +} NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS; + + + +/* + * NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG + * + * This enum defines default/primary/secondary sor sublinks to be configured. + * These access modes are: + * + * NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_NONE + * Default link config + * NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_PRIMARY_SOR_LINK + * Primary sor sublink to be configured + * NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_SECONDARY_SOR_LINK + * Secondary sor sublink to be configured + */ +typedef enum NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG { + NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_NONE = 0, + NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_PRIMARY_SOR_LINK = 1, + NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_SECONDARY_SOR_LINK = 2, +} NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG; + +/* + * NV0073_CTRL_DFP_ASSIGN_SOR_INFO + * + * This structure describes info about assigned SOR + * + * displayMask + * The displayMask for the SOR corresponding to its HW routings + * sorType + * This parameter specifies the SOR type + * Here are the current defined fields: + * NV0073_CTRL_DFP_SOR_TYPE_NONE + * Unallocated SOR + * NV0073_CTRL_DFP_SOR_TYPE_2H1OR_PRIMARY + * Primary SOR for 2H1OR stream + * NV0073_CTRL_DFP_SOR_TYPE_2H1OR_SECONDARY + * Secondary SOR for 2H1OR stream + * NV0073_CTRL_DFP_SOR_TYPE_SINGLE + * Default Single SOR + * Note - sorType should only be referred to identify 2H1OR Primary and Secondary SOR + * + */ + +typedef struct NV0073_CTRL_DFP_ASSIGN_SOR_INFO { + NvU32 displayMask; + NvU32 sorType; +} NV0073_CTRL_DFP_ASSIGN_SOR_INFO; + +#define NV0073_CTRL_DFP_SOR_TYPE_NONE (0x00000000U) +#define NV0073_CTRL_DFP_SOR_TYPE_SINGLE (0x00000001U) +#define NV0073_CTRL_DFP_SOR_TYPE_2H1OR_PRIMARY (0x00000002U) +#define NV0073_CTRL_DFP_SOR_TYPE_2H1OR_SECONDARY (0x00000003U) + +/* + * NV0073_CTRL_CMD_DFP_ASSIGN_SOR + * + * This command is used by the clients to assign SOR to DFP for CROSS-BAR + * when the default SOR-DFP routing that comes from vbios is not considered. + * SOR shall be assigned to a DFP at the runtime. This call should be called + * before a modeset is done on any dfp display and also before LinkTraining for DP displays. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * DisplayId of the primary display for which SOR is to be assigned. However, if + * displayId is 0 then RM shall return the XBAR config it has stored in it's structures. + * sorExcludeMask + * sorMask of the SORs which should not be used for assignment. If this is 0, + * then SW is free to allocate any available SOR. + * slaveDisplayId + * displayId of the slave device in case of dualSST mode. This ctrl call will + * allocate SORs to both slave and the master if slaveDisplayId is set. + * forceSublinkConfig + * forces RM to configure primary or secondary sor sublink on the given diaplayId. + * If not set, then RM will do the default configurations. + * bIs2Head1Or + * Specifies that SOR allocation is required for 2 head 1 OR. This will allocate + * 2 SOR for same displayId - one Master and one Slave. Slave SOR would be disconnected + * from any padlink and get feedback clock from Master SOR's padlink. + * sorAssignList[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS] + * returns the displayMask for all SORs corresponding to their HW routings. + * sorAssignListWithTag[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS] + * returns the displayMask for all SORs corresponding to their HW routings along with + * SOR type to identify 2H1OR Primary and Secondary SORs. SOR type would be identified by + * NV0073_CTRL_DFP_SOR_TYPE. sorAssignList would look as below - + * sorAssignListWithTag[] = { DisplayMask, SOR Type + * {0x100, SECONDARY_SOR} + * {0x200, SINGLE_SOR} + * {0x100, PRIMARY_SOR} + * {0, NONE}} + * } + * Here, for display id = 0x100, SOR2 is Primary and SOR0 is Secondary. + * Note - sorAssignList parameter would be removed after Bug 200749158 is resolved + * reservedSorMask + * returns the sorMask reserved for the internal panels. + * flags + * Other detail settings. + * _AUDIO_OPTIMAL: Client requests trying to get audio SOR if possible. + * If there's no audio capable SOR and OD is HDMI/DP, + * RM will fail the control call. + * _AUDIO_DEFAULT: RM does not check audio-capability of SOR. + * + * _ACTIVE_SOR_NOT_AUDIO_CAPABLE_YES : RM returns Active SOR which is not Audio capable. + * _ACTIVE_SOR_NOT_AUDIO_CAPABLE_NO : RM is not returning 'Active non-audio capable SOR'. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + + +#define NV0073_CTRL_CMD_DFP_ASSIGN_SOR (0x731152U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS 4U + +#define NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS_MESSAGE_ID (0x52U) + +typedef struct NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU8 sorExcludeMask; + NvU32 slaveDisplayId; + NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG forceSublinkConfig; + NvBool bIs2Head1Or; + NvU32 sorAssignList[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS]; + NV0073_CTRL_DFP_ASSIGN_SOR_INFO sorAssignListWithTag[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS]; + NvU8 reservedSorMask; + NvU32 flags; +} NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS; + +#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO 0:0 +#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO_OPTIMAL (0x00000001U) +#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO_DEFAULT (0x00000000U) +#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE 1:1 +#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE_NO (0x00000000U) +#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE_YES (0x00000001U) + +/* +* NV0073_CTRL_CMD_DFP_GET_PADLINK_MASK +* +* This command will only be used by chipTB tests to get the padlinks corresponding +* to the given displayId. RM gets this information from vbios. This control call is +* only for verif purpose. +* +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. This parameter must specify a value between zero and the +* total number of subdevices within the parent device. This parameter +* should be set to zero for default behavior. +* displayId +* DisplayId of the display for which the client needs analog link Mask +* padlinkMask +* analogLinkMask for the given displayId. This value returned is 0xffffffff if +* the given displayId is invalid else RM returns the corresponding padlinkMask. +* NV_OK +* NV_ERR_INVALID_ARGUMENT +* NV_ERR_NOT_SUPPORTED +*/ + + +#define NV0073_CTRL_CMD_DFP_GET_PADLINK_MASK (0x731153U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS_MESSAGE_ID (0x53U) + +typedef struct NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 padlinkMask; +} NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS; + +/* + * NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE + * This enum defines the functions that are supported for which a + * corresponding GPIO pin number could be retrieved + * Values copied from objgpio.h GPIO_FUNC_TYPE_LCD_*. Please keep the + * values in sync between the 2 files + */ + +typedef enum NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE { + // GPIO types of LCD GPIO functions common to all internal panels + NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_BACKLIGHT = 268435456, + NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_POWER = 285212672, + NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_POWER_OK = 301989888, + NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_SELF_TEST = 318767104, + NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_LAMP_STATUS = 335544320, + NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_BRIGHTNESS = 352321536, +} NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE; + +/* + * NV0073_CTRL_CMD_DFP_GET_LCD_GPIO_PIN_NUM + * + * This command can be used to get the GPIO pin number that corresponds to one + * of the LCD functions + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the dfp display. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NVOS_STATUS_ERROR_INVALID_ARGUMENT. + * funcType + * The LDC function for which the GPIO pin number is needed + * lcdGpioPinNum + * The GPIO pin number that corresponds to the LCD function. + * +*/ +#define NV0073_CTRL_CMD_DFP_GET_LCD_GPIO_PIN_NUM (0x731154U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS_MESSAGE_ID (0x54U) + +typedef struct NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE funcType; + NvU32 lcdGpioPinNum; +} NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS; + + + +/* + * NV0073_CTRL_CMD_DFP_CONFIG_TWO_HEAD_ONE_OR + * + * This command is used for configuration of 2 head 1 OR. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * Display Id of the panel for which Two Head One OR is going to be used + * bEnable + * Enable/Disable 2 Head 1 OR + * masterSorIdx + * Master SOR Index which will send pixels to panel + * slaveSorIdx + * Slave SOR Index which will take feedback clock from Master SOR's + * padlink + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + * NVOS_STATUS_ERROR_INVALID_ARGUMENT + * NVOS_STATUS_ERROR_NOT_SUPPORTED + */ + + +#define NV0073_CTRL_CMD_DFP_CONFIG_TWO_HEAD_ONE_OR (0x731156U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS_MESSAGE_ID (0x56U) + +typedef struct NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bEnable; + NvU32 masterSorIdx; + NvU32 slaveSorIdx; +} NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS; + +/* + * NV0073_CTRL_CMD_DFP_DSC_CRC_CONTROL + * + * This command is used to enable/disable CRC on the GPU or query the registers + * related to it + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * headIndex + * index of the head + * cmd + * specifying if setup or querying is done + * bEnable + * enable or disable CRC on the GPU + * gpuCrc0 + * 0-indexed CRC register of the GPU + * gpuCrc1 + * 1-indexed CRC register of the GPU + * gpuCrc0 + * 2-indexed CRC register of the GPU + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + * NVOS_STATUS_ERROR_NOT_SUPPORTED + */ + + +#define NV0073_CTRL_CMD_DFP_DSC_CRC_CONTROL (0x731157U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS_MESSAGE_ID (0x57U) + +typedef struct NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS { + NvU32 subDeviceInstance; + NvU32 headIndex; + NvU32 cmd; + NvBool bEnable; + NvU16 gpuCrc0; + NvU16 gpuCrc1; + NvU16 gpuCrc2; +} NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS; + +#define NV0073_CTRL_DP_CRC_CONTROL_CMD 0:0 +#define NV0073_CTRL_DP_CRC_CONTROL_CMD_SETUP (0x00000000U) +#define NV0073_CTRL_DP_CRC_CONTROL_CMD_QUERY (0x00000001U) + +/* + * NV0073_CTRL_CMD_DFP_INIT_MUX_DATA + * + * This control call is used to configure the display MUX related data + * for the given display device. Clients to RM are expected to call this + * control call to initialize the data related to MUX before any MUX related + * operations such mux switch or PSR entry/ exit are performed. + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId (in) + * ID of the display device for which the mux state has to be initialized + * manfId (in) + * Specifies the manufacturer ID of panel obtained from the EDID. This + * parameter is expected to be non-zero only in case of internal panel. + * productId (in) + * Specifies the product ID of panel obtained from the EDID. This + * parameter is expected to be non-zero only in case of internal panel. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_DFP_INIT_MUX_DATA (0x731158U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS_MESSAGE_ID (0x58U) + +typedef struct NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU16 manfId; + NvU16 productId; +} NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS; + + + +/* + * NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX + * + * This command is used to switch the dynamic display mux between + * integrated GPU and discrete GPU. + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId (in) + * ID of the display device for which the display MUX has to be switched + * flags (in) + * Flags indicating the action to be performed. Here are the possible + * valid values- + * NV0073_CTRL_DFP_DISP_MUX_SWITCH_IGPU_TO_DGPU + * When set mux is switched from integrated to discrete GPU. + * NV0073_CTRL_DFP_DISP_MUX_SWITCH_DGPU_TO_IGPU + * When set mux is switched from discrete to integrated GPU. + * NV0073_CTRL_DFP_DISP_MUX_SWITCH_SKIP_SIDEBAND_ACCESS + * Set to true for PSR panels as we skip sideband access. + * auxSettleDelay (in) + * Time, in milliseconds, necessary for AUX channel to settle and become + * accessible after a mux switch. Set to zero to use the default delay. + * muxSwitchLatencyMs (out) + * mux switch latency stats in milli-seconds + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX (0x731160U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS_MESSAGE_ID (0x60U) + +typedef struct NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 flags; + NvU32 auxSettleDelay; + NvU32 muxSwitchLatencyMs; +} NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS; + +/* valid flags*/ +#define NV0073_CTRL_DFP_DISP_MUX_SWITCH 0:0 +#define NV0073_CTRL_DFP_DISP_MUX_SWITCH_IGPU_TO_DGPU 0x00000000 +#define NV0073_CTRL_DFP_DISP_MUX_SWITCH_DGPU_TO_IGPU 0x00000001 +#define NV0073_CTRL_DFP_DISP_MUX_SWITCH_SKIP_SIDEBAND_ACCESS 1:1 +#define NV0073_CTRL_DFP_DISP_MUX_SWITCH_SKIP_SIDEBAND_ACCESS_YES 0x00000001 +#define NV0073_CTRL_DFP_DISP_MUX_SWITCH_SKIP_SIDEBAND_ACCESS_NO 0x00000000 + +/* + * NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS + * + * This command is used to perform all the operations that need to be + * performed before a mux switch is started. + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId (in) + * ID of the display device for which the pre mux switch operations have + * to be performed. + * flags (in) + * Flags indicating the action to be performed. Here are the possible + * valid values - + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_IGPU_TO_DGPU + * Indicates a switch from i to d is initiated + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_DGPU_TO_IGPU + * Indicates a switch from d to i is initiated + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP_NO + * When set RM will execute the PSR enter sequence. By default RM will + * not skip SR enter sequence + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP_YES + * When set RM will skip the PSR enter sequence + * iGpuBrightness (in) + * iGPU brightness value (scale 0~100) before switching mux from I2D. + * This is used to match brightness after switching mux to dGPU + * preOpsLatencyMs (out) + * premux switch operations latency stats in milli-seconds. This includes - + * - disabling SOR sequencer and enable BL GPIO control + * - toggling LCD VDD, BL EN and PWM MUX GPIOs + * - PSR entry, if not skipped + * psrEntryLatencyMs (out) + * psr entry latency stats in milli-seconds + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS (0x731161U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS_MESSAGE_ID (0x61U) + +typedef struct NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 flags; + NvU32 iGpuBrightness; + NvU32 preOpsLatencyMs; + NvU32 psrEntryLatencyMs; +} NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS; + +/* valid flags*/ +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE 0:0 +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_IGPU_TO_DGPU 0x00000000U +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_DGPU_TO_IGPU 0x00000001U +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP 1:1 +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP_NO 0x00000000U +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP_YES 0x00000001U +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING 2:2 +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_KNOWN 0x00000000 +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_UNKNOWN 0x00000001 + +#define NV0073_CTRL_DISP_MUX_BACKLIGHT_BRIGHTNESS_MIN 0U +#define NV0073_CTRL_DISP_MUX_BACKLIGHT_BRIGHTNESS_MAX 100U + +/* + * NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS + * + * This command is used to perform all the operations that need to be + * performed after a successful mux switch is completed. + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId (in) + * ID of the display device for which the post mux switch operations have + * to be performed. + * flags (in) + * Flags indicating the action to be performed. Here are the possible + * valid values - + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_IGPU_TO_DGPU + * Indicates a switch from i to d is initiated + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_DGPU_TO_IGPU + * Indicates a switch from d to i is initiated + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP_NO + * When set RM will execute the PSR exit sequence. By default RM will + * not skip SR exit sequence + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP_YES + * When set RM will skip the PSR exit sequence + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_KNOWN + * Indicates mux switches where we know when igpu powers up + * NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_UNKNOWN + * Indicates mux switches where we don't know when igpu powers up + * postOpsLatencyMs (out) + * postmux switch operations latency stats in milli-seconds. This includes - + * - restoring SOR sequencer and BL GPIO control + * - toggling LCD VDD, BL EN and PWM MUX GPIOs + * - PSR exit, if not skipped + * psrExitLatencyMs (out) + * psr exit latency stats in milli-seconds + * psrExitTransitionToInactiveLatencyMs (out) + * psr exit latency stats in milli-seconds, from state 2 (SR active) to state 4 (transition to inactive) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_TIMEOUT in case of SR exit failure + */ + +#define NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS (0x731162U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS_MESSAGE_ID (0x62U) + +typedef struct NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 flags; + NvU32 postOpsLatencyMs; + NvU32 psrExitLatencyMs; + NvU32 psrExitTransitionToInactiveLatencyMs; +} NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS; + +/* valid flags*/ +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE 0:0 +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP 1:1 +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP_NO 0x00000000U +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP_YES 0x00000001U + +/* + * NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS + * + * This command is used to query the display mux status for the given + * display device + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId (in) + * ID of the display device for which the post mux switch operations have + * to be performed. + * muxStatus (out) + * status indicating the current state of the mux. + * valid values - + * NV0073_CTRL_DFP_DISP_MUX_STATE_INTEGRATED_GPU + * Indicates that the MUX is currently switched to integrated GPU. + * NV0073_CTRL_DFP_DISP_MUX_STATE_DISCRETE_GPU + * Indicates that the MUX is currently switched to discrete GPU. + * NV0073_CTRL_DFP_DISP_MUX_MODE_DISCRETE_ONLY + * Indicates that the MUX mode is set to discrete mode, where all displays + * are driven by discrete GPU. + * NV0073_CTRL_DFP_DISP_MUX_MODE_INTEGRATED_ONLY + * Indicates that the MUX mode is set to integrated mode, where all + * displays are driven by Integrated GPU. + * NV0073_CTRL_DFP_DISP_MUX_MODE_HYBRID + * Indicates that the MUX mode is set to hybrid, where internal panel is + * driven by integrated GPU, while external displays might be driven by + * discrete GPU. + * NV0073_CTRL_DFP_DISP_MUX_MODE_DYNAMIC + * Indicates that the MUX mode is dynamic. It is only in this mode, the + * display MUX can be toggled between discrete and hybrid dynamically. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS (0x731163U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS_MESSAGE_ID (0x63U) + +typedef struct NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 muxStatus; +} NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS; + +/* valid flags */ +#define NV0073_CTRL_DFP_DISP_MUX_STATE 1:0 +#define NV0073_CTRL_DFP_DISP_MUX_STATE_INVALID 0x00000000U +#define NV0073_CTRL_DFP_DISP_MUX_STATE_INTEGRATED_GPU 0x00000001U +#define NV0073_CTRL_DFP_DISP_MUX_STATE_DISCRETE_GPU 0x00000002U +#define NV0073_CTRL_DFP_DISP_MUX_MODE 4:2 +#define NV0073_CTRL_DFP_DISP_MUX_MODE_INVALID 0x00000000U +#define NV0073_CTRL_DFP_DISP_MUX_MODE_INTEGRATED_ONLY 0x00000001U +#define NV0073_CTRL_DFP_DISP_MUX_MODE_DISCRETE_ONLY 0x00000002U +#define NV0073_CTRL_DFP_DISP_MUX_MODE_HYBRID 0x00000003U +#define NV0073_CTRL_DFP_DISP_MUX_MODE_DYNAMIC 0x00000004U + + + +/* +* NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING +* +* This command can be used to get DSI mode timing parameters. +* +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. This parameter must specify a value between zero and the +* total number of subdevices within the parent device. This parameter +* should be set to zero for default behavior. +* displayId +* This parameter specifies the ID of the display on which the DSI +* info will be set. The display ID must be a DSI-capable display. +* hActive +* This parameter specifies the horizontal length of the active pixel +* data in the raster. +* vActive +* This parameter specifies the vertical lines of the active pixel +* data in the raster. +* hFrontPorch +* This parameter specifies the number of horizontal front porch +* blanking pixels in the raster. +* vFrontPorch +* This parameter specifies the numer of lines of the vertical front +* porch in the raster. +* hBackPorch +* This parameter specifies the number of horizontal back porch +* blanking pixels in the raster. +* vBackPorch +* This parameter specifies the numer of lines of the vertical back +* porch in the raster. +* hSyncWidth +* This parameter specifies the number of horizontal sync pixels in +* the raster. +* vSyncWidth +* This parameter specifies the numer of lines of the vertical sync +* in the raster. +* bpp +* This parameter specifies the depth (Bits per Pixel) of the output +* display stream. +* refresh +* This parameter specifies the refresh rate of the panel (in Hz). +* pclkHz +* This parameter specifies the pixel clock rate in Hz. +* numLanes +* Number of DSI data lanes. +* dscEnable +* Flag to indicate if DSC an be enabled, which in turn indicates if +* panel supports DSC. +* dscBpp +* DSC Bits per pixel +* dscNumSlices +* Number of slices for DSC. +* dscDuaDsc +* Flag to indicate if panel supports DSC streams from two DSI +* controllers. +* dscSliceHeight +* Height of DSC slices. +* dscBlockPrediction +* Flag to indicate if DSC Block Prediction needs to be enabled. +* dscDecoderVersionMajor +* Major version number of DSC decoder on Panel. +* dscDecoderVersionMinor +* Minor version number of DSC decoder on Panel. +* dscUseCustomPPS +* Flag to indicate if Panel uses custom PPS values which deviate from standard values. +* dscCustomPPSData +* 32 bytes of custom PPS data required by Panel. +* dscEncoderCaps +* Capabilities of DSC encoder in SoC. +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_ARGUMENT +* NV_ERR_NOT_SUPPORTED +*/ + +#define NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING (0x731166U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DFP_DSI_CUSTOM_PPS_DATA_COUNT 32U + +#define NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS_MESSAGE_ID (0x66U) + +typedef struct NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 hActive; + NvU32 vActive; + NvU32 hFrontPorch; + NvU32 vFrontPorch; + NvU32 hBackPorch; + NvU32 vBackPorch; + NvU32 hSyncWidth; + NvU32 vSyncWidth; + NvU32 bpp; + NvU32 refresh; + NvU32 pclkHz; + NvU32 numLanes; + NvU32 dscEnable; + NvU32 dscBpp; + NvU32 dscNumSlices; + NvU32 dscDualDsc; + NvU32 dscSliceHeight; + NvU32 dscBlockPrediction; + NvU32 dscDecoderVersionMajor; + NvU32 dscDecoderVersionMinor; + NvBool dscUseCustomPPS; + NvU32 dscCustomPPSData[NV0073_CTRL_CMD_DFP_DSI_CUSTOM_PPS_DATA_COUNT]; + + struct { + NvBool bDscSupported; + NvU32 encoderColorFormatMask; + NvU32 lineBufferSizeKB; + NvU32 rateBufferSizeKB; + NvU32 bitsPerPixelPrecision; + NvU32 maxNumHztSlices; + NvU32 lineBufferBitDepth; + } dscEncoderCaps; +} NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS; + + + +/* + * NV0073_CTRL_CMD_DFP_GET_FIXED_MODE_TIMING + * + * This control call is used to retrieve the display mode timing info that's + * specified for a given DFP from an offline configuration blob (e.g., Device Tree). + * This display timing info is intended to replace the timings exposed in a + * sink's EDID. + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId (in) + * ID of the display device for which the timings should be retrieved. + * stream (in) + * For MST connectors with static topologies (e.g., DP serializers), + * this parameter further identifies the video stream for which the + * timings should be retrieved. + * valid (out) + * Indicates whether a valid display timing was found for this DFP. + * hActive (out) + * Horizontal active width in pixels + * hFrontPorch (out) + * Horizontal front porch + * hSyncWidth (out) + * Horizontal sync width + * hBackPorch (out) + * Horizontal back porch + * vActive (out) + * Vertical active height in lines + * vFrontPorch (out) + * Vertical front porch + * vSyncWidth (out) + * Vertical sync width + * vBackPorch (out) + * Vertical back porch + * pclkKHz (out) + * Pixel clock frequency in KHz + * rrx1k (out) + * Refresh rate in units of 0.001Hz + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_DFP_GET_FIXED_MODE_TIMING (0x731172) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8 | NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS_MESSAGE_ID)" */ + +#define NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS_MESSAGE_ID (0x72U) + +typedef struct NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU8 stream; + + NvBool valid; + + NvU16 hActive; + NvU16 hFrontPorch; + NvU16 hSyncWidth; + NvU16 hBackPorch; + + NvU16 vActive; + NvU16 vFrontPorch; + NvU16 vSyncWidth; + NvU16 vBackPorch; + + NvU32 pclkKHz; + NvU32 rrx1k; +} NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS; + +/* _ctrl0073dfp_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h new file mode 100644 index 0000000..e593227 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h @@ -0,0 +1,2767 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073dp.finn +// + +#include "ctrl/ctrl0073/ctrl0073base.h" + +/* NV04_DISPLAY_COMMON dfp-display-specific control commands and parameters */ + +/* + * NV0073_CTRL_CMD_DP_AUXCH_CTRL + * + * This command can be used to perform an aux channel transaction to the + * displayPort receiver. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must a dfp display. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * bAddrOnly + * If set to NV_TRUE, this parameter prompts an address-only + * i2c-over-AUX transaction to be issued, if supported. Else the + * call fails with NVOS_STATUS_ERR_NOT_SUPPORTED. The size parameter is + * expected to be 0 for address-only transactions. + * cmd + * This parameter is an input to this command. The cmd parameter follows + * Section 2.4 AUX channel syntax in the DisplayPort spec. + * Here are the current defined fields: + * NV0073_CTRL_DP_AUXCH_CMD_TYPE + * This specifies the request command transaction + * NV0073_CTRL_DP_AUXCH_CMD_TYPE_I2C + * Set this value to indicate a I2C transaction. + * NV0073_CTRL_DP_AUXCH_CMD_TYPE_AUX + * Set this value to indicate a DisplayPort transaction. + * NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT + * This field is dependent on NV0073_CTRL_DP_AUXCH_CMD_TYPE. + * It is only valid if NV0073_CTRL_DP_AUXCH_CMD_TYPE_I2C + * is specified above and indicates a middle of transaction. + * In the case of AUX, this field should be set to zero. The valid + * values are: + * NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT_FALSE + * The I2C transaction is not in the middle of a transaction. + * NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT_TRUE + * The I2C transaction is in the middle of a transaction. + * NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE + * The request type specifies if we are doing a read/write or write + * status request: + * NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_READ + * An I2C or AUX channel read is requested. + * NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_WRITE + * An I2C or AUX channel write is requested. + * NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_WRITE_STATUS + * An I2C write status request desired. This value should + * not be set in the case of an AUX CH request and only applies + * to I2C write transaction command. + * addr + * This parameter is an input to this command. The addr parameter follows + * Section 2.4 in DisplayPort spec and the client should refer to the valid + * address in DisplayPort spec. Only the first 20 bits are valid. + * data[] + * In the case of a read transaction, this parameter returns the data from + * transaction request. In the case of a write transaction, the client + * should write to this buffer for the data to send. The max # of bytes + * allowed is NV0073_CTRL_DP_AUXCH_MAX_DATA_SIZE. + * size + * Specifies how many data bytes to read/write depending on the transaction type. + * The input size value should be indexed from 0. That means if you want to read + * 1 byte -> size = 0, 2 bytes -> size = 1, 3 bytes -> size = 2, up to 16 bytes + * where size = 15. On return, this parameter returns total number of data bytes + * successfully read/written from/to the transaction (indexed from 1). That is, + * if you successfully requested 1 byte, you would send down size = 0. On return, + * you should expect size = 1 if all 1 byte were successfully read. (Note that + * it is valid for a display to reply with fewer than the requested number of + * bytes; in that case, it is up to the client to make a new request for the + * remaining bytes.) + * replyType + * This parameter is an output to this command. It returns the auxChannel + * status after the end of the aux Ch transaction. The valid values are + * based on the DisplayPort spec: + * NV0073_CTRL_DP_AUXCH_REPLYTYPE_ACK + * In the case of a write, + * AUX: write transaction completed and all data bytes written. + * I2C: return size bytes has been written to i2c slave. + * In the case of a read, return of ACK indicates ready to reply + * another read request. + * NV0073_CTRL_DP_AUXCH_REPLYTYPE_NACK + * In the case of a write, first return size bytes have been written. + * In the case of a read, implies that does not have requested data + * for the read request transaction. + * NV0073_CTRL_DP_AUXCH_REPLYTYPE_DEFER + * Not ready for the write/read request and client should retry later. + * NV0073_CTRL_DP_DISPLAYPORT_AUXCH_REPLYTYPE_I2CNACK + * Applies to I2C transactions only. For I2C write transaction: + * has written the first return size bytes to I2C slave before getting + * NACK. For a read I2C transaction, the I2C slave has NACKED the I2C + * address. + * NV0073_CTRL_DP_AUXCH_REPLYTYPE_I2CDEFER + * Applicable to I2C transactions. For I2C write and read + * transactions, I2C slave has yet to ACK or NACK the I2C transaction. + * NV0073_CTRL_DP_AUXCH_REPLYTYPE_TIMEOUT + * The receiver did not respond within the timeout period defined in + * the DisplayPort 1.1a specification. + * retryTimeMs + * This parameter is an output to this command. In case of + * NVOS_STATUS_ERROR_RETRY return status, this parameter returns the time + * duration in milli-seconds after which client should retry this command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_ERROR_RETRY + */ +#define NV0073_CTRL_CMD_DP_AUXCH_CTRL (0x731341U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_AUXCH_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_AUXCH_MAX_DATA_SIZE 16U +#define NV0073_CTRL_DP_AUXCH_CTRL_PARAMS_MESSAGE_ID (0x41U) + +typedef struct NV0073_CTRL_DP_AUXCH_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bAddrOnly; + NvU32 cmd; + NvU32 addr; + NvU8 data[NV0073_CTRL_DP_AUXCH_MAX_DATA_SIZE]; + NvU32 size; + NvU32 replyType; + NvU32 retryTimeMs; +} NV0073_CTRL_DP_AUXCH_CTRL_PARAMS; + +#define NV0073_CTRL_DP_AUXCH_CMD_TYPE 3:3 +#define NV0073_CTRL_DP_AUXCH_CMD_TYPE_I2C (0x00000000U) +#define NV0073_CTRL_DP_AUXCH_CMD_TYPE_AUX (0x00000001U) +#define NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT 2:2 +#define NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT_FALSE (0x00000000U) +#define NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT_TRUE (0x00000001U) +#define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE 1:0 +#define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_WRITE (0x00000000U) +#define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_READ (0x00000001U) +#define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_WRITE_STATUS (0x00000002U) + +#define NV0073_CTRL_DP_AUXCH_ADDR 20:0 + +#define NV0073_CTRL_DP_AUXCH_REPLYTYPE 3:0 +#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_ACK (0x00000000U) +#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_NACK (0x00000001U) +#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_DEFER (0x00000002U) +#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_TIMEOUT (0x00000003U) +#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_I2CNACK (0x00000004U) +#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_I2CDEFER (0x00000008U) + +//This is not the register field, this is software failure case when we +//have invalid argument +#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_INVALID_ARGUMENT (0xffffffffU) + +/* + * NV0073_CTRL_CMD_DP_AUXCH_SET_SEMA + * + * This command can be used to set the semaphore in order to gain control of + * the aux channel. This control is only used in HW verification. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must a dfp display + * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * owner + * This parameter is an input to this command. + * Here are the current defined fields: + * NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_RM + * Write the aux channel semaphore for resource manager to own the + * the aux channel. + * NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_VBIOS + * Write the aux channel semaphore for vbios/efi to own the + * the aux channel. This value is used only for HW verification + * and should not be used in normal driver operation. + * NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_PMU + * Write the aux channel semaphore for pmu to own the + * the aux channel. This value is used only by pmu + * and should not be used in normal driver operation. + * NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_DPU + * Write the aux channel semaphore for dpu to own the + * the aux channel and should not be used in normal + * driver operation. + * NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_SEC2 + * Write the aux channel semaphore for sec2 to own the + * the aux channel and should not be used in normal + * driver operation. + * NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_RELEASE + * Write the aux channel semaphore for hardware to own the + * the aux channel. This value is used only for HW verification + * and should not be used in normal driver operation. + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_DP_AUXCH_SET_SEMA (0x731342U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_AUXCH_SET_SEMA_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_AUXCH_SET_SEMA_PARAMS_MESSAGE_ID (0x42U) + +typedef struct NV0073_CTRL_DP_AUXCH_SET_SEMA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 owner; +} NV0073_CTRL_DP_AUXCH_SET_SEMA_PARAMS; + +#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER 2:0 +#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_RELEASE (0x00000000U) +#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_RM (0x00000001U) +#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_VBIOS (0x00000002U) +#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_PMU (0x00000003U) +#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_DPU (0x00000004U) +#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_SEC2 (0x00000005U) + +/* + * NV0073_CTRL_CMD_DP_CTRL + * + * This command is used to set various displayPort configurations for + * the specified displayId such a lane count and link bandwidth. It + * is assumed that link training has already occurred. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must a dfp display. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * cmd + * This parameter is an input to this command. + * Here are the current defined fields: + * NV0073_CTRL_DP_CMD_SET_LANE_COUNT + * Set to specify the number of displayPort lanes to configure. + * NV0073_CTRL_DP_CMD_SET_LANE_COUNT_FALSE + * No request to set the displayport lane count. + * NV0073_CTRL_DP_CMD_SET_LANE_COUNT_TRUE + * Set this value to indicate displayport lane count change. + * NV0073_CTRL_DP_CMD_SET_LINK_BANDWIDTH + * Set to specify a request to change the link bandwidth. + * NV0073_CTRL_DP_CMD_SET_LINK_BANDWIDTH_FALSE + * No request to set the displayport link bandwidth. + * NV0073_CTRL_DP_CMD_SET_LINK_BANDWIDTH_TRUE + * Set this value to indicate displayport link bandwidth change. + * NV0073_CTRL_DP_CMD_SET_LINK_BANDWIDTH + * Set to specify a request to change the link bandwidth. + * NV0073_CTRL_DP_CMD_SET_LINK_BANDWIDTH_FALSE + * No request to set the displayport link bandwidth. + * NV0073_CTRL_DP_CMD_SET_LINK_BANDWIDTH_TRUE + * Set this value to indicate displayport link bandwidth change. + * NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD + * Set to disable downspread during link training. + * NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD_FALSE + * Downspread will be enabled. + * NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD_TRUE + * Downspread will be disabled (e.g. for compliance testing). + * NV0073_CTRL_DP_CMD_SET_FORMAT_MODE + * This field specifies the DP stream mode. + * NV0073_CTRL_DP_CMD_SET_FORMAT_MODE_SINGLE_STREAM + * This value indicates that single stream mode is specified. + * NV0073_CTRL_DP_CMD_SET_FORMAT_MODE_MULTI_STREAM + * This value indicates that multi stream mode is specified. + * NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING + * Set to do Fast link training (avoid AUX transactions for link + * training). We need to restore all the previous trained link settings + * (e.g. the drive current/preemphasis settings) before doing FLT. + * During FLT, we send training pattern 1 followed by training pattern 2 + * each for a period of 500us. + * NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING_NO + * Not a fast link training scenario. + * NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING_YES + * Do fast link training. + * NV0073_CTRL_DP_CMD_NO_LINK_TRAINING + * Set to do No link training. We need to restore all the previous + * trained link settings (e.g. the drive current/preemphasis settings) + * before doing NLT, but we don't need to do the Clock Recovery and + * Channel Equalization. (Please refer to NVIDIA PANEL SELFREFRESH + * CONTROLLER SPECIFICATION 3.1.6 for detail flow) + * NV0073_CTRL_DP_CMD_NO_LINK_TRAINING_NO + * Not a no link training scenario. + * NV0073_CTRL_DP_CMD_NO_LINK_TRAINING_YES + * Do no link training. + * NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING + * Specifies whether RM should use the DP Downspread setting specified by + * NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD command regardless of what the Display + * is capable of. This is used along with the Fake link training option so that + * we can configure the GPU to enable/disable spread when a real display is + * not connected. + * NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING_FORCE + * RM Always use the DP Downspread setting specified. + * NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING_DEFAULT + * RM will enable Downspread only if the display supports it. (default) + * NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING + * Specifies whether RM should skip HW training of the link. + * If this is the case then RM only updates its SW state without actually + * touching any HW registers. Clients should use this ONLY if it has determined - + * a. link is trained and not lost + * b. desired link config is same as current trained link config + * c. link is not in D3 (should be in D0) + * NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING_NO + * RM doesn't skip HW LT as the current Link Config is not the same as the + * requested Link Config. + * NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING_YES + * RM skips HW LT and only updates its SW state as client has determined that + * the current state of the link and the requested Link Config is the same. + * NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG + * Set if the client does not want link training to happen. + * This should ONLY be used for HW verification. + * NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG_FALSE + * This is normal production behaviour which shall perform + * link training or follow the normal procedure for lane count + * reduction. + * NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG_TRUE + * Set this value to not perform link config steps, this should + * only be turned on for HW verif testing. If _LINK_BANDWIDTH + * or _LANE_COUNT is set, RM will only write to the TX DP registers + * and perform no link training. + * NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED + * This field specifies if source grants Post Link training Adjustment request or not. + * NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED_NO + * Source does not grant Post Link training Adjustment request + * NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED_YES + * Source grants Post Link training Adjustment request + * Source wants to link train LT Tunable Repeaters + * NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING + * This field specifies if fake link training is to be done. This will + * program enough of the hardware to avoid any hardware hangs and + * depending upon option chosen by the client, OR will be enabled for + * transmisssion. + * NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_NO + * No Fake LT will be performed + * NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_DONOT_TOGGLE_TRANSMISSION + * SOR will be not powered up during Fake LT + * NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_TOGGLE_TRANSMISSION_ON + * SOR will be powered up during Fake LT + * NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER + * This field specifies if source wants to link train LT Tunable Repeaters or not. + * NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER_NO + * Source does not want to link train LT Tunable Repeaters + * NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER_YES + * NV0073_CTRL_DP_CMD_BANDWIDTH_TEST + * Set if the client wants to reset the link after the link + * training is done. As a part of uncommtting a DP display. + * NV0073_CTRL_DP_CMD_BANDWIDTH_TEST_NO + * This is for normal operation, if DD decided not to reset the link. + * NV0073_CTRL_DP_CMD_BANDWIDTH_TEST_YES + * This is to reset the link, if DD decided to uncommit the display because + * the link is no more required to be enabled, as in a DP compliance test. + * NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE + * Set if the client does not want link training to happen. + * This should ONLY be used for HW verification if necessary. + * NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_FALSE + * This is normal production behaviour which shall perform + * pre link training checks such as if both rx and tx are capable + * of the requested config for lane and link bw. + * NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_TRUE + * Set this value to bypass link config check, this should + * only be turned on for HW verif testing. If _LINK_BANDWIDTH + * or _LANE_COUNT is set, RM will not check TX and DX caps. + * NV0073_CTRL_DP_CMD_FALLBACK_CONFIG + * Set if requested config by client fails and if link if being + * trained for the fallback config. + * NV0073_CTRL_DP_CMD_FALLBACK_CONFIG_FALSE + * This is the normal case when the link is being trained for a requested config. + * NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_TRUE + * Set this value in case the link configuration for requested config fails + * and the link is being trained for a fallback config. + * NV0073_CTRL_DP_CMD_ENABLE_FEC + * Specifies whether RM should set NV_DPCD14_FEC_CONFIGURATION_FEC_READY + * before link training if client has determined that FEC is required(for DSC). + * If required to be enabled RM sets FEC enable bit in panel, start link training. + * Enabling/disabling FEC on GPU side is not done during Link training + * and RM Ctrl call NV0073_CTRL_CMD_DP_CONFIGURE_FEC has to be called + * explicitly to enable/disable FEC after LT(including PostLT LQA). + * If enabled, FEC would be disabled while powering down the link. + * Client has to make sure to account for 3% overhead of transmitting + * FEC symbols while calculating DP bandwidth. + * NV0073_CTRL_DP_CMD_ENABLE_FEC_FALSE + * This is the normal case when FEC is not required + * NV0073_CTRL_DP_CMD_ENABLE_FEC_TRUE + * Set this value in case FEC needs to be enabled + * data + * This parameter is an input and output to this command. + * Here are the current defined fields: + * NV0073_CTRL_DP_DATA_SET_LANE_COUNT + * This field specifies the desired setting for lane count. A client + * may choose any lane count as long as it does not exceed the + * capability of DisplayPort receiver as indicated in the + * receiver capability field. The valid values for this field are: + * NV0073_CTRL_DP_DATA_SET_LANE_COUNT_0 + * For zero-lane configurations, link training is shut down. + * NV0073_CTRL_DP_DATA_SET_LANE_COUNT_1 + * For one-lane configurations, lane0 is used. + * NV0073_CTRL_DP_DATA_SET_LANE_COUNT_2 + * For two-lane configurations, lane0 and lane1 is used. + * NV0073_CTRL_DP_DATA_SET_LANE_COUNT_4 + * For four-lane configurations, all lanes are used. + * NV0073_CTRL_DP_DATA_SET_LANE_COUNT_8 + * For devices that supports 8-lane DP. + * On return, the lane count setting is returned which may be + * different from the requested input setting. + * NV0073_CTRL_DP_DATA_SET_LINK_BW + * This field specifies the desired setting for link bandwidth. There + * are only four supported main link bandwidth settings. The + * valid values for this field are: + * NV0073_CTRL_DP_DATA_SET_LINK_BW_1_62GBPS + * NV0073_CTRL_DP_DATA_SET_LINK_BW_2_70GBPS + * NV0073_CTRL_DP_DATA_SET_LINK_BW_5_40GBPS + * NV0073_CTRL_DP_DATA_SET_LINK_BW_8_10GBPS + * On return, the link bandwidth setting is returned which may be + * different from the requested input setting. + * NV0073_CTRL_DP_DATA_TARGET + * This field specifies which physical repeater or sink to be trained. + * Client should make sure + * 1. Physical repeater should be targeted in order, start from the one closest to GPU. + * 2. All physical repeater is properly trained before targets sink. + * The valid values for this field are: + * NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_X + * 'X' denotes physical repeater index. It's a 1-based index to + * reserve 0 for _SINK. + * 'X' can't be more than 8. + * NV0073_CTRL_DP_DATA_TARGET_SINK + * err + * This parameter specifies provides info regarding the outcome + * of this calling control call. If zero, no errors were found. + * Otherwise, this parameter will specify the error detected. + * The valid parameter is broken down as follows: + * NV0073_CTRL_DP_ERR_SET_LANE_COUNT + * If set to _ERR, set lane count failed. + * NV0073_CTRL_DP_ERR_SET_LINK_BANDWIDTH + * If set to _ERR, set link bandwidth failed. + * NV0073_CTRL_DP_ERR_DISABLE_DOWNSPREAD + * If set to _ERR, disable downspread failed. + * NV0073_CTRL_DP_ERR_INVALID_PARAMETER + * If set to _ERR, at least one of the calling functions + * failed due to an invalid parameter. + * NV0073_CTRL_DP_ERR_SET_LINK_TRAINING + * If set to _ERR, link training failed. + * NV0073_CTRL_DP_ERR_TRAIN_PHY_REPEATER + * If set to _ERR, the operation to Link Train repeater is failed. + * NV0073_CTRL_DP_ERR_ENABLE_FEC + * If set to _ERR, the operation to enable FEC is failed. + * retryTimeMs + * This parameter is an output to this command. In case of + * NVOS_STATUS_ERROR_RETRY return status, this parameter returns the time + * duration in milli-seconds after which client should retry this command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_ERROR_RETRY + */ + +#define NV0073_CTRL_CMD_DP_CTRL (0x731343U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_CTRL_PARAMS_MESSAGE_ID (0x43U) + +typedef struct NV0073_CTRL_DP_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 cmd; + NvU32 data; + NvU32 err; + NvU32 retryTimeMs; + NvU32 eightLaneDpcdBaseAddr; +} NV0073_CTRL_DP_CTRL_PARAMS; + +#define NV0073_CTRL_DP_CMD_SET_LANE_COUNT 0:0 +#define NV0073_CTRL_DP_CMD_SET_LANE_COUNT_FALSE (0x00000000U) +#define NV0073_CTRL_DP_CMD_SET_LANE_COUNT_TRUE (0x00000001U) +#define NV0073_CTRL_DP_CMD_SET_LINK_BW 1:1 +#define NV0073_CTRL_DP_CMD_SET_LINK_BW_FALSE (0x00000000U) +#define NV0073_CTRL_DP_CMD_SET_LINK_BW_TRUE (0x00000001U) +#define NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD 2:2 +#define NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD_FALSE (0x00000000U) +#define NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD_TRUE (0x00000001U) +#define NV0073_CTRL_DP_CMD_UNUSED 3:3 +#define NV0073_CTRL_DP_CMD_SET_FORMAT_MODE 4:4 +#define NV0073_CTRL_DP_CMD_SET_FORMAT_MODE_SINGLE_STREAM (0x00000000U) +#define NV0073_CTRL_DP_CMD_SET_FORMAT_MODE_MULTI_STREAM (0x00000001U) +#define NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING 5:5 +#define NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING_NO (0x00000000U) +#define NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING_YES (0x00000001U) +#define NV0073_CTRL_DP_CMD_NO_LINK_TRAINING 6:6 +#define NV0073_CTRL_DP_CMD_NO_LINK_TRAINING_NO (0x00000000U) +#define NV0073_CTRL_DP_CMD_NO_LINK_TRAINING_YES (0x00000001U) +#define NV0073_CTRL_DP_CMD_SET_ENHANCED_FRAMING 7:7 +#define NV0073_CTRL_DP_CMD_SET_ENHANCED_FRAMING_FALSE (0x00000000U) +#define NV0073_CTRL_DP_CMD_SET_ENHANCED_FRAMING_TRUE (0x00000001U) +#define NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING 8:8 +#define NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING_DEFAULT (0x00000000U) +#define NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING_FORCE (0x00000001U) +#define NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING 9:9 +#define NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING_NO (0x00000000U) +#define NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING_YES (0x00000001U) +#define NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED 10:10 +#define NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED_NO (0x00000000U) +#define NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED_YES (0x00000001U) +#define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING 12:11 +#define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_NO (0x00000000U) +#define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_DONOT_TOGGLE_TRANSMISSION (0x00000001U) +#define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_TOGGLE_TRANSMISSION_ON (0x00000002U) +#define NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER 13:13 +#define NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER_NO (0x00000000U) +#define NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER_YES (0x00000001U) +#define NV0073_CTRL_DP_CMD_FALLBACK_CONFIG 14:14 +#define NV0073_CTRL_DP_CMD_FALLBACK_CONFIG_FALSE (0x00000000U) +#define NV0073_CTRL_DP_CMD_FALLBACK_CONFIG_TRUE (0x00000001U) +#define NV0073_CTRL_DP_CMD_ENABLE_FEC 15:15 +#define NV0073_CTRL_DP_CMD_ENABLE_FEC_FALSE (0x00000000U) +#define NV0073_CTRL_DP_CMD_ENABLE_FEC_TRUE (0x00000001U) + +#define NV0073_CTRL_DP_CMD_BANDWIDTH_TEST 29:29 +#define NV0073_CTRL_DP_CMD_BANDWIDTH_TEST_NO (0x00000000U) +#define NV0073_CTRL_DP_CMD_BANDWIDTH_TEST_YES (0x00000001U) +#define NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE 30:30 +#define NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG 31:31 +#define NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG_FALSE (0x00000000U) +#define NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG_TRUE (0x00000001U) + +#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT 4:0 +#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_0 (0x00000000U) +#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_1 (0x00000001U) +#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_2 (0x00000002U) +#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_4 (0x00000004U) +#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_8 (0x00000008U) +#define NV0073_CTRL_DP_DATA_SET_LINK_BW 15:8 +#define NV0073_CTRL_DP_DATA_SET_LINK_BW_1_62GBPS (0x00000006U) +#define NV0073_CTRL_DP_DATA_SET_LINK_BW_2_16GBPS (0x00000008U) +#define NV0073_CTRL_DP_DATA_SET_LINK_BW_2_43GBPS (0x00000009U) +#define NV0073_CTRL_DP_DATA_SET_LINK_BW_2_70GBPS (0x0000000AU) +#define NV0073_CTRL_DP_DATA_SET_LINK_BW_3_24GBPS (0x0000000CU) +#define NV0073_CTRL_DP_DATA_SET_LINK_BW_4_32GBPS (0x00000010U) +#define NV0073_CTRL_DP_DATA_SET_LINK_BW_5_40GBPS (0x00000014U) +#define NV0073_CTRL_DP_DATA_SET_LINK_BW_8_10GBPS (0x0000001EU) +#define NV0073_CTRL_DP_DATA_SET_ENHANCED_FRAMING 18:18 +#define NV0073_CTRL_DP_DATA_SET_ENHANCED_FRAMING_NO (0x00000000U) +#define NV0073_CTRL_DP_DATA_SET_ENHANCED_FRAMING_YES (0x00000001U) +#define NV0073_CTRL_DP_DATA_TARGET 22:19 +#define NV0073_CTRL_DP_DATA_TARGET_SINK (0x00000000U) +#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_0 (0x00000001U) +#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_1 (0x00000002U) +#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_2 (0x00000003U) +#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_3 (0x00000004U) +#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_4 (0x00000005U) +#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_5 (0x00000006U) +#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_6 (0x00000007U) +#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_7 (0x00000008U) + +#define NV0073_CTRL_DP_ERR_SET_LANE_COUNT 0:0 +#define NV0073_CTRL_DP_ERR_SET_LANE_COUNT_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_SET_LANE_COUNT_ERR (0x00000001U) +#define NV0073_CTRL_DP_ERR_SET_LINK_BW 1:1 +#define NV0073_CTRL_DP_ERR_SET_LINK_BW_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_SET_LINK_BW_ERR (0x00000001U) +#define NV0073_CTRL_DP_ERR_DISABLE_DOWNSPREAD 2:2 +#define NV0073_CTRL_DP_ERR_DISABLE_DOWNSPREAD_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_DISABLE_DOWNSPREAD_ERR (0x00000001U) +#define NV0073_CTRL_DP_ERR_UNUSED 3:3 +#define NV0073_CTRL_DP_ERR_CLOCK_RECOVERY 4:4 +#define NV0073_CTRL_DP_ERR_CLOCK_RECOVERY_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_CLOCK_RECOVERY_ERR (0x00000001U) +#define NV0073_CTRL_DP_ERR_CHANNEL_EQUALIZATION 5:5 +#define NV0073_CTRL_DP_ERR_CHANNEL_EQUALIZATION_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_CHANNEL_EQUALIZATION_ERR (0x00000001U) +#define NV0073_CTRL_DP_ERR_TRAIN_PHY_REPEATER 6:6 +#define NV0073_CTRL_DP_ERR_TRAIN_PHY_REPEATER_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_TRAIN_PHY_REPEATER_ERR (0x00000001U) +#define NV0073_CTRL_DP_ERR_ENABLE_FEC 7:7 +#define NV0073_CTRL_DP_ERR_ENABLE_FEC_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_ENABLE_FEC_ERR (0x00000001U) +#define NV0073_CTRL_DP_ERR_CR_DONE_LANE 11:8 +#define NV0073_CTRL_DP_ERR_CR_DONE_LANE_0_LANE (0x00000000U) +#define NV0073_CTRL_DP_ERR_CR_DONE_LANE_1_LANE (0x00000001U) +#define NV0073_CTRL_DP_ERR_CR_DONE_LANE_2_LANE (0x00000002U) +#define NV0073_CTRL_DP_ERR_CR_DONE_LANE_4_LANE (0x00000004U) +#define NV0073_CTRL_DP_ERR_CR_DONE_LANE_8_LANE (0x00000008U) +#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE 15:12 +#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE_0_LANE (0x00000000U) +#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE_1_LANE (0x00000001U) +#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE_2_LANE (0x00000002U) +#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE_4_LANE (0x00000004U) +#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE_8_LANE (0x00000008U) +#define NV0073_CTRL_DP_ERR_INVALID_PARAMETER 30:30 +#define NV0073_CTRL_DP_ERR_INVALID_PARAMETER_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_INVALID_PARAMETER_ERR (0x00000001U) +#define NV0073_CTRL_DP_ERR_LINK_TRAINING 31:31 +#define NV0073_CTRL_DP_ERR_LINK_TRAINING_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ERR_LINK_TRAINING_ERR (0x00000001U) + +/* + * NV0073_CTRL_DP_LANE_DATA_PARAMS + * + * This structure provides lane characteristics. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must a dfp display. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * numLanes + * Indicates number of lanes for which the data is valid + * data + * This parameter is an input to this command. + * Here are the current defined fields: + * NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS + * This field specifies the preemphasis level set in the lane. + * The valid values for this field are: + * NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_NONE + * No-preemphais for this lane. + * NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL1 + * Preemphasis set to 3.5 dB. + * NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL2 + * Preemphasis set to 6.0 dB. + * NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL3 + * Preemphasis set to 9.5 dB. + * NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT + * This field specifies the drive current set in the lane. + * The valid values for this field are: + * NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL0 + * Drive current level is set to 8 mA + * NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL1 + * Drive current level is set to 12 mA + * NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL2 + * Drive current level is set to 16 mA + * NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL3 + * Drive current level is set to 24 mA + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_MAX_LANES 8U + +typedef struct NV0073_CTRL_DP_LANE_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 numLanes; + NvU32 data[NV0073_CTRL_MAX_LANES]; +} NV0073_CTRL_DP_LANE_DATA_PARAMS; + +#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS 1:0 +#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_NONE (0x00000000U) +#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL1 (0x00000001U) +#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL2 (0x00000002U) +#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL3 (0x00000003U) +#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT 3:2 +#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL0 (0x00000000U) +#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL1 (0x00000001U) +#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL2 (0x00000002U) +#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL3 (0x00000003U) + +/* + * NV0073_CTRL_CMD_GET_DP_LANE_DATA + * + * This command is used to get the current pre-emphasis and drive current + * level values for the specified number of lanes. + * + * The command takes a NV0073_CTRL_DP_LANE_DATA_PARAMS structure as the + * argument with the appropriate subDeviceInstance and displayId filled. + * The arguments of this structure and the format of preemphasis and drive- + * current levels are described above. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * NOTE: This control call is only for testing purposes and + * should not be used in normal DP operations. Preemphais + * and drive current level will be set during Link training + * in normal DP operations + * + */ + +#define NV0073_CTRL_CMD_DP_GET_LANE_DATA (0x731345U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | 0x45" */ + + +/* + * NV0073_CTRL_CMD_SET_DP_LANE_DATA + * + * This command is used to set the pre-emphasis and drive current + * level values for the specified number of lanes. + * + * The command takes a NV0073_CTRL_DP_LANE_DATA_PARAMS structure as the + * argument with the appropriate subDeviceInstance, displayId, number of + * lanes, preemphasis and drive current values filled in. + * The arguments of this structure and the format of preemphasis and drive- + * current levels are described above. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * NOTE: This control call is only for testing purposes and + * should not be used in normal DP operations. Preemphais + * and drivecurrent will be set during Link training in + * normal DP operations + * + */ + +#define NV0073_CTRL_CMD_DP_SET_LANE_DATA (0x731346U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | 0x46" */ + +/* + * NV0073_CTRL_DP_CSTM + * + * This structure specifies the 80 bit DP CSTM Test Pattern data + * The fields of this structure are to be specified as follows: + * lower takes bits 31:0 + * middle takes bits 63:32 + * upper takes bits 79:64 + * + */ +typedef struct NV0073_CTRL_DP_CSTM { + NvU32 lower; + NvU32 middle; + NvU32 upper; +} NV0073_CTRL_DP_CSTM; + +/* + * NV0073_CTRL_DP_TESTPATTERN + * + * This structure specifies the possible test patterns available in + * display port. The field testPattern can be one of the following + * values. + * NV0073_CTRL_DP_SET_TESTPATTERN_DATA_NONE + * No test pattern on the main link + * NV0073_CTRL_DP_SET_TESTPATTERN_DATA_D10_2 + * D10.2 pattern on the main link + * NV0073_CTRL_DP_SET_TESTPATTERN_DATA_SERMP + * SERMP pattern on main link + * NV0073_CTRL_DP_SET_TESTPATTERN_DATA_PRBS_7 + * PRBS7 pattern on the main link + * + */ + +typedef struct NV0073_CTRL_DP_TESTPATTERN { + NvU32 testPattern; +} NV0073_CTRL_DP_TESTPATTERN; + +#define NV0073_CTRL_DP_TESTPATTERN_DATA 2:0 +#define NV0073_CTRL_DP_TESTPATTERN_DATA_NONE (0x00000000U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_D10_2 (0x00000001U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_SERMP (0x00000002U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_7 (0x00000003U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_CSTM (0x00000004U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_HBR2COMPLIANCE (0x00000005U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_CP2520PAT3 (0x00000006U) + +/* + * NV0073_CTRL_CMD_DP_SET_TESTPATTERN + * + * This command forces the main link to output the selected test patterns + * supported in DP specs. + * + * The command takes a NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS structure as the + * argument with the appropriate subDeviceInstance, displayId and test pattern + * to be set as inputs. + * The arguments of this structure and the format of test patterns are + * described above. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must a dfp display. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * testPattern + * This parameter is of type NV0073_CTRL_DP_TESTPATTERN and specifies + * the testpattern to set on displayport. The format of this structure + * is described above. + * laneMask + * This parameter specifies the bit mask of DP lanes on which test + * pattern is to be applied. + * lower + * This parameter specifies the lower 64 bits of the CSTM test pattern + * upper + * This parameter specifies the upper 16 bits of the CSTM test pattern + * bIsHBR2 + * This Boolean parameter is set to TRUE if HBR2 compliance test is + * being performed. + * bSkipLaneDataOverride + * skip override of pre-emp and drive current + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * NOTE: This control call is only for testing purposes and + * should not be used in normal DP operations. Preemphais + * and drivecurrent will be set during Link training in + * normal DP operations + * + */ + +#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_MESSAGE_ID (0x47U) + +typedef struct NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NV0073_CTRL_DP_TESTPATTERN testPattern; + NvU8 laneMask; + NV0073_CTRL_DP_CSTM cstm; + NvBool bIsHBR2; + NvBool bSkipLaneDataOverride; +} NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS; + +#define NV0073_CTRL_CMD_DP_SET_TESTPATTERN (0x731347U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_CSTM0 31:0 +#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_CSTM1 63:32 +#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_CSTM2 15:0 + +/* + * NV0073_CTRL_CMD_GET_DP_TESTPATTERN + * + * This command returns the current test pattern set on the main link of + * Display Port. + * + * The command takes a NV0073_CTRL_DP_GET_TESTPATTERN_PARAMS structure as the + * argument with the appropriate subDeviceInstance, displayId as inputs and + * returns the current test pattern in testPattern field of the structure. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must a dfp display. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * testPattern + * This parameter is of type NV0073_CTRL_DP_TESTPATTERN and specifies the + * testpattern set on displayport. The format of this structure is + * described above. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * NOTE: This control call is only for testing purposes and + * should not be used in normal DP operations. + * + */ + +#define NV0073_CTRL_DP_GET_TESTPATTERN_PARAMS_MESSAGE_ID (0x48U) + +typedef struct NV0073_CTRL_DP_GET_TESTPATTERN_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NV0073_CTRL_DP_TESTPATTERN testPattern; +} NV0073_CTRL_DP_GET_TESTPATTERN_PARAMS; + + +#define NV0073_CTRL_CMD_DP_GET_TESTPATTERN (0x731348U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_TESTPATTERN_PARAMS_MESSAGE_ID" */ + +/* + * NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA + * + * This structure specifies the Pre-emphasis/Drive Current/Postcursor2/TxPu information + * for a display port device. These are the the current values that RM is + * using to map the levels for Pre-emphasis and Drive Current for Link + * Training. + * preEmphasis + * This field specifies the preemphasis values. + * driveCurrent + * This field specifies the driveCurrent values. + * postcursor2 + * This field specifies the postcursor2 values. + * TxPu + * This field specifies the pull-up current source drive values. + */ +#define NV0073_CTRL_MAX_DRIVECURRENT_LEVELS 4U +#define NV0073_CTRL_MAX_PREEMPHASIS_LEVELS 4U +#define NV0073_CTRL_MAX_POSTCURSOR2_LEVELS 4U + +typedef struct NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_1 { + NvU32 preEmphasis; + NvU32 driveCurrent; + NvU32 postCursor2; + NvU32 TxPu; +} NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_1; + +typedef NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_1 NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_SLICE1[NV0073_CTRL_MAX_PREEMPHASIS_LEVELS]; + +typedef NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_SLICE1 NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_SLICE2[NV0073_CTRL_MAX_DRIVECURRENT_LEVELS]; + +typedef NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_SLICE2 NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA[NV0073_CTRL_MAX_POSTCURSOR2_LEVELS]; + + +/* + * NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA + * + * This command is used to override the Pre-emphasis/Drive Current/PostCursor2/TxPu + * data in the RM. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the digital display for which the + * data should be returned. The display ID must a digital display. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * dpData + * This parameter is of type NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA + * and specifies the Pre-emphasis/Drive Current/Postcursor2/TxPu information + * for a display port device. + * The command takes a NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS + * structure as the argument with the appropriate subDeviceInstance, displayId, + * and dpData. The fields of this structure are described above. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS_MESSAGE_ID (0x51U) + +typedef struct NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA dpData; +} NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS; + +#define NV0073_CTRL_CMD_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA (0x731351U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS_MESSAGE_ID" */ + +/* + * NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA + * + * This command is used to get the Pre-emphasis/Drive Current/PostCursor2/TxPu data. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the digital display for which the + * data should be returned. The display ID must a digital display. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * The command takes a NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS + * structure as the argument with the appropriate subDeviceInstance, displayId, + * and dpData. The fields of this structure are described above. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS_MESSAGE_ID (0x52U) + +typedef struct NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NV0073_CTRL_DP_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA dpData; +} NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS; + +#define NV0073_CTRL_CMD_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA (0x731352U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS_MESSAGE_ID" */ + + + +/* + * NV0073_CTRL_CMD_DP_MAIN_LINK_CTRL + * + * This command is used to set various Main Link configurations for + * the specified displayId such as powering up/down Main Link. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the DP display which owns + * the Main Link to be adjusted. The display ID must a DP display + * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * ctrl + * Here are the current defined fields: + * NV0073_CTRL_DP_MAIN_LINK_CTRL_POWER_STATE_POWERDOWN + * This value will power down Main Link. + * NV0073_CTRL_DP_MAIN_LINK_CTRL_POWER_STATE_POWERUP + * This value will power up Main Link. + * +*/ +#define NV0073_CTRL_CMD_DP_MAIN_LINK_CTRL (0x731356U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_MAIN_LINK_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_MAIN_LINK_CTRL_PARAMS_MESSAGE_ID (0x56U) + +typedef struct NV0073_CTRL_DP_MAIN_LINK_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 ctrl; +} NV0073_CTRL_DP_MAIN_LINK_CTRL_PARAMS; + +#define NV0073_CTRL_DP_MAIN_LINK_CTRL_POWER_STATE 0:0 +#define NV0073_CTRL_DP_MAIN_LINK_CTRL_POWER_STATE_POWERDOWN (0x00000000U) +#define NV0073_CTRL_DP_MAIN_LINK_CTRL_POWER_STATE_POWERUP (0x00000001U) + + + +/* + * NV0073_CTRL_CMD_DP_GET_AUDIO_MUTESTREAM + * + * This command returns the current audio mute state on the main link of Display Port + * + * The command takes a NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS structure as the + * argument with the appropriate subDeviceInstance, displayId as inputs and returns the + * current mute status in mute field of the structure. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the audio stream + * state should be returned. The display ID must a DP display. + * If the display ID is invalid or if it is not a DP display, + * this call will return NV_ERR_INVALID_ARGUMENT. + * mute + * This parameter will return one of the following values: + * NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_DISABLE + * Audio mute is currently disabled. + * NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_ENABLE + * Audio mute is currently enabled. + * NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_AUTO + * Audio mute is automatically controlled by hardware. + * NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_UNKNOWN + * Audio mute is currently in an unknown state. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * + */ +#define NV0073_CTRL_CMD_DP_GET_AUDIO_MUTESTREAM (0x731358U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID (0x58U) + +typedef struct NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 mute; +} NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS; + +#define NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_DISABLE (0x00000000U) +#define NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_ENABLE (0x00000001U) +#define NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_AUTO (0x00000002U) +#define NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_UNKNOWN (0x00000003U) + +/* + * NV0073_CTRL_CMD_DP_SET_AUDIO_MUTESTREAM + * + * This command sets the current audio mute state on the main link of Display Port + * + * The command takes a NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS structure as the + * argument with the appropriate subDeviceInstance, displayId as inputs and whether to enable + * or disable mute in the parameter - mute. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the audio stream + * state should be returned. The display ID must a DP display. + * If the display ID is invalid or if it is not a DP display, + * this call will return NV_ERR_INVALID_ARGUMENT. + * mute + * This parameter is an input to this command. + * Here are the current defined values: + * NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_DISABLE + * Audio mute will be disabled. + * NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_ENABLE + * Audio mute will be enabled. + * NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_AUTO + * Audio mute will be automatically controlled by hardware. + * + * Note: Any other value for mute in NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS is not allowed and + * the API will return an error. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + * + */ +#define NV0073_CTRL_CMD_DP_SET_AUDIO_MUTESTREAM (0x731359U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID (0x59U) + +typedef struct NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 mute; +} NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_ASSR_CTRL + * + * This command is used to control and query DisplayPort ASSR + * settings for the specified displayId. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the DP display which owns + * the Main Link to be adjusted. The display ID must a DP display + * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * cmd + * This input parameter specifies the command to execute. Legal + * values for this parameter include: + * NV0073_CTRL_DP_ASSR_CMD_QUERY_STATE + * This field can be used to query ASSR state. When used the ASSR + * state value is returned in the data parameter. + * NV0073_CTRL_DP_ASSR_CMD_DISABLE + * This field can be used to control the ASSR disable state. + * NV0073_CTRL_DP_ASSR_CMD_FORCE_STATE + * This field can be used to control ASSR State without looking at + * whether the display supports it. Used in conjunction with + * Fake link training. Note that this updates the state on the + * source side only. The sink is assumed to be configured for ASSR + * by the client (DD). + * data + * This parameter specifies the data associated with the cmd + * parameter. + * NV0073_CTRL_DP_ASSR_DATA_STATE_ENABLED + * This field indicates the state of ASSR when queried using cmd + * parameter. When used to control the State, it indicates whether + * ASSR should be enabled or disabled. + * NV0073_CTRL_DP_ASSR_DATA_STATE_ENABLED_NO + * When queried this flag indicates that ASSR is not enabled on the sink. + * When used as the data for CMD_FORCE_STATE, it requests ASSR to + * to be disabled on the source side. + * NV0073_CTRL_DP_ASSR_DATA_STATE_ENABLED_YES + * When queried this flag indicates that ASSR is not enabled on the sink. + * When used as the data for CMD_FORCE_STATE, it requests ASSR to + * to be enabled on the source side. + * err + * This output parameter specifies any errors associated with the cmd + * parameter. + * NV0073_CTRL_DP_ASSR_ERR_CAP + * This field indicates the error pertaining to ASSR capability of + * the sink device. + * NV0073_CTRL_DP_ASSR_ERR_CAP_NOERR + * This flag indicates there is no error. + * NV0073_CTRL_DP_ASSR_ERR_CAP_ERR + * This flag indicates that the sink is not ASSR capable. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_CMD_DP_ASSR_CTRL (0x73135aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_ASSR_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_ASSR_CTRL_PARAMS_MESSAGE_ID (0x5AU) + +typedef struct NV0073_CTRL_DP_ASSR_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 cmd; + NvU32 data; + NvU32 err; +} NV0073_CTRL_DP_ASSR_CTRL_PARAMS; + +#define NV0073_CTRL_DP_ASSR_CMD 31:0 +#define NV0073_CTRL_DP_ASSR_CMD_QUERY_STATE (0x00000001U) +#define NV0073_CTRL_DP_ASSR_CMD_DISABLE (0x00000002U) +#define NV0073_CTRL_DP_ASSR_CMD_FORCE_STATE (0x00000003U) +#define NV0073_CTRL_DP_ASSR_CMD_ENABLE (0x00000004U) +#define NV0073_CTRL_DP_ASSR_DATA_STATE_ENABLED 0:0 +#define NV0073_CTRL_DP_ASSR_DATA_STATE_ENABLED_NO (0x00000000U) +#define NV0073_CTRL_DP_ASSR_DATA_STATE_ENABLED_YES (0x00000001U) +#define NV0073_CTRL_DP_ASSR_ERR_CAP 0:0 +#define NV0073_CTRL_DP_ASSR_ERR_CAP_NOERR (0x00000000U) +#define NV0073_CTRL_DP_ASSR_ERR_CAP_ERR (0x00000001U) + +/* + * NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID + * + * This command is used to assign a displayId from the free pool + * to a specific AUX Address in a DP 1.2 topology. The topology + * is uniquely identified by the DisplayId of the DP connector. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This is the DisplayId of the DP connector to which the topology + * is rooted. + * preferredDisplayId + * Client can sent a preferredDisplayID which RM can use during allocation + * if available. If this Id is a part of allDisplayMask in RM then we return + * a free available Id to the client. However, if this is set to + * NV0073_CTRL_CMD_DP_INVALID_PREFERRED_DISPLAY_ID then we return allDisplayMask value. + * useBFM + * Set to true if DP-BFM is used during emulation/RTL Sim. + * + * [out] displayIdAssigned + * This is the out field that will receive the new displayId. If the + * function fails this is guaranteed to be 0. + * [out] allDisplayMask + * This is allDisplayMask RM variable which is returned only when + * preferredDisplayId is set to NV0073_CTRL_CMD_DP_INVALID_PREFERRED_DISPLAY_ID + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID (0x73135bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS_MESSAGE_ID" */ + +/* + * There cannot be more than 128 devices in a topology (also by DP 1.2 specification) + * NOTE: Temporarily lowered to pass XAPI RM tests. Should be reevaluated! + */ +#define NV0073_CTRL_CMD_DP_MAX_TOPOLOGY_NODES 120U +#define NV0073_CTRL_CMD_DP_INVALID_PREFERRED_DISPLAY_ID 0xffffffffU + +#define NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS_MESSAGE_ID (0x5BU) + +typedef struct NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 preferredDisplayId; + + NvBool force; + NvBool useBFM; + + NvU32 displayIdAssigned; + NvU32 allDisplayMask; +} NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID + * + * This command is used to return a multistream displayid to the unused pool. + * You must not call this function while either the ARM or ASSEMBLY state cache + * refers to this display-id. The head must not be attached. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This is the displayId to free. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + * + */ +#define NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID (0x73135cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS_MESSAGE_ID (0x5CU) + +typedef struct NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; +} NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS; + + + +/* + * NV0073_CTRL_CMD_DP_GET_LINK_CONFIG + * + * This command is used to query DisplayPort link config + * settings on the transmitter side. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the DP display which owns + * the Main Link to be queried. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * laneCount + * Number of lanes the DP transmitter hardware is set up to drive. + * linkBW + * The BW of each lane that the DP transmitter hardware is set up to drive. + * The values returned will be according to the DP specifications. + * + */ +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG (0x731360U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS_MESSAGE_ID (0x60U) + +typedef struct NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 laneCount; + NvU32 linkBW; +} NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS; + +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT 3:0 +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_0 (0x00000000U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_1 (0x00000001U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_2 (0x00000002U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_4 (0x00000004U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW 3:0 +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_1_62GBPS (0x00000006U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_2_70GBPS (0x0000000aU) + +/* + * NV0073_CTRL_CMD_DP_GET_EDP_DATA + * + * This command is used to query Embedded DisplayPort information. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the eDP display which owns + * the Main Link to be queried. + * If more than one displayId bit is set or the displayId is not a eDP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * data + * This output parameter specifies the data associated with the eDP display. + * It is only valid if this function returns NV_OK. + * NV0073_CTRL_CMD_DP_GET_EDP_DATA_PANEL_POWER + * This field indicates the state of the eDP panel power. + * NV0073_CTRL_CMD_DP_GET_EDP_DATA_PANEL_POWER_OFF + * This eDP panel is powered off. + * NV0073_CTRL_CMD_DP_GET_EDP_DATA_PANEL_POWER_ON + * This eDP panel is powered on. + * NV0073_CTRL_CMD_DP_GET_EDP_DATA_DPCD_POWER_OFF + * This field tells the client if DPCD power off command + * should be used for the current eDP panel. + * NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_OFF_ENABLE + * This eDP panel can use DPCD to power off the panel. + * NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_OFF_DISABLE + * This eDP panel cannot use DPCD to power off the panel. + * NV0073_CTRL_DP_GET_EDP_DATA_DPCD_SET_POWER + * This field tells the client current eDP panel DPCD SET_POWER (0x600) status + * NV0073_CTRL_DP_GET_EDP_DATA_DPCD_SET_POWER_D0 + * This eDP panel is current up and in full power mode. + * NV0073_CTRL_DP_GET_EDP_DATA_DPCD_SET_POWER_D3 + * This eDP panel is current standby. + */ +#define NV0073_CTRL_CMD_DP_GET_EDP_DATA (0x731361U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_EDP_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_GET_EDP_DATA_PARAMS_MESSAGE_ID (0x61U) + +typedef struct NV0073_CTRL_DP_GET_EDP_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 data; +} NV0073_CTRL_DP_GET_EDP_DATA_PARAMS; + +#define NV0073_CTRL_DP_GET_EDP_DATA_PANEL_POWER 0:0 +#define NV0073_CTRL_DP_GET_EDP_DATA_PANEL_POWER_OFF (0x00000000U) +#define NV0073_CTRL_DP_GET_EDP_DATA_PANEL_POWER_ON (0x00000001U) +#define NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_OFF 1:1 +#define NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_OFF_ENABLE (0x00000000U) +#define NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_OFF_DISABLE (0x00000001U) +#define NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_STATE 2:2 +#define NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_STATE_D0 (0x00000000U) +#define NV0073_CTRL_DP_GET_EDP_DATA_DPCD_POWER_STATE_D3 (0x00000001U) +/* + * NV0073_CTRL_CMD_DP_CONFIG_STREAM + * + * This command sets various multi/single stream related params for + * for a given head. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * Head + * Specifies the head index for the stream. + * sorIndex + * Specifies the SOR index for the stream. + * dpLink + * Specifies the DP link: either 0 or 1 (A , B) + * bEnableOverride + * Specifies whether we're manually configuring this stream. + * If not set, none of the remaining settings have any effect. + * bMST + * Specifies whether in Multistream or Singlestream mode. + * MST/SST + * Structures for passing in either Multistream or Singlestream params + * slotStart + * Specifies the start value of the timeslot + * slotEnd + * Specifies the end value of the timeslot + * PBN + * Specifies the PBN for the timeslot. + * minHBlank + * Specifies the min HBlank + * minVBlank + * Specifies the min VBlank + * sendACT -- deprecated. A new control call has been added. + * Specifies whether ACT has to be sent or not. + * tuSize + * Specifies TU size value + * watermark + * Specifies stream watermark. + * linkClkFreqHz -- moving to MvidWarParams. Use that instead. + * Specifies the link freq in Hz. Note that this is the byte clock. + * eg: = (5.4 Ghz / 10) + * actualPclkHz; -- moving to MvidWarParams. Use that instead. + * Specifies the actual pclk freq in Hz. + * mvidWarEnabled + * Specifies whether MVID WAR is enabled. + * MvidWarParams + * Is valid if mvidWarEnabled is true. + * bEnableTwoHeadOneOr + * Whether two head one OR is enabled. If this is set then RM will + * replicate SF settings of Master head on Slave head. Head index + * passed should be of Master Head. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC: when this command has already been called + * + */ +#define NV0073_CTRL_CMD_DP_CONFIG_STREAM (0x731362U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS_MESSAGE_ID (0x62U) + +typedef struct NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvU32 sorIndex; + NvU32 dpLink; + + NvBool bEnableOverride; + NvBool bMST; + NvU32 singleHeadMultistreamMode; + NvU32 hBlankSym; + NvU32 vBlankSym; + NvU32 colorFormat; + NvBool bEnableTwoHeadOneOr; + + struct { + NvU32 slotStart; + NvU32 slotEnd; + NvU32 PBN; + NvU32 Timeslice; + NvBool sendACT; // deprecated -Use NV0073_CTRL_CMD_DP_SEND_ACT + NvU32 singleHeadMSTPipeline; + NvBool bEnableAudioOverRightPanel; + } MST; + + struct { + NvBool bEnhancedFraming; + NvU32 tuSize; + NvU32 waterMark; + NvU32 actualPclkHz; // deprecated -Use MvidWarParams + NvU32 linkClkFreqHz; // deprecated -Use MvidWarParams + NvBool bEnableAudioOverRightPanel; + struct { + NvU32 activeCnt; + NvU32 activeFrac; + NvU32 activePolarity; + NvBool mvidWarEnabled; + struct { + NvU32 actualPclkHz; + NvU32 linkClkFreqHz; + } MvidWarParams; + } Legacy; + } SST; +} NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_SET_RATE_GOV + * + * This command enables rate governing for a MST. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * Head + * Specifies the head index for the stream. + * sorIndex + * Specifies the SOR index for the stream. + * flags + * Specifies Rate Governing, trigger type and wait on trigger and operation type. + * + * _FLAGS_OPERATION: whether this control call should program or check for status of previous operation. + * + * _FLAGS_STATUS: Out only. Caller should check the status for _FLAGS_OPERATION_CHECK_STATUS through + * this bit. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC: when this command has already been called + * + */ +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV (0x731363U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_RATE_GOV_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_PARAMS_MESSAGE_ID (0x63U) + +typedef struct NV0073_CTRL_CMD_DP_SET_RATE_GOV_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvU32 sorIndex; + NvU32 flags; +} NV0073_CTRL_CMD_DP_SET_RATE_GOV_PARAMS; + +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_ENABLE_RG 0:0 +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_ENABLE_RG_OFF (0x00000000U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_ENABLE_RG_ON (0x00000001U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_TRIGGER_MODE 1:1 +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_TRIGGER_MODE_LOADV (0x00000000U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_TRIGGER_MODE_IMMEDIATE (0x00000001U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_WAIT_TRIGGER 2:2 +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_WAIT_TRIGGER_OFF (0x00000000U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_WAIT_TRIGGER_ON (0x00000001U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_OPERATION 3:3 +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_OPERATION_PROGRAM (0x00000000U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_OPERATION_CHECK_STATUS (0x00000001U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_STATUS 31:31 +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_STATUS_FAIL (0x00000000U) +#define NV0073_CTRL_CMD_DP_SET_RATE_GOV_FLAGS_STATUS_PASS (0x00000001U) + +/* + * NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT + * + * This call is used by the displayport library. Once + * all of the platforms have ported, this call will be + * deprecated and made the default behavior. + * + * Disables automatic watermark programming + * Disables automatic DP IRQ handling (CP IRQ) + * Disables automatic retry on defers + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT (0x731365U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS_MESSAGE_ID (0x65U) + +typedef struct NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS { + NvU32 subDeviceInstance; +} NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_SET_ECF + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * sorIndex + * This parameter specifies the Index of sor for which ecf + * should be updated. + * ecf + * This parameter has the ECF bit mask. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_CMD_DP_SET_ECF (0x731366U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_ECF_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SET_ECF_PARAMS_MESSAGE_ID (0x66U) + +typedef struct NV0073_CTRL_CMD_DP_SET_ECF_PARAMS { + NvU32 subDeviceInstance; + NvU32 sorIndex; + NV_DECLARE_ALIGNED(NvU64 ecf, 8); + NvBool bForceClearEcf; + NvBool bAddStreamBack; +} NV0073_CTRL_CMD_DP_SET_ECF_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_SEND_ACT + * + * This command sends ACT. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * displayId + * Specifies the root port displayId for which the trigger has to be done. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC: when this command has already been called + * + */ +#define NV0073_CTRL_CMD_DP_SEND_ACT (0x731367U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS_MESSAGE_ID (0x67U) + +typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; +} NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS; + + + +/* + * NV0073_CTRL_CMD_DP_GET_CAPS + * + * This command returns the following info + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * sorIndex + * Specifies the SOR index. + * dpVersionsSupported + * Specified the DP versions supported by the GPU + * bIsMultistreamSupported + * Returns NV_TRUE if MST is supported by the GPU else NV_FALSE + * bIsSCEnabled + * Returns NV_TRUE if Stream cloning is supported by the GPU else NV_FALSE + * maxLinkRate + * Returns Maximum allowed orclk for DP mode of SOR + * 1 signifies 5.40(HBR2), 2 signifies 2.70(HBR), 3 signifies 1.62(RBR) + * bHasIncreasedWatermarkLimits + * Returns NV_TRUE if the GPU uses higher watermark limits, else NV_FALSE + * bIsPC2Disabled + * Returns NV_TRUE if VBIOS flag to disable PostCursor2 is set, else NV_FALSE + * bFECSupported + * Returns NV_TRUE if GPU supports FEC, else NV_FALSE + * bIsTrainPhyRepeater + * Returns NV_TRUE if LTTPR Link Training feature is set + * bOverrideLinkBw + * Returns NV_TRUE if DFP limits defined in DCB have to be honored, else NV_FALSE + * + * DSC caps - + * bDscSupported + * If GPU supports DSC or not + * + * encoderColorFormatMask + * Mask of all color formats for which DSC + * encoding is supported by GPU + * + * lineBufferSizeKB + * Size of line buffer. + * + * rateBufferSizeKB + * Size of rate buffer per slice. + * + * bitsPerPixelPrecision + * Bits per pixel precision for DSC e.g. 1/16, 1/8, 1/4, 1/2, 1bpp + * + * maxNumHztSlices + * Maximum number of horizontal slices supported by DSC encoder + * + * lineBufferBitDepth + * Bit depth used by the GPU to store the reconstructed pixels within + * the line buffer + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ + +#define NV0073_CTRL_CMD_DP_GET_CAPS (0x731369U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID (0x69U) + +typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS { + NvU32 subDeviceInstance; + NvU32 sorIndex; + NvU32 maxLinkRate; + NvU32 dpVersionsSupported; + NvBool bIsMultistreamSupported; + NvBool bIsSCEnabled; + NvBool bHasIncreasedWatermarkLimits; + NvBool bIsPC2Disabled; + NvBool isSingleHeadMSTSupported; + NvBool bFECSupported; + NvBool bIsTrainPhyRepeater; + NvBool bOverrideLinkBw; + + struct { + NvBool bDscSupported; + NvU32 encoderColorFormatMask; + NvU32 lineBufferSizeKB; + NvU32 rateBufferSizeKB; + NvU32 bitsPerPixelPrecision; + NvU32 maxNumHztSlices; + NvU32 lineBufferBitDepth; + } DSC; +} NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS; + +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2 0:0 +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2_NO (0x00000000U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2_YES (0x00000001U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4 1:1 +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_NO (0x00000000U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_YES (0x00000001U) + + + +#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE 2:0 +#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_NONE (0x00000000U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_1_62 (0x00000001U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_2_70 (0x00000002U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_5_40 (0x00000003U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_8_10 (0x00000004U) + +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_RGB (0x00000001U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_444 (0x00000002U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_422 (0x00000004U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_420 (0x00000008U) + +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_16 (0x00000001U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_8 (0x00000002U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_4 (0x00000003U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_2 (0x00000004U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1 (0x00000005U) + +#define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES (0x73136aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_MSA_PROPERTIES_SYNC_POLARITY_LOW (0U) +#define NV0073_CTRL_CMD_DP_MSA_PROPERTIES_SYNC_POLARITY_HIGH (1U) + +typedef struct NV0073_CTRL_DP_MSA_PROPERTIES_MASK { + NvU8 miscMask[2]; + NvBool bRasterTotalHorizontal; + NvBool bRasterTotalVertical; + NvBool bActiveStartHorizontal; + NvBool bActiveStartVertical; + NvBool bSurfaceTotalHorizontal; + NvBool bSurfaceTotalVertical; + NvBool bSyncWidthHorizontal; + NvBool bSyncPolarityHorizontal; + NvBool bSyncHeightVertical; + NvBool bSyncPolarityVertical; + NvBool bReservedEnable[3]; +} NV0073_CTRL_DP_MSA_PROPERTIES_MASK; + +typedef struct NV0073_CTRL_DP_MSA_PROPERTIES_VALUES { + NvU8 misc[2]; + NvU16 rasterTotalHorizontal; + NvU16 rasterTotalVertical; + NvU16 activeStartHorizontal; + NvU16 activeStartVertical; + NvU16 surfaceTotalHorizontal; + NvU16 surfaceTotalVertical; + NvU16 syncWidthHorizontal; + NvU16 syncPolarityHorizontal; + NvU16 syncHeightVertical; + NvU16 syncPolarityVertical; + NvU8 reserved[3]; +} NV0073_CTRL_DP_MSA_PROPERTIES_VALUES; + +#define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS_MESSAGE_ID (0x6AU) + +typedef struct NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bEnableMSA; + NvBool bStereoPhaseInverse; + NvBool bCacheMsaOverrideForNextModeset; + NV0073_CTRL_DP_MSA_PROPERTIES_MASK featureMask; + NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureValues; + NV_DECLARE_ALIGNED(struct NV0073_CTRL_DP_MSA_PROPERTIES_VALUES *pFeatureDebugValues, 8); +} NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT + * + * This command can be used to invoke a fake interrupt for the operation of DP1.2 branch device + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * interruptType + * This parameter specifies the type of fake interrupt to be invoked. Possible values are: + * 0 => IRQ + * 1 => HPDPlug + * 2 => HPDUnPlug + * displayId + * should be for DP only + * + */ + +#define NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT (0x73136bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_PARAMS_MESSAGE_ID (0x6BU) + +typedef struct NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 interruptType; +} NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_PARAMS; + +#define NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_IRQ (0x00000000U) +#define NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_PLUG (0x00000001U) +#define NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_UNPLUG (0x00000002U) + +/* + * NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG + * + * This command sets the MS displayId lit up by driver for further use of VBIOS + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * should be for DP only + * activeDevAddr + * Active MS panel address + * sorIndex + * SOR Index + * dpLink + * DP Sub Link Index + * hopCount + * Maximum hopcounts in MS address + * dpMsDevAddrState + * DP Multistream Device Address State. The values can be + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_TIMEOUT + * + */ +#define NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG (0x73136cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG_PARAMS_MESSAGE_ID (0x6CU) + +typedef struct NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 activeDevAddr; + NvU32 sorIndex; + NvU32 dpLink; + NvU32 hopCount; + NvU32 dpMsDevAddrState; +} NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG_PARAMS; + + + +/* +* NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT +* +* This command configures a new bit, NV_PDISP_SF_DP_LINKCTL_TRIGGER_SELECT +* to indicate which pipeline will handle the +* time slots allocation in single head MST mode +* +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. This parameter must specify a value between zero and the +* total number of subdevices within the parent device. This parameter +* should be set to zero for default behavior +* Head +* Specifies the head index for the stream +* sorIndex +* Specifies the SOR index for the stream +* streamIndex +* Stream Identifier +* +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_ARGUMENT +* NV_ERR_GENERIC: when this command has already been called +* +*/ +#define NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT (0x73136fU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT_PARAMS_MESSAGE_ID (0x6FU) + +typedef struct NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvU32 sorIndex; + NvU32 singleHeadMSTPipeline; +} NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT_PARAMS; + +/* +* NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM +* +* This call is used by the displayport library.& clients of RM +* Its main function is to configure single Head Multi stream mode + * this call configures internal RM datastructures to support required mode. +* +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. This parameter must specify a value between zero and the +* total number of subdevices within the parent device. This parameter +* should be set to zero for default behavior. +* +* displayIDs +* This parameter specifies array of DP displayIds to be configured which are driven out from a single head. +* +* numStreams +* This parameter specifies number of streams driven from a single head +* ex: for 2SST & 2MST its value is 2. +* +* mode +* This parameter specifies single head multi stream mode to be configured. +* +* bSetConfigure +* This parameter configures single head multistream mode +* if TRUE it sets SST or MST based on 'mode' parameter and updates internal driver data structures with the given information. +* if FALSE clears the configuration of single head multi stream mode. +* +* vbiosPrimaryDispIdIndex +* This parameter specifies vbios master displayID index in displayIDs input array. +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_ARGUMENT +* NV_ERR_NOT_SUPPORTED +* +*/ +#define NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM (0x73136eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SINGLE_HEAD_MAX_STREAMS (0x00000002U) +#define NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM_PARAMS_MESSAGE_ID (0x6EU) + +typedef struct NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayIDs[NV0073_CTRL_CMD_DP_SINGLE_HEAD_MAX_STREAMS]; + NvU32 numStreams; + NvU32 mode; + NvBool bSetConfig; + NvU8 vbiosPrimaryDispIdIndex; +} NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM_PARAMS; + +#define NV0073_CTRL_CMD_DP_SINGLE_HEAD_MULTI_STREAM_NONE (0x00000000U) +#define NV0073_CTRL_CMD_DP_SINGLE_HEAD_MULTI_STREAM_MODE_SST (0x00000001U) +#define NV0073_CTRL_CMD_DP_SINGLE_HEAD_MULTI_STREAM_MODE_MST (0x00000002U) + +/* +* NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL +* +* This command configures a new bit, NV_PDISP_SF_DP_LINKCTL_TRIGGER_ALL +* to indicate which if all the pipelines to take affect on ACT (sorFlushUpdates) +* in single head MST mode +* +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. This parameter must specify a value between zero and the +* total number of subdevices within the parent device. This parameter +* should be set to zero for default behavior +* Head +* Specifies the head index for the stream +* sorIndex +* Specifies the SOR index for the stream +* streamIndex +* Stream Identifier +* +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_ARGUMENT +* NV_ERR_GENERIC: when this command has already been called +* +*/ +#define NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL (0x731370U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL_PARAMS_MESSAGE_ID (0x70U) + +typedef struct NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvBool enable; +} NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL_PARAMS; + + + +/* +* NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA +* +* This command collects the DP AUX log from the RM aux buffer and +* sends it to the application. +* +* dpAuxBufferReadSize +* Specifies the number of logs to be read from the +* AUX buffer in RM +* dpNumMessagesRead +* Specifies the number of logs read from the AUX buffer +* dpAuxBuffer +* The local buffer to copy the specified number of logs +* from RM to user application +* +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_ARGUMENT +* NV_ERR_GENERIC: when this command has already been called +* +* +*DPAUXPACKET - This structure holds the log information +* auxPacket - carries the hex dump of the message transaction +* auxEvents - Contains the information as in what request and reply type where +* auxRequestTimeStamp - Request timestamp +* auxMessageReqSize - Request Message size +* auxMessageReplySize - Reply message size(how much information was actually send by receiver) +* auxOutPort - DP port number +* auxPortAddress - Address to which data was requested to be read or written +* auxReplyTimeStamp - Reply timestamp +* auxCount - Serial number to keep track of transactions +*/ + +/*Maximum dp messages size is 16 as per the protocol*/ +#define DP_MAX_MSG_SIZE 16U +#define MAX_LOGS_PER_POLL 50U + +/* Various kinds of DP Aux transactions */ +#define NV_DP_AUXLOGGER_REQUEST_TYPE 3:0 +#define NV_DP_AUXLOGGER_REQUEST_TYPE_NULL 0x00000000U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_I2CWR 0x00000001U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_I2CREQWSTAT 0x00000002U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_MOTWR 0x00000003U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_MOTREQWSTAT 0x00000004U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_AUXWR 0x00000005U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_I2CRD 0x00000006U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_MOTRD 0x00000007U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_AUXRD 0x00000008U +#define NV_DP_AUXLOGGER_REQUEST_TYPE_UNKNOWN 0x00000009U + +#define NV_DP_AUXLOGGER_REPLY_TYPE 7:4 +#define NV_DP_AUXLOGGER_REPLY_TYPE_NULL 0x00000000U +#define NV_DP_AUXLOGGER_REPLY_TYPE_SB_ACK 0x00000001U +#define NV_DP_AUXLOGGER_REPLY_TYPE_RETRY 0x00000002U +#define NV_DP_AUXLOGGER_REPLY_TYPE_TIMEOUT 0x00000003U +#define NV_DP_AUXLOGGER_REPLY_TYPE_DEFER 0x00000004U +#define NV_DP_AUXLOGGER_REPLY_TYPE_DEFER_TO 0x00000005U +#define NV_DP_AUXLOGGER_REPLY_TYPE_ACK 0x00000006U +#define NV_DP_AUXLOGGER_REPLY_TYPE_ERROR 0x00000007U +#define NV_DP_AUXLOGGER_REPLY_TYPE_UNKNOWN 0x00000008U + +#define NV_DP_AUXLOGGER_EVENT_TYPE 9:8 +#define NV_DP_AUXLOGGER_EVENT_TYPE_AUX 0x00000000U +#define NV_DP_AUXLOGGER_EVENT_TYPE_HOT_PLUG 0x00000001U +#define NV_DP_AUXLOGGER_EVENT_TYPE_HOT_UNPLUG 0x00000002U +#define NV_DP_AUXLOGGER_EVENT_TYPE_IRQ 0x00000003U + +#define NV_DP_AUXLOGGER_AUXCTL_CMD 15:12 +#define NV_DP_AUXLOGGER_AUXCTL_CMD_INIT 0x00000000U +#define NV_DP_AUXLOGGER_AUXCTL_CMD_I2CWR 0x00000000U +#define NV_DP_AUXLOGGER_AUXCTL_CMD_I2CRD 0x00000001U +#define NV_DP_AUXLOGGER_AUXCTL_CMD_I2CREQWSTAT 0x00000002U +#define NV_DP_AUXLOGGER_AUXCTL_CMD_MOTWR 0x00000004U +#define NV_DP_AUXLOGGER_AUXCTL_CMD_MOTRD 0x00000005U +#define NV_DP_AUXLOGGER_AUXCTL_CMD_MOTREQWSTAT 0x00000006U +#define NV_DP_AUXLOGGER_AUXCTL_CMD_AUXWR 0x00000008U +#define NV_DP_AUXLOGGER_AUXCTL_CMD_AUXRD 0x00000009U + + +typedef struct DPAUXPACKET { + NvU32 auxEvents; + NvU32 auxRequestTimeStamp; + NvU32 auxMessageReqSize; + NvU32 auxMessageReplySize; + NvU32 auxOutPort; + NvU32 auxPortAddress; + NvU32 auxReplyTimeStamp; + NvU32 auxCount; + NvU8 auxPacket[DP_MAX_MSG_SIZE]; +} DPAUXPACKET; +typedef struct DPAUXPACKET *PDPAUXPACKET; + +#define NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA (0x731373U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA_PARAMS_MESSAGE_ID (0x73U) + +typedef struct NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA_PARAMS { + //In + NvU32 subDeviceInstance; + NvU32 dpAuxBufferReadSize; + + //Out + NvU32 dpNumMessagesRead; + DPAUXPACKET dpAuxBuffer[MAX_LOGS_PER_POLL]; +} NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA_PARAMS; + + + + +/* NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES + * + * This setup link rate table for target display to enable indexed link rate + * and export valid link rates back to client. Client may pass empty table to + * reset previous setting. + * + * subDeviceInstance + * client will give a subdevice to get right pGpu/pDisp for it + * displayId + * DisplayId of the display for which the client targets + * linkRateTbl + * Link rates in 200KHz as native granularity from eDP 1.4 + * linkBwTbl + * Link rates in 270MHz and valid for client to apply to + * linkBwCount + * Total valid link rates + * + * Possible status values returned include: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES (0x731377U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES 8U + +#define NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS_MESSAGE_ID (0x77U) + +typedef struct NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS { + // In + NvU32 subDeviceInstance; + NvU32 displayId; + NvU16 linkRateTbl[NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES]; + + // Out + NvU8 linkBwTbl[NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES]; + NvU8 linkBwCount; +} NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS; + + +/* + * NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES + * + * This command is used to not depend on supervisor interrupts for setting the + * stereo msa params. We will not cache the values and can toggle stereo using + * this ctrl call on demand. Note that this control call will only change stereo + * settings and will leave other settings as is. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * should be for DP only + * bEnableMSA + * To enable or disable MSA + * bStereoPhaseInverse + * To enable or disable Stereo Phase Inverse value + * featureMask + * Enable/Disable mask of individual MSA property. + * featureValues + * MSA property value to write + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_TIMEOUT + * + */ +#define NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES (0x731378U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES_PARAMS_MESSAGE_ID (0x78U) + +typedef struct NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bEnableMSA; + NvBool bStereoPhaseInverse; + NV0073_CTRL_DP_MSA_PROPERTIES_MASK featureMask; + NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureValues; +} NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES_PARAMS; + + + +/* + * NV0073_CTRL_CMD_DP_CONFIGURE_FEC + * + * This command is used to enable/disable FEC on DP Mainlink. + * FEC is a prerequisite to DSC. This should be called only + * after LT completes (including PostLT LQA) while enabling. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * displayId + * Can only be 1 and must be DP. + * + * bEnableFec + * To enable or disable FEC + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV0073_CTRL_CMD_DP_CONFIGURE_FEC (0x73137aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIGURE_FEC_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_CONFIGURE_FEC_PARAMS_MESSAGE_ID (0x7AU) + +typedef struct NV0073_CTRL_CMD_DP_CONFIGURE_FEC_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bEnableFec; +} NV0073_CTRL_CMD_DP_CONFIGURE_FEC_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior + * cmd + * This parameter is an input to this command. + * Here are the current defined fields: + * NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_CMD_POWER + * Set to specify what operation to run. + * NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_CMD_POWER_UP + * Request to power up pad. + * NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_CMD_POWER_DOWN + * Request to power down the pad. + * linkBw + * This parameter is used to pass in the link bandwidth required to run the + * power up sequence. Refer enum DP_LINK_BANDWIDTH for valid values. + * laneCount + * This parameter is used to pass the lanecount. + * sorIndex + * This parameter is used to pass the SOR index. + * sublinkIndex + * This parameter is used to pass the sublink index. Please refer + * enum DFPLINKINDEX for valid values + * priPadLinkIndex + * This parameter is used to pass the padlink index for primary link. + * Please refer enum DFPPADLINK for valid index values for Link A~F. + * secPadLinkIndex + * This parameter is used to pass the padlink index for secondary link. + * For Single SST pass in NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PADLINK_INDEX_INVALID + * bEnableSpread + * This parameter is boolean value used to indicate if spread is to be enabled or disabled. + */ + +#define NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD (0x73137bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PARAMS_MESSAGE_ID (0x7BU) + +typedef struct NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PARAMS { + NvU32 subDeviceInstance; + NvU32 cmd; + NvU32 linkBw; + NvU32 laneCount; + NvU32 sorIndex; + NvU32 sublinkIndex; // sublink A/B + NvU32 priPadLinkIndex; // padlink A/B/C/D/E/F + NvU32 secPadLinkIndex; // padlink A/B/C/D/E/F for secondary link in DualSST case. + NvBool bEnableSpread; +} NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PARAMS; + +#define NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_CMD_POWER 0:0 +#define NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_CMD_POWER_UP (0x00000000U) +#define NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_CMD_POWER_DOWN (0x00000001U) + +#define NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PADLINK_INDEX_INVALID (0x000000FFU) + +/* + * NV0073_CTRL_CMD_DP_AUXCH_CTRL + * + * This command can be used to perform the I2C Bulk transfer over + * DP Aux channel. This is the display port specific implementation + * for sending bulk data over the DpAux channel, by splitting up the + * data into pieces and retrying for pieces that aren't ACK'd. + * + * subDeviceInstance [IN] + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId [IN] + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must a dfp display. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * addr [IN] + * This parameter is an input to this command. The addr parameter follows + * Section 2.4 in DisplayPort spec and the client should refer to the valid + * address in DisplayPort spec. Only the first 20 bits are valid. + * bWrite [IN] + * This parameter specifies whether the command is a I2C write (NV_TRUE) or + * a I2C read (NV_FALSE). + * data [IN/OUT] + * In the case of a read transaction, this parameter returns the data from + * transaction request. In the case of a write transaction, the client + * should write to this buffer for the data to send. + * size [IN/OUT] + * Specifies how many data bytes to read/write depending on the + * transaction type. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_DP_AUXCH_I2C_TRANSFER_CTRL (0x73137cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_MAX_DATA_SIZE 256U + +#define NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_CTRL_PARAMS_MESSAGE_ID (0x7CU) + +typedef struct NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 addr; + NvBool bWrite; + NvU8 data[NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_MAX_DATA_SIZE]; + NvU32 size; +} NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_CTRL_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_ENABLE_VRR + * + * The command is used to enable VRR. + * + * subDeviceInstance [IN] + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior + * displayId [IN] + * This parameter is an input to this command, specifies the ID of the display + * for client targeted to. + * The display ID must a DP display. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * cmd [IN] + * This parameter is an input to this command. + * + * _STAGE: specifies the stage id to execute in the VRR enablement sequence. + * _MONITOR_ENABLE_BEGIN: Send command to the monitor to start monitor + * enablement procedure. + * _MONITOR_ENABLE_CHALLENGE: Send challenge to the monitor + * _MONITOR_ENABLE_CHECK: Read digest from the monitor, and verify + * if the result is valid. + * _DRIVER_ENABLE_BEGIN: Send command to the monitor to start driver + * enablement procedure. + * _DRIVER_ENABLE_CHALLENGE: Read challenge from the monitor and write back + * corresponding digest. + * _DRIVER_ENABLE_CHECK: Check if monitor enablement worked. + * _RESET_MONITOR: Set the FW state m/c to a known state. + * _INIT_PUBLIC_INFO: Send command to the monitor to prepare public info. + * _GET_PUBLIC_INFO: Read public info from the monitor. + * _STATUS_CHECK: Check if monitor is ready for next command. + * result [OUT] + * This is an output parameter to reflect the result of the operation. + */ +#define NV0073_CTRL_CMD_DP_ENABLE_VRR (0x73137dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS_MESSAGE_ID (0x7DU) + +typedef struct NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 cmd; + NvU32 result; +} NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS; + +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE 3:0 +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_MONITOR_ENABLE_BEGIN (0x00000000U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_MONITOR_ENABLE_CHALLENGE (0x00000001U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_MONITOR_ENABLE_CHECK (0x00000002U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_DRIVER_ENABLE_BEGIN (0x00000003U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_DRIVER_ENABLE_CHALLENGE (0x00000004U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_DRIVER_ENABLE_CHECK (0x00000005U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_RESET_MONITOR (0x00000006U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_INIT_PUBLIC_INFO (0x00000007U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_GET_PUBLIC_INFO (0x00000008U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_STATUS_CHECK (0x00000009U) + +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_OK (0x00000000U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_PENDING (0x80000001U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_READ_ERROR (0x80000002U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_WRITE_ERROR (0x80000003U) +#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_DEVICE_ERROR (0x80000004U) + +/* + * NV0073_CTRL_CMD_DP_GET_GENERIC_INFOFRAME + * + * This command is used to capture the display output packets for DP protocol. + * Common supported packets are Dynamic Range and mastering infoframe SDP for HDR, + * VSC SDP for colorimetry and pixel encoding info. + * + * displayID (in) + * This parameter specifies the displayID for the display resource to configure. + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the NV04_DISPLAY_COMMON + * parent device to which the operation should be directed. + * infoframeIndex (in) + * HW provides support to program 2 generic infoframes per frame for DP. + * This parameter indicates which infoframe packet is to be captured. + * Possible flags are as follows: + * NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_CAPTURE_MODE + * This flag indicates the INFOFRAME that needs to be read. + * Set to _INFOFRAME0 if RM should read GENERIC_INFOFRAME + * Set to _INFOFRAME1 if RM should read GENERIC_INFOFRAME1 + * packet (out) + * pPacket points to the memory for reading the infoframe packet. + * bTransmitControl (out) + * This gives the transmit mode of infoframes. + * If set, means infoframe will be sent as soon as possible and then on + * every frame during vblank. + * If cleared, means the infoframe will be sent once as soon as possible. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_DP_GET_GENERIC_INFOFRAME (0x73137eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_GENERIC_INFOFRAME_MAX_PACKET_SIZE 36U + +#define NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_PARAMS_MESSAGE_ID (0x7EU) + +typedef struct NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 infoframeIndex; + NvU8 packet[NV0073_CTRL_DP_GENERIC_INFOFRAME_MAX_PACKET_SIZE]; + NvBool bTransmitControl; +} NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_PARAMS; + + +#define NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_CAPTURE_MODE 0:0 +#define NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_CAPTURE_MODE_INFOFRAME0 (0x0000000U) +#define NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_CAPTURE_MODE_INFOFRAME1 (0x0000001U) + + +/* + * NV0073_CTRL_CMD_DP_GET_MSA_ATTRIBUTES + * + * This command is used to capture the various data attributes sent in the MSA for DP protocol. + * Refer table 2-94 'MSA Data Fields' in DP1.4a spec document for MSA data field description. + * + * displayID (in) + * This parameter specifies the displayID for the display resource to configure. + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the NV04_DISPLAY_COMMON + * parent device to which the operation should be directed. + * mvid, nvid (out) + * Video timestamp used by DP sink for regenerating pixel clock. + * misc0, misc1 (out) + * Miscellaneous MSA attributes. + * hTotal, vTotal (out) + * Htotal measured in pixel count and vtotal measured in line count. + * hActiveStart, vActiveStart (out) + * Active start measured from start of leading edge of the sync pulse. + * hActiveWidth, vActiveWidth (out) + * Active video width and height. + * hSyncWidth, vSyncWidth (out) + * Width of sync pulse. + * hSyncPolarity, vSyncPolarity (out) + * Polarity of sync pulse. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_DP_GET_MSA_ATTRIBUTES (0x73137fU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_MSA_ATTRIBUTES_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_MSA_MAX_DATA_SIZE 7U + +#define NV0073_CTRL_DP_GET_MSA_ATTRIBUTES_PARAMS_MESSAGE_ID (0x7FU) + +typedef struct NV0073_CTRL_DP_GET_MSA_ATTRIBUTES_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 mvid; + NvU32 nvid; + NvU8 misc0; + NvU8 misc1; + NvU16 hTotal; + NvU16 vTotal; + NvU16 hActiveStart; + NvU16 vActiveStart; + NvU16 hActiveWidth; + NvU16 vActiveWidth; + NvU16 hSyncWidth; + NvU16 vSyncWidth; + NvBool hSyncPolarity; + NvBool vSyncPolarity; +} NV0073_CTRL_DP_GET_MSA_ATTRIBUTES_PARAMS; + +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_MVID 23:0 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_NVID 23:0 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_MISC0 7:0 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_MISC1 15:8 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_HTOTAL 15:0 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_VTOTAL 31:16 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_HACTIVE_START 15:0 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_VACTIVE_START 31:16 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_HACTIVE_WIDTH 15:0 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_VACTIVE_WIDTH 31:16 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_HSYNC_WIDTH 14:0 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_HSYNC_POLARITY 15:15 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_VSYNC_WIDTH 30:16 +#define NV0073_CTRL_DP_MSA_ATTRIBUTES_VSYNC_POLARITY 31:31 + +/* + * NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL + * + * This command is used to query OD capability and status as well as + * control OD functionality of eDP LCD panels. + * + * subDeviceInstance [in] + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId [in] + * This parameter specifies the ID of the DP display which owns + * the Main Link to be adjusted. The display ID must a DP display + * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. + * If more than one displayId bit is set or the displayId is not a DP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * cmd [in] + * This parameter is an input to this command. The cmd parameter tells + * whether we have to get the value of a specific field or set the + * value in case of a writeable field. + * control [in] + * This parameter is input by the user. It is used by the user to decide the control + * value to be written to change the Sink OD mode. The command to write is + * the NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET command. + * bOdCapable [out] + * This parameter reflects the OD capability of the Sink which can be + * fetched by using the NV0073_CTRL_CMD_DP_AUXCH_OD_CAPABLE_QUERY command. + * bOdControlCapable [out] + * This parameter reflects the OD control capability of the Sink which can be + * fetched by using the NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_CAPABLE_QUERY command. + * bOdStatus [out] + * This parameter reflects the Sink OD status which can be + * fetched by using the NV0073_CTRL_CMD_DP_AUXCH_OD_STATUS_QUERY command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL (0x731380U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS_MESSAGE_ID (0x80U) + +typedef struct NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU8 control; + NvU8 cmd; + NvBool bOdCapable; + NvBool bOdControlCapable; + NvBool bOdStatus; +} NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS; + +/* valid commands */ +#define NV0073_CTRL_CMD_DP_AUXCHQUERY_OD_CAPABLE 0x00000000 +#define NV0073_CTRL_CMD_DP_AUXCHQUERY_OD_CTL_CAPABLE 0x00000001 +#define NV0073_CTRL_CMD_DP_AUXCHQUERY_OD_STATUS 0x00000002 +#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET 0x00000003 + +/* valid state values */ +#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET_AUTONOMOUS 0x00000000 +#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET_DISABLE_OD 0x00000002 +#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET_ENABLE_OD 0x00000003 + +/* + * NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES + * + * This command returns the following info + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * should be for DP only + * bEnableMSA + * To enable or disable MSA + * bStereoPhaseInverse + * To enable or disable Stereo Phase Inverse value + * bCacheMsaOverrideForNextModeset + * Cache the values and don't apply them until next modeset + * featureMask + * Enable/Disable mask of individual MSA property + * featureValues + * MSA property value to write + * bDebugValues + * To inform whether actual MSA values need to be returned + * pFeatureDebugValues + * It will actual MSA property value being written on HW. + * If its NULL then no error but return nothing + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_TIMEOUT + * + */ +#define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2 (0x731381U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bEnableMSA; + NvBool bStereoPhaseInverse; + NvBool bCacheMsaOverrideForNextModeset; + NV0073_CTRL_DP_MSA_PROPERTIES_MASK featureMask; + NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureValues; + NvBool bDebugValues; + NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureDebugValues; +} NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS; +/* _ctrl0073dp_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073dpu.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073dpu.h new file mode 100644 index 0000000..1ac3e6f --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073dpu.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073dpu.finn +// + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h new file mode 100644 index 0000000..a2423a8 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073event.finn +// + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h new file mode 100644 index 0000000..2b4965d --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073internal.finn +// + +#include "ctrl/ctrl0073/ctrl0073base.h" +#include "ctrl/ctrl0073/ctrl0073system.h" + +#define NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE (0x730401U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS_MESSAGE_ID" */ + + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS { + NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS params; +} NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS; + + +/* ctrl0073internal_h */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h new file mode 100644 index 0000000..7ac6f6e --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073psr.finn +// + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h new file mode 100644 index 0000000..74ace22 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h @@ -0,0 +1,1909 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073specific.finn +// + +#include "ctrl/ctrl0073/ctrl0073base.h" + +#include "ctrl/ctrlxxxx.h" +/* NV04_DISPLAY_COMMON display-specific control commands and parameters */ + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_TYPE + * + * This command can be used to determine the associated display type for + * the specified displayId. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the display + * type is to be returned. Only one display may be indicated in this + * parameter. + * displayType + * This parameter returns the display type associated with the specified + * displayId parameter. Valid displayType values are: + * NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_CRT + * NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_DFP + * NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_TV + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_TYPE (0x730240U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_TYPE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_GET_TYPE_PARAMS_MESSAGE_ID (0x40U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_TYPE_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 displayType; +} NV0073_CTRL_SPECIFIC_GET_TYPE_PARAMS; + +/* valid display types */ +#define NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_UNKNOWN (0x00000000U) +#define NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_CRT (0x00000001U) +#define NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_DFP (0x00000002U) +#define NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_TV (0x00000003U) + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_EDID_V2 + * + * This command can be used to request the EDID for the specified displayId. + * + * [in] subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the total + * number of subdevices within the parent device. This parameter should + * be set to zero for default behavior. + * [in] displayId + * This parameter specifies the display to read the EDID. The display ID + * must specify a display with a positive connect state as determined + * with the NV0073_CTRL_CMD_SYSTEM_GET_CONNECT_STATE command. Only one + * display may be indicated in this parameter. If a more than one + * display Id is used, the RM will return NV_ERR_INVALID_ARGUMENT. + * [out] bufferSize + * This parameter returns the number of bytes copied into edidBuffer after + * performing the requested EDID operations. + * [out] edidBuffer + * The array of EDIDs that RM will fill after the requested operations. If + * the size of the array is not large enough to hold the number of bytes to + * be copied, NV_ERR_INVALID_ARGUMENT will be returned. + * [in] flags + * This parameter defines the specific operations that will be performed + * in reading the EDID. + * Here are the current defined fields: + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_COPY_CACHE + * A client uses this field to indicate whether to return the cached + * copy of the EDID or to use DDC to read the EDID from the display. + * Possible values are: + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_COPY_CACHE_NO + * The RM will use DDC to grab the EDID. + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_COPY_CACHE_YES + * The RM will copy the last EDID found into the clients + * buffer. No DDC will be performed. + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_READ_MODE + * A client uses this field to indicate whether to read from + * the HW and return the EDID w/o any patching + * Possible values are: + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_READ_MODE_COOKED + * Use the _COPY_CACHE policy + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_READ_MODE_RAW + * Perform the read and return an unadulterated EDID. + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE + * A client uses this field to indicate whether to read EDID + * from SBIOS using ACPI sub function for display dynamic switching + * feature. This flag should only be set on internal display with + * dynamic switching feature enabled. + * Possible values are: + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE_ACPI + * RM reads the EDID from SBIOS and returns the raw EDID provided + * by SBIOS. + * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE_DEFAULT + * EDID is read based on rest of the 'flags' that are passed to + * this function. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_EDID_V2 (0x730245U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_GET_EDID_MAX_EDID_BYTES 2048U + +#define NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS_MESSAGE_ID (0x45U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 bufferSize; + NvU32 flags; + NvU8 edidBuffer[NV0073_CTRL_SPECIFIC_GET_EDID_MAX_EDID_BYTES]; +} NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS; + +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_COPY_CACHE 0:0 +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_COPY_CACHE_NO 0x00000000U +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_COPY_CACHE_YES 0x00000001U + +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_READ_MODE 1:1 +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_READ_MODE_COOKED 0x00000000U +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_READ_MODE_RAW 0x00000001U + +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE 3:2 +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE_DEFAULT 0x00000000U +#define NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE_ACPI 0x00000001U + +/* + * NV0073_CTRL_CMD_SPECIFIC_SET_EDID_V2 + * + * This command can be used to set or remove a complete EDID for the + * specified displayId. Once the EDID is set, any requests + * to read the EDID or use DDC detection will always use a cached copy of + * the EDID. That is, the EDID becomes static until disabled by calling + * this same function with edidBuffer. Note, that DDC based + * detection will always pass for any displayId that has set an EDID. Also, + * this path will not store any value across reboots. If an EDID needs to + * remain set after a reboot, RM clients must call this function again. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the total + * number of subdevices within the parent device. This parameter should + * be set to zero for default behavior. + * displayId + * This parameter specifies the display to store or the EDID. Only one + * display may be indicated in this parameter. If more than one displayId + * is used, the RM will return NV_ERR_INVALID_ARGUMENT. + * If the displayId does not use DDC and hence would not have an EDID, + * then the RM could also return NV_ERR_INVALID_ARGUMENT. + * bufferSize + * This parameter specifies the size of the EDID buffer pointed to by + * pEdidBuffer. If the EDID write contains more bytes than bufferSize, + * the RM will extend the bufferSize of the EDID inside the RM to match. + * Note a bufferSize of 0 would mean no bytes will be copied, but set the + * current cached EDID as static. + * edidBuffer + * This parameter specifies the EDID buffer that the RM will copy into + * the RM buffer. If the EDID buffer is empty, the RM will remove any + * previous set EDID and allow further detection and EDID reads to use DDC. + * The RM will not check to see if the EDID is valid here or not. + * The client should validate the EDID if needed before calling this function. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + */ + +#define NV0073_CTRL_CMD_SPECIFIC_SET_EDID_V2 (0x730246U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_EDID_V2_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_EDID_V2_PARAMS_MESSAGE_ID (0x46U) + +typedef struct NV0073_CTRL_SPECIFIC_SET_EDID_V2_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 bufferSize; + NvU8 edidBuffer[NV0073_CTRL_SPECIFIC_GET_EDID_MAX_EDID_BYTES]; +} NV0073_CTRL_SPECIFIC_SET_EDID_V2_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE + * + * This Control Cmd is for providing the Faking device(s) support from RM. + * This command serves as the entry point for all interaction of RM with + * user mode component of the any internal [test] tool. The Faking framework + * in RM will be activated only after the usermode app sends in a proper ENABLE + * cmd first. Any attempt to issue other cmds while the faking code has not + * been enabled will result in RM err _INVALID_DATA. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the total + * number of subdevices within the parent device. This parameter should + * be set to zero for default behavior. + * cmd + * This field will carry the command to be executed by the framework. + * This includes Enabling/Disabling the test framework and faking devices + * like CRT/DVI/TV. + * data + * This field is to carry the data required for executing the cmd. + * Except for Enable and Disable, the other faking device commands will + * require the device mask of the device to be faked/removed. + * tvType + * This field specifies a specific TV type while faking a TV. + * Possible values are: + * NV0073_FAKE_DEVICE_TV_NONE + * NV0073_FAKE_DEVICE_TV_SVIDEO + * NV0073_FAKE_DEVICE_TV_COMPOSITE + * NV0073_FAKE_DEVICE_TV_COMPONENT + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_DATA + * + */ + +#define NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE (0x730243U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE_PARAMS_MESSAGE_ID" */ + +/* valid fake device TV connector types */ +#define NV0073_FAKE_DEVICE_TV_NONE (0U) +#define NV0073_FAKE_DEVICE_TV_SVIDEO (1U) +#define NV0073_FAKE_DEVICE_TV_COMPOSITE (2U) +#define NV0073_FAKE_DEVICE_TV_COMPONENT (3U) + +#define NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE_PARAMS_MESSAGE_ID (0x43U) + +typedef struct NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE_PARAMS { + NvU32 subDeviceInstance; + NvU32 cmd; + NvU32 data; + NvU32 tvType; +} NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE_PARAMS; + +/* Faking Support commands */ +/* some random value to enable/disable test code */ +#define NV0073_FAKE_DEVICE_SUPPORT_ENABLE 0x11faU +#define NV0073_FAKE_DEVICE_SUPPORT_DISABLE 0x99ceU +#define NV0073_FAKE_DEVICE_SUPPORT_ATTACH_DEVICES 0x100U +#define NV0073_FAKE_DEVICE_SUPPORT_REMOVE_DEVICES 0x101U + + + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID + * + * This command returns the I2C portID for the specified display device. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the display for which information is to be + * returned. Only one display may be indicated in this parameter. + * If more than one displayId is used a failing status of + * NV_ERR_INVALID_ARGUMENT will be returned. + * commPortId + * This parameter returns the I2C communication port ID of the + * display device indicated by the displayId parameter. + * ddcPortId + * This parameter returns the I2C DDC port ID of the display device + * indicated by the displayId parameter. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID (0x730211U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 commPortId; + NvU32 ddcPortId; +} NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS; + +#define NV0073_CTRL_SPECIFIC_I2C_PORT_NONE (0x0U) + + + + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_CONNECTOR_DATA + * + * This command can be used to get display connector data. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the display for which information is to be + * returned. Only one display may be indicated in this parameter. + * If more than one displayId is used a failing status of + * NV_ERR_INVALID_ARGUMENT will be returned. + * DDCPartners + * This parameter specifies an NV0073_DISPLAY_MASK value describing + * the set of displays that share the same DDC line as displayId. This + * parameter will always be returned even if we also return the + * NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_FLAGS_PRESENT_NO flag. + * flags + * This parameter specifies optional flags to be used while retrieving + * the connector data for a given displayId. + * Legal values for this parameter include: + * NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_FLAGS_PRESENT + * This flag describes whether the connector data is present + * inside the firmware. + * count + * This parameter returns the number of connectors associated with + * the displayId argument. This value indicates the number of +* valid entries returned in the data parameter. + * data + * This parameter returns an array of structures containing the connector + * data associated with each connector for the given displayId argument. + * The count field specifies how many entries in this array are returned. + * Each entry in the array contains the following members: + * index + * This value is the index associated with the given connector. If + * two displayIds share the same index, then they share the same + * connector. + * type + * This value defines the type of connector associated with the + * displayId argument. + * location + * This value provides a possible means to determine the relative + * location of the connector in association to other connectors. + * For desktop boards, a value of zero defines the south most + * connector (the connector closest to the bus slot into which + * the board is inserted). + * platform + * This value defines the type of system with which to associate the + * location of each connector. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * + */ + +#define NV0073_CTRL_CMD_SPECIFIC_GET_CONNECTOR_DATA (0x730250U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS_MESSAGE_ID" */ + +/* maximum number of connectors */ +#define NV0073_CTRL_MAX_CONNECTORS 4U + +#define NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS_MESSAGE_ID (0x50U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 flags; + NvU32 DDCPartners; + NvU32 count; + struct { + NvU32 index; + NvU32 type; + NvU32 location; + } data[NV0073_CTRL_MAX_CONNECTORS]; + NvU32 platform; +} NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS; + +/* defines for the flags field */ +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_FLAGS_PRESENT 0:0 +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_FLAGS_PRESENT_NO 0x00000000U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_FLAGS_PRESENT_YES 0x00000001U + +/* defines for the data[].type field */ +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_VGA_15_PIN 0x00000000U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_TV_COMPOSITE 0x00000010U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_TV_SVIDEO 0x00000011U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_TV_HDTV_COMPONENT 0x00000013U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_TV_SCART 0x00000014U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_TV_COMPOSITE_SCART_OVER_EIAJ4120_BLUE 0x00000016U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_TV_HDTV_EIAJ4120 0x00000017U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_PC_POD_HDTV_YPRPB 0x00000018U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_PC_POD_SVIDEO 0x00000019U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_PC_POD_COMPOSITE 0x0000001AU +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DVI_I_TV_SVIDEO 0x00000020U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DVI_I_TV_COMPOSITE 0x00000021U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DVI_I 0x00000030U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DVI_D 0x00000031U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_ADC 0x00000032U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_LFH_DVI_I_1 0x00000038U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_LFH_DVI_I_2 0x00000039U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_SPWG 0x00000040U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_OEM 0x00000041U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DP_EXT 0x00000046U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DP_INT 0x00000047U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DP_MINI_EXT 0x00000048U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DP_SERIALIZER 0x00000049U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_HDMI_A 0x00000061U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_HDMI_C_MINI 0x00000063U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_LFH_DP_1 0x00000064U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_LFH_DP_2 0x00000065U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_VIRTUAL_WFD 0x00000070U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_USB_C 0x00000071U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DSI 0x00000072U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_STEREO_3PIN_DIN 0x00000073U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_UNKNOWN 0xFFFFFFFFU + +/* defines for the platform field */ +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_DEFAULT_ADD_IN_CARD 0x00000000U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_TWO_PLATE_ADD_IN_CARD 0x00000001U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_CONFIGURABLE 0x00000002U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_DESKTOP_FULL_DP 0x00000007U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_MOBILE_ADD_IN_CARD 0x00000008U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_MXM 0x00000009U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_MOBILE_BACK 0x00000010U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_MOBILE_BACK_LEFT 0x00000011U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_MOBILE_BACK_DOCK 0x00000018U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_CRUSH_DEFAULT 0x00000020U +#define NV0073_CTRL_SPECIFIC_CONNECTOR_PLATFORM_UNKNOWN 0xFFFFFFFFU + + + +/* + * NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_ENABLE + * + * This command is used to signal the resource manager that the upcoming mode + * shall be hdmi vs dvi. This is required since the resource manager + * does not read the display edid. The resource manager shall enable hdmi + * components such as turning on the audio engine for instance. This should + * be called prior to every modeset in which the displayId is capable of hdmi. + * displayId + * This parameter specifies the displayId of HDMI resource to configure. + * This comes as input to this command. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which operation should be directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * enable + * This field specifies the legal values: + * NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_TRUE + * NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_FALSE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_ENABLE (0x730273U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS_MESSAGE_ID (0x73U) + +typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS { + NvU8 subDeviceInstance; + NvU32 displayId; + NvU8 enable; +} NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS; + +#define NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_FALSE (0x00000000U) +#define NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_TRUE (0x00000001U) + +/* + * NV0073_CTRL_CMD_SPECIFIC_CTRL_HDMI + * + * This command can be used to enable HDMI communication on the associated GPU. + * This should be called prior to every modeset in which the displayId is capable of HDMI. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which operation should be directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * displayId + * This parameter specifies the displayId of HDMI resource to configure. + * This comes as input to this command. + * enable + * This field specifies the legal values: + * NV0073_CTRL_SPECIFIC_CTRL_HDMI_DISABLE + * NV0073_CTRL_SPECIFIC_CTRL_HDMI_ENABLE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_CTRL_HDMI (0x730274U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_CTRL_HDMI_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_CTRL_HDMI_PARAMS_MESSAGE_ID (0x74U) + +typedef struct NV0073_CTRL_SPECIFIC_CTRL_HDMI_PARAMS { + NvU8 subDeviceInstance; + NvU32 displayId; + NvBool bEnable; +} NV0073_CTRL_SPECIFIC_CTRL_HDMI_PARAMS; + +#define NV0073_CTRL_SPECIFIC_CTRL_HDMI_DISABLE (0x00000000U) +#define NV0073_CTRL_SPECIFIC_CTRL_HDMI_ENABLE (0x00000001U) + + + +/* + * NV0073_CTRL_SPECIFIC_ACPI_ID_MAPPING + * + * This structure defines the mapping between the ACPI ID and the corresponding + * display ID of a display device + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * acpiId + * The ACPI ID of the display device + * displayId + * The corresponding display ID + * dodIndex + * The corresponding DOD index + */ +typedef struct NV0073_CTRL_SPECIFIC_ACPI_ID_MAPPING { + NvU32 subDeviceInstance; + NvU32 acpiId; + NvU32 displayId; + NvU32 dodIndex; +} NV0073_CTRL_SPECIFIC_ACPI_ID_MAPPING; + +/* + * NV0073_CTRL_CMD_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT + * + * This call will return the Display Port Attachment value + * per displayID as defined by Nvidia that is directly + * associated with the ACPI 3.0 _DOD entry's Display Port + * Attachment field. This should help clients map the + * _DOD ACPI ID to each displayID. Note, that some systems + * do not have a standard in place for this field. On those + * systems, the RM will return NV_ERR_NOT_SUPPORTED. + * + * Note that this "Display Port" attachment field has nothing + * to do with DisplayPort/DP. It's an unfortunate name inside + * the ACPI 3.0 spec that coincides with the name of DisplayPort. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_NOT_SUPPORTED + * +*/ + +#define NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS_MESSAGE_ID (0x85U) + +typedef struct NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 dispPortAttachment; +} NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS; + + +#define NV0073_CTRL_CMD_SPECIFIC_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT (0x730285U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS_MESSAGE_ID" */ + +// defines for dispPortAttachment +#define NV0073_DISPLAY_PORT_ATTACHMENT_ANALOG (0x00000000U) +#define NV0073_DISPLAY_PORT_ATTACHMENT_LVDS (0x00000001U) +#define NV0073_DISPLAY_PORT_ATTACHMENT_DP_A (0x00000002U) +#define NV0073_DISPLAY_PORT_ATTACHMENT_DP_B (0x00000003U) +#define NV0073_DISPLAY_PORT_ATTACHMENT_DP_C (0x00000004U) +#define NV0073_DISPLAY_PORT_ATTACHMENT_DP_D (0x00000005U) +#define NV0073_DISPLAY_PORT_ATTACHMENT_UNKNOWN (0xFFFFFFFFU) + +/* + * NV0073_CTRL_CMD_SPECIFIC_SET_ACPI_ID_MAPPING + * + * This call will update the RM data structure which holds the + * ACPI ID to display ID mapping of the display devices + * + * The input parameter is an array of structures of type + * NV0073_CTRL_SPECIFIC_ACPI_ID_MAPPING + * + * If some of the array elements remain unused, the acpiId field of the + * structure must be set to 0x0000 + * + * The size of the array is given by + * NV0073_CTRL_SPECIFIC_MAX_ACPI_DEVICES (defined below) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * +*/ +#define NV0073_CTRL_CMD_SPECIFIC_SET_ACPI_ID_MAPPING (0x730284U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_MAX_ACPI_DEVICES 16U + +#define NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS_MESSAGE_ID (0x84U) + +typedef struct NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS { + NV0073_CTRL_SPECIFIC_ACPI_ID_MAPPING mapTable[NV0073_CTRL_SPECIFIC_MAX_ACPI_DEVICES]; +} NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_ALL_HEAD_MASK + * + * This call will return all head mask. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * headMask + * headMask is the mask of all heads that are usable. For example, if + * head 0 and head 2 are present, headMask would be NVBIT(0)|NVBIT(2). This + * parameter returns to the client. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_ALL_HEAD_MASK (0x730287U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS_MESSAGE_ID (0x87U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS { + NvU32 subDeviceInstance; + NvU32 headMask; +} NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_SET_OD_PACKET + * + * This command is used to program the display output packets. + * Currently it supports DP and HDMI. + * Common supported packets are AVI infoframes, Audio Infoframes, Gamma + * Metadata, Vendor Specific infoframes and General Control Packets (GCP). + * + GCP AVMute Enable should be performed before the start of the modeset. + * + GCP AVMute Disable should be performed after the end of the modeset. + * GCP AVMute should contain HDR + 7 bytes. + * + AVI infoframes should occur after the modeset but before a GCP AVMute + * Disable. AVI infoframe should contain HDR + 14 bytes + * + Audio infoframes should occur after the modeset but before a GCP AVMute + * Enable. + * Audio infoframe should contain HDR + 11 bytes. + * + Gamma Metadata packets should contain HDR + 28 bytes. + * + Vendor Specific packets are variable length. + * By HDMI 1.4 June 5 2009 spec, payload can be 5 bytes, 6 bytes, 7 bytes or + * 16 bytes, depending on the packets spec. + * Unused data bytes should be zero-ed out. + * + * displayID + * This parameter specifies the displayID for the display resource to + * configure. + * This comes as input to this command. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * transmitControl + * This parameter controls how the packet is to be sent by setting the + * control bits. + * Possible flags are as follows: + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE + * Set to _ENABLE to start sending the packet at next frame, set to + * _DISABLE to stop sending. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME + * Set to _ENABLE to send the packet at other frame, set to _DISABLE to + * send at every frame. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME + * Set to _ENABLE to send once next frame, set to _DISABLE to send at + * every frame. + * Note: A setting to set both _OTHER_FRAME and _SINGLE_FRAME is invalid + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK + * Set to _ENABLE to send the packet once on next HBLANK, set to + * _DISABLE to send on VBLANK. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE + * Set to _ENABLE to send the info frame packet as soon as possible. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT + * Set to _SW_CONTROLLED to set HDMI_Video_Format field and 3D_Structure field + * from NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB4 and PB5, if it is set to _HW_CONTROLLED + * then HW will get them based on the state of the setHdmiCtrl method. + * Btw this applies only for stereo ovverides. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY + * Set to TRUE to send Vendor specific info frame used for 3D stereo LR sync. + * Set PACKET_TYPE=pktType_VendorSpecInfoFrame along with this flag. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING + * Set to TRUE to send Vendor specific info frame used for Self Refresh panels + * Set PACKET_TYPE=pktType_VendorSpecInfoFrame along with this flag. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE + * HW provides support to program 2 generic infoframes per frame for DP with GP10X+. + * This flag indicates the INFOFRAME that needs to be programmed. + * Set to _INFOFRAME0 if RM should program GENERIC_INFOFRAME + * Set to _INFOFRAME1 if RM should program GENERIC_INFOFRAME1 + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE + * This option is reserved for backward compatibility with + * NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_PACKET and + * NV0073_CTRL_CMD_DP_SET_PACKET. + * It is temporal and will be deprecated soon. + * packetSize + * packet size of packets in pPacket to send, including header and payload. + * targetHead + * Specifies the target head number for which SDP needs to be updated. + * bUsePsrHeadforSdp + * Indicates use targetHead field for setting SDP or infoframe packet instead + * of deriving the active head from displayID. + * pPacket + * pPacket points to the packets to send. + * For HDMI 1.1, the maximum allowed bytes is 31. + * The packet array includes the 3 bytes of header + data depending on + * the type of packet. For an infoframe, the header bytes refer to type, + * version and length respectively. This comes as input to this command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_SET_OD_PACKET (0x730288U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SET_OD_MAX_PACKET_SIZE 36U + +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS_MESSAGE_ID (0x88U) + +typedef struct NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 transmitControl; + NvU32 packetSize; + NvU32 targetHead; + NvBool bUsePsrHeadforSdp; + NvU8 aPacket[NV0073_CTRL_SET_OD_MAX_PACKET_SIZE]; +} NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS; + +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE 0:0 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE_YES (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME 1:1 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME_DISABLE (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME_ENABLE (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME 2:2 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME_DISABLE (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME_ENABLE (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK 3:3 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK_DISABLE (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK_ENABLE (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE 4:4 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE_DISABLE (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE_ENABLE (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT 5:5 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT_SW_CONTROLLED (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT_HW_CONTROLLED (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY 6:6 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY_FALSE (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY_TRUE (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING 7:7 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_FALSE (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_TRUE (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE 9:8 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE_INFOFRAME0 (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE_INFOFRAME1 (0x0000001U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE 31:31 +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_NO (0x0000000U) +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_YES (0x0000001U) + + +/* + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_PARAMS + * + * This command is used to enable/disable sending of display output packets. + * Currently it supports HDMI only. + * Unused data bytes should be zero-ed out. + * + * displayID + * This parameter specifies the displayID for the display output resource to + * configure. + * This comes as input to this command. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * type + * The client shall specify the type of display output packet. For HDMI, set + * this according to HDMI specification 1.4. + * This comes as input to this command. + * transmitControl + * This parameter controls how the packet is to be sent by setting the control + * bits. + * Possible flags are as follows: + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ENABLE + * Set to _ENABLE to start sending the packet at next frame, set to + * _DISABLE to stop sending. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_OTHER_FRAME + * Set to _ENABLE to send the packet at other frame, set to _DISABLE to + * send at every frame. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SINGLE_FRAME + * Set to _ENABLE to send once next frame, set to _DISABLE to send at + * every frame. + * Note: A setting to set both _OTHER_FRAME and _SINGLE_FRAME is invalid + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ON_HBLANK + * Set to _ENABLE to send the packet once on next HBLANK, set to _DISABLE + * to send on VBLANK. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_VIDEO_FMT + * Set to _SW_CONTROLLED to set HDMI_Video_Format field and 3D_Structure field + * from NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB4 and PB5, if it is set to _HW_CONTROLLED + * then HW will get them based on the state of the setHdmiCtrl method. + * Btw this applies only for stereo ovverides. + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_STEREO_POLARITY + * Set to TRUE to enable Vendor specific info frame used for 3D stereo LR sync + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING + * Set to TRUE to enable Vendor specific info frame used for Self Refresh panels + * NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE + * This option is reserved for backward compatibility with + * NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_PACKET and + * NV0073_CTRL_CMD_DP_SET_PACKET. + * It is temporal and will be deprecated soon. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_SET_OD_PACKET_CTRL (0x730289U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_PARAMS_MESSAGE_ID (0x89U) + +typedef struct NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 type; + NvU32 transmitControl; +} NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_PARAMS; + +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ENABLE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ENABLE_NO NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE_NO +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ENABLE_YES NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE_YES +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_OTHER_FRAME NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_OTHER_FRAME_DISABLE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME_DISABLE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_OTHER_FRAME_ENABLE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME_ENABLE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SINGLE_FRAME NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SINGLE_FRAME_DISABLE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME_DISABLE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SINGLE_FRAME_ENABLE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME_ENABLE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ON_HBLANK NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ON_HBLANK_DISABLE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK_DISABLE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_ON_HBLANK_ENABLE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK_ENABLE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_VIDEO_FMT NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_VIDEO_FMT_SW_CONTROLLED NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT_SW_CONTROLLED +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_VIDEO_FMT_HW_CONTROLLED NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT_HW_CONTROLLED +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_STEREO_POLARITY NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_STEREO_POLARITY_FALSE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY_FALSE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_STEREO_POLARITY_TRUE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY_TRUE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_TRUE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_FALSE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_FALSE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_TRUE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_NO NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_NO +#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_YES NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_YES + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_PCLK_LIMIT + * + * This command returns the maximum supported pixel clock rate that is + * supported by the specified display device. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the display for which information is to be + * returned. Only one display may be indicated in this parameter. + * If more than one displayId is used a failing status of + * NV_ERR_INVALID_ARGUMENT will be returned. + * pclkLimit + * This parameter returns the min of orPclkLimit and vbPclkLimit in KHz. + * It may be used for SLI configs that use a video bridge. For non-SLI + * configs and bridgeless SLI configs, the client should use orPclkLimit instead. + * orPclkLimit + * This parameter returns the maximum pixel clock frequency of OR in KHz. + * vbPclkLimit + * This parameter returns the maximum pixel clock frequency of the + * video bridge (SLI) in KHz (or zero if there is no video bridge). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_PCLK_LIMIT (0x73028aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_PCLK_LIMIT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_GET_PCLK_LIMIT_PARAMS_MESSAGE_ID (0x8AU) + +typedef struct NV0073_CTRL_SPECIFIC_GET_PCLK_LIMIT_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 pclkLimit; + NvU32 orPclkLimit; + NvU32 vbPclkLimit; +} NV0073_CTRL_SPECIFIC_GET_PCLK_LIMIT_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_OR_GET_INFO + * + * This command returns output resource information for the specified display + * device. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the display for which information is to be + * returned. Only one display may be indicated in this parameter. + * If more than one displayId is used a failing status of + * NV_ERR_INVALID_ARGUMENT will be returned. + * type + * This parameter returns the output resource type. Legal values for + * this parameter include: + * NV0073_CTRL_SPECIFIC_OR_TYPE_DAC + * The output resource is a DAC. + * NV0073_CTRL_SPECIFIC_OR_TYPE_SOR + * The output resource is a serial output resource. + * NV0073_CTRL_SPECIFIC_OR_TYPE_DSI + * The output resource is a Display Serial Interface output resource. + * NV0073_CTRL_SPECIFIC_OR_TYPE_PIOR + * The output resource is a parallel input output resource. + * index + * This parameter returns the type-specific index of the output + * resource associated with the specified displayId. + * protocol + * This parameter returns the type-specific protocol used by the + * output resource. Legal values for this parameter include: + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_DAC_RGB_CRT + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_LVDS_CUSTOM + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_A + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_B + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DUAL_TMDS + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_A + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_B + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_PIOR_EXT_TMDS_ENC + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_DSI + * NV0073_CTRL_SPECIFIC_OR_PROTOCOL_UNKNOWN + * ditherType + * This parameter returns the dither type for the output resource. + * Legal values for this parameter include: + * NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_6_BITS + * NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_8_BITS + * NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_10_BITS + * NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_OFF + * ditherAlgo + * This parameter returns the dithering algorithm used by the output + * resource. Legal values for this parameter include: + * NV0073_CTRL_SPECIFIC_OR_DITHER_ALOGO_DYNAMIC_ERR_ACC + * NV0073_CTRL_SPECIFIC_OR_DITHER_ALOGO_STATIC_ERR_ACC + * NV0073_CTRL_SPECIFIC_OR_DITHER_ALOGO_DYNAMIC_2X2 + * NV0073_CTRL_SPECIFIC_OR_DITHER_ALOGO_STATIC_2X2 + * NV0073_CTRL_SPECIFIC_OR_DITHER_ALOGO_TEMPORAL + * NV0073_CTRL_SPECIFIC_OR_DITHER_ALOGO_UNKNOWN + * location + * This parameter returns the physical location of the output resource. + * Legal values for this parameter include: + * NV0073_CTRL_SPECIFIC_OR_LOCATION_CHIP + * NV0073_CTRL_SPECIFIC_OR_LOCATION_BOARD + * rootPortId + * This parameter specifies the Root-Port ID for the given display. + * dcbIndex + * This parameter returns the DCB index of the display device. + * vbiosAddress + * This parameter is the VBIOS IP address which will have valid value + * only if displayId is allocated by VBIOS. + * bIsLitByVbios + * This parameter specifies that whether displayID allocation was + * requested by VBIOS or not. + * bIsDispDynamic + * Returns NV_TRUE if DisplayID is allocated Dynamically else NV_FALSE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_OR_GET_INFO (0x73028bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS_MESSAGE_ID (0x8BU) + +typedef struct NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 index; + NvU32 type; + NvU32 protocol; + NvU32 ditherType; + NvU32 ditherAlgo; + NvU32 location; + NvU32 rootPortId; + NvU32 dcbIndex; + NV_DECLARE_ALIGNED(NvU64 vbiosAddress, 8); + NvBool bIsLitByVbios; + NvBool bIsDispDynamic; +} NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS; + +/* valid type values */ +#define NV0073_CTRL_SPECIFIC_OR_TYPE_NONE (0x00000000U) +#define NV0073_CTRL_SPECIFIC_OR_TYPE_DAC (0x00000001U) +#define NV0073_CTRL_SPECIFIC_OR_TYPE_SOR (0x00000002U) +#define NV0073_CTRL_SPECIFIC_OR_TYPE_PIOR (0x00000003U) + + +#define NV0073_CTRL_SPECIFIC_OR_TYPE_DSI (0x00000005U) + +/* valid DAC protocol values */ +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_DAC_RGB_CRT (0x00000000U) + + + +/* valid SOR protocol values */ +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_LVDS_CUSTOM (0x00000000U) +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_A (0x00000001U) +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_B (0x00000002U) +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DUAL_TMDS (0x00000005U) +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_A (0x00000008U) +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_B (0x00000009U) +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DSI (0x00000010U) + +/* valid DSI protocol values */ +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_DSI (0x00000011U) + +/* valid PIOR protocol values */ +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_PIOR_EXT_TMDS_ENC (0x00000000U) + +/* valid UNKNOWN protocol value */ +#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_UNKNOWN (0xFFFFFFFFU) + +/* valid ditherType values */ +#define NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_6_BITS (0x00000000U) +#define NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_8_BITS (0x00000001U) +#define NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_10_BITS (0x00000002U) +#define NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_OFF (0x00000003U) + +/* valid ditherAlgo values */ +#define NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_DYNAMIC_ERR_ACC (0x00000000U) +#define NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_STATIC_ERR_ACC (0x00000001U) +#define NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_DYNAMIC_2X2 (0x00000002U) +#define NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_STATIC_2X2 (0x00000003U) +#define NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_TEMPORAL (0x00000004U) +#define NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_UNKNOWN (0xFFFFFFFFU) + +/* valid location values */ +#define NV0073_CTRL_SPECIFIC_OR_LOCATION_CHIP (0x00000000U) +#define NV0073_CTRL_SPECIFIC_OR_LOCATION_BOARD (0x00000001U) + + + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS + * NV0073_CTRL_CMD_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS + * + * These commands retrieve and set the user backlight brightness for + * the specified display. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId + * Display for which brightness is to be retrieved or set. + * brightness + * The backlight brightness in the range [0,100], inclusive. This + * is an input for SET_BACKLIGHT_BRIGHTNESS, and an output for + * GET_BACKLIGHT_BRIGHTNESS. + * + * + * Possible status values returned include: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS (0x730291U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | 0x91" */ + +#define NV0073_CTRL_CMD_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS (0x730292U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | 0x92" */ + +#define NV0073_CTRL_BACKLIGHT_BRIGHTNESS_MIN_VALUE 0U +#define NV0073_CTRL_BACKLIGHT_BRIGHTNESS_MAX_VALUE 100U + +typedef struct NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 brightness; +} NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS + * + * This command is used to inform RM about the scrambling, clock mode, FRL and + * DSC caps of the HDMI sink device. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed.. + * displayID + * This parameter specifies the displayID for the display output resource to + * configure. + * caps + * This parameter specifies the sink caps. + * GT_340MHZ_CLOCK_SUPPORTED refers to whether sink supports TMDS clock (sorClk) rate greater than 340 MHz + * LTE_340MHZ_SCRAMBLING_SUPPORTED refers to whether scrambling is supported for clock rate at or below 340 MHz + * SCDC_SUPPORTED refers to whether SCDC access is supported on sink + * MAX_FRL_RATE_SUPPORTED refers to the maximum HDMI 2.1 FRL rate supported + * DSC_12_SUPPORTED refers to whether VESA DSC v1.2a is supported + * DSC_12_MAX_FRL_RATE_SUPPORTED refers to the maximum HDMI 2.1 FRL rate supported when VESA DSC v1.2a is supported + * + * + * Possible status values returned include: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS (0x730293U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS_MESSAGE_ID (0x93U) + +typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 caps; +} NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS; + +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_GT_340MHZ_CLOCK_SUPPORTED 0:0 +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_GT_340MHZ_CLOCK_SUPPORTED_FALSE (0x00000000U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_GT_340MHZ_CLOCK_SUPPORTED_TRUE (0x00000001U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_LTE_340MHZ_SCRAMBLING_SUPPORTED 1:1 +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_LTE_340MHZ_SCRAMBLING_SUPPORTED_FALSE (0x00000000U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_LTE_340MHZ_SCRAMBLING_SUPPORTED_TRUE (0x00000001U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_SCDC_SUPPORTED 2:2 +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_SCDC_SUPPORTED_FALSE (0x00000000U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_SCDC_SUPPORTED_TRUE (0x00000001U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED 5:3 +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_NONE (0x00000000U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_3LANES_3G (0x00000001U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_3LANES_6G (0x00000002U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_6G (0x00000003U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_8G (0x00000004U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_10G (0x00000005U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_12G (0x00000006U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_12_SUPPORTED 6:6 +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_12_SUPPORTED_FALSE (0x00000000U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_12_SUPPORTED_TRUE (0x00000001U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED 9:7 +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_NONE (0x00000000U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_3LANES_3G (0x00000001U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_3LANES_6G (0x00000002U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_6G (0x00000003U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_8G (0x00000004U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_10G (0x00000005U) +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_12G (0x00000006U) + + + +/* + * NV0073_CTRL_CMD_SPECIFIC_SET_MONITOR_POWER + * + * This command sets monitor power on/off. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId + * This parameter specifies the displayID for the display output resource to + * configure. + * powerState + * This parameter should be one of the valid + * NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_* values. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SPECIFIC_SET_MONITOR_POWER (0x730295U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS_MESSAGE_ID (0x95U) + +typedef struct NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 powerState; +} NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS; + +#define NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_OFF (0x00000000U) +#define NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_ON (0x00000001U) + + + +/* +* NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_CONFIG +* +* This command is used to perform HDMI FRL link training and enable FRL mode for +* the specified displayId. The link configuration will be returned after link +* training success. +* +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. +* displayID +* This parameter specifies the displayID for the display output resource to +* configure. +* data +* This parameter is an input and output to this command. +* Here are the current defined fields: +* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE +* This field specifies the desired setting for lane count. A client may +* choose any lane count as long as it does not exceed the capability of +* HDMI FRL sink as indicated in the sink capability field. +* The valid values for this field are: +* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_NONE +* For 0 lane configuration, link training is shut down (disable FRL). +* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_3G +* For FRL 3-lane configuration and 3 Gbps bandwidth per lane. +* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_6G +* For FRL 3-lane configuration and 6 Gbps bandwidth per lane. +* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_6G +* For FRL 4-lane configuration and 6 Gbps bandwidth per lane. +* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_8G +* For FRL 4-lane configuration and 8 Gbps bandwidth per lane. +* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_10G +* For FRL 4-lane configuration and 10 Gbps bandwidth per lane. +* NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_12G +* For FRL 4-lane configuration and 12 Gbps bandwidth per lane. +* On return, the link bandwidth setting is returned which may be +* different from the requested input setting. +* bFakeLt +* This flag as input to this command. +* It indicates the FRL link training is a fake link training or not. +* TRUE if the FRL link training is fake and no real sink device attached. +* bLtSkipped +* The flag returned indicating whether link training is skipped or not. +* TRUE if link training is skipped due to the link config is not changed. +* +* Possible status values returned include: +* NV_OK - +* Affter finishing link tranning, NV_OK status will be returned along with +* the updated link congiration. In case of link training failure, FRL_RATE_NONE +* will be returned with NV_OK. +* NV_ERR_NOT_SUPPORTED - +* If the GPU/sink is not capable for HDMI FRL, NV_ERR_NOT_SUPPORTED status +* will be returned. +* NV_ERR_INVALID_ARGUMENT +* If any argument is valid for this control call, NV_ERR_INVALID_ARGUMENT +* status will be returned. +*/ +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_CONFIG (0x73029aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS_MESSAGE_ID (0x9AU) + +typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 data; + NvBool bFakeLt; + NvBool bLtSkipped; +} NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS; + +#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE 2:0 +#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_NONE (0x00000000U) +#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_3G (0x00000001U) +#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_6G (0x00000002U) +#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_6G (0x00000003U) +#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_8G (0x00000004U) +#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_10G (0x00000005U) +#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_12G (0x00000006U) + + + +#define NV0073_CTRL_SPECIFIC_MAX_CRC_REGIONS 9U + +#define NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS_PARAMS_MESSAGE_ID (0xA0U) + +typedef struct NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 regionCrcs[NV0073_CTRL_SPECIFIC_MAX_CRC_REGIONS]; + NvU16 reqRegionCrcMask; +} NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS + * + * This command is used to capture the active viewport region CRCs + * + * [in]subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * [in]displayId + * This parameter specifies the displayId of panel, for which region CRC to be captured +.* + * [out]regionCrcs + * This field holds the region CRC values to be returned after successful completion of the control command. + * + * [in]reqRegionCrcMask + * This parameter specifies BIT mask value of requested CRC regions. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS (0x7302a0U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS_PARAMS_MESSAGE_ID" */ + +/* +* NV0073_CTRL_CMD_SPECIFIC_APPLY_EDID_OVERRIDE_V2 +* +* Apply EDID override on specific OD. +* +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. +* displayId (in) +* ID of panel on which the operation is to be performed. +* bufferSize (in) +* Size of the EDID buffer. +* edidBuffer (in/out) +* The buffer which stores the EDID before and after override. +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_PARAMETER +*/ +#define NV0073_CTRL_CMD_SPECIFIC_APPLY_EDID_OVERRIDE_V2 (0x7302a1U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_APPLY_EDID_OVERRIDE_V2_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_APPLY_EDID_OVERRIDE_V2_PARAMS_MESSAGE_ID (0xA1U) + +typedef struct NV0073_CTRL_SPECIFIC_APPLY_EDID_OVERRIDE_V2_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 bufferSize; + NvU8 edidBuffer[NV0073_CTRL_SPECIFIC_GET_EDID_MAX_EDID_BYTES]; +} NV0073_CTRL_SPECIFIC_APPLY_EDID_OVERRIDE_V2_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS + * + * This command is used to get the HDMI FRL caps of GPU side. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * caps + * This parameter specifies the GPU caps. + * MAX_FRL_RATE_SUPPORTED refers to the maximum HDMI 2.1 FRL link rate supported + * + * + * Possible status values returned include: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS (0x7302a2U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_HDMI_GPU_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_GET_HDMI_GPU_CAPS_PARAMS_MESSAGE_ID (0xA2U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_HDMI_GPU_CAPS_PARAMS { + NvU32 subDeviceInstance; + NvU32 caps; +} NV0073_CTRL_SPECIFIC_GET_HDMI_GPU_CAPS_PARAMS; + +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED 2:0 +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_NONE (0x00000000U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_3LANES_3G (0x00000001U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_3LANES_6G (0x00000002U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_4LANES_6G (0x00000003U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_4LANES_8G (0x00000004U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_4LANES_10G (0x00000005U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_GPU_CAPS_MAX_FRL_LINK_RATE_SUPPORTED_4LANES_12G (0x00000006U) + + + +/* + * NV0073_CTRL_CMD_SPECIFIC_DISPLAY_CHANGE + * + * Notifies the system that a display change is about to begin/end. + * Also performs the necessary synchronizations for the same. + * + * The command takes a NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS structure as an + * argument with appropriate subDeviceInstance. + * + * [in]subDeviceInstance + * The sub-device instance + * [in]newDevices + * Bitmask of devices that are planned on being enabled with the + * pending device change. See NV_CFGEX_GET_DEVICES_CONFIGURATION for bit defs. + * [in]properties + * Bitmask of display attributes for new configuration (none used at the moment). + * [in]enable + * Parameter to decide between display change start and end. Can take values + * NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_START or NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_END. + * Possible return values: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + */ + +#define NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS_MESSAGE_ID (0xA4U) + +typedef struct NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS { + + NvU32 subDeviceInstance; + NvU32 newDevices; + NvU32 properties; + NvU32 enable; +} NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS; + +#define NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_END (0x00000000U) +#define NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_START (0x00000001U) + +#define NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PROPERTIES_SPANNING (0x00000001U) + +#define NV0073_CTRL_CMD_SPECIFIC_DISPLAY_CHANGE (0x7302a4U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS_MESSAGE_ID" */ + + + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA + * + * This command is used to get the HDMI sink status/caps via Status and Control + * Data Channel (SCDC). + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayId + * This parameter specifies the displayId of HDMI sink. + * offset + * This parameter specifies the SCDC offset which the read operation + * should be used. + * data + * This field specifies the return data from sink for reading the specified + * SCDC offset. + * + * + * Possible status values returned include: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA (0x7302a6U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_HDMI_SCDC_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_GET_HDMI_SCDC_DATA_PARAMS_MESSAGE_ID (0xA6U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_HDMI_SCDC_DATA_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU8 offset; + NvU8 data; +} NV0073_CTRL_SPECIFIC_GET_HDMI_SCDC_DATA_PARAMS; + +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET 7:0 +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_NONE (0x00000000U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_SINK_VERSION (0x00000001U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_SOURCE_VERSION (0x00000002U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_UPDATE_FLAGS_0 (0x00000010U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_TMDS_CONFIGURATION (0x00000020U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_SCRAMBLER_STATUS (0x00000021U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CONFIGURATION_0 (0x00000030U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CONFIGURATION_1 (0x00000031U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_SOURCE_TEST_CONFIGURATION (0x00000035U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_STATUS_FLAGS_0 (0x00000040U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_STATUS_FLAGS_1 (0x00000041U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_STATUS_FLAGS_2 (0x00000042U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_0 (0x00000050U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_1 (0x00000051U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_2 (0x00000052U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_3 (0x00000053U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_4 (0x00000054U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_5 (0x00000055U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_6 (0x00000056U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_7 (0x00000057U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_CED_8 (0x00000058U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_RSED_0 (0x00000059U) +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_SCDC_DATA_OFFSET_RSED_1 (0x0000005AU) + +/* + * NV0073_CTRL_CMD_SPECIFIC_IS_DIRECTMODE_DISPLAY + * + * This command is used to query whether the specified monitor should be used + * with directmode. + * + * [in]manufacturerID + * This parameter specifies the 16-bit EDID Manufacturer ID. + * [in]productID + * This parameter specifies the 16-bit EDID Product ID. + * [out]bIsDirectmode; + * This indicates whether the monitor should be used with directmode. + * Possible return values: + * NV_OK + */ + +#define NV0073_CTRL_CMD_SPECIFIC_IS_DIRECTMODE_DISPLAY (0x7302a7U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_IS_DIRECTMODE_DISPLAY_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_IS_DIRECTMODE_DISPLAY_PARAMS_MESSAGE_ID (0xA7U) + +typedef struct NV0073_CTRL_SPECIFIC_IS_DIRECTMODE_DISPLAY_PARAMS { + NvU16 manufacturerID; + NvU16 productID; + NvBool bIsDirectmode; +} NV0073_CTRL_SPECIFIC_IS_DIRECTMODE_DISPLAY_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION + * + * This command is used to get the HDMI FRL capacity computation result. + * + * [in] cmd + * This parameter specifies the command for the HDMI FRL capacity computation. + * [in] input + * This parameter specifies the input data for the HDMI FRL capacity + * computation. + * [out] result + * This indicates the computation result of HDMI FRL capacity computation. + * [in/out] preCalc + * This indicates the pre-caculation result of HDMI FRL capacity computation. + * [in/out] dsc + * This indicates the DSC parameters of HDMI FRL capacity computation. + * Possible return values: + * NV_OK + */ + +#define NV0073_CTRL_CMD_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION (0x7302a8U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS_MESSAGE_ID" */ + +typedef struct NV0073_CTRL_FRL_CAPACITY_COMPUTATION_PARAMS { + NvU32 numLanes; + NvU32 frlBitRateGbps; + NvU32 pclk10KHz; + NvU32 hTotal; + NvU32 hActive; + NvU32 bpc; + NvU32 pixelPacking; + NvU32 audioType; + NvU32 numAudioChannels; + NvU32 audioFreqKHz; + + struct { + NvU32 bppTargetx16; + NvU32 hSlices; + NvU32 sliceWidth; + NvU32 dscTotalChunkKBytes; + } compressionInfo; +} NV0073_CTRL_FRL_CAPACITY_COMPUTATION_PARAMS; + +typedef struct NV0073_CTRL_FRL_CAPACITY_COMPUTATION_RESULT { + NvU32 frlRate; + NvU32 bppTargetx16; + NvBool engageCompression; + NvBool isAudioSupported; + NvBool dataFlowDisparityReqMet; + NvBool dataFlowMeteringReqMet; + NvBool isVideoTransportSupported; + NvU32 triBytesBorrowed; + NvU32 hcActiveBytes; + NvU32 hcActiveTriBytes; + NvU32 hcBlankTriBytes; + NvU32 tBlankToTTotalX1k; +} NV0073_CTRL_FRL_CAPACITY_COMPUTATION_RESULT; + +typedef struct NV0073_CTRL_FRL_PRE_CALC_CONFIG { + NvU32 vic; + NvU32 packing; + NvU32 bpc; + NvU32 frlRate; + NvU32 bppX16; + NvBool bHasPreCalcFRLData; +} NV0073_CTRL_FRL_PRE_CALC_CONFIG; + +typedef struct NV0073_CTRL_IS_FRL_DSC_POSSIBLE_PARAMS { + NvU32 maxSliceCount; + NvU32 maxSliceWidth; + NvBool bIsDSCPossible; +} NV0073_CTRL_IS_FRL_DSC_POSSIBLE_PARAMS; + +#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS_MESSAGE_ID (0xA8U) + +typedef struct NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS { + NvU8 cmd; + NV0073_CTRL_FRL_CAPACITY_COMPUTATION_PARAMS input; + NV0073_CTRL_FRL_CAPACITY_COMPUTATION_RESULT result; + NV0073_CTRL_FRL_PRE_CALC_CONFIG preCalc; + NV0073_CTRL_IS_FRL_DSC_POSSIBLE_PARAMS dsc; +} NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS; + +#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_NULL (0x00000000U) +#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_UNCOMPRESSED_VIDEO (0x00000001U) +#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_COMPRESSED_VIDEO (0x00000002U) +#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_HAS_PRECAL_FRL_DATA (0x00000003U) +#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_GET_PRECAL_UNCOMPRESSED_FRL_CONFIG (0x00000004U) +#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_GET_PRECAL_COMPRESSED_FRL_CONFIG (0x00000005U) +#define NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_CMD_IS_FRL_DSC_POSSIBLE (0x00000006U) + +/* + * NV0073_CTRL_CMD_SPECIFIC_SET_SHARED_GENERIC_PACKET + * + * This command is used to program the display output packets. + * This generic packets can be used for both HDMI and DP. + * HW has added 6 new generic packets for each head because some usecases have + * requirement to send infoframe in particular location (vsync, vblank, loadV). + * + * Note: 1. Client first needs to reserve or acquire a free infoframe index + * using NV0073_CTRL_CMD_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET. + * 2. Client needs to update the SDP index for head through control call + * NV0073_CTRL_CMD_SPECIFIC_SET_SHARED_GENERIC_PACKET + * 3. Client needs to Release the infoframe index using control call + * NV0073_CTRL_CMD_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET + * + * [in]subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * [in]transmitControl + * This parameter controls how the packet is to be sent by setting the + * control bits. + * Possible flags are as follows: + * NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_ENABLE + * Setting this field to _YES will enable this generic infoframe, + * Setting this field to _NO will disable this generic infoframe. + * NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_SINGLE + * Set to _YES will cause new infoframe to be transmitted exactly once. + * Set to _NO will cause new infoframe to be transmitted every frame. + * NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_LOC + * SDP can be sent in 3 different locations: + * VBLANK - new infoframe will be sent at Vblank. + * VSYNC - new infoframe will be sent at Vsync. + * LOADV - new infoframe will be triggered by LOADV, and sent at Vsync + * NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_UPDATE_RFB_OVERRIDE + * _ENABLE: override DB1 bit1 with existence of loadv (for Panel Self Refresh) + * _DISABLE: do not override shared generic infoframe subpacker DB1 bit1. + * NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_SU_COORDINATES_VALID_OVERRIDE + * _ENABLE: override DB1 bit3 with existence of loadv (for Panel Replay) + * _DISABLE: do not override shared generic infoframe subpacker DB1 bit3. + * [in]packetSize + * size of packets in Packet array to send, including header and payload. + * [in]infoframeIndex + * Specifies the target head number for which SDP needs to be updated. + * [in]infoframeIndex + * Specifies the index of infoframe. + * [in]packet + * pPacket points to the packets to send. + * For HDMI 1.1, the maximum allowed bytes is 31. + * The packet array includes the 3 bytes of header + data depending on + * the type of packet. For an infoframe, the header bytes refer to type, + * version and length respectively. This comes as input to this command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SPECIFIC_SET_SHARED_GENERIC_PACKET (0x7302a9) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_SHARED_GENERIC_PACKET_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_SHARED_GENERIC_PACKET_PARAMS_MESSAGE_ID (0xA9U) + +typedef struct NV0073_CTRL_SPECIFIC_SET_SHARED_GENERIC_PACKET_PARAMS { + NvU32 subDeviceInstance; + NvU32 transmitControl; + NvU32 packetSize; + NvU32 targetHeadIndex; + NvU32 infoframeIndex; + NvU8 packet[NV0073_CTRL_SET_OD_MAX_PACKET_SIZE]; +} NV0073_CTRL_SPECIFIC_SET_SHARED_GENERIC_PACKET_PARAMS; + +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_ENABLE 0:0 +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_ENABLE_NO (0x0000000) +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_ENABLE_YES (0x0000001) + +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_SINGLE 1:1 +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_SINGLE_NO (0x0000000) +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_SINGLE_YES (0x0000001) + +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_LOC 5:2 +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_LOC_VBLANK (0x0000000) +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_LOC_VSYNC (0x0000001) +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_LOC_LOADV (0x0000002) + +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_STATE_OVERRIDE 6:6 +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_STATE_OVERRIDE_DISABLE (0x0000000) +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_STATE_OVERRIDE_ENABLE (0x0000001) + +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_UPDATE_RFB_OVERRIDE 7:7 +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_UPDATE_RFB_OVERRIDE_DISABLE (0x0000000) +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_UPDATE_RFB_OVERRIDE_ENABLE (0x0000001) + +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_SU_COORDINATES_VALID_OVERRIDE 8:8 +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_SU_COORDINATES_VALID_OVERRIDE_DISABLE (0x0000000) +#define NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_VSC_SDP_SU_COORDINATES_VALID_OVERRIDE_ENABLE (0x0000001) + +/* + * NV0073_CTRL_CMD_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET + * + * This command is used to reserve the infoframe for head and RM would assign + * free infoframe index and return the index of infoframe. Later client needs + * to call control call NV0073_CTRL_CMD_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET + * to release the index. + * + * [in]subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * [in]targetHeadIndex + * target Head for which SDP needs to be sent + * [out]infoframeIndex + * return Infoframe Index for head. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFIENT_RESOURCES + */ + +#define NV0073_CTRL_CMD_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET (0x7302aa) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET_PARAMS_MESSAGE_ID (0xAAU) + +typedef struct NV0073_CTRL_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET_PARAMS { + NvU32 subDeviceInstance; + NvU32 targetHeadIndex; + NvU32 infoframeIndex; +} NV0073_CTRL_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET + * + * This command is used to release the infoframe index which was acquired by + * client. + * + * [in]subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * [in]targetHeadIndex + * Specifies the target head number for which SDP needs to be updated. + * [in]infoframeIndex + * Infoframe index for the target head + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET (0x7302ab) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET_PARAMS_MESSAGE_ID (0xABU) + +typedef struct NV0073_CTRL_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET_PARAMS { + NvU32 subDeviceInstance; + NvU32 targetHeadIndex; + NvU32 infoframeIndex; +} NV0073_CTRL_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET_PARAMS; + +/* + * NV0073_CTRL_CMD_SPECIFIC_DISP_I2C_READ_WRITE + * + * This command is used to do I2C R/W to slave on display i2c instance. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * i2cPort + * This parameter specifies the I2C CCB port ID. + * i2cSlaveAddress + * This parameter specifies the I2C slave address. + * readWriteFlag + * This parameter specifies whether its read/write operation. + * readWriteLen + * This parameter specifies the length of the read/write buffer + * readBuffer + * This parameter reads the data from slave address and copies to this + * buffer + * writeBuffer + * This parameter specifies this buffer data that would be written to + * slave address + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SPECIFIC_DISP_I2C_READ_WRITE (0x7302acU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_BUF_LEN 128U + +#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS_MESSAGE_ID (0xACU) + +typedef struct NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS { + NvU32 subDeviceInstance; + NvU32 i2cPort; + NvU32 i2cSlaveAddress; + NvU32 readWriteFlag; + NvU32 readWriteLen; + NvU8 readBuffer[NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_BUF_LEN]; + NvU8 writeBuffer[NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_BUF_LEN]; +} NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS; + +#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_MODE (0x00000001) +#define NV0073_CTRL_SPECIFIC_DISP_I2C_WRITE_MODE (0x00000000) + +/* + * NV0073_CTRL_CMD_GET_VALID_HEAD_WINDOW_ASSIGNMENT + * + * This command returns the valid window head assignment mask + * + * windowHeadMask [out] + * This out parameter is an array which holds the head mask for + * each window. The Nth element in the array would be a bitmask + * of which heads can possibly drive window N. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT (0x7302ad) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_MAX_WINDOWS 32U +#define NV0073_CTRL_SPECIFIC_FLEXIBLE_HEAD_WINDOW_ASSIGNMENT (0xFFU) + +#define NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS_MESSAGE_ID (0xADU) + +typedef struct NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS { + NvU32 subDeviceInstance; + NvU8 windowHeadMask[NV0073_CTRL_SPECIFIC_MAX_WINDOWS]; +} NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS; + +/* _ctrl0073specific_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h new file mode 100644 index 0000000..9a585aa --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h @@ -0,0 +1,166 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073stereo.finn +// + +#include "ctrl/ctrl0073/ctrl0073base.h" + + + +/* + * NV0073_CTRL_CMD_STEREO_DONGLE_SET_TIMINGS + * + * Sets new video mode timings + * E.g. from display driver on mode set + * + * Parameters: + * [IN] subDeviceInstance - This parameter specifies the subdevice instance + * within the NV04_DISPLAY_COMMON parent device to which the operation + * should be directed. This parameter must specify a value between + * zero and the total number of subdevices within the parent device. + * This parameter should be set to zero for default behavior. + * [IN] head - head to be passed to stereoDongleControl + * [IN] timings - new timings to be set + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED - stereo is not initialized on the GPU + */ +#define NV0073_CTRL_CMD_STEREO_DONGLE_SET_TIMINGS (0x731703U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID << 8) | NV0073_CTRL_STEREO_DONGLE_SET_TIMINGS_PARAMS_MESSAGE_ID" */ + +typedef struct NV0073_CTRL_STEREO_VIDEO_MODE_TIMINGS { + NvU32 PixelClock; + NvU16 TotalWidth; + NvU16 VisibleImageWidth; + NvU16 HorizontalBlankStart; + NvU16 HorizontalBlankWidth; + NvU16 HorizontalSyncStart; + NvU16 HorizontalSyncWidth; + NvU16 TotalHeight; + NvU16 VisibleImageHeight; + NvU16 VerticalBlankStart; + NvU16 VerticalBlankHeight; + NvU16 VerticalSyncStart; + NvU16 VerticalSyncHeight; + NvU16 InterlacedMode; + NvU16 DoubleScanMode; + + NvU16 MonitorVendorId; + NvU16 MonitorProductId; +} NV0073_CTRL_STEREO_VIDEO_MODE_TIMINGS; + +#define NV0073_CTRL_STEREO_DONGLE_SET_TIMINGS_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0073_CTRL_STEREO_DONGLE_SET_TIMINGS_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NV0073_CTRL_STEREO_VIDEO_MODE_TIMINGS timings; +} NV0073_CTRL_STEREO_DONGLE_SET_TIMINGS_PARAMS; + +/* + * NV0073_CTRL_CMD_STEREO_DONGLE_ACTIVATE + * + * stereoDongleActivate wrapper / NV_STEREO_DONGLE_ACTIVATE_DATA_ACTIVE_YES + * Updates sbios of 3D stereo state active + * + * Parameters: + * [IN] subDeviceInstance - This parameter specifies the subdevice instance + * within the NV04_DISPLAY_COMMON parent device to which the operation + * should be directed. This parameter must specify a value between + * zero and the total number of subdevices within the parent device. + * This parameter should be set to zero for default behavior. + * [IN] head - head to be passed to stereoDongleActivate + * [IN] bSDA - enable stereo on DDC SDA + * [IN] bWorkStation - is workstation stereo? + * [IN] bDLP - is checkerboard DLP Stereo? + * [IN] IRPower - IR power value + * [IN] flywheel - FlyWheel value + * [IN] bRegIgnore - use reg? + * [IN] bI2cEmitter - Sets NV_STEREO_DONGLE_ACTVATE_DATA_I2C_EMITTER_YES and pStereo->bAegisDT + * [IN] bForcedSupported - Sets NV_STEREO_DONGLE_FORCED_SUPPORTED_YES and pStereo->GPIOControlledDongle + * [IN] bInfoFrame - Aegis DT with DP InfoFrame + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT - if (head > OBJ_MAX_HEADS) + * NV_ERR_NOT_SUPPORTED - stereo is not initialized on the GPU + */ +#define NV0073_CTRL_CMD_STEREO_DONGLE_ACTIVATE (0x731704U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID << 8) | NV0073_CTRL_STEREO_DONGLE_ACTIVATE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_STEREO_DONGLE_ACTIVATE_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0073_CTRL_STEREO_DONGLE_ACTIVATE_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvBool bSDA; + NvBool bWorkStation; + NvBool bDLP; + NvU8 IRPower; + NvU8 flywheel; + NvBool bRegIgnore; + NvBool bI2cEmitter; + NvBool bForcedSupported; + NvBool bInfoFrame; +} NV0073_CTRL_STEREO_DONGLE_ACTIVATE_PARAMS; + +/* + * NV0073_CTRL_CMD_STEREO_DONGLE_DEACTIVATE + * + * stereoDongleActivate wrapper / NV_STEREO_DONGLE_ACTIVATE_DATA_ACTIVE_NO + * + * If active count<=0 then no 3D app is running which indicates + * that we have really deactivated the stereo, updates sbios of 3D stereo state NOT ACTIVE. + * + * Parameters: + * [IN] subDeviceInstance - This parameter specifies the subdevice instance + * within the NV04_DISPLAY_COMMON parent device to which the operation + * should be directed. This parameter must specify a value between + * zero and the total number of subdevices within the parent device. + * This parameter should be set to zero for default behavior. + * [IN] head - head to be passed to stereoDongleActivate + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT - if (head > OBJ_MAX_HEADS) + * NV_ERR_NOT_SUPPORTED - stereo is not initialized on the GPU + */ +#define NV0073_CTRL_CMD_STEREO_DONGLE_DEACTIVATE (0x731705U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID << 8) | NV0073_CTRL_STEREO_DONGLE_DEACTIVATE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_STEREO_DONGLE_DEACTIVATE_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0073_CTRL_STEREO_DONGLE_DEACTIVATE_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; +} NV0073_CTRL_STEREO_DONGLE_DEACTIVATE_PARAMS; + + + +/* _ctrl0073stereo_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073svp.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073svp.h new file mode 100644 index 0000000..08a06ae --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073svp.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073svp.finn +// + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h new file mode 100644 index 0000000..d25501a --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h @@ -0,0 +1,1480 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073system.finn +// + +#include "ctrl/ctrl0073/ctrl0073base.h" + +/* NV04_DISPLAY_COMMON system-level control commands and parameters */ + +/* extract cap bit setting from tbl */ +#define NV0073_CTRL_SYSTEM_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* Caps format is byte_index:bit_mask. + * Important: keep the number of bytes needed for these fields in sync with + * NV0073_CTRL_SYSTEM_CAPS_TBL_SIZE + */ +#define NV0073_CTRL_SYSTEM_CAPS_AA_FOS_GAMMA_COMP_SUPPORTED 0:0x01 +#define NV0073_CTRL_SYSTEM_CAPS_TV_LOWRES_BUG_85919 0:0x02 +#define NV0073_CTRL_SYSTEM_CAPS_DFP_GPU_SCALING_BUG_154102 0:0x04 +#define NV0073_CTRL_SYSTEM_CAPS_SLI_INTERLACED_MODE_BUG_235218 0:0x08 // Deprecated +#define NV0073_CTRL_SYSTEM_CAPS_STEREO_DIN_AVAILABLE 0:0x10 +#define NV0073_CTRL_SYSTEM_CAPS_OFFSET_PCLK_DFP_FOR_EMI_BUG_443891 0:0x20 +#define NV0073_CTRL_SYSTEM_CAPS_GET_DMI_SCANLINE_SUPPORTED 0:0x40 +/* + * Indicates support for HDCP Key Selection Vector (KSV) list and System + * Renewability Message (SRM) validation +*/ +#define NV0073_CTRL_SYSTEM_CAPS_KSV_SRM_VALIDATION_SUPPORTED 0:0x80 + +#define NV0073_CTRL_SYSTEM_CAPS_SINGLE_HEAD_MST_SUPPORTED 1:0x01 +#define NV0073_CTRL_SYSTEM_CAPS_SINGLE_HEAD_DUAL_SST_SUPPORTED 1:0x02 +#define NV0073_CTRL_SYSTEM_CAPS_HDMI_2_0_SUPPORTED 1:0x04 +#define NV0073_CTRL_SYSTEM_CAPS_CROSS_BAR_SUPPORTED 1:0x08 +#define NV0073_CTRL_SYSTEM_CAPS_RASTER_LOCK_NEEDS_MIO_POWER 1:0x10 +/* + * Indicates that modesets where no heads are increasing resource requirements, + * or no heads are decreasing resource requirements, can be done glitchlessly. + */ +#define NV0073_CTRL_SYSTEM_CAPS_GLITCHLESS_MODESET_SUPPORTED 1:0x20 +/* Indicates the SW ACR is enabled for HDMI 2.1 due to Bug 3275257. */ +#define NV0073_CTRL_SYSTEM_CAPS_HDMI21_SW_ACR_BUG_3275257 1:0x40 + +/* Size in bytes of display caps table. Keep in sync with # of fields above. */ +#define NV0073_CTRL_SYSTEM_CAPS_TBL_SIZE 2U + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_CAPS_V2 + * + * This command returns the set of display capabilities for the parent device + * in the form of an array of unsigned bytes. Display capabilities + * include supported features and required workarounds for the display + * engine(s) within the device, each represented by a byte offset into the + * table and a bit position within that byte. The set of display capabilities + * will be normalized across all GPUs within the device (a feature capability + * will be set only if it's supported on all GPUs while a required workaround + * capability will be set if any of the GPUs require it). + * + * [out] capsTbl + * The display caps bits will be transferred by the RM into this array of + * unsigned bytes. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_CAPS_V2 (0x730138U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x38U) + +typedef struct NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS { + NvU8 capsTbl[NV0073_CTRL_SYSTEM_CAPS_TBL_SIZE]; +} NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_NUM_HEADS + * + * This commands returns the number of heads supported by the specified + * subdevice and available for use by displays. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * flags + * This parameter specifies optional flags to be used to while retrieving + * the number of heads. + * Possible valid flags are: + * NV0073_CTRL_SYSTEM_GET_NUM_HEADS_CLIENT + * This flag is used to request the number of heads that are + * currently in use by an NV client using a user display class + * instance (see NV15_VIDEO_LUT_CURSOR_DAC for an examle). If this + * flag is disabled then the total number of heads supported is + * returned. + * numHeads + * This parameter returns the number of usable heads for the specified + * subdevice. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_NUM_HEADS (0x730102U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS { + NvU32 subDeviceInstance; + NvU32 flags; + NvU32 numHeads; +} NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS; + +/* valid get num heads flags */ +#define NV0073_CTRL_SYSTEM_GET_NUM_HEADS_FLAGS_CLIENT 0:0 +#define NV0073_CTRL_SYSTEM_GET_NUM_HEADS_FLAGS_CLIENT_DISABLE (0x00000000U) +#define NV0073_CTRL_SYSTEM_GET_NUM_HEADS_FLAGS_CLIENT_ENABLE (0x00000001U) + + + + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_SCANLINE + * + * This command returns the current RG scanline of the specified head on the + * specified subdevice. To get the DMI scanline on supported chips, use + * NV0073_CTRL_CMD_SYSTEM_GET_DMI_SCANLINE + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * head + * This parameter specifies the head for which the active display + * should be retrieved. This value must be between zero and the + * maximum number of heads supported by the subdevice. + * currentScanline + * This parameter returns the current RG scanline value for the specified + * head. If the head does not have a valid mode enabled then a scanline + * value of 0xffffffff is returned. + * bStereoEyeSupported (out) + * This parameter specifies whether stereoEye reporting is supported (this + * is hw dependent). Note that this value doesn't actually reflect whether + * given head is really in stereo mode. + * stereoEye (out) + * If supported (ie bStereoEyeSupported is TRUE), this parameter returns + * either NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS_RIGHT_EYE or + * NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS_LEFT_EYE, reflecting the + * stereo eye that is currently scanned out. Although this value typically + * changes at the beginning of vblank, the exact guarantee isn't more + * accurate than "somewhere in vblank". + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_SCANLINE (0x730108U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_GET_SCANLINE_RIGHT_EYE 0x00000000U +#define NV0073_CTRL_CMD_SYSTEM_GET_SCANLINE_LEFT_EYE 0x00000001U + +#define NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvU32 currentScanline; + NvBool bStereoEyeSupported; + NvU32 stereoEye; +} NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_VBLANK_COUNTER + * + * This command returns the current VBlank counter of the specified head on the + * specified subdevice. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * head + * This parameter specifies the head for which the vblank counter + * should be retrieved. This value must be between zero and the + * maximum number of heads supported by the subdevice. + * verticalBlankCounter + * This parameter returns the vblank counter value for the specified + * head. If the display mode is not valid or vblank not active then + * the verticalBlankCounter value is undefined. + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_VBLANK_COUNTER (0x730109U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvU32 verticalBlankCounter; +} NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_VBLANK_ENABLE + * + * This command returns the current VBlank enable status for the specified + * head. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * head + * This parameter specifies the head for which the vblank status + * should be retrieved. This value must be between zero and the + * maximum number of heads supported by the subdevice. + * bEnabled + * This parameter returns the vblank enable status for the specified head. + * A value of NV_FALSE indicates that vblank interrupts are not currently + * enabled while a value of NV_TRUE indicates that vblank are currently + * enabled. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_VBLANK_ENABLE (0x73010aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvBool bEnabled; +} NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED + * + * This command returns the set of supported display IDs for the specified + * subdevice in the form of a 32bit display mask. State from internal + * display connectivity tables is used to determine the set of possible + * display connections for the GPU. The presence of a display in the + * display mask only indicates the display is supported. The connectivity + * status of the display should be determined using the + * NV0073_CTRL_CMD_SYSTEM_GET_CONNECT_STATE command. The displayMask + * value returned by NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED is static + * and will remain consistent across boots of the system. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayMask + * This parameter returns a NV0073_DISPLAY_MASK value describing the set + * of displays supported by the subdevice. An enabled bit in displayMask + * indicates the support of a display device with that displayId. + * displayMaskDDC + * This parameter returns a NV0073_DISPLAY_MASK value, indicating the + * subset of displayMask that supports DDC. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED (0x730120U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayMask; + NvU32 displayMaskDDC; +} NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_CONNECT_STATE + * + * This command can be used to check the presence of a mask of display + * devices on the specified subdevice. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * flags + * This parameter specifies optional flags to be used while retrieving + * the connection state information. + * Here are the current defined fields: + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD + * A client uses this field to indicate what method it wishes the + * system to use when determining the presence of attached displays. + * Possible values are: + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD_DEFAULT + * The system decides what method to use. + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD_CACHED + * Return the last full detection state for the display mask. + * safety.) + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD_ECONODDC + * Ping the DDC address of the given display mask to check for + * a connected device. This is a lightweight method to check + * for a present device. + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_DDC + * A client uses this field to indicate whether to allow DDC during + * this detection or to not use it. + * Possible values are: + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_DDC_DEFAULT + * The system will use DDC as needed for each display. + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_DDC_DISABLE + * The system will not use DDC for any display. If DDC is + * disabled, this detection state will not be cached. + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_LOAD + * A client uses this field to indicate whether to detect loads + * during this detection or to not use it. + * Possible values are: + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_LOAD_DEFAULT + * The system will use load detection as needed for each display. + * NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_LOAD_DISABLE + * The system will not use load detection for any display. If + * load detection is disabled, this detection state will not + * be cached. + * displayMask + * This parameter specifies an NV0073_DISPLAY_MASK value describing + * the set of displays for which connectivity status is to be checked. + * If a display is present then the corresponding bit in the display + * mask is left enabled. If the display is not present then the + * corresponding bit in the display mask is disabled. Upon return this + * parameter contains the subset of displays in the mask that are + * connected. + * + * If displayMask includes bit(s) that correspond to a TV encoder, the + * result will be simply 'yes' or 'no' without any indication of which + * connector(s) are actually attached. For fine-grained TV attachment + * detection, please see NV0073_CTRL_CMD_TV_GET_ATTACHMENT_STATUS. + * retryTimeMs + * This parameter is an output to this command. In case of + * NVOS_STATUS_ERROR_RETRY return status, this parameter returns the time + * duration in milli-seconds after which client should retry this command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_ERROR_RETRY + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_CONNECT_STATE (0x730122U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS { + NvU32 subDeviceInstance; + NvU32 flags; + NvU32 displayMask; + NvU32 retryTimeMs; +} NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS; + +/* valid get connect state flags */ +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD 1:0 +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD_DEFAULT (0x00000000U) +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD_CACHED (0x00000001U) +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_METHOD_ECONODDC (0x00000002U) +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_DDC 4:4 +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_DDC_DEFAULT (0x00000000U) +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_DDC_DISABLE (0x00000001U) +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_LOAD 5:5 +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_LOAD_DEFAULT (0x00000000U) +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_LOAD_DISABLE (0x00000001U) +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_VBLANK 6:6 +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_VBLANK_DEFAULT (0x00000000U) +#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_FLAGS_VBLANK_SAFE (0x00000001U) + + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_CONFIG + * + * This command can be used to retrieve dynamic hotplug state information that + * are currently recorded by the RM. This information can be used by the client + * to determine which displays to detect after a hotplug event occurs. Or if + * the client knows that this device generates a hot plug/unplug signal on all + * connectors, then this can be used to cull displays from detection. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * flags + * This parameter specifies optional flags to be used while retrieving + * or changing the hotplug configuration. + * No flags are currently defined. + * hotplugEventMask + * For _GET_HOTPLUG_CONFIG, this returns which connectors the client + * has asked for notifications for, when a hotplug event is detected. + * Events can only be provided for connectors whose displayID is set + * by the system in the hotplugInterruptible field. + * hotplugPollable + * For _GET_HOTPLUG_CONFIG, this returns which connectors are pollable + * in some non-destructive fashion. + * hotplugInterruptible + * For _GET_HOTPLUG_CONFIG, this returns which connectors are capable + * of generating interrupts. + * + * This display mask specifies an NV0073_DISPLAY_MASK value describing + * the set of displays that have seen a hotplug or hotunplug event + * sometime after the last valid EDID read. If the device never has + * a valid EDID read, then it will always be listed here. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + + +#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_CONFIG (0x730123U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS_MESSAGE_ID (0x23U) + +typedef struct NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS { + NvU32 subDeviceInstance; + NvU32 flags; + NvU32 hotplugEventMask; + NvU32 hotplugPollable; + NvU32 hotplugInterruptible; + NvU32 hotplugAlwaysAttached; +} NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS; + + + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_HEAD_ROUTING_MAP + * + * This command can be used to retrieve the suggested head routing map + * for the specified display mask. A head routing map describes the + * suggested crtc (or head) assignments for each display in the specified + * mask. + * + * Up to MAX_DISPLAYS displays may be specified in the display mask. Displays + * are numbered from zero beginning with the lowest bit position set in the + * mask. The corresponding head assignment for each of specified displays can + * then be found in the respective per-device field in the routing map. + * + * If a particular display cannot be successfully assigned a position in the + * head routing map then it is removed from the display mask. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayMask + * This parameter specifies the NV0073_DISPLAY_MASK value for which + * the head routing map is desired. Each enabled bit indicates + * a display device to include in the routing map. Enabled bits + * must represent supported displays as indicated by the + * NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED command. If a particular + * display cannot be included in the routing map then it's corresponding + * bit in the displayMask will be disabled. A return value of 0 in + * displayMask indicates that a head routing map could not be constructed + * with the given display devices. + * oldDisplayMask + * This optional parameter specifies a prior display mask to be + * used when generating the head routing map to be returned in + * headRoutingMap. Displays set in oldDisplayMask are retained + * if possible in the new routing map. + * oldHeadRoutingMap + * This optional parameter specifies a prior head routing map to be + * used when generating the new routing map to be returned in + * headRoutingMap. Head assignments in oldHeadRoutingMap are + * retained if possible in the new routing map. + * headRoutingMap + * This parameter returns the new head routing map. This parameter + * is organized into eight distinct fields, each containing the head + * assignment for the corresponding display in display mask. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_HEAD_ROUTING_MAP (0x730125U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_HEAD_ROUTING_MAP_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_HEAD_ROUTING_MAP_PARAMS_MESSAGE_ID (0x25U) + +typedef struct NV0073_CTRL_SYSTEM_GET_HEAD_ROUTING_MAP_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayMask; + NvU32 oldDisplayMask; + NvU32 oldHeadRoutingMap; + NvU32 headRoutingMap; +} NV0073_CTRL_SYSTEM_GET_HEAD_ROUTING_MAP_PARAMS; + +/* maximum number of allowed displays in a routing map */ +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_MAX_DISPLAYS (8U) + +/* per-display head assignments in a routing map */ +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY0 3:0 +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY1 7:4 +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY2 11:8 +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY3 15:12 +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY4 19:16 +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY5 23:20 +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY6 27:24 +#define NV0073_CTRL_SYSTEM_HEAD_ROUTING_MAP_DISPLAY7 31:28 + + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_ACTIVE + * + * This command returns the active display ID for the specified head + * on the specified subdevice. The active display may be established + * at system boot by low-level software and can then be later modified + * by an NV client using a user display class instance (see + * NV15_VIDEO_LUT_CURSOR_DAC). + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * head + * This parameter specifies the head for which the active display + * should be retrieved. This value must be between zero and the + * maximum number of heads supported by the subdevice. + * flags + * This parameter specifies optional flags to be used to while retrieving + * the active display information. + * Possible valid flags are: + * NV0073_CTRL_SYSTEM_GET_ACTIVE_FLAGS_CLIENT + * This flag is used to limit the search for the active display to + * that established by an NV client. If this flag is not specified, + * then any active display is returned (setup at system boot by + * low-level software or later by an NV client). + * displayId + * This parameter returns the displayId of the active display. A value + * of zero indicates no display is active. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_ACTIVE (0x730126U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS_MESSAGE_ID (0x26U) + +typedef struct NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvU32 flags; + NvU32 displayId; +} NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS; + +/* valid get active flags */ +#define NV0073_CTRL_SYSTEM_GET_ACTIVE_FLAGS_CLIENT 0:0 +#define NV0073_CTRL_SYSTEM_GET_ACTIVE_FLAGS_CLIENT_DISABLE (0x00000000U) +#define NV0073_CTRL_SYSTEM_GET_ACTIVE_FLAGS_CLIENT_ENABLE (0x00000001U) + + + +/* + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP + * + * This structure defines the mapping between the RM's displayId and the + * defined ACPI IDs for each display. + * displayId + * This parameter is a handle to a single display output path from the + * GPU pins to the display connector. Each display ID is defined by one bit. + * A zero in this parameter indicates a skip entry. + * acpiId + * This parameter defines the corresponding ACPI ID of the displayId. + * flags + * This parameter specifies optional flags that describe the association + * between the display ID and the ACPI ID. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN + * This field describes where the ACPI was found. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_RM + * The ACPI ID was generated by RM code. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_DOD + * The ACPI ID was found via the ACPI _DOD call. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_CLIENT + * The ACPI ID was generated by RM Client and sent to RM. Note this + * must be set on a NV0073_CTRL_CMD_SYSTEM_SET_ACPI_ID_MAP call. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_UNDOCKED + * This flag explains that the ACPI ID is only valid when the system + * is undocked. If this flag is not set, the ACPI ID is valid always. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_DOCKED + * This flag explains that the ACPI ID is only valid when the system + * is docked. If this flag is not set, the ACPI ID is valid always. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_BIOS_DETECT + * This flag is set only if the _DOD returns that the device can be + * detected by the system BIOS. This flag is copied directly from + * the ACPI spec. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_NON_VGA_OUTPUT + * This flag is set only if the _DOD returns that the device is + * a non-VGA device whose power is related to the VGA device. + * i.e. TV tuner, DVD decoder, Video capture. This flag is copied + * directly from the ACPI spec. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_MULTIHEAD_ID + * This value is set only if the _DOD returns it. The number + * indicates the head output of a multi-head device. This has no + * relation to the term, Head, currently used in the RM today. + * This is strictly a copy of the value directly from the ACPI spec. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_SCHEME + * This flag is set only if the _DOD returns that the acpiID follows + * the ACPI 3.0 spec. This flag is copied directly from + * the ACPI spec. + * + */ + +typedef struct NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS { + NvU32 displayId; + NvU32 acpiId; + NvU32 flags; +} NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS; + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN 1:0 +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_RM 0x00000000U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_DOD 0x00000001U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_CLIENT 0x00000002U + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_UNDOCKED 2:2 +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_UNDOCKED_FALSE 0x00000000U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_UNDOCKED_TRUE 0x00000001U + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_DOCKED 3:3 +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_DOCKED_FALSE 0x00000000U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_DOCKED_TRUE 0x00000001U + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_BIOS_DETECT 16:16 +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_BIOS_DETECT_FALSE 0x00000000U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_BIOS_DETECT_TRUE 0x00000001U + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_NON_VGA_OUTPUT 17:17 +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_NON_VGA_OUTPUT_FALSE 0x00000000U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_NON_VGA_OUTPUT_TRUE 0x00000001U + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_MULTIHEAD_ID 20:18 + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_SCHEME 31:31 +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_SCHEME_VENDOR 0x00000000U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_SCHEME_30 0x00000001U + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS (16U) + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_ACPI_ID_MAP + * + * This command retrieves the mapping between the RM's displayId and the + * defined ACPI IDs for each display. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and + * the total number of subdevices within the parent device. It should + * be set to zero for default behavior. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS + * An array of display ID to ACPI ids with flags for each description. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * Only returned if subdeviceInstance was not valid. + */ + +#define NV0073_CTRL_CMD_SYSTEM_GET_ACPI_ID_MAP (0x73015aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS_MESSAGE_ID" */ + + +#define NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS_MESSAGE_ID (0x5AU) + +typedef struct NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS { + NvU32 subDeviceInstance; + NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS acpiIdMap[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS]; +} NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_INTERNAL_DISPLAYS + * + * This command returns the set of internal (safe) display IDs for the specified + * subdevice in the form of a 32bit display mask. Safe means the displays do + * not require copy protection as they are on the motherboard. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * internalDisplaysMask + * This parameter returns a NV0073_DISPLAY_MASK value describing the set + * of displays that are internal (safe) and which do not require copy + * protection schemes. + * availableInternalDisplaysMask + * This parameter returns a NV0073_DISPLAY_MASK value describing the set + * of displays that are internal and available for use. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_INTERNAL_DISPLAYS (0x73015bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS_MESSAGE_ID (0x5BU) + +typedef struct NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS { + NvU32 subDeviceInstance; + NvU32 internalDisplaysMask; + NvU32 availableInternalDisplaysMask; +} NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS; + + + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_BOOT_DISPLAYS + * + * This command returns a mask of boot display IDs. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * bootDisplayMask + * This parameter returns the mask of boot display IDs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_BOOT_DISPLAYS (0x730166U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS_MESSAGE_ID (0x66U) + +typedef struct NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS { + NvU32 subDeviceInstance; + NvU32 bootDisplayMask; +} NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS; + + + +/* + * NV0073_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD + * + * This command is used to execute general MXM ACPI methods. + * + * method + * This parameter identifies the MXM ACPI API to be invoked. + * Valid values for this parameter are: + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMI + * This value specifies that the MXMI API is to invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMS + * This value specifies that the MXMS API is to invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX + * This value specifies that the MXMX API is to invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUON + * This value specifies that the Hybrid GPU ON API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUOFF + * This value specifies that the Hybrid GPU OFF API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUSTA + * This value specifies that the Hybrid GPU STA API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS + * This value specifies that the Hybrid GPU MXDS API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX + * This value specifies that the Hybrid GPU MXMX API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS + * This value specifies that the Hybrid GPU DOS API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_ROM + * This value specifies that the Hybrid GPU ROM API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOD + * This value specifies that the Hybrid GPU DOD API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_SUPPORT + * This value specifies that the Hybrid GPU DSM subfunction SUPPORT + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HYBRIDCAPS + * This value specifies that the Hybrid GPU DSM subfunction SUPPORT + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POLICYSELECT + * This value specifies that the Hybrid GPU DSM subfunction POLICYSELECT + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POWERCONTROL + * This value specifies that the Hybrid GPU DSM subfunction POWERCONTROL + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_PLATPOLICY + * This value specifies that the Hybrid GPU DSM subfunction PLATPOLICY + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_DISPLAYSTATUS + * This value specifies that the Hybrid GPU DSM subfunction DISPLAYSTATUS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MDTL + * This value specifies that the Hybrid GPU DSM subfunction MDTL + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBLIST + * This value specifies that the Hybrid GPU DSM subfunction HCSMBLIST + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBADDR + * This value specifies that the Hybrid GPU DSM subfunction HCSMBADDR + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCREADBYTE + * This value specifies that the Hybrid GPU DSM subfunction HCREADBYTE + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSENDBYTE + * This value specifies that the Hybrid GPU DSM subfunction HCSENDBYTES + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETSTATUS + * This value specifies that the Hybrid GPU DSM subfunction HCGETSTATUS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCTRIGDDC + * This value specifies that the Hybrid GPU DSM subfunction HCTRIGDDC + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETDDC + * This value specifies that the Hybrid GPU DSM subfunction HCGETDDC + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DCS + * This value specifies that the Hybrid GPU DCS API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXSS + * This value specifies that the DSM MXM subfunction MXSS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMI + * This value specifies that the DSM MXM subfunction MXMI + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMS + * This value specifies that the DSM MXM subfunction MXMS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXPP + * This value specifies that the DSM MXM subfunction MXPP + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXDP + * This value specifies that the DSM MXM subfunction MXDP + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MDTL + * This value specifies that the DSM MXM subfunction MDTL + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXCB + * This value specifies that the DSM MXM subfunction MXCB + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_REMAPFUNC + * This value specifies the DSM generic remapping should return function + * and subfunction when this API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_HYBRIDCAPS + * This value specifies that the generic DSM subfunction HYBRIDCAPS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_POLICYSELECT + * This value specifies that the generic DSM subfunction POLICYSELECT + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_PLATPOLICY + * This value specifies that the generic DSM subfunction PLATPOLICY + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_DISPLAYSTATUS + * This value specifies that the generic DSM subfunction DISPLAYSTATUS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_MDTL + * This value specifies that the generic DSM subfunction MDTL + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETOBJBYTYPE + * This value specifies that the generic DSM subfunction GETOBJBYTYPE + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETALLOBJS + * This value specifies that the generic DSM subfunction GETALLOBJS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETEVENTLIST + * This value specifies that the generic DSM subfunction GETEVENTLIST + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETBACKLIGHT + * This value specifies that the generic DSM subfunction GETBACKLIGHT + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_TESTSUBFUNCENABLED + * This value specifies the testIfDsmSubFunctionEnabled test should + * be done for the func/subfunction when this API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_GETSUPPORTEDFUNC + * This value specifies the list of supported generic dsm functions + * should be returned. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS + * This value specifies that the DSM NVOP subfunction OPTIMUSCAPS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG + * This value specifies that the DSM NVOP subfunction OPTIMUSFLAG + * API is to be invoked. This API will set a Flag in sbios to Indicate + * that HD Audio Controller is disable/Enabled from GPU Config space. + * This flag will be used by sbios to restore Audio state after resuming + * from s3/s4. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_WMMX_NVOP_GPUON + * This value specifies that the WMMX (WMI-ACPI) GPON methods has to be invoked + * this call should happen below DPC level from any client. + * inData + * This parameter specifies the method-specific input buffer. Data is + * passed to the specified API using this buffer. For display related + * APIs the associated display mask can be found at a byte offset within + * the inData buffer using the following method-specific values: + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX_DISP_MASK_OFFSET + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS_DISP_MASK_OFFSET + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX_DISP_MASK_OFFSET + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS_DISP_MASK_OFFSET + * inDataSize + * This parameter specifies the size of the inData buffer in bytes. + * outStatus + * This parameter returns the status code from the associated ACPI call. + * outData + * This parameter specifies the method-specific output buffer. Data + * is returned by the specified API using this buffer. + * outDataSize + * This parameter specifies the size of the outData buffer in bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD (0x730168U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID (0x68U) + +typedef struct NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS { + NvU32 method; + NV_DECLARE_ALIGNED(NvP64 inData, 8); + NvU16 inDataSize; + NvU32 outStatus; + NV_DECLARE_ALIGNED(NvP64 outData, 8); + NvU16 outDataSize; +} NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS; + + +/* valid method parameter values */ +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX (0x00000002U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX_DISP_MASK_OFFSET (0x00000001U) + +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUON (0x00000003U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUOFF (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUSTA (0x00000005U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS (0x00000006U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX (0x00000007U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS (0x00000008U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_ROM (0x00000009U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOD (0x0000000aU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_SUPPORT (0x0000000bU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HYBRIDCAPS (0x0000000cU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POLICYSELECT (0x0000000dU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POWERCONTROL (0x0000000eU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_PLATPOLICY (0x0000000fU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_DISPLAYSTATUS (0x00000010U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MDTL (0x00000011U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBLIST (0x00000012U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBADDR (0x00000013U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCREADBYTE (0x00000014U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSENDBYTE (0x00000015U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETSTATUS (0x00000016U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCTRIGDDC (0x00000017U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETDDC (0x00000018U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DCS (0x00000019U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXSS (0x0000001aU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMI (0x0000001bU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMS (0x0000001cU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXPP (0x0000001dU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXDP (0x0000001eU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MDTL (0x0000001fU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXCB (0x00000020U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_GETEVENTLIST (0x00000021U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETMEMTABLE (0x00000022U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETMEMCFG (0x00000023U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETOBJBYTYPE (0x00000024U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETALLOBJS (0x00000025U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_REMAPFUNC (0x00000026U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_DISPLAYSTATUS (0x0000002aU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_MDTL (0x0000002bU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETOBJBYTYPE (0x0000002cU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETALLOBJS (0x0000002dU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETEVENTLIST (0x0000002eU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETBACKLIGHT (0x0000002fU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_TESTSUBFUNCENABLED (0x00000030U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_GETSUPPORTEDFUNC (0x00000031U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS (0x00000032U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_WMMX_NVOP_GPUON (0x00000033U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG (0x00000034U) + + +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETCALLBACKS (0x00000036U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_SUPPORTFUNCS (0x00000037U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_PLATCAPS (0x00000038U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_PLATPOLICY (0x00000039U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_MSTL (0x0000003aU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVGPS_FUNC_SUPPORT (0x0000003bU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDS (0x0000003cU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDM (0x0000003dU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXID (0x0000003eU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_LRST (0x0000003fU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DDC_EDID (0x00000040U) + +/* valid input buffer offset values */ +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDS_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDM_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXID_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_LRST_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DDC_EDID_DISP_MASK_OFFSET (0x00000004U) + + + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_UNPLUG_STATE + * + * This command can be used to retrieve hotplug and unplug state + * information that are currently recorded by the RM. This information is + * used by the client to determine which displays to detect after a + * hotplug event occurs. Or if the client knows that this device generates + * a hot plug/unplug signal on all connectors, then this can be used to call + * displays from detection. The displayIds on which hotplug/unplug has + * happened will be reported only ONCE to the client. That is if the call + * is done multiple times for the same event update, then for consequent + * calls the display mask will be reported as 0. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * flags + * This parameter specifies optional flags to be used while retrieving + * the hotplug state information. + * Here are the current defined fields: + * NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID + * A client uses this field to determine the lid state. + * Possible values are: + * NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID_OPEN + * The lid is open. + * NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID_CLOSED + * The lid is closed. The client should remove devices a + * reported inside the + * NV0073_CTRL_SYSTEM_GET_CONNECT_POLICY_PARAMS.lidClosedMask. + * hotPlugMask + * This display mask specifies an NV0073_DISPLAY_MASK value describing + * the set of displays that have seen a hotplug. + * hotUnplugMask + * This display mask specifies an NV0073_DISPLAY_MASK value describing + * the set of displays that have seen a hot unplug + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_UNPLUG_STATE (0x73017bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | 0x7B" */ + +typedef struct NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS { + NvU32 subDeviceInstance; + NvU32 flags; + NvU32 hotPlugMask; + NvU32 hotUnplugMask; +} NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS; + +/* valid get hoplug state flags */ +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_FLAGS_LID 0:0 +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_FLAGS_LID_OPEN (0x00000000U) +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_FLAGS_LID_CLOSED (0x00000001U) + +/* + * NV0073_CTRL_CMD_SYSTEM_CLEAR_ELV_BLOCK + * + * This command instructs the RM to explicitly clear any + * ELV block. Clients should call this before attempting core-channel + * updates when in VRR one-shot mode. ELV block mode will be + * properly restored to its appropriate setting based on the stall-lock + * in Supervisor3 after the core channel update + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * displayId + * The public ID of the Output Display which is to be used for VRR. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ + +#define NV0073_CTRL_CMD_SYSTEM_CLEAR_ELV_BLOCK (0x73017dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS_MESSAGE_ID (0x7DU) + +typedef struct NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; +} NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR + * + * This command arms the display modeset supervisor to operate in + * a lightweight mode. By calling this, the client is implicitly + * promising not to make any changes in the next modeset that require + * the full supervisor. After SV3, the LWSV will disarm and any subsequent + * modesets will revert to full supervisors. This must be called separately + * for every display that will be part of the modeset. + * It is recommended that the client explicitly disarm the lightweight + * supervisor after every modeset as null modesets will not trigger the + * supervisor interrupts and the RM will not be able to disarm automatically + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * displayId + * The public ID of the Output Display which is to be used for VRR. + * + * bArmLWSV + * If this is set to NV_TRUE, the RM will arm the lightweight supervisor + * for the next modeset. + * If this is set to NV_FALSE, the RM will disarm the lightweight supervisor + * + * bVrrState + * VRR state to be changed. + * + * vActive + * GPU-SRC vertical active value + * + * vfp + * GPU-SRC vertical front porch + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ + +#define NV0073_CTRL_CMD_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR (0x73017eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR_PARAMS_MESSAGE_ID (0x7EU) + +typedef struct NV0073_CTRL_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bArmLWSV; + NvBool bVrrState; + NvU32 vActive; + NvU32 vfp; +} NV0073_CTRL_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR_PARAMS; + + + +/* +* NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS +* +* This command is used to configure pstate switch parameters on VRR monitors +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed.This parameter must specify a value between zero and the +* total number of subdevices within the parent device.This parameter +* should be set to zero for default behavior. +* +* displayId +* DisplayId of the monitor being vrr configured +* +* bVrrState +* When set to NV_TRUE, signifies that the vrr is about to become active. +* When set to NV_FALSE, signifies that the vrr is about to become suspended. +* +* bVrrDirty +* When set to NV_TRUE, indicates that vrr configuration has been changed +* When set to NV_FALSE, this will indicate transitions from One shot mode to +* Continuous mode and vice versa +* +* bVrrEnabled +* When set to NV_TRUE, indicates that vrr has been enabled, i.e. vBp extended by 2 lines +* +* maxVblankExtension +* When VRR is enabled, this is the maximum amount of lines that the vblank can be extended. +* Only updated when bVrrDirty = true +* +* internalVRRHeadVblankStretch +* When VRR is enabled, this is the maximum amount of lines that the vblank can be extended. +* On NVSR and DD panels . Only updated when bVrrDirty = true +* +* minVblankExtension +* When VRR is enabled, this is the minimum amount of lines that should be present in the Vblank. The purpose is to cap the maximum refresh (currently only for HDMI 2.1 VRR compliance) +*/ +#define NV0073_CTRL_CMD_SYSTEM_CONFIG_VRR_PSTATE_SWITCH (0x730184U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS_MESSAGE_ID (0x84U) + +typedef struct NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bVrrState; + NvBool bVrrDirty; + NvBool bVrrEnabled; + NvU32 maxVblankExtension; + NvU32 internalVRRHeadVblankStretch; + NvU32 minVblankExtension; +} NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS; + + + +/* + * NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX + * + * This command is used to query the display mask of all displays + * that support dynamic display MUX. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * displayMask (out) + * Mask of all displays that support dynamic display MUX + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX (0x730190U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS_MESSAGE_ID (0x90U) + +typedef struct NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS { + NvU32 subDeviceInstance; + NvU32 muxDisplayMask; +} NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS; + + + +/* + * NV0073_CTRL_CMD_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH + * + * This command allocates a specified amount of ISO memory bandwidth for + * display. If the requested amount of bandwidth cannot be allocated (either + * because it exceeds the total bandwidth available to the system, or because + * too much bandwidth is already allocated to other clients), the call will + * fail and NV_ERR_INSUFFICIENT_RESOURCES will be returned. + * + * If bandwidth has already been allocated via a prior call, and a new + * allocation is requested, the new allocation will replace the old one. (If + * the new allocation fails, the old allocation remains in effect.) + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * averageBandwidthKBPS + * This parameter specifies the amount of ISO memory bandwidth requested. + * floorBandwidthKBPS + * This parameter specifies the minimum required (i.e., floor) dramclk + * frequency, multiplied by the width of the pipe over which the display + * data will travel. (It is understood that the bandwidth calculated by + * multiplying the clock frequency by the pipe width will not be + * realistically achievable, due to overhead in the memory subsystem. The + * API will not actually use the bandwidth value, except to reverse the + * calculation to get the required dramclk frequency.) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INSUFFICIENT_RESOURCES + * NV_ERR_NOT_SUPPORTED + * NV_ERR_GENERIC + */ + +#define NV0073_CTRL_CMD_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH (0x730196U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_MESSAGE_ID (0x96U) + +typedef struct NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS { + NvU32 subDeviceInstance; + NvU32 averageBandwidthKBPS; + NvU32 floorBandwidthKBPS; +} NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS; + +/* + * NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS + * + * This structure represents the hotplug event config control parameters. + * + * subDeviceInstance + * This parameter should specify the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * + * deviceMapFilter + * This parameter returns (in GET) or should specify (in SET) a device map + * indicating device(s) to sense. + * + * hotPluginSense + * This parameter returns (in GET) or should specify (in SET) a device map + * indicating device(s) plugged in that caused the most recent hotplug + * event. + * + * hotUnplugSense + * This parameter returns (in GET) or should specify (in SET) a device map + * indicating device(s) un plugged that caused the most recent hotplug + * event. + */ + +typedef struct NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS { + NvU32 subDeviceInstance; + NvU32 deviceMapFilter; + NvU32 hotPluginSense; + NvU32 hotUnplugSense; +} NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_EVENT_CONFIG + * + * This command fetches the hotplug event configuration. + * + * See @ref NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS for documentation on + * the parameters. + */ + +#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_EVENT_CONFIG (0x730197U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | 0x97" */ + +/* + * NV0073_CTRL_CMD_SYSTEM_SET_HOTPLUG_EVENT_CONFIG + * + * This command sets the hotplug event configuration. + * + * See @ref NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS for documentation on + * the parameters. + */ + +#define NV0073_CTRL_CMD_SYSTEM_SET_HOTPLUG_EVENT_CONFIG (0x730198U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | 0x98" */ + + + +/* +* NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS +* +* This command is used to read Core channel, Cursor channel, Window channel, and Head register values and encode these values with ProtoDmp. +* +* subDeviceInstance (in) +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed. +* headMask (in) +* Head mask representing which register values should be encoded +* windowMask (in) +* Window channel mask whose register values should be encoded +* bRecordCoreChannel (in) +* Indicates whether or not to encode core channel register values +* bRecordCursorChannel (in) +* Indicates whether or not to encode cursor channel register values +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_ARGUMENT +* NV_ERR_NOT_SUPPORTED +*/ +#define NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS (0x73019bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS_MESSAGE_ID (0x9BU) + +typedef struct NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS { + NvU32 subDeviceInstance; + NvU32 headMask; + NvU32 windowMask; + NvBool bRecordCoreChannel; + NvBool bRecordCursorChannel; +} NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT + * + * This command is used to query the display mux status for the given + * display device + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT (0x73019cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS_MESSAGE_ID (0x9CU) + +typedef struct NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS { + NvU32 subDeviceInstance; + NvBool bIsSidebandI2cSupported; +} NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS; + +/* + * NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT + * + * This command is used to query if SIDEBAND SR can be used with the + * given display device. If PSR API is supported on the system, + * then sideband SR support is set to false. + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation + * should be directed. + * displayId (in) + * This parameter inputs the displayId of the active display. A value + * of zero indicates no display is active. + * bIsSidebandSrSupported + * If it is true, it means that sideband is supported and not PSR API. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT (0x73019dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS_MESSAGE_ID (0x9DU) + +typedef struct NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bIsSidebandSrSupported; +} NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS; + +/* _ctrl0073system_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080.h new file mode 100644 index 0000000..238c0d6 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080.finn +// + + + + +#include "ctrl0080/ctrl0080bif.h" +#include "ctrl0080/ctrl0080gpu.h" +#include "ctrl0080/ctrl0080clk.h" +#include "ctrl0080/ctrl0080dma.h" +#include "ctrl0080/ctrl0080gr.h" +#include "ctrl0080/ctrl0080cipher.h" +#include "ctrl0080/ctrl0080fb.h" +#include "ctrl0080/ctrl0080fifo.h" +#include "ctrl0080/ctrl0080host.h" + + +#include "ctrl0080/ctrl0080perf.h" +#include "ctrl0080/ctrl0080msenc.h" +#include "ctrl0080/ctrl0080bsp.h" +#include "ctrl0080/ctrl0080rc.h" +#include "ctrl0080/ctrl0080nvjpg.h" +#include "ctrl0080/ctrl0080unix.h" +#include "ctrl0080/ctrl0080internal.h" diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h new file mode 100644 index 0000000..4b20dc1 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h @@ -0,0 +1,73 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080base.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV01_DEVICE_XX/NV03_DEVICE control commands and parameters */ + +#define NV0080_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0080, NV0080_CTRL_##cat, idx) + +/* GPU device command categories (6bits) */ +#define NV0080_CTRL_RESERVED (0x00) +#define NV0080_CTRL_BIF (0x01) +#define NV0080_CTRL_GPU (0x02) +#define NV0080_CTRL_CLK (0x10) +#define NV0080_CTRL_GR (0x11) +#define NV0080_CTRL_CIPHER (0x12) +#define NV0080_CTRL_FB (0x13) +#define NV0080_CTRL_HOST (0x14) +#define NV0080_CTRL_VIDEO (0x15) +#define NV0080_CTRL_FIFO (0x17) +#define NV0080_CTRL_DMA (0x18) +#define NV0080_CTRL_PERF (0x19) +#define NV0080_CTRL_PERF_LEGACY_NON_PRIVILEGED (0x99) /* finn: Evaluated from "(NV0080_CTRL_PERF | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV0080_CTRL_MSENC (0x1B) +#define NV0080_CTRL_BSP (0x1C) +#define NV0080_CTRL_RC (0x1D) +#define NV0080_CTRL_OS_UNIX (0x1E) +#define NV0080_CTRL_NVJPG (0x1F) +#define NV0080_CTRL_INTERNAL (0x20) +#define NV0080_CTRL_NVLINK (0x21) + +/* + * NV0080_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0080_CTRL_CMD_NULL (0x800000) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrl0080base_h_ */ + +/* extract device cap setting from specified category-specific caps table */ +#define NV0080_CTRL_GET_CAP(cat,tbl,c) \ + NV0080_CTRL_##cat##_GET_CAP(tbl, NV0080_CTRL_##cat##_CAPS_##c) diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h new file mode 100644 index 0000000..05a18bf --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h @@ -0,0 +1,138 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080bif.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* + * NV0080_CTRL_CMD_BIF_RESET + * + * This command initiates the specified reset type on the GPU. + * + * flags + * Specifies various arguments to the reset operation. + * + * Supported fields include: + * + * NV0080_CTRL_BIF_RESET_FLAGS_TYPE + * When set to _SW_RESET, a SW (fullchip) reset is performed. When set + * to _SBR, a secondary-bus reset is performed. When set to + * _FUNDAMENTAL, a fundamental reset is performed. + * + * NOTE: _FUNDAMENTAL is not yet supported. + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0080_CTRL_CMD_BIF_RESET (0x800102) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_RESET_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_BIF_RESET_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_BIF_RESET_PARAMS { + NvU32 flags; +} NV0080_CTRL_BIF_RESET_PARAMS; + +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE 2:0 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SW_RESET (0x00000001) +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SBR (0x00000002) +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_FUNDAMENTAL (0x00000003) + +/* + * NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR + * + * baseDmaSysmemAddr + * This parameter represents the base DMA address for sysmem which will be + * added to all DMA accesses issued by GPU. Currently GPUs do not support 64-bit physical address, + * hence if sysmem is greater than max GPU supported physical address width, this address + * will be non-zero + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_PARENT + */ + +#define NV0080_CTRL_CMD_BIF_GET_DMA_BASE_SYSMEM_ADDR (0x800103) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS { + NV_DECLARE_ALIGNED(NvU64 baseDmaSysmemAddr, 8); +} NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS; + +/* + * NV0080_CTRL_BIF_SET_ASPM_FEATURE + * + * aspmFeatureSupported + * ASPM feature override by client + * + * Possible status values returned are: + * NV_OK + */ + +#define NV0080_CTRL_CMD_BIF_SET_ASPM_FEATURE (0x800104) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS { + NvU32 aspmFeatureSupported; +} NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS; + +#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S 0:0 +#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_ENABLED 0x000000001 +#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_DISABLED 0x000000000 +#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1 1:1 +#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_ENABLED 0x000000001 +#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_DISABLED 0x000000000 + +/* + * NV0080_CTRL_BIF_ASPM_CYA_UPDATE + * + * bL0sEnable + * bL1Enable + * ASPM CYA update by client + * + * Possible status values returned are: + * NV_OK + */ + +#define NV0080_CTRL_CMD_BIF_ASPM_CYA_UPDATE (0x800105) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS { + NvBool bL0sEnable; + NvBool bL1Enable; +} NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS; + +/* _ctrl0080bif_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h new file mode 100644 index 0000000..d4911f5 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h @@ -0,0 +1,112 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080bsp.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE bit stream processor control commands and parameters */ + +/* + * NV0080_CTRL_CMD_BSP_GET_CAPS + * + * This command returns the set of BSP capabilities for the device + * in the form of an array of unsigned bytes. BSP capabilities + * include supported features and required workarounds for the decoder + * within the device, each represented by a byte offset into the + * table and a bit position within that byte. + * + * capsTblSize + * This parameter specifies the size in bytes of the caps table. + * This value should be set to NV0080_CTRL_BSP_CAPS_TBL_SIZE. + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the BSP caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + * instanceId + * This parameter specifies the instance Id of NVDEC for which + * cap bits are requested. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0080_CTRL_CMD_BSP_GET_CAPS (0x801c01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BSP_INTERFACE_ID << 8) | NV0080_CTRL_BSP_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_BSP_GET_CAPS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0080_CTRL_BSP_GET_CAPS_PARAMS { + NvU32 capsTblSize; + NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); + NvU32 instanceId; +} NV0080_CTRL_BSP_GET_CAPS_PARAMS; + + + +/* + * Size in bytes of bsp caps table. This value should be one greater + * than the largest byte_index value above. + */ +#define NV0080_CTRL_BSP_CAPS_TBL_SIZE 8 + +/* + * NV0080_CTRL_CMD_BSP_GET_CAPS_V2 + * + * This command returns the set of BSP capabilities for the device + * in the form of an array of unsigned bytes. BSP capabilities + * include supported features and required workarounds for the decoder + * within the device, each represented by a byte offset into the + * table and a bit position within that byte. + * (The V2 version flattens the capsTbl array pointer). + * + * capsTbl + * This parameter is an array of unsigned bytes where the BSP caps bits + * will be transferred by the RM. + * instanceId + * This parameter specifies the instance Id of NVDEC for which + * cap bits are requested. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0080_CTRL_CMD_BSP_GET_CAPS_V2 (0x801c02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BSP_INTERFACE_ID << 8) | NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2_MESSAGE_ID" */ + +#define NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2 { + NvU8 capsTbl[NV0080_CTRL_BSP_CAPS_TBL_SIZE]; + NvU32 instanceId; +} NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2; + +/* _ctrl0080bsp_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080cipher.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080cipher.h new file mode 100644 index 0000000..279151b --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080cipher.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080cipher.finn +// + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080clk.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080clk.h new file mode 100644 index 0000000..de61930 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080clk.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080clk.finn +// + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h new file mode 100644 index 0000000..b209ca2 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h @@ -0,0 +1,908 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080dma.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE dma control commands and parameters */ + +/* + * NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK + * + * This parameter returns the parameters specific to a PTE as follows: + * pageSize + * GET: This parameter returns the page size of the PTE information + * being returned. If 0, then this pteBlock[] array entry is + * invalid or not used. (pteBlock[0] is always used.) + * SET: This parameter specifies the page size of the PTE information + * to be set. If 0, then this pteBlock[] array entry is invalid + * or not used. (pteBlock[0] is always used.) + * pteEntrySize + * GET: This parameter returns the size of the PTE in bytes for this GPU. + * SET: N/A + * comptagLine + * GET: This parameter returns the comptagline field of the corresponding PTE. + * SET: This parameter sets the comptagline field of the corresponding PTE. + * Incorrect values may lead to dire consequences. + * kind + * GET: This parameter returns the kind field of the corresponding PTE. + * SET: This parameter sets the kind field of the corresponding PTE. + * Incorrect values may lead to undesirable consequences. + * pteFlags + * This parameter returns various fields from the PTE, these are: + * FLAGS_VALID: + * GET: This flag returns the valid bit of the PTE. + * SET: This flag sets the valid bit of the PTE. + * FLAGS_ENCRYPTED: + * GET: This flag returns the encrypted bit of the PTE. Not all GPUs + * support encryption. If not supported, this flag will be set to + * NOT_SUPPORTED. + * SET: This flag sets the encrypted bit of the PTE. + * FLAGS_APERTURE: + * GET: This flag returns the aperture field of the PTE. See + * NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_FLAGS_APERTURE_* for values. + * SET: This flag sets the aperture field of the PTE. See + * NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_FLAGS_APERTURE_* for values. + * FLAGS_COMPTAGS: + * GET: This flag returns the comptags field of the PTE. (Not used on Fermi) + * SET: N/A + * FLAGS_GPU_CACHED: + * GET: This flag returns the GPU cacheable bit of the PTE. GPU caching of + * sysmem was added in iGT21a and Fermi. If not supported, this flag + * will be set to NOT_SUPPORTED. + * SET: N/A for specific chips, e.g., GF100 + * FLAGS_SHADER_ACCESS: + * GET: This flag returns the shader access control of the PTE. This feature + * was introduced in Kepler. If not supported, this flag will be set to + * NOT_SUPPORTED. + * SET: N/A + */ + +typedef struct NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK { + NvU32 pageSize; + NV_DECLARE_ALIGNED(NvU64 pteEntrySize, 8); + NvU32 comptagLine; + NvU32 kind; + NvU32 pteFlags; +} NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK; + +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID 0:0 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_TRUE (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED 2:1 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_TRUE (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_NOT_SUPPORTED (0x00000002U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE 6:3 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_VIDEO_MEMORY (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_PEER_MEMORY (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_COHERENT_MEMORY (0x00000002U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_NON_COHERENT_MEMORY (0x00000003U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS 10:7 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_NONE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_1 (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_2 (0x00000002U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_4 (0x00000004U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED 12:11 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_TRUE (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_NOT_SUPPORTED (0x00000002U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS 14:13 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_WRITE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_ONLY (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_WRITE_ONLY (0x00000002U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_NOT_SUPPORTED (0x00000003U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY 15:15 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_TRUE (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC 16:16 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_DISABLE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_ENABLE (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING 17:17 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_DISABLE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_ENABLE (0x00000001U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED 18:18 +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_TRUE (0x00000001U) + +/* + * NV0080_CTRL_DMA_GET_PTE_INFO + * + * This command queries PTE information for the specified GPU virtual address. + * + * gpuAddr + * This parameter specifies the GPU virtual address for which PTE + * information is to be returned. + * skipVASpaceInit + * This parameter specifies(true/false) whether the VA Space + * initialization should be skipped in this ctrl call. + * pteBlocks + * This parameter returns the page size-specific attributes of a PTE. + * Please see NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK. + * hVASpace + * handle for the allocated VA space that this control call should operate + * on. If it's 0, it assumes to use the implicit allocated VA space. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + * NV_ERR_GENERIC + */ + +#define NV0080_CTRL_CMD_DMA_GET_PTE_INFO (0x801801U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS 4U + +#define NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 gpuAddr, 8); + NvU32 subDeviceId; + NvU8 skipVASpaceInit; + NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK pteBlocks[NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS], 8); + NvHandle hVASpace; +} NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS; + +/* + * NV0080_CTRL_DMA_SET_PTE_INFO + * + * This command sets PTE information for the specified GPU virtual address. + * Usage of parameter and field definitions is identical to that of + * NV0080_CTRL_DMA_GET_PTE_INFO, with the following exception: + * + * - pteFlags field NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS is ignored, + * as this setting is specified via the kind specification. + * - pteEntrySize is ignored, as this setting is read-only in the GET case. + * - hVASpace + * handle for the allocated VA space that this control call should operate + * on. If it's 0, it assumes to use the implicit allocated VA space. + * + */ + +#define NV0080_CTRL_CMD_DMA_SET_PTE_INFO (0x80180aU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS 4U + +#define NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 gpuAddr, 8); + NvU32 subDeviceId; + NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK pteBlocks[NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS], 8); + NvHandle hVASpace; +} NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS; + + +#define NV0080_CTRL_CMD_DMA_FILL_PTE_MEM (0x801802U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS { + NvU32 pageCount; + struct { + NvHandle hClient; + NvHandle hDevice; + NvHandle hMemory; + NvU32 subDeviceId; + } hwResource; + struct { + NvU32 fbKind; + NvU32 sysKind; + NvU32 compTagStartOffset; + } comprInfo; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 gpuAddr, 8); + NV_DECLARE_ALIGNED(NvP64 pageArray, 8); + NV_DECLARE_ALIGNED(NvP64 pteMem, 8); + NvU32 pteMemPfn; + NvU32 pageSize; + NvU32 startPageIndex; + NvU32 flags; + NvHandle hSrcVASpace; + NvHandle hTgtVASpace; + NvU32 peerId; +} NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS; + + + +/* + * NV0080_CTRL_DMA_FLUSH + * + * This command flushes the specified target unit + * + * targetUnit + * The unit to flush, either L2 cache or compression tag cache. + * This field is a logical OR of the individual fields such as + * L2 cache or compression tag cache. Also L2 invalidation for + * either SYSMEM/PEERMEM is triggered. But this invalidation is + * for FERMI. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + * + * See Also: + * NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE + * Flushes the entire GPU cache or a set of physical addresses (if the + * hardware supports it). Use this call if you want to flush a set of + * addresses or the entire GPU cache in unicast mode. + * NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE + * Flushes memory associated with a single allocation if the hardware + * supports it. Use this call if you want to flush a single allocation and + * you have a memory object describing the physical memory. + */ +#define NV0080_CTRL_CMD_DMA_FLUSH (0x801805U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_FLUSH_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_FLUSH_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0080_CTRL_DMA_FLUSH_PARAMS { + NvU32 targetUnit; +} NV0080_CTRL_DMA_FLUSH_PARAMS; + +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2 0:0 +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_DISABLE (0x00000000U) +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_ENABLE (0x00000001U) +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG 1:1 +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_DISABLE (0x00000000U) +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_ENABLE (0x00000001U) +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB 2:2 +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_DISABLE (0x00000000U) +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_ENABLE (0x00000001U) + +// This is exclusively for Fermi +// The selection of non-zero valued bit-fields avoids the routing +// into the above cases and vice-versa +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE 4:3 +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_SYSMEM (0x00000001U) +#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_PEERMEM (0x00000002U) + + +/** + * NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS + * + * This command returns information about the VA caps on the GPU + * + * vaBitCount + * Returns number of bits in a virtual address + * pdeCoverageBitCount + * Returns number of VA bits covered in each PDE. One PDE covers + * 2^pdeCoverageBitCount bytes. + * + * bigPageSize + * Size of the big page + * compressionPageSize + * Size of region each compression tag covers + * dualPageTableSupported + * TRUE if one page table can map with both 4KB and big pages + * + * numPageTableFormats + * Returns the number of different page table sizes supported by the RM + * pageTableBigFormat + * pageTable4KFormat[] + * Returns size in bytes and number of VA bits covered by each page table + * format. Up to MAX_NUM_PAGE_TABLE_FORMATS can be returned. The most + * compact format will be pageTableSize[0] and the least compact format + * will be last. + * hVASpace + * handle for the allocated VA space that this control call should operate + * on. If it's 0, it assumes to use the implicit allocated VA space. + * vaRangeLo + * Indicates the start of usable VA range. + * + * hugePageSize + * Size of the huge page if supported, 0 otherwise. + * + * vaSpaceId + * Virtual Address Space id assigned by RM. + * Only relevant on AMODEL. + * + * pageSize512MB + * Size of the 512MB page if supported, 0 otherwise. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS (0x801806U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_MESSAGE_ID" */ + +typedef struct NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT { + NvU32 pageTableSize; + NvU32 pageTableCoverage; +} NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT; + +#define NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS (16U) +#define NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS { + NvU32 vaBitCount; + NvU32 pdeCoverageBitCount; + NvU32 num4KPageTableFormats; + NvU32 bigPageSize; + NvU32 compressionPageSize; + NvU32 dualPageTableSupported; + NvU32 idealVRAMPageSize; + NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT pageTableBigFormat; + NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT pageTable4KFormat[NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS]; + NvHandle hVASpace; + NV_DECLARE_ALIGNED(NvU64 vaRangeLo, 8); + NvU32 hugePageSize; + NvU32 vaSpaceId; + NvU32 pageSize512MB; +} NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS; + +/* + * Adding a version define to allow clients to access valid + * parameters based on version. + */ +#define NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS_WITH_VA_RANGE_LO 0x1U + +/* + * NV0080_CTRL_DMA_GET_PDE_INFO + * + * This command queries PDE information for the specified GPU virtual address. + * + * gpuAddr + * This parameter specifies the GPU virtual address for which PDE + * information is to be returned. + * pdeVirtAddr + * This parameter returns the GPU virtual address of the PDE. + * pdeEntrySize + * This parameter returns the size of the PDE in bytes for this GPU. + * pdeAddrSpace + * This parameter returns the GPU address space of the PDE. + * pdeSize + * This parameter returns the fractional size of the page table(s) as + * actually set in the PDE, FULL, 1/2, 1/4 or 1/8. (This amount may + * differ from that derived from pdeVASpaceSize.) Intended for VERIF only. + * pteBlocks + * This parameter returns the page size-specific parameters as follows: + * ptePhysAddr + * This parameter returns the GPU physical address of the page table. + * pteCacheAttrib + * This parameter returns the caching attribute of the + * GPU physical address of the page table. + * pteEntrySize + * This parameter returns the size of the PTE in bytes for this GPU. + * pageSize + * This parameter returns the page size of the page table. + * If pageSize == 0, then this PTE block is not valid. + * pteAddrSpace + * This parameter returns the GPU address space of the page table. + * pdeVASpaceSize + * This parameter returns the size of the VA space addressable by + * the page table if fully used (i.e., if all PTEs marked VALID). + * pdbAddr + * This parameter returns the PDB address for the PDE. + * hVASpace + * handle for the allocated VA space that this control call should operate + * on. If it's 0, it assumes to use the implicit allocated VA space. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV0080_CTRL_CMD_DMA_GET_PDE_INFO (0x801809U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_MESSAGE_ID" */ + +typedef struct NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK { + NV_DECLARE_ALIGNED(NvU64 ptePhysAddr, 8); + NvU32 pteCacheAttrib; + NvU32 pteEntrySize; + NvU32 pageSize; + NvU32 pteAddrSpace; + NvU32 pdeVASpaceSize; + NvU32 pdeFlags; +} NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK; + +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_VIDEO_MEMORY (0x00000000U) +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY (0x00000001U) +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY (0x00000002U) + +#define NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS 4U + +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 gpuAddr, 8); + NV_DECLARE_ALIGNED(NvU64 pdeVirtAddr, 8); + NvU32 pdeEntrySize; + NvU32 pdeAddrSpace; + NvU32 pdeSize; + NvU32 subDeviceId; + NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK pteBlocks[NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS], 8); + NV_DECLARE_ALIGNED(NvU64 pdbAddr, 8); + NvHandle hVASpace; +} NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS; + +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_VIDEO_MEMORY (0x00000000U) +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY (0x00000001U) +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY (0x00000002U) +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_FULL 1U +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_HALF 2U +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_QUARTER 3U +#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_EIGHTH 4U + +/* + * NV0080_CTRL_CMD_DMA_INVALIDATE_PDB_TARGET + * + * This command invalidates PDB target setting in hardware. + * After execeution of this command PDB target would be in undefined state. + * + * Returns error if the PDB target can not be invalidate. + * + * This call is only supported on chips fermi and later chips. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0080_CTRL_CMD_DMA_INVALIDATE_PDB_TARGET (0x80180bU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | 0xB" */ + +/* + * NV0080_CTRL_CMD_DMA_INVALIDATE_TLB + * + * This command invalidates the GPU TLB. This is intended to be used + * for RM clients that manage their own TLB consistency when updating + * page tables on their own, or with DEFER_TLB_INVALIDATION options + * to other RM APIs. + * + * hVASpace + * This parameter specifies the VASpace object whose MMU TLB entries + * needs to be invalidated, if the flag is set to NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_FALSE. + * Specifying a GMMU VASpace object handle will invalidate the GMMU TLB for the particular VASpace. + * Specifying a SMMU VASpace object handle will flush the entire SMMU TLB & PTC. + * + * flags + * This parameter can be used to specify any flags needed + * for the invlalidation request. + * NV0080_CTRL_DMA_INVALIDATE_TLB_ALL + * When set to TRUE this flag requests a global invalidate. + * When set to FALSE this flag requests a chip-specfic + * optimization to invalidate only the address space bound + * to the associated hDevice. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_TIMEOUT_RETRY + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0080_CTRL_CMD_DMA_INVALIDATE_TLB (0x80180cU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS { + NvHandle hVASpace; + NvU32 flags; +} NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS; + +#define NV0080_CTRL_DMA_INVALIDATE_TLB_ALL 0:0 +#define NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_TRUE (0x00000001U) + +/** + * NV0080_CTRL_CMD_DMA_GET_CAPS + * + * This command returns the set of DMA capabilities for the device + * in the form of an array of unsigned bytes. DMA capabilities + * include supported features and required workarounds for address + * translation system within the device, each represented by a byte + * offset into the table and a bit position within that byte. + * + * capsTblSize + * This parameter specifies the size in bytes of the caps table. + * This value should be set to NV0080_CTRL_DMA_CAPS_TBL_SIZE. + * + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the framebuffer caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + * + * 32BIT_POINTER_ENFORCED + * If this property is TRUE NVOS32 and NVOS46 calls with + * 32BIT_POINTER_DISABLED will return addresses above 4GB. + * + * SHADER_ACCESS_SUPPORTED + * If this property is set, the MMU in the system supports the independent + * access bits for the shader. This is accessed with the following fields: + * NVOS46_FLAGS_SHADER_ACCESS + * NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_FLAGS_SHADER_ACCESS + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_DMA_GET_CAPS (0x80180dU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_GET_CAPS_PARAMS_MESSAGE_ID" */ +/* size in bytes of fb caps table */ +#define NV0080_CTRL_DMA_CAPS_TBL_SIZE 8U +#define NV0080_CTRL_DMA_GET_CAPS_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV0080_CTRL_DMA_GET_CAPS_PARAMS { + NvU32 capsTblSize; + NvU8 capsTbl[NV0080_CTRL_DMA_CAPS_TBL_SIZE]; +} NV0080_CTRL_DMA_GET_CAPS_PARAMS; + +/* extract cap bit setting from tbl */ +#define NV0080_CTRL_DMA_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* caps format is byte_index:bit_mask */ +#define NV0080_CTRL_DMA_CAPS_32BIT_POINTER_ENFORCED 0:0x01 +#define NV0080_CTRL_DMA_CAPS_SHADER_ACCESS_SUPPORTED 0:0x04 +#define NV0080_CTRL_DMA_CAPS_SPARSE_VIRTUAL_SUPPORTED 0:0x08 +#define NV0080_CTRL_DMA_CAPS_MULTIPLE_VA_SPACES_SUPPORTED 0:0x10 + +/* + * NV0080_CTRL_DMA_SET_VA_SPACE_SIZE + * + * Change the size of an existing VA space. + * NOTE: Currently this only supports growing the size, not shrinking. + * + * 1. Allocate new page directory able to map extended range. + * 2. Copy existing PDEs from old directory to new directory. + * 3. Initialize new PDEs to invalid. + * 4. Update instmem to point to new page directory. + * 5. Free old page directory. + * + * vaSpaceSize + * On input, the requested size of the VA space in bytes. + * On output, the actual resulting VA space size. + * + * The actual size will be greater than or equal to the requested size, + * unless NV0080_CTRL_DMA_GROW_VA_SPACE_SIZE_MAX is requested, which + * requests the maximum available. + * + * NOTE: Specific size requests (e.g. other than SIZE_MAX) must account + * for the VA hole at the beginning of the range which is used to + * distinguish NULL pointers. This region is not counted as part + * of the vaSpaceSize since it is not allocatable. + * + * hVASpace + * handle for the allocated VA space that this control call should operate + * on. If it's 0, it assumes to use the implicit allocated VA space + * associated with the client/device pair. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_RESOURCES + */ +#define NV0080_CTRL_CMD_DMA_SET_VA_SPACE_SIZE (0x80180eU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 vaSpaceSize, 8); + NvHandle hVASpace; +} NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS; + +#define NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_MAX (0xFFFFFFFFFFFFFFFFULL) + +/* + * NV0080_CTRL_DMA_UPDATE_PDE_2 + * + * This command updates a single PDE for the given (hClient, hDevice) + * with specific attributes. + * This command is only available on Windows and MODS platforms. + * This command can be called by kernel clients only. + * + * The VA range the PDE maps must be contained by a VA allocation marked with + * NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED. + * However if the MODS-only FORCE_OVERRIDE flag is set this restriction is relaxed. + * + * RM does not track the PDE's attributes in SW - this control simply stuffs + * the PDE in memory after translating and checking the parameters. + * + * Parameters are checked for relative consistency (e.g. valid domains), + * but it is the client's responsibility to provide correct page table + * addresses, e.g. global consistency is not checked. + * + * It is also the client's responsibility to flush/invalidate the MMU + * when appropriate, either by setting the _FLUSH_PDE_CACHE flag for this + * call or by flushing through other APIs. + * This control does not flush automatically to allow batches of calls + * to be made before a single flush. + * + * ptParams + * Page-size-specific parameters, as follows: + * + * physAddr + * Base address of physically contiguous memory of page table. + * Must be aligned sufficiently for the PDE address field. + * numEntries + * Deprecated and ignored. + * Use FLAGS_PDE_SIZE that applies to the tables for all page sizes. + * aperture + * Address space the base address applies to. + * Can be left as INVALID to ignore this page table size. + * + * pdeIndex + * The PDE index this update applies to. + * flags + * See NV0080_CTRL_DMA_UPDATE_PDE_FLAGS_*. + * hVASpace + * handle for the allocated VA space that this control call should operate + * on. If it's 0, it assumes to use the implicit allocated VA space + * associated with the client/device pair. + * pPdeBuffer [out] + * Kernel pointer to 64 bit unsigned integer representing a Page Dir Entry + * that needs to be updated. It should point to memory as wide as the Page Dir + * Entry. + * + * If NULL, Page Dir Entry updates will go to the internally managed Page Dir. + * If not NULL, the updates will be written to this buffer. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_NOT_SUPPORTED + */ +#define NV0080_CTRL_CMD_DMA_UPDATE_PDE_2 (0x80180fU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_MESSAGE_ID" */ + +typedef struct NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 physAddr, 8); + NvU32 numEntries; // deprecated + NvU32 aperture; +} NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS; + +#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_INVALID (0x00000000U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_VIDEO_MEMORY (0x00000001U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_COHERENT_MEMORY (0x00000002U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_NON_COHERENT_MEMORY (0x00000003U) + +#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_SMALL 0U +#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_BIG 1U +#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE 2U + +#define NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS { + NvU32 pdeIndex; + NvU32 flags; + NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS ptParams[NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE], 8); + NvHandle hVASpace; + NV_DECLARE_ALIGNED(NvP64 pPdeBuffer, 8); // NV_MMU_VER2_DUAL_PDE__SIZE + NvU32 subDeviceId; // ID+1, 0 for BC +} NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS; + +/*! + * If set a PDE cache flush (MMU invalidate) will be performed. + */ +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE 0:0 +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_TRUE (0x00000001U) + +/*! + * For verification purposes (MODS-only) this flag may be set to modify any PDE + * in the VA space (RM managed or externally managed). + * It is up to caller to restore any changes properly (or to expect faults). + */ +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE 1:1 +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_TRUE (0x00000001U) + +/*! + * Directly controls the PDE_SIZE field (size of the page tables pointed to by this PDE). + */ +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE 3:2 +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_FULL (0x00000000U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_HALF (0x00000001U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_QUARTER (0x00000002U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_EIGHTH (0x00000003U) + +/*! + * Used to specify if the allocation is sparse. Applicable only in case of + * VA Space managed by OS, as in WDDM2.0 + */ +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE 4:4 +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_TRUE (0x00000001U) + +/* + * NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE + * This interface will create a corresponding privileged + * kernel address space that will mirror user space allocations in this + * VASPACE. + * The user can either pass a FERMI_VASPACE_A handle or RM will use the + * vaspace associated with the client/device if hVaspace is passed as + * NULL. + * Once this property is set, the user will not be able to make allocations + * from the top most PDE of this address space. + * + * The user is expected to call this function as soon as he has created + * the device/Vaspace object. If the user has already made VA allocations + * in this vaspace then this call will return a failure + * (NV_ERR_INVALID_STATE). + * The Vaspace should have no VA allocations when this call is made. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE +*/ +#define NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE (0x801810U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS { + NvHandle hVASpace; +} NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS; + +/* + * NV0080_CTRL_DMA_SET_DEFAULT_VASPACE + * This is a special control call provided for KMD to use. + * It will associate an allocated Address Space Object as the + * default address space of the device. + * + * This is added so that the USER can move to using address space objects when they + * want to specify the size of the big page size they want to use but still want + * to use the rest of the relevant RM apis without specifying the hVASpace. + * + * This call will succeed only if there is already no VASPACE associated with the + * device. This means the user will have to call this before he has made any allocations + * on this device/address space. + * + * The hVASpace that is passed in to be associated shoould belong to the parent device that + * this call is made for. This call will fail if we try to associate a VASpace belonging to + * some other client/device. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + * + */ +#define NV0080_CTRL_DMA_SET_DEFAULT_VASPACE (0x801812U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS { + NvHandle hVASpace; +} NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS; + +/*! + * NV0080_CTRL_DMA_SET_PAGE_DIRECTORY + * + * Move an existing VA space to an externally-managed top-level page directory. + * The VA space must have been created in SHARED_MANAGEMENT mode. + * For lifecycle details, see NV_VASPACE_ALLOCATION_PARAMETERS documentation in nvos.h. + * + * RM will propagate the update to all channels using the VA space. + * + * NOTE: All channels using this VA space are expected to be idle and unscheduled prior + * to and during this control call - it is responsibility of caller to ensure this. + * + * physAddress + * Physical address of the new page directory within the aperture specified by flags. + * numEntries + * Number of entries in the new page directory. + * The backing phyical memory must be at least this size (multiplied by entry size). + * flags + * APERTURE + * Specifies which physical aperture the page directory resides. + * PRESERVE_PDES + * Deprecated - RM will always copy the RM-managed PDEs from the old page directory + * to the new page directory. + * ALL_CHANNELS + * If true, RM will update the instance blocks for all channels using + * the VAS and ignore the chId parameter. + * EXTEND_VASPACE + * If true, RM will use the client VA for client VA requests in VASPACE_SHARED_MANAGEMENT mode + * If false, RM will use the internal VA for client VA requests. + * IGNORE_CHANNEL_BUSY + * If true, RM will ignore the channel busy status during set page + * directory operation. + * hVASpace + * handle for the allocated VA space that this control call should operate + * on. If it's 0, it assumes to use the implicit allocated VA space + * associated with the client/device pair. + * chId + * ID of the Channel to be updated. + * pasid + * PASID (Process Address Space IDentifier) of the process corresponding to + * the VA space. Ignored unless the VA space has ATS enabled. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_LIMIT + * NV_ERR_GENERIC + */ +#define NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY (0x801813U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS { + NV_DECLARE_ALIGNED(NvU64 physAddress, 8); + NvU32 numEntries; + NvU32 flags; + NvHandle hVASpace; + NvU32 chId; + NvU32 subDeviceId; // ID+1, 0 for BC + NvU32 pasid; +} NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS; + +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE 1:0 +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_VIDMEM (0x00000000U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_COH (0x00000001U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_NONCOH (0x00000002U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES 2:2 +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_TRUE (0x00000001U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS 3:3 +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_TRUE (0x00000001U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY 4:4 +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_TRUE (0x00000001U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE 5:5 +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_FALSE (0x00000000U) +#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_TRUE (0x00000001U) + +/*! + * NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY + * + * Restore an existing VA space to an RM-managed top-level page directory. + * The VA space must have been created in SHARED_MANAGEMENT mode and + * previously relocated to an externally-managed page directory with + * NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY (these two API are symmetric operations). + * For lifecycle details, see NV_VASPACE_ALLOCATION_PARAMETERS documentation in nvos.h. + * + * RM will propagate the update to all channels using the VA space. + * + * NOTE: All channels using this VA space are expected to be idle and unscheduled prior + * to and during this control call - it is responsibility of caller to ensure this. + * + * hVASpace + * handle for the allocated VA space that this control call should operate + * on. If it's 0, it assumes to use the implicit allocated VA space + * associated with the client/device pair. + */ +#define NV0080_CTRL_CMD_DMA_UNSET_PAGE_DIRECTORY (0x801814U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS { + NvHandle hVASpace; + NvU32 subDeviceId; // ID+1, 0 for BC +} NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS; + + + +/* _ctrl0080dma_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h new file mode 100644 index 0000000..7fcc696 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h @@ -0,0 +1,232 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080fb.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE fb control commands and parameters */ + +/** + * NV0080_CTRL_CMD_FB_GET_CAPS + * + * This command returns the set of framebuffer capabilities for the device + * in the form of an array of unsigned bytes. Framebuffer capabilities + * include supported features and required workarounds for the framebuffer + * engine(s) within the device, each represented by a byte offset into the + * table and a bit position within that byte. + * + * capsTblSize + * This parameter specifies the size in bytes of the caps table. + * This value should be set to NV0080_CTRL_FB_CAPS_TBL_SIZE. + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the framebuffer caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_POINTER + */ +#define NV0080_CTRL_CMD_FB_GET_CAPS (0x801301) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FB_GET_CAPS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0080_CTRL_FB_GET_CAPS_PARAMS { + NvU32 capsTblSize; + NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); +} NV0080_CTRL_FB_GET_CAPS_PARAMS; + +/* extract cap bit setting from tbl */ +#define NV0080_CTRL_FB_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* caps format is byte_index:bit_mask */ +#define NV0080_CTRL_FB_CAPS_SUPPORT_RENDER_TO_SYSMEM 0:0x01 +#define NV0080_CTRL_FB_CAPS_BLOCKLINEAR 0:0x02 +#define NV0080_CTRL_FB_CAPS_SUPPORT_SCANOUT_FROM_SYSMEM 0:0x04 +#define NV0080_CTRL_FB_CAPS_SUPPORT_CACHED_SYSMEM 0:0x08 +#define NV0080_CTRL_FB_CAPS_SUPPORT_C24_COMPRESSION 0:0x10 // Deprecated +#define NV0080_CTRL_FB_CAPS_SUPPORT_SYSMEM_COMPRESSION 0:0x20 +#define NV0080_CTRL_FB_CAPS_NISO_CFG0_BUG_534680 0:0x40 // Deprecated +#define NV0080_CTRL_FB_CAPS_ISO_FETCH_ALIGN_BUG_561630 0:0x80 // Deprecated + +#define NV0080_CTRL_FB_CAPS_BLOCKLINEAR_GOBS_512 1:0x01 +#define NV0080_CTRL_FB_CAPS_L2_TAG_BUG_632241 1:0x02 +#define NV0080_CTRL_FB_CAPS_SINGLE_FB_UNIT 1:0x04 // Deprecated +#define NV0080_CTRL_FB_CAPS_CE_RMW_DISABLE_BUG_897745 1:0x08 // Deprecated +#define NV0080_CTRL_FB_CAPS_OS_OWNS_HEAP_NEED_ECC_SCRUB 1:0x10 +#define NV0080_CTRL_FB_CAPS_ASYNC_CE_L2_BYPASS_SET 1:0x20 // Deprecated +#define NV0080_CTRL_FB_CAPS_DISABLE_TILED_CACHING_INVALIDATES_WITH_ECC_BUG_1521641 1:0x40 + +#define NV0080_CTRL_FB_CAPS_DISABLE_MSCG_WITH_VR_BUG_1681803 2:0x01 +#define NV0080_CTRL_FB_CAPS_VIDMEM_ALLOCS_ARE_CLEARED 2:0x02 +#define NV0080_CTRL_FB_CAPS_DISABLE_PLC_GLOBALLY 2:0x04 +#define NV0080_CTRL_FB_CAPS_PLC_BUG_3046774 2:0x08 + + +/* size in bytes of fb caps table */ +#define NV0080_CTRL_FB_CAPS_TBL_SIZE 3 + + + +/*! + * NV0080_CTRL_CMD_FB_COMPBIT_STORE_GET_INFO + * + * This command returns compbit backing store-related information. + * + * size + * [out] Size of compbit store, in bytes + * address + * [out] Address of compbit store + * addressSpace + * [out] Address space of compbit store (corresponds to type NV_ADDRESS_SPACE in nvrm.h) + * maxCompbitLine + * [out] Maximum compbitline possible, determined based on size + * comptagsPerCacheLine + * [out] Number of compression tags per compression cache line, across all + * L2 slices. + * cacheLineSize + * [out] Size of compression cache line, across all L2 slices. (bytes) + * cacheLineSizePerSlice + * [out] Size of the compression cache line per slice (bytes) + * cacheLineFetchAlignment + * [out] Alignment used while fetching the compression cacheline range in FB. + * If start offset of compcacheline in FB is S and end offset is E, then + * the range to fetch to ensure entire compcacheline data is extracted is: + * (align_down(S) , align_up(E)) + * This is needed in GM20X+ because of interleaving of data in Linear FB space. + * Example - In GM204 every other 1K FB chunk of data is offset by 16K. + * backingStoreBase + * [out] Address of start of Backing Store in linear FB Physical Addr space. + * This is the actual offset in FB which HW starts using as the Backing Store and + * in general will be different from the start of the region that driver allocates + * as the backing store. This address is expected to be 2K aligned. + * gobsPerComptagPerSlice + * [out] (Only on Pascal) Number of GOBS(512 bytes of surface PA) that correspond to one 64KB comptgaline, per slice. + * One GOB stores 1 byte of compression bits. + * 0 value means this field is not applicable for the current architecture. + * backingStoreCbcBase + * [out] 2KB aligned base address of CBC (post divide address) + * comptaglineAllocationPolicy + * [out] Policy used to allocate comptagline from CBC for the device + * privRegionStartOffset + * [out] Starting offset for any priv region allocated by clients. only used by MODS + * Possible status values returned are: + * NV_OK + */ +#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO (0x801306) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 Size, 8); + NV_DECLARE_ALIGNED(NvU64 Address, 8); + NvU32 AddressSpace; + NvU32 MaxCompbitLine; + NvU32 comptagsPerCacheLine; + NvU32 cacheLineSize; + NvU32 cacheLineSizePerSlice; + NvU32 cacheLineFetchAlignment; + NV_DECLARE_ALIGNED(NvU64 backingStoreBase, 8); + NvU32 gobsPerComptagPerSlice; + NvU32 backingStoreCbcBase; + NvU32 comptaglineAllocationPolicy; + NV_DECLARE_ALIGNED(NvU64 privRegionStartOffset, 8); +} NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS; + +#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_UNKNOWN 0 // ADDR_UNKNOWN +#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_SYSMEM 1 // ADDR_SYSMEM +#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_FBMEM 2 // ADDR_FBMEM + +// Policy used to allocate comptaglines +/** + * Legacy mode allocates a comptagline for 64kb page. This mode will always allocate + * contiguous comptaglines from a ctag heap. + */ +#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_LEGACY 0 +/** + * 1TO1 mode allocates a comptagline for 64kb page. This mode will calculate + * comptagline offset based on physical address. This mode will allocate + * contiguous comptaglines if the surface is contiguous and non-contiguous + * comptaglines for non-contiguous surfaces. + */ +#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO1 1 +/** + * 1TO4_Heap mode allocates a comptagline for 256kb page granularity. This mode + * will allocate comptagline from a heap. This mode will align the surface allocations + * to 256kb before allocating comptaglines. The comptaglines allocated will always be + * contiguous here. + * TODO: For GA10x, this mode will support < 256kb surface allocations, by sharing + * a comptagline with at most 3 different 64Kb allocations. This will result in + * miixed-contiguity config where comptaglines will be allocated contiguously as well + * as non-contiguous when shared with other allocations. + */ +#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO4 2 +/** + * Rawmode will transfer allocation of comptaglines to HW, where HW manages + * comptaglines based on physical offset. The comptaglines are cleared when SW + * issues physical/virtual scrub to the surface before reuse. + */ +#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_RAWMODE 3 + +/** + * NV0080_CTRL_CMD_FB_GET_CAPS_V2 + * + * This command returns the same set of framebuffer capabilities for the + * device as @ref NV0080_CTRL_CMD_FB_GET_CAPS. The difference is in the structure + * NV0080_CTRL_FB_GET_CAPS_V2_PARAMS, which contains a statically sized array, + * rather than a caps table pointer and a caps table size in + * NV0080_CTRL_FB_GET_CAPS_PARAMS. + * + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the framebuffer caps bits will be written by the RM. + * The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_POINTER + */ +#define NV0080_CTRL_CMD_FB_GET_CAPS_V2 (0x801307) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FB_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV0080_CTRL_FB_GET_CAPS_V2_PARAMS { + NvU8 capsTbl[NV0080_CTRL_FB_CAPS_TBL_SIZE]; +} NV0080_CTRL_FB_GET_CAPS_V2_PARAMS; + + + + +/* _ctrl0080fb_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h new file mode 100644 index 0000000..823cc0c --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h @@ -0,0 +1,642 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080fifo.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE fifo control commands and parameters */ + +/** + * NV0080_CTRL_FIFO_GET_CAPS + * + * This command returns the set of FIFO engine capabilities for the device + * in the form of an array of unsigned bytes. FIFO capabilities + * include supported features and required workarounds for the FIFO + * engine(s) within the device, each represented by a byte offset into the + * table and a bit position within that byte. + * + * capsTblSize + * This parameter specifies the size in bytes of the caps table. + * This value should be set to NV0080_CTRL_FIFO_CAPS_TBL_SIZE. + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the framebuffer caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_FIFO_GET_CAPS (0x801701) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_GET_CAPS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0080_CTRL_FIFO_GET_CAPS_PARAMS { + NvU32 capsTblSize; + NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); +} NV0080_CTRL_FIFO_GET_CAPS_PARAMS; + +/* extract cap bit setting from tbl */ +#define NV0080_CTRL_FIFO_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* caps format is byte_index:bit_mask */ +#define NV0080_CTRL_FIFO_CAPS_SUPPORT_SCHED_EVENT 0:0x01 +#define NV0080_CTRL_FIFO_CAPS_SUPPORT_PCI_PB 0:0x02 +#define NV0080_CTRL_FIFO_CAPS_SUPPORT_VID_PB 0:0x04 +#define NV0080_CTRL_FIFO_CAPS_USERD_IN_SYSMEM 0:0x40 +/* do not use pipelined PTE BLITs to update PTEs: call the RM */ +#define NV0080_CTRL_FIFO_CAPS_NO_PIPELINED_PTE_BLIT 0:0x80 +#define NV0080_CTRL_FIFO_CAPS_GPU_MAP_CHANNEL 1:0x01 +#define NV0080_CTRL_FIFO_CAPS_BUFFEREDMODE_SCHEDULING 1:0x02 // Deprecated +#define NV0080_CTRL_FIFO_CAPS_WFI_BUG_898467 1:0x08 // Deprecated +#define NV0080_CTRL_FIFO_CAPS_HAS_HOST_LB_OVERFLOW_BUG_1667921 1:0x10 +/* + * To indicate Volta subcontext support with multiple VA spaces in a TSG. + * We are not using "subcontext" tag for the property, since we also use + * subcontext to represent pre-VOlta SCG feature, which only allows a single + * VA space in a TSG. + */ +#define NV0080_CTRL_FIFO_CAPS_MULTI_VAS_PER_CHANGRP 1:0x20 + + +#define NV0080_CTRL_FIFO_CAPS_SUPPORT_WDDM_INTERLEAVING 1:0x40 + +/* size in bytes of fifo caps table */ +#define NV0080_CTRL_FIFO_CAPS_TBL_SIZE 2 + +/* + * NV0080_CTRL_CMD_FIFO_ENABLE_SCHED_EVENTS + * + * This command enables the GPU to place various scheduling events in the + * off chip event buffer (with optional interrupt) for those GPUs that support + * it. + * + * record + * This parameter specifies a mask of event types to record. + * interrupt + * This parameter specifies a mask of event types for which to interrupt + * the CPU when the event occurs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_FIFO_ENABLE_SCHED_EVENTS (0x801703) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0x3" */ + +typedef struct NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PARAMS { + NvU32 record; + NvU32 interrupt; +} NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PARAMS; + +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_START_CTX 0:0 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_START_CTX_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_START_CTX_ENABLE (0x00000001) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_END_CTX 1:1 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_END_CTX_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_END_CTX_ENABLE (0x00000001) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_NEW_RUNLIST 2:2 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_NEW_RUNLIST_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_NEW_RUNLIST_ENABLE (0x00000001) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_SEM_ACQUIRE 3:3 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_SEM_ACQUIRE_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_SEM_ACQUIRE_ENABLE (0x00000001) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PAGE_FAULT 4:4 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PAGE_FAULT_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PAGE_FAULT_ENABLE (0x00000001) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PREEMPT 5:5 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PREEMPT_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PREEMPT_ENABLE (0x00000001) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_YIELD 6:6 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_YIELD_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_YIELD_ENABLE (0x00000001) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_IDLE_CTX 7:7 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_IDLE_CTX_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_IDLE_CTX_ENABLE (0x00000001) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_HI_PRI 8:8 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_HI_PRI_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_HI_PRI_ENABLE (0x00000001) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ENG_STALLED 9:9 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ENG_STALLED_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ENG_STALLED_ENABLE (0x00000001) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_VSYNC 10:10 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_VSYNC_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_VSYNC_ENABLE (0x00000001) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_FGCS_FAULT 11:11 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_FGCS_FAULT_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_FGCS_FAULT_ENABLE (0x00000001) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ALL 11:0 +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ALL_DISABLE (0x00000000) +#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ALL_ENABLE (0x00000fff) + +/* + * NV0080_CTRL_CMD_FIFO_START_SELECTED_CHANNELS + * + * This command allows the caller to request that a set of channels + * be added to the runlist. + * + * fifoStartChannelListSize + * Size of the fifoStartChannelList. The units are in entries, not + * bytes. + * fifoStartChannelList + * This will be a list of NV0080_CTRL_FIFO_CHANNEL data structures, + * one for each channel that is to be started. + * channelHandle + * deprecated + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +/* + * hChannel + * This is the handle to the channel that is scheduled to be started. + */ +typedef struct NV0080_CTRL_FIFO_CHANNEL { + NvHandle hChannel; +} NV0080_CTRL_FIFO_CHANNEL; + +#define NV0080_CTRL_CMD_FIFO_START_SELECTED_CHANNELS (0x801705) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS { + NvU32 fifoStartChannelListCount; + NvHandle channelHandle[8]; + NV_DECLARE_ALIGNED(NvP64 fifoStartChannelList, 8); +} NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS; + +#define NV0080_CTRL_FIFO_ENGINE_ID_GRAPHICS (0x00000000) +#define NV0080_CTRL_FIFO_ENGINE_ID_MPEG (0x00000001) +#define NV0080_CTRL_FIFO_ENGINE_ID_MOTION_ESTIMATION (0x00000002) +#define NV0080_CTRL_FIFO_ENGINE_ID_VIDEO (0x00000003) +#define NV0080_CTRL_FIFO_ENGINE_ID_BITSTREAM (0x00000004) +#define NV0080_CTRL_FIFO_ENGINE_ID_ENCRYPTION (0x00000005) +#define NV0080_CTRL_FIFO_ENGINE_ID_FGT (0x00000006) + +/* + * NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES + * + * This command is used to provide the caller with the alignment and size + * of the context save region for an engine + * + * engineId + * This parameter is an input parameter specifying the engineId for which + * the alignment/size is requested. + * alignment + * This parameter is an output parameter which will be filled in with the + * minimum alignment requirement. + * size + * This parameter is an output parameter which will be filled in with the + * minimum size of the context save region for the engine. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES (0x801707) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID 4:0 +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS (0x00000000) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VLD (0x00000001) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VIDEO (0x00000002) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_MPEG (0x00000003) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_CAPTURE (0x00000004) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_DISPLAY (0x00000005) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_ENCRYPTION (0x00000006) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_POSTPROCESS (0x00000007) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ZCULL (0x00000008) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PM (0x00000009) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COMPUTE_PREEMPT (0x0000000a) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PREEMPT (0x0000000b) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SPILL (0x0000000c) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL (0x0000000d) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BETACB (0x0000000e) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV (0x0000000f) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PATCH (0x00000010) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BUNDLE_CB (0x00000011) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL_GLOBAL (0x00000012) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ATTRIBUTE_CB (0x00000013) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV_CB_GLOBAL (0x00000014) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_POOL (0x00000015) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_CTRL_BLK (0x00000016) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_FECS_EVENT (0x00000017) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PRIV_ACCESS_MAP (0x00000018) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT (0x00000019) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS { + NvU32 engineId; + NvU32 alignment; + NvU32 size; +} NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS; + +/* + * NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS + * + * This command allows the caller to group two sets of channels. A channel + * set includes one or more channels. After grouping, the grouped channel IDs + * are set to next to each other in the runlist. This command can be used + * several times to group more than two channels. + * + * Using a NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE after + * NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS is the general usage. A + * NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS after a + * NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE for a channel handle is not + * allowed. + * + * NV0080_CTRL_FIFO_RUNLIST_GROUP_MAX_CHANNELS defines the max channels in a + * group. + * + * hChannel1 + * This parameter specifies the handle of the channel that belongs to the + * base set of channels. + * hChannel2 + * This parameter specifies the handle of the channel that belongs to the + * additional set of channels. + + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_CHANNEL + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS (0x801709) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0x9" */ + +typedef struct NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM { + NvHandle hChannel1; + NvHandle hChannel2; +} NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM; + +#define NV0080_CTRL_FIFO_RUNLIST_GROUP_MAX_CHANNELS (8) + +/* + * NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE + * + * This command allows the caller to divide the timeslice (DMA_TIMESLICE) of a + * channel between the channels in the group in which the channel resides. + * After applying this command, a timeslice divided channel (group) has a + * short timeslice and repeats more than once in the runlist. The total + * available execution time is not changed. + * + * Using this command after NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS is the + * general usage. A NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS after a + * NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE for a channel handle is not + * allowed. + * + * hChannel + * This parameter specifies the handle of the channel for the channel + * group to which the divided timeslice operation will apply. + * tsDivisor + * This parameter specifies the timeslice divisor value. This value + * should not exceed NV0080_CTRL_FIFO_RUNLIST_MAX_TIMESLICE_DIVISOR + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_CHANNEL + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_RESOURCES + */ +#define NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE (0x80170b) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0xB" */ + +typedef struct NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM { + NvHandle hChannel; + NvU32 tsDivisor; +} NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM; + +#define NV0080_CTRL_FIFO_RUNLIST_MAX_TIMESLICE_DIVISOR (12) + +/* + * NV0080_CTRL_CMD_FIFO_PREEMPT_RUNLIST + * + * This command preepmts the engine represented by the specified runlist. + * + * hRunlist + * This parameter specifies the per engine runlist handle. This + * parameter is being retained to maintain backwards compatibility + * with clients that have not transitioned over to using runlists + * on a per subdevice basis. + * + * engineID + * This parameter specifies the engine to be preempted. Engine defines + * can be found in cl2080.h. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_FIFO_PREEMPT_RUNLIST (0x80170c) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0xC" */ + +typedef struct NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS { + NvHandle hRunlist; + NvU32 engineID; +} NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS; + + +/* + * NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST + * + * Takes a list of hChannels as input and returns the + * corresponding Channel IDs that they corresponding to + * on hw. + * + * numChannels + * Size of input hChannellist + * pChannelHandleList + * List of input channel handles + * pChannelList + * List of Channel ID's corresponding to the + * each entry in the hChannelList. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST (0x80170d) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS { + NvU32 numChannels; + NV_DECLARE_ALIGNED(NvP64 pChannelHandleList, 8); + NV_DECLARE_ALIGNED(NvP64 pChannelList, 8); +} NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS; + + +/* + * NV0080_CTRL_CMD_FIFO_GET_LATENCY_BUFFER_SIZE + * + * This control call is used to return the number of gp methods(gpsize) and push buffer methods(pbsize) + * allocated to each engine. + * + *engineID + * The engine ID which is an input + * + *gpEntries + * number of gp entries + * + *pbEntries + * number of pb entries (in units of 32B rows) + * + */ + + +#define NV0080_CTRL_CMD_FIFO_GET_LATENCY_BUFFER_SIZE (0x80170e) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS { + NvU32 engineID; + NvU32 gpEntries; + NvU32 pbEntries; +} NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS; + +#define NV0080_CTRL_FIFO_GET_CHANNELLIST_INVALID_CHANNEL (0xffffffff) + +/* + * NV0080_CTRL_CMD_FIFO_SET_CHANNEL_PROPERTIES + * + * This command allows internal properties of the channel + * to be modified even when the channel is active. Most of these properties + * are not meant to be modified during normal runs hence have been + * kept separate from channel alloc params. It is the + * responsibility of the underlying hal routine to make + * sure the channel properties are changed while the channel + * is *NOT* in a transient state. + * + * hChannel + * The handle to the channel. + * + * property + * The channel property to be modified. + * NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_xxx provides the entire list + * of properties. + * + * value + * The new value for the property. + * When property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEINMICROSECONDS + * value = timeslice in microseconds + * desc: Used to change a channel's engine timeslice in microseconds + * + * property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEINMICROSECONDS + * value = timeslice in microseconds + * desc: Used to change a channel's pbdma timeslice in microseconds + * + * property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEDISABLE + * value is ignored + * desc: Disables a channel from being timesliced out from an engine. + * Other scheduling events like explicit yield, acquire failures will + * switch out the channel though. + * + * property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEDISABLE + * value is ignored + * desc: Disables a channel from being timesliced out from its pbdma. + * + * property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_INVALIDATE_PDB_TARGET + * value is ignored + * desc: Override the channel's page directory pointer table with an + * erroneous aperture value. (TODO: make test calls NV_VERIF_FEATURES + * only)(VERIF ONLY) + * + * property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT + * value = engineID of engine that will have its context pointer reset. + * engineID defines can be found in cl2080.h + * (e.g., NV2080_ENGINE_TYPE_GRAPHICS) + * desc: Override the channel's engine context pointer with a non existent + * buffer forcing it to fault. (VERIF ONLY) + * + * property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT_NOPREEMPT + * value = engineID of engine that will have its context pointer reset. + * engineID defines can be found in cl2080.h + * (e.g., NV2080_ENGINE_TYPE_GRAPHICS) + * desc: Override the channel's engine context pointer with a non existent + * buffer forcing it to fault. However the channel will not be preempted + * before having its channel state modified.(VERIF ONLY) + * + * property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_NOOP + * value is ignored + * desc: does not change any channel state exercises a full channel preempt/ + * unbind/bind op. (VERIF ONLY) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_CHANNEL + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0080_CTRL_CMD_FIFO_SET_CHANNEL_PROPERTIES (0x80170f) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS { + NvHandle hChannel; + NvU32 property; + NV_DECLARE_ALIGNED(NvU64 value, 8); +} NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS; + +#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEINMICROSECONDS (0x00000000) +#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEINMICROSECONDS (0x00000001) +#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEDISABLE (0x00000002) +#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEDISABLE (0x00000003) +#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_INVALIDATE_PDB_TARGET (0x00000004) +#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT (0x00000005) +#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_NOOP (0x00000007) +#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT_NOPREEMPT (0x00000008) + + + +/* + * NV0080_CTRL_CMD_FIFO_STOP_RUNLIST + * + * Stops all processing on the runlist for the given engine. This is only + * valid in per-engine round-robin scheduling mode. + * + * engineID + * This parameter specifies the engine to be stopped. Engine defines + * can be found in cl2080.h. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV0080_CTRL_CMD_FIFO_STOP_RUNLIST (0x801711) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS { + NvU32 engineID; +} NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS; + +/* + * NV0080_CTRL_CMD_FIFO_START_RUNLIST + * + * Restarts a runlist previously stopped with NV0080_CTRL_CMD_FIFO_STOP_RUNLIST. + * This is only valid for per-engine round-robin mode. + * + * engineID + * This parameter specifies the engine to be started. Engine defines + * can be found in cl2080.h. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV0080_CTRL_CMD_FIFO_START_RUNLIST (0x801712) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV0080_CTRL_FIFO_START_RUNLIST_PARAMS { + NvU32 engineID; +} NV0080_CTRL_FIFO_START_RUNLIST_PARAMS; + +/** + * NV0080_CTRL_FIFO_GET_CAPS_V2 + * + * This command returns the same set of FIFO engine capabilities for the device + * as @ref NV0080_CTRL_FIFO_GET_CAPS. The difference is in the structure + * NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS, which contains a statically sized array, + * rather than a caps table pointer and a caps table size in + * NV0080_CTRL_FIFO_GET_CAPS_PARAMS. + * + * capsTbl + * This parameter is an array of the client's caps table buffer. + * The framebuffer caps bits will be written by the RM. + * The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_FIFO_GET_CAPS_V2 (0x801713) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS { + NvU8 capsTbl[NV0080_CTRL_FIFO_CAPS_TBL_SIZE]; +} NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS; + +/** + * NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS + * + * @brief This command idles (deschedules and waits for pending work to complete) channels + * belonging to a particular device. + * + * numChannels + * Number of channels to idle + * + * hChannels + * Array of channel handles to idle + * + * flags + * NVOS30_FLAGS that control aspects of how the channel is idled + * + * timeout + * GPU timeout in microseconds, for each CHID Manager's idling operation + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_TIMEOUT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_LOCK_STATE + */ +#define NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS (0x801714) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS_MESSAGE_ID" */ +#define NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS_MAX_CHANNELS 4096 + +#define NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS { + NvU32 numChannels; + NvHandle hChannels[NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS_MAX_CHANNELS]; + NvU32 flags; + NvU32 timeout; +} NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS; + +/* _ctrl0080fifo_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h new file mode 100644 index 0000000..5ce19e5 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h @@ -0,0 +1,585 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080gpu.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" +#include "nvlimits.h" + + +/* NV01_DEVICE_XX/NV03_DEVICE gpu control commands and parameters */ + +/* + * NV0080_CTRL_CMD_GPU_GET_CLASSLIST + * + * This command returns supported class information for the specified device. + * If the device is comprised of more than one GPU, the class list represents + * the set of supported classes common to all GPUs within the device. + * + * It has two modes: + * + * If the classList pointer is NULL, then this command returns the number + * of classes supported by the device in the numClasses field. The value + * should then be used by the client to allocate a classList buffer + * large enough to hold one 32bit value per numClasses entry. + * + * If the classList pointer is non-NULL, then this command returns the + * set of supported class numbers in the specified buffer. + * + * numClasses + * If classList is NULL, then this parameter will return the + * number of classes supported by the device. If classList is non-NULL, + * then this parameter indicates the number of entries in classList. + * classList + * This parameter specifies a pointer to the client's buffer into + * which the supported class numbers should be returned. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV0080_CTRL_CMD_GPU_GET_CLASSLIST (0x800201) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS { + NvU32 numClasses; + NV_DECLARE_ALIGNED(NvP64 classList, 8); +} NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS; + +/** + * NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES + * + * This command returns the number of subdevices for the device. + * + * numSubDevices + * This parameter returns the number of subdevices within the device. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES (0x800280) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS_MESSAGE_ID (0x80U) + +typedef struct NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS { + NvU32 numSubDevices; +} NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS; + +/* + * NV0080_CTRL_CMD_GPU_GET_VIDLINK_ORDER + * + * This command returns the video link order of each subdevice id inside the + * device. This call can only be made after SLI is enabled. This call is + * intended for 3D clients to use to determine the vidlink order of the + * devices. The Display Output Parent will always be the first subdevice + * mask listed in the array. Note that this command should not be used in + * case of bridgeless SLI. The order of the subdevices returned by this + * command will not be correct in case of bridgeless SLI. + * + * ConnectionCount + * Each HW can provide 1 or 2 links between all GPUs in a device. This + * number tells how many links are available between GPUs. This data + * also represents the number of concurrent SLI heads that can run at + * the same time over this one device. + * + * Order + * This array returns the order of subdevices that are used through + * the vidlink for display output. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0080_CTRL_CMD_GPU_GET_VIDLINK_ORDER (0x800281) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS { + NvU32 ConnectionCount; + NvU32 Order[NV_MAX_SUBDEVICES]; +} NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS; + +/* + * NV0080_CTRL_CMD_GPU_SET_DISPLAY_OWNER + * + * This command sets display ownership within the device to the specified + * subdevice instance. The actual transfer of display ownership will take + * place at the next modeset. + * + * subDeviceInstance + * This member specifies the subdevice instance of the new display + * owner. The subdevice instance must be in the legal range + * indicated by the NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0080_CTRL_CMD_GPU_SET_DISPLAY_OWNER (0x800282) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS_MESSAGE_ID (0x82U) + +typedef struct NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS { + NvU32 subDeviceInstance; +} NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS; + +/* + * NV0080_CTRL_CMD_GPU_GET_DISPLAY_OWNER + * + * This command returns the subdevice instance of the current display owner + * within the device. + * + * subDeviceInstance + * This member returns the subdevice instance of the current display + * owner. The subdevice instance will be in the legal range + * indicated by the NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0080_CTRL_CMD_GPU_GET_DISPLAY_OWNER (0x800283) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS_MESSAGE_ID (0x83U) + +typedef struct NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS { + NvU32 subDeviceInstance; +} NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS; + +/* + * NV0080_CTRL_CMD_GPU_SET_VIDLINK + * + * This command enables or disables the VIDLINK of all subdevices in the + * current SLI configuration. + * + * enable + * Enables or disables the vidlink + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV0080_CTRL_CMD_GPU_SET_VIDLINK (0x800285) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_VIDLINK_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_SET_VIDLINK_PARAMS_MESSAGE_ID (0x85U) + +typedef struct NV0080_CTRL_GPU_SET_VIDLINK_PARAMS { + NvU32 enable; +} NV0080_CTRL_GPU_SET_VIDLINK_PARAMS; + +#define NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_FALSE (0x00000000) +#define NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_TRUE (0x00000001) + +/* commands */ +#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_GET_STATUS 0 +#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERDOWN 1 +#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERUP 2 + +/* status */ +#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWER_ON 0 +#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_DOWN 1 +#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_GATED 2 +#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_UP 3 + +/* + * NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE + * + * This command is used to enable or disable the persistence of a GPU's + * software state when no clients exist. With persistent software state enabled + * the GPU's software state is not torn down when the last client exits, but is + * retained until either the kernel module unloads or persistent software state + * is disabled. + * + * newState + * This input parameter is used to enable or disable the persistence of the + * software state of all subdevices within the device. + * Possible values are: + * NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED + * NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE (0x800287) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID" */ + +/* Possible values of persistentSwState */ +#define NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED (0x00000000) +#define NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED (0x00000001) + +#define NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID (0x87U) + +typedef struct NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS { + NvU32 newState; +} NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS; + +/* + * NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE + * + * swStatePersistence + * This parameter returns a value indicating if persistent software + * state is currently enabled or not for the specified GPU. See the + * description of NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE. + * Possible values are: + * NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED + * NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE (0x800288) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID (0x88U) + +typedef struct NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS { + NvU32 swStatePersistence; +} NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS; + +/** + * NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE + * + * This command returns a value indicating virtualization mode in + * which the GPU is running. + * + * virtualizationMode + * This parameter returns the virtualization mode of the device. + * Possible values are: + * NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE + * This value indicates that there is no virtualization mode associated with the + * device (i.e. it's a baremetal GPU). + * NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS + * This value indicates that the device is associated with the NMOS. + * NV0080_CTRL_GPU_VIRTUALIZATION_MODE_VGX + * This value indicates that the device is associated with VGX(guest GPU). + * NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST + * NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VGPU + * This value indicates that the device is associated with vGPU(host GPU). + * NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VSGA + * This value indicates that the device is associated with vSGA(host GPU). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE (0x800289) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE (0x00000000) +#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS (0x00000001) +#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_VGX (0x00000002) +#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST (0x00000003) +#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VGPU NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST +#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VSGA (0x00000004) + +#define NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS_MESSAGE_ID (0x89U) + +typedef struct NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS { + NvU32 virtualizationMode; +} NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS; + + + +/* + * NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE + * + * This command returns the setting information for sparse texture compute + * mode optimization on the associated GPU. This setting indicates how the + * large page size should be selected by the RM for the GPU. + * + * defaultSetting + * This field specifies what the OS default setting is for the associated + * GPU. See NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE for a list + * of possible values. + * currentSetting + * This field specifies which optimization mode was applied when the + * driver was loaded. See + * NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE for a list of + * possible values. + * pendingSetting + * This field specifies which optimization mode will be applied on the + * next driver reload. See + * NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE for a list of + * possible values. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE (0x80028c) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID (0x8CU) + +typedef struct NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS { + NvU32 defaultSetting; + NvU32 currentSetting; + NvU32 pendingSetting; +} NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS; + +/* + * NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE + * + * This command sets the pending setting for sparse texture compute mode. This + * setting indicates how the large page size should be selected by the RM for + * the GPU on the next driver reload. + * + * setting + * This field specifies which use case the RM should optimize the large + * page size for on the next driver reload. Possible values for this + * field are: + * NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_DEFAULT + * This value indicates that the RM should use the default setting for + * the GPU's large page size. The default setting is reported by + * NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE. + * NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_COMPUTE + * This value indicates that the RM should select the GPU's large page + * size to optimize for compute use cases. + * NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_SPARSE_TEXTURE + * This value indicates that the RM should select the GPU's large page + * size to optimize for sparse texture use cases. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +#define NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE (0x80028d) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID (0x8DU) + +typedef struct NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS { + NvU32 setting; +} NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS; + +/* Possible sparse texture compute mode setting values */ +#define NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_DEFAULT 0 +#define NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_COMPUTE 1 +#define NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_SPARSE_TEXTURE 2 + +/* + * NV0080_CTRL_CMD_GPU_GET_VGX_CAPS + * + * This command gets the VGX capability of the GPU depending on the status of + * the VGX hardware fuse. + * + * isVgx + * This field is set to NV_TRUE is VGX fuse is enabled for the GPU otherwise + * it is set to NV_FALSE. + * + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + * NVOS_STATUS_ERROR_NOT_SUPPORTED + */ +#define NV0080_CTRL_CMD_GPU_GET_VGX_CAPS (0x80028e) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS_MESSAGE_ID (0x8EU) + +typedef struct NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS { + NvBool isVgx; +} NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS; + + + +/* + * NV0080_CTRL_CMD_GPU_GET_SRIOV_CAPS + * + * This command is used to query GPU SRIOV capabilities + * totalVFs + * Total number of virtual functions supported. + * + * firstVfOffset + * Offset of the first VF. + * + * vfFeatureMask + * Bitmask of features managed by the guest + * + * FirstVFBar0Address + * Address of BAR0 region of first VF. + * + * FirstVFBar1Address + * Address of BAR1 region of first VF. + * + * FirstVFBar2Address + * Address of BAR2 region of first VF. + * + * bar0Size + * Size of BAR0 region on VF. + * + * bar1Size + * Size of BAR1 region on VF. + * + * bar2Size + * Size of BAR2 region on VF. + * + * b64bitBar0 + * If the VF BAR0 is 64-bit addressable. + * + * b64bitBar1 + * If the VF BAR1 is 64-bit addressable. + * + * b64bitBar2 + * If the VF BAR2 is 64-bit addressable. + * + * bSriovEnabled + * Flag for SR-IOV enabled or not. + * + * bSriovHeavyEnabled + * Flag for whether SR-IOV is enabled in standard or heavy mode. + * + * bEmulateVFBar0TlbInvalidationRegister + * Flag for whether VF's TLB Invalidate Register region needs emulation. + * + * bClientRmAllocatedCtxBuffer + * Flag for whether engine ctx buffer is managed by client RM. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV0080_CTRL_CMD_GPU_GET_SRIOV_CAPS (0x800291) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_MESSAGE_ID (0x91U) + +typedef struct NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS { + NvU32 totalVFs; + NvU32 firstVfOffset; + NvU32 vfFeatureMask; + NV_DECLARE_ALIGNED(NvU64 FirstVFBar0Address, 8); + NV_DECLARE_ALIGNED(NvU64 FirstVFBar1Address, 8); + NV_DECLARE_ALIGNED(NvU64 FirstVFBar2Address, 8); + NV_DECLARE_ALIGNED(NvU64 bar0Size, 8); + NV_DECLARE_ALIGNED(NvU64 bar1Size, 8); + NV_DECLARE_ALIGNED(NvU64 bar2Size, 8); + NvBool b64bitBar0; + NvBool b64bitBar1; + NvBool b64bitBar2; + NvBool bSriovEnabled; + NvBool bSriovHeavyEnabled; + NvBool bEmulateVFBar0TlbInvalidationRegister; + NvBool bClientRmAllocatedCtxBuffer; +} NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS; + + +// Update this macro if new HW exceeds GPU Classlist MAX_SIZE +#define NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE 160 + +#define NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 (0x800292) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID (0x92U) + +typedef struct NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS { + NvU32 numClasses; // __OUT__ + NvU32 classList[NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE]; // __OUT__ +} NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS; + +/* + * NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE + * + * Find a subdevice handle allocated under this device + */ +#define NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE (0x800293) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM_MESSAGE_ID (0x93U) + +typedef struct NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM { + NvU32 subDeviceInst; // [in] + NvHandle hSubDevice; // [out] +} NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM; + +/* + * NV0080_CTRL_CMD_GPU_GET_BRAND_CAPS + * + * This command gets branding information for the device. + * + * brands + * Mask containing branding information. A bit in this + * mask is set if the GPU has particular branding. + * + * Possible status values returned are: + * NV_OK + */ + +#define NV0080_CTRL_GPU_GET_BRAND_CAPS_QUADRO NVBIT(0) +#define NV0080_CTRL_GPU_GET_BRAND_CAPS_NVS NVBIT(1) +#define NV0080_CTRL_GPU_GET_BRAND_CAPS_TITAN NVBIT(2) + +#define NV0080_CTRL_CMD_GPU_GET_BRAND_CAPS (0x800294) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS_MESSAGE_ID (0x94U) + +typedef struct NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS { + NvU32 brands; +} NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS; + +/* + * These are the per-VF BAR1 sizes that we support in MB. + * They are used with the NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE control call and + * should match the NV_XVE_BAR1_CONFIG_SIZE register defines. + */ +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M 64 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128M 128 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256M 256 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_512M 512 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_1G 1024 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_2G 2048 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_4G 4096 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_8G 8192 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_16G 16384 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_32G 32768 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64G 65536 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G 131072 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MIN NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MAX NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G + +#define NV0080_CTRL_GPU_VGPU_NUM_VFS_INVALID NV_U32_MAX + +/* + * NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE + * + * @brief Resize BAR1 per-VF on the given GPU + * vfBar1SizeMB[in] size of per-VF BAR1 size in MB + * numVfs[out] number of VFs that can be created given the new BAR1 size + */ +#define NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE (0x800296) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS_MESSAGE_ID (0x96U) + +typedef struct NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS { + NvU32 vfBar1SizeMB; + NvU32 numVfs; +} NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS; + +/* _ctrl0080gpu_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h new file mode 100644 index 0000000..2592559 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h @@ -0,0 +1,275 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080gr.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +typedef struct NV0080_CTRL_GR_ROUTE_INFO { + NvU32 flags; + NV_DECLARE_ALIGNED(NvU64 route, 8); +} NV0080_CTRL_GR_ROUTE_INFO; + +/* NV01_DEVICE_XX/NV03_DEVICE gr engine control commands and parameters */ + +/** + * NV0080_CTRL_CMD_GR_GET_CAPS + * + * This command returns the set of graphics capabilities for the device + * in the form of an array of unsigned bytes. Graphics capabilities + * include supported features and required workarounds for the graphics + * engine(s) within the device, each represented by a byte offset into the + * table and a bit position within that byte. + * + * capsTblSize + * This parameter specifies the size in bytes of the caps table. + * This value should be set to NV0080_CTRL_GR_CAPS_TBL_SIZE. + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the graphics caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + */ +#define NV0080_CTRL_CMD_GR_GET_CAPS (0x801102) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GR_GET_CAPS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_GR_GET_CAPS_PARAMS { + NvU32 capsTblSize; + NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); +} NV0080_CTRL_GR_GET_CAPS_PARAMS; + +/* extract cap bit setting from tbl */ +#define NV0080_CTRL_GR_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + + + +/* + * Size in bytes of gr caps table. This value should be one greater + * than the largest byte_index value above. + */ +#define NV0080_CTRL_GR_CAPS_TBL_SIZE 23 + + + +/* + * NV0080_CTRL_CMD_GR_INFO + * + * This structure represents a single 32bit graphics engine value. Clients + * request a particular graphics engine value by specifying a unique bus + * information index. + * + * Legal graphics information index values are: + * NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS + * This index is used to request the number of clip IDs supported by + * the device. + * NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 + * This index is used to request the minimum number of attributes that + * need to be enabled to avoid bug 261894. A return value of 0 + * indicates that there is no minimum and the bug is not present on this + * system. + */ +typedef struct NV0080_CTRL_GR_INFO { + NvU32 index; + NvU32 data; +} NV0080_CTRL_GR_INFO; + +/* valid graphics info index values */ +#define NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS (0x00000000) +#define NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 (0x00000001) +#define NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK (0x00000002) +#define NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT (0x00000003) +#define NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT (0x00000004) +#define NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE (0x00000005) +#define NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT (0x00000006) +#define NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT (0x00000007) +#define NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR (0x00000008) +#define NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT (0x00000009) +#define NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT (0x0000000A) +#define NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT (0x0000000B) +#define NV0080_CTRL_GR_INFO_INDEX_SM_VERSION (0x0000000C) +#define NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM (0x0000000D) +#define NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP (0x0000000E) +#define NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES (0x0000000F) +#define NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES (0x00000010) +#define NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY (0x00000011) +#define NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY (0x00000012) +#define NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM (0x00000013) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS (0x00000014) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS (0x00000015) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS (0x00000016) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC (0x00000017) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS (0x00000018) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS (0x00000019) +#define NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED (0x0000001A) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS (0x0000001B) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC (0x0000001C) +#define NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT (0x0000001D) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES (0x0000001E) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS (0x0000001F) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC (0x00000020) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS (0x00000021) +#define NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT (0x00000022) +#define NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT (0x00000023) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS (0x00000024) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS (0x00000025) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES (0x00000026) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC (0x00000027) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP (0x00000028) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC (0x00000029) +#define NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC (0x0000002A) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP (0x0000002B) +#define NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT (0x0000002C) +#define NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT (0x0000002D) +#define NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT (0x0000002E) + + +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC (0x00000032) + +/* When adding a new INDEX, please update MAX_SIZE accordingly + * NOTE: 0080 functionality is merged with 2080 functionality, so this max size + * reflects that. + */ +#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000032) +#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x33) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */ + +/* + * NV0080_CTRL_CMD_GR_GET_INFO + * + * This command returns graphics engine information for the associate GPU. + * Request to retrieve graphics information use a list of one or more + * NV0080_CTRL_GR_INFO structures. + * + * grInfoListSize + * This field specifies the number of entries on the caller's + * grInfoList. + * grInfoList + * This field specifies a pointer in the caller's address space + * to the buffer into which the bus information is to be returned. + * This buffer must be at least as big as grInfoListSize multiplied + * by the size of the NV0080_CTRL_GR_INFO structure. + */ +#define NV0080_CTRL_CMD_GR_GET_INFO (0x801104) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV0080_CTRL_GR_GET_INFO_PARAMS { + NvU32 grInfoListSize; + NV_DECLARE_ALIGNED(NvP64 grInfoList, 8); +} NV0080_CTRL_GR_GET_INFO_PARAMS; + +/* + * NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE + * This command gets the current partition mode of a TSG context. + * + * NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE + * This command sets the partition mode of a TSG context. + * + * NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS + * This structure defines the parameters used for TPC partitioning mode SET/GET commands + * + * hChannelGroup [IN] + * RM Handle to the TSG + * + * mode [IN/OUT] + * Partitioning mode enum value + * For the SET cmd, this is an input parameter + * For the GET cmd, this is an output parameter + * + * bEnableAllTpcs [IN] + * Flag to enable all TPCs by default + * + * grRouteInfo[IN] + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + */ +#define NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE (0x801107) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | 0x7" */ + +#define NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x801108) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | 0x8" */ + +/* Enum for listing TPC partitioning modes */ +typedef enum NV0080_CTRL_GR_TPC_PARTITION_MODE { + NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE = 0, + NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC = 1, + NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC = 2, +} NV0080_CTRL_GR_TPC_PARTITION_MODE; + +typedef struct NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS { + NvHandle hChannelGroup; // [in] + NV0080_CTRL_GR_TPC_PARTITION_MODE mode; // [in/out] + NvBool bEnableAllTpcs; // [in/out] + NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); // [in] +} NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS; + +/** + * NV0080_CTRL_CMD_GR_GET_CAPS_V2 + * + * This command returns the same set of graphics capabilities for the device + * as @ref NV0080_CTRL_CMD_GR_GET_CAPS. The difference is in the structure + * NV0080_CTRL_GR_GET_INFO_V2_PARAMS, which contains a statically sized array, + * rather than a caps table pointer and a caps table size in + * NV0080_CTRL_GR_GET_INFO_PARAMS. Additionally, + * NV0080_CTRL_GR_GET_INFO_V2_PARAMS contains a parameter for specifying routing + * information, used for MIG. + * + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the graphics caps bits will be written by the RM. + * The caps table is an array of unsigned bytes. + * + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + * bCapsPopulated + * This parameter indicates that the capsTbl has been partially populated by + * previous calls to NV0080_CTRL_CMD_GR_GET_CAPS_V2 on other subdevices. + */ +#define NV0080_CTRL_CMD_GR_GET_CAPS_V2 (0x801109) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV0080_CTRL_GR_GET_CAPS_V2_PARAMS { + NvU8 capsTbl[NV0080_CTRL_GR_CAPS_TBL_SIZE]; + NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvBool bCapsPopulated; +} NV0080_CTRL_GR_GET_CAPS_V2_PARAMS; + +#define NV0080_CTRL_CMD_GR_GET_INFO_V2 (0x801110) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV0080_CTRL_GR_GET_INFO_V2_PARAMS { + NvU32 grInfoListSize; + NV0080_CTRL_GR_INFO grInfoList[NV0080_CTRL_GR_INFO_MAX_SIZE]; + NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV0080_CTRL_GR_GET_INFO_V2_PARAMS; + +/* _ctrl0080gr_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h new file mode 100644 index 0000000..096c451 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h @@ -0,0 +1,112 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080host.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE host control commands and parameters */ + +/* + * NV0080_CTRL_CMD_HOST_GET_CAPS + * + * This command returns the set of host capabilities for the device + * in the form of an array of unsigned bytes. Host capabilities + * include supported features and required workarounds for the host-related + * engine(s) within the device, each represented by a byte offset into + * the table and a bit position within that byte. + * + * capsTblSize + * This parameter specifies the size in bytes of the caps table. + * This value should be set to NV0080_CTRL_HOST_CAPS_TBL_SIZE. + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the host caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_POINTER + */ +#define NV0080_CTRL_CMD_HOST_GET_CAPS (0x801401) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_HOST_INTERFACE_ID << 8) | NV0080_CTRL_HOST_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_HOST_GET_CAPS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0080_CTRL_HOST_GET_CAPS_PARAMS { + NvU32 capsTblSize; + NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); +} NV0080_CTRL_HOST_GET_CAPS_PARAMS; + +/* extract cap bit setting from tbl */ +#define NV0080_CTRL_HOST_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* caps format is byte_index:bit_mask */ +#define NV0080_CTRL_HOST_CAPS_SEMA_ACQUIRE_BUG_105665 0:0x01 +#define NV0080_CTRL_HOST_CAPS_DUP_CMPLT_BUG_126020 0:0x02 +/* + * This bit indicates whether CPU mappings obtained with NvRmMapMemory() are + * coherent with the GPU. When this bit is _not_ set, all mappings are to the + * "raw" memory; i.e., they behave as it the NVOS33_FLAGS_MAPPING_DIRECT flag + * were used on a sysmem mapping. + */ +#define NV0080_CTRL_HOST_CAPS_GPU_COHERENT_MAPPING_SUPPORTED 0:0x04 +#define NV0080_CTRL_HOST_CAPS_SYS_SEMA_DEADLOCK_BUG_148216 0:0x08 +#define NV0080_CTRL_HOST_CAPS_SLOWSLI 0:0x10 +#define NV0080_CTRL_HOST_CAPS_SEMA_READ_ONLY_BUG 0:0x20 +#define NV0080_CTRL_HOST_CAPS_LARGE_NONCOH_UPSTR_WRITE_BUG_114871 0:0x40 +#define NV0080_CTRL_HOST_CAPS_LARGE_UPSTREAM_WRITE_BUG_115115 0:0x80 +#define NV0080_CTRL_HOST_CAPS_SEP_VIDMEM_PB_NOTIFIERS_BUG_83923 1:0x02 +#define NV0080_CTRL_HOST_CAPS_P2P_4_WAY 1:0x08 // Deprecated +#define NV0080_CTRL_HOST_CAPS_P2P_8_WAY 1:0x10 // Deprecated +#define NV0080_CTRL_HOST_CAPS_P2P_DEADLOCK_BUG_203825 1:0x20 // Deprecated +#define NV0080_CTRL_HOST_CAPS_VIRTUAL_P2P 1:0x40 +#define NV0080_CTRL_HOST_CAPS_BUG_254580 1:0x80 +#define NV0080_CTRL_HOST_CAPS_COMPRESSED_BL_P2P_BUG_257072 2:0x02 // Deprecated +#define NV0080_CTRL_HOST_CAPS_CROSS_BLITS_BUG_270260 2:0x04 // Deprecated +/* unused 2:0x08 */ +#define NV0080_CTRL_HOST_CAPS_MEM2MEM_BUG_365782 2:0x10 +#define NV0080_CTRL_HOST_CAPS_CPU_WRITE_WAR_BUG_420495 2:0x20 +#define NV0080_CTRL_HOST_CAPS_EXPLICIT_CACHE_FLUSH_REQD 2:0x40 +#define NV0080_CTRL_HOST_CAPS_BAR1_READ_DEADLOCK_BUG_511418 2:0x80 // Deprecated + +/* size in bytes of host caps table */ +#define NV0080_CTRL_HOST_CAPS_TBL_SIZE 3 + +#define NV0080_CTRL_CMD_HOST_GET_CAPS_V2 (0x801402) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_HOST_INTERFACE_ID << 8) | NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS { + NvU8 capsTbl[NV0080_CTRL_HOST_CAPS_TBL_SIZE]; +} NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS; + +/* _ctrl0080host_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h new file mode 100644 index 0000000..8607cc2 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h @@ -0,0 +1,103 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080internal.finn +// + +#include "nvlimits.h" +#include "ctrl0080gr.h" +#include "ctrl/ctrl0080/ctrl0080base.h" +#include "ctrl/ctrl0080/ctrl0080perf.h" + + + + +/*! + * @ref NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE + */ +#define NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE (0x802002) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID" */ + + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS { + NV_DECLARE_ALIGNED(NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS params, 8); +} NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS; + + +/*! + * @ref NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE + */ +#define NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE (0x802003) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID" */ + + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS { + NV_DECLARE_ALIGNED(NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS params, 8); +} NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS; + + +/*! + * @ref NV0080_CTRL_CMD_PERF_CUDA_LIMIT_SET_CONTROL + */ +#define NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_SET_CONTROL (0x802009) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS_MESSAGE_ID" */ + + +/*! + * This command disables cuda limit activation at teardown of the client. + */ +#define NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE (0x802004) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x4" */ + +/*! + * @ref NV0080_CTRL_CMD_PERF_SLI_GPU_BOOST_SYNC_SET_CONTROL + */ +#define NV0080_CTRL_CMD_INTERNAL_PERF_SLI_GPU_BOOST_SYNC_SET_CONTROL (0x802007) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID" */ + + + +/*! + * @ref NV0080_CTRL_CMD_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT + */ +#define NV0080_CTRL_CMD_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT (0x802006) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS { + NvU8 powerDisconnectedGpuBus[NV_MAX_DEVICES]; + NvU8 powerDisconnectedGpuCount; +} NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS; + +/* ctrl0080internal_h */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h new file mode 100644 index 0000000..60af5a6 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h @@ -0,0 +1,73 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080msenc.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE MSENC control commands and parameters */ + +/* + * NV0080_CTRL_CMD_MSENC_GET_CAPS + * + * This command returns the set of MSENC capabilities for the device + * in the form of an array of unsigned bytes. MSENC capabilities + * include supported features and required workarounds for the MSENC-related + * engine(s) within the device, each represented by a byte offset into + * the table and a bit position within that byte. + * + * capsTblSize + * This parameter specifies the size in bytes of the caps table. + * This value should be set to NV0080_CTRL_MSENC_CAPS_TBL_SIZE. + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the MSENC caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_MSENC_GET_CAPS (0x801b01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_MSENC_INTERFACE_ID << 8) | NV0080_CTRL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0080_CTRL_MSENC_GET_CAPS_PARAMS { + NvU32 capsTblSize; + NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); +} NV0080_CTRL_MSENC_GET_CAPS_PARAMS; + + + +/* size in bytes of MSENC caps table */ +#define NV0080_CTRL_MSENC_CAPS_TBL_SIZE 4 + +/* _ctrl0080msenc_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h new file mode 100644 index 0000000..689fe4b --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h @@ -0,0 +1,75 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080nvjpg.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE NVJPG control commands and parameters */ + + + +/* + * Size in bytes of NVJPG caps table. This value should be one greater + * than the largest byte_index value above. + */ +#define NV0080_CTRL_NVJPG_CAPS_TBL_SIZE 9 + +/* + * NV0080_CTRL_CMD_NVJPG_GET_CAPS_V2 + * + * This command returns the set of NVJPG capabilities for the device + * in the form of an array of unsigned bytes. NVJPG capabilities + * include supported features of the NVJPG engine(s) within the device, + * each represented by a byte offset into the table and a bit position within + * that byte. + * + * [out] capsTbl + * This caps table array is where the NVJPG caps bits will be transferred + * by the RM. The caps table is an array of unsigned bytes. + * instanceId + * This parameter specifies the instance Id of NVDEC for which + * cap bits are requested. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_NVJPG_GET_CAPS_V2 (0x801f02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_NVJPG_INTERFACE_ID << 8) | NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS { + NvU8 capsTbl[NV0080_CTRL_NVJPG_CAPS_TBL_SIZE]; + NvU32 instanceId; +} NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS; + +/* _ctrl0080NVJPG_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h new file mode 100644 index 0000000..3001076 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080perf.finn +// + +#define NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS { + NvBool bActivate; +} NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS; + +#define NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS { + NvBool bCudaLimit; +} NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS; + + + +/* _ctrl0080perf_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h new file mode 100644 index 0000000..100a612 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h @@ -0,0 +1,57 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080rc.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE gpu control commands and parameters */ + +/* + * NV0080_CTRL_CMD_RC_DISABLE_RESET_CHANNEL_CALLBACK + * + * This command prevents RM from using callbacks when resetting a channel due + * to a page fault. + * + * Possible status return values are: + * NV_OK + */ +#define NV0080_CTRL_CMD_RC_DISABLE_RESET_CHANNEL_CALLBACK (0x801d01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_RC_INTERFACE_ID << 8) | 0x1" */ + +/* + * NV0080_CTRL_CMD_RC_ENABLE_RESET_CHANNEL_CALLBACK + * + * This command permits RM to use callbacks when resetting a channel due + * to a page fault. + * + * Possible status return values are: + * NV_OK + */ +#define NV0080_CTRL_CMD_RC_ENABLE_RESET_CHANNEL_CALLBACK (0x801d02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_RC_INTERFACE_ID << 8) | 0x2" */ + +/* _ctrl0080rc_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h new file mode 100644 index 0000000..fbbdf73 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h @@ -0,0 +1,93 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0080/ctrl0080unix.finn +// + +#include "ctrl/ctrl0080/ctrl0080base.h" + +/* NV01_DEVICE_XX/NV03_DEVICE UNIX-specific control commands and parameters */ + +/* + * NV0080_CTRL_CMD_OS_UNIX_VT_SWITCH + * + * This command notifies RM to save or restore the current console state. It is + * intended to be called just before the display driver starts using the display + * engine, and after it has finished using it. + * + * cmd + * Indicates which operation should be performed. + * + * SAVE_VT_STATE + * Records the current state of the console, to be restored later. + * RESTORE_VT_STATE + * Restores the previously-saved console state. + * + * fbInfo + * Returns information about the system's framebuffer console, if one + * exists. If no console is present, all fields will be zero. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_OS_UNIX_VT_SWITCH (0x801e01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS { + NvU32 cmd; /* in */ +} NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS; + +/* Called when the display driver needs RM to save the console data, + * which will be used in RM based console restore */ +#define NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_SAVE_VT_STATE (0x00000001) + +/* Called when the display driver needs RM to restore the console */ +#define NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_RESTORE_VT_STATE (0x00000002) + +/* Called when the display driver has restored the console -- RM doesn't + * need to do anything further, but needs to be informed to avoid turning the + * GPU off and thus destroying the console state. */ +#define NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_CONSOLE_RESTORED (0x00000003) + +#define NV0080_CTRL_CMD_OS_UNIX_VT_GET_FB_INFO (0x801e02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS { + NvU32 subDeviceInstance; /* out */ + + NvU16 width; /* out */ + NvU16 height; /* out */ + NvU16 depth; /* out */ + NvU16 pitch; /* out */ +} NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS; + +/* _ctrl0080unix_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0090.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0090.h new file mode 100644 index 0000000..83af684 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl0090.h @@ -0,0 +1,130 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0090.finn +// + + + +// NV0080_CTRL_GR_TPC_PARTITION_MODE +#include "ctrl/ctrl0080/ctrl0080gr.h" + +/*! + * This file defines control call interfaces for the KernelGraphicsContext + * objects Each channel running within a TSG contains a HW context represented + * by the above object(s). GR permits multiple channels to share a single + * context, and these APIs operate upon that context and may be issued from any + * TSG, channel, or context handle. + */ + +/* + * NV0090_CTRL_CMD_NULL + * + * @brief This command does nothing. + * + * @return NV_OK + */ +#define NV0090_CTRL_CMD_NULL (0x900100) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x0" */ + +/*! + * NV0090_CTRL_CMD_SET_TPC_PARTITION_MODE + * NV0090_CTRL_CMD_GET_TPC_PARTITION_MODE + * + * @brief sets or gets the TPC partition mode for this context + * + * @param[in/out] mode Partitioning mode enum value + * @param[in/out] bEnableAllTpcs Flag to enable all TPCs by default + * + * @return NV_OK on success + * NV_ERR_OBJECT_NOT_FOUND if issued on non-GR ctx + */ +typedef struct NV0090_CTRL_TPC_PARTITION_MODE_PARAMS { + NV0080_CTRL_GR_TPC_PARTITION_MODE mode; + NvBool bEnableAllTpcs; +} NV0090_CTRL_TPC_PARTITION_MODE_PARAMS; + +#define NV0090_CTRL_CMD_SET_TPC_PARTITION_MODE (0x900101) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x1" */ +#define NV0090_CTRL_CMD_INTERNAL_SET_TPC_PARTITION_MODE (0x900102) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x2" */ +#define NV0090_CTRL_CMD_GET_TPC_PARTITION_MODE (0x900103) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x3" */ +#define NV0090_CTRL_CMD_INTERNAL_GET_TPC_PARTITION_MODE (0x900104) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x4" */ + +/** + * NV0090_CTRL_GET_MMU_DEBUG_MODE + * + * @brief retrieve the current MMU debug mode for the grctx according to the HW + * + * @param[out] bMode current MMU debug mode + */ +typedef struct NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS { + NvBool bMode; +} NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS; + +#define NV0090_CTRL_CMD_GET_MMU_DEBUG_MODE (0x900105) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x5" */ +#define NV0090_CTRL_CMD_INTERNAL_GET_MMU_DEBUG_MODE (0x900106) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x6" */ + +/** + * NV0090_CTRL_PROGRAM_VIDEMEM_PROMOTE + * + * @brief This control call is used to set the promotion policies to vidmem through + * per-TSG config + * + * If the request is for less bytes than the current PROMOTE setting, then + * the request is promoted. For example if the request size is for 32B and + * 64B promotion is turned on for that unit, then the request to FB will be + * for all the bytes to the 64B aligned address. + * + * @param[in] l1 + * An input parameter which represents VIDMEM_L1_PROMOTE[17:16]. + * @param[in] t1 + * An input parameter which represents VIDMEM_T1_PROMOTE[19:18]. + * + * @return NV_OK on success, or + * NV_ERR_INVALID_ARGUMENT or + * NV_ERR_INVALID_STATE + */ +typedef enum NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE { + NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_NONE = 0, + NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_64B = 1, + NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_128B = 2, +} NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE; + +typedef struct NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD { + NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE size; +} NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD; + +#define NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS { + NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD l1; + NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD t1; +} NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS; + +#define NV0090_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE (0x900107) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x7" */ +#define NV0090_CTRL_CMD_INTERNAL_PROGRAM_VIDMEM_PROMOTE (0x900108) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x8" */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl00f8.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl00f8.h new file mode 100644 index 0000000..595b021 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl00f8.h @@ -0,0 +1,218 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl00f8.finn +// + +#include "ctrl/ctrlxxxx.h" + +#define NV00F8_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x00f8, NV00F8_CTRL_##cat, idx) + +/* NV00F8 command categories (6bits) */ +#define NV00F8_CTRL_RESERVED (0x00U) +#define NV00F8_CTRL_FABRIC (0x01U) + +/* + * NV00F8_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV00F8_CTRL_CMD_NULL (0xf80000U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV00F8_CTRL_CMD_GET_INFO + * + * Queries memory allocation attributes. + * + * size [OUT] + * Size of the allocation. + * + * pageSize [OUT] + * Page size of the allocation. + * + * allocFlags [OUT] + * Flags passed during the allocation. + * + * physAttrs [OUT] + * Physical attributes associated with memory allocation. + * For flexible mappings, it is not possible to retrieve this information, + * behavior is undefined (returns all zeros). + */ +#define NV00F8_CTRL_CMD_GET_INFO (0xf80101U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_GET_INFO_PARAMS_MESSAGE_ID" */ + +/* + * addressSpace + * Same as NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE. + * + * compressionCoverage + * Same as NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE. + */ +typedef struct NV_PHYSICAL_MEMORY_ATTRS { + NvU32 addressSpace; + NvU32 compressionCoverage; +} NV_PHYSICAL_MEMORY_ATTRS; + +#define NV00F8_CTRL_GET_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV00F8_CTRL_GET_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 pageSize; + NvU32 allocFlags; + NV_PHYSICAL_MEMORY_ATTRS physAttrs; +} NV00F8_CTRL_GET_INFO_PARAMS; + +/* + * NV00F8_CTRL_CMD_DESCRIBE + * + * Queries the physical attributes of the fabric memory allocation. + * + * offset [IN] + * Offset into memory allocation to query physical addresses for. + * + * totalPfns [OUT] + * Number of PFNs in memory allocation. + * + * pfnArray [OUT] + * Array of PFNs in memory allocation (2MB page size shifted). + * + * numPfns [OUT] + * Number of valid entries in pfnArray. + * + * Note: This ctrl call is only available for kerenl mode client in vGPU platforms. + */ + +#define NV00F8_CTRL_CMD_DESCRIBE (0xf80102) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_DESCRIBE_PARAMS_MESSAGE_ID" */ + +#define NV00F8_CTRL_DESCRIBE_PFN_ARRAY_SIZE 512 + +#define NV00F8_CTRL_DESCRIBE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV00F8_CTRL_DESCRIBE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 totalPfns, 8); + NvU32 pfnArray[NV00F8_CTRL_DESCRIBE_PFN_ARRAY_SIZE]; + NvU32 numPfns; +} NV00F8_CTRL_DESCRIBE_PARAMS; + +/* + * hMemory [IN] + * Physical memory handle to be attached. + * + * offset [IN] + * Offset into the fabric object. + * Must be physical memory pagesize aligned (at least). + * + * mapOffSet [IN] + * Offset into the physical memory descriptor. + * Must be physical memory pagesize aligned. + * + * mapLength [IN] + * Length of physical memory handle to be mapped. + * Must be physical memory pagesize aligned and less than or equal to + * fabric alloc size. + */ +typedef struct NV00F8_CTRL_ATTACH_MEM_INFO { + NvHandle hMemory; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 mapOffset, 8); + NV_DECLARE_ALIGNED(NvU64 mapLength, 8); +} NV00F8_CTRL_ATTACH_MEM_INFO; + +/* + * NV00F8_CTRL_CMD_ATTACH_MEM + * + * Attaches physical memory info to the fabric object. + * + * memInfos [IN] + * Memory infos to be attached. + * + * numMemInfos [IN] + * Number of memory infos to be attached. + * + * flags [IN] + * For future use only. Must be zero for now. + * + * numAttached [OUT] + * Successful attach count (returns a valid value on error too) + * + * Restrictions: + * a. Physical memory with 2MB pagesize is allowed + * b. Only vidmem physical memory handle can be attached + * c. Supported only for flexible fabric objects. + */ +#define NV00F8_CTRL_CMD_ATTACH_MEM (0xf80103) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_ATTACH_MEM_PARAMS_MESSAGE_ID" */ + +#define NV00F8_MAX_ATTACHABLE_MEM_INFOS 64 + +#define NV00F8_CTRL_ATTACH_MEM_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV00F8_CTRL_ATTACH_MEM_PARAMS { + NV_DECLARE_ALIGNED(NV00F8_CTRL_ATTACH_MEM_INFO memInfos[NV00F8_MAX_ATTACHABLE_MEM_INFOS], 8); + NvU16 numMemInfos; + NvU32 flags; + NvU16 numAttached; +} NV00F8_CTRL_ATTACH_MEM_PARAMS; + +/* + * NV00F8_CTRL_CMD_DETACH_MEM + * + * Detaches physical memory handle from the fabric object. + * + * offsets [IN] + * Offsets at which memory was attached. + * + * numOffsets [IN] + * Number of offsets to be detached. + * + * flags [IN] + * For future use only. Must be zero for now. + * + * numDetached [OUT] + * Successful detach count (returns a valid value on error too) + */ +#define NV00F8_CTRL_CMD_DETACH_MEM (0xf80104) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_DETACH_MEM_PARAMS_MESSAGE_ID" */ + +#define NV00F8_MAX_DETACHABLE_OFFSETS 64 + +#define NV00F8_CTRL_DETACH_MEM_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV00F8_CTRL_DETACH_MEM_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offsets[NV00F8_MAX_DETACHABLE_OFFSETS], 8); + NvU16 numOffsets; + NvU32 flags; + NvU16 numDetached; +} NV00F8_CTRL_DETACH_MEM_PARAMS; + +/* _ctrl00f8_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl00fd.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl00fd.h new file mode 100644 index 0000000..7ba86f8 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl00fd.h @@ -0,0 +1,160 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl00fd.finn +// + +#include "ctrl/ctrlxxxx.h" + +#define NV00FD_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x00fd, NV00FD_CTRL_##cat, idx) + +/* NV00FD command categories (6bits) */ +#define NV00FD_CTRL_RESERVED (0x00) +#define NV00FD_CTRL_MULTICAST_FABRIC (0x01) + +/* + * NV00FD_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV00FD_CTRL_CMD_NULL (0xfd0000) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV00FD_CTRL_CMD_GET_INFO + * + * Queries multicast memory fabric allocation attributes. + * + * alignment [OUT] + * Alignment for the allocation. + * + * allocSize [OUT] + * Size of the allocation. + * + * pageSize [OUT] + * Page size of the allocation. + * + * numMaxGpus [OUT] + * Maximum number of attachable GPUs + * + * numAttachedGpus [OUT] + * Number of GPUs currently attached + * + */ +#define NV00FD_CTRL_CMD_GET_INFO (0xfd0101) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV00FD_CTRL_GET_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV00FD_CTRL_GET_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 alignment, 8); + NV_DECLARE_ALIGNED(NvU64 allocSize, 8); + NvU32 pageSize; + NvU32 numMaxGpus; + NvU32 numAttachedGpus; +} NV00FD_CTRL_GET_INFO_PARAMS; + +/* + * NV00FD_CTRL_CMD_ATTACH_MEM + * + * Attaches the physical memory handle and in turn the memory + * owner of the physical memory to the Multicast FLA object. + * + * hSubdevice [IN] + * Subdevice handle of the owner GPU + * + * hMemory [IN] + * Physical memory handle to be attached. + * + * offset [IN] + * Offset into the MCFLA object. (Must be zero for now, maybe used in future) + * Must be MCFLA pagesize aligned. + * + * mapOffSet [IN] + * Offset into the physical memory descriptor. + * Must be physical memory pagesize aligned. + * + * mapLength [IN] + * Length of physical memory handle to be mapped. + * Must be physical memory pagesize aligned and less than or equal to + * MCFLA alloc size + * + * flags [IN] + * For future use only. Must be zero for now. + * + * devDescriptor [IN] + * devDescriptor is a file descriptor for unix RM clients, but a void + * pointer for windows RM clients. It is transparent to RM clients i.e. RM's + * user-mode shim populates this field on behalf of clients. + * + * Restrictions: + * a. Memory belonging to only NVSwitch P2P supported GPUs + * which can do multicast can be attached + * b. Physical memory with 2MB pagesize is allowed + * c. Memory of an already attached GPU should not be attached + * d. Only vidmem physical memory handle can be attached + * + */ +#define NV00FD_CTRL_CMD_ATTACH_MEM (0xfd0102) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_ATTACH_MEM_PARAMS_MESSAGE_ID" */ + +#define NV00FD_CTRL_ATTACH_MEM_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV00FD_CTRL_ATTACH_MEM_PARAMS { + NvHandle hSubdevice; + NvHandle hMemory; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 mapOffset, 8); + NV_DECLARE_ALIGNED(NvU64 mapLength, 8); + NvU32 flags; + NV_DECLARE_ALIGNED(NvU64 devDescriptor, 8); +} NV00FD_CTRL_ATTACH_MEM_PARAMS; + +/* + * NV00FD_CTRL_CMD_REGISTER_EVENT + * + * Allows clients to optionally register for events after the Multicast + * FLA object is duped under another client. + * + * pOsEvent [IN] + * OS event handle created with NvRmAllocOsEvent(). + * + */ +#define NV00FD_CTRL_CMD_REGISTER_EVENT (0xfd0103) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_REGISTER_EVENT_PARAMS_MESSAGE_ID" */ + +#define NV00FD_CTRL_REGISTER_EVENT_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV00FD_CTRL_REGISTER_EVENT_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pOsEvent, 8); +} NV00FD_CTRL_REGISTER_EVENT_PARAMS; + +/* _ctrl00fd_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl00fe.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl00fe.h new file mode 100644 index 0000000..2be1a04 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl00fe.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl00fe.finn +// + +#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_FLAG_PAGE_KIND_SOURCE_ALLOCATION 0:0 +#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_FLAG_PAGE_KIND_SOURCE_ALLOCATION_PHYSICAL (0x00000000U) +#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_FLAG_PAGE_KIND_SOURCE_ALLOCATION_VIRTUAL (0x00000001U) + +typedef struct NV00FE_CTRL_PAGING_OPERATION { + NvHandle hVirtualMemory; + NV_DECLARE_ALIGNED(NvU64 virtualOffset, 8); + NvHandle hPhysicalMemory; + NV_DECLARE_ALIGNED(NvU64 physicalOffset, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 flags; +} NV00FE_CTRL_PAGING_OPERATION; + +/* + * NV00FE_CTRL_CMD_SUBMIT_PAGING_OPERATIONS + * + * Execute a list of paging operations + * Page size is determined by the virtual allocation + * Offsets/sizes must respect the page size + * + */ +#define NV00FE_CTRL_CMD_SUBMIT_PAGING_OPERATIONS (0xfe0002U) /* finn: Evaluated from "(FINN_NV_MEMORY_MAPPER_INTERFACE_ID << 8) | NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS_MESSAGE_ID" */ + +#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_MAX_COUNT (0x00010000U) + +#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS { + NvU32 pagingOpsCount; + NV_DECLARE_ALIGNED(NvP64 pagingOps, 8); +} NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS; + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080.h new file mode 100644 index 0000000..05f19cf --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080.h @@ -0,0 +1,84 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080.finn +// + + + + +#include "ctrl/ctrlxxxx.h" +#include "ctrl2080/ctrl2080gpu.h" +#include "ctrl2080/ctrl2080fuse.h" +#include "ctrl2080/ctrl2080event.h" +#include "ctrl2080/ctrl2080tmr.h" +#include "ctrl2080/ctrl2080bios.h" +#include "ctrl2080/ctrl2080mc.h" +#include "ctrl2080/ctrl2080fifo.h" +#include "ctrl2080/ctrl2080fb.h" + + +#include "ctrl2080/ctrl2080gr.h" +#include "ctrl2080/ctrl2080bus.h" +#include "ctrl2080/ctrl2080thermal.h" +#include "ctrl2080/ctrl2080fan.h" +#include "ctrl2080/ctrl2080i2c.h" +#include "ctrl2080/ctrl2080internal.h" +#include "ctrl2080/ctrl2080spi.h" +#include "ctrl2080/ctrl2080gpio.h" +#include "ctrl2080/ctrl2080clk.h" +#include "ctrl2080/ctrl2080perf.h" +#include "ctrl2080/ctrl2080perf_cf.h" + + +#include "ctrl2080/ctrl2080rc.h" +#include "ctrl2080/ctrl2080dma.h" +#include "ctrl2080/ctrl2080dmabuf.h" +#include "ctrl2080/ctrl2080nvd.h" +#include "ctrl2080/ctrl2080boardobj.h" +#include "ctrl2080/ctrl2080pmgr.h" +#include "ctrl2080/ctrl2080power.h" +#include "ctrl2080/ctrl2080lpwr.h" +#include "ctrl2080/ctrl2080acr.h" +#include "ctrl2080/ctrl2080ce.h" +#include "ctrl2080/ctrl2080nvlink.h" +#include "ctrl2080/ctrl2080flcn.h" +#include "ctrl2080/ctrl2080volt.h" +#include "ctrl2080/ctrl2080ecc.h" +#include "ctrl2080/ctrl2080cipher.h" +#include "ctrl2080/ctrl2080fla.h" +#include "ctrl2080/ctrl2080gsp.h" + + +#include "ctrl2080/ctrl2080grmgr.h" +#include "ctrl2080/ctrl2080ucodefuzzer.h" +#include "ctrl2080/ctrl2080vgpumgrinternal.h" +#include "ctrl2080/ctrl2080hshub.h" +/* include appropriate os-specific command header */ + + +#include "ctrl2080/ctrl2080unix.h" diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080acr.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080acr.h new file mode 100644 index 0000000..322e119 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080acr.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080acr.finn +// + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h new file mode 100644 index 0000000..7df6a6d --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h @@ -0,0 +1,112 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080base.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV20_SUBDEVICE_XX control commands and parameters */ + +#define NV2080_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x2080, NV2080_CTRL_##cat, idx) + +/* Subdevice command categories (6bits) */ +#define NV2080_CTRL_RESERVED (0x00) +#define NV2080_CTRL_GPU (0x01) +#define NV2080_CTRL_GPU_LEGACY_NON_PRIVILEGED (0x81) /* finn: Evaluated from "(NV2080_CTRL_GPU | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_FUSE (0x02) +#define NV2080_CTRL_FUSE_LEGACY_NON_PRIVILEGED (0x82) /* finn: Evaluated from "(NV2080_CTRL_FUSE | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_EVENT (0x03) +#define NV2080_CTRL_TIMER (0x04) +#define NV2080_CTRL_THERMAL (0x05) +#define NV2080_CTRL_THERMAL_LEGACY_PRIVILEGED (0xc5) /* finn: Evaluated from "(NV2080_CTRL_THERMAL | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */ +#define NV2080_CTRL_THERMAL_LEGACY_NON_PRIVILEGED (0x85) /* finn: Evaluated from "(NV2080_CTRL_THERMAL | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_I2C (0x06) +#define NV2080_CTRL_EXTI2C (0x07) +#define NV2080_CTRL_BIOS (0x08) +#define NV2080_CTRL_CIPHER (0x09) +#define NV2080_CTRL_INTERNAL (0x0A) +#define NV2080_CTRL_CLK_LEGACY_PRIVILEGED (0xd0) /* finn: Evaluated from "(NV2080_CTRL_CLK | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */ +#define NV2080_CTRL_CLK_LEGACY_NON_PRIVILEGED (0x90) /* finn: Evaluated from "(NV2080_CTRL_CLK | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_CLK (0x10) +#define NV2080_CTRL_FIFO (0x11) +#define NV2080_CTRL_GR (0x12) +#define NV2080_CTRL_FB (0x13) +#define NV2080_CTRL_MC (0x17) +#define NV2080_CTRL_BUS (0x18) +#define NV2080_CTRL_PERF_LEGACY_PRIVILEGED (0xe0) /* finn: Evaluated from "(NV2080_CTRL_PERF | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */ +#define NV2080_CTRL_PERF_LEGACY_NON_PRIVILEGED (0xa0) /* finn: Evaluated from "(NV2080_CTRL_PERF | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_PERF (0x20) +#define NV2080_CTRL_NVIF (0x21) +#define NV2080_CTRL_RC (0x22) +#define NV2080_CTRL_GPIO (0x23) +#define NV2080_CTRL_GPIO_LEGACY_NON_PRIVILEGED (0xa3) /* finn: Evaluated from "(NV2080_CTRL_GPIO | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_NVD (0x24) +#define NV2080_CTRL_DMA (0x25) +#define NV2080_CTRL_PMGR (0x26) +#define NV2080_CTRL_PMGR_LEGACY_PRIVILEGED (0xe6) /* finn: Evaluated from "(NV2080_CTRL_PMGR | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */ +#define NV2080_CTRL_PMGR_LEGACY_NON_PRIVILEGED (0xa6) /* finn: Evaluated from "(NV2080_CTRL_PMGR | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_POWER (0x27) +#define NV2080_CTRL_POWER_LEGACY_NON_PRIVILEGED (0xa7) /* finn: Evaluated from "(NV2080_CTRL_POWER | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_LPWR (0x28) +#define NV2080_CTRL_LPWR_LEGACY_NON_PRIVILEGED (0xa8) /* finn: Evaluated from "(NV2080_CTRL_LPWR | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_LPWR_LEGACY_PRIVILEGED (0xe8) /* finn: Evaluated from "(NV2080_CTRL_LPWR | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */ +#define NV2080_CTRL_ACR (0x29) +#define NV2080_CTRL_CE (0x2A) +#define NV2080_CTRL_SPI (0x2B) +#define NV2080_CTRL_NVLINK (0x30) +#define NV2080_CTRL_FLCN (0x31) +#define NV2080_CTRL_VOLT (0x32) +#define NV2080_CTRL_VOLT_LEGACY_PRIVILEGED (0xf2) /* finn: Evaluated from "(NV2080_CTRL_VOLT | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */ +#define NV2080_CTRL_VOLT_LEGACY_NON_PRIVILEGED (0xb2) /* finn: Evaluated from "(NV2080_CTRL_VOLT | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_FAS (0x33) +#define NV2080_CTRL_ECC (0x34) +#define NV2080_CTRL_ECC_NON_PRIVILEGED (0xb4) /* finn: Evaluated from "(NV2080_CTRL_ECC | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ +#define NV2080_CTRL_FLA (0x35) +#define NV2080_CTRL_GSP (0x36) +#define NV2080_CTRL_NNE (0x37) +#define NV2080_CTRL_GRMGR (0x38) +#define NV2080_CTRL_UCODE_FUZZER (0x39) +#define NV2080_CTRL_DMABUF (0x3A) + +// per-OS categories start at highest category and work backwards +#define NV2080_CTRL_OS_WINDOWS (0x3F) +#define NV2080_CTRL_OS_MACOS (0x3E) +#define NV2080_CTRL_OS_UNIX (0x3D) + + +/* + * NV2080_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_NULL (0x20800000) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrl2080base_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h new file mode 100644 index 0000000..cf58350 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h @@ -0,0 +1,477 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080bios.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX bios-related control commands and parameters */ + + + +typedef struct NV2080_CTRL_BIOS_INFO { + NvU32 index; + NvU32 data; +} NV2080_CTRL_BIOS_INFO; + +/* Maximum number of bios infos that can be queried at once */ +#define NV2080_CTRL_BIOS_INFO_MAX_SIZE (0x0000000F) + +#define NV2080_CTRL_BIOS_INFO_INDEX_REVISION (0x00000000) +#define NV2080_CTRL_BIOS_INFO_INDEX_OEM_REVISION (0x00000001) + + + +/* + * NV2080_CTRL_CMD_BIOS_GET_INFO + * + * This command returns bios information for the associated GPU. + * Requests to retrieve bios information use a list of one or more + * NV2080_CTRL_BIOS_INFO structures. + * + * biosInfoListSize + * This field specifies the number of entries on the caller's + * biosInfoList. + * biosInfoList + * This field specifies a pointer in the caller's address space + * to the buffer into which the bios information is to be returned. + * This buffer must be at least as big as biosInfoListSize multiplied + * by the size of the NV2080_CTRL_BIOS_INFO structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV2080_CTRL_CMD_BIOS_GET_INFO (0x20800802) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | 0x2" */ + +typedef struct NV2080_CTRL_BIOS_GET_INFO_PARAMS { + NvU32 biosInfoListSize; + NV_DECLARE_ALIGNED(NvP64 biosInfoList, 8); +} NV2080_CTRL_BIOS_GET_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_BIOS_GET_INFO_V2 + * + * This command returns bios information for the associated GPU. + * Requests to retrieve bios information use a list of one or more + * NV2080_CTRL_BIOS_INFO structures. + * + * biosInfoListSize + * This field specifies the number of entries on the caller's + * biosInfoList. + * biosInfoList + * Bios information to be returned. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV2080_CTRL_CMD_BIOS_GET_INFO_V2 (0x20800810) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS { + NvU32 biosInfoListSize; + NV2080_CTRL_BIOS_INFO biosInfoList[NV2080_CTRL_BIOS_INFO_MAX_SIZE]; +} NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS; + +/* + * NV2080_CTRL_BIOS_NBSI + * + * NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH + * This is the maximum length of a given registry string input (in characters). + * + * NV2080_CTRL_BIOS_NBSI_STRING_TYPE_ASCII + * This is a value indicating the format of a registry string is ascii. + * NV2080_CTRL_BIOS_NBSI_STRING_TYPE_UNICODE + * This is a value indicating the format of a registry string is unicode. + * NV2080_CTRL_BIOS_NBSI_STRING_TYPE_HASH + * This is a value indicating a registry string is actually a pre-hashed value. + * + * NV2080_CTRL_BIOS_NBSI_REG_STRING + * This is a structure used to store a registry string object. + * The members are as follows: + * + * size + * This is the size (in bytes) of the data contained in the string. If this + * is greater than the maximum registry string length, an error will be + * returned. + * type + * This is the type of data contained in the registry string. It can be either + * ascii, unicode or a pre-hashed value. + * value + * This is the value of the string. Depending on the type, a different object + * will be used to access the data. + */ +#define NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH (0x00000100) + +#define NV2080_CTRL_BIOS_NBSI_STRING_TYPE_ASCII (0x00000000) +#define NV2080_CTRL_BIOS_NBSI_STRING_TYPE_UNICODE (0x00000001) +#define NV2080_CTRL_BIOS_NBSI_STRING_TYPE_HASH (0x00000002) + +#define NV2080_CTRL_BIOS_NBSI_MODULE_ROOT (0x00000000) +#define NV2080_CTRL_BIOS_NBSI_MODULE_RM (0x00000001) +#define NV2080_CTRL_BIOS_NBSI_MODULE_DISPLAYDRIVER (0x00000002) +#define NV2080_CTRL_BIOS_NBSI_MODULE_VIDEO (0x00000003) +#define NV2080_CTRL_BIOS_NBSI_MODULE_CPL (0x00000004) +#define NV2080_CTRL_BIOS_NBSI_MODULE_D3D (0x00000005) +#define NV2080_CTRL_BIOS_NBSI_MODULE_OGL (0x00000006) +#define NV2080_CTRL_BIOS_NBSI_MODULE_PMU (0x00000007) +#define NV2080_CTRL_BIOS_NBSI_MODULE_MODE (0x00000008) +// this should equal the last NBSI_MODULE plus 1. +#define NV2080_CTRL_BIOS_NBSI_NUM_MODULES (0x00000009) + +// +// Never use this value! It's needed for DD/Video modules, but does not correspond +// to a valid NBSI hive! +// +#define NV2080_CTRL_BIOS_NBSI_MODULE_UNKNOWN (0x80000000) + +typedef struct NV2080_CTRL_BIOS_NBSI_REG_STRING { + NvU32 size; + NvU32 type; + + union { + NvU8 ascii[NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH]; + NvU16 unicode[NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH]; + NvU16 hash; + } value; +} NV2080_CTRL_BIOS_NBSI_REG_STRING; + + +/* + * NV2080_CTRL_CMD_BIOS_GET_NBSI + * + * module + * This field specifies the given module per the MODULE_TYPES enum. + * path + * This field specifies the full path and registry node name for a + * given NBSI object. This is a maximum of 255 unicode characters, + * but may be provided as ascii or a pre-formed hash per the type + * member. The size (in bytes) of the given string/hash should be + * provided in the size member. + * + * NOTE: In the case of an incomplete path such as HKR, one may pass + * in simply the root node. E.g.: + * 1.) Normal case: HKLM\Path\Subpath + * 2.) Unknown case: HKR + * It is expected that all unknown/incomplete paths will be determined + * prior to NBSI programming! There is otherwise NO WAY to match + * the hash given by an incomplete path to that stored in NBSI! + * + * valueName + * This field specifies the registry name for a given NBSI object. + * This is a maximum of 255 unicode characters, but may be provided + * in ascii or a pre-formed hash per the type member. The size (in bytes) + * of the given string/hash should be provided in the size member. + * retBuf + * This field provides a pointer to a buffer into which the value + * retrieved from NBSI may be returned + * retSize + * This field is an input/output. It specifies the maximum size of the + * return buffer as an input, and the size of the returned data as an + * output. + * errorCode + * This field is a return value. It gives an error code representing + * failure to return a value (as opposed to failure of the call). + * This obeys the following: + * + * NV2080_CTRL_BIOS_GET_NBSI_SUCCESS + * The call has returned complete and valid data. + * NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE + * The call returned complete and valid data which is expected to override + * any stored registry settings. + * NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE + * The call returned data, but the size of the return buffer was + * insufficient to contain it. The value returned in retSize represents + * the total size necessary (in bytes) to contain the data. + * if the size was non-0, the buffer is filled with the object contents up + * to that size. Can be used with retBufOffset to use multiple calls to get + * tables of very large size. + * NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND + * The call did not find a valid NBSI object for this key. This indicates + * NBSI has no opinion and, more importantly, any data returned is identical + * to data passed in. + * + * Possible return values are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_BIOS_GET_NBSI_SUCCESS (0x00000000) +#define NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE (0x00000001) +#define NV2080_CTRL_BIOS_GET_NBSI_BAD_HASH (0xFFFFFFFA) +#define NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS (0xFFFFFFFB) +#define NV2080_CTRL_BIOS_GET_NBSI_BAD_TABLE (0xFFFFFFFC) +#define NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE (0xFFFFFFFD) +#define NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE (0xFFFFFFFE) +#define NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND (0xFFFFFFFF) + +#define NV2080_CTRL_CMD_BIOS_GET_NBSI (0x20800803) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_NBSI_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BIOS_GET_NBSI_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_BIOS_GET_NBSI_PARAMS { + NvU32 module; + NV2080_CTRL_BIOS_NBSI_REG_STRING path; + NV2080_CTRL_BIOS_NBSI_REG_STRING valueName; + NV_DECLARE_ALIGNED(NvP64 retBuf, 8); + NvU32 retSize; + NvU32 errorCode; +} NV2080_CTRL_BIOS_GET_NBSI_PARAMS; + +#define NV2080_CTRL_CMD_BIOS_GET_NBSI_V2 (0x2080080e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_BIOS_GET_NBSI_MAX_RET_SIZE (0x100) + +#define NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS { + NvU32 module; + NV2080_CTRL_BIOS_NBSI_REG_STRING path; + NV2080_CTRL_BIOS_NBSI_REG_STRING valueName; + NvU8 retBuf[NV2080_BIOS_GET_NBSI_MAX_RET_SIZE]; + NvU32 retSize; + NvU32 errorCode; +} NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS; + +/* + * NV2080_CTRL_CMD_BIOS_GET_NBSI_OBJ + * + * globType + * This field specifies the glob type wanted + * 0xffff: APItest... returns NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS + * globIndex + * Index for globType desired + * 0 = best fit + * 1..255 = actual index + * globSource + * Index to nbsi directory sources used when getting entire directory + * 0 = registry + * 1 = VBIOS + * 2 = SBIOS + * 3 = ACPI + * retBufOffset + * When making multiple calls to get the object (if retSize is too small) + * offset into real object (0=start of object) + * retBuf + * This field provides a pointer to a buffer into which the object + * retrieved from NBSI may be returned + * retSize + * This field is an input/output. It specifies the maximum size of the + * return buffer as an input, and the size of the returned data as an + * output. + * totalObjSize + * This field is an output, where the total size of the object being + * retrieved is returned. + * errorCode + * This field is a return value. It gives an error code representing + * failure to return a value (as opposed to failure of the call). + * This obeys the following: + * + * NV2080_CTRL_BIOS_GET_NBSI_SUCCESS + * The call has returned complete and valid data. + * NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE + * The call returned complete and valid data which is expected to override + * any stored registry settings. + * NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE + * The call returned data, but the size of the return buffer was + * insufficient to contain it. The value returned in retSize represents + * the total size necessary (in bytes) to contain the data. + * NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND + * The call did not find a valid NBSI object for this key. This indicates + * NBSI has no opinion and, more importantly, any data returned is identical + * to data passed in. + * + * Possible return values are: + * NV2080_CTRL_BIOS_GET_NBSI_SUCCESS + * NV2080_CTRL_BIOS_GET_NBSI_APITEST_NODIRACCESS + * NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS + * NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE + * NV2080_CTRL_BIOS_GET_NBSI_BAD_TABLE + * NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE + * NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND + */ +#define NV2080_CTRL_CMD_BIOS_GET_NBSI_OBJ (0x20800806) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS { + NvU16 globType; + NvU8 globIndex; + NvU16 globSource; + NvU32 retBufOffset; + NV_DECLARE_ALIGNED(NvP64 retBuf, 8); + NvU32 retSize; + NvU32 totalObjSize; + NvU32 errorCode; +} NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS; + +#define GLOB_TYPE_GET_NBSI_DIR 0xfffe +#define GLOB_TYPE_APITEST 0xffff +#define GLOB_TYPE_GET_NBSI_ACPI_RAW 0xfffd + + + +/* + * NV2080_CTRL_CMD_BIOS_GET_SKU_INFO + * + * This command returns information about the current board SKU. + * NV_ERR_INVALID_OWNER will be returned if the call + * isn't made with the OS as the administrator. + * + * chipSKU + * This field returns the sku for the current chip. + * chipSKUMod + * This field returns the SKU modifier. + * project + * This field returns the Project (Board) number. + * projectSKU + * This field returns the Project (Board) SKU number. + * CDP + * This field returns the Collaborative Design Project Number. + * projectSKUMod + * This field returns the Project (Board) SKU Modifier. + * businessCycle + * This field returns the business cycle the board is associated with. + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OWNER + */ +#define NV2080_CTRL_CMD_BIOS_GET_SKU_INFO (0x20800808) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID" */ + +/* maximum length of parameter strings */ + + +#define NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS { + NvU32 BoardID; + char chipSKU[4]; + char chipSKUMod[2]; + char project[5]; + char projectSKU[5]; + char CDP[6]; + char projectSKUMod[2]; + NvU32 businessCycle; +} NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_BIOS_GET_POST_TIME + + * This command is used to get the GPU POST time (in milliseconds). + * If the associated GPU is the master GPU this value will be recorded + * by the VBIOS and retrieved from the KDA buffer. If the associated + * GPU is a secondaryGPU then this value will reflect the devinit + * processing time. + * + * vbiosPostTime + * This parameter returns the vbios post time in msec. + * + * Possible return status values are + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV2080_CTRL_CMD_BIOS_GET_POST_TIME (0x20800809) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS { + NV_DECLARE_ALIGNED(NvU64 vbiosPostTime, 8); +} NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS; + + + +/* + * NV2080_CTRL_CMD_BIOS_GET_UEFI_SUPPORT + * + * This function is used to give out the UEFI version, UEFI image presence and + * Graphics Firmware Mode i.e. whether system is running in UEFI or not. + * + * version + * This parameter returns the UEFI version. + * + * flags + * This parameter indicates UEFI image presence and Graphics Firmware mode. + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE + * This field returns UEFI presence value. Legal values for this + * field include: + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_NO + * This value indicates that UEFI image is not present. + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_YES + * This value indicates that UEFI image is present. + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_PLACEHOLDER + * This value indicates that there is a dummy UEFI placeholder, + * which can later be updated with a valid UEFI image. + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_HIDDEN + * This value indicates that UEFI image is hidden. + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING + * This field indicates the UEFI running value. Legal values for + * this parameter include: + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_FALSE + * This value indicates that UEFI is not running. + * NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE + * This value indicates that UEFI is running. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_READY + * NV_ERR_INVALID_STATE + */ + +#define NV2080_CTRL_CMD_BIOS_GET_UEFI_SUPPORT (0x2080080b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS { + NvU32 version; + NvU32 flags; +} NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS; + +/* Legal values for flags parameter */ +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE 1:0 +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_NO (0x00000000) +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_YES (0x00000001) +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_PLACEHOLDER (0x00000002) +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_HIDDEN (0x00000003) +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING 2:2 +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_FALSE (0x00000000) +#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE (0x00000001) + + + +/* _ctrl2080bios_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobj.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobj.h new file mode 100644 index 0000000..6f69c5c --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobj.h @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080boardobj.finn +// + + + +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h" + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h new file mode 100644 index 0000000..caafd74 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080boardobjgrpclasses.finn +// + + + +#include "nvtypes.h" + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h new file mode 100644 index 0000000..eb8d979 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h @@ -0,0 +1,1588 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080bus.finn +// + +#include "nvcfg_sdk.h" +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX bus control commands and parameters */ + +/** + * NV2080_CTRL_CMD_BUS_GET_PCI_INFO + * + * This command returns PCI bus identifier information for the specified GPU. + * + * pciDeviceId + * This parameter specifies the internal PCI device and vendor + * identifiers for the GPU. + * pciSubSystemId + * This parameter specifies the internal PCI subsystem identifier for + * the GPU. + * pciRevisionId + * This parameter specifies the internal PCI device-specific revision + * identifier for the GPU. + * pciExtDeviceId + * This parameter specifies the external PCI device identifier for + * the GPU. It contains only the 16-bit device identifier. This + * value is identical to the device identifier portion of + * pciDeviceId since non-transparent bridges are no longer supported. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_BUS_GET_PCI_INFO (0x20801801) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS { + NvU32 pciDeviceId; + NvU32 pciSubSystemId; + NvU32 pciRevisionId; + NvU32 pciExtDeviceId; +} NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS; + +/* + * NV2080_CTRL_BUS_INFO + * + * This structure represents a single 32bit bus engine value. Clients + * request a particular bus engine value by specifying a unique bus + * information index. + * + * Legal bus information index values are: + * NV2080_CTRL_BUS_INFO_INDEX_TYPE + * This index is used to request the bus type of the GPU. + * Legal return values for this index are: + * NV2080_CTRL_BUS_INFO_TYPE_PCI + * NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS + * NV2080_CTRL_BUS_INFO_TYPE_FPCI + * NV2080_CTRL_BUS_INFO_INDEX_INTLINE + * This index is used to request the interrupt line (or irq) assignment + * for the GPU. The return value is system-dependent. + * NV2080_CTRL_BUS_INFO_INDEX_CAPS + * This index is used to request the bus engine capabilities for the GPU. + * The return value is specified as a mask of capabilities. + * Legal return values for this index are: + * NV2080_CTRL_BUS_INFO_CAPS_NEED_IO_FLUSH + * NV2080_CTRL_BUS_INFO_CAPS_CHIP_INTEGRATED + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CAPS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CAPS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CAPS + * These indices are used to request PCI Express link-specific + * capabilities values. A value of zero is returned for non-PCIE GPUs. + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CTRL_STATUS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CTRL_STATUS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CTRL_STATUS + * These indices are used to request PCI Express link-specific + * control status values. A value of zero is returned for non-PCIE GPUs. + * NV2080_CTRL_BUS_INFO_INDEX_COHERENT_DMA_FLAGS + * This index is used to request coherent dma transfer flags. + * Valid coherent dma transfer flags include: + * NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA + * NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART + * NV2080_CTRL_BUS_INFO_INDEX_NONCOHERENT_DMA_FLAGS + * This index is used to request noncoherent dma transfer flags. + * Valid noncoherent dma transfer flags include: + * NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA + * NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART + * NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE + * NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE + * This index is used to request the size of the GPU GART in MBytes. + * NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_FLAGS + * This index is used to request GPU GART flags. + * Valid gart flags include: + * NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH + * This flag indicates that GPU GART clients need to do an explicit + * flush via an appropriate SetContextDma method. + * NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED + * This flag indicates that the GART address range includes both + * system and video memory. + * NV2080_CTRL_BUS_INFO_INDEX_BUS_NUMBER + * This index is used to request the PCI-based bus number of the GPU. + * Support for this index is platform-dependent. + * NV2080_CTRL_BUS_INFO_INDEX_DEVICE_NUMBER + * This index is used to request the PCI-based device number of the GPU. + * Support for this index is platform-dependent. + * NV2080_CTRL_BUS_INFO_INDEX_DOMAIN_NUMBER + * This index is used to request the PCI-based domain number of the GPU. + * Support for this index is platform-dependent. + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_ERRORS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_ERRORS + * These indices are used to request PCI Express error status. + * The current status is cleared as part of these requests. + * Valid PCI Express error status values include: + * NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR + * NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_NON_FATAL_ERROR + * NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_FATAL_ERROR + * NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_UNSUPP_REQUEST + * NV2080_CTRL_BUS_INFO_INDEX_INTERFACE_TYPE + * This index is used to request the bus interface type of the GPU. + * Legal return values for this index are: + * NV2080_CTRL_BUS_INFO_TYPE_PCI + * NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS + * NV2080_CTRL_BUS_INFO_TYPE_FPCI + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_INFO // DEPRECATED + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN_INFO // REPLACES "GEN2" variant + * This index is used to retrieve PCI Express Gen configuration support + * This index is used to retrieve PCI Express Gen2 configuration support + * for the GPU. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN1 + * The GPU is PCI Express Gen1 capable. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN2 + * The GPU is PCI Express Gen2 capable. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN3 + * The GPU is PCI Express Gen3 capable. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN4 + * The GPU is PCI Express Gen4 capable. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN5 + * The GPU is PCI Express Gen5 capable. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN1 + * The GPU is configured in PCI Express Gen1 mode. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN2 + * The GPU is configured in PCI Express Gen2 mode. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN3 + * The GPU is configured in PCI Express Gen3 mode. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN4 + * The GPU is configured in PCI Express Gen4 mode. + * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN5 + * The GPU is configured in PCI Express Gen5 mode. + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_AER + * This index retrieves PCI Express Advanced Error Reporting (AER) errors + * for the GPU. + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CAPS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CAPS + * This index retrieves the PCI Express link capabilities for the + * board. For example, a Quadro FX4700X2 has two GPUs and PCIe + * switch. With this board, this index returns the link + * capabilities of the PCIe switch. In a single GPU board, this + * index returns the link capabilities of the GPU. A value of + * zero is returned for non-PCIE GPUs. + * UPSTREAM_LINK_CAPS is kept for backwards compatibility. + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CTRL_STATUS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CTRL_STATUS + * This index retrieves the PCI Express link status for the board. + * For example, a Quadro FX4700X2 has two GPUs and PCIe switch. + * With this board, this index returns the link capabilities of + * the PCIe switch. In a single GPU board, this index returns the + * link status of the GPU. A value of zero is returned for + * non-PCIE GPUs. + * UPSTREAM_LINK_CTRL_STATUS is kept for backwards compatibility. + * NV2080_CTRL_BUS_INFO_INDEX_ASLM_STATUS + * This index is used to request the PCI Express ASLM settings. + * This index is only valid when NV2080_CTRL_BUS_INFO_TYPE indicates PCIE. + * A value of zero is returned for non-PCI Express bus type. + * _ASLM_STATUS_PCIE is always _PRESENT if PCI Express bus type. + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_WIDTH_SWITCH_ERROR_COUNT + * This index is used to get the ASLM switching error count. + * A value of zero will be returned if no errors occurs while + * ASLM switching + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_SWITCH_ERROR_COUNT + * This index is used to get the Gen1<-->Gen2 switching error count + * A value of zero will be returned in case speed change from Gen1 to + * Gen2 is clean or if chipset is not gen2 capable or if gen1<-->gen2 + * switching is disabled. + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_CYA_ASPM + * This index is used to get the ASPM CYA L0s\L1 enable\disable status. + * Legal return value is specified as a mask of valid and data field + * possible return values are: + * NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_NO + * NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_YES + * NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_DISABLED + * NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S + * NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L1 + * NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S_L1 + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS + * These indices are used to request detailed PCI Express error counters. + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS_CLEAR + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS_CLEAR + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED_CLEAR + * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS_CLEAR + * These indices are used to clear detailed PCI Express error counters. + * NV2080_CTRL_BUS_INFO_INDEX_GPU_INTERFACE_TYPE + * This index is used to request the internal interface type of the GPU. + * Legal return values for this index are: + * NV2080_CTRL_BUS_INFO_TYPE_PCI + * NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS + * NV2080_CTRL_BUS_INFO_TYPE_FPCI + * NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE + * This index queries the type of sysmem connection to CPU + * NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE + * NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK + * NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C + * + */ + +typedef struct NV2080_CTRL_BUS_INFO { + NvU32 index; + NvU32 data; +} NV2080_CTRL_BUS_INFO; + +/* valid bus info index values */ + +/** + * This index is used to request the bus type of the GPU. + * Legal return values for this index are: + * NV2080_CTRL_BUS_INFO_TYPE_PCI + * NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS + * NV2080_CTRL_BUS_INFO_TYPE_FPCI + */ +#define NV2080_CTRL_BUS_INFO_INDEX_TYPE (0x00000000) +#define NV2080_CTRL_BUS_INFO_INDEX_INTLINE (0x00000001) +#define NV2080_CTRL_BUS_INFO_INDEX_CAPS (0x00000002) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CAPS (0x00000003) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CAPS (0x00000004) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CAPS (0x00000005) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CAPS (0x00000006) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CTRL_STATUS (0x00000007) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CTRL_STATUS (0x00000008) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CTRL_STATUS (0x00000009) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CTRL_STATUS (0x0000000A) +/** + * This index is used to request coherent dma transfer flags. + * Valid coherent dma transfer flags include: + * NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA + * NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART + */ +#define NV2080_CTRL_BUS_INFO_INDEX_COHERENT_DMA_FLAGS (0x0000000B) +/** + * This index is used to request noncoherent dma transfer flags. + * Valid noncoherent dma transfer flags include: + * NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA + * NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART + * NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE + */ +#define NV2080_CTRL_BUS_INFO_INDEX_NONCOHERENT_DMA_FLAGS (0x0000000C) +/** + * This index is used to request the size of the GPU GART in MBytes. + */ +#define NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE (0x0000000D) +/** + * This index is used to request GPU GART flags. + * Valid gart flags include: + * NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH + * This flag indicates that GPU GART clients need to do an explicit + * flush via an appropriate SetContextDma method. + * NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED + * This flag indicates that the GART address range includes both + * system and video memory. + */ +#define NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_FLAGS (0x0000000E) +#define NV2080_CTRL_BUS_INFO_INDEX_BUS_NUMBER (0x0000000F) +#define NV2080_CTRL_BUS_INFO_INDEX_DEVICE_NUMBER (0x00000010) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_ERRORS (0x00000011) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_ERRORS (0x00000012) +#define NV2080_CTRL_BUS_INFO_INDEX_INTERFACE_TYPE (0x00000013) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_INFO (0x00000014) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_AER (0x00000015) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CAPS (0x00000016) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CTRL_STATUS (0x00000017) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_ASLM_STATUS (0x00000018) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_WIDTH_SWITCH_ERROR_COUNT (0x00000019) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_SPEED_SWITCH_ERROR_COUNT (0x0000001A) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_CYA_ASPM (0x0000001B) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS (0x0000001C) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS (0x0000001D) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED (0x0000001E) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS (0x0000001F) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS_CLEAR (0x00000020) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS_CLEAR (0x00000021) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED_CLEAR (0x00000022) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS_CLEAR (0x00000023) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS (0x00000024) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS (0x00000025) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS (0x00000026) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS (0x00000027) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS_CLEAR (0x00000028) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS_CLEAR (0x00000029) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS_CLEAR (0x0000002A) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS_CLEAR (0x0000002B) +#define NV2080_CTRL_BUS_INFO_INDEX_DOMAIN_NUMBER (0x0000002C) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN_INFO (0x0000002D) +#define NV2080_CTRL_BUS_INFO_INDEX_GPU_INTERFACE_TYPE (0x0000002E) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_GEN_INFO (0x0000002F) +#define NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_GEN_INFO (0x00000030) +#define NV2080_CTRL_BUS_INFO_INDEX_MSI_INFO (0x00000031) +/** + * This index is used to request the top 32 bits of the size of the GPU + * GART in MBytes. + */ +#define NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE_HI (0x00000032) +#define NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE (0x00000033) +#define NV2080_CTRL_BUS_INFO_INDEX_MAX NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE +#define NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE (0x00000034) + +/* valid bus info type return values */ +#define NV2080_CTRL_BUS_INFO_TYPE_PCI (0x00000001) +#define NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS (0x00000003) +#define NV2080_CTRL_BUS_INFO_TYPE_FPCI (0x00000004) +#define NV2080_CTRL_BUS_INFO_TYPE_AXI (0x00000008) + +/* valid bus capability flags */ +#define NV2080_CTRL_BUS_INFO_CAPS_NEED_IO_FLUSH (0x00000001) +#define NV2080_CTRL_BUS_INFO_CAPS_CHIP_INTEGRATED (0x00000002) + +/* + * Format of PCIE link caps return values + * Note that Link Capabilities register format is followed only for bits 11:0 + */ +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED 3:0 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_2500MBPS (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_5000MBPS (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_8000MBPS (0x00000003) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_16000MBPS (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_32000MBPS (0x00000005) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_64000MBPS (0x00000006) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_WIDTH 9:4 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM 11:10 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_NONE (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S_L1 (0x00000003) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN 15:12 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN1 (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN2 (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN3 (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN4 (0x00000003) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN5 (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN6 (0x00000005) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL 19:16 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN1 (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN2 (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN3 (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN4 (0x00000003) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN5 (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN6 (0x00000005) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN 23:20 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN1 (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN2 (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN3 (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN4 (0x00000003) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN5 (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN6 (0x00000005) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES 24:24 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_ENABLED (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_DISABLED (0x00000001) + +/* format of PCIE control status return values */ +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM 1:0 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_DISABLED (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L1 (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S_L1 (0x00000003) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED 19:16 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_2500MBPS (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_5000MBPS (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_8000MBPS (0x00000003) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_16000MBPS (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_32000MBPS (0x00000005) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_64000MBPS (0x00000006) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH 25:20 +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_UNDEFINED (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X1 (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X2 (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X4 (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X8 (0x00000008) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X12 (0x0000000C) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X16 (0x00000010) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X32 (0x00000020) + +/* coherent dma transfer flags */ +#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA 0:0 +#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_FALSE (0x00000000) +#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_TRUE (0x00000001) +#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART 2:2 +#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_FALSE (0x00000000) +#define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_TRUE (0x00000001) + +/* noncoherent dma transfer flags */ +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA 0:0 +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_FALSE (0x00000000) +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_TRUE (0x00000001) +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART 2:2 +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_FALSE (0x00000000) +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_TRUE (0x00000001) +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE 3:3 +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_FALSE (0x00000000) +#define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_TRUE (0x00000001) + +/* GPU GART flags */ +#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH 0:0 +#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_FALSE (0x00000000) +#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_TRUE (0x00000001) +#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED 1:1 +#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_FALSE (0x00000000) +#define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_TRUE (0x00000001) + +/* format of PCIE errors return values */ +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_NON_FATAL_ERROR (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_FATAL_ERROR (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_UNSUPP_REQUEST (0x00000008) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_ENTERED_RECOVERY (0x00000010) + +/* PCIE Gen2 capability and current level */ +#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP 0:0 +#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_FALSE (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_TRUE (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL 1:1 +#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN1 (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN2 (0x00000001) + +/* format of PCIE AER return values */ +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_TRAINING_ERR (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_DLINK_PROTO_ERR (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_POISONED_TLP (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_FC_PROTO_ERR (0x00000008) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_TIMEOUT (0x00000010) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_ABORT (0x00000020) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNEXP_CPL (0x00000040) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_RCVR_OVERFLOW (0x00000080) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_MALFORMED_TLP (0x00000100) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_ECRC_ERROR (0x00000200) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNSUPPORTED_REQ (0x00000400) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RCV_ERR (0x00010000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_TLP (0x00020000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_DLLP (0x00040000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_ROLLOVER (0x00080000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_TIMEOUT (0x00100000) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_ADVISORY_NONFATAL (0x00200000) + +/* format of PCIE ASLM status return value */ +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE 0:0 +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_ERROR (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_PRESENT (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED 1:1 +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE 2:2 +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED 3:3 +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04 4:4 +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_MISSING (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_PRESENT (0x00000001) + +/* format of GPU CYA CAPS return value */ +#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID 0:0 +#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM 2:1 +#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_DISABLED (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L1 (0x00000002) +#define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S_L1 (0x00000003) + +/* format of MSI INFO return value */ +#define NV2080_CTRL_BUS_INFO_MSI_STATUS 0:0 +#define NV2080_CTRL_BUS_INFO_MSI_STATUS_DISABLED (0x00000000) +#define NV2080_CTRL_BUS_INFO_MSI_STATUS_ENABLED (0x00000001) + +/*format of L1PM Substates capabilities information */ +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED 0:0 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED 1:1 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED 2:2 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED 3:3 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED 4:4 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_RESERVED 7:5 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PORT_RESTORE_TIME 15:8 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_T_POWER_ON_SCALE 17:16 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_T_POWER_ON_VALUE 23:19 + +/*format of L1 PM Substates Control 1 Register */ +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED 0:0 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED 1:1 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED 2:2 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED 3:3 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_YES (0x00000001) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_NO (0x00000000) +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_COMMON_MODE_RESTORE_TIME 15:8 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_LTR_L1_2_THRESHOLD_VALUE 25:16 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_LTR_L1_2_THRESHOLD_SCALE 31:29 + +/*format of L1 PM Substates Control 2 Register */ +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL2_T_POWER_ON_SCALE 1:0 +#define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL2_T_POWER_ON_VALUE 7:3 + +/* valid sysmem connection type values */ +#define NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE (0x00000000) +#define NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK (0x00000001) +#define NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C (0x00000002) + +/** + * NV2080_CTRL_CMD_BUS_GET_INFO + * + * This command returns bus engine information for the associated GPU. + * Requests to retrieve bus information use a list of one or more + * NV2080_CTRL_BUS_INFO structures. + * + * busInfoListSize + * This field specifies the number of entries on the caller's + * busInfoList. + * busInfoList + * This field specifies a pointer in the caller's address space + * to the buffer into which the bus information is to be returned. + * This buffer must be at least as big as busInfoListSize multiplied + * by the size of the NV2080_CTRL_BUS_INFO structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV2080_CTRL_CMD_BUS_GET_INFO (0x20801802) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_GET_INFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_BUS_GET_INFO_PARAMS { + NvU32 busInfoListSize; + NV_DECLARE_ALIGNED(NvP64 busInfoList, 8); +} NV2080_CTRL_BUS_GET_INFO_PARAMS; + +#define NV2080_CTRL_CMD_BUS_GET_INFO_V2 (0x20801823) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_MESSAGE_ID (0x23U) + +typedef struct NV2080_CTRL_BUS_GET_INFO_V2_PARAMS { + NvU32 busInfoListSize; + NV2080_CTRL_BUS_INFO busInfoList[NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE]; +} NV2080_CTRL_BUS_GET_INFO_V2_PARAMS; + +/* + * NV2080_CTRL_BUS_PCI_BAR_INFO + * + * This structure describes PCI bus BAR information. + * + * flags + * This field contains any flags for the associated BAR. + * barSize + * This field contains the size in megabytes of the associated BAR. + * DEPRECATED, please use barSizeBytes. + * barSizeBytes + * This field contains the size in bytes of the associated BAR. + * barOffset + * This field contains the PCI bus offset in bytes of the associated BAR. + */ +typedef struct NV2080_CTRL_BUS_PCI_BAR_INFO { + NvU32 flags; + NvU32 barSize; + NV_DECLARE_ALIGNED(NvU64 barSizeBytes, 8); + NV_DECLARE_ALIGNED(NvU64 barOffset, 8); +} NV2080_CTRL_BUS_PCI_BAR_INFO; + +/* + * NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO + * + * This command returns PCI bus BAR information. + * + * barCount + * This field returns the number of BARs for the associated subdevice. + * Legal values for this parameter will be between one to + * NV2080_CTRL_BUS_MAX_BARS. + * barInfo + * This field returns per-BAR information in the form of an array of + * NV2080_CTRL_BUS_PCI_BAR_INFO structures. Information for as many as + * NV2080_CTRL_BUS_MAX_PCI_BARS will be returned. Any unused entries will + * be initialized to zero. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO (0x20801803) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS_MESSAGE_ID" */ + +/* maximum number of BARs per subdevice */ +#define NV2080_CTRL_BUS_MAX_PCI_BARS (8) + +#define NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS { + NvU32 pciBarCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_BUS_PCI_BAR_INFO pciBarInfo[NV2080_CTRL_BUS_MAX_PCI_BARS], 8); +} NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_SET_PCIE_LINK_WIDTH + * + * This command sets PCI-E link width to the specified new value. + * + * pcieLinkWidth + * This field specifies the new PCI-E link width. + * + * failingReason + * This field specifies the reason why the change of link width fails. + * It is valid only when this routine returns NV_ERR_GENERIC. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_GENERIC + */ +#define NV2080_CTRL_CMD_BUS_SET_PCIE_LINK_WIDTH (0x20801804) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS { + NvU32 pcieLinkWidth; + NvU32 failingReason; +} NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS; + +#define NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PSTATE (0x00000001) +#define NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PCIE_CFG_ACCESS (0x00000002) +#define NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_TRAINING (0x00000004) + +/* + * NV2080_CTRL_CMD_BUS_SET_PCIE_SPEED + * + * This command Initiates a change in PCIE Bus Speed + * + * busSpeed + * This field is the target speed to train to. + * Legal values for this parameter are: + * NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS + * NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS + * NV2080_CTRL_BUS_SET_PCIE_SPEED_8000MBPS + * NV2080_CTRL_BUS_SET_PCIE_SPEED_16000MBPS + * NV2080_CTRL_BUS_SET_PCIE_SPEED_32000MBPS + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_BUS_SET_PCIE_SPEED (0x20801805) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS { + NvU32 busSpeed; +} NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS; + +#define NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS (0x00000001) +#define NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS (0x00000002) +#define NV2080_CTRL_BUS_SET_PCIE_SPEED_8000MBPS (0x00000003) +#define NV2080_CTRL_BUS_SET_PCIE_SPEED_16000MBPS (0x00000004) +#define NV2080_CTRL_BUS_SET_PCIE_SPEED_32000MBPS (0x00000005) +#define NV2080_CTRL_BUS_SET_PCIE_SPEED_64000MBPS (0x00000006) + +/* + * NV2080_CTRL_CMD_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED + * + * This command Initiates a change in PCIE Bus Speed for a HWBC device's upstream + * link. + * + * busSpeed + * This field specifies the target speed to which to train. + * Legal values for this parameter are: + * NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS + * NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS + * primaryBus + * This field is the PCI Express Primary Bus number that uniquely identifies + * a HWBC device's upstream port, i.e. the BR04 Upstream Port. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED (0x20801806) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS { + NvU32 busSpeed; + NvU8 primaryBus; +} NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS; + +#define NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_2500MBPS (0x00000001) +#define NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_5000MBPS (0x00000002) + +/* + * NV2080_CTRL_CMD_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED + * + * This command gets the current PCIE Bus Speed for a HWBC device's upstream + * link. + * + * primaryBus + * This field is the PCI Express Primary Bus number that uniquely identifies + * a HWBC device's upstream port, i.e. the BR04 Upstream Port. + * busSpeed + * This field specifies a pointer in the caller's address space + * to the NvU32 variable into which the bus speed is to be returned. + * On success, this parameter will contain one of the following values: + * NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS + * NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED (0x20801807) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS { + NvU32 busSpeed; + NvU8 primaryBus; +} NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS; + +#define NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_2500MBPS (0x00000001) +#define NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_5000MBPS (0x00000002) + +/* + * NV2080_CTRL_CMD_BUS_MAP_BAR2 + * + * This command sets up BAR2 page tables for passed-in memory handle. + * This command MUST be executed before NV2080_CTRL_CMD_BUS_UNMAP_BAR2 + * or NV2080_CTRL_CMD_BUS_VERIFY_BAR2. Not supported on SLI. + * + * hMemory + * This field is a handle to physical memory. + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV2080_CTRL_CMD_BUS_MAP_BAR2 (0x20801809) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_MAP_BAR2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_MAP_BAR2_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_BUS_MAP_BAR2_PARAMS { + NvHandle hMemory; +} NV2080_CTRL_BUS_MAP_BAR2_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_UNMAP_BAR2 + * + * This command unmaps any pending BAR2 page tables created with + * NV2080_CTRL_CMD_BUS_MAP_BAR2 command. The handle passed in must + * match the handle used to map the page tables. Not supported on SLI. + * + * hMemory + * This field is a handle to physical memory. + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV2080_CTRL_CMD_BUS_UNMAP_BAR2 (0x2080180a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS { + NvHandle hMemory; +} NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_VERIFY_BAR2 + * + * This command tests BAR2 against BAR0 if there are BAR2 page tables + * set up with NV2080_CTRL_CMD_BUS_MAP_BAR2 command. The handle passed + * in must match the handle used to map the page tables. Not supported on SLI. + * + * hMemory + * This field is a handle to physical memory. + * offset + * Base offset of the surface where the test will make its first dword write. + * size + * Test will write '(size/4)*4' bytes starting at surface offset `offset'. + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV2080_CTRL_CMD_BUS_VERIFY_BAR2 (0x2080180b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS { + NvHandle hMemory; + NvU32 offset; + NvU32 size; +} NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_HWBC_GET_UPSTREAM_BAR0 + * + * This command gets the BAR0 for a HWBC device's upstream port. + * + * primaryBus + * This field is the PCI Express Primary Bus number that uniquely identifies + * a HWBC device's upstream port, i.e. the BR04 Upstream Port. + * physBAR0 + * This field returns the BAR0 physical address of the HWBC device's + * upstream port. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_BUS_HWBC_GET_UPSTREAM_BAR0 (0x2080180e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_HWBC_GET_UPSTREAM_BAR0_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_HWBC_GET_UPSTREAM_BAR0_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV2080_CTRL_BUS_HWBC_GET_UPSTREAM_BAR0_PARAMS { + NV_DECLARE_ALIGNED(NvU64 physBAR0, 8); + NvU8 primaryBus; +} NV2080_CTRL_BUS_HWBC_GET_UPSTREAM_BAR0_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_SERVICE_GPU_MULTIFUNC_STATE + * This command would reports the current Audio device power state or Sets new power state. + * + * command + * This parametrer specifies the target GPU multifunction state. + * NV2080_CTRL_BUS_ENABLE_GPU_MULTIFUNC_STATE Enables the multi function state + * NV2080_CTRL_BUS_DISABLE_GPU_MULTIFUNC_STATE Disables the multi function state. + * NV2080_CTRL_BUS_GET_GPU_MULTIFUNC_STATE Get the Current device power state. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + */ + +#define NV2080_CTRL_CMD_BUS_SERVICE_GPU_MULTIFUNC_STATE (0x20801812) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS { + NvU8 command; + NvU32 deviceState; +} NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS; + +#define NV2080_CTRL_BUS_ENABLE_GPU_MULTIFUNC_STATE (0x00000000) +#define NV2080_CTRL_BUS_DISABLE_GPU_MULTIFUNC_STATE (0x00000001) +#define NV2080_CTRL_BUS_GET_GPU_MULTIFUNC_STATE (0x00000002) + +/* + * NV2080_CTRL_CMD_BUS_GET_PEX_COUNTERS + * This command gets the counts for different counter types. + * + * pexCounterMask + * This parameter specifies the input mask for desired counter types. + * + * pexTotalCorrectableErrors + * This parameter gives the total correctable errors which includes + * NV_XVE_ERROR_COUNTER1 plus LCRC Errors, 8B10B Errors, NAKS and Failed L0s + * + * pexCorrectableErrors + * This parameter only includes NV_XVE_ERROR_COUNTER1 value. + * + * pexTotalNonFatalErrors + * This parameter returns total Non-Fatal Errors which may or may not + * include Correctable Errors. + * + * pexTotalFatalErrors + * This parameter returns Total Fatal Errors + * + * pexTotalUnsupportedReqs + * This parameter returns Total Unsupported Requests + * + * pexErrors + * This array contains the error counts for each error type as requested from + * the pexCounterMask. The array indexes correspond to the mask bits one-to-one. + */ + +#define NV2080_CTRL_CMD_BUS_GET_PEX_COUNTERS (0x20801813) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PEX_MAX_COUNTER_TYPES 31 +#define NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS { + NvU32 pexCounterMask; + NvU32 pexTotalCorrectableErrors; + NvU16 pexCorrectableErrors; + NvU8 pexTotalNonFatalErrors; + NvU8 pexTotalFatalErrors; + NvU8 pexTotalUnsupportedReqs; + NvU16 pexCounters[NV2080_CTRL_PEX_MAX_COUNTER_TYPES]; +} NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS; + +/* + * Note that MAX_COUNTER_TYPES will need to be updated each time + * a new counter type gets added to the list below. The value + * depends on the bits set for the last valid define. Look + * at pexCounters[] comments above for details. + * + */ +#define NV2080_CTRL_BUS_PEX_COUNTER_TYPE 0x00000000 +#define NV2080_CTRL_BUS_PEX_COUNTER_RECEIVER_ERRORS 0x00000001 +#define NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_COUNT 0x00000002 +#define NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_ROLLOVER_COUNT 0x00000004 +#define NV2080_CTRL_BUS_PEX_COUNTER_BAD_DLLP_COUNT 0x00000008 +#define NV2080_CTRL_BUS_PEX_COUNTER_BAD_TLP_COUNT 0x00000010 +#define NV2080_CTRL_BUS_PEX_COUNTER_8B10B_ERRORS_COUNT 0x00000020 +#define NV2080_CTRL_BUS_PEX_COUNTER_SYNC_HEADER_ERRORS_COUNT 0x00000040 +#define NV2080_CTRL_BUS_PEX_COUNTER_LCRC_ERRORS_COUNT 0x00000080 +#define NV2080_CTRL_BUS_PEX_COUNTER_FAILED_L0S_EXITS_COUNT 0x00000100 +#define NV2080_CTRL_BUS_PEX_COUNTER_NAKS_SENT_COUNT 0x00000200 +#define NV2080_CTRL_BUS_PEX_COUNTER_NAKS_RCVD_COUNT 0x00000400 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_ERRORS 0x00000800 +#define NV2080_CTRL_BUS_PEX_COUNTER_L1_TO_RECOVERY_COUNT 0x00001000 +#define NV2080_CTRL_BUS_PEX_COUNTER_L0_TO_RECOVERY_COUNT 0x00002000 +#define NV2080_CTRL_BUS_PEX_COUNTER_RECOVERY_COUNT 0x00004000 +#define NV2080_CTRL_BUS_PEX_COUNTER_CHIPSET_XMIT_L0S_ENTRY_COUNT 0x00008000 +#define NV2080_CTRL_BUS_PEX_COUNTER_GPU_XMIT_L0S_ENTRY_COUNT 0x00010000 +#define NV2080_CTRL_BUS_PEX_COUNTER_L1_ENTRY_COUNT 0x00020000 +#define NV2080_CTRL_BUS_PEX_COUNTER_L1P_ENTRY_COUNT 0x00040000 +#define NV2080_CTRL_BUS_PEX_COUNTER_DEEP_L1_ENTRY_COUNT 0x00080000 +#define NV2080_CTRL_BUS_PEX_COUNTER_ASLM_COUNT 0x00100000 +#define NV2080_CTRL_BUS_PEX_COUNTER_TOTAL_CORR_ERROR_COUNT 0x00200000 +#define NV2080_CTRL_BUS_PEX_COUNTER_CORR_ERROR_COUNT 0x00400000 +#define NV2080_CTRL_BUS_PEX_COUNTER_NON_FATAL_ERROR_COUNT 0x00800000 +#define NV2080_CTRL_BUS_PEX_COUNTER_FATAL_ERROR_COUNT 0x01000000 +#define NV2080_CTRL_BUS_PEX_COUNTER_UNSUPP_REQ_COUNT 0x02000000 +#define NV2080_CTRL_BUS_PEX_COUNTER_L1_1_ENTRY_COUNT 0x04000000 +#define NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ENTRY_COUNT 0x08000000 +#define NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ABORT_COUNT 0x10000000 +#define NV2080_CTRL_BUS_PEX_COUNTER_L1SS_TO_DEEP_L1_TIMEOUT_COUNT 0x20000000 +#define NV2080_CTRL_BUS_PEX_COUNTER_L1_SHORT_DURATION_COUNT 0x40000000 + +/* + * NV2080_CTRL_CMD_BUS_CLEAR_PEX_COUNTER_COUNTERS + * This command gets the counts for different counter types. + * + * pexCounterMask + * This parameter specifies the input mask for desired counters to be + * cleared. Note that all counters cannot be cleared. + */ + +#define NV2080_CTRL_CMD_BUS_CLEAR_PEX_COUNTERS (0x20801814) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS { + NvU32 pexCounterMask; +} NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_FREEZE_PEX_COUNTERS + * This command gets the counts for different counter types. + * + * pexCounterMask + * This parameter specifies the input mask for desired counters to be + * freezed. Note that all counters cannot be frozen. + * + * bFreezeRmCounter + * This parameter decides whether API will freeze it or unfreeze it. + * NV_TRUE for freeze and NV_FALSE for unfreeze. + */ + +#define NV2080_CTRL_CMD_BUS_FREEZE_PEX_COUNTERS (0x20801815) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS { + NvU32 pexCounterMask; + NvBool bFreezeRmCounter; +} NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS + * This command gets the per Lane Counters and the type of errors. + * + * pexLaneErrorStatus + * This mask specifies the type of error detected on any of the Lanes. + * + * pexLaneCounter + * This array gives the counters per Lane. Each index corresponds to Lane + * index + 1 + */ + +#define NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS (0x20801816) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PEX_MAX_LANES 16 +#define NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS { + NvU16 pexLaneErrorStatus; + NvU8 pexLaneCounter[NV2080_CTRL_PEX_MAX_LANES]; +} NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS; + +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_TYPE 0x00000000 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_CODING_ERR 0x00000001 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_ORDER_ERR 0x00000002 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_OS_DATA_SEQ_ERR 0x00000004 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_TSX_DATA_SEQ_ERR 0x00000008 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_SKPOS_LFSR_ERR 0x00000010 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_RX_CLK_FIFO_OVERFLOW 0x00000020 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_ELASTIC_FIFO_OVERFLOW 0x00000040 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LINK_NUM_ERR 0x00000080 +#define NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LANE_NUM_ERR 0x00000100 + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY (0x20801817) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID (0x17U) + +typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS { + NvBool bPexLtrRegkeyOverride; + NvBool bPexRootPortLtrSupported; + NvBool bPexGpuLtrSupported; + NvU16 pexLtrSnoopLatencyValue; + NvU8 pexLtrSnoopLatencyScale; + NvU16 pexLtrNoSnoopLatencyValue; + NvU8 pexLtrNoSnoopLatencyScale; +} NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS; + +#define NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY (0x20801818) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS { + NvU16 pexLtrSnoopLatencyValue; + NvU8 pexLtrSnoopLatencyScale; + NvU16 pexLtrNoSnoopLatencyValue; + NvU8 pexLtrNoSnoopLatencyScale; +} NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_GET_PEX_UTIL_COUNTERS + * This command gets the counts for different counter types. + * + * pexCounterMask + * This parameter specifies the input mask for desired counter types. + * + */ +#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_BYTES 0x00000001 +#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_BYTES 0x00000002 +#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0 0x00000004 +#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0 0x00000008 +#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0S 0x00000010 +#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0S 0x00000020 +#define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_NON_L0_L0S 0x00000040 +#define NV2080_CTRL_PEX_UTIL_MAX_COUNTER_TYPES 7 + +#define NV2080_CTRL_CMD_BUS_GET_PEX_UTIL_COUNTERS (0x20801819) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS { + NvU32 pexCounterMask; + NvU32 pexCounters[NV2080_CTRL_PEX_UTIL_MAX_COUNTER_TYPES]; +} NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_CLEAR_PEX_UTIL_COUNTER_COUNTERS + * This command gets the counts for different counter types. + * + * pexCounterMask + * This parameter specifies the input mask for desired counters to be + * cleared. Note that all counters cannot be cleared. + * + * NOTE: EX_UTIL_COUNTER_UPSTREAM & NV2080_CTRL_BUS_PEX_UTIL_COUNTER_DOWNSTREAM + * belongs to PMU. The ctrl function will not reset nor disable/enable them. + */ +#define NV2080_CTRL_CMD_BUS_CLEAR_PEX_UTIL_COUNTERS (0x20801820) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS { + NvU32 pexCounterMask; +} NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS; + +#define NV2080_CTRL_CMD_BUS_GET_BFD (0x20801821) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_BFD_PARAMSARR_MESSAGE_ID" */ + +typedef struct NV2080_CTRL_BUS_GET_BFD_PARAMS { + NvBool valid; + NvU16 deviceID; + NvU16 vendorID; + NvU32 domain; + NvU16 bus; + NvU16 device; + NvU8 function; +} NV2080_CTRL_BUS_GET_BFD_PARAMS; + +#define NV2080_CTRL_BUS_GET_BFD_PARAMSARR_MESSAGE_ID (0x21U) + +typedef struct NV2080_CTRL_BUS_GET_BFD_PARAMSARR { + NV2080_CTRL_BUS_GET_BFD_PARAMS params[32]; +} NV2080_CTRL_BUS_GET_BFD_PARAMSARR; + +/* + * NV2080_CTRL_CMD_BUS_GET_ASPM_DISABLE_FLAGS + * This command gets the following mentioned PDB Properties + * + * aspmDisableFlags[] + * NvBool array stores each of the properties' state. the array size can + * be increased as per requirement. + * + * NOTE: When adding more properties, increment NV2080_CTRL_ASPM_DISABLE_FLAGS_MAX_FLAGS. + */ + +#define NV2080_CTRL_ASPM_DISABLE_FLAGS_L1_MASK_REGKEY_OVERRIDE 0x00000000 +#define NV2080_CTRL_ASPM_DISABLE_FLAGS_OS_RM_MAKES_POLICY_DECISIONS 0x00000001 +#define NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_BEHIND_BRIDGE 0x00000002 +#define NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_UNSUPPORTED 0x00000003 +#define NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED 0x00000004 +#define NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_POR_MOBILE_ONLY 0x00000005 +#define NV2080_CTRL_ASPM_DISABLE_FLAGS_CL_ASPM_L1_CHIPSET_DISABLED 0x00000006 +#define NV2080_CTRL_ASPM_DISABLE_FLAGS_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY 0x00000007 +#define NV2080_CTRL_ASPM_DISABLE_FLAGS_BIF_ENABLE_ASPM_DT_L1 0x00000008 +//append properties here + +#define NV2080_CTRL_ASPM_DISABLE_FLAGS_MAX_FLAGS 9 + +#define NV2080_CTRL_CMD_BUS_GET_ASPM_DISABLE_FLAGS (0x20801822) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS { + NvBool aspmDisableFlags[NV2080_CTRL_ASPM_DISABLE_FLAGS_MAX_FLAGS]; +} NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS; + +#define NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS (0x20801824) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS_MESSAGE_ID (0x24U) + +typedef struct NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS { + NvBool bEnable; +} NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_GET_NVLINK_PEER_ID_MASK + * + * This command returns cached(SW only) NVLINK peer id mask. Currently, this control + * call is only needed inside a SR-IOV enabled guest where page table management is + * being done by the guest. Guest needs this mask to derive the peer id corresponding + * to the peer GPU. This peer id will then be programmed inside the PTEs by guest RM. + * + * nvlinkPeerIdMask[OUT] + * - The peer id mask is returned in this array. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_BUS_GET_NVLINK_PEER_ID_MASK (0x20801825) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_MAX_NUM_GPUS 32 + +#define NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_MESSAGE_ID (0x25U) + +typedef struct NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS { + NvU32 nvlinkPeerIdMask[NV2080_CTRL_BUS_MAX_NUM_GPUS]; +} NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS + * This command takes parameters eomMode, eomNblks and eomNerrs from the client + * and then sends it out to PMU. + */ +#define NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS (0x20801826) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS_MESSAGE_ID (0x26U) + +typedef struct NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS { + NvU8 eomMode; + NvU8 eomNblks; + NvU8 eomNerrs; +} NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE + * This command takes parameters UPHY register's address and lane from the client + * and then sends it out to PMU. + */ +#define NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE (0x20801827) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS_MESSAGE_ID (0x27U) + +typedef struct NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS { + NvU32 regAddress; + NvU32 laneSelectMask; + NvU16 regValue; +} NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_GET_EOM_STATUS + * + */ +#define NV2080_CTRL_CMD_BUS_GET_EOM_STATUS (0x20801828) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_MAX_NUM_LANES 32 + +#define NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS_MESSAGE_ID (0x28U) + +typedef struct NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS { + NvU8 eomMode; + NvU8 eomNblks; + NvU8 eomNerrs; + NvU8 eomBerEyeSel; + NvU8 eomPamEyeSel; + NvU32 laneMask; + NvU16 eomStatus[NV2080_CTRL_BUS_MAX_NUM_LANES]; +} NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS + * + * This command returns the PCIe requester atomics operation capabilities + * from GPU to coherent SYSMEM. + * + * atomicsCaps[OUT] + * Mask of supported PCIe atomic operations in the form of + * NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_* + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS (0x20801829) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID (0x29U) + +typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS { + NvU32 atomicsCaps; +} NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS; + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32 0:0 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64 1:1 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32 2:2 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64 3:3 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32 4:4 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64 5:5 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_NO (0x00000000) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128 6:6 +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_YES (0x00000001) +#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_NO (0x00000000) + +/* + * NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS + * + * This command returns the supported GPU atomic operations + * that map to the capable PCIe atomic operations from GPU to + * coherent SYSMEM. + * + * atomicOp[OUT] + * Array of structure that contains the atomic operation + * supported status and its attributes. The array can be + * indexed using one of NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_* + * + * bSupported[OUT] + * Is the GPU atomic operation natively supported by the PCIe? + * + * attributes[OUT] + * Provides the attributes mask of the GPU atomic operation when supported + * in the form of + * NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_* + * + */ +#define NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS (0x2080182a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IADD 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMIN 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMAX 2 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_INC 3 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_DEC 4 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IAND 5 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IOR 6 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IXOR 7 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_EXCH 8 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_CAS 9 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FADD 10 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMIN 11 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMAX 12 + +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT 13 + +#define NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID (0x2AU) + +typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS { + struct { + NvBool bSupported; + NvU32 attributes; + } atomicOp[NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT]; +} NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS; + +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR 0:0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR 1:1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION 2:2 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32 3:3 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64 4:4 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128 5:5 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED 6:6 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_NO 0 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED 7:7 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_YES 1 +#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_NO 0 + +/* + * NV2080_CTRL_CMD_BUS_GET_C2C_INFO + * + * This command returns the C2C links information. + * + * bIsLinkUp[OUT] + * NV_TRUE if the C2C links are present and the links are up. + * The below remaining fields are valid only if return value is + * NV_OK and bIsLinkUp is NV_TRUE. + * nrLinks[OUT] + * Total number of C2C links that are up. + * linkMask[OUT] + * Bitmask of the C2C links present and up. + * perLinkBwMBps[OUT] + * Theoretical per link bandwidth in MBps. + * remoteType[OUT] + * Type of the device connected to the remote end of the C2C link. + * Valid values are : + * NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU - connected to a CPU + * NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU - connected to another GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * + * Please also review the information below for additional information on + * select fields: + * + * remoteType[OUT] + * NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU - connected to a CPU + */ + + + +#define NV2080_CTRL_CMD_BUS_GET_C2C_INFO (0x2080182b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID (0x2BU) + +typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS { + NvBool bIsLinkUp; + NvU32 nrLinks; + NvU32 linkMask; + NvU32 perLinkBwMBps; + NvU32 remoteType; +} NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS; + +#define NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU 1 +#define NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU 2 + +/* + * NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS + * + * This command disables the GPU system memory access after quiescing the GPU, + * or re-enables sysmem access. + * + * bDisable + * If NV_TRUE the GPU is quiesced and system memory access is disabled . + * If NV_FALSE the GPU system memory access is re-enabled and the GPU is resumed. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS (0x2080182c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS_MESSAGE_ID (0x2CU) + +typedef struct NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS { + NvBool bDisable; +} NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO + * + * This command returns the C2C error info for a C2C links. + * + * errCnts[OUT] + * Array of structure that contains the error counts for + * number of times one of C2C fatal error interrupt has happened. + * The array size should be NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES + * * NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE. + * + * nrCrcErrIntr[OUT] + * Number of times CRC error interrupt triggered. + * nrReplayErrIntr[OUT] + * Number of times REPLAY error interrupt triggered. + * nrReplayB2bErrIntr[OUT] + * Number of times REPLAY_B2B error interrupt triggered. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO (0x2080182d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES 2 +#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE 5 + +#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID (0x2DU) + +typedef struct NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS { + struct { + NvU32 nrCrcErrIntr; + NvU32 nrReplayErrIntr; + NvU32 nrReplayB2bErrIntr; + } errCnts[NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES * NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE]; +} NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS; + + +/* + * NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING + * + * This command sets P2P mapping. + * + * connectionType[IN] + * Connection type, one of NV2080_CTRL_CMD_BUS_SET_P2P_MAPPINGS_CONNECTION + * peerId[IN] + * peerId of remote GPU from local GPU on which call is made. + * bSpaAccessOnly[IN] + * SPA access only. SPA addressing mode is supported when we support ATS. + * bUseUuid [in] + * Option only available for Guest RPCs and is not avaliable for external clients. + * Set to NV_TRUE to use remoteGpuUuid in lieu of remoteGpuId to identify target GPU. + * remoteGpuId[IN] + * GPU ID of remote GPU. + * remoteGpuUuid [in] + * Alternative to gpuId; used to identify target GPU for which caps are being queried. + * Option only available for Guest RPCs. + * If bUseUuid == NV_TRUE, gpuUuid is used in lieu of gpuId to identify target GPU. + * If bUseUuid == NV_FALSE, gpuUuid is ignored and gpuId is used by default. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING (0x2080182e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_INVALID 0 +#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_NVLINK 1 +#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE 2 +#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE_BAR1 3 +#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_C2C 4 + +#define NV2080_SET_P2P_MAPPING_UUID_LEN 16U + +#define NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_MESSAGE_ID (0x2EU) + +typedef struct NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS { + NvU32 connectionType; + NvU32 peerId; + NvBool bSpaAccessOnly; + NvBool bUseUuid; + NvU32 remoteGpuId; + NvU8 remoteGpuUuid[NV2080_SET_P2P_MAPPING_UUID_LEN]; +} NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING + * + * This command unsets P2P mapping. + * + * connectionType[IN] + * Connection type, one of NV2080_CTRL_CMD_BUS_SET_P2P_MAPPINGS_CONNECTION + * peerId[IN] + * peerId of remote GPU from local GPU on which call is mad. + * bUseUuid [in] + * Option only available for Guest RPCs and is not avaliable for external clients. + * Set to NV_TRUE to use remoteGpuUuid in lieu of remoteGpuId to identify target GPU. + * remoteGpuId[IN] + * GPU ID of remote GPU. + * remoteGpuUuid [in] + * Alternative to gpuId; used to identify target GPU for which caps are being queried. + * Option only available for Guest RPCs. + * If bUseUuid == NV_TRUE, gpuUuid is used in lieu of gpuId to identify target GPU. + * If bUseUuid == NV_FALSE, gpuUuid is ignored and gpuId is used by default. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING (0x2080182f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_MESSAGE_ID (0x2FU) + +typedef struct NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS { + NvU32 connectionType; + NvU32 peerId; + NvBool bUseUuid; + NvU32 remoteGpuId; + NvU8 remoteGpuUuid[NV2080_SET_P2P_MAPPING_UUID_LEN]; +} NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS; + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h new file mode 100644 index 0000000..d2f5424 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h @@ -0,0 +1,329 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080ce.finn +// + + + +#include "nvcfg_sdk.h" + + +/* NV20_SUBDEVICE_XX ce control commands and parameters */ + +/* + * NV2080_CTRL_CMD_CE_GET_CAPS + * + * This command returns the set of CE capabilities for the device + * in the form of an array of unsigned bytes. + * + * ceEngineType + * This parameter specifies the copy engine type + * capsTblSize + * This parameter specifies the size in bytes of the caps table per CE. + * This value should be set to NV2080_CTRL_CE_CAPS_TBL_SIZE. + * capsTbl + * This parameter specifies a pointer to the client's caps table buffer + * into which the CE caps bits will be transferred by the RM. + * The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_CE_GET_CAPS (0x20802a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CAPS_PARAMS_MESSAGE_ID" */ + +/* + * Size in bytes of CE caps table. This value should be one greater + * than the largest byte_index value below. + */ +#define NV2080_CTRL_CE_CAPS_TBL_SIZE 2 + +#define NV2080_CTRL_CE_GET_CAPS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_CE_GET_CAPS_PARAMS { + NvU32 ceEngineType; + NvU32 capsTblSize; + NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); +} NV2080_CTRL_CE_GET_CAPS_PARAMS; + +#define NV2080_CTRL_CMD_CE_GET_CAPS_V2 (0x20802a03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS { + NvU32 ceEngineType; + NvU8 capsTbl[NV2080_CTRL_CE_CAPS_TBL_SIZE]; +} NV2080_CTRL_CE_GET_CAPS_V2_PARAMS; + +/* extract cap bit setting from tbl */ +#define NV2080_CTRL_CE_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* caps format is byte_index:bit_mask */ +#define NV2080_CTRL_CE_CAPS_CE_GRCE 0:0x01 +#define NV2080_CTRL_CE_CAPS_CE_SHARED 0:0x02 +#define NV2080_CTRL_CE_CAPS_CE_SYSMEM_READ 0:0x04 +#define NV2080_CTRL_CE_CAPS_CE_SYSMEM_WRITE 0:0x08 +#define NV2080_CTRL_CE_CAPS_CE_NVLINK_P2P 0:0x10 +#define NV2080_CTRL_CE_CAPS_CE_SYSMEM 0:0x20 +#define NV2080_CTRL_CE_CAPS_CE_P2P 0:0x40 +#define NV2080_CTRL_CE_CAPS_CE_BL_SIZE_GT_64K_SUPPORTED 0:0x80 +#define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_NONPIPELINED_BL 1:0x01 +#define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL 1:0x02 + + + +/* + * NV2080_CTRL_CE_CAPS_CE_GRCE + * Set if the CE is synchronous with GR + * + * NV2080_CTRL_CE_CAPS_CE_SHARED + * Set if the CE shares physical CEs with any other CE + * + * NV2080_CTRL_CE_CAPS_CE_SYSMEM_READ + * Set if the CE can give enhanced performance for SYSMEM reads over other CEs + * + * NV2080_CTRL_CE_CAPS_CE_SYSMEM_WRITE + * Set if the CE can give enhanced performance for SYSMEM writes over other CEs + * + * NV2080_CTRL_CE_CAPS_CE_NVLINK_P2P + * Set if the CE can be used for P2P transactions using NVLINK + * Once a CE is exposed for P2P over NVLINK, it will remain available for the life of RM + * PCE2LCE mapping may change based on the number of GPUs registered in RM however + * + * NV2080_CTRL_CE_CAPS_CE_SYSMEM + * Set if the CE can be used for SYSMEM transactions + * + * NV2080_CTRL_CE_CAPS_CE_P2P + * Set if the CE can be used for P2P transactions + * + * NV2080_CTRL_CE_CAPS_CE_BL_SIZE_GT_64K_SUPPORTED + * Set if the CE supports BL copy size greater than 64K + * + * NV2080_CTRL_CE_CAPS_CE_SUPPORTS_NONPIPELINED_BL + * Set if the CE supports non-pipelined Block linear + * + * NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL + * Set if the CE supports pipelined Block Linear + */ + + + +/* + * NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK + * + * This command returns the mapping of PCE's for the given LCE. + * + * ceEngineType + * This parameter specifies the copy engine type + * pceMask + * This parameter specifies a mask of PCEs that correspond + * to the LCE specified in ceEngineType + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + + + +#define NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK (0x20802a02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS { + NvU32 ceEngineType; + NvU32 pceMask; +} NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS; + +/* + * NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG + * + * This command sets the PCE2LCE configuration + * + * pceLceConfig[NV2080_CTRL_MAX_PCES] + * This parameter specifies the PCE-LCE mapping requested + * grceLceConfig[NV2080_CTRL_MAX_GRCES] + * This parameter specifies which LCE is the GRCE sharing with + * 0xF -> Does not share with any LCE + * 0-MAX_LCE -> Shares with the given LCE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG (0x20802a04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MAX_PCES 32 +#define NV2080_CTRL_MAX_GRCES 2 + +#define NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS { + NvU32 ceEngineType; + NvU32 pceLceMap[NV2080_CTRL_MAX_PCES]; + NvU32 grceSharedLceMap[NV2080_CTRL_MAX_GRCES]; +} NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS; + +/* + * NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS + * + * This command updates the PCE-LCE mappings + * + * pceLceMap [IN] + * This parameter contains the array of PCE to LCE mappings. + * The array is indexed by the PCE index, and contains the + * LCE index that the PCE is assigned to. A unused PCE is + * tagged with NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE. + * + * grceConfig [IN] + * This parameter contains the array of GRCE configs. + * 0xF -> GRCE does not share with any LCE + * 0-MAX_LCE -> GRCE shares with the given LCE + * + * exposeCeMask [IN] + * This parameter specifies the mask of LCEs to export to the + * clients after the update. + * + * bUpdateNvlinkPceLce [IN] + * Whether PCE-LCE mappings need to be updated for nvlink topology. + * If this is NV_FALSE, RM would ignore the above values. However, + * PCE-LCE mappings will still be updated if there were any regkey + * overrides. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ + +#define NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS (0x20802a05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS { + NvU32 pceLceMap[NV2080_CTRL_MAX_PCES]; + NvU32 grceConfig[NV2080_CTRL_MAX_GRCES]; + NvU32 exposeCeMask; + NvBool bUpdateNvlinkPceLce; +} NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS; + +#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE 0xf + +/* + * NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB + * + * This function triggers an update of the exported CE classes. CEs with + * no physical resources will not be exported. A record of these + * will be return in in the stubbedCeMask. + * + * An example if NV2080_ENGINE_TYPE_COPY4 is stubbed (1<<4) will be + * set in stubbedCeMask. + */ + + +#define NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB (0x20802a06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS { + NvU32 stubbedCeMask; +} NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS; + +/* + * NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS + * + * Query _CE_GRCE, _CE_SHARED, _CE_SUPPORTS_PIPELINED_BL, _CE_SUPPORTS_NONPIPELINED_BL bits of CE + * capabilities. + * + */ + +#define NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS (0x20802a07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | 0x7" */ + +#define NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS { + NvU32 size; +} NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS; + +#define NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE (0x20802a08) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASKS + * + * Get HSHUB and FBHUB PCE masks. + * + * [out] hshubPceMasks + * PCE mask for each HSHUB + * [out] fbhubPceMask + * FBHUB PCE mask + */ + +#define NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK (0x20802a09) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_MAX_HSHUBS 5 + +#define NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS { + NvU32 hshubPceMasks[NV2080_CTRL_CE_MAX_HSHUBS]; + NvU32 fbhubPceMask; +} NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS; + +/* + * NV2080_CTRL_CMD_CE_GET_ALL_CAPS + * + * Query caps of all CEs. + * + * [out] capsTbl + * Array of CE caps in the order of CEs. The caps bits interpretation is the same as in + * NV2080_CTRL_CMD_CE_GET_CAPS. + * [out] present + * Bit mask indicating which CEs are usable by the client and have their caps indicated in capsTbl. + * If a CE is not marked present, its caps bits should be ignored. + * If client is subscribed to a MIG instance, only the CEs present in the instance are tagged as such. + */ + +#define NV2080_CTRL_CMD_CE_GET_ALL_CAPS (0x20802a0a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID (0xaU) + +typedef struct NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS { + NvU8 capsTbl[NV2080_CTRL_MAX_PCES][NV2080_CTRL_CE_CAPS_TBL_SIZE]; + NvU32 present; +} NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS; + +#define NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS (0x20802a0b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | 0xb" */ + +/* _ctrl2080ce_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080cipher.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080cipher.h new file mode 100644 index 0000000..55b9964 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080cipher.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080cipher.finn +// + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h new file mode 100644 index 0000000..20b8f4f --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080clk.finn +// + + + +/* _ctrl2080clk_h_ */ +#include "nvfixedtypes.h" +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "ctrl/ctrl2080/ctrl2080boardobj.h" +#include "ctrl/ctrl2080/ctrl2080gpumon.h" +#include "ctrl/ctrl2080/ctrl2080clkavfs.h" +#include "ctrl/ctrl2080/ctrl2080volt.h" +#include "ctrl/ctrl2080/ctrl2080pmumon.h" + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h new file mode 100644 index 0000000..570987b --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h @@ -0,0 +1,36 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080clkavfs.finn +// + + + +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "ctrl/ctrl2080/ctrl2080boardobj.h" +#include "ctrl/ctrl2080/ctrl2080volt.h" + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h new file mode 100644 index 0000000..e72e63c --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h @@ -0,0 +1,183 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080dma.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX dma control commands and parameters */ + +/* + * NV2080_CTRL_CMD_DMA_INVALIDATE_TLB + * + * This command invalidates the GPU TLB. This is intended to be used + * by RM clients that manage their own TLB consistency when updating + * page tables on their own, or with DEFER_TLB_INVALIDATION options + * to other RM APIs. + * + * hVASpace + * This parameter specifies the VASpace object whose MMU TLB entries needs to be invalidated. + * Specifying a GMMU VASpace object handle will invalidate the GMMU TLB for the particular VASpace. + * Specifying a SMMU VASpace object handle will flush the entire SMMU TLB & PTC. + * + * This call can be used with the NV50_DEFERRED_API_CLASS (class 0x5080). + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_TIMEOUT_RETRY + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_DMA_INVALIDATE_TLB (0x20802502) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMA_INTERFACE_ID << 8) | NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS { + NvHandle hClient; // Deprecated. Kept here for compactibility with chips_GB9-2-1-1 + NvHandle hDevice; // Deprecated. Kept here for compactibility with chips_GB9-2-1-1 + NvU32 engine; // Deprecated. Kept here for compactibility with chips_GB9-2-1-1 + NvHandle hVASpace; +} NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS; + +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS 0:0 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO 1:1 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY 2:2 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE 3:3 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB 4:4 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV 5:5 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG 6:6 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD 7:7 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION 8:8 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON 9:9 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS 10:10 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_TRUE (0x00000001) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR 11:11 +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_FALSE (0x00000000) +#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_TRUE (0x00000001) + +/* + * NV2080_CTRL_DMA_INFO + * + * This structure represents a single 32bit dma engine value. Clients + * request a particular DMA engine value by specifying a unique dma + * information index. + * + * Legal dma information index values are: + * NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE + * This index can be used to request the system address size in bits. + */ +typedef struct NV2080_CTRL_DMA_INFO { + NvU32 index; + NvU32 data; +} NV2080_CTRL_DMA_INFO; + +/* valid dma info index values */ +#define NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE (0x000000000) + +/* set INDEX_MAX to greatest possible index value */ +#define NV2080_CTRL_DMA_INFO_INDEX_MAX NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE + +/* + * NV2080_CTRL_CMD_DMA_GET_INFO + * + * This command returns dma engine information for the associated GPU. + * Requests to retrieve dma information use an array of one or more + * NV2080_CTRL_DMA_INFO structures. + * + * dmaInfoTblSize + * This field specifies the number of valid entries in the dmaInfoList + * array. This value cannot exceed NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES. + * dmaInfoTbl + * This parameter contains the client's dma info table into + * which the dma info values will be transferred by the RM. + * The dma info table is an array of NV2080_CTRL_DMA_INFO structures. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_DMA_GET_INFO (0x20802503) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMA_INTERFACE_ID << 8) | NV2080_CTRL_DMA_GET_INFO_PARAMS_MESSAGE_ID" */ + +/* maximum number of NV2080_CTRL_DMA_INFO entries per request */ +#define NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES (256) + +#define NV2080_CTRL_DMA_GET_INFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_DMA_GET_INFO_PARAMS { + NvU32 dmaInfoTblSize; + /* + * C form: + * NV2080_CTRL_DMA_INFO dmaInfoTbl[NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES]; + */ + NV2080_CTRL_DMA_INFO dmaInfoTbl[NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES]; +} NV2080_CTRL_DMA_GET_INFO_PARAMS; + +typedef struct NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO { + /*! + * 64KB aligned address of source 64KB tile for comptag reswizzle. + */ + NvU32 srcAddr; + + /*! + * 64KB aligned address of destination 64KB tile for comptag reswizzle. + */ + NvU32 dstAddr; + + /*! + * Comptag index assigned to the 64K sized tile relative to + * the compcacheline. Absolute comptag index would be: + * startComptagIndex + relComptagIndex. + */ + NvU16 relComptagIndex; +} NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO; + +// _ctrl2080dma_h_ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h new file mode 100644 index 0000000..982381f --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h @@ -0,0 +1,105 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080dmabuf.finn +// + + + +/* + * NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD + * + * Exports RM vidmem handles to a dma-buf fd. + * + * The objects in the 'handles' array are exported to the fd as range: + * [index, index + numObjects). + * + * A dma-buf fd is created the first time this control call is called. + * The fd is an input parameter for subsequent calls to attach additional handles + * over NV2080_CTRL_DMABUF_MAX_HANDLES. + * + * fd + * A dma-buf file descriptor. If -1, a new FD will be created. + * + * totalObjects + * The total number of objects that the client wishes to export to the FD. + * This parameter will be honored only when the FD is getting created. + * + * numObjects + * The number of handles the user wishes to export in this call. + * + * index + * The index into the export fd at which to start exporting the handles in + * 'handles'. This index cannot overlap a previously used index. + * + * totalSize + * The total size of memory being exported in bytes, needed to create the dma-buf. + * This size includes the memory that will be exported in future export calls + * for this dma-buf. + * + * handles + * An array of {handle, offset, size} that describes the dma-buf. + * The offsets and sizes must be OS page-size aligned. + * + * Limitations: + * 1. This call only supports vidmem objects for now. + * 2. All memory handles should belong to the same GPU or the same GPU MIG instance. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_NO_MEMORY + * NV_ERR_OPERATING_SYSTEM + * NV_ERR_IN_USE + * NV_ERR_INVALID_OBJECT + * NV_ERR_INVALID_OBJECT_PARENT + */ +#define NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD (0x20803a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMABUF_INTERFACE_ID << 8) | NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_DMABUF_MAX_HANDLES 128 + +typedef struct NV2080_CTRL_DMABUF_MEM_HANDLE_INFO { + NvHandle hMemory; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); +} NV2080_CTRL_DMABUF_MEM_HANDLE_INFO; + +#define NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS { + NvS32 fd; + NvU32 totalObjects; + NvU32 numObjects; + NvU32 index; + NV_DECLARE_ALIGNED(NvU64 totalSize, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_DMABUF_MEM_HANDLE_INFO handles[NV2080_CTRL_DMABUF_MAX_HANDLES], 8); +} NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS; + +// _ctrl2080dmabuf_h_ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h new file mode 100644 index 0000000..7d0fabe --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080ecc.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + + + +#define NV2080_CTRL_CMD_ECC_GET_CLIENT_EXPOSED_COUNTERS (0x20803400U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS + * + * sramLastClearedTimestamp [out] + * dramLastClearedTimestamp [out] + * unix-epoch based timestamp. These fields indicate when the error counters + * were last cleared by the user. + * + * sramErrorCounts [out] + * dramErrorCounts [out] + * Aggregate error counts for SRAM and DRAM + */ + +#define NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID (0x0U) + +typedef struct NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS { + NvU32 sramLastClearedTimestamp; + NvU32 dramLastClearedTimestamp; + + NV_DECLARE_ALIGNED(NvU64 sramCorrectedTotalCounts, 8); + NV_DECLARE_ALIGNED(NvU64 sramUncorrectedTotalCounts, 8); + NV_DECLARE_ALIGNED(NvU64 dramCorrectedTotalCounts, 8); + NV_DECLARE_ALIGNED(NvU64 dramUncorrectedTotalCounts, 8); +} NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS; +/* _ctrl2080ecc_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h new file mode 100644 index 0000000..e71eb81 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h @@ -0,0 +1,372 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080event.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +#include "nv_vgpu_types.h" +/* NV20_SUBDEVICE_XX event-related control commands and parameters */ + +/* + * NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * This command sets event notification state for the associated subdevice. + * This command requires that an instance of NV01_EVENT has been previously + * bound to the associated subdevice object. + * + * event + * This parameter specifies the type of event to which the specified + * action is to be applied. This parameter must specify a valid + * NV2080_NOTIFIERS value (see cl2080.h for more details) and should + * not exceed one less NV2080_NOTIFIERS_MAXCOUNT. + * action + * This parameter specifies the desired event notification action. + * Valid notification actions include: + * NV2080_CTRL_SET_EVENT_NOTIFICATION_DISABLE + * This action disables event notification for the specified + * event for the associated subdevice object. + * NV2080_CTRL_SET_EVENT_NOTIFICATION_SINGLE + * This action enables single-shot event notification for the + * specified event for the associated subdevice object. + * NV2080_CTRL_SET_EVENT_NOTIFICATION_REPEAT + * This action enables repeated event notification for the specified + * event for the associated system controller object. + * bNotifyState + * This boolean is used to indicate the current state of the notifier + * at the time of event registration. This is optional and its semantics + * needs to be agreed upon by the notifier and client using the notifier + * info32 + * This is used to send 32-bit initial state info with the notifier at + * time of event registration + * info16 + * This is used to send 16-bit initial state info with the notifier at + * time of event registration + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION (0x20800301) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS { + NvU32 event; + NvU32 action; + NvBool bNotifyState; + NvU32 info32; + NvU16 info16; +} NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001) +#define NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002) + +/* XUSB/PPC D-state defines */ +#define NV2080_EVENT_DSTATE_XUSB_D0 (0x00000000) +#define NV2080_EVENT_DSTATE_XUSB_D3 (0x00000003) +#define NV2080_EVENT_DSTATE_XUSB_INVALID (0xFFFFFFFF) +#define NV2080_EVENT_DSTATE_PPC_D0 (0x00000000) +#define NV2080_EVENT_DSTATE_PPC_D3 (0x00000003) +#define NV2080_EVENT_DSTATE_PPC_INVALID (0xFFFFFFFF) + +// HDACODEC Decice DState, D3_COLD is only for verbose mapping, it cannot be logged +typedef enum NV2080_EVENT_HDACODEC_DSTATE { + NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D0 = 0, + NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D1 = 1, + NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D2 = 2, + NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_HOT = 3, + NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_COLD = 4, + NV2080_EVENT_HDACODEC_DEVICE_DSTATE_DSTATE_MAX = 5, +} NV2080_EVENT_HDACODEC_DSTATE; + +/* + * NV2080_CTRL_CMD_EVENT_SET_TRIGGER + * + * This command triggers a software event for the associated subdevice. + * This command accepts no parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_EVENT_SET_TRIGGER (0x20800302) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | 0x2" */ + +/* + * NV2080_CTRL_CMD_EVENT_SET_NOTIFIER_MEMORY + * + * hMemory + * This parameter specifies the handle of the memory object + * that identifies the memory address translation for this + * subdevice instance's notification(s). The beginning of the + * translation points to an array of notification data structures. + * The size of the translation must be at least large enough to hold the + * maximum number of notification data structures identified by + * the NV2080_MAX_NOTIFIERS value. + * Legal argument values must be instances of the following classes: + * NV01_NULL + * NV04_MEMORY + * When hMemory specifies the NV01_NULL_OBJECT value then any existing + * memory translation connection is cleared. There must not be any + * pending notifications when this command is issued. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES (0x20800303) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS { + NvHandle hMemory; +} NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS; + +#define NV2080_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED 0 +#define NV2080_EVENT_MEMORY_NOTIFIES_STATUS_PENDING 1 +#define NV2080_EVENT_MEMORY_NOTIFIES_STATUS_ERROR 2 + +/* + * NV2080_CTRL_CMD_EVENT_SET_SEMAPHORE_MEMORY + * + * hSemMemory + * This parameter specifies the handle of the memory object that + * identifies the semaphore memory associated with this subdevice + * event notification. Once this is set RM will generate an event + * only when there is a change in the semaphore value. It is + * expected that the semaphore memory value will be updated by + * the GPU indicating that there is an event pending. This + * command is used by VGX plugin to determine which virtual + * machine has generated a particular event. + * + * semOffset + * This parameter indicates the memory offset of the semaphore. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_EVENT_SET_SEMAPHORE_MEMORY (0x20800304) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS { + NvHandle hSemMemory; + NvU32 semOffset; +} NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS; + +/* + * NV2080_CTRL_CMD_EVENT_SET_GUEST_MSI + * + * hSemMemory + * This parameter specifies the handle of the memory object that + * identifies the semaphore memory associated with this subdevice + * event notification. Once this is set RM will generate an event + * only when there is a change in the semaphore value. It is + * expected that the semaphore memory value will be updated by + * the GPU indicating that there is an event pending. This + * command is used by VGX plugin to determine which virtual + * machine has generated a particular event. + * + * guestMSIAddr + * This parameter indicates the guest allocated MSI address. + * + * guestMSIData + * This parameter indicates the MSI data set by the guest OS. + * + * vmIdType + * This parameter specifies the type of guest virtual machine identifier + * + * guestVmId + * This parameter specifies the guest virtual machine identifier + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_EVENT_SET_GUEST_MSI (0x20800305) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS { + NV_DECLARE_ALIGNED(NvU64 guestMSIAddr, 8); + NvU32 guestMSIData; + NvHandle hSemMemory; + NvBool isReset; + VM_ID_TYPE vmIdType; + NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); +} NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS; + + +/* + * NV2080_CTRL_CMD_EVENT_SET_SEMA_MEM_VALIDATION + * + * hSemMemory + * This parameter specifies the handle of the memory object that + * identifies the semaphore memory associated with this subdevice + * event notification. Once this is set RM will generate an event + * only when there is a change in the semaphore value. It is + * expected that the semaphore memory value will be updated by + * the GPU indicating that there is an event pending. This + * command is used by VGX plugin to determine which virtual + * machine has generated a particular event. + * + * isSemaMemValidationEnabled + * This parameter used to enable/disable change in sema value check + * while generating an event. + * + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + * NVOS_STATUS_ERROR_INVALID_OBJECT_HANDLE + * NVOS_STATUS_ERROR_INVALID_ARGUMENT + */ + + +#define NV2080_CTRL_CMD_EVENT_SET_SEMA_MEM_VALIDATION (0x20800306) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS { + NvHandle hSemMemory; + NvBool isSemaMemValidationEnabled; +} NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS; + + +/* + * NV2080_CTRL_CMD_EVENT_SET_VMBUS_CHANNEL + * + * hSemMemory + * This parameter specifies the handle of the memory object that + * identifies the semaphore memory associated with this subdevice + * event notification. Once this is set RM will generate an event + * only when there is a change in the semaphore value. It is + * expected that the semaphore memory value will be updated by + * the GPU indicating that there is an event pending. This + * command is used by VGX plugin to determine which virtual + * machine has generated a particular event. + * + * vmIdType + * This parameter specifies the type of guest virtual machine identifier + * + * guestVmId + * This parameter specifies the guest virtual machine identifier + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_EVENT_SET_VMBUS_CHANNEL (0x20800307) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS { + NvHandle hSemMemory; + VM_ID_TYPE vmIdType; + NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); +} NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS; + + +/* + * NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO + * + * This command triggers a FIFO event for the associated subdevice. + * + * hEvent + * Handle of the event that should be notified. If zero, all + * non-stall interrupt events for this subdevice will be notified. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO (0x20800308) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS { + NvHandle hEvent; +} NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS; + +/* + * NV2080_CTRL_CMD_EVENT_VIDEO_BIND_EVTBUF_FOR_UID + * + * This command is used to create a video bind-point to an event buffer that + * is filtered by UID. + * + * hEventBuffer[IN] + * The event buffer to bind to + * + * recordSize[IN] + * The size of the FECS record in bytes + * + * levelOfDetail[IN] + * One of NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_: + * FULL: Report all CtxSw events + * SIMPLE: Report engine start and engine end events only + * CUSTOM: Report events in the eventFilter field + * NOTE: RM may override the level-of-detail depending on the caller + * + * eventFilter[IN] + * Bitmask of events to report if levelOfDetail is CUSTOM + * + * bAllUsers[IN] + * Only report video data for the current user if false, for all users if true + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_EVENT_VIDEO_BIND_EVTBUF (0x20800309) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD { + NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_FULL = 0, + NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_SIMPLE = 1, + NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_CUSTOM = 2, +} NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD; + +#define NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS { + NvHandle hEventBuffer; + NvU32 recordSize; + NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD levelOfDetail; + NvU32 eventFilter; + NvBool bAllUsers; +} NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS; + +/* _ctrl2080event_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fan.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fan.h new file mode 100644 index 0000000..a338bab --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fan.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080fan.finn +// + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h new file mode 100644 index 0000000..a883326 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h @@ -0,0 +1,2906 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080fb.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX fb control commands and parameters */ + +#include "nvlimits.h" + +/* + * NV2080_CTRL_FB_INFO + * + * This structure represents a single 32bit fb engine value. Clients + * request a particular fb engine value by specifying a unique fb + * information index. + * + * Legal fb information index values are: + * NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT + * This index is used to request the number of tiled regions supported + * by the associated subdevice. The return value is GPU + * implementation-dependent. A return value of 0 indicates the GPU + * does not support tiling. + * NV2080_CTRL_FB_INFO_INDEX_COMPRESSION_SIZE + * This index is used to request the amount of compression (in bytes) + * supported by the associated subdevice. The return value is GPU + * implementation-dependent. A return value of 0 indicates the GPU + * does not support compression. + * Nv2080_CTRL_FB_INFO_INDEX_DRAM_PAGE_STRIDE + * This index is used to request the DRAM page stride (in bytes) + * supported by the associated subdevice. The return value is GPU + * implementation-dependent. + * NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_FREE_COUNT + * This index is used to request the number of free tiled regions on + * the associated subdevice. The return value represents the current + * number of free tiled regions at the time the command is processed and + * is not guaranteed to remain unchanged. A return value of 0 indicates + * that there are no available tiled regions on the associated subdevice. + * NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT + * This index is used to request the number of frame buffer partitions + * on the associated subdevice. Starting with Fermi there are now two units + * with the name framebuffer partitions. On those chips this index returns + * the number of FBPAs. For number of FBPs use + * NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE + * This index is used to request the amount of framebuffer memory in + * kilobytes physically present on the associated subdevice. This + * value will never exceed the value reported by + * NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE. + * This an SMC aware attribute, so the per-partition framebuffer memory + * size will be returned when the client has a partition subscription. + * NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE + * This index is used to request the total amount of video memory in + * kilobytes for use with the associated subdevice. This value will + * reflect both framebuffer memory as well as any system memory dedicated + * for use with the subdevice. + * This an SMC aware attribute, so the per-partition video memory size + * will be returned when the client has a partition subscription. + * NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE + * This index is used to request the amount of total RAM in kilobytes + * available for user allocations. This value reflects the total ram + * size less the amount of memory reserved for internal use. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_HEAP_START + * This index is used to request the offset for start of heap in + * kilobytes. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE + * This index is used to request the available amount of video memory in + * kilobytes for use with the associated subdevice or the SMC partition. + * This an SMC aware attribute, thus necessary partition subscription is + * required to query per partition information, if the device is partitioned. + * Alternatively, the SMC/MIG monitor capability can be acquired to query + * aggregate available memory across all the valid partitions. + * NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE + * This index reflects the amount of heap memory in kilobytes that + * is accessible by the CPU. On subdevices with video memory sizes that + * exceed the amount that can be bus mappable this value will be less + * than that reported by NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_BUS_WIDTH + * This index is used to request the FB bus bandwidth on the associated + * subdevice. + * NV2080_CTRL_FB_INFO_INDEX_RAM_CFG + * This index is used to request the implementation-dependent RAM + * configuration value of the associated subdevice. + * NV2080_CTRL_FB_INFO_INDEX_RAM_TYPE + * This index is used to request the type of RAM used for the framebuffer + * on the associated subdevice. Legal RAM types include: + * NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN + * NV2080_CTRL_FB_INFO_RAM_TYPE_SDRAM + * NV2080_CTRL_FB_INFO_RAM_TYPE_DDR1 + * NV2080_CTRL_FB_INFO_RAM_TYPE_DDR2 + * NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR2 + * NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR3 + * NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR4 + * NV2080_CTRL_FB_INFO_RAM_TYPE_DDR3 + * NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5 + * NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5X + * NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6 + * NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6X + * NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR2 + * NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR4 + * NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5 + * NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT + * This index is used to request the number of FB banks on the associated + * subdevice. + * NV2080_CTRL_FB_INFO_INDEX_OVERLAY_OFFSET_ADJUSTMENT + * This index is used to request the offset relative to the start of the + * overlay surface(s), in bytes, at which scanout should happen if the + * primary and the overlay surfaces are all aligned on large page + * boundaries. + * NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_SPACE_SIZE_KB + * This index is used to request the size of the GPU's virtual address + * space in kilobytes. + * NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_HEAP_SIZE_KB + * This index is used to request the size of the GPU's virtual address + * space heap (minus RM-reserved space) in kilobytes. + * NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_MAPPBLE_SIZE_KB + * This index is used to request the size of the GPU's BAR1 mappable + * virtual address space in kilobytes. + * NV2080_CTRL_FB_INFO_INDEX_EFFECTIVE_BW + * This index is deprecated, and returns zero value. + * NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK + * This index is used to request the mask of currently active partitions. + * Each active partition has an ID that's equivalent to the corresponding + * bit position in the mask. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE + * This index is used to request the amount of total RAM in kilobytes + * reserved for internal RM allocations on Vista. This will need to + * be subtracted from the total heap size to get the amount available to + * KMD. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_RAM_LOCATION + * This index is used to distinguish between different memory + * configurations. + * NV2080_CTRL_FB_INFO_INDEX_FB_IS_BROKEN + * This index is used to check if the FB is functional + * NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT + * This index is used to get the number of FBPs on the subdevice. This + * field is not to be confused with + * NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT (returns number of FBPAs). + * Starting with Fermi the term partition is an ambiguous term, both FBP + * and FBPA mean FB partitions. The FBPA is the low level DRAM controller, + * while a FBP is the aggregation of one or more FBPAs, L2, ROP, and some + * other units. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_L2CACHE_SIZE + * This index is used to get the size of the L2 cache in Bytes. + * A value of zero indicates that the L2 cache isn't supported on the + * associated subdevice. + * NV2080_CTRL_FB_INFO_INDEX_MEMORYINFO_VENDOR_ID + * This index is used to get the memory vendor ID information from + * the Memory Information Table in the VBIOS. Legal memory Vendor ID + * values include: + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_UNKNOWN + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_RESERVED + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_SAMSUNG + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_QIMONDA + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ELPIDA + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ETRON + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_NANYA + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_HYNIX + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MOSEL + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_WINBOND + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ESMT + * NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MICRON + * NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE + * This index is used to request the amount of unused bar1 space. The + * data returned is a value in KB. It is not guaranteed to be entirely + * accurate since it is a snapshot at a particular time and can + * change quickly. + * NV2080_CTRL_FB_INFO_INDEX_BAR1_MAX_CONTIGUOUS_AVAIL_SIZE + * This index is used to request the amount of largest unused contiguous + * block in bar1 space. The data returned is a value in KB. It is not + * guaranteed to be entirely accurate since it is a snapshot at a particular + * time and can change quickly. + * NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE + * This index is used to request the amount of usable framebuffer memory in + * kilobytes physically present on the associated subdevice. This + * value will never exceed the value reported by + * NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_LTC_COUNT + * Returns the active LTC count across all active FBPs. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_LTS_COUNT + * Returns the active LTS count across all active LTCs. + * This an SMC aware attribute, thus necessary partition subscription is + * required if the device is partitioned. + * NV2080_CTRL_FB_INFO_INDEX_PSEUDO_CHANNEL_MODE + * This is used to identify if pseudo-channel mode is enabled for HBM + * NV2080_CTRL_FB_INFO_INDEX_SMOOTHDISP_RSVD_BAR1_SIZE + * This is used by WDDM-KMD to determine whether and how much RM reserved BAR1 for smooth transition + * NV2080_CTRL_FB_INFO_INDEX_HEAP_OFFLINE_SIZE + * Returns the total size of the all dynamically offlined pages in KiB + * NV2080_CTRL_FB_INFO_INDEX_1TO1_COMPTAG_ENABLED + * Returns true if 1to1 comptag is enabled + * NV2080_CTRL_FB_INFO_INDEX_SUSPEND_RESUME_RSVD_SIZE + * Returns the total size of the memory(FB) that will saved/restored during save/restore cycle + * NV2080_CTRL_FB_INFO_INDEX_ALLOW_PAGE_RETIREMENT + * Returns true if page retirement is allowed + * NV2080_CTRL_FB_INFO_POISON_FUSE_ENABLED + * Returns true if poison fuse is enabled + * NV2080_CTRL_FB_INFO_FBPA_ECC_ENABLED + * Returns true if ECC is enabled for FBPA + * NV2080_CTRL_FB_INFO_DYNAMIC_PAGE_OFFLINING_ENABLED + * Returns true if dynamic page blacklisting is enabled + * NV2080_CTRL_FB_INFO_INDEX_FORCED_BAR1_64KB_MAPPING_ENABLED + * Returns true if 64KB mapping on BAR1 is force-enabled + * NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_SIZE + * Returns the P2P mailbox size to be allocated by the client. + * Returns 0 if the P2P mailbox is allocated by RM. + * NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_ALIGNMENT_SIZE + * Returns the P2P mailbox alignment requirement. + * Returns 0 if the P2P mailbox is allocated by RM. + * NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_BAR1_MAX_OFFSET_64KB + * Returns the P2P mailbox max offset requirement. + * Returns 0 if the P2P mailbox is allocated by RM. + * NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB + * Returns total protected memory when memory protection is enabled + * Returns 0 when memory protection is not enabled. + * NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB + * Returns protected memory available for allocation when memory + * protection is enabled. + * Returns 0 when memory protection is not enabled. + * NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE + * Returns the ECC status size (corresponds to subpartitions or channels + * depending on architecture/memory type). + */ +typedef struct NV2080_CTRL_FB_INFO { + NvU32 index; + NvU32 data; +} NV2080_CTRL_FB_INFO; + +/* valid fb info index values */ +#define NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT (0x00000000U) // Deprecated +#define NV2080_CTRL_FB_INFO_INDEX_COMPRESSION_SIZE (0x00000001U) +#define NV2080_CTRL_FB_INFO_INDEX_DRAM_PAGE_STRIDE (0x00000002U) +#define NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_FREE_COUNT (0x00000003U) +#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT (0x00000004U) +#define NV2080_CTRL_FB_INFO_INDEX_BAR1_SIZE (0x00000005U) +#define NV2080_CTRL_FB_INFO_INDEX_BANK_SWIZZLE_ALIGNMENT (0x00000006U) +#define NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE (0x00000007U) +#define NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE (0x00000008U) +#define NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE (0x00000009U) +#define NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE (0x0000000AU) +#define NV2080_CTRL_FB_INFO_INDEX_BUS_WIDTH (0x0000000BU) +#define NV2080_CTRL_FB_INFO_INDEX_RAM_CFG (0x0000000CU) +#define NV2080_CTRL_FB_INFO_INDEX_RAM_TYPE (0x0000000DU) +#define NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT (0x0000000EU) +#define NV2080_CTRL_FB_INFO_INDEX_OVERLAY_OFFSET_ADJUSTMENT (0x0000000FU) // Deprecated (index reused to return 0) +#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_SPACE_SIZE_KB (0x0000000FU) // Deprecated (index reused to return 0) +#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_HEAP_SIZE_KB (0x0000000FU) // Deprecated (index reused to return 0) +#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_MAPPBLE_SIZE_KB (0x0000000FU) // Deprecated (index reused to return 0) +#define NV2080_CTRL_FB_INFO_INDEX_EFFECTIVE_BW (0x0000000FU) // Deprecated (index reused to return 0) +#define NV2080_CTRL_FB_INFO_INDEX_FB_TAX_SIZE_KB (0x00000010U) +#define NV2080_CTRL_FB_INFO_INDEX_HEAP_BASE_KB (0x00000011U) +#define NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_SIZE_KB (0x00000012U) +#define NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_BASE_KB (0x00000013U) +#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK (0x00000014U) +#define NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE (0x00000015U) +#define NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE (0x00000016U) +#define NV2080_CTRL_FB_INFO_INDEX_RAM_LOCATION (0x00000017U) +#define NV2080_CTRL_FB_INFO_INDEX_FB_IS_BROKEN (0x00000018U) +#define NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT (0x00000019U) +#define NV2080_CTRL_FB_INFO_INDEX_FBP_MASK (0x0000001AU) +#define NV2080_CTRL_FB_INFO_INDEX_L2CACHE_SIZE (0x0000001BU) +#define NV2080_CTRL_FB_INFO_INDEX_MEMORYINFO_VENDOR_ID (0x0000001CU) +#define NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE (0x0000001DU) +#define NV2080_CTRL_FB_INFO_INDEX_HEAP_START (0x0000001EU) +#define NV2080_CTRL_FB_INFO_INDEX_BAR1_MAX_CONTIGUOUS_AVAIL_SIZE (0x0000001FU) +#define NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE (0x00000020U) +#define NV2080_CTRL_FB_INFO_INDEX_TRAINIG_2T (0x00000021U) +#define NV2080_CTRL_FB_INFO_INDEX_LTC_COUNT (0x00000022U) +#define NV2080_CTRL_FB_INFO_INDEX_LTS_COUNT (0x00000023U) +#define NV2080_CTRL_FB_INFO_INDEX_L2CACHE_ONLY_MODE (0x00000024U) +#define NV2080_CTRL_FB_INFO_INDEX_PSEUDO_CHANNEL_MODE (0x00000025U) +#define NV2080_CTRL_FB_INFO_INDEX_SMOOTHDISP_RSVD_BAR1_SIZE (0x00000026U) +#define NV2080_CTRL_FB_INFO_INDEX_HEAP_OFFLINE_SIZE (0x00000027U) +#define NV2080_CTRL_FB_INFO_INDEX_1TO1_COMPTAG_ENABLED (0x00000028U) +#define NV2080_CTRL_FB_INFO_INDEX_SUSPEND_RESUME_RSVD_SIZE (0x00000029U) +#define NV2080_CTRL_FB_INFO_INDEX_ALLOW_PAGE_RETIREMENT (0x0000002AU) +#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK (0x0000002BU) +#define NV2080_CTRL_FB_INFO_POISON_FUSE_ENABLED (0x0000002CU) +#define NV2080_CTRL_FB_INFO_FBPA_ECC_ENABLED (0x0000002DU) +#define NV2080_CTRL_FB_INFO_DYNAMIC_PAGE_OFFLINING_ENABLED (0x0000002EU) +#define NV2080_CTRL_FB_INFO_INDEX_FORCED_BAR1_64KB_MAPPING_ENABLED (0x0000002FU) +#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_SIZE (0x00000030U) +#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_ALIGNMENT (0x00000031U) +#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_BAR1_MAX_OFFSET_64KB (0x00000032U) +#define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB (0x00000033U) +#define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB (0x00000034U) +#define NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE (0x00000035U) +#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE (0x00000036U) + +#define NV2080_CTRL_FB_INFO_INDEX_MAX (0x35U) /* finn: Evaluated from "(NV2080_CTRL_FB_INFO_MAX_LIST_SIZE - 1)" */ + +/* valid fb RAM type values */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN (0x00000000U) +#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDRAM (0x00000001U) +#define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR1 (0x00000002U) /* SDDR and GDDR (aka DDR1 and GDDR1) */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2 (0x00000003U) /* SDDR2 Used on NV43 and later */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR2 NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2 /* Deprecated alias */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR2 (0x00000004U) /* GDDR2 Used on NV30 and some NV36 */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR3 (0x00000005U) /* GDDR3 Used on NV40 and later */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR4 (0x00000006U) /* GDDR4 Used on G80 and later (deprecated) */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3 (0x00000007U) /* SDDR3 Used on G9x and later */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR3 NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3 /* Deprecated alias */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5 (0x00000008U) /* GDDR5 Used on GT21x and later */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR2 (0x00000009U) /* LPDDR (Low Power SDDR) used on T2x and later. */ + + +#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR4 (0x0000000CU) /* SDDR4 Used on Maxwell and later */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR4 (0x0000000DU) /* LPDDR (Low Power SDDR) used on T21x and later.*/ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM1 (0x0000000EU) /* HBM1 (High Bandwidth Memory) used on GP100 */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM2 (0x0000000FU) /* HBM2 (High Bandwidth Memory-pseudo channel) */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5X (0x00000010U) /* GDDR5X Used on GP10x */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6 (0x00000011U) /* GDDR6 Used on TU10x */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6X (0x00000012U) /* GDDR6X Used on GA10x */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5 (0x00000013U) /* LPDDR (Low Power SDDR) used on T23x and later.*/ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM3 (0x00000014U) /* HBM3 (High Bandwidth Memory) v3 */ + +/* valid RAM LOCATION types */ +#define NV2080_CTRL_FB_INFO_RAM_LOCATION_GPU_DEDICATED (0x00000000U) +#define NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_SHARED (0x00000001U) +#define NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_DEDICATED (0x00000002U) + +/* valid Memory Vendor ID values */ +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_SAMSUNG (0x00000001U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_QIMONDA (0x00000002U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ELPIDA (0x00000003U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ETRON (0x00000004U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_NANYA (0x00000005U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_HYNIX (0x00000006U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MOSEL (0x00000007U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_WINBOND (0x00000008U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ESMT (0x00000009U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MICRON (0x0000000FU) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_UNKNOWN (0xFFFFFFFFU) + +#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_UNSUPPORTED (0x00000000U) +#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_DISABLED (0x00000001U) +#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_ENABLED (0x00000002U) + +/** + * NV2080_CTRL_CMD_FB_GET_INFO + * + * This command returns fb engine information for the associated GPU. + * Requests to retrieve fb information use a list of one or more + * NV2080_CTRL_FB_INFO structures. + * + * fbInfoListSize + * This field specifies the number of entries on the caller's + * fbInfoList. + * fbInfoList + * This field specifies a pointer in the caller's address space + * to the buffer into which the fb information is to be returned. + * This buffer must be at least as big as fbInfoListSize multiplied + * by the size of the NV2080_CTRL_FB_INFO structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV2080_CTRL_CMD_FB_GET_INFO (0x20801301U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_FB_GET_INFO_PARAMS { + NvU32 fbInfoListSize; + NV_DECLARE_ALIGNED(NvP64 fbInfoList, 8); +} NV2080_CTRL_FB_GET_INFO_PARAMS; + +#define NV2080_CTRL_CMD_FB_GET_INFO_V2 (0x20801303U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_INFO_V2_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_FB_GET_INFO_V2_PARAMS { + NvU32 fbInfoListSize; + NV2080_CTRL_FB_INFO fbInfoList[NV2080_CTRL_FB_INFO_MAX_LIST_SIZE]; +} NV2080_CTRL_FB_GET_INFO_V2_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_GET_TILE_ADDRESS_INFO + * + * This command returns tile addressing information. + * + * StartAddr + * This parameter returns BAR1 plus the size of the local FB. + * SpaceSize + * This parameter returns the BAR1 aperture size less the size of the + * local FB. + * + * Note that both parameters will contain zero if there is no system tile + * address space. + */ +#define NV2080_CTRL_CMD_FB_GET_TILE_ADDRESS_INFO (0x20801302U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2" */ + +typedef struct NV2080_CTRL_FB_GET_SYSTEM_TILE_ADDRESS_SPACE_INFO { + NV_DECLARE_ALIGNED(NvU64 StartAddr, 8); + NV_DECLARE_ALIGNED(NvU64 SpaceSize, 8); +} NV2080_CTRL_FB_GET_SYSTEM_TILE_ADDRESS_SPACE_INFO; + +/* + * NV2080_CTRL_CMD_FB_GET_BAR1_OFFSET + * + * This command returns the GPU virtual address of a bar1 + * allocation, given the CPU virtual address. + * + * cpuVirtAddress + * This field specifies the associated CPU virtual address of the + * memory allocation. + * gpuVirtAddress + * The GPU virtual address associated with the allocation + * is returned in this field. + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_GET_BAR1_OFFSET (0x20801310U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS { + NV_DECLARE_ALIGNED(NvP64 cpuVirtAddress, 8); + NV_DECLARE_ALIGNED(NvU64 gpuVirtAddress, 8); +} NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS; + +/* + * Note: Returns Zeros if no System carveout address info + * + * NV2080_CTRL_CMD_FB_GET_CARVEOUT_ADDRESS_INFO + * + * This command returns FB carveout address space information + * + * StartAddr + * Returns the system memory address of the start of carveout space. + * SpaceSize + * Returns the size of carveout space. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_FB_GET_CARVEOUT_ADDRESS_INFO (0x2080130bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO_MESSAGE_ID (0xBU) + +typedef struct NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO { + NV_DECLARE_ALIGNED(NvU64 StartAddr, 8); + NV_DECLARE_ALIGNED(NvU64 SpaceSize, 8); +} NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO; + +/* + * NV2080_CTRL_FB_CMD_GET_CALIBRATION_LOCK_FAILED + * + * This command returns the failure counts for calibration. + * + * uFlags + * Just one for now -- ehether to reset the counts. + * driveStrengthRiseCount + * This parameter specifies the failure count for drive strength rising. + * driveStrengthFallCount + * This parameter specifies the failure count for drive strength falling. + * driveStrengthTermCount + * This parameter specifies the failure count for drive strength + * termination. + * slewStrengthRiseCount + * This parameter specifies the failure count for slew strength rising. + * slewStrengthFallCount + * This parameter specifies the failure count for slew strength falling. + * slewStrengthTermCount + * This parameter specifies the failure count for slew strength + * termination. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INVALID_PARAM_STRUCT + * NVOS_STATUS_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_GET_CALIBRATION_LOCK_FAILED (0x2080130cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS { + NvU32 flags; + NvU32 driveStrengthRiseCount; + NvU32 driveStrengthFallCount; + NvU32 driveStrengthTermCount; + NvU32 slewStrengthRiseCount; + NvU32 slewStrengthFallCount; +} NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS; + +/* valid flags parameter values */ +#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE (0x00000000U) +#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET (0x00000001U) + +/* + * NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOWED + * + * This command specifies to RM if scanout compaction feature is allowed or + * not in the current configuration. In hybrid mode when dGPU is rendering the + * image, the dGPU blit to the scanout surface happens without mGPU's + * knowledge (directly to system memory), which results in stale compacted + * data resulting in corruption. + * + * This control call can be used to disable the compaction whenever the KMD + * (client) is switching to the pref mode in Hybrid i.e., whenever there is a + * possibility of dGPU doing a blit to mGpu scanout surface. Compaction can + * be enabled when system is back in hybrid power mode as mGpu will be + * rendering the image. + * + * allowCompaction + * This parameter specifies if the display compaction feature is allowed + * or not allowed. + * immediate + * This parameter specifies whether compaction has to be enabled or + * disabled immediately (based on the value of allowCompaction field) or + * during the next modeset. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INVALID_PARAM_STRUCT + * NVOS_STATUS_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOWED (0x2080130dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0xD" */ // Deprecated, removed form RM + +typedef struct NV2080_CTRL_FB_SET_SCANOUT_COMPACTION_ALLOWED_PARAMS { + NvU32 allowCompaction; + NvU32 immediate; +} NV2080_CTRL_FB_SET_SCANOUT_COMPACTION_ALLOWED_PARAMS; + +/* valid allowCompaction values */ +#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOW (0x00000001U) +#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_DISALLOW (0x00000000U) + +/* valid immediate values */ +#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_IMMEDIATE (000000001U) +#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_NOT_IMMEDIATE (000000000U) + +/* + * NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE + * + * This command flushes a cache on the GPU which all memory accesses go + * through. The types of flushes supported by this API may not be supported by + * all hardware. Attempting an unsupported flush type will result in an error. + * + * addressArray + * An array of physical addresses in the aperture defined by + * NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE. Each entry points to a + * contiguous block of memory of size memBlockSizeBytes. The addresses are + * aligned down to addressAlign before coalescing adjacent addresses and + * sending flushes to hardware. + * addressAlign + * Used to align-down addresses held in addressArray. A value of 0 will be + * forced to 1 to avoid a divide by zero. Value is treated as minimum + * alignment and any hardware alignment requirements above this value will + * be honored. + * addressArraySize + * The number of entries in addressArray. + * memBlockSizeBytes + * The size in bytes of each memory block pointed to by addressArray. + * flags + * Contains flags to control various aspects of the flush. Valid values + * are defined in NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS*. Not all flags are + * valid for all defined FLUSH_MODEs or all GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + * + * See Also: + * NV0080_CTRL_CMD_DMA_FLUSH + * Performs flush operations in broadcast for the GPU cache and other hardware + * engines. Use this call if you want to flush all GPU caches in a + * broadcast device. + * NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE + * Flushes memory associated with a single allocation if the hardware + * supports it. Use this call if you want to flush a single allocation and + * you have a memory object describing the physical memory. + */ +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE (0x2080130eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES 500U + +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 addressArray[NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES], 8); + NvU32 addressArraySize; + NvU32 addressAlign; + NV_DECLARE_ALIGNED(NvU64 memBlockSizeBytes, 8); + NvU32 flags; +} NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS; + +/* valid fields and values for flags */ +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE 1:0 +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_VIDEO_MEMORY (0x00000000U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_SYSTEM_MEMORY (0x00000001U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_PEER_MEMORY (0x00000002U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK 2:2 +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_NO (0x00000000U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_YES (0x00000001U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE 3:3 +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_NO (0x00000000U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_YES (0x00000001U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE 4:4 +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_ADDRESS_ARRAY (0x00000000U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_FULL_CACHE (0x00000001U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH 5:5 +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_NO (0x00000000U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_YES (0x00000001U) + +/* + * NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY (deprecated; use NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2 instead) + * + * These commands access the cache allocation policy on a specific + * engine, if supported. + * + * engine + * Specifies the target engine. Possible values are defined in + * NV2080_ENGINE_TYPE. + * allocPolicy + * Specifies the read/write allocation policy of the cache on the specified + * engine. Possible values are defined in + * NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS and + * NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES. + * + */ +typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS { + NvU32 engine; + NvU32 allocPolicy; +} NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS; + +/* valid values for allocPolicy */ +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS 0:0 +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_NO (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_YES (0x00000001U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES 1:1 +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_NO (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_YES (0x00000001U) + + +/* + * NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY + * + * This command is deprecated. + * Use NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2 instead. + * + * This command sets the state of the cache allocation policy on a specific + * engine, if supported. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY (0x2080130fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0xF" */ + +/* + * NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAM + * + * These commands access the cache allocation policy on a specific + * client, if supported. + * + * count + * Specifies the number of entries in entry. + * entry + * Specifies an array of allocation policy entries. + * + * NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY + * + * clients + * Specifies the target client. Possible values are defined in + * NV2080_CLIENT_TYPE_*. + * allocPolicy + * Specifies the read/write allocation policy of the cache on the specified + * engine. Possible values are defined in + * NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS and + * NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES. + * + * NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY_SIZE + * + * Specifies the maximum number of allocation policy entries allowed + */ +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY_SIZE 11U + +typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY { + NvU32 client; + NvU32 allocPolicy; +} NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY; + +typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS { + NvU32 count; + NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY entry[NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY_SIZE]; +} NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS; + +/* valid values for allocPolicy */ +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS 0:0 +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_DISABLE (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ENABLE (0x00000001U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ALLOW 1:1 +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ALLOW_NO (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ALLOW_YES (0x00000001U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES 2:2 +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_DISABLE (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ENABLE (0x00000001U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ALLOW 3:3 +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ALLOW_NO (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ALLOW_YES (0x00000001U) + + +/* + * NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2 + * + * This command sets the state of the cache allocation policy on a specific + * engine, if supported. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801318U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x18" */ + +/* + * NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY (deprecated; use NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 instead) + * + * This command gets the state of the cache allocation policy on a specific + * engine, if supported. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY (0x20801312U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x12" */ + +/* + * NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 + * + * This command gets the state of the cache allocation policy on a specific + * engine, if supported. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801319U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x19" */ + + +/* + * NV2080_CTRL_CMD_FB_IS_KIND + * + * This command is used to perform various operations like 'IS_KIND_VALID', + * 'IS_KIND_COMPRESSIBLE'on the kind passed by the caller. The operation to be + * performed should be passed in the 'operation' parameter of + * NV2080_CTRL_FB_IS_KIND_PARAMS, the kind on which the operation is to be + * performed should be passed in the 'kind' parameter. The result of the + * operation (true/false) will be returned in the 'result' parameter. + * + * operation + * Specifies what operation is to be performed on the kind passed by the + * caller. The supported operations are + * NV2080_CTRL_FB_IS_KIND_OPERATION_SUPPORTED + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure is + * supported for this GPU. Returns nonzero value in 'result' parameter + * if the input kind is supported, else returns zero in the result. + * NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure is + * compressible. Returns nonzero value in 'result' parameter if the + * input kind is compressible, else returns zero in the result. + * NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_1 + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure supports + * 1 bit compression. Returns nonzero value in 'result' parameter if + * kind supports 1 bit compression, else returns zero in the result. + * NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_2 + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure supports + * 2 bit compression. Returns nonzero value in 'result' parameter if + * kind supports 1 bit compression, else returns zero in the result. + * NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_4 + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure supports + * 4 bit compression. Returns nonzero value in 'result' parameter if + * kind supports 4 bit compression, else returns zero in the result. + * NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure + * supports ZBC. Returns nonzero value in 'result' parameter if the + * input kind supports ZBC, else returns zero in the result. + * NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_1 + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure + * supports 1 bit ZBC. Returns nonzero value in 'result' parameter if + * the input kind supports 1 bit ZBC, else returns zero in the result. + * NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_2 + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure + * supports 2 bit ZBC. Returns nonzero value in 'result' parameter if + * the input kind supports 2 bit ZBC, else returns zero in the result. + * NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_4 + * This operation checks whether the kind passed in the 'kind' + * parameter of the 'NV2080_CTRL_FB_IS_KIND_PARAMS' structure + * supports 4 bit ZBC. Returns nonzero value in 'result' parameter if + * the input kind supports 4 bit ZBC, else returns zero in the result. + * kind + * Specifies the kind on which the operation is to be carried out. The + * legal range of values for the kind parameter is different on different + * GPUs. For e.g. on Fermi, valid range is 0x00 to 0xfe. Still, some values + * inside this legal range can be invalid i.e. not defined. + * So its always better to first check if a particular kind is supported on + * the current GPU with 'NV2080_CTRL_FB_IS_KIND_SUPPORTED' operation. + * result + * Upon return, this parameter will hold the result (true/false) of the + * operation performed on the kind. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_IS_KIND (0x20801313U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV2080_CTRL_FB_IS_KIND_PARAMS { + NvU32 operation; + NvU32 kind; + NvBool result; +} NV2080_CTRL_FB_IS_KIND_PARAMS; + +/* valid values for operation */ +#define NV2080_CTRL_FB_IS_KIND_OPERATION_SUPPORTED (0x00000000U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE (0x00000001U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_1 (0x00000002U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_2 (0x00000003U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_4 (0x00000004U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC (0x00000005U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_1 (0x00000006U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_2 (0x00000007U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_4 (0x00000008U) + +/** + * NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO + * + * This command returns the state of a cache which all GPU memory accesess go + * through. + * + * powerState + * Returns the power state of the cache. Possible values are defined in + * NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE. + * + * writeMode + * Returns the write mode of the cache. Possible values are defined in + * NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE. + * + * bypassMode + * Returns the bypass mode of the L2 cache. Possible values are defined in + * NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE. + * + * rcmState + * Returns the RCM state of the cache. Possible values are defined in + * NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO (0x20801315U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS { + NvU32 powerState; + NvU32 writeMode; + NvU32 bypassMode; + NvU32 rcmState; +} NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS; + +/* valid values for powerState */ +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_ENABLED (0x00000000U) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_DISABLED (0x00000001U) +/* valid values for writeMode */ +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITETHROUGH (0x00000000U) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITEBACK (0x00000001U) +/* valid values for bypassMode */ +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_DISABLED (0x00000000U) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_ENABLED (0x00000001U) +/* valid values for rcmState */ +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_FULL (0x00000000U) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_TRANSITIONING (0x00000001U) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_REDUCED (0x00000002U) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_ZERO_CACHE (0x00000003U) + +/* + * NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY + * + * These commands access the cache promotion policy on a specific + * engine, if supported by the hardware. + * + * Cache promotion refers to the GPU promoting a memory read to a larger + * size to preemptively fill the cache so future reads to nearby memory + * addresses will hit in the cache. + * + * engine + * Specifies the target engine. Possible values are defined in + * NV2080_ENGINE_TYPE. + * promotionPolicy + * Specifies the promotion policy of the cache on the specified + * engine. Possible values are defined by + * NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_*. These values are in terms + * of the hardware cache line size. + * + */ +typedef struct NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS { + NvU32 engine; + NvU32 promotionPolicy; +} NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS; + +/* valid values for promotionPolicy */ +#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_NONE (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_QUARTER (0x00000001U) +#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_HALF (0x00000002U) +#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_FULL (0x00000003U) + + +/* + * NV2080_CTRL_CMD_FB_SET_GPU_CACHE_PROMOTION_POLICY + * + * This command sets the cache promotion policy on a specific engine, if + * supported by the hardware. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_PROMOTION_POLICY (0x20801316U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x16" */ // Deprecated, removed form RM + + +/* + * NV2080_CTRL_CMD_FB_GET_GPU_CACHE_PROMOTION_POLICY + * + * This command gets the cache promotion policy on a specific engine, if + * supported by the hardware. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_PROMOTION_POLICY (0x20801317U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x17" */ // Deprecated, removed form RM + +/* + * NV2080_CTRL_FB_CMD_GET_FB_REGION_INFO + * + * This command returns the FB memory region characteristics. + * + * numFBRegions + * Number of valid regions returned in fbRegion[] + * fbRegion[].base + * Base address of region. The first valid address in the range + * [base..limit]. + * fbRegion[].limit + * Last/end address of region. The last valid address in the range + * [base..limit]. + * (limit - base + 1) = size of the region + * fbRegion[].reserved + * Amount of memory that RM speculatively needs within the region. A + * client doing its own memory management should leave at least this much + * memory available for RM use. This particularly applies to a driver + * model like LDDM. + * fbRegion[].performance + * Relative performance of this region compared to other regions. + * The definition is vague, and only connotes relative bandwidth or + * performance. The higher the value, the higher the performance. + * fbRegion[].supportCompressed + * TRUE if compressed surfaces/kinds are supported + * FALSE if compressed surfaces/kinds are not allowed to be allocated in + * this region + * fbRegion[].supportISO + * TRUE if ISO surfaces/kinds are supported (Display, cursor, video) + * FALSE if ISO surfaces/kinds are not allowed to be allocated in this + * region + * fbRegion[].bProtected + * TRUE if this region is a protected memory region. If true only + * allocations marked as protected (NVOS32_ALLOC_FLAGS_PROTECTED) can be + * allocated in this region. + * fbRegion[].blackList[] - DEPRECATED: Use supportISO + * TRUE for each NVOS32_TYPE_IMAGE* that is NOT allowed in this region. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO (0x20801320U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES 17U + +typedef NvBool NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES]; + +typedef struct NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO { + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 limit, 8); + NV_DECLARE_ALIGNED(NvU64 reserved, 8); + NvU32 performance; + NvBool supportCompressed; + NvBool supportISO; + NvBool bProtected; + NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG blackList; +} NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO; + +#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES 16U + +#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS { + NvU32 numFBRegions; + NV_DECLARE_ALIGNED(NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO fbRegion[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES], 8); +} NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_OFFLINE_PAGES + * + * This command adds video memory page addresses to the list of offlined + * addresses so that they're not allocated to any client. The newly offlined + * addresses take effect after a reboot. + * + * offlined + * This input parameter is an array of NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO + * structures, containing the video memory physical page numbers that + * are to be blacklisted. This array can hold a maximum of NV2080_CTRL_FB_ + * BLACKLIST_PAGES_MAX_PAGES address pairs. Valid entries are adjacent. + * pageSize + * This input parameter contains the size of the page that is to be + * blacklisted. + * validEntries + * This input parameter specifies the number of valid entries in the + * offlined array. + * numPagesAdded + * This output parameter specifies how many of the validEntries were + * actually offlined. If numPagesAdded < validEntries, it + * means that only addresses from offlined[0] to offlined[numPagesAdded - 1] + * were added to the list of offlined addresses. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_OFFLINE_PAGES (0x20801321U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES (0x00000040U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_INVALID_ADDRESS (0xffffffffffffffffULL) +#define NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_4K (0x00000000U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_64K (0x00000001U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_128K (0x00000002U) + +/* + * NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO + * + * pageAddressWithEccOn + * Address of the memory page retired when ECC is enabled on the board. + * pageAddressWithEccOff + * Address of the memory page retired when ECC is disabled on the board. + * rbcAddress + * Row/Bank/Column Address of the faulty memory which caused the page to + * be retired + * source + * The reason for the page to be retired + * status + * Non-exceptional reasons for a page retirement failure + * NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_OK + * No error + * NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_PENDING_RETIREMENT + * The given address is already pending retirement or has + * been retired during the current driver run. The page + * will be offlined during the next driver run. + * NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_BLACKLISTING_FAILED + * The given page was retired on a previous driver run, + * so it should not be accessible unless offlining failed. + * Failing to offline a page is strongly indicative of a + * driver offlining bug. + * NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_TABLE_FULL + * The PBL is full and no more pages can be retired + * NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_INTERNAL_ERROR + * Internal driver error + * + */ + + + +typedef struct NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO { + NV_DECLARE_ALIGNED(NvU64 pageAddressWithEccOn, 8); + NV_DECLARE_ALIGNED(NvU64 pageAddressWithEccOff, 8); + NvU32 rbcAddress; + NvU32 source; + NvU32 status; + NvU32 timestamp; +} NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO; + +/* valid values for source */ +#define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE (0x00000002U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE (0x00000004U) + + + +/* valid values for status */ +#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_OK (0x00000000U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_PENDING_RETIREMENT (0x00000001U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_BLACKLISTING_FAILED (0x00000002U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_TABLE_FULL (0x00000003U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_INTERNAL_ERROR (0x00000004U) + +/* deprecated */ +#define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_MULTIPLE_SBE NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE +#define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DBE NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE + + +#define NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS_MESSAGE_ID (0x21U) + +typedef struct NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO offlined[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES], 8); + NvU32 pageSize; + NvU32 validEntries; + NvU32 numPagesAdded; +} NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_GET_OFFLINED_PAGES + * + * This command returns the list of video memory page addresses in the + * Inforom's blacklist. + * + * offlined + * This output parameter is an array of NV2080_CTRL_FB_BLACKLIST_ADDRESS_ + * INFO structures, containing the video memory physical page numbers that + * are blacklisted. This array can hold a maximum of NV2080_CTRL_FB_ + * BLACKLIST_PAGES_MAX_PAGES address pairs. Valid entries are adjacent. + * The array also contains the Row/Bank/Column Address and source. + * validEntries + * This output parameter specifies the number of valid entries in the + * offlined array. + * bRetirementPending (DEPRECATED, use retirementPending instead) + * This output parameter returns if any pages on the list are pending + * retirement. + * retirementPending + * Communicates to the caller whether retirement updates are pending and the + * reason for the updates. Possible fields are: + * NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_*: + * NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE: + * Indicates whether pages are pending retirement due to SBE. + * NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE: + * Indicates whether pages are pending retirement due to DBE. Driver + * reload needed to retire bad memory pages and allow compute app runs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + + + +#define NV2080_CTRL_CMD_FB_GET_OFFLINED_PAGES (0x20801322U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE 0:0 +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_FALSE 0U +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_TRUE 1U +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE 1:1 +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_FALSE 0U +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_TRUE 1U + + + +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO offlined[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES], 8); + NvU32 validEntries; + NvBool bRetirementPending; + NvU8 retirementPending; +} NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_QUERY_ACR_REGION + * + * This control command is used to query the secured region allocated + * + * queryType + * NV2080_CTRL_CMD_FB_ACR_QUERY_GET_REGION_STATUS: Provides the alloc + * status and ACR region ID. + * NV2080_CTRL_CMD_FB_QUERY_MAP_REGION : Maps the region on BAR1 + * it returns the "pCpuAddr" and pPriv to user. + * NV2080_CTRL_CMD_FB_QUERY_UNMAP_REGION: Unmaps the mapped region. + * it takes the pPriv as input + * + * clientReq : struct ACR_REQUEST_PARAMS + * It is used to find the allocated ACR region for that client + * clientId : ACR Client ID + * reqReadMask : read mask of ACR region + * reqWriteMask : Write mask of ACR region + * regionSize : ACR region Size + * + * clientReqStatus : struct ACR_STATUS_PARAMS + * This struct is stores the output of requested ACR region. + * allocStatus : Allocated Status of ACR region + * regionId : ACR region ID + * physicalAddress : Physical address on FB + * + * + * NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE + * NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_NONE : Control command executed successfully + * NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_INVALID_CLIENT_REQUEST : Please check the parameter + * for ACR client request + * NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_FAILED_TO_MAP_ON_BAR1 : RM Fails to map ACR region + * on BAR1 + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED +*/ +#define NV2080_CTRL_CMD_FB_QUERY_ACR_REGION (0x20801325U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS_MESSAGE_ID" */ + +// +// We can create an ACR region by using RMCreateAcrRegion[1|2] regkey or mods -acr[1|2]_size +// Client ID for such region is 2 in RM. +// +#define NV2080_CTRL_CMD_FB_ACR_CLIENT_ID 2U + +typedef enum NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE { + NV2080_CTRL_CMD_FB_ACR_QUERY_GET_CLIENT_REGION_STATUS = 0, + NV2080_CTRL_CMD_FB_ACR_QUERY_GET_REGION_PROPERTY = 1, + NV2080_CTRL_CMD_FB_ACR_QUERY_GET_FALCON_STATUS = 2, +} NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE; + +typedef enum NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE { + NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_NONE = 0, + NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_INVALID_CLIENT_REQUEST = 1, +} NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE; + +typedef struct ACR_REQUEST_PARAMS { + NvU32 clientId; + NvU32 reqReadMask; + NvU32 reqWriteMask; + NvU32 regionSize; +} ACR_REQUEST_PARAMS; + +typedef struct ACR_REGION_ID_PROP { + NvU32 regionId; + NvU32 readMask; + NvU32 writeMask; + NvU32 regionSize; + NvU32 clientMask; + NV_DECLARE_ALIGNED(NvU64 physicalAddress, 8); +} ACR_REGION_ID_PROP; + +typedef struct ACR_STATUS_PARAMS { + NvU32 allocStatus; + NvU32 regionId; + NV_DECLARE_ALIGNED(NvU64 physicalAddress, 8); +} ACR_STATUS_PARAMS; + +typedef struct ACR_REGION_HANDLE { + NvHandle hClient; + NvHandle hParent; + NvHandle hMemory; + NvU32 hClass; + NvHandle hDevice; +} ACR_REGION_HANDLE; + +typedef struct ACR_FALCON_LS_STATUS { + NvU16 falconId; + NvBool bIsInLs; +} ACR_FALCON_LS_STATUS; + +#define NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS_MESSAGE_ID (0x25U) + +typedef struct NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS { + NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE queryType; + NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE errorCode; + NV_DECLARE_ALIGNED(ACR_REGION_ID_PROP acrRegionIdProp, 8); + ACR_REQUEST_PARAMS clientReq; + NV_DECLARE_ALIGNED(ACR_STATUS_PARAMS clientReqStatus, 8); + ACR_REGION_HANDLE handle; + ACR_FALCON_LS_STATUS falconStatus; +} NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_CLEAR_OFFLINED_PAGES + * + * This command clears offlined video memory page addresses from the Inforom. + * + * sourceMask + * This is a bit mask of NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE. Pages + * offlined from the specified sources will be cleared/removed from the + * Inforom PBL object denylist. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_CLEAR_OFFLINED_PAGES (0x20801326U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS_MESSAGE_ID (0x26U) + +typedef struct NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS { + NvU32 sourceMask; +} NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO + * + * Gets pointer to then object of class CompBitCopy, which is used for swizzling + * compression bits in the compression backing store. The caller is expected to + * have the appropriate headers for class CompBitCopy. Also retrieves values of some + * parameters needed to call the compbit swizzling method. + * + * @params[out] void *pCompBitCopyObj + * Opaque pointer to object of class CompBitCopy + * @params[out] void *pSwizzleParams + * Opaque pointer to values needed to call the compbit + * swizzle method. + * + * Possible status values returned are: + * NV_OK NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO (0x20801327U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS_MESSAGE_ID (0x27U) + +typedef struct NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pCompBitCopyObj, 8); + NV_DECLARE_ALIGNED(NvP64 pSwizzleParams, 8); +} NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_GET_LTC_INFO_FOR_FBP + * + * Gets the count and mask of LTCs for a given FBP. + * + * fbpIndex + * The physical index of the FBP to get LTC info for. + * ltcMask + * The mask of active LTCs for the given FBP. + * ltcCount + * The count of active LTCs for the given FBP. + * ltsMask + * The mask of active LTSs for the given FBP + * ltsCount + * The count of active LTSs for the given FBP + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_GET_LTC_INFO_FOR_FBP (0x20801328U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_MESSAGE_ID (0x28U) + +typedef struct NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS { + NvU8 fbpIndex; + NvU32 ltcMask; + NvU32 ltcCount; + NvU32 ltsMask; + NvU32 ltsCount; +} NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS; + + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT < Deprecated > + * + * "set the context" for following CompBitCopy member functions. + * These are the CompBitCopy member variables that remain connstant + * over multiple CompBitCopy member function calls, yet stay the same + * throughout a single surface eviction. + * + * @params[in] UINT64 backingStorePA; + * Physical Address of the Backing Store + * @params[in] UINT08 *backingStoreVA; + * Virtual Address of the Backing Store + * @params[in] UINT64 backingStoreChunkPA; + * Physical Address of the "Chunk Buffer" + * @params[in] UINT08 *backingStoreChunkVA; + * Virtual Address of the "Chunk Buffer" + * @params[in] UINT32 backingStoreChunkSize; + * Size of the "Chunk Buffer" + * @params[in] UINT08 *cacheWriteBitMap; + * Pointer to the bitmap which parts of the + * "Chunk" was updated. + * @params[in] bool backingStoreChunkOverfetch; + * Overfetch factor. + * @params[in] UINT32 PageSizeSrc; + * Page size of Source Surface. + * @params[in] UINT32 PageSizeDest; + * page size of Destination Surface. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT (0x20801329U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x29" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS { + NvU32 CBCBaseAddress; + NV_DECLARE_ALIGNED(NvU64 backingStorePA, 8); + NV_DECLARE_ALIGNED(NvU8 *backingStoreVA, 8); + NV_DECLARE_ALIGNED(NvU64 backingStoreChunkPA, 8); + NV_DECLARE_ALIGNED(NvU8 *backingStoreChunkVA, 8); + NvU32 backingStoreChunkSize; + NV_DECLARE_ALIGNED(NvU8 *cacheWriteBitMap, 8); + NvBool backingStoreChunkOverfetch; + NvU32 PageSizeSrc; + NvU32 PageSizeDest; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS < Deprecated > + * + * Retrieves the Compression and Fast Clear bits for the surface+offset given. + * + * @params[out] NvU32 *fcbits; + * Fast Clear Bits returned + * @params[out] NvU32 *compbits; + * Compression Bits returned + * @params[in] NvU64 dataPhysicalStart; + * Start Address of Data + * @params[in] NvU64 surfaceOffset; + * Offset in the surface + * @params[in] NvU32 comptagLine; + * Compression Tag Number + * @params[in] NvBool upper64KBCompbitSel; + * Selects Upper or Lower 64K + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTEDD + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS (0x2080132aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2A" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS { + NV_DECLARE_ALIGNED(NvU32 *fcbits, 8); + NV_DECLARE_ALIGNED(NvU32 *compbits, 8); + NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8); + NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8); + NvU32 comptagLine; + NvBool upper64KBCompbitSel; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS < Deprecated > + * + * Sets the Compression and Fast Clear bits for the surface+offset given. + * + * @params[in] NvU32 fcbits; + * Fast Clear Bits to write. + * @params[in] NvU32 compbits; + * Compression Bits to write + * @params[in] NvBool writeFc; + * Indicates if Fast Clear Bits should be written + * @params[in] NvU64 dataPhysicalStart; + * Start Address of Data + * @params[in] NvU64 surfaceOffset; + * Offset in the surface + * @params[in] NvU32 comptagLine; + * Compression Tag Number + * @params[in] NvBool upper64KBCompbitSel; + * Selects Upper or Lower 64K + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS (0x2080132bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2B" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS { + NvU32 fcbits; + NvU32 compbits; + NvBool writeFc; + NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8); + NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8); + NvU32 comptagLine; + NvBool upper64KBCompbitSel; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB < Deprecated > + * + * Read 64KB chunk of CompBits + * + * @params[in] NvU64 SrcDataPhysicalStart; + * Start Address of Data + * @params[in] NvU32 SrcComptagLine; + * Compression Tag Number + * @params[in] NvU32 page64KB; + * Which 64K block to read from. + * @params[out] NvU32 *compbitBuffer; + * Buffer for CompBits read, + * @params[in] NvBool upper64KBCompbitSel; + * Selects Upper or Lower 64K + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB (0x2080132cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2C" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS { + NV_DECLARE_ALIGNED(NvU64 SrcDataPhysicalStart, 8); + NvU32 SrcComptagLine; + NvU32 page64KB; + NV_DECLARE_ALIGNED(NvU32 *compbitBuffer, 8); + NvBool upper64KBCompbitSel; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB < Deprecated > + * + * Write 64K chunk of COmpBits. + * + * @params[in] NvU64 SrcDataPhysicalStart; + * Start Address of Data + * @params[in] NvU32 SrcComptagLine; + * Compression Tag Number + * @params[in] NvU32 page64KB; + * Which 64K block to read from. + * @params[in] NvU32 *compbitBuffer; + * Buffer for CompBits to write. + * @params[in] NvBool upper64KBCompbitSel + * Selects Upper or Lower 64K + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB (0x2080132dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2D" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS { + NV_DECLARE_ALIGNED(NvU64 DstDataPhysicalStart, 8); + NvU32 DstComptagLine; + NvU32 page64KB; + NV_DECLARE_ALIGNED(NvU32 *compbitBuffer, 8); + NvBool upper64KBCompbitSel; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS < Deprecated > + * + * The PS (Performance Path, or Optimized path, or Per Slice version) + * of PutCompBits. + * + * @params[out] NvU32 *fcbits; + * Buffer to receive Fast Clear Bits. + * @params[out] NvU32 *compbits; + * Buffer to receive Compression Bits. + * @params[out] NvU32 *compCacheLine; + * Buffer to receive Comp Cache Line data. + * @params[in] NvU64 dataPhysicalStart; + * Start Address of Data + * @params[in] NvU64 surfaceOffset; + * Offset in the surface + * @params[in] NvU32 comptagLine; + * Compression Tag Line Number + * @params[in] NvU32 ROPTile_offset; + * Offset in the surface of the ROP tile. + * @params[in] NvBool upper64KBCompbitSel; + * Selects Upper or Lower 64K + * @params[in] NvBool getFcBits; + * Indicates if fast clear bits should be returned. + * @params[in] NvP64 derivedParams + * Actually a CompBitDerivedParams structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS (0x2080132eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2E" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS_PARAMS { + NV_DECLARE_ALIGNED(NvU32 *fcbits, 8); + NV_DECLARE_ALIGNED(NvU32 *compbits, 8); + NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8); + NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8); + NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8); + NvU32 comptagLine; + NvU32 ROPTile_offset; + NvBool upper64KBCompbitSel; + NvBool getFcBits; + NV_DECLARE_ALIGNED(NvP64 derivedParams, 8); +} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS < Deprecated > + * + * The PS (Performance Path, or Optimized path, or Per Slice version) + * of GetCompBits. + * + * @params[in] NvU32 fcbits; + * Buffer with Fast Clear Bits to write. + * @params[in] NvU32 compbits; + * Buffer to receive Compression Bits. + * @params[in] NvBool writeFc + * Indicates of Fast Clear Bits should be written. + * @params[in] NvU32 *compCacheLine; + * Buffer to receive Comp Cache Line data. + * @params[in] NvU64 dataPhysicalStart; + * Start Address of Data + * @params[in] NvU64 surfaceOffset; + * Offset in the surface + * @params[in] NvU32 comptagLine; + * Compression Tag Line Number + * @params[in] NvU32 ROPTile_offset; + * Offset in the surface of the ROP tile. + * @params[in] NvBool upper64KBCompbitSel; + * Selects Upper or Lower 64K + * @params[in] NvP64 derivedParams + * Actually a CompBitDerivedParams structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS (0x2080132fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2F" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS_PARAMS { + NvU32 fcbits; + NvU32 compbits; + NvBool writeFc; + NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8); + NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8); + NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8); + NvU32 comptagLine; + NvU32 ROPTile_offset; + NvBool upper64KBCompbitSel; + NV_DECLARE_ALIGNED(NvP64 derivedParams, 8); +} NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS < Deprecated > + * + * The PS (Performance Path, or Optimized path, or Per Slice version) + * of ReadCompCacheLine. + * + * @paramsNvU32 *compCacheLine; + * Buffer for Comp Cache Line Read + * @paramsNvU32 comptagLine; + * Comp Tag Line Number to read + * @paramsNvU32 partition; + * FB Partition of the desired Comp Cache Line + * @paramsNvU32 slice; + * Slice of the desired Comp Cache Line + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS (0x20801330U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x30" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS_PARAMS { + NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8); + NvU32 comptagLine; + NvU32 partition; + NvU32 slice; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS < Deprecated > + * + * The PS (Performance Path, or Optimized path, or Per Slice version) + * of WriteCompCacheLine. + * + * @params[in] NvU32 *compCacheLine; + * Buffer for Comp Cache Line to Write + * @params[in] NvU32 comptagLine; + * Comp Tag Line Number to Write + * @params[in] NvU32 partition; + * FB Partition of the desired Comp Cache Line + * @params[in] NvU32 slice; + * Slice of the desired Comp Cache Line + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS (0x20801331U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x31" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS_PARAMS { + NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8); + NvU32 comptagLine; + NvU32 partition; + NvU32 slice; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS < Deprecated > + * + * Used by PS (Performance Path, or Optimized path, or Per Slice version) + * to retrieve upper and lower Address of the CompCacheLine. + * + * @params[out] NvU64 *minCPUAddress; + * Minimum (lower bound) of the ComCacheLine. + * @params[out] NvU64 *minCPUAddress; + * Minimum (lower bound) of the ComCacheLine. + * @params[in] NvU32 comptagLine; + * CompTagLine to fetch the bounds of. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS (0x20801332U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x32" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 *minCPUAddress, 8); + NV_DECLARE_ALIGNED(NvU64 *maxCPUAddress, 8); + NvU32 comptagLine; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET < Deprecated > + * + * Used by PS (Performance Path, or Optimized path, or Per Slice version) + * to retrieve partition, slice and ROP Tile Offset of the passed in + * surface location. + * + * @params[out] NvU64 *part; + * Partition in which the target part of the surface resides. + * @params[out] NvU64 *slice; + * Slice in which the target part of the surface resides. + * @params[out] NvU64 *ropTileoffset; + * Offset to the start of the ROP Tile in which the target part of + * the surface resides. + * @params[in] NvU64 *dataPhysicalStart; + * Start address of data for which part/slice/offset is desired. + * @params[in] NvU64 surfaceOffset; + * Byte offset of data for which part/slice/offset is desired. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET (0x20801333U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x33" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET_PARAMS { + NV_DECLARE_ALIGNED(NvU64 *part, 8); + NV_DECLARE_ALIGNED(NvU64 *slice, 8); + NV_DECLARE_ALIGNED(NvU64 *ropTileoffset, 8); + NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8); + NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8); +} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS < Deprecated > + * + * Used by PS (Performance Path, or Optimized path, or Per Slice version) + * to create a CompBitCopy::CompBitDerivedParams object + * + * @params[out] NvP64 derivedParams + * Actually a CompBitDerivedParams structure. + * @params[in] NvU32 comptagLine; + * Compression Tag Line Number + * @params[in] NvU32 ROPTile_offset; + * Offset in the surface of the ROP tile. + * @params[in] NvBool upper64KBCompbitSel; + * Selects Upper or Lower 64K + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS (0x20801334U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x34" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS_PARAMS { + NV_DECLARE_ALIGNED(NvP64 derivedParams, 8); + NvU32 comptagLine; + NvBool upper64KBCompbitSel; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1 < Deprecated > + * + * Used by MODS (and possibly other clients) to have compbit code write + * write directly to BAR1, rather than a intermediate buffer. + * + * @params[in] NvBool bForceBar1; + * Enables or disables direct writes to BAR1. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1 (0x20801335U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x35" */ + +typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS { + NvBool bForceBar1; +} NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_GET_AMAP_CONF + * + * Fills in fields of a structure of class ConfParamsV1, which is used for + * swizzling compression bits in the compression backing store. + * The caller is expected to have the appropriate headers for class ConfParamsV1. + * + * @params[in|out] void *pAmapConfParms + * Opaque pointer to structure of values for ConfParamsV1 + * @params[in|out] void *pCbcSwizzleParms + * Opaque pointer to structure of values for CbcSwizzleParamsV1 + * + * Possible status values returned are: + * NV_OK NV_ERR_NOT_SUPPORTED + * + * pCbcSwizzleParams will be filled in with certain parameters from + * @CbcSwizzleParamsV1. However, the caller is responsible for making sure + * all parameters are filled in before using it. + */ +#define NV2080_CTRL_CMD_FB_GET_AMAP_CONF (0x20801336U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS_MESSAGE_ID (0x36U) + +typedef struct NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pAmapConfParams, 8); + NV_DECLARE_ALIGNED(NvP64 pCbcSwizzleParams, 8); +} NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_CBC_OP + * + * Provides a way for clients to request a CBC Operation + * + * @params[in] CTRL_CMD_FB_CBC_OP fbCBCOp + * CBC Operation requested. + * Valid Values: + * CTRL_CMD_FB_CBC_OP_CLEAN + * CTRL_CMD_FB_CBC_OP_INVALIDATE + * + * Possible status values returned are: + * NV_OK NV_ERR_NOT_SUPPORTED NV_ERR_INVALID_ARGUMENT NV_ERR_TIMEOUT + */ +#define NV2080_CTRL_CMD_FB_CBC_OP (0x20801337U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_CBC_OP_PARAMS_MESSAGE_ID" */ + +/*! + * Permitted CBC Operations + */ +typedef enum CTRL_CMD_FB_CBC_OP { + CTRL_CMD_FB_CBC_OP_CLEAN = 0, + CTRL_CMD_FB_CBC_OP_INVALIDATE = 1, +} CTRL_CMD_FB_CBC_OP; + +#define NV2080_CTRL_CMD_FB_CBC_OP_PARAMS_MESSAGE_ID (0x37U) + +typedef struct NV2080_CTRL_CMD_FB_CBC_OP_PARAMS { + CTRL_CMD_FB_CBC_OP fbCBCOp; +} NV2080_CTRL_CMD_FB_CBC_OP_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_GET_CTAGS_FOR_CBC_EVICTION + * + * The call will fetch the compression tags reserved for CBC eviction. + * + * Each comptag will correspond to a unique compression cacheline. The usage of + * these comptags is to evict the CBC by making accesses to a dummy compressed page, + * thereby evicting each CBC line. + * + * @param [in][out] NvU32 pCompTags + * Array of reserved compression tags of size @ref NV2080_MAX_CTAGS_FOR_CBC_EVICTION + * @param [out] numCompTags + * Number of entries returned in @ref pCompTags + * + * @returns + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_OUT_OF_RANGE + * NV_ERR_INVALID_PARAMETER + */ +#define NV2080_CTRL_CMD_FB_GET_CTAGS_FOR_CBC_EVICTION (0x20801338U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS_MESSAGE_ID" */ + +/*! + * Max size of @ref NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS::pCompTags + * Arbitrary, but sufficiently large number. Should be checked against CBC size. + */ +#define NV2080_MAX_CTAGS_FOR_CBC_EVICTION 0x7FU + + +#define NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS_MESSAGE_ID (0x38U) + +typedef struct NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS { + NvU32 pCompTags[NV2080_MAX_CTAGS_FOR_CBC_EVICTION]; + NvU32 numCompTags; +} NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE + * + * This Call will allocate compression tag + * + * @params[in] NvU32 attr + * Stores the information: + * 1. NVOS32_ATTR_COMPR_REQUIRED or not + * 2. NVOS32_ATTR_PAGE_SIZE + * @params[in] NvU32 attr2 + * Determine whether to allocate + * an entire cache line or allocate by size + * @params[in] NvU32 size + * Specify the size of allocation, in pages not bytes + * @params[in] NvU32 ctagOffset + * Determine the offset usage of the allocation + * @params[out] NvU32 hwResId + * Stores the result of the allocation + * @params[out] NvU32 RetcompTagLineMin + * The resulting min Ctag Number from the allocation + * @params[out] NvU32 RetcompTagLineMax + * The resulting max Ctag Number from the allocation + * @returns + * NV_OK + * NV_ERR_INSUFFICIENT_RESOURCES + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ + +#define NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE (0x20801339U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS_MESSAGE_ID (0x39U) + +typedef struct NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS { + NvU32 attr; + NvU32 attr2; + NvU32 size; + NvU32 ctagOffset; + NvU32 hwResId; + NvU32 retCompTagLineMin; + NvU32 retCompTagLineMax; +} NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_FREE_TILE + * + * This control call is used to release tile back to the free pool + * + * @params[in] NvU32 hwResId + * Stores the information of a previous allocation + * @returns + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ + +#define NV2080_CTRL_CMD_FB_FREE_TILE (0x2080133aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS_MESSAGE_ID (0x3AU) + +typedef struct NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS { + NvU32 hwResId; +} NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS; + + +/* + * NV2080_CTRL_CMD_FB_SETUP_VPR_REGION + * + * This control command is used to request vpr region setup + * + * requestType + * NV2080_CTRL_CMD_FB_SET_VPR: Request to setup VPR + * + * requestParams : struct VPR_REQUEST_PARAMS + * It contains the VPR region request details like, + * startAddr : FB offset from which we need to setup VPR + * size : required size of the region + * + * statusParams : struct VPR_STATUS_PARAMS + * This struct stores the output of requested VPR region + * status : Whether the request was successful + * + * NV2080_CTRL_CMD_FB_VPR_ERROR_CODE : + * NV2080_CTRL_CMD_FB_VPR_ERROR_GENERIC : Some unknown error occurred + * NV2080_CTRL_CMD_FB_VPR_ERROR_INVALID_CLIENT_REQUEST : Request was invalid + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_SETUP_VPR_REGION (0x2080133bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE { + NV2080_CTRL_CMD_FB_SET_VPR = 0, +} NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE; + +typedef enum NV2080_CTRL_CMD_FB_VPR_ERROR_CODE { + NV2080_CTRL_CMD_FB_VPR_ERROR_GENERIC = 0, + NV2080_CTRL_CMD_FB_VPR_ERROR_INVALID_CLIENT_REQUEST = 1, +} NV2080_CTRL_CMD_FB_VPR_ERROR_CODE; + +typedef struct VPR_REQUEST_PARAMS { + NvU32 startAddr; + NvU32 size; +} VPR_REQUEST_PARAMS; + +typedef struct VPR_STATUS_PARAMS { + NvU32 status; +} VPR_STATUS_PARAMS; + +#define NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS_MESSAGE_ID (0x3BU) + +typedef struct NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS { + NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE requestType; + VPR_REQUEST_PARAMS requestParams; + VPR_STATUS_PARAMS statusParams; +} NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS; +typedef struct NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS *PNV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_GET_CLI_MANAGED_OFFLINED_PAGES + * + * This command returns the list of offlined video memory page addresses in the + * region managed by Client + * + * offlinedPages + * This output parameter is an array of video memory physical page numbers that + * are offlined. This array can hold a maximum of NV2080_CTRL_FB_ + * OFFLINED_PAGES_MAX_PAGES addresses. + * pageSize + * This output parameter contains the size of the page that is offlined. + * validEntries + * This output parameter specifies the number of valid entries in the + * offlined array. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_FB_GET_CLI_MANAGED_OFFLINED_PAGES (0x2080133cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS_MESSAGE_ID (0x3CU) + +typedef struct NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS { + NvU32 offlinedPages[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES]; // A 32B can hold enough. + NvU32 pageSize; + NvU32 validEntries; +} NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO + * + * This command returns parameters required to initialize compbit copy object + * used by address mapping library + * + * defaultPageSize + * Page size used by @ref CompBitCopy methods + * comptagsPerCacheLine + * Number of compression tags in a single compression cache line. + * unpackedComptagLinesPerCacheLine; + * From hw (not adjusted for CompBits code) Number of compression tags + * in a single compression cache line. + * compCacheLineSizePerLTC; + * Size of compression cache line per L2 slice. Size in Bytes. + * unpackedCompCacheLineSizePerLTC; + * From hw (not adjusted for CompBits code) size of compression + * cache line per L2 slice. Size in Bytes + * slicesPerLTC; + * Number of L2 slices per L2 cache. + * numActiveLTCs; + * Number of active L2 caches. (Not floorswept) + * familyName; + * Family name for the GPU. + * chipName; + * Chip name for the GPU. + * bitsPerRAMEntry; + * Bits per RAM entry. (Need better doc) + * ramBankWidth; + * Width of RAM bank. (Need better doc) + * bitsPerComptagLine; + * Number of bits per compression tag line. + * ramEntriesPerCompCacheLine; + * Number of RAM entries spanned by 1 compression cache line. + * comptagLineSize; + * Size of compression tag line, in Bytes. + * + * Possible status values returned are: + * NV_OK + */ + +#define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO (0x2080133dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS_MESSAGE_ID (0x3DU) + +typedef struct NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS { + NvU32 defaultPageSize; + NvU32 comptagsPerCacheLine; + NvU32 unpackedComptagLinesPerCacheLine; + NvU32 compCacheLineSizePerLTC; + NvU32 unpackedCompCacheLineSizePerLTC; + NvU32 slicesPerLTC; + NvU32 numActiveLTCs; + NvU32 familyName; + NvU32 chipName; + NvU32 bitsPerRAMEntry; + NvU32 ramBankWidth; + NvU32 bitsPerComptagLine; + NvU32 ramEntriesPerCompCacheLine; + NvU32 comptagLineSize; +} NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_SET_RRD + * + * Sets the row-to-row delay on the GPU's FB + * + * Possible status values returned are: + * NV_OK + * Any error code + */ +#define NV2080_CTRL_CMD_FB_SET_RRD (0x2080133eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_RRD_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_SET_RRD_RESET_VALUE (~((NvU32)0)) +#define NV2080_CTRL_FB_SET_RRD_PARAMS_MESSAGE_ID (0x3EU) + +typedef struct NV2080_CTRL_FB_SET_RRD_PARAMS { + NvU32 rrd; +} NV2080_CTRL_FB_SET_RRD_PARAMS; + +/* + * NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS + * + * This is not a control call of it's own, but there are common definitions for + * the two NV2080_CTRL_CMD_FB_SET_READ/WRITE_LIMIT control calls. + */ +typedef struct NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS { + NvU8 limit; +} NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS; +#define NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE (0xffU) + +/* + * NV2080_CTRL_CMD_FB_SET_READ_LIMIT + * + * Sets the READ_LIMIT to be used in the NV_PFB_FBPA_DIR_ARB_CFG0 register + * + * limit + * The limit value to use + * + * Possible status values returned are: + * NV_OK + * Any error code + */ +#define NV2080_CTRL_CMD_FB_SET_READ_LIMIT (0x2080133fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_SET_READ_LIMIT_RESET_VALUE NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE +#define NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS_MESSAGE_ID (0x3FU) + +typedef NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_SET_WRITE_LIMIT + * + * Sets the WRITE_LIMIT to be used in the NV_PFB_FBPA_DIR_ARB_CFG0 register + * + * limit + * The limit value to us + * + * Possible status values returned are: + * NV_OK + * Any error code + */ +#define NV2080_CTRL_CMD_FB_SET_WRITE_LIMIT (0x20801340U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_SET_WRITE_LIMIT_RESET_VALUE NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE +#define NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS_MESSAGE_ID (0x40U) + +typedef NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_PATCH_PBR_FOR_MINING + * + * Patches some VBIOS values related to PBR to better suit mining applications + * + * bEnable + * Set the mining-specific values or reset to the original values + * + * Possible status values returned are: + * NV_OK + * Any error code + */ +#define NV2080_CTRL_CMD_FB_PATCH_PBR_FOR_MINING (0x20801341U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS_MESSAGE_ID (0x41U) + +typedef struct NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS { + NvBool bEnable; +} NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT + * + * Get memory alignment. Replacement for NVOS32_FUNCTION_GET_MEM_ALIGNMENT + */ +#define NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT (0x20801342U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS (4U) +#define NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID (0x42U) + +typedef struct NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS { + NvU32 alignType; // Input + NvU32 alignAttr; + NvU32 alignInputFlags; + NvU32 alignHead; + NV_DECLARE_ALIGNED(NvU64 alignSize, 8); + NvU32 alignHeight; + NvU32 alignWidth; + NvU32 alignPitch; + NvU32 alignPad; + NvU32 alignMask; + NvU32 alignOutputFlags[NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS]; + NvU32 alignBank[NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS]; + NvU32 alignKind; + NvU32 alignAdjust; // Output -- If non-zero the amount we need to adjust the offset + NvU32 alignAttr2; +} NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_GET_CBC_BASEADDR + * + * Get the CBC Base physical address + * This control call is required by error containment tests + * NV2080_CTRL_CMD_FB_GET_AMAP_CONF can also return CBC base address + * but it requires kernel privilege, and it not callalble from SRT test + * + * @params[out] NvU64 cbcBaseAddr + * Base physical address for CBC data. + * + * Possible status values returned are: + * NV_OK NV_ERR_NOT_SUPPORTED + * + */ +#define NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR (0x20801343U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS_MESSAGE_ID (0x43U) + +typedef struct NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS { + NvU32 cbcBaseAddress; + NvU32 compCacheLineSize; + NV_DECLARE_ALIGNED(NvU64 backingStoreStartPA, 8); + NV_DECLARE_ALIGNED(NvU64 backingStoreAllocPA, 8); + NvU32 backingStoreChunkOverfetch; +} NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS; + +#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING 0:0 +#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE 0U +#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE 1U + + + +typedef struct NV2080_CTRL_FB_REMAP_ENTRY { + NvU32 remapRegVal; + NvU32 timestamp; + NvU8 fbpa; + NvU8 sublocation; + NvU8 source; + NvU8 flags; +} NV2080_CTRL_FB_REMAP_ENTRY; + +/* valid values for source */ + + +#define NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_SBE_FIELD (0x00000002U) +#define NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_DBE_FIELD (0x00000003U) + +#define NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS (0x00000200U) + +/* + * NV2080_CTRL_CMD_FB_GET_REMAPPED_ROWS + * + * This command returns the list of remapped rows stored in the Inforom. + * + * entryCount + * This output parameter specifies the number of remapped rows + * flags + * This output parameter contains info on whether or not there are pending + * remappings and whether or not a remapping failed + * entries + * This output parameter is an array of NV2080_CTRL_FB_REMAP_ENTRY + * containing inforomation on the remapping that occurred. This array can + * hold a maximum of NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_POINTER + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_GET_REMAPPED_ROWS (0x20801344U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING \ + NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING +#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_FALSE NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE +#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_TRUE NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE +#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE 1:1 +#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_FALSE 0U +#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_TRUE 1U + +#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS_MESSAGE_ID (0x44U) + +typedef struct NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS { + NvU32 entryCount; + NvU8 flags; + NV2080_CTRL_FB_REMAP_ENTRY entries[NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS]; +} NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS; + +// Max size of the queryParams in Bytes, so that the NV2080_CTRL_FB_FS_INFO_QUERY struct is still 32B +#define NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE 24U + +/*! + * Structure holding the out params for NV2080_CTRL_FB_FS_INFO_INVALID_QUERY. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS { + // Unused param, will ensure the size of NV2080_CTRL_FB_FS_INFO_QUERY struct to be 32B + NvU8 data[NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE]; +} NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_FBP_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS { + /*! + * [IN]: swizzId + * PartitionID associated with a created smc partition. Currently used only for a + * device monitoring client to get the physical values of the FB. The client needs to pass + * 'NV2080_CTRL_GPU_PARTITION_ID_INVALID' explicitly if it wants RM to ignore the swizzId. + * RM will consider this request similar to a legacy case. + * The client's subscription is used only as a capability check and not as an input swizzId. + */ + NvU32 swizzId; + /*! + * [OUT]: physical/local fbp mask. + */ + NV_DECLARE_ALIGNED(NvU64 fbpEnMask, 8); +} NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_LTC_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS { + /*! + * [IN]: physical/local FB partition index. + */ + NvU32 fbpIndex; + /*! + * [OUT]: physical/local ltc mask. + */ + NvU32 ltcEnMask; +} NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_LTS_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS { + /*! + * [IN]: physical/local FB partition index. + */ + NvU32 fbpIndex; + /*! + * [OUT]: physical/local lts mask. + * Note that lts bits are flattened out for all ltc with in a fbp. + */ + NvU32 ltsEnMask; +} NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_FBPA_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS { + /*! + * [IN]: physical/local FB partition index. + */ + NvU32 fbpIndex; + /*! + * [OUT]: physical/local FBPA mask. + */ + NvU32 fbpaEnMask; +} NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS { + /*! + * [IN]: physical/local FB partition index. + */ + NvU32 fbpIndex; + /*! + * [OUT]: physical/local FBPA-SubPartition mask. + */ + NvU32 fbpaSubpEnMask; +} NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP + */ +typedef struct NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS { + /*! + * [IN]: physical/local FB partition index. + */ + NvU32 fbpIndex; + /*! + * [OUT]: Logical/local FBP index + */ + NvU32 fbpLogicalIndex; +} NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_ROP_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS { + /*! + * [IN]: physical/local FB partition index. + */ + NvU32 fbpIndex; + /*! + * [OUT]: physical/local ROP mask. + */ + NvU32 ropEnMask; +} NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS { + /*! + * [IN]: Physical FB partition index. + */ + NvU32 fbpIndex; + /*! + * [IN]: swizzId + * PartitionID associated with a created smc partition. + */ + NvU32 swizzId; + /*! + * [OUT]: physical ltc mask. + */ + NvU32 ltcEnMask; +} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS { + /*! + * [IN]: Physical FB partition index. + */ + NvU32 fbpIndex; + /*! + * [IN]: swizzId + * PartitionID associated with a created smc partition. + */ + NvU32 swizzId; + /*! + * [OUT]: physical lts mask. + */ + NvU32 ltsEnMask; +} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS { + /*! + * [IN]: Physical FB partition index. + */ + NvU32 fbpIndex; + /*! + * [IN]: swizzId + * PartitionID associated with a created smc partition. + */ + NvU32 swizzId; + /*! + * [OUT]: physical fbpa mask. + */ + NvU32 fbpaEnMask; +} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS { + /*! + * [IN]: Physical FB partition index. + */ + NvU32 fbpIndex; + /*! + * [IN]: swizzId + * PartitionID associated with a created smc partition. + */ + NvU32 swizzId; + /*! + * [OUT]: physical rop mask. + */ + NvU32 ropEnMask; +} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS { + /*! + * [IN]: Physical FB partition index. + */ + NvU32 fbpIndex; + /*! + * [IN]: swizzId + * PartitionID associated with a created smc partition. Currently used only for a + * device monitoring client to get the physical values of the FB. The client needs to pass + * 'NV2080_CTRL_GPU_PARTITION_ID_INVALID' explicitly if it wants RM to ignore the swizzId. + * RM will consider this request similar to a legacy case. + * The client's subscription is used only as a capability check and not as an input swizzId. + */ + NvU32 swizzId; + /*! + * [OUT]: physical FBPA_SubPartition mask associated with requested partition. + */ + NV_DECLARE_ALIGNED(NvU64 fbpaSubpEnMask, 8); +} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS; + +// Possible values for queryType +#define NV2080_CTRL_FB_FS_INFO_INVALID_QUERY 0x0U +#define NV2080_CTRL_FB_FS_INFO_FBP_MASK 0x1U +#define NV2080_CTRL_FB_FS_INFO_LTC_MASK 0x2U +#define NV2080_CTRL_FB_FS_INFO_LTS_MASK 0x3U +#define NV2080_CTRL_FB_FS_INFO_FBPA_MASK 0x4U +#define NV2080_CTRL_FB_FS_INFO_ROP_MASK 0x5U +#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK 0x6U +#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK 0x7U +#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK 0x8U +#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK 0x9U +#define NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK 0xAU +#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK 0xBU +#define NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP 0xCU + +typedef struct NV2080_CTRL_FB_FS_INFO_QUERY { + NvU16 queryType; + NvU8 reserved[2]; + NvU32 status; + union { + NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS inv; + NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS fbp, 8); + NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS ltc; + NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS lts; + NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS fbpa; + NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS rop; + NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS dmLtc; + NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS dmLts; + NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS dmFbpa; + NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS dmRop; + NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS dmFbpaSubp, 8); + NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS fbpaSubp; + NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS fbpLogicalMap; + } queryParams; +} NV2080_CTRL_FB_FS_INFO_QUERY; + +// Max number of queries that can be batched in a single call to NV2080_CTRL_CMD_FB_GET_FS_INFO +#define NV2080_CTRL_FB_FS_INFO_MAX_QUERIES 96U + +#define NV2080_CTRL_FB_GET_FS_INFO_PARAMS_MESSAGE_ID (0x46U) + +typedef struct NV2080_CTRL_FB_GET_FS_INFO_PARAMS { + NvU16 numQueries; + NvU8 reserved[6]; + NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_QUERY queries[NV2080_CTRL_FB_FS_INFO_MAX_QUERIES], 8); +} NV2080_CTRL_FB_GET_FS_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_GET_FS_INFO + * + * This control call returns the fb engine information for a partition/GPU. + * Supports an interface so that the caller can issue multiple queries by batching them + * in a single call. Returns the first error it encounters. + * + * numQueries[IN] + * - Specifies the number of valid queries. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_GET_FS_INFO (0x20801346U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_FS_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_HISTOGRAM_IDX_NO_REMAPPED_ROWS (0x0U) +#define NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAPPED_ROW (0x1U) +#define NV2080_CTRL_FB_HISTOGRAM_IDX_MIXED_REMAPPED_REMAINING_ROWS (0x2U) +#define NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAINING_ROW (0x3U) +#define NV2080_CTRL_FB_HISTOGRAM_IDX_MAX_REMAPPED_ROWS (0x4U) + +#define NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS_MESSAGE_ID (0x47U) + +typedef struct NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS { + NvU32 histogram[5]; +} NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS; + +/*! + * NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM + * + * This control call returns stats on the number of banks that have a certain + * number of rows remapped in the bank. Specifically the number of banks that + * have 0, 1, 2 through (max-2), max-1 and max number of rows remapped in the + * bank. Values will be returned in an array. + * + * Index values are: + * + * NV2080_CTRL_FB_HISTOGRAM_IDX_NO_REMAPPED_ROWS + * Number of banks with zero rows remapped + NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAPPED_ROW + * Number of banks with one row remapped + NV2080_CTRL_FB_HISTOGRAM_IDX_MIXED_REMAPPED_REMAINING_ROWS + * Number of banks with 2 through (max-2) rows remapped + NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAINING_ROW + * Number of banks with (max-1) rows remapped + NV2080_CTRL_FB_HISTOGRAM_IDX_MAX_REMAPPED_ROWS + * Number of banks with max rows remapped + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM (0x20801347U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_FB_GET_DYNAMICALLY_BLACKLISTED_PAGES + * + * This command returns the list of dynamically blacklisted video memory page addresses + * after last driver load. + * + * blackList + * This output parameter is an array of NV2080_CTRL_FB_DYNAMIC_BLACKLIST_ADDRESS_INFO + * This array can hold a maximum of NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES. + * validEntries + * This output parameter specifies the number of valid entries in the + * blackList array. + * baseIndex + * With the limit of up to 512 blacklisted pages, the size of this array + * exceeds the rpc buffer limit. This control call will collect the data + * in multiple passes. This parameter indicates the start index of the + * data to be passed back to the caller + * This cannot be greater than NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES + * bMore + * This parameter indicates whether there are more valid elements to be + * fetched. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_FB_GET_DYNAMIC_OFFLINED_PAGES (0x20801348U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */ + +/* Maximum pages that can be dynamically blacklisted */ +#define NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES 512U + +/* + * Maximum entries that can be sent in a single pass of + * NV2080_CTRL_CMD_FB_GET_DYNAMIC_OFFLINED_PAGES + */ +#define NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES 64U + +/** + * NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO + * pageNumber + * This output parameter specifies the dynamically blacklisted page number. + * source + * The reason for the page to be retired. Valid values for + * this parameter include: + * NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_INVALID + * Invalid source. + * NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE + * Page retired by dynamic page retirement due to a double bit + * error seen. + */ +typedef struct NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO { + NV_DECLARE_ALIGNED(NvU64 pageNumber, 8); + NvU8 source; +} NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO; + +#define NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_MESSAGE_ID (0x48U) + +typedef struct NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO offlined[NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES], 8); + NvU32 validEntries; + NvU32 baseIndex; + NvBool bMore; +} NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS; + +/* valid values for source */ + +#define NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_INVALID (0x00000000U) +#define NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_DPR_DBE (0x00000001U) + +/* + * NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO + * + * This control command is used by clients to query information pertaining to client allocations. + * + * + * @params [IN/OUT] NvU64 allocCount: + * Client specifies the allocation count that it received using the + * previous NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO control call. + * RM will get the total number of allocations known by RM and fill + * allocCount with it. + * + * @params [IN] NvP64 pAllocInfo: + * Pointer to the buffer allocated by client of size NV2080_CTRL_CMD_FB_ALLOCATION_INFO * + * allocCount. RM returns the info pertaining to each of the contiguous client + * allocation chunks in pAllocInfo. The format of the allocation information is given by + * NV2080_CTRL_CMD_FB_ALLOCATION_INFO. The client has to sort the returned information if + * it wants to retain the legacy behavior of SORTED BY OFFSET. Information is only returned + * if and only if allocCount[IN]>=allocCount[OUT] and clientCount[IN]>=clientCount[OUT]. + * + * @params [IN/OUT] NvP64 clientCount: + * Client specifies the client count that it received using the + * previous NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO control call. + * RM will get the total number of clients that have allocations with RM + * and fill clientCount with it. + * + * @params [IN] NvP64 pClientInfo: + * Pointer to the buffer allocated by client of size NV2080_CTRL_CMD_FB_CLIENT_INFO * + * clientCount. RM returns the info pertaining to each of the clients that have allocations + * known about by RM in pClientInfo. The format of the allocation information is given by + * NV2080_CTRL_CMD_FB_CLIENT_INFO. Information is only returned if and only if + * allocCount[IN]>=allocCount[OUT] and clientCount[IN]>=clientCount[OUT]. + * + * @returns Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_POINTER + * NV_ERR_NO_MEMORY + * + * @Usage: All privileged RM clients for debugging only. Initially, call this with allocCount = + * clientCount = 0 to get client count, and then call again with allocated memory and sizes. + * Client can repeat with the new count-sized allocations until a maximum try count is + * reached or client is out of memory. + */ + +#define NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO (0x20801349U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS_MESSAGE_ID" */ + +/* + * These work with the FLD_SET_REF_NUM and FLD_TEST_REF macros and describe the 'flags' member + * of the NV2080_CTRL_CMD_FB_ALLOCATION_INFO struct. + */ + +// Address space of the allocation +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE 4:0 +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_SYSMEM 0U +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_VIDMEM 1U + +// Whether the allocation is shared +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED 5:5 +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_FALSE 0U +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_TRUE 1U + +// Whether this client owns this allocation +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER 6:6 +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_FALSE 0U +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_TRUE 1U + +typedef struct NV2080_CTRL_CMD_FB_ALLOCATION_INFO { + NvU32 client; /* [OUT] Identifies the client that made or shares the allocation (index into pClientInfo)*/ + NvU32 flags; /* [OUT] Flags associated with the allocation (see previous defines) */ + NV_DECLARE_ALIGNED(NvU64 beginAddr, 8); /* [OUT] Starting physical address of the chunk */ + NV_DECLARE_ALIGNED(NvU64 size, 8); /* [OUT] Size of the allocated contiguous chunk in bytes */ +} NV2080_CTRL_CMD_FB_ALLOCATION_INFO; + +typedef struct NV2080_CTRL_CMD_FB_CLIENT_INFO { + NvHandle handle; /* [OUT] Handle of the client that made or shares the allocation */ + NvU32 pid; /* [OUT] PID of the client that made or shares the allocation */ + + /* For the definition of the subprocessID and subprocessName params, see NV0000_CTRL_CMD_SET_SUB_PROCESS_ID */ + NvU32 subProcessID; /* [OUT] Subprocess ID of the client that made or shares the allocation */ + char subProcessName[NV_PROC_NAME_MAX_LENGTH]; /* [OUT] Subprocess Name of the client that made or shares the allocation */ +} NV2080_CTRL_CMD_FB_CLIENT_INFO; + +#define NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS_MESSAGE_ID (0x49U) + +typedef struct NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 allocCount, 8); + NV_DECLARE_ALIGNED(NvP64 pAllocInfo, 8); + NV_DECLARE_ALIGNED(NvU64 clientCount, 8); + NV_DECLARE_ALIGNED(NvP64 pClientInfo, 8); +} NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS + * + * This control command is used by clients to update the NUMA status. + * + * @params [IN] NvBool bOnline: + * + * @returns Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * + */ +#define NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS (0x20801350U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS_MESSAGE_ID (0x50U) + +typedef struct NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS { + NvBool bOnline; +} NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_FB_GET_NUMA_INFO + * + * This control command is used by clients to get per-subdevice NUMA memory + * information as assigned by the system. + * + * numaNodeId[OUT] + * - Specifies the NUMA node ID. + * + * numaMemAddr[OUT] + * - Specifies the NUMA memory address. + * + * numaMemSize[OUT] + * - Specifies the NUMA memory size. + * + * numaOfflineAddressesCount[IN/OUT] + * - If non-zero, then it specifies the maximum number of entries in + * numaOfflineAddresses[] for which the information is required. + * It will be updated with the actual number of entries present in + * the numaOfflineAddresses[]. + * + * numaOfflineAddresses[OUT] + * - If numaOfflineAddressesCount is non-zero, it contains the addresses + * of offline pages in the NUMA region. + * + * @returns Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FB_GET_NUMA_INFO (0x20801351U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_NUMA_INFO_MAX_OFFLINE_ADDRESSES 64U + +#define NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS_MESSAGE_ID (0x51U) + +typedef struct NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS { + NvS32 numaNodeId; + NV_DECLARE_ALIGNED(NvU64 numaMemAddr, 8); + NV_DECLARE_ALIGNED(NvU64 numaMemSize, 8); + NvU32 numaOfflineAddressesCount; + NV_DECLARE_ALIGNED(NvU64 numaOfflineAddresses[NV2080_CTRL_FB_NUMA_INFO_MAX_OFFLINE_ADDRESSES], 8); +} NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS; + +/* _ctrl2080fb_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h new file mode 100644 index 0000000..b8341aa --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h @@ -0,0 +1,791 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080fifo.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* + * NV2080_CTRL_CMD_SET_GPFIFO + * + * This command set the GPFIFO offset and number of entries for a channel + * after it has been allocated. The channel must be idle and not pending, + * otherwise ERROR_IN_USE will be returned. + * + * hChannel + * The handle to the channel. + * base + * The base of the GPFIFO in the channel ctxdma. + * numEntries + * The number of entries in the GPFIFO. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_CHANNEL + * NV_ERR_STATE_IN_USE + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV2080_CTRL_CMD_SET_GPFIFO (0x20801102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_SET_GPFIFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_SET_GPFIFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_CMD_SET_GPFIFO_PARAMS { + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 base, 8); + NvU32 numEntries; +} NV2080_CTRL_CMD_SET_GPFIFO_PARAMS; + +/* + * NV2080_CTRL_FIFO_BIND_CHANNEL + * + * This structure is used to describe a channel that is to have + * it's bindable engines bound to those of other channels. + * + * hClient + * This structure member contains the handle of the client object + * that owns the channel object specified by hChannel. + * + * hChannel + * This structure member contains the channel handle of the channel + * object. + */ + +typedef struct NV2080_CTRL_FIFO_BIND_CHANNEL { + NvHandle hClient; + NvHandle hChannel; +} NV2080_CTRL_FIFO_BIND_CHANNEL; + +/* + * NV2080_CTRL_CMD_FIFO_BIND_ENGINES + * + * This control call is now deprecated. + * This command can be used to bind different video engines on G8X from separate + * channels together for operations such as idling. The set of bindable engines + * includes the NV2080_ENGINE_TYPE_BSP, NV2080_ENGINE_TYPE_VP and + * NV2080_ENGINE_TYPE_PPP engines. + * + * bindChannelCount + * This parameter specifies the number of channels to bind together. This + * parameter cannot exceed NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS. + * + * bindChannels + * The parameter specifies the array of channels to bind together. The first + * bindChannelCount entries are used in the bind channel operation. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_CHANNEL + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS (16) + +#define NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS { + NvU32 bindChannelCount; + NV2080_CTRL_FIFO_BIND_CHANNEL bindChannels[NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS]; +} NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS; + +#define NV2080_CTRL_CMD_FIFO_BIND_ENGINES (0x20801103) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES + * + * This command is used for a client to setup specialized custom operational + * properties that may be specific to an environment, or properties that + * should be set generally but are not for reasons of backward compatibility + * with previous chip generations + * + * flags + * This field specifies the operational properties to be applied + * + * Possible return status values returned are + * NV_OK + * NV_ERR_INVALID_CHANNEL + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES (0x20801104) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS { + NvU32 flags; +} NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS; + +#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE 0:0 +#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_FALSE (0x00000000) +#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_TRUE (0x00000001) + +/* + * NV2080_CTRL_CMD_FIFO_GET_PHYSICAL_CHANNEL_COUNT + * + * This command returns the maximum number of physical channels available for + * allocation on the current GPU. This may be less than or equal to the total + * number of channels supported by the current hardware. + * + * physChannelCount + * This output parameter contains the maximum physical channel count. + * + * physChannelCountInUse + * This output parameter contains the number of physical channels in use + * + * Possible return status values returned are + * NV_OK + * + */ +#define NV2080_CTRL_CMD_FIFO_GET_PHYSICAL_CHANNEL_COUNT (0x20801108) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS { + NvU32 physChannelCount; + NvU32 physChannelCountInUse; +} NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS; + +/* + * NV2080_CTRL_FIFO_INFO + * + * This structure represents a single 32bit fifo engine value. Clients + * request a particular FIFO engine value by specifying a unique fifo + * information index. + * + * Legal fifo information index values are: + * NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL + * This index can be used to request the amount of instance space + * in kilobytes reserved by the fifo engine. + * NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS + * This index can be used to query the maximum number of channel groups + * that can be allocated on the GPU. + * NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP + * This index can be used to query the maximum number of channels that can + * be allocated in a single channel group. + * NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP + * This index can be used to query the maximum number of subcontext that can + * be allocated in a single channel group. + * NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET + * This index can be used to query the starting offset of the RM + * pre-allocated USERD range in BAR1. This index query is honored only + * on Legacy-vGPU host RM. + * NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE + * This index can be used to query the default timeslice value + * (microseconds) used for a channel or channel group. + * NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE + * This index can be used to query the number of channel groups that are + * already allocated on the GPU. + * NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED + * This index can be used to check if per runlist channel ram is supported, and + * to query the supported number of channels per runlist. + * NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE + * This index can be used to get max channel groups supported per engine/runlist. + * NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE + * This index can be used too get channel groups currently in use per engine/runlist. + * + */ +typedef struct NV2080_CTRL_FIFO_INFO { + NvU32 index; + NvU32 data; +} NV2080_CTRL_FIFO_INFO; + +/* valid fifo info index values */ +#define NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL (0x000000000) +#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS (0x000000001) +#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP (0x000000002) +#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP (0x000000003) +#define NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET (0x000000004) +#define NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE (0x000000005) +#define NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE (0x000000006) +#define NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED (0x000000007) +#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE (0x000000008) +#define NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE (0x000000009) + + +/* set INDEX_MAX to greatest possible index value */ +#define NV2080_CTRL_FIFO_INFO_INDEX_MAX NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE + +#define NV2080_CTRL_FIFO_GET_INFO_USERD_OFFSET_SHIFT (12) + +/* + * NV2080_CTRL_CMD_FIFO_GET_INFO + * + * This command returns fifo engine information for the associated GPU. + * Requests to retrieve fifo information use an array of one or more + * NV2080_CTRL_FIFO_INFO structures. + * + * fifoInfoTblSize + * This field specifies the number of valid entries in the fifoInfoList + * array. This value cannot exceed NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES. + * fifoInfoTbl + * This parameter contains the client's fifo info table into + * which the fifo info values will be transferred by the RM. + * The fifo info table is an array of NV2080_CTRL_FIFO_INFO structures. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FIFO_GET_INFO (0x20801109) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_INFO_PARAMS_MESSAGE_ID" */ + +/* maximum number of NV2080_CTRL_FIFO_INFO entries per request */ +#define NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES (256) + +#define NV2080_CTRL_FIFO_GET_INFO_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_FIFO_GET_INFO_PARAMS { + NvU32 fifoInfoTblSize; + /* + * C form: + * NV2080_CTRL_FIFO_INFO fifoInfoTbl[NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES]; + */ + NV2080_CTRL_FIFO_INFO fifoInfoTbl[NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES]; + NvU32 engineType; +} NV2080_CTRL_FIFO_GET_INFO_PARAMS; + + + +/* + * NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL + * + * This command removes the specified channel from the associated GPU's runlist + * and then initiates RC recovery. If the channel is active it will first be preempted. + * hChannel + * The handle to the channel to be preempted. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_CHANNEL + */ +#define NV2080_CTRL_CMD_FIFO_CHANNEL_PREEMPTIVE_REMOVAL (0x2080110a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS { + NvHandle hChannel; +} NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS + * + * This command will disable or enable scheduling of channels described in the + * list provided. Whether or not the channels are also preempted off the GPU + * can be controlled by bOnlyDisableScheduling. By default channels are preempted + * off the GPU. + * + * bDisable + * This value determines whether to disable or + * enable the set of channels. + * numChannels + * The number of channels to be stopped. + * bOnlyDisableScheduling + * When false and bDisable=NV_TRUE,the call will ensure none of the listed + * channels are running in hardware and will not run until a call with + * bDisable=NV_FALSE is made. When true and bDisable=NV_TRUE, the control + * call will ensure that none of the listed channels can be scheduled on the + * GPU until a call with bDisable=NV_FALSE is made, but will not remove any + * of the listed channels from hardware if they are currently running. When + * bDisable=NV_FALSE this field is ignored. + * bRewindGpPut + * If a channel is being disabled and bRewindGpPut=NV_TRUE, the channel's RAMFC + * will be updated so that GP_PUT is reset to the value of GP_GET. + * hClientList + * An array of NvU32 listing the client handles + * hChannelList + * An array of NvU32 listing the channel handles + * to be stopped. + * pRunlistPreemptEvent + * KEVENT handle for Async HW runlist preemption (unused on preMaxwell) + * When NULL, will revert to synchronous preemption with spinloop + * + * Possible status values returned are: + * NV_OK + * NVOS_INVALID_STATE + */ + +#define NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS (0x2080110b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES (64) + +#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS { + NvBool bDisable; + NvU32 numChannels; + NvBool bOnlyDisableScheduling; + NvBool bRewindGpPut; + NV_DECLARE_ALIGNED(NvP64 pRunlistPreemptEvent, 8); + // C form: NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES] + NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES]; + // C form: NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES] + NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES]; +} NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS; + +#define NV2080_CTRL_FIFO_DISABLE_CHANNEL_FALSE (0x00000000) +#define NV2080_CTRL_FIFO_DISABLE_CHANNEL_TRUE (0x00000001) +#define NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_FALSE (0x00000000) +#define NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_TRUE (0x00000001) + +/* + * NV2080_CTRL_FIFO_MEM_INFO + * + * This structure describes the details of a block of memory. It consists + * of the following fields + * + * aperture + * One of the NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_* values + * base + * Physical base address of the memory + * size + * Size in bytes of the memory +*/ +typedef struct NV2080_CTRL_FIFO_MEM_INFO { + NvU32 aperture; + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); +} NV2080_CTRL_FIFO_MEM_INFO; + +/* + * NV2080_CTRL_FIFO_CHANNEL_MEM_INFO + * + * This structure describes the details of the instance memory, ramfc + * and method buffers a channel. It consists of the following fields + * + * inst + * Structure describing the details of instance memory + * ramfc + * Structure describing the details of ramfc + * methodBuf + * Array of structures describing the details of method buffers + * methodBufCount + * Number of method buffers(one per runqueue) + */ + +// max runqueues +#define NV2080_CTRL_FIFO_GET_CHANNEL_MEM_INFO_MAX_COUNT 0x2 + +typedef struct NV2080_CTRL_FIFO_CHANNEL_MEM_INFO { + NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_MEM_INFO inst, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_MEM_INFO ramfc, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_MEM_INFO methodBuf[NV2080_CTRL_FIFO_GET_CHANNEL_MEM_INFO_MAX_COUNT], 8); + NvU32 methodBufCount; +} NV2080_CTRL_FIFO_CHANNEL_MEM_INFO; + +/* + * NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM + * + * This command returns the memory aperture, physical base address and the + * size of each of the instance memory, cache1 and ramfc of a channel. + * + * hChannel + * The handle to the channel for which the memory information is desired. + * chMemInfo + * A NV2080_CTRL_FIFO_CHANNEL_MEM_INFO structure + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_CHANNEL +*/ + +#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO (0x2080110c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS { + NvHandle hChannel; + NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_CHANNEL_MEM_INFO chMemInfo, 8); +} NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS; + +#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_INVALID 0x00000000 +#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_VIDMEM 0x00000001 +#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_COH 0x00000002 +#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_NCOH 0x00000003 + +/* + * NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION + * + * This command determines the location (vidmem/sysmem) + * and attribute (cached/uncached/write combined) of memory where USERD is located. + * + * aperture + * One of the NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_* values. + * + * attribute + * One of the NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_* values. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_POINTER +*/ + +#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION (0x2080110d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS { + NvU32 aperture; + NvU32 attribute; +} NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS; + +// support for CPU coherent vidmem (VIDMEM_NVILINK_COH) is not yet available in RM + +#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_VIDMEM 0x00000000 +#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_SYSMEM 0x00000001 + +#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_CACHED 0x00000000 +#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_UNCACHED 0X00000001 +#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_WRITECOMBINED 0X00000002 + + + +/* + * NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE + * + * This command retrieves entries from the SW encoded GPU device info table + * from Host RM. + * + * Parameters: + * + * baseIndex [in] + * The starting index to read from the devinfo table. Must be a multiple of + * MAX_ENTRIES. + * + * entries [out] + * A buffer to store up to MAX_ENTRIES entries of the devinfo table. + * + * numEntries [out] + * Number of populated entries in the provided buffer. + * + * bMore [out] + * A boolean flag indicating whether more valid entries are available to be + * read. A value of NV_TRUE indicates that a further call to this control + * with baseIndex incremented by MAX_ENTRIES will yield further valid data. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE (0x20801112) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_DEVICES 256 +#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES 32 +#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES 16 +#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA 2 +#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN 16 + +/* + * NV2080_CTRL_FIFO_DEVICE_ENTRY + * + * This structure contains the engine, engine name and + * push buffers information of FIFO device entry. It consists of the following fields + * + * engineData + * Type of the engine + * pbdmaIds + * List of pbdma ids associated with engine + * pbdmaFaultIds + * List of pbdma fault ids associated with engine + * numPbdmas + * Number of pbdmas + * engineName + * Name of the engine + */ +typedef struct NV2080_CTRL_FIFO_DEVICE_ENTRY { + NvU32 engineData[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES]; + NvU32 pbdmaIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA]; + NvU32 pbdmaFaultIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA]; + NvU32 numPbdmas; + char engineName[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN]; +} NV2080_CTRL_FIFO_DEVICE_ENTRY; + +#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS { + NvU32 baseIndex; + NvU32 numEntries; + NvBool bMore; + // C form: NV2080_CTRL_FIFO_DEVICE_ENTRY entries[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES]; + NV2080_CTRL_FIFO_DEVICE_ENTRY entries[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES]; +} NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT + * + * This command clears the ENGINE or PBDMA FAULTED bit and reschedules the faulted channel + * by ringing channel's doorbell + * + * Parameters: + * + * engineType [in] + * The NV2080_ENGINE_TYPE of the engine to which the faulted + * channel is bound. This may be a logical id for guest RM in + * case of SMC. + * + * vChid [in] + * Virtual channel ID on which the fault occurred + * + * faultType [in] + * Whether fault was triggered by engine (_ENGINE_FAULTED) or PBDMA (_PBDMA_FAULTED) + * The value specified must be one of the NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_* values + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT (0x20801113) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_ENGINE 0x00000001 +#define NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_PBDMA 0x00000002 + +#define NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS { + NvU32 engineType; + NvU32 vChid; + NvU32 faultType; +} NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS; + + + +/* + * NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY + * + * Allows clients to set the global scheduling policy for all runlists + * associated to the given subdevice. + * + * Currently, this is only supported for HW runlists. + * + * Since this is a global setting, only privileged clients will be allowed to + * set it. Regular clients will get NV_ERR_INSUFFICIENT_PERMISSIONS error. + * + * Once a certain scheduling policy is set, that policy cannot be changed to a + * different one unless all clients which set it have either restored the policy + * (using the corresponding restore flag) or died. Clients trying to set a + * policy while a different one is locked by another client will get a + * NV_ERR_INVALID_STATE error. + * + * The same client can set a scheduling policy and later change to another one + * only when no other clients have set the same policy. Such sequence will be + * equivalent to restoring the policy in between. + * + * For instance, the following sequence: + * + * 1. Set policy A + * 2. Set policy B + * + * is equivalent to: + * + * 1. Set policy A + * 2. Restore policy + * 3. Set policy B + * + * Parameters: + * + * flags + * This field specifies the operational properties to be applied: + * + * - NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_FALSE + * Try to set the provided 'schedPolicy' scheduling policy. If the + * operation succeeds, other clients will be prevented from setting a + * different scheduling policy until all clients using it have either + * restored it or died. + * + * - NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_TRUE + * Let the scheduler know the client no longer requires the current + * scheduling policy. This may or may not actually change the + * scheduling policy, depending on how many other clients are also + * using the current policy. + * + * The 'schedPolicy' parameter is ignored when this flag is set. + * + * schedPolicy + * One of: + * + * - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_DEFAULT + * Set the default scheduling policy and prevent other clients from + * changing it. + * + * - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED + * This scheduling policy will make channels to be scheduled according + * to their interleave level. See NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL + * description for more details. + * - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM + * This scheduling policy will make channels to be scheduled according + * to their interleave level per WDDM policy. + * See NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL description for more details. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_INVALID_STATE + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY (0x20801115) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS_MESSAGE_ID" */ + +/* schedPolicy values */ +#define NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_DEFAULT 0x0 +#define NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED 0x1 +#define NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM 0x2 + +/* SET_SCHED_POLICY flags */ +#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE 0:0 +#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_FALSE (0x00000000) +#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_TRUE (0x00000001) + +#define NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS { + NvU32 flags; + NvU32 schedPolicy; +} NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_UPDATE_CHANNEL_INFO + * + * This command updates the channel info params for an existing channel + * + * Can be a deferred Api. The control call can be used for migrating a + * + * channel to a new userd and gpfifo + * + * Parameters: + * [in] hClient - Client handle + * [in] hChannel - Channel handle + * [in] hUserdMemory - UserD handle + * [in] gpFifoEntries - Number of Gpfifo Entries + * [in] gpFifoOffset - Gpfifo Virtual Offset + * [in] userdOffset - UserD offset + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FIFO_UPDATE_CHANNEL_INFO (0x20801116) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS { + NvHandle hClient; + NvHandle hChannel; + NvHandle hUserdMemory; + NvU32 gpFifoEntries; + NV_DECLARE_ALIGNED(NvU64 gpFifoOffset, 8); + NV_DECLARE_ALIGNED(NvU64 userdOffset, 8); +} NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS + * + * This command will disable or enable scheduling of all usermode channels. + * + * bDisable + * This value determines whether to disable or enable the usermode channels. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS (0x20801117) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS_MESSAGE_ID (0x17U) + +typedef struct NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS { + NvBool bDisable; +} NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB + * + * When a VF subcontext is marked as a zombie, host RM points its PDB to a dummy + * page allocated by guest RM in GPA space. This command provides the parameters + * of the guest RMs memory descriptor to be able to create a corresponding + * memory descriptor on the host RM. Host RM uses this to program the PDB of a + * zombie subcontext. + * + * Parameters: + * Input parameters to describe the memory descriptor + * [in] base + * [in] size + * [in] addressSpace + * [in] cacheAttrib + */ +#define NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB (0x20801118) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS { + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 addressSpace; + NvU32 cacheAttrib; +} NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_GET_ALLOCATED_CHANNELS + * + * Get's a bitmask of allocated channels. No guarantees are made about + * synchronization. A channel returned as allocated by this ctrl cmd might have + * already been destructed. + * + * Parameters: + * [in] runlistId + * [in,out] bitMask A 1 bit indicates that a channel with this index/id is + * allocated. This field is a multiple of 32 bits and each 32 + * bit group must be accessed as a platform 32 bit int to + * correctly map channel IDs. + * + */ +#define NV2080_CTRL_CMD_FIFO_GET_ALLOCATED_CHANNELS (0x20801119) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS_MESSAGE_ID" */ + +/* + * The maximum number than can be returned by + * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS + */ +#define NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS 4096 + +#define NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS { + NvU32 runlistId; + NvU32 bitMask[NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS / 32]; +} NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS; + + + +/* _ctrl2080fifo_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h new file mode 100644 index 0000000..3fe89b9 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h @@ -0,0 +1,208 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080fla.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX FLA control commands and parameters */ + +/* + * NV2080_CTRL_CMD_FLA_RANGE + * + * This command is used to initialize/destroy FLA VAS for a GPU.This is intended + * to be used by RM clients that manages the FLA VASpace range. The mode of the + * command is decided based on the parameter passed by the client. + * + * base + * This parameter specifies the base of the FLA VAS that needs to be allocated + * for this GPU + * + * size + * This parameter specifies the size of the FLA VAS that needs to be allocated + * for this GPU + * + * mode + * This parameter specifies the functionality of the command. + * MODE_INITIALIZE + * Setting this mode, will initialize the FLA VASpace for the gpu with + * base and size passed as arguments. FLA VASpace will be owned by RM. + * if the client calls the command more than once before destroying + * the FLA VAS, then this command will verify the range exported before and + * return success if it matches. If FLA is not supported for the platform, + * will return NV_ERR_NOT_SUPPORTED. + * MODE_DESTROY (deprecated) + * This command is NOP. + * MODE_HOST_MANAGED_VAS_INITIALIZE + * This mode will initialize the FLA VASpace for the gpu with hVASpace + * handle in addition to base and size arguments. FLA VASpace will be initiated + * and owned by guest RM. Used only in virtualization platforms by internal clients. + * MODE_HOST_MANAGED_VAS_DESTROY + * This mode will destroy the FLA VAS associated with the device. It will destruct + * only the resources associated with host RM side. Used only in virtualization platforms + * by internal clients. + * + * hVASpace + * This paramete specifies the FLA VAspace that needs to be associated with + * device. This parameter takes effect only for internal client in virtualization + * platforms. For any other platform and external clients, this parameter has no effect. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_IN_USE + * NV_ERR_INVALID_OWNER + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_FLA_RANGE (0x20803501) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_RANGE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLA_RANGE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_FLA_RANGE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 mode; + NvHandle hVASpace; +} NV2080_CTRL_FLA_RANGE_PARAMS; + +#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_NONE 0x00000000 +#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_INITIALIZE NVBIT(0) +#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_DESTROY NVBIT(1) +#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_INITIALIZE NVBIT(2) +#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_DESTROY NVBIT(3) + + +/* + * NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK + * + * This command is used to (un)bind FLA Instance Memory Block(IMB) with MMU. + * This control call is created for vGPU platform, when a FLA VAS is created/destroyed + * by Guest RM. Guest RM doesn't have privilege to (un)bind the IMB with MMU, hence + * need to be RPC-ed to Host RM to (un)bind + * The mode of the command is decided based on the actionParam passed by the client. + * + * imbPhysAddr + * This parameter specifies the FLA Instance Memory Block PA to be programmed + * to MMU. IMB address should be 4k aligned. This parameter is needed only + * for ACTION_BIND. + * + * addrSpace + * This parameter specifies the address space of FLA Instance Memory Block. This + * parmater is needed only for ACTION_BIND. + * Available options are: + * NV2080_CTRL_FLA_ADDRSPACE_SYSMEM + * Clients need to use this address space if the IMB is located in sysmem + * NV2080_CTRL_FLA_ADDRSPACE_FBMEM + * Clients need to use this address space if the IMB is located in FB + * + * actionParam + * This parameter specifies the functionality of the command. + * NV2080_CTRL_FLA_ACTION_BIND + * Setting this type, will call busBindFla helper HAL + * NV2080_CTRL_FLA_ACTION_UNBIND + * Setting this type, will call busUnbindFla helper HAL + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +typedef enum NV2080_CTRL_FLA_ADDRSPACE { + NV2080_CTRL_FLA_ADDRSPACE_SYSMEM = 0, + NV2080_CTRL_FLA_ADDRSPACE_FBMEM = 1, +} NV2080_CTRL_FLA_ADDRSPACE; + +typedef enum NV2080_CTRL_FLA_ACTION { + NV2080_CTRL_FLA_ACTION_BIND = 0, + NV2080_CTRL_FLA_ACTION_UNBIND = 1, +} NV2080_CTRL_FLA_ACTION; + +#define NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK (0x20803502) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS { + NV_DECLARE_ALIGNED(NvU64 imbPhysAddr, 8); + NV2080_CTRL_FLA_ADDRSPACE addrSpace; + NV2080_CTRL_FLA_ACTION flaAction; +} NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS; + + +/* + * NV2080_CTRL_CMD_FLA_GET_RANGE + * + * This command is used to query the FLA base and size from plugin to return as static info to Guest RM. + * + * base + * This parameter returns the base address of FLA range registered to the subdevice. + * size + * This parameter returns the size of FLA range registered to the subdevice. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FLA_GET_RANGE (0x20803503) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_GET_RANGE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLA_GET_RANGE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_FLA_GET_RANGE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); +} NV2080_CTRL_FLA_GET_RANGE_PARAMS; + +/* + * NV2080_CTRL_CMD_FLA_GET_FABRIC_MEM_STATS + * + * This command returns the total size and the free size of the fabric vaspace. + * Note: This returns the information for the FABRIC_VASPACE_A class. + * + * totalSize[OUT] + * - Total fabric vaspace. + * + * freeSize [OUT] + * - Available fabric vaspace. + * + * Possible status values returned are: + * + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FLA_GET_FABRIC_MEM_STATS (0x20803504) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 totalSize, 8); + NV_DECLARE_ALIGNED(NvU64 freeSize, 8); +} NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS; + +// _ctrl2080fla_h_ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h new file mode 100644 index 0000000..474f916 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h @@ -0,0 +1,444 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080flcn.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + + +// +// XAPICHK/XAPI_TEST breaks on including "nvmisc.h". Workaround: don't include +// the header in that case and just redefine the macros we need. +// +#include "nvmisc.h" +/* + * Obsolete Falcon ID type. Use NV2080_ENGINE_TYPE_ instead + */ +#define FALCON_ID_PMU (NV2080_ENGINE_TYPE_PMU) +#define FALCON_ID_DPU (NV2080_ENGINE_TYPE_DPU) +#define FALCON_ID_SEC2 (NV2080_ENGINE_TYPE_SEC2) +#define FALCON_ID_FBFLCN (NV2080_ENGINE_TYPE_FBFLCN) + +/* + * NV2080_CTRL_CMD_FLCN_GET_DMEM_USAGE + * + * This command returns total heap size and free heap size of a falcon engine + * + * flcnID + * The falcon ID + * + * heapSize + * Total heap size in byte + * + * heapFree + * Total free heap size in byte + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT + */ +#define NV2080_CTRL_CMD_FLCN_GET_DMEM_USAGE (0x20803101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS { + NvU32 flcnID; + NvU32 heapSize; + NvU32 heapFree; +} NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS; + +/*! + * @defgroup NVOS_INST_EVT Instrumentation event types. + * @{ + */ + +//! Reserved for uStreamer internal use. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RSVD_DO_NOT_USE 0x00U + +//! RTOS CTXSW includes next taskID and number of ODP for previous task. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_END 0x01U + +//! Begin of a HW IRQ. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_BEGIN 0x02U + +//! End of a HW IRQ, before stack pinning etc is performed. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_END 0x03U + +//! RTOS Timer tick slip. (Only for # tick processed > 1). +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TIMER_TICK 0x04U + +//! Task start processing an event, includes taskId, eventType and unitId (optional). +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_BEGIN 0x05U + +//! Task finished processing an event, incldues taskId. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_END 0x06U + +//! Latency for inserting response into RM queue. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RM_QUEUE_LATENCY 0x07U + +//! Special / multi-purpose event, see field definition below. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_SPECIAL_EVENT 0x08U + +//! Unused, recycle +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_UNUSED_0 0x09U + +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_DMA_END 0x0AU + +//! Begin/end for arbitrary block of code. The payload contains a sub-ID for each location profiled. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_BEGIN 0x0BU +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_END 0x0CU + +//! Queueing time for the most recent event. +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_LATENCY 0x0DU +/*!@}*/ + +#define NV2080_CTRL_FLCN_NVOS_INST_INVALID_TASK_ID 0xFFU + +/* + * NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH + * + * Get the egine arch i.e FALCON, RISCV etc given the NV2080_ENGINE_TYPE_*. + * + */ +#define NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH (0x20803118) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS { + //! The engine type, from NV2080_ENGINE_TYPE_* + NvU32 engine; + + //! The engine architecture - FALCON or RISC-V + NvU32 engineArch; +} NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS; + +/*! + * @defgroup Engine Arch types + * @{ + */ +#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_DEFAULT 0x0 +#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_FALCON 0x1 +#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV 0x2 +/*!@}*/ + + +/* ----------------------- uStreamer (INST v2) ------------------------------ */ +/*! + * @defgroup NV2080_CTRL_FLCN_USTREAMER_EVENT uStreamer event fields. + * + * This is a binary-packed representation of uStreamer events. There are + * three main types of entry: Head, Payload, and Tail. COMM here is used + * when a field is shared among multiple event types. + * + * @{ + */ +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_COMM_FLAG 31:31 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_COMM_HEAD 30:30 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_VARIABLE 29:29 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EXTEND 28:28 + +/*! + * Below DRF's need constants assigned to start and end so they can be represented in FINN properly + * This is because FINN v1 will not have the ability to represent DRF's and bit fields yet. + */ +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT (27) +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE (20) +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID \ + (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT) : \ + (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE) +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT (28) +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE (24) +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT \ + (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT) : \ + (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE) + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_LENGTH 19:8 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOAD 7:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT 23:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_HEAD_TIME 29:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_DATA_PAYLOAD 30:0 +/*!@}*/ + + +/*! + * @defgroup NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_BREAKDOWN + * + * These DRFs define breakdown of the compact payload for various event IDs. + * + * @{ + */ + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_TASK_ID 7:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON 10:8 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_YIELD 0x0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_INT0 0x1 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_TIMER_TICK 0x2 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_QUEUE_BLOCK 0x3 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_DMA_SUSPENDED 0x4 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_ODP_MISS_COUNT 23:11 + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TIMER_TICK_TIME_SLIP 23:0 + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_TASK_ID 7:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_UNIT_ID 15:8 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_EVENT_TYPE 23:16 + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_TASK_ID 7:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_CALLBACK_ID 15:8 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC 15:8 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC_BOBJ_CMD_BASE 0xF0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_CLASS_ID 23:16 + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_RM_QUEUE_LATENCY_SHIFT 10U + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_TASK_ID 7:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID 23:8 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_RESERVED 0x000000 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_CB_ENQUEUE_FAIL 0x000001 + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_LATENCY_SHIFT 6U + +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID 11:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_INVALID 0x000 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_VF_SWITCH_TOTAL 0x001 + +/*!@}*/ + + +/*! + * @defgroup NV2080_CTRL_FLCN_USTREAMER_FEATURE + * + * This defines all the features currently supported by uStreamer. For a new + * usecase of uStreamer, a feature should be defined here describing the usecase. + * This value should be unique for each queue. + * + * @{ + */ +#define NV2080_CTRL_FLCN_USTREAMER_FEATURE_DEFAULT 0U +#define NV2080_CTRL_FLCN_USTREAMER_FEATURE_PMUMON 1U +#define NV2080_CTRL_FLCN_USTREAMER_FEATURE__COUNT 2U +/*!@}*/ + +/*! + * @defgroup NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY + * + * This defines the DRF used for ustreamer queue policy + * + * @{ + */ + +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH 0:0 +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_DISABLED 0U +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_ENABLED 1U + +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH 1:1 +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_DISABLED 0U +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_ENABLED 1U + +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH 2:2 +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_DISABLED 0U +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_ENABLED 1U + +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_THRESHOLD 31:8 + +/*!@}*/ + +/*! + * The maximum number of compact event types, calculated from the number of bits + * in the event structure. + */ +#define NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES_COMPACT (0x20U) /* finn: Evaluated from "(1 << (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT - NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE + 1))" */ + +/*! + * The maximum number of event types, calculated from the number of bits in the + * event structure. + */ +#define NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES (0x120U) /* finn: Evaluated from "((1 << (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT - NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE + 1)) + NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES_COMPACT)" */ + +/*! + * The number of bytes required in the event mask to contain all event types. + */ +#define NV2080_CTRL_FLCN_USTREAMER_MASK_SIZE_BYTES (0x24U) /* finn: Evaluated from "((NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES + 7) / 8)" */ + +/*! + * uStreamer Event Filter type, stored as a bitmask. + */ +typedef struct NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER { + NvU8 mask[NV2080_CTRL_FLCN_USTREAMER_MASK_SIZE_BYTES]; +} NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER; + +/*! + * NV2080_CTRL_CMD_FLCN_USTREAMER_QUEUE_INFO + * Get queue info for mapping / unmapping + */ +#define NV2080_CTRL_CMD_FLCN_USTREAMER_QUEUE_INFO (0x20803120) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS { + //! The engine type, from NV2080_ENGINE_TYPE_* + NvU32 engine; + + //! + // The page size of the requested queue in bytes. + // + NvU32 pageSize; + + //! Offset of the queue buffer in FB. + NV_DECLARE_ALIGNED(NvUPtr offset, 8); + + //! + // The size of the user-mapped instrumentation buffer. Measured in bytes. + // + NvU32 size; + + //! + // The feature ID of the queue. + // + NvU8 queueFeatureId; +} NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET/SET + * + * Get/set the event bitmask for the default queue. + */ +#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET (0x20803122) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x22" */ + +#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_SET (0x20803123) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x23" */ + +typedef struct NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS { + //! The engine type, from NV2080_ENGINE_TYPE_* + NvU32 engine; + + /*! + * The bitmask of which event types to log. An event type corresponding to + * a bit with a zero will be ignored at the log site, which prevents it + * from filling up the resident buffer in the PMU. In general, set this to + * only log the event types you actually want to use. + * Refer to NVOS_BM_* in nvos_utility.h for usage. + */ + NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER eventFilter; + + //! The queueId of the queue whose eventFilter we want to interact with + NvU8 queueId; +} NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS; + +/* + * NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO + * + * This command provides the attributes of the falcon engine context buffer + * + * hUserClient [IN] + * This parameter specifies the client handle that owns this channel. + * hChannel [IN] + * This parameter specifies the channel or channel group (TSG) handle + * alignment + * Specifies the alignment requirement for each context buffer + * size + * Aligned size of context buffer + * bufferHandle + * Opaque pointer to memdesc. Used by kernel clients for tracking purpose only. + * pageCount + * allocation size in the form of pageCount + * physAddr + * Physical address of the buffer first page + * aperture + * allocation aperture. Could be SYSMEM, VIDMEM, UNKNOWN + * kind + * PTE kind of this allocation. + * pageSize + * Page size of the buffer. + * bIsContigous + * States if physical allocation for this buffer is contiguous. PageSize will + * have no meaning if this flag is set. + * bDeviceDescendant + * TRUE if the allocation is a constructed under a Device or Subdevice. + * uuid + * SHA1 UUID of the Device or Subdevice. Valid when bDeviceDescendant is TRUE. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO (0x20803124) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID (0x24U) + +typedef struct NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS { + NvHandle hUserClient; + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 alignment, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NV_DECLARE_ALIGNED(NvP64 bufferHandle, 8); + NV_DECLARE_ALIGNED(NvU64 pageCount, 8); + NV_DECLARE_ALIGNED(NvU64 physAddr, 8); + NvU32 aperture; + NvU32 kind; + NvU32 pageSize; + NvBool bIsContigous; + NvBool bDeviceDescendant; + NvU8 uuid[16]; +} NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS; + +// Aperture flags +#define NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_UNKNWON ADDR_UNKNOWN +#define NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_SYSMEM ADDR_SYSMEM +#define NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_FBMEM ADDR_FBMEM + +/* + * NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE + * + * This command provides the size of the falcon engine context buffer + * + * hChannel [IN] + * This parameter specifies the channel or channel group (TSG) handle + * totalBufferSize [OUT] + * This parameter returns the total context buffers size. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE (0x20803125) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x25U) + +typedef struct NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS { + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 totalBufferSize, 8); +} NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS; + + + +/* _ctrl2080flcn_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h new file mode 100644 index 0000000..2af63e7 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080fuse.finn +// + + + +/* _ctrl2080fuse_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h new file mode 100644 index 0000000..41f9767 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h @@ -0,0 +1,36 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080gpio.finn +// + + + +/* _ctrl2080gpio_h_ */ + +#include "ctrl/ctrl2080/ctrl2080base.h" + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h new file mode 100644 index 0000000..0b97569 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h @@ -0,0 +1,4115 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080gpu.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "ctrl/ctrl2080/ctrl2080gr.h" +#include "ctrl/ctrl0000/ctrl0000system.h" +#include "nvcfg_sdk.h" +#include "nvstatus.h" + +#define NV_GRID_LICENSE_INFO_MAX_LENGTH (128) + +/* License info strings for vGPU products */ +#define NV_GRID_LICENSE_FEATURE_VPC_EDITION "GRID-Virtual-PC,2.0;Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0" +#define NV_GRID_LICENSE_FEATURE_VAPPS_EDITION "GRID-Virtual-Apps,3.0" +#define NV_GRID_LICENSE_FEATURE_VIRTUAL_WORKSTATION_EDITION "Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0" +#define NV_GRID_LICENSE_FEATURE_GAMING_EDITION "GRID-vGaming,8.0" +#define NV_GRID_LICENSE_FEATURE_COMPUTE_EDITION "NVIDIA-vComputeServer,9.0;Quadro-Virtual-DWS,5.0" + +#define NV_GRID_LICENSED_PRODUCT_VWS "NVIDIA RTX Virtual Workstation" +#define NV_GRID_LICENSED_PRODUCT_GAMING "NVIDIA Cloud Gaming" +#define NV_GRID_LICENSED_PRODUCT_VPC "NVIDIA Virtual PC" +#define NV_GRID_LICENSED_PRODUCT_VAPPS "NVIDIA Virtual Applications" +#define NV_GRID_LICENSED_PRODUCT_COMPUTE "NVIDIA Virtual Compute Server" + + + +/* NV20_SUBDEVICE_XX gpu control commands and parameters */ + +/* Valid feature values */ +#define NV2080_CTRL_GPU_GET_FEATURES_CLK_ARCH_DOMAINS 0:0 +#define NV2080_CTRL_GPU_GET_FEATURES_CLK_ARCH_DOMAINS_FALSE (0x00000000U) +#define NV2080_CTRL_GPU_GET_FEATURES_CLK_ARCH_DOMAINS_TRUE (0x00000001U) + + + +typedef struct NV2080_CTRL_GPU_INFO { + NvU32 index; + NvU32 data; +} NV2080_CTRL_GPU_INFO; + +/* valid gpu info index values */ + + + +#define NV2080_CTRL_GPU_INFO_INDEX_MINOR_REVISION_EXT (0x00000004U) + + +#define NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV0 (0x00000012U) +#define NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV1 (0x00000013U) + + +#define NV2080_CTRL_GPU_INFO_INDEX_SYSMEM_ACCESS (0x0000001fU) + + +#define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD (0x00000022U) + + +#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE (0x00000025U) +#define NV2080_CTRL_GPU_INFO_INDEX_IBMNPU_RELAXED_ORDERING (0x00000026U) +#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED (0x00000027U) +#define NV2080_CTRL_GPU_INFO_INDEX_NVSWITCH_PROXY_DETECTED (0x00000028U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT (0x00000029U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SMC_MODE (0x0000002aU) +#define NV2080_CTRL_GPU_INFO_INDEX_SPLIT_VAS_MGMT_SERVER_CLIENT_RM (0x0000002bU) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SM_VERSION (0x0000002cU) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY (0x0000002dU) + + +#define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM (0x0000002fU) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY (0x00000030U) +#define NV2080_CTRL_GPU_INFO_INDEX_NVENC_STATS_REPORTING_STATE (0x00000031U) + + +#define NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED (0x00000033U) +#define NV2080_CTRL_GPU_INFO_INDEX_DISPLAY_ENABLED (0x00000034U) +#define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED (0x00000035U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY (0x00000036U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY (0x00000037U) + + +#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU (0x0000003cU) +#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY (0x0000003dU) +#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x0000003eU) + +/* valid minor revision extended values */ +#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE (0x00000000U) +#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_P (0x00000001U) +#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_V (0x00000002U) +#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_PV (0x00000003U) + + + +/* valid system memory access capability values */ +#define NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_YES (0x00000001U) + + + +/* valid gemini board values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_YES (0x00000001U) + +/* valid surprise removal values */ +#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_YES (0x00000001U) + +/* valid relaxed ordering values */ +#define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_DISABLED (0x00000000U) +#define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_ENABLED (0x00000001U) +#define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_UNSUPPORTED (0xFFFFFFFFU) + +/* valid poison fuse capability values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_YES (0x00000001U) + +/* valid nvswitch proxy detected values */ +#define NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_YES (0x00000001U) + +/* valid NVSR GPU support info values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_YES (0x00000001U) + +/* valid SMC mode values */ +#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_UNSUPPORTED (0x00000000U) +#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLED (0x00000001U) +#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLED (0x00000002U) +#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLE_PENDING (0x00000003U) +#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLE_PENDING (0x00000004U) + +/* valid split VAS mode values */ +#define NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_YES (0x00000001U) + +/* valid grid capability values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_YES (0x00000001U) + +/* valid per runlist channel ram capability values */ +#define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_DISABLED (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_ENABLED (0x00000001U) + +/* valid ATS capability values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_YES (0x00000001U) + +/* valid Nvenc Session Stats reporting state values */ +#define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_DISABLED (0x00000000U) +#define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED (0x00000001U) +#define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_NOT_SUPPORTED (0x00000002U) + +/* valid 4K PAGE isolation requirement values */ +#define NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_YES (0x00000001U) + +/* valid display enabled values */ +#define NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_YES (0x00000001U) + +/* valid mobile config enabled values */ +#define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_YES (0x00000001U) + + +/* valid profiling capability values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_DISABLED (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_ENABLED (0x00000001U) + +/* valid debugging capability values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_DISABLED (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_ENABLED (0x00000001U) + + + +/* valid CMP (Crypto Mining Processor) SKU values */ +#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_YES (0x00000001U) + + +/* valid dma-buf suport values */ +#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES (0x00000001U) + +/* + * NV2080_CTRL_CMD_GPU_GET_INFO + * + * This command returns gpu information for the associated GPU. Requests + * to retrieve gpu information use a list of one or more NV2080_CTRL_GPU_INFO + * structures. + * + * gpuInfoListSize + * This field specifies the number of entries on the caller's + * gpuInfoList. + * gpuInfoList + * This field specifies a pointer in the caller's address space + * to the buffer into which the gpu information is to be returned. + * This buffer must be at least as big as gpuInfoListSize multiplied + * by the size of the NV2080_CTRL_GPU_INFO structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_OPERATING_SYSTEM + */ +#define NV2080_CTRL_CMD_GPU_GET_INFO (0x20800101U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_GPU_GET_INFO_PARAMS { + NvU32 gpuInfoListSize; + NV_DECLARE_ALIGNED(NvP64 gpuInfoList, 8); +} NV2080_CTRL_GPU_GET_INFO_PARAMS; + +#define NV2080_CTRL_CMD_GPU_GET_INFO_V2 (0x20800102U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x2" */ + +typedef struct NV2080_CTRL_GPU_GET_INFO_V2_PARAMS { + NvU32 gpuInfoListSize; + NV2080_CTRL_GPU_INFO gpuInfoList[NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE]; +} NV2080_CTRL_GPU_GET_INFO_V2_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_NAME_STRING + * + * This command returns the name of the GPU in string form in either ASCII + * or UNICODE format. + * + * gpuNameStringFlags + * This field specifies flags to use while creating the GPU name string. + * Valid flags values: + * NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII + * The returned name string should be in standard ASCII format. + * NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE + * The returned name string should be in unicode format. + * gpuNameString + * This field contains the buffer into which the name string should be + * returned. The length of the returned string will be no more than + * NV2080_CTRL_GPU_MAX_NAME_STRING_LENGTH bytes in size. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV2080_CTRL_CMD_GPU_GET_NAME_STRING (0x20800110U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID" */ + +#define NV2080_GPU_MAX_NAME_STRING_LENGTH (0x0000040U) + +// This field is deprecated - 'gpuNameStringFlags' is now a simple scalar. +// Field maintained (and extended from 0:0) for compile-time compatibility. +#define NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE 31:0 + +/* valid gpu name string flags */ +#define NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII (0x00000000U) +#define NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE (0x00000001U) + +#define NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS { + NvU32 gpuNameStringFlags; + union { + NvU8 ascii[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + NvU16 unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + } gpuNameString; +} NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING + * + * This command returns the short name of the GPU in ASCII string form. + * + * gpuShortNameString + * This field contains the buffer into which the short name string should + * be returned. The length of the returned string will be no more than + * NV2080_MAX_NAME_STRING_LENGTH bytes in size. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ +#define NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING (0x20800111U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS { + NvU8 gpuShortNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH]; +} NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_SET_POWER + * + * This command sets the power state for the GPU as a whole, various engines, + * or clocks. + * + * target + * One of NV2080_CTRL_GPU_SET_POWER_TARGET_* + * + * newLevel + * One of NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_* + * NV2080_CTRL_GPU_SET_POWER_STATE_ENGINE_LEVEL_* + * NV2080_CTRL_GPU_SET_POWER_STATE_CLOCK_LEVEL_* + * depending on the target above. + * + * oldLevel + * Previous level as appropriate. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_GPU_SET_POWER (0x20800112U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV2080_CTRL_GPU_SET_POWER_PARAMS { + NvU32 target; + NvU32 newLevel; + NvU32 oldLevel; +} NV2080_CTRL_GPU_SET_POWER_PARAMS; + + + +#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_0 (0x00000000U) +#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_1 (0x00000001U) +#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_2 (0x00000002U) +#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3 (0x00000003U) +#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_4 (0x00000004U) +#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_7 (0x00000007U) + +/* + * NV2080_CTRL_CMD_GPU_GET_SDM + * + * This command returns the subdevice mask value for the associated subdevice. + * The subdevice mask value can be used with the SET_SUBDEVICE_MASK instruction + * provided by the NV36_CHANNEL_DMA and newer channel dma classes. + * + * subdeviceMask [out] + * This field return the subdevice mask value. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_GPU_GET_SDM (0x20800118U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV2080_CTRL_GPU_GET_SDM_PARAMS { + NvU32 subdeviceMask; +} NV2080_CTRL_GPU_GET_SDM_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_SET_SDM + * + * This command sets the subdevice instance and mask value for the associated subdevice. + * The subdevice mask value can be used with the SET_SUBDEVICE_MASK instruction + * provided by the NV36_CHANNEL_DMA and newer channel dma classes. + * It must be called before the GPU HW is initialized otherwise + * NV_ERR_INVALID_STATE is being returned. + * + * subdeviceMask [in] + * This field configures the subdevice mask value for the GPU/Subdevice + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_DATA + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_GPU_SET_SDM (0x20800120U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV2080_CTRL_GPU_SET_SDM_PARAMS { + NvU32 subdeviceMask; +} NV2080_CTRL_GPU_SET_SDM_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO + * + * This command returns the associated subdevices' simulation information. + * + * type + * This field returns the simulation type. + * One of NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_* + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO (0x20800119U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS { + NvU32 type; +} NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS; + +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_NONE (0x00000000U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_MODS_AMODEL (0x00000001U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_LIVE_AMODEL (0x00000002U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_FMODEL (0x00000003U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_RTL (0x00000004U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU (0x00000005U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU_LOW_POWER (0x00000006U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA (0x00000007U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_RTL (0x00000008U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_FMODEL (0x00000009U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_UNKNOWN (0xFFFFFFFFU) + +/* + * NV2080_CTRL_GPU_REG_OP + * + * This structure describes register operation information for use with + * the NV2080_CTRL_CMD_GPU_EXEC_REG_OPS command. The structure describes + * a single register operation. The operation can be a read or write and + * can involve either 32bits or 64bits of data. + * + * For 32bit read operations, the operation takes the following form: + * + * regValueLo = read(bar0 + regOffset) + * regValueHi = 0 + * + * For 64bit read operations, the operation takes the following form: + * + * regValueLo = read(bar0 + regOffset) + * regValueHi = read(bar0 + regOffset + 4) + * + * For 32bit write operations, the operation takes the following form: + * + * new = ((read(bar0 + regOffset) & ~regAndNMaskLo) | regValueLo) + * write(bar0 + regOffset, new) + * + * For 64bit write operations, the operation takes the following form: + * + * new_lo = ((read(bar0 + regOffset) & ~regAndNMaskLo) | regValueLo) + * new_hi = ((read(bar0 + regOffset + 4) & ~regAndNMaskHi) | regValueHi) + * write(bar0 + regOffset, new_lo) + * write(bar0 + regOffset + 4, new_hi) + * + * Details on the parameters follow: + * + * regOp + * This field specifies the operation to be applied to the register + * specified by the regOffset parameter. Valid values for this + * parameter are: + * NV2080_CTRL_GPU_REG_OP_READ_08 + * The register operation should be a 8bit global privileged register read. + * NV2080_CTRL_GPU_REG_OP_WRITE_08 + * The register operation should be a 8bit global privileged register write. + * NV2080_CTRL_GPU_REG_OP_READ_32 + * The register operation should be a 32bit register read. + * NV2080_CTRL_GPU_REG_OP_WRITE_32 + * The register operation should be a 32bit register write. + * NV2080_CTRL_GPU_REG_OP_READ_64 + * The register operation should be a 64bit register read. + * NV2080_CTRL_GPU_REG_OP_WRITE_64 + * The register operation should be a 64bit register write. + * regType + * This field specifies the type of the register specified by the + * regOffset parameter. Valid values for this parameter are: + * NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL + * The register is a global privileged register. Read operations + * return the current value from the associated global register. + * Write operations for registers of this type take effect immediately. + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX + * The register is a graphics context register. Read operations + * return the current value from the associated global register. + * Write operations are applied to all existing graphics engine + * contexts. Any newly created graphics engine contexts will also + * be modified. + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC + * This is a graphics context TPC register group. Write operations are + * applied to TPC group(s) specified by regGroupMask. + * This field is ignored for read operations. + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM + * This is a graphics context SM register group that is inside TPC + * group. Write operations are applied to SM group(s) specified by + * regGroupMask (TPC) and regSubGroupMask (SM). This field is ignored + * for read operations. + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP + * This is a graphics context CROP register group. Write operations + * are applied to registers specified by regGroupMask. This field is + * ignored for read operations. + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP + * This is a graphics context ZROP register group. Write operations + * are applied to registers specified by regGroupMask. This field is + * ignored for read operations. + * NV2080_CTRL_GPU_REG_OP_TYPE_FB + * This is a fb register group. Write operations are applied to + * registers specified by regGroupMask. This field is + * ignored for read operations. + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD + * This is a graphics context QUAD register group. Operations + * are applied to registers specified by regQuad value. + * regQuad + * This field specifies the quad to be accessed for register regOffsetwhen + * the regType specified is NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD. + * regGroupMask + * This field specifies which registers inside an array should be updated. + * This field is used when regType is one of below: + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP + * NV2080_CTRL_GPU_REG_OP_TYPE_FB + * When regGroupMask is used, the regOffset MUST be the first register in + * an array. + * regSubGroupMask + * This field specifies which registers inside a group should be updated. + * This field is used for updating SM registers when regType is: + * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC + * When regSubGroupMask is used, regOffset MUST be the first register in an + * array AND also the first one in sub array. regGroupMask specifies + * TPC(X) and regSubGroupMask specifies SM_CTX_N(Y) + * regStatus + * This field returns the completion status for the associated register + * operation in the form of a bitmask. Possible status values for this + * field are: + * NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS + * This value indicates the operation completed successfully. + * NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OP + * This bit value indicates that the regOp value is not valid. + * NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_TYPE + * This bit value indicates that the regType value is not valid. + * NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OFFSET + * This bit value indicates that the regOffset value is invalid. + * The regOffset value must be within the legal BAR0 range for the + * associated GPU and must target a supported register with a + * supported operation. + * NV2080_CTRL_GPU_REG_OP_STATUS_UNSUPPORTED_OFFSET + * This bit value indicates that the operation to the register + * specified by the regOffset value is not supported for the + * associated GPU. + * NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_MASK + * This bit value indicates that the regTpcMask value is invalid. + * The regTpcMask must be a subset of TPCs that are enabled on the + * associated GPU. + * NV2080_CTRL_GPU_REG_OP_STATUS_NOACCESS + * The caller does not have access to the register at given offset + * regOffset + * This field specifies the register offset to access. The specified + * offset must be a valid BAR0 offset for the associated GPU. + * regValueLo + * This field contains the low 32bits of the register value. + * For read operations, this value returns the current value of the + * register specified by regOffset. For write operations, this field + * specifies the logical OR value applied to the current value + * contained in the register specified by regOffset. + * regValueHi + * This field contains the high 32bits of the register value. + * For read operations, this value returns the current value of the + * register specified by regOffset + 4. For write operations, this field + * specifies the logical OR value applied to the current value + * contained in the register specified by regOffset + 4. + * regAndNMaskLo + * This field contains the mask used to clear a desired field from + * the current value contained in the register specified by regOffsetLo. + * This field is negated and ANDed to this current register value. + * This field is only used for write operations. This field is ignored + * for read operations. + * regAndNMaskHi + * This field contains the mask used to clear a desired field from + * the current value contained in the register specified by regOffsetHi. + * This field is negated and ANDed to this current register value. + * This field is only used for write operations. This field is ignored + * for read operations. + */ +typedef struct NV2080_CTRL_GPU_REG_OP { + NvU8 regOp; + NvU8 regType; + NvU8 regStatus; + NvU8 regQuad; + NvU32 regGroupMask; + NvU32 regSubGroupMask; + NvU32 regOffset; + NvU32 regValueHi; + NvU32 regValueLo; + NvU32 regAndNMaskHi; + NvU32 regAndNMaskLo; +} NV2080_CTRL_GPU_REG_OP; + +/* valid regOp values */ +#define NV2080_CTRL_GPU_REG_OP_READ_32 (0x00000000U) +#define NV2080_CTRL_GPU_REG_OP_WRITE_32 (0x00000001U) +#define NV2080_CTRL_GPU_REG_OP_READ_64 (0x00000002U) +#define NV2080_CTRL_GPU_REG_OP_WRITE_64 (0x00000003U) +#define NV2080_CTRL_GPU_REG_OP_READ_08 (0x00000004U) +#define NV2080_CTRL_GPU_REG_OP_WRITE_08 (0x00000005U) + +/* valid regType values */ +#define NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL (0x00000000U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX (0x00000001U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC (0x00000002U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM (0x00000004U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP (0x00000008U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP (0x00000010U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_FB (0x00000020U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD (0x00000040U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_DEVICE (0x00000080U) + +/* valid regStatus values (note: NvU8 ie, 1 byte) */ +#define NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS (0x00U) +#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OP (0x01U) +#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_TYPE (0x02U) +#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OFFSET (0x04U) +#define NV2080_CTRL_GPU_REG_OP_STATUS_UNSUPPORTED_OP (0x08U) +#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_MASK (0x10U) +#define NV2080_CTRL_GPU_REG_OP_STATUS_NOACCESS (0x20U) + +/* + * NV2080_CTRL_CMD_GPU_EXEC_REG_OPS + * + * This command is used to submit a buffer containing one or more + * NV2080_CTRL_GPU_REG_OP structures for processing. Each entry in the + * buffer specifies a single read or write operation. Each entry is checked + * for validity in an initial pass over the buffer with the results for + * each operation stored in the corresponding regStatus field. Unless + * bNonTransactional flag is set to true, if any invalid entries are found + * during this initial pass then none of the operations are executed. Entries + * are processed in order within each regType with NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL + * entries processed first followed by NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX entries. + * + * hClientTarget + * This parameter specifies the handle of the client that owns the channel + * specified by hChannelTarget. If this parameter is set to 0 then the set + * of channel-specific register operations are applied to all current and + * future channels. + * hChannelTarget + * This parameter specifies the handle of the target channel (or channel + * group) object instance to which channel-specific register operations are + * to be directed. If hClientTarget is set to 0 then this parameter must + * also be set to 0. + * bNonTransactional + * This field specifies if command is non-transactional i.e. if set to + * true, all the valid operations will be executed. + * reserved00 + * This parameter is reserved for future use. It should be initialized to + * zero for correct operation. + * regOpCount + * This field specifies the number of entries on the caller's regOps + * list. + * regOps + * This field specifies a pointer in the caller's address space + * to the buffer from which the desired register information is to be + * retrieved. This buffer must be at least as big as regInfoCount + * multiplied by the size of the NV2080_CTRL_GPU_REG_OP structure. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. When SMC is enabled, this + * is a mandatory parameter. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS (0x20800122U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x22" */ + +typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS { + NvHandle hClientTarget; + NvHandle hChannelTarget; + NvU32 bNonTransactional; + NvU32 reserved00[2]; + NvU32 regOpCount; + NV_DECLARE_ALIGNED(NvP64 regOps, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_ENGINES + * + * Returns a list of supported engine types along with the number of instances + * of each type. Querying with engineList NULL returns engineCount. + * + * engineCount + * This field specifies the number of entries on the caller's engineList + * field. + * engineList + * This field is a pointer to a buffer of NvU32 values representing the + * set of engines supported by the associated subdevice. Refer to cl2080.h + * for the complete set of supported engine types. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_GPU_GET_ENGINES (0x20800123U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID (0x23U) + +typedef struct NV2080_CTRL_GPU_GET_ENGINES_PARAMS { + NvU32 engineCount; + NV_DECLARE_ALIGNED(NvP64 engineList, 8); +} NV2080_CTRL_GPU_GET_ENGINES_PARAMS; + +#define NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 (0x20800170U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID" */ + +/* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */ +#define NV2080_GPU_MAX_ENGINES_LIST_SIZE 0x3EU + +#define NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID (0x70U) + +typedef struct NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS { + NvU32 engineCount; + NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; +} NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST + * + * Returns a list of classes supported by a given engine type. + * + * engineType + * This field specifies the engine type being queried. + * NV2080_CTRL_ENGINE_TYPE_ALLENGINES will return classes + * supported by all engines. + * + * numClasses + * This field specifies the number of classes supported by + * engineType. + * + * classList + * This field is an array containing the list of supported + * classes. Is of type (NvU32*) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST (0x20800124U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID (0x24U) + +typedef struct NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS { + NvU32 engineType; + NvU32 numClasses; + NV_DECLARE_ALIGNED(NvP64 classList, 8); +} NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS; + + +/* + * NV2080_CTRL_CMD_GPU_GET_ENGINE_FAULT_INFO + * + * This command returns the fault properties of the specified engine type. + * + * engineType + * Input parameter. + * This field specifies the engine type being queried. + * Engine type is specified using the NV2080_ENGINE_TYPE_* defines in cl2080.h. + * The list of engines supported by a chip can be got using the + * NV2080_CTRL_CMD_GPU_GET_ENGINES ctrl call. + * + * mmuFaultId + * Output parameter. + * This field returns the MMU fault ID for the specified engine. + * If the engine supports subcontext, this field provides the base fault id. + * + * bSubcontextSupported + * Output parameter. + * Returns TRUE if subcontext faulting is supported by the engine. + * Engine that support subcontext use fault IDs in the range [mmuFaultId, mmuFaultId + maxSubCtx). + * "maxSubctx" can be found using the NV2080_CTRL_FIFO_INFO ctrl call with + * NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP as the index. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_GPU_GET_ENGINE_FAULT_INFO (0x20800125U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID (0x25U) + +typedef struct NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS { + NvU32 engineType; + NvU32 mmuFaultId; + NvBool bSubcontextSupported; +} NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GPU_QUERY_MODE + * + * This command is used to detect the mode of the GPU associated with the + * subdevice. + * + * mode + * This parameter returns the current mode of GPU. Legal values for + * this parameter include: + * NV2080_CTRL_GPU_QUERY_MODE_GRAPHICS_MODE + * The GPU is currently operating in graphics mode. + * NV2080_CTRL_GPU_QUERY_MODE_COMPUTE_MODE + * The GPU is currently operating in compute mode. + * NV2080_CTRL_GPU_QUERY_MODE_UNKNOWN_MODE + * The current mode of the GPU could not be determined. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_GPU_QUERY_MODE (0x20800128U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_MODE_PARAMS_MESSAGE_ID" */ + +/* valid mode parameter values */ +#define NV2080_CTRL_GPU_QUERY_MODE_UNKNOWN_MODE (0x00000000U) +#define NV2080_CTRL_GPU_QUERY_MODE_GRAPHICS_MODE (0x00000001U) +#define NV2080_CTRL_GPU_QUERY_MODE_COMPUTE_MODE (0x00000002U) + +#define NV2080_CTRL_GPU_QUERY_MODE_PARAMS_MESSAGE_ID (0x28U) + +typedef struct NV2080_CTRL_GPU_QUERY_MODE_PARAMS { + NvU32 mode; +} NV2080_CTRL_GPU_QUERY_MODE_PARAMS; + + + +/*! + * NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY + * Data block describing a virtual context buffer to be promoted + * + * gpuPhysAddr [IN] + * GPU Physical Address for the buffer + * gpuVirtAddr [IN] + * GPU Virtual Address for the buffer + * size[IN] + * Size of this virtual context buffer + * physAttr [IN] + * Physical memory attributes (aperture, cacheable) + * bufferId [IN] + * Virtual context buffer type, data type NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_* + * bInitialize [IN] + * Flag indicating that this virtual context buffer should be initialized prior to promotion. + * The client must clear (memset) the buffer to 0x0 prior to initialization. + * Following buffers need initialization: + * 1. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN + * 2. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH + * 3. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP + * 4. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP + * bNonmapped [IN] + * Flag indicating that the virtual address is not to be promoted with this + * call. It is illegal to set this flag and not set bInitialize. + */ +typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY { + NV_DECLARE_ALIGNED(NvU64 gpuPhysAddr, 8); + NV_DECLARE_ALIGNED(NvU64 gpuVirtAddr, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 physAttr; + NvU16 bufferId; + NvU8 bInitialize; + NvU8 bNonmapped; +} NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY; + +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN 0U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM 1U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH 2U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_BUFFER_BUNDLE_CB 3U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PAGEPOOL 4U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_ATTRIBUTE_CB 5U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_RTV_CB_GLOBAL 6U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_POOL 7U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_CTRL_BLK 8U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_FECS_EVENT 9U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP 10U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP 11U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GLOBAL_PRIV_ACCESS_MAP 12U + +#define NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES 16U + +/* + * NV2080_CTRL_CMD_GPU_PROMOTE_CTX + * + * This command is used to promote a Virtual Context + * + * engineType + * Engine Virtual Context is for + * hClient + * Client Handle for hVirtMemory + * ChID + * Hw Channel -- Actually hw index for channel (deprecated) + * hChanClient + * The client handle for hObject + * hObject + * Passed in object handle for either a single channel or a channel group + * hVirtMemory + * Virtual Address handle to map Virtual Context to + * virtAddress + * Virtual Address to map Virtual Context to + * size + * size of the Virtual Context + * entryCount + * Number of valid entries in the promotion entry list + * promoteEntry + * List of context buffer entries to issue promotions for. + * + * When not using promoteEntry, only hVirtMemory or (virtAddress, size) should be + * specified, the code cases based on hVirtMemory(NULL vs non-NULL) so + * if both are specified, hVirtMemory has precedence. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED - The Class does not support version info retrieval + * NV_ERR_INVALID_DEVICE - The Class/Device is not yet ready to provide this info. + * NV_ERR_INVALID_ARGUMENT - Bad/Unknown Class ID specified. + */ +#define NV2080_CTRL_CMD_GPU_PROMOTE_CTX (0x2080012bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID (0x2BU) + +typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS { + NvU32 engineType; + NvHandle hClient; + NvU32 ChID; + NvHandle hChanClient; + NvHandle hObject; + NvHandle hVirtMemory; + NV_DECLARE_ALIGNED(NvU64 virtAddress, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 entryCount; + // C form: NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY promoteEntry[NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES]; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY promoteEntry[NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES], 8); +} NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS; +typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS *PNV2080_CTRL_GPU_PROMOTE_CTX_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_EVICT_CTX + * + * This command is used to evict a Virtual Context + * + * engineType + * Engine Virtual Context is for + * hClient + * Client Handle + * ChID + * Hw Channel -- Actually hw index for channel (deprecated) + * hChanClient + * Client handle for hObject + * hObject + * Passed in object handle for either a single channel or a channel group + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED - The Class does not support version info retrieval + * NV_ERR_INVALID_DEVICE - The Class/Device is not yet ready to provide this info. + * NV_ERR_INVALID_ARGUMENT - Bad/Unknown Class ID specified. + */ +#define NV2080_CTRL_CMD_GPU_EVICT_CTX (0x2080012cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID (0x2CU) + +typedef struct NV2080_CTRL_GPU_EVICT_CTX_PARAMS { + NvU32 engineType; + NvHandle hClient; + NvU32 ChID; + NvHandle hChanClient; + NvHandle hObject; +} NV2080_CTRL_GPU_EVICT_CTX_PARAMS; +typedef struct NV2080_CTRL_GPU_EVICT_CTX_PARAMS *PNV2080_CTRL_GPU_EVICT_CTX_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_INITIALIZE_CTX + * + * This command is used to initialize a Virtual Context. The ctx buffer must be + * cleared (zerod) by the caller prior to invoking this method. + * + * engineType + * Engine Virtual Context is for + * hClient + * Client Handle for the hVirtMemory + * ChID + * Hw channel -- Actually channel index (deprecated) + * hChanClient + * The client handle for hObject + * hObject + * Passed in object handle for either a single channel or a channel group + * hVirtMemory + * Virtual Address where to map Virtual Context to + * physAddress + * Physical offset in FB to use as Virtual Context + * physAttr + * Physical memory attributes + * hDmaHandle + * Dma Handle when using discontiguous context buffers + * index + * Start offset in Virtual DMA Context + * size + * Size of the Virtual Context + * + * Only hVirtMemory or size should be specified, the code cases based on hVirtMemory + * (NULL vs non-NULL) so if both are specified, hVirtMemory has precedence. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED - The Class does not support version info retrieval + * NV_ERR_INVALID_DEVICE - The Class/Device is not yet ready to provide this info. + * NV_ERR_INVALID_ARGUMENT - Bad/Unknown Class ID specified. + */ +#define NV2080_CTRL_CMD_GPU_INITIALIZE_CTX (0x2080012dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID (0x2DU) + +typedef struct NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS { + NvU32 engineType; + NvHandle hClient; + NvU32 ChID; + NvHandle hChanClient; + NvHandle hObject; + NvHandle hVirtMemory; + NV_DECLARE_ALIGNED(NvU64 physAddress, 8); + NvU32 physAttr; + NvHandle hDmaHandle; + NvU32 index; + NV_DECLARE_ALIGNED(NvU64 size, 8); +} NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS; +typedef struct NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS *PNV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS; + +#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE 1:0 +#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_VIDMEM (0x00000000U) +#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_COH_SYS (0x00000001U) +#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_NCOH_SYS (0x00000002U) + +#define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE 2:2 +#define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_YES (0x00000000U) +#define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_NO (0x00000001U) + +/* + * NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX - Tells RM Whether this Ctx buffer needs to + * do a full initialization (Load the golden image). When a context is promoted on a different + * channel than it was originally inited, the client can use this flag to tell RM + * that this is an already inited Context. In such cases RM will update the internal state + * to update the context address and state variables. + */ + +#define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX 3:3 +#define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_NO (0x00000000U) +#define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_YES (0x00000001U) + +/* + * NV2080_CTRL_CMD_CPU_QUERY_ECC_INTR + * Queries the top level ECC PMC PRI register + * TODO remove these parameters, tracked in bug #1975721 + */ +#define NV2080_CTRL_CMD_GPU_QUERY_ECC_INTR (0x2080012eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x2E" */ + +typedef struct NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS { + NvU32 eccIntrStatus; +} NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS; + +/** + * NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS + * + * This command is used to query the ECC status of a GPU by a subdevice + * handle. Please see the NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS + * data structure description below for details on the data reported + * per hardware unit. + * + * units + * Array of structures used to describe per-unit state + * + * flags + * See interface flag definitions below. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + + + +#define NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS (0x2080012fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID" */ + + +#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x00000018U) + + + +// Deprecated do not use +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE 0:0 +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_FILTERED (0x00000000U) +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_RAW (0x00000001U) + +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_FALSE 0U +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_TRUE 1U +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_INDETERMINATE 2U + +/* + * NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS + * + * This structure represents the exception status of a class of per-unit + * exceptions + * + * count + * number of exceptions that have occurred since boot + */ +typedef struct NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS { + NV_DECLARE_ALIGNED(NvU64 count, 8); +} NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS; + +/* + * NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS + * + * This structure represents the per-unit ECC exception status + * + * enabled + * ECC enabled yes/no for this unit + * scrubComplete + * Scrub has completed yes/no. A scrub is performed for some units to ensure + * the checkbits are consistent with the protected data. + * supported + * Whether HW supports ECC in this unit for this GPU + * dbe + * Double bit error (DBE) status. The value returned reflects a counter + * that is monotonic, but can be reset by clients. + * dbeNonResettable (deprecated do not use) + * Double bit error (DBE) status, not client resettable. + * sbe + * Single bit error (SBE) status. The value returned reflects a counter + * that is monotonic, but can be reset by clients. + * sbeNonResettable (deprecated do not use) + * Single bit error (SBE) status, not client resettable. + * + */ +typedef struct NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS { + NvBool enabled; + NvBool scrubComplete; + NvBool supported; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS dbe, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS dbeNonResettable, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS sbe, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS sbeNonResettable, 8); +} NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS; + +/* + * NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS + * + * This structure returns ECC exception status and GPU Fatal Poison for all units + * + * units + * This structure represents ECC exception status for all Units. + * bFatalPoisonError + * Whether GPU Fatal poison error occurred in this GPU. This will be set for Ampere_and_later + * uncorrectableError + * Indicates whether any uncorrectable GR ECC errors have occurred. When + * SMC is enabled, uncorrectableError is only valid when the client is + * subscribed to a partition. Check QUERY_ECC_STATUS_UNC_ERR_* + * flags + * Flags passed by caller. Refer NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_* for details. + * grRouteInfo + * SMC partition information. This input is only valid when SMC is + * enabled on Ampere_and_later. + * + */ +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID (0x2FU) + +typedef struct NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS units[NV2080_CTRL_GPU_ECC_UNIT_COUNT], 8); + NvBool bFatalPoisonError; + NvU8 uncorrectableError; + NvU32 flags; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES + * + * This command sets the compute mode rules for the associated subdevice. The + * default mode is equivalent to NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE. This + * command is available to clients with administrator privileges only. An + * attempt to use this command by a client without administrator privileged + * results in the return of an NV_ERR_INSUFFICIENT_PERMISSIONS status. + * + * rules + * This parameter is used to specify the rules that govern the GPU with + * respect to NV50_COMPUTE objects. Legal values for this parameter include: + * + * NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE + * This mode indicate that no special restrictions apply to the + * allocation of NV50_COMPUTE objects. + * + * NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE + * This mode means that only one instance of NV50_COMPUTE will be + * allowed at a time. This restriction is enforced at each subsequent + * NV50_COMPUTE allocation attempt. Setting this mode will not affect + * any existing compute programs that may be running. For example, + * if this mode is set while three compute programs are running, then + * all of those programs will be allowed to continue running. However, + * until they all finish running, no new NV50_COMPUTE objects may be + * allocated. User-mode clients should treat this as restricting access + * to a NV50_COMPUTE object to a single thread within a process. + * + * NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED + * This mode means that that GPU is not ever allowed to instantiate an + * NV50_COMPUTE object, and thus cannot run any new compute programs. + * This restriction is enforced at each subsequent NV50_COMPUTE object + * allocation attempt. Setting this mode will not affect any existing + * compute programs that may be running. For example, if this mode is + * set while three compute programs are running, then all of those + * programs will be allowed to continue running. However, no new + * NV50_COMPUTE objects may be allocated. + * + * + * NV2080_CTRL_GPU_COMPUTE_MODE_EXCLUSIVE_COMPUTE_PROCESS + * This mode is identical to EXCLUSIVE_COMPUTE, where only one instance + * of NV50_COMPUTE will be allowed at a time. It is separate from + * EXCLUSIVE_COMPUTE to allow user-mode clients to differentiate + * exclusive access to a compute object from a single thread of a + * process from exclusive access to a compute object from all threads + * of a process. User-mode clients should not limit access to a + * NV50_COMPUTE object to a single thread when the GPU is set to + * EXCLUSIVE_COMPUTE_PROCESS. + * + * An invalid rules parameter value results in the return of an + * NV_ERR_INVALID_ARGUMENT status. + * + * flags + * Reserved. Caller should set this field to zero. + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT (if an invalid rule number is provided) + * NV_ERR_INSUFFICIENT_PERMISSIONS (if the user is not the Administrator or superuser) + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES (0x20800130U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID" */ + +/* valid rules parameter values */ +#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE (0x00000000U) +#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE (0x00000001U) +#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED (0x00000002U) +#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE_PROCESS (0x00000003U) + +#define NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID (0x30U) + +typedef struct NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS { + NvU32 rules; + NvU32 flags; +} NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES + * + * This command queries the compute mode rules for the associated subdevice. + * Please see the NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES command, above, for + * details as to what the rules mean. + * + * rules + * Specifies the rules that govern the GPU, with respect to NV50_COMPUTE + * objects. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES (0x20800131U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID (0x31U) + +typedef struct NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS { + NvU32 rules; +} NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION + * + * This command returns the current ECC configuration setting for + * a GPU given its subdevice handle. The value returned is + * the current ECC setting for the GPU stored in non-volatile + * memory on the board. + * + * currentConfiguration + * The current ECC configuration setting. + * + * defaultConfiguration + * The factory default ECC configuration setting. + * + * Please see the NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS command if + * you wish to determine if ECC is currently enabled. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION (0x20800133U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLED (0x00000000U) +#define NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLED (0x00000001U) + +#define NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID (0x33U) + +typedef struct NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS { + NvU32 currentConfiguration; + NvU32 defaultConfiguration; +} NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_SET_ECC_CONFIGURATION + * + * This command changes the ECC configuration setting for a GPU + * given its subdevice handle. The value specified is + * stored in non-volatile memory on the board and will take + * effect with the next GPU reset + * + * newConfiguration + * The new configuration setting to take effect with + * the next GPU reset. + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_SET_ECC_CONFIGURATION (0x20800134U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLE (0x00000000U) +#define NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLE (0x00000001U) + +#define NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID (0x34U) + +typedef struct NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS { + NvU32 newConfiguration; +} NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS + * + * This command resets volatile and/or persistent ECC error + * status information for a GPU given its subdevice + * handle. + * + * statuses + * The ECC error statuses (the current, volatile + * and/or the persistent error counter(s)) to + * be reset by the command. + * flags + * FORCE_PURGE + * Forcibly clean all the ECC InfoROM state if this flag is set + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS (0x20800136U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_ECC_ERROR_STATUS_NONE (0x00000000U) +#define NV2080_CTRL_GPU_ECC_ERROR_STATUS_VOLATILE (0x00000001U) +#define NV2080_CTRL_GPU_ECC_ERROR_STATUS_AGGREGATE (0x00000002U) + +#define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE 0:0 +#define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_FALSE 0U +#define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_TRUE 1U + +#define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID (0x36U) + +typedef struct NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS { + NvU32 statuses; + NvU8 flags; +} NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_FERMI_GPC_INFO + * + * This command returns a mask of enabled GPCs for the associated GPU. + * + * gpcMask + * This parameter returns a mask of enabled GPCs. Each GPC has an ID + * that's equivalent to the corresponding bit position in the mask. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_GPU_GET_FERMI_GPC_INFO (0x20800137U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID (0x37U) + +typedef struct NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS { + NvU32 gpcMask; +} NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_FERMI_TPC_INFO + * + * This command returns a mask of enabled TPCs for a specified GPC. + * + * gpcId + * This parameter specifies the GPC for which TPC information is + * to be retrieved. If the GPC with this ID is not enabled this command + * will return an tpcMask value of zero. + * + * tpcMask + * This parameter returns a mask of enabled TPCs for the specified GPC. + * Each TPC has an ID that's equivalent to the corresponding bit + * position in the mask. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_GPU_GET_FERMI_TPC_INFO (0x20800138U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID (0x38U) + +typedef struct NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS { + NvU32 gpcId; + NvU32 tpcMask; +} NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_FERMI_ZCULL_INFO + * + * This command returns a mask of enabled ZCULLs for a specified GPC. + * + * gpcId + * This parameter specifies the GPC for which ZCULL information is to be + * retrieved. If the GPC with this ID is not enabled this command will + * return an zcullMask value of zero. + * + * zcullMask + * This parameter returns a mask of enabled ZCULLs for the specified GPC. + * Each ZCULL has an ID that's equivalent to the corresponding bit + * position in the mask. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_PARAM_STRUCT + * + * Deprecated: Please use GR based control call + * NV2080_CTRL_CMD_GR_GET_ZCULL_MASK + * + */ +#define NV2080_CTRL_CMD_GPU_GET_FERMI_ZCULL_INFO (0x20800139U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID (0x39U) + +typedef struct NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS { + NvU32 gpcId; + NvU32 zcullMask; +} NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO + * + * If an InfoROM with a valid OEM Board Object is present, this + * command returns relevant information from the object to the + * caller. + * + * The following data are currently reported: + * + * buildDate + * The board's build date (8 digit BCD in format YYYYMMDD). + * + * marketingName + * The board's marketing name (24 ASCII letters e.g. "Quadro FX5800"). + * + * boardSerialNumber + * The board's serial number. + * + * memoryManufacturer + * The board's memory manufacturer ('S'amsung/'H'ynix/'I'nfineon). + * + * memoryDateCode + * The board's memory datecode (LSB justified ASCII field with 0x00 + * denoting empty space). + * + * productPartNumber + * The board's 900 product part number (LSB justified ASCII field with 0x00 + * denoting empty space e.g. "900-21228-0208-200"). + * + * boardRevision + * The board's revision (for e.g. A02, B01) + * + * boardType + * The board's type ('E'ngineering/'P'roduction) + * + * board699PartNumber + * The board's 699 product part number (LSB justified ASCII field with 0x00 + * denoting empty space e.g. "699-21228-0208-200"). + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO (0x2080013fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_GPU_MAX_MARKETING_NAME_LENGTH (0x00000018U) +#define NV2080_GPU_MAX_SERIAL_NUMBER_LENGTH (0x00000010U) +#define NV2080_GPU_MAX_MEMORY_PART_ID_LENGTH (0x00000014U) +#define NV2080_GPU_MAX_MEMORY_DATE_CODE_LENGTH (0x00000006U) +#define NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH (0x00000014U) + +#define NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID (0x3FU) + +typedef struct NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS { + NvU32 buildDate; + NvU8 marketingName[NV2080_GPU_MAX_MARKETING_NAME_LENGTH]; + NvU8 serialNumber[NV2080_GPU_MAX_SERIAL_NUMBER_LENGTH]; + NvU8 memoryManufacturer; + NvU8 memoryPartID[NV2080_GPU_MAX_MEMORY_PART_ID_LENGTH]; + NvU8 memoryDateCode[NV2080_GPU_MAX_MEMORY_DATE_CODE_LENGTH]; + NvU8 productPartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH]; + NvU8 boardRevision[3]; + NvU8 boardType; + NvU8 board699PartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH]; +} NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GPU_GET_ID + * + * This command returns the gpuId of the associated object. + * + * gpuId + * This field return the gpuId. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_ID (0x20800142U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID (0x42U) + +typedef struct NV2080_CTRL_GPU_GET_ID_PARAMS { + NvU32 gpuId; +} NV2080_CTRL_GPU_GET_ID_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE + * + * This command is used to enable or disable GPU debug mode. While this mode + * is enabled, some client RM calls that can potentially timeout return + * NV_ERR_BUSY_RETRY, signalling the client to try again once GPU + * debug mode is disabled. + * + * mode + * This parameter specifies whether GPU debug mode is to be enabled or + * disabled. Possible values are: + * + * NV2080_CTRL_GPU_DEBUG_MODE_ENABLED + * NV2080_CTRL_GPU_DEBUG_MODE_DISABLED + * + * Possible return status values are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE (0x20800143U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID (0x43U) + +typedef struct NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS { + NvU32 mode; +} NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS; + +#define NV2080_CTRL_GPU_DEBUG_MODE_ENABLED (0x00000001U) +#define NV2080_CTRL_GPU_DEBUG_MODE_DISABLED (0x00000002U) + +/* + * NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE + * + * This command is used to query whether debug mode is enabled on the current + * GPU. Please see the description of NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE + * for more details on GPU debug mode. + * + * currentMode + * This parameter returns the state of GPU debug mode for the current GPU. + * Possible values are: + * + * NV2080_CTRL_GPU_DEBUG_MODE_ENABLED + * NV2080_CTRL_GPU_DEBUG_MODE_DISABLED + * + * Possible return status values are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE (0x20800144U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID (0x44U) + +typedef struct NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS { + NvU32 currentMode; +} NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST + * + * Returns a list of engines that can partner or coexist + * when using the target channel or partnership class. + * This list may include all engines (pre-Kepler), or as few + * as 1 engine (Kepler and beyond). + * + * engineType + * This field specifies the target engine type. + * See cl2080.h for a list of valid engines. + * + * partnershipClassId + * This field specifies the target channel + * or partnership class ID. + * An example of such a class is GF100_CHANNEL_GPFIFO. + * + * runqueue + * This field is an index which indicates the runqueue to + * return the list of supported engines for. This is the + * same field as what NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE + * specifies. This is only valid for TSG. + * + * numPartners; + * This field returns the number of + * valid entries in the partnersList array + * + * partnerList + * This field is an array containing the list of supported + * partner engines types, in no particular order, and + * may even be empty (numPartners = 0). + * See cl2080.h for a list of possible engines. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST (0x20800147U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID" */ + +/* this macro specifies the maximum number of partner entries */ +#define NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS (0x00000020U) + +#define NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID (0x47U) + +typedef struct NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS { + NvU32 engineType; + NvU32 partnershipClassId; + NvU32 runqueue; + NvU32 numPartners; + // C form: NvU32 partnerList[NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS]; + NvU32 partnerList[NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS]; +} NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GPU_GET_GID_INFO + * + * This command returns the GPU ID (GID) string for the associated + * GPU. This value can be useful for GPU identification and security + * system validation. + * + * The GPU ID is a SHA-1 based 16 byte ID, formatted as a 32 character + * hexadecimal string as "GPU-%08x-%04x-%04x-%04x-%012x" (the + * canonical format of a UUID) + * + * The GPU IDs are generated using the ECID, PMC_BOOT_0, and + * PMC_BOOT_42 of the GPU as the hash message. + * + * index + * (Input) "Select which GID set to get." Or so the original documentation + * said. In reality, there is only one GID per GPU, and the implementation + * completely ignores this parameter. You can too. + * + * flags (Input) The _FORMAT* flags designate ascii or binary format. Binary + * format returns the raw bytes of either the 16-byte SHA-1 ID or the + * 32-byte SHA-256 ID. + * + * The _TYPE* flags needs to specify the _SHA1 type. + * + * length + * (Output) Actual GID length, in bytes. + * + * data[NV2080_BUS_MAX_GID_LENGTH] + * (Output) Result buffer: the GID itself, in a format that is determined by + * the "flags" field (described above). + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_GPU_GET_GID_INFO (0x2080014aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID" */ + +/* maximum possible number of bytes of GID information returned */ +#define NV2080_GPU_MAX_GID_LENGTH (0x000000100ULL) + +/* maximum possible number of bytes of GID information returned if given the BINARY and SHA1 flags */ +#define NV2080_GPU_MAX_SHA1_BINARY_GID_LENGTH (0x000000010ULL) + +#define NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID (0x4AU) + +typedef struct NV2080_CTRL_GPU_GET_GID_INFO_PARAMS { + NvU32 index; + NvU32 flags; + NvU32 length; + NvU8 data[NV2080_GPU_MAX_GID_LENGTH]; +} NV2080_CTRL_GPU_GET_GID_INFO_PARAMS; + +/* valid flags values */ +#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT 1:0 +#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_ASCII (0x00000000U) +#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_BINARY (0x00000002U) + +#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE 2:2 +#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE_SHA1 (0x00000000U) + +/* + * NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION + * + * This command can be used by clients to retrieve the version of an + * InfoROM object. + * + * objectType + * This parameter specifies the name of the InfoROM object whose version + * should be queried. + * + * version + * This parameter returns the version of the InfoROM object specified by + * the objectType parameter. + * + * subversion + * This parameter returns the subversion of the InfoROM object specified + * by the objectType parameter. + * + * Possible return status values: + * NV_OK + * NV_ERR_STATE_IN_USE + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION (0x2080014bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_INFOROM_OBJ_TYPE_LEN 3U + +#define NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID (0x4BU) + +typedef struct NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS { + char objectType[NV2080_CTRL_GPU_INFOROM_OBJ_TYPE_LEN]; + NvU8 version; + NvU8 subversion; +} NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS; + + +/* + * NV2080_CTRL_CMD_SET_GPU_OPTIMUS_INFO + * + * This command will specify that system is Optimus enabled. + * + * isOptimusEnabled + * Set NV_TRUE if system is Optimus enabled. + * + * Possible status return values are: + * NV_OK + */ +#define NV2080_CTRL_CMD_SET_GPU_OPTIMUS_INFO (0x2080014cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID (0x4CU) + +typedef struct NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS { + NvBool isOptimusEnabled; +} NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_IP_VERSION + * + * Will return the IP VERSION on the given engine for engines that support + * this capability. + * + * targetEngine + * This parameter specifies the target engine type to query for IP_VERSION. + * + * ipVersion + * This parameter returns the IP VERSION read from the unit's IP_VER + * register. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_GPU_GET_IP_VERSION (0x2080014dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID (0x4DU) + +typedef struct NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS { + NvU32 targetEngine; + NvU32 ipVersion; +} NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS; + +#define NV2080_CTRL_GPU_GET_IP_VERSION_DISPLAY (0x00000001U) +#define NV2080_CTRL_GPU_GET_IP_VERSION_HDACODEC (0x00000002U) +#define NV2080_CTRL_GPU_GET_IP_VERSION_PMGR (0x00000003U) +#define NV2080_CTRL_GPU_GET_IP_VERSION_PPWR_PMU (0x00000004U) +#define NV2080_CTRL_GPU_GET_IP_VERSION_DISP_FALCON (0x00000005U) + + + +/* + * NV2080_CTRL_CMD_GPU_ID_ILLUM_SUPPORT + * + * This command returns an indicator which reports if the specified Illumination control + * attribute is supported + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_GPU_ILLUM_ATTRIB_LOGO_BRIGHTNESS 0U +#define NV2080_CTRL_GPU_ILLUM_ATTRIB_SLI_BRIGHTNESS 1U +#define NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT (0x20800153U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID (0x53U) + +typedef struct NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS { + NvU32 attribute; + NvBool bSupported; +} NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_ID_ILLUM + * + * This command returns the current value of the specified Illumination control attribute. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_ILLUM (0x20800154U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x54" */ + +typedef struct NV2080_CTRL_CMD_GPU_ILLUM_PARAMS { + NvU32 attribute; + NvU32 value; +} NV2080_CTRL_CMD_GPU_ILLUM_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_SET_ID_ILLUM + * + * This command sets a new valuefor the specified Illumination control attribute. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_SET_ILLUM (0x20800155U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x55" */ + +/* + * NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION + * + * This command can be used by clients to retrieve the version of the entire + * InfoROM image. + * + * version + * This parameter returns the version of the InfoROM image as a NULL- + * terminated character string of the form "XXXX.XXXX.XX.XX" where each + * 'X' is an integer character. + * + * Possible status return values are: + * NVOS_STATUS_SUCCES + * NV_ERR_INSUFFICIENT_RESOURCES + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_DATA + */ +#define NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION (0x20800156U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_INFOROM_IMAGE_VERSION_LEN 16U + +#define NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID (0x56U) + +typedef struct NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS { + NvU8 version[NV2080_CTRL_GPU_INFOROM_IMAGE_VERSION_LEN]; +} NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT + * + * This command returns whether or not ECC is supported via the InfoROM. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT (0x20800157U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x57" */ + +/* + * NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION + * + * This structure contains information about a single physical bridge. + * + * fwVersion + * This field specifies Firmware Version of the bridge stored in + * bridge EEPROM. + * oemVersion + * This field specifies Oem Version of the firmware stored in + * bridge EEPROM. + * siliconRevision + * This field contains the silicon revision of the bridge hardware. + * It is set by the chip manufacturer. + * hwbcResourceType + * This field specifies the hardware broadcast resource type. + * Value denotes the kind of bridge - PLX or BR04 + * + */ + +typedef struct NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS { + NvU32 fwVersion; + NvU8 oemVersion; + NvU8 siliconRevision; + NvU8 hwbcResourceType; +} NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO + * + * This command returns physical bridge information in the system. + * Information consists of bridgeCount and a list of bridgeId's. + * The bridge Id's are used by NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION + * to get firmware version, oem version and silicon revision info. + * + * bridgeCount + * This field specifies the number of physical brides present + * in the system. + * hPhysicalBridges + * This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE. + * In this array, the bridge Id's are stored. + * bridgeList + * This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE. + * In this array, the bridge version details are stored. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO (0x2080015aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MAX_PHYSICAL_BRIDGE (100U) +#define NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID (0x5AU) + +typedef struct NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS { + NvU8 bridgeCount; + NvHandle hPhysicalBridges[NV2080_CTRL_MAX_PHYSICAL_BRIDGE]; + NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS bridgeList[NV2080_CTRL_MAX_PHYSICAL_BRIDGE]; +} NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS; + +/* + * NV2080_CTRL_GPU_BRIDGE_VERSION + * + * This structure contains information about a single physical bridge. + * + * bus + * This field specifies the bus id of the bridge. + * device + * This field specifies the device id of the bridge. + * func + * This field specifies the function id of the bridge. + * oemVersion + * This field specifies Oem Version of the firmware stored in + * bridge EEPROM. + * siliconRevision + * This field contains the silicon revision of the bridge hardware. + * It is set by the chip manufacturer. + * hwbcResourceType + * This field specifies the hardware broadcast resource type. + * Value denotes the kind of bridge - PLX or BR04 + * domain + * This field specifies the respective domain of the PCI device. + * fwVersion + * This field specifies Firmware Version of the bridge stored in + * bridge EEPROM. + * + * If (fwVersion, oemVersion, siliconRevision) == 0, it would mean that RM + * was unable to fetch the value from the bridge device. + * + */ + +typedef struct NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS { + NvU8 bus; + NvU8 device; + NvU8 func; + NvU8 oemVersion; + NvU8 siliconRevision; + NvU8 hwbcResourceType; + NvU32 domain; + NvU32 fwVersion; +} NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU + * + * This command returns information about all the upstream bridges of the GPU. + * Information consists of bridge firmware version and its bus topology. + * + * bridgeCount + * This field specifies the number of physical brides present + * in the system. + * physicalBridgeIds + * This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE. + * In this array, the bridge Ids are stored. + * bridgeList + * This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE. + * In this array, the bridge version details are stored. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU (0x2080015bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID (0x5BU) + +typedef struct NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS { + NvU8 bridgeCount; + NvU32 physicalBridgeIds[NV2080_CTRL_MAX_PHYSICAL_BRIDGE]; + NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS bridgeList[NV2080_CTRL_MAX_PHYSICAL_BRIDGE]; +} NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS + * + * This command is used to query the status of the HW scrubber. If a scrub is + * in progress then the range which is being scrubbed is also reported back. + * + * scrubberStatus + * Reports the status of the scrubber unit - running/idle. + * + * remainingtimeMs + * If scrubbing is going on, reports the remaining time in milliseconds + * required to finish the scrub. + * + * scrubStartAddr + * This parameter reports the start address of the ongoing scrub if scrub + * is going on, otherwise reports the start addr of the last finished scrub + * + * scrubEndAddr + * This parameter reports the end address of the ongoing scrub if scrub + * is going on, otherwise reports the end addr of the last finished scrub. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS (0x2080015fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID (0x5FU) + +typedef struct NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS { + NvU32 scrubberStatus; + NvU32 remainingTimeMs; + NV_DECLARE_ALIGNED(NvU64 scrubStartAddr, 8); + NV_DECLARE_ALIGNED(NvU64 scrubEndAddr, 8); +} NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS; + +/* valid values for scrubber status */ +#define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_RUNNING (0x00000000U) +#define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_IDLE (0x00000001U) + +/* + * NV2080_CTRL_CMD_GPU_GET_VPR_CAPS + * + * This command is used to query the VPR capability information for a + * GPU. If VPR is supported, the parameters are filled accordingly. + * The addresses returned are all physical addresses. + * + * minStartAddr + * Returns the minimum start address that can be possible for VPR. + * + * maxEndAddr + * Returns the maximum end address that can be possible for VPR. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_GPU_GET_VPR_CAPS (0x20800160U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID (0x60U) + +typedef struct NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 minStartAddr, 8); + NV_DECLARE_ALIGNED(NvU64 maxEndAddr, 8); +} NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GPU_HANDLE_GPU_SR + * + * Communicates to RM to handle GPU Surprise Removal + * Called from client when it receives SR IRP from OS + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + */ +#define NV2080_CTRL_CMD_GPU_HANDLE_GPU_SR (0x20800167U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x67" */ + + +/* + * NV2080_CTRL_CMD_GPU_GET_PES_INFO + * + * This command provides the PES count and mask of enabled PES for a + * specified GPC. It also returns the TPC to PES mapping information + * for a given GPU. + * + * gpcId[IN] + * This parameter specifies the GPC for which PES information is to be + * retrieved. If the GPC with this ID is not enabled this command will + * return an activePesMask of zero + * + * numPesInGpc[OUT] + * This parameter returns the number of PES in this GPC. + * + * activePesMask[OUT] + * This parameter returns a mask of enabled PESs for the specified GPC. + * Each PES has an ID that is equivalent to the corresponding bit position + * in the mask. + * + * maxTpcPerGpcCount[OUT] + * This parameter returns the max number of TPCs in a GPC. + * + * tpcToPesMap[OUT] + * This array stores the TPC to PES mappings. The value at tpcToPesMap[tpcIndex] + * is the index of the PES it belongs to. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_PES_INFO (0x20800168U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_GPU_GET_PES_INFO_MAX_TPC_PER_GPC_COUNT 10U + +#define NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID (0x68U) + +typedef struct NV2080_CTRL_GPU_GET_PES_INFO_PARAMS { + NvU32 gpcId; + NvU32 numPesInGpc; + NvU32 activePesMask; + NvU32 maxTpcPerGpcCount; + NvU32 tpcToPesMap[NV2080_CTRL_CMD_GPU_GET_PES_INFO_MAX_TPC_PER_GPC_COUNT]; +} NV2080_CTRL_GPU_GET_PES_INFO_PARAMS; + +/* NV2080_CTRL_CMD_GPU_GET_OEM_INFO + * + * If an InfoROM with a valid OEM Object is present, this + * command returns relevant information from the object to the + * caller. + * + * oemInfo + * This array stores information specifically for OEM use + * (e.g. "their own serial number", "lot codes", etc) + * "The byte definition is up to the OEM" + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_GPU_GET_OEM_INFO (0x20800169U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_GPU_MAX_OEM_INFO_LENGTH (0x000001F8U) + +#define NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID (0x69U) + +typedef struct NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS { + NvU8 oemInfo[NV2080_GPU_MAX_OEM_INFO_LENGTH]; +} NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS; + +/* NV2080_CTRL_CMD_GPU_PROCESS_POST_GC6_EXIT_TASKS + * + * Complete any pending tasks the need to be run after GC6 exit is complete at OS/KMD level + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_READY + */ +#define NV2080_CTRL_CMD_GPU_PROCESS_POST_GC6_EXIT_TASKS (0x2080016aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x6A" */ + +/* + * NV2080_CTRL_CMD_GPU_GET_VPR_INFO + * + * This command is used to query the VPR information for a GPU. + * The following VPR related information can be queried by selecting the queryType: + * 1. The current VPR range. + * 2. The max VPR range ever possible on this GPU. + * + * queryType [in] + * This input parameter is used to select the type of information to query. + * Possible values for this parameter are: + * 1. NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS: Use this to query the + * max VPR range ever possible on this GPU. + * 2. NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE: Use this to query + * the current VPR range on this GPU. + * + * bVprEnabled [out] + * For query type "NV2080_CTRL_GPU_GET_VPR_INFO_CUR_RANGE", this parameter + * returns if VPR is currently enabled or not. + * + * vprStartAddress [out] + * For NV2080_CTRL_GPU_GET_VPR_INFO_CAPS, it returns minimum allowed VPR start address. + * For NV2080_CTRL_GPU_GET_VPR_INFO_RANGE, it returns current VPR start address. + * + * vprEndAddress [out] + * For NV2080_CTRL_GPU_GET_VPR_INFO_CAPS, it returns maximum allowed VPR end address. + * For NV2080_CTRL_GPU_GET_VPR_INFO_RANGE, it returns current VPR end address. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_VPR_INFO (0x2080016bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID" */ + + +typedef enum NV2080_CTRL_VPR_INFO_QUERY_TYPE { + NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS = 0, + NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE = 1, +} NV2080_CTRL_VPR_INFO_QUERY_TYPE; + +#define NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID (0x6BU) + +typedef struct NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS { + NV2080_CTRL_VPR_INFO_QUERY_TYPE queryType; + NvBool bIsVprEnabled; + NV_DECLARE_ALIGNED(NvU64 vprStartAddressInBytes, 8); + NV_DECLARE_ALIGNED(NvU64 vprEndAddressInBytes, 8); +} NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_ENCODER_CAPACITY + * + * This command is used to query the encoder capacity of the GPU. + * + * queryType [in] + * This input parameter is used to select the type of information to query. + * Possible values for this parameter are: + * 1. NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264: Use this to query the + * H.264 encoding capacity on this GPU. + * 2. NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC: Use this to query the + * H.265/HEVC encoding capacity on this GPU. + * + * encoderCapacity [out] + * Encoder capacity value from 0 to 100. Value of 0x00 indicates encoder performance + * may be minimal for this GPU and software should fall back to CPU-based encode. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_GPU_GET_ENCODER_CAPACITY (0x2080016cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE { + NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264 = 0, + NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC = 1, +} NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE; + +#define NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID (0x6CU) + +typedef struct NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS { + NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE queryType; + NvU32 encoderCapacity; +} NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS; + +/* + * NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS + * + * This command is used to retrieve the GPU's count of encoder sessions, + * trailing average FPS and encode latency over all active sessions. + * + * encoderSessionCount + * This field specifies count of all active encoder sessions on this GPU. + * + * averageEncodeFps + * This field specifies the average encode FPS for this GPU. + * + * averageEncodeLatency + * This field specifies the average encode latency in microseconds for this GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS (0x2080016dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID (0x6DU) + +typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS { + NvU32 encoderSessionCount; + NvU32 averageEncodeFps; + NvU32 averageEncodeLatency; +} NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS; + +#define NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES 0x200U // 512 entries. + +/* + * NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO + * + * This command returns NVENC software sessions information for the associate GPU. + * Request to retrieve session information use a list of one or more + * NV2080_CTRL_NVENC_SW_SESSION_INFO structures. + * + * sessionInfoTblEntry + * This field specifies the number of entries on the that are filled inside + * sessionInfoTbl. Max value of this field once returned from RM would be + * NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES, + * + * sessionInfoTbl + * This field specifies a pointer in the caller's address space + * to the buffer into which the NVENC session information is to be returned. + * When buffer is NULL, RM assume that client is querying sessions count value + * and return the current encoder session counts in sessionInfoTblEntry field. + * To get actual buffer data, client should allocate sessionInfoTbl of size + * NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES multiplied by the + * size of the NV2080_CTRL_NVENC_SW_SESSION_INFO structure. RM will fill the + * current session data in sessionInfoTbl buffer and then update the + * sessionInfoTblEntry to reflect current session count value. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NO_MEMORY + * NV_ERR_INVALID_LOCK_STATE + * NV_ERR_INVALID_ARGUMENT + */ + +typedef struct NV2080_CTRL_NVENC_SW_SESSION_INFO { + NvU32 processId; + NvU32 subProcessId; + NvU32 sessionId; + NvU32 codecType; + NvU32 hResolution; + NvU32 vResolution; + NvU32 averageEncodeFps; + NvU32 averageEncodeLatency; +} NV2080_CTRL_NVENC_SW_SESSION_INFO; + +#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS_MESSAGE_ID (0x6EU) + +typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS { + NvU32 sessionInfoTblEntry; + NV_DECLARE_ALIGNED(NvP64 sessionInfoTbl, 8); +} NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS; + +#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO (0x2080016eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR + * + * The command sets fabric base address which represents top N bits of a + * peer memory address. These N bits will be used to index NvSwitch routing + * tables to forward peer memory accesses to associated GPUs. + * + * The command is available to clients with administrator privileges only. + * An attempt to use this command by a client without administrator privileged + * results in the return of NV_ERR_INSUFFICIENT_PERMISSIONS status. + * + * The command allows to set fabricAddr once in a lifetime of a GPU. A GPU must + * be destroyed in order to re-assign a different fabricAddr. An attempt to + * re-assign address without destroying a GPU would result in the return of + * NV_ERR_STATE_IN_USE status. + * + * fabricBaseAddr[IN] + * - An address with at least 32GB alignment. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_NOT_SUPPORTED + * NV_ERR_STATE_IN_USE + */ + +#define NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID (0x6FU) + +typedef struct NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS { + NV_DECLARE_ALIGNED(NvU64 fabricBaseAddr, 8); +} NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS; + +#define NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR (0x2080016fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT + * + * The command will trigger the specified interrupt on the host from a guest. + * + * handle[IN] + * - An opaque handle that will be passed in along with the interrupt + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS_MESSAGE_ID (0x72U) + +typedef struct NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS { + NvU32 handle; +} NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS; + +#define NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT (0x20800172U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS + * + * This control call is to query the status of gpu function registers + * + * statusMask[IN] + * - Input mask of required status registers + * xusbData[OUT] + * - data from querying XUSB status register + * ppcData[OUT] + * - data from querying PPC status register + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + + + +#define NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS_MESSAGE_ID (0x73U) + +typedef struct NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS { + NvU32 statusMask; + NvU32 xusbData; + NvU32 ppcData; +} NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS; + +#define NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS (0x20800173U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_GPU_PARTITION_SPAN + * + * This struct represents the span of a memory partition, which represents the + * slices a given partition occupies (or may occupy) within a fixed range which + * is defined per-chip. A partition containing more resources will cover more + * GPU slices and therefore cover a larger span. + * + * lo + * - The starting unit of this span, inclusive + * + * hi + * - The ending unit of this span, inclusive + * + */ +typedef struct NV2080_CTRL_GPU_PARTITION_SPAN { + NV_DECLARE_ALIGNED(NvU64 lo, 8); + NV_DECLARE_ALIGNED(NvU64 hi, 8); +} NV2080_CTRL_GPU_PARTITION_SPAN; + +/* + * NV2080_CTRL_GPU_SET_PARTITION_INFO + * + * This command partitions a GPU into different SMC-Memory partitions. + * The command will configure HW partition table to create work and memory + * isolation. + * + * The command is available to clients with administrator privileges only. + * An attempt to use this command by a client without administrator privileged + * results in the return of NV_ERR_INSUFFICIENT_PERMISSIONS status. + * + * The command allows partitioning an invalid partition only. An attempt to + * re-partition a valid partition will resule in NV_ERR_STATE_IN_USE. + * Repartitioning can be done only if a partition has been destroyed/invalidated + * before re-partitioning. + * + * swizzId[IN/OUT] + * - PartitionID associated with a newly created partition. Input in case + * of partition invalidation. + * + * partitionFlag[IN] + * - Flags to determine if GPU is requested to be partitioned in FULL, + * HALF, QUARTER or ONE_EIGHTHED and whether the partition requires + * any additional resources. + * When flags include NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA + * partition will be created with at least one video decode, jpeg and + * optical flow engines. This flag is valid only for partitions with + * a single GPC. + * + * bValid[IN] + * - NV_TRUE if creating a partition. NV_FALSE if destroying a partition. + * + * placement[IN] + * - Optional placement span to allocate the partition into. Valid + * placements are returned from NV2080_CTRL_CMD_GPU_GET_PARTITION_CAPACITY. + * The partition flag NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN must + * be set for this parameter to be used. If the flag is set and the given + * placement is not valid, an error will be returned. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_NOT_SUPPORTED + * NV_ERR_STATE_IN_USE + */ +typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO { + NvU32 swizzId; + NvU32 partitionFlag; + NvBool bValid; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN placement, 8); +} NV2080_CTRL_GPU_SET_PARTITION_INFO; + +#define PARTITIONID_INVALID NV2080_CTRL_GPU_PARTITION_ID_INVALID +#define NV2080_CTRL_GPU_PARTITION_ID_INVALID 0xFFFFFFFFU +#define NV2080_CTRL_GPU_MAX_PARTITIONS 0x00000008U +#define NV2080_CTRL_GPU_MAX_PARTITION_IDS 0x00000009U +#define NV2080_CTRL_GPU_MAX_SMC_IDS 0x00000008U +#define NV2080_CTRL_GPU_MAX_GPC_PER_SMC 0x0000000cU +#define NV2080_CTRL_GPU_MAX_CE_PER_SMC 0x00000008U + +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE 1:0 +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL 0x00000000U +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF 0x00000001U +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER 0x00000002U +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH 0x00000003U +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE 4U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE 4:2 +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL 0x00000000U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF 0x00000001U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF 0x00000002U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER 0x00000003U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER 0x00000004U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH 0x00000005U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE 6U + + +#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 8U +#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA 30:30 +#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE 0U +#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE 1U +#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN 31:31 +#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE 0U +#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE 1U + +// TODO XXX Bug 2657907 Remove these once clients update +#define NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _FULL) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _FULL)) +#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _HALF) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _HALF)) +#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _HALF) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _MINI_HALF)) +#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _QUARTER) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _QUARTER)) +#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _EIGHTH) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _EIGHTH)) + +#define NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID (0x74U) + +typedef struct NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS { + NvU32 partitionCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_SET_PARTITION_INFO partitionInfo[NV2080_CTRL_GPU_MAX_PARTITIONS], 8); +} NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS; + +#define NV2080_CTRL_CMD_GPU_SET_PARTITIONS (0x20800174U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_GPU_GET_PARTITION_INFO + * + * This command gets the partition information for requested partitions. + * If GPU is not partitioned, the control call will return NV_ERR_NOT_SUPPORTED. + * + * The command will can return global partition information as well as single + * partition information if global flag is not set. + * In bare-metal user-mode can request all partition info while in virtualization + * plugin should make an RPC with swizzId which is assigned to the requesting + * VM. + * + * swizzId[IN] + * - HW Partition ID associated with the requested partition. + * + * partitionFlag[OUT] + * - partitionFlag that was provided during partition creation. + * + * grEngCount[OUT] + * - Number of SMC engines/GR engines allocated in partition + * GrIDs in a partition will always start from 0 and end at grEngCount-1 + * + * veidCount[OUT] + * - VEID Count assigned to a partition. These will be divided across + * SMC engines once CONFIGURE_PARTITION call has been made. The current + * algorithm is to assign veidPerGpc * gpcCountPerSmc to a SMC engine. + * + * smCount[OUT] + * - SMs assigned to a partition. + * + * ceCount[OUT] + * - Copy Engines assigned to a partition. + * + * nvEncCount[OUT] + * - NvEnc Engines assigned to a partition. + * + * nvDecCount[OUT] + * - NvDec Engines assigned to a partition. + * + * nvJpgCount[OUT] + * - NvJpg Engines assigned to a partition. + * + * gpcCount[OUT] + * - Max GPCs assigned to a partition, including the GfxCapable ones. + * + * virtualGpcCount[OUT] + * - Virtualized GPC count assigned to partition + * + * gfxGpcCount[OUT] + * - Max GFX GPCs assigned to a partition. This is a subset of the GPCs incuded in gpcCount. + * + * gpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT] + * - GPC count associated with every valid SMC/Gr, including the GPCs capable of GFX + * + * virtualGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT] + * - Virtualized GPC count associated with every valid SMC/Gr, including the GPCs capable of GFX + * + * gfxGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT] + * - GFX GPC count associated with every valid SMC/Gr. This is a subset of the GPCs included in gfxGpcCount + * + * veidsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT] + * - VEID count associated with every valid SMC. VEIDs within this SMC + * will start from 0 and go till veidCount[SMC_ID] - 1. + * + * span[OUT] + * - The span covered by this partition + * + * bValid[OUT] + * - NV_TRUE if partition is valid else NV_FALSE. + * + * bPartitionError[OUT] + * - NV_TRUE if partition had poison error which requires drain and reset + * else NV_FALSE. + * + * validCTSIdMask[OUT] + * - Mask of CTS IDs usable by this partition, not reflecting current allocations + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_NOT_SUPPORTED + */ +typedef struct NV2080_CTRL_GPU_GET_PARTITION_INFO { + NvU32 swizzId; + NvU32 partitionFlag; + NvU32 grEngCount; + NvU32 veidCount; + NvU32 smCount; + NvU32 ceCount; + NvU32 nvEncCount; + NvU32 nvDecCount; + NvU32 nvJpgCount; + NvU32 nvOfaCount; + NvU32 gpcCount; + NvU32 virtualGpcCount; + NvU32 gfxGpcCount; + NvU32 gpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NvU32 virtualGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NvU32 gfxGpcPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NvU32 veidsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NV_DECLARE_ALIGNED(NvU64 memSize, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN span, 8); + NvBool bValid; + NvBool bPartitionError; + NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8); +} NV2080_CTRL_GPU_GET_PARTITION_INFO; + +/* + * NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS + * + * queryPartitionInfo[IN] + * - Max sized array of NV2080_CTRL_GPU_GET_PARTITION_INFO to get partition + * Info + * + * bGetAllPartitionInfo[In] + * - Flag to get all partitions info. Only root client will receive all + * partition's info. Non-Root clients should not use this flag + * + * validPartitionCount[Out] + * - Valid partition count which has been filled by RM as part of the call + * + */ +#define NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS_MESSAGE_ID (0x75U) + +typedef struct NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_GET_PARTITION_INFO queryPartitionInfo[NV2080_CTRL_GPU_MAX_PARTITIONS], 8); + NvU32 validPartitionCount; + NvBool bGetAllPartitionInfo; +} NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS; + +#define NV2080_CTRL_CMD_GPU_GET_PARTITIONS (0x20800175U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_GPU_CONFIGURE_PARTITION + * + * This command configures a partition by associating GPCs with SMC Engines + * available in that partition. Engines which are to have GPCs assigned to them + * shall not already have any GPCs assigned to them. It is not valid to both + * assign GPCs and remove GPCs as part of a single call to this function. + * + * swizzId[IN] + * - PartitionID for configuring partition. If partition has a valid + * context created, then configuration is not allowed. + * + * gpcCountPerSmcEng[IN] + * - Number of GPCs expected to be configured per SMC. Supported + * configurations are 0, 1, 2, 4 or 8. "0" means a particular SMC + * engine will be disabled with no GPC connected to it. + * + * updateSmcEngMask[IN] + * - Mask tracking valid entries of gpcCountPerSmcEng. A value of + * 0 in bit index i indicates that engine i will keep its current + * configuration. + * + * bUseAllGPCs[IN] + * - Flag specifying alternate configuration mode, indicating that in + * swizzid 0 only, all non-floorswept GPCs should be connected to the + * engine indicated by a raised bit in updateSmcEngMask. Only a single + * engine may be targeted by this operation. The gpcCountPerSmcEng + * parameter should not be used with this flag. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_INSUFFICIENT_RESOURCES + * NV_ERR_NOT_SUPPORTED + * NV_ERR_STATE_IN_USE + */ +#define NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION (0x20800176U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID (0x76U) + +typedef struct NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS { + NvU32 swizzId; + NvU32 gpcCountPerSmcEng[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NvU32 updateSmcEngMask; + NvBool bUseAllGPCs; +} NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS; + + +/* + * NV2080_CTRL_GPU_FAULT_PACKET + * + * This struct represents a GMMU fault packet. + * + */ +#define NV2080_CTRL_GPU_FAULT_PACKET_SIZE 32U +typedef struct NV2080_CTRL_GPU_FAULT_PACKET { + NvU8 data[NV2080_CTRL_GPU_FAULT_PACKET_SIZE]; +} NV2080_CTRL_GPU_FAULT_PACKET; + +/* + * NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT + * + * This command reports a nonreplayable fault packet to RM. + * It is only used by UVM. + * + * pFaultPacket[IN] + * - A fault packet that will be later cast to GMMU_FAULT_PACKET *. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_GPU_REPORT_NON_REPLAYABLE_FAULT (0x20800177U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID (0x77U) + +typedef struct NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS { + NV2080_CTRL_GPU_FAULT_PACKET faultPacket; +} NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU + * + * This command is similar to NV2080_CTRL_CMD_GPU_EXEC_REG_OPS, except it is used + * by the VGPU plugin client only. This command provides access to the subset of + * privileged registers. + * + * See confluence page "vGPU UMED Security" for details. + * + */ +#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU (0x20800178U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x78" */ + +/* + * NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE + * + * This command returns the runlist pri base of the specified engine(s). + * + * engineList + * Input array. + * This array specifies the engines being queried for information. + * The list of engines supported by a chip can be fetched using the + * NV2080_CTRL_CMD_GPU_GET_ENGINES/GET_ENGINES_V2 ctrl call. + * + * runlistPriBase + * Output array. + * Returns the runlist pri base for the specified engines + * Else, will return _NULL when the input is a NV2080_ENGINE_TYPE_NULL + * and will return _ERROR when the control call fails due to an invalid argument + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE (0x20800179U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID (0x79U) + +typedef struct NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS { + NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; + NvU32 runlistPriBase[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; +} NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS; + +#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_NULL (0xFFFFFFFFU) +#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_ERROR (0xFFFFFFFBU) + +/* + * NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID + * + * This command returns the host hardware defined engine ID of the specified engine(s). + * + * engineList + * Input array. + * This array specifies the engines being queried for information. + * The list of engines supported by a chip can be fetched using the + * NV2080_CTRL_CMD_GPU_GET_ENGINES/GET_ENGINES_V2 ctrl call. + * + * hwEngineID + * Output array. + * Returns the host hardware engine ID(s) for the specified engines + * Else, will return _NULL when the input is a NV2080_ENGINE_TYPE_NULL + * and will return _ERROR when the control call fails due to an invalid argument + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID (0x2080017aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID (0x7AU) + +typedef struct NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS { + NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; + NvU32 hwEngineID[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; +} NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS; + +#define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_NULL (0xFFFFFFFFU) +#define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_ERROR (0xFFFFFFFBU) + +/* + * NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS + * + * This command is used to retrieve the GPU's count of FBC sessions, + * average FBC calls and FBC latency over all active sessions. + * + * sessionCount + * This field specifies count of all active fbc sessions on this GPU. + * + * averageFPS + * This field specifies the average frames captured. + * + * averageLatency + * This field specifies the average FBC latency in microseconds. + * + * Possible status values returned are : + * NV_OK + * NV_ERR_INVALID_ARGUMENT +*/ +#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS (0x2080017bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID (0x7BU) + +typedef struct NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS { + NvU32 sessionCount; + NvU32 averageFPS; + NvU32 averageLatency; +} NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS; + +/* +* NV2080_CTRL_NVFBC_SW_SESSION_INFO +* +* processId[OUT] +* Process id of the process owning the NvFBC session. +* On VGX host, this will specify the vGPU plugin process id. +* subProcessId[OUT] +* Process id of the process owning the NvFBC session if the +* session is on VGX guest, else the value is zero. +* vgpuInstanceId[OUT] +* vGPU on which the process owning the NvFBC session +* is running if session is on VGX guest, else +* the value is zero. +* sessionId[OUT] +* Unique session id of the NvFBC session. +* sessionType[OUT] +* Type of NvFBC session. +* displayOrdinal[OUT] +* Display identifier associated with the NvFBC session. +* sessionFlags[OUT] +* One or more of NV2080_CTRL_NVFBC_SESSION_FLAG_xxx. +* hMaxResolution[OUT] +* Max horizontal resolution supported by the NvFBC session. +* vMaxResolution[OUT] +* Max vertical resolution supported by the NvFBC session. +* hResolution[OUT] +* Horizontal resolution requested by caller in grab call. +* vResolution[OUT] +* Vertical resolution requested by caller in grab call. +* averageFPS[OUT] +* Average no. of frames captured per second. +* averageLatency[OUT] +* Average frame capture latency in microseconds. +*/ + +#define NV2080_CTRL_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED 0x00000001U +#define NV2080_CTRL_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED 0x00000002U +#define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_NO_WAIT 0x00000004U +#define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_INFINITE 0x00000008U +#define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_TIMEOUT 0x00000010U + +typedef struct NV2080_CTRL_NVFBC_SW_SESSION_INFO { + NvU32 processId; + NvU32 subProcessId; + NvU32 vgpuInstanceId; + NvU32 sessionId; + NvU32 sessionType; + NvU32 displayOrdinal; + NvU32 sessionFlags; + NvU32 hMaxResolution; + NvU32 vMaxResolution; + NvU32 hResolution; + NvU32 vResolution; + NvU32 averageFPS; + NvU32 averageLatency; +} NV2080_CTRL_NVFBC_SW_SESSION_INFO; + +/* +* NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO +* +* This command returns NVFBC software sessions information for the associate GPU. +* +* sessionInfoCount +* This field specifies the number of entries that are filled inside +* sessionInfoTbl. Max value of this field once returned from RM would be +* NV2080_GPU_NVFBC_MAX_COUNT. +* +* sessionInfoTbl +* This field specifies the array in which the NVFBC session information is to +* be returned. RM will fill the current session data in sessionInfoTbl array +* and then update the sessionInfoCount to reflect current session count value. +* +* Possible status values returned are: +* NV_OK +* NV_ERR_NO_MEMORY +* NV_ERR_INVALID_LOCK_STATE +* NV_ERR_INVALID_ARGUMENT +*/ + +#define NV2080_GPU_NVFBC_MAX_SESSION_COUNT 256U + +#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID (0x7CU) + +typedef struct NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS { + NvU32 sessionInfoCount; + NV2080_CTRL_NVFBC_SW_SESSION_INFO sessionInfoTbl[NV2080_GPU_NVFBC_MAX_SESSION_COUNT]; +} NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS; + +#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO (0x2080017cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID" */ + + + +/* + * NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE + * + * This command returns the VMMU page size + * + * vmmuSegmentSize + * Output parameter. + * Returns the VMMU segment size (in bytes) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE (0x2080017eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID (0x7EU) + +typedef struct NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 vmmuSegmentSize, 8); +} NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS; + +#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_32MB 0x02000000U +#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_64MB 0x04000000U +#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_128MB 0x08000000U +#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_256MB 0x10000000U +#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_512MB 0x20000000U + + + +/* + * NV2080_CTRL_GPU_GET_PARTITION_CAPACITY + * + * This command returns the count of partitions of given size (represented by + * NV2080_CTRL_GPU_PARTITION_FLAG_*) which can be requested via + * NV2080_CTRL_GPU_SET_PARTITIONS ctrl call. + * Note that this API does not "reserve" any partitions, and there is no + * guarantee that the reported count of available partitions of a given size + * will remain consistent following creation of partitions of different size + * through NV2080_CTRL_GPU_SET_PARTITIONS. + * Note that this API is unsupported if SMC is feature-disabled. + * + * partitionFlag[IN] + * - Partition flag indicating size of requested partitions + * + * partitionCount[OUT] + * - Available number of partitions of the given size which can currently be created. + * + * availableSpans[OUT] + * - For each partition able to be created of the specified size, the span + * it could occupy. + * + * availableSpansCount[OUT] + * - Number of valid entries in availableSpans. + * + * totalPartitionCount[OUT] + * - Total number of partitions of the given size which can be created. + * + * totalSpans[OUT] + * - List of spans which can possibly be occupied by partitions of the + * given type. + * + * totalSpansCount[OUT] + * - Number of valid entries in totalSpans. + * + * bStaticInfo[IN] + * - Flag indicating that client requests only the information from + * totalPartitionCount and totalSpans. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_PARTITION_CAPACITY (0x20800181U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS { + NvU32 partitionFlag; + NvU32 partitionCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN availableSpans[NV2080_CTRL_GPU_MAX_PARTITIONS], 8); + NvU32 availableSpansCount; + NvU32 totalPartitionCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN totalSpans[NV2080_CTRL_GPU_MAX_PARTITIONS], 8); + NvU32 totalSpansCount; + NvBool bStaticInfo; +} NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_CACHED_INFO + * + * This command returns cached(SW only) gpu information for the associated GPU. + * Requests to retrieve gpu information use a list of one or more NV2080_CTRL_GPU_INFO + * structures. + * The gpuInfoList is aligned with NV2080_CTRL_GPU_GET_INFO_V2_PARAMS for security concern + * + * gpuInfoListSize + * This field specifies the number of entries on the caller's + * gpuInfoList. + * gpuInfoList + * This field specifies a pointer in the caller's address space + * to the buffer into which the gpu information is to be returned. + * This buffer must be at least as big as gpuInfoListSize multiplied + * by the size of the NV2080_CTRL_GPU_INFO structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_OPERATING_SYSTEM + */ +#define NV2080_CTRL_CMD_GPU_GET_CACHED_INFO (0x20800182U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x82" */ + +typedef struct NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS { + NvU32 gpuInfoListSize; + NV2080_CTRL_GPU_INFO gpuInfoList[NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE]; +} NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS; + +/* + * NV2080_CTRL_GPU_SET_PARTITIONING_MODE + * + * This command configures this GPU to control global mode for partitioning. + * This command may not be sent to a GPU with any active partitions. + * This command may be used to set the following modes: + * + * NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING + * NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_LEGACY + * This is the default mode. While this GPU is in this mode, no partitions + * will be allowed to be created via SET_PARTITIONS - a client must set one + * of the below modes prior to partitioning the GPU. When a client sets a + * GPU into this mode, any performance changes resulting from partitions + * made while in either of the below modes will be cleared. A + * physical-function-level reset is required after setting this mode. + * + * NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_MAX_PERF + * In this mode, when the GPU is partitioned, each partition will have the + * maximum possible performance which can be evenly distributed among all + * partitions. The total performance of the GPU, taking into account all + * partitions created in this mode, may be less than that of a GPU running + * in legacy non-SMC mode. Partitions created while in this mode require a + * physical-function-level reset before the partitioning may take full + * effect. Destroying all partitions while in this mode may be + * insufficient to restore full performance to the GPU - only by setting + * the mode to _LEGACY can this be achieved. A physical-function-level + * reset is NOT required after setting this mode. + * + * NV2080_CTRL_GPU_SET_PARTIITONING_MODE_REPARTITIONING_FAST_RECONFIG + * By setting this mode, the performance of the GPU will be restricted such + * that all partitions will have a consistent fraction of the total + * available performance, which may be less than the maximum possible + * performance available to each partition. Creating or destroying + * partitions on this GPU while in this mode will not require a + * physical-function-level reset, and will not affect other active + * partitions. Destroying all partitions while in this mode may be + * insufficient to restore full performance to the GPU - only by setting + * the mode to _LEGACY can this be achieved. A physical-function-level + * reset is required after setting this mode. + * + * Parameters: + * partitioningMode[IN] + * - Partitioning Mode to set for this GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE (0x20800183U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING 1:0 +#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_LEGACY 0U +#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_MAX_PERF 1U +#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_FAST_RECONFIG 2U + +#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID (0x83U) + +typedef struct NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS { + NvU32 partitioningMode; +} NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS; + + + +/* NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO + * + * This structure describes resources available in a partition requested of a + * given type. + * + * [OUT] partitionFlag + * - Flags to specify in NV2080_CTRL_CMD_GPU_SET_PARTITIONS to request this + * partition + * + * [OUT] grCount + * - Total Number of SMC engines/GR engines (including GFX capable ones in this parition) + * + * [OUT] gfxGrCount + * - Number of SMC engines/GR engines capable of GFX. This is a subset of the engines included in grCount + * + * [OUT] gpcCount + * - Number of GPCs in this partition, including the GFX Capable ones. + * + * [OUT] virtualGpcCount + * - Number of virtualized GPCs in this partition, including the GFX Capable ones. + * + * [OUT] gfxGpcCount + * - Number of GFX Capable GPCs in this partition. This is a subset of the GPCs included in gpcCount. + * + * [OUT] veidCount + * - Number of VEIDS in this partition + * + * [OUT] smCount + * - Number of SMs in this partition + * + * [OUT] ceCount + * - Copy Engines in this partition + * + * [OUT] nvEncCount + * - Encoder Engines in this partition + * + * [OUT] nvDecCount + * - Decoder Engines in this partition + * + * [OUT] nvJpgCount + * - Jpg Engines in this partition + * + * [OUT] nvOfaCount + * - Ofa engines in this partition + * [OUT] memorySize + * - Total available memory within this partition + */ +typedef struct NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO { + NvU32 partitionFlag; + NvU32 grCount; + NvU32 gfxGrCount; + NvU32 gpcCount; + NvU32 virtualGpcCount; + NvU32 grGpcCount; + NvU32 veidCount; + NvU32 smCount; + NvU32 ceCount; + NvU32 nvEncCount; + NvU32 nvDecCount; + NvU32 nvJpgCount; + NvU32 nvOfaCount; + NV_DECLARE_ALIGNED(NvU64 memorySize, 8); +} NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO; + +/* + * NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS + * + * This command returns information regarding GPU partitions which can be + * requested via NV2080_CTRL_CMD_GPU_SET_PARTITIONS. + * + * [OUT] descCount + * - Number of valid partition types + * + * [OUT] partitionDescs + * - Information describing available partitions + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS_MESSAGE_ID (0x85U) + +typedef struct NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS { + NvU32 descCount; + // C form: NV2080_CTRL_GPU_DESCRIBE_PARTITION_INFO partitionDescs[NV2080_CTRL_GPU_PARTITION_MAX_TYPES]; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO partitionDescs[NV2080_CTRL_GPU_PARTITION_MAX_TYPES], 8); +} NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS; + +#define NV2080_CTRL_CMD_GPU_DESCRIBE_PARTITIONS (0x20800185U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS_MESSAGE_ID" */ + + + +/* + * NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE + * + * This command returns information regarding maximum page size supported + * by GMMU on the platform on which RM is running. + * + * [OUT] maxSupportedPageSize + * - Maximum local vidmem page size supported by GMMU of a given GPU (HW) + * on a given platform (OS) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE (0x20800188U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID (0x88U) + +typedef struct NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS { + NvU32 maxSupportedPageSize; +} NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS; + + + +/* + * NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC + * + * This command returns the max number of MMUs per GPC + * + * gpcId [IN] + * Logical GPC id + * count [OUT] + * The number of MMUs per GPC + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. When SMC is enabled, this + * is a mandatory parameter. + */ +#define NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID (0x8AU) + +typedef struct NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS { + NvU32 gpcId; + NvU32 count; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS; + +#define NV2080_CTRL_CMD_GPU_GET_NUM_MMUS_PER_GPC (0x2080018aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS + * + * This command returns the GPU partition IDs for all active partitions + * If GPU is not partitioned, the control call will return partition count as "0" + * + * swizzId[OUT] + * - HW Partition ID associated with the active partitions + * + * partitionCount[OUT] + * - Number of active partitions in system + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS_MESSAGE_ID (0x8BU) + +typedef struct NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS { + NvU32 swizzId[NV2080_CTRL_GPU_MAX_PARTITION_IDS]; + NvU32 partitionCount; +} NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS; + +#define NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS (0x2080018bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS_MESSAGE_ID" */ + + + +/* + * NV2080_CTRL_CMD_GPU_GET_PIDS + * + * Given a resource identifier and its type, this command returns a set of + * process identifiers (PIDs) of processes that have instantiated this resource. + * For example, given a class number, this command returns a list of all + * processes with clients that have matching object allocations. + * This is a SMC aware call and the scope of the information gets restricted + * based on partition subscription. + * The call enforces partition subscription if SMC is enabled, and client is not + * a monitoring client. + * Monitoring clients get global information without any scope based filtering. + * Monitoring clients are also not expected to subscribe to a partition when + * SMC is enabled. + * + * idType + * Type of the resource identifier. See below for a list of valid types. + * id + * Resource identifier. + * pidTblCount + * Number of entries in the PID table. + * pidTbl + * Table which will contain the PIDs. Each table entry is of type NvU32. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_GPU_GET_PIDS (0x2080018dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID" */ + +/* max size of pidTable */ +#define NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT 950U + +#define NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID (0x8DU) + +typedef struct NV2080_CTRL_GPU_GET_PIDS_PARAMS { + NvU32 idType; + NvU32 id; + NvU32 pidTblCount; + NvU32 pidTbl[NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT]; +} NV2080_CTRL_GPU_GET_PIDS_PARAMS; + +/* + * Use class NV20_SUBDEVICE_0 with NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_CLASS to query + * PIDs with or without GPU contexts. For any other class id, PIDs only with GPU + * contexts are returned. + */ +#define NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_CLASS (0x00000000U) +#define NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_VGPU_GUEST (0x00000001U) + +/* + * NV2080_CTRL_SMC_SUBSCRIPTION_INFO + * + * This structure contains information about the SMC subscription type. + * If MIG is enabled a valid ID is returned, it is set to PARTITIONID_INVALID otherwise. + * + * computeInstanceId + * This parameter returns a valid compute instance ID + * gpuInstanceId + * This parameter returns a valid GPU instance ID + */ +typedef struct NV2080_CTRL_SMC_SUBSCRIPTION_INFO { + NvU32 computeInstanceId; + NvU32 gpuInstanceId; +} NV2080_CTRL_SMC_SUBSCRIPTION_INFO; + +/* + * NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA + * + * This structure contains the video memory usage information. + * + * memPrivate + * This parameter returns the amount of memory exclusively owned + * (i.e. private) to the client + * memSharedOwned + * This parameter returns the amount of shared memory owned by the client + * memSharedDuped + * This parameter returns the amount of shared memory duped by the client + * protectedMemPrivate + * This parameter returns the amount of protected memory exclusively owned + * (i.e. private) to the client whenever memory protection is enabled + * protectedMemSharedOwned + * This parameter returns the amount of shared protected memory owned by the + * client whenever memory protection is enabled + * protectedMemSharedDuped + * This parameter returns the amount of shared protected memory duped by the + * client whenever memory protection is enabled + */ +typedef struct NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA { + NV_DECLARE_ALIGNED(NvU64 memPrivate, 8); + NV_DECLARE_ALIGNED(NvU64 memSharedOwned, 8); + NV_DECLARE_ALIGNED(NvU64 memSharedDuped, 8); + NV_DECLARE_ALIGNED(NvU64 protectedMemPrivate, 8); + NV_DECLARE_ALIGNED(NvU64 protectedMemSharedOwned, 8); + NV_DECLARE_ALIGNED(NvU64 protectedMemSharedDuped, 8); +} NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA; + +#define NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE (0x00000000U) + +#define NV2080_CTRL_GPU_PID_INFO_INDEX_MAX NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE + +typedef union NV2080_CTRL_GPU_PID_INFO_DATA { + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA vidMemUsage, 8); +} NV2080_CTRL_GPU_PID_INFO_DATA; + + +/* + * NV2080_CTRL_GPU_PID_INFO + * + * This structure contains the per pid information. Each type of information + * retrievable via NV2080_CTRL_CMD_GET_PID_INFO is assigned a unique index + * below. In addition the process for which the lookup is for is also defined. + * This is a SMC aware call and the scope of the information gets restricted + * based on partition subscription. + * The call enforces partition subscription if SMC is enabled, and client is not + * a monitoring client. + * Monitoring clients get global information without any scope based filtering. + * Monitoring clients are also not expected to subscribe to a partition when + * SMC is enabled. + * + * pid + * This parameter specifies the PID of the process for which information is + * to be queried. + * index + * This parameter specifies the type of information being queried for the + * process of interest. + * result + * This parameter returns the result of the instruction's execution. + * data + * This parameter returns the data corresponding to the information which is + * being queried. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + * + * Valid PID information indices are: + * + * NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE + * This index is used to request the amount of video memory on this GPU + * allocated to the process. + */ +typedef struct NV2080_CTRL_GPU_PID_INFO { + NvU32 pid; + NvU32 index; + NvU32 result; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PID_INFO_DATA data, 8); + NV2080_CTRL_SMC_SUBSCRIPTION_INFO smcSubscription; +} NV2080_CTRL_GPU_PID_INFO; + +/* + * NV2080_CTRL_CMD_GPU_GET_PID_INFO + * + * This command allows querying per-process information from the RM. Clients + * request information by specifying a unique informational index and the + * Process ID of the process in question. The result is set to indicate success + * and the information queried (if available) is returned in the data parameter. + * + * pidInfoListCount + * The number of valid entries in the pidInfoList array. + * pidInfoList + * An array of NV2080_CTRL_GPU_PID_INFO of maximum length + * NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_GPU_GET_PID_INFO (0x2080018eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID" */ + +/* max size of pidInfoList */ +#define NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT 200U + +#define NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID (0x8EU) + +typedef struct NV2080_CTRL_GPU_GET_PID_INFO_PARAMS { + NvU32 pidInfoListCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PID_INFO pidInfoList[NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT], 8); +} NV2080_CTRL_GPU_GET_PID_INFO_PARAMS; + + + +/*! + * NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT + * + * @brief Handle VF PRI faults + * + * faultType + * BAR1, BAR2, PHYSICAL or UNBOUND_INSTANCE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * + */ + +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT (0x20800192U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_INVALID 0U +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR1 1U +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR2 2U +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_PHYSICAL 3U +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_UNBOUND_INSTANCE 4U + +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_MESSAGE_ID (0x92U) + +typedef struct NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS { + NvU32 faultType; +} NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS; + + +/*! + * Compute policy types to be specified by callers to set a config. + * + * _TIMESLICE + * Set the timeslice config for the requested GPU. + * Check @ref NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE for + * permissible timeslice values. + */ +#define NV2080_CTRL_GPU_COMPUTE_POLICY_TIMESLICE 0U +#define NV2080_CTRL_GPU_COMPUTE_POLICY_MAX 1U + +/*! + * Enum consisting of permissible timeslice options that can configured + * for a GPU. These can be queried by compute clients and the exact + * timeslice values can be chosen appropriately as per GPU support + */ +typedef enum NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE { + NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_DEFAULT = 0, + NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_SHORT = 1, + NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MEDIUM = 2, + NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_LONG = 3, + NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MAX = 4, +} NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE; + +typedef struct NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG { + /*! + * NV2080_CTRL_GPU_COMPUTE_POLICY_ + */ + NvU32 type; + + /*! + * Union of type-specific data + */ + union { + NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE timeslice; + } data; +} NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG; + +#define NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID (0x94U) + +typedef struct NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS { + NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG config; +} NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG + * + * This command retrieves all compute policies configs for the associated gpu. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG (0x20800195U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID" */ + +/*! + * This define limits the max number of policy configs that can be handled by + * NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG command. + * + * @note Needs to be in sync (greater or equal) to NV2080_CTRL_GPU_COMPUTE_POLICY_MAX. + */ + +#define NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX 32U + +#define NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID (0x95U) + +typedef struct NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS { + NvU32 numConfigs; + + /*! + * C form: + * NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG configList[NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX]; + */ + NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG configList[NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX]; +} NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_GFID + * + * This command returns the GFID (GPU Function ID) for a given SR-IOV + * Virtual Function (VF) of the physical GPU. + * + * domain [IN] + * This field specifies the respective domain of the PCI device. + * bus [IN] + * This field specifies the bus id for a given VF. + * device [IN] + * This field specifies the device id for a given VF. + * func [IN] + * This field specifies the function id for a given VF. + * gfid[OUT] + * - This field returns GFID for a given VF BDF. + * gfidMask[OUT] + * - This field returns GFID mask value. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ + +#define NV2080_CTRL_CMD_GPU_GET_GFID (0x20800196U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GFID_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_GFID_PARAMS_MESSAGE_ID (0x96U) + +typedef struct NV2080_CTRL_GPU_GET_GFID_PARAMS { + NvU32 domain; + NvU8 bus; + NvU8 device; + NvU8 func; + NvU32 gfid; + NvU32 gfidMask; +} NV2080_CTRL_GPU_GET_GFID_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY + * + * This command informs the GPU driver that the GPU partition associated with + * a given GFID has been activated or will be deactivated. + * + * gfid[IN] + * - The GPU function identifier for a given VF BDF + * bEnable [IN] + * - Set to NV_TRUE if the GPU partition has been activated. + * - Set to NV_FALSE if the GPU partition will be deactivated. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ + +#define NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY (0x20800197U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS_MESSAGE_ID (0x97U) + +typedef struct NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS { + NvU32 gfid; + NvBool bEnable; +} NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS; + +/*! + * NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST + * + * @brief Validate the address range for memory map request by comparing the + * user supplied address range with GPU BAR0/BAR1 range. + * + * @param[in] addressStart Start address for memory map request + * @param[in] addressLength Length for for memory map request + * @param[out] protection NV_PROTECT_READ_WRITE, if both read/write is allowed + * NV_PROTECT_READABLE, if only read is allowed + * + * Possible status values returned are: + * NV_OK + * NV_ERR_PROTECTION_FAULT + * + */ +#define NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST (0x20800198U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID (0x98U) + +typedef struct NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS { + NV_DECLARE_ALIGNED(NvU64 addressStart, 8); + NV_DECLARE_ALIGNED(NvU64 addressLength, 8); + NvU32 protection; +} NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES + * + * This command is used to retrieve the load time (latency) of each engine. + * + * engineCount + * This field specifies the number of entries of the following + * three arrays. + * + * engineList[NV2080_GPU_MAX_ENGINE_OBJECTS] + * An array of NvU32 which stores each engine's descriptor. + * + * engineStateLoadTime[NV2080_GPU_MAX_ENGINE_OBJECTS] + * A array of NvU64 which stores each engine's load time. + * + * engineIsInit[NV2080_GPU_MAX_ENGINE_OBJECTS] + * A array of NvBool which stores each engine's initialization status. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES (0x2080019bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS 0xA0U + +#define NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID (0x9BU) + +typedef struct NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS { + NvU32 engineCount; + NvU32 engineList[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS]; + NV_DECLARE_ALIGNED(NvU64 engineStateLoadTime[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS], 8); + NvBool engineIsInit[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS]; +} NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING + * + * This command is used to retrieve the mapping of engine ID and engine Name. + * + * engineCount + * This field specifies the size of the mapping. + * + * engineID + * An array of NvU32 which stores each engine's descriptor. + * + * engineName + * An array of char[100] which stores each engine's name. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING (0x2080019cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID (0x9CU) + +typedef struct NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS { + NvU32 engineCount; + NvU32 engineID[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS]; + char engineName[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS][100]; +} NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_NOPTRS + * + * Same as above NV2080_CTRL_CMD_GPU_EXEC_REG_OPS except that this CTRL CMD will + * not allow any embedded pointers. The regOps array is inlined as part of the + * struct. + * NOTE: This intended for gsp plugin only as it may override regOp access + * restrictions + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_NOPTRS (0x2080019dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID" */ + +/* setting this to 100 keeps it right below 4k in size */ +#define NV2080_CTRL_REG_OPS_ARRAY_MAX 100U +#define NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID (0x9DU) + +typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS { + NvHandle hClientTarget; + NvHandle hChannelTarget; + NvU32 bNonTransactional; + NvU32 reserved00[2]; + NvU32 regOpCount; + NV2080_CTRL_GPU_REG_OP regOps[NV2080_CTRL_REG_OPS_ARRAY_MAX]; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS; + + + + +/*! + * NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO + * + * [in/out] gpuId + * GPU ID for which the capabilities are queried. + * For the NV2080_CTRL_CMD_GET_P2P_CAPS control: + * If bAllCaps == NV_TRUE, this parameter is an out parameter and equals to + * the GPU ID of an attached GPU. + * If bAllCaps == NV_FALSE, this parameter is an in parameter and the requester + * should set it to the ID of the GPU that needs to be queried from. + * [in] gpuUuid + * Alternative to gpuId; used to identify target GPU for which caps are being queried. + * Option only available for Guest RPCs. + * If bUseUuid == NV_TRUE, gpuUuid is used in lieu of gpuId to identify target GPU. + * If bUseUuid == NV_FALSE, gpuUuid is ignored and gpuId is used by default. + * If bAllCaps == NV_TRUE, gpuUuid is ignored. + * [out] p2pCaps + * Peer to peer capabilities discovered between the GPUs. + * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. + * [out] p2pOptimalReadCEs + * Mask of CEs to use for p2p reads over Nvlink. + * [out] p2pOptimalWriteCEs + * Mask of CEs to use for p2p writes over Nvlink. + * [out] p2pCapsStatus + * Status of all supported p2p capabilities. + * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. + * [out] busPeerId + * Bus peer ID. For an invalid or a non-existent peer this field + * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. + */ +#define NV2080_GET_P2P_CAPS_UUID_LEN 16U + +typedef struct NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO { + NvU32 gpuId; + NvU8 gpuUuid[NV2080_GET_P2P_CAPS_UUID_LEN]; + NvU32 p2pCaps; + NvU32 p2pOptimalReadCEs; + NvU32 p2pOptimalWriteCEs; + NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; + NvU32 busPeerId; +} NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO; + +/*! + * NV2080_CTRL_CMD_GET_P2P_CAPS + * + * Returns peer to peer capabilities present between GPUs. + * The caller must either specify bAllCaps to query the capabilities for + * all the attached GPUs or they must pass a valid list of GPU IDs. + * + * [in] bAllCaps + * Set to NV_TRUE to query the capabilities for all the attached GPUs. + * Set to NV_FALSE and specify peerGpuCount and peerGpuCaps[].gpuId + * to retrieve the capabilities only for the specified GPUs. + * [in] bUseUuid + * Option only available for Guest RPCs. + * Set to NV_TRUE to use gpuUuid in lieu of gpuId to identify target GPU. + * If bAllCaps == NV_TRUE, bUseUuid is ignored. + * [in/out] peerGpuCount + * The number of the peerGpuCaps entries. + * If bAllCaps == NV_TRUE, this parameter is an out parameter and equals to + * the total number of the attached GPUs. + * If bAllCaps == NV_FALSE, this parameter is an in parameter and the requester + * should set it to the number of the peerGpuCaps entries. + * [in/out] peerGpuCaps + * The array of NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO entries, describing + * the peer to peer capabilities of the GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT - Invalid peerGpuCount + * NV_ERR_OBJECT_NOT_FOUND - Invalid peerGpuCaps[].gpuId + */ +#define NV2080_CTRL_CMD_GET_P2P_CAPS (0x208001a0U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID (0xA0U) + +typedef struct NV2080_CTRL_GET_P2P_CAPS_PARAMS { + NvBool bAllCaps; + NvBool bUseUuid; + NvU32 peerGpuCount; + NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO peerGpuCaps[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; +} NV2080_CTRL_GET_P2P_CAPS_PARAMS; + + + +/*! + * NV2080_CTRL_GPU_COMPUTE_PROFILE + * + * This structure specifies resources in an execution partition + * + * id[OUT] + * - Total Number of GPCs in this partition + * + * computeSize[OUT] + * - NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* associated with this profile + * + * gpcCount[OUT] + * - Total Number of GPCs in this partition (including GFX Supported GPCs) + * + * veidCount[OUT] + * - Number of VEIDs allocated to this profile + * + * smCount[OUT] + * - Number of SMs usable in this profile + */ +typedef struct NV2080_CTRL_GPU_COMPUTE_PROFILE { + NvU8 computeSize; + NvU32 gfxGpcCount; + NvU32 gpcCount; + NvU32 veidCount; + NvU32 smCount; +} NV2080_CTRL_GPU_COMPUTE_PROFILE; + +/*! + * NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS + * + * This structure specifies resources in an execution partition + * + * profileCount[OUT] + * - Total Number of profiles filled + * + * profiles[OUT] + * - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles + */ +#define NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xA2U) + +typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS { + NvU32 profileCount; + NV2080_CTRL_GPU_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE]; +} NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS; + +#define NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILES (0x208001a2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_UNSUPPORTED 0U +#define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_NOT_STARTED 1U +#define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_IN_PROGRESS 2U +#define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE 3U + +#define NV2080_GPU_FABRIC_CLUSTER_UUID_LEN 16U + +#define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_SUPPORTED NVBIT64(0) + +/*! + * NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS + * + * This structure provides the GPU<-->FM probe state info on NVSwitch based + * systems + * + * state[OUT] + * - Current state of GPU<-->FM probe req/rsp + * Following values can be returned + * _UNSUPPORTED - system does not support this feature + * _NOT_STARTED - probe request is not yet sent to the FM + * _IN_PROGRESS - probe response is not yet received + * _COMPLETE - probe response is received + * When state is NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE + * status has to be checked for probe response success/failure + * status[OUT] + * - Inband Probe response status + * A GPU which returns NV_OK status upon receiving the probe response + * can participate in P2P + * clusterUuid[OUT] + * - Uuid of the cluster to which this node belongs + * fabricPartitionId[OUT] + * - Fabric partition Id + * fabricCaps[OUT] + * - Summary of fabric capabilities received from probe resp + * Possible values are + * NV2080_CTRL_GPU_FABRIC_PROBE_CAP_* + */ +#define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xA3U) + +typedef struct NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS { + NvU8 state; + NV_STATUS status; + NvU8 clusterUuid[NV2080_GPU_FABRIC_CLUSTER_UUID_LEN]; + NvU16 fabricPartitionId; + NV_DECLARE_ALIGNED(NvU64 fabricCaps, 8); +} NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS; + +#define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO (0x208001a3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS + * + * This command retrieves and constructs the GPU partnumber from the VBIOS. + * + * The following data are currently supported: + * + * pciDevId + * The PCI device ID + * + * chipSku + * The chip SKU information + * + * chipMajor + * The chip major number + * + * chipMinor + * The chip minor number + * + */ +#define NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS (0x208001a4U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID" */ + +/* + * The string format for a GPU part number + * The GPU part number is formatted with 4 hexadecimal digits for the PCI device ID, the chip SKU string, + * the chip major number, and then the chip minor number. + * Ordering of the fields for the string format must be synced with the NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS + * struct fields. + */ +#define GPU_PART_NUMBER_FMT "%04X-%s-%X%X" + +/* The maximum length for the chip sku */ +#define NV2080_MAX_CHIP_SKU_LENGTH 0x00000004U + +#define NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID (0xA4U) + +typedef struct NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS { + NvU32 pciDevId; + NvU8 chipSku[NV2080_MAX_CHIP_SKU_LENGTH]; + NvU32 chipMajor; + NvU32 chipMinor; +} NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP + * + * This command returns the host hardware defined engine ID of the specified engine(s). + * + * swizzId[IN] + * - HW Partition ID associated with the requested partition. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP (0x208001a5U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS_MESSAGE_ID (0xA5U) + +typedef struct NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS { + NvU32 swizzId; +} NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS; + +#define NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS (0x208001a6U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_GSP (0x208001a7U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_VGPU (0x208001a8U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID" */ + +/* setting this to 100 keeps it right below 4k in size */ +#define NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX 50U +typedef struct NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS { + NvHandle hClientTarget; + NvHandle hChannelTarget; + NvU32 bNonTransactional; + NvU32 regOpCount; + NvU32 smIds[NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX]; + NV2080_CTRL_GPU_REG_OP regOps[NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX]; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS; + +#define NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_MESSAGE_ID (0xA6U) + +typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS; +#define NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS_MESSAGE_ID (0xA7U) + +typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS; +#define NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID (0xA8U) + +typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS; +/* _ctrl2080gpu_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gpumon.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gpumon.h new file mode 100644 index 0000000..742b21a --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gpumon.h @@ -0,0 +1,96 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080gpumon.finn +// + + + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/*! + * This structure represents base class of GPU monitoring sample. + */ +typedef struct NV2080_CTRL_GPUMON_SAMPLE { + /*! + * Timestamps in nano-seconds. + */ + NV_DECLARE_ALIGNED(NvU64 timeStamp, 8); +} NV2080_CTRL_GPUMON_SAMPLE; + +/*! + * This structure represents base GPU monitoring sample. + */ +typedef struct NV2080_CTRL_GPUMON_SAMPLES { + /*! + * Type of the sample, see NV2080_CTRL_GPUMON_SAMPLE_TYPE_* for reference. + */ + NvU8 type; + /*! + * Size of the buffer, this should be + * bufSize == NV2080_CTRL_*_GPUMON_SAMPLE_COUNT_* + * sizeof(derived type of NV2080_CTRL_GPUMON_SAMPLE). + */ + NvU32 bufSize; + /*! + * Number of samples in ring buffer. + */ + NvU32 count; + /*! + * tracks the offset of the tail in the circular queue array pSamples. + */ + NvU32 tracker; + /*! + * Pointer to a circular queue based on array of NV2080_CTRL_GPUMON_SAMPLE + * or its derived types structs with size == bufSize. + * + * @note This circular queue wraps around after 10 seconds of sampling, + * and it is clients' responsibility to query within this time frame in + * order to avoid losing samples. + * @note With one exception, this queue contains last 10 seconds of samples + * with tracker poiniting to oldest entry and entry before tracker as the + * newest entry. Exception is when queue is not full (i.e. tracker is + * pointing to a zeroed out entry), in that case valid entries are between 0 + * and tracker. + * @note Clients can store tracker from previous query in order to provide + * samples since last read. + */ + NV_DECLARE_ALIGNED(NvP64 pSamples, 8); +} NV2080_CTRL_GPUMON_SAMPLES; + +/*! + * Enumeration of GPU monitoring sample types. + */ +#define NV2080_CTRL_GPUMON_SAMPLE_TYPE_PWR_MONITOR_STATUS 0x00000001 +#define NV2080_CTRL_GPUMON_SAMPLE_TYPE_PERFMON_UTIL 0x00000002 + +/*! + * Macro for invalid PID. + */ +#define NV2080_GPUMON_PID_INVALID ((NvU32)(~0)) diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h new file mode 100644 index 0000000..dde6eed --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h @@ -0,0 +1,1820 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080gr.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +#include "ctrl/ctrl0080/ctrl0080gr.h" /* 2080 is partially derivative of 0080 */ +#include "nvcfg_sdk.h" + +/* + * NV2080_CTRL_GR_ROUTE_INFO + * + * This structure specifies the routing information used to + * disambiguate the target GR engine. + * + * flags + * This field decides how the route field is interpreted + * + * route + * This field has the data to identify target GR engine + * + */ +#define NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE 1:0 +#define NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_NONE 0x0U +#define NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_ENGID 0x1U +#define NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_CHANNEL 0x2U + +#define NV2080_CTRL_GR_ROUTE_INFO_DATA_CHANNEL_HANDLE 31:0 +#define NV2080_CTRL_GR_ROUTE_INFO_DATA_ENGID 31:0 + +typedef NV0080_CTRL_GR_ROUTE_INFO NV2080_CTRL_GR_ROUTE_INFO; + +/* NV20_SUBDEVICE_XX gr control commands and parameters */ + +/* + * NV2080_CTRL_GR_INFO + * + * This structure represents a single 32bit gr engine value. Clients + * request a particular gr engine value by specifying a unique gr + * information index. + * + * Legal gr information index values are: + * NV2080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT + * This index is used to request the surface buffer alignment (in bytes) + * required by the associated subdevice. The return value is GPU + * implementation-dependent. + * NV2080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT + * This index is used to request the required swizzled surface alignment + * (in bytes) supported by the associated subdevice. The return value + * is GPU implementation-dependent. A return value of 0 indicates the GPU + * does not support swizzled surfaces. + * NV2080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE + * This index is used to request the vertex cache size (in entries) + * supported by the associated subdevice. The return value is GPU + * implementation-dependent. A value of 0 indicates the GPU does + * have a vertex cache. + * NV2080_CTRL_GR_INFO_INDEX_VPE_COUNT + * This index is used to request the number of VPE units supported by the + * associated subdevice. The return value is GPU implementation-dependent. + * A return value of 0 indicates the GPU does not contain VPE units. + * NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT + * This index is used to request the number of shader pipes supported by + * the associated subdevice. The return value is GPU + * implementation-dependent. A return value of 0 indicates the GPU does + * not contain dedicated shader units. + * For tesla: this value is the number of enabled TPCs + * NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT + * This index is used to request the number of sub units per + * shader pipes supported by the associated subdevice. The return + * value is GPU implementation-dependent. A return value of 0 indicates + * the GPU does not contain dedicated shader units. + * For tesla: this value is the number of enabled SMs (per TPC) + * NV2080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR + * This index is used to request the scaling factor for thread stack + * memory. + * A value of 0 indicates the GPU does not support this function. + * NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT + * This index is used to request the number of SM register banks supported. + * A value of 0 indicates the GPU does not support this function. + * NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT + * This index is used to request the number of registers per SM register + * bank. A value of 0 indicates the GPU does not support this function. + * NV2080_CTRL_GR_INFO_INDEX_SM_VERSION + * This index is used to determine the SM version. + * A value of 0 indicates the GPU does not support this function. + * Otherwise one of NV2080_CTRL_GR_INFO_SM_VERSION_*. + * NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM + * This index is used to determine the maximum number of warps + * (thread groups) per SM. + * A value of 0 indicates the GPU does not support this function. + * NV2080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP + * This index is used to determine the maximum number of threads + * in each warp (thread group). + * A value of 0 indicates the GPU does not support this function. + * NV2080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY + * This index is used to request the default fb memory read/write request + * size in bytes (typically based on the memory configuration/controller). + * Smaller memory requests are likely to take as long as a full one. + * A value of 0 indicates the GPU does not support this function. + * NV2080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY + * This index is used to request the default host memory read/write request + * size in bytes (typically based on the memory configuration/controller). + * Smaller memory requests are likely to take as long as a full one. + * A value of 0 indicates the GPU does not support this function. + * NV2080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM + * This index is used to request the maximum number of streaming processors + * per SM. + * NV2080_CTRL_GR_INFO_INDEX_LITTER_* + * This index is used to query the various LITTER size information from + * the chip. + * NV2080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED + * This index is used to query whether the chip has timeslice mode enabled. + * NV2080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT + * This index is used to return the number of "GPU Cores" + * supported by the graphics pipeline + * NV2080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT + * This index is used to return the number of "Ray Tracing Cores" + * supported by the graphics pipeline + * NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT + * This index is used to return the number of "Tensor Cores" + * supported by the graphics pipeline + */ +typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO; + +/* + * Valid GR info index values + * These indices are offset from supporting the 0080 version of this call + */ +#define NV2080_CTRL_GR_INFO_INDEX_MAXCLIPS NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS +#define NV2080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 +#define NV2080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK +/** + * This index is used to request the surface buffer alignment (in bytes) + * required by the associated subdevice. The return value is GPU + * implementation-dependent. + */ +#define NV2080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT +#define NV2080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT +#define NV2080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE +/** + * This index is used to request the number of VPE units supported by the + * associated subdevice. The return value is GPU implementation-dependent. + * A return value of 0 indicates the GPU does not contain VPE units. + */ +#define NV2080_CTRL_GR_INFO_INDEX_VPE_COUNT NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT +/** + * This index is used to request the number of shader pipes supported by + * the associated subdevice. The return value is GPU + * implementation-dependent. A return value of 0 indicates the GPU does + * not contain dedicated shader units. + * For tesla: this value is the number of enabled TPCs + */ +#define NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT +/** + * This index is used to request the scaling factor for thread stack + * memory. + * A value of 0 indicates the GPU does not support this function. + */ +#define NV2080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR +/** + * This index is used to request the number of sub units per + * shader pipes supported by the associated subdevice. The return + * value is GPU implementation-dependent. A return value of 0 indicates + * the GPU does not contain dedicated shader units. + * For tesla: this value is the number of enabled SMs (per TPC) + */ +#define NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT +#define NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT +#define NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT +/** + * This index is used to determine the SM version. + * A value of 0 indicates the GPU does not support this function. + * Otherwise one of NV2080_CTRL_GR_INFO_SM_VERSION_*. + */ +#define NV2080_CTRL_GR_INFO_INDEX_SM_VERSION NV0080_CTRL_GR_INFO_INDEX_SM_VERSION +/** + * This index is used to determine the maximum number of warps + * (thread groups) per SM. + * A value of 0 indicates the GPU does not support this function. + */ +#define NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM +/** + * This index is used to determine the maximum number of threads + * in each warp (thread group). + * A value of 0 indicates the GPU does not support this function. + */ +#define NV2080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP +#define NV2080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES +#define NV2080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES +#define NV2080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY +#define NV2080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY +#define NV2080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS +#define NV2080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC +#define NV2080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS +/** + * This index is used to return the number of "Ray Tracing Cores" + * supported by the graphics pipeline + */ +#define NV2080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT +#define NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC +#define NV2080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP +#define NV2080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT +#define NV2080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT +#define NV2080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC + +/* When adding a new INDEX, please update INDEX_MAX and MAX_SIZE accordingly + * NOTE: 0080 functionality is merged with 2080 functionality, so this max size + * reflects that. + */ +#define NV2080_CTRL_GR_INFO_INDEX_MAX NV0080_CTRL_GR_INFO_INDEX_MAX +#define NV2080_CTRL_GR_INFO_MAX_SIZE NV0080_CTRL_GR_INFO_MAX_SIZE + +/* valid SM version return values */ + +#define NV2080_CTRL_GR_INFO_SM_VERSION_NONE (0x00000000U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_1_05 (0x00000105U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_1_1 (0x00000110U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_1_2 (0x00000120U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_1_3 (0x00000130U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_1_4 (0x00000140U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_1_5 (0x00000150U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_2_0 (0x00000200U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_2_1 (0x00000210U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_2_2 (0x00000220U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_3_0 (0x00000300U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_3_1 (0x00000310U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_3_2 (0x00000320U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_3_3 (0x00000330U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_3_5 (0x00000350U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_3_6 (0x00000360U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_3_8 (0x00000380U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_3_9 (0x00000390U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_4_0 (0x00000400U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_5_0 (0x00000500U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_5_02 (0x00000502U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_5_03 (0x00000503U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_6_0 (0x00000600U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_6_01 (0x00000601U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_6_02 (0x00000602U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_0 (0x00000700U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_01 (0x00000701U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_02 (0x00000702U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_03 (0x00000703U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_05 (0x00000705U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_02 (0x00000802U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_06 (0x00000806U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_07 (0x00000807U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_08 (0x00000808U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_09 (0x00000809U) +#define NV2080_CTRL_GR_INFO_SM_VERSION_9_00 (0x00000900U) + + + +/* compatibility SM versions to match the official names in the ISA (e.g., SM5.2) */ +#define NV2080_CTRL_GR_INFO_SM_VERSION_5_2 (NV2080_CTRL_GR_INFO_SM_VERSION_5_02) +#define NV2080_CTRL_GR_INFO_SM_VERSION_5_3 (NV2080_CTRL_GR_INFO_SM_VERSION_5_03) +#define NV2080_CTRL_GR_INFO_SM_VERSION_6_1 (NV2080_CTRL_GR_INFO_SM_VERSION_6_01) +#define NV2080_CTRL_GR_INFO_SM_VERSION_6_2 (NV2080_CTRL_GR_INFO_SM_VERSION_6_02) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_1 (NV2080_CTRL_GR_INFO_SM_VERSION_7_01) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_2 (NV2080_CTRL_GR_INFO_SM_VERSION_7_02) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_3 (NV2080_CTRL_GR_INFO_SM_VERSION_7_03) +#define NV2080_CTRL_GR_INFO_SM_VERSION_7_5 (NV2080_CTRL_GR_INFO_SM_VERSION_7_05) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_2 (NV2080_CTRL_GR_INFO_SM_VERSION_8_02) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_6 (NV2080_CTRL_GR_INFO_SM_VERSION_8_06) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_7 (NV2080_CTRL_GR_INFO_SM_VERSION_8_07) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_8 (NV2080_CTRL_GR_INFO_SM_VERSION_8_08) +#define NV2080_CTRL_GR_INFO_SM_VERSION_8_9 (NV2080_CTRL_GR_INFO_SM_VERSION_8_09) +#define NV2080_CTRL_GR_INFO_SM_VERSION_9_0 (NV2080_CTRL_GR_INFO_SM_VERSION_9_00) + + + +/** + * NV2080_CTRL_CMD_GR_GET_INFO + * + * This command returns gr engine information for the associated GPU. + * Requests to retrieve gr information use a list of one or more + * NV2080_CTRL_GR_INFO structures. + * + * grInfoListSize + * This field specifies the number of entries on the caller's + * grInfoList. + * grInfoList + * This field specifies a pointer in the caller's address space + * to the buffer into which the gr information is to be returned. + * This buffer must be at least as big as grInfoListSize multiplied + * by the size of the NV2080_CTRL_GR_INFO structure. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. When MIG is enabled, this + * is a mandatory parameter. + */ +#define NV2080_CTRL_CMD_GR_GET_INFO (0x20801201U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_GR_GET_INFO_PARAMS { + NvU32 grInfoListSize; + NV_DECLARE_ALIGNED(NvP64 grInfoList, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_GET_INFO_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE + * + * This command is used to set the zcull context switch mode for the specified + * channel. A value of NV_ERR_NOT_SUPPORTED is returned if the + * target channel does not support zcull context switch mode changes. + * + * hChannel + * This parameter specifies the channel handle of + * the channel that is to have it's zcull context switch mode changed. + * hShareClient + * Support for sharing zcull buffers across RM clients is no longer + * supported. To maintain API compatibility, this field must match + * the hClient used in the control call. + * hShareChannel + * This parameter specifies the channel handle of + * the channel with which the zcull context buffer is to be shared. This + * parameter is valid when zcullMode is set to SEPARATE_BUFFER. This + * parameter should be set to the same value as hChannel if no + * sharing is intended. + * zcullMode + * This parameter specifies the new zcull context switch mode. + * Legal values for this parameter include: + * NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_GLOBAL + * This mode is the normal zcull operation where it is not + * context switched and there is one set of globally shared + * zcull memory and tables. This mode is only supported as + * long as all channels use this mode. + * NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_NO_CTXSW + * This mode causes the zcull tables to be reset on a context + * switch, but the zcull buffer will not be saved/restored. + * NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_SEPARATE_BUFFER + * This mode will cause the zcull buffers and tables to be + * saved/restored on context switches. If a share channel + * ID is given (shareChID), then the 2 channels will share + * the zcull context buffers. + */ +#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE (0x20801205U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x5" */ + +typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS { + NvHandle hChannel; + NvHandle hShareClient; + NvHandle hShareChannel; + NvU32 zcullMode; +} NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS; +/* valid zcullMode values */ +#define NV2080_CTRL_CTXSW_ZCULL_MODE_GLOBAL (0x00000000U) +#define NV2080_CTRL_CTXSW_ZCULL_MODE_NO_CTXSW (0x00000001U) +#define NV2080_CTRL_CTXSW_ZCULL_MODE_SEPARATE_BUFFER (0x00000002U) + +/** + * NV2080_CTRL_CMD_GR_GET_ZCULL_INFO + * + * This command is used to query the RM for zcull information that the + * driver will need to allocate and manage the zcull regions. + * + * widthAlignPixels + * This parameter returns the width alignment restrictions in pixels + * used to adjust a surface for proper aliquot coverage (typically + * #TPC's * 16). + * + * heightAlignPixels + * This parameter returns the height alignment restrictions in pixels + * used to adjust a surface for proper aliquot coverage (typically 32). + * + * pixelSquaresByAliquots + * This parameter returns the pixel area covered by an aliquot + * (typically #Zcull_banks * 16 * 16). + * + * aliquotTotal + * This parameter returns the total aliquot pool available in HW. + * + * zcullRegionByteMultiplier + * This parameter returns multiplier used to convert aliquots in a region + * to the number of bytes required to save/restore them. + * + * zcullRegionHeaderSize + * This parameter returns the region header size which is required to be + * allocated and accounted for in any save/restore operation on a region. + * + * zcullSubregionHeaderSize + * This parameter returns the subregion header size which is required to be + * allocated and accounted for in any save/restore operation on a region. + * + * subregionCount + * This parameter returns the subregion count. + * + * subregionWidthAlignPixels + * This parameter returns the subregion width alignment restrictions in + * pixels used to adjust a surface for proper aliquot coverage + * (typically #TPC's * 16). + * + * subregionHeightAlignPixels + * This parameter returns the subregion height alignment restrictions in + * pixels used to adjust a surface for proper aliquot coverage + * (typically 62). + * + * The callee should compute the size of a zcull region as follows. + * (numBytes = aliquots * zcullRegionByteMultiplier + + * zcullRegionHeaderSize + zcullSubregionHeaderSize) + */ +#define NV2080_CTRL_CMD_GR_GET_ZCULL_INFO (0x20801206U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_SUBREGION_SUPPORTED +#define NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS { + NvU32 widthAlignPixels; + NvU32 heightAlignPixels; + NvU32 pixelSquaresByAliquots; + NvU32 aliquotTotal; + NvU32 zcullRegionByteMultiplier; + NvU32 zcullRegionHeaderSize; + NvU32 zcullSubregionHeaderSize; + NvU32 subregionCount; + NvU32 subregionWidthAlignPixels; + NvU32 subregionHeightAlignPixels; +} NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_CTXSW_PM_MODE + * + * This command is used to set the pm context switch mode for the specified + * channel. A value of NV_ERR_NOT_SUPPORTED is returned if the + * target channel does not support pm context switch mode changes. + * + * hChannel + * This parameter specifies the channel handle of + * the channel that is to have its pm context switch mode changed. + * pmMode + * This parameter specifies the new pm context switch mode. + * Legal values for this parameter include: + * NV2080_CTRL_CTXSW_PM_MODE_NO_CTXSW + * This mode says that the pms are not to be context switched. + * NV2080_CTRL_CTXSW_PM_MODE_CTXSW + * This mode says that the pms in Mode-B are to be context switched. + * NV2080_CTRL_CTXSW_PM_MODE_STREAM_OUT_CTXSW + * This mode says that the pms in Mode-E (stream out) are to be context switched. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_CTXSW_PM_MODE (0x20801207U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x7" */ + +typedef struct NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS { + NvHandle hChannel; + NvU32 pmMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS; + +/* valid pmMode values */ +#define NV2080_CTRL_CTXSW_PM_MODE_NO_CTXSW (0x00000000U) +#define NV2080_CTRL_CTXSW_PM_MODE_CTXSW (0x00000001U) +#define NV2080_CTRL_CTXSW_PM_MODE_STREAM_OUT_CTXSW (0x00000002U) + +/* + * NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND + * + * This command is used to set the zcull context switch mode and virtual address + * for the specified channel. A value of NV_ERR_NOT_SUPPORTED is + * returned if the target channel does not support zcull context switch mode + * changes. + * + * hClient + * This parameter specifies the client handle of + * that owns the zcull context buffer. This field must match + * the hClient used in the control call for non-kernel clients. + * hChannel + * This parameter specifies the channel handle of + * the channel that is to have its zcull context switch mode changed. + * vMemPtr + * This parameter specifies the 64 bit virtual address + * for the allocated zcull context buffer. + * zcullMode + * This parameter specifies the new zcull context switch mode. + * Legal values for this parameter include: + * NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_GLOBAL + * This mode is the normal zcull operation where it is not + * context switched and there is one set of globally shared + * zcull memory and tables. This mode is only supported as + * long as all channels use this mode. + * NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_NO_CTXSW + * This mode causes the zcull tables to be reset on a context + * switch, but the zcull buffer will not be saved/restored. + * NV2080_CTRL_GR_SET_CTXSW_ZCULL_MODE_SEPARATE_BUFFER + * This mode will cause the zcull buffers and tables to be + * saved/restored on context switches. If a share channel + * ID is given (shareChID), then the 2 channels will share + * the zcull context buffers. + */ +#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND (0x20801208U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x8" */ + +typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS { + NvHandle hClient; + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 vMemPtr, 8); + NvU32 zcullMode; +} NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS; +/* valid zcullMode values same as above NV2080_CTRL_CTXSW_ZCULL_MODE */ + +/* + * NV2080_CTRL_CMD_GR_CTXSW_PM_BIND + * + * This command is used to set the PM context switch mode and virtual address + * for the specified channel. A value of NV_ERR_NOT_SUPPORTED is + * returned if the target channel does not support PM context switch mode + * changes. + * + * hClient + * This parameter specifies the client handle of + * that owns the PM context buffer. + * hChannel + * This parameter specifies the channel handle of + * the channel that is to have its PM context switch mode changed. + * vMemPtr + * This parameter specifies the 64 bit virtual address + * for the allocated PM context buffer. + * pmMode + * This parameter specifies the new PM context switch mode. + * Legal values for this parameter include: + * NV2080_CTRL_GR_SET_CTXSW_PM_MODE_NO_CTXSW + * This mode says that the pms are not to be context switched + * NV2080_CTRL_GR_SET_CTXSW_PM_MODE_CTXSW + * This mode says that the pms are to be context switched + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_CTXSW_PM_BIND (0x20801209U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x9" */ + +typedef struct NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS { + NvHandle hClient; + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 vMemPtr, 8); + NvU32 pmMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS; +/* valid pmMode values same as above NV2080_CTRL_CTXSW_PM_MODE */ + +/* + * NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP + * + * Send a list of values used to describe GPC/TPC tile mapping tables. + * + * mapValueCount + * This field specifies the number of actual map entries. This count + * should equal the number of TPCs in the system. + * mapValues + * This field is a pointer to a buffer of NvU08 values representing map + * data. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_GR_SET_GPC_TILE_MAP_MAX_VALUES 128U +#define NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP (0x2080120aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0xA" */ + +typedef struct NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS { + NvU32 mapValueCount; + NvU8 mapValues[NV2080_CTRL_GR_SET_GPC_TILE_MAP_MAX_VALUES]; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE + * + * This command is used to set the SMPC context switch mode for the specified + * channel or channel group (TSG). A value of NV_ERR_NOT_SUPPORTED + * is returned if the target channel/TSG does not support SMPC context switch + * mode changes. If a channel is part of a TSG, the user must send in the TSG + * handle and not an individual channel handle, an error will be returned if a + * channel handle is used in this case. + * + * SMPC = SM Performance Counters + * + * hChannel + * This parameter specifies the channel or channel group (TSG) handle + * that is to have its SMPC context switch mode changed. + * If this parameter is set to 0, then the mode below applies to all current + * and future channels (i.e. we will be enabling/disabling global mode) + * smpcMode + * This parameter specifies the new SMPC context switch mode. + * Legal values for this parameter include: + * NV2080_CTRL_GR_SET_CTXSW_SMPC_MODE_NO_CTXSW + * This mode says that the SMPC data is not to be context switched. + * NV2080_CTRL_GR_SET_CTXSW_SMPC_MODE_CTXSW + * This mode says that the SMPC data is to be context switched. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE (0x2080120eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0xE" */ + +typedef struct NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS { + NvHandle hChannel; + NvU32 smpcMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS; + +/* valid smpcMode values */ +#define NV2080_CTRL_CTXSW_SMPC_MODE_NO_CTXSW (0x00000000U) +#define NV2080_CTRL_CTXSW_SMPC_MODE_CTXSW (0x00000001U) + +/* + * NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS + * + * This command returns an array of the mappings between SMs and GPC/TPCs. + * + * smId + * An array of the mappings between SMs and GPC/TPCs. + * smCount + * Returns the number of valid mappings in the array. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS (0x2080120fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_MAX_SM_COUNT 144U +#define NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS { + struct { + NvU32 gpcId; + NvU32 tpcId; + } smId[NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_MAX_SM_COUNT]; + NvU32 smCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE + * + * This command is used to set the preemption context switch mode for the specified + * channel. A value of NV_ERR_NOT_SUPPORTED is returned if the + * target channel does not support preemption context switch mode changes. + * + * flags + * This field specifies flags for the preemption mode changes. + * These flags can tell callee which mode is valid in the call + * since we handle graphics and/or compute + * hChannel + * This parameter specifies the channel handle of the channel + * that is to have it's preemption context switch mode set. + * gfxpPreemptMode + * This parameter specifies the new Graphics preemption context switch + * mode. Legal values for this parameter include: + * NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_WFI + * This mode is the normal wait-for-idle context switch mode. + * NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP + * This mode causes the graphics engine to allow preempting the + * channel mid-triangle. + * NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP_POOL + * This mode causes the graphics engine to use a shared pool of buffers + * to support GfxP with lower memory overhead + * cilpPreemptMode + * This parameter specifies the new Compute preemption context switch + * mode. Legal values for this parameter include: + * NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_WFI + * This mode is the normal wait-for-idle context switch mode. + * NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CTA + * This mode causes the compute engine to allow preempting the channel + * at the instruction level. + * NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CILP + * This mode causes the compute engine to allow preempting the channel + * at the instruction level. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE (0x20801210U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x10" */ + +typedef struct NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS { + NvU32 flags; + NvHandle hChannel; + NvU32 gfxpPreemptMode; + NvU32 cilpPreemptMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS; + +/* valid preemption flags */ +#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP 0:0 +#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_IGNORE (0x00000000U) +#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_SET (0x00000001U) +#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP 1:1 +#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_IGNORE (0x00000000U) +#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_SET (0x00000001U) + +/* valid Graphics mode values */ +#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_WFI (0x00000000U) +#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP (0x00000001U) +#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP_POOL (0x00000002U) + +/* valid Compute mode values */ +#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_WFI (0x00000000U) +#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CTA (0x00000001U) +#define NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CILP (0x00000002U) + +/* valid preemption buffers */ +typedef enum NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS { + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_MAIN = 0, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SPILL = 1, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_PAGEPOOL = 2, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_BETACB = 3, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_RTV = 4, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL = 5, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL = 6, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL_CPU = 7, + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END = 8, +} NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS; + +/* + * NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND + * + * This command is used to set the preemption context switch mode and virtual + * addresses of the preemption buffers for the specified channel. A value of + * NV_ERR_NOT_SUPPORTED is returned if the target channel does not + * support preemption context switch mode changes. + * + * flags + * This field specifies flags for the preemption mode changes. + * These flags can tell callee which mode is valid in the call + * since we handle graphics and/or compute + * hClient + * This parameter specifies the client handle of + * that owns the preemption context buffer. + * hChannel + * This parameter specifies the channel handle of the channel + * that is to have its preemption context switch mode set. + * vMemPtr + * This parameter specifies the 64 bit virtual address + * for the allocated preemption context buffer. + * gfxpPreemptMode + * This parameter specifies the new Graphics preemption context switch + * mode. Legal values for this parameter include: + * NV2080_CTRL_CTXSW_PREEMPTION_MODE_GFX_WFI + * This mode is the normal wait-for-idle context switch mode. + * NV2080_CTRL_CTXSW_PREEMPTION_MODE_GFX_GFXP + * This mode causes the graphics engine to allow preempting the + * channel mid-triangle. + * cilpPreemptMode + * This parameter specifies the new Compute preemption context switch + * mode. Legal values for this parameter include: + * NV2080_CTRL_CTXSW_PREEMPTION_MODE_COMPUTE_WFI + * This mode is the normal wait-for-idle context switch mode. + * NV2080_CTRL_CTXSW_PREEMPTION_MODE_COMPUTE_CTA + * This mode causes the compute engine to allow preempting the channel + * at the instruction level. + * NV2080_CTRL_CTXSW_PREEMPTION_MODE_COMPUTE_CILP + * This mode causes the compute engine to allow preempting the channel + * at the instruction level. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND (0x20801211U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x11" */ + +typedef struct NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS { + NvU32 flags; + NvHandle hClient; + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 vMemPtrs[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END], 8); + NvU32 gfxpPreemptMode; + NvU32 cilpPreemptMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS; +/* valid mode and flag values same as above NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE */ + +/* + * NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE + * + * This command is used to apply the WAR for PC sampling to avoid hang in + * multi-ctx scenario. + * + * hChannel + * This parameter specifies the channel or channel group (TSG) handle + * that is to have its PC Sampling mode changed. + * samplingMode + * This parameter specifies whether sampling is turned ON or OFF. + * Legal values for this parameter include: + * NV2080_CTRL_GR_SET_PC_SAMPLING_MODE_DISABLED + * This mode says that PC sampling is disabled for current context. + * NV2080_CTRL_GR_SET_PC_SAMPLING_MODE_ENABLED + * This mode says that PC sampling is disabled for current context. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE (0x20801212U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x12" */ + +typedef struct NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS { + NvHandle hChannel; + NvU32 samplingMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS; + +/* valid samplingMode values */ +#define NV2080_CTRL_PC_SAMPLING_MODE_DISABLED (0x00000000U) +#define NV2080_CTRL_PC_SAMPLING_MODE_ENABLED (0x00000001U) + +/* + * NV2080_CTRL_CMD_GR_GET_ROP_INFO + * + * Gets information about ROPs including the ROP unit count and information + * about ROP operations per clock. + * + * ropUnitCount + * The count of active ROP units. + * ropOperationsFactor. + * The number of ROP operations per clock for a single ROP unit. + * ropOperationsCount + * The number of ROP operations per clock across all active ROP units. + */ +#define NV2080_CTRL_CMD_GR_GET_ROP_INFO (0x20801213U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV2080_CTRL_GR_GET_ROP_INFO_PARAMS { + NvU32 ropUnitCount; + NvU32 ropOperationsFactor; + NvU32 ropOperationsCount; +} NV2080_CTRL_GR_GET_ROP_INFO_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GR_GET_CTXSW_STATS + * + * This command is used to get the context switch statistics. The user can + * also add a flag to tell RM to reset the stats counters back to 0. + * + * hChannel + * This parameter specifies the channel or channel group (TSG) handle + * that is to have the stats returned. Note, must be the TSG handle if + * channel is part of a TSG. + * flags + * This parameter specifies processing flags. See possible flags below. + * saveCnt + * This parameter returns the number of saves on the channel. + * restoreCnt + * This parameter returns the number of restores on the channel. + * wfiSaveCnt + * This parameter returns the number of WFI saves on the channel. + * ctaSaveCnt + * This parameter returns the number of CTA saves on the channel. + * cilpSaveCnt + * This parameter returns the number of CILP saves on the channel. + * gfxpSaveCnt + * This parameter returns the number of GfxP saves on the channel. + */ +#define NV2080_CTRL_CMD_GR_GET_CTXSW_STATS (0x20801215U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x15" */ + +typedef struct NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS { + NvHandle hChannel; + NvU32 flags; + NvU32 saveCnt; + NvU32 restoreCnt; + NvU32 wfiSaveCnt; + NvU32 ctaSaveCnt; + NvU32 cilpSaveCnt; + NvU32 gfxpSaveCnt; +} NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS; +/* valid GET_CTXSW_STATS flags settings */ +#define NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET 0:0 +#define NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_FALSE (0x00000000U) +#define NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_TRUE (0x00000001U) + + + +/* + * NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE + * + * This command provides the size, alignment of all context buffers including global and + * local context buffers which has been created & will be mapped on a context + * + * hChannel [IN] + * This parameter specifies the channel or channel group (TSG) handle + * totalBufferSize [OUT] + * This parameter returns the total context buffers size. + */ +#define NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE (0x20801218U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS { + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 totalBufferSize, 8); +} NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS; + +/* + * NV2080_CTRL_GR_CTX_BUFFER_INFO + * alignment + * Specifies the alignment requirement for each context buffer + * size + * Aligned size of context buffer + * bufferHandle [deprecated] + * Opaque pointer to memdesc. Used by kernel clients for tracking purpose only. + * pageCount + * allocation size in the form of pageCount + * physAddr + * Physical address of the buffer first page + * bufferType + * NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID type of this buffer + * aperture + * allocation aperture. Could be SYSMEM, VIDMEM, UNKNOWN + * kind + * PTE kind of this allocation. + * pageSize + * Page size of the buffer. + * bIsContigous + * States if physical allocation for this buffer is contiguous. PageSize will + * have no meaning if this flag is set. + * bGlobalBuffer + * States if a defined buffer is global as global buffers need to be mapped + * only once in TSG. + * bLocalBuffer + * States if a buffer is local to a channel. + * bDeviceDescendant + * TRUE if the allocation is a constructed under a Device or Subdevice. + * uuid + * SHA1 UUID of the Device or Subdevice. Valid when deviceDescendant is TRUE. + */ +typedef struct NV2080_CTRL_GR_CTX_BUFFER_INFO { + NV_DECLARE_ALIGNED(NvU64 alignment, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NV_DECLARE_ALIGNED(NvP64 bufferHandle, 8); + NV_DECLARE_ALIGNED(NvU64 pageCount, 8); + NV_DECLARE_ALIGNED(NvU64 physAddr, 8); + NvU32 bufferType; + NvU32 aperture; + NvU32 kind; + NvU32 pageSize; + NvBool bIsContigous; + NvBool bGlobalBuffer; + NvBool bLocalBuffer; + NvBool bDeviceDescendant; + NvU8 uuid[16]; +} NV2080_CTRL_GR_CTX_BUFFER_INFO; +typedef struct NV2080_CTRL_GR_CTX_BUFFER_INFO *PNV2080_CTRL_GR_CTX_BUFFER_INFO; + +#define NV2080_CTRL_GR_MAX_CTX_BUFFER_COUNT 64U + +/* + * NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_INFO + * + * This command provides the size, alignment of all context buffers including global and + * local context buffers which has been created & will be mapped on a context. + * If the client invoking the command is a kernel client, the buffers are retained. + * + * hUserClient [IN] + * This parameter specifies the client handle that owns this channel. + * hChannel [IN] + * This parameter specifies the channel or channel group (TSG) handle + * bufferCount [OUT] + * This parameter specifies the number of entries in ctxBufferInfo filled + * by the command. + * ctxBufferInfo [OUT] + * Array of context buffer info containing alignment, size etc. + */ +#define NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_INFO (0x20801219U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS { + NvHandle hUserClient; + NvHandle hChannel; + NvU32 bufferCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTX_BUFFER_INFO ctxBufferInfo[NV2080_CTRL_GR_MAX_CTX_BUFFER_COUNT], 8); +} NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS; + +// Aperture flags +#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_UNKNWON ADDR_UNKNOWN +#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_SYSMEM ADDR_SYSMEM +#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_FBMEM ADDR_FBMEM + +/* + * NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER + * This command returns the global logical ordering of SM w.r.t GPCs/TPCs. + * + * NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS + * This structure holds the TPC/SM ordering info. + * + * gpcId + * Logical GPC Id. + * This is the ordering of enabled GPCs post floor sweeping. + * The GPCs are numbered from 0 to N-1, where N is the enabled GPC count. + * + * localTpcId + * Local Logical TPC Id. + * This is the ordering of enabled TPCs within a GPC post floor sweeping. + * This ID is used in conjunction with the gpcId. + * The TPCs are numbered from 0 to N-1, where N is the enabled TPC count for the given GPC. + * + * localSmId + * Local Logical SM Id. + * This is the ordering of enabled SMs within a TPC post floor sweeping. + * This ID is used in conjunction with the localTpcId. + * The SMs are numbered from 0 to N-1, where N is the enabled SM count for the given TPC. + * + * globalTpcId + * Global Logical TPC Id. + * This is the ordering of all enabled TPCs in the GPU post floor sweeping. + * The TPCs are numbered from 0 to N-1, where N is the enabled TPC count across all GPCs + * + * globalSmId + * Global Logical SM Id array. + * This is the global ordering of all enabled SMs in the GPU post floor sweeping. + * The SMs are numbered from 0 to N-1, where N is the enabled SM count across all GPCs. + * + * virtualGpcId + * Virtual GPC Id. + * This is the ordering of enabled GPCs post floor sweeping (ordered in increasing + * number of TPC counts) The GPCs are numbered from 0 to N-1, where N is the + * enabled GPC count and 8-23 for singleton TPC holders. + * + * migratableTpcId + * Migratable TPC Id. + * This is the same as the Local Tpc Id for virtual GPC 0-8 (true physical gpcs) and 0 for + * virtual gpcs 8-23 that represent singleton tpcs. + * + * numSm + * Enabled SM count across all GPCs. + * This represent the valid entries in the globalSmId array + * + * numTpc + * Enabled TPC count across all GPCs. + * + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + */ +#define NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER (0x2080121bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER_MAX_SM_COUNT 512U + +#define NV2080_CTRL_GR_DISABLED_SM_VGPC_ID 0xFFU + +#define NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x1BU) + +typedef struct NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS { + struct { + NvU16 gpcId; + NvU16 localTpcId; + NvU16 localSmId; + NvU16 globalTpcId; + NvU16 virtualGpcId; + NvU16 migratableTpcId; + } globalSmId[NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER_MAX_SM_COUNT]; + + NvU16 numSm; + NvU16 numTpc; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS; + +/* +* NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL +* +* This command gives current resident channel on GR engine +* +* chID [OUT] +* RM returns current resident channel on GR engine +* grRouteInfo [IN] +* This parameter specifies the routing information used to +* disambiguate the target GR engine. +*/ +#define NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL (0x2080121cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x1C" */ + +typedef struct NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS { + NvU32 chID; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA + * + * This command provides the _VAT_ALARM data i.e. error and warning, counter and + * timestamps along with max GPC and TPC per GPC count. + * + * smVatAlarm [OUT] + * VAT Alarm data array per SM containing per GPC per TPC, counter and + * timestamp values for error and warning alarms. + * maxGpcCount [OUT] + * This parameter returns max GPC count. + * maxTpcPerGpcCount [OUT] + * This parameter returns the max TPC per GPC count. + */ +#define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_GPC_COUNT 10U +#define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_TPC_PER_GPC_COUNT 10U + +#define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA (0x2080121dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x1D" */ + +typedef struct NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC { + NV_DECLARE_ALIGNED(NvU64 errorCounter, 8); + NV_DECLARE_ALIGNED(NvU64 errorTimestamp, 8); + NV_DECLARE_ALIGNED(NvU64 warningCounter, 8); + NV_DECLARE_ALIGNED(NvU64 warningTimestamp, 8); +} NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC; + +typedef struct NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC tpc[NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_TPC_PER_GPC_COUNT], 8); +} NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC; + +typedef struct NV2080_CTRL_GR_VAT_ALARM_DATA { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC gpc[NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_GPC_COUNT], 8); +} NV2080_CTRL_GR_VAT_ALARM_DATA; + +typedef struct NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_VAT_ALARM_DATA smVatAlarm, 8); + NvU32 maxGpcCount; + NvU32 maxTpcPerGpcCount; +} NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS; +typedef struct NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS *PNV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE + * + * This command provides the size of GR attribute buffer. + * + * attribBufferSize [OUT] + * This parameter returns the attribute buffer size. + */ +#define NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE (0x2080121eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x1EU) + +typedef struct NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS { + NvU32 attribBufferSize; +} NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE + * + * This API queries size parameters for a request maximum graphics preemption + * pool size. It is only available to kernel callers + * + * NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS + * struct to return the size parameters + * + * maxSlots + * Input specifying the maximum number of slots, RM will calculate the output + * parameters based on this. Must be non-zero + * ctrlStructSize + * Output indicating the required size in bytes of the control structure to + * support a pool of maxSlots size. + * ctrlStructAlign + * Output indicating the required alignment of the control structure + * poolSize + * Output indicating the required size in bytes of the GfxP Pool. + * poolAlign + * Output indicating the required alignment of the GfxP Pool + * slotStride + * The number of bytes in each slot, i * slotStride gives the offset from the + * base of the pool to a given slot + */ +#define NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE (0x2080121fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x1F" */ + +typedef struct NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS { + NvU32 maxSlots; + NvU32 slotStride; + NV_DECLARE_ALIGNED(NvU64 ctrlStructSize, 8); + NV_DECLARE_ALIGNED(NvU64 ctrlStructAlign, 8); + NV_DECLARE_ALIGNED(NvU64 poolSize, 8); + NV_DECLARE_ALIGNED(NvU64 poolAlign, 8); +} NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE + * + * This API takes a CPU pointer to a GFxP Pool Control Structure and does the + * required onetime initialization. It should be called once and only once + * before a pool is used. It is only accessible to kernel callers. + * + * NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS + * struct to hand in the required info to RM + * + * pControlStructure + * This input is the kernel CPU pointer to the control structure. + */ +#define NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE (0x20801220U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x20" */ + +typedef struct NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8); + NvU32 maxSlots; +} NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS; + +#define NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS 64U + +/* + * NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS + * + * This API adds a list of buffer slots to a given control structure. It can + * only be called when no channel using the given pool is running or may become + * running for the duration of this call. If more slots are added than there + * is room for in the control structure the behavior is undefined. It is only + * accessible to kernel callers. + * + * NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS + * + * pControlStructure + * This input is the kernel CPU pointer to the control structure + * numSlots + * This input indicates how many slots are being added and are contained in the slots parameter + * slots + * This input contains an array of the slots to be added to the control structure + */ +#define NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS (0x20801221U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x21" */ + +typedef struct NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8); + NvU32 numSlots; + NvU32 slots[NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS]; +} NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS + * + * This API removes buffer slots from a given control structure. It can + * only be called when no channel using the given pool is running or may become + * running for the duration of this call. It can operate in two modes, either + * it will a specified number of slots, or a specified list of slots. + * + * It is only accessible to kernel callers. + * + * NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS_PARAMS + * + * pControlStructure + * This input is the kernel CPU pointer to the control structure + * numSlots + * This input indicates how many slots are being removed. if + * bRemoveSpecificSlots is true, then it also indicates how many entries in + * the slots array are populated. + * slots + * This array is either an input or output. If bRemoveSpecificSlots is true, + * then this will contain the list of slots to remove. If it is false, then + * it will be populated by RM with the indexes of the slots that were + * removed. + * bRemoveSpecificSlots + * This input determines which mode the call will run in. If true the caller + * will specify the list of slots they want removed, if any of those slots + * are not on the freelist, the call will fail. If false they only specify + * the number of slots they want removed and RM will pick up to that + * many. If there are not enough slots on the freelist to remove the + * requested amount, RM will return the number it was able to remove. + */ +#define NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS (0x20801222U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x22" */ + +typedef struct NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8); + NvU32 numSlots; + NvU32 slots[NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS]; + NvBool bRemoveSpecificSlots; +} NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS; + + + +#define NV2080_CTRL_CMD_GR_GET_CAPS_V2 (0x20801227U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x27U) + +typedef NV0080_CTRL_GR_GET_CAPS_V2_PARAMS NV2080_CTRL_GR_GET_CAPS_V2_PARAMS; + +#define NV2080_CTRL_CMD_GR_GET_INFO_V2 (0x20801228U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID (0x28U) + +typedef NV0080_CTRL_GR_GET_INFO_V2_PARAMS NV2080_CTRL_GR_GET_INFO_V2_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GR_GET_GPC_MASK + * + * This command returns a mask of enabled GPCs for the associated subdevice. + * + * grRouteInfo[IN] + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + * gpcMask[OUT] + * This parameter returns a mask of enabled GPCs. Each GPC has an ID + * that's equivalent to the corresponding bit position in the mask. + */ +#define NV2080_CTRL_CMD_GR_GET_GPC_MASK (0x2080122aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GPC_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_GPC_MASK_PARAMS_MESSAGE_ID (0x2AU) + +typedef struct NV2080_CTRL_GR_GET_GPC_MASK_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvU32 gpcMask; +} NV2080_CTRL_GR_GET_GPC_MASK_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_TPC_MASK + * + * This command returns a mask of enabled TPCs for a specified GPC. + * + * grRouteInfo[IN] + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + * gpcId[IN] + * This parameter specifies the GPC for which TPC information is + * to be retrieved. If the GPC with this ID is not enabled this command + * will return an tpcMask value of zero. + * + * tpcMask[OUT] + * This parameter returns a mask of enabled TPCs for the specified GPC. + * Each TPC has an ID that's equivalent to the corresponding bit + * position in the mask. + */ +#define NV2080_CTRL_CMD_GR_GET_TPC_MASK (0x2080122bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_TPC_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_TPC_MASK_PARAMS_MESSAGE_ID (0x2BU) + +typedef struct NV2080_CTRL_GR_GET_TPC_MASK_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvU32 gpcId; + NvU32 tpcMask; +} NV2080_CTRL_GR_GET_TPC_MASK_PARAMS; + +#define NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x2080122cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x2C" */ + +typedef NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID (0x2CU) + +typedef struct NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS params, 8); +} NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES + * + * This command is used to provide the caller with the alignment and size + * of the context save region for an engine + * + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * engineId + * This parameter is an input parameter specifying the engineId for which + * the alignment/size is requested. + * alignment + * This parameter is an output parameter which will be filled in with the + * minimum alignment requirement. + * size + * This parameter is an output parameter which will be filled in with the + * minimum size of the context save region for the engine. + * bInfoPopulated + * This parameter will be set if alignment and size are already set with + * valid values from a previous call. + */ + +#define NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES (0x2080122dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID (0x2DU) + +typedef struct NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvU32 engineId; + NvU32 alignment; + NvU32 size; + NvBool bInfoPopulated; +} NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER + * + * This command provides an interface to retrieve the speed select values of + * various instruction types. + * + * grRouteInfo[IN] + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + * imla0[OUT] + * The current speed select for IMLA0. + * + * fmla16[OUT] + * The current speed select for FMLA16. + * + * dp[OUT] + * The current speed select for DP. + * + * fmla32[OUT] + * The current speed select for FMLA32. + * + * ffma[OUT] + * The current speed select for FFMA. + * + * imla1[OUT] + * The current speed select for IMLA1. + * + * imla2[OUT] + * The current speed select for IMLA2. + * + * imla3[OUT] + * The current speed select for IMLA3. + * + * imla4[OUT] + * The current speed select for IMLA4. + */ +#define NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER (0x20801230U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_2 (0x1U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_4 (0x2U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_8 (0x3U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_16 (0x4U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_32 (0x5U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_64 (0x6U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_2 (0x1U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_4 (0x2U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_8 (0x3U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_16 (0x4U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_32 (0x5U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_REDUCED_SPEED (0x1U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_2 (0x1U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_4 (0x2U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_8 (0x3U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_16 (0x4U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_32 (0x5U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_2 (0x1U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_4 (0x2U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_8 (0x3U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_16 (0x4U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_32 (0x5U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_2 (0x1U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_4 (0x2U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_8 (0x3U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_16 (0x4U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_32 (0x5U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_64 (0x6U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_2 (0x1U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_4 (0x2U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_8 (0x3U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_16 (0x4U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_32 (0x5U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_64 (0x6U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_2 (0x1U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_4 (0x2U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_8 (0x3U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_16 (0x4U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_32 (0x5U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_64 (0x6U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_FULL_SPEED (0x0U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_2 (0x1U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_4 (0x2U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_8 (0x3U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_16 (0x4U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_32 (0x5U) +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_64 (0x6U) + +#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x30U) + +typedef struct NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvU8 imla0; + NvU8 fmla16; + NvU8 dp; + NvU8 fmla32; + NvU8 ffma; + NvU8 imla1; + NvU8 imla2; + NvU8 imla3; + NvU8 imla4; +} NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID + * + * *DEPRECATED* Use NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID_V2 instead + * + * This command is used to create a FECS bind-point to an event buffer that + * is filtered by UID. + * + * hEventBuffer[IN] + * The event buffer to bind to + * + * recordSize[IN] + * The size of the FECS record in bytes + * + * levelOfDetail[IN] + * One of NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_: + * FULL: Report all CtxSw events + * SIMPLE: Report ACTIVE_REGION_START and ACTIVE_REGION_END only + * COMPAT: Events that KMD is interested in (for backwards compatibility) + * CUSTOM: Report events in the eventFilter field + * NOTE: RM may override the level-of-detail depending on the caller + * + * eventFilter[IN] + * Bitmask of events to report if levelOfDetail is CUSTOM + * + * bAllUsers[IN] + * Only report FECS CtxSw data for the current user if false, for all users if true + */ + +#define NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID (0x20801231U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD { + NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_FULL = 0, + NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_SIMPLE = 1, + NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_COMPAT = 2, + NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_CUSTOM = 3, +} NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD; + +#define NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS_MESSAGE_ID (0x31U) + +typedef struct NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS { + NvHandle hEventBuffer; + NvU32 recordSize; + NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD levelOfDetail; + NvU32 eventFilter; + NvBool bAllUsers; +} NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK + * + * This command returns a mask of physical GPC Ids for the associated syspipe + * + * physSyspipeId[IN] + * This parameter specifies syspipe for which phys GPC mask is requested + * + * gpcMask[OUT] + * This parameter returns a mask of mapped GPCs to provided syspipe. + * Each GPC-ID has a corresponding bit position in the mask. + */ +#define NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK (0x20801232U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS_MESSAGE_ID (0x32U) + +typedef struct NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS { + NvU32 physSyspipeId; + NvU32 gpcMask; +} NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_PPC_MASK + * + * This command returns a mask of enabled PPCs for a specified GPC. + * + * grRouteInfo[IN] + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + * gpcId[IN] + * This parameter specifies the GPC for which TPC information is + * to be retrieved. If the GPC with this ID is not enabled this command + * will return an ppcMask value of zero. + * + * ppcMask[OUT] + * This parameter returns a mask of enabled PPCs for the specified GPC. + * Each PPC has an ID that's equivalent to the corresponding bit + * position in the mask. + */ +#define NV2080_CTRL_CMD_GR_GET_PPC_MASK (0x20801233U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_PPC_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_PPC_MASK_PARAMS_MESSAGE_ID (0x33U) + +typedef struct NV2080_CTRL_GR_GET_PPC_MASK_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvU32 gpcId; + NvU32 ppcMask; +} NV2080_CTRL_GR_GET_PPC_MASK_PARAMS; + +#define NV2080_CTRL_CMD_GR_GET_NUM_TPCS_FOR_GPC (0x20801234U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS_MESSAGE_ID (0x34U) + +typedef struct NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS { + NvU32 gpcId; + NvU32 numTpcs; +} NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_CTXSW_MODES + * + * This command is used to get context switch modes for the specified + * channel. A value of NV_ERR_NOT_SUPPORTED is returned if the + * target channel does not support context switch mode changes. + * + * hChannel + * This parameter specifies the channel handle of + * the channel that is to have its context switch modes retrieved. + * zcullMode + * See NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE for possible return values + * pmMode + * See NV2080_CTRL_CMD_GR_CTXSW_PM_MODE for possible return values + * smpcMode + * See NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE for possible return values + * cilpPreemptMode + * See NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE for possible return values + * gfxpPreemptMode + * See NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE for possible return values + */ +#define NV2080_CTRL_CMD_GR_GET_CTXSW_MODES (0x20801235U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID (0x35U) + +typedef struct NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS { + NvHandle hChannel; + NvU32 zcullMode; + NvU32 pmMode; + NvU32 smpcMode; + NvU32 cilpPreemptMode; + NvU32 gfxpPreemptMode; +} NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP + * + * Get a list of values used to describe GPC/TPC tile mapping tables. + * + * mapValueCount + * This field specifies the number of actual map entries. This count + * should equal the number of TPCs in the system. + * mapValues + * This field is a pointer to a buffer of NvU08 values representing map + * data. + * grRouteInfo + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP (0x20801236U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x36" */ + +typedef NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP_FINN_PARAMS_MESSAGE_ID (0x36U) + +typedef struct NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP_FINN_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS params, 8); +} NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP_FINN_PARAMS; + + + +/* + * NV2080_CTRL_CMD_GR_GET_ZCULL_MASK + * + * This command returns a mask of enabled ZCULLs for a specified GPC. + * + * gpcId[IN] + * This parameter, physical GPC index, specifies the GPC for which ZCULL + * information is to be retrieved. If the GPC with this ID is not enabled + * this command will return a zcullMask value of zero. + * + * zcullMask[OUT] + * This parameter returns a mask of enabled ZCULLs for the specified GPC. + * Each ZCULL has an ID that's equivalent to the corresponding bit + * position in the mask. + */ + +#define NV2080_CTRL_CMD_GR_GET_ZCULL_MASK (0x20801237U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS_MESSAGE_ID (0x37U) + +typedef struct NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS { + NvU32 gpcId; + NvU32 zcullMask; +} NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID_V2 + * + * This command is used to create a FECS bind-point to an event buffer that + * is filtered by UID. + * + * hEventBuffer[IN] + * The event buffer to bind to + * + * recordSize[IN] + * The size of the FECS record in bytes + * + * levelOfDetail[IN] + * One of NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_: + * FULL: Report all CtxSw events + * SIMPLE: Report ACTIVE_REGION_START and ACTIVE_REGION_END only + * COMPAT: Events that KMD is interested in (for backwards compatibility) + * CUSTOM: Report events in the eventFilter field + * NOTE: RM may override the level-of-detail depending on the caller + * + * eventFilter[IN] + * Bitmask of events to report if levelOfDetail is CUSTOM + * + * bAllUsers[IN] + * Only report FECS CtxSw data for the current user if false, for all users if true + * + * reasonCode [OUT] + * Reason for failure + */ +#define NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID_V2 (0x20801238U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE { + NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NONE = 0, + NV2080_CTRL_GR_FECS_BIND_REASON_CODE_GPU_TOO_OLD = 1, + NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED_GPU = 2, + NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED = 3, + NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_ADMIN = 4, + NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_CAPABILITY = 5, +} NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE; + +#define NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS_MESSAGE_ID (0x38U) + +typedef struct NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS { + NvHandle hEventBuffer; + NvU32 recordSize; + NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD levelOfDetail; + NvU32 eventFilter; + NvBool bAllUsers; + NvU32 reasonCode; +} NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS; + +/* + * NV2080_CTRL_CMD_GR_GET_GFX_GPC_AND_TPC_INFO + * + * This command grabs information on GFX capable GPC's and TPC's for a specifc GR engine + * + * grRouteInfo[IN] + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + * + * physGfxGpcMask [OUT] + * Physical mask of Gfx capable GPC's + * + * numGfxTpc [OUT] + * Total number of Gfx capable TPC's + */ +#define NV2080_CTRL_CMD_GR_GET_GFX_GPC_AND_TPC_INFO (0x20801239U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS_MESSAGE_ID (0x39U) + +typedef struct NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvU32 physGfxGpcMask; + NvU32 numGfxTpc; +} NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS; + +/* _ctrl2080gr_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h new file mode 100644 index 0000000..481b59a --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h @@ -0,0 +1,263 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080grmgr.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX grmgr control commands and parameters */ + +// +// NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO +// +// This control call works as a batched query interface where we +// have multiple different queries that can be passed in +// and RM will return the associated data and status type +// If there is any error in NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS, +// we will immediately fail the call. +// However, if there is an error in the query-specific calls, we will +// log the error and march on. +// +// NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS +// numQueries[IN] +// - Specifies the number of valid queries that the caller will be passing in +// +// Possible status values returned are: +// NV_OK +// NV_ERR_INVALID_ARGUMENT +// NV_ERR_INVALID_STATE +// +#define NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO (0x20803801) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GRMGR_INTERFACE_ID << 8) | NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_MESSAGE_ID" */ + +// Max number of queries that can be batched in a single call to NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO +#define NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES 96 + +// +// Preference is to keep max.size of union at 24 bytes (i.e. 6 32-bit members) +// so that the size of entire query struct is maintained at 32 bytes, to ensure +// that overall params struct does not exceed 4kB +// +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_MAX_SIZE 32 +#define NV2080_CTRL_GRMGR_MAX_SMC_IDS 8 + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS + * gpcCount[OUT] + * - No. of logical/local GPCs which client can use to create the + * logical/local mask respectively + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS { + NvU32 gpcCount; // param[out] - logical/local GPC mask +} NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS + * gpcId[IN] + * - Logical/local GPC ID + * chipletGpcMap[OUT] + * - Returns chiplet GPC ID for legacy case and device monitoring client + * - Returns local GPC ID (== input gpcId) for SMC client + * - Does not support DM attribution case + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS { + NvU32 gpcId; // param[in] - logical/local GPC ID + NvU32 chipletGpcMap; // param[out] - chiplet GPC ID +} NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS + * gpcId[IN] + * - Logical/local GPC ID + * tpcMask[OUT] + * - Returns physical TPC mask for legacy, DM client and SMC cases + * - Does not support DM attribution case + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS { + NvU32 gpcId; // param[in] - logical/local GPC ID + NvU32 tpcMask; // param[out] - physical TPC mask +} NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS + * gpcId[IN] + * - Logical/local GPC ID + * ppcMask[OUT] + * - Returns physical PPC mask for legacy, DM client and SMC cases + * - Does not support DM attribution case + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS { + NvU32 gpcId; // param[in] - logical/local GPC ID + NvU32 ppcMask; // param[out] - physical PPC mask +} NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS; + +/*! + * !!! DEPRECATED - This query will return NV_ERR_NOT_SUPPORTED since deleting + * it would break driver compatibility !!! + * + * NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS + * swizzId[IN] + * - Swizz ID of partition + * - A DM client with an invalid swizz ID, will fail this call + * - This parameter is not compulsory for an SMC client; the subscription + * itself will do the necessary validation. + * gpcId[IN] + * - Logical/local GPC ID + * chipletGpcMap[OUT] + * - Returns chiplet GPC ID for legacy case and device monitoring client + * - Returns local GPC ID (== input gpcId) for SMC client + * - Does not support non-attribution case for DM client + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS { + NvU32 swizzId; // param[in] - swizz ID of partition + NvU32 gpcId; // param[in] - logical/local GPC ID + NvU32 chipletGpcMap; // param[out] - chiplet GPC ID +} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS + * gpcId[IN] + * - Logical/local GPC ID + * ropMask[OUT] + * - Returns physical ROP mask for legacy, DM client + * - Returns logical ROP mask for SMC + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS { + NvU32 gpcId; // param[in] - logical/local GPC ID + NvU32 ropMask; // param[out] - physical ROP mask +} NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS + * chipletSyspipeMask [OUT] + * - Mask of chiplet SMC-IDs for DM client attribution case + * - Mask of local SMC-IDs for SMC client + * - Legacy case returns 1 GR + * - Does not support attribution case for DM client + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS { + NvU32 chipletSyspipeMask; // param[out] - Mask of chiplet SMC IDs +} NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS + * swizzId[IN] + * - Swizz ID of partition + * - A DM client with an invalid swizz ID, will fail this call + * physSyspipeId[GRMGR_MAX_SMC_IDS] [OUT] + * - Physical SMC-IDs mapped to partition local idx for DM client attribution case + * - Does not support non-attribution case for DM client, SMC clients, legacy case + * physSyspipeIdCount[OUT] + * - Valid count of physSmcIds which has been populated in above array. + * - Failure case will return 0 + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS { + NvU16 swizzId; // param[in] - swizz ID of partition + NvU16 physSyspipeIdCount; // param[out] - Count of physSmcIds in above array + NvU8 physSyspipeId[NV2080_CTRL_GRMGR_MAX_SMC_IDS]; // param[out] - physical/local SMC IDs +} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS + * swizzId[IN] + * - Swizz ID of partition + * - Mandatory parameter + * - A DM client with an invalid swizz ID, will fail this call + * grIdx[IN] + * - Local grIdx for a partition + * - Mandatory parameter + * gpcEnMask[OUT] + * - Logical enabled GPC mask associated with requested grIdx of the partition i.e swizzid->engineId->gpcMask + * - These Ids should be used as input further + * - Does not support non-attribution case for DM client, SMC clients, legacy case + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS { + NvU32 swizzId; // param[in] - swizz ID of partition + NvU32 grIdx; // param[in] - partition local GR ID + NvU32 gpcEnMask; // param[out] - logical enabled GPC mask +} NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS; + +/*! + * NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID + * syspipeId[OUT] + * - Partition-local GR idx for client subscribed to exec partition + * - Does not support legacy case, DM client, or SMC client subscribed only to partition + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS { + NvU32 syspipeId; // param[out] - partition-local Gr idx +} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS; + +/*! + * queryType[IN] + * - Use queryType defines to specify what information is being requested + * status[OUT] + * - Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS { + NvU16 queryType; + NvU8 reserved[2]; // To keep the struct aligned for now and available for future use (if needed) + NvU32 status; + union { + NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS gpcCountData; + NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS chipletGpcMapData; + NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS tpcMaskData; + NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS ppcMaskData; + NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS partitionGpcMapData; + NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS syspipeMaskData; + NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS partitionChipletSyspipeData; + NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS dmGpcMaskData; + NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS partitionSyspipeIdData; + NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS ropMaskData; + } queryData; +} NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS; + +#define NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS { + NvU16 numQueries; + NvU8 reserved[6]; // To keep the struct aligned for now and available for future use (if needed) + NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS queries[NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES]; +} NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS; + +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_INVALID 0 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GPC_COUNT 1 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GPC_MAP 2 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_TPC_MASK 3 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PPC_MASK 4 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_GPC_MAP 5 /* deprecated */ +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_SYSPIPE_MASK 6 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_SYSPIPE_IDS 7 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PROFILER_MON_GPC_MASK 8 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_SYSPIPE_ID 9 +#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_ROP_MASK 10 + +/* _ctrl2080grmgr_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h new file mode 100644 index 0000000..ee04d61 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h @@ -0,0 +1,82 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080gsp.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX GSP control commands and parameters */ + +/* + * NV2080_CTRL_CMD_GSP_GET_FEATURES + * + * This command is used to determine which GSP features are + * supported on this GPU. + * + * gspFeatures + * Bit mask that specifies GSP features supported. + * bValid + * If this field is set to NV_TRUE, then above bit mask is + * considered valid. Otherwise, bit mask should be ignored + * as invalid. bValid will be set to NV_TRUE when RM is a + * GSP client with GPU support offloaded to GSP firmware. + * bDefaultGspRmGpu + * If this field is set to NV_TRUE, it indicates that the + * underlying GPU has GSP-RM enabled by default. If set to NV_FALSE, + * it indicates that the GPU has GSP-RM disabled by default. + * firmwareVersion + * This field contains the buffer into which the firmware build version + * should be returned, if GPU is offloaded. Otherwise, the buffer + * will remain untouched. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_GSP_GET_FEATURES (0x20803601) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_GSP_GET_FEATURES_PARAMS_MESSAGE_ID" */ + +#define NV2080_GSP_MAX_BUILD_VERSION_LENGTH (0x0000040) + +#define NV2080_CTRL_GSP_GET_FEATURES_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_GSP_GET_FEATURES_PARAMS { + NvU32 gspFeatures; + NvBool bValid; + NvBool bDefaultGspRmGpu; + NvU8 firmwareVersion[NV2080_GSP_MAX_BUILD_VERSION_LENGTH]; +} NV2080_CTRL_GSP_GET_FEATURES_PARAMS; + +/* Valid feature values */ +#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED 0:0 +#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE (0x00000000) +#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE (0x00000001) + +// _ctrl2080gsp_h_ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h new file mode 100644 index 0000000..f0df6c5 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080hshub.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* + * NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK + * + * This command get active HSHUB masks. + * + * hshubNcisocMask + * NCISOC enabled active HSHUBs + * hshubNvlMask + * NVLINK capable active HSHUBs. + */ + +#define NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS { + NvU32 hshubNcisocMask; + NvU32 hshubNvlMask; +} NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS; + +#define NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK (0x20804101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_HSHUB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID" */ + +/* _ctrl2080hshub_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h new file mode 100644 index 0000000..b3314d9 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h @@ -0,0 +1,365 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080i2c.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX i2c-related control commands and parameters */ + +/* + * NV2080_CTRL_I2C_VERSION + * + * NV2080_CTRL_I2C_VERSION_0_0: + * This return state specifies that support is only available + * for single subAddr reads. + * + */ +#define NV2080_CTRL_I2C_VERSION_0 0x00 + +/* maximum number of i2c entries support */ +#define NV2080_CTRL_I2C_MAX_ENTRIES 256 +#define NV2080_CTRL_I2C_MAX_REG_LEN 8 +#define NV2080_CTRL_I2C_MAX_ADDR_ENTRIES 20 + +/* + * NV2080_CTRL_I2C_FLAGS + * + * NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC: + * This option specified that non-compliant i2c for SI1930UC is required + * + * NV2080_CTRL_I2C_FLAGS_PRIVILEGE + * This option specified that the i2c access is privileged + * + * NV2080_CTRL_I2C_FLAGS_PX3540 + * This option specified that the i2c device -PX3540/3544- is accessed + */ +#define NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC (0x00000001) +#define NV2080_CTRL_I2C_FLAGS_PRIVILEGE (0x00000002) +#define NV2080_CTRL_I2C_FLAGS_DATA_ENCRYPTED (0x00000004) +#define NV2080_CTRL_I2C_FLAGS_PX3540 (0x00000010) +#define NV2080_CTRL_I2C_FLAGS_ADDR_AUTO_INC_NOT_SUPPORTED (0x00000008) + +/* + * NV2080_CTRL_CMD_I2C_READ_BUFFER + * + * This command allocates video memory for a particular subset of microcode. + * + * version + * This field is returned to the client and indicates the current + * supported I2C controls available. + * + * port + * This field must be specified by the client to indicate which port/bus + * in which i2c access is desired. + * + * flags + * This field is specified by the client to request additional options + * as provided by NV2080_CTRL_I2C_FLAGS. + * + * inputCount + * This field specifies the total # of elements contained in inputBuffer + * + * inputBuffer + * This should contain the chipaddr as the first element, followed by + * the each subAddress in which to access the first element of data + * Eg. ... + * In general, client will only have 2 elements + * + * outputCount + * This field specifies how many registers from the start register index. + * The maximum values allow are NV2080_CTRL_I2C_MAX_ENTRIES. + * + * outputBuffer + * This buffer is returned to the client with the data read from + * the start register index. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_STATE_IN_USE + * NV_ERR_INVALID_STATE + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV2080_CTRL_I2C_READ_BUFFER_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_I2C_READ_BUFFER_PARAMS { + NvU32 version; + NvU32 port; + NvU32 flags; + NvU32 inputCount; + // C form: NvU8 inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES]; + NvU8 inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES]; + NvU32 outputCount; + // C form: NvU8 outputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES]; + NvU8 outputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES]; +} NV2080_CTRL_I2C_READ_BUFFER_PARAMS; + +#define NV2080_CTRL_CMD_I2C_READ_BUFFER (0x20800601) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_READ_BUFFER_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_I2C_WRITE_BUFFER + * + * This command allocates video memory for a particular subset of microcode. + * + * version + * This field is returned to the client and indicates the current + * supported I2C controls available. + * + * port + * This field must be specified by the client to indicate which port/bus + * in which i2c access is desired. + * + * flags + * This field is specified by the client to request additional options. + * NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC: + * - Specifies that non-compliant i2c access for SI1930UC is required + * + * inputCount + * This field specifies the total # of elements contained in inputBuffer + * + * inputBuffer + * This should contain the chipaddr as the first element, followed by + * the each subAddress in which to access the first element of data, + * and finally the data to be programmed. + * Eg. ... ... + * In general, client will have 2 elements + data to be programmed. + * ... + * + * encrClientID + * This field is specified by client, which is used to uniquely access + * the client's encryption context + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_STATE_IN_USE + * NV_ERR_INVALID_STATE + * + */ + +#define NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS { + NvU32 version; + NvU32 port; + NvU32 flags; + NvU32 inputCount; + // C form: NvU8 inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES]; + NvU8 inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES]; + NvU32 encrClientID; +} NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS; + +#define NV2080_CTRL_CMD_I2C_WRITE_BUFFER (0x20800602) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS_MESSAGE_ID" */ + + +/* + * NV2080_CTRL_CMD_I2C_READ_REG + * + * This command allocates video memory for a particular subset of microcode. + * + * version + * This field is returned to the client and indicates the current + * supported I2C controls available. + * + * port + * This field must be specified by the client to indicate which port/bus + * in which i2c access is desired. + * + * flags + * This field is specified by the client to request additional options. + * NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC: + * - Specifies that non-compliant i2c access for SI1930UC is required + * addr + * This field is specified by the client to target address. + * reg + * This field is specified by the client to target register address. + * + * bufsize + * This field specifies the total bytes # of register size + * + * buffer + * when used for read, it used as buffer that store returned register content + * when used for write, It include data that will be written. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_STATE_IN_USE + * NV_ERR_INVALID_STATE + * + */ +typedef struct NV2080_CTRL_I2C_RW_REG_PARAMS { + NvU32 version; + NvU32 port; + NvU32 flags; + NvU32 addr; + NvU8 reg; + NvU8 bufsize; + // C form: NvU8 buffer[NV2080_CTRL_I2C_MAX_ENTRIES - 1]; + NvU8 buffer[(NV2080_CTRL_I2C_MAX_ENTRIES - 1)]; +} NV2080_CTRL_I2C_RW_REG_PARAMS; + +// provide NV2080_CTRL_I2C_READ_REG_PARAMS as the historical name +typedef NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_READ_REG_PARAMS; +#define NV2080_CTRL_CMD_I2C_READ_REG (0x20800603) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | 0x3" */ + +#define NV2080_CTRL_CMD_I2C_WRITE_REG (0x20800604) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | 0x4" */ + +/* + * NV006F_CTRL_CMD_SYSTEM_I2C_ACCESS + * + * This command allows Clients to read and write data using the I2C ports + * + * token [IN] + * This used in i2cAcquirePort + * + * cmd [IN] + * The I2CAccess command + * + * port [IN] + * The port ID of the concerned display + * + * flags [IN] + * The I2CAccess Flags such ack,start,stop + * + * data [OUT/IN] + * Data that needs to be pass or read out + * + * dataBuffSize [IN] + * Size of the data buffer. + * + * speed [IN] + * Speed of transaction. + * + * status [OUT] + * The I2CAccess Status returned + * + * encrClientID [IN] + * This field is specified by client, which is used to uniquely access + * the client's encryption context + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_I2C_ACCESS (0x20800610) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV2080_CTRL_I2C_ACCESS_PARAMS { + NvU32 token; + NvU32 cmd; + NvU32 port; + NvU32 flags; + NV_DECLARE_ALIGNED(NvP64 data, 8); + NvU32 status; + NvU32 dataBuffSize; + NvU32 speed; + NvU32 encrClientID; +} NV2080_CTRL_I2C_ACCESS_PARAMS; + +// commands +#define NV2080_CTRL_I2C_ACCESS_CMD_ACQUIRE 0x1 +#define NV2080_CTRL_I2C_ACCESS_CMD_RELEASE 0x2 +#define NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BYTE 0x3 +#define NV2080_CTRL_I2C_ACCESS_CMD_READ_BYTE 0x4 +#define NV2080_CTRL_I2C_ACCESS_CMD_NULL 0x5 +#define NV2080_CTRL_I2C_ACCESS_CMD_RESET 0x6 +#define NV2080_CTRL_I2C_ACCESS_CMD_TEST_PORT 0x11 +#define NV2080_CTRL_I2C_ACCESS_CMD_SET_FAST_MODE 0x12 +#define NV2080_CTRL_I2C_ACCESS_CMD_SET_NORMAL_MODE 0x13 +#define NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BUFFER 0x14 +#define NV2080_CTRL_I2C_ACCESS_CMD_READ_BUFFER 0x15 +#define NV2080_CTRL_I2C_ACCESS_CMD_START 0x17 +#define NV2080_CTRL_I2C_ACCESS_CMD_STOP 0x18 +#define NV2080_CTRL_I2C_ACCESS_CMD_SET_SLOW_MODE 0x20 + +// flags +#define NV2080_CTRL_I2C_ACCESS_FLAG_START 0x1 +#define NV2080_CTRL_I2C_ACCESS_FLAG_STOP 0x2 +#define NV2080_CTRL_I2C_ACCESS_FLAG_ACK 0x4 +#define NV2080_CTRL_I2C_ACCESS_FLAG_RAB 0x8 +#define NV2080_CTRL_I2C_ACCESS_FLAG_ADDR_10BITS 0x10 +#define NV2080_CTRL_I2C_ACCESS_FLAG_PRIVILEGE 0x20 +#define NV2080_CTRL_I2C_ACCESS_FLAG_DATA_ENCRYPTED 0x40 +#define NV2080_CTRL_I2C_ACCESS_FLAG_RESTART 0x80 +#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33_33PCT 0x100 +#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33PCT 0x200 +#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_10PCT 0x400 +#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3_33PCT 0x800 +#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3PCT 0x1000 + +// port +#define NV2080_CTRL_I2C_ACCESS_PORT_DYNAMIC 0x0 +#define NV2080_CTRL_I2C_ACCESS_PORT_PRIMARY 0x1 +#define NV2080_CTRL_I2C_ACCESS_PORT_SECONDARY 0x2 +#define NV2080_CTRL_I2C_ACCESS_PORT_TERTIARY 0x3 +#define NV2080_CTRL_I2C_ACCESS_PORT_QUARTIARY 0x4 + +// Alternate numeric port designators +#define NV2080_CTRL_I2C_ACCESS_PORT_1 0x1 +#define NV2080_CTRL_I2C_ACCESS_PORT_2 0x2 +#define NV2080_CTRL_I2C_ACCESS_PORT_3 0x3 +#define NV2080_CTRL_I2C_ACCESS_PORT_4 0x4 +#define NV2080_CTRL_I2C_ACCESS_PORT_5 0x5 +#define NV2080_CTRL_I2C_ACCESS_PORT_6 0x6 +#define NV2080_CTRL_I2C_ACCESS_PORT_7 0x7 +#define NV2080_CTRL_I2C_ACCESS_PORT_8 0x8 +#define NV2080_CTRL_I2C_ACCESS_PORT_9 0x9 +#define NV2080_CTRL_I2C_ACCESS_PORT_10 0x10 + +// Total ports count +#define NV2080_CTRL_I2C_ACCESS_NUM_PORTS NV2080_CTRL_I2C_ACCESS_PORT_10 + +// status +#define NV2080_CTRL_I2C_ACCESS_STATUS_SUCCESS 0x0 +#define NV2080_CTRL_I2C_ACCESS_STATUS_ERROR 0x1 +#define NV2080_CTRL_I2C_ACCESS_STATUS_PROTOCOL_ERROR 0x2 +#define NV2080_CTRL_I2C_ACCESS_STATUS_DEVICE_BUSY 0x3 +#define NV2080_CTRL_I2C_ACCESS_STATUS_NACK_AFTER_SEND 0x4 +#define NV2080_CTRL_I2C_ACCESS_STATUS_DP2TMDS_DONGLE_MISSING 0x5 + +#define NV2080_CTRL_CMD_I2C_ENABLE_MONITOR_3D_MODE (0x20800620) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS { + NvU32 head; + NvU32 authType; + NvU32 status; +} NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS; + +/* _ctrl2080i2c_h_ */ + + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h new file mode 100644 index 0000000..54a762a --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080illum.finn +// + + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h new file mode 100644 index 0000000..5307f5d --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h @@ -0,0 +1,3176 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080internal.finn +// + +#include "nvimpshared.h" +#include "ctrl/ctrl2080/ctrl2080base.h" + +#include "ctrl/ctrl2080/ctrl2080gpu.h" +#include "ctrl/ctrl2080/ctrl2080gr.h" /* Some controls derivative of 2080gr */ +#include "ctrl/ctrl0080/ctrl0080msenc.h" /* NV0080_CTRL_MSENC_CAPS_TBL_SIZE */ +#include "ctrl/ctrl0080/ctrl0080bsp.h" /* NV0080_CTRL_BSP_CAPS_TBL_SIZE */ +#include "ctrl/ctrl2080/ctrl2080fifo.h" /* NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO */ +#include "ctrl/ctrl0000/ctrl0000system.h" +#include "ctrl/ctrl90f1.h" +#include "ctrl/ctrl30f1.h" + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO + * + * This command obtains information from physical RM for use by CPU-RM. + * + * feHwSysCap + * Display IP v03_00 and later. + * Contents of capability register. + * + * windowPresentMask + * Display IP v03_00 and later. + * Mask for the present WINDOWs actually on the current chip. + * bFbRemapperEnabled + * Display IP v02_01 and later. + * Indicates that the display remapper HW exists and is enabled. + * numHeads + * Display IP v02_01 and later. + * Provides the number of heads HW support. + */ + +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO (0x20800a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS { + NvU32 feHwSysCap; + NvU32 windowPresentMask; + NvBool bFbRemapperEnabled; + NvU32 numHeads; + NvBool bPrimaryVga; + NvU32 i2cPort; + NvU32 internalDispActiveMask; +} NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS; + + + +// +// MemorySystem settings that are static after GPU state init/load is finished. +// +// Fields are shared between the VGPU guest/GSP Client as well as the VGPU +// host/GSP-RM. +// +#define NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID (0x1CU) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS { + /*! Determines if RM should use 1 to 1 Comptagline allocation policy */ + NvBool bOneToOneComptagLineAllocation; + + /*! Determines if RM should use 1 to 4 Comptagline allocation policy */ + NvBool bUseOneToFourComptagLineAllocation; + + /*! Determines if RM should use raw Comptagline allocation policy */ + NvBool bUseRawModeComptaglineAllocation; + + /*! Has COMPBIT_BACKING_SIZE been overridden to zero (i.e. disabled)? */ + NvBool bDisableCompbitBacking; + + /*! Determine if we need to disable post L2 compression */ + NvBool bDisablePostL2Compression; + + /*! Is ECC DRAM feature supported? */ + NvBool bEnabledEccFBPA; + + NvBool bL2PreFill; + + /*! L2 cache size */ + NV_DECLARE_ALIGNED(NvU64 l2CacheSize, 8); + + NvBool bReservedMemAtBottom; + + /*! Indicate whether fpba is present or not */ + NvBool bFbpaPresent; + + /*! Size covered by one comptag */ + NvU32 comprPageSize; + + /*! log32(comprPageSize) */ + NvU32 comprPageShift; + + /*! Maximum number of pages that can be dynamaically blacklisted */ + NvU16 maximumBlacklistPages; + + /*! RAM type */ + NvU32 ramType; + + /*! LTC count */ + NvU32 ltcCount; + + /*! LTS per LTC count */ + NvU32 ltsPerLtcCount; + + /*! Ampere PLC bug */ + NvBool bDisablePlcForCertainOffsetsBug3046774; +} NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS; + +/*! + * Retrieve Memory System Static data. + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_STATIC_CONFIG (0x20800a1c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_REGISTER_UVM_ACCESS_CNTR_BUFFER + * + * This command sends access counter buffer pages allocated by CPU-RM + * to be setup and enabled in physical RM. + * + * bufferSize + * Size of the access counter buffer to register. + * + * bufferPteArray + * Pages of access counter buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER (0x20800a1d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES 64 +#define NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID (0x1DU) + +typedef struct NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS { + NvU32 bufferSize; + NV_DECLARE_ALIGNED(NvU64 bufferPteArray[NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES], 8); +} NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER + * + * This command requests physical RM to disable the access counter buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER (0x20800a1e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x1E" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_UVM_SERVICE_ACCESS_CNTR_BUFFER + * + * This command requests physical RM to service the access counter buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_UVM_SERVICE_ACCESS_CNTR_BUFFER (0x20800a21) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x21" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE + * + * This command retrieves the access counter buffer size from physical RM. + * + * bufferSize[OUT] + * Size of the access counter buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE (0x20800a29) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x29U) + +typedef struct NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS { + NvU32 bufferSize; +} NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS; + +#define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES 8 + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_CAPS_V2 + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS (0x20800a1f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x1F" */ + + + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CAPS { + NvU8 capsTbl[NV0080_CTRL_GR_CAPS_TBL_SIZE]; +} NV2080_CTRL_INTERNAL_STATIC_GR_CAPS; +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_CAPS engineCaps[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER + * @ref NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER (0x20800a22) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x22" */ + + + +#define NV2080_CTRL_INTERNAL_GR_MAX_SM 240 + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER { + struct { + NvU16 gpcId; + NvU16 localTpcId; + NvU16 localSmId; + NvU16 globalTpcId; + NvU16 virtualGpcId; + NvU16 migratableTpcId; + } globalSmId[NV2080_CTRL_INTERNAL_GR_MAX_SM]; + + NvU16 numSm; + NvU16 numTpc; +} NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER globalSmOrder[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS; + + +/*! + * Retrieve BSP Static data. + */ +#define NV2080_CTRL_CMD_INTERNAL_BSP_GET_CAPS (0x20800a24) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_MAX_BSPS 8 + +typedef struct NV2080_CTRL_INTERNAL_BSP_CAPS { + NvU8 capsTbl[NV0080_CTRL_BSP_CAPS_TBL_SIZE]; +} NV2080_CTRL_INTERNAL_BSP_CAPS; + +#define NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS_MESSAGE_ID (0x24U) + +typedef struct NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS { + NV2080_CTRL_INTERNAL_BSP_CAPS caps[NV2080_CTRL_CMD_INTERNAL_MAX_BSPS]; + NvBool valid[NV2080_CTRL_CMD_INTERNAL_MAX_BSPS]; +} NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS; + +/*! + * Retrieve MSENC Static data. + */ +#define NV2080_CTRL_CMD_INTERNAL_MSENC_GET_CAPS (0x20800a25) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS 3 + +typedef struct NV2080_CTRL_INTERNAL_MSENC_CAPS { + NvU8 capsTbl[NV0080_CTRL_MSENC_CAPS_TBL_SIZE]; +} NV2080_CTRL_INTERNAL_MSENC_CAPS; + +#define NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID (0x25U) + +typedef struct NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS { + NV2080_CTRL_INTERNAL_MSENC_CAPS caps[NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS]; + NvBool valid[NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS]; +} NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS; + + +#define NV2080_CTRL_INTERNAL_GR_MAX_GPC 12 +#define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT 10 + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_GPC_MASK + * @ref NV2080_CTRL_CMD_GR_GET_TPC_MASK + * @ref NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS (0x20800a26) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x26" */ + + + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS { + NvU32 gpcMask; + + /*! + * tpcMask is indexed by logical GPC ID for MIG case + * and indexed by physical GPC ID for non-MIG case + */ + NvU32 tpcMask[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; + + /*! + * tpcCount is always indexed by logical GPC ID + */ + NvU32 tpcCount[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; + NvU32 physGpcMask; + NvU32 mmuPerGpc[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; + + NvU32 tpcToPesMap[NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT]; + NvU32 numPesPerGpc[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; + + /*! + * zcullMask is always indexed by physical GPC ID + */ + NvU32 zcullMask[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; + + NvU32 physGfxGpcMask; + NvU32 numGfxTpc; +} NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS { + /*! + * floorsweeping masks which are indexed via local GR index + */ + NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS floorsweepingMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS; + +/* + * NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES + * + * This command returns physical addresses of specified context buffer. + * To obtain addresses of whole buffer firstPage has to be advanced on + * subsequent invocations of the control until whole buffer is probed. + * If the buffer is contiguous, only single address will be returned by + * this control. + * + * bufferType[IN] + * Buffer type as returned by GET_CTX_BUFFER_INFO. + * + * firstPage[IN] + * Index of the first page to return in 'physAddrs' array. + * + * numPages[OUT] + * Number of entries filled in 'physAddrs' array. This will be 0 + * if firstPage is greater or equal to number of pages managed by 'hBuffer'. + * + * physAddrs[OUT] + * Physical addresses of pages comprising specified buffer. + * + * bNoMorePages[OUT] + * End of buffer reached. Either 'physAddrs' contains last page of the + * buffer or 'firstPage' specifies index past the buffer. + */ +#define NV2080_CTRL_KGR_MAX_BUFFER_PTES 128 +#define NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES (0x20800a28) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID (0x28U) + +typedef struct NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS { + NvHandle hUserClient; + NvHandle hChannel; + NvU32 bufferType; + NvU32 firstPage; + NvU32 numPages; + NV_DECLARE_ALIGNED(NvU64 physAddrs[NV2080_CTRL_KGR_MAX_BUFFER_PTES], 8); + NvBool bNoMorePages; +} NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS; + +/*! + * @ref NV0080_CTRL_CMD_GR_GET_INFO + * @ref NV0080_CTRL_CMD_GR_GET_INFO_V2 + * @ref NV2080_CTRL_CMD_GR_GET_INFO + * @ref NV2080_CTRL_CMD_GR_GET_INFO_V2 + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO (0x20800a2a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x2A" */ + + + +/*! + * @ref NV2080_CTRL_GR_INFO + */ +typedef struct NV2080_CTRL_INTERNAL_GR_INFO { + NvU32 index; + NvU32 data; +} NV2080_CTRL_INTERNAL_GR_INFO; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_INFO { + NV2080_CTRL_INTERNAL_GR_INFO infoList[NV0080_CTRL_GR_INFO_MAX_SIZE]; +} NV2080_CTRL_INTERNAL_STATIC_GR_INFO; +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_INFO engineInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_ZCULL_INFO + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO (0x20800a2c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x2C" */ + + + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO { + NvU32 widthAlignPixels; + NvU32 heightAlignPixels; + NvU32 pixelSquaresByAliquots; + NvU32 aliquotTotal; + NvU32 zcullRegionByteMultiplier; + NvU32 zcullRegionHeaderSize; + NvU32 zcullSubregionHeaderSize; + NvU32 subregionCount; + NvU32 subregionWidthAlignPixels; + NvU32 subregionHeightAlignPixels; +} NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO engineZcullInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_ROP_INFO + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO (0x20800a2e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x2E" */ + + + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO { + NvU32 ropUnitCount; + NvU32 ropOperationsFactor; + NvU32 ropOperationsCount; +} NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO engineRopInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_PPC_MASK + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS (0x20800a30) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x30" */ + + + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS { + NvU32 mask[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; +} NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS enginePpcMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES + * @ref NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO (0x20800a32) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x32" */ + + + +#define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT 0x19 + +typedef struct NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO { + NvU32 size; + NvU32 alignment; +} NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO { + NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO engine[NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT]; +} NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO engineContextBuffersInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER (0x20800a34) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x34" */ + + + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER { + NvU8 imla0; + NvU8 fmla16; + NvU8 dp; + NvU8 fmla32; + NvU8 ffma; + NvU8 imla1; + NvU8 imla2; + NvU8 imla3; + NvU8 imla4; +} NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER smIssueRateModifier[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS; + +/* + * NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS + * + * This command obtains information from physical RM for use by CPU-RM. + */ + +#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_CHIP_INFO (0x20800a36) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID" */ + +/* + * Maximum number of register bases to return. + * These are indexed by NV_REG_BASE_* constants from gpu.h, and this value needs + * to be updated if NV_REG_BASE_LAST ever goes over it. See the ct_assert() in gpu.h + */ +#define NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX 16 +#define NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID (0x36U) + +typedef struct NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS { + NvU8 chipSubRev; + NvU32 emulationRev1; + NvBool isCmpSku; + NvU32 bar1Size; + NvU32 pciDeviceId; + NvU32 pciSubDeviceId; + NvU32 pciRevisionId; + NvU32 regBases[NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX]; +} NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS; + +/** + * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE + * + * Set whether or not context switch logging is enabled + * + * bEnable + * Enable/Disable status for context switch logging + */ +#define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE (0x20800a37) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID" */ + +/** + * NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE + * + * Retrieve whether or not context switch logging is enabled + * + * bEnable + * Enable/Disable status for context switch logging + */ +#define NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE (0x20800a38) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID" */ + +typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvBool bEnable; +} NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS; +#define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x37U) + +typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS; +#define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x38U) + +typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS; + +/** + * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET + * + * Set read offset into FECS context switch trace record + * + * offset + * Value indicating number of records by which to offset + */ +#define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET (0x20800a39) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID" */ + +/** + * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET + * + * Set write offset into FECS context switch trace record + * + * offset + * Value indicating number of records by which to offset + */ +#define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET (0x20800a3a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID" */ + +/** + * NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET + * + * Get read offset into FECS context switch trace record + * + * offset + * Value indicating number of records by which to offset + */ + +#define NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET (0x20800a3b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID" */ + +typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); + NvU32 offset; +} NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS; + +#define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x39U) + +typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS; +#define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID (0x3AU) + +typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS; +#define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x3BU) + +typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS; + +/** + * NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE + * + * Get size of FECS record + * + * fecsRecordSize + * Size of FECS record + */ + + + +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE (0x20800a3d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID" */ + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE { + NvU32 fecsRecordSize; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE; + +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID (0x3CU) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE fecsRecordSize[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID (0x3DU) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS; + +/** + * NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES + * + * Get HW defines used to extract information from FECS records + * + * fecsRecordSize + * Size of FECS record + * + * timestampHiTagMask + * Mask for high bits of raw timestamp to extract tag + * + * timestampHiTagShift + * Shift for high bits of raw timestamp to extract tag + * + * timestampVMask + * Mask to extract timestamp from raw timestamp + * + * numLowerBitsZeroShift + * Number of bits timestamp is shifted by + */ + + + +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES (0x20800a3f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x3F" */ + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES { + NvU32 fecsRecordSize; + NvU32 timestampHiTagMask; + NvU8 timestampHiTagShift; + NV_DECLARE_ALIGNED(NvU64 timestampVMask, 8); + NvU8 numLowerBitsZeroShift; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES fecsTraceDefines[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES], 8); +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS; + +/** + * NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE + * + * Parse the DEVICE_INFO2_TABLE on the physical side and return it to kernel. + */ +typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO { + NvU32 faultId; + NvU32 instanceId; + NvU32 typeEnum; + NvU32 resetId; + NvU32 devicePriBase; + NvU32 isEngine; + NvU32 rlEngId; + NvU32 runlistPriBase; + NvU32 groupId; +} NV2080_CTRL_INTERNAL_DEVICE_INFO; +#define NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES 88 + +#define NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE (0x20800a40) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID (0x40U) + +typedef struct NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS { + NvU32 numEntries; + NV2080_CTRL_INTERNAL_DEVICE_INFO deviceInfoTable[NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES]; +} NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP (0x20800a41) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE 4096 +#define NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES 4096 + +#define NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID (0x41U) + +typedef struct NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS { + NvU32 userRegisterAccessMapSize; + NvU32 compressedSize; + NvU8 compressedData[NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE]; + NvU32 profilingRangesSize; + NvU8 profilingRanges[NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES]; +} NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS; + +typedef struct NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO { + NvU32 engDesc; + NvU32 ctxAttr; + NvU32 ctxBufferSize; + NvU32 addrSpaceList; + NvU32 registerBase; +} NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO; +#define NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS 0x40 + +#define NV2080_CTRL_CMD_INTERNAL_GET_CONSTRUCTED_FALCON_INFO (0x20800a42) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID (0x42U) + +typedef struct NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS { + NvU32 numConstructedFalcons; + NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS]; +} NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS; + +/** + * Get GR PDB properties synchronized between Kernel and Physical + * + * bPerSubCtxheaderSupported + * @ref PDB_PROP_GR_SUPPORTS_PER_SUBCONTEXT_CONTEXT_HEADER + */ + + + +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES (0x20800a48) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x48" */ + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES { + NvBool bPerSubCtxheaderSupported; +} NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS { + NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES pdbTable[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM + * + * This command writes instance memory information in the display hardware registers. + * + * instMemPhysAddr + * GPU physical address or IOVA address of the display instance memory. + * + * instMemSize + * Size of the display instance memory. + * + * instMemAddrSpace + * Address space of the display instance memory. + * + * instMemCpuCacheAttr + * Cache attribute of the display instance memory. + */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM (0x20800a49) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID (0x49U) + +typedef struct NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS { + NV_DECLARE_ALIGNED(NvU64 instMemPhysAddr, 8); + NV_DECLARE_ALIGNED(NvU64 instMemSize, 8); + NvU32 instMemAddrSpace; + NvU32 instMemCpuCacheAttr; +} NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS; + +/* + * NV2080_CTRL_INTERNAL_GPU_RECOVER_ALL_COMPUTE_CONTEXTS + * + * This command issues RC recovery for all compute contexts running on the given GPU. + */ +#define NV2080_CTRL_CMD_INTERNAL_RECOVER_ALL_COMPUTE_CONTEXTS (0x20800a4a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x4A" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION + * + * This command obtains IP version of display engine for use by Kernel RM. + * + * ipVersion + * IP Version of display engine. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED - DISP has been disabled + */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION (0x20800a4b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID (0x4BU) + +typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS { + NvU32 ipVersion; +} NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE + * + * This command determines the current status of MIG MODE from Physical RM. + * + * smcMode [OUT] + * Current MIG MODE of the GPU. Values range NV2080_CTRL_GPU_INFO_GPU_SMC_MODE* + */ +#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE (0x20800a4c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID (0x4CU) + +typedef struct NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS { + NvU32 smcMode; +} NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR + * + * head + * This parameter specifies the head for which the callback is to be registered/unregistered. This value must be + * less than the maximum number of heads supported by the GPU subdevice. + * + * rgLineNum + * This indicates the RG scanout line number on which the callback will be executed. + * + * intrLine + * Enable: [out] Which interrupt line was allocated for this head. + * Disable: [in] Which interrupt line to deallocate. + * + * bEnable + * Should we allocate or deallocate an interrupt line? + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC - There was no available interrupt to allocate. + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR (0x20800a4d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID (0x4DU) + +typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS { + NvU32 head; + NvU32 rgLineNum; + NvU32 intrLine; + NvBool bEnable; +} NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS; + +/*! + * NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO + * + * Description of a supported GPU instance. + * + * partitionFlag [OUT] + * Allocation flag to be used to allocate a partition with this profile. + * + * grCount [OUT] + * # GR engines, including the GFX capable ones. + * + * gfxGrCount [OUT] + * # GR engines capable of Gfx, which is a subset of the GR engines included in grCount + * + * gpcCount [OUT] + * # total gpcs, including the GFX capable ones. + * + * virtualGpcCount [OUT] + * # virtualized gpcs, including the GFX capable ones. + * + * gfxGpcCount [OUT] + * # total gpcs capable of Gfx. This is a subset of the GPCs included in gpcCount. + * + * veidCount [OUT] + * # total veids + * + * smCount [OUT] + * # total SMs + * + * ceCount [OUT] + * # CE engines + * + * nvEncCount [OUT] + * # NVENC engines + * + * nvDecCount [OUT] + * # NVDEC engines + * + * nvJpgCount [OUT] + * # NVJPG engines + * + * nvOfaCount [OUT] + * # NVOFA engines + * + * validCTSIdMask [OUT] + * # mask of CTS IDs which can be assigned under this profile + */ +#define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 20 + + + +typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO { + NvU32 partitionFlag; + NvU32 grCount; + NvU32 gfxGrCount; + NvU32 gpcCount; + NvU32 virtualGpcCount; + NvU32 gfxGpcCount; + NvU32 veidCount; + NvU32 smCount; + NvU32 ceCount; + NvU32 nvEncCount; + NvU32 nvDecCount; + NvU32 nvJpgCount; + NvU32 nvOfaCount; + NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8); +} NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO; + +/*! + * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS + * + * Returns the list of supported GPU instance profiles. + * + * count [OUT] + * Number of supported profiles. + * + * table [OUT] + * Supported profiles. + */ +typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS { + NvU32 count; + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO table[NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES], 8); +} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM + * + * This command instructs the physical MemorySystem to set up memory partitioning + * exterior boundaries in hardware. + * + * partitionableMemSize [input] + * Size of the partitionable memory in bytes + * + * bottomRsvdSize [input] + * Size of the reserved region below partitionable memory in bytes + * + * topRsvdSize [input] + * Size of the reserved region above partitionable memory in bytes + * + * partitionableStartAddr [output] + * Start address of the partitionable memory, aligned to HW constraints + * + * partitionableEndAddr [output] + * End address of the partitionable memory, aligned to HW constraints + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM (0x20800a51) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID (0x51U) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS { + NV_DECLARE_ALIGNED(NvU64 partitionableMemSize, 8); + NV_DECLARE_ALIGNED(NvU64 bottomRsvdSize, 8); + NV_DECLARE_ALIGNED(NvU64 topRsvdSize, 8); + NV_DECLARE_ALIGNED(NvU64 partitionableStartAddr, 8); + NV_DECLARE_ALIGNED(NvU64 partitionableEndAddr, 8); +} NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS; + + + +typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS { + NV_DECLARE_ALIGNED(NvU64 engineMask, 8); +} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS; + + +/*! + * NV2080_CTRL_INTERNAL_MEMDESC_INFO + * + * A generic container structure representing a memory region to be used as a + * component of other control call parameters. + * + */ +typedef struct NV2080_CTRL_INTERNAL_MEMDESC_INFO { + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NV_DECLARE_ALIGNED(NvU64 alignment, 8); + NvU32 addressSpace; + NvU32 cpuCacheAttrib; +} NV2080_CTRL_INTERNAL_MEMDESC_INFO; + +#define NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS 2 +#define NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID 64 +/*! + * NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS + * + * Promote a single partition's runlist buffers allocated by kernel Client RM to Physical RM + * + * rlBuffers [IN] + * 2D array of runlist buffers for a single partition + * + * runlistIdMask [IN] + * Mask of runlists belonging to partition + * + */ +#define NV2080_CTRL_CMD_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS (0x20800a53) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID (0x53U) + +typedef struct NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MEMDESC_INFO rlBuffers[NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID][NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS], 8); + NV_DECLARE_ALIGNED(NvU64 runlistIdMask, 8); + NvU32 swizzId; +} NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_SET_IMP_INIT_INFO (0x20800a54) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID (0x54U) + +typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS { + TEGRA_IMP_IMPORT_DATA tegraImpImportData; +} NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR + * + * This command triggers a sysmembar to flush VIDMEM writes. + * This command accepts no parameters. + * + */ +#define NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR (0x20800a70) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x70" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL + * + * Setup local PCIE P2P Mailbox + * + * local2Remote[IN] + * Local peer ID of remote gpu on local gpu + * + * remote2Local[IN] + * Remote peer ID of local gpu on remote gpu + * + * localP2PDomainRemoteAddr[IN] + * P2P domain remote address on local gpu + * + * remoteP2PDomainLocalAddr[IN] + * P2P domain local address on remote gpu + * + * remoteWMBoxLocalAddr[IN] + * Local mailbox address on remote gpu + * + * p2pWmbTag[OUT] + * Tag for mailbox to transport from local to remote GPU + * + * bNeedWarBug999673[IN] + * Set to true if WAR for bug 999673 is required + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL (0x20800a71) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID (0x71U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS { + NvU32 local2Remote; + NvU32 remote2Local; + NV_DECLARE_ALIGNED(NvU64 localP2PDomainRemoteAddr, 8); + NV_DECLARE_ALIGNED(NvU64 remoteP2PDomainLocalAddr, 8); + NV_DECLARE_ALIGNED(NvU64 remoteWMBoxLocalAddr, 8); + NV_DECLARE_ALIGNED(NvU64 p2pWmbTag, 8); + NvBool bNeedWarBug999673; +} NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS; + + /* + * NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE + * + * Setup remote PCIE P2P Mailbox + * + * local2Remote[IN] + * Local peer ID of remote gpu on local gpu + * + * remote2Local[IN] + * Remote peer ID of local gpu on remote gpu + * + * localP2PDomainRemoteAddr[IN] + * P2P domain remote address on local gpu + * + * remoteP2PDomainLocalAddr[IN] + * P2P domain local address on remote gpu + * + * remoteWMBoxAddrU64[IN] + * Mailbox address on remote gpu + * + * p2pWmbTag[IN] + * Tag for mailbox to transport from local to remote GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE (0x20800a72) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID (0x72U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS { + NvU32 local2Remote; + NvU32 remote2Local; + NV_DECLARE_ALIGNED(NvU64 localP2PDomainRemoteAddr, 8); + NV_DECLARE_ALIGNED(NvU64 remoteP2PDomainLocalAddr, 8); + NV_DECLARE_ALIGNED(NvU64 remoteWMBoxAddrU64, 8); + NV_DECLARE_ALIGNED(NvU64 p2pWmbTag, 8); +} NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX + * + * Destroy PCIE P2P Mailbox + * + * peerIdx[IN] + * Peer ID of the P2P destination GPU + * + * bNeedWarBug999673[IN] + * Set to true if WAR for bug 999673 is required + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX (0x20800a73) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID (0x73U) + +typedef struct NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS { + NvU32 peerIdx; + NvBool bNeedWarBug999673; +} NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING + * + * Create C2C mapping to a given peer GPU + * + * peerId[IN] + * Peer ID for local to remote GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING (0x20800a74) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID (0x74U) + +typedef struct NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS { + NvU32 peerId; +} NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING + * + * Remove C2C mapping to a given peer GPU + * + * peerId[IN] + * Peer ID for local to remote GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING (0x20800a75) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID (0x75U) + +typedef struct NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS { + NvU32 peerId; +} NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES + * + * Retrieves the corresponding SPAs (per the given GFID's VMMU mappings) + * for the given array of GPAs. + * + * gfid [IN] + * GFID to translate GPAs for + * + * numEntries [IN] + * Number of entries (<= NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES) + * to translate (i.e. number of elements in gpaEntries) + * + * gpaEntries [IN] + * Array of GPAs to translate + * + * spaEntries [OUT] + * Resulting array of SPAs + */ +#define NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES (0x20800a57) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES 128 + +#define NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID (0x57U) + +typedef struct NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS { + NvU32 gfid; + NvU32 numEntries; + NV_DECLARE_ALIGNED(NvU64 gpaEntries[NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES], 8); + NV_DECLARE_ALIGNED(NvU64 spaEntries[NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES], 8); +} NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER + * + * Pass required pushbuffer parameters from kernel RM to Physical RM + * + * addressSpace [IN] + * Address space of pushbuffer whtether it is ADDR_SYSMEM or ADDR_FBMEM + * + * physicalAddr [IN] + * Physical address of pushbuffer + * + * addressSpace [IN] + * Limit of the pushbuffer address, it should be less than 4K + * + * cacheSnoop [IN] + * Cachesnoop supported or not + * + * channelInstance [IN] + * Channel instance pass by the client to get corresponding dispchannel + * + * hclass [IN] + * External class ID pass by the client to get the channel class + * + * valid [IN] + * This bit indicates whether pushbuffer parameters are valid or not + * + */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER (0x20800a58) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID (0x58U) + +typedef struct NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS { + NvU32 addressSpace; + NV_DECLARE_ALIGNED(NvU64 physicalAddr, 8); + NV_DECLARE_ALIGNED(NvU64 limit, 8); + NvU32 cacheSnoop; + NvU32 hclass; + NvU32 channelInstance; + NvBool valid; +} NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO + * + * This command obtains information from physical RM for use by CPU-RM. + * + * replayableFaultBufferSize + * Default size of replayable fault buffer + * + * nonReplayableFaultBufferSize + * Default size of non-replayable fault buffer + * + */ + +#define NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO (0x20800a59) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0x59U) + +typedef struct NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS { + NvU32 replayableFaultBufferSize; + NvU32 nonReplayableFaultBufferSize; +} NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GR_GET_CTXSW_MODES + */ +#define NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES (0x20800a5a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x5A" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE + * + * Get heap reservation size needed by different module + */ +#define NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE (0x20800a5b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID (0x5BU) + +typedef struct NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS { + NvU32 moduleIndex; + NvU32 size; +} NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE + * + * tableLen [OUT] + * Number of valid records in table field. + * + * table [OUT] + * Interrupt table for Kernel RM. + */ +#define NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE (0x20800a5c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE 128 + +typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY { + NvU16 engineIdx; + NvU32 pmcIntrMask; + NvU32 vectorStall; + NvU32 vectorNonStall; +} NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY; + +#define NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID (0x5CU) + +typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS { + NvU32 tableLen; + NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY table[NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE]; +} NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS; + +/* Index to retrieve the needed heap space for specific module */ +#define NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_GR (0x00000000) + +/* + * NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK + * + * Checking if the reservation / release of the PERFMON HW is possible + * + * bReservation [IN] + * NV_TRUE -> request for reservation, NV_FALSE -> request for release + * + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK (0x20800a98) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID" */ + + +#define NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID (0x98U) + +typedef struct NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS { + NvBool bReservation; +} NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET + * + * Reserving / Releasing PERFMON HW + * + * bReservation [IN] + * NV_TRUE -> request for reservation, NV_FALSE -> request for release + * + * bClientHandlesGrGating [IN] + * DM-TODO: Add comment for this + * + * bRmHandlesIdleSlow [IN] + * If the IDLE slowdown is required + * + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET (0x20800a99) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID (0x99U) + +typedef struct NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS { + NvBool bReservation; + NvBool bClientHandlesGrGating; + NvBool bRmHandlesIdleSlow; +} NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES + * + * Get active display devices + * + * displayMask [OUT] + * Get the mask of the active display devices in VBIOS + * + * numHeads [OUT] + * Number of heads display supported. + * + */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES (0x20800a5d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID (0x5DU) + +typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS { + + NvU32 displayMask; + NvU32 numHeads; +} NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS; + + + +/* + * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES + * + * Get FB Mem page ranges for all possible swizzIds + * + * fbMemPageRanges [OUT] + * Mem page ranges for each swizzId in the form of {lo, hi} + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a60) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID 15 + +typedef struct NV2080_CTRL_INTERNAL_NV_RANGE { + NV_DECLARE_ALIGNED(NvU64 lo, 8); + NV_DECLARE_ALIGNED(NvU64 hi, 8); +} NV2080_CTRL_INTERNAL_NV_RANGE; + +#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x60U) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NV_RANGE fbMemPageRanges[NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID], 8); +} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS + * + * This command is an internal command sent from Kernel RM to Physical RM + * to get number of channels for a given runlist ID + * + * runlistId [IN] + * numChannels [OUT] + */ +#define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS (0x20800a61) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID (0x61U) + +typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS { + NvU32 runlistId; + NvU32 numChannels; +} NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES + * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PROFILES + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES (0x20800a63) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x63" */ + +/*! + * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK + * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_VALID_SWIZZID_MASK + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK (0x20800a64) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x64" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES + * NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES (0x20800a65) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x65" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES + * NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a66) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x66" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG + * + * This command retrieves memory config from HW + * + * memBoundaryCfgA [OUT] + * Memory boundary config A (4KB aligned) + * + * memBoundaryCfgB [OUT] + * Memory boundary config B (4KB aligned) + * + * memBoundaryCfgC [OUT] + * Memory boundary config C (64KB aligned) + * + * memBoundaryCfg [OUT] + * Memory boundary config (64KB aligned) + * + * memBoundaryCfgValInit [OUT] + * Memory boundary config initial value (64KB aligned) + */ +#define NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a67) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x67" */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a68) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x68" */ + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS { + NV_DECLARE_ALIGNED(NvU64 memBoundaryCfgA, 8); + NV_DECLARE_ALIGNED(NvU64 memBoundaryCfgB, 8); + NvU32 memBoundaryCfgC; + NvU32 memBoundaryCfg; + NvU32 memBoundaryCfgValInit; +} NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE (0x20800a6b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE 8 + +#define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID (0x6BU) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS { + NvU32 data[NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE]; +} NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT + * + * Invoke RC recovery after watchdog timeout is hit. + */ +#define NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT (0x20800a6a) /* finn: Evaluated from "((FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6a)" */ + +/* ! + * This command disables cuda limit activation at teardown of the client. + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE (0x20800a7a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7A" */ + +/* + * This command is cleaning up OPTP when a client is found to have + * been terminated unexpectedly. + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_OPTP_CLI_CLEAR (0x20800a7c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7C" */ + +/* ! + * This command is used to get the current AUX power state of the sub-device. + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_GET_AUX_POWER_STATE (0x20800a81) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS { + NvU32 powerState; +} NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS; + +/*! + * This command can be used to boost P-State up one level or to the highest for a limited + * duration for the associated subdevice. Boosts from different clients are being tracked + * independently. Note that there are other factors that can limit P-States so the resulting + * P-State may differ from expectation. + * + * flags + * This parameter specifies the actual command. _CLEAR is to clear existing boost. + * _BOOST_1LEVEL is to boost P-State one level higher. _BOOST_TO_MAX is to boost + * to the highest P-State. + * duration + * This parameter specifies the duration of the boost in seconds. This has to be less + * than NV2080_CTRL_PERF_BOOST_DURATION_MAX. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_2X (0x20800a9a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID (0x9AU) + +typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X { + + NvBool flags; + NvU32 duration; +} NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X; + +#define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_PSTATE 0U +#define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK 1U +#define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK +#define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM (0x2U) /* finn: Evaluated from "NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST + 1" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL + * + * Activate/Deactivate GPU Boost Sync algorithm + * + * bActivate [IN] + * GPU Boost Sync algorithm: + * NV_TRUE -> activate + * NV_FALSE -> deactivate + * + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL (0x20800a7e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID (0x7EU) + +typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS { + NvBool bActivate; +} NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS + * + * Apply given limits to a specific subdevice + * + * flags [IN] + * DM-TODO: write description here + * + * bBridgeless [IN] + * Bridgeless information, for now supporting only MIO bridges + * + * currLimits + * Array of limits that will be applied + * + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS (0x20800a7f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID (0x7FU) + +typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS { + NvU32 flags; + NvBool bBridgeless; + NvU32 currLimits[NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM]; +} NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO + * + * Data for GPU Boost Sync structure initialization + * + * hysteresisus [OUT] + * Hysteresis value for GPU Boost synchronization hysteresis algorithm. + * + * bHystersisEnable [OUT] + * hysteresis algorithm for SLI GPU Boost synchronization: + * NV_TRUE -> enabled, + * NV_FALSE -> disabled + * + * bSliGpuBoostSyncEnable [OUT] + * SLI GPU Boost feature is: + * NV_TRUE -> enabled, + * NV_FALSE -> disabled + * + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO (0x20800a80) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID (0x80U) + +typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 hysteresisus, 8); + NvBool bHystersisEnable; + NvBool bSliGpuBoostSyncEnable; +} NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER + * + * This command sends replayable fault buffer pages allocated by CPU-RM + * to be setup and enabled in physical RM. + * + * hClient + * Client handle. + * + * hObject + * Object handle. + * + * faultBufferSize + * Size of the replayable fault buffer to register. + * + * faultBufferPteArray + * Pages of replayable fault buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER (0x20800a9b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES 256 +#define NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9BU) + +typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS { + NvHandle hClient; + NvHandle hObject; + NvU32 faultBufferSize; + NV_DECLARE_ALIGNED(NvU64 faultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES], 8); +} NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER + * + * This command requests physical RM to disable the replayable fault buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER (0x20800a9c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x9C" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER + * + * This command sends client shadow fault buffer pages allocated by CPU-RM + * to be setup and enabled in physical RM. + * + * shadowFaultBufferQueuePhysAddr + * Physical address of shadow fault buffer queue. + * + * faultBufferSize + * Size of the client shadow fault buffer to register. + * + * shadowFaultBufferPteArray + * Pages of client shadow fault buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES 1500 +#define NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9DU) + +typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS { + NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferQueuePhysAddr, 8); + NvU32 shadowFaultBufferSize; + NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES], 8); +} NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER + * + * Pin PDEs for Global VA range on the server RM and then mirror the client's page + * directory/tables in the server. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER (0x20800a9f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID (0x9FU) + +typedef struct NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS { + NV_DECLARE_ALIGNED(NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS PdeCopyParams, 8); +} NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER + * + * This command requests physical RM to disable the client shadow fault buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x9E" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X + * + * This command can be used to boost P-State the highest for a limited + * duration for the associated subdevice. Boosts from different clients are being tracked + * independently. Note that there are other factors that can limit P-States so the resulting + * P-State may differ from expectation. + * + * flags [IN] + * This parameter specifies the actual command. _CLEAR is to clear existing boost. + * and _BOOST_TO_MAX is to boost to the highest P-State. + * + * boostDuration [IN] + * This parameter specifies the duration of the boost in seconds. This has to be less + * than NV2080_CTRL_PERF_BOOST_DURATION_MAX. + * + * gfId [IN] + * This specifies Id of the Kernel RM that is requesting the Boost + * + * bOverrideInfinite[IN] + * This parameter specifies if we want to override already registered infinite boost for the specific Kernel RM. + * This should be NV_TRUE only in case when we are removing the current infinite boost for a specific Kernel RM + * and setting the boost duration to a next maximum duration registered for the Kernel RM in question. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X (0x20800aa0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID (0xA0U) + +typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X { + NvU32 flags; + NvU32 boostDuration; + NvU32 gfId; + NvBool bOverrideInfinite; +} NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X + * + * Clear the boost for specific Kernel RM + * + * bIsCudaClient [IN] + * Specifies if the request is for clearing the CUDA boost or regular boost + * NV_TRUE -> CUDA boost, NV_FALSE otherwise + * + * gfId [IN] + * Specifies Id of the Kernel RM that is requesting Boost clear + * + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X (0x20800aa1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID (0xA1U) + +typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X { + + NvBool bIsCudaClient; + NvU32 gfId; +} NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X; + +/* + * NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO + * + * Retrieves skyline information about the GPU. Params are sized to currently known max + * values, but will need to be modified in the future should that change. + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO (0x20800aa2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES 8 +#define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS 8 +/*! + * NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO + * skylineVgpcSize[OUT] + * - TPC count of non-singleton VGPCs + * singletonVgpcMask[OUT] + * - Mask of active Singletons + * maxInstances[OUT] + * - Max allowed instances of this skyline concurrently on a GPU + * computeSizeFlag + * - One of NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* flags which is associated with this skyline + * numNonSingletonVgpcs + * - Number of VGPCs with non-zero TPC counts which are not singletons + */ +typedef struct NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO { + NvU8 skylineVgpcSize[NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS]; + NvU32 singletonVgpcMask; + NvU32 maxInstances; + NvU32 computeSizeFlag; + NvU32 numNonSingletonVgpcs; +} NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO; + +/*! + * NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS + * skylineTable[OUT] + * - TPC count of non-singleton VGPCs + * - Mask of singleton vGPC IDs active + * - Max Instances of this skyline possible concurrently + * - Associated compute size with the indexed skyline + * - Number of VGPCs with non-zero TPC counts which are not singletons + * validEntries[OUT] + * - Number of entries which contain valid info in skylineInfo + */ +#define NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID (0xA2U) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS { + NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO skylineTable[NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES]; + NvU32 validEntries; +} NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE + */ +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE (0x20800aa3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA3" */ + +/*! + * @ref NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION + */ +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE (0x20800aa4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA4" */ + +/*! + * @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONS + */ +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES (0x20800aa5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA5" */ + +/*! + * @ref NV2080_CTRL_CMD_GPU_GET_PARTITIONS + */ +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES (0x20800aa6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA6" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED + * + * Tell Physical RM whether any ZBC-kind surfaces are allocated. + * If PF and all VFs report false, ZBC table can be flushed by Physical RM. + * + * bZbcReferenced [IN] + * NV_TRUE -> ZBC-kind (and no _SKIP_ZBCREFCOUNT flag) are allocated in Kernel RM + * + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED (0x20800a69) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID (0x69U) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS { + NvBool bZbcSurfacesExist; +} NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE + * + * Export the resource and placement information about a gpu instance such that a + * similar gpu instance can be recreated from scratch in the same position on the + * same or similar GPU. Note that different GPUs may have different physical + * resources due to floorsweeping, and an imported gpu instance is not guaranteed + * to get the exact same resources as the exported gpu instance, but the imported + * gpu instance should behave identically with respect to fragmentation and + * placement / span positioning. + */ +#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE (0x20800aa7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA7" */ +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE (0x20800aa8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA8" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE + * + * Create a gpu instance resembling the exported instance info. Note that + * different GPUs may have different physical resources due to floorsweeping, + * and an imported gpu instance is not guaranteed to get the exact same resources + * as the exported gpu instance, but the imported gpu instance should behave + * identically with respect to fragmentation and placement / span positioning. + */ +#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE (0x20800aa9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA9" */ +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE (0x20800aaa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xAA" */ + +#define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE 4 +typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO { + NV_DECLARE_ALIGNED(NvU64 enginesMask[NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE], 8); + NvU32 partitionFlags; + NvU32 gpcMask; + NvU32 virtualGpcCount; + NvU32 veidOffset; + NvU32 veidCount; +} NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO; + +typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS { + NvU32 swizzId; + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO info, 8); +} NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT + * + * Invalidate and/or evict the L2 cache + * + * flags [IN] + * flags that specify required actions + * + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT (0x20800a6c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID (0x6cU) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS { + NvU32 flags; +} NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS; + +#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL (0x00000001) +#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_FIRST (0x00000002) +#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_LAST (0x00000004) +#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_NORMAL (0x00000008) +#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_CLEAN (0x00000010) +#define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_WAIT_FB_PULL (0x00000020) + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES + * + * Flush all L2 Rams and Caches using the ELPG flush + * + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES (0x20800a6d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6D" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO + * + * This command obtains information from physical RM for use by CPU-RM + * + * Data fields -> + * bPcieGen4Capable - tells whether PCIe is Gen4 capable + */ +#define NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO (0x20800aac) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0xacU) + +typedef struct NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS { + NvBool bPcieGen4Capable; + NvBool bIsC2CLinkUp; + NV_DECLARE_ALIGNED(NvU64 dmaWindowStartAddress, 8); +} NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG + * + * Program HSHUB Peer Conn Config space. + * + * programPeerMask[IN] + * If nonzero, the peer mask for programming peers based on hshub connectivity. + * + * invalidatePeerMask[IN] + * If nonzero, the peer mask for invalidating peers. + * + * programPciePeerMask[IN] + * If nonzero, the peer mask for programming peers in pcie case. + * + * Possible status values returned are: + * NV_OK + * NV_WARN_NOTHING_TO_DO + * If all peer masks are zero. + */ +#define NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG (0x20800a88) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID (0x88U) + +typedef struct NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS { + NvU32 programPeerMask; + NvU32 invalidatePeerMask; + NvU32 programPciePeerMask; +} NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_HSHUB_FIRST_LINK_PEER_ID + * + * Given a mask of link ids, find the first with a valid peerId. + * + * linkMask[IN] + * Mask of linkIds to check. + * + * peerId[OUT] + * The peerId for the lowest-index link with a valid peerId, if any. + * If none found, NV2080_CTRLINTERNAL_HSHUB_FIRST_LINK_PEER_ID_INVALID_PEER (return value will still be NV_OK). + * + * Possible status values returned are: + * NV_OK + * + */ +#define NV2080_CTRL_CMD_INTERNAL_HSHUB_FIRST_LINK_PEER_ID (0x20800a89) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_INVALID_PEER 0xffffffff + +#define NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS_MESSAGE_ID (0x89U) + +typedef struct NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS { + NvU32 linkMask; + NvU32 peerId; +} NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS + * + * Get the Hshub Ids connected to the other end of links. + * + * linkMask[IN] + * A mask of link ids to query. + * + * hshubIds[OUT] + * For each set bit in the link mask, the peer Hshub Id. + * + * Possible status values returned are: + * NV_OK + * NV_WARN_NOTHING_TO_DO + * If the mask is zero. + */ +#define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS (0x20800a8a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE 32 + +#define NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID (0x8aU) + +typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS { + NvU32 linkMask; + NvU8 hshubIds[NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE]; +} NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS + * + * Return the number of HSHUB units. + * + * numHshubs[OUT] + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS (0x20800a8b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID (0x8bU) + +typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS { + NvU32 numHshubs; +} NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID + * + * Return the next hshubId after the given hshubId. + * + * hshubId[IN/OUT] + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID (0x20800a8c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID (0x8cU) + +typedef struct NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS { + NvU8 hshubId; +} NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR + * + * Enable compute peer addressing mode + * This command accepts no parameters. + */ + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR (0x20800aad) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xad" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR + * + * Get/Set NVSwitch fabric address for FLA + * + * [In] bGet + * Whether to get or set the NVSwitch fabric address + * [In/Out] addr + * Address that is to be set or retrieved. + */ +#define NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID (0xaeU) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS { + NvBool bGet; + NV_DECLARE_ALIGNED(NvU64 addr, 8); +} NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR (0x20800aae) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_BIF_GET_ASPM_L1_FLAGS + * + * This command obtains information from physical RM for use by CPU-RM + * + * Data fields -> + * bCyaMaskL1 + * bEnableAspmDtL1 + */ +#define NV2080_CTRL_CMD_INTERNAL_BIF_GET_ASPM_L1_FLAGS (0x20800ab0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS_MESSAGE_ID (0xb0U) + +typedef struct NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS { + NvBool bCyaMaskL1; + NvBool bEnableAspmDtL1; +} NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT + * + * Sets number of VM slots that are active in VGPU's scheduler + * + * maxActiveVGpuVMCount [IN] + * Number of VM slots that are active in vGPU's scheduler. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OUT_OF_RANGE - Passed value is out of range + * NV_ERR_NO_MEMORY - Out of memory + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT (0x20800ab1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID" */ + +/*! + * Maximum value of VM slots that are active in vGPU's scheduler. + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_MAX_ACTIVE_VGPU_VM_COUNT_MAX_VALUE 32 + +#define NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID (0xB1U) + +typedef struct NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS { + NvU8 maxActiveVGpuVMCount; +} NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS + * + * Disable all NVLINK FB peers + * + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS (0x20800a6e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6E" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE + * + * Program GPU in raw / legacy compression mode + * + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE (0x20800a6f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID (0x6fU) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS { + NvBool bRawMode; +} NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_CCU_MAP + * + * This command gets the shared buffer memory descriptor from the CPU-RM and maps to it + * in physical-RM. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_ADDRESS + */ +#define NV2080_CTRL_CMD_INTERNAL_CCU_MAP (0x20800ab3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX 1 +#define NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID (0xB3U) + +typedef struct NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 phyAddr[NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE + NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX], 8); +} NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS; +/* + * NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP + * + * This command unmaps the shared buffer memory mapping in physical-RM + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP (0x20800ab4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID (0xB4U) + +typedef struct NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS { + NvBool bDevShrBuf; + NvBool bMigShrBuf; +} NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS; + +/*! + * NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO + * + * [in] gpuId + * GPU ID. + * [in] gpuInstance + * GPU instance. + * [in] p2pCaps + * Peer to peer capabilities discovered between the GPUs. + * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. + * [in] p2pOptimalReadCEs + * Mask of CEs to use for p2p reads over Nvlink. + * [in] p2pOptimalWriteCEs + * Mask of CEs to use for p2p writes over Nvlink. + * [in] p2pCapsStatus + * Status of all supported p2p capabilities. + * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. + * [in] busPeerId + * Bus peer ID. For an invalid or a non-existent peer this field + * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. + */ +typedef struct NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO { + NvU32 gpuId; + NvU32 gpuInstance; + NvU32 p2pCaps; + NvU32 p2pOptimalReadCEs; + NvU32 p2pOptimalWriteCEs; + NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; + NvU32 busPeerId; +} NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO; + +/*! + * NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS + * + * An internal call to propagate the peer to peer capabilities of peer GPUs + * to the Physical RM. These capabilities are to be consumed by the vGPU GSP plugin. + * This control is used to both add and and update the peer to peer capabilities. + * The existing GPU entries will be updated and those which don't exist will be added. + * Use NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS to remove the added entries. + * + * [in] peerGpuCount + * The number of the peerGpuInfos entries. + * [in] peerGpuInfos + * The array of NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS entries, describing + * the peer to peer capabilities of the specified GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT - Invalid peerGpuCount + * NV_ERR_INSUFFICIENT_RESOURCES - Total GPU count exceeds the maximum value + */ +#define NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS (0x20800ab5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID (0xB5U) + +typedef struct NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS { + NvU32 peerGpuCount; + NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO peerGpuInfos[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; +} NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS + * + * An internal call to remove the cached peer to peer capabilities of peer GPUs + * from the Physical RM. + * + * [in] peerGpuIdCount + * The number of the peerGpuIds entries. + * [in] peerGpuIds + * The array of GPU IDs, specifying the GPU for which the entries need to be removed. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT - Invalid peerGpuIdCount + * NV_ERR_OBJECT_NOT_FOUND - Invalid peerGpuIds[] entry + */ +#define NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS (0x20800ab6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID (0xB6U) + +typedef struct NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS { + NvU32 peerGpuIdCount; + NvU32 peerGpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; +} NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS; + + + +/*! + * NV2080_CTRL_CMD_INTERNAL_BUS_GET_PCIE_P2P_CAPS + * + * This command returns the GPU's PCIE P2P caps + * + * [in] bCommonPciSwitchFound + * All GPUs are under the same PCI switch + * [out] p2pReadCapsStatus + * [out] p2pWriteCapsStatus + * These members returns status of all supported p2p capabilities. Valid + * status values include: + * NV0000_P2P_CAPS_STATUS_OK + * P2P capability is supported. + * NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED + * Chipset doesn't support p2p capability. + * NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED + * GPU doesn't support p2p capability. + * NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED + * IOH topology isn't supported. For e.g. root ports are on different + * IOH. + * NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY + * P2P Capability is disabled by a regkey. + * NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED + * P2P Capability is not supported. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_INTERNAL_GET_PCIE_P2P_CAPS (0x20800ab8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID (0xB8U) + +typedef struct NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS { + NvBool bCommonPciSwitchFound; + NvU8 p2pReadCapsStatus; + NvU8 p2pWriteCapsStatus; +} NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO + * + * Enable/disable PCIe Relaxed Ordering. + * + */ +#define NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO (0x20800ab9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID (0xB9U) + +typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS { + // Enable/disable PCIe relaxed ordering + NvBool enableRo; +} NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE + * + * An internal call to invoke the sequence VGA register reads & writes to + * perform save and restore of VGA + * + * [in] saveOrRestore + * To indicate whether save or restore needs to be performed. + * [in] useVbios + * Primary VGA indication from OS. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE (0x20800a76) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS_MESSAGE_ID (0x76U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS { + + NvBool bSaveOrRestore; + NvBool bUseVbios; +} NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE + * + * To perform restore operation from saved fonts. + * + * [in] saveOrRestore + * To indicate whether save or restore needs to be performed. + * [in] useVbios + * Primary VGA indication from OS. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE (0x20800a77) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS_MESSAGE_ID (0x77U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS { + + NvBool bWriteCr; +} NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS; + +/*! + * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES + * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES + */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xba" */ + +/*! + * NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE + * + * This structure specifies resources in an execution partition + * + * computeSize[OUT] + * - NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* associated with this profile + * + * gfxGpcCount[OUT] + * - Total Number of GFX Supporting GPCs in this partition + * + * gpcCount[OUT] + * - Total Number of GPCs in this partition (including GFX Supported GPCs) + * + * veidCount[OUT] + * - Number of VEIDs allocated to this profile + * + * smCount[OUT] + * - Number of SMs usable in this profile + */ +typedef struct NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE { + NvU8 computeSize; + NvU32 gfxGpcCount; + NvU32 gpcCount; + NvU32 veidCount; + NvU32 smCount; + NvU32 physicalSlots; +} NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE; + +/*! + * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS + * + * This structure specifies resources in an execution partition + * + * profileCount[OUT] + * - Total Number of profiles filled + * + * profiles[OUT] + * - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles + */ +#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBBU) + +typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS { + NvU32 profileCount; + NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE]; +} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS; + + + +/* + * NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE + * + * This command sets the ccu stream to enable/disable state. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE (0x20800abd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID (0xBDU) + +typedef struct NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS { + NvBool bStreamState; +} NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT + * + * Attach GPU to the external device. + * + * [in] bExtDevFound + * To enable GPIO interrupts. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT (0x20800abe) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID (0xBEU) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS { + NvBool bExtDevFound; +} NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS + * + * Optimize the Gsync timing parameters + * + * [in] timingParameters + * Timing parameters passed by client. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS (0x20800abf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID (0xBFU) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS { + NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS timingParameters; +} NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS + * + * Get displayIDs supported by the display. + * + * [out] displayIds + * Associated display ID with head. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS (0x20800ac0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID" */ + +#define NV2080_MAX_NUM_HEADS 4 + +#define NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID (0xC0U) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS { + NvU32 displayIds[NV2080_MAX_NUM_HEADS]; +} NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC + * + * Set the Stereo sync for Gsync + * + * [in] slave + * Slave GPU head status. + * [in] localSlave + * Slave GPU head status but are not coupled. + * [in] master + * Master GPU head status. + * [in] regstatus + * Register status of status1 register. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC (0x20800ac1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID (0xC1U) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS { + NvU32 slave[NV2080_MAX_NUM_HEADS]; + NvU32 localSlave[NV2080_MAX_NUM_HEADS]; + NvU32 master[NV2080_MAX_NUM_HEADS]; + NvU32 regStatus; +} NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES + * + * Get vertical active lines for given head. + * + * [in] head + * For the headIdx which we need active. + * [out] vActiveLines + * Vertical active lines. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES (0x20800ac4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID (0xC4U) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS { + NvU32 headIdx; + NvU32 vActiveLines; +} NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID + * + * Verifies if this displayId is valid. + * + * [in] displays + * Displays given by the client + * + * [out] displayId + * DisplayId for the given display + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID (0x20800ac9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID (0xC9U) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS { + NvU32 displays; + NvU32 displayId; +} NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC + * + * Disable the raster sync gpio on the other P2060 GPU + * that's connected to master over Video bridge. + * + * [in] bEnableMaster + * If it is master gpu. + * + * [out] bRasterSyncGpioSaved + * If raster sync GPIO direction is saved or not. + * + * [in/out] bRasterSyncGpioDirection + * During save it gets the direction. + * In restores it sets the direction. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC (0x20800aca) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID (0xCAU) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS { + NvBool bEnableMaster; + NvBool bRasterSyncGpioSaved; + NvU32 bRasterSyncGpioDirection; +} NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_FBSR_INIT + * + * Initialize FBSR on GSP to prepare for suspend-resume + * + * [in] fbsrType + * Fbsr object type + * [in] numRegions + * Number of regions that GSP should allocate records for + * [in] hClient + * Handle to client of SYSMEM memlist object + * [in] hSysMem + * Handle to SYSMEM memlist object + * [in] gspFbAllocsSysOffset + * Offset in SYSMEM for GSP's FB Allocations + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_FBSR_INIT (0x20800ac2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID (0xC2U) + +typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS { + NvU32 fbsrType; + NvU32 numRegions; + NvHandle hClient; + NvHandle hSysMem; + NV_DECLARE_ALIGNED(NvU64 gspFbAllocsSysOffset, 8); +} NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO + * + * Send info of FB region that will be saved/restored by GSP on suspend-resume + * + * [in] fbsrType + * Fbsr object type + * [in] hClient + * Handle to client of FBMEM memlist object + * [in] hVidMem + * Handle to FBMEM memlist object + * [in] vidOffset + * Offset in FBMEM region to save/restore + * [in] sysOffset + * Offset in SYSMEM region to save to/restore from + * [in] size + * Size of region being saved/restored + */ +#define NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO (0x20800ac3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID (0xC3U) + +typedef struct NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS { + NvU32 fbsrType; + NvHandle hClient; + NvHandle hVidMem; + NV_DECLARE_ALIGNED(NvU64 vidOffset, 8); + NV_DECLARE_ALIGNED(NvU64 sysOffset, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); +} NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB + * + * This command is used to get the amount of host reserved FB + * + * hostReservedFb [OUT] + * Amount of FB reserved for the host + * vgpuTypeId [IN] + * The Type ID for VGPU profile + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB (0x20800ac5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID (0xC5U) + +typedef struct NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS { + NV_DECLARE_ALIGNED(NvU64 hostReservedFb, 8); + NvU32 vgpuTypeId; +} NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD + * + * This command initiates brightc module state load. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD (0x20800ac6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_ACPI_DSM_READ_SIZE (0x1000) /* finn: Evaluated from "(4 * 1024)" */ + +#define NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID (0xC6U) + +typedef struct NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS { + NvU32 status; + NvU16 backLightDataSize; + NvU8 backLightData[NV2080_CTRL_ACPI_DSM_READ_SIZE]; +} NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS; + +/* + * NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL + * + * Returns number of active links allowed per IOCTRL + * + * [Out] numActiveLinksPerIoctrl + */ +#define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xC7U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS { + NvU32 numActiveLinksPerIoctrl; +} NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS; +#define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL (0x20800ac7U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */ +/* + * NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL + * + * Returns number of links per IOCTRL + * + * [Out] numLinksPerIoctrl + */ +#define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xC8U) + +typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS { + NvU32 numLinksPerIoctrl; +} NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS; +#define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL (0x20800ac8U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE + * + * Update the system control capability + * + * bIsSysCtrlSupported [IN] + If the system control is supported + * bIsPlatformLegacy [OUT] + If the platform is legacy + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE (0x20800acb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID (0xCBU) + +typedef struct NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS { + NvBool bIsSysCtrlSupported; + NvBool bIsPlatformLegacy; +} NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS; + +/*! + * Macros for PFM_REQ_HNDLR_STATE_SYNC data types. + */ +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_PMGR 0x00U +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_THERM 0x01U +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_SMBPBI 0x02U + +/*! + * Structure representing static data for a PFM_REQ_HNDLR_STATE_SYNC_SMBPBI. + */ +typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI { + /*! + * PFM sensor ID + */ + NvU32 sensorId; + + /*! + * PFM sensor limit value if required + */ + NvU32 limit; +} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI; + +/*! + * Structure of static information describing PFM_REQ_HNDLR_STATE_SYNC data types. + */ +typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA { + /*! + * @ref NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_ + */ + NvU8 type; + + /*! + * Type-specific information. + */ + union { + NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI smbpbi; + } data; +} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA; + +/*! + * Macros for PFM_REQ_HNDLR_STATE_SYNC flags for specific operation. + */ +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_PMGR_LOAD 0x00U +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_THERM_INIT 0x01U +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_CLEAR 0x02U +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_SET 0x03U + +/*! + * Structure of static information describing PFM_REQ_HNDLR_STATE_SYNC params. + */ +typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS { + /*! + * @ref NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_ + */ + NvU8 flags; + + /*! + * Type-specific information. + */ + NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA syncData; +} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC + * + * State sync with platform req handler and SMBPBI + * + * flags [IN] + * Flags that needs sync operation between physical and kernel + * + * syncData [IN] + * Sync payload data + * + */ +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC (0x20800acc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xCC" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC + * + * State sync with platform req handler and SMBPBI + * + * flags [IN] + * Flags that needs sync operation between physical and kernel + * + * syncData [IN] + * Sync payload data + * + */ +#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC (0x20800acd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xCD" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE + * + * Query Coherent FB Aperture Size. + * + */ +#define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID (0xDAU) + +typedef struct NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS { + // Get Coherent Fb Aperture Size + NV_DECLARE_ALIGNED(NvU64 coherentFbApertureSize, 8); +} NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS; + + +/*! + * Macros for NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE flag + */ +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_FORCED_OFF_STATUS 0x00U +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_STATUS 0x01U + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE + * + * Queries PM1 Forced off / PM1 Available status + * + * flag [IN] + * Fetch PM1 Forced off / PM1 Available status based on value. + * bStatus [OUT] + * PM1 Forced off / PM1 Available is true or false. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMETS + */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE (0x20800ace) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID (0xCEU) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS { + /*! + * Fetch PM1 Forced off / PM1 Available status based on value. + */ + NvU8 flag; + + /*! + * PM1 Forced off / PM1 Available status + */ + NvBool bStatus; +} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE + * + * Set PM1 state to enabled / disabled (boost clocks). + * + * bEnable [IN] + * NV_TRUE means enable PM1, NV_FALSE means disable. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE (0x20800acf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID (0xCFU) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS { + + /*! + * NV_TRUE means enable PM1, NV_FALSE means disable. + */ + NvBool bEnable; +} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT + * + * Updates EDPpeak Limit of GPU + * + * bEnable [IN] + * Enable or Reset the settings + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + * NV_ERR_NOT_READY + */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT (0x20800ad0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID (0xD0U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS { + NvBool bEnable; +} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT + * + * Updates Target Temperature of GPU + * + * targetTemp [IN] + * Target Temperature Set from SBIOS + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT (0x20800ad1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID (0xD1U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS { + NvS32 targetTemp; +} NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE + * + * Enable / disable CTGP MODE + * + * bEnable [IN] + * Enable or Reset the settings + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE (0x20800ad2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID (0xD2U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS { + NvBool bEnable; +} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2 + * + * Configuration of the turbo v2 parameters for NVPCF-Turbo arb control + * + * ctgpOffsetmW [IN] + * TGP MODE Offset in mW + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2 (0x20800ad3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID (0xD3U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS { + NvU32 ctgpOffsetmW; +} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO + * + * Query VPstatese info. Get VPS PS2.0 support / get highest VP State Idx and requested VP State Idx + * + * bVpsPs20Supported [OUT] + * Reflects Vpstates PS20 support + * vPstateIdxHighest [OUT} + * Reflects Highest VPstate Idx + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO (0x20800ad4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID (0xD4U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS { + /*! + * Reflects Vpstates PS20 support + */ + NvBool bVpsPs20Supported; + + /*! + * Get highest VPState Idx from VBIOS + */ + NvU32 vPstateIdxHighest; +} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING + * + * Get vPstate mapping for requested pStateIdx + * + * pStateIdx [IN] + * Requested PState Idx + * vPstateIdx [OUT} + * Mapped VPstate Idx + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING (0x20800ad5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID (0xD5U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS { + /*! + * Requested PState Idx + */ + NvU32 pStateIdx; + + /*! + * Mapped VPstate Idx + */ + NvU32 vPstateIdxMapping; +} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE + * + * Set requested VPstate + * + * vPstateIdx [IN] + * VPstate Idx to be set + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE (0x20800ad6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID (0xD6U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS { + + /*! + * NV_TRUE means enable PM1, NV_FALSE means disable. + */ + NvU32 vPstateIdx; +} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS; + +/* + * This command unsets Dynamic Boost limit when nvidia-powerd is terminated unexpectedly. + */ +#define NV2080_CTRL_CMD_INTERNAL_PMGR_UNSET_DYNAMIC_BOOST_LIMIT (0x20800a7b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7B" */ + +/* ctrl2080internal_h */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h new file mode 100644 index 0000000..9a121f9 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h @@ -0,0 +1,100 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080lpwr.finn +// + + + +/*! + * NV2080_CTRL_CMD_LPWR_DIFR_CTRL + * + * This command is used to control the DIFR + * feature behavior. + * + */ +#define NV2080_CTRL_CMD_LPWR_DIFR_CTRL (0x20802801) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_LPWR_INTERFACE_ID << 8) | NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS_MESSAGE_ID" */ + +/*! + * @brief Various Values for control + */ +// Disable the DIFR +#define NV2080_CTRL_LPWR_DIFR_CTRL_DISABLE (0x00000001) +// Enable the DIFR +#define NV2080_CTRL_LPWR_DIFR_CTRL_ENABLE (0x00000002) + +// Support status for DIFR +#define NV2080_CTRL_LPWR_DIFR_CTRL_SUPPORT_STATUS (0x00000003) + +/*! + * Structure containing DIFR control call Parameters + */ +#define NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS { + NvU32 ctrlParamVal; +} NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS; + +// Values for the SUPPORT Control Status +#define NV2080_CTRL_LPWR_DIFR_SUPPORTED (0x00000001) +#define NV2080_CTRL_LPWR_DIFR_NOT_SUPPORTED (0x00000002) + +/*! + * NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE + * + * This control call is used to send the prefetch response + * + */ +#define NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE (0x20802802) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_LPWR_INTERFACE_ID << 8) | NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS_MESSAGE_ID" */ + +/*! + * @brief Various Values of Reponses for Prefetch Status + */ + +// Prefetch is successfull. +#define NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS (0x00000001) +// OS Filps are enabled, so prefetch can not be done. +#define NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_OS_FLIPS_ENABLED (0x00000002) +// Current Display surface can not fit in L2 +#define NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_INSUFFICIENT_L2_SIZE (0x00000003) +// Fatal and un recoverable Error +#define NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_CE_HW_ERROR (0x00000004) + +/*! + * Structure containing DIFR prefetch response control call Parameters + */ +#define NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS { + NvU32 responseVal; +} NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS; + + +// _ctrl2080lpwr_h_ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h new file mode 100644 index 0000000..2bb1c30 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h @@ -0,0 +1,325 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080mc.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "nvcfg_sdk.h" + +/* NV20_SUBDEVICE_XX mc control commands and parameters */ + +/** + * NV2080_CTRL_CMD_MC_GET_ARCH_INFO + * + * This command returns chip architecture information from the + * master control engine in the specified GPU. + * + * architecture + * This parameter specifies the architecture level for the GPU. + * implementation + * This parameter specifies the implementation of the architecture + * for the GPU. + * revision + * This parameter specifies the revision of the mask used to produce + * the GPU. + * subRevision + * This parameter specific the sub revision of the GPU. Value is one of + * NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_* + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_MC_GET_ARCH_INFO (0x20801701) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS { + NvU32 architecture; + NvU32 implementation; + NvU32 revision; + NvU8 subRevision; +} NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS; + +/* valid architecture values */ + + +#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_T23X (0xE0000023) + + +#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100 (0x00000160) +#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100 (0x00000170) + + + +/* valid ARCHITECTURE_T23X implementation values */ + + +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234 (0x00000004) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234D (0x00000005) + + +/* valid ARCHITECTURE_TU10x implementation values */ +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU100 (0x00000000) + + +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU102 (0x00000002) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU104 (0x00000004) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU106 (0x00000006) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU116 (0x00000008) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU117 (0x00000007) + + +/* valid ARCHITECTURE_GA10x implementation values */ +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA100 (0x00000000) + + +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA102 (0x00000002) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA103 (0x00000003) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA104 (0x00000004) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA106 (0x00000006) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA107 (0x00000007) +#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA10B (0x0000000B) + + + +/* Valid Chip sub revisions */ +#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_NO_SUBREVISION (0x00000000) +#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_P (0x00000001) +#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_Q (0x00000002) +#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_R (0x00000003) + +/* + * NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS + * + * This command instructs the RM to service interrupts for the specified + * engine(s). + * + * engines + * This parameter specifies which engines should have their interrupts + * serviced. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS (0x20801702) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MC_ENGINE_ID_GRAPHICS 0x00000001 +#define NV2080_CTRL_MC_ENGINE_ID_ALL 0xFFFFFFFF + +#define NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS { + NvU32 engines; +} NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS; + + +/* + * NV2080_CTRL_CMD_MC_GET_MANUFACTURER + * + * This command returns the GPU manufacturer information for the associated + * subdevice. + * + * manufacturer + * This parameter returns the manufacturer value for the GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_MC_GET_MANUFACTURER (0x20801703) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS { + NvU32 manufacturer; +} NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS; + + + +/* + * NV2080_CTRL_CMD_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS + * + * This command is used to allow clients to query whether hostclk slowdown is + * disabled. + * + * bDisabled + * This parameter will hold the status of hostclk slowdown + * + * Possible status values returned are: + * NV_OK + * + */ +#define NV2080_CTRL_CMD_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS (0x20801708) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS { + NvBool bDisabled; +} NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_MC_SET_HOSTCLK_SLOWDOWN_STATUS + * + * This command is used to allow clients to disable/enable hostclk slowdown. + * + * bDisable + * When this parameter is set to TRUE, RM should disable hostclk slowdown. + * If it is set to FALSE, RM will attempt to enable hostclk slowdown, but + * in this case, slowdown is NOT guaranteed to be enabled since there may + * be other reason (like regkey) preventing slowdown. + * + * Possible status values returned are: + * NV_OK + * + */ +#define NV2080_CTRL_CMD_MC_SET_HOSTCLK_SLOWDOWN_STATUS (0x20801709) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS { + NvBool bDisable; +} NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS; + + + +/* + * NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP + * + * This call will setup RM to either service or ignore the + * repayable fault interrupt. + * This is a privileged call that can only be called by the UVM driver + * when it will take ownership of the repalayable fault interrupt. + * + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + * NVOS_STATUS_ERROR_INVALID_ARGUMENT + * NVOS_STATUS_ERROR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP (0x2080170c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS { + NvBool bOwnedByRm; +} NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS; + +/* + * NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS + * + * This command gets the notification interrupt vectors device for all VGPU engines from Host RM. + * + * Parameters: + * + * entries [out] + * A buffer to store up to MAX_ENGINES entries of type + * NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY. + * + * numEntries [out] + * Number of populated entries in the provided buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS (0x2080170d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES 256 + +typedef struct NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY { + NvU32 nv2080EngineType; + NvU32 notificationIntrVector; +} NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY; + +#define NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS { + NvU32 numEntries; + NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY entries[NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES]; +} NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS; + +/* + * NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE + * + * This command gets the static interrupts needed by VGPU from Host RM. + * + * Parameters: + * + * entries [out] + * A buffer to store up to MAX_ENGINES entries of type + * NV2080_CTRL_MC_STATIC_INTR_ENTRY. + * + * numEntries [out] + * Number of populated entries in the provided buffer. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE (0x2080170e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX 32 + +// Interface defines for static MC_ENGINE_IDX defines +#define NV2080_INTR_TYPE_NULL (0x00000000) +#define NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT (0x00000001) +#define NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT_ERROR (0x00000002) +#define NV2080_INTR_TYPE_INFO_FAULT (0x00000003) +#define NV2080_INTR_TYPE_REPLAYABLE_FAULT (0x00000004) +#define NV2080_INTR_TYPE_REPLAYABLE_FAULT_ERROR (0x00000005) +#define NV2080_INTR_TYPE_ACCESS_CNTR (0x00000006) +#define NV2080_INTR_TYPE_TMR (0x00000007) +#define NV2080_INTR_TYPE_CPU_DOORBELL (0x00000008) +#define NV2080_INTR_TYPE_GR0_FECS_LOG (0x00000009) +#define NV2080_INTR_TYPE_GR1_FECS_LOG (0x0000000A) +#define NV2080_INTR_TYPE_GR2_FECS_LOG (0x0000000B) +#define NV2080_INTR_TYPE_GR3_FECS_LOG (0x0000000C) +#define NV2080_INTR_TYPE_GR4_FECS_LOG (0x0000000D) +#define NV2080_INTR_TYPE_GR5_FECS_LOG (0x0000000E) +#define NV2080_INTR_TYPE_GR6_FECS_LOG (0x0000000F) +#define NV2080_INTR_TYPE_GR7_FECS_LOG (0x00000010) + +typedef struct NV2080_CTRL_MC_STATIC_INTR_ENTRY { + NvU32 nv2080IntrType; + NvU32 pmcIntrMask; + NvU32 intrVectorStall; + NvU32 intrVectorNonStall; +} NV2080_CTRL_MC_STATIC_INTR_ENTRY; + +#define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS { + NvU32 numEntries; + NV2080_CTRL_MC_STATIC_INTR_ENTRY entries[NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX]; +} NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS; + +/* _ctrl2080mc_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h new file mode 100644 index 0000000..f1e490b --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h @@ -0,0 +1,338 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080nvd.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +#include "ctrl/ctrlxxxx.h" +/* + * NV2080_CTRL_CMD_NVD_GET_DUMP_SIZE + * + * This command gets the expected dump size of a particular GPU dump component. + * Note that events that occur between this command and a later + * NV2080_CTRL_CMD_NVD_GET_DUMP command could alter the size of + * the buffer required. + * + * component + * One of NVDUMP_COMPONENT < 0x400 defined in nvdump.h to estimate + * the size of. + * size + * This parameter returns the expected size. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT if component is invalid. + * + */ + +#define NV2080_CTRL_CMD_NVD_GET_DUMP_SIZE (0x20802401) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS { + NvU32 component; + NvU32 size; +} NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS; + +/* + * NV2080_CTRL_CMD_NVD_GET_DUMP + * + * This command gets a dump of a particular GPU dump component. If triggers + * is non-zero, the command waits for the trigger to occur + * before it returns. + * + * pBuffer + * This parameter points to the buffer for the data. + * component + * One of NVDUMP_COMPONENT < 0x400 defined in nvdump.h to select + * for dumping. + * size + * On entry, this parameter specifies the maximum length for + * the returned data. On exit, it specifies the number of bytes + * returned. + * + * Possible status values returned are: + * NV_OK + * NVOS_ERROR_INVALID_ARGUMENT if component is invalid. + * NVOS_ERROR_INVALID_ADDRESS if pBuffer is invalid + * NVOS_ERROR_INVALID_???? if the buffer was too small + * + * + */ +#define NV2080_CTRL_CMD_NVD_GET_DUMP (0x20802402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_NVD_GET_DUMP_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pBuffer, 8); + NvU32 component; + NvU32 size; +} NV2080_CTRL_NVD_GET_DUMP_PARAMS; + +/* + * NV2080_CTRL_CMD_NVD_GET_NOCAT_JOURNAL + * + * This command returns the contents of the Journal used by NOCAT, and + * optionally clears the data + * + * clear: + * [IN] indicates if should the data be cleared after reporting + * + * JournalRecords : + * [OUT] an array of Journal records reported. + * + * outstandingAssertCount: + * [OUT] number of asserts that remain to be reported on. + * + * reportedAssertCount: + * [OUT] the number of asserts contained in the report + * + * asserts: + * [OUT] an array of up to NV2080_NOCAT_JOURNAL_MAX_ASSERT_RECORDS assert reports + */ + + +#define NV2080_CTRL_CMD_NVD_GET_NOCAT_JOURNAL (0x20802409) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID" */ + +#define NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER 1024 +#define NV2080_NOCAT_JOURNAL_MAX_STR_LEN 65 +#define NV2080_NOCAT_JOURNAL_MAX_JOURNAL_RECORDS 10 +#define NV2080_NOCAT_JOURNAL_MAX_ASSERT_RECORDS 32 + +// structure to hold clock details. +typedef struct NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS { + NvS32 userMinOffset; + NvS32 userMaxOffset; + NvU32 factoryMinOffset; + NvU32 factoryMaxOffset; + NvU32 lastActiveClock; + NvU32 lastActiveVolt; + NvU32 lastActivePoint; + NvU32 kappa; +} NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS; + + +// structure to hold clock configuration & state. +typedef struct NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG { + NvU32 pstateVer; + NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS gpcOverclock; + NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS mclkOverclock; + NvBool bUserOverclocked; + NvBool bFactoryOverclocked; +} NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG; + +// structure to hold the GPU context at the time of the report. +typedef struct NV2080_NOCAT_JOURNAL_GPU_STATE { + NvBool bValid; + NvU32 strap; + NvU16 deviceId; + NvU16 vendorId; + NvU16 subsystemVendor; + NvU16 subsystemId; + NvU16 revision; + NvU16 type; + NvU32 vbiosVersion; + NvBool bOptimus; + NvBool bMsHybrid; + NvBool bFullPower; + NvU32 vbiosOemVersion; + NvU16 memoryType; + NvU8 tag[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; + NvU8 vbiosProject[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; + NvBool bInFullchipReset; + NvBool bInSecBusReset; + NvBool bInGc6Reset; + NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG overclockCfg; +} NV2080_NOCAT_JOURNAL_GPU_STATE; + +#define NV2080_NOCAT_JOURNAL_REC_TYPE_UNKNOWN 0 +#define NV2080_NOCAT_JOURNAL_REC_TYPE_BUGCHECK 1 +#define NV2080_NOCAT_JOURNAL_REC_TYPE_ENGINE 2 +#define NV2080_NOCAT_JOURNAL_REC_TYPE_TDR 3 +#define NV2080_NOCAT_JOURNAL_REC_TYPE_RC 4 +#define NV2080_NOCAT_JOURNAL_REC_TYPE_ASSERT 5 +#define NV2080_NOCAT_JOURNAL_REC_TYPE_ANY 6 + +// this should be relative to the highest type value +#define NV2080_NOCAT_JOURNAL_REC_TYPE_COUNT (0x7) /* finn: Evaluated from "NV2080_NOCAT_JOURNAL_REC_TYPE_ANY + 1" */ +typedef struct NV2080_NOCAT_JOURNAL_ENTRY { + NvU8 recType; + NvU32 bugcheck; + NvU32 tdrBucketId; + NvU8 source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; + NvU32 subsystem; + NV_DECLARE_ALIGNED(NvU64 errorCode, 8); + NvU32 diagBufferLen; + NvU8 diagBuffer[NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER]; + NvU8 faultingEngine[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; + NvU32 mmuFaultType; + NvU32 mmuErrorSrc; + NvU8 tdrReason[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; +} NV2080_NOCAT_JOURNAL_ENTRY; + +typedef struct NV2080_NOCAT_JOURNAL_RECORD { + NvU32 GPUTag; + NV_DECLARE_ALIGNED(NvU64 loadAddress, 8); + NV_DECLARE_ALIGNED(NvU64 timeStamp, 8); + NV_DECLARE_ALIGNED(NvU64 stateMask, 8); + NV2080_NOCAT_JOURNAL_GPU_STATE nocatGpuState; + NV_DECLARE_ALIGNED(NV2080_NOCAT_JOURNAL_ENTRY nocatJournalEntry, 8); +} NV2080_NOCAT_JOURNAL_RECORD; + +// NOCAT activity counter indexes +// collection activity +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_IDX 0 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX 1 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECTED_IDX 2 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX 3 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX 4 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_DROPPED_IDX 5 + +// reporting activity +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX 6 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX 7 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX 8 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MISSED_IDX 9 + +// update activity +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX 10 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX 11 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX 12 + +// general errors +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX 13 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX 14 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX 15 + +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX 16 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES2_IDX 17 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CACHE_UPDATE_IDX 18 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_INSERT_RECORDS_IDX 19 + +// this should be relative to the highest counter index +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT (0x14) /* finn: Evaluated from "NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_INSERT_RECORDS_IDX + 1" */ + +#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY 0:0 +#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_YES 1 +#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_NO 0 + +#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS 1:1 +#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_YES 1 +#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_NO 0 + + +#define NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS { + NvU32 flags; + NvU32 nocatRecordCount; + NvU32 nocatOutstandingRecordCount; + NV_DECLARE_ALIGNED(NV2080_NOCAT_JOURNAL_RECORD journalRecords[NV2080_NOCAT_JOURNAL_MAX_JOURNAL_RECORDS], 8); + NvU32 activityCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT]; + NvU8 reserved[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; +} NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS; + + /* + * NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA + * + * This command reports the TDR data collected by KMD to be added to the + * nocat record + * + * dataType: + * [IN] specifies the type of data provided. + * targetRecordType + * [IN] specifies record type the data is intended for. + * nocatJournalData + * [IN] specifies the data to be added. + */ + +#define NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA (0x2080240b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID" */ + +// data types & structures +#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_EMPTY 0 +#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_TDR_REASON 1 +#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_INSERT_RECORD 2 +#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG 3 + +#define NV2080_CTRL_NOCAT_TDR_TYPE_NONE 0 +#define NV2080_CTRL_NOCAT_TDR_TYPE_LEGACY 1 +#define NV2080_CTRL_NOCAT_TDR_TYPE_FULLCHIP 2 +#define NV2080_CTRL_NOCAT_TDR_TYPE_BUSRESET 3 +#define NV2080_CTRL_NOCAT_TDR_TYPE_GC6_RESET 4 +#define NV2080_CTRL_NOCAT_TDR_TYPE_SURPRISE_REMOVAL 5 +#define NV2080_CTRL_NOCAT_TDR_TYPE_UCODE_RESET 6 +#define NV2080_CTRL_NOCAT_TDR_TYPE_TEST 7 + +typedef struct NV2080CtrlNocatJournalDataTdrReason { + NvU32 flags; + NvU8 source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; + NvU32 subsystem; + NV_DECLARE_ALIGNED(NvU64 errorCode, 8); + NvU32 reasonCode; +} NV2080CtrlNocatJournalDataTdrReason; + +#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR 0:0 +#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_YES 1 +#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_NO 0 +#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER 1:1 +#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_YES 1 +#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_NO 0 +typedef struct NV2080CtrlNocatJournalInsertRecord { + NvU32 flags; + NvU8 recType; + NvU32 bugcheck; + NvU8 source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; + NvU32 subsystem; + NV_DECLARE_ALIGNED(NvU64 errorCode, 8); + NvU8 faultingEngine[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; + NvU32 tdrReason; +} NV2080CtrlNocatJournalInsertRecord; + +#define NV2080_CTRL_NOCAT_TAG_CLEAR 0:0 +#define NV2080_CTRL_NOCAT_TAG_CLEAR_YES 1 +#define NV2080_CTRL_NOCAT_TAG_CLEAR_NO 0 +typedef struct NV2080CtrlNocatJournalSetTag { + NvU32 flags; + NvU8 tag[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; +} NV2080CtrlNocatJournalSetTag; + +#define NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS { + NvU32 dataType; + NvU32 targetRecordType; + union { + NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalDataTdrReason tdrReason, 8); + NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalInsertRecord insertData, 8); + NV2080CtrlNocatJournalSetTag tagData; + } nocatJournalData; +} NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS; +/* _ctr2080nvd_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h new file mode 100644 index 0000000..090f813 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h @@ -0,0 +1,2950 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080nvlink.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX bus control commands and parameters */ + +/* + * NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS + * + * This command returns the NVLink capabilities supported by the subdevice. + * + * capsTbl + * This is bit field for getting different global caps. The individual bitfields are specified by NV2080_CTRL_NVLINK_CAPS_* + * lowestNvlinkVersion + * This field specifies the lowest supported NVLink version for this subdevice. + * highestNvlinkVersion + * This field specifies the highest supported NVLink version for this subdevice. + * lowestNciVersion + * This field specifies the lowest supported NCI version for this subdevice. + * highestNciVersion + * This field specifies the highest supported NCI version for this subdevice. + * discoveredLinkMask + * This field provides a bitfield mask of NVLink links discovered on this subdevice. + * enabledLinkMask + * This field provides a bitfield mask of NVLink links enabled on this subdevice. + * + */ +#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS { + NvU32 capsTbl; + + NvU8 lowestNvlinkVersion; + NvU8 highestNvlinkVersion; + NvU8 lowestNciVersion; + NvU8 highestNciVersion; + + NvU32 discoveredLinkMask; + NvU32 enabledLinkMask; +} NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS; + +/* extract cap bit setting from tbl */ +#define NV2080_CTRL_NVLINK_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* + * NV2080_CTRL_NVLINK_CAPS + * + * SUPPORTED + * Set if NVLink is present and supported on this subdevice, NV_FALSE otherwise. This field is used for *global* caps only and NOT for per-link caps + * P2P_SUPPORTED + * Set if P2P over NVLink is supported on this subdevice, NV_FALSE otherwise. + * SYSMEM_ACCESS + * Set if sysmem can be accessed over NVLink on this subdevice, NV_FALSE otherwise. + * PEER_ATOMICS + * Set if P2P atomics are supported over NVLink on this subdevice, NV_FALSE otherwise. + * SYSMEM_ATOMICS + * Set if sysmem atomic transcations are supported over NVLink on this subdevice, NV_FALSE otherwise. + * PEX_TUNNELING + * Set if PEX tunneling over NVLink is supported on this subdevice, NV_FALSE otherwise. + * SLI_BRIDGE + * GLOBAL: Set if SLI over NVLink is supported on this subdevice, NV_FALSE otherwise. + * LINK: Set if SLI over NVLink is supported on a link, NV_FALSE otherwise. + * SLI_BRIDGE_SENSABLE + * GLOBAL: Set if the subdevice is capable of sensing SLI bridges, NV_FALSE otherwise. + * LINK: Set if the link is capable of sensing an SLI bridge, NV_FALSE otherwise. + * POWER_STATE_L0 + * Set if L0 is a supported power state on this subdevice/link, NV_FALSE otherwise. + * POWER_STATE_L1 + * Set if L1 is a supported power state on this subdevice/link, NV_FALSE otherwise. + * POWER_STATE_L2 + * Set if L2 is a supported power state on this subdevice/link, NV_FALSE otherwise. + * POWER_STATE_L3 + * Set if L3 is a supported power state on this subdevice/link, NV_FALSE otherwise. + * VALID + * Set if this link is supported on this subdevice, NV_FALSE otherwise. This field is used for *per-link* caps only and NOT for global caps. + * + */ + +/* caps format is byte_index:bit_mask */ +#define NV2080_CTRL_NVLINK_CAPS_SUPPORTED 0:0x01 +#define NV2080_CTRL_NVLINK_CAPS_P2P_SUPPORTED 0:0x02 +#define NV2080_CTRL_NVLINK_CAPS_SYSMEM_ACCESS 0:0x04 +#define NV2080_CTRL_NVLINK_CAPS_P2P_ATOMICS 0:0x08 +#define NV2080_CTRL_NVLINK_CAPS_SYSMEM_ATOMICS 0:0x10 +#define NV2080_CTRL_NVLINK_CAPS_PEX_TUNNELING 0:0x20 +#define NV2080_CTRL_NVLINK_CAPS_SLI_BRIDGE 0:0x40 +#define NV2080_CTRL_NVLINK_CAPS_SLI_BRIDGE_SENSABLE 0:0x80 +#define NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L0 1:0x01 +#define NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L1 1:0x02 +#define NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L2 1:0x04 +#define NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L3 1:0x08 +#define NV2080_CTRL_NVLINK_CAPS_VALID 1:0x10 + +/* + * Size in bytes of nvlink caps table. This value should be one greater + * than the largest byte_index value above. + */ +#define NV2080_CTRL_NVLINK_CAPS_TBL_SIZE 2U + +#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_INVALID (0x00000000U) +#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0 (0x00000001U) +#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0 (0x00000002U) +#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2 (0x00000004U) +#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0 (0x00000005U) +#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1 (0x00000006U) +#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0 (0x00000007U) + +#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID (0x00000000U) +#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0 (0x00000001U) +#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_0 (0x00000002U) +#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_2 (0x00000004U) +#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_0 (0x00000005U) +#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1 (0x00000006U) +#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0 (0x00000007U) + + +/* + * NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS (0x20803001U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_NVLINK_DEVICE_INFO + * + * This structure stores information about the device to which this link is associated + * + * deviceIdFlags + * Bitmask that specifies which IDs are valid for the device + * Refer NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_* for possible values + * If NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI is set, PCI information is valid + * If NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID is set, UUID is valid + * domain, bus, device, function, pciDeviceId + * PCI information for the device + * deviceType + * Type of the device + * See NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_* for possible values + * deviceUUID + * This field specifies the device UUID of the device. Useful for identifying the device (or version) + */ +typedef struct NV2080_CTRL_NVLINK_DEVICE_INFO { + // ID Flags + NvU32 deviceIdFlags; + + // PCI Information + NvU32 domain; + NvU16 bus; + NvU16 device; + NvU16 function; + NvU32 pciDeviceId; + + // Device Type + NV_DECLARE_ALIGNED(NvU64 deviceType, 8); + + // Device UUID + NvU8 deviceUUID[16]; +} NV2080_CTRL_NVLINK_DEVICE_INFO; + +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS 31:0 +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_NONE (0x00000000U) +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI (0x00000001U) +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID (0x00000002U) + +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_EBRIDGE (0x00000000U) +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU (0x00000001U) +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU (0x00000002U) +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH (0x00000003U) +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA (0x00000004U) +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE (0x000000FFU) + +#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_UUID_INVALID (0xFFFFFFFFU) + +/* + * NV2080_CTRL_NVLINK_NVLINK_LINK_STATUS_INFO + * + * This structure stores the per-link status of different NVLink parameters. + * + * capsTbl + * This is bit field for getting different global caps. The individual bitfields + * are specified by NV2080_CTRL_NVLINK_CAPS_* + * phyType + * This field specifies the type of PHY (NVHS or GRS) being used for this link. + * subLinkWidth + * This field specifies the no. of lanes per sublink. + * linkState + * This field specifies the current state of the link. + * See NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_LINK_STATE_* for possible values. + * rxSublinkStatus + * This field specifies the current state of RX sublink. + * See NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_SUBLINK_RX_STATE_* for possible values. + * txSublinkStatus + * This field specifies the current state of TX sublink. + * See NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_SUBLINK_TX_STATE_* for possible values. + * bLaneReversal + * This field indicates that lane reversal is in effect on this link. + * nvlinkVersion + * This field specifies the NVLink version supported by the link. + * nciVersion + * This field specifies the NCI version supported by the link. + * phyVersion + * This field specifies the version of PHY being used by the link. + * nvlinkLineRateMbps + * Bit rate at which bits toggle on wires in megabits per second. + * NOTE: This value is the full speed line rate, not the instantaneous line rate of the link. + * nvlinkLinkClockMhz + * Clock corresponding to link logic in mega hertz + * nvlinkRefClkType + * This field specifies whether the link clock is taken from NVHS reflck + * or PEX refclk for the current GPU. + * nvlinkLinkDataRateKiBps + * Effective rate available for transactions after subtracting overhead, + * as seen at Data Layer in kibibytes (1024 bytes) per second. + * Only valid in GA100+, reported as 0 otherwise + * NOTE: Because minion calculates these values, it will only be valid if + * links are in ACTIVE state + * nvlinkRefClkSpeedMhz + * The input reference frequency to the PLL + * connected + * This field specifies if any device is connected on the other end of the link + * loopProperty + * This field specifies if the link is a loopback/loopout link. See NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_* for possible values. + * remoteDeviceLinkNumber + * This field specifies the link number on the remote end of the link + * remoteDeviceInfo + * This field stores the device information for the remote end of the link + * + */ +typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO { + // Top level capablilites + NvU32 capsTbl; + + NvU8 phyType; + NvU8 subLinkWidth; + + // Link and sublink states + NvU32 linkState; + NvU8 rxSublinkStatus; + NvU8 txSublinkStatus; + + // Indicates that lane reversal is in effect on this link. + NvBool bLaneReversal; + + NvU8 nvlinkVersion; + NvU8 nciVersion; + NvU8 phyVersion; + + // Legacy clock information (to be deprecated) + NvU32 nvlinkLinkClockKHz; + NvU32 nvlinkCommonClockSpeedKHz; + NvU32 nvlinkRefClkSpeedKHz; + + NvU32 nvlinkCommonClockSpeedMhz; + + // Clock Speed and Data Rate Reporting + NvU32 nvlinkLineRateMbps; + NvU32 nvlinkLinkClockMhz; + NvU8 nvlinkRefClkType; + NvU32 nvlinkLinkDataRateKiBps; + NvU32 nvlinkRefClkSpeedMhz; + + // Connection information + NvBool connected; + NvU8 loopProperty; + NvU8 remoteDeviceLinkNumber; + NvU8 localDeviceLinkNumber; + + // + // Added as part of NvLink 3.0 + // Note: SID has link info appended to it when provided by minion + // + NV_DECLARE_ALIGNED(NvU64 remoteLinkSid, 8); + NV_DECLARE_ALIGNED(NvU64 localLinkSid, 8); + + // Ampere+ only + NvU32 laneRxdetStatusMask; + + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_DEVICE_INFO remoteDeviceInfo, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_DEVICE_INFO localDeviceInfo, 8); +} NV2080_CTRL_NVLINK_LINK_STATUS_INFO; + +// NVLink link states +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INIT (0x00000000U) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_HWCFG (0x00000001U) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SWCFG (0x00000002U) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_ACTIVE (0x00000003U) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_FAULT (0x00000004U) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SLEEP (0x00000005U) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY (0x00000006U) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_AC (0x00000008U) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_RX (0x0000000aU) +#define NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INVALID (0xFFFFFFFFU) + +// NVLink Rx sublink states +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_HIGH_SPEED_1 (0x00000000U) +// TODO: @achaudhry remove SINGLE_LANE define once references switch to LOW_POWER +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SINGLE_LANE (0x00000004) // Deprecated +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_LOW_POWER (0x00000004) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TRAINING (0x00000005U) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SAFE_MODE (0x00000006U) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_OFF (0x00000007U) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TEST (0x00000008U) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_FAULT (0x0000000eU) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_INVALID (0x000000FFU) + +// NVLink Tx sublink states +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_HIGH_SPEED_1 (0x00000000U) +// TODO: @achaudhry remove SINGLE_LANE define once references switch to LOW_POWER +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SINGLE_LANE (0x00000004) // Deprecated +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_LOW_POWER (0x00000004) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TRAINING (0x00000005U) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SAFE_MODE (0x00000006U) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_OFF (0x00000007U) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TEST (0x00000008U) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_FAULT (0x0000000eU) +#define NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_INVALID (0x000000FFU) + +#define NV2080_CTRL_NVLINK_STATUS_PHY_NVHS (0x00000001U) +#define NV2080_CTRL_NVLINK_STATUS_PHY_GRS (0x00000002U) +#define NV2080_CTRL_NVLINK_STATUS_PHY_INVALID (0x000000FFU) + +// Version information +#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_1_0 (0x00000001U) +#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_0 (0x00000002U) +#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_2 (0x00000004U) +#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_0 (0x00000005U) +#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_1 (0x00000006U) +#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_4_0 (0x00000007U) +#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID (0x000000FFU) + +#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_1_0 (0x00000001U) +#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_0 (0x00000002U) +#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_2 (0x00000004U) +#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_0 (0x00000005U) +#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_1 (0x00000006U) +#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_4_0 (0x00000007U) +#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_INVALID (0x000000FFU) + +#define NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_1_0 (0x00000001U) +#define NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_INVALID (0x000000FFU) + +#define NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_1_0 (0x00000001U) +#define NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_INVALID (0x000000FFU) + +// Connection properties +#define NV2080_CTRL_NVLINK_STATUS_CONNECTED_TRUE (0x00000001U) +#define NV2080_CTRL_NVLINK_STATUS_CONNECTED_FALSE (0x00000000U) + +#define NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPBACK (0x00000001U) +#define NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPOUT (0x00000002U) +#define NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_NONE (0x00000000U) + +#define NV2080_CTRL_NVLINK_STATUS_REMOTE_LINK_NUMBER_INVALID (0x000000FFU) + +#define NV2080_CTRL_NVLINK_MAX_LINKS 32 + +// NVLink REFCLK types +#define NV2080_CTRL_NVLINK_REFCLK_TYPE_INVALID (0x00U) +#define NV2080_CTRL_NVLINK_REFCLK_TYPE_NVHS (0x01U) +#define NV2080_CTRL_NVLINK_REFCLK_TYPE_PEX (0x02U) + +#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS { + NvU32 enabledLinkMask; + NvBool bSublinkStateInst; // whether instantaneous sublink state is needed + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_STATUS_INFO linkInfo[NV2080_CTRL_NVLINK_MAX_LINKS], 8); +} NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS + * + * enabledLinkMask + * This field specifies the mask of available links on this subdevice. + * linkInfo + * This structure stores the per-link status of different NVLink parameters. The link is identified using an index. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS (0x20803002U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_NVLINK_ERR_INFO + * Error information per link + * + * TLErrlog + * Returns the error mask for NVLINK TL errors + * Used in Pascal + * + * TLIntrEn + * Returns the intr enable mask for NVLINK TL errors + * Used in Pascal + * + * TLCTxErrStatus0 + * Returns the TLC Tx Error Mask 0 + * Used in Volta and later + * + * TLCTxErrStatus1 + * Returns the TLC Tx Error Mask 1 + * Used in Ampere and later + * + * TLCTxSysErrStatus0 + * Returns the TLC Tx Sys Error Mask 0 + * Used in Ampere and later. + * + * TLCRxErrStatus0 + * Returns the TLC Rx Error Mask 0 + * Used in Volta and later + * + * TLCRxErrStatus1 + * Returns the TLC Rx Error Mask 1 + * Used in Volta and later + * + * TLCRxSysErrStatus0 + * Returns the TLC Rx Sys Error Mask 0 + * Used in Ampere and later. + * + * TLCTxErrLogEn0 + * Returns the TLC Tx Error Log En 0 + * Used in Volta and later + * + * TLCTxErrLogEn1 + * Returns the TLC Tx Error Log En 1 + * Used in Ampere and later + * + * TLCTxSysErrLogEn0 + * Returns the TLC Tx Sys Error Log En 0 + * Used in Ampere and later + * + * TLCRxErrLogEn0 + * Returns the TLC Rx Error Log En 0 + * Used in Volta and later + * + * TLCRxErrLogEn1 + * Returns the TLC Rx Error Log En 1 + * Used in Volta and later + * + * TLCRxSysErrLogEn0 + * Returns the TLC Rx Sys Error Log En 0 + * Used in Ampere and later + * + * MIFTxErrStatus0 + * Returns the MIF Rx Error Mask 0 + * Used in Volta and Turing + * + * MIFRxErrStatus0 + * Returns the MIF Tx Error Mask 0 + * Used in Volta and Turing + * + * NVLIPTLnkErrStatus0 + * Returns the NVLIPT_LNK Error Mask 0 + * Used in Ampere and later + * + * NVLIPTLnkErrLogEn0 + * Returns the NVLIPT_LNK Log En Mask 0 + * Used in Ampere and later + * + * NVLIPTLnkCtrlLinkStateRequest + * Returns the NVLIPT_LNK Control Link State Request value + * Used in Ampere and later + * + * DLSpeedStatusTx + * Returns the NVLINK DL speed status for sublink Tx + * + * DLSpeedStatusRx + * Returns the NVLINK DL speed status for sublink Rx + * + * NVLDLRxSlsmErrCntl + * Returns the NVLDL_RXSLSM_ERR_CNTL value + * Used in Hopper and later + * + * NVLDLTopLinkState + * Returns the NVLDL_TOP_LINK_STATE value + * Used in Hopper and later + * + * NVLDLTopIntr + * Returns the NVLDL_TOP_INTR value + * Used in Hopper and later + * + * DLStatMN00 + * Returns the DLSTAT MN00 Code and subcode + * Used in Hopper and later + * + * DLStatUC01 + * Returns the DLSTAT UC01 value + * Used in Hopper and later + * + * MinionNvlinkLinkIntr + * Returns the MINION_NVLINK_LINK_INTR code and subcode + * Used in Hopper and later + * + * bExcessErrorDL + * Returns true for excessive error rate interrupt from DL + */ +typedef struct NV2080_CTRL_NVLINK_ERR_INFO { + NvU32 TLErrlog; + NvU32 TLIntrEn; + NvU32 TLCTxErrStatus0; + NvU32 TLCTxErrStatus1; + NvU32 TLCTxSysErrStatus0; + NvU32 TLCRxErrStatus0; + NvU32 TLCRxErrStatus1; + NvU32 TLCRxSysErrStatus0; + NvU32 TLCTxErrLogEn0; + NvU32 TLCTxErrLogEn1; + NvU32 TLCTxSysErrLogEn0; + NvU32 TLCRxErrLogEn0; + NvU32 TLCRxErrLogEn1; + NvU32 TLCRxSysErrLogEn0; + NvU32 MIFTxErrStatus0; + NvU32 MIFRxErrStatus0; + NvU32 NVLIPTLnkErrStatus0; + NvU32 NVLIPTLnkErrLogEn0; + NvU32 NVLIPTLnkCtrlLinkStateRequest; + NvU32 DLSpeedStatusTx; + NvU32 DLSpeedStatusRx; + NvU32 NVLDLRxSlsmErrCntl; + NvU32 NVLDLTopLinkState; + NvU32 NVLDLTopIntr; + NvU32 DLStatMN00; + NvU32 DLStatUC01; + NvU32 MinionNvlinkLinkIntr; + NvBool bExcessErrorDL; +} NV2080_CTRL_NVLINK_ERR_INFO; + +/* + * NV2080_CTRL_NVLINK_COMMON_ERR_INFO + * Error information per IOCTRL + * + * NVLIPTErrStatus0 + * Returns the NVLIPT_COMMON Error Mask 0 + * Used in Ampere and later + * + * NVLIPTErrLogEn0 + * Returns the NVLIPT_COMMON Log En Mask 0 + * Used in Ampere and later + */ +typedef struct NV2080_CTRL_NVLINK_COMMON_ERR_INFO { + NvU32 NVLIPTErrStatus0; + NvU32 NVLIPTErrLogEn0; +} NV2080_CTRL_NVLINK_COMMON_ERR_INFO; + +/* Extract the error status bit for a given TL error index i */ +#define NV2080_CTRL_NVLINK_GET_TL_ERRLOG_BIT(intr, i) (((1U << i) & (intr)) >> i) + +/* Extract the intr enable bit for a given TL error index i */ +#define NV2080_CTRL_NVLINK_GET_TL_INTEN_BIT(intr, i) NV2080_CTRL_NVLINK_GET_TL_ERRLOG_BIT(intr, i) + +/* Error status values for a given NVLINK TL error */ +#define NV2080_CTRL_NVLINK_TL_ERRLOG_TRUE (0x00000001U) +#define NV2080_CTRL_NVLINK_TL_ERRLOG_FALSE (0x00000000U) + +/* Intr enable/disable for a given NVLINK TL error */ +#define NV2080_CTRL_NVLINK_TL_INTEN_TRUE (0x00000001U) +#define NV2080_CTRL_NVLINK_TL_INTEN_FALSE (0x00000000U) + +/* NVLINK TL interrupt enable fields for errors */ +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLDATAPARITYEN 0U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLCTRLPARITYEN 1U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPROTOCOLEN 2U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXOVERFLOWEN 3U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMDATAPARITYEN 4U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMHDRPARITYEN 5U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRESPEN 6U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPOISONEN 7U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMDATAPARITYEN 8U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMHDRPARITYEN 9U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLFLOWPARITYEN 10U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLHDRPARITYEN 12U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXCREDITEN 13U +#define NV2080_CTRL_NVLINK_TL_INTEN_IDX_MAX 14U + +/* NVLINK TL error fields */ +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLDATAPARITYERR 0U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLCTRLPARITYERR 1U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPROTOCOLERR 2U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXOVERFLOWERR 3U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMDATAPARITYERR 4U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMHDRPARITYERR 5U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRESPERR 6U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPOISONERR 7U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMDATAPARITYERR 8U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMHDRPARITYERR 9U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLFLOWPARITYERR 10U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLHDRPARITYERR 12U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXCREDITERR 13U +#define NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_MAX 14U + +/* NVLINK DL speed status for sublink Tx*/ +#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_HS (0x00000000U) +#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SINGLE_LANE (0x00000004U) +#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_TRAIN (0x00000005U) +#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SAFE (0x00000006U) +#define NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_OFF (0x00000007U) + +/* NVLINK DL speed status for sublink Rx*/ +#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_HS (0x00000000U) +#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SINGLE_LANE (0x00000004U) +#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_TRAIN (0x00000005U) +#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SAFE (0x00000006U) +#define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_OFF (0x00000007U) + +/* Flags to query different debug registers */ +#define NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_DEFAULT (0x0U) +#define NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_INTR_STATUS (0x1U) +#define NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_ALI_STATUS (0x2U) + +#define NV2080_CTRL_NVLINK_MAX_IOCTRLS 3U +/* + * NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS + * + * linkMask + * Returns the mask of links enabled + * + * linkErrInfo + * Returns the error information for all the links + * + * ioctrlMask + * Returns the mask of ioctrls + * + * commonErrInfo + * Returns the error information common to each IOCTRL + * + * ErrInfoFlags + * Input for determining which values to query. Possible values: + * NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_INTR_STATUS + * NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_ALI_STATUS + * + */ +#define NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS { + NvU32 linkMask; + NV2080_CTRL_NVLINK_ERR_INFO linkErrInfo[NV2080_CTRL_NVLINK_MAX_LINKS]; + NvU32 ioctrlMask; + NV2080_CTRL_NVLINK_COMMON_ERR_INFO commonErrInfo[NV2080_CTRL_NVLINK_MAX_IOCTRLS]; + NvU8 ErrInfoFlags; +} NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_ERR_INFO + * This command is used to query the NVLINK error information + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_NVLINK_GET_ERR_INFO (0x20803003U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS_MESSAGE_ID" */ + +/* + * APIs for getting NVLink counters + */ + +// These are the bitmask definitions for different counter types + +#define NV2080_CTRL_NVLINK_COUNTER_INVALID 0x00000000U + +#define NV2080_CTRL_NVLINK_COUNTER_TL_TX0 0x00000001U +#define NV2080_CTRL_NVLINK_COUNTER_TL_TX1 0x00000002U +#define NV2080_CTRL_NVLINK_COUNTER_TL_RX0 0x00000004U +#define NV2080_CTRL_NVLINK_COUNTER_TL_RX1 0x00000008U + +#define NV2080_CTRL_NVLINK_LP_COUNTERS_DL 0x00000010U + +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L(i) (1 << (i + 8)) +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE__SIZE 4U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L0 0x00000100U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L1 0x00000200U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L2 0x00000400U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L3 0x00000800U + +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT 0x00010000U + +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L(i) (1 << (i + 17)) +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE__SIZE 8U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0 0x00020000U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1 0x00040000U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2 0x00080000U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3 0x00100000U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4 0x00200000U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5 0x00400000U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6 0x00800000U +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7 0x01000000U + +#define NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_REPLAY 0x02000000U +#define NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_RECOVERY 0x04000000U + +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_REPLAY 0x08000000U + +#define NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_MASKED 0x10000000U + +/* + * Note that COUNTER_MAX_TYPES will need to be updated each time + * a new counter type gets added to the list above. + * + */ +#define NV2080_CTRL_NVLINK_COUNTER_MAX_TYPES 32U + +/* + * NV2080_CTRL_CMD_NVLINK_GET_COUNTERS + * This command gets the counts for different counter types. + * + * [in] counterMask + * Mask of counter types to be queried + * One of NV2080_CTRL_NVLINK_COUNTERS_TYPE_* macros + * + * [in] linkMask + * Mask of links to be queried + * + * [out] counters + * Counter value returned + * + * [out] bTx0TlCounterOverflow + * This boolean is set to NV_TRUE if TX Counter 0 has rolled over. + * + * [out] bTx1TlCounterOverflow + * This boolean is set to NV_TRUE if TX Counter 1 has rolled over. + * + * [out] bRx0TlCounterOverflow + * This boolean is set to NV_TRUE if RX Counter 0 has rolled over. + * + * [out] bRx1TlCounterOverflow + * This boolean is set to NV_TRUE if RX Counter 1 has rolled over. + * + * [out] value + * This array contains the error counts for each error type as requested from + * the counterMask. The array indexes correspond to the mask bits one-to-one. + */ +typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES { + NvBool bTx0TlCounterOverflow; + NvBool bTx1TlCounterOverflow; + NvBool bRx0TlCounterOverflow; + NvBool bRx1TlCounterOverflow; + NV_DECLARE_ALIGNED(NvU64 value[NV2080_CTRL_NVLINK_COUNTER_MAX_TYPES], 8); +} NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES; + +#define NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS { + NvU32 counterMask; + NV_DECLARE_ALIGNED(NvU64 linkMask, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES counters[NV2080_CTRL_NVLINK_MAX_LINKS], 8); +} NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_COUNTERS (0x20803004U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS_MESSAGE_ID" */ + + +/* + * NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS + * This command clears/resets the counters for the specified types. + * + * [in] linkMask + * This parameter specifies for which links we want to clear the + * counters. + * + * [in] counterMask + * This parameter specifies the input mask for desired counters to be + * cleared. Note that all counters cannot be cleared. + * + * NOTE: Bug# 2098529: On Turing all DL errors and LP counters are cleared + * together. They cannot be cleared individually per error type. RM + * would possibly move to a new API on Ampere and beyond + */ + +#define NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS (0x20803005U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS { + NvU32 counterMask; + NV_DECLARE_ALIGNED(NvU64 linkMask, 8); +} NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_INJECT_ERROR + * This command causes all the same actions to occur as if the related + * error were to occur, either fatal or recoverable. + * + * [in] linkMask size: 32 bits + * Controls which links to apply error injection to. + * [in] bFatal + * This parameter specifies that the error should be fatal. + * + */ +#define NV2080_CTRL_CMD_NVLINK_INJECT_ERROR (0x20803006U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS { + NvU32 linkMask; + NvBool bFatalError; +} NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS; + +/* NVLINK unit list - to be used with error notifiers */ +#define NV2080_CTRL_NVLINK_UNIT_DL 0x01U +#define NV2080_CTRL_NVLINK_UNIT_TL 0x02U +#define NV2080_CTRL_NVLINK_UNIT_TLC_RX_0 0x03U +#define NV2080_CTRL_NVLINK_UNIT_TLC_RX_1 0x04U +#define NV2080_CTRL_NVLINK_UNIT_TLC_TX_0 0x05U +#define NV2080_CTRL_NVLINK_UNIT_MIF_RX_0 0x06U +#define NV2080_CTRL_NVLINK_UNIT_MIF_TX_0 0x07U + +/* + * NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES + * This command gets the number of successful error recoveries + * + * [in] linkMask size: 32 bits + * This parameter controls which links to get recoveries for. + * [out] numRecoveries + * This parameter specifies the number of successful per link error recoveries + */ +#define NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES (0x20803007U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS { + NvU32 linkMask; + NvU32 numRecoveries[NV2080_CTRL_NVLINK_MAX_LINKS]; +} NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE + * + * This command queries the remote endpoint type of the link recorded at the + * time the last error occurred on the link. + * + * [in] linkId + * This parameter specifies the link to get the last remote endpoint type + * recorded for. + * + * [out] remoteType + * This parameter returns the remote endpoint type of the link recorded at + * the time the last error occurred on the link. Possible values are: + * NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE + * The link is not connected to an active remote endpoint. + * NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU + * The remote endpoint of the link is a peer GPU. + * NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU + * The remote endpoint of the link is the host system (e.g., an NPU + * on IBM POWER platforms). + * NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA + * The remote endpoint of the link a tegra device + * + * Possible return status values are: + * NV_OK + * If the remoteType parameter value is valid upon return. + * NV_ERR_INVALID_ARGUMENT + * If the linkId parameter does not specify a valid link. + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on this GPU or the remote endpoint type is + * not recorded in non-volatile storage. + */ +#define NV2080_CTRL_CMD_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE (0x20803008U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS { + NvU32 linkId; + NvU32 remoteType; +} NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_LINK_FATAL_ERROR_COUNTS + * + * This command queries the number of each type of fatal errors that have + * occurred on the given link. + * + * [in] linkId + * This parameter specifies the link to get the fatal error information + * for. + * + * [out] supportedCounts + * This parameter identifies which counts in the fatalErrorCounts array + * are valid for the given link. A bit set in this field means that the + * corresponding index is valid in the fatalErrorCounts array. + * + * [out] fatalErrorCounts + * This parameter returns an array of 8-bit counts, one for each type of + * fatal error that can occur on the link. The valid indices of this array + * are: + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_RX_DL_DATA_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_RX_DL_CTRL_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_PROTOCOL + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_OVERFLOW + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_RX_RAM_DATA_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_RX_RAM_HDR_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RESP + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_POISON + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_POISONED_PKT_RCVD + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_TX_RAM_DATA_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL(C)_TX_RAM_HDR_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_CREDIT + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_FLOW_CTRL_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_FLOW_CTRL_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_HDR_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_RECOVERY_LONG + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_RAM + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_INTERFACE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_DL_PROTOCOL + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_HDR_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_AE_FLIT_RCVD + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_BE_FLIT_RCVD + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_ADDR_ALIGN + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_PKT_LEN + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CMD_ENC + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_DAT_LEN_ENC + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_ADDR_TYPE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_RSP_STATUS + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_PKT_STATUS + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_PO_FOR_CACHE_ATTR + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COMPRESSED_RESP + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_TARGET + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_HDR_OVERFLOW + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_OVERFLOW + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_STOMPED_PKT_RCVD + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_CORRECTABLE_INTERNAL + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_VC_OVERFLOW + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_HDR_CREDIT_OVERFLOW + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_CREDIT_OVERFLOW + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_REPLAY_CREDIT_OVERFLOW + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_UNSUPPORTED_VC_OVERFLOW + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_STOMPED_PKT_SENT + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_POISONED_PKT_SENT + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_TARGET + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_DATA_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_HDR_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_DATA_PARITY + * NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_HDR_PARITY + * + * Possible return status values are: + * NV_OK + * If the values in the fatalErrorCounts array are valid upon return. + * NV_ERR_INVALID_ARGUMENT + * If the linkId parameter does not specify a valid link. + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on this GPU or aggregate NVLINK fatal error + * counts are not recorded in non-volatile storage. + */ +#define NV2080_CTRL_CMD_NVLINK_GET_LINK_FATAL_ERROR_COUNTS (0x20803009U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS_MESSAGE_ID" */ + +/* + * NVLink 1 Fatal Error Types + */ +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_DATA_PARITY 0U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_CTRL_PARITY 1U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_PROTOCOL 2U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_OVERFLOW 3U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_DATA_PARITY 4U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_HDR_PARITY 5U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RESP 6U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_POISON 7U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_DATA_PARITY 8U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_HDR_PARITY 9U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_CREDIT 10U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_FLOW_CTRL_PARITY 11U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_HDR_PARITY 12U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_RECOVERY_LONG 13U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_RAM 14U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_INTERFACE 15U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE 16U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE 17U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_DL_PROTOCOL 18U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT 19U + +/* + * NVLink 2 Fatal Error Types + */ +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_DATA_PARITY 0U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_CTRL_PARITY 1U +// No direct equivalent to: TL_RX_PROTOCOL 2 +// No direct equivalent to: TL_RX_OVERFLOW 3 +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_DATA_PARITY 4U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_HDR_PARITY 5U +// No direct equivalent to: TL_RX_RESP 6 +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_POISONED_PKT_RCVD 7U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_DATA_PARITY 8U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_HDR_PARITY 9U +// No direct equivalent to: TL_TX_CREDIT 10 +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_FLOW_CONTROL_PARITY 11U +// No direct equivalent to: TL_DL_HDR_PARITY 12 +// Identical to NVLink 1: DL_TX_RECOVERY_LONG 13 +// Identical to NVLink 1: DL_TX_FAULT_RAM 14 +// Identical to NVLink 1: DL_TX_FAULT_INTERFACE 15 +// Identical to NVLink 1: DL_TX_FAULT_SUBLINK_CHANGE 16 +// Identical to NVLink 1: DL_RX_FAULT_SUBLINK_CHANGE 17 +// Identical to NVLink 1: DL_RX_FAULT_DL_PROTOCOL 18 +// Identical to NVLink 1: DL_LTSSM_FAULT 19 +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_HDR_PARITY 20U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_AE_FLIT_RCVD 21U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_BE_FLIT_RCVD 22U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_ADDR_ALIGN 23U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_PKT_LEN 24U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CMD_ENC 25U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_DAT_LEN_ENC 26U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_ADDR_TYPE 27U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_RSP_STATUS 28U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_PKT_STATUS 29U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ 30U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP 31U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE 32U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE 33U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE 34U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_PO_FOR_CACHE_ATTR 35U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COMPRESSED_RESP 36U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_TARGET 37U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST 38U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_HDR_OVERFLOW 39U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_OVERFLOW 40U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_STOMPED_PKT_RCVD 41U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_CORRECTABLE_INTERNAL 42U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_VC_OVERFLOW 43U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE 44U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE 45U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_HDR_CREDIT_OVERFLOW 46U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_CREDIT_OVERFLOW 47U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_REPLAY_CREDIT_OVERFLOW 48U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_UNSUPPORTED_VC_OVERFLOW 49U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_STOMPED_PKT_SENT 50U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_POISONED_PKT_SENT 51U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_TARGET 52U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST 53U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_DATA_PARITY 54U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_HDR_PARITY 55U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_DATA_PARITY 56U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_HDR_PARITY 57U + +/* + * NVLink 3 Fatal Error Types + */ +// Identical to NVLink 2: TLC_RX_DL_DATA_PARITY 0 +// Identical to NVLink 2: TLC_RX_DL_CTRL_PARITY 1 +// No direct equivalent to: TL_RX_PROTOCOL 2 +// No direct equivalent to: TL_RX_OVERFLOW 3 +// No direct equivalent to: TLC_RX_RAM_DATA_PARITY 4 +// No direct equivalent to: RX_RAM_HDR_PARITY 5 +// No direct equivalent to: TL_RX_RESP 6 +// No direct equivalent to: TLC_RX_DATA_POISONED_PKT_RCVD 7 +// No direct equivalent to: TLC_TX_RAM_DATA_PARITY 8 +// No direct equivalent to: TLC_TX_RAM_HDR_PARITY 9 +// No direct equivalent to: TL_TX_CREDIT 10 +// Identical to NVLink 2: TLC_TX_DL_FLOW_CONTROL_PARITY 11 +// No direct equivalent to: TL_DL_HDR_PARITY 12 +// No direct equivalent to: DL_TX_RECOVERY_LONG 13 +// Identical to NVLink 1: DL_TX_FAULT_RAM 14 +// Identical to NVLink 1: DL_TX_FAULT_INTERFACE 15 +// Identical to NVLink 1: DL_TX_FAULT_SUBLINK_CHANGE 16 +// Identical to NVLink 1: DL_RX_FAULT_SUBLINK_CHANGE 17 +// Identical to NVLink 1: DL_RX_FAULT_DL_PROTOCOL 18 +// No direct equivalent to: DL_LTSSM_FAULT 19 +// Identical to NVLink 2: TLC_RX_DL_HDR_PARITY 20 +// Identical to NVLink 2: TLC_RX_INVALID_AE_FLIT_RCVD 21 +// Identical to NVLink 2: TLC_RX_INVALID_BE_FLIT_RCVD 22 +// Identical to NVLink 2: TLC_RX_INVALID_ADDR_ALIGN 23 +// Identical to NVLink 2: TLC_RX_PKT_LEN 24 +// Identical to NVLink 2: TLC_RX_RSVD_CMD_ENC 25 +// Identical to NVLink 2: TLC_RX_RSVD_DAT_LEN_ENC 26 +// No direct equivalent to: TLC_RX_RSVD_ADDR_TYPE 27 +// No direct equivalent to: TLC_RX_RSVD_RSP_STATUS 28 +// Identical to NVLink 2: TLC_RX_RSVD_PKT_STATUS 29 +// Identical to NVLink 2: TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ 30 +// Identical to NVLink 2: TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP 31 +// No direct equivalent to: TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE 32 +// Identical to NVLink 2: TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE 33 +// Identical to NVLink 2: TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE 34 +// Identical to NVLink 2: TLC_RX_INVALID_PO_FOR_CACHE_ATTR 35 +// Identical to NVLink 2: TLC_RX_INVALID_COMPRESSED_RESP 36 +// No direct equivalent to: TLC_RX_RESP_STATUS_TARGET 37 +// No direct equivalent to: TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST 38 +// Identical to NVLink 2: TLC_RX_HDR_OVERFLOW 39 +// Identical to NVLink 2: TLC_RX_DATA_OVERFLOW 40 +// Identical to NVLink 2: TLC_RX_STOMPED_PKT_RCVD 41 +// No direct equivalent to: TLC_RX_CORRECTABLE_INTERNAL 42 +// No direct equivalent to: TLC_RX_UNSUPPORTED_VC_OVERFLOW 43 +// No direct equivalent to: TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE 44 +// No direct equivalent to: TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE 45 +// No direct equivalent to: TLC_TX_HDR_CREDIT_OVERFLOW 46 +// No direct equivalent to: TLC_TX_DATA_CREDIT_OVERFLOW 47 +// No direct equivalent to: TLC_TX_DL_REPLAY_CREDIT_OVERFLOW 48 +// No direct equivalent to: TLC_TX_UNSUPPORTED_VC_OVERFLOW 49 +// No direct equivalent to: TLC_TX_STOMPED_PKT_SENT 50 +// No direct equivalent to: TLC_TX_DATA_POISONED_PKT_SENT 51 +// No direct equivalent to: TLC_TX_RESP_STATUS_TARGET 52 +// No direct equivalent to: TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST 53 +// No direct equivalent to: MIF_RX_RAM_DATA_PARITY 54 +// No direct equivalent to: MIF_RX_RAM_HDR_PARITY 55 +// No direct equivalent to: MIF_TX_RAM_DATA_PARITY 56 +// No direct equivalent to: MIF_TX_RAM_HDR_PARITY 57 +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COLLAPSED_RESPONSE 58U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_HDR_ECC_DBE 59U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_PARITY 60U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_UP 61U +#define NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_DOWN 62U + +#define NV2080_CTRL_NVLINK_NUM_FATAL_ERROR_TYPES 63U + +#define NV2080_CTRL_NVLINK_IS_FATAL_ERROR_COUNT_VALID(count, supportedCounts) \ + (!!((supportedCounts) & NVBIT64(count))) + +#define NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS { + NvU32 linkId; + NV_DECLARE_ALIGNED(NvU64 supportedCounts, 8); + NvU8 fatalErrorCounts[NV2080_CTRL_NVLINK_NUM_FATAL_ERROR_TYPES]; +} NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_LINK_NONFATAL_ERROR_RATES + * + * This command queries recent non-fatal error rates for the given link. + * + * The error rates specify the maximum number of errors per minute recorded + * for the given link within a 24-hour period for daily maximums or a 30-day + * period for monthly maximums. + * + * [in] linkId + * This parameter specifies the link to get the nonfatal error information + * for. + * + * [out] numDailyMaxNonfatalErrorRates + * This parameter returns the number of valid nonfatal error rate entries + * in the dailyMaxNonfatalErrorRates parameter. + * + * [out] dailyMaxNonfatalErrorRates + * This parameter returns maximum nonfatal error rate entries recorded + * over the last few 24-hour periods. For example, index 0 contains the + * maximum nonfatal error rate recorded in the current day, index 1 + * contains the maximum nonfatal error rate recorded yesterday ago, etc. + * + * [out] numMonthlyMaxNonfatalErrorRates + * This parameter returns the number of valid nonfatal error rate entries + * in the monthlyMaxNonfatalErrorRates parameter. + * + * [out] monthlyMaxNonfatalErrorRates + * THis parameter returns maximum nonfatal error rate entries recorded + * over the last few 30-day periods. For example, index 0 contains the + * maximum nonfatal error rate recorded in the current month, index 1 + * contains the maximum nonfatal error recorded last month, etc. + * + * Possible status values returned are: + * NV_OK + * If any nonfatal error rates are valid upon return. + * NV_ERR_INVALID_ARGUMENT + * If the linkId parameter does not specify a valid link. + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on this GPU or NVLINK nonfatal error rates + * are not recorded in non-volatile storage. + */ +#define NV2080_CTRL_CMD_NVLINK_GET_LINK_NONFATAL_ERROR_RATES (0x2080300aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS_MESSAGE_ID" */ + +typedef struct NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE { + NvU32 errorsPerMinute; + NvU32 timestamp; +} NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE; + +#define NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE_ENTRIES 5U + +#define NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS { + NvU32 linkId; + NvU32 numDailyMaxNonfatalErrorRates; + NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE dailyMaxNonfatalErrorRates[NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE_ENTRIES]; + NvU32 numMonthlyMaxNonfatalErrorRates; + NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE monthlyMaxNonfatalErrorRates[NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE_ENTRIES]; +} NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_SET_ERROR_INJECTION_MODE + * + * This command sets the injection mode so that error handling and error + * logging software can be aware that errors cropping up on links are + * intentional and not due to HW failures. + * + * [in] bEnabled + * This parameter specifies whether injection mode should be enabled or + * disabled. + * + * Possible status values returned are: + * NV_OK + * If injection mode is enabled or disabled according to the parameters. + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on this GPU. + */ +#define NV2080_CTRL_CMD_NVLINK_SET_ERROR_INJECTION_MODE (0x2080300bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS { + NvBool bEnabled; +} NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_SETUP_EOM + * + * This command passes a packed 32bit params value to NV_PMINION_MISC_0_SCRATCH_SWRW_0 + * and then issues an EOM DLCMD to minion for the desired link. Only one DLCMD + * at a time can be issued to any given link. + * + * Params Packing is specified in Minion IAS + */ +#define NV2080_CTRL_CMD_NVLINK_SETUP_EOM (0x2080300cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS { + NvU8 linkId; + NvU32 params; +} NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_SET_POWER_STATE + * + * This command sets the mask of links associated with the GPU + * to a target power state + * + * [in] linkMask + * Mask of links that will be put to desired power state + * Note: In Turing RM supports only tansitions into/out of L2 + * [in] powerState + * Target power state to which the links will transition + * This can be any one of NV2080_CTRL_NVLINK_POWER_STATE_* states + * + * Possible status values returned are: + * NV_OK + * If all links transitioned successfully to the target state + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip or if the power state + * is not enabled on the chip + * NV_ERR_INVALID_ARGUMENT + * If the any of the links in the mask is not enabled + * NV_ERR_INVALID_REQUEST + * If the power state transition is not supported + * NV_WARN_MORE_PROCESSING_REQUIRED + * Link has received the request for the power transition + * The transition will happen when the remote end also agrees + * + * Note: Currently only L0->L2 and L2->L0 is supported + */ +#define NV2080_CTRL_CMD_NVLINK_SET_POWER_STATE (0x2080300dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS { + NvU32 linkMask; + NvU32 powerState; +} NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS; + +// NVLink Power States +#define NV2080_CTRL_NVLINK_POWER_STATE_L0 (0x00U) +#define NV2080_CTRL_NVLINK_POWER_STATE_L1 (0x01U) +#define NV2080_CTRL_NVLINK_POWER_STATE_L2 (0x02U) +#define NV2080_CTRL_NVLINK_POWER_STATE_L3 (0x03U) + +/* + * NV2080_CTRL_CMD_NVLINK_GET_POWER_STATE + * + * This command gets the power state of a link associated + * with the GPU + * + * [in] linkId + * Link whose power state is being requested + * [out] powerState + * Current power state of the link + * Is any one the NV2080_CTRL_NVLINK_POWER_STATE_* states + * + * Possible status values returned are: + * NV_OK + * If the power state is retrieved successfully + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip + * NV_ERR_INVALID_ARGUMENT + * If the link is not enabled on the GPU + * NV_ERR_INVALID_STATE + * If the link is in an invalid state + */ +#define NV2080_CTRL_CMD_NVLINK_GET_POWER_STATE (0x2080300eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS { + NvU32 linkId; + NvU32 powerState; +} NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_INJECT_TLC_ERROR + * + * This command injects TLC_*_REPORT_INJECT error. An RM interrupt + * will be triggered after injection. Currently the injection call + * only deals with HW_ERR, UR_ERR, PRIV_ERR in TX_SYS and RX_LNK devices + * + * [in] linkId + * Link whose power state is being requested. + * [in] errorType + * error type that needs to be injected. + * [in] device + * The device this injection is intended for. + * [in] bBroadcast + * Whether the link report error should be fired in multiple links. + + * Possible status values returned are: + * NV_OK + * If the injection succeeds. + * NV_ERR_NOT_SUPPORTED + * If the error type of NVLINK is not supported on the chip + */ +#define NV2080_CTRL_CMD_NVLINK_INJECT_TLC_ERROR (0x2080300fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE { + TLC_RX_LNK = 0, + TLC_TX_SYS = 1, +} NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE; + +typedef enum NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE { + TX_SYS_TX_RSP_STATUS_HW_ERR = 0, + TX_SYS_TX_RSP_STATUS_UR_ERR = 1, + TX_SYS_TX_RSP_STATUS_PRIV_ERR = 2, +} NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE; + +typedef enum NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE { + RX_LNK_RX_RSP_STATUS_HW_ERR = 0, + RX_LNK_RX_RSP_STATUS_UR_ERR = 1, + RX_LNK_RX_RSP_STATUS_PRIV_ERR = 2, +} NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE; + +typedef union NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE { + NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE txSysErrorType; + NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE rxLnkErrorType; +} NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE; + + +#define NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS { + NvU32 linkId; + NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE device; + NvBool bBroadcast; + NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE errorType; +} NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS; + + + +/* + * NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES + * + * This command returns the per-lane Figure Of Merit (FOM) Values from a link + * + * [in] linkId + * The NVLink link ID to report FOM values for + * [out] numLanes + * This field specifies the no. of lanes per link + * [out] figureOfMeritValues + * This field contains the FOM values per lane + * + */ +#define NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES (0x20803011U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_MAX_LANES 4U + +#define NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS { + NvU32 linkId; + NvU8 numLanes; + NvU16 figureOfMeritValues[NV2080_CTRL_NVLINK_MAX_LANES]; +} NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS; + +/* + * NV2080_CTRL_NVLINK_SET_NVLINK_PEER + * + * This command sets/unsets the USE_NVLINK_PEER bit for a given + * mask of peers + * + * [in] peerMask + * Mask of Peer IDs for which USE_NVLINK_PEER needs to be updated + * [in] bEnable + * Whether the bit needs to be set or unset + * + * Possible status values returned are: + * NV_OK + * If the USE_NVLINK_PEER bit was updated successfully + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip, or + * If unsetting USE_NVLINK_PEER bit is not supported + * + * NOTE: This is only supported on Windows + * + */ +#define NV2080_CTRL_CMD_NVLINK_SET_NVLINK_PEER (0x20803012U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS { + NvU32 peerMask; + NvBool bEnable; +} NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_READ_UPHY_PAD_LANE_REG + * + * This command packs the lane and addr values into NV_PMINION_MISC_0_SCRATCH_SWRW_0 + * and then issues a READPADLANEREG DLCMD to minion for the desired link. Only one DLCMD + * at a time can be issued to any given link. + * + * After this command completes it is necessary to read the appropriate + * NV_PNVL_BR0_PAD_CTL_7_CFG_RDATA register to retrieve the results of the read + * Only GV100 should read NV_PNVL_BR0_PAD_CTL_7_CFG_RDATA. + * From TU102+ the ctrl the required data would be updated in phyConfigData. + * + * [in] linkId + * Link whose pad lane register is being read + * [in] lane + * Lane whose pad lane register is being read + * [in] addr + * Address of the pad lane register to read + * [out] phyConfigData + * Provides phyconfigaddr and landid + * + * Possible status values returned are: + * NV_OK + * If the minion command completed successfully + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip + * NV_ERR_INVALID_ARGUMENT + * If the link is not enabled on the GPU or the lane is invalid + * NV_ERR_TIMEOUT + * If a timeout occurred waiting for minion response + */ +#define NV2080_CTRL_CMD_NVLINK_READ_UPHY_PAD_LANE_REG (0x20803013U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS { + NvU8 linkId; + NvU8 lane; + NvU16 addr; + NvU32 phyConfigData; +} NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS; + +/* + * Structure to store the ECC error data. + * valid + * Is the lane valid or not + * eccErrorValue + * Value of the Error. + * overflowed + * If the error overflowed or not + */ +typedef struct NV2080_CTRL_NVLINK_LANE_ERROR { + NvBool bValid; + NvU32 eccErrorValue; + NvBool overflowed; +} NV2080_CTRL_NVLINK_LANE_ERROR; + +/* + * Structure to store ECC error data for Links + * errorLane array index corresponds to the lane number. + * + * errorLane[] + * Stores the ECC error data per lane. + */ +typedef struct NV2080_CTRL_NVLINK_LINK_ECC_ERROR { + NV2080_CTRL_NVLINK_LANE_ERROR errorLane[NV2080_CTRL_NVLINK_MAX_LANES]; + NvU32 eccDecFailed; + NvBool eccDecFailedOverflowed; +} NV2080_CTRL_NVLINK_LINK_ECC_ERROR; + +/* + * NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS + * + * Control to get the values of ECC ERRORS + * + * Parameters: + * linkMask [IN] + * Links on which the ECC error data requested + * A valid link/port mask returned by the port masks returned by + * NVSWITCH_GET_INFO + * errorLink[] [OUT] + * Stores the ECC error related information for each link. + * errorLink array index corresponds to the link Number. + */ + +#define NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS { + NvU32 linkMask; + NV2080_CTRL_NVLINK_LINK_ECC_ERROR errorLink[NV2080_CTRL_NVLINK_MAX_LINKS]; +} NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS; + + +#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_ECC_ERRORS (0x20803014U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS_MESSAGE_ID" */ + +// Nvlink throughput counters reading data flits in TX +#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_TX 0U + +// Nvlink throughput counters reading data flits in RX +#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_RX 1U + +// Nvlink throughput counters reading all flits in TX +#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_TX 2U + +// Nvlink throughput counters reading all flits in RX +#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_RX 3U + +#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_MAX 4U + +/* + * NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS + * + * Reads reserved monotonically increasing NVLINK throughput counters for given linkIds + * + * [in] counterMask + * Mask of counter types to be queried + * One of NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_* macros + * [in] linkMask + * Mask of links to be queried + * [out] value + * Throughput counter value returned + * + * Possible status values returned are: + * NV_OK + * If command completed successfully + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip + * NV_ERR_INVALID_ARGUMENT + * If numLinks is out-of-range or requested link is inactive + * + * Note: + * The following commands will be deprecated in favor of NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS: + * NV90CC_CTRL_CMD_NVLINK_GET_COUNTERS + * NV2080_CTRL_CMD_NVLINK_GET_COUNTERS + * Other commands that will be deprecated due to the change in design: + * NV90CC_CTRL_CMD_NVLINK_RESERVE_COUNTERS + * NV90CC_CTRL_CMD_NVLINK_RELEASE_COUNTERS + * NV90CC_CTRL_CMD_NVLINK_SET_COUNTERS_FROZEN + * NV90CC_CTRL_CMD_NVLINK_GET_TL_COUNTER_CFG + * NV90CC_CTRL_CMD_NVLINK_SET_TL_COUNTER_CFG + * NV90CC_CTRL_CMD_NVLINK_CLEAR_COUNTERS + * + * Also, note that there is no counter overflow handling for these calls. + * These counters would be counting in flits and assuming 25GB/s bandwidth per link, + * with traffic flowing continuously, it would take 174 years for overflow to happen. + * It is reasonable to assume an overflow will not occur within the GPU operation, + * given that the counters get reset at system reboot or GPU reset. Counters are 63-bit. + */ + +typedef struct NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES { + NV_DECLARE_ALIGNED(NvU64 value[NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_MAX], 8); +} NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES; + +#define NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS { + NvU16 counterMask; + NV_DECLARE_ALIGNED(NvU64 linkMask, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES counters[NV2080_CTRL_NVLINK_MAX_LINKS], 8); +} NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS (0x20803015U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE + * + * This command locks the link power state so that RM doesn't modify the state + * of the link during pstate switch. + * + * [in] linkMask Links for which power mode needs to be locked. + */ +#define NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE (0x20803016U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS { + NvBool bLockPowerMode; +} NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS; + +/* + * NV2080_CTRL_CMD_NVLINK_ENABLE_NVLINK_PEER + * + * This command is used to enable RM NVLink enabled peer state. + * Note: This just updates the RM state. To reflect the state in the registers, + * use NV2080_CTRL_CMD_NVLINK_SET_NVLINK_PEER + * + * [in] peerMask + * Mask of Peer IDs for which USE_NVLINK_PEER needs to be enabled + * [in] bEnable + * Whether the bit needs to be set or unset + * + * Possible status values returned are: + * NV_OK + * If the USE_NVLINK_PEER bit was enabled successfully + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip, or + * If unsetting USE_NVLINK_PEER bit is not supported + * + */ +#define NV2080_CTRL_CMD_NVLINK_ENABLE_NVLINK_PEER (0x20803017U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID (0x17U) + +typedef struct NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS { + NvU32 peerMask; + NvBool bEnable; +} NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS; + +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_NVHS 0U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_EIGHTH 1U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_OTHER 2U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_ENTER 3U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_EXIT 4U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_SLEEP 5U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS 6U + +/* + * NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS + * + * Reads NVLINK low power counters for given linkId + * + * [in] linkId + * ID of the link to be queried + * [in,out] counterValidMask + * Mask of valid counters + * [out] counterValues + * Low power counter values returned + * + * Possible status values returned are: + * NV_OK + * If command completed successfully + * NV_ERR_NOT_SUPPORTED + * If NVLINK is not supported on the chip + * NV_ERR_INVALID_ARGUMENT + * If linkId is out-of-range or requested link is inactive + */ + +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS { + NvU32 linkId; + NvU32 counterValidMask; + NvU32 counterValues[NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS]; +} NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS (0x20803018U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID" */ + +/* + * NVLINK Link states + * These should ALWAYS match the nvlink core library defines in nvlink.h + */ +#define NV2080_NVLINK_CORE_LINK_STATE_OFF 0x00U +#define NV2080_NVLINK_CORE_LINK_STATE_HS 0x01U +#define NV2080_NVLINK_CORE_LINK_STATE_SAFE 0x02U +#define NV2080_NVLINK_CORE_LINK_STATE_FAULT 0x03U +#define NV2080_NVLINK_CORE_LINK_STATE_RECOVERY 0x04U +#define NV2080_NVLINK_CORE_LINK_STATE_FAIL 0x05U +#define NV2080_NVLINK_CORE_LINK_STATE_DETECT 0x06U +#define NV2080_NVLINK_CORE_LINK_STATE_RESET 0x07U +#define NV2080_NVLINK_CORE_LINK_STATE_ENABLE_PM 0x08U +#define NV2080_NVLINK_CORE_LINK_STATE_DISABLE_PM 0x09U +#define NV2080_NVLINK_CORE_LINK_STATE_SLEEP 0x0AU +#define NV2080_NVLINK_CORE_LINK_STATE_SAVE_STATE 0x0BU +#define NV2080_NVLINK_CORE_LINK_STATE_RESTORE_STATE 0x0CU +#define NV2080_NVLINK_CORE_LINK_STATE_PRE_HS 0x0EU +#define NV2080_NVLINK_CORE_LINK_STATE_DISABLE_ERR_DETECT 0x0FU +#define NV2080_NVLINK_CORE_LINK_STATE_LANE_DISABLE 0x10U +#define NV2080_NVLINK_CORE_LINK_STATE_LANE_SHUTDOWN 0x11U +#define NV2080_NVLINK_CORE_LINK_STATE_TRAFFIC_SETUP 0x12U +#define NV2080_NVLINK_CORE_LINK_STATE_INITPHASE1 0x13U +#define NV2080_NVLINK_CORE_LINK_STATE_INITNEGOTIATE 0x14U +#define NV2080_NVLINK_CORE_LINK_STATE_POST_INITNEGOTIATE 0x15U +#define NV2080_NVLINK_CORE_LINK_STATE_INITOPTIMIZE 0x16U +#define NV2080_NVLINK_CORE_LINK_STATE_POST_INITOPTIMIZE 0x17U +#define NV2080_NVLINK_CORE_LINK_STATE_DISABLE_HEARTBEAT 0x18U +#define NV2080_NVLINK_CORE_LINK_STATE_CONTAIN 0x19U +#define NV2080_NVLINK_CORE_LINK_STATE_INITTL 0x1AU +#define NV2080_NVLINK_CORE_LINK_STATE_INITPHASE5 0x1BU +#define NV2080_NVLINK_CORE_LINK_STATE_ALI 0x1CU +#define NV2080_NVLINK_CORE_LINK_STATE_ACTIVE_PENDING 0x1DU +#define NV2080_NVLINK_CORE_LINK_STATE_INVALID 0xFFU + +/* + * NVLINK TX Sublink states + * These should ALWAYS match the nvlink core library defines in nvlink.h + */ +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_HS 0x00U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SINGLE_LANE 0x04U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_LOW_POWER 0x04U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_TRAIN 0x05U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SAFE 0x06U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_OFF 0x07U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE 0x08U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE_DISABLE 0x09U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_DATA_READY 0x0AU +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_EQ 0x0BU +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_PRBS_EN 0x0CU +#define NV2080_NVLINK_CORE_SUBLINK_STATE_TX_POST_HS 0x0DU + +/* + * NVLINK RX Sublink states + * These should ALWAYS match the nvlink core library defines in nvlink.h + */ +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_HS 0x00U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SINGLE_LANE 0x04U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_LOW_POWER 0x04U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_TRAIN 0x05U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SAFE 0x06U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_OFF 0x07U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_RXCAL 0x08U +#define NV2080_NVLINK_CORE_SUBLINK_STATE_RX_INIT_TERM 0x09U + +/* + * Link training seed values + * These should ALWAYS match the values defined in nvlink.h + */ +#define NV2080_CTRL_NVLINK_MAX_SEED_NUM 6U +#define NV2080_CTRL_NVLINK_MAX_SEED_BUFFER_SIZE (0x7U) /* finn: Evaluated from "NV2080_CTRL_NVLINK_MAX_SEED_NUM + 1" */ + +// NVLINK callback types +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_DL_LINK_MODE 0x00U +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_DL_LINK_MODE 0x01U +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_TL_LINK_MODE 0x02U +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_TL_LINK_MODE 0x03U +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_TX_SUBLINK_MODE 0x04U +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_TX_SUBLINK_MODE 0x05U +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_MODE 0x06U +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_MODE 0x07U +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_DETECT 0x08U +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_DETECT 0x09U +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_WRITE_DISCOVERY_TOKEN 0x0AU +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_READ_DISCOVERY_TOKEN 0x0BU +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_TRAINING_COMPLETE 0x0CU +#define NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_UPHY_LOAD 0x0DU + +/* + * Structure to store the GET_DL_MODE callback params. + * mode + * The current Nvlink DL mode + */ +typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS { + NvU32 mode; +} NV2080_CTRL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS; + +/* + * Structure to store the SET_DL_LINK_MODE callback OFF params + * seedData + * The output seed data + */ +typedef struct NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS { + NvU32 seedData[NV2080_CTRL_NVLINK_MAX_SEED_BUFFER_SIZE]; +} NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS; + +/* + * Structure to store the SET_DL_LINK_MODE callback PRE_HS params + * remoteDeviceType + * The input remote Device Type + * ipVerDlPl + * The input DLPL version + */ +typedef struct NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS { + NvU32 remoteDeviceType; + NvU32 ipVerDlPl; +} NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS; + +/* + * Structure to store SET_DL_LINK_MODE callback INIT_PHASE1 params + * seedData[] + * The input seed data + */ +typedef struct NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS { + NvU32 seedData[NV2080_CTRL_NVLINK_MAX_SEED_BUFFER_SIZE]; +} NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS; + +/* + * Structure to store the Nvlink Remote and Local SID info + * remoteSid + * The output remote SID + * remoteDeviceType + * The output remote Device Type + * remoteLinkId + * The output remote link ID + * localSid + * The output local SID + */ +typedef struct NV2080_CTRL_NVLINK_REMOTE_LOCAL_SID_INFO { + NV_DECLARE_ALIGNED(NvU64 remoteSid, 8); + NvU32 remoteDeviceType; + NvU32 remoteLinkId; + NV_DECLARE_ALIGNED(NvU64 localSid, 8); +} NV2080_CTRL_NVLINK_REMOTE_LOCAL_SID_INFO; + +/* + * Structure to store the SET_DL_LINK_MODE callback POST_INITNEGOTIATE params + * bInitnegotiateConfigGood + * The output bool if the config is good + * remoteLocalSidInfo + * The output structure containing the Nvlink Remote/Local SID info + */ +typedef struct NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS { + NvBool bInitnegotiateConfigGood; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_REMOTE_LOCAL_SID_INFO remoteLocalSidInfo, 8); +} NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS; + +/* + * Structure to store the SET_DL_LINK_MODE callback POST_INITOPTIMIZE params + * bPollDone + * The output bool if the polling has finished + */ +typedef struct NV2080_CTRLNVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS { + NvBool bPollDone; +} NV2080_CTRLNVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS; + +/* + * Structure to store the SET_DL_LINK_MODE callback params + * mode + * The input nvlink state to set + * bSync + * The input sync boolean + * linkMode + * The input link mode to be set for the callback + */ +typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 mode, 8); + NvBool bSync; + NvU32 linkMode; + union { + NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS linkModeOffParams; + NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS linkModePreHsParams; + NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS linkModeInitPhase1Params; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS linkModePostInitNegotiateParams, 8); + NV2080_CTRLNVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS linkModePostInitOptimizeParams; + } linkModeParams; +} NV2080_CTRL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS; + +/* + * Structure to store the GET_TL_MODE callback params. + * mode + * The current Nvlink TL mode + */ +typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS { + NvU32 mode; +} NV2080_CTRL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS; + +/* + * Structure to store the SET_TL_LINK_MODE callback params + * mode + * The input nvlink mode to set + * bSync + * The input sync boolean + */ +typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 mode, 8); + NvBool bSync; +} NV2080_CTRL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS; + +/* + * Structure to store the GET_RX/TX_SUBLINK_MODE callback params + * sublinkMode + * The current Sublink mode + * sublinkSubMode + * The current Sublink sub mode + */ +typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS { + NvU32 sublinkMode; + NvU32 sublinkSubMode; +} NV2080_CTRL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS; + +/* + * Structure to store the SET_TL_LINK_MODE callback params + * mode + * The input nvlink mode to set + * bSync + * The input sync boolean + */ +typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 mode, 8); + NvBool bSync; +} NV2080_CTRL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS; + +/* + * Structure to store the SET_RX_SUBLINK_MODE callback params + * mode + * The input nvlink mode to set + * bSync + * The input sync boolean + */ +typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 mode, 8); + NvBool bSync; +} NV2080_CTRL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS; + +/* + * Structure to store the GET_RX_SUBLINK_DETECT callback params + * laneRxdetStatusMask + * The output RXDET per-lane status mask + */ +typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS { + NvU32 laneRxdetStatusMask; +} NV2080_CTRL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS; + +/* + * Structure to store the SET_RX_DETECT callback params + * bSync + * The input bSync boolean + */ +typedef struct NV2080_CTRL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS { + NvBool bSync; +} NV2080_CTRL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS; + +/* + * Structure to store the RD_WR_DISCOVERY_TOKEN callback params + * ipVerDlPl + * The input DLPL version + * token + * The output token + */ +typedef struct NV2080_CTRL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS { + NvU32 ipVerDlPl; + NV_DECLARE_ALIGNED(NvU64 token, 8); +} NV2080_CTRL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS; + +/* + * Structure to store the GET_UPHY_LOAD callback params + * bUnlocked + * The output unlocked boolean + */ +typedef struct NV2080_CTRL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS { + NvBool bUnlocked; +} NV2080_CTRL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS; + +/* + * Structure to store the Union of Callback params + * type + * The input type of callback to be executed + */ +typedef struct NV2080_CTRL_NVLINK_CALLBACK_TYPE { + NvU8 type; + union { + NV2080_CTRL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS getDlLinkMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS setDlLinkMode, 8); + NV2080_CTRL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS getTlLinkMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS setTlLinkMode, 8); + NV2080_CTRL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS getTxSublinkMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS setTxSublinkMode, 8); + NV2080_CTRL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS getRxSublinkMode; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS setRxSublinkMode, 8); + NV2080_CTRL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS getRxSublinkDetect; + NV2080_CTRL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS setRxSublinkDetect; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS writeDiscoveryToken, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS readDiscoveryToken, 8); + NV2080_CTRL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS getUphyLoad; + } callbackParams; +} NV2080_CTRL_NVLINK_CALLBACK_TYPE; + +/* + * NV2080_CTRL_CMD_NVLINK_CORE_CALLBACK + * + * Generic NvLink callback RPC to route commands to GSP + * + * [In] linkdId + * ID of the link to be used + * [In/Out] callBackType + * Callback params + */ +#define NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS { + NvU32 linkId; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_CALLBACK_TYPE callbackType, 8); +} NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_CORE_CALLBACK (0x20803019U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_GET_ALI_ENABLED + * + * Returns if ALI is enabled + * + * [Out] bEnableAli + * Output boolean for ALI enablement + */ +#define NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID (0x1aU) + +typedef struct NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS { + NvBool bEnableAli; +} NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_ALI_ENABLED (0x2080301aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_UPDATE_REMOTE_LOCAL_SID + * + * Update Remote and Local Sid info via GSP + * + * [In] linkId + * ID of the link to be used + * [Out] remoteLocalSidInfo + * The output structure containing the Nvlink Remote/Local SID info + */ +#define NV2080_CTRL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID (0x1bU) + +typedef struct NV2080_CTRL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS { + NvU32 linkId; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_REMOTE_LOCAL_SID_INFO remoteLocalSidInfo, 8); +} NV2080_CTRL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_UPDATE_REMOTE_LOCAL_SID (0x2080301bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_TYPE_PROGRAM 0x0U +#define NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_TYPE_RESET 0x1U + +/* + * NV2080_CTRL_CMD_NVLINK_UPDATE_HSHUB_MUX + * + * Generic Hshub Mux Update RPC to route commands to GSP + * + * [In] updateType + * HSHUB Mux update type to program or reset Mux + * [In] bSysMem + * Boolean to differentiate between sysmen and peer mem + * [In] peerMask + * Mask of peer IDs. Only parsed when bSysMem is false + */ +#define NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID (0x1cU) + +typedef struct NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_PARAMS { + NvBool updateType; + NvBool bSysMem; + NvU32 peerMask; +} NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_UPDATE_HSHUB_MUX (0x2080301cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_PRE_SETUP_NVLINK_PEER + * + * Performs all the necessary actions required before setting a peer on NVLink + * + * [In] peerId + * Peer ID which will be set on NVLink + * [In] peerLinkMask + * Mask of links that connects the given peer + * [In] bNvswitchConn + * Is the GPU connected to NVSwitch + */ +#define NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID (0x1dU) + +typedef struct NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS { + NvU32 peerId; + NvU32 peerLinkMask; + NvBool bNvswitchConn; +} NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS; +#define NV2080_CTRL_CMD_NVLINK_PRE_SETUP_NVLINK_PEER (0x2080301dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_POST_SETUP_NVLINK_PEER + * + * Performs all the necessary actions required after setting a peer on NVLink + * + * [In] peerMask + * Mask of Peer IDs which has been set on NVLink + */ +#define NV2080_CTRL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID (0x1eU) + +typedef struct NV2080_CTRL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS { + NvU32 peerMask; +} NV2080_CTRL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS; +#define NV2080_CTRL_CMD_NVLINK_POST_SETUP_NVLINK_PEER (0x2080301eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_SYSMEM 0x1U +#define NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_PEER 0x2U + +/* + * NV2080_CTRL_CMD_NVLINK_REMOVE_NVLINK_MAPPING + * + * Performs all the necessary actions required to remove NVLink mapping (sysmem or peer or both) + * + * [In] mapTypeMask + * Remove NVLink mapping for the given map types (sysmem or peer or both) + * [In] peerMask + * Mask of Peer IDs which needs to be removed on NVLink + * Only parsed if mapTypeMask accounts peer + * [In] bL2Entry + * Is the peer removal happening because links are entering L2 low power state? + * Only parsed if mapTypeMask accounts peer + */ +#define NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID (0x1fU) + +typedef struct NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS { + NvU32 mapTypeMask; + NvU32 peerMask; + NvBool bL2Entry; +} NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS; +#define NV2080_CTRL_CMD_NVLINK_REMOVE_NVLINK_MAPPING (0x2080301fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_SAVE_RESTORE_HSHUB_STATE + * + * Performs all the necessary actions required to save/restore HSHUB state during NVLink L2 entry/exit + * + * [In] bSave + * Whether this is a save/restore operation + * [In] linkMask + * Mask of links for which HSHUB config registers need to be saved/restored + */ +#define NV2080_CTRL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV2080_CTRL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS { + NvBool bSave; + NvU32 linkMask; +} NV2080_CTRL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS; +#define NV2080_CTRL_CMD_NVLINK_SAVE_RESTORE_HSHUB_STATE (0x20803020U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SET (0x00000000) +#define NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SAVE (0x00000001) +#define NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_RESTORE (0x00000002) + +/* + * NV2080_CTRL_CMD_NVLINK_PROGRAM_BUFFERREADY + * + * Performs all the necessary actions required to save/restore bufferready state during NVLink L2 entry/exit + * + * [In] flags + * Whether to set, save or restore bufferready + * [In] bSysmem + * Whether to perform the operation for sysmem links or peer links + * [In] peerLinkMask + * Mask of peer links for which bufferready state need to be set/saved/restored + */ +#define NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID (0x21U) + +typedef struct NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_PARAMS { + NvU32 flags; + NvBool bSysmem; + NvU32 peerLinkMask; +} NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_PARAMS; +#define NV2080_CTRL_CMD_NVLINK_PROGRAM_BUFFERREADY (0x20803021U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_UPDATE_CURRENT_CONFIG + * + * Performs all the necessary actions required to update the current Nvlink configuration + * + * [out] bNvlinkSysmemEnabled + * Whether sysmem nvlink support was enabled + */ +#define NV2080_CTRL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NV2080_CTRL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS { + NvBool bNvlinkSysmemEnabled; +} NV2080_CTRL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS; +#define NV2080_CTRL_CMD_NVLINK_UPDATE_CURRENT_CONFIG (0x20803022U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID" */ + +// +// Set the near end loopback mode using the following +// Currently, three modes - NEA, NEDR, NEW +// +#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_DEFAULT (0x00000000) +#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEA (0x00000001) +#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDR (0x00000002) +#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDW (0x00000003) + +/* + * NV2080_CTRL_CMD_NVLINK_SET_LOOPBACK_MODE + * + * Generic NvLink callback for MODS + * + * [In] linkdId + * ID of the link to be used + * [In] loopbackMode + * This value will decide which loopback mode need to + * set on the specified link. + * Modes are NEA / NEDR / NEDW + */ +#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS_MESSAGE_ID (0x23U) + +typedef struct NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS { + NvU32 linkId; + NvU8 loopbackMode; +} NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_SET_LOOPBACK_MODE (0x20803023U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_UPDATE_PEER_LINK_MASK + * + * Synchronizes the peerLinkMask between CPU-RM and GSP-RM + * + * [In] gpuInst + * Gpu instance + * [In] peerLinkMask + * Mask of links to the given peer GPU + */ +#define NV2080_CTRL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID (0x24U) + +typedef struct NV2080_CTRL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS { + NvU32 gpuInst; + NvU32 peerLinkMask; +} NV2080_CTRL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_UPDATE_PEER_LINK_MASK (0x20803024U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_UPDATE_LINK_CONNECTION + * + * Updates the remote connection information for a link + * + * [In] linkId + * Id of the link to be used + * [In] bConnected + * Boolean that tracks whether the link is connected + * [In] remoteDeviceType + * Tracks whether the remote device is switch/gpu/ibmnpu/tegra + * [In] remoteLinkNumber + * Tracks the link number for the connected remote device + */ +#define NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID (0x25U) + +typedef struct NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS { + NV_DECLARE_ALIGNED(NvU64 remoteDeviceType, 8); + NV_DECLARE_ALIGNED(NvU64 remoteChipSid, 8); + NvU32 linkId; + NvU32 laneRxdetStatusMask; + NvU32 remoteLinkNumber; + NvU32 remotePciDeviceId; + NvU32 remoteDomain; + NvU8 remoteBus; + NvU8 remoteDevice; + NvU8 remoteFunction; + NvBool bConnected; +} NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_UPDATE_LINK_CONNECTION (0x20803025U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS_POST_TOPOLOGY + * + * Enable links post topology via GSP + * + * [In] linkMask + * Mask of links to enable + * [Out] initializedLinks + * Mask of links that were initialized + */ +#define NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID (0x26U) + +typedef struct NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS { + NvU32 linkMask; + NvU32 initializedLinks; +} NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS_POST_TOPOLOGY (0x20803026U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_PRE_LINK_TRAIN_ALI + * + * [In] linkMask + * Mask of enabled links to train + * [In] bSync + * The input sync boolean + */ +#define NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID (0x27U) + +typedef struct NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS { + NvU32 linkMask; + NvBool bSync; +} NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_PRE_LINK_TRAIN_ALI (0x20803027U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID" */ + +// +// Read Refresh counter - the pass/fail occurrences +// + +typedef struct NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO { + // requested links or not + NvBool bValid; + + // counters + NvU16 passCount; + NvU16 failCount; +} NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO; + +#define NV2080_CTRL_NVLINK_MAX_LINK_COUNT 32 + +/* + * NV2080_CTRL_CMD_NVLINK_GET_REFRESH_COUNTERS + * + * + * [In] linkMask + * Specifies for which links we want to read the counters + * [Out] refreshCountPass + * Count of number of times PHY refresh pass + * [Out] refreshCountFail + * Count of number of times PHY refresh fail + */ +#define NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS_MESSAGE_ID (0x28U) + +typedef struct NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS { + NvU32 linkMask; + NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO refreshCount[NV2080_CTRL_NVLINK_MAX_LINK_COUNT]; +} NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_REFRESH_COUNTERS (0x20803028U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS_MESSAGE_ID" */ + +// +// Clear Refresh counter - the pass/fail occurrences +// + +/* + * NV2080_CTRL_CMD_NVLINK_CLEAR_REFRESH_COUNTERS + * + * + * [In] linkMask + * Specifies for which links we want to clear the counters + */ +#define NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS_MESSAGE_ID (0x29U) + +typedef struct NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS { + NvU32 linkMask; +} NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_CLEAR_REFRESH_COUNTERS (0x20803029U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_GET_LINK_MASK_POST_RX_DET + * + * Get link mask post Rx detection + * + * [Out] postRxDetLinkMask + * Mask of links discovered + */ +#define NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID (0x2aU) + +typedef struct NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS { + NvU32 postRxDetLinkMask; +} NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_LINK_MASK_POST_RX_DET (0x2080302aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_LINK_TRAIN_ALI + * + * [In] linkMask + * Mask of enabled links to train + * [In] bSync + * The input sync boolean + */ +#define NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID (0x2bU) + +typedef struct NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS { + NvU32 linkMask; + NvBool bSync; +} NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_LINK_TRAIN_ALI (0x2080302bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID" */ + +typedef struct NV2080_CTRL_NVLINK_DEVICE_LINK_VALUES { + NvBool bValid; + NvU8 linkId; + NvU32 ioctrlId; + NvU8 pllMasterLinkId; + NvU8 pllSlaveLinkId; + NvU32 ipVerDlPl; +} NV2080_CTRL_NVLINK_DEVICE_LINK_VALUES; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_NVLINK_DEVICE_INFO + * + * [Out] ioctrlMask + * Mask of IOCTRLs discovered from PTOP device info table + * [Out] ioctrlNumEntries + * Number of IOCTRL entries in the PTOP device info table + * [Out] ioctrlSize + * Maximum number of entries in the PTOP device info table + * [Out] discoveredLinks + * Mask of links discovered from all the IOCTRLs + * [Out] ipVerNvlink + * IP revision of the NVLink HW + * [Out] linkInfo + * Per link information + */ + +#define NV2080_CTRL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID (0x2cU) + +typedef struct NV2080_CTRL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS { + NvU32 ioctrlMask; + NvU8 ioctrlNumEntries; + NvU32 ioctrlSize; + NvU32 discoveredLinks; + NvU32 ipVerNvlink; + NV2080_CTRL_NVLINK_DEVICE_LINK_VALUES linkInfo[NV2080_CTRL_NVLINK_MAX_LINKS]; +} NV2080_CTRL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_DEVICE_INFO (0x2080302cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_MAX_LINKS_PER_IOCTRL_SW 6U + +typedef struct NV2080_CTRL_NVLINK_DEVICE_IP_REVISION_VALUES { + NvU32 ipVerIoctrl; + NvU32 ipVerMinion; +} NV2080_CTRL_NVLINK_DEVICE_IP_REVISION_VALUES; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_IOCTRL_DEVICE_INFO + * + * [In] ioctrlIdx + * IOCTRL index + * [Out] PublicId + * PublicId of the IOCTRL discovered + * [Out] localDiscoveredLinks + * Mask of discovered links local to the IOCTRL + * [Out] localGlobalLinkOffset + * Global link offsets for the locally discovered links + * [Out] ioctrlDiscoverySize + * IOCTRL table size + * [Out] numDevices + * Number of devices discovered from the IOCTRL + * [Out] deviceIpRevisions + * IP revisions for the devices discovered in the IOCTRL + */ + +#define NV2080_CTRL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID (0x2dU) + +typedef struct NV2080_CTRL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS { + NvU32 ioctrlIdx; + NvU32 PublicId; + NvU32 localDiscoveredLinks; + NvU32 localGlobalLinkOffset; + NvU32 ioctrlDiscoverySize; + NvU8 numDevices; + NV2080_CTRL_NVLINK_DEVICE_IP_REVISION_VALUES ipRevisions; +} NV2080_CTRL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_IOCTRL_DEVICE_INFO (0x2080302dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_PROGRAM_LINK_SPEED + * + * Program NVLink Speed from OS/VBIOS + * + * [In] bPlatformLinerateDefined + * Whether line rate is defined in the platform + * [In] platformLineRate + * Platform defined line rate + * [Out] nvlinkLinkSpeed + * The line rate that was programmed for the links + */ +#define NV2080_CTRL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID (0x2eU) + +typedef struct NV2080_CTRL_NVLINK_PROGRAM_LINK_SPEED_PARAMS { + NvBool bPlatformLinerateDefined; + NvU32 platformLineRate; + NvU32 nvlinkLinkSpeed; +} NV2080_CTRL_NVLINK_PROGRAM_LINK_SPEED_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_PROGRAM_LINK_SPEED (0x2080302eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_ARE_LINKS_TRAINED + * + * [In] linkMask + * Mask of links whose state will be checked + * [In] bActiveOnly + * The input boolean to check for Link Active state + * [Out] bIsLinkActive + * Boolean array to track if the link is trained + */ +#define NV2080_CTRL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID (0x2fU) + +typedef struct NV2080_CTRL_NVLINK_ARE_LINKS_TRAINED_PARAMS { + NvU32 linkMask; + NvBool bActiveOnly; + NvBool bIsLinkActive[NV2080_CTRL_NVLINK_MAX_LINKS]; +} NV2080_CTRL_NVLINK_ARE_LINKS_TRAINED_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_ARE_LINKS_TRAINED (0x2080302fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_RESET_FLAGS_ASSERT (0x00000000) +#define NV2080_CTRL_NVLINK_RESET_FLAGS_DEASSERT (0x00000001) +#define NV2080_CTRL_NVLINK_RESET_FLAGS_TOGGLE (0x00000002) + +/* + * NV2080_CTRL_CMD_NVLINK_RESET_LINKS + * + * [In] linkMask + * Mask of links which need to be reset + * [In] flags + * Whether to assert, de-assert or toggle the Nvlink reset + */ + +#define NV2080_CTRL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID (0x30U) + +typedef struct NV2080_CTRL_NVLINK_RESET_LINKS_PARAMS { + NvU32 linkMask; + NvU32 flags; +} NV2080_CTRL_NVLINK_RESET_LINKS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_RESET_LINKS (0x20803030U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_DISABLE_DL_INTERRUPTS + * + * [In] linkMask + * Mask of links for which DL interrrupts need to be disabled + */ +#define NV2080_CTRL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID (0x31U) + +typedef struct NV2080_CTRL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS { + NvU32 linkMask; +} NV2080_CTRL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_DISABLE_DL_INTERRUPTS (0x20803031U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID" */ + +/* + * Structure to store the GET_LINK_AND_CLOCK__INFO params + * + * [Out] bLinkConnectedToSystem + * Boolean indicating sysmem connection of a link + * [Out] bLinkConnectedToPeer + * Boolean indicating peer connection of a link + * [Out] bLinkReset + * Whether the link is in reset + * [Out] subLinkWidth + * Number of lanes per sublink + * [Out] linkState + * Mode of the link + * [Out] txSublinkState + * Tx sublink state + * [Out] rxSublinkState + * Rx sublink state + * [Out] bLaneReversal + * Boolean indicating if a link's lanes are reversed + * [Out] nvlinkLinkClockKHz + * Link clock value in KHz + * [Out] nvlinkLineRateMbps + * Link line rate in Mbps + * [Out] nvlinkLinkClockMhz + * Link clock in MHz + * [Out] nvlinkLinkDataRateKiBps + * Link Data rate in KiBps + * [Out] nvlinkRefClkType + * Current Nvlink refclk source + * [Out] nvlinkReqLinkClockMhz + * Requested link clock value + */ +typedef struct NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES { + NvBool bLinkConnectedToSystem; + NvBool bLinkConnectedToPeer; + NvBool bLinkReset; + NvU8 subLinkWidth; + NvU32 linkState; + NvU32 txSublinkState; + NvU32 rxSublinkState; + NvBool bLaneReversal; + NvU32 nvlinkLinkClockKHz; + NvU32 nvlinkLineRateMbps; + NvU32 nvlinkLinkClockMhz; + NvU32 nvlinkLinkDataRateKiBps; + NvU8 nvlinkRefClkType; + NvU32 nvlinkReqLinkClockMhz; +} NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES; + +/* + * NV2080_CTRL_CMD_NVLINK_GET_LINK_AND_CLOCK_INFO + * + * [In] linkMask + * Mask of enabled links to loop over + * [Out] nvlinkRefClkSpeedKHz + * Ref clock value n KHz + * [Out] linkInfo + * Per link information + */ +#define NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID (0x32U) + +typedef struct NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS { + NvU32 linkMask; + NvU32 nvlinkRefClkSpeedKHz; + NvBool bSublinkStateInst; // whether instantaneous sublink state is needed + NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES linkInfo[NV2080_CTRL_NVLINK_MAX_LINKS]; +} NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_LINK_AND_CLOCK_INFO (0x20803032U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_SETUP_NVLINK_SYSMEM + * + * Updates the HSHUB sysmem config resgister state to reflect sysmem NVLinks + * + * [In] sysmemLinkMask + * Mask of discovered sysmem NVLinks + */ +#define NV2080_CTRL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID (0x33U) + +typedef struct NV2080_CTRL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS { + NvU32 sysmemLinkMask; +} NV2080_CTRL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS; +#define NV2080_CTRL_CMD_NVLINK_SETUP_NVLINK_SYSMEM (0x20803033U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_PROCESS_FORCED_CONFIGS + * + * Process NVLink forced configurations which includes setting of HSHUB and memory system + * + * [In] bLegacyForcedConfig + * Tracks whether the forced config is legacy forced config or chiplib config + * [Out] bOverrideComputePeerMode + * Whether compute peer mode was enabled + * [In] phase + * Only applicable when bLegacyForcedConfig is true + * Tracks the set of registers to program from the NVLink table + * [In] linkConnection + * Array of chiplib configurations + */ +#define NV2080_CTRL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID (0x34U) + +typedef struct NV2080_CTRL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS { + NvBool bLegacyForcedConfig; + NvBool bOverrideComputePeerMode; + NvU32 phase; + NvU32 linkConnection[NV2080_CTRL_NVLINK_MAX_LINKS]; +} NV2080_CTRL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_PROCESS_FORCED_CONFIGS (0x20803034U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS + * + * Sync the NVLink lane shutdown properties with GSP-RM + * + * [In] bLaneShutdownEnabled + * Whether nvlink shutdown is enabled for the chip + * [In] bLaneShutdownOnUnload + * Whether nvlink shutdown should be triggered on driver unload + */ +#define NV2080_CTRL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID (0x35U) + +typedef struct NV2080_CTRL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS { + NvBool bLaneShutdownEnabled; + NvBool bLaneShutdownOnUnload; +} NV2080_CTRL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS (0x20803035U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_ENABLE_SYSMEM_NVLINK_ATS + * + * Enable ATS functionality related to NVLink sysmem if hardware support is available + * + * [In] notUsed + */ +#define NV2080_CTRL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID (0x36U) + +typedef struct NV2080_CTRL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS { + NvU32 notUsed; +} NV2080_CTRL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_ENABLE_SYSMEM_NVLINK_ATS (0x20803036U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK + * + * Get the mask of Nvlink links connected to system + * + * [Out] sysmemLinkMask + * Mask of Nvlink links connected to system + */ +#define NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID (0x37U) + +typedef struct NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS { + NvU32 sysmemLinkMask; +} NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK (0x20803037U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_GET_SET_NVSWITCH_FLA_ADDR + * + * Get/Set NVSwitch FLA address + * + * [In] bGet + * Whether to get or set the NVSwitch FLA address + * [In/Out] addr + * Address that is to be set or retrieved. + */ +#define NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS_MESSAGE_ID (0x38U) + +typedef struct NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS { + NvBool bGet; + NV_DECLARE_ALIGNED(NvU64 addr, 8); +} NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_SET_NVSWITCH_FLA_ADDR (0x20803038) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO + * + * Syncs the different link masks and vbios defined values between CPU-RM and GSP-RM + * + * [in] discoveredLinks + * Mask of links discovered from IOCTRLs + * + * [in] connectedLinksMask + * Mask of links which are connected (remote present) + * + * [in] bridgeSensableLinks + * Mask of links whose remote endpoint presence can be sensed + * + * [in] bridgedLinks + * Mask of links which are connected (remote present) + * Same as connectedLinksMask, but also tracks the case where link + * is connected but marginal and could not initialize + * + * [out] initDisabledLinksMask + * Mask of links for which initialization is disabled + * + * [out] vbiosDisabledLinkMask + * Mask of links disabled in the VBIOS + * + * [out] initializedLinks + * Mask of initialized links + * + * [out] bEnableTrainingAtLoad + * Whether the links should be trained to active during driver load + * + * [out] bEnableSafeModeAtLoad + * Whether the links should be initialized to swcfg during driver load + */ + +#define NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS_MESSAGE_ID (0x39U) + +typedef struct NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS { + NvU32 discoveredLinks; + NvU32 connectedLinksMask; + NvU32 bridgeSensableLinks; + NvU32 bridgedLinks; + NvU32 initDisabledLinksMask; + NvU32 vbiosDisabledLinkMask; + NvU32 initializedLinks; + NvBool bEnableTrainingAtLoad; + NvBool bEnableSafeModeAtLoad; +} NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO (0x20803039U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS + * + * Enable pre-topology setup on the mask of enabled links + * This command accepts no parameters. + */ + +#define NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS (0x2080303aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | 0x3a" */ + +/* + * NV2080_CTRL_CMD_NVLINK_PROCESS_INIT_DISABLED_LINKS + * + * Process the init disabled NVLinks and filter those out + * + * [in/out] initDisabledLinksMask + * Mask of links initdisabled on a given GPU + * + * [in] bSkipHwNvlinkDisable + * Whether to consider skipping the HW initdisable links + */ + +#define NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS_MESSAGE_ID (0x3bU) + +typedef struct NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS { + NvU32 initDisabledLinksMask; + NvBool bSkipHwNvlinkDisable; +} NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_PROCESS_INIT_DISABLED_LINKS (0x2080303bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_EOM_CONTROL + * + * cmd [IN] enum identifying the EOM related command for the driver to process + * link [IN] linkId + * params [IN] NvU32 word that is written into NV_PMINION_SCRATCH_SWRW_0 before calling CONFIGEOM dlcmd + * + * Params Packing is specified in Minion IAS + */ + +typedef enum NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND { + NVLINK_EOM_CONTROL_START_EOM = 0, + NVLINK_EOM_CONTROL_END_EOM = 1, + NVLINK_EOM_CONTROL_CONFIG_EOM = 2, + NVLINK_EOM_CONTROL_FULL_EOM_SEQUENCE = 3, +} NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND; + +#define NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID (0x3cU) + +typedef struct NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS { + NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND cmd; + NvU32 linkId; + NvU32 params; +} NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_EOM_CONTROL (0x2080303c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID" */ + +/*! + * Inband Recieved Data + */ +#define NV2080_CTRL_NVLINK_INBAND_MAX_MSG_SIZE 4096 +#define NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_MESSAGE_ID (0x3dU) + +typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS { + NvU8 data[NV2080_CTRL_NVLINK_INBAND_MAX_MSG_SIZE]; + NvU32 dataSize; +} NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS; + +#define NV2080_CTRL_NVLINK_L1_THRESHOLD_SET (0x00000000U) +#define NV2080_CTRL_NVLINK_L1_THRESHOLD_GET (0x00000001U) + +/* + * NV2080_CTRL_CMD_NVLINK_L1_THRESHOLD + * + * This command is used to get/set the L1 threshold value + * + * [in] flag + * Whether to set or get the L1 threshold value + * + * [in/out] l1Threshold + * Used to set or get the L1 threshold value + * + */ +#define NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS_MESSAGE_ID (0x3eU) + +typedef struct NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS { + NvU32 flag; + NvU32 l1Threshold; +} NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_L1_THRESHOLD (0x2080303eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_INBAND_SEND_DATA + * + * RPC for sending Inband data + * + * [In] data[] + * data to be sent over inband + * [In] dataSize + * Size of valid data in data array + */ +#define NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID (0x3fU) + +typedef struct NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS { + NvU8 buffer[NV2080_CTRL_NVLINK_INBAND_MAX_MSG_SIZE]; + NvU32 dataSize; +} NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_INBAND_SEND_DATA (0x2080303fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_IS_GPU_DEGRADED + * + * RPC for Getting GPU degraded status upon link error + * + * [In] linkId + * Id of the link on which error occured + * [In] bIsGpuDegraded + * Boolean to track corresponding GPU is degraded or not + */ +#define NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID (0x40U) + +typedef struct NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS { + NvU32 linkId; + NvBool bIsGpuDegraded; +} NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_IS_GPU_DEGRADED (0x20803040U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_DIRECT_CONNECT_CHECK + * + * This command is used to check for missing + * bridge/nvlink for direct connect GPU + * + * [out] bIsEnoughNvLink + * Check if number of active nvlink meet the minimum requirements. + * [out] numBridge + * Number of NVLink bridge + * [out] bridgePresenceMask + * Bit mask of NVLink bridges's presence + */ +#define NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS_MESSAGE_ID (0x41U) + +typedef struct NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS { + NvBool bIsEnoughNvLink; + NvU32 numBridge; + NvU32 bridgePresenceMask; +} NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_DIRECT_CONNECT_CHECK (0x20803041U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS_MESSAGE_ID" */ + + +/* _ctrl2080nvlink_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h new file mode 100644 index 0000000..b12521d --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h @@ -0,0 +1,578 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080perf.finn +// + +#include "nvfixedtypes.h" +#include "ctrl/ctrl2080/ctrl2080base.h" + +#define NV_SUBPROC_NAME_MAX_LENGTH 100 + +#include "nvmisc.h" + +#include "ctrl/ctrl2080/ctrl2080clk.h" +#include "ctrl/ctrl2080/ctrl2080gpumon.h" +#include "ctrl/ctrl2080/ctrl2080volt.h" +#include "ctrl/ctrl2080/ctrl2080vfe.h" +#include "ctrl/ctrl2080/ctrl2080pmumon.h" +#include "ctrl/ctrl0080/ctrl0080perf.h" +// +// XAPICHK/XAPI_TEST chokes on the "static NVINLINE" defines in nvmisc.h. +// However, we don't need any of those definitions for those tests (XAPICHK is a +// syntactical check, not a functional test). So, instead, just #define out the +// macros referenced below. +// + +/* + * NV2080_CTRL_CMD_PERF_BOOST + * + * This command can be used to boost P-State up one level or to the highest for a limited + * duration for the associated subdevice. Boosts from different clients are being tracked + * independently. Note that there are other factors that can limit P-States so the resulting + * P-State may differ from expectation. + * + * flags + * This parameter specifies the actual command. _CLEAR is to clear existing boost. + * _BOOST_1LEVEL is to boost P-State one level higher. _BOOST_TO_MAX is to boost + * to the highest P-State. + * duration + * This parameter specifies the duration of the boost in seconds. This has to be less + * than NV2080_CTRL_PERF_BOOST_DURATION_MAX. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD 1:0 +#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_CLEAR (0x00000000) +#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_1LEVEL (0x00000001) +#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_TO_MAX (0x00000002) + +#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA 4:4 +#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_NO (0x00000000) +#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_YES (0x00000001) + +#define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC 5:5 +#define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_NO (0x00000000) +#define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_YES (0x00000001) + +#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY 6:6 +#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_DEFAULT (0x00000000) +#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_HIGH (0x00000001) + +#define NV2080_CTRL_PERF_BOOST_DURATION_MAX 3600 //The duration can be specified up to 1 hour +#define NV2080_CTRL_PERF_BOOST_DURATION_INFINITE 0xffffffff // If set this way, the boost will last until cleared. + +#define NV2080_CTRL_CMD_PERF_BOOST (0x2080200a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_BOOST_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_BOOST_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV2080_CTRL_PERF_BOOST_PARAMS { + NvU32 flags; + NvU32 duration; +} NV2080_CTRL_PERF_BOOST_PARAMS; + +/* + * NV2080_CTRL_CMD_PERF_RESERVE_PERFMON_HW + * + * This command reserves HW Performance Monitoring capabilities for exclusive + * use by the requester. If the HW Performance Monitoring capabilities are + * currently in use then NVOS_STATUS_ERROR_STATE_IN_USE is returned. + * + * bAcquire + * When set to TRUE this parameter indicates that the client wants to + * acquire the Performance Monitoring capabilities on the subdevice. + * When set to FALSE this parameter releases the Performance Monitoring + * capabilities on the subdevice. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_ERROR_STATE_IN_USE + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_PERF_RESERVE_PERFMON_HW (0x20802093) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS_MESSAGE_ID (0x93U) + +typedef struct NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS { + NvBool bAcquire; +} NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS; + +/* + * NV2080_CTRL_PERF_POWERSTATE + * + * This structure describes power state information. + * + * powerState + * This parameter specifies the type of power source. + * Legal values for this parameter include: + * NV2080_CTRL_PERF_POWER_SOURCE_AC + * This values indicates that the power state is AC. + * NV2080_CTRL_PERF_POWER_SOURCE_BATTERY + * This values indicates that the power state is battery. + */ +#define NV2080_CTRL_PERF_POWER_SOURCE_AC (0x00000000) +#define NV2080_CTRL_PERF_POWER_SOURCE_BATTERY (0x00000001) + +typedef struct NV2080_CTRL_PERF_POWERSTATE_PARAMS { + NvU32 powerState; +} NV2080_CTRL_PERF_POWERSTATE_PARAMS; + +/* + * NV2080_CTRL_CMD_PERF_SET_POWERSTATE + * + * This command can be used to set the perf power state as AC or battery. + * + * powerStateInfo + * This parameter specifies the power source type to set. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_PERF_SET_POWERSTATE (0x2080205b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS_MESSAGE_ID (0x5BU) + +typedef struct NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS { + NV2080_CTRL_PERF_POWERSTATE_PARAMS powerStateInfo; +} NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS; + +/* + * NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE + * + * This command allows the forcing of a performance level based on auxiliary + * power-states. + * + * powerState + * This parameter specifies the target auxiliary Power state. Legal aux + * power-states for this parameter are defined by the + * NV2080_CTRL_PERF_AUX_POWER_STATE_P* definitions that follow. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE (0x20802092) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS_MESSAGE_ID (0x92U) + +typedef struct NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS { + NvU32 powerState; +} NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS; + +#define NV2080_CTRL_PERF_AUX_POWER_STATE_P0 (0x00000000) +#define NV2080_CTRL_PERF_AUX_POWER_STATE_P1 (0x00000001) +#define NV2080_CTRL_PERF_AUX_POWER_STATE_P2 (0x00000002) +#define NV2080_CTRL_PERF_AUX_POWER_STATE_P3 (0x00000003) +#define NV2080_CTRL_PERF_AUX_POWER_STATE_P4 (0x00000004) +#define NV2080_CTRL_PERF_AUX_POWER_STATE_COUNT (0x00000005) + +/*! + * Enumeration of the RATED_TDP arbitration clients which make requests to force + * enable/disable VF points above the RATED_TDP point. + * + * These clients are sorted in descending priority - the RM will arbitrate + * between all clients in order of priority, taking as output the first client + * whose input action != @ref NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT. + */ +typedef enum NV2080_CTRL_PERF_RATED_TDP_CLIENT { + /*! + * Internal RM client corresponding to the RM's internal state and features. + * The RM client will either allow default behavior (@ref + * NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT) or will limit to RATED_TDP + * (@ref NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT) when no power + * controllers are active. + */ + NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM = 0, + /*! + * This Client is specifically for Bug 1785342 where we need to limit the TDP + * to Min value on boot. And clear the Max TDP limit. + */ + NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342 = 1, + /*! + * Global client request. This client is expected to be used by a global + * switch functionality in an end-user tool, such as EVGA Precision, to + * either force enabling boost above RATED_TDP (@ref + * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED) or to force limiting to + * RATED_TDP (@ref NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT) across the + * board, regardless of any app-profie settings. + */ + NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL = 2, + /*! + * Operating system request. This client is expected to be used by the + * operating system to set @ref NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK + * for performance profiling. + */ + NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS = 3, + /*! + * App profile client requests. This client is expected to be used by the + * app-profile settings to either default to whatever was requested by + * higher-priority clients (@ref NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT) + * or to limit to RATED_TDP (@ref + * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT) for apps which have shown + * bad behavior when boosting. + */ + NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE = 4, + /*! + * Number of supported clients. + * + * @Note MUST ALWAYS BE LAST! + */ + NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS = 5, +} NV2080_CTRL_PERF_RATED_TDP_CLIENT; + +/*! + * Enumeration RATED_TDP actions - these are the requested actions clients can + * make to change the behavior of the RATED_TDP functionality. + */ +typedef enum NV2080_CTRL_PERF_RATED_TDP_ACTION { + /*! + * The default action - meaning no explicit request from the client other + * than to take the default behavior (allowing boosting above RATED_TDP) or + * any explicit actions from lower priority clients. + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT = 0, + /*! + * Force allow boosting above RATED_TDP - this action explicitly requests + * boosting above RATED_TDP, preventing lower priority clients to limit to + * RATED_TDP. + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED = 1, + /*! + * Force to limit above RATED_TDP - this action explicitly requests to limit + * to RATED_TDP. This is the opposite of the default behavior to allow + * boosting above RATED_TDP. Clients specify this action when they + * explicitly need boost to be disabled (e.g. eliminating perf variation, + * special apps which exhibit bad behavior, etc.). + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT = 2, + /*! + * Lock to RATED_TDP - this action requests the clocks to be fixed at the + * RATED_TDP. Used for achieving stable clocks required for profiling. + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK = 3, + /*! + * Lock to Min TDP - This requests min to be fixed at RATED_TDP but allow + * boosting for max + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR = 4, +} NV2080_CTRL_PERF_RATED_TDP_ACTION; + +/*! + * Structure describing dynamic state of the RATED_TDP feature. + */ +#define NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_MESSAGE_ID (0x6DU) + +typedef struct NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS { + /*! + * Structure of internal RM state - these values are used to determine the + * behavior of NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM per the RM's @ref + * perfPwrRatedTdpLimitRegisterClientActive() interface. + */ + struct { + /*! + * [out] - Mask of active client controllers (@ref + * PERF_PWR_RATED_TDP_CLIENT) which are currently regulating TDP. When + * this mask is zero, NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM will request + * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT. + */ + NvU32 clientActiveMask; + /*! + * [out] - Boolean indicating that user has requested locking to + * RATED_TDP vPstate via corresponding regkey + * NV_REG_STR_RM_PERF_RATED_TDP_LIMIT. When the boolean value is true, + * NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM will request + * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT. + */ + NvU8 bRegkeyLimitRatedTdp; + } rm; + + /*! + * [out] - Arbitrated output action of all client requests (@ref inputs). + * This is the current state of the RATED_TDP feature. Will only be @ref + * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED or @ref + * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT. + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION output; + /*! + * [out] - Array of input client request actions, indexed via @ref + * NV2080_CTRL_PERF_RATED_TDP_CLIENT_. RM will arbitrate between these + * requests, choosing the highest priority request != @ref + * NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT or fallback to choosing @ref + * NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED. + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION inputs[NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS]; +} NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS; + +/*! + * NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL + * + * This command retrieves the current requested RATED_TDP action corresponding + * to the specified client. + * + * See @ref NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS for documentation of + * parameters. + * + * Possible status values returned are + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL (0x2080206e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | 0x6E" */ + +/*! + * NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL + * + * This command sets the requested RATED_TDP action corresponding to the + * specified client. @Note, however, that this command is unable to set @ref + * NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM. + * + * See @ref NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS for documentation of + * parameters. + * + * Possible status values returned are + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL (0x2080206f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | 0x6F" */ + +/*! + * Structure containing the requested action for a RATED_TDP client (@ref + * NV2080_CTRL_PERF_RATED_TDP_CLIENT). + */ +typedef struct NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS { + /*! + * [in] - Specified client for request. + */ + NV2080_CTRL_PERF_RATED_TDP_CLIENT client; + /*! + * [in/out] - Client's requested action. + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION input; +} NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS; + +/*! + * This struct represents the GPU monitoring perfmon sample for an engine. + */ +typedef struct NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE { + /*! + * Percentage during the sample that the engine remains busy. This + * is in units of pct*100. + */ + NvU32 util; + /*! + * Scaling factor to convert utilization from full GPU to per vGPU. + */ + NvU32 vgpuScale; + /*! + * Process ID of the process that was active on the engine when the + * sample was taken. If no process is active then NV2080_GPUMON_PID_INVALID + * will be returned. + */ + NvU32 procId; + /*! + * Process ID of the process in the vGPU VM that was active on the engine when + * the sample was taken. If no process is active then NV2080_GPUMON_PID_INVALID + * will be returned. + */ + NvU32 subProcessID; + /*! + * Process name of the process in the vGPU VM that was active on the engine when + * the sample was taken. If no process is active then NULL will be returned. + */ + char subProcessName[NV_SUBPROC_NAME_MAX_LENGTH]; +} NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE; + +/*! + * This struct represents the GPU monitoring perfmon sample. + */ +typedef struct NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE { + /*! + * Base GPU monitoring sample. + */ + NV_DECLARE_ALIGNED(NV2080_CTRL_GPUMON_SAMPLE base, 8); + /*! + * FB bandwidth utilization sample. + */ + NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE fb; + /*! + * GR utilization sample. + */ + NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE gr; + /*! + * NV ENCODER utilization sample. + */ + NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvenc; + /*! + * NV DECODER utilization sample. + */ + NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvdec; +} NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE; + +/*! + * This struct represents the GPU monitoring samples of perfmon values that + * client wants the access to. + */ +#define NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM_MESSAGE_ID (0x83U) + +typedef NV2080_CTRL_GPUMON_SAMPLES NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM; + +/*! + * Number of GPU monitoring sample in their respective buffers. + */ +#define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL 72 + +#define NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_BUFFER_SIZE \ + NV_SIZEOF32(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE) * \ + NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL + +/*! + * NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2 + * + * This command returns perfmon gpu monitoring utilization samples. + * This command is not supported with SMC enabled. + * + * See NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM_V2 for documentation + * on the parameters. + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + * Note this is the same as NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES + * but without the embedded pointer. + * + */ +#define NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2 (0x20802096) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_MESSAGE_ID" */ + +/*! + * This structure represents the GPU monitoring samples of utilization values that + * the client wants access to. + */ +#define NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_MESSAGE_ID (0x96U) + +typedef struct NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS { + /*! + * Type of the sample, see NV2080_CTRL_GPUMON_SAMPLE_TYPE_* for reference. + */ + NvU8 type; + /*! + * Size of the buffer, this should be + * bufSize == NV2080_CTRL_*_GPUMON_SAMPLE_COUNT_* + * sizeof(derived type of NV2080_CTRL_GPUMON_SAMPLE). + */ + NvU32 bufSize; + /*! + * Number of samples in ring buffer. + */ + NvU32 count; + /*! + * tracks the offset of the tail in the circular queue array pSamples. + */ + NvU32 tracker; + /*! + * A circular queue with size == bufSize. + * + * @note This circular queue wraps around after 10 seconds of sampling, + * and it is clients' responsibility to query within this time frame in + * order to avoid losing samples. + * @note With one exception, this queue contains last 10 seconds of samples + * with tracker poiniting to oldest entry and entry before tracker as the + * newest entry. Exception is when queue is not full (i.e. tracker is + * pointing to a zeroed out entry), in that case valid entries are between 0 + * and tracker. + * @note Clients can store tracker from previous query in order to provide + * samples since last read. + */ + NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE samples[NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL], 8); +} NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS; + +/* + * NV2080_CTRL_CMD_PERF_GPU_IS_IDLE + * + * This command notifies RM to make p state switching aggressive by setting + * required limiting factors to speed up GC6 Entry initiation. + * + * prevPstate [out] + * This parameter will contain the pstate before the switch was initiated + * + * Possible status return values are: + * NV_OK : If P State Switch is successful + * NV_INVALID_STATE : If unable to access P State structure + * NVOS_STATUS_ERROR : If P State Switch is unsuccessful + */ +#define NV2080_CTRL_CMD_PERF_GPU_IS_IDLE (0x20802089) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS_MESSAGE_ID (0x89U) + +typedef struct NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS { + NvU32 prevPstate; + NvU32 action; +} NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS; + +#define NV2080_CTRL_PERF_GPU_IS_IDLE_TRUE (0x00000001) +#define NV2080_CTRL_PERF_GPU_IS_IDLE_FALSE (0x00000002) + +/* + * NV2080_CTRL_CMD_PERF_AGGRESSIVE_PSTATE_NOTIFY + * + * This command is for the KMD Aggressive P-state feature. + * + * bGpuIsIdle [in] + * When true, applies cap to lowest P-state/GPCCLK. When false, releases cap. + * idleTimeUs [in] + * The amount of time (in microseconds) the GPU was idle since previous + * call, part of the GPU utilization data from KMD. + * busyTimeUs [in] + * The amount of time (in microseconds) the GPU was not idle since + * previous call, part of the GPU utilization data from KMD. + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + + +#define NV2080_CTRL_CMD_PERF_AGGRESSIVE_PSTATE_NOTIFY (0x2080208f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS_MESSAGE_ID (0x8FU) + +typedef struct NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS { + NvBool bGpuIsIdle; + NvBool bRestoreToMax; + NV_DECLARE_ALIGNED(NvU64 idleTimeUs, 8); + NV_DECLARE_ALIGNED(NvU64 busyTimeUs, 8); +} NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS; + + +/* _ctrl2080perf_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h new file mode 100644 index 0000000..8eb6c01 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080perf_cf.finn +// + + +/* _ctrl2080perf_cf_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h new file mode 100644 index 0000000..0a3e6b2 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.finn +// + + + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h new file mode 100644 index 0000000..fa476b5 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h @@ -0,0 +1,67 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080pmgr.finn +// + + + +#define NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED 0U +#define NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED 1U +#define NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_APPLICABLE 2U + +/*! + * NV2080_CTRL_PMGR_MODULE_INFO_PARAMS + * + * This provides information about different module properties + * + * moduleId[OUT] + * - This is a static HW identifier that is unique for each module on a given baseboard. + * For non-baseboard products this would always be 0. + * nvswitchSupport[OUT] + * - NVSwitch present or not. Possible values are + * NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED + * NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED + * NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_APPLICABLE + */ +#define NV2080_CTRL_PMGR_MODULE_INFO_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_PMGR_MODULE_INFO_PARAMS { + NvU32 moduleId; + NvU8 nvswitchSupport; +} NV2080_CTRL_PMGR_MODULE_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_PMGR_GET_MODULE_INFO + * + * Control call to query the subdevice module INFO. + * + */ +#define NV2080_CTRL_CMD_PMGR_GET_MODULE_INFO (0x20802609) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PMGR_INTERFACE_ID << 8) | NV2080_CTRL_PMGR_MODULE_INFO_PARAMS_MESSAGE_ID" */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080pmumon.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080pmumon.h new file mode 100644 index 0000000..53cb620 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080pmumon.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080pmumon.finn +// + + + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080power.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080power.h new file mode 100644 index 0000000..2d01ed5 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080power.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080power.finn +// + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h new file mode 100644 index 0000000..e2471c3 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h @@ -0,0 +1,368 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080rc.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* + * NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM + * + * This command returns data read from the specified virtual memory address for + * the associated subdevice. + * + * hChannel + * This parameter specifies the channel object handle from which the virtual + * memory range applies. + * virtAddress + * This parameter specifies the GPU base virtual memory address from which data should + * be read. The amount of data read is specified by the bufferSize parameter. + * bufferPtr + * This parameter specifies the buffer address in the caller's address space into which + * the data is to be returned. The address must be aligned on an 8-byte boundary. + * The buffer must be at least as big as the value specified bufferSize parameter (in bytes). + * bufferSize + * This parameter specifies the size of the buffer referenced by the bufferPtr parameter. + * This parameter also indicates the total number of bytes to be returned. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_XLATE + */ +#define NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS { + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 virtAddress, 8); + NV_DECLARE_ALIGNED(NvP64 bufferPtr, 8); + NvU32 bufferSize; +} NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS; + +#define NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM (0x20802204) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_RC_GET_ERROR_COUNT + * + * This command returns the number of RC errors. + * + * errorCount + * Number of RC errors. + * + * Note: If SMC is enabled, mig/monitor capability must be acquired to query + * aggregate information. Otherwise, the control call returns + * NV_ERR_INSUFFICIENT_PERMISSIONS. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INSUFFICIENT_PERMISSIONS. + */ +#define NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS { + NvU32 errorCount; +} NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS; + +#define NV2080_CTRL_CMD_RC_GET_ERROR_COUNT (0x20802205) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_RC_ERROR_PARAMS_BUFFER_SIZE (0x2000) /* finn: Evaluated from "(8 * 1024)" */ + +#define NV2080_CTRL_CMD_RC_GET_ERROR (0x20802206) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x6" */ + +/* + * NV2080_CTRL_CMD_RC_GET_ERROR_V2 + * + * This command returns an error element in the RC error list. + * + * whichBuffer + * Which Error to return (0 is oldest) + * outputRecordSize + * Output Size of Buffer -- Zero if error record doesn't exist + * recordBuffer + * buffer + * + * Note: If SMC is enabled, mig/monitor capability must be acquired to query + * aggregate information. Otherwise, the control call returns + * NV_ERR_INSUFFICIENT_PERMISSIONS. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INSUFFICIENT_PERMISSIONS. + * + */ + +#define NV2080_CTRL_RC_GET_ERROR_V2_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV2080_CTRL_RC_GET_ERROR_V2_PARAMS { + + NvU32 whichBuffer; // [IN] - which error to return (0 is oldest) + NvU32 outputRecordSize; // [OUT] + NvU8 recordBuffer[NV2080_CTRL_RC_ERROR_PARAMS_BUFFER_SIZE]; +} NV2080_CTRL_RC_GET_ERROR_V2_PARAMS; + +#define NV2080_CTRL_CMD_RC_GET_ERROR_V2 (0x20802213) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_GET_ERROR_V2_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_RC_SET_CLEAN_ERROR_HISTORY + * + * This command cleans error history. + * + * This command has no input parameters. + * + * Possible status values returned are: + * NV_OK + */ + +#define NV2080_CTRL_CMD_RC_SET_CLEAN_ERROR_HISTORY (0x20802207) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x7" */ + +/* + * NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO + * + * This command returns information about the RC watchdog. + * + * watchdogStatusFlags + * This output parameter is a combination of one or more of the following: + * + * NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_NONE + * This is the value of watchdogStatusFlags if no flags are set. + * + * NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_DISABLED + * This means that the watchdog is disabled. + * + * NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_RUNNING + * This means that the watchdog is running. + * + * NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_INITIALIZED + * This means that the watchdog has been initialized. + * + * A typical result would be either "running and initialized", or + * "disabled". However, "initialized, but not running, and not disabled" + * is also quite reasonable (if the computer is hibernating, for example). + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS { + NvU32 watchdogStatusFlags; +} NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS; + +#define NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO (0x20802209) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS_MESSAGE_ID" */ + +/* valid values for watchdogStatusFlags */ +#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_NONE (0x00000000) +#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_DISABLED (0x00000001) +#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_RUNNING (0x00000002) +#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_INITIALIZED (0x00000004) + +/* + * NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG + * + * This command disables the RC watchdog, if possible. + * If, however, another RM client has already explicitly (via NV2080 call) enabled + * the RC watchdog, then this method returns NV_ERR_STATE_IN_USE. + * + * This command, if successful, will prevent other clients from enabling the + * watchdog until the calling RM client releases its request with + * NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS or frees its NV20_SUBDEVICE. + * + * See NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG for disabling the watchdog + * without preventing other clients from enabling it. + * + * Possible status return values are: + * NV_OK + * NV_ERR_STATE_IN_USE + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG (0x2080220a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xA" */ + +/* + * NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG + * + * This command enables the RC watchdog, if possible. + * If, however, another RM client has already explicitly (via NV2080 call) disabled + * the RC watchdog, then this method returns NV_ERR_STATE_IN_USE. + * + * Possible status return values are: + * NV_OK + * NV_ERR_STATE_IN_USE + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG (0x2080220b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xB" */ + +/* + * NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS + * + * This command releases all of the RM client's outstanding requests to enable + * or disable the watchdog. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS (0x2080220c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xC" */ + +/* + * NV2080_CTRL_CMD_SET_RC_RECOVERY/NV2080_CTRL_CMD_GET_RC_RECOVERY + * + * This command disables/enables RC recovery. + * + * rcEnable + * NV2080_CTRL_CMD_SET_RC_RECOVERY_DISABLED + * Disable robust channel recovery. + * + * NV2080_CTRL_CMD_SET_RC_RECOVERY_ENABLED + * Enable robust channel recovery with default breakpoint handling. + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +typedef struct NV2080_CTRL_CMD_RC_RECOVERY_PARAMS { + NvU32 rcEnable; +} NV2080_CTRL_CMD_RC_RECOVERY_PARAMS; + +#define NV2080_CTRL_CMD_SET_RC_RECOVERY (0x2080220d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xD" */ + +#define NV2080_CTRL_CMD_GET_RC_RECOVERY (0x2080220e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xE" */ + +/* valid values for rcEnable */ +#define NV2080_CTRL_CMD_RC_RECOVERY_DISABLED (0x00000000) +#define NV2080_CTRL_CMD_RC_RECOVERY_ENABLED (0x00000001) + +/* + * NV2080_CTRL_CMD_TDR_SET_TIMEOUT_STATE + * + * This command can be used to set TDR timeout state. + * + * It can be used to indicate that a timeout has occurred and that a GPU + * reset will start. It can also be used to indicate that the reset has + * completed along with the corresponding complition status. + * + * cmd + * This parameter is used to indicate the stage of the TDR recovery + * process. Legal values for this parameter are: + * NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_BEGIN + * This value indicates that TDR recovery is about to begin. + * NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END + * This value indicates that TDR recovery has completed. + * + * status + * This parameter is valid when the cmd parameter is set to + * NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END. It is used + * to specify the completion status of the TDR recovery. Legal + * values for this parameter include: + * NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_FAIL + * This value indicates the recovery failed. + * NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_SUCCESS + * This value indicates the recovery succeeded. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_COMMAND + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_TDR_SET_TIMEOUT_STATE (0x2080220f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS { + NvU32 cmd; + NvS32 status; +} NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS; + +/* valid cmd values */ +#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_BEGIN (0x00000000) +#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END (0x00000001) + +/* valid status values */ +#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_SUCCESS (0x00000000) +#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_FAIL (0x00000001) + +/* + * NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG + * + * This command disables the RC watchdog, similarly to how + * NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG does. However, unlike that command, this + * command will not prevent another RM client from explicitly enabling the RC + * watchdog with NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG. + * + * Possible status return values are: + * NV_OK + * NV_ERR_STATE_IN_USE + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG (0x20802210) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x10" */ + +/* + * NV2080_CTRL_CMD_GET_RC_INFO/NV2080_CTRL_CMD_SET_RC_INFO + * + * This command can be used to set robust channel parameters. + * + * rcMode + * NV2080_CTRL_CMD_SET_RC_INFO_MODE_DISABLE + * Disable robust channel operation. + * + * NV2080_CTRL_CMD_SET_RC_INFO_MODE_ENABLE + * Enable robust channel operation. + * + * rcBreak + * NV2080_CTRL_CMD_SET_RC_INFO_BREAK_DISABLE + * Disable breakpoint handling during robust channel operation. + * + * NV2080_CTRL_CMD_SET_RC_INFO_BREAK_ENABLE + * Enable breakpoint handling during robust channel operation. + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +typedef struct NV2080_CTRL_CMD_RC_INFO_PARAMS { + NvU32 rcMode; + NvU32 rcBreak; +} NV2080_CTRL_CMD_RC_INFO_PARAMS; + +#define NV2080_CTRL_CMD_SET_RC_INFO (0x20802211) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x11" */ + +#define NV2080_CTRL_CMD_GET_RC_INFO (0x20802212) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x12" */ + +/* valid rcMode values */ +#define NV2080_CTRL_CMD_RC_INFO_MODE_DISABLE (0x00000000) +#define NV2080_CTRL_CMD_RC_INFO_MODE_ENABLE (0x00000001) + +/* valid rcBreak values */ +#define NV2080_CTRL_CMD_RC_INFO_BREAK_DISABLE (0x00000000) +#define NV2080_CTRL_CMD_RC_INFO_BREAK_ENABLE (0x00000001) + +/* _ctrl2080rc_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080spi.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080spi.h new file mode 100644 index 0000000..448723c --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080spi.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080spi.finn +// + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080thermal.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080thermal.h new file mode 100644 index 0000000..abe66ef --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080thermal.h @@ -0,0 +1,30 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080thermal.finn +// + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h new file mode 100644 index 0000000..d018e20 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h @@ -0,0 +1,233 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2008-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080tmr.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_TIMER related control commands and parameters */ + +/* + * NV2080_CTRL_CMD_TIMER_SCHEDULE + * + * This command schedules a GPU timer event to fire at the specified time interval. + * Can be called without API & GPU locks if NVOS54_FLAGS_IRQL_RAISED and + * NVOS54_FLAGS_LOCK_BYPASS are set in NVOS54_PARAMETERS.flags + * + * time_nsec + * This parameter specifies the time in nanoseconds at which the GPU timer + * event is to fire. + * flags + * This parameter determines the interpretation of the value specified by + * the time_nsec parameter: + * NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_ABS + * This flag indicates that time_nsec is in absolute time. + * NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_REL + * This flag indicates that time_nsec is in relative time. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_TIMER_SCHEDULE (0x20800401) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 time_nsec, 8); + NvU32 flags; +} NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS; + +/* valid flag values */ +#define NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME 0:0 +#define NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_ABS (0x00000000) +#define NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_REL (0x00000001) + +/* + * NV2080_CTRL_CMD_TIMER_CANCEL + * + * This command cancels any pending timer events initiated with the + * NV2080_CTRL_CMD_TIMER_SCHEDULE command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_TIMER_CANCEL (0x20800402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | 0x2" */ + +/* + * NV2080_CTRL_CMD_TIMER_GET_TIME + * + * This command returns the current GPU timer value. The current time is + * expressed in elapsed nanoseconds since 00:00 GMT, January 1, 1970 + * (zero hour) with a resolution of 32 nanoseconds. + * + * Can be called without API & GPU locks if NVOS54_FLAGS_IRQL_RAISED and + * NVOS54_FLAGS_LOCK_BYPASS are set in NVOS54_PARAMETERS.flags + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_TIMER_GET_TIME (0x20800403) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_TIMER_GET_TIME_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_TIMER_GET_TIME_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_TIMER_GET_TIME_PARAMS { + NV_DECLARE_ALIGNED(NvU64 time_nsec, 8); +} NV2080_CTRL_TIMER_GET_TIME_PARAMS; + +/* + * NV2080_CTRL_CMD_TIMER_GET_REGISTER_OFFSET + * + * The command returns the offset of the timer registers, so that clients may + * map them directly. + * + * Possible status values returned are: + * NV_OK + */ + +#define NV2080_CTRL_CMD_TIMER_GET_REGISTER_OFFSET (0x20800404) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS { + NvU32 tmr_offset; +} NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS; + +/* + * NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE + * + * This structure describes the information obtained with + * NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO command. + * + * gpuTime + * GPU time is the value of GPU global timer (PTIMER) with a resolution + * of 32 nano seconds. + * cpuTime + * CPU time. Resolution of the cpu time depends on its source. Refer to + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_* for more information. + + */ +typedef struct NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE { + NV_DECLARE_ALIGNED(NvU64 cpuTime, 8); + NV_DECLARE_ALIGNED(NvU64 gpuTime, 8); +} NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE; + + +/* + * NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO + * + * This command returns correlation information between GPU time and CPU time + * for a given CPU clock type. + * + * cpuClkId + * This parameter specifies the source of the CPU clock. Legal values for + * this parameter include: + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME + * This clock id will provide real time in microseconds since + * 00:00:00 UTC on January 1, 1970. + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API + * This clock id will provide time stamp that is constant-rate, high + * precision using platform API that is also available in the user mode. + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC + * This clock id will provide time stamp using CPU's time stamp counter. + * + * sampleCount + * This field specifies the number of clock samples to be taken. + * This value cannot exceed NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES. + * + * samples + * This field returns an array of requested samples. Refer to + * NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE to get details about each entry + * in the array. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO (0x20800406) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES 16 + +#define NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS { + NvU8 cpuClkId; + NvU8 sampleCount; + NV_DECLARE_ALIGNED(NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE samples[NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES], 8); +} NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS; + +/* Legal cpuClkId values */ +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME (0x00000001) +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC (0x00000002) +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API (0x00000003) +/*! + * NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ + * + * This command changes the frequency at which Graphics Engine time stamp is + * updated. Frequency can either be set to max or restored to default. + * Clients can independently use this call to increase the timer frequency + * as a global reference count is maintained for requests to Max frequency. + * Client is assured that the system stays in this state till the requested + * client releases the state or is killed. Timer frequency will automatically + * be restored to default when there is no pending request to increase. + * + * Note that recursive requests for the same state from the same client + * are considered invalid. + * + * bSetMaxFreq + * Set to NV_TRUE if GR tick frequency needs to be set to Max. + * + * See @ref NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS for + * documentation of parameters. + * + * Possible status values returned are + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_STATE_IN_USE + * NV_ERR_INVALID_OPERATION + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ (0x20800407) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID" */ + +/*! + * This struct contains bSetMaxFreq flag. + */ +#define NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS { + NvBool bSetMaxFreq; +} NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS; + +/* _ctrl2080tmr_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h new file mode 100644 index 0000000..e4995b8 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080ucodefuzzer.finn +// + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h new file mode 100644 index 0000000..782e182 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h @@ -0,0 +1,190 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080unix.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" + +/* NV20_SUBDEVICE_XX OS control commands and parameters */ + +/* + * NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT + * + * This command increases or decreases the value of the per-GPU GC6 blocker + * refCount used by Linux kernel clients to prevent the GPU from entering GC6. + * + * When the refCount is non-zero, the GPU cannot enter GC6. When the refCount + * transitions from zero to non-zero as a result of this command, the GPU will + * automatically come out of GC6. + * + * action Whether to increment or decrement the value of the refCount. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT (0x20803d01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS { + NvU32 action; +} NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS; + +// Possible values for action +#define NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_INC (0x00000001) +#define NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_DEC (0x00000002) + +/* + * NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF + * + * RM by default allows GCOFF but when the X driver disallows to enter in GCOFF + * then this rmcontrol sets flag as NV_FALSE and if it allows to enter in GCOFF + * then the flag is set as NV_TRUE. + * + * action Whether to allow or disallow the user mode clients to enter in GCOFF. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF (0x20803d02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS { + NvU32 action; +} NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS; + +// Possible values for action +#define NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_ALLOW (0x00000001) +#define NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_DISALLOW (0x00000002) + +/* + * NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER + * + * GPU can have integrated HDA (High Definition Audio) controller which + * can be in active or suspended state during dynamic power management. + * This command will perform HDA controller wakeup (if bEnter is false) or + * suspend (if bEnter is true). + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER (0x20803d03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS { + NvBool bEnter; +} NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS; + +/* + * NV2080_CTRL_CMD_OS_UNIX_INSTALL_PROFILER_HOOKS + * + * Initialize cyclestats HWPM support in the kernel. This will set up a callback + * event for the channel indicated by hNotifierResource. This callback will execute + * perf register read / write commands enqueued in the shared buffer indicated by + * hNotifyDataMemory. Only one client may use HWPM functionality at a time. + * + * Additionally, if perfmonIdCount is greater than zero, mode-e HWPM streaming into + * the buffer indicated by hSnapshotMemory will be initialized (but not turned on). + * Data will be copied into the provided buffer every 10ms, or whenever a + * NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER command is issued. + */ +#define NV2080_CTRL_CMD_OS_UNIX_INSTALL_PROFILER_HOOKS (0x20803d04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS { + NvHandle hNotifierResource; + NvU32 notifyDataSize; + NvHandle hNotifyDataMemory; + NvU32 perfmonIdCount; + NvU32 snapshotBufferSize; + NvHandle hSnapshotMemory; +} NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS; + +/* + * NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER + * + * Immediately copies any pending mode-e HWPM data into the previously + * installed snapshot buffer instead of waiting for the timer. + */ +#define NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER (0x20803d05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | 0x5" */ + +/* + * NV2080_CTRL_CMD_OS_UNIX_STOP_PROFILER + * + * Stop the timer responsible for copying mode-e HWPM data to the snapshot buffer. + * The snapshot buffer must not be freed by the client before this command is issued. + */ +#define NV2080_CTRL_CMD_OS_UNIX_STOP_PROFILER (0x20803d06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | 0x6" */ + +/* + * NV2080_CTRL_CMD_OS_UNIX_VIDMEM_PERSISTENCE_STATUS + * + * This command will be used by clients to check if the GPU video memory will + * be persistent during system suspend/resume cycle. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_OS_UNIX_VIDMEM_PERSISTENCE_STATUS (0x20803d07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS { + NvBool bVidmemPersistent; +} NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_OS_UNIX_UPDATE_TGP_STATUS + * + * This command will be used by clients to set restore TGP flag which will + * help to restore TGP limits when clients are destroyed. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_OS_UNIX_UPDATE_TGP_STATUS (0x20803d08) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS { + NvBool bUpdateTGP; +} NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS; +/* _ctrl2080unix_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h new file mode 100644 index 0000000..a5a9db1 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h @@ -0,0 +1,42 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080vfe.finn +// + + + +/* _ctrl2080vfe_h_ */ +#include "nvfixedtypes.h" +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "ctrl/ctrl2080/ctrl2080boardobj.h" +#include "ctrl/ctrl2080/ctrl2080bios.h" + +/* --------------------------- Forward Defines ----------------------------- */ +/* --------------------------- VFE Variable -------------------------------- */ +/* --------------------------- VFE Equation -------------------------------- */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h new file mode 100644 index 0000000..2da2c80 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h @@ -0,0 +1,407 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080vgpumgrinternal.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "ctrl/ctrla081.h" + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK + * + * This command is used to bootload GSP VGPU plugin task. + * Can be called only with SR-IOV and with VGPU_GSP_PLUGIN_OFFLOAD feature. + * + * dbdf - domain (31:16), bus (15:8), device (7:3), function (2:0) + * gfid - Gfid + * vgpuType - The Type ID for VGPU profile + * vmPid - Plugin process ID of vGPU guest instance + * swizzId - SwizzId + * numChannels - Number of channels + * numPluginChannels - Number of plugin channels + * bDisableSmcPartitionRestore - If set to true, SMC default execution partition + * save/restore will not be done in host-RM + * guestFbPhysAddrList - list of VMMU segment aligned physical address of guest FB memory + * guestFbLengthList - list of guest FB memory length in bytes + * pluginHeapMemoryPhysAddr - plugin heap memory offset + * pluginHeapMemoryLength - plugin heap memory length in bytes + * bDeviceProfilingEnabled - If set to true, profiling is allowed + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK (0x20804001) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MAX_VMMU_SEGMENTS 384 + +/* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */ +#define NV2080_GPU_MAX_ENGINES 0x3e + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS { + NvU32 dbdf; + NvU32 gfid; + NvU32 vgpuType; + NvU32 vmPid; + NvU32 swizzId; + NvU32 numChannels; + NvU32 numPluginChannels; + NvU32 chidOffset[NV2080_GPU_MAX_ENGINES]; + NvBool bDisableDefaultSmcExecPartRestore; + NvU32 numGuestFbSegments; + NV_DECLARE_ALIGNED(NvU64 guestFbPhysAddrList[NV2080_CTRL_MAX_VMMU_SEGMENTS], 8); + NV_DECLARE_ALIGNED(NvU64 guestFbLengthList[NV2080_CTRL_MAX_VMMU_SEGMENTS], 8); + NV_DECLARE_ALIGNED(NvU64 pluginHeapMemoryPhysAddr, 8); + NV_DECLARE_ALIGNED(NvU64 pluginHeapMemoryLength, 8); + NV_DECLARE_ALIGNED(NvU64 ctrlBuffOffset, 8); + NvBool bDeviceProfilingEnabled; +} NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK + * + * This command is used to shutdown GSP VGPU plugin task. + * Can be called only with SR-IOV and with VGPU_GSP_PLUGIN_OFFLOAD feature. + * + * gfid - Gfid + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK (0x20804002) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS { + NvU32 gfid; +} NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE + * + * This command is used to add a new vGPU config to the pGPU in physical RM. + * Unlike NVA081_CTRL_CMD_VGPU_CONFIG_SET_INFO, it does no validation + * and is only to be used internally. + * + * discardVgpuTypes [IN] + * This parameter specifies if existing vGPU configuration should be + * discarded for given pGPU + * + * vgpuInfoCount [IN] + * This parameter specifies the number of entries of virtual GPU type +* information + * + * vgpuInfo [IN] + * This parameter specifies virtual GPU type information + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE (0x20804003) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS { + NvBool discardVgpuTypes; + NvU32 vgpuInfoCount; + NV_DECLARE_ALIGNED(NVA081_CTRL_VGPU_INFO vgpuInfo[NVA081_MAX_VGPU_TYPES_PER_PGPU], 8); +} NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS; + +/* + * NV2080_GUEST_VM_INFO + * + * This structure represents vGPU guest's (VM's) information + * + * vmPid [OUT] + * This param specifies the vGPU plugin process ID + * guestOs [OUT] + * This param specifies the vGPU guest OS type + * migrationProhibited [OUT] + * This flag indicates whether migration is prohibited for VM or not + * guestNegotiatedVgpuVersion [OUT] + * This param specifies the vGPU version of guest driver after negotiation + * frameRateLimit [OUT] + * This param specifies the current value of FRL set for guest + * licensed [OUT] + * This param specifies whether the VM is Unlicensed/Licensed + * licenseState [OUT] + * This param specifies the current state of the GRID license state machine + * licenseExpiryTimestamp [OUT] + * License expiry time in seconds since UNIX epoch + * licenseExpiryStatus [OUT] + * License expiry status + * guestDriverVersion [OUT] + * This param specifies the driver version of the driver installed on the VM + * guestDriverBranch [OUT] + * This param specifies the driver branch of the driver installed on the VM + * guestVmInfoState [OUT] + * This param stores the current state of guest dependent fields + * + */ +typedef struct NV2080_GUEST_VM_INFO { + NvU32 vmPid; + NvU32 guestOs; + NvU32 migrationProhibited; + NvU32 guestNegotiatedVgpuVersion; + NvU32 frameRateLimit; + NvBool licensed; + NvU32 licenseState; + NvU32 licenseExpiryTimestamp; + NvU8 licenseExpiryStatus; + NvU8 guestDriverVersion[NVA081_VGPU_STRING_BUFFER_SIZE]; + NvU8 guestDriverBranch[NVA081_VGPU_STRING_BUFFER_SIZE]; + GUEST_VM_INFO_STATE guestVmInfoState; +} NV2080_GUEST_VM_INFO; + +/* + * NV2080_GUEST_VGPU_DEVICE + * + * This structure represents host vgpu device's (assigned to VM) information + * + * gfid [OUT] + * This parameter specifies the gfid of vGPU assigned to VM. + * vgpuPciId [OUT] + * This parameter specifies vGPU PCI ID + * vgpuDeviceInstanceId [OUT] + * This paramter specifies the vGPU device instance per VM to be used for supporting + * multiple vGPUs per VM. + * fbUsed [OUT] + * This parameter specifies FB usage in bytes + * eccState [OUT] + * This parameter specifies the ECC state of the virtual GPU. + * One of NVA081_CTRL_ECC_STATE_xxx values. + * bDriverLoaded [OUT] + * This parameter specifies whether driver is loaded on this particular vGPU. + * + */ +typedef struct NV2080_HOST_VGPU_DEVICE { + NvU32 gfid; + NV_DECLARE_ALIGNED(NvU64 vgpuPciId, 8); + NvU32 vgpuDeviceInstanceId; + NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); + NvU32 encoderCapacity; + NvU32 eccState; + NvBool bDriverLoaded; +} NV2080_HOST_VGPU_DEVICE; + +/* + * NV2080_VGPU_GUEST + * + * This structure represents a vGPU guest + * + */ +typedef struct NV2080_VGPU_GUEST { + NV2080_GUEST_VM_INFO guestVmInfo; + NV_DECLARE_ALIGNED(NV2080_HOST_VGPU_DEVICE vgpuDevice, 8); +} NV2080_VGPU_GUEST; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU + * + * This command enumerates list of vGPU guest instances per pGpu + * + * numVgpu [OUT] + * This parameter specifies the number of virtual GPUs created on this physical GPU + * + * vgpuGuest [OUT] + * This parameter specifies an array containing guest vgpu's information for + * all vGPUs created on this physical GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU (0x20804004) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS { + NvU32 numVgpu; + NV_DECLARE_ALIGNED(NV2080_VGPU_GUEST vgpuGuest[NVA081_MAX_VGPU_PER_PGPU], 8); +} NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO + * + * This command is used clear guest vm info. It should be used when + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE + * is called with NVA081_NOTIFIERS_EVENT_VGPU_GUEST_DESTROYED state. + * + * gfid [IN] + * This parameter specifies the gfid of vGPU assigned to VM. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO (0x20804005) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS { + NvU32 gfid; +} NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE + * + * This command is used to get the FB usage of all vGPU instances running on a GPU. + * + * vgpuCount [OUT] + * This field specifies the number of vGPU devices for which FB usage is returned. + * vgpuFbUsage [OUT] + * This is an array of type NV2080_VGPU_FB_USAGE, which contains a list of vGPU gfid + * and their corresponding FB usage in bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE (0x20804006) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID" */ + +typedef struct NV2080_VGPU_FB_USAGE { + NvU32 gfid; + NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); +} NV2080_VGPU_FB_USAGE; + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS { + NvU32 vgpuCount; + NV_DECLARE_ALIGNED(NV2080_VGPU_FB_USAGE vgpuFbUsage[NVA081_MAX_VGPU_PER_PGPU], 8); +} NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY + * + * This command is used to set vGPU instance's (represented by gfid) encoder Capacity. + * + * gfid [IN] + * This parameter specifies the gfid of vGPU assigned to VM. + * encoderCapacity [IN] + * Encoder capacity value from 0 to 100. Value of 0x00 indicates encoder performance + * may be minimal for this GPU and software should fall back to CPU-based encode. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY (0x20804007) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS { + NvU32 gfid; + NvU32 encoderCapacity; +} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP + * + * This command is used to cleanup all the GSP VGPU plugin task allocated resources after its shutdown. + * Can be called only with SR-IOV and with VGPU_GSP_PLUGIN_OFFLOAD feature. + * + * gfid [IN] + * This parameter specifies the gfid of vGPU assigned to VM. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP (0x20804008) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS { + NvU32 gfid; +} NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS; + +#define NV2080_CTRL_MAX_NVU32_TO_CONVERTED_STR_LEN 8 +#define NV2080_CTRL_MAX_GPC_COUNT 32 + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING + * + * Reroutes kvgpumgrGetPgpuFSEncoding to vgpuMgrGetPgpuFSEncoding. + * + * pgpuString [OUT] + * Resulting PGPU string + * pgpuStringSize + * PGPU string size + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING (0x20804009) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS { + NvU8 pgpuString[NVA081_PGPU_METADATA_STRING_SIZE]; + NvU32 pgpuStringSize; +} NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT + * + * Reroutes kvgpumgrCheckPgpuMigrationSupport to vgpuMgrCheckPgpuMigrationSupport. + * + * bIsMigrationSupported [OUT] + * Resulting status of the migration support + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT (0x2080400a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS { + NvBool bIsMigrationSupported; +} NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG + * + * Sets vgpu manager parameters. This control is used after GSP initialization. + * + * bSupportHeterogeneousTimeSlicedVgpuTypes [IN] + * Enable/disable heterogeneous time-sliced vgpu types + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG (0x2080400b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS { + NvBool bSupportHeterogeneousTimeSlicedVgpuTypes; +} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS; + +/* _ctrl2080vgpumgrinternal_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h new file mode 100644 index 0000000..eacd596 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h @@ -0,0 +1,38 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080volt.finn +// + + + +/* _ctrl2080volt_h_ */ + +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "ctrl/ctrl2080/ctrl2080boardobj.h" +#include "ctrl/ctrl2080/ctrl2080pmumon.h" + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f.h new file mode 100644 index 0000000..b526aa3 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f.finn +// + + + + +#include "ctrl/ctrlxxxx.h" +#include "ctrl208f/ctrl208fpower.h" +#include "ctrl208f/ctrl208ffifo.h" +#include "ctrl208f/ctrl208ffb.h" +#include "ctrl208f/ctrl208ffbio.h" + + +#include "ctrl208f/ctrl208fbif.h" +#include "ctrl208f/ctrl208fbus.h" +#include "ctrl208f/ctrl208fevent.h" +#include "ctrl208f/ctrl208fgpu.h" +#include "ctrl208f/ctrl208fgr.h" +#include "ctrl208f/ctrl208fclk.h" +#include "ctrl208f/ctrl208fpmgr.h" +#include "ctrl208f/ctrl208fdma.h" +#include "ctrl208f/ctrl208fmmu.h" + + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fbase.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fbase.h new file mode 100644 index 0000000..eb08864 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fbase.h @@ -0,0 +1,71 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fbase.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV20_SUBDEVICE_DIAG: diagnostic class control commands and parameters */ + +#define NV208F_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x208F, NV208F_CTRL_##cat, idx) + +/* Subdevice diag command categories (6bits) */ +#define NV208F_CTRL_RESERVED (0x00) +#define NV208F_CTRL_POWER (0x01) +#define NV208F_CTRL_THERMAL (0x02) +#define NV208F_CTRL_SEQ (0x03) +#define NV208F_CTRL_FIFO (0x04) +#define NV208F_CTRL_FB (0x05) +#define NV208F_CTRL_MC (0x06) +#define NV208F_CTRL_BIF (0x07) +#define NV208F_CTRL_CLK (0x08) +#define NV208F_CTRL_PERF (0x09) +#define NV208F_CTRL_FBIO (0x0A) +#define NV208F_CTRL_MMU (0x0B) +#define NV208F_CTRL_PMU (0x0C) +#define NV208F_CTRL_EVENT (0x10) +#define NV208F_CTRL_GPU (0x11) +#define NV208F_CTRL_GR (0x12) +#define NV208F_CTRL_PMGR (0x13) +#define NV208F_CTRL_DMA (0x14) +// const NV208F_CTRL_TMR = (0x15); // not supported +#define NV208F_CTRL_RMFS (0x16) +#define NV208F_CTRL_GSPMSGTIMING (0x17) +#define NV208F_CTRL_BUS (0x18) + +/* + * NV208F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV208F_CTRL_CMD_NULL (0x208f0000) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrl208fbase_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h new file mode 100644 index 0000000..3499ef9 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h @@ -0,0 +1,194 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fbif.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* +* NV208F_CTRL_CMD_BIF_PBI_WRITE_COMMAND +* +* Control command to send a write command to the Post Box Interface +* +* Parameters: +* +*cmdFuncId +* this specifies the function that needs to be performed on pbi +*data +* the data to be set in the data in register +* status +* this corresponds to pbi status register +* sysNotify +* this corresponds to system notify event, i.e. whether system +* needs to be notified of command completion +* drvNotify +* this corresponds to driver notify event, i.e. whether driver +* needs to be notified of command completion +* +* For the possible values of the above parameters refer rmpbicmdif.h +*/ +#define NV208F_CTRL_CMD_BIF_PBI_WRITE_COMMAND (0x208f0701) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_PBI_WRITE_COMMAND_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_BIF_PBI_WRITE_COMMAND_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV208F_CTRL_BIF_PBI_WRITE_COMMAND_PARAMS { + NvU8 cmdFuncId; + NvU32 data; + NvU8 status; + NvBool sysNotify; + NvBool drvNotify; +} NV208F_CTRL_BIF_PBI_WRITE_COMMAND_PARAMS; + +/* +* NV208F_CTRL_CMD_BIF_CONFIG_REG_READ +* This command is used to read any of the PBI registers in the config space +* +* Parameters: +* +* RegIndex +* Defines the index of the PBI register +* data +* Data that is read +*/ +#define NV208F_CTRL_CMD_BIF_CONFIG_REG_READ (0x208f0702) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_CONFIG_REG_READ_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_BIF_CONFIG_REG_READ_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV208F_CTRL_BIF_CONFIG_REG_READ_PARAMS { + NvU8 RegIndex; + NvU32 data; +} NV208F_CTRL_BIF_CONFIG_REG_READ_PARAMS; + +/* +* NV208F_CTRL_CMD_BIF_CONFIG_REG_WRITE +* This command is used to write any of the PBI registers in the config space +* +* Parameters: +* +* RegIndex +* Defines the index of the PBI register +* data +* Data that is to be written +*/ +#define NV208F_CTRL_CMD_BIF_CONFIG_REG_WRITE (0x208f0703) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_CONFIG_REG_WRITE_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_BIF_CONFIG_REG_WRITE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV208F_CTRL_BIF_CONFIG_REG_WRITE_PARAMS { + NvU8 RegIndex; + NvU32 data; +} NV208F_CTRL_BIF_CONFIG_REG_WRITE_PARAMS; + +/* +* NV208F_CTRL_CMD_BIF_INFO +* This command is used to read a bif property +* +* Parameters: +* +* index +* Defines the index of the property to read +* data +* Data that is read +*/ +#define NV208F_CTRL_CMD_BIF_INFO (0x208f0704) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_INFO_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_BIF_INFO_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV208F_CTRL_BIF_INFO_PARAMS { + NvU32 index; + NvU32 data; +} NV208F_CTRL_BIF_INFO_PARAMS; + +/* valid bif info index values */ +#define NV208F_CTRL_BIF_INFO_INDEX_L0S_ENABLED (0x00000000) +#define NV208F_CTRL_BIF_INFO_INDEX_L1_ENABLED (0x00000001) + +/* + * NV208F_CTRL_CMD_BIF_ECC_INJECT_ERROR + * + * This ctrl call injects PCI-E XPL-EP ECC errors. Please see the confluence + * page "ECC" for more information on ECC and ECC injection: + * + * Parameters: + * + * errorUnit + * Specifies the HW unit where the injection will occur. + * + * errorType + * Specifies whether the injected error will be correctable or uncorrectable. + * Correctable errors have no effect on running programs while uncorrectable + * errors will cause all channels to be torn down. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_BIF_ECC_INJECT_ERROR (0x208f0705) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */ + + + +#define NV208F_CTRL_BIF_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV208F_CTRL_BIF_ECC_INJECT_ERROR_PARAMS { + NvU8 errorType; + NvU8 errorUnit; +} NV208F_CTRL_BIF_ECC_INJECT_ERROR_PARAMS; + +/* + * NV208F_CTRL_CMD_BIF_ECC_INJECTION_SUPPORTED + * + * Reports if error injection is supported for XPL-EP + * + * bCorrectableSupported [out]: + * Boolean value that shows if correcatable errors can be injected. + * + * bUncorrectableSupported [out]: + * Boolean value that shows if uncorrecatable errors can be injected. + * + * Return values: + * NV_OK on success + * NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled. + * NV_ERR_NOT_SUPPORTED otherwise + * + * + */ +#define NV208F_CTRL_CMD_BIF_ECC_INJECTION_SUPPORTED (0x208f0706) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_BIF_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV208F_CTRL_BIF_ECC_INJECTION_SUPPORTED_PARAMS { + NvU8 errorUnit; + NvBool bCorrectableSupported; + NvBool bUncorrectableSupported; +} NV208F_CTRL_BIF_ECC_INJECTION_SUPPORTED_PARAMS; + +/* _ctrl208fbif_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fbus.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fbus.h new file mode 100644 index 0000000..11fd26e --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fbus.h @@ -0,0 +1,113 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fbus.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* + * NV208F_CTRL_CMD_BUS_IS_BAR1_VIRTUAL + * + * This command checks whether or not BAR1 is in virtual mode. + * This API is intended for internal testing only. + * + * bIsVirtual + * Whether or not Bar1 is in virtual mode. + */ +#define NV208F_CTRL_CMD_BUS_IS_BAR1_VIRTUAL (0x208f1801) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BUS_INTERFACE_ID << 8) | NV208F_CTRL_BUS_IS_BAR1_VIRTUAL_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_BUS_IS_BAR1_VIRTUAL_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV208F_CTRL_BUS_IS_BAR1_VIRTUAL_PARAMS { + NvBool bIsVirtual; +} NV208F_CTRL_BUS_IS_BAR1_VIRTUAL_PARAMS; + +/* + * NV208F_CTRL_CMD_BUS_ECC_INJECT_ERROR + * + * This ctrl call injects BUS ECC errors. Please see the confluence + * page "ECC" for more information on ECC and ECC injection: + * + * Parameters: + * + * location + * Specifies the BUS HW unit where the injection will occur. + * + * errorType + * Specifies whether the injected error will be correctable or uncorrectable. + * Correctable errors have no effect on running programs while uncorrectable + * errors will cause all channels to be torn down. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_BUS_ECC_INJECT_ERROR (0x208f1802) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BUS_INTERFACE_ID << 8) | NV208F_CTRL_BUS_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */ + + + +#define NV208F_CTRL_BUS_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV208F_CTRL_BUS_ECC_INJECT_ERROR_PARAMS { + NvU8 errorType; + NvU8 errorUnit; +} NV208F_CTRL_BUS_ECC_INJECT_ERROR_PARAMS; + +/* + * NV208F_CTRL_CMD_BUS_ECC_INJECTION_SUPPORTED + * + * Reports if error injection is supported for BUS units + * + * bCorrectableSupported [out]: + * Boolean value that shows if correcatable errors can be injected. + * + * bUncorrectableSupported [out]: + * Boolean value that shows if uncorrecatable errors can be injected. + * + * Return values: + * NV_OK on success + * NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled. + * NV_ERR_NOT_SUPPORTED otherwise + * + * + */ +#define NV208F_CTRL_CMD_BUS_ECC_INJECTION_SUPPORTED (0x208f1803) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BUS_INTERFACE_ID << 8) | NV208F_CTRL_BUS_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_BUS_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV208F_CTRL_BUS_ECC_INJECTION_SUPPORTED_PARAMS { + NvU8 errorUnit; + NvBool bCorrectableSupported; + NvBool bUncorrectableSupported; +} NV208F_CTRL_BUS_ECC_INJECTION_SUPPORTED_PARAMS; + +/* _ctrl208fbus_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fclk.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fclk.h new file mode 100644 index 0000000..450d881 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fclk.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fclk.finn +// + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fdma.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fdma.h new file mode 100644 index 0000000..a302d42 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fdma.h @@ -0,0 +1,92 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fdma.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* + * NV208F_CTRL_CMD_DMA_IS_SUPPORTED_SPARSE_VIRTUAL + * + * This command checks whether or not "sparse" virtual address ranges are + * supported for a given chip. This API is intended for debug-use only. + * + * bIsSupported + * Whether or not "sparse" virtual address ranges are supported. + */ +#define NV208F_CTRL_CMD_DMA_IS_SUPPORTED_SPARSE_VIRTUAL (0x208f1401) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_DMA_INTERFACE_ID << 8) | NV208F_CTRL_DMA_IS_SUPPORTED_SPARSE_VIRTUAL_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_DMA_IS_SUPPORTED_SPARSE_VIRTUAL_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV208F_CTRL_DMA_IS_SUPPORTED_SPARSE_VIRTUAL_PARAMS { + NvBool bIsSupported; +} NV208F_CTRL_DMA_IS_SUPPORTED_SPARSE_VIRTUAL_PARAMS; + +/* + * NV208F_CTRL_CMD_DMA_GET_VAS_BLOCK_DETAILS + * + * This command retrieves various details of the virtual address space block + * allocated from the virtual address space heap for the given virtual address. + * + * virtualAddress + * Virtual address to get information about. + * + * beginAddress + * Start address of the corresponding virtual address space block. + * + * endAddress + * End address (inclusive) of the corresponding virtual address space + * block. + * + * alignedAddress + * Aligned address of the corresponding virtual address space block. + * + * pageSize + * Page size of the virtual address space block. + * + * hVASpace + * Handle to an allocated VA space. If 0, it is assumed that the device's + * VA space should be used. + */ +#define NV208F_CTRL_CMD_DMA_GET_VAS_BLOCK_DETAILS (0x208f1402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_DMA_INTERFACE_ID << 8) | NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 virtualAddress, 8); + NV_DECLARE_ALIGNED(NvU64 beginAddress, 8); + NV_DECLARE_ALIGNED(NvU64 endAddress, 8); + NV_DECLARE_ALIGNED(NvU64 alignedAddress, 8); + NvU32 pageSize; + NvHandle hVASpace; +} NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS; + +/* _ctrl208fdma_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fevent.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fevent.h new file mode 100644 index 0000000..3777829 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fevent.h @@ -0,0 +1,93 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fevent.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* NV20_SUBDEVICE_DIAG event-related control commands and parameters */ + +/* + * NV208F_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * This command sets event notification state for the associated subdevice. + * This command requires that an instance of NV01_EVENT has been previously + * bound to the associated subdevice object. + * + * event + * This parameter specifies the type of event to which the specified + * action is to be applied. This parameter must specify a valid + * NV208F_NOTIFIERS value (see cl208f.h for more details) and should + * not exceed one less NV208F_NOTIFIERS_MAXCOUNT. + * action + * This parameter specifies the desired event notification action. + * Valid notification actions include: + * NV208F_CTRL_SET_EVENT_NOTIFICATION_DISABLE + * This action disables event notification for the specified + * event for the associated subdevice object. + * NV208F_CTRL_SET_EVENT_NOTIFICATION_SINGLE + * This action enables single-shot event notification for the + * specified event for the associated subdevice object. + * NV208F_CTRL_SET_EVENT_NOTIFICATION_REPEAT + * This action enables repeated event notification for the specified + * event for the associated system controller object. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV208F_CTRL_CMD_EVENT_SET_NOTIFICATION (0x208f1001) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_EVENT_INTERFACE_ID << 8) | NV208F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV208F_CTRL_EVENT_SET_NOTIFICATION_PARAMS { + NvU32 event; + NvU32 action; +} NV208F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NV208F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NV208F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001) +#define NV208F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002) + +/* + * NV208F_CTRL_CMD_EVENT_SET_TRIGGER + * + * This command triggers a software event for the associated subdevice. + * This command accepts no parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV208F_CTRL_CMD_EVENT_SET_TRIGGER (0x208f1002) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_EVENT_INTERFACE_ID << 8) | 0x2" */ + +/* _ctrl208fevent_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h new file mode 100644 index 0000000..ec16916 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h @@ -0,0 +1,611 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208ffb.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* + * NV208F_CTRL_CMD_FB_GET_INFO + * + * This command returns fb engine information for the associated GPU. + * The client specifies what information to query through 'index' param. + * On success, the information is stored in the 'data' param. + * + * index + * Specify what information to query. Please see below for valid values of + * indexes for this command. + * data + * On success, this param will hold the data that the client queried for. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_FB_GET_INFO (0x208f0501) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV208F_CTRL_FB_GET_INFO_PARAMS { + NvU32 index; + NV_DECLARE_ALIGNED(NvU64 data, 8); +} NV208F_CTRL_FB_GET_INFO_PARAMS; + +/* valid fb info index values */ +#define NV208F_CTRL_FB_INFO_INDEX_FREE_CONTIG_COMPRESSION_SIZE (0x00000001) + +#define NV208F_CTRL_FB_INFO_INDEX_MAX NV208F_CTRL_FB_INFO_INDEX_FREE_CONTIG_COMPRESSION_SIZE + +/* + * NV208F_CTRL_CMD_FB_GET_ZBC_REFCOUNT + * + * This command gets the ZBC reference count associated with a given + * compression tag address. It is not supported on GPUs which support class + * GF100_ZBC_CLEAR as it is specific to a different hardware implementation. + * + * compTagAddress + * The input parameter indicating the compression tag address for which the + * associated ZBC refcount should be looked up. + * zbcRefCount + * An array of reference counts for the ZBC clear values associated with + * compTagAddress. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_FB_GET_ZBC_REFCOUNT (0x208f0505) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | 0x5" */ // Deprecated, removed form RM + +#define NV208F_CTRL_FB_GET_ZBC_REFCOUNT_MAX_REFCOUNTS 2 +typedef struct NV208F_CTRL_FB_GET_ZBC_REFCOUNT_PARAMS { + NvU32 compTagAddress; + NvU32 zbcRefCount[NV208F_CTRL_FB_GET_ZBC_REFCOUNT_MAX_REFCOUNTS]; +} NV208F_CTRL_FB_GET_ZBC_REFCOUNT_PARAMS; + +/* + * NV208F_CTRL_CMD_FB_CTRL_GPU_CACHE + * + * This command controls the state of a cache which all GPU memory accesses go + * through. If supported, it allows changing of the power state and the write + * mode. This is only supported when NV_VERIF_FEATURES is defined. An error + * will be returned if the requested combination of settings is not possible. + * + * writeMode + * Specifies the write mode of the cache. Possible values are defined in + * NV208F_CTRL_FB_CTRL_GPU_CACHE_WRITE_MODE. Passing _DEFAULT means to + * maintain the current write mode. It is illegal to change the write mode + * while the cache is disabled or in the same call as a request to disable + * it. + * powerState + * Specifies the power state of the cache. Possible values are defined in + * NV208F_CTRL_FB_CTRL_GPU_CACHE_POWER_STATE. Passing _DEFAULT means + * to maintain the current power state. + * rcmState + * Specifies the reduced cache mode of the cache. Possible values are + * defined in NV208F_CTRL_FB_CTRL_GPU_CACHE_RCM_STATE. Passing _DEFAULT + * means to maintain the current RCM state. + * vgaCacheMode + * Specifies whether or not to enable VGA out-of-cache mode. Possible + * values are defined in NV208F_CTRL_FB_CTRL_GPU_CACHE_VGA_MODE. Passing + * _DEFAULT means to maintain the current VGA caching mode. + * cacheReset + * Triggers a hardware reset of the cache. Possible values are defined in + * NV208F_CTRL_FB_CTRL_GPU_CACHE_CACHE_RESET. Passing _DEFAULT does + * nothing while passing _RESET clears all data in the cache. + * flags + * Contains flags to control the details of how transitions should be + * handled. Possible values are defined in + * NV208F_CTRL_FB_CTRL_GPU_CACHE_FLAGS. Passing _DEFAULT for any of + * the fields means to use the defaults specified by the Resource Manager. + * Note not all options are available for all transitions. Flags that are + * set but not applicable will be silently ignored. + * bypassMode + * (Fermi only) Specifies the bypass mode of the L2 cache. Normal GPU + * operation is _DISABLE. For TEST ONLY, setting _ENABLE enables a debug + * mode where all transactions miss in L2 and no writes are combined, + * essentially disabling the caching feature of the L2 cache. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV208F_CTRL_CMD_FB_CTRL_GPU_CACHE (0x208f0506) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_CTRL_GPU_CACHE_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV208F_CTRL_FB_CTRL_GPU_CACHE_PARAMS { + NvU32 writeMode; + NvU32 powerState; + NvU32 rcmState; + NvU32 vgaCacheMode; + NvU32 cacheReset; + NvU32 flags; + NvU32 bypassMode; +} NV208F_CTRL_FB_CTRL_GPU_CACHE_PARAMS; + +/* valid values for writeMode */ +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_WRITE_MODE_DEFAULT (0x00000000) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_WRITE_MODE_WRITETHROUGH (0x00000001) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_WRITE_MODE_WRITEBACK (0x00000002) + +/* valid values for powerState */ +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_POWER_STATE_DEFAULT (0x00000000) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_POWER_STATE_ENABLED (0x00000001) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_POWER_STATE_DISABLED (0x00000002) + +/* valid values for rcmState */ +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_RCM_STATE_DEFAULT (0x00000000) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_RCM_STATE_FULL (0x00000001) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_RCM_STATE_REDUCED (0x00000002) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_RCM_STATE_ZERO_CACHE (0x00000003) + +/* valid values for vgaCacheMode */ +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_VGA_MODE_DEFAULT (0x00000000) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_VGA_MODE_ENABLED (0x00000001) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_VGA_MODE_DISABLED (0x00000002) + +/* valid values for cacheReset */ +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_CACHE_RESET_DEFAULT (0x00000000) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_CACHE_RESET_RESET (0x00000001) + +/* valid fields and values for flags */ +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_FLAGS_MODE 1:0 +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_FLAGS_MODE_DEFAULT (0x00000000) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_FLAGS_MODE_RM (0x00000001) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_FLAGS_MODE_PMU (0x00000002) + +/* valid values for bypassMode */ +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_BYPASS_MODE_DEFAULT (0x00000000) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_BYPASS_MODE_DISABLED (0x00000001) +#define NV208F_CTRL_FB_CTRL_GPU_CACHE_BYPASS_MODE_ENABLED (0x00000002) + + + +/* + * NV208F_CTRL_CMD_FB_SET_STATE + * + * This command is used to put fb engine in a state requested by the caller. + * + * state + * This parameter specifies the desired engine state: + * NV208F_CTRL_FB_SET_STATE_STOPPED + * This value stops/halts the fb engine. + * NV208F_CTRL_FB_SET_STATE_RESTART + * This value restarts fb from a stopped state. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_FB_SET_STATE (0x208f0508) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_SET_STATE_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_SET_STATE_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV208F_CTRL_FB_SET_STATE_PARAMS { + NvU32 state; +} NV208F_CTRL_FB_SET_STATE_PARAMS; + +/* valid values for state */ +#define NV208F_CTRL_FB_SET_STATE_STOPPED (0x00000000) +#define NV208F_CTRL_FB_SET_STATE_RESTART (0x00000001) + +/* + * NV208F_CTRL_CMD_GPU_ECC_SCRUB_DIAG + * + * This command reads all the settings internal to scrubbing (both asynchronous + * and synchronous. + * + * Currently implemented: FB offset scrubber has completed, FB offset that scrubber + * is completing to, whether or not asynchronous scrubbing is enabled. + * + * fbOffsetCompleted + * This is the offset into FB that the scrubber has completed up to at the + * time this function is invoked. Note that the scrubber is top-down. Therefore + * the memory that remains unscrubbed is from 0x0 to fbOffsetCompleted. + * + * fbEndOffset + * This is the offset of the base of the last block that ECC asynchronous + * scrubber has been tasked to scrub. + * + * bAsyncScru bDisabled + * This is NV_TRUE if asynchronous scrubbing is disabled and NV_FALSE if + * asynchronous scrubbing is enabled. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV208F_CTRL_CMD_FB_ECC_SCRUB_DIAG (0x208f0509) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_CMD_FB_ECC_SCRUB_DIAG_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_CMD_FB_ECC_SCRUB_DIAG_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV208F_CTRL_CMD_FB_ECC_SCRUB_DIAG_PARAMS { + NV_DECLARE_ALIGNED(NvU64 fbOffsetCompleted, 8); + NV_DECLARE_ALIGNED(NvU64 fbEndOffset, 8); + NvBool bAsyncScrubDisabled; +} NV208F_CTRL_CMD_FB_ECC_SCRUB_DIAG_PARAMS; + +/* + * NV208F_CTRL_CMD_GPU_ECC_ASYNCH_SCRUB_REGION + * + * This command launches the ECC scrubber in asynchronous mode. The scrubber, as + * in normal operation, will continue to operate until all of FB (excluding + * dedicated system memory) has been scrubbed. Like usual operation, scrubbing is + * only done on silicon. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV208F_CTRL_CMD_FB_ECC_ASYNC_SCRUB_REGION (0x208f050a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_CMD_FB_ECC_ASYNC_SCRUB_REGION_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_CMD_FB_ECC_ASYNC_SCRUB_REGION_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV208F_CTRL_CMD_FB_ECC_ASYNC_SCRUB_REGION_PARAMS { + NV_DECLARE_ALIGNED(NvU64 startBlock, 8); + NV_DECLARE_ALIGNED(NvU64 endBlock, 8); +} NV208F_CTRL_CMD_FB_ECC_ASYNC_SCRUB_REGION_PARAMS; + +/* + * NV208F_CTRL_CMD_GPU_ECC_ERROR_INFO + * This is a structure that is defined here for diag/debug purposes in mods. + * It is used to return the error information as part of the callback to + * kernel clients registering for SBE/DBE callbacks. + */ + +typedef struct NV208F_CTRL_CMD_FB_ECC_ERROR_INFO { + NvU32 row; + NvU32 bank; + NvU32 col; + NvU32 extBank; + NvU32 xbarAddress; + NV_DECLARE_ALIGNED(NvU64 physAddress, 8); +} NV208F_CTRL_CMD_FB_ECC_ERROR_INFO; + + +#define NV208F_CTRL_CMD_FB_ECC_GET_FORWARD_MAP_ADDRESS (0x208f050c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_CMD_FB_ECC_GET_FORWARD_MAP_ADDRESS_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_CMD_FB_ECC_GET_FORWARD_MAP_ADDRESS_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV208F_CTRL_CMD_FB_ECC_GET_FORWARD_MAP_ADDRESS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 pAddr, 8); + NvU32 row; + NvU32 bank; + NvU32 col; + NvU32 extBank; + NvU32 rank; + NvU32 sublocation; + NvU32 partition; + NvU32 writeKillPtr0; + NvU32 injectionAddr; + NvU32 injectionAddrExt; + NvU32 rbcAddress; + NvU32 rbcAddressExt; + NvU32 rbcAddressExt2; + NvU32 eccCol; +} NV208F_CTRL_CMD_FB_ECC_GET_FORWARD_MAP_ADDRESS_PARAMS; + +/* + * NV208F_CTRL_CMD_FB_ECC_SET_KILL_PTR + * + * This command sets the kill pointer for the specified DRAM address. If + * the kill pointer is set to NV208F_CTRL_FB_ERROR_TYPE_CORRECTABLE + * or NV208F_CTRL_FB_ERROR_TYPE_UNCORRECTABLE, accesses to the specified + * address will result in ECC errors until all kill pointers are unset + * using NV208F_CTRL_FB_ERROR_TYPE_NONE. + * + * Only one kill pointer can be set at a time. Setting a kill pointer will + * clear all currently set kill pointers and set the new kill pointer. + * Calling NV208F_CTRL_FB_ERROR_TYPE_NONE simply clears all currently set + * kill pointers. + * + * errorType + * The type of kill pointer to set. NV208F_CTRL_FB_ERROR_TYPE_CORRECTABLE + * will set a single kill pointer resulting in a correctable error. + * NV208F_CTRL_FB_ERROR_TYPE_UNCORRECTABLE will set both kill pointers + * resulting in an uncorrectable error. NV208F_CTRL_FB_ERROR_TYPE_NONE + * will clear all kill pointers, which stops the associated addresses + * from generating ECC errors if NV208F_CTRL_FB_ERROR_TYPE_CORRECTABLE + * or NV208F_CTRL_FB_ERROR_TYPE_UNCORRECTABLE was previously set. + * Only one kill pointer can be set at a time and setting a new + * kill pointer will clear the previous kill pointer. + * + * address + * The physical DRAM address to be targeted by the kill pointer + * + * bProdInjection + * Whether the kill pointer is set through the production injection flow or not + */ +#define NV208F_CTRL_CMD_FB_ECC_SET_KILL_PTR (0x208f050e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_ECC_SET_KILL_PTR_PARAMS_MESSAGE_ID" */ + +typedef enum NV208F_CTRL_FB_ERROR_TYPE { + NV208F_CTRL_FB_ERROR_TYPE_CORRECTABLE = 0, + NV208F_CTRL_FB_ERROR_TYPE_UNCORRECTABLE = 1, + NV208F_CTRL_FB_ERROR_TYPE_NONE = 2, +} NV208F_CTRL_FB_ERROR_TYPE; + +#define NV208F_CTRL_FB_ECC_SET_KILL_PTR_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV208F_CTRL_FB_ECC_SET_KILL_PTR_PARAMS { + NV208F_CTRL_FB_ERROR_TYPE errorType; + NV_DECLARE_ALIGNED(NvU64 address, 8); + NvBool bProdInjection; +} NV208F_CTRL_FB_ECC_SET_KILL_PTR_PARAMS; + + + +/* + * NV208F_CTRL_CMD_FB_INJECT_LTC_ECC_ERROR + * + * This API allows a client to inject ECC errors in the L2. + * + * ltc: + * The physical LTC number to inject the error into. + * slice: + * THe physical slice number within the LTC to inject the error into. + * locationMask + * LTC location subtype(s) where error is to be injected. (Valid on Ampere and later) + * errorType + * Type of error to inject + * NV208F_CTRL_FB_ERROR_TYPE_CORRECTABLE for SBE. + * NV208F_CTRL_FB_ERROR_TYPE_UNCORRECTABLE for DBE. + * + */ +#define NV208F_CTRL_CMD_FB_INJECT_LTC_ECC_ERROR (0x208f050f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_INJECT_LTC_ECC_ERROR_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_INJECT_LTC_ECC_ERROR_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NV208F_CTRL_FB_INJECT_LTC_ECC_ERROR_PARAMS { + NvU8 ltc; + NvU8 slice; + NvU8 locationMask; + NV208F_CTRL_FB_ERROR_TYPE errorType; +} NV208F_CTRL_FB_INJECT_LTC_ECC_ERROR_PARAMS; + +/* + * NV208F_CTRL_CMD_FB_ECC_INJECTION_SUPPORTED + * + * Reports if error injection is supported for a given HW unit + * + * location [in]: + * The ECC protected unit for which ECC injection support is being checked. + * The location type is defined by NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC. + * + * bCorrectableSupported [out]: + * Boolean value that shows if correcatable errors can be injected. + * + * bUncorrectableSupported [out]: + * Boolean value that shows if uncorrecatable errors can be injected. + * + * Return values: + * NV_OK on success + * NV_ERR_INVALID_ARGUMENT if the requested location is invalid. + * NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled. + * NV_ERR_NOT_SUPPORTED otherwise + * + * + */ +#define NV208F_CTRL_CMD_FB_ECC_INJECTION_SUPPORTED (0x208f0510) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_PARAMS { + NvU8 location; + NvBool bCorrectableSupported; + NvBool bUncorrectableSupported; +} NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_PARAMS; + +#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC 0:0 +#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC_LTC (0x00000000) +#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC_DRAM (0x00000001) + +/* + * NV208F_CTRL_CMD_FB_ECC_SET_WRITE_KILL + * + * This command sets the write kill for the specified DRAM address. If set, + * writes to the specified address won't update the ECC checkbits. When unset, + * writes the specified address will update the ECC checkbits. + * + * Only one write kill register can be set at a time. Setting a write kill + * will clear all currently set write kills and set the new write kill. + * Calling this ctrl call with setWriteKill = false simply clears all currently + * set write kills. + * + * setWriteKill + * When true, the ECC checkbits for the specified address won't update on + * writes. When false, the ECC checkbits for the specified address will + * revert to normal behavior and update on all writes. + * + * address + * The physical DRAM address to be targeted by the write kill + */ +#define NV208F_CTRL_CMD_FB_ECC_SET_WRITE_KILL (0x208f0511) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS { + NvBool setWriteKill; + NV_DECLARE_ALIGNED(NvU64 address, 8); +} NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS; + +/* + * NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO + * + * physicalAddress + * Physical address to be remapped + * source + * The reason for retirement. Valid values for this parameter are + * from NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_* + * status + * Reason for row remapping failure. Valid values are: + * NV208F_CTRL_FB_REMAP_ROW_STATUS_OK + * No error + * NV208F_CTRL_FB_REMAP_ROW_STATUS_REMAPPING_PENDING + * The remapping is pending + * NV208F_CTRL_FB_REMAP_ROW_STATUS_TABLE_FULL + * Table full + * NV208F_CTRL_FB_REMAP_ROW_STATUS_ALREADY_REMAPPED + * Attempting to remap a reserved row + * NV208F_CTRL_FB_REMAP_ROW_STATUS_INTERNAL_ERROR + * Some other RM failure + */ +typedef struct NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO { + NV_DECLARE_ALIGNED(NvU64 physicalAddress, 8); + NvU8 source; + NvU32 status; +} NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO; + +/* valid values for status */ +#define NV208F_CTRL_FB_REMAP_ROW_STATUS_OK (0x00000000) +#define NV208F_CTRL_FB_REMAP_ROW_STATUS_REMAPPING_PENDING (0x00000001) +#define NV208F_CTRL_FB_REMAP_ROW_STATUS_TABLE_FULL (0x00000002) +#define NV208F_CTRL_FB_REMAP_ROW_STATUS_ALREADY_REMAPPED (0x00000003) +#define NV208F_CTRL_FB_REMAP_ROW_STATUS_INTERNAL_ERROR (0x00000004) + +#define NV208F_CTRL_FB_REMAPPED_ROWS_MAX_ROWS (0x00000200) +/* + * NV208F_CTRL_CMD_FB_REMAP_ROW + * + * This command will write entries to Inforom. During init the entries will be + * read and used to remap a row. + * + * addressList + * This input parameter is an array of NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO + * structures containing information used for row remapping. Valid entries + * are adjacent + * validEntries + * This input parameter specifies the number of valid entries in the + * address array + * numEntriesAdded + * This output parameter specifies how many validEntries were successfully + * added to the Inforom + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_FB_REMAP_ROW (0x208f0512) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_REMAP_ROW_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_REMAP_ROW_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV208F_CTRL_FB_REMAP_ROW_PARAMS { + NV_DECLARE_ALIGNED(NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO addressList[NV208F_CTRL_FB_REMAPPED_ROWS_MAX_ROWS], 8); + NvU32 validEntries; + NvU32 numEntriesAdded; +} NV208F_CTRL_FB_REMAP_ROW_PARAMS; + + +#define NV208F_CTRL_CMD_FB_REVERSE_MAP_RBC_ADDR_TO_PA (0x208f0513) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_REVERSE_MAP_RBC_ADDR_TO_PA_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_REVERSE_MAP_RBC_ADDR_TO_PA_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV208F_CTRL_FB_REVERSE_MAP_RBC_ADDR_TO_PA_PARAMS { + NV_DECLARE_ALIGNED(NvU64 address, 8); + NvU32 rbcAddress; + NvU32 rbcAddressExt; + NvU32 rbcAddressExt2; + NvU32 partition; + NvU32 sublocation; +} NV208F_CTRL_FB_REVERSE_MAP_RBC_ADDR_TO_PA_PARAMS; + +/** + * NV208F_CTRL_CMD_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF + * + * This command will convert a physical address when ECC is on to the physical + * address when ECC is off or vice versa + * + * @params[in] NvU64 inputAddress + * Input physical address + * + * @params[in] NvBool eccOn + * Whether or not input physical address is with ECC on or off + * + * @params[out] NvU64 outputAddress + * Output physical address + */ +#define NV208F_CTRL_CMD_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF (0x208f0514) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV208F_CTRL_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF_PARAMS { + NV_DECLARE_ALIGNED(NvU64 inputAddress, 8); + NvBool eccOn; + NV_DECLARE_ALIGNED(NvU64 outputAddress, 8); +} NV208F_CTRL_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF_PARAMS; + +/* + * NV208F_CTRL_CMD_FB_CLEAR_REMAPPED_ROWS + * + * This command clears remapping entries from the Inforom's row remapping table. + * + * sourceMask + * This is a bit mask of NV2080_CTRL_FB_REMAPPED_ROW_SOURCE. Rows + * remapped from the specified sources will be cleared/removed from the + * Inforom RRL object entries list. + * + * Possbile status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV208F_CTRL_CMD_FB_CLEAR_REMAPPED_ROWS (0x208f0515) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS { + NvU32 sourceMask; +} NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS; + +/* + * NV208F_CTRL_CMD_FB_GET_FLOORSWEPT_FBPA_MASK + * + * This command calculates the floorswept fbpa mask by taking 1/2 HBM + * floorsweeping into account + * + * fbpaMask + * This value of the mask. + * + * Possbile status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV208F_CTRL_CMD_FB_GET_FLOORSWEPT_FBPA_MASK (0x208f0516) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_GET_FLOORSWEPT_FBPA_MASK_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_GET_FLOORSWEPT_FBPA_MASK_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV208F_CTRL_FB_GET_FLOORSWEPT_FBPA_MASK_PARAMS { + NvU32 fbpaMask; +} NV208F_CTRL_FB_GET_FLOORSWEPT_FBPA_MASK_PARAMS; + +/* _ctrl208ffb_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208ffbio.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208ffbio.h new file mode 100644 index 0000000..a523160 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208ffbio.h @@ -0,0 +1,249 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208ffbio.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* + * NV208F_CTRL_CMD_FBIO_SETUP_TRAINING_EXP + * + * This command defines an fbio training experiment for later use. + * + * This command has the form of a 'cmd' operation descriminant + * followed by a union populated with an operand to match the 'cmd'. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_COMMAND + * + */ +#define NV208F_CTRL_CMD_FBIO_SETUP_TRAINING_EXP (0x208f0a03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FBIO_INTERFACE_ID << 8) | NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_PARAMS_MESSAGE_ID" */ + +/* + * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_NULL + * + * This command has no effect when used. + */ +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_NULL 0 + +/* + * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS + * + * This command defines the number of register modification slots to be used + * in the setup phase of the pass/fail training exercise. Using this cmd + * causes any previously defined modification table to be cleared/released. + * The maximum size of the table is defined by + * _SETUP_FBIO_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS__MAX + * Using the value of zero for number of mod slots is valid. "Mod slots" + * are defined below. + * + * Possible status values returned are: + * NV_ERR_INVALID_LIMIT + * if modSlots is > __MAX + * NV_ERR_INSUFFICIENT_RESOURCES + * if we're out of memory setting up the mod slot table + */ +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS 1 +typedef struct NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS_OPERANDS { + NvU32 modSlots; +} NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS_OPERANDS; + +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS__MAX 256 + +/* + * NV208F_CTRL_FBIO_SETUPFBIO_TRAINING_EXP_SET_MOD_SLOT + * + * This command is used to define each individual element of the the sequence + * of operations which will be performed before running the pass/fail training + * exercise. Note that this cmd is multi-cmd (with a null cmd all its own, + * etc). + * + * Possible status values returned are: + * NV_ERR_INVALID_INDEX + * if seq is out of range for previously set SET_NUMBER_OF_MOD_SLOTS + * operation. + * NV_ERR_INVALID_COMMAND + * if cmd isn't recognized + */ +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT 2 + +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_NULL 0 + +/* + * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_SET_REGISTER + * + * This cmd is used to define a register transaction to be applied in + * sequence before running the pass/fail experiment. This is where + * NV_PFB_TRAINING_ADR, NV_PFB_TRAINING_CMD, NV_PFB_TRAINING_DP(i), + * NV_PFB_TRAINING_THRESHOLD and NV_PFB_TRAINING_MASK, etc. should be + * configured before calling back with cmd + * NV208F_CTRL_CMD_FBIO_RUN_TRAINING_EXP. + * + * reg + * This parameter specifies the BAR0 register offset to affect. + * andMask + * orMask + * These parameter specify the RMW values to be used in the following: + * write32(reg, (read32(reg) & andMask) | orMask) + */ +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_SET_REGISTER 1 +typedef struct NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_SET_REGISTER_OPERANDS { + NvU32 reg; + NvU32 andMask; + NvU32 orMask; +} NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_SET_REGISTER_OPERANDS; + +/* + * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_DELAY + * + * This cmd is used to define a delay to be applied in the setup sequence + * before running the pass/fail experiment. + * + * usec + * Specifies delay to be used in microseconds. + */ + +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_DELAY 2 +typedef struct NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_DELAY_OPERANDS { + NvU32 usec; +} NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_DELAY_OPERANDS; + +/* + * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_INIT_LT + * + * This cmd is used to define a point where normal link training initialization + * may be executed in the sequence before running the pass/fail experiment. + * In general, this is not needed since it is done during normal + * initialization, but does allow re-initialization during the sequence. + */ +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_INIT_LT 3 + +/* + * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_RUN_LT + * + * This cmd is used to define a point where normal link training may be + * executed in the sequence before running the pass/fail experiment. + * In general, this is not needed since it is somewhat redundant. + */ +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_RUN_LT 4 + +/* + * NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_STOP_SEQ + * + * This cmd is used to define a point where the sequence stops without + * running the pass/fail experiment. + */ +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_STOP_SEQ 5 + + + +typedef struct NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_PARAMS { + NvU32 cmd; + /* C form: NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_OPERANDS op; */ + union { + + NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_SET_REGISTER_OPERANDS setRegister; + + NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_DELAY_OPERANDS delay; + } op; + NvU32 seq; +} NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_PARAMS; + + + +#define NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_PARAMS { + NvU32 cmd; + + /* C form: NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_OPERANDS op; */ + union { + + NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_NUMBER_OF_MOD_SLOTS_OPERANDS setNumberOfModSlots; + + NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_SET_MOD_SLOT_PARAMS setModSlot; + } op; +} NV208F_CTRL_FBIO_SETUP_TRAINING_EXP_PARAMS; + +/* + * NV208F_CTRL_CMD_FBIO_RUN_TRAINING_EXP + * + * This command runs the previously defined experiment and returns status on + * pass/fail. NV_OK is returned in the case of both pass + * and fail. + * + * The risingPasses and fallingPasses outputs represents the results across + * all partitions and bytelanes. Each array entry corresponds to a partition + * and the bits within each member represent the bytelane. So e.g.: + * risingPasses[4] represents the rising pass results for all of partition 4's + * byte lanes. + * + * The partitionsValid bitmask represents the partitions for which the results + * in risingPasses and fallingPasses are valid (not floorswept). + * + * The bytelanesValid bitmask represents the bytelanes for which the results + * are valid (available bytelanes). + * + * The failingDebug[] represent debug data for why (if so) a test fails. + * This is basically NV_PFB_TRAINING_DEBUG(i) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_TIMEOUT + * if hardware doesn't respond to request in a timely manner. + * NV_ERR_INVALID_DATA + * if there was some sort of very weird data corruption issue. + */ +#define NV208F_CTRL_CMD_FBIO_RUN_TRAINING_EXP (0x208f0a04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FBIO_INTERFACE_ID << 8) | NV208F_CTRL_FBIO_RUN_TRAINING_EXP_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FBIO_RUN_TRAINING_EXP_RESULT__SIZE 8 +#define NV208F_CTRL_FBIO_RUN_TRAINING_EXP_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV208F_CTRL_FBIO_RUN_TRAINING_EXP_PARAMS {NvU32 risingPasses[NV208F_CTRL_FBIO_RUN_TRAINING_EXP_RESULT__SIZE]; + NvU32 fallingPasses[NV208F_CTRL_FBIO_RUN_TRAINING_EXP_RESULT__SIZE]; + NvU32 failingDebug[NV208F_CTRL_FBIO_RUN_TRAINING_EXP_RESULT__SIZE]; + NvU32 partitionsValid; + NvU32 bytelanesValid; +} NV208F_CTRL_FBIO_RUN_TRAINING_EXP_PARAMS; + +#define NV208F_CTRL_CMD_FBIO_GET_TRAINING_CAPS (0x208f0a05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FBIO_INTERFACE_ID << 8) | NV208F_CTRL_FBIO_GET_TRAINING_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FBIO_GET_TRAINING_CAPS_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV208F_CTRL_FBIO_GET_TRAINING_CAPS_PARAMS { + NvU32 supported; +} NV208F_CTRL_FBIO_GET_TRAINING_CAPS_PARAMS; + +// _ctrl208ffbio_h_ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208ffifo.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208ffifo.h new file mode 100644 index 0000000..dba64cd --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208ffifo.h @@ -0,0 +1,159 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208ffifo.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* + * NV208F_CTRL_CMD_FIFO_CHECK_ENGINE_CONTEXT + * + * This command checks whether or not engine context exists for a given + * engine for the channel with a given channel ID. This API is intended + * for testing virtual context. For debug only. + * + * hChannel + * The handle to the channel. + * engine + * The engine ID. + * Valid values are: + * NV2080_ENGINE_TYPE_GRAPHICS + * exists + * The output are TRUE or FALSE. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_CHANNEL + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_FIFO_CHECK_ENGINE_CONTEXT (0x208f0401) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FIFO_INTERFACE_ID << 8) | NV208F_CTRL_FIFO_CHECK_ENGINE_CONTEXT_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FIFO_CHECK_ENGINE_CONTEXT_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV208F_CTRL_FIFO_CHECK_ENGINE_CONTEXT_PARAMS { + NvHandle hChannel; + NvU32 engine; + NvBool exists; +} NV208F_CTRL_FIFO_CHECK_ENGINE_CONTEXT_PARAMS; + +/* + * NV208F_CTRL_CMD_FIFO_ENABLE_VIRTUAL_CONTEXT + * + * This command enables virtual context for a given channel (for all engines). + * This API is intended for testing virtual context. For debug only. + * + * hChannel + * The handle to the channel. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_CHANNEL + */ +#define NV208F_CTRL_CMD_FIFO_ENABLE_VIRTUAL_CONTEXT (0x208f0402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FIFO_INTERFACE_ID << 8) | NV208F_CTRL_FIFO_ENABLE_VIRTUAL_CONTEXT_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FIFO_ENABLE_VIRTUAL_CONTEXT_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV208F_CTRL_FIFO_ENABLE_VIRTUAL_CONTEXT_PARAMS { + NvHandle hChannel; +} NV208F_CTRL_FIFO_ENABLE_VIRTUAL_CONTEXT_PARAMS; + +/* + * NV208F_CTRL_CMD_FIFO_GET_CHANNEL_STATE + * + * This command returns the fifo channel state for the given channel. + * This is for testing channel behavior. For debug only. + * + * hChannel + * The handle to the channel + * hClient + * The handle to the client + * bound + * The channel has been bound to channel RAM + * enabled + * The channel is able to run. + * scheduled + * The channel has been scheduled to run. + * cpuMap + * There is a cpu mapping available to this channel. + * contention + * The virtual channel is under contention + * runlistSet + * A runlist has been chosen for this channel + * deferRC + * An RC error has occurred, but recovery will occur at channel teardown. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_CHANNEL + */ +#define NV208F_CTRL_CMD_FIFO_GET_CHANNEL_STATE (0x208f0403) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FIFO_INTERFACE_ID << 8) | NV208F_CTRL_FIFO_GET_CHANNEL_STATE_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FIFO_GET_CHANNEL_STATE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV208F_CTRL_FIFO_GET_CHANNEL_STATE_PARAMS { + NvHandle hChannel; + NvHandle hClient; + NvBool bBound; + NvBool bEnabled; + NvBool bScheduled; + NvBool bCpuMap; + NvBool bContention; + NvBool bRunlistSet; + NvBool bDeferRC; +} NV208F_CTRL_FIFO_GET_CHANNEL_STATE_PARAMS; + +/* + * NV208F_CTRL_CMD_FIFO_GET_CONTIG_RUNLIST_POOL + * + * This command returns the location of the pool runlists are allocated from for + * WPR testing. + * For debug only. + * + * physAddr [out] + * Physical address of the pool + * + * size [out] + * Size in bytes of the pool + * + */ +#define NV208F_CTRL_CMD_FIFO_GET_CONTIG_RUNLIST_POOL (0x208f0404) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FIFO_INTERFACE_ID << 8) | NV208F_CTRL_FIFO_GET_CONTIG_RUNLIST_POOL_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FIFO_GET_CONTIG_RUNLIST_POOL_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV208F_CTRL_FIFO_GET_CONTIG_RUNLIST_POOL_PARAMS { + NV_DECLARE_ALIGNED(NvU64 physAddr, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); +} NV208F_CTRL_FIFO_GET_CONTIG_RUNLIST_POOL_PARAMS; + +/* _ctrl208ffifo_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h new file mode 100644 index 0000000..d473f11 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h @@ -0,0 +1,161 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fgpu.finn +// + +#include "ctrl/ctrl2080/ctrl2080gr.h" /* 208F is partially derivative of 2080 */ +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* + * NV208F_CTRL_CMD_GPU_GET_RAM_SVOP_VALUES + * + * This command can be used to get the RAM SVOP values. + * + * sp + * This field outputs RAM_SVOP_SP + * rg + * This field outputs RAM_SVOP_REG + * pdp + * This field outputs RAM_SVOP_PDP + * dp + * This field outputs RAM_SVOP_DP + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV208F_CTRL_CMD_GPU_GET_RAM_SVOP_VALUES (0x208f1101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | 0x1" */ + +typedef struct NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS { + NvU32 sp; + NvU32 rg; + NvU32 pdp; + NvU32 dp; +} NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS; + +/* + * NV208F_CTRL_CMD_GPU_SET_RAM_SVOP_VALUES + * + * This command can be used to set the RAM SVOP values. + * + * sp + * Input for RAM_SVOP_SP + * rg + * Input for RAM_SVOP_REG + * pdp + * Input for RAM_SVOP_PDP + * dp + * Input for RAM_SVOP_DP + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV208F_CTRL_CMD_GPU_SET_RAM_SVOP_VALUES (0x208f1102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | 0x2" */ + + + +/* + * NV208F_CTRL_CMD_GPU_VERIFY_INFOROM + * + * This command can be used by clients to determine if an InfoROM + * with a valid image is present. If the SKU in question does + * not feature an InfoROM, the NV_ERR_NOT_SUPPORTED + * error is returned. Else the RM attempts to read the ROM object + * and any objects listed in the ROM object. The checksum of + * each object read is verified. If all checksums are valid, the + * RM will report the InfoROM as being valid. If image is valid then + * RM will return a checksum for all of the dynamically configurable + * data in InfoROM. This checksum is expected to be same for all the + * boards with an identical InfoROM version and similarly configured. + * + * result + * The result of the InfoROM verification attempt. Possible + * values are: + * NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULTS_NONE + * This value indicates that a validation couldn't be done + * due to some software/OS related error. + * NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULTS_IO_ERROR + * This value indicates that a validation couldn't be done + * due to some IO error. + * NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULTS_VALID + * This value indicates that all InfoROM objects have valid + * checksum. + * NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULTS_INVALID + * This value indicates that some InfoROM objects have invalid + * checksum. + * checksum + * Checksum for all of the dynamically configurable data + * in InfoROM for e.g. PWR and CFG objects. + * + * NOTE: For the result values to be valid, return status should be: + * NV_OK + * + * Possible return status values: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * + */ +#define NV208F_CTRL_CMD_GPU_VERIFY_INFOROM (0x208f1105) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | NV208F_CTRL_GPU_VERIFY_INFOROM_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_GPU_VERIFY_INFOROM_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV208F_CTRL_GPU_VERIFY_INFOROM_PARAMS { + NvU32 result; + NvU32 checksum; +} NV208F_CTRL_GPU_VERIFY_INFOROM_PARAMS; + +/* valid result values */ +#define NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULT_NONE (0x00000000) +#define NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULT_IO_ERROR (0x00000001) +#define NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULT_VALID (0x00000002) +#define NV208F_CTRL_GPU_INFOROM_VERIFICATION_RESULT_INVALID (0x00000003) + +/* + * NV208F_CTRL_CMD_GPU_DISABLE_ECC_INFOROM_REPORTING + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + + + +#define NV208F_CTRL_CMD_GPU_DISABLE_ECC_INFOROM_REPORTING (0x208f1107) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | 0x7" */ + + + +/* _ctrl208fgpu_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fgr.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fgr.h new file mode 100644 index 0000000..357ac1f --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fgr.h @@ -0,0 +1,109 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fgr.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +#include "ctrl/ctrl2080/ctrl2080gr.h" + + + +/* + * NV208F_CTRL_CMD_GR_ECC_INJECT_ERROR + * + * Control command to inject a gr ecc error + * + * Parameters: + * + * location + * location index + * sublocation + * sublocation index + * unit + * unit to inject error into + * errorType + * SBE or DBE + * grRouteInfo + * Routing info for SMC + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_GR_ECC_INJECT_ERROR (0x208f1203) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GR_INTERFACE_ID << 8) | NV208F_CTRL_GR_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_GR_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV208F_CTRL_GR_ECC_INJECT_ERROR_PARAMS { + NvU32 location; + NvU32 sublocation; + NvU8 unit; + NvU8 errorType; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV208F_CTRL_GR_ECC_INJECT_ERROR_PARAMS; + + + +/* + * NV208F_CTRL_CMD_GR_ECC_INJECTION_SUPPORTED + * + * Reports if error injection is supported for a given HW unit + * + * unit [in]: + * The ECC protected unit for which ECC injection support is being checked. + * + * bCorrectableSupported [out]: + * Boolean value that shows if correcatable errors can be injected. + * + * bUncorrectableSupported [out]: + * Boolean value that shows if uncorrecatable errors can be injected. + * + * Return values: + * NV_OK on success + * NV_ERR_INVALID_ARGUMENT if the requested unit is invalid. + * NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled. + * NV_ERR_NOT_SUPPORTED otherwise + * + * + */ +#define NV208F_CTRL_CMD_GR_ECC_INJECTION_SUPPORTED (0x208f1204) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GR_INTERFACE_ID << 8) | NV208F_CTRL_GR_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_GR_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV208F_CTRL_GR_ECC_INJECTION_SUPPORTED_PARAMS { + NvU8 unit; + NvBool bCorrectableSupported; + NvBool bUncorrectableSupported; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV208F_CTRL_GR_ECC_INJECTION_SUPPORTED_PARAMS; + +/* _ctrl208fgr_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h new file mode 100644 index 0000000..2b298e6 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h @@ -0,0 +1,128 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fmmu.finn +// + +#include "ctrl/ctrl208f/ctrl208fbase.h" + +/* + * NV208F_CTRL_CMD_MMU_ECC_INJECT_ERROR + * + * This ctrl call injects MMU ECC errors. Please see the confluence + * page "ECC" for more information on ECC and ECC injection: + * + * Parameters: + * + * location + * Only used for HSHUBMMU. + * + * sublocation + * Only used for HSHUBMMU. + * + * unit + * Specifies the MMU HW unit where the injection will occur. + * + * errorType + * Specifies whether the injected error will be correctable or uncorrectable. + * Correctable errors have no effect on running programs while uncorrectable + * errors will cause all channels to be torn down. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + */ +#define NV208F_CTRL_CMD_MMU_ECC_INJECT_ERROR (0x208f0b01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID << 8) | NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS { + NvU32 location; + NvU32 sublocation; + NvU8 unit; + NvU8 errorType; +} NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS; + + + +/* + * NV208F_CTRL_CMD_MMU_ECC_INJECTION_SUPPORTED + * + * Reports if error injection is supported for a given HW unit + * + * unit [in]: + * The ECC protected unit for which ECC injection support is being checked. + * + * bCorrectableSupported [out]: + * Boolean value that shows if correcatable errors can be injected. + * + * bUncorrectableSupported [out]: + * Boolean value that shows if uncorrecatable errors can be injected. + * + * Return values: + * NV_OK on success + * NV_ERR_INVALID_ARGUMENT if the requested location is invalid. + * NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled. + * NV_ERR_NOT_SUPPORTED otherwise + * + */ +#define NV208F_CTRL_CMD_MMU_ECC_INJECTION_SUPPORTED (0x208f0b02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID << 8) | NV208F_CTRL_MMU_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */ + + + +#define NV208F_CTRL_MMU_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV208F_CTRL_MMU_ECC_INJECTION_SUPPORTED_PARAMS { + NvU8 unit; + NvBool bCorrectableSupported; + NvBool bUncorrectableSupported; +} NV208F_CTRL_MMU_ECC_INJECTION_SUPPORTED_PARAMS; + +/* + * NV208F_CTRL_CMD_MMU_GET_NUM_HSHUBMMUS + * + * Returns the number of ECC Capable HSHUBMMUS. + * + * numHshubmmus [out] + * Number of Hshubmmus + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV208F_CTRL_CMD_MMU_GET_NUM_HSHUBMMUS (0x208f0b03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID << 8) | NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS { + NvU32 numHshubmmus; +} NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS; + +/* _ctrl208fmmu_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fpmgr.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fpmgr.h new file mode 100644 index 0000000..d7ea299 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fpmgr.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fpmgr.finn +// + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fpower.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fpower.h new file mode 100644 index 0000000..e225c7b --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl208f/ctrl208fpower.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl208f/ctrl208fpower.finn +// + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl30f1.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl30f1.h new file mode 100644 index 0000000..fdfa8fb --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl30f1.h @@ -0,0 +1,1493 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl30f1.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV30_GSYNC_CTRL control commands and parameters */ + +#define NV30F1_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x30F1, NV30F1_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NV30F1_CTRL_RESERVED (0x00) +#define NV30F1_CTRL_GSYNC (0x01) + +/* + * NV30F1_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV30F1_CTRL_CMD_NULL (0x30f10000) /* finn: Evaluated from "(FINN_NV30_GSYNC_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* NV30F1_CTRL_GSYNC + * + * Gsync board access/control functionality. + * + */ + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_VERSION + * + * This command will get the current gsync api version info. + * + * version + * The api's major version. Does not change often. + * + * revision + * The api's minor version. + * Bumped with each change, no matter how minor. + * + * Possible status values returned are: + * NV_OK + * + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_VERSION (0x30f10101) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS { + NvU32 version; + NvU32 revision; +} NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS; + +#define NV30F1_CTRL_GSYNC_API_VER 1 +#define NV30F1_CTRL_GSYNC_API_REV 0 + +/* + * NV30F1_CTRL_GSYNC api + * + * The gsync interface provides access to gsync devices in the system. + * + * There are commands: + * NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SIGNALS + * Status on input sync signals. + * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_PARAMS + * Get gsync parameters. + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_PARAMS + * Get gsync parameters. + * NV30F1_CTRL_CMD_GSYNC_GET_INFO_CAPS + * Get basic info about the device and its connected displays + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SYNC + * Enable frame sync. + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_UNSYNC + * Disable frame sync. + * NV30F1_CTRL_CMD_GSYNC_GET_STATUS + * Get status info relevant for the control panel + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_TESTING + * Test signal enabling/disabling + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_WATCHDOG + * Control the gsync watchdog + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_INTERLACE_MODE + * Set the interlace mode + * + */ + + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SIGNALS + * + * This command returns information associated with incoming signals to the + * gsync device. + * + * RJ45 + * This parameter contains the signal information for each of the two RJ45 + * ports on the gsync device. A value of ~0 indicates that a signal is + * detected, but no rate information is available. Anything else is a rate + * in units of 10e-4 Hz. + * house + * This parameter contains the signal information for the house sync signal + * (i.e. the bnc port). A value of 0 means that no signal is present. A value + * of ~0 indicates that a signal is detected, but no rate information is + * available. Anything else is a rate in units of 10e-4 Hz. + * rate + * A mask representing signals for which we would like rate information (if + * available). + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + * + */ + +#define NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SIGNALS (0x30f10102) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS { + NvU32 RJ45[2]; + NvU32 house; + NvU32 rate; +} NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS; + +/* + * rate values + * + */ + +#define NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_RJ45_0 (0x00000001) +#define NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_RJ45_1 (0x00000002) +#define NV30F1_CTRL_GSYNC_GET_SIGNALS_HOUSE (0x00000004) + + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_PARAMS + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_PARAMS + * + * These commands respectively return and set state related to the operation + * of the gsync device. + * + * which + * This value is a mask set by the client representing which parameters are + * to be updated. In the case of a GET command, these parameters will + * be used to change the state of the hardware. For both a GET + * command and a SET command, the hardware state will be returned by + * the RM in the respective parameter. All other parameters are untouched. + * syncPolarity + * This parameter specifies which edge of the house sync signal to sync with. + * videoMode + * This parameter specifies which video mode to use to decode the house sync + * signal. + * nSync + * This parameter specifies the number of pulses to wait between frame lock + * signal generation. 0 indicates that every incomming pulse should result in + * a frame lock sync pulse being generated (i.e. the input and output rate + * matches). + * syncSkew + * This parameter specifies the time delay between the frame sync signal and + * the GPUs signal in units of 0.977 us. Maximum value for SyncSkew is defined + * in respective header files of gsync boards. e.g. For P2060 board value + * is defined in drivers/resman/kernel/inc/dacp2060.h + * syncStartDelay + * In master mode, the amount of time to wait before generating the first + * sync pulse in units of 7.81 us, max 512 ms (i.e 65535 units). + * useHouseSync + * When a house sync signal is detected, this parameter indicates that it + * should be used as the reference to generate the frame sync signal. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ + +#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_PARAMS (0x30f10103) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_PARAMS (0x30f10104) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS { + NvU32 which; + NvU32 syncPolarity; + NvU32 syncVideoMode; + NvU32 nSync; + NvU32 syncSkew; + NvU32 syncStartDelay; + NvU32 useHouseSync; +} NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS; +#define NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS_MESSAGE_ID (0x4U) + +typedef NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS; + +/* + * which values + * + */ + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY 0x0001 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE 0x0002 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC 0x0004 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW 0x0008 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY 0x0010 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE 0x0020 + +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_POLARITY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE +#define NV30F1_CTRL_GSYNC_GET_CONTROL_NSYNC NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_SKEW NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_START_DELAY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_USE_HOUSE NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE + +/* + * syncPolarity values + * + */ + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_RISING_EDGE 0 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_FALLING_EDGE 1 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_BOTH_EDGES 2 + +/* + * syncVideoMode values + * Video_Mode_Composite is valid for P2060 only. + * + */ + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE 0 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL 1 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM 2 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV 3 + +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NONE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_TTL NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NTSCPALSECAM NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_HDTV NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_COMPOSITE 4 + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_CAPS + * + * This command returns the capabilities of this gsync device. + * + * revId + * This parameter is set by the RM to indicate the combined + * FPGA revision (low 4 bits) and board ID (high 4 bits). + * + * boardId + * This parameter is set by the RM to indicate the board ID, + * allowing disambiguation of P2060 and so forth. + * + * minRevRequired + * This parameter is set by the RM to indicate the minimum + * Qsync FPGA revision required for a specific CHIP Familiy + * + * isFirmwareRevMismatch + * This parameter is set to TRUE by RM when the Qsync Firmware + * Revision is incompatibled with the connected GPU chip family. + * + * revision + * This parameter is set by the RM to indicate the device revision, + * also known as major version. + * + * extendedRevision + * This parameter is set by the RM to indicate the device extended + * revision, also known as minor version. + * + * capFlags + * This parameter is set by the RM to indicate capabilities of + * the board, preventing the client from needing to keep track + * of the feature lists supported by each revision of each board. + * + * maxSyncSkew + * This parameter returns that maximum units of sync skew the + * board supports. The value prgrammed into the board has to be + * between 0 and maxSyncSkew, inclusive. The value of each unit + * can be learned from the syncSkewResolution parameter. + * + * syncSkewResolution + * This parameter returns the number of nanoseconds that one unit + * of sync skew corresponds to. + * + * maxStartDelay + * This parameter returns that maximum units of sync start delay + * the board supports. The value prgrammed into the board has to be + * between 0 and maxStartDelay, inclusive. The value of each unit + * can be learned from the startDelayResolution parameter. + * + * startDelayResolution + * This parameter returns the number of nanoseconds that one unit + * of sync start delay corresponds to. + * + * maxSyncInterval + * This parameter returns the maximum duration of house sync interval + * between frame lock sync cycle that the board supports. The value + * programmed into the board has to be between 0 and maxSyncInterval, + * inclusive. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV30F1_CTRL_CMD_GSYNC_GET_CAPS (0x30f10105) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS { + NvU32 revId; + NvU32 boardId; + NvU32 minRevRequired; + NvBool isFirmwareRevMismatch; + NvU32 revision; + NvU32 extendedRevision; + NvU32 capFlags; + NvU32 maxSyncSkew; + NvU32 syncSkewResolution; + NvU32 maxStartDelay; + NvU32 startDelayResolution; + NvU32 maxSyncInterval; +} NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS; + +#define NV30F1_CTRL_GSYNC_GET_CAPS_BOARD_ID_P2060 (0x00002060) +#define NV30F1_CTRL_GSYNC_GET_CAPS_BOARD_ID_P2061 (0x00002061) + +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_FREQ_ACCURACY_2DPS (0x00000001) +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_FREQ_ACCURACY_3DPS (0x00000002) +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_FREQ_ACCURACY_4DPS (0x00000004) + +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_NEED_MASTER_BARRIER_WAR (0x00000010) + +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_SYNC_LOCK_EVENT (0x10000000) +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_HOUSE_SYNC_EVENT (0x20000000) +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_FRAME_COUNT_EVENT (0x40000000) + +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_ONLY_PRIMARY_CONNECTOR_EVENT (0x01000000) +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_ALL_CONNECTOR_EVENT (0x02000000) + +// For P2060, clients can only request for video modes at BNC connector +// e.g. NO HS, TTL and Composite etc. +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_ONLY_GET_VIDEO_MODE (0x00100000) + +/* + * NV30F1_CTRL_CMD_GET_GSYNC_GPU_TOPOLOGY + * + * This command returns the list of GPU IDs connected with the associated + * gsync device. + * + * gpus + * This array is set by RM to contain the gpu connection information + * for gpus attached to the gsync device. Valid entries are contiguous, + * beginning with the first entry in the list. The elements of this array contain + * the following fields: + * gpuId + * This field contains the ID of the connected GPU. If the entry in the + * table is invalid, this fields contains NV30F1_CTRL_GPU_INVALID_ID. + * connector + * This field indicates which connector on the device the GPU is connected + * to (i.e. the primary or secondary connector), if any. + * proxyGpuId + * If the 'connector' field indicates that the GPU is not connected to + * a G-Sync device directly, then this field contains the ID of the + * GPU that acts as a proxy, i.e. the GPU to which this GPU should be + * a RasterLock slave. + * connectorCount + * This parameter indicates the number of GPU connectors available on + * the gsync device. The connector count of the gsync device may be + * less than NV30F1_CTRL_MAX_GPUS_PER_GSYNC. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV30F1_CTRL_CMD_GET_GSYNC_GPU_TOPOLOGY (0x30f10106) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_MAX_GPUS_PER_GSYNC 4 +#define NV30F1_CTRL_GPU_INVALID_ID (0xffffffff) + +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS { + struct { + NvU32 gpuId; + NvU32 connector; + NvU32 proxyGpuId; + } gpus[NV30F1_CTRL_MAX_GPUS_PER_GSYNC]; + NvU32 connectorCount; +} NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS; + +/* + * connector values + * + */ +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_ONE 1 +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_TWO 2 +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_THREE 3 +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_FOUR 4 + +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_NONE 0 +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PRIMARY NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_ONE +#define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_SECONDARY NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_TWO + + + + +/* + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SYNC + * + * This command enables frame sync on displays. + * + * gpuId + * The parameter is set by the client to indicate the gpuId on which + * frame lock will be enabled. + * master + * This parameter is set by the client to specify whether this/these + * displays should be set as the master or as slaves. If this is a GET + * and displays is not 0, this will be set by the RM to indicate if + * the display can be the master. + * displays + * This is a device mask set by the client to indicate which display(s) + * are to be synched. Note that only one display may be set as master. + * If this is a GET, this set by the client to indicate which display + * is to be queried. If the display cannot be synched to this device, + * the RM will overwrite the mask with a 0. + * validateExternal + * This parameter is set by the client to tell the RM to validate the + * presence of an external sync source when enabling a master. + * refresh + * This parameter is set by the client to indicate the desired refresh rate + * The value is in 0.0001 Hertz (i.e. it has been multiplied by 10000). + * configFlags + * contains flags for specific options. So far only + * NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_CONFIG_FLAGS_KEEP_MASTER_SWAPBARRIER_DISABLED + * is supported which allows the caller to prevent the rm code to automatically + * enable the swapbarrier on framelock masters on fpga revisions <= 5. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SYNC (0x30f10110) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SYNC (0x30f10111) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS_MESSAGE_ID" */ + +// If set the swapbarrier is not enable automatically when enablign a framelock master on fpga revs <= 5. +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_CONFIG_FLAGS_KEEP_MASTER_SWAPBARRIER_DISABLED (0x00000001) + +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS { + NvU32 gpuId; + NvU32 master; + NvU32 displays; + NvU32 validateExternal; + NvU32 refresh; + NvU32 configFlags; +} NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS; +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS_MESSAGE_ID (0x11U) + +typedef NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS; + +/* + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_UNSYNC + * + * This command disables frame sync on displays + * + * gpuId + * The parameter is set by the client to indicate the gpuId on which + * frame lock will be disabled. + * master + * This parameter is set by the client to specify whether this/these + * display(s) to be unset is a master/are slaves. + * displays + * This is a device mask set by the client to indicate which display(s) + * are to be unsynched. + * retainMaster + * Retain the designation as master, but unsync the displays. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + */ +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_UNSYNC (0x30f10112) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS { + NvU32 gpuId; + NvU32 master; + NvU32 displays; + NvU32 retainMaster; +} NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS; + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SYNC + * + * This command gets the sync state for the gpus attached to the + * framelock device. Note that the frame lock device only has + * knowledge of sync status at the gpu level, not the display + * device level. + * + * gpuId + * The parameter is set by the client to indicate which gpuId is to be + * queried. + * bTiming + * This parameter is set by the RM to indicate that timing on the GPU is + * in sync with the master sync signal. + * bStereoSync + * This parameter is set by the RM to indicate whether the phase of the + * timing signal coming from the GPU is the same as the phase of the + * master sync signal. + * bSyncReady + * This parameter is set by the RM to indicate if a sync signal has + * been detected. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ + +#define NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SYNC (0x30f10113) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS { + NvU32 gpuId; + NvU32 bTiming; + NvU32 bStereoSync; + NvU32 bSyncReady; +} NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS; + + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_STATUS + * + * This command gets status information for the frame lock device + * relevant to a control panel. + * + * which + * This is a mask set by the client describing which of the other + * parameters we should collect status information for. + * bLeadingEdge + * This parameter is set by the RM to indicate that the gsync device is + * set to sync to the leading edge of a house sync signal. Note that + * this does not mean that house sync is the signal source. + * bFallingEdge + * This parameter is set by the RM to indicate that the gsync device is + * set to sync to the falling edge of a house sync signal. Note that + * this does not mean that house sync is the signal source. + * syncDelay + * This parameter is set by the RM to indicate the sync delay in + * microseconds, + * refresh + * This parameter is set by the RM to indicate the rate of frame sync pulse in + * 0.0001 Hertz (i.e. it has been multiplied by 10000). This is not the refresh + * rate of display device. This is same as incoming house sync rate if + * framelocked to an external house sync signal. Otherwise, this is same + * as the refresh rate of the master display device. + * houseSyncIncomming + * This parameter is set by the RM to indicate the rate of an incomming + * house sync signal in 0.0001 Hertz (i.e. it has been multiplied by 10000). + * syncInterval + * This parameter is set by the RM to indicate the number of incoming + * sync pulses to wait before the generation of the frame sync pulse. + * bSyncReady + * This paramater is set by the RM to indicate if a sync signal has + * been detected (this parameter is also available from the + * NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SYNC method). + * bSwapReady + * This paramater is set by the RM to indicate if the hardware is + * ready to swap. + * bHouseSync + * This parameter is set by the RM to indicate that a house sync signal + * should be used as the source signal if it is available. + * bPort0Input + * This parameter is set by the RM to indicate that RJ45 port 0 is + * configured as an input. + * bPort1Input + * This parameter is set by the RM to indicate that RJ45 port 1 is + * configured as an input + * bPort0Ehternet + * This parameter is set by the RM to indicate that RJ45 port 0 has + * been connected to an ethernet hub (this is not the right thing to do). + * bPort1Ehternet + * This parameter is set by the RM to indicate that RJ45 port 1 has + * been connected to an ethernet hub (this is not the right thing to do). + * universalFrameCount + * This parameter is set by the RM to indicate the value of the + * Universal frame counter. + * bInternalSlave + * This parameter is set by the RM to indicate that a p2061 has been + * configured as internal slave. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_STATUS (0x30f10114) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS { + NvU32 which; + NvU32 bLeadingEdge; + NvU32 bFallingEdge; + NvU32 syncDelay; + NvU32 refresh; + NvU32 houseSyncIncoming; + NvU32 syncInterval; + NvU32 bSyncReady; + NvU32 bSwapReady; + NvU32 bHouseSync; + NvU32 bPort0Input; + NvU32 bPort1Input; + NvU32 bPort0Ethernet; + NvU32 bPort1Ethernet; + NvU32 universalFrameCount; + NvU32 bInternalSlave; +} NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS; + +/* + * which values + * + */ + +#define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_POLARITY (0x00000001) +#define NV30F1_CTRL_GSYNC_GET_STATUS_LEADING_EDGE (0x00000001) +#define NV30F1_CTRL_GSYNC_GET_STATUS_FALLING_EDGE (0x00000001) +#define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_DELAY (0x00000002) +#define NV30F1_CTRL_GSYNC_GET_STATUS_REFRESH (0x00000004) +#define NV30F1_CTRL_GSYNC_GET_STATUS_HOUSE_SYNC_INCOMING (0x00000008) +#define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_INTERVAL (0x00000010) +#define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_READY (0x00000020) +#define NV30F1_CTRL_GSYNC_GET_STATUS_SWAP_READY (0x00000040) +#define NV30F1_CTRL_GSYNC_GET_STATUS_TIMING (0x00000080) +#define NV30F1_CTRL_GSYNC_GET_STATUS_STEREO_SYNC (0x00000100) +#define NV30F1_CTRL_GSYNC_GET_STATUS_HOUSE_SYNC (0x00000200) +#define NV30F1_CTRL_GSYNC_GET_STATUS_PORT_INPUT (0x00000400) +#define NV30F1_CTRL_GSYNC_GET_STATUS_PORT0_INPUT (0x00000400) +#define NV30F1_CTRL_GSYNC_GET_STATUS_PORT1_INPUT (0x00000400) +#define NV30F1_CTRL_GSYNC_GET_STATUS_PORT_ETHERNET (0x00000800) +#define NV30F1_CTRL_GSYNC_GET_STATUS_PORT0_ETHERNET (0x00000800) +#define NV30F1_CTRL_GSYNC_GET_STATUS_PORT1_ETHERNET (0x00000800) +#define NV30F1_CTRL_GSYNC_GET_STATUS_UNIVERSAL_FRAME_COUNT (0x00001000) +#define NV30F1_CTRL_GSYNC_GET_STATUS_INTERNAL_SLAVE (0x00002000) + +/* + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_TESTING + * + * This command controls the test signal on the gsync device. + * + * bEmitTestSignal + * This parameter is set by the client to emit or stop emitting the test + * signal. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_TESTING (0x30f10120) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_TESTING (0x30f10121) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS_MESSAGE_ID (0x21U) + +typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS { + NvU32 bEmitTestSignal; +} NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS; +#define NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS_MESSAGE_ID (0x20U) + +typedef NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS; + +/* + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_WATCHDOG + * + * This command enables and disables the gsync watchdog + * + * enable + * This parameter is set by the client to enable or disable the + * gsync watchdog. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + */ +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_WATCHDOG (0x30f10130) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS_MESSAGE_ID (0x30U) + +typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS { + NvU32 enable; +} NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS; + + +/* + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_INTERLACE_MODE + * + * This command enables or disables interlace mode. + * + * enable + * This parameter is set by the client to enable or disable + * interlace mode + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_INTERLACE_MODE (0x30f10140) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_INTERLACE_MODE (0x30f10141) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID (0x41U) + +typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS { + NvU32 enable; +} NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS; +#define NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID (0x40U) + +typedef NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS; + +/* + * + * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SWAP_BARRIER + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SWAP_BARRIER + * + * These commands enables or disables the swap barrier + * connection between a GPU and the rest of the gsync + * network + * + * gpuId + * The parameter is set by the client to indicate which gpuId is to be + * queried. + * enable + * In a set command, this parameter is set by the client to + * indicate if the barrier should be enabled (i.e. connected + * to the rest of the network) or disabled (disconnected). + * In both a set and a get command, if successful, the RM + * uses this parameter to return the current (i.e. post-set) + * value. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SWAP_BARRIER (0x30f10150) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SWAP_BARRIER (0x30f10151) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID (0x51U) + +typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS { + NvU32 gpuId; + NvBool enable; +} NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS; +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID (0x50U) + +typedef NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS; + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW + * + * This command allow clients to obtain time period for which SwapLock window will + * remain HIGH for GSYNC III (P2060) i.e. TswapRdyHi. RM clients will use this value + * for programming SWAP_LOCKOUT_START on all heads of GPU connected to P2060. + * + * tSwapRdyHi + * RM will return swap lock window High time period in this variable. By default + * tSwapRdyHi is 250 micro seconds. RM also provide regkey to change this value. + * tSwapRdyHi also used by RM to configure value of LSR_MIN_TIME while programming + * swap barrier. + * Client should consider tSwapRdyHi only for Gsync III (P2060) network. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW (0x30f10153) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS_MESSAGE_ID (0x53U) + +typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS { + NvU32 tSwapRdyHi; +} NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS; + + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_OPTIMIZED_TIMING + * + * This command allows the client to obtain suggested + * adjustments to vertical and horizontal timing values + * that will improve the ability of gsync to lock. + * + * gpuId + * This parameter is set by the client to indicate the + * gpuId of the GPU to which the display to be optimized + * is attached. + * display + * This parameter is not used by RM currently. + * Clients can ignore this parameter. Note that this + * parameter will be removed in future. + * output + * This parameter is set by the client to indicate the + * output resource type of the display to be optimized. + * For example, CRTs use DAC output, while DFPs use SOR + * (Serial Output Resource) type. + * protocol + * This parameter is set by the client to indicate the + * data protocol of output resource. For DAC displays, + * the format of the standard mode most closely matching + * the desired mode is used. For SOR display devices, + * the LVDS/TMDS/etc format is the protocol. + * structure + * This parameter is set by the client to indicate the + * raster structure of the mode, either progressive or + * interlaced. Diagrams of the raster structures are + * provided below. + * adjust + * This parameter is set by the client to specify which + * of the timing values, other than hTotal and vTotal, + * may be adjusted during optimization. + * If the client does not obtain instructions from the + * user about where adjustments should be applied, safe + * default values for progressive/interlaced modes are + * provided below. + * hTotal + * This parameter is set by the client to specify the + * initial Horizontal Pixel Total, from which the + * RM will begin optimizing. The RM also uses the + * parameter to return the optimized value. + * vTotal + * This parameter is set by the client to specify the + * initial Vertical Pixel Total, from which the + * RM will begin optimizing. The RM also uses the + * parameter to return the optimized value. + * hBlankStart + * This parameter is set by the client to specify the + * initial Horizontal Blanking Start, from which the + * RM will begin optimizing. The RM also uses the + * parameter to return the optimized value. + * vBlankStart + * This parameter is set by the client to specify the + * initial Vertical Blanking Start, from which the + * RM will begin optimizing. The RM also uses the + * parameter to return the optimized value. + * hBlankEnd + * This parameter is set by the client to specify the + * initial Horizontal Blanking End, from which the + * RM will begin optimizing. The RM also uses the + * parameter to return the optimized value. + * vBlankEnd + * This parameter is set by the client to specify the + * initial Vertical Blanking End, from which the + * RM will begin optimizing. The RM also uses the + * parameter to return the optimized value. + * vInterlacedBlankStart + * This parameter is set by the client to specify the + * initial Interlaced Vertical Blanking Start, from + * which the RM will begin optimizing. The RM will + * ignore this parameter for non-interlaced modes, as + * it has no meaning in those modes. In modes where + * it is meaningful, the RM also uses the parameter + * to return the optimized value. + * vInterlacedBlankEnd + * This parameter is set by the client to specify the + * initial Interlaced Vertical Blanking End, from + * which the RM will begin optimizing. The RM will + * ignore this parameter for non-interlaced modes, as + * it has no meaning in those modes. In modes where + * it is meaningful, the RM also uses the parameter + * to return the optimized value. + * hSyncEnd + * This parameter is set by the client to specify the + * initial Horizontal Raster Sync End, from which the + * RM will begin optimizing. The RM also uses the + * parameter to return the optimized value. + * vSyncEnd + * This parameter is set by the client to specify the + * initial Vertical Raster Sync End, from which the + * RM will begin optimizing. The RM also uses the + * parameter to return the optimized value. + * hDeltaStep + * This parameter is set by the client to specify the + * increments by which the Horizontal Pixel Total may + * be adjusted by the RM, during optimization. + * If the client does not obtain a custom value for + * this parameter from the user, setting all four of + * hDeltaStep, vDeltaStep, hDeltaMax, and vDeltaMax + * to zero will result in a safe default for all four. + * vDeltaStep + * This parameter is set by the client to specify the + * increments by which the vertical timings of each + * frame (in interlaced modes, each field) may be + * adjusted by the RM, during optimization. + * In interlaced modes, the adjustments to vTotal, + * vInterlacedBlankStart, and vInterlacedBlankEnd may + * be in increments of vDeltaStep or twice vDeltaStep, + * depending on where adjustments are made. + * In progressive modes, the adjustment to the vTotal + * will simply be in increments of vDeltaStep. + * If the client does not obtain a custom value for + * this parameter from the user, setting all four of + * hDeltaStep, vDeltaStep, hDeltaMax, and vDeltaMax + * to zero will result in a safe default for all four. + * hDeltaMax + * This parameter is set by the client to specify the + * maximum amount that the Horizontal Pixel Total may + * be adjusted by the RM, during optimization. + * If the client does not obtain a custom value for + * this parameter from the user, setting all four of + * hDeltaStep, vDeltaStep, hDeltaMax, and vDeltaMax + * to zero will result in a safe default for all four. + * vDeltaMax + * This parameter is set by the client to specify the + * maximum amount that vertical timings of each frame + * (in interlaced modes, each field) may be adjusted + * by the RM, during optimization. + * In interlaced modes, the adjustments to vTotal, + * vInterlacedBlankStart, and vInterlacedBlankEnd may + * be up to twice vDeltaMax. + * In progressive modes, the adjustment to the vTotal + * may simply be up to vDeltaMax. + * If the client does not obtain a custom value for + * this parameter from the user, setting all four of + * hDeltaStep, vDeltaStep, hDeltaMax, and vDeltaMax + * to zero will result in a safe default for all four. + * refreshX10K + * This parameter is set by the client to specify the + * desired refresh rate, multiplied by 10000. This + * allows refresh rate to be set in units of 0.0001 Hz. + * For example, a 59.94 Hz rate would be set as 599400. + * The client can alternatively specify a the + * pixelClockHz parameter (if the passed in refreshX10K + * parameter is set to 0, the pixelClockHz parameter + * will be used). + * pixelClockHz + * This parameter is set by the client to specify the + * desired pixel clock frequency in units of Hz. The + * client can alternatively specify the refreshX10K parameter. + * This parameter is returned by the RM to report the + * optimal pixel clock to use with the adjusted mode, + * in units of Hz. + * + * Progressive Raster Structure + * + * hSyncEnd hTotal + * 0 | hBlankEnd hBlankStart | + * | | | | | vSync vBlank + * 0--+--------------------------------------------+ +-+ | + * | Sync | | | + * vSyncEnd--| +----------------------------------------+ +-+ | + * | | Back Porch | | | + * vBlankEnd--| | +--------------------------------+ | | +-+ + * | | | Active Area | | | | + * | | | +------------------------+ | | | | + * | | | | | | | | | + * | S | B | A | | A | F | | | + * | y | a | c | | c | r | | | + * | n | c | t | | t | o | | | + * | c | k | i | | i | n | | | + * | | | v | | v | t | | | + * | | P | e | Output Viewport | e | | | | + * | | o | | | | P | | | + * | | r | A | | A | o | | | + * | | c | r | | r | r | | | + * | | h | e | | e | c | | | + * | | | a | | a | h | | | + * | | | | | | | | | + * | | | +------------------------+ | | | | + * | | | Active Area | | | | + * vBlankStart-| | +--------------------------------+ | | +-+ + * | | Front Porch | | | + * vTotal--+---+----------------------------------------+ +-+ | + * ___ + * / \________________________________________/ hSync + * ________ ____ + * \________________________________/ hBlank + * + * + * + * Interlaced Raster Structure + * + * hSyncEnd hTotal + * 0 | hBlankEnd hBlankStart | + * | | | | | vSync vBlank + * 0--+--------------------------------------------+ +-+ | + * | Sync | | | + * vSyncEnd--| +----------------------------------------+ +-+ | + * | | Back Porch | | | + * vBlankEnd--| | +--------------------------------+ | | +-+ + * | | | Active Area | | | | + * | | | +------------------------+ | | | | + * | | | | | | | | | + * | S | B | A | | A | F | | | + * | y | a | c | | c | r | | | + * | n | c | t | | t | o | | | + * | c | k | i | | i | n | | | + * | | | v | | v | t | | | + * | | P | e | Output Viewport | e | | | | + * | | o | | | | P | | | + * | | r | A | | A | o | | | + * | | c | r | | r | r | | | + * | | h | e | | e | c | | | + * | | | a | | a | h | | | + * | | | | | | | | | + * | | | +------------------------+ | | | | + * | | | Active Area | | | | + * vBlankStart-| | +--------------------------------+ | | +-+ + * | | | | | + * | | Front Porch +--------------------+ | | + * | | | | +-+ | + * | +-------------------+ | | | + * | | | | + * | Sync +--------------------+ | | + * | | | +-+ | + * | +-------------------+ | | | + * vInterlaced | | Back Porch | | | + * BlankEnd--| | +--------------------------------+ | | +-+ + * | | | Active Area | | | | + * | | | +------------------------+ | | | | + * | | | | | | | | | + * | S | B | A | | A | F | | | + * | y | a | c | | c | r | | | + * | n | c | t | | t | o | | | + * | c | k | i | | i | n | | | + * | | | v | | v | t | | | + * | | P | e | Output Viewport | e | | | | + * | | o | | | | P | | | + * | | r | A | | A | o | | | + * | | c | r | | r | r | | | + * | | h | e | | e | c | | | + * | | | a | | a | h | | | + * | | | | | | | | | + * | | | +------------------------+ | | | | + * vInterlaced | | | Active Area | | | | + * BlankStart-| | +--------------------------------+ | | +-+ + * | | Front Porch | | | + * vTotal--+---+----------------------------------------+ +-+ | + * ___ + * / \________________________________________/ hSync + * ________ ____ + * \________________________________/ hBlank + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * +*/ + +#define NV30F1_CTRL_CMD_GSYNC_GET_OPTIMIZED_TIMING (0x30f10160) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS_MESSAGE_ID (0x60U) + +typedef struct NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS { + NvU32 gpuId; + NvU32 display; + NvU32 output; + NvU32 protocol; + NvU32 structure; + NvU32 adjust; + NvU32 hDeltaStep; + NvU32 hDeltaMax; + NvU32 vDeltaStep; + NvU32 vDeltaMax; + NvU32 hSyncEnd; + NvU32 hBlankEnd; + NvU32 hBlankStart; + NvU32 hTotal; + NvU32 vSyncEnd; + NvU32 vBlankEnd; + NvU32 vBlankStart; + NvU32 vInterlacedBlankEnd; + NvU32 vInterlacedBlankStart; + NvU32 vTotal; + NvU32 refreshX10K; + NvU32 pixelClockHz; +} NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS; + +/* output values */ +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_OUTPUT_DAC (0x00000001) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_OUTPUT_SOR (0x00000004) + +/* protocol values for DAC displays (e.g. CRTs) */ +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_DAC_RGB_CRT (0x00000000) + +/* protocol values for SOR displays (e.g. DFPs) */ +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_LVDS_CUSTOM (0x00000000) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_SINGLE_TMDS_A (0x00000001) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_SINGLE_TMDS_B (0x00000002) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_DUAL_TMDS (0x00000005) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_DP_A (0x00000008) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_DP_B (0x00000009) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_HDMI_FRL (0x0000000C) + +/* structure values */ +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_STRUCTURE_INTERLACED (0x00000001) + +/* adjust values */ +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_H_FRONT_PORCH (0x00000001) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_V_FRONT_PORCH (0x00000002) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_H_ACTIVE_AREA (0x00000004) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_V_ACTIVE_AREA (0x00000008) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_H_BACK_PORCH (0x00000010) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_V_BACK_PORCH (0x00000020) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_H_RASTER_SYNC (0x00000040) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_V_RASTER_SYNC (0x00000080) + +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_DEFAULT_CRT (0x00000030) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_DEFAULT_DFP (0x00000020) + +/* DeltaStep and DeltaMax values to trigger default settings */ +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_H_DELTA_STEP_USE_DEFAULTS (0x00000000) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_H_DELTA_MAX_USE_DEFAULTS (0x00000000) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_V_DELTA_STEP_USE_DEFAULTS (0x00000000) +#define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_V_DELTA_MAX_USE_DEFAULTS (0x00000000) + +/* + * NV30F1_CTRL_CMD_GSYNC_SET_EVENT_NOTIFICATION + * + * This command sets event notification state for the associated Gsync + * object. This command requires that an instance of NV01_EVENT has + * been previously bound to the associated Gsync object. + * + * If one or more of the "smart event notification" options are set in the + * action parameter, multiple sequential events of the same type will only + * trigger one notification. After that, only an event of a different type + * will trigger a new notification. + * + * action + * This member specifies the desired event notification action. + * Valid notification actions include: + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_DISABLE + * This action disables event notification for the associated + * Gsync object. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_LOSS + * This action enables smart event notification for the + * associated Gsync object, for "sync loss" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_GAIN + * This action enables smart event notification for the + * associated Gsync object, for "sync gained" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_STEREO_LOSS + * This action enables smart event notification for the + * associated Gsync object, for "stereo lost" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_STEREO_GAIN + * This action enables smart event notification for the + * associated Gsync object, for "stereo gained" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_HOUSE_GAIN + * This action enables smart event notification for the + * associated Gsync object, for "house sync (BNC) plug in" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_HOUSE_LOSS + * This action enables smart event notification for the + * associated Gsync object, for "house sync (BNC) plug out" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_RJ45_GAIN + * This action enables smart event notification for the + * associated Gsync object, for "ethernet (RJ45) plug in" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_RJ45_LOSS + * This action enables smart event notification for the + * associated Gsync object, for "ethernet (RJ45) plug out" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_COUNT_MATCH + * This action enables smart event notification for the + * associated Gsync object, for "frame counter match" events. + * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_ALL + * This action enables smart event notification for the + * associated Gsync object, for any type of event. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV30F1_CTRL_CMD_GSYNC_SET_EVENT_NOTIFICATION (0x30f10170) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS_MESSAGE_ID (0x70U) + +typedef struct NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS { + NvU32 action; +} NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS; + +/* valid action values */ + +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_LOSS (0x00000001) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_GAIN (0x00000002) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_STEREO_LOSS (0x00000004) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_STEREO_GAIN (0x00000008) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_HOUSE_GAIN (0x00000010) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_HOUSE_LOSS (0x00000020) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_RJ45_GAIN (0x00000040) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_RJ45_LOSS (0x00000080) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_COUNT_MATCH (0x00000100) +#define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_ALL (0x000001FF) + +#define NV30F1_CTRL_GSYNC_EVENT_TYPES 9 + +/* + * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE + * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE + * + * These commands can be used to get/set the stereo lock assistance mode of + * the GSYNC device. This is supported by GSYNC III device only. + * 1] In this mode the GSYNC recreates the hidden VS either by -> + * (a) using local stereo edge if stereo is toggle or + * (b) counting lines and generate the missing VS. + * 2] Master GSYNC card recreates the stereo and passes it along to + * the slave GSYNC cards. + * 3] Slave GSYNC cards generates the stereo raster sync structure to + * synchronize the GPU. + * 4] For stereo sync status reporting, under this mode, the GSYNC automatically + * reports stereo lock whenever it gets the master stereo signal. The + * assumption is local stereo will be in synced with the new structure. + * 5] If the slave GSYNC card does not observed master stereo for any reason, + * (a) it clears the stereo sync bit and + * (b) it generates its own version of stereo and sync the GPU. + * + * Parameters: + * gpuId + * This parameter is set by the client to indicate the gpuId on which + * the stereo lock mode should be enabled/disabled. + * + * enable + * In SET query, this parameter is set by the client to indicate whether + * RM should enable or disable stereo lock mode for GPU specified in gpuId. + * 1 and 0 indicates enable and disable stereo lock mode respectively. In + * GET query, RM will set this parameter to 1 or 0 depending on StereoLock + * mode is enabled or not respectively for specified GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE (0x30f10172) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE (0x30f10173) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID (0x72U) + +typedef struct NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS { + NvU32 gpuId; + NvU32 enable; +} NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS; +#define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID (0x73U) + +typedef NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS; + +/* + * NV30F1_CTRL_CMD_GSYNC_READ_REGISTER + * + * This command is used to read raw i2c registers from the gsync device, via + * the given GPU (registers on the same gsync device may have different values + * depending on which GPU is used to do the read). + * + * This may only be used by a privileged client. + * + * Parameters: + * gpuId + * This parameter is set by the client to specify which GPU to use to + * perform the read. + * + * reg + * This parameter is set by the client to specify which i2c register to + * read. + * + * data + * This parameter is written by the RM and returned to the client upon a + * successful read. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +#define NV30F1_CTRL_CMD_GSYNC_READ_REGISTER (0x30f10180) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS_MESSAGE_ID (0x80U) + +typedef struct NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS { + NvU32 gpuId; + NvU8 reg; + NvU8 data; +} NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS; + +/* + * NV30F1_CTRL_CMD_GSYNC_WRITE_REGISTER + * + * This command is used to write raw i2c registers on the gsync device, via the + * given GPU (registers on the same gsync device may have different values + * depending on which GPU is used to do the write). + * + * This may only be used by a privileged client. + * + * Parameters: + * gpuId + * This parameter is set by the client to specify which GPU to use to + * perform the write. + * + * reg + * This parameter is set by the client to specify which i2c register to + * write. + * + * data + * This parameter is set by the client to specify what data to write to the + * given i2c register. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ + +#define NV30F1_CTRL_CMD_GSYNC_WRITE_REGISTER (0x30f10181) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS { + NvU32 gpuId; + NvU8 reg; + NvU8 data; +} NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS; + + + +/* + * NV30F1_CTRL_CMD_GSYNC_SET_LOCAL_SYNC + * + * This command enables/disables raster sync on displays i.e. + * mosaic groups between gpus. + * + * gpuTimingSource + * The parameter is set by the client to indicate the gpuId of the + * Timing Source gpu for specified mosaic group. + * gpuTimingSlaves[] + * This parameter is set by the client to indicate the gpuIds of the + * timing slave gpus for specified mosaic group. It should not contain + * more gpuids than slaveGpuCount. + * slaveGpuCount + * This parameter is set by the client to indicate the count of timing + * slave gpus under specified group. + * Referring to gsync3-P2060, slaveGpuCount can vary from 0x01 to 0x03 + * as maximum possible connected gpus are four and one gpu must be + * timing master for mosaic group. + * mosaicGroupNumber + * This parameter is set by the client to tell the RM to which mosaic + * group it should refer. + * Referring to gsync3-P2060, mosaicGroupNumber can contain 0x00 or + * 0x01 as only two mosaic groups are possible. + * enableMosaic + * This parameter is set by the client to indicate RM that whether RM + * should enable mosaic or disable mosaic. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV30F1_CTRL_CMD_GSYNC_SET_LOCAL_SYNC (0x30f10185) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS_MESSAGE_ID (0x85U) + +typedef struct NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS { + NvU32 gpuTimingSource; + NvU32 gpuTimingSlaves[NV30F1_CTRL_MAX_GPUS_PER_GSYNC]; + NvU32 slaveGpuCount; + NvU32 mosaicGroupNumber; + NvBool enableMosaic; +} NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS; + +/* + * NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH + * + * This command configure GSYNC registers for pre-flash and post-flash + * operations. This is currenly used for GSYNC-3 (P2060) only. RM clients + * has to make sure that they perform both pre-flash and post-flash + * operations on GSYNC board. Avoiding, post-flash will cause mismatch + * between RM cached-data and GSYNC register values. + * + * Parameters: + * gpuId + * This parameter is set by the client to indicate the gpuId for which + * GSYNC board connected to that GPU will be configured for pre-flash + * or post-flash operation depending on preFlash value. + * + * preFlash + * This parameter is set by the client to indicate whether RM has to configure + * GSYNC registers and SW state for pre-flash or post-flash operation. Values + * 1 and 0 indicates that RM will configure GSYNC board for pre-flash and + * post-flash operations respectively. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH (0x30f10186) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS_MESSAGE_ID (0x86U) + +typedef struct NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS { + NvU32 gpuId; + NvU32 preFlash; +} NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS; + +/* + * NV30F1_CTRL_CMD_GSYNC_GET_HOUSE_SYNC_MODE + * NV30F1_CTRL_CMD_GSYNC_SET_HOUSE_SYNC_MODE + * + * These two commands gets/sets house sync mode as input or output. + * + * Parameters: + * houseSyncMode + * This parameter indicates whether the house sync mode is input or + * output. For GET_HOUSE_SYNC_MODE, the current mode will be written + * by RM and returned to the client; for SET_HOUSE_SYNC_MODE, the client + * will write the new mode value to this parameter and pass it to RM + * for execution. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_STATE + * + */ +#define NV30F1_CTRL_CMD_GSYNC_GET_HOUSE_SYNC_MODE (0x30f10187) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | 0x87" */ + +#define NV30F1_CTRL_CMD_GSYNC_SET_HOUSE_SYNC_MODE (0x30f10188) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | 0x88" */ + +typedef struct NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS { + NvU8 houseSyncMode; +} NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS; + + +#define NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_INPUT (0x00) +#define NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_OUTPUT (0x01) + +/* _ctrl30f1_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl402c.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl402c.h new file mode 100644 index 0000000..eb9bef5 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl402c.h @@ -0,0 +1,971 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl402c.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV40_I2C control commands and parameters */ +#define NV402C_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0x402C, NV402C_CTRL_##cat, idx) + +/* I2C command categories (6 bits) */ +#define NV402C_CTRL_RESERVED (0x00) +#define NV402C_CTRL_I2C (0x01) + + +/* This field specifies the maximum regular port identifier allowed. */ +#define NV402C_CTRL_NUM_I2C_PORTS 16 +/* This temporary field specifies the dynamic port identifier. */ +#define NV402C_CTRL_DYNAMIC_PORT NV_U8_MAX + +/* + * NV402C_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV402C_CTRL_CMD_NULL (0x402c0000) /* finn: Evaluated from "(FINN_NV40_I2C_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV402C_CTRL_I2C_GET_PORT_INFO_IMPLEMENTED + * The port exists on this hardware. + * NV402C_CTRL_I2C_GET_PORT_INFO_DCB_DECLARED + * The port has an entry in the DCB. + * NV402C_CTRL_I2C_GET_PORT_INFO_DDC_CHANNEL + * The port is used to read EDIDs via DDC. + * NV402C_CTRL_I2C_GET_PORT_INFO_CRTC_MAPPED + * The port is accessible via the CRTC register space. + * NV402C_CTRL_I2C_GET_PORT_INFO_VALID + * The port is validated using I2C device. + */ +#define NV402C_CTRL_I2C_GET_PORT_INFO_IMPLEMENTED 0:0 +#define NV402C_CTRL_I2C_GET_PORT_INFO_IMPLEMENTED_NO 0x00 +#define NV402C_CTRL_I2C_GET_PORT_INFO_IMPLEMENTED_YES 0x01 +#define NV402C_CTRL_I2C_GET_PORT_INFO_DCB_DECLARED 1:1 +#define NV402C_CTRL_I2C_GET_PORT_INFO_DCB_DECLARED_NO 0x00 +#define NV402C_CTRL_I2C_GET_PORT_INFO_DCB_DECLARED_YES 0x01 +#define NV402C_CTRL_I2C_GET_PORT_INFO_DDC_CHANNEL 2:2 +#define NV402C_CTRL_I2C_GET_PORT_INFO_DDC_CHANNEL_ABSENT 0x00 +#define NV402C_CTRL_I2C_GET_PORT_INFO_DDC_CHANNEL_PRESENT 0x01 +#define NV402C_CTRL_I2C_GET_PORT_INFO_CRTC_MAPPED 3:3 +#define NV402C_CTRL_I2C_GET_PORT_INFO_CRTC_MAPPED_NO 0x00 +#define NV402C_CTRL_I2C_GET_PORT_INFO_CRTC_MAPPED_YES 0x01 +#define NV402C_CTRL_I2C_GET_PORT_INFO_VALID 4:4 +#define NV402C_CTRL_I2C_GET_PORT_INFO_VALID_NO 0x00 +#define NV402C_CTRL_I2C_GET_PORT_INFO_VALID_YES 0x01 +#define NV402C_CTRL_I2C_GET_PORT_INFO_ALL 4:0 +#define NV402C_CTRL_I2C_GET_PORT_INFO_ALL_DEFAULT 0x00 + +/* + * NV402C_CTRL_CMD_I2C_GET_PORT_INFO + * + * Returns information for the first eight I2C ports. + * + * info + * This parameter is an output from the command and is ignored as an + * input. Each element contains the flags described previously named + * NV402C_CTRL_I2C_GET_PORT_INFO*. Note that the index into the info + * array is one less than the port identifier that would be returned from + * NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID; the port numbers here are + * 0-indexed as opposed to 1-indexed. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + + +#define NV402C_CTRL_CMD_I2C_GET_PORT_INFO (0x402c0101) /* finn: Evaluated from "(FINN_NV40_I2C_I2C_INTERFACE_ID << 8) | NV402C_CTRL_I2C_GET_PORT_INFO_PARAMS_MESSAGE_ID" */ + + + +#define NV402C_CTRL_I2C_GET_PORT_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV402C_CTRL_I2C_GET_PORT_INFO_PARAMS { + NvU8 info[NV402C_CTRL_NUM_I2C_PORTS]; +} NV402C_CTRL_I2C_GET_PORT_INFO_PARAMS; +#define NV402C_CTRL_I2C_INDEX_LENGTH_MAX 4 +#define NV402C_CTRL_I2C_MESSAGE_LENGTH_MAX 4096 + +//! Minimum and maximum valid read/write message length for block process protocol. +#define NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MIN 3 +#define NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX 32 + +/* + * NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE + * A client uses this field to indicate the I2C addressing mode to be + * used. + * Possible values are: + * NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE_7BIT + * The default, this value specifies the master to operate in the + * basic 7-bit addressing mode, which is available on all + * implementations. + * NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE_10BIT + * This I2C mode allows for 10 bits of addressing space and is + * reverse compatible with 7-bit addressing. + */ +#define NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE 0:0 +#define NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE_7BIT (0x00000000) +#define NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE_10BIT (0x00000001) +#define NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE_DEFAULT NV402C_CTRL_I2C_FLAGS_ADDRESS_MODE_7BIT +/* + * NV402C_CTRL_I2C_FLAGS_SPEED_MODE + * A client uses this field to indicate the target speed at which the + * I2C master should attempt to drive the bus. The master may throttle + * its own speed for various reasons, and devices may slow the bus + * using clock-streching. Neither of these possibilities are + * considered failures. + */ +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE 4:1 +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_100KHZ (0x00000000) +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_200KHZ (0x00000001) +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_400KHZ (0x00000002) +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_33KHZ (0x00000003) +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_10KHZ (0x00000004) +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_3KHZ (0x00000005) +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_DEFAULT (0x00000006) +#define NV402C_CTRL_I2C_FLAGS_SPEED_MODE_300KHZ (0x00000007) + + +/* + * NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE + * A client uses this field to specify a transaction mode. + * Possible values are: + * NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE_NORMAL + * The default, this value indicates to use the normal I2C transaction + * mode which will involve read/write operations depending on client's + * needs. + * NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE_PING + * This value specifies that the device only needs to be pinged. No need + * of performing a complete read/write transaction. This will send a + * single byte to the device to be pinged. On receiving an ACK, we will + * get a confirmation on the device's availability. + */ +#define NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE 11:10 +#define NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE_NORMAL (0x00000000) +#define NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE_PING (0x00000001) +#define NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE_DEFAULT NV402C_CTRL_I2C_FLAGS_TRANSACTION_MODE_NORMAL +/*! + * NV402C_CTRL_I2C_FLAGS_RESERVED + * A client must leave this field as 0, as it is reserved for future use. + */ +#define NV402C_CTRL_I2C_FLAGS_RESERVED 31:12 + +/*! + * The following defines specify WAR flags that can be specified during + * I2C Quick Read or Write command (Refer NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW). + * + * _NONE + * No workaround is needed. + * + * _TEST_PORT + * Use this flag to have the client sent a request to test a port instead + * of performing any transaction on it. Transaction type has to be + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW. + */ +#define NV402C_CTRL_I2C_SMBUS_QUICK_RW_WAR_FLAGS 0:0 +#define NV402C_CTRL_I2C_SMBUS_QUICK_RW_WAR_FLAGS_NONE 0x00000000 +#define NV402C_CTRL_I2C_SMBUS_QUICK_RW_WAR_FLAGS_TEST_PORT 0x00000001 + +/*! + * The following defines specify WAR flags that can be specified during + * I2C Register Read or Write buffer command + * (Refer NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW) + * + * _NONE + * No workaround is needed. + * + * _SI1930 + * SI1930 microcontroller register read or write requested by a client. + * Transaction type has to be NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW. + * + * _PX3540 + * Register read from PX3540 or PX3544 device. Transaction type has to be + * NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW and bWrite must be TRUE to + * indicate READ operation + */ +#define NV402C_CTRL_I2C_BUFFER_RW_WAR_FLAGS 1:0 +#define NV402C_CTRL_I2C_BUFFER_RW_WAR_FLAGS_NONE 0x00000000 +#define NV402C_CTRL_I2C_BUFFER_RW_WAR_FLAGS_SI1930 0x00000001 +#define NV402C_CTRL_I2C_BUFFER_RW_WAR_FLAGS_PX3540 0x00000002 + +/*! + * The following defines specify WAR flags that can be specified during + * I2C buffer Read or Write to Multibyte Register + * (Refer NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW) + * + * _NONE + * No workaround is needed. + * + * _NO_AUTO_INC + * This value specifies that the device does not support auto-increment. + * Most devices allow you to write multiple bytes after specifying a + * register address, and the subsequent bytes will go to incremented + * addresses. Without auto-increment, we write a buffer of data as a + * sequence of address-register-value triplets separated by starts. + */ +#define NV402C_CTRL_I2C_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW_WAR_FLAGS 0:0 +#define NV402C_CTRL_I2C_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW_WAR_FLAGS_NONE 0x00000000 +#define NV402C_CTRL_I2C_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW_WAR_FLAGS_NO_AUTO_INC 0x00000001 + +/* + * NV402C_CTRL_CMD_I2C_SYNC + * + * Perform a basic I2C transaction synchronously. + * + * portId + * This field must be specified by the client to indicate the logical + * port/bus for which the transaction is requested. The port identifier + * is one less than the value returned by + * NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID unless that value was 0 (the + * 'dynamic' port). For the 'dynamic' port, this should be 0xFF. Note + * that future versions of the API may obsolete use of the 'dynamic' port; + * please contact the RM if you begin using this portion of the API so we + * can help you migrate when the time comes. + * + * bIsWrite + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + * + * flags + * This parameter specifies optional flags used to control certain modal + * features such as target speed and addressing mode. The currently + * defined fields are described previously; see NV402C_I2C_FLAGS_*. + * + * address + * The address of the I2C slave. The address should be shifted left by + * one. For example, the I2C address 0x50, often used for reading EDIDs, + * would be stored here as 0xA0. This matches the position within the + * byte sent by the master, as the last bit is reserved to specify the + * read or write direction. + * + * indexLength + * This required parameter specifies how many bytes to write as part of the + * first index. If zero is specified, then no index will be sent. + * + * index + * This parameter, required of the client if index is one or more, + * specifies the index to be written. The buffer should be arranged such + * that index[0] will be the first byte sent. + * + * messageLength + * This parameter, required of the client, specifies the number of bytes to + * read or write from the slave after the index is written. + * + * pMessage + * This parameter, required of the client, specifies the data to be written + * to the slave. The buffer should be arranged such that pMessage[0] will + * be the first byte read or written. If the transaction is a read, then + * it will follow the combined format described in the I2C specification. + * If the transaction is a write, the message will immediately follow the + * index without a restart. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_STATE_IN_USE + * NV_ERR_GENERIC, if the I2C transaction fails. + */ +#define NV402C_CTRL_I2C_INDEXED_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV402C_CTRL_I2C_INDEXED_PARAMS { + NvU8 portId; + NvU8 bIsWrite; + NvU16 address; + NvU32 flags; + + NvU32 indexLength; + NvU8 index[NV402C_CTRL_I2C_INDEX_LENGTH_MAX]; + + NvU32 messageLength; + NV_DECLARE_ALIGNED(NvP64 pMessage, 8); +} NV402C_CTRL_I2C_INDEXED_PARAMS; + +#define NV402C_CTRL_CMD_I2C_INDEXED (0x402c0102) /* finn: Evaluated from "(FINN_NV40_I2C_I2C_INTERFACE_ID << 8) | NV402C_CTRL_I2C_INDEXED_PARAMS_MESSAGE_ID" */ + +/* + * NV402C_CTRL_CMD_I2C_GET_PORT_SPEED + * + * Returns information for the I2C ports. + * + * portSpeed + * This parameter is an output from the command and is ignored as an + * input. Each element contains the current I2C speed of the port. + * Note that the index into the info array is one less than the + * port identifier that would be returned from + * NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID; the port numbers here are + * 0-indexed as opposed to 1-indexed. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV402C_CTRL_I2C_GET_PORT_SPEED_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV402C_CTRL_I2C_GET_PORT_SPEED_PARAMS { + NvU32 portSpeed[NV402C_CTRL_NUM_I2C_PORTS]; +} NV402C_CTRL_I2C_GET_PORT_SPEED_PARAMS; + +#define NV402C_CTRL_CMD_I2C_GET_PORT_SPEED (0x402c0103) /* finn: Evaluated from "(FINN_NV40_I2C_I2C_INTERFACE_ID << 8) | NV402C_CTRL_I2C_GET_PORT_SPEED_PARAMS_MESSAGE_ID" */ + +/* + * NV402C_CTRL_I2C_DEVICE_INFO + * + * This structure describes the basic I2C Device information. + * + * type + * This field return the type of device NV_DCB4X_I2C_DEVICE_TYPE_ + * i2cAddress + * This field contains the 7 bit/10 bit address of the I2C device. + * i2cLogicalPort + * This field contains the Logical port of the I2C device. + */ +typedef struct NV402C_CTRL_I2C_DEVICE_INFO { + NvU8 type; + NvU16 i2cAddress; + NvU8 i2cLogicalPort; + NvU8 i2cDevIdx; +} NV402C_CTRL_I2C_DEVICE_INFO; + +/* Maximum number of I2C devices in DCB */ +#define NV402C_CTRL_I2C_MAX_DEVICES 32 + +/* + * NV402C_CTRL_CMD_I2C_TABLE_GET_DEV_INFO + * + * RM Control to get I2C device info from the DCB I2C Devices Table. + * + * i2cDevCount + * The value of this parameter will give the number of + * I2C devices found in DCB. + * + * i2cDevInfo + * For each device found in DCB the control call will write the info + * in this parameter. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV402C_CTRL_I2C_TABLE_GET_DEV_INFO_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV402C_CTRL_I2C_TABLE_GET_DEV_INFO_PARAMS { + NvU8 i2cDevCount; + NV402C_CTRL_I2C_DEVICE_INFO i2cDevInfo[NV402C_CTRL_I2C_MAX_DEVICES]; +} NV402C_CTRL_I2C_TABLE_GET_DEV_INFO_PARAMS; + +#define NV402C_CTRL_CMD_I2C_TABLE_GET_DEV_INFO (0x402c0104) /* finn: Evaluated from "(FINN_NV40_I2C_I2C_INTERFACE_ID << 8) | NV402C_CTRL_I2C_TABLE_GET_DEV_INFO_PARAMS_MESSAGE_ID" */ + +/*! + * The IDs of each type of I2C command available. + */ +typedef enum NV402C_CTRL_I2C_TRANSACTION_TYPE { + /*! + * This transaction type is used to perform the Quick SMBus Read/write command + * on a slave device. No data is sent or received, just used to verify the + * presence of the device. + * Refer SMBus spec 2.0 (section 5.5.1 Quick Command) + * SMBus Quick Write : S Addr|Wr [A] P + * SMBus Quick Read : S Addr|Rd [A] P + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW = 0, + /*! + * This transaction type is used to perform the I2C byte read/write from/to + * a slave device. As per the spec last byte should be NA (Not Acknolwedged) + * by slave. + * Refer I2CBus spec 3.0 (section 9 Fig 11 and Fig 12) or Refer SMBus spec + * 2.0 (section 5.5.2 Send Byte and 5.5.3 Receive Byte). + * I2C Byte Write : S Addr|Wr [A] Data [NA] P + * I2C Byte Read : S Addr|Rd [A] Data NA P + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW = 1, + /*! + * This transaction type is used to perform the I2C block (buffer) + * read/write from/to a slave device. As per the spec last byte should be NA + * (Not Acknolwedged) by slave. + * Refer I2CBus spec 3.0 (section 9 Fig 11 and Fig 12) + * I2C Byte Write : S Addr|Wr [A] Data1 [A]...Data(N-1) [A] DataN [NA] P + * I2C Byte Read : S Addr|Rd [A] Data1 A...Data(N-1) A DataN NA P + * + * Distinction between I2C_BLOCK and SMBUS_BLOCK protocol: + * In I2C Block write it is the slave device (and in I2C Block read it's + * the master device) that determines the number of bytes to transfer by + * asserting the NAK at last bit before stop. This differs from the SMBus + * block mode write command in which the master determines the block + * write transfer size. In I2c Block read there is no limit to maximum size + * of data that could be transferred whereas in SMBus block it is restricted + * to 255 bytes (0xFF). + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW = 2, + /*! + * This transaction type is used to perform the I2C Buffer read/write + * from/to a register of a slave device. It does not send bytecount as + * part of data buffer. + * Not a part of SMBus spec. + * I2C Buffer Write : S Addr|Wr [A] cmd [A] Data1 [A]...DataN[A] P + * I2C Buffer Read : S Addr|Wr [A] cmd [A] Sr Addr|Rd [A] Data1 A... + * DataN-1 A DataN A P + * + * Distinction between SMBUS_BLOCK and I2C_BUFFER protocol: + * In SMBUS_BLOCK Read/write the first byte of data buffer contains the + * count size (The number of bytes to be transferred) and it is restricted + * to 255 bytes whereas in I2C_BUFFER, count size is not sent during the + * transfer and there is no restriction in terms of size. + * + * Distinction between I2C_BLOCK and I2C_BUFFER protocol: + * I2C_BUFFER takes the register address as argument whereas I2C_BLOCK does + * not have any register or command provision. + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW = 3, + /*! + * This transaction type is used to perform the I2C byte read/write from/to + * a slave device + * Refer SMBus spec 2.0 (section 5.5.4 Write Byte and 5.5.5 Read Byte) + * SMBus Byte Write : S Addr|Wr [A] cmd [A] Data [A] P + * SMBus Byte Read : S Addr|Wr [A] cmd [A] Sr Addr|Rd [A] Data A P + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW = 4, + /*! + * This transaction type is used to perform the SMBus byte read/write + * from/to a register of a slave device + * Refer SMBus spec 2.0 (section 5.5.4 Write Word and 5.5.5 Read Word) + * SMBus Word Write : S Addr|Wr [A] cmd [A] DataLow [A] DataHigh [A] P + * SMBus Word Read : S Addr|Wr [A] cmd [A] Sr Addr|Rd [A] DataLow A + * DataHigh A P + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW = 5, + /*! + * This transaction type is used to perform the SMBus Block read/write + * from/to a register of a slave device + * Refer SMBus spec 2.0 (section 5.5.7 Block Write/Read) + * SMBus Block Write : S Addr|Wr [A] cmd [A] ByteCount [A] Data1 [A]... + * DataN-1 [A] DataN[A] P + * SMBus Block Read : S Addr|Wr [A] cmd [A] Sr Addr|Rd [A] ByteCount A + * Data1 A...DataN-1 A DataN A P + * + * Distinction between I2C_BLOCK and SMBUS_BLOCK protocol: + * In I2C Block write it is the slave device (and in I2C Block read it's + * the master device) that determines the number of bytes to transfer by + * asserting the NAK at last bit before stop. This differs from the SMBus + * block mode write/Read command in which the master determines the block + * write transfer size. In I2c Block read/Write there is no limit to maximum + * size of data that could be transferred whereas in SMBus block it is + * restricted to 255 bytes (0xFF). + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW = 6, + /*! + * This transaction type is used to perform the SMBus process call. It sends + * data and waits for the slave to return a value dependent on that data. + * The protocol is simply a SMBus write Word followed by a SMBus Read Word + * without the Read-Word command field and the Write-Word STOP bit. + * Note that there is no STOP condition before the repeated START condition, + * and that a NACK signifies the end of the read transfer. + * + * Refer SMBus spec 2.0 (section 5.5.6 Process Call) + * SMBus Process Call : S Addr|Wr [A] cmd [A] DataLow [A] DataHigh [A] + * Sr Addr|Rd [A] DataLow [A] DataHigh [NA] P + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL = 7, + /*! + * This transaction type is used to perform the SMBus Block Write Block Read + * process call. + * The block write-block read process call is a two-part message. The call + * begins with a slave address and a write condition. After the command code + * the host issues a write byte count (M) that describes how many more bytes + * will be written in the first part of the message. + * If a master has 6 bytes to send, the byte count field will have the value + * 6 (0000 0110b), followed by the 6 bytes of data. The write byte count (M) + * cannot be zero. + * The second part of the message is a block of read data beginning with a + * repeated start condition followed by the slave address and a Read bit. + * The next byte is the read byte count (N), which may differ from the write + * byte count (M). The read byte count (N) cannot be zero. The combined data + * payload must not exceed 32 bytes. + * The byte length restrictions of this process call are summarized as + * follows: + * M >= 1 byte + * N >= 1 byte + * M + N <= 32 bytes + * Note that there is no STOP condition before the repeated START condition, + * and that a NACK signifies the end of the read transfer. + * + * Refer SMBus spec 2.0 (section 5.5.8 Block Write Block Read Process Call) + * SMBus Process Call : S Addr|Wr [A] cmd [A] ByteCount=M [A] Data1 [A]... + * DataN-1 [A] DataM[A] Sr Addr|Rd [A] ByteCount=N [A] + * Data1 [A]...DataN [NA] P + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL = 8, + /*! + * This transaction type is used to perform SMBus buffer read/write + * from/to multiple registers of a slave device known as Auto Increment. + * It is not a part of any standard I2C/SMBus spec but a feature of many + * SMBus devices like EEPROM. + * It is also used for reading a block of bytes from a designated register + * that is specified through the two Comm bytes.of a slave device or writing + * a block of bytes from a designated register of a slave device (Note : The + * command byte in this case could be 0, 2 or 4 Bytes) + * SMBus Multi-Byte Register Block Write : S Addr|Wr [A] cmd1 A cmd 2 [A]... + * cmdN [A] data1 [A] Data2 [A].....DataN [A] P + * SMBus Multi-Byte Register Block Read : S Addr|Rd [A] cmd1 A cmd 2 [A]... + * cmdN [A] data1 [A] Sr Addr [A] Data1 A Data2 A...DataN A P + * + * This transaction type could be also used for those devices which supports + * AUTO_INC. Even though it is frequently related to I2C/SMBus, automatic + * incrementation is not part of any I2C standard but rather a common + * feature found in many I2C devices. What it means is that the device + * maintains in internal pointer which is automatically incremented upon + * data read or write activities and which can be manually set to a fixed + * value. This comes in handy when storing larger amounts of data for + * instance in an ordinary I2C RAM or EEPROM. + * SMBus AUTO_INC Write : S Addr|Wr [A] cmd1 A Data1 [A] Data2 [A]... + * DataN [A] P + * SMBus AUTO_INC Read : S Addr|Rd [A] cmd1 A data1 [A] Sr Addr [A] Data1 A + * Data2 A...DataN A P + * If the device does not support AUTO_INC set warFlags of + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW to + * NV402C_CTRL_I2C_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW_WAR_FLAGS_NO_AUTO_INC. + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW = 9, + /*! + * This transaction type is used to perform the EDID read via DDC. + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC = 10, +} NV402C_CTRL_I2C_TRANSACTION_TYPE; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW. + * + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW { + /*! + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + */ + NvBool bWrite; + /*! + * Transaction specific flags + * (see NV402C_CTRL_I2C_SMBUS_QUICK_RW_WAR_FLAGS_*). + */ + NvU32 warFlags; +} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW. + * + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW { + /*! + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + */ + NvBool bWrite; + /*! + * The main message data. + */ + NvU8 message; +} NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW + * + * Specifies the structure of data filled by the client for I2C transaction + * when the transaction type is NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW. + * + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW { + /*! + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + */ + NvBool bWrite; + /*! + * This parameter specifies the number of bytes to read or + * write from the slave after the register address is written. + */ + NvU32 messageLength; + /*! + * The main message data. + */ + NV_DECLARE_ALIGNED(NvP64 pMessage, 8); +} NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW. + * + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW { + /*! + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + */ + NvBool bWrite; + /*! + * The address of the register. + */ + NvU8 registerAddress; + /*! + * The main message data. + */ + NvU8 message; +} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW. + * + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW { + /*! + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + */ + NvBool bWrite; + /*! + * The address of the register. + */ + NvU8 registerAddress; + /*! + * The main message data. + */ + NvU16 message; +} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BUFFER_RW + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BUFFER_RW. + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW { + /*! + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + */ + NvBool bWrite; + /*! + * Transaction specific flags to be set (see + * NV_NV402C_CTRL_I2C_BUFFER_RW_WAR_FLAGS_*) + */ + NvU32 warFlags; + /*! + * This parameter specifies how many bytes to write as part of the + * register address. If zero is specified, then no index will be sent. + */ + NvU8 registerAddress; + /*! + * This parameter specifies the number of bytes to read or + * write from the slave after the register address is written. + */ + NvU32 messageLength; + /*! + * The main message data. + * C form: NvU8 message[NV402C_CTRL_I2C_MESSAGE_LENGTH_MAX] + */ + NV_DECLARE_ALIGNED(NvP64 pMessage, 8); +} NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW. + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW { + /*! + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + */ + NvBool bWrite; + /*! + * This parameter specifies how many bytes to write as part of the + * register address. If zero is specified, then no index will be sent. + */ + NvU8 registerAddress; + /*! + * This parameter specifies the number of bytes to read or + * write from the slave after the register address is written. + */ + NvU32 messageLength; + /*! + * The main message data. + * C form: NvU8 message[NV402C_CTRL_I2C_MESSAGE_LENGTH_MAX] + */ + NV_DECLARE_ALIGNED(NvP64 pMessage, 8); +} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL. + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL { + /*! + * This parameter specifies how many bytes to write as part of the + * register address. If zero is specified, then no index will be sent. + */ + NvU8 registerAddress; + /*! + * The message data to be written to the slave. + */ + NvU16 writeMessage; + /*! + * The message data to be read from the slave. + */ + NvU16 readMessage; +} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL. + * + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL { + /*! + * This parameter specifies how many bytes to write as part of the + * register address. If zero is specified, then no index will be sent. + */ + NvU8 registerAddress; + /*! + * This parameter specifies the number of bytes to write the the slave + * after the writeByteCount is sent to the slave. + */ + NvU32 writeMessageLength; + /*! + * The message buffer to be written to the slave. + * C form: NvU8 writeMessage[NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX] + */ + NvU8 writeMessage[NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX]; + /*! + * This parameter specifies the number of bytes to read from the slave + * after the readByteCount is sent to the slave. + */ + NvU32 readMessageLength; + /*! + * The message buffer to be read from the slave. + * C form: NvU8 readMessage[NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX] + */ + NvU8 readMessage[NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX]; +} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW. + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW { + /*! + * This field must be specified by the client to indicate whether the + * command is a write (TRUE) or a read (FALSE). + */ + NvBool bWrite; + /*! + * Transaction specific flags (see + * NV402C_CTRL_I2C_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW_WAR_FLAGS_*) + */ + NvU32 warFlags; + /*! + * This parameter specifies how many bytes to write as part of the + * register address. If zero is specified, then no index will be sent. + */ + NvU32 indexLength; + /*! + * Optional indexing data; aka register address. + * C form: NvU8 index[NV402C_CTRL_I2C_INDEX_LENGTH_MAX] + */ + NvU8 index[NV402C_CTRL_I2C_INDEX_LENGTH_MAX]; + /*! + * This parameter specifies the number of bytes to read or + * write from the slave after the register address is written. + */ + NvU32 messageLength; + /*! + * The main message data. + * C form: NvU8 message[NV402C_CTRL_I2C_MESSAGE_LENGTH_MAX] + */ + NV_DECLARE_ALIGNED(NvP64 pMessage, 8); +} NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC + * + * Specifies the structure of data filled by the client for I2C transaction + * when the.transaction type is NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC. + * + */ +typedef struct NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC { + /*! + * The segment number of the EDID block which is to be read. + */ + NvU8 segmentNumber; + /*! + * The address of the register. + */ + NvU8 registerAddress; + /*! + * This parameter specifies the number of bytes to read or + * write from the slave after the register address is written. + */ + NvU32 messageLength; + /*! + * The main message data. + * C form: NvU8 message[NV402C_CTRL_I2C_MESSAGE_LENGTH_MAX] + */ + NV_DECLARE_ALIGNED(NvP64 pMessage, 8); +} NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC; + +/*! + * NV402C_CTRL_I2C_TRANSACTION_DATA + * + * This union encapsulates the transaction data corresponding to the + * transaction type enlisted above. + */ +typedef union NV402C_CTRL_I2C_TRANSACTION_DATA { + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW. + */ + NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW smbusQuickData; + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW. + */ + NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW i2cByteData; + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW. + */ + NV_DECLARE_ALIGNED(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW i2cBlockData, 8); + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW. + */ + NV_DECLARE_ALIGNED(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW i2cBufferData, 8); + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW. + */ + NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW smbusByteData; + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW. + */ + NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW smbusWordData; + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW. + */ + NV_DECLARE_ALIGNED(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW smbusBlockData, 8); + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL. + */ + NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL smbusProcessData; + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL. + */ + NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL smbusBlockProcessData; + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW. + */ + NV_DECLARE_ALIGNED(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW smbusMultibyteRegisterData, 8); + /*! + * This transaction data is to be filled when transaction type is + * NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC. + */ + NV_DECLARE_ALIGNED(NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC edidData, 8); +} NV402C_CTRL_I2C_TRANSACTION_DATA; + + +/*! + * NV402C_CTRL_I2C_TRANSACTION_PARAMS + * + * The params data structure for NV402C_CTRL_CMD_I2C_TRANSACTION. + */ +#define NV402C_CTRL_I2C_TRANSACTION_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV402C_CTRL_I2C_TRANSACTION_PARAMS { + /*! + * The logical port ID. + */ + NvU8 portId; + /*! + * This parameter specifies optional flags used to control certain modal + * features such as target speed and addressing mode. The currently + * defined fields are described previously; see NV402C_CTRL_I2C_FLAGS_* + */ + NvU32 flags; + /*! + * The address of the I2C slave. + */ + NvU16 deviceAddress; + /*! + * The transaction type. + */ + NV402C_CTRL_I2C_TRANSACTION_TYPE transType; + /*! + * The transaction data corresponding transaction type. + */ + NV_DECLARE_ALIGNED(NV402C_CTRL_I2C_TRANSACTION_DATA transData, 8); +} NV402C_CTRL_I2C_TRANSACTION_PARAMS; + +#define NV402C_CTRL_CMD_I2C_TRANSACTION (0x402c0105) /* finn: Evaluated from "(FINN_NV40_I2C_I2C_INTERFACE_ID << 8) | NV402C_CTRL_I2C_TRANSACTION_PARAMS_MESSAGE_ID" */ + + +/* _ctrl402c_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl503c.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl503c.h new file mode 100644 index 0000000..e3a9532 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl503c.h @@ -0,0 +1,200 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl503c.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl503c/ctrl503cbase.h" + +/* + * NV503C_CTRL_CMD_REGISTER_VA_SPACE + * + * This command registers the specified GPU VA space with the given + * NV50_THIRD_PARTY_P2P object, and returns a token that + * uniquely identifies the VA space within the object's parent + * client. + * + * Its parameter structure has the following fields: + * + * hVASpace + * This field specifies the GPU VA space to be registered + * with the third-party P2P object. + * + * vaSpaceToken + * Upon successful completion of the regristration attempt, + * this field holds the new VA space identifier. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INVALID_OBJECT_HANDLE + * NVOS_STATUS_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_RESOURCES + */ +#define NV503C_CTRL_CMD_REGISTER_VA_SPACE (0x503c0102) /* finn: Evaluated from "(FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID << 8) | NV503C_CTRL_REGISTER_VA_SPACE_PARAMS_MESSAGE_ID" */ + +#define NV503C_CTRL_REGISTER_VA_SPACE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV503C_CTRL_REGISTER_VA_SPACE_PARAMS { + NvHandle hVASpace; + NV_DECLARE_ALIGNED(NvU64 vaSpaceToken, 8); +} NV503C_CTRL_REGISTER_VA_SPACE_PARAMS; + + +/* + * NV503C_CTRL_CMD_UNREGISTER_VA_SPACE + * + * This command unregisters (a previously registered) GPU VA space. + * + * Its parameter structure has the following field: + * + * hVASpace + * This field specifies the GPU VA space to be + * unregistered. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV503C_CTRL_CMD_UNREGISTER_VA_SPACE (0x503c0103) /* finn: Evaluated from "(FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID << 8) | NV503C_CTRL_UNREGISTER_VA_SPACE_PARAMS_MESSAGE_ID" */ + +#define NV503C_CTRL_UNREGISTER_VA_SPACE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV503C_CTRL_UNREGISTER_VA_SPACE_PARAMS { + NvHandle hVASpace; +} NV503C_CTRL_UNREGISTER_VA_SPACE_PARAMS; + + +/* + * NV503C_CTRL_CMD_REGISTER_VIDMEM + * + * This command registers a video memory allocation with the given + * NV50_THIRD_PARTY_P2P object. Registration of video memory + * allocations is required if they are to be made accessible via the + * third-party P2P infrastructure. + * + * The vidmem allocation is made available to the users of the third-party P2P + * APIs. It's exposed at the range specified by address and size starting at the + * specified offset within the physical allocation. The same physical memory is + * exposed as the NvRmMapMemoryDma() API would make accessible to the GPU if + * used with equivalent parameters. Notably this API doesn't create any virtual + * mappings nor verifies that any mappings are present, it only registers the + * memory for the purpose of the third-party P2P infrastructure. + * + * The address range specified by address and size cannot overlap any previously + * registered ranges for the given NV50_THIRD_PARTY_P2P object. + * + * Its parameter structure has the following field: + * + * hMemory + * This field specifies the video memory allocation to be + * registered with the third-party P2P object. + * + * address + * The address to register the video memory allocation at. Has to be + * aligned to 64K. + * + * size + * Size in bytes, has to be non-0 and aligned to 64K. Offset + size cannot + * be larger than the vidmem allocation. + * + * offset + * Offset within the video memory allocation where the registered address + * range starts. Has to be aligned to 64K. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_RESOURCES + */ +#define NV503C_CTRL_CMD_REGISTER_VIDMEM (0x503c0104) /* finn: Evaluated from "(FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID << 8) | NV503C_CTRL_REGISTER_VIDMEM_PARAMS_MESSAGE_ID" */ + +#define NV503C_CTRL_REGISTER_VIDMEM_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV503C_CTRL_REGISTER_VIDMEM_PARAMS { + NvHandle hMemory; + NV_DECLARE_ALIGNED(NvU64 address, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NV_DECLARE_ALIGNED(NvU64 offset, 8); +} NV503C_CTRL_REGISTER_VIDMEM_PARAMS; + + +/* + * NV503C_CTRL_CMD_UNREGISTER_VIDMEM + * + * This command unregisters (a previously registered) video memory + * allocation. + * + * Its parameter structure has the following field: + * + * hMemory + * This field specifies the video memory allocation to be + * unregistered. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV503C_CTRL_CMD_UNREGISTER_VIDMEM (0x503c0105) /* finn: Evaluated from "(FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID << 8) | NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS_MESSAGE_ID" */ + +#define NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS { + NvHandle hMemory; +} NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS; + +/* + * NV503C_CTRL_CMD_REGISTER_PID + * + * This command registers the PID of the process that allocated + * the RM client identified by the hClient argument with the + * third-party P2P object, granting this process access to any + * underlying video memory. + * + * Its parameter structure has the following field: + * + * hClient + * This field specifies the client id and should be the handle + * to a valid NV01_ROOT_USER instance. + * + * Possible status values returned are: + * NVOS_STATUS_SUCCES + * NV_ERR_INVALID_ARGUMENT + */ +#define NV503C_CTRL_CMD_REGISTER_PID (0x503c0106) /* finn: Evaluated from "(FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID << 8) | NV503C_CTRL_REGISTER_PID_PARAMS_MESSAGE_ID" */ + +#define NV503C_CTRL_REGISTER_PID_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV503C_CTRL_REGISTER_PID_PARAMS { + NvHandle hClient; +} NV503C_CTRL_REGISTER_PID_PARAMS; + +/* _ctrl503c_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl503c/ctrl503cbase.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl503c/ctrl503cbase.h new file mode 100644 index 0000000..22f3fbe --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl503c/ctrl503cbase.h @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl503c/ctrl503cbase.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV50_THIRD_PARTY_P2P control commands and parameters */ +#define NV503C_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x503C,NV503C_CTRL_##cat,idx) + +/* NV50_THIRD_PARTY_P2P command categories (6bits) */ +#define NV503C_CTRL_RESERVED (0x00) +#define NV503C_CTRL_P2P (0x01) + +/* + * NV503C_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV503C_CTRL_CMD_NULL (0x503c0000) /* finn: Evaluated from "(FINN_NV50_THIRD_PARTY_P2P_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrl503cbase_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl506f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl506f.h new file mode 100644 index 0000000..7fd7c36 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl506f.h @@ -0,0 +1,96 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl506f.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV50_GPFIFO control commands and parameters */ + +#define NV506F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0x506F, NV506F_CTRL_##cat, idx) + +/* NV50_GPFIFO command categories (6bits) */ +#define NV506F_CTRL_RESERVED (0x00) +#define NV506F_CTRL_GPFIFO (0x01) +#define NV506F_CTRL_EVENT (0x02) + +/* + * NV506F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV506F_CTRL_CMD_NULL (0x506f0000) /* finn: Evaluated from "(FINN_NV50_CHANNEL_GPFIFO_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* + * NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL + * + * This command resets a channel which was isolated previously by RC recovery. + * + * exceptType + * This input parameter specifies the type of RC error that occurred. See the + * description of the ROBUST_CHANNEL_* values in nverror.h for valid exceptType + * values. info32 field of the error notifier is set with the exceptType when + * the error notifier is signaled. + * + * engineID + * This input parameter specifies the engine to be reset. See the description + * of the NV2080_ENGINE_TYPE values in cl2080.h for valid engineID values. info16 + * field of the error notifier is set with the engineID when the error notifier is + * signaled. + * + * Possible status return values are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + + +#define NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL (0x506f0105) /* finn: Evaluated from "(FINN_NV50_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_MESSAGE_ID" */ + +/* + * NV506F_CTRL_CMD_EVENT_SET_TRIGGER (deprecated on Fermi+) + * + * This command triggers a software event for the associated channel. + * This command accepts no parameters. + * + * Possible status values returned are: + * NV_OK + */ +// #define NV506F_CTRL_CMD_EVENT_SET_TRIGGER NV506F_CTRL_CMD(EVENT, 0x09) + +#define NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS { + NvU32 exceptType; + NvU32 engineID; +} NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS;/* _ctrl506f.h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070base.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070base.h new file mode 100644 index 0000000..49297f7 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070base.h @@ -0,0 +1,67 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070base.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV5070_DISPLAY control commands and parameters */ + +#define NV5070_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x5070, NV5070_CTRL_##cat, idx) + +/* Display command categories (6bits) */ +#define NV5070_CTRL_RESERVED (0x00) +#define NV5070_CTRL_CHNCTL (0x01) +#define NV5070_CTRL_RG (0x02) +#define NV5070_CTRL_SEQ (0x03) +#define NV5070_CTRL_OR (0x04) +#define NV5070_CTRL_INST (0x05) +#define NV5070_CTRL_VERIF (0x06) +#define NV5070_CTRL_SYSTEM (0x07) +#define NV5070_CTRL_EVENT (0x09) + +/* + * NV5070_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV5070_CTRL_CMD_NULL (0x50700000) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + +// This struct must be the first member of all +// 5070 control calls +typedef struct NV5070_CTRL_CMD_BASE_PARAMS { + NvU32 subdeviceIndex; +} NV5070_CTRL_CMD_BASE_PARAMS; + +/* _ctrl5070base_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070chnc.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070chnc.h new file mode 100644 index 0000000..1916d7f --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070chnc.h @@ -0,0 +1,1181 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070chnc.finn +// + +#include "ctrl/ctrl5070/ctrl5070base.h" +#include "ctrl5070common.h" +#include "nvdisptypes.h" + +#define NV5070_CTRL_CMD_NUM_DISPLAY_ID_DWORDS_PER_HEAD 2 + + + +#define NV5070_CTRL_IDLE_CHANNEL_ACCL_NONE (0x00000000) +#define NV5070_CTRL_IDLE_CHANNEL_ACCL_IGNORE_PI (NVBIT(0)) +#define NV5070_CTRL_IDLE_CHANNEL_ACCL_SKIP_NOTIF (NVBIT(1)) +#define NV5070_CTRL_IDLE_CHANNEL_ACCL_SKIP_SEMA (NVBIT(2)) +#define NV5070_CTRL_IDLE_CHANNEL_ACCL_IGNORE_INTERLOCK (NVBIT(3)) +#define NV5070_CTRL_IDLE_CHANNEL_ACCL_IGNORE_FLIPLOCK (NVBIT(4)) +#define NV5070_CTRL_IDLE_CHANNEL_ACCL_TRASH_ONLY (NVBIT(5)) +#define NV5070_CTRL_IDLE_CHANNEL_ACCL_TRASH_AND_ABORT (NVBIT(6)) + +#define NV5070_CTRL_IDLE_CHANNEL_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV5070_CTRL_IDLE_CHANNEL_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 channelClass; + NvU32 channelInstance; + + NvU32 desiredChannelStateMask; + NvU32 accelerators; // For future expansion. Not yet implemented + NvU32 timeout; // For future expansion. Not yet implemented + NvBool restoreDebugMode; +} NV5070_CTRL_IDLE_CHANNEL_PARAMS; + +/* + * NV5070_CTRL_CMD_STOP_OVERLAY + * + * This command tries to turn the overlay off ASAP. + * + * channelInstance + * This field indicates which of the two instances of the overlay + * channel the cmd is meant for. + * + * notifyMode + * This field indicates the action RM should take once the overlay has + * been successfully stopped. The options are (1) Set a notifier + * (2) Set the notifier and generate and OS event + * + * hNotifierCtxDma + * Handle to the ctx dma for the notifier that must be written once + * overlay is stopped. The standard NvNotification notifier structure + * is used. + * + * offset + * Offset within the notifier context dma where the notifier begins + * Offset must be 16 byte aligned. + * + * hEvent + * Handle to the event that RM must use to awaken the client when + * notifyMode is WRITE_AWAKEN. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT: Invalid notify mode + * NV_ERR_INVALID_CHANNEL: When the overlay is unallocated + * NV_ERR_INVALID_OWNER: Callee isn't the owner of the channel + * NV_ERR_INVALID_OBJECT_HANDLE: Notif ctx dma not found + * NV_ERR_INVALID_OFFSET: Bad offset within notif ctx dma + * NV_ERR_INSUFFICIENT_RESOURCES + * NV_ERR_TIMEOUT: RM timedout waiting to inject methods + */ +#define NV5070_CTRL_CMD_STOP_OVERLAY (0x50700102) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_CMD_STOP_OVERLAY_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_STOP_OVERLAY_NOTIFY_MODE_WRITE (0x00000000) +#define NV5070_CTRL_CMD_STOP_OVERLAY_NOTIFY_MODE_WRITE_AWAKEN (0x00000001) + +#define NV5070_CTRL_CMD_STOP_OVERLAY_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV5070_CTRL_CMD_STOP_OVERLAY_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 channelInstance; + NvU32 notifyMode; + NvHandle hNotifierCtxDma; + NvU32 offset; + NV_DECLARE_ALIGNED(NvP64 hEvent, 8); +} NV5070_CTRL_CMD_STOP_OVERLAY_PARAMS; + + + +/* + * NV5070_CTRL_CMD_IS_MODE_POSSIBLE + * + * This command is used by DD to determine whether or not a given mode + * is possible given the current nvclk, mclk, dispclk and potentially some + * other parameters that are normally hidden from it. All the parameters + * except IsPossible (output), Force422(output), MinPstate (input/output), + * minPerfLevel (output), CriticalWatermark (output), worstCaseMargin (output), + * and worstCaseDomain (output) params are supplied by the caller. + * + * HeadActive + * Whether or not the params for this head are relevant. + * + * PixelClock + * Frequency: Pixel clk frequency in KHz. + * Adj1000Div1001: 1000/1001 multiplier for pixel clock. + * + * RasterSize + * Width: Total width of the raster. Also referred to as HTotal. + * Height: Total height of the raster. Also referred to as VTotal. + * + * RasterBlankStart + * X: Start of horizontal blanking for the raster. + * Y: Start of vertical blanking for the raster. + * + * RasterBlankEnd + * X: End of horizontal blanking for the raster. + * Y: End of vertical blanking for the raster. + * + * RasterVertBlank2 + * YStart: Start of second blanking for second field for an + * interlaced raster. This field is irrelevant when raster is + * progressive. + * YEnd: End of second blanking for second field for an + * interlaced raster. This field is irrelevant when raster is + * progressive. + * + * Control + * RasterStructure: Whether the raster ir progressive or interlaced. + * + * OutputScaler + * VerticalTaps: Vertical scaler taps. + * HorizontalTaps: Horizontal scaler taps. + * Force422: Whether OutputScaler is operating in 422 mode or not. + * + * ViewportSizeOut + * Width: Width of output viewport. + * Height: Height of output viewport. + * Both the above fields are irrelevant for G80. + * + * ViewportSizeOutMin + * Width: Minimum possible/expected width of output viewport. + * Height: Minimum possible/expected height of output viewport. + * + * ViewportSizeIn + * Width: Width of input viewport. + * Height: Height of input viewport. + * + * Params + * Format: Core channel's pixel format. See the enumerants following + * the variable declaration for possible options. + * SuperSample: Whether to use X1AA or X4AA in core channel. + * This parameter is ignored for G80. + * + * BaseUsageBounds + * Usable: Whether or not the base channel is expected to be used. + * PixelDepth: Maximum pixel depth allowed in base channel. + * SuperSample: Whether or not X4AA is allowed in base channel. + * BaseLutUsage: Base LUT Size + * OutputLutUsage: Output LUT size + * + * OverlayUsageBounds + * Usable: Whether or not the overlay channel is expected to be used. + * PixelDepth: Maximum pixel depth allowed in overlay channel. + * OverlayLutUsage: Overlay LUT Size + * + * BaseLutLo + * Enable: Specifies Core Channel's Base LUT is enable or not. + * Mode: Specifies the LUT Mode. + * NeverYieldToBase: Specifies whether NEVER_YIELD_TO_BASE is enabled or not. + * + * OutputLutLo + * Enable: Specifies Core Channel's Output LUT is enable or not. + * Mode: Specifies the LUT Mode. + * NeverYieldToBase: Specifies whether NEVER_YIELD_TO_BASE is enabled or not. + * + * outputResourcePixelDepthBPP + * Specifies the output pixel depth with scaler mode. + * + * CriticalWatermark + * If MinPState is set to _NEED_MIN_PSTATE, this will return the critical + * watermark level at the minimum Pstate. Otherwise, this will return + * the critical watermark at the level that the IMP calculations are + * otherwise performed at. + * + * pixelReplicateMode + * Specifies the replication mode whether it is X2 or X4. Need to set the parameter + * to OFF if there is no pixel replication. + * + * numSSTLinks + * Number of Single Stream Transport links which will be used by the + * SOR. "0" means to use the number indicated by the most recent + * NV0073_CTRL_CMD_DP_SINGLE_HEAD_MULTI_STREAM_MODE_SST call. + * + * RequestedOperation + * This parameter is used to determine whether + * 1. DD is simplying querying whether or not the specified mode is + * possible (REQUESTED_OPER = _QUERY) or + * 2. DD is about to set the specified mode and RM should make + * appropriate preparations to make the mode possible. DD should + * never pass in a mode that was never indicated by RM as possible + * when DD queried for the possibility of the mode. This + * corresponds to REQUESTED_OPER = _PRE_MODESET. + * 3. DD just finished setting the specified mode. RM can go ahead + * and make changes like lowering the perf level if desired. This + * corresponds to REQUESTED_OPER = _POST_MODESET. This parameter is + * useful when we are at a higher perf level in a mode that's not + * possible at a lower perf level and want to go to a mode that is + * possible even at a lower perf level. In such cases, lowering + * perf level before modeset is complete is dangerous as it will + * cause underflow. RM will wait until the end of modeset to lower + * the perf level. + * + * options + * Specifies a bitmask for options. + * NV5070_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN + * Tells IMP to calculate worstCaseMargin and worstCaseDomain. + * + * IsPossible + * This is the first OUT param for this call. It indicates whether + * or not the current mode is possible. + * + * MinPState + * MinPState is an IO (in/out) variable; it gives the minimum p-state + * value at which the mode is possible on a PStates 2.0 system if the + * parameter is initialized by the caller with _NEED_MIN_PSTATE. If + * _NEED_MIN_PSTATE is not specified, IMP query will just run at the + * max available perf level and return results for that pstate. + * + * If the minimum pstate is required, then MasterLockMode, + * MasterLockPin, SlaveLockMode, and SlaveLockPin must all be + * initialized. + * + * On a PStates 3.0 system, the return value for MinPState is + * undefined, but minPerfLevel can return the minimum IMP v-pstate. + * + * minPerfLevel + * On a PStates 3.0 system, minPerfLevel returns the minimum IMP + * v-pstate at which the mode is possible. On a PStates 2.0 system, + * minPerfLevel returns the minimum perf level at which the mode is + * possible. + * + * minPerfLevel is valid only if MinPState is initialized to + * _NEED_MIN_PSTATE. + * + * worstCaseMargin + * Returns the ratio of available bandwidth to required bandwidth, + * multiplied by NV5070_CTRL_IMP_MARGIN_MULTIPLIER. Available + * bandwidth is calculated in the worst case bandwidth domain, i.e., + * the domain with the least available margin. Bandwidth domains + * include the IMP-relevant clock domains, and possibly other virtual + * bandwidth domains such as AWP. + * + * Note that IMP checks additional parameters besides the bandwidth + * margins, but only the bandwidth margin is reported here, so it is + * possible for a mode to have a more restrictive domain that is not + * reflected in the reported margin result. + * + * This result is not guaranteed to be valid if the mode is not + * possible. + * + * Note also that the result is generally calculated for the highest + * pstate possible (usually P0). But if _NEED_MIN_PSTATE is specified + * with the MinPState parameter, the result will be calculated for the + * min possible pstate (or the highest possible pstate, if the mode is + * not possible). + * + * The result is valid only if + * NV5070_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN is set in + * "options". + * + * worstCaseDomain + * Returns a short text string naming the domain for the margin + * returned in "worstCaseMargin". See "worstCaseMargin" for more + * information. + * + * bUseCachedPerfState + * Indicates that RM should use cached values for the fastest + * available perf level (v-pstate for PStates 3.0 or pstate for + * PStates 2.0) and dispclk. This feature allows the query call to + * execute faster, and is intended to be used, for example, during + * mode enumeration, when many IMP query calls are made in close + * succession, and perf conditions are not expected to change between + * query calls. When IMP has not been queried recently, it is + * recommended to NOT use cached values, in case perf conditions have + * changed and the cached values no longer reflect the current + * conditions. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * + * Assumptions/Limitations: + * - If the caller sends any methods to alter the State Cache, before calling of + * the following functions: + * NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_QUERY_USE_SC + * NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_PRE_MODESET_USE_SC + * NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_POST_MODESET_USE_SC + * the caller must repeatedly issue NV5070_CTRL_CMD_GET_CHANNEL_INFO, and delay until the + * returned channelState is either: + * NV5070_CTRL_CMD_GET_CHANNEL_INFO_STATE_IDLE, + * NV5070_CTRL_CMD_GET_CHANNEL_INFO_STATE_WRTIDLE, or + * NV5070_CTRL_CMD_GET_CHANNEL_INFO_STATE_EMPTY. + * This ensures that all commands have reached the State Cache before RM reads + * them. + * + * + */ +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE (0x50700109) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_QUERY (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_PRE_MODESET (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_POST_MODESET (0x00000002) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_QUERY_USE_SC (0x00000003) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_PRE_MODESET_USE_SC (0x00000004) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_POST_MODESET_USE_SC (0x00000005) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_REQUESTED_OPERATION_SUPERVISOR (0x00000007) + +#define NV5070_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN (0x00000001) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_IS_POSSIBLE_NO (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_IS_POSSIBLE_YES (0x00000001) + +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_UNDEFINED (0x00000000) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P0 (0x00000001) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P1 (0x00000002) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P2 (0x00000004) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P3 (0x00000008) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P8 (0x00000100) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P10 (0x00000400) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P12 (0x00001000) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P15 (0x00008000) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_MAX NV5070_CTRL_IS_MODE_POSSIBLE_PSTATES_P15 +#define NV5070_CTRL_IS_MODE_POSSIBLE_NEED_MIN_PSTATE (0x10101010) +#define NV5070_CTRL_IS_MODE_POSSIBLE_NEED_MIN_PSTATE_DEFAULT (0x00000000) + +#define NV5070_CTRL_IMP_MARGIN_MULTIPLIER (0x00000400) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_HEAD_ACTIVE_NO (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_HEAD_ACTIVE_YES (0x00000001) + +#define NV5070_CTRL_IS_MODE_POSSIBLE_DISPLAY_ID_SKIP_IMP_OUTPUT_CHECK (0xAAAAAAAA) + +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000009) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PIXEL_CLOCK_ADJ1000DIV1001_NO (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PIXEL_CLOCK_ADJ1000DIV1001_YES (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_CONTROL_STRUCTURE_INTERLACED (0x00000001) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_VERTICAL_TAPS_1 (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_VERTICAL_TAPS_2 (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_VERTICAL_TAPS_3 (0x00000002) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_VERTICAL_TAPS_3_ADAPTIVE (0x00000003) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_VERTICAL_TAPS_5 (0x00000004) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_HORIZONTAL_TAPS_1 (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_HORIZONTAL_TAPS_2 (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_SCALER_HORIZONTAL_TAPS_8 (0x00000002) + +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_SCALER_FORCE422_MODE_DISABLE (0x00000000) +#define NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_SCALER_FORCE422_MODE_ENABLE (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_I8 (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_VOID16 (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_VOID32 (0x00000002) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x00000003) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_A8R8G8B8 (0x00000004) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_A2B10G10R10 (0x00000005) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_A8B8G8R8 (0x00000006) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_R5G6B5 (0x00000007) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_FORMAT_A1R5G5B5 (0x00000008) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_SUPER_SAMPLE_X1AA (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_SUPER_SAMPLE_X4AA (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_USABLE_USE_CURRENT (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_USABLE_NO (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_USABLE_YES (0x00000002) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_PIXEL_DEPTH_USE_CURRENT (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_PIXEL_DEPTH_8 (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_PIXEL_DEPTH_16 (0x00000002) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_PIXEL_DEPTH_32 (0x00000003) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_PIXEL_DEPTH_64 (0x00000004) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_SUPER_SAMPLE_USE_CURRENT (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_SUPER_SAMPLE_X1AA (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_SUPER_SAMPLE_X4AA (0x00000002) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_BASE_LUT_USAGE_NONE (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_BASE_LUT_USAGE_257 (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_BASE_LUT_USAGE_1025 (0x00000002) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_USABLE_USE_CURRENT (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_USABLE_NO (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_USABLE_YES (0x00000002) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_USE_CURRENT (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_16 (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_32 (0x00000002) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_64 (0x00000003) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257 (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025 (0x00000002) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000002) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000003) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000004) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000005) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000006) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000007) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000002) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000003) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000004) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000005) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000006) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000007) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NV5070_CTRL_IS_MODE_POSSIBLE_PIXEL_REPLICATE_MODE_X4 (0x00000002) + +#define NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + struct { + NvU32 HeadActive; + struct { + NvU32 Frequency; + + NvU32 Adj1000Div1001; + } PixelClock; + + struct { + NvU32 Width; + NvU32 Height; + } RasterSize; + + struct { + NvU32 X; + NvU32 Y; + } RasterBlankStart; + + struct { + NvU32 X; + NvU32 Y; + } RasterBlankEnd; + + struct { + NvU32 YStart; + NvU32 YEnd; + } RasterVertBlank2; + + struct { + NvU32 Structure; +/* + * Note: For query calls, the lock modes and lock pins are used only if the min + * pstate is required (i.e., if MinPState is set to + * NV5070_CTRL_IS_MODE_POSSIBLE_NEED_MIN_PSTATE). + */ + NV_DISP_LOCK_MODE MasterLockMode; + NV_DISP_LOCK_PIN MasterLockPin; + NV_DISP_LOCK_MODE SlaveLockMode; + NV_DISP_LOCK_PIN SlaveLockPin; + } Control; + + struct { + NvU32 VerticalTaps; + NvU32 HorizontalTaps; + NvBool Force422; + } OutputScaler; + + struct { + NvU32 Width; + NvU32 Height; + } ViewportSizeOut; + + struct { + NvU32 Width; + NvU32 Height; + } ViewportSizeOutMin; + + struct { + NvU32 Width; + NvU32 Height; + } ViewportSizeOutMax; + + struct { + NvU32 Width; + NvU32 Height; + } ViewportSizeIn; + + struct { + NvU32 Format; + NvU32 SuperSample; + } Params; + + struct { + NvU32 Usable; + NvU32 PixelDepth; + NvU32 SuperSample; + NvU32 BaseLutUsage; + NvU32 OutputLutUsage; + } BaseUsageBounds; + + struct { + NvU32 Usable; + NvU32 PixelDepth; + NvU32 OverlayLutUsage; + } OverlayUsageBounds; + + struct { + NvBool Enable; + NvU32 Mode; + NvBool NeverYieldToBase; + } BaseLutLo; + + struct { + NvBool Enable; + NvU32 Mode; + NvBool NeverYieldToBase; + } OutputLutLo; + + NvU32 displayId[NV5070_CTRL_CMD_NUM_DISPLAY_ID_DWORDS_PER_HEAD]; + NvU32 outputResourcePixelDepthBPP; + + NvU32 CriticalWatermark; // in pixels + + } Head[NV5070_CTRL_CMD_MAX_HEADS]; + + struct { + NvU32 owner; + NvU32 protocol; + } Dac[NV5070_CTRL_CMD_MAX_DACS]; + + struct { +// +// owner field is deprecated. In the future, all client calls should set +// ownerMask and bUseSorOwnerMask. bUseSorOwnerMask must be set in order +// to use ownerMask. +// + NvU32 owner; + NvU32 ownerMask; // Head mask owned this sor + + NvU32 protocol; + NvU32 pixelReplicateMode; + + NvU8 numSSTLinks; + } Sor[NV5070_CTRL_CMD_MAX_SORS]; + + NvBool bUseSorOwnerMask; + + struct { + NvU32 owner; + NvU32 protocol; + } Pior[NV5070_CTRL_CMD_MAX_PIORS]; + + + NvU32 RequestedOperation; +// This argument is for VERIF and INTERNAL use only + NvU32 options; + NvU32 IsPossible; + NvU32 MinPState; + + NvU32 minPerfLevel; +// +// Below are the possible Output values for MinPState variable. +// Lower the p-state value higher the power consumption; if no p-states are defined on chip +// then it will return as zero. +// + +// +// Below are the possible input values for MinPstate Variable, by default it calculate +// mode is possible or not at max available p-state and return the same state in that variable. +// + NvU32 worstCaseMargin; + +// +// The calculated margin is multiplied by a constant, so that it can be +// represented as an integer with reasonable precision. "0x400" was chosen +// because it is a power of two, which might allow some compilers/CPUs to +// simplify the calculation by doing a shift instead of a multiply/divide. +// (And 0x400 is 1024, which is close to 1000, so that may simplify visual +// interpretation of the raw margin value.) +// + char worstCaseDomain[8]; + + NvBool bUseCachedPerfState; +} NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS; + + + +/* + * NV5070_CTRL_CMD_GET_CHANNEL_INFO + * + * This command returns the current channel state. + * + * channelClass + * This field indicates the hw class number (507A-507E) + * + * channelInstance + * This field indicates which of the two instances of the channel + * (in case there are two. ex: base, overlay etc) the cmd is meant for. + * Note that core channel has only one instance and the field should + * be set to 0 for core channel. + * + * channelState + * This field indicates the desired channel state in a mask form that + * is compatible with NV5070_CTRL_CMD_IDLE_CHANNEL. A mask format + * allows clients to check for one from a group of states. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + * + * Display driver uses this call to ensure that all it's methods have + * propagated through hardware's internal fifo + * (NV5070_CTRL_GET_CHANNEL_INFO_STATE_NO_METHOD_PENDING) before it calls + * RM to check whether or not the mode it set up in Assembly State Cache will + * be possible. Note that display driver can not use completion notifier in + * this case because completion notifier is associated with Update and Update + * will propagate the state from Assembly to Armed and when checking the + * possibility of a mode, display driver wouldn't want Armed state to be + * affected. + */ +#define NV5070_CTRL_CMD_GET_CHANNEL_INFO (0x5070010b) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_CHANNEL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_IDLE NV5070_CTRL_CMD_CHANNEL_STATE_IDLE +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_WRTIDLE NV5070_CTRL_CMD_CHANNEL_STATE_WRTIDLE +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_EMPTY NV5070_CTRL_CMD_CHANNEL_STATE_EMPTY +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_FLUSHED NV5070_CTRL_CMD_CHANNEL_STATE_FLUSHED +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_BUSY NV5070_CTRL_CMD_CHANNEL_STATE_BUSY +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_DEALLOC NV5070_CTRL_CMD_CHANNEL_STATE_DEALLOC +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_DEALLOC_LIMBO NV5070_CTRL_CMD_CHANNEL_STATE_DEALLOC_LIMBO +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_LIMBO1 NV5070_CTRL_CMD_CHANNEL_STATE_LIMBO1 +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_LIMBO2 NV5070_CTRL_CMD_CHANNEL_STATE_LIMBO2 +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_FCODEINIT NV5070_CTRL_CMD_CHANNEL_STATE_FCODEINIT +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_FCODE NV5070_CTRL_CMD_CHANNEL_STATE_FCODE +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_VBIOSINIT NV5070_CTRL_CMD_CHANNEL_STATE_VBIOSINIT +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_VBIOSOPER NV5070_CTRL_CMD_CHANNEL_STATE_VBIOSOPER +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_UNCONNECTED NV5070_CTRL_CMD_CHANNEL_STATE_UNCONNECTED +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_INITIALIZE NV5070_CTRL_CMD_CHANNEL_STATE_INITIALIZE +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_SHUTDOWN1 NV5070_CTRL_CMD_CHANNEL_STATE_SHUTDOWN1 +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_SHUTDOWN2 NV5070_CTRL_CMD_CHANNEL_STATE_SHUTDOWN2 +#define NV5070_CTRL_GET_CHANNEL_INFO_STATE_NO_METHOD_PENDING (NV5070_CTRL_GET_CHANNEL_INFO_STATE_EMPTY | NV5070_CTRL_GET_CHANNEL_INFO_STATE_WRTIDLE | NV5070_CTRL_GET_CHANNEL_INFO_STATE_IDLE) +#define NV5070_CTRL_CMD_GET_CHANNEL_INFO_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV5070_CTRL_CMD_GET_CHANNEL_INFO_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 channelClass; + NvU32 channelInstance; + NvBool IsChannelInDebugMode; + + NvU32 channelState; +} NV5070_CTRL_CMD_GET_CHANNEL_INFO_PARAMS; + + + +/* + * NV5070_CTRL_CMD_SET_ACCL + * + * This command turns accelerators on and off. The use of this command + * should be restricted as it may have undesirable effects. It's + * purpose is to provide a mechanism for clients to use the + * accelerator bits to get into states that are either not detectable + * by the RM or may take longer to reach than we think is reasonable + * to wait in the RM. + * + * NV5070_CTRL_CMD_GET_ACCL + * + * This command queries the current state of the accelerators. + * + * channelClass + * This field indicates the hw class number (507A-507E) + * + * channelInstance + * This field indicates which of the two instances of the channel + * (in case there are two. ex: base, overlay etc) the cmd is meant for. + * Note that core channel has only one instance and the field should + * be set to 0 for core channel. + * + * accelerators + * Accelerators to be set in the SET_ACCEL command. Returns the + * currently set accelerators on the GET_ACCEL command. + * + * accelMask + * A mask to specify which accelerators to change with the + * SET_ACCEL command. This field does nothing in the GET_ACCEL + * command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_CHANNEL + * NV_ERR_INVALID_OWNER + * NV_ERR_GENERIC + * + */ + +#define NV5070_CTRL_CMD_SET_ACCL (0x5070010c) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_SET_ACCL_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_ACCL (0x5070010d) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_GET_ACCL_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_ACCL_NONE NV5070_CTRL_IDLE_CHANNEL_ACCL_NONE +#define NV5070_CTRL_ACCL_IGNORE_PI NV5070_CTRL_IDLE_CHANNEL_ACCL_IGNORE_PI +#define NV5070_CTRL_ACCL_SKIP_NOTIF NV5070_CTRL_IDLE_CHANNEL_ACCL_SKIP_NOTIF +#define NV5070_CTRL_ACCL_SKIP_SEMA NV5070_CTRL_IDLE_CHANNEL_ACCL_SKIP_SEMA +#define NV5070_CTRL_ACCL_IGNORE_INTERLOCK NV5070_CTRL_IDLE_CHANNEL_ACCL_IGNORE_INTERLOCK +#define NV5070_CTRL_ACCL_IGNORE_FLIPLOCK NV5070_CTRL_IDLE_CHANNEL_ACCL_IGNORE_FLIPLOCK +#define NV5070_CTRL_ACCL_TRASH_ONLY NV5070_CTRL_IDLE_CHANNEL_ACCL_TRASH_ONLY +#define NV5070_CTRL_ACCL_TRASH_AND_ABORT NV5070_CTRL_IDLE_CHANNEL_ACCL_TRASH_AND_ABORT +#define NV5070_CTRL_SET_ACCL_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV5070_CTRL_SET_ACCL_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 channelClass; + NvU32 channelInstance; + + NvU32 accelerators; + NvU32 accelMask; +} NV5070_CTRL_SET_ACCL_PARAMS; +#define NV5070_CTRL_GET_ACCL_PARAMS_MESSAGE_ID (0xDU) + +typedef NV5070_CTRL_SET_ACCL_PARAMS NV5070_CTRL_GET_ACCL_PARAMS; + +/* + * NV5070_CTRL_CMD_STOP_BASE + * + * This command tries to turn the base channel off ASAP. + * + * channelInstance + * This field indicates which of the two instances of the base + * channel the cmd is meant for. + * + * notifyMode + * This field indicates the action RM should take once the base + * channel has been successfully stopped. The options are (1) Set a + * notifier (2) Set the notifier and generate and OS event + * + * hNotifierCtxDma + * Handle to the ctx dma for the notifier that must be written once + * base channel is stopped. The standard NvNotification notifier + * structure is used. + * + * offset + * Offset within the notifier context dma where the notifier begins + * Offset must be 16 byte aligned. + * + * hEvent + * Handle to the event that RM must use to awaken the client when + * notifyMode is WRITE_AWAKEN. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT: Invalid notify mode + * NV_ERR_INVALID_CHANNEL: When the overlay is unallocated + * NV_ERR_INVALID_OWNER: Callee isn't the owner of the channel + * NV_ERR_INVALID_OBJECT_HANDLE: Notif ctx dma not found + * NV_ERR_INVALID_OFFSET: Bad offset within notif ctx dma + * NV_ERR_INSUFFICIENT_RESOURCES + * NV_ERR_TIMEOUT: RM timedout waiting to inject methods + */ +#define NV5070_CTRL_CMD_STOP_BASE (0x5070010e) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_CMD_STOP_BASE_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_STOP_BASE_NOTIFY_MODE_WRITE (0x00000000) +#define NV5070_CTRL_CMD_STOP_BASE_NOTIFY_MODE_WRITE_AWAKEN (0x00000001) + +#define NV5070_CTRL_CMD_STOP_BASE_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV5070_CTRL_CMD_STOP_BASE_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 channelInstance; + NvU32 notifyMode; + NvHandle hNotifierCtxDma; + NvU32 offset; + NV_DECLARE_ALIGNED(NvP64 hEvent, 8); +} NV5070_CTRL_CMD_STOP_BASE_PARAMS; + + + +/* + * NV5070_CTRL_CMD_GET_PINSET_COUNT + * + * Get number of pinsets on this GPU. + * + * pinsetCount [out] + * Number of pinsets on this GPU is returned in this parameter. + * This count includes pinsets that are not connected. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV5070_CTRL_CMD_GET_PINSET_COUNT (0x50700115) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_GET_PINSET_COUNT_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_GET_PINSET_COUNT_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV5070_CTRL_GET_PINSET_COUNT_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 pinsetCount; +} NV5070_CTRL_GET_PINSET_COUNT_PARAMS; + +/* + * NV5070_CTRL_CMD_GET_PINSET_PEER + * + * Retrieve the pinset/GPU that is connected to the specified pinset on + * this GPU. + * + * pinset [in] + * Pinset on this GPU for which peer info is to be returned must be + * specified in this parameter. + * + * peerGpuId [out] + * Instance of the GPU on the other side of the connection is + * returned in this parameter. + * + * peerPinset [out] + * Pinset on the other side of the connection is returned in this + * parameter. If there is no connection then the value is + * NV5070_CTRL_CMD_GET_PINSET_PEER_PEER_PINSET_NONE. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV5070_CTRL_CMD_GET_PINSET_PEER (0x50700116) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_GET_PINSET_PEER_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_PINSET_PEER_PEER_GPUINSTANCE_NONE (0xffffffff) + +#define NV5070_CTRL_CMD_GET_PINSET_PEER_PEER_PINSET_NONE (0xffffffff) + +#define NV5070_CTRL_GET_PINSET_PEER_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV5070_CTRL_GET_PINSET_PEER_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 pinset; + + NvU32 peerGpuInstance; + NvU32 peerPinset; +} NV5070_CTRL_GET_PINSET_PEER_PARAMS; + +/* + * NV5070_CTRL_CMD_SET_RMFREE_FLAGS + * + * This command sets the flags for an upcoming call to RmFree(). + * After the RmFree() API runs successfully or not, the flags are cleared. + * + * flags + * This parameter holds the NV0000_CTRL_GPU_SET_RMFREE_FLAGS_* + * flags to be passed for the next RmFree() command only. + * The flags can be one of those: + * - NV0000_CTRL_GPU_SET_RMFREE_FLAGS_NONE: + * explicitly clears the flags + * - NV0000_CTRL_GPU_SET_RMFREE_FLAGS_FREE_PRESERVES_HW: + * instructs RmFree() to preserve the HW configuration. After + * RmFree() is run this flag is cleared. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV5070_CTRL_CMD_SET_RMFREE_FLAGS (0x50700117) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_SET_RMFREE_FLAGS_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_SET_RMFREE_FLAGS_NONE 0x00000000 +#define NV5070_CTRL_SET_RMFREE_FLAGS_PRESERVE_HW 0x00000001 +#define NV5070_CTRL_SET_RMFREE_FLAGS_PARAMS_MESSAGE_ID (0x17U) + +typedef struct NV5070_CTRL_SET_RMFREE_FLAGS_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 flags; +} NV5070_CTRL_SET_RMFREE_FLAGS_PARAMS; + + +/* + * NV5070_CTRL_CMD_IMP_SET_GET_PARAMETER + * + * This command allows to set or get certain IMP parameters. Change of + * values take effect on next modeset and is persistent across modesets + * until the driver is unloaded or user changes the override. + * + * index + * One of NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_XXX defines - + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IMP_ENABLE + * Only supports "get" operation. If FALSE, IMP is being bypassed and + * all Is Mode Possible queries are answered with "mode is possible" + * and registers normally set by IMP are not changed from their defaults. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED + * Should IMP consider using ASR. ASR won't be allowed unless it is set to + * "allowed" through both _IS_ASR_ALLOWED and _IS_ASR_ALLOWED_PER_PSTATE. + * Note that IMP will not run ASR and MSCG at the same time. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED_PER_PSTATE + * Should IMP consider using ASR when this pstate is being used. ASR won't + * be allowed unless it is set to "allowed" through both + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED and + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED_PER_PSTATE. + * So when NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED + * returns FALSE, IMP won't consider ASR for any p-state. Note that IMP + * will not run ASR and MSCG at the same time. This function is valid + * only on PStates 2.0 systems. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_MSCG_ALLOWED_PER_PSTATE + * Should IMP consider using MSCG when this pstate is being used. MSCG + * won't be allowed if the MSCG feature isn't enabled even if we set to + * "allowed" through + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_MSCG_ALLOWED_PER_PSTATE. + * Use NV2080_CTRL_CMD_MC_QUERY_POWERGATING_PARAMETER to query if MSCG is + * supported and enabled. Note that IMP will not run ASR and MSCG at the + * same time. This function is valid only on PStates 2.0 systems. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_STUTTER_FEATURE_PER_PSTATE + * Only supports "get" operation. Returns which stutter feature is being + * engaged in hardware when running on the given pstate. Valid values are: + * NV5070_CTRL_IMP_STUTTER_FEATURE_NONE + * This value indicates no stutter feature is enabled. + * NV5070_CTRL_IMP_STUTTER_FEATURE_ASR + * This value indicates ASR is the current enabled stutter feature. + * NV5070_CTRL_IMP_STUTTER_FEATURE_MSCG + * This value indicates MSCG is the current enabled stutter feature. + * Note that system will not run ASR and MSCG at the same time. This + * function is valid only on PStates 2.0 systems. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_STUTTER_FEATURE_PREDICTED_EFFICIENCY_PER_PSTATE + * Only supports "get" operation. Returns the efficiency which IMP + * predicted for the engaged stutter feature (ASR or MSCG) when running + * on the given pstate. Normally, the actual efficiency should be higher + * than the calculated predicted efficiency. For MSCG, the predicted + * efficiency assumes no mempool compression. If compression is enabled + * with MSCG, the actual efficiency may be significantly higher. Returns + * 0 if no stutter feature is running. On PStates 3.0 systems, the + * pstateApi parameter is ignored, and the result is returned for the min + * IMP v-pstate possible. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS + * Only supports "get" operation. Returns information about what the possible + * mclk switch is. Valid fields are: + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_POSSIBLE + * This field is not head-specific and indicates if mclk switch is + * possible with the current mode. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_OVERRIDE_MEMPOOL + * This field is not head-specific and indicates if mclk switch is + * possible with the nominal mempool settings (_NO) or if special + * settings are required in order for mclk switch to be possible (_YES). + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_MID_WATERMARK + * Each head has its own setting for this field. If this field is + * set to _YES, then the specified head will allow mclk switch to + * begin if mempool occupancy exceeds the MID_WATERMARK setting. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_DWCF + * Each head has its own setting for this field. If this field is + * set to _YES, then the specified head will allow mclk switch to + * begin if the head is in its DWCF interval, and the mempool + * occupancy is greater than or equal to the DWCF watermark. + * Note: If neither _MID_WATERMARK nor _DWCF is set to _YES, then the + * specified head is ignored when determining when it is OK to start an + * mclk switch. Mclk switch must be allowed (or ignored) by all heads + * before an mclk switch will actually begin. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_FORCE_MIN_MEMPOOL + * Should min mempool be forced. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MEMPOOL_COMPRESSION + * Should mempool compression be enabled. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_CURSOR_SIZE + * The cursor size (in horizontal pixels) used by IMP (rather than the + * actual cursor size) for its computation. + * A maximum value is in place for what can be set. It can be queried + * after resetting the value - it gets reset to the maximum possible + * value. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_ENABLE + * This is to Enable/Disable ISO FB Latency Test. + * The test records the max ISO FB latency for all heads during the test period (excluding modeset time). + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_WC_TOTAL_LATENCY + * This is used to retrieve calculated wcTotalLatency of ISO FB Latency Test. + * wcTotalLatency is the worst case time for a request's data to come back after the request is issued. + * It is the sum of IMP calculated FbLatency and stream delay. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_MAX_LATENCY + * This is used to retrieve the max latency among all heads during the whole ISO FB Latency Test. + * The max latency can be used to compare with the wcTotalLatency we calculated. + * It decides whether the ISO FB Latency Test is passed or not. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_MAX_TEST_PERIOD + * This is used to retrieve the max test period during the whole ISO FB Latency Test. + * By experimental result, the test period should be at least 10 secs to approximate the + * worst case Fb latency in real situation. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_GLITCHLESS_MODESET_ENABLE + * This enables or disables glitchless modesets. Modesets can be + * glitchless if: + * (1) There are no raster timing changes, and + * (2) The resource requirements of all bandwidth clients are either not + * changing, or they are all changing in the same direction (all + * increasing or all decreasing). + * If glitchless modeset is disabled, or is not possible, heads will be + * blanked during the modeset transition. + * pstateApi + * NV2080_CTRL_PERF_PSTATES_PXXX value. + * Required for NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED_PER_PSTATE, + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_MSCG_ALLOWED_PER_PSTATE, + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_STUTTER_FEATURE_PER_PSTATE and + * NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_STUTTER_FEATURE_PREDICTED_EFFICIENCY_PER_PSTATE + * on PStates 2.0 systems. For other indices must be + * NV2080_CTRL_PERF_PSTATES_UNDEFINED. Not used on PStates 3.0 systems. + * head + * Head index, which is required when querying Mclk switch feature. + * (index = NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS) + * operation + * NV5070_CTRL_IMP_SET_GET_PARAMETER_OPERATION_GET + * Indicates a "get" operation. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_OPERATION_SET + * Indicates a "set" operation. + * NV5070_CTRL_IMP_SET_GET_PARAMETER_OPERATION_RESET + * Indicates a "reset" operation. This operation will reset the values for + * all indices to their RM defaults. + * value + * Value for new setting of a "set" operation, or the returned value of a + * "get" operation; for enable/disable operations, "enable" is non-zero, + * and "disable" is zero. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_POINTER + * NV_ERR_INVALID_INDEX specified index is not supported + * NV_ERR_INSUFFICIENT_RESOURCES cannot handle any more overrides + * NV_ERR_INVALID_OBJECT the struct needed to get the specified information + * is not marked as valid + * NV_ERR_INVALID_STATE the parameter has been set but resetting will + * not be possible + */ +#define NV5070_CTRL_CMD_IMP_SET_GET_PARAMETER (0x50700118) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_IMP_SET_GET_PARAMETER_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NV5070_CTRL_IMP_SET_GET_PARAMETER_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 index; + NvU32 pstateApi; + NvU32 head; + NvU32 operation; + NvU32 value; +} NV5070_CTRL_IMP_SET_GET_PARAMETER_PARAMS; + +/* valid operation values */ +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_OPERATION_GET 0 +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_OPERATION_SET 1 +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_OPERATION_RESET 2 + +/* valid index value */ +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_NONE (0x00000000) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IMP_ENABLE (0x00000001) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED (0x00000002) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_ASR_ALLOWED_PER_PSTATE (0x00000003) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_IS_MSCG_ALLOWED_PER_PSTATE (0x00000004) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_STUTTER_FEATURE_PER_PSTATE (0x00000005) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_STUTTER_FEATURE_PREDICTED_EFFICIENCY_PER_PSTATE (0x00000006) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS (0x00000007) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_FORCE_MIN_MEMPOOL (0x00000008) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MEMPOOL_COMPRESSION (0x00000009) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_CURSOR_SIZE (0x0000000A) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_ENABLE (0x0000000B) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_WC_TOTAL_LATENCY (0x0000000C) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_MAX_LATENCY (0x0000000D) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOFBLATENCY_TEST_MAX_TEST_PERIOD (0x0000000E) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_GLITCHLESS_MODESET_ENABLE (0x0000000F) + +/* valid NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_ISOHUB_STUTTER_FEATURE values */ +#define NV5070_CTRL_IMP_STUTTER_FEATURE_NONE 0 +#define NV5070_CTRL_IMP_STUTTER_FEATURE_ASR 1 +#define NV5070_CTRL_IMP_STUTTER_FEATURE_MSCG 2 + +/* valid NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE values */ +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_POSSIBLE 0:0 +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_POSSIBLE_NO (0x00000000) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_POSSIBLE_YES (0x00000001) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_OVERRIDE_MEMPOOL 1:1 +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_OVERRIDE_MEMPOOL_NO (0x00000000) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_OVERRIDE_MEMPOOL_YES (0x00000001) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_MID_WATERMARK 2:2 +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_MID_WATERMARK_NO (0x00000000) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_MID_WATERMARK_YES (0x00000001) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_DWCF 3:3 +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_DWCF_NO (0x00000000) +#define NV5070_CTRL_IMP_SET_GET_PARAMETER_INDEX_MCLK_SWITCH_FEATURE_OUTPUTS_VALUE_DWCF_YES (0x00000001) + +/* + * NV5070_CTRL_CMD_SET_MEMPOOL_WAR_FOR_BLIT_TEARING + * + * This command engages the WAR for blit tearing caused by huge mempool size and + * mempool compression. The EVR in aero off mode uses scanline info to predict + * where the scanline will be at a later time. Since RG scanline is used to perform + * front buffer blits and isohub buffers large amount of display data it may have + * fetched several lines of data ahead of where the RG is scanning out leading to + * video tearing. The WAR for this problem is to reduce the amount of data fetched. + * + * base + * This struct must be the first member of all 5070 control calls containing + * the subdeviceIndex. + * bEngageWAR + * Indicates if mempool WAR has to be engaged or disengaged. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV5070_CTRL_CMD_SET_MEMPOOL_WAR_FOR_BLIT_TEARING (0x50700119) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_SET_MEMPOOL_WAR_FOR_BLIT_TEARING_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_SET_MEMPOOL_WAR_FOR_BLIT_TEARING_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV5070_CTRL_SET_MEMPOOL_WAR_FOR_BLIT_TEARING_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvBool bEngageWAR; +} NV5070_CTRL_SET_MEMPOOL_WAR_FOR_BLIT_TEARING_PARAMS; +typedef struct NV5070_CTRL_SET_MEMPOOL_WAR_FOR_BLIT_TEARING_PARAMS *PNV5070_CTRL_SET_MEMPOOL_WAR_FOR_BLIT_TEARING_PARAMS; + +#define NV5070_CTRL_CMD_GET_ACTIVE_VIEWPORT_BASE (0x50700120) /* finn: Evaluated from "(FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_ACTIVE_VIEWPORT_BASE_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_ACTIVE_VIEWPORT_BASE_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV5070_CTRL_CMD_GET_ACTIVE_VIEWPORT_BASE_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 head; + NvU32 activeViewportBase; +} NV5070_CTRL_CMD_GET_ACTIVE_VIEWPORT_BASE_PARAMS; +typedef struct NV5070_CTRL_CMD_GET_ACTIVE_VIEWPORT_BASE_PARAMS *PNV5070_CTRL_CMD_GET_ACTIVE_VIEWPORT_BASE_PARAMS; + +/* _ctrl5070chnc_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070common.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070common.h new file mode 100644 index 0000000..bbfa794 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070common.h @@ -0,0 +1,79 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070common.finn +// + + + +#define NV5070_CTRL_CMD_CHANNEL_STATE_IDLE NVBIT(0) +#define NV5070_CTRL_CMD_CHANNEL_STATE_WRTIDLE NVBIT(1) +#define NV5070_CTRL_CMD_CHANNEL_STATE_QUIESCENT1 NVBIT(2) +#define NV5070_CTRL_CMD_CHANNEL_STATE_QUIESCENT2 NVBIT(3) +#define NV5070_CTRL_CMD_CHANNEL_STATE_EMPTY NVBIT(4) +#define NV5070_CTRL_CMD_CHANNEL_STATE_FLUSHED NVBIT(5) +#define NV5070_CTRL_CMD_CHANNEL_STATE_BUSY NVBIT(6) +#define NV5070_CTRL_CMD_CHANNEL_STATE_DEALLOC NVBIT(7) +#define NV5070_CTRL_CMD_CHANNEL_STATE_DEALLOC_LIMBO NVBIT(8) +#define NV5070_CTRL_CMD_CHANNEL_STATE_LIMBO1 NVBIT(9) +#define NV5070_CTRL_CMD_CHANNEL_STATE_LIMBO2 NVBIT(10) +#define NV5070_CTRL_CMD_CHANNEL_STATE_FCODEINIT NVBIT(11) +#define NV5070_CTRL_CMD_CHANNEL_STATE_FCODE NVBIT(12) +#define NV5070_CTRL_CMD_CHANNEL_STATE_VBIOSINIT NVBIT(13) +#define NV5070_CTRL_CMD_CHANNEL_STATE_VBIOSOPER NVBIT(14) +#define NV5070_CTRL_CMD_CHANNEL_STATE_UNCONNECTED NVBIT(15) +#define NV5070_CTRL_CMD_CHANNEL_STATE_INITIALIZE NVBIT(16) +#define NV5070_CTRL_CMD_CHANNEL_STATE_SHUTDOWN1 NVBIT(17) +#define NV5070_CTRL_CMD_CHANNEL_STATE_SHUTDOWN2 NVBIT(18) +#define NV5070_CTRL_CMD_CHANNEL_STATE_INIT NVBIT(19) + +#define NV5070_CTRL_CMD_MAX_HEADS 4U +#define NV5070_CTRL_CMD_MAX_DACS 4U +#define NV5070_CTRL_CMD_MAX_SORS 8U +#define NV5070_CTRL_CMD_MAX_PIORS 4U + +#define NV5070_CTRL_CMD_OR_OWNER_NONE (0xFFFFFFFFU) +#define NV5070_CTRL_CMD_OR_OWNER_HEAD(i) (i) +#define NV5070_CTRL_CMD_OR_OWNER_HEAD__SIZE_1 NV5070_CTRL_CMD_MAX_HEADS + +#define NV5070_CTRL_CMD_SOR_OWNER_MASK_NONE (0x00000000U) +#define NV5070_CTRL_CMD_SOR_OWNER_MASK_HEAD(i) (1 << i) + +#define NV5070_CTRL_CMD_DAC_PROTOCOL_RGB_CRT (0x00000000U) + + + +#define NV5070_CTRL_CMD_SOR_PROTOCOL_SINGLE_TMDS_A (0x00000000U) +#define NV5070_CTRL_CMD_SOR_PROTOCOL_SINGLE_TMDS_B (0x00000001U) +#define NV5070_CTRL_CMD_SOR_PROTOCOL_DUAL_TMDS (0x00000002U) +#define NV5070_CTRL_CMD_SOR_PROTOCOL_LVDS_CUSTOM (0x00000003U) +#define NV5070_CTRL_CMD_SOR_PROTOCOL_DP_A (0x00000004U) +#define NV5070_CTRL_CMD_SOR_PROTOCOL_DP_B (0x00000005U) +#define NV5070_CTRL_CMD_SOR_PROTOCOL_SUPPORTED (0xFFFFFFFFU) + +#define NV5070_CTRL_CMD_PIOR_PROTOCOL_EXT_TMDS_ENC (0x00000000U) + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070event.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070event.h new file mode 100644 index 0000000..5154638 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070event.h @@ -0,0 +1,143 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070event.finn +// + +#include "ctrl/ctrl5070/ctrl5070base.h" + +/* NV50_DISPLAY event-related control commands and parameters */ + +/* + * NV5070_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * This command sets event notification state for the NV50_DISPLAY object. + * This command requires that an instance of NV01_EVENT has been previously + * bound to the NV50_DISPLAY object. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the NV50_DISPLAY + * parent device to which the operation should be directed. This parameter + * must specify a value between zero and the total number of subdevices + * within the parent device. This parameter should be set to zero for + * default behavior. + * hEvent + * This parameter specifies the handle of the NV01_EVENT instance + * to be bound to the given subDeviceInstance. + * event + * This parameter specifies the type of event to which the specified + * action is to be applied. This parameter must specify a valid + * NOTIFIERS value of display class. + * action + * This parameter specifies the desired event notification action. + * Valid notification actions include: + * NV5070_CTRL_SET_EVENT_NOTIFICATION_DISABLE + * This action disables event notification for the specified + * event for the associated subdevice object. + * NV5070_CTRL_SET_EVENT_NOTIFICATION_SINGLE + * This action enables single-shot event notification for the + * specified event for the associated subdevice object. + * NV5070_CTRL_SET_EVENT_NOTIFICATION_REPEAT + * This action enables repeated event notification for the specified + * event for the associated system controller object. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV5070_CTRL_CMD_EVENT_SET_NOTIFICATION (0x50700901) /* finn: Evaluated from "(FINN_NV50_DISPLAY_EVENT_INTERFACE_ID << 8) | NV5070_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV5070_CTRL_EVENT_SET_NOTIFICATION_PARAMS { + NvU32 subDeviceInstance; + NvHandle hEvent; + NvU32 event; + NvU32 action; +} NV5070_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001) +#define NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002) + + +/* + * NV5070_CTRL_CMD_EVENT_SET_TRIGGER + * + * This command triggers a software event for the NV50_DISPLAY object. + * This command accepts no parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV5070_CTRL_CMD_EVENT_SET_TRIGGER (0x50700902) /* finn: Evaluated from "(FINN_NV50_DISPLAY_EVENT_INTERFACE_ID << 8) | 0x2" */ + + +/* + * NV5070_CTRL_CMD_EVENT_SET_NOTIFIER_MEMORY + * + * hMemory + * This parameter specifies the handle of the memory object + * that identifies the memory address translation for this + * subdevice instance's notification(s). The beginning of the + * translation points to an array of notification data structures. + * The size of the translation must be at least large enough to hold the + * maximum number of notification data structures. + * Legal argument values must be instances of the following classes: + * NV01_NULL + * NV04_MEMORY + * When hMemory specifies the NV01_NULL_OBJECT value then any existing + * memory translation connection is cleared. There must not be any + * pending notifications when this command is issued. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV5070_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES (0x50700903) /* finn: Evaluated from "(FINN_NV50_DISPLAY_EVENT_INTERFACE_ID << 8) | NV5070_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV5070_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS { + NvU32 subDeviceInstance; + NvHandle hMemory; +} NV5070_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS; + +#define NV5070_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED 0 +#define NV5070_EVENT_MEMORY_NOTIFIES_STATUS_PENDING 1 +#define NV5070_EVENT_MEMORY_NOTIFIES_STATUS_ERROR 2 + + + +/* _ctrl5070event_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070impoverrides.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070impoverrides.h new file mode 100644 index 0000000..11b79b2 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070impoverrides.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070impoverrides.finn +// + + + + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h new file mode 100644 index 0000000..0052168 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h @@ -0,0 +1,936 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070or.finn +// + +#include "ctrl5070common.h" +#include "ctrl/ctrl5070/ctrl5070base.h" + + + +/* + * NV5070_CTRL_CMD_SET_DAC_PWR + * + * This command sets the DAC power control register. orNumber, normalPower, + * and safePower will always have to be specified. However, HSync, VSync, + * and data for normal and/or safe mode can be empty, leaving the current + * values intact. + * + * orNumber + * The dac for which the settings need to be programmed. + * + * normalHSync + * The normal operating state for the H sync signal. + * + * normalVSync + * The normal operating state for the V sync signal. + * + * normalData + * The normal video data input pin of the d/a converter. + * + * normalPower + * The normal state of the dac macro power. + * + * safeHSync + * The safe operating state for the H sync signal. + * + * safeVSync + * The safe operating state for the V sync signal. + * + * safeData + * The safe video data input pin of the d/a converter. + * + * safePower + * The safe state of the dac macro power. + * + * flags + * The following flags have been defined: + * (1) SPECIFIED_NORMAL: Indicates whether HSync, VSync, data, + * for normal state have been specified in the parameters. + * (2) SPECIFIED_SAFE: Indicates whether HSync, VSync, data, + * for safe state have been specified in the parameters. + * (3) SPECIFIED_FORCE_SWITCH: Indicates whether to force the + * change immediately instead of waiting for VSync + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + * NV_ERR_TIMEOUT + */ +#define NV5070_CTRL_CMD_SET_DAC_PWR (0x50700404) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_DAC_PWR_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_HSYNC 1:0 +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_HSYNC_ENABLE (0x00000000) +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_HSYNC_LO (0x00000001) +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_HSYNC_HI (0x00000002) + +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_VSYNC 1:0 +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_VSYNC_ENABLE (0x00000000) +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_VSYNC_LO (0x00000001) +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_VSYNC_HI (0x00000002) + +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_DATA 1:0 +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_DATA_ENABLE (0x00000000) +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_DATA_LO (0x00000001) +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_DATA_HI (0x00000002) + +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_PWR 0:0 +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_PWR_OFF (0x00000000) +#define NV5070_CTRL_CMD_SET_DAC_PWR_NORMAL_PWR_ON (0x00000001) + +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_HSYNC 1:0 +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_HSYNC_ENABLE (0x00000000) +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_HSYNC_LO (0x00000001) +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_HSYNC_HI (0x00000002) + +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_VSYNC 1:0 +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_VSYNC_ENABLE (0x00000000) +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_VSYNC_LO (0x00000001) +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_VSYNC_HI (0x00000002) + +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_DATA 1:0 +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_DATA_ENABLE (0x00000000) +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_DATA_LO (0x00000001) +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_DATA_HI (0x00000002) + +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_PWR 0:0 +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_PWR_OFF (0x00000000) +#define NV5070_CTRL_CMD_SET_DAC_PWR_SAFE_PWR_ON (0x00000001) + +#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_SPECIFIED_NORMAL 0:0 +#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_SPECIFIED_NORMAL_NO (0x00000000) +#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_SPECIFIED_NORMAL_YES (0x00000001) +#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_SPECIFIED_SAFE 1:1 +#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_SPECIFIED_SAFE_NO (0x00000000) +#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_SPECIFIED_SAFE_YES (0x00000001) +#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_FORCE_SWITCH 2:2 +#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_FORCE_SWITCH_NO (0x00000000) +#define NV5070_CTRL_CMD_SET_DAC_PWR_FLAGS_FORCE_SWITCH_YES (0x00000001) +#define NV5070_CTRL_CMD_SET_DAC_PWR_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV5070_CTRL_CMD_SET_DAC_PWR_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 orNumber; + + NvU32 normalHSync; + NvU32 normalVSync; + NvU32 normalData; + NvU32 normalPower; + NvU32 safeHSync; + NvU32 safeVSync; + NvU32 safeData; + NvU32 safePower; + NvU32 flags; +} NV5070_CTRL_CMD_SET_DAC_PWR_PARAMS; + + + +/* + * NV5070_CTRL_CMD_GET_SOR_PWM + * + * This command returns SOR's current PWM settings. + * + * orNumber + * The OR number for which the seq ctrls are to be modified. + * + * targetFreq + * The target PWM freq. This is the PWM frequency we planned on + * programming. + * + * actualFreq + * Actual PWM freq programmed into PWM. + * + * div + * The divider being used currently for generating PWM clk. + * A valued of 0 means that PWM is disabled. + * + * resolution + * The resolution of steps currently programmed or the max number of + * clocks per cycle. The possible values for NV50 are 128, 256, 512 + * and 1024. This field is irrelevant when div is 0. + * + * dutyCycle + * Duty cycle in range 0-1024 + * + * sourcePCLK (OUT) + * The PWM source clock selector. This field is non-zero if the PCLK + * is selected as the PWM source clock. Otherwise, the PWM source + * clock is XTAL. + * + * head (IN) + * The head for which the pixel clock is sourced from. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_GET_SOR_PWM (0x50700420) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_SOR_PWM_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_SOR_PWM_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV5070_CTRL_CMD_GET_SOR_PWM_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 orNumber; + NvU32 targetFreq; + NvU32 actualFreq; + NvU32 div; + NvU32 resolution; + NvU32 dutyCycle; + NvU32 sourcePCLK; + NvU32 head; +} NV5070_CTRL_CMD_GET_SOR_PWM_PARAMS; + + +/* + * NV5070_CTRL_CMD_SET_SOR_PWM + * + * This command returns SOR's current PWM settings. + * + * orNumber + * The OR number for which the seq ctrls are to be modified. + * + * targetFreq + * The target PWM freq to be programmed. + * + * actualFreq + * Actual PWM freq programmed into PWM after all the specified + * settings have been applied. + * + * div + * The divider to use for generating PWM clk. + * Set this to 0 to disable PWM. Note that only one of div + * or targetFreq can be specified at a time since specifying one + * automatically determines the value of the other. Selection is + * done via USE_SPECIFIED_DIV flag. + * + * resolution + * The resolution or the max number of clocks per cycle desired. + * Note that if it's not possible to program the given resolution + * and frequency (or div) combination, RM would not attempt to + * smartly lower the resolution. The call would return failure. + * The possible values for NV50 are 128, 256, 512 and 1024. This + * field is irrelevant when div is 0. + * + * dutyCycle + * Duty cycle in range 0-1024 + * + * flags + * The following flags have been defined: + * (1) USE_SPECIFIED_DIV: Indicates whether RM should use + * specified div or targetFreq when determining the divider + * for xtal clock. + * (2) PROG_DUTY_CYCLE: Indicates whether or not the caller + * desires to program duty cycle. Normally whenever pwm freq + * and range need to be programmed, it's expected that duty + * cycle would be reprogrammed as well but this is not + * enforced. + * (3) PROG_FREQ_AND_RANGE: Indicates whether or not the caller + * desires to program a new PWM setting (div and resolution). + * (4) SOURCE_CLOCK: Indicates whether the PCLK or XTAL is used + * as the PWM clock source. GT21x and better. + * + * head (IN) + * The head for which the pixel clock is sourced from. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_SET_SOR_PWM (0x50700421) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_SOR_PWM_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_USE_SPECIFIED_DIV 0:0 +#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_USE_SPECIFIED_DIV_NO (0x00000000) +#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_USE_SPECIFIED_DIV_YES (0x00000001) +#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_PROG_DUTY_CYCLE 1:1 +#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_PROG_DUTY_CYCLE_NO (0x00000000) +#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_PROG_DUTY_CYCLE_YES (0x00000001) +#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_PROG_FREQ_AND_RANGE 2:2 +#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_PROG_FREQ_AND_RANGE_NO (0x00000000) +#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_PROG_FREQ_AND_RANGE_YES (0x00000001) +#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_SOURCE_CLOCK 3:3 +#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_SOURCE_CLOCK_XTAL (0x00000000) +#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_SOURCE_CLOCK_PCLK (0x00000001) + +#define NV5070_CTRL_CMD_SET_SOR_PWM_PARAMS_MESSAGE_ID (0x21U) + +typedef struct NV5070_CTRL_CMD_SET_SOR_PWM_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 orNumber; + NvU32 targetFreq; + NvU32 actualFreq; + NvU32 div; // equivalent of NV_PDISP_SOR_PWM_DIV_DIVIDE + NvU32 resolution; // equivalent of NV_PDISP_SOR_PWM_DIV_RANGE + NvU32 dutyCycle; + NvU32 flags; + NvU32 head; +} NV5070_CTRL_CMD_SET_SOR_PWM_PARAMS; + + +/* + * NV5070_CTRL_CMD_GET_SOR_OP_MODE + * + * This command returns current settings for the specified SOR. + * + * orNumber + * The OR number for which the operating mode needs to be read. + * + * category + * Whether LVDS or CSTM setting are desired. + * + * puTxda + * Status of data pins of link A + * + * puTxdb + * Status of data pins of link B + * + * puTxca + * Status of link A clock + * + * puTxcb + * Status of link B clock + * + * upper + * Whether LVDS bank A is the upper, odd, or first pixel. + * + * mode + * Current protocol. + * + * linkActA + * Status of link B clock + * + * linkActB + * Status of link B clock + * + * lvdsEn + * Output driver configuration. + * + * lvdsDual + * Whether LVDS dual-link mode is turned on or not. + * + * dupSync + * Whether DE, HSYNC, and VSYNC are used for encoding instead of + * RES, CNTLE, and CNTLF. + * + * newMode + * Whether new or old mode is being used. + * + * balanced + * Whether balanced encoding is enabled. + * + * plldiv + * Feedback divider for the hi-speed pll + * + * rotClk + * Skew of TXC clock. + * + * rotDat + * How much are the 8 bits of each color channel rotated by + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE (0x50700422) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_SOR_OP_MODE_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_CATEGORY 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_CATEGORY_LVDS 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_CATEGORY_CUSTOM 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_0 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_0_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_0_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_1 1:1 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_1_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_1_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_2 2:2 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_2_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_2_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_3 3:3 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_3_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDA_3_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_0 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_0_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_0_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_1 1:1 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_1_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_1_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_2 2:2 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_2_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_2_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_3 3:3 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_3_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXDB_3_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXCA 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXCA_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXCA_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXCB 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXCB_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PU_TXCB_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_UPPER 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_UPPER_UPPER_RESET 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_MODE 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_MODE_LVDS 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_MODE_TMDS 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LINKACTA 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LINKACTA_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LINKACTA_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LINKACTB 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LINKACTB_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LINKACTB_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LVDS_EN 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LVDS_EN_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LVDS_EN_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LVDS_DUAL 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LVDS_DUAL_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_LVDS_DUAL_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_DUP_SYNC 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_DUP_SYNC_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_DUP_SYNC_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_NEW_MODE 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_NEW_MODE_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_NEW_MODE_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_BALANCED 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_BALANCED_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_BALANCED_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PLLDIV 0:0 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PLLDIV_BY_7 0x00000000 +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PLLDIV_BY_10 0x00000001 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_ROTCLK 3:0 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_ROTDAT 2:0 + +#define NV5070_CTRL_CMD_GET_SOR_OP_MODE_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NV5070_CTRL_CMD_GET_SOR_OP_MODE_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 orNumber; + + NvU32 category; + NvU32 puTxda; + NvU32 puTxdb; + NvU32 puTxca; + NvU32 puTxcb; + NvU32 upper; + NvU32 mode; + NvU32 linkActA; + NvU32 linkActB; + NvU32 lvdsEn; + NvU32 lvdsDual; + NvU32 dupSync; + NvU32 newMode; + NvU32 balanced; + NvU32 plldiv; + NvU32 rotClk; + NvU32 rotDat; +} NV5070_CTRL_CMD_GET_SOR_OP_MODE_PARAMS; + + +/* + * NV5070_CTRL_CMD_SET_SOR_OP_MODE + * + * This command applies the specified settings to the specified SOR. + * + * orNumber + * The OR number for which the operating mode needs to be read. + * Note that if DCB doesn't report LVDS for the specified orNumber, + * the call will return failure. + * + * category + * Whether LVDS or CSTM settings are specified. + * + * puTxda + * Used to enable or disable the data pins of link A. + * + * puTxdb + * Used to enable or disable the data pins of link B. + * + * puTxca + * Used to enable or disable link A clock. + * + * puTxcb + * Used to enable or disable link B clock. + * + * upper + * Whether LVDS bank A should be the upper, odd, or first pixel. + * + * mode + * What protocol (LVDS/TMDS to use). + * + * linkActA + * Used to enable or disable the digital logic of link A. + * + * linkActB + * Used to enable or disable the digital logic of link B. + * + * lvdsEn + * Output driver configuration. + * + * lvdsDual + * Whether to turn on LVDS dual-link mode. + * + * dupSync + * Whether to use DE, HSYNC, and VSYNC for encoding instead of + * RES, CNTLE, and CNTLF. + * + * newMode + * Whether to use new or old mode. + * + * balanced + * Whether or not to use balanced encoding. + * + * plldiv + * Feedback divider to use for the hi-speed pll. + * + * rotClk + * How much to skew TXC clock. + * + * rotDat + * How much to rotate the 8 bits of each color channel by. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE (0x50700423) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_SOR_OP_MODE_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_CATEGORY 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_CATEGORY_LVDS 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_CATEGORY_CUSTOM 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_0 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_0_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_0_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_1 1:1 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_1_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_1_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_2 2:2 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_2_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_2_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_3 3:3 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_3_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDA_3_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_0 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_0_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_0_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_1 1:1 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_1_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_1_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_2 2:2 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_2_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_2_ENABLE 0x00000001 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_3 3:3 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_3_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXDB_3_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXCA 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXCA_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXCA_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXCB 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXCB_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PU_TXCB_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_UPPER 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_UPPER_UPPER_RESET 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_MODE 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_MODE_LVDS 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_MODE_TMDS 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LINKACTA 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LINKACTA_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LINKACTA_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LINKACTB 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LINKACTB_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LINKACTB_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LVDS_EN 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LVDS_EN_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LVDS_EN_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LVDS_DUAL 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LVDS_DUAL_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_LVDS_DUAL_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_DUP_SYNC 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_DUP_SYNC_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_DUP_SYNC_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_NEW_MODE 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_NEW_MODE_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_NEW_MODE_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_BALANCED 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_BALANCED_DISABLE 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_BALANCED_ENABLE 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PLLDIV 0:0 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PLLDIV_BY_7 0x00000000 +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PLLDIV_BY_10 0x00000001 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_ROTCLK 3:0 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_ROTDAT 2:0 + +#define NV5070_CTRL_CMD_SET_SOR_OP_MODE_PARAMS_MESSAGE_ID (0x23U) + +typedef struct NV5070_CTRL_CMD_SET_SOR_OP_MODE_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 orNumber; + + NvU32 category; + NvU32 puTxda; + NvU32 puTxdb; + NvU32 puTxca; + NvU32 puTxcb; + NvU32 upper; + NvU32 mode; + NvU32 linkActA; + NvU32 linkActB; + NvU32 lvdsEn; + NvU32 lvdsDual; + NvU32 dupSync; + NvU32 newMode; + NvU32 balanced; + NvU32 plldiv; + NvU32 rotClk; + NvU32 rotDat; +} NV5070_CTRL_CMD_SET_SOR_OP_MODE_PARAMS; + +/* + * NV5070_CTRL_CMD_GET_PIOR_OP_MODE + * + * This command returns current settings for the specified PIOR. + * + * orNumber + * The OR number for which the operating mode needs to be programmed. + * + * category + * Whether ext TMDS, TV, DRO or DRI settings are desired. + * EXT TV is not supported at the moment. + * EXT DisplayPort is specified through EXT 10BPC 444. + * + * clkPolarity + * Whether or not output clock is inverted relative to generated clock. + * + * clkMode + * Whether data being transmitted is SDR or DDR. + * + * clkPhs + * Position of the edge on which data is launched. + * + * unusedPins + * Status of unused pins of this PIOR. + * + * polarity + * Whether or not sync and DE pin polarities are inverted. + * + * dataMuxing + * How are the bits are multiplexed together. + * + * clkDelay + * Extra delay for the clock. + * + * dataDelay + * Extra delay for the data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE (0x50700430) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_PIOR_OP_MODE_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CATEGORY 2:0 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CATEGORY_EXT_TMDS 0x00000000 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CATEGORY_EXT_TV 0x00000001 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CATEGORY_DRO 0x00000003 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CATEGORY_DRI 0x00000004 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CATEGORY_EXT_10BPC_444 0x00000005 + +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_POLARITY 0:0 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_POLARITY_NORMAL 0x00000000 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_POLARITY_INV 0x00000001 + +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_MODE 0:0 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_MODE_SDR 0x00000000 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_MODE_DDR 0x00000001 + +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_PHS 1:0 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_PHS_0 0x00000000 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_PHS_1 0x00000001 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_PHS_2 0x00000002 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_PHS_3 0x00000003 + +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_UNUSED_PINS 0:0 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_UNUSED_PINS_LO 0x00000000 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_UNUSED_PINS_TS 0x00000001 + +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_H 0:0 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_H_NORMAL 0x00000000 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_H_INV 0x00000001 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_V 1:1 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_V_NORMAL 0x00000000 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_V_INV 0x00000001 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_DE 2:2 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_DE_NORMAL 0x00000000 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_DE_INV 0x00000001 + +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_MUXING 3:0 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_MUXING_RGB_0 0x00000000 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_MUXING_RGB_1 0x00000001 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_MUXING_DIST_RNDR 0x00000003 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_MUXING_YUV_0 0x00000004 +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_MUXING_UYVY 0x00000005 + +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_DLY 2:0 + +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_DLY 2:0 + +#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_PARAMS_MESSAGE_ID (0x30U) + +typedef struct NV5070_CTRL_CMD_GET_PIOR_OP_MODE_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 orNumber; + + NvU32 category; + NvU32 clkPolarity; + NvU32 clkMode; + NvU32 clkPhs; + NvU32 unusedPins; + NvU32 polarity; + NvU32 dataMuxing; + NvU32 clkDelay; + NvU32 dataDelay; +} NV5070_CTRL_CMD_GET_PIOR_OP_MODE_PARAMS; + + +/* + * NV5070_CTRL_CMD_SET_PIOR_OP_MODE + * + * This command applies the specified settings to the specified PIOR. + * + * orNumber + * The OR number for which the operating mode needs to be programmed. + * + * category + * Whether ext TMDS, TV, DRO or DRI settings are to be programmed. + * EXT TV is not supported at the moment. + * EXT DisplayPort is specified through EXT 10BPC 444. + * + * clkPolarity + * Whether or not to invert output clock relative to generated clock. + * + * clkMode + * Whether data being transmitted should be SDR or DDR. + * + * clkPhs + * Position of the edge on which data should be launched. + * + * unusedPins + * What to do with unused pins of this PIOR. + * + * polarity + * Whether or not to invert sync and DE pin polarities. + * + * dataMuxing + * How to multiplex the bits together. + * + * clkDelay + * Extra delay for the clock. + * + * dataDelay + * Extra delay for the data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE (0x50700431) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_PIOR_OP_MODE_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CATEGORY 2:0 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CATEGORY_EXT_TMDS 0x00000000 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CATEGORY_EXT_TV 0x00000001 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CATEGORY_DRO 0x00000003 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CATEGORY_DRI 0x00000004 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CATEGORY_EXT_10BPC_444 0x00000005 + +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_POLARITY 0:0 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_POLARITY_NORMAL 0x00000000 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_POLARITY_INV 0x00000001 + +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_MODE 0:0 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_MODE_SDR 0x00000000 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_MODE_DDR 0x00000001 + +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_PHS 1:0 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_PHS_0 0x00000000 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_PHS_1 0x00000001 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_PHS_2 0x00000002 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_PHS_3 0x00000003 + +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_UNUSED_PINS 0:0 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_UNUSED_PINS_LO 0x00000000 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_UNUSED_PINS_TS 0x00000001 + +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_H 0:0 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_H_NORMAL 0x00000000 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_H_INV 0x00000001 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_V 1:1 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_V_NORMAL 0x00000000 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_V_INV 0x00000001 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_DE 2:2 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_DE_NORMAL 0x00000000 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_DE_INV 0x00000001 + +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_MUXING 3:0 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_MUXING_RGB_0 0x00000000 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_MUXING_RGB_1 0x00000001 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_MUXING_DIST_RNDR 0x00000003 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_MUXING_YUV_0 0x00000004 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_MUXING_UYVY 0x00000005 + +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_DLY 2:0 + +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_DLY 2:0 + +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DRO_MASTER 1:0 + +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DRO_DRIVE_PIN_SET 2:0 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DRO_DRIVE_PIN_SET_NEITHER 0 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DRO_DRIVE_PIN_SET_A 1 +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DRO_DRIVE_PIN_SET_B 2 + + +#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_PARAMS_MESSAGE_ID (0x31U) + +typedef struct NV5070_CTRL_CMD_SET_PIOR_OP_MODE_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 orNumber; + + NvU32 category; + NvU32 clkPolarity; + NvU32 clkMode; + NvU32 clkPhs; + NvU32 unusedPins; + NvU32 polarity; + NvU32 dataMuxing; + NvU32 clkDelay; + NvU32 dataDelay; + NvU32 dro_master; + NvU32 dro_drive_pin_set; +} NV5070_CTRL_CMD_SET_PIOR_OP_MODE_PARAMS; + +/* + * NV5070_CTRL_CMD_SET_SOR_FLUSH_MODE + * + * Set the given SOR number into flush mode in preparation for DP link training. + * + * orNumber [in] + * The SOR number to set into flush mode. + * + * bEnable [in] + * Whether to enable or disable flush mode on this SOR. + * + * bImmediate [in] + * If set to true, will enable flush in immediate mode. + * If not, will enable flush in loadv mode. + * NOTE: We do not support exit flush in LoadV mode. + * + * headMask [in] + * Optional. If set brings only the heads in the head mask out of flush + * OR will stay in flush mode until last head is out of flush mode. + * Caller can use _HEAD__ALL to specify all the heads are to be brought out. + * NOTE: headMask would be considered only while exiting from flush mode. + * + * bForceRgDiv [in] + * If set forces RgDiv. Should be used only for HW/SW testing + * + * bUseBFM [in] + * If Set then it mean we are using BFM else executing on non-BFM paltforms. + * + * bFireAndForget [in] + * Fire the flush mode & perform post-processing without waiting for it + * to be done. This is required for special cases like GC5 where we have + * ELV blocked, RG stall & we trigger flush for one shot mode & then do + * a modeset by disabling it without actually waiting for it to get + * disabled. We will not get any vblank interrupt in this case as we have + * stalled RG. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV5070_CTRL_CMD_SET_SOR_FLUSH_MODE (0x50700457) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS_MESSAGE_ID (0x57U) + +typedef struct NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 sorNumber; + NvBool bEnable; + NvBool bImmediate; + NvU32 headMask; + NvBool bForceRgDiv; + NvBool bUseBFM; + NvBool bFireAndForget; +} NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS; + +#define NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS_HEADMASK_HEAD(i) (i):(i) +#define NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS_HEADMASK_HEAD__SIZE_1 NV5070_CTRL_CMD_MAX_HEADS +#define NV5070_CTRL_SET_SOR_FLUSH_MODE_PARAMS_HEADMASK_HEAD_ALL 0xFFFFFFFF + + + +/* _ctrl5070or_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h new file mode 100644 index 0000000..64269d8 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h @@ -0,0 +1,578 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070rg.finn +// + +#include "ctrl/ctrl5070/ctrl5070base.h" + + + +/* + * NV5070_CTRL_CMD_GET_RG_STATUS + * + * This 'get' command returns the status of raster generator + * + * head + * The head for which RG status is desired. + * + * scanLocked + * Whether or not RG is scan (raster or frame) locked. + * flipLocked + * Whether or not RG is flip locked. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_GET_RG_STATUS (0x50700202) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_RG_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_RG_STATUS_SCANLOCKED_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_STATUS_SCANLOCKED_YES (0x00000001) + +#define NV5070_CTRL_CMD_GET_RG_STATUS_FLIPLOCKED_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_STATUS_FLIPLOCKED_YES (0x00000001) + +#define NV5070_CTRL_CMD_GET_RG_STATUS_STALLED_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_STATUS_STALLED_YES (0x00000001) + +#define NV5070_CTRL_CMD_GET_RG_STATUS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV5070_CTRL_CMD_GET_RG_STATUS_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 head; + + NvU32 scanLocked; // [OUT] + NvU32 flipLocked; // [OUT] + NvU32 rgStalled; +} NV5070_CTRL_CMD_GET_RG_STATUS_PARAMS; + +/* + * NV5070_CTRL_CMD_UNDERFLOW_PARAMS + * + * This structure contains data for + * NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP and + * NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP CTRL calls + * + * head + * The head for which RG underflow properties needed to be set/get. + * Valid values for this parameter are 0 to NV5070_CTRL_CMD_MAX_HEADS. + * enable + * _SET_RG_: Whether to enable or disable RG underflow reporting. + * _GET_RG_: Whether or not RG underflow reporting is enabled. + * underflow + * _SET_RG_: Clear underflow (CLEAR_UNDERFLOW_YES) or leave it alone + * (CLEAR_UNDERFLOW_NO). + * Note: The GET_RG function automatically clears the underflow. + * It is recommended that GET_RG be used to clear any initial + * underflows, and that the "underflow" field be set to + * CLEAR_UNDERFLOW_NO in any SET_RG calls. This field may be + * deprecated in the future, for SET_RG calls. + * _GET_RG_: UNDERFLOWED_YES if an RG underflow occurred since the most + * recent prior call to to NV5070_CTRL_CMD_GET_RG_STATUS. + * epfifoUnderflow + * _SET_RG_: Not used. + * _GET_RG_: EPFIFO_UNDERFLOWED_YES if an EPFIFO underflow occurred since + * the most recent prior call to NV5070_CTRL_CMD_GET_RG_STATUS. + * mode + * _SET_RG_: What mode to use when underflow occurs. This is + * independent from enable field. This is always active. + * _GET_RG_: What mode is used when underflow occurs. This is + * independent from enable field. This is always active. + */ +typedef struct NV5070_CTRL_CMD_UNDERFLOW_PARAMS { + NvU32 head; + NvU32 enable; + NvU32 underflow; + NvU32 epfifoUnderflow; + NvU32 mode; +} NV5070_CTRL_CMD_UNDERFLOW_PARAMS; + +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_ENABLED_NO (0x00000000) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_ENABLED_YES (0x00000001) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_UNDERFLOWED_NO (0x00000000) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_UNDERFLOWED_YES (0x00000001) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_EPFIFO_UNDERFLOWED_NO (0x00000000) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_EPFIFO_UNDERFLOWED_YES (0x00000001) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_MODE_REPEAT (0x00000000) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_MODE_RED (0x00000001) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_ENABLE_NO (0x00000000) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_ENABLE_YES (0x00000001) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_CLEAR_UNDERFLOW_NO (0x00000000) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_CLEAR_UNDERFLOW_YES (0x00000001) + +/* + * NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP + * + * This command returns the underflow reporting parameters inside + * NV5070_CTRL_CMD_UNDERFLOW_PARAMS structure + * + * underflowParams + * Contains data for underflow logging. + * Check NV5070_CTRL_CMD_UNDERFLOW_PARAMS structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP (0x50700203) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NV5070_CTRL_CMD_UNDERFLOW_PARAMS underflowParams; +} NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP_PARAMS; + + +/* + * NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP + * + * This command sets up the underflow parameters using + * NV5070_CTRL_CMD_UNDERFLOW_PARAMS structure + * + * underflowParams + * Contains data for underflow logging. + * Check NV5070_CTRL_CMD_UNDERFLOW_PARAMS structure. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP (0x50700204) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NV5070_CTRL_CMD_UNDERFLOW_PARAMS underflowParams; +} NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP_PARAMS; + + +/* + * NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP + * + * This command gets the timing parameters associated with the lockout period. + * + * head + * The head for which RG fliplock properties are desired. + * + * maxSwapLockoutSkew + * The maximum possible skew between the swap lockout signals for all + * heads which are fliplocked to this head. + * + * swapLockoutStart + * Determines the start of the start lockout period, expressed as the + * number of lines before the end of the frame. The minimum allowed + * value is 1. + + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP (0x50700205) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_MAX_SWAP_LOCKOUT_SKEW 9:0 + +#define NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_SWAP_LOCKOUT_START 15:0 + +#define NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 head; + + NvU32 maxSwapLockoutSkew; + NvU32 swapLockoutStart; +} NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_PARAMS; + +/* + * NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP + * + * This command sets the timing parameters associated with the lockout period. + * + * head + * The head for which RG fliplock properties are desired. + * + * maxSwapLockoutSkew + * The maximum possible skew between the swap lockout signals for all + * heads which are fliplocked to this head. + * + * swapLockoutStart + * Determines the start of the start lockout period, expressed as the + * number of lines before the end of the frame. The minimum allowed + * value is 1. + + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP (0x50700206) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_MAX_SWAP_LOCKOUT_SKEW 9:0 +#define NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_MAX_SWAP_LOCKOUT_SKEW_INIT (0x00000000) + +#define NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_SWAP_LOCKOUT_START 15:0 +#define NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_SWAP_LOCKOUT_START_INIT (0x00000000) + +#define NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 head; + + NvU32 maxSwapLockoutSkew; + NvU32 swapLockoutStart; +} NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS; + +/* + * NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN + * + * This command returns which lockpin has been connected for the specified + * subdevice in the current SLI and/or framelock configuration. + * + * head + * The head for which the locking is associated with + * + * masterScanLock + * Indicate the connection status and pin number of master scanlock + * + * slaveScanLock + * Indicate the connection status and pin number of slave scanlock + * + * flipLock + * Indicate the connection status and pin number of fliplock + * + * stereoLock + * Indicate the connection status and pin number of stereo lock + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN (0x50700207) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_MASTER_SCAN_LOCK_CONNECTED 0:0 +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_MASTER_SCAN_LOCK_CONNECTED_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_MASTER_SCAN_LOCK_CONNECTED_YES (0x00000001) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_MASTER_SCAN_LOCK_PIN 3:1 + +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_SLAVE_SCAN_LOCK_CONNECTED 0:0 +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_SLAVE_SCAN_LOCK_CONNECTED_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_SLAVE_SCAN_LOCK_CONNECTED_YES (0x00000001) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_SLAVE_SCAN_LOCK_PIN 3:1 + +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_FLIP_LOCK_CONNECTED 0:0 +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_FLIP_LOCK_CONNECTED_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_FLIP_LOCK_CONNECTED_YES (0x00000001) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_FLIP_LOCK_PIN 3:1 + +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STEREO_LOCK_CONNECTED 0:0 +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STEREO_LOCK_CONNECTED_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STEREO_LOCK_CONNECTED_YES (0x00000001) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STEREO_LOCK_PIN 3:1 + +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 head; + + NvU32 masterScanLock; + NvU32 slaveScanLock; + NvU32 flipLock; + NvU32 stereoLock; +} NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS; + +/* + * NV5070_CTRL_CMD_SET_VIDEO_STATUS + * + * This command is used to set the current video playback status for use + * by the Display Power Saving (nvDPS) feature. The playback status is + * used to maximize power savings by altering the DFP refresh rate used for + * video playback. + * + * displayId + * This parameter specifies the ID of the video playback display. + * Only one display may be indicated in this parameter. + * clientId + * This parameter specifies the opaque client ID associated with + * the video playback application. + * mode + * This parameter specifies the video playback mode. Valid values + * for this parameter include: + * NV5070_CTRL_DFP_SET_VIDEO_STATUS_MODE_NON_FULLSCREEN + * This value indicates that there is either no video playback or + * that video playback is windowed. + * NV5070_CTRL_DFP_SET_VIDEO_STATUS_MODE_FULLSCREEN + * This value indicates that video playback is fullscreen. + * NV5070_CTRL_DFP_SET_VIDEO_STATUS_MODE_D3D + * This value indicates that there is a D3D app started. + * frameRate + * The parameter indicates the current video playback frame rate. + * The value is a 32 bit unsigned fixed point number, 24 bit unsigned + * integer (bits 31:7), and 8 fraction bits (bits 7:0), measured in + * number of frames per second. + * A value of 0 indicates that video playback is stopped or not playing. + * frameRateAlarmUpperLimit + * The parameter indicates the upper limit which will can be tolerated in + * notifying frame rate change. If the frame rate changed but is still + * below the limit. The newer frame rate doesn't have to be set till it's + * over the limit. + * The value is a 32 bit unsigned fixed point number, 24 bit unsigned + * integer (bits 31:7), and 8 fraction bits (bits 7:0), measured in + * number of frames per second. + * A value of 0 indicates no tolerance of frame rate notifying. Instant + * frame rate has to be set when it has changed. + * frameRateAlarmLowerLimit + * The parameter indicates the lower limit which will can be tolerated in + * notifying frame rate change. If the frame rate changed but is still + * above the limit. The newer frame rate doesn't have to be set till it's + * below the limit. + * The value is a 32 bit unsigned fixed point number, 24 bit unsigned + * integer (bits 31:7), and 8 fraction bits (bits 7:0), measured in + * number of frames per second. + * A value of 0 indicates no tolerance of frame rate notifying. Instant + * frame rate has to be set when it has changed. + * + * The frameRateAlarm limit values can be used by the video client to + * indicate the the range in which frame rate changes do not require + * notification (i.e. frame rates outside these limits will result in + * notification). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV5070_CTRL_CMD_SET_VIDEO_STATUS (0x50700209) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_DFP_SET_VIDEO_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_DFP_SET_VIDEO_STATUS_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV5070_CTRL_DFP_SET_VIDEO_STATUS_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + + NvU32 displayId; + NvU32 clientId; + NvU32 mode; + NvU32 frameRate; + NvU32 frameRateAlarmUpperLimit; + NvU32 frameRateAlarmLowerLimit; +} NV5070_CTRL_DFP_SET_VIDEO_STATUS_PARAMS; + +/* valid mode flags */ +#define NV5070_CTRL_DFP_SET_VIDEO_STATUS_MODE_NON_FULLSCREEN (0x00000000) +#define NV5070_CTRL_DFP_SET_VIDEO_STATUS_MODE_FULLSCREEEN (0x00000001) +#define NV5070_CTRL_DFP_SET_VIDEO_STATUS_MODE_D3D (0x00000002) + +/* + * NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS + * + * This command returns which set of lockpins needs to be used in order to + * successfully raster lock two heads on different GPUs together. The + * second GPU is not inferred from linked SLI state, if any, and needs to + * be specified explicitly. + * + * head + * The local head to be locked with the peer head. + * + * peer.hDisplay + * The handle identifying a display object allocated on another + * GPU. It specifies the peer of interest with a subdevice + * index (see below) and needs to be be distinct from the handle + * supplied directly to NvRmControl(). + * + * peer.subdeviceIndex + * The index of the peer subdevice of interest. + * + * peer.head + * The peer head to be locked with the local head. + * + * masterScanLockPin + * slaveScanLockPin + * Returns the master and slave scanlock pins that would need to + * be used to lock the specified heads together, if any. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_OBJECT_PARENT + */ +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS (0x5070020a) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_MASTER_SCAN_LOCK_CONNECTED 0:0 +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_MASTER_SCAN_LOCK_CONNECTED_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_MASTER_SCAN_LOCK_CONNECTED_YES (0x00000001) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_MASTER_SCAN_LOCK_PIN 2:1 + +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_SLAVE_SCAN_LOCK_CONNECTED 0:0 +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_SLAVE_SCAN_LOCK_CONNECTED_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_SLAVE_SCAN_LOCK_CONNECTED_YES (0x00000001) +#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS_SLAVE_SCAN_LOCK_PIN 2:1 + +#define NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 head; + + struct { + NvHandle hDisplay; + NvU32 subdeviceIndex; + NvU32 head; + } peer; + + NvU32 masterScanLock; + NvU32 slaveScanLock; +} NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS; + +/* + * NV5070_CTRL_CMD_GET_PINSET_LOCKPINS + * + * Get the lockpins for the specified pinset. + * + * pinset [in] + * The pinset whose corresponding lockpin numbers need to be determined + * must be specified with this parameter. + * + * scanLockPin [out] + * The scanlock lockpin (rasterlock or framelock) index, which can be + * either master or slave, is returned in this parameter. + * + * flipLockPin [out] + * The fliplock lockpin index, is returned in this parameter. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV5070_CTRL_CMD_GET_PINSET_LOCKPINS (0x5070020b) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_GET_PINSET_LOCKPINS_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_GET_PINSET_LOCKPINS_SCAN_LOCK_PIN_NONE 0xffffffff + +#define NV5070_CTRL_GET_PINSET_LOCKPINS_FLIP_LOCK_PIN_NONE 0xffffffff + +#define NV5070_CTRL_GET_PINSET_LOCKPINS_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV5070_CTRL_GET_PINSET_LOCKPINS_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 pinset; + NvU32 scanLockPin; + NvU32 flipLockPin; +} NV5070_CTRL_GET_PINSET_LOCKPINS_PARAMS; + +/* + * NV5070_CTRL_CMD_GET_RG_SCAN_LINE + * + * This 'get' command returns the current scan line value from raster generator + * + * head + * The head for which current scan line number is desired. + * + * scanLine + * Current scan line number. + * + * inVblank + * Whether or not in vblank. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_GET_RG_SCAN_LINE (0x5070020c) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_RG_SCAN_LINE_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_RG_SCAN_LINE_IN_VBLANK_NO (0x00000000) +#define NV5070_CTRL_CMD_GET_RG_SCAN_LINE_IN_VBLANK_YES (0x00000001) + +#define NV5070_CTRL_CMD_GET_RG_SCAN_LINE_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV5070_CTRL_CMD_GET_RG_SCAN_LINE_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 head; + NvU32 scanLine; // [OUT] + NvU32 inVblank; // [OUT] +} NV5070_CTRL_CMD_GET_RG_SCAN_LINE_PARAMS; + +/* + * NV5070_CTRL_CMD_GET_FRAMELOCK_HEADER_LOCKPINS + * + * This command returns FrameLock header lock pin information. + * Lock pin index returned by this command corresponds to the + * evo lock pin number. Example - lock pin index 0 means + * LOCKPIN_0. + * + * frameLockPin [out] + * This parameter returns the FrameLock pin index + * connected to FrameLock header. + * + * rasterLockPin [out] + * This parameter returns the RasterLock pin index + * connected to FrameLock header. + * + * flipLockPin [out] + * This parameter returns the FlipLock pin index + * connected to FrameLock header. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV5070_CTRL_CMD_GET_FRAMELOCK_HEADER_LOCKPINS (0x5070020d) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_FRAME_LOCK_PIN_NONE (0xffffffff) +#define NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_RASTER_LOCK_PIN_NONE (0xffffffff) +#define NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_FLIP_LOCK_PIN_NONE (0xffffffff) +#define NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 frameLockPin; + NvU32 rasterLockPin; + NvU32 flipLockPin; +} NV5070_CTRL_GET_FRAMELOCK_HEADER_LOCKPINS_PARAMS; + + + +/* _ctrl5070rg_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070seq.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070seq.h new file mode 100644 index 0000000..0da723f --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070seq.h @@ -0,0 +1,521 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070seq.finn +// + +#include "ctrl/ctrl5070/ctrl5070base.h" + +/* + * NV5070_CTRL_CMD_GET_SOR_SEQ_CTL + * + * This command returns SOR sequencer's power up and down PCs and sequencer + * program to be used for power up and dowm. + * + * orNumber + * The OR number for which the seq ctrls are to be modified. + * + * puPcAlt + * Alternate power up PC. + * + * pdPc + * Power down PC. + * + * pdPcAlt + * Alternate power down PC. + * + * normalStart + * Whether normal mode is using normal or alt PC + * + * safeStart + * Whether safe mode is using normal or alt PC + * + * normalState + * Whether normal state is PD or PU. + * + * safeState + * Whether safe state is PD or PU. + * + * flags + * There is only one flag defined currently + * 1. GET_SEQ_PROG: Whether or not current seq program must be + * return back. Caller should set this to _YES to read the + * current seq program. + * + * seqProgram + * The sequencer program consisting of power up and down sequences. + * For NV50, this consists of 16 DWORDS. The program is + * relevant only when GET_SEQ_PROG flags is set to _YES. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL (0x50700301U) /* finn: Evaluated from "(FINN_NV50_DISPLAY_SEQ_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PU_PC_ALT_VALUE 3:0 + +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PD_PC_VALUE 3:0 + +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PD_PC_ALT_VALUE 3:0 + +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_NORMAL_START_VAL 0:0 +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_NORMAL_START_VAL_NORMAL (0x00000000U) +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_NORMAL_START_VAL_ALT (0x00000001U) + +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SAFE_START_VAL 0:0 +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SAFE_START_VAL_NORMAL (0x00000000U) +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SAFE_START_VAL_ALT (0x00000001U) + +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_NORMAL_STATE_VAL 0:0 +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_NORMAL_STATE_VAL_PD (0x00000000U) +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_NORMAL_STATE_VAL_PU (0x00000001U) + +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SAFE_STATE_VAL 0:0 +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SAFE_STATE_VAL_PD (0x00000000U) +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SAFE_STATE_VAL_PU (0x00000001U) + +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_FLAGS_GET_SEQ_PROG 0:0 +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_FLAGS_GET_SEQ_PROG_NO (0x00000000U) +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_FLAGS_GET_SEQ_PROG_YES (0x00000001U) + +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SEQ_PROG_SIZE 16U +#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 orNumber; + + NvU32 puPcAlt; + NvU32 pdPc; + NvU32 pdPcAlt; + NvU32 normalStart; + NvU32 safeStart; + NvU32 normalState; + NvU32 safeState; + NvU32 flags; + NvU32 seqProgram[NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SEQ_PROG_SIZE]; +} NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PARAMS; + +/* + * NV5070_CTRL_CMD_SET_SOR_SEQ_CTL + * + * This command does the following in that order + * (a) Loads a specified sequencer program for power up and down. + * (b) Updates SOR sequencer's power up and down PCs, tells seq to SKIP + * current wait for vsync and waits until sequencer actually SKIPs or halts + * (see more below under SKIP_WAIT_FOR_VSYNC flag) and + * (c) Update power settings (safe/normal start and state). + * + * orNumber + * The OR number for which the seq ctrls are to be modified. + * + * puPcAlt + * Alternate power up PC. + * + * pdPc + * Power down PC. + * + * pdPcAlt + * Alternate power down PC. + * + * normalStart + * Whether normal mode should use normal or alt PC. + * + * safeStart + * Whether safe mode should use normal or alt PC. + * + * normalState + * Whether normal state should be PD or PU. + * + * safeState + * Whether safe state should be PD or PU. + * + * flags + * The following flags have been defined + * 1. SKIP_WAIT_FOR_VSYNC: Should seq be forced to skip waiting + * for vsync if it's currently waiting on such an instruction. + * If the current instruction doesn't have a wait for vsync, + * SKIP will be applied to the next one and so on until + * either sequencer halts or an instruction with a wait for + * vsync is found. The call will block until seq halts or + * SKIPs a wait for vsync. + * 2. SEQ_PROG_PRESENT: Whether or not a new seq program has + * been specified. + * + * seqProgram + * The sequencer program consisting of power up and down sequences. + * For NV50, this consists of 16 DWORDS. The program is + * relevant only when SEQ_PROG_PRESENT flags is set to _YES. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL (0x50700302U) /* finn: Evaluated from "(FINN_NV50_DISPLAY_SEQ_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PU_PC_ALT_VALUE 3:0 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PU_PC_ALT_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PU_PC_ALT_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PU_PC_ALT_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_VALUE 3:0 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_ALT_VALUE 3:0 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_ALT_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_ALT_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_ALT_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_START_VAL 0:0 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_START_VAL_NORMAL (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_START_VAL_ALT (0x00000001U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_START_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_START_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_START_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_START_VAL 0:0 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_START_VAL_NORMAL (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_START_VAL_ALT (0x00000001U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_START_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_START_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_START_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_STATE_VAL 0:0 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_STATE_VAL_PD (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_STATE_VAL_PU (0x00000001U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_STATE_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_STATE_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_STATE_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_STATE_VAL 0:0 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_STATE_VAL_PD (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_STATE_VAL_PU (0x00000001U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_STATE_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_STATE_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_STATE_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_FLAGS_SKIP_WAIT_FOR_VSYNC 0:0 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_FLAGS_SKIP_WAIT_FOR_VSYNC_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_FLAGS_SKIP_WAIT_FOR_VSYNC_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_FLAGS_SEQ_PROG_PRESENT 1:1 +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_FLAGS_SEQ_PROG_PRESENT_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_FLAGS_SEQ_PROG_PRESENT_YES (0x00000001U) + + +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SEQ_PROG_SIZE 16U +#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 orNumber; + + NvU32 puPcAlt; + NvU32 pdPc; + NvU32 pdPcAlt; + NvU32 normalStart; + NvU32 safeStart; + NvU32 normalState; + NvU32 safeState; + NvU32 flags; + NvU32 seqProgram[NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SEQ_PROG_SIZE]; +} NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PARAMS; + +/* + * NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL + * + * This command returns PIOR sequencer's power up and down PCs and sequencer + * program to be used for power up and dowm. + * + * orNumber + * The OR number for which the seq ctrls are to be modified. + * + * puPcAlt + * Alternate power up PC. + * + * pdPc + * Power down PC. + * + * pdPcAlt + * Alternate power down PC. + * + * normalStart + * Whether normal mode is using normal or alt PC + * + * safeStart + * Whether safe mode is using normal or alt PC + * + * normalState + * Whether normal state is PD or PU. + * + * safeState + * Whether safe state is PD or PU. + * + * flags + * There is only one flag defined currently + * 1. GET_SEQ_PROG: Whether or not current seq program must be + * return back. Caller should set this to _YES to read the + * current seq program. + * + * seqProgram + * The sequencer program consisting of power up and down sequences. + * For NV50, this consists of 16 DWORDS. The program is + * relevant only when GET_SEQ_PROG flags is set to _YES. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL (0x50700303U) /* finn: Evaluated from "(FINN_NV50_DISPLAY_SEQ_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PU_PC_ALT_VALUE 3:0 + +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PD_PC_VALUE 3:0 + +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PD_PC_ALT_VALUE 3:0 + +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_NORMAL_START_VAL 0:0 +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_NORMAL_START_VAL_NORMAL (0x00000000U) +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_NORMAL_START_VAL_ALT (0x00000001U) + +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SAFE_START_VAL 0:0 +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SAFE_START_VAL_NORMAL (0x00000000U) +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SAFE_START_VAL_ALT (0x00000001U) + +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_NORMAL_STATE_VAL 0:0 +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_NORMAL_STATE_VAL_PD (0x00000000U) +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_NORMAL_STATE_VAL_PU (0x00000001U) + +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SAFE_STATE_VAL 0:0 +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SAFE_STATE_VAL_PD (0x00000000U) +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SAFE_STATE_VAL_PU (0x00000001U) + +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_FLAGS_GET_SEQ_PROG 0:0 +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_FLAGS_GET_SEQ_PROG_NO (0x00000000U) +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_FLAGS_GET_SEQ_PROG_YES (0x00000001U) + +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SEQ_PROG_SIZE 8U +#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 orNumber; + + NvU32 puPcAlt; + NvU32 pdPc; + NvU32 pdPcAlt; + NvU32 normalStart; + NvU32 safeStart; + NvU32 normalState; + NvU32 safeState; + NvU32 flags; + NvU32 seqProgram[NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SEQ_PROG_SIZE]; +} NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PARAMS; + +/* + * NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL + * + * This command does the following in that order + * (a) Loads a specified sequencer program for power up and down. + * (b) Updates PIOR sequencer's power up and down PCs, tells seq to SKIP + * current wait for vsync and waits until sequencer actually SKIPs or halts + * (see more below under SKIP_WAIT_FOR_VSYNC flag) and + * (c) Update power settings (safe/normal start and state). + * + * orNumber + * The OR number for which the seq ctrls are to be modified. + * + * puPcAlt + * Alternate power up PC. + * + * pdPc + * Power down PC. + * + * pdPcAlt + * Alternate power down PC. + * + * normalStart + * Whether normal mode should use normal or alt PC + * + * safeStart + * Whether safe mode should use normal or alt PC + * + * normalState + * Whether normal state should be PD or PU. + * + * safeState + * Whether safe state should be PD or PU. + * + * flags + * The following flags have been defined + * 1. SKIP_WAIT_FOR_VSYNC: Should seq be forced to skip waiting + * for vsync if it's currently waiting on such an instruction. + * If the current instruction doesn't have a wait for vsync, + * SKIP will be applied to the next one and so on until + * either sequencer halts or an instruction with a wait for + * vsync is found. The call will block until seq halts or + * SKIPs a wait for vsync. + * 2. SEQ_PROG_PRESENT: Whether or not a new seq program has + * been specified. + * + * seqProgram + * The sequencer program consisting of power up and down sequences. + * For NV50, this consists of 8 DWORDS. The program is + * relevant only when SEQ_PROG_PRESENT flags is set to _YES. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL (0x50700304U) /* finn: Evaluated from "(FINN_NV50_DISPLAY_SEQ_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PU_PC_ALT_VALUE 3:0 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PU_PC_ALT_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PU_PC_ALT_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PU_PC_ALT_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_VALUE 3:0 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_ALT_VALUE 3:0 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_ALT_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_ALT_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_ALT_SPECIFIED_YES (0x00000001U) + + +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_START_VAL 0:0 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_START_VAL_NORMAL (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_START_VAL_ALT (0x00000001U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_START_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_START_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_START_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_START_VAL 0:0 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_START_VAL_NORMAL (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_START_VAL_ALT (0x00000001U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_START_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_START_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_START_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_STATE_VAL 0:0 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_STATE_VAL_PD (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_STATE_VAL_PU (0x00000001U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_STATE_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_STATE_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_STATE_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_STATE_VAL 0:0 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_STATE_VAL_PD (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_STATE_VAL_PU (0x00000001U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_STATE_SPECIFIED 31:31 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_STATE_SPECIFIED_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_STATE_SPECIFIED_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_FLAGS_SKIP_WAIT_FOR_VSYNC 0:0 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_FLAGS_SKIP_WAIT_FOR_VSYNC_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_FLAGS_SKIP_WAIT_FOR_VSYNC_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_FLAGS_SEQ_PROG_PRESENT 1:1 +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_FLAGS_SEQ_PROG_PRESENT_NO (0x00000000U) +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_FLAGS_SEQ_PROG_PRESENT_YES (0x00000001U) + +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SEQ_PROG_SIZE 8U +#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + NvU32 orNumber; + + NvU32 puPcAlt; + NvU32 pdPc; + NvU32 pdPcAlt; + NvU32 normalStart; + NvU32 safeStart; + NvU32 normalState; + NvU32 safeState; + NvU32 flags; + NvU32 seqProgram[NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SEQ_PROG_SIZE]; +} NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PARAMS; + +/* + * NV5070_CTRL_CMD_CTRL_SEQ_PROG_SPEED + * + * This call allows a fast sequencer program to be selected. It's intended for + * situations where panel sequencing is not required and the usual sequencing + * delays cost too much time. + * + * displayId + * The corresponding display ID. (Note that this call is currently only + * supported for LVDS on an internal encoder, i.e. a SOR.) + * cmd + * The command to perform. Valid values are: + * NV5070_CTRL_SEQ_PROG_SPEED_CMD_GET + * Get the current state. + * NV5070_CTRL_SEQ_PROG_SPEED_CMD_SET + * Set the current state. + * state + * The state of panel sequencing for this displayId. This is an input + * when cmd = SET and an output when cmd = GET. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_NOT_SUPPORTED + * + */ + +#define NV5070_CTRL_CMD_CTRL_SEQ_PROG_SPEED (0x50700305U) /* finn: Evaluated from "(FINN_NV50_DISPLAY_SEQ_INTERFACE_ID << 8) | NV5070_CTRL_SEQ_PROG_SPEED_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_SEQ_PROG_SPEED_CMD_GET (0x00000000U) +#define NV5070_CTRL_SEQ_PROG_SPEED_CMD_SET (0x00000001U) + +#define NV5070_CTRL_SEQ_PROG_SPEED_STATE_NORMAL (0x00000000U) +#define NV5070_CTRL_SEQ_PROG_SPEED_STATE_FAST (0x00000001U) + +#define NV5070_CTRL_SEQ_PROG_SPEED_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV5070_CTRL_SEQ_PROG_SPEED_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + + NvU32 displayId; + + NvU32 cmd; + NvU32 state; +} NV5070_CTRL_SEQ_PROG_SPEED_PARAMS; + +/* _ctrl5070seq_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070system.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070system.h new file mode 100644 index 0000000..bbb07e6 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070system.h @@ -0,0 +1,81 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070system.finn +// + +#include "ctrl/ctrl5070/ctrl5070base.h" +#include "ctrl/ctrl5070/ctrl5070common.h" // NV5070_CTRL_CMD_MAX_HEADS + +/* extract cap bit setting from tbl */ +#define NV5070_CTRL_SYSTEM_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) + +/* caps format is byte_index:bit_mask */ +#define NV5070_CTRL_SYSTEM_CAPS_BUG_237734_REQUIRES_DMI_WAR 0:0x01 // Deprecated +#define NV5070_CTRL_SYSTEM_CAPS_STEREO_DIN_AVAILABLE 0:0x02 +#define NV5070_CTRL_SYSTEM_CAPS_BUG_381003_MULTIWAY_AFR_WAR 0:0x04 +#define NV5070_CTRL_SYSTEM_CAPS_BUG_538079_COLOR_COMPRESSION_SUPPORTED 0:0x08 // Deprecated +#define NV5070_CTRL_SYSTEM_CAPS_BUG_2052012_GLITCHY_MCLK_SWITCH 0:0x10 +#define NV5070_CTRL_SYSTEM_CAPS_DEEP_COLOR_SUPPORT 0:0x20 +#define NV5070_CTRL_SYSTEM_CAPS_BUG_644815_DNISO_VIDMEM_ONLY 0:0x40 + + +/* size in bytes of display caps table */ +#define NV5070_CTRL_SYSTEM_CAPS_TBL_SIZE 1 + +/* + * NV5070_CTRL_CMD_SYSTEM_GET_CAPS_V2 + * + * This command returns the set of display capabilities for the parent device + * in the form of an array of unsigned bytes. Display capabilities + * include supported features and required workarounds for the display + * engine(s) within the device, each represented by a byte offset into the + * table and a bit position within that byte. The set of display capabilities + * will be normalized across all GPUs within the device (a feature capability + * will be set only if it's supported on all GPUs while a required workaround + * capability will be set if any of the GPUs require it). + * + * [out] capsTbl + * This caps table array is where the display cap bits will be transferred + * by the RM. The caps table is an array of unsigned bytes. + * + * Possible status values returned are: + * NV_OK + */ +#define NV5070_CTRL_CMD_SYSTEM_GET_CAPS_V2 (0x50700709) /* finn: Evaluated from "(FINN_NV50_DISPLAY_SYSTEM_INTERFACE_ID << 8) | NV5070_CTRL_SYSTEM_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV5070_CTRL_SYSTEM_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV5070_CTRL_SYSTEM_GET_CAPS_V2_PARAMS { + NV5070_CTRL_CMD_BASE_PARAMS base; + + NvU8 capsTbl[NV5070_CTRL_SYSTEM_CAPS_TBL_SIZE]; +} NV5070_CTRL_SYSTEM_GET_CAPS_V2_PARAMS; + +/* _ctrl5070system_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070verif.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070verif.h new file mode 100644 index 0000000..6741891 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5070/ctrl5070verif.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5070/ctrl5070verif.finn +// + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5080.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5080.h new file mode 100644 index 0000000..777bdab --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl5080.h @@ -0,0 +1,212 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl5080.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl0080/ctrl0080dma.h" /* NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS */ +#include "ctrl/ctrl2080/ctrl2080dma.h" /* NV2080_CTRL_DMA_* */ +#include "ctrl/ctrl2080/ctrl2080fb.h" /* NV2080_CTRL_FB_* */ +#include "ctrl/ctrl2080/ctrl2080fifo.h" /* NV2080_CTRL_FIFO_* */ +#include "ctrl/ctrl2080/ctrl2080gpu.h" /* NV2080_CTRL_GPU_* */ +#include "ctrl/ctrl2080/ctrl2080gr.h" /* NV2080_CTRL_GR_* */ +/* NV5080_DEFERRED_API - deferred RmControl commands */ + + +#define NV5080_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x5080, NV5080_CTRL_##cat,idx) + +/* Command categories (6bits) */ +#define NV5080_CTRL_RESERVED (0x00) +#define NV5080_CTRL_DEFERRED (0x01) + +/* + * NV5080_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV5080_CTRL_CMD_NULL (0x50800000) /* finn: Evaluated from "(FINN_NV50_DEFERRED_API_CLASS_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + + +/* + * NV5080_CTRL_CMD_DEFERRED_API (deprecated; use NV5080_CTRL_CMD_DEFERRED_API_V2 instead) + * + * This command sets up a deferred api call. + * hApiHandle + * Client Unique Handle which is used as the data of a sw method to invoke + * the api in the future + * cmd + * The rmcontrol cmd to invoke as a deferred api. + * flags_delete + * Indicates if an explicit delete is needed (default behavior is to + * auto delete after SW method has executed/completed). + * flags_wait_for_tlb_flush + * Indicates if the API should wait for an InvalidateTlb to also occur + * (not just that it's executed) before being considered completed and + * works in conjunction with flags_delete. + * hClientVA, hDeviceVA + * Client/Device handles of the owner of the virtual address space to + * to be updated (used with the FillPteMem API bundle) + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV5080_CTRL_CMD_DEFERRED_API (0x50800101) /* finn: Evaluated from "(FINN_NV50_DEFERRED_API_CLASS_DEFERRED_INTERFACE_ID << 8) | NV5080_CTRL_DEFERRED_API_PARAMS_MESSAGE_ID" */ + +#define NV5080_CTRL_DEFERRED_API_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV5080_CTRL_DEFERRED_API_PARAMS { + NvHandle hApiHandle; + NvU32 cmd; + NvU32 flags; + NvHandle hClientVA; + NvHandle hDeviceVA; + + union { + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS InitCtx, 8); + + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS PromoteCtx, 8); + + NV2080_CTRL_GPU_EVICT_CTX_PARAMS EvictCtx; + + NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS InvalidateTlb; + + NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS FillPteMem, 8); + + NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS CacheAllocPolicy; + + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS ZcullCtxsw, 8); + + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS PmCtxsw, 8); + + NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS CachePromotePolicy; + + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS PreemptionCtxsw, 8); + } api_bundle; +} NV5080_CTRL_DEFERRED_API_PARAMS; + +#define NV5080_CTRL_CMD_DEFERRED_API_FLAGS_DELETE 0:0 +#define NV5080_CTRL_CMD_DEFERRED_API_FLAGS_DELETE_EXPLICIT (0x00000001) +#define NV5080_CTRL_CMD_DEFERRED_API_FLAGS_DELETE_IMPLICIT (0x00000000) + +#define NV5080_CTRL_CMD_DEFERRED_API_FLAGS_WAIT_FOR_TLB_FLUSH 1:1 +#define NV5080_CTRL_CMD_DEFERRED_API_FLAGS_WAIT_FOR_TLB_FLUSH_FALSE (0x00000000) +#define NV5080_CTRL_CMD_DEFERRED_API_FLAGS_WAIT_FOR_TLB_FLUSH_TRUE (0x00000001) +/* + * NV5080_CTRL_CMD_DEFERRED_API_V2 + * + * This command sets up a deferred api call. + * hApiHandle + * Client Unique Handle which is used as the data of a sw method to invoke + * the api in the future + * cmd + * The rmcontrol cmd to invoke as a deferred api. + * flags_delete + * Indicates if an explicit delete is needed (default behavior is to + * auto delete after SW method has executed/completed). + * flags_wait_for_tlb_flush + * Indicates if the API should wait for an InvalidateTlb to also occur + * (not just that it's executed) before being considered completed and + * works in conjunction with flags_delete. + * hClientVA, hDeviceVA + * Client/Device handles of the owner of the virtual address space to + * to be updated (used with the FillPteMem API bundle) + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV5080_CTRL_CMD_DEFERRED_API_V2 (0x50800103) /* finn: Evaluated from "(FINN_NV50_DEFERRED_API_CLASS_DEFERRED_INTERFACE_ID << 8) | NV5080_CTRL_DEFERRED_API_V2_PARAMS_MESSAGE_ID" */ + +#define NV5080_CTRL_DEFERRED_API_V2_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV5080_CTRL_DEFERRED_API_V2_PARAMS { + NvHandle hApiHandle; + NvU32 cmd; + NvU32 flags; + NvHandle hClientVA; + NvHandle hDeviceVA; + + union { + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS InitCtx, 8); + + NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS PromoteCtx, 8); + + NV2080_CTRL_GPU_EVICT_CTX_PARAMS EvictCtx; + + NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS InvalidateTlb; + + NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS FillPteMem, 8); + + NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS CacheAllocPolicy; + + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS ZcullCtxsw, 8); + + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS PmCtxsw, 8); + + NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS CachePromotePolicy; + + NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS DisableChannels, 8); + + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS PreemptionCtxsw, 8); + + NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS ChannelInfoUpdate, 8); + } api_bundle; +} NV5080_CTRL_DEFERRED_API_V2_PARAMS; + +/* + * NV5080_CTRL_CMD_REMOVE_API + * + * This command removes an explicit deferred api call. + * hApiHandle + * Client Unique Handle which is used as the data of a sw method to invoke + * the api in the future + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV5080_CTRL_CMD_REMOVE_API (0x50800102) /* finn: Evaluated from "(FINN_NV50_DEFERRED_API_CLASS_DEFERRED_INTERFACE_ID << 8) | NV5080_CTRL_REMOVE_API_PARAMS_MESSAGE_ID" */ + +#define NV5080_CTRL_REMOVE_API_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV5080_CTRL_REMOVE_API_PARAMS { + NvHandle hApiHandle; +} NV5080_CTRL_REMOVE_API_PARAMS; + +/* _ctrl5080_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl83de.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl83de.h new file mode 100644 index 0000000..12d792a --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl83de.h @@ -0,0 +1,36 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl83de.finn +// + + + + +#include "ctrl/ctrlxxxx.h" +#include "ctrl83de/ctrl83dedebug.h" + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl83de/ctrl83debase.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl83de/ctrl83debase.h new file mode 100644 index 0000000..6ab74be --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl83de/ctrl83debase.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl83de/ctrl83debase.finn +// + +#include "ctrl/ctrlxxxx.h" +/* GT200_DEBUG control commands and parameters */ + +#define NV83DE_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x83DEU, NV83DE_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NV83DE_CTRL_RESERVED (0x00) +#define NV83DE_CTRL_GR (0x01) +#define NV83DE_CTRL_FIFO (0x02) +#define NV83DE_CTRL_DEBUG (0x03) +#define NV83DE_CTRL_INTERNAL (0x04) + + +/* + * NV83DE_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV83DE_CTRL_CMD_NULL (0x83de0000) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrl83debase_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h new file mode 100644 index 0000000..c4c36b0 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h @@ -0,0 +1,1106 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl83de/ctrl83dedebug.finn +// + +#include "ctrl/ctrl83de/ctrl83debase.h" +#include "nvstatus.h" + +#include "ctrl/ctrl2080/ctrl2080gpu.h" + + + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG + * + * This command sets the MMU DEBUG mode. This is Fermi-onwards feature. + * If the query is made on an incorrect platform (for example, pre-Fermi) + * the call will return with an NV_ERR_NOT_SUPPORTED error. + * + * action + * The possible action values are: + * - NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_ENABLE + * This enables the MMU debug mode if possible. If however, any another + * client has already disabled the mode (via NV83DE call) then this + * operation returns NV_ERR_STATE_IN_USE. + * + * - NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_DISABLE + * This disables the MMU debug mode if possible. If however, any another + * client has already enabled the mode (via NV83DE call) then this + * operation returns NV_ERR_STATE_IN_USE. + * + * - NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_DEBUG_REQUESTS + * This operation releases all the client's outstanding requests to enable + * or disable the MMU debug mode. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG (0x83de0307) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS { + NvU32 action; +} NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS; + +#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_ENABLE (0x00000001) +#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_DISABLE (0x00000002) +#define NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_DEBUG_REQUESTS (0x00000003) + +/* + * NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG + * + * This command gets the value of currently configured MMU DEBUG mode. + * This is Fermi-onwards feature. If the query is made on an incorrect + * platform (for example, pre-Fermi) the call will return with an + * NV_ERR_NOT_SUPPORTED error. + * + * value + * This parameter returns the configured value. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG (0x83de0308) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS { + NvU32 value; +} NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS; + +#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG_ENABLED (0x00000001) +#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG_DISABLED (0x00000002) + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_EXCEPTION_MASK + * + * This command allows the caller to filter events (which are also referred to + * as "notifications", not to be confused with true notifiers), in the RM, + * fairly close to the source of the events. In other words, depending on the + * value of the exceptionMask, some events may not be raised. + * + * The original reason for creating this command is that the CUDA driver needs + * to place the RM and the GPU(s) into SM debug mode, for some GPUs, in order to + * activate various features and HW bug WARs. Being in SM debug mode has the + * side effect of exposing the caller to debug events, which are generally + * undesirable for the CUDA driver, but desirable for the CUDA debugger. This + * command allows each client to receive only the events that it is + * specifically interested in. + * + * If this command is never invoked, then the RM will behave as if + * exceptionMask==NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_ALL. + * + * As with many of the debugger features, this is Fermi-onwards feature. If this + * API call is issued on an earlier platform, it will return an + * NV_ERR_NOT_SUPPORTED error. + * + * exceptionMask + * This identifies the category of notifications that the debug client + * is interested in. + * + * Here are the allowed values for exceptionMask: + * + * - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_FATAL + * This means that the caller wishes to receive events for any exceptions + * that are classified as fatal. For example, + * HWW_WARP_ESR_ERROR_PC_OVERFLOW is one such exception. + * + * If any debug object, in any channel, has registered to receive events + * for _FATAL exceptions, then RC recovery will be deferred if such an + * exception occurs. + * + * Also, if a client is registered for fatal exceptions, RC error recovery + * will be deferred. If not registered for fatal exceptions, then fatal + * errors will (as usual) cause RC recovery to run immediately. + * + * - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_TRAP + * This means that an event will be raised when an SM executes a bpt.pause + * instruction. Note that on Fermi, the SM raises HWW when bpt.trap is + * executed as well, so this event will also be raised in that situation. + * + * - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_SINGLE_STEP + * This means that an event will be raised a single step completion + * interrupt is received. + * + * - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_INT + * This means that an event will be raised when an SM executes a bpt.int + * instruction. + * + * - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_NONE + * This means that no debug events will be raised. + * + * - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_ALL + * This means that an event will be raised for any and all debug + * exceptions. This is the default behavior. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_EXCEPTION_MASK (0x83de0309) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS { + NvU32 exceptionMask; +} NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS; + +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_FATAL (0x00000001) +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_TRAP (0x00000002) +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_SINGLE_STEP (0x00000004) +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_INT (0x00000008) +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_CILP (0x00000010) +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PREEMPTION_STARTED (0x00000020) +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_NONE (0x00000000) +#define NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_ALL (0x0000FFFF) + + + +/* + * NV83DE_CTRL_CMD_READ_SINGLE_SM_ERROR_STATE + * + * This command reads the SM error state of a single SM. The error state + * consists of several 32-bit values. + * + * Note that this acts upon the currently resident GR (graphics) context. It is + * up to the RM client to ensure that the desired GR context is resident, before + * making this API call. + * + * See also: NV83DE_CTRL_CMD_READ_ALL_SM_ERROR_STATES. + * + * This is a Fermi-and-later feature. If this API call is issued on an earlier + * platform, it will return an NV_ERR_NOT_SUPPORTED error. + * + * Parameters: + * + * hTargetChannel (input) + * This identifies the channel. + * + * smID (input) + * This identifies the SM. Allowed values are any valid SM ID. The RM + * grProgramSmIdNumbering_HAL() routines are a good place to look, in order + * to see how SM IDs are set up. The main idea is that the RM chooses a + * numbering scheme, and then informs the GPU hardware of that scheme, by + * actually recording each SM ID into the GPU, via a series of PRI (GPU + * register) writes. + * + * smErrorState.hwwGlobalEsr (output) + * Value of the Global Error Status Register. + * + * smErrorState.hwwWarpEsr (output) + * Value of the Warp Error Status Register. + * + * smErrorState.hwwWarpEsrPc (output) : DEPRECATED for 64b PC below, will hold low 32b for now + * Value of the Warp Error Status Register Program Counter. + * + * smErrorState.hwwGlobalEsrReportMask (output) + * Value of the Global Error Status Register Report Mask. + * + * smErrorState.hwwWarpEsrReportMask (output) + * Value of the Error Status Register Report Mask. + * + * smErrorState.hwwWarpEsrPc64 (output) + * Value of the 64b Warp Error Status Register Program Counter. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_READ_SINGLE_SM_ERROR_STATE (0x83de030b) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID" */ + +typedef struct NV83DE_SM_ERROR_STATE_REGISTERS { + NvU32 hwwGlobalEsr; + NvU32 hwwWarpEsr; + NvU32 hwwWarpEsrPc; + NvU32 hwwGlobalEsrReportMask; + NvU32 hwwWarpEsrReportMask; + NV_DECLARE_ALIGNED(NvU64 hwwEsrAddr, 8); + NV_DECLARE_ALIGNED(NvU64 hwwWarpEsrPc64, 8); + NvU32 hwwCgaEsr; + NvU32 hwwCgaEsrReportMask; +} NV83DE_SM_ERROR_STATE_REGISTERS; + +#define NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS { + NvHandle hTargetChannel; + NvU32 smID; + NV_DECLARE_ALIGNED(NV83DE_SM_ERROR_STATE_REGISTERS smErrorState, 8); +} NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS; + +/* + * NV83DE_CTRL_CMD_READ_ALL_SM_ERROR_STATES + * + * This command reads the SM error state of all SMs. + * + * Note that this acts upon the currently resident GR (graphics) context. It is + * up to the RM client to ensure that the desired GR context is resident, before + * making this API call. + * + * Parameters: + * + * hTargetChannel (input) + * This identifies the channel. + * + * numSMsToRead (input) + * This should be set to the number of SMs that the RM is supposed to read. + * It will typically be the total number of SMs in the GPU. For best + * results, you should not pass in a value that is greater than the number + * of SMs that the GPU actually contains. + * + * startingSM (input) + * This should be set to the starting index of the first SM to read. + * Clients may use this to read data from SMs beyond the maximum specified + * in NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL. + * + * smErrorStateArray (output) + * This is an array of NV83DE_SM_ERROR_STATE_REGISTERS structs. Please see + * the description of NV83DE_CTRL_CMD_READ_SINGLE_SM_ERROR_STATE, above, for + * a description of the individual fields. + * + * mmuFault.valid (output) + * This is NV_TRUE if an MMU fault occurred on the target channel since the last call to + * NV83DE_CTRL_CMD_CLEAR_ALL_SM_ERROR_STATES to this channel. + * + * mmuFault.faultInfo (output) + * This is the value of the first NV_PFIFO_INTR_MMU_FAULT_INFO that caused the MMU fault. + * + * mmuFaultInfo (output) + * Deprecated field, see mmuFault.faultInfo + * + * This is a Fermi-and-later feature. If this API call is issued on an earlier + * platform, it will return an NV_ERR_NOT_SUPPORTED error. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_READ_ALL_SM_ERROR_STATES (0x83de030c) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL 100 + +typedef struct NV83DE_MMU_FAULT_INFO { + NvBool valid; + NvU32 faultInfo; +} NV83DE_MMU_FAULT_INFO; + +#define NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS { + NvHandle hTargetChannel; + NvU32 numSMsToRead; + NV_DECLARE_ALIGNED(NV83DE_SM_ERROR_STATE_REGISTERS smErrorStateArray[NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL], 8); + NvU32 mmuFaultInfo; // Deprecated, use mmuFault field instead + NV83DE_MMU_FAULT_INFO mmuFault; + NvU32 startingSM; +} NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS; + +/* + * NV83DE_CTRL_CMD_CLEAR_SINGLE_SM_ERROR_STATE + * + * This command clears the SM error state of a single SM. The error state + * consists of several 32-bit values. + * + * Note that this acts upon the currently resident GR (graphics) context. It is + * up to the RM client to ensure that the desired GR context is resident, before + * making this API call. + * + * See also: NV83DE_CTRL_CMD_CLEAR_ALL_SM_ERROR_STATES. + * + * This API call has a slightly different effect than what would occur as a + * result of issuing a read-modify-write via _READ_SINGLE_SM_ERROR_STATE and + * _WRITE_SINGLE_SM_ERROR_STATE. The difference arises due to the fact that RM + * is caching the error state, to compensate for the fact that the real GPU + * error state must be cleared very early on in the exception handling routine. + * + * In other words, the _READ data is stale by design, and cannot be used in a + * read-modify-write routine from user space. Therefore, in order to clear the + * SM error state, a separate RM API call is required. + * + * This is a Fermi-and-later feature. If this API call is issued on an earlier + * platform, it will return an NV_ERR_NOT_SUPPORTED error. + * + * Parameters: + * + * hTargetChannel (input) + * This identifies the channel. + * + * smID (input) + * This identifies the SM. Allowed values are any valid SM ID. Please see + * NV83DE_CTRL_CMD_READ_SINGLE_SM_ERROR_STATE for further details. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE (0x83de030f) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS { + NvHandle hTargetChannel; + NvU32 smID; +} NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS; + +/* + * NV83DE_CTRL_CMD_CLEAR_ALL_SM_ERROR_STATES + * + * This command clears the SM error state of all SMs. + * + * Note that this acts upon the currently resident GR (graphics) context. It is + * up to the RM client to ensure that the desired GR context is resident, before + * making this API call. + * + * Parameters: + * + * hTargetChannel (input) + * This identifies the channel. + * + * numSMsToClear (input) + * This should be set to the number of SMs that the RM is supposed to write. + * It will typically be the total number of SMs in the GPU. For best + * results, you should not pass in a value that is greater than the number + * of SMs that the GPU actually contains. + * + * Please see the description of + * NV83DE_CTRL_CMD_CLEAR_SINGLE_SM_ERROR_STATE, above, for a description of + * why these two _CLEAR API calls are required. + * + * This is a Fermi-and-later feature. If this API call is issued on an earlier + * platform, it will return an NV_ERR_NOT_SUPPORTED error. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_CLEAR_ALL_SM_ERROR_STATES (0x83de0310) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS { + NvHandle hTargetChannel; + NvU32 numSMsToClear; +} NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS; + + + +#define NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS_DEFINED 1 +#define NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_HAS_RESIDENT_CHANNEL 1 +typedef struct NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS { + NvU32 waitForEvent; + NvHandle hResidentChannel; +} NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS; + + + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE + * + * This command set the type of action we want on RM encountering an error + * and issuing a STOP_TRIGGER. The action will be to either braodcast the + * STOP_TRIGGER to all SM's, or just send to the SM hitting an exception. + * + * stopTriggerType + * This identifies trigger type to initiate. + * + * Here are the allowed values for stopTriggerType: + * + * - NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_SINGLE_SM + * This means that we will issue STOP_TRIGGER to the single SM + * noted in the exception + * + * - NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_BROADCAST + * This means that we will issue STOP_TRIGGER to all SM's + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE (0x83de0313) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS { + NvU32 stopTriggerType; +} NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS; + +#define NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_SINGLE_SM (0x00000001) +#define NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_BROADCSAT (0x00000002) + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING + * + * This command sets the type of action we want on RM encountering a + * SINGLE_STEP exception while in CILP debug mode. In the normal case, + * non-pausing, we ignore these exceptions as on prior chips. When the + * user selects pausing, it will cause the exception to be treated just + * like we had seen an SM error or BPT_PAUSE. + * + * singleStepHandling + * This identifies single step handling type to use. + * + * Here are the allowed values for singleStepHandling: + * + * - NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_NONPAUSING + * Treat SINGLE_STEP exceptions while in debug mode as non-pausing, + * which is the default/normal mode in the interrupt pre-process + * function, where they are ignored. + * + * - NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PAUSING + * Treat SINGLE_STEP exceptions while in debug mode as pausing, + * which means in the interrupt pre-process function they will + * be treated like BPT_PAUSE and SM error exceptions + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING (0x83de0314) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS { + NvU32 singleStepHandling; +} NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS; + +#define NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_NONPAUSING (0x00000001) +#define NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PAUSING (0x00000002) + +/* + * NV83DE_CTRL_CMD_DEBUG_READ_MEMORY + * + * This command reads a block of memory. + * This command is deprecated in favor of NV83DE_CTRL_CMD_DEBUG_READ_BATCH_MEMORY + * + * hMemory [IN] + * The handle to the memory being accessed. If hMemory is not accessible + * from the caller's address space, NV_ERR_INSUFFICIENT_PERMISSIONS + * is returned. + * + * length [IN/OUT] + * Number of bytes to read, as well as the number of bytes actually read + * returned. + * + * offset [IN] + * The offset into the physical memory region given by the handle above. + * + * buffer [OUT] + * The data read is returned in this buffer. + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ACCESS_TYPE + * NV_ERR_INSUFFICIENT_PERMISSIONS + * + */ +#define NV83DE_CTRL_CMD_DEBUG_READ_MEMORY (0x83de0315) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS { + NvU32 hMemory; + NvU32 length; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvP64 buffer, 8); +} NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_WRITE_MEMORY + * + * This command writes a block of memory. + * This command is deprecated in favor of NV83DE_CTRL_CMD_DEBUG_WRITE_BATCH_MEMORY + * + * hMemory [IN] + * The handle to the memory being accessed. If hMemory is not accessible + * from the caller's address space, NV_ERR_INSUFFICIENT_PERMISSIONS + * is returned. + * + * length [IN/OUT] + * Number of bytes to write, as well as the number of bytes actually + * written. + * + * offset [IN] + * The offset into the physical memory region given by the handle above. + * + * buffer [IN] + * The data to be written is sent in this buffer. + * + * Possible status values returned are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ACCESS_TYPE + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +#define NV83DE_CTRL_CMD_DEBUG_WRITE_MEMORY (0x83de0316) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS { + NvU32 hMemory; + NvU32 length; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvP64 buffer, 8); +} NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT + * + * This command suspends a SM context associated with the debugger object. + * + * When the suspend call returns, context associated with the debugger object + * should not be actively executing any code on any SM. The channel will have + * been disabled if not resident on GR, or have its SM suspended if it was resident. + * + * This is a Fermi-and-later feature. If this API call is issued on an earlier + * platform, it will return an NV_ERR_NOT_SUPPORTED error. + * + * waitForEvent + * This return param indicates if the call had to issue a Preempt, + * therefore it is in process and user may need to wait for it. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_STATE + */ +#define NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT (0x83de0317) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_MESSAGE_ID (0x17U) + +typedef NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_RESUME_CONTEXT + * + * This command safely resumes the SM context associated with the debugger object. + * + * This is a Fermi-and-later feature. If this API call is issued on an earlier + * platform, it will return an NV_ERR_NOT_SUPPORTED error. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_STATE + */ +#define NV83DE_CTRL_CMD_DEBUG_RESUME_CONTEXT (0x83de0318) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x18" */ + +/* + * NV83DE_CTRL_CMD_DEBUG_GET_HANDLES + * + * This command returns relevant handles for the debug object + * This command is only available on debug and develop builds. + * + * Possible return values: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_CLIENT + * NV_ERR_INVALID_OBJECT_HANDLE + * + */ +#define NV83DE_CTRL_CMD_DEBUG_GET_HANDLES (0x83de0319) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x19" */ + +typedef struct NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS { + NvHandle hChannel; + NvHandle hSubdevice; +} NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS; + +/* + * NV83DE_CTRL_CMD_READ_SURFACE + * + * This command allows the caller to copy the data from a specified gpuVA + * to a usermode buffer. Before copying, this command validates whether or + * not the virtual address (VA) range provided as input has valid and allocated + * pages mapped to it in its entirety. + * + * This command's input is NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS which + * contains a buffer of NV83DE_CTRL_DEBUG_ACCESS_OPs + * + * Possible return values: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_XLATE + */ +#define NV83DE_CTRL_CMD_READ_SURFACE (0x83de031a) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x1A" */ + +/* + * NV83DE_CTRL_CMD_WRITE_SURFACE + * + * This command allows the caller to copy the data from a provided usermode + * buffer to a specified GPU VA. Before copying, this command validates whether or + * not the virtual address (VA) range provided as input has valid and allocated + * pages mapped to it in its entirety. + * + * This command's input is NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS which + * contains a buffer of NV83DE_CTRL_DEBUG_ACCESS_OPs + * + * Possible return values: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_XLATE + */ +#define NV83DE_CTRL_CMD_WRITE_SURFACE (0x83de031b) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x1B" */ + +#define MAX_ACCESS_OPS 64 + +typedef struct NV83DE_CTRL_DEBUG_ACCESS_OP { + NV_DECLARE_ALIGNED(NvU64 gpuVA, 8); // IN + NV_DECLARE_ALIGNED(NvP64 pCpuVA, 8); // IN/OUT Debugger CPU Pointer of buffer + NvU32 size; // IN Size in bytes + NvU32 valid; // OUT Whether the GpuVA is accessible +} NV83DE_CTRL_DEBUG_ACCESS_OP; + +typedef struct NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS { + NvU32 count; // IN Number of ops in this call + NV_DECLARE_ALIGNED(NV83DE_CTRL_DEBUG_ACCESS_OP opsBuffer[MAX_ACCESS_OPS], 8); +} NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS; + +/* + * NV83DE_CTRL_CMD_GET_MAPPINGS + * + * This command traverses through the virtual memory page hierarchy and + * fetches the valid virtual mappings and their sizes for a provided virtual + * address (VA) range. + * If a given VA range has more than MAX_GET_MAPPINGS_OPS valid mappings, + * hasMore is set to 1, and opsBuffer is still filled with MAX_GET_MAPPINGS_OPS + * valid mappings. In this case, this command should be called again with + * vaLo = opsBuffer[MAX_GET_MAPPINGS_OPS - 1].gpuVA + + * opsBuffer[MAX_GET_MAPPINGS_OPS - 1].size; + * and vaHi set to the next desired upper limit. + * + * This command's input is NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS which + * contains a buffer of NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP + * + * Possible return values: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_XLATE + */ +#define NV83DE_CTRL_CMD_GET_MAPPINGS (0x83de031c) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x1C" */ + +#define MAX_GET_MAPPINGS_OPS 64 + +typedef struct NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP { + NV_DECLARE_ALIGNED(NvU64 gpuVA, 8); // OUT Start of GPU VA for this mapping + NvU32 size; // OUT Size in bytes of this mapping +} NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP; + +typedef struct NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS { + NV_DECLARE_ALIGNED(NvU64 vaLo, 8); // IN Lower VA range, inclusive + NV_DECLARE_ALIGNED(NvU64 vaHi, 8); // IN Upper VA range, inclusive + NvU32 count; // OUT Number of ops in this call + NvU32 hasMore; // OUT Whether there are more valid mappings in this range than MAX_GET_MAPPINGS_OPS + NV_DECLARE_ALIGNED(NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP opsBuffer[MAX_GET_MAPPINGS_OPS], 8); +} NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS; + +/* + * NV83DE_CTRL_CMD_DEBUG_EXEC_REG_OPS + * + * This command is used to submit a buffer containing one or more + * NV2080_CTRL_GPU_REG_OP structures for processing. Each entry in the + * buffer specifies a single read or write operation. Each entry is checked + * for validity in an initial pass over the buffer with the results for + * each operation stored in the corresponding regStatus field. Unless + * bNonTransactional flag is set to true, if any invalid entries are found + * during this initial pass then none of the operations are executed. Entries + * are processed in order within each regType with NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL + * entries processed first followed by NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX entries. + * + * [IN] bNonTransactional + * This field specifies if command is non-transactional i.e. if set to + * true, all the valid operations will be executed. + * + * [IN] regOpCount + * This field specifies the number of valid entries in the regops list. + * + * [IN/OUT] regOps + * This field is to be filled with the desired register information that is + * to be retrieved. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV83DE_CTRL_CMD_DEBUG_EXEC_REG_OPS (0x83de031d) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_GPU_EXEC_REG_OPS_MAX_OPS 100 +#define NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_MESSAGE_ID (0x1DU) + +typedef struct NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS { + NvBool bNonTransactional; + NvU32 regOpCount; + // C form: NV2080_CTRL_GPU_REG_OP regOps[NV2080_CTRL_GPU_EXEC_REG_OPS_MAX_OPS] + NV2080_CTRL_GPU_REG_OP regOps[NV83DE_CTRL_GPU_EXEC_REG_OPS_MAX_OPS]; +} NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR + * + * This command sets the Errbar Debug mode. This is Volta-onwards feature. + * If the query is made on an incorrect platform (for example, pre-Volta) + * the call will return with an NV_ERR_NOT_SUPPORTED error. + * + * action + * The possible action values are: + * - NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_ENABLE + * This enables the Errbar debug mode. + * + * - NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DISABLE + * This disables the Errbar debug mode. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_WRITE + * NV_ERR_INVALID_ARGUMENT + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG (0x83de031f) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID (0x1FU) + +typedef struct NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS { + NvU32 action; +} NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS; + +#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG_DISABLE (0x00000000) +#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG_ENABLE (0x00000001) + +/* + * NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR + * + * This command gets the value of currently configured Errbar DEBUG mode. + * This is Volta-onwards feature. If the query is made on an incorrect + * platform (for example, pre-Volta) the call will return with an + * NV_ERR_NOT_SUPPORTED error. + * + * value + * This parameter returns the configured value. + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_READ + * NV_ERR_INVALID_ARGUMENT + */ +#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG (0x83de0320) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS { + NvU32 value; +} NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS; + +#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG_DISABLED (0x00000000) +#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG_ENABLED (0x00000001) + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SINGLE_STEP + * + * This command either enables or disables single step mode for the given SM. + * + * smID (input) + * This identifies the SM. + * bSingleStep (input) + * This indicates the single step mode. NV_TRUE for ENABLED. + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SINGLE_STEP (0x83de0321) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_MESSAGE_ID (0x21U) + +typedef struct NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS { + NvU32 smID; + NvBool bSingleStep; +} NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_STOP_TRIGGER + * + * This command sets or clears the stop trigger for the given SM. + * + * smID (input) + * This identifies the SM. + * bStopTrigger (input) + * This indicates whether to set or clear the trigger. NV_TRUE for ENABLED. + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_STOP_TRIGGER (0x83de0322) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_BROADCAST ((NvU32)~0) + +#define NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS { + NvU32 smID; + NvBool bStopTrigger; +} NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_RUN_TRIGGER + * + * This command sets or clears the run trigger for the given SM. + * + * smID (input) + * This identifies the SM. + * bRunTrigger (input) + * This indicates whether to set or clear the trigger. NV_TRUE for ENABLED. + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_RUN_TRIGGER (0x83de0323) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS_MESSAGE_ID (0x23U) + +typedef struct NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS { + NvU32 smID; + NvBool bRunTrigger; +} NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT + * + * This command enables or disables skip idle warp detect for the given sm. + * + * smID (input) + * This identifies the SM. + * bSkipIdleWarpDetect (input) + * This indicates whether to enable or disable the mode. NV_TRUE for ENABLED. + */ +#define NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT (0x83de0324) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS_MESSAGE_ID (0x24U) + +typedef struct NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS { + NvU32 smID; + NvBool bSkipIdleWarpDetect; +} NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS; + +/* + * NV83DE_CTRL_CMD_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS + * + * This command retrieves the debugger status states of the given SM. + * + * smID (input) + * This identifies the SM. + * bInTrapMode (output) + * This indicates whether the SM is in trap mode. + * bCrsFlushDone (output) + * Deprecated GK110+. Always 0 Volta+. + * bRunTriggerInProgress (output) + * Deprecated GM10X+. Always 0 Volta+. + * bComputeContext (output) + * Deprecated GM10X+. Always 0 Volta+. + * bLockedDown (output) + * This indicates whether the SM is locked down. + */ +#define NV83DE_CTRL_CMD_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS (0x83de0325) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS_MESSAGE_ID" */ + +typedef struct NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS { + NvBool bInTrapMode; + NvBool bCrsFlushDone; + NvBool bRunTriggerInProgress; + NvBool bComputeContext; + NvBool bLockedDown; +} NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS; + +#define NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS_MESSAGE_ID (0x25U) + +typedef struct NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS { + NvU32 smID; + NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS smDebuggerStatus; +} NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS; + +/*! + * NV83DE_CTRL_CMD_DEBUG_ACCESS_MEMORY_ENTRY + * + * This struct represents a requet to read/write a block of memory. + * + * hMemory [IN] + * The handle to the memory being accessed. If hMemory is not accessible + * from the caller's address space, NV_ERR_INSUFFICIENT_PERMISSIONS + * is returned. + * + * length [IN] + * Number of bytes to read/write + * + * memOffset [IN] + * The offset into the physical memory region given by the handle above. + * + * dataOffset [IN] + * An offset into the usermode memory region provided by the enclosing + * params indicating where to read/write data from/to. + * + * status [OUT] + * The result status of the operation will be output. If NV_OK, even if + * command returned error status, the given operation was successful. If + * not NV_OK, it is guaranteed that the command will return error status. + */ +typedef struct NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY { + NvHandle hMemory; + NvU32 length; + NV_DECLARE_ALIGNED(NvU64 memOffset, 8); + NvU32 dataOffset; + NV_STATUS status; +} NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY; + +/*! + * NV83DE_CTRL_CMD_DEBUG_READ_BATCH_MEMORY + * + * Execute a batch of read memory operations. + * + * count [IN] + * Number of read/write operations to perform. + * + * dataLength [IN] + * Length of the usermode buffer passed in, in bytes. + * + * pData [OUT] + * Usermode buffer to store the output of the read operations. Each + * operation is expected to provide an offset into this buffer. + * + * entries [IN] + * List of operations to perform. First `count` entries are used. + */ +#define NV83DE_CTRL_CMD_DEBUG_READ_BATCH_MEMORY (0x83de0326) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x26" */ + +/*! + * NV83DE_CTRL_CMD_DEBUG_WRITE_BATCH_MEMORY + * + * Execute a batch of write memory operations. + * + * count [IN] + * Number of read/write operations to perform. + * + * dataLength [IN] + * Length of the usermode buffer passed in, in bytes. + * + * pData [IN] + * Usermode buffer to store the input of the write operations. Each + * operation is expected to provide an offset into this buffer. + * + * entries [IN] + * List of operations to perform. First `count` entries are used. + */ +#define NV83DE_CTRL_CMD_DEBUG_WRITE_BATCH_MEMORY (0x83de0327) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x27" */ + +#define MAX_ACCESS_MEMORY_OPS 150 +typedef struct NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pData, 8); + NvU32 dataLength; + NvU32 count; + NV_DECLARE_ALIGNED(NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY entries[MAX_ACCESS_MEMORY_OPS], 8); +} NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS; + +/* + * NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY + * + * faultAddress (OUT) + * Faulting address + * faultType (OUT) + * Type of MMU fault + * accessType (OUT) + * Type of access that caused this fault + */ +#define NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_MAX_ENTRIES 4 +typedef struct NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY { + NV_DECLARE_ALIGNED(NvU64 faultAddress, 8); + NvU32 faultType; + NvU32 accessType; +} NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY; + +/* + * NV83DE_CTRL_CMD_DEBUG_READ_MMU_FAULT_INFO + * + * mmuFaultInfoList (OUT) + * Entries of MMU faults recorded for the attached context. The cached data is only cleared via LRU policy when new MMU faults arrive so repeat data may be returned by this command. + * count (OUT) + * Number of MMU fault entries contain valid data. + */ +#define NV83DE_CTRL_CMD_DEBUG_READ_MMU_FAULT_INFO (0x83de0328) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x28U) + +typedef struct NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS { + NV_DECLARE_ALIGNED(NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY mmuFaultInfoList[NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_MAX_ENTRIES], 8); + NvU32 count; +} NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS; + +/* _ctrl83dedebug_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9010.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9010.h new file mode 100644 index 0000000..43dada9 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9010.h @@ -0,0 +1,83 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl9010.finn +// + +#include "ctrl/ctrlxxxx.h" +#define NV9010_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0x9010, NV9010_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NV9010_CTRL_RESERVED (0x00) +#define NV9010_CTRL_VBLANK_CALLBACK (0x01) + + +/* + * NV9010_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV9010_CTRL_CMD_NULL (0x90100000) /* finn: Evaluated from "(FINN_NV9010_VBLANK_CALLBACK_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION + * + * This command is used to enable and disable vblank notifications. This + * is specially intended for cases where the RM client is calling from a + * high IRQL context, where other mechanisms to toggle vblank notification + * (such as freeing and reallocating the NV9010_VBLANK_CALLBACK object) + * would not be suitable. As this is being invoked at the high IRQL, + * locking can be bypassed, if the NVOS54_FLAGS_LOCK_BYPASS flag is set on + * the control call.Here the OS will take care of the synchronization. + * The Windows Display Driver for Cobalt requires this, for example. + * + * bSetVBlankNotifyEnable + * This parameter tell whether to enable or disable the Vblank notification + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION (0x90100101) /* finn: Evaluated from "(FINN_NV9010_VBLANK_CALLBACK_INTERFACE_ID << 8) | NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION_PARAMS_MESSAGE_ID (0x01U) + +typedef struct NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION_PARAMS { + NvBool bSetVBlankNotifyEnable; +} NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION_PARAMS; + +/* _ctrl9010_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9067.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9067.h new file mode 100644 index 0000000..62cb948 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9067.h @@ -0,0 +1,150 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl9067.finn +// + +#include "ctrl/ctrlxxxx.h" +/* Subcontext control commands and parameters */ +#define NV9067_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x9067, NV9067_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NV9067_CTRL_RESERVED (0x00) +#define NV9067_CTRL_TPC_PARTITION (0x01) +#define NV9067_CTRL_CWD_WATERMARK (0x02) + +/*! + * Does nothing. + */ +#define NV9067_CTRL_CMD_NULL (0x90670000) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/*! + * NV9067_CTRL_CMD_GET_TPC_PARTITION_TABLE + * This command gets the current partition table configuration of a subcontext + * + * NV9067_CTRL_CMD_SET_TPC_PARTITION_TABLE + * This command sets the partition table of a subcontext + * + * NV9067_CTRL_TPC_PARTITION_TABLE_PARAMS + * This structure defines the parameters used for SET/GET per-subcontext TPC partitioning table configuration + * + * numUsedTpc [in/out] + * Specifies the number of TPCs used by the subcontext + * While querying the enabled TPCs, this is an output paramter + * While configuring the TPCs, this is an input parameter + * + * tpcList [in/out] + * Array containing the TPCs enabled for the subcontext. + * The first numUsedTpc in the array interpreted as the valid entries. + * + * Only applicable for STATIC and DYNAMIC modes. + * + * NV9067_CTRL_TPC_PARTITION_TABLE_MAX_TPC_COUNT + * Max TPC count supported by this ctrl call + * + * NV9067_CTRL_TPC_PARTITION_TABLE_TPC_INFO + * This structure defines the parameters for a TPC + * + * globalTpcIndex + * Global logical index of the enabled TPC + * + * lmemBlockIndex + * Block index of the Local memory backing store for the enabled TPC. + * For GET command, we will return the current lmem block assigment for STATIC & DYNAMIC modes. + * For SET command, this index is relevant only for STATIC mode. + * HW automatically assign it for other modes. So should be zeroed out for other modes. + * + */ +#define NV9067_CTRL_CMD_GET_TPC_PARTITION_TABLE (0x90670101) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_TPC_PARTITION_INTERFACE_ID << 8) | 0x1" */ + +#define NV9067_CTRL_CMD_SET_TPC_PARTITION_TABLE (0x90670102) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_TPC_PARTITION_INTERFACE_ID << 8) | NV9067_CTRL_TPC_PARTITION_TABLE_PARAMS_MESSAGE_ID" */ + +#define NV9067_CTRL_TPC_PARTITION_TABLE_TPC_COUNT_MAX 256 + +typedef struct NV9067_CTRL_TPC_PARTITION_TABLE_TPC_INFO { + NvU16 globalTpcIndex; + NvU16 lmemBlockIndex; +} NV9067_CTRL_TPC_PARTITION_TABLE_TPC_INFO; + +#define NV9067_CTRL_TPC_PARTITION_TABLE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV9067_CTRL_TPC_PARTITION_TABLE_PARAMS { + NvU16 numUsedTpc; + NV9067_CTRL_TPC_PARTITION_TABLE_TPC_INFO tpcList[NV9067_CTRL_TPC_PARTITION_TABLE_TPC_COUNT_MAX]; +} NV9067_CTRL_TPC_PARTITION_TABLE_PARAMS; + + +/*! + * NV9067_CTRL_CMD_GET_CWD_WATERMARK + * This command gets the cached watermark value for a subcontext + * + * NV9067_CTRL_CMD_SET_CWD_WATERMARK + * This command sets the watermark value for a subcontexts + * + * NV9067_CTRL_CWD_WATERMARK_PARAMS + * This structure defines the parameters used to SET/GET watermark value per-subcontext. + * + * watermarkValue [in/out] + * Value of watermark per-subcontext + * Acts as a output parameter to get the current value of watermark for a subcontext. + * Acts as a input parameter to set the current value of watermark for a subcontexts. + * + * NV9067_CTRL_CWD_WATERMARK_VALUE_MIN + * Minimum value of watermark for any subcontext + * RM will throw an error if any value less than this value is specified + * + * NV9067_CTRL_CWD_WATERMARK_VALUE_DEFAULT + * Default value of watermark for any subcontext + * RM will set watermark of a subcontext to this value when the subcontext + * is created/initialized for the first time + * + * NV9067_CTRL_CWD_WATERMARK_VALUE_MAX + * Maximum value of watermark for any subcontext + * RM will throw an error if any value more than this value is specified + * + */ + +#define NV9067_CTRL_CMD_GET_CWD_WATERMARK (0x90670201) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID << 8) | 0x1" */ + +#define NV9067_CTRL_CMD_SET_CWD_WATERMARK (0x90670202) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID << 8) | 0x2" */ + +#define NV9067_CTRL_CWD_WATERMARK_VALUE_MIN 1 +#define NV9067_CTRL_CWD_WATERMARK_VALUE_DEFAULT 2 +#define NV9067_CTRL_CWD_WATERMARK_VALUE_MAX 256 + +typedef struct NV9067_CTRL_CWD_WATERMARK_PARAMS { + NvU32 watermarkValue; +} NV9067_CTRL_CWD_WATERMARK_PARAMS; + + +/* _ctrl9067_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl906f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl906f.h new file mode 100644 index 0000000..8be99d2 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl906f.h @@ -0,0 +1,261 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl906f.finn +// + + + + +/* GF100_GPFIFO control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#define NV906F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0x906F, NV906F_CTRL_##cat, idx) + +/* GF100_GPFIFO command categories (6bits) */ +#define NV906F_CTRL_RESERVED (0x00) +#define NV906F_CTRL_GPFIFO (0x01) +#define NV906F_CTRL_EVENT (0x02) + + +/* + * NV906F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV906F_CTRL_CMD_NULL (0x906f0000) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + + +/* + * NV906F_CTRL_GET_CLASS_ENGINEID + * + * Takes an object handle as input and returns + * the Class and Engine that this object uses. + * + * hObject + * Handle to an object created. For example a + * handle to object of type FERMI_A created by + * the client. This is supplied by the client + * of this call. + * + * classEngineID + * A concatenation of class and engineid + * that the object with handle hObject + * belongs to. This is returned by RM. The internal + * format of this data structure is opaque to clients. + * + * classID + * ClassID for object represented by hObject + * + * engineID + * EngineID for object represented by hObject + * + * Possible status values returned are: + * NV_OK + * If the call was successful. + * + * NV_ERR_INVALID_OBJECT_HANDLE + * No object of handle hObject was found. + */ +#define NV906F_CTRL_GET_CLASS_ENGINEID (0x906f0101) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */ + +#define NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS { + NvHandle hObject; + NvU32 classEngineID; + NvU32 classID; + NvU32 engineID; +} NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS; + +/* + * NV906F_CTRL_RESET_CHANNEL + * + * This command resets the channel corresponding to specified engine and also + * resets the specified engine. + * + * Takes an engine ID as input. + * + * engineID + * This parameter specifies the engine to be reset. See the description of the + * NV2080_ENGINE_TYPE values in cl2080.h for more information. + * subdeviceInstance + * This parameter specifies the subdevice to be reset when in SLI. + * resetReason + * Specifies reason to reset a channel. + * + * Possible status values returned are: + * NV_OK + */ +#define NV906F_CTRL_CMD_RESET_CHANNEL_REASON_DEFAULT 0 +#define NV906F_CTRL_CMD_RESET_CHANNEL_REASON_VERIF 1 +#define NV906F_CTRL_CMD_RESET_CHANNEL_REASON_MMU_FLT 2 +#define NV906F_CTRL_CMD_RESET_CHANNEL_REASON_ENUM_MAX 3 +/* + * Internal values for NV906F_CTRL_CMD_RESET_REASON. External values will be + * checked and enforced to be < NV906F_CTRL_CMD_RESET_CHANNEL_REASON_ENUM_MAX + */ +#define NV906F_CTRL_CMD_INTERNAL_RESET_CHANNEL_REASON_FAKE_ERROR (0x4) /* finn: Evaluated from "NV906F_CTRL_CMD_RESET_CHANNEL_REASON_ENUM_MAX + 1" */ + + +#define NV906F_CTRL_CMD_RESET_CHANNEL (0x906f0102) /* finn: Evaluated from "((FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID)" */ + +#define NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS { + NvU32 engineID; + NvU32 subdeviceInstance; + NvU32 resetReason; +} NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS; + +/* + * NV906F_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * This command sets event notification state for the associated channel. + * This command requires that an instance of NV01_EVENT has been previously + * bound to the associated channel object. + * + * event + * This parameter specifies the type of event to which the specified + * action is to be applied. This parameter must specify a valid + * NV906F_NOTIFIERS value (see cl906f.h for more details) and should + * not exceed one less NV906F_NOTIFIERS_MAXCOUNT. + * action + * This parameter specifies the desired event notification action. + * Valid notification actions include: + * NV906F_CTRL_SET_EVENT_NOTIFICATION_ACTION_DISABLE + * This action disables event notification for the specified + * event for the associated channel object. + * NV906F_CTRL_SET_EVENT_NOTIFICATION_ACTION_SINGLE + * This action enables single-shot event notification for the + * specified event for the associated channel object. + * NV906F_CTRL_SET_EVENT_NOTIFICATION_ACTION_REPEAT + * This action enables repeated event notification for the specified + * event for the associated channel object. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV906F_CTRL_CMD_EVENT_SET_NOTIFICATION (0x906f0203) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_EVENT_INTERFACE_ID << 8) | NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS { + NvU32 event; + NvU32 action; +} NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NV906F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NV906F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001) +#define NV906F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002) + +/* + * NV906F_CTRL_CMD_GET_DEFER_RC_STATE + * + * If SM Debugger is attached then on a MMU fault, RM defers the RC error + * recovery and keeps a flag indicating that RC is deferred. This command + * checks whether or not deferred RC is pending in RM for the associated + * channel. + * + * bDeferRCPending + * The output are TRUE and FALSE. + * + * Possible status values returned are: + * NV_OK + */ +#define NV906F_CTRL_CMD_GET_DEFER_RC_STATE (0x906f0105) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV906F_CTRL_CMD_GET_DEFER_RC_STATE_PARAMS_MESSAGE_ID" */ + +#define NV906F_CTRL_CMD_GET_DEFER_RC_STATE_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV906F_CTRL_CMD_GET_DEFER_RC_STATE_PARAMS { + NvBool bDeferRCPending; +} NV906F_CTRL_CMD_GET_DEFER_RC_STATE_PARAMS; + +#define NV906F_CTRL_CMD_GET_MMU_FAULT_INFO (0x906f0106) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */ + +/* + * Shader types supported by MMU fault info + * The types before compute shader refer to NV9097_SET_PIPELINE_SHADER_TYPE + */ +#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_VERTEX 0x00000001 +#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_TESSELLATION 0x00000003 +#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_GEOMETRY 0x00000004 +#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_PIXEL 0x00000005 +#define NV906F_CTRL_MMU_FAULT_SHADER_TYPE_COMPUTE 0x00000006 +#define NV906F_CTRL_MMU_FAULT_SHADER_TYPES 7 + +/* + * NV906F_CTRL_CMD_GET_MMU_FAULT_INFO + * + * This command returns MMU fault information for a given channel. The MMU + * fault information will be cleared once this command is executed. + * + * addrHi - [out] + * Upper 32 bits of faulting address + * addrLo [out] + * Lower 32 bits of faulting address + * faultType [out] + * MMU fault type. Please see NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE_* in + * dev_fifo.h for details about MMU fault type. + * faultString [out] + * String indicating the MMU fault type + * shaderProgramVA [out] + * an array of shader program virtual addresses to indicate faulted shaders in the pipeline + * + * Possible status values returned are: + * NV_OK + */ +#define NV906F_CTRL_MMU_FAULT_STRING_LEN 32 +#define NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS { + NvU32 addrHi; + NvU32 addrLo; + NvU32 faultType; + char faultString[NV906F_CTRL_MMU_FAULT_STRING_LEN]; + NV_DECLARE_ALIGNED(NvU64 shaderProgramVA[NV906F_CTRL_MMU_FAULT_SHADER_TYPES], 8); +} NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS; + + +/* _ctrl906f.h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9072.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9072.h new file mode 100644 index 0000000..8c3cceb --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9072.h @@ -0,0 +1,86 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl9072.finn +// + +#include "ctrl/ctrlxxxx.h" +#define NV9072_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0x9072, NV9072_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NV9072_CTRL_RESERVED (0x00) +#define NV9072_CTRL_DISP_SW (0x01) + + +/* + * NV9072_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV9072_CTRL_CMD_NULL (0x90720000) /* finn: Evaluated from "(FINN_GF100_DISP_SW_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV9072_CTRL_CMD_NOTIFY_ON_VBLANK + * + * This command implements an out-of-band version of the + * GF100_DISP_SW class's NV9072_NOTIFY_ON_VBLANK method. + * + * Parameters: + * + * data + * Valid data accepted by the NV9072_NOTIFY_ON_VBLANK method. + * bHeadDisabled + * Specifies whether head is active while adding vblank + * callback. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ +#define NV9072_CTRL_CMD_NOTIFY_ON_VBLANK (0x90720101) /* finn: Evaluated from "(FINN_GF100_DISP_SW_DISP_SW_INTERFACE_ID << 8) | NV9072_CTRL_CMD_NOTIFY_ON_VBLANK_PARAMS_MESSAGE_ID" */ + +#define NV9072_CTRL_CMD_NOTIFY_ON_VBLANK_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV9072_CTRL_CMD_NOTIFY_ON_VBLANK_PARAMS { + NvU32 data; + NvBool bHeadDisabled; +} NV9072_CTRL_CMD_NOTIFY_ON_VBLANK_PARAMS; + +/* _ctrl9072.h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9074.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9074.h new file mode 100644 index 0000000..47b8d2f --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9074.h @@ -0,0 +1,148 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl9074.finn +// + +#include "ctrl/ctrlxxxx.h" +#define NV9074_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x9074, NV9074_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NV9074_CTRL_RESERVED (0x00) +#define NV9074_CTRL_SEM (0x01) + +/* + * NV9074_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV9074_CTRL_CMD_NULL (0x90740000) /* finn: Evaluated from "(FINN_GF100_TIMED_SEMAPHORE_SW_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV9074_CTRL_CMD_FLUSH + * + * This command is intended to aid in idling/flushing a channel containing + * methods invoked against a specific NV9074 object. + * + * This control manipulates an NV9074 object's "flushing" state. + * + * Typical usage is: + * NvRmControl(NV9074_CTRL_CMD_FLUSH, {TRUE, flushDelay}); + * NvRmIdleChannel(channel_containing_the_9074_object); + * NvRmControl(NV9074_CTRL_CMD_FLUSH, {FALSE, 0}); + * + * When an NV9074 object is placed into the flushing state, a snaphot of the + * current timer value is taken, and "maxFlushTime" is added to this. This + * value is the "flush limit timestamp". Any previously or newly invoked + * NV9074_SEMAPHORE_SCHED methods and NV9074_CTRL_CMD_RELEASE requests that + * specify a release timestamp at or after this "flush limit timestamp" will + * immediately release the specified semaphore, without waiting for the + * specified timestamp, and write a DONE_FORCED value to the specified notifier. + */ +#define NV9074_CTRL_CMD_FLUSH (0x90740101) /* finn: Evaluated from "(FINN_GF100_TIMED_SEMAPHORE_SW_SEM_INTERFACE_ID << 8) | NV9074_CTRL_CMD_FLUSH_PARAMS_MESSAGE_ID" */ + +#define NV9074_CTRL_CMD_FLUSH_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV9074_CTRL_CMD_FLUSH_PARAMS { + NvU32 isFlushing; + NV_DECLARE_ALIGNED(NvU64 maxFlushTime, 8); +} NV9074_CTRL_CMD_FLUSH_PARAMS; + +/* + * NV9074_CTRL_CMD_GET_TIME + * + * Retrieve the current time value. + */ +#define NV9074_CTRL_CMD_GET_TIME (0x90740102) /* finn: Evaluated from "(FINN_GF100_TIMED_SEMAPHORE_SW_SEM_INTERFACE_ID << 8) | NV9074_CTRL_CMD_GET_TIME_PARAMS_MESSAGE_ID" */ + +#define NV9074_CTRL_CMD_GET_TIME_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV9074_CTRL_CMD_GET_TIME_PARAMS { + NV_DECLARE_ALIGNED(NvU64 currentTime, 8); +} NV9074_CTRL_CMD_GET_TIME_PARAMS; + +/* + * NV9074_CTRL_CMD_RELEASE + * + * This command adds a timed semaphore release request. When the desired time is + * reached, the semaphore is written with the release value, the notifier is + * filled with status and timestamp, and optionally an event is sent to all the + * client waiting on it. + * + * notifierGPUVA + * This parameter specifies the GPU VA of the notifier to receive the status + * for this particular release. + * + * semaphoreGPUVA + * This parameter specifies the GPU VA of the semaphore to release. + * + * waitTimestamp + * This parameter specifies the timestamp at which to release the semaphore. + * + * releaseValue + * This parameter specifies the semaphore value to release. + * + * releaseFlags + * This parameter specifies the flags: + * _NOTIFY wake client or not. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ADDRESS + * NV_ERR_INVALID_EVENT + * NV_ERR_INVALID_STATE + * + */ +#define NV9074_CTRL_CMD_RELEASE (0x90740103) /* finn: Evaluated from "(FINN_GF100_TIMED_SEMAPHORE_SW_SEM_INTERFACE_ID << 8) | NV9074_CTRL_CMD_RELEASE_PARAMS_MESSAGE_ID" */ + +#define NV9074_CTRL_CMD_RELEASE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV9074_CTRL_CMD_RELEASE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 notifierGPUVA, 8); + NV_DECLARE_ALIGNED(NvU64 semaphoreGPUVA, 8); + NV_DECLARE_ALIGNED(NvU64 waitTimestamp, 8); + NvU32 releaseValue; + NvU32 releaseFlags; +} NV9074_CTRL_CMD_RELEASE_PARAMS; + +#define NV9074_CTRL_CMD_RELEASE_FLAGS +#define NV9074_CTRL_CMD_RELEASE_FLAGS_NOTIFY 1:0 +#define NV9074_CTRL_CMD_RELEASE_FLAGS_NOTIFY_WRITE_ONLY (0x00000000) +#define NV9074_CTRL_CMD_RELEASE_FLAGS_NOTIFY_WRITE_THEN_AWAKEN (0x00000001) + +/* _ctrl9074.h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9096.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9096.h new file mode 100644 index 0000000..4aaca21 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl9096.h @@ -0,0 +1,444 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl9096.finn +// + +#include "ctrl/ctrlxxxx.h" +#define NV9096_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0x9096, NV9096_CTRL_##cat, idx) + +/* NV9096 command categories (6bits) */ +#define NV9096_CTRL_RESERVED (0x00U) +#define NV9096_CTRL_ZBC (0x01U) + + +/* + * NV9096_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV9096_CTRL_CMD_NULL (0x90960000U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* + * NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_ + * These are various possible CtFormats which + * the Client passes down to RM to set in the DS + * Color Table. + */ + + + +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_INVALID 0x00000000U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_ZERO 0x00000001U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_UNORM_ONE 0x00000002U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_RF32_GF32_BF32_AF32 0x00000004U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_R16_G16_B16_A16 0x00000008U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_RN16_GN16_BN16_AN16 0x0000000cU +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_RS16_GS16_BS16_AS16 0x00000010U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_RU16_GU16_BU16_AU16 0x00000014U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_RF16_GF16_BF16_AF16 0x00000016U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_A8R8G8B8 0x00000018U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_A8RL8GL8BL8 0x0000001cU +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_A2B10G10R10 0x00000020U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_AU2BU10GU10RU10 0x00000024U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_A8B8G8R8 0x00000028U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_A8BL8GL8RL8 0x0000002cU +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_AN8BN8GN8RN8 0x00000030U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_AS8BS8GS8RS8 0x00000034U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_AU8BU8GU8RU8 0x00000038U +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_A2R10G10B10 0x0000003cU +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL_BF10GF11RF11 0x00000040U + +/* + * NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR + * + * This command attempts to add a new entry to Color ZBC Tables. + * + * colorFB + * This field sets the raw framebuffer values for the ZBC table entries. Prior to + * GA10x, these values are written into the "L2" table. + * From GA10x and later, these values are written in "CROP" table. + * colorDS + * This field sets format-independent values for ZBC table entries. Prior to GA10X, + * these values are written in the "DS" table and matched with the format-independent + * clear color sent in the 3D class. These values are ignored on GA10X and later + * format + * This field specifies color format for ZBC table entries and should be one of the + * NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT* enums. Prior to GA10X, these values + * are written in the format field of the hardware ZBC table entry and are matched + * against the color format sent in the 3D class. These values are ignored on GA10X and later. + * bSkipL2Table + * This parameter specifies if the L2 ZBC table should be updated or not. If + * this parameter is set to a non-zero value, the L2 ZBC table will not be + * updated. If this parameter is set to 0, the L2 ZBC table will be updated. This + * parameter will skip programming DS table values in Pre-GA10x. From GA10x and later + * this parameter will skip programming CROP table entries. + * Note: This parameter will only be supported in verification platforms. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INSUFFICIENT_RESOURCES + */ +#define NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR (0x90960101U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_MESSAGE_ID" */ + +#define NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE 4U +#define NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS { + NvU32 colorFB[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 colorDS[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 format; + NvBool bSkipL2Table; +} NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS; + + +/* + * NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR_FMT_VAL + * These are various possible formats which the Client passes down to RM to set in the ZBC clear + * Table. + * + * Though the "Depth" data written in both the DS as well as L2 Version of the + * depth table are of (only available!) FP32 Format. Still the format + * support is currently given with _CTRL_CMD_SET_ZBC_DEPTH_CLEAR as this format will + * be used later on to disable/remove an entry from the table. + * In future this field is going to be significant for + * "Depth" entries too. + */ + +#define NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR_FMT_VAL_INVALID 0x00000000U +// Fix me: Fix the name to FMT_VAL_FP32 +#define NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR_FMT_FP32 0x00000001U + +/* + * NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR + * + * This command attempts to add a new entry to Depth ZBC Tables. + * + * depth + * This field specifies the ZBC depth clear value to be set. + * format + * This field specifies the Depth format for the data send in by the client. + * bSkipL2Table + * This parameter specifies if the L2 ZBC table should be updated or not. If + * this parameter is set to a non-zero value, the L2 ZBC table will not be + * updated. If this parameter is set to 0, the L2 ZBC table will be updated. + * Note: This parameter will only be supported in verification platforms. + * + + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INSUFFICIENT_RESOURCES + */ +#define NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR (0x90960102U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_MESSAGE_ID" */ + +#define NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS { + NvU32 depth; + NvU32 format; + NvBool bSkipL2Table; +} NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS; + +/* + * NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE + * + * + * This command is used to get the ZBC Clear Color/Depth/Stencil table data i.e. color + * values and the status "Use-satatus" of each value in the table from RM. + * + * colorFB + * This value returns raw framebuffer values for color ZBC table entries. Pre-GA10x, these values + * are taken from the "L2" table. From GA10x+, these values are taken from CROP table. This value is + * set only when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_COLOR" + * colorDS + * Pre-GA10x, returns the DS color value set for ZBC. From GA10x+, returns zeroes since this format is + * deprecated in HW. This value is set only when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_COLOR" + * depth + * This field returns the ZBC depth clear value set, when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_DEPTH". + * stencil + * This field returns the ZBC stencil clear value set, when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_STENCIL" + * format + * This field returns the format of color, depth, or stencil ZBC table entries, using the + * NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT, + * NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR_FMT, + * NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR_FMT* enums depending on the table identified by valType. + * On GA10X and later, color ZBC table entries do not have a format in hardware and this query + * returns a format of "INVALID". + * valType + * This filed specifies the type of the Table data to be fetched. + * Possible Types are : + * NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_COLOR + * NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_DEPTH + * NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_STENCIL + * indexUsed + * This boolean parameter indicates if a particular index of the table is valid or not. + * + * Note: The following parameters are deprecated after Tegra interface is also changed. Clients need + * to use NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_SIZE to query the (start, end) indexes of respective ZBC tables + * + * indexSize + * This parameter is used to fetch the table size when "valType" parameter + * is specified as " 0 ".(INVALID TYPE). It is also used to pass in the + * index of the ZBC table for which we want the COLOR/DEPTH info. + * indexStart + * This parameter is used to return the valid starting index of ZBC table, when + * "valType" parameter is specified as "INVALID_TYPE". It will also be used + * as input index to query the ZBC table for COLOR/QUERY/STENCIL Info. + * indexEnd + * This parameter is used to return the valid ending index of ZBC table, when + * "valType" parameter is specified as "INVALID_TYPE". + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE (0x90960103U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_MESSAGE_ID" */ + +#define NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_INVALID 0U +#define NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_COLOR 1U +#define NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_DEPTH 2U +#define NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_STENCIL 3U +#define NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS { + struct { + NvU32 colorFB[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 colorDS[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 depth; + NvU32 stencil; + } value; + NvU32 indexSize; + NvU32 indexStart; + NvU32 indexEnd; + NvU32 indexUsed; /* TODO: Change to NvBool, need to fix the tegra interface too */ + NvU32 format; + NvU32 valType; +} NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS; + +/* + * Note: This ctrl call is deprecated. To program ZBC table entries, please use + * NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR + * NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR + * NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR + * which will update a single entry in single table at a time. + * + * + * NV9096_CTRL_CMD_SET_ZBC_CLEAR_TABLE + * + * This command is used to set the ZBC Clear Color/Depth/Stencil table data at a specified + * index. The parameters to this command are described below. + * + * colorFB + * This array field specifies the L2 color value to be written to the ZBC table. + * colorDS + * This array field specifies the DS color value to be written to the ZBC table. + * colorFormat + * This field specifies the ZBC color format to be set. This field must be set + * to one of the valid NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL* defines. + * depth + * This field specifies the ZBC depth clear value to be set. + * depthFormat + * This field specifies the ZBC depth format to be set. This field must be set + * to one of the valid NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR_FMT_VAL* defines. + * stencil + * This field specifies the ZBC stencil clear value to be set. + * stencilFormat + * This field specifies the ZBC stencil format to be set. This field must be set + * to one of the valid NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR_FMT_VAL* defines. + * index + * This field specifies the index at which the color/depth data is to be + * written into the ZBC table. Legal values for this field must lie between + * 1 and the value returned in the indexSize parameter of the + * NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE control call when called with the + * parameter valType set to NV9096_CTRL_ZBC_CLEAR_OBJECT_TYPE_INVALID. + * bSkipL2Table + * This parameter specifies if the L2 ZBC table should be updated or not. If + * this parameter is set to a non-zero value, the L2 ZBC table will not be + * updated. If this parameter is set to 0, the L2 ZBC table will be updated. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INSUFFICIENT_RESOURCES + */ +#define NV9096_CTRL_CMD_SET_ZBC_CLEAR_TABLE (0x90960104U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_SET_ZBC_CLEAR_TABLE_PARAMS_MESSAGE_ID" */ + +#define NV9096_CTRL_SET_ZBC_CLEAR_TABLE_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV9096_CTRL_SET_ZBC_CLEAR_TABLE_PARAMS { + NvU32 colorFB[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 colorDS[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 colorFormat; + NvU32 depth; + NvU32 depthFormat; + NvU32 stencil; + NvU32 stencilFormat; + NvU32 index; + NvBool bSkipL2Table; +} NV9096_CTRL_SET_ZBC_CLEAR_TABLE_PARAMS; + +/* + * NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR_FMT_VAL_ + * These are various possible Formats which the Client passes down to RM to set in the + * ZBC clear(DSS) Table. + */ + +#define NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR_FMT_VAL_INVALID 0x00000000U +// Fix me: Change it to CLEAR_FMT_VAL_U8 +#define NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR_FMT_U8 0x00000001U + +/* + * NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR + * + * This command attempts to add a new entry to Stencil ZBC Tables. + * + * stencil + * This field specifies the ZBC stencil clear value to be set. + * format + * This field specifies the stencil format for the data send in by the client. + * bSkipL2Table + * This parameter specifies if the L2 ZBC table should be updated or not. If + * this parameter is set to a non-zero value, the L2 ZBC table will not be + * updated. If this parameter is set to 0, the L2 ZBC table will be updated. + * Note: This parameter will only be supported in verification platforms. + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INSUFFICIENT_RESOURCES + */ +#define NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR (0x90960105U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_MESSAGE_ID" */ + +#define NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS { + NvU32 stencil; + NvU32 format; + NvBool bSkipL2Table; +} NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS; + +/* + * NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_SIZE + * This command returns the range of valid indices in the color, depth, or stencil ZBC tables. + * + * indexStart + * This parameter is used to return the first valid index in the color, depth, or stencil ZBC table, + * depending on the value passed in the tableType + * indexEnd + * This parameter is used to return the last valid index in the color, depth, or stencil ZBC table, + * depending on the value passed in the tableType + * tableType + * This field specifies the type of the Table data to be fetched. + * Possible Types are : + * NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR + * NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_DEPTH + * NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_STENCIL + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +typedef enum NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE { + NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_INVALID = 0, + NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR = 1, + NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_DEPTH = 2, + NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_STENCIL = 3, + NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT = 4, +} NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE; + +#define NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_SIZE (0x90960106U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS { + NvU32 indexStart; + NvU32 indexEnd; + NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE tableType; +} NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS; + +/* + * NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_ENTRY + * This command returns the ZBC entry stored in the color, depth or stencil ZBC tables + * + * colorFB[out] + * This value returns raw framebuffer values for color ZBC table entries. Pre-GA10x, these values + * are taken from the "L2" table. From GA10x+, these values are taken from CROP table. This value is + * set only when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR" + * colorDS[out] + * Pre-GA10x, returns the DS color value set for ZBC. From GA10x+, returns zeroes since this format is + * deprecated in HW. This value is set only when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR" + * depth[out] + * This field specifies the ZBC depth clear value set, when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_DEPTH". + * stencil[out] + * This field specifies the ZBC stencil clear value set, when valType is chosen as "NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_STENCIL" + * format + * This field returns the format of color, depth, or stencil ZBC table entries, using the + * NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR_FMT_VAL*, + * NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR_FMT*, + * NV9096_CTRL_CMD_SET_ZBC_STENCIL_CLEAR_FMT* enums depending on the table identified by valType. + * On GA10X and later, color ZBC table entries do not have a format in hardware and this query + * returns a format of "INVALID". + * index[in] + * This field specifies table index for which the ZBC entry information needs to be fetched. + * bIndexValid[out] + * This field specifies whether the entry is valid or not. + * tableType[in] + * This field specifies the type of the Table data to be fetched. + * Possible Types are : + * NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR + * NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_DEPTH + * NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_STENCIL + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_ENTRY (0x90960107U) /* finn: Evaluated from "(FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID << 8) | NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_MESSAGE_ID" */ + +#define NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS { + struct { + NvU32 colorFB[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 colorDS[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 depth; + NvU32 stencil; + } value; + NvU32 format; + NvU32 index; + NvBool bIndexValid; + NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE tableType; +} NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS; + +/* _ctrl9096_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cc.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cc.h new file mode 100644 index 0000000..fa02e75 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cc.h @@ -0,0 +1,455 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90cc.finn +// + + + + +#include "ctrl/ctrlxxxx.h" +#include "ctrl90cc/ctrl90ccbase.h" + +#include "ctrl90cc/ctrl90cchwpm.h" + + +#include "ctrl90cc/ctrl90ccpower.h" + + +/* + * NV90CC_CTRL_CMD_PROFILER_RESERVE_HWPM + * + * This command is deprecated; please use NV90CC_CTRL_CMD_HWPM_RESERVE. + * + * This command attempts to reserve the perfmon for use by the calling client. + * If this object was allocated as a child of a subdevice, then the + * reservation will be global among all contexts on that subdevice. If this + * object was allocated as a child of a channel group or a channel, then the + * reservation will only be for the hardware context of that channel group or + * channel. + * + * If the global reservation is held on a subdevice by another client, then + * this command will fail, regardless of the parent class. + * + * If one or more per-context reservations are held by other clients, then + * this command will fail if the parent object is a subdevice or another + * client already holds the perfmon reservation for the parent context. + * + * This command will return NV_ERR_STATE_IN_USE for all of the failure + * cases described above. A return status of NV_OK guarantees + * that the client holds the perfmon reservation of the appropriate scope. + * + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_STATE_IN_USE + */ +#define NV90CC_CTRL_CMD_PROFILER_RESERVE_HWPM NV90CC_CTRL_CMD_HWPM_RESERVE + +/* + * NV90CC_CTRL_CMD_PROFILER_RELEASE_HWPM + * + * This command is deprecated; please use NV90CC_CTRL_CMD_HWPM_RELEASE. + * + * This command releases an existing reservation of the perfmon for the + * calling client. If the calling client does not currently have the perfmon + * reservation as acquired by NV90CC_CTRL_CMD_PROFILER_RESERVE_HWPM, this + * command will return NV_ERR_INVALID_REQUEST. + * + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + */ +#define NV90CC_CTRL_CMD_PROFILER_RELEASE_HWPM NV90CC_CTRL_CMD_HWPM_RELEASE + + + +/* + * NV90CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS + * + * This command is deprecated; please use + * NV90CC_CTRL_CMD_POWER_REQUEST_POWER_FEATURES. + * + * This command attempts to enable or disable various clock-gating features of + * the GPU on behalf of the profiler. If this command is unable to set the + * clock-gating feature state of any of the requested features, this command + * will fail and none of the requested features will be modified. If this + * command fails because one or more clock-gating feature requests were + * rejected, it will return NV_ERR_STATE_IN_USE in the globalStatus + * parameter and the fields in the statusMask parameter for the features for + * which the requests were rejected will have the value + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_REJECTED. + * If a given feature is not supported on the GPU, the field for that clock- + * gating feature will have the value + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_NOT_SUPPORTED in the + * statusMask parameter, but this condition by itself will not cause the + * command to fail. Even if this command fails, the field for clock-gating + * features which would have successfully changed will have the value + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_FULFILLED in the statusMask + * parameter. + * + * Each of the clock-gating features is reference-counted individually, so + * that multiple GF100_PROFILER objects may request and rely on the same + * settings for the features simultaneously. Each clock-gating feature is + * locked to the requested state until the GF100_PROFILER object is freed or + * the NV90CC_CTRL_CMD_PROFILER_RELEASE_CG_CONTROLS command is called for that + * feature. + * + * Currently, only GF100_PROFILER requests for power features using this + * command are reference counted. Changes to the power feature settings made + * either by other control commands or the RM itself may interfere with the + * settings requested by GF100_PROFILER instances. + * + * This command will always return NV_OK when given valid + * parameters. If there is any other failure that prevents the clock-gating + * features from being set appropriately, the globalStatus parameter will + * indicate this and the statusMask parameter will indicate which clock-gating + * feature requests failed and why. + * + * controlMask + * This parameter indicates which clock-gating features the request should + * apply to. This parameter has the following fields: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG + * The value of this field indicates whether this request should apply + * to engine-level clock-gating of the GR engine. Valid values for + * this field are: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_IGNORE + * This value indicates that the GR engine-level clock-gating + * should be ignored. This will not affect the reference count for + * this feature. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_DISABLE + * This value indicates that the GR engine-level clock-gating + * should be disabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_ENABLE + * This value indicates that the GR engine-level clock-gating + * should be enabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG + * The value of this field indicates whether this request should apply + * to block-level clock-gating. Valid values for this field are: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_IGNORE + * This value indicates that block-level clock-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_DISABLE + * This value indicates that block-level clock-gating should be + * disabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_ENABLE + * This value indicates that block-level clock-gating should be + * enabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG + * The value of this field indicates whether this request should apply + * to second-level clock-gating. Valid values for this field are: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_IGNORE + * This value indicates that second-level clock-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_DISABLE + * This value indicates that second-level clock-gating should be + * disabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_ENABLE + * This value indicates that second-level clock-gating should be + * enabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG + * The value of this field indicates whether this request should apply + * to GR engine-level power-gating. Valid values for this field are: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_IGNORE + * This value indicates that engine-level power-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_DISABLE + * This value indicates that engine-level power-gating should be + * disabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_ENABLE + * This value indicates that engine-level power-gating should be + * enabled. + * Note that this field is only temporary to allow reference counting + * restricted to GF100_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN + * The value of this field indicates whether this request should apply + * to SM idle slowdown. Valid values for this field are: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_IGNORE + * This value indicates that SM idle slowdown should be ignored. + * This will not affect the reference count for this feature. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_DISABLE + * This value indicates that SM idle slowdown should be disabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_ENABLE + * This value indicates that SM idle slowdown should be enabled. + * Note that this field is only temporary to allow reference counting + * restricted to GF100_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT + * The value of this field indicates whether this request should apply + * to VAT. Valid values for this field are: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_IGNORE + * This value indicates that VAT should be ignored. + * This will not affect the reference count for this feature. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_DISABLE + * This value indicates that VAT should be disabled. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_ENABLE + * This value indicates that VAT should be enabled. + * Note that this field is only temporary to allow reference counting + * restricted to GF100_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * globalStatus + * This parameter returns the overall status of the requests for all + * clock-gating controls. If the value of this parameter is not + * NV_OK, none of the clock-gating controls will be set as + * requested. Possible values for this parameter are: + * NV_OK + * This value indicates that all of the clock-gating control requests + * were either fulfilled or not supported on the hardware. + * NV_ERR_INVALID_REQUEST + * This value indicates that at least one of the clock-gating control + * requests were invalid given the GF100_PROFILER instance's + * outstanding requests. + * NV_ERR_STATE_IN_USE + * This value indicates that at least one of the clock-gating controls + * has already been locked to a conflicting state by another + * GF100_PROFILER instance or the RM itself. + * statusMask + * This parameter returns the status of the request to set each clock- + * gating control specified by the controlMask parameter. The fields are + * identical to those of the controlMask parameter. For each field for + * which the corresponding field in the controlMask parameter has the + * value NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_IGNORE, the value is + * undefined. For each field for which the corresponding field in the + * controlMask parameter has the value + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST, the value will be + * one of the following: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_FULFILLED + * This value indicates that the clock-gating feature corresponding to + * the field in question was enabled or disabled according to the + * controlMask parameter, and the reference count for the feature was + * incremented accordingly. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_REJECTED + * This value indicates that the clock-gating feature corresponding to + * the field in question was not set to the expected state according + * to the controlMask parameter because another conflicting request is + * currently outstanding for the clock-gating feature. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_FAILED + * This value indicates that the clock-gating feature corresponding to + * the field in question was not set to the expected state according + * to the controlMask parameter because the attempt to do so failed + * with an error other than a conflicting request. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_NOT_SUPPORTED + * This value indicates that the clock-gating feature corresponding to + * the field in question is not supported on this GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV90CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES + +typedef NV90CC_CTRL_POWER_REQUEST_FEATURES_PARAMS NV90CC_CTRL_PROFILER_REQUEST_CG_CONTROLS_PARAMS; + +/* valid fields for the controlMask and statusMask parameters */ +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG 1:0 +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG 3:2 +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG 5:4 + +/* + * The following are temporary fields for the controlMask and statusMask + * parameters. They are required to reference count their respective features + * until the existing RM controls can be safely updated, and the definitions + * for these features will be removed soon after that. + */ +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG 7:6 +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN 9:8 +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT 11:10 + +/* valid values for fields in the controlMask parameter */ +#define NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE (0x00000000) +#define NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE (0x00000001) +#define NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE (0x00000002) + +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_IGNORE NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_DISABLE NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_ENABLE NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_IGNORE NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_DISABLE NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_ENABLE NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_IGNORE NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_DISABLE NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_ENABLE NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_IGNORE NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_DISABLE NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_ENABLE NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_IGNORE NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_DISABLE NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_ENABLE NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_IGNORE NV90CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_DISABLE NV90CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_ENABLE NV90CC_CTRL_PROFILER_CG_CONTROL_ENABLE +/* possible values for fields in the statusMask parameter */ +#define NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED (0x00000000) +#define NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED (0x00000001) +#define NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED (0x00000002) +#define NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED (0x00000003) + +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_FULFILLED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_REJECTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_NOT_SUPPORTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_FAILED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_FULFILLED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_REJECTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_NOT_SUPPORTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_FAILED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_FULFILLED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_REJECTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_NOT_SUPPORTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_FAILED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_FULFILLED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_REJECTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_NOT_SUPPORTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_FAILED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_FULFILLED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_REJECTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_NOT_SUPPORTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_FAILED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_FULFILLED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_REJECTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_NOT_SUPPORTED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_FAILED NV90CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED + +/* utility masks for the controlMask parameter for all controls */ +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL \ + DRF_SHIFTMASK(NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG) | \ + DRF_SHIFTMASK(NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG) | \ + DRF_SHIFTMASK(NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG) | \ + DRF_SHIFTMASK(NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG) | \ + DRF_SHIFTMASK(NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN) | \ + DRF_SHIFTMASK(NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT) +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_IGNORE \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _IGNORE) +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_DISABLE \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _DISABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _DISABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _DISABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _DISABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _DISABLE)| \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _DISABLE) +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_ENABLE \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _ENABLE) + +/* + * NV90CC_CTRL_CMD_PROFILER_RELEASE_CG_CONTROLS + * + * This command is deprecated; please us + * NV90CC_CTRL_CMD_POWER_RELEASE_FEATURES. + * + * This command releases the GF100_PROFILER's request for the given clock- + * gating features that was previously created by the + * NV90CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS command. If the GF100_PROFILER + * object does not have an outstanding request to one or more of the given + * clock-gating features, those features will be ignored while the other + * feature requests will be released. + * + * After calling this command, the calling client may not rely on the current + * value of any of the released clock-gating features to remain, even if + * several identical requests for the given clock-gating features were made + * using NV90CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS. The RM only reference- + * counts the settings requested by GF100_PROFILER instances - it does not + * reference-count multiple identical requests made using the same + * GF100_PROFILER instance. + * + * All outstanding requests made using this GF100_PROFILER object are + * implicitly released when the GF100_PROFILER is freed. + * + * controlMask + * This parameter indicates which clock-gating features the RM should + * release the GF100_PROFILER's reference to. See + * NV90CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS for valid fields. Valid + * values for each field are: + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_IGNORE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_IGNORE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_IGNORE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_IGNORE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_IGNORE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_IGNORE + * This value indicates that the clock-gating feature associated with + * the field should not be released, even if the GF100_PROFILER has an + * outstanding request for it. This will not affect the reference + * count for the feature. + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_RELEASE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_RELEASE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_RELEASE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_RELEASE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_RELEASE + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_RELEASE + * This value indicates that the GF100_PROFILER's outstanding request + * for the clock-gating feature associated with the field should be + * released. This will decrement the reference count for the feature + * if the GF100_PROFILER has an outstanding request for it. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV90CC_CTRL_CMD_PROFILER_RELEASE_CG_CONTROLS NV90CC_CTRL_CMD_POWER_RELEASE_FEATURES + +typedef NV90CC_CTRL_POWER_RELEASE_FEATURES_PARAMS NV90CC_CTRL_PROFILER_RELEASE_CG_CONTROLS_PARAMS; + +/* + * valid values for the controlMask parameter in addition to + * NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_*_IGNORE + */ +#define NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE (0x00000003) + +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_RELEASE NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_RELEASE NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_RELEASE NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_RELEASE NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_RELEASE NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_RELEASE NV90CC_CTRL_PROFILER_CG_CONTROL_RELEASE + +/* utility mask for the controlMask parameter for all fields */ +#define NV90CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_RELEASE \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _RELEASE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _RELEASE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _RELEASE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _RELEASE) | \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _RELEASE)| \ + DRF_DEF(90CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _RELEASE) + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cc/ctrl90ccbase.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cc/ctrl90ccbase.h new file mode 100644 index 0000000..707ec03 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cc/ctrl90ccbase.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90cc/ctrl90ccbase.finn +// + +#include "ctrl/ctrlxxxx.h" +/* GF100_PROFILER control commands and parameters */ + +#define NV90CC_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x90CC, NV90CC_CTRL_##cat, idx) + +/* GF100_PROFILER command categories (6 bits) */ +#define NV90CC_CTRL_RESERVED (0x00) +#define NV90CC_CTRL_HWPM (0x01) + + +#define NV90CC_CTRL_POWER (0x03) + +/* + * NV90CC_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV90CC_CTRL_CMD_NULL (0x90cc0000) /* finn: Evaluated from "(FINN_GF100_PROFILER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrl90ccbase_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cc/ctrl90cchwpm.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cc/ctrl90cchwpm.h new file mode 100644 index 0000000..b1013f2 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cc/ctrl90cchwpm.h @@ -0,0 +1,135 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90cc/ctrl90cchwpm.finn +// + +#include "ctrl/ctrl90cc/ctrl90ccbase.h" + +/* GF100_PROFILER HWPM control commands and parameters */ + +/* + * NV90CC_CTRL_CMD_HWPM_RESERVE + * + * This command attempts to reserve the perfmon for use by the calling client. + * If this object was allocated as a child of a subdevice, then the + * reservation will be global among all contexts on that subdevice. If this + * object was allocated as a child of a channel group or a channel, then the + * reservation will only be for the hardware context of that channel group or + * channel. + * + * If the global reservation is held on a subdevice by another client, then + * this command will fail, regardless of the parent class. + * + * If one or more per-context reservations are held by other clients, then + * this command will fail if the parent object is a subdevice or another + * client already holds the perfmon reservation for the parent context. + * + * This command will return NV_ERR_STATE_IN_USE for all of the failure + * cases described above. A return status of NV_OK guarantees + * that the client holds the perfmon reservation of the appropriate scope. + * + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_STATE_IN_USE + */ +#define NV90CC_CTRL_CMD_HWPM_RESERVE (0x90cc0101) /* finn: Evaluated from "(FINN_GF100_PROFILER_HWPM_INTERFACE_ID << 8) | 0x1" */ + +/* + * NV90CC_CTRL_CMD_HWPM_RELEASE + * + * This command releases an existing reservation of the perfmon for the + * calling client. If the calling client does not currently have the perfmon + * reservation as acquired by NV90CC_CTRL_CMD_PROFILER_RESERVE_HWPM, this + * command will return NV_ERR_INVALID_REQUEST. + * + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + */ +#define NV90CC_CTRL_CMD_HWPM_RELEASE (0x90cc0102) /* finn: Evaluated from "(FINN_GF100_PROFILER_HWPM_INTERFACE_ID << 8) | 0x2" */ + +/* + * NV90CC_CTRL_CMD_HWPM_GET_RESERVATION_INFO + * + * This command returns information about any outstanding perfmon + * reservations. If this object was allocated as a child of a subdevice, then + * this command will return information about all reservations on the + * subdevice (global or per-context). If this object was allocated as a child + * of a channel group or channel, then this command will only return + * information about the per-context reservation for that context or the + * global reservation, if one exists. + * + * reservationCount + * This parameter returns the number of outstanding perfmon reservations + * in the applicable scope. If the value of the bGlobal parameter is + * NV_TRUE, then this parameter will have a value of 1. If this object was + * allocated as a child of a channel group or channel, then this parameter + * will have a value of either 0 or 1. If this object was allocated as a + * child of a subdevice and the bGlobal parameter is NV_FALSE, then this + * parameter will return the number of per-context reservations on the + * subdevice. + * pid + * This parameter returns the PID of a process that holds a reservation in + * the applicable scope. If the value of the bGlobal parameter is NV_TRUE, + * then this parameter will be the PID of the process holding the global + * perfmon reservation on the subdevice. Otherwise, if the value of + * reservationCount is greater than 0, the value of this parameter will be + * the PID of one of the process that holds the per-context lock in the + * applicable scope. If the value of the reservationCount parameter is 0, + * the value of this parameter is undefined. + * bGlobal + * This parameter returns whether the outstanding perfmon reservation held + * by any client is global or per-context. If the value of this parameter + * is NV_TRUE, then the value of the reservationCount parameter should be 1 + * and the value of the pid parameter should be the pid of the process + * that holds the global perfmon reservation. The value of this parameter + * will be NV_FALSE when there is no global perfmon reservation. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV90CC_CTRL_CMD_HWPM_GET_RESERVATION_INFO (0x90cc0103) /* finn: Evaluated from "(FINN_GF100_PROFILER_HWPM_INTERFACE_ID << 8) | NV90CC_CTRL_HWPM_GET_RESERVATION_INFO_PARAMS_MESSAGE_ID" */ + +#define NV90CC_CTRL_HWPM_GET_RESERVATION_INFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV90CC_CTRL_HWPM_GET_RESERVATION_INFO_PARAMS { + NvU32 reservationCount; + NvU32 pid; + NvBool bGlobal; +} NV90CC_CTRL_HWPM_GET_RESERVATION_INFO_PARAMS; + + + +/* _ctrl90cchwpm_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cc/ctrl90ccpower.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cc/ctrl90ccpower.h new file mode 100644 index 0000000..aa25ceb --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cc/ctrl90ccpower.h @@ -0,0 +1,403 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90cc/ctrl90ccpower.finn +// + +#include "ctrl/ctrl90cc/ctrl90ccbase.h" + +/* GF100_PROFILER GPU control commands and parameters */ +/* + * NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES + * + * This command attempts to enable or disable various clock-gating features of + * the GPU on behalf of the profiler. If this command is unable to set the + * clock-gating feature state of any of the requested features, this command + * will fail and none of the requested features will be modified. If this + * command fails because one or more clock-gating feature requests were + * rejected, it will return NV_ERR_STATE_IN_USE in the globalStatus + * parameter and the fields in the statusMask parameter for the features for + * which the requests were rejected will have the value + * NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_REJECTED. + * If a given feature is not supported on the GPU, the field for that clock- + * gating feature will have the value + * NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_NOT_SUPPORTED in the + * statusMask parameter, but this condition by itself will not cause the + * command to fail. Even if this command fails, the field for clock-gating + * features which would have successfully changed will have the value + * NV90CC_CTRL_POWER_FEATURE_MASK_*_FULFILLED in the statusMask + * parameter. + * + * Each of the clock-gating features is reference-counted individually, so + * that multiple GF100_PROFILER objects may request and rely on the same + * settings for the features simultaneously. Each clock-gating feature is + * locked to the requested state until the GF100_PROFILER object is freed or + * the NV90CC_CTRL_CMD_POWER_RELEASE_FEATURES command is called for that + * feature. + * + * Currently, only GF100_PROFILER requests for power features using this + * command are reference counted. Changes to the power feature settings made + * either by other control commands or the RM itself may interfere with the + * settings requested by GF100_PROFILER instances. + * + * This command will always return NV_OK when given valid + * parameters. If there is any other failure that prevents the clock-gating + * features from being set appropriately, the globalStatus parameter will + * indicate this and the statusMask parameter will indicate which clock-gating + * feature requests failed and why. + * + * controlMask + * This parameter indicates which clock-gating features the request should + * apply to. This parameter has the following fields: + * NV90CC_CTRL_POWER_FEATURE_MASK_ELCG + * The value of this field indicates whether this request should apply + * to engine-level clock-gating of the GR engine. Valid values for + * this field are: + * NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE + * This value indicates that the GR engine-level clock-gating + * should be ignored. This will not affect the reference count for + * this feature. + * NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_DISABLE + * This value indicates that the GR engine-level clock-gating + * should be disabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_ENABLE + * This value indicates that the GR engine-level clock-gating + * should be enabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_BLCG + * The value of this field indicates whether this request should apply + * to block-level clock-gating. Valid values for this field are: + * NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE + * This value indicates that block-level clock-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_DISABLE + * This value indicates that block-level clock-gating should be + * disabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_ENABLE + * This value indicates that block-level clock-gating should be + * enabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_SLCG + * The value of this field indicates whether this request should apply + * to second-level clock-gating. Valid values for this field are: + * NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE + * This value indicates that second-level clock-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_DISABLE + * This value indicates that second-level clock-gating should be + * disabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_ENABLE + * This value indicates that second-level clock-gating should be + * enabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_ELPG + * The value of this field indicates whether this request should apply + * to GR engine-level power-gating. Valid values for this field are: + * NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE + * This value indicates that engine-level power-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_DISABLE + * This value indicates that engine-level power-gating should be + * disabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_ENABLE + * This value indicates that engine-level power-gating should be + * enabled. + * Note that this field is only temporary to allow reference counting + * restricted to GF100_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN + * The value of this field indicates whether this request should apply + * to SM idle slowdown. Valid values for this field are: + * NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE + * This value indicates that SM idle slowdown should be ignored. + * This will not affect the reference count for this feature. + * NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_DISABLE + * This value indicates that SM idle slowdown should be disabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_ENABLE + * This value indicates that SM idle slowdown should be enabled. + * Note that this field is only temporary to allow reference counting + * restricted to GF100_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * NV90CC_CTRL_POWER_FEATURE_MASK_VAT + * The value of this field indicates whether this request should apply + * to VAT. Valid values for this field are: + * NV90CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE + * This value indicates that VAT should be ignored. + * This will not affect the reference count for this feature. + * NV90CC_CTRL_POWER_FEATURE_MASK_VAT_DISABLE + * This value indicates that VAT should be disabled. + * NV90CC_CTRL_POWER_FEATURE_MASK_VAT_ENABLE + * This value indicates that VAT should be enabled. + * Note that this field is only temporary to allow reference counting + * restricted to GF100_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * globalStatus + * This parameter returns the overall status of the requests for all + * clock-gating controls. If the value of this parameter is not + * NV_OK, none of the clock-gating controls will be set as + * requested. Possible values for this parameter are: + * NV_OK + * This value indicates that all of the clock-gating control requests + * were either fulfilled or not supported on the hardware. + * NV_ERR_INVALID_REQUEST + * This value indicates that at least one of the clock-gating control + * requests were invalid given the GF100_PROFILER instance's + * outstanding requests. + * NV_ERR_STATE_IN_USE + * This value indicates that at least one of the clock-gating controls + * has already been locked to a conflicting state by another + * GF100_PROFILER instance or the RM itself. + * statusMask + * This parameter returns the status of the request to set each clock- + * gating control specified by the controlMask parameter. The fields are + * identical to those of the controlMask parameter. For each field for + * which the corresponding field in the controlMask parameter has the + * value NV90CC_CTRL_POWER_FEATURE_MASK_*_IGNORE, the value is + * undefined. For each field for which the corresponding field in the + * controlMask parameter has the value + * NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST, the value will be + * one of the following: + * NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_FULFILLED + * This value indicates that the clock-gating feature corresponding to + * the field in question was enabled or disabled according to the + * controlMask parameter, and the reference count for the feature was + * incremented accordingly. + * NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_REJECTED + * This value indicates that the clock-gating feature corresponding to + * the field in question was not set to the expected state according + * to the controlMask parameter because another conflicting request is + * currently outstanding for the clock-gating feature. + * NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_FAILED + * This value indicates that the clock-gating feature corresponding to + * the field in question was not set to the expected state according + * to the controlMask parameter because the attempt to do so failed + * with an error other than a conflicting request. + * NV90CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_NOT_SUPPORTED + * This value indicates that the clock-gating feature corresponding to + * the field in question is not supported on this GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES (0x90cc0301) /* finn: Evaluated from "(FINN_GF100_PROFILER_POWER_INTERFACE_ID << 8) | NV90CC_CTRL_POWER_REQUEST_FEATURES_PARAMS_MESSAGE_ID" */ + +#define NV90CC_CTRL_POWER_REQUEST_FEATURES_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV90CC_CTRL_POWER_REQUEST_FEATURES_PARAMS { + NvU32 globalStatus; + NvU32 controlMask; + NvU32 statusMask; +} NV90CC_CTRL_POWER_REQUEST_FEATURES_PARAMS; + +/* valid fields for the controlMask and statusMask parameters */ +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG 1:0 +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG 3:2 +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG 5:4 + +/* + * The following are temporary fields for the controlMask and statusMask + * parameters. They are required to reference count their respective features + * until the existing RM controls can be safely updated, and the definitions + * for these features will be removed soon after that. + */ +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG 7:6 +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN 9:8 +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT 11:10 + +/* valid values for fields in the controlMask parameter */ +#define NV90CC_CTRL_POWER_FEATURE_IGNORE (0x00000000) +#define NV90CC_CTRL_POWER_FEATURE_DISABLE (0x00000001) +#define NV90CC_CTRL_POWER_FEATURE_ENABLE (0x00000002) + +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE NV90CC_CTRL_POWER_FEATURE_IGNORE +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_DISABLE NV90CC_CTRL_POWER_FEATURE_DISABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_ENABLE NV90CC_CTRL_POWER_FEATURE_ENABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE NV90CC_CTRL_POWER_FEATURE_IGNORE +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_DISABLE NV90CC_CTRL_POWER_FEATURE_DISABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_ENABLE NV90CC_CTRL_POWER_FEATURE_ENABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE NV90CC_CTRL_POWER_FEATURE_IGNORE +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_DISABLE NV90CC_CTRL_POWER_FEATURE_DISABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_ENABLE NV90CC_CTRL_POWER_FEATURE_ENABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE NV90CC_CTRL_POWER_FEATURE_IGNORE +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_DISABLE NV90CC_CTRL_POWER_FEATURE_DISABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_ENABLE NV90CC_CTRL_POWER_FEATURE_ENABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE NV90CC_CTRL_POWER_FEATURE_IGNORE +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_DISABLE NV90CC_CTRL_POWER_FEATURE_DISABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_ENABLE NV90CC_CTRL_POWER_FEATURE_ENABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE NV90CC_CTRL_POWER_FEATURE_IGNORE +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_DISABLE NV90CC_CTRL_POWER_FEATURE_DISABLE +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_ENABLE NV90CC_CTRL_POWER_FEATURE_ENABLE +/* possible values for fields in the statusMask parameter */ +#define NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED (0x00000000) +#define NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED (0x00000001) +#define NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED (0x00000002) +#define NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED (0x00000003) + +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_FULFILLED NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_REJECTED NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_NOT_SUPPORTED NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_FAILED NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_FULFILLED NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_REJECTED NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_NOT_SUPPORTED NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_FAILED NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_FULFILLED NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_REJECTED NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_NOT_SUPPORTED NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_FAILED NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_FULFILLED NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_REJECTED NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_NOT_SUPPORTED NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_FAILED NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_FULFILLED NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_REJECTED NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_NOT_SUPPORTED NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_FAILED NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_FULFILLED NV90CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_REJECTED NV90CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_NOT_SUPPORTED NV90CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_FAILED NV90CC_CTRL_POWER_FEATURE_REQUEST_FAILED + +/* utility masks for the controlMask parameter for all controls */ +#define NV90CC_CTRL_POWER_FEATURE_MASK_ALL \ + DRF_SHIFTMASK(NV90CC_CTRL_POWER_FEATURE_MASK_ELCG) | \ + DRF_SHIFTMASK(NV90CC_CTRL_POWER_FEATURE_MASK_BLCG) | \ + DRF_SHIFTMASK(NV90CC_CTRL_POWER_FEATURE_MASK_SLCG) | \ + DRF_SHIFTMASK(NV90CC_CTRL_POWER_FEATURE_MASK_ELPG) | \ + DRF_SHIFTMASK(NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN) | \ + DRF_SHIFTMASK(NV90CC_CTRL_POWER_FEATURE_MASK_VAT) +#define NV90CC_CTRL_POWER_FEATURE_MASK_ALL_IGNORE \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _IGNORE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _VAT, _IGNORE) +#define NV90CC_CTRL_POWER_FEATURE_MASK_ALL_DISABLE \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _DISABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _DISABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _DISABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _DISABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _DISABLE)| \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _VAT, _DISABLE) +#define NV90CC_CTRL_POWER_FEATURE_MASK_ALL_ENABLE \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _ENABLE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _VAT, _ENABLE) + +/* + * NV90CC_CTRL_CMD_POWER_RELEASE_FEATUERS + * + * This command releases the GF100_PROFILER's request for the given clock- + * gating features that was previously created by the + * NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES command. If the GF100_PROFILER + * object does not have an outstanding request to one or more of the given + * clock-gating features, those features will be ignored while the other + * feature requests will be released. + * + * After calling this command, the calling client may not rely on the current + * value of any of the released clock-gating features to remain, even if + * several identical requests for the given clock-gating features were made + * using NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES. The RM only reference- + * counts the settings requested by GF100_PROFILER instances - it does not + * reference-count multiple identical requests made using the same + * GF100_PROFILER instance. + * + * All outstanding requests made using this GF100_PROFILER object are + * implicitly released when the GF100_PROFILER is freed. + * + * controlMask + * This parameter indicates which clock-gating features the RM should + * release the GF100_PROFILER's reference to. See + * NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES for valid fields. Valid + * values for each field are: + * NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE + * NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE + * NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE + * NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE + * NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE + * NV90CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE + * This value indicates that the clock-gating feature associated with + * the field should not be released, even if the GF100_PROFILER has an + * outstanding request for it. This will not affect the reference + * count for the feature. + * NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_RELEASE + * NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_RELEASE + * NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_RELEASE + * NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_RELEASE + * NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_RELEASE + * NV90CC_CTRL_POWER_FEATURE_MASK_VAT_RELEASE + * This value indicates that the GF100_PROFILER's outstanding request + * for the clock-gating feature associated with the field should be + * released. This will decrement the reference count for the feature + * if the GF100_PROFILER has an outstanding request for it. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV90CC_CTRL_CMD_POWER_RELEASE_FEATURES (0x90cc0302) /* finn: Evaluated from "(FINN_GF100_PROFILER_POWER_INTERFACE_ID << 8) | NV90CC_CTRL_POWER_RELEASE_FEATURES_PARAMS_MESSAGE_ID" */ + +#define NV90CC_CTRL_POWER_RELEASE_FEATURES_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV90CC_CTRL_POWER_RELEASE_FEATURES_PARAMS { + NvU32 controlMask; +} NV90CC_CTRL_POWER_RELEASE_FEATURES_PARAMS; + +/* + * valid values for the controlMask parameter in addition to + * NV90CC_CTRL_POWER_FEATURE_MASK_*_IGNORE + */ +#define NV90CC_CTRL_POWER_FEATURE_RELEASE (0x00000003) + +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELCG_RELEASE NV90CC_CTRL_POWER_FEATURE_RELEASE +#define NV90CC_CTRL_POWER_FEATURE_MASK_BLCG_RELEASE NV90CC_CTRL_POWER_FEATURE_RELEASE +#define NV90CC_CTRL_POWER_FEATURE_MASK_SLCG_RELEASE NV90CC_CTRL_POWER_FEATURE_RELEASE +#define NV90CC_CTRL_POWER_FEATURE_MASK_ELPG_RELEASE NV90CC_CTRL_POWER_FEATURE_RELEASE +#define NV90CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_RELEASE NV90CC_CTRL_POWER_FEATURE_RELEASE +#define NV90CC_CTRL_POWER_FEATURE_MASK_VAT_RELEASE NV90CC_CTRL_POWER_FEATURE_RELEASE + + +/* _ctrl90ccpower_h_ */ + +/* utility mask for the controlMask parameter for all fields */ +#define NV90CC_CTRL_POWER_FEATURE_MASK_ALL_RELEASE \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _RELEASE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _RELEASE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _RELEASE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _RELEASE) | \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _RELEASE)| \ + DRF_DEF(90CC, _CTRL_POWER_FEATURE_MASK, _VAT, _RELEASE) diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cd.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cd.h new file mode 100644 index 0000000..29449ab --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90cd.h @@ -0,0 +1,174 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90cd.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV_EVENT_BUFFER control commands and parameters */ + +#define NV_EVENT_BUFFER_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x90CD, NV90CD_CTRL_##cat, idx) + +#define NV90CD_CTRL_RESERVED (0x00) +#define NV90CD_CTRL_EVENT (0x01) + +/* +* NV_EVENT_BUFFER_CTRL_CMD_NULL +* +* This command does nothing. +* This command does not take any parameters. +* +* Possible status values returned are: +* NV_OK +*/ +#define NV_EVENT_BUFFER_CTRL_CMD_NULL (0x90cd0000) /* finn: Evaluated from "(FINN_NV_EVENT_BUFFER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* +* NV_EVENT_BUFFER_CTRL_CMD_ENABLE_EVENTS +* This interface enables all the events that are associated to the event buffer +*/ +#define NV_EVENT_BUFFER_CTRL_CMD_ENABLE_EVENTS (0x90cd0101) /* finn: Evaluated from "(FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID << 8) | 0x1" */ + +#define NV_EVENT_BUFFER_FLAG 0:32 + +/* +* NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY +* This flag defines the kernel behavior when the buffer is full +* +* DEFAULT/DISABLED: By default kernel doesn't assume any policy. To enable events +* an overflow policy has to be set to retain older or newer events +* +* KEEP_OLDEST: kernel would retain older events and drop newer events if the buffer is full +* +* KEEP_NEWEST: kernel would retain newer events and drop older events if the buffer is full +* +*/ +#define NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY 0:1 +#define NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY_DISABLED 0 +#define NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY_KEEP_OLDEST 1 +#define NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY_KEEP_NEWEST 2 +#define NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY_DEFAULT NV_EVENT_BUFFER_FLAG_OVERFLOW_POLICY_DISABLED + +/* +* NV_EVENT_BUFFER_CTRL_CMD_ENABLE_EVENTS_PARAMS +* +* enable [IN] +* This field is used to enable or disable events +* +* flags[IN] +* This field sets NV_EVENT_BUFFER_FLAG parameter used to configure event buffer overflow options +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_ARGUMENT +*/ +typedef struct NV_EVENT_BUFFER_CTRL_CMD_ENABLE_EVENTS_PARAMS { + NvBool enable; + NvU32 flags; +} NV_EVENT_BUFFER_CTRL_CMD_ENABLE_EVENTS_PARAMS; + +/* +* NV_EVENT_BUFFER_CTRL_CMD_UPDATE_GET +* This interface allows the user to update get pointers. +* This call is useful in the KEEP_OLDEST policy to update free space available in the buffer. +* In keep oldest policy, kernel adds new entries in the buffer only if there is free space. +* The full/empty decision is made as follows: +* - when GET==PUT, the fifo is empty +* - when GET==PUT+1, the fifo is full +*/ +#define NV_EVENT_BUFFER_CTRL_CMD_UPDATE_GET (0x90cd0102) /* finn: Evaluated from "(FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID << 8) | 0x2" */ + +/* +* NV_EVENT_BUFFER_CTRL_CMD_UPDATE_GET_PARAMS +* +* recordBufferGet [IN] +* Value to be used to update the get offset of record buffer +* +* varDataBufferGet[IN] +* This is the buffer offset up to which user has consumed the vardataBuffer +* +* Possible status values returned are: +* NV_OK +* NV_ERR_INVALID_ARGUMENT: if any of the get offsets is greater than respective bufferSize. +*/ +typedef struct NV_EVENT_BUFFER_CTRL_CMD_UPDATE_GET_PARAMS { + NvU32 recordBufferGet; + NvU32 varDataBufferGet; +} NV_EVENT_BUFFER_CTRL_CMD_UPDATE_GET_PARAMS; + +/* + * Send a test event-buffer notification (verification-only) + */ +#define NV_EVENT_BUFFER_CTRL_CMD_VERIF_NOTIFY (0x90cd0103) /* finn: Evaluated from "(FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID << 8) | 0x3" */ + +/* + * Synchronous flush + */ +#define NV_EVENT_BUFFER_CTRL_CMD_FLUSH (0x90cd0104) /* finn: Evaluated from "(FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID << 8) | 0x4" */ + +/* + * post event + */ +#define NV_EVENT_BUFFER_CTRL_CMD_POST_TELEMETRY_EVENT (0x90cd0105) /* finn: Evaluated from "(FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID << 8) | 0x5" */ + + /* + * NV_EVENT_BUFFER_CTRL_CMD_POST_TELEMETRY_EVENT_PARAMS + * + * eventType [IN] + * the NvTelemetry event type. + * typeVersion [IN] + * the version of the event structure + * eventData [IN] + * an array of 256 bytes used to hold the event data. + * eventDataSz [IN] + * the amount of valid data in the eventData buffer. + * varData [IN] + * an array of 256 bytes used to hold the var data. + * varDataSz [IN] + * the amount of valid data in the varData buffer. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +typedef struct NV_EVENT_BUFFER_CTRL_CMD_POST_TELEMETRY_EVENT_PARAMS { + NvU32 eventType; + NvU16 typeVersion; + NvU8 eventData[256]; + NvU16 eventDataSz; + NvU8 varData[256]; + NvU16 varDataSz; +} NV_EVENT_BUFFER_CTRL_CMD_POST_TELEMETRY_EVENT_PARAMS; + +/* _ctr l90cd_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90e6.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90e6.h new file mode 100644 index 0000000..ad1d9fb --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90e6.h @@ -0,0 +1,137 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90e6.finn +// + +#include "ctrl/ctrlxxxx.h" +#define NV90E6_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0x90E6, NV90E6_CTRL_##cat, idx) + + +/* NV90E6 command categories (6bits) */ +#define NV90E6_CTRL_RESERVED (0x00) +#define NV90E6_CTRL_MASTER (0x01) + + +/* + * NV90E6_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ + +#define NV90E6_CTRL_CMD_NULL (0x90e60000) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_MASTER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV90E6_CTRL_CMD_MASTER_GET_ERROR_INTR_OFFSET_MASK + * + * This command is used to query the offset and mask within the object mapping + * that can be used to query for ECC and NVLINK interrupts. + * + * If a read of the given offset+mask is non-zero then it is possible an ECC or + * an NVLINK error has been reported and not yet handled. If this is true then + * the caller must either wait until the read returns zero or call into the + * corresponding count reporting APIs to get updated counts. + * + * offset + * The offset into a GF100_SUBDEVICE_MASTSER's mapping where the top level + * interrupt register can be found. + * mask + * Compatibility field that contains the same bits as eccMask. This field is + * deprecated and will be removed. + * eccMask + * The mask to AND with the value found at offset to determine if any ECC + * interrupts are pending. + * nvlinkMask + * The mask to AND with the value found at offset to determine if any NVLINK + * interrupts are pending. + * + * Possible return status values are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV90E6_CTRL_CMD_MASTER_GET_ERROR_INTR_OFFSET_MASK (0x90e60101) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_MASTER_MASTER_INTERFACE_ID << 8) | NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS_MESSAGE_ID" */ + +#define NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS { + NvU32 offset; + NvU32 mask; // TODO: remove after all users have switched to use eccMask + NvU32 eccMask; + NvU32 nvlinkMask; +} NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS; + +// TODO: remove once users of this interface have switched to the new name. +#define NV90E6_CTRL_CMD_MASTER_GET_ECC_INTR_OFFSET_MASK NV90E6_CTRL_CMD_MASTER_GET_ERROR_INTR_OFFSET_MASK + +typedef NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS NV90E6_CTRL_MASTER_GET_ECC_INTR_OFFSET_MASK_PARAMS; + +/* + * NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK + * + * This command is used to query the mask within the fastpath register + * (VIRTUAL_FUNCTION_ERR_CONT) that can be used to query for ECC and NVLINK interrupts. + * + * If a read of the given mask is non-zero then it is possible an ECC or + * an NVLINK error has been reported and not yet handled. If this is true then + * the caller must either wait until the read returns zero or call into the + * corresponding count reporting APIs to get updated counts. + * + * [out] eccMask + * The mask to AND with the value found at offset to determine if any ECC + * interrupts are possibly pending. + * [out] nvlinkMask + * The mask to AND with the value found at offset to determine if any NVLINK + * interrupts are possibly pending. + * + * Possible return status values are + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK (0x90e60102) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_MASTER_MASTER_INTERFACE_ID << 8) | NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_MESSAGE_ID" */ + +#define NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS { + NvU32 eccMask; + NvU32 nvlinkMask; +} NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS; + +/* _ctrl90e6_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90ec.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90ec.h new file mode 100644 index 0000000..00094c1 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90ec.h @@ -0,0 +1,124 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90ec.finn +// + +#include "ctrl/ctrlxxxx.h" +/* GK104 HDACODEC control commands and parameters */ + +#define NV90EC_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x90EC, NV90EC_CTRL_##cat, idx) + +/* NV04_DISPLAY_COMMON command categories (6bits) */ +#define NV90EC_CTRL_RESERVED (0x00) +#define NV90EC_CTRL_HDACODEC (0x01) + +/* + * NV90EC_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV90EC_CTRL_CMD_NULL (0x90ec0000) /* finn: Evaluated from "(FINN_GF100_HDACODEC_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV90EC_CTRL_CMD_HDACODEC_SET_CP_READY_ENABLE + * + * This command sets the CP_READY bit. It basically informs RM whether + * the DD has worked upon the HDCP request requested by the Audio driver + * or not. DD asks RM to enable CP_READY bit (by setting CpReadyEnable to NV_TRUE) + * once it is done honouring/dishonouring the request. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId + * This parameter specifies the ID of the display for which the cp ready + * bit should be enabled. The display ID must a dfp display. + * If the displayId is not a dfp, this call will return + * NV_ERR_INVALID_ARGUMENT. + * CpReadyEnable + * This parameter specifies whether to enable (NV_TRUE) or not. If CpReady + * is enabled then AudioCodec can send more HDCP requests. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + * + */ +#define NV90EC_CTRL_CMD_HDACODEC_SET_CP_READY_ENABLE (0x90ec0101) /* finn: Evaluated from "(FINN_GF100_HDACODEC_HDACODEC_INTERFACE_ID << 8) | NV90EC_CTRL_CMD_HDACODEC_SET_CP_READY_ENABLE_PARAMS_MESSAGE_ID" */ + +#define NV90EC_CTRL_CMD_HDACODEC_SET_CP_READY_ENABLE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV90EC_CTRL_CMD_HDACODEC_SET_CP_READY_ENABLE_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bCpReadyEnable; +} NV90EC_CTRL_CMD_HDACODEC_SET_CP_READY_ENABLE_PARAMS; + +/* + * NV90EC_CTRL_CMD_HDACODEC_NOTIFY_AUDIO_EVENT + * + * This command notifies Audio of any events to audio + * like notification of PD bit being set. + * + * audioEvent + * This parameter specifies the event type. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + * + */ +#define NV90EC_CTRL_CMD_HDACODEC_NOTIFY_AUDIO_EVENT (0x90ec0102) /* finn: Evaluated from "(FINN_GF100_HDACODEC_HDACODEC_INTERFACE_ID << 8) | NV90EC_CTRL_HDACODEC_NOTIFY_AUDIO_EVENT_PARAMS_MESSAGE_ID" */ + +#define NV90EC_CTRL_HDACODEC_NOTIFY_AUDIO_EVENT_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV90EC_CTRL_HDACODEC_NOTIFY_AUDIO_EVENT_PARAMS { + NvU32 audioEvent; +} NV90EC_CTRL_HDACODEC_NOTIFY_AUDIO_EVENT_PARAMS; + +/* + * This command notifies audio driver that PD bit is set by DD, by writing to scratch register + */ +#define NV90EC_CTRL_HDACODEC_AUDIOEVENT_PD_BIT_SET (0x00000001) + +/* _ctrl90ec_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90f1.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90f1.h new file mode 100644 index 0000000..20d94dd --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrl90f1.h @@ -0,0 +1,309 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90f1.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "mmu_fmt_types.h" + +#define GMMU_FMT_MAX_LEVELS 6U + +/* Fermi+ GPU VASpace control commands and parameters */ +#define NV90F1_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x90F1, NV90F1_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NV90F1_CTRL_RESERVED (0x00U) +#define NV90F1_CTRL_VASPACE (0x01U) + +/*! + * Does nothing. + */ +#define NV90F1_CTRL_CMD_NULL (0x90f10000U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/*! + * Get VAS GPU MMU format. + */ +#define NV90F1_CTRL_CMD_VASPACE_GET_GMMU_FORMAT (0x90f10101U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS_MESSAGE_ID" */ + +#define NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS { + /*! + * [in] GPU sub-device handle - this API only supports unicast. + * Pass 0 to use subDeviceId instead. + */ + NvHandle hSubDevice; + + /*! + * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. + */ + NvU32 subDeviceId; + + /*! + * [out] GMMU format struct. This is of RM-internal type "struct GMMU_FMT*" + * which can only be accessed by kernel builds since this is a kernel + * only API. + */ + NV_DECLARE_ALIGNED(NvP64 pFmt, 8); +} NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS; + +/*! + * Get VAS page level information. + */ +#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO (0x90f10102U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | 0x2" */ + +typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS { + /*! + * [in] GPU sub-device handle - this API only supports unicast. + * Pass 0 to use subDeviceId instead. + */ + NvHandle hSubDevice; + + /*! + * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. + */ + NvU32 subDeviceId; + + /*! + * [in] GPU virtual address to query. + */ + NV_DECLARE_ALIGNED(NvU64 virtAddress, 8); + + /*! + * [in] Page size to query. + */ + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); + + /*! + * [out] Number of levels populated. + */ + NvU32 numLevels; + + /*! + * [out] Per-level information. + */ + struct { + /*! + * Format of this level. + */ + NV_DECLARE_ALIGNED(struct MMU_FMT_LEVEL *pFmt, 8); + + /*! + * Level/Sublevel Formats flattened + */ + NV_DECLARE_ALIGNED(MMU_FMT_LEVEL levelFmt, 8); + NV_DECLARE_ALIGNED(MMU_FMT_LEVEL sublevelFmt[MMU_FMT_MAX_SUB_LEVELS], 8); + + /*! + * Physical address of this page level instance. + */ + NV_DECLARE_ALIGNED(NvU64 physAddress, 8); + + /*! + * Aperture in which this page level instance resides. + */ + NvU32 aperture; + + /*! + * Size in bytes allocated for this level instance. + */ + NV_DECLARE_ALIGNED(NvU64 size, 8); + } levels[GMMU_FMT_MAX_LEVELS]; +} NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS; + +/*! + * Reserve (allocate and bind) page directory/table entries up to + * a given level of the MMU format. Also referred to as "lock-down". + * + * Each range that has been reserved must be released + * eventually with @ref NV90F1_CTRL_CMD_VASPACE_RELEASE_ENTRIES. + * A particular VA range and level (page size) combination may only be + * locked down once at a given time, but each level is independent. + */ +#define NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES (0x90f10103U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID" */ + +#define NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS { + /*! + * [in] GPU sub-device handle - this API only supports unicast. + * Pass 0 to use subDeviceId instead. + */ + NvHandle hSubDevice; + + /*! + * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. + */ + NvU32 subDeviceId; + + /*! + * [in] Page size (VA coverage) of the level to reserve. + * This need not be a leaf (page table) page size - it can be + * the coverage of an arbitrary level (including root page directory). + */ + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); + + /*! + * [in] First GPU virtual address of the range to reserve. + * This must be aligned to pageSize. + */ + NV_DECLARE_ALIGNED(NvU64 virtAddrLo, 8); + + /*! + * [in] Last GPU virtual address of the range to reserve. + * This (+1) must be aligned to pageSize. + */ + NV_DECLARE_ALIGNED(NvU64 virtAddrHi, 8); +} NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS; + +/*! + * Release (unbind and free) page directory/table entries up to + * a given level of the MMU format that has been reserved through a call to + * @ref NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES. Also referred to as "unlock". + */ +#define NV90F1_CTRL_CMD_VASPACE_RELEASE_ENTRIES (0x90f10104U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_MESSAGE_ID" */ + +#define NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS { + /*! + * [in] GPU sub-device handle - this API only supports unicast. + * Pass 0 to use subDeviceId instead. + */ + NvHandle hSubDevice; + + /*! + * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. + */ + NvU32 subDeviceId; + + /*! + * [in] Page size (VA coverage) of the level to release. + * This need not be a leaf (page table) page size - it can be + * the coverage of an arbitrary level (including root page directory). + */ + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); + + /*! + * [in] First GPU virtual address of the range to release. + * This must be aligned to pageSize. + */ + NV_DECLARE_ALIGNED(NvU64 virtAddrLo, 8); + + /*! + * [in] Last GPU virtual address of the range to release. + * This (+1) must be aligned to pageSize. + */ + NV_DECLARE_ALIGNED(NvU64 virtAddrHi, 8); +} NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS; + +/*! + * Get VAS page level information without kernel priviledge. This will internally call + * NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO. + */ +#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO_VERIF (0x90f10105U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | 0x5" */ + +/*! + * Pin PDEs for a given VA range on the server RM and then mirror the client's page + * directory/tables in the server. + * + * @ref + */ +#define NV90F1_CTRL_CMD_VASPACE_COPY_SERVER_RESERVED_PDES (0x90f10106U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID" */ + +#define NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS { + /*! + * [in] GPU sub-device handle - this API only supports unicast. + * Pass 0 to use subDeviceId instead. + */ + NvHandle hSubDevice; + + /*! + * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. + */ + NvU32 subDeviceId; + + /*! + * [in] Page size (VA coverage) of the level to reserve. + * This need not be a leaf (page table) page size - it can be + * the coverage of an arbitrary level (including root page directory). + */ + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); + + /*! + * [in] First GPU virtual address of the range to reserve. + * This must be aligned to pageSize. + */ + NV_DECLARE_ALIGNED(NvU64 virtAddrLo, 8); + + /*! + * [in] Last GPU virtual address of the range to reserve. + * This (+1) must be aligned to pageSize. + */ + NV_DECLARE_ALIGNED(NvU64 virtAddrHi, 8); + + /*! + * [in] Number of PDE levels to copy. + */ + NvU32 numLevelsToCopy; + + /*! + * [in] Per-level information. + */ + struct { + /*! + * Physical address of this page level instance. + */ + NV_DECLARE_ALIGNED(NvU64 physAddress, 8); + + /*! + * Size in bytes allocated for this level instance. + */ + NV_DECLARE_ALIGNED(NvU64 size, 8); + + /*! + * Aperture in which this page level instance resides. + */ + NvU32 aperture; + + /*! + * Page shift corresponding to the level + */ + NvU8 pageShift; + } levels[GMMU_FMT_MAX_LEVELS]; +} NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS; + +/* _ctrl90f1_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06c.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06c.h new file mode 100644 index 0000000..775ce94 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06c.h @@ -0,0 +1,421 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla06c.finn +// + + + + +/* + * KEPLER_CHANNEL_GROUP_A control commands and parameters + * + * A channel group is a collection of channels which are executed in a specific + * order by hardware. Hardware will not move from one channel in the group + * until it is finished executing all its work or gives up control to the next + * channel. + * + * Channels are added to the group by allocating them as a child of the + * KEPLER_CHANNEL_GROUP_A object. + * + * A channel in a channel group may be restricted with respect to what objects + * can be allocated on it and what APIs are allowed to operate on the channel. + * For more details on specifics of how groups behave see the Software and + * Hardware documetation for the specific architecture in which you are + * interested. + * + */ + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrla06f.h" /* A06C is partially derived from A06F */ + +#include "ctrl/ctrl2080/ctrl2080internal.h" /* For NV2080_CTRL_INTERNAL_MEMDESC_INFO */ +#include "ctrl/ctrlc36f.h" /* For NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES */ + +#define NVA06C_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xA06C, NVA06C_CTRL_##cat, idx) + +/* KEPLER_CHANNEL_GROUP_A command categories (6bits) */ +#define NVA06C_CTRL_RESERVED (0x00) +#define NVA06C_CTRL_GPFIFO (0x01) +#define NVA06C_CTRL_INTERNAL (0x02) + +/* + * NVA06C_CTRL_CMD_NULL + * + * Please see description of NV906D_CTRL_CMD_NULL. + * + */ +#define NVA06C_CTRL_CMD_NULL (0xa06c0000) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NVA06C_CTRL_CMD_GPFIFO_SCHEDULE + * + * This command schedules a channel group in hardware. This command should be + * called after objects have been allocated on the channel or a call to + * NVA06C_CTRL_CMD_BIND has been made. + * + * See NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for parameter definitions. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_OPERATION + * + */ +#define NVA06C_CTRL_CMD_GPFIFO_SCHEDULE (0xa06c0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */ +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA06C_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA06C_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS { + NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS params; +} NVA06C_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS; + + + + +/* + * NVA06C_CTRL_CMD_BIND + * + * This command uses the given engine to configure the group for scheduling. + * It alleviates the need to call NVA06C_CTRL_CMD_GPFIFO_SCHEDULE after objects + * have been allocated. However, it requires that the caller know which engine + * they want to be able to execute in the group. Once this has been called + * only objects that can be allocated on the specified engine or other engines + * allowed to coexist in the group will be allowed. See + * NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST to determine which engines can + * share a parent. + * + * See NVA06F_CTRL_CMD_BIND for parameter definitions. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06C_CTRL_CMD_BIND (0xa06c0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_BIND_PARAMS_MESSAGE_ID" */ + +#define NVA06C_CTRL_BIND_PARAMS_MESSAGE_ID (0x2U) + +typedef NVA06F_CTRL_BIND_PARAMS NVA06C_CTRL_BIND_PARAMS; + +/* + * NVA06C_CTRL_CMD_SET_TIMESLICE + * + * This command modifies the timeslice for a channel group. Hardware may not + * support all possible values, so the input will be rounded down to a valid + * hardware value. + * + * This takes effect immediately, meaning the channel may be forced off of the + * GPU so the change can be made. + * + * timesliceUs + * This parameter is an input containing the desired timeslice in microseconds + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06C_CTRL_CMD_SET_TIMESLICE (0xa06c0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */ + +/* + * NVA06C_CTRL_CMD_GET_TIMESLICE + * + * This command returns the timeslice for a channel group. If + * NVA06C_CTRL_CMD_SET_TIMESLICE has been used this call will return the exact + * value passed to that function, which may not be exactly what is programmed + * to hardware (see NVA06C_CTRL_CMD_SET_TIMESLICE for more details). + * + * timesliceUs + * This parameter is an output containing current timeslice in microseconds. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06C_CTRL_CMD_GET_TIMESLICE (0xa06c0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */ + +typedef struct NVA06C_CTRL_TIMESLICE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 timesliceUs, 8); +} NVA06C_CTRL_TIMESLICE_PARAMS; + +/* + * NVA06C_CTRL_CMD_PREEMPT + * + * This command preempts a channel group. It optionally waits for the preempt to + * complete before returning. + * + * bWait + * If bWait evaluates to NV_TRUE then this control call waits till the preempt + * completes, else it returns immediately after issuing the preempt. Calling + * this control call multiple times with bWait = NV_FALSE without waiting for + * the preempt to complete by some other means can lead to undefined results. + * bManualTimeout + * If bManualTimer evaluates to NV_TRUE then timeoutUs will be used as the + * timeout value. + * timeoutUs + * The desired timeout in microseconds. Only used if bManualTimeout evaluates + * to NV_TRUE. The maximum value of timeoutUs is + * NVA06C_CTRL_CMD_PREEMPT_MAX_MANUAL_TIMEOUT_US. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + * + */ +#define NVA06C_CTRL_CMD_PREEMPT (0xa06c0105) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_PREEMPT_PARAMS_MESSAGE_ID" */ + +#define NVA06C_CTRL_PREEMPT_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVA06C_CTRL_PREEMPT_PARAMS { + NvBool bWait; + NvBool bManualTimeout; + NvU32 timeoutUs; +} NVA06C_CTRL_PREEMPT_PARAMS; + +#define NVA06C_CTRL_CMD_PREEMPT_MAX_MANUAL_TIMEOUT_US (1000000) // 1 second + +/* + * NVA06C_CTRL_CMD_GET_INFO + * + * This command returns information about the channel group. + * + * tsgID + * Output parameter containing the hardware TSG ID for this channel group. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NVA06C_CTRL_CMD_GET_INFO (0xa06c0106) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NVA06C_CTRL_GET_INFO_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NVA06C_CTRL_GET_INFO_PARAMS { + NvU32 tsgID; +} NVA06C_CTRL_GET_INFO_PARAMS; + +/* + * NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL + * + * Used to change the target TSG's interleave level in the runlist. The + * interleave level indicates how often channels in the TSG appear in the + * runlist according to the following policy: + * + * - LOW: Appear once + * - MEDIUM: If L > 0, appear L times + * Else, appear once + * - HIGH: If L > 0, appear (M + 1) * L times + * Else if M > 0, appear M times + * Else, appear once + * where + * - L = # of LOW interleave level TSGs + * - M = # of MEDIUM interleave level TSGs + * + * For safety reasons, setting this property requires PRIVILEGED user level. + * + * tsgInterleaveLevel + * Input parameter. One of: + * - NVA06C_CTRL_INTERLEAVE_LEVEL_LOW + * - NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM + * - NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +#define NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL (0xa06c0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */ + +/* + * NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL + * + * Returns the target TSG's interleave level. + * + * tsgInterleaveLevel + * Output parameter. One of: + * - NVA06C_CTRL_INTERLEAVE_LEVEL_LOW + * - NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM + * - NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL (0xa06c0108) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x8" */ + +typedef struct NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS { + NvU32 tsgInterleaveLevel; +} NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS; + +#define NVA06C_CTRL_INTERLEAVE_LEVEL_LOW (0x00000000) +#define NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM (0x00000001) +#define NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH (0x00000002) + +/* + * NVA06C_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE + * This ctrl call is deprecated in favor of NV0090_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE. + * @see NV0090_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE + */ +#define NVA06C_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE (0xa06c0109) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS_MESSAGE_ID" */ + +typedef enum NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE { + NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_NONE = 0, + NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_64B = 1, + NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_128B = 2, +} NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE; + +typedef struct NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD { + NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE size; +} NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD; + +#define NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS { + NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD l1; + NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD t1; +} NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS; + +/*! + * NVA06C_CTRL_CMD_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS + * + * This control call is used to + * - set the fault method buffer addresses in vGpu host / GSP after the fault + * method buffers are allocated by vGpu guest / GSP_CLIENT during channel + * group allocation + * - destroy the method buffer memory descriptors during channel group free + * + * methodBufferMemdesc [input] + * Details about the memory allocated for method buffer for each runqueue. + * If the size of the memory region is zero, the descriptor will be destroyed. + * + * bar2Addr [input] + * CPU invisible BAR2 address that the method buffer is mapped to for each + * runqueue + * + * numValidEntries [input] + * The number of valid entries upto + * NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES actually filled in + * the control call parameters. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA06C_CTRL_CMD_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS (0xa06c010a) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8 | NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_MESSAGE_ID)" */ + +#define NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES (NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES) + +#define NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_MESSAGE_ID (0xaU) + +typedef struct NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS { + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MEMDESC_INFO methodBufferMemdesc[NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES], 8); + NV_DECLARE_ALIGNED(NvU64 bar2Addr[NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES], 8); + NvU32 numValidEntries; +} NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS; + +/* + * NVA06C_CTRL_CMD_MAKE_REALTIME + * + * Promote the specified TSG to realtime, or demote to non-realtime, + * depending on the given bRealtime parameter. A realtime TSG will have the + * highest interleave level when the scheduling policy is CHANNEL_INTERLEAVED, + * and will also precede any non-realtime channel/TSG in the order channels are + * added to the corresponding runlist. + * + * Whenever a realtime TSG is added to a runlist, all non-realtime channels/TSGs + * are made preemptible by setting a COMPUTE preemption mode to CTA. + * + * Preemption modes for realtime TSGs remain WFI. + * + * A client must then issue a NVA06F_CTRL_CMD_RESTART_RUNLIST control call when + * kicking off work on a realtime TSG to preempt non-realtime channels and + * restart the runlist such that the realtime TSG will start executing next. + * + * bRealtime + * Whether the TSG is to be promoted to/demoted from realtime. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAMETER + * NV_ERR_INVALID_OBJECT + * NV_ERR_INVALID_STATE + * NV_ERR_NOT_SUPPORTED + */ +#define NVA06C_CTRL_CMD_MAKE_REALTIME (0xa06c0110) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_MAKE_REALTIME_PARAMS_MESSAGE_ID" */ + +#define NVA06C_CTRL_MAKE_REALTIME_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NVA06C_CTRL_MAKE_REALTIME_PARAMS { + NvBool bRealtime; +} NVA06C_CTRL_MAKE_REALTIME_PARAMS; + + + +/* + * NVA06C_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE + * + * This command is an internal command sent from Kernel RM to Physical RM + * to schedule a channel group in hardware. + * + * Please see description of NVA06C_CTRL_CMD_GPFIFO_SCHEDULE for more information. + * + */ +#define NVA06C_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE (0xa06c0201) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID << 8) | 0x1" */ + +/* + * NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE + * + * This command is an internal command sent from Kernel RM to Physical RM + * to modify the timeslice for a channel group in hardware. + * + * Please see description of NVA06C_CTRL_CMD_SET_TIMESLICE for more information. + * + */ +#define NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE (0xa06c0202) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID << 8) | 0x2" */ + +/* _ctrla06c.h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f.h new file mode 100644 index 0000000..b768326 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f.h @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla06f.finn +// + + + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrla06f/ctrla06fbase.h" +#include "ctrl/ctrla06f/ctrla06fgpfifo.h" +#include "ctrl/ctrla06f/ctrla06fevent.h" +#include "ctrl/ctrla06f/ctrla06finternal.h" diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f/ctrla06fbase.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f/ctrla06fbase.h new file mode 100644 index 0000000..39c977a --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f/ctrla06fbase.h @@ -0,0 +1,60 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla06f/ctrla06fbase.finn +// + + + + +/* GK100_GPFIFO control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl906f.h" /* A06F is partially derived from 906F */ + +#define NVA06F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xA06F, NVA06F_CTRL_##cat, idx) + +/* GK100_GPFIFO command categories (6bits) */ +#define NVA06F_CTRL_RESERVED (0x00) +#define NVA06F_CTRL_GPFIFO (0x01) +#define NVA06F_CTRL_EVENT (0x02) +#define NVA06F_CTRL_INTERNAL (0x03) + +/* + * NVA06F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + * + */ +#define NVA06F_CTRL_CMD_NULL (0xa06f0000) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/* _ctrla06fbase_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f/ctrla06fevent.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f/ctrla06fevent.h new file mode 100644 index 0000000..245673b --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f/ctrla06fevent.h @@ -0,0 +1,92 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla06f/ctrla06fevent.finn +// + +#include "ctrl/ctrla06f/ctrla06fbase.h" + +/* + * NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * This command sets event notification state for the associated channel. + * This command requires that an instance of NV01_EVENT has been previously + * bound to the associated channel object. + * + * event + * This parameter specifies the type of event to which the specified + * action is to be applied. This parameter must specify a valid + * NVA06F_NOTIFIERS value (see cla06f.h for more details) and should + * not exceed one less NVA06F_NOTIFIERS_MAXCOUNT. + * action + * This parameter specifies the desired event notification action. + * Valid notification actions include: + * NVA06F_CTRL_SET_EVENT_NOTIFICATION_ACTION_DISABLE + * This action disables event notification for the specified + * event for the associated channel object. + * NVA06F_CTRL_SET_EVENT_NOTIFICATION_ACTION_SINGLE + * This action enables single-shot event notification for the + * specified event for the associated channel object. + * NVA06F_CTRL_SET_EVENT_NOTIFICATION_ACTION_REPEAT + * This action enables repeated event notification for the specified + * event for the associated channel object. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa06f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS { + NvU32 event; + NvU32 action; +} NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001) +#define NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002) + +/* + * NVA06F_CTRL_CMD_EVENT_SET_TRIGGER + * + * This command triggers a software event for the associated channel. + * This command accepts no parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVA06F_CTRL_CMD_EVENT_SET_TRIGGER (0xa06f0206) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */ + + +/* _ctrla06fevent_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h new file mode 100644 index 0000000..699e6c6 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h @@ -0,0 +1,288 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla06f/ctrla06fgpfifo.finn +// + +#include "ctrl/ctrla06f/ctrla06fbase.h" + +/* + * NVA06F_CTRL_GET_CLASS_ENGINEID + * + * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. + * + */ +#define NVA06F_CTRL_GET_CLASS_ENGINEID (0xa06f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */ + +typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS { + NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS params; +} NVA06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS; + + + +/* + * NVA06F_CTRL_RESET_CHANNEL + * + * Please see description of NV906F_CTRL_RESET_CHANNEL for more information. + */ +#define NVA06F_CTRL_CMD_RESET_CHANNEL (0xa06f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */ + +typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVA06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS { + NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS params; +} NVA06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS; + + + +/* + * NVA06F_CTRL_CMD_GPFIFO_SCHEDULE + * + * This command schedules a channel in hardware. This command should be called + * after objects have been allocated on the channel or a call to + * NVA06F_CTRL_CMD_BIND has been made. + * + * bEnable + * This parameter indicates whether or not the channel should be scheduled in hardware. + * When set, the channel will be enabled in addition to being added to the appropriate runlist. + * When not set, the channel will be disabled and removed from runlist. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_OPERATION + * + */ +#define NVA06F_CTRL_CMD_GPFIFO_SCHEDULE (0xa06f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */ +#define NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS { + NvBool bEnable; + NvBool bSkipSubmit; +} NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS; + +/* + * NVA06F_CTRL_CMD_BIND + * + * This command uses the given engine to configure the channel for scheduling. + * It alleviates the need to call NVA06F_CTRL_CMD_GPFIFO_SCHEDULE after objects + * have been allocated. However, it requires that the caller know which engine + * they want to be able to execute on the channel. Once this has been called + * only objects that can be allocated on the specified engine or other engines + * allowed to coexist on the channel will be allowed. See + * NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST to determine which engines can + * share a parent. + * + * engineType + * This parameter specifies an NV2080_ENGINE_TYPE value indicating the + * engine to which this channel should be bound. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06F_CTRL_CMD_BIND (0xa06f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_BIND_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_BIND_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVA06F_CTRL_BIND_PARAMS { + NvU32 engineType; +} NVA06F_CTRL_BIND_PARAMS; + + + +/* + * NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO + * + * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. + * + */ +#define NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa06f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */ + +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA06F_CTRL_GET_MMU_FAULT_INFO_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS { + NV_DECLARE_ALIGNED(NVA06F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8); +} NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS; + + + +/* + * NVA06F_CTRL_CMD_SET_ERROR_NOTIFIER + * + * This command sets the channel error notifier of the target channel. + * bNotifyEachChannelInTSG + * When true, the error notifier will be set on every channel in + * the TSG that contains the channel. + * + * Possible status values returned are: + * NV_OK + */ +#define NVA06F_CTRL_CMD_SET_ERROR_NOTIFIER (0xa06f0108) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS { + NvBool bNotifyEachChannelInTSG; +} NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS; + +/* + * NVA06F_CTRL_CMD_SET_INTERLEAVE_LEVEL + * + * Symmetric to NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL, applied to the individual + * target channel. + * + * When belonging to a TSG, same interleave level will be set to every channel + * in the TSG. + * + * channelInterleaveLevel + * Input parameter. One of: + * - NVA06C_CTRL_INTERLEAVE_LEVEL_LOW + * - NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM + * - NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +#define NVA06F_CTRL_CMD_SET_INTERLEAVE_LEVEL (0xa06f0109) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x9" */ + +/* + * NVA06F_CTRL_CMD_GET_INTERLEAVE_LEVEL + * + * Returns the target channel's interleave level. + * + * channelInterleaveLevel + * Output parameter. One of: + * - NVA06C_CTRL_INTERLEAVE_LEVEL_LOW + * - NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM + * - NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06F_CTRL_CMD_GET_INTERLEAVE_LEVEL (0xa06f0110) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x10" */ + +typedef struct NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS { + NvU32 channelInterleaveLevel; +} NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS; + +/* + * NVA06F_CTRL_CMD_RESTART_RUNLIST + * + * This command expires the current timeslice and restarts the runlist the given + * channel belongs to. This effectively preempts the current channel on the + * corresponding engine. + * + * This is useful for clients to trigger preemption manually and reduce start + * latency for higher priority channels as they are added first to the runlist + * if NV0080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED policy is + * configured. + * + * This command interacts with the scheduler and may cause certain low priority + * channels to starve under certain circumstances. Therefore, it is only + * available to privileged clients. + * + * bForceRestart + * Input parameter. If NV_FALSE, the runlist restart will be skipped + * whenever the given channel (or its group) is already running on the + * corresponding engine. + * + * bBypassWait + * Input parameter. If NV_TRUE, the command will return immediately after + * issuing the hardware preemption request, without actually waiting for the + * context switch to complete. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06F_CTRL_CMD_RESTART_RUNLIST (0xa06f0111) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_RESTART_RUNLIST_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_RESTART_RUNLIST_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NVA06F_CTRL_RESTART_RUNLIST_PARAMS { + NvBool bForceRestart; + NvBool bBypassWait; +} NVA06F_CTRL_RESTART_RUNLIST_PARAMS; + +/* + * NVA06F_CTRL_CMD_STOP_CHANNEL + * + * This command is used to stop the channel + * + * Stopping the channel here means disabling and unbinding the channel and removing it from runlist. + * So, if the channel needs to run again, it has to be scheduled, bound and enabled again. + * If we fail to preempt channel or remove it from runlist, then we RC the channel. + * Also set an error notifier to notify user space that channel is stopped. + * + * bImmediate + * Input parameter. If NV_FALSE, we will wait for default RM timeout + * for channel to idle. If NV_TRUE, we don't wait for channel to idle. + * If channel is not idle, we forcefully preempt it off the runlist. + * If the preempt times out, we will RC the channel. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA06F_CTRL_CMD_STOP_CHANNEL (0xa06f0112) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_STOP_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_STOP_CHANNEL_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NVA06F_CTRL_STOP_CHANNEL_PARAMS { + NvBool bImmediate; +} NVA06F_CTRL_STOP_CHANNEL_PARAMS; + +/* _ctrla06fgpfifo_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h new file mode 100644 index 0000000..7a37815 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h @@ -0,0 +1,67 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla06f/ctrla06finternal.finn +// + +#include "ctrl/ctrla06f/ctrla06fbase.h" +#include "ctrl/ctrla06f/ctrla06fgpfifo.h" + +/* + * NVA06F_CTRL_CMD_INTERNAL_STOP_CHANNEL + * + * This command is an internal command sent from Kernel RM to Physical RM + * to stop the channel in hardware + * + * Please see description of NVA06F_CTRL_CMD_STOP_CHANNEL for more information. + * + */ +#define NVA06F_CTRL_CMD_INTERNAL_STOP_CHANNEL (0xa06f0301) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | 0x1" */ + +/* + * NVA06F_CTRL_CMD_INTERNAL_RESET_CHANNEL + * + * This command is an internal command sent from Kernel RM to Physical RM + * to perform the channel reset operations in hardware + * + * Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information. + * + */ +#define NVA06F_CTRL_CMD_INTERNAL_RESET_CHANNEL (0xa06f0302) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | 0x2" */ + +/* + * NVA06F_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE + * + * This command is an internal command sent from Kernel RM to Physical RM + * to schedule the channel in hardware + * + * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. + * + */ +#define NVA06F_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE (0xa06f0303) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | 0x3" */ + +/* ctrla06finternal_h */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla080.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla080.h new file mode 100644 index 0000000..b956ab9 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla080.h @@ -0,0 +1,658 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla080.finn +// + + + + + +/* + * NVA080_CTRL_CMD_VGPU_DISPLAY_SET_SURFACE_PROPERTIES + * + * This command sets primary surface properties on a virtual GPU in displayless mode + * + * Parameters: + * headIndex + * This parameter specifies the head for which surface properties are + * + * isPrimary + * This parameter indicates whether surface information is for primary surface. set to 1 if its a primary surface. + * + * hMemory + * Memory handle containing the surface (only for RM-managed heaps) + * + * offset + * Offset from base of allocation (hMemory for RM-managed heaps; physical + * memory otherwise) + * + * surfaceType + * This parameter indicates whether surface type is block linear or pitch + * + * surfaceBlockHeight + * This parameter indicates block height for the surface + * + * surfacePitch + * This parameter indicates pitch value for the surface + * + * surfaceFormat + * This parameter indicates surface format (A8R8G8B8/A1R5G5B5) + * + * surfaceWidth + * This parameter indicates width value for the surface + * + * surfaceHeight + * This parameter indicates height value for the surface + * + * surfaceSize + * This parameter indicates size of the surface + * + * surfaceKind + * This parameter indicates surface kind (only for externally-managed + * heaps) + * + * rectX [unused] + * This parameter indicates X coordinate of the region to be displayed + * + * rectY [unused] + * This parameter indicates Y coordinate of the region to be displayed + * + * rectWidth + * This parameter indicates width of the region to be displayed + * + * rectHeight + * This parameter indicates height of the region to be displayed + * + * hHwResDevice + * This parameter indicates the device associated with surface + * + * hHwResHandle + * This parameter indicates the handle to hardware resources allocated to surface + * + * effectiveFbPageSize + * This parameter indicates the actual page size used by KMD for the surface + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_NOT_SUPPORTED + */ + +#define NVA080_CTRL_CMD_VGPU_DISPLAY_SET_SURFACE_PROPERTIES (0xa0800103) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MESSAGE_ID" */ + +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MESSAGE_ID (0x3U) + +typedef struct NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES { + NvU32 headIndex; + NvU32 isPrimary; + NvU32 hMemory; + NvU32 offset; + NvU32 surfaceType; + NvU32 surfaceBlockHeight; + NvU32 surfacePitch; + NvU32 surfaceFormat; + NvU32 surfaceWidth; + NvU32 surfaceHeight; + NvU32 rectX; + NvU32 rectY; + NvU32 rectWidth; + NvU32 rectHeight; + NvU32 surfaceSize; + NvU32 surfaceKind; + NvU32 hHwResDevice; + NvU32 hHwResHandle; + NvU32 effectiveFbPageSize; +} NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES; + +/* valid surfaceType values */ +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MEMORY_LAYOUT 0:0 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MEMORY_LAYOUT_PITCH 0x00000001 +/* valid surfaceBlockHeight values */ +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +/* valid surfaceFormat values */ +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_I8 0x0000001E +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_RF16_GF16_BF16_AF16 0x000000CA +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A8R8G8B8 0x000000CF +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A2B10G10R10 0x000000D1 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_X2BL10GL10RL10_XRBIAS 0x00000022 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A8B8G8R8 0x000000D5 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_R5G6B5 0x000000E8 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A1R5G5B5 0x000000E9 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_R16_G16_B16_A16 0x000000C6 + +/* + * NVA080_CTRL_CMD_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS + * + * This command clears surface information related to head. + * It should be called while shutting down head in displayless mode on virtual GPU + * + * Parameters: + * headIndex + * This parameter specifies the head for which cleanup is requested. + * + * blankingEnabled + * This parameter must be set to 1 to enable blanking. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_NOT_SUPPORTED + */ +#define NVA080_CTRL_CMD_VGPU_DISPLAY_CLEANUP_SURFACE (0xa0800104) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS { + NvU32 headIndex; + NvU32 blankingEnabled; +} NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS; + +/* + * NVA080_CTRL_CMD_VGPU_DISPLAY_GET_POINTER_ADDRESS + * + * This command returns CPU virtual address of the mouse pointer mapping for VGPU. + * The address returned by this command is the pointer address for the head 0. + * VGPU_POINTER_OFFSET_HEAD(i) should be added to this address to get the address of head i. + * VGPU mouse pointer is a 32 bit value, X location of the mouse pointer is stored in + * 15:0 and Y location is stored in 31:16 bits. X location value of the mouse pointer is + * negative if bit 15 is set. Similarly, Y location value is negative if bit 31 is set. + * + * Parameters: + * pPointerAddress + * CPU virtual address of the mouse pointer mapping for VGPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_NOT_SUPPORTED + */ + +#define NVA080_CTRL_CMD_VGPU_DISPLAY_GET_POINTER_ADDRESS (0xa0800105) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pPointerAddress, 8); +} NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS; + +#define VGPU_POINTER_OFFSET_HEAD0_VALUE 0x00000000 +#define VGPU_POINTER_OFFSET_HEAD0_FLAG 0x00000004 +#define VGPU_POINTER_OFFSET_HEAD1_VALUE 0x00000008 +#define VGPU_POINTER_OFFSET_HEAD1_FLAG 0x0000000c +#define VGPU_POINTER_OFFSET_HEAD2_VALUE 0x00000010 +#define VGPU_POINTER_OFFSET_HEAD2_FLAG 0x00000014 +#define VGPU_POINTER_OFFSET_HEAD3_VALUE 0x00000018 +#define VGPU_POINTER_OFFSET_HEAD3_FLAG 0x0000001c +#define VGPU_POINTER_OFFSET_HEAD_VALUE(i) (i * 8) +#define VGPU_POINTER_OFFSET_HEAD_FLAG(i) (4 + i * 8) +#define VGPU_POINTER_OFFSET_HEAD_SIZE 4 + +/* + * NVA080_CTRL_CMD_GET_MAPPABLE_VIDEO_SIZE + * + * This command returns mappable video size to be used by each VM. + * + * Parameters: + * mappableVideoSize + * This parameter returns mappable video size in bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_NOT_SUPPORTED + */ + + +#define NV_VGPU_POINTER_X_LOCATION 15:0 +#define NV_VGPU_POINTER_Y_LOCATION 31:16 +#define NVA080_CTRL_CMD_GET_MAPPABLE_VIDEO_SIZE (0xa0800201) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 mappableVideoSize, 8); +} NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS; + +/* + * NVA080_CTRL_CMD_MAP_SEMA_MEM + * + * This command returns GPU VA for the channel with 'hCtxDma' handle + * where per VM semaphore memory is mapped which is used for tracking + * non-stall interrupt of each VM. + * + * Parameters: + * hClient [in] + * This parameter specifies the handle to the NV01_ROOT object of + * the client. This object should be the parent of the object + * specified by hDevice. + * hDevice [in] + * This parameter specifies the handle of the NV01_DEVICE object + * representing the desired GPU. + * hMemory [in] + * This parameter specifies the handle for semaphore memory + * hCtxDma [in] + * This parameter specifies the handle of the NV01_CONTEXT_DMA + * object through which bufferId is written in semaphore memory for + * non-stall interrupt tracking. + * semaAddress [out] + * This parameter returns the GPU virtual address of the semaphore + * memory. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INVALID_DATA + * NV_ERR_INVALID_CLIENT + * NV_ERR_INVALID_OBJECT_HANDLE + * + */ + +#define NVA080_CTRL_CMD_MAP_SEMA_MEM (0xa0800202) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | 0x2" */ + +typedef struct NVA080_CTRL_MAP_SEMA_MEM_PARAMS { + NvHandle hClient; + NvHandle hDevice; + NvHandle hMemory; + NvHandle hCtxDma; + NV_DECLARE_ALIGNED(NvU64 semaAddress, 8); +} NVA080_CTRL_MAP_SEMA_MEM_PARAMS; + +/* + * NVA080_CTRL_CMD_UNMAP_SEMA_MEM + * + * This command unmaps per VM semaphore memory from GPU VA space, mapped by + * NVA080_CTRL_CMD_MAP_SEMA_MEM command. + * + * Parameters: + * Same as NVA080_CTRL_MAP_SEMA_MEM_PARAMS, except semaAddress is input + * parameter here. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INVALID_DATA + * NV_ERR_INVALID_CLIENT + * NV_ERR_INVALID_OBJECT_HANDLE + * + */ + +#define NVA080_CTRL_CMD_UNMAP_SEMA_MEM (0xa0800203) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | 0x3" */ + +/*! + * NVA080_CTRL_CMD_SET_FB_USAGE + * + * This command sets the current framebuffer usage value in the plugin. + * + * Parameters: + * fbUsed [in] + * This parameter holds the current FB usage value in bytes. + * + * Possible status values returned are: + * NV_OK + */ +#define NVA080_CTRL_CMD_SET_FB_USAGE (0xa0800204) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVA080_CTRL_SET_FB_USAGE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); +} NVA080_CTRL_SET_FB_USAGE_PARAMS; + +/*! +* NVA080_CTRL_CMD_MAP_PER_ENGINE_SEMA_MEM +* +* This command allocates the per engine vGPU semaphore memory and map it to +* GPU/CPU VA. +* +* Calculate engine's semaphore GPU VA = +* semaAddress + semaStride * NV2080_ENGINE_TYPE_ of that engine +* +* Parameters: +* hClient [in] +* This parameter specifies the handle to the NV01_ROOT object of +* the client. This object should be the parent of the object +* specified by hDevice. +* hDevice [in] +* This parameter specifies the handle of the NV01_DEVICE object +* representing the desired GPU. +* hMemory [in] +* This parameter specifies the handle for semaphore memory +* hCtxDma [in] +* This parameter specifies the handle of the NV01_CONTEXT_DMA +* object through which bufferId is written in semaphore memory for +* non-stall interrupt tracking. +* semaAddress [out] +* This parameter returns the GPU VA of the per engine semaphore memory. +* semaStride [out] +* This parameter specifies the stride of each engine's semaphore offset within this memory. +* +* Possible status values returned are: +* NV_OK +*/ + +#define NVA080_CTRL_CMD_MAP_PER_ENGINE_SEMA_MEM (0xa0800205) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS { + NvU32 hClient; + NvU32 hDevice; + NvHandle hMemory; + NvU32 hCtxDma; + NV_DECLARE_ALIGNED(NvU64 semaAddress, 8); + NvU32 semaStride; +} NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS; + +/*! +* NVA080_CTRL_CMD_UNMAP_PER_ENGINE_SEMA_MEM +* +* This command unmaps and frees the per engine vGPU semaphore memory. +* +* Parameters: +* Same as NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS, except semaAddress is input +* parameter here. +* +* Possible status values returned are: +* NV_OK +*/ + +#define NVA080_CTRL_CMD_UNMAP_PER_ENGINE_SEMA_MEM (0xa0800206) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x6U) + +typedef NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS; + +/* + * NVA080_CTRL_CMD_UPDATE_SYSMEM_BITMAP + * + * This command provides the guest RM with PFN information, so that it can + * update the shared memory with the plugin, which keeps track of guest sysmem. + * + * Parameters: + * destPhysAddr + * Start address of the segment to be tracked + * + * pageCount + * Number of pages in the segment + * + * pageSize + * Size of pages in the segment + * + * isValid: + * TRUE : Set bits corresponding to PFNs in bitmap and increase segment refcount + * FALSE: Decrease segment refcount and then unset bits if refcount is 0 + * + * pfnList + * List of PFNs in the segment + * + * flags + * FLAGS_DST_PHYS_ADDR_BAR1_OFFSET + * Flag set to TRUE if pteMem is CPU VA pointing to BAR1 and + * dstPhysAddr contains BAR1 offset. + * + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + */ + +#define NVA080_CTRL_CMD_UPDATE_SYSMEM_BITMAP (0xa0800207) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_FLAGS_DST_PHYS_ADDR_BAR1_OFFSET 0:0 +#define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_FLAGS_DST_PHYS_ADDR_BAR1_OFFSET_FALSE (0x00000000) +#define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_FLAGS_DST_PHYS_ADDR_BAR1_OFFSET_TRUE (0x00000001) + +#define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS { + NV_DECLARE_ALIGNED(NvU64 destPhysAddr, 8); + NvU32 pageCount; + NvU32 pageSize; + NvBool isValid; + NV_DECLARE_ALIGNED(NvP64 pfnList, 8); + NvU32 flags; +} NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS; + +/* + * Blit semaphore offset location + */ +#define VGPU_BLIT_RESTORE_SEMA_MEM_OFFSET 0x200 +#define VGPU_BLIT_RESTORE_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_BLIT_RESTORE_SEMA_MEM_OFFSET) + +#define VGPU_BLIT_SEMA_MEM_OFFSET 0x400 +#define VGPU_BLIT_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_BLIT_SEMA_MEM_OFFSET) + +#define VGPU_FBMEMCE_PUSH_SEMA_MEM_OFFSET 0x800 +#define VGPU_FBMEMCE_PUSH_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_PUSH_SEMA_MEM_OFFSET) + +#define VGPU_FBMEMCE_SEMA_MEM_OFFSET 0x810 +#define VGPU_FBMEMCE_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_SEMA_MEM_OFFSET) + +#define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_LOWER_OFFSET 0x820 +#define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_LOWER_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_PIPELINED_SEMA_MEM_LOWER_OFFSET) + +#define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_UPPER_OFFSET 0x824 + +/* + * NVA080_CTRL_CMD_VGPU_GET_CONFIG + * + * This command returns VGPU configuration information for the associated GPU. + * + * Parameters: + * frameRateLimiter + * This parameter returns value of frame rate limiter + * swVSyncEnabled + * This parameter returns value of SW VSync flag (zero for disabled, + * non-zero for enabled) + * cudaEnabled + * This parameter returns whether CUDA is enabled or not + * pluginPteBlitEnabled + * This parameter returns whether to use plugin pte blit path + * disableWddm1xPreemption + * This parameter returns whether to disable WDDM 1.x Preemption or not + * debugBuffer + * This parameter specifies a pointer to memory which is filled with + * debugging information. + * debugBufferSize + * This parameter specifies the size of the debugging buffer in bytes. + * guestFbOffset + * This parameter returns FB offset start address for VM + * mappableCpuHostAperture + * This parameter returns mappable CPU host aperture size + * linuxInterruptOptimization + * This parameter returns whether stall interrupts are enabled/disabled for + * Linux VM + * vgpuDeviceCapsBits + * This parameter specifies CAP bits to ON/OFF features from guest OS. + * CAPS_SW_VSYNC_ENABLED + * cap bit to indicate if SW VSync flag enabled/disabled. + * Please note, currently, guest doesn't honour this bit. + * CAPS_CUDA_ENABLED + * cap bit to indicate if CUDA enabled/disabled. + * Please note, currently, guest doesn't honour this bit. + * CAPS_WDDM1_PREEMPTION_DISABLED + * cap bit to indicate if WDDM 1.x Preemption disabled/enabled. + * Please note, currently, guest doesn't honour this bit. + * CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED + * cap bit to indicate if stall interrupts are enabled/disabled for + * Linux VM. Please note, currently, guest doesn't honour this bit. + * CAPS_PTE_BLIT_ENABLED + * cap bit to indicate if PTE blit is enabled/disabled. + * Please note, currently, guest doesn't honour this bit. + * CAPS_PDE_BLIT_ENABLED + * cap bit to indicate if PDE blit is enabled/disabled. + * CAPS_GET_PDE_INFO_CTRL_DISABLED + * cap bit to indicate if GET_PDE_INFO RM Ctrl is disabled/enabled. + * CAPS_GUEST_FB_OFFSET_DISABLED + * cap bit to indicate if FB Offset is exposed to guest or not. + * If set, FB Offset is not exposed to guest. + * CAPS_CILP_DISABLED_ON_WDDM + * cap bit to indicate if CILP on WDDM disabled/enabled. + * CAPS_UPDATE_DOORBELL_TOKEN_ENABLED + * cap bit to indicate if guest needs to use doorbell token value updated + * dynamically by host after migration. + * CAPS_SRIOV_ENABLED + * Cap bit to indicate if the vGPU is running in SRIOV mode or not. + * CAPS_GUEST_MANAGED_VA_ENABLED + * Cap bit to indicate if the Guest is managing the VA. + * CAPS_VGPU_1TO1_COMPTAG_ENABLED + * Cap bit to indicate if the 1to1 comptag enabled. This is always TRUE + * when SR-IOV is enabled. + * CAPS_MBP_ENABLED + * Cap bit to indicate if the Mid Buffer Preemption enabled. + * CAPS_ASYNC_MBP_ENABLED + * Cap bit to indicate if the asynchronus Mid buffer Preemption enabled. + * CAPS_TLB_INVALIDATE_ENABLED + * Cap bit to indicate if the vGPU supports TLB Invalidation operation or not. + * CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED + * Cap bit to indicate if the vGPU supports PTE blit for page table updates using BAR1 + * CAPS_SRIOV_HEAVY_ENABLED + * Cap bit to indicate if vGPU is running in SRIOV Heavy mode or not. + * When set true SRIOV Heavy is enabled. + * When set false and CAPS_SRIOV_ENABLED is set true, SRIOV Standard is enabled. + * CAPS_TIMESLICE_OVERRIDE_ENABLED + * Cap bit to indicate whether TSG timeslice override is enabled or not. + * When set true, TSG timeslice override is enabled. + * When false, TSG timeslice override is disabled. + * uvmEnabledFeatures + * This parameter returns mask of UVM enabled features on vGPU. It comprises of + * UVM managed APIs and replayable faults that are enabled or disabled based on + * vGPU version. + * enableKmdSysmemScratch + * This parameter is used to overwrite guest regkey PreferSystemMemoryScratch. + * Setting vgpu parameter "vgpu_enable_kmd_sysmem_scratch" in plugin will + * set this parameter. If the parameter is set, guest moves shader buffer + * allocation from FB to sysmem. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_UPPER_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_PIPELINED_SEMA_MEM_UPPER_OFFSET) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG (0xa0800301) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_OTHERS_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED 0:0 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CUDA_ENABLED 1:1 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CUDA_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CUDA_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_WDDM1_PREEMPTION_DISABLED 2:2 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_WDDM1_PREEMPTION_DISABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_WDDM1_PREEMPTION_DISABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED 3:3 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_ENABLED 4:4 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PDE_BLIT_ENABLED 5:5 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PDE_BLIT_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PDE_BLIT_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GET_PDE_INFO_CTRL_DISABLED 6:6 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GET_PDE_INFO_CTRL_DISABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GET_PDE_INFO_CTRL_DISABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_FB_OFFSET_DISABLED 7:7 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_FB_OFFSET_DISABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_FB_OFFSET_DISABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CILP_DISABLED_ON_WDDM 8:8 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CILP_DISABLED_ON_WDDM_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CILP_DISABLED_ON_WDDM_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_SEMAPHORE_DISABLED 9:9 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_SEMAPHORE_DISABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_SEMAPHORE_DISABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_UPDATE_DOORBELL_TOKEN_ENABLED 10:10 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_UPDATE_DOORBELL_TOKEN_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_UPDATE_DOORBELL_TOKEN_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED 11:11 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_MANAGED_VA_ENABLED 12:12 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_MANAGED_VA_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_MANAGED_VA_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_1TO1_COMPTAG_ENABLED 13:13 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_1TO1_COMPTAG_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_1TO1_COMPTAG_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_MBP_ENABLED 14:14 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_MBP_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_MBP_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_ASYNC_MBP_ENABLED 15:15 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_ASYNC_MBP_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_ASYNC_MBP_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TLB_INVALIDATE_ENABLED 16:16 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TLB_INVALIDATE_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TLB_INVALIDATE_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED 17:17 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED 18:18 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED 19:19 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED 20:20 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED_TRUE (0x00000001) + +/* UVM supported features */ +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED 0:0 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_API_ENABLED 1:1 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_API_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_API_ENABLED_TRUE (0x00000001) + +#define NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA080_CTRL_VGPU_GET_CONFIG_PARAMS { + NvU32 frameRateLimiter; + NvU32 swVSyncEnabled; + NvU32 cudaEnabled; + NvU32 pluginPteBlitEnabled; + NvU32 disableWddm1xPreemption; + NvU32 debugBufferSize; + NV_DECLARE_ALIGNED(NvP64 debugBuffer, 8); + NV_DECLARE_ALIGNED(NvU64 guestFbOffset, 8); + NV_DECLARE_ALIGNED(NvU64 mappableCpuHostAperture, 8); + NvU32 linuxInterruptOptimization; + NvU32 vgpuDeviceCapsBits; + NvU32 maxPixels; + NvU32 uvmEnabledFeatures; + NvBool enableKmdSysmemScratch; +} NVA080_CTRL_VGPU_GET_CONFIG_PARAMS; + + + +/* _ctrla080_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla081.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla081.h new file mode 100644 index 0000000..35876db --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla081.h @@ -0,0 +1,716 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla081.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl2080/ctrl2080gpu.h" +#include "nv_vgpu_types.h" +/* NVA081_VGPU_CONFIG control commands and parameters */ + +#define NVA081_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xA081, NVA081_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NVA081_CTRL_RESERVED (0x00) +#define NVA081_CTRL_VGPU_CONFIG (0x01) + +#define NVA081_CTRL_VGPU_CONFIG_INVALID_TYPE 0x00 +#define NVA081_MAX_VGPU_TYPES_PER_PGPU 0x40 +#define NVA081_MAX_VGPU_PER_PGPU 32 +#define NVA081_VM_UUID_SIZE 16 +#define NVA081_VGPU_STRING_BUFFER_SIZE 32 +#define NVA081_VGPU_SIGNATURE_SIZE 128 +#define NVA081_VM_NAME_SIZE 128 +#define NVA081_PCI_CONFIG_SPACE_SIZE 0x100 +#define NVA081_PGPU_METADATA_STRING_SIZE 256 +#define NVA081_EXTRA_PARAMETERS_SIZE 1024 + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_SET_INFO + * + * This command sets the vGPU config information in RM + * + * Parameters: + * + * discardVgpuTypes [IN] + * This parameter specifies if existing vGPU configuration should be + * discarded for given pGPU + * + * vgpuInfo [IN] + * This parameter specifies virtual GPU type information + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_SET_INFO (0xa0810101) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NVA081_CTRL_VGPU_CONFIG_INFO + * + * This structure represents the per vGPU information + * + */ +typedef struct NVA081_CTRL_VGPU_INFO { + // This structure should be in sync with NVA082_CTRL_CMD_HOST_VGPU_DEVICE_GET_VGPU_TYPE_INFO_PARAMS + NvU32 vgpuType; + NvU8 vgpuName[NVA081_VGPU_STRING_BUFFER_SIZE]; + NvU8 vgpuClass[NVA081_VGPU_STRING_BUFFER_SIZE]; + NvU8 vgpuSignature[NVA081_VGPU_SIGNATURE_SIZE]; + NvU8 license[NV_GRID_LICENSE_INFO_MAX_LENGTH]; + NvU32 maxInstance; + NvU32 numHeads; + NvU32 maxResolutionX; + NvU32 maxResolutionY; + NvU32 maxPixels; + NvU32 frlConfig; + NvU32 cudaEnabled; + NvU32 eccSupported; + NvU32 gpuInstanceSize; + NvU32 multiVgpuSupported; + NV_DECLARE_ALIGNED(NvU64 vdevId, 8); + NV_DECLARE_ALIGNED(NvU64 pdevId, 8); + NV_DECLARE_ALIGNED(NvU64 profileSize, 8); + NV_DECLARE_ALIGNED(NvU64 fbLength, 8); + NV_DECLARE_ALIGNED(NvU64 gspHeapSize, 8); + NV_DECLARE_ALIGNED(NvU64 fbReservation, 8); + NV_DECLARE_ALIGNED(NvU64 mappableVideoSize, 8); + NvU32 encoderCapacity; + NV_DECLARE_ALIGNED(NvU64 bar1Length, 8); + NvU32 frlEnable; + NvU8 adapterName[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + NvU16 adapterName_Unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + NvU8 shortGpuNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + NvU8 licensedProductName[NV_GRID_LICENSE_INFO_MAX_LENGTH]; + NvU32 vgpuExtraParams[NVA081_EXTRA_PARAMETERS_SIZE]; + NvU32 ftraceEnable; + NvU32 gpuDirectSupported; + NvU32 nvlinkP2PSupported; + NvU32 multiVgpuExclusive; + NvU32 exclusiveType; + NvU32 exclusiveSize; + // used only by NVML + NvU32 gpuInstanceProfileId; +} NVA081_CTRL_VGPU_INFO; + +/* + * NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS + * + * This structure represents the vGPU configuration information + * + */ +#define NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS { + NvBool discardVgpuTypes; + NV_DECLARE_ALIGNED(NVA081_CTRL_VGPU_INFO vgpuInfo, 8); + NvU32 vgpuConfigState; +} NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS; + +/* VGPU Config state values */ +#define NVA081_CTRL_VGPU_CONFIG_STATE_UNINITIALIZED 0 +#define NVA081_CTRL_VGPU_CONFIG_STATE_IN_PROGRESS 1 +#define NVA081_CTRL_VGPU_CONFIG_STATE_READY 2 + +/* + * NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU + * + * This command enumerates list of vGPU guest instances per pGpu + * + * Parameters: + * + * vgpuType [OUT] + * This parameter specifies the virtual GPU type for this physical GPU + * + * numVgpu [OUT] + * This parameter specifies the number of virtual GPUs created on this physical GPU + * + * guestInstanceInfo [OUT] + * This parameter specifies an array containing guest instance's information for + * all instances created on this physical GPU + * + * guestVgpuInfo [OUT] + * This parameter specifies an array containing guest vgpu's information for + * all vGPUs created on this physical GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU (0xa0810102) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID" */ + +/* + * NVA081_GUEST_VM_INFO + * + * This structure represents vGPU guest's (VM's) information + * + * vmPid [OUT] + * This param specifies the vGPU plugin process ID + * vmIdType [OUT] + * This param specifies the VM ID type, i.e. DOMAIN_ID or UUID + * guestOs [OUT] + * This param specifies the vGPU guest OS type + * migrationProhibited [OUT] + * This flag indicates whether migration is prohibited for VM or not + * guestNegotiatedVgpuVersion [OUT] + * This param specifies the vGPU version of guest driver after negotiation + * frameRateLimit [OUT] + * This param specifies the current value of FRL set for guest + * licensed [OUT] + * This param specifies whether the VM is Unlicensed/Licensed + * licenseState [OUT] + * This param specifies the current state of the GRID license state machine + * licenseExpiryTimestamp [OUT] + * License expiry time in seconds since UNIX epoch + * licenseExpiryStatus [OUT] + * License expiry status + * guestDriverVersion [OUT] + * This param specifies the driver version of the driver installed on the VM + * guestDriverBranch [OUT] + * This param specifies the driver branch of the driver installed on the VM + * vmName [OUT] + * This param stores the name assigned to VM (KVM only) + * guestVmInfoState [OUT] + * This param stores the current state of guest dependent fields + * + */ +typedef struct NVA081_GUEST_VM_INFO { + NvU32 vmPid; + VM_ID_TYPE vmIdType; + NvU32 guestOs; + NvU32 migrationProhibited; + NvU32 guestNegotiatedVgpuVersion; + NvU32 frameRateLimit; + NvBool licensed; + NvU32 licenseState; + NvU32 licenseExpiryTimestamp; + NvU8 licenseExpiryStatus; + NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); + NvU8 guestDriverVersion[NVA081_VGPU_STRING_BUFFER_SIZE]; + NvU8 guestDriverBranch[NVA081_VGPU_STRING_BUFFER_SIZE]; + NvU8 vmName[NVA081_VM_NAME_SIZE]; + GUEST_VM_INFO_STATE guestVmInfoState; +} NVA081_GUEST_VM_INFO; + +/* + * NVA081_GUEST_VGPU_DEVICE + * + * This structure represents host vgpu device's (assigned to VM) information + * + * eccState [OUT] + * This parameter specifies the ECC state of the virtual GPU. + * One of NVA081_CTRL_ECC_STATE_xxx values. + * bDriverLoaded [OUT] + * This parameter specifies whether driver is loaded on this particular vGPU. + * swizzId [OUT] + * This param specifies the GPU Instance ID or Swizz ID + * + */ +typedef struct NVA081_HOST_VGPU_DEVICE { + NvU32 vgpuType; + NvU32 vgpuDeviceInstanceId; + NV_DECLARE_ALIGNED(NvU64 vgpuPciId, 8); + NvU8 vgpuUuid[VM_UUID_SIZE]; + NvU8 mdevUuid[VM_UUID_SIZE]; + NvU32 encoderCapacity; + NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); + NvU32 eccState; + NvBool bDriverLoaded; + NvU32 swizzId; +} NVA081_HOST_VGPU_DEVICE; + +/* ECC state values */ +#define NVA081_CTRL_ECC_STATE_UNKNOWN 0 +#define NVA081_CTRL_ECC_STATE_NOT_SUPPORTED 1 +#define NVA081_CTRL_ECC_STATE_DISABLED 2 +#define NVA081_CTRL_ECC_STATE_ENABLED 3 + +/* + * NVA081_VGPU_GUEST + * + * This structure represents a vGPU guest + * + */ +typedef struct NVA081_VGPU_GUEST { + NV_DECLARE_ALIGNED(NVA081_GUEST_VM_INFO guestVmInfo, 8); + NV_DECLARE_ALIGNED(NVA081_HOST_VGPU_DEVICE vgpuDevice, 8); +} NVA081_VGPU_GUEST; + +/* + * NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS + * + * This structure represents the information of vGPU guest instances per pGpu + * + */ +#define NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS { + NvU32 vgpuType; + NvU32 numVgpu; + NV_DECLARE_ALIGNED(NVA081_VGPU_GUEST vgpuGuest[NVA081_MAX_VGPU_PER_PGPU], 8); +} NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_VGPU_TYPE_INFO + * + * This command fetches vGPU type info from RM. + * + * Parameters: + * + * vgpuType [IN] + * This parameter specifies the virtual GPU type for which vGPU info should be returned. + * + * vgpuTypeInfo [OUT] + * This parameter returns NVA081_CTRL_VGPU_INFO data for the vGPU type specified by vgpuType. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ + +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_VGPU_TYPE_INFO (0xa0810103) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS + * + */ +#define NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS { + NvU32 vgpuType; + NV_DECLARE_ALIGNED(NVA081_CTRL_VGPU_INFO vgpuTypeInfo, 8); +} NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS; + +/* + * NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS + * This structure represents supported/creatable vGPU types on a pGPU + */ +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS { + /* + * [OUT] vGPU config state on a pGPU + */ + NvU32 vgpuConfigState; + + /* + * [OUT] Count of supported/creatable vGPU types on a pGPU + */ + NvU32 numVgpuTypes; + + /* + * [OUT] - Array of vGPU type ids supported/creatable on a pGPU + */ + NvU32 vgpuTypes[NVA081_MAX_VGPU_TYPES_PER_PGPU]; +} NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS; + + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES + * + * This command fetches count and list of vGPU types supported on a pGpu from RM + * + * Parameters: + * + * numVgpuTypes [OUT] + * This parameter returns the number of vGPU types supported on this pGPU + * + * vgpuTypes [OUT] + * This parameter returns list of supported vGPUs types on this pGPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + */ + +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES (0xa0810104) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | 0x4" */ + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES + * + * This command fetches count and list of vGPU types creatable on a pGpu from RM + * + * Parameters: + * + * numVgpuTypes [OUT] + * This parameter returns the number of vGPU types creatable on this pGPU + * + * vgpuTypes [OUT] + * This parameter returns list of creatable vGPUs types on this pGPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + */ + +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES (0xa0810105) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | 0x5" */ + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_EVENT_SET_NOTIFICATION + * + * This command sets event notification state for the associated subdevice/pGPU. + * This command requires that an instance of NV01_EVENT has been previously + * bound to the associated subdevice object. + * + * event + * This parameter specifies the type of event to which the specified + * action is to be applied. This parameter must specify a valid + * NVA081_NOTIFIERS value (see cla081.h for more details) and should + * not exceed one less NVA081_NOTIFIERS_MAXCOUNT. + * action + * This parameter specifies the desired event notification action. + * Valid notification actions include: + * NVA081_CTRL_SET_EVENT_NOTIFICATION_DISABLE + * This action disables event notification for the specified + * event for the associated subdevice object. + * NVA081_CTRL_SET_EVENT_NOTIFICATION_SINGLE + * This action enables single-shot event notification for the + * specified event for the associated subdevice object. + * NVA081_CTRL_SET_EVENT_NOTIFICATION_REPEAT + * This action enables repeated event notification for the specified + * event for the associated system controller object. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_EVENT_SET_NOTIFICATION (0xa0810106) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS { + NvU32 event; + NvU32 action; +} NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS; + + +/* valid event action values */ +#define NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001) +#define NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002) + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_NOTIFY_START + * + * This command notifies the nvidia-vgpu-vfio module with start status. + * It notifies whether start has been successful or not. + * + * mdevUuid + * This parameter specifies the uuid of the mdev device for which start has + * been called. + * vmUuid + * The UUID of VM for which vGPU has been created. + * vmName + * The name of VM for which vGPU has been created. + * returnStatus + * This parameter species whether the vGPU plugin is initialized or not. + * it specifies the error code in case plugin initialization has failed + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_NOTIFY_START (0xa0810107) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS_MESSAGE_ID" */ + +/* + * NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS + * This structure represents information of plugin init status. + */ +#define NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS { + NvU8 mdevUuid[VM_UUID_SIZE]; + NvU8 vmUuid[VM_UUID_SIZE]; + NvU8 vmName[NVA081_VM_NAME_SIZE]; + NvU32 returnStatus; +} NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_MDEV_REGISTER + * + * This command register the GPU to Linux kernel's mdev module for vGPU on KVM. + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_MDEV_REGISTER (0xa0810109) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | 0x9" */ + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_SET_VGPU_INSTANCE_ENCODER_CAPACITY + * + * This command is used to set vGPU instance's (represented by vgpuUuid) encoder Capacity. + * + * vgpuUuid + * This parameter specifies the uuid of vGPU assigned to VM. + * encoderCapacity + * Encoder capacity value from 0 to 100. Value of 0x00 indicates encoder performance + * may be minimal for this GPU and software should fall back to CPU-based encode. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVA081_CTRL_CMD_VGPU_CONFIG_SET_VGPU_INSTANCE_ENCODER_CAPACITY (0xa0810110) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS_MESSAGE_ID" */ + +/* + * NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS + * + * This structure represents encoder capacity for vgpu instance. + */ +#define NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS { + NvU8 vgpuUuid[VM_UUID_SIZE]; + NvU32 encoderCapacity; +} NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_VGPU_FB_USAGE + * + * This command is used to get the FB usage of all vGPU instances running on a GPU. + * + * vgpuCount + * This field specifies the number of vGPU devices for which FB usage is returned. + * vgpuFbUsage + * This is an array of type NVA081_VGPU_FB_USAGE, which contains a list of vGPUs + * and their corresponding FB usage in bytes; + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_VGPU_FB_USAGE (0xa0810111) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID" */ + +typedef struct NVA081_VGPU_FB_USAGE { + NvU8 vgpuUuid[VM_UUID_SIZE]; + NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); +} NVA081_VGPU_FB_USAGE; + +/* + * NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS + * + * This structure represents the FB usage information of vGPU instances running on a GPU. + */ +#define NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS { + NvU32 vgpuCount; + NV_DECLARE_ALIGNED(NVA081_VGPU_FB_USAGE vgpuFbUsage[NVA081_MAX_VGPU_PER_PGPU], 8); +} NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP + * + * This command is used to query whether pGPU is live migration capable or not. + * + * bMigrationCap + * Set to NV_TRUE if pGPU is migration capable. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_REQUEST + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP (0xa0810112) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS_MESSAGE_ID" */ + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS { + NvBool bMigrationCap; +} NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_HOST_FB_RESERVATION + * + * This command is used to get the host FB requirements + * + * hostReservedFb [OUT] + * Amount of FB reserved for the host + * eccAndPrReservedFb [OUT] + * Amount of FB reserved for the ecc and page retirement + * totalReservedFb [OUT] + * Total FB reservation + * vgpuTypeId [IN] + * The Type ID for VGPU profile + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_HOST_FB_RESERVATION (0xa0810113) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS { + NV_DECLARE_ALIGNED(NvU64 hostReservedFb, 8); + NV_DECLARE_ALIGNED(NvU64 eccAndPrReservedFb, 8); + NV_DECLARE_ALIGNED(NvU64 totalReservedFb, 8); + NvU32 vgpuTypeId; +} NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_PGPU_METADATA_STRING + * + * This command is used to get the pGpu metadata string. + * + * pGpuString + * String holding pGpu Metadata + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_STATE + * NV_ERR_INSUFFICIENT_RESOURCES + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_PGPU_METADATA_STRING (0xa0810114) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS { + NvU8 pGpuString[NVA081_PGPU_METADATA_STRING_SIZE]; +} NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS; + +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT (0xa0810115) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS { + NvBool doorbellEmulationEnabled; +} NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_FREE_SWIZZID + * + * This command is used to get free swizzid from RM + * + * gpuPciId [IN] + * This param specifies the PCI device ID of VF on which VM is running + * + * vgpuTypeId [IN] + * This param specifies the Type ID for VGPU profile + * + * swizzId [OUT] + * This param specifies the GPU Instance ID or Swizz ID + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_FREE_SWIZZID (0xa0810116) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS { + NvU32 gpuPciId; + NvU32 vgpuTypeId; + NvU32 swizzId; +} NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS; + +/* + * NVA081_CTRL_CMD_PGPU_GET_MULTI_VGPU_SUPPORT_INFO + * + * This command is used to get multi vGPU related info for the physical GPU. + * + * fractionalmultiVgpuSupported [OUT] + * This param specifies whether fractional multi-vGPU is supported + * + * heterogeneousTimesliceProfilesSupported [OUT] + * This param specifies whether concurrent execution of timesliced vGPU profiles of differing types is supported + * + * heterogeneousTimesliceSizesSupported [OUT] + * This param specifies whether concurrent execution of timesliced vGPU profiles of differing framebuffer sizes is supported + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVA081_CTRL_CMD_PGPU_GET_MULTI_VGPU_SUPPORT_INFO (0xa0810117) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS_MESSAGE_ID (0x17U) + +typedef struct NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS { + NvU32 fractionalmultiVgpuSupported; + NvU32 heterogeneousTimesliceProfilesSupported; + NvU32 heterogeneousTimesliceSizesSupported; +} NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS; + +/* + * NVA081_CTRL_CMD_GET_VGPU_DRIVER_CAPS + * + * This command is used to get vGPU driver capabilities. + * + * heterogeneousMultiVgpuSupported [OUT] + * This param specifies whether heterogeneous multi-vGPU is supported + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVA081_CTRL_CMD_GET_VGPU_DRIVER_CAPS (0xa0810118) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS { + NvU32 heterogeneousMultiVgpuSupported; +} NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_SET_PGPU_INFO + * + * This command is to set pgpu info + * + * fractionalMultiVgpu [IN] + * This param specifies the fractional multivgpu is enabled or disabled on GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ + +#define NVA081_CTRL_CMD_VGPU_CONFIG_SET_PGPU_INFO (0xa0810119) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS { + NvU32 fractionalMultiVgpu; +} NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS; + +/* _ctrlA081vgpuconfig_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla084.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla084.h new file mode 100644 index 0000000..f5a5146 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla084.h @@ -0,0 +1,302 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla084.finn +// + +#include "nv_vgpu_types.h" +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl2080/ctrl2080gpu.h" // NV2080_GPU_MAX_GID_LENGTH +#include "ctrl/ctrl2080/ctrl2080fb.h" // NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES + +/* NVA084_KERNEL_HOST_VGPU_DEVICE control commands and parameters */ +#define NVA084_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xA084U, NVA084_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NVA084_CTRL_RESERVED (0x00) +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE (0x01) + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO + * + * This command sets the guest vgpu device's information + * + * Parameter: + * + * vgpuUuid [IN] + * This parameter specifies the universaly unique identifier of the guest vGPU device + * + * vgpuDeviceInstanceId [IN] + * This parameter specifies the vGPU device instance + * + * Possible status values returned are: + * NV_OK + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO (0xa0840101) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS { + NvU8 vgpuUuid[NV2080_GPU_MAX_GID_LENGTH]; + NvU32 vgpuDeviceInstanceId; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS; + +/* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE + * + * This command triggers the notifier for vGPU guest. + * + * Parameters: + * + * vmLifeCycleState[IN] + * The life cycle event of the vGPU guest. This can be: + * NVA081_NOTIFIERS_EVENT_VGPU_GUEST_DESTROYED + * NVA081_NOTIFIERS_EVENT_VGPU_GUEST_CREATED + * + * Possible status values returned are: + * NV_OK + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE (0xa0840102) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS { + NvU32 vmLifeCycleState; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS; + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO + * + * This command is used to copy offlined page mapping info from plugin to host vgpu device + * + * guestFbSegmentPageSize [in] + * Guest FB segment page size + * + * offlinedPageCount [in] + * Offlined page count in the guest FB range + * + * gpa [in] + * This array represents guest page address list of offlined page + * + * hMemory [in] + * This array represents memory handle list of good page + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO (0xa0840103) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS { + NvU32 guestFbSegmentPageSize; + NvU32 offlinedPageCount; + NV_DECLARE_ALIGNED(NvU64 gpa[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES], 8); + NvHandle hMemory[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES]; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS; + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS + * + * Config space access for the virtual function + * + * Parameters: + * + * offset [IN] + * Offset within the config space + * + * numBytes [IN] + * Number of bytes to be read/written: 1/2/4 + * + * accessType [IN] + * To indicate whether it is a read operation or a write operation + * + * value [INOUT] + * Value to be read or written + * + * Possible status values returned are: + * NV_OK + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS (0xa0840104) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_VF_CONFIG_SPACE_ACCESS_TYPE_READ 0x1 +#define NVA084_CTRL_VF_CONFIG_SPACE_ACCESS_TYPE_WRITE 0x2 + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS { + NvU16 offset; + NvU8 numBytes; + NvU8 accessType; + NvU32 value; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS; + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF + * + * This command is used to create a bind-point on a host system + * for the collection of guest VM FECS events + * + * hEventBufferClient[IN] + * The client of the event buffer to bind to + * + * hEventBufferSubdevice[IN] + * The subdevice of the event buffer to bind to + * + * hEventBuffer[IN] + * The event buffer to bind to + * + * reasonCode[OUT] + * The reason for failure (if any); see NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF (0xa0840105) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS { + NvHandle hEventBufferClient; + NvHandle hEventBufferSubdevice; + NvHandle hEventBuffer; + NvU32 reasonCode; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS; + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL + * + * The command will trigger the specified interrupt on the host from CPU Plugin. + * + * handle[IN] + * - An opaque handle that will be passed in along with the interrupt + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL (0xa0840106) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS { + NvU32 handle; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS; + +/* valid action values */ +#define NVA084_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NVA084_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001) +#define NVA084_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002) + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION + * + * This command sets event notification state for the associated host vgpu device. + * This command requires that an instance of NV01_EVENT has been previously + * bound to the associated host vgpu device object. + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION (0xa0840107) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS { + // + // @todo: We will define the actual event values later based on the use case. + // These event values are only for Test purpose. + // + NvU32 event; + NvU32 action; + NvBool bNotifyState; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS; + +/* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE + * + * This command is used to set SRIOV state parameters in RM. + * + * Parameters: + * + * numPluginChannels [IN] + * Number of channels required by plugin + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE (0xa0840108) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_MAX_PLUGIN_CHANNELS 5 + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS { + NvU32 numPluginChannels; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS; + +/* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID + * + * This command is used to set/unset VM ID parameters in host vgpu device in RM. + * + * Parameters: + * + * action + * This parameter specifies the desired set guest id action. + * Valid set guest id actions include: + * NVA084_CTRL_HOST_VGPU_DEVICE_KERNEL_SET_GUEST_ID_ACTION_SET + * This action sets the VM ID information in host vgpu device. + * NVA084_CTRL_HOST_VGPU_DEVICE_KERNEL_SET_GUEST_ID_ACTION_UNSET + * This action unsets the VM ID information in host vgpu device. + * vmPid [IN] + * VM process ID + * vmIdType[IN] + * VM ID type whether it's UUID or DOMAIN_ID + * guestVmId[IN] + * VM ID + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID (0xa0840109) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS { + NvU8 action; + NvU32 vmPid; + VM_ID_TYPE vmIdType; + NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS; + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_ACTION_SET (0x00000000) +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_ACTION_UNSET (0x00000001) + +/* _ctrla084_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla16f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla16f.h new file mode 100644 index 0000000..7cf7069 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla16f.h @@ -0,0 +1,200 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla16f.finn +// + + + + +/* GK100_GPFIFO control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrla06f.h" /* A16F is partially derived from A06F */ +#include "ctrl/ctrl906f.h" /* A16F is partially derived from 906F */ +#define NVA16F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xA16F, NVA16F_CTRL_##cat, idx) + +/* GK100_GPFIFO command categories (6bits) */ +#define NVA16F_CTRL_RESERVED (0x00) +#define NVA16F_CTRL_GPFIFO (0x01) +#define NVA16F_CTRL_EVENT (0x02) + +/* + * NVA16F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVA16F_CTRL_CMD_NULL (0xa16f0000) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NVA16F_CTRL_GET_CLASS_ENGINEID + * + * Please see description of NVA06F_CTRL_GET_CLASS_ENGINEID for more information. + * + */ +#define NVA16F_CTRL_GET_CLASS_ENGINEID (0xa16f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x1" */ + +typedef NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS NVA16F_CTRL_GET_CLASS_ENGINEID_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA16F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA16F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS { + NVA16F_CTRL_GET_CLASS_ENGINEID_PARAMS params; +} NVA16F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS; + + + +/* + * NVA16F_CTRL_RESET_CHANNEL + * + * Please see description of NVA06F_CTRL_RESET_CHANNEL for more information. + * + */ +#define NVA16F_CTRL_CMD_RESET_CHANNEL (0xa16f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x2" */ +typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA16F_CTRL_CMD_RESET_CHANNEL_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA16F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVA16F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS { + NVA16F_CTRL_CMD_RESET_CHANNEL_PARAMS params; +} NVA16F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS; + + + +/* + * NVA16F_CTRL_CMD_GPFIFO_SCHEDULE + * + * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. + * + */ +#define NVA16F_CTRL_CMD_GPFIFO_SCHEDULE (0xa16f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x3" */ +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA16F_CTRL_GPFIFO_SCHEDULE_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA16F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVA16F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS { + NVA16F_CTRL_GPFIFO_SCHEDULE_PARAMS params; +} NVA16F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS; + + + +/* + * NVA16F_CTRL_CMD_BIND + * + * Please see description of NVA06F_CTRL_CMD_BIND for more information. + */ +#define NVA16F_CTRL_CMD_BIND (0xa16f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x4" */ + +typedef NVA06F_CTRL_BIND_PARAMS NVA16F_CTRL_BIND_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA16F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVA16F_CTRL_CMD_BIND_FINN_PARAMS { + NVA16F_CTRL_BIND_PARAMS params; +} NVA16F_CTRL_CMD_BIND_FINN_PARAMS; + + + +/* + * NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. +*/ +#define NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa16f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID << 8) | 0x5" */ + +typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVA16F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS { + NVA16F_CTRL_EVENT_SET_NOTIFICATION_PARAMS params; +} NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS; + + + +/* valid action values */ +#define NVA16F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE +#define NVA16F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE +#define NVA16F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT + +/* + * NVA16F_CTRL_CMD_EVENT_SET_TRIGGER + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information. + */ +#define NVA16F_CTRL_CMD_EVENT_SET_TRIGGER (0xa16f0206) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID << 8) | 0x6" */ + + + + + +/* + * NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO + * + * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. + * + */ +#define NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa16f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x7" */ + +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA16F_CTRL_GET_MMU_FAULT_INFO_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS { + NV_DECLARE_ALIGNED(NVA16F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8); +} NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS; + + + +/* _ctrla16f.h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla26f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla26f.h new file mode 100644 index 0000000..6dcf930 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrla26f.h @@ -0,0 +1,200 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla26f.finn +// + + + + +/* GK20A_GPFIFO control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrla06f.h" /* A26F is partially derived from A06F */ +#include "ctrl/ctrl906f.h" /* A26F is partially derived from 906F */ +#define NVA26F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xA26F, NVA26F_CTRL_##cat, idx) + +/* GK20A_GPFIFO command categories (6bits) */ +#define NVA26F_CTRL_RESERVED (0x00) +#define NVA26F_CTRL_GPFIFO (0x01) +#define NVA26F_CTRL_EVENT (0x02) + +/* + * NVA26F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVA26F_CTRL_CMD_NULL (0xa26f0000) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NVA26F_CTRL_GET_CLASS_ENGINEID + * + * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. + * + */ +#define NVA26F_CTRL_GET_CLASS_ENGINEID (0xa26f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x1" */ + +typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVA26F_CTRL_GET_CLASS_ENGINEID_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA26F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA26F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS { + NVA26F_CTRL_GET_CLASS_ENGINEID_PARAMS params; +} NVA26F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS; + + + +/* + * NVA26F_CTRL_RESET_CHANNEL + * + * Please see description of NVA06F_CTRL_CMD_RESET_CHANNEL for more information. + * + */ +#define NVA26F_CTRL_CMD_RESET_CHANNEL (0xa26f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x2" */ +typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA26F_CTRL_CMD_RESET_CHANNEL_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA26F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVA26F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS { + NVA26F_CTRL_CMD_RESET_CHANNEL_PARAMS params; +} NVA26F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS; + + + +/* + * NVA26F_CTRL_CMD_GPFIFO_SCHEDULE + * + * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. + * + */ +#define NVA26F_CTRL_CMD_GPFIFO_SCHEDULE (0xa26f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x3" */ +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA26F_CTRL_GPFIFO_SCHEDULE_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA26F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVA26F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS { + NVA26F_CTRL_GPFIFO_SCHEDULE_PARAMS params; +} NVA26F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS; + + + +/* + * NVA26F_CTRL_CMD_BIND + * + * Please see description of NVA06F_CTRL_CMD_BIND for more information. + */ +#define NVA26F_CTRL_CMD_BIND (0xa26f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x4" */ + +typedef NVA06F_CTRL_BIND_PARAMS NVA26F_CTRL_BIND_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA26F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVA26F_CTRL_CMD_BIND_FINN_PARAMS { + NVA26F_CTRL_BIND_PARAMS params; +} NVA26F_CTRL_CMD_BIND_FINN_PARAMS; + + + +/* + * NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. +*/ +#define NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa26f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID << 8) | 0x5" */ + +typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVA26F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS { + NVA26F_CTRL_EVENT_SET_NOTIFICATION_PARAMS params; +} NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS; + + + +/* valid action values */ +#define NVA26F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE +#define NVA26F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE +#define NVA26F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT + +/* + * NVA26F_CTRL_CMD_EVENT_SET_TRIGGER + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information. + */ +#define NVA26F_CTRL_CMD_EVENT_SET_TRIGGER (0xa26f0206) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID << 8) | 0x6" */ + + + + + +/* + * NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO + * + * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. + * + */ +#define NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa26f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x7" */ + +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA26F_CTRL_GET_MMU_FAULT_INFO_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS { + NV_DECLARE_ALIGNED(NVA26F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8); +} NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS; + + + +/* _ctrla26f.h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb069.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb069.h new file mode 100644 index 0000000..66eb26d --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb069.h @@ -0,0 +1,180 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlb069.finn +// + +#include "ctrl/ctrlxxxx.h" +/* MAXWELL_FAULT_BUFFER_A control commands and parameters */ + +#define NVB069_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xB069, NVB069_CTRL_##cat, idx) + +/* MAXWELL_FAULT_BUFFER_A command categories (6bits) */ +#define NVB069_CTRL_RESERVED (0x00) +#define NVB069_CTRL_FAULTBUFFER (0x01) + +/* + * NVB069_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVB069_CTRL_CMD_NULL (0xb0690000) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + + +/* + * NVB069_CTRL_CMD_FAULTBUFFER_READ_GET + * + * This command returns the current HW GET pointer for the requested type fault buffer + * + * faultBufferGetOffset + * Value of current HW GET pointer + * faultBufferType + * Type of fault buffer. FAULT_BUFFER_REPLAYABLE or FAULT_BUFFER_NON_REPLAYABLE + */ +#define NVB069_CTRL_CMD_FAULTBUFFER_READ_GET (0xb0690101) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_FAULTBUFFER_READ_GET_PARAMS_MESSAGE_ID" */ + +#define NVB069_CTRL_FAULTBUFFER_READ_GET_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVB069_CTRL_FAULTBUFFER_READ_GET_PARAMS { + NvU32 faultBufferGetOffset; + NvU32 faultBufferType; +} NVB069_CTRL_FAULTBUFFER_READ_GET_PARAMS; + +// +// Valid Fault buffer Types +// NON_REPLAYABLE is only supported in Volta+ GPUs. +// +#define NVB069_CTRL_FAULT_BUFFER_NON_REPLAYABLE (0x00000000) +#define NVB069_CTRL_FAULT_BUFFER_REPLAYABLE (0x00000001) + +/* + * NVB069_CTRL_CMD_FAULTBUFFER_WRITE_GET + * + * This command writes the HW GET pointer for the requested type of fault buffer + * + * NOTE: The caller must issue a write barrier before this function to + * ensure modifications to the current buffer entry are committed before + * the GET pointer is updated. + * + * faultBufferGetOffset + * Value to be written to HW GET pointer + * faultBufferType + * Type of fault buffer. FAULT_BUFFER_REPLAYABLE or FAULT_BUFFER_NON_REPLAYABLE + */ +#define NVB069_CTRL_CMD_FAULTBUFFER_WRITE_GET (0xb0690102) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_FAULTBUFFER_WRITE_GET_PARAMS_MESSAGE_ID" */ + +#define NVB069_CTRL_FAULTBUFFER_WRITE_GET_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVB069_CTRL_FAULTBUFFER_WRITE_GET_PARAMS { + NvU32 faultBufferGetOffset; + NvU32 faultBufferType; +} NVB069_CTRL_FAULTBUFFER_WRITE_GET_PARAMS; + +/* + * NVB069_CTRL_CMD_FAULTBUFFER_READ_PUT + * + * This command returns the current HW PUT pointer for the requested type fault buffer + * + * faultBufferGetOffset + * Value of current HW PUT pointer + * faultBufferType + * Type of fault buffer. FAULT_BUFFER_REPLAYABLE or FAULT_BUFFER_NON_REPLAYABLE + */ +#define NVB069_CTRL_CMD_FAULTBUFFER_READ_PUT (0xb0690103) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_FAULTBUFFER_READ_PUT_PARAMS_MESSAGE_ID" */ + +#define NVB069_CTRL_FAULTBUFFER_READ_PUT_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVB069_CTRL_FAULTBUFFER_READ_PUT_PARAMS { + NvU32 faultBufferPutOffset; + NvU32 faultBufferType; +} NVB069_CTRL_FAULTBUFFER_READ_PUT_PARAMS; + +#define NVB069_CTRL_CMD_FAULTBUFFER_ENABLE_NOTIFICATION (0xb0690104) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_FAULTBUFFER_ENABLE_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NVB069_CTRL_FAULTBUFFER_ENABLE_NOTIFICATION_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVB069_CTRL_FAULTBUFFER_ENABLE_NOTIFICATION_PARAMS { + NvBool Enable; +} NVB069_CTRL_FAULTBUFFER_ENABLE_NOTIFICATION_PARAMS; + +#define NVB069_CTRL_CMD_FAULTBUFFER_GET_SIZE (0xb0690105) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_FAULTBUFFER_GET_SIZE_PARAMS_MESSAGE_ID" */ + +#define NVB069_CTRL_FAULTBUFFER_GET_SIZE_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVB069_CTRL_FAULTBUFFER_GET_SIZE_PARAMS { + NvU32 faultBufferSize; +} NVB069_CTRL_FAULTBUFFER_GET_SIZE_PARAMS; + + +/* + * NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS + * + * This command provides kernel mapping to a few registers. + * These mappings are needed by UVM driver to handle non fatal gpu faults + * + * pFaultBufferGet + * Mapping for fault buffer's get pointer (NV_PFIFO_REPLAYABLE_FAULT_BUFFER_GET) + * pFaultBufferPut + * Mapping for fault buffer's put pointer (NV_PFIFO_REPLAYABLE_FAULT_BUFFER_PUT) + * pFaultBufferInfo + * Mapping for fault buffer's Info pointer (NV_PFIFO_REPLAYABLE_FAULT_BUFFER_INFO) + * Note: this variable is deprecated since buffer overflow is not a seperate register from Volta + * pPmcIntr + * Mapping for PMC intr register (NV_PMC_INTR(0)) + * pPmcIntrEnSet + * Mapping for PMC intr set register - used to enable an intr (NV_PMC_INTR_EN_SET(0)) + * pPmcIntrEnClear + * Mapping for PMC intr clear register - used to disable an intr (NV_PMC_INTR_EN_CLEAR(0)) + * replayableFaultMask + * Mask for the replayable fault bit(NV_PMC_INTR_REPLAYABLE_FAULT) + */ +#define NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS (0xb0690106) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS_MESSAGE_ID" */ + +#define NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pFaultBufferGet, 8); + NV_DECLARE_ALIGNED(NvP64 pFaultBufferPut, 8); + NV_DECLARE_ALIGNED(NvP64 pFaultBufferInfo, 8); + NV_DECLARE_ALIGNED(NvP64 pPmcIntr, 8); + NV_DECLARE_ALIGNED(NvP64 pPmcIntrEnSet, 8); + NV_DECLARE_ALIGNED(NvP64 pPmcIntrEnClear, 8); + NvU32 replayableFaultMask; + NV_DECLARE_ALIGNED(NvP64 pPrefetchCtrl, 8); +} NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS; + +/* _ctrlb069_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb06f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb06f.h new file mode 100644 index 0000000..14a6199 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb06f.h @@ -0,0 +1,527 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlb06f.finn +// + + + + +/* MAXWELL_CHANNEL_GPFIFO_A control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrla06f.h" /* B06F is partially derived from A06F */ +#include "ctrl/ctrl906f.h" /* B06F is partially derived from 906F */ +#define NVB06F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xB06F, NVB06F_CTRL_##cat, idx) + +/* MAXWELL_CHANNEL_GPFIFO_A command categories (6bits) */ +#define NVB06F_CTRL_RESERVED (0x00) +#define NVB06F_CTRL_GPFIFO (0x01) +#define NVB06F_CTRL_EVENT (0x02) + +/* + * NVB06F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVB06F_CTRL_CMD_NULL (0xb06f0000) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NVB06F_CTRL_GET_CLASS_ENGINEID + * + * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. + * + */ +#define NVB06F_CTRL_GET_CLASS_ENGINEID (0xb06f0101) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */ + +typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVB06F_CTRL_GET_CLASS_ENGINEID_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVB06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVB06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS { + NVB06F_CTRL_GET_CLASS_ENGINEID_PARAMS params; +} NVB06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS; + + + +/* + * NVB06F_CTRL_RESET_CHANNEL + * + * Please see description of NVA06F_CTRL_RESET_CHANNEL for more information. + * + */ +#define NVB06F_CTRL_CMD_RESET_CHANNEL (0xb06f0102) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */ + +typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVB06F_CTRL_CMD_RESET_CHANNEL_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVB06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVB06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS { + NVB06F_CTRL_CMD_RESET_CHANNEL_PARAMS params; +} NVB06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS; + + + +/* + * NVB06F_CTRL_CMD_GPFIFO_SCHEDULE + * + * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. + * + */ +#define NVB06F_CTRL_CMD_GPFIFO_SCHEDULE (0xb06f0103) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */ + +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVB06F_CTRL_GPFIFO_SCHEDULE_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVB06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVB06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS { + NVB06F_CTRL_GPFIFO_SCHEDULE_PARAMS params; +} NVB06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS; + + + +/* + * NVB06F_CTRL_CMD_BIND + * + * Please see description of NVA06F_CTRL_CMD_BIND for more information. + */ +#define NVB06F_CTRL_CMD_BIND (0xb06f0104) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */ + +typedef NVA06F_CTRL_BIND_PARAMS NVB06F_CTRL_BIND_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVB06F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVB06F_CTRL_CMD_BIND_FINN_PARAMS { + NVB06F_CTRL_BIND_PARAMS params; +} NVB06F_CTRL_CMD_BIND_FINN_PARAMS; + + + +/* + * NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. +*/ +#define NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xb06f0205) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x5" */ + +typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVB06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS { + NVB06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS params; +} NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS; + + + +/* valid action values */ +#define NVB06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE +#define NVB06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE +#define NVB06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT + +/* + * NVB06F_CTRL_CMD_EVENT_SET_TRIGGER + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information. + */ +#define NVB06F_CTRL_CMD_EVENT_SET_TRIGGER (0xb06f0206) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */ + + + + + +/* + * NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO + * + * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. + * + */ +#define NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xb06f0107) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */ + +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVB06F_CTRL_GET_MMU_FAULT_INFO_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS { + NV_DECLARE_ALIGNED(NVB06F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8); +} NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS; + + + +/* + * NVB06F_CTRL_CMD_GET_ENGINE_CTX_SIZE + * + * This command returns the size of the engine context. + * + * engineID + * This parameter specifies the engine context size to be retrieved. + * + * See the description of the NV2080_ENGINE_TYPE values in cl2080.h for more + * information + * + * size + * This parameter returns the size of the engine context + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVB06F_CTRL_CMD_GET_ENGINE_CTX_SIZE (0xb06f010b) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GET_ENGINE_CTX_SIZE_PARAMS_MESSAGE_ID" */ + +#define NVB06F_CTRL_GET_ENGINE_CTX_SIZE_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NVB06F_CTRL_GET_ENGINE_CTX_SIZE_PARAMS { + NvU32 engineID; + NvU32 size; +} NVB06F_CTRL_GET_ENGINE_CTX_SIZE_PARAMS; + +/* + * NVB06F_CTRL_CMD_GET_ENGINE_CTX_DATA + * + * This command returns the context buffer data for the given engine for vGPU motion. + * + * engineID + * This parameter specifies the engine context to be retrieved. + * + * See the description of the NV2080_ENGINE_TYPE values in cl2080.h for + * more information + * + * size + * This parameter specifies the size of the context buffer. + * + * pEngineCtxBuff + * This parameter specifies the context buffer for motion operation to be filled in. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ + +#define NVB06F_CTRL_CMD_GET_ENGINE_CTX_DATA (0xb06f010c) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID" */ + +typedef struct SW_OBJECT_ENGINE_CTX { + NvU32 hObject; + NvU32 subCh; +} SW_OBJECT_ENGINE_CTX; + +#define NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS { + NvU32 engineID; + NvU32 size; + NV_DECLARE_ALIGNED(NvP64 pEngineCtxBuff, 8); +} NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS; + +/* + * NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA + * + * This command restores the context buffer for the given engine for vGPU motion. + * + * engineID + * This parameter specifies the engine context to be restored. + * + * See the description of the NV2080_ENGINE_TYPE values in cl2080.h for + * more information + * + * size + * This parameter specifies the size of the context buffer. + * + * pEngineCtxBuff + * This parameter specifies the context buffer for motion operation restore. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ + +#define NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA (0xb06f010d) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS_MESSAGE_ID" */ + +typedef NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS { + NV_DECLARE_ALIGNED(NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS params, 8); +} NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS; + + + +/* + * NVB06F_CTRL_CMD_GET_ENGINE_CTX_STATE + * + * This command returns the context buffer state of the given engine for vGPU motion. + * + * engineID + * This input parameter specifies the engine context to be restored. + * + * See the description of the NV2080_ENGINE_TYPE values in cl2080.h for + * more information + * + * hObject + * This parameter specifies the channel object that is running on the SW engine. + * + * engineCtxState + * This parameter specifies the engine context state. For SW engine, the only meaningful + * field is INVALID, INITIALIZED and the subch. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ + +#define NVB06F_CTRL_CMD_GET_ENGINE_CTX_STATE (0xb06f010e) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GET_ENGINE_CTX_STATE_PARAMS_MESSAGE_ID" */ + +#define NVB06F_CTRL_GET_ENGINE_CTX_STATE_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NVB06F_CTRL_GET_ENGINE_CTX_STATE_PARAMS { + NvU32 engineID; + NvU32 hObject; + NvU32 engineCtxState; +} NVB06F_CTRL_GET_ENGINE_CTX_STATE_PARAMS; + +#define NVB06F_CTRL_GET_ENGINE_CTX_VIRTUAL_CONTEXT 0:0 +#define NVB06F_CTRL_GET_ENGINE_CTX_VIRTUAL_CONTEXT_DISABLED (0x00000000) +#define NVB06F_CTRL_GET_ENGINE_CTX_VIRTUAL_CONTEXT_ENABLED (0x00000001) +#define NVB06F_CTRL_GET_ENGINE_CTX_STATE 2:1 +#define NVB06F_CTRL_GET_ENGINE_CTX_STATE_INVALID (0x00000000) +#define NVB06F_CTRL_GET_ENGINE_CTX_STATE_INITIALIZED (0x00000001) +#define NVB06F_CTRL_GET_ENGINE_CTX_STATE_PROMOTED (0x00000002) +#define NVB06F_CTRL_GET_ENGINE_CTX_STATE_EVICTED (0x00000003) +#define NVB06F_CTRL_GET_ENGINE_CTX_SUBCH 6:4 + +/* + * NVB06F_CTRL_CMD_GET_CHANNEL_HW_STATE + * + * This command returns the channel HW state. + * + * state + * This parameter stores single bit-fields corresponding to the following + * channel HW states: + * NEXT + * A value of NV_TRUE indicates that this channel should be scheduled + * first when GPU Host chooses this TSG to run next on the runlist. + * + * CTX_RELOAD + * A value of NV_TRUE indicates that this channel's context was + * preempted and needs to be reloaded. + * + * PENDING + * A value of NV_TRUE indicates that this channel is not loaded on the + * PBDMA but methods still remain. This includes the completion of + * semaphores acquires and WFI methods. This field is deprecated + * from Volta onwards, and can be ignored. + * + * ENG_FAULTED + * A value of NV_TRUE indicates that the channel's engine has faulted, + * and the channel will not be rescheduled until the fault has been + * cleared. This bit should only be set as part of migration, and will + * not necessarily cause the channel to be prevented from being + * scheduled. + * + * PBDMA_FAULTED + * A value of NV_TRUE indicates that the channel's PBDMA has faulted, + * and the channel will not be rescheduled until the fault has been + * cleared. This bit should only be set as part of migration, and will + * not necessarily cause the channel to be prevented from being + * scheduled. + * + * ACQUIRE_FAIL + * A value of NV_TRUE indicates that the engine scheduler failed to + * acquire a semaphore for this channel. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ +#define NVB06F_CTRL_CMD_GET_CHANNEL_HW_STATE (0xb06f010f) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS_MESSAGE_ID" */ + +#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_NEXT 0:0 +#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_CTX_RELOAD 1:1 +#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_PENDING 2:2 +#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_ENG_FAULTED 3:3 +#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_PBDMA_FAULTED 4:4 +#define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_ACQUIRE_FAIL 5:5 + +#define NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS_MESSAGE_ID (0xFU) + +typedef struct NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS { + NvU32 state; +} NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS; + +/* + * NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE + * + * This command restores the channel HW state. + * + * state + * This parameter stores single bit-fields corresponding to the following + * channel HW states: + * NEXT + * A value of NV_TRUE indicates that this channel should be scheduled + * first when GPU Host chooses this TSG to run next on the runlist. + * + * CTX_RELOAD + * A value of NV_TRUE indicates that this channel's context was + * preempted and needs to be reloaded. + * + * PENDING + * A value of NV_TRUE indicates that this channel is not loaded on the + * PBDMA but methods still remain. This includes the completion of + * semaphores acquires and WFI methods. This field is deprecated + * from Volta onwards, and can be ignored. + * + * ENG_FAULTED + * A value of NV_TRUE indicates that the channel's engine has faulted, + * and the channel will not be rescheduled until the fault has been + * cleared. This bit should only be set as part of migration, and will + * not necessarily cause the channel to be prevented from being + * scheduled. + * + * PBDMA_FAULTED + * A value of NV_TRUE indicates that the channel's PBDMA has faulted, + * and the channel will not be rescheduled until the fault has been + * cleared. This bit should only be set as part of migration, and will + * not necessarily cause the channel to be prevented from being + * scheduled. + * + * ACQUIRE_FAIL + * A value of NV_TRUE indicates that the engine scheduler failed to + * acquire a semaphore for this channel. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ +#define NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE (0xb06f0110) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x10" */ + +typedef NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE_FINN_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE_FINN_PARAMS { + NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS params; +} NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE_FINN_PARAMS; + +/* + * NVB06F_CTRL_CMD_SAVE_ENGINE_CTX_DATA + * + * This command returns the context buffer data for the given engine for vGPU migration. + * + * engineID + * This parameter specifies the engine context to be retrieved. + * + * See the description of the NV2080_ENGINE_TYPE values in cl2080.h for + * more information + * + * size + * This parameter specifies the size of the context buffer. The maximum size + * of engine context buffer is choosen to support only RAMFC and instance + * memory block. To use this RmCtrl for a higher sized buffer, like the GR + * context, the max size would have to be increased. + * + * engineCtxBuff + * This parameter specifies the context buffer data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ + +#define NVB06F_CTRL_CMD_SAVE_ENGINE_CTX_DATA (0xb06f0111) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID" */ + +#define NVB06F_CTRL_ENGINE_CTX_BUFFER_SIZE_MAX 4096 + +#define NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS { + NvU32 engineID; + NvU32 size; + NvU8 engineCtxBuff[NVB06F_CTRL_ENGINE_CTX_BUFFER_SIZE_MAX]; +} NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS; + +/* + * NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA + * + * This command restores the context buffer for the given engine for vGPU migration. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ + +#define NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA (0xb06f0112) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS_MESSAGE_ID" */ + +typedef NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS NVB06F_CTRL_RESTORE_ENGINE_CTX_DATA_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS { + NVB06F_CTRL_RESTORE_ENGINE_CTX_DATA_PARAMS params; +} NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS; + + + +/* _ctrlb06f.h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb0cc.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb0cc.h new file mode 100644 index 0000000..decc79a --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb0cc.h @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlb0cc.finn +// + + + + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl2080/ctrl2080gpu.h" // NV2080_CTRL_GPU_REG_OP +#include "ctrlb0cc/ctrlb0ccprofiler.h" +#include "ctrlb0cc/ctrlb0ccinternal.h" diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h new file mode 100644 index 0000000..a6d2929 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlb0cc/ctrlb0ccbase.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl2080/ctrl2080gpu.h" // NV2080_CTRL_GPU_REG_OP +#define NVB0CC_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xB0CC, NVB0CC_CTRL_##cat, idx) + +/* MAXWELL_PROFILER command categories (6 bits) */ +#define NVB0CC_CTRL_RESERVED (0x00) +#define NVB0CC_CTRL_PROFILER (0x01) +#define NVB0CC_CTRL_INTERNAL (0x02) + +/*! + * NVB0CC_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVB0CC_CTRL_CMD_NULL (0xb0cc0000) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + +/* _ctrlb0ccbase_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h new file mode 100644 index 0000000..54e2dbd --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h @@ -0,0 +1,79 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlb0cc/ctrlb0ccinternal.finn +// + +#include "ctrl/ctrlb0cc/ctrlb0ccbase.h" + +#include "ctrl/ctrlb0cc/ctrlb0ccprofiler.h" /* Some controls derivative of b0ccprofiler */ +/*! + * @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM + */ +#define NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM (0xb0cc0200) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS_MESSAGE_ID" */ + + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS_MESSAGE_ID (0x0U) + +typedef struct NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS { + NV_DECLARE_ALIGNED(NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS params, 8); +} NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS; + + + +/*! + * NVB0CC_CTRL_CMD_INTERNAL_PERMISSIONS_INIT + * + * This command is used to convey the client permissions for appropriate + * profiling capability initialization + */ +#define NVB0CC_CTRL_CMD_INTERNAL_PERMISSIONS_INIT (0xb0cc0203) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS { + /*! + * [in] Is Admin profiling permitted + */ + NvBool bAdminProfilingPermitted; + /*! + * [in] Is Device profiling permitted + */ + NvBool bDevProfilingPermitted; + + /*! + * [in] Is Memory profiling permitted + */ + NvBool bMemoryProfilingPermitted; +} NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS; + +/* _ctrlb0ccinternal_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h new file mode 100644 index 0000000..d456c63 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h @@ -0,0 +1,479 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlb0cc/ctrlb0ccprofiler.finn +// + +#include "ctrl/ctrlb0cc/ctrlb0ccbase.h" + + +/*! + * NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY + * + * Reserves the HWPM legacy PM system for use by the calling client. + * This PM system will only be accessible if this reservation is + * taken. + * + * If a device level reservation is held by another client, then this command + * will fail regardless of reservation scope. + * + * This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_HWPM_LEGACY. + * + */ + + +#define NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY (0xb0cc0101) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS { + /*! + * [in] Enable ctxsw for HWPM. + */ + NvBool ctxsw; +} NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_RELEASE_HWPM_LEGACY + * + * Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY. + * + * This command does not take any parameters. + * + */ +#define NVB0CC_CTRL_CMD_RELEASE_HWPM_LEGACY (0xb0cc0102) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x2" */ + +/*! + * NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC + * + * Reserves the SMPC PM system for use by the calling client. + * This PM system will only be accessible if this reservation is + * taken. + * + * Reservation scope and rules are same as for @ref NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY. + * + * This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_PM_AREA_SMPC. + * + */ +#define NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC (0xb0cc0103) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS { + /*! + * [in] Enable ctxsw for SMPC. + */ + NvBool ctxsw; +} NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_RELEASE_PM_AREA_SMPC + * + * Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC. + * + * This command does not take any parameters. + * + */ +#define NVB0CC_CTRL_CMD_RELEASE_PM_AREA_SMPC (0xb0cc0104) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x4" */ + +/*! + * NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM + * + * Allocates PMA VA and map it to the buffers for streaming records and for + * for streaming the updated bytes available in the buffer. + * + */ +#define NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM (0xb0cc0105) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x5" */ + +/*! + * Defines the maximum size of PMA buffer for streamout. It can be up to 4GB minus one page + * reserved for streaming mem_bytes (see @ref NVB0CC_PMA_BYTES_AVAILABLE_SIZE). + */ +#define NVB0CC_PMA_BUFFER_SIZE_MAX (0xffe00000ULL) /* finn: Evaluated from "(4 * 1024 * 1024 * 1024 - 2 * 1024 * 1024)" */ +#define NVB0CC_PMA_BYTES_AVAILABLE_SIZE (0x1000) /* finn: Evaluated from "(4 * 1024)" */ + +typedef struct NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS { + /*! + * [in] Memory handle (RW memory) for streaming records. + * Size of this must be >= @ref pmaBufferOffset + @ref pmaBufferSize. + */ + NvHandle hMemPmaBuffer; + + /*! + * [in] Start offset of PMA buffer (offset in @ref hMemPmaBuffer). + */ + NV_DECLARE_ALIGNED(NvU64 pmaBufferOffset, 8); + + /*! + * [in] size of the buffer. This must be <= NVB0CC_PMA_BUFFER_SIZE_MAX. + */ + NV_DECLARE_ALIGNED(NvU64 pmaBufferSize, 8); + + /*! + * [in] Memory handle (RO memory) for streaming number of bytes available. + * Size of this must be of at least @ref pmaBytesAvailableOffset + + * @ref NVB0CC_PMA_BYTES_AVAILABLE_SIZE. + */ + NvHandle hMemPmaBytesAvailable; + + /*! + * [in] Start offset of PMA bytes available buffer (offset in @ref hMemPmaBytesAvailable). + */ + NV_DECLARE_ALIGNED(NvU64 pmaBytesAvailableOffset, 8); + + /*! + * [in] Enable ctxsw for PMA stream. + */ + NvBool ctxsw; + + /*! + * [out] The PMA Channel Index associated with a given PMA stream. + */ + NvU32 pmaChannelIdx; + + /*! + * [out] PMA buffer VA. Note that this is a HWPM Virtual address. + */ + NV_DECLARE_ALIGNED(NvU64 pmaBufferVA, 8); +} NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_FREE_PMA_STREAM + * + * Releases (unmap and free) PMA stream allocated through + * @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM. + * + */ +#define NVB0CC_CTRL_CMD_FREE_PMA_STREAM (0xb0cc0106) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS { + /*! + * [in] The PMA channel index associated with a given PMA stream. + */ + NvU32 pmaChannelIdx; +} NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_BIND_PM_RESOURCES + * + * Binds all PM resources reserved through @ref NVB0CC_CTRL_CMD_RESERVE_* + * and with @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM with PMA engine. + * After this call, interface is ready for programming a collection + * of counters. + * @Note: Any new PM resource reservation via NVB0CC_CTRL_CMD_RESERVE_* or + * @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM request after this call will fail, + * clients need to unbind (see @ref NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES) to + * reserve more resources. + * + * This can be unbound with @ref NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES. + * + */ +#define NVB0CC_CTRL_CMD_BIND_PM_RESOURCES (0xb0cc0107) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x7" */ + +/*! + * NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES + * + * Unbinds PM resources that were bound with @ref NVB0CC_CTRL_CMD_BIND_PM_RESOURCES + * + */ +#define NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES (0xb0cc0108) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x8" */ + +/*! + * NVB0CC_CTRL_CMD_PMA_STREAM_UPDATE_GET_PUT + * + * This command updates bytes consumed by the SW and optionally gets the + * current available bytes in the buffer. + * + */ +#define NVB0CC_CTRL_CMD_PMA_STREAM_UPDATE_GET_PUT (0xb0cc0109) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_AVAILABLE_BYTES_DEFAULT_VALUE 0xFFFFFFFF +#define NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS { + /*! + * [in] Total bytes consumed by SW since last update. + */ + NV_DECLARE_ALIGNED(NvU64 bytesConsumed, 8); + + /*! + * [in] Initiate streaming of the bytes available (see @ref hMemPmaBytesAvailable). + * RM will set the memory for streaming (see @ref hMemPmaBytesAvailable) to NVB0CC_AVAILABLE_BYTES_DEFAULT_VALUE and + * client can optionally wait (see @ref bWait) for it to change from this value. + */ + NvBool bUpdateAvailableBytes; + + /*! + * [in] Waits for available bytes to get updated + */ + NvBool bWait; + + /*! + * [out] Bytes available in the PMA buffer (see @ref hMemPmaBuffer) for SW to consume. + * This will only be populated if both bUpdateAvailableBytes and bWait are set + * to TRUE. + */ + NV_DECLARE_ALIGNED(NvU64 bytesAvailable, 8); + + /*! + * [in] If set to TRUE, current put pointer will be returned in @ref putPtr. + */ + NvBool bReturnPut; + + /*! + * [out] Current PUT pointer (MEM_HEAD). + * This will only be populated if bReturnPut is set to TRUE. + */ + NV_DECLARE_ALIGNED(NvU64 putPtr, 8); + + /*! + * [in] The PMA Channel Index associated with a given PMA stream. + */ + NvU32 pmaChannelIdx; +} NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS; + +/*! + * Maximum number of register operations allowed in a single request. + * @NOTE: @ref NVB0CC_REGOPS_MAX_COUNT is chosen to keep struct size + * of @ref NVB0CC_CTRL_EXEC_REG_OPS_PARAMS under 4KB. + */ +#define NVB0CC_REGOPS_MAX_COUNT (124) + +/*! + * NVB0CC_CTRL_CMD_EXEC_REG_OPS + * + * This command is used to submit an array containing one or more + * register operations for processing. Each entry in the + * array specifies a single read or write operation. Each entry is + * checked for validity in the initial pass: Only registers from PM area + * are allowed using this interface and only register from PM systems for + * which user has a valid reservation are allowed (see @ref NVB0CC_CTRL_CMD_RESERVE_*). + * Operation type (@ref NV2080_CTRL_GPU_REG_OP_TYPE_*) is not required to be passed in. + */ +#define NVB0CC_CTRL_CMD_EXEC_REG_OPS (0xb0cc010a) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_MESSAGE_ID" */ + +/*! + * Structure definition for register operation. See @ref NV2080_CTRL_GPU_REG_OP. + */ +typedef NV2080_CTRL_GPU_REG_OP NVB0CC_GPU_REG_OP; + +/*! + * Enumeration of different REG_OPS modes. This mode determines how a failure + * of a regop is handled in a batch of regops. + */ +typedef enum NVB0CC_REGOPS_MODE { + + /*! + * Either all regops will be executed or none of them will be executed. + * Failing regop will have the appropriate status (see @ref NVB0CC_GPU_REG_OP::regStatus). + */ + NVB0CC_REGOPS_MODE_ALL_OR_NONE = 0, + /*! + * All regops will be attempted and the ones that failed will have the + * the appropriate status (see @ref NVB0CC_GPU_REG_OP::regStatus). + */ + NVB0CC_REGOPS_MODE_CONTINUE_ON_ERROR = 1, +} NVB0CC_REGOPS_MODE; + +#define NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NVB0CC_CTRL_EXEC_REG_OPS_PARAMS { + /*! + * [in] Number of valid entries in the regOps array. This value cannot + * exceed NVB0CC_REGOPS_MAX_COUNT. + */ + NvU32 regOpCount; + + /*! + * [in] Specifies the mode for the entire operation see @ref NVB0CC_REGOPS_MODE. + */ + NVB0CC_REGOPS_MODE mode; + + /*! + * [out] Provides status for the entire operation. This is only valid for + * mode @ref NVB0CC_REGOPS_MODE_CONTINUE_ON_ERROR. + */ + NvBool bPassed; + + /*! + * [out] This is currently not populated. + */ + NvBool bDirect; + + /*! + * [in/out] An array (of fixed size NVB0CC_REGOPS_MAX_COUNT) of register read or write + * operations (see @ref NVB0CC_GPU_REG_OP) + * + */ + NVB0CC_GPU_REG_OP regOps[NVB0CC_REGOPS_MAX_COUNT]; +} NVB0CC_CTRL_EXEC_REG_OPS_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_RESERVE_PM_AREA_PC_SAMPLER + * + * Reserves the PC sampler system for use by the calling client. + * + * This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_PM_AREA_PC_SAMPLER. + * + * This command does not take any parameters. + * + * PC sampler is always context switched with a GR context, so reservation scope is + * always context. This requires that profiler object is instantiated with a valid GR + * context. See @ref NVB2CC_ALLOC_PARAMETERS. + */ + +#define NVB0CC_CTRL_CMD_RESERVE_PM_AREA_PC_SAMPLER (0xb0cc010b) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0xB" */ + +/*! + * NVB0CC_CTRL_CMD_RELEASE_PM_AREA_PC_SAMPLER + * + * Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_PM_AREA_PC_SAMPLER. + * + * This command does not take any parameters. + * + */ +#define NVB0CC_CTRL_CMD_RELEASE_PM_AREA_PC_SAMPLER (0xb0cc010c) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0xC" */ + +/*! + * NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS + * + * Gets the total high speed streaming credits available for the client. + * + * This command can only be performed after a bind using NVB0CC_CTRL_CMD_BIND_PM_RESOURCES. + * + */ +#define NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS (0xb0cc010d) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS { + NvU32 numCredits; +} NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_SET_HS_CREDITS_CHIPLET + * + * Sets per chiplet (pmm router) credits for high speed streaming for a pma channel. + * + * @note: This command resets the current credits to 0 before setting the new values also + * if programming fails, it will reset credits to 0 for all the chiplets. + * + */ +#define NVB0CC_CTRL_CMD_SET_HS_CREDITS (0xb0cc010e) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_MESSAGE_ID" */ + +typedef enum NVB0CC_CHIPLET_TYPE { + NVB0CC_CHIPLET_TYPE_INVALID = 0, + NVB0CC_CHIPLET_TYPE_FBP = 1, + NVB0CC_CHIPLET_TYPE_GPC = 2, + NVB0CC_CHIPLET_TYPE_SYS = 3, +} NVB0CC_CHIPLET_TYPE; + +typedef enum NVB0CC_HS_CREDITS_CMD_STATUS { + NVB0CC_HS_CREDITS_CMD_STATUS_OK = 0, + /*! + * More credits are requested than the total credits. Total credits can be queried using @ref NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS + */ + NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CREDITS = 1, + /*! + * Chiplet index is invalid. + */ + NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CHIPLET = 2, +} NVB0CC_HS_CREDITS_CMD_STATUS; + +typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO { + /*! + * Specifies the chiplet type @ref NVB0CC_CHIPLET_TYPE. + */ + NvU8 chipletType; + + /*! + * Specifies the logical index of the chiplet. + */ + NvU8 chipletIndex; + + /*! + * Specifies the number of credits for the chiplet. + */ + NvU16 numCredits; +} NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO; + +typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS { + /*! + * Status for the command @ref NVB0CC_HS_CREDITS_CMD_STATUS. + */ + NvU8 status; + + /*! + * Index of the failing @ref NVB0CC_CTRL_SET_HS_CREDITS_PARAMS::creditInfo entry. This + * is only relevant if status is NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CHIPLET. + */ + NvU8 entryIndex; +} NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS; + +#define NVB0CC_MAX_CREDIT_INFO_ENTRIES (63) + +#define NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NVB0CC_CTRL_SET_HS_CREDITS_PARAMS { + /*! + * [in] The PMA Channel Index associated with a given PMA stream. + */ + NvU8 pmaChannelIdx; + + /*! + * [in] Number of valid entries in creditInfo. + */ + NvU8 numEntries; + + /*! + * [out] Provides status for the entire operation. + */ + NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS statusInfo; + + /*! + * [in] Credit programming per chiplet + */ + NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO creditInfo[NVB0CC_MAX_CREDIT_INFO_ENTRIES]; +} NVB0CC_CTRL_SET_HS_CREDITS_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_GET_HS_CREDITS + * + * Gets per chiplet (pmm router) high speed streaming credits for a pma channel. + * + */ +#define NVB0CC_CTRL_CMD_GET_HS_CREDITS (0xb0cc010f) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0xF" */ + +typedef NVB0CC_CTRL_SET_HS_CREDITS_PARAMS NVB0CC_CTRL_GET_HS_CREDITS_PARAMS; + + + +/* _ctrlb0ccprofiler_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc06f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc06f.h new file mode 100644 index 0000000..1b493c7 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc06f.h @@ -0,0 +1,200 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc06f.finn +// + + + + +/* PASCAL_CHANNEL_GPFIFO_A control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrla06f.h" /* C06F is partially derived from A06F */ +#include "ctrl/ctrl906f.h" /* C06F is partially derived from 906F */ +#define NVC06F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xC06F, NVC06F_CTRL_##cat, idx) + +/* PASCAL_CHANNEL_GPFIFO_B command categories (6bits) */ +#define NVC06F_CTRL_RESERVED (0x00) +#define NVC06F_CTRL_GPFIFO (0x01) +#define NVC06F_CTRL_EVENT (0x02) + +/* + * NVC06F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVC06F_CTRL_CMD_NULL (0xc06f0000) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NVC06F_CTRL_GET_CLASS_ENGINEID + * + * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. + * + */ +#define NVC06F_CTRL_GET_CLASS_ENGINEID (0xc06f0101) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */ + +typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC06F_CTRL_GET_CLASS_ENGINEID_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVC06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS { + NVC06F_CTRL_GET_CLASS_ENGINEID_PARAMS params; +} NVC06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS; + + + +/* + * NVC06F_CTRL_RESET_CHANNEL + * + * Please see description of NVA06F_CTRL_RESET_CHANNEL for more information. + * + */ +#define NVC06F_CTRL_CMD_RESET_CHANNEL (0xc06f0102) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */ +typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC06F_CTRL_CMD_RESET_CHANNEL_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVC06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVC06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS { + NVC06F_CTRL_CMD_RESET_CHANNEL_PARAMS params; +} NVC06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS; + + + +/* + * NVC06F_CTRL_CMD_GPFIFO_SCHEDULE + * + * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. + * + */ +#define NVC06F_CTRL_CMD_GPFIFO_SCHEDULE (0xc06f0103) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */ +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC06F_CTRL_GPFIFO_SCHEDULE_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVC06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVC06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS { + NVC06F_CTRL_GPFIFO_SCHEDULE_PARAMS params; +} NVC06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS; + + + +/* + * NVC06F_CTRL_CMD_BIND + * + * Please see description of NVA06F_CTRL_CMD_BIND for more information. + */ +#define NVC06F_CTRL_CMD_BIND (0xc06f0104) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */ + +typedef NVA06F_CTRL_BIND_PARAMS NVC06F_CTRL_BIND_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVC06F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVC06F_CTRL_CMD_BIND_FINN_PARAMS { + NVC06F_CTRL_BIND_PARAMS params; +} NVC06F_CTRL_CMD_BIND_FINN_PARAMS; + + + +/* + * NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. +*/ +#define NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xc06f0205) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x5" */ + +typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS { + NVC06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS params; +} NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS; + + + +/* valid action values */ +#define NVC06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE +#define NVC06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE +#define NVC06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT + +/* + * NVC06F_CTRL_CMD_EVENT_SET_TRIGGER + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information. + */ +#define NVC06F_CTRL_CMD_EVENT_SET_TRIGGER (0xc06f0206) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */ + + + + + +/* + * NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO + * + * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. + * + */ +#define NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xc06f0107) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */ + +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC06F_CTRL_GET_MMU_FAULT_INFO_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS { + NV_DECLARE_ALIGNED(NVC06F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8); +} NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS; + + + +/* _ctrlc06f.h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc365.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc365.h new file mode 100644 index 0000000..fc23e13 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc365.h @@ -0,0 +1,331 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc365.finn +// + +#include "ctrl/ctrlxxxx.h" +#define NVC365_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xC365, NVC365_CTRL_##cat, idx) + + +#define NVC365_CTRL_RESERVED (0x00) +#define NVC365_CTRL_ACCESS_CNTR_BUFFER (0x01) + + +/* + * NVC365_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVC365_CTRL_CMD_NULL (0xc3650000) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_READ_GET + * + * This command provides the value of the GET register + * + * accessCntrBufferGetOffset [OUT] + * This parameter returns the value of the GET register + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_READ_GET (0xc3650101) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_GET_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_GET_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_GET_PARAMS { + NvU32 accessCntrBufferGetOffset; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_GET_PARAMS; + + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_WRITE_GET + * + * This command writes a value into the GET register + * + * accessCntrBufferGetValue [IN] + * This parameter specifies the new value of the GET register + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_WRITE_GET (0xc3650102) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_WRITE_GET_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_WRITE_GET_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_WRITE_GET_PARAMS { + NvU32 accessCntrBufferGetValue; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_WRITE_GET_PARAMS; + + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_READ_PUT + * + * This command provides the value of the PUT register + * + * accessCntrBufferPutOffset [OUT] + * This parameter returns the value of the PUT register + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_READ_PUT (0xc3650103) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_PUT_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_PUT_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_PUT_PARAMS { + NvU32 accessCntrBufferPutOffset; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_READ_PUT_PARAMS; + + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_ENABLE + * + * This command enables/disables the access counters + * It also sets up RM to either service or ignore the Access Counter interrupts. + * + * intrOwnership [IN] + * This parameter specifies whether RM should own the interrupt upon return + * enable [IN] + * NV_TRUE = Access counters will be enabled + * NV_FALSE = Access counters will be disabled + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_ENABLE (0xc3650104) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_PARAMS { + NvU32 intrOwnership; + NvBool enable; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_PARAMS; + +#define NVC365_CTRL_ACCESS_COUNTER_INTERRUPT_OWNERSHIP_NO_CHANGE (0x0) +#define NVC365_CTRL_ACCESS_COUNTER_INTERRUPT_OWNERSHIP_RM (0x1) +#define NVC365_CTRL_ACCESS_COUNTER_INTERRUPT_OWNERSHIP_NOT_RM (0x2) + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_SIZE + * + * This command provides the size of the notification buffer + * + * accessCntrBufferSize [OUT] + * This parameter returns the size of the notification buffer + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_SIZE (0xc3650105) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_SIZE_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_SIZE_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_SIZE_PARAMS { + NvU32 accessCntrBufferSize; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_SIZE_PARAMS; + + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS + * + * This command provides the access counter register mappings + * + * pAccessCntrBufferGet [OUT] + * This parameter returns the pointer to the GET register + * pAccessCntrBufferPut [OUT] + * This parameter returns the pointer to the PUT register + * pAccessCntrlBufferFull [OUT] + * This parameter returns the pointer to the FULL register + * pHubIntr [OUT] + * This parameter returns the pointer to the hub interrupt register + * pHubIntrEnSet [OUT] + * This parameter returns the pointer to the set register + * pHubIntrEnClear [OUT] + * This parameter returns the pointer to the clear register + * accessCntrMask [OUT] + * This parameter returns the interrupt mask + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS (0xc3650106) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pAccessCntrBufferGet, 8); + NV_DECLARE_ALIGNED(NvP64 pAccessCntrBufferPut, 8); + NV_DECLARE_ALIGNED(NvP64 pAccessCntrBufferFull, 8); + NV_DECLARE_ALIGNED(NvP64 pHubIntr, 8); + NV_DECLARE_ALIGNED(NvP64 pHubIntrEnSet, 8); + NV_DECLARE_ALIGNED(NvP64 pHubIntrEnClear, 8); + NvU32 accessCntrMask; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS_PARAMS; + + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_FULL_INFO + * + * This command gives information whether the buffer is full + * + * fullFlag [OUT] + * This parameter specifies whether the buffer is full + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_GET_FULL_INFO (0xc3650107) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_FULL_INFO_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_FULL_INFO_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_FULL_INFO_PARAMS { + NvBool fullFlag; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_FULL_INFO_PARAMS; + + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_RESET_COUNTERS + * + * This command resets access counters of specified type + * + * resetFlag [OUT] + * This parameter specifies that counters have been reset + * counterType [IN] + * This parameter specifies the type of counters that should be reset (MIMC, MOMC or ALL) + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_RESET_COUNTERS (0xc3650108) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_RESET_COUNTERS_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_RESET_COUNTERS_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_RESET_COUNTERS_PARAMS { + NvBool resetFlag; + NvU32 counterType; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_RESET_COUNTERS_PARAMS; + +#define NVC365_CTRL_ACCESS_COUNTER_TYPE_MIMC (0x0) +#define NVC365_CTRL_ACCESS_COUNTER_TYPE_MOMC (0x1) +#define NVC365_CTRL_ACCESS_COUNTER_TYPE_ALL (0x2) + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_SET_CONFIG + * + * This command configures the access counters + * + * mimcGranularity [IN] + * This parameter specifies the desired granularity for mimc (64K, 2M, 16M, 16G) + * momcGranularity [IN] + * This parameter specifies the desired granularity for momc (64K, 2M, 16M, 16G) + * mimcLimit [IN] + * This parameter specifies mimc limit (none, qtr, half, full) + * momcLimit [IN] + * This parameter specifies momc limit (none, qtr, half, full) + * threshold [IN] + * This parameter specifies the threshold + * flag [IN] + * This parameter is a bitmask denoting what configurations should be made + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_SET_CONFIG (0xc3650109) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_SET_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_SET_CONFIG_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NVC365_CTRL_ACCESS_CNTR_SET_CONFIG_PARAMS { + NvU32 mimcGranularity; + NvU32 momcGranularity; + NvU32 mimcLimit; + NvU32 momcLimit; + NvU32 threshold; + NvU32 cmd; +} NVC365_CTRL_ACCESS_CNTR_SET_CONFIG_PARAMS; + +#define NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_64K (0x0) +#define NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_2M (0x1) +#define NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_16M (0x2) +#define NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_16G (0x3) + +#define NVC365_CTRL_ACCESS_COUNTER_MIMC_LIMIT (0x0) +#define NVC365_CTRL_ACCESS_COUNTER_MOMC_LIMIT (0x1) + +#define NVC365_CTRL_ACCESS_COUNTER_USE_LIMIT_NONE (0x0) +#define NVC365_CTRL_ACCESS_COUNTER_USE_LIMIT_QTR (0x1) +#define NVC365_CTRL_ACCESS_COUNTER_USE_LIMIT_HALF (0x2) +#define NVC365_CTRL_ACCESS_COUNTER_USE_LIMIT_FULL (0x3) + +#define NVC365_CTRL_ACCESS_COUNTER_SET_MIMC_GRANULARITY (0x1) +#define NVC365_CTRL_ACCESS_COUNTER_SET_MOMC_GRANULARITY (0x2) +#define NVC365_CTRL_ACCESS_COUNTER_SET_MIMC_LIMIT (0x4) +#define NVC365_CTRL_ACCESS_COUNTER_SET_MOMC_LIMIT (0x8) +#define NVC365_CTRL_ACCESS_COUNTER_SET_THRESHOLD (0x10) + +/* + * NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_ENABLE_INTR + * + * This command enables the access counters interrupts + * + * enable [OUT] + * This parameter specifies that the access counters interrupts are enabled + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC365_CTRL_CMD_ACCESS_CNTR_BUFFER_ENABLE_INTR (0xc365010b) /* finn: Evaluated from "(FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID << 8) | NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_INTR_PARAMS_MESSAGE_ID" */ + +#define NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_INTR_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_INTR_PARAMS { + NvBool enable; +} NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_INTR_PARAMS; +/* _ctrlc365_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc369.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc369.h new file mode 100644 index 0000000..135de33 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc369.h @@ -0,0 +1,109 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc369.finn +// + +#include "ctrl/ctrlxxxx.h" +/* MMU_FAULT_BUFFER control commands and parameters */ + +#define NVC369_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xC369, NVC369_CTRL_##cat, idx) + +/* MMU_FAULT_BUFFER command categories (6bits) */ +#define NVC369_CTRL_RESERVED (0x00) +#define NVC369_CTRL_MMU_FAULT_BUFFER (0x01) + +/* + * NVC369_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVC369_CTRL_CMD_NULL (0xc3690000) /* finn: Evaluated from "(FINN_MMU_FAULT_BUFFER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + + +/* + * NVC369_CTRL_CMD_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUFFER + * + * This call creates and registers a client buffer for the non replayable faults + * + * pShadowBuffer [OUT] + * This parameter represents the pointer to the shadow buffer + * + * pShadowBufferContext [OUT] + * Execution context for pShadowBuffer queue + * + * bufferSize [OUT] + * Size in bytes of the shadow buffer for non replayable faults + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC369_CTRL_CMD_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF (0xc3690101) /* finn: Evaluated from "(FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER_INTERFACE_ID << 8) | NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF_PARAMS_MESSAGE_ID" */ + +#define NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pShadowBuffer, 8); + NV_DECLARE_ALIGNED(NvP64 pShadowBufferContext, 8); + NvU32 bufferSize; +} NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF_PARAMS; + + +/* + * NVC369_CTRL_CMD_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUFFER + * + * This call unregisters and destroys a client buffer for the non replayable + * faults + * + * pShadowBuffer [IN] + * This parameter represents the pointer to the shadow buffer + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVC369_CTRL_CMD_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF (0xc3690102) /* finn: Evaluated from "(FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER_INTERFACE_ID << 8) | NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS_MESSAGE_ID" */ + +#define NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pShadowBuffer, 8); +} NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS; + +/* _ctrlc369_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc36f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc36f.h new file mode 100644 index 0000000..ddfce20 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc36f.h @@ -0,0 +1,275 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc36f.finn +// + + + + +/* VOLTA_CHANNEL_GPFIFO_A control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl906f.h" /* C36F is partially derived from 906F */ +#include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */ +#define NVC36F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xC36F, NVC36F_CTRL_##cat, idx) + +/* VOLTA_CHANNEL_GPFIFO_A command categories (6bits) */ +#define NVC36F_CTRL_RESERVED (0x00) +#define NVC36F_CTRL_GPFIFO (0x01) +#define NVC36F_CTRL_EVENT (0x02) + +/* + * NVC36F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned is: NV_OK +*/ +#define NVC36F_CTRL_CMD_NULL (0xc36f0000) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + + +/* + * NVC36F_CTRL_GET_CLASS_ENGINEID + * + * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. + * + */ +#define NVC36F_CTRL_GET_CLASS_ENGINEID (0xc36f0101) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */ + +typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC36F_CTRL_GET_CLASS_ENGINEID_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVC36F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC36F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS { + NVC36F_CTRL_GET_CLASS_ENGINEID_PARAMS params; +} NVC36F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS; + + + +/* + * NVC36F_CTRL_RESET_CHANNEL + * + * Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information. + * + */ +#define NVC36F_CTRL_CMD_RESET_CHANNEL (0xc36f0102) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */ + +typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC36F_CTRL_CMD_RESET_CHANNEL_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVC36F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVC36F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS { + NVC36F_CTRL_CMD_RESET_CHANNEL_PARAMS params; +} NVC36F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS; + + + +/* + * NVC36F_CTRL_CMD_GPFIFO_SCHEDULE + * + * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. + * + */ +#define NVC36F_CTRL_CMD_GPFIFO_SCHEDULE (0xc36f0103) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */ + +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC36F_CTRL_GPFIFO_SCHEDULE_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVC36F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVC36F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS { + NVC36F_CTRL_GPFIFO_SCHEDULE_PARAMS params; +} NVC36F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS; + + + +/* + * NVC36F_CTRL_CMD_BIND + * + * Please see description of NVA06F_CTRL_CMD_BIND for more information. + */ +#define NVC36F_CTRL_CMD_BIND (0xc36f0104) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */ + +typedef NVA06F_CTRL_BIND_PARAMS NVC36F_CTRL_BIND_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVC36F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVC36F_CTRL_CMD_BIND_FINN_PARAMS { + NVC36F_CTRL_BIND_PARAMS params; +} NVC36F_CTRL_CMD_BIND_FINN_PARAMS; + + + +/* + * NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. +*/ +#define NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xc36f0205) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x5" */ + +typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC36F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NVC36F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE +#define NVC36F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE +#define NVC36F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT + +/* + * NVC36F_CTRL_CMD_EVENT_SET_TRIGGER + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information. + */ +#define NVC36F_CTRL_CMD_EVENT_SET_TRIGGER (0xc36f0206) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */ + + + + + +/* + * NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO + * + * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. + * + */ +#define NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO (0xc36f0107) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */ + +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC36F_CTRL_GET_MMU_FAULT_INFO_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS { + NV_DECLARE_ALIGNED(NVC36F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8); +} NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS; + + + +/* + * NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN + * + * This command returns an opaque work submit token to the caller which + * can be used to write to doorbell register to finish submitting work. If + * the client has provided an error context handle during channel allocation, + * and the error context is large enough to write the doorbell token, a + * notification at index NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN + * will be sent with the work submit token value. This index may be modified + * by NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX. + * + * workSubmitToken The 32-bit work submit token + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + * + */ + +#define NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN (0xc36f0108) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID" */ + +#define NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS { + NvU32 workSubmitToken; +} NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS; + +/** + * NVC36F_CTRL_CMD_GPFIFO_UPDATE_FAULT_METHOD_BUFFER + * + * This command updates the HOST CE Fault method buffer + * data structure of Virtual channel created for SR-IOV guest. It will also + * update the fault method buffer address in the instance block of the channel + * + * bar2Addr[] + * Array contains the Virtual BAR2 address mapped by the Guest during channel + * creation. + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_INSUFFICIENT_RESOURCES + * + */ +#define NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES 0x2 +#define NVC36F_CTRL_CMD_GPFIFO_UPDATE_FAULT_METHOD_BUFFER (0xc36f0109) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS_MESSAGE_ID" */ + +#define NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS { + NV_DECLARE_ALIGNED(NvU64 bar2Addr[NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES], 8); +} NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS; + +/* + * NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX + * + * This command updates the notifier index within the error context notifier + * to write the doorbell token to. This interface cannot be used to cause the + * token to overwrite the RC notification slot. The notification slot + * referred to by the passed index must be within the bounds of the error + * context notifier object. In the case that multiple channels share the same + * error context, it is not illegal for the client to set the same index for + * multiple channels (however it is not recommended). + * + * [IN] index + * Notification slot to write the doorbell token. The initial value of this + * index is NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX (0xc36f010a) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_MESSAGE_ID" */ + +#define NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS { + NvU32 index; +} NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS; + +/* _ctrlc36f.h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370base.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370base.h new file mode 100644 index 0000000..c132cc0 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370base.h @@ -0,0 +1,67 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc370/ctrlc370base.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NVC370_DISPLAY control commands and parameters */ + +#define NVC370_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0XC370, NVC370_CTRL_##cat, idx) + +/* NVC370_DISPLAY command categories (6bits) */ +#define NVC370_CTRL_RESERVED (0x00) +#define NVC370_CTRL_CHNCTL (0x01) +#define NVC370_CTRL_RG (0x02) +#define NVC370_CTRL_SEQ (0x03) +#define NVC370_CTRL_OR (0x04) +#define NVC370_CTRL_INST (0x05) +#define NVC370_CTRL_VERIF (0x06) +#define NVC370_CTRL_SYSTEM (0x07) +#define NVC370_CTRL_EVENT (0x09) + +// This struct must be the first member of all C370 control calls +typedef struct NVC370_CTRL_CMD_BASE_PARAMS { + NvU32 subdeviceIndex; +} NVC370_CTRL_CMD_BASE_PARAMS; + + +/* + * NVC370_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVC370_CTRL_CMD_NULL (0xc3700000) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + +/* _ctrlc370base_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h new file mode 100644 index 0000000..a231232 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h @@ -0,0 +1,300 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc370/ctrlc370chnc.finn +// + +#include "ctrl/ctrlc370/ctrlc370base.h" +/* C370 is partially derived from 5070 */ +#include "ctrl/ctrl5070/ctrl5070chnc.h" + + + + +#define NVC370_CTRL_CMD_CHANNEL_STATE_IDLE NVBIT(0) +#define NVC370_CTRL_CMD_CHANNEL_STATE_QUIESCENT1 NVBIT(2) +#define NVC370_CTRL_CMD_CHANNEL_STATE_QUIESCENT2 NVBIT(3) +#define NVC370_CTRL_CMD_CHANNEL_STATE_BUSY NVBIT(6) +#define NVC370_CTRL_CMD_CHANNEL_STATE_DEALLOC NVBIT(7) +#define NVC370_CTRL_CMD_CHANNEL_STATE_DEALLOC_LIMBO NVBIT(8) +#define NVC370_CTRL_CMD_CHANNEL_STATE_EFI_INIT1 NVBIT(11) +#define NVC370_CTRL_CMD_CHANNEL_STATE_EFI_INIT2 NVBIT(12) +#define NVC370_CTRL_CMD_CHANNEL_STATE_EFI_OPERATION NVBIT(13) +#define NVC370_CTRL_CMD_CHANNEL_STATE_VBIOS_INIT1 NVBIT(14) +#define NVC370_CTRL_CMD_CHANNEL_STATE_VBIOS_INIT2 NVBIT(15) +#define NVC370_CTRL_CMD_CHANNEL_STATE_VBIOS_OPERATION NVBIT(16) +#define NVC370_CTRL_CMD_CHANNEL_STATE_UNCONNECTED NVBIT(17) +#define NVC370_CTRL_CMD_CHANNEL_STATE_INIT1 NVBIT(18) +#define NVC370_CTRL_CMD_CHANNEL_STATE_INIT2 NVBIT(19) +#define NVC370_CTRL_CMD_CHANNEL_STATE_SHUTDOWN1 NVBIT(20) +#define NVC370_CTRL_CMD_CHANNEL_STATE_SHUTDOWN2 NVBIT(21) + +#define NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CORE 1 +#define NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW 32 +#define NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW_IMM 32 +#define NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WRITEBACK 8 +#define NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CURSOR 8 + +/* + * NVC370_CTRL_CMD_IDLE_CHANNEL + * + * This command tries to wait or forces the desired channel state. + * + * channelClass + * This field indicates the hw class number (0xC378 - 0xC37E). + * It's defined in the h/w header (i.e. clc37d.h, etc.). + * + * channelInstance + * This field indicates which instance of the channelClass the cmd is + * meant for. (zero-based) + * + * desiredChannelStateMask + * This field indicates the desired channel states. When more than + * one bit is set, RM will return whenever it finds hardware on one + * of the states in the bistmask. + * Normal options are IDLE, QUIESCENT1 and QUIESCENT2. + * Verif only option includes BUSY as well. + * Note: + * (1) When QUIESCENT1 or QUIESCENT2 is chosen only one bit should + * be set in the bitmask. RM will ignore any other state. + * (2) Accelerators should not be required for QUIESCENT states as + * RM tries to ensure QUIESCENT forcibly on it's own. + * + * accelerators + * What accelerator bits should be used if RM timesout trying to + * wait for the desired state. This is not yet implemented since it + * should normally not be required to use these. Usage of accelerators + * should be restricted and be done very carefully as they may have + * undesirable effects. + * NOTE: accelerators should not be used directly in production code. + * + * timeout + * Timeout to use when waiting for the desired state. This is also for + * future expansion and not yet implemented. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_TIMEOUT + */ +#define NVC370_CTRL_CMD_IDLE_CHANNEL (0xc3700101) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NVC370_CTRL_IDLE_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NVC370_CTRL_IDLE_CHANNEL_MAX_INSTANCE_CORE NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CORE +#define NVC370_CTRL_IDLE_CHANNEL_MAX_INSTANCE_WINDOW NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW +#define NVC370_CTRL_IDLE_CHANNEL_MAX_INSTANCE_WINDOW_IMM NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW_IMM +#define NVC370_CTRL_IDLE_CHANNEL_MAX_INSTANCE_WRITEBACK NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WRITEBACK +#define NVC370_CTRL_IDLE_CHANNEL_MAX_INSTANCE_CURSOR NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CURSOR + +#define NVC370_CTRL_IDLE_CHANNEL_STATE_IDLE NVC370_CTRL_CMD_CHANNEL_STATE_IDLE +#define NVC370_CTRL_IDLE_CHANNEL_STATE_QUIESCENT1 NVC370_CTRL_CMD_CHANNEL_STATE_QUIESCENT1 +#define NVC370_CTRL_IDLE_CHANNEL_STATE_QUIESCENT2 NVC370_CTRL_CMD_CHANNEL_STATE_QUIESCENT2 + +#define NVC370_CTRL_IDLE_CHANNEL_STATE_BUSY NVC370_CTRL_CMD_CHANNEL_STATE_BUSY + +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_NONE (0x00000000) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_PI (NVBIT(0)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_NOTIF (NVBIT(1)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_SEMA (NVBIT(2)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_INTERLOCK (NVBIT(3)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_FLIPLOCK (NVBIT(4)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_TRASH_ONLY (NVBIT(5)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_TRASH_AND_ABORT (NVBIT(6)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_SYNCPOINT (NVBIT(7)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_TIMESTAMP (NVBIT(8)) +#define NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_MGI (NVBIT(9)) + +#define NVC370_CTRL_IDLE_CHANNEL_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC370_CTRL_IDLE_CHANNEL_PARAMS { + NVC370_CTRL_CMD_BASE_PARAMS base; + NvU32 channelClass; + NvU32 channelInstance; + NvU32 desiredChannelStateMask; + NvU32 accelerators; // For future expansion. Not yet implemented + NvU32 timeout; // For future expansion. Not yet implemented + NvBool restoreDebugMode; +} NVC370_CTRL_IDLE_CHANNEL_PARAMS; + +/* + * NVC370_CTRL_CMD_SET_ACCL + * + * This command turns accelerators on and off. The use of this command + * should be restricted as it may have undesirable effects. It's + * purpose is to provide a mechanism for clients to use the + * accelerator bits to get into states that are either not detectable + * by the RM or may take longer to reach than we think is reasonable + * to wait in the RM. + * + * NVC370_CTRL_CMD_GET_ACCL + * + * This command queries the current state of the accelerators. + * + * channelClass + * This field indicates the hw class number (0xC378 - 0xC37E). + * It's defined in the h/w header (i.e. clc37d.h, etc.). + * + * channelInstance + * This field indicates which instance of the channelClass the cmd is + * meant for. (zero-based) + * + * accelerators + * Accelerators to be set in the SET_ACCEL command. Returns the + * currently set accelerators on the GET_ACCEL command. + */ + + +/* + * + * accelMask + * A mask to specify which accelerators to change with the + * SET_ACCEL command. This field does nothing in the GET_ACCEL + * command. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_CHANNEL + * NV_ERR_INVALID_OWNER + * NV_ERR_GENERIC + * + */ + +#define NVC370_CTRL_CMD_SET_ACCL (0xc3700102) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NVC370_CTRL_SET_ACCL_PARAMS_MESSAGE_ID" */ + +#define NVC370_CTRL_CMD_GET_ACCL (0xc3700103) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | 0x3" */ + +#define NVC370_CTRL_ACCL_MAX_INSTANCE_CORE NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CORE +#define NVC370_CTRL_ACCL_MAX_INSTANCE_WINDOW NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW +#define NVC370_CTRL_ACCL_MAX_INSTANCE_WINDOW_IMM NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW_IMM +#define NVC370_CTRL_ACCL_MAX_INSTANCE_WRITEBACK NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WRITEBACK +#define NVC370_CTRL_ACCL_MAX_INSTANCE_CURSOR NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CURSOR + +#define NVC370_CTRL_ACCL_NONE NVC370_CTRL_IDLE_CHANNEL_ACCL_NONE +#define NVC370_CTRL_ACCL_IGNORE_PI NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_PI +#define NVC370_CTRL_ACCL_SKIP_NOTIF NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_NOTIF +#define NVC370_CTRL_ACCL_SKIP_SEMA NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_SEMA +#define NVC370_CTRL_ACCL_IGNORE_INTERLOCK NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_INTERLOCK +#define NVC370_CTRL_ACCL_IGNORE_FLIPLOCK NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_FLIPLOCK +#define NVC370_CTRL_ACCL_TRASH_ONLY NVC370_CTRL_IDLE_CHANNEL_ACCL_TRASH_ONLY +#define NVC370_CTRL_ACCL_TRASH_AND_ABORT NVC370_CTRL_IDLE_CHANNEL_ACCL_TRASH_AND_ABORT +#define NVC370_CTRL_ACCL_SKIP_SYNCPOINT NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_SYNCPOINT +#define NVC370_CTRL_ACCL_IGNORE_TIMESTAMP NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_TIMESTAMP +#define NVC370_CTRL_ACCL_IGNORE_MGI NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_MGI +#define NVC370_CTRL_SET_ACCL_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVC370_CTRL_SET_ACCL_PARAMS { + NVC370_CTRL_CMD_BASE_PARAMS base; + NvU32 channelClass; + NvU32 channelInstance; + NvU32 accelerators; + NvU32 accelMask; +} NVC370_CTRL_SET_ACCL_PARAMS; +typedef NVC370_CTRL_SET_ACCL_PARAMS NVC370_CTRL_GET_ACCL_PARAMS; + +// FINN PORT: The below type was generated by the FINN port to +// ensure that all API's have a unique structure associated +// with them! +#define NVC370_CTRL_CMD_GET_ACCL_FINN_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVC370_CTRL_CMD_GET_ACCL_FINN_PARAMS { + NVC370_CTRL_GET_ACCL_PARAMS params; +} NVC370_CTRL_CMD_GET_ACCL_FINN_PARAMS; + + + + +/* + * NVC370_CTRL_CMD_GET_CHANNEL_INFO + * + * This command returns the current channel state. + * + * channelClass + * This field indicates the hw class number (0xC378 - 0xC37E). + * It's defined in the h/w header (i.e. clc37d.h, etc.). + * + * channelInstance + * This field indicates which instance of the channelClass the cmd is + * meant for. (zero-based) + * + * channelState + * This field indicates the desired channel state in a mask form that + * is compatible with NVC370_CTRL_CMD_IDLE_CHANNEL. A mask format + * allows clients to check for one from a group of states. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + * + * Display driver uses this call to ensure that all it's methods have + * propagated through hardware's internal fifo + * (NVC370_CTRL_GET_CHANNEL_INFO_STATE_NO_METHOD_PENDING) before it calls + * RM to check whether or not the mode it set up in Assembly State Cache will + * be possible. Note that display driver can not use completion notifier in + * this case because completion notifier is associated with Update and Update + * will propagate the state from Assembly to Armed and when checking the + * possibility of a mode, display driver wouldn't want Armed state to be + * affected. + */ + + + +#define NVC370_CTRL_CMD_GET_CHANNEL_INFO (0xc3700104) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NVC370_CTRL_CMD_GET_CHANNEL_INFO_PARAMS_MESSAGE_ID" */ + +#define NVC370_CTRL_GET_CHANNEL_INFO_MAX_INSTANCE_CORE NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CORE +#define NVC370_CTRL_GET_CHANNEL_INFO_MAX_INSTANCE_WINDOW NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW +#define NVC370_CTRL_GET_CHANNEL_INFO_MAX_INSTANCE_WINDOW_IMM NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW_IMM +#define NVC370_CTRL_GET_CHANNEL_INFO_MAX_INSTANCE_WRITEBACK NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WRITEBACK +#define NVC370_CTRL_GET_CHANNEL_INFO_MAX_INSTANCE_CURSOR NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CURSOR + +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_IDLE NVC370_CTRL_CMD_CHANNEL_STATE_IDLE +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_BUSY NVC370_CTRL_CMD_CHANNEL_STATE_BUSY +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_DEALLOC NVC370_CTRL_CMD_CHANNEL_STATE_DEALLOC +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_DEALLOC_LIMBO NVC370_CTRL_CMD_CHANNEL_STATE_DEALLOC_LIMBO +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_EFI_INIT1 NVC370_CTRL_CMD_CHANNEL_STATE_EFI_INIT1 +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_EFI_INIT2 NVC370_CTRL_CMD_CHANNEL_STATE_EFI_INIT2 +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_EFI_OPERATION NVC370_CTRL_CMD_CHANNEL_STATE_EFI_OPERATION +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_VBIOS_INIT1 NVC370_CTRL_CMD_CHANNEL_STATE_VBIOS_INIT1 +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_VBIOS_INIT2 NVC370_CTRL_CMD_CHANNEL_STATE_VBIOS_INIT2 +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_VBIOS_OPERATION NVC370_CTRL_CMD_CHANNEL_STATE_VBIOS_OPERATION +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_UNCONNECTED NVC370_CTRL_CMD_CHANNEL_STATE_UNCONNECTED +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_INIT1 NVC370_CTRL_CMD_CHANNEL_STATE_INIT1 +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_INIT2 NVC370_CTRL_CMD_CHANNEL_STATE_INIT2 +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_SHUTDOWN1 NVC370_CTRL_CMD_CHANNEL_STATE_SHUTDOWN1 +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_SHUTDOWN2 NVC370_CTRL_CMD_CHANNEL_STATE_SHUTDOWN2 +#define NVC370_CTRL_GET_CHANNEL_INFO_STATE_NO_METHOD_PENDING NVC370_CTRL_GET_CHANNEL_INFO_STATE_IDLE +#define NVC370_CTRL_CMD_GET_CHANNEL_INFO_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVC370_CTRL_CMD_GET_CHANNEL_INFO_PARAMS { + NVC370_CTRL_CMD_BASE_PARAMS base; + NvU32 channelClass; + NvU32 channelInstance; + NvBool IsChannelInDebugMode; + NvU32 channelState; +} NVC370_CTRL_CMD_GET_CHANNEL_INFO_PARAMS; + + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h new file mode 100644 index 0000000..ef18c7d --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc370/ctrlc370event.finn +// + +#include "ctrl/ctrlc370/ctrlc370base.h" +/* C370 is partially derived from 5070 */ +#include "ctrl/ctrl5070/ctrl5070event.h" + + + + + +/* valid action values */ +#define NVC370_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE +#define NVC370_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE +#define NVC370_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT + +/* _ctrlc370event_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370rg.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370rg.h new file mode 100644 index 0000000..2a49284 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370rg.h @@ -0,0 +1,123 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc370/ctrlc370rg.finn +// + +#include "ctrl/ctrlc370/ctrlc370base.h" +/* C370 is partially derived from 5070 */ +#include "ctrl/ctrl5070/ctrl5070rg.h" + + + + +/* + * NVC370_CTRL_CMD_GET_LOCKPINS_CAPS + * + * This command returns lockpins for the specified pinset, + * as well as lockpins' HW capabilities. + * + * pinset [in] + * This parameter takes the pinset whose corresponding + * lockpin numbers need to be determined. This only affects + * the return value for the RaterLock and FlipLock pins. + * + * frameLockPin [out] + * This parameter returns the FrameLock pin index. + * + * rasterLockPin [out] + * This parameter returns the RasterLock pin index. + * + * flipLockPin [out] + * This parameter returns the FlipLock pin index. + * + * stereoPin [out] + * This parameter returns the Stereo pin index. + * + * numScanLockPins [out] + * This parameter returns the HW capability of ScanLock pins. + * + * numFlipLockPins [out] + * This parameter returns the HW capability of FlipLock pins. + * + * numStereoPins [out] + * This parameter returns the HW capability of Stereo pins. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NVC370_CTRL_CMD_GET_LOCKPINS_CAPS (0xc3700201) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_RG_INTERFACE_ID << 8) | NVC370_CTRL_GET_LOCKPINS_CAPS_PARAMS_MESSAGE_ID" */ + +#define NVC370_CTRL_GET_LOCKPINS_CAPS_FRAME_LOCK_PIN_NONE (0xffffffff) +#define NVC370_CTRL_GET_LOCKPINS_CAPS_RASTER_LOCK_PIN_NONE (0xffffffff) +#define NVC370_CTRL_GET_LOCKPINS_CAPS_FLIP_LOCK_PIN_NONE (0xffffffff) +#define NVC370_CTRL_GET_LOCKPINS_CAPS_STEREO_PIN_NONE (0xffffffff) +#define NVC370_CTRL_GET_LOCKPINS_CAPS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC370_CTRL_GET_LOCKPINS_CAPS_PARAMS { + NVC370_CTRL_CMD_BASE_PARAMS base; + NvU32 pinset; + NvU32 frameLockPin; + NvU32 rasterLockPin; + NvU32 flipLockPin; + NvU32 stereoPin; + NvU32 numScanLockPins; + NvU32 numFlipLockPins; + NvU32 numStereoPins; +} NVC370_CTRL_GET_LOCKPINS_CAPS_PARAMS; + +/* + * NVC370_CTRL_CMD_SET_SWAPRDY_GPIO_WAR + * + * This command switches SWAP_READY_OUT GPIO between SW + * and HW control to WAR bug 200374184 + * + * bEnable [in]: + * This parameter indicates enable/disable external fliplock + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ + +#define NVC370_CTRL_CMD_SET_SWAPRDY_GPIO_WAR (0xc3700202) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_RG_INTERFACE_ID << 8) | NVC370_CTRL_SET_SWAPRDY_GPIO_WAR_PARAMS_MESSAGE_ID" */ + +#define NVC370_CTRL_SET_SWAPRDY_GPIO_WAR_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVC370_CTRL_SET_SWAPRDY_GPIO_WAR_PARAMS { + NVC370_CTRL_CMD_BASE_PARAMS base; + NvBool bEnable; +} NVC370_CTRL_SET_SWAPRDY_GPIO_WAR_PARAMS; + + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370verif.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370verif.h new file mode 100644 index 0000000..d891974 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc370/ctrlc370verif.h @@ -0,0 +1,133 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc370/ctrlc370verif.finn +// + +#include "ctrl/ctrlc370/ctrlc370base.h" +/* C370 is partially derived from 5070 */ +#include "ctrl/ctrl5070/ctrl5070verif.h" + + + + +#define NVC370_CTRL_CMD_GET_FORCE_MODESWITCH_FLAGS_OVERRIDES (0xc3700601) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_VERIF_INTERFACE_ID << 8) | NVC370_CTRL_CMD_GET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS_MESSAGE_ID" */ + +#define NVC370_CTRL_CMD_GET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC370_CTRL_CMD_GET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS { + NVC370_CTRL_CMD_BASE_PARAMS base; + NvU32 headInstance; + NvU32 modesetValue; +} NVC370_CTRL_CMD_GET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS; + +/* + * NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES + * + * This command sets modeswitch flags, prior to a modeset. The flags will be + * automatically cleared at the end of each modeset, so this function must be + * called for each modeset where overrides are desired. + * + * headInstance + * this field specifies the head for which modeswitch flags will be overridden + * + * modesetMaskValid + * this field specifies the maskset at which modeswitch flags will be overridden + * + * modesetValue + * this field specifies the override value + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES (0xc3700602) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_VERIF_INTERFACE_ID << 8) | NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS_MESSAGE_ID" */ + +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS { + NVC370_CTRL_CMD_BASE_PARAMS base; + NvU32 headInstance; + NvU32 modesetMaskValid; + NvU32 modesetValue; +} NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS; + +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_BLANK 0:0 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_BLANK_VALID 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_BLANK_INVALID 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK 1:1 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_VALID 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_INVALID 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_SHUTDOWN 2:2 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_SHUTDOWN_VALID 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_SHUTDOWN_INVALID 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOSHUTDOWN 3:3 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOSHUTDOWN_VALID 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOSHUTDOWN_INVALID 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_CHANGE_VPLL 4:4 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_CHANGE_VPLL_VALID 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_CHANGE_VPLL_INVALID 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOCHANGE_VPLL 5:5 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOCHANGE_VPLL_VALID 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOCHANGE_VPLL_INVALID 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_WAKEUP 6:6 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_WAKEUP_VALID 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_WAKEUP_INVALID 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_SHUTDOWN 7:7 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_SHUTDOWN_VALID 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_MASK_VALID_FORCE_NOBLANK_SHUTDOWN_INVALID 0x00000000 + + +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_BLANK 0:0 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_BLANK_YES 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_BLANK_NO 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK 1:1 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_YES 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_NO 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_SHUTDOWN 2:2 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_SHUTDOWN_YES 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_SHUTDOWN_NO 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOSHUTDOWN 3:3 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOSHUTDOWN_YES 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOSHUTDOWN_NO 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_CHANGE_VPLL 4:4 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_CHANGE_VPLL_YES 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_CHANGE_VPLL_NO 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOCHANGE_VPLL 5:5 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOCHANGE_VPLL_YES 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOCHANGE_VPLL_NO 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_WAKEUP 6:6 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_WAKEUP_YES 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_WAKEUP_NO 0x00000000 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_SHUTDOWN 7:7 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_SHUTDOWN_YES 0x00000001 +#define NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_VALUE_FORCE_NOBLANK_SHUTDOWN_NO 0x00000000 + + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc372/ctrlc372base.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc372/ctrlc372base.h new file mode 100644 index 0000000..2d4aea5 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc372/ctrlc372base.h @@ -0,0 +1,61 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc372/ctrlc372base.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NVC372_DISPLAY_SW control commands and parameters */ + +#define NVC372_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0XC372, NVC372_CTRL_##cat, idx) + +/* NVC372_DISPLAY_SW command categories (6 bits) */ +#define NVC372_CTRL_RESERVED (0x00) +#define NVC372_CTRL_CHNCTL (0x01) +#define NVC372_CTRL_VERIF (0x02) + +/* + * NVC372_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVC372_CTRL_CMD_NULL (0xc3720000) /* finn: Evaluated from "(FINN_NVC372_DISPLAY_SW_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + +// This struct must be the first member of all +// C372 control calls +typedef struct NVC372_CTRL_CMD_BASE_PARAMS { + NvU32 subdeviceIndex; +} NVC372_CTRL_CMD_BASE_PARAMS; + +/* _ctrlc372base_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h new file mode 100644 index 0000000..743663c --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h @@ -0,0 +1,721 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc372/ctrlc372chnc.finn +// + +#include "nvdisptypes.h" +#include "ctrl/ctrlc372/ctrlc372base.h" + +#define NVC372_CTRL_MAX_POSSIBLE_HEADS 8 +#define NVC372_CTRL_MAX_POSSIBLE_WINDOWS 32 + +#define NVC372_CTRL_CMD_IS_MODE_POSSIBLE (0xc3720101) /* finn: Evaluated from "(FINN_NVC372_DISPLAY_SW_CHNCTL_INTERFACE_ID << 8) | NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS_MESSAGE_ID" */ + +/* + * NVC372_CTRL_CMD_IS_MODE_POSSIBLE + * + * This command tells whether or not the specified display config is possible. + * A config might not be possible if the display requirements exceed the GPU + * capabilities. Display requirements will be higher with more display + * surfaces, higher resolutions, higher downscaling factors, etc. GPU + * capabilities are determined by clock frequencies, the width of data pipes, + * amount of mempool available, number of thread groups available, etc. + * + * Inputs: + * head.headIndex + * This is the hardware index number for the head. Only active heads + * should be included in the input structure. + * + * head.maxPixelClkKHz + * This parameter specifies the pixel scanout rate (in KHz). + * + * head.rasterSize + * This structure specifies the total width and height of the raster that + * is sent to the display. (The width and height are also referred to as + * HTotal and VTotal, respectively.) + * + * head.rasterBlankStart + * X specifies the pixel column where horizontal blanking begins; + * Y specifies the pixel row where vertical blanking begins. + * + * head.rasterBlankEnd + * X specifies the pixel column where horizontal blanking ends; + * Y specifies the pixel row where vertical blanking ends. + * + * head.rasterVertBlank2 + * X and Y specify the pixel column/row where horizontal/vertical blanking + * ends on the second field of every pair for an interlaced raster. This + * field is not used when the raster is progressive. + * + * head.control.masterLockMode + * head.control.masterLockPin + * head.control.slaveLockMode + * head.control.slaveLockPin + * Heads that are raster locked or frame locked together will have + * synchronized timing. For example, vblank will occur at the same time on + * all of the heads that are locked together. + * + * "LockMode" tells if a head is raster locked, frame locked, or not locked. + * + * "LockPin" tells which heads are in a group of locked heads. There + * should be one master per group, and all slave heads that are locked to + * that master should have the same slaveLockPin number as the master's + * masterLockPin number. + * + * Note: The LockModes and LockPins are used only if the min v-pstate is + * required (i.e., if NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE + * is set). + * + * head.maxDownscaleFactorH + * head.maxDownscaleFactorV + * maxDownscaleFactorH and maxDownscaleFactorV represent the maximum amount + * by which the the composited image can be reduced in size, horizontally + * and vertically, respectively, multiplied by 0x400. For example, if the + * scaler input width is 1024, and the scaler output width is 2048, the + * downscale factor would be 1024 / 2048 = 0.5, and multiplying by 0x400 + * would give 512. + * + * head.outputScalerVerticalTaps + * scalerVerticalTaps indicates the maximum number of vertical taps + * allowed in the output scaler. + * + * Note that there are no #defines for tap values; the parameter is simply + * the number of taps (e.g., "2" for 2 taps). + * + * head.bUpscalingAllowedV + * bUpscalingAllowed indicates whether or not the composited image can be + * increased in size, vertically. + * + * head.bOverfetchEnabled + * bOverfetchEnabled indicates whether or not the vertical overfetch is + * enabled in postcomp scaler. + * + * head.minFrameIdle.leadingRasterLines + * leadingRasterLines defines the number of lines between the start of the + * frame (vsync) and the start of the active region. This includes Vsync, + * Vertical Back Porch, and the top part of the overscan border. The + * minimum value is 2 because vsync and VBP must be at least 1 line each. + * + * head.minFrameIdle.trailingRasterLines + * trailingRasterLines defines the number of lines between the end of the + * active region and the end of the frame. This includes the bottom part + * of the overscan border and the Vertical Front Porch. + * + * head.lut + * This parameter specifies whether or not the output LUT is enabled, and + * the size of the LUT. The parameter should be an + * NVC372_CTRL_IMP_LUT_USAGE_xxx value. + * + * head.cursorSize32p + * This parameter specifies the width of the cursor, in units of 32 pixels. + * So, for example, "8" would mean 8 * 32 = 256, for a 256x256 cursor. Zero + * means the cursor is disabled. + * + * head.bEnableDsc + * bEnableDsc indicates whether or not DSC is enabled + * + * head.bYUV420Format + * This parameter indicates output format is YUV420. + * Refer to NVD_YUV420_Output_Functional_Description.docx for more details. + * + * head.bIs2Head1Or + * This parameter specifies if the head operates in 2Head1Or mode. + * Refer to NVD_2_Heads_Driving_1_OR_Functional_Description.docx for more details. + * + * head.bGetOSLDOutput + * This parameter specifies if the client requires output for the OSLD + * (One Shot Mode with Stall Lock Disabled) mode along with legacy outputs. + * + * head.bDisableMidFrameAndDWCFWatermark + * WAR for bug 200508242. + * In linux it is possible that there will be no fullscreen window visible + * for a head. For these cases we would not hit dwcf or midframe watermarks + * leading to fbflcn timing out waiting on ok_to_switch and forcing mclk + * switch. This could lead to underflows. So if that scenario is caught (by + * Display Driver) bDisableMidFrameAndDWCFWatermark will be set to true and + * IMP will exclude dwcf and midframe contribution from the "is mclk switch + * guaranteed" calculation for the bandwidth clients of that head. + * + * window.windowIndex + * This is the hardware index number for the window. Only active windows + * should be included in the input structure. + * + * window.owningHead + * This is the hardware index of the head that will receive the window's + * output. + * + * window.formatUsageBound + * This parameter is a bitmask of all possible non-rotated mode data + * formats (NVC372_CTRL_FORMAT_xxx values). + * + * window.rotatedFormatUsageBound + * This parameter is a bitmask of all possible rotated mode data formats + * (NVC372_CTRL_FORMAT_xxx values). + * + * window.maxPixelsFetchedPerLine + * This parameter defines the maximum number of pixels that may need to be + * fetched in a single line for this window. Often, this can be set to the + * viewportSizeIn.Width. But if the window is known to be clipped, such + * that an entire line will never be fetched, then this parameter can be + * set to the clipped size (to improve the chances of the mode being + * possible, or possible at a lower v-pstate). + * + * In some cases, the value of this parameter must be increased by a few + * pixels in order to account for scaling overfetch, input chroma overfetch + * (420/422->444), and/or chroma output low pass filter overfetch + * (444->422/420). This value is chip dependent; refer to the + * MaxPixelsFetchedPerLine parameter in nvdClass_01.mfs for the exact + * value. In no case does the maxPixelsFetchedPerLine value need to exceed + * the surface width. + * + * window.maxDownscaleFactorH + * window.maxDownscaleFactorV + * maxDownscaleFactorH and maxDownscaleFactorV represent the maximum amount + * by which the the window image can be reduced in size, horizontally and + * vertically, respectively, multiplied by + * NVC372_CTRL_SCALING_FACTOR_MULTIPLIER. For example, + * if the scaler input width is 1024, and the scaler output width is 2048, + * the downscale factor would be 1024 / 2048 = 0.5, and multiplying by + * NVC372_CTRL_SCALING_FACTOR_MULTIPLIER if 0x400 would give 512. + * + * window.inputScalerVerticalTaps + * scalerVerticalTaps indicates the maximum number of vertical taps + * allowed in the input scaler. + * + * Note that there are no #defines for tap values; the parameter is simply + * the number of taps (e.g., "2" for 2 taps). + * + * window.bUpscalingAllowedV + * bUpscalingAllowed indicates whether or not the composited image can be + * increased in size, vertically. + * + * window.bOverfetchEnabled + * bOverfetchEnabled indicates whether or not the vertical overfetch is + * enabled in precomp scaler. + * + * window.lut + * This parameter specifies whether or not the input LUT is enabled, and + * the size of the LUT. The parameter should be an + * NVC372_CTRL_IMP_LUT_USAGE_xxx value. + * + * window.tmoLut + * This parameter specifies whether or not the tmo LUT is enabled, and + * the size of the LUT. This lut is used for HDR. The parameter should be + * an NVC372_CTRL_IMP_LUT_USAGE_xxx value. + * + * numHeads + * This is the number of heads in the "head" array of the + * NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS struct. Only active heads should be + * included in the struct. + * + * numWindows + * This is the number of windows in the "window" array of the + * NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS struct. Only active windows should + * be included in the struct. + * + * options + * This parameter specifies a bitmask for options. + * + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN + * tells IMP to calculate worstCaseMargin and worstCaseDomain. + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE + * tells IMP to calculate and report the minimum v-pstate at which the + * mode is possible. + * + * bUseCachedPerfState + * Indicates that RM should use cached values for the fastest + * available perf level (v-pstate for PStates 3.0 or pstate for + * PStates 2.0) and dispclk. This feature allows the query call to + * execute faster, and is intended to be used, for example, during + * mode enumeration, when many IMP query calls are made in close + * succession, and perf conditions are not expected to change between + * query calls. When IMP has not been queried recently, it is + * recommended to NOT use cached values, in case perf conditions have + * changed and the cached values no longer reflect the current + * conditions. + * + * testMclkFreqKHz + * This is the mclk frequency specified by the client, in KHz. RM will + * use this value to compare with the minimum dramclk required by the + * given mode. The parameter will have value 0 if the client doesn't want + * IMP query to consider this. This input is valid only on Tegra and only + * for verification purposes on internal builds. + * For this input to work, client must set + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE in the + * "options" field. + * + * Outputs: + * bIsPossible + * This output tells if the specified mode can be supported. To know if + * the mode is possible with OSLD, the bIsOSLDPossible result must + * be checked. + * + * bIsOSLDPossible + * This output is returned for each head and suggests to the clients + * if the mode will be possible or not on that head when OSLD is enabled. + * The output is only valid if bGetOSLDOutput is set in the head input. + * Note that with OSLD output, RM will also return the legacy output + * values. + * + * minImpVPState + * minImpVPState returns the minimum v-pstate at which the mode is possible + * (assuming bIsPossible is TRUE). This output is valid only on dGPU, and + * only if NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in + * the "options" field. + * + * If the minimum v-pstate is required for a multi-head config, then + * masterLockMode, masterLockPin, slaveLockMode, and slaveLockPin must all + * be initialized. + * minPState + * minPState returns the pstate value corresponding to minImpVPState. It + * is returned as the numeric value of the pstate (P0 -> 0, P1 -> 1, etc.). + * This output is valid only on dGPU, and only if + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set + * in the "options" field. + * + * Note that the pstate returned by minPstateForGlitchless is not + * necessarily sufficient to meet IMP requirements. The pstate corresponds + * to the vpstate returned by minImpVPState, and this vpstate represents + * clocks that are sufficient for IMP requirements, but the pstate + * typically covers a range of frequencies (depending on the clock), and it + * is possible that only part of the range is sufficient for IMP. + * + * minRequiredBandwidthKBPS + * minRequiredBandwidthKBPS returns the minimum bandwidth that must be + * allocated to display in order to make the mode possible (assuming + * bIsPossible is TRUE). This output is valid only on Tegra, and only if + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in the + * "options" field. + * + * floorBandwidthKBPS + * floorBandwidthKBPS returns the minimum mclk frequency that can support + * the mode, and allow glitchless mclk switch, multiplied by the width of + * the data pipe. (This is an approximation of the bandwidth that can be + * provided by the min required mclk frequency, ignoring overhead.) If the + * mode is possible, but glitchless mclk switch is not, floorBandwidthKBPS + * will be calculated based on the maximum possible mclk frequency. This + * output is valid only on Tegra, and only if + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in the + * "options" field. + * + * minRequiredHubclkKHz + * minRequiredHubclkKHz returns the minimum hubclk frequency that can + * support the mode. This output is valid only on Tegra, and only if + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in the + * "options" field. + * + * vblankIncreaseInLinesForOSLDMode + * vblankIncreaseInLinesForOSLDMode returns the amount, in lines, by + * which vblank needs to be extended to achieve optimized MSCG when OSLD + * Mode is enabled (assuming bIsPossible is TRUE). Features like Panel + * Replay and Panel Self Refresh enable OSLD mode. This value is 0 if + * the vblank is large enough to accommodate spool up and MSCG latencies. + * This output is valid only if + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in the + * "options" field and bGetOSLDOutput was specified in the head input. + * + * wakeUpRgLineForOSLDMode + * wakeUpRgLineForOSLDMode returns the rg line in the vblank region at which + * the clients will be required to send a timestamped update to achieve + * optimized MSCG when OSLD Mode is enabled (assuming bIsPossible is + * is TRUE). Features like Panel Replay and Panel Self Refresh enable + * OSLD mode. This output is valid only if + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in the + * "options" field and bGetOSLDOutput was specified in the head input. + * + * worstCaseMargin + * worstCaseMargin returns the ratio of available bandwidth to required + * bandwidth, multiplied by NV5070_CTRL_IMP_MARGIN_MULTIPLIER. Available + * bandwidth is calculated in the worst case bandwidth domain, i.e., the + * domain with the least available margin. Bandwidth domains include the + * IMP-relevant clock domains, and possibly other virtual bandwidth + * domains such as AWP. + * + * Note that IMP checks additional parameters besides the bandwidth margins + * but only the bandwidth margin is reported here, so it is possible for a + * mode to have a more restrictive domain that is not reflected in the + * reported margin result. + * + * This result is not guaranteed to be valid if the mode is not possible. + * + * Note also that the result is generally calculated for the highest + * v-pstate possible (usually P0). But if the _NEED_MIN_VPSTATE is + * specified, the result will be calculated for the min possible v-pstate + * (or the highest possible v-pstate, if the mode is not possible). + * + * The result is valid only if + * NV5070_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN is set in "options". + * + * dispClkKHz + * This is the dispclk frequency selected by IMP for this mode. For dGPU, + * it will be one of the fixed frequencies from the list of frequencies + * supported by the vbios. + * + * worstCaseDomain + * Returns a short text string naming the domain for the margin returned in + * "worstCaseMargin". See "worstCaseMargin" for more information. + * + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + * NVOS_STATUS_ERROR_GENERIC + */ +#define NVC372_CTRL_IMP_LUT_USAGE_NONE 0 +#define NVC372_CTRL_IMP_LUT_USAGE_257 1 +#define NVC372_CTRL_IMP_LUT_USAGE_1025 2 + +typedef struct NVC372_CTRL_IMP_HEAD { + NvU8 headIndex; + + NvU32 maxPixelClkKHz; + + struct { + NvU32 width; + NvU32 height; + } rasterSize; + + struct { + NvU32 X; + NvU32 Y; + } rasterBlankStart; + + struct { + NvU32 X; + NvU32 Y; + } rasterBlankEnd; + + struct { + NvU32 yStart; + NvU32 yEnd; + } rasterVertBlank2; + + struct { + NV_DISP_LOCK_MODE masterLockMode; + NV_DISP_LOCK_PIN masterLockPin; + NV_DISP_LOCK_MODE slaveLockMode; + NV_DISP_LOCK_PIN slaveLockPin; + } control; + + NvU32 maxDownscaleFactorH; + NvU32 maxDownscaleFactorV; + NvU8 outputScalerVerticalTaps; + NvBool bUpscalingAllowedV; + NvBool bOverfetchEnabled; + + struct { + NvU16 leadingRasterLines; + NvU16 trailingRasterLines; + } minFrameIdle; + + NvU8 lut; + NvU8 cursorSize32p; + + NvBool bEnableDsc; + + NvBool bYUV420Format; + + NvBool bIs2Head1Or; + + NvBool bGetOSLDOutput; + + NvBool bDisableMidFrameAndDWCFWatermark; +} NVC372_CTRL_IMP_HEAD; +typedef struct NVC372_CTRL_IMP_HEAD *PNVC372_CTRL_IMP_HEAD; + +typedef struct NVC372_CTRL_IMP_WINDOW { + NvU32 windowIndex; + NvU32 owningHead; + NvU32 formatUsageBound; + NvU32 rotatedFormatUsageBound; + NvU32 maxPixelsFetchedPerLine; + NvU32 maxDownscaleFactorH; + NvU32 maxDownscaleFactorV; + NvU8 inputScalerVerticalTaps; + NvBool bUpscalingAllowedV; + NvBool bOverfetchEnabled; + NvU8 lut; + NvU8 tmoLut; +} NVC372_CTRL_IMP_WINDOW; +typedef struct NVC372_CTRL_IMP_WINDOW *PNVC372_CTRL_IMP_WINDOW; + +#define NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN (0x00000001) +#define NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE (0x00000002) + +#define NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS { + NVC372_CTRL_CMD_BASE_PARAMS base; + + NvU8 numHeads; + NvU8 numWindows; + + NVC372_CTRL_IMP_HEAD head[NVC372_CTRL_MAX_POSSIBLE_HEADS]; + + // C form: NVC372_CTRL_IMP_WINDOW window[NVC372_CTRL_MAX_POSSIBLE_WINDOWS]; + NVC372_CTRL_IMP_WINDOW window[NVC372_CTRL_MAX_POSSIBLE_WINDOWS]; + + NvU32 options; + + NvU32 testMclkFreqKHz; + + NvBool bIsPossible; + + NvBool bIsOSLDPossible[NVC372_CTRL_MAX_POSSIBLE_HEADS]; + + NvU32 minImpVPState; + + NvU32 minPState; + + NvU32 minRequiredBandwidthKBPS; + + NvU32 floorBandwidthKBPS; + + NvU32 minRequiredHubclkKHz; + + NvU32 vblankIncreaseInLinesForOSLDMode[NVC372_CTRL_MAX_POSSIBLE_HEADS]; + + NvU32 wakeUpRgLineForOSLDMode[NVC372_CTRL_MAX_POSSIBLE_HEADS]; + + NvU32 worstCaseMargin; + + NvU32 dispClkKHz; + + char worstCaseDomain[8]; + + NvBool bUseCachedPerfState; +} NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS; +typedef struct NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS *PNVC372_CTRL_IS_MODE_POSSIBLE_PARAMS; + +/* valid format values */ +#define NVC372_CTRL_FORMAT_RGB_PACKED_1_BPP (0x00000001) +#define NVC372_CTRL_FORMAT_RGB_PACKED_2_BPP (0x00000002) +#define NVC372_CTRL_FORMAT_RGB_PACKED_4_BPP (0x00000004) +#define NVC372_CTRL_FORMAT_RGB_PACKED_8_BPP (0x00000008) +#define NVC372_CTRL_FORMAT_YUV_PACKED_422 (0x00000010) +#define NVC372_CTRL_FORMAT_YUV_PLANAR_420 (0x00000020) +#define NVC372_CTRL_FORMAT_YUV_PLANAR_444 (0x00000040) +#define NVC372_CTRL_FORMAT_YUV_SEMI_PLANAR_420 (0x00000080) +#define NVC372_CTRL_FORMAT_YUV_SEMI_PLANAR_422 (0x00000100) +#define NVC372_CTRL_FORMAT_YUV_SEMI_PLANAR_422R (0x00000200) +#define NVC372_CTRL_FORMAT_YUV_SEMI_PLANAR_444 (0x00000400) +#define NVC372_CTRL_FORMAT_EXT_YUV_PLANAR_420 (0x00000800) +#define NVC372_CTRL_FORMAT_EXT_YUV_PLANAR_444 (0x00001000) +#define NVC372_CTRL_FORMAT_EXT_YUV_SEMI_PLANAR_420 (0x00002000) +#define NVC372_CTRL_FORMAT_EXT_YUV_SEMI_PLANAR_422 (0x00004000) +#define NVC372_CTRL_FORMAT_EXT_YUV_SEMI_PLANAR_422R (0x00008000) +#define NVC372_CTRL_FORMAT_EXT_YUV_SEMI_PLANAR_444 (0x00010000) + +/* valid impResult values */ +#define NVC372_CTRL_IMP_MODE_POSSIBLE 0 +#define NVC372_CTRL_IMP_NOT_ENOUGH_MEMPOOL 1 +#define NVC372_CTRL_IMP_REQ_LIMIT_TOO_HIGH 2 +#define NVC372_CTRL_IMP_VBLANK_TOO_SMALL 3 +#define NVC372_CTRL_IMP_HUBCLK_TOO_LOW 4 +#define NVC372_CTRL_IMP_INSUFFICIENT_BANDWIDTH 5 +#define NVC372_CTRL_IMP_DISPCLK_TOO_LOW 6 +#define NVC372_CTRL_IMP_ELV_START_TOO_HIGH 7 +#define NVC372_CTRL_IMP_OSLD_ELV_START_TOO_HIGH 8 +#define NVC372_CTRL_IMP_INSUFFICIENT_THREAD_GROUPS 9 +#define NVC372_CTRL_IMP_INVALID_PARAMETER 10 +#define NVC372_CTRL_IMP_UNRECOGNIZED_FORMAT 11 +#define NVC372_CTRL_IMP_UNSPECIFIED 12 + +/* + * The calculated margin is multiplied by a constant, so that it can be + * represented as an integer with reasonable precision. "0x400" was chosen + * because it is a power of two, which might allow some compilers/CPUs to + * simplify the calculation by doing a shift instead of a multiply/divide. + * (And 0x400 is 1024, which is close to 1000, so that may simplify visual + * interpretation of the raw margin value.) + */ +#define NVC372_CTRL_IMP_MARGIN_MULTIPLIER (0x00000400) + +/* scaling factor */ +#define NVC372_CTRL_SCALING_FACTOR_MULTIPLIER (0x00000400) + +#define NVC372_CTRL_CMD_NUM_DISPLAY_ID_DWORDS_PER_HEAD 2 +#define NVC372_CTRL_CMD_MAX_SORS 4 + +#define NVC372_CTRL_CMD_IS_MODE_POSSIBLE_OR_SETTINGS (0xc3720102) /* finn: Evaluated from "(FINN_NVC372_DISPLAY_SW_CHNCTL_INTERFACE_ID << 8) | NVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS_MESSAGE_ID" */ + +/* + * NVC372_CTRL_CMD_IS_MODE_POSSIBLE_OR_SETTINGS + * + * This command tells us if output resource pixel clocks requested by client + * is possible or not. Note that this will not be used for displayport sor as + * it will be handled by displayport library. + * + * Inputs: + * numHeads + * This is the number of heads in the "head" array of the + * NVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS struct. Only active heads + * should be included in the struct. + * + * head.headIndex + * This is the hardware index number for the head. Only an active head + * should be included in the input structure. + * + * head.maxPixelClkKHz + * This parameter specifies the pixel scanout rate (in KHz). + * + * head.displayId + * Array of displayId's associated with the head. This is limited by + * NVC372_CTRL_CMD_NUM_DISPLAY_ID_DWORDS_PER_HEAD. + * + * sor.ownerMask + * Consists of a mask of all heads that drive this sor. + * + * sor.protocol + * Defines the protocol of the sor in question. + * + * sor.pixelReplicateMode + * Defines which pixel replication mode is requested. This can be off + * or X2 or X4 mode. + * + * Outputs: + * bIsPossible + * This tells us that the requested pixel clock can be supported. + */ + + +#define NVC372_CTRL_IS_MODE_POSSIBLE_DISPLAY_ID_SKIP_IMP_OUTPUT_CHECK (0xAAAAAAAA) + +typedef struct NVC372_CTRL_IMP_OR_SETTINGS_HEAD { + NvU8 headIndex; + NvU32 maxPixelClkKhz; + + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP outputResourcePixelDepthBPP; + + NvU32 displayId[NVC372_CTRL_CMD_NUM_DISPLAY_ID_DWORDS_PER_HEAD]; +} NVC372_CTRL_IMP_OR_SETTINGS_HEAD; +typedef struct NVC372_CTRL_IMP_OR_SETTINGS_HEAD *PNVC372_CTRL_IMP_OR_SETTINGS_HEAD; + +#define NVC372_CTRL_CMD_SOR_OWNER_MASK_NONE (0x00000000) +#define NVC372_CTRL_CMD_SOR_OWNER_MASK_HEAD(i) (1 << i) + +#define NVC372_CTRL_CMD_SOR_PROTOCOL_SINGLE_TMDS_A (0x00000000) +#define NVC372_CTRL_CMD_SOR_PROTOCOL_SINGLE_TMDS_B (0x00000001) +#define NVC372_CTRL_CMD_SOR_PROTOCOL_DUAL_TMDS (0x00000002) +#define NVC372_CTRL_CMD_SOR_PROTOCOL_SUPPORTED (0xFFFFFFFF) + +#define NVC372_CTRL_IS_MODE_POSSIBLE_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NVC372_CTRL_IS_MODE_POSSIBLE_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NVC372_CTRL_IS_MODE_POSSIBLE_PIXEL_REPLICATE_MODE_X4 (0x00000002) + +typedef struct NVC372_CTRL_IMP_OR_SETTINGS_SOR { + NvU32 ownerMask; + NvU32 protocol; + NvU32 pixelReplicateMode; +} NVC372_CTRL_IMP_OR_SETTINGS_SOR; +typedef struct NVC372_CTRL_IMP_OR_SETTINGS_SOR *PNVC372_CTRL_IMP_OR_SETTINGS_SOR; + +#define NVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS { + NVC372_CTRL_CMD_BASE_PARAMS base; + + NvU32 numHeads; + + NVC372_CTRL_IMP_OR_SETTINGS_HEAD head[NVC372_CTRL_MAX_POSSIBLE_HEADS]; + + NVC372_CTRL_IMP_OR_SETTINGS_SOR sor[NVC372_CTRL_CMD_MAX_SORS]; + + NvBool bIsPossible; +} NVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS; +typedef struct NVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS *PNVC372_CTRL_IS_MODE_POSSIBLE_OR_SETTINGS_PARAMS; + +#define NVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE (0xc3720103) /* finn: Evaluated from "(FINN_NVC372_DISPLAY_SW_CHNCTL_INTERFACE_ID << 8) | NVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE_PARAMS_MESSAGE_ID" */ + +/* + * NVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE + * + * This control call is used by clients to inform RM about video adaptive refresh rate enable/disable. + * Based on the state, RM will enable/disable supported low power features. + * + * Inputs: + * displayID + * displayId of panel on which video adaptive refresh rate is enabled/disabled. + * + * bEnable + * NV_TRUE to enable video adaptive refresh rate mode. + * NV_FALSE to disable video adaptive refresh rate mode. + * + * Outputs: + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE_PARAMS { + NvU32 displayID; + NvBool bEnable; +} NVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE_PARAMS; +typedef struct NVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE_PARAMS *PNVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE_PARAMS; + + +#define NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN (0xc3720104) /* finn: Evaluated from "(FINN_NVC372_DISPLAY_SW_CHNCTL_INTERFACE_ID << 8) | NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS_MESSAGE_ID" */ + +/* + * NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN + * + * This control call is used by clients to query the active viewport for the + * provided window precalculated at the beginning of each frame. + * + * Inputs: + * windowIndex + * Index of the window to be queried. Must be connected to an active head. + * + * Outputs: + * activeViewportPointIn + * X and Y coordinates of the active viewport on the provided window for + * the most recent frame. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT if the window index is invalid + * NV_ERR_INVALID_STATE if the window index isn't connected to a head + * NV_ERR_NOT_SUPPORTED + */ +#define NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS { + NVC372_CTRL_CMD_BASE_PARAMS base; + + NvU32 windowIndex; + + struct { + NvU32 x; + NvU32 y; + } activeViewportPointIn; +} NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS; +typedef struct NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS *PNVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS; + +/* _ctrlc372chnc_h_ */ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc46f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc46f.h new file mode 100644 index 0000000..c53e217 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc46f.h @@ -0,0 +1,162 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc46f.finn +// + + + + +/* TURING_CHANNEL_GPFIFO_A control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl906f.h" /* C36F is partially derived from 906F */ +#include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */ +#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F + +#define NVC46F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xC36F, NVC46F_CTRL_##cat, idx) + +/* TURING_CHANNEL_GPFIFO_A command categories (6bits) */ +#define NVC46F_CTRL_RESERVED (0x00) +#define NVC46F_CTRL_GPFIFO (0x01) +#define NVC46F_CTRL_EVENT (0x02) + +/* + * NVC46F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned is: NV_OK +*/ +#define NVC46F_CTRL_CMD_NULL (NVC36F_CTRL_CMD_NULL) + + + + + + +/* + * NVC46F_CTRL_GET_CLASS_ENGINEID + * + * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. + * + */ +#define NVC46F_CTRL_GET_CLASS_ENGINEID (NVC36F_CTRL_GET_CLASS_ENGINEID) + +typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC46F_CTRL_GET_CLASS_ENGINEID_PARAMS; + +/* + * NVC46F_CTRL_RESET_CHANNEL + * + * Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information. + * + */ +#define NVC46F_CTRL_CMD_RESET_CHANNEL (NVC36F_CTRL_CMD_RESET_CHANNEL) + +typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC46F_CTRL_CMD_RESET_CHANNEL_PARAMS; + +/* + * NVC46F_CTRL_CMD_GPFIFO_SCHEDULE + * + * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. + * + */ +#define NVC46F_CTRL_CMD_GPFIFO_SCHEDULE (NVC36F_CTRL_CMD_GPFIFO_SCHEDULE) + +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC46F_CTRL_GPFIFO_SCHEDULE_PARAMS; + +/* + * NVC46F_CTRL_CMD_BIND + * + * Please see description of NVA06F_CTRL_CMD_BIND for more information. + */ +#define NVC46F_CTRL_CMD_BIND (NVC36F_CTRL_CMD_BIND) + +typedef NVA06F_CTRL_BIND_PARAMS NVC46F_CTRL_BIND_PARAMS; + +/* + * NVC46F_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. +*/ +#define NVC46F_CTRL_CMD_EVENT_SET_NOTIFICATION (NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION) + +typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC46F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NVC46F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE +#define NVC46F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE +#define NVC46F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT + +/* + * NVC46F_CTRL_CMD_EVENT_SET_TRIGGER + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information. + */ +#define NVC46F_CTRL_CMD_EVENT_SET_TRIGGER (NVC36F_CTRL_CMD_EVENT_SET_TRIGGER) + + + + + +/* + * NVC46F_CTRL_CMD_GET_MMU_FAULT_INFO + * + * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. + * + */ +#define NVC46F_CTRL_CMD_GET_MMU_FAULT_INFO (NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO) + +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC46F_CTRL_GET_MMU_FAULT_INFO_PARAMS; + +/* + * NVC46F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN + * + * This command returns an opaque work submit token to the caller which + * can be used to write to doorbell register to finish submitting work. + * + * workSubmitToken The 32-bit work submit token + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + * + */ + +#define NVC46F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN (NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN) + +typedef struct NVC46F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS { + NvU32 workSubmitToken; +} NVC46F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS; + +/* _ctrlc46f.h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc56f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc56f.h new file mode 100644 index 0000000..a781b1a --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc56f.h @@ -0,0 +1,166 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc56f.finn +// + + + + +/* AMPERE_CHANNEL_GPFIFO_A control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl906f.h" /* C36F is partially derived from 906F */ +#include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */ +#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F + + + +#define NVC56F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xC36F, NVC56F_CTRL_##cat, idx) + +/* AMPERE_CHANNEL_GPFIFO_A command categories (6bits) */ +#define NVC56F_CTRL_RESERVED (0x00) +#define NVC56F_CTRL_GPFIFO (0x01) +#define NVC56F_CTRL_EVENT (0x02) + +/* + * NVC56F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned is: NV_OK +*/ +#define NVC56F_CTRL_CMD_NULL (NVC36F_CTRL_CMD_NULL) + + + + + + +/* + * NVC56F_CTRL_GET_CLASS_ENGINEID + * + * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. + * + */ +#define NVC56F_CTRL_GET_CLASS_ENGINEID (NVC36F_CTRL_GET_CLASS_ENGINEID) + +typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC56F_CTRL_GET_CLASS_ENGINEID_PARAMS; + +/* + * NVC56F_CTRL_RESET_CHANNEL + * + * Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information. + * + */ +#define NVC56F_CTRL_CMD_RESET_CHANNEL (NVC36F_CTRL_CMD_RESET_CHANNEL) + +typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC56F_CTRL_CMD_RESET_CHANNEL_PARAMS; + +/* + * NVC56F_CTRL_CMD_GPFIFO_SCHEDULE + * + * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. + * + */ +#define NVC56F_CTRL_CMD_GPFIFO_SCHEDULE (NVC36F_CTRL_CMD_GPFIFO_SCHEDULE) + +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC56F_CTRL_GPFIFO_SCHEDULE_PARAMS; + +/* + * NVC56F_CTRL_CMD_BIND + * + * Please see description of NVA06F_CTRL_CMD_BIND for more information. + */ +#define NVC56F_CTRL_CMD_BIND (NVC36F_CTRL_CMD_BIND) + +typedef NVA06F_CTRL_BIND_PARAMS NVC56F_CTRL_BIND_PARAMS; + +/* + * NVC56F_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. +*/ +#define NVC56F_CTRL_CMD_EVENT_SET_NOTIFICATION (NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION) + +typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC56F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NVC56F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE +#define NVC56F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE +#define NVC56F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT + +/* + * NVC56F_CTRL_CMD_EVENT_SET_TRIGGER + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information. + */ +#define NVC56F_CTRL_CMD_EVENT_SET_TRIGGER (NVC36F_CTRL_CMD_EVENT_SET_TRIGGER) + + + + + +/* + * NVC56F_CTRL_CMD_GET_MMU_FAULT_INFO + * + * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. + * + */ +#define NVC56F_CTRL_CMD_GET_MMU_FAULT_INFO (NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO) + +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC56F_CTRL_GET_MMU_FAULT_INFO_PARAMS; + +/* + * NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN + * + * This command returns an opaque work submit token to the caller which + * can be used to write to doorbell register to finish submitting work. + * + * workSubmitToken The 32-bit work submit token + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + * + */ + +#define NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN (NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN) + +typedef struct NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS { + NvU32 workSubmitToken; +} NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS; + + + +/* _ctrlc56f.h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc637.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc637.h new file mode 100644 index 0000000..155d639 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc637.h @@ -0,0 +1,392 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc637.finn +// + +#include "ctrl/ctrlxxxx.h" +/* AMPERE_SMC_PARTITION_REF commands and parameters */ + +#define NVC637_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xC637, NVC637_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NVC637_CTRL_RESERVED (0x00) +#define NVC637_CTRL_EXEC_PARTITIONS (0x01) + + +/*! + * NVC637_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVC637_CTRL_CMD_NULL (0xc6370000) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/*! + * NVC637_CTRL_EXEC_PARTITIONS_INFO + * + * This structure specifies resources in an execution partition + * + * gpcCount[IN/OUT] + * - Total Number of GPCs in this partition (including GFX Supported GPCs) + * + * gfxGpcCount[IN/OUT] + * - Number of GFX GPCs in this partition. This should be a subset of gpcs inlcuded in gpcCount + * + * VeidCount[OUT] + * - Number of VEIDs available in this partition. + * + * ceCount[IN/OUT] + * - Copy Engines in this partition + * + * nvEncCount[IN/OUT] + * - Encoder Engines in this partition + * + * nvDecCount[IN/OUT] + * - Decoder Engines in this partition + * + * nvJpgCount[IN/OUT] + * - Jpg Engines in this partition + * + * nvOfaCount[IN/OUT] + * - Ofa engines in this partition + * + * sharedEngFlags[IN/OUT] + * - Flags determining whether above engines are shared with other execution partitions + * + * veidStartOffset[OUT] + * - VEID start offset within GPU partition + * + * smCount[IN/OUT] + * - Number of active SMs in this partition + * + * spanStart[IN/OUT] + * - First slot in the span for an execution partition placement + * + * computeSize[IN/OUT] + * - Flag corresponding to the compute profile used + * + */ +typedef struct NVC637_CTRL_EXEC_PARTITIONS_INFO { + NvU32 gpcCount; + NvU32 gfxGpcCount; + NvU32 veidCount; + NvU32 ceCount; + NvU32 nvEncCount; + NvU32 nvDecCount; + NvU32 nvJpgCount; + NvU32 ofaCount; + NvU32 sharedEngFlag; + NvU32 veidStartOffset; + NvU32 smCount; + NvU32 spanStart; + NvU32 computeSize; +} NVC637_CTRL_EXEC_PARTITIONS_INFO; + +#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG 31:0 +#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NONE 0x0 +#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_CE NVBIT(0) +#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVDEC NVBIT(1) +#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVENC NVBIT(2) +#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_OFA NVBIT(3) +#define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVJPG NVBIT(4) + +#define NVC637_CTRL_MAX_EXEC_PARTITIONS 8 +#define NVC637_CTRL_EXEC_PARTITIONS_ID_INVALID 0xFFFFFFFF + +/*! + * NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS + * + * This command will create requested execution partitions under the subscribed + * memory partition. The memory partition is expected to be configured before + * execution partition creation. + * + * bQuery[IN] + * - If NV_TRUE, execution partitions will not be created, but return + * status of NV_OK will indicate that the request is valid and can + * currently be fulfilled + * flag [IN] + * REQUEST_WITH_PART_ID + * - If set, RM will try to assign execution partition id requested by clients. + * This flag is only supported on vGPU enabled RM build and will be removed + * when vgpu plugin implements virtualized execution partition ID support. + * (bug 2938187) + * + * REQUEST_AT_SPAN + * - If set, RM will try to assign execution partition resources at the specified span. + * This flag currently is only useful for chips in which CTS IDs are mandatory in RM, + * as it allows the requester to position compute instances without using RM best fit + * allocation. + * + * execPartCount[IN] + * - Number of execution partitions requested + * + * execPartInfo[IN] + * - Requested execution partition resources for each requested partition + * + * execPartId[OUT] + * - ID of each requested execution partition + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_WITH_PART_ID 0:0 +#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_WITH_PART_ID_FALSE (0x00000000) +#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_WITH_PART_ID_TRUE (0x00000001) +#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_AT_SPAN 1:1 +#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_AT_SPAN_FALSE (0x00000000) +#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_AT_SPAN_TRUE (0x00000001) + +#define NVC637_CTRL_CMD_EXEC_PARTITIONS_CREATE (0xc6370101) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_MESSAGE_ID" */ + +/*! + * NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS + * + * This command will delete requested execution partitions. + * + * execPartCount[IN] + * - Number of execution partitions to delete. + * + * execPartId[IN] + * - Execution partition IDs to delete + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS { + NvBool bQuery; + NvU32 flags; + NvU32 execPartCount; + // C form: NVC637_CTRL_EXEC_PARTITIONS_INFO execPartInfo[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + NVC637_CTRL_EXEC_PARTITIONS_INFO execPartInfo[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + // C form: NvU32 execPartId[NVC637_CTRL_MAX_EXECUTION_PARTITIONS]; + NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS]; +} NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS; +#define NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS { + NvU32 execPartCount; + NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS]; +} NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS; + +#define NVC637_CTRL_CMD_EXEC_PARTITIONS_DELETE (0xc6370102) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_MESSAGE_ID" */ + +/*! + * NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS + * + * This command will return information about execution partitions which + * currently exist within the subscribed memory partition. + * + * execPartCount[OUT] + * - Number of existing execution partitions + * + * execPartId[OUT] + * - ID of existing execution partitions + * + * execPartInfo[OUT] + * - Resources within each existing execution partition + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS { + NvU32 execPartCount; + // C form: NvU32 execPartId[NVC637_CTRL_MAX_EXECUTION_PARTITIONS]; + NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + // C form: NVC637_CTRL_EXEC_PARTITIONS_INFO execPartInfo[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + NVC637_CTRL_EXEC_PARTITIONS_INFO execPartInfo[NVC637_CTRL_MAX_EXEC_PARTITIONS]; +} NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS; + +#define NVC637_CTRL_CMD_EXEC_PARTITIONS_GET (0xc6370103) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_MESSAGE_ID" */ + +/*! + * NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS + * + * This command will return IDs of all active execution partitions in a memory + * partition + * + * execPartCount[OUT] + * - Number of existing execution partitions + * + * execPartId[OUT] + * - ID of existing execution partitions + * + * execPartUuid[OUT] + * - ASCII UUID string of existing execution partitions + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +/* 'M' 'I' 'G' '-'(x5), '\0x0', extra = 9 */ +#define NVC637_UUID_LEN 16 +#define NVC637_UUID_STR_LEN (0x29) /* finn: Evaluated from "((NVC637_UUID_LEN << 1) + 9)" */ + +typedef struct NVC637_EXEC_PARTITION_UUID { + // C form: char str[NVC638_UUID_STR_LEN]; + char str[NVC637_UUID_STR_LEN]; +} NVC637_EXEC_PARTITION_UUID; + +#define NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS { + NvU32 execPartCount; + + // C form: NvU32 execPartId[NVC637_CTRL_MAX_EXECUTION_PARTITIONS]; + NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + + // C form: NVC637_EXEC_PARTITION_UUID execPartUuid[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + NVC637_EXEC_PARTITION_UUID execPartUuid[NVC637_CTRL_MAX_EXEC_PARTITIONS]; +} NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS; + +#define NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS (0xc6370104) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS_MESSAGE_ID" */ + +/* + * NVC637_CTRL_CMD_EXEC_PARTITIONS_EXPORT + * + * Export the resource and placement information about an exec partition such + * that a similar partition can be recreated from scratch in the same position. + */ +#define NVC637_CTRL_CMD_EXEC_PARTITIONS_EXPORT (0xc6370105) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | 0x5" */ + +/* + * NVC637_CTRL_CMD_EXEC_PARTITIONS_IMPORT + * + * Create an exec partition resembling the exported partition info. The imported + * partition should behave identically with respect to fragmentation. + */ +#define NVC637_CTRL_CMD_EXEC_PARTITIONS_IMPORT (0xc6370106) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | 0x6" */ + +#define NVC637_CTRL_EXEC_PARTITIONS_EXPORT_MAX_ENGINES_MASK_SIZE 4 +typedef struct NVC637_CTRL_EXEC_PARTITIONS_EXPORTED_INFO { + NV_DECLARE_ALIGNED(NvU64 enginesMask[NVC637_CTRL_EXEC_PARTITIONS_EXPORT_MAX_ENGINES_MASK_SIZE], 8); + NvU8 uuid[NVC637_UUID_LEN]; + NvU32 sharedEngFlags; + NvU32 gpcMask; + NvU32 veidOffset; + NvU32 veidCount; + NvU32 smCount; + NvU32 spanStart; + NvU32 computeSize; +} NVC637_CTRL_EXEC_PARTITIONS_EXPORTED_INFO; + +typedef struct NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS { + NvU32 id; + NV_DECLARE_ALIGNED(NVC637_CTRL_EXEC_PARTITIONS_EXPORTED_INFO info, 8); +} NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS; + +/* + * NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN + * + * This struct represents the span of a compute instance, which represents the + * resource slots a given partition occupies (or may occupy) within a fixed range which + * is defined per-chip. A partition containing more resources will cover more + * resource slots and therefore cover a larger span. + * + * lo + * - The starting unit of this span, inclusive + * + * hi + * - The ending unit of this span, inclusive + * + */ +typedef struct NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN { + NV_DECLARE_ALIGNED(NvU64 lo, 8); + NV_DECLARE_ALIGNED(NvU64 hi, 8); +} NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN; + +/* + * NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY + * + * This command returns the count of compute instances which can be created + * of the given commpute profile size (represented by the computeSize field + * within a profile) which can be requested via NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILES + * Note that this API does not "reserve" any partitions, and there is no + * guarantee that the reported count of available partitions of a given size + * will remain consistent following creation of partitions of different size + * through NV2080_CTRL_GPU_SET_PARTITIONS. + * Note that this API is unsupported if SMC is feature-disabled. + * Note that the caller of this CTRL must be subscribed to a valid GPU instance + * + * computeSize[IN] + * - Partition flag indicating size of requested profile + * + * profileCount[OUT] + * - Available number of profiles of the given size which can currently be created. + * + * availableSpans[OUT] + * - For each profile able to be created of the specified size, the span + * it could occupy. + * + * availableSpansCount[OUT] + * - Number of valid entries in availableSpans. + * + * totalProfileCount[OUT] + * - Total number of profiles of the given size which can be created. + * + * totalSpans[OUT] + * - List of spans which can possibly be occupied by profiles of the + * given type. + * + * totalSpansCount[OUT] + * - Number of valid entries in totalSpans. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NVC637_CTRL_CMD_EXEC_PARTITIONS_GET_PROFILE_CAPACITY (0xc63701a9U) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS_MESSAGE_ID" */ + +#define NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS_MESSAGE_ID (0xA9U) + +typedef struct NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS { + NvU32 computeSize; + NvU32 profileCount; + NV_DECLARE_ALIGNED(NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN availableSpans[NVC637_CTRL_MAX_EXEC_PARTITIONS], 8); + NvU32 availableSpansCount; + NvU32 totalProfileCount; + NV_DECLARE_ALIGNED(NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN totalSpans[NVC637_CTRL_MAX_EXEC_PARTITIONS], 8); + NvU32 totalSpansCount; +} NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS; + +// _ctrlc637_h_ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc638.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc638.h new file mode 100644 index 0000000..f9cf5fb --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc638.h @@ -0,0 +1,91 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc638.finn +// + +#include "ctrl/ctrlxxxx.h" +/* AMPERE_SMC_EXEC_PARTITION_REF commands and parameters */ + +#define NVC638_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xC638, NVC638_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NVC638_CTRL_RESERVED (0x00) +#define NVC638_CTRL_EXEC_PARTITION (0x01) + +/*! + * NVC638_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVC638_CTRL_CMD_NULL (0xc6380000) /* finn: Evaluated from "(FINN_AMPERE_SMC_EXEC_PARTITION_REF_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +/*! + * NVC638_CTRL_CMD_GET_UUID + * + * This command returns SHA1 ASCII UUID string as well as the binary UUID for + * the execution partition. The ASCII string format is, + * "MIG-%16x-%08x-%08x-%08x-%024x" (the canonical format of a UUID) + * + * uuid[OUT] + * - Raw UUID bytes + * + * uuidStr[OUT] + * - ASCII UUID string + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + */ + +#define NVC638_UUID_LEN 16 + +/* 'M' 'I' 'G' '-'(x5), '\0x0', extra = 9 */ +#define NVC638_UUID_STR_LEN (0x29) /* finn: Evaluated from "((NVC638_UUID_LEN << 1) + 9)" */ + + + +#define NVC638_CTRL_CMD_GET_UUID (0xc6380101) /* finn: Evaluated from "(FINN_AMPERE_SMC_EXEC_PARTITION_REF_EXEC_PARTITION_INTERFACE_ID << 8) | NVC638_CTRL_GET_UUID_PARAMS_MESSAGE_ID" */ + + + +#define NVC638_CTRL_GET_UUID_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC638_CTRL_GET_UUID_PARAMS { + // C form: NvU8 uuid[NVC638_UUID_LEN]; + NvU8 uuid[NVC638_UUID_LEN]; + + // C form: char uuidStr[NVC638_UUID_STR_LEN]; + char uuidStr[NVC638_UUID_STR_LEN]; +} NVC638_CTRL_GET_UUID_PARAMS;// _ctrlc638_h_ diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc86f.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc86f.h new file mode 100644 index 0000000..eeb8923 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlc86f.h @@ -0,0 +1,165 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. +*/ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc86f.finn +// + + + +#include "nvcfg_sdk.h" + + + +/* HOPPER_CHANNEL_GPFIFO_A control commands and parameters */ + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl906f.h" /* C36F is partially derived from 906F */ +#include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */ +#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F + +#define NVC86F_CTRL_CMD(cat,idx) \ + NVXXXX_CTRL_CMD(0xC36F, NVC86F_CTRL_##cat, idx) + +/* HOPPER_CHANNEL_GPFIFO_A command categories (6bits) */ +#define NVC86F_CTRL_RESERVED (0x00) +#define NVC86F_CTRL_GPFIFO (0x01) +#define NVC86F_CTRL_EVENT (0x02) + +/* + * NVC86F_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned is: NV_OK +*/ +#define NVC86F_CTRL_CMD_NULL (NVC36F_CTRL_CMD_NULL) + + + + + + +/* + * NVC86F_CTRL_GET_CLASS_ENGINEID + * + * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. + * + */ +#define NVC86F_CTRL_GET_CLASS_ENGINEID (NVC36F_CTRL_GET_CLASS_ENGINEID) + +typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC86F_CTRL_GET_CLASS_ENGINEID_PARAMS; + +/* + * NVC86F_CTRL_RESET_CHANNEL + * + * Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information. + * + */ +#define NVC86F_CTRL_CMD_RESET_CHANNEL (NVC36F_CTRL_CMD_RESET_CHANNEL) + +typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC86F_CTRL_CMD_RESET_CHANNEL_PARAMS; + +/* + * NVC86F_CTRL_CMD_GPFIFO_SCHEDULE + * + * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. + * + */ +#define NVC86F_CTRL_CMD_GPFIFO_SCHEDULE (NVC36F_CTRL_CMD_GPFIFO_SCHEDULE) + +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC86F_CTRL_GPFIFO_SCHEDULE_PARAMS; + +/* + * NVC86F_CTRL_CMD_BIND + * + * Please see description of NVA06F_CTRL_CMD_BIND for more information. + */ +#define NVC86F_CTRL_CMD_BIND (NVC36F_CTRL_CMD_BIND) + +typedef NVA06F_CTRL_BIND_PARAMS NVC86F_CTRL_BIND_PARAMS; + +/* + * NVC86F_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. +*/ +#define NVC86F_CTRL_CMD_EVENT_SET_NOTIFICATION (NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION) + +typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC86F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NVC86F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE +#define NVC86F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE +#define NVC86F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT + +/* + * NVC86F_CTRL_CMD_EVENT_SET_TRIGGER + * + * Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information. + */ +#define NVC86F_CTRL_CMD_EVENT_SET_TRIGGER (NVC36F_CTRL_CMD_EVENT_SET_TRIGGER) + + + + + +/* + * NVC86F_CTRL_CMD_GET_MMU_FAULT_INFO + * + * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. + * + */ +#define NVC86F_CTRL_CMD_GET_MMU_FAULT_INFO (NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO) + +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC86F_CTRL_GET_MMU_FAULT_INFO_PARAMS; + +/* + * NVC86F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN + * + * This command returns an opaque work submit token to the caller which + * can be used to write to doorbell register to finish submitting work. + * + * workSubmitToken The 32-bit work submit token + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + * + */ + +#define NVC86F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN (NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN) + +typedef struct NVC86F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS { + NvU32 workSubmitToken; +} NVC86F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS; + +/* _ctrlC86F.h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlcbca.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlcbca.h new file mode 100644 index 0000000..1e47dec --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlcbca.h @@ -0,0 +1,120 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlcbca.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NV_COUNTER_COLLECTION_UNIT control commands and parameters */ + +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xCBCA, NVCBCA_CTRL_##cat, idx) + +#define NVCBCA_CTRL_RESERVED (0x00) +#define NVCBCA_CTRL_COUNTER_COLLECTION_UNIT (0x01) + +/* + * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible return values: + * NV_OK + */ +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_NULL (0xcbca0000) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_SUBSCRIBE + * + * This command is used to subscribe performance counter data + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_SUBSCRIBE (0xcbca0101) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID << 8) | NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS_MESSAGE_ID" */ + +#define NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 bufferSize, 8); + NvU32 counterBlockSize; +} NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS; + +/* + * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_UNSUBSCRIBE + * + * This command is used to unsubscribe performance counter data + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_UNSUBSCRIBE (0xcbca0102) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID << 8) | 0x2" */ + +/* + * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_SET_STREAM_STATE + * + * This command is used to set the counter collection unit stream state + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_SET_STREAM_STATE (0xcbca0103) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID << 8) | NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS_MESSAGE_ID" */ + +#define NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS { + NvBool bStreamState; +} NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS; + +/* + * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_GET_STREAM_STATE + * + * This command is used to get the counter collection unit stream state + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_GET_STREAM_STATE (0xcbca0104) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID << 8) | 0x4" */ + +/* _ctrlcbca_h_ */ + diff --git a/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlxxxx.h b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlxxxx.h new file mode 100644 index 0000000..efe0c58 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/ctrl/ctrlxxxx.h @@ -0,0 +1,67 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2008,2013,2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlxxxx.finn +// + + + +#include "nvtypes.h" + +/* definitions shared by all CTRL interfaces */ + +/* Basic command format: +* cmd_class [31:16], +* cmd_reserved [15:15], +* cmd_reserved [14:14], +* cmd_category [13:8], +* cmd_index [7:0] +*/ + +#define NVXXXX_CTRL_CMD_CLASS 31:16 + +#define NVXXXX_CTRL_CMD_CATEGORY 13:8 +#define NVXXXX_CTRL_CMD_INDEX 7:0 + +/* don't use DRF_NUM - not always available */ +# define NVXXXX_CTRL_CMD(cls,cat,idx) \ + (((cls) << 16) | ((0) << 15) | ((0) << 14) \ + | ((cat) << 8) | ((idx) & 0xFF)) +/* + * NVXXXX_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * This command is valid for all classes. + * + * Possible status values returned are: + * NV_OK + */ +#define NVXXXX_CTRL_CMD_NULL (0x00000000) + +#define NVxxxx_CTRL_LEGACY_PRIVILEGED (0xC0) +#define NVxxxx_CTRL_LEGACY_NON_PRIVILEGED (0x80) diff --git a/userspace/sdks/nv570/nvidia/inc/dpringbuffertypes.h b/userspace/sdks/nv570/nvidia/inc/dpringbuffertypes.h new file mode 100644 index 0000000..b61abaf --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/dpringbuffertypes.h @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2002-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef INCLUDED_DPRINGBUFFERTYPES_H +#define INCLUDED_DPRINGBUFFERTYPES_H + +#define MAX_MESSAGE_LEN 100 +#define MAX_RECORD_COUNT 15 + +typedef enum _DP_RECORD_TYPE +{ + ASSERT_HIT = 135, + LOG_CALL = 136, +} DP_RECORD_TYPE; + +typedef struct _DpAssertHitRecord +{ + NvU64 breakpointAddr; +} DpAssertHitRecord, *PDpAssertHitRecord; + +typedef struct _DpLogCallRecord +{ + char msg[MAX_MESSAGE_LEN]; + NvU64 addr; +} DpLogCallRecord, *PDpLogCallRecord; + +typedef union _DpLogRecord +{ + DpAssertHitRecord dpAssertHitRecord; + DpLogCallRecord dpLogCallRecord; +} DpLogRecord, *PDpLogRecord; + +typedef enum _DpLogQueryType +{ + DpLogQueryTypeAssert = 1, + DpLogQueryTypeCallLog = 2, +} DpLogQueryType, *PDpLogQueryType; + +#endif //INCLUDED_DPRINGBUFFERTYPES_H diff --git a/userspace/sdks/nv570/nvidia/inc/finn_rm_api.h b/userspace/sdks/nv570/nvidia/inc/finn_rm_api.h new file mode 100644 index 0000000..0722dd9 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/finn_rm_api.h @@ -0,0 +1,709 @@ +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// + + +#include + + +#include +#include + +#define FINN_INTERFACE_ID(T) (T ## _INTERFACE_ID) +#define FINN_MESSAGE_ID(T) (T ## _MESSAGE_ID) + +#if (defined(__cplusplus) && __cplusplus >= 201103L) || (defined(_MSVC_LANG) && _MSVC_LANG >= 201103L) +#define FINN_OFFSETOF(T,f) (offsetof(T, f)) +#else +#define FINN_OFFSETOF(T,f) ((NvU64)&((T*)0)->f) +#endif + +#if !defined(_MSC_VER) && (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L) && !defined(__arm) +#define FINN_PACK_COMPOSITE(b) b __attribute__ ((packed)) +#else +#define FINN_PACK_COMPOSITE(b) b +#endif + +/* + * FINN serialization version. A version mismatch indicates incompatibility + * between the serializer and the deserializer. + * + * WARNING: Current serialization version is 0. This is a pre-release version of + * serialization and is only intended to be used in a driver and client compiled + * together. DO NOT use this in firmware or versioned clients. + */ +#define FINN_SERIALIZATION_VERSION 0 + +/* + * FINN compiler version + */ +#define FINN_VERSION_MAJOR 1 +#define FINN_VERSION_MINOR 14 +#define FINN_VERSION_PATCH 0 + +typedef struct FINN_RM_API +{ + NV_DECLARE_ALIGNED(NvU64 version, 8); + NV_DECLARE_ALIGNED(NvU64 payloadSize, 8); + NV_DECLARE_ALIGNED(NvU64 interface, 8); + NV_DECLARE_ALIGNED(NvU64 message, 8); +} FINN_RM_API; + + +/*! + * @brief Serializes an RM API control params struct and copies it into the + * serialization buffer as a FINN message. + * + * @note FinnRmApiSerializeDown is for serializing down the call stack. + * + * FinnRmApiSerializeUp is for serializing up the call stack. It + * frees memory allocated by FinnRmApiDeserializeDown. Use only + * when handling RM API control requests. + * + * @warning One of these may be unimplemented depending on platform. If both + * are implemented, misuse causes memory corruption and memory leaks. + * + * @param[in] interface FINN interface ID of the param struct. + * @param[in] message FINN message ID of the param struct. + * @param[in] src Pointer to the source param struct from which to + * copy the data. + * @param[in, out] dst Double pointer to the destination buffer into + * which to copy the data. *dst will be set to + * *dst + serialized size on success and to the + * location of failed serialization on failure. + * @param[in] dst_size Maximum size of the destination buffer measured in + * `NvU8` units. + * + * @retval NV_OK Serialization successful. + * @retval NV_ERR_INVALID_ARGUMENT Bad function arguments, invalid union + * selector, or invalid enum value. + * @retval NV_ERR_NOT_SUPPORTED Unserializable or nonexistent ID. + * @retval NV_ERR_NOT_COMPATIBLE Container count too large. + * @retval NV_ERR_OUT_OF_RANGE Ranged field exceeded bounds. + * @retval NV_ERR_BUFFER_TOO_SMALL Destination buffer size too small. + */ +/**@{*/ +NV_STATUS FinnRmApiSerializeUp(NvU64 interface, NvU64 message, const void *src, NvU8 **dst, NvLength dst_size); +NV_STATUS FinnRmApiSerializeDown(NvU64 interface, NvU64 message, const void *src, NvU8 **dst, NvLength dst_size); +/**@}*/ + + +/*! + * @brief The following APIs deserialize a FINN message from the serialization + * buffer and copy it into an RM API control params struct. + * + * @note FinnRmApiDeserializeDown is for deserializing down the call stack. It + * allocates deep buffers for primitive pointers in the serialization + * buffer, assuming that it remains in memory. Use only when handling + * RM API control requests. + * + * FinnRmApiDeserializeUp is for deserializing up the call stack. It + * copies deep buffers of primitive pointers into the params struct, + * assuming that memory is already allocated for them. Use only when + * receiving RM API control results. + * + * @warning One of these may be unimplemented depending on platform. If both + * are implemented, misuse causes memory corruption and memory leaks. + * + * @param[in, out] src Double pointer to the source buffer from which to + * copy the data. *src is set to *src + serialized + * size on success and to the location of failed + * deserialization on failure. + * @param[in] src_size Maximum size of the source buffer measured in + * `NvU8` units. + * @param[in, out] dst Pointer to the destination param struct into which + * to copy the data. + * @param[in] dst_size Size of the destination param struct measured in + * `char` units per `sizeof` operator. + * + * @retval NV_OK Deserialization successful. + * @retval NV_ERR_INVALID_ARGUMENT Bad function arguments, invalid union + * selector, invalid enum value, or + * mismatch between expected and actual + * serialized size. + * @retval NV_ERR_NOT_SUPPORTED Unserializable or nonexistent ID. + * @retval NV_ERR_OUT_OF_RANGE Ranged field exceeded bounds. + * @retval NV_ERR_BUFFER_TOO_SMALL Source/destination buffer too small. + * @retval NV_ERR_LIB_RM_VERSION_MISMATCH Version mismatch. + */ +/**@{*/ +NV_STATUS FinnRmApiDeserializeDown(NvU8 **src, NvLength src_size, void *dst, NvLength dst_size); +NV_STATUS FinnRmApiDeserializeUp(NvU8 * const *src, NvLength src_size, void *dst, NvLength dst_size); +/**@}*/ + +/*! + * @brief Calculates the serialized size of an RM API param struct. + * + * @param[in] interface FINN interface ID of the param struct. + * @param[in] message FINN message ID of the param struct. + * @param[in] src Pointer to the param struct. + * + * @retval Non-zero serialized size of param struct on success. + * @retval 0 if the API is unsupported by serialization or src is NULL. + */ +NvU64 FinnRmApiGetSerializedSize(NvU64 interface, NvU64 message, const NvP64 src); + +/*! + * @brief Fetches the unserialized size of an API param struct. + * + * @note The size is measured in `char` units like the `sizeof` operator. + * + * @param[in] interface FINN interface ID of the param struct. + * @param[in] message FINN message ID of the param struct. + * + * @retval Non-zero sizeof param struct on success. + * @retval 0 if the API is unsupported by serialization. + */ +NvU64 FinnRmApiGetUnserializedSize(NvU64 interface, NvU64 message); + +#define NV_RM_ALLOC_INTERFACE_INTERFACE_ID (0xA000U) +typedef FINN_RM_API NV_RM_ALLOC_INTERFACE; +#define FINN_NV01_ROOT_RESERVED_INTERFACE_ID (0x0U) +typedef FINN_RM_API FINN_NV01_ROOT_RESERVED; +#define FINN_NV01_ROOT_CLIENT_INTERFACE_ID (0xdU) +typedef FINN_RM_API FINN_NV01_ROOT_CLIENT; +#define FINN_NV01_ROOT_DIAG_INTERFACE_ID (0x4U) +typedef FINN_RM_API FINN_NV01_ROOT_DIAG; +#define FINN_NV01_ROOT_EVENT_INTERFACE_ID (0x5U) +typedef FINN_RM_API FINN_NV01_ROOT_EVENT; +#define FINN_NV01_ROOT_GPU_INTERFACE_ID (0x2U) +typedef FINN_RM_API FINN_NV01_ROOT_GPU; +#define FINN_NV01_ROOT_GPUACCT_INTERFACE_ID (0xbU) +typedef FINN_RM_API FINN_NV01_ROOT_GPUACCT; +#define FINN_NV01_ROOT_GSYNC_INTERFACE_ID (0x3U) +typedef FINN_RM_API FINN_NV01_ROOT_GSYNC; +#define FINN_NV01_ROOT_NVD_INTERFACE_ID (0x6U) +typedef FINN_RM_API FINN_NV01_ROOT_NVD; +#define FINN_NV01_ROOT_PROC_INTERFACE_ID (0x9U) +typedef FINN_RM_API FINN_NV01_ROOT_PROC; + +#define FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID (0xaU) +typedef FINN_RM_API FINN_NV01_ROOT_SYNC_GPU_BOOST; +#define FINN_NV01_ROOT_SYSTEM_INTERFACE_ID (0x1U) +typedef FINN_RM_API FINN_NV01_ROOT_SYSTEM; +#define FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID (0x3dU) +typedef FINN_RM_API FINN_NV01_ROOT_OS_UNIX; +#define FINN_NV01_ROOT_VGPU_INTERFACE_ID (0xcU) +typedef FINN_RM_API FINN_NV01_ROOT_VGPU; +#define FINN_NV01_ROOT_OS_WINDOWS_INTERFACE_ID (0x3fU) +typedef FINN_RM_API FINN_NV01_ROOT_OS_WINDOWS; +#define FINN_NV01_CONTEXT_DMA_RESERVED_INTERFACE_ID (0x200U) +typedef FINN_RM_API FINN_NV01_CONTEXT_DMA_RESERVED; +#define FINN_NV01_CONTEXT_DMA_DMA_INTERFACE_ID (0x201U) +typedef FINN_RM_API FINN_NV01_CONTEXT_DMA_DMA; +#define FINN_NV01_TIMER_RESERVED_INTERFACE_ID (0x400U) +typedef FINN_RM_API FINN_NV01_TIMER_RESERVED; +#define FINN_NV01_TIMER_TMR_INTERFACE_ID (0x401U) +typedef FINN_RM_API FINN_NV01_TIMER_TMR; +#define FINN_FABRIC_MANAGER_SESSION_RESERVED_INTERFACE_ID (0xf00U) +typedef FINN_RM_API FINN_FABRIC_MANAGER_SESSION_RESERVED; +#define FINN_FABRIC_MANAGER_SESSION_FM_INTERFACE_ID (0xf01U) +typedef FINN_RM_API FINN_FABRIC_MANAGER_SESSION_FM; +#define FINN_FABRIC_MANAGER_SESSION_IMEX_INTERFACE_ID (0xf02U) +typedef FINN_RM_API FINN_FABRIC_MANAGER_SESSION_IMEX; +#define FINN_NV0020_GPU_MANAGEMENT_RESERVED_INTERFACE_ID (0x2000U) +typedef FINN_RM_API FINN_NV0020_GPU_MANAGEMENT_RESERVED; +#define FINN_NV0020_GPU_MANAGEMENT_GPU_MGMT_INTERFACE_ID (0x2001U) +typedef FINN_RM_API FINN_NV0020_GPU_MANAGEMENT_GPU_MGMT; +#define FINN_NV01_MEMORY_SYSTEM_RESERVED_INTERFACE_ID (0x3e00U) +typedef FINN_RM_API FINN_NV01_MEMORY_SYSTEM_RESERVED; +#define FINN_NV01_MEMORY_SYSTEM_MEMORY_INTERFACE_ID (0x3e01U) +typedef FINN_RM_API FINN_NV01_MEMORY_SYSTEM_MEMORY; +#define FINN_NV01_ROOT_USER_RESERVED_INTERFACE_ID (0x4100U) +typedef FINN_RM_API FINN_NV01_ROOT_USER_RESERVED; +#define FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID (0x4101U) +typedef FINN_RM_API FINN_NV01_ROOT_USER_MEMORY; +#define FINN_NV04_DISPLAY_COMMON_RESERVED_INTERFACE_ID (0x7300U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_RESERVED; +#define FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID (0x7311U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_DFP; +#define FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID (0x7313U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_DP; + +#define FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID (0x7304U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_INTERNAL; + +#define FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID (0x7302U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_SPECIFIC; +#define FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID (0x7317U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_STEREO; + +#define FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID (0x7301U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_SYSTEM; +#define FINN_NV01_DEVICE_0_RESERVED_INTERFACE_ID (0x8000U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_RESERVED; +#define FINN_NV01_DEVICE_0_BIF_INTERFACE_ID (0x8001U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_BIF; +#define FINN_NV01_DEVICE_0_BSP_INTERFACE_ID (0x801cU) +typedef FINN_RM_API FINN_NV01_DEVICE_0_BSP; + +#define FINN_NV01_DEVICE_0_DMA_INTERFACE_ID (0x8018U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_DMA; +#define FINN_NV01_DEVICE_0_FB_INTERFACE_ID (0x8013U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_FB; +#define FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID (0x8017U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_FIFO; +#define FINN_NV01_DEVICE_0_GPU_INTERFACE_ID (0x8002U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_GPU; +#define FINN_NV01_DEVICE_0_GR_INTERFACE_ID (0x8011U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_GR; +#define FINN_NV01_DEVICE_0_HOST_INTERFACE_ID (0x8014U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_HOST; +#define FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID (0x8020U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_INTERNAL; +#define FINN_NV01_DEVICE_0_MSENC_INTERFACE_ID (0x801bU) +typedef FINN_RM_API FINN_NV01_DEVICE_0_MSENC; +#define FINN_NV01_DEVICE_0_NVJPG_INTERFACE_ID (0x801fU) +typedef FINN_RM_API FINN_NV01_DEVICE_0_NVJPG; +#define FINN_NV01_DEVICE_0_PERF_INTERFACE_ID (0x8019U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_PERF; + +#define FINN_NV01_DEVICE_0_RC_INTERFACE_ID (0x801dU) +typedef FINN_RM_API FINN_NV01_DEVICE_0_RC; +#define FINN_NV01_DEVICE_0_OS_UNIX_INTERFACE_ID (0x801eU) +typedef FINN_RM_API FINN_NV01_DEVICE_0_OS_UNIX; + +#define FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID (0x9001U) +typedef FINN_RM_API FINN_NV0090_KERNEL_GRAPHICS_CONTEXT; +#define FINN_IMEX_SESSION_INTERFACE_ID (0xf100U) +typedef FINN_RM_API FINN_IMEX_SESSION; +#define FINN_NV01_MEMORY_FABRIC_EXPORT_RESERVED_INTERFACE_ID (0xf400U) +typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_EXPORT_RESERVED; +#define FINN_NV01_MEMORY_FABRIC_EXPORT_EXPORT_INTERFACE_ID (0xf401U) +typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_EXPORT_EXPORT; +#define FINN_NV01_MEMORY_FABRIC_IMPORT_RESERVED_INTERFACE_ID (0xf500U) +typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_IMPORT_RESERVED; +#define FINN_NV01_MEMORY_FABRIC_IMPORT_IMPORT_INTERFACE_ID (0xf501U) +typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_IMPORT_IMPORT; +#define FINN_NV_MEMORY_FABRIC_EXPORT_RESERVED_INTERFACE_ID (0xf700U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORT_RESERVED; +#define FINN_NV_MEMORY_FABRIC_EXPORT_INTERFACE_ID (0xf701U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORT; +#define FINN_NV_MEMORY_FABRIC_RESERVED_INTERFACE_ID (0xf800U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_RESERVED; +#define FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID (0xf801U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_FABRIC; +#define FINN_NV_MEMORY_FABRIC_IMPORT_V2_RESERVED_INTERFACE_ID (0xf900U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORT_V2_RESERVED; +#define FINN_NV_MEMORY_FABRIC_IMPORT_V2_IMPORT_INTERFACE_ID (0xf901U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORT_V2_IMPORT; +#define FINN_NV_MEMORY_FABRIC_EXPORTED_REF_RESERVED_INTERFACE_ID (0xfa00U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORTED_REF_RESERVED; +#define FINN_NV_MEMORY_FABRIC_EXPORTED_REF_EXPORT_REF_INTERFACE_ID (0xfa01U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORTED_REF_EXPORT_REF; +#define FINN_NV_MEMORY_FABRIC_IMPORTED_REF_RESERVED_INTERFACE_ID (0xfb00U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORTED_REF_RESERVED; +#define FINN_NV_MEMORY_FABRIC_IMPORTED_REF_IMPORT_REF_INTERFACE_ID (0xfb01U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORTED_REF_IMPORT_REF; +#define FINN_NV_MEMORY_MULTICAST_FABRIC_RESERVED_INTERFACE_ID (0xfd00U) +typedef FINN_RM_API FINN_NV_MEMORY_MULTICAST_FABRIC_RESERVED; +#define FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID (0xfd01U) +typedef FINN_RM_API FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC; +#define FINN_NV_MEMORY_MAPPER_INTERFACE_ID (0x00FE00U) +typedef FINN_RM_API FINN_NV_MEMORY_MAPPER; + +#define FINN_NV20_SUBDEVICE_0_RESERVED_INTERFACE_ID (0x208000U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_RESERVED; +#define FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID (0x208008U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_BIOS; +#define FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID (0x208018U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_BUS; +#define FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID (0x20802aU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_CE; + +#define FINN_NV20_SUBDEVICE_0_CLK_INTERFACE_ID (0x208010U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_CLK; + +#define FINN_NV20_SUBDEVICE_0_DMA_INTERFACE_ID (0x208025U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_DMA; +#define FINN_NV20_SUBDEVICE_0_DMABUF_INTERFACE_ID (0x20803AU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_DMABUF; +#define FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID (0x208034U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_ECC; + +#define FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID (0x208003U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_EVENT; + +#define FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID (0x208013U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FB; +#define FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID (0x208011U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FIFO; +#define FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID (0x208035U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FLA; +#define FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID (0x208031U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FLCN; +#define FINN_NV20_SUBDEVICE_0_FUSE_INTERFACE_ID (0x208002U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FUSE; + +#define FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID (0x208023U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GPIO; + +#define FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID (0x208001U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GPU; + +#define FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID (0x208012U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GR; +#define FINN_NV20_SUBDEVICE_0_GRMGR_INTERFACE_ID (0x208038U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GRMGR; +#define FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID (0x208036U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GSP; +#define FINN_NV20_SUBDEVICE_0_HSHUB_INTERFACE_ID (0x208041U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_HSHUB; +#define FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID (0x208006U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_I2C; +#define FINN_NV20_SUBDEVICE_0_PMGR_INTERFACE_ID (0x208026U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_PMGR; + +#define FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID (0x20800aU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_INTERNAL; +#define FINN_NV20_SUBDEVICE_0_LPWR_INTERFACE_ID (0x208028U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_LPWR; + +#define FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID (0x208017U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_MC; + +#define FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID (0x208024U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_NVD; + +#define FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID (0x208030U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_NVLINK; + +#define FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID (0x208020U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_PERF; + +#define FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID (0x208022U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_RC; +#define FINN_NV20_SUBDEVICE_0_SEC2_INTERFACE_ID (0x208042U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_SEC2; + +#define FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID (0x208004U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_TIMER; + +#define FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID (0x20803dU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_OS_UNIX; +#define FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID (0x208040U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL; +#define FINN_NV20_SUBDEVICE_0_VOLT_INTERFACE_ID (0x208032U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_VOLT; + +#define FINN_NV2081_BINAPI_RESERVED_INTERFACE_ID (0x208100U) +typedef FINN_RM_API FINN_NV2081_BINAPI_RESERVED; +#define FINN_NV2081_BINAPI_INTERFACE_ID (0x208101U) +typedef FINN_RM_API FINN_NV2081_BINAPI; +#define FINN_NV2082_BINAPI_RESERVED_INTERFACE_ID (0x208200U) +typedef FINN_RM_API FINN_NV2082_BINAPI_RESERVED; +#define FINN_NV2082_BINAPI_INTERFACE_ID (0x208201U) +typedef FINN_RM_API FINN_NV2082_BINAPI; +#define FINN_NV20_SUBDEVICE_DIAG_RESERVED_INTERFACE_ID (0x208f00U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_RESERVED; +#define FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID (0x208f07U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_BIF; +#define FINN_NV20_SUBDEVICE_DIAG_BUS_INTERFACE_ID (0x208f18U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_BUS; + +#define FINN_NV20_SUBDEVICE_DIAG_DMA_INTERFACE_ID (0x208f14U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_DMA; +#define FINN_NV20_SUBDEVICE_DIAG_EVENT_INTERFACE_ID (0x208f10U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_EVENT; +#define FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID (0x208f05U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_FB; +#define FINN_NV20_SUBDEVICE_DIAG_FBIO_INTERFACE_ID (0x208f0aU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_FBIO; +#define FINN_NV20_SUBDEVICE_DIAG_FIFO_INTERFACE_ID (0x208f04U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_FIFO; +#define FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID (0x208f11U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_GPU; +#define FINN_NV20_SUBDEVICE_DIAG_GR_INTERFACE_ID (0x208f12U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_GR; + +#define FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID (0x208f0bU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_MMU; + +#define FINN_NV30_GSYNC_RESERVED_INTERFACE_ID (0x30f100U) +typedef FINN_RM_API FINN_NV30_GSYNC_RESERVED; +#define FINN_NV30_GSYNC_GSYNC_INTERFACE_ID (0x30f101U) +typedef FINN_RM_API FINN_NV30_GSYNC_GSYNC; +#define FINN_NV40_I2C_RESERVED_INTERFACE_ID (0x402c00U) +typedef FINN_RM_API FINN_NV40_I2C_RESERVED; +#define FINN_NV40_I2C_I2C_INTERFACE_ID (0x402c01U) +typedef FINN_RM_API FINN_NV40_I2C_I2C; +#define FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID (0x503c01U) +typedef FINN_RM_API FINN_NV50_THIRD_PARTY_P2P_P2P; +#define FINN_NV50_THIRD_PARTY_P2P_RESERVED_INTERFACE_ID (0x503c00U) +typedef FINN_RM_API FINN_NV50_THIRD_PARTY_P2P_RESERVED; +#define FINN_NV50_CHANNEL_GPFIFO_RESERVED_INTERFACE_ID (0x506f00U) +typedef FINN_RM_API FINN_NV50_CHANNEL_GPFIFO_RESERVED; +#define FINN_NV50_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID (0x506f01U) +typedef FINN_RM_API FINN_NV50_CHANNEL_GPFIFO_GPFIFO; +#define FINN_NV50_DISPLAY_RESERVED_INTERFACE_ID (0x507000U) +typedef FINN_RM_API FINN_NV50_DISPLAY_RESERVED; +#define FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID (0x507001U) +typedef FINN_RM_API FINN_NV50_DISPLAY_CHNCTL; +#define FINN_NV50_DISPLAY_EVENT_INTERFACE_ID (0x507009U) +typedef FINN_RM_API FINN_NV50_DISPLAY_EVENT; +#define FINN_NV50_DISPLAY_OR_INTERFACE_ID (0x507004U) +typedef FINN_RM_API FINN_NV50_DISPLAY_OR; +#define FINN_NV50_DISPLAY_RG_INTERFACE_ID (0x507002U) +typedef FINN_RM_API FINN_NV50_DISPLAY_RG; +#define FINN_NV50_DISPLAY_SEQ_INTERFACE_ID (0x507003U) +typedef FINN_RM_API FINN_NV50_DISPLAY_SEQ; +#define FINN_NV50_DISPLAY_SYSTEM_INTERFACE_ID (0x507007U) +typedef FINN_RM_API FINN_NV50_DISPLAY_SYSTEM; + +#define FINN_NV50_DEFERRED_API_CLASS_RESERVED_INTERFACE_ID (0x508000U) +typedef FINN_RM_API FINN_NV50_DEFERRED_API_CLASS_RESERVED; +#define FINN_NV50_DEFERRED_API_CLASS_DEFERRED_INTERFACE_ID (0x508001U) +typedef FINN_RM_API FINN_NV50_DEFERRED_API_CLASS_DEFERRED; +#define FINN_GT200_DEBUGGER_RESERVED_INTERFACE_ID (0x83de00U) +typedef FINN_RM_API FINN_GT200_DEBUGGER_RESERVED; +#define FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID (0x83de03U) +typedef FINN_RM_API FINN_GT200_DEBUGGER_DEBUG; +#define FINN_GT200_DEBUGGER_FIFO_INTERFACE_ID (0x83de02U) +typedef FINN_RM_API FINN_GT200_DEBUGGER_FIFO; +#define FINN_GT200_DEBUGGER_INTERNAL_INTERFACE_ID (0x83de04U) +typedef FINN_RM_API FINN_GT200_DEBUGGER_INTERNAL; + +#define FINN_NV9010_VBLANK_CALLBACK_RESERVED_INTERFACE_ID (0x901000U) +typedef FINN_RM_API FINN_NV9010_VBLANK_CALLBACK_RESERVED; +#define FINN_NV9010_VBLANK_CALLBACK_INTERFACE_ID (0x901001U) +typedef FINN_RM_API FINN_NV9010_VBLANK_CALLBACK; +#define FINN_FERMI_CONTEXT_SHARE_A_RESERVED_INTERFACE_ID (0x906700U) +typedef FINN_RM_API FINN_FERMI_CONTEXT_SHARE_A_RESERVED; +#define FINN_FERMI_CONTEXT_SHARE_A_TPC_PARTITION_INTERFACE_ID (0x906701U) +typedef FINN_RM_API FINN_FERMI_CONTEXT_SHARE_A_TPC_PARTITION; +#define FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID (0x906702U) +typedef FINN_RM_API FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK; +#define FINN_GF100_CHANNEL_GPFIFO_RESERVED_INTERFACE_ID (0x906f00U) +typedef FINN_RM_API FINN_GF100_CHANNEL_GPFIFO_RESERVED; +#define FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID (0x906f01U) +typedef FINN_RM_API FINN_GF100_CHANNEL_GPFIFO_GPFIFO; +#define FINN_GF100_CHANNEL_GPFIFO_EVENT_INTERFACE_ID (0x906f02U) +typedef FINN_RM_API FINN_GF100_CHANNEL_GPFIFO_EVENT; +#define FINN_GF100_DISP_SW_RESERVED_INTERFACE_ID (0x907200U) +typedef FINN_RM_API FINN_GF100_DISP_SW_RESERVED; +#define FINN_GF100_DISP_SW_DISP_SW_INTERFACE_ID (0x907201U) +typedef FINN_RM_API FINN_GF100_DISP_SW_DISP_SW; +#define FINN_GF100_TIMED_SEMAPHORE_SW_RESERVED_INTERFACE_ID (0x907400U) +typedef FINN_RM_API FINN_GF100_TIMED_SEMAPHORE_SW_RESERVED; +#define FINN_GF100_TIMED_SEMAPHORE_SW_SEM_INTERFACE_ID (0x907401U) +typedef FINN_RM_API FINN_GF100_TIMED_SEMAPHORE_SW_SEM; +#define FINN_GF100_REMAPPER_RESERVED_INTERFACE_ID (0x907f00U) +typedef FINN_RM_API FINN_GF100_REMAPPER_RESERVED; +#define FINN_GF100_REMAPPER_REMAPPER_INTERFACE_ID (0x907f01U) +typedef FINN_RM_API FINN_GF100_REMAPPER_REMAPPER; +#define FINN_GF100_ZBC_CLEAR_RESERVED_INTERFACE_ID (0x909600U) +typedef FINN_RM_API FINN_GF100_ZBC_CLEAR_RESERVED; +#define FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID (0x909601U) +typedef FINN_RM_API FINN_GF100_ZBC_CLEAR_ZBC; +#define FINN_GF100_PROFILER_RESERVED_INTERFACE_ID (0x90cc00U) +typedef FINN_RM_API FINN_GF100_PROFILER_RESERVED; +#define FINN_GF100_PROFILER_HWPM_INTERFACE_ID (0x90cc01U) +typedef FINN_RM_API FINN_GF100_PROFILER_HWPM; +#define FINN_GF100_PROFILER_NVLINK_INTERFACE_ID (0x90cc02U) +typedef FINN_RM_API FINN_GF100_PROFILER_NVLINK; +#define FINN_GF100_PROFILER_POWER_INTERFACE_ID (0x90cc03U) +typedef FINN_RM_API FINN_GF100_PROFILER_POWER; +#define FINN_NV_EVENT_BUFFER_RESERVED_INTERFACE_ID (0x90cd00U) +typedef FINN_RM_API FINN_NV_EVENT_BUFFER_RESERVED; +#define FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID (0x90cd01U) +typedef FINN_RM_API FINN_NV_EVENT_BUFFER_EVENT; +#define FINN_GF100_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0x90e000U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_GRAPHICS_RESERVED; +#define FINN_GF100_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0x90e001U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_GRAPHICS_GRAPHICS; +#define FINN_GF100_SUBDEVICE_FB_RESERVED_INTERFACE_ID (0x90e100U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_FB_RESERVED; +#define FINN_GF100_SUBDEVICE_FB_FB_INTERFACE_ID (0x90e101U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_FB_FB; +#define FINN_GF100_SUBDEVICE_MASTER_RESERVED_INTERFACE_ID (0x90e600U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_MASTER_RESERVED; +#define FINN_GF100_SUBDEVICE_MASTER_MASTER_INTERFACE_ID (0x90e601U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_MASTER_MASTER; +#define FINN_GF100_SUBDEVICE_INFOROM_RESERVED_INTERFACE_ID (0x90e700U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_RESERVED; +#define FINN_GF100_SUBDEVICE_INFOROM_BBX_INTERFACE_ID (0x90e701U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_BBX; +#define FINN_GF100_SUBDEVICE_INFOROM_RPR_INTERFACE_ID (0x90e702U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_RPR; + +#define FINN_GF100_HDACODEC_RESERVED_INTERFACE_ID (0x90ec00U) +typedef FINN_RM_API FINN_GF100_HDACODEC_RESERVED; +#define FINN_GF100_HDACODEC_HDACODEC_INTERFACE_ID (0x90ec01U) +typedef FINN_RM_API FINN_GF100_HDACODEC_HDACODEC; +#define FINN_FERMI_VASPACE_A_RESERVED_INTERFACE_ID (0x90f100U) +typedef FINN_RM_API FINN_FERMI_VASPACE_A_RESERVED; +#define FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID (0x90f101U) +typedef FINN_RM_API FINN_FERMI_VASPACE_A_VASPACE; +#define FINN_KEPLER_CHANNEL_GROUP_A_RESERVED_INTERFACE_ID (0xa06c00U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GROUP_A_RESERVED; +#define FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID (0xa06c01U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO; +#define FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID (0xa06c02U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL; +#define FINN_KEPLER_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xa06f00U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_KEPLER_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xa06f02U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_EVENT; +#define FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xa06f01U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID (0xa06f03U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL; + +#define FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID (0xa08001U) +typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY; +#define FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID (0xa08002U) +typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY; +#define FINN_KEPLER_DEVICE_VGPU_VGPU_OTHERS_INTERFACE_ID (0xa08003U) +typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_VGPU_OTHERS; +#define FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID (0xa08101U) +typedef FINN_RM_API FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG; + +#define FINN_NVA083_GRID_DISPLAYLESS_RESERVED_INTERFACE_ID (0xa08300U) +typedef FINN_RM_API FINN_NVA083_GRID_DISPLAYLESS_RESERVED; +#define FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY_INTERFACE_ID (0xa08301U) +typedef FINN_RM_API FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY; +#define FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID (0xa08401U) +typedef FINN_RM_API FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE; +#define FINN_NVENC_SW_SESSION_NVENC_SW_SESSION_INTERFACE_ID (0xa0bc01U) +typedef FINN_RM_API FINN_NVENC_SW_SESSION_NVENC_SW_SESSION; +#define FINN_NVFBC_SW_SESSION_NVFBC_SW_SESSION_INTERFACE_ID (0xa0bd01U) +typedef FINN_RM_API FINN_NVFBC_SW_SESSION_NVFBC_SW_SESSION; +#define FINN_GK110_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0xa0e000U) +typedef FINN_RM_API FINN_GK110_SUBDEVICE_GRAPHICS_RESERVED; +#define FINN_GK110_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0xa0e001U) +typedef FINN_RM_API FINN_GK110_SUBDEVICE_GRAPHICS_GRAPHICS; +#define FINN_GK110_SUBDEVICE_FB_RESERVED_INTERFACE_ID (0xa0e100U) +typedef FINN_RM_API FINN_GK110_SUBDEVICE_FB_RESERVED; +#define FINN_GK110_SUBDEVICE_FB_FB_INTERFACE_ID (0xa0e101U) +typedef FINN_RM_API FINN_GK110_SUBDEVICE_FB_FB; +#define FINN_KEPLER_CHANNEL_GPFIFO_B_RESERVED_INTERFACE_ID (0xa16f00U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_B_RESERVED; +#define FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID (0xa16f01U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO; +#define FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID (0xa16f02U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT; +#define FINN_KEPLER_CHANNEL_GPFIFO_C_RESERVED_INTERFACE_ID (0xa26f00U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_C_RESERVED; +#define FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID (0xa26f01U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO; +#define FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID (0xa26f02U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT; +#define FINN_MAXWELL_FAULT_BUFFER_A_RESERVED_INTERFACE_ID (0xb06900U) +typedef FINN_RM_API FINN_MAXWELL_FAULT_BUFFER_A_RESERVED; +#define FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID (0xb06901U) +typedef FINN_RM_API FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER; +#define FINN_MAXWELL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xb06f00U) +typedef FINN_RM_API FINN_MAXWELL_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xb06f01U) +typedef FINN_RM_API FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xb06f02U) +typedef FINN_RM_API FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT; +#define FINN_MAXWELL_PROFILER_RESERVED_INTERFACE_ID (0xb0cc00U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_RESERVED; +#define FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID (0xb0cc02U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_INTERNAL; +#define FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID (0xb0cc01U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_PROFILER; +#define FINN_MAXWELL_PROFILER_CONTEXT_RESERVED_INTERFACE_ID (0xb1cc00U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_CONTEXT_RESERVED; +#define FINN_MAXWELL_PROFILER_CONTEXT_PROFILER_INTERFACE_ID (0xb1cc01U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_CONTEXT_PROFILER; +#define FINN_MAXWELL_PROFILER_DEVICE_RESERVED_INTERFACE_ID (0xb2cc00U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_DEVICE_RESERVED; + +#define FINN_MAXWELL_SEC2_SEC2_INTERFACE_ID (0xb6b901U) +typedef FINN_RM_API FINN_MAXWELL_SEC2_SEC2; +#define FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc06f00U) +typedef FINN_RM_API FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc06f01U) +typedef FINN_RM_API FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc06f02U) +typedef FINN_RM_API FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT; +#define FINN_GP100_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0xc0e000U) +typedef FINN_RM_API FINN_GP100_SUBDEVICE_GRAPHICS_RESERVED; +#define FINN_GP100_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0xc0e001U) +typedef FINN_RM_API FINN_GP100_SUBDEVICE_GRAPHICS_GRAPHICS; +#define FINN_GP100_SUBDEVICE_FB_RESERVED_INTERFACE_ID (0xc0e100U) +typedef FINN_RM_API FINN_GP100_SUBDEVICE_FB_RESERVED; +#define FINN_GP100_SUBDEVICE_FB_FB_INTERFACE_ID (0xc0e101U) +typedef FINN_RM_API FINN_GP100_SUBDEVICE_FB_FB; +#define FINN_VOLTA_GSP_GSP_INTERFACE_ID (0xc31001U) +typedef FINN_RM_API FINN_VOLTA_GSP_GSP; +#define FINN_ACCESS_COUNTER_NOTIFY_BUFFER_RESERVED_INTERFACE_ID (0xc36500U) +typedef FINN_RM_API FINN_ACCESS_COUNTER_NOTIFY_BUFFER_RESERVED; +#define FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID (0xc36501U) +typedef FINN_RM_API FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER; +#define FINN_MMU_FAULT_BUFFER_RESERVED_INTERFACE_ID (0xc36900U) +typedef FINN_RM_API FINN_MMU_FAULT_BUFFER_RESERVED; +#define FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER_INTERFACE_ID (0xc36901U) +typedef FINN_RM_API FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER; +#define FINN_VOLTA_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc36f00U) +typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc36f01U) +typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc36f02U) +typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT; +#define FINN_NVC370_DISPLAY_RESERVED_INTERFACE_ID (0xc37000U) +typedef FINN_RM_API FINN_NVC370_DISPLAY_RESERVED; +#define FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID (0xc37001U) +typedef FINN_RM_API FINN_NVC370_DISPLAY_CHNCTL; +#define FINN_NVC370_DISPLAY_EVENT_INTERFACE_ID (0xc37009U) +typedef FINN_RM_API FINN_NVC370_DISPLAY_EVENT; +#define FINN_NVC370_DISPLAY_RG_INTERFACE_ID (0xc37002U) +typedef FINN_RM_API FINN_NVC370_DISPLAY_RG; +#define FINN_NVC370_DISPLAY_VERIF_INTERFACE_ID (0xc37006U) +typedef FINN_RM_API FINN_NVC370_DISPLAY_VERIF; +#define FINN_NVC372_DISPLAY_SW_RESERVED_INTERFACE_ID (0xc37200U) +typedef FINN_RM_API FINN_NVC372_DISPLAY_SW_RESERVED; +#define FINN_NVC372_DISPLAY_SW_CHNCTL_INTERFACE_ID (0xc37201U) +typedef FINN_RM_API FINN_NVC372_DISPLAY_SW_CHNCTL; + +#define FINN_GV100_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0xc3e000U) +typedef FINN_RM_API FINN_GV100_SUBDEVICE_GRAPHICS_RESERVED; +#define FINN_GV100_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0xc3e001U) +typedef FINN_RM_API FINN_GV100_SUBDEVICE_GRAPHICS_GRAPHICS; +#define FINN_GV100_SUBDEVICE_FB_RESERVED_INTERFACE_ID (0xc3e100U) +typedef FINN_RM_API FINN_GV100_SUBDEVICE_FB_RESERVED; +#define FINN_GV100_SUBDEVICE_FB_FB_INTERFACE_ID (0xc3e101U) +typedef FINN_RM_API FINN_GV100_SUBDEVICE_FB_FB; +#define FINN_TURING_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc46f00U) +typedef FINN_RM_API FINN_TURING_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_TURING_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc46f01U) +typedef FINN_RM_API FINN_TURING_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_TURING_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc46f02U) +typedef FINN_RM_API FINN_TURING_CHANNEL_GPFIFO_A_EVENT; +#define FINN_AMPERE_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc56f00U) +typedef FINN_RM_API FINN_AMPERE_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc56f01U) +typedef FINN_RM_API FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_AMPERE_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc56f02U) +typedef FINN_RM_API FINN_AMPERE_CHANNEL_GPFIFO_A_EVENT; +#define FINN_AMPERE_SMC_PARTITION_REF_RESERVED_INTERFACE_ID (0xc63700U) +typedef FINN_RM_API FINN_AMPERE_SMC_PARTITION_REF_RESERVED; +#define FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID (0xc63701U) +typedef FINN_RM_API FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS; +#define FINN_AMPERE_SMC_EXEC_PARTITION_REF_RESERVED_INTERFACE_ID (0xc63800U) +typedef FINN_RM_API FINN_AMPERE_SMC_EXEC_PARTITION_REF_RESERVED; +#define FINN_AMPERE_SMC_EXEC_PARTITION_REF_EXEC_PARTITION_INTERFACE_ID (0xc63801U) +typedef FINN_RM_API FINN_AMPERE_SMC_EXEC_PARTITION_REF_EXEC_PARTITION; +#define FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_RESERVED_INTERFACE_ID (0xc76300U) +typedef FINN_RM_API FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_RESERVED; +#define FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER_INTERFACE_ID (0xc76301U) +typedef FINN_RM_API FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER; +#define FINN_HOPPER_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc86f00U) +typedef FINN_RM_API FINN_HOPPER_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_HOPPER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc86f01U) +typedef FINN_RM_API FINN_HOPPER_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_HOPPER_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc86f02U) +typedef FINN_RM_API FINN_HOPPER_CHANNEL_GPFIFO_A_EVENT; + +#define FINN_NV_COUNTER_COLLECTION_UNIT_RESERVED_INTERFACE_ID (0xcbca00U) +typedef FINN_RM_API FINN_NV_COUNTER_COLLECTION_UNIT_RESERVED; +#define FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID (0xcbca01U) +typedef FINN_RM_API FINN_NV_COUNTER_COLLECTION_UNIT_CCU; +#define FINN_NVE2_SYNCPOINT_BASE_RESERVED_INTERFACE_ID (0xe2ad00U) +typedef FINN_RM_API FINN_NVE2_SYNCPOINT_BASE_RESERVED; +#define FINN_NVE2_SYNCPOINT_BASE_SYNCPOINT_BASE_INTERFACE_ID (0xe2ad01U) +typedef FINN_RM_API FINN_NVE2_SYNCPOINT_BASE_SYNCPOINT_BASE; diff --git a/userspace/sdks/nv570/nvidia/inc/mmu_fmt_types.h b/userspace/sdks/nv570/nvidia/inc/mmu_fmt_types.h new file mode 100644 index 0000000..ecbe2aa --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/mmu_fmt_types.h @@ -0,0 +1,151 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: mmu_fmt_types.finn +// + + + + +/*! + * @file mmu_fmt_types.h + * + * @brief Types used to describre MMU HW formats. + */ +#include "nvtypes.h" + +// Forward declarations. + + +/*! + * Generic MMU page directory/table level format description. + * + * Since the terminology of page directories and tables varies, + * the following describes the interpretation assumed here. + * + * Each level of virtual address translation is described by a range of + * virtual address bits. + * These bits index into a contiguous range of physical memory referred to + * generally as a "page level." + * Page level memory is interpreted as an array of entries, with each entry + * describing the next step of virtual to physical translation. + * + * Each entry in a given level may be interpreted as either a PDE or PTE. + * 1. A PDE (page directory entry) points to one or more "sub-levels" that + * continue the VA translation recursively. + * 2. A PTE (page table entry) is the base case, pointing to a physical page. + * + * The decision to treat an entry as a PDE or PTE may be static for a level. + * Levels that only contain PDEs are referred to as page directories. + * Levels that only contain PTEs are referred to as page tables. + * + * However, some formats have levels that may contain a mix of PDEs and PTEs, + * with the intpretation based on a "cutoff" bit in each entry (e.g. PTE valid bit). + * Such levels are referred to as "polymorphic page levels" since they can be + * viewed as both a page directory and a page table. + */ +typedef struct MMU_FMT_LEVEL { + /*! + * First virtual address bit that this page level covers. + */ + NvU8 virtAddrBitLo; + + /*! + * Last virtual address bit that this page level covers. + */ + NvU8 virtAddrBitHi; + + /*! + * Size in bytes of each entry within a level instance. + */ + NvU8 entrySize; + + /*! + * Indicates if this level can contain PTEs. + */ + NvBool bPageTable; + + /*! + * Number of sub-levels pointed to by PDEs in this level in + * range [0, MMU_FMT_MAX_SUB_LEVELS]. + * 0 indicates this level cannot contain PDEs. + */ + NvU8 numSubLevels; + + /*! + * Information tag used to decode internal level naming. + * Used for verif. + * */ + NvU32 pageLevelIdTag; + + + /*! + * Array of sub-level formats of length numSubLevels. + * + * @warning This array results in a circular reference to MMU_FMT_LEVEL. + * This can present an issue for FINN serialization and may have to + * be refactored before MMU_FMT_LEVEL can be serialized. + */ + NV_DECLARE_ALIGNED(struct MMU_FMT_LEVEL *subLevels, 8); +} MMU_FMT_LEVEL; + +/*! + * Maximum number of pointers to sub-levels within a page directory entry. + * + * Standard page directory entries (PDEs) point to a single sub-level, + * either the next page directory level in the topology or a leaf page table. + * + * However, some formats contain PDEs that point to more than one sub-level. + * These sub-levels are translated by HW in parallel to support multiple + * page sizes at a higher granularity (e.g. for migration between + * 4K system memory pages and big video memory pages for GPU MMU). + * + * The current supported formats have a maximum of 2 parallel sub-levels, + * often referred to as "dual PDE" or "dual page table" support. + * + * Example for Fermi GPU HW: + * Sub-level 0 corresponds to big page table pointer. + * Sub-level 1 corresponds to small page table pointer. + * + * This number is very unlikely to change, but it is defined to + * simplify SW handling, encouraging loops over "dual copy-paste." + */ +#define MMU_FMT_MAX_SUB_LEVELS 2 + +/*! + * Valid values for the pageLevelIdTag field. + * These values are used to identify the internal naming of the page level. + * Used for verif purposes. + */ +#define MMU_FMT_PT_SURF_ID_PD0 0 +#define MMU_FMT_PT_SURF_ID_PD1 1 +#define MMU_FMT_PT_SURF_ID_PD2 2 +#define MMU_FMT_PT_SURF_ID_PD3 3 +#define MMU_FMT_PT_SURF_ID_PD4 4 +#define MMU_FMT_PT_SURF_ID_PT_4K 5 +#define MMU_FMT_PT_SURF_ID_PT_BIG 6 diff --git a/userspace/sdks/nv570/nvidia/inc/nv-hypervisor.h b/userspace/sdks/nv570/nvidia/inc/nv-hypervisor.h new file mode 100644 index 0000000..6ee37f7 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/nv-hypervisor.h @@ -0,0 +1,123 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NV_HYPERVISOR_H_ +#define _NV_HYPERVISOR_H_ + +#include + +// Enums for supported hypervisor types. +// New hypervisor type should be added before OS_HYPERVISOR_UNKNOWN +typedef enum _HYPERVISOR_TYPE +{ + OS_HYPERVISOR_XEN = 0, + OS_HYPERVISOR_VMWARE, + OS_HYPERVISOR_HYPERV, + OS_HYPERVISOR_KVM, + OS_HYPERVISOR_UNKNOWN +} HYPERVISOR_TYPE; + +#define CMD_VGPU_VFIO_WAKE_WAIT_QUEUE 0 +#define CMD_VGPU_VFIO_INJECT_INTERRUPT 1 +#define CMD_VGPU_VFIO_REGISTER_MDEV 2 +#define CMD_VGPU_VFIO_PRESENT 3 + +#define MAX_VF_COUNT_PER_GPU 64 + +typedef enum _VGPU_TYPE_INFO +{ + VGPU_TYPE_NAME = 0, + VGPU_TYPE_DESCRIPTION, + VGPU_TYPE_INSTANCES, +} VGPU_TYPE_INFO; + +typedef struct +{ + void *vgpuVfioRef; + void *waitQueue; + void *nv; + NvU32 *vgpuTypeIds; + NvU32 numVgpuTypes; + NvU32 domain; + NvU8 bus; + NvU8 slot; + NvU8 function; + NvBool is_virtfn; +} vgpu_vfio_info; + +typedef struct +{ + NvU32 domain; + NvU8 bus; + NvU8 slot; + NvU8 function; + NvBool isNvidiaAttached; + NvBool isMdevAttached; +} vgpu_vf_pci_info; + +typedef enum VGPU_CMD_PROCESS_VF_INFO_E +{ + NV_VGPU_SAVE_VF_INFO = 0, + NV_VGPU_REMOVE_VF_PCI_INFO = 1, + NV_VGPU_REMOVE_VF_MDEV_INFO = 2, + NV_VGPU_GET_VF_INFO = 3 +} VGPU_CMD_PROCESS_VF_INFO; + +typedef enum VGPU_DEVICE_STATE_E +{ + NV_VGPU_DEV_UNUSED = 0, + NV_VGPU_DEV_OPENED = 1, + NV_VGPU_DEV_IN_USE = 2 +} VGPU_DEVICE_STATE; + +typedef enum _VMBUS_CMD_TYPE +{ + VMBUS_CMD_TYPE_INVALID = 0, + VMBUS_CMD_TYPE_SETUP = 1, + VMBUS_CMD_TYPE_SENDPACKET = 2, + VMBUS_CMD_TYPE_CLEANUP = 3, +} VMBUS_CMD_TYPE; + +typedef struct +{ + NvU32 request_id; + NvU32 page_count; + NvU64 *pPfns; + void *buffer; + NvU32 bufferlen; +} vmbus_send_packet_cmd_params; + + +typedef struct +{ + NvU32 override_sint; + NvU8 *nv_guid; +} vmbus_setup_cmd_params; + +/* + * Function prototypes + */ + +HYPERVISOR_TYPE NV_API_CALL nv_get_hypervisor_type(void); + +#endif // _NV_HYPERVISOR_H_ diff --git a/userspace/sdks/nv570/nvidia/inc/nv-kernel-interface-api.h b/userspace/sdks/nv570/nvidia/inc/nv-kernel-interface-api.h new file mode 100644 index 0000000..183f9b4 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/nv-kernel-interface-api.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NV_KERNEL_INTERFACE_API_H +#define _NV_KERNEL_INTERFACE_API_H +/************************************************************************************************************** +* +* File: nv-kernel-interface-api.h +* +* Description: +* Defines the NV API related macros. +* +**************************************************************************************************************/ + +#if NVOS_IS_UNIX && NVCPU_IS_X86_64 && defined(__use_altstack__) +#define NV_API_CALL __attribute__((altstack(0))) +#else +#define NV_API_CALL +#endif + +#endif /* _NV_KERNEL_INTERFACE_API_H */ diff --git a/userspace/sdks/nv570/nvidia/inc/nv_stdarg.h b/userspace/sdks/nv570/nvidia/inc/nv_stdarg.h new file mode 100644 index 0000000..b23f7f7 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/nv_stdarg.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _NV_STDARG_H_ +#define _NV_STDARG_H_ + +#if defined(NV_KERNEL_INTERFACE_LAYER) && defined(NV_LINUX) + #include "conftest.h" + #if defined(NV_LINUX_STDARG_H_PRESENT) + #include + #else + #include + #endif +#else + #include +#endif + +#endif // _NV_STDARG_H_ diff --git a/userspace/sdks/nv570/nvidia/inc/nv_vgpu_types.h b/userspace/sdks/nv570/nvidia/inc/nv_vgpu_types.h new file mode 100644 index 0000000..fae9985 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/nv_vgpu_types.h @@ -0,0 +1,61 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: nv_vgpu_types.finn +// + + + + +/* XAPIGEN - this file is not suitable for (nor needed by) xapigen. */ +/* Rather than #ifdef out every such include in every sdk */ +/* file, punt here. */ +#include "nvtypes.h" + /* ! XAPIGEN */ + +#define VM_UUID_SIZE 16 +#define INVALID_VGPU_DEV_INST 0xFFFFFFFFU +#define MAX_VGPU_DEVICES_PER_VM 16U + +/* This enum represents the current state of guest dependent fields */ +typedef enum GUEST_VM_INFO_STATE { + GUEST_VM_INFO_STATE_UNINITIALIZED = 0, + GUEST_VM_INFO_STATE_INITIALIZED = 1, +} GUEST_VM_INFO_STATE; + +/* This enum represents types of VM identifiers */ +typedef enum VM_ID_TYPE { + VM_ID_DOMAIN_ID = 0, + VM_ID_UUID = 1, +} VM_ID_TYPE; + +/* This structure represents VM identifier */ +typedef union VM_ID { + NvU8 vmUuid[VM_UUID_SIZE]; + NV_DECLARE_ALIGNED(NvU64 vmId, 8); +} VM_ID; diff --git a/userspace/sdks/nv570/nvidia/inc/nvcd.h b/userspace/sdks/nv570/nvidia/inc/nvcd.h new file mode 100644 index 0000000..6c462eb --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/nvcd.h @@ -0,0 +1,159 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2002-2002 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVCD_H +#define NVCD_H + +//****************************************************************************** +// +// Module Name: NVCD.H +// +// This file contains structures and constants that define the NV specific +// data to be returned by the miniport's new VideoBugCheckCallback. The callback +// can return up to 4k bytes of data that will be appended to the dump file. +// The bugcheck callback is currently only invoked for bugcheck 0xEA failures. +// The buffer returned contains a top level header, followed by a variable +// number of data records. The top level header contains an ASCII signature +// that can be located with a search as well as a GUID for unique identification +// of the crash dump layout, i.e. future bugcheck callbacks can define a new +// GUID to redefine the entire crash dump layout. A checksum and crash dump +// size values are also included to insure crash dump data integrity. The +// data records each contain a header indicating what group the data belongs to +// as well as the actual record type and size. This flexibility allows groups +// to define and extend the information in their records without adversely +// affecting the code in the debugger extension that has to parse and display +// this information. The structures for these individual data records are +// contained in separate header files for each group. +// +//****************************************************************************** +#include "nvtypes.h" + +// Define the GUID type for non-Windows OSes + +#ifndef GUID_DEFINED +#define GUID_DEFINED +typedef struct _GUID { + NvU32 Data1; + NvU16 Data2; + NvU16 Data3; + NvU8 Data4[8]; +} GUID, *LPGUID; +#endif + +// Define the crash dump ASCII tag value and the dump format GUIDs +#define NVCD_SIGNATURE 0x4443564E /* ASCII crash dump signature "NVCD" */ + +#define GUID_NVCD_DUMP_V1 { /* e3d5dc6e-db7d-4e28-b09e-f59a942f4a24 */ \ + 0xe3d5dc6e, 0xdb7d, 0x4e28, \ + {0xb0, 0x9e, 0xf5, 0x9a, 0x94, 0x2f, 0x4a, 0x24}\ +}; +#define GUID_NVCD_DUMP_V2 { /* cd978ac1-3aa1-494b-bb5b-e93daf2b0536 */ \ + 0xcd978ac1, 0x3aa1, 0x494b, \ + {0xbb, 0x5b, 0xe9, 0x3d, 0xaf, 0x2b, 0x05, 0x36}\ +}; +#define GUID_NVCDMP_RSVD1 { /* 391fc656-a37c-4574-8d57-b29a562f909b */ \ + 0x391fc656, 0xa37c, 0x4574, \ + {0x8d, 0x57, 0xb2, 0x9a, 0x56, 0x2f, 0x90, 0x9b}\ +}; +#define GUID_NVCDMP_RSVD2 { /* c6d9982d-1ba9-4f80-badd-3dc992d41b46 */ \ + 0xc6d9982d, 0x1ba9, 0x4f80, \ + {0xba, 0xdd, 0x3d, 0xc9, 0x92, 0xd4, 0x1b, 0x46}\ +}; + +// RC 2.0 NVCD (NV crash dump) GUID +#define GUID_NVCD_RC2_V1 { /* d3793533-a4a6-46d3-97f2-1446cfdc1ee7 */ \ + 0xd3793533, 0xa4a6, 0x46d3, \ + {0x97, 0xf2, 0x14, 0x46, 0xcf, 0xdc, 0x1e, 0xe7}\ +}; + + +// Define NVIDIA crash dump header structure (First data block in crash dump) +typedef struct +{ + NvU32 dwSignature; // ASCII crash dump signature "NVCD" + GUID gVersion; // GUID for crashdump file (Version) + NvU32 dwSize; // Size of the crash dump data + NvU8 cCheckSum; // Crash dump checksum (Zero = ignore) + NvU8 cFiller[3]; // Filler (Possible CRC value) +} NVCD_HEADER; +typedef NVCD_HEADER *PNVCD_HEADER; + +// Define the crash dump record groups +typedef enum +{ + NvcdGroup = 0, // NVIDIA crash dump group (System NVCD records) + RmGroup = 1, // Resource manager group (RM records) + DriverGroup = 2, // Driver group (Driver/miniport records) + HardwareGroup = 3, // Hardware group (Hardware records) + InstrumentationGroup = 4, // Instrumentation group (Special records) +} NVCD_GROUP_TYPE; + +// Define the crash dump group record types (Single end of data record type) +typedef enum +{ + EndOfData = 0, // End of crash dump data record + CompressedDataHuffman = 1, // Compressed huffman data +} NVCD_RECORD_TYPE; + +// Define the crash dump data record header +typedef struct +{ + NvU8 cRecordGroup; // Data record group (NVCD_GROUP_TYPE) + NvU8 cRecordType; // Data record type (See group header) + NvU16 wRecordSize; // Size of the data record in bytes +} NVCD_RECORD; +typedef NVCD_RECORD *PNVCD_RECORD; + +// Define the EndOfData record structure +typedef struct +{ + NVCD_RECORD Header; // End of data record header +} EndOfData_RECORD; +typedef EndOfData_RECORD *PEndOfData_RECORD; + +// +// Generic mini-record type (keep the size at 64bits) +// +typedef struct +{ + NVCD_RECORD Header; // header for mini record + NvU32 Payload; // 32 bit payload value +} NVCDMiniRecord; +typedef NVCDMiniRecord *PNVCDMiniRecord; + +// +// Generic record collection type +// +typedef struct +{ + NVCD_RECORD Header; // generic header to binary type this in OCA buffer + // size is actual size of this struct + all items in collection + NvU32 NumRecords; // number of records this collection contain + NVCD_RECORD FirstRecord; // first record, its data follow +} NVCDRecordCollection; +typedef NVCDRecordCollection *PNVCDRecordCollection; + +#define COLL_HEADER_SIZEOF (sizeof(NVCDRecordCollection) - sizeof(NVCD_RECORD)) + + +#endif // NVCD_H diff --git a/userspace/sdks/nv570/nvidia/inc/nvcfg_sdk.h b/userspace/sdks/nv570/nvidia/inc/nvcfg_sdk.h new file mode 100644 index 0000000..4ce8d4b --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/nvcfg_sdk.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef NV_CFG_SDK_INCLUDED +#define NV_CFG_SDK_INCLUDED + + +#endif // NV_CFG_SDK_INCLUDED diff --git a/userspace/sdks/nv570/nvidia/inc/nvdeprecated.h b/userspace/sdks/nv570/nvidia/inc/nvdeprecated.h new file mode 100644 index 0000000..75d99cc --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/nvdeprecated.h @@ -0,0 +1,133 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NV_DEPRECATED_H +#define NV_DEPRECATED_H + +/*! + * @file nvdeprecated.h + * + * @brief Deprecation in the NVIDIA SDK + * + * Why deprecate: + * Code is deprecated when you want to remove a feature entirely, but cannot + * do so immediately, nor in a single step, due to a requirement to remain + * backward compatible (keep older clients working). + * + * Backwards compatibility: + * Deprecated symbols and features may be supported for an unknown amount of + * time. "Deprecated" means that we want that time interval to be small, but + * that may not be under our control. + * + * This file provides the following ways to support deprecated features: + * + * 1) Defining NV_STRICT_SDK before including a SDK headers. This will + * remove *all* deprecated APIs from the NV SDK, for example: + * + * #define NV_STRICT_SDK + * #include "sdk/foo.h" + * + * 2) Defining the per-feature compatibility setting before including the + * SDK, for example: + * + * #define NV_DEPRECATED_NVOS_STATUS 0 // enable compatibility mode + * #include "sdk/foo.h" + * + * How to deprecate a feature in the SDK: + * + * 1) Define the deprecated feature in this file. Often, you'll want to + * start with SDK compatibility enabled by default, for example: + * + * #ifndef NV_DEPRECATED_FEATURE_NAME + * #define NV_DEPRECATED_FEATURE_NAME 0 + * #endif + * + * 2) Wrap SDK definitions with compatibility #ifdefs: + * + * #if NV_DEPRECATED_COMPAT(FEATURE_NAME) + * ...legacy definitions... + * #endif + * + * 3) In the API implementation, consider stubbing or wrapping the new API. + * + * 4) Update older clients: file bugs to track this effort. Bug numbers + * should be placed in comments near the deprecated features that RM is + * supporting. That way, people reading the code can easily find the + * bug(s) that show the status of completely removing the deprecated + * feature. + * + * 5) Once all the client (calling) code has been upgraded, change the + * macro to "compatibility off". This is a little more cautious and + * conservative than jumping directly to step (6), because it allows you + * to recover from a test failure (remember, there are extended, offline + * tests that are not, unfortunately, run in DVS, nor per-CL checkin) + * with a tiny change in code. + * + * 6) Once the code base has migrated, remove all definitions from the SDK. + */ + +/* + * \defgroup Deprecated SDK Features + * + * 0 = Compatibility on by default (i.e.: defines present in SDK) + * 1 = Compatibility off by default (i.e.: defines NOT in SDK) + * + * @{ + */ + +/*! + * RM Config Get/Set API is deprecated and RmControl should be used instead. + * Bugs: XXXXXX, XXXXXX, etc + */ +#ifndef NV_DEPRECATED_RM_CONFIG_GET_SET +#define NV_DEPRECATED_RM_CONFIG_GET_SET 0 +#endif + +#ifndef NV_DEPRECATED_NVOS_STATUS +/* NVOS_STATUS codes is deprecated. NV_STATUS to be used instead */ +#define NV_DEPRECATED_NVOS_STATUS 0 +#endif + +#ifndef NV_DEPRECATED_RM_STATUS +/* RM_STATUS codes is deprecated. NV_STATUS to be used instead */ +#define NV_DEPRECATED_RM_STATUS 0 +#endif + +#ifndef NV_DEPRECATED_UNSAFE_HANDLES +/* Using NvU32 for handles is deprecated. NvHandle to be used instead */ +#define NV_DEPRECATED_UNSAFE_HANDLES 0 +#endif + +/**@}*/ + +/*! + * Utility Macros + */ + +#ifdef NV_STRICT_SDK +// In strict mode, all obsolete features are unavailable in the SDK. +#define NV_DEPRECATED_COMPAT(feature) 0 +#else +#define NV_DEPRECATED_COMPAT(feature) (!NV_DEPRECATED_##feature) +#endif + +#endif diff --git a/userspace/sdks/nv570/nvidia/inc/nvdisptypes.h b/userspace/sdks/nv570/nvidia/inc/nvdisptypes.h new file mode 100644 index 0000000..90d8ac0 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/nvdisptypes.h @@ -0,0 +1,92 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + /***************************************************************************\ +|* *| +|* NV Display Common Types *| +|* *| +|* defines the common display types. *| +|* *| + \***************************************************************************/ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: nvdisptypes.finn +// + + + + +#include "nvtypes.h" + + + +typedef enum NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP { + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_DEFAULT = 0, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 = 1, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 = 2, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 = 3, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 = 4, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 = 5, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 = 6, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 = 7, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 = 8, + NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 = 9, +} NV_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP; + + + +typedef NvU32 NV_DISP_LOCK_PIN; + +#define NV_DISP_LOCK_PIN_0 0x0 +#define NV_DISP_LOCK_PIN_1 0x1 +#define NV_DISP_LOCK_PIN_2 0x2 +#define NV_DISP_LOCK_PIN_3 0x3 +#define NV_DISP_LOCK_PIN_4 0x4 +#define NV_DISP_LOCK_PIN_5 0x5 +#define NV_DISP_LOCK_PIN_6 0x6 +#define NV_DISP_LOCK_PIN_7 0x7 +#define NV_DISP_LOCK_PIN_8 0x8 +#define NV_DISP_LOCK_PIN_9 0x9 +#define NV_DISP_LOCK_PIN_A 0xA +#define NV_DISP_LOCK_PIN_B 0xB +#define NV_DISP_LOCK_PIN_C 0xC +#define NV_DISP_LOCK_PIN_D 0xD +#define NV_DISP_LOCK_PIN_E 0xE +#define NV_DISP_LOCK_PIN_F 0xF + +// Value used solely for HW initialization +#define NV_DISP_LOCK_PIN_UNSPECIFIED 0x10 + + + +typedef NvU32 NV_DISP_LOCK_MODE; + +#define NV_DISP_LOCK_MODE_NO_LOCK 0x0 +#define NV_DISP_LOCK_MODE_FRAME_LOCK 0x1 +#define NV_DISP_LOCK_MODE_RASTER_LOCK 0x3 + diff --git a/userspace/sdks/nv570/nvidia/inc/nvdump.h b/userspace/sdks/nv570/nvidia/inc/nvdump.h new file mode 100644 index 0000000..32c6c76 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/nvdump.h @@ -0,0 +1,163 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +//////////////////////////////////////////////////////////////////////////////// +// +// Module: nvDump.h +// Shared definitions for HW/SW dumping facility residing in resman/rc. +// +// ************************************************************************** + +#ifndef _NVDUMP_H_ +#define _NVDUMP_H_ + +#include "nvtypes.h" + +//------------------------------------------------------------------------- +// DEFINTIONS +//------------------------------------------------------------------------- + +#define NVDUMP_SUB_ALLOC_NOT_ENCODED 0x01 +#define NVDUMP_SUB_ALLOC_VALID 0x02 +#define NVDUMP_SUB_ALLOC_HAS_MORE 0x04 + +#define NVDUMP_DEBUG_BUFFER_MAX_SIZE 4096 // max of 4K per buffer +#define NVDUMP_DEBUG_BUFFER_MAX_SUBALLOCATIONS 256 + +#define NVDUMP_CONFIG_SIGNATURE "NVDUMPCONFIGSIG" // multiple of 8 bytes + +typedef enum +{ + // The following components are GPU instance specific: + NVDUMP_COMPONENT_DEBUG_BUFFERS = 0, + NVDUMP_COMPONENT_ENG_MC, + NVDUMP_COMPONENT_ENG_FIFO, + NVDUMP_COMPONENT_ENG_GRAPHICS, + NVDUMP_COMPONENT_ENG_FB, + NVDUMP_COMPONENT_ENG_DISP, + NVDUMP_COMPONENT_ENG_FAN, + NVDUMP_COMPONENT_ENG_THERMAL, + NVDUMP_COMPONENT_ENG_FUSE, + NVDUMP_COMPONENT_ENG_VBIOS, + NVDUMP_COMPONENT_ENG_PERF, + NVDUMP_COMPONENT_ENG_BUS, + NVDUMP_COMPONENT_ENG_PMU, + NVDUMP_COMPONENT_ENG_ALL, + NVDUMP_COMPONENT_ENG_CE, + NVDUMP_COMPONENT_ENG_GPU, + NVDUMP_COMPONENT_ENG_LPWR, + NVDUMP_COMPONENT_ENG_NVD, + NVDUMP_COMPONENT_ENG_VOLT, + NVDUMP_COMPONENT_ENG_CLK, + NVDUMP_COMPONENT_ENG_SEC2, + NVDUMP_COMPONENT_ENG_NVLINK, + NVDUMP_COMPONENT_ENG_BSP, + NVDUMP_COMPONENT_ENG_DPU, + NVDUMP_COMPONENT_ENG_FBFLCN, + NVDUMP_COMPONENT_ENG_HDA, + NVDUMP_COMPONENT_ENG_MSENC, + NVDUMP_COMPONENT_ENG_GSP, + NVDUMP_COMPONENT_ENG_INFOROM, + NVDUMP_COMPONENT_ENG_GCX, + // The following components are global to the system: + NVDUMP_COMPONENT_SYS_RCDB = 0x400, + NVDUMP_COMPONENT_SYS_SYSINFO, + NVDUMP_COMPONENT_SYS_ALL, + // The following components are nvlog related. + NVDUMP_COMPONENT_NVLOG_RM = 0x800, + NVDUMP_COMPONENT_NVLOG_ALL, + // Reserved + NVDUMP_COMPONENT_NVLOG_RESERVED = 0xB00, +} NVDUMP_COMPONENT; + +#define NVDUMP_IS_GPU_COMPONENT(c) ((c) < NVDUMP_COMPONENT_SYS_RCDB) +#define NVDUMP_IS_SYS_COMPONENT(c) (((c) >= NVDUMP_COMPONENT_SYS_RCDB) && \ + ((c) < NVDUMP_COMPONENT_NVLOG_RM)) +#define NVDUMP_IS_NVLOG_COMPONENT(c) (((c) >= NVDUMP_COMPONENT_NVLOG_RM) && \ + ((c) < NVDUMP_COMPONENT_NVLOG_RESERVED)) + +typedef enum +{ + NVDUMP_BUFFER_PROVIDED = 0, // Dump buffer provided by caller + NVDUMP_BUFFER_ALLOCATE, // Dump buffer to be allocated + NVDUMP_BUFFER_COUNT, // Just count, no buffer needed +} NVDUMP_BUFFER_POLICY; + +typedef enum +{ + NVDUMP_STATUS_IDLE, + NVDUMP_STATUS_ERROR, + NVDUMP_STATUS_COUNT_REQUESTED, + NVDUMP_STATUS_COUNT_COMPLETE, + NVDUMP_STATUS_DUMP_REQUESTED, + NVDUMP_STATUS_DUMP_BUFFER_FULL, + NVDUMP_STATUS_DUMP_END_OF_MSG, + NVDUMP_STATUS_DUMP_COMPLETE, +} NVDUMP_STATUS; + +// +// The following structures require that all elements are precisely sized +// and aligned on natural boundaries. +// + +typedef struct +{ + NvP64 address NV_ALIGN_BYTES(8); + NvU32 size; + NvU32 curNumBytes; +} NVDUMP_BUFFER; + +// Max number of bytes that can be returned in a dump buffer +#define NVDUMP_MAX_DUMP_SIZE (1 << 20) // 1 MB + +typedef struct +{ + NvU8 sigHead[sizeof(NVDUMP_CONFIG_SIGNATURE)] NV_ALIGN_BYTES(8); + + NvP64 debuggerControlFuncAddr NV_ALIGN_BYTES(8); + NVDUMP_BUFFER buffer; + NvU32 gpuSelect; + NvU32 component; + NvU32 dumpStatus; + NvU32 rmStatus; + + NvU8 sigTail[sizeof(NVDUMP_CONFIG_SIGNATURE)] NV_ALIGN_BYTES(8); +} NVDUMP_CONFIG; + +typedef struct +{ + NvU16 length; + NvU16 start; + NvU16 end; + NvU16 flags; + NvU16 tag; +} NVDUMP_SUB_ALLOC_HEADER; + +// +// Export is needed to allow remote kernel debuggers without symbols +// to find global NVDUMP_CONFIG variables in driver export address table. +// +#define NVDUMP_EXPORT + +#endif // _NVDUMP_H_ + diff --git a/userspace/sdks/nv570/nvidia/inc/nverror.h b/userspace/sdks/nv570/nvidia/inc/nverror.h new file mode 100644 index 0000000..a7fef7d --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/nverror.h @@ -0,0 +1,224 @@ +/* + * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVERROR_H +#define NVERROR_H +/****************************************************************************** +* +* File: nverror.h +* +* Description: +* This file contains the error codes set when the error notifier +* is signaled. +* +******************************************************************************/ + +#include "nvcfg_sdk.h" + +#define ROBUST_CHANNEL_GR_EXCEPTION (13) +#define ROBUST_CHANNEL_GR_ERROR_SW_NOTIFY (13) +#define ROBUST_CHANNEL_FAKE_ERROR (14) +#define ROBUST_CHANNEL_VBLANK_CALLBACK_TIMEOUT (16) +#define ROBUST_CHANNEL_DISP_MISSED_NOTIFIER (19) +#define ROBUST_CHANNEL_MPEG_ERROR_SW_METHOD (20) +#define ROBUST_CHANNEL_ME_ERROR_SW_METHOD (21) +#define ROBUST_CHANNEL_VP_ERROR_SW_METHOD (22) +#define ROBUST_CHANNEL_RC_LOGGING_ENABLED (23) +#define ROBUST_CHANNEL_VP_ERROR (27) +#define ROBUST_CHANNEL_VP2_ERROR (28) +#define ROBUST_CHANNEL_BSP_ERROR (29) +#define ROBUST_CHANNEL_BAD_ADDR_ACCESS (30) +#define ROBUST_CHANNEL_FIFO_ERROR_MMU_ERR_FLT (31) +#define ROBUST_CHANNEL_PBDMA_ERROR (32) +#define ROBUST_CHANNEL_SEC_ERROR (33) +#define ROBUST_CHANNEL_MSVLD_ERROR (34) +#define ROBUST_CHANNEL_MSPDEC_ERROR (35) +#define ROBUST_CHANNEL_MSPPP_ERROR (36) +#define ROBUST_CHANNEL_CE0_ERROR (39) +#define ROBUST_CHANNEL_CE1_ERROR (40) +#define ROBUST_CHANNEL_CE2_ERROR (41) +#define ROBUST_CHANNEL_VIC_ERROR (42) +#define ROBUST_CHANNEL_RESETCHANNEL_VERIF_ERROR (43) +#define ROBUST_CHANNEL_GR_FAULT_DURING_CTXSW (44) +#define ROBUST_CHANNEL_PREEMPTIVE_REMOVAL (45) +#define ROBUST_CHANNEL_NVENC0_ERROR (47) +#define ROBUST_CHANNEL_GPU_ECC_DBE (48) +#define PMU_ERROR (59) +#define ROBUST_CHANNEL_SEC2_ERROR (60) +#define PMU_BREAKPOINT (61) +#define PMU_HALT_ERROR (62) +#define INFOROM_PAGE_RETIREMENT_EVENT (63) +#define INFOROM_PAGE_RETIREMENT_FAILURE (64) +#define INFOROM_DRAM_RETIREMENT_EVENT (63) +#define INFOROM_DRAM_RETIREMENT_FAILURE (64) +#define ROBUST_CHANNEL_NVENC1_ERROR (65) +#define ROBUST_CHANNEL_NVDEC0_ERROR (68) +#define ROBUST_CHANNEL_GR_CLASS_ERROR (69) +#define ROBUST_CHANNEL_CE3_ERROR (70) +#define ROBUST_CHANNEL_CE4_ERROR (71) +#define ROBUST_CHANNEL_CE5_ERROR (72) +#define ROBUST_CHANNEL_NVENC2_ERROR (73) +#define NVLINK_ERROR (74) +#define ROBUST_CHANNEL_CE6_ERROR (75) +#define ROBUST_CHANNEL_CE7_ERROR (76) +#define ROBUST_CHANNEL_CE8_ERROR (77) +#define VGPU_START_ERROR (78) +#define ROBUST_CHANNEL_GPU_HAS_FALLEN_OFF_THE_BUS (79) +#define PBDMA_PUSHBUFFER_CRC_MISMATCH (80) +#define ROBUST_CHANNEL_VGA_SUBSYSTEM_ERROR (81) +#define ROBUST_CHANNEL_NVJPG0_ERROR (82) +#define ROBUST_CHANNEL_NVDEC1_ERROR (83) +#define ROBUST_CHANNEL_NVDEC2_ERROR (84) +#define ROBUST_CHANNEL_CE9_ERROR (85) +#define ROBUST_CHANNEL_OFA0_ERROR (86) +#define NVTELEMETRY_DRIVER_REPORT (87) +#define ROBUST_CHANNEL_NVDEC3_ERROR (88) +#define ROBUST_CHANNEL_NVDEC4_ERROR (89) +#define LTC_ERROR (90) +#define RESERVED_XID (91) +#define EXCESSIVE_SBE_INTERRUPTS (92) +#define INFOROM_ERASE_LIMIT_EXCEEDED (93) +#define ROBUST_CHANNEL_CONTAINED_ERROR (94) +#define ROBUST_CHANNEL_UNCONTAINED_ERROR (95) +#define ROBUST_CHANNEL_NVDEC5_ERROR (96) +#define ROBUST_CHANNEL_NVDEC6_ERROR (97) +#define ROBUST_CHANNEL_NVDEC7_ERROR (98) +#define ROBUST_CHANNEL_NVJPG1_ERROR (99) +#define ROBUST_CHANNEL_NVJPG2_ERROR (100) +#define ROBUST_CHANNEL_NVJPG3_ERROR (101) +#define ROBUST_CHANNEL_NVJPG4_ERROR (102) +#define ROBUST_CHANNEL_NVJPG5_ERROR (103) +#define ROBUST_CHANNEL_NVJPG6_ERROR (104) +#define ROBUST_CHANNEL_NVJPG7_ERROR (105) +#define SEC_FAULT_ERROR (110) +#define GSP_RPC_TIMEOUT (119) +#define GSP_ERROR (120) +#define C2C_ERROR (121) +#define SPI_PMU_RPC_READ_FAIL (122) +#define SPI_PMU_RPC_WRITE_FAIL (123) +#define SPI_PMU_RPC_ERASE_FAIL (124) +#define INFOROM_FS_ERROR (125) +#define ALI_TRAINING_FAIL (136) +#define ROBUST_CHANNEL_LAST_ERROR (ALI_TRAINING_FAIL) + + + +// Indexed CE reference +#define ROBUST_CHANNEL_CE_ERROR(x) \ + ((x < 3) ? \ + (ROBUST_CHANNEL_CE0_ERROR + (x)) : \ + ((x < 6) ? \ + (ROBUST_CHANNEL_CE3_ERROR + (x - 3)) : \ + ((x < 9) ? \ + (ROBUST_CHANNEL_CE6_ERROR + (x - 6)) : \ + (ROBUST_CHANNEL_CE9_ERROR)))) + +#define ROBUST_CHANNEL_IS_CE_ERROR(x) \ + ((x == ROBUST_CHANNEL_CE0_ERROR) || (x == ROBUST_CHANNEL_CE1_ERROR) || \ + (x == ROBUST_CHANNEL_CE2_ERROR) || (x == ROBUST_CHANNEL_CE3_ERROR) || \ + (x == ROBUST_CHANNEL_CE4_ERROR) || (x == ROBUST_CHANNEL_CE5_ERROR) || \ + (x == ROBUST_CHANNEL_CE6_ERROR) || (x == ROBUST_CHANNEL_CE7_ERROR) || \ + (x == ROBUST_CHANNEL_CE8_ERROR) || (x == ROBUST_CHANNEL_CE9_ERROR)) + +#define ROBUST_CHANNEL_CE_ERROR_IDX(x) \ + (((x >= ROBUST_CHANNEL_CE0_ERROR) && (x <= ROBUST_CHANNEL_CE2_ERROR)) ? \ + (x - ROBUST_CHANNEL_CE0_ERROR) : \ + (((x >= ROBUST_CHANNEL_CE3_ERROR) && (x <= ROBUST_CHANNEL_CE5_ERROR)) ? \ + (x - ROBUST_CHANNEL_CE3_ERROR + 3) : \ + (((x >= ROBUST_CHANNEL_CE6_ERROR) && (x <= ROBUST_CHANNEL_CE8_ERROR)) ? \ + (x - ROBUST_CHANNEL_CE6_ERROR + 6) : \ + (x - ROBUST_CHANNEL_CE9_ERROR + 9)))) + +// Indexed NVDEC reference +#define ROBUST_CHANNEL_NVDEC_ERROR(x) \ + ((x < 1) ? \ + (ROBUST_CHANNEL_NVDEC0_ERROR) : \ + ((x < 3) ? \ + (ROBUST_CHANNEL_NVDEC1_ERROR + (x - 1)) : \ + ((x < 5) ? \ + (ROBUST_CHANNEL_NVDEC3_ERROR + (x - 3)): \ + (ROBUST_CHANNEL_NVDEC5_ERROR + (x - 5))))) + +#define ROBUST_CHANNEL_IS_NVDEC_ERROR(x) \ + ((x == ROBUST_CHANNEL_NVDEC0_ERROR) || \ + (x == ROBUST_CHANNEL_NVDEC1_ERROR) || \ + (x == ROBUST_CHANNEL_NVDEC2_ERROR) || \ + (x == ROBUST_CHANNEL_NVDEC3_ERROR) || \ + (x == ROBUST_CHANNEL_NVDEC4_ERROR) || \ + (x == ROBUST_CHANNEL_NVDEC5_ERROR) || \ + (x == ROBUST_CHANNEL_NVDEC6_ERROR) || \ + (x == ROBUST_CHANNEL_NVDEC7_ERROR)) + +#define ROBUST_CHANNEL_NVDEC_ERROR_IDX(x) \ + ((x == ROBUST_CHANNEL_NVDEC0_ERROR) ? \ + (x - ROBUST_CHANNEL_NVDEC0_ERROR) : \ + (((x >= ROBUST_CHANNEL_NVDEC1_ERROR) && (x <= ROBUST_CHANNEL_NVDEC2_ERROR)) ? \ + (x - ROBUST_CHANNEL_NVDEC1_ERROR + 1) : \ + (((x >= ROBUST_CHANNEL_NVDEC3_ERROR) && (x <= ROBUST_CHANNEL_NVDEC4_ERROR)) ? \ + (x - ROBUST_CHANNEL_NVDEC3_ERROR + 3) : \ + (x - ROBUST_CHANNEL_NVDEC5_ERROR + 5)))) + +// Indexed NVENC reference +#define ROBUST_CHANNEL_NVENC_ERROR(x) \ + ((x == 0) ? (ROBUST_CHANNEL_NVENC0_ERROR) : \ + ((x == 1) ? (ROBUST_CHANNEL_NVENC1_ERROR) : \ + (ROBUST_CHANNEL_NVENC2_ERROR))) + +#define ROBUST_CHANNEL_IS_NVENC_ERROR(x) \ + ((x == ROBUST_CHANNEL_NVENC0_ERROR) || \ + (x == ROBUST_CHANNEL_NVENC1_ERROR) || \ + (x == ROBUST_CHANNEL_NVENC2_ERROR)) + +#define ROBUST_CHANNEL_NVENC_ERROR_IDX(x) \ + (((x == ROBUST_CHANNEL_NVENC0_ERROR)) ? \ + (x - ROBUST_CHANNEL_NVENC0_ERROR) : \ + (((x == ROBUST_CHANNEL_NVENC1_ERROR)) ? \ + (x - ROBUST_CHANNEL_NVENC1_ERROR + 1) : \ + (x - ROBUST_CHANNEL_NVENC2_ERROR + 2))) + +// Indexed NVJPG reference +#define ROBUST_CHANNEL_NVJPG_ERROR(x) \ + ((x < 1) ? \ + (ROBUST_CHANNEL_NVJPG0_ERROR) : \ + (ROBUST_CHANNEL_NVJPG1_ERROR + (x - 1))) + +#define ROBUST_CHANNEL_IS_NVJPG_ERROR(x) \ + ((x == ROBUST_CHANNEL_NVJPG0_ERROR) || \ + (x == ROBUST_CHANNEL_NVJPG1_ERROR) || \ + (x == ROBUST_CHANNEL_NVJPG2_ERROR) || \ + (x == ROBUST_CHANNEL_NVJPG3_ERROR) || \ + (x == ROBUST_CHANNEL_NVJPG4_ERROR) || \ + (x == ROBUST_CHANNEL_NVJPG5_ERROR) || \ + (x == ROBUST_CHANNEL_NVJPG6_ERROR) || \ + (x == ROBUST_CHANNEL_NVJPG7_ERROR)) + +#define ROBUST_CHANNEL_NVJPG_ERROR_IDX(x) \ + ((x == ROBUST_CHANNEL_NVJPG0_ERROR) ? \ + (x - ROBUST_CHANNEL_NVJPG0_ERROR) : \ + (x - ROBUST_CHANNEL_NVJPG1_ERROR + 1)) + +// Error Levels +#define ROBUST_CHANNEL_ERROR_RECOVERY_LEVEL_INFO (0) +#define ROBUST_CHANNEL_ERROR_RECOVERY_LEVEL_NON_FATAL (1) +#define ROBUST_CHANNEL_ERROR_RECOVERY_LEVEL_FATAL (2) + +#endif // NVERROR_H diff --git a/userspace/sdks/nv570/nvidia/inc/nvfixedtypes.h b/userspace/sdks/nv570/nvidia/inc/nvfixedtypes.h new file mode 100644 index 0000000..73c7923 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/nvfixedtypes.h @@ -0,0 +1,379 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVFIXEDTYPES_INCLUDED +#define NVFIXEDTYPES_INCLUDED + +#include "nvtypes.h" + +/*! + * Fixed-point master data types. + * + * These are master-types represent the total number of bits contained within + * the FXP type. All FXP types below should be based on one of these master + * types. + */ +typedef NvS16 NvSFXP16; +typedef NvS32 NvSFXP32; +typedef NvS64 NvSFXP64; +typedef NvU16 NvUFXP16; +typedef NvU32 NvUFXP32; +typedef NvU64 NvUFXP64; + + +/*! + * Fixed-point data types. + * + * These are all integer types with precision indicated in the naming of the + * form: NvFXP_. The actual + * size of the data type is calculated as num_bits_above_radix + + * num_bit_below_radix. + * + * All of these FXP types should be based on one of the master types above. + */ +typedef NvSFXP16 NvSFXP11_5; +typedef NvSFXP16 NvSFXP4_12; +typedef NvSFXP16 NvSFXP8_8; +typedef NvSFXP32 NvSFXP8_24; +typedef NvSFXP32 NvSFXP10_22; +typedef NvSFXP32 NvSFXP16_16; +typedef NvSFXP32 NvSFXP18_14; +typedef NvSFXP32 NvSFXP20_12; +typedef NvSFXP32 NvSFXP24_8; +typedef NvSFXP32 NvSFXP27_5; +typedef NvSFXP32 NvSFXP28_4; +typedef NvSFXP32 NvSFXP29_3; +typedef NvSFXP32 NvSFXP31_1; +typedef NvSFXP64 NvSFXP52_12; + +typedef NvUFXP16 NvUFXP0_16; +typedef NvUFXP16 NvUFXP4_12; +typedef NvUFXP16 NvUFXP8_8; +typedef NvUFXP32 NvUFXP3_29; +typedef NvUFXP32 NvUFXP4_28; +typedef NvUFXP32 NvUFXP7_25; +typedef NvUFXP32 NvUFXP8_24; +typedef NvUFXP32 NvUFXP9_23; +typedef NvUFXP32 NvUFXP10_22; +typedef NvUFXP32 NvUFXP15_17; +typedef NvUFXP32 NvUFXP16_16; +typedef NvUFXP32 NvUFXP18_14; +typedef NvUFXP32 NvUFXP20_12; +typedef NvUFXP32 NvUFXP24_8; +typedef NvUFXP32 NvUFXP25_7; +typedef NvUFXP32 NvUFXP26_6; +typedef NvUFXP32 NvUFXP28_4; + +typedef NvUFXP64 NvUFXP40_24; +typedef NvUFXP64 NvUFXP48_16; +typedef NvUFXP64 NvUFXP52_12; + +/*! + * Utility macros used in converting between signed integers and fixed-point + * notation. + * + * - COMMON - These are used by both signed and unsigned. + */ +#define NV_TYPES_FXP_INTEGER(x, y) ((x)+(y)-1):(y) +#define NV_TYPES_FXP_FRACTIONAL(x, y) ((y)-1):0 +#define NV_TYPES_FXP_FRACTIONAL_MSB(x, y) ((y)-1):((y)-1) +#define NV_TYPES_FXP_FRACTIONAL_MSB_ONE 0x00000001 +#define NV_TYPES_FXP_FRACTIONAL_MSB_ZERO 0x00000000 +#define NV_TYPES_FXP_ZERO (0) + +/*! + * - UNSIGNED - These are only used for unsigned. + */ +#define NV_TYPES_UFXP_INTEGER_MAX(x, y) (~(NVBIT((y))-1U)) +#define NV_TYPES_UFXP_INTEGER_MIN(x, y) (0U) + +/*! + * - SIGNED - These are only used for signed. + */ +#define NV_TYPES_SFXP_INTEGER_SIGN(x, y) ((x)+(y)-1):((x)+(y)-1) +#define NV_TYPES_SFXP_INTEGER_SIGN_NEGATIVE 0x00000001 +#define NV_TYPES_SFXP_INTEGER_SIGN_POSITIVE 0x00000000 +#define NV_TYPES_SFXP_S32_SIGN_EXTENSION(x, y) 31:(x) +#define NV_TYPES_SFXP_S32_SIGN_EXTENSION_POSITIVE(x, y) 0x00000000 +#define NV_TYPES_SFXP_S32_SIGN_EXTENSION_NEGATIVE(x, y) (NVBIT(32-(x))-1U) +#define NV_TYPES_SFXP_INTEGER_MAX(x, y) (NVBIT((x))-1U) +#define NV_TYPES_SFXP_INTEGER_MIN(x, y) (~(NVBIT((x))-1U)) +#define NV_TYPES_SFXP_S64_SIGN_EXTENSION(x, y) 63:(x) +#define NV_TYPES_SFXP_S64_SIGN_EXTENSION_POSITIVE(x, y) 0x0000000000000000 +#define NV_TYPES_SFXP_S64_SIGN_EXTENSION_NEGATIVE(x, y) (NVBIT64(64-(x))-1U) +#define NV_TYPES_SFXP_S64_INTEGER_MAX(x, y) (NVBIT64((x)-1)-1U) +#define NV_TYPES_SFXP_S64_INTEGER_MIN(x, y) (~(NVBIT64((x)-1)-1U)) + +/*! + * Conversion macros used for converting between integer and fixed point + * representations. Both signed and unsigned variants. + * + * Warning: + * Note that most of the macros below can overflow if applied on values that can + * not fit the destination type. It's caller responsibility to ensure that such + * situations will not occur. + * + * Some conversions perform some commonly performed tasks other than just + * bit-shifting: + * + * - _SCALED: + * For integer -> fixed-point we add handling divisors to represent + * non-integer values. + * + * - _ROUNDED: + * For fixed-point -> integer we add rounding to integer values. + */ + +// 32-bit Unsigned FXP: +#define NV_TYPES_U32_TO_UFXP_X_Y(x, y, integer) \ + ((NvUFXP##x##_##y) (((NvU32) (integer)) << \ + DRF_SHIFT(NV_TYPES_FXP_INTEGER((x), (y))))) + +#define NV_TYPES_U32_TO_UFXP_X_Y_SCALED(x, y, integer, scale) \ + ((NvUFXP##x##_##y) ((((((NvU32) (integer)) << \ + DRF_SHIFT(NV_TYPES_FXP_INTEGER((x), (y))))) / \ + (scale)) + \ + ((((((NvU32) (integer)) << \ + DRF_SHIFT(NV_TYPES_FXP_INTEGER((x), (y)))) % \ + (scale)) > ((scale) >> 1)) ? 1U : 0U))) + +#define NV_TYPES_UFXP_X_Y_TO_U32(x, y, fxp) \ + ((NvU32) (DRF_VAL(_TYPES, _FXP, _INTEGER((x), (y)), \ + ((NvUFXP##x##_##y) (fxp))))) + +#define NV_TYPES_UFXP_X_Y_TO_U32_ROUNDED(x, y, fxp) \ + (NV_TYPES_UFXP_X_Y_TO_U32(x, y, (fxp)) + \ + (FLD_TEST_DRF_NUM(_TYPES, _FXP, _FRACTIONAL_MSB((x), (y)), \ + NV_TYPES_FXP_FRACTIONAL_MSB_ONE, ((NvUFXP##x##_##y) (fxp))) ? \ + 1U : 0U)) + +// 64-bit Unsigned FXP +#define NV_TYPES_U64_TO_UFXP_X_Y(x, y, integer) \ + ((NvUFXP##x##_##y) (((NvU64) (integer)) << \ + DRF_SHIFT64(NV_TYPES_FXP_INTEGER((x), (y))))) + +#define NV_TYPES_U64_TO_UFXP_X_Y_SCALED(x, y, integer, scale) \ + ((NvUFXP##x##_##y) (((((NvU64) (integer)) << \ + DRF_SHIFT64(NV_TYPES_FXP_INTEGER((x), (y)))) + \ + ((scale) >> 1)) / \ + (scale))) + +#define NV_TYPES_UFXP_X_Y_TO_U64(x, y, fxp) \ + ((NvU64) (DRF_VAL64(_TYPES, _FXP, _INTEGER((x), (y)), \ + ((NvUFXP##x##_##y) (fxp))))) + +#define NV_TYPES_UFXP_X_Y_TO_U64_ROUNDED(x, y, fxp) \ + (NV_TYPES_UFXP_X_Y_TO_U64(x, y, (fxp)) + \ + (FLD_TEST_DRF_NUM64(_TYPES, _FXP, _FRACTIONAL_MSB((x), (y)), \ + NV_TYPES_FXP_FRACTIONAL_MSB_ONE, ((NvUFXP##x##_##y) (fxp))) ? \ + 1U : 0U)) + +// +// 32-bit Signed FXP: +// Some compilers do not support left shift negative values +// so typecast integer to NvU32 instead of NvS32 +// +// Note that there is an issue with the rounding in +// NV_TYPES_S32_TO_SFXP_X_Y_SCALED. In particular, when the signs of the +// numerator and denominator don't match, the rounding is done towards positive +// infinity, rather than away from 0. This will need to be fixed in a follow-up +// change. +// +#define NV_TYPES_S32_TO_SFXP_X_Y(x, y, integer) \ + ((NvSFXP##x##_##y) (((NvU32) (integer)) << \ + DRF_SHIFT(NV_TYPES_FXP_INTEGER((x), (y))))) + +#define NV_TYPES_S32_TO_SFXP_X_Y_SCALED(x, y, integer, scale) \ + ((NvSFXP##x##_##y) (((((NvS32) (integer)) << \ + DRF_SHIFT(NV_TYPES_FXP_INTEGER((x), (y)))) + \ + ((scale) >> 1)) / \ + (scale))) + +#define NV_TYPES_SFXP_X_Y_TO_S32(x, y, fxp) \ + ((NvS32) ((DRF_VAL(_TYPES, _FXP, _INTEGER((x), (y)), \ + ((NvSFXP##x##_##y) (fxp)))) | \ + ((DRF_VAL(_TYPES, _SFXP, _INTEGER_SIGN((x), (y)), (fxp)) == \ + NV_TYPES_SFXP_INTEGER_SIGN_NEGATIVE) ? \ + DRF_NUM(_TYPES, _SFXP, _S32_SIGN_EXTENSION((x), (y)), \ + NV_TYPES_SFXP_S32_SIGN_EXTENSION_NEGATIVE((x), (y))) : \ + DRF_NUM(_TYPES, _SFXP, _S32_SIGN_EXTENSION((x), (y)), \ + NV_TYPES_SFXP_S32_SIGN_EXTENSION_POSITIVE((x), (y)))))) + +/*! + * Note: The rounding action for signed numbers should ideally round away from + * 0 in both the positive and the negative regions. + * For positive numbers, we add 1 if the fractional MSb is 1. + * For negative numbers, we add -1 (equivalent to subtracting 1) if the + * fractional MSb is 1. + */ +#define NV_TYPES_SFXP_X_Y_TO_S32_ROUNDED(x, y, fxp) \ + (NV_TYPES_SFXP_X_Y_TO_S32(x, y, (fxp)) + \ + (FLD_TEST_DRF_NUM(_TYPES, _FXP, _FRACTIONAL_MSB((x), (y)), \ + NV_TYPES_FXP_FRACTIONAL_MSB_ONE, ((NvSFXP##x##_##y) (fxp))) ? \ + ((DRF_VAL(_TYPES, _SFXP, _INTEGER_SIGN((x), (y)), (fxp)) == \ + NV_TYPES_SFXP_INTEGER_SIGN_POSITIVE) ? 1 : -1) : 0)) + +#define NV_TYPES_SFXP_X_Y_TO_FLOAT32(x, y, fxp) \ + ((NvF32) NV_TYPES_SFXP_X_Y_TO_S32(x, y, (fxp)) + \ + ((NvF32) DRF_NUM(_TYPES, _FXP, _FRACTIONAL((x), (y)), \ + ((NvSFXP##x##_##y) (fxp))) / (NvF32) (1 << (y)))) + +// +// 64-bit Signed FXP: +// Some compilers do not support left shift negative values +// so typecast integer to NvU64 instead of NvS64 +// +// Note that there is an issue with the rounding in +// NV_TYPES_S64_TO_SFXP_X_Y_SCALED. In particular, when the signs of the +// numerator and denominator don't match, the rounding is done towards positive +// infinity, rather than away from 0. This will need to be fixed in a follow-up +// change. +// +#define NV_TYPES_S64_TO_SFXP_X_Y(x, y, integer) \ + ((NvSFXP##x##_##y) (((NvU64) (integer)) << \ + DRF_SHIFT64(NV_TYPES_FXP_INTEGER((x), (y))))) + +#define NV_TYPES_S64_TO_SFXP_X_Y_SCALED(x, y, integer, scale) \ + ((NvSFXP##x##_##y) (((((NvS64) (integer)) << \ + DRF_SHIFT64(NV_TYPES_FXP_INTEGER((x), (y)))) + \ + ((scale) >> 1)) / \ + (scale))) + +#define NV_TYPES_SFXP_X_Y_TO_S64(x, y, fxp) \ + ((NvS64) ((DRF_VAL64(_TYPES, _FXP, _INTEGER((x), (y)), \ + ((NvSFXP##x##_##y) (fxp)))) | \ + ((DRF_VAL64(_TYPES, _SFXP, _INTEGER_SIGN((x), (y)), (fxp)) == \ + NV_TYPES_SFXP_INTEGER_SIGN_NEGATIVE) ? \ + DRF_NUM64(_TYPES, _SFXP, _S64_SIGN_EXTENSION((x), (y)), \ + NV_TYPES_SFXP_S64_SIGN_EXTENSION_NEGATIVE((x), (y))) : \ + DRF_NUM64(_TYPES, _SFXP, _S64_SIGN_EXTENSION((x), (y)), \ + NV_TYPES_SFXP_S64_SIGN_EXTENSION_POSITIVE((x), (y)))))) + +/*! + * Note: The rounding action for signed numbers should ideally round away from + * 0 in both the positive and the negative regions. + * For positive numbers, we add 1 if the fractional MSb is 1. + * For negative numbers, we add -1 (equivalent to subtracting 1) if the + * fractional MSb is 1. + */ +#define NV_TYPES_SFXP_X_Y_TO_S64_ROUNDED(x, y, fxp) \ + (NV_TYPES_SFXP_X_Y_TO_S64(x, y, (fxp)) + \ + (FLD_TEST_DRF_NUM64(_TYPES, _FXP, _FRACTIONAL_MSB((x), (y)), \ + NV_TYPES_FXP_FRACTIONAL_MSB_ONE, ((NvSFXP##x##_##y) (fxp))) ? \ + ((DRF_VAL64(_TYPES, _SFXP, _INTEGER_SIGN((x), (y)), (fxp)) == \ + NV_TYPES_SFXP_INTEGER_SIGN_POSITIVE) ? 1 : -1) : 0)) + +/*! + * Macros representing the single-precision IEEE 754 floating point format for + * "binary32", also known as "single" and "float". + * + * Single precision floating point format wiki [1] + * + * _SIGN + * Single bit representing the sign of the number. + * _EXPONENT + * Unsigned 8-bit number representing the exponent value by which to scale + * the mantissa. + * _BIAS - The value by which to offset the exponent to account for sign. + * _MANTISSA + * Explicit 23-bit significand of the value. When exponent != 0, this is an + * implicitly 24-bit number with a leading 1 prepended. This 24-bit number + * can be conceptualized as FXP 9.23. + * + * With these definitions, the value of a floating point number can be + * calculated as: + * (-1)^(_SIGN) * + * 2^(_EXPONENT - _EXPONENT_BIAS) * + * (1 + _MANTISSA / (1 << 23)) + */ +// [1] : https://en.wikipedia.org/wiki/Single_precision_floating-point_format +#define NV_TYPES_SINGLE_SIGN 31:31 +#define NV_TYPES_SINGLE_SIGN_POSITIVE 0x00000000 +#define NV_TYPES_SINGLE_SIGN_NEGATIVE 0x00000001 +#define NV_TYPES_SINGLE_EXPONENT 30:23 +#define NV_TYPES_SINGLE_EXPONENT_ZERO 0x00000000 +#define NV_TYPES_SINGLE_EXPONENT_BIAS 0x0000007F +#define NV_TYPES_SINGLE_MANTISSA 22:0 + + +/*! + * Helper macro to return a IEEE 754 single-precision value's mantissa as an + * unsigned FXP 9.23 value. + * + * @param[in] single IEEE 754 single-precision value to manipulate. + * + * @return IEEE 754 single-precision values mantissa represented as an unsigned + * FXP 9.23 value. + */ +#define NV_TYPES_SINGLE_MANTISSA_TO_UFXP9_23(single) \ + ((NvUFXP9_23)(FLD_TEST_DRF(_TYPES, _SINGLE, _EXPONENT, _ZERO, single) ? \ + NV_TYPES_U32_TO_UFXP_X_Y(9, 23, 0) : \ + (NV_TYPES_U32_TO_UFXP_X_Y(9, 23, 1) + \ + DRF_VAL(_TYPES, _SINGLE, _MANTISSA, single)))) + +/*! + * Helper macro to return an IEEE 754 single-precision value's exponent, + * including the bias. + * + * @param[in] single IEEE 754 single-precision value to manipulate. + * + * @return Signed exponent value for IEEE 754 single-precision. + */ +#define NV_TYPES_SINGLE_EXPONENT_BIASED(single) \ + ((NvS32)(DRF_VAL(_TYPES, _SINGLE, _EXPONENT, single) - \ + NV_TYPES_SINGLE_EXPONENT_BIAS)) + +/*! + * NvTemp - temperature data type introduced to avoid bugs in conversion between + * various existing notations. + */ +typedef NvSFXP24_8 NvTemp; + +/*! + * Macros for NvType <-> Celsius temperature conversion. + */ +#define NV_TYPES_CELSIUS_TO_NV_TEMP(cel) \ + NV_TYPES_S32_TO_SFXP_X_Y(24,8,(cel)) +#define NV_TYPES_NV_TEMP_TO_CELSIUS_TRUNCED(nvt) \ + NV_TYPES_SFXP_X_Y_TO_S32(24,8,(nvt)) +#define NV_TYPES_NV_TEMP_TO_CELSIUS_ROUNDED(nvt) \ + NV_TYPES_SFXP_X_Y_TO_S32_ROUNDED(24,8,(nvt)) +#define NV_TYPES_NV_TEMP_TO_CELSIUS_FLOAT(nvt) \ + NV_TYPES_SFXP_X_Y_TO_FLOAT32(24,8,(nvt)) + +/*! + * Macro for NvType -> number of bits conversion + */ +#define NV_NBITS_IN_TYPE(type) (8 * sizeof(type)) + +/*! + * Macro to convert SFXP 11.5 to NvTemp. + */ +#define NV_TYPES_NVSFXP11_5_TO_NV_TEMP(x) ((NvTemp)(x) << 3) + +/*! + * Macro to convert UFXP11.5 Watts to NvU32 milli-Watts. + */ +#define NV_TYPES_NVUFXP11_5_WATTS_TO_NVU32_MILLI_WATTS(x) ((((NvU32)(x)) * ((NvU32)1000)) >> 5) + +#endif /* NVFIXEDTYPES_INCLUDED */ diff --git a/userspace/sdks/nv570/nvidia/inc/nvgputypes.h b/userspace/sdks/nv570/nvidia/inc/nvgputypes.h new file mode 100644 index 0000000..d018414 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/nvgputypes.h @@ -0,0 +1,177 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2006 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + + /***************************************************************************\ +|* *| +|* NV GPU Types *| +|* *| +|* This header contains definitions describing NVIDIA's GPU hardware state. *| +|* *| + \***************************************************************************/ + + +#ifndef NVGPUTYPES_INCLUDED +#define NVGPUTYPES_INCLUDED +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + + /***************************************************************************\ +|* NvNotification *| + \***************************************************************************/ + +/***** NvNotification Structure *****/ +/* + * NV objects return information about method completion to clients via an + * array of notification structures in main memory. + * + * The client sets the status field to NV???_NOTIFICATION_STATUS_IN_PROGRESS. + * NV fills in the NvNotification[] data structure in the following order: + * timeStamp, otherInfo32, otherInfo16, and then status. + */ + +/* memory data structures */ +typedef volatile struct NvNotificationRec { + struct { /* 0000- */ + NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/ + } timeStamp; /* -0007*/ + NvV32 info32; /* info returned depends on method 0008-000b*/ + NvV16 info16; /* info returned depends on method 000c-000d*/ + NvV16 status; /* user sets bit 15, NV sets status 000e-000f*/ +} NvNotification; + + /***************************************************************************\ +|* NvGpuSemaphore *| + \***************************************************************************/ + +/***** NvGpuSemaphore Structure *****/ +/* + * NvGpuSemaphore objects are used by the GPU to synchronize multiple + * command-streams. + * + * Please refer to class documentation for details regarding the content of + * the data[] field. + */ + +/* memory data structures */ +typedef volatile struct NvGpuSemaphoreRec { + NvV32 data[2]; /* Payload/Report data 0000-0007*/ + struct { /* 0008- */ + NvV32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 8- f*/ + } timeStamp; /* -000f*/ +} NvGpuSemaphore; + + /***************************************************************************\ +|* NvGetReport *| + \***************************************************************************/ + +/* + * NV objects, starting with Kelvin, return information such as pixel counts to + * the user via the NV*_GET_REPORT method. + * + * The client fills in the "zero" field to any nonzero value and waits until it + * becomes zero. NV fills in the timeStamp, value, and zero fields. + */ +typedef volatile struct NVGetReportRec { + struct { /* 0000- */ + NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/ + } timeStamp; /* -0007*/ + NvU32 value; /* info returned depends on method 0008-000b*/ + NvU32 zero; /* always written to zero 000c-000f*/ +} NvGetReport; + + /***************************************************************************\ +|* NvRcNotification *| + \***************************************************************************/ + +/* + * NV robust channel notification information is reported to clients via + * standard NV01_EVENT objects bound to instance of the NV*_CHANNEL_DMA and + * NV*_CHANNEL_GPFIFO objects. + */ +typedef struct NvRcNotificationRec { + struct { + NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/ + } timeStamp; /* -0007*/ + NvU32 exceptLevel; /* exception level 000c-000f*/ + NvU32 exceptType; /* exception type 0010-0013*/ +} NvRcNotification; + + /***************************************************************************\ +|* NvSyncPointFence *| + \***************************************************************************/ + +/***** NvSyncPointFence Structure *****/ +/* + * NvSyncPointFence objects represent a syncpoint event. The syncPointID + * identifies the syncpoint register and the value is the value that the + * register will contain right after the event occurs. + * + * If syncPointID contains NV_INVALID_SYNCPOINT_ID then this is an invalid + * event. This is often used to indicate an event in the past (i.e. no need to + * wait). + * + * For more info on syncpoints refer to Mobile channel and syncpoint + * documentation. + */ +typedef struct NvSyncPointFenceRec { + NvU32 syncPointID; + NvU32 value; +} NvSyncPointFence; + +#define NV_INVALID_SYNCPOINT_ID ((NvU32)-1) + + /***************************************************************************\ +|* *| +|* 64 bit type definitions for use in interface structures. *| +|* *| + \***************************************************************************/ + +typedef NvU64 NvOffset; /* GPU address */ + +#define NvOffset_HI32(n) ((NvU32)(((NvU64)(n)) >> 32)) +#define NvOffset_LO32(n) ((NvU32)((NvU64)(n))) + +/* +* There are two types of GPU-UUIDs available: +* +* (1) a SHA-256 based 32 byte ID, formatted as a 64 character +* hexadecimal string as "GPU-%16x-%08x-%08x-%08x-%024x"; this is +* deprecated. +* +* (2) a SHA-1 based 16 byte ID, formatted as a 32 character +* hexadecimal string as "GPU-%08x-%04x-%04x-%04x-%012x" (the +* canonical format of a UUID); this is the default. +*/ +#define NV_GPU_UUID_SHA1_LEN (16) +#define NV_GPU_UUID_SHA256_LEN (32) +#define NV_GPU_UUID_LEN NV_GPU_UUID_SHA1_LEN + +#ifdef __cplusplus +}; +#endif + +#endif /* NVGPUTYPES_INCLUDED */ diff --git a/userspace/sdks/nv570/nvidia/inc/nvi2c.h b/userspace/sdks/nv570/nvidia/inc/nvi2c.h new file mode 100644 index 0000000..28c1ba5 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/nvi2c.h @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef _NV_I2C_H_ +#define _NV_I2C_H_ + +#define NV_I2C_MSG_WR 0x0000 +#define NV_I2C_MSG_RD 0x0001 + +typedef struct nv_i2c_msg_s +{ + NvU16 addr; + NvU16 flags; + NvU16 len; + NvU8* buf; +} nv_i2c_msg_t; + +#endif diff --git a/userspace/sdks/nv570/nvidia/inc/nvimpshared.h b/userspace/sdks/nv570/nvidia/inc/nvimpshared.h new file mode 100644 index 0000000..eb4dc72 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/nvimpshared.h @@ -0,0 +1,98 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/******************************************************************************\ +* * +* Description: * +* Accommodates sharing of IMP-related structures between kernel interface * +* files and core RM. * +* * +\******************************************************************************/ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: nvimpshared.finn +// + + + + +// +// There are only a small number of discrete dramclk frequencies available on +// the system. This structure contains IMP-relevant information associated +// with a specific dramclk frequency. +// +typedef struct DRAM_CLK_INSTANCE { + NvU32 dram_clk_freq_khz; + + NvU32 mchub_clk_khz; + + NvU32 mc_clk_khz; + + NvU32 max_iso_bw_kbps; + + // + // switch_latency_ns is the maximum time required to switch the dramclk + // frequency to the frequency specified in dram_clk_freq_khz. + // + NvU32 switch_latency_ns; +} DRAM_CLK_INSTANCE; + +// +// This table is used to collect information from other modules that is needed +// for RM IMP calculations. (Used on Tegra only.) +// +#define TEGRA_IMP_IMPORT_DATA_DRAM_TYPE_UNKNOWN 0U +#define TEGRA_IMP_IMPORT_DATA_DRAM_TYPE_LPDDR4 1U +#define TEGRA_IMP_IMPORT_DATA_DRAM_TYPE_LPDDR5 2U + +typedef struct TEGRA_IMP_IMPORT_DATA { + // + // max_iso_bw_kbps stores the maximum possible ISO bandwidth available to + // display, assuming display is the only active ISO client. (Note that ISO + // bandwidth will typically be allocated to multiple clients, so display + // will generally not have access to the maximum possible bandwidth.) + // + NvU32 max_iso_bw_kbps; + + NvU32 dram_type; + // On Orin, each dram channel is 16 bits wide. + NvU32 num_dram_channels; + + // + // dram_clk_instance stores entries for all possible dramclk frequencies, + // sorted by dramclk frequency in increasing order. + // + // "24" is expected to be larger than the actual number of required entries + // (which is provided by a BPMP API), but it can be increased if necessary. + // + // num_dram_clk_entries is filled in with the actual number of distinct + // dramclk entries. + // + NvU32 num_dram_clk_entries; + DRAM_CLK_INSTANCE dram_clk_instance[24]; +} TEGRA_IMP_IMPORT_DATA; diff --git a/userspace/sdks/nv570/nvidia/inc/nvlimits.h b/userspace/sdks/nv570/nvidia/inc/nvlimits.h new file mode 100644 index 0000000..a896adf --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/nvlimits.h @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: nvlimits.finn +// + + + + +/* + * This is the maximum number of GPUs supported in a single system. + */ +#define NV_MAX_DEVICES 32 + +/* + * This is the maximum number of subdevices within a single device. + */ +#define NV_MAX_SUBDEVICES 8 + +/* + * This is the maximum length of the process name string. + */ +#define NV_PROC_NAME_MAX_LENGTH 100U + +/* + * This is the maximum number of heads per GPU. + */ +#define NV_MAX_HEADS 4 diff --git a/userspace/sdks/nv570/nvidia/inc/nvmisc.h b/userspace/sdks/nv570/nvidia/inc/nvmisc.h new file mode 100644 index 0000000..fa33a9f --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/nvmisc.h @@ -0,0 +1,927 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * nvmisc.h + */ +#ifndef __NV_MISC_H +#define __NV_MISC_H + +#ifdef __cplusplus +extern "C" { +#endif //__cplusplus + +#include "nvtypes.h" + +#if !defined(NVIDIA_UNDEF_LEGACY_BIT_MACROS) +// +// Miscellaneous macros useful for bit field manipulations +// +// STUPID HACK FOR CL 19434692. Will revert when fix CL is delivered bfm -> chips_a. +#ifndef BIT +#define BIT(b) (1U<<(b)) +#endif +#ifndef BIT32 +#define BIT32(b) ((NvU32)1U<<(b)) +#endif +#ifndef BIT64 +#define BIT64(b) ((NvU64)1U<<(b)) +#endif + +#endif + +// +// It is recommended to use the following bit macros to avoid macro name +// collisions with other src code bases. +// +#ifndef NVBIT +#define NVBIT(b) (1U<<(b)) +#endif +#ifndef NVBIT_TYPE +#define NVBIT_TYPE(b, t) (((t)1U)<<(b)) +#endif +#ifndef NVBIT32 +#define NVBIT32(b) NVBIT_TYPE(b, NvU32) +#endif +#ifndef NVBIT64 +#define NVBIT64(b) NVBIT_TYPE(b, NvU64) +#endif + +// Helper macro's for 32 bit bitmasks +#define NV_BITMASK32_ELEMENT_SIZE (sizeof(NvU32) << 3) +#define NV_BITMASK32_IDX(chId) (((chId) & ~(0x1F)) >> 5) +#define NV_BITMASK32_OFFSET(chId) ((chId) & (0x1F)) +#define NV_BITMASK32_SET(pChannelMask, chId) \ + (pChannelMask)[NV_BITMASK32_IDX(chId)] |= NVBIT(NV_BITMASK32_OFFSET(chId)) +#define NV_BITMASK32_GET(pChannelMask, chId) \ + ((pChannelMask)[NV_BITMASK32_IDX(chId)] & NVBIT(NV_BITMASK32_OFFSET(chId))) + + +// Index of the 'on' bit (assuming that there is only one). +// Even if multiple bits are 'on', result is in range of 0-31. +#define BIT_IDX_32(n) \ + (((((n) & 0xFFFF0000U) != 0U) ? 0x10U: 0U) | \ + ((((n) & 0xFF00FF00U) != 0U) ? 0x08U: 0U) | \ + ((((n) & 0xF0F0F0F0U) != 0U) ? 0x04U: 0U) | \ + ((((n) & 0xCCCCCCCCU) != 0U) ? 0x02U: 0U) | \ + ((((n) & 0xAAAAAAAAU) != 0U) ? 0x01U: 0U) ) + +// Index of the 'on' bit (assuming that there is only one). +// Even if multiple bits are 'on', result is in range of 0-63. +#define BIT_IDX_64(n) \ + (((((n) & 0xFFFFFFFF00000000ULL) != 0U) ? 0x20U: 0U) | \ + ((((n) & 0xFFFF0000FFFF0000ULL) != 0U) ? 0x10U: 0U) | \ + ((((n) & 0xFF00FF00FF00FF00ULL) != 0U) ? 0x08U: 0U) | \ + ((((n) & 0xF0F0F0F0F0F0F0F0ULL) != 0U) ? 0x04U: 0U) | \ + ((((n) & 0xCCCCCCCCCCCCCCCCULL) != 0U) ? 0x02U: 0U) | \ + ((((n) & 0xAAAAAAAAAAAAAAAAULL) != 0U) ? 0x01U: 0U) ) + +/*! + * DRF MACRO README: + * + * Glossary: + * DRF: Device, Register, Field + * FLD: Field + * REF: Reference + * + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA 0xDEADBEEF + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_GAMMA 27:0 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA 31:28 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_ZERO 0x00000000 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_ONE 0x00000001 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_TWO 0x00000002 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_THREE 0x00000003 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_FOUR 0x00000004 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_FIVE 0x00000005 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_SIX 0x00000006 + * #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_SEVEN 0x00000007 + * + * + * Device = _DEVICE_OMEGA + * This is the common "base" that a group of registers in a manual share + * + * Register = _REGISTER_ALPHA + * Register for a given block of defines is the common root for one or more fields and constants + * + * Field(s) = _FIELD_GAMMA, _FIELD_ZETA + * These are the bit ranges for a given field within the register + * Fields are not required to have defined constant values (enumerations) + * + * Constant(s) = _ZERO, _ONE, _TWO, ... + * These are named values (enums) a field can contain; the width of the constants should not be larger than the field width + * + * MACROS: + * + * DRF_SHIFT: + * Bit index of the lower bound of a field + * DRF_SHIFT(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 28 + * + * DRF_SHIFT_RT: + * Bit index of the higher bound of a field + * DRF_SHIFT_RT(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 31 + * + * DRF_MASK: + * Produces a mask of 1-s equal to the width of a field + * DRF_MASK(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 0xF (four 1s starting at bit 0) + * + * DRF_SHIFTMASK: + * Produces a mask of 1s equal to the width of a field at the location of the field + * DRF_SHIFTMASK(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 0xF0000000 + * + * DRF_DEF: + * Shifts a field constant's value to the correct field offset + * DRF_DEF(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, _THREE) == 0x30000000 + * + * DRF_NUM: + * Shifts a number to the location of a particular field + * DRF_NUM(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, 3) == 0x30000000 + * NOTE: If the value passed in is wider than the field, the value's high bits will be truncated + * + * DRF_SIZE: + * Provides the width of the field in bits + * DRF_SIZE(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 4 + * + * DRF_VAL: + * Provides the value of an input within the field specified + * DRF_VAL(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, 0xABCD1234) == 0xA + * This is sort of like the inverse of DRF_NUM + * + * DRF_IDX...: + * These macros are similar to the above but for fields that accept an index argumment + * + * FLD_SET_DRF: + * Set the field bits in a given value with the given field constant + * NvU32 x = 0x00001234; + * x = FLD_SET_DRF(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, _THREE, x); + * x == 0x30001234; + * + * FLD_SET_DRF_NUM: + * Same as FLD_SET_DRF but instead of using a field constant a literal/variable is passed in + * NvU32 x = 0x00001234; + * x = FLD_SET_DRF_NUM(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, 0xF, x); + * x == 0xF0001234; + * + * FLD_IDX...: + * These macros are similar to the above but for fields that accept an index argumment + * + * FLD_TEST_DRF: + * Test if location specified by drf in 'v' has the same value as NV_drfc + * FLD_TEST_DRF(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, _THREE, 0x3000ABCD) == NV_TRUE + * + * FLD_TEST_DRF_NUM: + * Test if locations specified by drf in 'v' have the same value as n + * FLD_TEST_DRF_NUM(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, 0x3, 0x3000ABCD) == NV_TRUE + * + * REF_DEF: + * Like DRF_DEF but maintains full symbol name (use in cases where "NV" is not prefixed to the field) + * REF_DEF(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, _THREE) == 0x30000000 + * + * REF_VAL: + * Like DRF_VAL but maintains full symbol name (use in cases where "NV" is not prefixed to the field) + * REF_VAL(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, 0xABCD1234) == 0xA + * + * REF_NUM: + * Like DRF_NUM but maintains full symbol name (use in cases where "NV" is not prefixed to the field) + * REF_NUM(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, 0xA) == 0xA00000000 + * + * FLD_SET_REF_NUM: + * Like FLD_SET_DRF_NUM but maintains full symbol name (use in cases where "NV" is not prefixed to the field) + * NvU32 x = 0x00001234; + * x = FLD_SET_REF_NUM(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, 0xF, x); + * x == 0xF0001234; + * + * FLD_TEST_REF: + * Like FLD_TEST_DRF but maintains full symbol name (use in cases where "NV" is not prefixed to the field) + * FLD_TEST_REF(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, _THREE, 0x3000ABCD) == NV_TRUE + * + * Other macros: + * There a plethora of other macros below that extend the above (notably Multi-Word (MW), 64-bit, and some + * reg read/write variations). I hope these are self explanatory. If you have a need to use them, you + * probably have some knowledge of how they work. + */ + +// tegra mobile uses nvmisc_macros.h and can't access nvmisc.h... and sometimes both get included. +#ifndef _NVMISC_MACROS_H +// Use Coverity Annotation to mark issues as false positives/ignore when using single bit defines. +#define DRF_ISBIT(bitval,drf) \ + ( /* coverity[identical_branches] */ \ + (bitval != 0) ? drf ) +#define DEVICE_BASE(d) (0?d) // what's up with this name? totally non-parallel to the macros below +#define DEVICE_EXTENT(d) (1?d) // what's up with this name? totally non-parallel to the macros below +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +#ifdef MISRA_14_3 +#define DRF_BASE(drf) (drf##_LOW_FIELD) +#define DRF_EXTENT(drf) (drf##_HIGH_FIELD) +#define DRF_SHIFT(drf) ((drf##_LOW_FIELD) % 32U) +#define DRF_SHIFT_RT(drf) ((drf##_HIGH_FIELD) % 32U) +#define DRF_SIZE(drf) ((drf##_HIGH_FIELD)-(drf##_LOW_FIELD)+1U) +#define DRF_MASK(drf) (0xFFFFFFFFU >> (31U - ((drf##_HIGH_FIELD) % 32U) + ((drf##_LOW_FIELD) % 32U))) +#else +#define DRF_BASE(drf) (NV_FALSE?drf) // much better +#define DRF_EXTENT(drf) (NV_TRUE?drf) // much better +#define DRF_SHIFT(drf) (((NvU32)DRF_BASE(drf)) % 32U) +#define DRF_SHIFT_RT(drf) (((NvU32)DRF_EXTENT(drf)) % 32U) +#define DRF_SIZE(drf) (DRF_EXTENT(drf)-DRF_BASE(drf)+1U) +#define DRF_MASK(drf) (0xFFFFFFFFU>>(31U - DRF_SHIFT_RT(drf) + DRF_SHIFT(drf))) +#endif +#define DRF_DEF(d,r,f,c) (((NvU32)(NV ## d ## r ## f ## c))<>(31-((DRF_ISBIT(1,drf)) % 32)+((DRF_ISBIT(0,drf)) % 32))) +#define DRF_DEF(d,r,f,c) ((NV ## d ## r ## f ## c)<>DRF_SHIFT(NV ## d ## r ## f))&DRF_MASK(NV ## d ## r ## f)) +#endif + +// Signed version of DRF_VAL, which takes care of extending sign bit. +#define DRF_VAL_SIGNED(d,r,f,v) (((DRF_VAL(d,r,f,(v)) ^ (NVBIT(DRF_SIZE(NV ## d ## r ## f)-1U)))) - (NVBIT(DRF_SIZE(NV ## d ## r ## f)-1U))) +#define DRF_IDX_DEF(d,r,f,i,c) ((NV ## d ## r ## f ## c)<>DRF_SHIFT(NV##d##r##f(i)))&DRF_MASK(NV##d##r##f(i))) +#define DRF_IDX_OFFSET_VAL(d,r,f,i,o,v) (((v)>>DRF_SHIFT(NV##d##r##f(i,o)))&DRF_MASK(NV##d##r##f(i,o))) +// Fractional version of DRF_VAL which reads Fx.y fixed point number (x.y)*z +#define DRF_VAL_FRAC(d,r,x,y,v,z) ((DRF_VAL(d,r,x,(v))*z) + ((DRF_VAL(d,r,y,v)*z) / (1<>(63-((DRF_ISBIT(1,drf)) % 64)+((DRF_ISBIT(0,drf)) % 64))) +#define DRF_SHIFTMASK64(drf) (DRF_MASK64(drf)<<(DRF_SHIFT64(drf))) + +#define DRF_DEF64(d,r,f,c) (((NvU64)(NV ## d ## r ## f ## c))<>DRF_SHIFT64(NV ## d ## r ## f))&DRF_MASK64(NV ## d ## r ## f)) + +#define DRF_VAL_SIGNED64(d,r,f,v) (((DRF_VAL64(d,r,f,(v)) ^ (NVBIT64(DRF_SIZE(NV ## d ## r ## f)-1)))) - (NVBIT64(DRF_SIZE(NV ## d ## r ## f)-1))) +#define DRF_IDX_DEF64(d,r,f,i,c) (((NvU64)(NV ## d ## r ## f ## c))<>DRF_SHIFT64(NV##d##r##f(i)))&DRF_MASK64(NV##d##r##f(i))) +#define DRF_IDX_OFFSET_VAL64(d,r,f,i,o,v) (((NvU64)(v)>>DRF_SHIFT64(NV##d##r##f(i,o)))&DRF_MASK64(NV##d##r##f(i,o))) + +#define FLD_SET_DRF64(d,r,f,c,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f)) | DRF_DEF64(d,r,f,c)) +#define FLD_SET_DRF_NUM64(d,r,f,n,v) ((((NvU64)(v)) & ~DRF_SHIFTMASK64(NV##d##r##f)) | DRF_NUM64(d,r,f,n)) +#define FLD_IDX_SET_DRF64(d,r,f,i,c,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f(i))) | DRF_IDX_DEF64(d,r,f,i,c)) +#define FLD_IDX_OFFSET_SET_DRF64(d,r,f,i,o,c,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f(i,o))) | DRF_IDX_OFFSET_DEF64(d,r,f,i,o,c)) +#define FLD_IDX_SET_DRF_DEF64(d,r,f,i,c,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f(i))) | DRF_IDX_DEF64(d,r,f,i,c)) +#define FLD_IDX_SET_DRF_NUM64(d,r,f,i,n,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f(i))) | DRF_IDX_NUM64(d,r,f,i,n)) +#define FLD_SET_DRF_IDX64(d,r,f,c,i,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f)) | DRF_DEF64(d,r,f,c(i))) + +#define FLD_TEST_DRF64(d,r,f,c,v) (DRF_VAL64(d, r, f, (v)) == NV##d##r##f##c) +#define FLD_TEST_DRF_AND64(d,r,f,c,v) (DRF_VAL64(d, r, f, (v)) & NV##d##r##f##c) +#define FLD_TEST_DRF_NUM64(d,r,f,n,v) (DRF_VAL64(d, r, f, (v)) == (n)) +#define FLD_IDX_TEST_DRF64(d,r,f,i,c,v) (DRF_IDX_VAL64(d, r, f, i, (v)) == NV##d##r##f##c) +#define FLD_IDX_OFFSET_TEST_DRF64(d,r,f,i,o,c,v) (DRF_IDX_OFFSET_VAL64(d, r, f, i, o, (v)) == NV##d##r##f##c) + +#define REF_DEF64(drf,d) (((drf ## d)&DRF_MASK64(drf))<>DRF_SHIFT64(drf))&DRF_MASK64(drf)) +#if defined(NV_MISRA_COMPLIANCE_REQUIRED) && defined(MISRA_14_3) +#define REF_NUM64(drf,n) (((NvU64)(n)&(0xFFFFFFFFFFFFFFFFU>>(63U-((drf##_HIGH_FIELD) % 63U)+((drf##_LOW_FIELD) % 63U)))) << ((drf##_LOW_FIELD) % 63U)) +#else +#define REF_NUM64(drf,n) (((NvU64)(n)&DRF_MASK64(drf))<>DRF_SHIFT(drf))&DRF_MASK(drf)) +#if defined(NV_MISRA_COMPLIANCE_REQUIRED) && defined(MISRA_14_3) +#define REF_NUM(drf,n) (((n)&(0xFFFFFFFFU>>(31U-((drf##_HIGH_FIELD) % 32U)+((drf##_LOW_FIELD) % 32U)))) << ((drf##_LOW_FIELD) % 32U)) +#else +#define REF_NUM(drf,n) (((n)&DRF_MASK(drf))<>DRF_SHIFT(CR ## d ## r ## f))&DRF_MASK(CR ## d ## r ## f)) + +// Multi-word (MW) field manipulations. For multi-word structures (e.g., Fermi SPH), +// fields may have bit numbers beyond 32. To avoid errors using "classic" multi-word macros, +// all the field extents are defined as "MW(X)". For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. +// +// DRF_VAL_MW() macro is meant to be used for native endian 32-bit aligned 32-bit word data, +// not for byte stream data. +// +// DRF_VAL_BS() macro is for byte stream data used in fbQueryBIOS_XXX(). +// +#define DRF_EXPAND_MW(drf) drf // used to turn "MW(a:b)" into "a:b" +#define DRF_PICK_MW(drf,v) ((v)? DRF_EXPAND_##drf) // picks low or high bits +#define DRF_WORD_MW(drf) (DRF_PICK_MW(drf,0)/32) // which word in a multi-word array +#define DRF_BASE_MW(drf) (DRF_PICK_MW(drf,0)%32) // which start bit in the selected word? +#define DRF_EXTENT_MW(drf) (DRF_PICK_MW(drf,1)%32) // which end bit in the selected word +#define DRF_SHIFT_MW(drf) (DRF_PICK_MW(drf,0)%32) +#define DRF_MASK_MW(drf) (0xFFFFFFFFU>>((31-(DRF_EXTENT_MW(drf))+(DRF_BASE_MW(drf)))%32)) +#define DRF_SHIFTMASK_MW(drf) ((DRF_MASK_MW(drf))<<(DRF_SHIFT_MW(drf))) +#define DRF_SIZE_MW(drf) (DRF_EXTENT_MW(drf)-DRF_BASE_MW(drf)+1) + +#define DRF_DEF_MW(d,r,f,c) ((NV##d##r##f##c) << DRF_SHIFT_MW(NV##d##r##f)) +#define DRF_NUM_MW(d,r,f,n) (((n)&DRF_MASK_MW(NV##d##r##f))<>DRF_SHIFT_MW(NV##d##r##f))&DRF_MASK_MW(NV##d##r##f)) +#define DRF_SPANS(drf) ((DRF_PICK_MW(drf,0)/32) != (DRF_PICK_MW(drf,1)/32)) +#define DRF_WORD_MW_LOW(drf) (DRF_PICK_MW(drf,0)/32) +#define DRF_WORD_MW_HIGH(drf) (DRF_PICK_MW(drf,1)/32) +#define DRF_MASK_MW_LOW(drf) (0xFFFFFFFFU) +#define DRF_MASK_MW_HIGH(drf) (0xFFFFFFFFU>>(31-(DRF_EXTENT_MW(drf)))) +#define DRF_SHIFT_MW_LOW(drf) (DRF_PICK_MW(drf,0)%32) +#define DRF_SHIFT_MW_HIGH(drf) (0) +#define DRF_MERGE_SHIFT(drf) ((32-((DRF_PICK_MW(drf,0)%32)))%32) +#define DRF_VAL_MW_2WORD(d,r,f,v) (((((v)[DRF_WORD_MW_LOW(NV##d##r##f)])>>DRF_SHIFT_MW_LOW(NV##d##r##f))&DRF_MASK_MW_LOW(NV##d##r##f)) | \ + (((((v)[DRF_WORD_MW_HIGH(NV##d##r##f)])>>DRF_SHIFT_MW_HIGH(NV##d##r##f))&DRF_MASK_MW_HIGH(NV##d##r##f)) << DRF_MERGE_SHIFT(NV##d##r##f))) +#define DRF_VAL_MW(d,r,f,v) ( DRF_SPANS(NV##d##r##f) ? DRF_VAL_MW_2WORD(d,r,f,v) : DRF_VAL_MW_1WORD(d,r,f,v) ) + +#define DRF_IDX_DEF_MW(d,r,f,i,c) ((NV##d##r##f##c)<>DRF_SHIFT_MW(NV##d##r##f(i)))&DRF_MASK_MW(NV##d##r##f(i))) + +// +// Logically OR all DRF_DEF constants indexed from zero to s (semiinclusive). +// Caution: Target variable v must be pre-initialized. +// +#define FLD_IDX_OR_DRF_DEF(d,r,f,c,s,v) \ +do \ +{ NvU32 idx; \ + for (idx = 0; idx < (NV ## d ## r ## f ## s); ++idx)\ + { \ + v |= DRF_IDX_DEF(d,r,f,idx,c); \ + } \ +} while(0) + + +#define FLD_MERGE_MW(drf,n,v) (((v)[DRF_WORD_MW(drf)] & ~DRF_SHIFTMASK_MW(drf)) | n) +#define FLD_ASSIGN_MW(drf,n,v) ((v)[DRF_WORD_MW(drf)] = FLD_MERGE_MW(drf, n, v)) +#define FLD_IDX_MERGE_MW(drf,i,n,v) (((v)[DRF_WORD_MW(drf(i))] & ~DRF_SHIFTMASK_MW(drf(i))) | n) +#define FLD_IDX_ASSIGN_MW(drf,i,n,v) ((v)[DRF_WORD_MW(drf(i))] = FLD_MERGE_MW(drf(i), n, v)) + +#define FLD_SET_DRF_MW(d,r,f,c,v) FLD_MERGE_MW(NV##d##r##f, DRF_DEF_MW(d,r,f,c), v) +#define FLD_SET_DRF_NUM_MW(d,r,f,n,v) FLD_ASSIGN_MW(NV##d##r##f, DRF_NUM_MW(d,r,f,n), v) +#define FLD_SET_DRF_DEF_MW(d,r,f,c,v) FLD_ASSIGN_MW(NV##d##r##f, DRF_DEF_MW(d,r,f,c), v) +#define FLD_IDX_SET_DRF_MW(d,r,f,i,c,v) FLD_IDX_MERGE_MW(NV##d##r##f, i, DRF_IDX_DEF_MW(d,r,f,i,c), v) +#define FLD_IDX_SET_DRF_DEF_MW(d,r,f,i,c,v) FLD_IDX_MERGE_MW(NV##d##r##f, i, DRF_IDX_DEF_MW(d,r,f,i,c), v) +#define FLD_IDX_SET_DRF_NUM_MW(d,r,f,i,n,v) FLD_IDX_ASSIGN_MW(NV##d##r##f, i, DRF_IDX_NUM_MW(d,r,f,i,n), v) + +#define FLD_TEST_DRF_MW(d,r,f,c,v) ((DRF_VAL_MW(d, r, f, (v)) == NV##d##r##f##c)) +#define FLD_TEST_DRF_NUM_MW(d,r,f,n,v) ((DRF_VAL_MW(d, r, f, (v)) == n)) +#define FLD_IDX_TEST_DRF_MW(d,r,f,i,c,v) ((DRF_IDX_VAL_MW(d, r, f, i, (v)) == NV##d##r##f##c)) + +#define DRF_VAL_BS(d,r,f,v) ( DRF_SPANS(NV##d##r##f) ? DRF_VAL_BS_2WORD(d,r,f,(v)) : DRF_VAL_BS_1WORD(d,r,f,(v)) ) + +//------------------------------------------------------------------------// +// // +// Common defines for engine register reference wrappers // +// // +// New engine addressing can be created like: // +// \#define ENG_REG_PMC(o,d,r) NV##d##r // +// \#define ENG_IDX_REG_CE(o,d,i,r) CE_MAP(o,r,i) // +// // +// See FB_FBPA* for more examples // +//------------------------------------------------------------------------// + +#define ENG_RD_REG(g,o,d,r) GPU_REG_RD32(g, ENG_REG##d(o,d,r)) +#define ENG_WR_REG(g,o,d,r,v) GPU_REG_WR32(g, ENG_REG##d(o,d,r), (v)) +#define ENG_RD_DRF(g,o,d,r,f) ((GPU_REG_RD32(g, ENG_REG##d(o,d,r))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) +#define ENG_WR_DRF_DEF(g,o,d,r,f,c) GPU_REG_WR32(g, ENG_REG##d(o,d,r),(GPU_REG_RD32(g,ENG_REG##d(o,d,r))&~(GPU_DRF_MASK(NV##d##r##f)<>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) +#define ENG_TEST_IDX_DRF_DEF(g,o,d,r,f,c,i) (ENG_RD_IDX_DRF(g, o, d, r, f, (i)) == NV##d##r##f##c) + +#define ENG_IDX_RD_REG(g,o,d,i,r) GPU_REG_RD32(g, ENG_IDX_REG##d(o,d,i,r)) +#define ENG_IDX_WR_REG(g,o,d,i,r,v) GPU_REG_WR32(g, ENG_IDX_REG##d(o,d,i,r), (v)) + +#define ENG_IDX_RD_DRF(g,o,d,i,r,f) ((GPU_REG_RD32(g, ENG_IDX_REG##d(o,d,i,r))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) + +// +// DRF_READ_1WORD_BS() and DRF_READ_1WORD_BS_HIGH() do not read beyond the bytes that contain +// the requested value. Reading beyond the actual data causes a page fault panic when the +// immediately following page happened to be protected or not mapped. +// +#define DRF_VAL_BS_1WORD(d,r,f,v) ((DRF_READ_1WORD_BS(d,r,f,v)>>DRF_SHIFT_MW(NV##d##r##f))&DRF_MASK_MW(NV##d##r##f)) +#define DRF_VAL_BS_2WORD(d,r,f,v) (((DRF_READ_4BYTE_BS(NV##d##r##f,v)>>DRF_SHIFT_MW_LOW(NV##d##r##f))&DRF_MASK_MW_LOW(NV##d##r##f)) | \ + (((DRF_READ_1WORD_BS_HIGH(d,r,f,v)>>DRF_SHIFT_MW_HIGH(NV##d##r##f))&DRF_MASK_MW_HIGH(NV##d##r##f)) << DRF_MERGE_SHIFT(NV##d##r##f))) + +#define DRF_READ_1BYTE_BS(drf,v) ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW(drf)*4])) +#define DRF_READ_2BYTE_BS(drf,v) (DRF_READ_1BYTE_BS(drf,v)| \ + ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW(drf)*4+1])<<8)) +#define DRF_READ_3BYTE_BS(drf,v) (DRF_READ_2BYTE_BS(drf,v)| \ + ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW(drf)*4+2])<<16)) +#define DRF_READ_4BYTE_BS(drf,v) (DRF_READ_3BYTE_BS(drf,v)| \ + ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW(drf)*4+3])<<24)) + +#define DRF_READ_1BYTE_BS_HIGH(drf,v) ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW_HIGH(drf)*4])) +#define DRF_READ_2BYTE_BS_HIGH(drf,v) (DRF_READ_1BYTE_BS_HIGH(drf,v)| \ + ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW_HIGH(drf)*4+1])<<8)) +#define DRF_READ_3BYTE_BS_HIGH(drf,v) (DRF_READ_2BYTE_BS_HIGH(drf,v)| \ + ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW_HIGH(drf)*4+2])<<16)) +#define DRF_READ_4BYTE_BS_HIGH(drf,v) (DRF_READ_3BYTE_BS_HIGH(drf,v)| \ + ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW_HIGH(drf)*4+3])<<24)) + +// Calculate 2^n - 1 and avoid shift counter overflow +// +// On Windows amd64, 64 << 64 => 1 +// +#define NV_TWO_N_MINUS_ONE(n) (((1ULL<<(n/2))<<((n+1)/2))-1) + +#define DRF_READ_1WORD_BS(d,r,f,v) \ + ((DRF_EXTENT_MW(NV##d##r##f)<8)?DRF_READ_1BYTE_BS(NV##d##r##f,(v)): \ + ((DRF_EXTENT_MW(NV##d##r##f)<16)?DRF_READ_2BYTE_BS(NV##d##r##f,(v)): \ + ((DRF_EXTENT_MW(NV##d##r##f)<24)?DRF_READ_3BYTE_BS(NV##d##r##f,(v)): \ + DRF_READ_4BYTE_BS(NV##d##r##f,(v))))) + +#define DRF_READ_1WORD_BS_HIGH(d,r,f,v) \ + ((DRF_EXTENT_MW(NV##d##r##f)<8)?DRF_READ_1BYTE_BS_HIGH(NV##d##r##f,(v)): \ + ((DRF_EXTENT_MW(NV##d##r##f)<16)?DRF_READ_2BYTE_BS_HIGH(NV##d##r##f,(v)): \ + ((DRF_EXTENT_MW(NV##d##r##f)<24)?DRF_READ_3BYTE_BS_HIGH(NV##d##r##f,(v)): \ + DRF_READ_4BYTE_BS_HIGH(NV##d##r##f,(v))))) + +#define LOWESTBIT(x) ( (x) & (((x) - 1U) ^ (x)) ) +// Destructive operation on n32 +#define HIGHESTBIT(n32) \ +{ \ + HIGHESTBITIDX_32(n32); \ + n32 = NVBIT(n32); \ +} +#define ONEBITSET(x) ( ((x) != 0U) && (((x) & ((x) - 1U)) == 0U) ) + +// Destructive operation on n32 +#define NUMSETBITS_32(n32) \ +{ \ + n32 = n32 - ((n32 >> 1) & 0x55555555); \ + n32 = (n32 & 0x33333333) + ((n32 >> 2) & 0x33333333); \ + n32 = (((n32 + (n32 >> 4)) & 0x0F0F0F0F) * 0x01010101) >> 24; \ +} + +/*! + * Calculate number of bits set in a 32-bit unsigned integer. + * Pure typesafe alternative to @ref NUMSETBITS_32. + */ +static NV_FORCEINLINE NvU32 +nvPopCount32(const NvU32 x) +{ + NvU32 temp = x; + temp = temp - ((temp >> 1) & 0x55555555U); + temp = (temp & 0x33333333U) + ((temp >> 2) & 0x33333333U); + temp = (((temp + (temp >> 4)) & 0x0F0F0F0FU) * 0x01010101U) >> 24; + return temp; +} + +/*! + * Calculate number of bits set in a 64-bit unsigned integer. + */ +static NV_FORCEINLINE NvU32 +nvPopCount64(const NvU64 x) +{ + NvU64 temp = x; + temp = temp - ((temp >> 1) & 0x5555555555555555ULL); + temp = (temp & 0x3333333333333333ULL) + ((temp >> 2) & 0x3333333333333333ULL); + temp = (temp + (temp >> 4)) & 0x0F0F0F0F0F0F0F0FULL; + temp = (temp * 0x0101010101010101ULL) >> 56; + return (NvU32)temp; +} + +/*! + * Determine how many bits are set below a bit index within a mask. + * This assigns a dense ordering to the set bits in the mask. + * + * For example the mask 0xCD contains 5 set bits: + * nvMaskPos32(0xCD, 0) == 0 + * nvMaskPos32(0xCD, 2) == 1 + * nvMaskPos32(0xCD, 3) == 2 + * nvMaskPos32(0xCD, 6) == 3 + * nvMaskPos32(0xCD, 7) == 4 + */ +static NV_FORCEINLINE NvU32 +nvMaskPos32(const NvU32 mask, const NvU32 bitIdx) +{ + return nvPopCount32(mask & (NVBIT32(bitIdx) - 1U)); +} + +// Destructive operation on n32 +#define LOWESTBITIDX_32(n32) \ +{ \ + n32 = BIT_IDX_32(LOWESTBIT(n32));\ +} + +// Destructive operation on n32 +#define HIGHESTBITIDX_32(n32) \ +{ \ + NvU32 count = 0; \ + while (n32 >>= 1) \ + { \ + count++; \ + } \ + n32 = count; \ +} + +// Destructive operation on n32 +#define ROUNDUP_POW2(n32) \ +{ \ + n32--; \ + n32 |= n32 >> 1; \ + n32 |= n32 >> 2; \ + n32 |= n32 >> 4; \ + n32 |= n32 >> 8; \ + n32 |= n32 >> 16; \ + n32++; \ +} + +/*! + * Round up a 32-bit unsigned integer to the next power of 2. + * Pure typesafe alternative to @ref ROUNDUP_POW2. + * + * param[in] x must be in range [0, 2^31] to avoid overflow. + */ +static NV_FORCEINLINE NvU32 +nvNextPow2_U32(const NvU32 x) +{ + NvU32 y = x; + y--; + y |= y >> 1; + y |= y >> 2; + y |= y >> 4; + y |= y >> 8; + y |= y >> 16; + y++; + return y; +} + + +static NV_FORCEINLINE NvU32 +nvPrevPow2_U32(const NvU32 x ) +{ + NvU32 y = x; + y |= (y >> 1); + y |= (y >> 2); + y |= (y >> 4); + y |= (y >> 8); + y |= (y >> 16); + return y - (y >> 1); +} + +static NV_FORCEINLINE NvU64 +nvPrevPow2_U64(const NvU64 x ) +{ + NvU64 y = x; + y |= (y >> 1); + y |= (y >> 2); + y |= (y >> 4); + y |= (y >> 8); + y |= (y >> 16); + y |= (y >> 32); + return y - (y >> 1); +} + +// Destructive operation on n64 +#define ROUNDUP_POW2_U64(n64) \ +{ \ + n64--; \ + n64 |= n64 >> 1; \ + n64 |= n64 >> 2; \ + n64 |= n64 >> 4; \ + n64 |= n64 >> 8; \ + n64 |= n64 >> 16; \ + n64 |= n64 >> 32; \ + n64++; \ +} + +#define NV_SWAP_U8(a,b) \ +{ \ + NvU8 temp; \ + temp = a; \ + a = b; \ + b = temp; \ +} + +#define NV_SWAP_U32(a,b) \ +{ \ + NvU32 temp; \ + temp = a; \ + a = b; \ + b = temp; \ +} + +/*! + * @brief Macros allowing simple iteration over bits set in a given mask. + * + * @param[in] maskWidth bit-width of the mask (allowed: 8, 16, 32, 64) + * + * @param[in,out] index lvalue that is used as a bit index in the loop + * (can be declared as any NvU* or NvS* variable) + * @param[in] mask expression, loop will iterate over set bits only + */ +#define FOR_EACH_INDEX_IN_MASK(maskWidth,index,mask) \ +{ \ + NvU##maskWidth lclMsk = (NvU##maskWidth)(mask); \ + for ((index) = 0U; lclMsk != 0U; (index)++, lclMsk >>= 1U)\ + { \ + if (((NvU##maskWidth)NVBIT64(0) & lclMsk) == 0U) \ + { \ + continue; \ + } +#define FOR_EACH_INDEX_IN_MASK_END \ + } \ +} + +// +// Size to use when declaring variable-sized arrays +// +#define NV_ANYSIZE_ARRAY 1 + +// +// Returns ceil(a/b) +// +#define NV_CEIL(a,b) (((a)+(b)-1)/(b)) + +// Clearer name for NV_CEIL +#ifndef NV_DIV_AND_CEIL +#define NV_DIV_AND_CEIL(a, b) NV_CEIL(a,b) +#endif + +#ifndef NV_MIN +#define NV_MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef NV_MAX +#define NV_MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +// +// Returns absolute value of provided integer expression +// +#define NV_ABS(a) ((a)>=0?(a):(-(a))) + +// +// Returns 1 if input number is positive, 0 if 0 and -1 if negative. Avoid +// macro parameter as function call which will have side effects. +// +#define NV_SIGN(s) ((NvS8)(((s) > 0) - ((s) < 0))) + +// +// Returns 1 if input number is >= 0 or -1 otherwise. This assumes 0 has a +// positive sign. +// +#define NV_ZERO_SIGN(s) ((NvS8)((((s) >= 0) * 2) - 1)) + +// Returns the offset (in bytes) of 'member' in struct 'type'. +#ifndef NV_OFFSETOF + #if defined(__GNUC__) && (__GNUC__ > 3) + #define NV_OFFSETOF(type, member) ((NvU32)__builtin_offsetof(type, member)) + #else + #define NV_OFFSETOF(type, member) ((NvU32)(NvU64)&(((type *)0)->member)) // shouldn't we use PtrToUlong? But will need to include windows header. + #endif +#endif + +// +// Performs a rounded division of b into a (unsigned). For SIGNED version of +// NV_ROUNDED_DIV() macro check the comments in bug 769777. +// +#define NV_UNSIGNED_ROUNDED_DIV(a,b) (((a) + ((b) / 2U)) / (b)) + +/*! + * Performs a ceiling division of b into a (unsigned). A "ceiling" division is + * a division is one with rounds up result up if a % b != 0. + * + * @param[in] a Numerator + * @param[in] b Denominator + * + * @return a / b + a % b != 0 ? 1 : 0. + */ +#define NV_UNSIGNED_DIV_CEIL(a, b) (((a) + (b - 1)) / (b)) + +/*! + * Performs subtraction where a negative difference is raised to zero. + * Can be used to avoid underflowing an unsigned subtraction. + * + * @param[in] a Minuend + * @param[in] b Subtrahend + * + * @return a > b ? a - b : 0. + */ +#define NV_SUBTRACT_NO_UNDERFLOW(a, b) ((a)>(b) ? (a)-(b) : 0) + +/*! + * Performs a rounded right-shift of 32-bit unsigned value "a" by "shift" bits. + * Will round result away from zero. + * + * @param[in] a 32-bit unsigned value to shift. + * @param[in] shift Number of bits by which to shift. + * + * @return Resulting shifted value rounded away from zero. + */ +#define NV_RIGHT_SHIFT_ROUNDED(a, shift) \ + (((a) >> (shift)) + !!((NVBIT((shift) - 1) & (a)) == NVBIT((shift) - 1))) + +// +// Power of 2 alignment. +// (Will give unexpected results if 'gran' is not a power of 2.) +// +#ifndef NV_ALIGN_DOWN +// +// Notably using v - v + gran ensures gran gets promoted to the same type as v if gran has a smaller type. +// Otherwise, if aligning a NVU64 with NVU32 granularity, the top 4 bytes get zeroed. +// +#define NV_ALIGN_DOWN(v, gran) ((v) & ~((v) - (v) + (gran) - 1)) +#endif + +#ifndef NV_ALIGN_UP +// +// Notably using v - v + gran ensures gran gets promoted to the same type as v if gran has a smaller type. +// Otherwise, if aligning a NVU64 with NVU32 granularity, the top 4 bytes get zeroed. +// +#define NV_ALIGN_UP(v, gran) (((v) + ((gran) - 1)) & ~((v) - (v) + (gran) - 1)) +#endif + +#ifndef NV_ALIGN_DOWN64 +#define NV_ALIGN_DOWN64(v, gran) ((v) & ~(((NvU64)gran) - 1)) +#endif + +#ifndef NV_ALIGN_UP64 +#define NV_ALIGN_UP64(v, gran) (((v) + ((gran) - 1)) & ~(((NvU64)gran)-1)) +#endif + +#ifndef NV_IS_ALIGNED +#define NV_IS_ALIGNED(v, gran) (0U == ((v) & ((gran) - 1U))) +#endif + +#ifndef NV_IS_ALIGNED64 +#define NV_IS_ALIGNED64(v, gran) (0U == ((v) & (((NvU64)gran) - 1U))) +#endif + +#ifndef NVMISC_MEMSET +static NV_FORCEINLINE void *NVMISC_MEMSET(void *s, NvU8 c, NvLength n) +{ + NvU8 *b = (NvU8 *) s; + NvLength i; + + for (i = 0; i < n; i++) + { + b[i] = c; + } + + return s; +} +#endif + +#ifndef NVMISC_MEMCPY +static NV_FORCEINLINE void *NVMISC_MEMCPY(void *dest, const void *src, NvLength n) +{ + NvU8 *destByte = (NvU8 *) dest; + const NvU8 *srcByte = (const NvU8 *) src; + NvLength i; + + for (i = 0; i < n; i++) + { + destByte[i] = srcByte[i]; + } + + return dest; +} +#endif + +static NV_FORCEINLINE char *NVMISC_STRNCPY(char *dest, const char *src, NvLength n) +{ + NvLength i; + + for (i = 0; i < n; i++) + { + dest[i] = src[i]; + if (src[i] == '\0') + { + break; + } + } + + for (; i < n; i++) + { + dest[i] = '\0'; + } + + return dest; +} + +/*! + * Convert a void* to an NvUPtr. This is used when MISRA forbids us from doing a direct cast. + * + * @param[in] ptr Pointer to be converted + * + * @return Resulting NvUPtr + */ +static NV_FORCEINLINE NvUPtr NV_PTR_TO_NVUPTR(void *ptr) +{ + union + { + NvUPtr v; + void *p; + } uAddr; + + uAddr.p = ptr; + return uAddr.v; +} + +/*! + * Convert an NvUPtr to a void*. This is used when MISRA forbids us from doing a direct cast. + * + * @param[in] ptr Pointer to be converted + * + * @return Resulting void * + */ +static NV_FORCEINLINE void *NV_NVUPTR_TO_PTR(NvUPtr address) +{ + union + { + NvUPtr v; + void *p; + } uAddr; + + uAddr.v = address; + return uAddr.p; +} + +// Get bit at pos (k) from x +#define NV_BIT_GET(k, x) (((x) >> (k)) & 1) +// Get bit at pos (n) from (hi) if >= 64, otherwise from (lo). This is paired with NV_BIT_SET_128 which sets the bit. +#define NV_BIT_GET_128(n, lo, hi) (((n) < 64) ? NV_BIT_GET((n), (lo)) : NV_BIT_GET((n) - 64, (hi))) +// +// Set the bit at pos (b) for U64 which is < 128. Since the (b) can be >= 64, we need 2 U64 to store this. +// Use (lo) if (b) is less than 64, and (hi) if >= 64. +// +#define NV_BIT_SET_128(b, lo, hi) { nvAssert( (b) < 128 ); if ( (b) < 64 ) (lo) |= NVBIT64(b); else (hi) |= NVBIT64( b & 0x3F ); } + +#ifdef __cplusplus +} +#endif //__cplusplus + +#endif // __NV_MISC_H + diff --git a/userspace/sdks/nv570/nvidia/inc/nvos.h b/userspace/sdks/nv570/nvidia/inc/nvos.h new file mode 100644 index 0000000..4fb1870 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/nvos.h @@ -0,0 +1,2909 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + /***************************************************************************\ +|* *| +|* NV Architecture Interface *| +|* *| +|* defines the Operating System function and ioctl interfaces to *| +|* NVIDIA's Unified Media Architecture (TM). *| +|* *| + \***************************************************************************/ + +#ifndef NVOS_INCLUDED +#define NVOS_INCLUDED +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvstatus.h" + +#include "nvgputypes.h" +#include "rs_access.h" +#include "nvcfg_sdk.h" + + +// Temporary include. Please include this directly instead of nvos.h +#include "alloc/alloc_channel.h" + +/* local defines here */ +#define FILE_DEVICE_NV 0x00008000 +#define NV_IOCTL_FCT_BASE 0x00000800 + +// This is the maximum number of subdevices supported in an SLI +// configuration. +#define NVOS_MAX_SUBDEVICES 8 + +/* Define to indicate the use of Unified status codes - bug 200043705*/ +#define UNIFIED_NV_STATUS 1 + + /***************************************************************************\ +|* NV OS Functions *| + \***************************************************************************/ + +/* + Result codes for RM APIs, shared for all the APIs + + *** IMPORTANT *** + + Ensure that no NVOS_STATUS value has the highest bit set. That bit + is used to passthrough the NVOS_STATUS on code expecting an RM_STATUS. +*/ +#define NVOS_STATUS NV_STATUS + +#define NVOS_STATUS_SUCCESS NV_OK +#define NVOS_STATUS_ERROR_CARD_NOT_PRESENT NV_ERR_CARD_NOT_PRESENT +#define NVOS_STATUS_ERROR_DUAL_LINK_INUSE NV_ERR_DUAL_LINK_INUSE +#define NVOS_STATUS_ERROR_GENERIC NV_ERR_GENERIC +#define NVOS_STATUS_ERROR_GPU_NOT_FULL_POWER NV_ERR_GPU_NOT_FULL_POWER +#define NVOS_STATUS_ERROR_ILLEGAL_ACTION NV_ERR_ILLEGAL_ACTION +#define NVOS_STATUS_ERROR_IN_USE NV_ERR_STATE_IN_USE +#define NVOS_STATUS_ERROR_INSUFFICIENT_RESOURCES NV_ERR_INSUFFICIENT_RESOURCES +#define NVOS_STATUS_ERROR_INVALID_ACCESS_TYPE NV_ERR_INVALID_ACCESS_TYPE +#define NVOS_STATUS_ERROR_INVALID_ARGUMENT NV_ERR_INVALID_ARGUMENT +#define NVOS_STATUS_ERROR_INVALID_BASE NV_ERR_INVALID_BASE +#define NVOS_STATUS_ERROR_INVALID_CHANNEL NV_ERR_INVALID_CHANNEL +#define NVOS_STATUS_ERROR_INVALID_CLASS NV_ERR_INVALID_CLASS +#define NVOS_STATUS_ERROR_INVALID_CLIENT NV_ERR_INVALID_CLIENT +#define NVOS_STATUS_ERROR_INVALID_COMMAND NV_ERR_INVALID_COMMAND +#define NVOS_STATUS_ERROR_INVALID_DATA NV_ERR_INVALID_DATA +#define NVOS_STATUS_ERROR_INVALID_DEVICE NV_ERR_INVALID_DEVICE +#define NVOS_STATUS_ERROR_INVALID_DMA_SPECIFIER NV_ERR_INVALID_DMA_SPECIFIER +#define NVOS_STATUS_ERROR_INVALID_EVENT NV_ERR_INVALID_EVENT +#define NVOS_STATUS_ERROR_INVALID_FLAGS NV_ERR_INVALID_FLAGS +#define NVOS_STATUS_ERROR_INVALID_FUNCTION NV_ERR_INVALID_FUNCTION +#define NVOS_STATUS_ERROR_INVALID_HEAP NV_ERR_INVALID_HEAP +#define NVOS_STATUS_ERROR_INVALID_INDEX NV_ERR_INVALID_INDEX +#define NVOS_STATUS_ERROR_INVALID_LIMIT NV_ERR_INVALID_LIMIT +#define NVOS_STATUS_ERROR_INVALID_METHOD NV_ERR_INVALID_METHOD +#define NVOS_STATUS_ERROR_INVALID_OBJECT_BUFFER NV_ERR_BUFFER_TOO_SMALL +#define NVOS_STATUS_ERROR_INVALID_OBJECT_ERROR NV_ERR_INVALID_OBJECT +#define NVOS_STATUS_ERROR_INVALID_OBJECT_HANDLE NV_ERR_INVALID_OBJECT_HANDLE +#define NVOS_STATUS_ERROR_INVALID_OBJECT_NEW NV_ERR_INVALID_OBJECT_NEW +#define NVOS_STATUS_ERROR_INVALID_OBJECT_OLD NV_ERR_INVALID_OBJECT_OLD +#define NVOS_STATUS_ERROR_INVALID_OBJECT_PARENT NV_ERR_INVALID_OBJECT_PARENT +#define NVOS_STATUS_ERROR_INVALID_OFFSET NV_ERR_INVALID_OFFSET +#define NVOS_STATUS_ERROR_INVALID_OWNER NV_ERR_INVALID_OWNER +#define NVOS_STATUS_ERROR_INVALID_PARAM_STRUCT NV_ERR_INVALID_PARAM_STRUCT +#define NVOS_STATUS_ERROR_INVALID_PARAMETER NV_ERR_INVALID_PARAMETER +#define NVOS_STATUS_ERROR_INVALID_POINTER NV_ERR_INVALID_POINTER +#define NVOS_STATUS_ERROR_INVALID_REGISTRY_KEY NV_ERR_INVALID_REGISTRY_KEY +#define NVOS_STATUS_ERROR_INVALID_STATE NV_ERR_INVALID_STATE +#define NVOS_STATUS_ERROR_INVALID_STRING_LENGTH NV_ERR_INVALID_STRING_LENGTH +#define NVOS_STATUS_ERROR_INVALID_XLATE NV_ERR_INVALID_XLATE +#define NVOS_STATUS_ERROR_IRQ_NOT_FIRING NV_ERR_IRQ_NOT_FIRING +#define NVOS_STATUS_ERROR_MULTIPLE_MEMORY_TYPES NV_ERR_MULTIPLE_MEMORY_TYPES +#define NVOS_STATUS_ERROR_NOT_SUPPORTED NV_ERR_NOT_SUPPORTED +#define NVOS_STATUS_ERROR_OPERATING_SYSTEM NV_ERR_OPERATING_SYSTEM +#define NVOS_STATUS_ERROR_LIB_RM_VERSION_MISMATCH NV_ERR_LIB_RM_VERSION_MISMATCH +#define NVOS_STATUS_ERROR_PROTECTION_FAULT NV_ERR_PROTECTION_FAULT +#define NVOS_STATUS_ERROR_TIMEOUT NV_ERR_TIMEOUT +#define NVOS_STATUS_ERROR_TOO_MANY_PRIMARIES NV_ERR_TOO_MANY_PRIMARIES +#define NVOS_STATUS_ERROR_IRQ_EDGE_TRIGGERED NV_ERR_IRQ_EDGE_TRIGGERED +#define NVOS_STATUS_ERROR_INVALID_OPERATION NV_ERR_INVALID_OPERATION +#define NVOS_STATUS_ERROR_NOT_COMPATIBLE NV_ERR_NOT_COMPATIBLE +#define NVOS_STATUS_ERROR_MORE_PROCESSING_REQUIRED NV_WARN_MORE_PROCESSING_REQUIRED +#define NVOS_STATUS_ERROR_INSUFFICIENT_PERMISSIONS NV_ERR_INSUFFICIENT_PERMISSIONS +#define NVOS_STATUS_ERROR_TIMEOUT_RETRY NV_ERR_TIMEOUT_RETRY +#define NVOS_STATUS_ERROR_NOT_READY NV_ERR_NOT_READY +#define NVOS_STATUS_ERROR_GPU_IS_LOST NV_ERR_GPU_IS_LOST +#define NVOS_STATUS_ERROR_IN_FULLCHIP_RESET NV_ERR_GPU_IN_FULLCHIP_RESET +#define NVOS_STATUS_ERROR_INVALID_LOCK_STATE NV_ERR_INVALID_LOCK_STATE +#define NVOS_STATUS_ERROR_INVALID_ADDRESS NV_ERR_INVALID_ADDRESS +#define NVOS_STATUS_ERROR_INVALID_IRQ_LEVEL NV_ERR_INVALID_IRQ_LEVEL +#define NVOS_STATUS_ERROR_MEMORY_TRAINING_FAILED NV_ERR_MEMORY_TRAINING_FAILED +#define NVOS_STATUS_ERROR_BUSY_RETRY NV_ERR_BUSY_RETRY +#define NVOS_STATUS_ERROR_INSUFFICIENT_POWER NV_ERR_INSUFFICIENT_POWER +#define NVOS_STATUS_ERROR_OBJECT_NOT_FOUND NV_ERR_OBJECT_NOT_FOUND +#define NVOS_STATUS_ERROR_RESOURCE_LOST NV_ERR_RESOURCE_LOST +#define NVOS_STATUS_ERROR_BUFFER_TOO_SMALL NV_ERR_BUFFER_TOO_SMALL +#define NVOS_STATUS_ERROR_RESET_REQUIRED NV_ERR_RESET_REQUIRED +#define NVOS_STATUS_ERROR_INVALID_REQUEST NV_ERR_INVALID_REQUEST + +#define NVOS_STATUS_ERROR_PRIV_SEC_VIOLATION NV_ERR_PRIV_SEC_VIOLATION +#define NVOS_STATUS_ERROR_GPU_IN_DEBUG_MODE NV_ERR_GPU_IN_DEBUG_MODE + +/* + Note: + This version of the architecture has been changed to allow the + RM to return a client handle that will subsequently used to + identify the client. NvAllocRoot() returns the handle. All + other functions must specify this client handle. + +*/ +/* macro NV01_FREE */ +#define NV01_FREE (0x00000000) + +/* NT ioctl data structure */ +typedef struct +{ + NvHandle hRoot; + NvHandle hObjectParent; + NvHandle hObjectOld; + NvV32 status; +} NVOS00_PARAMETERS; + +/* valid hClass values. */ +#define NV01_ROOT (0x0U) +// +// Redefining it here to maintain consistency with current code +// This is also defined in class cl0001.h +// +#define NV01_ROOT_NON_PRIV (0x00000001) + +// Deprecated, please use NV01_ROOT_CLIENT +#define NV01_ROOT_USER NV01_ROOT_CLIENT + +// +// This will eventually replace NV01_ROOT_USER in RM client code. Please use this +// RM client object type for any new RM client object allocations that are being +// added. +// +#define NV01_ROOT_CLIENT (0x00000041) + +/* macro NV01_ALLOC_MEMORY */ +#define NV01_ALLOC_MEMORY (0x00000002) + +/* parameter values */ +#define NVOS02_FLAGS_PHYSICALITY 7:4 +#define NVOS02_FLAGS_PHYSICALITY_CONTIGUOUS (0x00000000) +#define NVOS02_FLAGS_PHYSICALITY_NONCONTIGUOUS (0x00000001) +#define NVOS02_FLAGS_LOCATION 11:8 +#define NVOS02_FLAGS_LOCATION_PCI (0x00000000) +#define NVOS02_FLAGS_LOCATION_AGP (0x00000001) +#define NVOS02_FLAGS_LOCATION_VIDMEM (0x00000002) +#define NVOS02_FLAGS_COHERENCY 15:12 +#define NVOS02_FLAGS_COHERENCY_UNCACHED (0x00000000) +#define NVOS02_FLAGS_COHERENCY_CACHED (0x00000001) +#define NVOS02_FLAGS_COHERENCY_WRITE_COMBINE (0x00000002) +#define NVOS02_FLAGS_COHERENCY_WRITE_THROUGH (0x00000003) +#define NVOS02_FLAGS_COHERENCY_WRITE_PROTECT (0x00000004) +#define NVOS02_FLAGS_COHERENCY_WRITE_BACK (0x00000005) +#define NVOS02_FLAGS_ALLOC 17:16 +#define NVOS02_FLAGS_ALLOC_NONE (0x00000001) +#define NVOS02_FLAGS_GPU_CACHEABLE 18:18 +#define NVOS02_FLAGS_GPU_CACHEABLE_NO (0x00000000) +#define NVOS02_FLAGS_GPU_CACHEABLE_YES (0x00000001) +// If requested, RM will create a kernel mapping of this memory. +// Default is no map. +#define NVOS02_FLAGS_KERNEL_MAPPING 19:19 +#define NVOS02_FLAGS_KERNEL_MAPPING_NO_MAP (0x00000000) +#define NVOS02_FLAGS_KERNEL_MAPPING_MAP (0x00000001) +#define NVOS02_FLAGS_ALLOC_NISO_DISPLAY 20:20 +#define NVOS02_FLAGS_ALLOC_NISO_DISPLAY_NO (0x00000000) +#define NVOS02_FLAGS_ALLOC_NISO_DISPLAY_YES (0x00000001) + +// +// If the flag is set, the RM will only allow read-only CPU user mappings to the +// allocation. +// +#define NVOS02_FLAGS_ALLOC_USER_READ_ONLY 21:21 +#define NVOS02_FLAGS_ALLOC_USER_READ_ONLY_NO (0x00000000) +#define NVOS02_FLAGS_ALLOC_USER_READ_ONLY_YES (0x00000001) + +// +// If the flag is set, the RM will only allow read-only DMA mappings to the +// allocation. +// +#define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY 22:22 +#define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_NO (0x00000000) +#define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_YES (0x00000001) + +// +// If the flag is set, the IO memory allocation can be registered with the RM if +// the RM regkey peerMappingOverride is set or the client is privileged. +// +// See Bug 1630288 "[PeerSync] threat related to GPU.." for more details. +// +#define NVOS02_FLAGS_PEER_MAP_OVERRIDE 23:23 +#define NVOS02_FLAGS_PEER_MAP_OVERRIDE_DEFAULT (0x00000000) +#define NVOS02_FLAGS_PEER_MAP_OVERRIDE_REQUIRED (0x00000001) + +// If the flag is set RM will assume the memory pages are of type syncpoint. +#define NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT 24:24 +#define NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT_APERTURE (0x00000001) + +// +// If _NO_MAP is requested, the RM in supported platforms will not map the +// allocated system or IO memory into user space. The client can later map +// memory through the RmMapMemory() interface. +// If _NEVER_MAP is requested, the RM will never map the allocated system or +// IO memory into user space +// +#define NVOS02_FLAGS_MAPPING 31:30 +#define NVOS02_FLAGS_MAPPING_DEFAULT (0x00000000) +#define NVOS02_FLAGS_MAPPING_NO_MAP (0x00000001) +#define NVOS02_FLAGS_MAPPING_NEVER_MAP (0x00000002) + +// ------------------------------------------------------------------------------------- + +/* parameters */ +typedef struct +{ + NvHandle hRoot; + NvHandle hObjectParent; + NvHandle hObjectNew; + NvV32 hClass; + NvV32 flags; + NvP64 pMemory NV_ALIGN_BYTES(8); + NvU64 limit NV_ALIGN_BYTES(8); + NvV32 status; +} NVOS02_PARAMETERS; + +/* parameter values */ +#define NVOS03_FLAGS_ACCESS 1:0 +#define NVOS03_FLAGS_ACCESS_READ_WRITE (0x00000000) +#define NVOS03_FLAGS_ACCESS_READ_ONLY (0x00000001) +#define NVOS03_FLAGS_ACCESS_WRITE_ONLY (0x00000002) + +#define NVOS03_FLAGS_PREALLOCATE 2:2 +#define NVOS03_FLAGS_PREALLOCATE_DISABLE (0x00000000) +#define NVOS03_FLAGS_PREALLOCATE_ENABLE (0x00000001) + +#define NVOS03_FLAGS_GPU_MAPPABLE 15:15 +#define NVOS03_FLAGS_GPU_MAPPABLE_DISABLE (0x00000000) +#define NVOS03_FLAGS_GPU_MAPPABLE_ENABLE (0x00000001) + +// ------------------------------------------------------------------------------------ +// This flag is required for a hack to be placed inside DD that allows it to +// access a dummy ctxdma as a block linear surface. Refer bug 1562766 for details. +// +// This flag is deprecated, use NVOS03_FLAGS_PTE_KIND. +// +#define NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE 16:16 +#define NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE_FALSE (0x00000000) +#define NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE_TRUE (0x00000001) + +/* + * This field allows to specify the page kind. If the page kind + * is not specified then the page kind associated with the memory will be used. + * + * In tegra display driver stack, the page kind remains unknown at the time + * of memory allocation/import, the page kind can only be known when display + * driver client creates a framebuffer from allocated/imported memory. + * + * This field compatible with NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE flag. + */ +#define NVOS03_FLAGS_PTE_KIND 17:16 +#define NVOS03_FLAGS_PTE_KIND_NONE (0x00000000) +#define NVOS03_FLAGS_PTE_KIND_BL (0x00000001) +#define NVOS03_FLAGS_PTE_KIND_PITCH (0x00000002) + +#define NVOS03_FLAGS_TYPE 23:20 +#define NVOS03_FLAGS_TYPE_NOTIFIER (0x00000001) + +/* + * This is an alias into the LSB of the TYPE field which + * actually indicates if a Kernel Mapping should be created. + * If the RM should have access to the memory then Enable this + * flag. + * + * Note that the NV_OS03_FLAGS_MAPPING is an alias to + * the LSB of the NV_OS03_FLAGS_TYPE. And in fact if + * type is NV_OS03_FLAGS_TYPE_NOTIFIER (bit 20 set) + * then it implicitly means that NV_OS03_FLAGS_MAPPING + * is _MAPPING_KERNEL. If the client wants to have a + * Kernel Mapping, it should use the _MAPPING_KERNEL + * flag set and the _TYPE_NOTIFIER should be used only + * with NOTIFIERS. + */ + +#define NVOS03_FLAGS_MAPPING 20:20 +#define NVOS03_FLAGS_MAPPING_NONE (0x00000000) +#define NVOS03_FLAGS_MAPPING_KERNEL (0x00000001) + +#define NVOS03_FLAGS_CACHE_SNOOP 28:28 +#define NVOS03_FLAGS_CACHE_SNOOP_ENABLE (0x00000000) +#define NVOS03_FLAGS_CACHE_SNOOP_DISABLE (0x00000001) + +// HASH_TABLE:ENABLE means that the context DMA is automatically bound into all +// channels in the client. This can lead to excessive hash table usage. +// HASH_TABLE:DISABLE means that the context DMA must be explicitly bound into +// any channel that needs to use it via NvRmBindContextDma. +// HASH_TABLE:ENABLE is not supported on NV50 and up, and HASH_TABLE:DISABLE should +// be preferred for all new code. +#define NVOS03_FLAGS_HASH_TABLE 29:29 +#define NVOS03_FLAGS_HASH_TABLE_ENABLE (0x00000000) +#define NVOS03_FLAGS_HASH_TABLE_DISABLE (0x00000001) + +/* macro NV01_ALLOC_OBJECT */ +#define NV01_ALLOC_OBJECT (0x00000005) + +/* parameters */ +typedef struct +{ + NvHandle hRoot; + NvHandle hObjectParent; + NvHandle hObjectNew; + NvV32 hClass; + NvV32 status; +} NVOS05_PARAMETERS; + +/* Valid values for hClass in Nv01AllocEvent */ +/* Note that NV01_EVENT_OS_EVENT is same as NV01_EVENT_WIN32_EVENT */ +/* TODO: delete the WIN32 name */ +#define NV01_EVENT_KERNEL_CALLBACK (0x00000078) +#define NV01_EVENT_OS_EVENT (0x00000079) +#define NV01_EVENT_WIN32_EVENT NV01_EVENT_OS_EVENT +#define NV01_EVENT_KERNEL_CALLBACK_EX (0x0000007E) + +/* NOTE: NV01_EVENT_KERNEL_CALLBACK is deprecated. Please use NV01_EVENT_KERNEL_CALLBACK_EX. */ +/* For use with NV01_EVENT_KERNEL_CALLBACK. */ +/* NVOS10_EVENT_KERNEL_CALLBACK data structure storage needs to be retained by the caller. */ +typedef void (*Callback1ArgVoidReturn)(void *arg); +typedef void (*Callback5ArgVoidReturn)(void *arg1, void *arg2, NvHandle hEvent, NvU32 data, NvU32 status); + +/* NOTE: the 'void* arg' below is ok (but unfortunate) since this interface + can only be used by other kernel drivers which must share the same ptr-size */ +typedef struct +{ + Callback1ArgVoidReturn func; + void *arg; +} NVOS10_EVENT_KERNEL_CALLBACK; + +/* For use with NV01_EVENT_KERNEL_CALLBACK_EX. */ +/* NVOS10_EVENT_KERNEL_CALLBACK_EX data structure storage needs to be retained by the caller. */ +/* NOTE: the 'void* arg' below is ok (but unfortunate) since this interface + can only be used by other kernel drivers which must share the same ptr-size */ +typedef struct +{ + Callback5ArgVoidReturn func; + void *arg; +} NVOS10_EVENT_KERNEL_CALLBACK_EX; + +/* Setting this bit in index will set the Event to a Broadcast type */ +/* i.e. each subdevice under a device needs to see the Event before it's signaled */ +#define NV01_EVENT_BROADCAST (0x80000000) + +/* allow non-root resman client to create NV01_EVENT_KERNEL_CALLBACK events */ +/* -- this works in debug/develop drivers only (for security reasons)*/ +#define NV01_EVENT_PERMIT_NON_ROOT_EVENT_KERNEL_CALLBACK_CREATION (0x40000000) + +/* RM event should be triggered only by the specified subdevice; see cl0005.h + * for details re: how to specify subdevice. */ +#define NV01_EVENT_SUBDEVICE_SPECIFIC (0x20000000) + +/* RM should trigger the event but shouldn't do the book-keeping of data + * associated with that event */ +#define NV01_EVENT_WITHOUT_EVENT_DATA (0x10000000) + +/* RM event should be triggered only by the non-stall interrupt */ +#define NV01_EVENT_NONSTALL_INTR (0x08000000) + +/* RM event was allocated from client RM, post events back to client RM */ +#define NV01_EVENT_CLIENT_RM (0x04000000) + +/* function OS19 */ +#define NV04_I2C_ACCESS (0x00000013) + +#define NVOS_I2C_ACCESS_MAX_BUFFER_SIZE 2048 + +/* parameters */ +typedef struct +{ + NvHandle hClient; + NvHandle hDevice; + NvU32 paramSize; + NvP64 paramStructPtr NV_ALIGN_BYTES(8); + NvV32 status; +} NVOS_I2C_ACCESS_PARAMS; + +/* current values for command */ +#define NVOS20_COMMAND_unused0001 0x0001 +#define NVOS20_COMMAND_unused0002 0x0002 +#define NVOS20_COMMAND_STRING_PRINT 0x0003 + +/* function OS21 */ +#define NV04_ALLOC (0x00000015) + +/* parameters */ +typedef struct +{ + NvHandle hRoot; + NvHandle hObjectParent; + NvHandle hObjectNew; + NvV32 hClass; + NvP64 pAllocParms NV_ALIGN_BYTES(8); + NvV32 status; +} NVOS21_PARAMETERS; + +#define NVOS64_FLAGS_NONE (0x00000000) +#define NVOS64_FLAGS_FINN_SERIALIZED (0x00000001) + +/* New struct with rights requested */ +typedef struct +{ + NvHandle hRoot; // [IN] client handle + NvHandle hObjectParent; // [IN] parent handle of new object + NvHandle hObjectNew; // [INOUT] new object handle, 0 to generate + NvV32 hClass; // [in] class num of new object + NvP64 pAllocParms NV_ALIGN_BYTES(8); // [IN] class-specific alloc parameters + NvP64 pRightsRequested NV_ALIGN_BYTES(8); // [IN] RS_ACCESS_MASK to request rights, or NULL + NvU32 flags; // [IN] flags for FINN serialization + NvV32 status; // [OUT] status +} NVOS64_PARAMETERS; + +/* RM Alloc header + * + * Replacement for NVOS21/64_PARAMETERS where embedded pointers are not allowed. + * Input layout for RM Alloc user space calls should be + * + * +--- NVOS62_PARAMETERS ---+--- RM Alloc parameters ---+ + * +--- NVOS65_PARAMETERS ---+--- Rights Requested ---+--- RM Alloc parameters ---+ + * + * NVOS62_PARAMETERS::paramsSize is the size of RM Alloc parameters + * If NVOS65_PARAMETERS::maskSize is 0, Rights Requested will not be present in memory. + * + */ +typedef struct +{ + NvHandle hRoot; // [IN] client handle + NvHandle hObjectParent; // [IN] parent handle of the new object + NvHandle hObjectNew; // [IN] new object handle + NvV32 hClass; // [IN] class num of the new object + NvU32 paramSize; // [IN] size in bytes of the RM alloc parameters + NvV32 status; // [OUT] status +} NVOS62_PARAMETERS; + +#define NVOS65_PARAMETERS_VERSION_MAGIC 0x77FEF81E + +typedef struct +{ + NvHandle hRoot; // [IN] client handle + NvHandle hObjectParent; // [IN] parent handle of the new object + NvHandle hObjectNew; // [INOUT] new object handle, 0 to generate + NvV32 hClass; // [IN] class num of the new object + NvU32 paramSize; // [IN] size in bytes of the RM alloc parameters + NvU32 versionMagic; // [IN] NVOS65_PARAMETERS_VERISON_MAGIC + NvU32 maskSize; // [IN] size in bytes of access mask, or 0 if NULL + NvV32 status; // [OUT] status +} NVOS65_PARAMETERS; + +/* function OS30 */ +#define NV04_IDLE_CHANNELS (0x0000001E) + +/* parameter values */ +#define NVOS30_FLAGS_BEHAVIOR 3:0 +#define NVOS30_FLAGS_BEHAVIOR_SPIN (0x00000000) +#define NVOS30_FLAGS_BEHAVIOR_SLEEP (0x00000001) +#define NVOS30_FLAGS_BEHAVIOR_QUERY (0x00000002) +#define NVOS30_FLAGS_BEHAVIOR_FORCE_BUSY_CHECK (0x00000003) +#define NVOS30_FLAGS_CHANNEL 7:4 +#define NVOS30_FLAGS_CHANNEL_LIST (0x00000000) +#define NVOS30_FLAGS_CHANNEL_SINGLE (0x00000001) +#define NVOS30_FLAGS_IDLE 30:8 +#define NVOS30_FLAGS_IDLE_PUSH_BUFFER (0x00000001) +#define NVOS30_FLAGS_IDLE_CACHE1 (0x00000002) +#define NVOS30_FLAGS_IDLE_GRAPHICS (0x00000004) +#define NVOS30_FLAGS_IDLE_MPEG (0x00000008) +#define NVOS30_FLAGS_IDLE_MOTION_ESTIMATION (0x00000010) +#define NVOS30_FLAGS_IDLE_VIDEO_PROCESSOR (0x00000020) +#define NVOS30_FLAGS_IDLE_MSPDEC (0x00000020) +#define NVOS30_FLAGS_IDLE_BITSTREAM_PROCESSOR (0x00000040) +#define NVOS30_FLAGS_IDLE_MSVLD (0x00000040) +#define NVOS30_FLAGS_IDLE_NVDEC0 NVOS30_FLAGS_IDLE_MSVLD +#define NVOS30_FLAGS_IDLE_CIPHER_DMA (0x00000080) +#define NVOS30_FLAGS_IDLE_SEC (0x00000080) +#define NVOS30_FLAGS_IDLE_CALLBACKS (0x00000100) +#define NVOS30_FLAGS_IDLE_MSPPP (0x00000200) +#define NVOS30_FLAGS_IDLE_CE0 (0x00000400) +#define NVOS30_FLAGS_IDLE_CE1 (0x00000800) +#define NVOS30_FLAGS_IDLE_CE2 (0x00001000) +#define NVOS30_FLAGS_IDLE_CE3 (0x00002000) +#define NVOS30_FLAGS_IDLE_CE4 (0x00004000) +#define NVOS30_FLAGS_IDLE_CE5 (0x00008000) +#define NVOS30_FLAGS_IDLE_VIC (0x00010000) +#define NVOS30_FLAGS_IDLE_MSENC (0x00020000) +#define NVOS30_FLAGS_IDLE_NVENC0 NVOS30_FLAGS_IDLE_MSENC +#define NVOS30_FLAGS_IDLE_NVENC1 (0x00040000) +#define NVOS30_FLAGS_IDLE_NVENC2 (0x00080000) +#define NVOS30_FLAGS_IDLE_NVJPG (0x00100000) +#define NVOS30_FLAGS_IDLE_NVDEC1 (0x00200000) +#define NVOS30_FLAGS_IDLE_NVDEC2 (0x00400000) +#define NVOS30_FLAGS_IDLE_ACTIVECHANNELS (0x00800000) +#define NVOS30_FLAGS_IDLE_ALL_ENGINES (NVOS30_FLAGS_IDLE_GRAPHICS | \ + NVOS30_FLAGS_IDLE_MPEG | \ + NVOS30_FLAGS_IDLE_MOTION_ESTIMATION | \ + NVOS30_FLAGS_IDLE_VIDEO_PROCESSOR | \ + NVOS30_FLAGS_IDLE_BITSTREAM_PROCESSOR | \ + NVOS30_FLAGS_IDLE_CIPHER_DMA | \ + NVOS30_FLAGS_IDLE_MSPDEC | \ + NVOS30_FLAGS_IDLE_NVDEC0 | \ + NVOS30_FLAGS_IDLE_SEC | \ + NVOS30_FLAGS_IDLE_MSPPP | \ + NVOS30_FLAGS_IDLE_CE0 | \ + NVOS30_FLAGS_IDLE_CE1 | \ + NVOS30_FLAGS_IDLE_CE2 | \ + NVOS30_FLAGS_IDLE_CE3 | \ + NVOS30_FLAGS_IDLE_CE4 | \ + NVOS30_FLAGS_IDLE_CE5 | \ + NVOS30_FLAGS_IDLE_NVENC0 | \ + NVOS30_FLAGS_IDLE_NVENC1 | \ + NVOS30_FLAGS_IDLE_NVENC2 | \ + NVOS30_FLAGS_IDLE_VIC | \ + NVOS30_FLAGS_IDLE_NVJPG | \ + NVOS30_FLAGS_IDLE_NVDEC1 | \ + NVOS30_FLAGS_IDLE_NVDEC2) +#define NVOS30_FLAGS_WAIT_FOR_ELPG_ON 31:31 +#define NVOS30_FLAGS_WAIT_FOR_ELPG_ON_NO (0x00000000) +#define NVOS30_FLAGS_WAIT_FOR_ELPG_ON_YES (0x00000001) + +/* parameters */ +typedef struct +{ + NvHandle hClient; + NvHandle hDevice; + NvHandle hChannel; + NvV32 numChannels; + + NvP64 phClients NV_ALIGN_BYTES(8); + NvP64 phDevices NV_ALIGN_BYTES(8); + NvP64 phChannels NV_ALIGN_BYTES(8); + + NvV32 flags; + NvV32 timeout; + NvV32 status; +} NVOS30_PARAMETERS; + +/* function OS32 */ +typedef void (*BindResultFunc)(void * pVoid, NvU32 gpuMask, NvU32 bState, NvU32 bResult); + +#define NV04_VID_HEAP_CONTROL (0x00000020) +/************************************************************************* +************************ New Heap Interface ****************************** +*************************************************************************/ +// NVOS32 Descriptor types +// +// NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR: The dma-buf object +// pointer, provided by the linux kernel buffer sharing sub-system. +// This descriptor can only be used by kernel space rm-clients. +// +#define NVOS32_DESCRIPTOR_TYPE_VIRTUAL_ADDRESS 0 +#define NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY 1 +#define NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY 2 +#define NVOS32_DESCRIPTOR_TYPE_OS_PHYS_ADDR 3 +#define NVOS32_DESCRIPTOR_TYPE_OS_FILE_HANDLE 4 +#define NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR 5 +#define NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR 6 +#define NVOS32_DESCRIPTOR_TYPE_KERNEL_VIRTUAL_ADDRESS 7 +// NVOS32 function +#define NVOS32_FUNCTION_ALLOC_DEPTH_WIDTH_HEIGHT 1 +#define NVOS32_FUNCTION_ALLOC_SIZE 2 +#define NVOS32_FUNCTION_FREE 3 +// #define NVOS32_FUNCTION_HEAP_PURGE 4 +#define NVOS32_FUNCTION_INFO 5 +#define NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT 6 +// #define NVOS32_FUNCTION_DESTROY 7 +// #define NVOS32_FUNCTION_RETAIN 9 +// #define NVOS32_FUNCTION_REALLOC 10 +#define NVOS32_FUNCTION_DUMP 11 +// #define NVOS32_FUNCTION_INFO_TYPE_ALLOC_BLOCKS 12 +#define NVOS32_FUNCTION_ALLOC_SIZE_RANGE 14 +#define NVOS32_FUNCTION_REACQUIRE_COMPR 15 +#define NVOS32_FUNCTION_RELEASE_COMPR 16 +// #define NVOS32_FUNCTION_MODIFY_DEFERRED_TILES 17 +#define NVOS32_FUNCTION_GET_MEM_ALIGNMENT 18 +#define NVOS32_FUNCTION_HW_ALLOC 19 +#define NVOS32_FUNCTION_HW_FREE 20 +// #define NVOS32_FUNCTION_SET_OFFSET 21 +// #define NVOS32_FUNCTION_IS_TILED 22 +// #define NVOS32_FUNCTION_ENABLE_RESOURCE 23 +// #define NVOS32_FUNCTION_BIND_COMPR 24 +#define NVOS32_FUNCTION_ALLOC_OS_DESCRIPTOR 27 + +typedef struct +{ + NvP64 sgt NV_ALIGN_BYTES(8); + NvP64 gem NV_ALIGN_BYTES(8); +} NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS; + +#define NVOS32_FLAGS_BLOCKINFO_VISIBILITY_CPU (0x00000001) +typedef struct +{ + NvU64 startOffset NV_ALIGN_BYTES(8); + NvU64 size NV_ALIGN_BYTES(8); + NvU32 flags; +} NVOS32_BLOCKINFO; + +// NVOS32 IVC-heap number delimiting value +#define NVOS32_IVC_HEAP_NUMBER_DONT_ALLOCATE_ON_IVC_HEAP 0 // When IVC heaps are present, + // IVC-heap number specified + // as part of 'NVOS32_PARAMETERS' + // which is less or equal to this + // constant indicates that allocation + // should not be done on IVC heap. + // Explanation of IVC-heap number is + // under 'AllocSize' structure below. + +typedef struct +{ + NvHandle hRoot; // [IN] - root object handle + NvHandle hObjectParent; // [IN] - device handle + NvU32 function; // [IN] - heap function, see below FUNCTION* defines + NvHandle hVASpace; // [IN] - VASpace handle + NvS16 ivcHeapNumber; // [IN] - When IVC heaps are present: either 1) number of the IVC heap + // shared between two VMs or 2) number indicating that allocation + // should not be done on an IVC heap. Values greater than constant + // 'NVOS32_IVC_HEAP_NUMBER_DONT_ALLOCATE_ON_IVC_HEAP' define set 1) + // and values less or equal to that constant define set 2). + // When IVC heaps are present, correct IVC-heap number must be specified. + // When IVC heaps are absent, IVC-heap number is diregarded. + // RM provides for each VM a bitmask of heaps with each bit + // specifying the other peer that can use the partition. + // Each bit set to one can be enumerated, such that the bit + // with lowest significance is enumerated with one. + // 'ivcHeapNumber' parameter specifies this enumeration value. + // This value is used to uniquely identify a heap shared between + // two particular VMs. + // Illustration: + // bitmask: 1 1 0 1 0 = 0x1A + // possible 'ivcHeapNumber' values: 3, 2, 1 + NvV32 status; // [OUT] - returned NVOS32* status code, see below STATUS* defines + NvU64 total NV_ALIGN_BYTES(8); // [OUT] - returned total size of heap + NvU64 free NV_ALIGN_BYTES(8); // [OUT] - returned free space available in heap + + union + { + // NVOS32_FUNCTION_ALLOC_DEPTH_WIDTH_HEIGHT + struct + { + NvU32 owner; // [IN] - memory owner ID + NvHandle hMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated) + NvU32 type; // [IN] - surface type, see below TYPE* defines + NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines + NvU32 depth; // [IN] - depth of surface in bits + NvU32 width; // [IN] - width of surface in pixels + NvU32 height; // [IN] - height of surface in pixels + NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 format; // [IN/OUT] - format requested, and format allocated + NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated + NvU32 zcullCovg; // [OUT] - zcull covg allocated + NvU32 partitionStride; // [IN/OUT] - 0 means "RM" chooses + NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated + NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on + NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset + NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit + NvP64 address NV_ALIGN_BYTES(8);// [OUT] - returned address + NvU64 rangeBegin NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range + NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive. + NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET) + } AllocDepthWidthHeight; + + // NVOS32_FUNCTION_ALLOC_SIZE + struct + { + NvU32 owner; // [IN] - memory owner ID + NvHandle hMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated) + NvU32 type; // [IN] - surface type, see below TYPE* defines + NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines + NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 format; // [IN/OUT] - format requested, and format allocated + NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated + NvU32 zcullCovg; // [OUT] - zcull covg allocated + NvU32 partitionStride; // [IN/OUT] - 0 means "RM" chooses + NvU32 width; // [IN] - width "hint" used for zcull region allocations + NvU32 height; // [IN] - height "hint" used for zcull region allocations + NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated + NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on + NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset + NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit + NvP64 address NV_ALIGN_BYTES(8);// [OUT] - returned address + NvU64 rangeBegin NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range + NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive. + NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET) + } AllocSize; + + // NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT + struct + { + NvU32 owner; // [IN] - memory owner ID + NvHandle hMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated) + NvU32 type; // [IN] - surface type, see below TYPE* defines + NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines + NvU32 height; // [IN] - height of surface in pixels + NvS32 pitch; // [IN/OUT] - desired pitch AND returned actual pitch allocated + NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 width; //[IN] - width of surface in pixels + NvU32 format; // [IN/OUT] - format requested, and format allocated + NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated + NvU32 zcullCovg; // [OUT] - zcull covg allocated + NvU32 partitionStride; // [IN/OUT] - 0 means "RM" chooses + NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated + NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on + NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset + NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit + NvP64 address NV_ALIGN_BYTES(8);// [OUT] - returned address + NvU64 rangeBegin NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range + NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive. + NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET) + } AllocTiledPitchHeight; + + // NVOS32_FUNCTION_FREE + struct + { + NvU32 owner; // [IN] - memory owner ID + NvHandle hMemory; // [IN] - unique memory handle + NvU32 flags; // [IN] - heap free flags (must be NVOS32_FREE_FLAGS_MEMORY_HANDLE_PROVIDED) + } Free; + + // NVOS32_FUNCTION_RELEASE_COMPR + struct + { + NvU32 owner; // [IN] - memory owner ID + NvU32 flags; // [IN] - must be NVOS32_RELEASE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED + NvHandle hMemory; // [IN] - unique memory handle (valid if _RELEASE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED + } ReleaseCompr; + + // NVOS32_FUNCTION_REACQUIRE_COMPR + struct + { + NvU32 owner; // [IN] - memory owner ID + NvU32 flags; // [IN] - must be NVOS32_REACQUIRE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED + NvHandle hMemory; // [IN] - unique memory handle (valid if _REACQUIRE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED + } ReacquireCompr; + + // NVOS32_FUNCTION_INFO + struct + { + NvU32 attr; // [IN] - memory heap attributes requested + NvU64 offset NV_ALIGN_BYTES(8); // [OUT] - base of largest free block + NvU64 size NV_ALIGN_BYTES(8); // [OUT] - size of largest free block + NvU64 base NV_ALIGN_BYTES(8); // [OUT] - returned heap phys base + } Info; + + // NVOS32_FUNCTION_DUMP + struct + { + NvU32 flags; // [IN] - see _DUMP_FLAGS + // [IN] - if NULL, numBlocks is the returned number of blocks in + // heap, else returns all blocks in eHeap + // if non-NULL points to a buffer that is at least numBlocks + // * sizeof(NVOS32_HEAP_DUMP_BLOCK) bytes. + NvP64 pBuffer NV_ALIGN_BYTES(8); + // [IN/OUT] - if pBuffer is NULL, will number of blocks in heap + // if pBuffer is non-NULL, is input containing the size of + // pBuffer in units of NVOS32_HEAP_DUMP_BLOCK. This must + // be greater than or equal to the number of blocks in the + // heap. + NvU32 numBlocks; + } Dump; + + // NVOS32_FUNCTION_DESTROY - no extra parameters needed + + // NVOS32_FUNCTION_ALLOC_SIZE_RANGE + struct + { + NvU32 owner; // [IN] - memory owner ID + NvHandle hMemory; // [IN] - unique memory handle + NvU32 type; // [IN] - surface type, see below TYPE* defines + NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines + NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 format; // [IN/OUT] - format requested, and format allocated + NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated + NvU32 zcullCovg; // [OUT] - zcull covg allocated + NvU32 partitionStride; // [IN/OUT] - 0 means "RM" chooses + NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated + NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on + NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset + NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit + NvU64 rangeBegin NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range + NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive. + NvP64 address NV_ALIGN_BYTES(8);// [OUT] - returned address + NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET) + } AllocSizeRange; + + // additions for Longhorn +#define NVAL_MAX_BANKS (4) +#define NVAL_MAP_DIRECTION 0:0 +#define NVAL_MAP_DIRECTION_DOWN 0x00000000 +#define NVAL_MAP_DIRECTION_UP 0x00000001 + + // NVOS32_FUNCTION_GET_MEM_ALIGNMENT + struct + { + NvU32 alignType; // Input + NvU32 alignAttr; + NvU32 alignInputFlags; + NvU64 alignSize NV_ALIGN_BYTES(8); + NvU32 alignHeight; + NvU32 alignWidth; + NvU32 alignPitch; + NvU32 alignPad; + NvU32 alignMask; + NvU32 alignOutputFlags[NVAL_MAX_BANKS]; // We could compress this information but it is probably not that big of a deal + NvU32 alignBank[NVAL_MAX_BANKS]; + NvU32 alignKind; + NvU32 alignAdjust; // Output -- If non-zero the amount we need to adjust the offset + NvU32 alignAttr2; + } AllocHintAlignment; + + struct + { + NvU32 allocOwner; // [IN] - memory owner ID + NvHandle allochMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated) + NvU32 flags; + NvU32 allocType; // Input + NvU32 allocAttr; + NvU32 allocInputFlags; + NvU64 allocSize NV_ALIGN_BYTES(8); + NvU32 allocHeight; + NvU32 allocWidth; + NvU32 allocPitch; + NvU32 allocMask; + NvU32 allocComprCovg; + NvU32 allocZcullCovg; + NvP64 bindResultFunc NV_ALIGN_BYTES(8); // BindResultFunc + NvP64 pHandle NV_ALIGN_BYTES(8); + NvHandle hResourceHandle; // Handle to RM container + NvU32 retAttr; // Output Indicates the resources that we allocated + NvU32 kind; + NvU64 osDeviceHandle NV_ALIGN_BYTES(8); + NvU32 allocAttr2; + NvU32 retAttr2; // Output Indicates the resources that we allocated + NvU64 allocAddr NV_ALIGN_BYTES(8); + // [out] from GMMU_COMPR_INFO in drivers/common/shared/inc/mmu/gmmu_fmt.h + struct + { + NvU32 compPageShift; + NvU32 compressedKind; + NvU32 compTagLineMin; + NvU32 compPageIndexLo; + NvU32 compPageIndexHi; + NvU32 compTagLineMultiplier; + } comprInfo; + // [out] fallback uncompressed kind. + NvU32 uncompressedKind; + } HwAlloc; + + // NVOS32_FUNCTION_HW_FREE + struct + { + NvHandle hResourceHandle; // Handle to RM Resource Info + NvU32 flags; // Indicate if HW Resources and/or Memory + } HwFree; +// Updated interface check. +#define NV_RM_OS32_ALLOC_OS_DESCRIPTOR_WITH_OS32_ATTR 1 + + // NVOS32_FUNCTION_ALLOC_OS_DESCRIPTOR + struct + { + NvHandle hMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated) + NvU32 type; // [IN] - surface type, see below TYPE* defines + NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines + NvU32 attr; // [IN] - attributes for memory placement/properties, see below + NvU32 attr2; // [IN] - attributes GPU_CACHEABLE + NvP64 descriptor NV_ALIGN_BYTES(8); // [IN] - descriptor address + NvU64 limit NV_ALIGN_BYTES(8); // [IN] - allocated size -1 + NvU32 descriptorType; // [IN] - descriptor type(Virtual | nvmap Handle) + } AllocOsDesc; + + } data; +} NVOS32_PARAMETERS; + +typedef struct +{ + NvU32 owner; // owner id - NVOS32_BLOCK_TYPE_FREE or defined by client during heap_alloc + NvU32 format; // arch specific format/kind + NvU64 begin NV_ALIGN_BYTES(8); // start of allocated memory block + NvU64 align NV_ALIGN_BYTES(8); // actual start of usable memory, aligned to chip specific boundary + NvU64 end NV_ALIGN_BYTES(8); // end of usable memory. end - align + 1 = size of block +} NVOS32_HEAP_DUMP_BLOCK; + + +#define NVOS32_DELETE_RESOURCES_ALL 0 + +// type field +#define NVOS32_TYPE_IMAGE 0 +#define NVOS32_TYPE_DEPTH 1 +#define NVOS32_TYPE_TEXTURE 2 +#define NVOS32_TYPE_VIDEO 3 +#define NVOS32_TYPE_FONT 4 +#define NVOS32_TYPE_CURSOR 5 +#define NVOS32_TYPE_DMA 6 +#define NVOS32_TYPE_INSTANCE 7 +#define NVOS32_TYPE_PRIMARY 8 +#define NVOS32_TYPE_ZCULL 9 +#define NVOS32_TYPE_UNUSED 10 +#define NVOS32_TYPE_SHADER_PROGRAM 11 +#define NVOS32_TYPE_OWNER_RM 12 +#define NVOS32_TYPE_NOTIFIER 13 +#define NVOS32_TYPE_RESERVED 14 +#define NVOS32_TYPE_PMA 15 +#define NVOS32_TYPE_STENCIL 16 +#define NVOS32_NUM_MEM_TYPES 17 + +// Surface attribute field - bitmask of requested attributes the surface +// should have. +// This value is updated to reflect what was actually allocated, and so this +// field must be checked after every allocation to determine what was +// allocated. Pass in the ANY tags to indicate that RM should fall back but +// still succeed the alloc. +// for example, if tiled_any is passed in, but no tile ranges are available, +// RM will allocate normal memory and indicate that in the returned attr field. +// Each returned attribute will have the REQUIRED field set if that attribute +// applies to the allocated surface. + +#define NVOS32_ATTR_NONE 0x00000000 + +#define NVOS32_ATTR_DEPTH 2:0 +#define NVOS32_ATTR_DEPTH_UNKNOWN 0x00000000 +#define NVOS32_ATTR_DEPTH_8 0x00000001 +#define NVOS32_ATTR_DEPTH_16 0x00000002 +#define NVOS32_ATTR_DEPTH_24 0x00000003 +#define NVOS32_ATTR_DEPTH_32 0x00000004 +#define NVOS32_ATTR_DEPTH_64 0x00000005 +#define NVOS32_ATTR_DEPTH_128 0x00000006 + +#define NVOS32_ATTR_COMPR_COVG 3:3 +#define NVOS32_ATTR_COMPR_COVG_DEFAULT 0x00000000 +#define NVOS32_ATTR_COMPR_COVG_PROVIDED 0x00000001 + +// Surface description - number of AA samples +// This number should only reflect AA done in hardware, not in software. For +// example, OpenGL's 8x AA mode is a mix of 2x hardware multisample and 2x2 +// software supersample. +// OpenGL should specify ATTR_AA_SAMPLES of 2 in this case, not 8, because +// the hardware will be programmed to run in 2x AA mode. +// Note that X_VIRTUAL_Y means X real samples with Y samples total (i.e. Y +// does not indicate the number of virtual samples). For instance, what +// arch and HW describe as NV_PGRAPH_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 +// corresponds to NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_16 here. + +#define NVOS32_ATTR_AA_SAMPLES 7:4 +#define NVOS32_ATTR_AA_SAMPLES_1 0x00000000 +#define NVOS32_ATTR_AA_SAMPLES_2 0x00000001 +#define NVOS32_ATTR_AA_SAMPLES_4 0x00000002 +#define NVOS32_ATTR_AA_SAMPLES_4_ROTATED 0x00000003 +#define NVOS32_ATTR_AA_SAMPLES_6 0x00000004 +#define NVOS32_ATTR_AA_SAMPLES_8 0x00000005 +#define NVOS32_ATTR_AA_SAMPLES_16 0x00000006 +#define NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_8 0x00000007 +#define NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_16 0x00000008 +#define NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_16 0x00000009 +#define NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_32 0x0000000A + +// Tiled region +#define NVOS32_ATTR_TILED 9:8 +#define NVOS32_ATTR_TILED_NONE 0x00000000 +#define NVOS32_ATTR_TILED_REQUIRED 0x00000001 +#define NVOS32_ATTR_TILED_ANY 0x00000002 +#define NVOS32_ATTR_TILED_DEFERRED 0x00000003 + +// Zcull region (NV40 and up) +// If ATTR_ZCULL is REQUIRED or ANY and ATTR_DEPTH is UNKNOWN, the +// allocation will fail. +// If ATTR_DEPTH or ATTR_AA_SAMPLES is not accurate, erroneous rendering +// may result. +#define NVOS32_ATTR_ZCULL 11:10 +#define NVOS32_ATTR_ZCULL_NONE 0x00000000 +#define NVOS32_ATTR_ZCULL_REQUIRED 0x00000001 +#define NVOS32_ATTR_ZCULL_ANY 0x00000002 +#define NVOS32_ATTR_ZCULL_SHARED 0x00000003 + +// Compression (NV20 and up) +// If ATTR_COMPR is REQUIRED or ANY and ATTR_DEPTH is UNKNOWN, the +// allocation will fail. +// If ATTR_DEPTH or ATTR_AA_SAMPLES is not accurate, performance will +// suffer heavily +#define NVOS32_ATTR_COMPR 13:12 +#define NVOS32_ATTR_COMPR_NONE 0x00000000 +#define NVOS32_ATTR_COMPR_REQUIRED 0x00000001 +#define NVOS32_ATTR_COMPR_ANY 0x00000002 +#define NVOS32_ATTR_COMPR_PLC_REQUIRED NVOS32_ATTR_COMPR_REQUIRED +#define NVOS32_ATTR_COMPR_PLC_ANY NVOS32_ATTR_COMPR_ANY +#define NVOS32_ATTR_COMPR_DISABLE_PLC_ANY 0x00000003 + +// Format +// _BLOCK_LINEAR is only available for nv50+. +#define NVOS32_ATTR_FORMAT 17:16 +// Macros representing the low/high bits of NVOS32_ATTR_FORMAT +// bit range. These provide direct access to the range limits +// without needing to split the low:high representation via +// ternary operator, thereby avoiding MISRA 14.3 violation. +#define NVOS32_ATTR_FORMAT_LOW_FIELD 16 +#define NVOS32_ATTR_FORMAT_HIGH_FIELD 17 +#define NVOS32_ATTR_FORMAT_PITCH 0x00000000 +#define NVOS32_ATTR_FORMAT_SWIZZLED 0x00000001 +#define NVOS32_ATTR_FORMAT_BLOCK_LINEAR 0x00000002 + +#define NVOS32_ATTR_Z_TYPE 18:18 +#define NVOS32_ATTR_Z_TYPE_FIXED 0x00000000 +#define NVOS32_ATTR_Z_TYPE_FLOAT 0x00000001 + +#define NVOS32_ATTR_ZS_PACKING 21:19 +#define NVOS32_ATTR_ZS_PACKING_S8 0x00000000 // Z24S8 and S8 share definition +#define NVOS32_ATTR_ZS_PACKING_Z24S8 0x00000000 +#define NVOS32_ATTR_ZS_PACKING_S8Z24 0x00000001 +#define NVOS32_ATTR_ZS_PACKING_Z32 0x00000002 +#define NVOS32_ATTR_ZS_PACKING_Z24X8 0x00000003 +#define NVOS32_ATTR_ZS_PACKING_X8Z24 0x00000004 +#define NVOS32_ATTR_ZS_PACKING_Z32_X24S8 0x00000005 +#define NVOS32_ATTR_ZS_PACKING_X8Z24_X24S8 0x00000006 +#define NVOS32_ATTR_ZS_PACKING_Z16 0x00000007 +// NOTE: ZS packing and color packing fields are overlaid +#define NVOS32_ATTR_COLOR_PACKING NVOS32_ATTR_ZS_PACKING +#define NVOS32_ATTR_COLOR_PACKING_A8R8G8B8 0x00000000 +#define NVOS32_ATTR_COLOR_PACKING_X8R8G8B8 0x00000001 + + + +// +// For virtual allocs to choose page size for the region. Specifying +// _DEFAULT will select a virtual page size that allows for a surface +// to be mixed between video and system memory and allow the surface +// to be migrated between video and system memory. For tesla chips, +// 4KB will be used. For fermi chips with dual page tables, a virtual +// address with both page tables will be used. +// +// For physical allocation on chips with page swizzle this field is +// used to select the page swizzle. This later also sets the virtual +// page size, but does not have influence over selecting a migratable +// virtual address. That must be selected when mapping the physical +// memory. +// +// BIG_PAGE = 64 KB on PASCAL +// = 64 KB or 128 KB on pre_PASCAL chips +// +// HUGE_PAGE = 2 MB on PASCAL+ +// = 2 MB or 512 MB on AMPERE+ +// = not supported on pre_PASCAL chips. +// +// To request for a HUGE page size, +// set NVOS32_ATTR_PAGE_SIZE to _HUGE and NVOS32_ATTR2_PAGE_SIZE_HUGE to +// the desired size. +// +#define NVOS32_ATTR_PAGE_SIZE 24:23 +#define NVOS32_ATTR_PAGE_SIZE_DEFAULT 0x00000000 +#define NVOS32_ATTR_PAGE_SIZE_4KB 0x00000001 +#define NVOS32_ATTR_PAGE_SIZE_BIG 0x00000002 +#define NVOS32_ATTR_PAGE_SIZE_HUGE 0x00000003 + +#define NVOS32_ATTR_LOCATION 26:25 +#define NVOS32_ATTR_LOCATION_VIDMEM 0x00000000 +#define NVOS32_ATTR_LOCATION_PCI 0x00000001 +#define NVOS32_ATTR_LOCATION_AGP 0x00000002 +#define NVOS32_ATTR_LOCATION_ANY 0x00000003 + +// +// _DEFAULT implies _CONTIGUOUS for video memory currently, but +// may be changed to imply _NONCONTIGUOUS in the future. +// _ALLOW_NONCONTIGUOUS enables falling back to the noncontiguous +// vidmem allocator if contig allocation fails. +// +#define NVOS32_ATTR_PHYSICALITY 28:27 +#define NVOS32_ATTR_PHYSICALITY_DEFAULT 0x00000000 +#define NVOS32_ATTR_PHYSICALITY_NONCONTIGUOUS 0x00000001 +#define NVOS32_ATTR_PHYSICALITY_CONTIGUOUS 0x00000002 +#define NVOS32_ATTR_PHYSICALITY_ALLOW_NONCONTIGUOUS 0x00000003 + +#define NVOS32_ATTR_COHERENCY 31:29 +#define NVOS32_ATTR_COHERENCY_UNCACHED 0x00000000 +#define NVOS32_ATTR_COHERENCY_CACHED 0x00000001 +#define NVOS32_ATTR_COHERENCY_WRITE_COMBINE 0x00000002 +#define NVOS32_ATTR_COHERENCY_WRITE_THROUGH 0x00000003 +#define NVOS32_ATTR_COHERENCY_WRITE_PROTECT 0x00000004 +#define NVOS32_ATTR_COHERENCY_WRITE_BACK 0x00000005 + +// ATTR2 fields +#define NVOS32_ATTR2_NONE 0x00000000 + +// +// DEFAULT - Let lower level drivers pick optimal page kind. +// PREFER_NO_ZBC - Prefer other types of compression over ZBC when +// selecting page kind. +// PREFER_ZBC - Prefer ZBC over other types of compression when +// selecting page kind. +// REQUIRE_ONLY_ZBC - Require a page kind that enables ZBC but disables +// other types of compression (i.e. 2C page kind). +// INVALID - Aliases REQUIRE_ONLY_ZBC, which is not supported +// by all RM implementations. +// +#define NVOS32_ATTR2_ZBC 1:0 +#define NVOS32_ATTR2_ZBC_DEFAULT 0x00000000 +#define NVOS32_ATTR2_ZBC_PREFER_NO_ZBC 0x00000001 +#define NVOS32_ATTR2_ZBC_PREFER_ZBC 0x00000002 +#define NVOS32_ATTR2_ZBC_REQUIRE_ONLY_ZBC 0x00000003 +#define NVOS32_ATTR2_ZBC_INVALID 0x00000003 + +// +// DEFAULT - Highest performance cache policy that is coherent with the highest +// performance CPU mapping. Typically this is gpu cached for video +// memory and gpu uncached for system memory. +// YES - Enable gpu caching if supported on this surface type. For system +// memory this will not be coherent with direct CPU mappings. +// NO - Disable gpu caching if supported on this surface type. +// INVALID - Clients should never set YES and NO simultaneously. +// +#define NVOS32_ATTR2_GPU_CACHEABLE 3:2 +#define NVOS32_ATTR2_GPU_CACHEABLE_DEFAULT 0x00000000 +#define NVOS32_ATTR2_GPU_CACHEABLE_YES 0x00000001 +#define NVOS32_ATTR2_GPU_CACHEABLE_NO 0x00000002 +#define NVOS32_ATTR2_GPU_CACHEABLE_INVALID 0x00000003 + +// +// DEFAULT - GPU-dependent cache policy +// YES - Enable gpu caching for p2p mem +// NO - Disable gpu caching for p2p mem +// +#define NVOS32_ATTR2_P2P_GPU_CACHEABLE 5:4 +#define NVOS32_ATTR2_P2P_GPU_CACHEABLE_DEFAULT 0x00000000 +#define NVOS32_ATTR2_P2P_GPU_CACHEABLE_YES 0x00000001 +#define NVOS32_ATTR2_P2P_GPU_CACHEABLE_NO 0x00000002 + +// This applies to virtual allocs only. See NVOS46_FLAGS_32BIT_POINTER. +#define NVOS32_ATTR2_32BIT_POINTER 6:6 +#define NVOS32_ATTR2_32BIT_POINTER_DISABLE 0x00000000 +#define NVOS32_ATTR2_32BIT_POINTER_ENABLE 0x00000001 + +// +// Indicates address conversion to be used, which affects what +// pitch alignment needs to be used +// +#define NVOS32_ATTR2_TILED_TYPE 7:7 +#define NVOS32_ATTR2_TILED_TYPE_LINEAR 0x00000000 +#define NVOS32_ATTR2_TILED_TYPE_XY 0x00000001 + +// +// Force SMMU mapping on GPU physical allocation in Tegra +// SMMU mapping for GPU physical allocation decided internally by RM +// This attribute provide an override to RM policy for verification purposes. +// +#define NVOS32_ATTR2_SMMU_ON_GPU 10:8 +#define NVOS32_ATTR2_SMMU_ON_GPU_DEFAULT 0x00000000 +#define NVOS32_ATTR2_SMMU_ON_GPU_DISABLE 0x00000001 +#define NVOS32_ATTR2_SMMU_ON_GPU_ENABLE 0x00000002 + +// +// Make comptag allocation aligned to compression cacheline size. +// Specifying this attribute will make RM allocate comptags worth an entire +// comp cacheline. The allocation will be offset aligned to number of comptags/comp cacheline. +// +#define NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN 11:11 +#define NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_OFF 0x0 +#define NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_ON 0x1 +#define NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_DEFAULT \ + NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_OFF + +// Allocation preferred in high or low priority memory +#define NVOS32_ATTR2_PRIORITY 13:12 +#define NVOS32_ATTR2_PRIORITY_DEFAULT 0x0 +#define NVOS32_ATTR2_PRIORITY_HIGH 0x1 +#define NVOS32_ATTR2_PRIORITY_LOW 0x2 + +// PMA: Allocation is an RM internal allocation (RM-only) +#define NVOS32_ATTR2_INTERNAL 14:14 +#define NVOS32_ATTR2_INTERNAL_NO 0x0 +#define NVOS32_ATTR2_INTERNAL_YES 0x1 + +// Allocate 2C instead of 2CZ +#define NVOS32_ATTR2_PREFER_2C 15:15 +#define NVOS32_ATTR2_PREFER_2C_NO 0x00000000 +#define NVOS32_ATTR2_PREFER_2C_YES 0x00000001 + +// Allocation used by display engine; RM verifies display engine has enough +// address bits or remapper available. +#define NVOS32_ATTR2_NISO_DISPLAY 16:16 +#define NVOS32_ATTR2_NISO_DISPLAY_NO 0x00000000 +#define NVOS32_ATTR2_NISO_DISPLAY_YES 0x00000001 + +// +// !!WARNING!!! +// +// This flag is introduced as a temporary WAR to enable color compression +// without ZBC. +// +// This dangerous flag can be used by UMDs to instruct RM to skip the zbc +// table refcounting that RM does today, when the chosen PTE kind has ZBC +// support. +// +// Currently we do not have a safe per process zbc slot management and +// refcounting mechanism between RM and UMD and hence, any process can +// access any other process's zbc entry in the global zbc table (without mask) +// Inorder to flush the ZBC table for slot reuse RM cannot track which +// process is using which zbc slot. Hence RM has a global refcount for the +// zbc table to flush and reuse the entries if the PTE kind supports zbc. +// +// This scheme poses a problem if there are apps that are persistent such as +// the desktop components that can have color compression enabled which will +// always keep the refcount active. Since these apps can live without +// ZBC, UMD can disable ZBC using masks. +// +// In such a case, if UMD so chooses to disable ZBC, this flag should be used +// to skip refcounting as by default RM would refcount the ZBC table. +// +// NOTE: There is no way for RM to enforce/police this, and we totally rely +// on UMD to use a zbc mask in the pushbuffer method to prevent apps from +// accessing the ZBC table. +// +#define NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT 17:17 +#define NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_NO 0x00000000 +#define NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_YES 0x00000001 + +// Allocation requires ISO bandwidth guarantees +#define NVOS32_ATTR2_ISO 18:18 +#define NVOS32_ATTR2_ISO_NO 0x00000000 +#define NVOS32_ATTR2_ISO_YES 0x00000001 + +// +// Turn off blacklist feature for video memory allocation +// This attribute should be used only by Kernel client (KMD), to mask +// the blacklisted pages for the allocation. This is done so that the clients +// will manage the above masked blacklisted pages after the allocation. It will +// return to RM's pool after the allocation was free-d.RmVidHeapCtrl returns +// NV_ERR_INSUFFICIENT_PERMISSIONS if it is being called by non-kernel clients. +// + +// TODO: Project ReLingo - This term is marked for deletion. Use PAGE_OFFLINING. +#define NVOS32_ATTR2_BLACKLIST 19:19 +#define NVOS32_ATTR2_BLACKLIST_ON 0x00000000 +#define NVOS32_ATTR2_BLACKLIST_OFF 0x00000001 +#define NVOS32_ATTR2_PAGE_OFFLINING 19:19 +#define NVOS32_ATTR2_PAGE_OFFLINING_ON 0x00000000 +#define NVOS32_ATTR2_PAGE_OFFLINING_OFF 0x00000001 + +// +// For virtual allocs to choose the HUGE page size for the region. +// NVOS32_ATTR_PAGE_SIZE must be set to _HUGE to use this. +// Currently, the default huge page is 2MB, so a request with _DEFAULT +// set will always be interpreted as 2MB. +// Not supported on pre_AMPERE chips. +// +#define NVOS32_ATTR2_PAGE_SIZE_HUGE 21:20 +#define NVOS32_ATTR2_PAGE_SIZE_HUGE_DEFAULT 0x00000000 +#define NVOS32_ATTR2_PAGE_SIZE_HUGE_2MB 0x00000001 +#define NVOS32_ATTR2_PAGE_SIZE_HUGE_512MB 0x00000002 + +// Allow read-only or read-write user CPU mappings +#define NVOS32_ATTR2_PROTECTION_USER 22:22 +#define NVOS32_ATTR2_PROTECTION_USER_READ_WRITE 0x00000000 +#define NVOS32_ATTR2_PROTECTION_USER_READ_ONLY 0x00000001 + +// Allow read-only or read-write device mappings +#define NVOS32_ATTR2_PROTECTION_DEVICE 23:23 +#define NVOS32_ATTR2_PROTECTION_DEVICE_READ_WRITE 0x00000000 +#define NVOS32_ATTR2_PROTECTION_DEVICE_READ_ONLY 0x00000001 + +// +// Force the allocation to go to guest subheap. +// This flag is used by vmiop plugin to allocate from GPA +// +#define NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP 27:27 +#define NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_NO 0x00000000 +#define NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_YES 0x00000001 + +/** + * NVOS32 ALLOC_FLAGS + * + * NVOS32_ALLOC_FLAGS_IGNORE_BANK_PLACEMENT + * + * NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_UP + * + * NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN + * + * NVOS32_ALLOC_FLAGS_FORCE_ALIGN_HOST_PAGE + * + * NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE + * + * NVOS32_ALLOC_FLAGS_BANK_HINT + * + * NVOS32_ALLOC_FLAGS_BANK_FORCE + * + * NVOS32_ALLOC_FLAGS_ALIGNMENT_HINT + * + * NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE + * + * NVOS32_ALLOC_FLAGS_BANK_GROW_UP + * Only relevant if bank_hint or bank_force are set + * + * NVOS32_ALLOC_FLAGS_BANK_GROW_DOWN + * Only relevant if bank_hint or bank_force are set + * + * NVOS32_ALLOC_FLAGS_LAZY + * Lazy allocation (deferred pde, pagetable creation) + * + * NVOS32_ALLOC_FLAGS_NO_SCANOUT + * Set if surface will never be scanned out + * + * NVOS32_ALLOC_FLAGS_PITCH_FORCE + * Fail alloc if supplied pitch is not aligned + * + * NVOS32_ALLOC_FLAGS_MEMORY_HANDLE_PROVIDED + * Memory handle provided to be associated with this allocation + * + * NVOS32_ALLOC_FLAGS_MAP_NOT_REQUIRED + * By default memory is mapped into the CPU address space + * + * NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM + * Allocate persistent video memory + * + * NVOS32_ALLOC_FLAGS_USE_BEGIN_END + * Use rangeBegin & rangeEnd fields in allocs other than size/range + * + * NVOS32_ALLOC_FLAGS_TURBO_CIPHER_ENCRYPTED + * Allocate TurboCipher encrypted region + * + * NVOS32_ALLOC_FLAGS_VIRTUAL + * Allocate virtual memory address space + * + * NVOS32_ALLOC_FLAGS_FORCE_INTERNAL_INDEX + * Force allocation internal index + * + * NVOS32_ALLOC_FLAGS_ZCULL_COVG_SPECIFIED + * This flag is depreciated and allocations will fail. + * + * NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED + * Must be used with NVOS32_ALLOC_FLAGS_VIRTUAL. + * Page tables for this allocation will be managed outside of RM. + * + * NVOS32_ALLOC_FLAGS_FORCE_DEDICATED_PDE + * + * NVOS32_ALLOC_FLAGS_PROTECTED + * Allocate in a protected memory region if available + * + * NVOS32_ALLOC_FLAGS_KERNEL_MAPPING_MAP + * Map kernel os descriptor + * + * NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE + * On WDDM all address spaces are created with MINIMIZE_PTETABLE_SIZE + * to reduce the overhead of private address spaces per application, + * at the cost of holes in the virtual address space. + * + * Shaders have short pointers that are required to be within a + * GPU dependent 32b range. + * + * MAXIMIZE_ADDRESS_SPACE will reverse the MINIMIZE_PTE_TABLE_SIZE + * flag with certain restrictions: + * - This flag only has an effect when the allocation has the side + * effect of creating a new PDE. It does not affect existing PDEs. + * - The first few PDEs of the address space are kept minimum to allow + * small applications to use fewer resources. + * - By default this operations on the 0-4GB address range. + * - If USE_BEGIN_END is specified the setting will apply to the + * specified range instead of the first 4GB. + * + * NVOS32_ALLOC_FLAGS_SPARSE + * Denote that a virtual address range is "sparse". Must be used with + * NVOS32_ALLOC_FLAGS_VIRTUAL. Creation of a "sparse" virtual address range + * denotes that an unmapped virtual address range should "not" fault but simply + * return 0's. + * + * NVOS32_ALLOC_FLAGS_ALLOCATE_KERNEL_PRIVILEGED + * This a special flag that can be used only by kernel(root) clients + * to allocate memory out of a protected region of the address space + * If this flag is set by non kernel clients then the allocation will + * fail. + * + * NVOS32_ALLOC_FLAGS_SKIP_RESOURCE_ALLOC + * + * NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY + * If new pagetable need to be allocated prefer them in sysmem (if supported by the gpu) + * + * NVOS32_ALLOC_FLAGS_SKIP_ALIGN_PAD + * As per KMD request to eliminate extra allocation + * + * NVOS32_ALLOC_FLAGS_WPR1 + * Allocate in a WPR1 region if available + * + * NVOS32_ALLOC_FLAGS_ZCULL_DONT_ALLOCATE_SHARED_1X + * If using zcull sharing and this surface is fsaa, then don't allocate an additional non-FSAA region. + * + * NVOS32_ALLOC_FLAGS_WPR2 + * Allocate in a WPR1 region if available + */ +#define NVOS32_ALLOC_FLAGS_IGNORE_BANK_PLACEMENT 0x00000001 +#define NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_UP 0x00000002 +#define NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN 0x00000004 +#define NVOS32_ALLOC_FLAGS_FORCE_ALIGN_HOST_PAGE 0x00000008 +#define NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE 0x00000010 +#define NVOS32_ALLOC_FLAGS_BANK_HINT 0x00000020 +#define NVOS32_ALLOC_FLAGS_BANK_FORCE 0x00000040 +#define NVOS32_ALLOC_FLAGS_ALIGNMENT_HINT 0x00000080 +#define NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE 0x00000100 +#define NVOS32_ALLOC_FLAGS_BANK_GROW_UP 0x00000000 +#define NVOS32_ALLOC_FLAGS_BANK_GROW_DOWN 0x00000200 +#define NVOS32_ALLOC_FLAGS_LAZY 0x00000400 +// unused 0x00000800 +#define NVOS32_ALLOC_FLAGS_NO_SCANOUT 0x00001000 +#define NVOS32_ALLOC_FLAGS_PITCH_FORCE 0x00002000 +#define NVOS32_ALLOC_FLAGS_MEMORY_HANDLE_PROVIDED 0x00004000 +#define NVOS32_ALLOC_FLAGS_MAP_NOT_REQUIRED 0x00008000 +#define NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM 0x00010000 +#define NVOS32_ALLOC_FLAGS_USE_BEGIN_END 0x00020000 +#define NVOS32_ALLOC_FLAGS_TURBO_CIPHER_ENCRYPTED 0x00040000 +#define NVOS32_ALLOC_FLAGS_VIRTUAL 0x00080000 +#define NVOS32_ALLOC_FLAGS_FORCE_INTERNAL_INDEX 0x00100000 +#define NVOS32_ALLOC_FLAGS_ZCULL_COVG_SPECIFIED 0x00200000 +#define NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED 0x00400000 +#define NVOS32_ALLOC_FLAGS_FORCE_DEDICATED_PDE 0x00800000 +#define NVOS32_ALLOC_FLAGS_PROTECTED 0x01000000 +#define NVOS32_ALLOC_FLAGS_KERNEL_MAPPING_MAP 0x02000000 // TODO BUG 2488679: fix alloc flag aliasing +#define NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE 0x02000000 +#define NVOS32_ALLOC_FLAGS_SPARSE 0x04000000 +#define NVOS32_ALLOC_FLAGS_USER_READ_ONLY 0x04000000 // TODO BUG 2488682: remove this after KMD transition +#define NVOS32_ALLOC_FLAGS_DEVICE_READ_ONLY 0x08000000 // TODO BUG 2488682: remove this after KMD transition +#define NVOS32_ALLOC_FLAGS_ALLOCATE_KERNEL_PRIVILEGED 0x08000000 +#define NVOS32_ALLOC_FLAGS_SKIP_RESOURCE_ALLOC 0x10000000 +#define NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY 0x20000000 +#define NVOS32_ALLOC_FLAGS_SKIP_ALIGN_PAD 0x40000000 +#define NVOS32_ALLOC_FLAGS_WPR1 0x40000000 // TODO BUG 2488672: fix alloc flag aliasing +#define NVOS32_ALLOC_FLAGS_ZCULL_DONT_ALLOCATE_SHARED_1X 0x80000000 +#define NVOS32_ALLOC_FLAGS_WPR2 0x80000000 // TODO BUG 2488672: fix alloc flag aliasing + +// Internal flags used for RM's allocation paths +#define NVOS32_ALLOC_INTERNAL_FLAGS_CLIENTALLOC 0x00000001 // RM internal flags - not sure if this should be exposed even. Keeping it here. +#define NVOS32_ALLOC_INTERNAL_FLAGS_SKIP_SCRUB 0x00000004 // RM internal flags - not sure if this should be exposed even. Keeping it here. +#define NVOS32_ALLOC_FLAGS_MAXIMIZE_4GB_ADDRESS_SPACE NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE // Legacy name + +// +// Bitmask of flags that are only valid for virtual allocations. +// +#define NVOS32_ALLOC_FLAGS_VIRTUAL_ONLY ( \ + NVOS32_ALLOC_FLAGS_VIRTUAL | \ + NVOS32_ALLOC_FLAGS_LAZY | \ + NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED | \ + NVOS32_ALLOC_FLAGS_SPARSE | \ + NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE | \ + NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY ) + +// COMPR_COVG_* allows for specification of what compression resources +// are required (_MIN) and necessary (_MAX). Default behavior is for +// RM to provide as much as possible, including none if _ANY is allowed. +// Values for min/max are (0-100, a %) * _COVG_SCALE (so max value is +// 100*100==10000). _START is used to specify the % offset into the +// region to begin the requested coverage. +// _COVG_BITS allows specification of the number of comptags per ROP tile. +// A value of 0 is default and allows RM to choose based upon MMU/FB rules. +// All other values for _COVG_BITS are arch-specific. +// Note: NVOS32_ATTR_COMPR_COVG_PROVIDED must be set for this feature +// to be available (verif-only). +#define NVOS32_ALLOC_COMPR_COVG_SCALE 10 +#define NVOS32_ALLOC_COMPR_COVG_BITS 1:0 +#define NVOS32_ALLOC_COMPR_COVG_BITS_DEFAULT 0x00000000 +#define NVOS32_ALLOC_COMPR_COVG_BITS_1 0x00000001 +#define NVOS32_ALLOC_COMPR_COVG_BITS_2 0x00000002 +#define NVOS32_ALLOC_COMPR_COVG_BITS_4 0x00000003 +#define NVOS32_ALLOC_COMPR_COVG_MAX 11:2 +#define NVOS32_ALLOC_COMPR_COVG_MIN 21:12 +#define NVOS32_ALLOC_COMPR_COVG_START 31:22 + + +// Note: NVOS32_ALLOC_FLAGS_ZCULL_COVG_SPECIFIED must be set for this feature +// to be enabled. +// If FALLBACK_ALLOW is set, a fallback from LOW_RES_Z or LOW_RES_ZS +// to HIGH_RES_Z is allowed if the surface can't be fully covered. +#define NVOS32_ALLOC_ZCULL_COVG_FORMAT 3:0 +#define NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_Z 0x00000000 +#define NVOS32_ALLOC_ZCULL_COVG_FORMAT_HIGH_RES_Z 0x00000002 +#define NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_ZS 0x00000003 +#define NVOS32_ALLOC_ZCULL_COVG_FALLBACK 4:4 +#define NVOS32_ALLOC_ZCULL_COVG_FALLBACK_DISALLOW 0x00000000 +#define NVOS32_ALLOC_ZCULL_COVG_FALLBACK_ALLOW 0x00000001 + + +// _ALLOC_COMPTAG_OFFSET allows the caller to specify the starting +// offset for the comptags for a given surface, primarily for test only. +// To specify an offset, set _USAGE_FIXED or _USAGE_MIN in conjunction +// with _START. +// +// _USAGE_FIXED sets a surface's comptagline to start at the given +// starting value. If the offset has already been assigned, then +// the alloc call fails. +// +// _USAGE_MIN sets a surface's comptagline to start at the given +// starting value or higher, depending on comptagline availability. +// In this case, if the offset has already been assigned, the next +// available comptagline (in increasing order) will be assigned. +// +// For Fermi, up to 2^17 comptags may be allowed, but the actual, +// usable limit depends on the size of the compbit backing store. +// +// For Pascal, up to 2 ^ 18 comptags may be allowed +// From Turing. up to 2 ^ 20 comptags may be allowed +// +// See also field ctagOffset in struct NVOS32_PARAMETERS. +#define NVOS32_ALLOC_COMPTAG_OFFSET_START 19:0 +#define NVOS32_ALLOC_COMPTAG_OFFSET_START_DEFAULT 0x00000000 +#define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE 31:30 +#define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_DEFAULT 0x00000000 +#define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_OFF 0x00000000 +#define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_FIXED 0x00000001 +#define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_MIN 0x00000002 + + +// REALLOC flags field +#define NVOS32_REALLOC_FLAGS_GROW_ALLOCATION 0x00000000 +#define NVOS32_REALLOC_FLAGS_SHRINK_ALLOCATION 0x00000001 +#define NVOS32_REALLOC_FLAGS_REALLOC_UP 0x00000000 // towards/from high memory addresses +#define NVOS32_REALLOC_FLAGS_REALLOC_DOWN 0x00000002 // towards/from memory address 0 + +// RELEASE_COMPR, REACQUIRE_COMPR flags field +#define NVOS32_RELEASE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED 0x000000001 + +#define NVOS32_REACQUIRE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED 0x000000001 + + +// FREE flags field +#define NVOS32_FREE_FLAGS_MEMORY_HANDLE_PROVIDED 0x00000001 + +// DUMP flags field +#define NVOS32_DUMP_FLAGS_TYPE 1:0 +#define NVOS32_DUMP_FLAGS_TYPE_FB 0x00000000 +#define NVOS32_DUMP_FLAGS_TYPE_CLIENT_PD 0x00000001 +#define NVOS32_DUMP_FLAGS_TYPE_CLIENT_VA 0x00000002 +#define NVOS32_DUMP_FLAGS_TYPE_CLIENT_VAPTE 0x00000003 + +#define NVOS32_BLOCK_TYPE_FREE 0xFFFFFFFF +#define NVOS32_INVALID_BLOCK_FREE_OFFSET 0xFFFFFFFF + +#define NVOS32_MEM_TAG_NONE 0x00000000 + +/* + * NV_CONTEXT_DMA_ALLOCATION_PARAMS - Allocation params to create context dma + through NvRmAlloc. + */ +typedef struct +{ + NvHandle hSubDevice; + NvV32 flags; + NvHandle hMemory; + NvU64 offset NV_ALIGN_BYTES(8); + NvU64 limit NV_ALIGN_BYTES(8); +} NV_CONTEXT_DMA_ALLOCATION_PARAMS; + +/* + * NV_MEMORY_ALLOCATION_PARAMS - Allocation params to create memory through + * NvRmAlloc. Flags are populated with NVOS32_ defines. + */ +typedef struct +{ + NvU32 owner; // [IN] - memory owner ID + NvU32 type; // [IN] - surface type, see below TYPE* defines + NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines + + NvU32 width; // [IN] - width of surface in pixels + NvU32 height; // [IN] - height of surface in pixels + NvS32 pitch; // [IN/OUT] - desired pitch AND returned actual pitch allocated + + NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated + + NvU32 format; // [IN/OUT] - format requested, and format allocated + NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated + NvU32 zcullCovg; // [OUT] - zcull covg allocated + + NvU64 rangeLo NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range + NvU64 rangeHi NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive. + + NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated + NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on + NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset + NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit + NvP64 address NV_ALIGN_BYTES(8); // [OUT] - returned address + + NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET) + NvHandle hVASpace; // [IN] - VASpace handle. Used when flag is VIRTUAL. + + NvU32 internalflags; // [IN] - internal flags to change allocation behaviors from internal paths + + NvU32 tag; // [IN] - memory tag used for debugging +} NV_MEMORY_ALLOCATION_PARAMS; + +/* + * NV_OS_DESC_MEMORY_ALLOCATION_PARAMS - Allocation params to create OS + * described memory through NvRmAlloc. Flags are populated with NVOS32_ defines. + */ +typedef struct +{ + NvU32 type; // [IN] - surface type, see below TYPE* defines + NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines + NvU32 attr; // [IN] - attributes for memory placement/properties, see below + NvU32 attr2; // [IN] - attributes GPU_CACHEABLE + NvP64 descriptor NV_ALIGN_BYTES(8); // [IN] - descriptor address + NvU64 limit NV_ALIGN_BYTES(8); // [IN] - allocated size -1 + NvU32 descriptorType; // [IN] - descriptor type(Virtual | nvmap Handle) + NvU32 tag; // [IN] - memory tag used for debugging +} NV_OS_DESC_MEMORY_ALLOCATION_PARAMS; + +/* + * NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS - Allocation params to create a memory + * object from user allocated video memory. Flags are populated with NVOS32_* + * defines. + */ +typedef struct +{ + NvU32 flags; // [IN] - allocation modifier flags, see NVOS02_FLAGS* defines + NvU64 physAddr NV_ALIGN_BYTES(8); // [IN] - physical address + NvU64 size NV_ALIGN_BYTES(8); // [IN] - mem size + NvU32 tag; // [IN] - memory tag used for debugging + NvBool bGuestAllocated; // [IN] - Set if memory is guest allocated (mapped by VMMU) +} NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS; + +/* + * NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS - Allocation params to create + * memory HW resources through NvRmAlloc. Flags are populated with NVOS32_ + * defines. + */ +typedef struct +{ + NvU32 owner; // [IN] - memory owner ID + NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines + NvU32 type; // [IN] - surface type, see below TYPE* defines + + NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated + NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated + + NvU32 height; + NvU32 width; + NvU32 pitch; + NvU32 alignment; + NvU32 comprCovg; + NvU32 zcullCovg; + + NvU32 kind; + + NvP64 bindResultFunc NV_ALIGN_BYTES(8); // BindResultFunc + NvP64 pHandle NV_ALIGN_BYTES(8); + NvU64 osDeviceHandle NV_ALIGN_BYTES(8); + NvU64 size NV_ALIGN_BYTES(8); + NvU64 allocAddr NV_ALIGN_BYTES(8); + + // [out] from GMMU_COMPR_INFO in drivers/common/shared/inc/mmu/gmmu_fmt.h + NvU32 compPageShift; + NvU32 compressedKind; + NvU32 compTagLineMin; + NvU32 compPageIndexLo; + NvU32 compPageIndexHi; + NvU32 compTagLineMultiplier; + + // [out] fallback uncompressed kind. + NvU32 uncompressedKind; + + NvU32 tag; // [IN] - memory tag used for debugging +} NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS; + +/* function OS33 */ +#define NV04_MAP_MEMORY (0x00000021) + +// Legacy map and unmap memory flags that don't use DRF_DEF scheme +#define NV04_MAP_MEMORY_FLAGS_NONE (0x00000000) +#define NV04_MAP_MEMORY_FLAGS_USER (0x00004000) + +// New map and unmap memory flags. These flags are used for both NvRmMapMemory +// and for NvRmUnmapMemory. + +// Mappings can have restricted permissions (read-only, write-only). Some +// RM implementations may choose to ignore these flags, or they may work +// only for certain memory spaces (system, AGP, video memory); in such cases, +// you may get a read/write mapping even if you asked for a read-only or +// write-only mapping. +#define NVOS33_FLAGS_ACCESS 1:0 +#define NVOS33_FLAGS_ACCESS_READ_WRITE (0x00000000) +#define NVOS33_FLAGS_ACCESS_READ_ONLY (0x00000001) +#define NVOS33_FLAGS_ACCESS_WRITE_ONLY (0x00000002) + +// Persistent mappings are no longer supported +#define NVOS33_FLAGS_PERSISTENT 4:4 +#define NVOS33_FLAGS_PERSISTENT_DISABLE (0x00000000) +#define NVOS33_FLAGS_PERSISTENT_ENABLE (0x00000001) + +// This flag is a hack to work around bug 150889. It disables the error +// checking in the RM that verifies that the client is not trying to map +// memory past the end of the memory object. This error checking needs to +// be shut off in some cases for a PAE bug workaround in certain kernels. +#define NVOS33_FLAGS_SKIP_SIZE_CHECK 8:8 +#define NVOS33_FLAGS_SKIP_SIZE_CHECK_DISABLE (0x00000000) +#define NVOS33_FLAGS_SKIP_SIZE_CHECK_ENABLE (0x00000001) + +// Normally, a mapping is created in the same memory space as the client -- in +// kernel space for a kernel RM client, or in user space for a user RM client. +// However, a kernel RM client can specify MEM_SPACE:USER to create a user-space +// mapping in the current RM client. +#define NVOS33_FLAGS_MEM_SPACE 14:14 +#define NVOS33_FLAGS_MEM_SPACE_CLIENT (0x00000000) +#define NVOS33_FLAGS_MEM_SPACE_USER (0x00000001) + +// The client can ask for direct memory mapping (i.e. no BAR1) if remappers and +// blocklinear are not required. RM can do direct mapping in this case if +// carveout is available. +// DEFAULT: Use direct mapping if available and no address/data translation +// is necessary; reflected otherwise +// DIRECT: Use direct mapping if available, even if some translation is +// necessary (the client is responsible for translation) +// REFLECTED: Always use reflected mapping +#define NVOS33_FLAGS_MAPPING 16:15 +#define NVOS33_FLAGS_MAPPING_DEFAULT (0x00000000) +#define NVOS33_FLAGS_MAPPING_DIRECT (0x00000001) +#define NVOS33_FLAGS_MAPPING_REFLECTED (0x00000002) + +// The client requests a fifo mapping but doesn't know the offset or length +// DEFAULT: Do error check length and offset +// ENABLE: Don't error check length and offset but have the RM fill them in +#define NVOS33_FLAGS_FIFO_MAPPING 17:17 +#define NVOS33_FLAGS_FIFO_MAPPING_DEFAULT (0x00000000) +#define NVOS33_FLAGS_FIFO_MAPPING_ENABLE (0x00000001) + +// The client can require that the CPU mapping be to a specific CPU address +// (akin to MAP_FIXED for mmap). +// DISABLED: RM will map the allocation at a CPU VA that RM selects. +// ENABLED: RM will map the allocation at the CPU VA specified by the address +// pass-back parameter to NvRmMapMemory +// NOTES: +// - Used for controlling CPU addresses in CUDA's unified CPU+GPU virtual +// address space +// - Only valid on NvRmMapMemory +// - Only implemented on Linux +#define NVOS33_FLAGS_MAP_FIXED 18:18 +#define NVOS33_FLAGS_MAP_FIXED_DISABLE (0x00000000) +#define NVOS33_FLAGS_MAP_FIXED_ENABLE (0x00000001) + +// The client can specify to the RM that the CPU virtual address range for an +// allocation should remain reserved after the allocation is unmapped. +// DISABLE: When this mapping is destroyed, RM will unmap the CPU virtual +// address space used by this allocation. On Linux this corresponds +// to calling munmap on the CPU VA region. +// ENABLE: When the map object is freed, RM will leave the CPU virtual +// address space used by allocation reserved. On Linux this means +// that RM will overwrite the previous mapping with an anonymous +// mapping of instead calling munmap. +// NOTES: +// - When combined with MAP_FIXED, this allows the client to exert +// significant control over the CPU heap +// - Used in CUDA's unified CPU+GPU virtual address space +// - Only valid on NvRmMapMemory (specifies RM's behavior whenever the +// mapping is destroyed, regardless of mechanism) +// - Only implemented on Linux +#define NVOS33_FLAGS_RESERVE_ON_UNMAP 19:19 +#define NVOS33_FLAGS_RESERVE_ON_UNMAP_DISABLE (0x00000000) +#define NVOS33_FLAGS_RESERVE_ON_UNMAP_ENABLE (0x00000001) + +// Systems with a coherent NVLINK2 connection between the CPU and GPU +// have the option of directly mapping video memory over that connection. +// During mapping you may specify a preference. +// +#define NVOS33_FLAGS_BUS 21:20 +#define NVOS33_FLAGS_BUS_ANY 0 +#define NVOS33_FLAGS_BUS_NVLINK_COHERENT 1 +#define NVOS33_FLAGS_BUS_PCIE 2 + +// Internal use only +#define NVOS33_FLAGS_OS_DESCRIPTOR 22:22 +#define NVOS33_FLAGS_OS_DESCRIPTOR_DISABLE (0x00000000) +#define NVOS33_FLAGS_OS_DESCRIPTOR_ENABLE (0x00000001) + +// +// For use in the linux mapping path. This flag sets the +// caching mode for pcie BAR mappings (from nv_memory_type.h). +// Internal use only. +// +#define NVOS33_FLAGS_CACHING_TYPE 25:23 +#define NVOS33_FLAGS_CACHING_TYPE_CACHED 0 +#define NVOS33_FLAGS_CACHING_TYPE_UNCACHED 1 +#define NVOS33_FLAGS_CACHING_TYPE_WRITECOMBINED 2 +#define NVOS33_FLAGS_CACHING_TYPE_WRITEBACK 5 +#define NVOS33_FLAGS_CACHING_TYPE_DEFAULT 6 +#define NVOS33_FLAGS_CACHING_TYPE_UNCACHED_WEAK 7 + +/* parameters */ +typedef struct +{ + NvHandle hClient; + NvHandle hDevice; // device or sub-device handle + NvHandle hMemory; // handle to memory object if provided -- NULL if not + NvU64 offset NV_ALIGN_BYTES(8); + NvU64 length NV_ALIGN_BYTES(8); + NvP64 pLinearAddress NV_ALIGN_BYTES(8); // pointer for returned address + NvU32 status; + NvU32 flags; +} NVOS33_PARAMETERS; + + +/* function OS34 */ +#define NV04_UNMAP_MEMORY (0x00000022) + +/* parameters */ +typedef struct +{ + NvHandle hClient; + NvHandle hDevice; + NvHandle hMemory; + NvP64 pLinearAddress NV_ALIGN_BYTES(8); // ptr to virtual address of mapped memory + NvU32 status; + NvU32 flags; +} NVOS34_PARAMETERS; + +/* function OS38 */ +#define NV04_ACCESS_REGISTRY (0x00000026) + +/* parameter values */ +#define NVOS38_ACCESS_TYPE_READ_DWORD 1 +#define NVOS38_ACCESS_TYPE_WRITE_DWORD 2 +#define NVOS38_ACCESS_TYPE_READ_BINARY 6 +#define NVOS38_ACCESS_TYPE_WRITE_BINARY 7 + +#define NVOS38_MAX_REGISTRY_STRING_LENGTH 256 +#define NVOS38_MAX_REGISTRY_BINARY_LENGTH 256 + +/* parameters */ +typedef struct +{ + NvHandle hClient; + NvHandle hObject; + NvV32 AccessType; + + NvV32 DevNodeLength; + NvP64 pDevNode NV_ALIGN_BYTES(8); + + NvV32 ParmStrLength; + NvP64 pParmStr NV_ALIGN_BYTES(8); + + NvV32 BinaryDataLength; + NvP64 pBinaryData NV_ALIGN_BYTES(8); + + NvV32 Data; + NvV32 Entry; + NvV32 status; +} NVOS38_PARAMETERS; + +#define NV04_ALLOC_CONTEXT_DMA (0x00000027) + +/* parameter values are the same as NVOS03 -- not repeated here */ + +/* parameters */ +typedef struct +{ + NvHandle hObjectParent; + NvHandle hSubDevice; + NvHandle hObjectNew; + NvV32 hClass; + NvV32 flags; + NvU32 selector; + NvHandle hMemory; + NvU64 offset NV_ALIGN_BYTES(8); + NvU64 limit NV_ALIGN_BYTES(8); + NvV32 status; +} NVOS39_PARAMETERS; + + +#define NV04_GET_EVENT_DATA (0x00000028) + +typedef struct +{ + NvHandle hObject; + NvV32 NotifyIndex; + + // + // Holds same information as that of nvgputypes.h::NvNotification's + // info32 and info16. + // + NvV32 info32; + NvU16 info16; +} NvUnixEvent; + +/* parameters */ +typedef struct +{ + NvP64 pEvent NV_ALIGN_BYTES(8); + NvV32 MoreEvents; + NvV32 status; +} NVOS41_PARAMETERS; + +/* function NVOS43 -- deleted 4/09 */ +/* #define NV04_UNIFIED_FREE (0x0000002B) */ + + +#define NVSIM01_BUS_XACT (0x0000002C) + +/* parameters */ +typedef struct +{ + NvHandle hClient; // n/a currently + NvHandle hDevice; // n/a currently + NvU32 offset; // phy bus offset + NvU32 bar; // ~0 := phy addr, {0..2} specify gpu bar + NvU32 bytes; // # of bytes + NvU32 write; // 0 := read request + NvU32 data; // in/out based upon 'write' + NvU32 status; +} NVOS2C_PARAMETERS; + +/* function NVOS2D -- deleted 4/09 */ +/* #define NVSIM01_BUS_GET_IFACES (0x0000002D) */ + + +/* function OS46 */ +#define NV04_MAP_MEMORY_DMA (0x0000002E) + +/* parameter values */ +#define NVOS46_FLAGS_ACCESS 1:0 +#define NVOS46_FLAGS_ACCESS_READ_WRITE (0x00000000) +#define NVOS46_FLAGS_ACCESS_READ_ONLY (0x00000001) +#define NVOS46_FLAGS_ACCESS_WRITE_ONLY (0x00000002) + +// +// Compute shaders support both 32b and 64b pointers. This allows mappings +// to be restricted to the bottom 4GB of the address space. How _DISABLE +// is handled is chip specific and may force a pointer above 4GB. +// +#define NVOS46_FLAGS_32BIT_POINTER 2:2 +#define NVOS46_FLAGS_32BIT_POINTER_DISABLE (0x00000000) +#define NVOS46_FLAGS_32BIT_POINTER_ENABLE (0x00000001) + +#define NVOS46_FLAGS_PAGE_KIND 3:3 +#define NVOS46_FLAGS_PAGE_KIND_PHYSICAL (0x00000000) +#define NVOS46_FLAGS_PAGE_KIND_VIRTUAL (0x00000001) + +#define NVOS46_FLAGS_CACHE_SNOOP 4:4 +#define NVOS46_FLAGS_CACHE_SNOOP_DISABLE (0x00000000) +#define NVOS46_FLAGS_CACHE_SNOOP_ENABLE (0x00000001) + +// The client requests a CPU kernel mapping so that SW class could use it +// DEFAULT: Don't map CPU address +// ENABLE: Map CPU address +#define NVOS46_FLAGS_KERNEL_MAPPING 5:5 +#define NVOS46_FLAGS_KERNEL_MAPPING_NONE (0x00000000) +#define NVOS46_FLAGS_KERNEL_MAPPING_ENABLE (0x00000001) + +// +// Compute shader access control. +// GPUs that support this feature set the NV0080_CTRL_DMA_CAPS_SHADER_ACCESS_SUPPORTED +// property. These were first supported in Kepler. _DEFAULT will match the ACCESS field. +// +#define NVOS46_FLAGS_SHADER_ACCESS 7:6 +#define NVOS46_FLAGS_SHADER_ACCESS_DEFAULT (0x00000000) +#define NVOS46_FLAGS_SHADER_ACCESS_READ_ONLY (0x00000001) +#define NVOS46_FLAGS_SHADER_ACCESS_WRITE_ONLY (0x00000002) +#define NVOS46_FLAGS_SHADER_ACCESS_READ_WRITE (0x00000003) + +// +// How the PAGE_SIZE field is interpreted is architecture specific. +// +// On Curie chips it is ignored. +// +// On Tesla it is used to guide is used to select which type PDE +// to use. By default the RM will select 4KB for system memory +// and BIG (64KB) for video memory. BOTH is not supported. +// +// Likewise on Fermi this used to select the PDE type. Fermi cannot +// mix page sizes to a single mapping so the page size is determined +// at surface alloation time. 4KB or BIG may be specified but they +// must match the page size selected at allocation time. DEFAULT +// allows the RM to select either a single page size or both PDE, +// while BOTH forces the RM to select a dual page size PDE. +// +// BIG_PAGE = 64 KB on PASCAL +// = 64 KB or 128 KB on pre_PASCAL chips +// +// HUGE_PAGE = 2 MB on PASCAL +// = not supported on pre_PASCAL chips. +// +#define NVOS46_FLAGS_PAGE_SIZE 11:8 +#define NVOS46_FLAGS_PAGE_SIZE_DEFAULT (0x00000000) +#define NVOS46_FLAGS_PAGE_SIZE_4KB (0x00000001) +#define NVOS46_FLAGS_PAGE_SIZE_BIG (0x00000002) +#define NVOS46_FLAGS_PAGE_SIZE_BOTH (0x00000003) +#define NVOS46_FLAGS_PAGE_SIZE_HUGE (0x00000004) + +// Some systems allow the device to use the system L3 cache when accessing the +// system memory. For example, the iGPU on T19X can allocate from the system L3 +// provided the SoC L3 cache is configured for device allocation. +// +// NVOS46_FLAGS_SYSTEM_L3_ALLOC_DEFAULT - Use the default L3 allocation +// policy. When using this policy, device memory access will be coherent with +// non-snooping devices such as the display on Tegra. +// +// NVOS46_FLAGS_SYSTEM_L3_ALLOC_ENABLE_HINT - Enable L3 allocation if possible. +// When L3 allocation is enabled, device memory access may be cached, and the +// memory access will be coherent only with other snoop-enabled access. This +// flag is a hint and will be ignored if the system does not support L3 +// allocation for the device. NVOS46_FLAGS_CACHE_SNOOP_ENABLE must also be set +// for this flag to be effective. +// +// Note: This flag is implemented only by rmapi_tegra. It is not implemented by +// Resman. +// +#define NVOS46_FLAGS_SYSTEM_L3_ALLOC 13:13 +#define NVOS46_FLAGS_SYSTEM_L3_ALLOC_DEFAULT (0x00000000) +#define NVOS46_FLAGS_SYSTEM_L3_ALLOC_ENABLE_HINT (0x00000001) + +#define NVOS46_FLAGS_DMA_OFFSET_GROWS 14:14 +#define NVOS46_FLAGS_DMA_OFFSET_GROWS_UP (0x00000000) +#define NVOS46_FLAGS_DMA_OFFSET_GROWS_DOWN (0x00000001) + +// +// DMA_OFFSET_FIXED is overloaded for two purposes. +// +// 1. For CTXDMA mappings that use DMA_UNICAST_REUSE_ALLOC_FALSE, +// DMA_OFFSET_FIXED_TRUE indicates to use the dmaOffset parameter +// for a fixed address allocation out of the VA space heap. +// DMA_OFFSET_FIXED_FALSE indicates dmaOffset input will be ignored. +// +// 2. For CTXDMA mappings that use DMA_UNICAST_REUSE_ALLOC_TRUE and +// for *ALL* non-CTXDMA mappings, DMA_OFFSET_FIXED_TRUE indicates +// to treat the input dmaOffset as an absolute virtual address +// instead of an offset relative to the virtual allocation being +// mapped into. Whether relative or absolute, the resulting +// virtual address *must* be contained within the specified +// virtual allocation. +// +// Internally, it is also required that the virtual address be aligned +// to the page size of the mapping (obviously cannot map sub-pages). +// For client flexibility the physical offset does not require page alignment. +// This is handled by adding the physical misalignment +// (internally called pteAdjust) to the returned virtual address. +// The *input* dmaOffset can account for this pteAdjust (or not), +// but the returned virtual address always will. +// +#define NVOS46_FLAGS_DMA_OFFSET_FIXED 15:15 +#define NVOS46_FLAGS_DMA_OFFSET_FIXED_FALSE (0x00000000) +#define NVOS46_FLAGS_DMA_OFFSET_FIXED_TRUE (0x00000001) + +#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP 19:16 +#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_DEFAULT (0x00000000) +#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_1 (0x00000001) +#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_2 (0x00000002) +#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_4 (0x00000003) +#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_8 (0x00000004) +#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_16 (0x00000005) +#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_32 (0x00000006) +#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_64 (0x00000007) +#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_128 (0x00000008) +#define NVOS46_FLAGS_P2P 27:20 + +#define NVOS46_FLAGS_P2P_ENABLE 21:20 +#define NVOS46_FLAGS_P2P_ENABLE_NO (0x00000000) +#define NVOS46_FLAGS_P2P_ENABLE_YES (0x00000001) +#define NVOS46_FLAGS_P2P_ENABLE_NONE NVOS46_FLAGS_P2P_ENABLE_NO +#define NVOS46_FLAGS_P2P_ENABLE_SLI NVOS46_FLAGS_P2P_ENABLE_YES +#define NVOS46_FLAGS_P2P_ENABLE_NOSLI (0x00000002) +// Subdevice ID. Reserved 3 bits for the possibility of 8-way SLI +#define NVOS46_FLAGS_P2P_SUBDEVICE_ID 24:22 +#define NVOS46_FLAGS_P2P_SUBDEV_ID_SRC NVOS46_FLAGS_P2P_SUBDEVICE_ID +#define NVOS46_FLAGS_P2P_SUBDEV_ID_TGT 27:25 +#define NVOS46_FLAGS_TLB_LOCK 28:28 +#define NVOS46_FLAGS_TLB_LOCK_DISABLE (0x00000000) +#define NVOS46_FLAGS_TLB_LOCK_ENABLE (0x00000001) +#define NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC 29:29 +#define NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_FALSE (0x00000000) +#define NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_TRUE (0x00000001) +// +// This flag must be used with caution. Improper use can leave stale entries in the TLB, +// and allow access to memory no longer owned by the RM client or cause page faults. +// Also see corresponding flag for NvUnmapMemoryDma. +// +#define NVOS46_FLAGS_DEFER_TLB_INVALIDATION 31:31 +#define NVOS46_FLAGS_DEFER_TLB_INVALIDATION_FALSE (0x00000000) +#define NVOS46_FLAGS_DEFER_TLB_INVALIDATION_TRUE (0x00000001) + +/* parameters */ +typedef struct +{ + NvHandle hClient; // [IN] client handle + NvHandle hDevice; // [IN] device handle for mapping + NvHandle hDma; // [IN] dma handle for mapping + NvHandle hMemory; // [IN] memory handle for mapping + NvU64 offset NV_ALIGN_BYTES(8); // [IN] offset of region + NvU64 length NV_ALIGN_BYTES(8); // [IN] limit of region + NvV32 flags; // [IN] flags + NvU64 dmaOffset NV_ALIGN_BYTES(8); // [OUT] offset of mapping + // [IN] if FLAGS_DMA_OFFSET_FIXED_TRUE + // *OR* hDma is NOT a CTXDMA handle + // (see NVOS46_FLAGS_DMA_OFFSET_FIXED) + NvV32 status; // [OUT] status +} NVOS46_PARAMETERS; + + +/* function OS47 */ +#define NV04_UNMAP_MEMORY_DMA (0x0000002F) + +#define NVOS47_FLAGS_DEFER_TLB_INVALIDATION 0:0 +#define NVOS47_FLAGS_DEFER_TLB_INVALIDATION_FALSE (0x00000000) +#define NVOS47_FLAGS_DEFER_TLB_INVALIDATION_TRUE (0x00000001) + +/* parameters */ +typedef struct +{ + NvHandle hClient; // [IN] client handle + NvHandle hDevice; // [IN] device handle for mapping + NvHandle hDma; // [IN] dma handle for mapping + NvHandle hMemory; // [IN] memory handle for mapping + NvV32 flags; // [IN] flags + NvU64 dmaOffset NV_ALIGN_BYTES(8); // [IN] dma offset from NV04_MAP_MEMORY_DMA + NvV32 status; // [OUT] status +} NVOS47_PARAMETERS; + + +#define NV04_BIND_CONTEXT_DMA (0x00000031) +/* parameters */ +typedef struct +{ + NvHandle hClient; // [IN] client handle + NvHandle hChannel; // [IN] channel handle for binding + NvHandle hCtxDma; // [IN] ctx dma handle for binding + NvV32 status; // [OUT] status +} NVOS49_PARAMETERS; + + +/* function OS54 */ +#define NV04_CONTROL (0x00000036) + +#define NVOS54_FLAGS_NONE (0x00000000) +#define NVOS54_FLAGS_IRQL_RAISED (0x00000001) +#define NVOS54_FLAGS_LOCK_BYPASS (0x00000002) +#define NVOS54_FLAGS_FINN_SERIALIZED (0x00000004) + +/* parameters */ +typedef struct +{ + NvHandle hClient; + NvHandle hObject; + NvV32 cmd; + NvU32 flags; + NvP64 params NV_ALIGN_BYTES(8); + NvU32 paramsSize; + NvV32 status; +} NVOS54_PARAMETERS; + +/* RM Control header + * + * Replacement for NVOS54_PARAMETERS where embedded pointers are not allowed. + * Input layout for user space RM Control calls should be: + * + * +--- NVOS63_PARAMETERS ---+--- RM Control parameters ---+ + * + * NVOS63_PARAMETERS::paramsSize is the size of RM Control parameters + * + */ +typedef struct +{ + NvHandle hClient; // [IN] client handle + NvHandle hObject; // [IN] object handle + NvV32 cmd; // [IN] control command ID + NvU32 paramsSize; // [IN] size in bytes of the RM Control parameters + NvV32 status; // [OUT] status +} NVOS63_PARAMETERS; + + +/* function OS55 */ +#define NV04_DUP_OBJECT (0x00000037) + +/* parameters */ +typedef struct +{ + NvHandle hClient; // [IN] destination client handle + NvHandle hParent; // [IN] parent of new object + NvHandle hObject; // [INOUT] destination (new) object handle + NvHandle hClientSrc; // [IN] source client handle + NvHandle hObjectSrc; // [IN] source (old) object handle + NvU32 flags; // [IN] flags + NvU32 status; // [OUT] status +} NVOS55_PARAMETERS; + +#define NV04_DUP_HANDLE_FLAGS_NONE (0x00000000) +#define NV04_DUP_HANDLE_FLAGS_REJECT_KERNEL_DUP_PRIVILEGE (0x00000001) // If set, prevents an RM kernel client from duping unconditionally + // NOTE: Do not declare a NV04_DUP_HANDLE_FLAGS_* value of 0x00000008 + // until Bug 2859347 is resolved! This is due to conflicting usage + // of RS_RES_DUP_PARAMS_INTERNAL.flags to pass + // NVOS32_ALLOC_INTERNAL_FLAGS_FLA_MEMORY to an object constructor. + +/* function OS56 */ +#define NV04_UPDATE_DEVICE_MAPPING_INFO (0x00000038) + +/* parameters */ +typedef struct +{ + NvHandle hClient; + NvHandle hDevice; + NvHandle hMemory; + NvP64 pOldCpuAddress NV_ALIGN_BYTES(8); + NvP64 pNewCpuAddress NV_ALIGN_BYTES(8); + NvV32 status; +} NVOS56_PARAMETERS; + +/* function OS57 */ +#define NV04_SHARE (0x0000003E) + +/* parameters */ +typedef struct +{ + NvHandle hClient; // [IN] owner client handle + NvHandle hObject; // [IN] resource to share + RS_SHARE_POLICY sharePolicy; // [IN] share policy entry + NvU32 status; // [OUT] status +} NVOS57_PARAMETERS; + +/* parameters */ +typedef struct +{ + NvU32 deviceReference; + NvU32 head; + NvU32 state; + NvU8 forceMonitorState; + NvU8 bForcePerfBiosLevel; + NvU8 bIsD3HotTransition; // [OUT] To tell client if it's a D3Hot transition + NvU32 fastBootPowerState; +} NVPOWERSTATE_PARAMETERS, *PNVPOWERSTATE_PARAMETERS; + + /***************************************************************************\ +|* Object Allocation Parameters *| + \***************************************************************************/ + +// GR engine creation parameters +typedef struct { + NvU32 version; // set to 0x2 + NvU32 flags; // input param from a rm client (no flags are currently defined) + NvU32 size; // sizeof(NV_GR_ALLOCATION_PARAMETERS) + NvU32 caps; // output param for a rm client - class dependent +} NV_GR_ALLOCATION_PARAMETERS; + +// +// NvAlloc parameters for NV03_DEVICE_XX class +// hClientShare +// For NV50+ this can be set to virtual address space for this +// device. On previous chips this field is ignored. There are +// three possible settings +// NV01_NULL_OBJECT - Use the default global VA space +// Handle to current client - Create a new private address space +// Handle to another client - Attach to other clients address space +// flags +// MAP_PTE_GLOBALLY Deprecated. +// MINIMIZE_PTETABLE_SIZE Pass hint to DMA HAL to use partial page +// tables. Depending on allocation pattern +// this may actually use more instance memory. +// RETRY_PTE_ALLOC_IN_SYS Fallback to PTEs allocation in sysmem. This +// is now enabled by default. +// VASPACE_SIZE Honor vaSpaceSize field. +// +// MAP_PTE Deprecated. +// +// VASPACE_IS_MIRRORED This flag will tell RM to create a mirrored +// kernel PDB for the address space associated +// with this device. When this flag is set +// the address space covered by the top PDE +// is restricted and cannot be allocated out of. +// +// +// VASPACE_BIG_PAGE_SIZE_64k ***Warning this flag will be deprecated do not use***** +// VASPACE_BIG_PAGE_SIZE_128k This flag will choose the big page size of the VASPace +// to 64K/128k if the system supports a configurable size. +// If the system does not support a configurable size then +// defaults will be chosen. +// If the user sets both these bits then this API will fail. +// +// SHARED_MANAGEMENT +// *** Warning: This will be deprecated - see NV_VASPACE_ALLOCATION_PARAMETERS. *** +// +// +// hTargetClient/hTargetDevice +// Deprecated. Can be deleted once client code has removed references. +// +// vaBase +// *** Warning: This will be deprecated - see NV_VASPACE_ALLOCATION_PARAMETERS. *** +// +// vaSpaceSize +// Set the size of the VA space used for this client if allocating +// a new private address space. Is expressed as a size such as +// (1<<32) for a 32b address space. Reducing the size of the address +// space allows the dma chip specific code to reduce the instance memory +// used for page tables. +// +// vaMode +// The vaspace allocation mode. There are three modes supported: +// 1. SINGLE_VASPACE +// An old abstraction that provides a single VA space under a +// device and it's allocated implicityly when an object requires a VA +// space. Typically, this VA space is also shared across clients. +// +// 2. OPTIONAL_MULTIPLE_VASPACES +// Global + multiple private va spaces. In this mode, the old abstraction, +// a single vaspace under a device that is allocated implicitly is still +// being supported. A private VA space is an entity under a device, which/ +// cannot be shared with other clients, but multiple channels under the +// same device can still share a private VA space. +// Private VA spaces (class:90f1,FERMI_VASPACE_A) can be allocated as +// objects through RM APIs. This mode requires the users to know what they +// are doing in terms of using VA spaces. Page fault can easily occur if +// one is not careful with a mixed of an implicit VA space and multiple +// VA spaces. +// +// 3. MULTIPLE_VASPACES +// In this mode, all VA spaces have to be allocated explicitly through RM +// APIs and users have to specify which VA space to use for each object. +// This case prevents users to use context dma, which is not supported and +// can be misleading if used. Therefore, it's more a safeguard mode to +// prevent people making mistakes that are hard to debug. +// +// DEFAULT MODE: 2. OPTIONAL_MULTIPLE_VASPACES +// +// See NV0080_ALLOC_PARAMETERS for allocation parameter structure. +// + +#define NV_DEVICE_ALLOCATION_SZNAME_MAXLEN 128 +#define NV_DEVICE_ALLOCATION_FLAGS_NONE (0x00000000) +#define NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE_GLOBALLY (0x00000001) +#define NV_DEVICE_ALLOCATION_FLAGS_MINIMIZE_PTETABLE_SIZE (0x00000002) +#define NV_DEVICE_ALLOCATION_FLAGS_RETRY_PTE_ALLOC_IN_SYS (0x00000004) +#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SIZE (0x00000008) +#define NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE (0x00000010) +#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_IS_TARGET (0x00000020) +#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SHARED_MANAGEMENT (0x00000100) +#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_64k (0x00000200) +#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_128k (0x00000400) +#define NV_DEVICE_ALLOCATION_FLAGS_RESTRICT_RESERVED_VALIMITS (0x00000800) + +/* + *TODO: Delete this flag once CUDA moves to the ctrl call + */ +#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_IS_MIRRORED (0x00000040) + +// XXX NV_DEVICE_ALLOCATION_FLAGS_VASPACE_PTABLE_PMA_MANAGED should not +// should not be exposed to clients. It should be the default RM +// behavior. +// +// Until it is made the default, certain clients such as OpenGL +// might still need PTABLE allocations to go through PMA, so this +// flag has been temporary exposed. +// +// See bug 1880192 +#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_PTABLE_PMA_MANAGED (0x00001000) + +// +// Indicates this device is being created by guest and requires a +// KernelHostVgpuDeviceApi creation in client. +// +#define NV_DEVICE_ALLOCATION_FLAGS_HOST_VGPU_DEVICE (0x00002000) + +// +// Indicates this device is being created for VGPU plugin use. +// Requires a HostVgpuDevice handle to indicate the guest on which +// this plugin operates. +// +#define NV_DEVICE_ALLOCATION_FLAGS_PLUGIN_CONTEXT (0x00004000) + +// +// For clients using unlinked SLI to catch allocations attempts on secondary GPUs +// not accompanied by a fixed offset. +// +#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_REQUIRE_FIXED_OFFSET (0x00008000) + +#define NV_DEVICE_ALLOCATION_VAMODE_OPTIONAL_MULTIPLE_VASPACES (0x00000000) +#define NV_DEVICE_ALLOCATION_VAMODE_SINGLE_VASPACE (0x00000001) +#define NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES (0x00000002) + + +#define NV_CHANNELGPFIFO_NOTIFICATION_TYPE_ERROR 0x00000000 +#define NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN 0x00000001 +#define NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1 2 +#define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_VALUE 14:0 +#define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS 15:15 +#define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_TRUE 0x1 +#define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_FALSE 0x0 + +typedef struct +{ + NvV32 channelInstance; // One of the n channel instances of a given channel type. + // Note that core channel has only one instance + // while all others have two (one per head). + NvHandle hObjectBuffer; // ctx dma handle for DMA push buffer + NvHandle hObjectNotify; // ctx dma handle for an area (of type NvNotification defined in sdk/nvidia/inc/nvtypes.h) where RM can write errors/notifications + NvU32 offset; // Initial offset for put/get, usually zero. + NvP64 pControl NV_ALIGN_BYTES(8); // pControl gives virt addr of UDISP GET/PUT regs + + NvU32 flags; +#define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB 1:1 +#define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_YES 0x00000000 +#define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_NO 0x00000001 + +} NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS; + +typedef struct +{ + NvV32 channelInstance; // One of the n channel instances of a given channel type. + // All PIO channels have two instances (one per head). + NvHandle hObjectNotify; // ctx dma handle for an area (of type NvNotification defined in sdk/nvidia/inc/nvtypes.h) where RM can write errors. + NvP64 pControl NV_ALIGN_BYTES(8); // pControl gives virt addr of control region for PIO channel +} NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS; + +// Used for allocating a channel group +typedef struct +{ + NvHandle hObjectError; // Error notifier for TSG + NvHandle hObjectEccError; // ECC Error notifier for TSG + NvHandle hVASpace; // VA space handle for TSG + NvU32 engineType; // Engine to which all channels in this TSG are associated with + NvBool bIsCallingContextVgpuPlugin; +} NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS; + +/* +* @params: +* @engineId : Engine to which the software runlist be associated with. +* @maxTSGs : Maximum number of TSG entries that will be submitted in this software runlist +* The size of the runlist buffer will be determined by +* 2 * // double buffer +* maxTSGs * // determined by KMD +* maxChannelPerTSG * // Determined by RM +* sizeof(RunlistEntry) // Determined by HW format +* @qosIntrEnableMask: QOS Interrupt bitmask that needs to be enabled for the SW runlist defined below. +*/ +typedef struct +{ + NvU32 engineId; //(IN) + NvU32 maxTSGs; //(IN) // Size of the RM could return error if the request cannot be accommodated. + NvU32 qosIntrEnableMask; //(IN) // Bitmask for QOS interrupts that needs to be enabled +} NV_SWRUNLIST_ALLOCATION_PARAMS; + +#define NV_SWRUNLIST_QOS_INTR_NONE 0x00000000 +#define NV_SWRUNLIST_QOS_INTR_RUNLIST_AND_ENG_IDLE_ENABLE NVBIT32(0) +#define NV_SWRUNLIST_QOS_INTR_RUNLIST_IDLE_ENABLE NVBIT32(1) +#define NV_SWRUNLIST_QOS_INTR_RUNLIST_ACQUIRE_ENABLE NVBIT32(2) +#define NV_SWRUNLIST_QOS_INTR_RUNLIST_ACQUIRE_AND_ENG_IDLE_ENABLE NVBIT32(3) + +typedef struct +{ + NvU32 size; + NvU32 caps; +} NV_ME_ALLOCATION_PARAMETERS; + +typedef struct +{ + NvU32 size; + NvU32 prohibitMultipleInstances; + NvU32 engineInstance; // Select NVDEC0 or NVDEC1 or NVDEC2 +} NV_BSP_ALLOCATION_PARAMETERS; + +// +// These are referenced by mdiag mods tests, but do not appear to be used during +// in the RM any longer +// +#define NV_VP_ALLOCATION_FLAGS_STANDARD_UCODE (0x00000000) +#define NV_VP_ALLOCATION_FLAGS_STATIC_UCODE (0x00000001) +#define NV_VP_ALLOCATION_FLAGS_DYNAMIC_UCODE (0x00000002) + +// +// NV_VP_ALLOCATION_PARAMETERS.flags +// +// NV_VP_ALLOCATION_FLAGS_AVP_CLIENT are used by Tegra to specify if +// the current allocation with be used by Video or Audio +// +#define NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_VIDEO (0x00000000) +#define NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_AUDIO (0x00000001) + +typedef struct +{ + NvU32 size; + NvU32 caps; + NvU32 flags; + NvU32 altUcode; + NvP64 rawUcode NV_ALIGN_BYTES(8); + NvU32 rawUcodeSize; + NvU32 numSubClasses; + NvU32 numSubSets; + NvP64 subClasses NV_ALIGN_BYTES(8); + NvU32 prohibitMultipleInstances; + NvP64 pControl NV_ALIGN_BYTES(8); // Used by Tegra to return a mapping to NvE276Control + NvHandle hMemoryCmdBuffer NV_ALIGN_BYTES(8); // Used by Tegra to specify cmd buffer + NvU64 offset NV_ALIGN_BYTES(8); // Used by Tegra to specify an offset into the cmd buffer + +} NV_VP_ALLOCATION_PARAMETERS; + +typedef struct +{ + NvU32 size; + NvU32 prohibitMultipleInstances; +} NV_PPP_ALLOCATION_PARAMETERS; + +typedef struct +{ + NvU32 size; + NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of MSENC? + NvU32 engineInstance; // Select MSENC/NVENC0 or NVENC1 or NVENC2 +} NV_MSENC_ALLOCATION_PARAMETERS; + +typedef struct +{ + NvU32 size; + NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of SEC2? +} NV_SEC2_ALLOCATION_PARAMETERS; + +typedef struct +{ + NvU32 size; + NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of NVJPG? + NvU32 engineInstance; +} NV_NVJPG_ALLOCATION_PARAMETERS; + +typedef struct +{ + NvU32 size; + NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of OFA? +} NV_OFA_ALLOCATION_PARAMETERS; + +#define NV04_ADD_VBLANK_CALLBACK (0x0000003D) + +#include "class/cl9010.h" // for OSVBLANKCALLBACKPROC + +/* parameters */ +/* NOTE: the "void* pParm's" below are ok (but unfortunate) since this interface + can only be used by other kernel drivers which must share the same ptr-size */ +typedef struct +{ + NvHandle hClient; // [IN] client handle + NvHandle hDevice; // [IN] device handle for mapping + NvHandle hVblank; // [IN] Vblank handle for control + OSVBLANKCALLBACKPROC pProc; // Routine to call at vblank time + + NvV32 LogicalHead; // Logical Head + void *pParm1; + void *pParm2; + NvU32 bAdd; // Add or Delete + NvV32 status; // [OUT] status +} NVOS61_PARAMETERS; + +/** + * @brief NvAlloc parameters for VASPACE classes + * + * Used to create a new private virtual address space. + * + * index + * Tegra: With TEGRA_VASPACE_A, index specifies the IOMMU + * virtual address space to be created. Based on the + * index, RM/NVMEM will decide the HW ASID to be used with + * this VA Space. "index" takes values from the + * NVMEM_CLIENT_* defines in + * "drivers/common/inc/tegra/memory/ioctl.h". + * + * Big GPU: With FERMI_VASPACE_A, see NV_VASPACE_ALLOCATION_INDEX_GPU_*. + * + * flags + * MINIMIZE_PTETABLE_SIZE Pass hint to DMA HAL to use partial page tables. + * Depending on allocation pattern this may actually + * use more instance memory. + * + * RETRY_PTE_ALLOC_IN_SYS Fallback to PTEs allocation in sysmem. This is now + * enabled by default. + * + * SHARED_MANAGEMENT + * Indicates management of the VA space is shared with another + * component (e.g. driver layer, OS, etc.). + * + * The initial VA range from vaBase (inclusive) through vaSize (exclusive) + * is managed by RM. The range must be aligned to a top-level PDE's VA + * coverage since backing page table levels for this range are managed by RM. + * All normal RM virtual memory management APIs work within this range. + * + * An external component can manage the remaining VA ranges, + * from 0 (inclusive) to vaBase (exclusive) and from vaSize (inclusive) up to the + * maximum VA limit supported by HW. + * Management of these ranges includes VA sub-allocation and the + * backing lower page table levels. + * + * The top-level page directory is special since it is a shared resource. + * Management of the page directory is as follows: + * 1. Initially RM allocates a page directory for RM-managed PDEs. + * 2. The external component may create a full page directory and commit it + * with NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY. + * This will copy the RM-managed PDEs from the RM-managed page directory + * into the external page directory and commit channels to the external page directory. + * After this point RM will update the external page directory directly for + * operations that modify RM-managed PDEs. + * 3. The external component may use NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY repeatedly + * if it needs to update the page directory again (e.g. to resize or migrate). + * This will copy the RM-managed PDEs from the old external page directory + * into the new external page directory and commit channels to the new page directory. + * 4. The external component may restore management of the page directory back to + * RM with NV0080_CTRL_CMD_DMA_UNSET_PAGE_DIRECTORY. + * This will copy the RM-managed PDEs from the external page directory + * into the RM-managed page directory and commit channels to the RM-managed page directory. + * After this point RM will update the RM-managed page directory for + * operations that modify RM-managed PDEs. + * Note that operations (2) and (4) are symmetric - the RM perspective of management is identical + * before and after a sequence of SET => ... => UNSET. + * + * IS_MIRRORED + * This flag will tell RM to create a mirrored + * kernel PDB for the address space associated + * with this device. When this flag is set + * the address space covered by the top PDE + * is restricted and cannot be allocated out of. + * ENABLE_PAGE_FAULTING + * Enable page faulting if the architecture supports it. + * As of now page faulting is only supported for compute on pascal+. + * IS_EXTERNALLY_OWNED + * This vaspace that has been allocated will be managed by + * an external driver. RM will not own the pagetables for this vaspace. + * + * ENABLE_NVLINK_ATS + * Enables VA translation for this address space using NVLINK ATS. + * Note, the GMMU page tables still exist and take priority over NVLINK ATS. + * VA space object creation will fail if: + * - hardware support is not available (NV_ERR_NOT_SUPPORTED) + * - incompatible options IS_MIRRORED or IS_EXTERNALLY_OWNED are set (NV_ERR_INVALID_ARGUMENT) + * IS_FLA + * Sets FLA flag for this VASPACE + * + * ALLOW_ZERO_ADDRESS + * Allows VASPACE Range to start from zero + * SKIP_SCRUB_MEMPOOL + * Skip scrubbing in MemPool + * + * vaBase [in, out] + * On input, the lowest usable base address of the VA space. + * If 0, RM will pick a default value - 0 is always reserved to respresent NULL pointers. + * The value must be aligned to the largest page size of the VA space. + * Larger values aid in debug since offsets added to NULL pointers will still fault. + * + * On output, the actual usable base address is returned. + * + * vaSize [in,out] + * On input, requested size of the virtual address space in bytes. + * Requesting a smaller size reduces the memory required for the initial + * page directory, but the VAS may be resized later (NV0080_CTRL_DMA_SET_VA_SPACE_SIZE). + * If 0, the default VA space size will be used. + * + * On output, the actual size of the VAS in bytes. + * NOTE: This corresponds to the VA_LIMIT + 1, so the usable size is (vaSize - vaBase). + * + * bigPageSIze + * Set the size of the big page in this address space object. Current HW supports + * either 64k or 128k as the size of the big page. HW that support multiple big + * page size per address space will use this size. Hw that do not support this feature + * will override to the default big page size that is supported by the system. + * If the big page size value is set to ZERO then we will pick the default page size + * of the system. + **/ +typedef struct +{ + NvU32 index; + NvV32 flags; + NvU64 vaSize NV_ALIGN_BYTES(8); + NvU64 vaStartInternal NV_ALIGN_BYTES(8); + NvU64 vaLimitInternal NV_ALIGN_BYTES(8); + NvU32 bigPageSize; + NvU64 vaBase NV_ALIGN_BYTES(8); +} NV_VASPACE_ALLOCATION_PARAMETERS; + +#define NV_VASPACE_ALLOCATION_FLAGS_NONE (0x00000000) +#define NV_VASPACE_ALLOCATION_FLAGS_MINIMIZE_PTETABLE_SIZE BIT(0) +#define NV_VASPACE_ALLOCATION_FLAGS_RETRY_PTE_ALLOC_IN_SYS BIT(1) +#define NV_VASPACE_ALLOCATION_FLAGS_SHARED_MANAGEMENT BIT(2) +#define NV_VASPACE_ALLOCATION_FLAGS_IS_EXTERNALLY_OWNED BIT(3) +#define NV_VASPACE_ALLOCATION_FLAGS_ENABLE_NVLINK_ATS BIT(4) +#define NV_VASPACE_ALLOCATION_FLAGS_IS_MIRRORED BIT(5) +#define NV_VASPACE_ALLOCATION_FLAGS_ENABLE_PAGE_FAULTING BIT(6) +#define NV_VASPACE_ALLOCATION_FLAGS_VA_INTERNAL_LIMIT BIT(7) +#define NV_VASPACE_ALLOCATION_FLAGS_ALLOW_ZERO_ADDRESS BIT(8) +#define NV_VASPACE_ALLOCATION_FLAGS_IS_FLA BIT(9) +#define NV_VASPACE_ALLOCATION_FLAGS_SKIP_SCRUB_MEMPOOL BIT(10) +#define NV_VASPACE_ALLOCATION_FLAGS_OPTIMIZE_PTETABLE_MEMPOOL_USAGE BIT(11) +#define NV_VASPACE_ALLOCATION_FLAGS_REQUIRE_FIXED_OFFSET BIT(12) + +#define NV_VASPACE_ALLOCATION_INDEX_GPU_NEW 0x00 // NV_STATUS_LEVEL_WARN + * to determine success v. failure of a call. + */ +#define NV_STATUS_LEVEL_WARN 1 + +/*! + * @def NV_STATUS_LEVEL_ERR + * @see NV_STATUS_LEVEL + * @brief Unrecoverable error condition + */ +#define NV_STATUS_LEVEL_ERR 3 + +/*! + * @def NV_STATUS_LEVEL + * @see NV_STATUS_LEVEL_OK + * @see NV_STATUS_LEVEL_WARN + * @see NV_STATUS_LEVEL_ERR + * @brief Level of the status code + * + * @warning IMPORTANT: When comparing NV_STATUS_LEVEL(_S) against one of + * these constants, it is important to use '<=' or '>' (rather + * than '<' or '>='). + * + * For example. do: + * if (NV_STATUS_LEVEL(status) <= NV_STATUS_LEVEL_WARN) + * rather than: + * if (NV_STATUS_LEVEL(status) < NV_STATUS_LEVEL_ERR) + * + * By being consistent in this manner, it is easier to systematically + * add additional level constants. New levels are likely to lower + * (rather than raise) the severity of _ERR codes. For example, + * if we were to add NV_STATUS_LEVEL_RETRY to indicate hardware + * failures that may be recoverable (e.g. RM_ERR_TIMEOUT_RETRY + * or RM_ERR_BUSY_RETRY), it would be less severe than + * NV_STATUS_LEVEL_ERR the level to which these status codes now + * belong. Using '<=' and '>' ensures your code is not broken in + * cases like this. + */ +#define NV_STATUS_LEVEL(_S) \ + ((_S) == NV_OK? NV_STATUS_LEVEL_OK: \ + ((_S) != NV_ERR_GENERIC && (_S) & 0x00010000? NV_STATUS_LEVEL_WARN: \ + NV_STATUS_LEVEL_ERR)) + +/*! + * @def NV_STATUS_LEVEL + * @see NV_STATUS_LEVEL_OK + * @see NV_STATUS_LEVEL_WARN + * @see NV_STATUS_LEVEL_ERR + * @brief Character representing status code level + */ +#define NV_STATUS_LEVEL_CHAR(_S) \ + ((_S) == NV_OK? '0': \ + ((_S) != NV_ERR_GENERIC && (_S) & 0x00010000? 'W': \ + 'E')) + +// Function definitions +const char *nvstatusToString(NV_STATUS nvStatusIn); + +#ifdef __cplusplus +} +#endif + +#endif /* SDK_NVSTATUS_H */ diff --git a/userspace/sdks/nv570/nvidia/inc/nvstatuscodes.h b/userspace/sdks/nv570/nvidia/inc/nvstatuscodes.h new file mode 100644 index 0000000..517a8ce --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/nvstatuscodes.h @@ -0,0 +1,163 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef SDK_NVSTATUSCODES_H +#define SDK_NVSTATUSCODES_H + +NV_STATUS_CODE(NV_OK, 0x00000000, "Success") +NV_STATUS_CODE(NV_ERR_GENERIC, 0x0000FFFF, "Failure: Generic Error") + +NV_STATUS_CODE(NV_ERR_BROKEN_FB, 0x00000001, "Frame-Buffer broken") +NV_STATUS_CODE(NV_ERR_BUFFER_TOO_SMALL, 0x00000002, "Buffer passed in is too small") +NV_STATUS_CODE(NV_ERR_BUSY_RETRY, 0x00000003, "System is busy, retry later") +NV_STATUS_CODE(NV_ERR_CALLBACK_NOT_SCHEDULED, 0x00000004, "The requested callback API not scheduled") +NV_STATUS_CODE(NV_ERR_CARD_NOT_PRESENT, 0x00000005, "Card not detected") +NV_STATUS_CODE(NV_ERR_CYCLE_DETECTED, 0x00000006, "Call cycle detected") +NV_STATUS_CODE(NV_ERR_DMA_IN_USE, 0x00000007, "Requested DMA is in use") +NV_STATUS_CODE(NV_ERR_DMA_MEM_NOT_LOCKED, 0x00000008, "Requested DMA memory is not locked") +NV_STATUS_CODE(NV_ERR_DMA_MEM_NOT_UNLOCKED, 0x00000009, "Requested DMA memory is not unlocked") +NV_STATUS_CODE(NV_ERR_DUAL_LINK_INUSE, 0x0000000A, "Dual-Link is in use") +NV_STATUS_CODE(NV_ERR_ECC_ERROR, 0x0000000B, "Generic ECC error") +NV_STATUS_CODE(NV_ERR_FIFO_BAD_ACCESS, 0x0000000C, "FIFO: Invalid access") +NV_STATUS_CODE(NV_ERR_FREQ_NOT_SUPPORTED, 0x0000000D, "Requested frequency is not supported") +NV_STATUS_CODE(NV_ERR_GPU_DMA_NOT_INITIALIZED, 0x0000000E, "Requested DMA not initialized") +NV_STATUS_CODE(NV_ERR_GPU_IS_LOST, 0x0000000F, "GPU lost from the bus") +NV_STATUS_CODE(NV_ERR_GPU_IN_FULLCHIP_RESET, 0x00000010, "GPU currently in full-chip reset") +NV_STATUS_CODE(NV_ERR_GPU_NOT_FULL_POWER, 0x00000011, "GPU not in full power") +NV_STATUS_CODE(NV_ERR_GPU_UUID_NOT_FOUND, 0x00000012, "GPU UUID not found") +NV_STATUS_CODE(NV_ERR_HOT_SWITCH, 0x00000013, "System in hot switch") +NV_STATUS_CODE(NV_ERR_I2C_ERROR, 0x00000014, "I2C Error") +NV_STATUS_CODE(NV_ERR_I2C_SPEED_TOO_HIGH, 0x00000015, "I2C Error: Speed too high") +NV_STATUS_CODE(NV_ERR_ILLEGAL_ACTION, 0x00000016, "Current action is not allowed") +NV_STATUS_CODE(NV_ERR_IN_USE, 0x00000017, "Generic busy error") +NV_STATUS_CODE(NV_ERR_INFLATE_COMPRESSED_DATA_FAILED, 0x00000018, "Failed to inflate compressed data") +NV_STATUS_CODE(NV_ERR_INSERT_DUPLICATE_NAME, 0x00000019, "Found a duplicate entry in the requested btree") +NV_STATUS_CODE(NV_ERR_INSUFFICIENT_RESOURCES, 0x0000001A, "Ran out of a critical resource, other than memory") +NV_STATUS_CODE(NV_ERR_INSUFFICIENT_PERMISSIONS, 0x0000001B, "The requester does not have sufficient permissions") +NV_STATUS_CODE(NV_ERR_INSUFFICIENT_POWER, 0x0000001C, "Generic Error: Low power") +NV_STATUS_CODE(NV_ERR_INVALID_ACCESS_TYPE, 0x0000001D, "This type of access is not allowed") +NV_STATUS_CODE(NV_ERR_INVALID_ADDRESS, 0x0000001E, "Address not valid") +NV_STATUS_CODE(NV_ERR_INVALID_ARGUMENT, 0x0000001F, "Invalid argument to call") +NV_STATUS_CODE(NV_ERR_INVALID_BASE, 0x00000020, "Invalid base") +NV_STATUS_CODE(NV_ERR_INVALID_CHANNEL, 0x00000021, "Given channel-id not valid") +NV_STATUS_CODE(NV_ERR_INVALID_CLASS, 0x00000022, "Given class-id not valid") +NV_STATUS_CODE(NV_ERR_INVALID_CLIENT, 0x00000023, "Given client not valid") +NV_STATUS_CODE(NV_ERR_INVALID_COMMAND, 0x00000024, "Command passed is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_DATA, 0x00000025, "Invalid data passed") +NV_STATUS_CODE(NV_ERR_INVALID_DEVICE, 0x00000026, "Current device is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_DMA_SPECIFIER, 0x00000027, "The requested DMA specifier is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_EVENT, 0x00000028, "Invalid event occurred") +NV_STATUS_CODE(NV_ERR_INVALID_FLAGS, 0x00000029, "Invalid flags passed") +NV_STATUS_CODE(NV_ERR_INVALID_FUNCTION, 0x0000002A, "Called function is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_HEAP, 0x0000002B, "Heap corrupted") +NV_STATUS_CODE(NV_ERR_INVALID_INDEX, 0x0000002C, "Index invalid") +NV_STATUS_CODE(NV_ERR_INVALID_IRQ_LEVEL, 0x0000002D, "Requested IRQ level is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_LIMIT, 0x0000002E, "Generic Error: Invalid limit") +NV_STATUS_CODE(NV_ERR_INVALID_LOCK_STATE, 0x0000002F, "Requested lock state not valid") +NV_STATUS_CODE(NV_ERR_INVALID_METHOD, 0x00000030, "Requested method not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OBJECT, 0x00000031, "Object not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_BUFFER, 0x00000032, "Object buffer passed is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_HANDLE, 0x00000033, "Object handle is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_NEW, 0x00000034, "New object is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_OLD, 0x00000035, "Old object is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_PARENT, 0x00000036, "Object parent is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OFFSET, 0x00000037, "The offset passed is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OPERATION, 0x00000038, "Requested operation is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_OWNER, 0x00000039, "Owner not valid") +NV_STATUS_CODE(NV_ERR_INVALID_PARAM_STRUCT, 0x0000003A, "Invalid structure parameter") +NV_STATUS_CODE(NV_ERR_INVALID_PARAMETER, 0x0000003B, "At least one of the parameters passed is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_PATH, 0x0000003C, "The requested path is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_POINTER, 0x0000003D, "Pointer not valid") +NV_STATUS_CODE(NV_ERR_INVALID_REGISTRY_KEY, 0x0000003E, "Found an invalid registry key") +NV_STATUS_CODE(NV_ERR_INVALID_REQUEST, 0x0000003F, "Generic Error: Invalid request") +NV_STATUS_CODE(NV_ERR_INVALID_STATE, 0x00000040, "Generic Error: Invalid state") +NV_STATUS_CODE(NV_ERR_INVALID_STRING_LENGTH, 0x00000041, "The string length is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_READ, 0x00000042, "The requested read operation is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_WRITE, 0x00000043, "The requested write operation is not valid") +NV_STATUS_CODE(NV_ERR_INVALID_XLATE, 0x00000044, "The requested translate operation is not valid") +NV_STATUS_CODE(NV_ERR_IRQ_NOT_FIRING, 0x00000045, "Requested IRQ is not firing") +NV_STATUS_CODE(NV_ERR_IRQ_EDGE_TRIGGERED, 0x00000046, "IRQ is edge triggered") +NV_STATUS_CODE(NV_ERR_MEMORY_TRAINING_FAILED, 0x00000047, "Failed memory training sequence") +NV_STATUS_CODE(NV_ERR_MISMATCHED_SLAVE, 0x00000048, "Slave mismatch") +NV_STATUS_CODE(NV_ERR_MISMATCHED_TARGET, 0x00000049, "Target mismatch") +NV_STATUS_CODE(NV_ERR_MISSING_TABLE_ENTRY, 0x0000004A, "Requested entry missing not found in the table") +NV_STATUS_CODE(NV_ERR_MODULE_LOAD_FAILED, 0x0000004B, "Failed to load the requested module") +NV_STATUS_CODE(NV_ERR_MORE_DATA_AVAILABLE, 0x0000004C, "There is more data available") +NV_STATUS_CODE(NV_ERR_MORE_PROCESSING_REQUIRED, 0x0000004D, "More processing required for the given call") +NV_STATUS_CODE(NV_ERR_MULTIPLE_MEMORY_TYPES, 0x0000004E, "Multiple memory types found") +NV_STATUS_CODE(NV_ERR_NO_FREE_FIFOS, 0x0000004F, "No more free FIFOs found") +NV_STATUS_CODE(NV_ERR_NO_INTR_PENDING, 0x00000050, "No interrupt pending") +NV_STATUS_CODE(NV_ERR_NO_MEMORY, 0x00000051, "Out of memory") +NV_STATUS_CODE(NV_ERR_NO_SUCH_DOMAIN, 0x00000052, "Requested domain does not exist") +NV_STATUS_CODE(NV_ERR_NO_VALID_PATH, 0x00000053, "Caller did not specify a valid path") +NV_STATUS_CODE(NV_ERR_NOT_COMPATIBLE, 0x00000054, "Generic Error: Incompatible types") +NV_STATUS_CODE(NV_ERR_NOT_READY, 0x00000055, "Generic Error: Not ready") +NV_STATUS_CODE(NV_ERR_NOT_SUPPORTED, 0x00000056, "Call not supported") +NV_STATUS_CODE(NV_ERR_OBJECT_NOT_FOUND, 0x00000057, "Requested object not found") +NV_STATUS_CODE(NV_ERR_OBJECT_TYPE_MISMATCH, 0x00000058, "Specified objects do not match") +NV_STATUS_CODE(NV_ERR_OPERATING_SYSTEM, 0x00000059, "Generic operating system error") +NV_STATUS_CODE(NV_ERR_OTHER_DEVICE_FOUND, 0x0000005A, "Found other device instead of the requested one") +NV_STATUS_CODE(NV_ERR_OUT_OF_RANGE, 0x0000005B, "The specified value is out of bounds") +NV_STATUS_CODE(NV_ERR_OVERLAPPING_UVM_COMMIT, 0x0000005C, "Overlapping unified virtual memory commit") +NV_STATUS_CODE(NV_ERR_PAGE_TABLE_NOT_AVAIL, 0x0000005D, "Requested page table not available") +NV_STATUS_CODE(NV_ERR_PID_NOT_FOUND, 0x0000005E, "Process-Id not found") +NV_STATUS_CODE(NV_ERR_PROTECTION_FAULT, 0x0000005F, "Protection fault") +NV_STATUS_CODE(NV_ERR_RC_ERROR, 0x00000060, "Generic RC error") +NV_STATUS_CODE(NV_ERR_REJECTED_VBIOS, 0x00000061, "Given Video BIOS rejected/invalid") +NV_STATUS_CODE(NV_ERR_RESET_REQUIRED, 0x00000062, "Reset required") +NV_STATUS_CODE(NV_ERR_STATE_IN_USE, 0x00000063, "State in use") +NV_STATUS_CODE(NV_ERR_SIGNAL_PENDING, 0x00000064, "Signal pending") +NV_STATUS_CODE(NV_ERR_TIMEOUT, 0x00000065, "Call timed out") +NV_STATUS_CODE(NV_ERR_TIMEOUT_RETRY, 0x00000066, "Call timed out, please retry later") +NV_STATUS_CODE(NV_ERR_TOO_MANY_PRIMARIES, 0x00000067, "Too many primaries") +NV_STATUS_CODE(NV_ERR_UVM_ADDRESS_IN_USE, 0x00000068, "Unified virtual memory requested address already in use") +NV_STATUS_CODE(NV_ERR_MAX_SESSION_LIMIT_REACHED, 0x00000069, "Maximum number of sessions reached") +NV_STATUS_CODE(NV_ERR_LIB_RM_VERSION_MISMATCH, 0x0000006A, "Library version doesn't match driver version") //Contained within the RMAPI library +NV_STATUS_CODE(NV_ERR_PRIV_SEC_VIOLATION, 0x0000006B, "Priv security violation") +NV_STATUS_CODE(NV_ERR_GPU_IN_DEBUG_MODE, 0x0000006C, "GPU currently in debug mode") +NV_STATUS_CODE(NV_ERR_FEATURE_NOT_ENABLED, 0x0000006D, "Requested Feature functionality is not enabled") +NV_STATUS_CODE(NV_ERR_RESOURCE_LOST, 0x0000006E, "Requested resource has been destroyed") +NV_STATUS_CODE(NV_ERR_PMU_NOT_READY, 0x0000006F, "PMU is not ready or has not yet been initialized") +NV_STATUS_CODE(NV_ERR_FLCN_ERROR, 0x00000070, "Generic falcon assert or halt") +NV_STATUS_CODE(NV_ERR_FATAL_ERROR, 0x00000071, "Fatal/unrecoverable error") +NV_STATUS_CODE(NV_ERR_MEMORY_ERROR, 0x00000072, "Generic memory error") +NV_STATUS_CODE(NV_ERR_INVALID_LICENSE, 0x00000073, "License provided is rejected or invalid") +NV_STATUS_CODE(NV_ERR_NVLINK_INIT_ERROR, 0x00000074, "Nvlink Init Error") +NV_STATUS_CODE(NV_ERR_NVLINK_MINION_ERROR, 0x00000075, "Nvlink Minion Error") +NV_STATUS_CODE(NV_ERR_NVLINK_CLOCK_ERROR, 0x00000076, "Nvlink Clock Error") +NV_STATUS_CODE(NV_ERR_NVLINK_TRAINING_ERROR, 0x00000077, "Nvlink Training Error") +NV_STATUS_CODE(NV_ERR_NVLINK_CONFIGURATION_ERROR, 0x00000078, "Nvlink Configuration Error") +NV_STATUS_CODE(NV_ERR_RISCV_ERROR, 0x00000079, "Generic RISC-V assert or halt") +NV_STATUS_CODE(NV_ERR_FABRIC_MANAGER_NOT_PRESENT, 0x0000007A, "Fabric Manager is not loaded") + +// Warnings: +NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch") +NV_STATUS_CODE(NV_WARN_INCORRECT_PERFMON_DATA, 0x00010002, "WARNING Incorrect performance monitor data") +NV_STATUS_CODE(NV_WARN_MISMATCHED_SLAVE, 0x00010003, "WARNING Slave mismatch") +NV_STATUS_CODE(NV_WARN_MISMATCHED_TARGET, 0x00010004, "WARNING Target mismatch") +NV_STATUS_CODE(NV_WARN_MORE_PROCESSING_REQUIRED, 0x00010005, "WARNING More processing required for the call") +NV_STATUS_CODE(NV_WARN_NOTHING_TO_DO, 0x00010006, "WARNING Nothing to do") +NV_STATUS_CODE(NV_WARN_NULL_OBJECT, 0x00010007, "WARNING NULL object found") +NV_STATUS_CODE(NV_WARN_OUT_OF_RANGE, 0x00010008, "WARNING value out of range") + +#endif /* SDK_NVSTATUSCODES_H */ diff --git a/userspace/sdks/nv570/nvidia/inc/nvtypes.h b/userspace/sdks/nv570/nvidia/inc/nvtypes.h new file mode 100644 index 0000000..53a60f9 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/nvtypes.h @@ -0,0 +1,625 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVTYPES_INCLUDED +#define NVTYPES_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include "cpuopsys.h" + +#ifndef NVTYPES_USE_STDINT +#define NVTYPES_USE_STDINT 0 +#endif + +#if NVTYPES_USE_STDINT +#ifdef __cplusplus +#include +#include +#else +#include +#include +#endif // __cplusplus +#endif // NVTYPES_USE_STDINT + +#ifndef __cplusplus +// Header includes to make sure wchar_t is defined for C-file compilation +// (C++ is not affected as it is a fundamental type there) +// _MSC_VER is a hack to avoid failures for old setup of UEFI builds which are +// currently set to msvc100 but do not properly set the include paths +#endif // __cplusplus + +#if defined(MAKE_NV64TYPES_8BYTES_ALIGNED) && defined(__i386__) +// ensure or force 8-bytes alignment of NV 64-bit types +#define OPTIONAL_ALIGN8_ATTR __attribute__((aligned(8))) +#else +// nothing needed +#define OPTIONAL_ALIGN8_ATTR +#endif // MAKE_NV64TYPES_8BYTES_ALIGNED && i386 + + /***************************************************************************\ +|* Typedefs *| + \***************************************************************************/ + +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +//Typedefs for MISRA COMPLIANCE +typedef unsigned long long UInt64; +typedef signed long long Int64; +typedef unsigned int UInt32; +typedef signed int Int32; +typedef unsigned short UInt16; +typedef signed short Int16; +typedef unsigned char UInt8 ; +typedef signed char Int8 ; + +typedef void Void; +typedef float float32_t; +typedef double float64_t; +#endif + + +// Floating point types +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +typedef float32_t NvF32; /* IEEE Single Precision (S1E8M23) */ +typedef float64_t NvF64 OPTIONAL_ALIGN8_ATTR; /* IEEE Double Precision (S1E11M52) */ +#else +typedef float NvF32; /* IEEE Single Precision (S1E8M23) */ +typedef double NvF64 OPTIONAL_ALIGN8_ATTR; /* IEEE Double Precision (S1E11M52) */ +#endif + + +// 8-bit: 'char' is the only 8-bit in the C89 standard and after. +#if NVTYPES_USE_STDINT +typedef uint8_t NvV8; /* "void": enumerated or multiple fields */ +typedef uint8_t NvU8; /* 0 to 255 */ +typedef int8_t NvS8; /* -128 to 127 */ +#else +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +typedef UInt8 NvV8; /* "void": enumerated or multiple fields */ +typedef UInt8 NvU8; /* 0 to 255 */ +typedef Int8 NvS8; /* -128 to 127 */ +#else +typedef unsigned char NvV8; /* "void": enumerated or multiple fields */ +typedef unsigned char NvU8; /* 0 to 255 */ +typedef signed char NvS8; /* -128 to 127 */ +#endif +#endif // NVTYPES_USE_STDINT + + +#if NVTYPES_USE_STDINT +typedef uint16_t NvV16; /* "void": enumerated or multiple fields */ +typedef uint16_t NvU16; /* 0 to 65535 */ +typedef int16_t NvS16; /* -32768 to 32767 */ +#else +// 16-bit: If the compiler tells us what we can use, then use it. +#ifdef __INT16_TYPE__ +typedef unsigned __INT16_TYPE__ NvV16; /* "void": enumerated or multiple fields */ +typedef unsigned __INT16_TYPE__ NvU16; /* 0 to 65535 */ +typedef signed __INT16_TYPE__ NvS16; /* -32768 to 32767 */ + +// The minimal standard for C89 and after +#else // __INT16_TYPE__ +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +typedef UInt16 NvV16; /* "void": enumerated or multiple fields */ +typedef UInt16 NvU16; /* 0 to 65535 */ +typedef Int16 NvS16; /* -32768 to 32767 */ +#else +typedef unsigned short NvV16; /* "void": enumerated or multiple fields */ +typedef unsigned short NvU16; /* 0 to 65535 */ +typedef signed short NvS16; /* -32768 to 32767 */ +#endif +#endif // __INT16_TYPE__ +#endif // NVTYPES_USE_STDINT + +// wchar type (fixed size types consistent across Linux/Windows boundaries) +#if defined(NV_HAS_WCHAR_T_TYPEDEF) + typedef wchar_t NvWchar; +#else + typedef NvV16 NvWchar; +#endif + +// Macro to build an NvU32 from four bytes, listed from msb to lsb +#define NvU32_BUILD(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d)) + +#if NVTYPES_USE_STDINT +typedef uint32_t NvV32; /* "void": enumerated or multiple fields */ +typedef uint32_t NvU32; /* 0 to 4294967295 */ +typedef int32_t NvS32; /* -2147483648 to 2147483647 */ +#else +// 32-bit: If the compiler tells us what we can use, then use it. +#ifdef __INT32_TYPE__ +typedef unsigned __INT32_TYPE__ NvV32; /* "void": enumerated or multiple fields */ +typedef unsigned __INT32_TYPE__ NvU32; /* 0 to 4294967295 */ +typedef signed __INT32_TYPE__ NvS32; /* -2147483648 to 2147483647 */ + +// Older compilers +#else // __INT32_TYPE__ + +// For historical reasons, NvU32/NvV32 are defined to different base intrinsic +// types than NvS32 on some platforms. +// Mainly for 64-bit linux, where long is 64 bits and win9x, where int is 16 bit. +#if (defined(NV_UNIX) || defined(vxworks) || defined(NV_WINDOWS_CE) || \ + defined(__arm) || defined(__IAR_SYSTEMS_ICC__) || defined(NV_QNX) || \ + defined(NV_INTEGRITY) || defined(NV_MODS) || \ + defined(__GNUC__) || defined(__clang__) || defined(NV_MACINTOSH_64)) && \ + (!defined(NV_MACINTOSH) || defined(NV_MACINTOSH_64)) +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +typedef UInt32 NvV32; /* "void": enumerated or multiple fields */ +typedef UInt32 NvU32; /* 0 to 4294967295 */ +#else +typedef unsigned int NvV32; /* "void": enumerated or multiple fields */ +typedef unsigned int NvU32; /* 0 to 4294967295 */ +#endif + +// The minimal standard for C89 and after +#else // (defined(NV_UNIX) || defined(vxworks) || ... +typedef unsigned long NvV32; /* "void": enumerated or multiple fields */ +typedef unsigned long NvU32; /* 0 to 4294967295 */ +#endif // (defined(NV_UNIX) || defined(vxworks) || ... + +// Mac OS 32-bit still needs this +#if defined(NV_MACINTOSH) && !defined(NV_MACINTOSH_64) +typedef signed long NvS32; /* -2147483648 to 2147483647 */ +#else +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +typedef Int32 NvS32; /* -2147483648 to 2147483647 */ +#else +typedef signed int NvS32; /* -2147483648 to 2147483647 */ +#endif +#endif // defined(NV_MACINTOSH) && !defined(NV_MACINTOSH_64) +#endif // __INT32_TYPE__ +#endif // NVTYPES_USE_STDINT + + + +#if NVTYPES_USE_STDINT +typedef uint64_t NvU64 OPTIONAL_ALIGN8_ATTR; /* 0 to 18446744073709551615 */ +typedef int64_t NvS64 OPTIONAL_ALIGN8_ATTR; /* -9223372036854775808 to 9223372036854775807 */ + +#define NvU64_fmtX PRIX64 +#define NvU64_fmtx PRIx64 +#define NvU64_fmtu PRIu64 +#define NvU64_fmto PRIo64 +#define NvS64_fmtd PRId64 +#define NvS64_fmti PRIi64 +#else +// 64-bit types for compilers that support them, plus some obsolete variants +#if defined(__GNUC__) || defined(__clang__) || defined(__arm) || \ + defined(__IAR_SYSTEMS_ICC__) || defined(__ghs__) || defined(_WIN64) || \ + defined(__SUNPRO_C) || defined(__SUNPRO_CC) || defined (__xlC__) +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +typedef UInt64 NvU64 OPTIONAL_ALIGN8_ATTR; /* 0 to 18446744073709551615 */ +typedef Int64 NvS64 OPTIONAL_ALIGN8_ATTR; /* -9223372036854775808 to 9223372036854775807 */ +#else +typedef unsigned long long NvU64 OPTIONAL_ALIGN8_ATTR; /* 0 to 18446744073709551615 */ +typedef long long NvS64 OPTIONAL_ALIGN8_ATTR; /* -9223372036854775808 to 9223372036854775807 */ +#endif + +#define NvU64_fmtX "llX" +#define NvU64_fmtx "llx" +#define NvU64_fmtu "llu" +#define NvU64_fmto "llo" +#define NvS64_fmtd "lld" +#define NvS64_fmti "lli" + +// Microsoft since 2003 -- https://msdn.microsoft.com/en-us/library/29dh1w7z.aspx +#else +typedef unsigned __int64 NvU64 OPTIONAL_ALIGN8_ATTR; /* 0 to 18446744073709551615 */ +typedef __int64 NvS64 OPTIONAL_ALIGN8_ATTR; /* -9223372036854775808 to 9223372036854775807 */ + +#define NvU64_fmtX "I64X" +#define NvU64_fmtx "I64x" +#define NvU64_fmtu "I64u" +#define NvU64_fmto "I64o" +#define NvS64_fmtd "I64d" +#define NvS64_fmti "I64i" + +#endif +#endif // NVTYPES_USE_STDINT + +#ifdef NV_TYPESAFE_HANDLES +/* + * Can't use opaque pointer as clients might be compiled with mismatched + * pointer sizes. TYPESAFE check will eventually be removed once all clients + * have transistioned safely to NvHandle. + * The plan is to then eventually scale up the handle to be 64-bits. + */ +typedef struct +{ + NvU32 val; +} NvHandle; +#else +/* + * For compatibility with modules that haven't moved typesafe handles. + */ +typedef NvU32 NvHandle; +#endif // NV_TYPESAFE_HANDLES + +/* Boolean type */ +typedef NvU8 NvBool; +#define NV_TRUE ((NvBool)(0 == 0)) +#define NV_FALSE ((NvBool)(0 != 0)) + +/* Tristate type: NV_TRISTATE_FALSE, NV_TRISTATE_TRUE, NV_TRISTATE_INDETERMINATE */ +typedef NvU8 NvTristate; +#define NV_TRISTATE_FALSE ((NvTristate) 0) +#define NV_TRISTATE_TRUE ((NvTristate) 1) +#define NV_TRISTATE_INDETERMINATE ((NvTristate) 2) + +/* Macros to extract the low and high parts of a 64-bit unsigned integer */ +/* Also designed to work if someone happens to pass in a 32-bit integer */ +#ifdef NV_MISRA_COMPLIANCE_REQUIRED +#define NvU64_HI32(n) ((NvU32)((((NvU64)(n)) >> 32) & 0xffffffffU)) +#define NvU64_LO32(n) ((NvU32)(( (NvU64)(n)) & 0xffffffffU)) +#else +#define NvU64_HI32(n) ((NvU32)((((NvU64)(n)) >> 32) & 0xffffffff)) +#define NvU64_LO32(n) ((NvU32)(( (NvU64)(n)) & 0xffffffff)) +#endif +#define NvU40_HI32(n) ((NvU32)((((NvU64)(n)) >> 8) & 0xffffffffU)) +#define NvU40_HI24of32(n) ((NvU32)( (NvU64)(n) & 0xffffff00U)) + +/* Macros to get the MSB and LSB of a 32 bit unsigned number */ +#define NvU32_HI16(n) ((NvU16)((((NvU32)(n)) >> 16) & 0xffffU)) +#define NvU32_LO16(n) ((NvU16)(( (NvU32)(n)) & 0xffffU)) + + /***************************************************************************\ +|* *| +|* 64 bit type definitions for use in interface structures. *| +|* *| + \***************************************************************************/ + +#if defined(NV_64_BITS) + +typedef void* NvP64; /* 64 bit void pointer */ +typedef NvU64 NvUPtr; /* pointer sized unsigned int */ +typedef NvS64 NvSPtr; /* pointer sized signed int */ +typedef NvU64 NvLength; /* length to agree with sizeof */ + +#define NvP64_VALUE(n) (n) +#define NvP64_fmt "%p" + +#define KERNEL_POINTER_FROM_NvP64(p,v) ((p)(v)) +#define NvP64_PLUS_OFFSET(p,o) (NvP64)((NvU64)(p) + (NvU64)(o)) + +#define NvUPtr_fmtX NvU64_fmtX +#define NvUPtr_fmtx NvU64_fmtx +#define NvUPtr_fmtu NvU64_fmtu +#define NvUPtr_fmto NvU64_fmto +#define NvSPtr_fmtd NvS64_fmtd +#define NvSPtr_fmti NvS64_fmti + +#else + +typedef NvU64 NvP64; /* 64 bit void pointer */ +typedef NvU32 NvUPtr; /* pointer sized unsigned int */ +typedef NvS32 NvSPtr; /* pointer sized signed int */ +typedef NvU32 NvLength; /* length to agree with sizeof */ + +#define NvP64_VALUE(n) ((void *)(NvUPtr)(n)) +#define NvP64_fmt "0x%llx" + +#define KERNEL_POINTER_FROM_NvP64(p,v) ((p)(NvUPtr)(v)) +#define NvP64_PLUS_OFFSET(p,o) ((p) + (NvU64)(o)) + +#define NvUPtr_fmtX "X" +#define NvUPtr_fmtx "x" +#define NvUPtr_fmtu "u" +#define NvUPtr_fmto "o" +#define NvSPtr_fmtd "d" +#define NvSPtr_fmti "i" + +#endif + +#define NvP64_NULL (NvP64)0 + +/*! + * Helper macro to pack an @ref NvU64_ALIGN32 structure from a @ref NvU64. + * + * @param[out] pDst Pointer to NvU64_ALIGN32 structure to pack + * @param[in] pSrc Pointer to NvU64 with which to pack + */ +#define NvU64_ALIGN32_PACK(pDst, pSrc) \ +do { \ + (pDst)->lo = NvU64_LO32(*(pSrc)); \ + (pDst)->hi = NvU64_HI32(*(pSrc)); \ +} while (NV_FALSE) + +/*! + * Helper macro to unpack a @ref NvU64_ALIGN32 structure into a @ref NvU64. + * + * @param[out] pDst Pointer to NvU64 in which to unpack + * @param[in] pSrc Pointer to NvU64_ALIGN32 structure from which to unpack + */ +#define NvU64_ALIGN32_UNPACK(pDst, pSrc) \ +do { \ + (*(pDst)) = NvU64_ALIGN32_VAL(pSrc); \ +} while (NV_FALSE) + +/*! + * Helper macro to unpack a @ref NvU64_ALIGN32 structure as a @ref NvU64. + * + * @param[in] pSrc Pointer to NvU64_ALIGN32 structure to unpack + */ +#define NvU64_ALIGN32_VAL(pSrc) \ + ((NvU64) ((NvU64)((pSrc)->lo) | (((NvU64)(pSrc)->hi) << 32U))) + +/*! + * Helper macro to check whether the 32 bit aligned 64 bit number is zero. + * + * @param[in] _pU64 Pointer to NvU64_ALIGN32 structure. + * + * @return + * NV_TRUE _pU64 is zero. + * NV_FALSE otherwise. + */ +#define NvU64_ALIGN32_IS_ZERO(_pU64) \ + (((_pU64)->lo == 0U) && ((_pU64)->hi == 0U)) + +/*! + * Helper macro to sub two 32 aligned 64 bit numbers on 64 bit processor. + * + * @param[in] pSrc1 Pointer to NvU64_ALIGN32 source 1 structure. + * @param[in] pSrc2 Pointer to NvU64_ALIGN32 source 2 structure. + * @param[in/out] pDst Pointer to NvU64_ALIGN32 dest. structure. + */ +#define NvU64_ALIGN32_ADD(pDst, pSrc1, pSrc2) \ +do { \ + NvU64 __dst, __src1, __scr2; \ + \ + NvU64_ALIGN32_UNPACK(&__src1, (pSrc1)); \ + NvU64_ALIGN32_UNPACK(&__scr2, (pSrc2)); \ + __dst = __src1 + __scr2; \ + NvU64_ALIGN32_PACK((pDst), &__dst); \ +} while (NV_FALSE) + +/*! + * Helper macro to sub two 32 aligned 64 bit numbers on 64 bit processor. + * + * @param[in] pSrc1 Pointer to NvU64_ALIGN32 source 1 structure. + * @param[in] pSrc2 Pointer to NvU64_ALIGN32 source 2 structure. + * @param[in/out] pDst Pointer to NvU64_ALIGN32 dest. structure. + */ +#define NvU64_ALIGN32_SUB(pDst, pSrc1, pSrc2) \ +do { \ + NvU64 __dst, __src1, __scr2; \ + \ + NvU64_ALIGN32_UNPACK(&__src1, (pSrc1)); \ + NvU64_ALIGN32_UNPACK(&__scr2, (pSrc2)); \ + __dst = __src1 - __scr2; \ + NvU64_ALIGN32_PACK((pDst), &__dst); \ +} while (NV_FALSE) + +/*! + * Structure for representing 32 bit aligned NvU64 (64-bit unsigned integer) + * structures. This structure must be used because the 32 bit processor and + * 64 bit processor compilers will pack/align NvU64 differently. + * + * One use case is RM being 64 bit proc whereas PMU being 32 bit proc, this + * alignment difference will result in corrupted transactions between the RM + * and PMU. + * + * See the @ref NvU64_ALIGN32_PACK and @ref NvU64_ALIGN32_UNPACK macros for + * packing and unpacking these structures. + * + * @note The intention of this structure is to provide a datatype which will + * packed/aligned consistently and efficiently across all platforms. + * We don't want to use "NV_DECLARE_ALIGNED(NvU64, 8)" because that + * leads to memory waste on our 32-bit uprocessors (e.g. FALCONs) where + * DMEM efficiency is vital. + */ +typedef struct +{ + /*! + * Low 32 bits. + */ + NvU32 lo; + /*! + * High 32 bits. + */ + NvU32 hi; +} NvU64_ALIGN32; + +/* Useful macro to hide required double cast */ +#define NV_PTR_TO_NvP64(n) (NvP64)(NvUPtr)(n) +#define NV_SIGN_EXT_PTR_TO_NvP64(p) ((NvP64)(NvS64)(NvSPtr)(p)) +#define KERNEL_POINTER_TO_NvP64(p) ((NvP64)(uintptr_t)(p)) + + /***************************************************************************\ +|* *| +|* Limits for common types. *| +|* *| + \***************************************************************************/ + +/* Explanation of the current form of these limits: + * + * - Decimal is used, as hex values are by default positive. + * - Casts are not used, as usage in the preprocessor itself (#if) ends poorly. + * - The subtraction of 1 for some MIN values is used to get around the fact + * that the C syntax actually treats -x as NEGATE(x) instead of a distinct + * number. Since 214748648 isn't a valid positive 32-bit signed value, we + * take the largest valid positive signed number, negate it, and subtract 1. + */ +#define NV_S8_MIN (-128) +#define NV_S8_MAX (+127) +#define NV_U8_MIN (0U) +#define NV_U8_MAX (+255U) +#define NV_S16_MIN (-32768) +#define NV_S16_MAX (+32767) +#define NV_U16_MIN (0U) +#define NV_U16_MAX (+65535U) +#define NV_S32_MIN (-2147483647 - 1) +#define NV_S32_MAX (+2147483647) +#define NV_U32_MIN (0U) +#define NV_U32_MAX (+4294967295U) +#define NV_S64_MIN (-9223372036854775807LL - 1LL) +#define NV_S64_MAX (+9223372036854775807LL) +#define NV_U64_MIN (0ULL) +#define NV_U64_MAX (+18446744073709551615ULL) + +/* Aligns fields in structs so they match up between 32 and 64 bit builds */ +#if defined(__GNUC__) || defined(__clang__) || defined(NV_QNX) +#define NV_ALIGN_BYTES(size) __attribute__ ((aligned (size))) +#elif defined(__arm) +#define NV_ALIGN_BYTES(size) __align(ALIGN) +#else +// XXX This is dangerously nonportable! We really shouldn't provide a default +// version of this that doesn't do anything. +#define NV_ALIGN_BYTES(size) +#endif + +// NV_DECLARE_ALIGNED() can be used on all platforms. +// This macro form accounts for the fact that __declspec on Windows is required +// before the variable type, +// and NV_ALIGN_BYTES is required after the variable name. +#if defined(__GNUC__) || defined(__clang__) || defined(NV_QNX) +#define NV_DECLARE_ALIGNED(TYPE_VAR, ALIGN) TYPE_VAR __attribute__ ((aligned (ALIGN))) +#elif defined(__arm) +#define NV_DECLARE_ALIGNED(TYPE_VAR, ALIGN) __align(ALIGN) TYPE_VAR +#endif + + /***************************************************************************\ +|* Function Declaration Types *| + \***************************************************************************/ + +// stretching the meaning of "nvtypes", but this seems to least offensive +// place to re-locate these from nvos.h which cannot be included by a number +// of builds that need them + + #if defined(__GNUC__) + #if (__GNUC__ > 3) || \ + ((__GNUC__ == 3) && (__GNUC_MINOR__ >= 1) && (__GNUC_PATCHLEVEL__ >= 1)) + #define NV_NOINLINE __attribute__((__noinline__)) + #endif + #elif defined(__clang__) + #if __has_attribute(noinline) + #define NV_NOINLINE __attribute__((__noinline__)) + #endif + #elif defined(__arm) && (__ARMCC_VERSION >= 300000) + #define NV_NOINLINE __attribute__((__noinline__)) + #elif (defined(__SUNPRO_C) && (__SUNPRO_C >= 0x590)) ||\ + (defined(__SUNPRO_CC) && (__SUNPRO_CC >= 0x590)) + #define NV_NOINLINE __attribute__((__noinline__)) + #elif defined (__INTEL_COMPILER) + #define NV_NOINLINE __attribute__((__noinline__)) + #endif + + #if !defined(NV_NOINLINE) + #define NV_NOINLINE + #endif + + /* GreenHills compiler defines __GNUC__, but doesn't support + * __inline__ keyword. */ + #if defined(__ghs__) + #define NV_INLINE inline + #elif defined(__GNUC__) || defined(__clang__) || defined(__INTEL_COMPILER) + #define NV_INLINE __inline__ + #elif defined (macintosh) || defined(__SUNPRO_C) || defined(__SUNPRO_CC) + #define NV_INLINE inline + #elif defined(__arm) + #define NV_INLINE __inline + #else + #define NV_INLINE + #endif + + /* Don't force inline on DEBUG builds -- it's annoying for debuggers. */ + #if !defined(DEBUG) + /* GreenHills compiler defines __GNUC__, but doesn't support + * __attribute__ or __inline__ keyword. */ + #if defined(__ghs__) + #define NV_FORCEINLINE inline + #elif defined(__GNUC__) + // GCC 3.1 and beyond support the always_inline function attribute. + #if (__GNUC__ > 3) || ((__GNUC__ == 3) && (__GNUC_MINOR__ >= 1)) + #define NV_FORCEINLINE __attribute__((__always_inline__)) __inline__ + #else + #define NV_FORCEINLINE __inline__ + #endif + #elif defined(__clang__) + #if __has_attribute(always_inline) + #define NV_FORCEINLINE __attribute__((__always_inline__)) __inline__ + #else + #define NV_FORCEINLINE __inline__ + #endif + #elif defined(__arm) && (__ARMCC_VERSION >= 220000) + // RVDS 2.2 also supports forceinline, but ADS 1.2 does not + #define NV_FORCEINLINE __forceinline + #else /* defined(__GNUC__) */ + #define NV_FORCEINLINE NV_INLINE + #endif + #else + #define NV_FORCEINLINE NV_INLINE + #endif + + #define NV_APIENTRY + #define NV_FASTCALL + #define NV_CDECLCALL + #define NV_STDCALL + + /* + * The 'warn_unused_result' function attribute prompts GCC to issue a + * warning if the result of a function tagged with this attribute + * is ignored by a caller. In combination with '-Werror', it can be + * used to enforce result checking in RM code; at this point, this + * is only done on UNIX. + */ + #if defined(__GNUC__) && defined(NV_UNIX) + #if (__GNUC__ > 3) || ((__GNUC__ == 3) && (__GNUC_MINOR__ >= 4)) + #define NV_FORCERESULTCHECK __attribute__((__warn_unused_result__)) + #else + #define NV_FORCERESULTCHECK + #endif + #elif defined(__clang__) + #if __has_attribute(warn_unused_result) + #define NV_FORCERESULTCHECK __attribute__((__warn_unused_result__)) + #else + #define NV_FORCERESULTCHECK + #endif + #else /* defined(__GNUC__) */ + #define NV_FORCERESULTCHECK + #endif + + #if defined(__GNUC__) || defined(__clang__) || defined(__INTEL_COMPILER) + #define NV_ATTRIBUTE_UNUSED __attribute__((__unused__)) + #else + #define NV_ATTRIBUTE_UNUSED + #endif + + /* + * Functions decorated with NV_FORMAT_PRINTF(f, a) have a format string at + * parameter number 'f' and variadic arguments start at parameter number 'a'. + * (Note that for C++ methods, there is an implicit 'this' parameter so + * explicit parameters are numbered from 2.) + */ + #if defined(__GNUC__) + #define NV_FORMAT_PRINTF(_f, _a) __attribute__((format(printf, _f, _a))) + #else + #define NV_FORMAT_PRINTF(_f, _a) + #endif + +#ifdef __cplusplus +} +#endif + +#endif /* NVTYPES_INCLUDED */ diff --git a/userspace/sdks/nv570/nvidia/inc/rmcd.h b/userspace/sdks/nv570/nvidia/inc/rmcd.h new file mode 100644 index 0000000..07d29ac --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/rmcd.h @@ -0,0 +1,393 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2002-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef RMCD_H +#define RMCD_H + +//****************************************************************************** +// +// Module Name: RMCD.H +// +// This file contains structures and constants that define the resource manager +// specific data for the crash dump file. The record definitions defined here +// are always stored after the crash dump file header. Each record defined here +// is preceded by the NVCD_RECORD structure. +// +//****************************************************************************** + +#include "nvgputypes.h" +#include "nvcd.h" + +#define NV_RMCD_VERSION (20) + +// Define RC Reset Callback function type +#define RM_RC_CALLBACK_HANDLE_UPDATE 1 +#if RM_RC_CALLBACK_HANDLE_UPDATE +typedef NvU32 RC_RESET_CALLBACK(NvHandle hClient, NvHandle hDevice, NvHandle hFifo, NvHandle hChannel, + void *pContext, NvBool clearRc); +#else +typedef NvU32 RC_RESET_CALLBACK(NvHandle hClient, NvHandle hDevice, NvHandle hChannel, void *pContext, NvBool clearRc); +#endif + +typedef struct _rc_error_context { + struct OBJGPU *pGpu; // GPU device + NvU32 ChId; // Channel ID of channel in RC recovery + NvU32 secChId; // Channel ID of secondary channel + NvHandle sechClient; // Client handle of secondary channel + NvU32 exceptType; // ROBUST_CHANNEL_* error identifier + NvU32 EngineId; // Engine ID of faulting engine + NvU32 subdeviceInstance; // This parameter returns the unicast subdevice instance number + // associated with the specified GPU. This value can be used to + // instantiate a unicast reference to the GPU using the NV20_SUBDEVICE + // classes. + + // FIFO_MMU_EXCEPTION_DATA + NvU32 addrLo; // MMU fault address (Lo) + NvU32 addrHi; // MMU fault address (Hi) + NvU32 faultType; // MMU fault code + const char *faultStr; // MMU fault string + +} RC_ERROR_CONTEXT, *PRC_ERROR_CONTEXT; + +#define MAX_FBBAS 0x2 +#define FBBA_MUX_SEL_MAX 0xF +#define FBBA_RXB_STATUS_SEL_MAX 0x10 +#define RDSTAT_MAX 0x2 + +// Define the resource manager group record types +typedef enum +{ + RmCurrentStateInfo_V2 = 4, // Revised Version 2 RM current state info. record + RmMissedNotifierInfo = 9, // RM Driver Indicates Missed Notifier + RmGlobalInfo_V3 = 10, // Revised Version 3 of Global Info + + RmProtoBuf = 131, // ProtoBuf + RmProtoBuf_V2 = 132, // ProtoBuf + NvDump + RmDclMsg = 133, // One of the optional DlcMsg fields, encoded + RmJournalEngDump = 134, + DP_ASSERT_HIT = 135, + DP_LOG_CALL = 136, + RmPrbFullDump = 137, // Full NvDump protobuf message + + // Includes RmRCCommonJournal_RECORD structure. + RmJournalBugCheck = 138, // Bugcheck record + RmRC2SwRmAssert_V3 = 139, // Retail logged RM_ASSERT info + RmRC2GpuTimeout_V3 = 140, // Retail logged RM_TIMEOUT events + RmRC2SwDbgBreakpoint_V3 = 141, // Uses same format as RmRC2SwRmAssert_V3 + RmBadRead_V2 = 142, // Record with Bad Read Information + RmSurpriseRemoval_V2 = 143, // Surprise Removal + RmPowerState = 144, // PowerState + RmPrbErrorInfo_V2 = 145, // Protobuf error record + RmPrbFullDump_V2 = 146, // Full NvDump protobuf message + RmRcDiagReport = 147, // Rc Diagnostic report message + RmNocatReport = 149, // Nocat reports. + RmDispState = 150, // Display error record + +} RMCD_RECORD_TYPE; + +typedef struct { + NVCD_RECORD Header; // Global information record header + NvU32 dwSize; // Total Protobuf Message Size +} RmProtoBuf_RECORD; +typedef RmProtoBuf_RECORD *PRmProtoBuf_RECORD; + +// +// Please include RmRCCommonJournal_RECORD structure at the top of all new and +// revised journal record structures. +// +#define NV_RM_JOURNAL_STATE_MASK_GC6_STATE 3:0 + +#define NV_RM_JOURNAL_STATE_MASK_IS_NOT_FULL_POWER 0x00000010 +#define NV_RM_JOURNAL_STATE_MASK_IS_NOT_CONNECTED 0x00000020 +#define NV_RM_JOURNAL_STATE_MASK_IS_IN_STANDBY 0x00000040 +#define NV_RM_JOURNAL_STATE_MASK_IS_IN_HIBERNATE 0x00000080 +#define NV_RM_JOURNAL_STATE_MASK_IS_IN_PM_CODEPATH 0x00000100 +#define NV_RM_JOURNAL_STATE_MASK_IS_IN_GC6_RESET 0x00000200 +#define NV_RM_JOURNAL_STATE_MASK_IS_IN_FULLCHIP_RESET 0x00000400 +#define NV_RM_JOURNAL_STATE_MASK_IS_IN_SEC_BUS_RESET 0x00000800 +#define NV_RM_JOURNAL_STATE_MASK_IS_IN_TIMEOUT_RECOVERY 0x00001000 +#define NV_RM_JOURNAL_STATE_MASK_IS_LOST 0x00002000 +#define NV_RM_JOURNAL_STATE_MASK_VIDMEM_FAILED_BAR0 0x00004000 +#define NV_RM_JOURNAL_STATE_MASK_VIDMEM_FAILED_BAR2 0x00008000 +#define NV_RM_JOURNAL_STATE_MASK_VIDMEM_FAILED_FBHUB 0x00010000 + + +typedef struct _RmRCCommonJournal_RECORD +{ + NVCD_RECORD Header; + NvU32 GPUTag; + NvU64 CPUTag; + NvU64 timeStamp NV_ALIGN_BYTES(8); + NvU64 stateMask; + NvU8 *pNext; // temporary link used for sorting. + // note using type NvU8 because Linux + // generated code does not properly + // resove the refeerence to the struct type. + // & balks about void * type. +} RmRCCommonJournal_RECORD; +typedef RmRCCommonJournal_RECORD *PRmRCCommonJournal_RECORD; + +// RM_ASSERT + DBG_BREAKPOINT info +typedef struct +{ + RmRCCommonJournal_RECORD common; + NvU64 lastTimeStamp NV_ALIGN_BYTES(8); + NvU64 breakpointAddrHint NV_ALIGN_BYTES(8); // address that can identify bp module + NvU64 callStack[10] NV_ALIGN_BYTES(8); // Call stack when the assert occurred. + NvU32 count; + NvU32 lineNum; + NvU32 lastReportedCount; // last count reported to NOCAT + NvU64 nextReportedTimeStamp; // time stamp to use as start time for the + // next NOCAT report. +} RmRCCommonAssert_RECORD; +typedef RmRCCommonAssert_RECORD *PRmRCCommonAssert_RECORD; +#define NV_RM_ASSERT_UNKNOWN_LINE_NUM 0 + +typedef RmRCCommonAssert_RECORD RmRC2GpuTimeout3_RECORD; +typedef RmRC2GpuTimeout3_RECORD *PRmRC2GpuTimeout3_RECORD; + +// How Serious is this RM_ASSERT/DBG_BREAKPOINT +// (1) Info -- This is unexpected but we should continue to run +// (2) Error -- +// (3) Fatal -- This is hopeless -- FBI Timeout, Bus Error Etc +#define NV_RM_ASSERT_TYPE 3:0 +#define NV_RM_ASSERT_TYPE_INFO 0x00000001 +#define NV_RM_ASSERT_TYPE_ERROR 0x00000002 +#define NV_RM_ASSERT_TYPE_FATAL 0x00000003 + +// HW Unit which is having the issue +#define NV_RM_ASSERT_HW_UNIT 15:8 +#define NV_RM_ASSERT_HW_UNIT_NULL (0x00) +#define NV_RM_ASSERT_HW_UNIT_GRAPHICS (0x01) +#define NV_RM_ASSERT_HW_UNIT_COPY0 (0x02) +#define NV_RM_ASSERT_HW_UNIT_COPY1 (0x03) +#define NV_RM_ASSERT_HW_UNIT_VP (0x04) +#define NV_RM_ASSERT_HW_UNIT_ME (0x05) +#define NV_RM_ASSERT_HW_UNIT_PPP (0x06) +#define NV_RM_ASSERT_HW_UNIT_BSP (0x07) +#define NV_RM_ASSERT_HW_UNIT_NVDEC0 NV_RM_ASSERT_HW_UNIT_BSP +#define NV_RM_ASSERT_HW_UNIT_MPEG (0x08) +#define NV_RM_ASSERT_HW_UNIT_SW (0x09) +#define NV_RM_ASSERT_HW_UNIT_CIPHER (0x0a) +#define NV_RM_ASSERT_HW_UNIT_VIC (0x0b) +#define NV_RM_ASSERT_HW_UNIT_MSENC (0x0c) +#define NV_RM_ASSERT_HW_UNIT_NVENC0 NV_RM_ASSERT_HW_UNIT_MSENC +#define NV_RM_ASSERT_HW_UNIT_NVENC1 (0x0d) +#define NV_RM_ASSERT_HW_UNIT_HOST (0x0e) +#define NV_RM_ASSERT_HW_UNIT_ROM (0x0f) +#define NV_RM_ASSERT_HW_UNIT_INSTMEM (0x10) +#define NV_RM_ASSERT_HW_UNIT_DISP (0x11) +#define NV_RM_ASSERT_HW_UNIT_NVENC2 (0x12) +#define NV_RM_ASSERT_HW_UNIT_NVDEC1 (0x13) +#define NV_RM_ASSERT_HW_UNIT_NVDEC2 (0x14) +#define NV_RM_ASSERT_HW_UNIT_NVDEC3 (0x15) +#define NV_RM_ASSERT_HW_UNIT_NVDEC4 (0x16) +#define NV_RM_ASSERT_HW_UNIT_NVDEC5 (0x17) +#define NV_RM_ASSERT_HW_UNIT_NVDEC6 (0x18) +#define NV_RM_ASSERT_HW_UNIT_NVDEC7 (0x19) +#define NV_RM_ASSERT_HW_UNIT_ALLENGINES (0xff) +// SW Module which generated the error +#define NV_RM_ASSERT_SW_MODULE 15:8 + +// This is a specific error number which we wish to follow regardless of builds +// We want to use this for backend processing +// This is also a compromise. Ideally, each event would have a unique id but +// instead of doing this we use EIP which is unique per load. If we subtracted off +// the Module Load Address then it would be unique per build, Using EIP allows us +// to use the debugger to lookup the source code that corresponds to the event. +#define NV_RM_ASSERT_LEVEL_TAG 30:16 +// Host Errors +#define NV_RM_ASSERT_LEVEL_TAG_BAR1_PAGE_FAULT (0x0001) +#define NV_RM_ASSERT_LEVEL_TAG_IFB_PAGE_FAULT (0x0002) +#define NV_RM_ASSERT_LEVEL_TAG_PIO_ERROR (0x0003) +#define NV_RM_ASSERT_LEVEL_TAG_CHSW_SAVE_INVALID (0x0004) +#define NV_RM_ASSERT_LEVEL_TAG_CHSW_ERROR (0x0005) +#define NV_RM_ASSERT_LEVEL_TAG_FBIRD_TIMEOUT (0x0006) +#define NV_RM_ASSERT_LEVEL_TAG_CPUQ_FBIBUSY_TIMEOUT (0x0007) +#define NV_RM_ASSERT_LEVEL_TAG_CHSW_FSM_TIMEOUT (0x0008) +#define NV_RM_ASSERT_LEVEL_TAG_FB_FLUSH_TIMEOUT (0x0009) +#define NV_RM_ASSERT_LEVEL_TAG_P2PSTATE_TIMEOUT (0x000a) +#define NV_RM_ASSERT_LEVEL_TAG_VBIOS_CHECKSUM (0x000b) +#define NV_RM_ASSERT_LEVEL_TAG_DISP_SYNC (0x000c) + +// What is the generating Source -- GPU or SW +#define NV_RM_ASSERT_LEVEL_SOURCE 31:31 +#define NV_RM_ASSERT_LEVEL_SOURCE_SW 0x00000000 +#define NV_RM_ASSERT_LEVEL_SOURCE_HW 0x00000001 + + +// RM_ASSERT + DBG_BREAKPOINT info +typedef struct +{ + RmRCCommonAssert_RECORD commonAssert; + NvU32 level; +} RmRC2SwRmAssert3_RECORD; +typedef RmRC2SwRmAssert3_RECORD *PRmRC2SwRmAssert3_RECORD; + +// RM JOURNAL BUG CHECK +typedef struct +{ + RmRCCommonJournal_RECORD common; + NvU32 bugCheckCode; +} RmJournalBugcheck_RECORD, *PRmJournalBugcheck_RECORD; + +typedef struct +{ + NVCD_RECORD Header; + NvS32 GpuTemp; + NvS32 LocTemp; +} RmRC2TempReading_RECORD; +typedef RmRC2TempReading_RECORD *PRmRC2TempReading_RECORD; + +typedef enum { + MEMORY_BAR0 = 1, + MEMORY_FB, + MEMORY_INSTANCE, + MEMORY_PCI, +} RMCD_BAD_READ_SPACE; + +typedef struct +{ + RmRCCommonJournal_RECORD common; + NvU32 MemorySpace; // Which Memory Space + NvU32 Offset; // Offset in Memory Space + NvU32 Mask; // Mask used to detect bad read + NvU32 Value; // Value Return + NvU32 Reason; // Potential Reason why this might have happened +} RmRC2BadRead2_RECORD; + +typedef RmRC2BadRead2_RECORD *PRmRC2BadRead2_RECORD; + +typedef struct +{ + RmRCCommonJournal_RECORD common; + NvU32 hostEngTag; + NvU32 exceptType; + NvU32 exceptLevel; +} RmRCRecovery_RECORD; + +typedef RmRCRecovery_RECORD *PRmRCRecovery_RECORD; + +typedef struct +{ + RmRCCommonJournal_RECORD common; +} RmPrbInfo_RECORD_V2, *PRmPrbInfo_RECORD_V2; + +// Counters per type of RC Error. WIll only keep first n (10) types. +#define MAX_RC_ERROR_COUNTER 10 +#define RC_ERROR_COUNTER_OTHER_INDEX MAX_RC_ERROR_COUNTER-1 +#define RC_ERROR_COUNTER_TYPE_INVALID ((NvU32)(~0)) +#define RC_ERROR_COUNTER_OTHER_TYPE 1024 + +typedef struct +{ + NvU32 rcFaultType; + NvU32 rcErrorSrc; + NvU64 mmuFaultVA; + NvU32 mmuAccessType; +} rcExtraMMUInfo; + +typedef struct +{ + NvU32 rcGRErrType; + NvU32 rcGRExcptnSubTyp; +} rcExtraGRInfo; + +typedef struct +{ + NvU32 rcPBDMAID; + NvU64 rcPBDMAErrFlag; +} rcExtraPBDMAInfo; + +/* +* Union for storing extra data values for each kind of RC Error +* +* MMU +* ===== +* rcFaultType +* rcErrorSrc +* +* GR +* ======= +* rcGRErrType +* rcGRExcptnSubTyp +* +* PBDMA +* ========= +* rcPBDMAID +* rcPBDMAErrFlag +*/ + +typedef union +{ + rcExtraMMUInfo rcMMUData; + rcExtraGRInfo rcGRData; + rcExtraPBDMAInfo rcPBDMAData; +} rcExtraInfo; + +typedef struct +{ + NvU32 rcErrorType; + NvU32 rcErrorCount; + NvU32 rcLastCHID; + NvU64 rcLastTime; + rcExtraInfo rcExtrInfo; +} rcErrorCounterEntry; + +typedef struct +{ + NvU32 powerEvent; // The name of the point we are tracing + // Such as NVRM_OCA_PWR_EVENT_SET_POWER_ENTRY + NvU32 powerState; + NvU32 fastBootPowerState; // Tracking fast boot shutdown/hibernate states +} RmPowerState_RECORD, *PRmPowerState_RECORD; + +#define MAX_RCDB_RCDIAG_ENTRIES 200 +typedef struct +{ + NvU32 offset; + NvU32 tag; + NvU32 value; + NvU32 attribute; +} RmRcDiagRecordEntry; + +#define RCDB_RCDIAG_DEFAULT_OWNER 0 +typedef struct +{ + NvU16 idx; + NvU32 timeStamp; // time in seconds since 1/1/1970 + NvU16 type; + NvU32 flags; + NvU16 count; + NvU32 owner; // a handle indicating the ownership + NvU32 processId; // process Id of the originating process. + RmRcDiagRecordEntry data[MAX_RCDB_RCDIAG_ENTRIES]; +} RmRcDiag_RECORD, *PRmRcDiag_RECORD; + +#define MAX_RCDB_RCDIAG_WRAP_BUFF 32 +#define INVALID_RCDB_RCDIAG_INDEX 0xffffffff + +#define MAX_RCDB_NOCAT_WRAP_BUFF 100 +#define INVALID_RCDB_NOCAT_ID 0xffffffff + +#endif // RMCD_H diff --git a/userspace/sdks/nv570/nvidia/inc/rs_access.h b/userspace/sdks/nv570/nvidia/inc/rs_access.h new file mode 100644 index 0000000..7c71a78 --- /dev/null +++ b/userspace/sdks/nv570/nvidia/inc/rs_access.h @@ -0,0 +1,272 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: rs_access.finn +// + + + + +#include "nvtypes.h" +#include "nvmisc.h" + + +/****************************************************************************/ +/* Access right definitions */ +/****************************************************************************/ + +// +// The meaning of each access right is documented in +// resman/docs/rmapi/resource_server/rm_capabilities.adoc +// +// RS_ACCESS_COUNT is the number of access rights that have been defined +// and are in use. All integers in the range [0, RS_ACCESS_COUNT) should +// represent valid access rights. +// +// When adding a new access right, don't forget to update +// 1) The descriptions in the resman/docs/rmapi/resource_server/rm_capabilities.adoc +// 2) RS_ACCESS_COUNT, defined below +// 3) The declaration of g_rsAccessMetadata in rs_access_rights.c +// 4) The list of access rights in drivers/common/chip-config/Chipcontrols.pm +// 5) Any relevant access right callbacks +// + +#define RS_ACCESS_DUP_OBJECT 0U +#define RS_ACCESS_NICE 1U +#define RS_ACCESS_DEBUG 2U +#define RS_ACCESS_COUNT 3U + + +/****************************************************************************/ +/* Access right data structures */ +/****************************************************************************/ + +/*! + * @brief A type that can be used to represent any access right. + */ +typedef NvU16 RsAccessRight; + +/*! + * @brief An internal type used to represent one limb in an access right mask. + */ +typedef NvU32 RsAccessLimb; +#define SDK_RS_ACCESS_LIMB_BITS 32 + +/*! + * @brief The number of limbs in the RS_ACCESS_MASK struct. + */ +#define SDK_RS_ACCESS_MAX_LIMBS 1 + +/*! + * @brief The maximum number of possible access rights supported by the + * current data structure definition. + * + * You probably want RS_ACCESS_COUNT instead, which is the number of actual + * access rights defined. + */ +#define SDK_RS_ACCESS_MAX_COUNT (0x20) /* finn: Evaluated from "(SDK_RS_ACCESS_LIMB_BITS * SDK_RS_ACCESS_MAX_LIMBS)" */ + +/** + * @brief A struct representing a set of access rights. + * + * Note that the values of bit positions larger than RS_ACCESS_COUNT is + * undefined, and should not be assumed to be 0 (see RS_ACCESS_MASK_FILL). + */ +typedef struct RS_ACCESS_MASK { + RsAccessLimb limbs[SDK_RS_ACCESS_MAX_LIMBS]; +} RS_ACCESS_MASK; + +/** + * @brief A struct representing auxiliary information about each access right. + */ +typedef struct RS_ACCESS_INFO { + NvU32 flags; +} RS_ACCESS_INFO; + + +/****************************************************************************/ +/* Access right macros */ +/****************************************************************************/ + +#define SDK_RS_ACCESS_LIMB_INDEX(index) ((index) / SDK_RS_ACCESS_LIMB_BITS) +#define SDK_RS_ACCESS_LIMB_POS(index) ((index) % SDK_RS_ACCESS_LIMB_BITS) + +#define SDK_RS_ACCESS_LIMB_ELT(pAccessMask, index) \ + ((pAccessMask)->limbs[SDK_RS_ACCESS_LIMB_INDEX(index)]) +#define SDK_RS_ACCESS_OFFSET_MASK(index) \ + NVBIT_TYPE(SDK_RS_ACCESS_LIMB_POS(index), RsAccessLimb) + +/*! + * @brief Checks that accessRight represents a valid access right. + * + * The valid range of access rights is [0, RS_ACCESS_COUNT). + * + * @param[in] accessRight The access right value to check + * + * @return true if accessRight is valid + * @return false otherwise + */ +#define RS_ACCESS_BOUNDS_CHECK(accessRight) \ + (accessRight < RS_ACCESS_COUNT) + +/*! + * @brief Test whether an access right is present in a set + * + * @param[in] pAccessMask The set of access rights to read + * @param[in] index The access right to examine + * + * @return NV_TRUE if the access right specified by index was present in the set, + * and NV_FALSE otherwise + */ +#define RS_ACCESS_MASK_TEST(pAccessMask, index) \ + (RS_ACCESS_BOUNDS_CHECK(index) && \ + (SDK_RS_ACCESS_LIMB_ELT(pAccessMask, index) & SDK_RS_ACCESS_OFFSET_MASK(index)) != 0) + +/*! + * @brief Add an access right to a mask + * + * @param[in] pAccessMask The set of access rights to modify + * @param[in] index The access right to set + */ +#define RS_ACCESS_MASK_ADD(pAccessMask, index) \ + do \ + { \ + if (RS_ACCESS_BOUNDS_CHECK(index)) { \ + SDK_RS_ACCESS_LIMB_ELT(pAccessMask, index) |= SDK_RS_ACCESS_OFFSET_MASK(index); \ + } \ + } while (NV_FALSE) + +/*! + * @brief Remove an access right from a mask + * + * @param[in] pAccessMask The set of access rights to modify + * @param[in] index The access right to unset + */ +#define RS_ACCESS_MASK_REMOVE(pAccessMask, index) \ + do \ + { \ + if (RS_ACCESS_BOUNDS_CHECK(index)) { \ + SDK_RS_ACCESS_LIMB_ELT(pAccessMask, index) &= ~SDK_RS_ACCESS_OFFSET_MASK(index); \ + } \ + } while (NV_FALSE) + +/*! + * @brief Performs an in-place union between two access right masks + * + * @param[in,out] pMaskOut The access rights mask to be updated + * @param[in] pMaskIn The set of access rights to be added to pMaskOut + */ +#define RS_ACCESS_MASK_UNION(pMaskOut, pMaskIn) \ + do \ + { \ + NvLength limb; \ + for (limb = 0; limb < SDK_RS_ACCESS_MAX_LIMBS; limb++) \ + { \ + SDK_RS_ACCESS_LIMB_ELT(pMaskOut, limb) |= SDK_RS_ACCESS_LIMB_ELT(pMaskIn, limb); \ + } \ + } while (NV_FALSE) + +/*! + * @brief Performs an in-place subtract of one mask's rights from another + * + * @param[in,out] pMaskOut The access rights mask to be updated + * @param[in] pMaskIn The set of access rights to be removed from pMaskOut + */ +#define RS_ACCESS_MASK_SUBTRACT(pMaskOut, pMaskIn) \ + do \ + { \ + NvLength limb; \ + for (limb = 0; limb < SDK_RS_ACCESS_MAX_LIMBS; limb++) \ + { \ + SDK_RS_ACCESS_LIMB_ELT(pMaskOut, limb) &= ~SDK_RS_ACCESS_LIMB_ELT(pMaskIn, limb); \ + } \ + } while (NV_FALSE) + +/*! + * @brief Removes all rights from an access rights mask + * + * @param[in,out] pAccessMask The access rights mask to be updated + */ +#define RS_ACCESS_MASK_CLEAR(pAccessMask) \ + do \ + { \ + portMemSet(pAccessMask, 0, sizeof(*pAccessMask)); \ + } while (NV_FALSE) + +/*! + * @brief Adds all rights to an access rights mask + * + * @param[in,out] pAccessMask The access rights mask to be updated + */ +#define RS_ACCESS_MASK_FILL(pAccessMask) \ + do \ + { \ + portMemSet(pAccessMask, 0xff, sizeof(*pAccessMask)); \ + } while (NV_FALSE) + + +/****************************************************************************/ +/* Share definitions */ +/****************************************************************************/ + +// +// The usage of Share Policy and the meaning of each share type is documented in +// resman/docs/rmapi/resource_server/rm_capabilities.adoc +// +#define RS_SHARE_TYPE_NONE (0U) +#define RS_SHARE_TYPE_ALL (1U) +#define RS_SHARE_TYPE_OS_SECURITY_TOKEN (2U) +#define RS_SHARE_TYPE_CLIENT (3U) +#define RS_SHARE_TYPE_PID (4U) +#define RS_SHARE_TYPE_SMC_PARTITION (5U) +#define RS_SHARE_TYPE_GPU (6U) +#define RS_SHARE_TYPE_FM_CLIENT (7U) +// Must be last. Update when a new SHARE_TYPE is added +#define RS_SHARE_TYPE_MAX (8U) + + +// +// Use Revoke to remove an existing policy from the list. +// Allow is based on OR logic, Require is based on AND logic. +// To share a right, at least one Allow (non-Require) must match, and all Require must pass. +// If Compose is specified, policies will be added to the list. Otherwise, they will replace the list. +// +#define RS_SHARE_ACTION_FLAG_REVOKE NVBIT(0) +#define RS_SHARE_ACTION_FLAG_REQUIRE NVBIT(1) +#define RS_SHARE_ACTION_FLAG_COMPOSE NVBIT(2) + +/****************************************************************************/ +/* Share flag data structures */ +/****************************************************************************/ + +typedef struct RS_SHARE_POLICY { + NvU32 target; + RS_ACCESS_MASK accessMask; + NvU16 type; ///< RS_SHARE_TYPE_ + NvU8 action; ///< RS_SHARE_ACTION_ +} RS_SHARE_POLICY; diff --git a/userspace/sdks/nv570/nvml/nvml.h b/userspace/sdks/nv570/nvml/nvml.h new file mode 100644 index 0000000..03e092d --- /dev/null +++ b/userspace/sdks/nv570/nvml/nvml.h @@ -0,0 +1,9664 @@ +/*** NVML VERSION: 12.0.76 ***/ +/*** From https://api.anaconda.org/download/nvidia/cuda-nvml-dev/12.0.76/linux-64/cuda-nvml-dev-12.0.76-0.tar.bz2 ***/ +/* + * Copyright 1993-2022 NVIDIA Corporation. All rights reserved. + * + * NOTICE TO USER: + * + * This source code is subject to NVIDIA ownership rights under U.S. and + * international Copyright laws. Users and possessors of this source code + * are hereby granted a nonexclusive, royalty-free license to use this code + * in individual and commercial software. + * + * NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE + * CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR + * IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE. + * IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS + * OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE + * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE + * OR PERFORMANCE OF THIS SOURCE CODE. + * + * U.S. Government End Users. This source code is a "commercial item" as + * that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of + * "commercial computer software" and "commercial computer software + * documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995) + * and is provided to the U.S. Government only as a commercial end item. + * Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through + * 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the + * source code with only those rights set forth herein. + * + * Any use of this source code in individual and commercial software must + * include, in the user documentation and internal comments to the code, + * the above Disclaimer and U.S. Government End Users Notice. + */ + +/* +NVML API Reference + +The NVIDIA Management Library (NVML) is a C-based programmatic interface for monitoring and +managing various states within NVIDIA Tesla &tm; GPUs. It is intended to be a platform for building +3rd party applications, and is also the underlying library for the NVIDIA-supported nvidia-smi +tool. NVML is thread-safe so it is safe to make simultaneous NVML calls from multiple threads. + +API Documentation + +Supported platforms: +- Windows: Windows Server 2008 R2 64bit, Windows Server 2012 R2 64bit, Windows 7 64bit, Windows 8 64bit, Windows 10 64bit +- Linux: 32-bit and 64-bit +- Hypervisors: Windows Server 2008R2/2012 Hyper-V 64bit, Citrix XenServer 6.2 SP1+, VMware ESX 5.1/5.5 + +Supported products: +- Full Support + - All Tesla products, starting with the Fermi architecture + - All Quadro products, starting with the Fermi architecture + - All vGPU Software products, starting with the Kepler architecture + - Selected GeForce Titan products +- Limited Support + - All Geforce products, starting with the Fermi architecture + +The NVML library can be found at \%ProgramW6432\%\\"NVIDIA Corporation"\\NVSMI\\ on Windows. It is +not be added to the system path by default. To dynamically link to NVML, add this path to the PATH +environmental variable. To dynamically load NVML, call LoadLibrary with this path. + +On Linux the NVML library will be found on the standard library path. For 64 bit Linux, both the 32 bit +and 64 bit NVML libraries will be installed. + +Online documentation for this library is available at http://docs.nvidia.com/deploy/nvml-api/index.html +*/ + +#ifndef __nvml_nvml_h__ +#define __nvml_nvml_h__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * On Windows, set up methods for DLL export + * define NVML_STATIC_IMPORT when using nvml_loader library + */ +#if defined _WINDOWS + #if !defined NVML_STATIC_IMPORT + #if defined NVML_LIB_EXPORT + #define DECLDIR __declspec(dllexport) + #else + #define DECLDIR __declspec(dllimport) + #endif + #else + #define DECLDIR + #endif +#else + #define DECLDIR +#endif + +/** + * NVML API versioning support + */ +#define NVML_API_VERSION 11 +#define NVML_API_VERSION_STR "11" +/** + * Defining NVML_NO_UNVERSIONED_FUNC_DEFS will disable "auto upgrading" of APIs. + * e.g. the user will have to call nvmlInit_v2 instead of nvmlInit. Enable this + * guard if you need to support older versions of the API + */ +#ifndef NVML_NO_UNVERSIONED_FUNC_DEFS + #define nvmlInit nvmlInit_v2 + #define nvmlDeviceGetPciInfo nvmlDeviceGetPciInfo_v3 + #define nvmlDeviceGetCount nvmlDeviceGetCount_v2 + #define nvmlDeviceGetHandleByIndex nvmlDeviceGetHandleByIndex_v2 + #define nvmlDeviceGetHandleByPciBusId nvmlDeviceGetHandleByPciBusId_v2 + #define nvmlDeviceGetNvLinkRemotePciInfo nvmlDeviceGetNvLinkRemotePciInfo_v2 + #define nvmlDeviceRemoveGpu nvmlDeviceRemoveGpu_v2 + #define nvmlDeviceGetGridLicensableFeatures nvmlDeviceGetGridLicensableFeatures_v4 + #define nvmlEventSetWait nvmlEventSetWait_v2 + #define nvmlDeviceGetAttributes nvmlDeviceGetAttributes_v2 + #define nvmlComputeInstanceGetInfo nvmlComputeInstanceGetInfo_v2 + #define nvmlDeviceGetComputeRunningProcesses nvmlDeviceGetComputeRunningProcesses_v3 + #define nvmlDeviceGetGraphicsRunningProcesses nvmlDeviceGetGraphicsRunningProcesses_v3 + #define nvmlDeviceGetMPSComputeRunningProcesses nvmlDeviceGetMPSComputeRunningProcesses_v3 + #define nvmlBlacklistDeviceInfo_t nvmlExcludedDeviceInfo_t + #define nvmlGetBlacklistDeviceCount nvmlGetExcludedDeviceCount + #define nvmlGetBlacklistDeviceInfoByIndex nvmlGetExcludedDeviceInfoByIndex + #define nvmlDeviceGetGpuInstancePossiblePlacements nvmlDeviceGetGpuInstancePossiblePlacements_v2 + #define nvmlVgpuInstanceGetLicenseInfo nvmlVgpuInstanceGetLicenseInfo_v2 +#endif // #ifndef NVML_NO_UNVERSIONED_FUNC_DEFS + +#define NVML_STRUCT_VERSION(data, ver) (unsigned int)(sizeof(nvml ## data ## _v ## ver ## _t) | \ + (ver << 24U)) + +/***************************************************************************************************/ +/** @defgroup nvmlDeviceStructs Device Structs + * @{ + */ +/***************************************************************************************************/ + +/** + * Special constant that some fields take when they are not available. + * Used when only part of the struct is not available. + * + * Each structure explicitly states when to check for this value. + */ +#define NVML_VALUE_NOT_AVAILABLE (-1) + +typedef struct nvmlDevice_st* nvmlDevice_t; + +/** + * Buffer size guaranteed to be large enough for pci bus id + */ +#define NVML_DEVICE_PCI_BUS_ID_BUFFER_SIZE 32 + +/** + * Buffer size guaranteed to be large enough for pci bus id for ::busIdLegacy + */ +#define NVML_DEVICE_PCI_BUS_ID_BUFFER_V2_SIZE 16 + +/** + * PCI information about a GPU device. + */ +typedef struct nvmlPciInfo_st +{ + char busIdLegacy[NVML_DEVICE_PCI_BUS_ID_BUFFER_V2_SIZE]; //!< The legacy tuple domain:bus:device.function PCI identifier (& NULL terminator) + unsigned int domain; //!< The PCI domain on which the device's bus resides, 0 to 0xffffffff + unsigned int bus; //!< The bus on which the device resides, 0 to 0xff + unsigned int device; //!< The device's id on the bus, 0 to 31 + unsigned int pciDeviceId; //!< The combined 16-bit device id and 16-bit vendor id + + // Added in NVML 2.285 API + unsigned int pciSubSystemId; //!< The 32-bit Sub System Device ID + + char busId[NVML_DEVICE_PCI_BUS_ID_BUFFER_SIZE]; //!< The tuple domain:bus:device.function PCI identifier (& NULL terminator) +} nvmlPciInfo_t; + +/** + * PCI format string for ::busIdLegacy + */ +#define NVML_DEVICE_PCI_BUS_ID_LEGACY_FMT "%04X:%02X:%02X.0" + +/** + * PCI format string for ::busId + */ +#define NVML_DEVICE_PCI_BUS_ID_FMT "%08X:%02X:%02X.0" + +/** + * Utility macro for filling the pci bus id format from a nvmlPciInfo_t + */ +#define NVML_DEVICE_PCI_BUS_ID_FMT_ARGS(pciInfo) (pciInfo)->domain, \ + (pciInfo)->bus, \ + (pciInfo)->device + +/** + * Detailed ECC error counts for a device. + * + * @deprecated Different GPU families can have different memory error counters + * See \ref nvmlDeviceGetMemoryErrorCounter + */ +typedef struct nvmlEccErrorCounts_st +{ + unsigned long long l1Cache; //!< L1 cache errors + unsigned long long l2Cache; //!< L2 cache errors + unsigned long long deviceMemory; //!< Device memory errors + unsigned long long registerFile; //!< Register file errors +} nvmlEccErrorCounts_t; + +/** + * Utilization information for a device. + * Each sample period may be between 1 second and 1/6 second, depending on the product being queried. + */ +typedef struct nvmlUtilization_st +{ + unsigned int gpu; //!< Percent of time over the past sample period during which one or more kernels was executing on the GPU + unsigned int memory; //!< Percent of time over the past sample period during which global (device) memory was being read or written +} nvmlUtilization_t; + +/** + * Memory allocation information for a device (v1). + * The total amount is equal to the sum of the amounts of free and used memory. + */ +typedef struct nvmlMemory_st +{ + unsigned long long total; //!< Total physical device memory (in bytes) + unsigned long long free; //!< Unallocated device memory (in bytes) + unsigned long long used; //!< Sum of Reserved and Allocated device memory (in bytes). + //!< Note that the driver/GPU always sets aside a small amount of memory for bookkeeping +} nvmlMemory_t; + +/** + * Memory allocation information for a device (v2). + * + * Version 2 adds versioning for the struct and the amount of system-reserved memory as an output. + * @note The \ref nvmlMemory_v2_t.used amount also includes the \ref nvmlMemory_v2_t.reserved amount. + */ +typedef struct nvmlMemory_v2_st +{ + unsigned int version; //!< Structure format version (must be 2) + unsigned long long total; //!< Total physical device memory (in bytes) + unsigned long long reserved; //!< Device memory (in bytes) reserved for system use (driver or firmware) + unsigned long long free; //!< Unallocated device memory (in bytes) + unsigned long long used; //!< Allocated device memory (in bytes). Note that the driver/GPU always sets aside a small amount of memory for bookkeeping +} nvmlMemory_v2_t; + +#define nvmlMemory_v2 NVML_STRUCT_VERSION(Memory, 2) + +/** + * BAR1 Memory allocation Information for a device + */ +typedef struct nvmlBAR1Memory_st +{ + unsigned long long bar1Total; //!< Total BAR1 Memory (in bytes) + unsigned long long bar1Free; //!< Unallocated BAR1 Memory (in bytes) + unsigned long long bar1Used; //!< Allocated Used Memory (in bytes) +}nvmlBAR1Memory_t; + +/** + * Information about running compute processes on the GPU, legacy version + * for older versions of the API. + */ +typedef struct nvmlProcessInfo_v1_st +{ + unsigned int pid; //!< Process ID + unsigned long long usedGpuMemory; //!< Amount of used GPU memory in bytes. + //! Under WDDM, \ref NVML_VALUE_NOT_AVAILABLE is always reported + //! because Windows KMD manages all the memory and not the NVIDIA driver +} nvmlProcessInfo_v1_t; + +/** + * Information about running compute processes on the GPU + */ +typedef struct nvmlProcessInfo_v2_st +{ + unsigned int pid; //!< Process ID + unsigned long long usedGpuMemory; //!< Amount of used GPU memory in bytes. + //! Under WDDM, \ref NVML_VALUE_NOT_AVAILABLE is always reported + //! because Windows KMD manages all the memory and not the NVIDIA driver + unsigned int gpuInstanceId; //!< If MIG is enabled, stores a valid GPU instance ID. gpuInstanceId is set to + // 0xFFFFFFFF otherwise. + unsigned int computeInstanceId; //!< If MIG is enabled, stores a valid compute instance ID. computeInstanceId is set to + // 0xFFFFFFFF otherwise. +} nvmlProcessInfo_v2_t; + +/** + * Information about running compute processes on the GPU + * Version 2 adds versioning for the struct + */ +typedef struct nvmlProcessInfo_st +{ + unsigned int pid; //!< Process ID + unsigned long long usedGpuMemory; //!< Amount of used GPU memory in bytes. + //! Under WDDM, \ref NVML_VALUE_NOT_AVAILABLE is always reported + //! because Windows KMD manages all the memory and not the NVIDIA driver + unsigned int gpuInstanceId; //!< If MIG is enabled, stores a valid GPU instance ID. gpuInstanceId is set to + // 0xFFFFFFFF otherwise. + unsigned int computeInstanceId; //!< If MIG is enabled, stores a valid compute instance ID. computeInstanceId is set to + // 0xFFFFFFFF otherwise. +} nvmlProcessInfo_t; + +typedef struct nvmlDeviceAttributes_st +{ + unsigned int multiprocessorCount; //!< Streaming Multiprocessor count + unsigned int sharedCopyEngineCount; //!< Shared Copy Engine count + unsigned int sharedDecoderCount; //!< Shared Decoder Engine count + unsigned int sharedEncoderCount; //!< Shared Encoder Engine count + unsigned int sharedJpegCount; //!< Shared JPEG Engine count + unsigned int sharedOfaCount; //!< Shared OFA Engine count + unsigned int gpuInstanceSliceCount; //!< GPU instance slice count + unsigned int computeInstanceSliceCount; //!< Compute instance slice count + unsigned long long memorySizeMB; //!< Device memory size (in MiB) +} nvmlDeviceAttributes_t; + +/** + * Possible values that classify the remap availability for each bank. The max + * field will contain the number of banks that have maximum remap availability + * (all reserved rows are available). None means that there are no reserved + * rows available. + */ +typedef struct nvmlRowRemapperHistogramValues_st +{ + unsigned int max; + unsigned int high; + unsigned int partial; + unsigned int low; + unsigned int none; +} nvmlRowRemapperHistogramValues_t; + +/** + * Enum to represent type of bridge chip + */ +typedef enum nvmlBridgeChipType_enum +{ + NVML_BRIDGE_CHIP_PLX = 0, + NVML_BRIDGE_CHIP_BRO4 = 1 +}nvmlBridgeChipType_t; + +/** + * Maximum number of NvLink links supported + */ +#define NVML_NVLINK_MAX_LINKS 18 + +/** + * Enum to represent the NvLink utilization counter packet units + */ +typedef enum nvmlNvLinkUtilizationCountUnits_enum +{ + NVML_NVLINK_COUNTER_UNIT_CYCLES = 0, // count by cycles + NVML_NVLINK_COUNTER_UNIT_PACKETS = 1, // count by packets + NVML_NVLINK_COUNTER_UNIT_BYTES = 2, // count by bytes + NVML_NVLINK_COUNTER_UNIT_RESERVED = 3, // count reserved for internal use + // this must be last + NVML_NVLINK_COUNTER_UNIT_COUNT +} nvmlNvLinkUtilizationCountUnits_t; + +/** + * Enum to represent the NvLink utilization counter packet types to count + * ** this is ONLY applicable with the units as packets or bytes + * ** as specified in \a nvmlNvLinkUtilizationCountUnits_t + * ** all packet filter descriptions are target GPU centric + * ** these can be "OR'd" together + */ +typedef enum nvmlNvLinkUtilizationCountPktTypes_enum +{ + NVML_NVLINK_COUNTER_PKTFILTER_NOP = 0x1, // no operation packets + NVML_NVLINK_COUNTER_PKTFILTER_READ = 0x2, // read packets + NVML_NVLINK_COUNTER_PKTFILTER_WRITE = 0x4, // write packets + NVML_NVLINK_COUNTER_PKTFILTER_RATOM = 0x8, // reduction atomic requests + NVML_NVLINK_COUNTER_PKTFILTER_NRATOM = 0x10, // non-reduction atomic requests + NVML_NVLINK_COUNTER_PKTFILTER_FLUSH = 0x20, // flush requests + NVML_NVLINK_COUNTER_PKTFILTER_RESPDATA = 0x40, // responses with data + NVML_NVLINK_COUNTER_PKTFILTER_RESPNODATA = 0x80, // responses without data + NVML_NVLINK_COUNTER_PKTFILTER_ALL = 0xFF // all packets +} nvmlNvLinkUtilizationCountPktTypes_t; + +/** + * Struct to define the NVLINK counter controls + */ +typedef struct nvmlNvLinkUtilizationControl_st +{ + nvmlNvLinkUtilizationCountUnits_t units; + nvmlNvLinkUtilizationCountPktTypes_t pktfilter; +} nvmlNvLinkUtilizationControl_t; + +/** + * Enum to represent NvLink queryable capabilities + */ +typedef enum nvmlNvLinkCapability_enum +{ + NVML_NVLINK_CAP_P2P_SUPPORTED = 0, // P2P over NVLink is supported + NVML_NVLINK_CAP_SYSMEM_ACCESS = 1, // Access to system memory is supported + NVML_NVLINK_CAP_P2P_ATOMICS = 2, // P2P atomics are supported + NVML_NVLINK_CAP_SYSMEM_ATOMICS= 3, // System memory atomics are supported + NVML_NVLINK_CAP_SLI_BRIDGE = 4, // SLI is supported over this link + NVML_NVLINK_CAP_VALID = 5, // Link is supported on this device + // should be last + NVML_NVLINK_CAP_COUNT +} nvmlNvLinkCapability_t; + +/** + * Enum to represent NvLink queryable error counters + */ +typedef enum nvmlNvLinkErrorCounter_enum +{ + NVML_NVLINK_ERROR_DL_REPLAY = 0, // Data link transmit replay error counter + NVML_NVLINK_ERROR_DL_RECOVERY = 1, // Data link transmit recovery error counter + NVML_NVLINK_ERROR_DL_CRC_FLIT = 2, // Data link receive flow control digit CRC error counter + NVML_NVLINK_ERROR_DL_CRC_DATA = 3, // Data link receive data CRC error counter + NVML_NVLINK_ERROR_DL_ECC_DATA = 4, // Data link receive data ECC error counter + + // this must be last + NVML_NVLINK_ERROR_COUNT +} nvmlNvLinkErrorCounter_t; + +/** + * Enum to represent NvLink's remote device type + */ +typedef enum nvmlIntNvLinkDeviceType_enum +{ + NVML_NVLINK_DEVICE_TYPE_GPU = 0x00, + NVML_NVLINK_DEVICE_TYPE_IBMNPU = 0x01, + NVML_NVLINK_DEVICE_TYPE_SWITCH = 0x02, + NVML_NVLINK_DEVICE_TYPE_UNKNOWN = 0xFF +} nvmlIntNvLinkDeviceType_t; + +/** + * Represents level relationships within a system between two GPUs + * The enums are spaced to allow for future relationships + */ +typedef enum nvmlGpuLevel_enum +{ + NVML_TOPOLOGY_INTERNAL = 0, // e.g. Tesla K80 + NVML_TOPOLOGY_SINGLE = 10, // all devices that only need traverse a single PCIe switch + NVML_TOPOLOGY_MULTIPLE = 20, // all devices that need not traverse a host bridge + NVML_TOPOLOGY_HOSTBRIDGE = 30, // all devices that are connected to the same host bridge + NVML_TOPOLOGY_NODE = 40, // all devices that are connected to the same NUMA node but possibly multiple host bridges + NVML_TOPOLOGY_SYSTEM = 50 // all devices in the system + + // there is purposefully no COUNT here because of the need for spacing above +} nvmlGpuTopologyLevel_t; + +/* Compatibility for CPU->NODE renaming */ +#define NVML_TOPOLOGY_CPU NVML_TOPOLOGY_NODE + +/* P2P Capability Index Status*/ +typedef enum nvmlGpuP2PStatus_enum +{ + NVML_P2P_STATUS_OK = 0, + NVML_P2P_STATUS_CHIPSET_NOT_SUPPORED, + NVML_P2P_STATUS_GPU_NOT_SUPPORTED, + NVML_P2P_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED, + NVML_P2P_STATUS_DISABLED_BY_REGKEY, + NVML_P2P_STATUS_NOT_SUPPORTED, + NVML_P2P_STATUS_UNKNOWN + +} nvmlGpuP2PStatus_t; + +/* P2P Capability Index*/ +typedef enum nvmlGpuP2PCapsIndex_enum +{ + NVML_P2P_CAPS_INDEX_READ = 0, + NVML_P2P_CAPS_INDEX_WRITE, + NVML_P2P_CAPS_INDEX_NVLINK, + NVML_P2P_CAPS_INDEX_ATOMICS, + NVML_P2P_CAPS_INDEX_PROP, + NVML_P2P_CAPS_INDEX_UNKNOWN +}nvmlGpuP2PCapsIndex_t; + +/** + * Maximum limit on Physical Bridges per Board + */ +#define NVML_MAX_PHYSICAL_BRIDGE (128) + +/** + * Information about the Bridge Chip Firmware + */ +typedef struct nvmlBridgeChipInfo_st +{ + nvmlBridgeChipType_t type; //!< Type of Bridge Chip + unsigned int fwVersion; //!< Firmware Version. 0=Version is unavailable +}nvmlBridgeChipInfo_t; + +/** + * This structure stores the complete Hierarchy of the Bridge Chip within the board. The immediate + * bridge is stored at index 0 of bridgeInfoList, parent to immediate bridge is at index 1 and so forth. + */ +typedef struct nvmlBridgeChipHierarchy_st +{ + unsigned char bridgeCount; //!< Number of Bridge Chips on the Board + nvmlBridgeChipInfo_t bridgeChipInfo[NVML_MAX_PHYSICAL_BRIDGE]; //!< Hierarchy of Bridge Chips on the board +}nvmlBridgeChipHierarchy_t; + +/** + * Represents Type of Sampling Event + */ +typedef enum nvmlSamplingType_enum +{ + NVML_TOTAL_POWER_SAMPLES = 0, //!< To represent total power drawn by GPU + NVML_GPU_UTILIZATION_SAMPLES = 1, //!< To represent percent of time during which one or more kernels was executing on the GPU + NVML_MEMORY_UTILIZATION_SAMPLES = 2, //!< To represent percent of time during which global (device) memory was being read or written + NVML_ENC_UTILIZATION_SAMPLES = 3, //!< To represent percent of time during which NVENC remains busy + NVML_DEC_UTILIZATION_SAMPLES = 4, //!< To represent percent of time during which NVDEC remains busy + NVML_PROCESSOR_CLK_SAMPLES = 5, //!< To represent processor clock samples + NVML_MEMORY_CLK_SAMPLES = 6, //!< To represent memory clock samples + + // Keep this last + NVML_SAMPLINGTYPE_COUNT +}nvmlSamplingType_t; + +/** + * Represents the queryable PCIe utilization counters + */ +typedef enum nvmlPcieUtilCounter_enum +{ + NVML_PCIE_UTIL_TX_BYTES = 0, // 1KB granularity + NVML_PCIE_UTIL_RX_BYTES = 1, // 1KB granularity + + // Keep this last + NVML_PCIE_UTIL_COUNT +} nvmlPcieUtilCounter_t; + +/** + * Represents the type for sample value returned + */ +typedef enum nvmlValueType_enum +{ + NVML_VALUE_TYPE_DOUBLE = 0, + NVML_VALUE_TYPE_UNSIGNED_INT = 1, + NVML_VALUE_TYPE_UNSIGNED_LONG = 2, + NVML_VALUE_TYPE_UNSIGNED_LONG_LONG = 3, + NVML_VALUE_TYPE_SIGNED_LONG_LONG = 4, + + // Keep this last + NVML_VALUE_TYPE_COUNT +}nvmlValueType_t; + + +/** + * Union to represent different types of Value + */ +typedef union nvmlValue_st +{ + double dVal; //!< If the value is double + unsigned int uiVal; //!< If the value is unsigned int + unsigned long ulVal; //!< If the value is unsigned long + unsigned long long ullVal; //!< If the value is unsigned long long + signed long long sllVal; //!< If the value is signed long long +}nvmlValue_t; + +/** + * Information for Sample + */ +typedef struct nvmlSample_st +{ + unsigned long long timeStamp; //!< CPU Timestamp in microseconds + nvmlValue_t sampleValue; //!< Sample Value +}nvmlSample_t; + +/** + * Represents type of perf policy for which violation times can be queried + */ +typedef enum nvmlPerfPolicyType_enum +{ + NVML_PERF_POLICY_POWER = 0, //!< How long did power violations cause the GPU to be below application clocks + NVML_PERF_POLICY_THERMAL = 1, //!< How long did thermal violations cause the GPU to be below application clocks + NVML_PERF_POLICY_SYNC_BOOST = 2, //!< How long did sync boost cause the GPU to be below application clocks + NVML_PERF_POLICY_BOARD_LIMIT = 3, //!< How long did the board limit cause the GPU to be below application clocks + NVML_PERF_POLICY_LOW_UTILIZATION = 4, //!< How long did low utilization cause the GPU to be below application clocks + NVML_PERF_POLICY_RELIABILITY = 5, //!< How long did the board reliability limit cause the GPU to be below application clocks + + NVML_PERF_POLICY_TOTAL_APP_CLOCKS = 10, //!< Total time the GPU was held below application clocks by any limiter (0 - 5 above) + NVML_PERF_POLICY_TOTAL_BASE_CLOCKS = 11, //!< Total time the GPU was held below base clocks + + // Keep this last + NVML_PERF_POLICY_COUNT +}nvmlPerfPolicyType_t; + +/** + * Struct to hold perf policy violation status data + */ +typedef struct nvmlViolationTime_st +{ + unsigned long long referenceTime; //!< referenceTime represents CPU timestamp in microseconds + unsigned long long violationTime; //!< violationTime in Nanoseconds +}nvmlViolationTime_t; + +#define NVML_MAX_THERMAL_SENSORS_PER_GPU 3 + +typedef enum +{ + NVML_THERMAL_TARGET_NONE = 0, + NVML_THERMAL_TARGET_GPU = 1, //!< GPU core temperature requires NvPhysicalGpuHandle + NVML_THERMAL_TARGET_MEMORY = 2, //!< GPU memory temperature requires NvPhysicalGpuHandle + NVML_THERMAL_TARGET_POWER_SUPPLY = 4, //!< GPU power supply temperature requires NvPhysicalGpuHandle + NVML_THERMAL_TARGET_BOARD = 8, //!< GPU board ambient temperature requires NvPhysicalGpuHandle + NVML_THERMAL_TARGET_VCD_BOARD = 9, //!< Visual Computing Device Board temperature requires NvVisualComputingDeviceHandle + NVML_THERMAL_TARGET_VCD_INLET = 10, //!< Visual Computing Device Inlet temperature requires NvVisualComputingDeviceHandle + NVML_THERMAL_TARGET_VCD_OUTLET = 11, //!< Visual Computing Device Outlet temperature requires NvVisualComputingDeviceHandle + + NVML_THERMAL_TARGET_ALL = 15, + NVML_THERMAL_TARGET_UNKNOWN = -1, +} nvmlThermalTarget_t; + +typedef enum +{ + NVML_THERMAL_CONTROLLER_NONE = 0, + NVML_THERMAL_CONTROLLER_GPU_INTERNAL, + NVML_THERMAL_CONTROLLER_ADM1032, + NVML_THERMAL_CONTROLLER_ADT7461, + NVML_THERMAL_CONTROLLER_MAX6649, + NVML_THERMAL_CONTROLLER_MAX1617, + NVML_THERMAL_CONTROLLER_LM99, + NVML_THERMAL_CONTROLLER_LM89, + NVML_THERMAL_CONTROLLER_LM64, + NVML_THERMAL_CONTROLLER_G781, + NVML_THERMAL_CONTROLLER_ADT7473, + NVML_THERMAL_CONTROLLER_SBMAX6649, + NVML_THERMAL_CONTROLLER_VBIOSEVT, + NVML_THERMAL_CONTROLLER_OS, + NVML_THERMAL_CONTROLLER_NVSYSCON_CANOAS, + NVML_THERMAL_CONTROLLER_NVSYSCON_E551, + NVML_THERMAL_CONTROLLER_MAX6649R, + NVML_THERMAL_CONTROLLER_ADT7473S, + NVML_THERMAL_CONTROLLER_UNKNOWN = -1, +} nvmlThermalController_t; + +typedef struct +{ + unsigned int count; + struct + { + nvmlThermalController_t controller; + int defaultMinTemp; + int defaultMaxTemp; + int currentTemp; + nvmlThermalTarget_t target; + } sensor[NVML_MAX_THERMAL_SENSORS_PER_GPU]; + +} nvmlGpuThermalSettings_t; + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlDeviceEnumvs Device Enums + * @{ + */ +/***************************************************************************************************/ + +/** + * Generic enable/disable enum. + */ +typedef enum nvmlEnableState_enum +{ + NVML_FEATURE_DISABLED = 0, //!< Feature disabled + NVML_FEATURE_ENABLED = 1 //!< Feature enabled +} nvmlEnableState_t; + +//! Generic flag used to specify the default behavior of some functions. See description of particular functions for details. +#define nvmlFlagDefault 0x00 +//! Generic flag used to force some behavior. See description of particular functions for details. +#define nvmlFlagForce 0x01 + +/** + * * The Brand of the GPU + * */ +typedef enum nvmlBrandType_enum +{ + NVML_BRAND_UNKNOWN = 0, + NVML_BRAND_QUADRO = 1, + NVML_BRAND_TESLA = 2, + NVML_BRAND_NVS = 3, + NVML_BRAND_GRID = 4, // Deprecated from API reporting. Keeping definition for backward compatibility. + NVML_BRAND_GEFORCE = 5, + NVML_BRAND_TITAN = 6, + NVML_BRAND_NVIDIA_VAPPS = 7, // NVIDIA Virtual Applications + NVML_BRAND_NVIDIA_VPC = 8, // NVIDIA Virtual PC + NVML_BRAND_NVIDIA_VCS = 9, // NVIDIA Virtual Compute Server + NVML_BRAND_NVIDIA_VWS = 10, // NVIDIA RTX Virtual Workstation + NVML_BRAND_NVIDIA_CLOUD_GAMING = 11, // NVIDIA Cloud Gaming + NVML_BRAND_NVIDIA_VGAMING = NVML_BRAND_NVIDIA_CLOUD_GAMING, // Deprecated from API reporting. Keeping definition for backward compatibility. + NVML_BRAND_QUADRO_RTX = 12, + NVML_BRAND_NVIDIA_RTX = 13, + NVML_BRAND_NVIDIA = 14, + NVML_BRAND_GEFORCE_RTX = 15, // Unused + NVML_BRAND_TITAN_RTX = 16, // Unused + + // Keep this last + NVML_BRAND_COUNT +} nvmlBrandType_t; + +/** + * Temperature thresholds. + */ +typedef enum nvmlTemperatureThresholds_enum +{ + NVML_TEMPERATURE_THRESHOLD_SHUTDOWN = 0, // Temperature at which the GPU will + // shut down for HW protection + NVML_TEMPERATURE_THRESHOLD_SLOWDOWN = 1, // Temperature at which the GPU will + // begin HW slowdown + NVML_TEMPERATURE_THRESHOLD_MEM_MAX = 2, // Memory Temperature at which the GPU will + // begin SW slowdown + NVML_TEMPERATURE_THRESHOLD_GPU_MAX = 3, // GPU Temperature at which the GPU + // can be throttled below base clock + NVML_TEMPERATURE_THRESHOLD_ACOUSTIC_MIN = 4, // Minimum GPU Temperature that can be + // set as acoustic threshold + NVML_TEMPERATURE_THRESHOLD_ACOUSTIC_CURR = 5, // Current temperature that is set as + // acoustic threshold. + NVML_TEMPERATURE_THRESHOLD_ACOUSTIC_MAX = 6, // Maximum GPU temperature that can be + // set as acoustic threshold. + // Keep this last + NVML_TEMPERATURE_THRESHOLD_COUNT +} nvmlTemperatureThresholds_t; + +/** + * Temperature sensors. + */ +typedef enum nvmlTemperatureSensors_enum +{ + NVML_TEMPERATURE_GPU = 0, //!< Temperature sensor for the GPU die + + // Keep this last + NVML_TEMPERATURE_COUNT +} nvmlTemperatureSensors_t; + +/** + * Compute mode. + * + * NVML_COMPUTEMODE_EXCLUSIVE_PROCESS was added in CUDA 4.0. + * Earlier CUDA versions supported a single exclusive mode, + * which is equivalent to NVML_COMPUTEMODE_EXCLUSIVE_THREAD in CUDA 4.0 and beyond. + */ +typedef enum nvmlComputeMode_enum +{ + NVML_COMPUTEMODE_DEFAULT = 0, //!< Default compute mode -- multiple contexts per device + NVML_COMPUTEMODE_EXCLUSIVE_THREAD = 1, //!< Support Removed + NVML_COMPUTEMODE_PROHIBITED = 2, //!< Compute-prohibited mode -- no contexts per device + NVML_COMPUTEMODE_EXCLUSIVE_PROCESS = 3, //!< Compute-exclusive-process mode -- only one context per device, usable from multiple threads at a time + + // Keep this last + NVML_COMPUTEMODE_COUNT +} nvmlComputeMode_t; + +/** + * Max Clock Monitors available + */ +#define MAX_CLK_DOMAINS 32 + +/** + * Clock Monitor error types + */ +typedef struct nvmlClkMonFaultInfo_struct { + /** + * The Domain which faulted + */ + unsigned int clkApiDomain; + + /** + * Faults Information + */ + unsigned int clkDomainFaultMask; +} nvmlClkMonFaultInfo_t; + +/** + * Clock Monitor Status + */ +typedef struct nvmlClkMonStatus_status { + /** + * Fault status Indicator + */ + unsigned int bGlobalStatus; + + /** + * Total faulted domain numbers + */ + unsigned int clkMonListSize; + + /** + * The fault Information structure + */ + nvmlClkMonFaultInfo_t clkMonList[MAX_CLK_DOMAINS]; +} nvmlClkMonStatus_t; + +/** + * ECC bit types. + * + * @deprecated See \ref nvmlMemoryErrorType_t for a more flexible type + */ +#define nvmlEccBitType_t nvmlMemoryErrorType_t + +/** + * Single bit ECC errors + * + * @deprecated Mapped to \ref NVML_MEMORY_ERROR_TYPE_CORRECTED + */ +#define NVML_SINGLE_BIT_ECC NVML_MEMORY_ERROR_TYPE_CORRECTED + +/** + * Double bit ECC errors + * + * @deprecated Mapped to \ref NVML_MEMORY_ERROR_TYPE_UNCORRECTED + */ +#define NVML_DOUBLE_BIT_ECC NVML_MEMORY_ERROR_TYPE_UNCORRECTED + +/** + * Memory error types + */ +typedef enum nvmlMemoryErrorType_enum +{ + /** + * A memory error that was corrected + * + * For ECC errors, these are single bit errors + * For Texture memory, these are errors fixed by resend + */ + NVML_MEMORY_ERROR_TYPE_CORRECTED = 0, + /** + * A memory error that was not corrected + * + * For ECC errors, these are double bit errors + * For Texture memory, these are errors where the resend fails + */ + NVML_MEMORY_ERROR_TYPE_UNCORRECTED = 1, + + + // Keep this last + NVML_MEMORY_ERROR_TYPE_COUNT //!< Count of memory error types + +} nvmlMemoryErrorType_t; + +/** + * ECC counter types. + * + * Note: Volatile counts are reset each time the driver loads. On Windows this is once per boot. On Linux this can be more frequent. + * On Linux the driver unloads when no active clients exist. If persistence mode is enabled or there is always a driver + * client active (e.g. X11), then Linux also sees per-boot behavior. If not, volatile counts are reset each time a compute app + * is run. + */ +typedef enum nvmlEccCounterType_enum +{ + NVML_VOLATILE_ECC = 0, //!< Volatile counts are reset each time the driver loads. + NVML_AGGREGATE_ECC = 1, //!< Aggregate counts persist across reboots (i.e. for the lifetime of the device) + + // Keep this last + NVML_ECC_COUNTER_TYPE_COUNT //!< Count of memory counter types +} nvmlEccCounterType_t; + +/** + * Clock types. + * + * All speeds are in Mhz. + */ +typedef enum nvmlClockType_enum +{ + NVML_CLOCK_GRAPHICS = 0, //!< Graphics clock domain + NVML_CLOCK_SM = 1, //!< SM clock domain + NVML_CLOCK_MEM = 2, //!< Memory clock domain + NVML_CLOCK_VIDEO = 3, //!< Video encoder/decoder clock domain + + // Keep this last + NVML_CLOCK_COUNT //!< Count of clock types +} nvmlClockType_t; + +/** + * Clock Ids. These are used in combination with nvmlClockType_t + * to specify a single clock value. + */ +typedef enum nvmlClockId_enum +{ + NVML_CLOCK_ID_CURRENT = 0, //!< Current actual clock value + NVML_CLOCK_ID_APP_CLOCK_TARGET = 1, //!< Target application clock + NVML_CLOCK_ID_APP_CLOCK_DEFAULT = 2, //!< Default application clock target + NVML_CLOCK_ID_CUSTOMER_BOOST_MAX = 3, //!< OEM-defined maximum clock rate + + //Keep this last + NVML_CLOCK_ID_COUNT //!< Count of Clock Ids. +} nvmlClockId_t; + +/** + * Driver models. + * + * Windows only. + */ + +typedef enum nvmlDriverModel_enum +{ + NVML_DRIVER_WDDM = 0, //!< WDDM driver model -- GPU treated as a display device + NVML_DRIVER_WDM = 1 //!< WDM (TCC) model (recommended) -- GPU treated as a generic device +} nvmlDriverModel_t; + +#define NVML_MAX_GPU_PERF_PSTATES 16 + +/** + * Allowed PStates. + */ +typedef enum nvmlPStates_enum +{ + NVML_PSTATE_0 = 0, //!< Performance state 0 -- Maximum Performance + NVML_PSTATE_1 = 1, //!< Performance state 1 + NVML_PSTATE_2 = 2, //!< Performance state 2 + NVML_PSTATE_3 = 3, //!< Performance state 3 + NVML_PSTATE_4 = 4, //!< Performance state 4 + NVML_PSTATE_5 = 5, //!< Performance state 5 + NVML_PSTATE_6 = 6, //!< Performance state 6 + NVML_PSTATE_7 = 7, //!< Performance state 7 + NVML_PSTATE_8 = 8, //!< Performance state 8 + NVML_PSTATE_9 = 9, //!< Performance state 9 + NVML_PSTATE_10 = 10, //!< Performance state 10 + NVML_PSTATE_11 = 11, //!< Performance state 11 + NVML_PSTATE_12 = 12, //!< Performance state 12 + NVML_PSTATE_13 = 13, //!< Performance state 13 + NVML_PSTATE_14 = 14, //!< Performance state 14 + NVML_PSTATE_15 = 15, //!< Performance state 15 -- Minimum Performance + NVML_PSTATE_UNKNOWN = 32 //!< Unknown performance state +} nvmlPstates_t; + +/** + * GPU Operation Mode + * + * GOM allows to reduce power usage and optimize GPU throughput by disabling GPU features. + * + * Each GOM is designed to meet specific user needs. + */ +typedef enum nvmlGom_enum +{ + NVML_GOM_ALL_ON = 0, //!< Everything is enabled and running at full speed + + NVML_GOM_COMPUTE = 1, //!< Designed for running only compute tasks. Graphics operations + //!< are not allowed + + NVML_GOM_LOW_DP = 2 //!< Designed for running graphics applications that don't require + //!< high bandwidth double precision +} nvmlGpuOperationMode_t; + +/** + * Available infoROM objects. + */ +typedef enum nvmlInforomObject_enum +{ + NVML_INFOROM_OEM = 0, //!< An object defined by OEM + NVML_INFOROM_ECC = 1, //!< The ECC object determining the level of ECC support + NVML_INFOROM_POWER = 2, //!< The power management object + + // Keep this last + NVML_INFOROM_COUNT //!< This counts the number of infoROM objects the driver knows about +} nvmlInforomObject_t; + +/** + * Return values for NVML API calls. + */ +typedef enum nvmlReturn_enum +{ + // cppcheck-suppress * + NVML_SUCCESS = 0, //!< The operation was successful + NVML_ERROR_UNINITIALIZED = 1, //!< NVML was not first initialized with nvmlInit() + NVML_ERROR_INVALID_ARGUMENT = 2, //!< A supplied argument is invalid + NVML_ERROR_NOT_SUPPORTED = 3, //!< The requested operation is not available on target device + NVML_ERROR_NO_PERMISSION = 4, //!< The current user does not have permission for operation + NVML_ERROR_ALREADY_INITIALIZED = 5, //!< Deprecated: Multiple initializations are now allowed through ref counting + NVML_ERROR_NOT_FOUND = 6, //!< A query to find an object was unsuccessful + NVML_ERROR_INSUFFICIENT_SIZE = 7, //!< An input argument is not large enough + NVML_ERROR_INSUFFICIENT_POWER = 8, //!< A device's external power cables are not properly attached + NVML_ERROR_DRIVER_NOT_LOADED = 9, //!< NVIDIA driver is not loaded + NVML_ERROR_TIMEOUT = 10, //!< User provided timeout passed + NVML_ERROR_IRQ_ISSUE = 11, //!< NVIDIA Kernel detected an interrupt issue with a GPU + NVML_ERROR_LIBRARY_NOT_FOUND = 12, //!< NVML Shared Library couldn't be found or loaded + NVML_ERROR_FUNCTION_NOT_FOUND = 13, //!< Local version of NVML doesn't implement this function + NVML_ERROR_CORRUPTED_INFOROM = 14, //!< infoROM is corrupted + NVML_ERROR_GPU_IS_LOST = 15, //!< The GPU has fallen off the bus or has otherwise become inaccessible + NVML_ERROR_RESET_REQUIRED = 16, //!< The GPU requires a reset before it can be used again + NVML_ERROR_OPERATING_SYSTEM = 17, //!< The GPU control device has been blocked by the operating system/cgroups + NVML_ERROR_LIB_RM_VERSION_MISMATCH = 18, //!< RM detects a driver/library version mismatch + NVML_ERROR_IN_USE = 19, //!< An operation cannot be performed because the GPU is currently in use + NVML_ERROR_MEMORY = 20, //!< Insufficient memory + NVML_ERROR_NO_DATA = 21, //!< No data + NVML_ERROR_VGPU_ECC_NOT_SUPPORTED = 22, //!< The requested vgpu operation is not available on target device, becasue ECC is enabled + NVML_ERROR_INSUFFICIENT_RESOURCES = 23, //!< Ran out of critical resources, other than memory + NVML_ERROR_FREQ_NOT_SUPPORTED = 24, //!< Ran out of critical resources, other than memory + NVML_ERROR_ARGUMENT_VERSION_MISMATCH = 25, //!< The provided version is invalid/unsupported + NVML_ERROR_DEPRECATED = 26, //!< The requested functionality has been deprecated + NVML_ERROR_UNKNOWN = 999 //!< An internal driver error occurred +} nvmlReturn_t; + +/** + * See \ref nvmlDeviceGetMemoryErrorCounter + */ +typedef enum nvmlMemoryLocation_enum +{ + NVML_MEMORY_LOCATION_L1_CACHE = 0, //!< GPU L1 Cache + NVML_MEMORY_LOCATION_L2_CACHE = 1, //!< GPU L2 Cache + NVML_MEMORY_LOCATION_DRAM = 2, //!< Turing+ DRAM + NVML_MEMORY_LOCATION_DEVICE_MEMORY = 2, //!< GPU Device Memory + NVML_MEMORY_LOCATION_REGISTER_FILE = 3, //!< GPU Register File + NVML_MEMORY_LOCATION_TEXTURE_MEMORY = 4, //!< GPU Texture Memory + NVML_MEMORY_LOCATION_TEXTURE_SHM = 5, //!< Shared memory + NVML_MEMORY_LOCATION_CBU = 6, //!< CBU + NVML_MEMORY_LOCATION_SRAM = 7, //!< Turing+ SRAM + // Keep this last + NVML_MEMORY_LOCATION_COUNT //!< This counts the number of memory locations the driver knows about +} nvmlMemoryLocation_t; + +/** + * Causes for page retirement + */ +typedef enum nvmlPageRetirementCause_enum +{ + NVML_PAGE_RETIREMENT_CAUSE_MULTIPLE_SINGLE_BIT_ECC_ERRORS = 0, //!< Page was retired due to multiple single bit ECC error + NVML_PAGE_RETIREMENT_CAUSE_DOUBLE_BIT_ECC_ERROR = 1, //!< Page was retired due to double bit ECC error + + // Keep this last + NVML_PAGE_RETIREMENT_CAUSE_COUNT +} nvmlPageRetirementCause_t; + +/** + * API types that allow changes to default permission restrictions + */ +typedef enum nvmlRestrictedAPI_enum +{ + NVML_RESTRICTED_API_SET_APPLICATION_CLOCKS = 0, //!< APIs that change application clocks, see nvmlDeviceSetApplicationsClocks + //!< and see nvmlDeviceResetApplicationsClocks + NVML_RESTRICTED_API_SET_AUTO_BOOSTED_CLOCKS = 1, //!< APIs that enable/disable Auto Boosted clocks + //!< see nvmlDeviceSetAutoBoostedClocksEnabled + // Keep this last + NVML_RESTRICTED_API_COUNT +} nvmlRestrictedAPI_t; + +/** @} */ + +/***************************************************************************************************/ +/** @addtogroup virtualGPU + * @{ + */ +/***************************************************************************************************/ +/** @defgroup nvmlVirtualGpuEnums vGPU Enums + * @{ + */ +/***************************************************************************************************/ + +/*! + * GPU virtualization mode types. + */ +typedef enum nvmlGpuVirtualizationMode { + NVML_GPU_VIRTUALIZATION_MODE_NONE = 0, //!< Represents Bare Metal GPU + NVML_GPU_VIRTUALIZATION_MODE_PASSTHROUGH = 1, //!< Device is associated with GPU-Passthorugh + NVML_GPU_VIRTUALIZATION_MODE_VGPU = 2, //!< Device is associated with vGPU inside virtual machine. + NVML_GPU_VIRTUALIZATION_MODE_HOST_VGPU = 3, //!< Device is associated with VGX hypervisor in vGPU mode + NVML_GPU_VIRTUALIZATION_MODE_HOST_VSGA = 4 //!< Device is associated with VGX hypervisor in vSGA mode +} nvmlGpuVirtualizationMode_t; + +/** + * Host vGPU modes + */ +typedef enum nvmlHostVgpuMode_enum +{ + NVML_HOST_VGPU_MODE_NON_SRIOV = 0, //!< Non SR-IOV mode + NVML_HOST_VGPU_MODE_SRIOV = 1 //!< SR-IOV mode +} nvmlHostVgpuMode_t; + +/*! + * Types of VM identifiers + */ +typedef enum nvmlVgpuVmIdType { + NVML_VGPU_VM_ID_DOMAIN_ID = 0, //!< VM ID represents DOMAIN ID + NVML_VGPU_VM_ID_UUID = 1 //!< VM ID represents UUID +} nvmlVgpuVmIdType_t; + +/** + * vGPU GUEST info state + */ +typedef enum nvmlVgpuGuestInfoState_enum +{ + NVML_VGPU_INSTANCE_GUEST_INFO_STATE_UNINITIALIZED = 0, //!< Guest-dependent fields uninitialized + NVML_VGPU_INSTANCE_GUEST_INFO_STATE_INITIALIZED = 1 //!< Guest-dependent fields initialized +} nvmlVgpuGuestInfoState_t; + +/** + * vGPU software licensable features + */ +typedef enum { + NVML_GRID_LICENSE_FEATURE_CODE_UNKNOWN = 0, //!< Unknown + NVML_GRID_LICENSE_FEATURE_CODE_VGPU = 1, //!< Virtual GPU + NVML_GRID_LICENSE_FEATURE_CODE_NVIDIA_RTX = 2, //!< Nvidia RTX + NVML_GRID_LICENSE_FEATURE_CODE_VWORKSTATION = NVML_GRID_LICENSE_FEATURE_CODE_NVIDIA_RTX, //!< Deprecated, do not use. + NVML_GRID_LICENSE_FEATURE_CODE_GAMING = 3, //!< Gaming + NVML_GRID_LICENSE_FEATURE_CODE_COMPUTE = 4 //!< Compute +} nvmlGridLicenseFeatureCode_t; + +/** + * Status codes for license expiry + */ +#define NVML_GRID_LICENSE_EXPIRY_NOT_AVAILABLE 0 //!< Expiry information not available +#define NVML_GRID_LICENSE_EXPIRY_INVALID 1 //!< Invalid expiry or error fetching expiry +#define NVML_GRID_LICENSE_EXPIRY_VALID 2 //!< Valid expiry +#define NVML_GRID_LICENSE_EXPIRY_NOT_APPLICABLE 3 //!< Expiry not applicable +#define NVML_GRID_LICENSE_EXPIRY_PERMANENT 4 //!< Permanent expiry + +/** + * vGPU queryable capabilities + */ +typedef enum nvmlVgpuCapability_enum +{ + NVML_VGPU_CAP_NVLINK_P2P = 0, //!< P2P over NVLink is supported + NVML_VGPU_CAP_GPUDIRECT = 1, //!< GPUDirect capability is supported + NVML_VGPU_CAP_MULTI_VGPU_EXCLUSIVE = 2, //!< vGPU profile cannot be mixed with other vGPU profiles in same VM + NVML_VGPU_CAP_EXCLUSIVE_TYPE = 3, //!< vGPU profile cannot run on a GPU alongside other profiles of different type + NVML_VGPU_CAP_EXCLUSIVE_SIZE = 4, //!< vGPU profile cannot run on a GPU alongside other profiles of different size + // Keep this last + NVML_VGPU_CAP_COUNT +} nvmlVgpuCapability_t; + + +/** +* vGPU driver queryable capabilities +*/ +typedef enum nvmlVgpuDriverCapability_enum +{ + NVML_VGPU_DRIVER_CAP_HETEROGENEOUS_MULTI_VGPU = 0, //!< Supports mixing of different vGPU profiles within one guest VM + // Keep this last + NVML_VGPU_DRIVER_CAP_COUNT +} nvmlVgpuDriverCapability_t; + + +/** +* Device vGPU queryable capabilities +*/ +typedef enum nvmlDeviceVgpuCapability_enum +{ + NVML_DEVICE_VGPU_CAP_FRACTIONAL_MULTI_VGPU = 0, //!< Fractional vGPU profiles on this GPU can be used in multi-vGPU configurations + NVML_DEVICE_VGPU_CAP_HETEROGENEOUS_TIMESLICE_PROFILES = 1, //!< Supports concurrent execution of timesliced vGPU profiles of differing types + NVML_DEVICE_VGPU_CAP_HETEROGENEOUS_TIMESLICE_SIZES = 2, //!< Supports concurrent execution of timesliced vGPU profiles of differing framebuffer sizes + // Keep this last + NVML_DEVICE_VGPU_CAP_COUNT +} nvmlDeviceVgpuCapability_t; + +/** @} */ + +/***************************************************************************************************/ + +/** @defgroup nvmlVgpuConstants vGPU Constants + * @{ + */ +/***************************************************************************************************/ + +/** + * Buffer size guaranteed to be large enough for \ref nvmlVgpuTypeGetLicense + */ +#define NVML_GRID_LICENSE_BUFFER_SIZE 128 + +#define NVML_VGPU_NAME_BUFFER_SIZE 64 + +#define NVML_GRID_LICENSE_FEATURE_MAX_COUNT 3 + +#define INVALID_GPU_INSTANCE_PROFILE_ID 0xFFFFFFFF + +#define INVALID_GPU_INSTANCE_ID 0xFFFFFFFF + +/*! + * Macros for vGPU instance's virtualization capabilities bitfield. + */ +#define NVML_VGPU_VIRTUALIZATION_CAP_MIGRATION 0:0 +#define NVML_VGPU_VIRTUALIZATION_CAP_MIGRATION_NO 0x0 +#define NVML_VGPU_VIRTUALIZATION_CAP_MIGRATION_YES 0x1 + +/*! + * Macros for pGPU's virtualization capabilities bitfield. + */ +#define NVML_VGPU_PGPU_VIRTUALIZATION_CAP_MIGRATION 0:0 +#define NVML_VGPU_PGPU_VIRTUALIZATION_CAP_MIGRATION_NO 0x0 +#define NVML_VGPU_PGPU_VIRTUALIZATION_CAP_MIGRATION_YES 0x1 + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlVgpuStructs vGPU Structs + * @{ + */ +/***************************************************************************************************/ + +typedef unsigned int nvmlVgpuTypeId_t; + +typedef unsigned int nvmlVgpuInstance_t; + +/** + * Structure to store Utilization Value and vgpuInstance + */ +typedef struct nvmlVgpuInstanceUtilizationSample_st +{ + nvmlVgpuInstance_t vgpuInstance; //!< vGPU Instance + unsigned long long timeStamp; //!< CPU Timestamp in microseconds + nvmlValue_t smUtil; //!< SM (3D/Compute) Util Value + nvmlValue_t memUtil; //!< Frame Buffer Memory Util Value + nvmlValue_t encUtil; //!< Encoder Util Value + nvmlValue_t decUtil; //!< Decoder Util Value +} nvmlVgpuInstanceUtilizationSample_t; + +/** + * Structure to store Utilization Value, vgpuInstance and subprocess information + */ +typedef struct nvmlVgpuProcessUtilizationSample_st +{ + nvmlVgpuInstance_t vgpuInstance; //!< vGPU Instance + unsigned int pid; //!< PID of process running within the vGPU VM + char processName[NVML_VGPU_NAME_BUFFER_SIZE]; //!< Name of process running within the vGPU VM + unsigned long long timeStamp; //!< CPU Timestamp in microseconds + unsigned int smUtil; //!< SM (3D/Compute) Util Value + unsigned int memUtil; //!< Frame Buffer Memory Util Value + unsigned int encUtil; //!< Encoder Util Value + unsigned int decUtil; //!< Decoder Util Value +} nvmlVgpuProcessUtilizationSample_t; + +/** + * vGPU scheduler policies + */ +#define NVML_VGPU_SCHEDULER_POLICY_UNKNOWN 0 +#define NVML_VGPU_SCHEDULER_POLICY_BEST_EFFORT 1 +#define NVML_VGPU_SCHEDULER_POLICY_EQUAL_SHARE 2 +#define NVML_VGPU_SCHEDULER_POLICY_FIXED_SHARE 3 + +#define NVML_SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT 3 + +#define NVML_SCHEDULER_SW_MAX_LOG_ENTRIES 200 + +/** + * Union to represent the vGPU Scheduler Parameters + */ +typedef union +{ + struct + { + unsigned int avgFactor; //!< Average factor in compensating the timeslice for Adaptive Round Robin mode + unsigned int timeslice; //!< The timeslice in ns for each software run list as configured, or the default value otherwise + } vgpuSchedDataWithARR; + + struct + { + unsigned int timeslice; //!< The timeslice in ns for each software run list as configured, or the default value otherwise + } vgpuSchedData; + +} nvmlVgpuSchedulerParams_t; + +/** + * Structure to store the state and logs of a software runlist + */ +typedef struct nvmlVgpuSchedulerLogEntries_st +{ + unsigned long long timestamp; //!< Timestamp in ns when this software runlist was preeempted + unsigned long long timeRunTotal; //!< Total time in ns this software runlist has run + unsigned long long timeRun; //!< Time in ns this software runlist ran before preemption + unsigned int swRunlistId; //!< Software runlist Id + unsigned long long targetTimeSlice; //!< The actual timeslice after deduction + unsigned long long cumulativePreemptionTime; //!< Preemption time in ns for this SW runlist +} nvmlVgpuSchedulerLogEntry_t; + +/** + * Structure to store a vGPU software scheduler log + */ +typedef struct nvmlVgpuSchedulerLog_st +{ + unsigned int engineId; //!< Engine whose software runlist log entries are fetched + unsigned int schedulerPolicy; //!< Scheduler policy + unsigned int isEnabledARR; //!< Flag to check Adaptive Round Robin scheduler mode + nvmlVgpuSchedulerParams_t schedulerParams; + unsigned int entriesCount; //!< Count of log entries fetched + nvmlVgpuSchedulerLogEntry_t logEntries[NVML_SCHEDULER_SW_MAX_LOG_ENTRIES]; +} nvmlVgpuSchedulerLog_t; + +/** + * Structure to store the vGPU scheduler state + */ +typedef struct nvmlVgpuSchedulerGetState_st +{ + unsigned int schedulerPolicy; //!< Scheduler policy + unsigned int isEnabledARR; //!< Flag to check Adaptive Round Robin scheduler mode + nvmlVgpuSchedulerParams_t schedulerParams; +} nvmlVgpuSchedulerGetState_t; + +/** + * Union to represent the vGPU Scheduler set Parameters + */ +typedef union +{ + struct + { + unsigned int avgFactor; //!< Average factor in compensating the timeslice for Adaptive Round Robin mode + unsigned int frequency; //!< Frequency for Adaptive Round Robin mode + } vgpuSchedDataWithARR; + + struct + { + unsigned int timeslice; //!< The timeslice in ms(milliseconds) for each software run list as configured, or the default value otherwise + } vgpuSchedData; + +} nvmlVgpuSchedulerSetParams_t; + +/** + * Structure to set the vGPU scheduler state + */ +typedef struct nvmlVgpuSchedulerSetState_st +{ + unsigned int schedulerPolicy; //!< Scheduler policy + unsigned int enableARRMode; //!< Flag to enable/disable Adaptive Round Robin scheduler + nvmlVgpuSchedulerSetParams_t schedulerParams; +} nvmlVgpuSchedulerSetState_t; + +/** + * Structure to store the vGPU scheduler capabilities + */ +typedef struct nvmlVgpuSchedulerCapabilities_st +{ + unsigned int supportedSchedulers[NVML_SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT]; //!< List the supported vGPU schedulers on the device + unsigned int maxTimeslice; //!< Maximum timeslice value in ns + unsigned int minTimeslice; //!< Minimum timeslice value in ns + unsigned int isArrModeSupported; //!< Flag to check Adaptive Round Robin mode enabled/disabled. + unsigned int maxFrequencyForARR; //!< Maximum frequency for Adaptive Round Robin mode + unsigned int minFrequencyForARR; //!< Minimum frequency for Adaptive Round Robin mode + unsigned int maxAvgFactorForARR; //!< Maximum averaging factor for Adaptive Round Robin mode + unsigned int minAvgFactorForARR; //!< Minimum averaging factor for Adaptive Round Robin mode +} nvmlVgpuSchedulerCapabilities_t; + +/** + * Structure to store the vGPU license expiry details + */ +typedef struct nvmlVgpuLicenseExpiry_st +{ + unsigned int year; //!< Year of license expiry + unsigned short month; //!< Month of license expiry + unsigned short day; //!< Day of license expiry + unsigned short hour; //!< Hour of license expiry + unsigned short min; //!< Minutes of license expiry + unsigned short sec; //!< Seconds of license expiry + unsigned char status; //!< License expiry status +} nvmlVgpuLicenseExpiry_t; + +/** + * vGPU license state + */ +#define NVML_GRID_LICENSE_STATE_UNKNOWN 0 //!< Unknown state +#define NVML_GRID_LICENSE_STATE_UNINITIALIZED 1 //!< Uninitialized state +#define NVML_GRID_LICENSE_STATE_UNLICENSED_UNRESTRICTED 2 //!< Unlicensed unrestricted state +#define NVML_GRID_LICENSE_STATE_UNLICENSED_RESTRICTED 3 //!< Unlicensed restricted state +#define NVML_GRID_LICENSE_STATE_UNLICENSED 4 //!< Unlicensed state +#define NVML_GRID_LICENSE_STATE_LICENSED 5 //!< Licensed state + +typedef struct nvmlVgpuLicenseInfo_st +{ + unsigned char isLicensed; //!< License status + nvmlVgpuLicenseExpiry_t licenseExpiry; //!< License expiry information + unsigned int currentState; //!< Current license state +} nvmlVgpuLicenseInfo_t; + +/** + * Structure to store utilization value and process Id + */ +typedef struct nvmlProcessUtilizationSample_st +{ + unsigned int pid; //!< PID of process + unsigned long long timeStamp; //!< CPU Timestamp in microseconds + unsigned int smUtil; //!< SM (3D/Compute) Util Value + unsigned int memUtil; //!< Frame Buffer Memory Util Value + unsigned int encUtil; //!< Encoder Util Value + unsigned int decUtil; //!< Decoder Util Value +} nvmlProcessUtilizationSample_t; + +/** + * Structure to store license expiry date and time values + */ +typedef struct nvmlGridLicenseExpiry_st +{ + unsigned int year; //!< Year value of license expiry + unsigned short month; //!< Month value of license expiry + unsigned short day; //!< Day value of license expiry + unsigned short hour; //!< Hour value of license expiry + unsigned short min; //!< Minutes value of license expiry + unsigned short sec; //!< Seconds value of license expiry + unsigned char status; //!< License expiry status +} nvmlGridLicenseExpiry_t; + +/** + * Structure containing vGPU software licensable feature information + */ +typedef struct nvmlGridLicensableFeature_st +{ + nvmlGridLicenseFeatureCode_t featureCode; //!< Licensed feature code + unsigned int featureState; //!< Non-zero if feature is currently licensed, otherwise zero + char licenseInfo[NVML_GRID_LICENSE_BUFFER_SIZE]; //!< Deprecated. + char productName[NVML_GRID_LICENSE_BUFFER_SIZE]; //!< Product name of feature + unsigned int featureEnabled; //!< Non-zero if feature is enabled, otherwise zero + nvmlGridLicenseExpiry_t licenseExpiry; //!< License expiry structure containing date and time +} nvmlGridLicensableFeature_t; + +/** + * Structure to store vGPU software licensable features + */ +typedef struct nvmlGridLicensableFeatures_st +{ + int isGridLicenseSupported; //!< Non-zero if vGPU Software Licensing is supported on the system, otherwise zero + unsigned int licensableFeaturesCount; //!< Entries returned in \a gridLicensableFeatures array + nvmlGridLicensableFeature_t gridLicensableFeatures[NVML_GRID_LICENSE_FEATURE_MAX_COUNT]; //!< Array of vGPU software licensable features. +} nvmlGridLicensableFeatures_t; + +/** + * GSP firmware + */ +#define NVML_GSP_FIRMWARE_VERSION_BUF_SIZE 0x40 + +/** + * Simplified chip architecture + */ +#define NVML_DEVICE_ARCH_KEPLER 2 // Devices based on the NVIDIA Kepler architecture +#define NVML_DEVICE_ARCH_MAXWELL 3 // Devices based on the NVIDIA Maxwell architecture +#define NVML_DEVICE_ARCH_PASCAL 4 // Devices based on the NVIDIA Pascal architecture +#define NVML_DEVICE_ARCH_VOLTA 5 // Devices based on the NVIDIA Volta architecture +#define NVML_DEVICE_ARCH_TURING 6 // Devices based on the NVIDIA Turing architecture + +#define NVML_DEVICE_ARCH_AMPERE 7 // Devices based on the NVIDIA Ampere architecture + +#define NVML_DEVICE_ARCH_ADA 8 // Devices based on the NVIDIA Ada architecture + +#define NVML_DEVICE_ARCH_HOPPER 9 // Devices based on the NVIDIA Hopper architecture + +#define NVML_DEVICE_ARCH_UNKNOWN 0xffffffff // Anything else, presumably something newer + +typedef unsigned int nvmlDeviceArchitecture_t; + +/** + * PCI bus types + */ +#define NVML_BUS_TYPE_UNKNOWN 0 +#define NVML_BUS_TYPE_PCI 1 +#define NVML_BUS_TYPE_PCIE 2 +#define NVML_BUS_TYPE_FPCI 3 +#define NVML_BUS_TYPE_AGP 4 + +typedef unsigned int nvmlBusType_t; + +/** + * Device Power Modes + */ + +/** + * Device Fan control policy + */ +#define NVML_FAN_POLICY_TEMPERATURE_CONTINOUS_SW 0 +#define NVML_FAN_POLICY_MANUAL 1 + +typedef unsigned int nvmlFanControlPolicy_t; + +/** + * Device Power Source + */ +#define NVML_POWER_SOURCE_AC 0x00000000 +#define NVML_POWER_SOURCE_BATTERY 0x00000001 + +typedef unsigned int nvmlPowerSource_t; + +/* + * Device PCIE link Max Speed + */ +#define NVML_PCIE_LINK_MAX_SPEED_INVALID 0x00000000 +#define NVML_PCIE_LINK_MAX_SPEED_2500MBPS 0x00000001 +#define NVML_PCIE_LINK_MAX_SPEED_5000MBPS 0x00000002 +#define NVML_PCIE_LINK_MAX_SPEED_8000MBPS 0x00000003 +#define NVML_PCIE_LINK_MAX_SPEED_16000MBPS 0x00000004 +#define NVML_PCIE_LINK_MAX_SPEED_32000MBPS 0x00000005 +#define NVML_PCIE_LINK_MAX_SPEED_64000MBPS 0x00000006 + +/* + * Adaptive clocking status + */ +#define NVML_ADAPTIVE_CLOCKING_INFO_STATUS_DISABLED 0x00000000 +#define NVML_ADAPTIVE_CLOCKING_INFO_STATUS_ENABLED 0x00000001 + +#define NVML_MAX_GPU_UTILIZATIONS 8 +typedef enum nvmlGpuUtilizationDomainId_t +{ + NVML_GPU_UTILIZATION_DOMAIN_GPU = 0, //!< Graphics engine domain + NVML_GPU_UTILIZATION_DOMAIN_FB = 1, //!< Frame buffer domain + NVML_GPU_UTILIZATION_DOMAIN_VID = 2, //!< Video engine domain + NVML_GPU_UTILIZATION_DOMAIN_BUS = 3, //!< Bus interface domain +} nvmlGpuUtilizationDomainId_t; + +typedef struct nvmlGpuDynamicPstatesInfo_st +{ + unsigned int flags; //!< Reserved for future use + struct + { + unsigned int bIsPresent; //!< Set if this utilization domain is present on this GPU + unsigned int percentage; //!< Percentage of time where the domain is considered busy in the last 1-second interval + unsigned int incThreshold; //!< Utilization threshold that can trigger a perf-increasing P-State change when crossed + unsigned int decThreshold; //!< Utilization threshold that can trigger a perf-decreasing P-State change when crossed + } utilization[NVML_MAX_GPU_UTILIZATIONS]; +} nvmlGpuDynamicPstatesInfo_t; + +/** @} */ +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlFieldValueEnums Field Value Enums + * @{ + */ +/***************************************************************************************************/ + +/** + * Field Identifiers. + * + * All Identifiers pertain to a device. Each ID is only used once and is guaranteed never to change. + */ +#define NVML_FI_DEV_ECC_CURRENT 1 //!< Current ECC mode. 1=Active. 0=Inactive +#define NVML_FI_DEV_ECC_PENDING 2 //!< Pending ECC mode. 1=Active. 0=Inactive +/* ECC Count Totals */ +#define NVML_FI_DEV_ECC_SBE_VOL_TOTAL 3 //!< Total single bit volatile ECC errors +#define NVML_FI_DEV_ECC_DBE_VOL_TOTAL 4 //!< Total double bit volatile ECC errors +#define NVML_FI_DEV_ECC_SBE_AGG_TOTAL 5 //!< Total single bit aggregate (persistent) ECC errors +#define NVML_FI_DEV_ECC_DBE_AGG_TOTAL 6 //!< Total double bit aggregate (persistent) ECC errors +/* Individual ECC locations */ +#define NVML_FI_DEV_ECC_SBE_VOL_L1 7 //!< L1 cache single bit volatile ECC errors +#define NVML_FI_DEV_ECC_DBE_VOL_L1 8 //!< L1 cache double bit volatile ECC errors +#define NVML_FI_DEV_ECC_SBE_VOL_L2 9 //!< L2 cache single bit volatile ECC errors +#define NVML_FI_DEV_ECC_DBE_VOL_L2 10 //!< L2 cache double bit volatile ECC errors +#define NVML_FI_DEV_ECC_SBE_VOL_DEV 11 //!< Device memory single bit volatile ECC errors +#define NVML_FI_DEV_ECC_DBE_VOL_DEV 12 //!< Device memory double bit volatile ECC errors +#define NVML_FI_DEV_ECC_SBE_VOL_REG 13 //!< Register file single bit volatile ECC errors +#define NVML_FI_DEV_ECC_DBE_VOL_REG 14 //!< Register file double bit volatile ECC errors +#define NVML_FI_DEV_ECC_SBE_VOL_TEX 15 //!< Texture memory single bit volatile ECC errors +#define NVML_FI_DEV_ECC_DBE_VOL_TEX 16 //!< Texture memory double bit volatile ECC errors +#define NVML_FI_DEV_ECC_DBE_VOL_CBU 17 //!< CBU double bit volatile ECC errors +#define NVML_FI_DEV_ECC_SBE_AGG_L1 18 //!< L1 cache single bit aggregate (persistent) ECC errors +#define NVML_FI_DEV_ECC_DBE_AGG_L1 19 //!< L1 cache double bit aggregate (persistent) ECC errors +#define NVML_FI_DEV_ECC_SBE_AGG_L2 20 //!< L2 cache single bit aggregate (persistent) ECC errors +#define NVML_FI_DEV_ECC_DBE_AGG_L2 21 //!< L2 cache double bit aggregate (persistent) ECC errors +#define NVML_FI_DEV_ECC_SBE_AGG_DEV 22 //!< Device memory single bit aggregate (persistent) ECC errors +#define NVML_FI_DEV_ECC_DBE_AGG_DEV 23 //!< Device memory double bit aggregate (persistent) ECC errors +#define NVML_FI_DEV_ECC_SBE_AGG_REG 24 //!< Register File single bit aggregate (persistent) ECC errors +#define NVML_FI_DEV_ECC_DBE_AGG_REG 25 //!< Register File double bit aggregate (persistent) ECC errors +#define NVML_FI_DEV_ECC_SBE_AGG_TEX 26 //!< Texture memory single bit aggregate (persistent) ECC errors +#define NVML_FI_DEV_ECC_DBE_AGG_TEX 27 //!< Texture memory double bit aggregate (persistent) ECC errors +#define NVML_FI_DEV_ECC_DBE_AGG_CBU 28 //!< CBU double bit aggregate ECC errors + +/* Page Retirement */ +#define NVML_FI_DEV_RETIRED_SBE 29 //!< Number of retired pages because of single bit errors +#define NVML_FI_DEV_RETIRED_DBE 30 //!< Number of retired pages because of double bit errors +#define NVML_FI_DEV_RETIRED_PENDING 31 //!< If any pages are pending retirement. 1=yes. 0=no. + +/* NvLink Flit Error Counters */ +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L0 32 //!< NVLink flow control CRC Error Counter for Lane 0 +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L1 33 //!< NVLink flow control CRC Error Counter for Lane 1 +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L2 34 //!< NVLink flow control CRC Error Counter for Lane 2 +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L3 35 //!< NVLink flow control CRC Error Counter for Lane 3 +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L4 36 //!< NVLink flow control CRC Error Counter for Lane 4 +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L5 37 //!< NVLink flow control CRC Error Counter for Lane 5 +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_TOTAL 38 //!< NVLink flow control CRC Error Counter total for all Lanes + +/* NvLink CRC Data Error Counters */ +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L0 39 //!< NVLink data CRC Error Counter for Lane 0 +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L1 40 //!< NVLink data CRC Error Counter for Lane 1 +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L2 41 //!< NVLink data CRC Error Counter for Lane 2 +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L3 42 //!< NVLink data CRC Error Counter for Lane 3 +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L4 43 //!< NVLink data CRC Error Counter for Lane 4 +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L5 44 //!< NVLink data CRC Error Counter for Lane 5 +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_TOTAL 45 //!< NvLink data CRC Error Counter total for all Lanes + +/* NvLink Replay Error Counters */ +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L0 46 //!< NVLink Replay Error Counter for Lane 0 +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L1 47 //!< NVLink Replay Error Counter for Lane 1 +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L2 48 //!< NVLink Replay Error Counter for Lane 2 +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L3 49 //!< NVLink Replay Error Counter for Lane 3 +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L4 50 //!< NVLink Replay Error Counter for Lane 4 +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L5 51 //!< NVLink Replay Error Counter for Lane 5 +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_TOTAL 52 //!< NVLink Replay Error Counter total for all Lanes + +/* NvLink Recovery Error Counters */ +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L0 53 //!< NVLink Recovery Error Counter for Lane 0 +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L1 54 //!< NVLink Recovery Error Counter for Lane 1 +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L2 55 //!< NVLink Recovery Error Counter for Lane 2 +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L3 56 //!< NVLink Recovery Error Counter for Lane 3 +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L4 57 //!< NVLink Recovery Error Counter for Lane 4 +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L5 58 //!< NVLink Recovery Error Counter for Lane 5 +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_TOTAL 59 //!< NVLink Recovery Error Counter total for all Lanes + +/* NvLink Bandwidth Counters */ +/* + * NVML_FI_DEV_NVLINK_BANDWIDTH_* field values are now deprecated. + * Please use the following field values instead: + * NVML_FI_DEV_NVLINK_THROUGHPUT_DATA_TX + * NVML_FI_DEV_NVLINK_THROUGHPUT_DATA_RX + * NVML_FI_DEV_NVLINK_THROUGHPUT_RAW_TX + * NVML_FI_DEV_NVLINK_THROUGHPUT_RAW_RX + */ +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L0 60 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 0 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L1 61 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 1 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L2 62 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 2 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L3 63 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 3 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L4 64 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 4 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L5 65 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 5 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_TOTAL 66 //!< NVLink Bandwidth Counter Total for Counter Set 0, All Lanes + +/* NvLink Bandwidth Counters */ +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L0 67 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 0 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L1 68 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 1 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L2 69 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 2 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L3 70 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 3 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L4 71 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 4 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L5 72 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 5 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_TOTAL 73 //!< NVLink Bandwidth Counter Total for Counter Set 1, All Lanes + +/* NVML Perf Policy Counters */ +#define NVML_FI_DEV_PERF_POLICY_POWER 74 //!< Perf Policy Counter for Power Policy +#define NVML_FI_DEV_PERF_POLICY_THERMAL 75 //!< Perf Policy Counter for Thermal Policy +#define NVML_FI_DEV_PERF_POLICY_SYNC_BOOST 76 //!< Perf Policy Counter for Sync boost Policy +#define NVML_FI_DEV_PERF_POLICY_BOARD_LIMIT 77 //!< Perf Policy Counter for Board Limit +#define NVML_FI_DEV_PERF_POLICY_LOW_UTILIZATION 78 //!< Perf Policy Counter for Low GPU Utilization Policy +#define NVML_FI_DEV_PERF_POLICY_RELIABILITY 79 //!< Perf Policy Counter for Reliability Policy +#define NVML_FI_DEV_PERF_POLICY_TOTAL_APP_CLOCKS 80 //!< Perf Policy Counter for Total App Clock Policy +#define NVML_FI_DEV_PERF_POLICY_TOTAL_BASE_CLOCKS 81 //!< Perf Policy Counter for Total Base Clocks Policy + +/* Memory temperatures */ +#define NVML_FI_DEV_MEMORY_TEMP 82 //!< Memory temperature for the device + +/* Energy Counter */ +#define NVML_FI_DEV_TOTAL_ENERGY_CONSUMPTION 83 //!< Total energy consumption for the GPU in mJ since the driver was last reloaded + +/* NVLink Speed */ +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L0 84 //!< NVLink Speed in MBps for Link 0 +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L1 85 //!< NVLink Speed in MBps for Link 1 +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L2 86 //!< NVLink Speed in MBps for Link 2 +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L3 87 //!< NVLink Speed in MBps for Link 3 +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L4 88 //!< NVLink Speed in MBps for Link 4 +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L5 89 //!< NVLink Speed in MBps for Link 5 +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_COMMON 90 //!< Common NVLink Speed in MBps for active links + +#define NVML_FI_DEV_NVLINK_LINK_COUNT 91 //!< Number of NVLinks present on the device + +#define NVML_FI_DEV_RETIRED_PENDING_SBE 92 //!< If any pages are pending retirement due to SBE. 1=yes. 0=no. +#define NVML_FI_DEV_RETIRED_PENDING_DBE 93 //!< If any pages are pending retirement due to DBE. 1=yes. 0=no. + +#define NVML_FI_DEV_PCIE_REPLAY_COUNTER 94 //!< PCIe replay counter +#define NVML_FI_DEV_PCIE_REPLAY_ROLLOVER_COUNTER 95 //!< PCIe replay rollover counter + +/* NvLink Flit Error Counters */ +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L6 96 //!< NVLink flow control CRC Error Counter for Lane 6 +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L7 97 //!< NVLink flow control CRC Error Counter for Lane 7 +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L8 98 //!< NVLink flow control CRC Error Counter for Lane 8 +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L9 99 //!< NVLink flow control CRC Error Counter for Lane 9 +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L10 100 //!< NVLink flow control CRC Error Counter for Lane 10 +#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L11 101 //!< NVLink flow control CRC Error Counter for Lane 11 + +/* NvLink CRC Data Error Counters */ +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L6 102 //!< NVLink data CRC Error Counter for Lane 6 +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L7 103 //!< NVLink data CRC Error Counter for Lane 7 +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L8 104 //!< NVLink data CRC Error Counter for Lane 8 +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L9 105 //!< NVLink data CRC Error Counter for Lane 9 +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L10 106 //!< NVLink data CRC Error Counter for Lane 10 +#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L11 107 //!< NVLink data CRC Error Counter for Lane 11 + +/* NvLink Replay Error Counters */ +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L6 108 //!< NVLink Replay Error Counter for Lane 6 +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L7 109 //!< NVLink Replay Error Counter for Lane 7 +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L8 110 //!< NVLink Replay Error Counter for Lane 8 +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L9 111 //!< NVLink Replay Error Counter for Lane 9 +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L10 112 //!< NVLink Replay Error Counter for Lane 10 +#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L11 113 //!< NVLink Replay Error Counter for Lane 11 + +/* NvLink Recovery Error Counters */ +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L6 114 //!< NVLink Recovery Error Counter for Lane 6 +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L7 115 //!< NVLink Recovery Error Counter for Lane 7 +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L8 116 //!< NVLink Recovery Error Counter for Lane 8 +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L9 117 //!< NVLink Recovery Error Counter for Lane 9 +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L10 118 //!< NVLink Recovery Error Counter for Lane 10 +#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L11 119 //!< NVLink Recovery Error Counter for Lane 11 + +/* NvLink Bandwidth Counters */ +/* + * NVML_FI_DEV_NVLINK_BANDWIDTH_* field values are now deprecated. + * Please use the following field values instead: + * NVML_FI_DEV_NVLINK_THROUGHPUT_DATA_TX + * NVML_FI_DEV_NVLINK_THROUGHPUT_DATA_RX + * NVML_FI_DEV_NVLINK_THROUGHPUT_RAW_TX + * NVML_FI_DEV_NVLINK_THROUGHPUT_RAW_RX + */ +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L6 120 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 6 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L7 121 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 7 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L8 122 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 8 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L9 123 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 9 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L10 124 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 10 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L11 125 //!< NVLink Bandwidth Counter for Counter Set 0, Lane 11 + +/* NvLink Bandwidth Counters */ +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L6 126 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 6 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L7 127 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 7 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L8 128 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 8 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L9 129 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 9 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L10 130 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 10 +#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L11 131 //!< NVLink Bandwidth Counter for Counter Set 1, Lane 11 + +/* NVLink Speed */ +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L6 132 //!< NVLink Speed in MBps for Link 6 +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L7 133 //!< NVLink Speed in MBps for Link 7 +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L8 134 //!< NVLink Speed in MBps for Link 8 +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L9 135 //!< NVLink Speed in MBps for Link 9 +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L10 136 //!< NVLink Speed in MBps for Link 10 +#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L11 137 //!< NVLink Speed in MBps for Link 11 + +/** + * NVLink throughput counters field values + * + * Link ID needs to be specified in the scopeId field in nvmlFieldValue_t. + * A scopeId of UINT_MAX returns aggregate value summed up across all links + * for the specified counter type in fieldId. + */ +#define NVML_FI_DEV_NVLINK_THROUGHPUT_DATA_TX 138 //!< NVLink TX Data throughput in KiB +#define NVML_FI_DEV_NVLINK_THROUGHPUT_DATA_RX 139 //!< NVLink RX Data throughput in KiB +#define NVML_FI_DEV_NVLINK_THROUGHPUT_RAW_TX 140 //!< NVLink TX Data + protocol overhead in KiB +#define NVML_FI_DEV_NVLINK_THROUGHPUT_RAW_RX 141 //!< NVLink RX Data + protocol overhead in KiB + +/* Row Remapper */ +#define NVML_FI_DEV_REMAPPED_COR 142 //!< Number of remapped rows due to correctable errors +#define NVML_FI_DEV_REMAPPED_UNC 143 //!< Number of remapped rows due to uncorrectable errors +#define NVML_FI_DEV_REMAPPED_PENDING 144 //!< If any rows are pending remapping. 1=yes 0=no +#define NVML_FI_DEV_REMAPPED_FAILURE 145 //!< If any rows failed to be remapped 1=yes 0=no + +/** + * Remote device NVLink ID + * + * Link ID needs to be specified in the scopeId field in nvmlFieldValue_t. + */ +#define NVML_FI_DEV_NVLINK_REMOTE_NVLINK_ID 146 //!< Remote device NVLink ID + +/** + * NVSwitch: connected NVLink count + */ +#define NVML_FI_DEV_NVSWITCH_CONNECTED_LINK_COUNT 147 //!< Number of NVLinks connected to NVSwitch + +/* NvLink ECC Data Error Counters + * + * Lane ID needs to be specified in the scopeId field in nvmlFieldValue_t. + * + */ +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L0 148 //!< NVLink data ECC Error Counter for Link 0 +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L1 149 //!< NVLink data ECC Error Counter for Link 1 +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L2 150 //!< NVLink data ECC Error Counter for Link 2 +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L3 151 //!< NVLink data ECC Error Counter for Link 3 +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L4 152 //!< NVLink data ECC Error Counter for Link 4 +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L5 153 //!< NVLink data ECC Error Counter for Link 5 +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L6 154 //!< NVLink data ECC Error Counter for Link 6 +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L7 155 //!< NVLink data ECC Error Counter for Link 7 +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L8 156 //!< NVLink data ECC Error Counter for Link 8 +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L9 157 //!< NVLink data ECC Error Counter for Link 9 +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L10 158 //!< NVLink data ECC Error Counter for Link 10 +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L11 159 //!< NVLink data ECC Error Counter for Link 11 +#define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_TOTAL 160 //!< NvLink data ECC Error Counter total for all Links + +#define NVML_FI_DEV_NVLINK_ERROR_DL_REPLAY 161 +#define NVML_FI_DEV_NVLINK_ERROR_DL_RECOVERY 162 +#define NVML_FI_DEV_NVLINK_ERROR_DL_CRC 163 +#define NVML_FI_DEV_NVLINK_GET_SPEED 164 +#define NVML_FI_DEV_NVLINK_GET_STATE 165 +#define NVML_FI_DEV_NVLINK_GET_VERSION 166 + +#define NVML_FI_DEV_NVLINK_GET_POWER_STATE 167 +#define NVML_FI_DEV_NVLINK_GET_POWER_THRESHOLD 168 + +#define NVML_FI_DEV_PCIE_L0_TO_RECOVERY_COUNTER 169 + +#define NVML_FI_MAX 170 //!< One greater than the largest field ID defined above + +/** + * Information for a Field Value Sample + */ +typedef struct nvmlFieldValue_st +{ + unsigned int fieldId; //!< ID of the NVML field to retrieve. This must be set before any call that uses this struct. See the constants starting with NVML_FI_ above. + unsigned int scopeId; //!< Scope ID can represent data used by NVML depending on fieldId's context. For example, for NVLink throughput counter data, scopeId can represent linkId. + long long timestamp; //!< CPU Timestamp of this value in microseconds since 1970 + long long latencyUsec; //!< How long this field value took to update (in usec) within NVML. This may be averaged across several fields that are serviced by the same driver call. + nvmlValueType_t valueType; //!< Type of the value stored in value + nvmlReturn_t nvmlReturn; //!< Return code for retrieving this value. This must be checked before looking at value, as value is undefined if nvmlReturn != NVML_SUCCESS + nvmlValue_t value; //!< Value for this field. This is only valid if nvmlReturn == NVML_SUCCESS +} nvmlFieldValue_t; + + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlUnitStructs Unit Structs + * @{ + */ +/***************************************************************************************************/ + +typedef struct nvmlUnit_st* nvmlUnit_t; + +/** + * Description of HWBC entry + */ +typedef struct nvmlHwbcEntry_st +{ + unsigned int hwbcId; + char firmwareVersion[32]; +} nvmlHwbcEntry_t; + +/** + * Fan state enum. + */ +typedef enum nvmlFanState_enum +{ + NVML_FAN_NORMAL = 0, //!< Fan is working properly + NVML_FAN_FAILED = 1 //!< Fan has failed +} nvmlFanState_t; + +/** + * Led color enum. + */ +typedef enum nvmlLedColor_enum +{ + NVML_LED_COLOR_GREEN = 0, //!< GREEN, indicates good health + NVML_LED_COLOR_AMBER = 1 //!< AMBER, indicates problem +} nvmlLedColor_t; + + +/** + * LED states for an S-class unit. + */ +typedef struct nvmlLedState_st +{ + char cause[256]; //!< If amber, a text description of the cause + nvmlLedColor_t color; //!< GREEN or AMBER +} nvmlLedState_t; + +/** + * Static S-class unit info. + */ +typedef struct nvmlUnitInfo_st +{ + char name[96]; //!< Product name + char id[96]; //!< Product identifier + char serial[96]; //!< Product serial number + char firmwareVersion[96]; //!< Firmware version +} nvmlUnitInfo_t; + +/** + * Power usage information for an S-class unit. + * The power supply state is a human readable string that equals "Normal" or contains + * a combination of "Abnormal" plus one or more of the following: + * + * - High voltage + * - Fan failure + * - Heatsink temperature + * - Current limit + * - Voltage below UV alarm threshold + * - Low-voltage + * - SI2C remote off command + * - MOD_DISABLE input + * - Short pin transition +*/ +typedef struct nvmlPSUInfo_st +{ + char state[256]; //!< The power supply state + unsigned int current; //!< PSU current (A) + unsigned int voltage; //!< PSU voltage (V) + unsigned int power; //!< PSU power draw (W) +} nvmlPSUInfo_t; + +/** + * Fan speed reading for a single fan in an S-class unit. + */ +typedef struct nvmlUnitFanInfo_st +{ + unsigned int speed; //!< Fan speed (RPM) + nvmlFanState_t state; //!< Flag that indicates whether fan is working properly +} nvmlUnitFanInfo_t; + +/** + * Fan speed readings for an entire S-class unit. + */ +typedef struct nvmlUnitFanSpeeds_st +{ + nvmlUnitFanInfo_t fans[24]; //!< Fan speed data for each fan + unsigned int count; //!< Number of fans in unit +} nvmlUnitFanSpeeds_t; + +/** @} */ + +/***************************************************************************************************/ +/** @addtogroup nvmlEvents + * @{ + */ +/***************************************************************************************************/ + +/** + * Handle to an event set + */ +typedef struct nvmlEventSet_st* nvmlEventSet_t; + +/** @defgroup nvmlEventType Event Types + * @{ + * Event Types which user can be notified about. + * See description of particular functions for details. + * + * See \ref nvmlDeviceRegisterEvents and \ref nvmlDeviceGetSupportedEventTypes to check which devices + * support each event. + * + * Types can be combined with bitwise or operator '|' when passed to \ref nvmlDeviceRegisterEvents + */ +//! Event about single bit ECC errors +/** + * \note A corrected texture memory error is not an ECC error, so it does not generate a single bit event + */ +#define nvmlEventTypeSingleBitEccError 0x0000000000000001LL + +//! Event about double bit ECC errors +/** + * \note An uncorrected texture memory error is not an ECC error, so it does not generate a double bit event + */ +#define nvmlEventTypeDoubleBitEccError 0x0000000000000002LL + +//! Event about PState changes +/** + * \note On Fermi architecture PState changes are also an indicator that GPU is throttling down due to + * no work being executed on the GPU, power capping or thermal capping. In a typical situation, + * Fermi-based GPU should stay in P0 for the duration of the execution of the compute process. + */ +#define nvmlEventTypePState 0x0000000000000004LL + +//! Event that Xid critical error occurred +#define nvmlEventTypeXidCriticalError 0x0000000000000008LL + +//! Event about clock changes +/** + * Kepler only + */ +#define nvmlEventTypeClock 0x0000000000000010LL + +//! Event about AC/Battery power source changes +#define nvmlEventTypePowerSourceChange 0x0000000000000080LL + +//! Event about MIG configuration changes +#define nvmlEventMigConfigChange 0x0000000000000100LL + +//! Mask with no events +#define nvmlEventTypeNone 0x0000000000000000LL + +//! Mask of all events +#define nvmlEventTypeAll (nvmlEventTypeNone \ + | nvmlEventTypeSingleBitEccError \ + | nvmlEventTypeDoubleBitEccError \ + | nvmlEventTypePState \ + | nvmlEventTypeClock \ + | nvmlEventTypeXidCriticalError \ + | nvmlEventTypePowerSourceChange \ + | nvmlEventMigConfigChange \ + ) +/** @} */ + +/** + * Information about occurred event + */ +typedef struct nvmlEventData_st +{ + nvmlDevice_t device; //!< Specific device where the event occurred + unsigned long long eventType; //!< Information about what specific event occurred + unsigned long long eventData; //!< Stores XID error for the device in the event of nvmlEventTypeXidCriticalError, + // eventData is 0 for any other event. eventData is set as 999 for unknown xid error. + unsigned int gpuInstanceId; //!< If MIG is enabled and nvmlEventTypeXidCriticalError event is attributable to a GPU + // instance, stores a valid GPU instance ID. gpuInstanceId is set to 0xFFFFFFFF + // otherwise. + unsigned int computeInstanceId; //!< If MIG is enabled and nvmlEventTypeXidCriticalError event is attributable to a + // compute instance, stores a valid compute instance ID. computeInstanceId is set to + // 0xFFFFFFFF otherwise. +} nvmlEventData_t; + +/** @} */ + +/***************************************************************************************************/ +/** @addtogroup nvmlClocksThrottleReasons + * @{ + */ +/***************************************************************************************************/ + +/** Nothing is running on the GPU and the clocks are dropping to Idle state + * \note This limiter may be removed in a later release + */ +#define nvmlClocksThrottleReasonGpuIdle 0x0000000000000001LL + +/** GPU clocks are limited by current setting of applications clocks + * + * @see nvmlDeviceSetApplicationsClocks + * @see nvmlDeviceGetApplicationsClock + */ +#define nvmlClocksThrottleReasonApplicationsClocksSetting 0x0000000000000002LL + +/** + * @deprecated Renamed to \ref nvmlClocksThrottleReasonApplicationsClocksSetting + * as the name describes the situation more accurately. + */ +#define nvmlClocksThrottleReasonUserDefinedClocks nvmlClocksThrottleReasonApplicationsClocksSetting + +/** SW Power Scaling algorithm is reducing the clocks below requested clocks + * + * @see nvmlDeviceGetPowerUsage + * @see nvmlDeviceSetPowerManagementLimit + * @see nvmlDeviceGetPowerManagementLimit + */ +#define nvmlClocksThrottleReasonSwPowerCap 0x0000000000000004LL + +/** HW Slowdown (reducing the core clocks by a factor of 2 or more) is engaged + * + * This is an indicator of: + * - temperature being too high + * - External Power Brake Assertion is triggered (e.g. by the system power supply) + * - Power draw is too high and Fast Trigger protection is reducing the clocks + * - May be also reported during PState or clock change + * - This behavior may be removed in a later release. + * + * @see nvmlDeviceGetTemperature + * @see nvmlDeviceGetTemperatureThreshold + * @see nvmlDeviceGetPowerUsage + */ +#define nvmlClocksThrottleReasonHwSlowdown 0x0000000000000008LL + +/** Sync Boost + * + * This GPU has been added to a Sync boost group with nvidia-smi or DCGM in + * order to maximize performance per watt. All GPUs in the sync boost group + * will boost to the minimum possible clocks across the entire group. Look at + * the throttle reasons for other GPUs in the system to see why those GPUs are + * holding this one at lower clocks. + * + */ +#define nvmlClocksThrottleReasonSyncBoost 0x0000000000000010LL + +/** SW Thermal Slowdown + * + * This is an indicator of one or more of the following: + * - Current GPU temperature above the GPU Max Operating Temperature + * - Current memory temperature above the Memory Max Operating Temperature + * + */ +#define nvmlClocksThrottleReasonSwThermalSlowdown 0x0000000000000020LL + +/** HW Thermal Slowdown (reducing the core clocks by a factor of 2 or more) is engaged + * + * This is an indicator of: + * - temperature being too high + * + * @see nvmlDeviceGetTemperature + * @see nvmlDeviceGetTemperatureThreshold + * @see nvmlDeviceGetPowerUsage + */ +#define nvmlClocksThrottleReasonHwThermalSlowdown 0x0000000000000040LL + +/** HW Power Brake Slowdown (reducing the core clocks by a factor of 2 or more) is engaged + * + * This is an indicator of: + * - External Power Brake Assertion being triggered (e.g. by the system power supply) + * + * @see nvmlDeviceGetTemperature + * @see nvmlDeviceGetTemperatureThreshold + * @see nvmlDeviceGetPowerUsage + */ +#define nvmlClocksThrottleReasonHwPowerBrakeSlowdown 0x0000000000000080LL + +/** GPU clocks are limited by current setting of Display clocks + * + * @see bug 1997531 + */ +#define nvmlClocksThrottleReasonDisplayClockSetting 0x0000000000000100LL + +/** Bit mask representing no clocks throttling + * + * Clocks are as high as possible. + * */ +#define nvmlClocksThrottleReasonNone 0x0000000000000000LL + +/** Bit mask representing all supported clocks throttling reasons + * New reasons might be added to this list in the future + */ +#define nvmlClocksThrottleReasonAll (nvmlClocksThrottleReasonNone \ + | nvmlClocksThrottleReasonGpuIdle \ + | nvmlClocksThrottleReasonApplicationsClocksSetting \ + | nvmlClocksThrottleReasonSwPowerCap \ + | nvmlClocksThrottleReasonHwSlowdown \ + | nvmlClocksThrottleReasonSyncBoost \ + | nvmlClocksThrottleReasonSwThermalSlowdown \ + | nvmlClocksThrottleReasonHwThermalSlowdown \ + | nvmlClocksThrottleReasonHwPowerBrakeSlowdown \ + | nvmlClocksThrottleReasonDisplayClockSetting \ +) +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlAccountingStats Accounting Statistics + * @{ + * + * Set of APIs designed to provide per process information about usage of GPU. + * + * @note All accounting statistics and accounting mode live in nvidia driver and reset + * to default (Disabled) when driver unloads. + * It is advised to run with persistence mode enabled. + * + * @note Enabling accounting mode has no negative impact on the GPU performance. + */ +/***************************************************************************************************/ + +/** + * Describes accounting statistics of a process. + */ +typedef struct nvmlAccountingStats_st { + unsigned int gpuUtilization; //!< Percent of time over the process's lifetime during which one or more kernels was executing on the GPU. + //! Utilization stats just like returned by \ref nvmlDeviceGetUtilizationRates but for the life time of a + //! process (not just the last sample period). + //! Set to NVML_VALUE_NOT_AVAILABLE if nvmlDeviceGetUtilizationRates is not supported + + unsigned int memoryUtilization; //!< Percent of time over the process's lifetime during which global (device) memory was being read or written. + //! Set to NVML_VALUE_NOT_AVAILABLE if nvmlDeviceGetUtilizationRates is not supported + + unsigned long long maxMemoryUsage; //!< Maximum total memory in bytes that was ever allocated by the process. + //! Set to NVML_VALUE_NOT_AVAILABLE if nvmlProcessInfo_t->usedGpuMemory is not supported + + + unsigned long long time; //!< Amount of time in ms during which the compute context was active. The time is reported as 0 if + //!< the process is not terminated + + unsigned long long startTime; //!< CPU Timestamp in usec representing start time for the process + + unsigned int isRunning; //!< Flag to represent if the process is running (1 for running, 0 for terminated) + + unsigned int reserved[5]; //!< Reserved for future use +} nvmlAccountingStats_t; + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlEncoderStructs Encoder Structs + * @{ + */ +/***************************************************************************************************/ + +/** + * Represents type of encoder for capacity can be queried + */ +typedef enum nvmlEncoderQueryType_enum +{ + NVML_ENCODER_QUERY_H264 = 0, //!< H264 encoder + NVML_ENCODER_QUERY_HEVC = 1 //!< HEVC encoder +}nvmlEncoderType_t; + +/** + * Structure to hold encoder session data + */ +typedef struct nvmlEncoderSessionInfo_st +{ + unsigned int sessionId; //!< Unique session ID + unsigned int pid; //!< Owning process ID + nvmlVgpuInstance_t vgpuInstance; //!< Owning vGPU instance ID (only valid on vGPU hosts, otherwise zero) + nvmlEncoderType_t codecType; //!< Video encoder type + unsigned int hResolution; //!< Current encode horizontal resolution + unsigned int vResolution; //!< Current encode vertical resolution + unsigned int averageFps; //!< Moving average encode frames per second + unsigned int averageLatency; //!< Moving average encode latency in microseconds +}nvmlEncoderSessionInfo_t; + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlFBCStructs Frame Buffer Capture Structures +* @{ +*/ +/***************************************************************************************************/ + +/** + * Represents frame buffer capture session type + */ +typedef enum nvmlFBCSessionType_enum +{ + NVML_FBC_SESSION_TYPE_UNKNOWN = 0, //!< Unknwon + NVML_FBC_SESSION_TYPE_TOSYS, //!< ToSys + NVML_FBC_SESSION_TYPE_CUDA, //!< Cuda + NVML_FBC_SESSION_TYPE_VID, //!< Vid + NVML_FBC_SESSION_TYPE_HWENC //!< HEnc +} nvmlFBCSessionType_t; + +/** + * Structure to hold frame buffer capture sessions stats + */ +typedef struct nvmlFBCStats_st +{ + unsigned int sessionsCount; //!< Total no of sessions + unsigned int averageFPS; //!< Moving average new frames captured per second + unsigned int averageLatency; //!< Moving average new frame capture latency in microseconds +} nvmlFBCStats_t; + +#define NVML_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED 0x00000001 //!< Bit specifying differential map state. +#define NVML_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED 0x00000002 //!< Bit specifying classification map state. +#define NVML_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_NO_WAIT 0x00000004 //!< Bit specifying if capture was requested as non-blocking call. +#define NVML_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_INFINITE 0x00000008 //!< Bit specifying if capture was requested as blocking call. +#define NVML_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_TIMEOUT 0x00000010 //!< Bit specifying if capture was requested as blocking call with timeout period. + +/** + * Structure to hold FBC session data + */ +typedef struct nvmlFBCSessionInfo_st +{ + unsigned int sessionId; //!< Unique session ID + unsigned int pid; //!< Owning process ID + nvmlVgpuInstance_t vgpuInstance; //!< Owning vGPU instance ID (only valid on vGPU hosts, otherwise zero) + unsigned int displayOrdinal; //!< Display identifier + nvmlFBCSessionType_t sessionType; //!< Type of frame buffer capture session + unsigned int sessionFlags; //!< Session flags (one or more of NVML_NVFBC_SESSION_FLAG_XXX). + unsigned int hMaxResolution; //!< Max horizontal resolution supported by the capture session + unsigned int vMaxResolution; //!< Max vertical resolution supported by the capture session + unsigned int hResolution; //!< Horizontal resolution requested by caller in capture call + unsigned int vResolution; //!< Vertical resolution requested by caller in capture call + unsigned int averageFPS; //!< Moving average new frames captured per second + unsigned int averageLatency; //!< Moving average new frame capture latency in microseconds +} nvmlFBCSessionInfo_t; + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlDrainDefs definitions related to the drain state + * @{ + */ +/***************************************************************************************************/ + +/** + * Is the GPU device to be removed from the kernel by nvmlDeviceRemoveGpu() + */ +typedef enum nvmlDetachGpuState_enum +{ + NVML_DETACH_GPU_KEEP = 0, + NVML_DETACH_GPU_REMOVE +} nvmlDetachGpuState_t; + +/** + * Parent bridge PCIe link state requested by nvmlDeviceRemoveGpu() + */ +typedef enum nvmlPcieLinkState_enum +{ + NVML_PCIE_LINK_KEEP = 0, + NVML_PCIE_LINK_SHUT_DOWN +} nvmlPcieLinkState_t; + +/** @} */ + +#define NVML_GPU_FABRIC_UUID_LEN 16 + +#define NVML_GPU_FABRIC_STATE_NOT_SUPPORTED 0 +#define NVML_GPU_FABRIC_STATE_NOT_STARTED 1 +#define NVML_GPU_FABRIC_STATE_IN_PROGRESS 2 +#define NVML_GPU_FABRIC_STATE_COMPLETED 3 + +typedef unsigned char nvmlGpuFabricState_t; + +typedef struct { + char clusterUuid[NVML_GPU_FABRIC_UUID_LEN]; //!< Uuid of the cluster to which this GPU belongs + nvmlReturn_t status; //!< Error status, if any. Must be checked only if state returns "complete". + unsigned int partitionId; //!< ID of the fabric partition to which this GPU belongs + nvmlGpuFabricState_t state; //!< Current state of GPU registration process +} nvmlGpuFabricInfo_t; +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlInitializationAndCleanup Initialization and Cleanup + * This chapter describes the methods that handle NVML initialization and cleanup. + * It is the user's responsibility to call \ref nvmlInit_v2() before calling any other methods, and + * nvmlShutdown() once NVML is no longer being used. + * @{ + */ +/***************************************************************************************************/ + +#define NVML_INIT_FLAG_NO_GPUS 1 //!< Don't fail nvmlInit() when no GPUs are found +#define NVML_INIT_FLAG_NO_ATTACH 2 //!< Don't attach GPUs + +/** + * Initialize NVML, but don't initialize any GPUs yet. + * + * \note nvmlInit_v3 introduces a "flags" argument, that allows passing boolean values + * modifying the behaviour of nvmlInit(). + * \note In NVML 5.319 new nvmlInit_v2 has replaced nvmlInit"_v1" (default in NVML 4.304 and older) that + * did initialize all GPU devices in the system. + * + * This allows NVML to communicate with a GPU + * when other GPUs in the system are unstable or in a bad state. When using this API, GPUs are + * discovered and initialized in nvmlDeviceGetHandleBy* functions instead. + * + * \note To contrast nvmlInit_v2 with nvmlInit"_v1", NVML 4.304 nvmlInit"_v1" will fail when any detected GPU is in + * a bad or unstable state. + * + * For all products. + * + * This method, should be called once before invoking any other methods in the library. + * A reference count of the number of initializations is maintained. Shutdown only occurs + * when the reference count reaches zero. + * + * @return + * - \ref NVML_SUCCESS if NVML has been properly initialized + * - \ref NVML_ERROR_DRIVER_NOT_LOADED if NVIDIA driver is not running + * - \ref NVML_ERROR_NO_PERMISSION if NVML does not have permission to talk to the driver + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlInit_v2(void); + +/** + * nvmlInitWithFlags is a variant of nvmlInit(), that allows passing a set of boolean values + * modifying the behaviour of nvmlInit(). + * Other than the "flags" parameter it is completely similar to \ref nvmlInit_v2. + * + * For all products. + * + * @param flags behaviour modifier flags + * + * @return + * - \ref NVML_SUCCESS if NVML has been properly initialized + * - \ref NVML_ERROR_DRIVER_NOT_LOADED if NVIDIA driver is not running + * - \ref NVML_ERROR_NO_PERMISSION if NVML does not have permission to talk to the driver + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlInitWithFlags(unsigned int flags); + +/** + * Shut down NVML by releasing all GPU resources previously allocated with \ref nvmlInit_v2(). + * + * For all products. + * + * This method should be called after NVML work is done, once for each call to \ref nvmlInit_v2() + * A reference count of the number of initializations is maintained. Shutdown only occurs + * when the reference count reaches zero. For backwards compatibility, no error is reported if + * nvmlShutdown() is called more times than nvmlInit(). + * + * @return + * - \ref NVML_SUCCESS if NVML has been properly shut down + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlShutdown(void); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlErrorReporting Error reporting + * This chapter describes helper functions for error reporting routines. + * @{ + */ +/***************************************************************************************************/ + +/** + * Helper method for converting NVML error codes into readable strings. + * + * For all products. + * + * @param result NVML error code to convert + * + * @return String representation of the error. + * + */ +const DECLDIR char* nvmlErrorString(nvmlReturn_t result); +/** @} */ + + +/***************************************************************************************************/ +/** @defgroup nvmlConstants Constants + * @{ + */ +/***************************************************************************************************/ + +/** + * Buffer size guaranteed to be large enough for \ref nvmlDeviceGetInforomVersion and \ref nvmlDeviceGetInforomImageVersion + */ +#define NVML_DEVICE_INFOROM_VERSION_BUFFER_SIZE 16 + +/** + * Buffer size guaranteed to be large enough for storing GPU identifiers. + */ +#define NVML_DEVICE_UUID_BUFFER_SIZE 80 + +/** + * Buffer size guaranteed to be large enough for \ref nvmlDeviceGetUUID + */ +#define NVML_DEVICE_UUID_V2_BUFFER_SIZE 96 + +/** + * Buffer size guaranteed to be large enough for \ref nvmlDeviceGetBoardPartNumber + */ +#define NVML_DEVICE_PART_NUMBER_BUFFER_SIZE 80 + +/** + * Buffer size guaranteed to be large enough for \ref nvmlSystemGetDriverVersion + */ +#define NVML_SYSTEM_DRIVER_VERSION_BUFFER_SIZE 80 + +/** + * Buffer size guaranteed to be large enough for \ref nvmlSystemGetNVMLVersion + */ +#define NVML_SYSTEM_NVML_VERSION_BUFFER_SIZE 80 + +/** + * Buffer size guaranteed to be large enough for storing GPU device names. + */ +#define NVML_DEVICE_NAME_BUFFER_SIZE 64 + +/** + * Buffer size guaranteed to be large enough for \ref nvmlDeviceGetName + */ +#define NVML_DEVICE_NAME_V2_BUFFER_SIZE 96 + +/** + * Buffer size guaranteed to be large enough for \ref nvmlDeviceGetSerial + */ +#define NVML_DEVICE_SERIAL_BUFFER_SIZE 30 + +/** + * Buffer size guaranteed to be large enough for \ref nvmlDeviceGetVbiosVersion + */ +#define NVML_DEVICE_VBIOS_VERSION_BUFFER_SIZE 32 + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlSystemQueries System Queries + * This chapter describes the queries that NVML can perform against the local system. These queries + * are not device-specific. + * @{ + */ +/***************************************************************************************************/ + +/** + * Retrieves the version of the system's graphics driver. + * + * For all products. + * + * The version identifier is an alphanumeric string. It will not exceed 80 characters in length + * (including the NULL terminator). See \ref nvmlConstants::NVML_SYSTEM_DRIVER_VERSION_BUFFER_SIZE. + * + * @param version Reference in which to return the version identifier + * @param length The maximum allowed length of the string returned in \a version + * + * @return + * - \ref NVML_SUCCESS if \a version has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a version is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a length is too small + */ +nvmlReturn_t DECLDIR nvmlSystemGetDriverVersion(char *version, unsigned int length); + +/** + * Retrieves the version of the NVML library. + * + * For all products. + * + * The version identifier is an alphanumeric string. It will not exceed 80 characters in length + * (including the NULL terminator). See \ref nvmlConstants::NVML_SYSTEM_NVML_VERSION_BUFFER_SIZE. + * + * @param version Reference in which to return the version identifier + * @param length The maximum allowed length of the string returned in \a version + * + * @return + * - \ref NVML_SUCCESS if \a version has been set + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a version is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a length is too small + */ +nvmlReturn_t DECLDIR nvmlSystemGetNVMLVersion(char *version, unsigned int length); + +/** + * Retrieves the version of the CUDA driver. + * + * For all products. + * + * The CUDA driver version returned will be retreived from the currently installed version of CUDA. + * If the cuda library is not found, this function will return a known supported version number. + * + * @param cudaDriverVersion Reference in which to return the version identifier + * + * @return + * - \ref NVML_SUCCESS if \a cudaDriverVersion has been set + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a cudaDriverVersion is NULL + */ +nvmlReturn_t DECLDIR nvmlSystemGetCudaDriverVersion(int *cudaDriverVersion); + +/** + * Retrieves the version of the CUDA driver from the shared library. + * + * For all products. + * + * The returned CUDA driver version by calling cuDriverGetVersion() + * + * @param cudaDriverVersion Reference in which to return the version identifier + * + * @return + * - \ref NVML_SUCCESS if \a cudaDriverVersion has been set + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a cudaDriverVersion is NULL + * - \ref NVML_ERROR_LIBRARY_NOT_FOUND if \a libcuda.so.1 or libcuda.dll is not found + * - \ref NVML_ERROR_FUNCTION_NOT_FOUND if \a cuDriverGetVersion() is not found in the shared library + */ +nvmlReturn_t DECLDIR nvmlSystemGetCudaDriverVersion_v2(int *cudaDriverVersion); + +/** + * Macros for converting the CUDA driver version number to Major and Minor version numbers. + */ +#define NVML_CUDA_DRIVER_VERSION_MAJOR(v) ((v)/1000) +#define NVML_CUDA_DRIVER_VERSION_MINOR(v) (((v)%1000)/10) + +/** + * Gets name of the process with provided process id + * + * For all products. + * + * Returned process name is cropped to provided length. + * name string is encoded in ANSI. + * + * @param pid The identifier of the process + * @param name Reference in which to return the process name + * @param length The maximum allowed length of the string returned in \a name + * + * @return + * - \ref NVML_SUCCESS if \a name has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a name is NULL or \a length is 0. + * - \ref NVML_ERROR_NOT_FOUND if process doesn't exists + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlSystemGetProcessName(unsigned int pid, char *name, unsigned int length); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlUnitQueries Unit Queries + * This chapter describes that queries that NVML can perform against each unit. For S-class systems only. + * In each case the device is identified with an nvmlUnit_t handle. This handle is obtained by + * calling \ref nvmlUnitGetHandleByIndex(). + * @{ + */ +/***************************************************************************************************/ + + /** + * Retrieves the number of units in the system. + * + * For S-class products. + * + * @param unitCount Reference in which to return the number of units + * + * @return + * - \ref NVML_SUCCESS if \a unitCount has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a unitCount is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlUnitGetCount(unsigned int *unitCount); + +/** + * Acquire the handle for a particular unit, based on its index. + * + * For S-class products. + * + * Valid indices are derived from the \a unitCount returned by \ref nvmlUnitGetCount(). + * For example, if \a unitCount is 2 the valid indices are 0 and 1, corresponding to UNIT 0 and UNIT 1. + * + * The order in which NVML enumerates units has no guarantees of consistency between reboots. + * + * @param index The index of the target unit, >= 0 and < \a unitCount + * @param unit Reference in which to return the unit handle + * + * @return + * - \ref NVML_SUCCESS if \a unit has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a index is invalid or \a unit is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlUnitGetHandleByIndex(unsigned int index, nvmlUnit_t *unit); + +/** + * Retrieves the static information associated with a unit. + * + * For S-class products. + * + * See \ref nvmlUnitInfo_t for details on available unit info. + * + * @param unit The identifier of the target unit + * @param info Reference in which to return the unit information + * + * @return + * - \ref NVML_SUCCESS if \a info has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a unit is invalid or \a info is NULL + */ +nvmlReturn_t DECLDIR nvmlUnitGetUnitInfo(nvmlUnit_t unit, nvmlUnitInfo_t *info); + +/** + * Retrieves the LED state associated with this unit. + * + * For S-class products. + * + * See \ref nvmlLedState_t for details on allowed states. + * + * @param unit The identifier of the target unit + * @param state Reference in which to return the current LED state + * + * @return + * - \ref NVML_SUCCESS if \a state has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a unit is invalid or \a state is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this is not an S-class product + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlUnitSetLedState() + */ +nvmlReturn_t DECLDIR nvmlUnitGetLedState(nvmlUnit_t unit, nvmlLedState_t *state); + +/** + * Retrieves the PSU stats for the unit. + * + * For S-class products. + * + * See \ref nvmlPSUInfo_t for details on available PSU info. + * + * @param unit The identifier of the target unit + * @param psu Reference in which to return the PSU information + * + * @return + * - \ref NVML_SUCCESS if \a psu has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a unit is invalid or \a psu is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this is not an S-class product + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlUnitGetPsuInfo(nvmlUnit_t unit, nvmlPSUInfo_t *psu); + +/** + * Retrieves the temperature readings for the unit, in degrees C. + * + * For S-class products. + * + * Depending on the product, readings may be available for intake (type=0), + * exhaust (type=1) and board (type=2). + * + * @param unit The identifier of the target unit + * @param type The type of reading to take + * @param temp Reference in which to return the intake temperature + * + * @return + * - \ref NVML_SUCCESS if \a temp has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a unit or \a type is invalid or \a temp is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this is not an S-class product + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlUnitGetTemperature(nvmlUnit_t unit, unsigned int type, unsigned int *temp); + +/** + * Retrieves the fan speed readings for the unit. + * + * For S-class products. + * + * See \ref nvmlUnitFanSpeeds_t for details on available fan speed info. + * + * @param unit The identifier of the target unit + * @param fanSpeeds Reference in which to return the fan speed information + * + * @return + * - \ref NVML_SUCCESS if \a fanSpeeds has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a unit is invalid or \a fanSpeeds is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this is not an S-class product + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlUnitGetFanSpeedInfo(nvmlUnit_t unit, nvmlUnitFanSpeeds_t *fanSpeeds); + +/** + * Retrieves the set of GPU devices that are attached to the specified unit. + * + * For S-class products. + * + * The \a deviceCount argument is expected to be set to the size of the input \a devices array. + * + * @param unit The identifier of the target unit + * @param deviceCount Reference in which to provide the \a devices array size, and + * to return the number of attached GPU devices + * @param devices Reference in which to return the references to the attached GPU devices + * + * @return + * - \ref NVML_SUCCESS if \a deviceCount and \a devices have been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a deviceCount indicates that the \a devices array is too small + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a unit is invalid, either of \a deviceCount or \a devices is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlUnitGetDevices(nvmlUnit_t unit, unsigned int *deviceCount, nvmlDevice_t *devices); + +/** + * Retrieves the IDs and firmware versions for any Host Interface Cards (HICs) in the system. + * + * For S-class products. + * + * The \a hwbcCount argument is expected to be set to the size of the input \a hwbcEntries array. + * The HIC must be connected to an S-class system for it to be reported by this function. + * + * @param hwbcCount Size of hwbcEntries array + * @param hwbcEntries Array holding information about hwbc + * + * @return + * - \ref NVML_SUCCESS if \a hwbcCount and \a hwbcEntries have been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if either \a hwbcCount or \a hwbcEntries is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a hwbcCount indicates that the \a hwbcEntries array is too small + */ +nvmlReturn_t DECLDIR nvmlSystemGetHicVersion(unsigned int *hwbcCount, nvmlHwbcEntry_t *hwbcEntries); +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlDeviceQueries Device Queries + * This chapter describes that queries that NVML can perform against each device. + * In each case the device is identified with an nvmlDevice_t handle. This handle is obtained by + * calling one of \ref nvmlDeviceGetHandleByIndex_v2(), \ref nvmlDeviceGetHandleBySerial(), + * \ref nvmlDeviceGetHandleByPciBusId_v2(). or \ref nvmlDeviceGetHandleByUUID(). + * @{ + */ +/***************************************************************************************************/ + + /** + * Retrieves the number of compute devices in the system. A compute device is a single GPU. + * + * For all products. + * + * Note: New nvmlDeviceGetCount_v2 (default in NVML 5.319) returns count of all devices in the system + * even if nvmlDeviceGetHandleByIndex_v2 returns NVML_ERROR_NO_PERMISSION for such device. + * Update your code to handle this error, or use NVML 4.304 or older nvml header file. + * For backward binary compatibility reasons _v1 version of the API is still present in the shared + * library. + * Old _v1 version of nvmlDeviceGetCount doesn't count devices that NVML has no permission to talk to. + * + * @param deviceCount Reference in which to return the number of accessible devices + * + * @return + * - \ref NVML_SUCCESS if \a deviceCount has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a deviceCount is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetCount_v2(unsigned int *deviceCount); + +/** + * Get attributes (engine counts etc.) for the given NVML device handle. + * + * @note This API currently only supports MIG device handles. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device NVML device handle + * @param attributes Device attributes + * + * @return + * - \ref NVML_SUCCESS if \a device attributes were successfully retrieved + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device handle is invalid + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetAttributes_v2(nvmlDevice_t device, nvmlDeviceAttributes_t *attributes); + +/** + * Acquire the handle for a particular device, based on its index. + * + * For all products. + * + * Valid indices are derived from the \a accessibleDevices count returned by + * \ref nvmlDeviceGetCount_v2(). For example, if \a accessibleDevices is 2 the valid indices + * are 0 and 1, corresponding to GPU 0 and GPU 1. + * + * The order in which NVML enumerates devices has no guarantees of consistency between reboots. For that reason it + * is recommended that devices be looked up by their PCI ids or UUID. See + * \ref nvmlDeviceGetHandleByUUID() and \ref nvmlDeviceGetHandleByPciBusId_v2(). + * + * Note: The NVML index may not correlate with other APIs, such as the CUDA device index. + * + * Starting from NVML 5, this API causes NVML to initialize the target GPU + * NVML may initialize additional GPUs if: + * - The target GPU is an SLI slave + * + * Note: New nvmlDeviceGetCount_v2 (default in NVML 5.319) returns count of all devices in the system + * even if nvmlDeviceGetHandleByIndex_v2 returns NVML_ERROR_NO_PERMISSION for such device. + * Update your code to handle this error, or use NVML 4.304 or older nvml header file. + * For backward binary compatibility reasons _v1 version of the API is still present in the shared + * library. + * Old _v1 version of nvmlDeviceGetCount doesn't count devices that NVML has no permission to talk to. + * + * This means that nvmlDeviceGetHandleByIndex_v2 and _v1 can return different devices for the same index. + * If you don't touch macros that map old (_v1) versions to _v2 versions at the top of the file you don't + * need to worry about that. + * + * @param index The index of the target GPU, >= 0 and < \a accessibleDevices + * @param device Reference in which to return the device handle + * + * @return + * - \ref NVML_SUCCESS if \a device has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a index is invalid or \a device is NULL + * - \ref NVML_ERROR_INSUFFICIENT_POWER if any attached devices have improperly attached external power cables + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to talk to this device + * - \ref NVML_ERROR_IRQ_ISSUE if NVIDIA kernel detected an interrupt issue with the attached GPUs + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetIndex + * @see nvmlDeviceGetCount + */ +nvmlReturn_t DECLDIR nvmlDeviceGetHandleByIndex_v2(unsigned int index, nvmlDevice_t *device); + +/** + * Acquire the handle for a particular device, based on its board serial number. + * + * For Fermi &tm; or newer fully supported devices. + * + * This number corresponds to the value printed directly on the board, and to the value returned by + * \ref nvmlDeviceGetSerial(). + * + * @deprecated Since more than one GPU can exist on a single board this function is deprecated in favor + * of \ref nvmlDeviceGetHandleByUUID. + * For dual GPU boards this function will return NVML_ERROR_INVALID_ARGUMENT. + * + * Starting from NVML 5, this API causes NVML to initialize the target GPU + * NVML may initialize additional GPUs as it searches for the target GPU + * + * @param serial The board serial number of the target GPU + * @param device Reference in which to return the device handle + * + * @return + * - \ref NVML_SUCCESS if \a device has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a serial is invalid, \a device is NULL or more than one + * device has the same serial (dual GPU boards) + * - \ref NVML_ERROR_NOT_FOUND if \a serial does not match a valid device on the system + * - \ref NVML_ERROR_INSUFFICIENT_POWER if any attached devices have improperly attached external power cables + * - \ref NVML_ERROR_IRQ_ISSUE if NVIDIA kernel detected an interrupt issue with the attached GPUs + * - \ref NVML_ERROR_GPU_IS_LOST if any GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetSerial + * @see nvmlDeviceGetHandleByUUID + */ +nvmlReturn_t DECLDIR nvmlDeviceGetHandleBySerial(const char *serial, nvmlDevice_t *device); + +/** + * Acquire the handle for a particular device, based on its globally unique immutable UUID associated with each device. + * + * For all products. + * + * @param uuid The UUID of the target GPU or MIG instance + * @param device Reference in which to return the device handle or MIG device handle + * + * Starting from NVML 5, this API causes NVML to initialize the target GPU + * NVML may initialize additional GPUs as it searches for the target GPU + * + * @return + * - \ref NVML_SUCCESS if \a device has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a uuid is invalid or \a device is null + * - \ref NVML_ERROR_NOT_FOUND if \a uuid does not match a valid device on the system + * - \ref NVML_ERROR_INSUFFICIENT_POWER if any attached devices have improperly attached external power cables + * - \ref NVML_ERROR_IRQ_ISSUE if NVIDIA kernel detected an interrupt issue with the attached GPUs + * - \ref NVML_ERROR_GPU_IS_LOST if any GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetUUID + */ +nvmlReturn_t DECLDIR nvmlDeviceGetHandleByUUID(const char *uuid, nvmlDevice_t *device); + +/** + * Acquire the handle for a particular device, based on its PCI bus id. + * + * For all products. + * + * This value corresponds to the nvmlPciInfo_t::busId returned by \ref nvmlDeviceGetPciInfo_v3(). + * + * Starting from NVML 5, this API causes NVML to initialize the target GPU + * NVML may initialize additional GPUs if: + * - The target GPU is an SLI slave + * + * \note NVML 4.304 and older version of nvmlDeviceGetHandleByPciBusId"_v1" returns NVML_ERROR_NOT_FOUND + * instead of NVML_ERROR_NO_PERMISSION. + * + * @param pciBusId The PCI bus id of the target GPU + * @param device Reference in which to return the device handle + * + * @return + * - \ref NVML_SUCCESS if \a device has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a pciBusId is invalid or \a device is NULL + * - \ref NVML_ERROR_NOT_FOUND if \a pciBusId does not match a valid device on the system + * - \ref NVML_ERROR_INSUFFICIENT_POWER if the attached device has improperly attached external power cables + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to talk to this device + * - \ref NVML_ERROR_IRQ_ISSUE if NVIDIA kernel detected an interrupt issue with the attached GPUs + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetHandleByPciBusId_v2(const char *pciBusId, nvmlDevice_t *device); + +/** + * Retrieves the name of this device. + * + * For all products. + * + * The name is an alphanumeric string that denotes a particular product, e.g. Tesla &tm; C2070. It will not + * exceed 96 characters in length (including the NULL terminator). See \ref + * nvmlConstants::NVML_DEVICE_NAME_V2_BUFFER_SIZE. + * + * When used with MIG device handles the API returns MIG device names which can be used to identify devices + * based on their attributes. + * + * @param device The identifier of the target device + * @param name Reference in which to return the product name + * @param length The maximum allowed length of the string returned in \a name + * + * @return + * - \ref NVML_SUCCESS if \a name has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a name is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a length is too small + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetName(nvmlDevice_t device, char *name, unsigned int length); + +/** + * Retrieves the brand of this device. + * + * For all products. + * + * The type is a member of \ref nvmlBrandType_t defined above. + * + * @param device The identifier of the target device + * @param type Reference in which to return the product brand type + * + * @return + * - \ref NVML_SUCCESS if \a name has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a type is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetBrand(nvmlDevice_t device, nvmlBrandType_t *type); + +/** + * Retrieves the NVML index of this device. + * + * For all products. + * + * Valid indices are derived from the \a accessibleDevices count returned by + * \ref nvmlDeviceGetCount_v2(). For example, if \a accessibleDevices is 2 the valid indices + * are 0 and 1, corresponding to GPU 0 and GPU 1. + * + * The order in which NVML enumerates devices has no guarantees of consistency between reboots. For that reason it + * is recommended that devices be looked up by their PCI ids or GPU UUID. See + * \ref nvmlDeviceGetHandleByPciBusId_v2() and \ref nvmlDeviceGetHandleByUUID(). + * + * When used with MIG device handles this API returns indices that can be + * passed to \ref nvmlDeviceGetMigDeviceHandleByIndex to retrieve an identical handle. + * MIG device indices are unique within a device. + * + * Note: The NVML index may not correlate with other APIs, such as the CUDA device index. + * + * @param device The identifier of the target device + * @param index Reference in which to return the NVML index of the device + * + * @return + * - \ref NVML_SUCCESS if \a index has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a index is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetHandleByIndex() + * @see nvmlDeviceGetCount() + */ +nvmlReturn_t DECLDIR nvmlDeviceGetIndex(nvmlDevice_t device, unsigned int *index); + +/** + * Retrieves the globally unique board serial number associated with this device's board. + * + * For all products with an inforom. + * + * The serial number is an alphanumeric string that will not exceed 30 characters (including the NULL terminator). + * This number matches the serial number tag that is physically attached to the board. See \ref + * nvmlConstants::NVML_DEVICE_SERIAL_BUFFER_SIZE. + * + * @param device The identifier of the target device + * @param serial Reference in which to return the board/module serial number + * @param length The maximum allowed length of the string returned in \a serial + * + * @return + * - \ref NVML_SUCCESS if \a serial has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a serial is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a length is too small + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetSerial(nvmlDevice_t device, char *serial, unsigned int length); + + +/***************************************************************************************************/ + +/** @defgroup nvmlAffinity CPU and Memory Affinity + * This chapter describes NVML operations that are associated with CPU and memory + * affinity. + * @{ + */ +/***************************************************************************************************/ + +//! Scope of NUMA node for affinity queries +#define NVML_AFFINITY_SCOPE_NODE 0 +//! Scope of processor socket for affinity queries +#define NVML_AFFINITY_SCOPE_SOCKET 1 + +typedef unsigned int nvmlAffinityScope_t; + +/** + * Retrieves an array of unsigned ints (sized to nodeSetSize) of bitmasks with + * the ideal memory affinity within node or socket for the device. + * For example, if NUMA node 0, 1 are ideal within the socket for the device and nodeSetSize == 1, + * result[0] = 0x3 + * + * \note If requested scope is not applicable to the target topology, the API + * will fall back to reporting the memory affinity for the immediate non-I/O + * ancestor of the device. + * + * For Kepler &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device The identifier of the target device + * @param nodeSetSize The size of the nodeSet array that is safe to access + * @param nodeSet Array reference in which to return a bitmask of NODEs, 64 NODEs per + * unsigned long on 64-bit machines, 32 on 32-bit machines + * @param scope Scope that change the default behavior + * + * @return + * - \ref NVML_SUCCESS if \a NUMA node Affinity has been filled + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, nodeSetSize == 0, nodeSet is NULL or scope is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ + +nvmlReturn_t DECLDIR nvmlDeviceGetMemoryAffinity(nvmlDevice_t device, unsigned int nodeSetSize, unsigned long *nodeSet, nvmlAffinityScope_t scope); + +/** + * Retrieves an array of unsigned ints (sized to cpuSetSize) of bitmasks with the + * ideal CPU affinity within node or socket for the device. + * For example, if processors 0, 1, 32, and 33 are ideal for the device and cpuSetSize == 2, + * result[0] = 0x3, result[1] = 0x3 + * + * \note If requested scope is not applicable to the target topology, the API + * will fall back to reporting the CPU affinity for the immediate non-I/O + * ancestor of the device. + * + * For Kepler &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device The identifier of the target device + * @param cpuSetSize The size of the cpuSet array that is safe to access + * @param cpuSet Array reference in which to return a bitmask of CPUs, 64 CPUs per + * unsigned long on 64-bit machines, 32 on 32-bit machines + * @param scope Scope that change the default behavior + * + * @return + * - \ref NVML_SUCCESS if \a cpuAffinity has been filled + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, cpuSetSize == 0, cpuSet is NULL or sope is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ + +nvmlReturn_t DECLDIR nvmlDeviceGetCpuAffinityWithinScope(nvmlDevice_t device, unsigned int cpuSetSize, unsigned long *cpuSet, nvmlAffinityScope_t scope); + +/** + * Retrieves an array of unsigned ints (sized to cpuSetSize) of bitmasks with the ideal CPU affinity for the device + * For example, if processors 0, 1, 32, and 33 are ideal for the device and cpuSetSize == 2, + * result[0] = 0x3, result[1] = 0x3 + * This is equivalent to calling \ref nvmlDeviceGetCpuAffinityWithinScope with \ref NVML_AFFINITY_SCOPE_NODE. + * + * For Kepler &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device The identifier of the target device + * @param cpuSetSize The size of the cpuSet array that is safe to access + * @param cpuSet Array reference in which to return a bitmask of CPUs, 64 CPUs per + * unsigned long on 64-bit machines, 32 on 32-bit machines + * + * @return + * - \ref NVML_SUCCESS if \a cpuAffinity has been filled + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, cpuSetSize == 0, or cpuSet is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetCpuAffinity(nvmlDevice_t device, unsigned int cpuSetSize, unsigned long *cpuSet); + +/** + * Sets the ideal affinity for the calling thread and device using the guidelines + * given in nvmlDeviceGetCpuAffinity(). Note, this is a change as of version 8.0. + * Older versions set the affinity for a calling process and all children. + * Currently supports up to 1024 processors. + * + * For Kepler &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device The identifier of the target device + * + * @return + * - \ref NVML_SUCCESS if the calling process has been successfully bound + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceSetCpuAffinity(nvmlDevice_t device); + +/** + * Clear all affinity bindings for the calling thread. Note, this is a change as of version + * 8.0 as older versions cleared the affinity for a calling process and all children. + * + * For Kepler &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device The identifier of the target device + * + * @return + * - \ref NVML_SUCCESS if the calling process has been successfully unbound + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceClearCpuAffinity(nvmlDevice_t device); + +/** + * Retrieve the common ancestor for two devices + * For all products. + * Supported on Linux only. + * + * @param device1 The identifier of the first device + * @param device2 The identifier of the second device + * @param pathInfo A \ref nvmlGpuTopologyLevel_t that gives the path type + * + * @return + * - \ref NVML_SUCCESS if \a pathInfo has been set + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device1, or \a device2 is invalid, or \a pathInfo is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device or OS does not support this feature + * - \ref NVML_ERROR_UNKNOWN an error has occurred in underlying topology discovery + */ + +/** @} */ +nvmlReturn_t DECLDIR nvmlDeviceGetTopologyCommonAncestor(nvmlDevice_t device1, nvmlDevice_t device2, nvmlGpuTopologyLevel_t *pathInfo); + +/** + * Retrieve the set of GPUs that are nearest to a given device at a specific interconnectivity level + * For all products. + * Supported on Linux only. + * + * @param device The identifier of the first device + * @param level The \ref nvmlGpuTopologyLevel_t level to search for other GPUs + * @param count When zero, is set to the number of matching GPUs such that \a deviceArray + * can be malloc'd. When non-zero, \a deviceArray will be filled with \a count + * number of device handles. + * @param deviceArray An array of device handles for GPUs found at \a level + * + * @return + * - \ref NVML_SUCCESS if \a deviceArray or \a count (if initially zero) has been set + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a level, or \a count is invalid, or \a deviceArray is NULL with a non-zero \a count + * - \ref NVML_ERROR_NOT_SUPPORTED if the device or OS does not support this feature + * - \ref NVML_ERROR_UNKNOWN an error has occurred in underlying topology discovery + */ +nvmlReturn_t DECLDIR nvmlDeviceGetTopologyNearestGpus(nvmlDevice_t device, nvmlGpuTopologyLevel_t level, unsigned int *count, nvmlDevice_t *deviceArray); + +/** + * Retrieve the set of GPUs that have a CPU affinity with the given CPU number + * For all products. + * Supported on Linux only. + * + * @param cpuNumber The CPU number + * @param count When zero, is set to the number of matching GPUs such that \a deviceArray + * can be malloc'd. When non-zero, \a deviceArray will be filled with \a count + * number of device handles. + * @param deviceArray An array of device handles for GPUs found with affinity to \a cpuNumber + * + * @return + * - \ref NVML_SUCCESS if \a deviceArray or \a count (if initially zero) has been set + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a cpuNumber, or \a count is invalid, or \a deviceArray is NULL with a non-zero \a count + * - \ref NVML_ERROR_NOT_SUPPORTED if the device or OS does not support this feature + * - \ref NVML_ERROR_UNKNOWN an error has occurred in underlying topology discovery + */ +nvmlReturn_t DECLDIR nvmlSystemGetTopologyGpuSet(unsigned int cpuNumber, unsigned int *count, nvmlDevice_t *deviceArray); + +/** + * Retrieve the status for a given p2p capability index between a given pair of GPU + * + * @param device1 The first device + * @param device2 The second device + * @param p2pIndex p2p Capability Index being looked for between \a device1 and \a device2 + * @param p2pStatus Reference in which to return the status of the \a p2pIndex + * between \a device1 and \a device2 + * @return + * - \ref NVML_SUCCESS if \a p2pStatus has been populated + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device1 or \a device2 or \a p2pIndex is invalid or \a p2pStatus is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetP2PStatus(nvmlDevice_t device1, nvmlDevice_t device2, nvmlGpuP2PCapsIndex_t p2pIndex,nvmlGpuP2PStatus_t *p2pStatus); + +/** + * Retrieves the globally unique immutable UUID associated with this device, as a 5 part hexadecimal string, + * that augments the immutable, board serial identifier. + * + * For all products. + * + * The UUID is a globally unique identifier. It is the only available identifier for pre-Fermi-architecture products. + * It does NOT correspond to any identifier printed on the board. It will not exceed 96 characters in length + * (including the NULL terminator). See \ref nvmlConstants::NVML_DEVICE_UUID_V2_BUFFER_SIZE. + * + * When used with MIG device handles the API returns globally unique UUIDs which can be used to identify MIG + * devices across both GPU and MIG devices. UUIDs are immutable for the lifetime of a MIG device. + * + * @param device The identifier of the target device + * @param uuid Reference in which to return the GPU UUID + * @param length The maximum allowed length of the string returned in \a uuid + * + * @return + * - \ref NVML_SUCCESS if \a uuid has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a uuid is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a length is too small + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetUUID(nvmlDevice_t device, char *uuid, unsigned int length); + +/** + * Retrieve the MDEV UUID of a vGPU instance. + * + * The MDEV UUID is a globally unique identifier of the mdev device assigned to the VM, and is returned as a 5-part hexadecimal string, + * not exceeding 80 characters in length (including the NULL terminator). + * MDEV UUID is displayed only on KVM platform. + * See \ref nvmlConstants::NVML_DEVICE_UUID_BUFFER_SIZE. + * + * For Maxwell &tm; or newer fully supported devices. + * + * @param vgpuInstance Identifier of the target vGPU instance + * @param mdevUuid Pointer to caller-supplied buffer to hold MDEV UUID + * @param size Size of buffer in bytes + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_NOT_SUPPORTED on any hypervisor other than KVM + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a mdevUuid is NULL + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a size is too small + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetMdevUUID(nvmlVgpuInstance_t vgpuInstance, char *mdevUuid, unsigned int size); + +/** + * Retrieves minor number for the device. The minor number for the device is such that the Nvidia device node file for + * each GPU will have the form /dev/nvidia[minor number]. + * + * For all products. + * Supported only for Linux + * + * @param device The identifier of the target device + * @param minorNumber Reference in which to return the minor number for the device + * @return + * - \ref NVML_SUCCESS if the minor number is successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a minorNumber is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMinorNumber(nvmlDevice_t device, unsigned int *minorNumber); + +/** + * Retrieves the the device board part number which is programmed into the board's InfoROM + * + * For all products. + * + * @param device Identifier of the target device + * @param partNumber Reference to the buffer to return + * @param length Length of the buffer reference + * + * @return + * - \ref NVML_SUCCESS if \a partNumber has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_NOT_SUPPORTED if the needed VBIOS fields have not been filled + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a serial is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetBoardPartNumber(nvmlDevice_t device, char* partNumber, unsigned int length); + +/** + * Retrieves the version information for the device's infoROM object. + * + * For all products with an inforom. + * + * Fermi and higher parts have non-volatile on-board memory for persisting device info, such as aggregate + * ECC counts. The version of the data structures in this memory may change from time to time. It will not + * exceed 16 characters in length (including the NULL terminator). + * See \ref nvmlConstants::NVML_DEVICE_INFOROM_VERSION_BUFFER_SIZE. + * + * See \ref nvmlInforomObject_t for details on the available infoROM objects. + * + * @param device The identifier of the target device + * @param object The target infoROM object + * @param version Reference in which to return the infoROM version + * @param length The maximum allowed length of the string returned in \a version + * + * @return + * - \ref NVML_SUCCESS if \a version has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a version is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a length is too small + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not have an infoROM + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetInforomImageVersion + */ +nvmlReturn_t DECLDIR nvmlDeviceGetInforomVersion(nvmlDevice_t device, nvmlInforomObject_t object, char *version, unsigned int length); + +/** + * Retrieves the global infoROM image version + * + * For all products with an inforom. + * + * Image version just like VBIOS version uniquely describes the exact version of the infoROM flashed on the board + * in contrast to infoROM object version which is only an indicator of supported features. + * Version string will not exceed 16 characters in length (including the NULL terminator). + * See \ref nvmlConstants::NVML_DEVICE_INFOROM_VERSION_BUFFER_SIZE. + * + * @param device The identifier of the target device + * @param version Reference in which to return the infoROM image version + * @param length The maximum allowed length of the string returned in \a version + * + * @return + * - \ref NVML_SUCCESS if \a version has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a version is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a length is too small + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not have an infoROM + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetInforomVersion + */ +nvmlReturn_t DECLDIR nvmlDeviceGetInforomImageVersion(nvmlDevice_t device, char *version, unsigned int length); + +/** + * Retrieves the checksum of the configuration stored in the device's infoROM. + * + * For all products with an inforom. + * + * Can be used to make sure that two GPUs have the exact same configuration. + * Current checksum takes into account configuration stored in PWR and ECC infoROM objects. + * Checksum can change between driver releases or when user changes configuration (e.g. disable/enable ECC) + * + * @param device The identifier of the target device + * @param checksum Reference in which to return the infoROM configuration checksum + * + * @return + * - \ref NVML_SUCCESS if \a checksum has been set + * - \ref NVML_ERROR_CORRUPTED_INFOROM if the device's checksum couldn't be retrieved due to infoROM corruption + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a checksum is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetInforomConfigurationChecksum(nvmlDevice_t device, unsigned int *checksum); + +/** + * Reads the infoROM from the flash and verifies the checksums. + * + * For all products with an inforom. + * + * @param device The identifier of the target device + * + * @return + * - \ref NVML_SUCCESS if infoROM is not corrupted + * - \ref NVML_ERROR_CORRUPTED_INFOROM if the device's infoROM is corrupted + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceValidateInforom(nvmlDevice_t device); + +/** + * Retrieves the display mode for the device. + * + * For all products. + * + * This method indicates whether a physical display (e.g. monitor) is currently connected to + * any of the device's connectors. + * + * See \ref nvmlEnableState_t for details on allowed modes. + * + * @param device The identifier of the target device + * @param display Reference in which to return the display mode + * + * @return + * - \ref NVML_SUCCESS if \a display has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a display is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetDisplayMode(nvmlDevice_t device, nvmlEnableState_t *display); + +/** + * Retrieves the display active state for the device. + * + * For all products. + * + * This method indicates whether a display is initialized on the device. + * For example whether X Server is attached to this device and has allocated memory for the screen. + * + * Display can be active even when no monitor is physically attached. + * + * See \ref nvmlEnableState_t for details on allowed modes. + * + * @param device The identifier of the target device + * @param isActive Reference in which to return the display active state + * + * @return + * - \ref NVML_SUCCESS if \a isActive has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a isActive is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetDisplayActive(nvmlDevice_t device, nvmlEnableState_t *isActive); + +/** + * Retrieves the persistence mode associated with this device. + * + * For all products. + * For Linux only. + * + * When driver persistence mode is enabled the driver software state is not torn down when the last + * client disconnects. By default this feature is disabled. + * + * See \ref nvmlEnableState_t for details on allowed modes. + * + * @param device The identifier of the target device + * @param mode Reference in which to return the current driver persistence mode + * + * @return + * - \ref NVML_SUCCESS if \a mode has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a mode is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceSetPersistenceMode() + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPersistenceMode(nvmlDevice_t device, nvmlEnableState_t *mode); + +/** + * Retrieves the PCI attributes of this device. + * + * For all products. + * + * See \ref nvmlPciInfo_t for details on the available PCI info. + * + * @param device The identifier of the target device + * @param pci Reference in which to return the PCI info + * + * @return + * - \ref NVML_SUCCESS if \a pci has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a pci is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPciInfo_v3(nvmlDevice_t device, nvmlPciInfo_t *pci); + +/** + * Retrieves the maximum PCIe link generation possible with this device and system + * + * I.E. for a generation 2 PCIe device attached to a generation 1 PCIe bus the max link generation this function will + * report is generation 1. + * + * For Fermi &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param maxLinkGen Reference in which to return the max PCIe link generation + * + * @return + * - \ref NVML_SUCCESS if \a maxLinkGen has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a maxLinkGen is null + * - \ref NVML_ERROR_NOT_SUPPORTED if PCIe link information is not available + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMaxPcieLinkGeneration(nvmlDevice_t device, unsigned int *maxLinkGen); + +/** + * Retrieves the maximum PCIe link generation supported by this device + * + * For Fermi &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param maxLinkGenDevice Reference in which to return the max PCIe link generation + * + * @return + * - \ref NVML_SUCCESS if \a maxLinkGenDevice has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a maxLinkGenDevice is null + * - \ref NVML_ERROR_NOT_SUPPORTED if PCIe link information is not available + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGpuMaxPcieLinkGeneration(nvmlDevice_t device, unsigned int *maxLinkGenDevice); + +/** + * Retrieves the maximum PCIe link width possible with this device and system + * + * I.E. for a device with a 16x PCIe bus width attached to a 8x PCIe system bus this function will report + * a max link width of 8. + * + * For Fermi &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param maxLinkWidth Reference in which to return the max PCIe link generation + * + * @return + * - \ref NVML_SUCCESS if \a maxLinkWidth has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a maxLinkWidth is null + * - \ref NVML_ERROR_NOT_SUPPORTED if PCIe link information is not available + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMaxPcieLinkWidth(nvmlDevice_t device, unsigned int *maxLinkWidth); + +/** + * Retrieves the current PCIe link generation + * + * For Fermi &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param currLinkGen Reference in which to return the current PCIe link generation + * + * @return + * - \ref NVML_SUCCESS if \a currLinkGen has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a currLinkGen is null + * - \ref NVML_ERROR_NOT_SUPPORTED if PCIe link information is not available + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetCurrPcieLinkGeneration(nvmlDevice_t device, unsigned int *currLinkGen); + +/** + * Retrieves the current PCIe link width + * + * For Fermi &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param currLinkWidth Reference in which to return the current PCIe link generation + * + * @return + * - \ref NVML_SUCCESS if \a currLinkWidth has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a currLinkWidth is null + * - \ref NVML_ERROR_NOT_SUPPORTED if PCIe link information is not available + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetCurrPcieLinkWidth(nvmlDevice_t device, unsigned int *currLinkWidth); + +/** + * Retrieve PCIe utilization information. + * This function is querying a byte counter over a 20ms interval and thus is the + * PCIe throughput over that interval. + * + * For Maxwell &tm; or newer fully supported devices. + * + * This method is not supported in virtual machines running virtual GPU (vGPU). + * + * @param device The identifier of the target device + * @param counter The specific counter that should be queried \ref nvmlPcieUtilCounter_t + * @param value Reference in which to return throughput in KB/s + * + * @return + * - \ref NVML_SUCCESS if \a value has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device or \a counter is invalid, or \a value is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPcieThroughput(nvmlDevice_t device, nvmlPcieUtilCounter_t counter, unsigned int *value); + +/** + * Retrieve the PCIe replay counter. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param value Reference in which to return the counter's value + * + * @return + * - \ref NVML_SUCCESS if \a value has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a value is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPcieReplayCounter(nvmlDevice_t device, unsigned int *value); + +/** + * Retrieves the current clock speeds for the device. + * + * For Fermi &tm; or newer fully supported devices. + * + * See \ref nvmlClockType_t for details on available clock information. + * + * @param device The identifier of the target device + * @param type Identify which clock domain to query + * @param clock Reference in which to return the clock speed in MHz + * + * @return + * - \ref NVML_SUCCESS if \a clock has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a clock is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device cannot report the specified clock + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetClockInfo(nvmlDevice_t device, nvmlClockType_t type, unsigned int *clock); + +/** + * Retrieves the maximum clock speeds for the device. + * + * For Fermi &tm; or newer fully supported devices. + * + * See \ref nvmlClockType_t for details on available clock information. + * + * \note On GPUs from Fermi family current P0 clocks (reported by \ref nvmlDeviceGetClockInfo) can differ from max clocks + * by few MHz. + * + * @param device The identifier of the target device + * @param type Identify which clock domain to query + * @param clock Reference in which to return the clock speed in MHz + * + * @return + * - \ref NVML_SUCCESS if \a clock has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a clock is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device cannot report the specified clock + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMaxClockInfo(nvmlDevice_t device, nvmlClockType_t type, unsigned int *clock); + +/** + * Retrieves the current setting of a clock that applications will use unless an overspec situation occurs. + * Can be changed using \ref nvmlDeviceSetApplicationsClocks. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param clockType Identify which clock domain to query + * @param clockMHz Reference in which to return the clock in MHz + * + * @return + * - \ref NVML_SUCCESS if \a clockMHz has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a clockMHz is NULL or \a clockType is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetApplicationsClock(nvmlDevice_t device, nvmlClockType_t clockType, unsigned int *clockMHz); + +/** + * Retrieves the default applications clock that GPU boots with or + * defaults to after \ref nvmlDeviceResetApplicationsClocks call. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param clockType Identify which clock domain to query + * @param clockMHz Reference in which to return the default clock in MHz + * + * @return + * - \ref NVML_SUCCESS if \a clockMHz has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a clockMHz is NULL or \a clockType is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * \see nvmlDeviceGetApplicationsClock + */ +nvmlReturn_t DECLDIR nvmlDeviceGetDefaultApplicationsClock(nvmlDevice_t device, nvmlClockType_t clockType, unsigned int *clockMHz); + +/** + * Resets the application clock to the default value + * + * This is the applications clock that will be used after system reboot or driver reload. + * Default value is constant, but the current value an be changed using \ref nvmlDeviceSetApplicationsClocks. + * + * On Pascal and newer hardware, if clocks were previously locked with \ref nvmlDeviceSetApplicationsClocks, + * this call will unlock clocks. This returns clocks their default behavior ofautomatically boosting above + * base clocks as thermal limits allow. + * + * @see nvmlDeviceGetApplicationsClock + * @see nvmlDeviceSetApplicationsClocks + * + * For Fermi &tm; or newer non-GeForce fully supported devices and Maxwell or newer GeForce devices. + * + * @param device The identifier of the target device + * + * @return + * - \ref NVML_SUCCESS if new settings were successfully set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceResetApplicationsClocks(nvmlDevice_t device); + +/** + * Retrieves the clock speed for the clock specified by the clock type and clock ID. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param clockType Identify which clock domain to query + * @param clockId Identify which clock in the domain to query + * @param clockMHz Reference in which to return the clock in MHz + * + * @return + * - \ref NVML_SUCCESS if \a clockMHz has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a clockMHz is NULL or \a clockType is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetClock(nvmlDevice_t device, nvmlClockType_t clockType, nvmlClockId_t clockId, unsigned int *clockMHz); + +/** + * Retrieves the customer defined maximum boost clock speed specified by the given clock type. + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param clockType Identify which clock domain to query + * @param clockMHz Reference in which to return the clock in MHz + * + * @return + * - \ref NVML_SUCCESS if \a clockMHz has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a clockMHz is NULL or \a clockType is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device or the \a clockType on this device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMaxCustomerBoostClock(nvmlDevice_t device, nvmlClockType_t clockType, unsigned int *clockMHz); + +/** + * Retrieves the list of possible memory clocks that can be used as an argument for \ref nvmlDeviceSetApplicationsClocks. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param count Reference in which to provide the \a clocksMHz array size, and + * to return the number of elements + * @param clocksMHz Reference in which to return the clock in MHz + * + * @return + * - \ref NVML_SUCCESS if \a count and \a clocksMHz have been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a count is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a count is too small (\a count is set to the number of + * required elements) + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceSetApplicationsClocks + * @see nvmlDeviceGetSupportedGraphicsClocks + */ +nvmlReturn_t DECLDIR nvmlDeviceGetSupportedMemoryClocks(nvmlDevice_t device, unsigned int *count, unsigned int *clocksMHz); + +/** + * Retrieves the list of possible graphics clocks that can be used as an argument for \ref nvmlDeviceSetApplicationsClocks. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param memoryClockMHz Memory clock for which to return possible graphics clocks + * @param count Reference in which to provide the \a clocksMHz array size, and + * to return the number of elements + * @param clocksMHz Reference in which to return the clocks in MHz + * + * @return + * - \ref NVML_SUCCESS if \a count and \a clocksMHz have been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_NOT_FOUND if the specified \a memoryClockMHz is not a supported frequency + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a clock is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a count is too small + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceSetApplicationsClocks + * @see nvmlDeviceGetSupportedMemoryClocks + */ +nvmlReturn_t DECLDIR nvmlDeviceGetSupportedGraphicsClocks(nvmlDevice_t device, unsigned int memoryClockMHz, unsigned int *count, unsigned int *clocksMHz); + +/** + * Retrieve the current state of Auto Boosted clocks on a device and store it in \a isEnabled + * + * For Kepler &tm; or newer fully supported devices. + * + * Auto Boosted clocks are enabled by default on some hardware, allowing the GPU to run at higher clock rates + * to maximize performance as thermal limits allow. + * + * On Pascal and newer hardware, Auto Aoosted clocks are controlled through application clocks. + * Use \ref nvmlDeviceSetApplicationsClocks and \ref nvmlDeviceResetApplicationsClocks to control Auto Boost + * behavior. + * + * @param device The identifier of the target device + * @param isEnabled Where to store the current state of Auto Boosted clocks of the target device + * @param defaultIsEnabled Where to store the default Auto Boosted clocks behavior of the target device that the device will + * revert to when no applications are using the GPU + * + * @return + * - \ref NVML_SUCCESS If \a isEnabled has been been set with the Auto Boosted clocks state of \a device + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a isEnabled is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support Auto Boosted clocks + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + */ +nvmlReturn_t DECLDIR nvmlDeviceGetAutoBoostedClocksEnabled(nvmlDevice_t device, nvmlEnableState_t *isEnabled, nvmlEnableState_t *defaultIsEnabled); + +/** + * Try to set the current state of Auto Boosted clocks on a device. + * + * For Kepler &tm; or newer fully supported devices. + * + * Auto Boosted clocks are enabled by default on some hardware, allowing the GPU to run at higher clock rates + * to maximize performance as thermal limits allow. Auto Boosted clocks should be disabled if fixed clock + * rates are desired. + * + * Non-root users may use this API by default but can be restricted by root from using this API by calling + * \ref nvmlDeviceSetAPIRestriction with apiType=NVML_RESTRICTED_API_SET_AUTO_BOOSTED_CLOCKS. + * Note: Persistence Mode is required to modify current Auto Boost settings, therefore, it must be enabled. + * + * On Pascal and newer hardware, Auto Boosted clocks are controlled through application clocks. + * Use \ref nvmlDeviceSetApplicationsClocks and \ref nvmlDeviceResetApplicationsClocks to control Auto Boost + * behavior. + * + * @param device The identifier of the target device + * @param enabled What state to try to set Auto Boosted clocks of the target device to + * + * @return + * - \ref NVML_SUCCESS If the Auto Boosted clocks were successfully set to the state specified by \a enabled + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support Auto Boosted clocks + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + */ +nvmlReturn_t DECLDIR nvmlDeviceSetAutoBoostedClocksEnabled(nvmlDevice_t device, nvmlEnableState_t enabled); + +/** + * Try to set the default state of Auto Boosted clocks on a device. This is the default state that Auto Boosted clocks will + * return to when no compute running processes (e.g. CUDA application which have an active context) are running + * + * For Kepler &tm; or newer non-GeForce fully supported devices and Maxwell or newer GeForce devices. + * Requires root/admin permissions. + * + * Auto Boosted clocks are enabled by default on some hardware, allowing the GPU to run at higher clock rates + * to maximize performance as thermal limits allow. Auto Boosted clocks should be disabled if fixed clock + * rates are desired. + * + * On Pascal and newer hardware, Auto Boosted clocks are controlled through application clocks. + * Use \ref nvmlDeviceSetApplicationsClocks and \ref nvmlDeviceResetApplicationsClocks to control Auto Boost + * behavior. + * + * @param device The identifier of the target device + * @param enabled What state to try to set default Auto Boosted clocks of the target device to + * @param flags Flags that change the default behavior. Currently Unused. + * + * @return + * - \ref NVML_SUCCESS If the Auto Boosted clock's default state was successfully set to the state specified by \a enabled + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_NO_PERMISSION If the calling user does not have permission to change Auto Boosted clock's default state. + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support Auto Boosted clocks + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + */ +nvmlReturn_t DECLDIR nvmlDeviceSetDefaultAutoBoostedClocksEnabled(nvmlDevice_t device, nvmlEnableState_t enabled, unsigned int flags); + + +/** + * Retrieves the intended operating speed of the device's fan. + * + * Note: The reported speed is the intended fan speed. If the fan is physically blocked and unable to spin, the + * output will not match the actual fan speed. + * + * For all discrete products with dedicated fans. + * + * The fan speed is expressed as a percentage of the product's maximum noise tolerance fan speed. + * This value may exceed 100% in certain cases. + * + * @param device The identifier of the target device + * @param speed Reference in which to return the fan speed percentage + * + * @return + * - \ref NVML_SUCCESS if \a speed has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a speed is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not have a fan + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetFanSpeed(nvmlDevice_t device, unsigned int *speed); + + +/** + * Retrieves the intended operating speed of the device's specified fan. + * + * Note: The reported speed is the intended fan speed. If the fan is physically blocked and unable to spin, the + * output will not match the actual fan speed. + * + * For all discrete products with dedicated fans. + * + * The fan speed is expressed as a percentage of the product's maximum noise tolerance fan speed. + * This value may exceed 100% in certain cases. + * + * @param device The identifier of the target device + * @param fan The index of the target fan, zero indexed. + * @param speed Reference in which to return the fan speed percentage + * + * @return + * - \ref NVML_SUCCESS if \a speed has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a fan is not an acceptable index, or \a speed is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not have a fan or is newer than Maxwell + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetFanSpeed_v2(nvmlDevice_t device, unsigned int fan, unsigned int * speed); + +/** + * Retrieves the intended target speed of the device's specified fan. + * + * Normally, the driver dynamically adjusts the fan based on + * the needs of the GPU. But when user set fan speed using nvmlDeviceSetFanSpeed_v2, + * the driver will attempt to make the fan achieve the setting in + * nvmlDeviceSetFanSpeed_v2. The actual current speed of the fan + * is reported in nvmlDeviceGetFanSpeed_v2. + * + * For all discrete products with dedicated fans. + * + * The fan speed is expressed as a percentage of the product's maximum noise tolerance fan speed. + * This value may exceed 100% in certain cases. + * + * @param device The identifier of the target device + * @param fan The index of the target fan, zero indexed. + * @param targetSpeed Reference in which to return the fan speed percentage + * + * @return + * - \ref NVML_SUCCESS if \a speed has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a fan is not an acceptable index, or \a speed is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not have a fan or is newer than Maxwell + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetTargetFanSpeed(nvmlDevice_t device, unsigned int fan, unsigned int *targetSpeed); + +/** + * Sets the speed of the fan control policy to default. + * + * For all cuda-capable discrete products with fans + * + * @param device The identifier of the target device + * @param fan The index of the fan, starting at zero + * + * return + * NVML_SUCCESS if speed has been adjusted + * NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * NVML_ERROR_INVALID_ARGUMENT if device is invalid + * NVML_ERROR_NOT_SUPPORTED if the device does not support this + * (doesn't have fans) + * NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceSetDefaultFanSpeed_v2(nvmlDevice_t device, unsigned int fan); + +/** + * Retrieves the min and max fan speed that user can set for the GPU fan. + * + * For all cuda-capable discrete products with fans + * + * @param device The identifier of the target device + * @param minSpeed The minimum speed allowed to set + * @param maxSpeed The maximum speed allowed to set + * + * return + * NVML_SUCCESS if speed has been adjusted + * NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * NVML_ERROR_INVALID_ARGUMENT if device is invalid + * NVML_ERROR_NOT_SUPPORTED if the device does not support this + * (doesn't have fans) + * NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMinMaxFanSpeed(nvmlDevice_t device, unsigned int * minSpeed, + unsigned int * maxSpeed); + +/** + * Gets current fan control policy. + * + * For Maxwell &tm; or newer fully supported devices. + * + * For all cuda-capable discrete products with fans + * + * device The identifier of the target \a device + * policy Reference in which to return the fan control \a policy + * + * return + * NVML_SUCCESS if \a policy has been populated + * NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a policy is null or the \a fan given doesn't reference + * a fan that exists. + * NVML_ERROR_NOT_SUPPORTED if the \a device is older than Maxwell + * NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetFanControlPolicy_v2(nvmlDevice_t device, unsigned int fan, + nvmlFanControlPolicy_t *policy); + +/** + * Sets current fan control policy. + * + * For Maxwell &tm; or newer fully supported devices. + * + * Requires privileged user. + * + * For all cuda-capable discrete products with fans + * + * device The identifier of the target \a device + * policy The fan control \a policy to set + * + * return + * NVML_SUCCESS if \a policy has been set + * NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a policy is null or the \a fan given doesn't reference + * a fan that exists. + * NVML_ERROR_NOT_SUPPORTED if the \a device is older than Maxwell + * NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceSetFanControlPolicy(nvmlDevice_t device, unsigned int fan, + nvmlFanControlPolicy_t policy); + +/** + * Retrieves the number of fans on the device. + * + * For all discrete products with dedicated fans. + * + * @param device The identifier of the target device + * @param numFans The number of fans + * + * @return + * - \ref NVML_SUCCESS if \a fan number query was successful + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a numFans is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not have a fan + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetNumFans(nvmlDevice_t device, unsigned int *numFans); + +/** + * Retrieves the current temperature readings for the device, in degrees C. + * + * For all products. + * + * See \ref nvmlTemperatureSensors_t for details on available temperature sensors. + * + * @param device The identifier of the target device + * @param sensorType Flag that indicates which sensor reading to retrieve + * @param temp Reference in which to return the temperature reading + * + * @return + * - \ref NVML_SUCCESS if \a temp has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a sensorType is invalid or \a temp is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not have the specified sensor + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetTemperature(nvmlDevice_t device, nvmlTemperatureSensors_t sensorType, unsigned int *temp); + +/** + * Retrieves the temperature threshold for the GPU with the specified threshold type in degrees C. + * + * For Kepler &tm; or newer fully supported devices. + * + * See \ref nvmlTemperatureThresholds_t for details on available temperature thresholds. + * + * @param device The identifier of the target device + * @param thresholdType The type of threshold value queried + * @param temp Reference in which to return the temperature reading + * @return + * - \ref NVML_SUCCESS if \a temp has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a thresholdType is invalid or \a temp is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not have a temperature sensor or is unsupported + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetTemperatureThreshold(nvmlDevice_t device, nvmlTemperatureThresholds_t thresholdType, unsigned int *temp); + +/** + * Sets the temperature threshold for the GPU with the specified threshold type in degrees C. + * + * For Maxwell &tm; or newer fully supported devices. + * + * See \ref nvmlTemperatureThresholds_t for details on available temperature thresholds. + * + * @param device The identifier of the target device + * @param thresholdType The type of threshold value to be set + * @param temp Reference which hold the value to be set + * @return + * - \ref NVML_SUCCESS if \a temp has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a thresholdType is invalid or \a temp is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not have a temperature sensor or is unsupported + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceSetTemperatureThreshold(nvmlDevice_t device, nvmlTemperatureThresholds_t thresholdType, int *temp); + +/** + * Used to execute a list of thermal system instructions. + * + * @param device The identifier of the target device + * @param sensorIndex The index of the thermal sensor + * @param pThermalSettings Reference in which to return the thermal sensor information + * + * @return + * - \ref NVML_SUCCESS if \a pThermalSettings has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a pThermalSettings is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetThermalSettings(nvmlDevice_t device, unsigned int sensorIndex, nvmlGpuThermalSettings_t *pThermalSettings); + +/** + * Retrieves the current performance state for the device. + * + * For Fermi &tm; or newer fully supported devices. + * + * See \ref nvmlPstates_t for details on allowed performance states. + * + * @param device The identifier of the target device + * @param pState Reference in which to return the performance state reading + * + * @return + * - \ref NVML_SUCCESS if \a pState has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a pState is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPerformanceState(nvmlDevice_t device, nvmlPstates_t *pState); + +/** + * Retrieves current clocks throttling reasons. + * + * For all fully supported products. + * + * \note More than one bit can be enabled at the same time. Multiple reasons can be affecting clocks at once. + * + * @param device The identifier of the target device + * @param clocksThrottleReasons Reference in which to return bitmask of active clocks throttle + * reasons + * + * @return + * - \ref NVML_SUCCESS if \a clocksThrottleReasons has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a clocksThrottleReasons is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlClocksThrottleReasons + * @see nvmlDeviceGetSupportedClocksThrottleReasons + */ +nvmlReturn_t DECLDIR nvmlDeviceGetCurrentClocksThrottleReasons(nvmlDevice_t device, unsigned long long *clocksThrottleReasons); + +/** + * Retrieves bitmask of supported clocks throttle reasons that can be returned by + * \ref nvmlDeviceGetCurrentClocksThrottleReasons + * + * For all fully supported products. + * + * This method is not supported in virtual machines running virtual GPU (vGPU). + * + * @param device The identifier of the target device + * @param supportedClocksThrottleReasons Reference in which to return bitmask of supported + * clocks throttle reasons + * + * @return + * - \ref NVML_SUCCESS if \a supportedClocksThrottleReasons has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a supportedClocksThrottleReasons is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlClocksThrottleReasons + * @see nvmlDeviceGetCurrentClocksThrottleReasons + */ +nvmlReturn_t DECLDIR nvmlDeviceGetSupportedClocksThrottleReasons(nvmlDevice_t device, unsigned long long *supportedClocksThrottleReasons); + +/** + * Deprecated: Use \ref nvmlDeviceGetPerformanceState. This function exposes an incorrect generalization. + * + * Retrieve the current performance state for the device. + * + * For Fermi &tm; or newer fully supported devices. + * + * See \ref nvmlPstates_t for details on allowed performance states. + * + * @param device The identifier of the target device + * @param pState Reference in which to return the performance state reading + * + * @return + * - \ref NVML_SUCCESS if \a pState has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a pState is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPowerState(nvmlDevice_t device, nvmlPstates_t *pState); + +/** + * This API has been deprecated. + * + * Retrieves the power management mode associated with this device. + * + * For products from the Fermi family. + * - Requires \a NVML_INFOROM_POWER version 3.0 or higher. + * + * For from the Kepler or newer families. + * - Does not require \a NVML_INFOROM_POWER object. + * + * This flag indicates whether any power management algorithm is currently active on the device. An + * enabled state does not necessarily mean the device is being actively throttled -- only that + * that the driver will do so if the appropriate conditions are met. + * + * See \ref nvmlEnableState_t for details on allowed modes. + * + * @param device The identifier of the target device + * @param mode Reference in which to return the current power management mode + * + * @return + * - \ref NVML_SUCCESS if \a mode has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a mode is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPowerManagementMode(nvmlDevice_t device, nvmlEnableState_t *mode); + +/** + * Retrieves the power management limit associated with this device. + * + * For Fermi &tm; or newer fully supported devices. + * + * The power limit defines the upper boundary for the card's power draw. If + * the card's total power draw reaches this limit the power management algorithm kicks in. + * + * This reading is only available if power management mode is supported. + * See \ref nvmlDeviceGetPowerManagementMode. + * + * @param device The identifier of the target device + * @param limit Reference in which to return the power management limit in milliwatts + * + * @return + * - \ref NVML_SUCCESS if \a limit has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a limit is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPowerManagementLimit(nvmlDevice_t device, unsigned int *limit); + +/** + * Retrieves information about possible values of power management limits on this device. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param minLimit Reference in which to return the minimum power management limit in milliwatts + * @param maxLimit Reference in which to return the maximum power management limit in milliwatts + * + * @return + * - \ref NVML_SUCCESS if \a minLimit and \a maxLimit have been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a minLimit or \a maxLimit is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceSetPowerManagementLimit + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPowerManagementLimitConstraints(nvmlDevice_t device, unsigned int *minLimit, unsigned int *maxLimit); + +/** + * Retrieves default power management limit on this device, in milliwatts. + * Default power management limit is a power management limit that the device boots with. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param defaultLimit Reference in which to return the default power management limit in milliwatts + * + * @return + * - \ref NVML_SUCCESS if \a defaultLimit has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a defaultLimit is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPowerManagementDefaultLimit(nvmlDevice_t device, unsigned int *defaultLimit); + +/** + * Retrieves power usage for this GPU in milliwatts and its associated circuitry (e.g. memory) + * + * For Fermi &tm; or newer fully supported devices. + * + * On Fermi and Kepler GPUs the reading is accurate to within +/- 5% of current power draw. + * + * It is only available if power management mode is supported. See \ref nvmlDeviceGetPowerManagementMode. + * + * @param device The identifier of the target device + * @param power Reference in which to return the power usage information + * + * @return + * - \ref NVML_SUCCESS if \a power has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a power is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support power readings + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPowerUsage(nvmlDevice_t device, unsigned int *power); + +/** + * Retrieves total energy consumption for this GPU in millijoules (mJ) since the driver was last reloaded + * + * For Volta &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param energy Reference in which to return the energy consumption information + * + * @return + * - \ref NVML_SUCCESS if \a energy has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a energy is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support energy readings + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetTotalEnergyConsumption(nvmlDevice_t device, unsigned long long *energy); + +/** + * Get the effective power limit that the driver enforces after taking into account all limiters + * + * Note: This can be different from the \ref nvmlDeviceGetPowerManagementLimit if other limits are set elsewhere + * This includes the out of band power limit interface + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The device to communicate with + * @param limit Reference in which to return the power management limit in milliwatts + * + * @return + * - \ref NVML_SUCCESS if \a limit has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a limit is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetEnforcedPowerLimit(nvmlDevice_t device, unsigned int *limit); + +/** + * Retrieves the current GOM and pending GOM (the one that GPU will switch to after reboot). + * + * For GK110 M-class and X-class Tesla &tm; products from the Kepler family. + * Modes \ref NVML_GOM_LOW_DP and \ref NVML_GOM_ALL_ON are supported on fully supported GeForce products. + * Not supported on Quadro ® and Tesla &tm; C-class products. + * + * @param device The identifier of the target device + * @param current Reference in which to return the current GOM + * @param pending Reference in which to return the pending GOM + * + * @return + * - \ref NVML_SUCCESS if \a mode has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a current or \a pending is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlGpuOperationMode_t + * @see nvmlDeviceSetGpuOperationMode + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGpuOperationMode(nvmlDevice_t device, nvmlGpuOperationMode_t *current, nvmlGpuOperationMode_t *pending); + +/** + * Retrieves the amount of used, free, reserved and total memory available on the device, in bytes. + * The reserved amount is supported on version 2 only. + * + * For all products. + * + * Enabling ECC reduces the amount of total available memory, due to the extra required parity bits. + * Under WDDM most device memory is allocated and managed on startup by Windows. + * + * Under Linux and Windows TCC, the reported amount of used memory is equal to the sum of memory allocated + * by all active channels on the device. + * + * See \ref nvmlMemory_v2_t for details on available memory info. + * + * @note In MIG mode, if device handle is provided, the API returns aggregate + * information, only if the caller has appropriate privileges. Per-instance + * information can be queried by using specific MIG device handles. + * + * @note nvmlDeviceGetMemoryInfo_v2 adds additional memory information. + * + * @param device The identifier of the target device + * @param memory Reference in which to return the memory information + * + * @return + * - \ref NVML_SUCCESS if \a memory has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a memory is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMemoryInfo(nvmlDevice_t device, nvmlMemory_t *memory); +nvmlReturn_t DECLDIR nvmlDeviceGetMemoryInfo_v2(nvmlDevice_t device, nvmlMemory_v2_t *memory); + +/** + * Retrieves the current compute mode for the device. + * + * For all products. + * + * See \ref nvmlComputeMode_t for details on allowed compute modes. + * + * @param device The identifier of the target device + * @param mode Reference in which to return the current compute mode + * + * @return + * - \ref NVML_SUCCESS if \a mode has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a mode is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceSetComputeMode() + */ +nvmlReturn_t DECLDIR nvmlDeviceGetComputeMode(nvmlDevice_t device, nvmlComputeMode_t *mode); + +/** + * Retrieves the CUDA compute capability of the device. + * + * For all products. + * + * Returns the major and minor compute capability version numbers of the + * device. The major and minor versions are equivalent to the + * CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MINOR and + * CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MAJOR attributes that would be + * returned by CUDA's cuDeviceGetAttribute(). + * + * @param device The identifier of the target device + * @param major Reference in which to return the major CUDA compute capability + * @param minor Reference in which to return the minor CUDA compute capability + * + * @return + * - \ref NVML_SUCCESS if \a major and \a minor have been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a major or \a minor are NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetCudaComputeCapability(nvmlDevice_t device, int *major, int *minor); + +/** + * Retrieves the current and pending ECC modes for the device. + * + * For Fermi &tm; or newer fully supported devices. + * Only applicable to devices with ECC. + * Requires \a NVML_INFOROM_ECC version 1.0 or higher. + * + * Changing ECC modes requires a reboot. The "pending" ECC mode refers to the target mode following + * the next reboot. + * + * See \ref nvmlEnableState_t for details on allowed modes. + * + * @param device The identifier of the target device + * @param current Reference in which to return the current ECC mode + * @param pending Reference in which to return the pending ECC mode + * + * @return + * - \ref NVML_SUCCESS if \a current and \a pending have been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or either \a current or \a pending is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceSetEccMode() + */ +nvmlReturn_t DECLDIR nvmlDeviceGetEccMode(nvmlDevice_t device, nvmlEnableState_t *current, nvmlEnableState_t *pending); + +/** + * Retrieves the default ECC modes for the device. + * + * For Fermi &tm; or newer fully supported devices. + * Only applicable to devices with ECC. + * Requires \a NVML_INFOROM_ECC version 1.0 or higher. + * + * See \ref nvmlEnableState_t for details on allowed modes. + * + * @param device The identifier of the target device + * @param defaultMode Reference in which to return the default ECC mode + * + * @return + * - \ref NVML_SUCCESS if \a current and \a pending have been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a default is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceSetEccMode() + */ +nvmlReturn_t DECLDIR nvmlDeviceGetDefaultEccMode(nvmlDevice_t device, nvmlEnableState_t *defaultMode); + +/** + * Retrieves the device boardId from 0-N. + * Devices with the same boardId indicate GPUs connected to the same PLX. Use in conjunction with + * \ref nvmlDeviceGetMultiGpuBoard() to decide if they are on the same board as well. + * The boardId returned is a unique ID for the current configuration. Uniqueness and ordering across + * reboots and system configurations is not guaranteed (i.e. if a Tesla K40c returns 0x100 and + * the two GPUs on a Tesla K10 in the same system returns 0x200 it is not guaranteed they will + * always return those values but they will always be different from each other). + * + * + * For Fermi &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param boardId Reference in which to return the device's board ID + * + * @return + * - \ref NVML_SUCCESS if \a boardId has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a boardId is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetBoardId(nvmlDevice_t device, unsigned int *boardId); + +/** + * Retrieves whether the device is on a Multi-GPU Board + * Devices that are on multi-GPU boards will set \a multiGpuBool to a non-zero value. + * + * For Fermi &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param multiGpuBool Reference in which to return a zero or non-zero value + * to indicate whether the device is on a multi GPU board + * + * @return + * - \ref NVML_SUCCESS if \a multiGpuBool has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a multiGpuBool is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMultiGpuBoard(nvmlDevice_t device, unsigned int *multiGpuBool); + +/** + * Retrieves the total ECC error counts for the device. + * + * For Fermi &tm; or newer fully supported devices. + * Only applicable to devices with ECC. + * Requires \a NVML_INFOROM_ECC version 1.0 or higher. + * Requires ECC Mode to be enabled. + * + * The total error count is the sum of errors across each of the separate memory systems, i.e. the total set of + * errors across the entire device. + * + * See \ref nvmlMemoryErrorType_t for a description of available error types.\n + * See \ref nvmlEccCounterType_t for a description of available counter types. + * + * @param device The identifier of the target device + * @param errorType Flag that specifies the type of the errors. + * @param counterType Flag that specifies the counter-type of the errors. + * @param eccCounts Reference in which to return the specified ECC errors + * + * @return + * - \ref NVML_SUCCESS if \a eccCounts has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a errorType or \a counterType is invalid, or \a eccCounts is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceClearEccErrorCounts() + */ +nvmlReturn_t DECLDIR nvmlDeviceGetTotalEccErrors(nvmlDevice_t device, nvmlMemoryErrorType_t errorType, nvmlEccCounterType_t counterType, unsigned long long *eccCounts); + +/** + * Retrieves the detailed ECC error counts for the device. + * + * @deprecated This API supports only a fixed set of ECC error locations + * On different GPU architectures different locations are supported + * See \ref nvmlDeviceGetMemoryErrorCounter + * + * For Fermi &tm; or newer fully supported devices. + * Only applicable to devices with ECC. + * Requires \a NVML_INFOROM_ECC version 2.0 or higher to report aggregate location-based ECC counts. + * Requires \a NVML_INFOROM_ECC version 1.0 or higher to report all other ECC counts. + * Requires ECC Mode to be enabled. + * + * Detailed errors provide separate ECC counts for specific parts of the memory system. + * + * Reports zero for unsupported ECC error counters when a subset of ECC error counters are supported. + * + * See \ref nvmlMemoryErrorType_t for a description of available bit types.\n + * See \ref nvmlEccCounterType_t for a description of available counter types.\n + * See \ref nvmlEccErrorCounts_t for a description of provided detailed ECC counts. + * + * @param device The identifier of the target device + * @param errorType Flag that specifies the type of the errors. + * @param counterType Flag that specifies the counter-type of the errors. + * @param eccCounts Reference in which to return the specified ECC errors + * + * @return + * - \ref NVML_SUCCESS if \a eccCounts has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a errorType or \a counterType is invalid, or \a eccCounts is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceClearEccErrorCounts() + */ +nvmlReturn_t DECLDIR nvmlDeviceGetDetailedEccErrors(nvmlDevice_t device, nvmlMemoryErrorType_t errorType, nvmlEccCounterType_t counterType, nvmlEccErrorCounts_t *eccCounts); + +/** + * Retrieves the requested memory error counter for the device. + * + * For Fermi &tm; or newer fully supported devices. + * Requires \a NVML_INFOROM_ECC version 2.0 or higher to report aggregate location-based memory error counts. + * Requires \a NVML_INFOROM_ECC version 1.0 or higher to report all other memory error counts. + * + * Only applicable to devices with ECC. + * + * Requires ECC Mode to be enabled. + * + * @note On MIG-enabled GPUs, per instance information can be queried using specific + * MIG device handles. Per instance information is currently only supported for + * non-DRAM uncorrectable volatile errors. Querying volatile errors using device + * handles is currently not supported. + * + * See \ref nvmlMemoryErrorType_t for a description of available memory error types.\n + * See \ref nvmlEccCounterType_t for a description of available counter types.\n + * See \ref nvmlMemoryLocation_t for a description of available counter locations.\n + * + * @param device The identifier of the target device + * @param errorType Flag that specifies the type of error. + * @param counterType Flag that specifies the counter-type of the errors. + * @param locationType Specifies the location of the counter. + * @param count Reference in which to return the ECC counter + * + * @return + * - \ref NVML_SUCCESS if \a count has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a bitTyp,e \a counterType or \a locationType is + * invalid, or \a count is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support ECC error reporting in the specified memory + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMemoryErrorCounter(nvmlDevice_t device, nvmlMemoryErrorType_t errorType, + nvmlEccCounterType_t counterType, + nvmlMemoryLocation_t locationType, unsigned long long *count); + +/** + * Retrieves the current utilization rates for the device's major subsystems. + * + * For Fermi &tm; or newer fully supported devices. + * + * See \ref nvmlUtilization_t for details on available utilization rates. + * + * \note During driver initialization when ECC is enabled one can see high GPU and Memory Utilization readings. + * This is caused by ECC Memory Scrubbing mechanism that is performed during driver initialization. + * + * @note On MIG-enabled GPUs, querying device utilization rates is not currently supported. + * + * @param device The identifier of the target device + * @param utilization Reference in which to return the utilization information + * + * @return + * - \ref NVML_SUCCESS if \a utilization has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a utilization is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetUtilizationRates(nvmlDevice_t device, nvmlUtilization_t *utilization); + +/** + * Retrieves the current utilization and sampling size in microseconds for the Encoder + * + * For Kepler &tm; or newer fully supported devices. + * + * @note On MIG-enabled GPUs, querying encoder utilization is not currently supported. + * + * @param device The identifier of the target device + * @param utilization Reference to an unsigned int for encoder utilization info + * @param samplingPeriodUs Reference to an unsigned int for the sampling period in US + * + * @return + * - \ref NVML_SUCCESS if \a utilization has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a utilization is NULL, or \a samplingPeriodUs is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetEncoderUtilization(nvmlDevice_t device, unsigned int *utilization, unsigned int *samplingPeriodUs); + +/** + * Retrieves the current capacity of the device's encoder, as a percentage of maximum encoder capacity with valid values in the range 0-100. + * + * For Maxwell &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param encoderQueryType Type of encoder to query + * @param encoderCapacity Reference to an unsigned int for the encoder capacity + * + * @return + * - \ref NVML_SUCCESS if \a encoderCapacity is fetched + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a encoderCapacity is NULL, or \a device or \a encoderQueryType + * are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if device does not support the encoder specified in \a encodeQueryType + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetEncoderCapacity (nvmlDevice_t device, nvmlEncoderType_t encoderQueryType, unsigned int *encoderCapacity); + +/** + * Retrieves the current encoder statistics for a given device. + * + * For Maxwell &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param sessionCount Reference to an unsigned int for count of active encoder sessions + * @param averageFps Reference to an unsigned int for trailing average FPS of all active sessions + * @param averageLatency Reference to an unsigned int for encode latency in microseconds + * + * @return + * - \ref NVML_SUCCESS if \a sessionCount, \a averageFps and \a averageLatency is fetched + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a sessionCount, or \a device or \a averageFps, + * or \a averageLatency is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetEncoderStats (nvmlDevice_t device, unsigned int *sessionCount, + unsigned int *averageFps, unsigned int *averageLatency); + +/** + * Retrieves information about active encoder sessions on a target device. + * + * An array of active encoder sessions is returned in the caller-supplied buffer pointed at by \a sessionInfos. The + * array elememt count is passed in \a sessionCount, and \a sessionCount is used to return the number of sessions + * written to the buffer. + * + * If the supplied buffer is not large enough to accomodate the active session array, the function returns + * NVML_ERROR_INSUFFICIENT_SIZE, with the element count of nvmlEncoderSessionInfo_t array required in \a sessionCount. + * To query the number of active encoder sessions, call this function with *sessionCount = 0. The code will return + * NVML_SUCCESS with number of active encoder sessions updated in *sessionCount. + * + * For Maxwell &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param sessionCount Reference to caller supplied array size, and returns the number of sessions. + * @param sessionInfos Reference in which to return the session information + * + * @return + * - \ref NVML_SUCCESS if \a sessionInfos is fetched + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a sessionCount is too small, array element count is returned in \a sessionCount + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a sessionCount is NULL. + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by \a device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetEncoderSessions(nvmlDevice_t device, unsigned int *sessionCount, nvmlEncoderSessionInfo_t *sessionInfos); + +/** + * Retrieves the current utilization and sampling size in microseconds for the Decoder + * + * For Kepler &tm; or newer fully supported devices. + * + * @note On MIG-enabled GPUs, querying decoder utilization is not currently supported. + * + * @param device The identifier of the target device + * @param utilization Reference to an unsigned int for decoder utilization info + * @param samplingPeriodUs Reference to an unsigned int for the sampling period in US + * + * @return + * - \ref NVML_SUCCESS if \a utilization has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a utilization is NULL, or \a samplingPeriodUs is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetDecoderUtilization(nvmlDevice_t device, unsigned int *utilization, unsigned int *samplingPeriodUs); + +/** +* Retrieves the active frame buffer capture sessions statistics for a given device. +* +* For Maxwell &tm; or newer fully supported devices. +* +* @param device The identifier of the target device +* @param fbcStats Reference to nvmlFBCStats_t structure contianing NvFBC stats +* +* @return +* - \ref NVML_SUCCESS if \a fbcStats is fetched +* - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized +* - \ref NVML_ERROR_INVALID_ARGUMENT if \a fbcStats is NULL +* - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible +* - \ref NVML_ERROR_UNKNOWN on any unexpected error +*/ +nvmlReturn_t DECLDIR nvmlDeviceGetFBCStats(nvmlDevice_t device, nvmlFBCStats_t *fbcStats); + +/** +* Retrieves information about active frame buffer capture sessions on a target device. +* +* An array of active FBC sessions is returned in the caller-supplied buffer pointed at by \a sessionInfo. The +* array element count is passed in \a sessionCount, and \a sessionCount is used to return the number of sessions +* written to the buffer. +* +* If the supplied buffer is not large enough to accomodate the active session array, the function returns +* NVML_ERROR_INSUFFICIENT_SIZE, with the element count of nvmlFBCSessionInfo_t array required in \a sessionCount. +* To query the number of active FBC sessions, call this function with *sessionCount = 0. The code will return +* NVML_SUCCESS with number of active FBC sessions updated in *sessionCount. +* +* For Maxwell &tm; or newer fully supported devices. +* +* @note hResolution, vResolution, averageFPS and averageLatency data for a FBC session returned in \a sessionInfo may +* be zero if there are no new frames captured since the session started. +* +* @param device The identifier of the target device +* @param sessionCount Reference to caller supplied array size, and returns the number of sessions. +* @param sessionInfo Reference in which to return the session information +* +* @return +* - \ref NVML_SUCCESS if \a sessionInfo is fetched +* - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized +* - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a sessionCount is too small, array element count is returned in \a sessionCount +* - \ref NVML_ERROR_INVALID_ARGUMENT if \a sessionCount is NULL. +* - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible +* - \ref NVML_ERROR_UNKNOWN on any unexpected error +*/ +nvmlReturn_t DECLDIR nvmlDeviceGetFBCSessions(nvmlDevice_t device, unsigned int *sessionCount, nvmlFBCSessionInfo_t *sessionInfo); + +/** + * Retrieves the current and pending driver model for the device. + * + * For Fermi &tm; or newer fully supported devices. + * For windows only. + * + * On Windows platforms the device driver can run in either WDDM or WDM (TCC) mode. If a display is attached + * to the device it must run in WDDM mode. TCC mode is preferred if a display is not attached. + * + * See \ref nvmlDriverModel_t for details on available driver models. + * + * @param device The identifier of the target device + * @param current Reference in which to return the current driver model + * @param pending Reference in which to return the pending driver model + * + * @return + * - \ref NVML_SUCCESS if either \a current and/or \a pending have been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or both \a current and \a pending are NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the platform is not windows + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceSetDriverModel() + */ +nvmlReturn_t DECLDIR nvmlDeviceGetDriverModel(nvmlDevice_t device, nvmlDriverModel_t *current, nvmlDriverModel_t *pending); + +/** + * Get VBIOS version of the device. + * + * For all products. + * + * The VBIOS version may change from time to time. It will not exceed 32 characters in length + * (including the NULL terminator). See \ref nvmlConstants::NVML_DEVICE_VBIOS_VERSION_BUFFER_SIZE. + * + * @param device The identifier of the target device + * @param version Reference to which to return the VBIOS version + * @param length The maximum allowed length of the string returned in \a version + * + * @return + * - \ref NVML_SUCCESS if \a version has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a version is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a length is too small + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetVbiosVersion(nvmlDevice_t device, char *version, unsigned int length); + +/** + * Get Bridge Chip Information for all the bridge chips on the board. + * + * For all fully supported products. + * Only applicable to multi-GPU products. + * + * @param device The identifier of the target device + * @param bridgeHierarchy Reference to the returned bridge chip Hierarchy + * + * @return + * - \ref NVML_SUCCESS if bridge chip exists + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a bridgeInfo is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if bridge chip not supported on the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + */ +nvmlReturn_t DECLDIR nvmlDeviceGetBridgeChipInfo(nvmlDevice_t device, nvmlBridgeChipHierarchy_t *bridgeHierarchy); + +/** + * Get information about processes with a compute context on a device + * + * For Fermi &tm; or newer fully supported devices. + * + * This function returns information only about compute running processes (e.g. CUDA application which have + * active context). Any graphics applications (e.g. using OpenGL, DirectX) won't be listed by this function. + * + * To query the current number of running compute processes, call this function with *infoCount = 0. The + * return code will be NVML_ERROR_INSUFFICIENT_SIZE, or NVML_SUCCESS if none are running. For this call + * \a infos is allowed to be NULL. + * + * The usedGpuMemory field returned is all of the memory used by the application. + * + * Keep in mind that information returned by this call is dynamic and the number of elements might change in + * time. Allocate more space for \a infos table in case new compute processes are spawned. + * + * @note In MIG mode, if device handle is provided, the API returns aggregate information, only if + * the caller has appropriate privileges. Per-instance information can be queried by using + * specific MIG device handles. + * Querying per-instance information using MIG device handles is not supported if the device is in vGPU Host virtualization mode. + * + * @param device The device handle or MIG device handle + * @param infoCount Reference in which to provide the \a infos array size, and + * to return the number of returned elements + * @param infos Reference in which to return the process information + * + * @return + * - \ref NVML_SUCCESS if \a infoCount and \a infos have been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a infoCount indicates that the \a infos array is too small + * \a infoCount will contain minimal amount of space necessary for + * the call to complete + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, either of \a infoCount or \a infos is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by \a device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see \ref nvmlSystemGetProcessName + */ +nvmlReturn_t DECLDIR nvmlDeviceGetComputeRunningProcesses_v3(nvmlDevice_t device, unsigned int *infoCount, nvmlProcessInfo_t *infos); + +/** + * Get information about processes with a graphics context on a device + * + * For Kepler &tm; or newer fully supported devices. + * + * This function returns information only about graphics based processes + * (eg. applications using OpenGL, DirectX) + * + * To query the current number of running graphics processes, call this function with *infoCount = 0. The + * return code will be NVML_ERROR_INSUFFICIENT_SIZE, or NVML_SUCCESS if none are running. For this call + * \a infos is allowed to be NULL. + * + * The usedGpuMemory field returned is all of the memory used by the application. + * + * Keep in mind that information returned by this call is dynamic and the number of elements might change in + * time. Allocate more space for \a infos table in case new graphics processes are spawned. + * + * @note In MIG mode, if device handle is provided, the API returns aggregate information, only if + * the caller has appropriate privileges. Per-instance information can be queried by using + * specific MIG device handles. + * Querying per-instance information using MIG device handles is not supported if the device is in vGPU Host virtualization mode. + * + * @param device The device handle or MIG device handle + * @param infoCount Reference in which to provide the \a infos array size, and + * to return the number of returned elements + * @param infos Reference in which to return the process information + * + * @return + * - \ref NVML_SUCCESS if \a infoCount and \a infos have been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a infoCount indicates that the \a infos array is too small + * \a infoCount will contain minimal amount of space necessary for + * the call to complete + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, either of \a infoCount or \a infos is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by \a device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see \ref nvmlSystemGetProcessName + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGraphicsRunningProcesses_v3(nvmlDevice_t device, unsigned int *infoCount, nvmlProcessInfo_t *infos); + +/** + * Get information about processes with a MPS compute context on a device + * + * For Volta &tm; or newer fully supported devices. + * + * This function returns information only about compute running processes (e.g. CUDA application which have + * active context) utilizing MPS. Any graphics applications (e.g. using OpenGL, DirectX) won't be listed by + * this function. + * + * To query the current number of running compute processes, call this function with *infoCount = 0. The + * return code will be NVML_ERROR_INSUFFICIENT_SIZE, or NVML_SUCCESS if none are running. For this call + * \a infos is allowed to be NULL. + * + * The usedGpuMemory field returned is all of the memory used by the application. + * + * Keep in mind that information returned by this call is dynamic and the number of elements might change in + * time. Allocate more space for \a infos table in case new compute processes are spawned. + * + * @note In MIG mode, if device handle is provided, the API returns aggregate information, only if + * the caller has appropriate privileges. Per-instance information can be queried by using + * specific MIG device handles. + * Querying per-instance information using MIG device handles is not supported if the device is in vGPU Host virtualization mode. + * + * @param device The device handle or MIG device handle + * @param infoCount Reference in which to provide the \a infos array size, and + * to return the number of returned elements + * @param infos Reference in which to return the process information + * + * @return + * - \ref NVML_SUCCESS if \a infoCount and \a infos have been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a infoCount indicates that the \a infos array is too small + * \a infoCount will contain minimal amount of space necessary for + * the call to complete + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, either of \a infoCount or \a infos is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by \a device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see \ref nvmlSystemGetProcessName + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMPSComputeRunningProcesses_v3(nvmlDevice_t device, unsigned int *infoCount, nvmlProcessInfo_t *infos); + +/** + * Check if the GPU devices are on the same physical board. + * + * For all fully supported products. + * + * @param device1 The first GPU device + * @param device2 The second GPU device + * @param onSameBoard Reference in which to return the status. + * Non-zero indicates that the GPUs are on the same board. + * + * @return + * - \ref NVML_SUCCESS if \a onSameBoard has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a dev1 or \a dev2 are invalid or \a onSameBoard is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this check is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the either GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceOnSameBoard(nvmlDevice_t device1, nvmlDevice_t device2, int *onSameBoard); + +/** + * Retrieves the root/admin permissions on the target API. See \a nvmlRestrictedAPI_t for the list of supported APIs. + * If an API is restricted only root users can call that API. See \a nvmlDeviceSetAPIRestriction to change current permissions. + * + * For all fully supported products. + * + * @param device The identifier of the target device + * @param apiType Target API type for this operation + * @param isRestricted Reference in which to return the current restriction + * NVML_FEATURE_ENABLED indicates that the API is root-only + * NVML_FEATURE_DISABLED indicates that the API is accessible to all users + * + * @return + * - \ref NVML_SUCCESS if \a isRestricted has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a apiType incorrect or \a isRestricted is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device or the device does not support + * the feature that is being queried (E.G. Enabling/disabling Auto Boosted clocks is + * not supported by the device) + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlRestrictedAPI_t + */ +nvmlReturn_t DECLDIR nvmlDeviceGetAPIRestriction(nvmlDevice_t device, nvmlRestrictedAPI_t apiType, nvmlEnableState_t *isRestricted); + +/** + * Gets recent samples for the GPU. + * + * For Kepler &tm; or newer fully supported devices. + * + * Based on type, this method can be used to fetch the power, utilization or clock samples maintained in the buffer by + * the driver. + * + * Power, Utilization and Clock samples are returned as type "unsigned int" for the union nvmlValue_t. + * + * To get the size of samples that user needs to allocate, the method is invoked with samples set to NULL. + * The returned samplesCount will provide the number of samples that can be queried. The user needs to + * allocate the buffer with size as samplesCount * sizeof(nvmlSample_t). + * + * lastSeenTimeStamp represents CPU timestamp in microseconds. Set it to 0 to fetch all the samples maintained by the + * underlying buffer. Set lastSeenTimeStamp to one of the timeStamps retrieved from the date of the previous query + * to get more recent samples. + * + * This method fetches the number of entries which can be accommodated in the provided samples array, and the + * reference samplesCount is updated to indicate how many samples were actually retrieved. The advantage of using this + * method for samples in contrast to polling via existing methods is to get get higher frequency data at lower polling cost. + * + * @note On MIG-enabled GPUs, querying the following sample types, NVML_GPU_UTILIZATION_SAMPLES, NVML_MEMORY_UTILIZATION_SAMPLES + * NVML_ENC_UTILIZATION_SAMPLES and NVML_DEC_UTILIZATION_SAMPLES, is not currently supported. + * + * @param device The identifier for the target device + * @param type Type of sampling event + * @param lastSeenTimeStamp Return only samples with timestamp greater than lastSeenTimeStamp. + * @param sampleValType Output parameter to represent the type of sample value as described in nvmlSampleVal_t + * @param sampleCount Reference to provide the number of elements which can be queried in samples array + * @param samples Reference in which samples are returned + + * @return + * - \ref NVML_SUCCESS if samples are successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a samplesCount is NULL or + * reference to \a sampleCount is 0 for non null \a samples + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_NOT_FOUND if sample entries are not found + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetSamples(nvmlDevice_t device, nvmlSamplingType_t type, unsigned long long lastSeenTimeStamp, + nvmlValueType_t *sampleValType, unsigned int *sampleCount, nvmlSample_t *samples); + +/** + * Gets Total, Available and Used size of BAR1 memory. + * + * BAR1 is used to map the FB (device memory) so that it can be directly accessed by the CPU or by 3rd party + * devices (peer-to-peer on the PCIE bus). + * + * @note In MIG mode, if device handle is provided, the API returns aggregate + * information, only if the caller has appropriate privileges. Per-instance + * information can be queried by using specific MIG device handles. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param bar1Memory Reference in which BAR1 memory + * information is returned. + * + * @return + * - \ref NVML_SUCCESS if BAR1 memory is successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a bar1Memory is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + */ +nvmlReturn_t DECLDIR nvmlDeviceGetBAR1MemoryInfo(nvmlDevice_t device, nvmlBAR1Memory_t *bar1Memory); + +/** + * Gets the duration of time during which the device was throttled (lower than requested clocks) due to power + * or thermal constraints. + * + * The method is important to users who are tying to understand if their GPUs throttle at any point during their applications. The + * difference in violation times at two different reference times gives the indication of GPU throttling event. + * + * Violation for thermal capping is not supported at this time. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param perfPolicyType Represents Performance policy which can trigger GPU throttling + * @param violTime Reference to which violation time related information is returned + * + * + * @return + * - \ref NVML_SUCCESS if violation time is successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a perfPolicyType is invalid, or \a violTime is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * + */ +nvmlReturn_t DECLDIR nvmlDeviceGetViolationStatus(nvmlDevice_t device, nvmlPerfPolicyType_t perfPolicyType, nvmlViolationTime_t *violTime); + +/** + * Gets the device's interrupt number + * + * @param device The identifier of the target device + * @param irqNum The interrupt number associated with the specified device + * + * @return + * - \ref NVML_SUCCESS if irq number is successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a irqNum is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * + */ +nvmlReturn_t DECLDIR nvmlDeviceGetIrqNum(nvmlDevice_t device, unsigned int *irqNum); + +/** + * Gets the device's core count + * + * @param device The identifier of the target device + * @param numCores The number of cores for the specified device + * + * @return + * - \ref NVML_SUCCESS if Gpu core count is successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a numCores is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * + */ +nvmlReturn_t DECLDIR nvmlDeviceGetNumGpuCores(nvmlDevice_t device, unsigned int *numCores); + +/** + * Gets the devices power source + * + * @param device The identifier of the target device + * @param powerSource The power source of the device + * + * @return + * - \ref NVML_SUCCESS if the current power source was successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a powerSource is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPowerSource(nvmlDevice_t device, nvmlPowerSource_t *powerSource); + +/** + * Gets the device's memory bus width + * + * @param device The identifier of the target device + * @param busWidth The devices's memory bus width + * + * @return + * - \ref NVML_SUCCESS if the memory bus width is successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a busWidth is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMemoryBusWidth(nvmlDevice_t device, unsigned int *busWidth); + +/** + * Gets the device's PCIE Max Link speed in MBPS + * + * @param device The identifier of the target device + * @param maxSpeed The devices's PCIE Max Link speed in MBPS + * + * @return + * - \ref NVML_SUCCESS if Pcie Max Link Speed is successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a maxSpeed is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPcieLinkMaxSpeed(nvmlDevice_t device, unsigned int *maxSpeed); + +/** + * Gets the device's PCIe Link speed in Mbps + * + * @param device The identifier of the target device + * @param pcieSpeed The devices's PCIe Max Link speed in Mbps + * + * @return + * - \ref NVML_SUCCESS if \a pcieSpeed has been retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a pcieSpeed is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support PCIe speed getting + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPcieSpeed(nvmlDevice_t device, unsigned int *pcieSpeed); + +/** + * Gets the device's Adaptive Clock status + * + * @param device The identifier of the target device + * @param adaptiveClockStatus The current adaptive clocking status + * + * @return + * - \ref NVML_SUCCESS if the current adaptive clocking status is successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a adaptiveClockStatus is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * + */ +nvmlReturn_t DECLDIR nvmlDeviceGetAdaptiveClockInfoStatus(nvmlDevice_t device, unsigned int *adaptiveClockStatus); + +/** + * @} + */ + +/** @addtogroup nvmlAccountingStats + * @{ + */ + +/** + * Queries the state of per process accounting mode. + * + * For Kepler &tm; or newer fully supported devices. + * + * See \ref nvmlDeviceGetAccountingStats for more details. + * See \ref nvmlDeviceSetAccountingMode + * + * @param device The identifier of the target device + * @param mode Reference in which to return the current accounting mode + * + * @return + * - \ref NVML_SUCCESS if the mode has been successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a mode are NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetAccountingMode(nvmlDevice_t device, nvmlEnableState_t *mode); + +/** + * Queries process's accounting stats. + * + * For Kepler &tm; or newer fully supported devices. + * + * Accounting stats capture GPU utilization and other statistics across the lifetime of a process. + * Accounting stats can be queried during life time of the process and after its termination. + * The time field in \ref nvmlAccountingStats_t is reported as 0 during the lifetime of the process and + * updated to actual running time after its termination. + * Accounting stats are kept in a circular buffer, newly created processes overwrite information about old + * processes. + * + * See \ref nvmlAccountingStats_t for description of each returned metric. + * List of processes that can be queried can be retrieved from \ref nvmlDeviceGetAccountingPids. + * + * @note Accounting Mode needs to be on. See \ref nvmlDeviceGetAccountingMode. + * @note Only compute and graphics applications stats can be queried. Monitoring applications stats can't be + * queried since they don't contribute to GPU utilization. + * @note In case of pid collision stats of only the latest process (that terminated last) will be reported + * + * @warning On Kepler devices per process statistics are accurate only if there's one process running on a GPU. + * + * @param device The identifier of the target device + * @param pid Process Id of the target process to query stats for + * @param stats Reference in which to return the process's accounting stats + * + * @return + * - \ref NVML_SUCCESS if stats have been successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a stats are NULL + * - \ref NVML_ERROR_NOT_FOUND if process stats were not found + * - \ref NVML_ERROR_NOT_SUPPORTED if \a device doesn't support this feature or accounting mode is disabled + * or on vGPU host. + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetAccountingBufferSize + */ +nvmlReturn_t DECLDIR nvmlDeviceGetAccountingStats(nvmlDevice_t device, unsigned int pid, nvmlAccountingStats_t *stats); + +/** + * Queries list of processes that can be queried for accounting stats. The list of processes returned + * can be in running or terminated state. + * + * For Kepler &tm; or newer fully supported devices. + * + * To just query the number of processes ready to be queried, call this function with *count = 0 and + * pids=NULL. The return code will be NVML_ERROR_INSUFFICIENT_SIZE, or NVML_SUCCESS if list is empty. + * + * For more details see \ref nvmlDeviceGetAccountingStats. + * + * @note In case of PID collision some processes might not be accessible before the circular buffer is full. + * + * @param device The identifier of the target device + * @param count Reference in which to provide the \a pids array size, and + * to return the number of elements ready to be queried + * @param pids Reference in which to return list of process ids + * + * @return + * - \ref NVML_SUCCESS if pids were successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a count is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if \a device doesn't support this feature or accounting mode is disabled + * or on vGPU host. + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a count is too small (\a count is set to + * expected value) + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetAccountingBufferSize + */ +nvmlReturn_t DECLDIR nvmlDeviceGetAccountingPids(nvmlDevice_t device, unsigned int *count, unsigned int *pids); + +/** + * Returns the number of processes that the circular buffer with accounting pids can hold. + * + * For Kepler &tm; or newer fully supported devices. + * + * This is the maximum number of processes that accounting information will be stored for before information + * about oldest processes will get overwritten by information about new processes. + * + * @param device The identifier of the target device + * @param bufferSize Reference in which to provide the size (in number of elements) + * of the circular buffer for accounting stats. + * + * @return + * - \ref NVML_SUCCESS if buffer size was successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a bufferSize is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature or accounting mode is disabled + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetAccountingStats + * @see nvmlDeviceGetAccountingPids + */ +nvmlReturn_t DECLDIR nvmlDeviceGetAccountingBufferSize(nvmlDevice_t device, unsigned int *bufferSize); + +/** @} */ + +/** @addtogroup nvmlDeviceQueries + * @{ + */ + +/** + * Returns the list of retired pages by source, including pages that are pending retirement + * The address information provided from this API is the hardware address of the page that was retired. Note + * that this does not match the virtual address used in CUDA, but will match the address information in XID 63 + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param cause Filter page addresses by cause of retirement + * @param pageCount Reference in which to provide the \a addresses buffer size, and + * to return the number of retired pages that match \a cause + * Set to 0 to query the size without allocating an \a addresses buffer + * @param addresses Buffer to write the page addresses into + * + * @return + * - \ref NVML_SUCCESS if \a pageCount was populated and \a addresses was filled + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a pageCount indicates the buffer is not large enough to store all the + * matching page addresses. \a pageCount is set to the needed size. + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a pageCount is NULL, \a cause is invalid, or + * \a addresses is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetRetiredPages(nvmlDevice_t device, nvmlPageRetirementCause_t cause, + unsigned int *pageCount, unsigned long long *addresses); + +/** + * Returns the list of retired pages by source, including pages that are pending retirement + * The address information provided from this API is the hardware address of the page that was retired. Note + * that this does not match the virtual address used in CUDA, but will match the address information in XID 63 + * + * \note nvmlDeviceGetRetiredPages_v2 adds an additional timestamps paramter to return the time of each page's + * retirement. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param cause Filter page addresses by cause of retirement + * @param pageCount Reference in which to provide the \a addresses buffer size, and + * to return the number of retired pages that match \a cause + * Set to 0 to query the size without allocating an \a addresses buffer + * @param addresses Buffer to write the page addresses into + * @param timestamps Buffer to write the timestamps of page retirement, additional for _v2 + * + * @return + * - \ref NVML_SUCCESS if \a pageCount was populated and \a addresses was filled + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a pageCount indicates the buffer is not large enough to store all the + * matching page addresses. \a pageCount is set to the needed size. + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a pageCount is NULL, \a cause is invalid, or + * \a addresses is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetRetiredPages_v2(nvmlDevice_t device, nvmlPageRetirementCause_t cause, + unsigned int *pageCount, unsigned long long *addresses, unsigned long long *timestamps); + +/** + * Check if any pages are pending retirement and need a reboot to fully retire. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param isPending Reference in which to return the pending status + * + * @return + * - \ref NVML_SUCCESS if \a isPending was populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a isPending is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetRetiredPagesPendingStatus(nvmlDevice_t device, nvmlEnableState_t *isPending); + +/** + * Get number of remapped rows. The number of rows reported will be based on + * the cause of the remapping. isPending indicates whether or not there are + * pending remappings. A reset will be required to actually remap the row. + * failureOccurred will be set if a row remapping ever failed in the past. A + * pending remapping won't affect future work on the GPU since + * error-containment and dynamic page blacklisting will take care of that. + * + * @note On MIG-enabled GPUs with active instances, querying the number of + * remapped rows is not supported + * + * For Ampere &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param corrRows Reference for number of rows remapped due to correctable errors + * @param uncRows Reference for number of rows remapped due to uncorrectable errors + * @param isPending Reference for whether or not remappings are pending + * @param failureOccurred Reference that is set when a remapping has failed in the past + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a corrRows, \a uncRows, \a isPending or \a failureOccurred is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If MIG is enabled or if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN Unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetRemappedRows(nvmlDevice_t device, unsigned int *corrRows, unsigned int *uncRows, + unsigned int *isPending, unsigned int *failureOccurred); + +/** + * Get the row remapper histogram. Returns the remap availability for each bank + * on the GPU. + * + * @param device Device handle + * @param values Histogram values + * + * @return + * - \ref NVML_SUCCESS On success + * - \ref NVML_ERROR_UNKNOWN On any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetRowRemapperHistogram(nvmlDevice_t device, nvmlRowRemapperHistogramValues_t *values); + +/** + * Get architecture for device + * + * @param device The identifier of the target device + * @param arch Reference where architecture is returned, if call successful. + * Set to NVML_DEVICE_ARCH_* upon success + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a device or \a arch (output refererence) are invalid + */ +nvmlReturn_t DECLDIR nvmlDeviceGetArchitecture(nvmlDevice_t device, nvmlDeviceArchitecture_t *arch); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlUnitCommands Unit Commands + * This chapter describes NVML operations that change the state of the unit. For S-class products. + * Each of these requires root/admin access. Non-admin users will see an NVML_ERROR_NO_PERMISSION + * error code when invoking any of these methods. + * @{ + */ +/***************************************************************************************************/ + +/** + * Set the LED state for the unit. The LED can be either green (0) or amber (1). + * + * For S-class products. + * Requires root/admin permissions. + * + * This operation takes effect immediately. + * + * + * Current S-Class products don't provide unique LEDs for each unit. As such, both front + * and back LEDs will be toggled in unison regardless of which unit is specified with this command. + * + * See \ref nvmlLedColor_t for available colors. + * + * @param unit The identifier of the target unit + * @param color The target LED color + * + * @return + * - \ref NVML_SUCCESS if the LED color has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a unit or \a color is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if this is not an S-class product + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlUnitGetLedState() + */ +nvmlReturn_t DECLDIR nvmlUnitSetLedState(nvmlUnit_t unit, nvmlLedColor_t color); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlDeviceCommands Device Commands + * This chapter describes NVML operations that change the state of the device. + * Each of these requires root/admin access. Non-admin users will see an NVML_ERROR_NO_PERMISSION + * error code when invoking any of these methods. + * @{ + */ +/***************************************************************************************************/ + +/** + * Set the persistence mode for the device. + * + * For all products. + * For Linux only. + * Requires root/admin permissions. + * + * The persistence mode determines whether the GPU driver software is torn down after the last client + * exits. + * + * This operation takes effect immediately. It is not persistent across reboots. After each reboot the + * persistence mode is reset to "Disabled". + * + * See \ref nvmlEnableState_t for available modes. + * + * After calling this API with mode set to NVML_FEATURE_DISABLED on a device that has its own NUMA + * memory, the given device handle will no longer be valid, and to continue to interact with this + * device, a new handle should be obtained from one of the nvmlDeviceGetHandleBy*() APIs. This + * limitation is currently only applicable to devices that have a coherent NVLink connection to + * system memory. + * + * @param device The identifier of the target device + * @param mode The target persistence mode + * + * @return + * - \ref NVML_SUCCESS if the persistence mode was set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a mode is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetPersistenceMode() + */ +nvmlReturn_t DECLDIR nvmlDeviceSetPersistenceMode(nvmlDevice_t device, nvmlEnableState_t mode); + +/** + * Set the compute mode for the device. + * + * For all products. + * Requires root/admin permissions. + * + * The compute mode determines whether a GPU can be used for compute operations and whether it can + * be shared across contexts. + * + * This operation takes effect immediately. Under Linux it is not persistent across reboots and + * always resets to "Default". Under windows it is persistent. + * + * Under windows compute mode may only be set to DEFAULT when running in WDDM + * + * @note On MIG-enabled GPUs, compute mode would be set to DEFAULT and changing it is not supported. + * + * See \ref nvmlComputeMode_t for details on available compute modes. + * + * @param device The identifier of the target device + * @param mode The target compute mode + * + * @return + * - \ref NVML_SUCCESS if the compute mode was set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a mode is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetComputeMode() + */ +nvmlReturn_t DECLDIR nvmlDeviceSetComputeMode(nvmlDevice_t device, nvmlComputeMode_t mode); + +/** + * Set the ECC mode for the device. + * + * For Kepler &tm; or newer fully supported devices. + * Only applicable to devices with ECC. + * Requires \a NVML_INFOROM_ECC version 1.0 or higher. + * Requires root/admin permissions. + * + * The ECC mode determines whether the GPU enables its ECC support. + * + * This operation takes effect after the next reboot. + * + * See \ref nvmlEnableState_t for details on available modes. + * + * @param device The identifier of the target device + * @param ecc The target ECC mode + * + * @return + * - \ref NVML_SUCCESS if the ECC mode was set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a ecc is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetEccMode() + */ +nvmlReturn_t DECLDIR nvmlDeviceSetEccMode(nvmlDevice_t device, nvmlEnableState_t ecc); + +/** + * Clear the ECC error and other memory error counts for the device. + * + * For Kepler &tm; or newer fully supported devices. + * Only applicable to devices with ECC. + * Requires \a NVML_INFOROM_ECC version 2.0 or higher to clear aggregate location-based ECC counts. + * Requires \a NVML_INFOROM_ECC version 1.0 or higher to clear all other ECC counts. + * Requires root/admin permissions. + * Requires ECC Mode to be enabled. + * + * Sets all of the specified ECC counters to 0, including both detailed and total counts. + * + * This operation takes effect immediately. + * + * See \ref nvmlMemoryErrorType_t for details on available counter types. + * + * @param device The identifier of the target device + * @param counterType Flag that indicates which type of errors should be cleared. + * + * @return + * - \ref NVML_SUCCESS if the error counts were cleared + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a counterType is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see + * - nvmlDeviceGetDetailedEccErrors() + * - nvmlDeviceGetTotalEccErrors() + */ +nvmlReturn_t DECLDIR nvmlDeviceClearEccErrorCounts(nvmlDevice_t device, nvmlEccCounterType_t counterType); + +/** + * Set the driver model for the device. + * + * For Fermi &tm; or newer fully supported devices. + * For windows only. + * Requires root/admin permissions. + * + * On Windows platforms the device driver can run in either WDDM or WDM (TCC) mode. If a display is attached + * to the device it must run in WDDM mode. + * + * It is possible to force the change to WDM (TCC) while the display is still attached with a force flag (nvmlFlagForce). + * This should only be done if the host is subsequently powered down and the display is detached from the device + * before the next reboot. + * + * This operation takes effect after the next reboot. + * + * Windows driver model may only be set to WDDM when running in DEFAULT compute mode. + * + * Change driver model to WDDM is not supported when GPU doesn't support graphics acceleration or + * will not support it after reboot. See \ref nvmlDeviceSetGpuOperationMode. + * + * See \ref nvmlDriverModel_t for details on available driver models. + * See \ref nvmlFlagDefault and \ref nvmlFlagForce + * + * @param device The identifier of the target device + * @param driverModel The target driver model + * @param flags Flags that change the default behavior + * + * @return + * - \ref NVML_SUCCESS if the driver model has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a driverModel is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the platform is not windows or the device does not support this feature + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetDriverModel() + */ +nvmlReturn_t DECLDIR nvmlDeviceSetDriverModel(nvmlDevice_t device, nvmlDriverModel_t driverModel, unsigned int flags); + +typedef enum nvmlClockLimitId_enum { + NVML_CLOCK_LIMIT_ID_RANGE_START = 0xffffff00, + NVML_CLOCK_LIMIT_ID_TDP, + NVML_CLOCK_LIMIT_ID_UNLIMITED +} nvmlClockLimitId_t; + +/** + * Set clocks that device will lock to. + * + * Sets the clocks that the device will be running at to the value in the range of minGpuClockMHz to maxGpuClockMHz. + * Setting this will supercede application clock values and take effect regardless if a cuda app is running. + * See /ref nvmlDeviceSetApplicationsClocks + * + * Can be used as a setting to request constant performance. + * + * This can be called with a pair of integer clock frequencies in MHz, or a pair of /ref nvmlClockLimitId_t values. + * See the table below for valid combinations of these values. + * + * minGpuClock | maxGpuClock | Effect + * ------------+-------------+-------------------------------------------------- + * tdp | tdp | Lock clock to TDP + * unlimited | tdp | Upper bound is TDP but clock may drift below this + * tdp | unlimited | Lower bound is TDP but clock may boost above this + * unlimited | unlimited | Unlocked (== nvmlDeviceResetGpuLockedClocks) + * + * If one arg takes one of these values, the other must be one of these values as + * well. Mixed numeric and symbolic calls return NVML_ERROR_INVALID_ARGUMENT. + * + * Requires root/admin permissions. + * + * After system reboot or driver reload applications clocks go back to their default value. + * See \ref nvmlDeviceResetGpuLockedClocks. + * + * For Volta &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param minGpuClockMHz Requested minimum gpu clock in MHz + * @param maxGpuClockMHz Requested maximum gpu clock in MHz + * + * @return + * - \ref NVML_SUCCESS if new settings were successfully set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a minGpuClockMHz and \a maxGpuClockMHz + * is not a valid clock combination + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceSetGpuLockedClocks(nvmlDevice_t device, unsigned int minGpuClockMHz, unsigned int maxGpuClockMHz); + +/** + * Resets the gpu clock to the default value + * + * This is the gpu clock that will be used after system reboot or driver reload. + * Default values are idle clocks, but the current values can be changed using \ref nvmlDeviceSetApplicationsClocks. + * + * @see nvmlDeviceSetGpuLockedClocks + * + * For Volta &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * + * @return + * - \ref NVML_SUCCESS if new settings were successfully set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceResetGpuLockedClocks(nvmlDevice_t device); + +/** + * Set memory clocks that device will lock to. + * + * Sets the device's memory clocks to the value in the range of minMemClockMHz to maxMemClockMHz. + * Setting this will supersede application clock values and take effect regardless of whether a cuda app is running. + * See /ref nvmlDeviceSetApplicationsClocks + * + * Can be used as a setting to request constant performance. + * + * Requires root/admin permissions. + * + * After system reboot or driver reload applications clocks go back to their default value. + * See \ref nvmlDeviceResetMemoryLockedClocks. + * + * For Ampere &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param minMemClockMHz Requested minimum memory clock in MHz + * @param maxMemClockMHz Requested maximum memory clock in MHz + * + * @return + * - \ref NVML_SUCCESS if new settings were successfully set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a minGpuClockMHz and \a maxGpuClockMHz + * is not a valid clock combination + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceSetMemoryLockedClocks(nvmlDevice_t device, unsigned int minMemClockMHz, unsigned int maxMemClockMHz); + +/** + * Resets the memory clock to the default value + * + * This is the memory clock that will be used after system reboot or driver reload. + * Default values are idle clocks, but the current values can be changed using \ref nvmlDeviceSetApplicationsClocks. + * + * @see nvmlDeviceSetMemoryLockedClocks + * + * For Ampere &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * + * @return + * - \ref NVML_SUCCESS if new settings were successfully set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceResetMemoryLockedClocks(nvmlDevice_t device); + +/** + * Set clocks that applications will lock to. + * + * Sets the clocks that compute and graphics applications will be running at. + * e.g. CUDA driver requests these clocks during context creation which means this property + * defines clocks at which CUDA applications will be running unless some overspec event + * occurs (e.g. over power, over thermal or external HW brake). + * + * Can be used as a setting to request constant performance. + * + * On Pascal and newer hardware, this will automatically disable automatic boosting of clocks. + * + * On K80 and newer Kepler and Maxwell GPUs, users desiring fixed performance should also call + * \ref nvmlDeviceSetAutoBoostedClocksEnabled to prevent clocks from automatically boosting + * above the clock value being set. + * + * For Kepler &tm; or newer non-GeForce fully supported devices and Maxwell or newer GeForce devices. + * Requires root/admin permissions. + * + * See \ref nvmlDeviceGetSupportedMemoryClocks and \ref nvmlDeviceGetSupportedGraphicsClocks + * for details on how to list available clocks combinations. + * + * After system reboot or driver reload applications clocks go back to their default value. + * See \ref nvmlDeviceResetApplicationsClocks. + * + * @param device The identifier of the target device + * @param memClockMHz Requested memory clock in MHz + * @param graphicsClockMHz Requested graphics clock in MHz + * + * @return + * - \ref NVML_SUCCESS if new settings were successfully set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a memClockMHz and \a graphicsClockMHz + * is not a valid clock combination + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceSetApplicationsClocks(nvmlDevice_t device, unsigned int memClockMHz, unsigned int graphicsClockMHz); + +/** + * Retrieves the frequency monitor fault status for the device. + * + * For Ampere &tm; or newer fully supported devices. + * Requires root user. + * + * See \ref nvmlClkMonStatus_t for details on decoding the status output. + * + * @param device The identifier of the target device + * @param status Reference in which to return the clkmon fault status + * + * @return + * - \ref NVML_SUCCESS if \a status has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a status is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetClkMonStatus() + */ +nvmlReturn_t DECLDIR nvmlDeviceGetClkMonStatus(nvmlDevice_t device, nvmlClkMonStatus_t *status); + +/** + * Set new power limit of this device. + * + * For Kepler &tm; or newer fully supported devices. + * Requires root/admin permissions. + * + * See \ref nvmlDeviceGetPowerManagementLimitConstraints to check the allowed ranges of values. + * + * \note Limit is not persistent across reboots or driver unloads. + * Enable persistent mode to prevent driver from unloading when no application is using the device. + * + * @param device The identifier of the target device + * @param limit Power management limit in milliwatts to set + * + * @return + * - \ref NVML_SUCCESS if \a limit has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a defaultLimit is out of range + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceGetPowerManagementLimitConstraints + * @see nvmlDeviceGetPowerManagementDefaultLimit + */ +nvmlReturn_t DECLDIR nvmlDeviceSetPowerManagementLimit(nvmlDevice_t device, unsigned int limit); + +/** + * Sets new GOM. See \a nvmlGpuOperationMode_t for details. + * + * For GK110 M-class and X-class Tesla &tm; products from the Kepler family. + * Modes \ref NVML_GOM_LOW_DP and \ref NVML_GOM_ALL_ON are supported on fully supported GeForce products. + * Not supported on Quadro ® and Tesla &tm; C-class products. + * Requires root/admin permissions. + * + * Changing GOMs requires a reboot. + * The reboot requirement might be removed in the future. + * + * Compute only GOMs don't support graphics acceleration. Under windows switching to these GOMs when + * pending driver model is WDDM is not supported. See \ref nvmlDeviceSetDriverModel. + * + * @param device The identifier of the target device + * @param mode Target GOM + * + * @return + * - \ref NVML_SUCCESS if \a mode has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a mode incorrect + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support GOM or specific mode + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlGpuOperationMode_t + * @see nvmlDeviceGetGpuOperationMode + */ +nvmlReturn_t DECLDIR nvmlDeviceSetGpuOperationMode(nvmlDevice_t device, nvmlGpuOperationMode_t mode); + +/** + * Changes the root/admin restructions on certain APIs. See \a nvmlRestrictedAPI_t for the list of supported APIs. + * This method can be used by a root/admin user to give non-root/admin access to certain otherwise-restricted APIs. + * The new setting lasts for the lifetime of the NVIDIA driver; it is not persistent. See \a nvmlDeviceGetAPIRestriction + * to query the current restriction settings. + * + * For Kepler &tm; or newer fully supported devices. + * Requires root/admin permissions. + * + * @param device The identifier of the target device + * @param apiType Target API type for this operation + * @param isRestricted The target restriction + * + * @return + * - \ref NVML_SUCCESS if \a isRestricted has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a apiType incorrect + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support changing API restrictions or the device does not support + * the feature that api restrictions are being set for (E.G. Enabling/disabling auto + * boosted clocks is not supported by the device) + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlRestrictedAPI_t + */ +nvmlReturn_t DECLDIR nvmlDeviceSetAPIRestriction(nvmlDevice_t device, nvmlRestrictedAPI_t apiType, nvmlEnableState_t isRestricted); + +/** + * @} + */ + +/** @addtogroup nvmlAccountingStats + * @{ + */ + +/** + * Enables or disables per process accounting. + * + * For Kepler &tm; or newer fully supported devices. + * Requires root/admin permissions. + * + * @note This setting is not persistent and will default to disabled after driver unloads. + * Enable persistence mode to be sure the setting doesn't switch off to disabled. + * + * @note Enabling accounting mode has no negative impact on the GPU performance. + * + * @note Disabling accounting clears all accounting pids information. + * + * @note On MIG-enabled GPUs, accounting mode would be set to DISABLED and changing it is not supported. + * + * See \ref nvmlDeviceGetAccountingMode + * See \ref nvmlDeviceGetAccountingStats + * See \ref nvmlDeviceClearAccountingPids + * + * @param device The identifier of the target device + * @param mode The target accounting mode + * + * @return + * - \ref NVML_SUCCESS if the new mode has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device or \a mode are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceSetAccountingMode(nvmlDevice_t device, nvmlEnableState_t mode); + +/** + * Clears accounting information about all processes that have already terminated. + * + * For Kepler &tm; or newer fully supported devices. + * Requires root/admin permissions. + * + * See \ref nvmlDeviceGetAccountingMode + * See \ref nvmlDeviceGetAccountingStats + * See \ref nvmlDeviceSetAccountingMode + * + * @param device The identifier of the target device + * + * @return + * - \ref NVML_SUCCESS if accounting information has been cleared + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceClearAccountingPids(nvmlDevice_t device); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup NvLink NvLink Methods + * This chapter describes methods that NVML can perform on NVLINK enabled devices. + * @{ + */ +/***************************************************************************************************/ + +/** + * Retrieves the state of the device's NvLink for the link specified + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param link Specifies the NvLink link to be queried + * @param isActive \a nvmlEnableState_t where NVML_FEATURE_ENABLED indicates that + * the link is active and NVML_FEATURE_DISABLED indicates it + * is inactive + * + * @return + * - \ref NVML_SUCCESS if \a isActive has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device or \a link is invalid or \a isActive is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetNvLinkState(nvmlDevice_t device, unsigned int link, nvmlEnableState_t *isActive); + +/** + * Retrieves the version of the device's NvLink for the link specified + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param link Specifies the NvLink link to be queried + * @param version Requested NvLink version + * + * @return + * - \ref NVML_SUCCESS if \a version has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device or \a link is invalid or \a version is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetNvLinkVersion(nvmlDevice_t device, unsigned int link, unsigned int *version); + +/** + * Retrieves the requested capability from the device's NvLink for the link specified + * Please refer to the \a nvmlNvLinkCapability_t structure for the specific caps that can be queried + * The return value should be treated as a boolean. + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param link Specifies the NvLink link to be queried + * @param capability Specifies the \a nvmlNvLinkCapability_t to be queried + * @param capResult A boolean for the queried capability indicating that feature is available + * + * @return + * - \ref NVML_SUCCESS if \a capResult has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a link, or \a capability is invalid or \a capResult is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetNvLinkCapability(nvmlDevice_t device, unsigned int link, + nvmlNvLinkCapability_t capability, unsigned int *capResult); + +/** + * Retrieves the PCI information for the remote node on a NvLink link + * Note: pciSubSystemId is not filled in this function and is indeterminate + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param link Specifies the NvLink link to be queried + * @param pci \a nvmlPciInfo_t of the remote node for the specified link + * + * @return + * - \ref NVML_SUCCESS if \a pci has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device or \a link is invalid or \a pci is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetNvLinkRemotePciInfo_v2(nvmlDevice_t device, unsigned int link, nvmlPciInfo_t *pci); + +/** + * Retrieves the specified error counter value + * Please refer to \a nvmlNvLinkErrorCounter_t for error counters that are available + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param link Specifies the NvLink link to be queried + * @param counter Specifies the NvLink counter to be queried + * @param counterValue Returned counter value + * + * @return + * - \ref NVML_SUCCESS if \a counter has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a link, or \a counter is invalid or \a counterValue is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetNvLinkErrorCounter(nvmlDevice_t device, unsigned int link, + nvmlNvLinkErrorCounter_t counter, unsigned long long *counterValue); + +/** + * Resets all error counters to zero + * Please refer to \a nvmlNvLinkErrorCounter_t for the list of error counters that are reset + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param link Specifies the NvLink link to be queried + * + * @return + * - \ref NVML_SUCCESS if the reset is successful + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device or \a link is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceResetNvLinkErrorCounters(nvmlDevice_t device, unsigned int link); + +/** + * Deprecated: Setting utilization counter control is no longer supported. + * + * Set the NVLINK utilization counter control information for the specified counter, 0 or 1. + * Please refer to \a nvmlNvLinkUtilizationControl_t for the structure definition. Performs a reset + * of the counters if the reset parameter is non-zero. + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param counter Specifies the counter that should be set (0 or 1). + * @param link Specifies the NvLink link to be queried + * @param control A reference to the \a nvmlNvLinkUtilizationControl_t to set + * @param reset Resets the counters on set if non-zero + * + * @return + * - \ref NVML_SUCCESS if the control has been set successfully + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a counter, \a link, or \a control is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceSetNvLinkUtilizationControl(nvmlDevice_t device, unsigned int link, unsigned int counter, + nvmlNvLinkUtilizationControl_t *control, unsigned int reset); + +/** + * Deprecated: Getting utilization counter control is no longer supported. + * + * Get the NVLINK utilization counter control information for the specified counter, 0 or 1. + * Please refer to \a nvmlNvLinkUtilizationControl_t for the structure definition + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param counter Specifies the counter that should be set (0 or 1). + * @param link Specifies the NvLink link to be queried + * @param control A reference to the \a nvmlNvLinkUtilizationControl_t to place information + * + * @return + * - \ref NVML_SUCCESS if the control has been set successfully + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a counter, \a link, or \a control is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetNvLinkUtilizationControl(nvmlDevice_t device, unsigned int link, unsigned int counter, + nvmlNvLinkUtilizationControl_t *control); + + +/** + * Deprecated: Use \ref nvmlDeviceGetFieldValues with NVML_FI_DEV_NVLINK_THROUGHPUT_* as field values instead. + * + * Retrieve the NVLINK utilization counter based on the current control for a specified counter. + * In general it is good practice to use \a nvmlDeviceSetNvLinkUtilizationControl + * before reading the utilization counters as they have no default state + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param link Specifies the NvLink link to be queried + * @param counter Specifies the counter that should be read (0 or 1). + * @param rxcounter Receive counter return value + * @param txcounter Transmit counter return value + * + * @return + * - \ref NVML_SUCCESS if \a rxcounter and \a txcounter have been successfully set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a counter, or \a link is invalid or \a rxcounter or \a txcounter are NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetNvLinkUtilizationCounter(nvmlDevice_t device, unsigned int link, unsigned int counter, + unsigned long long *rxcounter, unsigned long long *txcounter); + +/** + * Deprecated: Freezing NVLINK utilization counters is no longer supported. + * + * Freeze the NVLINK utilization counters + * Both the receive and transmit counters are operated on by this function + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param link Specifies the NvLink link to be queried + * @param counter Specifies the counter that should be frozen (0 or 1). + * @param freeze NVML_FEATURE_ENABLED = freeze the receive and transmit counters + * NVML_FEATURE_DISABLED = unfreeze the receive and transmit counters + * + * @return + * - \ref NVML_SUCCESS if counters were successfully frozen or unfrozen + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a link, \a counter, or \a freeze is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceFreezeNvLinkUtilizationCounter (nvmlDevice_t device, unsigned int link, + unsigned int counter, nvmlEnableState_t freeze); + +/** + * Deprecated: Resetting NVLINK utilization counters is no longer supported. + * + * Reset the NVLINK utilization counters + * Both the receive and transmit counters are operated on by this function + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param link Specifies the NvLink link to be reset + * @param counter Specifies the counter that should be reset (0 or 1) + * + * @return + * - \ref NVML_SUCCESS if counters were successfully reset + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a link, or \a counter is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceResetNvLinkUtilizationCounter (nvmlDevice_t device, unsigned int link, unsigned int counter); + +/** +* Get the NVLink device type of the remote device connected over the given link. +* +* @param device The device handle of the target GPU +* @param link The NVLink link index on the target GPU +* @param pNvLinkDeviceType Pointer in which the output remote device type is returned +* +* @return +* - \ref NVML_SUCCESS if \a pNvLinkDeviceType has been set +* - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized +* - \ref NVML_ERROR_NOT_SUPPORTED if NVLink is not supported +* - \ref NVML_ERROR_INVALID_ARGUMENT if \a device or \a link is invalid, or +* \a pNvLinkDeviceType is NULL +* - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is +* otherwise inaccessible +* - \ref NVML_ERROR_UNKNOWN on any unexpected error +*/ +nvmlReturn_t DECLDIR nvmlDeviceGetNvLinkRemoteDeviceType(nvmlDevice_t device, unsigned int link, nvmlIntNvLinkDeviceType_t *pNvLinkDeviceType); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlEvents Event Handling Methods + * This chapter describes methods that NVML can perform against each device to register and wait for + * some event to occur. + * @{ + */ +/***************************************************************************************************/ + +/** + * Create an empty set of events. + * Event set should be freed by \ref nvmlEventSetFree + * + * For Fermi &tm; or newer fully supported devices. + * @param set Reference in which to return the event handle + * + * @return + * - \ref NVML_SUCCESS if the event has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a set is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlEventSetFree + */ +nvmlReturn_t DECLDIR nvmlEventSetCreate(nvmlEventSet_t *set); + +/** + * Starts recording of events on a specified devices and add the events to specified \ref nvmlEventSet_t + * + * For Fermi &tm; or newer fully supported devices. + * Ecc events are available only on ECC enabled devices (see \ref nvmlDeviceGetTotalEccErrors) + * Power capping events are available only on Power Management enabled devices (see \ref nvmlDeviceGetPowerManagementMode) + * + * For Linux only. + * + * \b IMPORTANT: Operations on \a set are not thread safe + * + * This call starts recording of events on specific device. + * All events that occurred before this call are not recorded. + * Checking if some event occurred can be done with \ref nvmlEventSetWait_v2 + * + * If function reports NVML_ERROR_UNKNOWN, event set is in undefined state and should be freed. + * If function reports NVML_ERROR_NOT_SUPPORTED, event set can still be used. None of the requested eventTypes + * are registered in that case. + * + * @param device The identifier of the target device + * @param eventTypes Bitmask of \ref nvmlEventType to record + * @param set Set to which add new event types + * + * @return + * - \ref NVML_SUCCESS if the event has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a eventTypes is invalid or \a set is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the platform does not support this feature or some of requested event types + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlEventType + * @see nvmlDeviceGetSupportedEventTypes + * @see nvmlEventSetWait + * @see nvmlEventSetFree + */ +nvmlReturn_t DECLDIR nvmlDeviceRegisterEvents(nvmlDevice_t device, unsigned long long eventTypes, nvmlEventSet_t set); + +/** + * Returns information about events supported on device + * + * For Fermi &tm; or newer fully supported devices. + * + * Events are not supported on Windows. So this function returns an empty mask in \a eventTypes on Windows. + * + * @param device The identifier of the target device + * @param eventTypes Reference in which to return bitmask of supported events + * + * @return + * - \ref NVML_SUCCESS if the eventTypes has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a eventType is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlEventType + * @see nvmlDeviceRegisterEvents + */ +nvmlReturn_t DECLDIR nvmlDeviceGetSupportedEventTypes(nvmlDevice_t device, unsigned long long *eventTypes); + +/** + * Waits on events and delivers events + * + * For Fermi &tm; or newer fully supported devices. + * + * If some events are ready to be delivered at the time of the call, function returns immediately. + * If there are no events ready to be delivered, function sleeps till event arrives + * but not longer than specified timeout. This function in certain conditions can return before + * specified timeout passes (e.g. when interrupt arrives) + * + * On Windows, in case of xid error, the function returns the most recent xid error type seen by the system. + * If there are multiple xid errors generated before nvmlEventSetWait is invoked then the last seen xid error + * type is returned for all xid error events. + * + * On Linux, every xid error event would return the associated event data and other information if applicable. + * + * In MIG mode, if device handle is provided, the API reports all the events for the available instances, + * only if the caller has appropriate privileges. In absence of required privileges, only the events which + * affect all the instances (i.e. whole device) are reported. + * + * This API does not currently support per-instance event reporting using MIG device handles. + * + * @param set Reference to set of events to wait on + * @param data Reference in which to return event data + * @param timeoutms Maximum amount of wait time in milliseconds for registered event + * + * @return + * - \ref NVML_SUCCESS if the data has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a data is NULL + * - \ref NVML_ERROR_TIMEOUT if no event arrived in specified timeout or interrupt arrived + * - \ref NVML_ERROR_GPU_IS_LOST if a GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlEventType + * @see nvmlDeviceRegisterEvents + */ +nvmlReturn_t DECLDIR nvmlEventSetWait_v2(nvmlEventSet_t set, nvmlEventData_t * data, unsigned int timeoutms); + +/** + * Releases events in the set + * + * For Fermi &tm; or newer fully supported devices. + * + * @param set Reference to events to be released + * + * @return + * - \ref NVML_SUCCESS if the event has been successfully released + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlDeviceRegisterEvents + */ +nvmlReturn_t DECLDIR nvmlEventSetFree(nvmlEventSet_t set); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlZPI Drain states + * This chapter describes methods that NVML can perform against each device to control their drain state + * and recognition by NVML and NVIDIA kernel driver. These methods can be used with out-of-band tools to + * power on/off GPUs, enable robust reset scenarios, etc. + * @{ + */ +/***************************************************************************************************/ + +/** + * Modify the drain state of a GPU. This method forces a GPU to no longer accept new incoming requests. + * Any new NVML process will no longer see this GPU. Persistence mode for this GPU must be turned off before + * this call is made. + * Must be called as administrator. + * For Linux only. + * + * For Pascal &tm; or newer fully supported devices. + * Some Kepler devices supported. + * + * @param pciInfo The PCI address of the GPU drain state to be modified + * @param newState The drain state that should be entered, see \ref nvmlEnableState_t + * + * @return + * - \ref NVML_SUCCESS if counters were successfully reset + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a nvmlIndex or \a newState is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_NO_PERMISSION if the calling process has insufficient permissions to perform operation + * - \ref NVML_ERROR_IN_USE if the device has persistence mode turned on + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceModifyDrainState (nvmlPciInfo_t *pciInfo, nvmlEnableState_t newState); + +/** + * Query the drain state of a GPU. This method is used to check if a GPU is in a currently draining + * state. + * For Linux only. + * + * For Pascal &tm; or newer fully supported devices. + * Some Kepler devices supported. + * + * @param pciInfo The PCI address of the GPU drain state to be queried + * @param currentState The current drain state for this GPU, see \ref nvmlEnableState_t + * + * @return + * - \ref NVML_SUCCESS if counters were successfully reset + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a nvmlIndex or \a currentState is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceQueryDrainState (nvmlPciInfo_t *pciInfo, nvmlEnableState_t *currentState); + +/** + * This method will remove the specified GPU from the view of both NVML and the NVIDIA kernel driver + * as long as no other processes are attached. If other processes are attached, this call will return + * NVML_ERROR_IN_USE and the GPU will be returned to its original "draining" state. Note: the + * only situation where a process can still be attached after nvmlDeviceModifyDrainState() is called + * to initiate the draining state is if that process was using, and is still using, a GPU before the + * call was made. Also note, persistence mode counts as an attachment to the GPU thus it must be disabled + * prior to this call. + * + * For long-running NVML processes please note that this will change the enumeration of current GPUs. + * For example, if there are four GPUs present and GPU1 is removed, the new enumeration will be 0-2. + * Also, device handles after the removed GPU will not be valid and must be re-established. + * Must be run as administrator. + * For Linux only. + * + * For Pascal &tm; or newer fully supported devices. + * Some Kepler devices supported. + * + * @param pciInfo The PCI address of the GPU to be removed + * @param gpuState Whether the GPU is to be removed, from the OS + * see \ref nvmlDetachGpuState_t + * @param linkState Requested upstream PCIe link state, see \ref nvmlPcieLinkState_t + * + * @return + * - \ref NVML_SUCCESS if counters were successfully reset + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a nvmlIndex is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device doesn't support this feature + * - \ref NVML_ERROR_IN_USE if the device is still in use and cannot be removed + */ +nvmlReturn_t DECLDIR nvmlDeviceRemoveGpu_v2(nvmlPciInfo_t *pciInfo, nvmlDetachGpuState_t gpuState, nvmlPcieLinkState_t linkState); + +/** + * Request the OS and the NVIDIA kernel driver to rediscover a portion of the PCI subsystem looking for GPUs that + * were previously removed. The portion of the PCI tree can be narrowed by specifying a domain, bus, and device. + * If all are zeroes then the entire PCI tree will be searched. Please note that for long-running NVML processes + * the enumeration will change based on how many GPUs are discovered and where they are inserted in bus order. + * + * In addition, all newly discovered GPUs will be initialized and their ECC scrubbed which may take several seconds + * per GPU. Also, all device handles are no longer guaranteed to be valid post discovery. + * + * Must be run as administrator. + * For Linux only. + * + * For Pascal &tm; or newer fully supported devices. + * Some Kepler devices supported. + * + * @param pciInfo The PCI tree to be searched. Only the domain, bus, and device + * fields are used in this call. + * + * @return + * - \ref NVML_SUCCESS if counters were successfully reset + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a pciInfo is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the operating system does not support this feature + * - \ref NVML_ERROR_OPERATING_SYSTEM if the operating system is denying this feature + * - \ref NVML_ERROR_NO_PERMISSION if the calling process has insufficient permissions to perform operation + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceDiscoverGpus (nvmlPciInfo_t *pciInfo); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlFieldValueQueries Field Value Queries + * This chapter describes NVML operations that are associated with retrieving Field Values from NVML + * @{ + */ +/***************************************************************************************************/ + +/** + * Request values for a list of fields for a device. This API allows multiple fields to be queried at once. + * If any of the underlying fieldIds are populated by the same driver call, the results for those field IDs + * will be populated from a single call rather than making a driver call for each fieldId. + * + * @param device The device handle of the GPU to request field values for + * @param valuesCount Number of entries in values that should be retrieved + * @param values Array of \a valuesCount structures to hold field values. + * Each value's fieldId must be populated prior to this call + * + * @return + * - \ref NVML_SUCCESS if any values in \a values were populated. Note that you must + * check the nvmlReturn field of each value for each individual + * status + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a values is NULL + */ +nvmlReturn_t DECLDIR nvmlDeviceGetFieldValues(nvmlDevice_t device, int valuesCount, nvmlFieldValue_t *values); + +/** + * Clear values for a list of fields for a device. This API allows multiple fields to be cleared at once. + * + * @param device The device handle of the GPU to request field values for + * @param valuesCount Number of entries in values that should be cleared + * @param values Array of \a valuesCount structures to hold field values. + * Each value's fieldId must be populated prior to this call + * + * @return + * - \ref NVML_SUCCESS if any values in \a values were cleared. Note that you must + * check the nvmlReturn field of each value for each individual + * status + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a values is NULL + */ +nvmlReturn_t DECLDIR nvmlDeviceClearFieldValues(nvmlDevice_t device, int valuesCount, nvmlFieldValue_t *values); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup vGPU Enums, Constants and Structs + * @{ + */ +/** @} */ +/***************************************************************************************************/ + +/***************************************************************************************************/ +/** @defgroup nvmlVirtualGpuQueries vGPU APIs + * This chapter describes operations that are associated with NVIDIA vGPU Software products. + * @{ + */ +/***************************************************************************************************/ + +/** + * This method is used to get the virtualization mode corresponding to the GPU. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device Identifier of the target device + * @param pVirtualMode Reference to virtualization mode. One of NVML_GPU_VIRTUALIZATION_? + * + * @return + * - \ref NVML_SUCCESS if \a pVirtualMode is fetched + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a pVirtualMode is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetVirtualizationMode(nvmlDevice_t device, nvmlGpuVirtualizationMode_t *pVirtualMode); + +/** + * Queries if SR-IOV host operation is supported on a vGPU supported device. + * + * Checks whether SR-IOV host capability is supported by the device and the + * driver, and indicates device is in SR-IOV mode if both of these conditions + * are true. + * + * @param device The identifier of the target device + * @param pHostVgpuMode Reference in which to return the current vGPU mode + * + * @return + * - \ref NVML_SUCCESS if device's vGPU mode has been successfully retrieved + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device handle is 0 or \a pVgpuMode is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if \a device doesn't support this feature. + * - \ref NVML_ERROR_UNKNOWN if any unexpected error occurred + */ +nvmlReturn_t DECLDIR nvmlDeviceGetHostVgpuMode(nvmlDevice_t device, nvmlHostVgpuMode_t *pHostVgpuMode); + +/** + * This method is used to set the virtualization mode corresponding to the GPU. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device Identifier of the target device + * @param virtualMode virtualization mode. One of NVML_GPU_VIRTUALIZATION_? + * + * @return + * - \ref NVML_SUCCESS if \a pVirtualMode is set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a pVirtualMode is NULL + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_NOT_SUPPORTED if setting of virtualization mode is not supported. + * - \ref NVML_ERROR_NO_PERMISSION if setting of virtualization mode is not allowed for this client. + */ +nvmlReturn_t DECLDIR nvmlDeviceSetVirtualizationMode(nvmlDevice_t device, nvmlGpuVirtualizationMode_t virtualMode); + +/** + * Retrieve the vGPU Software licensable features. + * + * Identifies whether the system supports vGPU Software Licensing. If it does, return the list of licensable feature(s) + * and their current license status. + * + * @param device Identifier of the target device + * @param pGridLicensableFeatures Pointer to structure in which vGPU software licensable features are returned + * + * @return + * - \ref NVML_SUCCESS if licensable features are successfully retrieved + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a pGridLicensableFeatures is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGridLicensableFeatures_v4(nvmlDevice_t device, nvmlGridLicensableFeatures_t *pGridLicensableFeatures); + +/** + * Retrieves the current utilization and process ID + * + * For Maxwell &tm; or newer fully supported devices. + * + * Reads recent utilization of GPU SM (3D/Compute), framebuffer, video encoder, and video decoder for processes running. + * Utilization values are returned as an array of utilization sample structures in the caller-supplied buffer pointed at + * by \a utilization. One utilization sample structure is returned per process running, that had some non-zero utilization + * during the last sample period. It includes the CPU timestamp at which the samples were recorded. Individual utilization values + * are returned as "unsigned int" values. + * + * To read utilization values, first determine the size of buffer required to hold the samples by invoking the function with + * \a utilization set to NULL. The caller should allocate a buffer of size + * processSamplesCount * sizeof(nvmlProcessUtilizationSample_t). Invoke the function again with the allocated buffer passed + * in \a utilization, and \a processSamplesCount set to the number of entries the buffer is sized for. + * + * On successful return, the function updates \a processSamplesCount with the number of process utilization sample + * structures that were actually written. This may differ from a previously read value as instances are created or + * destroyed. + * + * lastSeenTimeStamp represents the CPU timestamp in microseconds at which utilization samples were last read. Set it to 0 + * to read utilization based on all the samples maintained by the driver's internal sample buffer. Set lastSeenTimeStamp + * to a timeStamp retrieved from a previous query to read utilization since the previous query. + * + * @note On MIG-enabled GPUs, querying process utilization is not currently supported. + * + * @param device The identifier of the target device + * @param utilization Pointer to caller-supplied buffer in which guest process utilization samples are returned + * @param processSamplesCount Pointer to caller-supplied array size, and returns number of processes running + * @param lastSeenTimeStamp Return only samples with timestamp greater than lastSeenTimeStamp. + + * @return + * - \ref NVML_SUCCESS if \a utilization has been populated + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a utilization is NULL, or \a samplingPeriodUs is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_NOT_FOUND if sample entries are not found + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetProcessUtilization(nvmlDevice_t device, nvmlProcessUtilizationSample_t *utilization, + unsigned int *processSamplesCount, unsigned long long lastSeenTimeStamp); + +/** + * Retrieve GSP firmware version. + * + * The caller passes in buffer via \a version and corresponding GSP firmware numbered version + * is returned with the same parameter in string format. + * + * @param device Device handle + * @param version The retrieved GSP firmware version + * + * @return + * - \ref NVML_SUCCESS if GSP firmware version is sucessfully retrieved + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or GSP \a version pointer is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if GSP firmware is not enabled for GPU + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGspFirmwareVersion(nvmlDevice_t device, char *version); + +/** + * Retrieve GSP firmware mode. + * + * The caller passes in integer pointers. GSP firmware enablement and default mode information is returned with + * corresponding parameters. The return value in \a isEnabled and \a defaultMode should be treated as boolean. + * + * @param device Device handle + * @param isEnabled Pointer to specify if GSP firmware is enabled + * @param defaultMode Pointer to specify if GSP firmware is supported by default on \a device + * + * @return + * - \ref NVML_SUCCESS if GSP firmware mode is sucessfully retrieved + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or any of \a isEnabled or \a defaultMode is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGspFirmwareMode(nvmlDevice_t device, unsigned int *isEnabled, unsigned int *defaultMode); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlVgpu vGPU Management + * @{ + * + * This chapter describes APIs supporting NVIDIA vGPU. + */ +/***************************************************************************************************/ + +/** + * Retrieve the requested vGPU driver capability. + * + * Refer to the \a nvmlVgpuDriverCapability_t structure for the specific capabilities that can be queried. + * The return value in \a capResult should be treated as a boolean, with a non-zero value indicating that the capability + * is supported. + * + * For Maxwell &tm; or newer fully supported devices. + * + * @param capability Specifies the \a nvmlVgpuDriverCapability_t to be queried + * @param capResult A boolean for the queried capability indicating that feature is supported + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a capability is invalid, or \a capResult is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED the API is not supported in current state or \a devices not in vGPU mode + * - \ref NVML_ERROR_UNKNOWN on any unexpected error +*/ +nvmlReturn_t DECLDIR nvmlGetVgpuDriverCapabilities(nvmlVgpuDriverCapability_t capability, unsigned int *capResult); + +/** + * Retrieve the requested vGPU capability for GPU. + * + * Refer to the \a nvmlDeviceVgpuCapability_t structure for the specific capabilities that can be queried. + * The return value in \a capResult should be treated as a boolean, with a non-zero value indicating that the capability + * is supported. + * + * For Maxwell &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param capability Specifies the \a nvmlDeviceVgpuCapability_t to be queried + * @param capResult A boolean for the queried capability indicating that feature is supported + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a capability is invalid, or \a capResult is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED the API is not supported in current state or \a device not in vGPU mode + * - \ref NVML_ERROR_UNKNOWN on any unexpected error +*/ +nvmlReturn_t DECLDIR nvmlDeviceGetVgpuCapabilities(nvmlDevice_t device, nvmlDeviceVgpuCapability_t capability, unsigned int *capResult); + +/** + * Retrieve the supported vGPU types on a physical GPU (device). + * + * An array of supported vGPU types for the physical GPU indicated by \a device is returned in the caller-supplied buffer + * pointed at by \a vgpuTypeIds. The element count of nvmlVgpuTypeId_t array is passed in \a vgpuCount, and \a vgpuCount + * is used to return the number of vGPU types written to the buffer. + * + * If the supplied buffer is not large enough to accomodate the vGPU type array, the function returns + * NVML_ERROR_INSUFFICIENT_SIZE, with the element count of nvmlVgpuTypeId_t array required in \a vgpuCount. + * To query the number of vGPU types supported for the GPU, call this function with *vgpuCount = 0. + * The code will return NVML_ERROR_INSUFFICIENT_SIZE, or NVML_SUCCESS if no vGPU types are supported. + * + * @param device The identifier of the target device + * @param vgpuCount Pointer to caller-supplied array size, and returns number of vGPU types + * @param vgpuTypeIds Pointer to caller-supplied array in which to return list of vGPU types + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_INSUFFICIENT_SIZE \a vgpuTypeIds buffer is too small, array element count is returned in \a vgpuCount + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuCount is NULL or \a device is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if vGPU is not supported by the device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetSupportedVgpus(nvmlDevice_t device, unsigned int *vgpuCount, nvmlVgpuTypeId_t *vgpuTypeIds); + +/** + * Retrieve the currently creatable vGPU types on a physical GPU (device). + * + * An array of creatable vGPU types for the physical GPU indicated by \a device is returned in the caller-supplied buffer + * pointed at by \a vgpuTypeIds. The element count of nvmlVgpuTypeId_t array is passed in \a vgpuCount, and \a vgpuCount + * is used to return the number of vGPU types written to the buffer. + * + * The creatable vGPU types for a device may differ over time, as there may be restrictions on what type of vGPU types + * can concurrently run on a device. For example, if only one vGPU type is allowed at a time on a device, then the creatable + * list will be restricted to whatever vGPU type is already running on the device. + * + * If the supplied buffer is not large enough to accomodate the vGPU type array, the function returns + * NVML_ERROR_INSUFFICIENT_SIZE, with the element count of nvmlVgpuTypeId_t array required in \a vgpuCount. + * To query the number of vGPU types createable for the GPU, call this function with *vgpuCount = 0. + * The code will return NVML_ERROR_INSUFFICIENT_SIZE, or NVML_SUCCESS if no vGPU types are creatable. + * + * @param device The identifier of the target device + * @param vgpuCount Pointer to caller-supplied array size, and returns number of vGPU types + * @param vgpuTypeIds Pointer to caller-supplied array in which to return list of vGPU types + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_INSUFFICIENT_SIZE \a vgpuTypeIds buffer is too small, array element count is returned in \a vgpuCount + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuCount is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if vGPU is not supported by the device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetCreatableVgpus(nvmlDevice_t device, unsigned int *vgpuCount, nvmlVgpuTypeId_t *vgpuTypeIds); + +/** + * Retrieve the class of a vGPU type. It will not exceed 64 characters in length (including the NUL terminator). + * See \ref nvmlConstants::NVML_DEVICE_NAME_BUFFER_SIZE. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuTypeId Handle to vGPU type + * @param vgpuTypeClass Pointer to string array to return class in + * @param size Size of string + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuTypeId is invalid, or \a vgpuTypeClass is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a size is too small + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuTypeGetClass(nvmlVgpuTypeId_t vgpuTypeId, char *vgpuTypeClass, unsigned int *size); + +/** + * Retrieve the vGPU type name. + * + * The name is an alphanumeric string that denotes a particular vGPU, e.g. GRID M60-2Q. It will not + * exceed 64 characters in length (including the NUL terminator). See \ref + * nvmlConstants::NVML_DEVICE_NAME_BUFFER_SIZE. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuTypeId Handle to vGPU type + * @param vgpuTypeName Pointer to buffer to return name + * @param size Size of buffer + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuTypeId is invalid, or \a name is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a size is too small + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuTypeGetName(nvmlVgpuTypeId_t vgpuTypeId, char *vgpuTypeName, unsigned int *size); + +/** + * Retrieve the GPU Instance Profile ID for the given vGPU type ID. + * The API will return a valid GPU Instance Profile ID for the MIG capable vGPU types, else INVALID_GPU_INSTANCE_PROFILE_ID is + * returned. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuTypeId Handle to vGPU type + * @param gpuInstanceProfileId GPU Instance Profile ID + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_NOT_SUPPORTED if \a device is not in vGPU Host virtualization mode + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuTypeId is invalid, or \a gpuInstanceProfileId is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuTypeGetGpuInstanceProfileId(nvmlVgpuTypeId_t vgpuTypeId, unsigned int *gpuInstanceProfileId); + +/** + * Retrieve the device ID of a vGPU type. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuTypeId Handle to vGPU type + * @param deviceID Device ID and vendor ID of the device contained in single 32 bit value + * @param subsystemID Subsytem ID and subsytem vendor ID of the device contained in single 32 bit value + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuTypeId is invalid, or \a deviceId or \a subsystemID are NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuTypeGetDeviceID(nvmlVgpuTypeId_t vgpuTypeId, unsigned long long *deviceID, unsigned long long *subsystemID); + +/** + * Retrieve the vGPU framebuffer size in bytes. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuTypeId Handle to vGPU type + * @param fbSize Pointer to framebuffer size in bytes + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuTypeId is invalid, or \a fbSize is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuTypeGetFramebufferSize(nvmlVgpuTypeId_t vgpuTypeId, unsigned long long *fbSize); + +/** + * Retrieve count of vGPU's supported display heads. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuTypeId Handle to vGPU type + * @param numDisplayHeads Pointer to number of display heads + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuTypeId is invalid, or \a numDisplayHeads is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuTypeGetNumDisplayHeads(nvmlVgpuTypeId_t vgpuTypeId, unsigned int *numDisplayHeads); + +/** + * Retrieve vGPU display head's maximum supported resolution. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuTypeId Handle to vGPU type + * @param displayIndex Zero-based index of display head + * @param xdim Pointer to maximum number of pixels in X dimension + * @param ydim Pointer to maximum number of pixels in Y dimension + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuTypeId is invalid, or \a xdim or \a ydim are NULL, or \a displayIndex + * is out of range. + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuTypeGetResolution(nvmlVgpuTypeId_t vgpuTypeId, unsigned int displayIndex, unsigned int *xdim, unsigned int *ydim); + +/** + * Retrieve license requirements for a vGPU type + * + * The license type and version required to run the specified vGPU type is returned as an alphanumeric string, in the form + * ",", for example "GRID-Virtual-PC,2.0". If a vGPU is runnable with* more than one type of license, + * the licenses are delimited by a semicolon, for example "GRID-Virtual-PC,2.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0". + * + * The total length of the returned string will not exceed 128 characters, including the NUL terminator. + * See \ref nvmlVgpuConstants::NVML_GRID_LICENSE_BUFFER_SIZE. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuTypeId Handle to vGPU type + * @param vgpuTypeLicenseString Pointer to buffer to return license info + * @param size Size of \a vgpuTypeLicenseString buffer + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuTypeId is invalid, or \a vgpuTypeLicenseString is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a size is too small + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuTypeGetLicense(nvmlVgpuTypeId_t vgpuTypeId, char *vgpuTypeLicenseString, unsigned int size); + +/** + * Retrieve the static frame rate limit value of the vGPU type + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuTypeId Handle to vGPU type + * @param frameRateLimit Reference to return the frame rate limit value + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_NOT_SUPPORTED if frame rate limiter is turned off for the vGPU type + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuTypeId is invalid, or \a frameRateLimit is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuTypeGetFrameRateLimit(nvmlVgpuTypeId_t vgpuTypeId, unsigned int *frameRateLimit); + +/** + * Retrieve the maximum number of vGPU instances creatable on a device for given vGPU type + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param vgpuTypeId Handle to vGPU type + * @param vgpuInstanceCount Pointer to get the max number of vGPU instances + * that can be created on a deicve for given vgpuTypeId + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuTypeId is invalid or is not supported on target device, + * or \a vgpuInstanceCount is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuTypeGetMaxInstances(nvmlDevice_t device, nvmlVgpuTypeId_t vgpuTypeId, unsigned int *vgpuInstanceCount); + +/** + * Retrieve the maximum number of vGPU instances supported per VM for given vGPU type + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuTypeId Handle to vGPU type + * @param vgpuInstanceCountPerVm Pointer to get the max number of vGPU instances supported per VM for given \a vgpuTypeId + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuTypeId is invalid, or \a vgpuInstanceCountPerVm is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuTypeGetMaxInstancesPerVm(nvmlVgpuTypeId_t vgpuTypeId, unsigned int *vgpuInstanceCountPerVm); + +/** + * Retrieve the active vGPU instances on a device. + * + * An array of active vGPU instances is returned in the caller-supplied buffer pointed at by \a vgpuInstances. The + * array elememt count is passed in \a vgpuCount, and \a vgpuCount is used to return the number of vGPU instances + * written to the buffer. + * + * If the supplied buffer is not large enough to accomodate the vGPU instance array, the function returns + * NVML_ERROR_INSUFFICIENT_SIZE, with the element count of nvmlVgpuInstance_t array required in \a vgpuCount. + * To query the number of active vGPU instances, call this function with *vgpuCount = 0. The code will return + * NVML_ERROR_INSUFFICIENT_SIZE, or NVML_SUCCESS if no vGPU Types are supported. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param device The identifier of the target device + * @param vgpuCount Pointer which passes in the array size as well as get + * back the number of types + * @param vgpuInstances Pointer to array in which to return list of vGPU instances + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, or \a vgpuCount is NULL + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a size is too small + * - \ref NVML_ERROR_NOT_SUPPORTED if vGPU is not supported by the device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetActiveVgpus(nvmlDevice_t device, unsigned int *vgpuCount, nvmlVgpuInstance_t *vgpuInstances); + +/** + * Retrieve the VM ID associated with a vGPU instance. + * + * The VM ID is returned as a string, not exceeding 80 characters in length (including the NUL terminator). + * See \ref nvmlConstants::NVML_DEVICE_UUID_BUFFER_SIZE. + * + * The format of the VM ID varies by platform, and is indicated by the type identifier returned in \a vmIdType. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuInstance Identifier of the target vGPU instance + * @param vmId Pointer to caller-supplied buffer to hold VM ID + * @param size Size of buffer in bytes + * @param vmIdType Pointer to hold VM ID type + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vmId or \a vmIdType is NULL, or \a vgpuInstance is 0 + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a size is too small + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetVmID(nvmlVgpuInstance_t vgpuInstance, char *vmId, unsigned int size, nvmlVgpuVmIdType_t *vmIdType); + +/** + * Retrieve the UUID of a vGPU instance. + * + * The UUID is a globally unique identifier associated with the vGPU, and is returned as a 5-part hexadecimal string, + * not exceeding 80 characters in length (including the NULL terminator). + * See \ref nvmlConstants::NVML_DEVICE_UUID_BUFFER_SIZE. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuInstance Identifier of the target vGPU instance + * @param uuid Pointer to caller-supplied buffer to hold vGPU UUID + * @param size Size of buffer in bytes + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a uuid is NULL + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a size is too small + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetUUID(nvmlVgpuInstance_t vgpuInstance, char *uuid, unsigned int size); + +/** + * Retrieve the NVIDIA driver version installed in the VM associated with a vGPU. + * + * The version is returned as an alphanumeric string in the caller-supplied buffer \a version. The length of the version + * string will not exceed 80 characters in length (including the NUL terminator). + * See \ref nvmlConstants::NVML_SYSTEM_DRIVER_VERSION_BUFFER_SIZE. + * + * nvmlVgpuInstanceGetVmDriverVersion() may be called at any time for a vGPU instance. The guest VM driver version is + * returned as "Not Available" if no NVIDIA driver is installed in the VM, or the VM has not yet booted to the point where the + * NVIDIA driver is loaded and initialized. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuInstance Identifier of the target vGPU instance + * @param version Caller-supplied buffer to return driver version string + * @param length Size of \a version buffer + * + * @return + * - \ref NVML_SUCCESS if \a version has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0 + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a length is too small + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetVmDriverVersion(nvmlVgpuInstance_t vgpuInstance, char* version, unsigned int length); + +/** + * Retrieve the framebuffer usage in bytes. + * + * Framebuffer usage is the amont of vGPU framebuffer memory that is currently in use by the VM. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuInstance The identifier of the target instance + * @param fbUsage Pointer to framebuffer usage in bytes + * + * @return + * - \ref NVML_SUCCESS successful completion + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a fbUsage is NULL + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetFbUsage(nvmlVgpuInstance_t vgpuInstance, unsigned long long *fbUsage); + +/** + * @deprecated Use \ref nvmlVgpuInstanceGetLicenseInfo_v2. + * + * Retrieve the current licensing state of the vGPU instance. + * + * If the vGPU is currently licensed, \a licensed is set to 1, otherwise it is set to 0. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuInstance Identifier of the target vGPU instance + * @param licensed Reference to return the licensing status + * + * @return + * - \ref NVML_SUCCESS if \a licensed has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a licensed is NULL + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetLicenseStatus(nvmlVgpuInstance_t vgpuInstance, unsigned int *licensed); + +/** + * Retrieve the vGPU type of a vGPU instance. + * + * Returns the vGPU type ID of vgpu assigned to the vGPU instance. + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuInstance Identifier of the target vGPU instance + * @param vgpuTypeId Reference to return the vgpuTypeId + * + * @return + * - \ref NVML_SUCCESS if \a vgpuTypeId has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a vgpuTypeId is NULL + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetType(nvmlVgpuInstance_t vgpuInstance, nvmlVgpuTypeId_t *vgpuTypeId); + +/** + * Retrieve the frame rate limit set for the vGPU instance. + * + * Returns the value of the frame rate limit set for the vGPU instance + * + * For Kepler &tm; or newer fully supported devices. + * + * @param vgpuInstance Identifier of the target vGPU instance + * @param frameRateLimit Reference to return the frame rate limit + * + * @return + * - \ref NVML_SUCCESS if \a frameRateLimit has been set + * - \ref NVML_ERROR_NOT_SUPPORTED if frame rate limiter is turned off for the vGPU type + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a frameRateLimit is NULL + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetFrameRateLimit(nvmlVgpuInstance_t vgpuInstance, unsigned int *frameRateLimit); + +/** + * Retrieve the current ECC mode of vGPU instance. + * + * @param vgpuInstance The identifier of the target vGPU instance + * @param eccMode Reference in which to return the current ECC mode + * + * @return + * - \ref NVML_SUCCESS if the vgpuInstance's ECC mode has been successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a mode is NULL + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_NOT_SUPPORTED if the vGPU doesn't support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetEccMode(nvmlVgpuInstance_t vgpuInstance, nvmlEnableState_t *eccMode); + +/** + * Retrieve the encoder capacity of a vGPU instance, as a percentage of maximum encoder capacity with valid values in the range 0-100. + * + * For Maxwell &tm; or newer fully supported devices. + * + * @param vgpuInstance Identifier of the target vGPU instance + * @param encoderCapacity Reference to an unsigned int for the encoder capacity + * + * @return + * - \ref NVML_SUCCESS if \a encoderCapacity has been retrived + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a encoderQueryType is invalid + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetEncoderCapacity(nvmlVgpuInstance_t vgpuInstance, unsigned int *encoderCapacity); + +/** + * Set the encoder capacity of a vGPU instance, as a percentage of maximum encoder capacity with valid values in the range 0-100. + * + * For Maxwell &tm; or newer fully supported devices. + * + * @param vgpuInstance Identifier of the target vGPU instance + * @param encoderCapacity Unsigned int for the encoder capacity value + * + * @return + * - \ref NVML_SUCCESS if \a encoderCapacity has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a encoderCapacity is out of range of 0-100. + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceSetEncoderCapacity(nvmlVgpuInstance_t vgpuInstance, unsigned int encoderCapacity); + +/** + * Retrieves the current encoder statistics of a vGPU Instance + * + * For Maxwell &tm; or newer fully supported devices. + * + * @param vgpuInstance Identifier of the target vGPU instance + * @param sessionCount Reference to an unsigned int for count of active encoder sessions + * @param averageFps Reference to an unsigned int for trailing average FPS of all active sessions + * @param averageLatency Reference to an unsigned int for encode latency in microseconds + * + * @return + * - \ref NVML_SUCCESS if \a sessionCount, \a averageFps and \a averageLatency is fetched + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a sessionCount , or \a averageFps or \a averageLatency is NULL + * or \a vgpuInstance is 0. + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetEncoderStats(nvmlVgpuInstance_t vgpuInstance, unsigned int *sessionCount, + unsigned int *averageFps, unsigned int *averageLatency); + +/** + * Retrieves information about all active encoder sessions on a vGPU Instance. + * + * An array of active encoder sessions is returned in the caller-supplied buffer pointed at by \a sessionInfo. The + * array element count is passed in \a sessionCount, and \a sessionCount is used to return the number of sessions + * written to the buffer. + * + * If the supplied buffer is not large enough to accomodate the active session array, the function returns + * NVML_ERROR_INSUFFICIENT_SIZE, with the element count of nvmlEncoderSessionInfo_t array required in \a sessionCount. + * To query the number of active encoder sessions, call this function with *sessionCount = 0. The code will return + * NVML_SUCCESS with number of active encoder sessions updated in *sessionCount. + * + * For Maxwell &tm; or newer fully supported devices. + * + * @param vgpuInstance Identifier of the target vGPU instance + * @param sessionCount Reference to caller supplied array size, and returns + * the number of sessions. + * @param sessionInfo Reference to caller supplied array in which the list + * of session information us returned. + * + * @return + * - \ref NVML_SUCCESS if \a sessionInfo is fetched + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a sessionCount is too small, array element count is + returned in \a sessionCount + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a sessionCount is NULL, or \a vgpuInstance is 0. + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetEncoderSessions(nvmlVgpuInstance_t vgpuInstance, unsigned int *sessionCount, nvmlEncoderSessionInfo_t *sessionInfo); + +/** +* Retrieves the active frame buffer capture sessions statistics of a vGPU Instance +* +* For Maxwell &tm; or newer fully supported devices. +* +* @param vgpuInstance Identifier of the target vGPU instance +* @param fbcStats Reference to nvmlFBCStats_t structure contianing NvFBC stats +* +* @return +* - \ref NVML_SUCCESS if \a fbcStats is fetched +* - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized +* - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a fbcStats is NULL +* - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system +* - \ref NVML_ERROR_UNKNOWN on any unexpected error +*/ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetFBCStats(nvmlVgpuInstance_t vgpuInstance, nvmlFBCStats_t *fbcStats); + +/** +* Retrieves information about active frame buffer capture sessions on a vGPU Instance. +* +* An array of active FBC sessions is returned in the caller-supplied buffer pointed at by \a sessionInfo. The +* array element count is passed in \a sessionCount, and \a sessionCount is used to return the number of sessions +* written to the buffer. +* +* If the supplied buffer is not large enough to accomodate the active session array, the function returns +* NVML_ERROR_INSUFFICIENT_SIZE, with the element count of nvmlFBCSessionInfo_t array required in \a sessionCount. +* To query the number of active FBC sessions, call this function with *sessionCount = 0. The code will return +* NVML_SUCCESS with number of active FBC sessions updated in *sessionCount. +* +* For Maxwell &tm; or newer fully supported devices. +* +* @note hResolution, vResolution, averageFPS and averageLatency data for a FBC session returned in \a sessionInfo may +* be zero if there are no new frames captured since the session started. +* +* @param vgpuInstance Identifier of the target vGPU instance +* @param sessionCount Reference to caller supplied array size, and returns the number of sessions. +* @param sessionInfo Reference in which to return the session information +* +* @return +* - \ref NVML_SUCCESS if \a sessionInfo is fetched +* - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized +* - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a sessionCount is NULL. +* - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system +* - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a sessionCount is too small, array element count is returned in \a sessionCount +* - \ref NVML_ERROR_UNKNOWN on any unexpected error +*/ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetFBCSessions(nvmlVgpuInstance_t vgpuInstance, unsigned int *sessionCount, nvmlFBCSessionInfo_t *sessionInfo); + +/** +* Retrieve the GPU Instance ID for the given vGPU Instance. +* The API will return a valid GPU Instance ID for MIG backed vGPU Instance, else INVALID_GPU_INSTANCE_ID is returned. +* +* For Kepler &tm; or newer fully supported devices. +* +* @param vgpuInstance Identifier of the target vGPU instance +* @param gpuInstanceId GPU Instance ID +* +* @return +* - \ref NVML_SUCCESS successful completion +* - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized +* - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a gpuInstanceId is NULL. +* - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system +* - \ref NVML_ERROR_UNKNOWN on any unexpected error +*/ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetGpuInstanceId(nvmlVgpuInstance_t vgpuInstance, unsigned int *gpuInstanceId); + +/** +* Retrieves the PCI Id of the given vGPU Instance i.e. the PCI Id of the GPU as seen inside the VM. +* +* The vGPU PCI id is returned as "00000000:00:00.0" if NVIDIA driver is not installed on the vGPU instance. +* +* @param vgpuInstance Identifier of the target vGPU instance +* @param vgpuPciId Caller-supplied buffer to return vGPU PCI Id string +* @param length Size of the vgpuPciId buffer +* +* @return +* - \ref NVML_SUCCESS if vGPU PCI Id is sucessfully retrieved +* - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized +* - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a vgpuPciId is NULL +* - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system +* - \ref NVML_ERROR_DRIVER_NOT_LOADED if NVIDIA driver is not running on the vGPU instance +* - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a length is too small, \a length is set to required length +* - \ref NVML_ERROR_UNKNOWN on any unexpected error +*/ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetGpuPciId(nvmlVgpuInstance_t vgpuInstance, char *vgpuPciId, unsigned int *length); + +/** +* Retrieve the requested capability for a given vGPU type. Refer to the \a nvmlVgpuCapability_t structure +* for the specific capabilities that can be queried. The return value in \a capResult should be treated as +* a boolean, with a non-zero value indicating that the capability is supported. +* +* For Maxwell &tm; or newer fully supported devices. +* +* @param vgpuTypeId Handle to vGPU type +* @param capability Specifies the \a nvmlVgpuCapability_t to be queried +* @param capResult A boolean for the queried capability indicating that feature is supported +* +* @return +* - \ref NVML_SUCCESS successful completion +* - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized +* - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuTypeId is invalid, or \a capability is invalid, or \a capResult is NULL +* - \ref NVML_ERROR_UNKNOWN on any unexpected error +*/ +nvmlReturn_t DECLDIR nvmlVgpuTypeGetCapabilities(nvmlVgpuTypeId_t vgpuTypeId, nvmlVgpuCapability_t capability, unsigned int *capResult); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvml vGPU Migration + * This chapter describes operations that are associated with vGPU Migration. + * @{ + */ +/***************************************************************************************************/ + +/** + * Structure representing range of vGPU versions. + */ +typedef struct nvmlVgpuVersion_st +{ + unsigned int minVersion; //!< Minimum vGPU version. + unsigned int maxVersion; //!< Maximum vGPU version. +} nvmlVgpuVersion_t; + +/** + * vGPU metadata structure. + */ +typedef struct nvmlVgpuMetadata_st +{ + unsigned int version; //!< Current version of the structure + unsigned int revision; //!< Current revision of the structure + nvmlVgpuGuestInfoState_t guestInfoState; //!< Current state of Guest-dependent fields + char guestDriverVersion[NVML_SYSTEM_DRIVER_VERSION_BUFFER_SIZE]; //!< Version of driver installed in guest + char hostDriverVersion[NVML_SYSTEM_DRIVER_VERSION_BUFFER_SIZE]; //!< Version of driver installed in host + unsigned int reserved[6]; //!< Reserved for internal use + unsigned int vgpuVirtualizationCaps; //!< vGPU virtualizaion capabilities bitfileld + unsigned int guestVgpuVersion; //!< vGPU version of guest driver + unsigned int opaqueDataSize; //!< Size of opaque data field in bytes + char opaqueData[4]; //!< Opaque data +} nvmlVgpuMetadata_t; + +/** + * Physical GPU metadata structure + */ +typedef struct nvmlVgpuPgpuMetadata_st +{ + unsigned int version; //!< Current version of the structure + unsigned int revision; //!< Current revision of the structure + char hostDriverVersion[NVML_SYSTEM_DRIVER_VERSION_BUFFER_SIZE]; //!< Host driver version + unsigned int pgpuVirtualizationCaps; //!< Pgpu virtualizaion capabilities bitfileld + unsigned int reserved[5]; //!< Reserved for internal use + nvmlVgpuVersion_t hostSupportedVgpuRange; //!< vGPU version range supported by host driver + unsigned int opaqueDataSize; //!< Size of opaque data field in bytes + char opaqueData[4]; //!< Opaque data +} nvmlVgpuPgpuMetadata_t; + +/** + * vGPU VM compatibility codes + */ +typedef enum nvmlVgpuVmCompatibility_enum +{ + NVML_VGPU_VM_COMPATIBILITY_NONE = 0x0, //!< vGPU is not runnable + NVML_VGPU_VM_COMPATIBILITY_COLD = 0x1, //!< vGPU is runnable from a cold / powered-off state (ACPI S5) + NVML_VGPU_VM_COMPATIBILITY_HIBERNATE = 0x2, //!< vGPU is runnable from a hibernated state (ACPI S4) + NVML_VGPU_VM_COMPATIBILITY_SLEEP = 0x4, //!< vGPU is runnable from a sleeped state (ACPI S3) + NVML_VGPU_VM_COMPATIBILITY_LIVE = 0x8 //!< vGPU is runnable from a live/paused (ACPI S0) +} nvmlVgpuVmCompatibility_t; + +/** + * vGPU-pGPU compatibility limit codes + */ +typedef enum nvmlVgpuPgpuCompatibilityLimitCode_enum +{ + NVML_VGPU_COMPATIBILITY_LIMIT_NONE = 0x0, //!< Compatibility is not limited. + NVML_VGPU_COMPATIBILITY_LIMIT_HOST_DRIVER = 0x1, //!< ompatibility is limited by host driver version. + NVML_VGPU_COMPATIBILITY_LIMIT_GUEST_DRIVER = 0x2, //!< Compatibility is limited by guest driver version. + NVML_VGPU_COMPATIBILITY_LIMIT_GPU = 0x4, //!< Compatibility is limited by GPU hardware. + NVML_VGPU_COMPATIBILITY_LIMIT_OTHER = 0x80000000 //!< Compatibility is limited by an undefined factor. +} nvmlVgpuPgpuCompatibilityLimitCode_t; + +/** + * vGPU-pGPU compatibility structure + */ +typedef struct nvmlVgpuPgpuCompatibility_st +{ + nvmlVgpuVmCompatibility_t vgpuVmCompatibility; //!< Compatibility of vGPU VM. See \ref nvmlVgpuVmCompatibility_t + nvmlVgpuPgpuCompatibilityLimitCode_t compatibilityLimitCode; //!< Limiting factor for vGPU-pGPU compatibility. See \ref nvmlVgpuPgpuCompatibilityLimitCode_t +} nvmlVgpuPgpuCompatibility_t; + +/** + * Returns vGPU metadata structure for a running vGPU. The structure contains information about the vGPU and its associated VM + * such as the currently installed NVIDIA guest driver version, together with host driver version and an opaque data section + * containing internal state. + * + * nvmlVgpuInstanceGetMetadata() may be called at any time for a vGPU instance. Some fields in the returned structure are + * dependent on information obtained from the guest VM, which may not yet have reached a state where that information + * is available. The current state of these dependent fields is reflected in the info structure's \ref nvmlVgpuGuestInfoState_t field. + * + * The VMM may choose to read and save the vGPU's VM info as persistent metadata associated with the VM, and provide + * it to Virtual GPU Manager when creating a vGPU for subsequent instances of the VM. + * + * The caller passes in a buffer via \a vgpuMetadata, with the size of the buffer in \a bufferSize. If the vGPU Metadata structure + * is too large to fit in the supplied buffer, the function returns NVML_ERROR_INSUFFICIENT_SIZE with the size needed + * in \a bufferSize. + * + * @param vgpuInstance vGPU instance handle + * @param vgpuMetadata Pointer to caller-supplied buffer into which vGPU metadata is written + * @param bufferSize Size of vgpuMetadata buffer + * + * @return + * - \ref NVML_SUCCESS vGPU metadata structure was successfully returned + * - \ref NVML_ERROR_INSUFFICIENT_SIZE vgpuMetadata buffer is too small, required size is returned in \a bufferSize + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a bufferSize is NULL or \a vgpuInstance is 0; if \a vgpuMetadata is NULL and the value of \a bufferSize is not 0. + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetMetadata(nvmlVgpuInstance_t vgpuInstance, nvmlVgpuMetadata_t *vgpuMetadata, unsigned int *bufferSize); + +/** + * Returns a vGPU metadata structure for the physical GPU indicated by \a device. The structure contains information about + * the GPU and the currently installed NVIDIA host driver version that's controlling it, together with an opaque data section + * containing internal state. + * + * The caller passes in a buffer via \a pgpuMetadata, with the size of the buffer in \a bufferSize. If the \a pgpuMetadata + * structure is too large to fit in the supplied buffer, the function returns NVML_ERROR_INSUFFICIENT_SIZE with the size needed + * in \a bufferSize. + * + * @param device The identifier of the target device + * @param pgpuMetadata Pointer to caller-supplied buffer into which \a pgpuMetadata is written + * @param bufferSize Pointer to size of \a pgpuMetadata buffer + * + * @return + * - \ref NVML_SUCCESS GPU metadata structure was successfully returned + * - \ref NVML_ERROR_INSUFFICIENT_SIZE pgpuMetadata buffer is too small, required size is returned in \a bufferSize + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a bufferSize is NULL or \a device is invalid; if \a pgpuMetadata is NULL and the value of \a bufferSize is not 0. + * - \ref NVML_ERROR_NOT_SUPPORTED vGPU is not supported by the system + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetVgpuMetadata(nvmlDevice_t device, nvmlVgpuPgpuMetadata_t *pgpuMetadata, unsigned int *bufferSize); + +/** + * Takes a vGPU instance metadata structure read from \ref nvmlVgpuInstanceGetMetadata(), and a vGPU metadata structure for a + * physical GPU read from \ref nvmlDeviceGetVgpuMetadata(), and returns compatibility information of the vGPU instance and the + * physical GPU. + * + * The caller passes in a buffer via \a compatibilityInfo, into which a compatibility information structure is written. The + * structure defines the states in which the vGPU / VM may be booted on the physical GPU. If the vGPU / VM compatibility + * with the physical GPU is limited, a limit code indicates the factor limiting compability. + * (see \ref nvmlVgpuPgpuCompatibilityLimitCode_t for details). + * + * Note: vGPU compatibility does not take into account dynamic capacity conditions that may limit a system's ability to + * boot a given vGPU or associated VM. + * + * @param vgpuMetadata Pointer to caller-supplied vGPU metadata structure + * @param pgpuMetadata Pointer to caller-supplied GPU metadata structure + * @param compatibilityInfo Pointer to caller-supplied buffer to hold compatibility info + * + * @return + * - \ref NVML_SUCCESS vGPU metadata structure was successfully returned + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuMetadata or \a pgpuMetadata or \a bufferSize are NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlGetVgpuCompatibility(nvmlVgpuMetadata_t *vgpuMetadata, nvmlVgpuPgpuMetadata_t *pgpuMetadata, nvmlVgpuPgpuCompatibility_t *compatibilityInfo); + +/** + * Returns the properties of the physical GPU indicated by the device in an ascii-encoded string format. + * + * The caller passes in a buffer via \a pgpuMetadata, with the size of the buffer in \a bufferSize. If the + * string is too large to fit in the supplied buffer, the function returns NVML_ERROR_INSUFFICIENT_SIZE with the size needed + * in \a bufferSize. + * + * @param device The identifier of the target device + * @param pgpuMetadata Pointer to caller-supplied buffer into which \a pgpuMetadata is written + * @param bufferSize Pointer to size of \a pgpuMetadata buffer + * + * @return + * - \ref NVML_SUCCESS GPU metadata structure was successfully returned + * - \ref NVML_ERROR_INSUFFICIENT_SIZE \a pgpuMetadata buffer is too small, required size is returned in \a bufferSize + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a bufferSize is NULL or \a device is invalid; if \a pgpuMetadata is NULL and the value of \a bufferSize is not 0. + * - \ref NVML_ERROR_NOT_SUPPORTED if vGPU is not supported by the system + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetPgpuMetadataString(nvmlDevice_t device, char *pgpuMetadata, unsigned int *bufferSize); + +/** + * Returns the vGPU Software scheduler logs. + * \a pSchedulerLog points to a caller-allocated structure to contain the logs. The number of elements returned will + * never exceed \a NVML_SCHEDULER_SW_MAX_LOG_ENTRIES. + * + * To get the entire logs, call the function atleast 5 times a second. + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target \a device + * @param pSchedulerLog Reference in which \a pSchedulerLog is written + * + * @return + * - \ref NVML_SUCCESS vGPU scheduler logs were successfully obtained + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a pSchedulerLog is NULL or \a device is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED The API is not supported in current state or \a device not in vGPU host mode + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetVgpuSchedulerLog(nvmlDevice_t device, nvmlVgpuSchedulerLog_t *pSchedulerLog); + +/** + * Returns the vGPU scheduler state. + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target \a device + * @param pSchedulerState Reference in which \a pSchedulerState is returned + * + * @return + * - \ref NVML_SUCCESS vGPU scheduler state is successfully obtained + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a pSchedulerState is NULL or \a device is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED The API is not supported in current state or \a device not in vGPU host mode + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetVgpuSchedulerState(nvmlDevice_t device, nvmlVgpuSchedulerGetState_t *pSchedulerState); + +/** + * Sets the vGPU scheduler state. + * + * For Pascal &tm; or newer fully supported devices. + * + * The scheduler state change won’t persist across module load/unload. + * Scheduler state and params will be allowed to set only when no VM is running. + * In \a nvmlVgpuSchedulerSetState_t, IFF enableARRMode=1 then + * provide avgFactorForARR and frequency as input. If enableARRMode is disabled + * then provide timeslice as input. + * + * @param device The identifier of the target \a device + * @param pSchedulerState vGPU \a pSchedulerState to set + * + * @return + * - \ref NVML_SUCCESS vGPU scheduler state has been successfully set + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a pSchedulerState is NULL or \a device is invalid + * - \ref NVML_ERROR_RESET_REQUIRED if setting \a pSchedulerState failed with fatal error, + * reboot is required to overcome from this error. + * - \ref NVML_ERROR_NOT_SUPPORTED The API is not supported in current state or \a device not in vGPU host mode + * or if any vGPU instance currently exists on the \a device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceSetVgpuSchedulerState(nvmlDevice_t device, nvmlVgpuSchedulerSetState_t *pSchedulerState); + +/** + * Returns the vGPU scheduler capabilities. + * The list of supported vGPU schedulers returned in \a nvmlVgpuSchedulerCapabilities_t is from + * the NVML_VGPU_SCHEDULER_POLICY_*. This list enumerates the supported scheduler policies + * if the engine is Graphics type. + * The other values in \a nvmlVgpuSchedulerCapabilities_t are also applicable if the engine is + * Graphics type. For other engine types, it is BEST EFFORT policy. + * If ARR is supported and enabled, scheduling frequency and averaging factor are applicable + * else timeSlice is applicable. + * + * For Pascal &tm; or newer fully supported devices. + * + * @param device The identifier of the target \a device + * @param pCapabilities Reference in which \a pCapabilities is written + * + * @return + * - \ref NVML_SUCCESS vGPU scheduler capabilities were successfully obtained + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a pCapabilities is NULL or \a device is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED The API is not supported in current state or \a device not in vGPU host mode + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetVgpuSchedulerCapabilities(nvmlDevice_t device, nvmlVgpuSchedulerCapabilities_t *pCapabilities); + +/* + * Virtual GPU (vGPU) version + * + * The NVIDIA vGPU Manager and the guest drivers are tagged with a range of supported vGPU versions. This determines the range of NVIDIA guest driver versions that + * are compatible for vGPU feature support with a given NVIDIA vGPU Manager. For vGPU feature support, the range of supported versions for the NVIDIA vGPU Manager + * and the guest driver must overlap. Otherwise, the guest driver fails to load in the VM. + * + * When the NVIDIA guest driver loads, either when the VM is booted or when the driver is installed or upgraded, a negotiation occurs between the guest driver + * and the NVIDIA vGPU Manager to select the highest mutually compatible vGPU version. The negotiated vGPU version stays the same across VM migration. + */ + +/** + * Query the ranges of supported vGPU versions. + * + * This function gets the linear range of supported vGPU versions that is preset for the NVIDIA vGPU Manager and the range set by an administrator. + * If the preset range has not been overridden by \ref nvmlSetVgpuVersion, both ranges are the same. + * + * The caller passes pointers to the following \ref nvmlVgpuVersion_t structures, into which the NVIDIA vGPU Manager writes the ranges: + * 1. \a supported structure that represents the preset range of vGPU versions supported by the NVIDIA vGPU Manager. + * 2. \a current structure that represents the range of supported vGPU versions set by an administrator. By default, this range is the same as the preset range. + * + * @param supported Pointer to the structure in which the preset range of vGPU versions supported by the NVIDIA vGPU Manager is written + * @param current Pointer to the structure in which the range of supported vGPU versions set by an administrator is written + * + * @return + * - \ref NVML_SUCCESS The vGPU version range structures were successfully obtained. + * - \ref NVML_ERROR_NOT_SUPPORTED The API is not supported. + * - \ref NVML_ERROR_INVALID_ARGUMENT The \a supported parameter or the \a current parameter is NULL. + * - \ref NVML_ERROR_UNKNOWN An error occurred while the data was being fetched. + */ +nvmlReturn_t DECLDIR nvmlGetVgpuVersion(nvmlVgpuVersion_t *supported, nvmlVgpuVersion_t *current); + +/** + * Override the preset range of vGPU versions supported by the NVIDIA vGPU Manager with a range set by an administrator. + * + * This function configures the NVIDIA vGPU Manager with a range of supported vGPU versions set by an administrator. This range must be a subset of the + * preset range that the NVIDIA vGPU Manager supports. The custom range set by an administrator takes precedence over the preset range and is advertised to + * the guest VM for negotiating the vGPU version. See \ref nvmlGetVgpuVersion for details of how to query the preset range of versions supported. + * + * This function takes a pointer to vGPU version range structure \ref nvmlVgpuVersion_t as input to override the preset vGPU version range that the NVIDIA vGPU Manager supports. + * + * After host system reboot or driver reload, the range of supported versions reverts to the range that is preset for the NVIDIA vGPU Manager. + * + * @note 1. The range set by the administrator must be a subset of the preset range that the NVIDIA vGPU Manager supports. Otherwise, an error is returned. + * 2. If the range of supported guest driver versions does not overlap the range set by the administrator, the guest driver fails to load. + * 3. If the range of supported guest driver versions overlaps the range set by the administrator, the guest driver will load with a negotiated + * vGPU version that is the maximum value in the overlapping range. + * 4. No VMs must be running on the host when this function is called. If a VM is running on the host, the call to this function fails. + * + * @param vgpuVersion Pointer to a caller-supplied range of supported vGPU versions. + * + * @return + * - \ref NVML_SUCCESS The preset range of supported vGPU versions was successfully overridden. + * - \ref NVML_ERROR_NOT_SUPPORTED The API is not supported. + * - \ref NVML_ERROR_IN_USE The range was not overridden because a VM is running on the host. + * - \ref NVML_ERROR_INVALID_ARGUMENT The \a vgpuVersion parameter specifies a range that is outside the range supported by the NVIDIA vGPU Manager or if \a vgpuVersion is NULL. + */ +nvmlReturn_t DECLDIR nvmlSetVgpuVersion(nvmlVgpuVersion_t *vgpuVersion); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlUtil vGPU Utilization and Accounting + * This chapter describes operations that are associated with vGPU Utilization and Accounting. + * @{ + */ +/***************************************************************************************************/ + +/** + * Retrieves current utilization for vGPUs on a physical GPU (device). + * + * For Kepler &tm; or newer fully supported devices. + * + * Reads recent utilization of GPU SM (3D/Compute), framebuffer, video encoder, and video decoder for vGPU instances running + * on a device. Utilization values are returned as an array of utilization sample structures in the caller-supplied buffer + * pointed at by \a utilizationSamples. One utilization sample structure is returned per vGPU instance, and includes the + * CPU timestamp at which the samples were recorded. Individual utilization values are returned as "unsigned int" values + * in nvmlValue_t unions. The function sets the caller-supplied \a sampleValType to NVML_VALUE_TYPE_UNSIGNED_INT to + * indicate the returned value type. + * + * To read utilization values, first determine the size of buffer required to hold the samples by invoking the function with + * \a utilizationSamples set to NULL. The function will return NVML_ERROR_INSUFFICIENT_SIZE, with the current vGPU instance + * count in \a vgpuInstanceSamplesCount, or NVML_SUCCESS if the current vGPU instance count is zero. The caller should allocate + * a buffer of size vgpuInstanceSamplesCount * sizeof(nvmlVgpuInstanceUtilizationSample_t). Invoke the function again with + * the allocated buffer passed in \a utilizationSamples, and \a vgpuInstanceSamplesCount set to the number of entries the + * buffer is sized for. + * + * On successful return, the function updates \a vgpuInstanceSampleCount with the number of vGPU utilization sample + * structures that were actually written. This may differ from a previously read value as vGPU instances are created or + * destroyed. + * + * lastSeenTimeStamp represents the CPU timestamp in microseconds at which utilization samples were last read. Set it to 0 + * to read utilization based on all the samples maintained by the driver's internal sample buffer. Set lastSeenTimeStamp + * to a timeStamp retrieved from a previous query to read utilization since the previous query. + * + * @param device The identifier for the target device + * @param lastSeenTimeStamp Return only samples with timestamp greater than lastSeenTimeStamp. + * @param sampleValType Pointer to caller-supplied buffer to hold the type of returned sample values + * @param vgpuInstanceSamplesCount Pointer to caller-supplied array size, and returns number of vGPU instances + * @param utilizationSamples Pointer to caller-supplied buffer in which vGPU utilization samples are returned + + * @return + * - \ref NVML_SUCCESS if utilization samples are successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a vgpuInstanceSamplesCount or \a sampleValType is + * NULL, or a sample count of 0 is passed with a non-NULL \a utilizationSamples + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if supplied \a vgpuInstanceSamplesCount is too small to return samples for all + * vGPU instances currently executing on the device + * - \ref NVML_ERROR_NOT_SUPPORTED if vGPU is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_NOT_FOUND if sample entries are not found + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetVgpuUtilization(nvmlDevice_t device, unsigned long long lastSeenTimeStamp, + nvmlValueType_t *sampleValType, unsigned int *vgpuInstanceSamplesCount, + nvmlVgpuInstanceUtilizationSample_t *utilizationSamples); + +/** + * Retrieves current utilization for processes running on vGPUs on a physical GPU (device). + * + * For Maxwell &tm; or newer fully supported devices. + * + * Reads recent utilization of GPU SM (3D/Compute), framebuffer, video encoder, and video decoder for processes running on + * vGPU instances active on a device. Utilization values are returned as an array of utilization sample structures in the + * caller-supplied buffer pointed at by \a utilizationSamples. One utilization sample structure is returned per process running + * on vGPU instances, that had some non-zero utilization during the last sample period. It includes the CPU timestamp at which + * the samples were recorded. Individual utilization values are returned as "unsigned int" values. + * + * To read utilization values, first determine the size of buffer required to hold the samples by invoking the function with + * \a utilizationSamples set to NULL. The function will return NVML_ERROR_INSUFFICIENT_SIZE, with the current vGPU instance + * count in \a vgpuProcessSamplesCount. The caller should allocate a buffer of size + * vgpuProcessSamplesCount * sizeof(nvmlVgpuProcessUtilizationSample_t). Invoke the function again with + * the allocated buffer passed in \a utilizationSamples, and \a vgpuProcessSamplesCount set to the number of entries the + * buffer is sized for. + * + * On successful return, the function updates \a vgpuSubProcessSampleCount with the number of vGPU sub process utilization sample + * structures that were actually written. This may differ from a previously read value depending on the number of processes that are active + * in any given sample period. + * + * lastSeenTimeStamp represents the CPU timestamp in microseconds at which utilization samples were last read. Set it to 0 + * to read utilization based on all the samples maintained by the driver's internal sample buffer. Set lastSeenTimeStamp + * to a timeStamp retrieved from a previous query to read utilization since the previous query. + * + * @param device The identifier for the target device + * @param lastSeenTimeStamp Return only samples with timestamp greater than lastSeenTimeStamp. + * @param vgpuProcessSamplesCount Pointer to caller-supplied array size, and returns number of processes running on vGPU instances + * @param utilizationSamples Pointer to caller-supplied buffer in which vGPU sub process utilization samples are returned + + * @return + * - \ref NVML_SUCCESS if utilization samples are successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid, \a vgpuProcessSamplesCount or a sample count of 0 is + * passed with a non-NULL \a utilizationSamples + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if supplied \a vgpuProcessSamplesCount is too small to return samples for all + * vGPU instances currently executing on the device + * - \ref NVML_ERROR_NOT_SUPPORTED if vGPU is not supported by the device + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_NOT_FOUND if sample entries are not found + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetVgpuProcessUtilization(nvmlDevice_t device, unsigned long long lastSeenTimeStamp, + unsigned int *vgpuProcessSamplesCount, + nvmlVgpuProcessUtilizationSample_t *utilizationSamples); +/** + * Queries the state of per process accounting mode on vGPU. + * + * For Maxwell &tm; or newer fully supported devices. + * + * @param vgpuInstance The identifier of the target vGPU instance + * @param mode Reference in which to return the current accounting mode + * + * @return + * - \ref NVML_SUCCESS if the mode has been successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a mode is NULL + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_NOT_SUPPORTED if the vGPU doesn't support this feature + * - \ref NVML_ERROR_DRIVER_NOT_LOADED if NVIDIA driver is not running on the vGPU instance + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetAccountingMode(nvmlVgpuInstance_t vgpuInstance, nvmlEnableState_t *mode); + +/** + * Queries list of processes running on vGPU that can be queried for accounting stats. The list of processes + * returned can be in running or terminated state. + * + * For Maxwell &tm; or newer fully supported devices. + * + * To just query the maximum number of processes that can be queried, call this function with *count = 0 and + * pids=NULL. The return code will be NVML_ERROR_INSUFFICIENT_SIZE, or NVML_SUCCESS if list is empty. + * + * For more details see \ref nvmlVgpuInstanceGetAccountingStats. + * + * @note In case of PID collision some processes might not be accessible before the circular buffer is full. + * + * @param vgpuInstance The identifier of the target vGPU instance + * @param count Reference in which to provide the \a pids array size, and + * to return the number of elements ready to be queried + * @param pids Reference in which to return list of process ids + * + * @return + * - \ref NVML_SUCCESS if pids were successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a count is NULL + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_NOT_SUPPORTED if the vGPU doesn't support this feature or accounting mode is disabled + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if \a count is too small (\a count is set to expected value) + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + * + * @see nvmlVgpuInstanceGetAccountingPids + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetAccountingPids(nvmlVgpuInstance_t vgpuInstance, unsigned int *count, unsigned int *pids); + +/** + * Queries process's accounting stats. + * + * For Maxwell &tm; or newer fully supported devices. + * + * Accounting stats capture GPU utilization and other statistics across the lifetime of a process, and + * can be queried during life time of the process or after its termination. + * The time field in \ref nvmlAccountingStats_t is reported as 0 during the lifetime of the process and + * updated to actual running time after its termination. + * Accounting stats are kept in a circular buffer, newly created processes overwrite information about old + * processes. + * + * See \ref nvmlAccountingStats_t for description of each returned metric. + * List of processes that can be queried can be retrieved from \ref nvmlVgpuInstanceGetAccountingPids. + * + * @note Accounting Mode needs to be on. See \ref nvmlVgpuInstanceGetAccountingMode. + * @note Only compute and graphics applications stats can be queried. Monitoring applications stats can't be + * queried since they don't contribute to GPU utilization. + * @note In case of pid collision stats of only the latest process (that terminated last) will be reported + * + * @param vgpuInstance The identifier of the target vGPU instance + * @param pid Process Id of the target process to query stats for + * @param stats Reference in which to return the process's accounting stats + * + * @return + * - \ref NVML_SUCCESS if stats have been successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a stats is NULL + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * or \a stats is not found + * - \ref NVML_ERROR_NOT_SUPPORTED if the vGPU doesn't support this feature or accounting mode is disabled + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetAccountingStats(nvmlVgpuInstance_t vgpuInstance, unsigned int pid, nvmlAccountingStats_t *stats); + +/** + * Clears accounting information of the vGPU instance that have already terminated. + * + * For Maxwell &tm; or newer fully supported devices. + * Requires root/admin permissions. + * + * @note Accounting Mode needs to be on. See \ref nvmlVgpuInstanceGetAccountingMode. + * @note Only compute and graphics applications stats are reported and can be cleared since monitoring applications + * stats don't contribute to GPU utilization. + * + * @param vgpuInstance The identifier of the target vGPU instance + * + * @return + * - \ref NVML_SUCCESS if accounting information has been cleared + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is invalid + * - \ref NVML_ERROR_NO_PERMISSION if the user doesn't have permission to perform this operation + * - \ref NVML_ERROR_NOT_SUPPORTED if the vGPU doesn't support this feature or accounting mode is disabled + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceClearAccountingPids(nvmlVgpuInstance_t vgpuInstance); + +/** + * Query the license information of the vGPU instance. + * + * For Maxwell &tm; or newer fully supported devices. + * + * @param vgpuInstance Identifier of the target vGPU instance + * @param licenseInfo Pointer to vGPU license information structure + * + * @return + * - \ref NVML_SUCCESS if information is successfully retrieved + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a vgpuInstance is 0, or \a licenseInfo is NULL + * - \ref NVML_ERROR_NOT_FOUND if \a vgpuInstance does not match a valid active vGPU instance on the system + * - \ref NVML_ERROR_DRIVER_NOT_LOADED if NVIDIA driver is not running on the vGPU instance + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetLicenseInfo_v2(nvmlVgpuInstance_t vgpuInstance, nvmlVgpuLicenseInfo_t *licenseInfo); +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlExcludedGpuQueries Excluded GPU Queries + * This chapter describes NVML operations that are associated with excluded GPUs. + * @{ + */ +/***************************************************************************************************/ + +/** + * Excluded GPU device information + **/ +typedef struct nvmlExcludedDeviceInfo_st +{ + nvmlPciInfo_t pciInfo; //!< The PCI information for the excluded GPU + char uuid[NVML_DEVICE_UUID_BUFFER_SIZE]; //!< The ASCII string UUID for the excluded GPU +} nvmlExcludedDeviceInfo_t; + + /** + * Retrieves the number of excluded GPU devices in the system. + * + * For all products. + * + * @param deviceCount Reference in which to return the number of excluded devices + * + * @return + * - \ref NVML_SUCCESS if \a deviceCount has been set + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a deviceCount is NULL + */ +nvmlReturn_t DECLDIR nvmlGetExcludedDeviceCount(unsigned int *deviceCount); + +/** + * Acquire the device information for an excluded GPU device, based on its index. + * + * For all products. + * + * Valid indices are derived from the \a deviceCount returned by + * \ref nvmlGetExcludedDeviceCount(). For example, if \a deviceCount is 2 the valid indices + * are 0 and 1, corresponding to GPU 0 and GPU 1. + * + * @param index The index of the target GPU, >= 0 and < \a deviceCount + * @param info Reference in which to return the device information + * + * @return + * - \ref NVML_SUCCESS if \a device has been set + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a index is invalid or \a info is NULL + * + * @see nvmlGetExcludedDeviceCount + */ +nvmlReturn_t DECLDIR nvmlGetExcludedDeviceInfoByIndex(unsigned int index, nvmlExcludedDeviceInfo_t *info); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup nvmlMultiInstanceGPU Multi Instance GPU Management + * This chapter describes NVML operations that are associated with Multi Instance GPU management. + * @{ + */ +/***************************************************************************************************/ + +/** + * Disable Multi Instance GPU mode. + */ +#define NVML_DEVICE_MIG_DISABLE 0x0 + +/** + * Enable Multi Instance GPU mode. + */ +#define NVML_DEVICE_MIG_ENABLE 0x1 + +/** + * GPU instance profiles. + * + * These macros should be passed to \ref nvmlDeviceGetGpuInstanceProfileInfo to retrieve the + * detailed information about a GPU instance such as profile ID, engine counts. + */ +#define NVML_GPU_INSTANCE_PROFILE_1_SLICE 0x0 +#define NVML_GPU_INSTANCE_PROFILE_2_SLICE 0x1 +#define NVML_GPU_INSTANCE_PROFILE_3_SLICE 0x2 +#define NVML_GPU_INSTANCE_PROFILE_4_SLICE 0x3 +#define NVML_GPU_INSTANCE_PROFILE_7_SLICE 0x4 +#define NVML_GPU_INSTANCE_PROFILE_8_SLICE 0x5 +#define NVML_GPU_INSTANCE_PROFILE_6_SLICE 0x6 +#define NVML_GPU_INSTANCE_PROFILE_1_SLICE_REV1 0x7 +#define NVML_GPU_INSTANCE_PROFILE_2_SLICE_REV1 0x8 +#define NVML_GPU_INSTANCE_PROFILE_1_SLICE_REV2 0x9 +#define NVML_GPU_INSTANCE_PROFILE_COUNT 0xA + +typedef struct nvmlGpuInstancePlacement_st +{ + unsigned int start; //!< Index of first occupied memory slice + unsigned int size; //!< Number of memory slices occupied +} nvmlGpuInstancePlacement_t; + +/** + * GPU instance profile information. + */ +typedef struct nvmlGpuInstanceProfileInfo_st +{ + unsigned int id; //!< Unique profile ID within the device + unsigned int isP2pSupported; //!< Peer-to-Peer support + unsigned int sliceCount; //!< GPU Slice count + unsigned int instanceCount; //!< GPU instance count + unsigned int multiprocessorCount; //!< Streaming Multiprocessor count + unsigned int copyEngineCount; //!< Copy Engine count + unsigned int decoderCount; //!< Decoder Engine count + unsigned int encoderCount; //!< Encoder Engine count + unsigned int jpegCount; //!< JPEG Engine count + unsigned int ofaCount; //!< OFA Engine count + unsigned long long memorySizeMB; //!< Memory size in MBytes +} nvmlGpuInstanceProfileInfo_t; + +/** + * GPU instance profile information (v2). + * + * Version 2 adds the \ref nvmlGpuInstanceProfileInfo_v2_t.version field + * to the start of the structure, and the \ref nvmlGpuInstanceProfileInfo_v2_t.name + * field to the end. This structure is not backwards-compatible with + * \ref nvmlGpuInstanceProfileInfo_t. + */ +typedef struct nvmlGpuInstanceProfileInfo_v2_st +{ + unsigned int version; //!< Structure version identifier (set to \ref nvmlGpuInstanceProfileInfo_v2) + unsigned int id; //!< Unique profile ID within the device + unsigned int isP2pSupported; //!< Peer-to-Peer support + unsigned int sliceCount; //!< GPU Slice count + unsigned int instanceCount; //!< GPU instance count + unsigned int multiprocessorCount; //!< Streaming Multiprocessor count + unsigned int copyEngineCount; //!< Copy Engine count + unsigned int decoderCount; //!< Decoder Engine count + unsigned int encoderCount; //!< Encoder Engine count + unsigned int jpegCount; //!< JPEG Engine count + unsigned int ofaCount; //!< OFA Engine count + unsigned long long memorySizeMB; //!< Memory size in MBytes + char name[NVML_DEVICE_NAME_V2_BUFFER_SIZE]; //!< Profile name +} nvmlGpuInstanceProfileInfo_v2_t; + +/** + * Version identifier value for \ref nvmlGpuInstanceProfileInfo_v2_t.version. + */ +#define nvmlGpuInstanceProfileInfo_v2 NVML_STRUCT_VERSION(GpuInstanceProfileInfo, 2) + +typedef struct nvmlGpuInstanceInfo_st +{ + nvmlDevice_t device; //!< Parent device + unsigned int id; //!< Unique instance ID within the device + unsigned int profileId; //!< Unique profile ID within the device + nvmlGpuInstancePlacement_t placement; //!< Placement for this instance +} nvmlGpuInstanceInfo_t; + +typedef struct nvmlGpuInstance_st* nvmlGpuInstance_t; + +/** + * Compute instance profiles. + * + * These macros should be passed to \ref nvmlGpuInstanceGetComputeInstanceProfileInfo to retrieve the + * detailed information about a compute instance such as profile ID, engine counts + */ +#define NVML_COMPUTE_INSTANCE_PROFILE_1_SLICE 0x0 +#define NVML_COMPUTE_INSTANCE_PROFILE_2_SLICE 0x1 +#define NVML_COMPUTE_INSTANCE_PROFILE_3_SLICE 0x2 +#define NVML_COMPUTE_INSTANCE_PROFILE_4_SLICE 0x3 +#define NVML_COMPUTE_INSTANCE_PROFILE_7_SLICE 0x4 +#define NVML_COMPUTE_INSTANCE_PROFILE_8_SLICE 0x5 +#define NVML_COMPUTE_INSTANCE_PROFILE_6_SLICE 0x6 +#define NVML_COMPUTE_INSTANCE_PROFILE_1_SLICE_REV1 0x7 +#define NVML_COMPUTE_INSTANCE_PROFILE_COUNT 0x8 + +#define NVML_COMPUTE_INSTANCE_ENGINE_PROFILE_SHARED 0x0 //!< All the engines except multiprocessors would be shared +#define NVML_COMPUTE_INSTANCE_ENGINE_PROFILE_COUNT 0x1 + +typedef struct nvmlComputeInstancePlacement_st +{ + unsigned int start; //!< Index of first occupied compute slice + unsigned int size; //!< Number of compute slices occupied +} nvmlComputeInstancePlacement_t; + +/** + * Compute instance profile information. + */ +typedef struct nvmlComputeInstanceProfileInfo_st +{ + unsigned int id; //!< Unique profile ID within the GPU instance + unsigned int sliceCount; //!< GPU Slice count + unsigned int instanceCount; //!< Compute instance count + unsigned int multiprocessorCount; //!< Streaming Multiprocessor count + unsigned int sharedCopyEngineCount; //!< Shared Copy Engine count + unsigned int sharedDecoderCount; //!< Shared Decoder Engine count + unsigned int sharedEncoderCount; //!< Shared Encoder Engine count + unsigned int sharedJpegCount; //!< Shared JPEG Engine count + unsigned int sharedOfaCount; //!< Shared OFA Engine count +} nvmlComputeInstanceProfileInfo_t; + +/** + * Compute instance profile information (v2). + * + * Version 2 adds the \ref nvmlComputeInstanceProfileInfo_v2_t.version field + * to the start of the structure, and the \ref nvmlComputeInstanceProfileInfo_v2_t.name + * field to the end. This structure is not backwards-compatible with + * \ref nvmlComputeInstanceProfileInfo_t. + */ +typedef struct nvmlComputeInstanceProfileInfo_v2_st +{ + unsigned int version; //!< Structure version identifier (set to \ref nvmlComputeInstanceProfileInfo_v2) + unsigned int id; //!< Unique profile ID within the GPU instance + unsigned int sliceCount; //!< GPU Slice count + unsigned int instanceCount; //!< Compute instance count + unsigned int multiprocessorCount; //!< Streaming Multiprocessor count + unsigned int sharedCopyEngineCount; //!< Shared Copy Engine count + unsigned int sharedDecoderCount; //!< Shared Decoder Engine count + unsigned int sharedEncoderCount; //!< Shared Encoder Engine count + unsigned int sharedJpegCount; //!< Shared JPEG Engine count + unsigned int sharedOfaCount; //!< Shared OFA Engine count + char name[NVML_DEVICE_NAME_V2_BUFFER_SIZE]; //!< Profile name +} nvmlComputeInstanceProfileInfo_v2_t; + +/** + * Version identifier value for \ref nvmlComputeInstanceProfileInfo_v2_t.version. + */ +#define nvmlComputeInstanceProfileInfo_v2 NVML_STRUCT_VERSION(ComputeInstanceProfileInfo, 2) + +typedef struct nvmlComputeInstanceInfo_st +{ + nvmlDevice_t device; //!< Parent device + nvmlGpuInstance_t gpuInstance; //!< Parent GPU instance + unsigned int id; //!< Unique instance ID within the GPU instance + unsigned int profileId; //!< Unique profile ID within the GPU instance + nvmlComputeInstancePlacement_t placement; //!< Placement for this instance within the GPU instance's compute slice range {0, sliceCount} +} nvmlComputeInstanceInfo_t; + +typedef struct nvmlComputeInstance_st* nvmlComputeInstance_t; + +/** + * Set MIG mode for the device. + * + * For Ampere &tm; or newer fully supported devices. + * Requires root user. + * + * This mode determines whether a GPU instance can be created. + * + * This API may unbind or reset the device to activate the requested mode. Thus, the attributes associated with the + * device, such as minor number, might change. The caller of this API is expected to query such attributes again. + * + * On certain platforms like pass-through virtualization, where reset functionality may not be exposed directly, VM + * reboot is required. \a activationStatus would return \ref NVML_ERROR_RESET_REQUIRED for such cases. + * + * \a activationStatus would return the appropriate error code upon unsuccessful activation. For example, if device + * unbind fails because the device isn't idle, \ref NVML_ERROR_IN_USE would be returned. The caller of this API + * is expected to idle the device and retry setting the \a mode. + * + * @note On Windows, only disabling MIG mode is supported. \a activationStatus would return \ref + * NVML_ERROR_NOT_SUPPORTED as GPU reset is not supported on Windows through this API. + * + * @param device The identifier of the target device + * @param mode The mode to be set, \ref NVML_DEVICE_MIG_DISABLE or + * \ref NVML_DEVICE_MIG_ENABLE + * @param activationStatus The activationStatus status + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a device,\a mode or \a activationStatus are invalid + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't support MIG mode + */ +nvmlReturn_t DECLDIR nvmlDeviceSetMigMode(nvmlDevice_t device, unsigned int mode, nvmlReturn_t *activationStatus); + +/** + * Get MIG mode for the device. + * + * For Ampere &tm; or newer fully supported devices. + * + * Changing MIG modes may require device unbind or reset. The "pending" MIG mode refers to the target mode following the + * next activation trigger. + * + * @param device The identifier of the target device + * @param currentMode Returns the current mode, \ref NVML_DEVICE_MIG_DISABLE or + * \ref NVML_DEVICE_MIG_ENABLE + * @param pendingMode Returns the pending mode, \ref NVML_DEVICE_MIG_DISABLE or + * \ref NVML_DEVICE_MIG_ENABLE + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a device, \a currentMode or \a pendingMode are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't support MIG mode + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMigMode(nvmlDevice_t device, unsigned int *currentMode, unsigned int *pendingMode); + +/** + * Get GPU instance profile information. + * + * Information provided by this API is immutable throughout the lifetime of a MIG mode. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device The identifier of the target device + * @param profile One of the NVML_GPU_INSTANCE_PROFILE_* + * @param info Returns detailed profile information + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a device, \a profile or \a info are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't have MIG mode enabled or \a profile isn't supported + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGpuInstanceProfileInfo(nvmlDevice_t device, unsigned int profile, + nvmlGpuInstanceProfileInfo_t *info); + +/** + * Versioned wrapper around \ref nvmlDeviceGetGpuInstanceProfileInfo that accepts a versioned + * \ref nvmlGpuInstanceProfileInfo_v2_t or later output structure. + * + * @note The caller must set the \ref nvmlGpuInstanceProfileInfo_v2_t.version field to the + * appropriate version prior to calling this function. For example: + * \code + * nvmlGpuInstanceProfileInfo_v2_t profileInfo = + * { .version = nvmlGpuInstanceProfileInfo_v2 }; + * nvmlReturn_t result = nvmlDeviceGetGpuInstanceProfileInfoV(device, + * profile, + * &profileInfo); + * \endcode + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device The identifier of the target device + * @param profile One of the NVML_GPU_INSTANCE_PROFILE_* + * @param info Returns detailed profile information + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a device, \a profile, \a info, or \a info->version are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't have MIG mode enabled or \a profile isn't supported + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGpuInstanceProfileInfoV(nvmlDevice_t device, unsigned int profile, + nvmlGpuInstanceProfileInfo_v2_t *info); + +/** + * Get GPU instance placements. + * + * A placement represents the location of a GPU instance within a device. This API only returns all the possible + * placements for the given profile. + * A created GPU instance occupies memory slices described by its placement. Creation of new GPU instance will + * fail if there is overlap with the already occupied memory slices. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * @param device The identifier of the target device + * @param profileId The GPU instance profile ID. See \ref nvmlDeviceGetGpuInstanceProfileInfo + * @param placements Returns placements allowed for the profile. Can be NULL to discover number + * of allowed placements for this profile. If non-NULL must be large enough + * to accommodate the placements supported by the profile. + * @param count Returns number of allowed placemenets for the profile. + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a device, \a profileId or \a count are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't have MIG mode enabled or \a profileId isn't supported + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGpuInstancePossiblePlacements_v2(nvmlDevice_t device, unsigned int profileId, + nvmlGpuInstancePlacement_t *placements, + unsigned int *count); + +/** + * Get GPU instance profile capacity. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * @param device The identifier of the target device + * @param profileId The GPU instance profile ID. See \ref nvmlDeviceGetGpuInstanceProfileInfo + * @param count Returns remaining instance count for the profile ID + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a device, \a profileId or \a count are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't have MIG mode enabled or \a profileId isn't supported + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGpuInstanceRemainingCapacity(nvmlDevice_t device, unsigned int profileId, + unsigned int *count); + +/** + * Create GPU instance. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * If the parent device is unbound, reset or the GPU instance is destroyed explicitly, the GPU instance handle would + * become invalid. The GPU instance must be recreated to acquire a valid handle. + * + * @param device The identifier of the target device + * @param profileId The GPU instance profile ID. See \ref nvmlDeviceGetGpuInstanceProfileInfo + * @param gpuInstance Returns the GPU instance handle + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a device, \a profile, \a profileId or \a gpuInstance are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't have MIG mode enabled or in vGPU guest + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + * - \ref NVML_ERROR_INSUFFICIENT_RESOURCES If the requested GPU instance could not be created + */ +nvmlReturn_t DECLDIR nvmlDeviceCreateGpuInstance(nvmlDevice_t device, unsigned int profileId, + nvmlGpuInstance_t *gpuInstance); + +/** + * Create GPU instance with the specified placement. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * If the parent device is unbound, reset or the GPU instance is destroyed explicitly, the GPU instance handle would + * become invalid. The GPU instance must be recreated to acquire a valid handle. + * + * @param device The identifier of the target device + * @param profileId The GPU instance profile ID. See \ref nvmlDeviceGetGpuInstanceProfileInfo + * @param placement The requested placement. See \ref nvmlDeviceGetGpuInstancePossiblePlacements_v2 + * @param gpuInstance Returns the GPU instance handle + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a device, \a profile, \a profileId, \a placement or \a gpuInstance + * are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't have MIG mode enabled or in vGPU guest + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + * - \ref NVML_ERROR_INSUFFICIENT_RESOURCES If the requested GPU instance could not be created + */ +nvmlReturn_t DECLDIR nvmlDeviceCreateGpuInstanceWithPlacement(nvmlDevice_t device, unsigned int profileId, + const nvmlGpuInstancePlacement_t *placement, + nvmlGpuInstance_t *gpuInstance); +/** + * Destroy GPU instance. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * @param gpuInstance The GPU instance handle + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a gpuInstance is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't have MIG mode enabled or in vGPU guest + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + * - \ref NVML_ERROR_IN_USE If the GPU instance is in use. This error would be returned if processes + * (e.g. CUDA application) or compute instances are active on the + * GPU instance. + */ +nvmlReturn_t DECLDIR nvmlGpuInstanceDestroy(nvmlGpuInstance_t gpuInstance); + +/** + * Get GPU instances for given profile ID. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * @param device The identifier of the target device + * @param profileId The GPU instance profile ID. See \ref nvmlDeviceGetGpuInstanceProfileInfo + * @param gpuInstances Returns pre-exiting GPU instances, the buffer must be large enough to + * accommodate the instances supported by the profile. + * See \ref nvmlDeviceGetGpuInstanceProfileInfo + * @param count The count of returned GPU instances + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a device, \a profileId, \a gpuInstances or \a count are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't have MIG mode enabled + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGpuInstances(nvmlDevice_t device, unsigned int profileId, + nvmlGpuInstance_t *gpuInstances, unsigned int *count); + +/** + * Get GPU instances for given instance ID. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * @param device The identifier of the target device + * @param id The GPU instance ID + * @param gpuInstance Returns GPU instance + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a device, \a id or \a gpuInstance are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't have MIG mode enabled + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + * - \ref NVML_ERROR_NOT_FOUND If the GPU instance is not found. + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGpuInstanceById(nvmlDevice_t device, unsigned int id, nvmlGpuInstance_t *gpuInstance); + +/** + * Get GPU instance information. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param gpuInstance The GPU instance handle + * @param info Return GPU instance information + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a gpuInstance or \a info are invalid + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + */ +nvmlReturn_t DECLDIR nvmlGpuInstanceGetInfo(nvmlGpuInstance_t gpuInstance, nvmlGpuInstanceInfo_t *info); + +/** + * Get compute instance profile information. + * + * Information provided by this API is immutable throughout the lifetime of a MIG mode. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param gpuInstance The identifier of the target GPU instance + * @param profile One of the NVML_COMPUTE_INSTANCE_PROFILE_* + * @param engProfile One of the NVML_COMPUTE_INSTANCE_ENGINE_PROFILE_* + * @param info Returns detailed profile information + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a gpuInstance, \a profile, \a engProfile or \a info are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a profile isn't supported + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + */ +nvmlReturn_t DECLDIR nvmlGpuInstanceGetComputeInstanceProfileInfo(nvmlGpuInstance_t gpuInstance, unsigned int profile, + unsigned int engProfile, + nvmlComputeInstanceProfileInfo_t *info); + +/** + * Versioned wrapper around \ref nvmlGpuInstanceGetComputeInstanceProfileInfo that accepts a versioned + * \ref nvmlComputeInstanceProfileInfo_v2_t or later output structure. + * + * @note The caller must set the \ref nvmlGpuInstanceProfileInfo_v2_t.version field to the + * appropriate version prior to calling this function. For example: + * \code + * nvmlComputeInstanceProfileInfo_v2_t profileInfo = + * { .version = nvmlComputeInstanceProfileInfo_v2 }; + * nvmlReturn_t result = nvmlGpuInstanceGetComputeInstanceProfileInfoV(gpuInstance, + * profile, + * engProfile, + * &profileInfo); + * \endcode + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param gpuInstance The identifier of the target GPU instance + * @param profile One of the NVML_COMPUTE_INSTANCE_PROFILE_* + * @param engProfile One of the NVML_COMPUTE_INSTANCE_ENGINE_PROFILE_* + * @param info Returns detailed profile information + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a gpuInstance, \a profile, \a engProfile, \a info, or \a info->version are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a profile isn't supported + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + */ +nvmlReturn_t DECLDIR nvmlGpuInstanceGetComputeInstanceProfileInfoV(nvmlGpuInstance_t gpuInstance, unsigned int profile, + unsigned int engProfile, + nvmlComputeInstanceProfileInfo_v2_t *info); + +/** + * Get compute instance profile capacity. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * @param gpuInstance The identifier of the target GPU instance + * @param profileId The compute instance profile ID. + * See \ref nvmlGpuInstanceGetComputeInstanceProfileInfo + * @param count Returns remaining instance count for the profile ID + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a gpuInstance, \a profileId or \a availableCount are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a profileId isn't supported + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + */ +nvmlReturn_t DECLDIR nvmlGpuInstanceGetComputeInstanceRemainingCapacity(nvmlGpuInstance_t gpuInstance, + unsigned int profileId, unsigned int *count); + +/** + * Get compute instance placements. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * A placement represents the location of a compute instance within a GPU instance. This API only returns all the possible + * placements for the given profile. + * A created compute instance occupies compute slices described by its placement. Creation of new compute instance will + * fail if there is overlap with the already occupied compute slices. + * + * @param gpuInstance The identifier of the target GPU instance + * @param profileId The compute instance profile ID. See \ref nvmlGpuInstanceGetComputeInstanceProfileInfo + * @param placements Returns placements allowed for the profile. Can be NULL to discover number + * of allowed placements for this profile. If non-NULL must be large enough + * to accommodate the placements supported by the profile. + * @param count Returns number of allowed placemenets for the profile. + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a gpuInstance, \a profileId or \a count are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't have MIG mode enabled or \a profileId isn't supported + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + */ +nvmlReturn_t DECLDIR nvmlGpuInstanceGetComputeInstancePossiblePlacements(nvmlGpuInstance_t gpuInstance, + unsigned int profileId, + nvmlComputeInstancePlacement_t *placements, + unsigned int *count); + +/** + * Create compute instance. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * If the parent device is unbound, reset or the parent GPU instance is destroyed or the compute instance is destroyed + * explicitly, the compute instance handle would become invalid. The compute instance must be recreated to acquire + * a valid handle. + * + * @param gpuInstance The identifier of the target GPU instance + * @param profileId The compute instance profile ID. + * See \ref nvmlGpuInstanceGetComputeInstanceProfileInfo + * @param computeInstance Returns the compute instance handle + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a gpuInstance, \a profile, \a profileId or \a computeInstance + * are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a profileId isn't supported + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + * - \ref NVML_ERROR_INSUFFICIENT_RESOURCES If the requested compute instance could not be created + */ +nvmlReturn_t DECLDIR nvmlGpuInstanceCreateComputeInstance(nvmlGpuInstance_t gpuInstance, unsigned int profileId, + nvmlComputeInstance_t *computeInstance); + +/** + * Create compute instance with the specified placement. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * If the parent device is unbound, reset or the parent GPU instance is destroyed or the compute instance is destroyed + * explicitly, the compute instance handle would become invalid. The compute instance must be recreated to acquire + * a valid handle. + * + * @param gpuInstance The identifier of the target GPU instance + * @param profileId The compute instance profile ID. + * See \ref nvmlGpuInstanceGetComputeInstanceProfileInfo + * @param placement The requested placement. See \ref nvmlGpuInstanceGetComputeInstancePossiblePlacements + * @param computeInstance Returns the compute instance handle + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a gpuInstance, \a profile, \a profileId or \a computeInstance + * are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a profileId isn't supported + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + * - \ref NVML_ERROR_INSUFFICIENT_RESOURCES If the requested compute instance could not be created + */ +nvmlReturn_t DECLDIR nvmlGpuInstanceCreateComputeInstanceWithPlacement(nvmlGpuInstance_t gpuInstance, unsigned int profileId, + const nvmlComputeInstancePlacement_t *placement, + nvmlComputeInstance_t *computeInstance); + +/** + * Destroy compute instance. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * @param computeInstance The compute instance handle + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a computeInstance is invalid + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + * - \ref NVML_ERROR_IN_USE If the compute instance is in use. This error would be returned if + * processes (e.g. CUDA application) are active on the compute instance. + */ +nvmlReturn_t DECLDIR nvmlComputeInstanceDestroy(nvmlComputeInstance_t computeInstance); + +/** + * Get compute instances for given profile ID. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * @param gpuInstance The identifier of the target GPU instance + * @param profileId The compute instance profile ID. + * See \ref nvmlGpuInstanceGetComputeInstanceProfileInfo + * @param computeInstances Returns pre-exiting compute instances, the buffer must be large enough to + * accommodate the instances supported by the profile. + * See \ref nvmlGpuInstanceGetComputeInstanceProfileInfo + * @param count The count of returned compute instances + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a gpuInstance, \a profileId, \a computeInstances or \a count + * are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a profileId isn't supported + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + */ +nvmlReturn_t DECLDIR nvmlGpuInstanceGetComputeInstances(nvmlGpuInstance_t gpuInstance, unsigned int profileId, + nvmlComputeInstance_t *computeInstances, unsigned int *count); + +/** + * Get compute instance for given instance ID. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * Requires privileged user. + * + * @param gpuInstance The identifier of the target GPU instance + * @param id The compute instance ID + * @param computeInstance Returns compute instance + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a device, \a ID or \a computeInstance are invalid + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't have MIG mode enabled + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + * - \ref NVML_ERROR_NOT_FOUND If the compute instance is not found. + */ +nvmlReturn_t DECLDIR nvmlGpuInstanceGetComputeInstanceById(nvmlGpuInstance_t gpuInstance, unsigned int id, + nvmlComputeInstance_t *computeInstance); + +/** + * Get compute instance information. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param computeInstance The compute instance handle + * @param info Return compute instance information + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_UNINITIALIZED If library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT If \a computeInstance or \a info are invalid + * - \ref NVML_ERROR_NO_PERMISSION If user doesn't have permission to perform the operation + */ +nvmlReturn_t DECLDIR nvmlComputeInstanceGetInfo_v2(nvmlComputeInstance_t computeInstance, nvmlComputeInstanceInfo_t *info); + +/** + * Test if the given handle refers to a MIG device. + * + * A MIG device handle is an NVML abstraction which maps to a MIG compute instance. + * These overloaded references can be used (with some restrictions) interchangeably + * with a GPU device handle to execute queries at a per-compute instance granularity. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device NVML handle to test + * @param isMigDevice True when handle refers to a MIG device + * + * @return + * - \ref NVML_SUCCESS if \a device status was successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device handle or \a isMigDevice reference is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if this check is not supported by the device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceIsMigDeviceHandle(nvmlDevice_t device, unsigned int *isMigDevice); + +/** + * Get GPU instance ID for the given MIG device handle. + * + * GPU instance IDs are unique per device and remain valid until the GPU instance is destroyed. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device Target MIG device handle + * @param id GPU instance ID + * + * @return + * - \ref NVML_SUCCESS if instance ID was successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device or \a id reference is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGpuInstanceId(nvmlDevice_t device, unsigned int *id); + +/** + * Get compute instance ID for the given MIG device handle. + * + * Compute instance IDs are unique per GPU instance and remain valid until the compute instance + * is destroyed. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device Target MIG device handle + * @param id Compute instance ID + * + * @return + * - \ref NVML_SUCCESS if instance ID was successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device or \a id reference is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetComputeInstanceId(nvmlDevice_t device, unsigned int *id); + +/** + * Get the maximum number of MIG devices that can exist under a given parent NVML device. + * + * Returns zero if MIG is not supported or enabled. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device Target device handle + * @param count Count of MIG devices + * + * @return + * - \ref NVML_SUCCESS if \a count was successfully retrieved + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device or \a count reference is invalid + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMaxMigDeviceCount(nvmlDevice_t device, unsigned int *count); + +/** + * Get MIG device handle for the given index under its parent NVML device. + * + * If the compute instance is destroyed either explicitly or by destroying, + * resetting or unbinding the parent GPU instance or the GPU device itself + * the MIG device handle would remain invalid and must be requested again + * using this API. Handles may be reused and their properties can change in + * the process. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param device Reference to the parent GPU device handle + * @param index Index of the MIG device + * @param migDevice Reference to the MIG device handle + * + * @return + * - \ref NVML_SUCCESS if \a migDevice handle was successfully created + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a index or \a migDevice reference is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_NOT_FOUND if no valid MIG device was found at \a index + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMigDeviceHandleByIndex(nvmlDevice_t device, unsigned int index, + nvmlDevice_t *migDevice); + +/** + * Get parent device handle from a MIG device handle. + * + * For Ampere &tm; or newer fully supported devices. + * Supported on Linux only. + * + * @param migDevice MIG device handle + * @param device Device handle + * + * @return + * - \ref NVML_SUCCESS if \a device handle was successfully created + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a migDevice or \a device is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetDeviceHandleFromMigDeviceHandle(nvmlDevice_t migDevice, nvmlDevice_t *device); + +/** + * Get the type of the GPU Bus (PCIe, PCI, ...) + * + * @param device The identifier of the target device + * @param type The PCI Bus type + * + * return + * - \ref NVML_SUCCESS if the bus \a type is successfully retreived + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \device is invalid or \type is NULL + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetBusType(nvmlDevice_t device, nvmlBusType_t *type); + +/** + * Retrieve performance monitor samples from the associated subdevice. + * + * @param device + * @param pDynamicPstatesInfo + * + * @return + * - \ref NVML_SUCCESS if \a pDynamicPstatesInfo has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a pDynamicPstatesInfo is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetDynamicPstatesInfo(nvmlDevice_t device, nvmlGpuDynamicPstatesInfo_t *pDynamicPstatesInfo); + +/** + * Sets the speed of a specified fan. + * + * WARNING: This function changes the fan control policy to manual. It means that YOU have to monitor + * the temperature and adjust the fan speed accordingly. + * If you set the fan speed too low you can burn your GPU! + * Use nvmlDeviceSetDefaultFanSpeed_v2 to restore default control policy. + * + * For all cuda-capable discrete products with fans that are Maxwell or Newer. + * + * device The identifier of the target device + * fan The index of the fan, starting at zero + * speed The target speed of the fan [0-100] in % of max speed + * + * return + * NVML_SUCCESS if the fan speed has been set + * NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * NVML_ERROR_INVALID_ARGUMENT if the device is not valid, or the speed is outside acceptable ranges, + * or if the fan index doesn't reference an actual fan. + * NVML_ERROR_NOT_SUPPORTED if the device is older than Maxwell. + * NVML_ERROR_UNKNOWN if there was an unexpected error. + */ +nvmlReturn_t DECLDIR nvmlDeviceSetFanSpeed_v2(nvmlDevice_t device, unsigned int fan, unsigned int speed); + +/** + * Retrieve the GPCCLK VF offset value + * @param[in] device The identifier of the target device + * @param[out] offset The retrieved GPCCLK VF offset value + * + * @return + * - \ref NVML_SUCCESS if \a offset has been successfully queried + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a offset is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGpcClkVfOffset(nvmlDevice_t device, int *offset); + +/** + * Set the GPCCLK VF offset value + * @param[in] device The identifier of the target device + * @param[in] offset The GPCCLK VF offset value to set + * + * @return + * - \ref NVML_SUCCESS if \a offset has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a offset is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceSetGpcClkVfOffset(nvmlDevice_t device, int offset); + +/** + * Retrieve the MemClk (Memory Clock) VF offset value. + * @param[in] device The identifier of the target device + * @param[out] offset The retrieved MemClk VF offset value + * + * @return + * - \ref NVML_SUCCESS if \a offset has been successfully queried + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a offset is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMemClkVfOffset(nvmlDevice_t device, int *offset); + +/** + * Set the MemClk (Memory Clock) VF offset value. It requires elevated privileges. + * @param[in] device The identifier of the target device + * @param[in] offset The MemClk VF offset value to set + * + * @return + * - \ref NVML_SUCCESS if \a offset has been set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a offset is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_GPU_IS_LOST if the target GPU has fallen off the bus or is otherwise inaccessible + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceSetMemClkVfOffset(nvmlDevice_t device, int offset); + +/** + * Retrieve min and max clocks of some clock domain for a given PState + * + * @param device The identifier of the target device + * @param type Clock domain + * @param pstate PState to query + * @param minClockMHz Reference in which to return min clock frequency + * @param maxClockMHz Reference in which to return max clock frequency + * + * @return + * - \ref NVML_SUCCESS if everything worked + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device, \a type or \a pstate are invalid or both + * \a minClockMHz and \a maxClockMHz are NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMinMaxClockOfPState(nvmlDevice_t device, nvmlClockType_t type, nvmlPstates_t pstate, + unsigned int * minClockMHz, unsigned int * maxClockMHz); + +/** + * Get all supported Performance States (P-States) for the device. + * + * The returned array would contain a contiguous list of valid P-States supported by + * the device. If the number of supported P-States is fewer than the size of the array + * supplied missing elements would contain \a NVML_PSTATE_UNKNOWN. + * + * The number of elements in the returned list will never exceed \a NVML_MAX_GPU_PERF_PSTATES. + * + * @param device The identifier of the target device + * @param pstates Container to return the list of performance states + * supported by device + * @param size Size of the supplied \a pstates array in bytes + * + * @return + * - \ref NVML_SUCCESS if \a pstates array has been retrieved + * - \ref NVML_ERROR_INSUFFICIENT_SIZE if the the container supplied was not large enough to + * hold the resulting list + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device or \a pstates is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support performance state readings + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetSupportedPerformanceStates(nvmlDevice_t device, + nvmlPstates_t *pstates, unsigned int size); + +/** + * Retrieve the GPCCLK min max VF offset value. + * @param[in] device The identifier of the target device + * @param[out] minOffset The retrieved GPCCLK VF min offset value + * @param[out] maxOffset The retrieved GPCCLK VF max offset value + * + * @return + * - \ref NVML_SUCCESS if \a offset has been successfully queried + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a offset is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGpcClkMinMaxVfOffset(nvmlDevice_t device, + int *minOffset, int *maxOffset); + +/** + * Retrieve the MemClk (Memory Clock) min max VF offset value. + * @param[in] device The identifier of the target device + * @param[out] minOffset The retrieved MemClk VF min offset value + * @param[out] maxOffset The retrieved MemClk VF max offset value + * + * @return + * - \ref NVML_SUCCESS if \a offset has been successfully queried + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a offset is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if the device does not support this feature + * - \ref NVML_ERROR_UNKNOWN on any unexpected error + */ +nvmlReturn_t DECLDIR nvmlDeviceGetMemClkMinMaxVfOffset(nvmlDevice_t device, + int *minOffset, int *maxOffset); + +/** + * Get fabric information associated with the device. + * + * %HOPPER_OR_NEWER% + * + * On Hopper + NVSwitch systems, GPU is registered with the NVIDIA Fabric Manager + * Upon successful registration, the GPU is added to the NVLink fabric to enable + * peer-to-peer communication. + * This API reports the current state of the GPU in the NVLink fabric + * along with other useful information. + * + * @param device The identifier of the target device + * @param gpuFabricInfo Information about GPU fabric state + * + * @return + * - \ref NVML_SUCCESS Upon success + * - \ref NVML_ERROR_NOT_SUPPORTED If \a device doesn't support gpu fabric + */ +nvmlReturn_t DECLDIR nvmlDeviceGetGpuFabricInfo(nvmlDevice_t device, nvmlGpuFabricInfo_t *gpuFabricInfo); + +/** @} */ + +/***************************************************************************************************/ +/** @defgroup GPM NVML GPM + * @{ + */ +/***************************************************************************************************/ +/** @defgroup nvmlGpmEnums GPM Enums + * @{ + */ +/***************************************************************************************************/ + +/* GPM Metric Identifiers */ +typedef enum +{ + NVML_GPM_METRIC_GRAPHICS_UTIL = 1, /* Percentage of time any compute/graphics app was active on the GPU. 0.0 - 100.0 */ + NVML_GPM_METRIC_SM_UTIL = 2, /* Percentage of SMs that were busy. 0.0 - 100.0 */ + NVML_GPM_METRIC_SM_OCCUPANCY = 3, /* Percentage of warps that were active vs theoretical maximum. 0.0 - 100.0 */ + NVML_GPM_METRIC_INTEGER_UTIL = 4, /* Percentage of time the GPU's SMs were doing integer operations. 0.0 - 100.0 */ + NVML_GPM_METRIC_ANY_TENSOR_UTIL = 5, /* Percentage of time the GPU's SMs were doing ANY tensor operations. 0.0 - 100.0 */ + NVML_GPM_METRIC_DFMA_TENSOR_UTIL = 6, /* Percentage of time the GPU's SMs were doing DFMA tensor operations. 0.0 - 100.0 */ + NVML_GPM_METRIC_HMMA_TENSOR_UTIL = 7, /* Percentage of time the GPU's SMs were doing HMMA tensor operations. 0.0 - 100.0 */ + NVML_GPM_METRIC_IMMA_TENSOR_UTIL = 9, /* Percentage of time the GPU's SMs were doing IMMA tensor operations. 0.0 - 100.0 */ + NVML_GPM_METRIC_DRAM_BW_UTIL = 10, /* Percentage of DRAM bw used vs theoretical maximum. 0.0 - 100.0 */ + NVML_GPM_METRIC_FP64_UTIL = 11, /* Percentage of time the GPU's SMs were doing non-tensor FP64 math. 0.0 - 100.0 */ + NVML_GPM_METRIC_FP32_UTIL = 12, /* Percentage of time the GPU's SMs were doing non-tensor FP32 math. 0.0 - 100.0 */ + NVML_GPM_METRIC_FP16_UTIL = 13, /* Percentage of time the GPU's SMs were doing non-tensor FP16 math. 0.0 - 100.0 */ + NVML_GPM_METRIC_PCIE_TX_PER_SEC = 20, /* PCIe traffic from this GPU in MiB/sec */ + NVML_GPM_METRIC_PCIE_RX_PER_SEC = 21, /* PCIe traffic to this GPU in MiB/sec */ + NVML_GPM_METRIC_NVDEC_0_UTIL = 30, /* Percent utilization of NVDEC 0. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVDEC_1_UTIL = 31, /* Percent utilization of NVDEC 1. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVDEC_2_UTIL = 32, /* Percent utilization of NVDEC 2. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVDEC_3_UTIL = 33, /* Percent utilization of NVDEC 3. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVDEC_4_UTIL = 34, /* Percent utilization of NVDEC 4. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVDEC_5_UTIL = 35, /* Percent utilization of NVDEC 5. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVDEC_6_UTIL = 36, /* Percent utilization of NVDEC 6. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVDEC_7_UTIL = 37, /* Percent utilization of NVDEC 7. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVJPG_0_UTIL = 40, /* Percent utilization of NVJPG 0. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVJPG_1_UTIL = 41, /* Percent utilization of NVJPG 1. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVJPG_2_UTIL = 42, /* Percent utilization of NVJPG 2. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVJPG_3_UTIL = 43, /* Percent utilization of NVJPG 3. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVJPG_4_UTIL = 44, /* Percent utilization of NVJPG 4. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVJPG_5_UTIL = 45, /* Percent utilization of NVJPG 5. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVJPG_6_UTIL = 46, /* Percent utilization of NVJPG 6. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVJPG_7_UTIL = 47, /* Percent utilization of NVJPG 7. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVOFA_0_UTIL = 50, /* Percent utilization of NVOFA 0. 0.0 - 100.0 */ + NVML_GPM_METRIC_NVLINK_TOTAL_RX_PER_SEC = 60, /* NvLink read bandwidth for all links in MiB/sec */ + NVML_GPM_METRIC_NVLINK_TOTAL_TX_PER_SEC = 61, /* NvLink write bandwidth for all links in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L0_RX_PER_SEC = 62, /* NvLink read bandwidth for link 0 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L0_TX_PER_SEC = 63, /* NvLink write bandwidth for link 0 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L1_RX_PER_SEC = 64, /* NvLink read bandwidth for link 1 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L1_TX_PER_SEC = 65, /* NvLink write bandwidth for link 1 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L2_RX_PER_SEC = 66, /* NvLink read bandwidth for link 2 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L2_TX_PER_SEC = 67, /* NvLink write bandwidth for link 2 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L3_RX_PER_SEC = 68, /* NvLink read bandwidth for link 3 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L3_TX_PER_SEC = 69, /* NvLink write bandwidth for link 3 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L4_RX_PER_SEC = 70, /* NvLink read bandwidth for link 4 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L4_TX_PER_SEC = 71, /* NvLink write bandwidth for link 4 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L5_RX_PER_SEC = 72, /* NvLink read bandwidth for link 5 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L5_TX_PER_SEC = 73, /* NvLink write bandwidth for link 5 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L6_RX_PER_SEC = 74, /* NvLink read bandwidth for link 6 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L6_TX_PER_SEC = 75, /* NvLink write bandwidth for link 6 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L7_RX_PER_SEC = 76, /* NvLink read bandwidth for link 7 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L7_TX_PER_SEC = 77, /* NvLink write bandwidth for link 7 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L8_RX_PER_SEC = 78, /* NvLink read bandwidth for link 8 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L8_TX_PER_SEC = 79, /* NvLink write bandwidth for link 8 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L9_RX_PER_SEC = 80, /* NvLink read bandwidth for link 9 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L9_TX_PER_SEC = 81, /* NvLink write bandwidth for link 9 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L10_RX_PER_SEC = 82, /* NvLink read bandwidth for link 10 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L10_TX_PER_SEC = 83, /* NvLink write bandwidth for link 10 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L11_RX_PER_SEC = 84, /* NvLink read bandwidth for link 11 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L11_TX_PER_SEC = 85, /* NvLink write bandwidth for link 11 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L12_RX_PER_SEC = 86, /* NvLink read bandwidth for link 12 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L12_TX_PER_SEC = 87, /* NvLink write bandwidth for link 12 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L13_RX_PER_SEC = 88, /* NvLink read bandwidth for link 13 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L13_TX_PER_SEC = 89, /* NvLink write bandwidth for link 13 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L14_RX_PER_SEC = 90, /* NvLink read bandwidth for link 14 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L14_TX_PER_SEC = 91, /* NvLink write bandwidth for link 14 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L15_RX_PER_SEC = 92, /* NvLink read bandwidth for link 15 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L15_TX_PER_SEC = 93, /* NvLink write bandwidth for link 15 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L16_RX_PER_SEC = 94, /* NvLink read bandwidth for link 16 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L16_TX_PER_SEC = 95, /* NvLink write bandwidth for link 16 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L17_RX_PER_SEC = 96, /* NvLink read bandwidth for link 17 in MiB/sec */ + NVML_GPM_METRIC_NVLINK_L17_TX_PER_SEC = 97, /* NvLink write bandwidth for link 17 in MiB/sec */ + NVML_GPM_METRIC_MAX = 98, /* Maximum value above +1. Note that changing this + should also change NVML_GPM_METRICS_GET_VERSION + due to struct size change */ +} nvmlGpmMetricId_t; + +/** @} */ // @defgroup nvmlGpmEnums + + +/***************************************************************************************************/ +/** @defgroup nvmlGpmStructs GPM Structs + * @{ + */ +/***************************************************************************************************/ + +/* Handle to an allocated GPM sample allocated with nvmlGpmSampleAlloc() + Free this with nvmlGpmSampleFree() */ +typedef struct nvmlGpmSample_st* nvmlGpmSample_t; + +typedef struct +{ + unsigned int metricId; /* IN: NVML_GPM_METRIC_? #define of which metric to retrieve */ + nvmlReturn_t nvmlReturn; /* OUT: Status of this metric. If this is nonzero, then value is not valid */ + double value; /* OUT: Value of this metric. Is only valid if nvmlReturn is 0 (NVML_SUCCESS) */ + struct + { + char *shortName; + char *longName; + char *unit; + } metricInfo; /* OUT: Metric name and unit. Those can be NULL if not defined */ +} nvmlGpmMetric_t; + +typedef struct +{ + unsigned int version; /* IN: Set to NVML_GPM_METRICS_GET_VERSION */ + unsigned int numMetrics; /* IN: How many metrics to retrieve in metrics[] */ + nvmlGpmSample_t sample1; /* IN: Sample buffer */ + nvmlGpmSample_t sample2; /* IN: Sample buffer */ + nvmlGpmMetric_t metrics[NVML_GPM_METRIC_MAX]; /* IN/OUT: Array of metrics. Set metricId on call. + see nvmlReturn and value on return */ +} nvmlGpmMetricsGet_t; + +#define NVML_GPM_METRICS_GET_VERSION 1 + +typedef struct +{ + unsigned int version; /* IN: Set to NVML_GPM_SUPPORT_VERSION */ + unsigned int isSupportedDevice; /* OUT: Indicates device support */ +} nvmlGpmSupport_t; + +#define NVML_GPM_SUPPORT_VERSION 1 + +/** @} */ // @defgroup nvmlGPMStructs + +/***************************************************************************************************/ +/** @defgroup nvmlGpmFunctions GPM Functions + * @{ + */ +/***************************************************************************************************/ + +/** + * Calculate GPM metrics from two samples. + * + * + * @param metricsGet IN/OUT: populated nvmlGpmMetricsGet_t struct + * + * %HOPPER_OR_NEWER% + * + * @return + * - \ref NVML_SUCCESS on success + * - Nonzero NVML_ERROR_? enum on error + */ +nvmlReturn_t DECLDIR nvmlGpmMetricsGet(nvmlGpmMetricsGet_t *metricsGet); + + +/** + * Free an allocated sample buffer that was allocated with \ref nvmlGpmSampleAlloc() + * + * %HOPPER_OR_NEWER% + * + * @param gpmSample Sample to free + * + * @return + * - \ref NVML_SUCCESS on success + * - \ref NVML_ERROR_INVALID_ARGUMENT if an invalid pointer is provided + */ +nvmlReturn_t DECLDIR nvmlGpmSampleFree(nvmlGpmSample_t gpmSample); + + +/** + * Allocate a sample buffer to be used with NVML GPM . You will need to allocate + * at least two of these buffers to use with the NVML GPM feature + * + * %HOPPER_OR_NEWER% + * + * @param gpmSample Where the allocated sample will be stored + * + * @return + * - \ref NVML_SUCCESS on success + * - \ref NVML_ERROR_INVALID_ARGUMENT if an invalid pointer is provided + * - \ref NVML_ERROR_MEMORY if system memory is insufficient + */ +nvmlReturn_t DECLDIR nvmlGpmSampleAlloc(nvmlGpmSample_t *gpmSample); + +/** + * Read a sample of GPM metrics into the provided \a gpmSample buffer. After + * two samples are gathered, you can call nvmlGpmMetricGet on those samples to + * retrive metrics + * + * %HOPPER_OR_NEWER% + * + * @param device Device to get samples for + * @param gpmSample Buffer to read samples into + * + * @return + * - \ref NVML_SUCCESS on success + * - Nonzero NVML_ERROR_? enum on error + */ +nvmlReturn_t DECLDIR nvmlGpmSampleGet(nvmlDevice_t device, nvmlGpmSample_t gpmSample); + +/** + * Read a sample of GPM metrics into the provided \a gpmSample buffer for a MIG GPU Instance. + * + * After two samples are gathered, you can call nvmlGpmMetricGet on those + * samples to retrive metrics + * + * %HOPPER_OR_NEWER% + * + * @param device Device to get samples for + * @param gpuInstanceId MIG GPU Instance ID + * @param gpmSample Buffer to read samples into + * + * @return + * - \ref NVML_SUCCESS on success + * - Nonzero NVML_ERROR_? enum on error + */ +nvmlReturn_t DECLDIR nvmlGpmMigSampleGet(nvmlDevice_t device, unsigned int gpuInstanceId, nvmlGpmSample_t gpmSample); + +/** + * Indicate whether the supplied device supports GPM + * + * @param device NVML device to query for + * @param gpmSupport Structure to indicate GPM support. Indicates + * GPM support per system for the supplied device + * + * @return + * - NVML_SUCCESS on success + * - Nonzero NVML_ERROR_? enum if there is an error in processing the query + */ +nvmlReturn_t DECLDIR nvmlGpmQueryDeviceSupport(nvmlDevice_t device, nvmlGpmSupport_t *gpmSupport); + +/** @} */ // @defgroup nvmlGpmFunctions +/** @} */ // @defgroup GPM + +/***************************************************************************************************/ +/** @defgroup nvmlDevice definitions related to Counter Collection Unit + * @{ + */ +/***************************************************************************************************/ + +/* CCU Stream State */ +#define NVML_COUNTER_COLLECTION_UNIT_STREAM_STATE_DISABLE 0 +#define NVML_COUNTER_COLLECTION_UNIT_STREAM_STATE_ENABLE 1 + +/** + * Get counter collection unit stream state. + * + * %HOPPER_OR_NEWER% + * Supported on Linux, Windows TCC. + * + * @param device The identifier of the target device + * @param state Returns counter collection unit stream state + * NVML_COUNTER_COLLECTION_UNIT_STREAM_STATE_DISABLE or + * NVML_COUNTER_COLLECTION_UNIT_STREAM_STATE_ENABLE + * + * @return + * - \ref NVML_SUCCESS if \a current counter collection unit stream state were successfully queried + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a state is NULL + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + */ +nvmlReturn_t DECLDIR nvmlDeviceCcuGetStreamState(nvmlDevice_t device, unsigned int *state); + +/** + * Set counter collection unit stream state. + * + * %HOPPER_OR_NEWER% + * Supported on Linux, Windows TCC. + * + * @param device The identifier of the target device + * @param state Counter collection unit stream state, + * NVML_COUNTER_COLLECTION_UNIT_STREAM_STATE_DISABLE or + * NVML_COUNTER_COLLECTION_UNIT_STREAM_STATE_ENABLE + * + * @return + * - \ref NVML_SUCCESS if \a current counter collection unit stream state is successfully set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + */ +nvmlReturn_t DECLDIR nvmlDeviceCcuSetStreamState(nvmlDevice_t device, unsigned int state); + +/** @} */ // @defgroup CCU + +#define NVML_NVLINK_POWER_STATE_HIGH_SPEED 0x0 +#define NVML_NVLINK_POWER_STATE_LOW 0x1 + +#define NVML_NVLINK_LOW_POWER_THRESHOLD_MIN 0x1 +#define NVML_NVLINK_LOW_POWER_THRESHOLD_MAX 0x1FFF +#define NVML_NVLINK_LOW_POWER_THRESHOLD_RESET 0xFFFFFFFF + +/* Structure containing Low Power parameters */ +typedef struct nvmlNvLinkPowerThres_st +{ + unsigned int lowPwrThreshold; //!< Low power threshold (in units of 100us) +} nvmlNvLinkPowerThres_t; + +/** + * Set NvLink Low Power Threshold for device. + * + * %HOPPER_OR_NEWER% + * + * @param device The identifier of the target device + * @param info Reference to \a nvmlNvLinkPowerThres_t struct + * input parameters + * + * @return + * - \ref NVML_SUCCESS if the \a Threshold is successfully set + * - \ref NVML_ERROR_UNINITIALIZED if the library has not been successfully initialized + * - \ref NVML_ERROR_INVALID_ARGUMENT if \a device is invalid or \a Threshold is not within range + * - \ref NVML_ERROR_NOT_SUPPORTED if this query is not supported by the device + * + **/ +nvmlReturn_t DECLDIR nvmlDeviceSetNvLinkDeviceLowPowerThreshold(nvmlDevice_t device, nvmlNvLinkPowerThres_t *info); + +/** + * NVML API versioning support + */ + +#ifdef NVML_NO_UNVERSIONED_FUNC_DEFS +nvmlReturn_t DECLDIR nvmlInit(void); +nvmlReturn_t DECLDIR nvmlDeviceGetCount(unsigned int *deviceCount); +nvmlReturn_t DECLDIR nvmlDeviceGetHandleByIndex(unsigned int index, nvmlDevice_t *device); +nvmlReturn_t DECLDIR nvmlDeviceGetHandleByPciBusId(const char *pciBusId, nvmlDevice_t *device); +nvmlReturn_t DECLDIR nvmlDeviceGetPciInfo(nvmlDevice_t device, nvmlPciInfo_t *pci); +nvmlReturn_t DECLDIR nvmlDeviceGetPciInfo_v2(nvmlDevice_t device, nvmlPciInfo_t *pci); +nvmlReturn_t DECLDIR nvmlDeviceGetNvLinkRemotePciInfo(nvmlDevice_t device, unsigned int link, nvmlPciInfo_t *pci); +nvmlReturn_t DECLDIR nvmlDeviceGetGridLicensableFeatures(nvmlDevice_t device, nvmlGridLicensableFeatures_t *pGridLicensableFeatures); +nvmlReturn_t DECLDIR nvmlDeviceGetGridLicensableFeatures_v2(nvmlDevice_t device, nvmlGridLicensableFeatures_t *pGridLicensableFeatures); +nvmlReturn_t DECLDIR nvmlDeviceGetGridLicensableFeatures_v3(nvmlDevice_t device, nvmlGridLicensableFeatures_t *pGridLicensableFeatures); +nvmlReturn_t DECLDIR nvmlDeviceRemoveGpu(nvmlPciInfo_t *pciInfo); +nvmlReturn_t DECLDIR nvmlEventSetWait(nvmlEventSet_t set, nvmlEventData_t * data, unsigned int timeoutms); +nvmlReturn_t DECLDIR nvmlDeviceGetAttributes(nvmlDevice_t device, nvmlDeviceAttributes_t *attributes); +nvmlReturn_t DECLDIR nvmlComputeInstanceGetInfo(nvmlComputeInstance_t computeInstance, nvmlComputeInstanceInfo_t *info); +nvmlReturn_t DECLDIR nvmlDeviceGetComputeRunningProcesses(nvmlDevice_t device, unsigned int *infoCount, nvmlProcessInfo_v1_t *infos); +nvmlReturn_t DECLDIR nvmlDeviceGetComputeRunningProcesses_v2(nvmlDevice_t device, unsigned int *infoCount, nvmlProcessInfo_v2_t *infos); +nvmlReturn_t DECLDIR nvmlDeviceGetGraphicsRunningProcesses(nvmlDevice_t device, unsigned int *infoCount, nvmlProcessInfo_v1_t *infos); +nvmlReturn_t DECLDIR nvmlDeviceGetGraphicsRunningProcesses_v2(nvmlDevice_t device, unsigned int *infoCount, nvmlProcessInfo_v2_t *infos); +nvmlReturn_t DECLDIR nvmlDeviceGetMPSComputeRunningProcesses(nvmlDevice_t device, unsigned int *infoCount, nvmlProcessInfo_v1_t *infos); +nvmlReturn_t DECLDIR nvmlDeviceGetMPSComputeRunningProcesses_v2(nvmlDevice_t device, unsigned int *infoCount, nvmlProcessInfo_v2_t *infos); +nvmlReturn_t DECLDIR nvmlDeviceGetGpuInstancePossiblePlacements(nvmlDevice_t device, unsigned int profileId, nvmlGpuInstancePlacement_t *placements, unsigned int *count); +nvmlReturn_t DECLDIR nvmlVgpuInstanceGetLicenseInfo(nvmlVgpuInstance_t vgpuInstance, nvmlVgpuLicenseInfo_t *licenseInfo); + +#endif // #ifdef NVML_NO_UNVERSIONED_FUNC_DEFS + +#if defined(NVML_NO_UNVERSIONED_FUNC_DEFS) +// We don't define APIs to run new versions if this guard is present so there is +// no need to undef +#elif defined(__NVML_API_VERSION_INTERNAL) +#undef nvmlDeviceGetGraphicsRunningProcesses +#undef nvmlDeviceGetComputeRunningProcesses +#undef nvmlDeviceGetMPSComputeRunningProcesses +#undef nvmlDeviceGetAttributes +#undef nvmlComputeInstanceGetInfo +#undef nvmlEventSetWait +#undef nvmlDeviceGetGridLicensableFeatures +#undef nvmlDeviceRemoveGpu +#undef nvmlDeviceGetNvLinkRemotePciInfo +#undef nvmlDeviceGetPciInfo +#undef nvmlDeviceGetCount +#undef nvmlDeviceGetHandleByIndex +#undef nvmlDeviceGetHandleByPciBusId +#undef nvmlInit +#undef nvmlBlacklistDeviceInfo_t +#undef nvmlGetBlacklistDeviceCount +#undef nvmlGetBlacklistDeviceInfoByIndex +#undef nvmlDeviceGetGpuInstancePossiblePlacements +#undef nvmlVgpuInstanceGetLicenseInfo + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/userspace/tests/Makefile b/userspace/tests/Makefile new file mode 100644 index 0000000..3be451d --- /dev/null +++ b/userspace/tests/Makefile @@ -0,0 +1,22 @@ +# Userspace Test Makefile + +CC = gcc +CFLAGS = -Wall -Wextra -O2 -std=gnu11 -I../../kernel/include +LDFLAGS = + +TARGET = test_vgpu_userspace +SRC = test_vgpu_userspace.c + +all: $(TARGET) + +$(TARGET): $(SRC) + $(CC) $(CFLAGS) -o $(TARGET) $(SRC) $(LDFLAGS) + +clean: + rm -f $(TARGET) + +test: $(TARGET) + @echo "Running userspace test (requires driver loaded)..." + sudo ./$(TARGET) + +.PHONY: all clean test \ No newline at end of file diff --git a/userspace/tests/test_guest_init.c b/userspace/tests/test_guest_init.c new file mode 100644 index 0000000..135c16f --- /dev/null +++ b/userspace/tests/test_guest_init.c @@ -0,0 +1,176 @@ +/* + * Test for guest vGPU driver initialization + * This test verifies that the guest vGPU driver can initialize properly + * when passed through to a VM via VFIO/mdev + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NV_VGPU_IOCTL_MAGIC 'N' +#define NV_VGPU_IOCTL_GET_INFO \ + _IOWR(NV_VGPU_IOCTL_MAGIC, 0x01, struct nv_vgpu_ioctl_get_info) +#define NV_VGPU_IOCTL_MAP_BAR \ + _IOWR(NV_VGPU_IOCTL_MAGIC, 0x02, struct nv_vgpu_ioctl_map_bar) +#define NV_VGPU_IOCTL_GSP_RPC \ + _IOWR(NV_VGPU_IOCTL_MAGIC, 0x06, struct nv_vgpu_ioctl_gsp_rpc) + +struct nv_vgpu_ioctl_get_info { + uint32_t vgpu_type; + uint32_t vgpu_id; + uint32_t gpu_instance_id; + uint32_t compute_instance_id; + uint32_t state; + uint64_t fb_base; + uint64_t fb_size; + uint64_t bar0_config_base; + uint32_t num_bars; + struct { + uint32_t index; + uint64_t gpa; + uint64_t size; + uint64_t iova; + bool mapped; + bool trapped; + } bars[8]; +}; + +struct nv_vgpu_ioctl_map_bar { + uint32_t bar_index; + uint64_t gpa; + uint64_t size; + uint64_t iova; + uint32_t flags; +}; + +struct nv_vgpu_ioctl_gsp_rpc { + uint32_t type; + uint32_t flags; + uint64_t data_ptr; + uint32_t data_size; + uint32_t result; +}; + +int main(int argc, char *argv[]) +{ + int ret = 0; + int vfio_fd = -1; + int mdev_fd = -1; + char *mdev_path = NULL; + struct nv_vgpu_ioctl_get_info info = {0}; + struct nv_vgpu_ioctl_map_bar map_bar = {0}; + struct vfio_device_info dev_info = {0}; + + printf("Testing guest vGPU driver initialization...\n"); + + if (argc < 2) { + printf("Usage: %s \n", argv[0]); + printf("Example: %s 00000000-0000-0000-0000-000000000000\n", argv[0]); + return 1; + } + + mdev_path = argv[1]; + + vfio_fd = open("/dev/vfio/vfio", O_RDWR); + if (vfio_fd < 0) { + printf("FAIL: Cannot open /dev/vfio/vfio: %s\n", strerror(errno)); + return 1; + } + + dev_info.argsz = sizeof(dev_info); + if (ioctl(vfio_fd, VFIO_GET_API_VERSION, &dev_info) < 0) { + printf("FAIL: VFIO_GET_API_VERSION failed: %s\n", strerror(errno)); + ret = 1; + goto cleanup; + } + + if (dev_info.version != VFIO_API_VERSION) { + printf("FAIL: VFIO API version mismatch\n"); + ret = 1; + goto cleanup; + } + + printf("PASS: VFIO API version %d\n", dev_info.version); + + char mdev_dev_path[256]; + snprintf(mdev_dev_path, sizeof(mdev_dev_path), "/dev/vfio/%s", mdev_path); + + mdev_fd = open(mdev_dev_path, O_RDWR); + if (mdev_fd < 0) { + printf("FAIL: Cannot open mdev device %s: %s\n", mdev_dev_path, strerror(errno)); + ret = 1; + goto cleanup; + } + + printf("PASS: Opened mdev device %s\n", mdev_dev_path); + + dev_info.argsz = sizeof(dev_info); + if (ioctl(mdev_fd, VFIO_DEVICE_GET_INFO, &dev_info) < 0) { + printf("FAIL: VFIO_DEVICE_GET_INFO failed: %s\n", strerror(errno)); + ret = 1; + goto cleanup; + } + + printf("PASS: Device info - flags: 0x%x, num_regions: %d, num_irqs: %d\n", + dev_info.flags, dev_info.num_regions, dev_info.num_irqs); + + if (ioctl(mdev_fd, NV_VGPU_IOCTL_GET_INFO, &info) < 0) { + printf("FAIL: NV_VGPU_IOCTL_GET_INFO failed: %s\n", strerror(errno)); + ret = 1; + goto cleanup; + } + + printf("PASS: vGPU info - type: %d, id: %d, state: %d\n", + info.vgpu_type, info.vgpu_id, info.state); + printf(" fb_base: 0x%lx, fb_size: 0x%lx\n", info.fb_base, info.fb_size); + printf(" bar0_config_base: 0x%lx\n", info.bar0_config_base); + printf(" num_bars: %d\n", info.num_bars); + + for (int i = 0; i < info.num_bars; i++) { + printf(" BAR%d: gpa=0x%lx, size=0x%lx, iova=0x%lx, mapped=%d, trapped=%d\n", + info.bars[i].index, info.bars[i].gpa, info.bars[i].size, + info.bars[i].iova, info.bars[i].mapped, info.bars[i].trapped); + } + + if (info.num_bars > 0) { + map_bar.bar_index = 0; + map_bar.gpa = info.bars[0].gpa; + map_bar.size = info.bars[0].size; + map_bar.flags = 0x1; + + if (ioctl(mdev_fd, NV_VGPU_IOCTL_MAP_BAR, &map_bar) < 0) { + printf("FAIL: NV_VGPU_IOCTL_MAP_BAR failed: %s\n", strerror(errno)); + ret = 1; + goto cleanup; + } + + printf("PASS: Mapped BAR0 at IOVA 0x%lx\n", map_bar.iova); + } + + struct nv_vgpu_ioctl_gsp_rpc rpc = {0}; + rpc.type = 0x01; + rpc.data_size = 0; + + if (ioctl(mdev_fd, NV_VGPU_IOCTL_GSP_RPC, &rpc) < 0) { + printf("WARN: NV_VGPU_IOCTL_GSP_RPC failed: %s (may not be implemented yet)\n", strerror(errno)); + } else { + printf("PASS: GSP RPC test completed\n"); + } + + printf("\nAll guest initialization tests PASSED\n"); + +cleanup: + if (mdev_fd >= 0) + close(mdev_fd); + if (vfio_fd >= 0) + close(vfio_fd); + + return ret; +} \ No newline at end of file diff --git a/userspace/tests/test_host_init.c b/userspace/tests/test_host_init.c new file mode 100644 index 0000000..a08fe33 --- /dev/null +++ b/userspace/tests/test_host_init.c @@ -0,0 +1,68 @@ +/* + * Test for host vGPU initialization + */ +#include +#include +#include +#include +#include + +#include +#include + +int main(int argc, char *argv[]) +{ + int ret = 0; + enum SupportedGpus selected_gpu = Nvidia; + const struct ManagerAPI *api = MANAGER_APIS[selected_gpu]; + struct NvManager *mgr = NULL; + + printf("Testing host vGPU initialization...\n"); + + mgr = calloc(1, sizeof(struct NvManager)); + if (!mgr) { + printf("Failed to allocate manager\n"); + return 1; + } + + mgr->ignore_version_check = 1; + mgr->create_signature = nvidia_open_create_signature; + mgr->use_vmiop = 1; + mgr->vmiop_plugin = "/usr/lib/x86_64-linux-gnu/libnvidia-vgpu.so"; + + if (api->init(mgr)) { + printf("FAIL: Manager initialization failed\n"); + ret = 1; + goto cleanup; + } + + printf("PASS: Manager initialized successfully\n"); + + if (!api->running(mgr)) { + printf("FAIL: Manager not running\n"); + ret = 1; + goto cleanup; + } + + printf("PASS: Manager is running\n"); + + if (mgr->vmiop) { + printf("PASS: VMIOP initialized\n"); + } else { + printf("FAIL: VMIOP not initialized\n"); + ret = 1; + } + +cleanup: + if (mgr) { + api->stop(mgr); + free(mgr); + } + + if (ret == 0) + printf("\nAll host initialization tests PASSED\n"); + else + printf("\nSome host initialization tests FAILED\n"); + + return ret; +} \ No newline at end of file diff --git a/userspace/tests/test_vgpu_userspace.c b/userspace/tests/test_vgpu_userspace.c new file mode 100644 index 0000000..cd22111 --- /dev/null +++ b/userspace/tests/test_vgpu_userspace.c @@ -0,0 +1,283 @@ +/* + * GSP vGPU-IO Userspace Test + * Tests VFIO interface and driver functionality from userspace + */ + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GSP_VGPU_DEVICE "/dev/vfio/gsp-vgpu" + +#define TEST_PASS 0 +#define TEST_FAIL 1 + +static int test_count = 0; +static int pass_count = 0; +static int fail_count = 0; + +#define TEST_ASSERT(cond, msg) \ + do { \ + test_count++; \ + if (cond) { \ + pass_count++; \ + printf("PASS: %s\n", msg); \ + } else { \ + fail_count++; \ + fprintf(stderr, "FAIL: %s\n", msg); \ + } \ + } while (0) + +#define TEST_ASSERT_EQ(a, b, msg) \ + TEST_ASSERT((a) == (b), msg " (expected " #b ", got " #a ")") + +/* IOCTL definitions matching kernel driver */ +#define GSP_IOCTL_MAGIC 'G' +#define GSP_IOCTL_CREATE_VF _IOW(GSP_IOCTL_MAGIC, 0x01, struct gsp_vf_config) +#define GSP_IOCTL_DESTROY_VF _IOW(GSP_IOCTL_MAGIC, 0x02, uint32_t) +#define GSP_IOCTL_ALLOC _IOWR(GSP_IOCTL_MAGIC, 0x10, struct gsp_alloc_args) +#define GSP_IOCTL_FREE _IOW(GSP_IOCTL_MAGIC, 0x11, struct gsp_free_args) +#define GSP_IOCTL_MAP _IOWR(GSP_IOCTL_MAGIC, 0x12, struct gsp_map_args) +#define GSP_IOCTL_UNMAP _IOW(GSP_IOCTL_MAGIC, 0x13, struct gsp_unmap_args) +#define GSP_IOCTL_PIN _IOWR(GSP_IOCTL_MAGIC, 0x14, struct gsp_pin_args) +#define GSP_IOCTL_UNPIN _IOW(GSP_IOCTL_MAGIC, 0x15, struct gsp_unpin_args) +#define GSP_IOCTL_BAR_TRAP _IOWR(GSP_IOCTL_MAGIC, 0x16, struct gsp_bar_trap_args) +#define GSP_IOCTL_MIGRATE _IOWR(GSP_IOCTL_MAGIC, 0x17, struct gsp_migrate_args) +#define GSP_IOCTL_WPR_PROTECT _IOWR(GSP_IOCTL_MAGIC, 0x18, struct gsp_wpr_args) +#define GSP_IOCTL_WPR_UNPROTECT _IOW(GSP_IOCTL_MAGIC, 0x19, struct gsp_wpr_args) + +struct gsp_vf_config { + uint32_t id; + uint64_t bar1_offset; + uint64_t bar1_size; + uint64_t pt_base; + uint64_t pt_size; + uint64_t cmd_base; + uint64_t cmd_size; + uint32_t max_memory_mb; + uint32_t num_engines; +}; + +struct gsp_alloc_args { + uint32_t vf_id; + uint64_t size; + uint32_t type; + uint64_t alignment; + uint64_t va_hint; + uint32_t flags; + uint32_t pid; + uint64_t handle; + uint64_t va; + uint64_t actual_size; +}; + +struct gsp_free_args { + uint32_t vf_id; + uint64_t handle; +}; + +struct gsp_map_args { + uint32_t vf_id; + uint64_t handle; + uint64_t gpu_va; + uint64_t size; + uint32_t prot; + uint32_t flags; + uint64_t offset; + uint64_t mapped_va; +}; + +struct gsp_unmap_args { + uint32_t vf_id; + uint64_t handle; + uint64_t gpu_va; + uint64_t size; +}; + +struct gsp_pin_args { + uint32_t vf_id; + uint64_t handle; + uint64_t offset; + uint64_t size; + uint32_t flags; + uint64_t dma_addr; + uint32_t num_pages; +}; + +struct gsp_unpin_args { + uint32_t vf_id; + uint64_t handle; + uint64_t offset; + uint64_t size; +}; + +struct gsp_bar_trap_args { + uint32_t vf_id; + uint32_t bar_index; + uint32_t trap_type; + uint64_t offset; + uint64_t value; + uint32_t size; + uint64_t ret_value; +}; + +struct gsp_migrate_args { + uint32_t vf_id; + uint32_t phase; + uint32_t subcmd; + uint64_t src_vf; + uint64_t dst_vf; + uint64_t data_ptr; + uint64_t data_size; + uint32_t flags; + uint64_t token; +}; + +struct gsp_wpr_args { + uint32_t vf_id; + uint64_t base; + uint64_t size; + uint32_t flags; +}; + +int main(int argc, char *argv[]) +{ + int fd, ret; + uint32_t vf_id = 1; + + printf("========================================\n"); + printf("GSP vGPU-IO Userspace Test Suite\n"); + printf("========================================\n"); + + /* Open device */ + fd = open(GSP_VGPU_DEVICE, O_RDWR); + if (fd < 0) { + fprintf(stderr, "Failed to open %s: %s\n", GSP_VGPU_DEVICE, strerror(errno)); + fprintf(stderr, "Make sure driver is loaded and VFIO device created\n"); + return TEST_FAIL; + } + printf("Opened device: %s (fd=%d)\n", GSP_VGPU_DEVICE, fd); + + /* Test 1: Create VF */ + { + struct gsp_vf_config config = { + .id = vf_id, + .bar1_offset = 0x10000000, + .bar1_size = 0x100000, + .pt_base = 0x20000000, + .pt_size = 0x100000, + .cmd_base = 0x30000000, + .cmd_size = 0x10000, + .max_memory_mb = 1024, + .num_engines = 4, + }; + + ret = ioctl(fd, GSP_IOCTL_CREATE_VF, &config); + TEST_ASSERT(ret == 0, "Create VF"); + if (ret == 0) + printf(" VF %u created successfully\n", vf_id); + } + + /* Test 2: Allocate memory */ + { + struct gsp_alloc_args args = { + .vf_id = vf_id, + .size = 0x10000, // 64KB + .type = 0, // VRAM + .alignment = 0x1000, + .va_hint = 0, + .flags = 0, + .pid = getpid(), + }; + + ret = ioctl(fd, GSP_IOCTL_ALLOC, &args); + TEST_ASSERT(ret == 0, "Allocate memory"); + if (ret == 0) { + printf(" Allocated: handle=0x%" PRIx64 ", va=0x%" PRIx64 ", size=0x%" PRIx64 "\n", + args.handle, args.va, args.actual_size); + } + } + + /* Test 3: Pin memory */ + { + struct gsp_pin_args args = { + .vf_id = vf_id, + .handle = 0, // Would use handle from alloc + .offset = 0, + .size = 0x1000, + .flags = 3, // READ | WRITE + }; + + ret = ioctl(fd, GSP_IOCTL_PIN, &args); + TEST_ASSERT(ret == 0 || errno == ENODEV, "Pin memory (may fail without real allocation)"); + } + + /* Test 4: BAR Trap */ + { + struct gsp_bar_trap_args args = { + .vf_id = vf_id, + .bar_index = 1, + .trap_type = 1, // WRITE + .offset = 0x1000, + .value = 0xDEADBEEF, + .size = 4, + }; + + ret = ioctl(fd, GSP_IOCTL_BAR_TRAP, &args); + TEST_ASSERT(ret == 0 || errno == ENODEV, "BAR trap (may fail without real HW)"); + } + + /* Test 5: WPR Protect */ + { + struct gsp_wpr_args args = { + .vf_id = vf_id, + .base = 0x10000000, + .size = 0x10000, + .flags = 3, // WRITE | READ + }; + + ret = ioctl(fd, GSP_IOCTL_WPR_PROTECT, &args); + TEST_ASSERT(ret == 0 || errno == ENODEV, "WPR protect (may fail without real HW)"); + } + + /* Test 6: Migration */ + { + struct gsp_migrate_args args = { + .vf_id = vf_id, + .phase = 1, // PREPARE + .subcmd = 3, + .src_vf = vf_id, + .dst_vf = 2, + .flags = 1, // LIVE + }; + + ret = ioctl(fd, GSP_IOCTL_MIGRATE, &args); + TEST_ASSERT(ret == 0 || errno == ENODEV, "Migration (may fail without real HW)"); + } + + /* Test 7: Destroy VF */ + { + ret = ioctl(fd, GSP_IOCTL_DESTROY_VF, &vf_id); + TEST_ASSERT(ret == 0, "Destroy VF"); + if (ret == 0) + printf(" VF %u destroyed successfully\n", vf_id); + } + + close(fd); + + printf("========================================\n"); + printf("Userspace Test Results: %d total, %d passed, %d failed\n", + test_count, pass_count, fail_count); + printf("========================================\n"); + + return (fail_count > 0) ? TEST_FAIL : TEST_PASS; +} \ No newline at end of file -- cgit v1.2.3